From 3893e0253d5c7c9b7793fed36d0e22be74c8e724 Mon Sep 17 00:00:00 2001 From: openpowerwtf <52765606+openpowerwtf@users.noreply.ggithub.com> Date: Tue, 5 Jul 2022 11:04:55 -0500 Subject: [PATCH] add dev --- README.md | 15 + dev/.gitignore | 1 + dev/readme.md | 32 + dev/sim/.gitignore | 11 + dev/sim/coco/A2L2.py | 413 + dev/sim/coco/Makefile.icarus | 49 + dev/sim/coco/Makefile.icarus.smt2 | 44 + dev/sim/coco/Makefile.sweetpea | 45 + dev/sim/coco/Makefile.verilator | 30 + dev/sim/coco/OPEnv.py | 117 + dev/sim/coco/boot.lst | 913 ++ dev/sim/coco/build_smt2/cmds.f | 1 + dev/sim/coco/build_sweetpea/cmds.f | 1 + dev/sim/coco/cocotb_icarus.v | 321 + dev/sim/coco/makegtkw | 310 + dev/sim/coco/pyvcd.gtkw | 255 + dev/sim/coco/results.xml | 8 + dev/sim/coco/sim.png | Bin 0 -> 715047 bytes dev/sim/coco/tb.cpp | 250 + dev/sim/coco/tb.py | 307 + dev/sim/coco/verilog | 1 + dev/sim/gtkwave/gtkf-64L.py | 32 + dev/sim/gtkwave/gtkf-64R.py | 32 + dev/sim/gtkwave/gtkf-a2l2.py | 943 ++ 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+ dev/verilog/work/c.v | 5062 +++++++ dev/verilog/work/c_fu_pc.v | 1036 ++ dev/verilog/work/c_perv_rp.v | 704 + dev/verilog/work/c_wrapper.v | 533 + dev/verilog/work/fu.v | 1579 ++ dev/verilog/work/fu_add.v | 705 + dev/verilog/work/fu_add_all1.v | 106 + dev/verilog/work/fu_add_glbc.v | 781 + dev/verilog/work/fu_alg.v | 1078 ++ dev/verilog/work/fu_alg_add.v | 744 + dev/verilog/work/fu_alg_bypmux.v | 120 + dev/verilog/work/fu_alg_or16.v | 171 + dev/verilog/work/fu_alg_sh16.v | 980 ++ dev/verilog/work/fu_alg_sh4.v | 691 + dev/verilog/work/fu_byp.v | 2381 +++ dev/verilog/work/fu_cr2.v | 871 ++ dev/verilog/work/fu_dcd.v | 4671 ++++++ dev/verilog/work/fu_divsqrt.v | 3254 ++++ dev/verilog/work/fu_divsqrt_add4.v | 131 + dev/verilog/work/fu_divsqrt_nq_table.v | 64 + dev/verilog/work/fu_divsqrt_q_table.v | 84 + dev/verilog/work/fu_eie.v | 739 + dev/verilog/work/fu_eov.v | 1134 ++ dev/verilog/work/fu_fmt.v | 1469 ++ dev/verilog/work/fu_fpr.v | 1693 +++ dev/verilog/work/fu_gst.v | 1382 ++ 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create mode 100755 dev/verilog/work/xu_spr_cspr.v create mode 100755 dev/verilog/work/xu_spr_tspr.v diff --git a/README.md b/README.md index 32d3c72..7ba65ed 100644 --- a/README.md +++ b/README.md @@ -1,5 +1,20 @@ # A2O +# Current Status + +* for now, /rel is the original and /dev has updates: + + * compiles with verilator, iverilog, yosys + * runs original simple boot code up to test invocation with cocotb (A2L2 interface partially implemented in Python) + +## To Do + + * continue with cocotb testing + * add A2Node bridge to WB, and Litex wrapper + * experiment with parameters to create smaller version(s) for dOpenLane + +# Original Release + ## The Project This is the release of the A2O POWER processor core RTL and associated FPGA implementation (using ADM-PCIE-9V3 FPGA). diff --git a/dev/.gitignore b/dev/.gitignore new file mode 100755 index 0000000..a136337 --- /dev/null +++ b/dev/.gitignore @@ -0,0 +1 @@ +*.pdf diff --git a/dev/readme.md b/dev/readme.md new file mode 100755 index 0000000..109b9e0 --- /dev/null +++ b/dev/readme.md @@ -0,0 +1,32 @@ +# Testing RTL with new environments + +## + +* RTL + + * updated source to remove a bunch of Verilator warnings + * updated source for compatibility with Icaraus -g2012 + * changed the GPR/FPR macro to remove need for clk4x on FPGA; was ugly and not working with either simulator + +* Verilator + + * can IFETCH some ops in ST and SMT2 mode + * can't get cocotb to build with Verilator (very long compile times) + +* Icarus (w/cocotb) + + * executing boot code until test call with python A2L2 interface + +* Yosys + + * finishes compile + + +## Next To Do + +* create A2L2 cpp model that can be used by Verilator and cocotb (Cython wrapper) +* create simple A2L2-WB RTL for easily connecting to Litex, etc. +* create Litex core wrapper +* OpenLane experiments with blackbox arrays and yosys/abc/sta +* create FPGA version of GPR/FPR (4R4W) using (4)4R1W banks and valid table +* parse vcd/fst and serve browser code for custom trace screens (handle spec/arch mapped facilities, arrays, etc.) diff --git a/dev/sim/.gitignore b/dev/sim/.gitignore new file mode 100755 index 0000000..6f288cf --- /dev/null +++ b/dev/sim/.gitignore @@ -0,0 +1,11 @@ +# verilator +**/obj_dir*/ +# cooc/icarus +coco_icarus +**/sim_build*/ +# gtkwave +*.vcd +*.fst +# python +**/__pycache__/ +*.py[cod] diff --git a/dev/sim/coco/A2L2.py b/dev/sim/coco/A2L2.py new file mode 100755 index 0000000..7e77c57 --- /dev/null +++ b/dev/sim/coco/A2L2.py @@ -0,0 +1,413 @@ +# A2L2 Interface + +import cocotb +from cocotb.triggers import Timer, RisingEdge +from cocotb.binary import BinaryValue +from cocotb.handle import Force +from cocotb.handle import Release + +from dotmap import DotMap +import itertools + +# ------------------------------------------------------------------------------------------------ +# Classes + +''' +Data return timings from spec: + +* Reload Data Coming +Indicates that reload data is coming in three cycles. This signal is required for L2 designs that return data in consecutive cycles, but can be +tied to a logic ‘0’ for designs that return data in every other cycle. For L2 designs that return data in consecutive cycles, this signal should be +asserted three cycles ahead of the first of two paired data beats. If more than two data beats will be presented consecutively, this signal should be +asserted once for the first set of two (paired) data beats and once for the second set of two (paired) data beats. Each assertion +should be three cycles ahead of the first beat of the paired set of data beats. This signal allows the A2 core to insert an issue bubble for the second +reload data beat to avoid flushing the processor pipe. This signal is not required to be asserted as described above for DITC return data. +For non-cacheable (I=1) reloads of one or two beats, this signal should be asserted three cycles ahead of the first (and possibly only) data beat transfer. + +* Reload Data Valid +Indicates that reload data is coming in two cycles. This signal qualifies the other reload interface signals sent in this cycle: reld_ditc, reld_core_tag, reld_crit_qw, and reld_qw. +If reld_data_vld is not active, then the qualified signals should be ignored. + +* Reload Direct Inter-Thread Communication +Indicates that the reload data is associated with a DITC transfer instead of a standard load-ttype reload. This signal is qualified by reld_data_vld and determines the +interpretation of the reld_core_tag bus. DITC reload data transfers are always 64-Byte transfers that follow the same consecutive cycle or every-other-cycle behavior +as standard load-ttype reloads for the attached L2. + +**i believe this means ditc can use either 1of2/2of2 or 1of2/-/-/2of2 pattern, but never requires data_coming (probs because pipe considerations not important for ditc)** + +====== +Cycles: + +* d-3 (reld_data_coming) +Loads: +1. I=1: assert 3 cycs ahead of first transfer (two transfers only if 32B allowed) +2. I=0 data every other cycle: not asserted +3. I=0 data consecutive cycles: assert 3 cycs ahead of the 1of2 paired beats; if more than 2 beats are consecutive, assert 3 cycs ahead of each paired beat +DITC: +1. assertion not required **(or used by core?)** + +* d-2 (reld_data_vld and qualified signals) +Loads: +1. assert 2 cycs ahead of data +DITC: +1. assert 2 cycs ahead of data and also assert reld_ditc + +Cacheable Return Modes: +1. no back-to-back: coming=0 +2. all back-to-back: coming=1/0/1 +3. interleaved back-to-back: coming=1/0/0/0/1 +4. mixed: legal cases for subxfers (?) **i think the 'mixed' aren't valid - xucr0[52] selects b2b mode** + * 1 1 1 1 (no b2b) + * 1 2 1 (mixed) + * 1 1 2 (mixed) + * 2 1 1 (mixed) + * 2 2 (full b2b) +5. between subxfers a delay or other transaction can be inserted + +?? xucr0[52] definition selects b2b but also says crit first; i guess this means crit first is allowed, but not required?? a2l2 spec says it is not required to send crit first + +''' +class A2L2Trans(DotMap): + '''A2L2 Transaction''' + nextID = itertools.count() + def __init__(self, sim, tid, tt, tag=None, addr=None, length=0, wimg=0, cycD=None, be=None, data=None): + super().__init__() + self.sim = sim + self.id = next(A2L2Trans.nextID) + self.tid = tid + self.tt = tt + self.tag = tag + self.addr = addr + self.len = length + self.wimg = wimg + self.xfers = 1 + self.xferNum = 0 + self.xferCrit = 1 + self.beatNum = 1 + if cycD is not None: + self.cycC = cycD - 3 + self.cycV = cycD - 2 + self.cycD = cycD + self.be = f'{int(be, 16):032b}' if be is not None else None + self.data = data + self.done = False + + self.ieq1 = wimg & 0x4 == 0x4 + + self.load = tt == 0x00 or tt == 0x08 or tt == 0x22 or tt == 0x09 or tt == 0x0B # IF, LD, DITC, LARX, LARX_HINT + self.store = tt == 0x20 or tt == 0x29 # ST, STCX + + if self.load: + self.addr = self.addr & 0xFFFFFFF0 + elif self.store: + self.addr = self.addr & 0xFFFFFFE0 + if self.be == None or self.data == None: + raise Exception('A2L2Trans: store must have BE and data') + else: + self.len = 0 + self.storeStart = None + for i in range(len(self.be)): + if self.be[i] == '1': + if self.storeStart is None: + self.storeStart = i + self.len += 1 + elif self.storeStart is not None: + break + else: + raise Exception(f'A2L2Trans: unsupported ttype={tt}') + + self.ditc = tt == 0x22 + + if self.ieq1: + if tt == 0x00 or tt == 0x08: # IF, LD + if len == 7: + self.xfers = 2 + elif tt == 0x22: # DITC + self.xfers = 4 + else: + if self.load: + self.xfers = 4 + self.xferCrit = ((self.addr & 0x30) >> 4) + 1 + self.addr = self.addr & 0xFFFFFFC0 + + def readXfer(self): + # read() returns this qw crit-first if cacheable! + w0 = self.sim.mem.read(self.addr) + w1 = self.sim.mem.read(self.addr+4) + w2 = self.sim.mem.read(self.addr+8) + w3 = self.sim.mem.read(self.addr+12) + beatNum = self.beatNum + if self.beatNum < self.xfers: + self.beatNum += 1 + self.cycD += 1 + self.addr += 16 #wtf this is wrong - going to need to schedule the pattern when the trans is created!!!!!!!!!!!!!!!!!!!!!!!! + return w0,w1,w2,w3,beatNum + + def doStore(self): + addr = ((self.addr + self.storeStart) >> 2) << 2 + dataStart = self.storeStart*2 + if self.len == 1: + word = self.sim.mem.read(addr) + byte = self.addr & 0x3 + if byte == 0: + mask = 0xFFFFFF00 + elif byte == 1: + mask = 0xFFFF00FF + elif byte == 2: + mask = 0xFF00FFFF + else: + mask = 0x00FFFFFF + word = (word & mask) | (int(self.data[dataStart:dataStart+2], 16) << (byte*2)) + self.sim.mem.write(addr, word) + + elif self.len == 2: + word = self.sim.mem.read(addr) + hw = (self.addr & 0x2) >> 1 + if hw == 0: + mask = 0xFFFF0000 + else: + mask = 0x0000FFFF + word = (word & mask) | (int(self.data[dataStart:dataStart+4], 16) << (hw*4)) + self.sim.mem.write(addr, word) + + elif self.len == 4: + self.sim.mem.write(addr, int(self.data[dataStart:dataStart+8], 16)) + + elif self.len == 8: + self.sim.mem.write(addr, int(self.data[dataStart:dataStart+16], 16)) + self.sim.mem.write(addr+4, int(self.data[dataStart+16:dataStart+32], 16)) + + elif self.len == 16: + self.sim.mem.write(addr, int(self.data[0:8], 16)) + self.sim.mem.write(addr+4, int(self.data[8:16], 16)) + self.sim.mem.write(addr+8, int(self.data[16:24], 16)) + self.sim.mem.write(addr+12, int(self.data[24:32], 16)) + + elif self.len == 32: + self.sim.mem.write(addr, int(self.data[0:8], 16)) + self.sim.mem.write(addr+4, int(self.data[8:16], 16)) + self.sim.mem.write(addr+8, int(self.data[16:24], 16)) + self.sim.mem.write(addr+12, int(self.data[24:32], 16)) + self.sim.mem.write(addr+16, int(self.data[32:40], 16)) + self.sim.mem.write(addr+20, int(self.data[40:48], 16)) + self.sim.mem.write(addr+24, int(self.data[48:56], 16)) + self.sim.mem.write(addr+28, int(self.data[56:64], 16)) + + else: + raise Exception(f'A2L2Trans: unsupported store len={self.len}') + + +# ------------------------------------------------------------------------------------------------ +# Functions + +def hex(n, pad=0): + if pad: + return f'000000000000000000000000{n.value.hex()[2:].upper()}'[-pad:] + else: + return n.value.hex()[2:].upper() + +# ------------------------------------------------------------------------------------------------ +# Tasks + +async def A2L2Driver(dut, sim): + """A2L2 node interface""" + + transTypes = { + '00': 'IFETCH', + '08': 'LOAD', + '20': 'STORE' + } + + ok = True + readPending = [] + countReads = 0 + mem = {} + sim.msg('A2L2 Driver: started.') + + dut.an_ac_flh2l2_gate.value = 0 + + while ok and not sim.done: + + await RisingEdge(dut.clk_1x) + + dut.an_ac_req_ld_pop.value = 0 + dut.an_ac_req_st_pop.value = 0 + dut.an_ac_req_st_gather.value = 0 + + dut.an_ac_reld_data_coming.value = 0 + dut.an_ac_reld_data_vld.value = 0 + dut.an_ac_reld_ecc_err.value = 0 + dut.an_ac_reld_ecc_err_ue.value = 0 + dut.an_ac_reld_ditc.value = 0 + dut.an_ac_reld_l1_dump.value = 0 + dut.an_ac_req_spare_ctrl_a1.value = 0 + + if sim.threads == 1: + dut.an_ac_reservation_vld.value = 0 + dut.an_ac_stcx_complete.value = 0 + dut.an_ac_stcx_pass.value = 0 + else: + for i in range(sim.threads): + dut.an_ac_reservation_vld[i].value = 0 + dut.an_ac_stcx_complete[i].value = 0 + dut.an_ac_stcx_pass[i].value = 0 + + dut.an_ac_sync_ack.value = 0 + dut.an_ac_icbi_ack.value = 0 + dut.an_ac_back_inv.value = 0 + + # bummer IndexError: Slice indexing is not supported + #dut.an_ac_reld_data[0:31].value = 0x48000000 + #dut.an_ac_reld_data[32:63].value = 0x48000000 + #dut.an_ac_reld_data[64:95].value = 0x48000000 + #dut.an_ac_reld_data[96:127].value = 0x48000000 + # bummer TypeError: Unsupported type for value assignment: ('48000000480000004800000048000000') + #dut.an_ac_reld_data.value = '48000000480000004800000048000000' + #v = 0x48000000 + # bummer TypeError: Unsupported type for value assignment: ('01001000000000000000000000000000010010000000000000000000000000000100100000000000000000000000000001001000000000000000000000000000') + #dut.an_ac_reld_data.value = f'{v:0>32b}{v:0>32b}{v:0>32b}{v:0>32b}' + # otay! + #v1 = cocotb.binary.BinaryValue() + #v1.assign(f'{v:0>32b}{v:0>32b}{v:0>32b}{v:0>32b}') + #dut.an_ac_reld_data.value = v1.value + + if dut.ac_an_req.value: # should first check ac_an_req_pwr_token prev cyc + + tt = hex(dut.ac_an_req_ttype, 2) + transType = transTypes[tt] + tid = hex(dut.ac_an_req_thread) + ra = hex(dut.ac_an_req_ra, 8) + tag = hex(dut.ac_an_req_ld_core_tag, 2) + lenEnc = hex(dut.ac_an_req_ld_xfr_len) + le = 'LE ' if dut.ac_an_req_endian.value else '' + wimg_w = dut.ac_an_req_wimg_w.value + wimg_i = dut.ac_an_req_wimg_i.value + wimg_m = dut.ac_an_req_wimg_m.value + wimg_g = dut.ac_an_req_wimg_g.value + wimg = 0 + if wimg_w: + wimg += 8 + if wimg_i: + wimg += 4 + if wimg_m: + wimg += 2 + if wimg_g: + wimg += 1 + + if transType == 'IFETCH' or transType == 'LOAD': + # when allowing out-of-order, schedule reld once added + if len(readPending) == 0: + reldCyc = sim.cycle + 6 # const for now + else: + reldCyc = readPending[-1].cycD + 4 # worst-case const for now + trans = A2L2Trans(sim, tid, int(tt, 16), int(tag, 16), int(ra, 16), int(lenEnc, 16), wimg, reldCyc) + readPending.append(trans) + sim.msg(f'T{tid} {transType} {ra} tag={tag} len={trans.len} {le}WIMG:{wimg:X} reld data:{trans.cycD}') + elif transType == 'STORE': + # should verify st_data_pwr_token prev cycle + be = hex(dut.ac_an_st_byte_enbl, 8) + data = hex(dut.ac_an_st_data, 64) + trans = A2L2Trans(sim, tid, int(tt, 16), int(tag, 16), int(ra, 16), int(lenEnc, 16), wimg, None, be=be, data=data) + sim.msg(f'T{tid} {transType} {ra} tag={tag} len={trans.len} be={be} data={data} {le}WIMG:{wimg:X}') + trans.doStore() + #assert False, 'got a store' + + # data early indicator (d-3) + dut.an_ac_reld_data_coming.value = 0 + for i in range(len(readPending)): + trans = readPending[i] + if trans.cycC == sim.cycle: + dut.an_ac_reld_data_coming.value = 1 + if trans.xferNum == 0 and trans.xfers == 4: # 4 beats b2b - need diff scheduling for all modes + trans.cycC += 2 + + # data valid indicator (d-2) + dut.an_ac_reld_data_vld.value = 0 + dut.an_ac_reld_core_tag.value = 0x1F + dut.an_ac_reld_ditc.value = 1 + dut.an_ac_reld_qw.value = 3 + dut.an_ac_reld_crit_qw.value = 1 + + for i in range(len(readPending)): + trans = readPending[i] + if trans.cycV == sim.cycle: + trans.xferNum += 1 + dut.an_ac_reld_data_vld.value = 1 + dut.an_ac_reld_core_tag.value = trans.tag + dut.an_ac_reld_ditc.value = 1 if trans.ditc else 0 + dut.an_ac_reld_qw.value = trans.xferNum - 1 + dut.an_ac_reld_crit_qw.value = 1 if trans.xferNum == trans.xferCrit else 0 + if trans.xferNum < 4 and trans.xfers == 4: + trans.cycV += 1 + + # data beat + if len(readPending) > 0 and readPending[0].cycD == sim.cycle: # ordered + + trans = readPending[0] + w0,w1,w2,w3,beatNum = trans.readXfer() + + v1 = cocotb.binary.BinaryValue() + v1.assign(f'{w0:0>32b}{w1:0>32b}{w2:0>32b}{w3:0>32b}') + dut.an_ac_reld_data.value = v1.value + + sim.msg(f'RELD tag={trans.tag:02X} {w0:08X}{w1:08X}{w2:08X}{w3:08X} {beatNum}of{trans.xfers}{" crit" if beatNum == trans.xferCrit else ""}') + + if beatNum == trans.xfers: + trans.done = True + countReads += 1 #wtf do this in monitor + if len(readPending) == 1: + readPending = [] + else: + readPending = readPending[1:] + dut.an_ac_req_ld_pop.value = 1 #wtf can randomize, etc. + + +# A2L2 Checker +# check protocol, etc. +async def A2L2Checker(dut, sim): + """A2L2 interface checker """ + + me = 'A2L2 Checker' + ok = True + sim.msg(f'{me}: started.') + + while ok: + await RisingEdge(dut.clk_1x) + + +# A2L2 Monitor +# count transactions, etc. +# fail on bad addresses +async def A2L2Monitor(dut, sim): + """A2L2 interface monitor""" + + me = 'A2L2 Monitor' + ok = True + start = len(sim.config.a2l2.badAddr) > 0 + sim.msg(f'{me}: started.') + + while start and ok: + + await RisingEdge(dut.clk_1x) + + if dut.ac_an_req.value: # should first check ac_an_req_pwr_token prev cyc + + tt = hex(dut.ac_an_req_ttype, 2) + if tt == '00': #wtf someone should make this a enum/class + ra = dut.ac_an_req_ra.value.integer + for i in range(len(sim.config.a2l2.badAddr)): + blk = sim.config.a2l2.badAddr[i] + if 'I' in blk[2].upper(): + blkStart = int(blk[0], 16) + blkEnd = int(blk[1], 16) + if ra >= blkStart and ra <= blkEnd: + ok = False + assert False, (f'{me}: Bad IFetch @={ra:08X}') #wtf want this to end back in main code for summary + +class A2L2: + driver = A2L2Driver + checker = A2L2Checker + monitor = A2L2Monitor + + def __init__(self): + pass diff --git a/dev/sim/coco/Makefile.icarus b/dev/sim/coco/Makefile.icarus new file mode 100755 index 0000000..3da686f --- /dev/null +++ b/dev/sim/coco/Makefile.icarus @@ -0,0 +1,49 @@ +# a2o tb +# make -f Makefile.icarus build # rebuild and sim and fst +# make -f Makefile.icarus run # sim and fst +# make -f Makefile.icarus # sim + +#COCOTB_LOG_LEVEL=DEBUG +#GPI_EXTRA=vpi + +#COCOTB_RESOLVE_X = ZEROS # VALUE_ERROR ZEROS ONES RANDOM + +#SIM_BUILD ?= build +SIM ?= icarus + +# options +#COCOTB_HDL_TIMEUNIT ?= 1ns +#COCOTB_HDL_TIMEPRECISION ?= 1ps +#COCOTB_RESOLVE_X = VALUE_ERROR # ZEROS ONES RANDOM + +# icarus +# +# includes are needed for *.vh +# unisims is for FPGA RAMs +# coco forces -g2012 for some reason, and appends it after COMPILE_ARGS below! issue #781 + +VERILOG_ROOT = ../../verilog + +COMPILE_ARGS = -I$(VERILOG_ROOT)/trilib -I$(VERILOG_ROOT)/work -y$(VERILOG_ROOT)/unisims -y$(VERILOG_ROOT)/trilib_clk1x -y$(VERILOG_ROOT)/trilib -y$(VERILOG_ROOT)/work + +# other options + +# rtl +TOPLEVEL_LANG = verilog +# top-level to enable trace, etc. +VERILOG_SOURCES = ./cocotb_icarus.v +TOPLEVEL = cocotb_icarus + +# python test +MODULE = tb + +# cocotb make rules +include $(shell cocotb-config --makefiles)/Makefile.sim + +build: clean sim fst + +run: sim fst + +fst: + vcd2fst wtf-coco.vcd wtf-coco.fst + rm wtf-coco.vcd diff --git a/dev/sim/coco/Makefile.icarus.smt2 b/dev/sim/coco/Makefile.icarus.smt2 new file mode 100755 index 0000000..be23851 --- /dev/null +++ b/dev/sim/coco/Makefile.icarus.smt2 @@ -0,0 +1,44 @@ +# a2o smt2 tb +# make -f Makefile.icarus build # rebuild and sim and fst +# make -f Makefile.icarus run # sim and fst +# make -f Makefile.icarus # sim + +SIM_BUILD ?= build_smt2 +SIM ?= icarus + +# options +#COCOTB_HDL_TIMEUNIT ?= 1ns +#COCOTB_HDL_TIMEPRECISION ?= 1ps +#COCOTB_RESOLVE_X = VALUE_ERROR # ZEROS ONES RANDOM + +# icarus +# +# includes are needed for *.vh +# unisims is for FPGA RAMs +# coco forces -g2012 for some reason, and appends it after COMPILE_ARGS below! issue #781 + +VERILOG_ROOT = ../../verilog + +COMPILE_ARGS = -I$(VERILOG_ROOT)/smt2 -I$(VERILOG_ROOT)/trilib -I$(VERILOG_ROOT)/work -y$(VERILOG_ROOT)/unisims -y$(VERILOG_ROOT)/trilib_clk1x -y$(VERILOG_ROOT)/trilib -y$(VERILOG_ROOT)/work + +# other options + +# rtl +TOPLEVEL_LANG = verilog +# top-level to enable trace, etc. +VERILOG_SOURCES = ./cocotb_icarus.v +TOPLEVEL = cocotb_icarus + +# python test +MODULE = tb + +# cocotb make rules +include $(shell cocotb-config --makefiles)/Makefile.sim + +build: clean sim fst + +run: sim fst + +fst: + vcd2fst wtf-coco.vcd wtf-coco.fst + rm wtf-coco.vcd diff --git a/dev/sim/coco/Makefile.sweetpea b/dev/sim/coco/Makefile.sweetpea new file mode 100755 index 0000000..a66db43 --- /dev/null +++ b/dev/sim/coco/Makefile.sweetpea @@ -0,0 +1,45 @@ +# a2o tb +# make -f Makefile.icarus build # rebuild and sim and fst +# make -f Makefile.icarus run # sim and fst +# make -f Makefile.icarus # sim + +#COCOTB_LOG_LEVEL=DEBUG +#GPI_EXTRA=vpi + +#COCOTB_RESOLVE_X = ZEROS # VALUE_ERROR ZEROS ONES RANDOM + +SIM_BUILD ?= build_sweetpea +SIM ?= icarus + +# options +#COCOTB_HDL_TIMEUNIT ?= 1ns +#COCOTB_HDL_TIMEPRECISION ?= 1ps +#COCOTB_RESOLVE_X = VALUE_ERROR # ZEROS ONES RANDOM + +# icarus + +VERILOG_ROOT = ../../verilog + +COMPILE_ARGS = -I$(VERILOG_ROOT)/sweetpea -I$(VERILOG_ROOT)/trilib -I$(VERILOG_ROOT)/work -y$(VERILOG_ROOT)/unisims -y$(VERILOG_ROOT)/trilib_clk1x -y$(VERILOG_ROOT)/trilib -y$(VERILOG_ROOT)/work + +# other options + +# rtl +TOPLEVEL_LANG = verilog +# top-level to enable trace, etc. +VERILOG_SOURCES = ./cocotb_icarus.v +TOPLEVEL = cocotb_icarus + +# python test +MODULE = tb + +# cocotb make rules +include $(shell cocotb-config --makefiles)/Makefile.sim + +build: clean sim fst + +run: sim fst + +fst: + vcd2fst wtf-coco.vcd wtf-coco.fst + rm wtf-coco.vcd diff --git a/dev/sim/coco/Makefile.verilator b/dev/sim/coco/Makefile.verilator new file mode 100755 index 0000000..6d3a650 --- /dev/null +++ b/dev/sim/coco/Makefile.verilator @@ -0,0 +1,30 @@ +# a2o tb + +SIM_BUILD ?= sim_build_verilator +SIM ?= verilator + +# set precision +#COCOTB_HDL_TIMEPRECISION ?= 1ns + +# verilator +COMPILE_ARGS = --error-limit 1 --language 1364-2001 -Wno-fatal -Wno-LITENDIAN -Iverilog/work -Iverilog/trilib -Iverilog/unisims + +# coverage +#EXTRA_ARGS += --coverage +# tracing +EXTRA_ARGS += --trace + +# rtl +TOPLEVEL_LANG = verilog +VERILOG_SOURCES += verilog/trilib_clk1x/*.v +VERILOG_SOURCES += verilog/trilib/*.v +VERILOG_SOURCES += verilog/work/*.v + +# rtl top +TOPLEVEL = c + +# python test +MODULE = tbv + +# cocotb make rules +include $(shell cocotb-config --makefiles)/Makefile.sim \ No newline at end of file diff --git a/dev/sim/coco/OPEnv.py b/dev/sim/coco/OPEnv.py new file mode 100755 index 0000000..78f61ae --- /dev/null +++ b/dev/sim/coco/OPEnv.py @@ -0,0 +1,117 @@ +# OP Environment + +import cocotb +from cocotb.triggers import Timer +from cocotb.handle import Force +from cocotb.handle import Release + +from dotmap import DotMap + +# ------------------------------------------------------------------------------------------------ +# Classes + +class Sim(DotMap): + + def msg(self, m): + self.dut._log.info(f'[{self.cycle:08d}] {m}') #wtf do multiline if /n in m + + def __init__(self, dut, cfg=None): + super().__init__() + self.dut = dut + # defaults + self.memFiles = ['../mem/boot_ieq1.bin.hex'] #wtf cmdline parm + self.threads = None + self.resetCycle = 10 + self.hbCycles = 100 + self.clk2x = True + self.clk4x = False + self.resetAddr = 0xFFFFFFFC + self.resetOp = 0x48000002 + self.maxCycles = 1500 + self.memFiles = None + self.config = DotMap() + self.config.core = DotMap({ + 'creditsLd': None, + 'creditsSt': None, + 'creditsLdStSingle': False + }) + self.config.a2l2 = DotMap({ + 'badAddr': [('E0','E0', 'IRW')] + }) + # json + if cfg is not None: + pass + + # runtime + self.cycle = 0 + self.ok = True + self.fail = None + self.done = False + + if self.threads is None: + try: + v = dut.an_ac_pm_thread_stop[1].value + self.threads = 2 + except: + self.threads = 1 + self.msg(f'Set threads={self.threads}.') + +class TransQ(DotMap): + def __init__(self): + super().__init__() + +class Memory(DotMap): + + def __init__(self, sim, default=0, logStores=True): + super().__init__() + self.sim = sim + self.data = {} + self.le = False + self.default = default # default word data for unloaded + self.logStores = logStores + + def loadFile(self, filename, format='ascii', addr=0, le=0): + # format # binary, ascii, ascii w/addr + # le: reverse bytes + try: + if format == 'ascii': + with open(filename, 'r') as f: + lines = f.readlines() + for line in lines: + self.data[addr] = int(line, 16) # key is int + addr += 4 + elif format == 'binary': + pass + elif format == 'addrdata': + pass + except Exception as e: + self.sim.msg(f'Error reading {filename}:\n{e}') + raise IOError + + # word-aligned byte address + def read(self, addr): + try: + addr = addr + 0 + except: + addr = int(addr, 16) + if addr in self.data: + return self.data[addr] + else: + return self.default + + # word-aligned byte address + data + def write(self, addr, data): + try: + addr = addr + 0 + except: + addr = int(addr, 16) + try: + data = data + 0 + except: + data = int(data, 16) + if self.logStores: + if addr not in self.data: + self.sim.msg(f'Mem Update: @{addr:08X} XXXXXXXX->{data:08X}') + else: + self.sim.msg(f'Mem Update: @{addr:08X} {self.data[addr]:08X}->{data:08X}') + self.data[addr] = data diff --git a/dev/sim/coco/boot.lst b/dev/sim/coco/boot.lst new file mode 100755 index 0000000..912d354 --- /dev/null +++ b/dev/sim/coco/boot.lst @@ -0,0 +1,913 @@ + 1 # © IBM Corp. 2020 + 2 # Licensed under and subject to the terms of the CC-BY 4.0 + 3 # license (https://creativecommons.org/licenses/by/4.0/legalcode). + 4 # Additional rights, including the right to physically implement a softcore + 5 # that is compliant with the required sections of the Power ISA + 6 # Specification, will be available at no cost via the OpenPOWER Foundation. + 7 # This README will be updated with additional information when OpenPOWER's + 8 # license is available. + 9 + 10 # boot kernel + 11 # set up translations + 12 # set up timer facilities + 13 # set up threads + 14 # call user code + 15 # process user rc + 16 + 17 # todo: + 18 # 1. skip_printf_init flag should be threaded + 19 + 20 .include "defines.s" + 1 # © IBM Corp. 2020 + 2 # Licensed under and subject to the terms of the CC-BY 4.0 + 3 # license (https://creativecommons.org/licenses/by/4.0/legalcode). + 4 # Additional rights, including the right to physically implement a softcore + 5 # that is compliant with the required sections of the Power ISA + 6 # Specification, will be available at no cost via the OpenPOWER Foundation. + 7 # This README will be updated with additional information when OpenPOWER's + 8 # license is available. + 9 + 10 #----------------------------------------- + 11 # Defines + 12 #----------------------------------------- + 13 + 14 # Regs + 15 + 16 .set r0, 0 + 17 .set r1, 1 + 18 .set r2, 2 + 19 .set r3, 3 + 20 .set r4, 4 + 21 .set r5, 5 + 22 .set r6, 6 + 23 .set r7, 7 + 24 .set r8, 8 + 25 .set r9, 9 + 26 .set r10,10 + 27 .set r11,11 + 28 .set r12,12 + 29 .set r13,13 + 30 .set r14,14 + 31 .set r15,15 + 32 .set r16,16 + 33 .set r17,17 + 34 .set r18,18 + 35 .set r19,19 + 36 .set r20,20 + 37 .set r21,21 + 38 .set r22,22 + 39 .set r23,23 + 40 .set r24,24 + 41 .set r25,25 + 42 .set r26,26 + 43 .set r27,27 + 44 .set r28,28 + 45 .set r29,29 + 46 .set r30,30 + 47 .set r31,31 + 48 + 49 .set f0, 0 + 50 .set f1, 1 + 51 .set f2, 2 + 52 .set f3, 3 + 53 .set f4, 4 + 54 .set f5, 5 + 55 .set f6, 6 + 56 .set f7, 7 + 57 .set f8, 8 + 58 .set f9, 9 + 59 .set f10,10 + 60 .set f11,11 + 61 .set f12,12 + 62 .set f13,13 + 63 .set f14,14 + 64 .set f15,15 + 65 .set f16,16 + 66 .set f17,17 + 67 .set f18,18 + 68 .set f19,19 + 69 .set f20,20 + 70 .set f21,21 + 71 .set f22,22 + 72 .set f23,23 + 73 .set f24,24 + 74 .set f25,25 + 75 .set f26,26 + 76 .set f27,27 + 77 .set f28,28 + 78 .set f29,29 + 79 .set f30,30 + 80 .set f31,31 + 81 + 82 .set cr0, 0 + 83 .set cr1, 1 + 84 .set cr2, 2 + 85 .set cr3, 3 + 86 .set cr4, 4 + 87 .set cr5, 5 + 88 .set cr6, 6 + 89 .set cr7, 7 + 90 + 91 # SPR numbers + 92 + 93 .set srr0, 26 + 94 .set srr1, 27 + 95 .set epcr, 307 + 96 .set tar, 815 + 97 + 98 .set dbsr, 304 + 99 .set dbcr0, 308 + 100 .set dbcr1, 309 + 101 .set dbcr2, 310 + 102 .set dbcr3, 848 + 103 + 104 .set ivpr, 63 + 105 + 106 .set iucr0, 1011 + 107 .set iucr1, 883 + 108 .set iucr2, 884 + 109 + 110 .set iudbg0, 888 + 111 .set iudbg1, 889 + 112 .set iudbg2, 890 + 113 .set iulfsr, 891 + 114 .set iullcr, 892 + 115 + 116 .set mmucr0, 1020 + 117 .set mmucr1, 1021 + 118 .set mmucr2, 1022 + 119 .set mmucr3, 1023 + 120 + 121 .set tb, 268 + 122 .set tbl, 284 + 123 .set tbh, 285 + 124 + 125 .set dec, 22 + 126 .set udec, 550 + 127 .set tsr, 336 + 128 .set tcr, 340 + 129 + 130 .set xucr0, 1014 + 131 .set xucr1, 851 + 132 .set xucr2, 1016 + 133 .set xucr3, 852 + 134 .set xucr4, 853 + 135 + 136 .set tens, 438 + 137 .set tenc, 439 + 138 .set tensr, 437 + 139 + 140 .set pid, 48 + 141 .set pir, 286 + 142 .set pvr, 287 + 143 .set tir, 446 + 144 + 21 + 22 .section .text + 23 start: + 24 + 25 int_000: + 26 0000 48000400 b boot_start + 27 + 28 # critical input + 29 0004 4800001C .align 5 + 29 60000000 + 29 60000000 + 29 60000000 + 29 60000000 + 30 int_020: + 31 0020 48000000 b . + 32 + 33 # debug + 34 0024 4800001C .align 5 + 34 60000000 + 34 60000000 + 34 60000000 + 34 60000000 + 35 int_040: + 36 0040 48000000 b . + 37 + 38 # dsi + 39 0044 4800001C .align 5 + 39 60000000 + 39 60000000 + 39 60000000 + 39 60000000 + 40 int_060: + 41 0060 48000000 b . + 42 + 43 # isi + 44 0064 4800001C .align 5 + 44 60000000 + 44 60000000 + 44 60000000 + 44 60000000 + 45 int_080: + 46 0080 48000000 b . + 47 + 48 # external + 49 0084 4800001C .align 5 + 49 60000000 + 49 60000000 + 49 60000000 + 49 60000000 + 50 int_0A0: + 51 00a0 48000000 b . + 52 + 53 # alignment + 54 00a4 4800001C .align 5 + 54 60000000 + 54 60000000 + 54 60000000 + 54 60000000 + 55 int_0C0: + 56 00c0 48000000 b . + 57 + 58 # program + 59 00c4 4800001C .align 5 + 59 60000000 + 59 60000000 + 59 60000000 + 59 60000000 + 60 int_0E0: + 61 00e0 48000000 b . + 62 + 63 # fp unavailable + 64 00e4 4800001C .align 5 + 64 60000000 + 64 60000000 + 64 60000000 + 64 60000000 + 65 int_100: + 66 0100 48000000 b . + 67 + 68 # sc + 69 0104 4800001C .align 5 + 69 60000000 + 69 60000000 + 69 60000000 + 69 60000000 + 70 int_120: + 71 0120 48000CE0 b int_120_handler + 72 + 73 # apu unavailable + 74 0124 4800001C .align 5 + 74 60000000 + 74 60000000 + 74 60000000 + 74 60000000 + 75 int_140: + 76 0140 48000000 b . + 77 + 78 # decrementer + 79 0144 4800001C .align 5 + 79 60000000 + 79 60000000 + 79 60000000 + 79 60000000 + 80 int_160: + 81 0160 48000000 b . + 82 + 83 # fit + 84 0164 4800001C .align 5 + 84 60000000 + 84 60000000 + 84 60000000 + 84 60000000 + 85 int_180: + 86 0180 48000000 b . + 87 + 88 # watchdog + 89 0184 4800001C .align 5 + 89 60000000 + 89 60000000 + 89 60000000 + 89 60000000 + 90 int_1A0: + 91 01a0 48000000 b . + 92 + 93 # dtlb + 94 01a4 4800001C .align 5 + 94 60000000 + 94 60000000 + 94 60000000 + 94 60000000 + 95 int_1C0: + 96 01c0 48000000 b . + 97 + 98 # itlb + 99 01c4 4800001C .align 5 + 99 60000000 + 99 60000000 + 99 60000000 + 99 60000000 + 100 int_1E0: + 101 01e0 48000000 b . + 102 + 103 # vector unavailable + 104 01e4 4800001C .align 5 + 104 60000000 + 104 60000000 + 104 60000000 + 104 60000000 + 105 int_200: + 106 0200 48000000 b . + 107 + 108 # + 109 0204 4800001C .align 5 + 109 60000000 + 109 60000000 + 109 60000000 + 109 60000000 + 110 int_220: + 111 0220 48000000 b . + 112 + 113 # + 114 0224 4800001C .align 5 + 114 60000000 + 114 60000000 + 114 60000000 + 114 60000000 + 115 int_240: + 116 0240 48000000 b . + 117 + 118 # + 119 0244 4800001C .align 5 + 119 60000000 + 119 60000000 + 119 60000000 + 119 60000000 + 120 int_260: + 121 0260 48000000 b . + 122 + 123 # doorbell + 124 0264 4800001C .align 5 + 124 60000000 + 124 60000000 + 124 60000000 + 124 60000000 + 125 int_280: + 126 0280 48000000 b . + 127 + 128 # doorbell critical + 129 0284 4800001C .align 5 + 129 60000000 + 129 60000000 + 129 60000000 + 129 60000000 + 130 int_2A0: + 131 02a0 48000000 b . + 132 + 133 # doorbell guest + 134 02a4 4800001C .align 5 + 134 60000000 + 134 60000000 + 134 60000000 + 134 60000000 + 135 int_2C0: + 136 02c0 48000000 b . + 137 + 138 # doorbell guest critical + 139 02c4 4800001C .align 5 + 139 60000000 + 139 60000000 + 139 60000000 + 139 60000000 + 140 int_2E0: + 141 02e0 48000000 b . + 142 + 143 # hvsc + 144 02e4 4800001C .align 8 + 144 60000000 + 144 60000000 + 144 60000000 + 144 60000000 + 145 int_300: + 146 0300 48000A00 b int_300_handler + 147 + 148 # hvpriv + 149 0304 4800001C .align 5 + 149 60000000 + 149 60000000 + 149 60000000 + 149 60000000 + 150 int_320: + 151 0320 48000000 b . + 152 + 153 # lrat + 154 0324 4800001C .align 5 + 154 60000000 + 154 60000000 + 154 60000000 + 154 60000000 + 155 int_340: + 156 0340 48000000 b . + 157 + 158 # ------------------------------------------------------------------------------------------------- + 159 # initial translation + 160 # both erats: + 161 # 00000000 1M: (boot) + 162 # 10000000 1M: (test) + 163 + 164 0344 480000BC .align 8 + 164 60000000 + 164 60000000 + 164 60000000 + 164 60000000 + 165 boot_start: + 166 + 167 0400 7CBE6AA6 mfspr r5,tir # who am i? + 168 0404 2C250000 cmpdi r5,0x00 # skip unless T0 + 169 0408 408200EC bne init_t123 + 170 + 171 040c 3C608C00 lis r3,0x8C00 # 32=ecl 36:37=tlbsel (10=i, 11=d) + 172 # derat 31 @00000000 + 173 + 174 0410 3800001F li r0,0x001F # entry #31 + 175 0414 38400015 li r2,0x0015 # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/ + 176 0418 38800000 li r4,0 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63 + 177 041c 3900025F li r8,0x025F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 s + 178 + 179 0420 7C7CFBA6 mtspr mmucr0,r3 + 180 0424 7C4011A6 eratwe r2,r0,2 + 181 0428 7C8009A6 eratwe r4,r0,1 + 182 042c 7D0001A6 eratwe r8,r0,0 + 183 0430 4C00012C isync + 184 + 185 0434 81400A08 lwz r10,CONFIG+S_ERATW2(r0) # load parms for erat settings + 186 + 187 # derat 30 @100000000 + 188 + 189 0438 3800001E li r0,0x001E # entry #30 + 190 043c 3C801000 lis r4,0x1000 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63 + 191 0440 3900025F li r8,0x025F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 s + 192 0444 65081000 oris r8,r8,0x1000 + 193 + 194 0448 7D4011A6 eratwe r10,r0,2 + 195 044c 7C8009A6 eratwe r4,r0,1 + 196 0450 7D0001A6 eratwe r8,r0,0 + 197 0454 4C00012C isync + 198 + 199 0458 3C608800 lis r3,0x8800 # 32=ecl 36:37=tlbsel (10=i, 11=d) + 200 # ierat 15 @00000000 + 201 + 202 045c 3800000F li r0,0x000F # entry #15 + 203 0460 3840003F li r2,0x003F # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/ + 204 0464 38800000 li r4,0 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63 + 205 0468 3900025F li r8,0x025F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 s + 206 + 207 046c 7C7CFBA6 mtspr mmucr0,r3 + 208 0470 7C4011A6 eratwe r2,r0,2 + 209 0474 7C8009A6 eratwe r4,r0,1 + 210 0478 7D0001A6 eratwe r8,r0,0 + 211 047c 4C00012C isync + 212 + 213 # *** leave the init'd entry 14 for MT access to FFFFFFC0 + 214 # ierat 13 @10000000 + 215 + 216 0480 3800000D li r0,0x000D # entry #13 + 217 0484 3C801000 lis r4,0x1000 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63 + 218 0488 3900025F li r8,0x025F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 s + 219 048c 65081000 oris r8,r8,0x1000 + 220 + 221 0490 7D4011A6 eratwe r10,r0,2 + 222 0494 7C8009A6 eratwe r4,r0,1 + 223 0498 7D0001A6 eratwe r8,r0,0 + 224 049c 4C00012C isync + 225 + 226 # ------------------------------------------------------------------------------------------------- + 227 # init + 228 # + 229 + 230 # T0-only + 231 # set up any core facilities, then enable the others if config'd + 232 init_t0: + 233 + 234 # switch to 64b + 235 + 236 04a0 81400A00 lwz r10,CONFIG+S_MSR(r0) + 237 04a4 7D400124 mtmsr r10 + 238 04a8 4C00012C isync + 239 + 240 # other init + 241 + 242 04ac 3C200300 lis r1,0x0300 # icm=gicm=1 + 243 04b0 7C334BA6 mtspr epcr,r1 + 244 + 245 # set up timer facs + 246 + 247 04b4 38200000 li r1,0 # clear + 248 04b8 7C3603A6 mtspr dec,r1 + 249 04bc 7C3D43A6 mtspr tbh,r1 + 250 04c0 7C3C43A6 mtspr tbl,r1 + 251 + 252 04c4 3C40FE00 lis r2,0xFE00 # mask: clear enw,wis,wrs,dis,fis,udis + 253 04c8 7C5053A6 mtspr tsr,r2 + 254 + 255 04cc 7C56FAA6 mfspr r2,xucr0 + 256 04d0 70420200 andi. r2,r2,0x0200 # set tcs=0 + 257 04d4 7C56FBA6 mtspr xucr0,r2 + 258 + 259 04d8 7C3053A6 mtspr tsr,r1 # clear tsr + 260 04dc 7C3453A6 mtspr tcr,r1 # disable all timers + 261 + 262 # set thread configuration + 263 + 264 04e0 80200A04 lwz r1,CONFIG+S_FLAGS(r0) + 265 04e4 7021000F andi. r1,r1,0xF + 266 04e8 7C366BA6 mtspr tens,r1 # 60:63 = tid 3:0 enabled + 267 #not r1,r1 + 268 #mtspr tenc,r1 # in case T0 is marked disabled + 269 04ec 4C00012C isync + 270 + 271 04f0 48000014 b boot_complete + 272 + 273 # except T0 + 274 # just worry about myself + 275 + 276 init_t123: + 277 + 278 # switch to 64b + 279 + 280 04f4 81400A00 lwz r10,CONFIG+S_MSR(r0) + 281 04f8 7D400124 mtmsr r10 + 282 04fc 4C00012C isync + 283 + 284 0500 48000004 b boot_complete + 285 + 286 # ------------------------------------------------------------------------------------------------- + 287 boot_complete: + 288 + 289 # set up thread and hop to it + 290 + 291 0504 80200A04 lwz r1,CONFIG+S_FLAGS(r0) + 292 0508 74218000 andis. r1,r1,0x8000 # 1=skip initial printf init + 293 050c 40820008 bne boot_complete_1 + 294 0510 480006F1 bl printf_reset # wipe buffer + 295 + 296 boot_complete_1: + 297 + 298 0514 80200A04 lwz r1,CONFIG+S_FLAGS(r0) + 299 0518 3C407FFF lis r2,0x7FFF # clear printf flag + 300 051c 6042FFFF ori r2,r2,0xFFFF + 301 0520 7C211038 and r1,r1,r2 + 302 0524 90200A04 stw r1,CONFIG+S_FLAGS(r0) + 303 + 304 0528 7CBE6AA6 mfspr r5,tir # who am i? + 305 052c 78A53664 sldi r5,r5,6 # 64B offset + 306 0530 38A50A80 addi r5,r5,CONFIG+T_CONFIG + 307 + 308 0534 81650000 lwz r11,T_MSR(r5) + 309 0538 E9850008 ld r12,T_STACK(r5) + 310 053c E9A50010 ld r13,T_ENTRY(r5) + 311 + 312 0540 80200A04 lwz r1,CONFIG+S_FLAGS(r0) + 313 0544 70210010 andi. r1,r1,FLAG_EOT_SC + 314 0548 4182001C beq eot_blr + 315 + 316 eot_sc: + 317 + 318 054c 80400A0C lwz r2,CONFIG+S_EOT_SC(r0) + 319 0550 3C204400 lis r1,0x4400 # 'sc 1' + 320 0554 60210012 ori r1,r1,0022 + 321 0558 F8220000 std r1,0x0(r2) + 322 055c 7C2803A6 mtlr r1 # prog will blr to sc + 323 0560 48000014 b process_start + 324 + 325 eot_blr: + 326 + 327 0564 48000005 bl 4 + 328 0568 7C2802A6 mflr r1 + 329 056c 38210030 addi r1,r1,0x30 # !!!!!!!!!!!!!!! <-- WARNING! + 330 0570 7C2803A6 mtlr r1 # prog will blr to exec_complete + 331 + 332 process_start: + 333 + 334 0574 7D7B03A6 mtspr srr1,r11 # msr + 335 0578 7DBA03A6 mtspr srr0,r13 # @entry + 336 057c 7D816378 mr r1,r12 # @stack + 337 0580 7C7E6AA6 mfspr r3,tir # tid - main(tid) if yall want it + 338 + 339 0584 7C4C42A6 mfspr r2,tb + 340 0588 F8450030 std r2,T_TIMER_START(r5) + 341 058c 4C000064 rfi + 342 0590 60000000 nop # !!!!!!!!!!!!!!! pads for lr calc + 343 0594 60000000 nop + 344 0598 60000000 nop + 345 + 346 # ------------------------------------------------------------------------------------------------- + 347 exec_complete: + 348 # allow blr to here, or it will be entered by sc directly + 349 + 350 # user blr'd here... + 351 059c 44000022 sc 1 # hvsc back to sup state + 352 + 353 exec_complete_sup: + 354 05a0 7CBE6AA6 mfspr r5,tir # who am i? + 355 05a4 78A53664 sldi r5,r5,6 # 64B offset + 356 05a8 38A50A80 addi r5,r5,CONFIG+T_CONFIG + 357 + 358 05ac 7C4C42A6 mfspr r2,tb + 359 05b0 F8450038 std r2,T_TIMER_END(r5) + 360 + 361 05b4 2C230000 cmpdi r3,0 # check rc + 362 05b8 41820148 beq pass + 363 05bc 48000044 b fail + 364 + 365 # ------------------------------------------------------------------------------------------------- + 366 # dead zone + 367 05c0 48000040 .align 8 + 367 60000000 + 367 60000000 + 367 60000000 + 367 60000000 + 368 fail: + 369 0600 48000000 b . + 370 + 371 # ------------------------------------------------------------------------------------------------- + 372 # happy ending + 373 0604 480000FC .align 8 + 373 60000000 + 373 60000000 + 373 60000000 + 373 60000000 + 374 pass: + 375 0700 48000000 b . + 376 + 377 # ------------------------------------------------------------------------------------------------- + 378 + 379 # dec + 380 0704 480000FC .align 11 + 380 60000000 + 380 60000000 + 380 60000000 + 380 60000000 + 381 int_800: + 382 0800 48000000 b . + 383 + 384 # perf + 385 0804 4800001C .align 5 + 385 60000000 + 385 60000000 + 385 60000000 + 385 60000000 + 386 int_820: + 387 0820 48000000 b . + 388 + 389 .set CONFIG,0x0A00 + 390 # ------------------------------------------------------------------------------------------------- + 391 # config info + 392 0824 480001DC .align 9 + 392 60000000 + 392 60000000 + 392 60000000 + 392 60000000 + 393 + 394 0a00 8002B000 .long 0x8002B000 # sup MSR cm=1 ce=1 ee=1 pr=0 fp=1 me=1 fe=00 de=0 is=0 ds=0 + 395 0a04 80000001 .long 0x80000001 # flags: skip_printf_init=0 eot_sc=27 thr_en=28:31(T3:T0) + 396 0a08 000000BF .long 0x000000BF # erat w2 (test) # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wi + 397 0a0c 10000000 .long 0x10000000 # @user eot sc + 398 + 399 # per-thread configs (64B each) + 400 0a10 48000070 .align 7 + 400 60000000 + 400 60000000 + 400 60000000 + 400 60000000 + 401 0a80 8002F000 .long 0x8002F000 # usr MSR cm=1 ce=1 ee=1 pr=1 fp=1 me=1 fe=00 de=0 is=0 ds=0 + 402 0a84 00000000 .long 0x00000000 # + 403 0a88 00000000 .long 0x00000000 # + 404 0a8c 1003FF00 .long 0x1003FF00 # @stack + 405 0a90 00000000 .long 0x00000000 # + 406 0a94 100004B0 .long 0x100004B0 # @entry + 407 0a98 00000000 .long 0 + 408 0a9c 10030000 .long 0x10030000 # @print_start + 409 0aa0 00000000 .long 0 + 410 0aa4 10031FFF .long 0x10031FFF # @print_end + 411 0aa8 00000000 .long 0 + 412 0aac 10030000 .long 0x10030000 # print ptr + 413 0ab0 00000000 .quad 0 # start tb + 413 00000000 + 414 0ab8 00000000 .quad 0 # end tb + 414 00000000 + 415 + 416 0ac0 8002F000 .long 0x8002F000 # usr MSR cm=1 ce=1 ee=1 pr=1 fp=1 me=1 fe=00 de=0 is=0 ds=0 + 417 0ac4 00000000 .long 0x00000000 # + 418 0ac8 00000000 .long 0x00000000 # + 419 0acc 1003DF00 .long 0x1003DF00 # @stack + 420 0ad0 00000000 .long 0x00000000 # + 421 0ad4 100004B0 .long 0x100004B0 # @entry + 422 0ad8 00000000 .long 0 + 423 0adc 10032000 .long 0x10032000 # @print_start + 424 0ae0 00000000 .long 0 + 425 0ae4 10033FFF .long 0x10033FFF # @print_end + 426 0ae8 00000000 .long 0 + 427 0aec 10032000 .long 0x10032000 # print ptr + 428 0af0 00000000 .quad 0 # start tb + 428 00000000 + 429 0af8 00000000 .quad 0 # end tb + 429 00000000 + 430 + 431 0b00 8002F000 .long 0x8002F000 # usr MSR cm=1 ce=1 ee=1 pr=1 fp=1 me=1 fe=00 de=0 is=0 ds=0 + 432 0b04 00000000 .long 0x00000000 # flags + 433 0b08 00000000 .long 0x00000000 # + 434 0b0c 1003BF00 .long 0x1003BF00 # @stack + 435 0b10 00000000 .long 0x00000000 # + 436 0b14 100004B0 .long 0x100004B0 # @entry + 437 0b18 00000000 .long 0 + 438 0b1c 10034000 .long 0x10034000 # @print_start + 439 0b20 00000000 .long 0 + 440 0b24 10035FFF .long 0x10035FFF # @print_end + 441 0b28 00000000 .long 0 + 442 0b2c 10034000 .long 0x10034000 # print ptr + 443 0b30 00000000 .quad 0 # start tb + 443 00000000 + 444 0b38 00000000 .quad 0 # end tb + 444 00000000 + 445 + 446 0b40 8002F000 .long 0x8002F000 # usr MSR cm=1 ce=1 ee=1 pr=1 fp=1 me=1 fe=00 de=0 is=0 ds=0 + 447 0b44 00000000 .long 0x00000000 # flags + 448 0b48 00000000 .long 0x00000000 # + 449 0b4c 10039F00 .long 0x10039F00 # @stack + 450 0b50 00000000 .long 0x00000000 # + 451 0b54 100004B0 .long 0x100004B0 # @entry + 452 0b58 00000000 .long 0 + 453 0b5c 10036000 .long 0x10036000 # @print_start + 454 0b60 00000000 .long 0 + 455 0b64 10037FFF .long 0x10037FFF # @print_end + 456 0b68 00000000 .long 0 + 457 0b6c 10036000 .long 0x10036000 # print ptr + 458 0b70 00000000 .quad 0 # start tb + 458 00000000 + 459 0b78 00000000 .quad 0 # end tb + 459 00000000 + 460 + 461 + 462 .set S_MSR,0x00 + 463 .set S_FLAGS,0x04 + 464 .set S_ERATW2,0x08 + 465 .set S_EOT_SC,0x0C + 466 + 467 .set T_CONFIG,0x80 + 468 .set T_MSR,0x00 + 469 .set T_FLAGS,0x04 + 470 .set T_STACK,0x08 + 471 .set T_ENTRY,0x10 + 472 .set T_TIMER_START,0x30 + 473 .set T_TIMER_END,0x38 + 474 .set T_PRINTSTART, 0x18 + 475 .set T_PRINTEND, 0x20 + 476 .set T_PRINTF, 0x28 + 477 .set FLAG_EOT_SC,0x10 + 478 + 479 + 480 # ------------------------------------------------------------------------------------------------- + 481 # other stuff + 482 0b80 48000080 .align 10 + 482 60000000 + 482 60000000 + 482 60000000 + 482 60000000 + 483 + 484 # clear buffer and reset pointer to start + 485 .align 6 + 486 printf_reset: + 487 + 488 0c00 7CBE6AA6 mfspr r5,tir # who am i? + 489 0c04 78A53664 sldi r5,r5,6 # 64B offset + 490 0c08 38A50A80 addi r5,r5,CONFIG+T_CONFIG + 491 + 492 0c0c 38C50018 addi r6,r5,T_PRINTSTART + 493 0c10 E8E60000 ld r7,0(r6) # buffer start + 494 0c14 38C50020 addi r6,r5,T_PRINTEND + 495 0c18 E9060000 ld r8,0(r6) # buffer end + 496 0c1c 7D074050 sub r8,r8,r7 + 497 0c20 39080001 addi r8,r8,1 # num bytes + 498 + 499 0c24 7D0903A6 mtctr r8 + 500 0c28 38C00000 li r6,0 + 501 0c2c 7CE83B78 mr r8,r7 + 502 printf_reset_clr: + 503 0c30 98C80000 stb r6,0(r8) + 504 0c34 39080001 addi r8,r8,1 + 505 0c38 4200FFF8 bdnz printf_reset_clr + 506 + 507 0c3c 39050028 addi r8,r5,T_PRINTF + 508 0c40 F8E80000 std r7,0(r8) # reset ptr + 509 + 510 0c44 4E800020 blr + 511 + 512 + 513 # hvsc + 514 0c48 480000B8 .align 8 + 514 60000000 + 514 60000000 + 514 60000000 + 514 60000000 + 515 # go to exec_complete_sup in sup mode + 516 int_300_handler: + 517 + 518 0d00 80000A00 lwz r0,CONFIG+S_MSR(r0) + 519 0d04 7C000124 mtmsr r0 + 520 0d08 4C00012C isync + 521 0d0c 4BFFF894 b exec_complete_sup + 522 + 523 # sc + 524 0d10 480000F0 .align 8 + 524 60000000 + 524 60000000 + 524 60000000 + 524 60000000 + 525 # r3 is id, remaining are function-specific + 526 # not preserving r0, r3-r9 right now + 527 # + 528 # 0001 whoami + 529 # 0010 tick + 530 # 0100 putchar r4=c + 531 # 0106 printf_mode *NI* + 532 # 0107 printf_rst + 533 # + 534 int_120_handler: + 535 + 536 0e00 7C0802A6 mflr r0 + 537 + 538 0e04 2C230001 cmpdi r3,0x0001 + 539 0e08 41820038 beq sc_whoami + 540 0e0c 2C230010 cmpdi r3,0x0010 + 541 0e10 41820070 beq sc_tick + 542 0e14 2C230100 cmpdi r3,0x100 + 543 0e18 418200A8 beq sc_putchar + 544 0e1c 2C230107 cmpdi r3,0x107 + 545 0e20 41820120 beq sc_printf_rst + 546 + 547 0e24 3860FFFF li r3,-1 + 548 0e28 7C0803A6 mtlr r0 + 549 0e2c 4C000064 rfi + 550 + 551 # thread id + 552 0e30 60000000 .align 6 + 552 60000000 + 552 60000000 + 552 60000000 + 553 sc_whoami: + 554 0e40 7C7E6AA6 mfspr r3,tir + 555 0e44 4C000064 rfi + 556 + 557 # tb + 558 0e48 48000038 .align 6 + 558 60000000 + 558 60000000 + 558 60000000 + 558 60000000 + 559 sc_tick: + 560 0e80 7C6C42A6 mfspr r3,tb + 561 0e84 4C000064 rfi + 562 + 563 # wrap buffer; could add flag to stop when full, or reset + 564 0e88 48000038 .align 6 + 564 60000000 + 564 60000000 + 564 60000000 + 564 60000000 + 565 sc_putchar: + 566 + 567 0ec0 7CBE6AA6 mfspr r5,tir # who am i? + 568 0ec4 78A53664 sldi r5,r5,6 # 64B offset + 569 0ec8 38A50A80 addi r5,r5,CONFIG+T_CONFIG + 570 + 571 0ecc 38C50028 addi r6,r5,T_PRINTF + 572 0ed0 E8E60000 ld r7,0(r6) # buffer ptr + 573 0ed4 98870000 stb r4,0(r7) # store char + 574 0ed8 38E70001 addi r7,r7,1 + 575 + 576 0edc 39050020 addi r8,r5,T_PRINTEND + 577 0ee0 E9080000 ld r8,0(r8) # buffer end + 578 0ee4 7C274000 cmpd r7,r8 + 579 0ee8 38600000 li r3,0 # rc=normal + 580 0eec 40810010 ble sc_putchar_ok + 581 0ef0 39050018 addi r8,r5,T_PRINTSTART + 582 0ef4 E8E80000 ld r7,0(r8) # buffer start + 583 0ef8 3860FFFF li r3,-1 # rc=full + 584 sc_putchar_ok: + 585 0efc F8E60000 std r7,0(r6) # save ptr + 586 + 587 0f00 4C000064 rfi + 588 + 589 # clear buffer and reset pointer to start + 590 0f04 4800003C .align 6 + 590 60000000 + 590 60000000 + 590 60000000 + 590 60000000 + 591 sc_printf_rst: + 592 + 593 0f40 7C6902A6 mfctr r3 + 594 + 595 0f44 4BFFFCBD bl printf_reset + 596 + 597 0f48 7C6903A6 mtctr r3 + 598 0f4c 7C0803A6 mtlr r0 + 599 0f50 38600000 li r3,0 + 600 + 601 0f54 4C000064 rfi + 602 diff --git a/dev/sim/coco/build_smt2/cmds.f b/dev/sim/coco/build_smt2/cmds.f new file mode 100755 index 0000000..3e26e00 --- /dev/null +++ b/dev/sim/coco/build_smt2/cmds.f @@ -0,0 +1 @@ ++timescale+1ns/1ps diff --git a/dev/sim/coco/build_sweetpea/cmds.f b/dev/sim/coco/build_sweetpea/cmds.f new file mode 100755 index 0000000..3e26e00 --- /dev/null +++ b/dev/sim/coco/build_sweetpea/cmds.f @@ -0,0 +1 @@ ++timescale+1ns/1ps diff --git a/dev/sim/coco/cocotb_icarus.v b/dev/sim/coco/cocotb_icarus.v new file mode 100755 index 0000000..d09f543 --- /dev/null +++ b/dev/sim/coco/cocotb_icarus.v @@ -0,0 +1,321 @@ + +`include "tri_a2o.vh" + +`timescale 1ns/1ps + +// might add some sim-only lines to enable clks, etc. + +module cocotb_icarus ( + + input[0:`NCLK_WIDTH-1] nclk, + input scan_in, + output scan_out, + + // Pervasive clock control + input an_ac_rtim_sl_thold_8, + input an_ac_func_sl_thold_8, + input an_ac_func_nsl_thold_8, + input an_ac_ary_nsl_thold_8, + input an_ac_sg_8, + input an_ac_fce_8, + input [0:7] an_ac_abst_scan_in, + + // L2 LARX/STCX + input [0:`THREADS-1] an_ac_reservation_vld, + input [0:`THREADS-1] an_ac_stcx_complete, + input [0:`THREADS-1] an_ac_stcx_pass, + + // ICBI ACK Interface + input an_ac_icbi_ack, + input [0:1] an_ac_icbi_ack_thread, + + // Back invalidate interface + input an_ac_back_inv, + input [64-`REAL_IFAR_WIDTH:63] an_ac_back_inv_addr, + input [0:4] an_ac_back_inv_target, // connect to bit(0) + input an_ac_back_inv_local, + input an_ac_back_inv_lbit, + input an_ac_back_inv_gs, + input an_ac_back_inv_ind, + input [0:7] an_ac_back_inv_lpar_id, + output ac_an_back_inv_reject, + output [0:7] ac_an_lpar_id, + + // L2 Reload Inputs + input an_ac_reld_data_vld, // reload data is coming next cycle + input [0:4] an_ac_reld_core_tag, // reload data destinatoin tag (which load queue) + input [0:127] an_ac_reld_data, // Reload Data + input [58:59] an_ac_reld_qw, // quadword address of reload data beat + input an_ac_reld_ecc_err, // Reload Data contains a Correctable ECC error + input an_ac_reld_ecc_err_ue, // Reload Data contains an Uncorrectable ECC error + input an_ac_reld_data_coming, + input an_ac_reld_ditc, + input an_ac_reld_crit_qw, + input an_ac_reld_l1_dump, + input [0:3] an_ac_req_spare_ctrl_a1, // spare control bits from L2 + + // load/store credit control + input an_ac_flh2l2_gate, // Gate L1 Hit forwarding SPR config bit + input an_ac_req_ld_pop, // credit for a load (L2 can take a load command) + input an_ac_req_st_pop, // credit for a store (L2 can take a store command) + input an_ac_req_st_gather, // credit for a store due to L2 gathering of store commands + input [0:`THREADS-1] an_ac_sync_ack, + + //SCOM Satellite + input [0:3] an_ac_scom_sat_id, + input an_ac_scom_dch, + input an_ac_scom_cch, + output ac_an_scom_dch, + output ac_an_scom_cch, + + // FIR and Error Signals + output [0:`THREADS-1] ac_an_special_attn, + output [0:2] ac_an_checkstop, + output [0:2] ac_an_local_checkstop, + output [0:2] ac_an_recov_err, + output ac_an_trace_error, + output ac_an_livelock_active, + input an_ac_checkstop, + input [0:`THREADS-1] an_ac_external_mchk, + + // Perfmon Event Bus + output [0:4*`THREADS-1] ac_an_event_bus0, + output [0:4*`THREADS-1] ac_an_event_bus1, + + // Reset related + input an_ac_reset_1_complete, + input an_ac_reset_2_complete, + input an_ac_reset_3_complete, + input an_ac_reset_wd_complete, + + // Power Management + output [0:`THREADS-1] ac_an_pm_thread_running, + input [0:`THREADS-1] an_ac_pm_thread_stop, + input [0:`THREADS-1] an_ac_pm_fetch_halt, + output ac_an_power_managed, + output ac_an_rvwinkle_mode, + + // Clock, Test, and LCB Controls + input an_ac_gsd_test_enable_dc, + input an_ac_gsd_test_acmode_dc, + input an_ac_ccflush_dc, + input an_ac_ccenable_dc, + input an_ac_lbist_en_dc, + input an_ac_lbist_ip_dc, + input an_ac_lbist_ac_mode_dc, + input an_ac_scan_diag_dc, + input an_ac_scan_dis_dc_b, + + //Thold input to clock control macro + input [0:8] an_ac_scan_type_dc, + + // Pervasive + output ac_an_reset_1_request, + output ac_an_reset_2_request, + output ac_an_reset_3_request, + output ac_an_reset_wd_request, + input an_ac_lbist_ary_wrt_thru_dc, + input [0:`THREADS-1] an_ac_sleep_en, + input [0:`THREADS-1] an_ac_ext_interrupt, + input [0:`THREADS-1] an_ac_crit_interrupt, + input [0:`THREADS-1] an_ac_perf_interrupt, + input [0:`THREADS-1] an_ac_hang_pulse, + input an_ac_tb_update_enable, + input an_ac_tb_update_pulse, + input [0:3] an_ac_chipid_dc, + input [0:7] an_ac_coreid, + output [0:`THREADS-1] ac_an_machine_check, + input an_ac_debug_stop, + output [0:`THREADS-1] ac_an_debug_trigger, + input [0:`THREADS-1] an_ac_uncond_dbg_event, + output [0:31] ac_an_debug_bus, + output ac_an_coretrace_first_valid, // coretrace_ctrls[0] + output ac_an_coretrace_valid, // coretrace_ctrls[1] + output [0:1] ac_an_coretrace_type, // coretrace_ctrls[2:3] + + // L2 Outputs + output ac_an_req_pwr_token, // power token for command coming next cycle + output ac_an_req, // command request valid + output [64-`REAL_IFAR_WIDTH:63] ac_an_req_ra, // real address for request + output [0:5] ac_an_req_ttype, // command (transaction) type + output [0:2] ac_an_req_thread, // encoded thread ID + output ac_an_req_wimg_w, // write-through + output ac_an_req_wimg_i, // cache-inhibited + output ac_an_req_wimg_m, // memory coherence required + output ac_an_req_wimg_g, // guarded memory + output [0:3] ac_an_req_user_defined, // User Defined Bits + output [0:3] ac_an_req_spare_ctrl_a0, // Spare bits + output [0:4] ac_an_req_ld_core_tag, // load command tag (which load Q) + output [0:2] ac_an_req_ld_xfr_len, // transfer length for non-cacheable load + output [0:31] ac_an_st_byte_enbl, // byte enables for store data + output [0:255] ac_an_st_data, // store data + output ac_an_req_endian, // endian mode (0=big endian, 1=little endian) + output ac_an_st_data_pwr_token // store data power token +); + +c c0( + // generic map ( + // EXPAND_TYPE => EXPAND_TYPE + // ); + + .nclk(nclk), + .scan_in(scan_in), + .scan_out(scan_out), + + // Pervasive clock control + .an_ac_rtim_sl_thold_8(an_ac_rtim_sl_thold_8), + .an_ac_func_sl_thold_8(an_ac_func_sl_thold_8), + .an_ac_func_nsl_thold_8(an_ac_func_nsl_thold_8), + .an_ac_ary_nsl_thold_8(an_ac_ary_nsl_thold_8), + .an_ac_sg_8(an_ac_sg_8), + .an_ac_fce_8(an_ac_fce_8), + .an_ac_abst_scan_in(an_ac_abst_scan_in), + + // L2 STCX complete + .an_ac_stcx_complete(an_ac_stcx_complete), + .an_ac_stcx_pass(an_ac_stcx_pass), + + // ICBI ACK Interface + .an_ac_icbi_ack(an_ac_icbi_ack), + .an_ac_icbi_ack_thread(an_ac_icbi_ack_thread), + + // Back invalidate interface + .an_ac_back_inv(an_ac_back_inv), + .an_ac_back_inv_addr(an_ac_back_inv_addr), + .an_ac_back_inv_target(an_ac_back_inv_target), + .an_ac_back_inv_local(an_ac_back_inv_local), + .an_ac_back_inv_lbit(an_ac_back_inv_lbit), + .an_ac_back_inv_gs(an_ac_back_inv_gs), + .an_ac_back_inv_ind(an_ac_back_inv_ind), + .an_ac_back_inv_lpar_id(an_ac_back_inv_lpar_id), + .ac_an_back_inv_reject(ac_an_back_inv_reject), + .ac_an_lpar_id(ac_an_lpar_id), + + // L2 Reload Inputs + .an_ac_reld_data_vld(an_ac_reld_data_vld), + .an_ac_reld_core_tag(an_ac_reld_core_tag), + .an_ac_reld_data(an_ac_reld_data), + .an_ac_reld_qw(an_ac_reld_qw), + .an_ac_reld_ecc_err(an_ac_reld_ecc_err), + .an_ac_reld_ecc_err_ue(an_ac_reld_ecc_err_ue), + .an_ac_reld_data_coming(an_ac_reld_data_coming), + .an_ac_reld_ditc(an_ac_reld_ditc), + .an_ac_reld_crit_qw(an_ac_reld_crit_qw), + .an_ac_reld_l1_dump(an_ac_reld_l1_dump), + .an_ac_req_spare_ctrl_a1(an_ac_req_spare_ctrl_a1), + + // load/store credit control + .an_ac_flh2l2_gate(an_ac_flh2l2_gate), + .an_ac_req_ld_pop(an_ac_req_ld_pop), + .an_ac_req_st_pop(an_ac_req_st_pop), + .an_ac_req_st_gather(an_ac_req_st_gather), + .an_ac_sync_ack(an_ac_sync_ack), + .an_ac_pm_fetch_halt(an_ac_pm_fetch_halt), + + //SCOM Satellite + .an_ac_scom_sat_id(an_ac_scom_sat_id), + .an_ac_scom_dch(an_ac_scom_dch), + .an_ac_scom_cch(an_ac_scom_cch), + .ac_an_scom_dch(ac_an_scom_dch), + .ac_an_scom_cch(ac_an_scom_cch), + + // FIR and Error Signals + .ac_an_special_attn(ac_an_special_attn), + .ac_an_checkstop(ac_an_checkstop), + .ac_an_local_checkstop(ac_an_local_checkstop), + .ac_an_recov_err(ac_an_recov_err), + .ac_an_trace_error(ac_an_trace_error), + .ac_an_livelock_active(ac_an_livelock_active), + .an_ac_checkstop(an_ac_checkstop), + .an_ac_external_mchk(an_ac_external_mchk), + + // Perfmon Event Bus + .ac_an_event_bus0(ac_an_event_bus0), + .ac_an_event_bus1(ac_an_event_bus1), + + // Reset related + .an_ac_reset_1_complete(an_ac_reset_1_complete), + .an_ac_reset_2_complete(an_ac_reset_2_complete), + .an_ac_reset_3_complete(an_ac_reset_3_complete), + .an_ac_reset_wd_complete(an_ac_reset_wd_complete), + + // Power Management + .ac_an_pm_thread_running(ac_an_pm_thread_running), + .an_ac_pm_thread_stop(an_ac_pm_thread_stop), + .ac_an_power_managed(ac_an_power_managed), + .ac_an_rvwinkle_mode(ac_an_rvwinkle_mode), + + // Clock, Test, and LCB Controls + .an_ac_gsd_test_enable_dc(an_ac_gsd_test_enable_dc), + .an_ac_gsd_test_acmode_dc(an_ac_gsd_test_acmode_dc), + .an_ac_ccflush_dc(an_ac_ccflush_dc), + .an_ac_ccenable_dc(an_ac_ccenable_dc), + .an_ac_lbist_en_dc(an_ac_lbist_en_dc), + .an_ac_lbist_ip_dc(an_ac_lbist_ip_dc), + .an_ac_lbist_ac_mode_dc(an_ac_lbist_ac_mode_dc), + .an_ac_scan_diag_dc(an_ac_scan_diag_dc), + .an_ac_scan_dis_dc_b(an_ac_scan_dis_dc_b), + + //Thold input to clock control macro + .an_ac_scan_type_dc(an_ac_scan_type_dc), + + // Pervasive + .ac_an_reset_1_request(ac_an_reset_1_request), + .ac_an_reset_2_request(ac_an_reset_2_request), + .ac_an_reset_3_request(ac_an_reset_3_request), + .ac_an_reset_wd_request(ac_an_reset_wd_request), + .an_ac_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc), + .an_ac_reservation_vld(an_ac_reservation_vld), + .an_ac_sleep_en(an_ac_sleep_en), + .an_ac_ext_interrupt(an_ac_ext_interrupt), + .an_ac_crit_interrupt(an_ac_crit_interrupt), + .an_ac_perf_interrupt(an_ac_perf_interrupt), + .an_ac_hang_pulse(an_ac_hang_pulse), + .an_ac_tb_update_enable(an_ac_tb_update_enable), + .an_ac_tb_update_pulse(an_ac_tb_update_pulse), + .an_ac_chipid_dc(an_ac_chipid_dc), + .an_ac_coreid(an_ac_coreid), + .ac_an_machine_check(ac_an_machine_check), + .an_ac_debug_stop(an_ac_debug_stop), + .ac_an_debug_trigger(ac_an_debug_trigger), + .an_ac_uncond_dbg_event(an_ac_uncond_dbg_event), + + // L2 Outputs + .ac_an_req_pwr_token(ac_an_req_pwr_token), + .ac_an_req(ac_an_req), + .ac_an_req_ra(ac_an_req_ra), + .ac_an_req_ttype(ac_an_req_ttype), + .ac_an_req_thread(ac_an_req_thread), + .ac_an_req_wimg_w(ac_an_req_wimg_w), + .ac_an_req_wimg_i(ac_an_req_wimg_i), + .ac_an_req_wimg_m(ac_an_req_wimg_m), + .ac_an_req_wimg_g(ac_an_req_wimg_g), + .ac_an_req_user_defined(ac_an_req_user_defined), + .ac_an_req_spare_ctrl_a0(ac_an_req_spare_ctrl_a0), + .ac_an_req_ld_core_tag(ac_an_req_ld_core_tag), + .ac_an_req_ld_xfr_len(ac_an_req_ld_xfr_len), + .ac_an_st_byte_enbl(ac_an_st_byte_enbl), + .ac_an_st_data(ac_an_st_data), + .ac_an_req_endian(ac_an_req_endian), + .ac_an_st_data_pwr_token(ac_an_st_data_pwr_token) + ); + +initial begin + $dumpfile ("wtf-coco.vcd"); + // you can do it by levels and also by module so could prune down + $dumpvars; + // need to explicitly specify arrays for icarus + // guess not: $dumpvars cannot dump a vpiMemory + //$dumpvars(0, c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.buffer_data_q); + #1; +end + +// see if coco lets me risingedge() these +wire clk_1x, clk_2x, clk_4x, rst; + +assign clk_1x = nclk[0]; +assign clk_2x = nclk[2]; +assign clk_4x = nclk[3]; +assign rst = nclk[1]; + +endmodule \ No newline at end of file diff --git a/dev/sim/coco/makegtkw b/dev/sim/coco/makegtkw new file mode 100755 index 0000000..639a8e2 --- /dev/null +++ b/dev/sim/coco/makegtkw @@ -0,0 +1,310 @@ +#!/bin/python3 + +# problems: +# some parse error causes it to ignore filters AND not let you add them (can be caused from gui); changing order +# of traces fixes it - maybe problem with my trans filter? + +import sys +import os +import io +from dotmap import DotMap + +from vcd.gtkw import * + +gtkwFile = 'pyvcd.gtkw' +#fo = io.StringIO(gtkwFile) +fo = open(gtkwFile, 'w') +gtkw = GTKWSave(fo) + +base = 'cocotb_icarus.' +topIndicator = '!' #wtf never need this? +vectorNoBits = False +core = 0 + +# add zero and one signals to top level for use here +zero = 'an_ac_sg_8' + +filterPath = '../gtkwave/' +filterNull = filterPath + 'gtkf-nop.py' +filterValid = filterPath + 'gtkf-valid.py' +filterIBuf = filterPath + 'gtkf-ibuf.py' +filterPPC = filterPath + 'gtkf-ppc.py' +filterA2L2 = filterPath + 'gtkf-a2l2.py' +filterR64 = filterPath + 'gtkf-64R.py' + +# need to indicate if signal is 'threaded' (vector) to gen diff netlists for diff smt modes + + +# showVector should maybe be done by Combined that can take specific bits to use +class Signal(DotMap): + def __init__(self, name, alias=None, color=None, highlight=False, rjustify=False, datafmt='bin', extraflags=GTKWFlag(0), translateFile=None, translateProc=None, transactionProc=None, bits=None, showVector=False): + super().__init__() + if name[0] != topIndicator: + name = base + name + else: + name = name[1:] + self.name = name + self.bits = bits + self.alias = alias + self.color = color + self.highlight = highlight + self.rjustify = rjustify + self.datafmt = datafmt + self.extraflags = extraflags + self.translateFile = translateFile + self.translateProc = translateProc + self.transactionProc = transactionProc + self.showVector = showVector + + def add(self): + trace = self.name + bits = self.bits + if bits is not None: + if vectorNoBits: + trace = trace.split('[')[0] + if type(bits) is not list: + bits = [bits] + with gtkw.trace_bits(trace, showVector=self.showVector): + for i in range(len(bits)): + # for now - i guess highlight and filters might make sense + #gtkw.trace_bit(bits[i], trace, self.alias, self.color, self.datafmt, self.highlight, self.rjustify, self.extraflags, translate_filter_file=self.translateFile, translate_filter_proc=self.translateProc, transaction_filter_proc=self.transactionProc) + gtkw.trace_bit(bits[i], trace, self.alias, self.color) + + else: + gtkw.trace(trace, self.alias, self.color, self.datafmt, self.highlight, self.rjustify, self.extraflags, translate_filter_file=self.translateFile, translate_filter_proc=self.translateProc, transaction_filter_proc=self.transactionProc) + +class Combined(DotMap): + def __init__(self, name, traces, color=None, highlight=False, rjustify=False, datafmt='bin', extraflags=GTKWFlag(0), translateFile=None, translateProc=None, transactionProc=None): + super().__init__() + self.name = name + self.traces = traces + self.color = color + self.highlight = highlight + self.rjustify = rjustify + self.datafmt = datafmt + self.extraflags = extraflags + self.translateFile = translateFile + self.translateProc = translateProc + self.transactionProc = transactionProc + + def add(self): + trace = [] + for t in self.traces: + trace.append(t.name) + gtkw.trace(trace, self.name, self.color, self.datafmt, self.highlight, self.rjustify, self.extraflags, translate_filter_file=self.translateFile, translate_filter_proc=self.translateProc, transaction_filter_proc=self.transactionProc) + +class Group(DotMap): + def __init__(self, name, traces, closed=True, highlight=False): + super().__init__() + self.name = name + self.traces = traces + self.closed = closed + self.highlight = highlight + + def add(self): + if len(self.traces) > 0: + with gtkw.group(self.name, self.closed, self.highlight): + for j in range(len(self.traces)): + self.traces[j].add() + + def addCombined(self, alias, color=None, highlight=False, rjustify=False, datafmt='bin', extraflags=GTKWFlag(0), translateFile=None, translateProc=None, transactionProc=None): + trace = [] + for t in self.traces: + trace.append(t.name) + gtkw.trace(trace, alias, color, datafmt, highlight, rjustify, extraflags, translate_filter_file=translateFile, translate_filter_proc=translateProc, transaction_filter_proc=transactionProc) + +nodeMisc = Group('Misc', [ + Signal(f'nclk[0:5]', alias='reset', bits=1, showVector=False), + Signal(f'nclk[0:5]', alias='clk1x', bits=0, showVector=False), + Signal(f'nclk[0:5]', alias='clk2x', bits=2, showVector=False), + Signal(f'an_ac_pm_thread_stop[0]') + #Signal('ac_an_checkstop[0:2]'), +]) +#nodeMisc.add() +# until gtkwave has a tiny nested indicator... +for i in range(len(nodeMisc.traces)): + nodeMisc.traces[i].add() + +a2l2Req = Group('A2L2 Req', [ + Signal(f'ac_an_req'), + Signal(f'ac_an_req_endian'), + Signal(f'ac_an_req_ld_core_tag[0:4]'), + Signal(f'ac_an_req_ld_xfr_len[0:2]'), + Signal(f'ac_an_req_pwr_token'), + Signal(f'ac_an_req_ra[22:63]'), + Signal(f'ac_an_req_ttype[0:5]'), + Signal(f'ac_an_req_wimg_w'), + Signal(f'ac_an_req_wimg_i'), + Signal(f'ac_an_req_wimg_m'), + Signal(f'ac_an_req_wimg_g') +]) + +a2l2Rsp = Group('A2L2 Rsp', [ + Signal(f'an_ac_reld_data_coming'), + Signal(f'an_ac_reld_data_vld'), + Signal(f'an_ac_reld_qw[58:59]', datafmt='dec', rjustify=True), + Signal(f'an_ac_reld_crit_qw'), + Signal(f'an_ac_reld_data[0:127]', datafmt='hex') +]) + +a2l2Misc = Group('A2L2 Misc', [ + Signal(f'ac_an_req_pwr_token'), + Signal(f'an_ac_req_ld_pop'), + Signal(f'c{core}.lq0.lsq.arb.load_cred_cnt_q[0:4]', datafmt='dec'), + Signal(f'an_ac_req_st_pop'), + Signal(f'an_ac_req_st_gather'), + Signal(f'c{core}.lq0.lsq.arb.store_cred_cnt_q[0:5]', datafmt='dec'), + Signal(f'an_ac_reservation_vld'), + Signal(f'an_ac_stcx_complete'), + Signal(f'an_ac_stcx_pass'), + Signal(f'an_ac_sync_ack'), + Signal(f'an_ac_icbi_ack') +]) + +ibuf = Group('IBuf', [ + Signal(f'c{core}.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.buffer_valid_q[0:15]', datafmt='hex'), + Signal(f'c{core}.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.buffer_head_q[0:15]', datafmt='hex') +]) +for i in range(16): + ibuf.traces.append( + Signal(f'c{core}.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[{i}].q[0:109]',translateProc=filterIBuf) + ) + +#ibuf2 = Combined(f'IBuf[{i}]', +# [ +# (Signal(f'c{core}.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.buffer_valid_q[0:15]', bits=[{i}]), +# Signal(f'c{core}.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[{i}].q[0:109]')) for i in range(16) +# ] +#) + + +pipe = [] + +pipe.append(Combined('iu_xu_nia', [ + Signal(f'c{core}.iuq0.iu_xu_t0_nia[0:61]'), + Signal(zero), # word-align + Signal(zero) +], datafmt='hex')) + +pipe.append(ibuf) +#pipe.append(ibuf2) + +for i in range(2): + pipe.append(Signal(f'c{core}.iu_rv_iu6_t0_i{i}_instr[0:31]', datafmt='hex', color=GTKWColor.green, translateProc=filterPPC)) + +# match cycle with instr +for i in range(2): + pipe.append(Combined(f'iu6_i{i}_itag_dispatched', [ + Signal(f'c{core}.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i{i}_dispatched_d'), + Signal(zero), # pad missing bit 0 + Signal(f'c{core}.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.rn_cp_iu6_i{i}_itag[1:6]') + ], color=GTKWColor.green, translateProc=filterValid)) + +#for i in range(2): +# pipe.append(Combined(f'iu6_i{i}_itag', [ +# Signal(f'c{core}.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i{i}_valop_q'), +# Signal(zero), # pad missing bit 0 +# Signal(f'c{core}.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i{i}_itag_q[1:6]') +# ], color=GTKWColor.blue, translateProc=filterValid)) + +for i in range(2): + pipe.append(Combined(f'iu6_i{i}_itag_dispatched', [ + Signal(f'c{core}.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i{i}_dispatched_q'), + Signal(zero), # pad missing bit 0 + Signal(f'c{core}.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i{i}_itag_q[1:6]') + ], color=GTKWColor.green, translateProc=filterValid)) + +# eventually arrange all by ex +for ex in range(1): + for rv in range(2): + for fx in range(2): + for src in range(1,4): + pipe.append(Combined(f'rv0_fx{fx}_ex{ex}_s{src}', [ + Signal(f'c{core}.rv_fx{fx}_ex{ex}_s{src}_v'), + Signal(f'c{core}.rv0.rf_byp.fx{fx}_ex{ex}_s{src}_itag_q[0:6]') + ], color=GTKWColor.blue, translateProc=filterValid)) + +for ex in range(6): + for fx in range(2): + pipe.append(Combined(f'fx{fx}_ex{ex}', [ + Signal(f'c{core}.xu0.xu{fx}.dec.ex{ex}_val_q[0]'), + Signal(f'c{core}.xu0.xu{fx}.dec.ex{ex}_itag_q[0:6]') + ], color=GTKWColor.blue, translateProc=filterValid)) + +for ex in range(4): + pipe.append(Combined(f'br_ex{ex}_bta', [ + Signal(f'c{core}.xu0.xu0.br.ex{ex}_bta_val_q'), + Signal(f'c{core}.xu0.xu0.br.ex{ex}_pred_bta_q[42:61]'), + Signal(zero), # word-align + Signal(zero) + ], color=GTKWColor.blue, translateProc=filterValid)) + + +for i in range(2): + pipe.append(Combined(f'cp2 i{i}_completed_itag', [ + Signal(f'c{core}.iu_lq_i{i}_completed'), + Signal(f'c{core}.iu_lq_t0_i{i}_completed_itag[0:6]'), + ], color=GTKWColor.green, translateProc=filterValid)) + +for i in range(2): + pipe.append(Combined(f'cp2 i{i}_completed_ifar', [ + Signal(f'c{core}.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.cp2_i{i}_complete_q'), + Signal(f'c{core}.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i{i}_ifar[42:61]'), + Signal(zero), # word-align + Signal(zero) + ], color=GTKWColor.green, translateProc=filterValid)) + +# or add more stuff and make transaction +for i in range(2): + pipe.append(Combined(f'cp2 i{i}_completed_itag/ifar', [ + Signal(f'c{core}.iu_lq_i{i}_completed'), + Signal(zero), # pad itag + Signal(f'c{core}.iu_lq_t0_i{i}_completed_itag[0:6]'), + Signal(zero), # pad ifar + Signal(zero), # pad + Signal(f'c{core}.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i{i}_ifar[42:61]'), + Signal(zero), # word-align + Signal(zero) + ], color=GTKWColor.green, translateProc=filterValid)) + + +pipe = Group('Pipe', pipe, closed=False) + + +threads = 1 +sprs = [None] * threads +for i in range(threads): + sprs[i] = Group(f't{i} SPR', [ + Signal(f'c{core}.xu0.spr.threads.thread[{i}].xu_spr_tspr.srr0_do[0:64]', datafmt='bin', translateProc=filterR64), + Signal(f'c{core}.xu0.spr.threads.thread[{i}].xu_spr_tspr.srr1_do[0:64]', datafmt='bin', translateProc=filterR64) + ], closed=False) + +a2l2Req.add() +a2l2Rsp.add() +a2l2Misc.add() + +# move this after and it works +#a2l2Req.addCombined('A2L2 Trans (Req)', transactionProc=filterA2L2) + +pipe.add() +sprs[0].add() + +a2l2Req.addCombined('A2L2 Trans (Req)', transactionProc=filterA2L2) + +#for i in range(len(groups)): +# groups[i].add() + + +#gtkw.comment('Test pyvcd') +#gtkw.savefile(gtkwFile) +#gtkw.zoom_markers() +#gtkw.pos() + +gtkw.sst_expanded(True) +gtkw.size(3000, 1500) +gtkw.treeopen(base) +gtkw.signals_width(600) +gtkw.pattern_trace(True) + + +fo.close() \ No newline at end of file diff --git a/dev/sim/coco/pyvcd.gtkw b/dev/sim/coco/pyvcd.gtkw new file mode 100755 index 0000000..8effc00 --- /dev/null +++ b/dev/sim/coco/pyvcd.gtkw @@ -0,0 +1,255 @@ +@800200 +- +@28 ++{reset} (1)cocotb_icarus.nclk[0:5] +@1001200 +-group_end +@800200 +- +@28 ++{clk1x} (0)cocotb_icarus.nclk[0:5] +@1001200 +-group_end +@800200 +- +@28 ++{clk2x} (2)cocotb_icarus.nclk[0:5] +@1001200 +-group_end +@8 +cocotb_icarus.an_ac_pm_thread_stop[0] +@c00200 +-A2L2 Req +@8 +cocotb_icarus.ac_an_req +cocotb_icarus.ac_an_req_endian +cocotb_icarus.ac_an_req_ld_core_tag[0:4] +cocotb_icarus.ac_an_req_ld_xfr_len[0:2] +cocotb_icarus.ac_an_req_pwr_token +cocotb_icarus.ac_an_req_ra[22:63] +cocotb_icarus.ac_an_req_ttype[0:5] +cocotb_icarus.ac_an_req_wimg_w +cocotb_icarus.ac_an_req_wimg_i +cocotb_icarus.ac_an_req_wimg_m +cocotb_icarus.ac_an_req_wimg_g +@1401200 +-A2L2 Req +@c00200 +-A2L2 Rsp +@8 +cocotb_icarus.an_ac_reld_data_coming +cocotb_icarus.an_ac_reld_data_vld +@24 +cocotb_icarus.an_ac_reld_qw[58:59] +@8 +cocotb_icarus.an_ac_reld_crit_qw +@2 +cocotb_icarus.an_ac_reld_data[0:127] +@1401200 +-A2L2 Rsp +@c00200 +-A2L2 Misc +@8 +cocotb_icarus.ac_an_req_pwr_token +cocotb_icarus.an_ac_req_ld_pop +@4 +cocotb_icarus.c0.lq0.lsq.arb.load_cred_cnt_q[0:4] +@8 +cocotb_icarus.an_ac_req_st_pop +cocotb_icarus.an_ac_req_st_gather +@4 +cocotb_icarus.c0.lq0.lsq.arb.store_cred_cnt_q[0:5] +@8 +cocotb_icarus.an_ac_reservation_vld +cocotb_icarus.an_ac_stcx_complete +cocotb_icarus.an_ac_stcx_pass +cocotb_icarus.an_ac_sync_ack +cocotb_icarus.an_ac_icbi_ack +@1401200 +-A2L2 Misc +@800200 +-Pipe +@2 +#{iu_xu_nia} (0)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (1)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (2)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (3)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (4)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (5)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (6)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (7)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (8)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (9)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (10)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (11)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (12)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (13)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (14)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (15)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (16)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (17)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (18)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (19)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (20)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (21)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (22)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (23)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (24)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (25)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (26)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (27)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (28)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (29)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (30)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (31)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (32)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (33)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (34)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (35)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (36)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (37)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (38)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (39)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (40)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (41)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (42)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (43)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (44)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (45)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (46)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (47)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (48)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (49)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (50)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (51)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (52)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (53)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (54)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (55)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (56)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (57)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (58)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (59)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (60)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] (61)cocotb_icarus.c0.iuq0.iu_xu_t0_nia[0:61] cocotb_icarus.an_ac_sg_8 cocotb_icarus.an_ac_sg_8 +@c00200 +-IBuf +@2 +cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.buffer_valid_q[0:15] +cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.buffer_head_q[0:15] +@4008 +^>1 ../gtkwave/gtkf-ibuf.py +cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[0].q[0:109] +^>1 ../gtkwave/gtkf-ibuf.py +cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[1].q[0:109] +^>1 ../gtkwave/gtkf-ibuf.py +cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[2].q[0:109] +^>1 ../gtkwave/gtkf-ibuf.py +cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[3].q[0:109] +^>1 ../gtkwave/gtkf-ibuf.py +cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[4].q[0:109] +^>1 ../gtkwave/gtkf-ibuf.py +cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[5].q[0:109] +^>1 ../gtkwave/gtkf-ibuf.py +cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[6].q[0:109] +^>1 ../gtkwave/gtkf-ibuf.py +cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[7].q[0:109] +^>1 ../gtkwave/gtkf-ibuf.py +cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[8].q[0:109] +^>1 ../gtkwave/gtkf-ibuf.py +cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[9].q[0:109] +^>1 ../gtkwave/gtkf-ibuf.py +cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[10].q[0:109] +^>1 ../gtkwave/gtkf-ibuf.py +cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[11].q[0:109] +^>1 ../gtkwave/gtkf-ibuf.py +cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[12].q[0:109] +^>1 ../gtkwave/gtkf-ibuf.py +cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[13].q[0:109] +^>1 ../gtkwave/gtkf-ibuf.py +cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[14].q[0:109] +^>1 ../gtkwave/gtkf-ibuf.py +cocotb_icarus.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.ibuf[15].q[0:109] +@1401200 +-IBuf +@4002 +[color] 4 +^>2 ../gtkwave/gtkf-ppc.py +cocotb_icarus.c0.iu_rv_iu6_t0_i0_instr[0:31] +[color] 4 +^>2 ../gtkwave/gtkf-ppc.py +cocotb_icarus.c0.iu_rv_iu6_t0_i1_instr[0:31] +@4008 +[color] 4 +^>3 ../gtkwave/gtkf-valid.py +#{iu6_i0_itag_dispatched} cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i0_dispatched_d cocotb_icarus.an_ac_sg_8 (0)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.rn_cp_iu6_i0_itag[1:6] (1)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.rn_cp_iu6_i0_itag[1:6] (2)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.rn_cp_iu6_i0_itag[1:6] (3)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.rn_cp_iu6_i0_itag[1:6] (4)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.rn_cp_iu6_i0_itag[1:6] (5)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.rn_cp_iu6_i0_itag[1:6] +[color] 4 +^>3 ../gtkwave/gtkf-valid.py +#{iu6_i1_itag_dispatched} cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i1_dispatched_d cocotb_icarus.an_ac_sg_8 (0)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.rn_cp_iu6_i1_itag[1:6] (1)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.rn_cp_iu6_i1_itag[1:6] (2)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.rn_cp_iu6_i1_itag[1:6] (3)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.rn_cp_iu6_i1_itag[1:6] (4)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.rn_cp_iu6_i1_itag[1:6] (5)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.rn_cp_iu6_i1_itag[1:6] +[color] 4 +^>3 ../gtkwave/gtkf-valid.py +#{iu6_i0_itag_dispatched} cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i0_dispatched_q cocotb_icarus.an_ac_sg_8 (0)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i0_itag_q[1:6] (1)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i0_itag_q[1:6] (2)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i0_itag_q[1:6] (3)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i0_itag_q[1:6] (4)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i0_itag_q[1:6] (5)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i0_itag_q[1:6] +[color] 4 +^>3 ../gtkwave/gtkf-valid.py +#{iu6_i1_itag_dispatched} cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i1_dispatched_q cocotb_icarus.an_ac_sg_8 (0)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i1_itag_q[1:6] (1)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i1_itag_q[1:6] (2)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i1_itag_q[1:6] (3)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i1_itag_q[1:6] (4)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i1_itag_q[1:6] (5)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.iu6_i1_itag_q[1:6] +[color] 5 +^>3 ../gtkwave/gtkf-valid.py +#{rv0_fx0_ex0_s1} cocotb_icarus.c0.rv_fx0_ex0_s1_v (0)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s1_itag_q[0:6] (1)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s1_itag_q[0:6] (2)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s1_itag_q[0:6] (3)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s1_itag_q[0:6] (4)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s1_itag_q[0:6] (5)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s1_itag_q[0:6] (6)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s1_itag_q[0:6] +[color] 5 +^>3 ../gtkwave/gtkf-valid.py +#{rv0_fx0_ex0_s2} cocotb_icarus.c0.rv_fx0_ex0_s2_v (0)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s2_itag_q[0:6] (1)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s2_itag_q[0:6] (2)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s2_itag_q[0:6] (3)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s2_itag_q[0:6] (4)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s2_itag_q[0:6] (5)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s2_itag_q[0:6] (6)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s2_itag_q[0:6] +[color] 5 +^>3 ../gtkwave/gtkf-valid.py +#{rv0_fx0_ex0_s3} cocotb_icarus.c0.rv_fx0_ex0_s3_v (0)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s3_itag_q[0:6] (1)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s3_itag_q[0:6] (2)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s3_itag_q[0:6] (3)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s3_itag_q[0:6] (4)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s3_itag_q[0:6] (5)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s3_itag_q[0:6] (6)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s3_itag_q[0:6] +[color] 5 +^>3 ../gtkwave/gtkf-valid.py +#{rv0_fx1_ex0_s1} cocotb_icarus.c0.rv_fx1_ex0_s1_v (0)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s1_itag_q[0:6] (1)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s1_itag_q[0:6] (2)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s1_itag_q[0:6] (3)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s1_itag_q[0:6] (4)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s1_itag_q[0:6] (5)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s1_itag_q[0:6] (6)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s1_itag_q[0:6] +[color] 5 +^>3 ../gtkwave/gtkf-valid.py +#{rv0_fx1_ex0_s2} cocotb_icarus.c0.rv_fx1_ex0_s2_v (0)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s2_itag_q[0:6] (1)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s2_itag_q[0:6] (2)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s2_itag_q[0:6] (3)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s2_itag_q[0:6] (4)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s2_itag_q[0:6] (5)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s2_itag_q[0:6] (6)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s2_itag_q[0:6] +[color] 5 +^>3 ../gtkwave/gtkf-valid.py +#{rv0_fx1_ex0_s3} cocotb_icarus.c0.rv_fx1_ex0_s3_v (0)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s3_itag_q[0:6] (1)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s3_itag_q[0:6] (2)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s3_itag_q[0:6] (3)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s3_itag_q[0:6] (4)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s3_itag_q[0:6] (5)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s3_itag_q[0:6] (6)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s3_itag_q[0:6] +[color] 5 +^>3 ../gtkwave/gtkf-valid.py +#{rv0_fx0_ex0_s1} cocotb_icarus.c0.rv_fx0_ex0_s1_v (0)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s1_itag_q[0:6] (1)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s1_itag_q[0:6] (2)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s1_itag_q[0:6] (3)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s1_itag_q[0:6] (4)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s1_itag_q[0:6] (5)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s1_itag_q[0:6] (6)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s1_itag_q[0:6] +[color] 5 +^>3 ../gtkwave/gtkf-valid.py +#{rv0_fx0_ex0_s2} cocotb_icarus.c0.rv_fx0_ex0_s2_v (0)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s2_itag_q[0:6] (1)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s2_itag_q[0:6] (2)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s2_itag_q[0:6] (3)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s2_itag_q[0:6] (4)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s2_itag_q[0:6] (5)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s2_itag_q[0:6] (6)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s2_itag_q[0:6] +[color] 5 +^>3 ../gtkwave/gtkf-valid.py +#{rv0_fx0_ex0_s3} cocotb_icarus.c0.rv_fx0_ex0_s3_v (0)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s3_itag_q[0:6] (1)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s3_itag_q[0:6] (2)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s3_itag_q[0:6] (3)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s3_itag_q[0:6] (4)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s3_itag_q[0:6] (5)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s3_itag_q[0:6] (6)cocotb_icarus.c0.rv0.rf_byp.fx0_ex0_s3_itag_q[0:6] +[color] 5 +^>3 ../gtkwave/gtkf-valid.py +#{rv0_fx1_ex0_s1} cocotb_icarus.c0.rv_fx1_ex0_s1_v (0)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s1_itag_q[0:6] (1)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s1_itag_q[0:6] (2)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s1_itag_q[0:6] (3)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s1_itag_q[0:6] (4)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s1_itag_q[0:6] (5)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s1_itag_q[0:6] (6)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s1_itag_q[0:6] +[color] 5 +^>3 ../gtkwave/gtkf-valid.py +#{rv0_fx1_ex0_s2} cocotb_icarus.c0.rv_fx1_ex0_s2_v (0)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s2_itag_q[0:6] (1)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s2_itag_q[0:6] (2)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s2_itag_q[0:6] (3)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s2_itag_q[0:6] (4)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s2_itag_q[0:6] (5)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s2_itag_q[0:6] (6)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s2_itag_q[0:6] +[color] 5 +^>3 ../gtkwave/gtkf-valid.py +#{rv0_fx1_ex0_s3} cocotb_icarus.c0.rv_fx1_ex0_s3_v (0)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s3_itag_q[0:6] (1)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s3_itag_q[0:6] (2)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s3_itag_q[0:6] (3)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s3_itag_q[0:6] (4)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s3_itag_q[0:6] (5)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s3_itag_q[0:6] (6)cocotb_icarus.c0.rv0.rf_byp.fx1_ex0_s3_itag_q[0:6] +[color] 5 +^>3 ../gtkwave/gtkf-valid.py +#{fx0_ex0} (bits)cocotb_icarus.c0.xu0.xu0.dec.ex0_val_q[0] (0)cocotb_icarus.c0.xu0.xu0.dec.ex0_itag_q[0:6] (1)cocotb_icarus.c0.xu0.xu0.dec.ex0_itag_q[0:6] (2)cocotb_icarus.c0.xu0.xu0.dec.ex0_itag_q[0:6] (3)cocotb_icarus.c0.xu0.xu0.dec.ex0_itag_q[0:6] (4)cocotb_icarus.c0.xu0.xu0.dec.ex0_itag_q[0:6] (5)cocotb_icarus.c0.xu0.xu0.dec.ex0_itag_q[0:6] (6)cocotb_icarus.c0.xu0.xu0.dec.ex0_itag_q[0:6] +[color] 5 +^>3 ../gtkwave/gtkf-valid.py +#{fx1_ex0} (bits)cocotb_icarus.c0.xu0.xu1.dec.ex0_val_q[0] (0)cocotb_icarus.c0.xu0.xu1.dec.ex0_itag_q[0:6] (1)cocotb_icarus.c0.xu0.xu1.dec.ex0_itag_q[0:6] (2)cocotb_icarus.c0.xu0.xu1.dec.ex0_itag_q[0:6] (3)cocotb_icarus.c0.xu0.xu1.dec.ex0_itag_q[0:6] (4)cocotb_icarus.c0.xu0.xu1.dec.ex0_itag_q[0:6] (5)cocotb_icarus.c0.xu0.xu1.dec.ex0_itag_q[0:6] (6)cocotb_icarus.c0.xu0.xu1.dec.ex0_itag_q[0:6] +[color] 5 +^>3 ../gtkwave/gtkf-valid.py +#{fx0_ex1} (bits)cocotb_icarus.c0.xu0.xu0.dec.ex1_val_q[0] (0)cocotb_icarus.c0.xu0.xu0.dec.ex1_itag_q[0:6] (1)cocotb_icarus.c0.xu0.xu0.dec.ex1_itag_q[0:6] (2)cocotb_icarus.c0.xu0.xu0.dec.ex1_itag_q[0:6] (3)cocotb_icarus.c0.xu0.xu0.dec.ex1_itag_q[0:6] (4)cocotb_icarus.c0.xu0.xu0.dec.ex1_itag_q[0:6] (5)cocotb_icarus.c0.xu0.xu0.dec.ex1_itag_q[0:6] (6)cocotb_icarus.c0.xu0.xu0.dec.ex1_itag_q[0:6] +[color] 5 +^>3 ../gtkwave/gtkf-valid.py +#{fx1_ex1} (bits)cocotb_icarus.c0.xu0.xu1.dec.ex1_val_q[0] (0)cocotb_icarus.c0.xu0.xu1.dec.ex1_itag_q[0:6] (1)cocotb_icarus.c0.xu0.xu1.dec.ex1_itag_q[0:6] (2)cocotb_icarus.c0.xu0.xu1.dec.ex1_itag_q[0:6] (3)cocotb_icarus.c0.xu0.xu1.dec.ex1_itag_q[0:6] (4)cocotb_icarus.c0.xu0.xu1.dec.ex1_itag_q[0:6] (5)cocotb_icarus.c0.xu0.xu1.dec.ex1_itag_q[0:6] (6)cocotb_icarus.c0.xu0.xu1.dec.ex1_itag_q[0:6] +[color] 5 +^>3 ../gtkwave/gtkf-valid.py +#{fx0_ex2} (bits)cocotb_icarus.c0.xu0.xu0.dec.ex2_val_q[0] (0)cocotb_icarus.c0.xu0.xu0.dec.ex2_itag_q[0:6] (1)cocotb_icarus.c0.xu0.xu0.dec.ex2_itag_q[0:6] (2)cocotb_icarus.c0.xu0.xu0.dec.ex2_itag_q[0:6] (3)cocotb_icarus.c0.xu0.xu0.dec.ex2_itag_q[0:6] (4)cocotb_icarus.c0.xu0.xu0.dec.ex2_itag_q[0:6] (5)cocotb_icarus.c0.xu0.xu0.dec.ex2_itag_q[0:6] (6)cocotb_icarus.c0.xu0.xu0.dec.ex2_itag_q[0:6] +[color] 5 +^>3 ../gtkwave/gtkf-valid.py +#{fx1_ex2} (bits)cocotb_icarus.c0.xu0.xu1.dec.ex2_val_q[0] (0)cocotb_icarus.c0.xu0.xu1.dec.ex2_itag_q[0:6] (1)cocotb_icarus.c0.xu0.xu1.dec.ex2_itag_q[0:6] (2)cocotb_icarus.c0.xu0.xu1.dec.ex2_itag_q[0:6] (3)cocotb_icarus.c0.xu0.xu1.dec.ex2_itag_q[0:6] (4)cocotb_icarus.c0.xu0.xu1.dec.ex2_itag_q[0:6] (5)cocotb_icarus.c0.xu0.xu1.dec.ex2_itag_q[0:6] (6)cocotb_icarus.c0.xu0.xu1.dec.ex2_itag_q[0:6] +[color] 5 +^>3 ../gtkwave/gtkf-valid.py +#{fx0_ex3} (bits)cocotb_icarus.c0.xu0.xu0.dec.ex3_val_q[0] (0)cocotb_icarus.c0.xu0.xu0.dec.ex3_itag_q[0:6] (1)cocotb_icarus.c0.xu0.xu0.dec.ex3_itag_q[0:6] (2)cocotb_icarus.c0.xu0.xu0.dec.ex3_itag_q[0:6] (3)cocotb_icarus.c0.xu0.xu0.dec.ex3_itag_q[0:6] (4)cocotb_icarus.c0.xu0.xu0.dec.ex3_itag_q[0:6] (5)cocotb_icarus.c0.xu0.xu0.dec.ex3_itag_q[0:6] (6)cocotb_icarus.c0.xu0.xu0.dec.ex3_itag_q[0:6] +[color] 5 +^>3 ../gtkwave/gtkf-valid.py +#{fx1_ex3} (bits)cocotb_icarus.c0.xu0.xu1.dec.ex3_val_q[0] (0)cocotb_icarus.c0.xu0.xu1.dec.ex3_itag_q[0:6] (1)cocotb_icarus.c0.xu0.xu1.dec.ex3_itag_q[0:6] (2)cocotb_icarus.c0.xu0.xu1.dec.ex3_itag_q[0:6] (3)cocotb_icarus.c0.xu0.xu1.dec.ex3_itag_q[0:6] (4)cocotb_icarus.c0.xu0.xu1.dec.ex3_itag_q[0:6] (5)cocotb_icarus.c0.xu0.xu1.dec.ex3_itag_q[0:6] (6)cocotb_icarus.c0.xu0.xu1.dec.ex3_itag_q[0:6] +[color] 5 +^>3 ../gtkwave/gtkf-valid.py +#{fx0_ex4} (bits)cocotb_icarus.c0.xu0.xu0.dec.ex4_val_q[0] (0)cocotb_icarus.c0.xu0.xu0.dec.ex4_itag_q[0:6] (1)cocotb_icarus.c0.xu0.xu0.dec.ex4_itag_q[0:6] (2)cocotb_icarus.c0.xu0.xu0.dec.ex4_itag_q[0:6] (3)cocotb_icarus.c0.xu0.xu0.dec.ex4_itag_q[0:6] (4)cocotb_icarus.c0.xu0.xu0.dec.ex4_itag_q[0:6] (5)cocotb_icarus.c0.xu0.xu0.dec.ex4_itag_q[0:6] (6)cocotb_icarus.c0.xu0.xu0.dec.ex4_itag_q[0:6] +[color] 5 +^>3 ../gtkwave/gtkf-valid.py +#{fx1_ex4} (bits)cocotb_icarus.c0.xu0.xu1.dec.ex4_val_q[0] (0)cocotb_icarus.c0.xu0.xu1.dec.ex4_itag_q[0:6] (1)cocotb_icarus.c0.xu0.xu1.dec.ex4_itag_q[0:6] (2)cocotb_icarus.c0.xu0.xu1.dec.ex4_itag_q[0:6] (3)cocotb_icarus.c0.xu0.xu1.dec.ex4_itag_q[0:6] (4)cocotb_icarus.c0.xu0.xu1.dec.ex4_itag_q[0:6] (5)cocotb_icarus.c0.xu0.xu1.dec.ex4_itag_q[0:6] (6)cocotb_icarus.c0.xu0.xu1.dec.ex4_itag_q[0:6] +[color] 5 +^>3 ../gtkwave/gtkf-valid.py +#{fx0_ex5} (bits)cocotb_icarus.c0.xu0.xu0.dec.ex5_val_q[0] (0)cocotb_icarus.c0.xu0.xu0.dec.ex5_itag_q[0:6] (1)cocotb_icarus.c0.xu0.xu0.dec.ex5_itag_q[0:6] (2)cocotb_icarus.c0.xu0.xu0.dec.ex5_itag_q[0:6] (3)cocotb_icarus.c0.xu0.xu0.dec.ex5_itag_q[0:6] (4)cocotb_icarus.c0.xu0.xu0.dec.ex5_itag_q[0:6] (5)cocotb_icarus.c0.xu0.xu0.dec.ex5_itag_q[0:6] (6)cocotb_icarus.c0.xu0.xu0.dec.ex5_itag_q[0:6] +[color] 5 +^>3 ../gtkwave/gtkf-valid.py +#{fx1_ex5} (bits)cocotb_icarus.c0.xu0.xu1.dec.ex5_val_q[0] (0)cocotb_icarus.c0.xu0.xu1.dec.ex5_itag_q[0:6] (1)cocotb_icarus.c0.xu0.xu1.dec.ex5_itag_q[0:6] (2)cocotb_icarus.c0.xu0.xu1.dec.ex5_itag_q[0:6] (3)cocotb_icarus.c0.xu0.xu1.dec.ex5_itag_q[0:6] (4)cocotb_icarus.c0.xu0.xu1.dec.ex5_itag_q[0:6] (5)cocotb_icarus.c0.xu0.xu1.dec.ex5_itag_q[0:6] (6)cocotb_icarus.c0.xu0.xu1.dec.ex5_itag_q[0:6] +[color] 5 +^>3 ../gtkwave/gtkf-valid.py +#{br_ex0_bta} cocotb_icarus.c0.xu0.xu0.br.ex0_bta_val_q (0)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (1)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (2)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (3)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (4)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (5)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (6)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (7)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (8)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (9)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (10)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (11)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (12)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (13)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (14)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (15)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (16)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (17)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (18)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] (19)cocotb_icarus.c0.xu0.xu0.br.ex0_pred_bta_q[42:61] cocotb_icarus.an_ac_sg_8 cocotb_icarus.an_ac_sg_8 +[color] 5 +^>3 ../gtkwave/gtkf-valid.py +#{br_ex1_bta} cocotb_icarus.c0.xu0.xu0.br.ex1_bta_val_q (0)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (1)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (2)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (3)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (4)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (5)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (6)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (7)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (8)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (9)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (10)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (11)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (12)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (13)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (14)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (15)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (16)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (17)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (18)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] (19)cocotb_icarus.c0.xu0.xu0.br.ex1_pred_bta_q[42:61] cocotb_icarus.an_ac_sg_8 cocotb_icarus.an_ac_sg_8 +[color] 5 +^>3 ../gtkwave/gtkf-valid.py +#{br_ex2_bta} cocotb_icarus.c0.xu0.xu0.br.ex2_bta_val_q (0)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (1)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (2)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (3)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (4)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (5)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (6)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (7)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (8)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (9)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (10)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (11)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (12)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (13)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (14)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (15)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (16)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (17)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (18)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] (19)cocotb_icarus.c0.xu0.xu0.br.ex2_pred_bta_q[42:61] cocotb_icarus.an_ac_sg_8 cocotb_icarus.an_ac_sg_8 +[color] 5 +^>3 ../gtkwave/gtkf-valid.py +#{br_ex3_bta} cocotb_icarus.c0.xu0.xu0.br.ex3_bta_val_q (0)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (1)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (2)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (3)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (4)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (5)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (6)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (7)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (8)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (9)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (10)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (11)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (12)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (13)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (14)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (15)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (16)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (17)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (18)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] (19)cocotb_icarus.c0.xu0.xu0.br.ex3_pred_bta_q[42:61] cocotb_icarus.an_ac_sg_8 cocotb_icarus.an_ac_sg_8 +[color] 4 +^>3 ../gtkwave/gtkf-valid.py +#{cp2 i0_completed_itag} cocotb_icarus.c0.iu_lq_i0_completed (0)cocotb_icarus.c0.iu_lq_t0_i0_completed_itag[0:6] (1)cocotb_icarus.c0.iu_lq_t0_i0_completed_itag[0:6] (2)cocotb_icarus.c0.iu_lq_t0_i0_completed_itag[0:6] (3)cocotb_icarus.c0.iu_lq_t0_i0_completed_itag[0:6] (4)cocotb_icarus.c0.iu_lq_t0_i0_completed_itag[0:6] (5)cocotb_icarus.c0.iu_lq_t0_i0_completed_itag[0:6] (6)cocotb_icarus.c0.iu_lq_t0_i0_completed_itag[0:6] +[color] 4 +^>3 ../gtkwave/gtkf-valid.py +#{cp2 i1_completed_itag} cocotb_icarus.c0.iu_lq_i1_completed (0)cocotb_icarus.c0.iu_lq_t0_i1_completed_itag[0:6] (1)cocotb_icarus.c0.iu_lq_t0_i1_completed_itag[0:6] (2)cocotb_icarus.c0.iu_lq_t0_i1_completed_itag[0:6] (3)cocotb_icarus.c0.iu_lq_t0_i1_completed_itag[0:6] (4)cocotb_icarus.c0.iu_lq_t0_i1_completed_itag[0:6] (5)cocotb_icarus.c0.iu_lq_t0_i1_completed_itag[0:6] (6)cocotb_icarus.c0.iu_lq_t0_i1_completed_itag[0:6] +[color] 4 +^>3 ../gtkwave/gtkf-valid.py +#{cp2 i0_completed_ifar} cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.cp2_i0_complete_q (0)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (1)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (2)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (3)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (4)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (5)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (6)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (7)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (8)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (9)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (10)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (11)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (12)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (13)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (14)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (15)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (16)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (17)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (18)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (19)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] cocotb_icarus.an_ac_sg_8 cocotb_icarus.an_ac_sg_8 +[color] 4 +^>3 ../gtkwave/gtkf-valid.py +#{cp2 i1_completed_ifar} cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.cp2_i1_complete_q (0)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (1)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (2)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (3)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (4)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (5)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (6)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (7)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (8)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (9)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (10)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (11)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (12)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (13)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (14)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (15)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (16)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (17)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (18)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (19)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] cocotb_icarus.an_ac_sg_8 cocotb_icarus.an_ac_sg_8 +[color] 4 +^>3 ../gtkwave/gtkf-valid.py +#{cp2 i0_completed_itag/ifar} cocotb_icarus.c0.iu_lq_i0_completed cocotb_icarus.an_ac_sg_8 (0)cocotb_icarus.c0.iu_lq_t0_i0_completed_itag[0:6] (1)cocotb_icarus.c0.iu_lq_t0_i0_completed_itag[0:6] (2)cocotb_icarus.c0.iu_lq_t0_i0_completed_itag[0:6] (3)cocotb_icarus.c0.iu_lq_t0_i0_completed_itag[0:6] (4)cocotb_icarus.c0.iu_lq_t0_i0_completed_itag[0:6] (5)cocotb_icarus.c0.iu_lq_t0_i0_completed_itag[0:6] (6)cocotb_icarus.c0.iu_lq_t0_i0_completed_itag[0:6] cocotb_icarus.an_ac_sg_8 cocotb_icarus.an_ac_sg_8 (0)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (1)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (2)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (3)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (4)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (5)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (6)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (7)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (8)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (9)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (10)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (11)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (12)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (13)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (14)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (15)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (16)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (17)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (18)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] (19)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar[42:61] cocotb_icarus.an_ac_sg_8 cocotb_icarus.an_ac_sg_8 +[color] 4 +^>3 ../gtkwave/gtkf-valid.py +#{cp2 i1_completed_itag/ifar} cocotb_icarus.c0.iu_lq_i1_completed cocotb_icarus.an_ac_sg_8 (0)cocotb_icarus.c0.iu_lq_t0_i1_completed_itag[0:6] (1)cocotb_icarus.c0.iu_lq_t0_i1_completed_itag[0:6] (2)cocotb_icarus.c0.iu_lq_t0_i1_completed_itag[0:6] (3)cocotb_icarus.c0.iu_lq_t0_i1_completed_itag[0:6] (4)cocotb_icarus.c0.iu_lq_t0_i1_completed_itag[0:6] (5)cocotb_icarus.c0.iu_lq_t0_i1_completed_itag[0:6] (6)cocotb_icarus.c0.iu_lq_t0_i1_completed_itag[0:6] cocotb_icarus.an_ac_sg_8 cocotb_icarus.an_ac_sg_8 (0)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (1)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (2)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (3)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (4)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (5)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (6)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (7)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (8)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (9)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (10)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (11)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (12)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (13)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (14)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (15)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (16)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (17)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (18)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] (19)cocotb_icarus.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar[42:61] cocotb_icarus.an_ac_sg_8 cocotb_icarus.an_ac_sg_8 +@1000200 +-Pipe +@800200 +-t0 SPR +@4008 +^>4 ../gtkwave/gtkf-64R.py +cocotb_icarus.c0.xu0.spr.threads.thread[0].xu_spr_tspr.srr0_do[0:64] +^>4 ../gtkwave/gtkf-64R.py +cocotb_icarus.c0.xu0.spr.threads.thread[0].xu_spr_tspr.srr1_do[0:64] +@1000200 +-t0 SPR +@10000008 +^<1 ../gtkwave/gtkf-a2l2.py +#{A2L2 Trans (Req)} cocotb_icarus.ac_an_req cocotb_icarus.ac_an_req_endian (0)cocotb_icarus.ac_an_req_ld_core_tag[0:4] (1)cocotb_icarus.ac_an_req_ld_core_tag[0:4] (2)cocotb_icarus.ac_an_req_ld_core_tag[0:4] (3)cocotb_icarus.ac_an_req_ld_core_tag[0:4] (4)cocotb_icarus.ac_an_req_ld_core_tag[0:4] (0)cocotb_icarus.ac_an_req_ld_xfr_len[0:2] (1)cocotb_icarus.ac_an_req_ld_xfr_len[0:2] (2)cocotb_icarus.ac_an_req_ld_xfr_len[0:2] cocotb_icarus.ac_an_req_pwr_token (0)cocotb_icarus.ac_an_req_ra[22:63] (1)cocotb_icarus.ac_an_req_ra[22:63] (2)cocotb_icarus.ac_an_req_ra[22:63] (3)cocotb_icarus.ac_an_req_ra[22:63] (4)cocotb_icarus.ac_an_req_ra[22:63] (5)cocotb_icarus.ac_an_req_ra[22:63] (6)cocotb_icarus.ac_an_req_ra[22:63] (7)cocotb_icarus.ac_an_req_ra[22:63] (8)cocotb_icarus.ac_an_req_ra[22:63] (9)cocotb_icarus.ac_an_req_ra[22:63] (10)cocotb_icarus.ac_an_req_ra[22:63] (11)cocotb_icarus.ac_an_req_ra[22:63] (12)cocotb_icarus.ac_an_req_ra[22:63] (13)cocotb_icarus.ac_an_req_ra[22:63] (14)cocotb_icarus.ac_an_req_ra[22:63] (15)cocotb_icarus.ac_an_req_ra[22:63] (16)cocotb_icarus.ac_an_req_ra[22:63] (17)cocotb_icarus.ac_an_req_ra[22:63] (18)cocotb_icarus.ac_an_req_ra[22:63] (19)cocotb_icarus.ac_an_req_ra[22:63] (20)cocotb_icarus.ac_an_req_ra[22:63] (21)cocotb_icarus.ac_an_req_ra[22:63] (22)cocotb_icarus.ac_an_req_ra[22:63] (23)cocotb_icarus.ac_an_req_ra[22:63] (24)cocotb_icarus.ac_an_req_ra[22:63] (25)cocotb_icarus.ac_an_req_ra[22:63] (26)cocotb_icarus.ac_an_req_ra[22:63] (27)cocotb_icarus.ac_an_req_ra[22:63] (28)cocotb_icarus.ac_an_req_ra[22:63] (29)cocotb_icarus.ac_an_req_ra[22:63] (30)cocotb_icarus.ac_an_req_ra[22:63] (31)cocotb_icarus.ac_an_req_ra[22:63] (32)cocotb_icarus.ac_an_req_ra[22:63] (33)cocotb_icarus.ac_an_req_ra[22:63] (34)cocotb_icarus.ac_an_req_ra[22:63] (35)cocotb_icarus.ac_an_req_ra[22:63] (36)cocotb_icarus.ac_an_req_ra[22:63] (37)cocotb_icarus.ac_an_req_ra[22:63] (38)cocotb_icarus.ac_an_req_ra[22:63] (39)cocotb_icarus.ac_an_req_ra[22:63] (40)cocotb_icarus.ac_an_req_ra[22:63] (41)cocotb_icarus.ac_an_req_ra[22:63] (0)cocotb_icarus.ac_an_req_ttype[0:5] (1)cocotb_icarus.ac_an_req_ttype[0:5] (2)cocotb_icarus.ac_an_req_ttype[0:5] (3)cocotb_icarus.ac_an_req_ttype[0:5] (4)cocotb_icarus.ac_an_req_ttype[0:5] (5)cocotb_icarus.ac_an_req_ttype[0:5] cocotb_icarus.ac_an_req_wimg_w cocotb_icarus.ac_an_req_wimg_i cocotb_icarus.ac_an_req_wimg_m cocotb_icarus.ac_an_req_wimg_g +[*] Test pyvcd +[sst_expanded] 1 +[size] 3000 1500 +[treeopen] cocotb_icarus. +[signals_width] 600 +[pattern_trace] 1 diff --git a/dev/sim/coco/results.xml b/dev/sim/coco/results.xml new file mode 100755 index 0000000..b6da424 --- /dev/null +++ b/dev/sim/coco/results.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/dev/sim/coco/sim.png b/dev/sim/coco/sim.png new file mode 100755 index 0000000000000000000000000000000000000000..eeaf2599329c4337a585affd3f2b9dd2cfcf7ddf GIT binary patch literal 715047 zcmaHTWmr_-P2s1ErcXtfma-Z+) z_;L1o0aI(%tm~a8@B4m;R8x_~#UjT7fk3$Oa#9)~5I%4h!x;k&xcSmC>(#)k;tF`2uxuDhm_rMs7@s|Co)(aFJr-Ob$9!otzb+R6P086plG#QygnNmmO~ zcN-^1S}hv~3y_Sf4J|h>t+J^PEe{tD4=tCVFb}uzYi`=N%CwSFTHo@vtw11Jki67e zE$__z1+Q;f(+~Y8SIwH94Ykix7Kw>d=xN&{uwG)#!1(y>t<6+p(t8Na*R159Nq436 z^uY4I)4rtF1xfo7BrKYKJaDiaJBpt*@@(jQqDUZ7xus`unCW-e?A0*ByA?PFeQh^0 zLjPY^KgyOh{u`HP1P`4lx+`oCR7 z9Nl5QSa3jOTwIZ4I9{Fg#HTP^3PJ(`q&Mp71n@>DtAn|EHgHGgr%#{qMK%7*wGbrS zx{RO(Yiekaiu((8hv72t@)9-rElHl=J+K+KeY2S=;`TZH;CVRj^I7KAf4gXnN2OZJ z(ftW(ls9Laqs@mcd!*cEJ%N&tdKPwei^&4{w)06v`}wBoY}uFp?L4m6R2QHs=-x)l zUd39vT}9X4#f)N3Z*Ong=@4t%{ps-6loa5J|8@#`*r^Y_eVjG-7b_d+@$89su^uja7TG&eM8?ta!#p@pHEP7BWlQ7nHW-a zr!9v6^K&5fh2`iPf39SXrKnesNmlP}QAO=KL~Ht=3w=VvCGSDT7k$G;y55CO^I@h; zPu5SaKRKTmbol2d(YVB;Xk=t$_=Vu??CiY%*(jS~({UB`mbV%;XtBkE6?pb}*W!;K zFF~hgXWj2wBp6b2n>I58Xq4Yl#s3}b17+Q)AGXa-@lvr`TL9F zQt*FRA4rhhw*NoPCyr)Dzs;CaJO@8#To$mg-c;xwBL_zuaLrF?XjFldR99E`^z;#u zkqs6^5~Ya;+)jvxcGGX&{)GMbobPI{*%aR7A{jqaEgkoHT>LIZCYBtj%3_!}42R71 ztE{`f3r%c@=gwqkDmbv2URVFUjSUN65NoBC9cEKS%KP)pNtv0Hz_!XMDC8+;@SpF` zCIO$ZeBs-D$9 zFLqHoGlkrK&B@5f@L2z*P2n&anya_#{?)~ttd z_%puK=TrUK9zy4N=b+ul` zHmVhqe%nBTa#btK-k*Zi_f6R1zO3GT_s8Nida&r}Km~$@{u?!1S8{{~;6cWJ@*jBm?&M$77Q4*fV0{#MD&u&w)Qv zAjCpKLNJ9OSW;r5oQg`3Uah6KXm%A=r;Uxx3ua~_z#L}E4OlOK&VxNYJ*9(^OOc}g zuP8WRytA`&zoe;3grN_7TalQ!!D?~g3epcaezg@F1`dUfI`-IT-8FCcf3oa_Ey`rf zBD#dV{_C5)kxtBIg`!VziTxlJ@l6fgUrgAmW_%r+(gSpJX)8&g3f68fBymZ^6 zBmrt+!yI45OpuLwK<3B$C#2@vi|ryn5Xx(6y0*qIChvFIUT75n)mn{LTv(OVR2a3c zUihX7I8k>kzeU;J7(fdK+?$lw5(k(3H3rK`V@6s6yly zQk??ctPf{;@q){8gtVe*6-z;(&h^(vu0E~1kM5M=wPV83K%61OK(U=4ccB!e#t*uK zFa5f#{0TWd_>T|*L0L?ZY(6fFlX^I&drWHy%M8)=F#fk#A4nF%EhQtf+BE+x6;P$MrYklW_SO2^%y z`EUw*xZjWdECzB=$4MW>;J^R|Tw6`8v;Asu*eWMLyFB3CyC(s+=eg?nGOw+F2Lq1Z z;IuThKU+InZ7wU_da(y}>wT_s4A^X9dbDByp{HIkGX?!d7p z2_c&ARRsqOtAe{IZwS1$E`J$`bh;NR^R9xWgQ@r$9WG+2f~4TwPeeQ5l)qQ_(H7 zcOK~O1dr%>8J;MXp@ov)wzvH|d5XM=l1?*v8zJC2$b-zCGr`Ad}+wV}w%*^anLsr1$>>VyB z$7|8&`Qstre@E?C)Q$75!`vi};xkm$Am>u;^1rdDyCM1OSLbeAfhv=(PgMuZna)oH zmi&3e{4RSoT;J~v>kofI#r8hwCAqoXtNf_;<+>=taW#@T8@44_(Q#`let#@EQwa`= zuyXe=v3tG&;Cpeh1v`x}Q*%kL`F?tDTJKlkX)-(^QuxVC3o=1ufgd=Y2z2CTyZ~$$9f%MEnSlrMj5j`P0YP)F3hl6&Z z7jI_r#=kYzUmBISa%Z7==0&1cAziZN49>?E!nXO(ci~|u=mSQB`?Gd?HWyx!T5!a< z9aX4g@PeYm7F=21@!#BB>V@exjrVCI`_DagYD+}O2ji1VB&u#-ii8wh{vGpGn{T_w zr@Kv!sWGM5n?Dn%V@9oZ))<=4bKrZFy7dIi&KsI**UBOxnD?C$973u6sSp0ho%|Lr zAwfHs6>?Y0W!{M+;C5p_^J2OMnTN=`N@}TAUCo1{V&jmp)k(TOmarVjXq34ifckVs%goZH&G)wK&*^|aMAHWG`%QouLs z^{42H)`Ut#AUecv4ZQ~6EN}w8Y43<+aGO*{Hw0Wnuc|(*SLiti(c82ZC(;B|m{+rXq}_>(iXiWc zX&o{kwkxJ`Fw)U|+}_@f@;rbyN-#a?Z1=me+=o?P`*&0wM3ZnX9(Ay4mwgXQ)6L2`nDS%wjOm35VqswojE`@{2i>oUUtRdN8wNdG%m+O_pa=2vH!~@xe@RIAIK1(T zRMOCp5|oyfrfY|Z7V>;$e}CUTozG52Nl6Ko5&8KuN=Mu7Z!+x?(cRE*~d(R^P4MbXJYQAkkjf21>yt##G43m1kRe+TqDowh#3 zDc4zOnKo(Co9<_vXxL2YD$s{8UWt|*d@ra)Q25ug!_D;bn&VP=CdQL3->FDCo-^qE z%^+N;wz<_&XFTQUYzg{KHQJMAd!vpojCQpzotYko7wV_m!s+Y-E|;;QvdxiYt5%){awZF74fbf(wweKCBfl%+xO4M-Ebc;{bV=Q9w39AQ;-R+%m`u!g}T<};vo(GtD9@sFVphyx-yjoK2> zY!>>QZ5q0b@~yA0SJ^=;9uD0$)2vSSYsaaHSgy_0fl_~Grko;<=oVSq*j1E{E;mm( zo?7hX%a`A)s=fdpHCbaZZ2R!+*)ugYwKu>k7-&~v;L=O0^1mm(;JyBnJAX2tZ@4hg z*cj!smrs6LBN>~e8_y)37TdDyW4yh&cvevC4X zxH6b|o+7bFm-~3+efh{y=!YZa4vC~dZ|kQ5|H%f4Z$lOTmBvbHi}EHpKS#0MhNM7| zk*M!Cd21d}1u;*){gBIyz@P-9aKxjh4oerfG<84kuTO~dHnIrN%A&2}ubY@To*&ms z#_FW*KkjReydeA^!w2qWp6+@o48MaAbCrPn=UWdN;6NYv2kFQvW@W~}$zpRPt<1PR zy{wEaG4WCbh2LrM{s(F>RsYH$b57Yy6s%mFNyM-Dny1m!da|j|osokha}Vk{Pk;UJ>=91s+zoOaA00p0 z$W{nIfgX3q_rh>Eo94bu%-~8)Ys(9M?1~TU>_(Bi?Enva(kc7RLqkr!;x&Pz=)vat!%@Q}!L!SH zOtHLel#Wh_AlzZUF?f%=Q>M{$xfkkkP+06{CMkdx9W)hR7VjjxC#)inK3#d%8Nw%~ zIncm@e+orHCJjoAgXlcIgXTG?(ZME^~;=_qVwC|Xi7NYh&doA9S%W`;~ zBvjaHx*Btw@S^TWGDn=)o`CVO+|^v#wEp@5ONES+9mdX{JNKzXyLpvly1)gU`%vA;kQ*?B;E6Pcw=%+H7$f>Yi!tFN5N6 zS6{L8x(GcJa?JKnAX|oI{gmWv3g3=}Y8J2Z zWP&Ll^-y(2ZL0FX4Hn@r-XK zRmt@$(x+z*vr5LcM2Y6%&IcAd_eZliFMnDyv zZTVL?G;;&KuQ zx3shbPAzF{ych^qXab5MvlvqVsjsu2t(o!MaG>nZwHQtTuF5pW0bjamp?=;+n~($f z8T<0Ih#mGLH8#DC%Z_f}(sb;zelvl90ZFJt4|;~3EyV{ozC;Z(EKaLmdhK$jCxh?9 z^s(RQ!r2G3zOR)sgx!(MIdbP;D}N%W93zyRWU{>5|6iEI0ceT79ND^@$P0~={Uq2_L++5Ydkln!Pg`h zMHhKqwKWXv*}Y}^>BeWEJxKOw7=^*_x#w@U7L6i&?@FU?M9rgFI3UY|HU-V>ipcNp zxOk#oX%9ld@8u@y@9@@an&zpqUFCuB3gsk-q! zv;GTFmH%_LzT_=*2)dI7FPfFrRA*%8avut=F3DLIE&LNP35PiA32$rD7eqor(=cH6 zrwa9Nhu(Ge>!B`x??sc$xy{KSP&E6Xe8%F(KCAt%SpO9Y=YsaTa4k+1cA83N8R5(& zx+sCoaN_INU2EIILvMNeoF5;qc+LB8sQvc2(eSBbpcJ>%Zq0^3&zZ`iSybh=rIOC? zpkKW-fdTT`hb1&Pz_mp$?;b>N)|0~j6xXNpQ~SjrA)_sOhSQe=c<+Y~AFBLsP9=Bm zyuDz^om9f^odAv_%JK5$GTaGL?mZ8nMC1aFhMfHh%F2aaM~fo>d=GIj;vfNF>JNXr zZP$Hp;`zCIO-&7~BR~X5Tov_M++je|UTX*Cn4FqQ{P3my_LL_BPU4$8%??%zPLIY3k$gC2G@VJK=8_6kSpDdxw{AbDzjznl%4c& zrXhT_7$hilDV7%4QTa_@tG+y=feOCD{e~+wd00SOX@F*oLdbcN^t3qW*qJk$CG!_J zY+-jTX(Pt;eyU8k9D6Tk@ga;_e4{iw5QLi6S-wPGvUFXyTVPtXDM3RZ0n z!0r2VSO1E7^z{A3>z770)CSsF)3+>hwOQpNt}i|N6Xu%;y}Pjqz5m4F#D$?^8QxJ~`T% zH|oUTwHSRe3s>o*oB@3E$Q1?P9hvl*$! zIP8R?bvK{KR4WAqsd}r;%CD`{Wt}`>av}zgG)|AL?cJffOfFL49ZR*Gz?u` zEsY+k(AJliA!|+E`~o>+*%;(axM+&M=hPMjba(cehRVa9jG~dw(v{3;Yibi8Z^syA zPH`8_fR3*+qML6I9PU@vrN$0Pjo2~lg9*sg+fD*hW^?09v3&;0>i?E4q7{a8jhe+O zvMwLO!AeRvTiJdbkM~;=X*?EKR#_gzPg~HC(QtlngD5E|{CfI@+_!&M^#jPM`C4CW zeZvx9;6H!<1lhwI%4a+QI>rQO<4vdI!vPWv_M|gkCU*4_?o^rD(HBQG{Fn9N450df zoHZz7Qm$W*<<|yej4G^l<}7!OX(PPB&X34@^Pb>oyFy_*cJZ8eeuud#%TaOwi@Ka$ zB$W&d6t|lx%LNKH@Ak!RjYN2h>hk)>+~h&bvW+DCP4xiWJ@dCOMmYoHbdGk&upS+6 zzCjFwXq?L7S9~s>>}D%rHD1W_Svy~~+hb$5yQ`3@1yNuP_Cg|`Oeivks*EdkW3&3) zx4%4XF-G*V8EWr%2G>vsJ!v-3YqS?%8ofz(>M;7nE3F*)zgmFZg+R8VRhc+HmHAfB z;Go6S5tb*;5qq;4aeS17oqgwpsztpf+=?A#b$LF|94fLqGvdK-a>5*A*v+6rPB*qQ z_QYl5`G3eWdk!IR^$y$Fw{#k3#)4PI{b{b^ z@yvUCAglMaVJ;d+NSU|AoU;KDQx*+x=`k&mb*}aoB?mK4+IS=)_^8t#cd=ArfBJ&L zKl4_u&WF8mCaGn*Pc39@h1D1D@1SA6{z129d++AGk(ji-;Dlji?2W2p^|j3OR8p0@xeu!yom0G=U;>S{bF5s%wk#dnB&wl?uXX=z zKGSQL_kqf8*SiulHNqxc^53CioX4G2GE&;2H1cPPG#iHymma{2lfeY=Izc+5O%wUOoTTzepxkqPvHzqd5^}~NE(<)cJe>|!B z%H8)H5)@Qc?+*|FrsK&ZJ7ww6=%^C0s=y{KT(h9to#H$D$K!7Nzo`L87~b2t;g_=w zwqTPekPMmU>tNRIEdyh+bq&QtI9|7I# z-Md(IZ3d`3EoT7idTskBqOR_><#={%{~Bhy-m&k=jsJ7jNL{-V-*!@SptUM9XpAFL z5&Q@o1?0rA;f)duB4m^&NTSr^Z{wl-`$}8C>5;ze3ym17Lx^A(3}G{=62sT6sxPKd zJ%?rQH(LCB>>Q|yej!U#Iooh|@f%a>_z8PCci$evkur(GdD(j3nTYXbQ!DO(bJkA3 zen89eq@Up33Pa5+7f2eZd9`o3_Kw){Aofqn(!j|`QCZddMF%O~+XaMIc5@l~goS`> z+iNEt1NLwGoZqUK#ltT6zF8uZ!B(X=D=Vm{JT6GzEXj4I)SO0F&XTh&1u~mE9=uC5 zH|^hQbH1YS*=ZHaP2N#vV;{R?H9wL_BhKE$X}?253%Eex#lqX?%jPnD()srN6YXoA zf0csksY8nW6yPlylIg`?Z2oZ*=9^zMFE9<>sHhM$oK6;fq-;14Jy)0RVSZ|)?Zd}h zO!}$x=6Kp>9`^8>oH3_2*(%mzH$(6FN2R@;A?Z{P<~bB@iS|LooK15F{@IO?IMo*u z)lbWK9?i~XJF0JMT8q4q!4el-m6t&w2Kpac?KoRx{YUzx(e^z%GCMx6if5fP3v+p^ zF=XG__$7b0V_WdGT;_W-A-Xxjxq(q;V3cLka|{XUL=Nzml5QGu{8sa zwsueK4>^>!q71K+ky)g1<`-t)p`~iW$1q}g^53+--VH87nFXD2yd+Y)J}M#d|ZkHOS*_@b2kvA8D2s~1nZHW&UXoni}wG? zGf#oU)1&`caHS?xgA3BXVQVjN~gC3vSalHOl2d7%0*>1kT;F;+)Hw zc!X_gm(A!GzA<5hdS6=i)GpU0M)FhZGdt1TA;_g5c7;ARznnr{hWFBA5@kr5>Y z1qJ8K-!yfn-wy#a!e+5eXkucbps0w)dHD@J1H%rWnIR)1GY#+-r3RSw5HwtRKE7la zOc#*oblqO;MaIOGZR69D;)EqTN|?l^PxfFwaKEO|t}Qy(%`owtx=wUyn``Ekk7I1I zp~qixmT-bH-ebSvW+g_v*%=s<`X)DL)$r?K@YVhEaoLH7y0-;_Cj2TEyI!>?<3nqc zXL*t2uQT6HxP8lnT&2TO(mu!-(8^6rhL-*C@9*uJA0U|TOXW>bpJYzL&|zZ6RoG~r z7Ac*7N+1vI3Xpg1yiVmd-_(90xcu6@XB!M4ZPz-dGgMy3_xFK##<|RGSh`3J_>Z#wCX-v7ZPDl;ze^V|$*3Dh?`C848 z|C^$*qqW^&>Y9&vug&}dcOplsu~NKO_8OcJnUo$KJlb2%1{3Y@TU%md<9ox=?2~Jn zag9QV#}#C!K+J1pES_&5y%J@ww1$Fhfb;aj)t2VX<=7a`xsSEiko;@E2ZvXx(X$cM z=ZBkJPkR8mv&=}A?jG9&XK_F`FJPrs|8P63PBfRdoOtZRd(($85nqP3=Sa(mtBG?E z2YYU5#*MXeLiLLdyo~;#)XL4tyj1VAL&q0_2?dvJUow1+b!TYhPP`ub%Y(A}^n=90 zg4!KO5is4rrS5QZ#aRSI!uhCYp#;JD&xGzO^}gcL(gjD#7w4f3k1WpA#|6~ylm@oF zp)3AsoWNm-=WX<5vnj#=*)1h`nX{C*#*b60BjPHyS;GNoC;QdUed31{i9I`H+%Kfb zJ=f8?c9Yy^OW%f|f%fO>S?&FNm}&|NUI4eI;|wfxbaeYCKyKJAKVmm%*ay1f?yj)l z_|Ric%8wxD_aEO}-;TY9u;9P9+4+c$%xK6(`r;{uNqH}62>V?K6$XkmK*OM-q5@|w zHS_bi8=~y*T01c*XJloKzQ6a^(9{IPIm)oWnYpOPRGp{dYW%O#w`+_XjPZo}=kKru zMq52O?!3OtPe!-d5UP+5TSCPNxeoWk>rh4=447>Su9n=3xo?ynNcYqZwX+L=O9B)lxj41-?$@<1~ zvy+bk+1Ib0Tb5Gsy-F?`rAVM$3(XU=UusHg+c*3qwZfAiCA05f*Pv=SdDY1KJqJ0h z*v&Vo(c7ha@k^xxG`s_o`1ovUgmc!p?$8JG(DHK0adUOol`=Z11Xo*XUu~eCUM1cd%q#q*SR~tH{>yp{D>M3>u5ag^jNT7)>W7Z7%T9> zE5E%gw9Ch!TzfjPhTnGUOCHqrz#=}Y;qe$k+S-WQP2(3T8~$R2>CIRwKF@7}6U;Hb zzBlb(=zE+~m>Q$L<|Pes6IFyWnOQ70xVq~IUB~4qgyspc;T!E-i$Cj>mi91k+;Ekj z&eN^7smL2su@6+2n!@yD^|0l|l0JTGOf+_sVTo2wxQb8Vl1Z<22&P4DEIZuf>QECQ z)Xc(~PKiUvhOdGy*?(WS85GMslEz!C?=lfk4{mXP^r5q3&l2_!{w5dlFLaG5(mzM0YQc(^nut4DeAQTUOkG7=N* zs^Zmw;2(?FW0T$FHm(h?%=P+jM+m9S_eWIcCs&nU>%l>x5V*;lOiKifH)mzr>_^$a zv!_m#Cr3eEon`u+_ie*+@#u42YbZ;8_G}nNPEJb+IEqzIb^EPy*osj?9z1!bJhR3u z1~JbmxPyDf#jR3NBfgtMaoW%@%FI_*#Zc^;&Cp#L!fP$Cl1LU5mWXhRrqse-`)6Pp zyt;sUU=%YMeE*tL6fhKT!TGIKQ$V;G>508z198SzC1t)g2X$ftx6;MVcALB zIe6Kjt5B+!2UkM`4dRTmgM;V!!I|6HJ0uh4xNAY$#@*aiYoUGe3Wym>vAd&OOzC7# z$AzYb?GIh2w$scYXNoC_Ol8NVz#g9#x4s=^@0$&F3w0e5WkBy0ij8qUP?nZ~`Nzid z$oZui{MYzwL)HC>V75;U_SVD3(f!WX7yem}o7M15*UfJ10l1C;`uD2uKlU%_BtLUL zk$gM)K3MsMICwi}hFDGaS)gX<)Cw^IF_N4~O7+6&Fe#?v0=HwFZ@K4p(^06Q*Iw*j zcPTxEGUNK&e!3PQ~JZi$tTi0v3FNv|RFWzJzlU@DI}0)@tokM*y{1<_5pT zqoLtcP*gm*d$@iGjN#6mX8!aRsHNl;70plA2cJEEzT(+hJ)@zouV0?%21s;g^np{q zWMf+orwLrHn^NiCI(z@(EIK-xbupMyV`FpP-j%HY^x{Q=wF#X2qLI6E2H(lzoM_8! z{M(Y-TR6r%`}oFqW$_o+Gl#aSrl!rv2L+`Q(GCL~5*$!o%Y@hhk4-L8(wj$K^e@}N zdSa20(UM0@N-H`_+1aCvBz-FfUi{rj;%i_LD(Awfdd=5(#I;r&O9(9s4a9e+by&}N zJc+YYJW<4X_P}q=MDGi5>+q*p@fIAhwAUnRJUN3o_9aaT3_sPo)kw(%MrGT3t@1BD zo)1-M*xv_M%peX}|1-%%P_|O$4YPvaqNmtb;^t9Xr$+**r+a?FgtHr172Et-J0$T1 z$=I+5%t{C(6y%588F~|{+bMj~)2}6_M2<}DonKcKL!FDV&E(fA_EeSsGUzvt;?|{Od;AQ5->F_m z`8eamJal~7+56=tp=?f7u}dlaXlXo;$2NDk72Au-Hh;J^?t>LxR{Bo8IG*`HaEBj+ErbsLMpFkq6_n(am%x$V?8OHS$bHoD%hDGWabz-^M z^lA#SWjxNybgQ3y*MGitnwdXNLfyj2!6D9rT)JMI6A1JQ^{Xxb^U{tQEaJYccAzUe zi2#6e{c94z`(c(!y;`Pym;N}a?!;|CD^mtt8%^gc9diKWzXp~4;@Nt3HuFu~0IyS~ zU%wlC1+KS!uCA^Q@c2!6FMQf(+df`w@UAJ(B_4_tO+qZ#7)ueuA*u1Jm0$~^Dl|fL zp4(7}o7)z~rHGhg?RDUy?LDZ1$^9@r1{sA&b*&6xj1xGcoJQH=@+9~jvC>VQlWVlU9-e71C8fZQSJ<76g&zLhc#V6_O^1We>C95(I-iS|EwJv8-->aQtdh& zRy%j2d7^*}U)!c=-`Or;j@nRbUiv!d_qTK|LOH$#Qj>VPnPODg4Q2QnN(#SOuJn5e*drFQ-_L*QEw z#`NcZ<yNE`~#1PyO*yucoG?oTW}4|LI97TEvpod z74tvad*&#_oqllhR{H>ptEN1DCzXkJCC1xWsP?Ti{FgSfdLkh;>`thr%VainqqH7% zI-4eipnJr?;B1UIb(rAW&rmn6Wyuo2Fz;Ns^lx_a$t)fl--S5gh?gkBS zMkXh5C&Z;fpnwlWFR}ISc#6GePw=XI4(DsW*M?t;wGdiS5~@%QcE0@XPLRZ0neVFZ zB@#rK#2@~o*+?c+#SVSm$oKa&GK^4rJv!JR zFEI}g3*J-RQ4vUMC^rqeg?R;J_44Z*gf_ob^8T7{7D45V z)lUEJAy9Y&J#JJV$@8e5TV3jAmvi4%o843%Gg$INxYFDop7NdD-=TOM*eI}Cd$NpI zqm|9@22S|+_}u$amY>bondM8oPMWhY3cjD0{z)HGod+5J{*rJv=_ywh(D@$cke%&q zN|7r%k3yQZ8aa6dbpFko6Y>k&o^WYBt7EME!(*OB=ap1wlEfHfBo4=l@^PzQ*`UF} zAK@^yLoDK_XY>iTc{tL$@uz;_b`;T3nd?^0`7q^k?^#sNzM5V!@%s4S0R$Iz#G1=- zDNwCP=wZ*8m0PUlW$I^SC6Eo5!Qos50ZQc#Eqsyd@TEdG1m=k#pTE81M|_eEEy|?t zPdW)}{H`4TO16RKl}y~rxw%=^Jq83&BiMfaLoCH#Qc^qz9*PPJ zT}}s?!~chQZ(a&f=R@%?`yV5Ab8{u>H263)%5OYt|{#a_Hv%Q?X%Vf2Xi>0!;@s@LIXPZ8I#BxakJ$E{60rK z|7W@;NH8~iJ)xc(l$Q6a#wTS+;d%w~Xz3_zu}mA91L=ZOl&WAGU}0lRx=Hs*D#Zxw z&-S3upm8B+^g2$L%~~uUMDE?Rx!+Q*h8cCu#wL=zE)!8l8`+KjR<}xO^auL-yF;s% zA*k!Xe!Qf=!mZ=OOkRx#0*+^Hy_f##sPFf~AMqE$Z@8j`z#Q1vH)x8A!<*MQ6BFw7 z96a_}FZ1$;I^HTo+1k7pp_tC02=pRXHbirUtR6LrbrtLNZ`(2b6UI5kR#Qj%rWP@+ zAC0R|$#yauIKzHX>uZdsNL;pjzzGOkM?{U&^agqgrA>w6N?W8>Ji30wUsV-*AMrYn zH`zR0IUX${?3jJlasR<(4pVmZ89t|?wC(M}jUOx-?1va3-Jb8!**nY1xVFVXq`{FcBg5+FzTTY4uF^SkwKn zlp{gWjXLCPj_L7&;fJx|Zi{bd@B$lDe8crnSNd@{5OFuXAPzz_{9@Jh2_Mb;p?~M$ zPHRo_BIDTZyi854t7l(jDjyy9oqtl3dtH?x|AY*#ioBFcg_b&RE zzL)TU0nPf?nuWm_0SQZUPz3n^qkv)mKsH{O#*E6tXA2Jl=nV$1)a5-c^vdnsndNNl zjit2Mm@t~a+0LV75*5nc;YhDQ_Pg#^sZe=Hdd7G}FVe^+zK@m4bto1Gc!W?QIQ)Et zVVhLl?P75taLYv>E4a}6W)hk5hvfb7UUL--X~y{E)?*K=#Lni6e|lj;ez`uK1TuBM zb6`I$rsK=e#dm=!)F1b0fggT!g@+Z>Bti+%6J=xFYZ4Q^l$@!hIcbQ1=j2grmg)G7 zIR#b9nNZ@ZcT+Qon$MPZcHsEqF2Th`PRxxjpL&jfqX5;Cwm-XG&FAfH>zKc&3$wkS z5vh5}MPucG>^q>Gt*<08_BPGA)3qBM87TmWXr(kB)L@`Z46RQSbfFIo4J{}r_>3B& zsHn(_Q-P0jiAOKQ);Fr?&Pts?OWt7R6|MMc{8Bsn> zb>Fiy#>=RlAL>z)C@5M_pFXuwG=g<_0Yl9Y-Rh z68_iD7rWDT#Q=x=UpPc-4x6sMhtpaUB*XF^__p)4Bng1-kaC|R~rJ~IB&&Bzk z#|lVCLw~OilCKv#NTY3?LbL9?wcBfDS<b)9Ih1f`8~6l#|1I&{;j(nGm;ZSspWb!e?dC z7vVd~L6;xwLO|8(>aD9i)p|!NQ%tNZ)3R2JCw4~e?qCo07;y<6pTb?W#JOFP(-uvd zsr)G;y`<9i@!N*Dp;WD_4r5=7NPUJ!yR&#GUr@U$q-i@t*w&<3`1#f=ix`cYgL>IV zNsm>Ft6iEPam~9;g&Mx}$9U#*Z4b9VZ;N`H{Q%$dwYoCOM`G7H?K-KMWTD0*|EmR9y17Sv@H5N0x>@a{*+WPm-t-?PlXQ^q z7bl@*`bWz=+*0f&B-;BX82jullqJX9?c@sYS9QC?Ou^IjP8RDblBQV8;d1xRYj9$tJ28i1U~m@oYT}onz{#GfQ^n-SxLtZcI$6&2 zHt;Ky+toJfqgYu$9ND+XUTm^S$Hec zt>I38331tYQJeF?R_z2#hWp-Zq1C>g2R zG8UFrd!zY0cC`vMSmcdqy>kLC)!)BQ?u(@;uD62@k>*%~7aMS7lJgeJp@;_jehd4Y^|5w{`^js@j&rKVLd`(e6L(N z<7TVZC|4jm=R0mVO(7oR!L)JWJYV|tnEkW`PS(ZYYlquSx>qMbU(9dB;&%#Ja%?SP zuV|ti?%v|*>>1w_8$V1S3748%1#B#jC6?{>KN_jBJDSBdymML*P$0r@*OyIs_G1e* zerG8FQPD30$(5%GtcWT>W2w~2@;!%khTv)DgyL^=I=$y7^ZfhoH2$$*2SU=XICv7v zv~==!NByl=9d+}3C>s1(G>K4y0R)Y(pTGT5cEM|tsO5z9W@sm%q#|%x%gDi~kb+_( zow86PF4N)0di+6)QUo~-b^1^L+?+(QZich~o+5T*(!NBFOA%vJgSd}Vt!oomo6OmYWx5wPtt7ufaE ztXZ3ht*5B3<~MwQda3zPuS&zfz?#9UTfB5)mDSPPS~9hsfj^CJYz@n`dh)-!L9NZx z_XzQfrIdX&lAt2-5)Ae`7i>OF>ROb0*w3o#3nYJd?9svH)E>WN(PNF((=8PsmVWQV z!eA6+Epov=Jn=A<_rBD(l-GEbJXzkjShCU`{#QpoxjS9j=p8F|36qp~*iq#(>xt+=0Euz877n-$AoMOE2#69C5DQi5E%eYKG=qRhPeL!DhYq2aZ|D7A%l*IiyU*jpiC2=HbM~HD zGqYxmeua8>`r{81CuEn(r`f8P>uD;+U-7w2M9AM16)kNhfn<^r{oQ4M>>GCWMZVj& zLE(4s3tw)TNf9X{JG=Wny;M(_d&#a&iR~xp?Fj~j;oTnKEnR239)P~ZUVsSI4VU(t zs>{l>tG&pS)+wO%k<n)(qBIS7<+ z7_E&rD9wybPS4$WKIglAa(}PU>0)YsHh$&9TpE#oXcoStXhA$ar`z$b$F%zZrX3=sakUXtvADkF*crt1@mT5 zs@RIYo#{8XJ7SdbI?XLva%xg}uMlrU$EK@`wJ0JrVAUQ4nzqJQkqqp(WcIiWT{;)D z!CtTFPo>3$(bBE%b5roSN*WE3s#1x|ALp&|Q21a^#N4+0VUnuprOd+2;7N%t?enQ!juT}4E@w<}lcNd!o8P3?hm&()qp_?l%Q!e`2bHc%t%)|o4QWLB!>>V-KHmR5B>wsw-$q`DYmyd(R$=~1 zYpfS1r<%!|txP(6tRn z`^VC2eMfhK%uo}s?GfZn)70&38`u70YvlUL{hmyZ>1%HAEN0jK{WY{v^yU|ZYv}vm zR+Ppfu(dh=6ENkrffj|D3qA3m8WTLKAEdMC!$;BQILx{ z@EQW0gP~#5-y*KN?yWSzzkd|;BB4rw*iMeXS%Bdz7chqh5*q|l2A!_I@81ukP+&D_ zMg2O9wW+|_`|1UL$rYq7UhJ-}uC9*;($7uH9F`k^zF3Dtpf=#rtD%(%_IC)2)60!P z=f|#dJql1L6jtL?o~9C?HQD-sC)ZG0JL4pq$KOC1V`yB0?b*62IC#aL2zyaelm>8C zuAnm|IK zbC~h`J%bmK1?d0o7%D1Zj5&RL$}#ul-4{FtGTQfZ=}Su1uc!>Ug&{xoPrG(6gFoT7 z`0GBc>BjrkB1C2IY4p$y_sb--_dvFHqVHTUO8tSjCM~o#D@zX`fSbjICe=1wx;mIj z#l+kFH@uC!#S>-H4@JKid@@w86asXRp6fU@8=FmH#D#svD zVtOVtN^&O16P;yUEK#FXqcW%UnP<9Zrmx&}MMtA}6m!cnw(NY7;?U$Dyq>4=^ECBHn(;r^1>=<}2HCE5yESy^2GWpb?1~DBYBEl@O|MTsd6LM6V+DWW7rd=&eV?J-@pLvHqBQT@p+)TU z(qEY?6?-%*+7Ylfb*8&_*N47r+Tm}OEQQ=>MvphIxi&_vJX78u4eU*uu1OC}97u@n znQM@I(|N?*{+XHcK1ayfcJj{HvV5s!gw57G#%nMAu-A~LGHX+Mzqbe;`s%4BS%XwO zSM*pI(FyCFAEoF0wbzZBK4NKMf`}N+`BC{G@%y*Cq1Ojm3u1-$^A0;wD)hUvD)r}Z zR?R1g=!rm0!uNno&wV*2aKTH$o`_c>s)5~+)5KW9yFyU z13eYQm|{Xw(lttCxYPN@_ua#{qUHdERBZIadpkPvzdF8UY3c+5EabJsL%r?oZRWck z`CYTc;1eU5O3@wm;{$>|0MX#V7DQYz753h+?Zx9MIAd<8(!FRTgcEA7okBmNn?mp2 z-0N;Axf{qL*?`OGslUR9&Yw*G<-TiG9!^d+_uzMFE6Q)OdVTRF@6rf!j$DlF2%B(n?;+w9*uVvM<^eWzmKn~AbEEH4P6 zw{IV*HMoW0BJYeuqIKiiGj;Ol7#5?gGltQkxC`|*6Gjc326$2Jec$;r$eod!@hj1H zz@Ko5Dnm&$|0Ay3MPIm4p=+YE<+G&q@5Ru5_34|HR01Eraf+^_t~4?{o}nm=d~t@` z*sPC**zun(br`#+?@)I_0_Zcjj0Ih`cfRB>Rv)xOGCa%zlz)|6C83FMt4^wXPM~{Y zSpn38$ltENF$;17Dr|W`^9rVA;F(G}r>7aXXNuaTyR$U1i$U^ma(X%&xHE89OM!G- zT5`CABIpED(n|&qj#9L1d^mC^Ve;%iN zid9MH^L5Ewr8zSx7B1m7pV8IzH2QssR%l`yFE6i#s$&5NK*7o~0_v|_WMrI42wZb% zJ8rE&E_u)#*H6CbJ$-vJFAn{BDa%|tDyp*)ZYpR5v2YRX6`4aYXpurgv$+(86rCI7 zM$sBbm`>kk4q+AB0oP00~_~RrL#yD+~HE#Idfcs~gL-BofHhM>+oT0h%?7a|6eJ-RpdsxWgs!3P+=PqUAtF z)|-S*c0b<_a_!mEG>b?6`>zNJxc>YHLZ^C9^u>*SAd0oLwrbhi=Q=q%M@Pjb$HnQP z9=mp|)?Lo1ImB~XI?EbmS4FdDHN5b4k6q5=L`f{FmU}Mfn%k$>JoT>H4%GZqnc4=D z+u5c$XmH?{HJko(wC61<*_I#lj?>mY7k8eTksR3$_uZ@L# zmme&G{RR}UvUE%B$J~}>P6Y&yY!NsHA@p1J3)*^nezs4Dw7auOy}oap89 zO_dlt2@~FxQrEMGA{;|w2jCxnl<|rJg4u@fcor$JG53ibT(5vaZ4gk0iQL*bC~yF z+Ey9Rk>LwmRF(0Xa4I^W4K)X(rEv7V%g4ZZ6K#c(=H}J`jcg8}VAcEg?-%JY{95&& z7gncHY*cjbK71fiejOxZk_HC{Su5lKx;5|^J0Z2V+~8yS=P&%eu6f)4h)Rr-@{IQw z50w~u!60n*?cC(Vgsr0w@W>WzF{!|M+W-&^t8}xYK{5XR)jzJReC=*iv1qBQr##yn z(gJ!lnjrNGPSg#Btjx?#U_#cxcAq1@kwf}nk^TpqgdsIw6U;OK*)%{ac$Nu#dk(_a05EUoyexOY0l z+&QM zF3h=F`A)G17vZL_qhTI75rZGByx zRrZZX^L8gq(S0v%1>C1fh#|&Bf%PimFas+bg!s^D@`MwrnQrgq#@Vo>-LtsMZRQs? zvmDI!#J%7@1nZ&%LwA2j%fOV+RjFLjvNxeE7`HIpf5z>`zv5p1jhpR7X@z>YMsnq+ zkl#n_kG1-1Mn&BT4?E55Z^tm!XGVj9BcEbh%!H`{J#n2`kH13h?iPf_5q0?+ZNCpv zfm%CRqpVQYN=q)6TwfUO$RN~g=%;7lp?&50o%>~_GtcYlh-+F zjk|0o{E|Ph$~>C?Xr@#MCoXBY7*vV(Z7u08OIJ8mEf=~bsp1+J&;7Z&U)OdD;ewH9 zxp0Q#>dJ(p^LFLN<2|q@n%3awPn(&vB16%eJ2@-&F}Wj}koEPQ=P*)`dN(e@G(gNo z0K>=MMLHRQS~*rZ92btE{(7{w?z;*uMtQtHH~MKfXDVklVNkX*kM9a`B-^isy@GtS zEZ2#JuP>uhtWVRHVfvr;hn>zXR_8v&wk^RmEC)VG5%~ST|FcsLzuch=?R-w!x8Li?Vtiq0SIkOtRLMX9D)b0)LZ8bt zCr86WrJp&K1yA1%IL8cSC5T5CXF}RuUh5ohOb@f=z^>>84XW2h(3c&W+P5 zcg8#v6vbzk(U9PXsOc+x`Q@UgSiON@pC`)f(O+Tk$q<*K#K#U_InLRdPgEG3(=M21 zIaQCzWyhA_A_Q|swC8u)1y0@VKKu##{Vz6=^UglnS4@QM=no4{%s&1` z3_qLpdrrKBudaR1I3#Ca$2nMQy^hXCl`~)F}Ykv|EE>$ zz=;_=!CMB7|MK(6 zPvT%?z01dQiXns#nIJ2GZJb)~_d|8%Cch)@3{|geCr=Y$JXMy-H}>F@Cvx;<2&~`Z zOSnnCKhed%@BI!-UO5gMo)@!Ep^aaPUU4YVG=3>I zS$42v+TL`0ZKpstxv@Vf1F>bc_oM*R{*U_%)}&qaNk1g^;{dfgynd70BQc3*O3Dy? zj8Q-K$7Y4UX(!@eYyJ76_`Y;AALmv5}j;^K+j-efPCVWNBVm7x`5?F=jS}@Zdrn%R-0;&&+ z3T5GWe*8|=YvX+RomB=*qNo0rf8=EJR}~A2@6;vBk~^_sC@W=yR)>66KbhoFfuHy9 zUqAaV@Vu(Q29`)e;Qi>xFxml|z>NIp)A!3{^)wC=aTdqn4FUyw&$#c(h?rjsXF*&D z?+>W%$S-Aeo%Z@NJmWiV_jRSi&V|!=A-`2yc1z4^2kCk$Brl+3=zE9ba(c3d2jRu_ zJ8GpOEU4v}&X{D&`JgxP-yb^2mBCu#I0j=o3+ID(|Fxo@FFM|ft<+|cPU-~;*f=x} zTz>HcDRcW&Z;SwoZK{BOY~NFoKIf}4Iph9}0ui<+v^d7~8S1MBO^r)sj+i&l5?YTRvkBxL z&9Lihwpw-Fx3t}Nw6CHS6LD7K`?;cj{rsEc{D?^m>O0y)^R}YpY_{A&*~*Mn)fbWZ zRJ6f4Xi*=Y+|ZDV-1rLd3nZO*Zpif`+~8|$Fl+h2K}NG^g^FBJJ~F)7@XZBFE@FW_ z7HWr0JkRj;t?A~a7ZKG{2K*ANccVOX9heBpcZp_JqP|+##)kG4>Cv!()9stX*YVh6 zKUC+h{A)=+U)Y5ZVf+qrCzOa%Wt~d~9>RUhq#&0e?Xce6NhZD~59KNqlj5X^0w;a` z)j7GVW``|xc@BnhYlyqYS;#A1d3x~rl}oqW|qhdUDx#Icfsw+OW) z>T&H3LSnb_3kPLe^A&%moLgcdZ(;>4U8Ys!bPHBu-^bFa4oq>HziM(pMCh8d#`hO3&|}oJU+XeFghjnrQG&j{Jw0&Kg@)#B z+j(@v1zK#u0G*}M#?H=jO9sPO4dKVjk8GKO-;ZClc-&G};O}rJcpfE{+(yvWft$Dk z_b&Il-v8$ct-Rw#gW$<&18Mh?hNbhKi&(Xzao?Ck#dAZc4e>GBWl*-lwgesm1C)%# zPw8L3QVT5*Pv*!YEp1MP$2cd;4Rg3af+A4S>~}@R-14W)&Xr|WzQi%0crRhl+*NLS zSImbi;nl=&%+!_?byI+$JwY@sZseh_sZ*i3c-7;2%%7|Ib#14~L?t4psLOK}tEdS) za&#%bdDXJ*xqIY$Wxg3bhu6;x%2ftp2R%A^KW2>KgM&&|igLn6UXs3Pw3NLH38{ux zgf8dS!xfEMe{un?AHeqVQG%*3McD$#F#o9iTJ9=VhzR>hk|MQN;4Uqj31h%U?tpqN z&J4XnEfln0kE4<1iS-$Bu)XUx4;9osv^J+<4h=+ysG68^#rjMrWCiE9{NQ)8@i(f#5&&(-@?b(4en;$qB8F!@M6JffMF*}1{retvK(E;r60 z(On8NCh8Vgrx8G+-h{B92RK`HI>S|z=}H{@k;SN37+(l6xg-DZQ5flDLKNvtKz*}O zaVc}tapfivpORrIc|N+B@CHlc*g4gbP`rrMwg0`w{+msLD})SuIfU)IO%C~9My{(F zO7sUhoIQ)SzCrbgs9kkNwzzGuTr4EGZ5~%$#yq(#y|*v;ro>riGj%m8CnNE zXQtoCAeMN&+MCf>87a5Kl{9m4RStsoVV@_-O|*Lva^mIxMiQFhk#}H@LJcV25JZl# zi0vLZ*1zFNUYvGRK6vE5$*9ZHNO>1l(*}#d3|hSM_t~$3tj*L%`Z-+YMTh%u#Km4Q zpvyh~BD`B9^<7jrsvUl32n8kP&@NQb$XTaKrY|hTxwM{MU6ct9azzly;t~XT^}f`g~AqbwRivMpO2rQ~tH32R%&lObC@e4o=(Z z-P6150b-wsnmU^~MJYpcW_thc)mw!c)u-yFpn2=skp@}pg`7$kf&x&>^> z$In;sjfsg-pXJI zc29niEh=`VM$TBT$)m28H*`t#N_)%42@ihG z!Q#&mgctDDGF&K`(^5w1_j9ieCyih*D&mujv}|{^L64;RvuD*eZ{8FJ?U103q_zX} zR$<nD_mhD=bCid415UNXs#nem(z32DEM z^O*mpA@Q;M_@+sN<;CD6({>rQ1iIU1=JgKw^&^4K$ta`5>&?(Q?{j)sIpV{kztcf~ zzb`Dj1C+k4nj^V%S-tzM(`P|a?LAR!tOoFp01-(Aq_=Q>2W#v{vj@I#B}{Kr{q{G1 z!%rWpl~WxTPN1PZRvg-WhghQe6q=xeJgMFAId7y8^1`uNa0N~X%l-%dYRPr-+lr+9 zP<|aA!qj#V!LgBRhdSMWQ9K@Eio(3Q*Q_$$K64B^I{&@H`CJ<<%wHdFhGd9UGj7di zKl0<$qoxEM4=K#^KIZaQA#ajzB-1T%a@i8z+SghH#UjP+?v6{I#8-4Eu^xQyc9-yXFG;V=$CA+W!ldp8B z1uO*7BiO{kV2|0Jimd<@2)7v+q0pe(YxWgiZpX0q5{2EOoN!kMv-Op~#N)@?tM}I% z*bkmyh4-)6g8U_*hE(#suhi|2Zg-X+HvF}FK0_xP?-v@=<| z_S9ioxAp!;DW(@lPXc~g(T~}_qG`I5{@&!dXu`on)MK|92|@+fj9}V>RV82y#5rFu z?gbnloAJg_7{<3+!exe|nFeJtFyAs=etqd@&6$eIjlXo*E1NU3u<&VK%}y4js`_<> zvTFfHj>T8gb-=E4VHJv`gK>K>(6R;?&0pzuul~WFK5C^8)ZVm7C zl5bSmm_>j1kk0T!T-Q)))@-4-G;fuL#;tB)Nx~Hh-Lb7ZT21b1WtQCGO@+)gnBv}? zHGsJdQ+AHYD@2`GQofC4vSd@LmMHp&l_y(TL9vQ8Z zSbV3pp3QEML`%Xcy$a}BNt^sWefe&;0Eb=GjBC{_{)VENZfqaVyu5FNGjUhpR|$*i zvmMaN?gaF&ezUF8iVE1pix+KdZPkI)Z!h4pC_Dw_$l+(3`U(`nm9XdPM2>R^9cxxq zRh7doCFc%GN+ypUJoqYtT1kmg>AGSW7eUwr72Mg$4~BH5D0B=cxChg*GB38;uF&G5 zV`Cxq^z71lSf)OL==LHSZxBi!)jeB$=`ZbkW%$=ze9g1n#u3!3S7++8B%l9rGbNs8 zzO%2{o?4JdPmOhmRRYTbCxgrL%XGJjr1Go_j2$pxOa}dr99u^ro+)Lj-yGD^)g4HJ zN1M>r8gM{Qt;Yzwjk&Vec6Kiq$X0(AJ%`>_%;l6fc#WEPBjn52E5pyGP`%;q9x^sU zFa4O*a1rT*F^Wcq3o;XK$?twh?{V+=Ti>}|f2a5BhZk*?okGP1MNaddm=8-birpf%gwH^%R@<~GTzPOBJha>>6$#!!Hc7XfMKJ3k#}&y8y?MT# zGSUPJMx8iR78k37PSOfG@riSkk|GX<(kp)oj!-W!*V&-9Xs++9RW_HE?E-3j!2|75 zn{jMjGhZAkGcq1NmLk7nX#$k1ksVyAx`xI@HVhyLuD2n4g$54*5h@c@-Z-bkwnhUf zRsY5s%>Dvm2ah@6QUKM&$1J4bYH!>Yko%YohS(G8D&GNahpC809Gh2UCM4KuypN*h3)*bSd$3;aCX$yEH$arvFeo1W^^SHQ3|G67M-h zp{`q!$3oZ@BR7WJ4Jm&U3aXFQYd<7!RcI=l!Q7UxN=D;E&i{jqOjrHhL;pTTTL8*^ zo~0y`EIN)4PrP(?$a3ZhtHaEf$dvSvyzXZR{QUQQbOpN~`iUjW$Gl_oGJ3mg4*t>! z;zB;Tb?hs27QAQXTIfxce5><96V&d`!Wowk;r+41XLY%49^;1je?xz+mCDU9Q(X}l z8x@n0z3nxC#_%CWM#{j$ngxVx>&!`Opd(QMp75lYN*MwhcBKL=n*mw<{5vA#Hb1|X ztgP%7vIEP+>QH+`XBxP6+t)`%M~_)5?96FlvP|Ddi8$UB71aWD-Z`Ms5-vW)Bz3sA z#tgN2$7u~3>_h1biAN^?*3r?qwxZpyLfX(?72wVs|O*|X| zQp}Q!`NIaF15W9<|H-pVZ^dfBV67KR9|Yxqgy6#*KIc6O6ZFZGd>XB)eISRCOd*E= z_JH#IQdjEh3YXa=P`x%JHoc*5K%Hc9@TZ8*M!$d0joqB-ybroFIskW%48+n%UoRWl zGOR%<^NN&Yw(983Oh#-HVq>!bV}uO;DbN^zclv4lx`&_byn#k2Fksn0@9gScSTlI; zj@TNIwSog15kF3H4P&Q+V&SimrTg46S>bd{rjr)XJ}*nA@`5QH zMBGYXb}TK8k`rnZKJumWy8o2ka}AX=!Pd6V||9iIWR;q>|57ReHc} zJk|sgN4~zg2t(UMb1vIfiAS6NTsurgwMTrMHPm` z*X72wqE->m(9aI5MZ(v$u$cGm90{As!9mHvV_OG%HAu$3ZVf% zMmR?K9&EBv7nn}#lE_;U+as7+H=N{#uwnPQ>in z+r|wrn~eejG-1kJL6;3aZuz?dZfM2idtG(4qHTVm+?<>qFryDRNAI9rAnJ8lWXpGw z&+zmn9*++h8wcFA3}A%;wxJAl?n=~J-U-yu`#;y}pu3*}^Xnn?l^ zsT?P!N+y$I1WkkKq}Dr@3Cm**_k|~w}1XT7LI|IAFm=;t%Iw=4c1D~QYUkQkRy4KK2 zESM$3$(wyzObs6F$HgnZTAzwNu3R8;{XqBk7D^S(*Rj~rH99qpC&U-p10!Cd0hS5)3$_kz8opbEQpPdeK@yWUiG z$N1&I2xeE>=GS@kdHyasnyW-+f4y51rcmOs3H`9&ZT3MfpiiN5mhU}K&Sql$8Cy(0{trW3!sS-h%-3qtc70@k^{_0#MYS0 z;lX}`DKG&B*Qo9SC2avJ+ptbB{i)s*SS+=)M-dYz-V>4KV5ndxa08h;J3Gs4U~<&O z+|8HQ!=D%!7S!O$k(1L4KWydR zN(eQ^&TNr&pXtk3El3TR1>8NQR4HP!K`U2&peL6b=2$G4GG2uQ&fJJO{51&4Iu&^0Q+N_QOtMXelWVY4f&0N1>f@<=B}037bLz>5RE4TZ56D|G;}Bo-&02q}NM!{vwscJ;9-HmnnDunV`oMQ#oPYm^Bl z5^&vXsB?8gFMu9%dTB97TM+mtOTTuJxW&7>zYQX9NU$T<(mq8@)O9jiD|k1Uo}G=_ zN!P1ps?g-?tHzDZnoX%Irt4rd2{^PRI@3QXPE@svV0x-@Awb0;W&q_cNHu$*#|0&!3(JXdrsEFHl$Ypf<&H!Mv@GsAOG-I$^_u5oRm2gVN z8!I{W__N%_c!=RaV(akJi8>on{Cg(2dHvrG%M!PmL!s1`HrL+K{oE*2#bq%uF^z7j zs+|^165+{!ztrfaBmvxw28Bz{?&I*9Xz?TN6M=$t932ZNUrHnsw3KK86AO^!Qzj}l z5!;U-P%AuI`w8C)oDsfe1Ip^yc)lMrO!oqQ(-qTV`=N?|-r^lu#KV(aBv6!4nxbNS z%u!bMIi1)jm2$iUwDas=yerB$*^golpwW#4?C;3jDkV3-RF`Lk+a9>K@JQYoUYHZf%QbdiG3){w{&yB83RC+B1Ggk@v+VRuC|2^8;bAugH=Q#W@i5SUMBj zUG9x|uenSKfHO-y3?4iP0x*EtUNSrxs1VKq(&^bvO5P_@*t#pl!BAB-0)(J3y-y{< zo?mvgw$3~N%;7mOLKP=_k~IaKJHX7mAtPfrRN<;-Y&>RxzevBKcqR}N!s@17miOh0 zECY|q*-{}$Oz8t(-vhVAqH4fv+!zM^yJjcsKr3P2GI_KvPy=KJPVqD)KGRjz(~Bb* zRJtv=AxFS)58Ou(mH=0~WUbVW*SpEb=i0>TZiXraAyImq(<>0f86#Q53;U*j**3xu z=u;eWYP}U|SQ!iUg;|gv3SC&xkt!&6T|T^rGJ=v>=^f{!hpgIldD-i>JsXhr5bS_S z;J)>MdZ9SedHSp!WSy^b{z^lQeTM;wc7*GUQ;x4&Ri{54)aiQ(mw`Uttv>Y>!|L~% zuBKT!c!pqvc|DcATDyqtCiKcu;9fCWW8Md&FOEBEYhtN$MO;p?iT|Ii%fFtAT_a^~ z5CKTl7lA(K9v%-|58K9YQ3+A5 z0|NyE2K%({&sLmaz{pW3;QC&(sS-f;9}2=1(4WJ5_kChw9+-sj6eLanr&cl6)9)AF zt2yO1-ToBJ6UYHt+)%!~U9jbD0>1$QO}ZrvI@aI0s>AA>7<9~}fhw!2HrEgqdyYED z&MiUsR2KLB+Rg{IV(GoPdzB8466ILSEOTvaN~Biin5;2UDaST5dR~~Dx0Sp%JLbT+ ziWKE*(v3p0e+>T-78FEmACBR0ivOro80u!p@4`|^ch%_ElPf*~hQO-4c*->kqS{^n zGP8l_*VOxD`Ckm`0%GSAn;@JaBG920%_bu@~ca$cm|hXg{>`eW@G4rf%?7q*4&dmXna*U_9##2S z?~&aEFwE)_n+%1&YToirf9DsT^dD*h^EE-E)gefMTct%CX)%Eo0u=!1{;BPQWrL~D zI+Tt`#votf)zOIS@>yVmu9Vvrx0Fclw&$xH)7_5hvoI+&~mD& zKvR%FU%g`*I9lLtFHqsxUCXr%5^-o?I>^I&$^+}!ApHu3_TFq!5GBD<<}EKRYB3(r z!rnC$6jTymVVHd`Ykt~xRm8U3k5*N zRyv-Vot0Ixdw=S?KjQ9SC74E?gUC$~ceXIu{Vvqr14511DmQ>@Ui(5kKqd-wvN79l z0wCzadbhNVH4&WVtrIPg#Q?4-0RO)F$`?Hn`o ztDJF{S)d&gorr95-pC?6y4NM!L2|cY`17Qj^B5ss)ht^W{(ciV(2Bok-!1+X3XM#0 z%UrcEeA7g;z`T?Sp3o!{D4s{5-gyYiE{lfk23KCJlINbGD(PhL#W)v*y6!=1T9U^!v!j?Z+C_RZfO<*FxTS5XbP?|J_oKRum8IUHSFC~#kpd;d9a5(7A zrsRc4Aj<0mG5I^iR1wHSIshZ&De(cQrNq0=gVX$hRG|acFS0-aq`|2`G0K!qof9;d zKr8Nptn6$xkQ^=s!%#9n?y+Jf>2)E@+&vYvdzhiGrFYK?WJrLS<=`Vcb*8~NyIoLi z+(2yyH092wOifJ8(EDu#QgY3dF9-4gV4zkeC~bu5yYM80GVs`d%{m9HLs>YeImv_3 z)?Hw%avFfUln!A^*Md7{S08jG+*+WL0;gr&lc74WA6K)2L{Ng=Q+V+H%sOz_Z&yP&vAsB)qK)M5BFNvm zQ7Y-Ky9=eI8+Ty;?6q2>&|YA|D#O@F?fPuDIjWaZ3!x5nUw>`qF1O`crb8l>~gnsja&F&ENx^8Mg=}y%7Ey5OuvDhPFv$7 zTVcO)9;>uxDDCfA6XC{fkWP9iGi{QaUhEDzAeI{gEtmSY41jSTJ+xf=iHN(|}-a-02y=C5nO3g&1Gx9$zT)CE2X6r74C z_9(&@YIbEGRy{zv?ZMSeEEemVqgVj4*O?U+6*EF=lv-3|aQp9gmMPrUv0?rq3XRsF z=+kui3AvyQF$U#&DodX2-oc!Ed_hM>GlXz<%gB4_cNC#mX0E#4QOthO?hWfLpC7kN42@TdUOIDd-#$&QW!*H9-<}l`mX{NyCGycSs>a^53vNMt;wted z-bPO(vOt8uX7}2X-+mKntUZ7{PVe=N`4?PZIu3Abm!-_E&a*}5#P0eanvflro%QHE zp9f&RX*clOL_5E&5WfuIdS^hcJhK2O4s=*buYKw%0YPqZhPhTGh;9uSEyC(w=OTbc zSp`TnDT-`u;6VjA1K5hc$n05$o|6|rzjD^Z7JzT0rGv$#_44*-Dj=CN9amXUpbF+> zSByGCGJgC}0f6w%#TJ7ClLvbQSoTFe%^5J8HLSE6w3~4qK0XV^`=tOsrhSL-mjVbm zA&o*y10YlX#c!|4uZQwAG_gV7h|T>W_Y;^pkF~7c{tE{o_6!G( zYZYJHnz^+{92|UP!ixO91?vV}GWsf$j89rLh6KM@!?k>v=w07uNBs6KN+=Xc8SJkl zFc&8U+)Yq^<%?>*5!-h2Lu)4ZUm^7DIB@jH^)&o505%81V6dIIrTgqVPi}UUfk`{g zCEY-}t|9ZuJOz6LIG>JP-`JP~;ZG)R2$WWUSyurt?lBVFw_b|C0|1vE1DO2*%q&Q} zKWLKn-7Av@*>)@{D{{Rz&sT$Te;xJp^(mmdXK*kFL}TEXf(5m}vcZv!7k8H1-CV*` z`g{O%vjH{P2Td)LPQcf6gIWgB&Tyye!_&6>ARr%>0vv)SD=RC2NopV@Y-wrf>F!QW zOXIfdD|`UDgsTjEwqS69P;{scIp z>LB^p(xT{@kiN0uW;ar!56TcZZi|Dw3Y3p-pqF7;8tCduN(2}w&`lXpO@2>lhjMjy z&jzjw)bm;_ifrudaRBudn|wV3f)u#p%pSM}l)6)N>!iBAKBdaJU6TjacgwIwkMccU z4JUrs@c>3m(tVLqccN6HfX7m%)XT;bRr(inm{`e<)lD7 z;sxq$PmOn<5B}yc7-f8_qL%~VdYiWIl$NCvhU^P@#cW?E&jC1$w3jL>+OV| zXS{l9klb>_P+6Yyh}onrFM`W3l0Q2RJ=eTDhpxFpYx*mg{bfqPh5y*~@ckWQ6JdLz zhQuC3xJ#~1pU*V1)~2wH6;l0Poq#3Qm+|ZPbihMmv_$G%00c~pDf9fU0*Ua z>M$&M)%t(-965YiO%X7=8HB77v0sxaHS$NNeI{!;&h*ffp13;ZG6N+{1&1p;YLj1? zP7F-IlI6^TWQQ_j`${{9PHo}738mhzRHYhluE%iun5BBilzI|wO3D2BjecDR)3*z0 zCY*+Oq8LSY<%|b2`tY#iu$9Rxm>U^z^LM46MpZ*UXVD%*$+n^#OD=xzlK)0-IiKUo zxI_NFZCa*j;Ncfm)b>zirXO})#^wTDVC{L)yS5iu1YVvtoQ41IFX!1Jw}3H-y8?AQ zRrZ#j-!_Xjpb9L(!aOx+Hk$u&4LM*+hsVg~(K!V&%{`0)huEoxOKc_RBFl5P9kH@$pU#Vbw%1y*MSj6t7~s300J)LR531itf%(ld5y~}UHsKE z{Ym7vkwz|zn@D`Sj@rnjTyL?&g3Reo!JIIkE1rcdAp?6o&(1DI{f@s?f=Gbqgk%m1caP^M@$f=issA;>;)rEXEYP7AHwP?tDl`Y(Q z-z!^A=>2|*(+<%VBh{?7|06~*KJLzj$_E1CD!RGfC1vX|HeTKE7@Xjkq? zx66RtIV*AlQd2HyrMFJqZUAlFO{dV+DWtLApPp6(R0m?qcaq{isOIOYZi#A#-&l`* z;g5=ReY*bb`0j(eifqg1?+iIEjMQ|#{q=Lke}3?<>$7~BR1W7PGzJIx6x6bQj4NSeKkixxZ+-8#L43&y%aE3b-`*`tyE9jB{IL3Js}Yqf?{Tl_D#{ zwR9Ix%EhR97^Zj(bzK?exMycJ$#>?2{4-3d?)%XH-IaXSP)A|4KFq2|4)T!Ma<_qT z@{!W<#|<5D#w}%-gKOu#+Q;*8Sw46sg{S}jK*D3%g> z61Q6Iw?xHM@+%SwT67r(*?H6-o&Dc7!=ptp5|Ml^KiV?D$hwDRSMx*fe2nwsu1_Cg zDgrvJd4rzg#7?mw1PgI3!0(BcT{X(fQN*@peHPi=3*(7uPVgI~ns$Nspp@^`&N>vU zm%UFo9atlBb}MGRLT=2EuUYNF60*KwaZ>le8pF}w^}JvAor;Rdz7VU;OBcz!?WknC zJc{Q@>FfR>)tt?fx<@tOO#|^mp03ZL)zX*x?78Eb^PK~?RYRMMg)-WP*4N@Z7jqQ~ zlK|EV*+zxX>v{>SGS5ms}cg{$@Hn%Luh*IFMlS9_K$Im|v+NoHp~ zy&-z+;d|;j+^9D0bPW!f!@m4L@3zgH93u)*n;}pO3G(YU-L0X=TCb7gEfXB;zur+< z;^#H` ztQxfoRf3jualE=<$Axb*LA(G@q9gA zf~v|*+}f%Soqlww9j!V$EJ^42cbI4vT?5JB1%(v(Pxt=RF`9}vX8Ne+#4JOixrAt$ zv(UJ0L>u}Y#Ot9W>?yrfnWn!bV^1Pk&wmUt=chST4zW)M8`iv<%P>;o6bIAAZoF_0 zPJHz5A#@ROj<=g=Tk9k>K2pc!83HLZhAcT@dG855Y*iO)o-^Uz2fb5KQy5*c@@_|8 zMrtC(0iLMdKImGg-X4EcNff-kNNtk4Pq4T}AA6mu!EmS5pHbq7dWN`*I$}L+$rK&D z@EP{6!-;F8uO!_$Z%kvzqiD8p-7qIi6Xi}Fiju9P8<6}*RyM7Nr=f?L5kPq8{*0hb z^=r%NvC+CaV@`X}un}H%!SEKxa0uhaV9n7?%KD63{GJq*`F8iezDHeIy45H#j3cs; z$v0qTu^4<{p3_CahXnKhw))W}_O*@6CYnAIqSLFA)5<_O|EV)ZI>BCaavjL~Wr@j{ zUkfWbhp4~g(%3pv!+pfoXUA>jRJXX|@vpb_eJeg$zyCy#@uf=g`!QGn0cP)9`$I?o#55Wz|3(R;T zd7ZtR^^hmdZ9%L!TM||BGlY2mB?nJ_-hEfgliEJU8yzaNeKQXTca$LiDEKe)eRnb+ zqq1tu?xV@4f~r~kjCwKRB|PTpajM>z(sPTp+`nRy@7sz z{4UePI-0BY!d3tAP*PRk%lCTp_x2?IjxG2{nHJLgG#At@qlcB(t5?1hJyF^krd=OT zXd!ssm!1ScK8KcWKKl>J9>f1ARv zQWx>AKLZ*ceEI-fa$``SZKX`E=V+)JB?Bg}C&P-IvC_NDEXE5?%AnE9?6q{}AMU%_ zU{{eF0GNEG__dz>FqdysP9sMr9=_0dv9KVmg!#@0q3(oMz-}~`qHt0voR(^QKv3t6 zoF4$w>>@7Kdn)uN=~5r(-*xzh#T2!a7Et1bWt14CcKU7zVtx)y50)?Nl)Cv1ji|={ zN@eQM2ux@1kR2O(U&;i?B8t{~MbPx=TQRG9%ToFE zjR7mJbmR$obF~MdX-VE)=z*K(lY?giVV>tU;jDtFU$f4S7!S~(95e?sMEneFYNaKUzrUG1m2x$j{nxv7x0&R#3_;HC z^{2c;#J4I>el^B+G4p>ajOfb@bYghqb*VXPd%*;0KVi|q0C#Gj>`OgRmGvtqF+U#m z^ioRziyPhA8Dmh#n(iR@X_U$45>sYM=0O8bbs$^ceXLSfA98_8o-F-(vvdoS%NJau zNxSLytkzr#XzPXaayp9iqRkry1(&rcRv9V=fx}_Kk2q3vtRjhh!>H^0#`WW%SA1APXAOXN-@##`^2$@-rNtxp}GL4MG}-UL6vF9UnzldO$w11!=$ zAn07|lqlj&EU`RM;F8v+a31yJgo};3BMM2w#HH)_6zze@=2L~9;-?f{`#HUnef`O$ z#TQ78p^ZR|%}leLGLF90hVK3Bhd+o8vxw~ehf&}W%&trz+32b#iE-yFswq*W)@4|` zxzTT=K zFWlS5SXF#7J*s;@O`jcH@lS@~^%!qpUNMShcLpvqx&JdfD#YZs9iw@wxqqY3) zgmi6>QwA-|a)#rGTixF9lh9jlR*z!9OpWH*N8j~Pjr*F2$-wiWHQbCN|nnid6GCh`gRKG^3~KNrg7#>flD-R zz^Jc(z7sH5ceUD|Nbk4nXii|tYR3?jCVe&Yx*U^vV?{5&7kRDK0YeYFk{=sj%?lln zYq+v0g$P?-hfYlo315v=$tFMjdcl=brXapJh)mIE1;zJ_CE5K&?G=D=BR78SzlB79 zJ#J=MWS~|lcH``N;eIu5oM6Zhi>-)G$ggkfu~v%!^%qU*ft@VLWas9_G_FI zx3}o!3IzxN<%Fc-c(K#br6`jQ>N!E;d@}9o%4;0qHcGN&fI20V2_f7*S^2;O;}-j>Mg;6BNciOvWMWzy6#$v$d4LvqQccQLKZouB5x zkY-1n=f^I<$&G-;Qd$M4)RyB$g2uO1W&O(pm1J?~5{G#8Sz*J79@xGoU^0-%oy?+I zVqoU9qfRY)+t5r-(!pryl2A!{-m9UmYKYy+Wmnt5=RIueonCAG5t(L{gZ%-0e?7dv zjXLW}9X4dEs7wD@diAz)CPwLDd9qt&Nf!N)z=$xhT_e$UnzEp(9`n<>>ROyKQQIa6 zPuQ+hEvaw*p9KKjYJFX9KMD%_61Kkau=arr^LhtaP~K#F#F!_iaSzV>+Tqr|E?;GG z3F2|0dnS0Zi*ziS26Ll?nKddWEevBl-(HPH6?u;`M6ucs+u_?K110-@Bkr?bV)v8t z6go)$3nL{6xcY`hllnRb#^v15XKus?S|1&(%$AB&52pwZaelA;P1HBX2~a5;6sw$N zXnSlaW#_=i8u=Bbk99LrbOu(v$@`#g_6sFI z=z>SK7Kl7c~R-6E1 zwQ#^xpEZ)>`{>24-hkKH$HPzo{C?8eegjdx=2L+;GyK)9rzKZiGIH;Xxzd&*_g@H- ze(N>&x9f$0hUD%S%z`KPw(`&}+m{V|2M!m8{VI)FkUjwf+-7mmiq%o~x6aX%rtFm) zga9+Ut3=5^1!9T>6Lro`yuI!dH#7$W&+%NuSn59CRNw-hZkcp`(v*eAvVWX!RIMd? zD|i(a#FgoatkgdIj~1ZaSN)hW2$-KW+f_@6@QdquY#e@7a3wyD5%946&4ojruL$~W zzqwoAZMs`@Hj5PNg3YrxXgLnvP&|q>WZ!7Am)YOthf=biY~q3g*Cb<*UBB`bdgW#7 z4|z@(zrUSyCBD<-)VbH}?62iO+&wSjY6{{$HLg#}zCnRcgCC|7@{EG?zR7K5mYBGt z7XbR!G&2*6v*2=5038rc>-4CHW)iBBR|0`p4`)q$R0=?{Kk}_Kj%i-dJNkWWSF-lY zW$#CGU6vwNQqUNT16<3aRsSdDp+d9Acs0y!Rw$F%Q5K{;xP-x%w4IVj+yQJmp^O}1wr=tNyg<>d2+q9I#&DJGuagu`kStnkiLe^xf zzNdHrG2*wKwp6{i+#iVhkEi{8ozCPJyy8^d(#IVNi;YO3*+&l|`8=-lofer%$JPVw z6p1g*kO3=SDfrQQ5jh51jYvkd#VYJxe2!Op($lHiPe{O%c*TAfA@-cCx%9ok&rY&a zdWd$O+7&Z#7p#js7QTp-hu8L||Izfiu>!p^*Ian(cUc0#{TW5iJ`yikjJ8DIdkp(V zE&j!zdQ|~!K-{nWaePo1yJ{+5c)G|n)Kn`=D*HJCJm~N6EZyY;HWeDzH?`mLoLpzY zpe&O?B<*EukB{yJz`4bVBJZB;Toc6|rOX4a^Ma9{76V_@9KgXdS)&_-Fs(J=Gik{G ze1~;?bL5G6Lh(qWib7tTxuROZT)AXph3c_3>5+-J+FS?Oeseptsi${tyvC+BHWRF; zU87~xQ?C`p%0xWPUK?3Ko)mg{(uI-Te(A@)2{cgNUlT^WZ8o=)L)*aHAse(fht*c{ z>cEwz@i-^kXMoF!exc4}{wpBbHFpuSnTI~^KOgqE+A8N&tjJWLHe#T>3La`n7OXyN z*Cs{~H~MD@YeOZA_JQ&-m>Dmjq6*pi6CQ-LU&BVZ@(93S1)0$jfMnQ~SRKDb9NJ7T z{;UVtJKdys;lL@^G%Ry>v<3EKoF*rd{V`p%Ls6B z4w>=YA|Zb-1~+>gLd-^pk?}o zBT&*n54!75D69`JOp?n5Gy{>XYm0~aznhG1J!XD@-$OU;_BHo6m08Tjuz43R+&Y7E z{#mJC+jAU4SGvhO>>W{@m4jD2C@K@okRarf`kG7RGh0{U7gdnf%CP+`EG?>8~W?UBIa+4$*Gpn_)Y#8cI@tVur-Dr}XNkmJl^fYWE9#I|i> z63(u64SlM=MfB!0%Rj>Q9BtEULm=v6-Qi`%omO_X4vW#OX(w8kgH1&otZv0C%#iGF zaLgb427=4(7a~XF)_&rO{JN=mexhw)HTGr7K25O*^THQPhqKJTSP%HTAlkc`tmcXa zdMf^YaQ*{!n9h(ypy!slQoBZaN&Mm$Efdup39r@RX;ZIF9pe4q<)ag=6mA3JDtb1! ziu%}Nmdh;9F0&5-@-xOg-8(*-*G%+WYO4iz8=0>@{PSPt#WxlDx_-=<3DTd%Pi(nZ zz8w~Cnt$mvX_WZhmHSVEbYEV4d!1P|@69XbZ$(M&cT6p1_010a?ow%WSw0+*r}w?Kf|k+v3SZZ{EA|2lYeZxA5|vec~x0D@(yny28qc%HS3k* z3)UrKH;h2ZFtJmx4Rt`ll5JN9q?aVM9Kl9&Zkp$|Fi_;)^Hy4Aq>DIB?5;-L-?sHf zL$efm)w>j{K#C{hQlve$2G0^c_#M5JsjqWfwi_q)CAzeds8J4 z6*W6-Q!Z_f;p(bxEuhQL2!0YEbsjn;SS+qT3AnZD9qeD+?&XNnJ|}$y`gduz(e1;a z@WKwYDW9GUnb|*@I|4Y&YYne@=q{8(0JZJLnV-|pUe1|Gaz#*L9C0E$sl6I@V7@!PA`TevEcyoE+bl_gac0I95ACJR%^&_xj-1ZjjPCEG)69S{=Q_(Q zUPHzvh;Yl&50{bHrL2)7Lw-5S$Q08+nSg)cHchMDx%ZgbZTL|D>#N{A3)ep!^H42T zkeK-oK9l$GgENL~lHrdHZ=^*r|+i%7V$vR z$=e>&fUuM)Pt2lbM((#;ry;glrxi_y!?KwJ;RyeNGM!zfzM%0`-{N!#hr>F;SbZr(WpE8rg!v~&%iBMaMtRF3Ju@lpx2?#LA-D2!u<`YCu(>jL;Dq>D*brHqEryY zjZ{J2sc3|CNr?eZaa)?pn<+uM&60*aIW8{v6O8}f8ogqFIv>UEVIU-8QT@V#H_KePNUi})xFGu zfM}Sgo?&8HIuhENNob&|RV_Q`*}wuVw@QRi6>SV$&G%QT3xT=&+HS#rFzNE|whT z^2#c7laO;@s&7cW-X=e}TG4XIX?%$GBJ6y!oeD@S$VOlXuV=|h3gKXSE#7tO8@jcj zTduE8Fk+uJ89x@68fY5o+E%mj#psU>(68*TE16d{YBlb2oa*gz`1MUnIZS1kkoq&c ziD!Cpd*fA#L+U2lg5GDUM}0Nmp>z}IdFfA>-})ah#)qG^#(_O1?lA%*IWcg_Vp4#* z_eDs5l{b9f(+nOyv}EshNbQ6gg7)mukk$w}ns}9E^l>5ND8oSj-}quI%|in5yTrFc zl7lmP^So8B+k1I0a!wWmc1CKfhu;Y5RN#|=dU>js=)QV&=&SNCyV_wqy+2>BH|snC zfESZBCgcQ{4D@mzN{_aAoN4`05+rZ{&bSTN41b3Q!sZSaqaB9|=qCk`B^Zt8LDvO~ z3#&Av+IgO!7R3vBmi#9BQCvuka$y}k_lY{kgaeoA!On+d(jI09!AE)Xoc`veb2j&( z-}+i^rgUvMYlKKR$qi~c|0BO^iVpv+*IBgy2pDnMv=*!K8DNfS({R`}bF3MC^ zddELF$ED0=SVbWq@7~j$s{*@C#hVC6wdZwAHa&jB)rYT6j~7!76rmMUfjBd?FP44s zaGTmdVOx>(dt*aMTKPu_WJ$nDy5V)L1{#DjC&55#XhW&rj}qk@l;K{US?B3T&#_-2 zwUX;=!>zBx0WRQruQ3^zF{30^cF91^9C>Am(yHGavjrA^zX^B3j`v&zJZ>r$8C&Ac z>nd?qH8jgKV_Nx_liz0*rIA#50yIkkj15AJiei@UrR<9USLQUp`7~KP9ilVr347QL zdCI9TbKdzC(J`UZywH5obqim>pWo~|5Ubb=L(ABk5kx7{`nNdu6b)E9JB52ex$w0Pg z-dVFK*^i9q{~XrYQ;WeU-EbM^EL93Z=FdaHl;G|4jf@~NeeE*rqXI%@yeWsv#o>A{ zIk(Ih2_qx1BH5#*>zl!*&B5Jog@8{Dnny8Ku3_bvV-&c@ZPK&PN61)Ky+Jm$KD1W}eR6}hxjpH>o{yCM`ci9jgx$i|3+5cl`1m)omcYO z3gyVn;!Q)G$OOKA$@W5XzI+COG$OKpC z!N+XTk(Y{_C|V?^K?SxShKZk|MIIVIv`UCInfu|XF(J$T!8lzz+fYTN0SpF1Ny}>T z+haeOf*FNF3JU1K3W3;qkkmDHuX7+hb>fN7PsGzhL$_R ziPf$fZ&{2pW!-cSFP1f|ujt!NsV(G56!a$cHfGw}Aom?dOHzJH*`Ek);+*hJc}8^J z^d;)`d)ZMtpJ`Z(NqhN;1&3BHtEfz=m7EnBry!@yUbIx#rjB-Rm$jgNT5=NG8d>cD zye6}`-#f?@u6VTkhZ%WU#j|?lI>ze{WK@OitJCEg6TaBYcw|MFtvFLo@)T}+M6jB? zuOi{G-FD>K1S+tLGc1$E_E`|a5lZ9@+HoxUrPS}>XPezPfm-jp8q}3@P{wGrYR86O z+`Xqh&0Qs>T4fVoU$o_(8KJ)rg-$o$wCax(@jfK|z`ZR~ttAu^m01_G9S7SVo}mAV z-~GGQO=XP*wXv)=(aBtrhsqa6TEBwts*_rc0uCkVulfy5R;#8XqLGiZ7FZOop#^BF zltW+^_$CB?cyb8gXl%G(!zf1Ou*w!uiUM!i>p@K5bemK3R}qL%QtWe_^5++Wy0VYf zWz;P`=UQ}f>JX8UiI|onYMn9-=7rvlz`lYo<6VeeWs=Jz0 zjojc6S+ye;5Utd0R|4bC)9$U0=G4M~BTn7=;^0tTqxHdCO}iy9Y8h`EFw-hkc0F+N zTc6=o&{D`7%bL2q)k6n|j`4Qg*_QgEsSE>2j161DUv7YzRHf5>SpF zs;>6{)K4WkO_mZqShik7_&aAyIy;Tz^5{X&?Sjndv75scSk5txaOGZhc#yDCssGZA zqcOC@(I|8Xdd?N7b%Qe5Zz_;n5F23y1T_LvgH4(z02)B$kH5a1nqKZ1R@QaV)>c|Z zy@EIIl7VJmDavLqNY#e1q)1dZm2$qN78zFJJEy&OdY$$tOwMlkEN&_qFK3;a<30zR81J3e{NB&tI67qeMhM8o z{G9HUm>$<~@bN@|6W;Ajp?@Xon6%1`f*3=|;O8zUCk7lGk~4OH``dr4MtbY8d*+>w z>_5jmZ&tcIk~rTjVh@M%2z^%?9TqplqUYLJVnhgj3CRJ(PVpvsTT-in30&T!2C|zD zhn_lZ8Y*NPDQv1^yLP97JlAx00?oyg)1nKfra(^S4O%Mu8#h2V!s?yp+-Hu^7gt-q zR$s@B7J$Spx1ba~^;wJ}O2vX)oA{lwx&7cBAg0)HYVaIuC zu>9HkDS!MWO<1#j%(j*cifaP-Im%Um*QD^e-s+JLpm1Yc!-vjnoID{#ib*6B1HH`( z9XwLNvl9oGZ9LXxeNU>NaJbq*bRcr})&2PjYwJ4XpNTVUv zF<9NG$7#5fhaQ0U?Oc=_u3iUVwz^ZRd1&bAtS6m5*2wRg$y;$@<)aE$A{q)Bs=7Cw zjMV+L&k33}1}10X()(1kLc=4w&codFnUHizBs@t6AC72Co=pf6jusH;<}oIDk+Zx# zbB*NX4NHV?UHV=bb`Ih%Hn|EqiU+~AJJ85&$-u2%r=#&3S4ZSNL2SF=`i6!`7Io*L z(gP;Zw+r|9IyHUbOuLhW^28lBZ)OFg)T3@aqYycrI`u3%RjhMTyOMHJRFt-xUian3i8Ob(v{? zF($(`aDG_)e?xm}%3I$4e5V2J!xo`A^vchWkzu9MhHH)h-MF=G3t(oO4Z_JXY zV_7co<%ce1PvGtZ?YLbchUQ^undlZPoz^A9=dg0s_iwvWl2@{B1-_A*^e<$kFbfzB zlEYj(Q?b6DVnmy)k|fM<4#G-*Jzd zl9eE5iu)5QrbPd@6f4`O{mAD{yv}to-};U5zZpLVWrZmjpL)E5TjFJ&KD zHhMGIBqw}@yRm*?qz30%sVD&zp+cPo3|Yu-aYNtq(r~7$nVQVHvCnHL`o&~6g65@$ ztoWzI!uI^O#!grr?RVuM_DhEBNwFyd5pF9MQ887xmc{{%0oKbMq_&3H-hb6JzMuJn z?TUKh)YPLSwkPg#fllo5w5`Qhzn$o8nkH%_3!fx=xO*58Uj*1{H3`V{ZbM_|tUs8137WdZ9 z0>?y0cRspyj&`b<`KrLFGBfSTz1QT)9y0_6NKZqXgQGtej0g%1^%>egp55C@A@PwljRjO6ui0^;f48HQ5v5H^bj%f~u90GUqPd8uCYJNDjBbBw;UB+Yz* ziA$K#i8KSTW}c!d^JEy4Z5eM}cHQfEbiI|g#e%+iL4cz1)Mxk8%td8+^mH=vRG1Qc z=l3r(H-M*QY`(%@g8aGBC$_af6)pk8@xhT95`CT`F>T1FObK}YZt zyQ0UU=VSfXU;op%$&|$;)d%ymmmCo@VP=X6Ee~Q=j)D0O?bbcflR9AqTvFNPb2Igh z;O-(STMfm}aTl?jxE_6W5>p?}BK9(@n=lK}mC0Q{r@r`(43K)9>8KsMR;Iew5!byv6=G#zS-3X z<4Nan?hEOc-JBx7Ixqwz(|beH0|V_AJsX_-=tLBl;GSOqGF(eHHD!VDgF4D6#&#w4 zj~;hWBDd9vXf=C;6GBHHo^Fa_bI?+5$m}p|qEDg2Vea!f&B32+2W}zapQygUufNkG zQKz@sPFpJycpt1kr;NQkHUBcHzi`3gku?SNYJ9nkXRQ0WVh!1 zN|RFP_CZ9Si2k`2D`d*2NcWVl<5O!pNXJ^r-l)b>r2|lkaRN}u})nm9SWkityJmeNNUCwvUN!*-jyMh^cm(w z1!DiA*?#bOwn@pTtV(<0J){+L>RL8mnpo#5A-uXko81xeR%Go`Y-~2&0dHUE_fmgs z5c6BD=N-O%7VVUG^@&~GZA@{z0>7~xR)Nh5N@89cVqVEL9f>72Lpn~bQn zBeyL>ODb1UVc9I&22afV!S?$i2czDK6Vcm{xzofTGZE4Rv&`}3j%%T)Ubl=3eLCI$ z(E{|BiHOiCb`a-2*d)fzEX$tizm-P);;p|)9}$dbbVal&Vt?Sil&ZJ}*8HgEZJOd{ zbwtFw$n!w%fTBp&$&r0e!FPol75?d`f7v(XMXnD-R2U~d)u!gTt`CV3R~YO2fM`@* zHv0Uot#g;#aSea}O*-cazw;(7(H$cy!T!o@ayNO9f;eYhhW0*n{!Saa5D}ZV3+;Pw zUG^#h6EyLiXu@w5V0WJXK*j|leJP_hD}arC$Q$M#$oGToYJ3bW)xgi|gk{+PVsaxN zC4vhjR*6m2=pSCgFQeN$04p-bvb=v)@SjEm$nbM$g-%r&*H!St@SYl-`&e;5jwcp_K*SaU^J8zP>$`EU-jSiDvVx$~Xg{Q{o%60f( z>DbYzRL~KXvZtmiYm2xz*O;v%VNi{H@_93|6%uXL*WRVpW%96ZKFsSKF#>%9|L<&j zQB$9+&JOJfueY@sxA{!y4Se zoJR}TP-pFSTvF5H(({n$7!$8Kr|luxryXN8C4>EJgf&4q zWWm*z&CHI$M{?!Rad?jnaL43O@?qa)+OGC79B;!9%hj)Uq-hxW5I;6f)d{1ao?`#> zjKA!Nj8wXh$`1^~Ee9pw+{3I_yoOq)EYxqm(+n-d!ld&{%D>@0(6&lC-_jZn%JU5^ zcOG6(uO=wlv2t`rC;_b!Jk(+$snDOzr4j;6q_gAM80oMN(nK6y3qLK3=@ZH7G{#!Q z+N+6BhB-*CPnI=8p6~bC&tQhK)a%+Kb;m%qP5M{JFzUJUY|JiQVy@cpa`9?b#>dEc zcJ89DcNyXz-M4ri`uWkP_kX_9F~S+(%sfE9uj@a%!=rZh$Fz^ul<*wR<1aDiS*KvWAk!i zGi<%Sz<6DNmk1mzU8MhjkPowYE0~FUgBB{ps!bXw>4Klxj`aM%-?uZka=o^Tm))cl z&c6(k8^f=r{DK>-;jXP&r6>MzfBWc)!`ey%tcRuM8xI64z#OzPnv@1TS5O-YOS0;L zA=iEH-;x$J5_qbdM)EwK0C*T&V(F}TxDt2g-eslR|K;aQWBG#GmAmh#bm4(f=aHJP zX;XrQ)+O%mQtwyz0T|8A-JQRm{S-N;UbtrR+~vO6D0{((NqMQGwph*n$Vp#ml3Cd2 zE_k2_MBO#GE9EQva1o5l4D>(HeGj&6^0_Z>MhdYkafHqyu<%Ma;J+ zSKxl{yX!x&_vByuksww3))qFmkf^0u*3k+YFGaWsQ zMqj;4UnW9WPyFt;ON+YPw_m$>W%Nx*JRW`(+g_t4@a88gvP3j{y5j09@f-i8Pf&gq zeChXP3zHPYLK@h<#&c}?gISaX4=Q&GLc06qJ*|mYxtSTjaRsF|=70060dq(Jf3TeY zKEjx%U*-NCrr>h{`{>J{s>!vKt@noBKk4jOdO`ly2R=L3Q_3w7GQuXQBx?#A zc=1bq9Uo5&K}~B3{Hm=f0%ixWEw^N?!TTl5$IA*rk7!Pq-gr^TU)A-ZJ^yq2+X8hV zHRLScVu6s`|IDGrDS3gzC?nn0!(bjkozXHzlh(=^uJqP7tT5Z+h7?)$*S`#Cn%|Z>=)Y#E;Wqy+a_{Py!Ey)# z$fmO+WMbw!jlELfI1e~@r%cnC?pj03woyZZ*x4{OwP+~YdS}-#tC0TYnL?{d#fOT!97!vZPMR!E|+t%A3E9GBYHFC@mYdP z^H~`%5L>MGk?Jbl@bK*`Guj_B<|?T}?`LoZ7m&Xw4!!-~JMawhy&hHeQ%K}D>XZpE z&JB>QT=Lk>pv@6}MZJ~L!#%L2sc9b6aI+M@Um02LWsD;vBAW(9&CGfVkkpXslF+x1 z>s7Xa{i46!il%=|K6_UdA+J7qH!L~05f;4bR`fm?LgIW(V14xM_#24ec?n`IZ*)<| zcvrO%W_!?XVQwk^br<~kehw?GL>o?J`WLnBqPhuP%SA0UwS2w8T?);JC93JIpYC<; z$B&~o~|)!zIZYNCo*~ z!dK38DJRRrN=61o#&CV92MOoa63K)g)9)JVW`Fof<;XJ`pii9 zl9;(`UMzGi^bLLWrmN&q20o;EPe0)XM0eA}Saa#eu%cpZcB!qUS5m^JC%o~zb&2XJ+wN=yADx|SjxsE zeX=3%ten5Uu=Yu-!0>U>;*!o=Q1b3~CH;4Ip8&7>`ttZZuS?TrRAB&~`(1WZb(2=x z`6WWqpP70tJL4AlLstW2>C1S=dL4C|eGPL@sIU3U4R!J^CXm*w>y*>!Hj6%|;_#kL&B+PC~cxpuIlU09o@eNQ9LX!_m zTpFAWc2vLbTbroU)PU_JA7G{E@O9sxIiS<#A(#zFo@1rpvZM|UHw8=Qd3ZIlyNghG zs8Ndu=aeY;jDK8gc=*BU!lYF5*C!5MSB%B=!kn5@q?ViyjAXuiay+;j9;TNHc;-N( zX<1X7yc73|%8dVJa8$oj2!)q6kgrM)%yy$jHXq7TzR^_wM4D-{me*h zhu1o3shd(uZ``GC#dWmBX5ydR6hUu%7i~;pVDyl{h?oJnZ_^hidOJ!<)ip21nq7rh zKcS&eTs?sDcUGu|K>d3Nl#ag89GObMxQC?=2<=B=g)n$ zdr!h?>aq33I%v9~b-sLTOD&=yIq1vx3%R8`i)eWZq&hn&oiA`Q05n~ zVRH4J1n-1wmgS2GdPYV~Rns;Q*GBev+h}2PPJTo?Z%3W2^x+e_%x+|35>YvJdd+L;HYaCn zw}FLr&vSusP#ieD> zbv8~dx;t&~Mf=hI&VMldbh28Vj1xWoW&T!v=$(V#Hf?nCnY%DJQ7fq|r|~B{kjyg# z3W_BgaxO?C^t203x8&*qtrf>{ku4#)kB_Ac1D>WWO_{bg=>;;z+IM|XIqO}Z1z?+k z#I=P*Zk|Ez|2RYaX>01`0JEL22LUf&J$S$@d@2CUME{T*) z;nTd2haI;ENemsY5_!cp*2)vTR?b#z+MgbCV1+W-Y0G8_=jeo^&*hv$=Y9Nx!VQwF4L)10eC>+8|sr+1g{$n z1?VC*Z`Tyg0-Zn2K#+J{r)|~m_Ft_m>|r9ESm9A1YpLo^O>tRli$v7&iB;kT-R;I>?bKx7nJTvZbGS^)Hve!U( zG?!GCBmzI0KS|uRk1u(0{u)(qbpHOe>;&n7ODtIVL+yJE zq{-4hhtd0_&Jj^N{T^J-lx0cJ}-a@74k)fA0OfV}dTy0wYy?HtW@k^A;-RKJu(du)1m$I!F8F@IW^?dNG9~ zXXoN{y1mUYOj(>gW0A5xH)P6J`1a@Pu4$LNNVIiYR;Ye5j_x}IdpiJ}xA&U0KH(A< z?>A}b!2maq)lx!_L$4JoAI5)}W^*0^|4v&U*TtJX1G#Mx{FH<4#-Fv1)HOMM7+LA% z=sSsux8wb~U;3b6Fb?>?_FXk;TARg#Rdh&>XZjxNuc8rvo&brDeD_O`P_a>t)gwrQ zJUwo!v)1;K$g)qeb}Q=WLZjNP1aGQVfisv|$P4jcSP8=;bp`5X3CC2Yo|jfauMfhf z(b$P3C&kH>et7@MuC5w64zK&Zg69#0HH5(?SdkiJlbTPZ+H~e%*U0>vKCB$vCG*X>rKy?jjY38oXT;j@QJ4 z)Ayo1g{7P6DY;en_=wjyksT=urqD~5TxBSWu(l)^BaPlA!-yRos`RBWc;n(_3ncD_ zT8`zHduHtrmqxd)K;TI1vxj$!(A7Z3@fwIG5G>0X_Ynum{_T=3bp>LEhq+F@2p z9ap%(63yl>zT&`A?Swn3UM;!(%1v|VY-ts?a^^pmP(g8m{ ztIk;whtaPJR98W2%6U~lOSt0y@Vl1yl(eJfS=)+h)(+=BcZ%(!F?)t z4Vtn^`c@M$V$-ju=X)~SeiO6(ZVDtHh_)?oqM#q)9dZXr}(An`HDnU~s!O^%^2LbFX`IrY81!5;8EHsM6fk ze)mF5C(}vhExubh6jEx%G`_i_vES%^%?w%s{p%f}ui#sju?%ozD zUfiL$1a}XV;#S0{n7E__ZTjox;T)reJ<^JrUn}epdhDsIll?*a3d!lU++dE+1u4 z{qQuQf4y0l0P+d;_d~IYb35QVA~>Po4?>**IbM`88q7PqeHa3*90Kk@q~fs4&q}fcvU)D8@Ek!cx>lq zr_Z7_ZjNIKwDSVg$+g*i8Atu2H5YbPI$KfuP3QzjhXO0To?y1*=xRJz2CWQ?OmyH+ zlqpG% z3R@3OIjft_9YMQH6@|qEi2@QI$go`Q8#MCYvWC~!#H=t!qsD)#9Z!Iefr0O?29RU- zI@3M(R=49Wg!?hF+I<7f0-~-o^gJ=wXCuTGf8-E$w})_Gba!_@IxD*!CZ|xc$47yT zCC4vr*0Q|y5eu948pTQm^3TUYuAf!lS7&&@;1dPv({&v8$J^c8 zOQcY2QmR`g)BOufB_uJ!4msJ9zJZB3E{kbx6BCms)gwfAoGSK2U8wx>`w{f`2WDYz z4j&q>+PrSwU-Lk+E;;ZYbeqOBb!=Ht@H!3JinqtC3RHbPc*FZeSC?svE@~s)m^v&5 zD;X%Balv@nE}FEw3?eD>U~;Z?@qDPbK|D|2X(7qXV)nXftOD1*59Y>gx~SmnqHOf4 zl0-*2#_3oTW42MQ0PJM0d&bNshgWEIjr5x}>0 zip+Wz278Bq5GVgVbf*^m<`uR~C3^8EPz1tjx6X3{2VtG6psPzlcys#ASrrG9l&7#~ z;TV~Lfn!Z?CEMn0r}um75+S03#6+1N50e?qk69YN&EUUkJCl7RNhI9)p-r*u zpzVwc6{%yi{>WDA;b3;0oTsjP|GJ@xoN-ffPC+U{OT6c*jM>)p)Us<@YIzbS#Fdft z1sB3nD{9dmg|#=?XVEP@f61`Klx{q_@D(x zQf>}@GxgjJ5rT};=RY^#u^swQOfco#IVi#h!AKFyr$$>(Icz(pS>BxckM!Cd)gQ*c zH(R}Z;&vVK_s!T#A%jOx4A<BuTX za(deM>W+WFWnV)%;z^qF45lzP$#%BMS0FL0OM>c`Z{EUUETTLe@hb8#u*TYBVW&n4 zn!&@v3=3n*F4qq^usAqPUx;zyZi3$DlG%@G5+>!ic{H)hI1j!`SEAJQyzdSk27piA zLdd$W2v?u5E6exHF91NxbM~%x?J@HL|9FE|T2PDdD!x&~=AmwhWp=SvbUTvYCi5FE z%ceZYI7{!KB*A3=N4|Q4Jw$CTkzH|iLp~WZe@mAUl$`JvfF`GNUUrv5Tl}gp^)NOc zwTDm(@UGuV40A3etPBvMY|Hx??;v5ydjps6#LqWnemAFZf|*}<5O@xeZ5}e>AMa;d zRsHNYmvdbfNQ=#!Q*B!rP4RtyhJ}{@r*MWJX@}SAet>ZW$_JX;>;YtWRa@b&Mx6%+ z{P}-(dRy}DSjlx|JqQoquLw`){gpa;so=YMn}u}zHD5$7X8YaclnxJIHZhXzNLt^P z<>BU-iis(Gt?{vckr(!@()?Y!Vb5R7DhjLgU3tjVIM1NRDB=?bm0*V0ImYa^Y|G*Z#bM~74`HJU8)KPihU2D=t$*0%W>C(2g7^k2s zF{C_uvhX=rMVu~u*@I79+UCwi#`(VY%${W5OqT`+sinFP*#>K|1{l+zvg73U0~4O1 z7N2>r@P3;!PR_{MXd)^+^V2|+>QM<8A2&cv)rNEP9?)z(EdYLmISMQQe^O3aC~R#_ z;r)mu7wrcmtaTrsb2xSunB`mE($0Mguyy=jT7Vk-$3UF1=u*JLkRpGS7LU+LP|9D0MBJe}HTN18yg zL1%eNhuEukf7LZ68C%jre4MT(y!yp@)%g0cF|8f-r6+Fma~5-vM-(SkwRd0Ox?QEg z$g?dzuF&=823gb12HwEek}}-VVD4Zi)^112$3PFd(|=RF04uLwC-VMYaW!D|`F*j@ zf7bHEOHVdj>5churhI}F5@k|ztK?y-s4Tvx)H#pne+LkQYsx2)KMznClr}482S!_1 zO|&Se+kTCT4qSJ&p05_OY!pT>nv(tUg<@mlW4X=^dd|pWqE3$Q?u&1S*-v196p6ga zSE`?@0p0OH%%0-ay~<=s=YJv2Rog2~o5X&@f>C5%Y;_by_?ek$<3XfV_ThPFq=qj7 zAvOHjvZ@s{uFfcvsd<=9qnZ7w{a8!ciH_X)M_Rsb~rke^QcGiAR)=~$Or*+AR&sa>YHIc6Ij0fqjxi*`ODe%^B! z0doMuAPVI_XI6e~v5Imu7`9ahl2S5(=c?L2zV|6xh_;JkKW%YMdMIu5gU9l0M^fd6 zL#Dxbd{;1m@u+V{i+TjhadCZ%ygr;l{2Nj3icV~g_}Ckne$OqE0E*f2+hpqNFQv8} zPd1|2m3tGa>!R5s#v1F~(lT*cB!5*SnrdJVQE4E7|$l|)&y@5qDI=Ptec{U^$?a9yAQM4dtW$e*td}g6S(QXb))*fR>GJ?SD)68 zb*ajBl`pRv&LSJ#RWwQhqRQ^BXE}Up0qZH*np{=2#}0$_$@>60n9VgohvlIFv*sKI zhAa1%dGUAV8G(x3w0}gRlwwEa{8v`flPdTz`3%uEIFvtP^EFZ4mE&{s1vJjC?LayYpH4?l|~y26UP$fP1^aLMA}R%Un{F&~_H7UuW@#$J7K{Lv=!0vAAfdAysZI{fo9jCi#3!y zvJ@Y!8TZ-l@hrEnC~Kvq4wtauTY4o3#_Fv|?$Fh73E15Uq$$T*N$$mK>OiKfpumEP z+9Hr;d?Z{Qi|}K=7>rUrBSA|sq4Gm7JBbhGMLUA-Ch9+kJSnj* zS?00Fqpl>DRY1M-*tN{zxN66Sdt-)Rfg|V?N$T8&`Tm>GK0f+x;%*+Sw(EVr5ML15 z-rbH*P5k~Me?L*~h1+PmI@FCCd3zRQ-7IP!f6(ozWhk8EF^`8g@yU4JkKDyMlk6H5V-L zJCO)6T+UiDs*vw){wQ)`YP>#6;$&^sA8JhYm`!}4<-*YPn!1B=rK&j*i*Rkw)DHn7 zPZ0+>6~+#M(sCIc7$-{+h6&jwV7c*Ik2L}A1EFh&WgkU)o27F6oz1epO z=zeQZ`4I~u5CyuI1I4;$+j13PU}O4v*RjP=z>ye;SXDW1UZF2>ens|N3(EQ9iuX(#7C-tCdgp7wwBw}?iLiDt~zn+!fF>ms_f*i*4E`ZEz^j8{aYoRNf z+A9$j&U3)`8{pkwxs4lJeKDDFcUir#$GAoqOUdAd_Lwku@qTlpLyS3(%_>-|K?vJ z)_>|;=mn)^Y++g8V+v+6A~R(Sa_?m%vAORb=^KEF!dn z!3Bxh6bJadk(JM%^BZ$?NqHUfe2c7RS!H45MD)%rV}i|GSPyVw_)VkGe2y(&2(O@Q zw`N;=blJ0jioQKN>ceb4$(qb_Dy#(O5`(SX>uvPqt7K*Wgq)bNyo5iA0hL3HY$$Is zY2b}QTkzVasUpu=qhp$ZE1LgN)N+>6Q<4}m$pf~v@y@-bba}(vS!h-k#M&^Y&@%Hw z?n1V{72N(5x<8b%8fo!-Ic;k>SlgJ>S}K8qk5Glw2VNTJ0U`23NxgeEnmOL%E-&tD zTYo!^cBZ`ix*dKhb$Bf;GOxY70SpJK8@H*GeOKn&vwIKnHxT@@2B0MeT<05$GA!_~ zyUi0w)y;NFOeLm0m*H8VrPof|e@zB<;ptnBrYqX|lBHl0Nq+Iix;mUK(safNVj~^s z^JDAZa@xA`6iCh*jTNsj+4x19OGxzx>Bv!Ff2oNbYbCH}1HqCbz*ruopS`JBAE9(z z`Y*48Y)(sOA!>a0;L7Ug<-n zRCKbfj3XP9A!GZMM3z|bta)}T>M)G^Pyw`~r_@o$^`rE)#|9M-B$h`6CU)=s5FgAe zKkp+@E_W4#8!!r|pOf27|JXw$Y#~xpQ?tEm@sWT4+VS*|DrSntEuJlFZ%+}#M&4P` zv?^VeY*~HK6zwT$*r8p$pMS;H?)xE6CN}rWQ^?V39eV6s&l@!{MBZoNrh7}vc|@0) zg;{)7f|RrB`=(`QVf)yOG|Dk5L}a!Cl4jxCBVHwCNm*H0;}J!~OrMwk11>o%1&B>9 z)=Qt`-;H=78hYW-vJfnb$L0*{*?K_)%ha`Xb$(aApzk^n{CVs}9X1Yr>5HNij_Hri zsP%i$6rsRIyy3nmYi@X}s6MY51H#i|<18*HzsTHqY~^Oty)BL35;-_nBO&&9--(>a z{YF$@-HCAp48I$`n72sa5Fr)cDcRd2r|*$=%kK0;f&H~)-EinRHM#z>ro>&y3EYDD za=`VaMI2Es-hg`x-=9ZXUhIk7eEmCy4IVM+zpUY5*BhapTOKumq1vH|CqXUF*U>JI z=R#6upMOCF1|Cz4az~5n7#|K5JFrwR?3OvuRv1j?pm~r%hL$$>1VE;|bCC4(tg(-I zQF^k(P58@hVGNv1Pc%Aqw_-ygJmL4EqIE)TmYsWzq;kSFruqLml8#;RY{e??2dQ`L@ypV9mZ`hws) z!w&H_Tb$Do`OQ>^SG%)udpNrb!{y50Dn~J&1^C?sXxqnK75VV@@2T1c)M2E=bpE;V}2s412PT}>O>C>xADOY&RVi=2Nt7kOT2 z$4zmSH=d2k`?3aAy6hmLxE%SSdlTyURP$^`rZ*C_MX@2DkxTB=#k#ygPu}3d)D-0z zpYwk7y%Ec8w&|&VcklJL=8nCk^0XAK;KfC2eQuJPV~5=h07))><@ObSP!;y+?#W^Ip@7=?BfKFSqXG!?sCq?7boQh4$%sq-txOr^JnOzs3zFN z<)bk5UKe@FUq4Q3u7-;{UjLN0ZNShgYd@zw*G#lP9{2URr*;{w|5=AF z-#-(i>J6W%-MP%o<*5G|+#4UF@k7st{jV?iL$|Zae&B1PS1@CfTO2QxSFVmZ>8y+k zY^S;xHBF7ReieJI;_dT?J?Zs=O1`gL&N!!dcEmLU;b<|hlLri98U>d5v1iM;1KKxXEhlfvSLWCBw z(Fb^fU1ho-M!8A^n)>Hs=BpY_LgUYYze9T*al z^OSsz2m>C;;typ{@%<0!k**Hs3N(hf5p$zlrDLJ#$^@?=Z&p2?A_T-E-v1v}=HSB7 zbfiC7Sv`d41RwFq`{qd@TbJH~&X*q;8Ljmlzi8Fg*53Ng>Z>71-$9?Ia0A|8w`9hU z3*(ZLe?#>AN|r>eCqF0R*>6o&3AfGmkj9&xzNPcpDOp>;BR(LW2K;DRybzxe;;~=+ zjevDkUEQzV-e}Pzystm;^QROTvGovt>^Epq?uEgtUpfuBxM9vJP4;G%d)1!C`~1S= zCVCSNW@THAW$|~9LW0^zm6=wp`m3=Rp`nVD9Rr}CYx1Fm>y2Swz9Z2}09V*BG<~FS zhF%%sZg&^qa1)y=wSvYo zE#->Tg)_Zi%1%ONRr`V*wK3M~!UBT?%29M@C##HcOr|koYlK463)ylFQBhS@KvW?< zH^=6Xm@G(xunY|H0 zn+`#lS~Xt%h?1o9y=F2@UXDf=Wp1z|veZ`dshZd!_S$TERASF6tR#bk(SRPlS*JDe z>4lks)P=I{W^wI}>4CE~<>ZyKf9gF}8Tv7OADhM4bK269NA6Qg#k-6f@*=GA@@HP$ znRDH2A15Bx9;~|cE-)Ov`kq?@wcPteDcg=S=uIn6;htjbBrX!WOfm?%UGNYzM|UsM zzp@g$EvnW6JC4pgU$XlClu~ov-lXFPZ_o7DaZ!+eifUo@h;xukn9Ua@ycUV&z&MYL z97Xhh|EPF=u<0kU{wpKnmoTIGIAcx8w93-qbwa#*l{tdXipKT#iquwT4^`u)&R(ztWox?brFpeZ4Kvijaw<5bZQK(%g7#Rc)z`kw$UV zFGU_{+np)SX^%aAdGyO!#Oa8aDJ+FD>tXDeE8!cp5>;NYs+=4i4c`vvVloxHEomZ) zk@e=1M$rSlb;68q!w$hZr{s~}KDZJ9L{Q60?e^ic}(g)m{`>}=_BkmV8h`9<|& zPwuT1r<;|Fp^UDS-~?~*$GGoLjdsO1Psr}U{yAZ|I5Q?h%3`ANyHIKt@9mFbE0#H5 zh{gTS#K4!J1Q#~HUpK0|wd;@-JfewwKC#FP_CpCGG}J!YT~I^VICSE$u?qQpWW<@L zh*f%wY6M3SZs=C8Y!z=fL5f5snzYkrDYW9p9gw&S{geG+j~j}SabJ`+nvoB3O{E)% z&yBYrAg}n3397C>l@rPQ*UwIc^#wNp*{)W)DVK=?_1!&W(eg5Hx>*E;UuRlI?KBXQ zsDN$p$6_)DAi~V4elgzlwj|Ngg4QbzdlQXamhIU(l$cq~QLZLRw9GkZDy&so1^lPE z@+NF+qHf&StOCA|yoUpS*TAbkRq3M@DHXPJa`qkg^6Md`h;WfJ%!=?vlqV3G(6Fas1qpAp`-#jo&BI=x{-xSW zl#y`99yL9I!;-ck%h-aiX4qVAHn*_~s}FqEqf3}_Q>j>%ENca;{gI71a_`8irEoYv zt2~xF)2XBI;z{QMUis2Rd8zWVBWGVyMkd7fdG4)-L4x=hcOjKVYqqV`I|JhBJObUp zxe?v!m)Be8)#gxi5nc$GP{pmyan$c+efA`)c`I#c!SQaZyp(2^e;S^N^M4glInUz+ zbm7>J(k!hTwE+D6)X|k*U$<+j5H!Bl1OKosShu;w@vR70TPM=j*f0{7vlie%>B-?D zvpr{83j6eF*{0~+pkY0w;jfW4Gq?5ZY~yCn&)oTxdq8wQJ$lAddMwI=^_R)I2A`j@ zuefXPG4o$jvWwSkB_i1+vWPWzDR-^zonR| z!!;bsDK$V&eOAxoAQxLoq>FI2%u-{8inQa`5?Wj>{Hi$^B6D4&(pl^OlTB6qCz}#m zLEs@P^F;x=PufkN{>wG;6B-5m&%;(jSyJ`_^O^6PS2J#HEBmcVzF$R76*&`7FniVu zC$^A1_uBa<+%CLhl*44^+;YP7F5HwQ6{kfrkGBU)1{HXAoxbEm7AGxcPMXGk%z+Dy z9%}ky4C|8^J(2aD*%|$4>f0fr#mj+z+Vv9 zMg%h&LP^Q@fPIv!ly$EFf*CHe@n7t+t!Gq$`?lae+LY)Xu1_pyhSX&8N3+_IVj=QV z7K-z&=A?)v6$Mpi94$=J5rkTTo=zwo<<0d+a`MsDcAr!}KcS1=5qfd(hffGLhL;0W zRD>u7EiVu|28b(EU&!hMu{AN7pmSJ#JqBGA7&B#Qc!Zey&iTL@K^9!W<}49mtG?}< zdI2`0FJ>^LYR?TE5CuCX>5L`h+JMEV@fU(kN5dfL6vaKIMbzgAefbAc(y>a>wp1Z= zCixVWyyD_wUBKVvg`>shKuisf{-6nyut;PE8gO+jE>zywm@(qJiHT|HCu}bcQCIR% zipL0NAB8}bx>Yx2>=YyE5;OJWsLktwNe!WC#gQ~PdeDhbN=NM2U#S;C-}{3-mRo;% z)N8dVl@tp_g)a7;?hLQ9sEA)i20X4NQRwM^{!lLzzQ*f4fUBLSgI6k2I>Dh}%UM$-Z1Sx*D@)ZJlj zrUye{*QlE_Vfz@1(PjY?<3H^{3PR;fUl93KI#XlEp)Vr;#wsP_LH;k-DSYF%mkbXGorC} ze{6&J_qXsn__ClIIs_OwQ9N_%PXWrux{EyB*#)wHlJ9C&6zA}`-&=m}2P}JDdp?Vq z5PvgTir{Z#&XcL92JO?w&|I$%b!mzVx#{-j<|a%SBWaaBl^fM&vIhU26-SEb#+|4je+0wcZVIj<}#1)ZszVo2r2BBjrpBBdSoRvm8F4}hFr3mu2( z@iW_J8(%Tv2W@|(a5M(f#n|w|l??lM?@+`|kJOL7YxCk9je*eEpm=k1?QDaYNPU&o z7va@(Ps#={pV+u7wvF?cv0581$A)o;TGFJm=)3=MTk>(n(I$QE88hDP__g@~TDsPU zz$7Cp%z9186;e{T)ARDu-+BXpI3~3=j%H(#*uzYsBg$YCg!T>%lbVAK0P=U!u8S4s z;G+J1-Y_O}cc^PBe5af~>QpQTcr!ZI5tAHsEG{vN@#{pSt?zHq@^AZM&y=j*`#r3FCf#%`U7dk9!eQkB!6dAZ^RYibhr z?-{+ZcM$=?3f}7!iN=2uxzybKVn+qjFE}tz%!wo=rOz)8a|FG&!`R{46M0(LpDytX zdtjou?bh$wL*|B4t-RBJ^36I5O{)3axGK+q7YF}h>2oD4V5-Ic(=y?%g z6bvs5!Psrov!@pl3Tc0E$Hm1R?(jn}x_%@G$o(V^{={L}6REo1AbV2u&0Uj^QsM4H zEM(L?h>e<>Itb;>jf!v`Thp5N8;aP-F$<{0$}mN$ zt;XV3$e{7G6#ce{SfiU`99Ac@Pf{4;zzY+!*DBP9W5>#Ylxco1FvK@M3-nf!O zfBUU*KLr#Y*75&h<(SKecsv*yoC)iShwsxeEVS{2Ve zbC7y&bn{@^ds;rc*T6BV2ck;Exr1UaH)1)}?^kGJgBRi+Q)+`K01+GqBMZwXF*b@= zh$3wEcz?Qtda3E;3}{&zRtdYLoR8IW=m<_`9s7COAu4h|PtB6r#F4)klPX}s6I@h3 z%?=}#*}drMhP$@-GAN6aNOSpkdK_v!PdjR8%9XrguJQ;?T0$#b%&yJZv{>5I5FHDkpS}cG5|-X>6YO4^;hQu+;k~6km>7 zapgzVl{QXwY}OLy8?duD;Vjd}oL0XJOqi6R67-o6^GJ?r!I#U0QKzxTX8WnPj2+m8 zUuF2Eu5wT9A-aN00U%vxM!vETM@n&`ZGCK!vI5CN;X8Xw$G2sadt37I*U=84e_QF> z&D*UTxaj99E3MaQ(vI{)BBrf#nSo-Zv_7PY^eBwR;{Ar_~w)lO9YB5*@{uQmIU+rBOs2oAY z9E|j#2)fNlI)P3gQ)!&1(SEVFtL>EbAVzNjY$RLfMr!T1VEz}+uqtJ@&E07?nN=hs z^?P#OVN0BgSdK&C0&3x|2Z37V+SmBbVeLWCMpXpLB$qcSfrXZZG!m{``+Q{bmu$FP>~I|*cQ06!S~OvPo@m)#?J7Jv`pc9n7Ny{}!r5{3+4#xb{82_$FT{Vt|8#OT_V)@@ADg zJat~X(QZxdtFH*6r8gc5RnzIXEECs!Mm;+*?kNF=XTk%Q8I|h`yhS*V5ey8f5+d)M@WpFhLho?1n3-;T zI&@+G9I9IDZHQwV1)CPRQjAb>?XU6vUg3@meTMUqqR8V$pU5*bCA(EU{{{?| z-9jiU*Lx`+gDFp%gzk< zW_Vz5BJZVyV}#WTQ&i2)5o4Kn&tm-XQSFb+jBhc4`ynaK7qvHoWjBJHpS=yv0sdUM zEcn z#vYH_7er$BR#ek9>pfnHyk&meX4odTop0${lM9C33%syOO)i%A?nbYsJhvW{;bX%- zjpF6A66KC0pwn z`b+8A?TcsPguyLF24@~qX@Z}JyYN{b;S6{k!&iHIqH1+@b((vA4>84mkc6=R^EQy% zFRMP>02iOF=c9cgY9q&(LR+GJ)yRe!ET_mq1BklW=?wzcjF(Zq;$XygFxA@Zn%7P; z7GKXuFIF5`Va6rHeg)Y(=)XS5$9%be2vhzfhR-in(7Q;4qs9+6<9Sb!1b zum!MjQvKT2mBa%d>J7K4>pH9Y%o#UN7S;EzUS2G#Fn4PDZowpt$v4_dUw5~kR}kPRisEw7CsK_M2aaH5=kVEZf$-} z$+$h7Z^7*e#kL&y(}i$02#P1CwOy@EibaUt(zw@t?ndd1q;p1o?=4$Sx5hVQw~c>R zo_dmS7;sAEG^OLVM9hc(dxT(_)OA*AZ7EK*nM`fCB-OI>FsnYt233diofhIQ;^5Ye z-_CiJb9ZWuzWahX{GqeI-)hyru6rY&-4p{A6?MeRlFnr{4WXb!?oahT*7XJ}KG~f3 z2Q{8zz>i>3%U2S@*%>OmC+FL*6~B~ayTW|1WGEh3g|3KxSKJcDs6~fkm~8ksz@h&@ zbf?U^gnj*`4XDgW4+x5~FF#z(^D!Kv(`3(z8jQ+f(3slY{ng)dE>^&L8IIUrxAcwb z>yz?@NA9^yH9341XOGn=OG!x4>TJD&d7YQgrzO%oq8lR3_p{~M5BKHE$;)}29PD{s zw^(X}jmf=Qyvp?(GJie3vIk#bLCJt5!NI6Ll*Pe#1O#0EkHpLV4>yDC3_lmn`w&N} zEsjZ^pZ39NP8`31$i@=}h%Nqr( z;b^iL4Q4LXEr7hJb#y)s4SBfiT3en+JNO2%>k9-@KiuT~tq$1Sr1B z>T)tw`gzNxt!?(P=TtO(-Z8&?UW`R~c(P4K+#>nE^8LdWr z{18dxyB)O;4}A6bZ3_mboPq`is~rWDZfvwJ{-c;4ipF(Q(eK0`Xj87v#f$SIZi+xq zK7Iu-v;E$=zv9c?%AZ0pi?1u}+pTbNmwij)-+mqk4+&1VxRt>@xa49 z=V@#DiBYG8I@=OLj;ht6^H{>_pI@G;cJ#`Shfmxhbboqaf|H2+V7$Dep{LU z`0C%iY1-yIJ0wjTAI!C%DN}gj;hgfmv(W30FeeQ&36rFn9#%iKY;+|7KJC3?V)(i3 zak7_Vq3;Z@?_p zgd)05b3@!|;diWsD}wGn;%9Pf;$nn{n&%TB$$;jT3u_Y5?Ek2a|NVx=YkZ2$9y9|) z*&H+^t&%1!-vqou)(z^5&7@;OroYeMb;Au@&8Gr~4>bn%U!hbT&=T754r)F9tabv~ zR@c=0wH>M{BqcPF*)@SZm6R&p&-Fg@(p1Shj{d@xFHI)1#Z8R`ILuqp+u8p+T4#V4il}XXJ?%TX;a1vTnGtR4F^=7-oO!;Rpb?nj|;f^D=Ow-|8r3D z^SwiSN($sWNuH6-rtjVj=5@G0pC;r*(l&(vnB`)a#*KZ~`_7KZ$*jk{mXzX>@bf-& zw!dmcN-PG~jDE2K@qi9*R)Cn^SepZQ>EDCx_ZMUt=Zn#`f=}W($|)@W+{$Ll4cd}r zD0~w6Eue)*f8V}%m+pynD(46UiW`ZAoQlKAAc|gDQcK@lN&JPjVvnWseUWcowm)h% zy6VUmiQ@X-3fq$=1U;z|^2I(-aC6^ghO&N&`Ad{( zR_rgAApZI&zNx5uB;~6pDlLsDFMm4*J|nx>9Ub!od)?g$NNA{{{_I@ozE~6a{3O_z zq^_wmFi0;x7AVT54(yyJUJ`(THkQxNf-bWz35FXrOzO@Lcn;49-sZH~dhN*gHmz+u z!WKykJabN7F`b@>zhr@S0SO= zD~WsKbmA6di!p+6$R9t61PuFoiKom0)F7pV{{5$xwh-06wpg)|M{e+Nb=6}MeXGc* zivvqRZ{udz7W;NQ_XAF)_5heNd*%20`2!x)N6?18-^~t&!(5u-)BR+gBA=wZ&gHa$ z?0)zREmhFxGbvN;f$OEV66r+JQM!i6^Kj_xbPm8%ph?V+-!BDfyc#ijRQgVB-s@9Q zws<;=2cZL~B_O$EDJxtzS=5!;6N|RX)4&`Bo@o&(oP@%iq@`CD8Gvn zdlD2eE75Dn93#n0$-TN=gP-$9-2Q~hu&mWbrvLa%9z)c{xD_(a*%sqAwg#DE-V_(f z5X~u^+>-s@ArNtYdmN`Rz*Il%MX0YWTe9og<-8yNUEK@+T=B&JNlG-#$){q>ulZ%}-D|%DW>R`ZXhw=`2c!xL3w5w# zsV2?L0gG1|m;^}9H*yZrMg?vBGzC>Voj?DAnb*v&qshH`=rSdRts_>X`+q);SKC2z zhF#)bd{I)=xwOex6fpNcf2m( zgWFu)Edd4Ku^YQ5sq^3zC zANkYv?|}$2PM_-x*4DN5g}Eob{zBhV-GoSh&=*a5o0V65mF(sdZ7;hGO$f&V&8Z&n zhcYBvRyVf>>;DS1)773!>na3t_Y|ZU%I!f7Zq49d5mRUDnO2Q{$aK38zmWS;?|(SQ zz+m=teOj0?C@o z9+EX`jj2IuOeUuUcd`SonX?V1aY{z<>}mD*j(Z!(!|a!Ouant1SXf!7PVuw0UP%6H z?uHUev@!Og#NW)h>9lwgSLl)VSAYIS?03ZQPbHTa7YN ziqn`}_&bVQ6Z!~V9$bs@`;`&XkxuF7hi3HL15t0$OS=Z9xU59z-9a^qxX-2|iSX9k zFlo`n@&_r6rnVtb8`bWiAGtz)ga$^z{!}Wm+U-8`J-2q)-}Nkew(mgOz|eytzv$DP zlQGVr6a1;$6=mSiH+h>3p($@JN-%B@R3HmCkJeUKG-Z$-x}Ef*upOP`LsCqoJ6s#; zu&JjbzGZ179_La?x=*e*Bfa~$!*=rcK(BtP_7Eb)?>BUQ_6gw{`j!k=xG<>--pTF{ z4LUuN^j>=K8Hq>^>k>ZCR8W>p|hw?j4%|R_) zPdPKEEEP8WNegUyd}p<`y-t~q?JZt5y-%W^Q%`-38BC$4gQ*fr5q4$Tjk(rU=3Kf7 z$^N3Xl$6TZAIMwX=uB7;-=*5b`k))bzbNuMh|@i7j{tSYifWUKVAb=Jq5so*rbN=( zE|ebETO|DdYzo83opc(g&v}Zm@zUGx;58C^8306nCZy?QA z5M?HF0FLRKua$=11qmdSN(W$Cc2~@6i=I|<>!`LXKhFfrmHcyhtqhG`1cLlFTb9=0 zw9#886+x8M*RgXAN`DnMwJR!&q6M1!yZ*ZVQ+51w7G-oZN4e|`A&KOasc6!j)z$xW zC>_38J7}l-Z*Sz>*?xZ}ax;@mOustdyYXj~`zzCj81hH+CvS`GU9Q&Jcn7zAiCAcs zPO~fHjIaln=lCa^ik(yWZqb?E8ZXtEvYyWsBMUyZwSe;j#-{lV=g z3IZ6^cIzy=Lp(f>;^;GY8XJ=Jl*=rZODv~Ke8Bnl(4Stn21R|>D+Tg|e75uB`}$OI zEK0&p>U0VMIVzACgi%bhETr1!#(vf3#eh!9H{80aLt0VMPGo*9@i}zTpW98_i9Bm* zcD%rjweOD2O~uo}2@Aj{!_nUhzV3H3pwoAxnA7*;U2?ZIJ>O;oogGEOnI=o@DjE^qcF`a6*yGYEulcxf>A(N~96yBq^l8tlP$_*V zThyG$lq9nUl~8Ft9nc{yd*E*9@5MDHa;2a5u(EXH`3<6@tvx_&nFIZO0WHv~T4m91 z4giXreY)6XwK{j=OM$gw2wO0CEc?GPXmz#NDNPc28c`eZ_T$^x*}<$-{>Ehx~;dObcF3{3dFH16|L%SMaMF|*RH3lftzH-6)cu}*A=#`jCt1*G<{#a>S3!1Y!xmXyymuR&B>Uw z8knzjNyj@)3wO+>3g_Z3j~CNzn|>iw>~*$^jJ&LkVv6MAk^<=e8YZH?`Q~=pU!JZ7 zXrKKdvI6l8OS7f=Eb9w+g6;gdp7@9ZNT?gmg%E34-L(OE29a5=(b4 zUCXldU%yYh@9+P7-{-zAcJ7^vojc~7&-u*EnR9HV(TQ%&v{;2CYagS}`@EiKV-)?_ zP7-~Kf>{fPtvl1=a+{ZKWxC*mbEjRtuUX!|T4gz%v)CU=h*VjOP!47wy98l!{+M1P zQPAn#Ht$|3-^ww@0`l*<>WtT}wr`!XWevPIGN2V}HQbxlIbE_|2fO1nPkUxV<|3pL z?H2pDeiK8AGHO`4FT6iPWU^n75B@NSm8M%NCPA!f@Eqd$Wo!oHb`;|V(-=S)I{k*Lsmy0FTR6VG?dyYW1x!8xy!AqB^nod$@s`le@1%c<&l#MWXc=RMSKwO7E_L`j1PNOEzRXOws; z%#D%L2fo!i>fgt$5@d@**ZebvK*V1WvYsH;}(Kst*tp?)>)$0 zLru{`3k&+*aOq6aEb&UGbqh_9u97|1aSOOFMdppNGHFmKof6o=V5Y(3DdULVOD`Sf zg>>;`2=?+|p5J+rKe+3@1>}TP!hJFapvr1eHMu@KHkNOM^>;nMEezUd5$H!zzRJ)x~O6%07Mnnt}K#TYZ1#kF%6Gdz!$Q*H?RMPp)dbg#% zie{~&pDv0y?74*1E!igFyz2P&8q9W=Au?~zcV)p9iyY6Ne{U*@IE`?2Kb-4nK58B6 z#3$0>12Rd}r`!0|F zibON=mg=(cq}OIqE~}#dO{>gQ5GJn%|C^>|E#!`$sLzML#rry_JTGkGd7Z zxDaxI7c|XU(JV|k9A)5P;C?W-Sm1^hfdcEX!M5h68tIZu}s;*T@@ubJHU*-da`TZMTw#4B~6y^XCcE(pL6E}iPKasS;b zv#H6+V~h{upTBOr;Z?_mj=D2=l^>Fn6(T9Lj<$Fqf)y<-wbkYWFcED7TZ}HDGjzB% zboiEu`h?8=SY|sOeo8{iZeOj`Sx;CPdS1%U)nzCZ@nr2T6hHOCM|{%KP&d?kr8CQb z+v3-bbH*m!8T;^`VDMMXfWD|_S9f3|&d2Qumm&KUzp$o}NC#Pc({yCEcgKv}4wQCm z&DgBNhywHpMrexmyS{01+*wxqD43h{BkbzLgl@ezsItS+u96HB#!7yxx1-LXOdLcT zIb3*o#+s%(FhfPQ!g@)5hZecID7PX;O{G`<<6pi243{pWy$!}Kxeni7S3^RbI5Xs~!>wKAvKEB34uiYfg_R)vO$xVGv1B~{XlXO0e zLIUa)et6*7mn%3J@*eD^+)!2`h5|GJdUFziU^66OKlS%02Y*b@GfSv9Df08Z0~rjN zaxH=5gO25w>|!6iM5~UvNPb52R(8R>X@7?X~sn{VDBsuII^(JsT#>*CKPUJ;zimvHrDHkWf-ah--+rb)jL=7 zx&aImXL@?NgJ!$&+IcE2Yy{sfvVY{tSeT`DJOia zquXJ=fLqwV$sX@f%zy2ZGfJ`>IGCg%3HEIz>DV&7J$1WDm)0)fPVzO{gIH9;o@+Xu z?vBHbccow9@94CqWmgw#tFp@sUy?uUWVPZr?w6Ax%psAALq*#xyS1H&(p@^EX%XBU2%cAj1 z(aIp#KJNc=eP+T?&l@vj(WXkyB_iSBU#%0sx*0!JY0I9&@B>H=4fo)O<>UuT&$orA zS*_zoW;|-%lO37=3<>Nkj^gKdl#J&`qi`~p*bS;fQ>ok&P3@vDxn`-{5?K`qe)SSj^To=JC8bmOZMY6YhM^JmR|nX?X9 zV(|30xb%{4AKUz%HiYfHflWlc*zRm$GFoY(kDAIhYvX|R8%Kpm_QkC^){&UCj8FL5 z|GtO+JlQaQNNVB6bf5hKoc1zovKO!TB>7~1n)Oz9vhk&$(9KNU5|OM)=f+|*?P10y z^&8jGwM=QT%msnhV{3ekI)wvH(2oWWYD&xM%4RkC%7k#aDL;<*(AxZTnmCY1^(HkG zF68LjT%)Flk$?@cfKs|EWdeLO^lwm7>C$X zLP*^0YWz?#)R;lE2w0UegA582xn6=y4Fnxnmn|B8GO*cZ+DW>Iyd*vQT z37nERk$3*zaG}40mDsRBFp-rwo#x)9SZ_~VRY`3xZGd*toG}FNKJS6rj^j`jzP>PD zN=s!&svi+Xm}P_78%%l@#E-x5qWVh_rPgUPd{DcYGrdi=kZ}2(k6C+_gW3#q-l0m{ z4y7+B`L0E{D(Aj%ReR;X!RT*J=stD6EUUI-Cf*}dC>K)5Q}6S9WhCRc2N3C1(0e7i z)Gqvk*@5DAuT>W8_`vL5gTE&O{{5nH2krrCSwl)+H%EpPx}>4yt>m*JvO)IZ55=Rj z!_#x^!WmoDOUkD6Ogm>Z|697k{5{Vrft=Gw;m)8*C#M3Y125Z7Zic z*19Wv<_%ygx-uX3-0H~5iiJy_brx3fkM3lRz*6cqr^oRL1yLE#d54a(KH|6dd+CiH zCIl&vpbJCn?D0~HX=WTMPmXy#U)h_r47QVe1=3THoU@TH39}R>%FAu2Zr2_Tomd(T zZ?eIe&%IRM{HKWjqh^DAOOWnn9rc3tPr=5)GI)~y$uza2X;M&hopX@3r9d@`B6 zdK5r^=XRC4Snt}Ls`D_^^VJ%GN3D$5?8AC%6=YY$fUQ+l`h=$3hH+KOc177?k;@sc ze~1(pHGrf z-p_ubRPvEjfPDcIbnLaV&U7>dU@&5*@A;akkM^}`kJj<)DU$pQY~$hd&B>zcgl`-` z6OEViM(Zew>j|bYB9{3kDLY-^9I&BZA_Q$qn(~&PYM+4>$t+m`KZIwYP^;1)} z6vWG{<)J{*Tejxqch3cGueY!=jFLLPGccglQw8dvbL-2&zmRVWmNifpt9p-h?0$0S zj0EDt*oz0gYZNV=!#pG@Y?d~Su;~e}=HVQN(qZ|rqxNby8ob}qYE(UpLznE1xqM6> zOYJA@%aQk-c1@nd-e>yD9{#p-`%za*<0$ACJJbD9Y^=IavhJ&_=!4#>k2bdX7yg_N z_auW8-jG`0(z-CPf4uq|)3$L&8KV7c$uqzR#A0vbwv;P(1tp8SW>U}4@0`94n4HXg z&Vk0WJC>$i;*VtGm5frx$I|mFn-RC_hI;KP+9OVhB(99jlv;(YyTHN*bRtzf3bYN% zTe=DC{B)vh{saF<(lsb)urFe`&O5%7X}YBj_?aHc!w#3c)SY|n)yG&I+tr-%!L zg>n523W>FM7Spzf0xFg5om+Ly>?G;-HGb5EPgfOA698C9GUFwb?&cLHl1f*XYa!r} zXDHgqyeHihRCK*x$LuUuljjnB%=+y20Pmq?#Xa89RaM^rPbRY(s8C-nZ}wwuk&6fB z6KZ#mKPNZ9j^fxdAo{71(vaI&TH0Kb*R;AnxFcn$-@lay13@VJPawBZFHmO zOsOzdPm{KI^+#Pca#d>rRkWs^4!`lx&4Q_GezNT5Z_ed7K6v|;q|o@`ddz^?+;GIp zZE~p?$w0~VYQNnF_1#Naf}5>!1(hUUXG5$I%I=zlZ8ChHsp|9iOpBM)JF{O_ik2z? z2*?g)k^406zL$52k{zC*^&YlT{by&y$*RAz4E!t5kKT-FMSx+sH)PQo!(J8MSV|z!93X)zJ$WQp ztdSzqr&`8QAls}@>~kp{`C%?1jE*b)YT?o2GrU5S*R5FrhwTP{3NvQ=QpbQA9xc&$ z5J9mM$9NBQyRKpC2bb5*8y>{O+sT`&tKj2(wAMJ7ofA_tXG>!~Hdu^0LCS0ms0=OA9$ty#5*L{(K1qV8XmMedLbI!Y>~oAo4fW)x;Y6XZT9l z5hhcDhv7Xk3`^9{{v$Gbs|bvVD26@A`BDJ?8;-pCGb>-$Csglp0cBqA<~V zck^?((rurh5%p#QhwaZD5Z2l}512Q81QvE~^=K>ZY@QDjZvSbju-G%x0kLMi6ool@>7En7(6G9p9g2H@~KTj2(K5*i550hQBZb+KHb{A9Rj5$b-j?RuuCke*chVQZ8#$ zpUGC1*J+?#-r5~ttS+w2Y}&u16FT%A75A20#;QMpK^#Q@hcQyC&9rGUn_?IZaJ-P7 zyV^nRcenzT%WQGi)gUi$xa6+LF=|WDJjk!`QIY?Vp#!!0@HCupeLO|_vw;_7k3sCp zPCch~A)Cz~$&Cw=qgSNlD%?_Bx0=ARi+^1*v)`ZaA2wlg-aED{k@5a2mZh@2L7{9Z zcW7s!)!P(u{h|^`$=Vc%AL;G|k+%8m6V7hCHEc2hCj8~HVMSm*vJoWbPgOKg6(zpF z)Z|23lOo@-+kWN4u$E$3Uu25-gt^}Mp!uoZ^jD*n%WNv|St*ip)_DMsrWL*v`JZI3 zpNTiSQi=2`U3=3Aw*1%_hOY)Y>y3b`xGDjqHZKj>D4kxz?V=Q@#4$$#-(7+kW4X6t zpzf^8Lf3KC~<^c}%3@V!7QEq`tLedqvfLxOE|e3e+ONM%6TD zw~t_bzbbAits^Y6w;Hv!t9~@4*~`n3QX)|c=Ik^cM9UKSPc4wHhfOF6l%;_IY6&&+ z)_HX&#@c6^+beDv&7>-SwW?6&ea_)P=Si88iSn_4Xs=0O=O0+0H~WU~x%;1JNH+r> z$k2*JoZ#|(d@TYCqiUFaADX?X>n+ae@&ls+vHKrtef?~Dk$mi{3O1EYpkmP|; z@61cj8H;l_iyXQNnZjcr&Kb}+YIV*8KT3vKWc}hD_}(;@%}~2>H4JclKiy)wOy@(k zWaH8$>sO%JcUsnyR>ii?SVmw*-R6C9Vu@G)=9J&i@50I7d6tiqNC@;tt4wpUn?EqI zWqZ7^|G>>CgVJLq=!85j)#;ejN_ikOOD9%I7A=Iz8MJQKrJdPm(E3IEc9G{ z>*TYCT?{?O@s+OR^qw;v{rQ#S-DSl|zv1)8wBaG%e1{ut;c((Y61GgqL^}`88p8|~ zA^fN`M{)X0n_s^$E*zRiH;OxVrO0sn`*?`t6IsMj|YS{tm^h0N&9 zob36u(|4?IJ+sQt_Y$6Nb&KiZRkoIAIfqbSF3i6Y!!y-}n_(q0A9q=otvhIF!uD7- z$4gPRj^zn=?D~!rcg;ztX(a_dJHA;{OxgQg+|stm%pzu#mn{6QU8 z=8NdM6r--yb>+gb92s-#haWO1#4b|p7L+E^B*FJyqs6LK7(#63Vw=Nrh~Hz-sT0K# z1fiWV^!*~L`G0Fv?%cyjnc&7EGOBx8C(jH!pmQ(3i};s!G}VT4IdTDP%#!SaUQN03 ze==L`{rL4bkHDtrmL7>lMQ(?n{dt!reMZTIOW z{A`M%>aL$&F?MqLGQ+5m-u^_Xj8xKgnu|H^&dc7_+X1<8yY%=KN00!yiFoSevnSoZ4 z>uS9AMc~INk6}N<>xKm@pZujg*;@qKuvP-Fx$o5y+hq2Oz&2UJIC#IsT$UGU(9=gP zLgwQ0`nlc=pqBbL#R|y)7ZrytPTozvogL-i?-`!hpt>qD*1`Q&xy3b(mZrVu6-O?t zmJA4yWPej@;Gj;_u#=9A{fjf(FOEEojW-(4#W9kkDjqK#66fBL-pAAad-kQcw@e|v zqH%tqjbgFk0@E%#;H?@%#Yqm^r(qd%S0o_@c+L5WAH!g8A6mHbVWTT(4PSz$O#snh zT;S^sG*gkP${DqXZh0?+CI9IDQ352 z7^y6V!)i^>PlE1%<@9hCRbCzE%XW8OkvsL$b+?vL`o>eiFQ6qi61-E7GfWO>vvxdR z>?CnQ)NS8N89UH?B9pw_{9aS3IaZHHG-(3V5*fN>*S_oj0E$_C<-ln0>-6leIrlgV z=h;h)Pgw-bX-L#(V+Y1j2H?XyDHl(#H`e6}AM92W2cKWE@w4ZaB zZPN5Fo2%q`7*Vm^MJ7V-c28{gd(G}lrwoCTlgzaTi3xmoEf3f-(mN=ZRAE(H5f?*( z_Wk+K?G8p8*L_;+AszFDvi*uC|O5k9;lhI^u)OHOrjAAAFo{LD3y)in>bp+{(Ys845PJU$QMd zrpTFJ#roG?5Ru8a`%lTnj^PsCynn+$LmB#hYtQwwYMm-22u2I5k%$U+8$!e>gByI0 z^VI9s<6j|Mc}a`Pf|MZAo~uTLBARGu^!C?)nfeWz_E#S>!mu<6Vc1^pgOqi}{vUnq z{$R{CD8O5OLcuy6NP#_ShtE856t5oXPf2BA6b8 z3tqo}{TCRMRyN5Gr?*C1{bZwB_Pn_`(>{r9QIxM#aurH2M1}1g->A6W+N~9y8qT`l zX*PpAA3Sfp{bf-&+R`%7crJGPG6xur$y;neEO6RIScaB*0taDsE?wu%YwkQpDPSo7 zh2dY<`F}r1%}s(Lsh+yEI9k(mtN<#b88P-hL3deo$`uf$t=+jskJVlpPH*c(U$zgD z(zc10ePJA#Nz-1qT7{BriSLdoO7hyZNV7IZ*O5|F5$f@7!7gT&SB?03)*BEx5DUAD z7fV1(9!01_QJL@u|Ij5m0S7Kw@en7l(t3ww$~tAv>_+`KTH57)T;afm7tcLwPW?t& zqm@y;=Ci(K-=w_l#SZi~0vDf@P*KLO zzMP%Yx1LV^d!_CvN+47y7(ml8@D(w$=aD8>#BwtKop@Q%^O6r4o}%q?skJ)+{#T`J-@HEF%qQY2+{A02 za-%eR^1x}JC2;u^uCW~gf6JYx6ZFur1ij&8UhTfDi8!M$ll3mPN?+{17uFvZVb_J zZ$bN1NZK;@WeLZu`pqS5ADXPk!@YQq-e=>;IL;qj_{fZQU)chM(nBpQjgVNzZgj$8 zl;!}nCBfxCG)}4(-Nu~90HMxDN<}YLh7)$q+Kp1ot^H%u}ph-yj!Ef4}Sh5pgGAJ>mdd$Z%8`QcN51`X$^aIVq(j#bIgRO z%6N11H%kN?}w6I-upwvQewgQa4)HQu#9z%f+*vM>L<1Fx7GcRF{0zs{49gG87ccRmfhn8Q5M? zmkHmouqZD%oo1~cU3vuIemzbT++j0R4BW9=PocDp29i)YmUpa~28fHi zpVSqepQDs0B=~x|`>RGoN}`U5S0A^v!oJL)Ek4?3@3I`%S2w5s;nAjwjX|F-Jo>&2 z&fadM^{(1)BWkN`_ZQld%Ac7}79t|O5*E`d7Vpi}c+*Sd z-!Qo+agpm2s<|Ql@wvN$=}0U%miuh~U;SAC?q9i}D>b z!3z{&bRU!+&x=%;%PMFLzMa|qTQL_`!wU0dwxxCGW;EfOb{Ij$8>V|@JN@n6W_P5BRA`{ufR>CFRT^BAl~_jJ$klRR$Me*;dK>N=yX)db7VPbY*32t($q;p-kSHOr7`MhbP+mj4I3z zeT{8y^vMm)Ry#B4Y1TXbArw7rk{)TM;vRK&xV13yV>kAFAcqLBm@IEccgf%OLi#K4 z=J!W>I<22=6Xxdj)TYbXN$iTv#tM^stF0N?{xRW-b$j8(8@JkSr`MWlUrKBH_fsZ2 z_wcGp+S*(@e!UzPBqw$+Pxurq+~~)ZYr}n_)=@>%d6Fd&lHjv>&~+}QQOCpUr#pIN zakP=ZEu{T~cgS&frPGfA*^n(pyz{LmP)P{2GDW`tzf^Xh))?04inPjV2E1Cq{rrKj zVb5BvygJv(1&OB7WhW%y#h|~7Z6&KvL)On<`=PbvGM?A15je@&a1~E6Qf>;u{D5gg ztT`nvg+M<|d!}*TorTHF_w^V0ICi1m|Bto|Phvl8PDI|-{7+rv@O|qyt z6a9jAFtk8WNE@bcbcXf!2NqWi2zNdFf-3&K&tWPY<`sSgzq=PIE!>9IG+}&4{$knZrH1Az?OwvmpAM&(` zH9gWI=KRjiR%14BSAuwt++;I`1`woFz6T4fYMlW=x>@83tD z8fgp9LiLKyLTBs~4ub^$=f(g3&NjZqvsT%xVRZwU3PL8{`Df`+1=+TGmM|Lh%n2G9 z2EC$xYS`Wou5X)$vVP2l^^?+)u1jl#l{zk7uQN_bNAgQKXGk9#;@-2A1Uf4<@9*u-FCmd#vm{i*GX<>Ni@*pX=m7mJ<3U$1DrJ(q8Rcp zo^jSk-WWjgAjzM}aRP*b)pYQIz>8zVW+dT~fb~9lSej)0-%PUnyNd2%=YUA-hBdP> zj4&|BL|vU%l!lnNsQmf-%h6grCs8y#ztG2_TJy~XiPB&)sMfQP6Hvk7^JF2+iS0aM z_x!+`Mu^f=DL94J##}w2ub70pY+h$5n%92S1CZ>veo~G&{q{P-`8CO5on9%|UQq-^ zUwq5b5`tgh{?beYZDbwmZgt+eLit@TX66wA>)!=qKKK4Hhhnss=`w0Pej*H5T3}v3 z-}e&0c?pM7K88WY^ZZe{LO059T9J@mtP}nzU)nnUWR&?+-q6MSMMJmONA{=uGQFZI zGi%oP%yjAi^&-YD<*pQip-6QQFtuKP15F0+6c5T5P3$(xt5MJMwo zgEjvB(2kW}UMYX9@ekwmuND)D`y`>n<)A~o+lJ(QkYWz^F+ycaXf zEgZe5&|7;o6QbT#Y(`jmQWz3C5gcw`WPu-NYTHv@xzSH&0O0p_d=wQAIJ! zobf5N5`JZ)J||do(56#gmkwyH{3_F?)5*l&nIdJds>zIykLbo7|hy=V2))C1G z`>x)#`Cb)0wpg>fnj)GH|K-}T0Zg7qs%i6iTIA~ZQ}5&!T=H1Bc>*oYUMj$*??(a6 zl1a~RcC|zf`hNiK`yXP**!IUkv6pdqxzO-TY>$hW+py}jyS-9DeWF|B@@7&WW;9;_ zs+u;rl-DN)J{zgBccP)be*+vm3q(KSEsrT&SXGrYz6CY(;V&XRl0{}duLl_obc(5a zoyHZVHFJ;LCCSA4A5{NbTz#>71lmP`!|;4CE& zY_3HMWQCcH)+Az?CE*ko7ZG3-sBkta%%3ugd!@jc%*fAq6V@iM9dXBfMVP>Qt* z>MNwRK@@!^T6^{97k+NJqYy(ZeJ1Jgy39Kemh={`G1$d&$7XvruoZ)3OrDC%v&t#Q?YrI<)(x~-*!1fCupZK8?f zB&RVP5?c9bw44IaUV@I~9B_PGXk@az*eTU!xp`NOI9P1l0$UoMDDBAD-l z1u`plxAvS|{cK=l3wv@0bNgXWINn2Y$2{i1hp)&Jxm7i1^Cgr<(a5I?0_iaY3hD7M zv^W0XfEb$?T!gLFdnc(mpwFF%iidbh{lV)yOu^)@<>ESm2&w!J&^2##JOK%DajSJ9 z%4nFh*}?wmO75Dt<5&x0s^F7H37fYGW78BW65f5!?g|kB6)fW^ z9$x@Mib@NW`YLUq1-S>jmz^TBCkKmyg7YBhxl@;_os;gq9jjgrOuBS>2Yl3A#e~t4 zxV0DC1&Xch{`5PBX!`Usn4#qg?1N|ZNPG!#pNP#sIYE@nx-q<8E08ORVK9PUl3X94VQ%s+}6L@|kiZeq_uRX^+OH|h@xizwL*&1H4?$dpA5 zo{8Vl!URZ>n){F3Mj}nkDRxdmFHmrDZM4>JpEtD-f_5zb9RQ}I82cWX%>)Xnj(v4? zN@g~)(sz7&ZpIL~5`PbeQwNJ+k0*f`I-sC4W6<#? zjeA}3Z`&v>f!xLV^<#}0ukx47N}pMg>F}J=eA(I_ zT}LzWz-0tv#)cxwu*R>XVa~5RQe-rxa^M6 zopllQ}4^5>JuyR!U`x)4~ngYnJ?(S};z~t}ht7A4Xf4bU~!CWA@mhf|S;(hhz{IejLw zCOQ(KVbqiB ziUTt5I+KB@Mw~mpNt4!y#ikwGE$d>#Me$ffbzzSl7E2_i+d;goF0>6Z7%9boVg3hupd112*d)6kg$Jl?~d zc;YTIV?(eS`|=d31~NZA&#h!!+n{9 z5sGN4IA7l}2k2$^$~NzX(dXxd7R|ix(l>~>!E;?Vc75Q<-q#9Xx=I7%`edbWDBMPf2l{|G6Hg4{nYy8kipXFR@Hjh;mwYaHyISV9dx0&Hfd=>Ki*z<#B zsHd8mTKL=SP?8JhW=VAYSl^?!M+huBJ{LHPpo zc(RiZn{2FXMxH_{EcM4ew6!5VRQLi_?qW}lR-OXC6e=;YU;~NrUjU1YTS+^UAdN^x zRNbl599>4wHw%#(_P)BLGj%JUc}l*L4pnKSe@ z5s`_#YPjgmC8d$uakCxfnzaP$%WKb*-OC_j)A(`^^4lMi0DU!JMqYuEHNYl)!VcNy zUh&_VM;x8x<`rXa(Fa+rNfDR~$wXb`$n-HrFZBJf1I?H-OXBYuSG_OuM}H#rQ-xAz zl45^h7VhqceSx{1(y&_-zwhVza#qa@gS7WO@qS1jw6b-S7q};bjgh(bjCu9#EcV;= z7=%Aed33qzjs+%86PsjD{2lK0t9CbN3IAAh`7bAe9WB zBfbHabD3K1%(fka!5)=$bl+yezN^3)3~mq}(Bg)&vhr3S5ziA=)?PC&Tx1~`^f^UZ zS{lQUV&+Y4j|`^insBYI*%@2FwVQBulSSOry?Ldqc`>NQ&dmN$L>f1^y+ky7y_q!VNnnSikzP= zw{AEV^OR!5r@ovG&6o@`Sul6g;V*pbajASViz0Gl9?NalMU{0fjm(Vdq#eK;Xv*F6 z&v-e(1eO}9@vFiDmA1wI1a_Pfh-O)Rg282$8uFem%b;%?(eq#i?S~(yI4ej|)Mpu; z_3TN4eI7nOli5zu4?FVWpqk>@7GgPjynr5M^L??d-1JPyY{l&8wCfr;n^ToC0`cn< zND*c#OjRnaZAiqTmTzfdY9jGMU%Xpx%3g+`zd4x^Ot4n@s&LXxIvG)I-Yl~-s!Q)8 z*twvc$PJ!FW!5IXiegBPNJdB<0jv7fOY({@lA`t*V(lkfF>t5Hm@}#Y89JO+B!7GN zouD_bm9Em$!SeI|`WL0V-McIrPTaiQSPidupcnpM8sNs0VxG}ZaqtZ5{D;a&#*awNu_ai<(XGbeW-_FATAIb=R{$$FSPpPGfhjL5Vq7 zhKAfX54Vh}m9xYjS!3|S!o%~-`eOVKhV0m(T=k>9hDhSJidny`k&eR!+7KezKp`Kq zVzo<))!zk-yt!HvYe%sHw)#tr&++Ejs&;a?4AHB6w3pkBTMKT&i{47z$WK`D1z-1Q zHO6H|?B|Vf;9SLn?c38|ng;kKJzps~NS2CEm0USoyQTQIP|akmiFo)ap2kV@ltd0hI~q~Kf5>FuYy)m0~BS^E(O-D$0F zPKOtiS@dUuuoe9$Gs6ql%3C}+gI{zhUkI0N#2TrXR!l?*FM>AWh;&`-222fS^^>uC zQ6HQ*I9RNW=@wMp6z5bHs{^k_^mXxK{KPX5p^G4x^`|2*(t{D9edk zVHPIr4LxDIP1S6;+sgsScYI!8rGxIs9G86l8+vOagLM_~GF_DQe40By%``o*a_gIm z*DeB^Rj~tAJ0(k6J0+7(mLJ=!c1U=R2z_^aO19yI@)Q?7A4p|=pY#snjOTzIt>gE*@(h)Cd&1WRE^roftbMIGhw z0G@#Mk(1HWYkfa@Ez9lGj-aE;jsu>f7R-AI`B(ArExylrYF2VmaCBKC;S3T+zR8$( zVFV5^cx==9`jq$KFp5(JO*K(T7&IovgdjwqKz0|)(@K3a^3m+0%MZKL%bg9e^BLNq zF&{G^XcUOHEWP#iAMTC9CEZ*UsI>DE8a(CI!R4ZiYz5)u*#AJ0(6Y3mhWnGt!m5p+ z##h^hHYaw_MaPn-4FJ<)pXSG^x4B-A4ukf6eE4*<%td~?go|+^a~3L6AiF4vr0`I( zf;l1g$8b~i(Be4bdvgavZbkRlXfE5V@9jNH^TPaYD#HSZ4yC{rY3ab5?sWAJW8&bV zd5LBfhTEx4>D~u57#dO9z$6z`2mb_!lhB|>#F|Rjs`)_vuQB9bADKKQzs^oX8jBDX zOP)JQ!bw-nd8{--w!wFUx_saXgydQotlTAW1vl&Q_GbZj>h|fvq@!=SZKillJ@aE9 z|EhkrI0pIVG6&v@SD@txv+v{fxL}(#JJ9xChTo=w4sOGXe8#^IeIKY@cztO zNfefTmrF*|2Kss9w^}1=F7h37j+@JNO=~S|rjSx!;M(_r2EmyH?`m)#c01kbclBfb z^d$QEGwS0#HTV75K}HCsySi41PP8`MD>g@ke$j>22m!X6|8jdk<~%T6=4V&V*}031 z3zyd&Pzx@8gt*X?AKv!qaGIWtG_qey_0e#Ktp2@Dc<|bpM>ZBoMiUSGnfMJyKDfMj zQrt4+24o%vrUReEQuNyvW`=ShnuA%er%)UpPQ8sl%cNf9Y%mhMlE!wa3nZR>dj?D~ zJ=4k*ce?jg`67|#VcKx{du|&xTjLUye1g$sT>4rx8zNLr^$e#WEZBRG{;3(LKbrB3 zV&lwc4`LPn(gsF~o9s*z7;BA^=;bvY7g*$HLIe{> zdU0GB1&5Ky;*>+a;&gC#zSZ6?i>Hqb_pq6dpTkN4g_zbPs8DFp`_i-S#r> z$I=3AKoWGMF=LI!5<8c(otji{H{8^FTrqWZ&_OxeRKa8b>zm(xu9*!cK{_MsEtPjA zxbhPkg{2K#zW1+Ny&wPCltvXgX?_6IJ3and_bx^xFR2Qo$)OFA0Xs^z^eJ#4xrW8x zm<)lCGjo>4?&E^^gR{iMqFa`Q$6MJc!x&oY+Ks~Vh8^cOm$o|lwcD@5*b9`aU}J*6 ze`}tN1++x?3;zR;!|qT*4`f;p#y*#=NIp;n&%rifboT~};KNy+S@u?ZkJ07f-$yy0 zN4kj=m?MYn@OM~P*&d1yIVGn%b>87h|6%{I8}I(ONpU zC2)hl=P9b0SeyVxr#eVBeU_pXF58YZH#!57!R7t1f_S6U!yD0vM`xKVp!g)Q8sqE~ z-2W201bzE6xVs&>+e?3hWs^f_WnTl98UXpixW|ye*66)<#NbAP<1KAih^KAjlWDu8 zi)$n0zohytN&5ZH^j7CdAZ^*)ZVnLtIgYq;W}axd2%?(6$Ff=;iV-vHMQOU1gQ|h1 z^gmF_~NVIaRPBlzYFEij27{WS-PQq9<%vH)8@ zF*au14=Ep8P-_$m61nofXup`zT&y2jX0KyzDsdb@LW0Qy2C#6;EngHrBhoLU3!YIE zf$fokQA+!*86LJFr47-CPl}GVGyaLmgU<@_$XXEWi^{&Ez#Md(`VT|G-+UQLR$oRe z@YH4Jz~vzoX;zbYLQ{fx86*BZgUc#(Trt&UCWt-#So7Yt#r>-1=QKjatNuwk<~1T{ z_K@QHT9S?u+k!vULO2tWWPSUPh?N6dt8X>wDGr`djLONBnv$(=jZ`FRl16fT+ut){ zjdEe)^@{>8HAEh2a9Sn)Lxfkd{)jO7`e&;% z9A~bc#btOck_qMdLv_(rZS7_{f}1$(mANuCyYpA0R)))1s5$kkve}Jmqi)XskF&pk ziaJ{RhG8sFDV2~80|f*`x)l@zB$Sda$r-wHP)a4GJ48Sl8M=njMWZ%X=e7`)inT@h4m|X5>Bg3{ zC8z%jqnedLulQN~wq9qGsXkii2HDy)i-%_!jS;x{j3jKFt)@l3y0dSxXt20^?Hnh(<+r1Gx>iK^xg6a!j_~!HBuzRTrh^~L9D22UI zKPzBj?@Y}Yy`PpjnJkxUZY%kP-Z(1Xc-+v}bK4PD!&P(`5yNMB_?2TlLCE)H!Mpg4 zw)*nQ@=qefPE_*VzI_yZXN7;};29{~)ECx#C?k;(MZ5gL0N2f@Vs`9Nzs&j|yO;G) zKF4zxl}K-3!Ax~(+y(-PFV^Dd)Kc|jEI078om*uu6lGBS+N-jP*!(7d41US%$9Z7! zGi>OCe+lH+W!9hP*Swf|ArFE$KrTa+lU~R>Y!ShB znJ-xzU09N+bv-ZJ^4k&Zc3yg`sK{n@RMdFT|1_hiT3jsh{1>iBQZ|-gq&&px1Pv_{ zq^iZ;!sAQ997-sTAVlAU8xDZ5?^h-8%*Zc*JW&4`95M*6^I7+9H=qc;fcuB7x_we0 zF7kKa^7_o0d}FOK?v$^Mt~&{T@axVBp}Y!y|~@1Rb#JB$UDM5sF6R< z(|7SIsgb5SU0<@AFaOm7L0*g4p|3V|MUs7hau8f|M*K&}Efn7x%0}mUlV#$mn&?Jp z*L$n{(zOA|pti;u5L~#&QsVfn`&}iAJ^<6DyE0jG(5Oq^sfMWN_q(HI=2j|EMBL8; zY(>BYv$VEFozdi%CdJGd&d-X1Ft3aG(AhD14Hb>CR%U7XEnF2duwsk5ablw{tepx! znHSPFTH5Su6fmo#REE4qEgP3AmMfOt;F=u*pouy3hn zVIa#u`GXR+iWN1nVKBS`EcH8AX+H5{ObD?OSPvobT$p8@iWZK4<;D%~eri*7hCcnG zYXDz<8rDs=fZ@Y%aF|hZ-0uJap&;N>6P9NCTG?qRfdVpp28t7p)FmEY&+b zuQn6~fpLqq!h|fdR$a}5BeUAQGS_7jA>U{p?tXfyB8oc-J1^Ul0bMzme1THTD+S*} z>=1Nn`FC@#eXIlwuQ&b}Z^EUI%kHgMuQQmiD~X3dHjO` zTxGHUVt|OD71q*}Y~M%tiU~aN*&6Zz}{C1th`#A)kYX{05S z8A$%s!fAF9{t@2fmf@v;WSP~Ty`Nx5E3wDzUfLwhLzncc*^g+=r<87Qdl%u|zVqp0 z(|7v&yN$Ouh2k5(YXB`*WcUb*;QE*3OGTij4!dNX^sH6FhqmU;h3XPtKsGh0NQQGn*csBkePM3BXhNE`rZFrdcKkr7GzP9E+erm*-gSFeS2vI!{U<&g8dSxwoP5m@BfNveoh zqM5zm>9A3Jh@Ig-M@sDOMZ&kY`TgFG5DmCCx!L|WLwZ?>M;(`GoQGaZns&Mfq9c5jjMtrv?5qNowT zeHP%}^1>G9tILI*ev#)+o%2!?VCv4Nk8AWK9q_e7i z^u|FMPy||wlfn;u(mgcbT@tR&i2>aS5+=}|!W_Px^A{H2^j@D}Pp};sFO%Bg77FRx z_)ZTzdgu0eMl)(7?gsLi&aa5<4Rtt7Y7Yfx7@D^ph@eEoWL6}CE~k9d*-)A2?jPru zB@u+)zAWx?3ip~&5`p9-+?=`fDJO@_Qilr_y%gSLleNHiUv_s;8Mp1sqBm#VikG#n zB9r5H2~xJ~;HKWCV?(J`f?$0Vg?~xBB*FK4w!(y!nDhm)`cqzSZxmS8#Ga~oqNfy= zXB&$aq^*jNDgE^pUidsL+^K7V7enT1Xe3-F-JaF*{S*Zc{swEDSi71ZIt!zuMSkW2Y` zCxww`?~IN+)SGN{ypK_^$M-YU%1TS#svH^-0ww>X;;;4^_O;>cav{`phGOnc$eDfL!IBd5{*wp`eWlEN!DqlHQ>WXn z<&iR}*FuslnWwc61-Mc>>?IF7b;7p`!0t28Lz*g52448TOf7)Ah3{zGaP#Hg1-X?^ zMjiF5>bIU=eO|Ni8bMbkaTHQ%|NaKF$82}bJUElWSA02BeHd2oOg01ZfKP;Ss6aR0 zau^VyM{Wxj%*pQQ@8zCRu)$`=|5U`a&g&3_=Lo#cAkU6sH}1Tjn+$t~7d^nS3TF>O zOzg%cKrxW?G0@#-%h=E|%irqne}EJPZ4X&HX~^9Uba)oJb4t^LiU||Fem*iR$pOKU zmJ}p@8Mf1>8@xPx?71{xHy;b<>Kao02EG9Ii=Bn_v2!bAYZa&-dBPe7N~VYV47!lq z)hmidk2yKO0Wjsu37^TOR9&I&xO7=4J+&qt)rL4XibSe7D<<2mfU%E5MErK!I zWcEwGn16$_1C}aeHgE_y^cu{iOGe%|_DqH&eG~a;K|Sf)GY8)b)Q~>;2jh#dWd3~` zBTpwL4NIu`u+ARlHJqe2-VsCZm{FN8LfmpX%}T~B)o5xqUK=k=Nn(~3-Ye0 z)Rws9%s@r0Bnm2lu8+ z?JS@Sk}-H~&3jPK*4E>iM)P?F>wQq`R!#nMr*luE%onjyb4{tGmg#zlO?_WF!#wek zkw%$ASp@g(YuabH5c(X%Jd;gRSMrRw7cc4BJFCThzCFnO?)|RAsFO`pz9JK0No1{Hl6TOJ^_$SIIK62NRy%gbdmJUe0TM9L5^++#FiLA2My$F?x&Qf;5upe z`p*DN8zN*EV!F^4{Kh^E&eB3O_9Nna4=PK`gH%n($m%ZA zLJe7Ybo;Q#8Q@#o%8JLo_%6ZDozLJQHc=so;MMk9bv?oHVXtkz{RiV2I$p-rt=nQi zC$=Hw-=@#62;Kusbeut&m-G!`W4-YAnSld-XsVG}oE)DfL2VeTn)VU+5;tYxbLFotSdy0n6o%<9M^MY27UA>w+N+K^mgvW zjvGR(igO+J4dJ7M@Yg~yiIn2x-mZHR;DA8_Yd%mnSt~}?y(NU#+u~#h+9=QQl2t!( zapHevO#q!Q_z1{UoN*k}uN1>gnfGMikk6}0ojP(}f@k9Tp6Teb#c^M~+K`bU!E13L z+M?)UbE!38wQ4YVDZ^ly<%NHEC||LPEO5_qGU5|fJ206$(o0Z^kZ&v=Y@IXI z`O5R2ISi@t1T!bF7Q8(ba!ew*E`*A0#NL-qMc?-UFa3sZJRmk63cd?dV=pifgy9W7 zT+3qZ^KR_Af;-&-NSAMag0;qed^c`Aaduli4H*o`@JmaF6ZVe}#5{a44pco0>0J-S zne4=j|6&~s>6ji9!I`8+Jh;!R?C(D=iqB50t+IL%3LjV)b(r|W*Zq3@lxO23fCRy1 zkMUxc9q5|VGUh*4*u7tuOhGR1+&;zGIj~^w=sEjfbx`Wv`KBQ4E~4GE9cS;f+<)Ke zk<}As-1*mC%1IgDFArr7Fy?h*=dSm3etF{@e^=lZa-QJZE0GjtPM~%%_oNHFy$QC> z%U~~4QBtNj7_?UPPo{iOL3f5-F4&*(pTnsD)aDxXnYmsSQjO+ezNdl$~HGh_;dH|#LK{D706ORH*pkdaJqE zj(FISCYHdL7{ODYVj+fSJfK5b`tX#EBo4!?+knbzVN=SzTpQUyL^AdeG1I(!B?NjB z|HevX1uR2B1>d?VKkFgI3>7QR*t=@X;(o>sQ^2v7K=YPpJY1Fn>f;~adzvMwOV4Q( zAim$=JCLL`Z-dSTNbb*%4E_i3cLGz^5K&`I?%`0WHkw&t=#=*(A88D ze~ld*`jPHZfnE*1#Kx$CI8qFS;#qgznsxW(KGO#$ODUkAk6X(hgZ0EUS{z zk;eUuNq<5enhkoD*D|`@1n!$A3#QV9F4_ppYuj(cwL@s%knY;~F6U~YRDEOlehTst zQAO}J#ZbyH?HF77XI{FVIN)NbI4f}(oHqAsEXmsgN`Bb!Ru!VK!p7=@^<^CQDi)Vv z2<|n}%eeS-=dy|~XpF(>5+}BUcIh91P)l1EiCs0wk35c-Me^trhNKji(c;XF#A_xC z$2uYVnZZxCWJr3BAU8D=QZ8QKA(W^_4ckf*p`9%m9s`S2uIIkiK^HWczJ-%f6Y}PX zCNwap8*0pWyYS3_eg>%FLHl?Erc||}d=<4czd`4?I zko3ylp4ZFEi?EY*Y-T2ml&^8#MP}b>u1_wIF^d)ZW6j<#rjx{1?Um6=F~ZZ)MCvd{ zX8)W=t-PmhZier~eUx#a7Ee~{f8yQTw2z+zl3z5Zt6uEiqT(pc`DF|%FZPZ=u_Ucw zILTRG?DpLn@LdKH&v`sFE=lS*WovARKk|Ivtt*YDk@U}XUx?abkqONolnPV!hJR|E zX=f?pK&_S~OCISvOS=C$gFm&lSB}~lA0pL$aj_5AbsWLoMDimuFK)iy=y2@fp-Pq< zb5fnI-p7J9ut%SCYeagavPSWpVl%^?O4F%P2QxpLw)79#6{f>KwJpD|ta`R~6l$~> zDhJxzu6Rhsyda!fVpVErc=9kn@S*Grmsc9=w}r1@2io;$-RCeQav+dIb(i7LE@dO zNNuO(>gI6oEi-#A1N-PY^ILpTb+J|;SV_{Fwk5;r*Oz+RNLn~wKUNMl$DB}E=Sx?TweesmJdl~r8(dTlUjaZU0f&m=(FdQ5D z$MR;F^&o5Dl0;1`a`8jyu4MV1hYawE2zne$>4fiBp4@$ypni#V^ZFMk!V`8WG_tAZ zE;Y8G>ATk75K#dV}v~xOm&3$*E zM5?}a=e8~GGa)|Hi=Ly(8yjz%{=||%HaS$0NDm7od%lcDwj-CqJX1l(G3z6meRK?jwih;K-|;uIAmn1>KH_|f$#4DfEHEO3m9GMc zw-7Z^zkWT6TCuUQc`STdFG75#x0~wFY&w+nDwjo|B_~R{uhwbFcSa+)83tV&|NIS@ z@*+lG`Yqq;7x}Ax1a2?7c5m{r1Cwv;c0doG1 zazjyW855uoix_m}$qzF-YdQsmT`*rCxc8 z4sSy!9|g*_)`0>nFVuSMp~Ma7B3~(mQT(idB#Q0MzNTUZ;@?>;uM?u1og?UP!Hr_i zZbV$whP;ULX%>||;^sg@C&7O}`ND7UClsZrCr`ZexGs#7deIje{B<(ncC2WY`X7lP ziQs|@L*K(WsGv*}#EtYHbK<-A0!b)&&&8uN-#6Cu_VheOQjHXi)Ve%5b*&BA24q-W ztjaAXIz+W*KZ%|$WG-PCfAGG4X*~l9oNRH61;LG7WHBv@l_7ifQC3Hrr!ZjlcGtr*olEEe2Km+Y;4}gmjLXT1@-}Bw;%KCB;+T%%noxA@7Y{jg)V2}TI3*kd&va5YEcXAsoxqxI3*g(H) zm!jg%v%hq)$sTyzKBl`K2NFX;Mw+dH+{hk01LZqLykf(K=2+fD0N7;Fp+ixh6QY$+ z)jZbf+;^8c>~UBCcWB?i9BapEnIJoe`L!cXHJc$Y08RNi04w*^_*y(0=q8j-GvPd4 z_CWmiBdo*?7qY8^G95?8ieGRHzdvE+_PW@H&fDFgzpuaYVb*LTyomOD|ByHLE|g(B zM|In_Lsy{p$b<@n^UFGP^5`$}+BCsomx7gIb)HTd zUvs#gp&L!WaeJmYr<25=oO=vg&mQTzRz2lHhdMVBtHz!$eP9^QUkjwBen#Pkqxp!B z@7jg8+QdQ77Z9fsWnIYPM)V5nEdsc^?_6Az932I={HcF>u=HI=RvmnI0tH%mp9gQT zNx6LA^bHJD4cZ2ZQkbQ5J+mhkQ=P#{SscZpgo}-C)@o z5gg}np0O2o)+&EdrjPmaVDJsbVB?}TU0ZUU9LGNbL_X7gV{Ky=3Ma5PZc4^=_k4V? zcdMD6Ep<%wi6w~Fo4-pJq)s6g?bZV$0WN|!B&>*pZ`b@G$&MpVS*U*IsbqVH7l7td ze@6gT*}hHHR$T95C*;I1_H8dLV7Jrb_{kW00%(d-lL7-RXOVT`K=rVR5v1U1&Vf?4pXrVPKGM=xgf~735&XR<;_7|UFDm-5m`lv^|t`K!%oXF_2*JCDF$q!(AnGF3_POdtj z!Z=)f&XsWZ=|#FhMEehw`*TD<^+)rLh<2K2m|+8j)*;x5-??Y9A|#xL=HfNiT@HQcq#sQZTK(D_YoVO?BF0=l)zMP$ zAPAbz>f-+UM}(70Aa<7Xi^&S%YY<99f~Jyf!IH=x5OSHx#DLfcJ{k|bn}U~ys@3;% z^9`VM!r*GOjP{l8>fHTNVHshket_Dj`_{DE^G~qSgQp6X3*vk$=alThD;-Ym+j@_& zXDGp58T?0a3E^!^c}OL<5((cr$G#Z}#Xi4r z`mAq^A84_bPw9fnW~^IUH9g#R;fXq=@16D0d0}+`Xhio*Kg->HO+d5U%}i3CtS!<~ z%(_kV?a|{})n=|+T3bj`XO|u!HeC{P4~8NPW0uxJc-UZ$CI6Z&5TRNbb{2Qx)qu59 z7Os3tvCV$#pB_-9@yd;)uQNIp)Z5*ZFNoR9iCz#7`=9^g$Yy@$|J?jv7k_=@uQ&g% z&xZMly}UBDdzMm!$jDrMlnY!i9~G8L{X%quKh)=#s>#901T8#;eu*=vNilpSl>lu+ zA@ftmdcPdhodo;)me3gVK2+tKQ0OPs;oBO7~Rdf1WKZ*86{ z!29q%RvJY&{m44|J4e88X* zQ;n0&KRf=CzuRo9eg@Rm*1n*4!`qP13|&%2=GeoP>BPJR+hIFU6+RJmn*s80wSLUf ze(+Zo4)D|wC3p&F!h zYxIF84*&hm%bHuCKtFsX5B#5&UHO0e(f_A{N2(Q7RF3K-#|CbbldCH!jBb@=2l!pp z+lpv1!RvK93ci@OiWhpG9T!qMwYLS-q*gsHlEmwtP%60aM_!2SVl9^xEsI6lX4fWU zM^&RZOmeArOC|fxA*!_CtJ2-=gMQj3j?i)-K9Q>t;`qcm<;qjC-1~!6#ek5UTcXdU zybo_$OQcqqK4rXpE!C9UAVbH5y*oiAgC~(m*=XV5D&UH6d&uWDbtCe=E~D!0o>pta zFncTE?n+B;Vc+MN1K6qtU5V|;INWGy!tI+n>mBvYj8nFUr3?1|o#H<*Et#*S#K&#!^+JYewjKO1YrVe}NlAR12( zz!l|OFD<}s8~1@c?dG~AkA2I7{|{RJuV)X~ETO}qg*F%r>osz?K{G{)4{70rkrkw{ zlwSQ4Db&u;$EEPYPDwFF9^N+hu%?OecE+i<%q)X;whp*s^ye*4J8xdK0YqqaoPtD| z0-)^pBp`>gzsR(I+kaO#Af0p4${AyT92eaZ7I2}PBxAHuNHl-CGDQT0F2VgE(N>W?g)5wr1F_-cJPPuOBw-CMDbPI7smCfF|r~eA||8ti8 zKe4EP_xkJTWSV;O3}dU<-`Xcts}tV&LsAU;aXB`Veo|1KoPsuffa7q&=%SuF7)@U4 zXZ1uT+(xB;+G$0q>vq*yQt*%6b7k#j7v7JFBVFxtf+f!zyEL=S)mrQtXT={2LFXK| zQ#_}pzHUzmGEwl6dC#sL=)!#$U9boIki=TZ77`x?Z{Fx44TLT4Bxky`I`m^*j-8&Z z7LGYgeQ9T%?OxWReFkdkuZ8*WFKlK=9uAVEUCi>GyJ$YC0uVOka(D?Gl+TMgi%XaH z#2D@!t38u&6>Cp1h6ULaoY(H$sa_6owe||A*-aT>s0lG~3B4T=Z$X8UCd)-6Z@ z>Q)GISPsv&tHYL1t{;xxu4WqSj*FIEvR8RtR|eeay8z>q!?q!4ID|yZg8zqRnbaEP z=Bse0??`{dQ!xJa-A{k2P#+9K<@&Ppz!_VyounAn8_Wg=eg>*fGY+Ahtfo-Y}3_GNzpwjX51RJD-!j_bH9bWH}t9C}Vlc zkurmP9ODGvj%ZEs@u}9Ky*)%NPOK!RAK)Z-?<@^ed+_%njG9ltnGN9njYI7D;Bn%*6^F+EYz zD_D**CKBH1U)iLWNOI8+Q-WXL0^$r)GpJ5fcH;w)`ig@A;9|75qrf8;p5W$|l!{l4K&tuHNqZ`E&|8d@!? zrJ(~gCr@K>`s4{`@?;CF%OMJDVA7ph^^Grsv2$j>%4V#bLTf3DjW0D;fzoB!Q}{+9 zS=17*!;>(hrijNHwxhL9hJ{_Suk2}`P_WL=fAhVqAm&0}W;C8@QxIXT-oT*sPS{!P zQ*`s%bFoh1r$J9COKcr@Hw@#AAu_#PFr;~B^pg#Zrl8~{a>fw*7!K3_)1`ks`!Y~$ z)6C$R&ZN>DNh|{`A)g%AEA$1f;dW!h1Hw{+C#odvtb`NQ5QAy@siVd21{(_0S4N`r z==jY^Ks!zZcw$tyLSQ9q--Xo*Iu0xm6ok4#xMt>j$hOfJ;&4qCXv7k-U&VKTt|CY0VC$zgTG7N_iv}8k@#^!A&pbj9fyEm(}2{hpGBA#E|*)wSN zSEIPEGTlc~BbcKDel1uMGgOS4Y{w7$|uade-A@WH4i)1Tlg!XxHx9r!OG2In9 z_RB}eSxD%z%VN@1ATZUBvVFBK{luF~&N!uSy*e*T>Y7U!%4Y_OWRGmKXbO`T1tpi zG^~~6YziHZ7Vq7U4-yMrWtJHELq^^bTK!mQLROQ3SWE#^;ZfGP)|3!Sza_O%{W6p) z!34Hm8autqIcGN%Pwy~j=09yjVQ1K%T~aDknN%pa<4tivOi6$n?8^NIt@-cK1knf+ zAsA)T1qQgN>%mK7R7Ib-3i@F6z5KgY4HAU&YpJ{NMW2hXbBGpRb}JySe^jAPu`N@=I#7O0=4_ ztoWoIkSz~29sS5(T2~ihAS3s` z4Bbyx%d_x`K@JwHGXmsXH`m5qnK>diQhuy0?*rdpo+fnoDwFGN+G3g3@65WAu1;JY z89J%IJT>-M^T{gEz*2TSolhq`r%%*_i4|-n7i7|kL)aPxn zZY2u_55R4=*@K>{0F?y9k8S1GzWYD;FXQq0E;!rORpH5RSrTfcjjXA)uj5SHEvkd^ znsPSlDZ9kRP(Od&vI0x3A4f#cBAO~Pzjg(IlJNAJMBRQ$bkE}g0~c+TMe}w6MpL8D zt!sct0sr1B)l36uQOy=77tPa5AZx=BwSZ9f$NNe%4e zV1r?Q)}J-BnpV&Zp&EuG`Q2q$$X9;E7H#N^l7+Vso1A5ajJy-v%B=GgS{dlWkZcB(|07?j$76+A$Q9qat!nJ_=qXEm14K{q3P zSW{5SYsiME74#w8$IEF!+PmuAVg;|zI=qxi<-_9FC^x9Hfp*9j$*@0-nf^>%%N*kA8Xe;sZO0=KiPh^9X(*JDgp+idABR;gHAZ?@ zy^4pF{q+duKwAewj);w> zpSxx0q;cA97oE>sdTO}*=X}3siddOVWZRU8iVMBXGH>UqR4kE=P5Gl)W|pTE9y0X_ z#8gD?OiHG@tVggHO#$*OjF{Cu_#BfvD>T1F`+P}^^3OY1*{>yDOGZN%XbV{+ec~(w zn0XuWrrKrB;VHC=k`QKDsOGzSGkx-x?IYW%w1G7#9CWC!PL_!nbUr-C;@BU9CfVBXR-Z7anEH{RLD>Sb`^v-ShQd z&6j`cfy<|_S;4X-xuzqA5zRYL2t%zgxd^#n!l09;FA^H^0~<$ zu4mf%Q`MBN%)1tyCD$Iag!S^1g8gXc%`8oLw`PQgsGsKMh&2-{xYVrrvZ-$#5}=Y5 zAIbG}t`%unZDgodE^dyA<8RG*Z+zIac`}uZp=!{4SnswA{jH<_9$%pEd3q-Ig0cMH zo&3Kl`hQEOJ}6l!z0dnB!Q)kR^7fL2v8k~lz-0`4bs~HdXx2H-1T>bp&hw)WwR^Dh zgc{|^$8E=)dCU!e%0+I7Zu;4jt&=U55|obeT)r`HeeNbq0$5>bY01sajju0Oh+?sr zGmh+3di7cL)#nES`B^itvacO1Gnk>5n<)Bc^gfKR3(uR3;#H@S7G2zdb=CuhzW6ir zd5o@;IoE%z^Zz{fIvO~I4L;jyQk?@|a2bG!0FfLff=GmTO&Cn-o%@Htdl_Gj1#3I^ zn<2IG$}q7osT#DA(Y@V^xJo}K7y?e+(j3`(j5Bwk6ib-0`lNkZ5SknY-q6Vg*bAK5 z-e&e`f1cvU2yZroA%q|3SdwgX;3=ZcmeE3eeuxu3Z5zAs3!nqqEwo-JG^L` zb1-_=#Dm?x4V&$bPaJHfDlGKJPY_4VaOvG%8DG!r$cu~PbwdYHJ<@!uH9`N-L8YJzz^~B^@oD!82rTP6UaTHzx)NfAYyuu zJzI^me{VNMW&l_uHn2Hv!0Sg1%Dkl9J)OawWhiNFVhVL5%7rDv_ttx%8jKon^w6S9$n*UTthHyMsWFZ(mtG8sFVYjRXi{69)*=D_O-Rf zavwGTrz)D^`XkrRBOH9?c1r6@wcu4<-Q898v*HmE5gUZ<6^BE}87rNZ zuR6Jyn?%?C(!PNFEE^(weNzpu;;LLQZG(T9yNO7$7ui|;yB!q)JKpdD;RwL+_p;01 z{Y);vJykVK^FDT4<$85OkuBp_5)!@kt-zgIs9j@4`~^Fip)Q|~rLB~E&CjeFYnAHC z%*g?SrDKWRzKYdv(frPUvMQ@+q=xO6rgXq?qbJ7ZLjwo^F?7IpvE@V9tT(3Obu*<#C#eRGJhQtWdrnWsf&oPHHgWB z4TbaQ-Tg}giCQ{BavSGG-k6fyaB3Fu0gb>pn>NsR-G@`5>B zos3P5`W^-Uq>@d96Et0Zsqm&K+zEK|WrJcBWz|{2z%yxHO3JnG0ZuIU28qcexq}0o zr3Y7x6cbWFqhu_B@Qmu&TeP7w-4PB7UpzS>B5x@tL$_3R6AK>?^xO!{&d!WXE?3{HgH>BDtE;Ew2NX4 zoclAa(lbBg>Q!m+Coy8^s||(O^WB#nrC)TiIg83U=qI%6Ev9Yfv>Uave7b;kUJNgM z7F#+1R`}2NesVEI&LDkJO@&SNc+|!PWdE+>NV2h%q4`mgyhsGV)i*~PUC;M6CQ@c? zWm;4^Z+|XnxpX((-y&teeJoNUX&F_C*@p&YqpG~O{^(8HRj&?~K8jaq9Z#!E(NJv0 zye~{{kb1}AHfHt8isVxRVplL`9%$&5REOaT zb|%?^FnaQ07-TyqeAQSW`RC`~d#5X_`n41bQ=5`{rQGoLyEvppe}dgnlF{s_DLOKy zXhMkcg3X9^J7Tlk3pQ%q^d712=GEBj%Ca}lQc zR=PX--KTq*WMF(zYOSx-t9-q1&T04_&vSU5kG8di!=laKT2EBn;aKxRIK&prW*7Se zdaWSdU_x*y#C=vciNVMNVTZm091qa}h-hWsn0z+3W*1P!_?`SXG?PC7V1c$L6THt4 z-5XGfj~6Pju&%q+=T1l!p1iL|+eS{_TUE#*3UqVvPj@!~uQofXd(qWuYxz<_y;kfx zcr}>etP?aoVTj$qCQ0xRn?Xb8+v6_4Q$9ZZ_*&VJmhvqJE)1RS*YI*vwjE z&DO=^jP)3!yz(eyHt(p6a?ENP7XXL4P>bX@}%M(Uj)5YP2Lh?a_) z?8WIK%h%PI@|vNaX_zf1J7~ieH+)pBY{zCwPG^0S1eB%XMdUdu?+04(IJ)pD8|vDp zCMpHMg}6(Hg=R5G%ec~u)fMk@mXYSN3ypN=c?zmD#gg$vkV^kVoh7r!cO#Ga@RQyi z|0gI=^QTf^yW8osMUf^Y6XoA}qkJU#(fzqnP_y^DqfLiRsyi~IeZMl<>hxX%#!aqkYjz|Y0GMiA zaHA3~HGk-6;dVDGg1lo2EayKCUFOxouCc!Z(C(5))W?tend<3K^{9NF-*EwB=Bhhu zZDycrje>ysf++@N?Oa>&FgUy;((@?^b#dO}0CG8)`gp^03kIc@>eIDzk%Z@vb zt08Xg32V#z?#Hi|oW@G1!Vzj%H|E2lvWeDg95$2h5$m+UZ{iXmYhceA0tg9L&|CeSGjKoey&jnjTs@m6ZjUla4j%NUN_31{z zA_VU=^&JZH6znO&Q4ZiZ_mwflF^qUVT$jPPdPeCs`@$f&z4p$}qi2&d*RADhMYghL zYZc?Y_uXnCMU1%kU#o&6DQLE`X^zD^0TkIwhs&*|GvdU4sl+D1yS*uag@&D{y~B!1#xRcnRU$!V)cS7!_Q1wv=o74B6 zya30kr)eanVH`$UZ_dhk%}MQ(s$z3#_6gY|TkI-+POD)mcCpHZ%(9i6!yqy1fJd;91`=|bVO)Eh4GNL$^O zTA663FHNR%j-Z;yVp1}UjFfe%Ftl*b)(Xo(yced}cXmhXv~f~Vz^V~GsxUiLrP~aY zZTVZ(h+Fmt{mRW<-bPueL{kVs^~*ozf4#h1TAf2v+u1x56ix(nyS?gjO(a zP;Yu!=(K}j`g0&swoly=H*ivX1!k9rrkm!G-j#d+0?w#0PC^k;<}J0c9=vT(tiNQC zD|hmyv-Oi`l%I^8i^If@ep-`U z;@L(Uc&cN8=4%I%kniB@VYH z%oN(CJ?qs@l15WY?g-O)pgg3S{%Aflkd|l=x}LC_5gO^Y_7HzEt6lSE~1Qahf6vdtewk>i&Gx-@gRx-L&xzX zdF}pfV5p?O)!+LgEroc#`g^s_krv_{<+m{1TyFDZfDz$e;sVaS@6{tzO|*7g`+cuu zrIf3T}>Zzt=|sEIT)D+m2`fSwm< zW_OARE_$)B**>9Z=8=K*54=<*l`aC0~_<+)w87HA%zZwJIG%v~#-9x^`h$ zAU9?!Mtr+n<*oRvrWJskB&CKjwA^XZ{Og_kvr%2|^R^F%Qv+I6>`UhzW+!54_SN?P zN#ej9X=Hz?#FrM*T~&>!{4i0G8mx+%yk6`K^msSX#$90d$1cT{TbZYsrM-!(&^L9c zC?A6uDn(S&hVD7D{3JJB6txmIdNIzf4_whhug={OEY&Ppi~r>wl^{YI>QdnxrQ}nL zAYR@RkQBc0rTs@}$V%mo9yI+c%O5~d$GgU#fA zYuh#eq#SC=OIj@C99s;Jv4womS8lEaFcY^D3B30W{y?$l!0W)efKQFJ3E zXR_VjiySh>u17V|v0j5s4E(5J(^+MxsGqVTdr%}(J|ktqeazSn+t-^IL=2iwp#f!@ z1%u6*m~e#I{ByN!)1!2@sz+e)NR^WAzjI{xr7@b^Kk#8sSoknyrXs+emH-io{EXmu ztzU%6rh5*RD~UgfYiqV?toc02Ryiwt1^(hXQwD1WBIp}UW_;BD!`pjDHI;P@k1)(NZ5YyWAGHfc7eB}MY9X(}KI`LNhyilXrwY&DlM~@h`b?91F z7k1q^YGqRtU$Yi|*1!ME_&Mg}rys(!gl1{_TZKfI?Y_#U5-+NTyiPcBEfveuLRMKi zm4o(-;tNmbcpd*ZYr{rEzF_Vge{6n_yg2NZ-rPjB6`Iyf45d*B2d%V7Ljigy8~TfY zab3l2Wsd2lp^PI4w1byjBDKq3S_C31Jg=9LdqrIY>uWiE!XR77yE4liomzHhIRyF8 zeUDNTXSVG65kyn^=5D;@@lL19U$1_X%~(|*9^M7+xGoR!H>6kE?YNJe{{-PM^1Dh9 zLw*iPLy?3U16@GziCthF%CdV4^@{4tK!kHSkChFQIzM#}mNoY5L6SaNd#f``7yBmL zfmwVpkK@yUjfPp`(P ze5>}-@;(3$bcO6$aZ|U+2a)@B+;Oo0@5|Pjz>#bBZ6&XG9vGNBQC9hggle`K?)ku_ zSJdj(&Dp#f?A3F#8L3P?NmmMgxMyWj0`G+gE%)^UyqKHEJ2a-xpH5S9bG-|&Xjd@& z`i6OFfA%&38mpe{ygC?Ve0)!8iaBS+oB6& zg*9m*m@^)QET^#pCp)i>9mwO0PHi4fb~=kI)9$$Yl3xhYwcRgV?2J%PnH3~o-u_zs z{pHAlTKMKseDVLN{GWH^bsm|k6)aFEaEYnSi)foYNqGS%n{d4+Ueqn#;%)!&!Kmf~ zAn#huM!}F>8joyp_&IuwJ>y$3szf?n}W2FKWXtv64T{N|9SM?L6E&P2*-D&jgZ__F4UaOQ>le4Vsi zcE1ch09xRZqF-5}uIOKuPl!%6oW{mJ9q`U>eFIOVL-UcAu43046}wk&7t0>(K#V&M zeJypRu3WD4S$K2BInHGqddw*4I$@2y%=%SVrDI+?Q}%!K*H?se3F+B;l|Q!6JbjW}-eHA|RAEeGa0W%5}A2xNzvcs*E*!^X(kB^4@kJv>T5 zu9rW?-LOVQ6Ksa6r?Oow>|xrKf99RfngNvzy7=O`Rm+$2i{40lSz15+KKf6GK^y4M z+lEutgTI<=sQtGe|2-44!|EwW*Xe^7)9riO#+tW zt@uP{TWv7(siMd-RAE~iO=j$p?oqef8BM`1=xPk9-KwwlwQ237sWX=L`@B`V#e&Yf z;b?88%@vlVR?#@&;_aH$3l}$OSQjD>Vg2Gn4&LCJs@jETkv(tCS2F$xnP~x&<-;Lr z9mDjte-0?Z$ot_PPHOnwsM zGE=;euiEVCth~t3N~Z>{G?hLwcx3u0W5(u8mHk|KP*QW)Z#$wIj$rD?-C_exW#nRW zYcz4e$*kX`jsZxXUm9m>FGZxs8E20iTCw}-WgY*SBea@)m6IRG1dvx>c9AB#Tld(Q;Z`jzMam?rND@LRtMc}^% zmj7&YGP=#O@z-Hp*|f*C*&Kl2+zT_+Fq!MQ9igsueJ*#aeDveGAE<1vR7m7}cXW-Z zw2^1k-Sv|{ta$KoC)6r`&S$+{Ectr;E_r<9LR?#q4F>I!GEfej1PM^C{+LgEZrXK1 zaFHKg8R&7o^TDNZtpn)}*4j)r^l?R+XkPGf?XY-MVwKQ9p%N38?1bt*qBB#$f6ZcW zwPux-fQb^UX2OcBGz8)7wrp^}_*H&6XP#6jkrqP!iikrNTg_XhsqF8cOe?ia zZ|-NBexdbgQ&)Q#efuiC+KGZAOo9#_nVCgz4E&exuKcXSeJ4qV85 zbfk=X`PM_&5jT|JIoZ?$@AE6+yyYnF>9vk9RN)|S0J`UAM8d{SagRzm#8TfqIHy}_ z_9HJ5kj@LX6Bg-bM;}f*Z{uBkP5B;doX_=FYL91 z?0Hi;Uxu-6gqNLO8QS4w@mOQWqlOfp5wh!z51LXNQ8=WumgMpNRs9zaOqT|aYj_t5 znwqaX==_Q7*f>4+VHdr^O`THG|FltthaSk$`OSHF2e9G(`1JDLBy=`BW9>>lyC`Qa zwPWAx<4N25r06$S{r9L=pX-#T&}8Q}=`bR{FrO-#w-19NjT;0^UZ=Kd6#SG?gYgQV zw^1sY<+dzAnXM70LPu0mZT~69Ixov99^D#KK;0@)XZlbR%rgCyw&+RUGj~JNH?7)x zol~ntU!1%A`x_)Ku^+U@`o=4*V$By34S43c2=7U;*nHsNRQ6CwwC*sqJxeY^ARpaJ zzwV5KId<6OR*tQQ7FN=*)Tm*JOS0~VWGNMZXviOdgKS*= z&J3UeI(yxT>yR*3Gjw_i*rXYjuLoJ&4>ts_HW+jjNoAG~!f!S!5sZ@8S)}Q<4M?s} z&3L$8S-oc1!g<@Wl|8~%W2XX!u4qC#q$O6Gv~)6)IFs+xF2=S zIL;t69o6>cIqlIrbWE_ql_hO7uKQo*oE7rmw9ikIqj+nk8NOd{GgJ))ggeSd`PUqv zw5o+wE*8RcQYwf%v-O`cy4YQ8U+W~O;y&VuCA+ZqPo`@MV5cXw#9L;E8d>TJVrytdSdTyp^Hbp0@jOxk3&Ew)%CV@TAhwP=(`v=h0W~7g!F^>qfjf4g?ZVTKi3AclobWpqKOW0mkp!F`qLVV zpj2h9;$xEs4jr`@a&MjQai{y01Rh?TE43r_BFuxL&)32#)}_B1N_q4v81!2*E;}i0 z)K3Ml)|9;_BbLm$YlLbw%G3r=7LzBKdT9!s)|sMp<1T-6x-w$E(oFokWpSE=Uub%2 zl&2sG&y-YD^d)uaYcIdrS%?zgv}jyI2cngB5MAx@Uo7SCdAWI9T+y^|dtg-9Zc#$k zIo|)V-g+r)52opT(V_9Lr*mbT%P$)r(bk+-cQ+v}72lgTAm)#X?vIYW9+g!)pR{C8 zx?e_zntM!lu##`W^7@%74uZM>2b@<_$c=|rq*z+vz^rD@mzVMyi{$Zz0f6#!~i z52|Kbcs4ZfrjvlgBD6zLt%#5|!do>TUF*$+N7XJWDPxbjQ_{ehxr~kP<{J9TDj_^s zdag^}gjAu%Mg&b`HO_I|R#4}qr&SAqo0W{(3 zK4fd;Gd39fSxe?bWuznj8Jm-B0W~ICIF%I1u;4k4e7-@q6WRuSBavZ6)0ap6aM|`K8WcyZ&-(^7M%|0BAI#sVfuQ3#TvsqyR82RH|{3 zBF8`QOr{0;kT2HWu?}5gR21vqS0*go81jE|yLzFrJnCc&MQZk$+vY_1U*(vEk1_}D!{qCi`hR`Fhu|@E24YV(dXm=M~CCx{MXxZbm zu&Eekg*&>xBD-Yrl5;h$#?aTEVF4ek?jziF#{>3fkl8BXy6y@KA;R z3n^A$)w^%~>&^yoFY0;|cn=h~?)*MM>mv9 zp5=gA(&RPsU?jy}&uHB|((vV5(=xSP0`}XjImr8BPIK+6fe(xqT8{2@wU0L zM?8j&OFPMnko+E~n2h*klqu@n#8Kuo@88ve#+i`13guc1l0Cz8x(qh3s>+t zHmKV;U~YeA{*>a=oY)Xi_K-jK?nVQ)n~ja}Od~KA(}aiIN=AQ*sep$bkyl8lNC+3k zb@r*C1g}us6C5ry^TW>5NF@ae(y2j>n0MYjH#ZUZKTArQ_STWE3&44&OW^Bh=|gup z>YC5UTc1&E6VLXW%5e5x`b;by0bc;+->?mtykQ&8WqEjWXdQa-+%&yBhR*kkVcdLw zOerYWFSRyg>L@NpcA>U(TA3cd2o`yew&4}0romga_8)gvEAP)p8hu@xe?be`kp_J7 zObn<+6Uz?D^EJDlHz1(UxqC6VlW-G?Q)n!T@%-Mn3!-(umN|Mo`Yk6_!JGm!fW5Rr zRo|k7&->%Kz$~DCX6fBqL=k}>O$!aoB=UdFcfH!*8aSk_wF`Q^*hbVh zgmrV}Ysid=;v0zdi)Jv7nN-;sGEwK=C#hitv|6fO9zdz==9DNP^CoQ6#C{`q$~!gZ z6O_@_NhKyLAK1VTB~6GH!FbY>!e7P-lb5g;Dp+(8%WDxzY1ee#^fnwh^5}Mh-Gexw zT&5OsEn|6ct2W1}lUyXLfA1KkCtb*$1IuRO9w-ZifR$Ndm8rEO*TDfdcUJ7Z$Xkib zD()GVXZ2c6WunGeauldqcoFw4kQzmT7lr_s<7ikyC!ri`*-%Jx$~PA_>u`o2d3x{~ zZ7-h`23Q~k)-<%OK+5CH!i>n0SEOuYSPfkI0;0P73reIN4fnBs0AAR$q4VfTzvOm} zN0G%?Wc}07KdxZT9Yw@>h7UT9GJL~^p5GYSXnz~P98~ra6U@b&YD)1_!pw-KHY@Mo zHm&~UfgPbMKJu-q5*}9-4~r6a?Fu%$JVetz4rI2gKYb1emBJL}HC{n9FGp|gQ7wkw zy?k5YeA{+Luft%GvQqXbPcL^ZYKny(4|j(v@O1Kx3Nc(Vde#uW9w_XUQtU}%2@^VT z{0@HC#hD{i{+f9jxNAF>@ez>>cBo$L!e=p;xFi`ZaDk-#k|{zYGmjfsRr7>8 zx0smqykBOG3f z_f>qSa41bUvHSTgnR7iNcgN3E(SoL2nDdQc@$%XXnY|V_yD_Y5{YfvOD8B6U$Q1VY zh_bg(LOM!G=5fs+E(m{SC#qL>O|Wd|k?A~$O}K$_oh)QGc5m54iO1?7iSm=WfgN%u z?QdTIWMUixse-PtSl>p;pCxq^+fl3Fg;_Llg5yZ@@q@ zS`rilNjLV))NhqFf+ z*BYyRTvxHZgy9Mi-afB&_A&hq%C?{%@NPwGn|*;*uhsDIqe9oy{k3bX&23!D9dD6J zK#$5K6DX@!3^Wi*@yTbDC@Qim8L8BVHY`pws*BLC^lQ}@8KF=Am$-h1l2#uoREI_a2%G%>L}k@XGh6p}2x@aV3-fhgvIw@aq2ECvYsT~fmR5b%vwsnem%L)(?7&yxY0&wD=WD*JbZE|p2Kqd)Vxbodn{j^D zZoQ8rhIm>*eu?Z%reCpM$eUu}YiU-gd{rJ*f^EC5`Az;$+NpBxIpl%EyA2Deos7JT zK^6`LWdSbT7v{dgH@BnCL-k+^F3T1r9lpV~4ew~?hD2r#_1^XS~uuj6SFbqDbPa25j?!fn4IwWas$r8UbTLfvFy@%`Q`6(ZM zHGjbZB$#q9Y*c2NJ8oPQjtuKmEElo*&<=dXj&yZn^(d2`SFzz6P|gIyu2^L0eL_7m z9~w5NfS-FIH4`o6h$4o})N8X|HB?mL%>j;3grXdDu-$N_GLB&0+z~Q1^Dnrbl|#{n zx(Xx?B;JW^C^)muENrKKK)do(+HH54x4nM5$f|P(Pic+(vGZ-kO8b7y`rPRqN0SIo z$W`III!*q%DqC|1h{Bs}1XGS0^{@lOY7AD3L}bRIcHDTB5B)6o4)<)hfi&`p)CN9h zv@m~2Sp*cCAL4GR8S-L}&#%pzPwNPdej*Bsh?FTcqG6HGYONLR{X)qfYeO5;$ulni z=^x$AneQA!i^Hc@RUq{f20b(>1`4QF?LcXImKZp|en?nqC-&OpD`wZHQu4X$&pRk> z8>37JS)K9xF0-2yHP7X{M6M*5UkDKE%mt zyhFVAZGXvC5P_K`y61ir5XW`;C&W_fe0k4RUfeD^d)5>0PH1^u;q(GKlmNf9gd9mBdTeL;)15ZcZ^SIejAZd4_u;chAGGP4(4gg^P zNr}eyM{*P@sG?ibYb2Xu8)6Cn(LVtbrpAA5LzMrtZ;)xPh507;-+dI!gSqXYX4OFZpn0fLq7%d&j~(oxrT(M zWDY$8qQCoG0vZ<1(@M+9X@9)VUmHFhwo0LmyJznW;-g@gEKT0IR85qHWYF*GQL|Mn zJSt$xfz283S3iAVBg%@QI(^IMV_#-%^rCv@MOkqYf_$3FKjHP)b;|nVEd#EFdM}NB z*)aaeGNH(7@H7zArSa0j^6Ndr5zTkMZL25mts*C=ty48OY3ee2Tg+UUHQpSh2R+(< z#+c&qP)x$(~kTRjTbLr z|1KAf43@r44ms6QEVo!{Z1Y(oD$F(h^g^;k*7y3+%)-YxEu7Xct?6H2;8&h~VH@ke z&IgU`@71+CG7xsjC3B8b8f`V3RPOXCMymJ~6KcdOMxfZqtejH(QQmBrVs|-o=>2mn zePtV*S3AfTh56@jOvNq~T*uf!j zeMG@mNRo*=h~@g<;ih~I+~`}_j#hKPKPa+7o<(H@jlD)>Fh9OMf0mB66RV*XM6|j` zMrCHw=tifat=WBt#w1KDEuBvI>RWq!Qf0jc98xQXn0zENu2D8cx2-JP-L?&`=Fno@ zo1id~!YxizuGGw1?0inCqjb}JaPCGGF!SWh`!yzFZAief0TA>))srN$nR9(_e9>jV z?G)9wrfrE{oFS`6>ZJWC|3S`TKp?p?)s00UbvZ!80;ncj4UK-D+S6S>yB~YH%OY&! zuj9||7sQpO+3J^#rA6T(t?Bh{zPr-vA25htkK9gw_VtJfM`*lxy#4>I{2zB{yzF%L z74c+I=&hHfwiFS1G`L*W* zXlA!sKWgk<4yqhW(IwA=zT&4kI76^mTCfw~5m;Ps9nempGLk zTQV<>L#W;$ab?{DzbV9|XBM06{l9Uo<+DzCMuDG^s0((clsWbD@ZH0#!s3Nc#mB{G zGHn}u?3h^%Ws}rJm!G3T0njl1^BdYDda~0=L_H&UrK%#KiEYjJXGh|OA%6_HU&9K! z)e#WJ&cyM_dj2k-0n?d&v~cA!Vu#wnNP2#7jkGAy3y?Z-%_lkZ?(gzjN;Ju6Cn6#F zFY1f0=n(B}Ji|s`G~0BS`2Wv`f?Kc!rNw(BeR6)+T?Eur0Ny7lW~caCwQ6vhG?|3 z;pJUAnhtlzSo^6Vo@X4q@ZTBs-?O@$-dz#9vBPQhiL+ZNZ5OkD3R*ni`Qp2u)FVoV z9!}^TUn!Er>xb3YipRpg7@c*ZA@~@_yFBL442d~w4Y40x#aXQfdrq1(-7l%tJ1e?qY8yjfe z^G^<}>34HxbkusT!JlT|47B+b*W5{O)QO$J2=qVy;dS>mpww&xps}9Ex;pDX77{}on{HTG6iXb4k2(kh98Ql*=0`S+ru9|OwG4Xq zK$Q+xhT-j%Y)Yaf#g@+?@Sd#(Ie(l@H`?P+6y%`q()Q(x*VN~JrDC%zJ8wtDVe*fg zYWYw|J-G0`f9bKbl<8K+F)4PMuGY7-)~r@~FoV-{8epW@Kt#24k5#Lp;?4~iM%VCu z74H>{$li0d6=GVhW^I={;$?O!;JjT;LzzXwNefp97dP}2QbRm4-w3sY!H-eD`+f0Hz3t9#M=la@&fEe&;Us8%nW{Bh^M5crR; z2&2OIlRzrma5doL`+~MZd=C}eeE`z)v-HV@njjNqQ1OM$!$_N>m^9K z=;C@a z#+jezmR<~+o|kfp=6g;Eox+nX#j*1xv{#;r z+VkOBzwJujRy?D~yQGo+yzbF^@IA!BlPX1h>Jan9ewmpOp5uoj)eGX-uTHm?;_fl; zT`xmnJ~j_2V;O5Hwcv(7HTNZNox6}G>HMSC#18odq8KC*k`L0dXGtwa?EzQOK|3Y8 zdu=V#m5HQ&tu8!or{nn1gwKrtd-&PoV>A0@JhLn|@;vAnSJE}N7%x$53nYTR*&8OA zo!=R5Vdop%G^0~!X?nOXZ_B1{z`u&~azT!6XyIX=#Im#3bUY*xSw6!)blY^vvJuuw zcY+PQgku{a2ra^z?(n!cYB2bPHin&)J#%mnski^0)H`0DXyRH{b+T&5zaG6=k)j(# z%Wd^CGPF62eYdR|@x-k;f{A8PJ5Ju{_ucGD^J8szgzsvimzMi>MiDU(!A zxdml2ajnaLWX6;nt_{pxMMGH{$+!p7|1!Y-)oMyWRN@U2_7<<>`_u2_wJy8aT6=A9 z&IJs;um&3WC170eY%pk*x4@<=GzZa-4Ii0}qz4D<&HdWR${_7Jr>wd^Ba=er}`|Ef4=k=qIjUNJXi#OPkeS(#tI-Wa| z*!ZgOO|{qqia4ZnqH<21nds2V(QMThR_5WQ}4$s=R{6lIG+Cc#kZ232#q{| zl3VszaU1r^E!GPNVmg3inwZNA{sa!mGfIk8ue`uB$lT@pS6l!1iZJpRcu>T><3`?f zx9#*`%?T}y?bV0I3l@6bYi3!^SB085XzWdXW}zN8Dh@<|`fs&Qe$xN`q$dZek2Ym0 z%@ftui+5vLk|DiwxeL|7A72$4r{O#bCY40Y`_-AD8PX_5SY6HN@6{5ut}b9K8Vf_W zJxPKauZ3llXO;N>*zb_qTXOEjHRP*=voHmeo&2ee$j{=?6VE+`dA^=|K1Q7%^;M0s z)_F95^kfiNJ#n5Z^|0?Z-UCb@b|O$u)Oz(6wl6T+)6dWQ4I7zm2?COx<^Y5<@`(tQ zR+NqReJie>O`tm)?_-zPz`I|qsoH)P5uqyauU*q7r0Pyyn)4|<$02dCjZx0%2N>(? z->_>BZun|CD0Ho=SR?y1<{-h%GB4p-zuyJC6$UQA&-w?-1%v^=v^lhp;*@0Jk&`%oWV;AC3IMh%+SL|h@%UYM; zmo@d%SnF)w8pR%C2Q#O=hU7c_nDGT4K=j93UyLX`S0cYHpP*%OHgTSaEBix>_S5y^ zOqy(DF+D17cLz3czG6*?AnWItieqz^gii;hb)i9>+bnyb19Q4z3PkCb&vnqfI89}z zRB^NpE9d^ceJ~lC1SL%!_2yU!W|Xng?)IWNE7DBiAEfx7ODeSlCSGkcpZ4m$8CpMZ zg?#Ynd}R;$yab{-&sojwLjOGHj_Lb>vL2iALxvsxbqHXe!pc3KsCt7FX)7eanOOjd z-y*ASoIvwvM26kQz3QXTo);ue=SjPsJx9rj(FJWI=ti;nMqSF1H>~kQINv^Fg8=g| z&p!RIKP3cBi8>IpxCLS5sA*ae|Af5bK8$|zW_h2-skj(SX|NVT_l1RFP|&yg1DIHa z$}f5HMG1;*!P8baGMWG zb97`;Y#DS)ZlMibh3dx@aVM+)L=0cokpE$a5;}a>Dm|w=>|EIo(WyL46F)-mW!gu+ z#9i;pD7)i{8v>^dcu_Ss`Gu&X1S@l!=hbv_wC(cosq{|up*3obk3MDcdaX3ly=(g$ z$;ZiQU+BNK+7;)oX=DV_D$hjMRW{ZI%30g^XSL-7(Oh8Vd$#^i5;f6oh#w*ki0TUd z{FPvs)O=r@6XCm~=eLl8YgH0F+c&dK4}s_~v-I4`+Np`t2T1zY*sSzO$In-G6MWfh z?*^uHs&8ho+vOd>RP4ob4k{U8Z-jXdA*;2;3E#MRbil4>D*m8-Q{KT>t9|63VZDr3 z;d8X$8VA>4?h?}xro7|!v8xeR58pUgDtYYl=Lc8kuVS3<)gMtl^iwW*2zy5b;w6wt z)V6FqD~U1tfFWD|Uhw(yhhLw6JhtcKBbgI>kH4RT5aGJxwy>-NDen`~8Q84vbLHHS zD2{hX+Db#?rhnSMO3AZ{UCzm;UqJgkKdS!JcbE%#d#~TmNsf65qlkzwJZ%}1c)6s- z)rvC`5=Vgp6WAP z_&`F)p5!Rl{k*E!oyn;dt9@Y{WOeX<0;~rMWrPrh9aMa9wKcNf>356Tr>Pl07J*0p zq{#VhAB`i}k_HPzXK} z3;Iv__TH+UKVEitgwY4!hnz2jg^c;ApxnbYngvL4Vvn(0^4rmnUqBfHZ*)cFmqE3N~M&9Y7JW|^rKq`!}Hv_9dOc{wibT*=*mWsJC@kwK%hiY zycD6<)XMmr?NYiW{$bxwNO*VQHsB~>vHp4tv`wzpUos>+z!Jw0#54dOVwFTlM6%$1 z9YuNg-tIy{R#r1Z?(H*YQ~m!7V$}>SRIE>U-d}%k=coRI3lhXU??Q|t+FNoXw)u@} zQ$JX;7SfFy5*DDlldAQuV#C<#c+N-v7J= zTeui)&@NHOAhPZF(;!yA%aooY{Nl#oB^wWsaK8Gak#aj6H_0eVNb)d}JO~qkIt1om zjuLhJ4_mc6a~VM;*2HMuovT&9N6=Km&le=((t2$%@wUm|w*Po3Gidl(dtQspMYzke zk6xaCVd`I}aU;YHO#@z4)M8z1H ziTS>arl=%FfNClmC97jP!bYC$Zl!T@fd*))Fky!6MA1rOu2a`@2WZzP8O1y)IGYxq z0}pAhUYX*-3Qx|gvq>ygNja&2>%=+*QhQlsQKFskRJ-4&3wr=%2WO`Q<|8F7Vh{1Cfu}l#0_z9tlkNRp*Oslm<&S`}kF1_yXBD8& z3qI;UorvbVF48Z4CK2!@P>n*S_~f(ESDdIItOFRV7+Et8%kbLBXs+bH1%A(q&svB^ z^)C99vmQ449pIBmS+6Df>!R&Wf+HQ&jV@hM&f*+2v;4NyI@R10v0Fc6j)3uG zART<`cltqNxHx0<`q2JUM(*pQFit*90a*lx=4Qg^7Aw`T@FI0d7+MrS`lQ3o*)^i9 zzx0|vaRuBTuTqPQPUp^OqN=~Y0W)ubLv8hOEP5s3yr?6P^SSf__=GjJ+R9A#MuEk# zf&P#a1`8E+kkG5J^|LK(As^cIqk`(XD^*+znN|a z8Y8^J5}KE+0KI{^YlhND2&=#+6MqG3?-bk&vJL6yX>2@-OO|k(>13Yo&7e5aZKzc3 z-&7xrM}TP>k4MwGQ^a8v?JTnsHX@Ei(K$d_T={aLqwKSQ(?Kg zMrzDi-aw21$_wpz>hXFR-}oM~j}zEHL`IX2Uq~I&wN{|`JYEG97^q?|5+X;3)?)Yb}G;oE2=z&FMQS* zHRx6ABV96qiza({fcD74Ugw}3f+|zW#}&n7(I{RcXho3Lx8bYMo*HYXFbt}eKijEo z5jO7x8`-W@WhIz%Vnx9Tvn;XZqZD+7M$VCbBhd!AT@5KHUHO)6i7VBrrGU3eGAsIi znCfGTiCx3BUa#*lZZ;mTAj!KfM%X^|VM>6?PMLVE2?j36`{%lynwFD`h85it@d-_FJ>+mEnE_~$^=40D=tc!t?5Ps@9FkA%#pU_>;%<2rzq^xlgK6qm|9F2%^%I%u^p^kA zRc}W!XM^GbtexPc!KEFhv@?RUipy^nm*1m2oHy8w=uIt^G}!+zI%{Wf`4D8)rcV23 z@ul)e)^@TDdIRt%Dt&OWYV!_v+x0bHX`S+prwZXRC7l(kHYF%#`+L%4t^HqrHWHny z!ZN+hNM)InQTMIP_Rm>6nfT7hm2<$qp58!uE>Y5XdiC7;xs+>6?~^gr6Lshoe?;-2 zOakZZw<4blRRMibb%l+-1&v2bY&`NMB)*JNzL_Esa=0O{6E0VrvWE8z;~pn95EoGO zR#cBpGuT%rn3wqA^;Ut`C8J}-V3qvFFmUfY+JOL=Q@zVgMVerGO)1dAf#KJtnoplP zMCnxz`ZgArsk{?nApqykShuRS#ZO5~5V33CI_xtV+w2Z(`wy3OR(EACGQYqsZoFhx zHJ!$HI>NH>HhQFYHtu@pixdBWT&I_KsPzYI-8F%W~DZ~dIJg6N8KhNei}7fen) z?p}EX)j--t9-M~j5APs(`~L@8-Ef&<1jOx|`{r-rXY6|D?jMpQQSuk0o7T@&0saDI z)c<+rLlV>bBk2q2`H_mwo0ksMcO6!NSh$>uID2OIbJb`w%jZQh4aH@vW>r^WFqcu5 z3MQ(^%A|#igQASDE?(Tp{rY*o07So{Cl*|!CzuvXrLJtDBTe0MM@{AiAUX6#q$<|2 zNSJ(v;BPj1$c?Ww< zL4^3G$O6K_;4B*(DV;*XKL zBx{(8sFj`LkTt!iq0u%8;urJUdM-KirrVvbVc5g!32|NhzZsQ zTI}Huy(m{#$^LGYL;}2H-RbBkThKxMti8z*-72`d99CL3^0VlJf`(EF3~4;;(+RFz zaj>M*$D&$DfehmW2q(A}@?D5cU4{PJ^h|ELpxKy|`H;0EoWRp$08wPaDr_yISpL_* z7{mpRv^C7uHHkV)h(y1k_LB%n)@f-Dv{?shIKV+A(B(cx?3EOC^VV*!G7v;{FA&}EU8 zeT&sMOg#dK|Ao&1803~41ZSSFUB0Q>OCDMiNl~OTMWK4^MLoseGNA^yiLAd$3g?z{KJ3=J zE$bMRUAvO2HiHC*6~$`L{-)sf?ReQ<%|<530K^K`+u_%s$xIL5$GdapJ98=X@LI;N zM5fR9Gmu)h&s*vHqW$8&+?HEFDsONMJb124=HHBo`BFq75z;ZOKOD(Gfos?r1U8ZQ ziRHler{QZ<;f_iRMa0mrPZ3sIf>wY+UQt$_w1IEx!e{?}S%(iK_;*?2vY1iml_-d9%_5BkChP1y93T5zJG5|JZs@L@mw zsnYHUDq~tO6>h)5CL}IB_q^cUhmr$5hx<5XD`hO5BPM zS7A?}=48g{5lu|Ds1`|_%7A9x{3Ld$7}=r#9e$do?rt_E+O5C%OndEn0_Tso(BH*7 z{M=4mwuu6y@1FMRNF?C4d`a}%HNhdS=`GEI+k@vSlmS+qTApKDk`ouf?u0`<=cl|a ziZ}7#e4@l=D3E2iqAXA-zNI(&N67b2irIQZ_9ca&)-^oLg#}W;5cyRiQM=N#8MtD8 z6x=OK3QOfuf31P8l$w(xvxL#wGemIzFDyM%rBHe@=S|pdd8k;3``_h)gl3-A{k@5S z+dj%X&&kko#ulblG7cY&{4BNv7RtjLSTQeE&R8?$e_MwMITW$`EU8bHxOxKvDr%52 zuqTBr_&0wc&WOYyxTl;ITDA!e%VM{4`#a%DrOLo?VSc%Kt-d} zF^?7}PQ4!VZS<~qq3V#EN>z7{&19!fO>?PW5+$l(R2x~XMak{kmTn8HmLQ%n$>=PJ z>8PcR_`GxCS=61)vI|kTPCX-GvbsrT2wdQ6)asX8E2I9T-W$n|$VM#V6gA`-H)!Oz z_WI|1=9Olpg0M+C1^%nzOdh({0xVot3&2iJi_C*Dj^V3jUgU;$=*Eh42wPB_d#W~9 zG-8uK(-@ZmSRx6Gi5sjC_APkML|W1IES|02#s?hp5hs(oD~z+Q1k5#VAjI`_@9tEr zcJyQxV{_jT@X;WE>Zq371zK6i4NNq z#PAroh%e8flJEy=gCeHj7Xw?64ydVLz=d^}=^)QTdN%m>ss zrokKbCrp*UzkYXUS*P)XHgyH}q6_@SN@aI=!XZ82%G%0DiAsURVs-PoW2 zxR6>Dow0r|Ll9@)*U3~59iGd}C$bp<-4o`N-RQN?j-uA)nJ;mQ`LrIn`50}UrCRSG zrT9TP(}Kh0)!r6#rfGEFQ6)@R(Mn^ZT^ewgB&Co24 z9g7zjNK4_~v|(qJn9!7jMx1d_T2vr~$2q(2T=3q-yhWeHQHf{3)SEtX4~;g+qq7$( z?=g?N(Lxfe{a8(*R9$Vtrj(<#8_L}6UUQ$tUvgNkM``mNoO%XHgSX1rf@&aIDB1Ie zIlR_!F*nPTD)>%}D!*A`#3d+7T`mL!1Vjl) zS6QNzfC8a~CJ`Zogc^|0Y=DKLR3#LVP6$W|fj|O^f+)Qtv=Hef5Tu0ALcXxyv(MRQ z>%QJU-}TNv$;<`UGv=7joO8@E?s1RWV;rkgasRJ(;<`RD2O6}xeAyH1j;_q~Wm~py zW%@C#g^JC29zKqYpX7!edy6j6Q?-fRVJ$kn$2(PB4|G~W5La>2v+5+=u@ENjYM#`z zS7$x%`tqdRh*3QBr6N8Nnxw>@hOAB`nDx-om+!F$XihmNc&5ve&>$5q!nEIul#Aux|4oDDLIleEJGxgvFhG1k<-Ljap*h5#Nm4+m+PBir7 zVgsMpvx=BDxn1g^C*bNL4oz0m!*2qc@;WZ!w+Ov9m^`1D;fb=>8dTbwWfoT(4S9&k zT;UmdJyd$gAWo0rt~gx4!J%C@N3~)pKKTysz#)%fLsq6&mnl2EY?aIoYP`E0Cm7QkD`WBt?dxUxV|%7c5j8dH1`qXf zRI9#MAym$%eO@n&(rWueSDSd&JeWJ@jxoNhyp36M_u3pWZ%_~8Q46><%1~2NQ`pI9 z*8p4w?_g`KAo9RgU5$IY5F$^MeW3k{A5}G86(*^(Dqtn*NBt38GkIBd_Km18JrH}Y z7Oa4asH!gA*YZSXH9C-VQ<%MeC3M}*sdHMIKVahsksYes6;?r3eULo0P>GphOMD;l zuDajsMx15@pM#e+XKshDHm9UzEp9d)`o`^s~T`;1ZpzZPmvmpjoZDV&s@DV3pb6LwYp(2csPfj61I z7@;O+jjMm*mQuA3gjwvnLRwvSdU|n}#uG;g zb?y2uSG`0d!60)(h55k{8jERecWI4O$FN+L?T# zJX`q$@5pZGGGj8v%{rq>#IZf7wol{Ckq)9AFMsaGPt?lqS2tUVtkh}V6?O}lkL%Y7 z8rn6_VDL+3Ta(zQMB5pP=|m#u(k?k4$GrO!-6?s#9;Rm$M|u` znX0D_Z8@}&%QH_cQXGSAWw+6ey?+cn&$2Ha5fx1sacr!!IPk(+%S&&2Xuuk(=9sQ! z#XqidYF`agqsertsheKSdnEJPF^{Ox(U&!eB55nQpJ%|HCuP>S_pyg<#@P$PioIe9 zj5BN_ii2MK+P03J>jLY!fI#K+VYivK@XFizioIygg6rm50xe6S1XXW}VvhTdZef6?_+QWrI z^u#}LRiABNPdSRN&s?LqzALq-%uQuF7Sh%sIB(CENy73ACy#T5Z}FKD-jX=MU#@g{ zIYWDj5m(hFj1_sE(3+R%($1-sBNL{BX+UPYxgr-~H>aEeFFYyLlXi`7tpsvQoz_FO zhF{1TdK;*nqg4icP$%}FZIpHxvdKV*QoSi;!N=XqiZ|SJTGNi=N`mRZ{(C2vx;|5~V-Rv(fr0vgpLk z0J!w<8e;p4yz?G>2~{cw($M!I_taE-Ha~|O>K=${T(7lyyR#y!MfcHC?urGEWMiYU z+dsj2I<-LSfkjt+Hp&S<7d0z)O#A7npX$Hg)Tf5AP7xlo?4#;<2wf(N7rNFQ+moMb zv95UoYur!p;A0pc{3M|#{g0HZ{%F-&9YeFw*4fRegWvrpqjpMlSKi0XuFJ)jEKn6x z2VG+C0|5hRTeCYadAb1#$c@18cat4qkE=)&tsx^`Hgn5=kRn-130*nG?r_S?VM%Oj zq;Efzv#w7uATS`Z^ockJ%$!8N{kH~m5|STN+&Ca+{&ykO!5>J zUrW^Me#}4c>=%S8x}ePbLdxXBl5+rthWlJuje1l_w%AqN?TfHk7agx-v}BEQ+%&@q z<}5uRUTEJJB@2kTI12944*-nivHPgi$U|zO37W6w6!>_Y%L(M$O<8n!YA?` zf!tnSuSSa4P7Y8Ni*4I1+W!g_G?nriCcwUJesrT(ZW6$<4;LI`iBF$4@Bi$Iw~RIObS4%**NhKyEZu%-(Yvz+_TQHD1b@mWS?Y1dw3viAc&>WbyrqtFk;sUx zKwm=apv59;TG@YG))7-5w0aChO<1D@RG7pUz6F3QcZOl+ZlZ2m4O>Fm9Jp>Y~Y1#IAV{emCf4$QqS?P(qf zt6Y1dsJOK>pt;l;isNM6ob7khwrCb#xrzErV)a~WCfYjf^nC-gRz@5P?bDmH4em%z z=KL**>VhCS5l1Q;k7>C_i3gAcIZTfjvX56|sN=i9%%yt^!_|!KkM%QOyw)R=19pz; zbt~&_y67xDlk)%k$IY2%Qn9@%9N#j=>zuCA)l6BPvyOV#Z;Em8J{yh8N5h)cnUT}= zhBT7?;PTo0IkuO!`HEKfNG3+#DKOb_t01U**_c@+%)z$Thwk5*emEsoTpvck_;+es z1P@VGS!P$R3TSPg7e`K9Lv=!&a+QZK##d=y<;MFL{riXc@%;ZjIsJ(Mx#OB2)D9rA zs?DhpqOI4j;+Q`b0K<_1;P2Ng3sskrUtxWZS{F5bpkDMLs5{Ujk^1Xu0D+XUyUVZ9 z29CUL-xsZ7e7wH7lmYSJeV(A!n)%DcR5%S_9Ed{R?|TAHRnY;*-ke_g*5SUf?F;h; zlrWdWH1mf~*mJoEaDB^I@XowtI#k4vXBP*GP8k?v)ktK{aAaQdmZq-5BVtMHt0 zCPz7Rbo=FM0-8Y{4wWbsPG8Np>n#qG8JaajO{eJP*=>kxp zbmx^L>RbLQJ>XL)y=C}jMjmH#TaP{){vn+wTbeKxEIjvV(J_}+>`~daKjXc6$XfVn za&z1C;<YTOYv7J+7S;(*>ZGrLBfLS6>o3It@pm0lT88~>s#W4( zNu_dEJyrbEz%VHVP)$t){xv2hrm8KcpX(1frxsLadC<3yzpE%!R_9go9&E5}>2vre z;L)FJqR}Tasogu8kEUM<9b2hNcf+8c4$awPzWQ(uH?KLV^Wv8>)buz!p6k1C*SwfV z0otp%C`yp*T&CB0Vc3I>4&=C(^)2wiJ1Q&ujYJhKHnk%8GJjxbn&T3qdG;jCZ)LuD zwiS~y*V;#gXw7zXY`$e&fi06*;cYkUmQ!)V_JHXGT6jblYX?Bn9G4A^Lk0?ZW;1 z0SE3u1ih6S%1?X)2=G_UqSjB4yj&6xbn@ZByyM=GLO6c@<9M~u=cG^DxzF*RQ!5)C_~(~HRAt94S=u=?!#jjrvgT*4G_m- z_jeCO;?P$p1!)yVS8BDbueb(@`Zg`0q$FVwhPvdgnCMIc@Z#p5Isp`3_54wl%RRgQ+++CnHA_^ur&n6e$cl}po)Y{!GZm}u;c1yMpugoUu4CGDH=(!4P@1xz3w>{JH@dz8O=+YNSqa8fnR$-$2g8l&-h8TY)D*i^{b53xS}bmxWXYSM|I%A) zW9I+J_(5YUHK#|m9+}>rhH6FGyWt=EZrAgl5!g38bZ)o!?rxx(`yXmuNb-uvZeTX-RO>sWRRzy~ z1-zw}xIx=}yU|+aX1HLU4I~CaK1u&s@nfW9WhA()9pxP7SXm!+YDh-CC-NfHlgyN9 zwxHjJbst`i`~w^fb0BKb8trJ^;ZPl(w%j&3+<0aPV6z|8t6fgEZl&@(mUsd-SI+QZ5@$ChN)kFr|-_zis=tK&Ec>Ti>`E-n%QoD);8)_tIXg3$g})dlb~S zs^lsa7Ax6mG62Vj=acb+r(Y^{kgedKvEUG%NoTm-WulivY8W~sobP&|KKVr%o%|g| zhFU9SO%E5%2PMz>DDqY-rX#f@#hR+DUId^0M_~A$6Z+qu7ul-uzNaf!IWov2-s%(R zZXD3F0bpyIIt4p*GYEQO?Q|OdO4SDPMIE6Rj>D?m3mQ58bm1wqXT+u7Mx_L4VOIItkOnucOm%pdHPHSXb zgFH%8)lH9Kh4p1xd+d{0-wj*;(k_Nh@=*yl)Od~iB4H|>b0x#^qFN6zA4+`B18{rt z&ttw%GK|UwP((z6w@%8Ws7VHIFaPK96$U%W>5xap)*It82A?!eZrc(Jr$)tw$EMA>Wrm}6!vnvx zh9+|Lg}jG4y!!g!lKg0|dDi=c(B-r%c;w3a?$kjZAHs zJL5fwZNVSx|uAqfQ3vlIQ;0MEkbwn2;1>%}4W zXD_=Kr`;9Z|LtrsQ0TX*UCsoUi8-bhA*zpAYCF-%FN{7N1@}$EwE^p)w+|8XWJbK5 zL>JYLP%g;6R3v%Te5CmCP>kPLN%x}FM~=`@0N0+EooammdXt-0{j}AOYMa4u2wXeG z>P1JA=!&B-pgHWQLIIF=Aple4a~Q2$#2dwMQ@zN=r2 z1Id$dVn#`Ye1yn79z930)spQVTGV^;r8ljCOP^HAu&iQoxBRR?$wR>w;czGwbds3< zx#%IBT^q!$IQpi!4d+4B&ToDNAM~m`Q59ZIfAyzRJPD#mc1^cd5~7o_V3YknaMq2r(bhfErE;IrYXv+wM1%XzPg zf<1qNqF;<+X|9rY^z!oNeT<4U&zY;@jBOKn5?O$OZ=K6M>wy zinCV4pHK%qtOmB&DkwHcTf#KF(X1Jt=-z=q4_yRxg0W=Hyr0Xwwk`sWSs5AbMJ0#^ z^|Y^4x2H}Hw~p}&>lLaYkAp?6z3!<={A`10hkp94Qr{p%}EG0|K}pI*Rlpc zr9kX@WA5wf*U(puUuRJdlC6Npj8aw>7k^uH6caB3K8z9Wm-xH3^`ua zNKdg94LpGkhhTgla4!c;1};Y);8I1-a)Zx%40s#%qw%-r`081$gx-uy3PC zcF}WuL1RhYiBw>RMciRp6ziKGYB9({&?l)Jlpy-Zf>S!FlhWxUm0|+9_M;^@regs* zO%09O5(TKe2sX?#Al&r8@HoE(Ews4SHJi0GDwc;4|HHjALS}V?yyP@_(c^h#^4F5W z7$UxKKSlFe&++4?qdnbUhvW}<)3>B!BEtRlm*&47MP(m;L=#hsJquZ>4q(|)Cq$e2 z0uz(RH-muEr_(Y(8!e5&g^wt`F$|P_Gx3hpWN2=!qF(-_1wVhoWHEZxTf!<3Ux$|& zp^vbOm*tvndwWQm0voaDXYAi*0-JaN(SCW-`|QVR&BcEJ7XemLaH7aiBvyhtYlcv1sqsLDRrhDv4WHPjWb~%0&f+>2j%de%k@OkQ7bR7f-bS6ATN~blrGh=i z2wZ~DnCzhtuRt2I(QDuVI`B<%&Y!+VnWlZoL+}I1E+4(8qrXXv^*zYAuas*wQiti* zNPAo>*Nd(Xob=u|AAL;5L%itNF%mfsvH`+cm?0dqh+54T6o>QJkV;|PaX{TR8 ze*X|m6fBi{%l+Bj>Fz;Cy<*$LajCie2n&H0hsvV&9}2V8cp+F)s#{0ausmUK;E}a8 z)!5ia+|ZPj8;tH38(v%nessAE3N*9B@U7diTI#f15eM3@Ibdp|jUNmYW7p==*#Y|r za_6X49necFMGnrxkux4)>S56azkXO<@uxw62dVjjK__A07q6 zRvboIYEhBF1O14XrPg=Hi)o)l$4fM#?VGJEoXMD1aOx}YO^Cio)kqxjQ!_h#Ef8df zvH*W53S~a|f?PoyIv+eu_&&a2b=M8kSY2paLsvb`sp5EB7N+#8VdVjZCRq`37pXrjtgy5u&8BIY;LE z;;h*!4=OMi^8`y4hvW_KpwUr^%#(p2al&2l=@I_DGl*;iA76@7nOqIuqMheH)5S@( zagU_(t^N|vxu;=3Hj;iB%MuUsk`1|(Ov&Z_50)bII@j=ckD-PQm+dL+yKDb))Y(Gx zNf~n;5m?G9NwhW30Yu}qokXRYp^=(9cDzt}`w%K2@&OR=sbk>Ug#nNIOC;AP$zaV)k z8dzh2+;9AXp3C;1KAbhF>g(H#we7$8;zz*RZ7d~*mMU@t{#9;X%q+BQU z0}jTu@al|x_=xFuP&Q6*3=p^1?#o5^5VTA2+SpR^V0Vk?r?L{6IA)P6zH&@{1hkI; zJgOYm{JQq;m_N_PizM+_{2^gxU`&$W1%>Llm4Zy&V$Fj4D{~i&61+9@5nEn;uRTva z`96M^&Pe#}ChAOZpF7nb_7r~rWQ_5I@*O+dOIGBC86Uzk-ebq}Tye+$tg1fTv3HPL zqipIjW`E@*5>l3=-uy@_E~)Wbp_%&AySy80^0)-b$7V4i)}or5y|QS%(H=H||2waT z)L4Ku}7{cQ&E!`XK#a*@vH z5wO}RYmjFG|NfiM7uufya;EkXfqem=>Y)3xaQJ9`>8e63Me{8A_%ryq6a$3D4lG@1 zSZ$k;=Y3ODA2-Wb>iqCUw#4PD&zEkIG?pL>ED~!h<)s-VG>nw=Z!bt{(TNr~JHxOs zyrdAUG~HXoyrw;F#W)oPwFK~{tYB&*EvhxYR5^^A$ll2RttIlohySM1+lbEM9Qi$H zmt5(i;Om7kc9~*%{QM*(me8TK{-d5AfM+p8;L+pxdpw6Svtk>q7L&`c=*YHPg%f1I z?drNB{V#>CSHhJ`2g5B^y!ei%H29$#Yo+UkQ5cz0L9;?WHN3=iQi;|5?9=;7GCId> z(K6g3=PsBsfKldaIo!c0FOwIK+$N`_!# z22Y=1=v2z_24nH>6Cc+gPhVLGJl&kVzDeczJuVtbHfwUb81?@U%`aac^}*r|GooGQX3(hvg%t$zw9HCXh{+qXXc#BDjq9idN+>SIe{yJWsNF$y>8j?JuV88+X?YhOyv- zPRQ_JsUnkR3iwNLEY07`xaod<2!1pN<&ncb+P$nv%MgX?&j6m9A}zfE z45OHjFCeKQfm8x4Jt=7s0TD##HGrdH`hq*OvKvX}wPjqWX|^_gnM}`n$B3yy&{ z?`zyhY+bSaA~9M`vfg@Twvb0gi}71|8Z#KuPb;_u@ye0!>tuqo>0tzQo_y(-dm$Ej zSAGc}?(T&TV@eAl6&cypxtVHAYF;u}(s&ZZ{D!#&*C7|Z^LS9&YM}}3aTu*7@KzrH z-5i-X?xj8{vJZEv5l3A|ob#1P&Mq#(uoPy1r#;<&8V%=YH}@uSmNCA$E2#oNz4>GcJn*}PW>^;c4wx&OMKwPNn$&_}u z+_!f~=sw)fxjI%la4^IVh6r>@$bilT8^6KVCdibI_8m&VaG~qDuGKA9$G9%1)#*{6FR+K8IeS z#wO!pOnt@V- za}L&mXpdT!KkE*!hjc=)1*80QC9cx-j*h?^0p$zs6$7uRX zHxY-j*7VD697<2EnJ}kwJ9v$GBAFbZYpXLg2jrl)(WN@S|GlY5{=wT*7^p9r}u z{O5OCnNhX(Vul;5o9wabWi$*H=YdS14GawJ@{c}Pa%oG~3S{f5?lBSkpX77^ z#lGUdlhfTYL;snajz-i$mt!zn$}>P$LhM_AJ;>>bysa~hZweW1M} z!stfJn>C%hn9QF2JV)KVx8A5gxXK%Q4A0LDLkaS}k_g{kdc3HhpfFxaC#hZZp1wEn zIPVeX;*J#IghIqTN))SZ}|hFfG2TeQ6(-phG-DV8$_)ug}o@_+NQ^xVml z!n4sY>q`XNb#FA4LPrUa&jkX_>;?T+tAX=$k)&}gm*{&d81YllOU)nT#s1F;{t%0X z{usv@tc7AN1v!kQ>8O4N|K4j!tjjFvCkfYJxLeFoN_-u2lUw^P%$u&ll!CR*va#^-&A{b zc?aHn_Ipy2NwElU?%LbRah~-vy(+%#j zY~J+m?neIJqb@||Og#YNkdFVV0*%pJrfY`$?a}Dh-vs5ffGKykkh2rTM4`9C} zobE}Lg=6oTl)I9@!u_t9vraq^)wB8 zaJrEr>{Y;7N7g9087YsxqNW(Z2Y;8i1pG+a+aH1PW55jWtWpLqN{&^LqiX$pjt|+r zKg1RE>IJQvob^!vp|q|YJ@LjoeTP!&X}{;n%A=hJ3`0WcuzPQx@*F#J0rUQThQY#% zSrp{c0iw1~(fttflD@u2nkvj?8mO#^ZI2OYO!K?W&aq>>givb_+YVnn?+r zt?4WplJ&^u7X&s$L~po6SzvMeo_=&O2UNk;N7n})5Qo2SV+D2yoyhZ)9ePt!84SiP z@^HQ%PSrUSorE)Q*Xft1@Nx(2iR_j_b~E+5I*mAJ|1aUp&IOL8E#io{o_$V!soqVB z?nOgmk2wzU=eK%J$yONhnN}ti;*HF&I0?UJsLrq+GM57{C zAp312d=eB*hNIJ*5-$EhI))W`6LQ?f=bh%@_pi+*Nwb}h@sCpS=ArGaxK z>r?JiPRd;ap;0rFnT%2{8zq7J@c-31kL70b3|u!L6P^{6CIOqm*wdZr6rM|b<39=~ z_FLDU_d8oNbw^5i`keHPAgCNZiLH^C(z(2Z_D;z>5OhaM zeRgdnmfW!hs|PfUy2Z`h46G|fs@;xj49lC&s5XIY&t~{;8j7%R`u?+eDX>kdUMG8+ z^bTW?pPF&}e~pLR(R}yku}vf0P6b1&M`iIXH~*%uZZ%9 zzP8wlHGU%N8VyZ~i@{09Id$WV|9TGYCy7M_V);+(rH4Ez9g?N(z=m6lcOH-lan%A> z{_r%7-hEtWa(C@albd6wgS8k~d0WBo8m-a4$E>~c;Z<`4NoIQs;)>t4MdYMSX>UGs z#C$MERVr0)e7eH@OCy0E>oDJl0EJ8CblKUDQTbKluz$a`JggF|?(`BmfQ%uP-_cg( z+mfkum2SarZI(K8s&8Hpz7ATJl9O}+3JZJn8cKxB>=n^L4c&JfBxe=mT=|0m9N|6r zG|b_M_oXm#dCAkJvG{m?L4kvax^4LL>35vn>=mcmqaMKUDHfOWOwhj*F$A0VaCb1E zS;xO0Domf!W8ZX5f-lv2n;P%y7T#aft2#r#5V(uNSlUMs+o+7nwvBLUgB@4l}eI314n)HT|Lxrf}DNUqBPx3iNO z4`6T0Tbu&9lr-H3D^_XK9J4^(O+O-QJ84j@-`p*!&&|vUyF?4Qbs1v}SbMyM9KXiy zO=}!7X>y9YLt#+)c21lh*!gpza$Ck>z1RGpGRS=f7C2i?Lhe}EFyA8xKePz-7xEo% z?ig6d(g*iZ`W~i2Q@8IJ#NU~wu66hO@88NX@aUj!oqtpJ_khMC%q~K;%8j1(%N^4b z+x^Jrumk-`KG~@0ZwJdeg5EP)_pqG7s1QMAEj%K7?1io2@>yrW8_%#yiXS6@cu}cC z`$A{ev;8N!qUJbk+W2OpILm!u@CC4LeoeMsNe1Cq#kb9OuzY9a{4t=q*uJ#{If8&% zMj7H^?M3%pJ$Wv8egSVTtydtMqv*N*P79&!0K(XOcID8s3?pl0N?nUGU6REvl_=#p zwO+F2?J+^&^_JtxL6)vK2i(x40R4HUBzC8bPZEp`+Tss=m2{5)rR@*6b7y(f`C0pR zBWDgP(9z3w6`;Ss2=u`OGIP&%seJO)@mX+1eYlYA+?j&hq6&NX-(hFpIs>`@F2S|g zbJKf@NbKMO8}n-aj45kdLnyzPu8A~%>@DcmuUSUW=a+CR09HkDZ$(zlFHGkC_OqV? z92F8gCvoQIrR1LBYma-pm+Lne1x?~x2*)wd3u8ld!in|kpD=@=aSr}JK5i8j6x^a+ zS@cZT-nl{zrDQU{I!Ri<;qZ#7p%b2$l~g37O_%pNK;{l&kLdU64#KD|VAwrRp?1@! zW!Vn{wRiIZ*Z(T)+QK_vwe;+i(IPn(jI?*W^}0r1md5n~F0B%pW34O5k5Avul`Spa zs60~y*ixo-uVXTL^J^G`EJFRPq@M2Ip{c?1gK_>Hiy1wsw~b=17z;~KDn@9wc`TL9 zfl!Kj_hJ0(6E|+r=fxp?Ge>PZ=;UgPzV*ydoU)aTwt+BpMJt_4hra5wrcYhVZR7%G zJu6I=0juUZTcdEz>RWu)7y4e@j^79GsV{|Tv|k{jd85l5JRMw! zxLv(;s7NJ3vf_R_S-qq7`ncJ4QAXIZ#-wi+YHdDial{{+5zb|&;F8}O<)(tN`sU^w zpFqcM>@ZZa@77k6i8k8U1zJxoNf!+r8ei(0)bSE8R09~dXu zv&t2TT&QInyDV%AcW+(&>`XQ>PVe@9ZV8Pj`OuI>3i4Bu*<6pkviSBBS>{CE({P-l zMVMbim{zWx8sJtwXEj)}64n?TKxJ)huEYsg351qdhxwNwGOe(wvw^emi+ZI=RWAeT z8D^Wae=r*x6iQf))o?HNUou{@){Pt z3&xWqCbs_0PbFQoYucmIO3)Yeg$|r5-QOFExoSm@dbo1di50&X z(rM|-Pr5Th36(VBJF!ru^jV(Xi1DewVpj%k@rlmwQ3HY|QGV0yJ^BLL?-vZ>dbxM6 z>aOv@R22g0eKN z|MpeYd)G#8Ah&qH2gDRx4CO^~9Rd-TrUvJx%je6C0i=-Ea6ZW92&0z4WxqiR!9m9&bp?QF?ROxb|-S%bZ-dbGbYjc|(geHjo!;{;hu@ z>FT$rsli2uWgLoK!eem&Ts(^Y^?N-AB1_8)T*x3S6D)e0Z-D@~Z?=Ycx4!UO0sj4} zceVM{fu=73;@S6N$#zl$SL3(5N1cR?n2nQz(CkP%nvsG6#PhEJk@GZ7G%eiXuiC~) zfj%!rH7HJx?Jc$w8s2T$hGrESGKZp>qaNcFH5yxV{R55(lNdaI6+TR83UUgJ zi!P4#*-E|2Hx4@H&~OED@7U~avGWGur=Tx`Ml9i*o%%Y#2Si0WUt9-Wu*<E>*aU*MhBuX8G^ zw6^5awI6&hem>jPs4gB=R9tZTeBsatWo8L_1oyKsA36R==iWV#?VZ>4PSm00uz$C? zu5KkB)0aE+{$jyvg-HI8jJ}8);|#~l)BJq#*>?_IX*plHe7BbncSD&`Qmdm;7p97{ zF3lkP_*6POyi)((#pw^6=YTJJjS@IJo1X#uV2cN;p4^A{AqKA-sJ`zgnNgw#pAmhi ze*@UYcy#-k&^qWmEV`KAHTuqJBbjH6j4h$f@u%hGKRo6-ce-+4V_cZ^ zmjBQ?z3}bMO$Ro*um~5Q*f$?s(pTDS)+w+y*S*>>e3Xh@3qt)!7&eeJj(@z@jn2p~ z>5+iS0i2)l`Z zt13~mDR}nZT(4X5xjr&^?&FqZ7d1TODhLEZ*BpRK=~ z=PZ2HEw^wr9jf8iOhrg% zu;ust#v0}L^%m8rsMbBXfUEeOMOV~x4h^zuM$O@Z&CKg%WCT)(??g@O|Befb z2Q39m&yZxpva&bT#y#an$Y#pbH@r%cP+}pu?FyTE?9oX%!onwXCG9(&UN8bA-t9su zDxeF`RFsQ`Ya14RleU}YB&+B&yGK2eBdY54cAu%J?3T#c%RFYAYulp-GBxjnM_19V zFMR%2jqZN`05CLORwT;RG(brzWI&Idc&{u*0gnOs+&m^IFflHGZ?^aR}%3rnHbh$?k2a&4Z9w&$CDMEo4)MliJNtnf^k28$k# z5$J>oq!${jR261vj@H(b8$frZv{YODMe`Tl_goOkXR~JWYNtxA?$3#$^2gAcxZw1? z+#6L4$ExL9!HOfVN8H$b@n7s@%>%5|2Xv_{U2PG-ng|3?r<#w!W9|?h2|pK=N(Y?F zUY@&Jswgn_&Pzy4DdcqsN%{&OJ~hU3PjZggba-ASZ4*q~{D$5b$0zWBhob53Z(c7| zoE9`v`b!cWY#)CPcSEcbt?d zli}>YYn%((H>r!r_792Crj&*75C@C)YA08-P_QtSh{>q)31-`0O^Gw1gi zmh*)i@jm}0hR7K2{W!qWSa0Ygk+w80E-VqSckH~7*rptoU#RKsk4UFk_}um)t%FpM z5UT|)B`#ZiTw8n3*ic)m&ufw$??$vmbG)$)cM1k?7LPNl$m)BC3U1gSqW87fu{0#c zWA9@#TRaioyX*(Nb8{knQ>h!l{!2CvJI$P~*Tj7hFvlJ8SCfL99#aNbn+&M^C2B=KY*zRKd;+Ym?010e!339U#1O zr(UC`o^zzJfYqhfqhq~LY#M-b+*(p+zGRUBi`(cg10V?ZR3%Nc6vrCn@Vc4mPr_xVdHg`9;CaSv=gKyG}zSOkT8$Q>-GF? zf?O-0p%n41!A4S7&6lO&lg2Z>JF8Wu=`5mQIFT*HuaGRShq^7ipl7EwA6{q5`DTqI zuR|(3X5hGHTl`!^huSLs#`CrMwP{Vadu5i)GKuP+f5O$@m2R%iX6uG-(r0LGeUTg^ z`9uliBL-pN98;i}Oys~q>B;Jrf3Q6qbwJ9*DoYK8fz}Y6fQ9Fp+dmsc*;nSeIr$wY zWSuFbLU22$aKu(2iQyZ=U}sA8R{XGLmke_9wpQ6}f+5I)Iph^;rd;CjMScHVWlBl? zirqq2+j;w?qA>qnn}vY>CC!~@I+Z=wD05CP{mf@=98l8&NG>aa)-Q4O{?y$45hW$o za)w#aWzQcLg7Cdf#EW&Ra9oj<5l^s#EEbl*Ukt0^$NIb;w?Yv&ew^KpoP)|Dyz6hg z{KlLZ=Xj(ixXXy1+>x;hj~NcVNP0eSTJn!IuAPJqp?VCV#wTxzz(T#eg=*XJhk7`> z1Qp83E-^bzPOFy2#*d}5am_4h9glsj35US= ziwelLn+te|Ah3eD{Q3L0lA?S1SlgCfVry{X71mw{-^oX)h0zMtd;94h3JHv@{W@$D zFNfgCj{lFf_l|06``SjafQkkzD45XBktPTzkkAC-s328Z==IPEA@p8FK#_oS>AeL) zXbBwzGzdzEgx-7T5PG>e?|0w(z2DDs?_YP1j1l%4JA<|6Tzl_1pZUx=$=}*Dir1Pk zMas?xrYEs(XPXX0@U?^7vwsk!|Kk8gCq!5vl}(M7iLZh*8M%zqVIrBD1C;7$+WJOw z#^S6Y{zk9Bdt(uTnQlRZr*tTSHDu=gG}kkmAD?CGPEiQBTd1;fEp07-<=(}u&dZV#+cd2Fl z;@RYIw$+?0AvO*-)p2-X`hmheGrKx z7((uFXsgw@G+q%s{|5yvbGtcc*{dpH)2j;i`;#SQr9`%#86{g^MgI7IXoqt0mB5*{ z8Km-F6^*>JHTyGRw{KJGeS^Q6-kQQFG}dZ0r!>`vEL|HMKg@uv_6 zQyhUBjm8QEsdtOs2!l)=gAQnyT&DilbPlt9d92#yjR9vD22FjLk%5e|K( zvfjgl7s3AjH;CwX<{?_q7@u@@ZPUgwkNvvu7BR$gZgQmXJ5f<6$dG5Knp*ynM(i!X zQd_ZlAeikGFdpD%dUy)L4BlyHd#oU__@RJS$7Fq2kLV!E~(zT^Ji+ijK zHk=l6tSl^@=UnsmDxlxxA`bC3J(Qz`vn$Zfa&8^8)C3|#D0jgXYFX8+c*BlLXtyF> zS1+VOyK_V>D?Xtxdz$$gJ!=Vtkx~RBmhxA#Q}sq_X=~#z2w zJxA`l38Hg~$F2Q|UPbQfZrHaEFp+?B7JeZjp)kj!`5W*}NzgZ->mDgl_sU1`XWigP z|1*tty(>PuT|%N$Oa|*)bykj%RHy+!w6w&WHSY?38D2h9p++nu^qB8SUx~HHz274HH%zh8Edee3l)H?fhPTD z%{59f^vk0bZzR+*Q!5|~27y;Pu6c6Kfl`d9hN=DTakkQ0`UQ&Zbv1ANk<%MW3s)8A zR{H zg8TiCsMl!u>S{B%rV)GPt8I=NB@Em@TGK&1zN|l&Vu8FIa$e4!&Q5!wsQ5l$cbD@@ zOHfBx;GJjEw^_j4^8C#LYoKE|fhOjLCH%H14+Z6%!_ph|RDffq(uJ}rAfKOQA#S_F zTjk_-g5Z?;Y{e*)9ZB<_2~sK8m3yeI@oeIUzfctSy8-4 z@XydcI)76lE8pz@kIpHIUtT5({-ZmJ0{>Of|KsAKxe{4(z*jUs#dTGmD}kM&f6B`n z^%Cp+j54)om8V$`{+Ky#nX>6Vo+0o*wqu#p#qn2`Ln0ECG^(tQwp?w3#YC8y_(1Sj z=ydScn7Er)@`BYydU>8|bOQs-w2%J1u6w4GLcRNNT*PKbm*}a!9v>S+yoMZbh_m31 zk+b48xtql$R$967H;k4=Xmh!OoBIwe%pGrEGuR!YwYSiyt__-8w2S}h_$aoH%cN+l zIfmhI-;%M8PI<7zo)cztf&o`3z80=+SII2Y602%r8Lm5;uLhCEQah;rRbzOxzC@xoZ8x0UH(FKVc0{naO<>}C z#79bjEnF$#>SG^|BhVe;a`U_0+Gb3P+38g4$rX^2*e*b}lo1Kj#n$V0zq9iV0m}!P zqqo1@QP-Z0oAzb${E2(|FLRfgHPptw^*N4nIOM?T5XXZ8KY9EAyAaBjWn~ z2k(oK%}NdvmWE}cSGDm>dZc&X%$U|QuAloyKlsgf`DaH?-{dMIP`erhRzHn_MYxV; z>XQW=8XiO7B~8ytv`cFVqP_Za*3Ll$wV=0G)X(7uzA{fxK{!B>q!%#~03 zM%&>L&&+0$nKa9~^s60YQ^(v6I=}RKh+JzrB3`RT!)V0|tnPjqiF!nbD;GcO= z*<1-iwqtA9!_w;CQOh^S7-Lfw!vEi*T5r530VzcSj5yGR5^C z5?4-L-_hBr&-aM26&9gADUg?4{uV)TgY7WZQ5IJ>#H2V-Mv0lxV0ZS3+K zf$(j&t{pym6+LAYaq~3UQ-JX*&WUQc#!uypMA;zgS~c4Di@%BDuVDp6;{~E%i_9e8i2R|8Flyv$KXqgnoX9-;Owx0cNcn;&BQGqr*fDx z{NSzfCwzMTLGm14HltXM-C*Z>2>iCF5}Bdv z%XuVk?2C+uX!YoR&a=Us9s%Gm;=Kel+G)%E$!>Xmqj%$Eva~u(So}cq`LMz@|1&q1 z29-Kf9fPCy#-3|o`pk+k(T{;8Es~R&=5#M~&ca8h$Nv-Vq*#jz{o3l4r8gJq>}{pr zA8#ke(QTx_onu~;uAouKu){!Gh9kgz&bP5G!}%2j1}=xywT7>VhrN}EI|=H`!Hsw( zVz&Lgu3xka=uCB{&DdM?pnKrU^2p}CzMV^mF^O${DjAN`Hv`6v#t4k#3;Ey;#-hy+ zCNN#|8>aQTmB#0F#;N;Fye{Mbjc!37WlgSgtt%eQM%*kC#*M%)?WIYX9>$F?i(CH& zNX?4Dr!Zsq3)s}<_94&2 zLJQ69m%e6W(|l*uP)PX-=*?d#vrfRupI)m5^@^~BMsx_@1G||j7};W*$#1vpEZ$-I zA70IW95w;{>bgYgH@kqUz5q4~;&$d^9q;g`#qRLz-wLJbgg4TkSFN|dS5nNUJpdM| z!gw{PWJh-RjY~B(*N5h69Cfu`ea8}GD1bY8JbA$&@#Z5Pi1AzEEQlJV!d#An1Sm6} z0yq{pK;J%PL{TkSb5jZgpnsNn%UTv!gr9fO@fr7z=RE{~2H)H-HbQaU%tr}vCuPg7 zzSwgFtT(6CxhWR8cbz0l?oR3JV--Jfn-t2!KJ6g|(=xmHy<6eFr@EQ5={_*Wp3?IM z0_<#5PyhT#ae<&hkjJFwhy2_a5N}87R0|%{S307sx&<@~WzukG=`v!kT_iSUAzPYpp=b|HnCS^pC#={zF!jQ-fw#SzXbNnx|U@&>(*u?d)Q? zArw#HJr!)f`KM2NofTCPtu^WdYW+Nm9t@0WA6W%a%i(N>Jp09gE82#0eOSZ-qTn6y zkLK;|fLQK_E=YztMHFFk-O*MY%dd}|Ts9Pco+tV$NdaGdeeIw|k zF<*yO(%`~KJ8y{XLhYW1xT5?mUfaG(2h!Y0rCLvUH7VkXyJCr^Ht8qZ;BJrq+e&Ss z9XW!u*XbU%JpZiGVCHcBja9lfbdlqJ@dZvEEVyNVY&)iY!UNtl=`7_NSOROmRBB%S z_#3H#;_Zii1&=Rk76;igcO&2BA<)Vz74#A-(LLeh{m!aMgZTc~PvLuMwrP7m-rc2^ z6KeWH)UElcswjz!~n(zNug~UR;dR(#mCYRtaFjA70MyB%qPzqG~8V z_^08fHxl`BSfGuWI$+{B1o9axd+H}0#EeosCbB)#$MjAOwI-NSeSKicSX8q1QZH{1 z{w-t_HvfjYb9MJ^IvV|3%<#>@fj1R=A|Chvt;X+>QxJQrG$HMn%WkWKF6L9390>v|MSnh0 zfTFs#7TNw~3w^4BPPb(Xq^DGB+zwM?f#uyFl8f?B(B^eSR%NNY*F)b-Nq*HUG9tqV zn>*T7`3jH^Ey2dncZL$y%_*pNW$n{yD7=z@C-$k49I^|lyL04%qAhZ6W9X?)z^-`| zVAiE6e;9jRNrQ)Ps>>KL3V-@kLd$2p z;{E*7a4SYHO!@Nei)aJZ?jKAkja>~;w-hMo40qOBpL}OML1>>U%a(1o(OqdgZs670 z-__G+QM>|_SV~?=Cbyg=pLe|CH)vEI(kpiDfUHjXhyqxgO5_k8RWu%(hSq9@V3&ZR zj~P$m73qmh*O*I3M?6+1YBzADWN<1V^6hr1vye|<#jog5E0 zb=?c8m%j_L*CEf3A2I#}M&WYajCh4?iuqI++7u%2cyz3$s;C4h&$rr&eAm)3?Wifv zV6HqMX)h9cz1hAM*Cll0(F{#=Ss+&43ZU3nPdU+i?i(`4;z5Mi+Z4CkbD zIFE@#@T*QuURE(p-_I{ZYVf&-Wt?fiX&F`yGSewZU+y2&T zZe1M(yhcxjw4g_G$J4>$8d3UgKTq{HDHKzo?KvfA`SDBsFJ~TIQj4}}4FkAQ8RP%q z(fqeuhB=%zz8~!JK2;ASzP8GCv=h1o;?Y`uBp4L^SIVvZx-%ok;e&xu8NwzAdo2uN z^YqXng5mhVgck35&mUR>iSS9BYxLNI&`wL?lqU3~Z|!2nr>TVPDbZg)^uLoR=E5~0 z3a|Hwj8nH6i>mtAi~VGJ%_%~%%E8yh&!y~1iwTvDTQRtK4Q^=}2XxI1jepaB4ivA^ zV(UTo$5b#vYuiIs32Rr&pk1w^RU&b@4#4LYsle4c4pMMGUj>pi%rf3bGa~ckjTae2ERE;=*iwCEkc*b?fBtfMs+?mSUJm zj`@M4!Aoz3V(+7?D&D)+$DT)*yS%pz8;1@!S;m`lhXjVwek`63MwZ5Aod37f{`a>* ztn2MpjTHne{=qlroOSh=6#l`4#LQHkiIRHY5X0Utx%C$H+co7piZ91f#vg=u+P9%` z{PpnN$iB~CYuIB!7PJI)4dz9#^z-%oO6d}o!!KBlxtHG{0efG=0=I!@Ti@?K`^?hCQ*D z^~lu`TJEXHD1?s9q@>5nKuNr^AaZD7se~P+y_~ zbolNg{PfN9OsnK>v8@J7Qm;y!UWean$lv)TnJjtXvMz!15VkVHaBdpqeN;kOcCoK} zE+c{JRWs`R)=I2XDDRQV(phjn{7Fw~{WX2U$$sOeRfL=ka#%x!P@5?NjwGw2QD z)I^mU0dMjY3>Ilt15#h=AV*34zK29%qjuO-T0q{&X18`%!CTwOV_~d|ZDnz)XbiM# zr|9^39K$W`sM4-Y1G+i@RP+(_eTGd(#gN97G=D(yZ?dGaadJ9JQ|EzQp~jQH>9Yxd zxoE>5gc=xD+A|2mUuL@x!9#oXlWL3zQmma!b7M9}h1l{#TT{cYoGCwRHiI)~;6ajS z_BaAU>G5?9(0GDk-fVf2vPugC2CrO#?VYaL3j^kZchq4=TcxCB00q6^0^K`)FwLIc zK6=Vh4mr{t>;|(l*uQO5g_7h-cBYgUZyv&m<;0X7WFwC1d|4w5+uSu~+wLZ|`W= z{o_n5g$I5G;+zG8U17Vuk8Xi{CTH1uxPrn0hitBbsLDE=V?{j9o%N_!pRZj9yg9GA zg}0mEy5#M#@Ym3j!|DeXc-S6|fh*eXCt~1U&-v?OXE`I>S)Quo+VyzcEN9i(HZr^p zIRr79P;XsxM(bf^C<$$QNBw%JNpu*{2-iPXbwc-2WV5ZOs&tJ;>ae+4^TI3)Hk>I1 zcKpf;6mhh66P$F6Eq%H- ze$RoHfhnCBmeS9MN(b8c9*WR@08R;!l6_xNJ4c)8yabK1Ka-bEg`LeG5%gYQ`0dO1 zE#kMk>R#J27IuWx(%?dzd=To^~0(JGr&B7VIQ=z*<%^YHT>JDe}?sFncfg=~*&>@;1b($}up^Xe-8p}-5B zN}t#}3SXg)Vk9#c|H-eVLgq`ZcWji4vX@XyF*piL_gY=j*LoCx>$p_)#rAXZ$h)L2 zoVdSYBYvU)!&0Vss`=FLAe2kmBYpC4572nh2%*ulPi%lAVe$P6aM0wP3veTY0u)0D#B#bSd-kDk>Y#DzG}sR@rHRvKT6+4#>8O zL!-6e5YnVK=W>Z^p5LJDqrZM4Z-jdny4VWd&s!|!f>~C^qrlKk?6COnAX8>up3#^+ zkGTf5O65*hh3ay1q{O=kx~$98PE~_&0KBRInF7ywh7Z$6-hg6cYetf%jA4{G1SoP@ zcWk^?6r(^yx|8mZcS5ykBb1EBJSWg`4e}jhyCqD^sURnNyJ~sN_6uv`DxZ!q?}9Y3 zlbU`dp3y;lB-Lc42>aOYEEP1=T-z)?BBXM>q_a2L%9~Uwzw+7KA2kt%!1Oa9F8`i# z-kVO{k)Ss>_e7)VF(D-QX7&8b{38nr@Wq^pTy$y~IQ2JcsFyVU@{>(4P4&dD!~$u7 z6iOGf`r^oGev!~5A&42h=Frd6!Ho;y_`P(hv zpU|N27V$>sRaTfE5FcRu{#3GFld5(e z&}lkN!gP$~`oDn1_SF4C0;;P(>jhr#xgVuYe{k^)!BVhCjz#whpK?5TXg=;L?YY{D z-*92K?OFwIe~cJ&lUMP&co|ZwhP22^E{dj*7@s;2S>`ar5`C5cxbGaI3QtIW2ajo% z>cqI3Q4NPho(-RV!?BYbOZZ220id=N{{8`$jKp8%3>I8ej=PUWaqrS~O)2b0Cg zRo=B$jVIjvV;eN&u|n-}8P3MHgsgVI{E&kHlbbF|Revwo*=|7q8}Ldt+m7%EJRL9U zZzZUz8gZ?&81 zz2Dzw{N3_azNsR2fZ&fk>c0l%mF6I$r|0Uu)v8S3hd^A&uD*gxevgL0(z`mMu}As- zFf6g=#^EQPG*wtnqx%q+X!Jy(bHO=T%3QTY8b63w0OKFHl9Rn{g;GqsVr`DV5aR=z z)SG50bvcyM#QcNFZ@FyrcpfvM@3e(Nb};strEQU}Swma*;^VuX_|AR$#h~JQ%&hVR z6Sv}A6)CZ9j3kXD|1lsz@ti?1lO{gvPJxt7V&I;^)eWzsu92SGRLXR%%iW$>E1=9F zd)4jg7XtQaoJ`}j9D1680q zJ3nkz%VB&xWw_-~+mtjGcx53tw?lu#_s#IJmolY)>S;{}W52dm$-u89m#P6($-;mO z_}(Xzi9tKYQP!?6&kRVsygOOT6bx84ZZz4`NQHS7>?AgZKX_UfkY#cD9Dlr>wJKM8 ziHiS+Kwm?}V_Ht?3A&*lO~~e~kQJ{Qx&33dc+4-m1#ZFR-7D_eY>zs+hXw=E^N24D zIH}vPXa0#WnZ=j<0tk!r?5xrJO)9W2NAW0lpsL2#cHm-_5un}N6gK*h{}U)2zi`N!&+j7<-0Ow=4ElOp%EcJ;vZIjB!8>_Tl`In#J6fA$*{o!Yj(>Qz1%kw z>g1-kG`kLa9w+w=id+fEzS-=J^cMZH{>x_NWNCTkAVqpTbLznDoQN2N$npE0YHRuC z?vMB}`kmq#77`|MK3Yx_u0Wf;07nkSX}*+Hd?z-Ca=vu)7*V5QkVaC zG3vjrdwP2nXdb)XNZshfwKq2V1;tVPwdO1qfIGq{GrvJg=8&%$SJ{-eJ}u~1<*fK8 zvDCTN@TQ5~m|~uWV!?n=3_*uj*x*~l@wloqOVpUr+|pN9C#D2o2&*_z&6*;HRPMr? zK0f3)B239R2sHCIFJ?_e4d11zx>Zcx<+d@yE3Tr<+72dU_#Db;I$rn?4Nm70_$ZBAm&$KLt#lvMW+K^ zos3M^cvt;1-6t=sC0xfHcpYZ1=Py&S2%QUcrEVFi80>^EJ|T|<8?V0Dw_@=)tX-{s zjfzs4^(w!C7&qH(_IQ|X`n!}2kggLlA8y9iv6qnnRq6wnvBlAy68ak;&EY30QMt!Q zF(%xj@2`ZQ(5P^>p9{|VmF{Q)+MuAbQ<1`^#r1PmBWGv-c3U5X8r8X~^TtzpihDEos>@(ICtUjDcecV(kJPk%w3R7iLGsQ>xy&^_V9Nt-p4(N@a zI(j*S&mM4F1s71-5MQP2u1}?B9r*x%IWP2|4f=eY zTqWjd3YXgLe#sV)R(61DYW`8=Qi)%(Bl5yHiz>tWIRbx=X5b#!!d_ByK?PY+hbOI& zQ4UH{7sGWNCD)Jg;$zTt8_PDoN+Bm?4lVp-Sp3UP%M4NgUHHjS>lW2Yypz*=&2Pe5 z!HG!{7<&;F&%jfqaeLx5$nA`B*U`S-W2EYp{ZhJ0@L+Qz)z{v0(;)hX*|;_*h!v@* zJvVHu%gx0;GP@eX^_;A8u93Z|dbe`i(iFRI@tKvbr%XdHy+%_-i@D20BL z_s(RzVW7^(ErfHb#p)XTZqPK(DXFQ{*d%9VQKoKGDzby%#1zxuIu+{s!cIlntia^*cHB5{SiB~BTxz4`ng z+)Cw`oo+c_2=g2g*>8E~u=jy8x z*W0)4O|N3I8Lv{`%)b7E%zODy&-*tyFJI20{`}zj`}ceAtGe>ny1h2o3Zy7C4!B0_ zlhV!_OfVhYsp36eoolH{BV8T=;$HZCUID)QOGs8>6CtjWLFRA1$ZcquF;g4e{@XuC zUr~zA@*t$JZP)yZf(hvu?xlvJp_?1TPd7Qd?!~8Ug=ABeO&q44@BRYlFJG%huH;;j z^wX1P@hn40_;3A-nDTsGIZ?kruN2VtuHuC7o%(OJjr%V7k~(4qP0|@c115M|n?C-P zZ|wPPwzH-3oLptqyoJKAL5v%Z_qAIDe+V*Uv$RGOBa6o${M2Gm?VL}Ds7ZEI&Wo~+ z@w4xrM7O3$M@C~+-;1tEjv)jRHM@TnnYlGi`di{wiG$YO%GKNRN=~K{;UsUNow@dw zx@YjYYfgv`#3NpAeiKU)E%(jf)t$> zdzu`;7z~k-Y)~As6(3`P7VOY$8wGnGby#!4<|X}fL0S*!T5+-_O;Bcu{noPbXpQy$ zIW13wTH~;OPAcQ;zjJ8oAasXZK})l>b(h9X8-0%;g|j5_mRXK{=Fpt9@!>wB{6TYR=qb~j zf#@)h_zUV7_fLRoSnE&}#2$GWtFAk=UM+5Hm?U~*ho(9iF&FAN@JJ=9R%@zBr%f-pY}VP?KB*Apq`@!#QGCo% zxkYE{fd#bp?|K0+{>~#g8%p116dDb8KcmXzE5=}=C{{4vm_uLoYq+?`KdYGdu{F~+ zM?xP(#J~q~+B@Koe~QRwN_s5`pJC_V#S%XMqAe0+T9y?;Tohz4BF*OsLoVOJXST_*6}C_Ywg1&gUNJ;RPDR%&$X9;t!^ zOMZ}O-UZKn5&OVQ=B~Xo=lTI+3)3*k`Rc?li$qbK5R^g!a>P@V4~grNvq@{LeG(Rb zwHBSko}o2c#H3@uveTn9)n|?db=dkzW2;ovY4MVA`?l-Ow*~e&?lC|2(#lr+zCvmA zWS_ma}W`kwzLZPlHe{x{Q$GPtS=d)heS<(>hy zVTFAKx*i<;H+#q<AU1c{?N3xi=U2J$|9-V16 zmEBep))?iDv3?hhZHoC&YVCWpGs|A$^k=2RePhr8V(uFZ@+u`9XmC%biJZEHs0eTg z(uqY4!&1?G+rhjI8x0fBxELSbdS-A>n=7F*p<`R6VIueP0D+5SrhIo8+`UuKHq;lL z?dC${-Dt5Laei(2``)FDxRyS>lcE(3_^VPw>mD)x5iUuhKKx2`%sijL5%I@c=oQ?| zxkAX47TKgWYs$vpDXr+A%w)D}u{qC}Nbjv;#lOu}Iv8-X!X_Scc;~*uszN8H-Mz8>;rzVSzV{Ojv?dC_igO0AI{vxAX=NAvvhij3pkW0iNf z4QYjX4*%3WDw(vdx0{wPEFlQ!*REE>-z6|rO>xs1r7SQDpu&yxpNP2v6ZnrWgBQ#OBf#@TRF2aVg`U*PFY8Dw`y-A!?Q(MO)Y zjxTy($Q%^8{}@c4QtC6_`s;U#g))O)y@q)^7qbzWyDzX#z7SBhiXE|zUlDq&g7``J z(S_GR$5FUdPdnKi4eZ99<CHn;^@2?SZ)R$Yo|e@4K{Z~d2Ra|^SY@JGoI!_9mk%$bBG)tX(?=(>cbh!Jn`#ns!I&V+RUOgZ$xI?|!>Heh6FV%Hplk|Hi zq#Sceba~6!#+P??Elnk4#qW_ykwX@LcjDhb8fHRX9-t}BEi+5YAG4V5w>8D<7u(oV z1@2TU@=f}v!*0rfuj~(PHAzYO$fUKKz?ci;8;A5#F#G&-6$#)a%@6wZ5=&%<3 z)-raOVUHf;_+ZD`VKLYAJ?4Y`%A5$XbzdS#{S{L#3$iiLH*MZu?!K zh{`z;t|C|aG|vjqEnG|lnPcu}Ws|R$!tG&;_NDh(X^xeQ`>|S}rqjTS7+`L>j-V z(BSXSJliF$+Luh>e0lR{XO_>4f;?!bssP1+&54pQwxep=t_|}z%!E$;h6grZB^hNr zAwcoyA$Bvd8GXTm-3b_8^7sZ75-6nKXon+iu^J?2|C0gmA4gq616KBphz^4cZ`zv* zA*VoXyprV`skyNG_6DlLN02kH9b<@L!Ii$2OWD zJWwWtX}yhLmW}+YMs;C|rwYU>9I;1ZUadY{bGwIsbvTL_#GR6g|Yx~j!d}@!9D?Jb?eEZ2qn=2r}I73Rl={b3LB}`&BCqvuBxamKZNjX)U z*@=nUrHyfpiE)JCASEF0E}tYB*pF&)Jv}c@zTspsPtwB|L(-)VFvSq9``3)6<_h+s z4zRM{C+(N3#ntl+F|Ps~0!4>)W|~wT_0mhgonG1@zf5zyP6#}k)Zq7(u=uMVIq!vL zLgBo(@zO1X@>}F8e+JhqJml*+d_6OzQE|o<@7QQHIx2Pw zvsg%SJrzSmr1%2%x8Y9Vg<6MtG0CTUO?cfSGx7va&Du`uNwAZsj*9pfN+H??iXHh? z$hfY*TtVloi&s}OE*0mmW-I3Ho8x{p;8JGgp4wDjBI$jbsuto=hd?h0Bb|@$X4QUJ zi6jl$aCT@$v7Qwf(f_8NK!-mBUqdYxu387vHmR3^QQ^f~u-J@G#Y_2@Yt5i~qPJ5% z&W2{qus>hZrcQ_nEWh#c`v`BVY=A;arjVm*6IhjOs>$$KsM_Cz`Y|wPgVcrRat27 z^|kG%w6S#_cNNHF#q7>rWMl?&~t~!({p*P z-;K90ALUqCILAes9NHA?WtVkggcEpNQ|Qip8xtBvJXX;37Yb}i zHJTrFfC``t;;#!y72!$a%y;#TX3^RhPdOLkS``e7b7JI#iw+cP^)GA;D*ZUYNe1m` z@HRSzl1*xCXRhWYYLtf4!j9HBmyK^BBo0Y5uuq$UswH^0aJWX7Xd!*-o@whUeuVd{ z!h)&zBgdC@d5gE1+aW%w>=LQzFV)auwd>mF6XOk)yI|QuVs14AbQ#iOdiG0zfr=(j zwZbV~8-Cq5Pq|BGC|7j~364?IG`|sWtZqvQVu5GP+$zD_P1V za;NPas$lQ9a%yM*(KE0XCY={{B87S+cYq)Z*^j*PEdMjtIaW5VniDT36;^)?VMJ=sM#aa|G9+HV(1*o1F<`-6-vffhf4C4N3;hkf z87K^6tgMnr19TIjuOLo-2vP9U42rAxlu|-Q0km-y|RrHICy%q7Y8dLa`7p6El?u-_kRy{Qr$1$QHbTQO4Rz! zKPo)p5ZqXTL`{W~DV)HzX7x{*iU@{RZc5h^H#na=J9bbykdkK`-!*+|w~GU`d&dAA zd^Gaw5F$+$2w2W^3BO*S*o5YwoYPk^tUT8t%z`sTOF)&*G$y=LqrpnuC$=OoH&f8V zNFz+6LKQ#KCY)z?lk)t38w)A**TP`;b|7=9IxJk&&^3kK9W~ESe9C!QtWiz}R#*W(nNNbuD#jivlL6 zBJfrOTZtZ11Coy|#m2Ye&O{wvfzwP7IwMvX$_$mD5Lt(9#?8Kni#4%rE-3K6I-^J- z>;h+XUaH#jsv4f-`=aO%M8h4R&yODLRAzSKEG{}Fx9`zOVoi?XOF5RzbYW|l(ZCaa zT|(gm4nr4uc%GA7U&mgQD7WrgWtSqk*Lx=N%Wa zZxNw7+KW2WXCeYL zN>r&tYgqljw7gSRn}QR~_h{&X%hlgNP)#7{ZPh3)AZAt(PXK!16YGuTV!CJw+U63N zV}(myfwer^%wc&3wAv|afo(^gazX^u;g|13Dk^waqRH@=5vzIVknQqvlr82=V34)# zTJ>1Q-%p3eiUTnH*pSAioFU>H(&>HuN~^S7b}B>NBRMrValUG?t9b9=wV4m7(KrkP zI={?c88evcMoRdJGD+!bD?QKKIG;GEGHtVi+uO$}3z8om*|N9}>pPoyff^^*B>g+YsZM}VJXAr^Hdq2j8=cB ze-`Z&U{95%W`H$5BYe}e^%q4eC=$P*dXk*(+2@nLb0L#c}tAL1w>BgM$nW1nbp@do5#*XsrkCuFA-cDqb*kprk@V#z! zZ~*r$_?#Z2OFKznXQI5=bFE0mN&TsW<|T1jIzE9;rmIP9t9T)Q-32izp`IkADppEN z@ozf{T<-vs;Fx+mVbH7|vUoljJjK)`@X#xru}PoFs}?m~Cu;1&dTugWi*u!(d0&tm zG*)eU-+X{lFU$FSM8hmk`&YeD)ae;-m)GvKI)sX9L56p2sDs15z;QCvKa^sueHCOa z8+itSSKoXp?mbq;PA@lcG{7vC@1F3-ONPUiE+PB?t-_7Q2GOX}x zp+*xv_PRH8xjuI0>q9hyh!l*md}pElkqYwJ#M@-+{sS-mH4>|E-IQ4Mz)!1rrJY&V zvKz&c+)?t(k`VtGRvId;bmY%LHMPB+^uIv~s1`*HV=15gsOlvjVo^afVf3B%EeTyo z0A{tY@4-(%ue+piVUF}xu7m%UEL?w|yUW;Lp@16oyKxg3Ij<1Ie@7OK7i7uB%K7Je zmpoI5AJyWVa11!WfrgRAr}${S0u4-RnH@^FS_8r0sIu{?_$=Z2nKxJXk2>?}nbc(Z zDVm%&qh5GHDV%b^$e6!jh#1Q(IsTWZ&o@tWo0t5|%wk1-$DG>pWcv>_wcA&y>ZHf^ z*!Ybnbyr!@Ci^jj!ie2)g&#r;5(HfInW2g#&>TS%6x5b19 z5t$&LL=zuH zY6auwVCg-Ji253Uv`bP z_(dC~ir~!1zMHssF>TH9=8sY4ty^UbTAOZBj1(i?Z{omj*jnBf3n*zcoA4)*mjtMqx;RRLGXV9I6qNV+*!LS3M!5)ePka)``zN&I| zF6d$RJv(FNe9VE^7Q9dRe10W;6_`je?Mm{q%9-9A&3r z){0cQoHHU*3R33B^4~b8f&0PYcHiB_YOmPgWHX7M#$IO)t(9lboe+Ljy?s|R^6b0p zxK<%<@6T65{u45#f(lN}4ot+*AVZMO0rL3ME21wfPB_Ffvd<~PS0O!OJGis0$cblT zfW>3GPBO?mw!|BkUiqxaBKAYIg4H!D9?2%iP|r{&6r?ygR&_3gHr%v-+JF4l3Ztl| zTOggp40Gf8v<|s{R(@|W#<5;h=A}nkX%3zA%a`FUZ86TPlIL=1lL!=Rz?wwk>4v0! z{hAZnXpvb`ROSkaZlJq99rZ`8M!Ss?-iy061M~Z~mpS-+U};ejePaNuEmy%+2!w?f zTKVXYGTVi4k%WS1RNs>^z`>Z`o1`L}Wp*}h1!Ry+_Op_|e>Lk0m4cyvx zzX!*}hm z-hj>b5;CPVpiIi{AY!w5mCvUd=Z9GLZoRucDwoqi|6D;negBT11_Zr z4imb!QJ$0_Cl#8W-zM#!oDXiu;#9JRsk{ufFV&VhS<96T#uvYJtLF{~j@BY;f7Zl} z);OVajam9B<*@(r=uO%&vlnd~8h$EbH>+6JMCnt-|F96*+B{;1Q$Hyjg;y$nI!IV^ zaVfc{(cLLN6jlk(E^}cp-f#6{>>0@|wJxShq!YN-?lP93Uu|kKr**}>t!pDaPlw-{ z*6FonG5c-%IJ!3=CC=AWg}zc+lJo3HP=6ia$XF8gZ8;5`4Znt6KzZ~APKw*Ak8hf7o>m!77)!Ep~cNKpsP z7XInrR9pr}wK~*EAb1T)G&X5=b(Cy;n1<|VZbfM#(8RkzL6;!h^2G(87@sI1_f#6= z37CEMiZA9@xflcUxQ-olgVtxU#z|SW?omtUuLSRz(fe$*u4xn|ap&jiYCN)NU{~;$ zP8(@y8HYWv+w1LH)q@uF`2FksF2!3Gm zCRgTM_*diS=Qhpkx7WJG^^`(j3~MRr8ImT|e!hm*jX9VmXahnkZP+N0XE_zc&b(p9 z>BaeXbAHk^B}aZCr@;O2tDsx&@HXlh3G3Z*=DmHyMk=!Q&p874ThsqmMT(M_%jos^ z`Ydqn>PyWbUlqePZKuP*2Sbrq!p)aO>M1-t#fQb#G2S&T4%&D?ofV3j+k8vIY^cT# zGr%SFfV%;tb9sOEvx_RE;~?~cDHb4jZDu-GqrBCvLIG<*?V`ajiu|;f?1@wsd;7S= zdo6NoSQ%`|3H`*Gc$9HYa@lNnFZoYK%GN=oGlMQJRHS0!0m1$4@f-2&Ep5rI_ zYiMV|rON6||Nf~yoG3~hdGs&t;pl5))gj%v_sYSjYS|FuY8uSrJ2lAaFxkIhoUyq< zb9T)X^v^fx@X+a$kpHqtAyo{R0>J0n&x57#8h&!S;U^JGnhgk7U(!{7N=}I7H2V(_ z9NQ`9lp}-b_=cEU?W9FffjHZhpikY~?_Eodb*lMeGSkR4;|5Vw>cE2Tdwl#QDx^rZ&w?!ey#9%hBk zBUd>S=_uU?jtG1b3E1yJGmCf=Z)T@!MGnDsZL(BiHGHVc%)b1GO}={kL&<~NauG~f z)Hfd#;&8bCi?{ELYO3wpv^;={fIb$KY6S!VDWO*j2pEd=8WE(0gbvbGP*j?9=}meG zEukhz5v2DP2nYy)1PCnw5|T`O-uL}x);F`(%&%GN1hUQwNjPWkeeZqkeP7paIfe!Q ze`>$x|0>}=PKxiXQU4BT7>X^OSD1SN8K2iyzdKv?uF8l9?KA5Di(q?a&`H%an6!6Q z7n&5Q3?& zX-0afCoP#4%XTts{xb^zDj@lm-Je~GVGNd3;=eU|xj7{)NAU$4r1O@E z;I{VuL%gx268ax92FA&zF|KEBzFCZRX<9dfeFGCr`wzJT2KyhThX2b+2A9KsUh(|E zJj}M^gO7G=RuY47;oD>hn)|(*;mx^iK08-~E3@uH{fijtGna+(1_TVCTQ%89q3mV^ zLwL@`JgoiP-evoQVSFB-k?H)SZ@1dIdZpICyY+0lDV?i-?!J>Ts=oN`otul%Bm}%n z9I8yvlGQ@Ij|FZ|r{+C#yL_3H#O9Vj``;({85cxI)5hqG410~nf!XZ^Z4^NLsj(K| zg;t3+LI4FjGArR{deMQZnFxL5S{i&|keG0y^3q4*GNS9OsHUx5y3wt{^8&^YIWA2l zQ$hBPehHB?7-s70yEXmLZ8`Qm;Y&|+8KAXg)%HP1cN6{5)rb zNaFRI{|6^wgyr`$eut0KrQ#)0$yGDw>PoaxCMbaI2}Hx+?w7ZLXaNe-rfX2f-;bUf z=}gyanE|eZ!!=NMhSmkI2n>F-2q=7g9%UT4>=D*$Fzb{!qY~NC?xp)2UtOG-v=(s}mL{b~|qAC_}LXD+r zAxmtpVm(ti3ekoaI#IGa$ixfC*0z*A@kOpacX=B*sZh>+;zqmULWQZ8SDY{*@J%<1 z+Fi-fD%%e2c|geVYf-C)2k_0#OM0$5?gw*TdN|+U;NT!-O6Y0jvOD8x?3)f_1tY<2 zzC+W8O@zN*S1`_^Pfy_0?My%7k$xS}hxm1G~OJv%|pye!?I}cRBNT|Do9-`_brlkco@d+4mbljJzg46v%4(Zqkc_J z{%MoTznh~?a$2Q~I)R3BajH#}5>?r9v00XO>Eo$&ZAoD-IL^sNN-nFy98oj6yAQxq6CK*mdpn zk%85r1GVmoKYzS-EaCf!5GK|FRpR*bzJM1rNXtKOkl8iIPBl6nVpVWqYuY|g>j4Pm zcNg8BjNZHXXI3H~u=Y5M`y4>Ky%+_I?UzE#R0n80p@=A$d@|8GGmV+)e2W(4YA}pz zFlu&U|B(waZL;S1$=1D0O5*jpJT7Y7Bg_65XY>T7#C!H>$*_m-Kza1TpFM{dq70)9 zYRlg+IU_Upe^#v);?FYpTc4Pz7!`k_Ou_{9?cF7{==Nd*z=G>fz?u9H2a2|nLesb{ ze$xxdX>325AfxKjcRqrpZoXWu8z5bW`;;9B0HW`{I#oYIqq@`O^qW)F+&X8UtxhT= zF$hiH={tvGC2q-_) zcwvKTpABv7OvNlGZkk4B~TxR%nt^x%0bV_@w&4;EPvi~s_N{4 zR7pVRkLCLXMla;8M`TmId_%g4M$6(inFskGN9&(W53I?M>;rT4J&KA!$nOm#x5`;4-T!H zHV;C_`em<{*dPJk8!8GL-=v5o&Wgo?o6dR^(R$|?T1aE#XN(i=BdD$G_tO{>A82slW7mU z)1Vuc`58N}DmYEDMA=sbZq9ov*4IET69$+)Zcj2N`G)OWjmh)4z)^|2!9*d6%phI`fL5uu8B z3i1ItJ;vZqhNh-?uce4Zj2ezQ>`STZ@b=ptO&>N^SN8C6;OhYCS#+LC1HP@aGWteI9z8Xc*}JZ#npz z$)A*X&zju|PUdHkc6rbSnRBxmSD>tuksUQ#Dh3Uc72ezox3d4;?J-fTP$g;XUEum^ z>Bf0(rlbU1+q&6|;ldd~5+2xhXYZS}eFoBW>;X;LvVPyXK7 zo6TT6NwnuIwJWf<)adTYjcYs`aqM&l^NY-kK7Fy14QR7&h=vY*Uv&0%K(8x`saGo{ z}W;_$NU9?XzrJ_wHvZIep`!4bn;r7}sPW zubr`tDIT14zP;75cYpjNhBQusi)JX73b?$ECGr3FJ8mJ!|JbPGfeX)^Pw6gKQ9wCx zK}PqAWzVp>Xc`ee6pLO zr9NSmaIT~2gJ71>UT*bdCv_uDMhPf?OJit3q;FyXBRC5ttgUBJJ=OSw@>faQ$YH5eWIrt z;}q5lTh|p6YK`B?j#*pA@@K+Iby>3fb5XC`X=s1Qei7evnN;^SqENCFsNp?!j!% z>|KxOVygX2W|3kIkg*K1`-6U==kQLrJ$0|3ihyH>U;;{BSh~K?fl{KzOH?YB&R{)^ z(k}#m;r7cz?fjrl$d)MGY;{IX-VfDtQ`)Pdkq#{_4EOC~A#xE=JoZjv$~k{NZ;kZN z7GW{^gL~pr0PyDYYd!{b+>A#2I>1abYtK4(_ajxh68gqPrgC^L#bFJlNEk-y4Nj3= zXSD;fP9+seg`|wy$Sow+YX=6s27Tu;8s%baAg=1$1?0Z_dauI|uKs!|@^rJogGme7 zGa2j|O~!9Akob4nDD8+hSKhlxZO*y0?;!ebgx!FQHVT&L8?8)Tj+Ngq)qeQHU}C`u zB)`XiS4S>ldYgB4G8#3z{mOV)-a4ulf5$UtbugOz6N~o2Ee-V1T+H}%SX}p&H(`{7 z4^Ye7A|Qde*so%`1sCA{Zt$tzwCvX>_wzYIqF)n zvz>TzPJfttN_Q-AeW*;Lz7};nRJ5NNTs9Wi;!#luOs&Lnd!diwBLI7)!HGo-F9f}V zy>C?nvIH%jTu}*W-kKq#C>)MnM<-_Iz?8^!g?hb+ed3m0%(zX8axU=5gS`7_2>R+o zLq&J&z;!8yXF*6nwm}Vq!L64upX-n}NL^O->4@t{oUPMlO@ThAH?`q50c$JiDwU7K zgY^4qRKrVCi$(Z@o|^_051GK7fvPKLhy6pacR!nB;>xrzl5hP!CJPD%`<}K>9sJ_?A;;6eW8KK#OlE5zt^z_sAGKVzr`Crw*)t;00$0=-b$uc#Th zY>>~8tqg$@vJ<9h`($RL^&Wl2hUUqjA3qbk)dqyfAu7f&LlKPfhEds^Rt#?H-(SB= zz^~5?A)MJ2Up@0-ibAv<8P*c*7XO`^7Ii0+E;Y)e!?%Ssw+cb zF==|5#E!-{GOy+e$=m6~tuWAd)pLH4a#&I=bVOdzI%fg75>)84DPI?+8ks0%bIHk2 z0)kNQ!M5d>9uwdL73yH6(q51(+Q^1m3rUjGJWz5Ei6a-w}0L$QoRGPYDnh2mR)bxQ3ouwLM-i|}15+L-4@L=0vy z0?C*Gr0FN2N^$m2S`Ot`4QaV5X7v^AyYxvA@wz;4t5MLW8HG|oWl>w-s^7FOI#tPN zHAX*b5;!+wA?TXE!R=8-XNDw(yIpY;>+vc(=<3#qNr#x8Ib97sBVWnx>KgPVZ|7dj zQDOZ|j-%`^p5SH+a3XB5jNXuGR8Ln)b0-Vd&E8FMB7kX@fmVSDzQ?0XXz1vjp0BSn zMm{e4bEo6R(EApTsgB*8M7Ja*z7azDb4sF_Ier6MfOvBArSKmLJ)>j|q&xm@)30}| zk}2Z&2o6zE@@*++69OGCNJhU(S>G+&noPf|bE|wzsy@Uz#o9L&71Dhlav!cE0twpm zYue3Y^=^Bgg6EW)l2M$557D$i$n8_s?u%1IJQklBsNi=TKk-=;I{bsvDu=aoClG0{ z4aXHM;Ab8AD(+qK8(qs3a3Va?n~>egC@>ySxiGtXsP#O-1jR@aju)r)-|O*}J>rG(FUywI3V>}j7L zqA5Mp@Q8 z%+n^UPE@r>%O&7Zs~qt(I+RY06ldWnp$CjodFnT@mM1VHh-_6=O0G!nt`a5=(nR5^ zBT(MeRRr)Fs}rasR)wl@{2GmacxOr(R_I^>wN_2a$Bs{qeu^Gzi%*r1h0T|w9W26@b-d95Krbsx%?)L~Cz-|bTU)#Zm; zt)|LvV>|ZV0GuG)J=`8OA=DIp{Kq(^0rC&5w2yr#+clG-n^b0(?l6^n{$og%48%)y zGRrU9e4=0zYI*lMFIdghTT(E$W*ypVtQ- z1DZBeZ#8W=6iqUL@*|r=JwvM?p^mec{hG(-kquN03UHt0`QUko` zxDTyIWjvG}Hm}FJ)fFx5eo=Ox8-Gzbu+MFsy%Z%r&zQAuq}cPPFUd2$&Nvh3plo(P zwz@PkteWqzyMmf0n6OFH)L4b}-0w?KUw0 ze+h_{9_HICYxEs^r?}~i#ekAhRfJk+XK@itS1K|1uy02{!ap_%{?g6(;0BG$LS!<7WqxxQpn3}XN2g^rlzoSx^R zRn_~Uu>OL8ZMkM_R`bjzCHc_*2+?1ZPhPb8?iel!3d41{AtKK)E>lnvMuei67b1vW zV0`-Q;b-dLygwFYlJTgX==J=)brS{ruu+*qjZ;nz9xRlVx z!Mwy7*%=sbXv%2vo^wZIB8KuVhRo*_7SfBO+G)R~;)nW_|HDeEl$Mc(_0a`x4-1pb15G!Q;;nOV%AP!tt zA7}r}8&gP%HR(fU8l6F?-*!}G=!Xy8TgZ=a(VTGpeKEpiLr}F+YYaA=H8qz*CD2qi z=?9Jgnj=Rsfk}0wYq=0SQCZ})vep5Au`DENxd7^$GAYYd7nasS!K&Il+>bRZE7}Lg zq<24O_Zk`Z4E6VYxDpBR#$2}y!u*`Ul|$rI4ZUH_raLZzWiOux|L716Gg@^l)oxd~pBg>bye)>rDjrZGy$L@U-6Z+wU7SiG zK9uGkU52Y0LHwMgTaOL38sga-o~lyD&MWWD8Imb(mE+ZllRu{e2FN=}O;q02$9)X; z!{c|ZA&Q#;omihA(XA68{!kmbza7FRofu9#E^}Ku+(G_srPo!`_h*{+kk6?)&+{k6 ztcw{4zw5-S#rTOGkQ*_jrJ|9|rI9O`(a6E z%K))f1%0#w=Q_TC z&oE}vHVo*Ieqb|C{^Op{W_hHiMP{pwN4f4qk$D5)A>IKX>T)kbLHX4HQqNhvBa%FF zrQR8OvxrxZ8XvQT5cwJk(^EjZN0CNMzdb{<|p0jQP_SEBUk$p z(%Z-eu37OvF0@6gt1oWM89-W5a^53!qi9%p{T`s`~a9%WRQ)rmI587 zRH_s=DHl#`QN5F}PIog{o3ztCEyJ!>1X_AsJ&Kn#>-gY0OJJ?v^!mFOSn$VN5(!{m z#=<5#S-#b&=Yv1sPuf;`!DcblbzaE?BKzX zy&=m!D-3Vt=3_tA-X?ME?sfSIa5DkdapZo1**5HZ^{3d)4`z|!l-Co+I0^4Bv|XvJmkP5Iy^0qXCon^b%tV4WriSaswmCF#f(@7!J(-IWk@UitY5?#?iLGn0ZV zB3>3#7h)C!z!x#T;!p0`E%!uaeM9jpH95VWsdBsg#W!6C!61W%eF8GQO$bgrYsWH$ z+-|UONgA`e=kaG?t4Uh#(Sh9K2>y`Q?(*LJ(f2dwg>@W$MG!HTVxxS@6;~HRKMkT* zfK2>MtN~ck-u_D9)n0~b;?TnJ?MyRMRGY(Wl^HS6s(@vS7NZh8ZNI5t>lggXE(IT> zI5;Kd-&2`gqDl{r`y9$r1BuO+C11wu_Lrsk6Jqx#hWKD%0-NQ$nlZzqWzuMyV5oKL z(HKCX92Q5Xse13xQ6&#c!laSq;Mln*%iXaHrG4QX))htEVUHL9lv5*rzvK3>`tF?) zk6gZ1Y5;Y6iavS_j87cL9WVxO6HnhfO=%nvL$3h6KJey<%^jT_RQVbbYB5jS8M-zvbtc!sD73zJ@ z=+*!aBVFPCskx)Op(1tf5jzYAc=o?K03)-5+b#PuuycFvl7QAn#5NU;_YA6?>Z$tQ zmy8RP_17Ok5KTSitiw-L4u4B0 zj6+phEt`*VFs`Ex79+1!IC_5(=CmFo=wiNb&mxZ(?&M)ZfW_mcn2dw+tEacMFI(xZ zUV(~NyF=CFTtu`0hOx$-d0K#( zPeDeIXrNoJ%+u!sFQPLaJcMgJw~bpBzyGwcjSCq}$de(6+tmKMw%M`oV^lV^%yC(1 zyYO`HEnOI1lXKzQ6k>(#`7#f3M^}B9*%`YN7M~p;3 zfi200!Ar7Xvz{oX;b8d4QEe0A{?HgNx-cE4PC<%)tfSSc4^*8+JMP*82dzjmc7a$Q z?^((^S^?+J*u}!ReLZ(>>brrmT7Fm5#B{YC!1ox6CVU*ivG`e+#qJZ~heNV!F;m(s zZ|XOAnnbe`^h1O<{l7Qn1cloC3lCvHeCL{7r8>W{Lx1>ZY~5%nr7e}%`v)p zCzgwxsVd~x#Q~?~u-3ht)3Pu^7A5;Dy6k-Bs<66SVJUd!T-#2~L{PrIoA6H zHvU5xhR%bxirwu6ER&uRIR`L)?^;lR-6%G$>muAHN+b-EiGuWICCv4C!E`5>D?Bpa zCw5ZuEOUBZ3k-q@z5U1F(OPg{d8~tV;D&xGIkjoEUur*93O0HP9L4;Mf(Y@MQNc~j zJeoUisI0}3C_I%~Hb(N1*D?W{RJve${{~vrZ&)Lba5`zkcGdve5tew&>gEhL6}?^7 zb&vu!E;;$zZ>oR;RX9`Y=r*xJyl(2GZR~yq&$)zaKMK+v6&MHxXK_{Bu^fIUyIMT2 zZKJ{;l6C*5U&y`3|Kug{bsm#!O@~FW(h@=&xvO5a^kxNh8XDkC2`+R-*R6`PY)V*7 z4DQUnJQm{AKvKqgf4W#x70lhD2Ak+U$ej|Sc*gYhzcd1HJj#C5o2ACc$x2q55{RGz zUtCVDb2h7Y{wGrJLh>c~EDOrja~wuZy~k4gCf-?!j~ryrR6!OT!vsfj%^KmNlIN@x`G#$?(B|!Sli$SOKtp z7Wje_QC_q)a*(ooA9=jn_ajBHwa9sgKgET5bXCo7QU*I@7j~yaoR9Ggejapp{lQAG8NV9(DBv zklR4GrQoS`@v+#6al?>&|GT00;04&>$v;(m>3^%@=caN-vslX2@#xoFa<3KrYj#ah zFo5NLU(&zOV7t(i=QOXypfQFE?JWMuXFh>{IT0Cn@CqPTa;4yglS?9dahLJmOD-*+ zPZvtq-NkFXzcfj8iDsxnx&wARJmJ9;q3y4U*QC|p%K|@Pym`1d#U5^@=h27=t_edn ze6$ILv3t)req6}e=Wj{f_U^%|_Ru^?7qZg*XGnuyohVw|Cj3{-YhMiyhZ(l{-a<#W zmW<;pWYVmDwguY|RSzET68PKaa9X9bq+~K-4@Vpv_1S&aFu%Cb;vS9JuHvk;yS(Ld zyWK!-+VFyK%+jr9V=hYBN0$m?8AIBWR$!$+Yu(j2%ruZD%Qst0Sq|jy;B7$$YHu!wBf5X z!MJ4UlInZPSx!NxRozjQl*RW7-mj51p=(0{&^7_$!cmxl{eqq|Id;nV2SZQ&z%41n zFWhrjYoX7kRWe|(ig^Xej7E5+wOS3$1;esH=1T{zY(iZ-Va6SMZIP#kN%C{SJ zuXWFx1+h*74?_v8buK@}m3vEa|i_&~U=>}r|E{NffJk>j*N5E*y!w7;R4S7-jtioQcTVMu<$U0S16DhvN zuIjknMDWpxs<1@;NqyYdcq*v8GO7$xo1Jq3wqF_YM4qMe4f{R)7a}auWmf7c+nlTumh>ykQ@#K27(k_#6TCt% zMG zSPF($zN$y8zmp;jyA`RzfHJUZK~PR?)Y`33%DrsU%1cd{?cO2pT@TQNYKnAES_?S_ zZ5SBEpL-HnmLwJb8{D(Ufh+M(w-0VTa^IGbq>@YYra@FRd>8O6n1pPMO4qX6tPBTf217$j4*_tOOV16xhJi;K&*u5NE) z(cnmLJ{Yh!Ia~J~W)hqB3;P()&9#($^$Dc3Z12CUy$5_eBa7oUlv(F@3K^LvpFZDrmhpZ$LuwwgsD{4?|~OA(#gb$axI<@b{)J$$L|dWg0<`WtF|_QQOGo z{f;TpIF{ZbIR@1k%B?Uzoe0wowxlGFqD6X9Y_}?}*`(5G&>S3kBin&XHJs&(E zt0-6Q1GyPHjog=I@$Vxcs~SoIMb-~se^a{`U+9IvzB!m&j*qFd)UsnSVeIwF>cx8P za&x~r2jp4-tV#K#dxxU5rBbAYImM#ffTgG0m6W){1CZ{v3^C@ob27y|8}Cnx$h9r3 zz3w&f{FBA>{_HXhEoFtJ7XVG-)1)b@k;DZ-rD8YTEzHa#5xw`aK6^~2YuP&Ic5yMo z`yfoQ7YA3|(W^cU>QQaJ&u$A)lm`o-{{B6*Hbrp7=)qfT1@YJe>r&+2bLjL_wjnK; z^pQo4`=_92k&7S2oO;^t3O{`g{i?yPN6Jy&Y<8mn19ldq;9c5CJpZVy>aLMNA5h1J ztu%sjbv<-Q{$cEaOljKdWGIrh%r(y}KlhJ)!>;J0^i8p&q1(Q@zriz?T8Hbi&JajA zX?sPz8azD6{Mwo?dY^w9{O?NA4$#DaJ|)2V#FLq!>*}S}dv3@Xid?3b%`V0gesGP! z*cHb=>NrTO^Xy3=FQ_UN{T*r~Jy14Qte{uJ4Szvf`lVEm(UlRD95bhDanwpLC|ll! z-GK~qGctz|&&g^sOe=eWlfl@Lb*%dL_mz^`EGfiBR(iR5YNdK$#+bItzm1)sO8JKJ zIbgG#C=43fELS&Ygv8>h5%xf&m?`hRl9_Mpp!_fMyP@KPV?PbuMyxrvid#WJ;f1PM zkI&Pyk$W+*c^33-F9+G^@L`>YaqOeto?g0lDuC&UL8)~WLqvWm5b|2o6h<~QxX3z9 zMC(_}MtywqX0$*niBJ3KP_lfhDq;XCqZU8lkkB#|VJj$ zVb^)AS;Di<+CKAB`JwC4uQfTp;I6u&kfl-14^pO1W1%Z!a_()$gg1 z-$~9qUa{cn*o^%$6kvTIF$Ao%UR;j-x})x+$kEC23NeGU6NF+;Tkc(Qa_O`4>0zl$ znZCw-_MvgUBq3Pjn`*i4a;#7^Yo5<}qY67wldh&koQYI7(^432HLT{wp2kQgJD))@ zkf{@SuH|B=@|Lm9Ntj#nkiZRBHhZUu4szbfbPL-PGZicehQB&DC2tOX-!$goOsFS! z)?K*s9qxKg1Vv0D#GZ1EUIhcWbe~2QJX^>{gJB(sW%nPxY*|32UqXA|c3U}h!|W+U zDB7@Nd$OnVZkJsXrr}(qP_KBWfzcW5kzCtbtsD2+A76C*E04})`?&dP2>@N@OR_FI zwe*63`Yu9yk`M4)I`i(vpF>?}g;y(0;n>Uo8<)=i-oSqFAz#|A+g1BVnd-8h{&TZR zif;0HR{pY7tn!bK?e9n;s|u~+LVFjI)6rasYZ3F}MgQ!bPLZg9u!fxy_3(m@zxdKr zPGa5s_LenUJr1uC1SQf)tG|3m!+UR@zJ{ZeXLuEUI+MazhS_~QpSQp%CpB{zSa>(CZSkhRlNHbLo?o)4$Y=e)JmZ*s zCePRlcon&;X<>@KU&^ldSio}|*=laNi+cvCTzL8U{H*}s$BKU$ve7s|F-$vqEV6JY z{y-s5lJ@aB{~sd{(%0Y~h+9ahY4ef6DDD@4U6>a)qBWW^Yv!76DVZf=W_js?I?3WZF%jgjuY4YS#6<5mS`s+mI58G z1b=EOdzW|UyD|RRridfLqU7=_=kqThHCy$Y>_x0n_ui|rU&)n_7{2?MPF!^qRre>o z?W*P5jtp(P#AJ49+D|xR&Empe>WrhfO(;GgL5a|GPp&=A-A%>|YTJ=KdiIe{^x*G4 zMVJFQ?UYfz!SO*sg#TJWk(?^#d!w_=)cof814}j=r>xVM1>@&1KhVh(ny)z&4D-sigI=yLZ?D5f-; zBcpY1<1Y3=!2a6Hz6QEj=SewJu_HWgpq#F z^!^QFD-oN}q;+Y4w95<4+-tIRiOvFR2bQGk|m8?W$G>;|h}srdxp=iz-qy*i*}kh8ZZG^FU+w{-fZ zZwVCpcAu#_a3E%d)LlB%YauJoh@vBP9xzIx-jw3aBk4hY^ZG+Kaob`jw&aG9Y~BRF z#_4spm+3e}sJ+zg&ThxUwsQBHfwH|-XD2$TCuw+y?h~f z$@Y=+l9aLqv}o-8$p$OUi#s1KuHY`TK|h_c9;Ipu^#naveq3IaXDf>tk?Hp3TV ze}RRf7e&?YWj~!2>=aY6!_V?hiV8n_Z2QONF8q~Sm{&ZO#{_2^eqVM7@!63TedX9P zG({2K?Gconoo~v*FQ7lqI<@>Tu6YlMGwjcB6H<3gE{oCKPpW$Mdu|@6q?%J|q>wG~ zmT^kL_BG4%kC#^{%e+6IT{=4#CHRZAx|22+E;C+kud#8R~E0i2e z?MeC8J=b_o<)Z=r;~G6h=6_=6!#m`maLMUTmjyAEkJbOHIdYV8k8&~=`f^H+{be{> z?|0m+-tCi|=^@9TcvlWTmEUK?#}u3|-&4?q<~^qBIhq;K+#D}}eS3H#O{T#_YOi`o zE(h$@3t9e(2Bf}Natgp5WlSn!N060UnfPXAocw8?*+^CL%TK1c7v za+^z~w-F9-Zau?uL6Qcr@^N}e;_l-pqDBmWx_+wNBs){{3+~hDjY~yj+N4nbHw7MN z#f;AI$MJ^oN-t;Rj*s5wwH$%_GiYKDhD@Ti!E8Ca-eXqt~C2vr*e0rw5?h=EoIeh^8 z#7+5%%*v;8l|<}Ev1o!b2Lw7BgrKAuYTHdzQXVq zaZyl@z&3|&bflst3OBUzaC*g4aSlcl>J=i5k6lAA#r<6#PPR6 z>8HCu0V8|rd-rGADi}KQ{((@gOk-o?+h~OdBHlHsVeLGboxfvv|MlOafgba!*(-5p zE2`;4u_>T`%*13-8dAp5TJoJuhqj|(vggZ*)n9FfYhHt&B+TnwR>J=Nh*x+U8ikKS zlkX0-G$!)2eu_59hpvvIe2OQ^Sso3c-iW|j!$Ro?wov(27PbN2ekA1lR76QcIT zn8VUw!+|X!fr}RUCrL zq>^x9eQ&4kXD7K2?sH9N=B{^+|M5jz{zSE&V6GS7p~ia9)1lu+X!dJ84LXGnUTLp+ z-lIl_{ED2IndcnWsBBfXaR~@D8=K_-bhC_oU|)F~6;(A`n!zC^xHL6#5*S|vaJuG2 z^_GUXG;s)fTj`(DM8=Q_4DJv3ws966D)?#w&Wp@AG0Mq<^}i5)tDr+)qt0({RuCrX z7AQX+k-PcHME)O-kD`2^^p&o+nM+6ah_1^s6u`ugi8|t~@9>1zU%Csebz3!<8~f<7 zeU*U;0}KVQ(SzKJEqbNwA4fqt9a$_XhU;DdBm3q7Ly_yVuAuj^ zsxNz4CN`BW@F(tA4gapp9AXf(OZvKVYJe2t3}>ZpB7vObES0wSZD8I&*gV#3>p9bMN->JXD8ClJ4EM`e&DUS8fbrZ$L(4?f~x{jHl5hQMaX zL4S&0^it~kC~pyaXoepP?h~}gUbLo>oL|U$L0?=yN}bGC84DQ4T4b+SqPFilQj*2t zeAFaId8|mq&=I;e18<2M3Fw!#h&`Iz^PjKJS~+%utI!pPBuR=D-5~_?uA^lBIzEEs zs(_27G(ONHlu`=(CW1$saj11`pVob`CcOYt zj36>{D`DO|J0m1-D>EcdrNmhigLG!W)H#pk6!;P5o1DiAo2;9CYkuB}yg%VtP4X$Q zez?gHm$r|4a@G8$ea|?*)r3~P^H^8Sw{@fD(H!rW)T?c?XpRw%W6wKsv2)7gv3r6} z+)nxms1Ozmp>8q2i6GMyW4&%6Xk7ujmY8!gQ;uwm6n{q?!t6z(8olyNgfhKHdCA>W z+fiPNa=LO3!bFI7YU>=e2h=EGNN;K3L6TLe-bzmSJNC*4?q8)F757;k6OBUr4?xMZ z&FZ$Mm__Giq>ZNXVaC~jr3Qn57ZCvpy7w}t*R_K?%zf%k@lIiHB5yUnjO_{D+ZsiJ zMcABP!OCVy*YhIw@j2X`{!@2-Mr1=8b+Dh2(~(q<11WC0+s7D|Xk-G)t}U+0nRZA} z(@R^n_?tLWd!SK5s|mM^@r4;AQxcXa(}n5mt$Lv-dDCX#W}Ej~e}VXVU(=lwcdKdd z>`0U_9BAJA$vEAl0vb8fWUR`68RP;y*5`Dphz$8!ntpu};t{Y`t60~U0$-nuX$cFU z;Eu>0>-Bgq-DeY};Y!gTP7_7l#KtI}gRYEOfDM~#W!GVR%6j#{^Vl%UnC8I=pAsW} z`|zOTqiZ6~101uFFSq6{^LI9Jd=|fZ;Ow-dxjw@(M_!ZLhtb#8kVB$+fxW2leOgsv zeXGEcnqIm|aL|{FyJwq(_Zwecnw7btDkg;DAu8ZnRo&Ntu^hu5D{_u8Ho7n3P&X9p zVn^XcO-G_6$Zx)zq@W9-`1aT3=X=mxObzy+rkyi)4?L)9@Fc8L**m7@rCrb-IjSV=W!Be)tE*4;G+NxCkIX{ z{aR8;mWEx4=kh7%P*=*0+rMk`lB-sX=H2d9k0(#_a6ayHTd{oU7IY1>T;UMQ+Q~A} z%d&FJ)?C=nowR>{;a6K&q;m>wCpMJF=WLOW@cN9}gkVLaiO~5gA2(Rv7B`{vI%-6D zvYyr-=AQubp3y85&9)RoJ$abPoH4AxTl66@QLVxHRgcJA5lr$fRPaKoskupbBo2IZ zrgwqs@xfR8qu%{`)AWr-zgw#$Hd?YD-qmrHN^~z%kc)Bsp?)rg?C36cbYA7~x8kI@ zWe4s_>m|p?+k;h$k$D?Kmmai)0IItVm^Neg8RNchKepybAn|bKL=AAXW%^eq$sTqW z9Y)PF4F{Wk`s}TKA-q%<3axB~iHPR0Wg)f}X3Zhx%w8TSk?1zjz1bZaB3 zX?7uft_5aCn2|dw>cp=W$i+Lci>J0hWN8udV2f>r!3^yxCEu zWR~2Tvch+F+<`EUT)f0pQnxW5?aQ|O6LZ8OGDRp_6FOp4;HWjeM|U1INP3jndLNM`AS;mbSlD`_|%=pzMBkiodcQG%-{GxLDcB4bTM5lEUf3h zwGs9YW}!_@j#pm+X?_}QxDjupCNH6=5_RW#;xyl%Og)E-oO6Dhv8)yX(?3`*Gh=Uj#& ztq&#ypEJEDo%QiiTRmSDJdIp433i@EFzH@~$G7PVn{{#vx3Jx2M}%38I72$;I^h(X4K_8)?^6z}@!%jtK0%tdm1F8gTZOq@44S&LX z?9gXsK6w-F)*4QW9u@jN-nIk*-97aZ3Oi#KI3*nIoYwH<#Qif5*&hG(ol%>2xA){m z>m2$Fh}HN&(){q63+%*CiU`{%{RuosrGGB7+ye1V^V0}iuV?4}q-3W%d5%%@<2}Cb1%Rl$2 zljVlW8{xIE^S96uCXFQ16H8%|XOv2B8tblIvi;3Su-+V==wxAhjy@aH_g6U@{hT~u z!m?t;Z#-Q(4ENqkgQC29r z;LG=gb7Ne)DR0~-^wYxIZ~txt&Ot9hrj-oBk~A}LoL%pP8Jl$fH489e(J{lvk^J+! zLKILxIm^MnhW%a#xoDv)t!P4KT|*=)r3ixGRn zS10>t!)~jdY!+ote*$rh&MQwOg^+Q}ku^L*M&>9>YbOigBBQDsmj8mJF1-7c9}@94 zYD0g9C?sNxq^)#3b=Hl|9auM*xw4b%5;q@wW*zgxX5$B{*I)uK&cI!bfRbm9UnnHv z_QIXO;Y@`^T$poOvkSqehmwsbGJj+rs>(+OYuRb+3P_Z3XM- zFi#YT>QiIhIwf5al`OW|y!cnH_Dj>(;rYGd3-FJ2qGkYOZ^|I2|Ku$rfR27Ld90mG3W9f75ZAI$Z&P z=smdR>3K^`irw0~lMwOHQPSU><4`44%&U&V^R2NJhk0~zP^Ezr+Xpu!yDNN) z8}u7=8uDqb{BvXp)4#x<|A(L9U)6~~e4e^(@tX(ZT>d8aq9?N;A4b2TtG;bl)M^yL z&xHq{T2dpoFmKK%?;3E)LLXy3_;}=NJ*%6x%-hR5m906uT8{`a6@Hxwh=!NvD8)*( zR;?TBPhLJI3Z@=p{tw2!Iw-Dh>oNfX2`<4c0fM`G2PZheB{c5t&`5$yfZ*O8+-V3N zq;Yq5m*DQu4EeqHzVEB4nVPBMk6T4|-M;7Sv)0<{?tM-Vb=~Cl#kaq{sWAb?l|`*d zXr!Iqwab$p1OK8^C$SU!bt^A-{s%S*D+g0xa1r8t-<}o($^-6&wNcqcNpDQI+_aL^ z@s3$u#YZJRyOotTGpwIKfBx&JMsIF!-`)Qn$F;8WI{%k7@XsR$kw`Ao+C8oeILF{x zS9u&8>?dSChvih4;27&;+VkXMzq&x2P`OqvIk1*QZiq$=crgWK3)2J@r>{IS{ommA z?yc11?R5AX23QT(EFx1yf8+M$9N>8g$h_sYo98~r$0Qf509_ybbTjFR7O{4x^u16W zU3pHg;m27c$n*H~qzu!fs+uS=VLUbBFGJedkVN5sD%*ua4f0Uj^c>3NJtvbidv*PQ=sKi#+mYC=Bl zv||Rp-}YK1)_GOc_p2*|#j~r944ndDYPj<=H2+=Uud^gq<0gxzSZo)rTyMFGvnMaE z0{_AwwuES5ZkGFCH4GPrG7Rh4vj3Y#_o7VDpQfqh`C@17TP9wK1r_d!7VaK~G9Cr) zO%qD)Q@mFY;MfS1%YLTCf5Gh$Vk#i|^?KmOi5SMsZIgI(Amipg7VKXD7gKZqsQ<)b zJYBAe)S4`uwY};XU z$59mACaR3=K#kq46{dTCh3JQ7H^&6F%Lm|AEKmhrZEl3Wu+8pEc>PR=lk8N)FFi-V zBC(~<(I-CDvDk6E^3ZMXL3|k1oxz>W#6wVQzv_H@Do~NOFQ+8bb6?zmKW6!F4>Z%4pKANZJsnr z)5Lp*T=4U0U1C*Cs z{pq@l9<7-VOKTD4u4b?0C>%1KaR7l?;3S2jb#zn7B}87)lBo}c06+4(tBBkJ>yPgEcm#2}U~I5S=Ar(3}< zx=TnZHt_%Zn6I&m_~@rE>NuWd-9KUX?6>b8qMW|`uZZhInUJ%!cxK$buxH=?KO*2C z;urIIv5tsM`JagW-@p3zfB#|hf7HSx8Rhd*uKwI#W7D*5u!VnO4K&rk5?zBThgn;1 zMN!${fV~fWtjeh7jDKssTh{paZ6Vkyjovmz@aJ`nwZB`~ye25P1m2|nk%)}ZacVxD z_j~_T-TYmVo2==oO2A}0__#~5ZTT?2NC0r^i)$Ov-cC($`HRX0$SNRUzg<==m664s zfQri($ae>o;AyZ%@jLp#r{I0VL6S?ja%p*l8-km%TX19(!FrSu4@p{#BD z&yD)zaae7;5iCKQU&Os+YUpkp)Fe!rwN(_*%jz^hRA%c=_d`v1>N##oI; z;WIY$4`ZHfcp?NJ6W`%qhWle6WNU0iBHJoj%-LH@WmkQr*4=Ow43CNIIh-a6VI)Z6 zqi-+&@Y}AkxAFbTsWd8Pam|%9HZ6Y&6vl5BPE^{l>BZdSZeM3EJ}yKv`~22PXE}tv zbydZjVore7Pd_tYhzUNmj9blj=KN#j!6;axHHKh?B&pl#*kGI>21(}SRrkx9{yIf*JQo&t!L0tY8YyYZe*asTJ-hOz_hkUM#^x-0`J3vAaB3pX1&h_d>J$TeRi zdb4(ZUCCwp=U&!f&yZP%D&$Gs7M$N0*<3RU_Y6nskJ@M}~W_Fx5zHk}>|SftRVDdcP_= z-`*jlu_-(h?L5i#N}(|#I6PkvaHE<-sjc$#71r@`U$>=LtA^geuW+!9)92NwAx{$N z8+htAk9q}K!_&Yk!!u`L8eQg2Y zv@SV9*f2uyjHapTJ+~W{@BElZ*ZIV-vxgE}cM{dAm*`kEuxU0g`{WYGEeE{!Js{e% z5o`GAY0F`?{Z!ajQZJRB1sty}f2NXhgZanBeTELE6O2GMT_{_W#-JXqnBba8(4~m( z+=s3Gd)LObc3lT!Efw_?w0ty(IKPX7=$wF(C{U9$-N;Z2Ipj?0u#0K+Qd&j&R;m^J zr*D4cYV|CUuNi6wp1%odP5b!P0uhg|pUD6d0{QQ#`mgZ%zg(!?&X%>=w&4yfw{*`=m>@sG$ykN8Z-?}L4XTF(lbPbSB4M-&Q~AZmuwsL! zeo0ExrGTjew^uRl@wyk;z(#fAo}@5Zk9|(Rg(Onfr>|o_h6~(t!dV1sdKX&0o9Q`^ zh7aw|!9?6lL*M)tOo(^6;Gb}wL|mU2Ga5wyt?e;U><>S5{+}ZiR2(=+oQQF%H-`;- z6QB}U5sDYDOFfDl8JPI=pU#iK`p7OwOAp=3Q-9iF>f71RRvFU)?jp!8+jIUo{^^rMq6DaO4XeHe zpkvY`+gSw4w93RP`R%H3z-fMJu?kq(z#a@5#)@kiMHT%w11Ua!7HiKe0h zGRt@8qucg>)M+OO#iOJwQ)(&fdRYWjW-n#73Gl_wNbdFf%ePs^V`MtKfkkThr@Pw^ z>srg#=I4XoBM7>zF#X-w;vss`Tz=S3K2NMlBFn!Pg>DayHyZ8|HB9wZXwC+Nw_7*@ zi3tHCC?nAYilwM`&ogBb;7kU<>5;x;*dX>Y<}@5Fbij*d{8m=|c)Yrh?#+Hw*3o6q ziumJnNM;ZYL)rCS^Y^-ZV$E`KPLaIB1^_@VSNQ1p?V03Z3#JwIW}F zz&!~}ck9Rz@P}v*|M_o?!isqP(s@@>X@O`I7XA27YoVFZKlW9Sf&T1~bd(~AdO*LZ z`w%{nJAwaK+Af}F6uM6J_Jr^(`J{vpY5dxJ1;?$Nn(i%U zqpF?_Zk`Yvda(`sgKXa?;Yxd!IePiuaa1o+61|x(EBH=1UbQ`M`!|-tkCxfFbF{wL z4au=9s*ka~+Odn1)!g<=vis%qu16_gi11#^E9cfbu`h`+@c_1ZnWgwT>}#Nl>Q}3% zJ3V6}lfTm=&i>hI0`vkAlf>0J$#sxW>orb3?gOyiTM%!gITTW*kihc19oDeK*u;^UFN$y2J$s*F zcwoGyH*$IwBc%N_U87(w^o7~1|Fh{+DKQrfiD;F+cY501wMionm96Bw zhV2-<(fjM%Nj!m<{*3-+aKq(pXq-7aw{S^?eMskV0FDTFy?MCkMoJ6j?G^6*C2)Mw z^|`nDGVs6xY45#+%PUV&?3a!oR2qC^8{Bx+XhnLjLlxDXLBqeV zylFA^WFo(^?z{p9&bMILFgSMv4gC`i{u%yI-4@e z{#z}`nm#c6H!~u5QYg0+|6(#~vy{ExE|YaT+>TjlWGFniQ-2w^=b9_Qc(Bm;t$Em_ z04l3K{>If#J2WHEW;O{}gvI`hv=pXr?J!!NP0uPio&vi->D*acdfy;BAwH*7qU8QP zbL!VT7>&wg#R2R02!c1qD$S+cbhH@VByH2zMS-=R6^CD9#Mhn$mC|R+x~m9Jx1VGV z7b`y(c`Wk+a<;9X#YMmw9Tw%Smd=5At<_c(iEUbnJ)M1WWWb^@DjMo@4dhRD0HsV; zV0)8~LP6v`2rl^r#2QV7SUmuo3Jk@M4nPpS`_M;vJF^`FFKL3K5uVN*3qe25l92QN z=%x#whBxobl|SHQC?4w~M(qw@u?J?qMti0n{D@{czUFHdJ`HyfYsRrFm5cdlD$j9ewnSKC;s0Cmjsa%g2Clc>ydWN`z=DA zm%m_66Fc{_T-Ptb2A-@jkTmQJ*)G)rH_G7yN6yFl>m1-yOGbq!qlm*pboT3M^+Hd^ zYi-wGp4(5S8%B7xy9%DWdgf792e2M8;Rmu|p_-S0BfhZ!7Xq%wTS)y~0}hQ;1@d#c z^SXAz^JX|EMVmc-;z=OUt2~00EmI89VS5jZ_$LKdW_S(X2X-R>)@$MY1<0S>8~^PE zysO)ls6%!Op8?%og%;fK?(a=PMRo<-%)Jul0j>)TTg*`he%X} z+FCV!bhRA%|FYV_p_<1?%pXE%l6b`X?y5;P+7LkScuk=I|E}N5Pj6N!r zAJ3lrVQZcVy%E^p5Ea4xHq)5w!Af0DdA%$MSs0QbKIwftVDXQ7NU(x;EXOoD_=e)> zmH+HHhgPZi&EN$Ue{%En6AM!;zCR_H31%RKb!|KoWEjz)R0@UwADne0}-9~Y7AGKa}=7{cE z^S`v=|Nc%d%wszX|5+xZe@v$kvp@aOEUH=}6;xUyMMOr1Kg)=EW!D}z$%Z=p6Ma;7 zgPE~?%XO8WK9?OpDD&+(+Q~97>4vFL?Ca1H&ZgTxw}jj|-RgU*%D???R1(BFZovkj#NJ<|BS5_F8R5$-Y#EiYI<=!U9frwp;?0h5u^0 z*W#PKx7$|c%xoV?F^C^0g@pO3SO$^GGeZs+G{g_1gVPm{oBNdoNDjzTI1lAuh8QnE z@~ob#$OaGIBrrnejT%0!=jPw$aB^}N4Jb@Slo9kq$_?~o%Xi09I3V5ey6||(g9VgcR)~486nMEEXs6LTmaeo{ofF1=SuXy! z@|=pNk8&Y(^-h2mz%%3V@PixlZqCC3rR};M<&vHB1xyk6gxy}U9VgCoybWQChCm zYH&D(9yp~L9&PTl$DtNu@|qFL6LBA3a;|*gNL6y8^_tV0Q%zBTfgg#MZ8(#MU|(?@ zM$ASyx~0!DVzK3CeT~)Hd&NYsCaj*kxoE@+EvKw4qKFO%H+9EJq~>OSU2iBTT-eW8 z+F{I*_V!W-T$<%0q-wWVs#jXJzybL6b0O2hN!|To=vOz3}NBTy#3|3v!pC$kXoqlYu3Lx3Nqb*#Y$HRQ^xy!yK2E} z$fBUIdYFlnizOVL;>kzITn<>?1S0DSMA)u$z3T9(SPpL94_@@Q!oqDg(@@giU*2j- zjqK&o<=Q^dBhuuH|KOm!bL#;!o9p)7oZA~a%biH^9Kz7&&1PZf@9MrT;4l&6ouurK zx&|vR#F?`Weet=x!SksZ$kl`}-CloKqNiZ1Dpk*aa=BT{Ve8{=TfRkwbMR)|)U7*~ z`KE&m?h<{D^I8l$q(>G;zc8ivE+{?_O%ezlb}tV^N$lx#;x*o`HS+ND%<9FgFM_+S zBg&R6hYzo?VNXY<1J^56r|@OhXiMxR=Y!`I%%2;@-zOv#upH2M^)Vj~5>}k{YvodI z9!{2@u7bV;-<5&5oX^M?om8>*D9qj!#5}Yu>OfE69+BErW|X05+;7}S#(qgCBS-Vc zt6F4=!IJvK+!(G;O@>M)AA81pyfZpG;Q+y_q%td`P##uA_vzR)uB?0)?dv{tF!+)o za{4&$T_w(;H)J@ssLs)8CB(>YGh(sf>#*6x43y*k5t;%sMgvu4&`dgr?YyLJaNMiO zm=WMPyO!J%CWxGVj0pwm%O)vh?@L`fYOKr~?Wa`P5@5j^;(R{;@tT9BEHZU1n4<(Q z_p#+TkwkTT3A2rowXsFiS5g0HBuT>hT70NWDS5);Tr!#V?c?R!4M=k&^jAhMFDz-s z!7quUU}!ts?MuB+*P64z{o6NvR=I+_=lgfT%!_IA#}iN!Sz`w0LSKp}az2uowJ-Ji zd`wz)|6am-N(tQ!PJ#8;;|l@;95GVBX!F5E$gBgx>0!goxPxcSF%h`Qk#j|qC;pJf zobwZQG>TLvrY}DO3(oag6tiwcgvcveC%1)h4;8kwn*D)K_b~H5R+$e8)VyO=IRCmy zu}}yL7zu>nB(32)Ki9SAwLx?P`aHYxxS_Yy7aHHKV$lQgsi&rK61N2M5fJ_HvNLQYP;@YX(NQKn4ERq;~tfdG{g{SatW=y*PH=1wi zJI)s+sxkd8e*;(=iU)bmO_tznf)R7po__CzJX=AIFA8Oo7l9VDwtTcE4PSE#p}l8t zBnqr|!-mkY?@Z#u5vA9#Y#7hMbbaMKDL(Hzs;Mrjdy*G&_pgdqaZ=Oh9dcLKE5DY- zsRehd7`ou&>@aq2Ip0q~zrAk#APKM8%vbdjVfB=3w@-dfsouTXHp9UINj3D-?OoRO?xWb`8rj)l(4=A73tJJ-%XVkNx**evxS?0%hM&wy zHMeT1nupyd*Azd9>f7UMqGYo(*;*#+n&dHRefEb{ zyy|B;k9o{}$rua5H#RlZ8oWF=a+=1J<7?Kb%|)M>%DZnfoV18u7PFczS#Wv57pQP$ zAcHVQ*%!7)86$dCE2}@t*zC%MGlym}d&q%@-Mg?bvUe`mw0`MznS$wn^>uIeaa<3s zovCYnOXmEwS(o|(y&K1X?b;a6v&v+h&BCF%f<+m9NgIQ3xJS8RTQ(WD`+T%;WO=OJ zEQix^@9L1w@eh3OEDt-QWg9(l&2FxWjiE(Dd`E(^^=lrbkE$g-eXf{w_qJubOI0ts zk3mj$cTpMwqYd^ndaBWnT2uQm+r4`YO@jN+bunKqL~aSeP1d}ms0c#bE-OIWn@f=2 z{2lSi;zIH!djmgjOZTRW!^Q-;RGUdl;Qd^)8A~M0FLKAOrZ>EwC~Bd=_8A9Q zzksq&CzF;Qcdx4f|VKsyTgew-0T$(da@ID{@w{T6eY0`VcRjeV@*EFFnh}G z@9*=lUzFT^7kv6ed-77PrKoFwFoSR^`SM@MmSj}P$pf~h#?8=a&4P>Z5)vk*_CR!i zGx}(>s!}4I+=f1=ic28p8wS_41jXI>eJko$6TD*|&P*F`Kv!#R4pGJhmBV(=EL#(Y zbLl4mp4a;XK(eAoI7c~ zdH?OFVV_$%W0h^rNUYU<;wEXy<811PCVqVXk_w!k6M07XXueRUO+HAM9jfY7+ zu{=G5ik@*m%lzV0>3{=MW#*1E)1$5E)hB9A{=%?@Eetk?A~)vZTO;+}MC*^Re| z7k*c!lsl_gB!3mM(T`;pPHGzlXD#K8?pHR=BT(zJtCl{DV@P)xDeKOIQT)wL1n~pD z{Zp@tv^cu)4E<<7>EkqA`6c!peT&Q=G|ONkoR=UaoWr_l&!9rEcKy8Z@vXhJ!{$Qi zAwOxxS6;=0&nfxR48fYqziQ~R#!<_JQH|6Zoi?}DnFo7xw7*u3;&s*015hRo`{=Nl zXXg>{Z-BR^kMB9>-sM%E?fV7>w=VPk=1F$d{-i4>sucRoUFe~Gy+g+y_59q+L&m>a zgd$mlLgE$V=)-`k2$jtQ6}%>*jKLfyBlIky!WY!>aidm!S%styGx@n8EC8Drm;Z7Y z>t>VlSkF?w#OrkL{+97T(mB6wctDr{`8~L;lOdTsTTyb${6*(wLvS4+broO7`d3S8w+35j zCo$lM&`L|7S^!cX@}(f}o8QD7*LFsFEyxGCnWMjuj2fc0%k&IQ*pzyB;SU3^+&a*j z2c+k&fzOg2Kl7et!d^JYsh_3Eae_$69^ASHXfeI>jXCX_*4I>k#mun59tUXcHDC;95LtL}GipAQpVA`+)x|W9%7E#P|>AEutz?uLYp3@}h_msYQ zxG>lq6*@*Ar`*plGdm~TltOpxof^feQWRK!vN+8lNW4m8;ZHj^JYJ(Yr)D{utHklG zy5U%Y!go4%c{SbZtUQu(mVBi6}w|B{bekCcLtlV}V$4VQO?6M`mX&D79p(d57Wi=n3z&ahQTSx^hNW#6^M}$SP?K{h*wnPb{wiP_D zUis;We49&O*$hb!J()C6T@oe=hw(HH6JkFpKcg@ zc)(eHU@BR3k#J&>Ijs}qT}*|Xt?};5t8jy~{92WVtN0r)>7^(AqP2eUV9SKUW1Rf! zXidw#!h{IRsOjBftUHNwC@h?R_w_@LS1T{S)kQXD-XQf#KaEb_UYhTY`; zdGc(q9m4-dZWOK)RTG^E%6Gf1`;X)~%@t>(GHliNK&0974V+N|FO(myn;k3#4-D*& zg%XB~PE9S~gN?w&F6xpxyrWp9#L-w6rN$^G5Jo=e(R-F0bYn6>X6|?S*5ztjGu5d) zLYbDBy~^Vk-DaEac`xf#3W?by)dz}RHjA8WIoD_&hJx)RlS%oUPub!-N9H?Ot3qAv zUxfM&5|z9IxzlKDjpefnSZkF3C?!`*MqI($`t9bB07^+8Cx+?97&YQ+%s%X23-xP9 z&q_{6|J&&jq~Rgy!tig5J{NM$(U7AWe(*gItw_7If%lX`02YBy?rloP69((Yhc;O% zlQz?2h(dH2e&HTMC`SzXjpj}p$tzC$mI$p%x}imjd}o|W4qzqYFj-2%KI!t%Km@h6wM&yE{0c82B`wvTu{ z*1_oO;B}KO#98=q77DP5PgDChu3dK~a9S-A$^?J-#_JWfC-8x&N$TYB+oP2`JbX7g zrq|+KYG1&>*D7KzhSH?8QJ^0#>d2HwyFGRm(VIv+y722h4Pp09;e6%a;aQhtwl|M{ z{Ic&j(iQ`IxQ*Hi1B=kO#>ez9-GGIid_L`(I1aUR4+jpe_!&c=nF zj10bAA6uKN-BkuT%Nd+Bv61alW*t`GE@{7BNzW`t!Qms!_&RiTf&Tr$0!VTQvbRLc_mVR$G4?x2S*6 z=M`=Tj=<@+EgWc8KPonh13N;dY2`qhuzUdYE4Cg;jkF(H_V?WzRkT?AQ3wChbpbV) zjgd;yq1v&`d^og*f48<_FqJn2nILLP0Iz&=y0O-Yehwt{iMTzeD*bHuV9EAw(?s*J z1f^NL#_edxN6nD%5z05( zR#12_85OU$<+5j`d?M3^EBfS)HDfTrEGt=j{n%;|c|KN5Kn;H+i1{*2!@g`YnzDTe z;#v<#ZvZgCW-GOpH|Uu2b^-mLY!Cc_W>=@@q{kJTKf~R(oDBD!w|#G^{mERjKP#{A zB^wwzm&_(St?LfqS%ACoNad~>we%wQZ;UVT&{4yE$}^SzTzM?t8dODo%Eq!Vlnj9(5G9yY(IMjDM-x;Vo8x3HtE_<~Byo*lmse9e@BU_5}cP8i8 zBs^r72|hiqjc?CAU)4hV9O9~u)K1LBcNQnT19cS#rF7Z?*Y4$@20}{U1ci`&ZHpgb zonJL6R|}#R>;~OrB2uXQsshF95DrMaIfmT)Ni!nT_vG0?sm*KYH{XwoN#(gGtyP7* z^l0hdu#mZvBKxa%oSGZ%^W}+W4f$a9x0yUeB1E(2myg873LcaHyYxWecq zgB+YNUdgp;8(L;t<&oo&{%H|VLs|p=GXUU40o+=Z_)~D%d&ifI$M=rt4zC}kJI)-* zJ-x(YFWu1*7JfuOf>Leh&w%qD405ehVN97e3`sl4*5t|4nRth&GjOv9f}=M5=N9bF zg6XUzg!5jb=pdzY!K&W=soaA6&wNu~#qrqt=BfxScGRp^N_mG5D0N(V`A~`r-NYU4 z+^s@bTt4h$^7pI$PgEwEP1hgD@E0CQWx%{T((U}EC{s~Tn{QI$^w6w^f?0MOA#;6a z--7XZ-!0#!>h0Sf+Cndbsqzfye$yh^k7i0?y!I1r`>6xf8HDZO>XOdcF8>b0kCwh5 zzd}A2eCYr78jx+2du4plhi4U6AMkzK;Y1vkRDbS%rez@NMgs0ma5?Wwc@lBJPe?)B zZO&&eCLq(jLw0c)0IdL%8ovJ^iwkveZ=@M4h1@tDS3-yxqOhnqo?@G=C7oh z1rDXai@Y)C1ZLR-uH-E80u*u{QBb7ffm8F`ap7jBFL?MrWOMjm74z;|eJR>Xr*$FE z0vo+y))}&u10<>B(&YYR?;8euevo1+?;v9wFHBH!wKEND`cWApY(djW@7_VmF0t_y!c{Es+AY zpUYXQ$HHPaLSuEuE@P+!>C(wCRAjqhQ1e4d$MqXfz1R4=`Fz3I=5=`kFKdExkEcEq zKBZivfm>nGdUrFeg_z+Hx)mf98k!GTj+N_`9N+z1SuhWpYS-kGgav=xbV`n}D-izB zJ1CP$l+l3tV@s=bFY|tQ=Xnt~`lv5mS9YC*Q0n68kV#ZS@I9 z(QdMcG;gC^{ZU3BG9vHM;b{GScOpQlnh|W?al9Rz>TlucZJDuX{awzyGm6jA*|~R5 z+QMmnEA#ebZR#!aT?(7~mo7J!b}||>0m6)dl*cpUv+C^Om7^`dhVI)KX$Oa);JPoZ zcq@RB+9{VC*ABakSpiPeRax>#hDUf;>Ak<%4Q%^-!*}Ln@+(_I9~^fEzE6s|XX^d< zh)+SH+3r>Tc^7oApM>ch+-RTD4PsmBh+(_qi(7>2Q-I+#YAAddx2o#cL3?4bi=l8C zbN0LC^jpCNjLGc%6M+Z*Q}m%Jp>{)~=Vh32@6aE8V``RS)73+WBTvGal1RvgA8r8iaPog3YG z=*ryAiyU{oy9--s@iF@();UugNYej&Ri(lcX0ck~@8m6q6A2IrUIUiCM)IuT%ksF+ zqS?~v@xb)Un1I;3yg0ZZsR{s&Sog3&FwG|e2IC-#P@Xgy*7}rbYrHD+jBYn3j}3&l z@$!v8A@Bw>BGp-y+G{5}`z@SnT?&vrQcU@>0vLH+$*}Wh)+YJkHD3-3Av&2HC+K!1 z8+z-1btEJjA^5a$voBQDIOqBrTl`oG`)$!@=2?)$0iC-@BjECY&U;#DWJ2xuEl8v> zpxF>Hb{PbH|KrCGFw6PlW2K!to?M(FHDpIbn74}S{BhWWt}%YjYoy@kbTV}EKtCk2 zWWX|{p|#POLcaKPX$}5eOnBJ;Pxh<9fpZtzl323k@zt2$zjtBS*-CwvXj28>KRi6n z<#=+^rB;>e56E;h#&h1kMTT9nY#kn(O(SA)6pyIrbG2k=hd^?s98ij%h=EU-DUUqmChUN3H#OWFTkeHM|v{fXn zLzn_9u_(?OQaUya%W@k?7g9h)9!QJdl4cvjqjbd_v+=o- z()v$uMx57funhN{CA>;TUwl4GQn#ix;-R22fX80q9O+2{r34;ARY6k5!aNXD^lr*- zly-{PhmqSsp$izM5QBYMjL*!Ms6pZm`d?hY)( zdqs@NEZlk9>Z1D~!yoSazKJIJpS_W9HZ%pdH^}gSPi%xO2V#JTa64uLU0E0@VEumP zXgeEEhRb+Udl-HWxH%~4;b&a>2+};C&vB^A!pV%BOaeThM0Xe=Q1F({1!*D9k4z`p zFiacrleKLS12n0BryHvs!!n&Qj5mLD_A93x?k+APaR=YNN@R87n0L<(l>e4E;=u;% zj>|?~ZY#cptCF7jKjQK4g$tDG){jY^%lQEA@@Zscb57lH}OVlMJ!`F@0<8aCzlP^T8R=QR1DM8R|IsrW4b_Y{fX0f<&M#UOWz4T{|CHvd+ncJ!}EBO7{TptV+xAs~~Lg*Y70{Cs%LOcFUSB z`#L|~@YP2H{k=0A`~okA19z>2ekch3(S$>_P?w`(oOXM%PT0Q29LgVWf#(EL?AX@M zM2~cBC4DJ&G%IfI)rhVh@R*NJUZ_zliZ62sY2PPnHMBkikwVD&c+gx(jvHv+lLWP| zy>3dr@e!?-%j)?P&%fKL#&54ei|OO(E65L_-doINb70^iJZ^=I2WABduJh`RTFic& z7nIiqfG|nr+*lT3&GsCKpF>#u^%zaz+ut>Pos$BC`Ze5l_f|kmm!0O3YLQ@xD;N$Z zvO%}bZbbHn7{}vmyR`}joh$jp(+(fTnZ_tAuD*e~F3VB-7=dcX%e2PU79e6&QL!fj} zc|*KMQcF)+!B%#@Unjl@=>{RL(r2y(Jm>;fVJEBWK(RL#yO2j-{G0U0E!%~-NT~w3 zdpSivLSY-tU&|=;@rv=3n@{Giri*K$;WMycGlHMK2a7FufZfiGI_mQK?737l_#?tZ zaz+m+Q;Q*|VXaVl0kA1#86^Bv*!Q@nsnmRfG3^!q$A6B-z<*QtE)S)GUlro2jCY!Pt?e*Ip?T&uS`XXdpssrqp7eEa) z%6@2r z5Wh1{xW*mnh@u}vqox_6j}Z;1dEN+sH$kebn{l?+T%Jp~2%kj)2wLA9h4;ke`3$CC zGcYk-)&!;65Ui5Bp@+I1MmM+;^E4{ti^jO%6N@-(7M=3BC`1}-GCu`0yrR%GjWV~L zLGwBZz&$f)iMsYs_dT!f&ThHlv67j80~PSZ2%RQTr?RqAdK-~jt)9Ucv&!%>Awp!| zOts#d;9Qq-pki2pC|+00J0#n%iYpByGSL=gIW9k0}u2SVo@%_ED;vm#r56ZWO`d2`3ZSCG@a^(Jfkm~_<~ z*6nv4JrOz%9Mr7%A8cG$5nJDJiQpkde(7o~zHDBDM~RU=OCSXIq?=L3#L{XSL$)_I z?E6cBMB8rky)v0(9&YCrw!-4zx6Q;(uQmA|JE%Aza3v~9m zSjjsTQOPal1GfO0fl0qk4@b)}(ChT(gFbx2)!9dh6Qn?f|57PH6ehhPgJZ>V11*0L{401gICaO1&D>fPJe>bD zSd87TC|B4{n2Kid#Kz_zx^ekNimp{niLy63ch`3mDPn|l%jV_9;yyUKVTwkKS!wu= z|0d>M$JS?a$Qo>n%PVOfEqBUQ(eM^5LT$~iFMJ)z{5f>Fy(iMXaww016&0@PkUK$D zcB*eVHhE9kwN|Kuty;6%Ss=QzwV7UjJ!NIfvOJgpT{a!oazF;V*O}bBx;~rC!Q-#) zf8-i2euS&KMBQI{jP6yuX*#Ji?^)wJ{jwY*{BSdqaero&JEew25+SGbCgWnE!{t+3 zxk$esQ`^|F|)e0h|!qrmeMOB9h2 zSonm{f!WIC@YdY@vUw)TV#m>Xng5rMlnVlq)MacN5byL%Cd?f+m>JjYH@e%~Y71h} z*QErB*EmLr4o31i2aTm&wGXz;^AojFw8%V<;u31x3^IssqLEIXx;x_G3h=LQ%@skJ zW%I!c#QX&s+YDt71`c-XhjrzfVM-7esXFus&6U2c_yRTcoR&`K(fdMw7Y9D96__s{ zg!>}X?3p)Szb6rIZ_99+yd+cWa?A8ZF^~r?jA(vqvj9%Q1JX#y{k_p<$@L;+?h*Nh zImv2CnHzV!lcD%SpjMLa3>9Uqsck| zPl>F{3~ah2rJq2~Cr%sDy7f>`{^fLJJ6}ztc#TfDoQam&KvOr4!Dllc&8+4>@Qi%V z44D5j00M*bYK4l9FocTqREsIc#f!uUknWuI^pALXTq&1A-J&NxX?ioEADZd;DdinE zl`f^vTC38%Gz1QR*3`J(47}%OB^`g&!Ixb3q^-TRLN%o|;6hAK)^-v(0&J!@93kr5 ze~|g$&ODOl!Yx zzQkjuD?O7IgY8zec#}6@F5cI*IK6#@{tk)ndF)P_IG@}4^p08}d>ljhm#chUC0(D(fLb=D|GU~GBx$k z(x%-RLd8*K$NoZ7$5@&v?rp-ZI4Ua1h(%@URIEEK^QF$F?Lb?$7Ji!$Kw!Zc!T(RX zj;pO!%#`VMR?#)U9v9?tv;tcz1!;0^6aZ5=_OZ+r?h|*>>Qq02hbW;-oeZQ+4`;Vi z7p3PzQ24z}l%6#L6gKBY<}Y|f(ehOIqp4_xYsQ5{hA;ZTKgeHT1OoUrGp%(@%1FKM z1HYd;BqIO?4C^&~cH7!{tCUQw#7Fm;KjRylx8udyxIds<=kN;uf>(B5r{T^~u?qw& z)xJXD1Ju03w(jmJCUn?1w(#rlm53|JSb^<Lj*Pxndv+33heC4Uk@5V6x{GtLf(AU^lQV&rfhxY-=mB*_{ao8Gfkbq86=42 zVV?r;$K+T&ef2FJdag>u!$o9NS=l4meEDx|m_5DQ^!CE=*Pr|SE!^6z9=vQf87y`v zQodSy(cne%_OfNPfn0XtRy;9>{y~X#aYElg2xYp&W{Vm!d8qPwpvmvkB^0`o)wEvx z#QD0MJHk@UJmemT?(s2S60MS2R(0q>*+dE$Rxseq>~1$$wk9R?ZEJsreZ>>(>mDG#!2tajFDV{?7MxGz zK`!qcsLaIoro7c|S_EGMlBqr{i5pnZF&IRHt5EomuNv=entG=v{SP2;Efm|#EBObCpw8UIUV2fZzjOFawSu4 zQt1+GJA>*{x5a#3Y;*=9C5H{@il3z3kVwTbRqC#gAA!)<-QXQ!p99dUA?s(w;)CL0 zv}-S(!9Z-d@i;PKB++Bau0RlSs_qx)XTOGheD6oT}-r$uQs-vVUj!Q({Ms>Sln#^f(X5usv_64h3LkpqZn>+gW0D z5+a*2Ka{fA4qXI@uDX9Ee*Gc`y_%C=S(ZAn_gXqjuD8;Jg8V58Dd76zgWJW~*cy+QJ)XrZQflN z-VDVc5E#&kE0BrT*o7{9)?{4>qh$XKny_%tpx@U~JN9o9(7iGqoNFd>xk~&hHCD_Z z?9>q@%q0>N0E8Hg4-R;)zd(K9iJDnaOdlj5db_@oDWUXgG;A61#i-eVc4NR6Q;7#o zqE1t09OLqZ>nWytg6fw0or}xtE=q#fK5yANL91Kc{zoRfT5AByee_nn(Pbl~#|_AQ zmkIj<$DTla?>iW!;MmduD;VCP)LI@0D^hl`mEKbO0Y6|dy?=>5Z)$dAq>oRmlUn~) zU0c9*=t}JH7?B~!GFM$3nMEFunwuiy#TRJ+2wZ_{8Vy8bCO@3?KA+R%?xthm#nGZi!Rfs;B z)SotSXpBs_3;Q=33NJ@ppG^o0aIpO)PsC0dD&Vp~O}s|B`#hMt_xMXdx6E?1*WjEA zPJugB{QlKVRYGQPmo`n6=lrEYiiXy8I~2O19}m_MVXvHxt4bQ5z0}^eLiUs>qO-{x8Db0;zV$%bLz!8r&{qSu#)xnKMZ%p{ua(9d0NYt{K6*Yry^`% zhuO(yEcJxK6YpHf++agjq!N;egx?lNWNe+od+bt2em2B>*BJRvY-1|vDdzCFx%l_n zH&*r{fZk;1F~(N+x$Nrz*N{~I9lT4rRDQ;*W zVG-}oiydFa;@#qGbAyF>N9t4EX4cgmn>E79D|zu*wdnAKjobFDjazp|k?aaQC^lcOp7&c%OcJ*810e)7 z<3-9FZOH5BE&Wy#K2gTz`A9=ac~w)k)LXfOIO2t6L@1znB4`SkWrhPi?>F5b=)n1c zkMy$QfsQ^_=|$~61+wKkOyFbs&srURNHGU->xtr-$T zls25owHKEztgU8l%I%QceiE|ObpF}hBr^QjL*dymjT-%$&Sy=mg89|bwI1MeAQ+4) z`6uBNjarr7B;yU~Nrn2@wA$({xJ&G7G{~{E7cn2jgmP?e@Bjv+;<(J^+Z$4F{Spk_ z_R-r=d>S)70gFX$8Q`6!gV(gX`%3|^klYg?)Bff(LR^23%X>RRZj90rvB|egtEb^h zxNICV7%;!#gQuzF3U>OO#<6ekZX`ui(a@8WmB(&G$ERq$@;GBfu>_{HoU(#XD!H?- z7cTDyf|gR#&(HW^-{qiyCuN=S266xbs*(JTlqKDAUnFi?Rq$P?R+DRIpM~BW&*Sk# znVa)>+|uz9-p3hI?L$D%0xA7L-aOF$Y@GCQFX~Ep1cfJ~n-bVxN#LfQuUZXG?P=5T zEA1Hxn;nEN3+@>U83lwJ-imDLn$-|%5v7cfs^~(cSX&O_?jLX z9Y$Qb!49@b?>LLzq`w;HeY;={)Q!sL_f2v7oOCBGn&dr%f8zkUvGGEnV|M?wr)a82 zi0|N{sN1j2#-H@g*Z6)RsC|&{47x2&H)l-)w4d%Mv{g=h&;q0+LCi>3<-fH%HJLN0x+O4suovBH zoP)&iT9XmWj*RWb)o)2TrmyKuWXm~?Vp8=4L{x?v$X?st=ye^4Oqo%MUhU|E_a}9V zS1E8iwSt_ssWiq>26wEvFTGyhT7SaDlhVTtf@j?914ND;`QjXcDYDA}9j^}vh2FeD zbl$dvywMI%Yy)%nbM7xHQUjUX;XmOvjEJt!*J?&?9u`@QuA$p}r}u5e?@G$5<-eNz z+*0-RfwAB?pUf(u0(cEv{lwA7^c=MyvJP)$sf?-*H&&7qy^M3xct0sB_>5yjL zCx|l}cfHy66t}LveX)s0cbv@&ZJJE)=BRW~zQu3SZ8O{r*+b z^dKbN0OEQ1>>x4k9FVztSBeP060?tA0ACgxV@1{SIXJB z_qF!M6h*dlJ*@MIYvQij^vp86UZ_=Q(N;F%FplOtI*BDGyQD#XiP)bO=+q8lL;2y)oU2-y*dEINi;X-sQK` zknNLka=nd2Vo9eFM9n}d9=k<~hYKAv!wIj_97Cq_Day3Y7ZWASQ;1lrH?>z56yO$A za!|)A=#icNDbkHU03`r;knXs;xfuPb?QnaQ&l-Lbkd8$7NP*&HYQNvvy;$)4nABlD znN_LYcMaig{3+Dpaz!=RPt6z&y|l_00R~}BfJkw6D%~?v!zLe5C0cuN6U#5HpTf+Z zd7L38t*BYIbBY*r?@$+Peut|k_tS?*aPC%JI5vGIe5n`DWxt=-=T)qZB1EpRW3bS6 zUFNUUd!tk>f{^~vcl zQ`e^H7}y?PJ)>_H+_>Clpuuyg^<90V=MqhfOjh!`_EG=lgR2Y&XF4UR;v>f;(2pWd zYc6>ypc(Y3VP-nZA3k;D&gY(BBWlhv`h6QbUIFxKd41an3rhSUN3xps$Dft9pVsh8LoXJe6XVC;qQ!T1!!H-V24EUL~J;z z-8L+kbG(L^*8)vmb_K4F3lm-rRk-UMtB*S0NUf%RtJ!PoveM=_vCZ?u4(Cl8BVF3m=!-0-Qn zWN}T~nUlly7}4k0_BR?<_{-y>sqSwUlRVGg>Af4`l`2~TStRa=$6s4jTY^yuUr<@v zv)4lG`Yz+!E6bjqALbo|~eV5QOtb>{=-{94pSf(ksW39jTO>QzP1CZNTe^{{7Rs-(XAn*{CtgC}KzP zh}ddJ$P`)qRR_sCZ}v_%{KlxqK$Afy)O6`-Fn)vDI;I(A$kgDglD%$&QG zZ-x(z_e_SpTH1E9h?6h({1fMC#;wn3g^r`N9WR?F(y8eK?E<{rv36zeb)LPdJ%?+x zoetDar)1rA?x5u|2va3u?bhw(&pQxGTa@?KZ|mN29lWftF9L}oeoYHA-LYhYMxoIv=^4NIkVl1w!7KR zhdLLwllLrn9dmX+b;rw+v;_yl^_sx-5-9|2X?`k~Ulu#c9Tg7SsB?{U_=T$PMv} zGXABNF#=9kgKJmkt4QrTXy+YH{G`Sm14S09aVK&lWoN_#08erXrM@=u=Tvln(h0*DV&y#_s1u`8akprA@c;bmD~({Sa$-#|BYFi{vES8PT>3K z{^{8(gJR}7`AxQ##2htw;4^wlcd~pWmFuur+iZOrmj94=xpr%oVC_keJ*@TgSs*c^ zYdEBH_%>ed;fn{w9-b!;|L(Avk30@Fq&X`Y;lmkq2k$X}eEsz^jQ3My0cHxo`+-h- zx*^ar1LJK=$%!lGPmMvlt$Nyn>A>6wha#{7FMTw02b>{?W#llQOv+hp!c0US^ zZtHJ_%|6t=GWs6n*~JYO895p`K)yj+&Jt#kxb_YO3|sPeBflvu!Uv& zDaYehd~K@tq6!gOZ33EC5;5@=#+1yyk!#7yVVw}V;Z+VaK_3QsUNB) z@f3zgUzsCg4!wFaYE=>B-`SmF$z)U!(5+Vx@NVt!v2JouB;*Z+`m^45lpIJWXs)4g zDkH=1G##rCCjFYMhI#SX>qE;eS7`VK# z#4-V~SUUyrKx^DyJ@2}=VMXzCS>y-x>svFxQ)s<$#t5TsHqJIlf?otY-fsZ0R3+BaO{JmehFpA@_pLwEbjA8~trXroKY#^^n2q zvTD#rXQK+2x9e)%vBg!`*$`c!WNmVa?Gl%q=)bD$8?lYud9EAKK%Z4(=hesz|t(o6=UUmm(8RdQ#4~ksmMU za#!O$77wmUUuv^(2Xk!hccw&Ire`RB%Y!H2`nnMCxuBnlZ{$HR7%MypizZ_m(BZ77_LWtea0 z8$I6l%?;w|+jvh`)=l|DTb!)mh4+j=HL4>cE`(5IWoJ0{s-j{g^NrEnZsJ$3 zZQ@&(MeX8j@{W^m=rPx?O1;oxpo7(X<7QSKn_}za1I+Goc<|C@Y6%{Jl=`28%ADNs zVePf6ufk-aU?Z9b%Mq)!+j$PlxGPMVNW7WKPDrEp`nUN!;m;a0#;JU&AE#BU?^*j% zY0rEJy#rZY|4PdBWhxq4L?~!7w`onntT`ql2oodGeV7hZ z#nl-98_`F(fAbKnpPHFZ`4Jma7OhM_O`Wl2T)czuo-0+f4X&(*j|P-q<9#Il+Wf-F zKS|&xDJewu)xQ@m7^Y%O5C;dn>hSS-_A90hu*Q08!<=hHWWM2ZwF-K)PEs`DLooE9 zpQY25PhvyW)M@17;rUb!j8>yH85!Am2_%j;#R!jx=)G{7$823&skbm(oIp5m*{-2_ zcKbbXIw7+;zFYm73A+S){2-|8txvD0oYWJBDB)XCHOI}1576M`&a3&n6>+VoePG}% zs)&B0nr~B2VzPGg>m*GQGA+C=A zS112yh6``MiPX*2GJkPGD@-1}m#>d>Tj;wxh347Xpe)@No=Gpxgl3w?Uurx3GkCU4 z$HQ=*4qi#r(CMi!8Vt6pQ88Cx?QbJrEAEfhuEu89mpV*dPwaPs}>hPO< z=z9A`o(B0v4l5(rvpJo)0&k?3hovF`pBJ6bECq9U&9ST#vGo z1-A+3Oy9z0pC$U$w3nTDFEF{euCt^bc2ZHEA5;5J?toiq7LX27XP&I#e;hUqZca?9 ziiGP`L2|s$4-wLjM;!YVG+jzZQ0qbw8-q;S4Cu`ko<60oclWhB!=yM0Do~sY-f+Hb za2M%P_hp@hJzj{w@;Bd`lfA@-*t05boxua8fy+CmM&_fK^vfnnmWZaxNs3#NMX1c)jF7-ZeV_kHfyte1M}WYThTtb9r8C^8 zvq-tUy%EolYGnzgxF$kf5spy{>CwW}HC{B&*N;iFKh+fA;K&G_u~g*Gt0`}uuAZH~ zcH&FEmtc=8PA&&?dAwi3fgY6JHhU)d8{%oT&l z;I-SBUUiTsFs^Q_62R+9oS}4532(1`q}V{0IsT%uN;UJn?u;!o2ZrbOj54(t``zne zaA#-*O;WY}I+lHe7fu+R+2V~p%F$|OJbBIYJTDYrP9NBrwR3i&-s#4}1sVRR_Gd6< zA+gd6fjQe_)ZH7^rWndrg?g#lk=#LbUq18K_ZXpGoF)G1aOxqaJkJA3EL!d1{WZlp znjlpIcU$?+jXGe={Vu#W!!@>z(eevf`RK9?*N1!)=iMzK@X?Yoe?%Z>*SrOk`oC(J zs0f;ez|2!NDB4oz>@$lQ**LQz#eYBfe%kbu35wQyD7#l-vl`TsxAd~Bj^g&FCVA4- zpPwnmbPHS9kSRS%)y?3Y_&|m6 z&$Yl$cjYa56&=faT&$L$*yZl8PQ8Q5?} z5MqR~Br22d-zcT`z0YF|$XP$sujdm4@C?Ait8#Jz+*AU9wTSr*dmV6)s4|&r_>eC= z&Yi5bs|6779E4 zYQxtg&ldwJ!PpfOS_&ixByH=ub$#OE%XN{4j{AL|tnr{^wrhwUyv^QW$#e6x#zI>5 z6W6|dPG9RZ&~#}$>J2q~X3YJ9XR~!r!cqVOGvH{N4OaN)L?L;Z_Egb7JBejKysg8} zLI+L+R~Pd$2G*nhsd9Z1X4RqsY*>5}A6DaiI;-PGeS?m#^ooCbwtJ6y2bhcvyLs%; zmEu%2Zr}=-WnpJDx;|^8-q!n)3eRPt%))HVM!HKLXetg6Wc0a^hrwF84q&d5(1a;#2=WY2v7{+bQ&I8x3F|?i zNnXcqq-RqV!i`3`(Cr+*I9L&Iuz|@?zyyc_60psb4TZ^I(mkvZA6>Xf;dbMt3Snqn2+Z9Fv%HF<| z^k5dI4?dcD1KO(SQrM@q<6}YE;VhdA#iGr=^MqHFef%gmm1}OS%0TuB?;Qae?h#8-+ zQW5`I?=&%>o%3#i=Lo}zLLneBmVgnzTuH`HXutTwnw<%X_w!E)y(bD*<*ff~$^XYT z%?18-LfPe$#fbstlu-+@I5v(!EAnLe1W1|GNLs%2rJrnxeKomoEE{<$&`(+j{Uog+ zjecKr<8jMR3VPnKt>LWFRF59FcylCHplPKgphvd*Vt+-lP$9E?`D|h@1^8e+7Wh-T zh=v+A3N`cmi9>cIT}14tQVu~w-S#0U_;^+2v`*InOrKNhW}8+&)H^}7ZT<^5c3p9XE|8ZX zEIsbJlkTcQBuqH;DW8~zrfj6h{r-F$G9D70?4%jmbJO)ty2Qh{R_`7`h}|ep zjO`D1nE7CvV=%Cyume2vR@nab*E!qiLJJZ3U8w_^${g%7?=2>y?6B$miwO!B<`L*g_GbkYP-4Kp%q|pCyK~^6M_U!!*RNuc(vEH8{K;C8&)^z6pWjBBNg`Rb) zi7oZaMvxi)@7u~R&i!%**MIngRBPhqN1S0st;!pRq;~xp+C3`3lSw`MM)CEP3|$_hMBFyEdFyM z+b#WVz_#c|%WuXw7HAbur~E)0PE-6!R=}f=BV!BT)HYwP!D^1W6t7A=0IniZ2ZC$c zrnsvjBGGNoSNo*#JpFq-@2kvVYYDCN53=#Se(X{DzANt~3Pi*rMA$rFyjZWAf7=cO zmWT+?$BM+{4KjXuh?0)+V*iB5Ue#l;BTvaG|4kz&9`iiu$0RTYvU;$Rrsm3&&U?wC zi&(=Wtu&PfNvga4GJ*MdNKH~p#_PG@O~&I59kK;|ek8gs@|Nc=hL-=0+i|aFp}%kx z9LR3A5nwH1aAXgUq3E25c9Fcg-?i>Ef$~_cq15bl77+CqS};CW=r>(2h~fIo(C6E6TIfw zXZ(<-M*D?)Kjw0E}!r0j>3QpLRKd2W~=m%MPrOVRi2a|y^P5fEW2{K1Hg zXkqvW>|(n%98k`cCHB%k$`}UW9YwzAc@XRmrLTZI9jCbF8WwUwYY`_Qbgus!BmWm< zAY9@kTPRL>K6ZIOb_`Tx8H8MK6gZi)x0S32ScQ86W@It74AZtSIz}Xf5#aQS?skLy z5H{v8sMMB`liO9RdBnPy7FhaYzCo~7FZO6mj7#T%TJkCpOR3F>Z@CrSb>@NR@dJTv zOU4$XP)asZ9paq)0{0Yyaz0-HX+kjgJf3>cH~9)8KRK-4R;Ubv)*1yBk%*|Ph~yHJ z^^MHq|G%FfLQoLmB*tKmii%g24PK!cgI4dBr|A=yC%rkRqqNkc|KdYRmN;;6Z-9q# zsi}{ra083@s)}+IOrB$TBglvgxRD=J1|#o;R}_E++J%$^|CqiDxtk#>T9@q>7rrctn?6-df_8YQ&;pDYzjUs62ijk zlmtlamz$=hkJW`C>>fUaH>{23jo;er1U z$W(rW@H|Qy6%#AE4Vs%*b^4vIhu2=$(y7h5-UsN9Uqtz);L4x8-f8iL*Aa@~u5p#* zc+9m8J#bjbfbT4h!8YHxWAc=yZM&7N5I^z>-S^9xnY|pPnvex+hK%2Qbuzcx?BK8Xgw9FsDeVov zlDw&YX!#{2F8lmatfTrwLSAPDG9T(5rsjUYUvc)>q=_MEc=UfGLc&JypHpBmSbc-A zYl@XNg4%44%%n%yaj!2e3pW-%hSAUG1q0r$D_*W1pFKgn(utO9-&0b=jay}Jd2ip# z^4`IUJIYz~JqvSb6?%1@T=B; zjlc-$S*p9^W$*%No1G~vkzsF*&uc^cxV|9RSK2 z_9DpciIz$W{N*0}NT{1t9c8}?Ovu~Rd12r6hUYG|Y};sehBiYJmJuqzIFdPZALDV6F2xb_ zNpUx~X1eDf@lmm542+!U$cI&$S8)|ml!@BzV?l$3>93ra1e%F6)b;V85^rX7uR6Jg z!{nWABY$)TeqhM>BNo@H*VxLLp@m;o`Z_=RMeuL?2>Yxc>WQ5GM7`m)dg$Km@a5od zU20U2pkVjM!6G6i64Ib}nUgEv3^VzIsxFF(G)lBzxUwqNU!9^eb((nt?bGoh#IL8N z`KSa2tGVq5;RWuLE{D7TFAi!B_II74w$D+|f84${>}~eMuTJhACt)j?PHxI%jr`%z z+X{-vI_UMulDg+U@t`}@c>!HKKitO)B)99c@kmt+J@B~OomAZ%b3m>Aod59_#uEo3 zo!rY0`28+`y?3Q%QLU;Qq=&k>?nt@2F)>)Wvz*llPF8z+WJJ(=_zDEypgobPF)3+- z^a3J9pL{sAOCOb5rP6Q)lFC$Rk>4EH7E^3 zOYkAle08Qe29j^eak4l)i59h8FK~-j$4Z=xF-xZG3|cVGR*pnMFNg7x$g2wq%bFO*{7L3MLm0=8KG zi<0n~&ngDXui-(*ui|=Ggzu40E>AG2iU9bxkRw(wiDYd-qeinQ6&Y1;Qr;|kC>zS?Mu{})o6EG`b zFkNnAZ*+NM3pVJ8vC8u`nCslEr}K?%)#up%JJ1gG3TVN7%J=Y*_4F10MQd2PVAnS% z5{K1yW4-2^+!Th5)`*P~`OQg-aAKPSUs2N6%h9ymqff0ucFR7_vB zma2?TLMc|RPU#W^!rdI7? zIN{@WH*SQ4_N_d3#wG{G2RwQ`bD}>cGRfQD!^n~~!MMytiDtc#s`SR!1k6)RHm~cS zi3?xge+Nsdyq`Myv_d93KtOgR4#Wr(C5ip^747d2ZG6)%)00j64#B^F8tQ1T`*p%U zLd2!!117#88ou+@eV+zcR0y}|R>(c3T&d4#8d496D4ti4w~SaN|EW@e(iL5!5^F~Y zl{XwZku70bssk)t7Hi`Sjj<}y(eYtpWwdxWmUg8fr}j8dm=y>a*>Dqm+WWK*=~tvj z+O6CC^JiJUN!qtzM*Hi?FvAjYSzT7NEK3qLo|rjan9|bR;BbtX4l&99b0+AEWb)W)c%6n3J*H7e$fpbufaJ%i!84&(u&wC!b3 z!Y?JA&S@KpgdD#D#+}=i+|fg&>=Y%TLibGT986>i_`Wt3^CSQcx*8Gs*ExUt`a3u8 zWLzuGXK&+_;plD0l|8u<&?o=qhQ-GO&i46Rqx?#X2hE$ChR057gwsNN%wBk)lsVO3O4!$KG7Zcf(}zHedT_lGe1* zzo!_}8zqOf>hBAtjx@6-Jg_Fz(I&(L{Dv*XhuZ@gjdOqM2qqYH?acqrT;>^pU;`FVz?ufk(CIAHn@S^96h#^XO^Ao~oGQ$AWb!-g#`T zEp?}Cy_5}Y??N^P(BTZ}oMoHh*r_(lyN1()I<&Ccw2-@+Uokr!-soQ=0x`Wp#`DBS zYn1dFIxJkNzrKsg&%jJ3`p%^|eWv!MMudUnBhT6FuMl1DbcV$anRu$`PIhs_BR!6iYMH5D#w(y-iyHG|qAR*fGL+ zcVju)EXTnx#o~?KjrrkNNng?4XT>rWuNB@tFZ_@mfr5lz40P77u_~nSN?Ht4tmtmW zm!<0&uU5fIEM`>q=Tw&8)1r;R2aG3$sy{Q+d*`fHA>|#RsNF0;Qe%r6rQBxL;%`bl zSgA^vczrxa$gLLhUY|;1PXU-Brer;&=1M1roiFwGo=3FAbpI1%+Ai@Y{{|V{a-&ow zUFDC;S8<8J*@_c~7d_E0We8C;ON}k8a9!>zNNe5uJjb=$Ax}t89N*1%zH(r=6W~$f z;UTKZR7A8^>J*#DMVG2}SLyVX?de&dzta+}aJB=UwUP0CELG_;=K*rye__DSo5t3I z!%$|G=`HssL{C6UfjzM=*-n#bazRn?atOPf?3QEN29Cni#s)ej{6S(lU`Sr}_)bbC zvS*n}%%?@x``(S*Z>Tl!cU<*30TLVt0j6ej-kJ_oAjS|jvjMUe8*=}@yMD6E1&$9Mfs5)Rntqu0|7UIcX- za=KJ@|2O15`^3-{Z?jYH+$e&b&O#yNFm0QuM8ZCn%*KFw}tB|q({GRLjjh7t!55 zN)tJ|%Ne*iXrYY6J3QIw&TfF~#MBA!Lo$CP_W2zi$tF6wKD@PGYU4z}A$t-+^ z@ddUk3aXP~S|RdcpbYUavc?`V=Xs)k{W=pQvCeUz^C@bJZvt};IL(6x_m1mAT}7YUd7m_$N=iZ~ zLgrp8GYbGBbTK6pZ>@zL1s98-nvp(-qTUepppJ-_CM7Df9V0 z?`d|`H5z&TXTy%eYtg0cuGhQfefHT974Hgtmvdp@B$|ibk7ZsBG6OAU>g)`i-d6O< z&&R*M=tQk1vp%AbScYlC-2aB0Fd10oc#>kl)a z=-6z-hn7mdBI_}}yWON$K##{VM_U`VTV~T_*ejsKh`YzX zAKmqCGYT+@^?0%_b`5iRi*pAedt!H9{v76_w*4){BZ`;wA16 zyy&O3V$zDTXMNc)gOmL?&ZLST?@Q#02+u-Ir@|Jn7ixAbb>Z?!d*k(R{_VyL-+g-= z$NsB!^4orSc^nZhdc~uQWtJuVG29q_&JyUIK}u>wTM>&+xQ_M?pZI9g&H=x7j72#5 zEMd==y$DDo{kTml>Ew7j5BOTtvzJaVZe~|2vu43lnr-0x8G~maXS5ym=wK>d`xw4& zRyzNaB_rB)+V{}L@J6AK#vkN#a$mlP3&T!99b#O9=MV zQTDGNXXG2UgzWHWZ5BOh2Sacid63evo%ETcbh@n`~QQos1}0&~A7Us_s0qaNq53#C zmUn9Fl`r*gSFTb(+|Uh~a|LV$>NEU*f zDt9t;)Sy^qy!g0Zxgs?7NZZy!VzzdKb?$ZgYY(76;t# z9jUvX{IYxF=!6za706zB{D-=Pyw9Fl3g%WBs8jaIpgDS|g>Bl7&~W2>bOw`9s7H>= zRnx*n*358c;uXSdW=H6Z6N#QQj&#U38%2}~-szVt4;# zbc)&+NBUfQwSi6$H0s(~`Veu@X@m)9&54aFL*}F+2ajGt9k{9J5G?VX3Jfayono7w zoQ%N=`&uz8#cHpr)W8G|vI%AKdw<*w4meIM6LFnp`tAKCmUVYNLG=)(SevcMS5Q+% zeXKRBG!Wz&e8j-}t&w{pUmUo5qNcYS0=_DDdwo~Pw%*se4zo6(^*O$Yjw%-E?e=2> z0B7QKSKxAvh2!QP^&TzdqRJzhY%TT-DrfA$9s`-+9Qa#63ZoR&J*Hnqsajef zmFs1lQ&-dNox(jof2ub_Jpo=8ntV(Pin-&YD;6ZQn(2|h$L%+Q`KVq6Y0x!3# zAKSdPFb0IL56~APB%UITO=qK75m7`(qj#55I@Q}AY4(Zu_p6Qq|A`#X!uoK7QaQXP zqjO{)9&3*yUx4wAI*qv>o5HSO3YkmAEJ{yiIPHGG=~cR?5l!T)4yAn;so-g1QxD;? zy1nX6t2dt+FCBP8E-Ow5`-ohbh=FyPX&u$TWyzS~u^)5LV>W zyk#A@U3_E4%P!-N|Lo++n3XnxzdEVyJeCpTWVtr0<@>(Cs2EyON?hO;-OEaAD((K} z&fjI}m(K0=n#MiK6P&j(ot&6Fzm-g(!){?-plVTRjNoV}#d+?{dZGh+be}U@u|f&A zN_z}in&GgN{+TK(@Lc5lQRGx0CHQ8B&!&{kLMDSaYHkS(X#S-(=J+%D8j1AZK2CE3 zWy~YAPJOH=@1?V_?BtKrCw1=ol#xI5U{myCIqQ{o3pQRciwhM8k#pC7{fmR#x~;3{ zqA9t1)C&mp*Mni!gr*zD&1(r}?tAiRpNhrz86?N!dp-ts5RIcw4VT%wNjlBG62&xb zx>bm-b6S^3nNL%U`7E-zMSq1IG3m75ylP$4a78S@fIse$bZ)#K`r#IFoYZ}?EK;-X z*KWfOmSN?Fcd?u*9(^yeN0M>sh^c%))-T5P%09&nE<rxHnyxB zN5r8rl_;M1O|lclyH<1r8sFoEyM}C$s^Gjs91;|UuMORwRPoEQQ|vz%0z^S>NE#nZ zxu|evcCSW8MYFu#Wem@FPzwtw(C+AD+}UJoFz8*<1fpb+T#I#Zf9aw|YIq-b)~r+& z>UblSr=jg8l>OcVmte1z9YJ4<(xqqJ-(OEl8(M}`&+_!N#nMj3xqNkW`*^85dwZow z{hC5eSQ3(^S@<==O^($Y}BO~fvQq18B*IDvEk{i!KO%@rDaj>rH1@b%VF zaXri0Fa!_52`&K=EVw(tAuvE7KyVH2Ft{bS2iL*f-Q5Ovx53@rc_+Vf&iCDWU+J}G z&HiJry}GNbtDkzhx+=s(muEo2`;eV!%{Ty}9*$7G$=hT}_X;o*<5v^>bI&uBaMW8s z=eNoirYYNfKNSqMr=h!(CGj&R-mxG?;&zqXp4J_j zi+>G;p6t$sNPAEQYk-yr4PgA%AjRyjPuI{f;RVEslIX&Sw@V) z=t)yq$|Jnh7h}q1M34TL_pjgvo5e~;OR=j&-t%W=fkz90A~mW$k82b$a~}K_jenJII;fL>jD#b`@g=us**Wn9kP)a!v+be)?Y82Ev z6hiBp8X`YWAM+&1fSPQLSLEcEnovLeW`gEnZorc)d&QOH;KTv$z|&kan(5lWmq*wH zLjpl}kaLDP>~FOT%?#xH!J}&o8I}=mOLK; zIM^{wwY4$KBs=;i3WTNG9T0F9IjE1HM&tye%+N9wt1lBggiTq5SjR4RDz~1v8!3Rz zlX9#MJL4MYiJhM_U>S=gHca@Wt`-QG8kTGUD3n!_s2X?39f9WZLr6?O;&fdQ5Q}A)4^Or4CR_^<*#Li(3kAQ`p^CjYKK~6e-RP#1ctCN4b+bA7|v3gogBP8P`wJQ0zALAM6%w5oDjttoVD8wW7QA`}G1? zH|p{(%Ykt?$u4zZn6km%hKxA2S2tyrUHEa(PUf#W_In%~EADh>l^SjS^>OY9NF`mn zuI$XS$&dEQvwK%-5(XZYBHUDoF(V@xTugs0CN{ot!!p9P;)Z7XT>40B(PcVgz(Ylk zk>x$8Q>QJRWjEy|aJ$EcXp9u)ZcPJ*b8~PwEl>2ahjX?8)NuG0rxn-RssPb4iY4mN zZ`pYAxn_uKvo!k&>(b}Nlx#JdfG)uZBkoEj52Y>6O>26&Eq%Pb05E?B7HQG+hcAHb z;d@__v0;bwj+xz{jB(?dpo--=p)+f?lZ3f=t7N z3k#oqAfo|r&}S_8ts}d?aU2uHR5vuN6?Cg>9Y^DgoUk2fUH*&GM;r;8e0aUPcyDr^ zhIUE>EJ%ADh_voT#6EvkOXY1#{p7Bjr!BR+Uc+ll*ZyK6u3TjMSRn)-2YeaAViX)X z;EM0oEstDZqkxu6`k6*J;rk%s+Hk{ISgu9I)nXA(EgBW*Gs;B+iD`m$sXI`zJFk?cKVZAn_AKVX>y!iQ(?KlO+V6`-? z=rS&G+uVWtp81vro70uU4Q8A;SGt!yu@ITrCo}GS&DA62GojKwlVGV8S*X_bY>_65 z2b#seoEjbxp-z?xia5 zm{#R0^S3Y|>TlfnlUNg1{Th3`p`6rnWiH<7sW2G93DdsB$0q@o|y{wH@U8++^V zD|5BF#Y(8(J^gxf1r9tg4I^gtaJ?sC+&C)x7r1Q|O+?RoJt5~AkL-Qt#~j7y0vG11 zuiU^#4?Gw?mdIDTTK-u6l^3ebq;hb+*TCpOoZMHZUCe-9H-|j8)D(FkO8d=&r5gW~ z=FZ`^V3XlQE7Au9XZqTGx;5<*OscG#uellFVxriE6A?*ORhIn+j%90;V#Jl>{gLW=tJiDn zsTzSFH50TQ_^Di7=MAhWo#i4=!iur~n#Qr&S`D|~FZ5O#2TdQz<@Qb2VUZ`)jBOJA z^D5^baod#&>i;5Dqlw`d{kK2suHSMj-7$w2gfm}Av=EjD1-cek^UC4!Qk>nQe94GP zN(rVuxa?7u3i5j9X%4)l@Od}sz-TD#oeo11m_b-semOqb-e1HQv2Y6!1D10Myw3Aq zUGjDwxf4yohkRiGQB+vwO3IINol><0eM{NWSK4om$SJyZ^9+q18d6m>yw8 zbw1%g-k|)sh=`51(gB|ah;W}JG zu8G@BEXX9@#HThbY6*qCs1 zVYCrnhVx5{ZLM!zPBfbX4;O2uvY|XQxw#YW>!*}oa_H%TzX;hUOwj)zB;sITS>eJ5 z%zP~Qhy&;?IP|D7iZ5}Qp?^W>*MkHk+);Oi>9$5K>x$``RzY1lI(t41>U;yWvu?;b)&9|A*$5JnMqBPjLM z&PxoJ-$+cXQ+0fZ_2?|QeutdmThZG)H7HBkC^v`I};r2FV2nN#e{ z&SwznR@Xu!em)y-)`DDM<#etEqx!``YFcT8{}T3mJFE$}z6p)-KZ1NK5u5=yJj-In zy*TI}@4UV@kbFm@#$dQx!{k_-q@9djWwehaw--dh6GnCtt1!nRYSN+SxkjJq>vHa` zjpF3GdyhRC^;J zXoeXFZ?wIm-ecC~Glynmq>+Z){`LEf!yMB)f_E@P=4n_l77gS4E*_?Umqh1eznPf5 z#WlmlnF2^{d>3?Zy`zzeLOK> zD^iMSehk*Aoii^YMR^mKkIYOo@n zmE=@?pL1Ev$$5=y@;!XiD-KzuBISV=ZEq=u%#Abc{nBg{eSXbV^YVviT$0(`x1Z8%82A^jP%kUKlUOnB>GxHuO|ve4W&6l&?a^hv9UzJd{MMu z`Pgjd>@Veem_F*9zSuI=2c5K{na1K&zo8j}fF>rb8+>Xp;7qhgmdtgo9jAv7NEh>D zNkqi!Y{XXMYxLW&nD?15h{-b%M)%9|@9uA7fia~v_a`0dbwa|y5%n#@e*j{4m5N}W zNxI0LI)R^3uC<&=5pp!b#wjs=dB4s+(f0d%S;NN-68We(s|_RCFv?SuL%PzLHu${v zy%{v z)7U9IW%rZrYxJr>jGu>Dc~@Hap+z>byUB>dGOtyfxfL`)qSsEO`*=_0rdMFDr`vcVh{ z*$^3t$f!4RTl~2Pr75SMHMeJK+_xH98{{KL?c@DDTgqbInQx5+@< zm8PamKCr&s;7sNeufi(+iTII_&eFt_$5!*HhL)|BsFt&>w5x1x!b@&c{)Jh4jhlE2pj$*3n*3>%O+Aez8e;}wytRlU?&d87> zoK?UI)a!+8j_tAqO%x;WFjZ^jK4qT5k1jp4d#%7rUb9xugx{wdUFQWxnh=O;t~p8S6@J|nf|VZFfK;ZIKcdBb?kLgbT@ zBvS6^F}^l41`j?bvQ)iC%{!)0n3~e-fjCfqQ6$?dX{@CIUD#MgSff9TXT@G72pD=7Z*wbR; zVUOko5~`E&g=RqwRhLz7BQ$5GhF|q@1ud9%&ztmf$U(!tpX(ab3$mhOOp+ihG|YMr z=qYz|qLN2*9^Uqp;_2SYB*E!aqtBHmXo*ay;upih59 zw^|CXY)ae0p&6Kkh8!#b^M2p{itjC4;V;CV1i9(!5a8Ta3(^;M1f=u={_BBIv_;@W z8Z*l$l8<>AGMWEu%2+i=$CknDtOb%Zi>}>vhVIs8O2MhiT8mt#Vs{TeqKlleT7|Vj z7Dc~PU|^mSjj?!d`A!dNfc?s$rEuSjWf>^KUY@8029`b2p1LUmW_jJvV$3Ds6(Rtii7m$*J`nq`A~i4Y|J_fQ18gi7AM%pn$(|hU&C)SL;bZ5fp(bn$3JUP&2g_> zDY(FfHI`yTXk*;lu0*Q}#NBk;gGA--r9Engvq$vKK-%QAYQP#H3$QX-XwDrwJWB`8)Ooj-uI~q@Ou8g;3{3wvt+S|H1Yi^=CSw zws3-*P7P>5`q)z9SL4G7E6Ww=t)<7!fni>79WM@n?PNb>2t1xK+}>7vDjWiuUzb?Pjc0?T5*;=Uj2UCisqX9-J}x%Oj}xNuso)FH zu(<3C8rx(|TFW*D3hgHCKlV?-$n|(!laRmD85$yeTFKY#9E-MC*NKKQFrjqo7AIa- z++xkbU4kQSb}CcX0mL%;bPx%={Etv3K|UO5^%jY3020u z*gN!qOU<1sz9~=PT(d=$VflU5J(#eqBtesRjQ=_z*cdR~Z)bY}Y0uwUDFq!pp@lxo zZbwSgvmGaT*7_SaDe{F9e6LPHpd&Iqd_xRUT6KV-AJ~^En9ftu`-J-)JJNHc7+jJs zf!6iR_&zo^>cq*T=rTN`De^Z=%QF?qEw&zggDLMPc7(X5f?W*T`C9B6_MVT%nKKw4 z*f`$#SNCd7YxP{1F8IgiGtidTQBOtf{}78whzSiCe;zpcPb>iW>Z%ShhkcAe@Ykv| zJRui%lnyzavd0A({j=V=rY42mp9d-*;Z+kt_A?oZhH9_lak!9m*Eex$PTr0o6p!0{D0LH$gGK~-gwZp3{XVqc)IMQDj~Ie`VlcZN4ka14 zq@vQU)>$bfeT#m;k0YA= zAh%xbK$O?AESg@O%!-kXm;qiB*$~E>45FR^mIxO{+wvqEmGaNLeWz9xBxGb)uK0#{ z;*O0eJ~~8#eDM$2Ek_PmFdHWBDlx9*c6!RA>QmA*ApLCQM#{CkIB+$ncWu$MUFbUs zh6n}PWiC9nJuJonG%0&kqwN!NV0O7RRvgo&z{$>CO&F?Hf1efahz!cdWY|o_#;>2= zK6CjkrMvx=aDf!Rn6mXwqjUk8lfSA~qgpF3}sHe^9r#TK>y{ zm9XZX?(A|l-@Bq^z)uzI8@6z5FrJjM24FmluHWW1YjL@-;M7{7YucoD0<_68?$fJH zXMV!O)!=xv{DdRSjiTcW_H%siQH(=a;>*#vruL7$3hrTq=y_A{@I@s~1*6lvS0ehE zrB8X^Mdkz=X3TXw3iNj-$mFvnW1;tZ2+YWcPEOj;xhsmBNv%(sLIL;B@?jIK{vmoJ z&qtkGER{_kPdbvt+@KC)Y&x_B&UXm(Chb==bilxxQ=1W5 zyOC(q0{Ch(o7A{=$95FyvS2}rG*w>iB%^u6|8q5=jHNLD`Ag9yDfK_GD)zLk^uHJ` z$((ZgMF1%ai?6afdm)6?`!Hya-ucKmfxRO{4Vq0CBZ?M)LlK-u2gXOE!D
tWB{Ly#hBTUp9TqJqNH{Ro=rV%X^P?G4UJ=hlK*C-+H*;fM{u5rOJ1yHolG>Rq zJhGXZmv1eO^R%oTU-M@nkbPW2prfCQ$^}}bX~#jBjkzus&!sqU!HXVEg(J(my2*NZ z;M2bYXVQFFYVyQ#hVmS;uuCmwB=d6}SWa@5w2y0B-m!7~TIEjkQSypQB5e*PrA8Ao zVs3immntit2qpU!ufmmrtz}Owy5~9OkvDs}(;pz!a9jMCh#My=p3j`*;6SBSKRYCF z&-^%&QN9>WT?VI$C6jHd>lZJgHQ0;IxJ>uebvU68mmyNzo>X66ek+SG_Kz)n^DrQI z&9=w|wI&rB|DbJxgXUL%BzHOZ)(q@a0X$T_NgwL2H%8){L1n0r(YKq7(jR0F`xlE1 z-D^5=c2WPrTqRcATAMMxO8-`4xYC1_KA)XZ8G)JrK{MhX4wOEtjDb_7PVc25eeDQ4 zB5->iyJH@Ud2e@bBX-+3oBQdfu(jb_2Ad*@e^JiXo|yvziI`BOB~&!#!oEx>@sN1m zB;&(8PM?SpgT9OijaFWDea)u%Si%Y@;>@($roYo-RYl8Q2tp)qoQs5w7FYU?3!_pk ztH(LQqyvmU<9n;f?7eJ1YTu(?WZo|S1C)weELOT8l4y?eLa$1rGecn@rKTIYHxuoh zGCc=co(K8Vt-YR<*+mSMGzK_0;yU47F2WBxQPjFq)WmF7PC>5&@BYL$`3WU@{Rg_z z$#Q5B) zrr~Fwn$pnP%RY|23&0a2oE*kcu~FQ3z|XvDtR{YW6Bg*D-+6NMdoEF-!oF81%tvXP zx`~sixC!$v(0`o@=29jioqo`u9L5c!$)5#bdK!{+Ib@bV{)Z^Ic&B2cM#4?j4O(;I<8)SAXMbe{wDc;=@- zIW$Ks&;7Y4HqT52K_c-z7%HT?Q>H+a1?W+;vHYlaG|g^$N6EC&9Syr{Mm&1%1E#UZ z3-UD@{cgPAP$F|S-C0iInMtq*GzN#8gVLvo^I%PPtxXlV_hbM*rvd~=EstZA>HIVUUOGa7 zsR_pg1D}6*P!i`}JPRyQOqxv*y*6bNsDpjtpSjz?O{Cuv%v~dnpC)nzum^yW@&ftH z1f7cE0oP)rC*0(eL~|61rbel}5>-<+O1~70`1v^Bi8i|=lD=wp6d2nZ%#n?55fsce zu>-msKPmio_X`Ol^?3!N9{e${tdTky2x_L$%7@T~@ zz*xq!tjwEkk6vw@q277}A6J76y*v^?W@(^R%w1NCQ^`Mr=a^PYT8{#dc!4o~O~kcv=LaA>nI!A1#BJhO3z&wObE_>!nn+y+wLD!(9)Y&Tb+hO9JV z{0+j)F*rA03YUMm`~mX%eF{nJJxiyVq#mDi&nHg<`@KFUIo!84B4vxSnVPEQy;T1~ z9n#%Fcvc_o3Uv}Y&5J@>0>+iRAk3V&Mz5c~3>-~Oc%1i$YcM?pxf5%E7yS=N&lV3J7X+lmIyzT`9!oI-i$;V~7`c__ z*LEJu=CC;Yh}juYWY=g40Co9j`tiBubd!@Zx1E1upczteHq|5{DL^kOVlcYLC-X%V2(ytbs@kAhb$R z`VumW#Q8$}2m&`V%onQb4ofeY#soWkeN)%Nr25Tvl>fyzu8XgMFf+0do^ z+cAOJv|t*rVt5|fslL$?hmNb=hY3lH*V2#wHafqye)ibYl5N-z8uv!TJ7blrLMqpT zxjfoVG1W!12^VbMkzScuYFyxbUO93=$oN^NH#@tzyl}|W=4OZLOdh@yO(=(Qc@Igx z{+M7Cl;3+fb%8-JwTH$BX-o!ovfrP7r{>fQ+upC6nP7TBUaLWtA{Po+z*vzoI)TU~ zUvlx6`s#6B$U*JcF!sOtGVn4S~++=a*mQu#NvXPnx4uMyo^HEGjTV-+SQ zJo+n#Qzgn4(cDKAoj2X}1pECg+XRyTaxBC*?3VeTbRH?UCvG;$pgB6A;*5Tq+3(rx z7Q|Rd7j%MFm{J>rAEC|_$^*1zlnQ7O(F8?Vf$JOw&eby<^)>`C6xFtDKQ1J6!kMtl zfAVxVFc*5-#2Ag+V9zPpSu6ts$s=OtNPaGSdup1!m^`x)PCyH&^ElV#;O$&-t%1-k z?lD!`T{k~@G46SP3$naLNwFy%jLIfn0KUNIPgb3wnTfU6IgfMo`_S!6rD?atUn$8d zQ{Ar_ybQO+@mnW@<9$Ar2q#EKAm*VCxp-f4Oi_cnQd#2%9@SMRMbPNAJWcqvAH zi!5&SMp@#AcnuMeadE-S!1Js~kU4(JBFJ3DFNVDgEoEMn#*)(DkynKZvObGfmmyWo zNM_NLJR&i_K=^~^ZJw1Zl|l#S(o8l1L=_E zSbji1{)>hX|JwkS;yZlHYed?&1;&8{|Dd)eqe?dejF;Q|O`&fO*H-f127iSkAa@ne=bLw_SVzQ^St2EJb4V*+q)N7HRC+3vyxr; zK(&j0OieF@qoRy_B9JteW)Y~CH0_J<$)0Cy`Ib;~r^nuD`{P528x|x3#>4T=S=Ob6 zclBPSbSg)X5UI;c_3k{+o}d%WbMLg*Na9i*XVf5X)(y$0g#rqX6!w#9wLLr6XH!<% z`&%Sq`Dd2omvZ$~RuD`2dcNKB-N21{VP_%)oh{qM%o8;?>J{5SetrBRsYK&}0!Qp{ zq6(;d;D_{qZ8LbW4MY{(2tBQ=!_hG@S{bs5Qz?PssPCqaGyMWDG?11H=#O&zF%V1V z6TB{COpgOf&aOK5HWq9R!Q=a>z<}oa_sUVn^_GhC_4y9Dz6>roRK$4@@n*iZ90?mk z&0&eKWKrqcge2ZJx`cMrmd5=?XBWL0u_xP&4-S$*6ZscjIMUVmfq-42_><~fcq$-o&{P6x2Y}hLJJ$R0@?h4}gX2NMdhrhBxtoNkXwO8(fAudN zP^0+9?V?B9W_%*o_g&d7&(y(!&~_F5_Gi4_?H{{AlRWm8{4#Wcoi+2Ks(LU4+^jacc9M|AKPBD56(4J3btg>+o+=CQJ#khyvtcpVw&M5S)mptX z4KsNxn_EbrF=_s*Wzd!VR%&~=9b@taQY9-gq|xPoI!W+2ZX{%7Qqi(I%s;UBKJvUj zJ&JdxX=3vA}9>j_)qBBgUqg$P}g}w86_o{jMxiP|qJbCz75R%sn z!$BpJ-?qKaJI1Ewy6RP_=AIY!@JI7GMxFDN)wqv;^wvx(EP0sfu&L^0)^6C<78TTf zpHvM^%HeipWc^AXX>;nH{NgFRhG#**$)EgF7JS~bD40t*+^XanuT`{%p!^d8y(Ym% z>M)2^XNl!#3Gp+()>K+ZHa_Y7adWgRr4`YADh4GN`0MkM)yU49o$NVA?#TxD+tW!| z;~E-eJo#!B44&(zj4XPk^Lboj^uOZ%$I{tbtrcD({FP53OvrNmZq?zPynXXZgqtO& zw>pjL$gcP9ZI7B6F&VgSlLpjV*yWR;<8ziPQ*6g!7t?Y+EU{De831d$F!D<~;ZW#; zuAFzUD(4PZYRs_J`04D*llej&sTFAH_bF!Dt~}Q%{Tfqq z;q0WC`SweyG~FxML*}`FSdD44DOlstz9$JstmKqrwgj*-!sRF^(m}Hu$)zY4pO2!S z9~wN!WkWTB2dq3H5ALak#@unw!M~x1ePf_X95LFS;1CYnwLCl`vTPhYQMAC{(-`I9 zzu?Q;-J`d}Y2XWSM|~TteQAt;#>aQlH00dLbEGy8iaIV}+O{pBlB%qBc*^RiMYvQt zi}}RZ%rVdO3Y1@>Osqrow6gBR+y50(R9Im8amU#XkCKv-$Nh!@7S{e#y*Oo~&_I8G z|LI{F-kdEslH55QBtd08BQ*1#xCj zs=_*Lv`xjZP~A90M4`}|9VNw>?f!nBfj{y0!1_0456V3*dwTM=8yLo+?nZXzh;Uuc z4wH6EJ!eOffh5WA0JxUDn-`&3A@!wjA7!ea;9Y^+D}DyM;r4N?={=^jS0h9m_wRIY z>n3I%-o_CvkQk;D_}H@8CZDRDd$nNDLgWpzH5m7Wb|_0YyWC>7#%O0{s$%>mzwf!v zV$8dP+533gF?ql>mJaucviYI|^_0!ZNE2VgfC9JpIacX4syX=^FyK--`B#c?h{4Q! z5M^ECq=%KH z_Bj`Q7l&oY%U|%Q6Js{aJ>I77)7D(* zIKq_2eDQFyPyo7wd6-_vYswhJE&X)vg!)Dl(X~i23B~7^LG7pGH=n^b8=VOGEJ%*q z;n&43b^ed4hI}uKV(x-NO`(cbXZ26d-L2w$5~>TKtg-4MX*{UQ)X?;nODT%=<4wR?Qe2HQ=MYM8K7BD-!T=}kXWBNWspV`qZy{&2dZt%$1&Xx_~VrM6dQSQI(%O-YpFD* zXy@?_cL>qJq!gV$5Qn7R(kV2q(fz#|(VbguJ0ZI3(B-3R%L2RlHt$F_CvRJcdI&o- zCgPp4m;S%)=|?gVee{ldmxF)ZcK(`hk<8w-N;~4#j5q5Ui}!wIwJfi!RqE_8ES(_s zh0ZfyPA`V(cYJL!W?7E?)3A`dQ9>NVo-hkuQLu#q==&MR2y@Gr29wzP4-}DfXBVHd z@#nRPXig!frOl?R%h=;7+FL1Fsc_bVi8;;1Jv>^bDk;PQw7AN2y`N|H9V8_sUm#@` za1xK^j2sm3A+}C!wd?W)=9jlK%R%~_#a~n$qUy|NF+yzdrWQAynAz%{e_}mpbS-KH zqFx2hBI6>7Q~+2koKfp`AMM}hfoVC5A1iEm^BUllIW1oNEtYTEQSmu-b+k$;FQypw z#4Mc^>Kb91-};D%O;xlJM7`021_Nv=)xBAp?CI}KB(;p>lTF5xHX0grG{+5CAB6ps zD{40FjgF6gs(%{AqZEetyX$Z~%k#52LOck`zA)=2mbV^_yWwa|+5NX#eNDc)kdI%A zS_Q}*_)M}futZxvXg6jX1>0{7yJ9nGec)XQ zqbQ&UCf8*BY#p~h>Hho`<|smoiDY@SY!BYPrMnPPhf`{Pr?aD$i1ZDb{Q*H(mcHc) zd*C`8{MIKlSm`GvalWT`{S|Y=b{x%uZ7(U~f2KQk^qTtNGtF0R7!Rtm*P|8Z)bBIT zujg}(>`QtHd9)IiwDckGd&vxgB@M-~aAdtgDkTiV9{>zk0J#nByBTri=^ipb7NuSm zwbR6p3Ve86k({^Uez_;3g6+cA{I@3zKiyr0FMli~HSVrD2(dS^^EaQ~JJx`cBc`k) zlxbiXpvIPx(yEUSu7i?tlGm}~Hd0fLxInY{sX3BMvHm(91*Ux*{jv=J&VChnHGYsm zI=^Q}svd&q7)e+t$QTLMs>1N3`>9MlTd%N~*L9b5_N}itV$Nf42LY(_lD9%*zF1BV z;Nu_|;!NOuE8s$2LNpYNIc_4ZjSevp!42jdI1$=-3Ude;uI0 zxQ2hHvP3$(&VQ=`O_)7H*3L`+XgTypXo)Q+7X!`b=l)i{>p}OYyN(c<%SCAuKQ^v~ z^Dhz0m9@JQFr{8hmfO40s=Dn#HLf}ebw^X_Y1)CdlXhy=-UH^V9_P0$^JHEqAE6?i zoLCmQ05h5xGu4APrI%(V$SnBemxLmM{@rTG-Np*^HL9(T?@xuUTr9x!3noh|XYsI6gG@@Fx>i^FxIwoDDcG5dY0oqXM0HPQJSX>CMTvHTX>@2-KUlsz@ttN zwWHTqkmT=k+Azer2}hMev%D@`cke`QS8{wSrW(1S={?%0SDiWP4d&d}uX{z?7ksLK zC;qf7pt5jfll(HSTJ1>$bu2wBXfsXDfqV-$-f@AEg9;-fBlNr6CiPV|Yj+SR%G3A&(6;N*6d?rbJ z$F=8o7~>a@HhLbT&C@Jr(CS6f53uIWv;M-Bq-vYZD)Xu(hPjMp{nomknh=D>-#oF; zV`;g(6k?U~B2)`#h&*DH5t!eQxU5|xBqm=9__Yai0^t1ZB(xxc)%|R50=r)BqxnMi zT-)OOop>*I0b9CLc~v=9 zHR<^OWxRhMqiV+?o;4YZ^$myXp{{l#{2p0Eq5X(#?pF%~h%1h*-!Zw65n|pZ=RH0c zJH?`1^-;-9ETM@6aSN%s2yn}#uCy=h&!NH032J6c_BK@)c|b3xogaq%;ki?OMm(W582bG%36H%TrT2 z2hCq&0SbK#?cMRPnpXmwQQRy}Bw9#9=W#J1;^xPc-Qta1mLbsRGW?%U1m@43KvlnU zRoI%fNVB`ZnsPGw9rQ#ee-Ge`h-PrI+*o)h8Aeb!yCQhePgOWHGc$93yU>m{40f=E zR_!Sd^$(ueYuV!!S+P`u6hLe^SPmqKkLU8N0p!gte|ScY*A8{?pNN4}b#|u)G1iwU z8~HbJC0)muM`aU6J3koiQ1uh^Osp5I2YRtP7UcW(D;&mwjq?uQ*}z6=Ms=aHTVTeZ z>vuGilN2RM{nu1wCI$dF@UHW2R=d_1){17Ku!noPw_)w=wZ+Tvd|a>} z3Qgp_-03?l03941B0-DA!6~BgJwAwV!a$#Wo!VdG-K^%ZR`G}dt%s&#%y1?Di3PZg z^rfyCC90V=%y=I;#SrQ1^u3)Qs1KR;~ zF9FFaJHe!J+vq6Em##m#wp^EUCuy3lx!B-1@j5ai#&YeK%sCD3pesYO z+MqXNHchmEf64n;ug+$e$y}`>tFCaTI&<;yiMY76T=&uj5-AMr_dad%0S+$zV?L|X z&9yIdR{!S=JLVCEl{tez`H0ubXy1KD+r0ixBFs!ibvgN8rTW6T_kU2Z|L--Zvi6ZPIIF+!B*q0T6fQQZgZ?C1M8G9f#6OsWo(`(F=}g=h&@`M}lDd`ZOqTnxXds6z zjJ}iTms?tESFcxZQbAE*w*0GckKsR^%<(jT%5NP>MX^=RzMawm{%?u`Dn#rR+W7(9 za(HXo6)bF?=Mdc5@UYCt7a?I#d@?#OsP`DeaI!+&g&Bh$Dc z44*Puw4A)^ZlTEY?5W2GO3Lu4di~!Vq&T%MNs2bOH)t2th!D}y9JuBa<>cD^rRe7z zxN5{uDa;pOBq4%+jE_BE$>CCtuPwHoQ(6Bo#bO`@%9`XMs~xQ6xIZ_EQEJm2g0O%N zhXu_CIhKS5*$Vc0QLSn{%`qdYx&7pOczwto9&4mJAfC}>kS5^wkrgsD7Q(DE!V7f1orE<6Fe}Rehw=YRwRkFdSQXATqoE^nmC9y zDEwQ9nHtO|$rhcG3+m3sJ(pecF5%Q6Ux{Pj9afG3_S$vm6P4K=*4T=5`k4IcHn>+n z{x>+~G=j4A?iJ)^pNfFr6Qn)7>#KEX|JhjoJ>dWLSHplXGMD~)ijopQNA8IOOy>Mi z!kQ%CDkH4H{H{xK1&FFoz`3fxLpwj(W0+k~L@ZsaUod}c4#h#{o-_r?$9jhnnz?+K zQV!>KHu7&85ivr^X<}PhWRCLrKF|~ccFg5$<%C0EG&d@$n?13mo%pB&iK%~?Y^*tQ zl+(r%lX99w6a8>@$C+VAw!}ZKB4MEW)HwG0F_P!YzdVG$8~^{ISp`EWLLj78e~qJU z6@Gmx^*qMbW*(Lxi2tyU|DDr!XW{ji6{bdB!|p?0>stSc&t>>dTj63|>pa{?8WjP* zIra5;R`hw^?lwWd>kyvr@7ikZl(^7oV@{TdOFQdzmcx18zDQo)mM&$^^QOrJ23q}T z0wCqBGzNkqSIP@!C$>$kze(-rd3~$j%u!7<8F1xFQy!n^T`^NX*Zm8F0g=)PfGa`*? zGQ4m0nmH~Y?xAhL>$LvK%lcPV>YctjdtRFczuwQQK|)CUT}_GW*qM~W(hf> z!AeAn%r1llIrX4VmLwzmrIz|F9Y4xS!=+7Lt~F1#snEdSBnY@7-?mWM%SLS7zGbOR z)wbk051;+i&}`G7n-W&F?zx7A5aDU*G4@x1q!;Op+pnBYUY6QjJP!nl_6PHpjyf}G z!Zvbz>oT$sOsXz60~-#OKQ}zaHI~@xG;JfjCI**ljf~#!@R%>Ddmrw>9G0sOnvl12 z<~Zk7>AAulUK`zRDi}ckEx<@CrSQ_9NDa*Yu}=T}pNQ6`RHmzui?jq###Lx*Fa&r8EO(8RAK|5uCUmAmF!#%GWmU+ zz1iy!ytC$b0u*cb#>4j+I?38zjMi)OJg>mdN$B5+qtUyqfAI2^1-IAB_{<-39C?sy zaS<4vXUJ%ZT-_*HpXm*dfh$qf5LS@W#ZoUf00S@msLM~ZH$f4cDvMBl)6Qp_m*8gHX68C z^1zu-q+I|T^5v6W{pGEGYtuy2=HUo|5}af-Y9jy0ZnHiSP44j{32pn8(bmzdY#(b9 zJSX!F{>%+a7hXOuHULgQY|KL=X>9hNDoxbTPVr+myIq@T+q&Q#0@Ba(GT7GW<#xUU z6W7%H^hcU-k`#YEwx}NZRZ<5wNc*N>ys{|dS<0@{OxFdY}gPcCam1}0~Dd|zD@K-cx~Gd=W}H z%hm;%msRF_p@;m+TFc#A|9=^=8Y)BSSEs*TVB@~4Nq6pRp0v35BE9Sxd;H%Qq@}Xw znxJ;Q>7uZs+(8VNl9S5;P9AfXPhUA-))rT&7k=sYl-b-$`_wwV+_DPykRSh%JtxyNMs%YnIWQL^1N5O9gA+avG$A{-S~$_Df-JpY+uy>Y-ApTVJovO~bLD zit4sYtW*)k{d7ndzF<7I`$#pr-NM(M-&PJIJSiH+Ey79WsH=E^cEjU4=&yCPf92Bd zr7U_|db1TIBDUaus{d}uow?5CTFZ(5l}@$(>^qU>kdwD=P*4qm&Zj`#7XHBN()>sF zV@fiDXIPukkTMp_^U_wH(~P&Xi_ELK13khmqj!XEYBJC+@-;+z9l35yJRSLL&O>49 zkdSv^{%L!hCi(N9pVzIp^!s4gY^JS}^~aJ|0w}`l5vaSH-A;8L|6i272UL^MvNjAV zARr(jH53&E3sofaq6mmmMJa|}MVj;yAPNd91XPp`5kU~?AT^LsB%vnK5+H=oBfS%P z{@}UioNs;i+`GPiuN49zybCt7XP$Xxo_SFVJC+AX{exDvIGD-l(stSBJ4T9Ns<1mh zxpMj&VP~dx?)*G4@8r{VztXHy?YmFR^sX?)jbv6vQyk%AO0;|GG8mDlz#8@Xr;_A( z#yC#Smu!lVKNN>cLTMO=zG)O)ax_U{)5nodF^tc3#TJp|lXOM8u}c~)Id@@&Jg`Au z6snUT>3J~F z5Ls5%zl?vFpIp{cB*q&^g+_L*mFp>=oU($kF#;mTi{Y!v^!7E36UyPPqBSbMKkd(j z#ouY`Sn|S8ekzOdCf22`9u=u1e~B$8Z1aU{{-BxMX*ve=BZ759S@)fYv-t_?qU?ev z-jg!8N)IpAs41n@m?4^pl*ZON{L*d2@T_BjjhRqG*5X4wd=&yTaDHTD5A=k|0$Fn< zpR{#8A8l^IWAF_6_EvS0&^Y2OryFa7)MC(xal}tkHR(%c;VmjieWn-t;hv|H556{36H>D(HL9W%; z>^`}hyL5w)vLP(g(WC2srN%|x4|$b#ZFND_Fd6YN<(FDg879+K#22!cE|t9`a~#^} z=eG9MX{K3gi6}(V$1Jv7(I|S-rPxJwhWTp6Fw^m7Q~d7U6_DWg^^))%>@7P?7+v+w zeE#g`ZACGbFJeTuL`eTj>--$A*&*BflBC~feIu7MJmR302;d^GM{jg_Ymm zH|_d~OqiueOTM;Y@;Mqr%a$R6^bV9%*A`?|WzqRvS+38ClxSm?aqLWLzWNu`orpqF zC6}5$Wi3B~V2`X;1P0_ixH{KwB)62N#y9E&)s>8e?X%%E_O4Ym-?dzwcL;03ghbj} z-%7~BxYt-AMQbiC}#`-4tm z2fIcGhXv+4+m~T(RCQ+{slAU|1pD%sLeA;0=$zM)Z>wMuY(Bk@BBo^8P3sgPy(*GsA0>D*S%G z@`_RqPM}4O*s@YgwQ4f46Ip0)`<;-Wo3p7xN}dPF81MOyvW29&w;yz=!D=+)d^50q zB#EvhiE?ipNJJ=ckW@34y$_)=dFS^lu_r1;6l1u&cP|_?Ms`(%9_ebAtXvgXA1x%i zbACvgDW7VKk(+%ZRTM!s&=EeoWYm4_w z+0{bwa?PdqOTAC}J%oljZ=a;j{sQrEhm%~k4%%pbW`+Fb&H2x0w!V-4;{jUmwM5h4 zi!3EN*`prcc|UdyH$2N^Z#CS1!nLfz4j`2EdIr~F^pw<-ifbH8Z?Ied4>NqoD!k@f z<}}iP<6ixhdylp6~MbT${hD-tvDQVU(dgFo)WweCD8QS8J~Sd3aDDc4PLC~ z90P3>9PSv5ff%E}w+4Sm+BRyugdZIUxL4FjL?o66AyVt5G-?%cqzq0pITMz!@vNoO zaXzf8SvIH_yb)*x1w-UWB{lrr4I?UNkfHSNjrRa0$USFY$HG#LjHy0_I_CksxFfuW z8C)8QOhLPv+K@Ytqir>4)fN~+BSi|+BjkMOo=5EY?kHt{P&7CPJHrEM9yQXK9u!|8 z2T7B<7WZ|Hdw<4wDboNFppFKRl+Qrq<;K#w3jOenZd*mK8-RsFl2-)R4iO$sEUJ)| z^XhYDBJwwAhIrx=1iFDCM6I`=M}2xUf*lN34SV`1N9}dyA|1^T^>-h5Gh5^nh%Nfa zzv~0jzkDsOarFoiYWr4TC zBro+7etQyb2ydrhi}QIN~`) z1^3z}fyG!5JPEILnjb1WT?i}+NMA)wUMPZUl?R-t9A@T!NI+SF9*hq2q%)TaO!(|ssjB!H70sp|T=K&J_}bRw=l zL`muXHljD*ie`oP2xhHdh0Klwn8iJ8Hfg4U+L*b2w0)LiYzt6wbd>F3I@bm=6H@)? z?X`G&=@Clp$zuO9JxiGKgvpqdqb!kqVy6|{R{H6H0d~{xHG}Ua(ZR3tT|BmY*z9CG zePEBi`fkHD4fmd$6?Owz zbCTvTKb-G(ch?cZb60wZQB)hwA7YO48|8|R#DwWpgc6G!YU3At8JnK8%OyPd`m?e6 z;yv~y&v)@5!F@lr1Vk@gssQHUP2!YGI9!HJM>kf7qN|h`54P9aPOXpaJJX{ zu+`Pv&6V|8qZFR3pqk0wV^DzTrKPv_P1Jp{Qskj^M4+7)G2Qz`p6XwG)nhcUi)O~&93=7HEic1eBLgQ1#&a$z+N zk&X$qMBY0`Ul}CU=~Y9$>t%&Cd#r3i$GsbtSDM=sIh-`z;thbr6hY%D>B(4agMA)@ zHXg8VJ5TR7fqHdo&M-RtLCtNYO_@L|G&m~{udvf5#Jh$vaSRS>N!V!?f^Ym8CVb3q ziUUWqwq&rr30GU39!ld4=3NOw9td(oJiqA z2d_@njoZrAQbtr1$qUKlQKpI8jS*$6Srg^v=5_|W?2XG2UWx(z)8F=V(#wXc!O#D^ z<@N3P$o)xS?t@U(3N4(K%DK!(Gd%M<8PTLc5^1Hs0xfk09p}!B;3-b8Q%z9tBwj=HUv|#cUY5RMi37uJe;>4 z%d#2&)2vd_#U5f|Z0gz_lbWz7t*&$Tu9K(g9#m27!1BOGOkzM6o-aRLXO6{Rx+LkD zlNlOACNgMa;I^yV{$0IM3NFb)sutr4!L*QiYvylAb;Hs^D()M)XJqbBkn;m-{esYX zPhjEeTrSVP$3P-OEy7me*S@@PM4yMEpldnq{F0zx&@fbaTUkNpq7A7&dni}5MArT{ zF0wfPacKa>Ia8isheXJsdKRC!f})@`Jva%LO;ls3fwGejLugJ_E#dZ0psBZY&hA}8 zoBP|z<_UIaIbWhbPc<%2tj+uHC_Kb@KiEssNveBD1Xh!ZRNz&&tMh!u+P2{rxzq92jnd(P>#~GekcbtFu?sg#~e&!yvbG z4>z67=)cX(OvDrv<%Wh3z><%Z7FmwMdg%Sh53=^>hDSHYuA3Ph36ZVVqi-B{n zo!w@&`7lQP!cycc+j7Iy<0Oz)O>60FGFoMVbT8tDVg2-7Al4Gsppmp@x)7Z_vb0AJ z>2N@7N~W;vZ5F7YHRG4nevE9o?$8ni&xvDnW_(|PoEM}cJ4YL|y*xujqir*~rhWF; zd+4=othf^wn&0Ly{vMPf_kvx^?&e$3!rR<$-!ntc=#;{EFj-yCUQ~>ERE9&Yvl*wL z$$qTw7kZM?gCvz*21AcSp=Io-rlDZKS?i@R;YLbF)sch^&XqPOUHMaXYN=Y_SjLa) z10CO-TmQ6=F2^Rb$I~xfR~EKzc=1*bBW|j$NRc<{czn4%>O%BHX$Vg8yJ~CY)w6#}4XY=>9YU# zDyW9u(r_G2)g&hM9CLV{Z>~A7BpNxvw+;@icgN6jVH<)25uLAeNtcD_OJ;J)9e2wZ z8w}zdrf)wk02SL_c$YZ4p=8G+>@f-j0}5nb!r0`5UtaOs0DBT}hy(9QVi0 zJAQ6~-A!9Guyg4l@&H4c8c^$6bv?=i!$626Nxw6SGln*)x8CZdmf~SMvf#iWk4OK+ zQhoJipI?!Q0!8>JKd}tVK!@x4tUGAfFM8>OLD13fmA1Ph3N%7q zzL+|Nk{SOb8tmM6O}{g&@#vS$e?j+w8ytE}Be|8O%*vb50PSW_hTStk|JRRN26b{; zU;N-@e4!@Zp8hJ_vw;-cKp3vMcN)mj7^+Rxk*(`Xh@Xp&U5Jyl|1+Ey4a6r2Ok&1IIQaMf zoPX9)KHMv+bRqGC{O-g1t$1U1vr_s{pY{-q+0`1(EXi3Ki-l{XCnt61tvz9 znomJkD^nLwRwupQ;C=W-rH;KUg06q#9s+VecND%N!J`^+ZQsjJ4lcA4uuTGAg|AdI zftQqC(LW9_BmBDmeI!@p@xoY{4Go$9BP6{Vk*=F5Bhbc73ydawYNwFW(qTJ5GW&2A z6}~N+r8s4pGzd>r-G>TvvxmU0aTv~i9_-QZq@RX}Qv#2nCKCm5sbEbJ8w^mt;HTTx&JV{M8+Mc?6 zc!evKXs@AI{x8TB9X7^_h4c76J~M_mgKc^t1nwhte>1+Ix)KUKhUBSpIGBh{jT)g% zy7UY&aLF+K+_o~=&P(l52={_?YHKlG-~LIIO)GHlAK{H%nfD&K>|z3-%iJ5%eUfTv zGkusrL+MO^9T!Yh6LYuRdNurwLq3Z6H|pYJ@w*E#%|lN?HQ*9}BoscUoNXqp>M}|b z+FwxgXsP~X=sNK*)Fhp1wga$Z37~)W0tC=kca-}wdhji7 z(V35W>E{bgH5%_XoSKgCCKx_UZgiju7= z*XO@t_?dpSz^3{PO#RVP2xme=(1*&;-$I8g#^pcZGlhvG%hEhOs2Jbo0+o%XKQ$JP z8y*`()}27=9+^`|(-|x(D5g|zR~3!uetCL7q6}Y`|C=!zhHxJ3#F|P6Yc*EX+zQUNdxdc7EA5 zjR@?k3kz|&Qc4O@@H=?e*%irQVpHd!ePE9+kd^1cJI2vYs@e~B#{p*0cyUPL{t6_B z#*~40)cr(xZMIo53q}5&{z=?0ABZLs1qZrkUB%Vfl68~T_cBFpqA6FUS&z1TX5I;q zts1i(X-#B>qbZJh%KJD6%OP23U=uq1kVl(G4- zv_6k6nj^AAjC}&N-;5##6Q^=pkiECRuC#{SU69p2G8=os71&;^5)_2M>DbTJTfZb8 z>I7_Ly!TnRjcR^1;gp_L<8uOwNn^$RdO7#$Pei#`z~i%K)#t+!f7qTq2zbJ@;AVIX zr+y0VvUvojk>-MR&KzloAr;cmCHbg9S0@yk9sl$D3Wf zXvaR*z8g5WlE!}=&|!}?xf z!+KwA!@)9bN-J%oY>;)6iJW_|{eh)NzaR&)MfYGCp6`Q?V*`s57dEVq6qg?cVigcc zp0merswoMnoUY&=U1mvHJ~R5Osc3SAV@uuTbgRP4$I@Z#QT?03A8Dt^pHV#)Y4Hln z<1qjhRh3}1MP$0$uzPRsm3Qa}4}F$+!WSX)I8*j0l*Vv#UPJxfPwD4JytN->rL5bv z9!=J9{fi(^a$e)Tu{MX&X}r+_D<1R1z=^|7qBM`J&5Hj8F|V7TS&n2StH$hTIPd$g ztQz~uL}W8bdJ%(^4oT^iz7o!{l*X;^{+#89+dl||jo&l^;iQ@uF6P*B+=^=PAwOsn zLBDtiUXeF>E`MfnlF2d0%1!W$VGv6Gax={u`nNpK9`yw7K*gr>Q4F_-6yq|OFM-zt z`zJ4$oS3K;#WJon2LKXaJK*%NZjKe-cDJyHPay+L%qI$nSALIUwTR-!FpP{Kx z;8&pg+*QJlq{A2(EJBDz&Mq@$VBM}jCX!r9F5Ud*6_iQ^pQoku(kDRR!>xRbHDIZv`7}#+s3B*BQK;?s1!OG9S$(b z*&F&CCL7KoVn8gzmUchJx`u4p--i}CgW$($*k$)b%G-GYY5~=50{RUV5JmN~VXdmV^Bw+!;MHV@CM(GZA@zQX+)AH}UevQSG!hov3bj zl-Hw;okorY*R{}pWnEo2-AB%uji^8J?9XWrsbPw$-u|+EBhOI!mP6c|pK8hHsE-4B z`0^U7TIzaMXYkL;b|j9R=)D_yQ>fA^XnXxB>|bh$tDj~WoHWZw{A(E!94$@m=b!fY zcVF4d`r_!ldb49-smVPGQ|ZMwC}+<*dg1Yc|4u+;mEuLxVzOK>tqlGf$jrs0um?O% z-ZObLd|4=%71xS>FBfq(zUO@NM;qPp!&3|8Yd{}Y`;W@Mgc5TOqpc(SPzhT7Hi9<| zTad$Riu;>!(32eqgP0$l!Ac`Wk9dO=BKXqc;W8@w?ZQShzmj{{Ro+vMmiswioI)`Y z-o>(*A=Q)CVB8l(UPW!RMSnhH4{Q7(WASV(wf#odJCDkBHZj8|FWZb|{WSumJ!ik& zdS%@{l?-e1*06Xx7k-%v-rqVn*rv^QgX#95gM2ZsIb`#P()EiQjt&gL6`cJS2%pQ>eo1=>Xi}V>QUTBf)|s{5)2)o6a_{};>Eww3N-if%hv~aL&B@R zIVDH&ji?<0+71kvd^EiiS`Ly!e4b_hNjU@;lW4WJ4@IMa;&RWZEQ`rT&#|=(dzN96 z|Dw37)(5ez8_Tncq#NO&hdowHXuSR8h?B~W&ej{8 z{mm`IAD-``bJZNDUX%r(o!_0sUK=&cgwQyMT+xkcLChO_XFdqMk?Q&_tok}%C982o z|5_ZM)vY7eN9$XTh}+T}2Un<*B{3BjAJIB*M%!NPs;69MSKJ18jLzDaa;Jn)Lo$M> zXIRGQ40n3Gl|nWIZAhG>oBREI7L#(`qiq>m=z@X6hDw|@axO$slw;+sD}EKVq_Doy zwh(-y$oK)V#$#k<4$y1g&7Ydqd#Ksu=guHWBB~l4r zmxx_i{de%uAdqY9qYHS>fS*vr1vP2Pj^2A7)hY3f%go((`t%f7)R_n%@pS;>Cxd$T zQXkw|=vKz%3Q*3~?+Z5k0n5<&Ocoo$bm3WsFQ$I%I1jygMRAJu*|0$O72K<*wBB6W z5rNk5qXm)D+$eJFn)%vPx!={4hkv?=A}}7FGOFH^ZcN=i+V2TdNC8 z{I;((AVm&G(|T)LrADDK*d%$p$b0$fq~gB?c}R3myjn`Kx>`B~rk)1(QhVQPzS6}8 z5ySuzjmFJ6@eIFN1}p0C%Fz%9+r=WJZyU7q!=50wYxnO$5nCj!1ly;l4f*^r z1X4Ze9;fUET7PY+8n#loXW0<1PyDAFapB1l_>lh_wWS`r31Nr<%h1O3NSt)eklZ08?=;(sRy2~ zhbHg`umL*=TBu<$fI1Kp_I2&U_l4*Fa6+~sw@l!<&gF(kNR&L<`b~}j@loYlvl+|{ zOLza_w9AVCJWyb2KxxaHPd#vf|5R9%=+0WGXE61yP@G)AO}n^kJGLDR+h6mG)+OcW z`ZjT6*GjMS@1Bxz*5a29yRbD2q3?|G9WG8@9i^2YX1|hm=dz>fz%|xG-RWp1@9^$P zf!Knf4< zSQ*w2IZNykIiI1yhy%pcPd3Tpl?OdvlPDDF;3*K7}WVRC}BS)F0y*G*;ceJ zX+x4z8Qr@U)-k`LSJPnfs?bAT58%5$lp0oq1(`GTa zJ#f+gjo*Ww`(uX$fK_0}<*Y2w0q+krL>(8JqA*~X+0sZY@XS{F>&Ao%$Bwws!s%1e zK{g$?U8#|WYoYe)P7-0o~;c+qcmX$hKTksj1_U*Cngkr)t9-15~w(Jd}6| zabni5h-DsOs-v=c6njUHy$xe%%+}#0C7hG``&SXB7pE5Mb9R5}IRcpcWf=iM1Owbt zdXC5~r`Bfecy5MlqNZQ@QjStS#eP!LN5(aA5j#}2;QgpD7hWb3;1bU}hi^=zft0(- zXZ!cB8t#O0QzJaC@n{Vn^MSDr*&RPS?agH)?np~1QIq2iS0CgVg}$7l6Vt6(Li9Kz z>)yt)|LLt(*J_Js){s(*rAaneer(Tl5+E%$*0CPuz*nr^`$}9K^(p!4b+LXJQUdSt zK6|>7vm0@X%=dh8B_yyge7DUA(i4t_bdFNQZ&D7OSWQO~J!6DWvf`O7hF65#59@li z$+bB)6WL^v3l5UMf%5AQ5w)q+O{U-XTTg(r{V@&7QFF2Z(AtM~soJyv*SbDOq}u%s zzp_cp69;V-e*x9mZ}rWD?KL~7gX*_!BP96ujY7#s!*~3+kDXI2OE+Xz8A08W-yw=s z^q{Uh!e({DO%Zlm%BV1RLi%tR`Qm~S4bq-!s&HED*u-QuWD)SI2fOKs8c0j=LH2*s z#W$&`<~z7*?}}Yaw>7!?*#F#7h3`Z1Ly6T0(q7L)nobYTr z_v{DGyw~gfX>_xBz5mi3?PQkD8=Z3xhd-Bmww`$eXQ`CF__y!#t3L1E(t-Tm(&z}6+Z9i{!HP1E`P(FnG6~W=T zC!bqT%Z9ygKJKGv{lFL+kNhIsVEf14EKo>K{EaHZw7_3{m>#{B7E|?!p`Q zoMnWb%BbR-#h=}heJ^U41A5gn!nxV#U8@!7v|Es38Ctinh?9F!FC#@B_3%kA+X>2B z#gkWFfei+V`J!UjR4#}gJgo=L@d?I!&s<``wYGA!4mQ&l^*htF4gd2R;i&|}G9~zY zZ=X;gYU7wwLVaWu-z0~kP!|U-Y~Ih*d|v*dfL@9^_;?ZW3tu34elDcGK3KkZa z0l7fvg5m_%%kdBGHA zg#=Ubn>Dtyv<&j4L2Awa7eQUvrjPfr!LgYvioX6PSDsVa7Kg~I%D;FiGdhcQ)29F~ zPPcvk5*|)U!q@bTu-^~SoFAflX)M8|Mw}<#put^b0WFw%_`9*2Pk&#S#bl<}d;NOD z=}shwCa8X_x3abtg1`<5O%2UUS?S9c0RDCIhU@1W9wEo;CBzztdDU+z?h^aLp>(e! zMHnASij7 zwiJHuAsTTt*sJR*MHYC*bWW5Dj#R%6n#s{D7@vo8Yv+gnTY4TbZ1RIpRAO?VZeI-Q;_LF+159V+E_iYifx4 zGyZsati$t@)7oD?-*(#+R(dvQn@t)7aC-T264q?jk4N9et%5ZU#%k1!8Ym~+Ss048 z$`Nff>WooqXNd5CoQ4L8&yn(mGI%yzo;pX%aLLn}aR=*{ax|!e$o%%LJ!| zNE~y$6mOC92W7h0d*c0{gkF$)((#{6xjt;S!_XiqtycP)F`fdnPu8M1Xu2h0e#|^Q z%mg3O(vYj+``b{Y_dE8cnHiF2McrRniockg;X<=nkhI&98!e9fd))(6KO3}-wIMAE zy~r^x@Ok*%Bx^AG+Q4_M;uRnS2G6Zi9tOZW>t9Y>F!m_7XCi)gE^dn^2IiPl z8zx(WjKpmh3~?!TaG6tr{s?)!6G~&@VruXtDdeyZ@Nr80MnR>mV`O?!+monfyEO~T zC)#yeYpk~w@f!`7Hy4(r4%9I>(D14q-1vuAg%=CnHZxM9&`cGvewmq82^*Xu-;P^IlZ0}U~i=5}B@;-*V z*t?ldQJ|c0@3Wd)GCMv)KkW?o1ghs&pPlc6!e^hv$=hF5oPW)lvICzaf{7QrswKU4 zO38t2ft1SXa2HB4+n%zcsWtfG8Ckr6F#v0P!HDgO-2<6V54Em6Zq+e)IP$sgUCF27 zl-524lnMNqcII;1@N5ez?aTI1t#%pN|8yW)2d_)a2nQJO6v^A4rey~I^K#Q#XK-(S zEflO4i7E3b8;rJwFrUn`*CkxtS+HM|4MrKYWpC4#N}_1&}cjPDe~ zm_R3Je+M%xY=pbs>~^x$ry%0z=2oCX$3_ifmESWi18HVk!XtBA4J%iFxa-%?Oqr3z z@&#vsrzmdc`ON74w+NE!DGT2k?wE~h=F6{?nDZzCOtQ7)&`LCkzaAL~9$AAZPhO1N zku*YRd`P=Pzp!uNzE;ekiP`vrD}J|LQL$;5@!l)LvbZ$LJG^G%RAlU8%~)4k36@2x z$;WPJ7(=H9**+&v1lwJQ-?rp$RJfMC_Yvvvqu%j4{Ei-T`qlz%1R^=HGGZvZCaZNg zx6u0>JH}rWg_>Bh69Jy~O}9H_h)e^8@uYt%ApW0`B=i3{lJu=~|2@O)du9KQBFC}i zpUX2T+X$wv?ahDd=~+KA#=u&^;n$n0<)sh0!g|&vB_;7l?2+de-pxa{J2^^@YpT-A zGOYG=^7D!Sj`b+^ic{GW-yb|5c&c!uKC154w{XPym5u5yJ3;MZy0Z9X!G9I1yy;?E z?qz{*l+hmKkyQ23WWT}v#B{(RNdLn7A7OJJH;P@0#o5?fpWSOMpHCRbz& z=IHFN5{5A~&1_kqc$v$B0cXsnj-^}2>q9*1)}DKpq_o$^!=Lz4+DRPLq@B&5|Mhf) zu{`59m#Oy2SNsE->7vAL^b;)=h#uD=Om;Dkw zifKW9VcFYHLlZXK88I|G07u z*1yuZU55+2zTYaXp&$PwvZNvl;PhHiMi9D@)0G;H^!ZYS@rl%Y-c54@6HfpEgKVXh z1-RPfavbM!&$7yBvVl}Cg?mX_xdaXc90ibRx9~JvLR-QO-Z`C)#QPKt6(oLZ_rFQq z!<3j#c-$oY3V1-0|EGogr{})FX*RE>Tc?ZDzRQ)f)er5NFyiKh7jAl87+R8A@JIH< zcSUt_t&GN0Wso-7FcOjFXI=dl*7o6cC14chesxe& z-{Yzs9(}wde?8gkQOS&)_y4ewxrd$ktzUqHKET1-Km=wSesRL->DikBt%W$|AIdKu z>Hl8AN7GMTo)B1ScgXQPeX_1sjHd|pDtaog4wqT;R;y|)(C~o+*S8PhuAdEs8lFr0 zJRM#VTkO6O5YBg|nx^2*4@_P4zJ-5e)4Dex{ynpqFa6m)LHy|D#01L1Xv}i?SNYWM zhR56avHabz^kF8Px-D%3Q%-nRUoi)y^$;@WD9(M6{Qk5#^)bgy{(trY6dmkbEK#Pg zEJrv?6=vWIcbhd_CU2Nm`XQ9!M*?vqBAJ|PXWy9KW=2MRtKm_Zcg)>BGIAz_Iri-xZ3XHCGlJVykMY zT@`CDR(;RYRgZ%nG}jF5@o4B*hN7ZsFM6N%37`OS!wqf$7Q|V_SXvk}U$Tw!$GSGL zf`!4UxViur!N611y-Nsa6w-$_YhcD_-P=F>JPVDRwu%R`&N4>isXhO>SSu?#w=X8| zO7<-uIVQgRpS>Pd4V=4&+3N>O1e}cf|D*U@n4LQ!B;iN`BMWUPK?{_C{29`k07MK^Ijt--lQKN={VTRr?y5t zz>~?J&jmKl+Qk!c#OtE<|8oe+g?8%Nn@IQntTz0ju>2iFNhr$^t3fgUV4Uc8csYFa zuE*pu(&y~pSz8hRl7RYohgHde^Adin>i80imP#x&UH*!2-q$mooifhfjGw&gAYX)` zr+wdVtonwu&&XuObj+-(a>VhT0z;c)qma=@j2NjoOz*eH(`paK_*@P0#@dUjfOFpg z#l#_*(@VL&IgtZ;vtsfIClDrN(gj1I^Y}FXafLxEMXxtj`I8gKww2?#1)TI2ZE#1! z+5MmfwD0{taOzbl#U*!-iJl1!3aL{F+vCuANM0pE6{dz^D_YKS*u1?|4L_2&ym5sn zulms$4O0G(RF#bCzZ$}Z2nfBm8U?sv9)+*cfG<-6wh7^&y#Q>b2M(aRyQ&egA4|PC zmyo})H2*M*+FJ96sLvs0TBihGY~)a5bsuhzXp5`Sa5#GQr($J7uq??T6yS-ri3%;A zDTlcddae%~n*T>DR?bj;A!}lcXD*wJevvu;G_TU5q0u0+6*xklT3b-%qiY3-_+}Ag zO3`F=&&JghU9~8=R;6kN|0G{%W=w0xqQCm0_+^X0=_urFIz`$}%k(;9Te}zC_gq5c|wcvaQ6tr%ZtK1|^E zxus>O^j<`@`h5qa;hl=np#rZ5A>&ZTJ$3EK>4#)6NDw8fm9BC?z~M;iBl~*~fW+8- zL*yq`WYE>9`h4`8Oqez%yl*v9mHw&z}i{<;m@{L+B*mKdZH z^{~VhF^9^|7u2#XJ@S0O(eM#6suB54EGz%bJ@jmOTa6UCAqwasnQyU56U%ChHtq2D z<^!ks6c5C$BBq-qK=qd4Q5Nfco(I08{0ngGlrb zA2aQvk>t_gVQUNJtEb<*xpUc}^__J&z~ox>wEWOl6rW>k@8z$hVzSM5r?8iSk1hvl z_TqVR$|KoWEzWY@RgV1RJWNalV^p7uYmo7ZicQ;^GzeN)^rgW_`k8tf z3y$Xm5*HnS!bMiuFO@Iu5i{98= zeBlDlXsgng*W$U5(u$M=7%372ags>pt^La6N zq*MuvMFFCck>R{FVWGPGqwhDPMwy8@r1)QdQig)NdKk)$VD;g#|0C3tKa0pe{|U~RmA+)vYTJrv z8j71a31OaYUG>n6uE-*M*mt`B=mP+FB$jRKn1izg4bWx8@11*5We@N<;C;2P_8x@s z*^(U2Za5dktks9IzxI<0y>a6SBl#maL#{XSU#djI*zPCy=l~4# zn(D8Xd9neY+rumU3Ib<>Dc%u6$3X_+-dvQ-FYj>M6gUPHoz+R3*lm&=QCM#$WgE6GhCSHuiU+8tsbCikDhFl_oR79(W39jG zc{g^t>nDTeV|irA8yu;t-B-QBJug@4u;uznVwZfC)_YejK9&S<+$)8|w;7SpwG8yZ z1liSr@K_sN8s}#&I4DOVLsOxi?wAj*%i1cYT@W4hcGtr1YqTEGi{APvnqJ}TrpFum ze=V~ciJy-0T63@A6i-Op&Bk3GNZ%`bJRu@-%-7{r1MSh6+G{ zoAQ1;e+I>a$7RzOhbP}R3l1J}>PV)vI68{^X~V1q+!VHU!$vK}3W8FSVs8FPesB++8hH9rQDpj9>cE#C`P^J#tOU8emL>eV0C4G)XPAAsbP8R6u z%Hkr@DXa0{N|7!5Ax%H+N+VQygYBQk&#>}TNRS1H_1DErwf7}Ky=4k@cV%MAMPZI^ zbg4oy&+n7GRqxQ^lx+VtUv$oNgUDuq^q=&gGt#?CHYL`y!I+X| zxXTOYv7&-rqoIrU@4!uRo}XWpd=;MKcX!TiYSPi*{4|5cRWF-(d_(g?P9R^5L96`< zLY++QQbu#?onS>P-0I}F;J2}LoHk41b z46)UL?R4A`#YDh9Qde-1p=YLN`10_;Q z&HbRM@!}!@e1RACJJx##t#$VX~@2ld&R#9ks9b694asmB(kA&64pUv`mbp zN+60gQs-p;%gSJ}(}W0vz1^0>+;2c--INCb+WW=xqR~>yFIihOi$qR^ol>2^Pp;E2 zqo1bT1-cWfay{+UPqCdNS89ve&M~}ThMeJ<@(@HD+(9x%87NS7D8=O__i&N2qgL>^ z#)_V&nLT#a!MHn-Krfv@wv)Yc_id96&3NMtp1jX|fV+BTl_v%gYnaZmCD5cDD^SA- zICB#SHq+P zL3+Hv=kqxajnFsuq69I4Z>y=3vQar%T<)$9^^t)3|QQQ#VUf)@51+ z-D_QSO~h(YfTGJOO)RcY1Ack$9DXTbI|)l&&Inz*b_Q}}=AtjqI%O*55;N9Tj)evu zX_h&0+A^{0UlCF%x%4Ggw-6_ZTkpORLP4?aY{07&y>BquP;Rgn?X95U+rD9|Sd#|O zicHU*PiK=S{_4+ks?!=q?^DG8N85Wx!?m}4<3vLAB%+R*1QDGWors7dLLxe&MUBqrZHORx^iFi5_ud)Z z=-mtkgVB5UPR@Dm-*e9W+|OFS_mB6xmbGVFGqYyz@3pUfeLl?J3iMiYqfE*@I@|%j z5nKOlmG|~)d@=yxVRKnd3v{KAtdOl23tc6V6tFDmQVPt}`!A^iRPT2yv~yMYGQ|`K z__sQ*&^3N&El(7AkHvBy04^fjZNLIy<*4G-PmGT~F=gYY=Fp{j1O(RS$tT_WfQE+Oqf1rd+gH@dM>);6IKSM6PKh+zeCo#Kl5k(@ z%^IBQQWy;TS+=&a;-Y>4T8b2sejo!GeDV3uayH;@l=1GEV)~R|Wf1hm34Q0jHlmkv zOwx3I+PT&(yorrA5ryP6JmbNuM)DF#pVsU0N}OLJNp1-HY#@~{)Vzk9 zlP_VfUw;qZ1NchQN$3{n-{SQ^lKPYdLggkx#(%q3W$X{c)9cWQJI&U7Dl32)#mnbD zSf-SSU)z%0qpAjV&5a-EoES|7weV(|ydaaz^M@C`JDC}Z}#cbJ}Q<}+_r^w+mvl0?(lim9wmeev(`A}b4BH6Tnk=< z>kk}v+|6FN5^<6Whmwhu%*;1(Ixn|MXb+#k{ex7k$sR_0N=WhQ+;ER38*qt_;4an} zOpPs;q-{H60M0)eI2R3YluV=CoSNhLJ(K%y>se%=ytK>4(74SHf*jb=gD{-6_nX~HByir&t;CK9@ zaq^eNpSml4dw@%{M5dOz0nayVw+(T7z{U?1hiZ46MfncPM` z&g(VmeY;z*iQe?7ro9+r7y7(x3%B(=pUK8CGyR!UOpn0M39*bNj;ayJoj(xNP4akj z>UHo8iB&Qdc(q!cHVh_b8q7(BT$?J#r{aZl57>3ot_<#}hPQA$uRAu~SHh|lBSdj_ z=BjqAO@-RtVC4*sBn#)U!$OmLuX4Gv5l(_-Xl%R+1iYbQuGn)194_HtRR$EV30t+f zjZhw{4ah(C=M1|dBfZ)AI9q%o>fL8n)}>Zx)xDRfadP#?Ti8KcHL^!JJpG!+i&9Cm zMc&nA{MC!8j`%lkfZXI;qDKK+KY9;)aZY)gtsO5#Vw*+%FZI%7KbA9V91v6hd$^@A zckSQT%#qP2-idYK)?FZ!*NT$9t$^1%P2?|L9l55`*@&*Ph_ zJF6!FQFU&srkRHG^}8TQVXLigF1y-{$b{hB{XF>+Fe$1R;_^U4LL5#SJr}g-G|)zP zs(KZo&JhMBtHQ>B;jJf_6FC>=t@XV}^L+c<_V!CO<99%mGW%meM%lyrWc|@sSrTtI zA`NoV2z;mIhHHf!bjIUB_Q?Vy0Osf>6{=}qc?-rT>cQ=;PS;7Q+Bo4bjB8^ZK8yvN znXL&yn_Y>oPuTGoZ`-KolM?Z40Juc60YQ;Z6$;cUd9bi2`s2ukBPiTKo$I7r@3vR- zbeqLIxQ(?(>R0{eM9pVUQSD>S%QpsO`OehUqUW!}v=xx%V?zj~21~YM65IZ>#eLB; zed4gb36y%B6*3Vb_I;Ap6^S82x_Vtqv;U%^pk-w{_wB)n^3#q%@|0G2gVKfup>&7`u{nG|NY`+v>e{&j_`;$2lqGIjT;m? zWZUGF2xvFUcAJu?t&+Y_m5oQ&S&5Jdt#02NgN40GEom7ja@;MAlt<-K$=T`w9;5?I zO$o%7{7l?1by>-Fn)f}dh9%|>lo`247fl_0ou{8>$8!7`1)O`IgV)GPJv&S^J=S0e;SBVz;uI}}Yj-~`$U=}P!DdQ-^WMV^E6T%M zWZKeHgP@JWZB9xHld>8`bMD~L@{zU|3_qor4P^19PG?HBTG|G5_#uC*cTrNj17BUy z_$rv2_ht}31afSw>kc7dH%IX;?GOr^ybX(^mkiie1D{_F$O=Oiv&Hx&f7*8+*6yaW zPgiu&sO(%YfYH5@Ydaej>f2_bsRNSq4bcmHp*Ez=F432|82**a%T{IKpPI2!@nl56>X{hcx zB2~@sLSpGs7IVrlS=zf{t?@jdq_SjP_*XecVKrP5z_hJu2ysWpkbY=aw=F72%c&<8 z6G9qxs3F@s)yw+0%(1z&vf5KzK>M?u1{SDMG(!^~^VA&{UgSA7 z_Mv2I`;!_5IzXf5FM~c=y+xdAnGbG7IZD-XoRAdsP;IPwoK(Rz1RCCd)62=-*uPg% z{CSu1=JjngG2$NZ_=;V`F((DDBIQHUE?v8UJMiF1Q9ec|XY*NAo8FSuVE$lt?!-ba z?h1nT_^rLH9?I)BCy2tS`iQS-^fL9^z#xe|5Pf1QYs12qdEPbBBbyfg-K&Ln6z?y; zh36JFQF=&iu9fh;Tms zvo(xE{y$dMhH?9u&5O5*#Rs7p(oBs>v!Dy1!I*hLgKnFV3WEm%=0~9?a%s~vr9ynr zj|uxi#a!L&P(Ddi?$;KBOKz$09<+Xl&AOiUhhTeoKU4%St|4;IGQQ9;wJkiAfai!n zEG*A#sFqwH{`nrD`qp1^(vPz>>cAgTl820^h*<&>^v4d&$@m~$UJQNPn0LS_l^0h` zdAgtqau|B6UcGc92P@+@;KzI|fq4H=-MA|`Hl{-{LLs!)vM{ZAn&1ZH7Bo>M2Q$)UkA@K0H9lF=PTjpdi$qFR>mX@n% zh5CTe)mg$__Y)1{hFx>3tV2C<`QTKX+LM!n#xgW{qpoCJcrHiVF?x7$p;7yQW{N~2 zWlr)}7urp%CZx^}iSZYd%cf!si_geXC`xqr1}fJpHs3B^)KDF_8rcv1SXh0m2)82_ zXv2gVaF-@U!*#Ei+7gB(c=uY#!6o{C>>(!o+7ao)Q%GO{wnV0nwUgPg7qQQ#M~vH+ zcaf*S-ZUht;Mkr;v-dG}Q|=Q*Yf4XQ&6{o-NI^Vy14}weh5|1cs2!iDK%i z7b+&4)P|*0JX}N_P|Za~F=s3lm)NL&c9$j~Y)V*?2n!JP&8JO2lV`7oT;fsR8!J#9X9#yH8H=HfF5)gokK_8{(eej2EsyYuK`w z4A~l(K6H<%ECp^~DI`6m@^}MCrD=+%SB$xcdrR72M0d#05SQCBnMU$w6Ul#@$=|OmIksMu=gPFV7P7ew zn4f$I#>tbpOn~y2biuy08CfV$-8pHeSiJUzYm%Y?mT>*UZ>OFamrKaFO>ub1P+7SI z<9(2Q^B!J^odzK_AvGCpNX?#@zlxf_Rf|s>E(M_Tl$gb>u@$yAT<&(@^VF7@ziFeF z874}0ljZzQ{dvPtEKi`78rci8!U*bi=!%e7GJN{XB8$`$Gq~5o(&J>%`qN7#(feNb zZ6Z5#04k{IMD1`#T%B6tWu?eLF446v1u}Mjxe8@BrY(=}{*kVq714H2U1CVxhiU9u z#mlQbHncI^N~h@3OJUf8LSA{w~aV z`8=tbsCN0$$uGV${vG6iPs_^4hghX~X>?w~F>W{!2E&WAIY=EXn0}5^S98-NCrJbC ziOVe;;GWSqq$VZ36t!7tRoQ}KyQ`AhoaXW^LvVSwV!B#g*}MML3s75boxIndR@Q$& z>T)VW;w$&LjZ4@cce^!|?WWelqxxuK84YOv zXo1_KC4CsO`k2x-g@62f$y+D7Rlz!?<6dk-?Ap1mao7Q$uc>%r-nHNtD%=pT5z$?W zzM`c(OMlAp)q%W0!w}-6Abf3aV*R3frY;_S$UPGY@fYGD>>==H5cUDC_a8;?gI;V| zd^%+#*koZ}B4Aqd9~{6aP`ntfx==+M1%qIASAzkOaLzwP@IFV17f<|kiARKK+k88vRITi^*g(D{V{Nc=|p#^a=98r78~TxeyU z%aRJw+)cAPmCWH;+`5cEm@K+-fw`Zl?k=p4HPNlsF%Mi@@Em__;U;&vkm?ihRLB>JW*mEd zm!oAvR|kQ(7jsAv_{Ayrw3m3zJ}$VM?_h@cuEs3A9Zk2>@GirXCkReybf!OFUWKez zA5MtJwdnZ;-oM8xm~%~8OOeusO*MG?q)QSdp1k~>j_f6b!;jiFR~@^v8VC2$af|jW z`vd_MBMwmwp`Y!aaePrp{x!{QghXkRarla=yK9o)gUguR(~4)W!UjPt9VlC)iKP{KMb3tVfQ0E8J> z81m;WHnT`~op~(zyLW%)O#(?b&&nc2?`6S36P}$%jm-{y(JXpOOkxMue`^{Srq^Cs zqr03fC}FGwA1$B42Z^5Co-Ozk2^N+p*%7)NjDl;Aky>VDr0NSd>?fA+9AdA|Oxk_;E6v(_H$T&EacC{3gF{=nC4*}$ zar=}3LvC=*BpPd_b$D98)g9QqB~?Q~e;k~^cMZ-?_%eV3JQvdu=buZy$&$Cer*=pTJswmp{ESmGl6LgwkZ~WN$B6XjeUhiC;&8%cM#H(6h z&avg&Ha7q!xWn}yTvxOzG~2$B>m5$6bVJ#mFr~>K0K$e(^IquWz{Ic0mpLbbuRhw7 zQwkyzmuU%9z5&rurH=ZrdpT3n?ffufAdh@=5|eoUwmk}j2ou4(3|LT<3HJO^<6UT^5GO$a=ZKP zho$}!bK990vyMA$Bu(z+s=<-7vkFEx)&0Dn!&Y7plH2qoIz0a1oTK^IkRkir@RtU< znR9n-rK(?0_?mAWWMuJJu-2x_@G@A}XkP}gJbaK@2euY)ESA| zUWfAGvUX(f?9XRc=*YbiLVZQ}C!O6fV9&QXE85RtERSv&a08f$sN=MycMpihVgn3= zd|PmX1(x8GR34@YO3Ly9g#o7Rt(?7XQ1&GATZKV3qCdLFLO->QFv)aj;D!)>%DwN~ zSU~V4V7mpEvgwsw>&#N5eremo2RiDUpx>fKoM2*EHRfYkrL0Vv6=;cdSh7AG+;n;R zc{iulMR^EeA%%jwkJO#&D%jd#cJe>0nU6+{MBj7Vj58U(M5`(YT)lq5Vfl_e*U9q1 z`%vj>7NYf0Mlo7H2=R#3<9kkA`1na?$*Dde0xr-W0=V2f@r;&N0wkax1X!YsyL(Y; zAOakwI-v*EMB3`LZxaOK8|4xqMP=S?RDhHxL^BuIa`BVYrI=B8W^k)a;Kt7fmcZWE zGGJ%osM@7?PJb-J);mM@h-o~KPmwu@v)DX=TAqd1-L@MTYL@?f_4qT9LA8P}oC68% z<;263bM_@R)D~aM+s-r1{~>4vat4UMcf5S$dq|1?c+N;MtAzeOFnj@mv!N1^GYSw=?|#zJRe~y8 zsJqlYI|6C+o?Xe1_bH9o@X5$BodE)zGo5tF@S+rcd`mzIR6v=D+vUy#n?u1+Tn~;1 z&+3r1OhP2m4Gz~8|NF&YWb(m#M3|^ZKwAaNmtA810^*KF5?=v3ew+P3&;530d3E`4X4*Rs;#dV zsnffdX(jTe6zGHc;#Xwaxd?i|p}g}#FSSRpEZ-Y|r#}L=Wj!oPS@IDI3gYJ13PZ*O ztd9AdT(ofvLMC@gxQ4TwZ}q?M3N1oyuUB8r$+gfV2ZRcRoxzOa5i8KI)b5v%T+gO znk}Ebyd8AE!NhLZ7rVD9<%2*tAyDKqsSi$*G$Vdxfu-g9zkNgtXPCzOZ*Rn$TJ9X;{r>J(7NyPP zf>_cb$ho{$@|t;Q+t`^ff_xSNh$1}@6WuVjZw@D<9g>k0DlDrspNI@Pu#EiXIOM~B zMq=M=_{B3-RL#WIv7XcVn)3@*v7To4xlUZg2h_V+wOFMDUZWfKrY<1|oH2bKKzc`z>pvXv&7kQPrs4?4X4BJagvUa3DHz#oiEww-THDvKqdYU$2mPW#{asd@pgK}es>2gkT8@;#G#n123a@$hvRB3z_dX#MWUho#0 z3^uqQ??Bb?Ade(DykkFx##_dSzk&C;hP#UxOLmm^=X!c zQ%cxoL*}^+{E+ft#O=FW#gxcPbOv^9#`20I5cpdaM-28JG1TN-ipwXuQT@YnD90`+ z@+=)eO}XRP&eJEoyv!LZW2Rk95DIyxv^UP&wy2V1p4 z_s~jP`vt#l@n0!fk$Bl(w0O2_+^Z!G{TA8{{iXngk_*x_ymq4m^$N-cM9CMaH%jtlQgYo=K`Jk1!u? zyh=7$8PuiYrv)u(sB}gb_6ScTpxaB~X}+qgZ>>d#=Q6>f8EUVL zjrIq@ntz*a0K+RCiA7EXGT0TD`}sFdg^wOduzR$_^|4$aUBKpV><+Ye zBv*_?w~8f>V*EHDo%u5hYM{0?o;GboM;q97NorROyb8{Blx-`}IPLYo;nSrG_Kd75dbI))*+}{7L^k?Wlkd<&Uyh zPA-oa5Lzw%*Izn>?^j7JMu(8ARC!xcYdcuVu8PJjKdix*_GU7?priC2FY84`3=M@f@3~mLD6j zz(9chYn9va{g(L=PI31WqoHJB85l9GkZqMIK-|q?1i87nx#G29io*}pX!To~&I+v= z+0k7tk~(5we!p4Q{%|R?R8>fTP#d=>6j?M=qjnToQX9g9Ce)Z7`#{*%h&Ls~->7P?>v@ zmYZ`PqXi}@8yma9Lf5>%d^ZPE9oPI6H?+o5)U#BjV{YNrMM&I6tXqUjm@wOsJ(tqK zV(>4SnNhhqg-loc-&?mfXf^HzDbW>MJstcpP6RF&vxfqgJSHUfFf&A6p!Bb&=coRE z+rNM4nL-PexH>@~8>%!6?f53zX*Tb8!HF5cS88{3}8ZJyRi7R%d=}#_y z=lzBr^cl8(Qh~uwsZiC73GSVEha01N(pRdz`3{I!|a9abV)G&Pfn zE9(sYTjm@Ozy*X`WkqhuA)(Ui4pAx|dKyjuZVFr4x^= zv+oVQU`*QI3+bW(-18=6(kGkP!X+``804{u@NIo-fN0ly;AiKVW?0={CZo!%Nmg}> z$rqOginuBh_w~j^$^=LCKYrAr#3*Dp2oXR8)8oi!;Yku5(I zOK>MQYW_c6(!c&!F4ZH1%3zt}aY!}=>9 z|LRoe^J5(y(ZxBVvi!na!7EeLzj^x`=wpWJZejc-b($A%nsJru9lV@#;8wG&^RFZ0 zzoi!41kfG0Csp|&y?e6mj9R+pm-ltOc50dtuLKoBrUn-&-Ry=f zQ26cV*9-FF=p>G_Zvs$?Qe4CLROgOLi_;0uU1)VPhi~Oa!qfVBUG!vCCqMbOy+s=+ zN4?MqRcW!KignsJL7crJfMt`u+z$dUw#M6Xesv(T?On3_IFk)E4%UjzjQvd6{Y}AO z{=(+n@9knXPdMJ}m_Hn@XcRW)ns{m2zkM+Z>G`NAo(G6QEd8OT==n`A4Z?gHk|u4n z>1mjAO5VtKBe)f<$)LVqyM}lP96E2PFNwbxx(j!?)R8z_SI+Si4rgXhFLz|E-mVY~ zAf|0s60OR$^b9v#x=Zh|VnuP!!sV3-;Ntd7qgg$|Z78kn@aawXht0_q_FxX}9Wa6K zMfFGt@L$68k7K!9?;GB+Qn`@VLgVp!_^46DLx30790h?leyK(VmW|7Esl}kzmBgDC zfoUOgUo$Urenbf1+LBlht)_N+!-e6AT0>J+uRh+tt)F#Mn;e323mSQZ&j-=^P%ie- z4%NTDKi$c+xEyaYdJc%8WF2h&Hnlt9gyADlR-EKF;xMulx`j&Uz+E^*>O)y6a?&zg zbHl!OOm!OGkJOPX63<5k75^Z(*WCdgv547X$nnnfcFM&0Gg;SoUg5Gl+LjDP;c>|0 zQR%t+*gd_4A}~dX@Oi#?t10K8NBUg_ApSE;>!d_qOYLg(SP~a!duK__U^P1T+F3dg zqC9Pe(u091ciMj{>5XaZoJhjLOghtUzInS0bMs$nxgbkhnX-f^ zyK*?EXg$Ijf^_<}Tr-n$Xh-R3^i8jBN(+_Q02*!h|Fd@xL9Bw?$}ctUFK@>(;Rj22 zF0+~3VNeQvC=|?ub>~jTrBdy9#e-TNgU$QCRd%99a$gC!$c-FFj)No@t*~IP5=>{x z`|P(AUEf~ka^T-Ci*Clkvg)gG%T+ZHuSho4#-qNd`3HBj=(_M32G)CJx>EbvZRp$X zlis}Z-!jPGBQl0ACh+_Kecyb0$d60Onx`H^hxPNP8AEje@~-a6YDrb5mx zadZjmk7j(EoVTT6J9J-Eck)sXnM%ZX!{Q|MpevA@Xrx;7;b;$&Lp8!-$fjGxYH-MX zR~i6u?9k~u!n9=Q(!E4G-@Pm`;k9be-I}S`Hot*LcAV(En7H|k-upjSQZkYEE{Aby z*F9`1-zt_DdBi+W<~ES*8Jiu7)}Qf9za!TKzwvUCilLPQ0IOMkJDQ+8@o0#v-k+BW zhuSc2kK@{X)pfOlXsqSs18=>GlmB%3W*Ck$CO2lM)LK`H%O&=F zp7|Y0i=ZK(sM$||D^#xGZR$N+7E4nn4O?ub7Jjd%>3ue zeFzm!OI=;6#>RoXN@JjJb^XAxk_ov=e3&cQ?Kf8fYaS6BWA%Jfg)_I!gS*w-+|dG< zy=rj>oL==$?{6uEv=lRlI`sgj-MVbJkvn7Ii|wo^e&>0C`J)T0n@YWNH|oHeYw8e} zlaPrWB;?HfWbV{$Eg|;kb_q+Qh$SRheDOspt-y~yM=?cAeK{$6t}O0w%y+h8cGvwr z#bF=9W^sRGzXs@XBy^(=@;YMT(3>!R|Axl-S zr9e0AI}E^tz^YIipsJP7GQ?>m>#0cjwHkT!)C3>Wm)q5HJRpR+B{}9|udU_?aeZ?W zb*)vhCUkxCH%n8V--Bf&X6r-BMHGeWMRj!#gArfPP@Xe94|ubog=){ym6e0WEPtAJ zX~{|tdVMC?$k|D={G%Aph{&iY`vscUXxGgjqUn=%ny-7t=E$!8I_KUB-3r0f;Ka)F z0*(&X#XIV>cNGP15>=2k_I9!{MN88Q{m)N{jDeV(Xrgasl}~MsV1j)5ppf`}yM&*N z{bL4=`*-Ko4Qf>khG*;AMab2vZAmDh5%?gXXP7A=sh6u*M0e%(rZVoAV(!WxiLmj2 zowe*$5M|H&)cDj_Lsca>X#0Gm1h&Eey9(<)*Stb?v8|lW<^Rvws}o&J6?Vw5 z00*|REMIL{rKcW|)H8JoZ$fbJq<~hzgh7wqBJj5>FU<#*5^t9zC$}*0u6}n(o+1KI%Va1k~zlDvKFZi&y?q{6k1-~vc5E}0^&@=3S>QO!$tn=ZQV=ux? zMnk`GwzF|vBry?Xuj#xv0x)ZLyf5?>GP5MG(*OwU#tP>RXgKXWDxGtZD0#0jFnW*w zCkLTKd}D`(de8iFB!&JR9*ShjR34)1#Ed-~(4vL6M{z2Wl)!ARF@%rIAJUW;DnzHs zW#pDw{kc_GIdPm>82shFQ15PH`;)GQ$FWZ|ky#IgCbVb;iROf6E!t5Y?cd84=qQ`5 zmE0@-984?s>BFGow_JC-{IYTmYuS84@}=pA;O)7(wdbNR{Ki3oy%A{Hbl8@B6h$c1 z1R?$PKJ^0wJrtpT8W_?tBv;Nx}nj05JM2Eo;2?Kf6s$Am8$)fT!*?XRs$DmqomkzZQYw!{H8M7lR8Iv@z*a{Oag zajstP@WQVQ$1j`bxwYmw5@6D&^j?W^h|6SGdHd*^?RUGLVawx(u+?vHPQZYba$<}2 z#Y5yyeN@1$Kx%Iq426yfJ5ZyWu16Jb&E5VHCb4FFGFyMH6=1@z?VM|Y%YvfokL9qc zN8tXt?dS=}MIuLxTffkbX5`~y5`%30{2Q@STcY*lBM?2K)7oTN8Xrl zw*TvNS9x3iATpe_xplha-HiiJ-fG3Bf5RMxXJRLpWc8b(FudVfbExU!DLfg4q0QB9 zNlk{xeAsMBim=JJnL{8vO%@=;P(FFatt3Zcq z!3n(IUOlsZ9|h{TKtwx;mImJL5L~xF}!v%sJoz^?lJODI_3wlffp;jq<3zFwSiHqf*2sOK35 z;8n`q8TVrjRTG?L{a%7>=kJ#3$r@tA*vfJye3PbuyoXOUSGIerP3fSOhl-2kxu_rV z@FS0|c41{#l;10YqY!xk(!?%CSeE8IG48Mm;pFukPfe6cf2B5Fr}p1-@-X1~7RrZYHO<}fO> z(~J(qWr(*Ah8qlgcMeMJKiX*>mM6qsJkY(|zxGqNn>0KugK_7g31&`D!> z0vTkOv1h-lfZ?E@!Q*{G?g^rbKe=6fEfazGTOarez?eg7^f|h8krtN{*o7e(e3l#3 zbx3p<+b8&Gh18eiDxcT#R`VYL-5@rRzBdp*Qi7O9Xgm*=<;HYBA@qbjp@2}a-D-;zl)cad6+?nxC+;+ z4Zq5nYa>MlkNcvI7ScH;Bn(X#cS*%eqQtdn`QkHYCEN4vDZ5y185OTr5EAnzOQc~K zGenO`#tuH>(v1LJ1s@OGCQ}QL^bF_EO-2if(1&v^G%WLmgRY4rF8N4{0Hib};_|uJ zf_v*E@)_I~`{!rHhqar5_u_YQ_fUWj8A%G;I#rwtWB7`5eoQr2DN`)O2A!3cwTmdc zgHcb`5oQUN`2P4{7%KIP@RpkIS-<4a=gac;rT@3{XT{g?)P(s zRBoST2M$>4PDi*$x-0(@lq}wy?doLlECTM9@1hXN><2drU~FO4fnv&w>%WKGpA)j; zCaFRMY8eSaa^~DJb2JTU7nef1p5-sTw%~l6k-HI|ookpcwqV zz%^wwOiwOtsu`$w*>94;XxR~12c_@KZVa`2`E5yu^mzr#Rp2Z{+%V((?RHD?5{J$R zHQ``0?wqat#+*vK$PPBH^kRGUs_l)^v+3;2wvn3=1ZcC9xP4k~Z{`i%P`=~GKY<8< zD(7+`u9eiHdSYR`9V9<>UX;1a|EM_YBInnb7jxrRc4U+e+wQr3y2f){R_0;5%C)7I zICzx1e-`iDD=eS%6c_v^sU48MSa9w^j-?@DIU_+NySBEsc}==+G91^IOZRH3u$w}= zx*Ny7O`YS+e8Foar+ki{c9zpCI`jN6hN`uCy-nhp6nTmGIAcCbKeW43`@JTddgv0# zwbUr;WVrRAn$;I}4=d!mWMnbyFEow>v?T%$B>G&nf_~1c_vYGa$pKAftc$WN7`dE&e0; z!}`RVP$;I}0q9r5fi12BOV8ROLbPk0^v)Rn(r18{gA=QnCRuV-FHSwL^6y`Q0VT16 zJ2RozT2wcZ?x%FDs*a_0SI$ENCpw9FD&$fskMEW-o=_-om|>9%lspQh2^Dz8YyN~L z%Is@d7d*o3<=3zH(07FzSmYn2elgNzaauW}QcuIRO`Rz7ciJTo9#1OxYm&hxF`^BJ z15pX$!RoBfy)Ldt(a!&}&X{B1J?ursAvE)yI;hb-XQul}A^|9=KL7Bp%g+5Vo++AY z7<6BSl43DY=m8+WyTY(ARsPNAPy}N#(EC`r?tJo1w>*$Mz^W$QXv`))%&|ALqwXP| zSCL~@Xj`I79t+2z01LYTx?SoGtJ51aO^#g!MX!wEcX|@weug9I&6oGfE?fk60KNz+ z%kmsmLqJ8F403NSwMk#~IQR+X=jC^Ua2pWZu8YnyONftB1q)`>o~i@so*&YWqe%JO zXKnpG?Qt#{;#1xZcpTr6?p9yk3cD)Z<$d`s)%@68%^l1CYsM2IRS&nhFUj_3l**5_ zz}~0l>yy&G+#E;T3=1@U>Ju#%`J=ui$Ps|#$}}2oGQP{b7AF1HUgm;{t8Rxpw)W8p z!`}TG+Oe!z)7J6xEB5Za=?;d{K5Ck@J<*%_T&v?&(|S5ny|Hkq5=8$1eg~DrInBvV zG~MOA35wLEKeluntRG}Hl5s)h$wni{b{U2)|E)Qxzop6(4c zH%!srgShC#{4E)ws&X8U3}*|1yUFWsu3N-6hsP9-y%=Qs&sVnjgimX4d{ZfbhZika z_Cxw1gw?)AdE?9g=crx%@bcV=dUHdT`@{7-nHCwX1-w7(1HElaBeY@M+>zJ@8T%{% z4?2VDspX8t68uM1Kq~niTRN_Xqr{X<66I~rD4vuJ2eRmrS=zLB1)0Z1^)IDO;~Kz? zghZXmqcn}ks_|IwwCGlbZvIJjK+k`EB$UhG?j>7bmRBmvpg6bsa3_H`&R)|)`RRrzHj1q8x90{`fKBwDk9!QV3rS=^K|btMYd}?BHIe; zsM5n$D^9aX`PQ#9Yh5~J=Vx!lpxKDUCUXBASwv@M%Z{QQvHQgF6~FRZ-c2-7{3DWG z&qtzD_6b_U$Bgyl@a};LWh%jDS`mSvna^{{lHLn-oJEJkX+>In1>s^tovD;%HkzCY zO=!c!($f)Ey90Xa#vpr&!Q`HAY{3bKYeiQpl^gR{dvu^uJo^NtFpJy7?}6>J?_=%x0rzS!M8>)g04cFuACDaEw>siXO`z(A`q1 z)+SUGa-=-jbiCiu09>7ymOYqHUMD7hIal@|IMaS(_89l0asS-j)GpgUq?swFgxZo%T~a3RB;p}wuRnWU(P;o_HcN4;RwTd=QW z$Gy-`t^O;q26HwCur0$*v_?@|;jE{D&@A&?7L20(1e=+3Sg?88?s<+kimE)BhjgnC z(C$BBAl;IJm2OpTg8iF#0$+Tp6wc-jKxMsB5J|gQyz}d`&b{FfL+*xHGAQw~^i)be z-qB|~oPsIUA9mioPg{zER9fWCDK8el47&=YyU*3Z(_2l_lI%=Le#D+1UhNBtLA^Kr(1|3ynznPC_#DaQuM$?Sj(Z#w zA+)bxB+jGT-!p{^yRo+rMWT3g(+SnafMIabY)XYSB(Wkx^p^&o_5CTGD~p@`bAFI# z-)9U#HCQUZoUZ>By|HN3vZ#o^U~kYA9{*7i(KMaV{#KM(vrn2#^b{BiM!cagqDB>k z0ha#MlYR{|-gO|4N_7nyK~L5c8J@FtxLjPHy9kH7U;=?8w{xcd0$Ki4@GE;BeC107 z(ug<~;a+fa-tjnB;o5Gbgfwhmrbui>*gLvMZ(wFkFG^-Dq-PR=YsU@U2Oo5Y|886& zwv%s*Z48-4RtTliiuk3@#)I2yy?BHk&MMGygbcIb6c}Vp-wp2sJ#KcCGMez?tgp=z zm{Khu#ZB(e%J^tOl@l69?{DF|V*gT?Hnwz0X!==#rIS?NRJ;+FAUiJr>Q~@r*5MhI zOR61~5-P!Rd(ZXi z9)(jx)47mKck9JW_bD~oXG8881IDtHuD9s~2E&m-hxL0$t#&H4FX@Krzba3S)oRro zIv47cB@^J)l7}$d@E`^COZtL-X)(-IuQ8Bh;IqOdl4ai&FJ5%RjTO%=p&_&b@e#h) z0fgH2wk_zo>kp{0suA2AQ|vz~I&M&4#K-P->Egu+W}CeLZM~e`r@6ys{X;*UteLop z>3biMS{CRggRf4VOddYOkD>c;%kR{s7Gm7<1D5yaSY3voHL6c9H0QwmUt@Ka3K%{u zjcfQX;j!~UZ|-%0a>63T?VcsSG3q*s*0NuXj{=xflVzDo;k3Ujh25_ImNI-IJWAq= z|GL^sQQ&)EJx>sUU6b`R7y6c;-RK?F4f8{gfM)nAu2xhCeo{c@%~GM^8$D`ePC zlb`o`bVppWpjye4#}u+1eIg!v5JIC!@os1rl32R;&t26GI>LRN%94G$ExoGz$~bMiHvt>ZAm&uwbB*c#T1U7yo#|G=K}|8B^9qXa z0dfl3+afX@_2#={Y9N~d=K0G7cqL0Exz}+3lIQt$m-U$Ox|BGSUV6^yN~8PDzy@av zJ7&CYJl(2jdw6d0iY!QE^t9x5^$4BA<2J4xaj{igwLtB+A=Pb12j0PH zydKg4503J6F7_bZI^7nq68+w!65i_N$6-TOyh9$nO{OU@BtNj2roCDy7*ChB^+q6u z00%w=I~>o85&Be#_5{j4o@z|NgpHj3bne&DV@`a9o)$bXk8A?QzdXGCqKicURLvfnJ*i=H8!o=oICEK)87aWl8z{c~FKCQmyK&-hp~nnF{sF`ekls(jgZVL; zQ8Gx-d@lbmgHjTAu_DXv{JpVrG2^LMwI3+0Q+Q(QZt45hCF$En@_8G1K8vVk%^X%r zIKT>;lfH~bG->6yc;<9}d}<~>-{t8(SLDI9DF^f=(}q^)dmf1Hh< zZ3P@%{5@7R|AG6JMK6G#0%MOsk0ljwl|luCNJHcdIE?tXW}&9bP%W}8>bvU5pXT$m z0Dt#PHLbXTOWN|Y*sT010!xeA* zQH@r87YZ@rw*N(7%FdfZP{^b}uWRxIKFb%P{$6)NY^xr|Gr4S#ndu_cZ~uab4JSUi zwIV;?RT$oin{L2p=7@`IbRmnu#^kYkoS0<-#x8AJ8M=Ah;1H^do3ss0o{%LyQ^qDz z$(=Dj8u@pJBH$h=<9Sgqbxc}w$9fC~=_@nYYBFRgC0rfJ^O(W*`Q=pi<4o<&9zDIz z1+po9C$WSUu_M``AyIE(*{f(&t{9YA{bZ$x74}ohsVWSW20wjOPcGh>tXe@O?nVKZ z+P1Jd)hV%ZxIvq;p{IkB7!tbz7K&G|gIqm?U8##vVE|{gT{XT-G_#9$FMCdH4&>n{ zE8&gVmeGT`P4=-uqe(0%DNHN*mIb{0 ziv4bzDh`(ri^0!W7uvdv;Uf7Q>nJu1{XF0n`0S=rD^mOIl6sV?1g%M=g8ltKCxb_G z%(2hu4ac9+%4h##Olixx#wrz1eO%~H-T-}Sto%5K;13kJL67`EKk3nIvhnvjGn%Ij zG>EI+kX~y2=`~uq_m~SbYA|#b4Ta+&I`M3{7gy6uz@OUWJ)(RXi#^vD@~ig@*kn&H zum@8iVa)xyOZ$+)jH!DK&tB(+$=rG+KRguY2^G3JVi<0O>&P3&3$O5T0r-4Ftojq2 z7Y2nJvUrZx!Y<)!QO)7J+g$~9>ps^mOQYgoEe*8OP0j}Xk$5`W(*Upj_yB9v1bBC~ zlWr3H^*wolO5)bQMz!cI@uSA(c8#DQf^zQFsUj1{`uOG9*R`#)FoxB1B`@!~pYqQ2 zkH;Ot=!Dlpf`!ZoN!%y2KkUyR5yd|t5pE#ep5lLtY2~0fSoeb8jtC&i7Q0woUGw1* ze~~(jmQp#*ws3A!46JqttImYKv=}6Yz~gk3!|I+kFQ-%m;uTOFwpxvyoiBthiD#Y!JYJDg;H%s%&K9j@%RdWR$Y+bUFR6+kC<{vogr89m7 zpd?`pr^|IBbJd7yDnecHfW?$3Lz%@)`6RTJ&!!|HPZVfV`?Lz}yaRaYO^*3!C|_o1 zDv>2p0CQfp#ET_CX~^z*kQJnOUYRNOf}w_TB)u3wkS>k?!`XWPHPv=)qbdR_O$BM8 zS!g1?*T{ncN)ze5_fF^~K|p#Hr56>YNbfBWArxt$6M72}dhd|r56|EvWn(Zzp+yDUtZf&QchG@giO#npsS zkj1J&W3c`!7BlzcXRkmzS3bUjwhOxA`(|LbSyyWRFps9H27K4s&Dk%bQ<2_>RVMM4 z-+FW5A5Yyb3m0k0`r~kv6vh?2AD!u3W_@nffvca}>`G+A?BvTFAl%X45 z_<-L#=Z0Dwi!vXS$pX>D3MK)n+R}h@e-`TUE1o1BE^HJ^iSB`Aif?Pw z0~Hty)0=nM>sOQ9sQ`meU&O72j$TV-~2}?#t{K?~z_=L6Dm6Z^TMiax{_!`A4{B!PGY{EqHnc+<% zyw+`-`Fm&c@umyAe(uu*`TVQVg7u{eOj?4lG1^yi7id%{Nk(*=J}_?rGVC=9PGeusVSMp7I|@Y-f} z;QM0-!?LS_TIpf)$O$S$??Ps)IHkNF=4H{{x>Nk{1@fe~wPl2l=l6QQzDC~WG_v{L zIL8vS`Ta*xH1k17`C>}{2kV=~gWe}*8`-o`<3C6Fi{rkspE>1Y)@PiF?>$f9 zciDKwrfkrrKVW8nb!^H2ru_`yzjDT6+E_~M8zr+&r!!`~o_7?d_qJ02Er-8*ifO#9 z<8oewdNq_WGZf`Dx58omA>j}k#S|fne8!A-%i0yTbGNj$Z!=q1zMVW>B5r6NP@V7X zz2P!PLJGE`V@kGW&xChNZghl4{5kC%Tn@*qk4U^8TehLS!cOhZ{a2NvRxr+Lgj&!- zMes!2OYKBjWM6TGUdG>x6xO(EVVq+Czhs7L#Xzt0;?jJ?>P+fHy9{0Vx<2kU6zKOZ z>#+0twWQmN<{1BHJy~&km?_~c-QJa{6YZ9;Sn;uoe|C670x-OUKgRFeGfw9G734NnatQSxtvtW?8PnSn3IOmngVvrlgt7tt zp$Oc!oMMJR(&F%axH{M%(puYVW;+w&$_FeB7HXrUfZzV7Our74_z7QAac8N_eJ`Xn z2&!2Bx-Tj@1*oM4NRb*--BOkR>OgCB?8!$R9gb!Y$#fXCE*71?b|g-Ew|pMjFc@_f z@s|8H<5(LC9})R_P<^xjpq2Sfhcv|6gax*Iwqu5M2;E5fK9rq*P}H=u@C%+XTE@j$ zmjI!tkMM^Xl2}PMV86|~zk5SA{m5grhuCE?E4OsDrZ67Vy%K&fu3CX@#)r^oy2|TPVJI|kD=!{pR?}uSe?^d;B zb*8G1&{C?*yq`JYLo}Rd6J;Y~XRh4rk<6~LI6A1%24km+iG0T|);^<}XLG-Q*bVRd zAaMOEhW?#0p96X4f79hjpHl6XdYO8!eg=UPD0}c+;*x<1#|iPRR0$h`y0T?R%I;s` z(`DwXeM1JGmjAd82Z3(NkfnK#fameajOoLrRu5wDk!@-hn_slE1~h+PrJ#@ZaX8z< z>WFW(s#ni7iEkTFzk64atd~T6IM(*-IKZ*dv0lX=lidTPNC=i zM}173Nys5fRFniTDBbaZEaW$WB)EYb%JR%Hh9G5s+KJJ}Y?>#`AL}8hk*E4?*4Y2m z2VkH^K7?YM8i15SZ6%mYzprx6 ztayBt2v{MV$%8H)GMEEYJxf(g-%;=t^X?o)qK7?^G`?QjB=7fwcM zFkJ+%Pz0Xlt)I{wENzh>z02{2>DwD*&R)s`;Nt4*r1PVy?mlBEeTqpBdC7E@cYa*; z^WJs0In`B{>CASO0sLRum%g+s!lZl%eCgo1qq>H^*F*~D#QwD%_oMOJl_5h<5^5gH?jBO#STF0k=Egza)4b&|=%w~2^Y|k9{cWv`a);JCPNL^P>;BC7%BiKK}FnoZQag>UV+4Pd5Zb?Gy(KeO*Um zfx4*jD1C7xL8Y7F*lU#raP|a6e)?C8DC&ilLy^zU5TrcM-BVjp*s|m}q-ES(qtk_2 zmG0iXXpZMR-|Guf+de&sijLxV@jS1fI&`@5{adBCoZMWw_4TPspB}z_+snbj`K`Jd zfAjwB+qWFgIrHi#C@2jw+VZXre>nEINRh*T^N_Hrb?>Jy>yLvM z*@8b}_Xi#cQFIv&z93~HQu0E&)T_{9Vsm1@N>2oJED}1ns7wI29)j+iiWc1byH$j= zGJi=U!mV^9qf6DxyoAcdCaFwr~ee z0viCNQK7USDe;5`Kjk%0cQo_IJpT*UmmxkX*DdAuA^JiIzr&+2BIJKWw z_NBg{Rd;lMU80EZkC@g}O};v@D?kbV;;oDQnQ}C8S%|=Y=)(GxQ8MKYm85Iu{7A2H zaC?>9QNX_zf4$)U{ZhmvdLhjC!0$#0XUom_gf4y$)r*c(#9owCa#G%QssMvZXl{qc zcF^xZ+s$H_RcmPZIN#G2zaez0VY9s@0w!_h6QhZRQ=HNh(D6pV=|kLj?$KR}FIqad z&B!o>S!W&Y1&jMViu)B+Q*24rJ5$%1*>-;ac2Y>LBnA3vuOvFS6MF(qtxvcL4miN8 zmp_L%<@}Ks2KA|Z8>Fw-1Bxpm2VBVDO|q8An{1Orj%^PvEhzLq5kF^yH&#K zWiL9<%nUM_*-jWHOeq{N@&;(D@^K=k<{`bMJzj8-F!@pXD;J*S+6DQNMugH#shMEg znX{`DO?Z0qg7t*9@^~rFkangmEt~TbFP@eGdO7g(c#r2fQW2v{0j~BiIc3^xjtEKU)^<29r%2FA}>E#9CvMoe}mQZR>dJ3Jsnp2(&X&y@JN^G z+=GLIHJB%W%Nu4llIPU@?eAQKBEfJ=;N{v$9#p=2)&_fZu6g-5_3t$Yu#4`o_5B8H z;%ROM?+&C1{jzjnYYqQCB=|r{gigQORvq;e&)BrwnQ72FJ>Hr1Z&m^7f^a2NyOCuegZh5*URiTMb}iNVC1*RTG#NwN1I~ppauXS^R_AehJ6HHU~GJ z;ydIPE!}G_Vz(aFsf_cNc((eel!rqYEUtno3HW$;_*66Dpg1boi4-wI1}D@fS&MkS zmdr=hWO0Db509PM$!!t^#wo-lm3n-J9-y+9Uipafck*2UR#V_;mbvU=VG_CS#eg3jGkKRdhlQli85j=L=7aBVU$L)`gZ-5lxQ| zd^`^PDr~#mazaP{rhHEIVYyE{$(5!qRI2WGIvE`e7`g$<9$U2@ z2J^X6eP@**AChJ(MUust#m+|o!u5@+b-a*HUSeX7ou1+)4bSAa+BD=*{p7Q3=!ZM+ zrqM<8lx0e^b2Z`yHo_M~Afd>kif%jF+Q{E!AhUPkb0Xvx$WbhyRGaU6=1X_6(B-Pd z?}?ZErUO=cnO${Wug9fE@ukb@Cho}_QZ92)ZgHUplhnS4w5L6~tJWfJkS5AYM(_Jh zhjnWOEx>dLJR9Hp&M`Te+d#gq?iGQn*`l6-qvPNH3t4x}VaDK2q?M;M>3_)9b)|T` z6k`*6>VhF!2|xD-aO{*N5#R8@7HskG=zh85=QZs4$IDVEtNA4cxFXIK10y zj!$Y+be7)m$zD1jDz>)!F6-q7{ge@}Ef%*e+ZQ}CUS3LWrCVW3u7V-+A`CG;Wt>aXij#lDFVJ-<^O^5+hY4&vhMqiV!15j452Ai0}cg+E)%Jy&O`k01(1rF zDG=d+AL$kuxDSYjm%(eTDz*Dxj%TV+DUxRdqr|)drqlP%yVpfTCO6Al?)-o9V_goAe?v2sb2O7}}Z#BN!8)v;$7s*$|JbL`_w8KW!XNa3`lGC^{x2S=C zyxbG{EN*Lleb3OV9nWb>Q_*I3&h#bkqPUG}yDdAtyk>NUYxkv0oIgw5w@_yhhXP3- zWo!{GZ~2Dh{+tq-{M6scwm)F$sQci5<|+Imc!?K%Tl3~7XvIWTJtG8=xcp60#k_AL?sm<4DDzig+fG%n#<6 z?6|qeC&ft4L3-CF6V_6i?3U4vH6Fb0_>ed@`vGMgaX7BmhY9h!&RTC=zs`9!{d&Zu zzP|pp@BIgpOxKJ`T*u-*A{ z5g$s{fIS)SRB1ErgcCLSAa0|{QXbEY-0yUQPyE8Avf3|qP(1fXJWKaa^1rBS=162f zaPm-#bZ7mEW3w^zAqUI=a*!)A10W*6k01<-D}!=e$NL`zHzu?GDP#b4m zk{>b5RL2CRVAoM!W2zoc-53?K_ngWJuT*|k7FkGNy>p$2AOYW}4R$O(yh?Dre^$dr z`qNtUMi-_PE8Us*n^uaZ?jV>Md(0sFa)N@^9}!>c*XqTSnnafFi^rrx^QL@J)19=W zL=K-?r%a8$Pn*HZnW?<=raLT1cfCVp(R@-2wOkqPV6$@3xjFjpoy$Jjt=#Aj#Ij4SVQIyaVUKr~75@YB`R}OoUmt$7l)t1(#Y2|BspGE}kzcV~Vf*hGWv_RY+SQ0Xoa`qxXo0{3v&C=Ew| zly?7Rl$wlBcpX+WN@mk^OzzT%BN1LqRqR2EzMkLDq!MIDQYV`@qag~tXi8sqY@HIJid2u(58hJbK< zXVu#A``ZAKeF>X~vf3$Q%MP(XYaqu~u>6cA>3GN*G|m;}>TDK-Om*dgHBX4ge|{r! zti3x_GnAS&f8?;_)J9u=Gm{_eDtb?ZeE?8gwBMDv59QbbbbSs%v%AH($}b*1m`{QJ ztiE<46}QI^`kMy!+pEg73m&2GVYS*DZlC;M6jN*?{1!J%aX5v9|lJl@Ul<2pQvI zdbq4dddEDX#~3;a)xyv#Ymc>=ND(XWl4#BJ&gWI|z5Z2v zV-ke4sOx|d^WJ{GhHmv#bQ$f4zw5EAjWh1%!o|^*OR?Y4l~&-nn)6jZKE~Qrilf>t z+d`z(5Ct*zcFlDC1Ty~Fvnwis`T3sk?=adkkuEhBaCjne49s<17E3-_~W!Xsndu8Y;c&iA_>5^rG4KT2#H=1jRvT zKQvN)(G@^h%Ru1M>T|`v;zeVCjzD#=(Z=_uXYhkxO3?cc3NgsXz-=pNZWmVNsE5E= zTdtXxi4*!V01t8+DXDC&<)MRetf3n=amyaPhfRPT?iJ`M)4Sib5q5!R)G_?EuFa%! z4v0S(9ew*}I-EBg&_R!7BHT?0HS|6=6BKK`wST-(Jn>hzK z9WmRq4M&^{OQ(K6E{(N!!Wl^}IwQ6`33gu`@)gQ^h+SENJ=W%`ISk>!dV**6TL#c7 zAFjCnEE4~hNZ%$V{k18JKY|3wC%NA_zeg1CgDJ{Fwo(gv&wJ)O<0&!#fSJ|W7G zG0(<83_>jwL&TECh5-XW+pFWM!N`5Wcu4|TUF6eA28K{qBXhT43tt{vJ`uC00zYCD z1gMp%4B76z2$`qex&w#+S&XvT6P^t05JyR0KlQU^JU3^4UOZU~F??14G5KZ zd2{TNN+QSqHV|U>z(mTGAU^B#xz1MNR8(%Ed1ojuhqtM>bha_EgLg!8z1qhScDO<{SNzO$J;pN3S0>|#bhua7KTy)u)#eeC z#h$MJ9st*}cX_(BseYuRhE&Du?;;k`T9as-Y#qoA|K5xrOcS9<%|dAjcg*V&TdKgn z>flAc%sZC8C}Vx7%b-m$k1hzC@!E3KItiTTU<;XQH4M--D`9RViL=@TcjlNF%3DX1 z*JpQgt?XehK|^*W6QC|CE*swE@6m9=V02(GV2Dal7`L&1oqM+v(nOJhx) z2OBeC`}-5`2b}s&J&fLMm{iptVJQma)#9RNW^EU91xqIR12`7EIKX&ilh*}{D9<>iUHNz zin)Qx9!mxR!XPNEyBC3sv<~h&B&)VdRwN-k#uHPUYR_op7~II!@Ie0h3L3@G;*ggv z=3i8N+I&9dmNA-UMz1b}XJ1>+M8z=90U3k=7vm4fgOLw3@{4LWhMNX=^Gx;@AjAUB z{j}LW8yY;#4Uz`D{%ag2dT|7fZk()uw49k|UZUWOGlwf7{;&>a2nD)?W@GvgcDFVc z?XtqIedXCm?&cnNMiS&-c10G~f@w4#`V0HOzW}~fCBfhNZTJ(KcSrCu^ zH(u{--M@aBGlFQWZHG$;yE4Zk!4T%w3LS*0I>MjTAlqMn8CcI=5`{W-cwZBtr53Mo zLw93N9;`Mk;_r5Pr~uNH34#~>DM$QR^Kvy%J%1z013B?jm2i1tqBS}eiWlBm_AqS) zuhn!D5xoInv3CtYKh?nPd+p#xFMNNb{zNa@;=Aw$@j@MUTp#)P)T?(QbRw~}-iuzc zG%lmAfNEmm#fgF;5jr+<@`Prm03OP#5!Tu``iQ%7?cGDPmAP%NzBDZQ!e2TkeC+&- zucdrQw1U19Z()R{O3F4j%j6a(Sq*Uo_06rI3YzVGsDEKk~w7$}kqM@OXmbA#~ zNDT1$-tqq4b=r61+b`an#Z!uyyqQ{5^=8>pDqHl~8nZWOSFlWAwTQ6zt*})JCT_Ja z8q(_9Rg*uexjzOXXxN>7G`PjVgPV=FGnrO<0~Lo}A!VUbUAbq!NgB@Cv$~1*Ru4KI zC<{FjoKK(ndG?moI{boj9&H4WpgOe#FvrOAjm{m9DRb8HI97b!F`idBzlWKFL`FB5 zxL%wWw5fGyn_iDls*y;%3Bx`p37N;0ULNFJ?YExltwv3pW&+M8WranF$`}qgAORbK z+V~3NVQDT7`_sVwmO&hsO%Ehzp#p8Zx~-Nk2+?CD?4KH5PhfUG`I+MCmoGoIT041I zc8CV9CPP{y6qpwqkn)0V7q^m2-Kd1-5{)FhP=hGdWd(LjP>46@Fr$Vu%O zT?zY?ML%*pA-%?@1XTJv;z%U2d}^X`Q&WX;pur}vXPGorGm6d0d+CP>L)(`wkHvkP z-t&Wnp#bfgDnDcMSFe=S! z%&o47)6sjb_ar@yU#ad@wHyS*gRpxwdSlNCB|i___6x`afOvKxnzE-wP41R@jH+_a zD(}vZI3yo#G`k!Qa^W#RV9u)5vfQ@Sk;QuFnd7x@S9^UHzDFo=hU2=Q_bBlxP)CvY zyQie+!EfvI^RN`if~*w8hL}D+qYuV5c7%-z3)sd#a>mnb!gckGg6!kz0JzMIrLC}S zdW8V7U9G6NO;o_n0JqY&LZ7 zgC~kkwBjKjmA7<|s_=HUy~3%pq-j@wzI~5wXIZGKO6_PdzFTw5!oC9V*{Ph)?57G+ ze@Dmhz;#v0VaQ8{8$1(-d?$Jy(ljmgH!d&UPPKUQ0v)phYtSu$v73+!C8mtzZ|fCx zAYb$a4c3#Z(_IZ$MR(RCTC8L|$D7%OOp;lG;e0YRh{;wGNhH)WeSE6WCg=fJ*-{bv z+WaPc*noZtX2ZJsuT@oCCIwb9)PEk(Co1QsQEjDW1knWdH0A0nDUM*n*(+S;ysxoU zn~NnDo%Ia?eBK1LD#9x^kTvD-QTi~G6Di#3a?e66OPm%-%E6o<^Zwj8W65>A5~0XQ z7mAZSmYwu=>2vrsIHjeGb$px?wmS-tj91ScAGDw1Jld?J32X}ZV}pVoGvTM8y`m51 z_QBjN&T0y!0H!M7o4*=2f2nf*=v2Q|Nlj&)>~_gJx40sXRjbj7!F^VOAmc2UX0uv! zJeN9CI{5_~Z-e^4wj7dkM(a3L2?)(j)2o}NgFxfU9_G?+amT#i!m-SgSV4>K_lJ=)E1OVl23q=A|1`0afYG>hcT&9R5Te%~Y+qU+3tTaefW(FwpU z*X=wW--Wcf{!L0fW9lo@35o@_3?H(E#I@V1eH}{eE^zK8A1AMuq760&Yi=5DV%9(c zhA_{NJk-JqFx-8{i-EB=jL+@(kx;#7cF*YGCdRKu2oOuq zmaai7WZn;*ft6@)lch8ol<{Dt#l-=96=(jZts8pQ_NsJy=F0{hf^VIH ztLRz+j?jj<;lGrdz*pNRf|J7PA@)k%`9_t2Q)PsN>_fhgjb>CIFkp?g3P?< z+KkG;{Sgj`<+`R8cvhEiWLcmn2C*ClR;M*ua zsrnawV{o3IijEoJo| ziI_LohtDNH+Phk2-fjEUUD8JDAV8jxWULZkG=jqVHrMxvinh@&e~!h^k{$=XJ*X!K z%rb}B!r3e+nV(8Q5(~Nd^vx2iKl+dQCNmbABB*=xggRI8hLK-Nf{#qAAQo z>-~Y>13b)mTYR}5HJP7RZ5eELLV!Km(~1$dyPp$##tMY^K#c2sD26Rl_m_F={niYj zS8;|%3r0uIR!B(su2EPag-Jj6E)V?Y)bQyyq))xev{?JBm$$^JRHzX`ESSqUt#u)T zY4uYsq+>2pcrx=G8IGRk_6bRm(Tx@CVDLV??=0zpKC=%D&$6vj@Q&N`W)z5K0jP?_H+8W>SR@iFb}=b7O!e_C-q`5Nf$jR^ak*EPlInv{ zI^t^HpF&m1lS#>Z+tcauRJEitw2#|m;4@D|Boi4|Q@vzs|+&4Pv%l5@*+ z)MwTHNf#Fq5)VeUagd2KAYm4d#ZTg7gxY9Hi>lzep#+?KUDR$R~A23F^i_=FsvWe&Eg@J zVksuNObD;+e0_L=95Hc$-4WBpv8(}j^6HRbUV!`8RN z<;l3&fCo8{oBpTGAGii2GEZWkr(UirGBu#o=dvZgK#ag_{ocMAFs2Ib;z+zV@LyER z!1|otVvAu|*FkSDaABobG|RwidoWcB#qVSvM(H9Ma#?Dtl+m_;w&zL_SQ;pE+jpwc zD>zmBr^GH-(OOpc>5^)=HjuJMFi2&j*huLDyUM5PboX2 z;@Cwg(x3xKJYYKMhn;gu{o7q=7#1N7#)E)Ov!db9`(dt_GRMJy496`MI+|_DybneQ z6Dc!3F)Y6(1D1@S*zCTzg!|}~1Lbs>{{`oLUUrr(VsjO$ezK4XYCKILL_xDyDYHr# z@%r+ti}l{B{%<-GAK9-+Lb7iB1V(nb!TqV%{EMdZ91)Ix>@QfSfW{zFF=#sg2RHTb zDHiM73Vu;8{HlxnLHkKT;ihPliXQ&if6Vd!!xvqxjT-;{f58|1{T0s_W%f!}%@4X~ zt(x`vC&3>+n**Vq*>9hJj0puR}tbK$N^%&X6M>8e+MJQT2GSm?KELlbWKcPK$Gy5#H_n0}%8GXnyM!2!!< zv^4?u;&FC&QW#G_UPUfH$MLS#2c2#tbKh!-T8e;wg~FsWx7gyS(L@pQG3oBqXAlKr zHwd&uk?k;Cd?WhXm~Yo%Jfb7u>a6L?Zp;3_d-@};$%EGqv)@(y7L)YUMK7r5?>sY} z0#K)3R%pH+H%rT3Xt2Z-uG5ldkgi*rc1gJVM#5m`J`pIe~dRc27| z?r@P38o#({KqE@-Pe&2nL9{<1b_P(;$Cv8@ya1u#W?RWUHGnYg;k=!4z4}a}LmQv7 zxeY~#Fh1M^q>^j|CRs#;Ko6(q*XJOuPV5nHboDt-;nowPmsr8u;TM^0xa-4b38I0)&ji1K{& zQZTL=U;U#Mji4~{=3yR;W+W{()>#avRAD+lA5|+fTJs(Vgo^GfXJ;O{$loYT2Cl{t z^X8$5!U|z7k2Kf?bMNtSTF27<;RPP#c+#|}-of<+z-gEke(4H99?;Pz^+->!^}%GM zaCz(T^8A8B$sT-H{EVrdT%0RiM{fi^lB!Z&3r#^k4E)xj|i(6 zj5H>9MV+j5&F@}@@&g-F?9$StPLCu>rM8GeADAZfJmvM_aU3zeIuVsd?YXc(;t%Ou zI~k#vJ<(#!8W7sD@Q}w*Z`ZHn^{Wl-vG+UTSXm;T;y-?e3XR7*Gv^0|hEu-0Sg(;3 zXuzU}Hc`CZCXT95<5VEbgfDbXt@w@%i^Z+@7DL1uj`8;g*p}=rarj~U>-p1Ayinq= z7KMzx^ykamX#=qAtS)n6wl8^aGFBP!&t z&8Fvk9&WMcRZfLB6gyozJ+eTF)XUvpUrlgsF?#!f19;ZJk8g?~Tb$}v)=BD7A5DyL zU5gW7qoxU;lqmI}eR^z2`<-ms1ElXBVzB6i5HH?m-p|CD57Se$u`QUoIFKQH#Zsig z!}<5YJY3_6Vnv56Q=OKW_1A%IBJ8)f@Z1kR`QULA^ir7No?Hz=Oquq~(+uD`+6o{f z`;>byfL;t{DPwLV!&e2V_B_QeeS$#7<*L{Rs4y$w#AX}1HB_Y?!JL2iJ#0ZtAX6%` z_d*`7)XCcd1qRb~C901Pge!Eh`f@hveS#usGQBiZ8hVD{pc4dPMTx z@KI@Gv6xG&#xszy%wjugMN{l|iRsl|I2{Z>vq@WX>|&x5 z0W-!6>;E15wwBS0duJ#`!yA$ynWtHCl;qa;=PF25wsum;{*@hHGjvD6O*a>i{SlPmMfEUWQtkKlkusVB$2Uu`{#4mR1uObaecb`QM`BFmHVk4uE z1Og_I?rpX3MH7>A;+*~E)Sav2h1#pH3h5B2=H)ybueI>kbW3cY%A>>8{)KU_dDKXI zZyt1f`}`8nd^VY*w&G$U)BO==Tr@w5cW4#kRAAT}x<{R~rB`Ey<4ECJj9c+taH-L| zgy0^RGx%g##gW2!z|jP{Z~w(dLaaYKvbc2gIK`1bUWmQTHL;)?taxslF$^YZJ4(j391*|D5a(Kqoz!S;F@w8KD8-PhJ_z-4 za)t6SY>5MdGAmmvGMSU(E_`F*O4US{PR-;15efjVfNjW}q1e7$e*ch4W;KQxO0L60 zdRsv-COYN13c68& zrT|`=jzvXWcM2xTzYnV?l0W!y`+mZwcS#Ls3@W)n@J+%?mJd=UKt=1-WY7Rvca~+g zuX%g4t`EJ7Xb{$k*E5z{=Y*obAi)w5Bn^K*D$7CqBIGY*o z`2);=p5p{GW?!ys^~cAC0KtQY`a4l-u=W?(;uxtg9*!x4yAsE0=<^4n!<;QyTEypQB8Z0O6qe{U)1_?GSLyI`VMJA&ML>d}ig2sJ`Zt6O?g!0)|4ORqz1su* za_Tio@BZ3Fb9jnQci$lFZ&-xu70;4cTpPn?c$^{RGgtpDsO=~m#AzzarYSO$9kuW=rk+xQ<6C{W!! zIVvQ{fTguggFMIZIkG1CnFaI6#PUv;Zk3jpIsKGSooJ=OH-Ou2NskR(OZN5M+*nv6 zlxX{ev0f;*@K;Zo#V7JYgGyA0d`DiN0;1_=LN{H2y5h95m0ZXR?$%b?W?1Vn{Lgr> z(ld#za0nwLBkn`!F;#q6yItt$QXnr$T zS)|Y-bi;iR6r;z$8?eQ!<>5ak4R+ugFMH$#-7$lx2Gdx}ON3ra@(E9c$Pr-h12H)5 zukmm=t+$CMc-d3kE&M7r%t|tTa<=k`_j$< zcYha7rHlNmQ5U@=-f3Q7YB8V~i?5G56u`n4cp=M)(axwrUgmtAl3^s1!8h5b_Fblh zD(^tJT=80mo9uS}+rRfyY7d#qCZnES)GS4SX>RgNf`ALH5W|k7`7-P6IyC{ywsWb8 zK=#!FJ}*j`4Z?an^Lvd%r+aeMHx4!aEo%{{eH{*yY+LWL!r7?g8ip2Q>+b2spMy3$ zBHmmL)GVrDJ^1)Es#71gSrmD-++WE7Vl;4)UYfWC!xFhX)43>phJOwC%WFJ#0awb% zGzlV>r{utXJO(0uY@6k>}Gc}Ht$AwdsL}ZM* zw1MazA2R)2^vgMkRm+VfrME>!m*P&y60;qFXgj?u?MsP-pLO1NDdf~v6(-7t@s9nm zI@$#3{cx$l`#sU>8=upkE`-rt+N&cnu3bTOiLR@g#@T4Nd)4`ieHI!P#+sEggMOe@Gz-b^fX zdGoMU=Gbn!XtoidW6HmX^&Ah>6cfxPQSvwb?SE*zSn1Gs*zb`4eyXx}-z$8uVk!E?YA|Q=yyTAK{jc zSgo6mZ5<0s`XM#WVj{qn82&gMag4=pKa_y%i1Ymm!o3hE_?9^784;XxI;5m-wtS^s zY*9CsncS;{`AWDu!L1zstz&0m2xW_%PTQ2LjPl?uN7B2SXWPA4sq=4^Wgk)%&yZ(M zZLL2DdwnF!MZ}qs++{p{uOVjs?D=}k7v5a)ZaRDW<@^ESTLj6^SaN4?T-0&%VM#O> z3+B4idvAJg;|F-of3G%;wpt07qpO)A)cErBf~ia9=MF~m;fsL7x1|A~n|Jf?=F6N@ z*$Brj3at&G2C@~RNmHzzmZCnP(dEYjqO}HT>0N?*XX#>ITuCMYp9i#Y-8J@4;;(jX zngqLG#F-FW!>!J5<{bx3tJ?v}jE&iTcT+!9u2VAL-#xlheb`L=$Gkb{KZLslmd5%4>$o5+@w8xYUK^ka2auEY zcXh<=wL{cD{j?^lwkGfvt#H&HvIG0Zx#E^~I`&Zb8a|5TsTYcHtqRSsZkh;2szm!%iO>jYz=;e0g&%qP1%acuoYM&dKFrOO)EeECkb&{^?? zULO*4e69F?_=tPRoW3OIA?A|rTR;i3{+(sa=m>df_Y9j}8PrNLGF46`2FWe1>E0{i z@76YEVU^hWX&uX~dTd_N9cH+TWdRtxt1AV(A(Ctj7rE1avA<&ZQ2e1o98(gCFa$Fe z!s2uxAX_XZw)K@^LO%H@5B^NSid%&A=H-wHtXcGq%4NfhqS%DNWSD_6kw1LL0!BD- zLEsj0qXx!r@#LF1Bw#!*i_>CQ4X}>Z$3L-U*@95sY0%D$_=ysj*;lfzJ>?VM%9_wu z-Vze-d%~K)#kYug$nAK9;egJmA%c=|ZfQ#H7s|9dTP74TBk@VA^l{64n&C*DabeS^ zDJcvmPm8Y*Y?@Tx=;}p$_IqAvX{qNH2I_kJ3VSla8vsInlp0*o*xAw-pBE9~&gees z5MQiWZzSA=#&26E<4Jd~kU1|k;`}a|+gr4v?WmQx{pQ^XW@VbQ+(_mZ+OS$a2j|o4 zb&wiG%5p2zr^tY#c^x`|U-Wgcz6npCaziD(uUH{i5W95yq?*(6kLZDK1B=`R)EL8A zu^ew=>8?;izDE*6RR&*f)v24~=Ogh$_%OVge_etGe$3yMwwm&}XbG|)<0@&O|+?(KQsm=XPRG}o?oOW=Y#Q+hd_ zL(kC3E_x{UuM3V>uX-fpP%R3Fv;AMvq`e*_*_5H`9{FlIYNi+mrjJx)%gwdv8G0jc z;X(7P;|If8Ku|Y()|%+DhdlEE<*w?S;`yqI`020O>S#3o`p`b9f!_Nr*6V2GNu}i0 z0_eF(v7SLTuKKY!wX3;ii9ra#NtyB(t)*I4-&lOfOP8YS(QSoZI~TdiAdt^x+#AE; zL)XUHp_~DL@(NG`WaoY*YdBUW;5GEZInaY{yDjw`asfgkF(%UIFeRq#vFMl3f!=D$&2=*84%9SO^AFm8C z97P$9?PT;exiS3UJ7dvpVIM}RL=4FRmg$ zDq*0J;J!}N5*0mmIssKlwxr@UPttl3;V4IC0X0CVTP*Hnb^8R7tSy9Nt~PjRdMz=u z%LP*rw%zXYZPiv@QY?7^Y_PC-!p##WnlmT=1a%FOn9L9t67ywIn7MeAQ`&DSW7^~W z4U$7mm5w7U82p%#-I87A2mJF{%LHUoRtuflXQ7wuO_lLvDgtrmEqyS=9x*bgyJ9Qb zCywXc2F_0foTW9T*7S|9kVB)24f4fpW_4tXz26$^AJ9-n630E&WU)8XDYw%F(%6vDxaM{IflbLVfKjxEi>2BYmtScru~m z=q_byvpdPS<~P*XsjD+6|0~(&we#pWRJ=*p;e;^Uw@*y7Ks%+ehRaN()cickvG#1& zkg8}TNz%kW2xU*TXPLLbPwIE@R}0YM4rmqH{n1F_@MTw=P+4+sWtv86cFj$E6twFl zsAe)BY2-$QH(MgTQ+--5CN!f7;_c*`ES|(KJ1?QV*+3)5Nwi5{aO|%pO(1X+HKn~_ zjV!T~ji=&>`Rpbz*;8jsW-pU|;_k=ye+&N;{}e`uDxv8w&HU-1vE~({l>W&KT_OG? z-f&zS<$#rdH+)Bo=z1Hgwq}kM^y<#L?jCJB_^fx7UL6lVT{F9}S!v(HYv?(rLu!%@ znN$9<;juLrQOo(WmriJVA|mg`vp=PE{W>%eTLP~yGizTkrgYOt8{nryaq(=>aXY%} z2|JOi%^i?Y1b&LWxGvd5>BPcnEnYsAo6DSpVngN*)bLJlN&S9Ebth3)T_Sr>;;-qi z6ry)(^D4m+V__=4sp<{y8+*P9Ga!pY?Y@|r0%((mYr$IIwUsnF(^ilvBuouuEH{eG z!1#^3cy+IuFei)U)}ngf0BKR9`TbzZih1R&C3IMGEFPb#RQ?9=<~6aIF(n=7{<82n zcy8JI8KCV3s3-Gmx*~DP1Yl=Rj))c}LWwdHf3U$QzQgPN6YV_2n@m4VEtyMGX==H1 zIpRT^`QX2j3V(StWhLg?yJ56&)@L!omZ}$F$~P!;^)oc;*SotKP9o@k7GaQBM7XGN zn_!iQ+}O^{$r6zB>kLg#9Xg$6$7;)@6m@tm*Rb^qe!dzzV*9@sdk>(dw{?9OL_nk| zZ0SWrL8MFXB5pt_ZbhZ{PJo2oiGqMg6R8qa)HrvmqT<-ZMN;G5Rij3jkkJX&Xv`V;&>si(I zM22z=gTdCqY~YuvIGq)?BN(sD ztt@^ys+p+s6}mD3q$Rq3jZZJZcQ&?EWusZ!xhuVJb0WKJvn1ohDQf@VQlsuXSA|h{ zg?e4{ETFD6>mJj{%B+mn>TactaT2%Ei|h^^f4^fTJy^72V7!>^eENflCk!=33oWH% z+US`Jho+8p%cXAM*71nviGy|m;&^4Xq{j*|RH&P=T8eihzI=%#lQ~JYLv5su+&`Ie zWGlqKw9V>%WL+;{YZ0{i*+k1)sLJKPY>p}UH3i7bg>w~0>wU>H)=PN4pc1$nQ`1&@s3)jcZk=hxy8-wu3-VOEpGJJ zk&qK&sX|?NEvpihw7MCFI|b=Y#J9qtf_GpvwS^Go)0I92dW z0U5b06C6Er14N=hhI|5G$!P5rq6j82v#rsbcLkZ+qha0iJlx#e7(MNGTPRB_E4q#0 z7ulla%sm&DGzx=;nl;5Qnm({fWhuvwfP@Y$k*)RquO0M)k$c5KvGE2gA+}8jLqQ2fX zD7m^CsG>O^m*tF6Oc`aD&4as(7A|E^ewUAKn?4ySYmXM){%e$or{T%CZF@%3G|1-V zb|Zefi=ISGyJx+baeP#UUS4@u@)|XGY&+*=4Sn~ip44^YjOeTRyMO3x{QZ{W!}GQ# zl~Kp*s{i)wdhDcdlEl=^rpvV>ieELaIVRK!Oy|;vBy4IlN|M7ba%*tw3(CLDvC@hI zz>84?S74L)l&XC(ateT{wRctE@_pzB zmcAuUs%W;tu2%6{(nk4YuX04l^^QDTfy|auY-_HsRj)@*az>2#zjyXOJg8{sWL2PJ zs_LyreCDrKY(Zv!w$_?)%_`UL(&5AR{>HA2Dpk$YJCL6}W;8u6bkcfI+&a3oq81!! z2q;5bbj3_#nb|(EztAM{rHm}cGY5es`7Hof=EuAH(;k64I^he`%%36cj{==^!pO1C zJnj26H1F_f=2rxoLdz!U;?;c;j6Ns3E|?YSL37dD$Ps*0u$@KP7pW34o%2roY~U5H&ek7(&pUNxauQfB}o zt{h&R22)N4Qo<+4(TdsaQ`9uv?XXtx_3x_Cs)<}{#-0j`dypcdJeH?%vt48p18IW# zOj~DtCkJ6)RC%h<3tCBH4e>$bX^(@;w}13r90aZth?1sDJw|m=ClL*^d|Xd2VpoXG zkz#mZiX64Hrn;?tvVI@8@q7vr_|Ed`Owonl`fahtE2IO2HdH3s1Ffm(hPKgTslT40 zKh&?MTi8$?RXV4h{5g=zG$hff+>{qo5h1|n1q6GmF`EjOM5nyv@0d_Z+j5 zlau!WhHr98q4rZ1%PdJ>wnJwv)vsJ{>xQx#EEM!9Hr0=28 z6$AHISiK^@H){sn&ZD21{C$FZzY}jvq@Nc8)cyw_@Y}Br^O%Jjd%(GRFLx9xQ! z0v2Hq3heVUVb2k>(iEhEBRPUvBQT~&D6$`L$o4>^iKMHRXUV)wG8p6-4%0^}Lzg9} z%`rdl=&7@f9^j+kD)f^F5B|i{Ny5Lg1$>FE{k08V9odG7K)PqT;f>2oL%X>vf-_xs zM&O*6PECPkx?l--g+C@;ir`w5{#_O=ZK+7^c_&{BV4l=JaiX>og`u;p>G03!Ozx2Q-sHrQ(f&uZ-DLGbH(tmhDc;;2T^7D2$ z86;ez)=vly$xSS0!0T^`vkaps;a2t)D254$gLCYjiTqK+pkH+Se1NNhmGlcE2vg?L z=8f{XbaleSFO|(9FF0Q_h8;)Ac=eZnV-;tm4aV&k&VTpEU#A}b!-}5c-X*q+`802V zbg+{gcWSiK1#n0RGAdKnMzby5&xC9fXzC-R{TqsDcag&L_#7~34)bZw0xjt8QwDBl zDxE@Hv`z|{KXwA%B390>2WE7FP&z!p`Y1bkRUHq?81=*_HWyV#BKJE z+0hCe)dG=Dpt6SnCc-^b=3x;xotr+E(ce5-?>Q@OA9+@J(Dki%F_^#Y8*XHA)|+r| zr{De`U3GYE`X5%eqZw7nLMyz?#0+bQ08VIp4F+p{fa5!WUKa3I!kum#K!*t#fe!jD zw~2QIYXxl@DeHX#RiJ=09#pP#nSbrnBh#ib$MDrR%0ykJeI>%CGQe6^BE^!aXOg`( zVP*8ssVX~lSQHpEJZFt+CpF0EeIzIl-hE~iC2lbyCXM)kzvVhKh|X#OK(ZT8*G&E! z&UgXCS8-3?*8q0$afzsul++TkKJ%5apomDNB%b&CdReN5(ebxMd8|skx{&Tm5ah<` zxBhO{>P{;U+=Wxr7iNcCXGX8z`u0d{sKJ??@Jiri_R*9fPWia{nMK!5=OP~v&J(yChE+r<0);}3L{fxBn#Hj0~I4;);$X|jA)~GZR zLLRd_VP;0|VLS_kjlNB|HCfF&__l}D?A6oJlt48A4!`2tgAF9SfzGq05XXI0SE<*0 z@!kh^n3hVwSd@%T+l60~5xT^jMevS&K$-K?*=>Adw?~sO!-^+Z$X}I_1=kF^6t}s> zMRC`sD~W<~W?u*66_8_oAgcQFwpF-5^hn)5V15qK4lw6Or?Amao$JGT3-QP22 zZP2Co%u3T*Q;j}KVph)pLeZK8YG~cL{|q&^AxTmc256coar?rEj9Sn2*AineKmprV zalsJP>|mq7TS9PsiD@?bG6wT9#F?6u4r)13RSQ^lj}|Yk)qz&VNbecdniFNakAa|4 z7zgbXl>WgI(=x5B?Bpv)|t1&%jWM2WEwwq-JH&@xe>@*!%WKGfygBZM6>?TNc|K$TYCGqV}Ei-fH{7^ zdKbv61CttRU@Mvp7YGr}`#L{#UCsQrb^Bk6#dsPEA;uqjLZ{D5S4+!) zzH0;7y}L8|XgfwM+A>pd+@x;vLcDQ-EU+Q^!?ddU#ETkwheArFHm>^8Zg~uKlUwGc zxFpxHnV8ofTMzmYk1EV?`5K4uNDRb4h{-^c1l&X&fLH_pu=PvtNC#lik3pWY{=64C(L57zFlKJsx|9zhu&$It@N`&R1`WPuX(&b)I~l;8#$~ ztWse+kE^}M8K;)anoYg1`@m)0q3L~U?WU9?Z* zeZYl#=7>(rp{E@+5L^C8KQN235iD+G{vhl2+h(l6R28T=0b1=ZQ%06R5h=!KU89JQ zFc=|bdAsqj{>tX#B;B_i%E%#&A3p+ChJNc$Ju@=)S;=o|MoDmQ31{4?@zY<&)?O#u z)@KWgpSHDaoXZ&;&LSH~jrz&a&KU;$dNn|`m7hk-5(sdL#1G#WbXq>0d)rqWm&*EZ3 zWUlc>Qir?q>Oa)O|Gdw6Ir}+7o15k~Wxe?U(5p?dEKSmlB@mS>NMD7ddwAs^2x#TG z|1lZtrPk)X(^|qW`5ma_B0Q^_4h>E2K!cjnF1QYw=PB3`+TUgdIi`t2I&RSaEw8> z>7tN#%m zp9n?$rBfb_*AcN?bbFUI_+&`W{*#Wk51M<1?W^8MoO|wDjF}XvRSb#iR4#I7_VDK( zR#fyT&y43TR@vCU>T`6Rna73mrPfa6wXMO$tqg&}^L}uek~Be5`xw)W#pqY->2@(Cwa-HwkOaai6J+6nm>=ZqiHi2q(r@=3{`5V*gNCh^qknRpPIN7Aby2B z7pxEWHk8^6V6IzFHmWK~m97C}7m%~=htEh}&vdsz9aj#}k!x5bkN1=yk{tp67^hSB zJi`>{bGD|nK?sBQ?t#J8((U+&dI-1w=0LmLZFaS~ROrDHfIut*QWdKhH?8NKdLN^6p9LZTt}ir+WOY1^(s#8``EXY(uQDj=8pUi#k44- zgr=V?kOWA{)H^=V;BfTdtpPsdTz#FL^Yh3XKM{bmrSmpjG5j7T;)63ZP)I9bao!teDlJ` zRpa4vh_lD!7Zy=$aDhQgIERlzD_z3<{p8s%Vu}i-oq$cT^S0g*htB}z=Pe^s+n$B{inh2W8B;Q)q+Odv0;zrKjD~< z85tRgjTdAtF+nrCY~8pE7`&q6x%{~&$tlaUEq%m7hEoD;xV9{Ww`w_gMsW4~^{%z| zJWVs!j>=0;IySZLkGoT9k`bpH1*egjDpCYt4Pvcyv{~j*u4G?Ll@f1j3hoq{lsf$^ z0Amu1%N-;x>q!u7Ajs0`+}P_c80cT4lqr`ug>SqI?CrGNiF{JJn;j&heH%iIRb zprE_UK`HtiDu9R8e6ag(9<;I9>y^f~OCJ%tb1XWwQWYKlY4yyqz)dMqy<;+59e z%e&{_4^_D8J*=*aEuHvW6LJ+NQd%3{>`=HSQM-?AwY-{k;{m?I>%UHmF==_9b$vXw=iQauV$+dBetWmxkqT{}9V(2$QVf^FoOXGBozW1YTBKp8vYB_b(J>ccbMLlZi@wf>bo~yW-Q>tQUKr`v;>2 zKiz7>k;>G$Lvf}1-Sni+^W9?S;IuTEPh+E7l7leSgJI;2Xx2=m zIo?o^eUXWd)Y}g%de*x2mja)CdlCQQ;)UWwz|Dy2ncgJtC0$bFam@-tSapd)iA5g> zTi8`bFJVc_Wz)-Vp^ojo&GNo#LqhI`;hoZ#NWd>KNh2Ex8Yc1DhxX3NksQefAa=wH zbf08v>eWZLHuln$(naOSRvGm`31V@3#~Q4=L8kDMst_Zy#*^#lBbI6RJJ1Uqhty?7 z_4?DZs;#g2)orctIky8^-xu{Kb;SyTv%J@Z21^+86odGJsr^DG20c%2z|=6oZMdS7sj*jH3O zKgyr6b2x#!OzbKePicnjjg7rrc0hr!5j_N;b8$II(3*pRs2TBKqJ5GtngTq>ef)d~ zdmsfh1QC^5aOHdTXBkX19|eJTE_f*9aq1*~^`H4i0JsJG*yrs~-@~+w{zb+2S}VS^?ZZs1}6X=&x^0QMc?kogY zy;kQM!_VAaFPczifQ8S_J=ObHhxes+i6$?VjZUf4Uz9*r9a8EyvJ=&@oR+W93@Y+I$+vyIY#b9Uv(1} z>7B--&!0OjOd;9)!Sm&6$yry<^CB9aFD5wuvjARn` zpKs|aHy;TK$YoGYB(v6igBD$y@+oW(=02IL_eftHOH(`9)8#X)uTlk9d?@OpHxN7$ zLWXaQ=m!f)P^(vSN>+NfBr6ze;4AMVN&VGDuB`=cqM0rp{Db%7AI|^V+ft(EmjHFl zfj)Mk(xBW?Dr+p1W#PWES*z+iq)O`Wi{*Jf?qGl`e|YDG_rwT!#GkKHo9Vu6zx?gT zOub(&*rPWGmFXym{?aSGi){E|Fbb$94paJ8DE5%qCu?acAn6mW;+UWS;tx#9z=Z}B z?rFaNyc9wG2RHKN;zxYw4kMOe;HEh@>&CtZ#BsdRmsqDMLR=!0R}p@Ajro%@P%1*~=UvTNgEwY%{_m^V`}yF%xO zdDvokVAJ=`#=CnWJBYxo*!kt8Zj04@_MU1gu_*TL1F;z7$K9Xzikt~qevQv`HN5Q~ zSZ;vMn`X}Z_+)*Y{j!e14Yi|0(e0*vaQSn&Dd}hJ9tTS$5X76%YyQL=II2}m9C9oj zPlU_nni!XkybLkuTa95`+IS-YI{&8G2)5;2eyFoQtx)TzL+4nBFgR?BIRffT``5>s zV85YiPaCQyb!bVN&!m({#5rVxG)}VoPTOs~?OvB)T?tDU3aH$aKGG-ct z86FU`hcA2)i`#S?g2;M0Hmz31PP^I8{uF5%tPO5JIA%Y8Bhl<8EhsCMNJLl5p*+jgyGa*JsXAtt#-p?BW01^KBsXc_Un&A z7vTx2EgE_Zg-dN?v$gj-l_cyrLONHE{|Yb zue@ddH3F@;WUzw*US}m*_6chJi2k5pgS_gG`a!1Y=yRWx^-jpW^GmY62|R|5Gcxm) z8Go4d(0z2&j$a?>E{`1Exz0Y@I%dGvm{6-etZq-ee+4t)~^Nd?u!C*pr9 zK}Y^7)7q3K5xkEgHXJib1jbBME8a&CFmT%oxZl3TLf;`whs+I*Yr5l@txMkq0#+$X z-kPk3qsHAFT$=+f{YHP0j3Z5)Tc+c)K~-Xa>HBSqF@o$7R0iXJi2odh;2 z-kM~F;mX~vggowipo$u0Pr#c=RURu^Nz%C%v`2O@m}rezJWJ8DkS2s$_J?w5Q_FIH zGzIR!U7GcKlCpZgUz+KdbGarfR(jv&=bs+cPMpk!1WM;$?+LFSj0O5ho_}Jre>7O= zqAYUoshvkVBfulYN+Pn0PSiY2 zar6!Ki4u5-(f#hsjqd$+U|$yet81YZMk?Bad+}&KS)^1UPz5gA-ew#u;yifFGAu53 zQkV5xlp5T{00!i_4~|jv?vZBiO5ap}(Vy>#ioynV`Ok(&h-KrNaI4)^}}MAk)Yq{5=jnXuesf`;9t#F zV)e%Mm1YM}U6?><`LUe-%A zR|iP9`C-@q!5V6~!b>WCNcWYd8Dm%_&2Tf-K+*>iL~e=EuFWokpQuL?_=X8BD)DM* zWfnAX<=ZF;e)iXkSG;&9f6B{SE*M{Tmp`~4j?eq%!Nz5e-9=-W`%Zrz-S4-15Yb2i z;Aeo)eC1C(4s4v4XX(;M1}}6Nv;fB3!dIYZuJ)oxvgN*lODBGw)_G7q!IJoQ#SM#F z)5hc81F%S^as*(`t^JO}p-vOr0<|C>%`YhlKMrimzM02q*zTV=r9V%(em6|m=$53c zHr6xH$e6Un6FEV_;qVi_PFqx1T|1e#jgJJ>SvNqW~^HrR|x$Ceo6U8PeO4&7;xZ8G1=R89@bq=Ko&pP^RSCe zbHZ~L#-zCz-|Jz++eN6|*utrR2~tzhSp9?^vb4jHHyZ=tg*R z?&uErx5U$X##iwKT0b~1(q1$@PZf_h9Z8vwBE<spp^wZm)U2)Nsw7VHY!usko-9!{f(!P+U!6wX3uGr1#WJL&|)=(pTY1)Ch9L zk@Zn0&|enYmQyu9D0IAAV#e)yw&C$F3Y3b%eS({Ea^wMtI>PV&Ov243H-j4iJG3?9X z`KKB@*92Wc5}ghRGZiSRemLTH3F5CYvhcY&{|kUr~%g%MCRA) zW3)}1eWS?r*HJ#2k@=Sqjh9y7Cv?a}eA{x;3o2vkAL05l8D=}bT;;8d>r*H3s&2NI zapSe+;YGlQilR#=HsDp+rz7LOdO*V4&Aozu%P55;+R2@D$>oi4VUFuErdtQTya_Ey zkZT>|eh5}vDPip!^Jr?HWxYs=;9!d~{rKVmVL7~N4kjJxWaDfC_z7WGeb}fi-nA0F zu(mN^xnHiqaO5Md0Ws`r3wlj(2k1)k+83ixVgn|Ln!BQ7Hx^CWW`*3it7uIA;^gr^ z)SR*taxYzsi}BgO!VMNtcy6#k1lhD7x!$xlhn_ixz=3e4-}oH_cW|_B)Y5u^Z?P)R zjg+BS_Xf(xBq>LBs0OT2&>_7!bYm(~R6VEaO}?Y>Omw!}r$>5WD^Nmx@XSb##u@a$ zrD5Ke5nr0sL0!a{w|y`*x1W5NoVq~S5SGM_=&;ze+nOKIKFDEmb$>-1xL{{;8Fvw}t1ty*yg}NH4IjcG64r7t0fUQoK@aZv=}hrYl4J z5O=;cR%2c~TkI7i|6zPZ@ZQG4_~K_3mBY7dg>^e|dpb##i9K1y_=!-+rVw7y^chCz z!RFP56R6rD*OPGa>4xQ?!m&KOG|(<&zE`Hy=o#v;Q)V?YOsiqcOID`;@X}NpJ@rfQ z3`xW;vY!)E@L^Pm_U@E^9g5+256EzDw&brs5j=4!z?!|YTVsmFcTn~N-9Be#oU!_P z5~QMgF6A0c_}`1C@Ml%lsin5FIw1_XfXnWiRB)adaAt5CiVVi`LBt*5H`e+RLT1Y` zsD54@7qfd@&4*9a=A7R>-fNon9D_$hYcl~Y*7nY!@z5hq>>gZVQ|^L>DfQ_`&L`nk zN9(MN310{<^zK)1kD!F{-IEfpiuDdhf8G?H6zaci#3aEV4iGlIB{>BL#C)1k@G`8Y z=hDQL(7kY^45}t+h(5D-OL+s|6B zhulYx@+mhy4$6Dhcn#z63;!_|kDrK4hAC8e{p4HUxG85(f1pm^{Lx-Kjyt>jKcZFd zFBLyqA^DSK*0IWRz0v@^`PwKyUUt11Bu9OE{&}Y1oxoPcy_P#e-TNiBD-Mz#`>?H< z#i6!pstG-Do+{S*{4Qg=L2xI6!uO2!VqQAR$=I*GHgtvYbPno^bD?7v7c|EV7fRWh z3M_;-evY4+^qbE-tKzX$wLi2v=-=89c2yj~gRaLFQZ`g( zRrA`ye6>1~s22B{9M{mNh{}t;p&u2;7LiYiBk+U9d>{jW^F6l(k+Rd!qb(1iE63C> za@|LAkN;ad@OxA-P{IPgH^&|0E9e{ox29a010c&8i$ADI96?jsygxTg|UPsR6YPxO!I zog945z(?pGmMgcN;bI z6(r_vluBk%^qo>-^(75h>lt5AQ+m^)@=9BF;p{L*k3kb0PS!(s2DxScF7c4icVm4a8dut1wnD|o^WGw8YU7wO@ zxfey0S0t{BpNwjPUx(U-D@>-M)IhyYwLaC zks(Emc)ERbtA4FYEOpmnxJh-xHGG;lX6XJG3 zxjW8BG(I(W@m1guD2m(!eClRXFYUT>H`?&g?q_YC`Of6fU?3;EuKFv_@!T#){`2Pr z1%NaC!@Zx#S~esO<$VH}Ypjj5jEa?#iRs$)O)_9G=~o12s1)bv)IK@aTlQ>#fnKnNbX4q}yK9;?)M#g*Ggy*M zLAY)U?A~qZ&}|-k0Bk`&{99quhw9@DKLoT*AF1XerNUI_3>W$U2am{UKgKc1J>1J^`!QU>QZvxVi-0v7mjl$W~XLuf4Qb$^76)0Dz<01 znxIFNg`jtPEBVLs4Mj$mJW4p|mw9^eh|hoV^D40P=C27P+OdqBO4dN%xt+c&+aKVq zI~*W>n9P-YvZ|FlAsU>a5T$U*uR!G+)PEQ0)Pp8Hz}|Cs^?vDRftM^%RB6wqDOl*d zQ{{Yn+gdW?M4U@9TIB&9x0p-)KOmPYFqvGZe4TP%Ebn=8fvi7#OIBKnId9%c7K2qw zp2+-SJvE+zDo7Z1vxe7Max$;PK+h1oCL@#R_CD!|f47xssiOBqMHyT56c`_SC zf~J2e&%2XQUjB;3=QJbv?cBFB2Vvu(2|=TO?FQ+kY4H66=yyQSmFy|2ZR{kpH;3kg z5UR^v%!1?{mc9DH8w%mnY6`5s+@-&+^EO+zjSle4JgxQyUBZUU7ZTMF`KJsGjCZG$ zuFqcN@4pq_y3=j~{I;kO8age+5*{kvf1#GNx-)Jy^-dfEgT7mEx%j-aa2gV^o`Q>9 zjhX;>T$r3ZthPfg9*JCz=IxPto%nsb6ks+Xx0MGu(Ne)EK#z2(NF31KwUHKc6sG;JrkuuwbE{MRjlT9(Z$D$%!-hnn7mjqm zg#)34BMklAF2leEW$Lnmmc;PtnOfaXW1{U$90-*~tBPgn$#7cWKHpvU?q|EaSDApY zf@6NYvv(D0x=2>-@@8D+$512Zj>)DvW#0ad2woXgsU8Ubqr&+@=abdj)MvR@4vlxp zjspu)Ed+&hipY{a7cYnd+W0>ce!#nG!^ImM1nOzxkd0I?2YOb$t&^@_)%c-Eg;n-b z$?iKd!#mw2jq+#Js|NZCKLHft6zC)&SJo{8Dt2-#P~A=j1ghJ6I~;ZEIwCp|r=rwk z>%I&1@5}>;{Gd)eG~8UsBc6HuDCo9f?ba6R{O4()y6&-<$BA8EAuDxed1d&P)<(HB z((DOa_uA`)*1PX(sx#(>N^p@rgRlfARK~I*@^BdznXB9zWPFdR!QmDZ3*z&LxD4$Q zz;cK99Y5?sd=-dYgh~jkPd0!bNcfS4b~gHX3C>eF%23v=W--dnSDtx)7MV8c9NyR% zzFd|_6xm`NL|r_=+0TTY3;?v`J^1_9UvDJzPuRQjYX*je;m*`9Fx&_smsKs_Gc2cp zzKg;%yDP!KuMe&E-DVe`$@-1zi1G7x4}SSbLcR3N+|jSY&#j2b$X5kcn@~8o&&=d| zILGPJtuT~L^#J&eOm77Tnml;+fLLi)sDl@o>6pUwu8LWw&YpNm|7rtIWWOWe_eq6x ze8L5Wh-ZL%4zG!T8FF@}9(hvjtr@cQDoQ`R~|E z?`9_G0I>&z7bg)1qhS(gq}pCy2%)_|VQ%9QZhOw>W8C{D+`*~0l?yD(Sw)dJ;$~+< zZf?$6&moP8-nmGW<buF>82#+nM%A#w zo7~)G~+lZLS3bFYN2UClS(h z)nqhGk?CRl*t8p55eAK3B642P?ZWNm@7Z|)k((E+d z<+-{pD3m==Rf-TgN-XrUIm2Q$FB3p$1*^B0qgmt4v3pC>C#D_pAx`7;uzms7HaJ}} z7$A=mQ=(c#tEjJ^fMvV3Pp$Tk+C@C2A)e2X8KnC;F8*!A+>tpEYeRkG_NP3W@>?3a zUT1GoQ|dm8_0hj+@O{%9$UEY*YU;ZN6Ie|)S9qlsr;5jPLWO zKrjdCkpfdnw3Wc>#1z0L-`k*9L9-!v)E44d`)?J2P_d_bt?Y+WceTrQ5=XXc-AI4U zdj-)O`6NteoM`;;T5$?*tdk+~U}?pgzcxMp-k{UuDld}P+^?@zh#QFcVo!C{^vvRF z^9o-W7?qxNB!VZlhuCEGngCpA629xb9Z_aB%cpx@|9;T*(i}<%LTh;7Z%`tkBb9`* z_fSn&zDGf>KZEvxy%iVA@knF{?^#QUNC>0k_dC0k{I#~Xj&eJ%SOktQxz_>i{2IPG z;*=}m>B93TiYD}@5gdyZ%JaVE{f7jONXucOXHKP%2`40MY{i4w+*c_9|?2Ia$3=tS1M}8JhgqrHd|a;tAIp zS=}c&8m>(Jl?!C8<{Q0Q9`TFGUYoUO_jUoD$cFT3?%v;h>G(Na>efmz9t1#&0}Q`Q zifQ|x38IKs{7e=iQv3-)pyy1fcLE#HaAUoaNf-NgQbE#*a~E(}!-EG^0n9>+6+dTG zB3WKKI5DcVU@SU8)DB-hH z4#!P(o2z3YPBP^FDW$4vo0#u+@$gY3YZpgQ*rP=X>mY&oJI$25-v{~_x5cYSWsXqF zY;ywx#`Q^;#(ICbk@2C92ar!l0tU>Ik*Wq?{s=+I&>O#9-D&p^R?cEvU#{bivTGRj z{au~as4JmhLOYQ}*zSC)GERX`h5Av?h5G5QEEk_+kVhu_`F;$tc4;4KJ=K0@TzrMtQckYBJjeuCG1v{T8JgeL4JVsFt)3muA<`_Nk8 zGN!rwF0u{}w(e{J2p^%IYf2W&e+T`br{h~c4^s186zBQ;(J(;GAU@A6BL~@er}Q3C zgFyW8#kWEij&T5o33E(KNl(aBEOG3L6WwbzxT61z!4fg()~aS|d199}pMc{HlcQla zitUNI3ru@G+~xAk#j%LlMB_$TZKgF*Ufd?%liTb zf(~LVMz(z8_$;y@xQ=9B0F8f8nZUQ&n;RH$7+e{vkg%h+;}vn!jzT_`lc$2Zn<-{{~c4m1y8$^OOyUB3*(6XvZ^geLbRLLi>KP$#)CXM@=S5 zwv^K=Oqw-Hjhki`kQsP6}}Fqn(R#Hx~YjAlo+qCSg1E! zoG3x6eraLovBRQC$ z^wGBfk&VFm2#%Iy>13$|npp-efWOZN!Q^F#4}Y=@CGG8vn>dDupt=t!x@>31Qw!f- zY5J*^kza;0PR9^7NxR_G$UV_NfdrtoP+GjjIv`M&T%6?EaIA{WzOxj;vE-S;pnGy| zMSpUz(_9c;?6t{DWlmY#md*DvKHdkNa zM-?~FKS!b+XfQh6{%;V0XmR_ApSZ$$zt!&OaRegXfmy6fSB@=fPivl}@;~Wd-ejFG{2@`Lt?Gy25G>{uLc3tU92&QfFvSd15?JCySX$ zlt95p5}>ESegkWj-K11JOFHZ~BQN8k_&$SIh~gEDw#PaRjGh`yCfM(q%97aLF316# z4<{drN!)jO*<2D#eGH#osd(Wm?*aB=uhmr2D!G%m*h5|38H7w@?lYR{sBy$zi6d)4!>h zZT9}=ZzlMsAWsi5Q7{Olzc116U1_At%oOIE7G+6V(@>%H2YGPp6o4G$K8!w?kes8nveb`i~ zc&+Ii89Tdc(mZS))vTwI{a?1>`gL24M}5z;Oa{Ny4cpy)FOvV#fR6EmV=>W_pN+u> zh^{;
Pe8;d(WuI&i%H*_M1TqM7n#gytI8c{y3XjS06D1hS`B*ev>*1>BZ zIxNrJJdd5+A(-_YW1aPlfi>+63A8@Sn3K5q(U6AZ2f;y2P(C2(*;i@;NZ@!L$dC!* zeyA%9aJ>J%R|=209Pam$fA<2!M~w8V@;~a- zNp3WD$F>HNidYY_)O+kje(8?SFDVhY#18;|5(N=9SN@y6cRKoi_=mB$p19u`P~SW5 ztwFWq{=@(4IQI#gw0!&-70x2{eR_Jj!eIp-p^uv4(oEKIhv7e@!SH;(oWo7XHcoZx}qQdkGJ;#YUE!^xg?YiiFTxXaNF*-U5U`NM88fdw=iV`}_W9 z-n@D9_RPsCb515XYwfky+IxN0M?Pbsbt5`gto{*?9#fXE+zJqLiYCHry318=0>~f}Ali$%2z#mvmV4%ET*(M^d(Y z0BjkRGpia?VPg^dc%=&6dQViLLU`Z$6znS=6{)AEmK!pBh=k896-$V9bvhT_tVrz> z36o}XNA@cA3^oWUUP!j;R`wlZr7jAmt1r`P<+warFPfAd8i#B4BHHiI?$Cza{8w&6 z*V5eJ=szKYc2A3c{QC^%gY1nbgQB*8B2mM)PFqohJ+#Uud`ke}Su<^VS76`sGdN`1 zZ>nNNlPqRtWpGW0RerJU2McK}77oAiH2`pEe{33Rh!&hPf3G)xIDX)Nv9PH~bS|~? zlL)0M(o(CEBD!|1tyArA%_N}6Q{-#}ePVatO9svKhZ`tS%MY_p zk4RGo?Oas5(NOfF`c$zit_dTsO)YC6r2WdT^LjL6&g_1hvT2(~&;C74{NIdOjF_JA z%%@~i-ueA=rEeT|BWm@iz`+W|!LBYlDhY{LIV8VKq8=Sq1`${y98I+ZNi7QeO{LxX zkSk%yzkvzcd8K!|QZ=L;UFDx|=Ip82JsD;&pJx4dtJmX>z}^<>^OXZmlPYxAnQ6ib z%$~LAp3(cUJLK!ElC0}TvGeTLBN8lVl;E-4(3QPW)K%&VfooL6CSOZQ04Pzao&b(mk0}xKg4R{=XshB~V^-SqMD6i4y}dGTGM*Ai0qr6p;z! z5(FExgHc`m!^`Q3LqiU;IdT)(oM^d1OYr?cQ-3mh1wwhl!@$|D|F9mXj`m+|B9`Ue zJS8>g>;nK5Kzmjx1<6hPn&Hd0wP=|VjjIk{*ZX!m69TdD*!wYUM8 z=Q6_%vW_3|Jf9APFD}WiX0~Y&4jP%=2Le>(T-qG#KILvT#KWKEF>`Xs{s^kbEKP54 z0RsBSM;D4WoZd;=?3t}Ad&%4iW&UO$lvQ+K%hPDjLQboV%Y&1dBTZ&LYXx|V2Fe>J z)Z2E(0xPfhMXlE-K=In)?1K+C;Qw2XDObwcg%$Pm^8au+f3@RyXPWS9zr|dVB{3+i zFyE)mbD8M*q-wfH=tXKoddO^Px#5SkK1ZVjIT^Cmz2~I&?XylF%hzAo-k)2ZF<3g@ zmMGDOZ*rAtt5cDP^VDWAgU(?^PvZWMa}ckwfc9j2@Rtp^l%3OJd>!AR$<%_Rx#hF< zCE0M`x95jW?Zi^Bqr;hA^ktCII!Z&tb*7A~Z8V9Q(BWodX$#3LOU|F@IIYe&nDGOI z?#37Uge)fXug&thZKb1aY=p?;FEMJJ%M!f5^YEgx@#e6;eIZiBkQT6~Y2f?}WaZi_ zL+l0<=BKK>`ypGi=eM!#Mg_=1#(Mph+Isoc3=sdDQc!0CZPZv=Jbk{R5DWG9v`8$T zZe0jFuupVWlJnh5+k%F2>JVje$-Zh}A=9pFQM~N}v>p?p9fLdHaECZC%yL=GDRi)X zwLhXX6x5e_%xtkP?$56FQ<{6tK-zvng{NlYp-YXo6e5MV6K5Tog`Zoa^~fRg*-0j- z98jy1hFCb{SI_>V2mHrp_JU@1X{NkOF93uPxW_@A$5-(5OKo@cIXUP42*%1MU;PnL zQV2|$)Q^-1gn$v#*ql|$2ybe~EQpT$#*rgnc|Tae;$ELPal8E1is7y`%H9yvOT>uu z_(K_)o9cevqylChSGzmkxfqh(R=}RWkNMKrA|(o38fBp>inFn_pad(7O_9;LkuRO# z)!=&^#$Upm5dmDnj#W)h77zb2G?kBX$UEnGjO<=;{DGTqkBAa4+;ap(!nXk?VDvea z`dvqt27+%Bp-uI+bHxt3Ct_9d#>zyx3uj?r<&EndaP+n}sZlZ{SYNKib26yvfLL4{ z#OKG;6TQT-+jY-?`n{ue;f8gkHUm;{{tbOgjpyzow!*{@=|e zOT@@wM%Ic(QihRqMD+_idy)Hwo#R*2!aoDz#Gx-2FgbdVJ0oWzm{?%1Jf+sZw23}& zL()3>f0F$mb8s#+XTIWyYpDs&L36-0Awo~4rc4H}mzsh|#Mb&@aWj3lS5g$enI2$yRwdZ@^zC{0{$JyYA%1(0gq(Ugc^yI1`DY{cvR-{FeXx5)tf3 znEmTr$AuV>oAFT9c2Gc|^`m{@-D<`RXudjG z(T{vh@Z>;#>Hz=eS-K*uT_i%MvC48X#+opm8H!83rPi)C=>^z&v^-eVcHQ`69%IL# zz*hCDF152G#pebT#BbrM^GSay@qKo?VPVOtAX%r_$aSA(!+@R1s2z~`AwN9*ZfGF1 zspe_)m=AUo?naEKZ(ECX&&P`Ws{0#?@dw6l{?I;Q4AaexCi?<@0I8m=%n45FGqq=V#b?+ za8udi_`9i?H1)c7Fb5^4n~5iTN`l2JE%tb_8uvU+zWD+wZ~uMP znv37vUlVh(Z7A#YH~f9QS(ZoA4K)mp_FeLfIJe+3pE(1L`Qv%Dtiv+qde>mWlW#aG z8HLi*Y2Pbvcu?`0y7HKx3_)UP6QuTH@(-&E5#|OHeo$-!l&o6>8+Z)UHS2K9nlw8c zOHgZz7xIsx--L#aw6pbY^)42UWz09B(akZ5It%hbQQw{B=Ki4(Gbv-Bh3u@}`At+l z0_tM8CtfLSzV!LnW$qXBB+}dEx>n-8iuXy+m~Z)+8o({#&-4g)3mkBO!;s8A{9Y;+o}K zN3XIpWtPb8bt?^O%sD5E4yS~=m&?tGa&cuITqW3C~36i)0+6CJ zKJ{nb88CAc!-GC(ox~}tmGL*YI4z8zGrE284Pl%CD(dicdZ5AKdV2Qp0fR)2;8#8_ zzeVzHabo1+(RF!TAqbkL^C+{0vANWvZyN@vOU5`n_ zFS8V2ESN|gifK}F_q--@LhxwFN9E$0Pv*o8F~RhG3i(UDR_%QM3}Fq$m(l2%3qeb?33fGl-c_6Eu$;y}oOdZx_b5ZwKEu|JS3?dqHMY*~ zU2yvwEpgVr0KtKz04cNq)+O@H(+TaM^!%=}qZ^_|oX(c^xVc$7BZu+lts`lH!;-X5 zSl1(j!YyaNd;?JebF)fi%j)~je8Ix|5fLW4_+*AvRPt{wa6-WuE^a5TD+lZ7g&Kaq z6&&AmtD&genz8XX>!@%g5C&X!dRePR@HeR8HU5N&ZHIWEZq}4x%Dom!R8XZ(ypgAo z*xFm4&&pfN-9`4#=X>dytnxLUZg*M3yOXg!^NlWZuXXTI;B|Xi*R}o1XXGK%2A@rr zb+cq7Fs)_UTTQD`V2`kOR&81cdM;i(t*`a!4a-y#;P{@EzgX1tkygf2yhUpwla)g! z$I(7Ih2xu=X;(cxKu&DPw!ZOj!E47%b(&}SBTX!iatS&!bZ5YGIJ>S1Hm^07-ZG?R z(oO%B^i{ujGQGY@?ITM>gYQta0@zB-u`?#k9Vx*s|FiI+IHxbBPP%rvRKO7VLeS*c zyC_vshS`mII%D8?tFx+;=l2R8{%1?PAri#3%dMto_?0mk3h*I0lLDu3zc2Q9F81@z zwCd`v!{8n0U%Z-+)>|?=p{cy0M)$Fm>9^DSvf%acxvW17+uT{32wcq5$CAaOzdHA) z;`NJ8%yl?MdvNG&mPDQax=QETamz@qQDaj4l^z&f2S4t(njfsk0MI5wy<2X49a;L8=B* zw0N5T@_`9y_Su`lC&_qHimUkYU}gx2S1v6RAnUK($Qv6*{{oV&lEl^VMLI2bcRs19 zvbEUr><2NE3iiW@NhD?P`sT?>MCy-@7$;o8MrmJgvk^E&eAs|3BKYe`LU59q@1gvv zi~~DOxt}RvJg86VFvrQquVZ?OFhy8zGVtXn-Px~CIZ>Il(CY5~0h9l< zp~*^#Tiz16iA9T?*qOeYYaN^R_@k`*;<}@PN@PWRPJa9lb@G!4{BJ*$ za$cn{=f97XA=>RWgY_~7=5}f5d_c2AyUjhc|oosDiXJ{SVw~;{dfC=je z_ZBAlYxPU5XWH+gE1RASUL=Q~nO9j_3yV3)GP+dn>e1BGjthFURCB|Uq3YnYK-H%T z@v#_xxQB|etpDdXud)7};JqsNT(`Xa-IXHy!xppSSl)@|eD9e*i2Y~=g^w3#6GLx{ zIrFp5#y^#9=CEs&N_|J;VAET1eHhib{PGUL%aG&Aq>Z(imf9}Tsb+5{kZ_cpd-&&x z&@OQ0KB;ne02@tD*zm@Gb8=!X{nD|*jN1l8%+|Th*4$b~Khvlka`BU{!j1G8OQqYJ z7X-d+ymN5qiUZO2K?k9?1C^D`44abRCrjsZHlY{m_YN;TM;6KRDlX8eDSwagc+O34 z_k8ik3VkxJUsqvnIhnX!hfwq#;~Amp_%V>?kIqlig9oS!om%{&1N2HrxWLa9^^mBj zO|AWSR}Ys1smqtoeA85K@%~QC}DsCdg_+hj^ zgA?2kd1)Kj%ih-YNN)ouY&5iqDWAdII`Mn)v>U%RR7rE?fPH*#{32sS$HIy>G40Oa z@11}YXFRfQso*9<8dQw+g2C5n{`z&rCz*dZC(^;euHYRb5tuy*xF7;krzsNsdCGD< zxWpfbavs~K!+TDJ?PzT^lg&s<<$@=lh1u2-q*9BDIor*KHCc|ImR(puSBr-ihvSt7 zr5a?6%il5fC+d^U>TqYY9K@|;u#ZR=0iwqd#id)20;-X^)GHW6V9M$x3| z_mAGmItQFwI+Zef4R>9KM?DUH;v$FJQcXSaZunSA%iVhBc=OMuHQr*Y@sV^zC+%`= zAu0nSULTJsV`LP4cfi_va^y`oK|p7F`ow;#de91Ojb~e5U%nR=5NN2?xlK!{+kD~H z1R3a3Z_8zB{Px++n;Xxqxydz~j)R3Pb-3+eEzjx8Iu)QhZMJt zI+OJAa=Pea<%}l0H)*by28BJu)vRloTUKYR;qI#mR85?Sn5Yi;c*BPXliz6xFc>lZ z0-V653h+9giaMPh_`K&Ycyf4Iu>CmQ4@|7Y)UF^xUGd$v>t3xMtgi@x-_J3tA*nVrLKw~-y&Lr^SMr*LVijqignke@MT_N0Y#)S)%Y(#ez zt9e^g&$4fIw_^qpVU?o*^CS82j2>9y7~2-bdRU!8Q^QY3hU~)p%)K)gb;F+4hucs6 zgyFiwwp{ztb$8WixgOZB`g+Yz_c**y;f}JJQcF)Ub8NnJezY0ED2#K$e!ctMv0OBw zr#M|VOZ`0`%^27hYQnc7}DdaW!- z6NwpvDy2@RO6;1FDG^y$N9o%OWbY+-lIyU&!V#{1hp?rCO_>X_s+x6VSY(~g6RzQhMBE=6eyuxb z98f7L8^(-LvXAa?aHeBsTXn@57T&7bKbkRt?Rw_HoejOF`x{d?(&awW$lI<>WcL3` zQ*e-BGfw30H8P@8IG^QD@0JuTQgJs_B*)DZbGV!4#Ya3{)hi4BiTd0Z#oMN9_AX>X zUDsx}o!0F!a%f7{QIIiid}VoOeIRqivIzg!i^s5yrd)3ct`zami;5SXEzLx*1G)-tDVa{oWS7s8 zWF4`GB3$9B@{Si;2|S`0N2fk$ULPG3k$Acpe2B9xMz`t0JvrcqV>c6sI5rdf!V{tg zdEYdv7dTWbe?i+30#(Bq(8Ol~0DtPG%`hX5$Z8P-eSP_;#kKwNc3O7I>;h2cfMjI` zbE@I?ld`Hm`*vuQC-(0I^YY^*h3AmF!?fBsZjCLFLqg#oH>c)L)P26YK)$mkz@Lm_ zb+417rmXI1n0atg!&x<(`6@Vz;|-=+CjvFQ4puN!(Ph*Yc?v$XbI73a}xo;69~ z=42Kr3VG@5{Kayfx#Kb*2pI}}QoeI|$#q6_ee9-yo48-(4G{6Uo$$GPoZO z?%Z1=bX4Q9F{zP13T+d$>(|@I#mDa26M%xc8PDtROvtL^qLENaUkV^yc^9toh1X0u zRj4zg4db-5yILVIPMUiYXQB^}F?Jdfc|8B?&pvtOf1aj3`vt%sP_v?#fPEN>B|0OO? zN95vklaaM#FeI;-t=HHo_4PA^-5Jx}h&PuP&Y_u1Mjxl4#l0?lMK;?e+w_Dw`D?ne z%r^zVWh(fN`Q7Ahv)u4xG60SU3|~z&t?jP?By||mzdvy(lYI)ImHJ$+z@fgl&M!_+ zW3T9N@$ynD&dSJ8Nz7b}657CEoi+c;1&9%Qc6Z&OV*|{mO9ZPy(+{b%JnBNdIWpT^ zFxTaO)n;3IGbyg>?=@oNSjB2#oGvirOCb<|E|Y_v1flu5^kep&`>YhqYE2Fw`zyw% znn+7_L!`IXE6c>9BM=SulW=IB>C0o!IeGg@aj@Af8eoOTncPA^*LzGiv5od?d=1Wj2}#r0Ny z#j?b#ok9w4&e~h@zhm$I8SgpfvutNhiFU8>EU@!BuDXi;N z6JXPW{RqISN(CNa+Rk!ApvgA`&`Y!5!#s70-Fdy?UwhK_Ue>-@j5m zrvx+=-V#Y3Zo*qL{%Y7M#n4A%6a*n}TbG^Y=SZ_qGOf_Y)Ma~Z-^0*c_x3n^8$!<- zHN18>TI*dd=@}OSjRElv!I6!>jAi!|AshAh-6Btm&SEp9tyYJW(h<+Wts+H#Hl;}x z9zx3>;zHi4CsYL6)EbwYF`u`+Rx6KYmdG@a+KLxO9pvVy^Z^i~JM&)tHBDTez0fjU zZ!Jtgs-o`{)UDG=TR4jUy2y-g?4*Qhye_vpPgJ4fA3`+=XRf|z519+1Kb%&#FR8eh z-~L6uX5%Ay@y|QgbZ_i8|GGrp?mN!+#N=o+x+f5a;%R>?Mgtz9RGBlb!W5zS@ zDPeq%9Qh3)>R_#XKHez_Q2phFe`=^F?#?7pr)#&aK&&P@16lR@nW&SJ*EKA?bKP$R zkncA>7w_J(8y|{iA`1UBovZot0wacHpURi^_w$(jQJwfY9Zv6LQv>8aIpF7fX}Efc z=xLi3-q?=v*Dn1MQTCdXcHI8&qJcXxA{+fZ9r*kk7F z7I9USM{PA%rF@$gLhgS#rQl@{!VgY9TK8Zb;VeREDefDfG0mG!$^$v}+Ps)hA=BRr zKl*LQq-zeKYWKIw#(bwyTMcUp_#FyHdjU%zjFD1Lcu15YM`D}9T>yD#M4LDy>#Kj;+3TN1Ud6KL zX={Ru5g&7+wQQ}2oaZ5Q3U0y?=Ra$g-2m#*rKS+FG<4!+GKy=zOM)3T2ZHtHlj?z$ z=!94{=FSg>gvmDU3(u(=S+&-?uM}S^tQnbcF#CkJo3q8zS=zK24M`h5W>O}q*=Cxs zjZs%^qGCQYD$8*0{cN+ec3Aj&kwUmbL z&4Tcv?XDgZ-YQzq_bCIL$7y}jUys~J9o3h56WOG#yKnVSxytTMtvqhRg&`C%%`?s- zB@SD=*mB*uUj_#EqfQjJCdhVMF0T*P{{ID?+=ZHyPvBb6UP$ODvpLxl!jUU1-_Isvu5Rf0L_bfKADO5LPvF0>Zo1OxZOu7I9=KzkT& zhPh>q-(#vygRa)6&o$wY&UN+Tfa&8wcDml`dYKT9HaV~YSV6jkA9@Swz^bFqn;^@Z zy#Kr_^S**C!dS0|;g-sh)ouAlAl$v}q)gT8?Rwnx|a&dq$bjT9d85J`pzDH@a5#<-IQ(zxVB74-S<(IO>)De^;q&)o|qbn(&L_Wg~cKI*jXP(08anO|3k0`Ggxw( zHr!&5g7$FP`QY4Z{jYiD|J0S0^u4ew=i=9Oqtyc>qRSMOtNi81&#qAIn3Zl9aOhr-yQn+SRx0 zpM+JXvisj{;v@e|N$c3~mli|%fq}CZOZCj%Q(qq(`HOn3CQ$YV6a6WZ4eXjp<DH!8lCl@tv#DN)qmlie6 zn;=ic78aRKWABD^kUI;svv91+F*J6#Dqa+4n|oVMR^Id_eIa5;QJCim&Jy^aFY!Om z9Az`lC{%2P2m;t*f8}k(i-D#q*XdXc=+1V2DT++Fz*xn z#EEcXD>iIvu+1+c7PL#25iE+C7e}w^EJNr)8P7Ug`AZ4%55mQQK3=(a(k#`rPQ;Wd z%2zQZo(r=6$;L~g^PbeGG*Imq+WL#YeYC%BIFMq}La>`t5X5phe*JECtM5{xysSO0 zioM%QZD{>V6l>pU&F;S%AhI0bNA=fXY9{@FljDE<8^;Wq^A+9k+E+iqrC3v$zm!xG zVZF5){y@Gnsg;Ww`>w0T*^v(sYb%qLG&JwL?no@P$FTR9)(N6rEPFC55{ETxP+Gp$ ze#K!M&B0wj7Oh0a5lCCc;`a6Tk{xv zid~-LS^$WlIyc|1Kt|$|dGV3n%UbJ!Z6RP^_8N}r1Ugq!Q`7RO)7<{YB}*^GdAy~f zMxk98?Rs#>mc-Jw8Sl0%7?4G%-Xc(Ng`5?0@LUE?uk+=0rUTU0D3!{;NoVh$!7^_+ zGKznz9UI)RXH3bJ{rj}{)BB8RPH`UpHwNRrA57hW@!lzZI&J5Gr@s59i``qWdR;ydHpw_1wDsPi_3iZe#SIsj$+GW=F=?&w2h^X66UIya(vQ zBb(!%BUJUMQl8kzC;)%%TT_#oIo?p5tF_k=C@o%43KdUr@^lLp%ByKqkpuSr+_R*n zEaYyCe7PoK>_>NVaP?g&u2a3Gm(%@A$h86ohrAu&+Z5<=2Ar}aA|SSZ;mgL!5c}jY z@h|YszYCuNln6bjIL{`d+;>oZ9y!GE7Z&L6ZlgWL3Egx0JH`43fatG>9Mqj8DXHym zYF((CEakd2ev%@g6fnt9j_=D|s#5e=?YL(u6gla3GK!x8Ff?~E&m?}JIj&p|k`tn# z-N$|l#GkX+@zXB5=XoF^$J>eJn>w#$Jo*BNBE`>7B!&iCPvRaWC;ZKv&i`BjzGsOJ z_Pb&*GqDB;@CO$&(-@o$$}(gJUi+-aW|dnitng~Q>1fsCXn!({6>Lz0{{`csqL6K1>m&r$heqRRuT9YYmBrE@AF_!&4kho93;@U(1bEmck z-_pcO3CKcjQ*t%6Z`bBXd`zi0IeKc$pru#qJ!%#fMU!gT8|+$why?da*>`ZwymOLE zSMvO(Jtpq4F&NCBhx&QN*=evMCSJsVf)=`H2j7pVretdXP_9el6v2s$tJcNB@yRh8o7+63Z zQjo{`1*$sNytrdYuDNxAv87lQchQfhMo7e<$cBOfZXlD63ydq@TK82xUzw_vZhW`@ z-JsY^6i^m7mf7aRW8jea)OavK zPYF}vgnQDJ@tV&6hwS;wsEVsHjduMzu-+1bf|i zhrK7}deXP|#1jjBEy*e>CaMc-*3CyAuTT{SQ()aXj}?uvB2$!8aiiLv*T1yvfA3=s zzQu)zIy~o-SOvVdrW@aiPQh)!4@b>;S#*AJVe|{~;zI+FW3=|A!+5kG%shac$T018 z+y8j~hjn7)8W(Uzx#0kSubm8Kwp3>_cDz`V zBAvV2OGgwWSz5)}qbZSr1$~T}`H+dv41}{}uGK#=LWDCSx%)4sqlt#NMKF4Hzj~?M z<8>euIsQ+O!aK451zjp!)q@P7y<5j3Mxtx-if-NHjcj5&?Z!X`0kl$Tob%qC9`9p; zvyZKR%7na1?G9}HOn?7P*c^Jd$`}h_xF&6<3q!82lp{3CMySgZ(mQDZe0*-1$f~D@ zm3qdDrNep`pOaP&g9BX3Vt#Ct zbddnRCB(7DJgx>(U*6vzZl3>Y#T@k@=UH;BEJ1C5SfBS@J*DI2lz#E%sgK|!`>5+a zPu1q0UWQ|MxZbTlf$Yp~ESFu-Dsw;DNFyV`wQlZW`4=Tvw6l8W2L7O}pE+8aRBrUZ zJ%ML%#pc}reVAQ0ZYT-fa9R7PvB4EN z!Z*kD;>z9L@n2R+@)ugn!Xhf}kE(KhZ1zo(Z`U|fsG4PIE9CRxs_u*~NDl4?2DpHI zb&G8cZmAc8Uuz&9&9kUiUwV2#n^1ki3W&le{RVf$KP@kD_3f`UzEs0*6Uo?Zlq!*M zu7I1cA1fMe>TttLygo66o7>lL{9?X^f(e~+=Os6WvthuC6ac2}VD=Nv21*{JO_mcR z)UP+ASs3mc^TW~d7|vrgxK*^YDq-HfVW4Ai%#>;&ir~exUNFa`tnBxfN+?J2v`6!( z?Es{K#}PxM$%G{|ha8qL>8J8;kznH6cjcLHfD-+iYyvHP{3F+;8T0XqGqa4Q2qdBQ zKfs#*(?J~12y|)IQnB;*$`8ruT@Dcld8wZ!0>#w?yXJxBB3g#}jn^(BTQX(GU_vc1 zN0M(9%%#THK!<=Q2T2I(GL$DJ4YOL5YfbVKwo+y)Qd+pDR+9XJD(zehCfMpwfkEzU zhQ9?HqVrnc8Q<`_B;+TNK*fSfd$Q#PFUO-MKm3?`Uo*-|jshnLeJ*#Tz@?dqavde0 zxo%%zO|76k9hR(WVtCuOCLWAswG6cTi$-zy#N9t?x>{Y zrT){$oE)e<*l~HLQ*E+3+do{Vvg@^R#4RRDevaI^lcsXg7v9WMBxvFswBs+tHfnIW zvWVig6!lY?Ouceg4sK0tPYp3jCGFJN&Y836RiJp=>KpjvANikD<%rdi#v1|^7Hp*` z?)v=x38|<=V8+W9bPWatb)A>$@z&dDDlaMY%5bMb`&9Gwg6SFlC*xO zBQ1y^Yy5Lg>}&|e&|1VbYtd;1-0{ZY==nw63`7S!C>YwH0i1=(JQ|dH)$R1IuBGvH# znxb{Z>BWEpi^xxhb=kd}w;P{qiHh1zPT`I*qbLp3IWN>nL+r?OvfrjERvD9yN2_45bsx73ybc+^p%m4a5C}T_^u19fes$Cx1{Ztq;4O_%s6Nz_ zPN=#t``B;A*sK<>EXa1Aja>;Q`)MuGsoCqey?*j=_0LYYNey1zOoQ?gY>K-bIy2c| zNHUK<1%Y$-w&C6QDD!}iLNiAhAG(IQg- zn|YssuG;UeU}5sdv(voc`~pnb*GSBbdrhT{H19Z3Asg zb8Og(ECaKT9|iIWhl|20JEIdDY5Dn*j~<-$nj>c7+aIjTq|@6}`?1#`$xXlToSN0( z^EgCSS+#U;EP20L<ty_*J?89vTTHR|GRwMz=*&y`nF0Bkn6b$ztG3#6_f7R3>Bc&ixYUcJ2HYBnuCM6y z?SSvFOS7>SoT?LlF%{|coQ&ZhFD>{`Uqv<>?=o;vN3Z{G$D8&I@lGKYoUi!K{m3)% zBU5b+c^uFomOdh9LOW%8G6%fO#U{AlP9EW_lu80}=?zrKmkom03`cc-e*XNbI>B?c z>eA&r#YNkt1Y8FTBfOzX`Pv4ZzweN&aHI|<)_vD$D z9l1{fcyZ&7&X2ER%ORdpNG6`13s_=Y7_8>~70}UpSzEMKem6ViUMx$6@&R_r-3iZ4 z6jw`Tlu)~RY&w;R`3#>;SW|YfH~Au9l;!(Voc8^`4~5D3*tT+^t~z9Q+%e+uRkl)y z=NCKL>bW5Bk?YQtEQOt%;A{Vq>CQi7DoT-QRQ~EoNB_?6z?#LQj>+rxMzNLeLsy?s z)lk1v)q0TK9UEC{=tL~4zHdJHiSbtU4pTFwj6#KfG?uYgYG6O)n{r{x`E<9>!EaCe zlS**K-g`bT#-F5Sjrq$nP^Y>^)jZ%1m$J13eMk9$BP%-?TN_9gR{(iq17qzJabaSx zH;9~@BBaL8kufvV3XKT&{!;lFDFr%S+B43a`SDla?L@uyHOG%th?TDw-efJEBAN6= z;(He#v?V6pALsiHQ`B0s7v>N&>t^AAFXA>oE4;8kP-FM>3d7O$laf;-o zM7V$Bg%sXSMsJu_b+?&-TjCB0#=CT4E6&K=7<&wzh2c!K*X^_!){=#hq7{!HrW+C_~i;A0u#>Z-bmfO@y{StJq{ndHEL z7Bg%QaZV`6@%32smDI}c;IL2gy%?x0`>U~UF&}_1_5ghPG<-oogfQd_+Z~;_yX93A z+%uWxb!Lc{_fHInUj!2VN5$h(vHECw&R2WfglHr9boB5vilrb}dfRd&g0yDHuq<9|+FA&1Tgbl_vJf&p`C%aGdtTJtJqk3>Mi(}Ox1cVRaHGwZJCyb)xc_N-QoN4 z7r8mrExEi-7;`L|L4dR-ad^J_!-%M?=UF0CWdbGlT@^-sQE+Dyrxs&%{^vf8Qb8Zq z92)O`s)4jjRD;Yn?_Q3nb3m2Z%Br5boEKETr)|cg_R;h6{dMofKRxgzlYkSF`_oqJ zBPXMBi1=5vlMgvK^z7gizjJvaZV5-WN|#PZz>+_q5Athxf7UNE^7t+rbzGHSD!3J( z^~m+%fQ%s2fSR4-fcG)%ONdb2-Pu`Ig|7yBO5Q9(7r*J2PglN0bgX3gkhUAa$>Z4Z+q>6ms6NYt?rl0bi!B z@Xmz@e~0@qh3ln|OCh3s7mk#@T_~DLmw*g|7cO}3JW4yj zwNy}2Ak^kz@g#Ax8lqoE1h@8|j5IsvSMi-@s%BxI)=g2|HJf#EHo3c$FDUkbCgUxt z94B5CHP(v=5&hLeW~M^@W|Fy-4Gb*9KMmhy#+;nPwOunyO-@9RHdug$H3{vhUKqDu zuB85BtDAnYz323*U*iMxYara1j-viG#Zy~rlgKaia$J_K<-Fx9>yNJayv7ldiN4@8;oV2c&T)Nob!R6sk{0_^>5v@Xn?cdt`_!GK zOiiSK?_A)1g8Zi&xk8>1=tc#FnuzBrzXH`U6%F^3x6cSV7;>%Ua~<$ARWplwcE|D4 z;p^n;kgfX~!Dldru%(LRS2mP-3D?Zbcq^R7A{PWR z)(Wj+tA%5yF788Xan5(tv|haewVsO7O#z_>Xs=c=PMBoe5TL08k#CPX0HEC{jH7XV zj5&sqt73xJ0MEW&p%6_h%}Mink5IEZSKf=QN>`3~JqKa&Se}SED@V?LewxioBQB!2WWc=R03 zeEujkaxpAX{JW-PhiOY{wF!bAr|mjn+MK0p`Xnmc!3SB)d;2J(Q-XNe+dn=ENg;4H zK(`<@qjD&|Py~JF?vgbeE5S=@{s|DDmrsY!mwruosO!7ddNdu(04I1o5*Kf+Q2FSz zRUZiBnoMMR&Q(=t-dgb4T=Hl?(H9|%e*l%glWDQfAs7FO=%-=(>~3g6VQTD?eJ3Lk z7y8SWpIE1Cb(Y{bEH5tM=GRjD{Z1LV^%8Bl+|TD$J&!h)jK#wvpuJ7Di$BK>ttOMx zWDgm1y8S+4-=N&B&0sHT^eLwBK~<-WI)#U`vgK+6BCJ?qU~As?)nchZ6or%9&!B_v z*zGMq^KFZY87z9H4Y>GI5mM@`-per+|8-XoH}&gR)a4le&zYD$9eW}y71zhB`p0%_ zvq@%pQw6&0FBPNu97~;7?*T`t{bf*9pE$L>5`NEHx!*+p05y8Uh@*0VQTHoJz6G7d zX~hk+zHTuFZ>|(v*VJZLiPWi!F_)`gB!Q7y%jt9VWu{{s2grXefy89G=J`yH)PnJR zx;D#&yqWgR$(h|G^4H?P*Ndl))yUIa+|nAO;&Q^v2H!2IichL9j|PGbcJq~4OPgZI zHX>LuEq$fp?R4zf7xP87`xDd0z+d;Vnu?|1ZT$-oYA&;?#m-X^ zZMsUyO`kUy&OgKHAGVdtOYiiA61;{BO>pac4f_Zl{wJl|?Q4V)PK2AZ-)>kgxs|Yy zR#7SoCtby5oLqyGm3UK^yZY_b=24m4S(m&!PnNxZ&w12sv%3)cG#*XiMGbh#P6tsV zHfS^T@z=2J-tj`iq3Exh(Bx2YC+?H(f$!J2-!aT)hk@oZh=n#=qqjQabg*+nk=QxZ z59Jv-!GRr)nN*Ubmi;SuLgn143+q&7OsV-&&E>8aESg*yNm%np19#!;#HWT-6f_6%;W+7^j~$ohw1R0SkI9u-E}HU%GWH z!b3?#D^q3K=!LhEO(AEqMwg@5hF7hXiq>(JSZbl}5wYKJpi63=ClsG_%-H(Qs+ZGX0F!cl zd)-*dH`_v9ciB0W`9gojB1WrD!4pGA+I{MV4xbit>(EVtBrc`*37A^R2ltzj>|(tcRHPi#As8wrZL$wn;XKVxCfjN`sP7;Jd>tJN+b-Y zRr^>QUl?_4S<%$}_JsHXP+c~1PSQr!;eBRY9&>sdYV0JT9;A>e4aGAC-?Q_oBJ+t& zj{jeLy?0ns?b1Cg(xj^>Afeenr1x$_R79G9(nFC>=)ERF1XQY^^rCyA6_p1Mv45ZxJ^2tMrxPbg(NeG_vv7h1AWS z`_;y3x$l4YoTfyif*v(g3>I;^>`#=oRGP64<*1*?_+1xwMAqm6ql=vcz-^AV?`Y>* zdMyp-wI%K>hXfq<4<^>18d^65lI40AEOftlcD=vGM_-wBQlLTN?d=oUg&E9>tjD#MMC5xo)be`x$CnvJ}6i5GCp5$ zJLNPUB%iPDOhL=m)hudCO27FOJ$3%Xt@589EI|oT6sd9v9Pe~ESWmY;Cx-xHoy@!4 zXg*SStbfspB!<5wMt^}pOU@kkps^BA&Aer$-N3sbM;84RaC4CQfnSu#AklWekTQWm zFKF6MgLJ`dT;Qv(=)z8nZtcjO6J3oFn+0CjN!B7&SRQcSN_|XWf=uxZBhB#C+M1n! zFW#vUA}k}D$QdA^cr^3iF~BlffMUYX7_0)$Hp=NJR>$lB*u@?-vrrbNxcRY2U1ebM zU$kHh^)D@*VnurkM?L9mIqmUgJgmDJwz%*OQ(DOaI54DNVGc=Xi|SbR{*(36_D@u! zKkM!|nCd>lmNC@7bC*bI_^MpIj6Q6tJ}ee%}8BrZk_?2($%FZXrxvxy{a}?;IJP@DqScy z@@Vv3eGo&2e>#@henBTc4qvkcOCpN2*(5Ys2f9kZ@E01ym}AQ2Pt0-4i3%8zHmIse zoCbBlj<{$%Aa$3t8S(F0j5y!$5Ojc}CqiN=4;Ran7;D0<#g@bZ4Sx}l+?Z$R^GJ7L z{VIpKU{6Cg+)snPbdd~|==8_*DZHq+Bw@s}=kuz)QR`KVe|Ely3GzF+#$L8e+nG?Y zrE-DkNl`_FYM7XHD;f8f6V?j?JDZ_Rxz<0)4&+bQQ0SaMi)??5-`LH*bl01499vK6 z?-P6{hJLzQ`^**o3A<5&s|<}o+-1(AwU6yb2Iie<*@YA$MHmIGo+K6TVi`vMhHKf{ zDjz5nVK?$3$(4J(KjEI_Gler3MTU8UFk5XR+|)D4$0l?X%r31_&5HyJgq!1}h5y-p zD_rBtFmC!RR7`5IsD#kaaF-GQ7zsU{jSyJ>4iaj|m|D;-EE!VjScA-krI?23V0~7< ztnnr8S5cm7uh)+og7I?PQv=8O9T4FmktyXg+9CbyOECDi@;@qG4g^YcGqi5KPD7KQMl5^4U zv*ss@?ZC&0*_OOGPU}?mX1Z#+?;$~j&pNXC%|yHUvb|n9xK1RH;qMDU@ty^&u}Xjvr=(K#m0{nf5@r0{VsX5 znceQTr_1PN;X^+k6xSSPuw)UKyf461XlE_DT zIT50l$`+kuliAch)QlI!j3;>Q)YtTO@;dMKK=rf_(f4N0i}ej{fYPP^j9zKGv(Xve z0{2))bG@0Of}#T5?d;>@UM^;Mr`bnb`#jYrZa0WKI?B;IKIj?BhU#3m6kgk4^jWG{ zGbl)bNAPSXb)-I22%81{ZF)Rw#$33zq8Vp?KyKgi*9)h-1zf6?p91Ay80^-C8uNQY zm{Tox#Me{bxr)@EI9R=YI2d--#lx3H97mdi^pkUm*d_SP`z+3voH-U`Is3>1r#C3R zFY1Rae(_Xc;gJsZ4giqZG}1RJUd%jrfFY-BIPoK~bOs|Xaxsw~DPwo*Nd3*N5gBn4 zZ%~HVH3|TRf75$XVi~iN_`s5l%pU}3kBu}9Lp7=0IKZu}_$Zg}(zijv(E4U6`i-r- zNCuKK&yO!N5B|(%9eb-GDB$M3++R<7%Ak;t9t~`d=*aQ`p9iwJzGk}gV|4EKR_%|N zwbmFKdY<~e7o!!tk#z5fMBHWLsiEVc6km&}{?bDJ6dLM=Rgi{GvP52^Gk(t%5 zzD2{4GZN?Ect?}g_TjsU(thu~J-v)5Oaqvs&llZJrScjF(SP_8*T4Cb0s|0XWW>i-;ZuUCiTZMM!yi=O8Dce!e8L~|^(*-g zn&WxZBCEDrG7+4F%e^ydW#tXtTGfuTtdJp>sl?dgzj>4UtQmbJG;-)0noG+G@YxpZ zQoKZle5*Q~LkYj3{I57P-qA=EzwdPUW&9pIA)q}}O!OA;+&{jSe$rshRM2VK@VcBH zc7uh8hTRNBe{aBKMDowyG!Dvtm@CbgT@J0r7Td2mOQiu1ni9LxzZ17h%6cET!G8Bs zr&F9;V|vzvJ8|H!$_NWK`bXBgUzjjuyzMW}E1?g}0Ph1v>lT+ltAt+b9$;8@ce^IW%K>{V8F5IlH0uH5sB2+UOM-_>b>6lbl{=6%e>@35_lsRo zJX4WH4Vi7uaz_XG`(6u5Ykw*g< zR<>Em-60RFAd`vt;t6t8edOEzm_J%5_IYI8AP1jh`Gv~^*!_z{5l3EZgG|(g!Ujtj zulXL}ZjveW$89BPsLP4o4Ms=VAxVv1}M+H%(AGfizjh_*ju;ebVeZL{-j z(Kk950&^5KLkTCO1C8#27LU$?MbHS*6^ziy%Ji}WuW<`%)%kbdv-<%ed(0m5jNb4u zHNq*n*B7!_)EK*6aU!DG7zhZvmv7o@=>Esz%#At)t+Z8uvf_>}t92=u^v)$;%*8-b zN2#gd$LV^jYlVMOIC%`l$U>8FRU5D=9WLtAGppT=qgkX|w85ugHs**UOzX zf4j3gp$)h7Tr~KU7Mbt*RN6y#jT!!hu&ib`9BahCKQke{@Xog@-FMP4tQ0m=HK@;# zK1UNkoOkb3CV|8fz|s284t(cA>47pK(D|`149>o3{_v<%j;W=>zC1T-`=iu30!^(k4wfku3zmc=Nq}8kb8d6KChV)MFP1xW5a^cLK}G#!ndzpa^O# zRa{_sF|S-g0dB4BfOSHATLrt3*n4asfWmLGv+`0|^u)s}Z!FYMim3LDn?-U}F2(2) zIypJH&dlmh_Xg~Sg6Y|(M{_)tBm?B4YEuqwydaL3(E4bS>fI7_?s|GJ9)3n)!66-r zW@PjQk6nJLGJ;8^VTsX#B-$b4<{TLV8oI2;`z8y@m4|a?_WKHnwE(2N&2}?!Ce!N= zjIyW+z1ZTKjAALp(JbeMy$I;eajuTfaZkPU=BTnvp6?0IkVGS4vuexk^E)faXHHl~ zY2R1mQX>OXloO`9qSchj856Lq!TReiyovkt3?L{e^u(I|#FP+XgP=oyzxzuos|V#+ zkPZw_D)-*n=VMIKE4zPe_R}6&RyF&FN{gj43F5n`Gw8Bw9Wqa|dqS0^+-F{DG#UDr zw^I4k;l5JZ&+!tytzf&=JaatWjbE!Zz5bF})F0v+VlgFC(lt9wL`I*frP*)EZr(^P zNgBRuGJ#$C`m4vHn4|dF(?h}DC7Bb4a!1>lMg#KIS?hzD!Jv`IzVwV=okVXG=ycci z(X;NhzN7{TFQQ;OQK`Wg*>BX*{&D=oS;mWvqlj>#gbn|=X)VkALLu|4UxNs;?%Ww) z_DS<&H>P2tL{qx&l9slN-YLcw5GT}gx)A56))41WlIQ@xZRBdg1e=iz=@c_41{1WQ zP~WG>)`Ft>ya}4d>t0=So$*^GV8>I42say}V3;lEP0uUzN0^J-mRE;xbt}*JJ=Ns< zz^;YiU=Y6~@*@iyI@q%fM`i)D_j5nAr!?`A{#hwC_jGX{b?$ieoNmIY4bvuE0>|18 z5FD@f^%p0-hN;A+jlR!`1bqHlu%>BEN9UK?LU)A!Oo?qsZ8Mrc4p@dh$A`J$#}oF^ zw-F;*9}ShlKXf(mD;~KEnVIF>u3S=>JI3mM>V$W9acajLw6=7A3bi^w?@BrA70GHD0~yZi_va(2CNho9bdaY42FiX ze{FZt?+SNz9_IP+Ck|{Zb=*vd5Gu1|^I#)Q$$^{3$}dPq4Y39L{eYrESvZSIKOnE(qwoNcgtR}`^Rj1dl}w6(Eu^_!L-#zC#QZS!wW z<3VygO9E?k24CbTIy~VkuWkZ*#>geTT1tY~oBG258 zgM1^-Y^}yg|LW1uNflgmAuOD+oGm|`gQ6`4`uxIv@OG_1Nmh^Ygb6giUCv{4Yze1u zgMB+&fp>A+G$rsK{~I=NvG>b8^_P$~a z#{u1zZsm$@=I;C0Q{T9ph)i|I2>abvO*$%u3Rl%EiAb4DXG~x-%G!t=!JTzc7MIDv zwG2B0++lbF{QEXOtz-LNz{+bmz~tmNi-vp_4e_#16Ij!&3~zwjKq2K2-?}K)RIE2O z-#akk!msxWDt*t|Ui#Bto0id{rN~V_yis`~>4) z<$rVpw|(P7zAfxfpDa-of_#&x5tO%1Os11vqCm8B0vgw^c~Q|T)s)tgHACikGl#2W^x@Xc3!QaV?=k0UE_BGye@c@(&I-6 zCxKj8gQkFC?9i{`C=1L|kD@HWW9|j#3Zsx{#2UG|##~Ir1KF8x+Ca?}0%|WtjUj9!?kq z#^!?1RxBYp--)x|K1K0}@1pZA(4PGfr2}M-)9194w5#eQz;$r&1br-E^?YLIRNXyv z#+47|PMh~kXm@}AB5cCO@!|eVcbVt9w2A*QtA-3gut{(~v;R>e0FrjoR^i$=&9s_HETV`sEY!-a&^;`57%yeGN?iC0Y?L0Vr! z9-wrfk9B7ak>^DAs|+jVA$>&FWU`~00}YTI1iI25%>|M%D0tE{+8B4Gg;~9-v*m`@ z+1$P*-6nLh);;fn zdn2{i49*ZeU#dcNT>KtT?)-cx^RQHe6wA@*PIPVA>C^MvlQvdnZe6h{?Ho-q+<8PQ|lItF{=^uP_%}Eumf0V-h^Bm9o2e6f4 zVi!E)aZd^^ac{_Dye}kj`Z6q2P*ReOrcN=zl@vf$Rg@O9afEB@7yFoQPsg3cj|87- zhWcb5%nVATjZlrmd0juh($b$SE?n>t+-kU^X~^-AZy3PQni>XQJxx6byTnpaAp+X^h3WEgeK ztQw2q9Bqvz!2eB13%VyZ8Y5w}SFM2G&*JVIX+=b@BgV*PJM1m6QV(WkS zDynH;j1ULR@O{_K+I6z(VNsu<8LJRu3UsB(p!5Bp0tT*n^WYXkU<{eC@?b3YpcUw2 zhxl5rgyu~D@Xb{raK!9^#1X@pf`z0a4Cb_wbfFMrZB_S+12R!Qb21-SYt#3dF#iU= zxHCv-?e4b#jPIO^oz67xYxY}ry%7@eZ#AtA7@|4P8N7XfnF=n54bbg7i(22G&{{K0 zt#l=lEM|{3O)H^Hm_1B&aW540oM;=m^Tgl8v0uTif&-CNkTBPQPpDXQ?S2KeU zsH6Kx{YUo98&w}%a-5IE@uVF>XznasIl7y_etBDqX#NL(%zv=__n>KSt7HGV|63t? zX%R2=ZpkM6#8XIMFWDm#lU=~CehuI|nkm3bo58p3P*uJeB46?}TaYhxPkBH=ss$K2 z-{A^BCsn@H9ADx!;y&YYQtabyb#mk%EHbFzE|-h_O@xxyqQ6hBx7BaYHqN%mt85?dGB29C$oEGaI+Q*3KI!<|FY4nkXexKZPPl) z3Iyex1Hzi~;6O%`CoZoU2@b78u0y6$J(rXb5!lJAo}^xHeHXbZ0D(+DaZ1%D_a>=G zt9PB+3G!+slC6y)X`k`z6fN^VYhCyg*&LYO2jJ`QKMGxF!;i^2RF$u)0>b9?ld(JR7 z=y~ZHsCV~wx5kipvyu5KghS5j;=E5EUI{nsaXf22+w;d2m}}>Y z-q4jFgUlrXr+WMu9FFFq?&~7QmZ8ROyp)z>g*YBrwhmvLsKv^`+!7yr05?Q3CODFz#IkPIhmp9-oJ5+;c`{#Z6KETPVNGVCFM{o+$U9Q?KY9T;`>5)sGWs#mmo@#zBlGN?7RSXYnX4+TSus;E0P}opW z$I``o24|@Oal{22?OMYOS9Q87ept+)G^i*#nXPQ6ewE^o;>10o?u5cZ{pyvdj*K=l z58(-69Dw02;%#>*s%{6?y*@!1WDj5-bTCn8 zSkA4^P(I4Gnq`JAN8e?RojiK7eLQKFY@H}tUH-$eEugdEOctwd04mB#>b6HL>}cYcmMZvMvuZWw`;=g|XAwWRN8)GGPBV*4M)1 zq2pXwdLW4n?Y3In(Lim#Q2KX8tSsNTY<;HM9+$J<- z9_05S^DZ+5o@kl`cyp(CxiAaMC`jXS6I|XN%HK8aT%7b zEpg-1AMIMAFKUB1v8RvSC_#vQi?H4111hzo^4QDMF-Qgal_65Om~u4ju2XEwHHLn( zQ6;(3JiCs`!9FvznB1KBhakR@I|H|t)Pbk<$5tAZCdpLT z&PU?U4zfXL(ZEzp*J&EPjoW;_jhpGOcUI*#!u~DVNGHJ#yBO8!ZAzC{Sg+p>)ghk2 zbJb8K!j`{NRDBLH9$Y`m{P2Q3=An7V=6FFOXq1s?o7X0lYeV?cPt~Ww(Az$JIe%y) zVj-yBKYhBBNO-Q`bceg=&CU-W-VJcxSsJc=ob5IGC(y6wzvY!x=nyVi`xNo?_5znJ z>%my$+Xn8wLchh=aZECinFU&_^IQ&WUP!vOCT?05BXC<_EfRYOc64xFXLp00gd*tb z&pR(yOC~mY=k3C(kU1R=jkP~KCFuRBmCtroQ_D)Dh)&o;9^{z$&HZ(*neO|bdHusF zxb({>0C+qyv7$1pIs`gBg>uS@*-h7NZN;vZSnWJ^OFcZ;_}r$4rf#*c@m$vkdr#z* zWyBI*P!RLJodOGacOE_x8XFZ1EqOE>vJahaO+WEyi?#sMmiE+A)c ze$ZSdQr`Fkw(0(te+<&qf;X~JruUD4;UTt zn4}uNI>EPyFTA^*;N}+H$zs%+vmCBp_x-(PR(u86s4Ld$W`!70u`Z8KO=*hVhkuK{ zVEyA*jA033v%!STOIwIO|08VT_bFqf-Mo$P)){S45DZH~%-9Ij2oY(4e?PhoXDH-1 zp%*Sm8Al!H4==`vQ9RL5%6RU@R z9DcmzVKLpIRIS(`DWJCLe3gMJOtn(WR`!FoKYO6MPhd&ljXLf?PAlYfexc1!2Y!0) zLU(uRqJWI$*h0jxcG*NXh4-%Cs@Q-EPT&-RI_A~QW)e%)(&6b# zX)pBv$()k!b?PLWQ8&QcO|4?Zn&u!XGggt~9{(EKi{D-=rBOl|)Enrbnxk6dv;Dia zX|@CJ+Wf`*wqI8nG=qA=q6zUwpI)||DT`vS2*P&*PQ~qCU}65lElel}5X zBj#Y${l5Yu6MK+c8R<#So_9N~=l>D5`frDov|_c9MW)bBa1%=$lO&x|w&E4x^9<(L z$jg81q@82D1##*&OmSVaFIeXp1$C*?sWBAG_L3PChvZf)Ir){-f7vij4` zq0+3Z&iw`48uCpptcmm}_dAIc^bQuf6apprq!-YZt3y-5!s>}tL9}n{$5{17NF8Iu zvXbiFrg%?VivQSe;c;D*fG<`{(ObFHZ?aDyf4e=tD6(WJG0NH7Hi8^izci+{h7Q!+ z7c}c~nE$M+;Q?~xKc{(BXMLS<^{bi4y_D+gNiQCwmv%jXv`KrQtklO(w&CGkqMQG( zAG`kH`Z0-qv3v1Ha;r$r5nLT2bkXF(ALGnv(}1j>+kOjj{`l-o))1H<1u#)&X{WO& zDlKYSbd3P=z^7dT26mn52p1N!fpneD(_lP~T*lmj&Z*|YMZ$#AobkPb`VH!;QpYwy zxK^6lR8vF7teJjE+DAubBeMqNdeHBMLtg)e<4ClgD6$h}hOZ0>48?;FJ%Y<)WEgYH z*JIl3lE>pMR+*8FVB-gQ#^i1E4n`OW?#xetmk28*E}kZpVt zSML6zu@8u2G8)*=%%}4e+iItRk*6g6BAA9~-JsNq*8-D7muKSnnjP7 z33$aRTRrf@E=z5uFy+PaDb=DSMfVo@I~~vCzD5 zNv*oH@Bc7*ZAPd3b*ewkY_n}-UfHnX%EEAR;)_BpsJ#p4*G6YUsQoLM@y8NBv6wK0 zH?TkqV>NgX|7~SM*Wdn?*v8qZqQs@~ORr&RMsSl{raU-={p`qbvv$8_PB!Yp>qufz zXu>)~SK#HH;@4UFUoA zDgCPx?|CN=no9t3(E1jA;0tgB6|6u@T)IxMDdWK64CHAMq|Ye#e8>vbah2^3#8*Bd zh3PjPf*h!fh$4nX{vZs4WGR|Lj#iG{2r#&sLzxjtW#g>YaL6=q`hAn@n?o?Z{dzZ{ zA(OsiZU)v^S7Vp<`KV&)B<|P?Zx&_u`B^dSY{<6fX_+5Z(}>bxm@TJYa3(Lz-KgPf z;g81@mX_A1?t}OEMvHYd{7>0XO|io&qOtW>GP_iz5CYkwL|{<#9HwQL8Psamn7kyu z)~UjSvzqB0tzvZ0h}jXVsjB!gGP@JN{dJENL4{!0maC9Hurc;F2PWTNs`hxD#m-sv zJ|rt+ncVxqD#vKtN>Z(d+`;QQI{9>+rV9pQbFoZ#)mCUXu>fGR_Y-_6XrFT-KlWji zCP!=kh0nXuWaNwx*?1;y0*fQc0|>mvBfbcNoUDg45ngS^hw8XM{5RHj_LqJs2ATqY zQhZ~59GI_ovZ{px<8S5zC2A6S(p4uiSYK;MyrLs6vAO1$*}T7cjn@o=eU(#X7KKD^ zQ!(dj(pPkkB~ZJkM~#RY(3^QI>7RR+xMSvxR$<99*s-ItOMmXYX8i5!(pWX?n#AuO z2ROwk`}aq$=>A-MC@ypJruW%v1hjKLYu4yqqw>YR$x1;1Dj{P zIs;X`PbjSYGwXkb*3qFd^3h3&N;sY1LS6J~ZG*qPY z6cO`Lw_MOc_J`VJH6GV25CW@RqjE8m7F>AuRf|)vW|8FO ztDeBQLmc?ZhPq-5_ihO_NJRGE+!}DQ0EOsna^yw2pZs3ds(@p(>Fv#Ihe{a>)9lU{ zbVZw)N=lnkyzdlC2(arLPFB77I+>y~u&rE9_N6GjE9HU^v#z?&>&EKd)d640giOj+ zXN>tZL9uq$fx}UcNa3m-r2vJpJ4d&bbezU zJHjd9^I8s(2E+$d;aAZAJ_REh4)Ndqj}iU*9sc$H70~{b{_!BIjMK=%(iGQE47p94 zxIN2wrTN0m;DtgurC%DTiU}VQbLi@>V9mPLs6M6Xg+Bsojd?p#73qDKz78L1U=ASn zgX+n1HTHDp~77+@tgQ3mhW5ZQ58b!_pVJQp7B=sa%-3X z-1g>|&(4!ovWRJ82Red-#%Br&NB#%XbcokXGzrKV+j;`o-cf{UvA7V4<9LX5SZPyu8c#P!Y7EGk(J%sr(_+c z1iOg;vR1e}iX+{+fm0n=PaefTox#7>?k`LD@5}vf{sW(zycG| zxXMFE`a>~wLcfRnIS8|42%vCz1U;RevGW14z1`f~sM&p7)G7ITr z61i?Tlp^oXy+OS{ySpXIn6G#BLDU5A#_P@Zm64R`FadT8mk4sejO029(#UBHKXWcw z*h~9#bg$m-p{eHN2k`X@1rK3REQQpC5qG~pk4~MyT*>Ni6PRj0!lXzR( zW~M=lo+AK06fvDBV@F}cpSU?kTe}oM;q9nVMY<3}q>5IX6zt0DWq&1E)7Bj)oFD%V zI&er(ZBwJPxNa$hX}@igp>e?`v;-=9dkb8ZQYdKEl8_8Z|fo2>jz~C`p#ki zT536@tU0skhbLwFN<9<_wTmJ!jXD#XrGsw{4UG9<5F7gatSii^u4ujy#amv))c_89 zS_9;n>YOUk<)$T3mUG4X-I{SR9=bhASI3(mV>0v+C0B*J+>4}BnsgfKo=D`vZFjq=TPG6|u3qv2Nj^rB^6v-$*)1`=S?@r~1}zHF6xCvlRJA7A1PW4kwI zCA~2G+=DZ%1j^+hmy7*cJRwfM9>V7&n$lTI*W+k<-ewGWu&x~4cW*1YK6&0VFd7J~ z{FEhF8yqwlzf_olGPdlt9ebZzKt_>pervwm$65UIf6zz&!!rCi@@!%i5he(R!FYy& zPz9g1W`5+`b1p}hB%Dr(iPHq;jA-XWFAaqy%^QS^cIyd-0CJttR>X2^=WbD*hIGOw zzsWlD7|FW1rS}Pl==I}iG7z*8tB%T(O8it^8Q!t0)JYMx7o05J*>Q;%6XOPoa6LC9 zmL|2F5~+LCpK&)Aa7NrFsG$cs)JlwN|fts>9Z`X$1!-}5Cvh?Oxr)U?w z=;eKE)T#}oRB$YL#4UL0%kr$M54im5p$9?<{D^R|1SWp-J?Na-@5JTo<PO9nZAWmd)T3_*;#7oc13>w6dA<2tpg-OeFG#TlmfVe}Uc8CdeP`b7}k=5eIGP z&~0axt&ZSwDZc8^y@vg-lYfIGB6y}Gf@C7*`49IXg6Dr+^6pd{);Rv5vcYo506CbJ zL+;Yp@JnEnPI~Pr=5$eCXlw&Sy8E-B8W@M1l|l`WvAYKCEM!alpj$N$9&#RwoDflj zE~0jWcOf<=JF;7T3AK=fd9F18uDg<;s4i>@EZSrN6y4rT$53X#G`ioDn6#pm_dU{`+f77|L7_xJ_V$bXZFmfcCu0&2+`4xLmt>ge|K2_RWNns57 zTHmR7iglskXqgJr7p5{9r~p{X;fIG*$ZJP}!y{i$$&7Qp@EqU5ZX)5X+p4Yox;gYs zzJ7gewlOF?x2gF;ZFWFI$4FlRDx1H02DCY{dX++ErsAlt3~>m178kk?jC(kx!YgKi z7a&T~ST{{G?c?~O_vR-6qnX5xSTVY)io{j{a)+6kq|6Gx9DU%HBS8`mVqLDfhnRir z3b|G+e=Oj@zmtU8oQcjIedhB(BXDa} zha}TINisz}MlUXUu?lXc#>!zUt*et{fW^l*SPv&O`T5nPB@^p#N*$%`MZ4B9v2 zMw*aKSsIODk7BX5=GD9He)@<~n zaK>q#@0Pr#&^>k|uRC9i>U;%yrLe8HXP@lp5grqI9%}mWMC-J7z6qbK`NewHwb9MH zip#NVxf5SFU<0NiZk3PcEi}v@TaZ@8_>Qh_$J5t4xsrh6nKx%TtG)hK{s^O8MqNj%~2wDwMNBa#q++>OsrMNrPFEuv~czdKY-VMq2(wv8pT3P9^VTx&V=?xaYG0u&faCw*chbH7>UIzOaEN)y@ZJ!0 zQH3CR`P_0^cZ!#4uJzx$#eaOAtiIQ{U8ZO|#_;_)F!b8!f{hd{g+IH`ZR*5i;aXOw zZ5qRIinCqDc5YNqzsxQWIzrl;5O)0WO^+3b8>3d8a*2rT0uD)*5{gXuB-+VlO%4IIqI2edT z%K!`B>X_#pnafAk3GWOQ{od?e{j1yiKiGt}MeKriKb>5^pPoMW;~rU#acIJWr44dV zi$>^Za83&(c)JzSCB60tb4&t)E0-`EMTS^_&ff_yT>gmK&7`m5-uyr;%Y+qGmpZk) zN0gKf@!PTcqrY1*=6Gk7xDJ_1qvps!9}0h{8Ou^18yX!ZQy(#d6j`#Pp434iTZPN% zV53N^EL%}eO3Z|>bZTG;!RL+)QNPzcVYkB_x)Kgz(H8e4^VXbI+RwAn=Hn6BSXLP( z&zXUm5x{7RSIy76sdJE?9S(a&vf|Eva6rx{QJtjYB9oOnz^hq!;=HRAPQ1%QT^F#SQeoj=DlDYoy zM;^AD_aTg+!)dWuD0uV~+}czJ@xFBzif454h1}ueyV4IiB*1+SHIKx0n4ybUhE(P1 z0tKnBVMLMIj^JBq}ztsK# zIR4&c{`s06|B`}Nhlk@%2Tcj9PEK4gXNl+e<}dK>lLm90DXuZrrvY@w=A+*b#T`EA zLZbWx>L;^vj85fMPm(CBH!$v|-MRL;hS9f8%d#h@%6C3U__K#Ka=8oJgm+LK-YA%+ zSX|QgUeZ4^<}t1|&HonXD!uv>Q;fq{eTZ#rsa#)Ne()1OFR7)_dP;^VfxMGld&<^( z+8LVb*;Zx;{3Am0AveaElRyQ8da)XHecRG%tJ&SNSl{GF!-aq?mDbUgd< z!BJRTd6-T4NgRBCq~UtkTCaK*aPcTiYOZZ?$$sMWs436~zx|LKDjD+i*@C#e=0#T2 zYL}AVP?241a0lbb0`4fW%uj(ay)Ky3ap3np&)^+rhS?-F4IX;gO&2$v>B%l9%f&BA z1^mIG%BelW)4VyOnanUh$@zgmph`47-2vdwP`LkljLCHS%!v=QPxqX*ObAZ{rcswQ zhSDSp(*(^~kSrMQ3JFNp#Hr%!!H%=MG=RPJdCP+SF{-ofI6ldzK%kV0v}IA`Ex7C{ z$b0m188Xz>yg06yd52E+m=)l0x9F$O@HJQ^Ma!(u`Uv06;v6~*FPXtVX9RE(6;4|= zMA2C*O^Q#X4+9O=(eB}#e<}Q4nz>)RQ;*;-?T{5$*#2A1=QK?_EEOt=7gPuZ&l$8u zx8oi$bF>LW6e{g7SV5w3P!qg(QTw)jI=cxPlNA;4?rRPe4@mZX zmB#Y4HHSMh_Ah0FefeikHzdObY-R^M5tWv5x%w^>`{Qv8B5vk8d302DY5M>tAexL? z((|Xo)e}=-Kg@aX;$m~wJN5PWB4Ky1R?O%f$c$H;`6<~A62DBc&yfm%b0}61UQ`+R^2Q@Tj4W`4h zY10ETjHZ1hM@eBlk1&e=e02Wx2GUeQB0aYU{-CS`lQlp~pgLnITaJn%4XxWKKmeM# zw=NcnCg*{vsQbn#ka4aWR;KgNAoGhL;WZjX0RoH(}@yES<2mF#qtuy^#0=(D;jCLiD)T?GlXHvwRU=qjcTUp1KeI*w-%GM ztx47Tz6u}fUojw8M+0;E50zmKq^1RNdB*36)0{`|+d}%D8GGZKUZ1+&ygz!pnB>pG z`Do#lPwNk350%?gQTYqsZiKsYyG37a{tp{zz3~W5Px8-aND9RrmPLjn7jiy{vayKd6!)?KB4EwL8+B?|YPpxRuppp)G{XL>tmMJy2`L}U zH3kbxW9X|W615xBQP07R!zeR(Nv2NvBBlaO^2)(KAA0=p`X+I(QdZmpx2d7kc(6

h>3){v29lo@AF?`lb5zd=T45)Uh?0YPJNDbnzW)<-}L8hl$-Cau)ELibLQC8 zR4B*pZAevMwdH@YP~=Kf)1m0;=?1%!)E{_mH+jjBmnJxUT*-B5i_9HvWuS0Q!^?Xs z98zH%1Z2~^`4ZT)Ar?EGd75q$KZPdMIA#TFl5SHjpJ24d_oGXn_4%Xio;MuJat4&X zyNP+(W%ud@qD|9k=WD`fwZ*Kc`*hrj^TgoW);P_bB{+|Wd&^76@o=n8u}I;RH~ND~ zuFKRqkE?CI?5%y(*spI+d@&vvMMQy(ev?GU-u+$`#c{HC;e@s>X88SQ!STd~vE%b! zEbl*br5Am<#c;U#L8P(=zb{;mh-^52%(u(xSN>*tblQFm{k%(G+D zjpIMaQGQMnxD{$j6`Zg2K(eRex$C?cmdlvcnGhNF8ZE_Q7(C?S5kW)jelR!0vPONx zou7W664nM(Q7S9Gr5q8wA=FN%;h-+Rz(y9D=8{m-C*?I;VJyYfbw(SW%X=4 zd>iN0Ob0-$&%ss3(S1JYa0GQ6=Ykh_q92{K)T5%r^rG~{UVZ%N&OPv~a=N80X znv|quDQAz*^$~MM*E!$m-q}Qg*7YVIgSHK;{o~D9 z>`y5u?JDy(s$p3KwdLNi(u(c4DfR zl(vc}M@t*p7#-K<3U3co-25_d7O@WaZh=pe0Qa8WV)WVQ*5nl$2cLIr{8|o>vY~c9$M6oYN`~?XZoJq+tteO#I*6`0W^O_RGK@T! z*Z>o`>=r#Wh=n*qpnUB8tTQbz<)EYL%Lll5#^rGVAXg*Cpa~jygHg9O29*GTMZfUp zc=puNru2ruX{;vm*Xlz0Tw{+1bp1>Ou|40WylT#F)a*m1qe?}a9@1h?seEK+xjqgvoOfb_nU z@;IcKL!mm&UQX}|2s)s3t(fyNxBb57PHUZ{G4>$TOx15+bn$2y$Ib}tTQI~(al^uK z_0i~{jk0(FBV7W;wa*Gqi3+X1{I1+71HDXyT-=X<21<}qX7rMiM&+tvF2|-Mh+wkx ze7A4%%!pkalcY|q-G5%3+{=fycGFocTCPYTYQvbbWe~MtW*OI@Zm=DRlzKN38Yv?# zm2zZZ7q7QGm0=a{y%y@1pP2Xhm$ZMv%Vl4)C*zvJ5{^t)p+2ggCN)i31d5AVD{i&V zW97n-8V=ZoKwC!V3{OMRofhR|pU%h6`#3w^z!gG|l+%=Y7g)SyEQ;%6b5|1<#Ib|; zXcM)1eG7;2K~B`^O$K`TaHB`YVf{`mr3v%xm84ObN@y|+JgpB!x&52dIS}z4Gq4z4 z2>cyng3G#!Nf(A589g`lzl&ye>=57R{#rfX?u%f1+*?NvguoMJbmncAdb4g3)!x>M ztnfUXdse(=domR^%soQ1g68O7;|>q<79yXJtBFQGSKrX8l9GYdN4Vadf7?jYtwDNg zEHFixSYNJT&6+w8Q=alxvZ+%{NJ!&sNculSxp^kB$T}AE56a*jhZtG9ZGmcH3j*$P zX`*m5fcgC^flhEkB~t_)AO!Xp>|$Zw$}m^gB5CpB1{c8a0ov#W`znOGxUaPj1RdX`#NQ$f3_j`myuf$ zfwhv9CQ?DAL=7JE&5&6GQlS-ZDS_W-vILss1`8IS=Q`=^r4hcx5f-QYAejeZM3*#p zT$-WtmYrIIqq&=WIQ+JE|4U@eCHlw|@ja84ul(pN8&k7S(`h8D?CR!T!Hvn{cSyd} zfb}b_SD#zkS8lgZ6~Z!J{@nKxz>Zr&jOekRcPQ^YlwlF3(^wK}E4JELZ##Bt#Tkp7 zb9I7{QTKS80#_bFq^xf_dHD+lZgL)gx3k%eaQm9O{X6rntIC*?k54G%3C^Jm4Xr^xyk)ES%Lqsm9iO*bE;wUp>YS)gV{*kuDVcc=-@ zox)KMfp6Ge_Cr5waXNM;v(+&?%016n?z`O&3Gv4!>u7xAY>t^N<($B6HA@oqiCU_c z*piRxV@9bL&Q_I0&2dqI3$XtS`ahhP#db=YxZI%RdGVf=G1L?Gpx~pz3X9N}RM=IIX9CoouLmqY+Qh6QxR*-ix9jz4sDoLhpo5=)Jd45^}<`_kQ2~yx%_OJJy^*cY`n2 zyi_de8e{%XYRwi_TBcq;g6SocpE((+f=PAyGGOwQcoO@>9mUe!tO-W`*|!?v2lT-! z;ij7_mGG*ee@jpb zN=BX2a^F*uHehsnPGB(Q{lafomNm8@*Qo0CSfbwGE;(`|RAStih3B2mh zS#@wyGS~Mc4c75NmOQPS1M{^tE==38zr~N5 zN%B_2Pe|Mwwn^K%wH4cYud5!GZI=6^_sg{^*(-W?BDSK;y3+3>RgeX2I6uf{$rFN-@NE&+d#_TfG3QGb_PuYta%LA zF+}O$FPsHqOZuvltTazK&Z4^xac&vn9-;g2Qn7<1Ut0E|~;05s90(7S4ZSW;$)$4MD z5|Pb1X~!|yTr*Zo(Z!+p(RE5_?U$Pik_#2g0e6@*IyZ|APjjv(XJ!e^jve0q?WFn( zyA#!M{atsn4efh_D=OS6VrdUNuAg@N!plGNOZv&sX@cisF&yJW+K>A_o|0I+n#qoy zTLAcbFIca10BcoilQVMMFS6Zs_GVlj^ErWY&})L(v&I%mqcW?p=X_+seTEZ<4_4K9 z4a27$E{K$(UT7Er8>SAg*+}fs2zcnoXJPFlcf?vt&O(9r>~~Bp9|TauiFbN=9p{{A zKQ9pwuH#QqP;llRF^+T-oIt^{q@c}z=$79H{n*}H8K`VK?%^5uMTT^o3Eszm7C%)f zzI^$Ny%rlp=Ds-l)H5Pt$12B2IiUGKj&BWHqB&(8ZflUlQIy z+|lI~XCPLrXY%g1%q+42y~fV7f6~T3_t_v0&ZlEJzM4;K7{Vfd^a6ge@|p~fxLO2C z1sxZzY1q{1coYj?uqpvb{9B%vx+of~gfHtgM~U9{_qxJ}2ia3!kFhI81yZsnfA05W zYzy#_o&Dn?Y@tDc8uyi+vISV4%J6le8Ym*07cQT|Q;e)ko| zn24)F9hN0HI=ME@;IAafyGco4w+TMU^6Ba`{~1BSA~y*CW3qVelG5x{s(kvx*%nXn z1IE;Z0|x3ZFH1|S@x@(cy3(&pb5?Y*Jz5Ps#BaS{QTyBDXm-@YC3lhdM2%){x}x8C zI>m`JN1Y(}w*LVsA90r5d;E(ThU#xI)HdlW4V3*`s|(=$A|H`Inl2P;0}0JornTyF z%Vc+6pQoOQZf*YcN~gd+{L*!X4`&>#!Pxr5(hR1SNyC=Ohxba^h?QiN?s`_|y(zx=cSrbdUQLpw$i_`mm zr`7n!{`N@y1%uR&1_5o30WN`8%WhxStVd1yvQSWX*GsdGK~4czGvAAklp~~Iw?6@n zZ+Vyxy=c=(7oNG!$fA&U1-#w_K;BDjdU@{FG&XjeE+|~}>q_3uzCeHmtZDW{AFbE> zeio(sdvzTprC;|IO#TE&=&`hG7jJ)zH2b-%Oa1b@Ht$O&K`bIQn6+-pcf+{(OEHT& z1w33Tx2Z2d*zOWH{DDj93V_V{*Q7vj!L_r&izbiwa56%532J4C?#GER=OgA3xwInn!$;HsbeX6p;B*OTZHq_mFhxmjb8BSg zX{8PUb<>+qbeKdU%AbOJJRD{Mod^o*!2=<+i$L;wV+>g*0 z{7p3WMay5X`oBAN5han*`$9oeR276a8$H$U#X)8jN6beDx%$t+PzCq8X}S$}o(j~< z^EU4)=~-b>7srA!wIaK^**rMABos@}&4IGA^hW7Xm(NW+`V1^vpWgu{4?ws;=BJvx z-x!(bYJcKg1p`>g7(EwSO{oeXMKZTVk86EGkJ89^9XC(7So~u%8s^GY9@JT5MQ)5f zX;8Y9rV(}T#W0%Gs~t+Xwb8wu?!*S)&q!z|p3zOPI-1X_+jTkag#mizP^`@I*0X^! z_8zL;kJ(+F#$0yhpDWa3X}IF@*_N1|cbSNRt91KO>XZkQ=MB3r%A@y>3`h4WC2eds znw&bP;T9`4uT6~I3bmt{s%D$ugO%eI&E*tM7@oW$CU?S0z0E%+KbZs`*1IuB&3L4} zQRNU=%b+|t=`yyQC`s;6)^1rNQ*ec0e{X7bEGf{{cgNtYXG3G2mWygP{h_m-|Bl`I zGo{$G{KEm(ql(^EE6*4@)MEBpBB79vg-_$Qjb-aA?zy@ol4kLJi*3C97AP%!7z(ioi#>7}meYP8!O&$(T+X{HhIGu4?^&P*i*V_>Jh{nldJ@Bp~5z zYrIh1yOORZFIgh4{P=ZZY=?ri$#&k(>nlo7577^Uk2HUSpv@_CGfi^9^qKdc4>s~( zd$YA^0-N)i;LYjtwUKno+hsW`X_I-x0P3RQ%tvE8u1ey+k~z&iw)_wJqPfkG?@cQg z{*>~PXn~-(Cm1a!A^eFe&xYg)X^Rw7vxG#K?n9Rm&8e{+d!3Vt=uNLa!;`VvwGlJ1 zW;oHY+^3$jmd)xI%nK8FntVM~KN}vEZa1i4RHfQ$XT8~UW}}_{@mDVwO&xCC<6C4~ zS7~jH;4N*RKK@TRQI(@eX!i_|0Utgx@qp$32UxXr(pE7~L;T`jt< zKW7_$h|nE%Hx-0-f@f$pjV*nM3So}i^p@D?R&{g2;=JE?R}2j%e-c^q{hY1QOBP+E zW0Wsl4j8CAWtj1RxPs$cSHWs=X5>1nBCB^Oyld8SBk#F}5eFG=wajREKo+U;U2fBc z$t4VV!!N*{5W}$M{>gjS{~~9#VjHWpfl)L-7@}hFEQXS&ToMk5XBV|JY?QN`7ut_1 ze+lLa1h7Q*$&ih{-){?eJK=iAYr|yoVBv!#cE^Oxnp39YT}kSd!dsm?A-;MjKZYdd!4Xpako!uJezddLZWw2F*sh({Lc1$D=te+ z{;;(uzEfnea;JwWoOgc6T6pixp1nz*cEHwneD~)A=V{~=|Lj%fv~s_f`YgDx?Jq>#0d+ERajuYUM! ztuZx#T%UT+IwX{bn%JpU6X6VX;{NC~8>Usp-JOG~)&VaKo z(b)G&U39qRQ_-K<;agaCPruyhhAp{hovnTisV$L_C4-FgqG^)5zeJJ6gO@!rC7~=f zDfru2f_aNqvsF|A+13(y~j_KG{e#sOs1k|VRtfnQ8xWmyo9h&t-)_EnwKVMU(zBqxzz}IgaxmGT*h#{dI~Gf5{T>PAEa@~U-f5$BK&v;= z0{}``vT*I8K&{#^j7{yg+APaXa81yP4MYEV=7xx1-**jgQ1BV_j$Eump=Y7NDTw^6sNZqIB*9yZK`{e1~&J>exYn}`xrVun^ zR<0Ad3`ym~1dZ0Nhv?sba*&q=eE)My^4y#HV%5@bQCBT|BX*)_1QeTaq~MApvZS{N ztsFTsE#eT58r3ki%?Bh|*OM2bTa)f+2<^d=9@RktS2Qvp?%{F{yS*#glYxo@6Rwyd zcFxMXr^IrRG1I@gA1o~|6ZIFpzt5Qhy;~SoFC4;#EG^g9w{u?Lt%SjUPFT@5^7DcB-HoKS3W~N)X-J1L(%0edyog1m{QFCNkT95I31jl@QIKP z6)I~!;bG~Kh)3ghoa#o;nI$z3ST3e=A1b?ueUI(6H&IGLPEZABI}v@x?xcaA6qZoq z_BZ{*s|?!-budKb6m_vk{EF*(7W;<-FgA8>3fmD#K+2L`Ks#7Ou=Oxo1D`RakK*{e zu+Im>84hb+9gmhTF!!Ne?L*k&1!+g?q3_9&PTY7C4uR!D<6wwgqILgRYUTf0Oy1BJ0aCX41?T-xZJ zU6OwqGqRv`ao)RQRvA3$I=!?&f4VHH#mJEC$!scEU|sA+h{&e=xX6}SML&>Un_8hi z?cm+tqx_$%N|={Kfpui8qc=k<+iUdk*2zuf#T?URUV}c_Iv2x~bN*J1w2-}|G_1q8 z>v>VAA1niePX7TG5QG?93&Rk}g}Yi+hrO{u0}A3|roVaDpS|l}+_Z0j6O~&m`J!DU zPRJ*=Twc;6LS>o!zWekS@A>p7)tQgUD%P8SwZMKU46O0y8E}r`M;6V2EA~O+&u-ad zVXjV&B?R_7Cun@5J_Cld-o}Ofmd|D)0Y_QN8&)pi%S`TE3!GCejY`C9DjV^5G{y}- zRH&}G{;pC+cbgsq!!E_2jck03)^39cYjw($RzAO&o7z8N5&5Mga=zraTp2$7rjW!x z(k69&KUdf24T7`n!xomB=GZIV1r7B@C-=vCf=VqB0d*pCcRA`VST4kD0Gd%p<}Sm} z3(gNt9XlsVm($GL*i6%Ad{C!1gWzd>!x)`~CA!p=-=mUx$B9%HcbPlb@#iFkxHY~U z^^3ZzkC)-#pm30;?eTo~fl}uUV?rya0#kM2V{ryfa&;yf6N`?DW8OKb&y@yf(CE-M zCTeVX`#-Ih0=qW+bo4B=2*mv2sM1fn8hV1-(=@JU%@5_Y@hU!^N&hew&-dky-~L=!e^l#e<@xsIR?{BI0_!gDm!(gU)ol&uNT-fmmq+Crj@MP)=-GsY z#TX*&z#E%VyC*&lV^wxmW1@`yar_r*`7BV1pS{Jd_IZ0?`Z$0}KMF?M96O`;#;45o z_MTAHMR_xH?y!x_r%`EQ75h=(J@;QHcF_*Wy*sp4o{K9ft%8eFD{&6nVJxqk?!)J@ zJ7lUL2-qohDi7 z%6dr2R$E=k$$Y2Mr?vy(;hi(C?UY@vZ8eEF-iG9^d7-4@aW_HBfmobaMV1>>)@qCS z87ymQZR%obZ7Ox5eXzPTzEhsT8Xhr*J1yO#b&<17t>LSF(;q%H&kV{ z#}Wjw1$7`oKu=Fw=+=#Xrrp`EjbAV7; z&m3k<2@PRRi$cL^>Vy`S$ zy=s;WW_AN=0``YH!7^!p9nhF%k!cdr(_ZIm+aEVNX5Y#1<swnp{=_dbdE)Z-e@JqEF%MJUucg3Vwf#xmzOMrs$LZ zA7Zfn&x4xc!vYq3+u4AHO)UT}3RST0zh#-vez$@>s|c}QuO0_Vqvg>kg5u87>OK)_ z|9#w#){7n22AL!aUIo*d6HKBM%#=dmuYbZ=WxPfERU8#*t8BYXC?*fbP)A)<;$oNDP}UY8%~o z06I}@&?(KYOrs|8n%5C0+^RaoBC=^<5%(p0si`9^VkM0u3xHS_`r zr5{6YpY?sPosPzz^tHdb+=8$70;WcGo=S3`1|m5r=O#-o z@O{zsn1)zCGM2HMhT{?=ho?R$qB4?np+9Q}|Kyc@H?%@2WDf9G8Gx)MmXh4PWTLe= z`xjyD@c-tDe^MN0_OV?4HKI$3+W)?2(;^cx^b|$*OZJBj^5n_~pd-$GPICjl*$Tz4 zA!M>IT>K9kB3vH{wfB>J)qo5gxALRlVJ@+*t0)aR?6EG;-`5AE9n4?7II^X*RWr@U zv0=)qw15DJ%znXjbjnA@rO8OQh_X=`Uu(-Aq>>ePC+3RnJx1KsCc&lKU(jT2-$?oy;z3_J5GF{-xpthcvb4zA z6}Qu^AK1R#uH9QEEM=&^&dI#9+4i-b;s>8cR@i!6#_8xLfib$hZ!k~2boV@EfG9c1 zV_OOMm;Aj}+}|qP7+PL)nw)w6U;FU#gGC;XW-2dcPkV;QvW2K{ffROgq3#0TENF9E zxEvIe;;#Q`haVV>BWcnCN=edM`aS9g`s(x0jwX&ZtO4K%mhTWn`d~oCNX~R1*88C? zRXLY-^43Vj)=ZiCP-1$7OUoIL<&!6wglDoi(({IlgELb7klB_@S={mQZ+0nvb5m-6 zyM-P^#G__lp7Qr9C7aI_VQ)?kC<+M9#qse$%K%99$;De~8es}e|BoP!2m4W0Gj-KD z0jv)`7BHVPIf$R*l2xOvO&r#G8Txn?4+_T*=m?6^$kfZ*KoKv9NR)(KGF}rTOUUcu zzs2DPM}AZPtrc|#RJwu2wR~yCf6-w3{BJJ!C;jn%3mwsaUnE2zz6Dunu#Y;01Wq{T zA2sJB;OVK^U45n?SP0F_Pz~RV+m@|rajWheAuT5U0fqtRYp7X+_wgwHnezH~wqEx8 zVH1z%&_>VRj25Jr51H6_f3dUe`Os-R(iuu1k4??j9NHN~=e_~Dr?|U~#WUK>hZepN z2Qvy{NY3T*;ixptVOB=`xJEFfseCVE=vw`r5}|kYGmZ=2M>wwk;Ew(4E0ry9LFkL0 z3HP~xD059_C3y(l%v=jxVyDyN^5A9g#W$2TS zG%Zt%MAwJ>5O`u^VUBtNhckFmt2@Y3@j1*RJ*1HS#CD)V5{o%VC8a) zU)qb;fI)&K**)*ZFibu?h`-DA>3ITN|E~ypgjMl>nUWIfHYtGC4s|Y_gz&$Xl<;25 zDKnI**fl-a;N?L;y2Kur^|eQeu^YA~AL-V;t1r0_K1yo{(o&ijd}-6eDCq5odmpmk)w4+L?`z7dm<3 z9y?w(1V=UxpbDDmpSTh-!lA>5?t^J7G@{Yej zy=|fJ_N?O!2re@UoAM9$m<$408_!|O^R%^Fp($Y*3YDq`4i)-0z~ZJwJ<(DvYFF$n zHP06IUKhRbIJQjK8pu3xC_BeKd-FHV{`bkROxs3ClMr+j6-|9h=!;>9t`4M$ekXo* z<@-^e@zBB_Xc6d9qaQ1nG5mTKsb79iNZW*2V^c#Qg!XM=T5?(l`TN*W%HIfhDTq8|AechKF{+FC&H6}iW^>Wi{)YilFjM@SRc1Wp@jyFl8R=zZ01Zf%`PxA37 zyRV$K`ER@N$Esn=9EqOV2!))1|C|IToD&yz*;4RdBO-_$H(Y?vB^C}zA$dPg=Eh$k`-Zw{ke);7I)O^Xf?aa-?L>xSQa^o)XjLTbJ$0wZ0=Flmh(x&it)mp&^kk8?UM@FeI^Cyt$EpgUr z;d-bS$$1-k;y3O7@i)9-FKWvTIp4pyD}A`5lRmlhclrM3%qTpP{6&@Y7y<*Ukr za0N7=Nc2Ae{lBIZ-37P*(tvxQYSkwJeTLZ9?BJ$ZUl&v4wd|P~#k{rAP@$WofSQ|8 zjcmuf0tDd+y4F}-UG2C&9D&8wJvsqWVq&Rh^Q*Rmy);kQW3N{<`U8Ruo6LZq^ZCL6 z_FG`mt~@YOF_N{JxJuC; z_>;|w1K#C)NX;PZkTN>17T1?#NWX`{{}`I}a9iJj|1?a|7LFW_6sA8$!uhlI`%G>n zXqfIU&V~@#u5qX04_I8STaN2=JAQ6hAsw7CSE;0o{}URVaJM5L21Cn_{dwT}rFl0i z{j3_He}<1_@=2)u9etM3eBzdkO~1-F7#2=?nxr#Fe5=Qcwnow08XKf~^E{O1Qg3a zn@>MPgRG!fzkh`Py<9%sH>bMq_VYx4W@&c@2WiH~2c|dkHSZ3Zq}8|BeWoG6CkHA^ ztcsZiVaGnT*(#vBJfz%#1l4A+hlsuPqW}6<E}B;&%1T3MZpk7 zZhxlQ*gYg9!}QbTo)X`lH$6SLmR8&$IxKd~`7Z-uDSsM~6!5xR7_IGt41^x)$vJ^G}AmEuB722&)~hQYPnsH6+5 zM{3QiQGuHkdl%hhi_8cZ(9=T3yTa?DJv57{4*}re z68+}HB7xA=O;9#YJ0buXF2~5XC}am*>>D-LS#Z^$khqv5$52Hye0=e)?LK~^RfJRc zxAuXSeTB6?Avjp~?2HScG|?Vjvo*_k=C*_86)Su5|dy_C9 zR=$@_==4y~jRBIc+Q?s|?$SGcay&5tx&PSgcOYhJx5 z)Z(VN>4P?UOTP@Da44#}xYahwZQR69ak9Y#5(vmPr>?-w3$vYb#Z)|{@c(dj`!d(h z7Hu#?ro49{OV)9$1wNeT!`^&ea@WTi9)z5s?<`}<+CTimTeTmyJrlg9-KmypVjYCno!FLy1;moFD7<>lV?ViJ;;t-sjrSEwBjc)1H?Se zNL$FI3LZKUBuSfiw^dK5*wyx4MryS>jqWJ?X8HX7Stv_tb->=-H3~mYtkyfq3XW3A(*oJeq`yV^c zgft7dwXb#~cDW;&ikNlx)+Y@^`#n72^%tpbJyhU(5?BB{3##PzwTcn3($x!Q8 z3A=WaB{E3auAk&rB)sKzU3cowME6?Z-a-16Aua7T!)iePFFg7uqi5k_9YK?@EAk5R z+1j9dq-j>@05RG!Uw%rm@!~Aj zHs1#^qgS5+G8{}T<)dK)y1D9H3nK=SSplal2>o0hjJ*5*UDQ&mGxfXfqEf%EVfeRm zcyRT?=adc-+qk`6xT%W4{qbc%cNeb7pNV6bx9%T0B=lp@n8GbN03N_y6Flv}q)QkE#;KG9@Ix@B50^ej3KSy!w z2NGR35iclAdVgL(|$PvR(j+b!Qs?)8k6ev|dMNVl; z;bK(&#JhOkgx>_%6Ux+6tDpDJs#J*Qo~8<$+4#A5SYKhzS3+L5Lq1_o4;DtRnmZ-M zTjDX*-bH!%W2TJG)m+J~@=7hY+wn6J3Gfh1o62;&#=u!5{2%`3>+;Vf-X49>I6KI* z3+MjnX5m-HE-o6INL6a(bemE_g$P#hDcp)y_0zA$j-O6_$69Wx9zn2#h@BtM?Q;x` zLTbI%4*K7)G{?4Yz6IFcl*y7-$ZyL{IeO8I>We!ItnD;6j=0sM3g)< z_nJb@i;NClLbb9LO4C5d`GY!7SW|cKJv?+eecw(W-%_dy&lOvF1e-lygXb2V7y*G#}_Qan(;>feVU(AamVTm{v5Bk>L zYw%d(kUj0`6B|t?rRvpp42e8g)5QZ%RcSzftg-Ii+G0oaW~cr?8i%$&rJ4fpapUw| zxX?=?2pwlv9!U3oI0!*R;S`QbR^;684(82Gmp6f|n(=(7Z@aC9E zKN7w*l4zTR8LF6oT~Yb{J5RebHnS&@D#aRT1&^@`CiO5}=sE#e?gMD@b*Y#cg*dVT z^6E|IA8}Y3=IY~am+>pnBf=;JZ+yyX3-;M9yI(`Q)|a*C;%GH7e0e)LKd3U%gxH|2 zu3}Tuiha|Ug|)$&FN@2@-Dj&GQ$5;lV!EZEL|GvBz=7Q5{m!a{so`oaV}azyv~TH= zrfsyUnCoY0Q>>n$O9fhu%{{cQ2lJe`>^qs1y<@Fzy(#jJocHrAt)f|vV-cLOqv&x* zw{)Eswj3cv&pWuPmPS6tgM3cTy;k}s0=H5sDXr#jDrK=>WAXG2HzhY}#lF`%nlyBU z4U3eKhuOsm9M^EUxkGO%9b8P|SKG?Ef+z~lPOoXg=bOHo+I0nN6pizMkN1b5H>O}0@^|8Gr$w;EM*-sfxzIxfH|2QvInTp_`iQ;Y3Im3t#m-5a`8q?2 zbYtxR7PxMAa`ukE-qJvbgLBzA-4qLl16r}=w1(#GbO!xYEkLQ-BeuwH!~zt(IVMIN z)t&J^$~}5Zv6r#^86wm(_~Z1SV~t-33+b7=5}%Fm#2?H7O3H*DWqC(4rG3zboFJ&kMOB1o5B&asHIhK0Y@J^%7!$^wTG2)o)ZGZP!cN)q@?X5UDQ+{GwIf&M)H~D?p`coZSaFuU4?ZPP0q;1~Jg|t`^Mu?dU zG$;Ag8mx2e?$qI>Ia5)L?$z7uDi_(Uxf#ObE(kE>)#+t$<%idr-$#$`=^iaIwKNJO z?r(lG?)ETd9J1N&luj7$9`;0pvh^)9zC(>*cOkJ_A8Tr zEQS8Bi(^tR`_xq(s2n{P9;lxxzo(B{i@4(dQE7xa;m~wpgJa{UArTI zK=RkAL8n<0D1?Ug)>5MlQ4>^er>|8X?#a=YxDfALmpA3xj9#DzxgfVE6lips@ICa1 z_v$e_af$c`8IltrLL!bVo=T^RT?sOYxLcSRp{(TRQeW=Z8cG#xO#TRB2z~X^S(u{d zT)W+zco%o@Fri3;1;F{2FsTeJ3R*NaSsk=1Sn2O2mv`eEuomN+G8zs>4fo4k@7VOb z!yd-{#_as{>wmmZy)mc*jm^^90?Bq|=Y}7(lI^9NdurARf$N3AD0~g*2(LQOcX70>yfv_-;hS+UUzm$;uz6 z>HRu-u$ng50{@!4>@mcR%?8PlgQIBs#1ZqS3-``X^BIR9N`%IrxicDO#_6RXl0|1- z*AcwsZURZ#L^4YG8uap~^Qn@_ZkW$BQHyKU)Cu;OJ4P$Z?uFHxe-+IXX6{qeCve)F zM^js0e8F6J-XrjFL_i|L9Zq{}N>He|bYSXi@4`l$8%}%afH$G@+g#MR5dm*?K@Ho| zRRirNShmb=knnGA1*q|Vu3-5W765F>y|AK#ykHtKOsn0(UU8Y$fZFoJYY19tIESQO zKU!b0S$L`7cAh3PBvZ#h2+2-0KMbE~yxEhR<5cOphG*zmA!yQCPM@=_QtcnpgCd62 z7~Z>9Lc{lLiAEn0aX%>WqO!UtxTv;1c2`_#AAtI}FQ=|Fgj_?jx}Nxfra!XJZ+lUsdDMob_+dA!_m4;YJs zkSy%KXxUpWqq_hg7zBxG_XLtws|D07H~-?T9Et5%E;=9?&ccawp4OcwaTNN_^m=i3ld09jGXR`5_ZmV7LogSgjGG5 zS*YJp(Ob9u03R|}Y2v)T zW&YBY-;SN=2FmC1hU=wxyDSIUS{iG+JGpedMu<8gZZC{Abj0+E3pqS3n4+6kN-ue{ z8(`DDJQ&I3QKtUXQVYP6Jjb^=>IG{Jik16SBX<#X0l5&x<8}asX+!s88zfu5z1kFhjuabaKEU zX)M5D$0OFEg;ZW$%t}yL*ZCp-Y+VHEvdqw3%j+=EU@RK@m3tp!(F+pwheZNx!i~Bk zX}|yx> z6uL6eZ+kYcfQpN9>BNqX!_fy;gQbL@d`e=Cn6e4rFwQ3fbL-Ukk`Mz}nYonu_A`a% zGM79B80?398j8P_gu?cy>XL$Dea~ApqkNnKD;Y^O1<2f59&+nfi8dG@C`pi-K0bC} z5?h?;?C#qccak~uzI)>3(Jbd~))#+bvB9l`SEEl?NqI^Rw6`*qLo;> zxDMp+7Yo;)vnW|3A~JO(_5oiM1`wfDg6wc)c}N1(%98hTKC|&Ci}`5d6ME+T&>y-{ zt$sh#0HusEj&aNs1e_a*7|BV28+Z91(P%bW>z$pqPAzK(uWWG0Sz-uwpJkKWJ9`OMi09P*v=`3^~}FHdxSA zwNG#d7B~*aCJ+5F_g8L_0O0%3y#CRcg-5&Qi_{cf@C?D7O${eU`;&Ql>* zwj0HXAqYKhhiid(^-V^yf=}p@v;O?~#)8VvAmC`kes2kHt;kncjTNzFRF9tM>)A~I z9J47xy*Co&p|!HAdVK44(ygm4?>7p8x~kk^X`L0)997*Xf30E0^^UDa;-L!8>&oyj zm?`QI-#6oheDfX+V}yB`VzyW7nV8IjzOdd3s!vjTcf|u5#1lKFXfXUzkU_}6vY5_t zK<%A$MlluFqc(rmC8EbJA4IA;r?)&|urJ?I_5m(qsj5IL>hbD z(b;G0QKL_`oX8L|lr!t9frLN5=j%^P66G7Ooynnjw(6<1j0A!?uC7Quw{3f>nOlzC zGu?=-=NqPy-7y%?4L^%)ydCNZ#xhvA$? z0EdL=M@=U8m37!l93iiM4o~)M(c)0V`o7UsHW^$=+i!EJrioeRciX(nSXq>;jL>}< z-ZSNucW~okryY1QTke#1adIs)CZ$n-?PCaasq5;Y!@XL)19=(nmeR_AaG~K&PSCAu z+kJ(5*w(Au{51fnC?DX5`s8olEP4G=ExilBK>mZusSCeFo?Q87m2K+J4u$wnGvQ&1 zNrUyFUti6n0IGv;y&eO#ih_Q~kfYXB>`D8N{w);x?E@`_>Ibc1a@nn_?7|k&3aH}< zJ#RPU;YahR`zW(A!Mqp14_SZ;CQD%zad1f{i=JYhcYH8^l8%0t|6{{gZuJ+0^!1xJ zyje$m9=bhshtEp^88tC4%1|5UHRTG$s1NIfm9NW=t$!t!@Iz-tWoI;DOT+QbYRV$) z1t}^iBFUCThz;GctHl<0f=X+D`WTg@Dtoxn%aR#!ehlWAhVlipW$q(P!QZK5WAES;6gBJAe<-`R|E!?I+zT_fJL5 z-20c3llFL-u_r);mhHoHFHc^%ia+yro(oOk-N%{C?)m%%Ngqs8uKa2G$oNaKocdTw zyUtCSLi9H$X^Q=oSrxt&p6#>gr73)y#lBR18fODTo3@OwOUU{_jiLY}DnhL`d1>S8 zAyE;J{;OW)?!@}J8mct|zph6)$7?TcLeDT{Z=aUm-s#CU-PAO%B9nU9I)BC@P;T{mlYmMzX@L96kH0|C;c7CA+=-=v|v4OL`KD z9G0w4niNm48d@-x?1hc9yPg?v5_y2)g3ajJeO(_RkelxiM1br1W&7jWRC);|<|fHX zWmAWlxHewShA$WK}ulmAt@NF@6>yUdETUZzE->(sY_U#b%Wdne7Ss zO&|QDNs_e4#p*5pL`>a5K(MQx?9I%hJuGf-QbfRzC6?Kfxvlo1s@rj76=ZZ5G22wYC#Yb}r;olc^3wU7}7*k|bclPU)R zZd{S1wo^*)r02Dn_}T5aXDOxu{f}bGh??A)bW0K=`YGN0gvtkX25-9)ktb=#Suk`j z*2I6%jhq&q|v=1X32Pqkkx%+zvLR$2MLAK%mq3jQ4VI+`70 zSlmiPw-E4E@pr$qqk^;}op+<{?P(z}0_d_p8M3F#hJ5^po-uDOpcsH4)5{tmMe&AQ z9xy&HI!Xl2$yn>}XLY%`Oa(B;9nmUKedpJ^-g5qdPSUbfza=cQ4N_PnikCn%)O^!l zaS0=I``|(|cljDWjptx=+#e{*aZ*-&Q?%>XRki6y%$BT_?2NybJR;(+55`DhAEQG& z6O)Atmw(D(=0g=cvOenPk6$D$Bl-5@m+J(!=?H~Hlsjp-+sKNkMhdFCYzB5J0$E}< zc;UdC%oB_6;LuMNCoW$6ZF?kwf1di1MPHoIgexCj?N-N;4oKzZc$Jy#X4CPz0ztK_ zQ7dl7(5r8~j-?!~PYd_U5-O#bpV2$^;`v#JO0YeqZZ4q>fJ?e_LfdCea;xL*mz7J^ zp5=A!3v ztOgDbRB+6%KKdU^>)?IzXCvSvuHCvsrJ$|px0H_v}QAYzb$$Z4WV`*auB$`xasb!goK4#JhVq z?0%Qc-hes)19lu9e8w#pOQzIEMz%MO4;sIP9ht}`djeI1c)7!MGD`$z3n(x7-lm{o?Op2miTE;9Fj_|VkX3Hnu?G5YDXs{M*87CE#eN^|-}vMI(Y5|XX>8Ta zC-@qAv_o(CCrE=ARV?w&haUxvf9E%f5{=Qh zLa%4Ot>S*XdT)Fq_QScNc7JB~K_(q7cN0DJ%}MuQF!Z))$otO)-xw`B=t&{E2uR72ruu&Rcq>pucyT_?W_qDeuNph)dF(9|3 zh7Ai8-v@~YZ$8b;KVyN3lu-7OPX&i5F$-k&89P2A;EXsZWwp^X3SEfYQ zK^*x$XCB&Z3owaflgAisAp<-xZPuSRe17>2dOw^D-+Dp4v+{>F!q1`#|GzkU@3^MA zW`7h!;E}4J^kN0+ASHA}0Tl=+NbkJ_2)&aiNRcX1rK(8pE!5Bn9Yi3Z_Z}ehPVx)S zbKY~_bMHC#bMM`MguqTVd#^QXX4cGnzrz^7Z?lzE$>_Oo(4Vn?dyNVbB6l>A3YpRW zs+FNW+sJtNr7}eWwPv$u!?tuotecrS!>EL~t(!aCOcI^^@BOVo?o4#*?z?H1 zfB!}7$2OeW^h#khK52KRPxI_bRP$7@Cftv7`r&Ndr4?1C%k7itGSbjYxlfO-N>B04 zD=O!3pWpPk549pk{<~`?Kn1Zf-sRcXm#aeSoDz75l;3G;*H2A8G&`=|0lE~ub#?(lJZ=W9pGCii8sKwH;O0&d+2WU{aN{=rN%QGp3 z*l&$#({9at^0`^<@#uhzEb-hi4Bc@u{fNSMRq>5e=KPp2s;*gTOAw^e8&VM-Kr5#02?uGtkk|~JZ}c;9;#4ja;^%BPPl}Uq*E;yp)r<+5=3u? z*t_ak2F|kRc99)J$+B{p6+g$8>58f71zl2(B*Wcs-sGsvdd?`XZc=giL7t%lpK{_{ zKF%}`cm1aZcwazH1&g*Bmh?n&@S6LL}@kEJPbBy(}`&u`WOTJ)y`JDo{_Got;ZDs(eF&Vch7hE zRIJ0RQ9ol^EtHuUQ)6aQo>I8j~{`Rm~u9pXL48lfSC!YmL(NnuKuX7=kPEP_*gW7e zpbcE>vEtBl&MQzm+jj4Pw?Ld1f+h7h!IFpa3l(R)x{Z-5JlbXT_vMx1VD2+;xhqeQ zn$lPym{Z8tSTxq8WHL~z5;73y6D(afF!i5IMjEf4^!B8}0~;p{YMTrO|F9qEo-c_x zCj3{034V*Fpi4OJtrY;DFMSf0kjspaI5frA2Si%V}< z)Zn$V8q58SqzVK5Yx@G_{?h(6-#QeIgim0)XSZ}{rAm9ST}&fChHgt9GFCj{8ObwJ zKd(l=X?C0y{72JWFZruLd=MHzfI5S!3`DR+?0!7|N8bN=WnR2FW?D>aL4i;J{UI5% zg1^pJxlMEI-A6KPqTa?N*T{U+2rg&Lfc&!Swa(GEO7d}R^moB$1%r0RPF=4(B`GZ< zf^mJ7*$Tr_YB9Z2aSGmx^oYTBJQt-YTWh1UZ<)ipJy*jT>4{KN!*=5{8BzJ6c2tiG zS)%a9)n5=o%SUoq_foEUn;>7N2;@~KUDCSQS{PEL2mk#Z|F7>g8pO>yX9SBji9fdQ zmH_6+H<@Vp*MdW?ob$_jcJ1rG7Zg*%(x)qyLbc-T48R7lldW8LbctZ*+OBn*wRpx( zLhVvxMZJl0!G30r504gR1#hQqfm}0=)`AEAdhsV1op`!^f~`e@+{QVfF-VTNhJ~Ha zvJ0Yr?I|@Z217;)*;C{1gE#j#Xdh{Pc;xs$5VZW~=*LdBZ;io9Ma6qszzp))8Wbpw zTtAf#RR+itDL&|-c0# z#j1hq>*<+D9QfPWj+Ol7ce2xi+CVX-J`6~=>Psvy4_*DIlHSVmkS}={fN~dBfc+@I zD1MoI-gVsq{67xMHA`DmiBWF|^Fb5wI>XKFC=SL7%Aat^xF}5`Wg>YJAol1(heM=r)g)mV za~=Ujnf;OSB&>&nZRjJyZC10c|5T&3cn!Vh#BBQp^Gi)(Sr={)h)^@V?LJ9)&y@0lSrXX+Rj;QDK>p^^7zjZ{bm?F!UiD-t}l{@ zz9NkxyuQd=)CKkRxewPTJm9$Ne}F#$161lvL6D{`;$~OIaZC=B*$CyVAKEDDMqdn2 z|1Ut~p3=(#o@t8 z$|^Xcl|$CIgyNzppuf0>azbo^n5v?i{Wn#?K-$qC)$-5BVosUl&Nsm|u151^Oo9sN zv2((uZdjwlt=IjX9VZ2@1Y+8Fr+aMkUX{~KqAo8R-UD#U@=BXQTebM*L340PIq80(?X)^<8J1^a)K|8gPO4j z4WuB6YOSNirOxNN=SSHvF}fRSk7vN5 z?_UqNvdB>|g(wvMb@SDYvM)@>l!enuL^Wpj43`8fi;pTAIXt8|>cMD7fQB22dg?q% zR3WfD`^#zFWVEC5z4?Sf?Jut%{}s;WcU1-PE2P4n50I^$q3@O$Y#yO*ni2f!xQ0Ne zt2JsBc#Hdr1V8or0j^dS&czWHEQa{zLeo{O3`?P!@M_@WdGx)LYEz05O7127w#l0O zv5+909=jZg@*5(;i+f0Wv z6}}9mDl%$-{Xyc@_>=!HYW&BmroXkggRIm!UH^J2sGdkm8fx;Ul+zHw>MXFF}F zlQmR@4>}A!fSdjd3mXMqBa*Zva`EsgJi$tiDzmKrDM^i(({ye8NpNs5-b$R1AmYZ% z9ILpC-{hNsu72mWo-SxJ-#R|W#P#KL20OkzLQ!LsurmiQDmb1XnFDNGuDm$#RFGSQ z4J7Ciyk7eNm_E+AB5H6QBhwcFr&FM`^#O4GlBoAjsScX&-dp9kxcv#rN~=wFTtFW> z=AC6g*>#@+M{=e7U9;?8wE&`aoMcFS!^VOhC)bzXiSXCK7yWx2!|Mahof$3rR z@;g>u){k&$sg~bGalCA~t>ARkop;1NA=#RGzuq1%1VL?PQTose#OcBW_s`so2L>i0 zIh$GxBo-`19xjos)uyy^W@%zyU`C)BAk&BNa98AVX^!Fna*Pz3H3s1sI5;;nth$Si z32$9Y9_=nprFkuufOw#xBXK5t_1Al?Gk`eNFn2TdEhp-@tqnr0L832Y`rj1hzx@)s zxnahNzjfiuj)J`x)u-}CEw>6LXtZZ3AxyL+nid>P;-bUZU!`ufmC(gev@sdtVvcxj z8Z@TBdf?}T^OltJmZ$X40*e-oL;}SGN$VM4A>Q!1j=375rkviEqt3xa)yD3~zB6qh zYMReCJ3IU098atb4AC4QPSS;W({5JY=sB&c_-JuD5G62T}rvd9WG%EZDbu- zZ!>2{@e+pAqV=u!j1B*f2>q1hn-2^lmf-tAjZV)(Hi;oY;jnjfp`T3dj1S>)b4L|D ztQ?QpqH$e?%jj3WS3dHl;^PJMs>gxFYLgJY&-)Vz$8q{DUhTboecdJ(DsTHynf1Woi0$$(VTwen`uywhT29`2Kdt^}i-#LfPU2 z`Vxiu!OeEP%C7#~D!Ud8d`y&pi6a<1$?jopaMRik-}pZ+`W|HYta&#GI27!L_+t5pkS; zs5(0N+8sbMO35+V{UVrH1%CCd%-rR-Ue^b7J;chYR9K9$qZ8wG^ltk5P|th`FjL*N zsk5`%%v4H}#5iw?0|np$T`Tq1dGSv&o7;p1n!8Yy2Ty-JaP*^C?ACncviid)ubId| z-t7MmJZ&FGf7*hhth) zX~RgNOcyj_Yw2>!Vu#(Z;Ea? zR!9w7w6wDLT?%d07|@ze!Orjl`ac}iFQmiP>ml``VW&*ApA>=5cF9ZVUy4#8zZT&E z#NE!PBdKhck=iscWJHy(yag$$z6YUzs=-2xB23I6lATT_{E?xemw8RSrg};ubA9q)!B? z@p1K1S@Ewk&pe+Sgv+ia#?tSPPrG(I$j3ke*2l+HE)n%RN?Ds3_baov1pJTZfzqc) z%N&2Hq=ZfZ1}2IK26(^V7$U} zv)#~l))ujLSEtF-=ge*gdP;*mXlI}*i0XRzKUqcvOP)@+a=lRF{rt{Fg`W)>W!z;Z zg~*VxfS{I=Tii$I=wwr-R(IMrB}zOKBn$6DN15u3O~(tdpg2PPzr<+soj??itu4|s z804Nd)ZyJx{8mgYD+H+dqR(s>rDXhSO)s1*DJN3L9Y)JYkB_;_rN+Y*@CwM0T>kkK zkS(>W9xSM#fW&(Y)^YmPj4jp1E0!;Bul=n&)Vb!OBq9znPct4q>y~xCtCQyUmr+`_ z|5=-ykNM(5i0^{A8h9)=20WFiG*u@W%r4V;aM1g}LcPR)?UB<|^WL$HpPP>G(GmUG zP`oQN@By8dGY^f&a;s1^`VPkJ7Tfq;Uoh4x>wyWlfS%#Ft&l@vNCBxbp>o^&i04Y5+369Z5~5VW0Yy{k zV=8$%B8C$?`E&H-?!DqHvmlOP<6l}hAV&BuJzsHEv7j@W*t6U$YPqWQjagiEOi)JXwTW`uz_%GGx~RO4b>tqKorQTd9S)s^;A#!p$xm)^-Ix^nACg z36OxHWVdSOZij3ElKJBVtmaqP%OHN32D&_>E-3jZVu_x;#YzAh8X@Imy|S>+?z3Cb zjBkh#F=8pGBaOR}6|?o+{>L1d_JC2?XK?#5KCY{rro`fQG|Q4;G=K}@(cW8JXH*p^ zw$J&oks(vN+cwK0k;mw``9!z+aVAF2q(x=us-r4ls&e6+s85s~nu!;lqdgW7Egz0&+p?kUzH}ex`7H_ImQf%c16_Xu!c6 zhY=FgGsY-!+tFD=cMU(^n&@|B-o)%pyOcP8i+jXlGY`MTD%M~pwrWhI&OHVmj_@sB zUF7aTN_O(&^-bMmM;Iv?y||w7KzIddA*F2h@0Jf88R9+hKv)&&0fngEHo6w7%p&hccIMIkL{V)nR5&X_|(QzAg*D|7qNNh}L~W2Nd! z-Ad=M$?z&V^xAaYr0Eav;my3O8+NkTI86VzJ(HkA$_>HSyi|^hw)X9LpW%Zw;D>wM zo)Yl0<>GzXaYHRgNo2bJa+%Jh-gS1IT3p~yh?b^j3j`EA>3Lbx!tZ`bHro&r+RW7| zSuDOVOMixrozU{%W6aeWViWx>iJzZOBOizcXF@?2+HN%OBxAssJZ=J(Tuf)z-f@7; z`d6zmWOfn7Gg6QFJTv%4l{0^C)JSQ{-zv?LzJ?g}zP!Y!ZaD>8RcL%}<*FO1gymtkeWw*Ta=FQZnTE$eeJA|p z010eqH}2dSA;;<5kwC8d&6CIOc%n;qrF^yue4Fc=X8G5j^tn6)yrN)Xxe>Ll8K3#; zc5y-4mc_&;x?pn(mOr0qA;Mq!Ot4>;2EVnYRitdp86Pat+SB$z<)O9cX4~)Q3!+c-IQy; z@=2vON1RtEAI_g_rtl)M!>G5xD`sIPo1gL+{=on`5~E50NQ#k7 zmahx;t}zjIFtyIsvXD_T)oq?imW8LCu|vAkQb~txQty4NF3Rwht7#U>BrE;Fn~AR) zC{vkR87$nlWs?Ywtd>heV|PK4r<_}8o2%3*_KUCn2ANGZGabP}g(VDzf=66VP^?tA zT}O+Xlj-Pe6ika0#%j<#jgxI3DQ)b_og1{#gGlJ{NeD^p2ITFrcV^^hn zOY9XOn`aC8oIWc-Z~Bv)(?p*n7UdLgOoQ%|viR^e%kJ2QxI5L7%MIp!h(W;HmFX7) z2G?TR3(4^HG~FCLCWtxpvt)pFb^z&e;LHwez59^z_=lT3iCEaEUqfXwAAKA#kYKpgd!zig!tYjh;CZhm6_~Y zDTnMWl^B-RH%Y90$uS7mozp+@Ke_ezn1_Eo&McK3TQld)>Onc$_`wGz(c_sHa>P;79dDdHUSO*V@~P=uk3I-o#b1{oz! zWU#1eqSQHU=Wjv~km6WqY=FcHek@lHP&|LBv%P88h&`-|x7(8~X7n&(AQ;>XxbIie z7)w5D7=2(ym@exRW>T#zGgaB_-x9TE)Hfn=D}~*KI_ab^V8NupiHSN|GHw{dXBKdH z*ISWI4tFSuyF%%zu?R~9>Jw=;45C|12m$>}-+^jh;<^K<5$iXqd;ag#A@ zf4C!!gJ>XgAu)CY2r#=h(Aj)`_mH$XZpmq zPyuZMUHe`nG-n3itO_k^mkNv*!oW)zJS_ZN5uP@?yF2c1FtujP*+uHvYB$voqAI^wamG!A#3;cI@<^y}A`uYb%ptwdkL zcpTg|E3!K`=3v1A6zvTg!)vx3N%1RLv8$GEQ8!!Bqb=^fUjX`VBz)3TH!p01t*%|S z$>KB&2L5FaQ}XLfHrH*i8xI=Dme^Y~w1!~m1mKKFVn_ee*O0MIEn{7wRKQ$v>(Ld- zTZ#5>rr1w_WNm99V6H;gBSX#j(qgEl zkK~#U#B1e&|Nf<&I|b6^!22pi#fKx8CHLyDoq)p|zDStq$~oQ-9Hp(>tMqrUCZ&R( z`j#;H+=d%;={A@?E1mOVK551Y)0Rj?$$6YbUPL?4WvGCya3Fk*=FW|brcLTdlPb0m z`=?2>t}-^P6`ZW8;_;Ui$(cEjHmOp03-jQyf26tuF^_gdiT^wFBcphs2^cZ=0=1eRl!`yVCcd6jO!7TKC?<3L)mm@SDj>hZBW>ay+!|a{7_< z!7-{|Pg~VGBKnZcUnDpEggJV;SpJ^D?K`o2_t0YzBPXBZl0_4mn{>bDw)_(ub>LAv zTVB?)HO};OJWO`Fo-@ZM7MK}vj;Sxnaxti!Ur1#GF*B;n_$|cV%X$|}^oDeubXw9= zE|k~229M*0O}!)t4<^`nk!yWqw@N@pfWNK-Ag9wQQZoBN&izmu6N6l+C%)lWYWQ?{ zhA|r8ts~R*yv-N&iQ{Wzb%I8Y7+)Dvh<|!~OHmXraMC?4^0q;${yo5x9EZO0&px`j z7!v&^7tp@W?-F2AZ-BC2rJ zd(}Rk&;1H^?*@K17OP*pNNNl%CiF8B{)l?TuG;sS;J8CmV15%#zpwHV$C5kzAkEib z%Gh5rsSe!KdIF#@#T+_VKMdU~g}$uwz_(m{9c{;!!CqIGSlNrms?ER>PClgU8_GiW zteQMYh4zc^c?HHS;FNa92UjmVm6PLCsqLoMMADmu0df&P-l5xJNPOLj`}n z-pT14zTEy?n2g6fG^IN8B}tb9z?U#i7aCsgV=qG)etJM9J-v*lT>F$1^XxcPlIbk1 zj@#7Q*|;vJk}Q@`J#y==agqCE6y)Ve?m<4OTc;nn_f8^b?P=Lu8US!u2Thr8Hv{pqqG;aX=VKF4n;)6(-PBT%3JJzp-g|jobZJ9-WGb-P+dSsr? zzaS?Ux$yn)t>L7JF*(a944 zs~Z)yY7FFoWRRW7Wl|DbKyvH}y!VmK2_7&1;9*5XxBXaPKt15+yPxr$a>X2LNd;h# zz1T0JfW^d4cHa3=d@Nxs64C(3X+3{vjoT&XQTB3f{|9Mp{}Bk!nY=wx^u*8e*_WrL z3+6ND*FZOB7~i1WCZ4&&VB~?d9N$q@n-w2*XU>;&h`Xcr*JAhV=qOoj0?!@NkJ_m8D3_BK zedhcR4L;%F%GQVwC(fF?It2tQltO;3CST2F5ATqDt1|E7BDA5s`6bA{O)JKB zx0fM~MpuoR`qc^k&hVk#iJODQsQvX!O+5Im=-8-7tqIgZ_(=VGdu0rsIzhS=>PG8_ zNlj5w?e__CnM<-rM_$@5FNl2JDX2|0r*HY9)hruA)&xgCR;xXD)f;xuzvXp$K1kGE zq%$N3=J`>UcPyipJ^Y2)dvmo^d@)4*+iB9AD+Y^kR=jlKZ(5Mio(kCtn2DSA^sb!r zqSKX4$jwYvjTIGHn``M<}<(;dA9q24!bM4WMk6K7NDUyY%qzNbiSOq z94m6+OFpjx>C6a)4_E0eIo8i@x8DXKIHm{@?z$_D8${0(E>TvL18iEL+X-GTSf z{)p|^ndXkHw+#cn?*-G>iEn<*tO=Kpeh%cp$ka&f@qSNZs_RJI%Oo~nk08Iq0S${E zDqq@Pky8?R&{XD1juc#oras*^iqQMv_v`QN*sqfDWl+JoUY&wEDL)7?;MAXy zr_pdxGL$lDKdWWtH*?n5915v+93j?nZYQhZIFqel$3<0hSfx~(ozhdBj%Z-h-6G0& z%!?eWI|)s93kYf)XX+-;kifV4^$%%usfdQmMghE`4p+Wit>U@;)m(RG0fBLnay>!htHKLWcGHa* z$frVWLG%&otehpyvrB0I_h`#^589j5Qc+zN&l$0o5^CuLejpn8skAGj>s$1 z<*65|u3X(G58B7P^Q-&qF?xsaMZVeQD}oe~R3=~XF7~k?O{y~)TGXJ`)|~Nt1(CoH zkRy*h-$M=N+LcRbAE8YDhLFxeLnbfBE+I}&>l3pJVaRj0LD_j$V?8EF5UNO#jwN6UzLU9mOC{pW7{uf`KNY@OYcxJ z+nAQ!y_aZ_Zfz*N;J_xy9ppnDY4Ll^=k8sf6BRLsw9oCn?%W*JGui<;!jrq9xQxNE znZS!^+RMv9dKSOEyRwEFJYZ+MEKFE+T%0VV1z6OQ+Z;@H>{IgUdHpS{=#H#=R`A>Q zZ$ATyT9}KwnMZ3VcS>PB*==45$a09SxE>A}D2iucA;*NYBJZEuJKhe88YNMq<34Wd znmzv6IwiQisomc;NoXJ{uGoow%7aJCC}}4gsGv&Q>Q{PXUV#pBLY%T>giSTO1|BC7 zTBOAjlmhrFj8d64C~r>fAvhw5Lc4}bmmIPd9I`*)t;;VuH%UR$QZWbD5&<_8rL@uX zS3BwLZMVSBtPUX*1BYu`m)&Uar2?^#WCp&T^^eAPj*K@s&_FF%6NPQ-og||np^>iL z1lEof6lGTS$HgNnWAS0jFW=s5-$nN`Qp@(!3#%ZM0Erka zI#ph^%IIS8`QM%_xZEsf<=Mp|A)lhL(hdCdJf6|M4h(Dq+ekv2{0H9nAPCG-l zWBiEqXl{|0BMv8I$h)5B%A}5rE`NRPeWHa}@=Yn*qJZrSr$1eWs;hQ7Zr~kfO%m4O z;MQigwnryPE{MDhRim1$3w)+bL#IQ+^ga7=Si|MvA61Uxx!)BYM}Kddw59WunMo8M zFtI;*HdNSx?o{V76mVdQ%2KL{)i6hXsOFEpRpS&%n}44r#3svZ{Qirr?WtCMR0P|U z<+NxW5xDO4`dCSh^Y&vVvDtKQCGzpZ_1EFmAe}$;T3y_0#fGw6*_mc(07>K7brN~& zt`8u%V5QKox3l2e;oUMhvRLK5gw;E2!YWnVZnbIjEuN3EzWEwnJ4E(RawYgu!GjWp zBt%LXs->hD^VOfX8uyO)C}e*7eNpK=DLq)7CJXbh8V|e5PlDyxO~xZgTC&T&6C`ZSR3*00P3fH=7Zol@Z@M-hr0eB8soez2KL9f86 znCnFR@DC~6r7Z*ftjj}O@)0k6qfx;t5B$F6bqb#xjzITp_w-U zvFiNpe+w#eK!m)Mj4RE=#%7nig!5wfd%rHarbBzwOnKx+cJw)>_ioV!o*bpPAeJ6^ zAIJ4w`u(dGV5^QPK0b5TGvolgB7x`4m64WvS8~^wqzC@276BncBE2^$ zSMdDf%d3$1A`c3)i@@^3b9_IrTxREDxmg7Ia~yK*5Df~V_Z6#!*p7d=6{C3jzGs;@ z;@78wI13%e0aK%a>oIerd(`xeSbZtrm0;tLT=Ll!&8+Vg57u|Sbu=q&V+j$bNm$O- z&LI1^a6e?T8p=xqT<>X?RcY$gRBR+=%=y9p0&paKH z!__Y-R<-A`6<^2rZxXSA;(${O{RM)f;1MLXwT^bPq6!nk({gn85XvJetb6roO5-QH zm8L;6sD5YB;habvaeoh2*G{HwfeH&=~jC(Sv%I?WxM{IYLK#Kq}U#JuwYBN|`vuqwH+=q7QlGQdV@i z=;wrO%iI>p2C5Lj0=0Ph+;e|z-GuGg)Qe<7O|FO^gZa<*@e9D? zE!yl#JfAWivj0e6U|25~ze8v5A!`|ytilHem<=CJzVWJ>iRS{VQgm*JG4ES+{v;z2D8#lSB;S_Gxj9aN0{aVfBT=b zOV~T#Bem1Kw#!p{F#t@DeD2}$cTIi*L$cMzPNU|Aw2Nk4AU5~pphG9C7PPJ%`Od@P z7LO}FNV7FixXHj{s5HFl?`5aLrH3i~lAw6_P9?`m-M7m5)FdPOr$az>b5+%fRlLCm zaYk+|&%+9zA|M1rk9D)ri?2+4HkIgo8fAKJkJbNMp*?I!LI1@Drm_%gv`s+0XRh%b zmLx0wVTa0bkCex*$^@z7ZH1@A6zGs{6 zuhPwZ|4H@O@s;XSH7GgGMo1>*Ph|vAoo{0yKJ6p6B4W0j$1n0D%_}3d{o$1+o~L{2 z%`YX*x7z@HMX~dQSafh;yL&IYkJfUHfbf`sQ|3`hvuMJT{XG+|pexjga%GuzL zbMqR2yuVm(Iu{oDGgoy9eJP_eNPK0c#|DC)ee%_t7zNi#9WfoYd=~v)Z@@rKhWcIf z2DIpc;kek}zp=m1!Exc_=q`f}g~GYv#+}AprI%<@*J5B{EeleGstajA-Q4TqzL9r- zkvY=3Oon-jlSZE^T7KME#tc6U_^M(d-!$pK0H@5sUyV4yojxfBJW68;s`lJpU5#-# zlRF~b`p^Q`8s%eaCc82RLHr6lkf?hz`Rs}2nS-(r-OHc=DpSlPgJczt&l)xTUP~km z9=URMu~g$`jgaM)ImI)KUx?6~NW`mW$RtcA8bzPXBz-($x3L?3$N|*8?^56Q6oWjyy{uh#TP9X(xC06>-WdWd?u0_SL znBFk*997@_+vGr})I; z{U#O5OhlFTrnycG$mu z_U;nIhA&NfsHNHTN~6@yOIfy)Yf$U3*EOh>5l77AGG3Ntx9}kq$7W$-6i??+UgYn` zOPg3{%H;OD=ha97GF|zJ?rEEq;c?py8Z}NeIF4{|lcl|fZ4geKsd7S*)c7}^)kYJx z7q$I1=S(P4I!7X!&th}wWEZ;`<$o_R@B99NLro4&s&x;5t&VcZGm!&br1hjCDP)fx z@;99>4xArMRZ`uTs;zLR)nZA_GjBRugJ0Sd6UTLax1h=bRte`wgt9{kC@JHI{1fPN z6W-4%m=l75r-`mDc5pe;!;+n55PqV1e_LY)DK_4o;bL+WNuBDm1dPlR8*jOt7Kx;- zVWneGO$99*^`ttPlgaB#_n4@5x+E?n$2}r^z<*Y?!tq%={4r7IFd;e?BC=j51#N%{ z>(%zB*D54jcglJ^0F%Sz@oZJF7+>a5FnO(nt4zHWNH$|~{!<;W!RqzxWS^G<1vB{) z@!sMdMSuI*GzQwunGFt}Jr7Ii2Vz)`B)ZS|E3!_!&%pzaH&u8*b-vLLPUI=l$4`xQK z0wSP4WFVEEz6+gOg1e#5Q~ z1A&DmtbprS6VRpXZohZn+>Bs`R>^~=sc(ipu2cG6YFd&@g#4H7QblEqhmE^tI}+uN z`&(6=@1RTNJWZ>o(90H1K;}^TMPru<381Jd>TBb-eqF<4X(E#b(_*Nyac{*p&C|&v z(%+VUJWt^3f4rHa0_|GM(4|)0egGl6g@ZJ?#ycl+zO=bpvyWYmL0rcBqPVjYVQHZs zw*U}t`cQ>}T_>aK6i1T!nUsy(+kO{%Y)Bl{x?0@2O|>^$X(Z%RX>aT3RBBMDNP#P} zsORNFngce=)3cFvufcC=u3H}u(c|N#^^ROUslBPx(;b;?DQcfZJ0vp)J(@QXkKc2@ zY|!Li8kLe;+)%9aSzat$KiQWPFV2NFa%=Byq$lm3lq#2V#L42k_(_o};NY;=MmFo- z`wRZq(2&c+iHAAZs>IABowv;|nWLrinTe((-}9z*jsXO|->=tyn8}ITXQjXL0;~Bf zy3bCW7#M%kSJkc=Omp*LKS%H+yAD|*ii`3gf0rePZT)574P1%v*ly3lROkM_p%#g7 zOeyc$p|oQO3f$1FTV(GWwz!V5JRU=)Lr3kL9td3dkkPaH6THMqr%_kr9+YmZxJz0K z@XKXC@EqoKs^yG1oOUnrf@TExtJfn4;yRu9KH`IXtbRDaIfsEllk?gqt8#sywB7%4+#kI8kf(L)$E0> zs(2lQQz`unw>9JA|9)%%yEjz#X8gg23X;1DZ|}UFejAP?E*#_LHm#n_)JNGH6+()6 z^c{;YGz{*c>>aBE!;5)J^1eTG3ahwz8%RKCb<6C{YQ`M9mz0-vAn(VU`;8{m{nK@Q z5;pf$yQL4Reh5~^=i-Dy!zG#0!@@);f}7Yy$4J1~6_{!s`ca(8v*4XRpYc<93@$PP=e)!B%)^4d3_OR|N z0l11^%)|fO_l=FStHYngH0f)vslsY+-Mz#47=B4 zuQQl!qnX^Ou}(EZBwbO9Zp7UNa)Bxw2SBkEgX7s4=NT@PFoa8F zX642XZs}u{8vM0GtE^7s^8N|cYRX=w^V9~^G!wA1JP+GZV{C$Kxl=WX*=hrO{M(x$ zQpr%o6Zl}-Ub8@LK(o?>UrEi+*|q&$xF)0PxrOT0E}q65eFyv74{+`|7mm=1_$FoX zEHjDUJR7_xnQnY>P>NoYJ0Q}`Xo$ecx{=dYO++^}Y$?I?eoi?I8#<4R)zokOZiG2j=ySapyu>UKv>!t<;3DYtA3{E zEeqYCmi9XT+AlDpo=5R-`_LRV3`L8Uihz9=1==f7)&4j zc{Yl}JG>eV`nX2wc4dk&&E`dR%*G=ezOrD6o8n>hFmrd-+hQQG#bgWc&)CO16i*2O=3X9VO;0AUUC<^YA%n}I-Sy3}fuyBg6jMyMzc zw@q1vt7HZ$IXl9yqM|~Cl_MHq?L3&;5j6AMRYa4>Tf$|*QsL~;aL?F>GN3rFf5xwe zk)p|McB}RpM$nzuQ6-gTL2cW^GbGSyZrgYw7(FRwV*9MP^8=5Mld1u~|%J$c`VG0ak@HZy~M0AbEYj~$e}$uX}Y)4 z#DA#j#Kc1X&^C^SB;8%K#?bFZ0Q$fj4-jGO>wkq+DeVehuL@wU_p()mqrJ_zbcCqkTdG=e**nG@%T$#w;7YK-F!}#PG&sO zVR5}3=W9R5rj`t)uFbw$s7rM(JNjZZ3tBo;9EuswF_D7JO=c}lDf*vlJt?#o|9PI} zvSldZ6c?>wxn10cvFkhJM7Va-TG&m)?#(oaC+qri41a6*Wx3Yoe5#Zxg8N*;nJ* z`d;?ToqLYAs6))YRr`s|c)pi_WX<%=%ql~?Y*;f|Y32%gtk&=rAU+kb~($@Z>>7{-2WwoyNAZFx~?(1rqSop@YzY(45leqwi&oRyCiR=a8wqs4q z0iKvHvDC$rk73>$vy|Gga8zB_j)I&z(gTsE@7?Eq#hp^vSj|% z>+!Tk*WW3u5cyI$WDF7r6FHZ`1CKOt8yL`?J8#^#yg{?uaNnb!`2JVbj_bdFfTU4* z@3J&bc(}P2rzS9zys9T>tFX3uN7zJ#fu~#D9h5uRdFSd7@@7l);_}^7z$TgJ%i6QR z<})y-!F1C?3L>7BTMf^g`P;n-qyS==8Kgf426hhf0iw5MdFTLVsR~(fW$t%(JxFP_ zm>aU*UXEpDW%P2NsJ)tpEc2Hc?^dZAnH-&P;RNs#I zsYA$c@wDF?u(MO65AYS|cJsS=@%l`;LkG>Z&&O^J!EyHnqiJ)&*?v*Cn8VtqkgWNB zkcb9zgypN0xH7lHWc)4tug9p|yAqMHedc?eDblf8ah#9Qy;S2Vf{`ikF}NCyWVF-R zXm+Y$d$Q^7Szwi@$61a6IP1*vRpP;R0^~8-E1OI?KmHvHL|sCFK=c6Tk???Y%UNlVZ26hUwAs8Hz8LGuT_mfN~n#wgfF7i)a z2Ea^%1Pg)DYJnZ^@0YaLdTcwj}O3y^eNIsz7dzJ=_m3BRtV z`TO`kw7qv!Q`^=)tRkRDQ9)WLDpl!1=tV?8q=_g<2SHjAdaoi?X$sQ2AVqrb9Rf%R zHKBwWAoLEQgz$xP?m73K_xIl4H@-iGAv+^kd#>5meC7kz;VoLf`sZm-k$mw_ zK%H{35uZXcGhVdKP$TP+hnddNJmEg-_$$DM2dMaB(G^|AiFTs2d*CB_ZHnbiDs9*5?TO56kuo zwN?1$HFH=~CN;Fo-FoFOn#jRHG{wI-z%pRW^uzRF>Dh>3G7BXywy0KzlELq35Q_!CuYiS8e_mwMBk~8xE z_eTJdRuLI#WQmYWg-O=0_1PbD0aw(BZAMbcg)5sogJex9gWRSS=DZYZx<19x>rmCI zdVHK#MDCvL#)E0Q33pQF97ng-^^ydA{K?v?p^nSUf!_-qKlpdLY6<9uJI&fx5KVxr zK3{9FX%-mR#Hw}<#kx_=OMYsxcR1njYk_#-1zE*e~oEC#1nnnFNrw8U)55? zJFCl^5$^yKT|!n4`i0?m@GyP{^g)8N1E@}>tfuIHaF!m9|BksBsBgprEWgLa4Da7)_mmU<-H`%8vO!$Y;0%>X^5=-=kjQ5BY$KWK4xIpq?uL|nX9|1O;JDr zZKs7Zl0k~0rb?E^l_L=fep61O z6YtxyN|}j%wu2_KdPL|nsa_vxqK?|COhk6TS7h?f5Rn$~l6+8F$@S>Z{_U$*oGLn_ zY}9!9*(HsrjMa#fK-_}VcfM7=#)l3Fx!d2wwfiDuq`oqWEK-fdywO6y-GqVt%_cCT z=g-%oCr__;2H~v2{*o3;GWx%nM}-bf6UJHz{ZmgqY2ch1LO6l>(@%-)dE>qcT2uFJV z9_nHsuCA$M0U^knUxQVYF3l5M(n;al zZ~ZI+Q${Ok0n4HohiX^v(od9}i^QASMHury29e2?Uo|93ZT%N107_0;2F<<9H?&d?NM#w=(%Bk6E)?~ir*+$W6Dp2xfc z=qyEg`A+6>-NoR$vyJ)&MKDS%duRP)`C0(} zv3yheNxs(cZIUY0+qzU2R4T2&12&s9LT&9}S-3Cd@F21(*>u_*=W%GOw!g)2>%@wo z6ZgR83aN&mOYR&dsZ z^@Z+qok7i=u6lQD4seiubcTMhTmY(fh8V)@aM^Yp0=#41-S6zO^en6ux>?g|^a}p@ z3w;#%Y!)+Ofldzk=`%sW*K?X=dtI;;WuO<24{~pP3$V$YB6!;c`(DM#=`;kJmSvK1 zL19DJLeYh$Lu08exP=+y++aqYhpl1|Kp3hvu*D} z-6_gKMrr=FFz^ZuJU~Jw?88VC=suz`UxnNDniqN?7VfR(7@iRP;Nb?t;K)`C-Tjdjvz30+c zv&Z{!7A1xN7l4Z-!IURp_0yr!xjPOqwic*Kiy2mKke;V(N(RPta!DmtuByNch#gjT zj2w2z3&*Ko=?0ZwSD97k&ObBnPkguf?jso4$(3%kt_DW9+LAMQaLa601Lc7!_XU$m zDb6E{wF>(&Tuh8dVyPze)kBf&|Eumb3tf0l6eVgoYym2TFML42p|bN>TV_{O?$#Yp z)K;r%B*$pfovM-T_Ex=jSxX5IXf)1t^tM0PPseu|qmn&UQv)F*YN z6dfigDop1$)j{fhtqt12@)^pEbc}Q&m<9?gO3Pi|@@LC>sm*Tqg4i88Wp9hK`eMOl zW?z&o$4tBL7Sn(WkevoJwC7sma=eNZX(XYq{BYLPxH|mA?Zj{pQa@>XQ8_EPwZ&C? zc5>6}xW|e5&1p}5XIrX%4T7&4d&SP%1BVDSf;z?}x5!hdn;E7KZUFeCJG+yLOd|!i z7Fz)k8H%WIvG}nDhnXT$Pb@K3GP3DpkCUlxGxFeMOjXirs(5u;5~en$d5jsm=xUBF z!q21phDX02L%An_MA&Ze|B%~1UN}@T!MW&jfC0pBGGCN@mMblCN{5G|?kc`5ESDl_ zX2+vKo76xykFyhnR@h}HS2QA7Yd|OmV}HQcerY4|9~&;~btbd-S3vDVMy@zva(at2 zj+-nTDa}gyZS1{^h9h@_yheW1(&Om>w_b9G`@+O!Q%t+0D)VK)hCE^mnUar7s4AYWRrf;jnkP9{+%|SkeWzBKGKHM zJkET;?SXrpp9_I`T1ZZtbv@MexM=7sYeQ0BTh@_%@ooLt>KVD~nTPpR{ws7qxnR;ffF$X4Fsan1CXTHx+ccw=@1Dhr8PSIG4XJ=~+loY;H1&+OPt}{Pq!Xqr!M;~j z?sQIL76%PIOE5D8v?Ulru*5w0H0|thzVK1yy5Hr**Z&~*wBNJkUB((wWNX`dfPIgf zMQRs9=8@+*Y~^V+pQhBM<7GA*ORYbKt~j2e!kT^Vdrty?yC0P0^Ucpklg~F?3|MT% zgKANY50H|%%cVk-+a$QN<5!6`Swmk!z@=XjM=l08X(dZo@VpEeo@jQVU%K)WqwZne zYl2KZ^Te@B*paUpT^a5XY07-TwTW~%lAKoj^t9X}1RbvQew5nvt!7-fTnjXwH6WQjQyQp(zt5~+O-`dJ z_Tf)%1vVb{hm0)ja9jzTvcpz3qnhFr_^mphGr4b24m83+e1rs+EwkQJu;f4F4l8Pm@h<@?|u2Q*W84unn~j-VjS=dlKzeC z0~>nm-YS~%tPU6QiRAU%P>)MwvKfvxGID>6X*%Fw*Y@pAvQ_!%@v8Z>JQnYl-YD*k zKpq}kCAGe8ysK^T?gPn+Ogfh$woV2uEf(9Zp4eA0wxtnNM7-H1-waafXLd9>$=+4L z{a_aTJGXRcW}E1@`@~>jOA&GsuS+}xmSzjHoiDC3xQ!Nz;fmWuSFmyK=9;$0K`?c- zrjS|8XP-LXr>9-Qpu>0{G~Zw`03J;uNCFz#Yg5U%%rFRgfJu z=Hnxs^C0p{l2J=c9*JV4RV#wD3(uKxuTmQ%VVj-Xt7OXyZT-LIfA;iol&}eR^qyrm zRaYi9jV_wyR7rZCQ4WZRhM0U6N6J|3gg+cn8W%ew?WwCNY@eg!Bfpc=rF4vB^_ySp zgIn>ttbfcDeC~&@Ww`V0^yg`>ul->oDsQLGar7RIo$)%M*AA?{25nT#Z$If3OH*Nz zWI#R_XMu}|Cc>l#=9y1wvK&uIC}(Wql0C-+4sutGl(0_>8&0SVx%aKA&{q1G^(LWf zJH76kV?A$lI5&J~vE@tuq>sweGC$@R)`I?ZCx(EN^TF7nvI(|`&jGK z1R0Y%(#E}pi_lxk!%%lI?ZJ~*yiEuEFWd0-{CpSvWSGXT_fy}cIrMv0J(p}r4TX1Q zZQM3AA6v;@MDwD*PwS4tuUkhJ8lNgh?hI=3?HzFlCREpafkNtsJ=4H=- z%T=xW#rtR(lQ3(!;u*3MgjA@H-fBCZZ3yq;f z*i^$s>H)9E_uBj?edjK`bh+h&ka^+hRoxrW`8>)rd_8Bas`xacpBDFgjOWZUE)LC) zD`$=uw7r+#r~sC!k#Utiru4z}`n&D4KRIgN43?A;E%Q3-;9~H_wCy-6P5yEZ-Lv`6 zkl|au>;nm-W3DIe14>0JHx6BT+ zI@`P5-+gnc&t?TP-)n{&J+}_N44-HknehsF?dgN-{bjNsn}a>>JX%3Fd(EQOs8Wp< zA(Ea`q1R+CA^_#!+}2kpkEvY@*z*I-*x+7drX8yydEQsuk% zko;4FTD`5^!kmY@f0V;u=SZ_@;< z9PSxgR;@D~47j?l;D%YL87p|+Rz4z-zghGm$SyY&=yTk;yMmL(hh6txnMNtWa%iw{$i z${(LophKH7y_RWI+*a+k+%e2vm)52TRSS80Z>&{BvcfV(=6++|oBm{If%TQhD2RCR zye1hQ8RLDjZ@$wNS|)6+C5T$Wh%J2?_%4m~Zwxw0pJJqZ)W3gX$JI--iwmfI1Bt@h zu78ggRSKIPWtwOxmVf=$GWYb?NVr-vD1lvODcR8_N6B2g8n@+O$bD-juk4`QQ|#IiKR<6y-Mx_*sVd0;h-eSkCr$hk zO>GQdb4syi44;Y(igA#nY=PRntLG_ej2UWlRy(6_-P>xtC^ATIKSPRkxAb>4b&* z(H{>D>`BOx+f!K#s@Bn|Lh9J|z@Yg@eNy55p>vtO}CieF3D;w$%al8+2UNW{d{uz41+dceuKM_p!;v{?_t@ecH~FcADUP=Qn+i z?kb^QiS6;BK0VA(UbW`f=@z`Jw@-15r%w5#>~1sgxDQSshE5e|5UKqx=4dW(7+vkY zbQcQpNEdWg!v>5_c+#DTTMr2Li}7?+E+=$h%CC;){s6vhTv+9 zGIgaKhiroFU*ueSQl5%hrO+0Se778aLSb9@k)43t)J`IX^z*2cH_z>f7ke$5qy*~;vFx8OB5=Hab zhgMSfdQ6=LmGA@yNfXhOAUvSIes$js8pTL<~t-l?FqasEu=!#wXoKR=aI0`rE(uOg_eY z+^=D8dKaFZ=l(~8xuX2iL?Vyati@+wTa-6C%L zx6K4kQNrs~z`4L%cxL~DcCoDR{Y2Y&FY41POq=3h#)j90kI^X{sfz@@u0d%f%m#pa zgH7#lsw;1C&zkh&(WnXGry~%|Vmc(#^Q{o`l#pBDWEt@psdRjbZx;Jl#W|fXz57*4 zisnG|E^O*-1Tx%WU_0+S%#lU;8tai}s z#bcIWS2iD#dK<-Azq6A5(lh&+-tyzFN*1y8kILgcI?-eazTR%QO)SFA=NTJZ$aKd! zaz8FwoOLz^JeJBUs?D(=8 zcwtz8+tabBo9Ehd^#ITxGX0iU+)k%9!6(ACo)(|KT-nfhoXu@)o?X<1FT(uyNQyAY zm-c@2sHEW3>#mX67{w&Mr-Z##5R1olAFsr{HZ0PoO#w1l+SNon_^>?Qw(0cK@HXOz zrCmM?H;B0QZ88UAimyO`YQ8gWGuJgOF~I@JClw$y>>EwMk7S>!QXg>j(E|~6ttKKb z0GrE!Z1vLdbNw^IHdkHrtTOcse`$(}=d@B>YZeA~I48Op$lexN-`s@14+|!?|2Qt* zY9V6A&_6V18b(vK=aH9fv`|WH(5-X|Cwl-uV_S7k=Syj$rPfC6Wp9Wk7_cWgy78`W zB*c&gI8Y69ArkNge zX_rl2SOKjV@_TGI6ncnm?~^l1Pzs^c2S3Z=YlvUC?V}{tYr2A4rJyuU{_ks2<+Qh(-AT4nEWK6!xv3J}v{`|x;HOb?S#GzW3G{O~k zIDdkn;aeb{{bcpBD*`B`NJv#}QyXDn*xFT%i{DUBSIup2udstN{iFJr%IHvI1Nq>0f!x%Yf}0^V_G0 zErUlb7BkgL1=lT+5u5cQ?`KAzJbvPMk}XN#Jv9VLT5ef5m=7mk{6#~)XuVH-1#EuP z=p5tXx2!jkl3y^LX4HepA{h88b$#TCU_-eDi{)YFxoYlOQ$x+D}`IFL-VK0VO(&vFe!NV1SWN6#f8OmR(lbEMMJ91x5?NygGoM zTdEG0K%)qzeww#)&XURVXE}I2O4x1hIb9Qzt0jpOg3GTyTz&FgmFH(0E+95Aa9**} zY-fFmqXPIor+ga~i#bB~2{7BC9&rfd?Eq&CtSuc|Dka@kw}kT7A1r@Mz!BMcrCc3J z_6}xJ3#PyOJKS|T6sL-VZv0+VIW4&6L1VF5>a$-=0c%ENaIuAxrtx0*X*0RS_YlC+ z)qBYx)>YhYtFP5+S6O05;u+PNz0pP z4c-q;rNfThy&$eM8mhl4^TPYQ_;R`q^j0l_$c=Z zr#0*+zMFpFbf)@1@6O?^ZHE;d<|ju}iMS_%PExzCplR`EAx5~H#IDS}>!&-H!PQ^m zTmRP#_g-pR?q04~(?+Ib;4;CMSdEzAmU!4SUvf*?67`PdOc^0lX#0EC7NY?K<;-H{ zu$Gq?=o(M`X3qmfrj`h~qWM|_Plp9{9J6}N2?$>xHOhP`S*?FcRsabPktt97HRREZ z)AzBC=_(CVo-4xRA|X}gUEpYb5E2JSoe*S~OzK}NQ9b%H)3K?Trx!L-qs-t{`K~~9 zW{)vk_{MBv7UTFccG8Ydo$v$d zBCVcvWp9K(QEAL8OcjXH8T6TmVpwjr6CkK=_Q#zuwxl;=jH_|=<%m@8)ky~f4;!9d_L+{|X7_;A ze6mf7#suGs)%%l0yLulV>Q-&{)wz%&a*ZV->JM*5go?Z=w;V?4`z-&&?uYu?&)>Nv zP%P7*H-$cs;$XqEN~=prf6uN2vfud@#ID(z#KN&)yENpK|K3H$QtwC{e8sof5!jXX z`I1Lo+vX9!|!>lo0%l~-VxvNwTi*l69H>lTmDtIKm zPLA`i+#{g(-4(@o^hc}c6{k(mlH9t*|CBx2?-TFAOernQ&1t%prgK^9Ny3~rG%#=g zwwIq{k7+fa+ns(=wd!)U++z0XQb?K=mRPtD4I z{9!TK-_Qal*%`}apO2Cq5NT-gc_GDl8diyB?pr1@E~^gQP61j?lU=K_SrnZRtl3V5 zRon2{QO$)<2IF^kRPH7msyOMFG+RWu@qUbChV_Q?b7)uWzKh1eV}$N2>j<%c?h2K zT(!9VqV2nwsoSzYh)y(D;L2E9`0~W+*sHVSp_t)4MP`avUznBKrY}KDpE!{=X4?}$kp2;X!0I)ahP~abtbMx#ew078g z$kUwYiOR7^->sC+}84v+GPUbAJIKsx#oNsS+{7sVsK%`lfy? zYhR+Ya2?5YKP2l$Vt`@cKFG;w^u~rsA#(>L`~f9VL_051avoJ8Ad;&6gez%M4enCS zI8JtsXKQ^n5JA9UGUrCvez+s)ZyW90E6r;y5&;7cXJ)>$9dAj-c;i;*9O}>_w+p|q z{d!e(tVVI!XyC>9o2T=2RH@ejy@LcQFc6iK4ZT$6b7^0O3TD;Z_rtkp&cdKio5B1} zPq&)CQaf!t%ei*^W75Ls#LLTLS-3aK1b_CV^{UfqMTGxUfR^eB06lxEbonQmWlCBMz~}$-M!=Fw_p7JM|Dr2W}4P)rPqzmIoX5DerqH9-Z(+ zO1aZ{R$_Mt`4jkR(KXTTZt%KuvzB!?28^_)K>e8hV$$o9etz8ST(A4#>Q8Qu^S9Ev z-q(po5eg9eUT**IPV8BmE1mQre}uTXc0{d{I3@;hnEtnZ!Jp6z*Bet=P$a+D(^+IP zP^0b9M7yG6Ldi`!B$QOTi*ONE>nZemItSCwysAFryXei&m(NX~)h6s4%56`kKLTj9s-^qZl%5vz`jP!F;xh zTTMkBjD?lcr#g~{0%9Vdcf#4kL1n_!rgpjknNrct1LWJ!#&b8Gf1S3kF%4&Omhf|| z_nSro6Mn{3#^J@Hn>xdoID!ry36Qx6*}I5%k0m>^f7<#yl}<3)nq*==*JQ)+yJx)B zbSR_5J${!e7?v-mtegCYshVL~RGwxNJAoUIXQ`YwWYpk@330J3KBGg@d6wGSBY&~D zg^*c}9Vs&2M%Y@|O;z6bWb{+QqUtc8V_X2}zGYwEyk*3_eH zTOjAEbZ@p4%*e-;*R`oWq|__5&(w=pO$ueN0L{`z{xpm2v%o!mdes=eE}^_9epZe==4bCc zY}RFKeReK`-M_}`oL|)Zkl||<{#_I@1`$6K=%BKiMpS9cQ|JE8wXBD$4+6g z%8ARTneW}RQ7qmh$?%}oRMswDT0I{P z)t5P;i6>Mg=R@t|s34`Vv@;onMvMiKFjK#ykwvfz$w^l4Sa%(fJNIZ6jN&+Z%? z1dFa?{TdEeN=K_V98A)rR%Z`au%>-FFv=N6NULm~E3`07d){b0NLnWqf<#JhuMO)tT0hh3_Z!>X^d*oeae9X1wHLZ|En^ zk3gjx99g`Ys*i8vcNeiYNjsmYPEj=9s&9}2mTRFwWoI)Rx@J4gd>^2$B;udJyqBh) zW$)EixA<8Gd( zldFO`lOf^#B<+a}-w^k)0KzYsJ7u3Edr~Wvrh91$@wX^xd*Av~z7D=2DmqFZ$hf9j z$)N|>iZ|>W9koNp*sf^|ij%N#VetTlhkCrlQyQdGY z(UQ`kVTc%`8Fv~Eu;xb-&gzRzh%^)K_D`5$HyviHP0(WdRWXUSYLXnS&kKMd?V%Lq zc5{rjT0^j0wQl=0i(frdR8a%THr-eef3ysC<|b;W!U~1lmVC@^f419Yzuxh|jnN0% z50h-UDFxrv5#AhM9~T@4$w6y>Mg4BW-#5AYZc8*24i^B~_&WRM=~aZA953g?hqa_r zTh)vy=6&YR+~E|aw-W7lDm@*|N+0YWiZqC+%DDa6No_2sx?S*W13D;IZ4tbuSDuMqlfl0#xXI zwTa?LKJ?X(jN?H^(GOh~wa&j^&(v&HBZszc@{X6&QuLPfu$)XU!Ab{3sBAD?12T2( zkqy_72U=?QzSn%-e%s(XQtB6gYNm+?KF;Gub29dLda<3*DQR>eNNou!Ww^Z7n21g` z?L>is9k#zafxjrYRQ{Q%4fh|w4hDgLov*U#GgoW3REDq$( zQ=I`*W3+nR>v$#i^w@(OyJ>cWJG_a9rTA@3lryTfa|{(FcXh!oQu6tl{VBM3+%`qA z2c{EMsleBvAz&QobTEbaMuPnJh_v=8W^b5C=&whXnte<%Q>kf(Rxf4E>C|!aa_4jS zo}+({tO5P7GqqW8KFxsHZDahaKve9N5uJ zBR3_`Y5G3vXRI;`dn*nHDGiQR#7*=VBBK~cCyn42E8Q|K|48vL9OIYV)N^&-hGn+c zv8@;K*YPRgJWrb^XyHHiuAZB0iA1cL>j9ujjXMI#XVOZyMW+1#@)r0aT_C&j(FRl( zHj&8Jk`!P(UE?r#u--L4mjx2NF`_VpSR5B^VKC^?qO6ICeY@dRc83xl9^~ya3 zmI#T@`%YMTQlH1&$&}8*iww3Z6%j)u@|mzH`(#0K8G2c#)KSgC8<&nEI8RcXQ6Sly z&(}YWChiFVe>lc?MMLVH+@nWA6aLCLk2|)cC%2e+yrT1oG0Wd@^@E*By^BgCI&VG* zsJbp!`!;^@)+<6XCmvD9K4{cFv!97vZ_ z=5chmgjh{sy=G7`vqXx2@p-_njaz0-^G3~#ea%143@rwZXK9d4Mw^E>Xbz?0g11wC ze;r{qT?@w8?HNYy1kcnDRi9}I73uaN>7q{>obGUWhay%FCewTkWG)hzm5m0s0fx0gRRyH;tESx}nAhs`U z!w7Gh3B)%+684QP+x^*4Wu#6-w$@{HR-5(`{htW61NZX3Jdexc;WwB_Wa^6xMUjCC zZ67ZdMP`E*0*ujb7z|74Pimb1?s$kG*>f*2EESET>ann2H8U?9_e-ImS7SD&CB9~y zPrbJqU2WeZFCti_FXMhU&-*`iu0%+BNV?eztCh+N>v<*-3k0bn1xbwTWK;gCPDMhq zx{{Q@8*(0elxYIL3(SpLpEowL->9OuU@~+YiNu6HtFXB;5tN|^;FFDC4TpVy{-wP< z@R5N?K~hJ2Gz;=D?5G+p+Pbh3zaz@wyivtp-`@sbRZ%O?Yn)zQT+|ZUsswTW;gcW} zT!I}puJX7qo&0=98jfLtYJfBZC*QZkNQz|h(4?GMDERIY{A6yDfAsND`WU&QLr+Sz zV{234IwJqk{}-&=n(CSLRf9+zpxBkUJFTcGp=%~t=>(19ypWt|7qXUvT_qM=)aDq@ z;Y7X*-7oG%H>daBj}Y^cyl~$)UG_5i-68TafmR)vse_PBwwnkK6U~!3xt=@7M2JTMFegYT}$|r5dh7v?gPH5e^fj5}JB!!w(-Wl&Sc>=MI(>h=oG* zh8jVRlhq&<)Y@2IQtekhbV0WGw!O4%swZbzo+$zLd-fgJl>0nO6`RQKrKO0`e2n(pRiEuCPsvqrVp9)}#J?ASSk zZz!0E5P@&#+Mnk}ARsIelg{mlhS4MwK|@9yPRUL;6!%q%lKOhObfXz4MJ_z@$Y+pO zDx4qoDS3&x7TLs$N?ZY>e9U%Gr3(E`9b8m}{`K!ygO=TXCbJvQn(yrDZ1A+c{r?4( z##vcu<$Qv*h}95wCegI;>23RB-H;8zLkO8&CQ1c)gj+{J>Oo)J1rrYYC6|3MjG?g~ zIIYM0Y$T2{w_PBdr@NGR-M9NctGMTuC+Sl!y~-Eu%R zC@QissB@ij{l|&&?eV#N@BkifK#-Q2(sQG1w3KyI(}d&|;PALv#~h>B;b{^USM-Vpa1;46hjCfoa2eRD;*_Hja*0$e{uSIBndB4hn93gp`C(`8 zLA1(4Bok&~ao<^LUE2LHzg`V*8MAQw{VT}r9H%X91c6meV#SnSBk^|2jI;f2ofqzw z?(1RCD{PI#qph7F&8s}(M_IOAsRxDY8UN{#FD>=)4UaFxE zxhqYEsyFdLI6iC8C>g6(+b%ftH)@Z?<0o&;bz!h?NXD)(`M51@2%CT)$Su(HjKMkw zDs;+875N^VEcTJvXyg{`DKZ(DFp+Li~(U_YkG|uJ#xRto1<=@%gHNJB| z#0P#nutumBK5dKwvG;dxF>p79Yl+8fb#`^di%N$%!>7Y({;$A_^ZBdxA=E#fT94WR zh*VXn$jHeb-2i+j_iun+H!%1YXF16NaO2+_*U2(choQIEiHTRBW@M75U>t0rWvL1DS3wI=LK( z3Wf9Bkn-Gh9?6H456~4@QR$MClSqW|>?U@A77OYseMI@X$9LRJe^82FB6a^5c(`uo z-&Oa6l`EBa0=dgETBxeCQf`7slmg5hP11IoD}(ThE4-E{X>HxFi5kpVC@ZH=a4u2y zH+W9;3Im~SAy924?oG`Y*)O8A>ynfTTB>C{(;`XNHT@-g7_7-6cKMeT7joeg(M7U= zVw$bw0QZzT@(;|`iP1nJ8Oi!>VuY}Uo2cZZ>oSdE9GS_}35vF6`&?oD2e+Wt{S4zI zFr3K@;UYE<$s;4H^ge;;D4lN;%TAL9ed3P~v%l8Ee)B^;7ft13Pj+kJ2%5nOzBNWI zf=gekn@C400uVIQQuFIjvdK<__ZUsapxcn(!ymdlTY|=Og&qzDU8D>bP7(H{dMomT zeb^uU2bQjaC>?kO|C`ffgtCCNvZ{Dk;Q;-p3Vu@ljbr*J`tI_IkKv_6NqbTRr#i18 zgY=eU#-@d>*{2?Ot5GS7N7ccfUIgh!2Q?A>8!06$j0fj533GluY@4&bOQpK-L*qV> z2e8G{w)7t2xrj+wW z=w!Eawo)|88Up@9#gp|EMC*;5f9sTK%KSt6{(2I6$EA&v_KA~!CcvA`UB z&PXC4RpPloytaog*FrMC7dT3Q(i*y2Fm&zrdL{TXe!0Vwqk)3ve2DM~jrO-%TJXc$&$9;Zm7~-t%(}?L zYNz0aI_|lu=`5#EQic6sw{0cXI9=;D21-%k1^n<74 zL7o2=#Q*JrOCiNWHvbLK`}p@oAA`z?7$sZ^qSwVgRG4%X3%Jcw11@L+jQ#t-qbq<7 z6A0CDu>WRmwuI-+$pF-Tt$+?pjJ-~)#MZBrVbXz65tyGn_?aok zp-3Y{M9iuP+4?g$l<;= zqyyv^lLZ&o0--vtre#H0_b=Dye;Y5nQS!1ga~I_VKW+!Q39#GbkkNZ*vfvqR=_&{m z4QkY`2zw2N_FAfrGH)Os_H9DFJCrnR8RUiSkH>GVhfr9SChk}3%9o2$uDeiMzz9Vo zl4knJCYH5!gU<9kXbKm8W$#;pe*7vj>rfIYoBF|U-R=BM%Xo_3?I;(%)dZ(_ky*iL z2@wt~!(JgCnO)A2wB7XIzU$@dqriXlBCvnu0D2$)>K7uz*v|F0s%OK1P;1Jp@ z$s2oVTm8;rlCA~qX{%)292IppmRre|^3KFC6%CE1mR8k3SIqbCSrJ@3Jca!xe-tRc zAQ=81eE~8kJpbU!)^T;|sEogZ7(L|whwaOnd4h**3T(6dvjM==KN8Y z6go|`+|eQEW|4?vz&X6i{D3X$X%o!`1ShKwLqTop*FSW!!yZjPwX2hu(D{DMY03?~ zZsD5Rz)zcO!{`!}jonDE!amIA_)0NozpNrGH-AD7rfVD08g^{$C2XH%Z zqU!lwiuCN;cBzikwC#7o1gka1 znP7aV9j+^Bx&WVF5fD*H-eS_?`YY4g9gB*sWBPb0WZmX3i+}!Sl^jmS)0K%<-o3^i zdp2Oh`{G5-;*A`Al1~r2e=Y>N-n;jzRQKl$T(1Hr+4}2k{#)hBhmW;*svdKWKVI;2 z%lH`bk<;P#ou^MD7`~dK&(8$}Jp))-Z{LqXk35`6F`ad{m{wVkJ_~u#kLr;3L^XY( zAWZ7`Ipm-x^U~T>FFs(!_Wf6cg2)kOna>4MKp`p+Z=K0gt@N?f@D-d^E>^P*qFU|v zN_1D_?%P2d5DNat7N|LZ`1zz<3F=_DXFi}Z`HU7ob`ew(P%7%fI;r|%Beqg=o%jbT zuI_p{Ael0$1j0=M4ofp)hZ8X{laj-4Qs6^l;+4y_82w;XoVu7f2JZy8+5U^|!}b;*CJ~E8;kh2)2Y9C&JH*oZsD6GL6;a zpdRJ{Dwa-!dIu7MxZxiA7XAXzs0PCw#4K-s`TU1@eM&cNdt5<_c*V3=i@Bsa|ucfr>{eFb{h$sMw087+>%*(_QBzv5- za)jDEIqK#!c+nxcY}6!a<)exa!$wN`IKAQc_?)f?J+ew7RsPbmylO0wFYOslbFt4P zNL}R_k!8IgP+tWdV4o~`)fM?aoo^uGrmEG zr7B`3A^Viok!U6*dyK%dv;q7Dgk92_nb@fj@-uP68)y)PxoBcBR$^TF}*hhK0Jh`OASFp3r-noZb zpT?i&-9Xz?#~^!|iU3QfZduS`jTqUa`?=P9K-8>pgemAb#WWG7>l(6@?^9`~e2xF< ze1O!YT)cQ=cF&fAx$PdT|3f~&^#aW-u=+E{{j@E|&3p7VITG;bHx@=Kw&6L1c8fWepGLYu;JSt*1Rait9@*4>=^X*{~Ks`Xza!R9_H(1Pz}QM?K8e z_oekWnh4N?4oA)cV7GkFDTDQQZkS$p+(}u7@05P$o}0yBziC(Fr!|I^ydL8=u&R+Z zXcM9Tzb?rv_M5~RhW>Fn&SA4~5Jaeto|~f1j1lD)-Y^tWOmm(8`h(fw2XD8-r-rEY zLVmt2q+ygk|JaXonxij^3Z+!EZ0-F`AHpgpOHBnoY^%LV2Y(!((+fWM`G&wQPvE=x zW&}p>{@tqx9!C~}1E;-X$31nV#^{%~!eUidY<&`*clbK&zROE^;tdE<^!%7*OGAZNX2ti zzYOy(w%(&_L1^Q7aRk|8x2@pS!H23c6aSFczy9d<;UG0G3=eY3yby}Oz#;3do%ARR zLsJvYF1HLrETn+>cGWJvIB++-nJDC)a`!uK@(2P&`0Vd~;-Uh$ENX|zYcJxl% z!g4`H-niwsICWDM`;CJIeDm1^*TTc)Xs=#obk8T5=nF%- zeYo;?r`5&2UOi77KL2`J0ZD!7VE-VWrfA6@vHavHMRjp&2lPO$zTCrcNh9z31wf>C z8P>D}vxTsiDgJ>||DS81Z4TJ65d8deXrPDd8Dlxz15#mcOYX#D+~_iCSukn@oBMzG zdhf8Nnr?j<1VKfbD7`3BMCrXFf*>HEpmYemcchmHp@=jArS~Ety@nn_3%x_=EkNkK z1xWZs&w0*y&wI}I%|CnZTsv1_X3eZM_pEi_KHHapA1JD~Y40TK*g4-^>ep4ZZ&kKK zEchrjT%o~PSx+7=hdHXiFB>cz?z_h=e`9ohqi#J+rZH-~ZK>1zpyiTUi#seXu0wdq zD}P^rAdT$dqaDF(x_xV_7d=Yc=MTZAQa$1C4GW=K;!!aFfT3$hNGQ0dai4< zwTn8^9nFQa?E?jv-7#?~fnH_aYW?G%GVVlR1QKlODccxO=r4Ua%j!67CDh_adJ5`{ z&>e>=ufsJl12+KazNt@4`Rdxb32uR!xcj+|z8!r5F@)(#8WKa-9-8dC>|z(3;(;mZ z&3-*(X7hewWt_y|6Fgs1042MgSiFKLB;pYJJlAE;=%uFu~OXj z*ONw|&Kl!L5LI5(?ZEW9U%x0EMo#sD%yz4d%u4v!X7KHE0>>Xy?>IRa(!)kYUL-E> zP7eR7TwZ+n4ByHKA7*&lPP+}B=>?rv)i*)-bkE zC|EgcWUL1UptRus+8{#k5b-CNOU_fi;d@%D_^&380l35NCN<`3z z5&Nx|dfQ3zbnBrdx-R{R5Px?EICk9L z+4A(>=n@)_X-p#$k_lM`rz_L~#q=-G5O3oXD*IX+`lH##x+d-EC}@3E1~M=alK=Tr z1Hg~4okYE?6z`X`aLns?z-kD5VJ%)vMYpj&={o_}=G;=P8_Per0OudL>(-wS?io0R zna%DZ7LiDqE=S$gJY*)K=Da`vxG65|P?cvc{PQDhk6vu)p_&Am#RvRbe@$V-xu~}K ze*5)`# zR;BAx5Xa|FyX|y^9Ph~~IvkX#Ja|+(ud|N+Gf)1lX*9P{@`%zhWAO#fFIyElEBE}G zE!cE|m@uq+MGTA4jQH;iw`*oBLsjaU=WQ!BiHfAR)D+vk`DPhC6)hJyk(h3TIMWpy z+~3xMPL{k|d8KhjuQrfm{;^oiwLcrHT)h4M(6WE?<3q53aUah@AbY_}EjjC1+?3jb zSKWu0i^p@WckO51ZMNURWfx7=&3w2Xn`0j&4S=tJ`9NloB1K)NSANZV=5&UX6v05l z8~M&bi z=n-{uZknNx({@3X0h6|=oAMDU23Tr%|5e%w2_~ z!V47-!t6qdw;bOJh|-mO{LF9-NiPy!_M`p?`jTprSD~;6nx1p+2w9%XLJE~ zM5nxO=Qi%}EqWFS`GEE&mO=A^dTwa@l4GKg^(qpY?2dG-Wp5UbVcPsM|dwP3};=CY?~5AW0=C-N$=M8#!uH4&(> zf&9J5hZPrC;YklGw}eOs#WLAl>*Eg2ggOaFh?Lb+fPa1H^8oYAe_ZvyTtDQNhj+<^ zd*HI)Tkvt@tqbTK$0}CTjF^V&IA4EuF0ZeV{VX&U0oB_Ux}*Qhm0^;Sb%eR(EAA4d z;nF#_#1oRApC@}&x{x_PQO-vX^jU-N1NrAJA4k?vepQAEKR?rCd4z{gzWA8afs2}A z+lT;icS_>+U9s&8He<7<`dW;CLdU^hV$3o*J~t*vTKIlxLBP;)y;t|)Cp*JTXIT;= zY2Q@sMb{iVOM01LO}gg67cxAnB_c>SUwHczUptM-W}XPDq1$vTy>%&`PQEN=&Rs>< z$T*O9Ko88E-+vfvJyOg1WKzSRI<51C%HyJ)ESCu}LAncGC;BEDIMep|5MUtP=_b-f z;yXmzgRvyNu4arh&%w`j)CO9gi-97K2iHPadE9o1VZ6I*$JXTbh*Fcb0rgv@-T>friRkt4F}iQ-tH%NMS`7V|cW^W)X;nMt3Hy{`e= z>fWX=wRSE&L}Gx8nZQ=VE+UbIu8v0`NebvX%hlcMvn1~7U&!*^#2?qZcC`CVhxeSs zKSF+cium`Kfn%0o4|q?b*MkBbTzUAv1>RM_AD-<_Fd?=#j^qn*DrV} zg3S028|f~*i=NeNH2gXTjMq zfAq59Y+I$s?aB@9+vjDoN?j_xr$rK-8b2?FNpZ&PHjsK>_1!8iZ2x>^w7eXV+EF@5 z$M`aWM2edCgkW#p;HB+r30L^xrV1jdVx%)+waR2##P4MA1EoD@*SN&@7a3^6_L=W) z7?t(I4G!4hMqAwTD5>!yTa3v5`)F>4=ZonT*vfPa7o+!582>FaPUz|&s1CKGW=l>< zURX`WaAh?%SFy^aGc?+ZzWk%V{qOB8u)Oo-@bhg&A7VD{*6n;Xvk@bTsF)Q`AsRFE zunn2gX>LBofx;pCwDwa|*lKQ+?tO=rKuVh**8Qr=A#Qs?dj&z7W4DM}Rv*@()XQDP z{0^7Zv^@h0g(KYaKFgHJQdJ>_>P37B?3&NkbeP=85JFIM*sWWk8>l;N9SdjzGsJAu z@5vojtXr$pp1w1f4L<0f564DB%E!Wj5evWDW90@PUuEX%)|)d^wA4qm$Gmy_R3X4G z{tzpfr)H+c;3|2#!t^`q^DV5-Vq8LKcCZ*}W+x4)zaqJbk--It0Hb)^>iCD72cC4^ zD4~75=gsE~lE8iKG-nw5+h(LP3Zb{#AdnN*dsIpyvwLTnL3E>08 zIT0tbFAii9g6H@SXdL@)i;%93kY<>on(n?e@Dd>OREzZA+d6~?AMZOZbhE*OlyYsx zjt1X<=`W5<-?0{Ax^|E^{Q_r+_iszTMkFt%4L9*iHBaQxc4-{7<1>1fH|2*m$Tc`O z|A~Shy~(kGy`^QP)7XONB9rIq5tnSiBE?G!u@O@r2EkR|e-dwujOCvwzM9Ip6_5u0 zF_+>=!}4zt!JnR7yh}JxRdHZLCduma;!X}hlXIb*-%S}G!FHI+0Li}A`J_MqSIHr$ z!;UB(Wv@wqEO3}Zz40XpjxWR2l*6iAcBw9(g)JWmm>8;s6jADg#VBvRf2dtg?|YLM z6`@Ax4snr!hSueWQ#d|&H6!6jyMtx#lh0ES=s7{{z7zl9_=ropdPz209lX!}cB#?SIVEH8n;8YR7AuPE;ZjKZldLam5!&zUahZ#a>VhSGS!kBa zZ^%W-=V+&s68oX>$n_DP=(S!Y0Wa&R&VCYLH&UPYG={F{7<`&F*urQ^!yNIG|Fqyv zQUkrz#;26;@$b~cimB!`GcCQL%$7p~puyz)$*CGd*=Dip?R?SwC+K zlH>PSwqlC!gu>DXoy6sxBaU<+e$vO34#ua7q%I@6D)mnN2m>E$g=t)bvv#ODCga7| zqO+=?y9Hyvih=5$R-7&G;vMP7PH}oO?#kKL_sPrSf6l|Jb2viHjZXq=YRCh8kZx-A zwrotr&-YW4v)4ijc+qVPiFIObq7}P@ejmbzj{d^l|8qwXJ5M1@MwEPM-=>}4o-aJJ zP9(eSWIsQ;44{i5g}rJOc0_-i)$ow+T_eCWc=Wi^masUS)Lhd z`?#ps-_ubzwCS>A$h&|~2dYju=MF-*`Mb7VOAAl7`|1)soGEpjo zVDny;7dq#I&X+a7pgnX9;+M3PSd%ZQ55vfh1ezZk^~4O_sF*0k^#%j0eH!|nr-3)! z&E?)lM{zT}^<0s4tIDbj&xUxVrtVL;SZ%s8P}; z`&RIdmX2w~qE1m+_;&8;)8-Lg+Z`vwqSXuQ#2U;(NexTbQk{ZD%NXxZH8z85YICOV zUO*-CRi~h9u5u}=d&k+%Sn#ip znr|7nrlG$o%= zc1NMBSG=&4Y zGZ}pnpA4nTHg8D<0j71Z!hCl~(%-zQadvsqbS~JBVX`;En{~~$PW6PG;h%UPj13u#kcA^WO07t_1c4?)epZ z2eMl3iXE6_ zU%$;1kJ=PyF~79RJV1fPR-FLtiDqTUleNybsb05ti!KhbwLqx(&k|lYQ6=`*8~!ca z;vj@Fm|C#~S$NE2vQzo{qlCEX5HcAY>gL5N<5{SIr45gjGP|Up)(|FNZrMpoh z=W4%I|Ug4l9B8es?*53|^AP%T1 zfl~AM`Iu{QpT<4kc(6H4H`p{mG}on~9H?0aBJpn`J17n>w;`@`;W7@nU4Ck%!$&0z zeAHGrTp^R@!F3{@y94W+zlF#M5-|$Rk1%y;v*6$ka#U=sC}{m0I4tN3bD#P2d6~5J z2lC~}83QFxwXy6nWqb%e=ezO05! z>&p`VLC>%b-+d(wI`3t@0AIcKlpJH)7;?$hZ4$HLU=7~R^vRjwjv(+s-@XD`z z&SL(YXxcg^XOo1r=r*Up0R?$$&&HdAl$l?tSGUh^Fw)Yq_mUL>Fjl1-({aVcgAEJM zQDiQRW;pBlZiTO+ZIwN3sBulyyPGV8ScNtXdts%=@`c?DiWI)zI)ePPwBg2$XW$C- zOARY)j%Jrx>|R&TFz?rH_o@SYL_Yh`MQFZU{-Zm=z4!&ba+u?;aDdSf-Xaet#IT+- zyQyYXds8t&ITE{-Iiqg0ppYr8NIFaYWWD<`y0I+m|A=;&ExxEs5|osy2};ridpHa~ zwllncQ34_0k>3)zd?jd}l0-zJ0j*f#q23Bs7OgblUOqY^Ts9X)a$65K?W|?8UDRf;)JEs9%$=N*^c-TF}BZJfA${~4dH5I4rA?rB*$$Ek$TKcXU z!+i&dmkMm6YfY#{YSAruYA@VKCZfG)i2+{n%h1}&yj2{TXAJmm&F*Fb>tVo>+aQQh zxdPc7Ny=yRB*2UptBLGjItNdXR{vv~S0QA(LyT{S2rUKt2X3fuIx{yD`2)jcUO%1- zaU<}|?T;JHD?Qo$0oCji(Ue4L{zMw}PM<25R5?&)4sy1d{u(=eLsAwV__{H})3GrK zGO!qGb4|zSeTK{ZW~*ll13^Z;=5d}NMkk#OxfR+>uN^#59G2SE)k2mTU!FXwYo7Tr zyQiORh@GeY7zTcElGPR~?Sqf!v#1Vw1(tr2h&!{_*6(4;r}4G_|Iv$b{BSO-2BbPAnhTX zz`bh0fn5(pS3T|nR;_lJypgz6`$R$f0OsiX1WsA_nm(IdBZ>DLF*LZVdMY(9|F1r{e&`$#s-{Y$6`MJn>k>G^6{ zAh8k2v;@Ew2fN#jMaPV-a}t~~_9SK&Bjyj8oPBy{i@&}cH389#*Ei*vh{K2_!wH<4 zy1EAT`OZ!s-EXS?XmDqu5(6H}-*<6Szitz5K&MJ}n{be0A}{ zp@=M0RuXf;vX(-tgox>}C@HMTvA>@%4%3<>#}60*Q#8-GOJT-F`B+yC^kOrP+*w*}}|;D^6j2mb;k z{keUkx`q#Zmorecq}^|d154V-)QK-c_&YR<-1T{~Xsl~5RbD}9vVDsZrc=(%F1+xn zk^`w4YD42Zmv2-De*VhDdg75<3xR?fsBtl@edu%fO|&Z!y_XJZ7G6X;px5PEK`0nj zgt-%sggzaD+JLg($M=Q-@zO~_EwCSrbtN3DOW&wMg-6Z+kdM;<*eM&|D73kC@u)it9v8L_Pu1pAW)x)5+Mg9v0kIf&MP@LXQ-QZPrPkihqg! z0grB0l4G0~UO)BPjAymy`Z1AX%vTn5K?ryRQj$u;G>=h$(dz-x``&CKm{S?QN@uCr z6}CY~K;I60-{N5UT%f8oXza@vk4)mE@2}epY}irHJL9ir;Qu_702pYqvEpAZQ*;?h z_oqf}^jz+^C#^jjK%VRVRaSX(M- zTOJHrH(aZanw{tivMgC@tp7Ga#uz{nO^>7W@ji1RU_eW>FspdO4a$ZFOPO?P7cFMscxF-PIIy@q_vLLp@A9@rk|J_7gRn6=uoz z60oBjvRa6XviIattLiJdxi~*X#n_udJ0ORPB1~&tmxQCI!yp^Cm*Q+PVJLuqC+Rj( z1zY+ad=b{^pu%p+g;J3=@1JMlUw4$NbHpRDPJ5j)V1-U`U!_FJ$R&Lusdp8OA(l2K zC77}s{Sz6#=-b*a`1VjnqNlb3)=4==Z4&;_ac5#fLj(WG;p`enIfT9VZYd|5M2y z-I8uhyP$NsTTGvE@2q|WwZ`TB^T?CLUI+g@V=oh!T^y?Xm3h@cT_muSo7n=N8b$009{{ z?;>(Vktdr?m_w1`3yZr|Kea_^~aUc3A{RWcB_r*Tq8f1g$n z(fkgHO}mb&c=R@@IGWwHhe^@(s@|}B3Z%Z2B8b&gnCYvuo+C_?+{4qL9nW>>YoH$% z4f!6&Jjp%Zdj8_;GY&V2#F#QV)r*E^NrV3hF8qDsh~J#dD-t>+Ztb|$I`Y{@P;*PD z-^XNGhjT(DUwkRdA7n@kkrkb?^BZ$UteP50ToYEt_1?|#khtsU^Jq(W3Y}}fN2-u< zr%=}!#?rl~gK2Pz43Xdt%T*6VE-Ww=#z z)L3P>dZ$L%j3Ug6qHS_P?9F1Ea_Ls)iDOfNg~GWWTP?h8LAh|%*OI7;e?oq72@6B=KJ>RqgC7uZ($v=G?tJfag4U2rXO|kaRhVnnIlB%iFTI*neyZ6x+3=Z)nRqncD597yilA}QE?%fkzL-hl^xW*NpyO6& z2ysB(#FG5Ead(WUUuL4h;$;PtHA&+3f)6#p{Ov-TM~nw*T$c}OG4}^ZLVcoM7@cR8 zE(IH7>~$JxQ);G~VMg`$8S8514tQEQMdo8Jx<;EQ@g{w67mS(jwl!f=@~e7;MZ=6V zs}5&V4V%yxk6Jrk2YK#K{rOMMw11KeG&0B?J6`!buFqVy1efN92@1iBF!c*V#mYw%)*iRe$@t6C zm21!JgaFNUAsy)xq&;mjeX^^^)Fh^(%ZZv#x=z2-;6KVOwRxaFsEN+3V2B`5ZxZ?<2+qUK*+&2JKgWVK8vZ?Wy~eZTsEx#AswnotrUE zVx6X3an$ruSSe_9Y02nDvV*npAA2x|2>1d1Bd29m+nS{z;ZJGdf3?^nnygJ}?^S2A zrB0s_1GC7*m)l{A=$D1?dAoA9FW+XYyG5iw&@P(WaRt1Yf~dCrw&x_N5|s(r8NYX{ z6(`m->Ev17c%Wu!$h**z4o;zXSt1hYbFqM0|a^;;=$RtgBYl;qlEckJW*6k*Tf01 z!HoHyi$4}_&i++;El`&9z~+$Kkx4p@?&cJyz+7uZyozn~5Wa`Nsw>f2pF;|&ZQP#r zCCa=fHbc4p-o++Z;tkV(UeBs!lCdUv>4uX6nhCgmm%46@zh;Qsmgf4_)*w7oh6{dqA)uL}r25C5{`#4jMA+w9~11Kc+_s5a#|kRmjJmAgX;xx#s`n#+2oQTc%B zG(6EyFM0IXw6}kqF){#mr30|1q+Hln|E#Q5QN7QaRc*IW6T-rOY%6xge416a+TZ24 zh4Bvz{@-ofcouxq*ncJAvGYbv%~aZBI7{}?p567u;a%|Y(Ghmd4{$OTogAhky6}lL z0`VF7jAKvF$GdKOgIddLCW*2xaWx@tMH|#stXN@=VqJFN^r{-}S!NQOC*U^Ftt?(9 zqdHt>*5Mn^M7YdMNt<3TJn@O8Tt%O1T*mmK8n6+CFgEKBt@TdDa9ZK~%6q1H&!mu^RnXV0eo zC@%SP$AhB9GC&?yRIIlje*XaXIuriSt|?Udy-o4Z?y7)q^8c`zKgRV-)r~i24pA)S z_D*^r@Zaq6j|Kh@!}|4q81TOsWY$@~?ATA$^B#oOyWH)XJ_3`4i|Sug7a=-|C16nx z2*jujW4f)k9r8XZ@H9lJcq&5!MUHd`*4__xVh8EVPG~8Zbz47dZ1&*jPrsK6ht^8+ z$kR)GAnFYH)<`p18Wgh_666P*BB7ruyzVlwGtrlh^ub|k(ZHr2w)VdK@yu*ivZ)b@U2mNc#YgNPO>Pq;gFit5g z9?v3y9i`7M6e!NXUzI&!GF&Mji1lFnOURn?PfxCSNn376gq==9>F%``${Al|K4z`i zfpI(!R@@KL#^Anw{X^>3*AkNiRURSW!lL7*0>Bj4gnci7u2@^VkB%5u|E9QOzi;1H z7=!q4qyFD_Z=y^a7>6flTdCPo#7>WLjXnule|5j_#b@lq3U3e%K$P(YTx@aC&3$?bw1>nw=To${Xw5IJ!?U~#Dia&Iiw*H9Zf*h8K69mJQSYnc zKfY~`RhuyJ4fh1zCF2{eWH6AXSEIY7OWeBvsX4gRsYB8}<18K>)}DD-%46HdpBec-!+-z|wM;LkHmOQmrS3^RT&tG6EYTPFAv3vzi!SgF*Z0 zIIm1>@Xsb75I<3*t?k{ov$GSti>)EkNN@kkjTx(#XV~a5Ql@fK{GKKstlQ|pB@v*U z_NPb2?;qZfe}LNyMKSO_5Lj98mx{E_L8k1e`m{_Kh>J8T9J4WN9B$s6xCQ*H<; z=2?!}1@1VV7|aT#h>%aG-d9Z(=5kYlMKkpD^eELi{aq>?{%xsv7U6!)tjoh|Th4ap zJAth69n+s(UWZu5@gS(YTp=YL)mbNL`GepP7Z8bFag8W}r9(-C9Ru$n--NQxDTCiR zpWt?#oEbMxG$I7V!*E+_@N?q+=X@eli%!;%cLp0F0lBl(7Xz=IH&usGNpI-)I-Qyeu>OcZB{bo4ST^lAIQEld9K z#(6(|KmDgS_TZ(zAaX9c5!q-cVVhwZ49~Eu6xl>+xpiiyw(ddX@>EmlbX%^&=NHrm z9^DYUmny)<>OZB9rAmLF-Ry@;6o?Je@5~~2UQAW78xcJZNSndX|6Mdr^vcVSS(d}} zAK>&mCCHPEiv0{iA+v>({lI^mR9p1nrRmd2($JLA!*??Lwx;I|lPeBZIpD*_z$j=; zhEHE{%?Mcq9|4>|wU&F*>7kL)x3=HAO7uDfUuE^o9;Y=OpT>zo%mZ%X+)J{y3ZSd5wBI(Oeu5ACZ%2}X_00BSg=WNgR z1F9_d#Hq?vb5XSC!2x6`Pxjk)gL?m;d2NS~!lQDm#B@mnA4!)e{xSdt*rMjiAd*Mk z`J&+A@M;6DF!ab}7JpkJ;9FANF{R`}8B##@e}~`y{fR9p4Emsgo19383dCxDziSCR z=2Oh{(4!oSa%mzipa3d(gHAErn9l#sw)T(@SNlTCm(VZP(VRr^7N>5@R%TYJ6yAv|s0&RK1PDbaC;pE}J3C&vs_ zb;=`&Oii|R7Av6&?XBSk#lVc>n>(`a^#4Xv>aIP2;#_ZBIqDNYRHo0W#ZDK9W{Ui-(fy?4Hnyd1J2k4;ftM9AYmD4RW7 zwSzAB(34LK`EY$hM`hUko#!=*)Ip9$tzNhq5t$$%7l(>29B#)~`dlOHx)j%AK0N8< zko-xzy3_V{m$HKB#as3zozyxlT*;@eO;QRdwF6GVZU`c)j!%2z=1KGz?yFF}+Q&6Y z-7oDfCY6c_K3^z4VFNU}bFkoh?ZT*Yj*XwqAJ9?Etx-EYrE{<*sf{=lY82j+Hfv&A zTADL;@wB%78wD2{%~CcG8p7wG5o2ysjGmh`dwvp`YLHaNWvRnov%06#c1;(V=SdaL z#NOliN>_~cMLnsh=x0-^)AyI)WnM321~NPQ#fWqhnV{mQVtxnjE*Z)rWF&USD&%!A z%Q~2IvtX=|bqI3VI~ zTdVBwxB{KkyfyWdDVD4Mw?pBz!FK}`jLvmvz%?Pc118r_eJ z>bB46$4f?Wjj56llldK)8f8$pDcbvfTf@?T-thW1HDV|;ilC&~0fYjN%r4z7Hni)N zj36Vr`}YsrAxCBMxpuEb8hyCmLu|cRBf!Pq)Zz4NATVz~oK!!ecx884u5P8i-rgOt zcXR!et@%Vy9dPlmEQYo%P|0_x;#}y8C^Nbt;=L2Fr(XzhQN!+h7pCoLeuWYqD9y%S;%L@;w&um3# zL)T9i{1@MX2+IOfnLu3wzw6}idJ2swD%?FA&M4{Def8NV`?nSI5bbr2)x=ZsvjLvP zKS_gHg?-cy+`nDAN9K3bxFCh4yB&J%Y5v20NW7V(hx#HSo)i*^G#x)VKOZn2G74}+ z&ME@?^3B%c)E^8)({`OE(#zRd2?3gpJiFc+LP^UEI#E%22P0^IrNvycX~O@iHj#eU zLv~N1j+OlE5{dbM&|#KofvtA3E&-?BvmpJk<&i&u`)Iz-zY4SezB)2Lpg3Fj>~Q_L z6iOXoXJ!a7A`{vp_*^sc#&-ClUCH6%cZcgYFQ5;AV>(48;8-d_4=&LzJ77u;Yx-i1 z0ifQvwYH?3gD|DG=z2s!d1*Fgsi(+fU~~#yN~CE7GNp3#xsw9^Il4I&XR6cOq=9vS z#4Htas$CK1DRrnP&y=HUFA1I)!-M!1=;;u~Uxcia>)akR^H>{^%mn9}McfW=4%4{( zw|aBuE-Pm$__HLD+BOBvl$&}O5NaqE?VE9t;O&hrTs7j!4Xt>9zzbX6S`;PvpJ&=v^8@>%1pr zxcLzrw74;CYAJbsyNqj`LcRChCNed9Ubnga=+}pR(3qjhdyK~<=X`gh&5NX(oTT1n zBDv>Wg<^`Nje#!)w^RzclvYdA+6l20OArW(q22|!)hY$YOL+Mywsp{XgtkP&wRQu z!xmxg$)%a$m&PI1aEm-P{f+G)x!ll_x?-m0COoZLnBBSO2bGI$Ca8PxeuV>?za?Eb z5UBv^5}`Y7czRTn2fsC~?{VHRVFN7$8w}l5rB|j@UxJPR#-kTEKUgfJt*7~o5vNTR zr=5RK@PpNnn3 zWWtXo7M^)VUrh|m)DGk7d{Pn}0O1StpQD7I_!7OX=9^YX^-*0BW-GOs zZrltD1!)OF{LE*Dl>>itCr>A@5dR+cllRdp*4bqpNBCm6jS@E{7hHS5U zU(tY)_~sUwW9M)zoZsi@j-^v-X9UmCa>|v@4ggo#ZD~r+N16-iDtDjg zrF)5K7x=+C>WOqO7tARa=F_>abVK#!^BRO24@COu=fl_C-|l$IvTpY{DzBA4qUtGoSH8=fnCrCP!|2yHMo~#$$H6JLka$WTYOv<`Pvs5f zV`kLD%B6v_y1j$yDi| zU0QSGX3Q_*wKnoP4dT*!_YBOrz7gAhHZL762GqjQkv}VO79^wX`?AuhhE6Jt3JEN! z!D3tTskZ1H$2s8mPdkR6MLf{**7>#>@zFg@@;f~hGG9Gsq_-e*LT=k9si93 zV+0$do2ab0kKHYy(!-69gII60e!tMbdEjH(eEk9mtacU#$#jLc3`qc}OwtwT-LA>$ zGd%9AX6STp?Xw>*jLvRULTW@KzI=Egr`-N&%VD-(n`!N!Gm_b7?h`f4{6o2tEzusM z8@|-`BLOs)%fzljIe;5?YaH2TMJR9Wgb~O^Ac>$;MaZCDcA(COo3OU&6jHhX=j=b@3FbtRs!|NgOI7M0NqDIXJ zy-o45ecWx}&5z_tH@cERG3)8vG->lUa%@ghbcn^wkWJSyB1s=*ihD@O!EXYN$oYxR z@okSsH-1(Rtl??oU(UN-{QFpB^7rq{bJ6|NW}4Gl zuH~YbmZb<9?~}UCE#;P$h&Q{Gz5^V3yirj0%<5x!+IVigZ$H;bapKSk;m}es`PlUh zW-^c{(?6zyDy`EjHK4HsTQh7f2&hGns z5_lz9(shuysXlw$sc{aVlcs%!CE)i}*?D@e_%?zJ-y4KqC=@_fayn~`o*|uDm)WRTkJD222XcAKgTQ@M?cLkU=y2!5n&BIkJM2GZ>O+9hL0~{h z$4jYMmn5t03)N0#Y5wzTOr6CZCsAczD|h2i zD!grQ&SNlnc`!ZsYOX9Q@=2kY`I~4vFTlGe)NQ@co}>Q!*8$C6JbHc){0*$u%%(-n z9u7&Pg+f>hic@=2hu*5z^DNZxCC+`nk7Kp#i+@#CAJwN&+C~EjpUjl*Rf^Jx`M5j8 z@^?Og#XDVhRu%gR5HJmD$exR=QuTAj0eyoZcHYxvC zS7QzGLYTmF;Cv44DRWKq4V;m9BOdi)NGw6xU)=e_{Jxh9I%5Nbg>K$_+H}3jiE-*j&H0X(d41~k^D$_YzpCTE%Sdt=#ccPS_+LI8tjD|xZ4yZ9!TcXP#dgK|uvFUA_& z+GbMhdoaVm;mf7o>5VrSo7F2Ys_7bTV&FXpI@xsNSDf$vZouhr^HLa!zJiw&D@Ln2hF$szb) zCj9_N*amb8TRXnCq_!TVjE3N2#7K;iZnsN+7D2XiwJ#52zG=c!!F6|}>4>z`ZzIn` z-j}tGzJ6E!XniQO(J6>9tTiDW^1a;vOkn4bw)^p-W^%}c4gps^i@wY;ONqq0GIMBZ z=rhWLD@2<#EB6^;Rpo;#xP&bn{?3)gu58ri`Qc@EY$Ux{T>Xo_WoAtP8mj@Am)s$@vOnrnRbna1;H)28(Tz;pZGg{RBne(N4SP?&&g z8@NAN0#w!&xwK9(6Q^4p{9XhTs^8`GM(V+0C#FE1JXMRwYP!u{?i6)#wao*k|LKB>kGe7NTWUolX+BwUhmoC;-oE5aWnrN(_q>?sF>{ID zD+3CSm};rTqsfBLTZQX1NKPyHu{<|ygn>vECUQsU5ge1J_=vVCOv+; zWu=xYA&&@A&1H(8>gLD43ElQApHv-O(k8B@Tz4o`a&$?XIqVobH$7$cvgC~fK3LH$ zcjPEW@lC&BCpk@lRwTATA)&&CPo6#?vYvVvAaF-bl+@B6k4N$r07yUwmoveAi=www z3lV0>mVK&Ie?Nf}-xCSA!^InxV*i9P@)r<7oSMv^*Ry;Cn=Ko*SN?#i=>mMTy_i|* z49i{K8TV;rWs?6JPaPGFoISp*A$EN9-p-Hs{?hnfw+TAN>;_QR6=UNp31o7S(p01A z^~}X|e|$=^TJl1IoE@5jEL#p0NkCY7tbb)^TrZ|9gy*=yOHE4vKeAlL6c#>4e@!?> z^_B7W>~@Mlq`poj^Q8zn$lrhF3a|8W5SJNOE;sHVo>FEc=*{GM{lY*GN8j0F%}z5l_9xiC1oqkG;(76>Dj9T znY@=(syh4|Bm34(Lmk_$=8y&R=BvB6-^!b-KhLO&vq|MD(HF_F zle(~UaMe>t?Al2*d1h4iwXo<#Y1AKMy)~e=(F#pYVCuT*zMdm)y74BbBDRKomNRX- zQKD%9V6ADjR!y%1w(a9;ldDBPE74`gWXq&29U3~{Fvf4mk;E6J%i23K6Sa6a(1wrK zus4Kz)oJpP+_<|i9Ry|dY*(m72{s!`$vD*}g&J;5@)5`spn_7dKP{0jS?0pby!NAE z2-Q-j+dICy>-H7-_6!2tR)G72Ix%a*dp1VfZ!iw`G_|+=9Ale7XSXX8yTyWL!weOw zl)!vTDAqcwkDowijJi?cV~u7+t`F#R#62mAfNH)r56NR)T^tXLA9rSCeFUWUy6pzGnayF4SH6Zi+_%B$=V zTh+>7bY*eZ9fE-YJ)kkL2Jh8-f(7wt_gYFRC!ep4SChHst7GeHvB+E0mA2!p@A|># z=oDNKrVUWW(8>V@LbVedZm$|1t>Q9;D z6g&nb9U*QUGVr}_nG9_4a07BU%Sct6zE-9^L;PE5_^G7l@k6%lG^0NUzF*C3UFSY0 zm^bQQ9Dsx#&fb!y0SDbG5N6Mq`Tof$RRy0ScT+lQW71(Z6Mf#7?csj$P5HUj2*Em6 z<&xP&yVF0p0OQ7sgF?SMkvWZuk(0an6zvuR>V4DqzD*?gH&nC0aKayP8fJXfF`KC= zT;nn8ng15iiKV5vw0BeLrH!&Sn0;A%yF?$;HX&0~QEW-PG0{lVta5#_^zbAI}EU}83ZO^u9bHU4gum2^{q<}6$wyZr{g;W%&QO11Gp>BNK z(m?4F1*A*5L?o1y?(P{{I;D}4Zb2#O?if0x z1!l-0h90_O;vIaxXMNwh*86+cxBnQ{oHOUJ&OZCT_g&X@_xIe)8NzUL^Ky=;5Kp^( zLZ|~!HtEY2O2&X-e2`S&0>R@}0SZ)ono~)iS($R`U031wKd%#!75+g#jcI$5^O%m~ z6#U2QuEKre0lx$Gvc>#dx$IJElH5ohI?sEG;XJSL?0SY?6U9pz)gQE42%kT03ize= zKrp6{;n}I=CX9~6#LjtLw`k&vDD!~@a@WKg)6aCR?OHLjgQ5k@!6SEllOu3^u=v)U zSo?YMzF$z}*2J6g9OsSGneDi%xlkRr`OX3(MNw?MWSF^Ve>$%RABk*0cj4(+zOslQ z2ZLHUW7_dbCUx72Ds8}-6ExjF|57)x9>Zjt35dH18DQRkuMym7xEF)dfS$ltuvsDn zFErq=CnlK=Iq1=6zvHGR=Z)|ZR(Io#%U5W7328g`sbH~8SQ5&d%8cF24ibm57Ar44 z5CEQyNf$4_p$Z@UjpO7+ZZ|X5WinUeMF8Fz?EIYQdDf)IPVUaz?r`-@Nx#ii?e4rO z7N^WemO%CcA2GvQTBXx~F(qB&9+*m=O2hp`sdByaKzE!4-nx#X4@^c)`_DbD8>u1w zVsyoU(Gi23tp8b-$%|WW%~pOli&l@bnDhr1IUNNpcp@ejysU4;QJ0RKRMs7X^>RzS zutf0gtzbN+$1k?pwdFa2ByMpc*>XIq*DtYA>x=6J?E$GjVwXe$=`NuFA^qICgdydg zul^$J_s9`lLPBB!RCa~1SvNa33_#gE{ZOvKG;N*G(fOV99R zN=N;)HJOdP-4TLn)Q@R|6$5tIhh8PrR0 zKPLSLE{m3{N3S7^1;87Nw>kC_iR!MbWd#fjn##cvxF?+;@5xH9m#&fqf2J)t&oAsh zE(c%0VohbrT93?)40EUcrGHsJjq%V3Hwdh^*QSl1w%tCHL=0YCbB2Gh8y_;1u-;Y7 zW@55k+vK}GzgE--?YsWjEH|l!QVu#;vz&0*J&B{rUQ%@k^Aroa|19!huij+6f+00* z!W%s{&2O9_?`d7t3+w75=O~qx7#6*x9%%LpKkAL)qc{;@X9{KtCo<~=jpb^gw16Da zva+)4?9V^e01;LaTmj9NnN{hnrWBI4bgT>sI2&FuB=IHv)51XjlsoNh7^cO#oBvEK zIlr*yinN%E*-7W{68BfRu(m&!8zQ7^)#J{)2kR086S?E{Vn>zmZHO*lFh}pSu+VNsgnIB??(1my4hcB`u?xt&!B!sa*6Zq z79&r=6>Ke~DtVnD@J*LikW(eyl@cewse5MDY3>C!1tKj+W=rpS1D*_fmo2;T7@d-2 zh_wq=iB%Bx%^tjO&Mj47WL|}-GzsnsF*Ra-q#(D}EcJOKx25KI3N(~k->4{bfkFx- z%q!!>w0jX*X}A0X-qb8$C?_Zox3q1(18?!|v;4-WMr=8<_s5MJIqQi6hc}fnoor?I zgDbXTb|7+_H9%mQrM#Jnr7m#P@@C;xS_g>&rb7~lT1EHPc;>ku zU&>`FbLX@PD7Iert&jVkGs^u|wPAKf52Rf5kF@dPftlaADc>SAIF#WIVwV^3S$gLD zkEzij=u77gbe}Ay9ffFU9Ia#^nJj6|dhU3d&RE>uU5ML4+rnu&uwj}HPr@sJ#gwVm zlY`E;DP7XTzPGq&8g|GBDScmRkBkIN@L zju!NdOxD3{NGbq)>B!Lf{`SFBdgZOsFxQ2bp}tNt9Bs{da-E`Far~u??TwyuK8R%{ zE|;5aHXG;pIqG!rj7ioKc7_+PiKSE_cx>Zgrs|UPc1M2(TKsdTj}NiAMgY}K?hD>E z{b_?WLzed>A5o{1N!EQcmHvzqbyBmV!3OfxcFsO$LEJuef-X&Tq>?@2tZd^rf&z|K z_N%Nco3%azSM?i7bt+jawF^>ndsejJ*tl@Iv1TxV-0iDJ{?A1z{uF-joc~bhW4c0b zV_%Ijr|xYFcH5RQynBVLIYD!A&P!O!-aqxeU85qYn$ZyRYlTC-f-yP(_}eB=n&w`O z-8HL$h`qjU>ci5M$`j?l82&uX)3=7~kE9nXo!#%xduhmzF0ds7+vqncn; zk&+p4+z$_)aZc6+=0)Y&Q%~P@CF-;k0&6lp*FBw-*Y{4YzsLs=Q`Thb?(0cVi$?~* zVllFMh=IK*64H!|29i*9-)MKNRd6E+R7cvZCATKO(li%Y3vwRbGLkGWphDUItwF&d zhpyrQNastbA_bK-Bwyn4sb$?@r^(d}%f782+M6_$o&OC(ji8H*%~E%uQWbEA)NnC( z(Ewa-6s4d~Dc}$hJequGLn$4cw>fQE)zC+(O`ZTc-BJKk%p|t_4lV6KmRK^vW z+YYl8eN~Dj<4^u}yn8sf-BT|}BcptfI#S6Whykf9id4Pg>8umUh{6>vGv<%iHp65uo$Fz(m^f7n zJ^ZOYke0LyDmK+5sgTrj2cM^&ZV{uQ8G*J`fWMWK-fJ75?&)70`04NxaJJA9i<7Kv z2r>Gee?9 z=Y1m*F*X11LOP|G`WHG6NKhBiz#=)b8uqNQ*4;bI=bbxa^f0~=lo$_fkuw_Zqu}B} ztqxANTY_>9ry zydFNzAD`XmljEpdTX^PRp6khx2>Lu&2mBQmV>)z6FxZIu*(XQ2&Pl#q^+Ow0wrKB9 z&!?xPqz<)(90UW$v*j@Ir2}tLF8{$+J~%lJnw13K`gkd;5h~u`b|t=GeCpcZfYzN; zM%@tx6D+Lh_+;ShNH(xfrhRyG%~mT4=47auT6?FH+^|kOK5wEe(*(n38#RldNDbj% z36CfTDb{5;9-Y?!f>le&1l*%Na;QH3WP;C7GCBNKs&`U@KU6vp}Tx zWm)d8@4Jw2TZ=57%B6|j|K_nz5JmS)x9oM#V=-o99riFAe8})ghLfF3TM!TPvz7BL z{)S#yQr3ay7v->6Od6srXB13^zBB06hGzMrJFfA=Mn?wTN+btJcs(YwIJ27joO*JD zuqO9hTJ^m_Gy@ZtMz_aIaUq+NeN=C5+#iq#BERzOCZ#b4;FBs;Pk0omy)rpz&R$_wW9yO@h8>C)C&#VtjSTw!v@cr|cz8DHov z@NZSp;qvZOlPPtuB><}Bm-4D6b)w@PYxyr*LeTbGSxfuO)ITC8q(&XrP9tXluGhx0 zwN^-j6js{~^%@_VKb5?M2jc{~ReHfp3@-+p5y)2a&SUAKF267fOA|=c`OPUMVM>V7 z7y;_UQ!}W%UWYyQW6X>2WT1Uj`L>8+((^pnfTz*$lbsg-@bkwn_cLrt0X2W5PcrVmU1S zBtAYuab+JRy|G%TO!Fu}+nQ0j9yM!oJFRr`A`Pw=B;KkhyqU8cn&naC!dc7S_EF5- ze^^YDL9>u^;GBDf+aH@Qty#kJ5~J=73RMh-tN=DBIF?YU%r1eYd)$G+;=tFnbH%Kr zN-mnaV9`aL=PPCLW=?0pxHt)&_WfIv*5o*-@yD0WvE&meH#g5zKU`Sp)(as@NUoQS zGZK;qH?Bns^G3!hs@dd@Pr{p3Zy(|qBiU+#@d{Z$C>Y}&6_-_4Dc7;)pKwf%F(N9a zt#eC{mhW=m$Q07DwNW`E)5tL&Ogs%=qXQ!JH2x&=z?HN4cc1c}>$h|XXWqaxM2YYrSD~ z`}L@>gJ3uyFzO%}${eizr+A$T(!&;emkGZ{gl;Bj>m? zeO)!Sn~y4*&+Wl2VV>axO$X71JMHALww*fxs8`|9w*(|)ph3E^KdY+)=u`4=Dj@@DurW2za8`4GP1p!4U}I5j1x zmYoiiM$v~M0#cN_0jKxCsV;3i@}IH6eS%fnBvRX*Xqh*Y8?;jA(6pnSsRBPe9zD~9 zZs|w4-tab9zoe)K{PhRn)RpbOlj6*)pc{%Y*FajOHV=DkR9?FFefDr3G?qJ+IyG&3 zYfn(F(v$!g2gVwnJZqFV;xFFf?%z4y8ux-<$+V%b6~Sb*feTLeu>Ac9XBh{?&YPB;Uulk69%^|Ft-bCwsAnn@(A{w&HMnpoo~ zIRa$R#yN`Pg%r=Z{3EHtqAk_2FBLwNGzzVRyDR0RfM+S%eGq~NB&dTG&2plWQ9XEg zK=8eij}=2*rSw1sQ}Zb8V(>ZJ{aZI@Jn3FiCi_8CODR&0T7th*3k9{S@ocL>qN{1A zFBc?jp?W&!Bx1f)ZI_flrSSp^_M=e!aDIVAn?5N0B31bqmAsa5LsOUMwUjMP`$&BL;G9>S7)xb>Nd;gv0WcWgNk8ngnJt|<4RCB>0YN?e2SM33_VqdzYJ#NkT< zLHZ!E*q0=r4dc}1Zc{qR5oaO>KFiBZmAJ*hfuiMs>G~WeA9RHn&pIeYjkd>-m&OgZ_ZiS%M@+OJ#rc4>9I@;RMxOEK}JzORC2JnbX4 z4mBn9QtA&1(b*4eY{=XC^{>s6YGSU0F#ooAKhgXG!s-b5WK);jzo$njUzD1EyvMQk zZpbIPhbO=vV<2t{|8yX{;U*wHo2ox%-;?XJ!29T4RIBYP80wk@vdEK@d;^xpDEZeM z?kLaE3Di3Amni)cN#l_aj)F?A>J>Q&or!ShZG&m&XNoq|n84wmf(+JEpJ1mh!ubo} z#|1UWZo;v0SchARebV8z)$h3mih+je=UZe|YvC9QmE#9SSC?O)>FU1|$)+seg6NfK zJ~OfN_0g;^8_UAo_ZlMV)pOS7qa0U8lNnVa+;u@V_pxbIHoIw=L$}Ue3yfK=(+Kij zL95v-akTHf`Hw)P)qwiH4%sS<_uMAUf*`+?#wAdw_CO^ik2A}H2n{1lmL2r{$N1ro zdfeNr)E~_;=I&NGwQl&ASuPBjw7zNjWBUWSKDTlm0s4bY0nibCkG29#oc*uz?So>< zFN=B-mQ;eNL>vFkkxgzke@ZIN|*erp0p-M)|&wIGP5?^ka zEYd%M2N|tj-};ZDHq(M}ZTr{?R^bk{*+Pah2|hqenN zXjc7?&_qegmw}O=t(T{+rg|Q`Amh*7ry?VH^m2~L>FOo3K+FD;T>d9m!`6x>*U{_L zOtli(#KN&tTut8{y0+wO_t4PM8dTn-;z*;3o$CjXba8dhHJ@-5n&&Oz^0bWeCXDBh z3zqSzCf0jn_VmnLf;d=#crr*uUX&SUNBK_(Fa25+_vB$uB}Ym$C9cV@nr*v<_o+v z$N`w?_bKB( z5pz=@>vQm~tE|hMr19jb-Uo|uHaLL#xk`HslFwlwul#v@N%z7QVs-ZYq6mq*T@I`Q z85GXBJNhbkexe>@hn4PExh*~09LXBbu=@h!P^-uIM?SJGvHGV*;+d3{g+HZyB5PtY zhaZn;%WaXl+H|Ne&kH(!$OcMF9kBYR2}jYnYNqRdU=83043n$F8d>TY`cyDK{$Gz@{-2+=@e_8S zNiTMYF#a9Erp!$foc+lE7w2+I*W4`*V2L|~s@F$}+ci?PlIU5_swYky35%wm{U1^! z4+oE`QSR(joI3Yk5!L5+d7CB1;GV-wr2{`vo>JTHKxXUO<00c8{Lo`wSAPEiDza@qw|-y@tUH&KP0a+E^o+JHM!tPxtWTMB$;vjqaD5G+Mw3Sgh-)>(V0a;v zS;jCC%+zMZ%DWiezaj74+{}J`L6EYyz9-g#S30Anw`%)@ZLyQ*SA!(>(rz8M^0b-O;JhjOelj?oV5aPF6MG$0(I+R)5rf` z01#_vW?-)G;l#5>nZF;$`R5YPd`sJY#mW59+_DV+1_&MrR~^Sb$O_v8 z_3`+FUR4S+Md0Fog*%lca>;g?uj_Ss!#{G;agrDF?m>`5($G82^*;?YU12G1{zn_$ z!1V$12prX5%C6O3?m@~B1NETt?=?T@^X-r|pstKIOovPZtXN47Q;t{K(_3HZ^iEtq zw;`T_xo6t4ZyP;)m>C0$9f&>1>doRuIjcWay40Na%oy1~9Mtn6H^CG%1Gz&|k7nz; zu5i1IB-{4G>+CJ&Rz81WFl^kQlfsC=|2XDG6&snB%C%zzNM(JMJ_*fSt*TZ2Dg)RH z#R0l_jM^}8;$`bseN#&0+vi~GZZ{t(Ek~~?yx~XT!%T;taCBl;1LyUd8hY@(XXexz zezd%Ms!Dw=c-6j+lu2q%;b~s!!bFPHuGe%DKbLCe_lK4(O$FP*9&2Wvs5h{qeKTb^{YbF8Zk)^B19QUanU@L#|jf1CIA}xJ>MR@o0d4 zmC=cumt5XVl}myGR8(Kiey~F@^>j>{R5uy{+TWD|l6`7CS71Z;IQiheaooDa9SVN_y^A8#Os3!D{~wg{C|67erp5A z?G%sAKlpDgKv;5o;!L3Z_vqNS3se;r*jpwe+0S@P8$U>@!$tq&;Y){-G+B2>W_g+k z2Pn5ES5vuZV9+tik#ie4?)wh%!`>I*oLy)@%-8;R=D8>U;aeQa;H4S#?{9~hKd=hK zB{VGwf1QaM=5|ByC><@qheIpKbm`^B6hr^8@#Vq{B_X-3>H~czz2N$|X90$%A=_!Nb|!GrmZQ z?nlLRokR|DJ)jCV9wGmF5VQ3 z$crJgYfR9Z!v={(PvUnnmLgMXA2{(GdHo{pAsN+Ow=&0LrN8}YXpZQ>hHXTh;r`N0 zNK7OmZS3{*B5Bj>5cr)&EkPVVbL(ub@Fc&XiBTk}3QzMMX}leq;fp}+GM)G_tH_AK zADa~>^G(ISpl4;;{Tl-{;1y3@XDfl=*MGkvqZ}0Rk_&;d>U5m-Sa~t$x z*f)p&ZUX<=3N+008&QqZw;mqYD?gnd9qIv>AUu;^Rd)-53Qd--H^g~wW9)WZm7b3 zb*<<)LM<|h`t?A&mB+M+PX37RZYReCq=a^S%xpxhflD){Po5TEoSdAnwqT-mH43|b zH?}*z%q43+--_4Hs<^;BTGH}b-{S&H@%?$joCdf3m=Yhfl=(eMEX=FEL{jG;A!$-TB0Z3L(&jMiul(X4cr4W{=P?zus8A(wW*R+7HHgYXq`ydV9ttBsrH*% z>HdLy&GwPm%1#tmoWLCr?X2Cr8tgn1#k`3XZr8K}<2>`OHs@^no z!{md3Wu}}hFZyeN3NsR!~!SC0^tu9hmp)kob@^K z{#lEN)b%v%rANOSqzWt`mD})#t}?8g`bVtXx5KY*?HN{=Z4x;`?yp&hFLTSs^z}Ux z3|q^6Rx7Ff>9^ip?&E(NtS_eWY#+ll_uUYx=1bGv#bdVEV4#DrPH!* zi@_P}Z-Hxrpvh$dg+(%3?`nQUcfhg6FN)=6e&joQyVhzc9g&DxCN>%>*cGyVNcHV% zU|7#{Eny}d+Y^6)eWde=<2A_fwDZP%znp`7gPsZaQHKnoC(tiY$PW3p7cDl8-e9n8 z2`z5$8sJG8G>Gr^Ba7ShO~sH(eS zibkG2%u)LE!Z?7MP>1SlBJBQ-Ngp_8=<4g1$t|X-9FLUZEZzW{)-U|395hh?UjI_5 z$X>#th!AQ%;T7FZ{(lr8Mq}QWW^1|s&z|yOp-~t47A$Y*WebqoOAcI`tY?Ok7j zdBFP6*Qstj_#kC+9k*BajU0Xag}}y%7$PiSyQb(Yw<5L1;5nF1qbK`^eqyF|14#}F`9v{H(^WdSY+Ba`2h^0B?U~J5l@x&JGw#tlf8L&Joz)VycXj8 z&+S?u-NOs4t_m_CqRpNb6KYTckT+sibB8FQT;Li0g%zJv`Z9fqT|%-`@TdBrrs_t{ zM4(CJMk3r9dF03&2=6l_07j>#@>}&6>KTAtUW89W6`2ki<{&mN%uU3dp)OP>YM-US ziC^KB;?V*{7LLfOnvdnbsWdPGJ0w84%^!c$Ds{eMlZmh!0DHgOoi?c^y3Hb#U|v|4 z)v{oC5%4OH0;g*P<&LRZi+}DO_ zkM`xuswNggEc%S8h~{xh&mhSov-5*$Pf=&v$coTI0q{y(=Df3eVm+eaSWhpbd;0TH z=4T+$@^i>qe7Duen~F#U7a6IiF#6Xtwx+zwfUdOZcaBeH-3VW^_aaILyWV&r>rvzx zP8lS`MIZ4_Qlj^9;-rMY{^mU~K0AM?b|4W?Z6@?EAn-eEq_ zG#J~px(U<6{B79>{gXb1-@9;J*H^1EPQ(Gauu)P@GN)jZl6oDvHDWmC_hzl7@iG2cuP0bSk95uw16?VNzi+Tn#UtZu^+A|Hb7~K+sq<({6wBbj4<7 zh5L*e?;_<92KaEb|FN7H(^Cqw`HOCh2gHC3{Mg2o4938NtJZDsoOJHv%Cm^WLL#z_ z6W9ogBBo5LwBdD?vLCV7tuL|T+Fl`%7H@Jf+7cLLc=`hEXO9nG%r*#Uqd{^>By-N~ z0BZiL8~(Sy@|I6jV%EG9?i(bQod6Oq=T`~?;y%h+ytGs*jy`5R5%HH<$;CLFsfzt} zG1Utp@jVkIISxzi%@*QI7X0RtWRCyVqd%35QeIVR~TRNnh1*Zcw^ z;Gyb90mf$rX5KY5|ESvr9jZ5655%@yexw;cOedNx^3m3txp)SucBlDkjD(;@LRJGz zuSAV`t{1M$hFlZnx{s9?osJw!-0wBym14^{KcGm&97=AI^1Y7@`gZITs7Xo(Li5{ZxsWAokvt( zUg2)nv(N^jj% zRUPf|lY^;<2$$NM{G3EIZOFl5QqWaL_a6Ua$*-?m|4uvn?{*Tso~+#6|G|uWhCYs! z4{XQ>vk5aE<#b}_(lt_7&pXKtsQLlwtk}1SNW1nfmk_C$Z2`ieK89v3Nmr^AFt(!3 zl0e$?hfZAtO*qM46$pAo0;%xCuuRDXe_I2Qtj(ryU=iFYjtg@SlF=rhFyacXb<5??idiz*np5)6TO}TK@pk7Gy7KZTf)%`cCt- z13T>=u2*E87OIU%sjS&%!EjpdN8!}o-1eZBj2{sHcU=cicT3gu8xVngq+3gpb-!Ut zkJq!>gN+D@%c{TAKhdE@Q*HQU?xauWEGcyB4kxpuAKS}by6alB=zF49i`zhL>$uWk z4Mnsgx#o6NJxe8-;~@bmYx^=cCLjOJ(rbJ7n|6KHMD-jJe@M)7)2N6irH?4PwA z1&Zq&3~9SF$+b5e1ASy5ESRPT$P&c1t&3D#oty402n8!CfGiOKw5#!rR@JsX15YS8 zgtig)7v0v=MM2R?DqgfXZ;D2}l z89y7W8+!<{(2L{eDmb>FX3eqgc>UguHmWP6Vhv<8P-oP)7-yE{M#nZYB9BqbD}>g(xuDApH6(4 zciyR`!?^8wU}Y%QLOJ{0+6U<4r=8_!r)gR^Q|63dGxJZoHOhQw$h!_L;=PXav;E9> zqN{aG+0Z6dK7G$ADzDWQMhAboF!?D;s~UCvv8`QS@1II$P(vo|x9h8o(t_6d8e>i? zzF#&r?!Au7QUbyIYm`z7#fIgt_fB*~>x9rRe;@~R-@4@<<ZC)i8NguR$Kdrftd!zjHg~Yox2MaT9JU#&WP- zU6C_1R3LY*$CT^y>rj(~I3>zB#vC)W6-%j6fyd9)K_M)g)0lO4BE z|4Q2Qw+4qliblcg{-OGyPnD6tiFu3Gpb2)*ndrpTS$Y@hBthj0=Gi2wki1tf7cuml zTGYguwmsL>pf%^WHj1y)sH0h4-|jxV54XXrl!?8R8!1H>M8Z!D*=J?~WKlWYg5zKg>3g})Z;DS=*VJaFOKv`OXkLGQbG8^4yMOr;P-!lFn-Orb zxwoixt5t9VYPCm&kf9nQ9`fjAq4aOS727zN2$xn^S(xzj&~hi_aBR)EF`%ai?r|pd zeK>m6acZk7Rj4c}Cl7brItIX!B@hSM+{I%2r(xsI-oSkX3 zPx(#o5sH`lN1hTT4nH45ePK?GKVcb%CH{FU92@`@3|z}eiJvv!C!PCoB34A?c8g3D z3`b@N^tpOn-@vvFBs2H+D5o93>972KaPv~P&Eyz-$o2_7{2BN@Qzh(nLUwZAI(}NY zK({e<4mxTZH}1WSL(zdmkLg9~f2+joWlWcS&KYBd_HS=cd_j!niTNpQ(HN5(VX8z6 znxbC1h({!K+Nc%_{LZB+ucHc)!{mY2=ef!ELhy7Ul>%_>8vY@>whyd}IGPT@cAZj# z{1lx^4s)di3NA4JzO{8;foPgm)PC-61r?JKvZTXQ2=e$M!=@KPl-Ct|AA*zYXP?hM zbdGI*SwilEbm0(sUHSlbLEd4CY9R#M9Qf(p{DKv)@BYosPVW1fYJr+_lT3g5dA(>n zTFpxL>O>$5DH*_U&pi+OpSf&l`u{+#&jpxM=G@f1PScB7F8f*qHWMKv0PLjfOXJKXlV_{Xw`*4L)NIdn(tni^YVXbxig7 zB?}Xm$LN>zYPNyBawO* z)&7(0DSK+RODohG=+@N}F$tDZKq^R*7(ivQGF1e-%#ne3gVf`QP*RgQR4Y zK^4Jt--%vTT+O(*FB?eq!mozSq9rR8YJNC85fkwL4c71PBUoSp@*<+@h5GSI@5$L+ zKMM)qkdh|{xj5#3svcJoHo1`Hf5aJnf7!$+3Zx{jgC*qOBr=Ce`qT>!mc;#+m`0(fdA99&Oxab9@%2qJ-OLU?Rf&pT1De3>szjM7}Wt6INvpG~o zh+}NMYk(_Hy`T1Ajf*9%@5ogJ)=(|^Ic+k*9Otq1dWd5>p9hX{3`N%{a~)%?4PKrD zf~YZi`TGs3$^~ zdUGE1e8YnB%Sr+tz*K-^^BUqh>GAHL{4ngOgD)KlrEobV1;cfYMSiq+81W*gEDgVX zn*!fKVT<4YU!lg;ENim_yItz*A)8qZ zUU0Nrr}WF<5*;qq7~j#^suiyE5Qr33ae)jgXb$OF#7$zhLEca6TLl|!kE_azn*#Yc zh0ZBeRkR~9?jO827{B)3ti}0au2$K(!lf*H3FoB-kQdVdOTCg|{%%Hqygc&;Jl$3n zkESN@M;h(S1TJNx)1Jz~J#kKG28q#}NtqjRm4yS0$tYlIP$l^1X+MA(y2=^sVk%b+ z^NZZ&h~WX$w*&4~+$NONX)7vzyl< z!-Y#_EN>sOb_G2Zbh_N4s;UNOov!0X3l;Gno4CMPEX_Z}8&;*gsbc%8zzilo4I!}y=_y5yAZaOL5&0+ar? zRxb*a>#0Dn%uqa>FH1RC7g0SWzwA>mSlu~g_E#I~KL(f?wjMdqxl@cXE%gU(rLO#_ z-_qk$YdP6>-KB96GKAr!_;aUF$b6r(p= zL+XdBYY;_YjCM2dkw^aKj3+;yw$)Y&M!p zxu2@Y&M+DyEM5n69{-NVe|9diY+z;HgbD{1?%i(JObbA)ZL*k<9~*Wpo#je7Ovf59d0JT1)aoeysl%|?Nk-k%s#hCW9VWtzNcI_z4GF+H zzA$itUDrkG;#;>3Eu1zWpW9dNqiH|)o~5FC1Vc&HVNPR`rC6ZvEEwjPFPJJkgo2*> zu)}IO8ELgt4)cGu9SwTvC{Cl$*fnf;S|#gUBu$NpN3YRQi7=I4lEa$qotF8<&ff%T ztk+sqU%Vce#n?g$wTg$I?@jZnNo;ueKHwKxPmv>^HsyT0eD%onOV*p@_tzJ~_LsIQ zVJudwLFHMV%W~`nH{$9{z9ZI&n^k7#)X67KC>$RiHqu-An?6vIHXj0PnH!?DEn239GjT+Du^sB zCVkpyPCh^}(oLtWvl@WTX}^t)Ymq<*p>BK+-|M^_ga!?MFZdlupz);9Emx}?$pZe0 zrCnU^qfzdrrOIZOJpd~d>#xsmJ_3DIF@}C*bI4yNTLm+qa8jB>N-MEmQToeC)GgnJntAxzg@m z8UI{gC1z8+-DR#AVS}>yGU+CITP~u8Q=Hpw`hh1r)4NEjF^3ZEW0?;ZAr`5`27fue zwwf?iMt^p_BYMFofNS3AV&fOM3efrTn*=7zKEc8y9aEM;&YtNaV44jkBhe45gzMX6dt=U;GsESFlGbmIE!>e~N)Ph^_eVi6`nXgFxu?EBf#2$td%~oFIpN1|O^? zvWTRp=!!+&T>=NY4Q=48Jwoh+Q4Vzmbl~CXc|7FunYSjJK@z6zvv<)2h8N1eu*rzM!YYf98L8HY z)Ti%$9Se)`oUzWQxDD2YxNMDB_)C~PW2bh049eLKRqt8m2?|h;Nju04@JVzLmc@6weL2v;TLm4{Xe}18Z0uM^VOh51c^fy zlW?KA)+*%+mBK|HF-ji_*J#3jeEXX-_ zM~k7aobX_hbRQa*m!&{Ik)HO+4o3`(1-B34KXKNFjE9TI>I(+jx#>IW>O?r}C0YlE^+Nu;#vb@Od7* zbN&q&@OQJ@6MfCm*AG(u)t-<0WcvQUIK_+jVvh$9otO z=G6hb$Dye@Yg#|;3NI=8IWh%tbKWW%GY3F9%hZRa_j=Q@DhgDrR-@)~1OhLrbCwE- zdk)!b-<7qxV(G$^5PUCtmKS_c4;J;ePNy7O_Dp`%qHbel&F4uXmVCa?D4c6vJ4z zEHmeYF=`e5)_;Cg4#%}DulLNZN72C>_w~5wsT`;Jj0I^Q#da4<#Z=Oz5H+X(+jSoC z`%zGFJ_U~U@^z6@clPx^Xg>DW?^bmyKaw%0eilnb zu1g|qcmVu{<`6`IKR)!N_iEgsE!82wK1wIXUymm8z(qX~z+IsEye>-)&y(T{TG z1?QpfASZWNcBmVT9nEakK8L2mK+a8M5m!?Z*%sO13!kD%Y%x*aC*diRsot%UpwUuu z0ke-2CCf5rB}M|bm|(+~^YOhAT_O`WndC{Ot~b$t0-N~=-4xD6`9A{mlVzkzBvlU*>>tjdg#J5SooL+I`4VmH13JWc$yFi^fW0OB`tkp`c(exsB>>U5t zN(TH_xh3^{#zT_~n&AS7NSPtekAQam^!nuEPYGr$o|!n|Rv-#39*3!>GQ(QZRIMgH z|COSkTX!-Zz=73XJijftjhI-$NkK#`-Y@Hb;KK!v{?^H1=D}tgpYcYSD~{6`2ikO7 zO`PXBhV%XP%e@#SKpl~u+cB&pq#FF@A+<5XqePthdWobhG2|d@A;jF{UXe-CZYC2z z&)SO3V*&E0K1wX`xqf8u6ML}-d(Ir>B!KpF>3XTe3XUqEccbI|%$`|Qvq?)yjlD)}G7;1)Pssf(laB7LCk-z#SZMO_KJWT&?20?4 z3=9&+6ee^4+LP#*zc(k2>tfpvAiUnwr)@{L$6oE>DgQQi?}!mEvx5~*D|J50Gy`3< z?<|Ptty8g$!y5HwRZp)d1e)^{w+ATs>@`Vqe3g+Rq3Bos_fg=N13iT zCaxjSxTwntN`pto;x-QEsMsA1Z9rZPAy??s?c(Jv-sHzwvHw-q--l z8q@on$O4{z$1~GnsNu7R)G38jMq_sk|7u!y;TTodc9wBXl|+mS(C<}??4bTM z)ndt5(?Y4|P>QmF;*i(&8^96JSP}1?H(JvS169Q5ydbX5?8Cj$(pfTv1Na#~Q|ev8 z>49%LN)xZ?1m>nD_}M5S`DE>RZr7*t<*0o3ty})MTHOIaIz{6cxu*F1X)3$~Wij1N zGXPh7WV2|ueYbi~{-6QP*F%?*LON(r^mf@s&oZ;v#-1L+c&T*1!56q z?W9l5cOufcq(d3r^9@Dvs;g{^I1rpdrW5U_zvM<&mcA2wHOar5YVsb$bI?dYNpo=< z5|=XspJMGr6y5bYrz;E$TgVj99X)F!P8Ng>9$Mw3ZE|((Q5jv1^mRUe?KeL#bDOpxltBm8sv46q+)UJ`v4*2>^GI-fjGp| zGKdBGU|%_|yy{>0QB&L4b4&8QK9OkdG@bovSd|-eov3OCc)%|1X}(28R+|PNDPkrB zuQO4Fq4UwEZTX1(QQ=;s&WWHwztY3H{>4dy0}X4BXM*i4)W*{RNcf>}d2%5vaYkWpRtBVSZ zX6QjYI5{{e!0U1XLVfAc&u6&dL z%S2~9sgBR=!ZYZDXXFZ0*5WhX0^^2tTAji=NQ#|$q4YXI0Qh^@_R%Qwg~Q!R<&IZ9 z8;A6yhxfk+`el@sq1ug$z%IV&7Ho|GWd{hdjbE27WFQ@Oz-uuM$%k8P#D^)M+jp>T zOG!LuCyi8z;()D-=ZPWCQMrL+>;~jSJm^qmDk5s{vQ2nEvU5EoV|BS+95bHwLF$)m z^ii)hp$JSpV|UHq&1w0B%WdfSlEz$W!VUGXCp=;a<7N-9eB-DC+POEn9%~qO>@%I& zLBB-&R|W6YS;3c+634ppIH9Auy_>~n=U(Z_Alogw&rV7Za-A0eydlS5t^v!;8;gX9 zg=1Bw%zhx_6EcW zo~l@HW+?30s(`AAZ@(Ax`ptUtOH);QfYD(okj|fcTamQVjg5BjbWR+jQT_P%Fu_v_ z&^Pc0GNdf=p~UW}?^S;W4pqOm>VQK-!s2hgssquH-c{Ig9~yZkwnb>F?EX$9aP_=Z z+dFFAfv)l)@uF^ulndULXMJmL2s3@$4&Oi+Kpwa|ah_H(lL+#SBr`KN@7GQ8U@;BE-_zi^;;bo0nogLUQ0 zhs_69gDu>)HObo7`kl|Ex(2t{9L`bT{f=2U>SsH6sd!hA1ZvV#zM-TWODPqh5B6@t zOTajK@>Gp8xAGK}AJSHX6R{O8cZa#i)dTqPM;`8;PQ)mx#=m>#W6RwZdkd*2RmRFK z@qHm|2d!`e8CHnEO1SWOR=JU%Kj^bI6S)kKi-0uXBa=PdG@s*&|y2 zdB4EzC&BoJ6thXV)Z%c~396`o!f+p>C~`Q@e`Y$x>QG@dRCW3_)ys)7!Zo7+5Lpfk zyyo}%;#+1ztoQ8MEzOg2e#u?>ZbTUI;Z&@$0C?j$QThmV!@i)6$F_I2oaNHioyOpZ z0&MxA^NBlpAQ1#(;&(lk$i?3Z5sr8GUHudp@tQsVUCqWQeL5WSOf$UxtD}FInQ2Yl zm%|hd(`vDFMIwEryk&D%Nf+>5;qaa~bB^*UA@f7k%-Oic%NhJx34^)gOFe=hg4&~w z0W6Z-F=>BL^l}ltRr>U^^W2E1gNE{II6jnzZNP9Sx#;N$q+^jSy*nsvGx{~xQkX82 zd13myU?7VSjeZFkEQa|0$*;0xx^|@F)FiJo)|ECQDkiPACsjgF%TO}r?hUSH=~L+4-(;F3zEx#{zU+4GgC)YOfL1}1 zaG;7pUyJ1h>3Fd658>TMwRB-jDa~P@Nn07MbsFpjb?B)mUIk>4@pUbp2|c^TicS8< zCW9U9(ylp!#KSsmeXNM*yBxiDm3J!H8U;lUPK;)Rig{ck@ZpG(+PEhOi8u3N=avSgtOXT>U+AdTIi#n^Rr3z<;)r^ zjgtoq*JQ{r#5v>2YI|_)985*+9Y6cuz!#6s&8W0M z_kM*c^;y?5j>VF9W9n!s*Qa7Z*Rm%jO6{uLchtq~ZPaCOy)=z{D)Z-8vf{vs9{={J zA*CTGieUc7X=S>E%e3?nPLD$6mef)dJT58A;svZuisBLQO}Xjw9hp=w7vHsvhVSad z?vW;U3=g#=&%O}pyHoCQ^U$B)9{;lQeOlCp3i+#%Geo~Rv6v^JZ(Pv<3utTBw9V!U z!(gO&mtqNP#1z?k#}RhS*FdiAO8)aMf&`4|nU5M@{~7@b=W?c2yQ;{naPIvnBQhN) z$tmw0J32Z#bIe);CkK8uDM)Tt9DAynVOIt;Ocg+T$HSfWon zKdjq?jCkg0bKI3{nElzy>Z92}9!<3<8 zXJGd2y_M?7$s{`exq%6k%@RtKhtF_f$P>L;V)@bNxe=uR_<}|X;{1SO?)X*-Oe!J= z9BQ^fF?2uoFRXH7D1o1+K2fE0%O-9Wqo^BPXWRT&GlffpOcW)|2D&8|64(V$R2dZ! zp=BNVwzCaP@4#qjn$RoOA#jmA-`KOM)y2%uD>(KJ@(M`iGZxWVL?<=Gedqtk4>4<& zBE9Nu@krydyitzUAGnCh0NK1WxX!~|e)?7nc2_{(pKhx) z49h@@I_GNH2xWR6rtn^w^D~`wcWw~`P3M7avAUZR=5E~@CO9X?O2X8zcpp7zCjq!8 z`jk=K2(Q{-I-f?LQrQR#G2U75UtBVrZl(5JC=c5i5ucakUkLEbl3H@JtFenIsR?`b zcDsrT71l0BxH>!^?VV2NpPseVw`J;L;?*|SC|AMp&*Yin6WJ^oncPR}X^jdjgs$aQ z;Of$NlC8Z&+o|-L(-bKy;VY2wS+!LAcp;e`8CXyI6IhQ|f%(DgDZh55JAd_C)3&&^lSSc}=uK}^SDMhLEh1p|%n08m_0V5Fn z#wKU;8eaN;Le(6<=&H`l|RNyL??9U4y{4ASlPh_m9}mg8K*Fchx-=W z6s93Ns`TlFJ`;vl(}!|PPHpPErsny!rBf0$p(Q-7y}if3BjWqAj7))nUbEDGD=#k0 zfQ>%lQ2x3F4=2>xsnD1hUZvSp{x&CP}9g&mY-2$d$!S@q_pNYb4IfCnm zq^F-@wr)Nie{n=-{iHdSWo7EctCV0un=E(}uc#K_+)L6?Usfb%axgB?`E3Ud^4r3< z%A>+-SQ>;rUkgV>W~mq=^HVZi|ek8EJ4dJOg-v? zzR{**)aHE8;GaB(|7ZAI4Wa+#QbUU@_(y3_esjUbLI$lM=wz6lufHKN!WLkiy##^J zty-&!=WlG=@~~Pr2&zywlD%pHDgITyUOc}`M~bEOGik)qqA=hTyBVU!o;FEso)3zp zp=gwMj3+e@3+cXP)YQZy{jKe>K2_+oiQ5qG z$BbbvMIB4$7q@j%q14$YA$8n8*$C@V-l7zOy{KL|C)yIkoQKti&s%T%Pa4qqXSdp}R%OfiF__pv zNf1vPp*Mf7RdO%3p~xdTMGR-PNbO$aJ}cbTBURb1N9!ar#O$w)H_Sk6T-sMYeG+;q zl)Y19Ig(pw0EaakK4Vs+F}1L$Fzt>uE2AFS(v^83UQJ{(9kS$rPNe;<`l37wA5QB259LzWo88EkgaT<6|ghyv!u5_o;tV*B2JC!Am2jEd<2hW01Nd-;|r?s2RL$Kx#x6BV=PM zp}#%R(0d)V&i)k$MFU^&YB7qSOjV@nzIm&_!`^Ql_X7Cg=l3h7y>+S^e|@N~sKHGl zBMcmW0G@X17(wD>g1)ce-t(yh0>t$U+doAEIq;}q=*$29+|SF5d;$>xcUmiQT6(> zcfE9EoUi?d5_S=i<0WDjKSe(~tI~P5mlKb-DTVau$NfD5&z(?1`dh*~^3ujK5)%*; za0fwCaTskF3RN@r;2X4SQ9q1|(&aLT0mY*+Ke+cE1Mgzfor^7NvV@DLbj|m! zUJlbn0K=-AOKZPIZBnHtUO0ZL`b7TX{69Xt$bb9zwl>2qOL_WQC8s6(y)4M9Re?b? z@jpKOFR#^;<9~bmmX`d-BG~Ic*1tZhh6exT2z-(zdNo1owvj>g=Ga1ZfQcf{RgK}Q zGNLR&^YD`s*(o_`OMKiUx;}Pe(U`K5_#!Xsg_T6KRU6S6V0>iAcj(zLwu`liJzIO3*H_03qIhI3%@@_l+~M4kMbeyudQm)Zf-)2e{OmNe%q<~F81yAbRde;hWhP^hj-QsPU%{q zIZpbU`e_rjBz%@z{;g)H5?fMYXTL|~EWzu^6I!T63&3ffzw9>RfxuI$u`W93-`fhH zaKSsg#0U$M3M1amr9?X(OUm7_X=@9{f9>M``_F8NBo#6--4Z~=1VPkSDLpd^q;-ED zGiQZghs)P(l)a3xq$ye88K&8#B7_d^ihUvYxOIztlh`~Jv=&bD##(Y~W3<>gSu-Y-sIFNh)} z#Z{;126^i%)BvuM!Ip>!`}fH>vzbX49FfEPJBZhBOTjMUv1 zrzvCtRge4ks2L_zHs!>ffkH(U4zCSKfWl>{ByP}&gJ;~Q>^o}i`zM(ww=dGPin2=m zqZa$`7Wuz_t3`=eHZ=%YMTWh~VdeU;`Q5Djt#&AH*-GO`IIoE8;=(g4T0&nGm{_uI zqX{mJv>BR@zkAcEeJH?N?!qzjc6sspm*WHQDc{y zVW7||JkgpcE>*iw_zdPg$$r#91KYBFF;G?)OdQ|d)Y)lUM);~3$EicdT~o3C|7&+2 zOF?WbJ*X98Aw*QEYnVkdN`J>Ja+F)I5O8YF@H5Qdmi}ookwM?-!$6sq088EYI$f$e z$&?8}ZE3@2Cyq}b*l;t*h)x95Q?YYt3iD;oTV*?tvy+sYDv|AKrbU&b$}J~3o6}yz z^GGqZC-RzLJeNEjj-UenZtI-&_lA+)?veP4*V=>X%l{~Ji;(V-S<|~>$~n9oS5;a1;{N3$hm<)xI*Pr{wmPE<=w<&XnYRPF zy-r%xMnaE1l>ZK+!Vdhw1nm44NoORP*47^48!CLYdub_q_B6$pa+Tt5;<`?&o1b%N zYlkgbkPvwg&+jH}7~1hB<(Hw&KZT)_P_BykrErK1DhI7NN$c@Ed3&F&GaMen-CaJh z^%3NK%*xY*zDH@n{Um@^Kw|%eiU=G`#ZUtt`)i!=PX+@ zj7=U~jm#1`Ycv?C(c{{q`*D)pNOmc)L&xeR9P=7W6#lnR1V^W9P;s71b=C0{6e=+WUvla(b z8g}#$Nn|wp%!95&J?n=pb$gZmEumY_6uw*+4y_bx_2I?Ueo|?#*Z4OUz?%j|3~90} z2P(N)LvFgQog5LQE;kfrm>nv@d25A8kW&-xt!3`ghFbv{O&O%FM2Pl*p?F`#%)1qE z&r7j#^bflisvr~k63R&(umpY49v7-}{A!K5$4-#ayfk-MY`DHHk*^j&Any7@J3avb znMn8~o1s4lR3)Agry=47RL%V8#PM4L)abwb5{~GRM!{tX@~&roUI}cjxA(A%!ZVjk z!kqITF$oF0OwHY;0eh%@j*Mj{id31cUOvVM?DsO6UBj*m%EY5t>yJ>EtohPtXzj0y z5?9G;=iU=`khB4Rce?x|FHwZo4 z7M+2K3nvjDOmbj$9+b=YH z=EZ^fE|{+%6b>`zm5^J438!zPpS+HJMoQXQqdq)F(3>!040&}7Vd zKNak8;`B&t@MSk?Haiotvl3W|Gzni@mzf@XD&F1seg4Jf4h6<#g-6N#gbx;{{(S%s z6FcrX_-lvU?`tSIY|WOy-;rV7SXj*q#?rmE8dnHSj-kNqN&L!T;@@nLa6itsX8*tV zSN}DDqnx@IWFNdaRw3+bAiAW`RWQ=y5!v)PewEElu0Me!%_j=0d;dr1R?qoQL&~Zf z;zoWY$9^?s*oo2r5&9%QmU*4%aK9=L(w(7mNI$c*3|-*R-nsCi)q1$RWbO>-4hux` zZY)~Zit@bNIv4B$z5Yfj&(&pl&lFx5C??U!t+F9lpTrp4Na9N>Uzwd{IkG zbG9p3d8}(Zu zI3mOGf@Y1^bkiKv2oqQRG?hRc@vNOhFGkv>z$SI(#4cPUlUOo*y&p$e{Bx@%V)A1l zSxzGOTqbu-x_ovrHR()hPYIj!o=FAO%&3=TU@j+XdcntMIhMn#KtB}N&&B_1$;S97 zCWfZT>4Jwu12XBWShCs0t}y!3vf8NU_pv9w!#bTwEXEeO-tiRZm#8MS+v!v{A}1ma zceh_fB>Rv0)=69*F(1XgbIBK}sgh;rhZpeALbey;WKs}+))44brP=-LTMeEb{FPD# z#F`B1V;4#xknY*aIJ3j?7wC}ho)s^6F4f%GS!k5kC-FqZ5?imQ#s&;gnR}S!3{~`~ zH_X%|3NKD)dc_OYkO$0%aoz|zbzgy zms57Y^vT9_P8Np?U_I;#m3fvfzFY;Xhghn;gUdnTGncSkSJ{)d^*jJ#(KVw+tWRX+ z6giUjQwEpn`o(U&)(a(=7CI%cHxvFuwZUuca8+P2JH_UQEo#TpMG&u`4_}kZwdR_B z9MUz%e%V_IY4V@)3349P0SD4W+!Dt~PiTSd?$Vyb2L-74?LWVHZ*pO`w@M#n+xSL= z@vC5&nI9Jm)(3L8icI&b@+by!>jq+o&fmzVW`Q8c+w=WMDSP9cR_ZJ)VOUeEero09 ze*2)b7A1judnOy0%X$WtOvfy;2&piSDGC-<=-A}PPrT&mSK5o13dfuf;x+vz>+`#jgWL7&|A zobNC=Q>a&awkwvv5Q3)+AHUql?&iL<|MQuTFBn&vt-dE>13#6R+dSp#Q6r^3UW}M= z{qxhz^-@KV+XHRFO*&9onEt_cr#6HJyZGVY&0yxUjk_0Lllz%Ifprhcy$|b6kHiKCUiV6{YO6BwO&`i^Awg5A zo;!<2B@KSpN*lgYNu{-<@E>~wW^>H#^bIx+w9a_yfd~!MDt|$h@B?^i5xe^)@mq(K zIm{JLkhnEUoQuPg`*mAd^?V6adLDxph4T)J>TAPm{_hLlrdS1-WBt+S0<5LMnAu41 z8Rv|aAEU+T4^=qs)4|O5RJ*=g@frsMY*cu(`$f%GpxOIX3Eb~1>(-5DCnl*s(H(f> z;labtYO_JJaC}QHGUEeatLjpC^HkK?1N307 z<7^NWpS3)?xmr*5Z_+NQX~eUzwIY93DqI*9)24z9u>&{-5xMr<<67-aVB9XOE84D} zrd1zy_Z2DOw=LMXyFb1~H$8DMJ~e^!Lpe5L|5&;Doqc~6OD}M!1HtYWtC!9TTR$TT z5$v3YAL}M_oxx&Cc|iz+x%&c~3dqPC|JwG%I3b-9-30g~1*vP?9IS<{gxk>+U)DR# zwy7>On1_~4iDn(1D`WGB8ejiM&zW<@He$^>n-A!?8wG2H2- zTBmaFN@)uD;zS`sp;{G`?#qXm>n5CHwRP{X*xu`b(J$elIgfYTfbR z#^dtP4c?bs@{s%?oH0&n=?izW@v{ieqla+p08bo-lDpy14XS;4{+XM;e9GIKb+&p1 z5-edLD;vz=9@>+JBV0>&T2f&`HC~){j!y9<;Jt*x?I|5awsQ+y(KtQX6KIFGzVcZ5 zjOg|$y*`8z#U$ZZv3u6$ol!zY1wOsUqwfTYAln#Nk4Yc9@MQKNo2BYXFTWVjRi5RR zxJ2@I88m+T5Rz*qJW9fnT(j3%V$w@R>FPCiz>3}%72eMnBh=q<@HSFWNxJh<_W9Rr z_%kD`SF!OH;d?V4 z5qiB%><*MojQsMI0bMm{dO!ME`BqrR@qlyY)?W%O55o2#cYP0sMcW!>u+CMK6*X(7 zjc>oDe~G|%ak+ITcQ;kz+Ale|w zQ}SctwJ#BGG<5cReHgs$1SWqyWUGErTVQUF_k&@m3=ehm;f^GlX|56qOkUTT%HeBc zRUS*!SIMw!3}c4}#r}Kz+7g)O4okV{ai#lH#{@uwRd5E=)_NqBMI$(u-jmBm2e_}k zMOT|20(@l}%G?bsWHNoYp$V#67rzJBlV;q9^Q@xJ9l-|(3Z7-2Ci2CN28$81g;%qP zhl+Nym=Y09$#@8$b@Kbyq=d^X)U)=F2g0y@)S_;+Uws1`F(R_p8B%wFeavZhojy5r zHbeb{f7#QHf&h=?h5!vkAwt`chO@@8(M61I|FY*HC_z#!%}A!dI6Grw8rLW|hnEL&rqyp9uG$#l zVs9&H{l-(snIc7{eFWx;=&F$San?|G6KHCc{@pQ5kY35D5a?9U5?g!iDLvcH+CuRl z=>y`Ts@D4(&?@OW!nHGDf;&Wz`uK@kzQ>%M*?Y(bV!8P&!X(R`w60LM50;0NKtl3K z$ewWRANJBcOnl+-jn?qnZOyHXz)4cNYZ9%Sg016i9k+Ia-HjBobhOA^d2sFO6dk38 z8pQO%4^H+M?=VTFF1F7v@>mG8T)$t$z1;2Uci05pBX17;h(7q3N3%w8CXUr*d&A`x zw`JoN(}AWqsO@n(U4^(=+AylbI0Ci;J(iS^MrX}llU8%mr=J_WN%=zPO?=IZl4Gt} z@7`GDe7>^RIDhg)rXT;XCPGKaMqWL<0d}h$0Yj+r!wlO3+G|&`vA?2gBJT;~lXbz` z2{>y{;Rx?F&MidP%7tf(=@2TP`$3aCBb_FnM6ejy|YZr9KkGOU|WN3c3WDodwolj7dN2*gt0* zrI2EY$u>cTf8ae+Vgd@>Ic#*zm_U2oA6BQ7qSY=Pc%7cvpI0t|!CW}%)5TNtX;RH8 z_1YWgWZ{Kt)Z3oHOT51MQjNjEn!d(c=N@2nC(Csw!+SM%$Tbes`~lYW`nfeqc4r`R z|NC=!K$mRN3)ic+W_p0utKsz=Yd-!eB{@$OCD~mD6Sw(vDfKLP-hFZSks+<#F4rER zS&_F`U^)@B@;$xCtGh{uWUrZ1PjY+I`c zdC)gMl$-Z`9K7>sCKrue===$tf9eQ9`-XyvF&+TVvx;z+c0SNy3qA0k7Fq-~vYN;| z*gU?`)`=^&X%ovB(P7UFxt=7N=QC(w>=kWoh1a2vT^Dp7+!5>DF_vc6oKj|g&2<0U5Z?o>= ztr&!cQV-KFVoz}nG+q=?nUGcD!8)Ye40e@R!o`?D3FoO_=St15mg9OU9w#35Q#IVQ zi8Ki7-M5lA%6%@*e(1e06hn~-B+om}M{pD1L-=qpsOu~>%E0DNv~+?LLT&yUYf8Eo zIopU}0z-e0zM% ziXs2u@vx^+6=r_o&k~AzPBHR>#p3Aowx=0zX6+geI;5%SG%ioEzg(=3;1HFWRY|i< z29Ov=Bw&zR-$XG!-F7Yag@%~JzI3-;TC%nvZ>_afP5P^nDO=qh9#N2bm1LUERz0vb z97N-&g$r6vm8h`PY|LtEEMN4=&cMnC^J`nO0XGcNV}_bT@KW=_O8UPBv;(&p0OYPm zP%^>}xzO_qKg)K<{fp5e(#5oaZ>wr$KONyX^Ip$VFV6}7@}=x^wtyRiTkjKW?v|1< zx9IcRQY(?^SYul(@4i%?4lgSM^5D~3-@W|eKY?ZG%uG$tA1E)xvE_ym-013Q!=QXP z(*90&=*{lm8WSaNpvlgbDtVL?OQnt!D-%8L4wpWtbuXx`JGPigl6zBnEk=AKQ_*o# zpjal(Dk)L+h6z19YT_He+M{-Q4*Qxitx__XzD1?vd@h>6FmbO{Ka+jZxRDzOA|6>N z^ubKEP;y`C&xxrc;&*fq9ifE>*eLIRMyi8)1p<1B+D$jDi05_H>!4JxDTkhq+^OAp zGCo1;#Bd~Wddf|&UzH+UF-iEs^kaelSd2-RqxZfJsy^hIO z{kdwMkNNlL^r?luDv!V0$`(KCsq14u8n-EbNHy#EnCpK04Ab07Q_`G{%@I}A}rtIZ*JKWnu^v}SzSdJ}wKaj;Rt@qTTgPGfA*wWMRwQZIEY+DBEPa*FDa`Kmo2!AoaO zx^ZaB(z}L!*n{)U9;@U046{c=-&U0$UYkqrm3J1|-j}D>Ul=gbv)TY06S6;KgFB&q zdTybV_t<|$OOy~bY;x_^pE|<2#ry*Fo8v~rgmYAO>!zS?<7aL}Jt0fT zt0izSw0#%GSR>U@Mclj4ae+99vC(WOerubK*=1w(I-@aZPH)?e<4BUav{A7vb~OO9 zNzu}HPT438_#ps5zD~TP==TP4v%0M4<=yRLp3@ZTb{6Ph6x}h#_cr%Iht5|MapAJa zlA!)h%)@$(=-ZpS1}WxxDZ}LuM_OlV*^gE-p|+F-q0Mu-=W#cz?^=+rJ)>6m^nw!IVke*n5_YNMH5zc3O4aqw zc_BeBfR|TawnawhAllkCNGJC{sV{&2C%5re_aS+``Ll>{@$dq9rRATvgcmGl>;|?k zwp}lqE>ZFA`TBo!#+C2=v5e`y8QJ42O4?m=TYT9rB$~!w(=F%slgIvv z`_gft*ZLHqR`S8XW2)_2R0cYPG-wqu(%|(VPo+{U9Hq;4W-d=|q5$jfB<=tC(Q+3M zWY36S3SgVdxk!EDcCwM>=53{lXW{HQw;Z9F*m6uytCcHxc7=!8CQ#Y|r4I22>D2@d z;Scp?wQ-XJo*8g(K-zFJx3|t;Q?EpYw~FQ5NbK7EVvZ%|2AG(I5PkQ>^a&>4)L_ZR zWY&GpkN#q;AXtVx2Xlay`t$Bd0V`2YZmP0Yo*)6xejCk#iTs!krUQ~5#a4h^RhIn2m##$LX_5^*`A|IEo(%IX%Df@3{vC;nBfUoO@pZhH zRKoFyzL{Z(w1l{Q6|m1wLI5cJ^XA@S?}c9}Vx`O9)!kgI@(vjL=h|og3{Xm~h3uJE ze0FBk=4!AXE(y=WCb=HYJ%-j|*72x5mh-SzvLqo7)#V<)S6^83ZE7U4BR#q~T?x;s zo?7^XVl(hlF$53Me$sgst@DEvDb7=5CbBso*tziZP8IEFHa3XZVemGw8otH-X@Tj2 z$omOoG$OZgYeruL{Ize|;f*%XLpg6Z$V6THl~&gXSXGz7bku%{^bb6hrO3w;)nu8xqKG@`Z){3U;D@UgU)a{oiB&I<=+Z{Z)yl9mgom{NJ zT11ZhxUJnWsjNLA6cm+F*w*p0wajas7QAb!a85s;h_K)^My)+L<6EOwnJ1+U1K=kh z=WwZ51S2?9D$Fqny}``NWB+Tmn7yfi;g6)>p_U_>dM+_5Li!4#|G`Bt0@8=pE=4rV-0f8}&cTvLYO9=Ia0#?e zWBeJKzdaW>e9cNpz2B?_9ttJjsjv@~IShw(3!z@;G^$=>iD^}cxvz})U1#ruwysv@ z2M^pr9m`!8c~xYe)2VM!7dPzPm^#C!SeP;RTFyq_9NUmuu$6FjIQrA0Cmf%*3-i-v zap(RRy*4)I?i|k8WfC#}GNV(p7jpzx(vMc$aX}0=Ov}yiyHP^8o0EiB*A<;*T>=1_ zpC=7N-Qq9Z_4-{d?%FkVhu<968Wj&Lc(ZLCceU$ycbrpAM@BHy0k-zaYouQ;=a6Un z2T|6XHPXSa<>Eq#l~Iy#w96buab3vsO;dipl|&$|!JI819+@iKh4WXWvc4Bi%3*_z zpP69kjO=L{gqb_y?pJ4jL`^Md$FlUI z{4aP#L_U-ZM{f7VkN%oUcNY|UpJ$~@TVwkgb&}^W+@gMl9@#rP$l*!C?|eFNP%nE= z%xmZe@%vFp_8eA54Y%*5c%1@x1PqUptqwpgom((#n6De3XEtnY6JH^ft&?tOYMvke z3lVIe=+0(`WzloPrn4_kJtfw+lZ0DsT6>>uTbJMQQS9#ws}*1_m=0^?Kkl4Ri%$)s zYqA(n5dr{p-X0w$|1Vv5x}=+Z7foe0-RnJwza&m9Wwc_jr?YKzqJi>Yg_)@dB`qJur?Q&EHL%iH#}ou?*6#ww?UozIXucudpxRU| zPsLeC^_+vk%l`K1rw=K8xayozjSN^jnYY$k{VPy#_VDw4>IATD05L<(jIP~5udlZvvv{v|t@CWsLd|iR*RZyih8g4$?Fo z@U3m?kgDnV-(&;AMhjy%$QPcHkxe19E?Ck&4`to%4t>hrkW@8oUSU4{L1?*;dEVwW zi31?`EbvZ7;&KZ*Srz|)TeMEGt6Q%vn#{mMHTAysXo>xc3kxRItU?=l2P;i-sT>Y| zcxr1G+^eOH3C22)e>?H4mwpQ+NQ9iK#1cYV^ywVl|I{<)XQclYRK#nO*bYbWr0j>RGVUK=;IAx3V`RzB7By8t4IxSG5^h*j=Gz@mYVr+G8xp(@4a zJ_0>)d$~RPP`u%Vf$2Yry&iSHl|_J5zex6H$4T~3DK>Wt-mEu7MD36Bsxr@>K(ybL zTD_AswOt;~{z6G0)DbP0av@MSkv+AUr%j>wmw-2I^zhY4wih5EKF(bAx9=^sCqjNAcHTT%PB1v=7O51x-69|! zuUO)&)nF`vcZWC}$z_%6rLcyYIm|s2=#lanC!^QO7dDiAs>gS0y*^v`n#^5hEP_^(Hw?H>FtdJh-V^Bzej&#PkA7W6CHCHc6b zw44A{@2(Lwx(jOIErTspUbFd{LAnbDWzWV>buEz@l)1HQei+DC4B3{V*E+p3#pHSy z8g7Na2qO-M7NQFE(4<;CueZO^2^%5G{Lnmy5r_hO*v_=UxO{~vmk8@;!V{CG#g~BO zNA;f@&A6mR-b6zozq^%mh5rI1e=oPEKQ(Y+GJyJQrxVl(palIrPq-rVVd4s&CpXzf z+38IMtEPvW?R`~2wS^c(H5!1Kxpb8{7Z(t`!lsvJFDI%n7H|Ap_}ibm9NC^#y@ zuQ&37GoBOU{Ehac{@gxxd3;FQq(_=JJ{h&t*7uo#<;V^2WR0pv6MCd1)g>G|(SQME!wuY#0C5f_qm*k8Qf9ZV-Y}cjkGU&^;eaOd^j&U~mKgr|)M?Ar={|_!XDb#XgCcL<= zX1;3w$@}%gE^O4E_irTwdC)`B^{W^oa|&njNru=QK{eZLk{Y<(XFM={aHk@-kc7u_ zvYaibI;C{E!o2@M^O?Es#&(|UKmjH2dV;qc!l6d0RXQ3s~4s@OaE#nL7hD)EuertS3IYMlEg@C@BH zyO_p4H!tH;7kZgPn`6=Qb8b`NK4zp|d#18M8Mmt#_ZL{f3!~{5xN2X9JVD%fo?oQ3 z#NAIX=;=T0Qcpy~{b?X`ru|d*whan|8R&5F`tTh&go*e8ApOI4T(S3NCC{!X#3a+F zlIpyQnvy|v&?@wJbpX?&g|80`e_YQwhlQA+wHdwMilhuTA6%Cse7K#NnVDbcrPrfVYNYLqJeV4v^N`m3 zQ@^XD4Qlld=H`A@A9#yo__o^3`?o9|2QCm?j%>GIzk2oRz|*O>cgCeZ3EiKTbkS=| znLGAkm%)oTFK?%>oM2!jEF;}wdBqRowA~%sy_l*TW8gGbpHn5w1W5Mh0 za=k1ZaX6tHVeffC@C zKz>Z;RpaoRVWISC6AsZO()^iU=a+AEpM|~Qw(|L=+cL1l`U0JIh?x&w`#k(O<}jV6 z+g_7NRo>4D{B$QQ7j?>hS)%-L<#-(0_Q<)EFlG2U<*)cu>sa*kO5$e?LsZ0GOnyDK)*SECR6<38;lefo>D zaR3F}0sDf;YqwZ=S2IEsv9ErbjbV60br*dtd#|(6w~m84W@&TJqEekq9qD!dXl5}j zVCTi|vA=&cSpuuc!MFI+NH|UXlGxW^R7rVKySK9@lI20D-kWRX~b%#Y7 zKTAy(!ZVP{xZRww#B?awaU+VqFK4Mnm|75PB*GdHW z?0UHy+NI+4(|WLk$AZG;hbfnO9&|Y2>s2h}tl`P#&oCQXn=*i4D&)L?O@sE)7aY%+ z`*8@D+`4AF2T=^#@=u8L1Y*5sCj3KXxlL@7g80OzJBz6i1xzciP)}%_|3ALo0<5X{ zfBaPukXDe85sCuRAd(6bK|m>`yL-UsW)qN*6p&6uK)O3djs~gGIl4Q?c8C7re($~i zd!C2$Ye$0*X?<9N8hddaZrABa?>oQ}oa$Ps>yW zD=h!)=?*ZYkTL`LT&CE423gDeu`P|Qx$2Yl#LtD0osncbj8K#q_QhJ`BaxcVdSanu z7_l^h^g$EH=y_k~X+er5=pZjA$x)=vk^n{Mk?B0>Y+* zNUL-aCuHV??a|`n8Boe{nP39L`(5qkyK2xF62&NTyg7Nb1;fdo?b7CjbZtu~jC>_+ z0(1`DAE!>bR#!mq=ra&EB8m6bPC)wm(^uqj_wsMY6l82`BMqvfN-BlY0lA|#3inT$ z%eeecIJmqp+R(Z!pnF#S-Mvblf=EE1ME% zuTLFVVXa`hrZSvPpd!ZfrcYQ5hs*1olSApEI-V-ccYUpY`Sq?Q*M(fp!5$3OT#ih# zZworJ|M)DuUg25^)qVs$r>~a3piD*tP++_tc`f&wPE{NxZ@t`=O4pl?6Zw(HZrhXC zU%(7NxzWX)5FxJieh_N%d5Mnb!c0rv=k#;ekJOgl778L`8OWG;TX6k^u5N2J{}Nuu z(DP#!ypk`%j1smYKPujmD`x+T2G(fzJTci`pIs-%k;j|WzEf(RBDVUFv=?7?e`R*h zvH$!nXUS?m#u4+Idq%W`br5>+3J-YnbR>?&a;ludB4Q@C5ui!ch{9EZ55#}C*7@MZoteRD%;1cFmf-~M@MYC*t?P19^!xt=8I;dv`LT%U^$tWL0?L57tb(;+E{&umY-T;><7{?8x zzs84R=Dyo;k+j!2oF*utuDu=@%=s{lhZ*Et*LRWrwmcc^Lo>v!svW#S5Hf1$AR0Va z&mu)rbnw&Kj|?gd_xZuRwpI@myck*&pDJ1GVL9fF-u&1ROV^;zwVtAu)yqI4dI;c! z8f`X&p@L|5jfk`G;sbG56^T=}{A#`kk>;@+cK7Mbudn!ZI%iu2jHQmC!d^vwnagK$L zt3h%vLdK)`!Bq4829mxYhpAM9%4?qUI5OaMz!%&Q>O;6%o4bjeExrA#5nx?3!x&Y9 zLdkm8kq8O_X5;3!A}H2-`DNU1T2YW1b>+n%%1d8=DLI#{9^CPxLn3GxXiJnFd}iKd zwBuno!1TeqvGdnEjiG#<*zZrUCJw*6y2>S)wbI`Ac@^1A70jvgoyQXT$z7omErh$m zt0adEqTja^ciWlWTvo|%aoWv!vdmtw#m^m5a2)?dvviS~ZAB81=tb^Ir`MQ`tPv%a zm7-3VSGkt_J^Ux@HCQ9Wc*BLzYOAxbQ58xE898@?^cs3+Lw8qOZx|h$4X(@z>k*qL zCV5r8@=Y-=S|MN=)sRxnGKlQRF+VJ33~@d*rer%`wNn&+0(Z(RUinS5X9~rcFjj|N z)5WLyFoO%9`@F5_ox(kOz72T^+jCQOpZjEdO*dD&!Y(~45Vdl$Kz-}K1dGKz+-v0m zAncy6k8Cz|$;M=~WS#DXua81YU{IcC#r<(j4=JOjddp0=_cnl4o(TO#IEVEu**kPz@TBFEy#LCa?jr`JxiyJScle1 zmdUH!1u$OM5=FI};^GBlj9k@TMdY$KjnM$!k8H2v==&!Q%Lsjr=1Q zZp&*H3TizOeq?&`wh)nzM^`kS+)I!*x>T8K)Ju#v|Ht3_6(EjM-Y~QN8S|)I?$*#f zhd=PgG=MKq|Ht47{Bfdbyv4=CJ1vXu-_xi_9s}&(@6YlKmKPa{U+tnTxINLzX_rWo z0==dIvUgq*h9)+Nkh__-!RmxnMgj}ZSYHf(KHy+w4P`gEcCI)mPVTD7j!2G}`F8S zXXQd(@9t9J-uMgXWlkSHFJIEJXatDCBbbBKQeAgF6Xdx+UiKHFuYlbh#fr~Kmg%0X(| z7psTeW`p-(1=`8ae%$2{uM0O4W5`y4HElPj&;sHHR-sPn$~B1>Yp*>x_4F;}2KDMj zAUV=CTU2~rtC0nqzkzENswgKqv0^N*0=Orz8yWO)Q82NLve*H8%Ou-zu5GTiS;3=} zlww7AZYR{Qy;tX6L*BD`o=qlJh0_xvI9G$TfTej1^g5xVTvOCtr=Qe13onW>5q;zN z84|C84QJ|{YyAR<7}4RidJxE>s%O*pclD`We=27cUs@SH@4F62x9}PKsjIe16~z@= zFZig%#kNe;_Wnnbx0(9C$6H#6;yiDw#eWG;Gqx>7aJ&ckX;&=T?vWQ-Zk=a={CA|F z`Hu@f(O&7!hD+;(YH9O+WxC3zw#4Oy=c9ELyT${z!rOJ8#(K3eHAlIASzPERR^G6N zv5hdD;SbF)ZvmNM?v(hab^b@`4BeR);%^r(y?Q^MFpcw|jpN>Ah?W859NT4kb)$!YI;PiH49-IU4z@s|PUyme@1jJr$!d$o}O_6H{MAeiB7C8bVY zM{aTX(r95i@F)V-WhamQTbh4fa#V2CA&CC^qZiMFMaFw^?4uxI&b?AuH_Zzg# zJmN^uDGbLZtLEOZlL*kq#sRC|<3{G+{@_T>e*_FY5lffV`-$ySGaEJWW?%-~H56pX zq%2`ndXT|ld!M#ridU0Riv64=ewa7j49M!ulR~K(FC7=+Vcj+iI#22xmpbzwL~2P2?rZuIRCJx+KtBfAz)*H(8$3 z!de!rBYktoHaZI2|Gw7<8?}wf`?Z#2qvY8%ra#oldeK4BIdBpQ#K0(!R0JRYEB(~@5oE=PfGaEjU4I4a+1RY}o!|qtJHc z{9T(DFB^&$EW|G_*aPV{|4v(b(XcIh+H*qGj51_B>ybWx`ixL6vCwy z3W}+8Q7|>@-mK3BIkj2o8;9f zJ?v9uYQ*?YG3&$Z#mf>rOe;^* z6n;FE9cc9w_ls8bhDA1Ko$r(Qna)-)H81F}pi4N8))v}fw4PvkJ}%w!Fj=;5tzLx!@qVC;W+4$ZM@9f?Dqop}U@wsz7<`LPlwYLS|4;J0!-%H~b(Uk*#{?v?$A>gT`G> zhkVB(1{{A2+lGOdMTYP?DPzgbSycagyfQ9(gI?sE7gXX!hp(--gC#3 zeDAVDHUu?KyMsK^%C@(uHOPoeqqe|X%WG@=b~82KH+H70m9*^8sEe`bkN-xcyv}WpL7(SZABP={ zHth(ZT$h=@8KBMjb?Tp@f-~BuaXNg}GrA-F6D?S7^K?uaxDv~4z7dSz(ZAeg8`xiN zbL9=Uc^u1a7Qu3xZ}Vasf>h10iFuuxUL3BlorTlz8Ha+rj{1dE?7$NxPa5+t{a(4>$*bv&G9?*0Iy(#81Uj-OCh zL0)k#QiAkKNJPr6U1p}Bcx|HS#MMXiB`mt8TReD4S=APnrvfvhYoNfYdV)?trbW+| z$&BsdgI5%)bK$4GQ_Cwk0(;6OBk~b7=ayjxh;cxO<>x6f!>g?-8fYq_xRj3MUh@8@ z5A=hEoUNW+u!Hr#ax$v&PNfDp@q?INySuk!E3rmjW&*1tk`rv3oHrcJVhb!}8b{Cm zftzto46qE{KQ!CxSpIUc$;U~D{5_M8Lu(SM{ne%B@C>xBbra^(i3_nc`lpYCnmCzj zpTh_SpB4v8f6joM0P~t6eABRRPk?GJ5iP6LD#<)2YaSVVAF*s_Ct^WZ>XdgbaL~W* zCEm@KhU<|)d;-(V`5^tEV@q-Swsq~3dz3Wcv){5G#qV=m7JQBr1 zIN~Pi8$7BJqdE@ zXB-3+5ut#BmTbJ#Oy7Cl54N(8e2|0pRq06aIPaOVYJAh?z@n?79UUEMgzRS22h-Ej z4Z;htiIkh;-}OjEzw1?*Q8HgF$E&J&VV^LX{Ss}u*cy~?TCZ29`^ju;>cQCma-H|C z{~O{we?@j;MQk@|1H_gB+oavF!Lc9x7uUJzf4I&*|HE~@{2#9KNh9Wl`TP$C{a+Wo zxqjqdWjl@Na!p+b;miGG$fFOq3sD)V86s>zq?@;zeJFn7L8J`2?Nv=eG7Yz?8pI3P z+3dPz(;73qC)i;3UQ^ED&MC;}N&NOHQ(`G+flH&kW2LSxZ9A<4WA5Z`xO;y-77{}fr&+t0)tU2VN!>D!Eh$hQu+vZ;NJ@wKE-XCcL#&i`iP zXK%kb^&h|e|KrWCIEUu^`=CM+|IDnVrgH~fjQWdro7y_ov~0eMhdFg-?1Scvaf%R| zChCta*Pp@5#(MVGa`(|LdOWClw|su#oN-BE7RB6-yq%>4;T+exARp~CxzftT^V*f~ zqa>1jg6GJ?>m)up=Yf_*8dgkPVdu7Xs7ds773AK;dAGqh*;`ZbY#V{&;DlY-q@r6x8o#vW2CP5BySY2)Bq5N z>*}9~+8X*;Qi&jI^ITMBRdyCk7%_ZmWKb+!SdB|DM-5*7vvgcO`(UGtaqUbA`i z(dehW5;mc9!`J>F!JEc`Un<+f4sgcNCZ;{=?@tjswquptd`K=(7%r#;az15@WjBX1 z^TZ{Wd0(CGXu%*pYNRp2vV|iRRw{AWPC=_^BsQBckOXk&TYCCnjRR6SyBa(%ZdQA7 zw5D;h0AP<_1DkV=Uha*@UL?QIuVN@U)bC&G{_8bf716k&-p3_0jurL1j~nUqH{Gu% z88&4kqPg{o3~z+Oy>QH11$IqN7(^Aj#s%@ERUm52%|YpPQ61U_*mEK?A~Zyq>7z^Ynqjs=vJd zdMb@r4+{1FQ=&13$k(1O5PC+-)9KRaqK(6%WhzX3*I$Ex2FbPZwTmk*5^Ner4)+Z%6v|6#q^Rsr|jv?OW=Dwh=XD9>k&t3N<&qIlA ze$|0_4D+newK+< zE=LjGE>6(_#xHFiJB5_5i;6bzMsJTfNLzSVAndMO^H}dTn&e^?6a!9MQ~5et1eGoJ7hiB#fM?u(!!&d@|E*=WY=rLl^|C0(li%aD!vftC1h z0&E?u7}Sl{U;EWqMa$F=%M+Vy`IN3s14u6!k)x)@!k-ckL9tVs_CGO-i~ITt6T448 zwsf`@T}Hz&M;r*7o#{q*>cAASFg;pTy_k1W)3v!0UW}pk4ZXbJ|D+c zI51@`flI0phh^0OacOKOo^43y#U6!;f@2Bg3Y%s_&&nQinbD3>f&fG{d_Au>T8j7wM z`fa&i>euq?uDtK}&E~36wiz=pGcZMVV%bMgw7rb5=lhTFWk{oL0b`hgrmT~8iPI6p z$abM$+A)TNYi#!M038Wyd^IUxKuaI0Eb~0q31Md{T=>2Q_Kk|m(u^t7CZ^w!>!EHMWF-`s~nU{ec{a?<-lxWzcjP5e}L_;_RF z5wGE`TO-*D`HKi_F+kS`&HY&$K}~y6#)19Dd=YGJ)Uf50%PmQ--TtPl-8S(n(qBjM z)FYTOvgZZ6w&QoKZ1EgVYc-rM5+&CsU&g)IsRKe=NjlToP56(r&NoS3JD)Dj)Pe=# zZqH#S9RjJFmhQYuwf5c{N_|Dv+x1|bOV{ql zv$I`Sk>34Ry>ggm{y&aNe03e|S#)L!>yi@=M_P`_T zNk&DHGA^+)z_(AD&8>-Y?rST19w2Lm^!~owv6x)oib$o2i~FzR7{t zQ}CDCU+3z45M&eiv0WusU3UC^l=2$kZ5F>VYN2o{OG z^&aKauIWfllz2XOHdD2i)}Eg)Hg>7`@Wsx`_<7UBQiW*JNThY{d>d7iC`e~Mz2fSc zHybz-x*f<;Tg<7|0oSnj4!AWS{+mbRI`3d!oDy~xnNfB&mP%F>;rt~7&?AsgI>nQYswR2%c$i87kSXShPD>AwoxV-qo_A6zf z$wd!S(#d>~WF#NT!*mS1TKDpZMlTeY>0_yWp%U7e36}sJSWv^`43ubLyC{{>JD-gEP1A98$ znG)Ds#P?IdJaH`5)WxI^A5C_>h6$usc87xWbhol+s%z!8`WU{~oP!huxoDEVqi+iq zev@i=PRF$snNPiPvUOkPZCeX2rr1O_?xCQdH;ReOYWV>Zu{8(kZ#KPJXPNn7o34QM z!%XRL|t)Thr8G;NpEh|^S1fgjgU`ab*RCxw7BZYr(+Gp zXt)74W5@5_VvD{olIctnN(-U=5wA$6S&>fO8cdP%ULAkqndp~!Jx?BR{{UAtczO)&c(JS`z6B=vSL1f zkAf8Wg`0amBCWlNo*~m?I>&PMn6HlEoZ(Ed=iS;q_WxxsmbP72j%I)rBmwi{?R>M- ze}1Uwl$|wvaf=hm*kc}a!Z`HHUH<`_#YKfopE?L~T{-NDbt;!RPexodmXGqqdgud^ z7+iV4VxF&4KdkO=QU;Bbd*IN%?E2*}owf~ybIEHKFuo$6EWH6ciUfwm?O2vsiDT%2 zarj_QKc#Ur{0K5~XAZhFh%#EgNjRznD9n`>5NF_yj+ND?cIKLUMk`^r zHupgL0m%g-V|-FkE9)+^$g6v=1N|=J3+H>U!7M_0(b6l-&XN6BcjrWIEudr zotz&&9gDTKRxkti$xko@B)Ts!qd* zt~9ytsi!!d3{{+Q;8+|_rO&F*Hhb)${Emzm=z%_dnXVtiAeAskGsznI>)INtC1e6e z7a^2Sd!-^Gcm`s4wdQP>Sn<7ez2&rrj;cQq-mU?+pScDf&M@Y!V%m8L#&xLo+|@bE#@^WNwo@bKo4@ty!%BZX4LjK6=?ej5RR zs(1+&+M65={{yVb%zD4y9qN>jQ||HaX{>9n4hHaQ=3#mVXTjeF9tbhE2cMQ4hLh2_ z4v~H75T7xo@K%C5p~p=)ovV!!MY$W*$Xxpe40rtYv~)KP>*f-(7B7BdHC#4sknXFLn0}zh zSySNas|f<(SewMrcUfuREY*Iex|AK&RS){DmJ6s@WU5KN$655#i?#`7qYNKpPx|>% zrPqZqK>N8e%nCap>toT-QM2y#Ov@9?Cd}mGkJloHKe-^T>qYMIF#Xtu*({=OU1oE? z>V?+=uM>dgG&nMJa`8coh7d6kSLz43c2Q?@5>lgqzS_@y)+tlXc_FAVyfJ^3)iXQX zsIkX0n}xVG_U;cw?1=Kw(s_4uh>EswKl3BQudg`mmdX37Ux1n88{ODKX$Op~G8t>P zujRC&k|_{ZBzadwGbPcz;&tD%NLIhaTs)0eX!=eGQ2(BLzrhjtLE6Wajf1vtF}|-h z>=LD{Zln94s6U?}3_4q%`Uw1%>G$qdwb;5`1x#=oOn`{HkLP2%nVDo|O z*1i|Rs|#VfgqrU^D^BTNZ}QD09&!QuE+Tm5z2ZQT+wz_V#&A6s!f~G(?vwMzsVlG+ zCLNpWd6zeQ(&8hq$DkphA+{G=@S_#L-3!%%`LO%c^m<%%oN4X7^&XEAu`NE{xnWw< zs~f90Y?3LfMq3SqJ1N?H>DK9*5ON%HY)T`Kre>{@_^&%1|$sHgaooXG4-|q!si9ch8dL@u|3x=zPi5ax^ANj_KhT+Q5 z72VIvENok}mlUv_+z5n8IS2ZY<9?MD1J)E9Bn4c$a{lnGjUgIiQqH+=oy7sL;kr*- zqZc8F;pZT+)MWQF?#cDRaoz+T5pc9*s{)?eQ$6hL4W#_sLi9jqoZ~?lf!q`PC#Dn^ z0VJJL`Sh$?ygJ0Bf^@VLcwaK3wudwS0wtAQUc4e(C>dxeG^X`Q_e~g4nw_ENXKrUsZv=wMD2^~Ka_MU(3V2?r z5W+?ztT8M&*oH&$G`NXwmJV`#WdkqF+c^DapLLyn6EESv62c;{Iajau9&TgXd`5-v zR&0;NpYq8qy78Yk3A^O!VSr7E=?fEc^`%!u4(C}l(Y>-Awn$-%ok4}jG?{!btK-Q; zN6phJgWh+7#g11g=2yf&-Cnmuld&A?@%`GX;P-Lcc+=KOw+cCX%0ZO(440W{Ivi`7 zS4xVCkd*Lc$k#U=#V+e3Lk#GjQuL*SBQ&bRq*erKumrAWA9kI3_VyQ z;h3R~DLCHp1LU5AW|yn{uJou6LxtXL9tEy|+n}OCTdgI#l9qGLe_qboJ6B7tBO1JV zUQo%!v*^(vT<&q9E+RI)@69H;9=)xPy7^Q%`{;gB_M@aMK%ndEFS`moMLd^-+0hDY zu^w&q{8@Pbd^a8cj`yoc{%Mns@9k(PS7Ff<`+&l6I!+T__?K8e+i$F=YhNME)bwIE z+j~({OrZ3wi|Ky+Ki@0mn>OAuBx$`_+-9ZmxPFG1kUoZ8ir4|2`4`8MR8f?Jz$<1z z;g9YpOs5_!^agodlmZ#Eat_f7Y4QqnTZ_AP&iA~8eFZbre8-2eHN(puIb6BWeOJ3E zLZld*Hyys1f2bwD`dAS#6h7be9qUS}1q&c6oJ5Da?3Q<^sY?_YS^im3qd0-vdJTm1 z%twg*m^>6Va3veizCKa;luuWkOHc9k8)**Lxhyd)JlW+EQ!EC%aD6y;Nbtte=0c`) zi;s&9Fwd^?uAZ`?GEAg$1=yZL|f zqi}7Q0#AU%4z?ftMYOCYZ<8a4PU{4NaagOZHlJdnUEj1w<)L^6DKEu|yuT*f;JWC`giMD0v9T566caLO#@bj$01zcmt!BTXln z+)rn3vCa1lO_FA6gjVWHsJ-ne#3dl3b~ayTy;Pavv^Q?^%wK;E*pJg$J%_sTbvGzV zJIA4ZsIeU*L@{WbV_k&q&Bp8xZvj8~{pkK-VgJ_4r;eMcOsxItWVPTn-%Nm$heH`V z`+xapWPwzLvqFZvEAh*= z6`v(D;ab84ZG~7wxlF3rwOF~5g6rE~-+Nvc(8%N!oa*D~6Qah=Nv1VaRcHzkwkk+h+YkZ?V$h~ zl1IXaMhuKe_tsp-6&4SY4c0oPYV)Ut)!Bsxtm+*ukmJM9S)j;CT;#-`kGBmkY^T>m zb_%Os41zixKEL$b8}oI;2!DIP!`V8GazgDin#o@;TjQZNq@`c;`)R0eXhcb|%VC!f zQSQ<(r8J*!1w}Y)iaMS8LG%O7nV43U$YqBqk;p@}A~X!UfUrB5G*~ympABXx25S57 z7ZV`s^+yr7bi@$`QR4>O%=?>a1t)RgX{kH2?A)K1!uf^)HRrX+lFJgnHC{IXE#VQO z4_-+S=Ac}KS=`q=$0sFMnWr_{S<=zO}sJeO1lQ7YI#^Sjb z{!9RiH5C~L-NM3iYql;ur6^n*ZvJ_nxI~>&RfkXA<~eHbFhpx;tl8J(&oeF=<5RqL zLOqaWAswLp$!j7OwbemT;Ly^|Fz_fyD0hPjn;JtF{>o{fTfsgAvbYkjQFfuh{qLvF z)!_sPJv8BKr_CO^^#}YGs}Z^odi3#i04xo{2Z|gpo;uA{5+&YQ}$+#kfs_0mQ@PWmWHpjkM-X&$qaHPGHgzXmkX^-mNREj0O%E(QAl_IqH0 zYS~6icW#0!F1v5xvo2ix^|~#s0c4W?yD5U65*T?8$(rAai{=+UmAC65N}I6`sLcHo}aEAuww$9-r*Fw z-^RjD2h9560^6gOIrgCvmD7dPQec%W3K{j9l@&o9tDcf3d-~8L^O4H0LisK+q0CPk z<^nlC^DP$#N6CK1;M75I4I{TSZV4vvE`%D~o+QBUzVtQN3i500>>)A-6r|?~LiQ)T z=z4dsemz#b7Jd}Ide04A(80o_2!P^FlxOt7D8QMW>WBhI(37;dRr<9~F9(E)o5S1s zdBQExmy@+mlaoO@R|aM0B-{)R0u)e(?ro5InzAUwM8v-=E6d{ufD|)K9)*LuiPLD;Uj#;}KM1V7%%^;SF$d=0wsopmmM<@SS*&Fh`>Rb-?S|=TrcIejhZPSsuEF4#ge2tZh zHC}b|#JY|m&zMkrpLa3)a;8C~7O#7O+C~)iT-x1{9V1Z*8%_s{wRET%ALo|r9Hj*I z>^dQev_j=HW<=%>BsXm9<<1=-;;t}GQD+<9wimkCy6*}s3CeA zsmQ@pwTF2vDd{_@ytgxaSxR?>jNTcju5&1d zdVtL5tp3M}7rB&Qt{<0ddHzttFMeU)_eQ#J1$hx8k~{w%t=@u#E-j!S2}Kr>m-RPWT&n{6&TBUQ(Uz z1xR0eJA%WF+^*1Y-$sIKFb#l-Gh`6WurY^U!L*jY>yFhUe=|XeBR$fUeP63sgGs^D zdA$qq@d%pkEus&y^B2TvK3jHy+ZC}U=0c^8XgWwjD*%V@zjFa}N@*iYNjN4nZNXgR zeHT}~-dcuF=0anX0B<~9Y_Y8E=oFR|XGM#ok9}XLp{Aux-B@oDdrbQ3DjYU^z2c}0 zJmFX8t^W1u+Ox{6c$L@7MXgE+t4B7g?uJ5BI$2(QhQB&{Jnb7WG?;*#U7zG4WhP2^ z1+xUi<(hGZgG39f9~pI zWhp*=ojA=Xmbg?5Hatu=C|3tEs6@U?19xO6rHy1&sU)rm5Ks*oyos8PIX55pMLGzZ z3sesoHTWB{&Bg4gUQCT+x*|mg`UdnihD1nvIa0T&A4COzr&WLhol94CyXXrl4RwLX z)~#l`z|qYFQ*o*ub@WLqd@eM=Kg-^VB^N`vF_%8`Y=UpWOB&#st@QDg z-ZNJK$*OemM2S#~V4K#@G3V<2JF5Y1y$l0dGqMcAwW#)Y;1S-{ptwv417)&Xde8^> zUCGG|MV;r7Z$4IzYqvHRZ5g=ve|Ofr9tSHe>r)UoV0Tqq2wJBEhwVC`f7?2$m*ywf z@8G@`1^xdNA6H-s@6=CgH4NUmw1_aDgm=iN*3q~bp7pDr&Hl9AhUuN*R;M~sWm-_* z-*SH)*?2)gX^-+Sc{$SCt)d)`!?qbs)Yqby}rNB14Aihjk7wuCXBMUIzT>7HI)Fsu z#=ItBcVE>#aXBmzw>2L<6SZGl+3iv*SljrsBT;jl?58%*Isi|#5PA?9M~4%>#QSuO zpX$1<3v71(V0IX|B46FYJP{F&I^ogLrT7)`&FuZ0a+8)oVjv$+flUFmsq3sMqu&m$ zq;^Hi6E_H6goC|(!~Kebw`1^U)rQwHEcZ~JYDrHclTVCciof6vJyoc4->(Hjkp$p= zC#*DKBbTpaOZHdfYL-`UpQS{kpt>?shS&l}?Cz3@c?iyq=sM2TMiZr_$=O~hSd5@# z6-CQLBDj|FhsgHPN%Q9m>^H@{S=FT&fcgF(tDM7T4G&@4h=r!=bY$2rWkD=Rn{R)a zh(^TGG=Q5rjW5A<>|xK``Gy<{xpp@JZ`*v(8jNQLO&oU%< zTPhaMfvJ+k?gU5r&;Xv$D%(f7HH4Andi`#UsN@4=XHa}35S@m7aWof3w^x7|D?i_# zM<(uHycT?pd?JwX;)={|NOL*v_0)e1;&!?RN0?*d~~Ube}=I0GnEv zf+-E^i6PRDIAk0y>*ROv(rCp{@)uzlR^OOHm*wwc0m-^F!BtiA^U*s>BrgA|Z1Hf* z8CFmr){^1uAtZ{`W1&Xyu1qr*DJ;f9TES$(fBs;jAG*BT$m%fCENzA;WwQ`0kF&WK z={3%yxrdqfc$>pq$s%bBDi0dAD(~HOw$pvbnv?i{tgThOQ?<;K3Ws6PcLpOstt5;prjMYdFxM-w?!pGG%8I@5_tJ-a1G=4Z2 zx_1~#lzq^W0(slnqlRUD=jIqUUh=sf+c|%|&Ejvz<*Ug*z~Dp}w1V^O{BYN;*4*1@ zlT|8_US#cfwVk52;b6&Fa8wHUH#bk}*9SF}*iYuQN-`0zk4|WhPeKf-o>XlZ@pv)| z+h4yOC@vZ6_*sd$S6h6K5*t+4=&@6E+Vxq?~TIo+(YS4?Vuv;SBTTX*0Q zXn)M4kxE_V%lljKNfYq{;499h-g>3wq=T)J_I1x;3U7BKs-ql8pM}BTlfl`T*Oz5y z586b2D#;mtWp04XHp&l4WMRYeUs-{ovW?~kqay1Ty*Qsi2&P#kNm?dhc%EbKr zJ4ia&+=(CmPNBQ&tHLy3#B2b#xZf3cHqGlmr>?<0cB2Ha$u*`PX}~tQg*bK=mogf|nNxWi>is5*s}233F^I*b zKTBQwG>8vl*rk`f)l?u0lW}?+A+x9OzvZN5Jb3*Pn{9hjfDfw!iyfHtam{}-bJOob zql~lAi^Z~W5og5h*Y?*%beEkzG~_8)AC;SD&enKc0tQ~+?64kEdOHcRrrbx?4vjmG z2Dp{MZrkwX!ypm815MG@>fcGORk5~quUYrR{0P)$tXK=lDUf-I^{8ssT;^D@m$1Ei zeYS2!C%!2jajSW0bzmiRi^q7mk^f;J^-Te1@TfFPKL0g73HQmQ(NobA#%-vprmTMQ zOAI95Oa;>+gP+!nzDn=%z?bIWpepxV1$r#=XgKY)XRZHMmio2X&c#wN1qko-q_n(F zEyXs(DMh?}hSEtA((o8jf#&uZPrS@$3qRElb%>5B40bl&cw;}QGc?Wo)p+;fkhE<0u!{<-QC~ezEVHh z@_6_i!YC%2fJJOb!`5Kl^Rq`d=w735_@{Y1n47LHtZFV8D9UBG&&Dj*&l&gb_w0!h z>JpApfXQ(_3)MC=oTgsdM1Gr#5KjK|V)8+3wjUmm-(x1VykmBkcw48zy+|Dkw@+?b zhQ4Pboh2%EB5Qr_YXdV^X^~&yMQ^Q4L9_dl0?7q?e_6?8v6Cwe&=IrOVudt>q>EK( zXm-d_)3@2wt+e{cA(`3cpmP0R^8!JK8yv7~msB=_d+ZFFfcJ&Xl-Q;KtxEo^_7pJ&i`@{o&(37F%JvaHLN z*6?Z)07Ku5wBze!y!#jBDJvX3=4aZKZn|8%N9twwu<&#$fRwAOo14oVeH`lzYta3x zXuFhT%a4&>B3Ve2ik+cUG1vE{MvJOVsZA--+Nm;m#jfz$^~&-tAKOp?c1{i09J5 zu)By!N z^K4}y;Pdr1_&$Rmgu`#Mqews)Zd^#<-*R9cAn-Zdz*qR5HGqPM+#(Q?zxm_FP48Nj zbLjF{(K=h;N%+4gd+%_zquE*nXFFq|33yKn zZ6@AgPKK?P3#;t%h-!X|WQ5%736mGqGv&gTv05Q_d+163G~VO0-3bm2@XiJzy7M z@;ZI@@^K;C{Q-T$-~9F+U%d53vYC`Rl!8`fopV92;ayHTX}q79j|$B8s*hlIlJX17 zabSEj!z_r~H%%~+;#*qoL0AfT*%+-v%ksiqI)ur4%}TCCN&um-UP|HCH5@=2coaL6vUKYvKLWG@N14;eCdWOxtr79S+Qb&4IM>+dZPF6eJUH32pz6vut+x`j9T0Us zEL$6{sHSUjg?&pZx!N zu){!L&Z#*Xi3hwf2+n`ya0vJ|kOJBjDSmH&N3Mm5OhBk?mnv1Pq~hx$u@d*n^*LTe1Ok71U)fvOY;YKIn`2I;QDHnkc%UTHd#uD$#;2NO_P7!c5-~K*>H38BkVnTnkgHqA~G%u^S7yADwYUGbI$f8u1eK2$C)nrd6)nD}mRj zpADSwx6>gf2M&NGb6+9;Lu?ibPy%F(H3B$jrw|F0da;TF6x zl&W*7n5UYq+YEAn`B`UpZK&~L`{IlJ^-wH#68qQOaOv-`-%r1yJp?_U`x#}g`Ejag zSo40}EdMF(!lv0bPNesVK`M2RdqiM+3@~{p*ag*Ti5KtRS=hn59Dsb|CH8qfr%9&( z-UyaArYsJxn93|LyIC9z?~XKD9SG$;n&X0(EGN|6cJZ)aUI)Ilvt4>fV

v)Dvhk z*ufU`Gz8j8OZohAWyn{9O{qgvluas1ghm=8Vmc7XxE{H4MPuG}@5{=dXt@sI^wr*B zZYZpcByVEwpFQgC#5)By$P&5eN)QcDwISZru0{u&;oL)Kb_e#GmOgL|%mDeseK5lK zf60eeWmwXp4e zyA#*84*ZeAPu+*iC)jsR=|=-`v9BgGbj4Wrd=5)W%7XjDOcZDX>(kwdJ>b6{*$gZj?B7tWjB6#jizNsk1j7 z49~g{Tsh_C?S9_fEVbc&d)X~mJYe*0j%}p!&Vx$k_`_L>(xrasFL_7(}gQKlo8iP;7ho-NSaBbtXib}B7=;?Cd6g(Zs8g(2|_RV>H zyZL?>qY-bdd0{SS?aN93Nb(?4 z)5PYpQyVXnuQ5fQB@*dYtAkFU-5Q1D24^;FMmN&dSErh@H8u(_lZiW_>T*-9j=z!H z$1gW{QwNsIureH7aJ^)G7_Z7tJ6W4F+=ds5RLx;sFgb@IoAA)t&5ks{iLSU<;=JaA z9#Q|m?o}%GV%LbJD2{5{uaL-!TabdlA``{l`d1RFaP#|lLLowxok?jkqyPJOm@l$jE(r|bG!-FiZ`VZBy{m=gp9I@M9#{AA-F696Hi+5-O zu`l$G_qZ!zKGN)U;!wGmZO0SJ-++YwLg6-%VhJ@9K`zcW%{CpnV^c)!xm*^Cfw~1l z^~0c(lw}|v|85cp4|w3T0zma`*G8cwp%axPgyCpX|KR{4MSgWqkX^`-cq{<|EkFb&*e~d{F%I_^RHh>S45j+jg(k%sa z$BxdR4;`f%`koLXE^tgbT7wXl0mS_HXwHG#Z|IwS8&u%VVgEt(7lR6NLhZDwj_-mw`z{aGZf zHd7b;|H;&0;8T@lmzQ+v8oLWRwRtSjgGTwGwi~W~a>B$!B*BoD6pZkfcR0PP7FFcD^bghpaJ4B!OjmOkDDCa{)QcNf! zjtZ|REPQYls*yax-w*fIUIF8QJ#x%Oc1#0D0Z@uEpd-KWhda|3C#-aQZK;QW&FZZx zRAHn&?QfY);6u$(U)PQElBT3HHT6jKLZ2uhV)#RyeFIaVQ^vo$l^+pk`I7)I03cQS z!{+H_ZT?IWS-86H+?6Rdc9&;0{=tfvQPBU#qWU|1yX;&e&fiT}+1W&RL2#&m;oGIU z{w4l~(L+dl$4+I34Z65fdf`SsEn?lY+j5P<7A4andY-86;n6WWeYtGMLh%Ea$r?W> zyCb#u_1{PrGD{a&7$9k2X7J$}If{I3{x>*Q^W1@wzBa$371=)JtpX>RTdMtewvEC4 zOaHE|X6^c&EmHUi|o6Vg`^$7THbX$q#9kStRaod?6dp>Iq4JdvUpyl`09mp z5>k_DhH2l9OKZEEG5n`2^^MTzDe&8@&xl}sSGT_7xRYU)L+<^q8BhIs`SBd9`N5Dm zs^0fF7W+9=Dv7;#3_BoLredcX`dMcBP4wF>KC@lxGiRzw5#XE|&t1CvSUoAg-e4U$}6!4msW!|Qa2WVNfE1Y6>c*>(>4D4gZaKUBHN~Ni%Lb$Ju?UZ z+Eof~qqIG{GgB|9-ye^!vXg8J^E}f4Y)h)jF}bxmC_56>PI=2^TUGPK&_@F8gtJ`8 zzpE(INWa+8M})XJyv-KMe@Lf2FMQP4wy0T(>S&u%Tf~pI<~h1<{!oNvBu<%S4Sm$b zgGblCA}zHOVEfV}5WZek`?HT)xd2`g0}@#H`B>oM%fjIAI#b=5qzB`Vzgl#@Yn%$& zBibPB=#oLK;@EIM;qy$A5zkehe?w?Z&7bp-@9cOOIok?@%E-vw^zkame*XY9qr=hu+5 zI=ydQIlvQfdra!hTGyo?u6HqmY(AZJhW*j)z(1aGkG>JzNDCJ`$Y1DPcwAJBYv1?I zDvGgF#~9L?U9cqR)2=aPA2c7#W3zO_6eW2=r@C7~R8X=|Ug?hJzqEs?q_tOe2u;~` zwOHQ-%ch7)OY_~a-S9&{V|>pAGgEXIjS5%WRh*)5sQy3Xd~D06Hu1Ehb@^h`nAV&V zt?f^#7s)y4t>vRarC0KSaGESDm|6cmMu1KC4fo*=-wTEalB`mgNpZITsiRWt)3TbM zzC-V57;4#waZ+_n0QT~`wV`+*E{g6F(M$mfJC*uDP-2JWg&(Ie^04z8E0IF3;t#7h zgvIytezxsw=Ljs-yX>ms2zd%i*yiahyR&-^C`8lJDnn9C7y>?ZYnnLhMn?{%Hvs?c zuVpC&u~gQ5J)~9n z4;Dai;J^CUe^cfE^R^R_tz$VA%89_o`AGiNzw=p@+>r*{`w@`6S-S9)*18jmrX$Y6 zKhYx2#n%FrEIkawmfk|sIPgkun~(1jSZ!y|71AUq$%{_Ie~me`a;_$byy5IO%gm5o7bV6k3@2+t@J9MZ)H87^qWQpN$6>VA-r;sL zKn|y*iLp&avT3})$c@IrK!iJ^W9uCMq*V-=gx=9Y7xJg7Vf;u-z_vJxDb6}as5#tA z6T@Uk2=n*P&I99|cND|GCEh9<$1h2|OJ} z*HTFr*ah}OL8h8;A5rZl$~G)OofhJ)rWNm=^{JMvnep&$#jO%j1`CjNXZ|3!vOS<`t|F}wlR%0IXfk2) zloH8!gB)4TZ+*G8$F;qt6Do-sZ22sWxnBx$!uyyBO{e6gYpj64_!#DxcpJiZ zARgqXQpG9hJ&+Dr>n4icoIOvhusD>IIO{GzBg%Pn-@vnNM)vQhZdFSY&`*Q|3Fvzr z%}cX4g&8$8O7L=$#mzWA4lvDJepVdPMz#I$Zy^z~=l+I_?Q%mG+$hYuTY%Z_lVZnb-tWS3(qeS2aea{WKq1#mrYVT{{i@5{p*Lye$$&boxzNc zpYSSvsGMcCjb%-L;uU&NiCyXC_h;K7;7FwlbFALR_dx8xG_(2p36d$WVui}O`Z*i; zVpIS|cE@`0Akwl~!{tdD>0ACQK!kJ1xx@Cuf5I2L#aM$sr$Z^rwMiC;vUVyS)6gIs zxHgWWh)us(SV#<7F}@S)a5*HYb24Avlw5vf2lTdlrnA_zMEZou-3E$LuU?$!6r*og zK3h83EpL6<;LDsDks@9Se>(FK z`{NspnhzwZCMnZt06n@Haxi~+9wld+?_M;Z&KCNj=LFtU8$h6-@JFH@p*fxU0e1S zA`q&FXVGFtRqMJY!KRl`XK%P$1-!ad-}IeQilGxJcaf(B<-Ck|a3{Q1t*BijPwAjlV0SMSE6VT- zv`%Nm^CHK#Y+Q7$zN$WZNzBl1-ieAI>Mc#i_iQc+yREe*VAwAAz>)+k93mcPM9)Dl z7Q%jgu!XZsgWc8EWfy~O{SIHEzE&{FArL!b(~vocAPJ3rQrPG(Fg<{g_N z+hb8yMN!~1!1l2y>?mN^w81=FfUvlv`H?#!C)7`Udd6a&79~ctIi0VaZ?miQz(a6@ z?Y_%3vqjIe^B@Ap!Qj{5o))&NWsWsEblHbkldj*X=ccWCKv^Chd|Zc29O0-%Cfj)3 z1uXbJEr;y0=h^dA)No@By5ah>!Nfiyr zvFq=3oDb$Dzz(Bz&Jd@(C@z#k)is8Qb*?r`?&X!!DHDI9{hydpyfkoE53xam@N6rK@)#6TmB;yo9lPfGlB#44+(X zE^mrq#x^f{4u|WP(;4f+4~Ffm+!o7thzO#V0cxeE(YThJdX0ts*H~4%#zG9kro)oK z2MEHxh2|2^IAWm<3@|(*syldA>4v>-*f*W`sSXLw%8Yx1@{BjSXiJZx**(_Kx1C-` z&EuepzHn+6bk(a2j>?6R+Sj!SLrYG=L#mqxWM?_PE6>Ip3>+GAr(UEAI9ehuuBqWi zfBGLRc{E7BwCkj>E&gUNqvY%oa9Dz8-fWCl4vyDXej-!@zE9PLZOHyMDYC-~CotLy zkG??SQ`+6fa`RAM0)KweeFXRZrLU}eG<6i%Mgeb9oxoT0$KB3B>7JHxAD;n-OM6P# zXE^r0THR#Z#e5Zpm5~xJdncQFs)(q1g$2d2nm!hdA`kYZr+XY_yiOTt{&;aVk}*?Q z^#fq046Uqt3An%OJ?RrTT_W3Y!E6Je)1N6AHR;ZgHV$3?_-tWk>Vk&5~q(WVpA&qgk^iNyNB zC!^l8zE?u*`>_q@pCIU%Iq*3FFeyD(Ju{>s*M}Re|1y*?Zs3mWqSWlm-;kU_goS`Xd; zcUOk?F?=6HHhne{a7C*>%^kCY3tCIdi?2W&=HWcK%lub#Ka@R=siJHSB``*kp}#sQ zo&9&j%u&T`l33xY4zqiRP7kxCe4KlXR$Jsx#HPs;MYw!9O>G7K%_b8@WGnR6zP+tRH#fr{e&evGHxu=ZbxXJmbCyC( zoxIN-RBltNUd)^ACGIKkv`pEH5wY=@4qDJ-S-=HQxIy3Xr0@06%YOedsr1ga+m9FH zBTI*EkFF0-jRdz{hI}0mh0j5b=z}4*sI|hPGZuEqxRA1z_+R18EaXTw$$@y!G`Ryv z`rr&abJ*xWvQL7t?brG?rJET`XE53RMhZm56bgybSUJ_Hzk+3nZ7hU~B6i#^Pnw3y zO+v5=8XT`b5Y2t~2|D6zp{WY0kgn^xtV_xK%z-& z$fz=|Cd7B#2xt7_)JH$F)GdQ`>u2{uNyqu#RE?%p2h zC*TxV2vf%~t0bRUvtAELY%Z2?jcc%AckNZOigVS#o}~!c*R^ilAG4}-IE7Fqk#gRl zeJKkA-UrzD15{?;{<5WwNYAVmS%J+4j{?gpEI|XO8I(O_Ha+4`@XBtiADP>Wf*tKc zMt(=u|JyPYAryI1y{Uot0yZN|_$1!p1Xm)RIFI+hod_p_bDzYzOwnkMqkDzpDQ+2P zc1lmh*o^ZBI>zU(h!E`4^~#`Y7?+o=2es;eAn0^Pc`GSQve};WB#b-eXSbt6Uuk6| zp?;kmc9NEJl2r3E0TSL~@jxx(gv*h(HfBtdE2{BK2|qHUw|aX?z-sG`qZAlW*}oxp z0W&_?jGnUCk94xaK%$zwiOH5;`X3CmPe`Yos5;bz^0oHsw)zTSr)h;#mPeH}@c~Pz zL#3t@F?<}A!D+bH&LBUggNIR)LS*IxN&KJhDSITvm18G!5vQ=qLB{M0YBoOk797t@ z?*z^1@+M_KIje(!YOHrd&7A7rB6dbV(-R}OTwav$4gJM0zb9Y3kt$9x25$Vm+lG$Ze@bj z_B>kVJh&3wxR9spqmqJqZxGJQxij^&?m*yPclajA#7Q8P2v^}iO5ypD}dxdheNjfQZ zJn6oSoybt8VRe5sUz2KY1;v8`=VaoIJHYoy9$b;Xr@dF&epJNcgLtB;Ov)fE_Y~|v z#asIqic1LgpDW>y{<~)t9eNk`?p*Cs%yY6}vJ4NZWMl|Pr8aaMZ{PRnjbDh~zFPKf zk-B7Vp+^&xQkC-^7%qNiwcTj(6$UidVEyRH6D7|@t!oD(${M*6E5hl?O)j6w8s`DiJH zRlksV|IX`OwX^HY4=+797)zRe5T))-vzv#0vsYOkPk3n>n4^+vv^DmyMUPrCVYcdp zPY&^VRiXg+vequ^@4D@RQW%#qaI3i8q^`asBd7RRt6uVMHHrKAJf}KR@-_gdVL6gd zqSFWRwInYWcuT~*G54H&iyaJys8T*7Rf~dh)|v?47kr4CD!oZ?vdY_@%i;1lh!3)~ z^#28vktF6tP8H{jjed!pMAx^QrR*xzkrG~1BtTwk%E_%!7WDa~eN$AKv`_sg<&XxE zsGy}sM*m4-udyb>fL5`lGo>fv^0j2x4earI(RBW@>$wo453QeZMzqgHt>efUi%+8J z?$WR4s4+WTe!mA*kYbbu-?Pei(I{i}DWU>z_5cEGe+=I(oj)I`RbB(0G>{zwt!SFt zQw5N`X`J$AHiqLf>zI9+$Uk;|n2q8j)bYDpCm{21Iv?oS1JNz}nBkv8S1B)|-drM_dfzqHHU5!|g6~ZOkij;n?VJ zDsBG(Z<;aAna7a|E!;Inr*%#Oo5x!Cg&rK%t52HHc9-F{$KE`@dQ^gOOEcOy`56@`c64<9BIyRYfgzKAqITERTZq^FpqjUC*_J9H)Pr5g7N94;w2ap1#MvBXw->opH1=V44dw^uD=# zQTjOxKX-y4k;azOB(g>AzEfmm zK9ep-T!*vHDM5q`b+7Njv1o*4-Eecd`ASx#)PNZ(aed95^Y=FM^C!FN!Af2OimwQr z>7_61+Ae!dSs31y4M4H zj_bntEZ!WOOBq|+d_I*#BR6h(i_CbDxrD3LeHM2)EEkI}f9UxOgI)=YB_Os)OFcN}49s`Y% zO8)pN*9Duy%@!?MQX69BSuilXyrGpvoap0gC{f`pYs~H+mCjrjJw23J4VzxH(I=Gn zugD1Mm$8gSiq&E%i#~5%cI29}L>pye%krE|PGi(`A^X%5WkXuw-*zX)e9yP$=tPlB z8Gcs}7gImipMy<#?AX=TQ&^-{W-4e=2%^8GyoTNT&e~H+iBO{||3}7N##7w%m$*v_ z2QVvYDEXV(xI}W}V7OgXiMpbwR>*&?;e?z1YA` zd`;YXHsVV>6xNXg@Wd>g^psX2AuoE!dWxLAVu{3D*LdqD2?Capq?=mSfUOb6aa8n- z=A3`8zPSEO(KvdXLU+zZIwWACv9@WAGfSmuW#e{B=<5YuSD5c67pq-Rh|t8L#^P)= z|9g{fi{u3zFi0ljS}(u`hHpa8*?3N)*&B<~(GTEsF66^eMg@q_XLBSDMA`cT`Dm?5>wqh!z z962)4&sx=@>e$HT69Q3>->-y3XK}X5#3S;Z+I=ggtE40G%*#cJN0B@|_2BYX_s;@! z)Tc?V8H2KoXvA&r1rXT!Zna3Dd%>r+>iwtDl>FfD%AJ2ow*1JTQf@L6Z4SF5Dp0?#-RV*Z56?UsZNrZ_IPd-An<9p6^HNSLtJ3P=fn2O*p#^h5I#4gf)S6x$4y*kiez!z@>GXF5_MQHp`p7|B@BHrd;r(}iiWxT9PG@9B2NVX^gef1 z?KAq**#qs%eCu#Zc8_)2x34e4*Td;nGXKXV0Xmuw;D~_zy=r?&nYthOd1n1mI_dj{ z7nD4B9PfK^gzvarNtBm1AJeJ|EP0TuAwGtrMkkUrsQq%C(S9F`mN@vd66~5@rf!}P zDc`NjBrZg_xG6F#G>`6NBGYLvPA%v^g#ARv_i; zdGSV1dW1yXrB@94MykiDE2UWQY<*%pEbP{6g%e~f4uS(vaz>5i+j5srd!c`3|$YGT2=!< zI|^iZv)0T0tRAK@6RWFRe&2ihIH0lOsLghr|8HBIs5O8RNP^oe!eH{8!i3~^E{tsB zu{N57^B!&MZmAvO#0Pnj%R&)M!ijf1`2{PY^q#xuTUA&R`I%VK zi$Y2|?j^ZllJ+Fpd0h!zC&<6VsuTa-FBr*?vGw)Si_Pmz$2G=062#ffNl}{AXtOZS zWB#0Z%b8Wn`p?CNdWk{<6nrPDR4PJw?&19(CnA`)b?!0EBok%&`i~o+4RztaZW$b= zCp0JbFnr%_d?+xUgC)Kf8?Uq@(J@CkeqxPgPuEU`GNjI*0n-eiPC@A#Sa+(Qsnd1Z zV4KFYzRq9)X_E5qY6q`^arbAtvOS(Nl2I%7RVZk5pJS0O8a%Ii>4W_SewFdC+-QXF6%eNUT|ACV(+_KE_Le(pXEY(;c>VqLDduPx$9M!e ziR9mRrQp+Q*21<&;!|4whSIK5P&gOaWy%&{k6s_+ai`1}9`y*oFuaf{e_d4jS!@Xo zIy8%>b{=Rq4-qR~4f{@(V; z;Frr+cUUT+hj-h+9uq`c-e2H@oE7+3;6gC~ipo6##6~6Rp>W&V4WDLJgV*3?5wveT zI;<NY#qu+bZj-Pa8n&UqPgL$R1ix-4_A2!TpimSoMIgGU<56@}YbSd&J3OA_^bV z)t@xw<`GLe2Hlh|fSp|0Xkl29p1p%rw@E;`YjK#9=D{>90D8pn8TOcS;_2C&9vNM+ zFj0jsD;FGp1LwDi7s%G-mZgOOYvj-N6}Yqdj#dWUB?+04D=k5!?+o3tU+BdFdC+Q3f@hWXSk|BO%|S?A3@J7^>1X<3<(e^uCU zGK+?%^zzkN8at_;7|pbnd^wJfxPHq#z7r}92)YGBcwyLN90f zhGwMVqgxu;#t!JWVhuKti>D02^=p#tE31fAvpO3#Mmvi#a>vEy&%4BaM7Bn%J4ITf zNRPsOQnAW#O&~y4Z{9b1=~&ZViq+&O-;^rxw~Aq@45w z!ZCp&GtT<7MM=BTpAgIoOsBhFqdMQazHM$O44iMDr3+Yge#ltr{p0gb!@uB^9jc}P zW`Hq_JPu%%lF_kry)^7qaHIFR>j31oL3G-*|4_>Bl8)2T^W%cpMcdtsjJn{;(5y?> zn*%W@_^Yi5cxcN-UYFSGnz6s-X=hm~^UU5I?~OBS^%dV1w5!zq7kUxBg>&}FYD}xm z3{vl~lhd#*`?$BLP~Yh{3H#D9nLb(>ZdiC2$|$PW zpo#AJvdg(t_ zQ?4W_y=Pr~5wuGju#QSon@RGCP827?o2*f8bey9X*&U{`>+#{~w3&-J{O0+aulb+w zTRAI8I_gZhpxcJh9JIwxUk28h3L7EZr>O{fj(C$-jLA{bwO2o1I!_0eON*q5Q*{gq z4D5zrojiIrJGB`q2EkTuv!KMEC!5~f+Gu8U;+On`4i^-S4PFmx8KN>9veQMl%=UKN@%^!jW^4<6+GE!csnO+tImaWsNW!??ay{)n)$w{P_rNxGyCguv}Z(; z@W-&}^oZ@QqA)c!50NA)8S`2O3RjCdIQ_9tzI>ZJo+VC6zw`R?Qwv>_I>GkeOTyxW z)pO-X98JvUaH`9d$AuZhg>uPYY(@o9x)@G{%}Tl{kLnn*m;} ztG1wal13SCAe$Ai!-3#WXAJDmGz2G?Hhu_h54hNulVbVpY2=?_|B`cNMjSrpnB^^53lP%MJ z+KPuee!=euS$^iBT+dC7X3Gk%lR3c>RbwB@0nf^GF(Qf9b8F5<{+Y;3`vZsb0f<^ zMfIRz83_q@`mB9uK#w=^+7&KV<4{l9>yFOS6)%^OY~_uYq32cU)3X$;aK&Ij9r_Ef z(`j?StL*Sv5P5V_Rp$oFK$+ucE01+hV)gTwfMc=ISjt<0$R#Ln3VV z=4%$+4F<;w5LC#k=Yc8|P5TXirl(ZSiH9rYgg^8YvAX+_Wq4n`-mnr5@eY{CR{?Qm#y1t>K6h-`Q{l`Y?0Y%j)-^pueuB-}?)zFx#I$ z4J)P7&kGY#9cgL35FJ>J-Z(PyqCFEY#DyZ&5JNQvHR4#;;PWa~j+t-Dw|>0rPqb<@ z6ALhOZ(4QWS!xoGb;jWa164kP#nvwh0wiYlCX=-BNPiTYAEE;5UGfW;>_t2UFi-@e zp+}eTmV3`bDf^>)WvU$6Lq~~jL)1LwC&uejA+66&=wPgpj+YUhQKx?y$Dg_ zbZ?f%qkhXmh1@W1!Vq8UbyCdy1c;Us>r<-`xrksIy?hDW$3Sk+pg4P}REpJ`zbU1U z>JDr{1loq9d8z5NWv z%bg>Wm(}od$!j+=ZX*OU-z`Xv65M}QqcV4Q=8;Wnja4DQk+eh&k~ZwP7{8sRaD+N- zK$jPPo7cW}9<*g2b%Q@yKLM@>Hw9OKY0s7A3VWopUWHXPUVPD}mDepn75;$*=E2B* zdo$1Q57QiTPSUhqahtYHnxMT5+nC=&VTsDzYj#lQ;u?`N8*X1(U^D~ao0g;J-jA#a zXc;Pr#{Q`Lgi5aF#H!ejaZJ$4yWB_x50q0698Nt=(_<`wn|-4^B7yPRw}$Fq?O7*R zn5c{dYH4e@sN$H=bn|(De}+^A1G|mG_2;YC7q0Yc`+kx)n6cDgYQhC?I^VfFjyJ2i z`&X{dq7ARCNf}V0Jt9#mKdPi5zB_NL73!_JV8rWX49_nxra(GuR&+5UfiYQ8E2SL`1tCW z{(ftY^H~pZJ;EG+-c)e|kgGQyyf*trn_CZdrGXI)Dp05!$V9AErA#{BX^a(;Zgzdq zvncqz@*Nq^a;pwqCnRuARhjqNlr^RK`02|&AXe{4Z z&#}J2YDAD)V*WU6`^bd>mWob!0(Y|uZ}iyH1iBq14Jr)cmEDz~iL)I`$$e+}R%HO$ zMaLnr#*!Rgb3)|}?u|Y5s*7`J_M^pWjr3M^<*?RE+Put+<;z=u+v+-Goga7lrFIk~ z!;ZJ{OI@P21oNyVYF_WhXVK6TpERo52(b6wXZ!^}7Pu6DM7MZ5-<|)yPE=4!h_;Ej z$czv=ebegH|Y+(<$C0Ji^Y+7I8>h-5u*E|%iqoeDqD=hH`8{m4OO<%>Kh zO5w<%k=*am7lc2=^X+V`!OkdxndfzvMH#|Th1*!FQ{WN-vPSqpAFQ*n!b968yf2@| z-uz=v(fv7RmlukAfzls{FOemo|Ii65YetTDY=e5TwkwJ>J{04i>_~q@7>R&ttEwGc0<69 zUz8ha23Y2=Ff&aDq6LN5k%&w;>ja?I4^F0l2XEeJ%9-=2n^XF%swtU;zMZgn{~MOk zMbi}e{Ooa@N&B=WteZY`;pM6PB4~{1LrOiD%&%AlpKc1zY)*)US zP5ZKOY`OgqWHCA{)4^F-x(LdwM6O+f;8|P$=)?^9R6?rs7|*K3S>PJgnh+U6Y&A~O zuZteim7)QJKP}P)&ktRXZCS(rcuI-m6LzQF;;S(mNzTDAJ@#3oQf)J@ghxAi2T! zeBXc07~lEty=x4TJqFpy-h0h8*DTL`Cc!%{#-5be)Ez@Pzuui~xb{e@PDA1iPz~~q|NmFEod#Bo~*~!%m5rkRq7vC`?x&Cm5YU}Vuy{8HTj5PTow!S zYi`XNXqYbq5qGV=jvWcue1&pi9m@J<*3kw&SsxiZ_Rf-YjTF`KN>$JzkE(FCHi)Ox zNB^>Qo&aoiq`FV^f7mY-JW5%%a2(D8ENmT0t>IWdF8nN=E{!Iydgj&>x$u0L2DqiN z@ukleZp_pYjkQ&mti54QC2s?|DUo9XnDi`Fx0jc$Y`L_y{Kcv5TXyG*#mP&WDw9Q! zCv<9idKUIf6rV=?6sChb4ePsIYSGT_m(E4|u2^BzrVwXuTQB0BW)&A6C7D1`SL*f0 z7jCk%I%-nvWbVe{e$}H{?2DZL9xbO@QqSG#@Ms*JWh$49tuAKmwS4|IXZtPlnE8cC z^vMp%$w{xeIsJnjgI(=nB&Ql`^80gt1<`UE;skTSL0~SD6pVwXpI&HL?`;k%`Um~fPpowvOAcdvKO`%cp6!(cxQWCwB8_U&N$$Tvpirgj=)H)IC-${13-P2nEByXxX-Y(7cYUIl9 zZobeuia{~uMmn`ZN=(~3t0-dNZSU)9IX&G}ydN&syg(S;+2UZOP#Ez9Gov_@?re_Q zgT4cd#|_FvoLJJtUYH{8fx_Zn^9xF+`p2dq@}8mZb=!^Pk~1YiFdZ0EwHv={LVFr7 zGN7y+*?5n9=&9D2OE`mKx|rxlEDw00+^%gq1*25qwKhzIr##peZU}zUlcSN9IIWJO zXGKU%yer=AeD`Gz%rdIc-fJ6R3Hc}g&ilJM3;#KNO*V%RKJ>HK>Ke*iBpk73>{^YP z%4`MUMd~%Mf1CS|CbYjxKhPfKqx}aGmy%j}k^N zwJ$~V`-UKFG6$1u?k@J^Ql9u_HYm^gk`MA2$qNxVpwM``T!aYH@9e42EFsu}#g<-@ z^|?DTVx*yApeGAk)Ivx8KRUOatE2xmROD|weQNqcn2+A$o7juX!0LO?h8LBG#{jIe z6!D9C+4SW+SDQM6-p0G1(Zmn5npKwAB=QpWq);qv)pX9IC8Smn5r8$mw6&XQeH|2j z@y?Xr+Tef0R81XRqCGb{Cp-hz8jT{5LyR65G}^lvfrvXlvv%i4IX5@d+ z0JFG*c=zkWn3Lnd>YrpxB$JSaAQK!Yyd$-v z)T*hOnWFBllWx6tygDw&PFI z59eI=_-tIb=4F;TqFZrij*K73V~&hzQ5`JOllGuzs+z%7GWJekmB6meUqKa>;xk!_ zCFR0qeRTKj;jW(ELB<-gvDQ)4ZzN;-1z}|WnrPB*O=w;=2nqLQE5=pW%8C^bp<>M^80ObBZ^`@Nk4H%-xsEu0 zXR#q1YLlBd#=xww+32TYHe35;CoIQyt}|jVPIjuFtv~JOiinQ^8Rp-e$JL3P1(f~y zl!sjo4fCe{c~-58GTcA&?dtoNelpkl*5YL&(SQ&vceI^t7T z;Kz$qJ${-ufp@ObQgwz!XY-tWs01n+%`mF8wL8Jre1km;3sjwL1Z?jw&@-{P%d4T5 zGt(`hat}&xDX@p0`Q3<3_Y{2S(GeEXeoXLW18l~oy#;cF*MtifrV4ng{m7(XeOIwg z#(%f}jXH!Z z+frh{u5WJ6a2_DA)!=1Ed~EjUFWWZzZ|Z|&+K|`!p2)qNHJ)Y<+}F$p$yKtRRlgV? zd-Vtw=rHF&x)Eaa4W0-P#*$3}$q)jU|S2b}QOHYa>rMp?|r+b+1LnakE-X!RZ zj(U<7)=%)>qP@L^lpik5*nHY9Dg}S~OpI)d>}|-hY`|-pr=;WW4TGF1S~P-2OVX*Y zXmr%YUeo+9pL$Dveg;WMs7PNxI{x>^{@ZcND;lW#rhyQ?KZK{+R>*+q-68o8f3PtV zgeD4Og^@%+HJXzr9$C~fL-J^fr(-Xe#~*@TBRaW^zSLyngDq}4GXu6>J1jWn?9RIh zPJS;&?E^O@)7+Q=#)Bqs_Oj^b1B@yuWL@R}UNZa2!&g1T~irDFdA_vekJLqJ6}t#fDUuI)j#W3yM2L6$MYb7d{0W z@ua$wYhck@bf)KW_`i&}@J`awyTdy5pxbb?i%~^tSt${O&}SNmmb_qyxmzKa^KvFG zvF|7feqxd8-!WElqvGq}6&yNmTH<;B~$e>JalUYY-K61wYt;c9JQN9BXM z%OnVma&n6<5dAUreFKMorAVd+ENX%g$o7@5w?-sP+MUj`-|GT_k|THeZ|9eDQfCx#!a2D{!a7* zV{R!`45iwX+@$G`x%XBm+s(fZ;QSdB*8gm#x^un-4y&v+RI7}oQ5ao0NL&J~r#GwPn+l_WmyJc%JqQp;V~M|9{~7c7x+PDiUWZZAgpjs@ zzzoiHl1Bf#hHEKaV2$m2l-^dICfNZ7)+Ogt3NT>Jyz$tSsRz7jH=fsg?ljQqyou%F zH6G~B2HT+fUt8?2u-bG*ie;I8|el>dj zuV??C-dR$lpOU?eDN9j9=*c~`yTef5?_MpYDL$@b4->4eUG)hh)v1N*R!#q`?sy<; zuRb%$$Zz&!uRsJm93f6K;N27!{n!|5T0U-Zw1Q(vwU7xg%F@lWIT@O=u!U1jl8Sw# z0p`Oj2B}9kj}l)=GWl>>n5(gw#@y)gCoU{B`3Vz?{si6D1nV=shdi4Z3bSc?@4(X5PiX;S z1~!Sw6vCP)IxRG?<0+m2PWFPwsg#~2({Sf!i^BRqVa@!xJ0gN|xYU8i$jsD_oHQ}k zH|b`-bjE@YO2wDVZLW;u*Us)&t}k@ z7RvOK)-2_Uv+&jwgk#ReCkfx(S;Nz9B;B#+#wA{j^qy18A*dD*a9cV}Mwx9uRvz%Z zxRgq#qpNMeKQiDH16mH}*)HWrMaaZV$MzeJ&3yjPJOwPlH^2>biirzJg&&_6+g=0E z3>XZTms09hgI zfTT2I7&v43C(5L!{!`8LH`^x8067CvtMLCcY`yn1nZ?#sSU;LKQI-Q}V=tD*momK- z6TIo*aHCWmKhUX33PNj>Gf=!A`QWH>c~PAnwG|eAfh6o?wDEz(HC#b;0Ridss-_Dq zB@mL?v*-+}Lq1SrMJ9y@lz2RBX7f;tNf5i_e07Quk`3(iZZNK^dO*)^&@xf)PGFtM zUUe32F8GjVBWwFv{3&rVL|0q&bka5rDrO*TjNgJucr9cw zx#8lJ1Dr{!wkXT_|E$t;@fMZnh<5xh#gp^62TkF!3*FNMP6oh)LF+-IaV8fBG8S+No*C5G(j% zCr>6+V3J;V_tdeG6LDQ!?P48(_BK`W<Zhuy1lVFQTZX$qHVz`zFaD z_b90kk5&BmFarSP%|RY1jyGXw$?xdz9AV*Qc?lQ}<^Noa}*}me%3p{)c=luCvrGATn?2+KDVywvw6({3YT!1@&_A_eMvi z+Now>1PA;!lcS#ylmFWV^}utf5} zWp(ICm9GRvjM(pSvpt5c1ynbw#Q$&&QW0Z@o*g`!ZCDb9)?H~t(8`(hkR!fbBcqau zUBm^Lw9^WZ@z4KWDi#*F4c!#n26eC_5BnP|l724z3hq5VDMypm3f8mK5zCWegxb z6S$MO)`QvTDXPdB?r~W$P(_XeR)6H%!WzbK@~E-U?Hu2+KEs`KkN+&p{^Af1-4p7i@PS#_)s=T1kIAFo%VTrks-Iwz0CB4^K} z;8Kn^vo)k5q);YCBnlu&Sdvf%G!7LzlgLSn4EFZ}TF&XfTvkcVz~(EcRR>B0moriI zLQQ*Q31Rz8qO-9V4Njk6PhD?NxVXvf+}{{)Zl=0-clh;fgHlusZSV3voaozWGC&N} zT`t+$;N0t>iQR4A+_Hwt;$R~^8S2cwhqiaPgYN_AuWECpii zNqzLn=H@YU@6ex|rQhQ+uC2~|(kU?*X~vMbANPbwODJ->-y5zc1!>>NgePD;vfC>^ zo^H!|kdVLNg>PQ=;#-O83zMn-y~NEXnlqS39;66RZHr94;FH-KKhnGE@k{;mOqX1T z_zX+(=oFgkBL$NloYM136edz&S$R`prJ;#+`jvx#}Kr#}Lf&V(#8us8VZ! zh=NLmV*T&eOeCeg!pTaNEr&2LzDn*V=6!|cM>Pe^MjxsNC2rsDO7u>QJ~tFTd?0&& z>yOW^(obc&XJAd6)>y%bP@_Q%+q2pxl^4(*OWHa0j`@6sc7u;Thcee-58u^8!` zjv3rdJPlTNb@kl%+H?$u9a5Fe9YUD1RQB^oimYAdlxWjEYKYD1Jyb;_ zXg$!&@%{}{2-^1KSm&OyNGE>&#a?SdU$<+W`9eDWvBNLILBo+9FCb)P>+WzPMUbTC{=O#jC!zs3zqnTiX!(AEuem?@WqpNh(tCi#{1ee^*^hLw(FbvGin`HKZ7<#Wj zIoren@Dyjg>z<$ND;GqZ#81fv{BW!~35TYMn!ugaBF?>&`d6Nq!fA1zvf1hfnQciX zoUPlLnVEj>CcXP~D@`3^a9H$}Tc(m5-G8W#Kpk>12~{@ZZh7jdI=N+QD8YhMTDEyN zj)oO|#?a5Gh4(R2KNUe6+6p;;9`W-H`rlC$OFjgcEpjf^rCY}q_9Aw7+atjTt7jE+ z!c@i|qBBiMl7S{c4D#2mt{w(>>>p7Pm%gOi9ifa7B?I9xFq1Y&m)l&!{^0zdNnGNU z!cS0%(o9@8k=t^t3*yw0#nu4fyPApm%|oZA4YZGw%qEGD{9C=+YNgq(iwRx~a0~a# z&+-pfb6$PA9%pq2?8p|yL-WZBf2QQ%68mDI=!NG5W0z)+1JBh}oTibg>F@x2O|~+# z^+uSxI-6ZIrS1Flz)0963s{B$Wp;UCNdT}VXoLeQN!GdD^9RokDY3h^LM9GlT>!kEZz8r|u7d{_&%NhCwYdpPdYyT64l}%h1}oejv1_aHJ2+ zeyQ58S&Z`X6xJLjb7V2ZVla?$=>IFzNh;j~+w>{6Gp$DmjK2_@Hjyb!!HYcO8(@}6 zFYh4Js9%y)as%6xP24=*s}-p~s5zN15~772N;pXsGkJM#wFoaX5*ms(xlI3 zaO|<^yPz{F+65oO#rf$yyHe6N76WmrBVREgQbU{l1o0@Du=fhcXd{cU%C5uEPo>E| zx{!gj>dm8TeN0KXnGxSNv;u&MudS)roc>R@qlgw4s}eBjGk2pS&%=E3)RY?s@=&UT z4s*F>zT9=ioZBk1C+Q*=CR+*%-5yR?jQ>gx9N|%`RHz+sxakRDw-KQCY}I3ua>uJ! zN?n3|c3=yR4k>?DiQM?2R}N5X>!M_u6BrvqZ0n`Xep!wmX{m(FzmxxCJo4whOq{^l zjJjqLf;FN@e@d>tfcAw9TCfcO%fo!$peo6}_;o!mZ9wDIt@FJohs(BZQ{wb2n0>8V z+E|jPP&1$6yU}z)mNjx97Y2E>E8Up!4c^OM*VJ*tezhFIdAy%xe2nP9 zF0Gnyc63Vg{(i-=T(SGj1oAWPBx1yqfTNZmp6)lyE%Y|b&sv{sNXcW7gG+y~#>+x@ ztObq!2IbGR*ll<$osNMTW>doM7jLv1$KAWpYNZUy(Hn|}uu$c#pU0o-fI;C>krN3uv-4ANb_!BdG(v|4`&C01dVgq}FBUz+th zFrI*X027MvTa|tc&)jGboB0WgK zB=cLkDN#`&CCK*%2hX}5^}W_v(YxzZ-e;E|GN&4QoXl3omcD3CGyqPsB1}3J!yK*3 zN>$6IYbz#8aAy&G9=qy3M|saI8ZD7acbz`~*Be-*tNP1b#!y- zzK~+JDDRzWF0S!SiLD)0#G~Z*QzG@AM=xsB4m_3Ws6xNpZT$OIH;=a3Fi z#A}VIk+}Pgd7{GRBTEu|?H37}+3SBs9m>Zf;%*W`J-i|ybR6Uv=Nj%bV@ z4(M5=avdMZbbanMMlcpWad&v#iww{|qQuG`P~2jc+&E&O-OAE!QdC%f?%(}12Fa@| z?j?B9Z! z+jZe2zjwqt{qp5i{|$i|xq9mD8840iZ!n_(Zi7TE=zEWfuq)>_xcO@!u{k!zGp_UL z%EdTu&GR}r|1c3;r-1y%)n@-a-y_+zs~JQq%d;4Dg`Akh5&lAfPhF+!Cb~v9fzj!_ zpa93E*A9RM7|s~v|6Xiu0fStTyl9x}-mIQoo#60woYPS<)6MtUjaHt9u6tEg9n%%2 zQ6}-C%SO`nh=&uNJ`_yXN~KfWVsgE&`f#oGnZK1DaZ~kIV^I@zqBgTCq(lJ!vUy)} zVRap)0q*1SmEU9QiNciK5UEgmCyBTVHSAAH^1hkGSihk#by2(R%4OZm9;Ovfr{f|= zjS>c2a-gWP9>{yz^&8}XfDjtg#rM{!#Gf=|1vhM?x+Lyr^q*zQbl=7glDM6~{>`?z z934+@ZvrDygT)wQ?$3CHo5 zCxjG85c&|5{go*8>=6Lr!YcX%UI)8nv!GS&> z=?RcuAx3fw`38mI0-5!x58aKZ*b(dXw83N#%;$7uyf#+anVk^`1sFUXE+-ZZG?9&T z9FUH^UKce-n3P;q{HaQsXx>uc=tMA{dLCz4Z44JO+-$zz?tdyp@J8N^VeyjLUjLZ= zL6qD}{^mbRO>6_$o)&7n*V_*f#F*sKa|e!&lMH=pTi)RMQ*Yo%QdXq1LKP ztLMVNa-%j>kM$mUkG#EuYkp%*F5T~-(=UF~MH1uIH#ys$?BAH<7dLXc@__Wl}OGVSO@esrP;7klg4jkor`S5f0(=fcr@5I>AKbSY|)rIZbrZgFap+xsJo5 zVez;3SE_EKOY7FVH0xyBk#c9$u>z^Tv9VsvmMe-mg}rz#WP!ZEE~H!OWqfYqn7q)y zdRq;E!3%=TnKvyD)g*#2NPD&6`Ek>hzzXNrh^c%04pE1}?YW)nT`nVrA@%moqOx*M zse&um!G5Ry?IkVB}|`LE3}v)?mA)6CKj!rsRKas9L5UPCbMbzk1refdDTBBhavr zEr)u4GWXlARzht$KIwVw104N5({R;@Mb4k(-h@Q}!OOrTVS5`4;bI#oH+HGzxR7XU$JdrY--JwgC!vtpLempS|Syz zH_Ug?)vq(HJUQ*KpD=G4JEM6mX8^&p;v|x+sNH6Lfk$jQI%m;iQ>TW1EZa3M@#mD! z88(A1+@uQJd}5`}*0q8z8b?2_^W;^v+dQngh$c95f(7b6qoUelr}Bo&NqmQlm)OM} zEWnbl2ja16rk{*8NXwQq;$9Bi^%MG~JvP-AjJ1B!{DV`T(#^7HK-gVFJ?6ZrQ%dbc zEneTACoq~#;N~kV885!fas_DC!s}I#^y~N|AHpo1H^&#iFq^rFq!$LS@aR2C!Y|<) z@mrrD6P`FHb7AeWD%%&mjN#w+W753)V{$zn&%GCHBE0{Nl1fZef_F*#d8&ylvxArN zjAJm-7mwRa+_YEHKE~_W20Wd$H~Kay?`z)fb3aPO{QJ3oo^TeB-&xmedXd5Erf}*} zZosy*TA6#Li9(KMx3xS>@W8Io7%rG$(9q?$Oybej14Os6T>SCgZWTJm2pNPRo@1UD zuk|1~lWR0pfYtQO-IP&P+y_$hF!8e18%Z{POdB-lY5wpb9YV*urjuj8plrwwM+>Ze zLv}gOuU~$?Bc=5d>hMyGCqC5kgt$#>RR(qtKvyUQQ1IXJqj0g|7+zB@$f?nFwF zlTA!YdmUXdBCb7AOFXMz7?*Q#n;ci0Ub8;MM@os4d*=IF;a zlAt!<56q{h#nk=YYA(`F-LH#G!X3`6%18g68p?ZHH)|wxbcX!qhA*{yC^X_PoVxt; zab8Wu9{ZNhj@IvztPX7KLbrf@VLvG$Yq1EJ4vv#rtk~y$kIhz1F-j!=JMGtPnMnZO z9&>c9d3OSYzvbmC(8|e6(*!Qvr43b-eV^5CD*aBwb`!awrh2Fyt4qN0( z>$Z+fjQ6(;$4<<9rolU!CzorH4#KI4tr&te^(C3xLuF#TMtwk(Z$3Osf#nJbugdbF z)^8Q2NxN}_am*M?>exidz5T90Gr}+u6%RaX3_BQMdTt~Hf(wB^Um>z=XV}PVdX7Pd z1bAl?Ib(RLUM-yEa61Rh3O8&~nMc0s%Sn%9PYv}2`HPqH5`KMkYq+C7hze)bCJPN6 zkLG6ydCWVhP^((;k$Y&ZZ{`#^{Nmb#UhyHHW7CdvW31=57N4k7=(Fl*VPl~1Gv0{} zDDe^QF9Mb3RZtH$z3m}Z{RjQQ!Us(0%6--q;i$QkRAMhx1hVy)^59%3+%HyHW48Di zBuFeByHMUFxxcu&?TH;P@;b@~R$y^OUgMyG@1J|)`}<1UPj&e%ZJTKvbr{+}gh^Dx zVQ#M8HGv3+j?W3Xyu)E;5t%LJKh>HO1iY4v2`AbY)a+}eaIbM=IzuGvrSt_ucBv2B zb%9{cv#9*#G3+^XiZpV1ekQe}1T(vZw$}!?n6_Jc%H#&3GjT}Ci_op1SOMOE9#zz8 z^m(B7i=}nUd=QhMIhJ#~qaYqW2p1v*E|FPr(@MJDOI_kS-pj&!*)Ks$xV3ecB&Q{O z_huM;-@G$)oZ?_=0(%YQOA~(uB;{Fr9c3Wab9nV7o^FzldlD|gIojbwkB8G|J2nI2 zr$UVo6tG^!blMC)H{tlZoZ4hQ8JLJ@k5b5yJWn|BU1;){N^~-j?KK>UgnF(3ECwS7 z(19`GZ3yDh(v@3>A_~{zByUm#Mk7p-(C_vn=o$o8Gag%odklhi3DQTnoYB^jLSkCx z-Dc(Eyw{EEIMEc|FKRQ8bfLEN0DV4K4A=UO{la5d34KINh-cvtG>ODmyz#Ezf3eOc z!&wCp_Bo!u^w9iwxI+ZebDQ_4(?+T9~>F6^?zQ+|^Nt4C75 z?Q(s!Y`;*EmmWuA(Qt138*0xX2oMjvW90BJtR|n}I0HmZ^yOT*4)LZv2C#R!-zXJ zEWJw$E8SVgm2?Dqf6&_W6QNJy6;A%`2ndCN*%dO`Obse~a8FAax{zL%U_ulRcE&AZ zcT-KuAFS7Y27|s3URb-XH{)fk&A< zFKg0R9F>Qf<-En@{c% z{lIKmD}whC4MK**)u;Z|OSr|WT3)MI-JPEqZ$GJse5Sfw!t>tI89mTw=KD}3L%F`7 zn7V~>_mxf@&*Ae5V;f*~cniHpUcY;nI&|L~li!* zu|-86u{+8M2Ql5OO{%BOiauKV(MOD*e9OX)1j44(%PPSp#P( zD|8z|@KqXRSc&?|Hk1ezYP>!7l2nG6{r+~>U?n_5Y~ zL*O$ZRLH~cQun2IZzDF|y84CoQfB;44`3Y(>O%D%dpIrBn|bWwgXB!#qYiELWixM^ z`2W7ouu>^qeF+&;Hh*H6pynGiP1w0uch>qD4C7#RUsJG$g-(hzTmJcdEOcokM&MOr zSP>nv{FmJ3cutBJf7|WY_k$w)SFY%R%QDMN5~tW}KB#D!PeCkJk7SsWuwVgmbe7Bn zbKu2Dz|R?jrV&{~7aKbHj$`MU{cu?x5)a4u7&opVFw!LMEEdvLOy^6v97-6LPY>2v z#vbQBHLOV69gIQuCwqIG^ZtIVJq_s(;q$LG!Q5+0B~{M~Qqeeq)PQATjdUqflP>_zR`F$;#EK!K4C;v`D-Wga z+FzA`FXr&g>M|SWbgq$n8~SATrrXdnx=3Rwhu%*40A{#*eXt_yw~o39HJ^QF z_lbFW|B86*>@&lGv{+&X1TGcHmqDPEDY_ZAe8+YDS`=4xX+R0)gW16arhMuT&E+eOP7G?9 z$T5FxT(6iJr}J8xh( z25x!8S|69WKXR6;SV?V~J~;$l`P6su9!J2M_AJp(mM^i-68EKHHfG+|iIWtomw(+Qp2v&0#O8sWSD zrPbDd;_DvFKOtZd)|2xIiK`VIln0pcFA02!B9=33ynR21B2r2Cnr^$BNhfU`8wjES zfa6J$I`Dz{F3|kMW`VL`-WXmyZ1 z1{wv@%tNBOd8eHLu4sUgLZ^2Dw-Z zxH=x5lkWELQ-=Y@gT@^cOB3eln{a1+oz(Z*fawyYJu)HWUO}2daESnmnOi=!GS%lk zo|2by6j7l5kxzLwLK(_a6%wpe|1c-eSULop=rI~MGe)M+OcKW{`0FA4k<0kAVC8(m zyIa`hiPH^4a)7&br~b&b^yYwTx=|A0k=C&*?XjIAkbyT2k?zGL7J0*KY)`RAibw%F zQ^K=4ki;1jB$0kG(%Qcxr%>d?eVl(;@X_mWGj5!NY-nq$TVC-mfW5N1G@}GAlW+r- zZmebgkGDjc=Qv6se(Nb~k)$JiKe}`Ez>@x+OH0-_{b5a0%-i&Jes#_I#`P{p$Ma^w zj&^ft$>WbI$dQJpIkb8@zQ8bNl)9ObA05dd<5&t3SD@~gM;rhUw-fu8=r0$mKd+hd zXou{+MX-uDX*61}^c}XBfBwiY?RL#ngxy@6_CJO>`Az@`8e(4 zW0)$1Jvyef(CCRgCVHgAvK5!^4f0qJ6;F5HsaX@lC~Z*XAUB-|ozsyRtg6f8m|P(^ zuiQzEE0@Feuk04yE`d69?#KYlJ=3?ulwqZ3w`XePLNIRdb3f+q7;Yp%eQ%jG|6GNV zG~EYLp-C(z!R{CL8`t%9&k<*V;qr6MRK7-JCn2#CJh=2OmpjWDGI;!eJT~l#gk7|i zL#2HT&J*lQrF0%y-TLy(=ZOaqHP(~E0z2d+ia5&oaIIZs3-fQ!i3K}vFI5LrM7KBn z37`;Cacoo`ka<2i^tYAn`EUQHA$lnYKOYP=y;6b+XGPjYp>6|P4hy2kUFS_$h1g%S zX{9@#f+ly$GNlDHvZlt)_?!R0>{Mq~oD9cgPx)$Bdr{Us)x`oVBP`4F+u6gFldLOS zSRX640PCBphey{vS>5cD`owgJ)rd->w%7ZAJ(d6TK0K843`D7KZX{$Pr(*Zyv1WV& zaGjYA$zg@-`=U>o;8eltN-LiDJ4;K;Ep>OC4}yC1yoj>Ar~y7)Yj2>9b!?gVq5YDd z+(CFbw)*T;(TGh7miQZDaE89+D6-D&aK%yOgQcdEnN^XD_kn3^Fhx;v><1MzqQYGH zJe#_7NCJ(=>4O)3eH4@6|2w_5O1MKzqLCoM(A@E6nTYGM+Cdih@1<*73pHMLou@dI zxfZ8Xu!sK(fVM-W%$7a;Hm2BrF!Or-4Tv2qS*pkaIQPo_wj5WF`~Om;^xkZU#5Fjh zHO@=SMT{_A8s47ds2WHkAILhm0()yXtL=6SQtTFMGE;}s>x_BV@xFziI_6Q@{2`VD z7gj91iC?_f)U4KQ9>z-tk56a3;23#>|L1P{d^{aD0ZXqJ(MwFr&13fG~*^; zoguyx;BQH%5LUK}GS5Z>Xx53Uq_Pqn5V^@&EQu}lZw-^!zIH%gi(m-1!kf~?-VCaSIBde2Fgi6##$Jq0LWw(+~`|b*vQOZjhm| z#)~~XwD~6p`|la~9|tP(-|9l|rCXs(tJbiqUpT+gsF6*G-j8ZcD!>)l;Jtuqq z{8~_5^TSWKt(6i!Qd;9F|0jg_e_Zzm6?ya8)h9zN*Mc5DW!pNG?8rNFMHdtX4M7db z_=6sYPL4hjBuJeA2gi{X3)icAShr-qGr$gwmt$$Gm`Wr z_4qqRQi4PG|5vR~*WX$nm61267rJZOjXkd~w^7?U;)j_>`zv^Vn3rUYp#Q73GjG58 zgE+)lc1S`wXP&h6r?9Yt$FiXx-^TubQJa}c$|J-ea2^PWqKHw*EBEJPVn1O!_ESChj)rku!ay(Eb8OmH70Lf{HzcgSvGz0-G#=^pOXfJ zmZG)OAuU_cPL@@p*Q_igj)ML5GD;e>r@e32Q&1Xp3g_5Uu>!}F2lcGy5g#4^blD>o zqQ*uSgYTab{cH!K_tZXfXtEsnRRo)4EU`pxRi-|ga*z$YAETGK>0Mi}K2yYRJ(rW^ zC~j-RI(urxgO?ReyqcP>x_hj{gcIn|fquT^yU*J)CA>E1fHq)d7#ouL#1(dYe=&-S z<(>OIb-e9)8v1`5D(G8JpW1*jO&E|jvB@=|Ji$e_e6tV4)0zhFU6{8?7OUhD@&+b+ z8d6FWnrx6krB9Y`rzd1*Iv+?j03XF+&<5Vbpab3Mg*YS19hs4K7mI5`Yd=d@{@J9T(%#lTH|%rr`0)!SX&!qLGl$D= z2|ll6_sIjgiok>*u9K+=j7ziEX6DS{kVvD9KV_tCuTrX02S-Hg;ws2{1PXAU{9KaO zU4@nI4_#smKAgmrbKjoLr8OykXwr?yZ0?ofj9HoHp>P;V=4A7}ISpnm_5zVzRr8+>)e0H-8-ks#*w7i@-`wQ+Q z9;N=<&J0EKMgmRnzR{J2R~mJefJ?w9w}itz3coEve*1S70n@r@V&NT9oc^sFxn{UT zewym5uQ!Q#VJ4!~9LV>uU(lE1mFl=OL zeXY3QLw23uDI3wvFQF=#3ic^eA;>N@+*4gsMf?iZJ3Y;Hwi8r7-Kk0+0Ui4ZI=>9N z-UTMYK$A&={Nx=CpFN8Ihpx8{i>mF~#t{UhMIOxQsKuccCR-kqY3|! z1%+|SzsrRXzJB4hJa$P~aMq6ka6sh0Qg}dRshdA38??C!EzRz0Q3iMSf?T%E9i`Wy zEzifcRzm33!aRmIsqmY9KWeEIoy$BWWf1O}Hq`j|@JKyqZ~W{sWb3fbzE<}CLh}57 zs_Qd%qQ|GHqG`wU8_Z4z^MpLWFaqYBD^bAs=w`v}?O9JTr*j>!vori4z@lkR``+e`Uz- zdU(QZz=mV9*(mi78oii_RN>ByC4%*F`}LpBa$BJXy!9Due&o`%mI;R7@i}9r?~NH& zuf7Qpb+uR^u!RKV>&t73bf@*8zGun3+p+PIykbf3ZU;3dAlZ(<{@AYDsho6QI=1U= zf|+tnq4oTE4H6YU*i8jM-nB%v@wbpqh7+Za`^aQ=50O?=l_d-jKJK~JE#w9CTEW*x)nf!IqPJU*&J+D6 zY%aSE+H4=xg?a zv$?_NbEB~=vhXOT6V|P0M!}?Yv|@?w0U{1(*ee@-(O~S>HZb2bqJI$*)oguk=YZ?R zaj2{IZI2&vYtheDb2?FV!n#a*!Dxu;6xXlKt$ksIy_9f<-x&JYc$UWXQN*f^Z2P&! zP2=yf_BX()H{(Wptc$aov@xjHuk)=VL3pK21H0vT{hnN>((2`S4A>pL^wX&CtN0@%!Md{+{1rl%5#E z=5CoYD#QGNa_a$TumfKu01p`Ged#r9G|^K+ME6-aQT0F{@YuQm}H`R|oO9aoU? zJMLr*1D`oS{jQ2{mSKAHi(o%WjvAXv&=eQ(byH;7?BR(CI?uPBb?90Wfd2Jjb~)qU zNR8?T{Cf~Est~mBnGB7vmHhA;+GH_+pV?~5sIHG)nduF0x<(*oh^RLTD(~2pL05R# ziULap_fHyKhuTd58;&GickN=IUqutni}gko_TBpMx&)bEK_ z=T5CZ^IuB1dOt=_A7n!ORU}%j82i>u2_3{T`g?PwaH@8LSUSwUGnYhgx>%LrBJ1{h zgp7l!GTE1o_kk#!(;r)9GZ?vxIGZ0gJMUj+3kNLZroET_@x5anAF`S;lwWz=^R*ZqEcoG1 zxGuzHeM=-|wSYc3{fdVB8cs7}IOk>Ua{Wg7x>WIQN|VBSfUtnYGga;g`(o^JzS(o| zjWlpRn5skgX~!#IhAjm*0!v5Qek)!V`?N9)7-z-uzK*gNRM-ywt-HF>r!D5PLJmw^ zFLlSg@UmY(bn)rI?>ahf3qJ3)!giKW+lTYl=NCue0Yn_8GTX#r(1&|ii<;a@XQhk3 zao>`~2T(PH^B5xar&r^fpOPIBZ3ciS00VwYYK{aV0xoZY-trnfGz&KntisH~X{*bD`o(W!Kt|yT{0u&7yUyDhb$60Bp?~ zpylC#yvVpt$e`I8Bfi2Z_lb5MT<0B}B*f}=S}~H>sYn{5#URA4x3{xnUS{RzyZ#5J z5}RYpU*}61&!}XEidib8^QR)=sk=y}Dj;W;GOqiz7=vF!3cP}D)kG&#Hm%)|`}U}M z*<%yQ>0-#nM|o$YxW#{GD9(AucwY}p?DjR&vGMu#(HrKqeJvjX%nx@1Q zL;HZNmZds04UHp&oO}B`+O>THNpW#T#G>DtsPE%mV}2!Wp+MUw*6Ojf6viw&#A}c} zFXsHwLKOBg>nJ>bq8^wRNrvH2L?K7FcRLRr=yrlV-%kTS612U*iF{F?`Is@-0E6nw z`VC7{f}qrm0k^iDZbLjKp0n3OOIlP&^f={bYZcd%`b!b)o6YN$hr3N_QO_%Ew!O<& zMDPUJ(V;>v*jexri1ahy{&7W3*wN6>S2ST)<)+IMAvea!L>$xxywO6m8C}Mugqq7d zq0-q|>-PKl&aZbg>p%Yzh!bK&$eOIRWc`^v;dJf2Kg{7xCTtJK%D*bS*SoD0WRCND z_cN&~%g_Z9!nQDUlE&={jt~9ZL34Xy-ye-1{cwx5R%QQiJ5#p!of~Vlb9ysr%NEK; z|5oa>iM3I8O2QSqo$f5BOQ|v34h+~<`Q{hhXfHNqzuUEV&!jAJk$aH7B`E6Ys<4)B z4je1dOWArZ5Q|dY=8CXu*FV(RW|; z0oDW?IU{2sPI`5H*vWHGFugAffb>gU`al8d0T|M4Ab7>^d#h1kSIQbJe7QuU!T#U$ zIX|x(yLYB?p_2LjOtC`7-HUO;vLFJ_UwUBMEbP{Mx~!PyV20z3a(9dhUpRDmVKl<= z!UvxQ!3kN}Q?g{tifIaDqT;GP&>v>rbSUsjD7`+8vQy&x7Sa+$`7Hi`%iC(=4K0xo z7jLbwm|d zM-j2W*1o5L^9~x-u`*(ss*p5#6PzK3GRoAk>^$+8zIw#gi7`3fF~>3`-7O&1LalKN zd)!(L$xY5ut?7U58U1Z6baVM->!+`5{9p##TMG-{=CBi@k5?Vw-HJ`!A&E~=Tl!md zvy=LS_BPlqF7G|dFFi;mq9s5xTPkBN>tf&g)c!6`nLNMwj>28>{s-OHR}HqnyBU0g zfX#fx5MD`LZ4}KT-r~uX*Uf7AY^a6r4;$18eYwK^|0oX^xEaj5rGk!0GFgKR5I~T(?rL|;o$FdtvYJQ@HdtE znqiAEBE2*1jB}Xbg4^Uwi-$%ZKHNBRsO?9mSb#=k_%Ep<^RW&vNbYR6$hg5SmPX>h zrI|<*qmi0xS>Y;k0n`Z!4t`#JNb_2E3b)s%+%DGO8pcUHzHFLwM1qQaqwK!#Fwefi zNr&Gaq>OB|GH^v;@$3|}NvEVtP?AN|p4WjI!4yCkwKYD|L& zt%y-P!QVO_e+J0W1zhM>I%&5L>TU|%yVs6Csw&oQ4Mwubq~bh0j4`(f-!e9sqj?so zw_?#EpBye~CWwvQXo;;mWZvDr>?au~-2`opSUTpMSc9!8pb74l`aPR;K(PFdM$hn4 zZ)+|?l^`Soj9ZI%C41qyy~ z$s&382qDL%Rb6fcQGm!uN`^~(5{07fs>J9%y-Ymhp00 zhkoAs?H7Htwm;} zDl5mw<9uKn>?^n)^=du&GWjVAba3v^@B@?-sT8r>h}teAugUF zMVGFv-%QIN9NIngVl}!G#_^1?>ktCZwCRKNV8jO{5%8ESY;=V>$5WE|AVAB++O)2d?C z^7jG`TiO*^Jj^<4#WKErnBOj*eJ!M<5t_~Z+8{FkOROUzC1$GA6NQ@C&~9Czut2|Y z8^$?(#MY}-#7;H)0)(%}0`aXhvuxCDrY<87UR=NcI`?y&TL?|pG1a^olva_8aCY@O zB?$hY54L^1YLvLDJHXaL9-{>OCM5=5zxR^YYP2L`E)*TRJyYpxH={QXCx57(Tq7Dk zrm!~a(*kNz;jwV^KR&iHs(J-@B~k$>DIG2!+9KCt=CIohx9|DdUb?~5BR1#F;#s3f zN((>!4Uz!p2S$-OU9~)7u3>WlFl$#lS~*)A+;!*QKgj%K_ER@`#BhQ!3^u>S-htk27_cwgrN~m1Hqtj|rFjky` z$9wPgfY&y3N@EZ90k?C0rM(V!@%rS~G20VVHd~Kb01ykfLEHfRdd1Iw70C|e3 z3;cGOU&*xrPBc^B@9W8B%hveRq3H#2IvG`8{*?+k!Aatarj)wVReXfR_kxH+^q)x^$)%yo%q2agO16cL>EPKthN9r~y@32V85gg&=xrXim=p2_< ze$m8_?c7RP_qFrqhs2L2VTx6GO1#yu*ZJ7jpCNG4?PBFNx#{a=is|=z*B)%OcZ!DUa-OWLy7E0#!VB0P|wLh94R?GH)Ps#$~}z8 zhj?VDgsDL3UXHw~A)sGkpBSPz?6f#LIj27S$O3U9ASZmd8@Qe~C+zoS{jQ#=xZB+Q zPw|PWxEH1K)qx|IW1pC(&)6&l4;=s{`#~p@2h`WZ`sYeQA zJ|0JXGUm?9n;^6UuOi;HEqNqzl?r>>2s+*RDV{j&guw-JNg1(D>-(W zj)>26SNrNJ@11ml-p6FlGEt07idf%%NX^^wm}=_#u7cWE;{H6 znOcK?*Up7uz~&W}qlxu`h#Qxo$VxJ^kI0zrYYo73ir3*-XwKXViImgxw`!jid(^5z z!^5W%g_^mj@BC=!9^%qp1GcG`yWEc?q$F{fc6M|RG!m;>@1JBj(yNkbCytrzl4wqH zU4mMq^1o7TW((_MfrhEz-Pi_WUCnK0H!@}5>uRk}*8*g-Ezlu(cA`R$l{Xr|YcaBu z!QXNt+(TC-7w1JpDNYxz&mz23q=wPiwY13iD>4#VyUWBB zaJ%-aHP#rdOj+#kgi`W%_Nd$d)4D9 zuvcQNrzLjsTD#QQ{Jjnup=?+f|4g>YPV0@`qJBj-KI$BiYu3u8{+@I;w))l4=_@XL zBf{Fl5gZnw;A$@Jn)AbC(A9Odf44|m69=Z_NUP^@H1Bh3&Q+72xAzJivZn#+(eY{O zX4Auo#PAUwYeh_3st}@46W-Xb4 zoz;=HGu^51^mqop!5tBHTin-H_0Llbu!PrQ@#chYZH72D5D%MK9GSvAWQ8YMuxKAF z8xxu0=-1`Vmf~x@Y=SDD#hVy;6@OVpeh^@iU!M}^%qz$<{+5zLF_=D*vYu6w-&4tw z{vn7)=|eRqLifC|An(W0(jgpGBQBc8OSdeIB;Tp=n?Y@=qOx`B&+}NkGk5&kGGph} zUcKe8AF@920C7HaJm!k<`6MYhoR^;EsBGYZjeR#jbB0oE!@rvv^geh#X*YF-+3*-~ zl z`|XlMAC&JG@MJB&@2K(uFpqBmMZC;9nN&HgmN!1hLkt)?>q53;)GKrDZ%0&r!a zXM;g_&VCW{WYiQlgiMbaW>YI|COKGl!e4dw8-Zka&_ENM7jRnaSi~$=6*?8baTuZ;TS_ zhTmA`6cDM^foW&1Aq~q@2jttpjO!?te-dk>tSHTYEpUc|*me$K1jQ-!A?jj?WT5g*P{j$+fHUl8mHe3oD%?#d zAO?kvQH^h2ptoN<_>#od^dG__g<9a!H>cw(Ht^Q)G3EQl-*qHKOH`3MA@@O$MRb-Cptm5!Fkxnyd!(3-T}X*A6?MFe z!9P0St@sAJu-i1rgD=JV>!x_BoYkEx0TB1yc8GxA81rRu(gg#rMj}~V$-z1VOxUVf zZVVEL7ZkvfHwF*0-k`Ob;OWq2=K%cs=E{}bhz>bKOB(j2plm@!UAo_{uDRbh8umXN z$)q&M8sFDo+F|E3|D@(q=Po{6too&HdrrQ8{^p3jxv0bFW{$&UTe_yIDtCm0Jk93| zL{^zzU}a!zky|T$G2S7+{jeGp;jI-YRwosvXs8tVEC*ZdkSNnW>2ZzB_KLt=Fr*U~ z1OMHz4xV|i{}>aDVViiKBgB_)NQ1W-Xj8uL>@8^+!GfI=;P1xTe>Cx8hD3866=E3J zzUi1h6s+HynfPAj$8x9tX!^m$kuIX#c0S%l@atLL_RNUCTo)vPOtJlEeHafFm$L$s zR}agouN9eNi%@?$xaw=}t4(EumU@yy1zE?i!aa($K5lm~%aNE*TyS_NEi}QsVzWUZ zqFx@>a<@pmn;Q8l0)CKu3US;E%906y3D7Fp%;FOfLgpO?x6-$y=gP)AUCR_M$lR(x zt9dA`bz6Y)DtTg08hvX`Lc&7iR9Eu3Zf}eI;cRWUdH6_IvZ6{ zO3(q=?u1LV>AZ!qW-vQJN8t$aV|YPpGYj*~s=HCA(aQx~DIokRfR!Zk8<6_cG3KMb zF-fxv%uzd|_pjp_`>glS{0`p8Wg+!m1B~Zs{4lLYG8;x?xzbyBz`*J0$>;C8Bj;@9 zk-Ow1og5yy;`?(n-z7EchMlcA!9HaMn$r3XGf?VQX+?k)wOxZi8n|hOqbz04HMYm0 z;nVrrnX`T|MIR676q6wXoM+$L{MET0cq~5fbkP=Fz_|I)v~?q?U3ASP91HbT;<<+MY@x6zVtp*h(xG*I`e_oh%~N z7%iphuO<2CvBhV3FuF;xL8;!DUnQvoc%PT-XHs0gVZvYam6uSp2l(`r(vx~l6iIAP zw;(IIJp6v(%5Zh~xzSqlmZz)7_Fjp@ze>^KBwheCCo9ivIqu$uz@8uGZW_e1?VPcx)1q>cR{ zH32!!M;!Zl1SvZ3GwB!Bf?B1zNU}?kda?FOM9?eNw~C<6(1d48CJePQ|xa^|WORRcgQb>4~Ce2C3?`UH(C{R{rW z4+Me5QB>)a9mlvWes)O>*}AL0=csVWs733ik9rAF^K5qtNL1IyOD~}Sk(du`Gp^oB z3thLY!xtaNOQdRz9vM(=!lYPb*264Kx~L z(>|K%UaS5kHHnSu9@s|W8xI0`*K0R#2W(B78nUq?Mm)E`SvT--S-TW(zQ$;wAogP` zSu=mWXcsoYWScDiQAA*E%EOQb+nuJwd<-zS9ho*-r%$Mrxa&03JoBzw!nkzbOV7yw z1q6YSgQ9?8j#yFohF7mgJClRPH{Wt`>rPxIE7A+UbyJP3ood&3c6-CeAupdV;)xa%x)Az#GXohHYy^-|xh3oY`w=v}gJB z)aN)C2e^o*&&0r6uX$#MOs4XABFv<|C!LI~Me;QUVCLSbv0q+xbab$}Wv-5Xbs;=m z>ZDwrDOQc`vtZQMiDwpDcI!2MAcn4iVo`hdZ}Yf%6eooG_ko=Z6JW#AMWc{@0^~oS zUDf3&jmY(+`@-4*$;pQ#KCiv*rGVF(5jK8V>*dCH&1+j*4>va;&x&al+5^=to(8Ec ze~G5*Sv3P4uauLlrVLF8uv0&S+0^v29%n!{k>8N$KsV%)GT2bH)e046RNu_OKF&TU zlSu*HiXhyysVk#=e#q;phd+5$Xosr*LS}UTuuk;6f$Z$<$#If9z~wV%GMKfiS(z@| zHzx`t5IYP}`po3j6F9wDR>sWH$_tMjw2Njz8tiFH-_tSQUXIr~XU*XergVrKM%076biL^l8~dD;C#W{SAS)-k5O!(**&7* z($RX8dbytuw4L;W`;Bkwi;C~zmVCLI`RcyjyC-^7Ohf1Q8Si^_6VssW;r>j`inGRB zphE5&xa1{R?mOU+H>Lcck{8#YXE|3%E>zOQ6qj7z2pt{9<*- zz2hokly<~e$+*vCLT)Y`Hpk=-Od2}ICD`F|e|RDdmc&lE4bxl09Q_Tt3PkqQZ04c@ z$g>n{`RURS+zIy`3!2-F$^qA?Fu(JI`MqzNz6bsZyR7K&4wa|Q>afrzQr48Hx0g5H z-wjV#vDx^XD8SDL3oo-Z;U3}f<=#D3^}Q)nS_6RtA&EGpvhBDQ2u3x+>De{*dojC( z%K$EwzHSsXUx(qpZ{!a-z%rC5)S}ZxT<|-xft^bEh?&q)I#_#6)V;4n;VVrmZTv%h znqr{5!RF4rZLRn5b=j&)hS}u z{wYF_|IJgijjm^TZS)tW04atuoXIz{4y6)90~h$mJU!8g;8UpBFZBHZ~|fBMCa;I_}hbpEbFS_`gIr|ZN7}&WTk}Kfl#Wj z0|EKUIjt>O)K)OtSI?>|>pEN2jFi#9Lp{*Pl zGL`neo<4M<_#F)gP6zYA^I`4D6hA1Jsj(ndnvIChioB@(yZK^4Nk3BcIzGk()k>oio{00PeSngLgocfv z5Ff+o?e&4zH464>qaIv=$s}$K5*v7%?CI(A08a;k(FFB{&=eT%$w1%?zGd)EYmMR4 zBY@GgH>%}|<(K;l3C*1w!g7oKL1KI#cLp5BP8u}aHdG8c79`cX1F;_m6!fWxLOa84 zB|{umYL6hy6IBw|ogE?>y-PBJUCi`v(|Q^_uqM|taZ8 z5m3dKBTlR_oOLBHz83AZwEKCnV!=JgyWFVnwhV&(n?uO&=Kn-bGn0F^a2nu6hVkE; zqz+CvjJOB8a zycM*3y~Mmcn>*~((m5va@Ya#5P?j&#>riU--uN}n$WC09u<#F3{lx9{M0>;k)B@<= zJ5TZiT2VdF)XtyM6=Brxto__|GPk;?EAh z2Yi<(^o3s?&M|uDd7Jj&+xQv=D72W1*ZFHya?{=oYg~c~szOWP0kEU%c_Lg9@rKy< z@a`Cg%?j~;GjXdfzwhb_2*3{H>=5#7gx4wodQiki6e70j7PoA z(u_!u{9ZdN{rNR6u!F}A8Xa#VNwal9P(voBkX97($ZGk9jn~ot>O@zMm}%=AH0}fg zZ_XYFp7s9>u5<8t=JtLm?+7|vLVB>^gHEFvk-)k{J_sG~JJg|IqSIGujtMskkPAbp z$)0{D&B={+{{76EbO#!Tx3_ELd33Abeo|n~R#k~h#B&};eqkG9j)2p5KO{QV*NRAR z)38jtu$=MD#jB0*m{X7hmt8!OQpq<9=JO3Z|VIFTO%aDW-ft+CYt>)Hllq5XL5#%=g+$94m?dxD3cJ?!S?s69FtCJmC(p| z-NxSreRdvo>{D0cQHpR#fy-KhZ?wicTAdZKn852D$1)pDzut<{XulihosOXbN&R$Y z)a{tjh>q4664sVAk^dEtza#GrfH1zwnIw%52~Y@3OVBUVu8H6o@F+%ohC3iII+uU3 zptC&kik>kT{m`X`(9wL6T^E(;&SRPE_?TyR_O{vue8Qq+*s~3WKEIv{O|UlbcsD<; zuguF;V{1xmPbEy2cl#X`j8LiOt$3Zlj?ze&Ocn22FD(x&ABSL70 z@{Oq|pW$BD^fL_8b|!cr;0rBZT&eI;YE*PP`YB8zHC@=7yZ>p$d%N2mGX?&aw)hYH z{D_o7pEA+r1~#6og{R@0ExBV@r!Sh;H}#iq&e%lTD`??58vF%&nTzjuPk5cHYeZrq zZ?>0LD4(dij0t$f5By6%_g4b{%TQewe`G`j5U>6MteWZW#-bG!NX+D^p_eWr-UPU{ zN$iw}9^d5(Gl_Z}i}8zA)K$p8Z1k3EPswFltI60)=XRjl(+-#@0p@($B0>anRWW=R zuSK@AHsaeCfpFB>2%+UKA4ZK>fTu-~N|d|DQ{517=GsY)ws#b;$@3 zFFAhXX79|7Z6I|DXq@N`-$e?{VQwOU4}qBN8Akh#)nqe1hDaqmQ!->qb zC~`pG7)_8rJQNkRT=y3Qa@XBF<( zGR9H94^4`Oa)F?oc7~j59ofR8uP9MNIl?HM5i!o45Da^1Cp5wL?=~{`TDPlcMH06^ zM=3+F8D>41gNcKKL%hP)dRX&X>8N&GG{Q3@A>p}qCVc551P&@!RDvIvQ9D_n?aU4L z+G;Ok-_>*}jl2(79fT z5yd3mJ7X4_rypJnBGT=MfMO%Bgjv?t5mzec>U7#8(o?4{iBaJ^QybKqkS!AzqvY#o z{ao->hmP^?u9RQ~%LbzywDi&bH}Aw_|5nL8RL^Yl;a+}y@R6-PuWy0|oqI@Z|9si`?Q6ac;>JcNiR zmGccLe!3DZA0i19JGv!odm<>PUspvlDz=O!CN_v4Q5p!2%!*LM2pq71eTLW(fFMh} z(-%NGbu_YA5)~D7wAE%8OBJ@H(9nmK^bD5N`jp3pj|LiTo#e9EdS%G>RKr3CadI41 zTC#VfR37p3!b<3MdH)JzEXhy-Rmp_eaMy+b{@)A#Gnl%jrVwei*PHr}77mDlD9b*= z4F^a$>T5#GV_v2N5=0wgN)$8bRrCI|CQuYJ@$Iy2WyVN5rStf{Fe{Ya%Cp{PZ)Fo8 zAjt5Ot^wU^d2lNX{{)LaVEy|eLq-mGr-CA2n+&nnO7-ePF@V$rNq?8zgLOz9Wl=HjoJ`th?vI0g9M{9`%l6vx^3KF{V^YWfw)1!{E)e6+d4eH*H zzNu0DJoLU~3-tg@P2e;`*0{Y74!)YPilrX}C+F#AuzvHR)pvz;ApXveiU^c0uR=(Q z38c51GZ~er{wSiPj{pDhJ?y{V|7Z`$sTBJ=quB(K_`yG+W{fXX-pJa1~uy#ExX3lNPbBJY`TWqn@Q2eR?GDg`o>~e z7wW_UUHTo29aS~>zZ^Vf+)_r-s)n}*;AkJ?f*AP4s}unIFC%b>l29dffFvyH5p|jc z9zV^g1&a9^t(zUHcPmu5mpX{g4t3ZCdSA05mNZ7)I-0sc*|W}WRc9f!uLD8rmg~bH zgoDz{;iDmq*whKFm}zm0_F2Fzbt=4(1BJfyUM>6ZtO+3j^`1<)SAneVuw zf{sc)*qYuRj9|$xw3IB;%Es?c+WD6WFuNB_-h)}+6bNO@wIAblWS4-N0$YDbfR1sy zD~_`l%33?Cd>)~{ST(9Qf_xAPzR z9SVH`aKOv9FShO}5yB@z6-T4*pPo>lUNbCPTh&9>f3BYZL#=%ku z)T2?XKj^Qy zA4+;?X3n5B<&DkU`%$`q6>*GJa-_5Py%r%{K}yM?7C--Jqz1h{DzM&Jv8bvNSqUm} zm;zB|$z5f@ zKrnoJk4!W^J34;13MG?}ODf%9eHuH3YMB9j3z^HP2r*XNU9QqY=xn@;VhAmdLni$oDS{67a%bsNLeU-c4a z>Uf$Wx^^tSSfY!>eT70fp$%QOpK4-0O7in-G&uvB9Lk4yW+)FqMlQoD7@eQo-h0V< zqkuNgYOUa-f~s8UUw+Kqj64bv?-VhFNDj-F<1H~Xw_F~TBlbH2<~5Am0&S13v=rJ} zL^WND(ku7Ipy|&Rr2|G?0V{`JZBD>< zZ}PWG5z?{|=LvvM(R?QO0W9zQBGA**wWk%ZTY_^LA(2#R)l)9!_}N);)hJR7a9GW1(2++NVrZ3da?0KrsUFq@>802#IifnG zwXOTk zjjJL5vc2WKkzGBf0@*8|;%dKp_Q1tuKJ^Ljm;C?teg5Z6HKFa#lV28v6EZ z^hn%Efg92%%aiYY2 z`k}UU3w~r2K&l06tg!BM%P4*B-Lj|MRRa1Z#ouJRY-}S`N6@`e)(KoMs!VJ3t`$l- z%8F7ndu#DmKAHSQ8~i?`M@X~wg@H0ElVb{G)STGAS||3yvcxQgWoosWEEr|ge#2yG z_FT52^jzFu57Q)j+1zhcR6%n18}k2~n1p^FS_?9&;?tVutGTn|*gpU|REYeH~bXp-qCW6>)_|}B7{cs+RG&ccAVBGV8xQv=8vf;@5(<9FzU};zUe

kf*i)JZxCvt(O#J!KGR$O2O7d8KXqezS^r?$%|)2@Za>qDdAtKI zN~ho*kljxCOoFQv$(>Rv4Q4EEBENda^(^Upnn>)lM;TZ%FK~DIR@t~wYH=~?KSKAv zXUwfDq!WiHdd9L7bg-rNxTF?Q(uGQqef(b(l zCZGh+@pKs?(w*?NM+V#a_F!@Jef{{bY+ z30Xq0g<<<9aZ!p}wOPh@J027C{m_$~5v(bP3GHRXtbs z&=n1@3~5_!DSCpDberT1+g=I3ZXlAh6rz#FJ#;4Lad`kD#()!x%9qpM8fAfO`%g1W z^~Pl}nu{{X2Te8`p*1io0&R-hWq)m8$BAL3aSsKr9e<2(+Z>$@SZ6qoxa+uU;7R|3 z=gVZ?;f>B;0uMV|*v(sX-6Qnx7(O64`qIFH;T=&oZ&^SDfkpg7+U`?n=W9` zh7cp;b$_=;Rl#eE{s>jM{wAtSFik}I*9F%lfSQM+?NJ%v2M>Rx7ghY;YMpp&xt1)i zqbXPOtP=0yukm5BbvKTHmJyAjF-QIqf{xH{ycPC4tKtkZV5U3uzo_xpZmy6Ub2Fg9 zi`pN(6UNI9&v+}0P$f<`(1>Zzlce}Cu&Jx%z4C+QRO{ijYxW-4ZxL|+cA4*W!01FB zteVf5CSu1f`#gA@Lalz+M0oqu!~k?gDLuBN)N;SzKCaYIW-vH<&FHeeJMMXJSk82^ zPcwb4uyp8`l2&-!kKm2Hp&M}aj~d+K0)n^K(~ga&u;|o%K)o498{Hz)$<=033`Q!5 z8KpYdb`2nt!S(P9jn5EU%^a(RHho=%s#)o=&cuVG7<7)#({TfvdKBUI-uAUif!*jF z=dWYd5biolGc;z~q4-NtOO)&+^sEf5{!o0l9dTWSUqhC!jt3$I3;WOT97)}E6Y}ht z=v9C9!ORAKM)%&$olQ-Iq*TAg_|`Mh?=+AL-{WyY`-{*T0C{JCmHzN^cKEe9m2Li) zAJw4KrW;z!!TAY*bg|Qg`RN1Cm-rdJx`Qzl;e2lc62*XhAzzPj^iMCvyx_xlUY^IF6kPqrXdlo#^d|$8ctog|>b{K| z`i0MTEOyrsBiFj5UA*d*6Hh0LR=zPCBKaijJbC9^%^|y$#Mzi z4cq>8*_DytzUkD{hf)RId*;fA3-@2+$j}4IKMinh+2z{gp44W)u#vQ_s9fozVacyI z_9}6xt;J_+GB+LISm{AmpFYiN69(C#L@Wbm2BtTRTKDy4L=dGv>c( z|ACl;_tt@m9B(Mg*lmp?ySln?)o`!?fT~B>bhINRPi}+RA1yHwCM z;g$ly$sLd$k#<{}m@5`egF6SJR8hv6Ck!{_%xW(Ls0m>*o`J8{jMA1CvX7oyh`&M` zAf<8FbnNHRIQ`dFYb#hV)U_tZh`x~B!3~HeNaKXfwB&h!qLIg1BfXZ;o#;x3-1S(l zHtmtyhw1ZlE)&YE7~zQh3S;)RbBkktBW|GjyArDI{|!8{{ARZr{2=&sqSQVuZdf2+(iSYc;UJ8|?g&wN{3rpTCE1TPzfp%{!3CbVmR zpfJHI>j}zDg(w$3B-49=_mjY}S2I{Kl}GE{H0v!p;|~$>VAj!z+MH&@$L4_FgKbpy zq{5GX5g8O|Yn|YC1pLjtZQ7+diYVmO(*N7TQ_kJwF~@_>(iiNnly2hd5BIa=_CvpW z-3Hr7DSI@3JYnMr}JF#2pb!{#6 zkOSZn)7#ommVG4S=!Lzia{wk**5)5B$L!u#*y+lN;nQ#bmaO|)(VOv`_B)3R2;;AH zfDx|aqwLA0<|)_s!5o5lmKzg}Cz}3*w&N#64ZC#1XrXU9`JVZ??#}FC-`K6ydBR*i zV&%U(hw4k2#0dl*odv3CB`-kP-DiA(^9Hm^_ae#P&vUN_rsetRUiWvv{C{g$Qq)j| zE7y>>x=V+`G-TRZ%ro~R>vwiuU8CUdlH!bV-I;_a@vYWrc=dDZ@-(GulF`3T;3Ms2 z?YKCjQGtQ;0dkncU(}lFoS@>5mgy~C+=`v9{}l&6emv*1B^yE){BG>!JHy`H5SMt6 zi82al_Pex%`sHFEq`Xbn=21?4XI-(2=gXu4WSMn$sBokO_GvohxZ64d>&O|9sgRAo z9A%j1U>T+jpJ}GOK-)+T=KgU}0aUtnR*t`=_VZ49piPZQ%qXmS)s^2iW z?(QD|h2>c)yC2r*k4UUYi$Fr0vBZFu4mv#=KNDccxG&eM&h+tjj1|t6GS=MB5^p`g z_h7;z7UtxpEOta~-6yKw$$R5=?-GI#FgU9&lB1)YB=Cf7$SMJpOdvA=m&-la6y^gdTh@9kZhuv)^)^Cy_sW6sj;oIX6RYxRvV$91-ZvdNU5 zpGu5wggd$yVJ~hCQI0F!Y>h+$)kKh0bsWd{ z48%@6Ig1$oC^F$o{n`D^O7xfASh5e3!}hmN<$=76ggM2VFVTxXwe9DzEf=hd&EVhf z{@6NF^7rQ9)%83HKJr{wJAZ-w+=FXhZeP40ID6j7z`LZxs6{8zG|00+=wkMgzR6HS z%`6*R^@oeKwYBR{YidXBO1JPCD2Hl_UbmCoE-HvY$)>`b>0U%&>5>C*B~*TlHLtoX2-h?#}0E z$WU_Ww}>uO??;V1vHSdSuXWh`h=OgBJf@_bFI})l{LBIJCbAi&!w4cddiC#oSDN-7 zx4*d$TlQgv(>ue>%CAH8T5o@PzsYy?XQ8nefdniqTkzL zJ|vFn3`z+bS7e+kF9tV#Ux;-lj1QLfCq|qYp-N3!{Vt6q^!dzOw{dt}_F*?+bX`)8 z2R>-F0mtPiS~aOxk$!zmH!&fbsA*j(VF=O06ejgpG5iw?pu6vpyZbt6t1s%ACGM_q zji7;KSp;|Ov^+%H8STtmLY`xyS6mhZo0`0rva8(~PYU$AI`ZB6dco@W-Q&$H7${f) zMJ!^XLu;9qDO)yB7P7{oy{TI@244)TY@QQXTgV5>0l^kR{IS9Df3$pD=zoJgkB(2W z4dzu2ym)B@fT1+5{?`EJRVOh-A7TzG9vq<;jwPWDm7^^+Na<-T=MSCbq!V_n-%tzd z)h!mZkc~C{MnfrywK5mJ%c$|J05>A_D>ZR-8YJ5m)z7Uh`n zAE!=YxJyUpx#K-x9rF3}&G6y_1j11GX?MMy;^|sf=uZd=4W@x%Ke-c{(tVin!P4d!I$FB;w;#_sb zAg)EW+;#lr8$xkO`Km{U>fPoX=fFPC$cg0-u?A)-fpxjJ^rt{DJ7#CAx&icU8}5!k zY?Br*fM@9UUB9=ZA!LX8i3ORk!ZSkYdx~CUweS5VNRDuR=G?>tN!v|N+9zvmnF`zb zaK{VFO^mr_k*@K@naIYC0mR01lh=%1V|=iQFAuTLB-HN2GDvBiH3;lNbt^opf5a?m z@r`--W+$&^-qWe7m(Gmq)2XBd;XI2&V_4$~mj+gG$flnTCiRUg(!7zH(Yi(c9QN=z zFIv>}GHt%3j^4xUcxRTB;j%m3RLiCq@2u=2-W_e=yFVob?G>LF3Mnlr^`;q4a>9A=Pe6I4sX$*k=Ik8mj)`!6Rm zjz~#F*N2UqJP;ef?%d(rSwISL@jCs%wuuB-Kgf%yaAdJ~HS9qY^hEu81~5|w$+QTg zJKUO7R$!*_GIpK2gBaRd7C7)aXi47u8K5C!Yr8m9ZoM4IoLt{USEWF$sSv{rLO+_3 zHB)-jTkB}&^wQLZ$Gv&r{)Uc}BQ>}eRlOC`XTch;cOPj*dfL2?GXNiYQMZCeGLQ4J zR8LZk9q&`jGT)h57H@oYBlcv`D@Kvv69%pp)ttT;T|;Ff5af1XxTB`OHP0M8)3keV zxHG<_cxom8*Qh-3F=vlAF*SR3BPK0>1d?9cz1B@t2%xDQQUa{?b7MOvpa?^=<&o9w zf?|V_eW9pggSfAlj|IhLn>jTei#FKZXw=Qarxv_#M+4&$;&M1!&9T-N5Z-qma+bi zNw_Y#AwIyd(;`nkcslE<{p{ck(bsI=t=krU^+2W>@)K*EdS&vy+V<@pV)%}O($*%;ZsJS=p;cmU! zW#Y$C8e<2+xD~nS*dTqGKnlAtsQGU-0SK+sHfR6Y8>W7}_%fjE9;C8lR!dh2@QC3} ztJ8k<(*k4rdS{3edS+|+Xl)WJU1OHUfGj>I4_fo5Roc<5{`z#;(%awDJ=&S6G^7$1_B!ww0eE$$0B#n(p#O#3D;oSYSLQ-QvM@)T|SxIQ1f!WnCRoY=dEK9%gxxB z=r1xJ*QtF1dOk?{gI``OQhOjU%20b9*LNH%QArG1ZGy<9>fW`TNs>J98K^7X6$avlF}bCGCETtoxWkA>OQGVI9e4VvA{td0jCK+bvQo%|g$6gk^{) z{>j{&J-5Lpz0&cidaRkHUz_%})sJZB%{h!|c4576toeQfe4o?>G9;`!a@C`WUVi;)kk4@mmkpJ1 zYh?kGdv^-l*Gp@(XA_c#9XMFz?PLHkO#Zzx`R0ahI`tH=0wmrWYq1zHDFL<_sNqth zWi>j{Sq+}{MRqUxV_IZHbGGQt{hzIJL?8+c9CXkBFc*PcR6XY zRG{rZF4Gx{Lv_mV81a^?rkYJzXfK7g#$_#`h+`7VH{KTIWrWrx?XfTgN=^Tc(#b7< z7Aw&BEtvGI{5r`&xLWZoq%%4X}fUOmHERIAeZ-IuRI#Z*r~Y7 zsckF#Ya*fdP95uQtNB#5>__LC!sG|skHth_YrZzYN|7Lefs2guHCAYxs>H(7vjP}_ zW4&nOcm14G9Wy!AF|#n`6X<*14Ocd~jVe&%hQWQz8_k2I?OVk~Uy;Lqp3EZrj~ti} z|HHlfb<(x)u@*yRckRNru!I0%Ew#}SA%N}|8s4-bd22T_^;$u(m)Oidy9?__tN-Mh zjr%O+0J0KnQTUcDq`6dmWn?lS=mh!Bg!u4Ji=ybjqBcFKR>?2UeIMu(=kn1e5v!aZ zT4Xa^^+mom^O9d*GRs?MXL4_y#ZTwHEqTu0Of=(gl-U|(W+!x$0>mKVkTlOP{w>F= zBhU_7>ezRPYtPP>R(#^qKXq?5{7CEJ`G%1^~ zH2gZQGqC4_D?rh&f#mFSoHqT_=NL#17n^CSs-MT*QA=xz(Djn@8qeXSTOWC+m$o+J zOg3#vZxiA2?Z#4GDzzX-cCj7J0GGY!`)D~Xxdr-n;pmg5r)drbXg+0jT8+*Z@N0I0fa|;N6M^*L(n^QX zhUz&PBVmKZ#_gB`JovWx&*^6e#LY~uTK}SkEL&z6*_s0poub@1U4Pj*0d(kWa_-k^ zs>&5en(3O@EMAW8gZ*)X{`FPnOd!3t0OXA2{RwV3iZPIJv0aftA!gies#$=Jdn7KD zb9T-~PIhCPT6SaPvH+7*-|n`Nr};ErL-|Icg5&OrpD<@f&DH-^QTXc=vo&mPYH*G1 zWY_J}P&up1RpIEiX4=YD9Z=B9m3L~P7k?0PA?umH6KTA+YCnAY6w1d5aE|LXh~Xj2 zP$-wpq?1wp$YkWBH_Q5Qk-cXm-iWp_Qy^3?_JpXJYio&Y%+2A zIcsa#_F(r{xhK041O9hJ=y#|;D!RGh!7nj+NJhCcdqU0omk{|MejVD|(Ak0m2mK`i zqRJaruc&-abTdD)hDGt@*ovlw=Y(Y*kA2#pQ4aztf__^q*Gii_cDeos!i98z!83!Y zkx(A3BiX|3v>Py4j6&yv8;TbBp2ykhcZ6b4SWPVti2A?28y>>O-K=KXVvhw8MH}e^_S|0auCHl*u&XQDj zH3NCmp1Hb;3+WYiHBus`i4WP?H=aIy3WS=uy1Eumr^~pnxc>!(9e(SvF{R)wcVJ>^ zd6RV4s5)XUeEy6csw)hm1+q}V4i3Uk+YJ9TKB@E$R#+ln{*>JS9@yF0IZS+c5Na9pfFM z3;X%0tDSzK87gVtxjF)SK4`ZB8@P2xq@XVyOD)QoQ8dXC&QjV7C7rN%dCdTm^#kn3 zGQdklXN*aUm@C%?#PLWtN$ZJhY8pdJBjja{8Paiu`rR z5`Hd}E~DzY9{8-+mfwzSJSnlnI#rl&eXZ z#NyMsb-zks1`E1r!_-U1i_h6)Z9N%%(ehrlRf`HeTN~A(T@*hRZPZQ;02{6tR{9K>RO2j1wJ)q zr+~=sUz!D}L`~|;6~k}csGL8zbg*freW(9tWefUsGh!zXV%`*E-)pzB%|_YDX|zB) zZ*uK0pK20z@XHU7cIu*@XiE_LxW{&f<{1?J6BKFJjw&S^Ppzdjofiw~=+&iStbc$N z`w7sC-mP+-4#`^M=DJl#!zHI9GH9Rkv`(vFdMU`~>DJ>{+qd3iz#OV;?DtVGEBL{7 zV+|$hI)>8IP<5}Ca}KlVx{u(%VA}cy33$au?NcSCMir-9W*0(#5X5~3ZiIz1@C|6q zF9cLLUAa;ay|uL!#`7lP2{+3So=$bBNF+S}ZXT?%xwGn<)b2rKL|1KYv*Lq_f?!U| z|6>AAr(CCI+u{F@84vkhMN8oabojXKXN7C*{#e#e8;t$<>M{>QTbq-|Ju_qGwW#LC z1C-T$)B+}PvPFEN5TYk#+&F~z9o`BgT2qIQ4I0FCW9NvQwdx|zJVdA6Fslid4xovh zP!_PjyWsybFFVoTAjMIh5&;@9C-`jwjFb8<6w3|PTlt!V6+DM(d$SM zsv1pX;%hb+iiPHcqPi-Ql_dftuSkEI-o`o)2@8?abz{3Hba}GQAY`*KQ;_;^*tB>)SB3o<}vM#&yq9KpUlDJe{m!A682L95D=Cv16#F zJy_gmHlB%D^;Qu07cLRwVZ1SY<$hTfaQ7he)DC`;8k-zujZ7*L1c=q^TDQ(39<~sk zR-p>SAnt+mgeQexb(gRDX&n8K$?jHu(PYpiRX^`U*>vLZFlg1;%`v3CzD?TApk*vW z*8nrNV1x*M;P)$CX*`Ro%G2mpFLR^r$DGki{yM_p>GBUpUvv`$oB3;1N;eDdU)*$e zEEzG&x_CMf|JN91_r2U{x!s|Gy;fFYbE%@K8#h-ZofcKqNmNE$m^j#ndhw(AKTL)_ zFd-@t_ge#%^lQdS4AbR#G@@k8=CNNg!m|u=A}CCP13zV}Tw*g(Jr_`8jNgLB${Am)1|G>r$tRN2rz^iH;s1)!C_k-6mNzH_nlGyE{Z?bA@Zz^RM-es7 zcL9z!ydc*B*BGcP!FwU7-y6e9a>krokPP3#u21-kB|FH~eRhVSTqvy&?%7@4J)q^UhD*>EP-wM^R%P=_G%}IVBRn&!(DY`SX zxEti$SQ7-l;QHJjXesH#e@uIn|IpFnE&z|05pF9R63?z`90KEhONL)7Q#pM0Ua`F&`XFNp{HF@+INFgEm5Xn|g$ zs2Rf0GEYlO`r{`}aEJNC`UVMy4tY5j* zNK1yxRs}gd8yk=W->6^FLzehyfT#e!y~190mcJLp{8L@UP1rnYOd1zWm!Q5!ALL}y z9a3%V4gzmW^CU4MxtTUqqZ1Fa*08}RrADrTJ=oTuFwdxv&XOxD|- zI_n)h{j&cUxijBFrR{DPR^nBRT`j(M`dB%@R*JJq;CL0w(2$a>CKe|8aD~as_Uy3? zvu#6K+3b+#GH9eqaGYlZ78NFTFRfb}ibf!(Vq@5LBX2Z*x^{7O#@04o;!g1`kcM}) z7B4aRK?unDnq{aZ6v8&}!(vm7U3ri2WWJEC5kaVgK>lC}#2Qp?yp2)!3T!*x~)zqvIo7uxowe+g0i7hN5URodj^wKK-yodK#YZdb>WMg2yVfogZZ6hHG86-mJuJ zyFIY4{5s_V>#kvZ)C>gh3|PVYhc0xDo>!r8n@|QO(FZH--zJovG4aw6`0X5m&rtCj zMI-a|^#*71h+>r|@FRZ<^)<-=Li=x12G-ZHp;fA6ezqx^YfX~2lRn~1$L?2oOAkU+ zdD8}zL2H@~Q-_fe4v$jTx;`#y;7XZ|J{z^f4Bz7LT0(!y2^vn5?9`ZBGIuvj4Y11x zQpj*9g)kl;4@H~^|D<9>hP=Vaxc;P^2om6(x@+F$Ugn1Wo%_!cGmYiXyQ_oFRI21T z{dDoYJT8UREZ=|3M3Wfh@+bV0Q+%War+^^dyV^LlGAReoj6V^yn`z&oyD9fIk<#|y6 zyawu?YGQ!yT^9i2f2C(u*$ibar3dXfWV&|R*3shY9GMV;XhIIlE*KxUqBFJ^gM zAgxva{8tr1cr$&4gVSMAeY6dFL3{e8Jiz#`aKz@g#HEC1$wvst!S3(m<*Er0j|odN z#*<~2b$@F{>olA)hjAyHXsq>|q0;PNkpFNX8oS(d^66-2c6xg?PiQ;nxBdp?ap!Il zqxDkxiS^{1?r4x&e<2gkOriNB4%t_f*xr;IC^os-J>RWH`iO?llCEtp55nh@=Xnl9D~l* zXi=GjoOUdkQg!6u2@K;!E-}|yVs{FT@=0V5%t4Us29Y;YRK1G$k(oWvZF>x&T7y4> z9_+SyNGD96tlt!5i~qSfu9>O`M@SyN%`gB3(krbrGn;y?KUpM)Z3fu6@9{`v4hhu# zDGx4E=e_dj&|G%4bt4#^(L-Y`b>uMe?;m27XR_lxN6@WQ?+G%N#E@P zaeA5cmy|LF2L!UTF6tAf6dU|jm0!)Ob5_%5De94oQx|(?5T1EK7~DBLESh|{C0%-i zVUcfv1@SVECul<#^GK4vs!!%K1x|W*Fx!UJR@cpf6;qM~Cc94LJg8cH=Cpg5$*H^Y zQHsyZEZX2i*AByzUZo^m?j-U$OQ{UWty59{_2PmTuDr>36hDSn7cMokIS%$+{iN!1 zle9sos}dd74eEfzs!W6iGyAyOj9&Ac4{w=YIu>v}_9SlZN0x0*sa7So_;5UXwz$JU{5ru_-P@9G@nk7EIYCa{2ltdwqY+*7-nh?r$S|I7XmL4P^#)wYchM z{#B9sh%--7`ALQOWXU|-uJ?T%wtIQuPHBUs#Ar}}{x+|eRoC%7WI!u5n^}MFE&RFO z9u6j#Ay3h&VUM}$XTd2xQTmaTdjNz3R6CaB8&ln99aUW#Qu=kh?-tM4re(IAabTZ1 z$EC9fmsylPl6Gc%DM{JD9LRB%p@^hX;;^c>g;qE42d%P%>0t*;U274f@yW3*8oiuX zZkt%m$FVssZXP1Y-`NpG+;mk^P`)$+vrV^}7zXnQ=?0b6?-kr&9-Pvx58lMU~nU5E~E8I|BH@dy*>64f4lJQ~0)J;_>UM zhP>`R|ES1th3@mjb2Tj=ZABX+R2OxAc^>n2%5MVpZs$+Wpp(Wa6f@MK^P)&4xk2&r1UYCwY$jQ;jvp-wWy^kuOKqmI9BQ>({3cz6WbeDKZdXmU>ouWULAN zjzTT`WIeF+sO8duyMwDKOR>?5r+@z0%}*9Gg}vF;jj=X7I8-+|K-1*z!9GriE-5$P zbsF6zeej)UeKKU1lwp@xr~5&q(d!n?*zWfJR$7lAUi3y~$?Y*`P|Su^S0DLvUS50f zfN-jG8VGfN`&^@&8mVFTRAoOkNL=M68?PUa?!ny1qw+1)4U4PK%ctLSP2W+rS-&K& z&_VVQ@6CR%Y0X=f(Ivj7o(@_gJ_awIY>kF=GPabg&SHOa7LfTDvZ8+P&Rq92g+*V};fvj_-Xo zbcWqwwYht@XdKi%m)$iKB+42A9LR^iEHmbnj-n!AEU!Sg%k;Q-m0_Qqn+Z_J1K=Bn zKkC}X2l&|%{~zoBp+=oKPdJ<`>PNYk0WO9K0-F%}1 zain4scc5rmS5*#UUdG7Y+(P{ zg7y^WUV15#UBZqbBEb!W>mt%y7x&bZRmB`*aj0;S`B2{Ig`D?E?lX@_gvkT{kNogS zC2-%S?Nh=ff0wCHZ^?Xj99bGVZldIjP~>t|%i6qfH#1ms)1h_ZePE1YqUCm;fhEkz zc5^VkXe_u+@4fBwj#U_V&Gx{m5v!#1;qf-T79J@`R(?t&sI+Zn5#iAAawtd$4zV~;#yx36O!Adej z3fWWOW4S!lD{Z^PRdqzSv->cwK5DZ{{ojQr_e^*+Xnu*IIGK)BM%~nbl`Dw0Ji<7P zkXlI?ujwohUDYEq)U_*<0~W#e6h-}&C|!y2FXUGMwVQ4gCP=#^=iju%#(X8ARh%<| z?+{F}thA0ff(U-^sr;34SCrhOjXOT6Qq9OnHQ~G-d(&>P$HX+bs^XH(U2nFxv-6dH+w1BzhdF3>lQ zCpCE!1HyR9mAR$E^z6R(9(j>s8b#A;UuQY`9Si<5f$&0s%uQitKA#ByVh1NOaZg}nQo+^}KFMr_VV+nVf~fjwW=S6Ct%sX*L-L0CUI-{SLH#KdX42e*FreyW7oYw*(ksoAfA>ps zsab|jrQb3-fUr#eT{EpSoHwW|e5Bdxoqj~?3j$Umaj};-k7(1bq-43bib>nq*anqa zhHRf;8kW6XG32ZlQ1T}ecU*zT*xUBnUCFmYn;x<>#kNyP+Xdwz{m&&JjMl6$4_VUD z-O#LpmNVT=EV(3RpqHfkvWdI?8XClvA@lPn{$|Dl|I;en6S$YAu8SG(rGJkhL?>v9U(fgeG05=ysO6APo=3Lfc zNQu>Q_BX5BHxlFx>}?0?i9!7RM;yUNN6P%?3p7sP$#lp(gx>S=uT!OF!a8?T+jG2Q z%qa}NV(wZpL7q$p=n}r*qxujOx9muRM(BP#Nu)7y8ItDyL${7_(%?8wuio&nZFMAN z7muQLl=17*nFh~Mst-FWpp%7L-Ej?dQ3x;My-d`@-7 zb<)7y&kFGS)y5>y_(Eod{ax9ClKWg8xsKWTM+Og!l~_}~koL@osC@(2YI@G$4}w_5 z!@q!i(SO0H)&3nut?CX2jMrfPaCWIIHif>~Wi1yeYL3N@DxDMLwRcw@|s5W{BC|vX)v};=5e>5acY= zNw@zt+A^@^(8VRgYJcl%FVxaaW;rv-jiekn_Oq|{j$pQ@7tFdyZ)W5ZiVoZ(DJkM< zWZ0uuauJ0TvIt*mI*Yg*%Zu-nwV&@#{r1J;90f@&L_tztk3$4Me7`XSGu%8JOx^l0 zS)`IS^_SuasK;K~m`^>2_nmM1B;ROd$zy7WiZAO|1Vd<9oCyE6_4>i#}^m#)5- zDx|2djR6wQl7i)U47qG}mH@H4Cn%T?5ey?tBF`4_?DgGa(vLt5x{)906?Zeioh zru_kVUgOWd3|o@0MP)&a>mwu%uf?5fI%>D7cwtd;L0g)o3SX=P83VTS>+p5IOPFo` z8pKm(k+y7`5al-q4&wr=RT<=X!hF0yv`8~ExT_+rxz$#}+{q?RW5biHj~W^KvSr6l z(a%;wNVxhgi3y!~1Wu^MvjuY&Kd?~@Zd&r0a2vugSGks@ARYv_!tFB^_RB*T3ITJ}wk4}a=3 z*ZptQxJ)cscI0aYofkuIVrfqx)z)_+W!AsFu@K=HO3)K}wx4ZHY)95|S1L_3xGh|U z6CP; z=O=u2jgarz=t$V1$3wFLEfVxW4i4R$j`iQ{#eh-UVb_fSkqiRJ*|1Fbk5bK1cE@8* zN}g{(Y#=R)5giM!d{LZhs8xna>^j{|Yv5DeyGo zE}EKIsB)fNOL%^7^N)eM`+IY!cR$u0l4GeMq z%f~pwG^~Ty(t|RMJK&7Ps{Ja%00>i#WkPqnBz~liJfpoI|Vn}j){SM>KSbt~_OJ8bS!K1SY$N2Ddkw-_kG^-wlqHV4vMR6pz_{NSv z4>CszlKmLUlq3^2B>xS_u9}H}{11qI6W(&_m#ws=H;%+KM~W}QfTs0UYDq`^{yTFE z{(djSDUi%y8}Vt|og>|UX54RnIdinT!wh7+0xu;)e?*?0OGMEN|MKKG9w_;go04qs zcp2QF)tjG{ZVU9y15^d3V^y}eg0QqH{QbikcGd2c0~l#N;OH0&VRNc^c7RA&bVc?_ zCGROM5OGd3i!^l4-S#o^E512%L#S0#J(QK9a4FkIE(88wM3JUHCCy%AJHHN~k%N_v#;E{ zx>Bk{{#sQs%{P`oNlf!+(PQbvq-N~>a&&dx$@1b*%YvTNlcC+g5q6WcpsddbNNypo~1@|5qIl0$vy~At*Vy>TFM(M)93&M)|;z&tJwHFfmys&1?!Iie`!gj*SvZLgQ@xOw$+@ zYv%htc6)WabUvjO!7iHCT_oD{~(&~EleECJX=sRfmcNd+AB=#L&b;N!@c+9-Xq)VTfsCS5y`rXLV_$0X-14pxMsXbcw+ogbkv0kU&$5nOx zbM^=+2O8DV2~7{RGHjH*h2Lx(wi}-r3;{SOxFM=H^H|X5I?a#L*&LF{Lgz_wd+NfD z+@b^H)P3DC;hyUG_#zS8`$CUwrYzGXmx6r{w-a;~f8+(UlH{chAI8XSaZYK#u2p+2 zD5U$(D;Zc^8Y6>>7<9Qchc_}w)j;`PVsl*p-o{N(Qav`%qfLIWo+G|!(~?F7iP zf5~?%k+Q`+bYwhHob>){x-0IcURojYPfp%PL%%0%Py>Hja?{eahOK&qyK&8#w zQ zic2v`A4Np!&PAiQ)oFcm0x>xpqRz;Co(k7PKWOHRc-x>jRN75iKMv2WVoP4-Q37te zH~@#xB_;TQ+e>RP_jrtA>~Bs?*4}=|RgxgLVbx(Fs!s;x-{)#CDbdy!&cDkQ(;@A8 zhAp+b3*#o*-fz_OIqIYKT^k6+lo?;r8}N%I+61e<+Z~%Jhd>vz73}19gQ;nnM9tf% ztEA^A5y?{XiUX@BxB2`x5L1n{Iffl>tU)qyv5Nt{M$@yNvLF}MLVPP)zI}9qtCwLzWAS8wySue)y1&8^tHRM7v}zL5YAB z0-a08Sg#K`ep=iU6AV30o{}Fg6E%gs>pR-K)Lc@Y%oadFga`{<}L4a31QI`S`4p&rKIA0c(GNxmPGnM^BXwaC-gew&GDCFRBvy`{ zM4=(bs0ne_7s;D6`tmUWBJrM)W`}c28hHS(->h9sA(QV;rArG*$D==+#`1P2`-^_t z>a?vdYZic|RCBrri>f*FS|?3*R%Hbs)9*No(f!CBYhLU&aV4^gaMwSoLE5d1n?1Io z)WUbNyblOG+8E!gz18L%Rm>Y_N;iZXY83L9;}D(KJc?)4{Q2_+Jo{v_J(gG>nL)&) zVZHBuacIp8*g5#j$x}A^o#GtGcY-ZuX@hE)|7Ts$)%jOVn!n1HG=-vK2bru?YD7r! zJXPm-)M@ksVPuiut3G>yQn;}sJ2aL9T?TK^&vXi%qpR_TU%7wvwI_twU>lVMl1VBY zeH%ApN=)ZxWo0C(vb@FV#=Su8IOJN>cC>EyqRR{G^BP0Yd?lTgMu)B(*sd8TG}9-xAWh<6ac_c z=_zibKi{9Y4xQ*;h-`;h14qnucc@F8Qb=ci`-Y)r(LY;Rong4Rs?2g>=CEaVI^KH>i# zh;h_^BF1HlX#pMn*!y-@0W}(9Qdh%*TjA{2G+DrPvgNU{;^r5m3curL=2xcpL*Y(4 zz`~!9bV6qlivVBi=qOYQQ;2Z##EDIDafucV0vs3~L1*MTaEtH9-_^l;I-IO9-1;u^ zY206v(n9-nS9jAbI}zZT+42eg^hnzm(7jG5E#WU>&wCpEOM{Cp8ml9NxcrQTHGj83 zaRr(DuXMvNITsFnODJ6!S4_vedo#VZ#V3Y*vv>!6vuIcT0Tp{;%NOy+)p#+@`|;yK zx8THR{^Kf*e=c1f12fOEOj6r#eibA!%!aiN=3CtT&3rU}*ztB$dc(Ik`8@p{h`=Gs z)lRR#H-e2?EM|~EfqQ_k=x!cLIUMjfMiMi%jxiYm##*VN7VMA0RK1W_XvI!eAeM5w4ZtxeLM zUx)pxlJ&3u@_!C;D>jRnxuR!tQNMo-GlQ2G1MYcJmpPH1$g4rbG07Fzc|?Gn(rY+hdP4nI`~y>MHKo!wxOo85d`Eu04YLb-WAA z+!34>d4*2vRo!`4w-T(3vVXQXX=cSJQqEGeR^w3TKY9+X#6(oN{1XdsDxUu{K6Uc1 zp>`RvbG6>0qklAL83Q7-R9f}xp1OF}gu;#LwQ8n)Sf=*Ze5A}l25I!=D#YljTlS8d z<*Z^4ena)@Eix=RSSm!1$no6YbGM`?>NChAR&E+U>+#We4g&LHOl2%2W6%HK`K4bl z24ObC4#_=m!kyzNW+q3Yy8p!xP|NcF@b%qsO)guzDheu9kls`Tq=S^u5evPFbO^nM z5_%6x6r>ACuL6Q}2)%}m^q$ar5kl`hH?Yt7zP;}`_s$>rrOhPoyld91S?hV$VxaQ8 zbuIppNYcRbPQn*lD^HU`!d1zKfnh7G20FHwE*TpWc)m3w4#H42dF6$oRw zDLZ=yTcjHn^bRushXHhv{LjPn_zS6vIFhFA7C>u^es#MPrPThetJG2fiiI$HzSmp` zkp`sx<&zp46JFJOHz!*r+yBCiuw?Vm8y{K42>E1M4O(d(vH5FQi9p+-azK?Uw zXm|x07+EF!i_u`X-|LI=p#8CSA#n{Smj5@Lm>PgCShdi#<{3n^>Kd2FW{{k2n zS0fBjo&^OtXy3p6h7)i7#Bl{SltPI+WvYZI+2 z$nX^>U^=LJuzF8AW_n+0(l)w6-6A=pi%FV--o%|v*H%y<9OF#kS$)w*jqR$qVbgg& zUs6AIf7%PO^;Hu6gpal`wrwI!c)x38Z;Ta#49DQbA7bE!X7Ap;`~LmAjU#+vVL=Q2 z1(zJLT8w#L)b}a<6^Qj`yw1_F@W650l`}^^Qq@)nLl?n>W733O*1uy2GKD2Pkv<6k zdOdrS8?d;Q+)7F{R;_rAcMJYMmSkq9PVJGsN9FOKLFmxX&{%~e6noS?-y+3>$rYZT z&yHd4%rrWW3fj~y*bt2<`kPEsnl(~FbL=(^wvyhIr@-4g`*&+9|M!DU_3m0 z5TtlHO!4ncV1Vl1_cM*(a(zD_s|-6MH`(IfvVobN|EB=lbodV``-_5e(}^#c|Ib*7 z2{Z|b3mT_l-lNtC`@&t8kl#ZcK2_tO5moS(nzmEJibSJ?zgnF04G}oBqGr|QSZhkq z*8A}wMa#E*>a);^c9Wh#xasAbsUQF{bHbBHCnD-3dW-hnXQ;;)r-#Sq)j~CcM#p+v z7mWZA3(@iT4{u)+S^r;+Pk`>T3s@{tQX}!4tBPK|D%3c?bG?oX)-+mdMxl6E z+QBzYl4zqlE0pf_T!PFx)cQViOVzGUQ+u_2GQ-)p)7khSW3_Iikq&Gz!DY`9EISoyL>PJ;iP3eOJ zV#N|CTPm9zG&5s5q%?1AAT}Zl7?PBfRQ3IPSm$L>aInecN>996Y76o8KaOC^{J+eS zrSk!i>rbrk7U;d$LxX8u7|ciTF%+YSf^U$D8@k%{Js2UZM=(7bI-wMH-H3Bj4yO}4 zL2pc3#64D@@!viFaEwR!eD(PqR^wOqu&S_o{A%t88IhKz8{X1-5(Az_sm6oNOlU!%dW{wy|OSf z`^kHu{ z|0HtU3h-X~&X#lL1MN3hM3a zOd}$|*Li;jtpM(?)Nc)-tTlsA><_vF+3}6rCEbyst^V@4%_yn$OW{sBri>2%rK^nF znkL39w{@69+85Lxh23?%?5daK@>`w}6|!p5j>EdeBGK2-oS2}sFKy^qWVsN2$k}v=Mn0Rb0C^7e~Ti(QU3@97q`h4 zuGs=8s%7Iv-iK*hk1qY`dCuMW%|S~@@XrGlpBrJ=v}&<8*q<-6^2U@;N32KbxC#qH z{&f}a>r@+w(5_%HwYR1g{*RXyiM%ta62qqW9NPez`b z)FZ;9s1{Fl2cM`=7l@+f&OT`|e=STX4g;5w*{f)dojK?v5(gam<+aaRG}p8$^bodT zm*`NRQeKtdqKE?29iCD>AZTe3sKyz34FjU}X__C_KGjvYD@-9z;p+PS2=q+-^Yqe` zu$BbgW>$GABJ_hr*cOMdzad$&Y2(JmGJhs$Fp|dbO0@pCxgaCiWEQbv09s4n=4Pej3x}dn;e;6G6AZ4)1)~A ze|svK<`4Fl;ahOzzuMp+^lKcf80>E@@7x~j>Lds=AQX)IwIif8kNy?k+}Z8QepQNym$|G8fXyQz>D=jOr#-`D^@}%z-6$X z|IC>+3Vrw@JOzE9D}1dxg|S!h-Q>SD+&^c_#=_zL>xP^`^{-MoP?drxyh%?7!~4)O zqa8lRxkO@Sr2%nNltOzl7Id{_`N`N5m+HJ zpEQ(*gfbhe(-6E))^hgSXh{%Hg!%Yk#EyMgy8XI925AU>plKX=b5J9}psJKPix3%7 zCnQkgE&&o(I#&FKfESS*m)P55RjQSOqZGPAGj>T4wlS1q?y`_?aKOJ^wYV}>m-BqN!KcQEe-uo4B)KhQW4sw|+Y24&)S9k2hby2IGcw#={q4&~` zfckfu)$wh-nm@{At}%P#r6!aB+eZ>&UW}`JmQ5ofgxTglEB`xjXZ&gb_=_*!9aoZ@ zKVObIw9@~FHdn~{^X))Hd}v`Jm3TSi75|tT1yLBH8GrIKsaJ~^ln8uQV>HHJ59IvJ zGj91rpnlJe&yq%;xqi~8)i+57us!muZD86IV!sxq-2oVr?pV^Q2BJR)>vceOt; z>bygUT=Vf9JiW-MTJMd%*cmHOsM_(xv!>4*IePZ2_IpUe0mZ=nDz0rALRjv?cqR@nv*;Y|?|Y&pX@1 zHJ!DUdTftlXe*cJ@B4PU2BqF+z7#AMJZa}wgC=?MU{3u5wqL`G~l3mz%OSTwKLjQcSTeEV9e&RLcQtY zOqcF;KaVckzq-XE5aXUiaorTm*toNBzK`rgGcaVFtP(3hGbkZm2EeU-zHVY%4~wqj zDF-d`g~=*R!t2=lSUdBjT9B19q6H6i_8gt4H*xl01uhsth}8Y+Hn$KF%hXbPt5tUp zeFSp9NRH^4I^kCq<4w%l78G=3XPW@NH6?%l^EQ^jb~luH^hr#rG$QD(7tP3Llm4;T zD-&j?sW}7f_^TlmkBRGPmth23BG8gdGm`=B1WU@7UwD)s@3$wjCR3c8d5OBeCow(+ z{nm--r^9hs9OLCoLywgT+U{n)(IILk3+6s(oH(UnU7$}gZfCtYKVo~YX`K5Z zwU4f^=i$tsqaij_f~kQ`*WRDAm;<`I=jB%Ca`cK-JyI2x@7pyGEUH}B@jg2(sXqw| zOX$C^vha3#gGg+s?pc>&k^u3{2OXE>S%!hV;N+p_0<(}Jhzx*ncqti*{{ zIwy;`Q!m|#poR3kBkE)iHMuX>bgOqV3!NuQ`E4iYf2&&P_cLsBKCu8L5lqmmC{uP9 z-_CYik~|+M+yriT?eHYI^!n5twbU5*zuJdf04ntXUnQaFE|Otntb0t&6>4`%6f->b zY;$Y8P=wb4qrWc}KY{RfAKqKU?7A?U(tWL`W}=WUvl6SJpn)gY_*6XwT)i1YXlLGraug#Q@s(Ju^axWja)Ezy&{i2x2-s@pD{daBC=rLfuV7(K~i>27(853YS zF-EU%yrdD<_kEV3l&dteL76nMrK(fr`Q2Q9#^Sw3QXiJG@rUhPEBY4A6oG5Y;ytB8 z25nkt=>?z=sTlh*#DQ94(DticQ7v z-&u%0MO(^^&dkHcw-q!}ewc!r0h96tZizZ2fIs>~8UzgGWWnWjjvCDm8|JVXcycmu zjT_f)FO3M{#$r#(hu@wwM&Py#3@#f93fI^sPNl!GZd+P-J$!vhu$E%bsm&4#jnfsa zsK_BTnW4@=;tW*bc(Z!L_(bUaUD< z2zo@gf1x{kvXEHK-gW&y4Nk90E92df%Lk%MZ|xE*tTEYlzFk7y?5NxGy7Puyev2i| zT05;7Jh3O>g|pql8zmI|>=Vq^OAYF7!Wr$j{cyG4uBzr??z z@HCD^zP?)mwbHY){s>;&_aS@R<$P!&$B_DZ;~9UQ@#2i9LtHIfZOh{$WW~&`!B?0O z!!{X}-~rDyeNgOKEdkjXbq#qp!tDA?^u&xGq7+EZfNqcpA)pXOd~8bQe26oGs`FU0 zr=0jMdqgn9RZwc7&$(?_l>C(HW9SU|XEQ}p z+(HhjLwsL(LXvF%j~sRriHHmzHYNm6=!h()B=NzM|`gDY^J z1k6);fo!~= zu=xJdDW*Ktrw8!mW6rxuhNEnS-tIKf4z5KE9?ov)Ig?^SYo=_`{)jq``(?LiWFn9N zqmqiiZbj{ng*@%n@z*INJWq4~Yi#&#Ca+P(f-qAj&dx0z&ZlDzh`b43qTbV9b z0&24ytYGA6T;W<;ZTk|9!0c+85rbyRN;cLq7iYXh-qB}*mEL=z;#2q4Ys-IHv;>vk zST{j0M})SvMV%#WXX-b}m_tq+1VO?G5F8sdIoebHf!EcytFbTAAr z=WKsVKLFj-ZhloH8=6NId4B)sal!K>pwF0;U-7#P7*KJhSkBH`uflQ;@GBxwhmzb+ z#g@oisespp=kbTU&V{H#Q?*O7Z}vGUCRT$PfP+7w@%uvNUBhvwvv1eW{Lf{I5^Q9` zxBdMVi3{hm4n@AArScx)WbgtTC#nqDn|ALX70nf4w({R$-DHnntv;I=FSSFzKRGqOsac-pFq-GD#C`62Vm7u)U^KhVX9 zFItJE)dx#r6*~9k_Gl!sC7Hvv##zShj0e*l_01)>Z}?8_(inIL@qZc4l2~l0iH9EN z#|u=flv(>ek)|E|EIy6ByG6gfcY?bw{WTb&2fUcMv9XEW897~sb)?s4@ls}^VYxGuvoo-#vq z5xe!{9XC=ojq1MyPt_Oh&lj$}*U-CiUKS212WfJHKK(>C;0qekt6<>JY)#*f!aUZh52;q0P{%EuH_Ic~m+O#Cww{KY`d&#Db zz!nJ#=+8jqBDUp{zY|yFeqL*{JAz@iqwxB%%RL$94g3ad2aWeSU*!d2>(*O0Wq#2u zP%QAH4qfse^|3Y822aWsCeslU7&pyRHHoLI+qc9py@v{hprzP06J%bDy**m6Wh*lG zfrwlR3-DXsM);L4U6mxbjI%X46ywkZo+CSCrVd_giR+iN%dQnAZbZrE#3oVkg!NEz zW{#2)Y~zP3TVF1N1(h6K-|I?A-#Ao6DAb@SNMOrT{vk4eXf%pzB33XaG!@=ADG%6h zXH0Aqnv<_OmC3awn8qCOjDHSa_p z@z2C1zJSFiOxqb<%zCN>j4IS_K9uSoe>+1M4qoO!FT3eNq5h(s$sIBLb+r-NgnBLL z-ignl{2BepEhlQddxS2ftf-Udh~YGnfX5He{>B{2tNj6HcfRx_UUE>gxoodF#zSWD zMa8)!GkCY>5GEk|U7phF>ZO`n{;Z?9MlVc{B>K{jjk=T$wp>c}n`#2Lz=lA=Fqy_qP>RsDpqvPem@ zCyN&;s#fVmom=vIMgJaam+8DVs^5wdL?kpc*+Qd2etCAcc%}0@w!E_SWSrb#)2>Fo zMO`F(cTsedJ*n79w+|pZC)O{uM9UGJ>NImZl>s?f7VpFTx|-);IY1|}WDnZYa_Y#b zxbiujJtqJoRucslZSA+J-KP%&!~(_Aa0(x^bReXpW9Z%sM2Kf=a1cyLW7VyZeu4hv z&-H(o`^fsnkI?ZAFEZh{iYQ?PK#1VTx+$Ln(LI z?$BkoURWudbKK4n7CTFlTO=MzQ772wl2pfk+-I?plw^$fZJL@#Z!uyO$|E#f?bi53 zk8h4ZT;JlC*TH58e9bU7Hpe0+dV8w%~|d;4hJy&Av^Vr0h~+P zxgX#>1ktzbO!jB0QZh}|Jn*x07p246(>~dM_K@9>ggv?TBMq*S=$7w@>K%Zp$L71Y zuB80dW`@N!zgZfEy}-*$!SUxUW<3PiuX<0`urWOf}{8As5Fu3j<5tQRN z@FS$YL0q2MyHTQn^^i93#YR7b|cF5Xyr+;nGa&OwWEsd7hf>V6M>SF#Q`6?8RIs z+b1t*FgWIH{Y@B;Pr8z*a9L_)Chm`L4(VU{WjYLV%d>2w77SPe%dOvZQ?M)9JOg#I z>gmK>qz4TrVG&xEDFU54(H@*|vO7%e>75MK4mFjUs8nWVU#6HHDDK#64Ne1DKjGFP z02$~VnkRg3&CO!}K-r#$@+7qau`1v?jMRe;!+KtQOyRH;7c6fat6j9eB#4u|yZO%1L zxv(4O+Ys|n3-@TcmLSXl(-F(1$Kp9LLc$8ZJ8_TaA(#SipI`t$@nB|=JEP$@SoE1`HQ{v6fjoP-?JsCDc{m{CjnQ2*=XnvtSf zj+r^r@iIG(Q?g=I+@ij8ER-$i7eL>#slrStrisDvZasX!la6))Xw9~R1JzvYg7 zP#esJc)i(TH{X`cne`_6rER(%>*h)HVAeLeQ>flT5{MI9}PVkNk+4olQDKIas|ecvG}E zDujH8fGy=4Z1<+B1&CRT+}I3A!|^!XulI641WGm$UqQBN^TipX)<_yGa!@MeLC3;F z?NfeBD0ega8?x0hNp_363B?RYs#_6NJBY1fX`>6q;}+%HpmFb^_{#Pwuy3)ALcC+vt24$t*6@I%=TJEH` zMe<{?XCH*BBIKM9b#+`Zc=LAG^wfOI|sj^zQVh&8jq=(CRa$tArQBTggnTJ7bwoodZ|*dol5I ziyu;b=Tj5s!Ou`D7U;QNN#jRcdOpumN4QO$Ya$i|eX7GtHR{%AXF4i}epB?~dhc-Tvg|8=qx0Tr`uz&hGWKY!A^<&x zhz!Q2(y*}DZSEe=ulPH3^YitQM}`Vc;H6~?2nk?fD7))o3AMDRXgqAL!+xS&PoB>& z$V8>=a>*eakz1R2&jY$pgD6@`q}s#xb$d3yX!%ZeyH+u*iSU5x4aM0#B%02S=d%AB zqme#DV&|@gt5`3{Ol@1aS~~@9jGtiGPyKp6hrG$x;K@-_u*$a`5RddZeaMKczi&oI z%OTb{lVeX^c|D-m>xW%%Ip@qg_^VWkn#m3M7RFF4#HLm9=r_Bkfw8&(8_7op%YkA@ z;Oz<90_)+Gk?^MXiD{T5369=K7{Vu13r*<;^u|fehYE`oE~kgAQt-NvWpL8=8L3GR zmjc&HwB6d!RXP39btj;w@m|RtRmiQM7Es&AS7zrl@YW*x{j-oztx}x&El4CPJXe!X z&jwj+YzACYHrSBTU_S|@UyadAt`;mwTDFn#>MJwqq!BlGKhfZ*{c;sI=2rZHc@%tX zWAIabV!ONj5BZ~Tr_*WIY}tsWrI*J6vvuLcxuc)LBGv~;ZLh7&V)lee|ImsD(4VQ>vsIu_{;R@CD87fp8J}E$OC^ zc?B;Q>^zbOWWDF{p+_p#o1+bJ`{iP5#TGOVea*J~=33xg!x%R@`?GC2o+1@SlB60A z%n-rXLquSPkZB4Dk3X^&$Rqiid@NkM>mIRai+X!ku*_!If2x2y89n9$FSQfPL%%4ol42(~zs=&tr zM+hpeB%qA*{dJ3)d=-!+LC=e3>&_dG-eU3TEDx&I`;0z5#Xsya@ z6kPe`1QOt=QqHVZWArH1x8Z&zsCMs*?xx(8)9|wB#k7<{%W&0pV67lvktl}Fg{P<| zwJ{nRKG%|cuKFH0TzL9jQMvQJ7cl8R28l_b}wgUXji61TJ0=*`a4o~Y&VdbQnpx#l@)5+YHM z2|#FH#R&%)^CY*nImssDWHfgT$gsj>N-{DxlbtIM10cJPhWGpCtFXed zyy^qAt5`+3g16oH#HfUy$M|$fJGHDXFI!L#pQviRmV5b}tlrxt+|N#tYyu z$HVQ2e?(+te_S7IBbl~FTV3iz^Bx#i8Wr>Xx(GI~M+Dx5*mim5kowp<1|BDBei4uw z%q>-t3tl>lm<^%VIfP&vX?1L?mDL}fQ+?nf@N1Jao931QMfwo3Zt3VTDslr`G2juV+5W`Q5(2OK4H5 z`$u##`abh0*Rme3s?0MoX8wdk!}(Gy%9D+v=SeY1mjf+HNLK$JgcueR+et$2>Z8?;ve| z#gK%?)VSHNnM7~cj& z9IqYCs}A?467Ul}jDL50^6S^{!PCDhx3Ateo9Hs5OKeHE>+7Fv{=*~k{*N$*gPiH0 zK=hUWW4TtMjv5j-vWBH;nEP!aYd#CLlu{I_brh*BtuF^N?8}pHRNjPe1yd^`R@caa z;Fv2|C!}>K_qH^W-=}H8s>hjV>OD!6T zN$}AEP$P9se0eB%xkA0BG5k&I1TXgB6jNEVjB_)8GO~6_9!Tdx%1pzXq&x&9nmCwl z(Q_U4)iUB8Lk&rLq`56F@qY5`nC)GJ9%ba}w*>gse)h_?m$6NX>;DW-YWp3IZZt1j z>45{gKcQB+ea;Sy;SE;~9)gw8g$o^A`yUHwK8(IIJ`ERr+>em-2ew{r00z7K^gjjj6rRWP(<6cTN*@iI$H!oDE$} z(48@i27Rp*i*2$HP@-1*OTSFf04a7!4OUtOP2bYbTv`AM>+*5k>b(U>&XA3qXMwtO zS}|wG#iAH57iPXD9ZKDeS}(oh)uP`>T?DwHg+kc4s9W{9l+9kFv&P<`S7LA)6hu1M zq%o$7t?b`YKClMdL~mgWMwUq2HGkEi;#?aH?csM|t4b((`Xt&lV}AHa4~hv1YtvX~ zw3RTrFTj7tCQ20p2D3Rh9uW`la*3P_LQrt#zfW#s*6V9;w-w;k&-C|Y0NC6cE~|i; zgg87iVf0}81)=%u1?7pTGYjlfF3W`}Y7h`i-0fhHbda>X312iMVdD%JTpf%04*pQ^ znFH69<+RsS8|<{zNxUc~@N$Mn2NcZ&&}Ls1F`LYS;!no(l;9hbE0DwcmcuxPcwQsIk}_u!?S<${V_@>U?EPctpn*3!O<%H~Iu`@(hyOj<`B*%A=G7}FoN zYM(@ro{Qx1jt;kGw=jvQ_{Xs%g)PubCL zH5lG>*|E3QYM^ztLKNl$q8PPCW?J{$ig&KPd;_ehdUx_jn%~p$^4nIO&;|nn0wHAH zIA)bT5d4@GFT{>3M>^`wu@rG~}$5|&=S#R9;9GQA}?Gt&FXztS)Z$XvfozBK=FbLhkF6PWL_wFty zS6nP#erM3b`j)HRZWdk3PzB@P z9P&9d*Qh2KC?M{0?9aTDKNWXHp0b5yCZ1D;Zu^0PD< z+s8u}EAfvBPoe``ehxP1qEoS0yza$btRHH5?~yKT4p!l@%zTe*j8>CFQsgUs3?#vq zl4ck-x@U%x_Jk6-2ukGK-uhEg7I7+9PX= zbCt2VgMKfI?kzI?a=F`*N+E@$YO`sOv%r>sFw@ifh;3hqMz9r$MG~e8C6X!epzNfh z9WNC0mD~*<7P(cWmSEOV`xN6vgB^Y~;!b@2WSk7>Thk0y>Z*$yx8^i&phw>7-r!R8 zOjZ(AnV17bMu(pC{ASUfj2WRjTh92V#!Q@EICWut0J6cL*RM$2^!CR<)mjsKe{sG9 zl;?)(0&l`!dxBOB94(Yxo+_DlNe$D)3P@sv@AoQKFR5GK__lJ`tGQC%m6OZsGBoWS zZ_kw-5e`|S`!+_OK$93Hc6ycBJZaF=-z*pi>c zNHh2zD2g-;x@ns`{JD);U(%=-6WilQPSSnhd|WdEnhrYKoQScdw#qLTjCEr)H*WhJ z2Q3NkA%qU*Fc2)l3nkV!bZt-I90}QnE0+eoa}= zW&*%IWyr3{?_Tsc$D;^7kNlG>`G%Cl-YnKoOE(qGBYO?o><8?2IzqAIvpr_Jxq3F{ zit7MOmacQxH0^={6<4=_GM}*2#L~|~2K_6m8~9`Ep_Y~Cr!)gKWFnZ2LJ!t(8Kk`* zQ#zxO?QjkibVienObyMsU29;QcbgOC@)-PUVF}~VB)dTaO%)tgbCY&D+WP)HKRkJP zl-6>1MVO4!8|>v~l2^(gZ7dbWe$+5+Mj)3VG(huR^lIl4hueD6Rqk3xUpLcOm=jR? zRz0MqHk_UhCr#+%v;{!|pVj+~Jpx+cZ_&}wuzclI@t=06QB4EIQ!!>{W)G3e`cJ!a z{^Zq%&GklYW0s-%Q5q4krb~SJ2JMoyk-GP_8YxH~?45nm!5W<7jJUjufj%}= zSxw@#zz01m=eGyH!P+7xi#g<#sy@FRO>YUbmPilzrkuOS3s_}a&N@nzB z_8`K`iHb(v*Z&eiO;RQ!ag+NAW|H$dLrK~}E_-u2d@pCBm?7YB2Xrvfetf(DR1JUY7dY)>NXb>y4JB7;PHu#qZKrg>I zEROU?D&nJK9;dqSxSORQ0J8!4i=54&nk*Jz0NyN=_dB= z8G7n))xxF1P{{c2<}TubJ?gM_9RS|04z=uou+=85FDbbKJI5k*Uua^8*?)%uUc-s5 zqma+HE@cXeK*67_L+RzqJ9UAkg8WG!wL3otm#hZ*f;Va;%MBK7C49rBOb=`PLpg*O zmh3aHR-=BQPfd*x3uGjP_|H0kTz)gy=lgazqk*=Wqx9#rEkSR*piy)Q9KmH*cc0D$ znSYGhYXJE8W(iv4(;qncRN!V50B(EO^~uywtFI5eydg z*|RpPgd;CANYxIa6#TUD&*oIH?Y!&X0NG;~Cjkp$^rL@+WABX%{R58Oxb+fek}H4` zha7}Y(Q!^OtBWeB6{@CyMwTKLktxrvj^lBD1D&fHs17WcD^=L5!CHYFee7 zx9p<;d`1fcoDV~4|12fDc|YtdgHl&e${bHiSdF% z0e?ngWflR(hSs|~ZNJ58Vxn>-5FyeKspu5Ce+Sui529%1s&_3WuHvWkPMWE;Csk=l zn~VBYTh+CKIekiJO)qQDPcWns@(;UkS=$M{j^;0f8m|ppl`wBhI^DX)m~U(?;`H9O zBzWaieAo`(uL~=kZtWb8anNBaorR1GZg}*ZY}j3f~_IYwzj$FEwxvySN%`isqd=l zbFta@{jxsc{kkFyF^n^911{p|(CQ^VsT_r{uZcXav<@{EAvdTDS}Br{IsCaFd3!94 zi>W&Gz`7xa)PaXUTl&DrHlU?T=v|x5j1HLNx!y}(gV#|y4!H-SwZ@6%F=NsC4hrnr z(}JR8g>V9j#cv6M1TD>jL}iNA{cSp^O8iPQ2W@KI#G&w&-o#Q@+x3@^BJ>rLgLI!)JtK4fNeru z@|B*6d}d{i&S8=q>ZXRv@2w?d@KM^P8mPhz@Q(#1;VkyMrI^i87qE8mM6>IaU^KJ0z;nZw0haTL?}qV&KORBV7e%FIdh+u@mZOx zZJJxqAy?=*pZ?5a6v?09R;Y}Px$?oKl@+^fP7Ll#h4$!bxMV{=Lh~)igxw+O-(-pFxBkV4aHE&FmepGc zf0LxC58UdcfPKlxJTodq(oEP+w$roia*fyhj*KBMaCi zM@Dv``J9~oF0=$jYm`Vy_J(nS39Tg34q#)u#`(ZOfiH1)_u-kmD~lqP)m1L;c0=R5y@c9qnW&S0UW~hnuyLZmMhvik{!B$Kk~0cF-$qhGGoz zq<0}DHbN6l8J&F9tCy&_c$}KGp1^LbM1%YM*^jmFMwua>MyBjaTJTqfGru^|raRe} z7(T!ncYkVdQCva!jy; z%gGeLpZ$u#?tCE-o2$G&DCw zX)f>-6Zlw;QvPW_ZT{1KawyWUSD`2KTZc<_?695c$oQ)k-0PUrOgOxg{f_=DqiL!* zrMT_A?JnU`h0v3!cg641zCWz76NN5!7&QBn(ORALMYZk&7>|of>~Lca>OMDHm+z32 z{p=kkb0WSsk}4i3Ea4;9LwMym>UOzf%UIIc369hUFx}U|IrOUMZ;^$uM1O=H4F)we z70g+Bc5uHh*ZQ~Ex!%sGaKpKNWm-#lXNnLnls#{(d`Q5y&}6Dgg09Ie*x^FI{JuEM<{hQ=evCHQ>ue-|*wDFpqIc15cmoD(Se4QJjU z1WV9RL1ziMiv(yX41#l9931M2ip%*D_5^p!$0I_s4|A*ZauqMDA*oyJ7v1_c)?*Jr z94P9o&U6#54DM3wDuF*`62*JIZODT3Q(Z#U<80-xx5FI33V6_6Dcas8jV0U*s?MfY z`sn*r5j#bPNZc*uqh&NU>qAFzGlLs$W@@vs_sJLv(>0F>RUTR)x{ODUn+V?f%Zkc)L9iROtPfqQZs$TwcQYb<{yjL&C5k2x%3Hdn#WxK6Li@i485bH&md_wj=nCF8qC|0mE1((nX-H z>?XRmY4i{F60h#x*h?^<&^!Jol`ga@7!<|eu_<1Y*WYY!*zom%Fj-yn7c)vd0iU(Y zpPh41D|a_?V2)ihnzdz zu^4B3E4vm}*rJ=nP_|4QAeynk2tQQfgq&Z4vy}%EVUK(?VVS%*SBsxWR$2~r6WFxa z?Nu=K!Gy0k36AX|J6_PJjdeWPLfzphdSA*?Q+TCyZT@b^5VJ!ZxU*-)sVkS&>n=B6 zc$(U5i*M@L%&@NXpZIaXQ`(Z~S4s?b9T7I4t-bin`uhSLyi*}bb-q{?eP!z>whAKnN7Rkg(v?{g=5AWo zQN;h&CY7gfW7YT5aySp&;*{nlhZO`nt}^V5t_7g1|zH;P~aVqasZ-d6Z7S5Pwkq zkm>awhOzx#^@S2FZg{+g>|8uUir!c$30#i$-Q6}Hlp!U$^gRFZ=Gx^^%M(f>_i@JC( z?B9i~lBquh%$Ku?Yfw+E-cv0oH>@kCA=!VOix@iDENK<6Gwf~3_Eh)k?siCXAknHN zgBU!pyJH+yIVGD1r@rew{d(PJUt+!2BRr0WV$uEfvdp{b;&q300R_f;Rv9kdEw<Ksivb6luV(1A8f7R>2>Y& z{Err~$+h*xkOSyrkXUCMHK&rgq}JH)P+j$7`9VBF#-n0E_)CX0#zNBQjxkyOBK|PpupeWC zl~}0w1vx*=_o+Dz*F_?Y2T=k(v=n0UEN5zDUPFtbMG0}tABNVYnBdR}A7eZm`_#q) zvm5IjS#P>o7$QY@N3|Q;;_&_ZN1!aJE?WzzxOarQ)S5kiQo@UdGFjP|TL z(UE+&XF%liMJ0dsVPUr~bANhT*(kY0zb#>(A=KrU)4}w`YI)w;9DU*N`9b>rskFmr zBHQVFiEcc29!)VKu90)??PQ_kU*k!`jZGa43BxzZH>mSFPDySXLu!^ZWFleL@l{N7 zrBlLHYH%Rx;CFp-amv31x!^^Rx~0SphP*jHUf349Qt0rf%r_8CJWiqQ9z()0F(nwK z7&hL@9xuV{9tIK+-IUYT32>dSYWHtWU3EBK)Mms013h3jh6?6ECZ`Kb`vb$4ni@c} zCm=<2ukm0N&pO`vH2^=1;D%xgjgwF@2YvRhtLRlY<`>eC%7dtN#_9U|tx=M?)3r++F}?+!>I^V&8Py zQpjD6=cswzuL@0sw#WMTKy}R1o(4_RMc$p+gvlS8t22@2>m~qO4@|&9&IrSxqF|cw zy6%4;d2IWk*(5QA`G1@w-wSP!kFvyFNwVn&Kiu4tmlD-fqVKV9Be{(|t)qslc|DYD zKD_FQ`%PU94QiIWr*BVBhSI!hBb-e54$d<%ZVh=ey)B-(n|bc=5b&v-^xTogatLpo zf2SE9c=s`x%JHO|)zyrNsa;nSW=9KrXFOo^LKsiVYcxpF@tYECwqhu~OmYW#GF{mz z*8}v`!}un&9te6)N;n(YhschbPt@Ni=nNR@)L}@XDjoS~V-})3;kMP@Nj}{*JggZp zrZC)0Z!j0r1f_7kw9G1msZ{x`DbIF&VRrdBoKj#leDx|!80AUl;dWa{cX4E3h1<7F z%O77bnt^a4z}5EHcorHypAXtvET>11dI=;PFT$%gYb5cgE;Li(8X8)85r+oht1Fn{ z`A*1~`g&N@Di;bShF%gFYFCS{tn~g*$z{f6hapLh%zfUy?*$12fv#{|G`GDL}i|hYa2Bl z{7?~6G#&M*@;GaLMO>t_cj3|vp3(TaZj&VmqB5xBW>W-Anh_#+yw~lu&BLV{cr8?v z1j&UG5vt7U%=SlkO18%@ICRA1N;$WAS=f|TKQZ&D)Y z%G8Rbh^KAM`SPw*@<`kTz4+3IYpB&=?*Ad|y`!4?wzg3b0hK1wJA!~xrFRfPL8;Pv z3%w(~E4?Eiy@~YRdkF|6(m{F+5PIkkdXgLcopbJa@Atjq?mv<-_Q=l2TA6FkXO?Hq zMRN(frjHLpw7jwyAp8(Su1~eY~Men`ajH2~M&VEnXbGB3z~f z^vHucat_<~j15B!ls6MpZF6%3gxa$$Qr{{x$QfEMJY{tvR+7qk9V~M6L@2B!NqV@i z`$!;QjG?4S0X^D7OP=60h~EhLlJC6eo5@K%`N8v?KqM8nmJST0etADcP&Vq>lc!Ti5wIwkGdE_ zo^bVYcO}%SC~v@x7soqYM|k0ttEt|1dJk8}J2d&sHt9Akzd^5<$^5(dpkTfgln;^^ z)nEV9IPFHGW$8BKmp+6PUyXe9P7LgR&`*jUuyEa6bkZ;6s{8HFZv~zrtep5xs)lyG ze?=|{I!rg+$}`;J94!gPXs2oy!oK-vShIz`2GhGSOsDxx1gD>e*eh2MTt@LH{IK zarmO92(jZ{!G$+-aCWSWwzh7I)z`rxnh0V{96H76KEIsXMSVrx3__im5$~9CIYrZK zn>P^HsESxB-lDk22&ewcJ6ZE+tfQBdn!|>gBAYq+yH;B+XNaM{Y(4XTqk)9MuDIhl zf#&0$(+7Vuaqc40-=_;gjS)1*WM@$$dfd2~6$UUlJ^TUxkU*BKhI{3n6Cg7eJanjU z{u{0Wxs0jlwH$?JB~^ocXsH%4IK)(k`q89M?=kE!!^Ga`>wM1@X-vMW#mUcZQmabi zXY-!{G&N)ZGYXoZ$9=m!fJ{8*Vn=ZMY=7gx!q8j7;+I?TO@EA_y|&{8`;wR?!E`*; zFtK{q`YrwT@ooW5%kk%hv>=WmJc;;(T>F9W4U$(@=N3!i7R>I1BH?+L5fMBxOkH>;WD0?nrIOwfn*P4A; zXEO_YY05?#$b&L}-7Xv%I_5mGnyT|uqTeI+WC36MY%1t}mSv#jIUx17Bw(n0s|p!} z<46bYc=M{!*ZFYQVP3DAIC=ZZg2sn->@VXgDUE;EJ*RE&9`8Ng_>H2}V6=W?Us^7A znLxHbvhR?*&GCB41QH+nreb-DZoJ~@N8*kIpUirCB#rwLN$>IH++6M2U7#CM6=M@RAL^Vv#y1+N*7 zisQeI?E6`Don^awcz8f=uPqM6w}#XDaK<2`l!kk2RfsQOY)g?_Qde2x$wHWmO}865ZSga!<$73(XU!t21E;QIP2dIxRe;Z8#z<4;OYj0oQR-Sv8r` zbtpQjmd?VGU_!XnLM2r+M&BR#sQ7KKJ>?+^e1xp4Ah-6oYa9Dxr`77`elX6VEZ=ns ze3RL`B^GnrD#cu^yZ(iHWxOSx6L>68<%9avq@&t+WwkGGC6il zEwt2@)(9`(GkYI{#pJZwZm*c}-wMdE-mM>>0GQ_iDE@vjxqBj%oFC`q8Izek!nZ>_O&eOU~uH^$5FZ@n=~3 zydPo^rf38;i+0uRv=)U*WpwWgyiI$D<2+xF+FFmBz7%jFoexxwKBRH=yEJ)Z&P{ok zjS#Ecby<3prRotS5IK2b@J_ikIr!3Eb-n%i_ioMQmvf09_?W(gmP-pR;%6Yg(Ociy z-z1bHD?Bi0 z^qL&kVr4#(K{_O(1`d0&5Zhhm1@Ek<+pvhf|1umIoOVoZMAtwW@cH0Zpmon&riz?+-D(3yt!y^F6 z-s!c*X-Ceac?p;h6W(E$dmy6PR@~6NhYcaS40ShmSV97%j0AmAollOpf==6N{1rn4 z!VzBzF;VYb5L-r#%U9qH&PbC_sxIUP28^I*9}k2Kuv*-lf0)nAru=%en0U7EouL|v z^Eudm4c^~a>jht9P|WU_`To>dwP!w-ds&Y>7>1LL=yX`Fv%UWZ0sk7c+;hEaoEDu_^0h`&rh=wgl8LpQh*sfnRck7)&5lE9pv*xVQ{r( zY1swDg=V!-GNO9X&1r7^hEuzag3+jHHcO3{>|stL4hllS<6&oE7`3MKd2Z24v8huJ2i=fBcBcG3@RY z;PN=KrlLPO1zXdfI6?a;1-B(&ZVq%*i-eT7(~g|3SOJ)bUJ(d`a541Bc~jpQ8JX24 z-wh1S#rJPZb%QRJJ0<&$@U)*_^bXA6VzAyHUVBl^+2}QRmC380B2o3aMHwu>D|AC@6E{`Hm|(pwN4Rs>!eIcug-?5uPL@#ihp7Jpi>DRvo*1Ut*8l1=4( z9X=s+=}FfsIvqfos;At%nutM&q52s0H+e{YmINaP96fULUcx$I!-&Jwv z;uh$LG$%OQ8d;k5+(-y@V- z$zDx4rBMNYYbN|d6*wz|--$6f&ZQ2MJFc(2)W5B>kU@mu-<|z5sF)05U%5?gttUr6 z9l*~3mg06Rfz*5nG}5V4+IB#fkgJKCZ!z~9so4!;L@h=pSuL|Gfp-nQH=yykKDuQ81NQfp06+?I zO-nC8Dq|}Nf(7hy9OowPb5J^-N{Zms@76m)4i-JM_uKVK4v2jO?~PRPjOpnQyC6X7 zq+hjQX$BZlKk&z7X(;+n6Y=X6EYF@q)xxUd1KwHWrm&>t=%EsvOJaT8dP#~JlMwP8V=vKk@b zm@Al!4ybOxn1OPt!y`Vq3-j^(YQ7hed1(TZMw_{*ke_z-E307`NOxVJ`V3%yTJCl7{d;tGascH-3KO-g@OXO!CKo_(}zl#W$9 zGhXt3IwlBOvlrp|%Wg5$BNvfrjRdLs8%D!$oO&L;4eYFOV>H$$ePkkaWuNsF-DZaF zP1A|$rx(05WefHQe^aP>M~m}m+0R>rzx(i19f$!R64B&?Q>%{M)A{6j*6fG9$6x3@ zNqf@6q|gJxC(%Q5Xtvs!(p&K>qaF`c51Q!FjIHAOq6aV8kSx6LMfYpj-6dU4c`-uR z7Eugosu1^km0NioX;K zdQ!;|s7;0WNy)Wa=1?@{Op3Hmw7m4|FO;B`g!vum-$k1^U3I-gGhA!#y08IcBqZ&9rb07Cn-$X zrh9|jh;dS>P&wmL*&@KmXvctes%QuHS7&@AFs#}KA9Mm@+E3Y6bXz$c{tHtVG_ZNm z=k3^q84G1Ve3AdyoPXf}M9}eFU6)Yjuu`i7Gxb zcbwjT}=6 z&@4v^`*~~>>yDfVqVfq0LBZNE+*hIpWMUD=wg~a+i~<_DEv7vbq#IY>V*8spQ{zMT z#dPEs49I=PEYOx*-}-PuZPUFx_*q8cI-GeS88_GOYyE;Fr|Rywb@gdE#4!iKKPw^H zi%Y6L++pRok-#Ul7H0%!UmB7RmpV;_q6S(fsCD@QXw-3WobBB;0xIhe&9r7`-j>Ht zB*)^`8en7N+qoNiUAqO$BMs?<$b|%Hg~!b`St8;BJB&sKB#TwkVh-3RxwS&BstsRr zyRwJh;lf?JR^ujt+yYLf7xqqgW(r==GNhk6gXbJLsmZx55RvP{||5q@EGLo-b_67lXi!PpP38_d zQabuK!Ml-PosWwJdi?TsrN5>*?+fXK%edGYrd){R-f7Ve9p!!TdMreDAG-n>ahz31XFg(|q;1$JLcTtkO5w1_maB^;amazL+MO z{Y1|Bs4ra^&%{5_m&$QSy!qR8Tp)ZzcVN)(dyKQKy}Mw!8Jc7^QRm%?u|Qj?yy%u8 z$1n-9Zc~v`7IyQ6b%ojAq}(EX2qE?%Ab&K;?Axr@r#rVW#DNC^HHrc(RKDXKNUPUm z8`S&GjJj@MMKK*WTg}#gn%?3B-mkf?Ft}oO z-AXaeZskbGBHdu&oJ(xCXMu1o{%$+f5j^uv!6?mA{vtKczxz|tfyu9Hj@ftAU}i4g zTHO|KnkIJZY4&-t2G>w#I*)x3-B0DxM3>h|;<^bR|I+r27!Fx`UVFaMPF*o(KXqFB zE3L?XA&Vu&yKI@s+y;%{$p*q%$(iE)`Sz?{|K71Y>%9X-FJCs88BfZv{_8G@kTBl^ zB|Dt0@a_1+_o)*3svQxnxWU|%3XbYG26Ywa?^|R#zb4_!XwY!ZXxd%?FQiKNrdBNp zb+Erx2U`AIoUe%9b^lK~Bcj+AB4@3An(ygDFD+Z3C;RMUdGp5h52fGVj#=BX3xKga z%#!ksiQCO&c8N#x2F=eD;=3Y7losq|h?Z6HjfkJ8(7sx&(0?E7ZJgk`L)ns0cKrYt zE2}$w$-PnRnZMj(73nw%FJjdcAi&BfXOy!G76|F>2N5DgDWELN00p6 ztTZF{>F7U6i-NK_bQBP&@NAn-_jGBd?j$w+jt-O2cf8WBzkE%raVH>ry#BD>e2Z(X z{U~LXZlTp|O{+aB-mx`i4Y&c&%K-s%I&;s|d=lm_t7CFd_q7c?9~gJ}5s(hrEhupy z{PDR=)b>7d>m?94_S%-2px&wn-E)swH+%7Mu=$(L%#k_hvo$Nh{zS|E;7<|tH2!+) zA>1f)=e^4KagWOO&Fc@Z@Gq^ZAHHS_H@c?Jk*e$be;~Em!zcCUleE1o#GkwM0^{6rW&=b#JPqZ&ZWxc#L zau&5FC?`NYx<2hu{s(vzyvStbrcfWPtrV(;{3hUY#ZFzRjnIV6gv2@cWdA2Fo>=gB zMNYVE-uaKST!$%pf>~sgY^cuon1Cy zC#F~RS?(-EzP8y2R092D8}Qjnfc9kb#gLdxEqCdNtkF)LsSeCtdi>(UvQQnn&YF6- zEsUj%Kzo{6lsQMZlHQj<(^@%0=tZ}^qIEnL3fuR&)(_FTAmATAMnKP=@(6g1?@2cw zkG;0*$Z`~SlVO0Ha1Isj@)cm#VejTY7@J3Ao=z;z1(`C$OCU%m#{#~D0-RRsP&D0XQ5NnXLT+%DyQme&;YGS*B*v7Q1 z4lPoLJykltV8-X0E$X7YS7ll;T~>wK4$D)};mnJCyD5vF5)nURoz{Q!Q1JZpo%o?l z02j2%2hRNyD{C5fd>u~zm9ov;M7skFGZyc2DL&s`$0a+?-9^KgN|Cdo=v^vK%bt?i z4_OK<3wT|7uiruV{QnA6-`3e#3uI8F$^A0kq5S%;H zCqTfMSR))C_h;u?SzXV$>{tG)X19u|tBfbBWAOr6ym!$Sg9sex{FR+ZPJx``?bvbuh!6LZV9+{id7S;}&ix6<% z@g6W1>1exOL28=e0;&|6X#eu8=?ZATdrTjLbY~iHQCC>0qxZ6#OV0AzKk!puf1}jH z-P?Me60c*UJ_mDBIosK-gc>_e?uX!bSsn*W)xxe%s}#JfKRK!`{@A^osGi+5Kn3Ps z*&ec;_L65l)_QeN*?tApz2spY3z`g4=avYUVAJ^FrLPfyDx`CMApxU!aT7{@=$$e! zpV@pxDmmd#usvQx&@$wGhLpQD^|yA+?Ctm%EOL4HeuJtW7abPhm)y1GT45yx2=T7v zuzULrVxwx!=g)`atFE`(D?IQgl($`$bt@I@)h+&zTv?WARw#Hw=|3@^Q}KRvK^=~e zrqcBxoDh-Zqm}W7r|c*{H}CbbbZL|j3ljwoK4(-we3*5 z7tWl@iwa2#3$YOAvHr`G<##2%-EeVVC#j5YC3`+s2Ta%7&8*I|o_tq81t;k7BNgX2 z^?k6^rBLHnpMH_Y(3nNcIK3-RQ7W->)om2dR0>7Hh$lZIxB|oEP;+GqZ*nzjQCSz; z&daS#Y3J)s=3Rk&2+5Y%wpc1vRr620b$i+WUzO)~RSLsMMFf6*_tjtI&UG zKVj28`;iM;Q#+JE(y$|c16EPen(5#gO*S^{Qg3uv%7b~L1I3A)e=qD z-^N`6v8BE*n&aCdw1- z@yC!zU;_MX)*O+Q)>|NGakRqf4D#NtH;$5;sM-k5@)Kl8b^67k&tuowugUE!4eKwI+OoRe zqFOTb$99!_Z8@&>m~Y4UH~ZwIEEQAbC{AX)ibf4V8L_Z|dNO$nKtP3TFv&&hjXS7i z)@3soklyUbW!xz=tN%?sR~g|1t!1q)zB+97E-Mpi$>87d$2sbnjiIjg|LSR330V8a zt^3e~k$=xeG%#?Tr|M|3V2Q!=uV$g+VDGw$o4m;R5KhNAUmhwmS|@OKZbz3{-tgCb z-nTt{he&A4Z{nAWAvIp=Wd@V23*KaO>J@ygw-=N`w0*+e4mHZ0ya>o5khp+=&?XFB zF)-z;FVgg10QXnZ+{`7B^5U&aobayE9!cE9Et(fU{cC@+F0)@RhB#7AxhFnX55=wS zQ8Cp>2BwIi4{B`Dp&q8^;A~ZM7k=D^7bjPI?l()Ov&WsO1UrH}*E9GGZFW@@ zw%(s@ayK+EBPpI?vg?Mtw1#vtLhA~vR!K<5Z-!E>#jO}kUWg(Ym(;6DHq1C*3Z1i< z(Nvf5U`I!jzar=wV5Gsj5F_5Fgax^*W0+v}RYU`VN@|oI{F$*?2IXPjdH?tn1PhK!<#`1aW!X!qx;D=%NTB>K)` zAhpzLdwUTKy2p>L>I?d=lqqPTeDu2zS65f}{UkO4O-sK;C*or9eIS~{(dU$UXKzBn zK>_B*ppgs_qevp*fg>Bqpg2yk^nHzafjm8|r4D`~k@w1r*XoQ-e#6Y^B_9eU*7YA( zN0LsuZL#ua-jWg#!)G1tKA;PwmZ+TZ;@ssq2U-31gDZq>UbSWuat30NuD+Yp3D~#T zXgvH-?qtL^9sjuYxwbZT_eoIabC7t+kNuIOE0s<%fMTR|O*9V~OfE7QmB@at{BaF> zOXNqA-<2Qwixfry$1LSaC+pb5X(7qI9y@wW{MPkCx6SjJ2+tj#p*q)#+{y0}ICPUa zn4bH#K@BNXdHl%ABhy|ZEnwnAXuK`Qqu z$yVxOtM!V{LTq4)B`_dXn^;H#KAS>n)R^au_tKHbLF!J5Y81&hmHPoXw~8a^wmWoG zj9*yek~zpNO5qK?f}$HQGltM=ps*_XDc(T$kLVRUvh5JH-F;4(;{lC59)Et{|8~j8 zKK%ykH+v;rz+WPYi`3xu%6M3eJ<{P^eS&H_d0l$4{T|5!dcs3Q1BetRfY*^HN+KzL zU{TBT=p7ZWoO(B)%!S>xxmosPBSeX4hx)9u4sKC-KMjK@v}=Fu5q3JkX_orx(mYL`rA8B-7g+fsI@0*VXK*o-q ztLea=^>w`t=PFG1S#DPUrNCd3`}U7BtX4_LC)`G5Ge)lyBQT%^t9`f-(3|8aL-fFr z=$>ap5*{@(>rXWXLP=QP485-=9$4(9kKGZ7bxk-t zXntmFA3J{^oKuMffI|1vOdt<1Oo2m!A3x6F+Lhn`Ba?rwUx(1G>}8BUX|4HEq|y4( zU?+Kt7f&}JSr1gT<~T@QzQBjQIZ0uSXFGa>HMF#b?MLQ*1%PSpP@$2#YAumvhh}=^n}aDOn0#vJrl}9 zCOJ@fZ|=m0j60y?@lBmw*})XjZ zazU>Fs`X8Q+Xm5ae@}Y{Qtgr&$CCGzC1IdyeIf zZ?aBmEmMCzZHK_C45W^sM+%(G%oqcC3UkdnY@3X}&*_oJ^h6`{j-2o)qG5U*T$vZb zpZAlT`eJ8F=Sp;Ot3u6i`?-|#`15TtQ%Lo-tf|!;50$1OS;}7czO*@J=SZ4kJ9c8e zhy|vv$oFj@zvG%Cm#$e{U7#SFqnQ8tFZ(5*!-CGX*(|m2q^GAZE^|ppNR%$0ZVr{# zq1k<6Iqg|CxysD!T0Ixa>;%F{RbI9725m8A^jiOj-$IiEHPG<15!CczzDPM+T65+P zJBTP@!F=Ma($4wso9t!$KR5n!mG(S-jMUyb=Q3>jL#XC=Snd9zZ!ojy1k677R905L z^B5Szeh1yvC+@SCh`e%m!YII8Hl)`bt340b)2YCy=zn^aU&KOpBYKKM&5ZrCYkVf@tjjdI>TUetRonZ~31^4L5^g^uGV_H);F_B;Ni`U3->Pe_? zUh=fo{hYVt#-qicj*iD|X_1~=@G-TFfgZes!WoV7D5IH!w3p}MskszjXH6@#qmkCp z(UHB3g)Vrt9hQ{41mq5K{1A@sSTEZfi_`i?_*gaJ_)(3BMGCurS;Fr;CI3VIriyqd z^bS2{{w;L>r$GJxNgi4d|379{3|$RL{!>XKOzA=3GZBV87RDa3nt)AX;8SPD0=tgq z<&SV85F+-%0efB=Zr2Sjl{MWmD?E1X`zo~Xof_n8=1+w+gKhG!^HA=>@Qki)PeS|#=O@R_+=Qrh>~`$=!^XD#5NC` z{-Ac|TWw0gIqaiU?eSS90swgXeT?0!_4lOy(6jlg3o1-zQLcXg%m4jV;Op*8U1sA0 zO|#$+-8s$=gbg@nhSv0Gh(lBzIxJo}4cJ89bQ3tf_(dJ!hIkafyqfq-Q%3cR@RAty zUO}Xl6|w2uaa*wOQ~!n*G6U-T7nK-8D(#^`f`(0!X3~!r8lTjw?*DFi>zdJI(+Y3W z*QUoynZ`bS#;%>C7*eos!$ z*OLPWti#8;ktkC3adKd!Je)UgaoW3M z{v!;14o~LtJON=Vnj>}-XC)Echn^hcKIj;uqa2;<@Ql^`J6bWLvGx9V?fFxWx9x`% z`@g{RhsWY&XM{vVkMsmo)PCD|vRt(N!h139`!?pk%!pVM z@S^i#*+>BDBmG@8N6vE_+ssQC{qhGxPmjERVEv5lDSo)FgQ|ld(M@BM zY^))%tZSqc*gIiTHnZVZJGU+NFCsA_k?S|8A@46e7Q-c>Bw^1LiqP?Fp+E@)P6g@O~aN8b|MN(Uw86 zW>P)(Aq+i(@qfPxZiJ1jr%q6KZ2dkM8WqNGXC9d9L9tArJ?gM#-TcnS~)VaU86!{jzf`fQGvmF|rty&_~YW%*|jCkc8Dh22e=kf~lY`v|4?vfN`Fv%)@1LzX+|;Jwmpe;RC~vgdxkN=fD?ZmCod0$Rd~Z(=dS)}kak9(u z@Mhi1{cG$=J1pMQJ2d9cUO(@tvRWyKR7^W&R!`kH*kAdT(xR*A1NF}FJ#5{`-8MG+ zxz0PfYsZv1wEohV*Yu}sS2j?(8tc!$WG;p^n}y+s9i}{}$ z|GurHZ;? znIVruU?&G+5LZvYT-Voh6rZHPwMjJKvEc#12hUb=zn4|4^e^?b9syq4Z|_#Y3Xy6pLRp5;k{wv&&7_ zAq>U01DD|Ov%0|kSp_0dW6xKC3wrljuB?o%!Aj!d#dCJaC)CR~5+5K9Z2SNAcK)rs z|9O|kCxHief1L1QHhDwp9UCd<+BxRr`yLxi(cQC}_z;dwq@VO~8QXhORlsDO{=_4R z?VM$1Ej*UkBK&Z2;92X?fq zLAB$~6a2$Cg!StM)Gq4Os+N1RET0-JmTgkFyA}N+cVf6-wXDohg3ER6JDxQ3!=HAa z)IR<(BMmubd!{ec<*Hcn&FPg^Pr$=61okp7Xi?k9WRdyf&0kXa;0C|hSTN!Cu>iqs z!K?+$I9sh-r58EO%w(0Q@Yo@~Ev<)~c7#ru1=1xNlt7$v3@g`uRr1ys1o0Hc_vmJs zqEg0*YrlIJcZO;h$_3mVXOrFw`&mKhC*Z=E3FC)49nNe+97JO0>a9HWQgy3@-rUf| zHmM=V&CVn@ld$@cFtrGaSZEUE+w%j%A+_oMDXyeuUrfc?iT`y|P5R@pO#aCS;FAY# zvGi5&`(=W3H(2CopF0pK`%BOuVV1DuW^Iw-idtg>e+J;dQMz6O+>*6e^tzfQL{L5a z*^MnT-1gk8ca;Kslo?q)W`@}G@po3N5qG|01Ff~#tBMHeyz8tGDFAxX52+w<`rR|U z7R{T}Zm@*HbVaH8PDmN+fe-8=g^3u}x8sz))+jGDq3PBdtQSqpPa%%f^lZe{<}?x7 zA{W6wPsXc(cP8esF3yoJk?iOd)G<%w;L*V;gPUDEJa=JB*H;>!DrKMmy48HosvptD zh37F}Fy~NrT?W@kHcQktflkq_?S=VM{?M{7sy5WO~ zDl3dbfSA;pk^_ zDzI-L{6NMB`tZ6OO*2hBI$q*);`LW@Kw9Dw&D*fKC}J}F4y_M2_;7?BHn)CxJ*#e9 z_l_KlhI&mU-DlS3M_-l#=GXX7Az_YFI}9_`HXzXSP@0&9cy2)b=U5*b2F6C|NPun^$l4~Ge!DU$VJ)Qf=jw_Z z8Wqo~;#8k&aKp|8iUtt@ENe?UU@R{Wgg2HjmKL`O7gydDyoqmQaoclw5l-vz@Yd7* zO<8-;SdLfBSe@+zZo&a&^EbhB@m-QQsr4s5hqKAb2N{Wa4LQTD>Q{Fo+g>O6-Zz07 zXd7i4cOX3W(z}w%&L#THy;4usw(!Lj+(W6a`i-57qN>~synG4-!%Q;35O!(c&wEm- zZ7_4SHg!xSK(mU^<<45Rye{Wn38a$|UZQ#sN<1CxpsLgyB3o%XTTWupvwk&c$lYvL zVXP!nVs4LMaCOe@r@{g2{D=##w|uz^2ut)HlzQPf#bRSI(I5+d2?M=~E`r7cCj1H- z5JvkUpC8?y0MVC!H>;Ck5u^zJ{=sFy>WA#k{0#y(Xj1x0^q~Q3ctvMZmGQ~!qXm<7 z&7i;K5Orq5^l(OF$GRs6KaInYoODPmhJ`P#M_pl7l9YoDcl6%7K)#l}oM2KDlKH2e zl)3)mNoI_0!fR?(ikbcGeA}ms#ksFM9iEAG`q>~q*GxB3ikiwCGt zGls$j^mOHuayoZCx3IFr*5heBmsu;=ymt#29b}tsT>#d;NNPpzE&GLO*QdF3T*&mL z+1wHdjMW1gp<)C>SbRWCz8VIHqbWwF5|xB6eeY-7sBBDLA8HJhQlj;)sq?KoigpU8GUutSfP(1!a5da%XDDlFmfk? z85@KV4yk)ETlb16Ee(UiosS^&(6 zN8CObCeYP1`3}||2ktrQ!>{z%f<_~dE63y8M0BeWO+Vt3t*a&w`ztYI+Gjg}*P0nr zn~xwiA{M0%l6iw(X+aa4*$r;<>3YnMr;|)>;!r_H;VR96qqoY=^;c#~+$6dY9-^Uq zK1C@R%yqN(M(0qHMM~`J&0|tlD~34rPVQI~%kW|3DydPxwmQp*&g-oOKSczY+m6RW zaMmXRa=bmcZEOpt*mg%2C#f?$)a|*LC8v=Rm%B|XxQoW;PQ<{cf1YOP$3{37V3^*Y zP{qIT3$~o$ukUkqOBXx0!z)u?{gu1o!jGhKB~oM7s}|{?!MU?ve|A4gSs1dl{WZ~@ltiS^k5jK?y$GEVUO;uARAoxMGl`P4ss((pndk?lG?~*?tSIFIFx6U&Y7Lwifp0;Oxkfbk(A{P$Hlw-Ax7TW z&UHTUQ#SMGyzwa*$?7OWoe(8HgJ(0c`1?iRGpQIFbCl#4jIWBOC+U!;YL-9?oxBycjoDOnwztJ{SxwN7&S7P8jl8Pzmzo+&SX@a zD}5aC6bs_2G^6D!N#H+$EJheYTo1RflU<>n%ml?%?kF!__ZIS;pFGE3 zEZ3Zj#ZXqa{S&2YaSSwe+t}h4YGt)(W$j7X(CHBpj5}ua(P>>4+3bZe1Tcb;jv4lT zS90BfA3S`=9qBz}z!P>mI+h3D@N5z8jpPPQf1BvIx)a~0%e2Y7<)-uZVQD>4Hcx7F zW-*SV><2TgY+p-xvJ`%h8vzI@Zw^F{0d|Uq=4j|XCl6gCW(WLE7oxKy_Z@QD&5eJ$ zEX*ZF-k}kSuJPXBq*F}bZu3)Ob&)!lyMg+Jl+cmau1FrgUo81>l%h+O9{0V{?a7E7GBw0;JIl5^j1xk?1c>@8B9Yfr2C{pDQ zNc=>0YIu*79Ol0{9xztuH)JqVv)AXCJ}{n0Hy4YuaY<0l`m`4yiwm^4T6S$gh7Rot zedmVD0aY9=+Fqam+g4q?RHe&hi+AQrTRK?)XvSlBlEjq zAcq79;~I;{%HR-uheG4)R8jF!5gM;Ky$`63RWuFw#^Lc%^Aqu3G6Hjmw~fnlhz#Op z8f}S6LurDJtviCM=!3AEij{oeh$u5A9>Rfz%Ubn*^8Xfoh4jr%Y*BqfU=O_iz|nq z61V4Cvc07Mn_~#|drFsQ2@`}*3?<_uT%4U>3Cq&p*pD+g#Z)TU8+X`p&m7sk2(c&T zfyttRPTZc}GOt((N#<-C18WmN05i4I_sB2AbM-&EexNy4(P6rqxxTR zq@ie;#+H*JI4vhoVQ12l>=XhH&(6C1qof+*O@#dW_31ge&+Mm0e3HVE5}EJhAlqd{q|N@G-)r69Rybe<$Oh8}CdpwQg3{MuMm2YGY`{ zGH|dPxM&S3`))9zETwvkxdM~DuT`su=v%e}iPL#}$tEQOBlT76M~>iS20jR8F~H`q(lFkPed?!&5I=HA0*Sw8&e zlA9Y=MuF^SP;OQ}?;D201AW&nuirL-yv4NN-kgl(o}9GjzA~ldmomL4x2J;+UkQ8| z@uTBZKXl?SI1HLh6s$a-wrA9|lcU9@;YFVECKU(vclxWByGV%H`g-I6N+Ny1{SA7``3xslezvJxc^~ zw7)C!hH428wT0s9Yz9phP%522RhBKF+IOt>_v{l0UbfLUx%9=`XWJIp(QAyD5}oi` zn0gfc;Y&eOw=}a6y07ijOzu#%IrRhk;Cps0Y0gjBE`Ih90Y$6e+qEZz)zo*x6~>#h z#nxo9~C_a zxAvtjnVAIMl+SQR+~bgf8!9IuHi*v39sgTRly!=G~dwWVp$8 zajpDy3@gJ!4d3R&A1^_9|+|DvBcZUa@1RR$|Yh#NNdCrSI?O`*}P*zsKi$ z|B`!?o4EJfbI$8|&Urpv$aA+A|4_`G4f{Gi4X(~+Mf6n*hckQ{nM%CINqkan z9NX>}MtQI8#+$lrFK(_|tl}nPH&R!diA`RgCM+)i+a1*6R@Ilj!enB(>%rT;GX8%^ z3jP>paB>~)r>2~Plx|0)C0_o4U`O{S@)}oXUjmy*dSr#S^MMZmUf9mf_-LMs{SB+* z7Z+c`uSd=eAXIASA-@u3Y$tSXSK0?}hD)fjyp3>pnF&zv27RG0M=K4QH*QxuI%h9Q!QK%;eO` zI<-y0O^wGko9(lT5Us#f{4XBR6_<;Gjc6SV@ha|z+U>a5E0JE8Y{vuAR#@%yr=Q|oYZarG&m|TIxWe)5JKT3)H}AehcuMp5 zlhaX8Uyu)<&1N5m+a4juQ}uEc8t3DC?V_WS&?0d3 z>b$)f#4R>^SIxYRqHg3txn)M*1yP_4RQIu%l>R@MOj{fvfa^hP|E6EhA8KtU<DtknPPjr?wj{3X>YD5_eNlyQHn`skP+{N3mXc4>KUr0 zz$1y|^V8M|XVXtzX*E+;7N70IUrj^XAXm)j>mwPqfUQNTi$2XV>^QZ}govRR!FYD# zH+)h5p{-Azz+E)EkX2sD--Tnzy5QT713ylL5Y-m6jyGQZufUn+qd3|UwU4rFP@%9F z7BTjn`3^%CjS17hy_G-F35zp$o|7hXK4%Ij^xlZPz+&$&Y~gsRvdXE{)tgXRFIH^t z`q3C)oRBTHjq8m<{+1&`hyrgsh=zzoj@66MA{we(X@>09fLK;1jwlzh>TZ$6;Bt9S z&@5Jp^xMq$=n=n41RLK}$sm|z=C=F_Gi;Ty&}Z929CtLp5>WJB;Umc{zy&Kr z`wmo1MSQmPw)}xC@!8+k@&WZf!?$UvUrN~C@35V$;w8l!Gp<6*Y`zkF?I^BNZGGQC z89{k6=veIooe9_dQ^}dcUhiA8IhJ{Sis|SGP~SLITG+^I_N6wv7WbN$PWJG1H~aVF z(%)xooTH1+W)LrFb@x>k}AM<2}pk4jM;O$?60vok2Nuw z_1jHr{Cv_eKdz_lNGt*-Ou`rQO)C3rIALhcU8CQ7V`NzBh^(HRY%kO!2$D zd5Q06Hxk|W$M_5FQQ@#n=8jy9%^20o0@tXEbot%h|QWKW_DPSPij)%z&iOggY~ z{P4?D7^P$eD&h{{6O)_aUhGq)7_PH8w`h~UV*zL0xf7bTiZOx>AB*jE=J5)MM5^iebgHn7=jLF$*hkI`}hF>qsawK$9HMNCO0>w>py>at0HUh(!y2axC!JwG-cb#I~ z!sn7JZg%?ArqgFllzzJ~Az4-IePIMOPYr&*2*C*+E^;=nf$u;eT z)W$R;f%*1pd$!(I=@L7~`uIIrrhZa}2g6i_USZEEGe3ARhSe*-bl#F^yZJy1LW-rO zOTIFujwkIlL+&lctqdxUr`7YOF!50>70I%yhtW81%m>VV@{EHY_WFyW9))GINyO5i zTL$^+7kjaZw>#48CMlD$@NT*=bA%2sd9x`Ye49nmUzI?ond+MISFD*xv<7&;_?n;T z;)N^@4!c3HAQwbq?OJ3eUgLTQg5F5Q-FZ4|HsYrva0Y35SkZv7J6LW%YFt@Z9vWW6 zAzW7xtn%nTJ5eUk9f{C4LF@Li$iLNOQ)@w7;#HGBqjjmRs9$)5Zi!S08KTNf;yh-4 z-?j=#fo(kOq7RsM ziTY2mfN%c-Vs|0z+1Ed4aJ>sSI9otw{KNP!tipr;bqbes4>aa0p= zyyJ9VGe+-p*c<63^_2Op^>|R-^879e@11^3<}qa13)LW0;kd)JMbj%iEcg*H4^Jf+r6K+D1udo~y8&KAgW#^;GF# zWysbG$YTf8OY36(4~87BTJ<35il$;%92(ek+_#^B}{l7(ciz2sZT-5uLpHph+HQzOlZ#V zIYI${>Au$VMmS{&#Z3Dw7;dzQegh%AuZhdKIw3lc{SvY%sbqfR_mRdpGWD??S+5&Y z`o`C}FZfIxmjm@+gfM0aL3_}X{@h+?wIZ$Vi&P0Uho%s0ah-HxhlZ-nTxFcFut=Dw z`E`1rG&X@Af8^nyQZ`>tk5#>Sz~2V~x!<-Gvb&g%mL_~kSx=}fV3KL8)lp)W)bWSU z_e9wwtHcRXO4V-j-i@z%pRbBGel8dG*^f22ICo*M1hk+v>k)Kw{)0b`9a>_4WkcG} zFQC8X+qhb(#G(S@%Iq(u(fgOt8DrUT;orpz>~#3y)dV|TDR`mjSQLjG{ru&b-Tvt4 zD8fu6yQ5xXt-cd{Py0u#!?yrKS;}&J<^}c+QRbFe?P{6T>P?@|E`GcS&xV)-SAhU;LsrR&P9e%+$=bZ+i&)(OKNqW)X}k?F zIv~lJcSd@3>>yh-f3@?ki)i0dxjA1WU0m<@HI_xW9_aF?UkUYT{UYwAbBuX=L^!RU zkKc|76PkQr-1NPd%vwoyZq~+Kba9H2ATAfv=i{K$9wXr%TnVs#bN`-tNfWbv7sZty~jYcj^SEth2xgrF|VsskQoNh`sr zZcjQzmun$Hy)f3*r5W1p;salkX0U7}D<0=_{p~nb$o4@}R9IGUr7;bPNF55PN!I#l z1$C3H+>3^@i(Ywjm#`7T4RCQ&A)hhTxVFd&&lCkSi&A;=k;RqHMWcoG?4Lbr5@$2uod zK0b1yCMj2bc!_4gA59p){L-H<;f}WLYC198qV0MCvmH;LbgcVg*7e6L+xF12W?{XUk`SI=nQ*0qr6O_*q; z2|MZ!qD?K{o-QD&hFpul0w(oYe>tyL+O55lVQP(EjThvXxR@?_D}UoQ zuadDp+VkpSJX<_}K*_(RzZvNO<`-!36IIeTX(tG1-j5SVzHrfmy}`m;2l@(cMs7o4 zw!8SEFMUCDYj5+d`^u0c*Ui5RKixD-u+&qrTFW+*k$3I#c0zZ_+*E@zWVD!CN8iefxYc7`IM>N-4Y-hei@u*}o zoAK(x#PstSvy_-E`^{;`z)RO!Wg7-PV?@yQNXGBmD!$`!**x|zD=+$8ii)42*=DPZ zq{%v+Xxk-iB8(r_m6Spy!_Icw0?&f7OKO&f>=pM{rl}5hdwsV3Ml_R? zFM8;yU#t$yf)>Xb>@>61@2u?$Re&=7**90uLe;N->yFWTEn|4r&!*gw~}Td&A&y zxXL&c0J}Wp{k)@_^343(6p0cI(T5m$<0(L?V20M#)QS_XpD+dvJ3;eSe=3*FF7o~K zD%rK{A}f~M0nP$x#gC2|e%6-SLB)yVCd6%#yrV@AV`%nOvIbWOqud-!UfWL5MltZ7 zE|_M0P^j+h(UJrtB(0?=*FyWJGu*&U6r5>KmtC?_n%68#hUZnwEIJzUWx~k0Kg zbtYR(Z)08(A#N2Ka)qB(SG5E@n|0p>dbw+_IuRDJe%u|+Sc!0DsD;Su|IRW6xEy3E zG&%}bXQX$o+GilXO-p(vjW~QJ(x7OLy{89twj`k-GT;^gUWS?2Y~*6i2dH&xi8SpSwPVkg21vP;mxM)Z(H{)kHg;MMd^O_-2BWh?JYFA!Spcw`lo;k zc~K7+x}~SxB{wg8z9n$+{a@BSLiX`5+{Etwiz+Z&(HJfAk;$o8lhzRd&K>~RgtuP5rC96mE`5IAYY2D<)y0Q zS^I`-lUwIPlIBTw9IeW<_H8iisJ3!;RB@oV>e`T}*>l=s_EjRftSwVV!#jdTV;9*k z+R`;nHgNedD*U_C+D@&DgQ@Uy4flh~7cOyuX2(**|JDbQTqOM9elz%oGOy!0@IJlu zq;*$LNd%!zo^LJZ721VPe@D%Qt;eD(y;H%%A(*sP?tY4;rPe#qd)-7G!z`-@mu0ZK7^D*t+@L>Mn;(kCY zMemYvlrq_a*$?gzKPYv9K8fXj@^`C`^?CBEce97xjHGOt2AwpR)+8rq+G{KzT!dmG zGox(|Zu)qhMYA>3dgPAk!@!X_+M21GYsnKPO(g!iN}GcR+7r(owL2PBdy_zUzZGqm zxxT>nJb943j+b<}xWR8S^pZi)XrkN#G-zK<*g`p#&K(2Q7QjDpij-jWb+@T6Wo7fy zqOH9hIKk+21*-kBn!#H&_&qTTax{j;k#x)R??|9S49lTu-A z*;JkSa{A%XbkaYQbo=Q+9-|_3R{zkkhFB9ASNF>8-K}Mf4QQrT{mp`7!SI}^B{Y;$ z)!xJ@e`sJ{^CL1(^2U${VZ~)UraXx90F~|Z zz%mH!$cQ)jcGHIVf3gF$F|r7v4wF5GnbLtoLMt*LZ^-NMS_H>PjZFa{qWa7Wi7mzMU2G4a2uni-uk2&(%Ry~V?HBHaYTPgo?^(Qg_Uo;}zz=RL zdtaLokynqZ9WP1jMY0;RC_ZH^Mh^+u7V-F?DGtp8ayOtc+%IvI3TqiS|2t7Ytg!PPBJU zPc6rTt1FlI0ZcAp1(pIGjE)nOs|rs0U45LZJ8`I$bK6i@twOUW9v1-YQc7fvZ^Ino zbv>fy40Qk((RKlCa}SHs?KgBF4F4(|Hbe`qm2BdpF9hQ#&TaBX#16gMp&LyJ^JdHWvW(?>at?7cUck z_|7-!3N4u0-L&nHX}{fBbQps^k+8Muv+abs9GSG;X%koVz2*Z?>swije{n7}Q@y>x zO-Eu9;Kw;```Z0#PPR^X0718XdH;r)pkG5bN~|N!%Mdbt_b|xNAE`&v$qQjSZ6S|p z z8xB1~S=F}@yT4C7e&U+cDzMbTmh{L)A`ihk`Rp0>i?<b>&V(91FDBl)ZG}&~~Of6Vg@4 zcdUq7Se-zt9vLQfmO|yD zK_A zHBcvttec>SjjN?26yJn~NU!y8iHfe))9rB=458t8$pTTwLQX@4kk*=IxhP^$iB^iT zc&S&ujgy?*BwE?>$}Kgzp4<1wl%dFC4tIqINy*NG@=zAk9EFRAY7G%RZk~A`*25@T z=fum)s!IuoweXn2j5p67T#CvSO+j4@PsIB4!j>^pd)(x2B^?5YJ63DH{--UMHvR`{ zG{p@ZW+k3zW&BwwEf`F3;Z!h=Dk&Jukbiy_F zsbBuH_vXi@Nw+JzM4y7&la|(rknY_K@Mc8iZ#y@Y1MIhwhO!M!Hkn^P4W!Uz)^our z2iZ7MUp0{?GgmgOJ^j7d!I`ktIH!&!gk9x+E#xpR7~^(yz*>~JmMJW0lvMORT&;a# z?JINnPi(jeqx8lzeyL|rrL3lqM9GP0LQOvA8^*4%^49k1y~#i8$laf4`eHGInL=i> z;+B!37}=w%OyqBDJegR|vVQS>hT2;N$(v98)KdPNh|=_Zyp)>~NtZd#dnc@4OzFwt zX@gm*@6BK2*J=y1t$rs%RHGa1-3~`_yxT?;@CUWFtDSD-e#i9AzW#TZVUH`Z4^6$) zON}d=ziEVNJVL+8-CRCia391`lfrz*n}=DWq3H;hCyIhc1+CU`_SEr_BR{5<G0j|-#RKJL^6m? z1KyJ=3(zTdInG*L;Ex;v!!eAm-YVpH_%8>SrM%-Lg+!)aY*$t~y@VkwE;O6!%NiX+?Xo z%D+{JEIyBQLdT!l$$8=5dSR|j{r{SMhMzoXzP?^KM$-y z0>bMXS02c~nyhD?^2tdSo_`FKyV&Kc+`!-1{`G=B3q7Tl@J3H4-OoGR;q+X?aSAljpyNOxhw8GW9?2_}vMRL_dj7 zM_@$f3#s^U&irxnDQGe1^2G&+Xw8A&Ty||oNK=2roui|6%Y)vv>ObIPem*cmkd{o& z)==PT%NP^lGX5aXnenxU>K%daTb6Ea!TSPohEpZMn3d3FV{2(2E1)Rp>>YJOThZbL zX4IAl2_$=Ivru<64v%>B|9p$5Pja@=<(8eRW5iJpm)`wl`LY5sTW9F)*` znUu&%6UB{)ddY+Tk780-A2&Jljk(KD|#^XML_%_P?`63 z#WVKr`5iN=Z3TIIaUBR_*Kv{$PJNz|LArOR74&`RE}nh;^^`2u-dv)PCws^JK6b}E zElEe|sOwnok5O1t*nF=%L%l7=2syy=d3gS6E!f@L;Z%V9!bBtV>zVE7Nm*rd3ugek z5o@_+pU$}0a&Ag0;M8pdb9zVAV=k`Mcrx$PE;s$id0Ms|zkMRejme_sMEsRx48A?( z`t0NC)Y}`6AAymDoVzI;NBnahv%nY<|0F(w!FqI z$t;-GGSydN-)GHR!rE%{&`&+5?fs=ViKFD_&09CCYQK3^JyAM#7$DGraP4ixJv_jQ z)VP@8MwxJK0%1Ejl%3XEDV=$l@qR;QR2ty*P`2&n5!%9CHk+^S{0X|i?F!qF*YA6J z+wf;f#?^jbPC#e&9CpT_Ep~`PDam0s1qr*Kz9l@2#oTzZo@- zSL-xw<`(It*;}5;YY6Dy@S&cL67Zy81aklg`w^S;wKzJJVccD3{zI8TT4V3cI zYX}?7a>+s^dm#hg+|qM?U}RfK6TEMTa|b zu3aeQDlChrqLG*Rmc<~$OGKVwO}38E$=v70j&gPcP{s4yFHR(JK8TMkiN%KA2Hx<{ zQNJK*z633*{&XA8ks2l(SOn(qW^O2qmFsP6;<`O_-zlS;o(BCcig;70e(w2MK$ZEf zU6*eYpvV=}(eQQB{u<9wGY}=RspsBm>C8PBCR8a{deGToeh&@$P#RNvba&L+CA%y; z^Mq&R66;YZ*3CohH|vLQRDS7dxHDx8?<}iVx_aOC^}4}oYI=6=grM`>-J=y-dT>V5 zN;5X2+rZ96{zR$z-YNoReZVb*lMRkxzvp??UVb7EKWK|si&HDra1l3!&=8~7LzX`Z zRI`*@{(GvmM;l8`UWFM|liu`=tMRN0f!=P1-sN5Verw9zjOA;=nwyn1t~iI@R3)SV z;WnIKlr^ibvm0*W!y2}}%{)67;!XO1Mc*Fi&Du8tm%3UG=Glj`ubv%oVZEStMP`qe z1t7Aa1!+dgI>BrNvP)eBqHa6$<-*{8Uhuh%zAKl}$?5VR%U0J1GT}($i zT3};GrEKG8#FGol1c+Z1B{sv2OJfcqlUd@30DDSiA!Hu*X5F^MF@(k0qY^wEJ?lMh zpg9-H8iG}m9akH5SRaQ8UizzJ5i)S(PPI1cjHhe@&4>ha!~_e?{UyIhEVG{Jc_w^5 z93P#1N<4@zwGOU*{S4)(O82`c{F=+eedLH;`yyH80`ZOA@Fm7iap;a}f`nh@FagrE zuO%wZW@s+qx;jgz`H3{u$KmMFYNJd{mBR_gdT;Tsv;m6g+x)=>k0m;mQ7Q8`(^a4T zC`B)P=$Oc{&nEcQG?~R+xkw$Rwb##Jlpq-&C!2;`yN2f7s|dgMWw4ZCBxhb_`qe@n zAB+iIXh$bMlHN0PdBFg-s9r-#d!z&m9vR5?Wo}UZ1a3%w(CxAsKWtRJ@R3j<6Fb92 zA0J6yRrfTZzn0t^0(J@fE-bg(sXekPAE$7)+V;(|IkV%<@dG9_2c~w>xV+vyQtoD#flE zfHRuDW;oR}?(Yvbh`<*{030~5V2~LioLS|}KdF^0Em`IKq5$suP^r~dJP89R)H~|k zM&-~a9igf|pafLYniVJa|7E}A)0IbELpaElgU;x|BU`@yM;WAAj3}!5rd|^Hx`U+; zx^xUJk+tBrGtp-R1$q-Fm=WWk$TqF}D6+B3=8KBU*ewBILor*JL7->@RaAr?9e{HgIm%uE7x?nk%@qbk34n7X z?y(W`SVyzprIc@%`!GeuKWoW$kbV8a5Mv#)N*vKzOL<7q>z$P3bYA_~)@O3_&HM6;2G4Q_T;jeqb7b}dNdB!F1&;TI>o@5%^5MeKb((Zw-y_i%4SrS!?be*z`{W)-@65OMjt~nytW3vt ztp@Gv6b@s^oRFYbhxT{&)xI_2HzA*- zko`!Uq@My#!W?1NHK)Az(kpDnapnNP5#m$YPgw?iX5V94P?kD4@qq20dhNUT%_~iu z{L(Z02Vg4H1ut(7GKs{2l*b19$IZ;`CmF?X83cwCdV zYpq!bY;8Tz{S(u>LF^s;u}z`Fl$mTi-SC}Q15#x~ae3|$Z$^LjI{jBrD{dX%?aU}c z$#Zh&1?JLf-doR-xsI%}1CLW!Y-ev!h(y+LCx-LhK^M~dv1K@6u37o}ms%Cm zxWTzr-0uv3S1COCp~_1jeY;hdcv-VmnadZjS+lBE-SWQLshQ!nsLq0pX>UGi)pLwV z-{E%_LEHyqpkyJIisDC(TWpWsco#I6Rdy z&SEE6TRy|_0N}RcmpSBQC2{?*CJ7}D{a zSF3ipf>dzH7-P_VLI9TwWq>!8v45q=dKx7378rMDi2jPSg%hu{VkI zGQ(<#Ksr`E)&gQqz-vF*W^jYpJ?bzJT`4SPrK6*1>XBgP0rX%UbPdfFsX?t2=oxql z%C(F7x7ApAiy7jmIsV_<3lkRE;;j%}Sd5HeM>i0D1Gh>QDSE?9XdJxH+f90#K7@4W zi_Y+Uys#t#HRnRZhkJ}g`5Kt@?*k5`mx)81N?{adw9fX{?$6lvV+vTe7l{(@;f%tg zb-kBNG>k6tpqRw3|F58Kh77joP1Omp-PkVGDQ1s{KHanP#Pcf0eO;T#$^l2kQ7Yk@ zszTZOCoD{@E%V>)`G0LV#Sn>Ce=Tte$YKxAx{FVU7BBD(x%77c#m_Os8e|_5)AU8a zB4#vqt%4uaqK1paq9Ns8@KxfZE*Ym5YiC_~G2su}wGoqyl-$I#MNDot9}%1GfZp=Y z(GkO=`7zH(w-qn`c*~A9^@7fbGJ6JR3W-zH7`L9)EiB{ZeeAgb=e|c+D&zeU#AC53 z3~o3{@7}7Z{Ww$eqQszZk&{DvVWLf&f)&$YQg4O&nO6?eCDqf}AIzcUEDaw7hX z4P30?E4S><_Y->#vX4{7IeD8}hjGp;nWNg?(>}-Q52GB1kn^nYcWwh-C;kk3N(u_y zK;nhKhu(f9XSo|%)PaXyyqdBc93ckjhz$Qd-S4D@uh{pzofo5<9oj7Nh6NWter3DXhzS<0jMZbivR4NQ266 zQcm79Do9iJ8h5>KtrV=XI02MCBA08lfIo7kor}3sr&Td^*Il^xHZ5n{WnXPZ;vw+x zWHlsQn47Zj+Ol)Pb;kJX<3G_j<}#GT5daTOb#G(PGVF(qbo@V7rfpp)e0}jccKvT2 z*@efI?8CMusf=;)SK9{${Op2Xct&Kuaz+=irYQr{$c^lJ+k^5lyi~N%ha9pCp8M59eKcH zg}K%}zNP2Bys9NK4qmYcZb)GBIym`(XfJCb`rgUZy|aBmk4|^;k!fD9%*kgbpu?zu zazuVJ>E>S`lKwC`HfE2dYaB>ZdJZ?z)@7URwd9;*e=%-^NlM&Cp8Wjx#te}uA5|<7 zYpLkh=Mzl2<=rC4b6wL@Aty3#_)fG)dYjSpx=v1HNzf7GB)0xM)={u` zHV%}RTHE7G_kCQuxx+9>da8(uCAt#))`F(w&bEsa{+uhn+{xl|(@fcQ5P7~SLq(}_ znR2rR-Iurd9M8*0+sPRCc}J`w-o5?9Z_^om!26D_s@aI&5K^Kp(yIeU8+&#bI=6~!xB;QeZ|`;!J#M%xhch@NZ~sZ z4$Fo#6T2sQ0|5H>>KNI3oU;{~6x@%ndZF_<(atSFF0P4i0h(u@I;eJtfSnIQqnujO zt4REiMFY&WCvQg78OqwkxmxPxj2ja&GZF@S3^V>aFZi~2gCnB zfwQ3>9I%ddzLDyc(vD;YoC*GqgK{7|V*;E#9A53^7Y^f)L`c2FO;AI6QSZb_t6Tm4XnpFW$64P;}%6R0rs&mvwn9B zp~dx$Uv)Fr=F7o?Ccq3PMxurVD<+5NfmrwbCOLgiJ)~3)IL8 zAB4CCo0u}!*2=v`Ek5n*v?B^-g2%+#EK{u6x4N9xNsIM$S5#T++-?Ws<}_h@ z`i%KM5Yf1DKE6|Ly>;IVUR1!KzN{ap6biq+v)jV#%k=ESD zPyM+DQW}TuY2N$`OSly2jwQ}$wF1v-KSWI&coB&v>UiBScolvSv)Z&Z|Er4G$-0<1n{2UD8ZsoZy@| z!cVYTLsN1R)1a9)t)i*kHmVX5sJE3BGuaUlUmh(^Nu;}WRC?h|j{OD&&<{j2K}_$5 zc;~%u#;sw57F5m1)D79EV`8QwiV2x3IO(}#rI*ETE@vK*u)H)+vH^8fRA3k^Jg+R& z?%%KLI4%AU()Z82wPR_ojge(oqPi8W|9Vbe%Yp9S=51f!z=PlCY+$agE!dl3$K^nb z(Es!Wuj`Ket3fb1IhWiq(AO2sQFKl&l06bc;ko0!m3b!iJPkN|diIP%J8OFYNo*U2 zvNS3HoN)s5xcQvUN3crdx1RLH+;eY3G0>DFqA`8;35k-_e4)+5H|oQZmk zb1cCL>o)q69x#fMYa)wY?+zWuQsc6EkD9_7%~G5UKu7sIX1&!~0D6(AeJS<1KMUPW z4EMhEI1oVsyxOYkkjZ#{pXHSGt}jLJ)1bXhx7l-=aFSj3&YKt^aFR8|{6=O4Nb#mY zt4@4N_TI80_TUo7O4*}kQvN6sbX9xW*#};dFm!)svgis%kx?|Gpov0SyffHVLb~Ab z0%m>L|5hLSU-HxVs%H+$foe-)y;Lw?I$zi=#Ol>#`BzMc5i85;%1kuguM>iz%8zil zebM3-vRLIMW9Crrh{@F$mpz0T@Y-&9hW0gM@yU#z+#k!^8_LdWA~^$eLCcMhL!e>l zNeSs}#i85!hD!Hpm0W}9y(?dQAe?=*Jg*WgXSs?Lp+6Og72Oh?Vjg;WPYw}0K#zEO zRjd5=v1L%ZYmEhHUNC`mc%cJ#nlL!A_1c$zZL0sTEnihxg0pgswqFU^Z(66aTMPL;k>Ld?geqsp>79l~Qu=75cC2JUStQPfu8dG2uCFeWM%0r8e zMbqner;DvKBW&@G5zSv*EN)X@V1!3p)e-;!Bg^~A5t+heRo!LwBMojt=JvnlO38?8 zVM%-PasRmnb-WGhj$bfeh)Y}%H-3i((uO)JdN-ZtzIBNB8S;O70Xj!3 z)o`9^o5ux-mT;k=j(`1s+{ZM|edHk0anlbfW3`)MIt&a5-ycRGRl_8dF@_kF_rBGf z&QugN6PFt*H&c{e=4GNuf~Fb|MH~;|Bn@v?CmkQtO(1$!aO>5b`D0Hox%gDAP^_rk z>bag9Q13GgUD$*B-^=7_x1RyLXkvQqVnvq>j!r!3vy~`&_6Je!-s; zzgkS<+Ar_tAHIaNBdJ*4>yvmSr5}mQ%VcyGz`!ftZfT zue}_i<#V+~K8iZZh4JI+13oc3w|iRut4Z20d?#Gi@7{p-NCc8A*-L3vgWKIVb=kK9YElN*WBb3!5zvap8w!ij-Jl4B@DuO zx$+Edzn#CyJHMpJK9JxzI61FwfY*@!)MRw;Qu0IFh{ZuI(C6UCSz6l6!{Ex&t8@Jk zcB%Ne_hGK%%%Wq}`3ZHlx(naY4cF}DRUb?6m+m?dZ6i0+@Rug;$oMRA?p}zvMDfMw z#Mp&p48qRlM~pH-e~g86m>n zD;Z;wC0CXDteRR=%UDsyKG(CjK*dhu6lNhlbq*A=3a5u}x$0(4Ek=I$Xa$?A*s~iaSExSChGrwS?RWgasGGE3+%r=#|OYE7~bCxo;7OBzy zqTem@yIy}ln6rv~C4s)&6SS$HkHVDuWIj0ssRbANl%|SgX_yBD z6^339FqvsTh|m0SA5o()tJ83?5?u7~M!9Qc-N|OSN;VbX`SeL!T1R^1l@*S2QrnI8 zvNjN5Q~wh!j&SosuR6@;Qzp453)>&2ko#Rg$XTW1VtivBRe_!lRX!RG9CvR1<~-S& zxRow)1{_Ye+uYgq?UnN4a#5XC&h9nZ&OKxN+5fTg@dnjWy6~;)`1ZJwq|1ZsR;kpE zy{pa{K33vu07JI-{T*f-Ckvcr?U-)rs;<6M`rc$#aBOp0t1+q|p*dWG%_m%g{x3(A zV-KY?ihLSIwbm_rwi+IcV|6!TWKnmdpI1UYz)0ummeAFsV+NNu3wIT#Vh__4H20k=j$ZVx4dq}(DQ}c09 zCc~>=oW;RCI#bPZ%B72g}X#+Mer=-rjp0_zY+g$2@Z{# z;Xwu9`;*PHRI@YBpE5fV#2V-UiZq!S?z+d+XVzyM{sxd&^uDR;z_IA`6oi;X7|cH7 z^JXCozjnJw`V>6YsikL$Ios$CYLe@Ew9Y~{M-*rr^tu{SDZ4|$VO;WPjwM>eR36UG z#rK8zYf7-pK`>k{1SoKqB?L-w;98ZU>e+hV&DE>I{CqO@+9NKRPv7}JQq+-g;|XM; z{sV-|6v?(guN7~FfhRhd(&`tYqLcy9qcE6N7ghG*a5~)0&MDwyWB5BJdr{vEFAB7$ zI=%mG!CC5OuXX4ZYkKA(ZI z!s%Z_kn!o-9@gwi=d<$RDN_!4Tu<Zs|xWur+ z=BREKhiVnD%BVkN%D#p~2VCl=>$>Njg|ATpaZnh!- zN!9Vg>U5`)6{1{OUg9az?lK4qneRSp=Mx0aL)}TjIPGPIzWJ&D_(1?w8d<5dr^Sh< z#KWe3Y-HV4^EK-eLGQ{P3jxD67VUTM>bH3d>?IG}wI+2dGbullCTI6$H3KmL_@F(} zAy9|k*9w%oSo<5)?JNF0KTf2&9!aXTR^Jf|t{s^=FkiWZlB~OAC3MpNy0`{>52dj9 z;I494MMNy&LarQTD<*Z1>14uZPncoO%jMJWJt@m}yKl~;Ao ziJ=Rky^7O@tD#TM?$q71IdYRT5EH}@1JT4OPpF zk~zJr%Z^)bx4-w=GG7H>@Bplf(e`K3R7({=jnxcc-*L|7rRfG9uA|d&jiZ_H(W{sC z4>7;q2h+1|dUiXQPTcCAmSmD3g za59H(ye?cAJ=!M=($yZbo}dowR}zG+?LC1$WN7k08IHP9u$uo1SH zoS*}Hywk)sJZ)gwziGCmncHK&BT+yF3EWsbPc7#hwjM1uOI5J$+KBWE zHew%mOD7-ls-5We*mt#Nv5%k++I@sJ?PqX!OP8?iHUKjnEx{>k6uvoT2Mx_wguOf; zy**ey(=n<5$jt-H#4opb8n%uUliBHr0v6FR5uWGr=5d?aFBH{fQxD= z)Ak|y%N*U1VG20W;WK@lj5`}FvBdjmMZRGl4zEBl6?=(6xfcCms|9@1u}c13;(MjP z5d#r@Bb5Y*n%4`__F~v*uC(MkiA8UA*0HX0YxOU4&U(mw0%UZW7DI06ap@6VC#6iB zgc{PaPbuz`_Ug&iC1meYhscJIoff6obdA_KEr06)@-Og}f~Q=FSRtni6EedOze_Z0 zpfjYraM9k~=%vV!3-_9Gg1Uh$GAEBYL3r~qKm4?X zkYPNNJ);%AG0Gk0im67A)vo(0-WIZRQC=lH^LbrcmvKFGFEqo0gG$O%CY$Ai7M`+5 z^G#d3;V9$0c1szj)q6W@G5UXk!2Q8*Z)o38Ku+&8+!aW3(tIcy*c0;x{-^u}v+fv0 zPz7gc1!fVHQNiId0U+(@C0Y(kP%C}otot*yVyui}U_Z3E!pb|%u-RK==|dLhy~Bc^ zkuW$>C3Wx2Tc?$u-}82Y2fCaqoWV|uMTZr`w{N8CI7csgJKMpv)&jpXw4|r00K_{i zz`P$J9gec$PRE=+xb<=TJGN@Ywsy#3Kd)E(TXb^D%N(ThQ&LBRx_tV8-pmd2?yg1t z#{%HoMt||B4RzplxB=tU<$Ux*H$s?jLJbDuALOplnzno-T9}zvW_U$ z>~DHiq>~%(iYo{}n?t8*+BUF+v%V_7t!$A%Lex~y!-#?`VXL{ zqPAfd7Nw|EMS8OWBE2O*01*|HCL+?CNGJ5(BE5rx(n3*s54}Tx2uKYbLWj^>=mbc} ziO+xD@0dG^%qH3F?0v7b?t0xA)Sj7Me_p4`rPJMnz;75V=6pHITs-BR+;Y#4 zJb%v*Ag}iRI+14Do3MD^$cxOD*zmc;r;Uu2uav@FmIRu-915;GP99tWgbw5UVevnQ zTnhfi&X6GscgfdOuL2^r8;POZvsWx1@7OI(trd^`67Z2M?C(Xvh3kOIGg_OS=1IHi zKgV1->v5UUdShJWB`LUjN%P+PEd(F-d?Po>IyiyZWj1ie7qs9*x%KHk+vN+6e1kPv z7bk5#lL^l`6N?3!@QKA5Cw4qSJ;4qVWeg^7K0ioqnByutY!l~*mm)hFIwv z+x5*1mXR$gr3n+@si1=*OrF-wQ@GIn(|#`fV+PujR7V{(;GR{c0<^lF zMTkB9v_qzK%|FxBa24B($5YJJSFHDYPId*${xfrKUi-P}g@97AN%miQZwtm2Hre8z z{wc#J&ZvWeC|Y%2@M&b;7{oIP`Qv2e)lzze=;3R4!hE|itzCGPHGM-$=4I6({gu;% zDpe+&#m05z7y=(GcncRbADL|SBY3$Mg8%A^M#>OGzj`n-xpHn++Ls|T6uU&tF03+S zt0ZngyLTozSA(SSUVa@a{+D}BYW9h3W%x*dyq?Zt{$V5K{9*}8Jy`llQ| zGKRa+TDldHKp~bJKi3^Gf6}h&F=`A7f!wDv>%FjCc7ry(rrL5{!a>!n z<3~!q)xp&kTebB(uh z*H}`9w@X0y8<967g~~j9DWJT#bXAK7za)%f7n@?<=jt1K7j89%-}^g+gLMmAEVInI zS+Ni{a!#s}8-~d8Nn+e*YK)GE$e$nNnrEJZ(xp!$nxBF^&e-?`Hy&mTJkiD!-hFD( zG$iGgvP?XMkf_D7Ht`g>pXXdA{JWh$qDc!;n8S%FY*@D*W6K%0v3)S#T-<6ndEOgh z!@zf%rg55uF>E99Z8~4rh#Bxz&%`?5zd;r_;lx})psIWRrW!m)+j$-QN+wBoY|Diy zE=@B*-Qki4k+?NVtZ;m1WZjY|q!06}`!gmRd!%k3tb6%Xs8s^ic1E6<)6w7gu~^OR z#$LRU!HGMMIzt!}osMEW_ zfXR#82dXjCjsHQKuoJ3J8;ns17T79W={`{=cIzB*pS${VFsVgI3P zusP^*qxL19N7Qs8hwgm}Jr6Mn;Q`rJU+m#=1|tS2}5Vm7_`(1%lUIC?bm;wvFz zYDj+Du6+;O9HkqCxZQf2y0` zu^-oM18ed2%!A7g-8iTzQt)%Hx@J%I)0CtLJ9|Nk1;~CEw5~GKc&&DIPkaBkl^QjL zelf2LO5xe_3sb(rP(@ zJ5}ck9LN#E{x)h9p13xK`D3c&dfTFHxgpM*#5n(f&zV&Gqq=h-pB`aK%h!|eDB94$ z$>wZz-ot1yF!3r~K+k#GHoefvK*;{QtS#C8F@}en!w(pgw>!m9@$v|Mw4@#ce0)Um z{UZIl5P`F4$+C->!9K|akMk4qk59tL1tjV>sBH+cA-2`!Ly~&RbDTek5hfkZ_gggj z4Q~8|o}u?Hk-t%Dgd4E%H>ghy{xXfV)-T*`7>@F;I{F#NWVx6tZNHc~>eg9kUdjJi zE&0+Z9aT6PFbKX|{sJO<=X<)@WvsQnrHx09<`HSmnuw)Q1mw7$XltZYv>>y8HlF;p zq*k<3s^jdR+9uTSUdSD0h<`+HnYS@nL4UcE z65QE9R%;6VH<=P*H9zP@5-L75*c(<-*GDmx7tF5dMb+D*WE*ye;loz_1IIp2f_qPM z0nY!zwG8VnwTcOvf{Rnq<;yjMgZYsWn&Nx*f?k?kqNeG&UPptjCE#S{%j)A28lNi5 z#0L&*z%C&TY@XHav&$Y2A{Ha(`q8^ZR<=*^)J2ndvadoMO6tz9S9HO$*hq~Gq4V?P zKYfE7MRJrv5JMuSA0$fOl{qy>!k6f>Y&sO+)@MqOVj?feAAC0JxDWQsjOeoZ3`Vec zQqpTF#tKEfh3W0Qa!H?RP1j-g0)WiuBujCEYAdd?7Tu~PHH4+~keM~#CR;6rwlMwo;HND zT}t!=wZzBv+&Gd>N&+9mu^>W4A1s`J6espdt+v+H=vDPS7i4OzQI)lDIB5(Nz#Y(+ z`YH;gGlW&4j%_>?ZT#5B?2b;T-`c5tTv2lVnK!eHw=2q~0quE(!st5uyM~`l1a`^= z^7vBVcB&Xk))a*seNV(_L@NYjox<%OD~1VmKT)U>D_bi`WXU|#wpJHxzIeHnr1yT} zTftnSA^`^=#~m4i_OS^dcfxb>G=JfNV%CzT)Cl!VWq7gtpth-~paka8UdxqUSU+C#HOWNAyU@4Ub{7gdt3q1v~n|&1ZE9(MgR@Fu^J@>!*M=F%@OERn|E{5)K-2& z4WNtJYtngnM;+9(BA<|@uRbO(#1RVv!~Z-%6xGF|wN9xik*|O2mUM=WTb434s#20% zl4!}Buzf6#$*4;g_JlIBcYSt5_)*yH7^Af}pJY3iiOhQ*K&4HePttwtiox_yY~1+EQbEMkaQ%qvK$AbjC*__SUC%J${86bTD9Ecy>GNn;C?vVmP`*Hds^CD3mp* zvy=Q8>qoJ{pP_C?ZOQ#V>6v`E4xxLr$A7P>_)EK!ickzTA_ zY{YS+o^7IHK7?S2X}z&hbo(?8f@~0*0i+*)`}XYx&kxc!8-~)n55sjxo@RxUDZIi) z96nqnBjtzP|Mdo=O7>DZm{IS=?FWx@5^7P>E=WwAzNI_hF;w8erLXH8Dy3mP!^a{m zC4EOs9l0E=;SRb~*?V=gX^FDO$ZoidyE0C;wm-v&J1x)e(qHu>JyY}LdxHwUAkj2t z&!5?9H=;?qk_?e)(=5$$HRQE>4H`S}&AF$|6`#U#Ydc(#D5*mSB_IvKk0g!zxbh>yT`jLz z<-9lLK}Ty;az@iHPr?nQuz&qnJjR5)OuC1C-9{$sUHp#&+*F&7El8{?jNouu`YIgVgo^1=~=-m_%%Y()0st@ZxTq+9WJPZI{R(7W} z_0)zC73`dn$)kc?q=jDvFf|dV6@0SjTVz6~fKr@mXN|^iV_Kbt@sO++RqMy+B z+u+p3Pn$D1Jlwaedcnor;xa+XeDVWM%EP&D)K>cF{tK{dBKdslmN0jJ^H(+qfs!-z zV!Qn7kmagOo%5;Dx)b`Dvc`plV$JHQ^_5Xg_#2PJh{`(2!UO6@)r?_WfYH~x@WB8~ zo0x`KX}gEqV%GJA`d7d!7YuNLjm*X`T5QEhC(9|zu_)q3$ z4Gh;R{6gh+QR-0nH@mmqVB`4dQh49(E>5Cw`?YGD_1hz-s;Ga##TA#H3Y!Tk#?jI6tit%K!D? zuSJ4(e@Zk{vpd)(ry`_fs%QZ9xhk>PMhsDFl1vc=O*}a0wsrhbO?S@-5+jy>WGa}v zJxd|990nu3jFSWMTxDc-`^YUi^Xt|JgJkt}iwEZ*qqqkCV-km(k3#G2MwT%T{v}~t zD*54kfcj>IZ7r8VDm+yO(K%13&vmCJXxUA_+ zDOx~hg`5#YupE@xeZlE@Agv}fakw~|BYE%w#f!XHJr+&8p`e6oBR5hrSN1d3v1&2Cy6f?_KUVAn!9WlsM*>I)t{LpLhMD{(_ z>HdR}068I8;X%^j*4&xsqdI|NZMdQ1_hP>Ysr0lq5m|1RiB6t-r874{e94X%;|3mY zL?1vps|?QiWTxxwd*GHUM_&7(qTU}_CYVFPVxbvpWQXUA4lbf8D#bH)vSmCIQ#E#v z9*(3O1D~Yl;`eOLXZ+*z3HuD8W39cNJcJ(*k9Me6`dMRX%y!~js7u+U2wL0Wvs1+X zJf_q4hwkws$4j{j#)q>Iv7qi3u~2;}lm( zZ38cwOWGpS=>*!NY20h?nDl=Cri{O@CQD3F+Q`+|lysl>jWDv~e{<>~x(P&1yKqh> z(BecVVMmZCw3sV+C3&Sb^*8F4p8c)Be1+$eooEHRt&{Z5JEY!*?1>UioB$d`9(_?) z=w-DIn*NUo{yr7^z^$ZUz4SN{a{6_<1iAnba{1fX(Dr4|J?;jJdqoo5DN2nbz?&nC zuW16^qH6(5t%uL|gIBxFQXi92nXpT$tmVbcNXhFYIF^DET&XE$@~?NADmemgC*SAi z=+Aa+xp&3zFS+ms@Dr@)meH;0jANTm#ZB)1yR2L6Uw>B?RgS+e)z*5|5FlYsE#Wp` z{GPE{T(YNlnGr@0`K30@tTq0zT9iangQfa5x}a1yDBDAZ^ee|n@u!iEYju%@w77`E z?Q$(mGy9;kS-DG(vB`;ekFSL}jk??Re?NZEYH<2f!{>f^S1A^ELwn$F1ukatTo^*9 z4|9oc{GpIAxS|f|H{CLw6!Rgv2#zuNNBh>$y8U6LhY#m;1(X>9@&Ewgj=%GKDf`Jr zA(h-=)Q;{cZ(JxBDJF5YleV>mR%YIx)wmv~yN0)s%AEK)lCMry12ZDRRi#3r)OKEh z!T8tvb`KvKmKAX+rORdDm7&Jsd*vL=Nf#)>A4ftb8{H=>gqdD5hAi%A#>KxKT9|}E zJy3Fu7Cc^6RNBR3R*QT(CZ_*#M9r#X^!YlueYv&{Xr1#MdwqD zNZ5=TC|231Y_mV;jqCJwZEcBusK`P~A|7G{7~J_zGp>ugWr%HZfEsaq z;`$4S<%$LS#?09JM4es~H=c~vnpGgwmewfz5lgEM&YcPrM+x~!p$em-UH+FCkQ>^g zVfAXff9@o|S!XgLEc=pGphbJ`3Cj7-_n4RDpppmnqcO|b3X9@Y!`I&?lu=;m{AjcD z1?^|tOsU4>6!W^6`85*k_kS>lK+trKzz@>wY`ZDEU+uDLmp~Km>0ZQMZ#m%dQ#y); zeuajGW;cA7Zspx)CrwdxWt{LNHMQ>eRmL`A8fquWmgX2EF8-QJx5{3HJBZ0h zc5>`O-?6OlJ2yo#KgY>$WLaT^fvu31i>f$@N%;~_2Nf%(puig5@~WL0;vEnHk)c2fttEt%%AvyF0G1Q` z7o%kvhaY(;bVOzc}XKky3qB(r^o)%N^X5T~>rM8(!{6c<*%QDljoroME+ z0ccmlXbI^I9AdJ>KtPOMA2M4mvp-#Fem5N83RDCY>~2Lw+GWWhVTDcc`p&eLJ0eeN z>=S?U;3H&^s6a@Dk1&&L68{fdgJzQLwJN)V55A$J9#yS6zH;e@58=%+R0=cg#~9o8 z@e0?Tt$iWKREMgSbNR!*b>06f(UQ1U3rU&qXIzaD386yh3Jgbkp$9U1ATy*gKpNww z&o&_-6H$eni7L_(63#xnIS72lBG5F-3u>d9gTgYcbz3)H*~7Ob61NGn4Zl(kR&VczE2b1g4lN?vFArF(yzWa3q6L)kC$$;AW@8f364 zybBT1K2^}k6u9`5l)AdrMJM6*ap<~|Y-2142(=lDdGSY~N_cQ7-``K2!X}&MS;92W z(gEo}ryz*DV{K8KYu%20UKPxanf%lJJ#O;;l!qME5;?fD=bEJTd&wTIJsIDUgFrVy z8|v89&danF9R1io29Kn+nWGh0q|ztm0c}Qi;u3( zk8JCM7l{``wz7(Uh%0>JQ3CBXyQSsnxI8C3vTW_*I3@RTzlB5j*MZ@@H{4bZru|Zq zd|2jyCe^>20+x?{9=hrSSlZW>bh)FMXZIK0nxV8LL$HO8OmmIup~B5w)<2-BWR;@7 z6i_@nj_V}mEcLvRHLlzA8ml-w(N4*bN!#sKFyvfJ@CyVK6HDFmn%l;d+`X$*dnN8lihDVLymdSx1AM`$# zx16o)6rb98F`31#6AWEIsxZU0(X-|*=N2Zuhm{$Pi&DQ8iHZt*eaFP61v>(u$)b<| zdH2nw;~GA*dGmAX$FhZlA)9F}BnbEa;Oz2{c7Jwf6Nb&mKXaXbipq_I+}Ug;W_{maV_YR4Xc|Tk`!cBlklYYa&J$HK0`uYx$??BzHDh{a=**x`dh~I$ zG##O{FSv0IjswStY6)(t`#b~fWU37V(>_7JN;=7@Te}e7X)U3tbs zMR6d9!=5U$e#JXNT07wXoVCy&BfB2vVev9vwWcHluPsAopS{10jFr;?`XaSSt0A3I zdGJ$4Tjp1B7Lzt6Ticis(&WerJBem9J|YoPruo2#-Z)icmYucBJNN>4U|LA&c>q(i$wKFG^^zGgH_mXxdLqgH6oKS?bqGVQt@) zm|2~v9eJWSF)pQlw0}08g*rXgb=W`MLKaM)ggQ;B3t0~3Z=Ze2Eu4=PnB?)*KO)zh zceqZKGN3e^*YpAXLQa?6pI6K4m7`Bo_+RO#GhP7qepZ~irHIQxBWR7yo6GffH&u-| z?#wB}An)wQ%P;7Pt2paxp>l}O59V#-Wxqes+CF?ZqFQqbN`(+eIFsEU%s4a&@o)j6 z*E2Ud-bTI&vz@Ws+WWniOE`RoxU~aE$f@kPP$P2%`|O%%ee5lIggi3{YRJ0AfwVEM zyxQ8B@Hdtt=pU|$k_(f3-7b4`XD;n8`?ixfIxFCQL^S6HzUjoME^o5obmfs(dG)z` za?+lc9E5PdnOq3iPp9NE?>V&gElKhr=7W7vH0JVtN{_I{qc zZMA3GFY{zac6qBQi5|vw9Nw|X_i$w=(0$QFB}#-`X!h@&k_awx%WV8hm)O9;VT0_& zYNpyNa+j+1W&=4IIVDQQFb_mUAk5^%kEurV@<62e-ju361rEa{5B(Q4@VgXI}V^ic(AGyVxQ(P-Z@XJJYKMdaML`sb&uE- zOQD1uxrO@3QF1mzEh*(h7v7`l9IB9|yli+af5^aFDvLX3Mjk#qkk3TdzCLjwHY;Gp zn+xKXT7Sfwb&Vo7oQNselBQr^&ViPJm?YUhAG8Oqm=@Z!yMNpRr<*UXn4vrh=D*!J z_qD=Ij?IPXWA8&C&I}*9`p*WZM7)rHs1`T4{DUe|*u^kdHX(`HR#lYr|FsNN&uT_W zfhQPR7nJ|cW)FOl6fV#bTMc~zp75EQ{V;zu`3QvDM+~%b`uLH^Ehe@i;9OqGN}15N zssMfUJ9p0Q*iJ8m`)a#)dt;vvO>Dx??nIAW`T-*CF1App^<7LAmGp&pESmw=-x77Y zu(F--?mi%h$yhh*+CDjv^i#UgvL#kq%Fn8WA@a}8zLUsXU6cG1pm+a-)O`7x-91v8 zX{+qKxdPtF;E-0q8b6&Gdn#_}lxeTKqH2RK8n$2?NY^08`4V$cNi#?#N3jF9~*+)M;6)0(t_F?F0hDK zx7WDbg}Pmw$?D$!t3ptfF#t|(@S-i2vLyb2&%U2()Gf-+pVxEy3p5`hh?H4vWXGA& zDuX;#Y3g0_=$U|}@m*|WKMnd1rTV(MkU_hQGUrN~8M2E2SC%rJ$ta|4(;bLbf~^M5 z@YS!>V#Fi|hfWuNjjCB3`%Mb_t;#p-R~IvTY||zW&4fZ#SL5;t;XaAjMetw}64*%n zd%*4IdN#Bb>6L(4-7u@+ruQzPxFNqQ);NV8( z${H?)3wP-BiODX>^fFVfJ19(s)5k`bOVIvTcY!Q$dBcxc>*qRRW^h^QOkiBzCgM#o zYf{-ti-)OE(XUM%(%#j60 z!wP$%*JkQK2#xc0adF>@jShCqoTF$yVHYh3Hnuj9mNBTKPJeYFlt6{ebi70gt&g<` znl2-`R%=CI2M{EdN(L)FDCbURzqf!zF$igXg9=Ws83&auIly4Vri2e4a@g#~fwwP! zt1+@a;a3N?(WT5PifGo?rxJ@XE875k7~YnI)oZh^`!G99dqeiit&%gp0pWdHZKsnv zK^0dYDrJn@h#J|i^ZFR1Q_mgw)d-7B-uVXUH8(bIfd>x{rN&H=w+2o}jo_DzsBh~T zhb`wL8u-5}>&|Ba>Kdc1V)~G6KmJ(rGlO1CtH*tK>i(0fLtid#{F1#<%H$iQ$ffh) zCQqfZZbqE_<&#M`>V%LrC5y2Q!DtyDE$g$N#L4{g8o4T`6r2NYa+8{l0q?Oz3W{}o zJtEPkdrtkLk#2I}^@GXf;}Vzpf`Ex+U=G_ENjI7&0JWI4j}sP$+Mjlc6T~h8pF7>_ zr-qadGixY2+GI>TRswgp-CVmv=9Vq5>QVU1p)w)oiIkmaY?lh`t?L}GNtzwY-Xyo} zn<;5K{;m{9UuZv%9^37iuh~yoaQn%D=db%#n-&=-q2PZT-FH1s{8a{SrRTUijA*=Wz}ACJINN<0_8+!no!> zEuWhB`{3-z2qwoFEitLXG>YWQ!GW~KOGAU|T|qlQ7E?-Nt}k|wtr=d<=+GTipJO$1 z7_siMD}{92VQ{G2*)(=;n*dbx+0O{K37Sp!!Gz7cXe@hK&eCnqSN+F#r7_|&5FYn3 z?=XG!`49-ETt)_L)O%Hscm&v4JuF*X4EtnWcF*6v+uvHzi*fxu13Nw2PIO#H7;4RtFy9x_+ zoe|RbDz!1M`Z~O_=53I@w6C3}K!=kR^L@K#vCv2~sk5|jdN9OriI8)*PeDf-xY>P4 zr3O$3DuH`7-pkP3?=EKFL*+KbH{pH~qg~;DUw7nNEU{Z4?ayNhF4W~MPV)=JKsuk` zBCUyhrpJ@^OYm&MADCccs*G`RH?9yV46*U7IM@)efv8>V{ib?aW+*YP(zs#D$>J<0 zj~n1{OPQx6QPDpF{@)7`XB-Vmj z3XW>HI&>%pqokvWYIGTX9dCECO<01(!Mk=kCB!dmn+8Ck94@lz;0lVQt7T_rz+FOGd)tt;1_|(6?+g9N$dY?gC8Jfu?a;WRJ~7YI5%69!xc}yHe{}fg264sg_|Y z{w$NFrw8H{JVJ?FtwFQbGG{@AsB*=U*5Zdi_6SVn8ouKaA^xU@*xt&vFZ;OgmT zlK*0!ppNei={HP~4jm!c@$FB+;j*fvOr|bK7pc3RmQTl5xYs z_aejXf_*I(e6O3?mwp~f%tn2FFYo<>h4qub=TjNX;c(G}T#6*JdOObKa8y1&2lq7e zxcHCp!5xe${%a@O>Ne+{P0s1lsxBjldea|4j!Sk z{bB8@?gvTlCp@_%j^@#&)=}0v#NB_vU#4~^$uR8SG#b5-S6ek|`UhkLT|16T;j|+TX-st3bX;0lVRHs{;QGo zhKm)$`n~=El=qAPiw?NZSTgBsA*KB;zVxMxEqXg`zh$cj0!(_K4=(*TLG*k7hzu1J zGJX)5dW>ZaGe_UI9eHjWPnqytbG)hR>oY4%j9J|Qu#jeMg|(2*@z3HD>egY2nD*iPkZPXk=+ECt`8S%?>KS(%WiD5W380krSJ5 z!)r&cVxMKMY-F||pK0b*nW%>PXLpG?g+2Jlyx7Trv-8UvCC?-LHn^Djje|>2rbvOw zx%?`F8EUApDSY0vQ-R=ahk?c3aVeFl!I?^7AREO;L%Q4K?EVUDWw#K`^&R&eh@{>Zuwk8$ zT}10qwy!;V_{rN-vkIO2n9DECR18|H#~T`|ZgDn6Ma2arWm%O)@sYiei#}RpvOcH3 z8kHn|{`~n-OIy=OS4~Tcf#D~^7v(C?iO(gS%=G>w6H$tYlNvXJV?-1dlYk`c?0!{z zmqY)Ej7Iwp!|@|C%^3!m`T;nBMvMoM`pH3)sAb(Vlq!`1tw?OGYOR+^+P;~}ab|8=k> z-M?m+_1v1hlllsJJDd@+_F`6)5@;3}tH)H0B|jLwU&I=$XBhw8P1te&8jai`-RoGE zh#I0v%WBK}^y%-ctiZ^~e+$XeV&3eM=IF@CcklY%J$?49)7z+>J*#WM(|&k!d8k-f zFDTswTPDoT7WeZu;ckrKy+w(hHZs#0Pr}kE;x$#L6c<;NrRuCd`@lR&-r^0x)UXJ& zM9g|-@Yg7ZD3cqMSnOc8G@D)K;Dz+$i}?Rk=ly%K|J#rxx0tm+v(uE+U^Q-l`REKh zA7UTi%`Ps6rD&K!9iy6DsJq(8l8o9+jY08^7v8DP4OknLN@9j=QO}p=z-#u}=340I z`+9<5iIkh!yCngJaQvg@k$0jgR2HZgHb$N)zJ{_IL((+N-3vi?;zd-F-^LbyMbJ4q z%bMA3iGD}|mfUh6wvh`kWRExcsjDlDd7v0t?rgr~MReb$X2|-8LauNp^Y(wgJs_JI zNR=p-&42Q6Bxcofm#L|8fq`rBb=m;E!&Ty3m7y#T(IF8lVKY{Mbv?kaZfAKyLnxWD z)P3o{$7bbnrv~uE-VfU{4I&|Jo;KKCU|KtLgXg2x1e0h!P1_h1XLA;1r*M1LA z=DjqJS*Pw&w`!lghWy3#)YMeswJeZN7f?+!bWn`D7MF=|-;C=r9ql;PU64vULS!c7 zP4jlJ8OQ^7FJm9IdXk<{$E+Nl1N&J4X!3|<&z;1Mnw~-V%ZOjt`p7zu!5V2bg`tKJ z3#0Y;Z)F$*(8BU?;-2?CFK+gx1TyFYBDkj z+)i@=Ub6X!PHk_U6K|idQ3~}HtH?6NuIS+UNpTYwoXGJgKb3g1{TJ^s;qS^d#QG0n zCGB6TaNNmVO>W)DWkv0ZV_RU&aa&27fyf*B$ZwRmiP_F6c@PLMJmmd}2&~1U7IN1k z^rYV}mx=qO+w1j9#Q%>gX?d`z8}$ zJ@1qW%vHnMZI)Zc7Q=FNtj{Rsaj>xk`vrNrd8Vkw3W4hO%jikJmcH#e)a*+rQQfanr<*oP*VPh^ zWF-QvWUOH1i$n}f^?LQo9GOF={R?{7!Q0lDnVG8{$2QW?pViw$EY8audMZ|NUb#6= z>Naz8p6Z#||IF~l1X}oflz_d_@c8JzTJirgzQ^eJ;pO!}@NBlPVj3G`JOwvuH`@d@ zzk!pr)j}Mz9l>-X1K0fHf5x2BQN>rEhnngp#KIcKesUaOHzntIb=b%P-^Q$dKrnx} zq`c7@`uL_@33aNEX5kcYpPj=&d^Za(0kuDHf3>t=GDvesv##PL4FHDRQ0JH6~b?^k~O0p zua`aHuV(TFc^IzTHg`L^mX`D8O%}Ls;Tt;|7^=wtGo~Y)?3m2Q-_pcb?nnJ5RkKAP^OwkHU zS{x>6QHLG>bq6EOx}b*qNdGNi=^|Ti?=2Sd(+(M1Z^T_rPPs6c|a1U4iCdnrmj7rc<8vYt${9-V;V*kr8DBu*Y`nK@PJCnSB*q-jyxdGE$RuFl*^r0?> zTY65+63w$FZ=9}c3B*?R6)!e}vLST^F5aZn6fS`c0@t1!6k zx#Ku?O3(Q9|8jZ%=g=lA%gq^|blS(iKPd8Tuo`o|RPtkzByYNZsL#$!Bid@3Hl;({ zuo!2K-3+GaR1`Mq?uTx(`vc*Qr{ebK5PXa|*s{fYog zXSz&{ftJ5VA^vK-kf!0LSMs4&ICB`{O$+uyFFNo!s=7Aibo2~6O$n>-hW*}Nu6cj; zpN4?{o5Dgo_62PgRG7Cia@wzbQ!Q@>?qho0bb^p= z+E7Vg7h2+jx&kVnG^QAAMR{%)n5NYK240{%dfdS6$%TIZI@%Qx;w2UxTVQ7Lm z`q8bPJUw$T`w!KJ1w91DP@PeB!JCDjZ<0G4yxVjjdoZ`0sXA;vD8VIWBM@76ivVaS zdz%`hO1axsSZ*h+Gh;_EWd_pRWeN*Itj#^vo$D}ny5V^Dz1oY>;ptq-IA{a{%9Cp5 zTWaDH7T3;g3;oE}{Va=yh=-^72JP-pw-~kRdn&-Cf;3X(J!^p-oT-yb)E4u*yr@J;Ct4JzLS#Q;ROTm40ULYyu1L4)y632i`rsMD7FB+0DmPT+4D{^k*~5`L1_Ld)qrJ?dw^LaA zN=4?%@i-}~1nvp9KIVaZ z#T~{xsiwDIwMv>+U!ebo>hk{)Drue2f~SmOBINLp*K@zL7_A4)$`ugv{bYa18lypas$J<2!2q~rg?XspTIAF(-l%i`Y zC#K#?uFOPTLEoi3%CW3^Y;e}utcsY@#jIJ$VOC3!#P!pB!DaX{y7Yx1O-X7f$~yn$v2RQ^^a zU=-!LKiO~}#6cR7@T`t}t1EQ^K!f;8nWiQF|=RVIvzTBl%)9>%4-Lq^rY7(d^PsPY_R{q$7EH=AuQuYgjRKM?>7{ps;xwTz>`9>4cF zQ(<#($@|klL#h&IOLUygwyxw!7)ZuKl!6v!& z(KdHQR1E>m_ia+iMnUgcLv8douG7qTAin!)J37r~5KZI#faajCX7m&GIMnN{%a7kU zh^ahcCPASKIR^kMY^R;qv%1=vL3A0=goKvE!wP z0sWe{VLMPE+ezbF18NDn5?D_LWX?7*yq^r2Qe%%%o~mXqDX}$mL$uXI<)y_kE4g*u zCPaq2hN@T#Rg(Wo?8+miz6)e`hi5t-lXPoXUjt-XV`P;znUL@PKdZt29JpLxrWWO>hfeqbU4L+(CIi?#74CV{ex^2IVXOb;Ov$T!MyRF8(&Vqc!c^ z_DYgYRSv)J<7^QkD(nog_D~BpV)f!>RHg?mCdYH`eQT!%l~4opjMbMlu?5NJanldI z9?Z?ChG%gQ;EN^mIcCSxyR!{L1k5f=(!5xN{OWJ^o|!LmUXEbf-I_rsch(?{!M=I& ze&ihe?oDZ(k~h2|U86&+a_J}9^S%V9HNgy3RX-Y-FE5l@Dj4h`{nH8WZP&*7-*(1u zyIIkm9$<&QE5juJGn*Ldjv~SE6TP;s_IZ=%e4p}Z@=1wbK4E6PJb1Vv_sY~GfAE_3ZL3$ z9Z^wt?OUN)PX|AV4i|IVQgwMag-@N~>z9DmFV*w{Vj}#br(-lLY?AD++}_dwsUCJm z>|hzKuI9S7Q^i?im_oi97JZ)*nj-S1*PF#c0*J8PO}S>HA4xh^e--Vi8?X^n_q!vd z>h`-RPF}H@vy2_Na>s7K6BooqnwG|48Hi|IaUv zk}6Cic_Ly%2P&KZrMG%14evfYF)Wf`4y1FelAQIWvvSj@2Hq}ujiw;5g+PKR6G#GI zFE1`P(~hR0?UBRpwYf;$Ie^3ly1MdwOpxBxJPBZ6Ijo{k*zw*qA~8gpi8MK3&6GZx zDHKvFvPi{<0I}1KO$rNYsyQGj^Q;Z0O4v?LLyuyrss)SYW1!IpR`lb2HlZJg`d=xN zKqgXWF!Muh+CrTlkDC9IDc!B%gYFZ%@5DLeTa}JBMGD@|Tgt9DYsE;s*z4-3^NIt+Y@*WKOzZ^`{71lBl7=M2O=K)9-~Db_^ZH@+JEXkv>K&XLb9+L^o>uF zCP5Fq)Z|O4NIogN)TU7dzW4gX@E$+S>FWQ(*jqrw5iRS&2?W;!_dp2l?hrJ%yGyWP zaM$2&!QFxd8*CuByX)W%!QJgm&bjBm_q}(|eSfc6(=)rf*P7W~Ro~ZDwX3Fp4aTz| zvg|R_0Voo*jkjudQ@fOrlj(KxghE?P+WujY5qgM|Bx51%^W1R5@{SGYob=0tgYAP; z)`>)`6m!q!bilu>F7iaTDKX87ux9u|!yCcTFW)QOYWu+`24)hDcH_@?`5%3s1!C;g z@VF_LKCRV#b>nJN8D?;NlshS^z z7Ao_qtxVmQD=f}+{Wc1y5Zu);h!ta@X`O{NuWeCLz9T6t-MX)>JncyEPhrfYK5t93kIdwrvHItN^RK^?0Widj;)s5-sZ4J9gRqwPaOq*b^(zeFD1s(d32D3;J=d z$eQ>CPu5bX&Bu)ooL>9Ky8XTi`{e&!DEHrPHYPUM@T1f?U<6cUf!6^K1q?^M+)bxW#{~9j$(5mV2Fh`<&>q^Y%f&H%l>rwln#* zXKu&-I=V50m}AF2+C$Hj>F$?Z7bnNYJU8?OzeeO_oMAtKYNH2%Inpgh3Fx}kvMtda ztSO?pICp@*yegPmWf?uxla<0P1QtwGeaa%_s{CV3$vD{NbjK9i3IEuIal0Vkew>Lx zg=oHHAALDSO$Hx<0t=ZWw?X~F@jhNYqk>ej{_PWncB8ul-Wa7+_fU$*ZF|4d9!ga_ zteiQ5E5vqQZOz;3m&pv%ntWF~xvC2XR>R7N$byZ6$29#EPo@jQtx;~nA|$c>0Tc)` z$xAfky$$!q@D)eQ)8=DpTX`YIr++83(8Ralck(S%HV^VlVKCh2SPd_Hdn|oD#v3J! zJc#f3pX{4+e{(_jjyj{Ioa-yuZ>m z`z@vb1!FI2P_yy49tg4K){5X5o8<3Wj??c_%8Dl?4t zq&IEK{p|%ab#>#oR&Hb+`JmZGkbsZXu};#+L1^A;PilAdz`2A*N?ZryM(M{@^<>IYB`MrY<-MjT z1nNdN9)7kp6KzLN59iK)FXmNm|0VgQ`zH4(2}3KvE8$)?9Rh9cY!s3663R<|DFWBs z=j;D#E`*fD-#?8=dy*p|I1-R+I3C0M?~MS{4MyGuG2C&< zR%#OHauaY>(dAKYZ4hAfrF63}C_8gO#@u3%d}C^gW|!BrusGgkfZnIBH*G#uzA;pU;c?<`+CLi+w-2a(=Ee=?8GG7 z@gC;Y@g83TgkwnmI5)N;d99F7_F2-)>b~_w_zGeQ9is6jGr4Rhu*Z0U-`rv$2rJ^WYQX{|RIN`fir+ z<1MJjLxkEoloONcD@vrZd?t;H@t-;t&jja}0F;8Zv3m&1529dqRI2(?Szu1)YUQ9s zCMUxvLf%SlD;MIJWT(#FdPUSXQFN|xUOE|60%qhh+_5o??kZk{&uu#*s=Y+MF|kBM ztXznKx_IyW-E}4cZ0lh!asx;jpMV7l8tT=VAA*|c>tIFaF_e^@!SfPn% zV54obo>w~2iiK5iZj-IQMI2M!wZsU#8w-J z-_p6*-dZmU&+puj+^1ThS+!spYZwcYPl2 zl#=Vs%E=kfi*n=U;TRjy?xJpLj8v`@izKs)vrz43HTmr`J4thn22Xpq zH$aiY7wd~*Yo{bxiGQc(!g?J^H#)*gdbK(uHzGAdp%2$Qg3f;nD$v0JDr&5Erh)dB zYF3AODB)Q&sKiuO3BE=tlz_Lopm2J`8hG8H(K-oWdtX}PBsT+bA51o@ncy&2w9unF z=`F|IAd~)t_)*szki!`%={VOmzQ(3PhARS7dv zXJ^73;7x&$XFvyBbdxOWQ?pP%*Jls-4Aef!FMF0_8>~MmW=jL*+Mdo(Q}i%L>8-z_ zJ5dq2I>-3fHH2rCzQLQ}1_vazRbi1Q6TV>Bu zOB6_YmTtIhji-9}hAlDWHe!5S4ZUc&!#bt7e61~tIPtiA;cttQ|8}!cvoVGw@+|A( zPoP!77-!g=1u6=;WHrulx%{%%O=xmWmzGkFRPYoD=S=iU?soJDu@I0$w?UV?OAoQgLjJ+eT8T+_9tt?pE zdU=KuCHoVbs0e*RPk(T2Q0iqcLE}wh!TxL8FnGX39ds<9oeJX!llI`%gTxxpxk=lA zzl9`|3>%$a*p^PAPw7ch{3m;(x|7xptSe<8!p-5qzB6HpS7@+ohE7vZ(`VIgP6CN` zq0i@^U2FC6Q(4!A%vW1tXVsu3`u_WEB{@2v%mKu$MvNKFL|^Yg*Sa1>bCMoYf{WlA zXXF)Vps z7G;1Oga&mEeoL2_V2h?YS!R4|LN593=R)_f?mPHHfpWX^r}gG*#_P6zK~CP}y^HPX zoqj5T8@2CvrYuxP;;zOz5JeqNlpj+Yi+AV8m=(Wh?^bK_{ks4}Dwj^B*Ld&a6}BAF zw%^F%6n+Mm6;FFCOL?EY$Z|x!Y5pze_4@hZ`|)pP-79JJcPV5&bDz9SEzLSJG+CQZ z*t2W(6vnOp`+4}Ai4&3Vb>F?TfTbma)qXjSxZy}=T=>>zyL!-Nxm8!NIC?~RKWzr; zILNOupJy-KUG7rRi$V%$%Jwf0R>1(@8sDl!UI&7zMgz}Lx;v=s+}Trhey3Ae6FF{Q z`r>mappW362?Scm3%o#QP;uTyIa=DFJ7it9@d(+2fDH8aRT6yy+V4U60H; zy=yNwPP@DRmP{>dn|&N8E_%3Sp+c)hnUcYH)OC-+J>;!A2h9 zBOPAmg+N*8%D?Yx$N82N6c^eDsrRQo?v4s#2Q8k~0FpSda&s|l!9J4Z=`e!dvY__q&Qp0BXza;p)5|H1J(r#v3~2~) z95=P;W37JoqHSk2g5a;S)u9OYJu5IxK6y`b2Vd_*IsKfbzUZSR_VF6wfEJBI2;KNr zqe}ns>-efqzqIn2AF-d0g=>|)8?pT2Wb^lrVYwxUHzD~Y)$^7dRD{ul1;T(C$~j6Z z$hIlabro{*j}R)#JCCjr=j=)BO%^&6ipC zV{Uy}HMgsZ4q-n^Zp1oo`48dUSNiGa5>R8nZ*x)Wz_7BnqJ#dYKi=SqhWRkt%T;*WSlZYOq0HCNH*jp! zPX35KqC*nM&FzuVQ#1&cVzXYZ(&pPi$F(A1w$zpo=E_o29DB{0=>v>_sZIxF0g1a7d zGbuQ>J>#mJZGh7?xam0?xOG|R`f=pf3W$ME35n+m-H;OUQZyA2vK(wzQGOxNUaMvo z0Tv9&wF$2HvM|ox zC$l9?_jw*s4VDTQ-arl41SlQkYbA}ZV@yXqc!(#AuJ$IzXI~34Px2j-+kb%4Y_)#} z%wO?XbZ6a-Nb(JI32p62FU~2#-j(N*^@eMJm@jQ9WUkJK z@VWonbbE{^mbHsev7RH9lwC%5vOcd?9=Oihj|Vudax#vBp&l8uO-Ke z$jC`^zET1~%jqHv0_h)5IRDe!1!2l-BDSns#Yxh_a$G5_Ieq0|e0QwMks$-49<-9f z@eZcUHdC`yE6Lyu5YYayA|v~{tJJ@oi3(FCf^s@nwnlylGzd090eWp1f`Gw}Wp9=U z9fyphN+r05`?zpIN@0w3xWjDt^A_Xs5EmjirgPl}%!SD7Dok;{XPs4TsKH1Y)Apw4 zt9Wvvm|C+q2blD!-SwipMJPMhxYGv|!`Oo&YE;G^Qe}G0cjhmy51@|sdH;yv5NO4h z7bNl^$ovHauri*s`EtX zQFqk$)h(C$z*~WBt1a~;hzd(5@4!Si*S>B0)NaZ{Bu>II6|m$R>*LT{dLTE*J(6=v;1REP0hYJ8?i+=qa-2HwkrY~1{EzAq zglWPYWPk8sb7sDRm{MQcj0N<&ekl!G!q}-gxT}K-lh>uY1`IwgTl!FT5s9aQmRMWQ zsc;9$lB9LBT|GUyYX068=5IxdN+cWx02F_yLYoYe$e@(J1cgtXFu>r1)T56~cwlmf zPuO(zFvaHAsh;BL@+SEuiSjyF(Zo*h&PILn0P32iDwG;j1ytX>Om>1QG*>hc`Z`dy z32BZXj;z)CZLpBuhpc2`pBQM|V zM{X{D=5d;&FThrm-*Rlu<9?D+?=2)@4mRP(Oy-*>>W@w$jqE1(k^#FDgJZf3MYRjJXm0 z$p3a_TWOVM!_%o}u|vlw-rQ+cku}s0C;-*HaTYINQ5r&e&BvDE^*5roo}^Y&=ub4S z_9c?>C?i4S1qeGGTKKN)W!hI>(2;KihoHH&5QB9KAt-nGoFPO}b2`7(6VReWBn)M} zmPSxs3C{zWX8nROO>&g1idhb>#u5n!DT|@)s$7J1im14q8~&gFJw7h)jVO$I+dwcfHMZDcQhJO{ zSxg@+q*`(l@3<(#+|pq0duEG_$y2e!}?(CG^rygK@CY{|`0b%zq%6QCwQ=Q!-D&N*mhEWXP!HliW`{5SMdHrWYFKN^2w! z@A~S^sarne*h@}H-iYvn|L}8FPF#Df+S@i@vvpAohJ1m%QME$-By^08PGGhy zfHIr^nF9bXZOr$r5cKTEoU2nO!U+iB5;Jo-5!o&Sup|+bi~{=UZXc>wj2d+cVDgMl zwfCAezd+j)_m6kGHb{S=5w2|4*4EzM*-`(^j7To78kd$f2<^-HYlVrPp1yJ=nNjzk zM)#ix5(fJ<6rIFGShHmgLWHyQ^QWGYg%8$0j%|w6>_*@^`_VS!HUD2gZP_Cu`?C*;uYhUtcy&U6rXvf3F?end?Yw*uAk}#-pwUbEZa(61|%pj8gfhM8# zC2yzRA)pohyNYFnslV!*3SfgHBmNL=5K(y(QCVA=%hMJnO2gvfJzeBtIS38+hyyhA zaXZ9sQUT6r2_E=`(t5I=!Q{^u@~H$dN&@(zDcg?=75PM3n!167x2gs;9R+q5m%#d^1=1teZ7btlO|Q zyU=nYh4AnY81;4l|9e!Yf7{DP(>HAJA5HCZtAvTan%WyC9eS)seVH{wHA6+ex<(*? zjbnX75D4q@{H5=W8LCL%x`?6Q-y!HY&%`|0-y!Juf1dhZ$I&xcE!Wz70vWisd!$?O zt8O#8BSRk?3?zP|?c9+YRwcnFRua=h2OGC~SRaR&ZsDy5+XTh}GRrIbN?$U{jLogW z0!T0^z>EA3FAZnQ=CfY+2d~i#R(}U$jLo}lyC^U}@x~6$F^_*+i1m&wnc@)Tn zEoW8!Dz>OvVl+B^r7JjT((uwDU%v7x>xz{&`aXUOS&+Y*_YkqdxlN4$B7B1O+wK}3 zW8vK}z-f>ib8@vIBB-8V#!S`dYX6_<%Ri1rD}SY>{t9TEREj1ejqa66615@{<|{iZ z=<>p&oVA=#n9w5dPY28N|JrRD)Nc2zBzlRqmM;aeD`u20mn-3>+OBH?l)#2>d2|SO z8Uu&+lL@EH1MM9G`j=Gv zU%K+22Q2l}a=4!BG)d-5*$&?YU`dDtIvAqa^2|zCYm_q|hN?a9a~dt-M%LmbWYxkh z%~=BbFRG+BSfKWZRepMO#G0Xkrq)J7_sr8Zj8k{n2t;&;<{K-{aZIxrVDR3vUZzMw zCN(jR!tDD-k#(T9kuHD%^9SRJA0h@nYL^~uJ^3M>GtfR&L7Ud*^%~Cwx!iuDBtf2e9q_9iVa1Rc7vB56qtn`03 zPYeHtc_J@ft=gyp;B2hjHC2ycyRN$lBkS?fly92;Qh30HgE+t*2K$DOiWx5`nRR1) zrqXqzk!$!pm%Dr#;wswlOJL{>{rzHL#?KIWxlbS_8UGvl?L|U{iZIL3BDU0eq=*Zg zAq{*TUiDbhYxgf!k*ka{1XJWm*xjWs0KSCYu4#pNV4_O3%VeiaJ6~fBA9(7ed$o}- zN@l~bO2)|^z@x~&wK4yQrs3#{dn)Dca^%3f^q<7vl8#i~Syl0$G`QO9cJOx{CPLGa zc}GD9uyM_ztDu0WPBuC_Dh*18AE^4X4-#0hK0f+edYa|nLic~?*8AGW;Owp~){+XOa2H)p3azCYma6p4VjiT`|Tiu2r zH6e?+boYFl?Lx=tWeoget2^)r`Tt`;6lw6e>tW9)jSy!aSFliv9@M`f$?3B`=#pFi zQe!wPGsRF3!vq9_$*q@c=#{pQzW;zZe&@?beFxCaWds!vmenC1=2FZhQO38cCVZ$t zBtRD9?bKr~KU90`noKqe;?O+r^$eWyE`>~{f)t{9cR(Eq>iS&8V1NED&T~rE%24ehcNt$c( z(f!stYG<>y-;CS@pYTDCP9Cg#q{dThoZ>&MFdbn#kmW(coz<7^2vieIjxQQZ27Gvh zok|Ac3wEOA;qwqgagQx}rhZM+o5goIRV`V;e}DUjTCKVp5Jn9_{NrZKGwVl#5GkJJ$_+wZmNdJO>}f zNE5#VOjr1TpVH~HFWxizw4s+RGRpH2`>^g2FSaZm(%xi``DPF)wnVt0gq#=K6*+#* zw{qOOyg6L^L9!esV~lUC!oDgf0Jx*h!&81>~Z`;6Il=wI^l&#)0H28J{ zPG3YS^?Mo1S~f)ea`W*eE&tJ{!_Z3pTwuJyU_MM{h0RQq+xq4vY<*hS5Ah` zrM9`}vh3XB%ifZ#aKEg@Uvo9r0EiGSLOI)-*Ic8L1M3eiA>CQR6POs3;et68zMJCTmw13ldLwv zFVXCT)<36$H^B2BpsqUTpP0=TJ|80U9XCwjc~4b)X^k#);vo51leM)q9K*IbRo5W1 zf9_pg;eNuJS=T2FmZQb?%O|nD3HDC!qw56st60Sviu4}k*v!7hgLmH#jqW)MXwxqR z+@6i;zRlWZ^n?lLj4XV3vl@z=dYVWw&h`wp`D6T$Rubc;_}C(CCcxELCn`VEIwb|2k_DxKv&B zI7d3!_k|^UI@63P<;j5x5aDFvh*voOD~ktn43aeQV^3NpFN@$yAZ>o+{hFZP`t?)m zZvzacKdt=^W5$fED?6u82LvZi-Q0<%@@@%|7xSw9tUQ5D!pXBnkI?0<8DE`tz5mIae}utyO_KthnpIKHpP|T;FK(Xe>vr zw-s4d$67Q?Rg*{c$RVNsFi3PY&@$7BNt2NKXlU$86;~XeGe4p(F>CZ`Ul>%68db-D zF6fCWg?238KY|H&xW~G4taxXWL3d>eAqI z!&zfqkrXGYJ7AA$s~AOA4Z@!wFSO+&|4^gR(h>NoADZRO)BbR5$#w(j`dF}MAL6Fy zHkMiN`DnQ@vA4`sDfwBjYRv<;*4I0GoGMdHqkxeot!ra`t)pbmum7rnY;&z$FpVF9 zQ+$83iD1~e9d|Zd#n=1Dq%s>6N73cX^B`l}vZ>WXm~rR2DV)aQBPdI4&<_XXJMRsY zQu!^p@4re)b01zjCY;4@anzwf#fTvkemO?aomS7 z`^s6wf^jhXUTU{52FY^|d6#J|rVvf%RxnejqJ>0A?)7G{xs{Du=k}X>jz)7DmH4Sb zX?TuisTmrvT*}o71G&JPQx>)2{u&*i-@koe*g)EV_j}9DaUfi3>M$)n>z4%rRn+T# zn=AWL2Fq#;^Im-iUi(>CNS)`nRe1L%`@(ve4z7p|k$`KkXb{OKe?%YGRb|k-w%$Dy!&06i5et@9xSMyT zX!K2;Ls{{hjm5FFAkYC6KQNs*y%+XTcLonk=KG&7%-uO;;gCi#RG ziQ2Oz?ajhZ6aVUqcwBG#I8`kVOkSIXlg5QqORYVLD%I-$YQJt(!lYNaLmMdYo_dXiDvJF4h8%Q(;ffmDlZEtM{0rf6wbEo z0;8q5DYM>gwd*ySWE5q~6>kWjC0Tsg_)v$CdcHd@ch_IM%(8*XcGz0$!kWzK#rTWS zs~fO<*>Flb1)o+xWjfKu`%@H$Jq7mkMw&9iMXE$IrTd>%e=x&P`L18e*7cTWN=3X zN9iz$b1QsHxxvaCYSy5|x)K2yJ<8{mF{8bYI5H>k!H&;=aZ;0~QNM`GgEV*cnwNv=`7#d`*2P)X|ha4;O!i_lBv3o==;pD*4jSwJJRZ= z;8aj^njFZ@OxhI2`0DZf+pu%tD~2nx=$PNB@nmfLUFfa#qx<1h<`luJ$yom(-Li{( z-irFIgS{W*{zi-;Qy-)$_~DXNLm;IGUaF zIjcEikMm_nHo35&Agv3H=4#_(%`q3c3%bOqphSuV4$EvaHe0Qr;s(m<+T5V2WtYUH zL{U#Zt=#;cA1#v~B0*qQQTSAzdrjEH4aUU^_@nJu)3-*2Z*3L}Qyk3f0(S@DrHlMa zVZLml%IW1urxJ;(k#j0Aax0vvhO$bpQT9CN zX(5y59BwOqq;}DMX^e9^MREo`uu`ZM&2J3Fm<>7jJp20vZg=4sk_M&mq6_t-6$8ZT zNL?An1zH2h6#UX>=Ul1Ud81ou$BHFP1*=`>e;+R~$3Jh>Lfd^=>8;Sn;A%QC04{XY z0J!w4?(u1GgrYu;2W^IZT?J!w&Kq5ie%-aIC#JrG0tOGKFuunJoVIG`sKYV#Mt}M zw9a+7)OhVz?;p7ofSs{r$}fzux$WK&A7iF?NDV4mOnb6%`+iG?R}wDVU_vUEms2gm zid|!{e}$WqfvMeI@i>{u0-IOEE18#{V8jOy@q9;;_lWMVo|8co_PQtTMyXDs6V>Q_o_La5#={srxEY)WJPz^W6tBaA ziTNI5S?)-bFM{oi9Yz;MmsqF-7S+zR$vj<6si>BXBya&qG=RywiYR_AqgHSH{GMgq zoHQ@jY-~{RY-Df4M}jX%BCIl$R!Zb`)8CEs4(pMZ=LH$GLJN$BIvh_EVt~Rs8u&Nh zuleus{u(QLh;A|4{-a~vWQ1ufe`X#vu`E9pg>2E;zI9oIMjl;vLv|f`=(I4ZQT4Yi z++XRcqa0TkhYHSvhsz$*(aY|a3EtKEV$PO?)%X9(1t4-VcoAk2{>B6A>0GFLDn{UP zGWrBKphMnL*v~)Gxq-vVx%)K#w22x+#+w-E_4gcqRN-@P-^(+=$Y6|Gwc2RRzTZ|d zk==Gt^QuwWw}j?1w3GG=4oTEMUm8fC@jahK375e0w_KU9>^)!nC3>d??m6uO{NMZxY+gAm{&>Eo7wGN zmI`A{VjlPsTA)e);s{>=Fj$a$fXOe<=8E1)uDjJ{@Z0*Dn*zKD1N4W#4q_qHfyqTXKB6 zCze@Mkp&5{tPlC(@)Jyd_7pmxGofXvmSo)7YP>ykwPR?Mme{!)h1kn{m}(VXZ4NGz zZJ+Gw0GE94cbP|pDoVEXT6{6PF01hj&d9y9Pw?gJ!=Y}y#NOp|V}bkiz$cIE0p*cQ zl_092m}0+9fD|b-ZH9F4)%GQbbPgqR&Zv<6g{8S?Npj;Ov^vKOr=%sFYS;cRrI~tAjsd4vQ-(fHy$e-mLXL~5u zI0srgSI(yn3az*=%}_%j)s9HhjLE4lrrcZK55TMEYRkb#L0@dD~OE;O|)xy~sEXQ~ryC zgw%+c>mrr)F};PrV{9xg7MRXMBQ*2SjgZo3)@!^Yi7=PK?snuTds9Yjs=weGQm}A- zZ?>Cgt@bcU>?ck)7@E~lA_tp~lJ>M8LWqFmLMb})9G7^tOK|N=H8nB3rhC)JoOaiB zDe$@($}nQk6ND1G`I9Jn`?w0Xn#+ryH$(I6d3&$%8L#2o_hU3s)+==knNYIf$}@(+ zqdQ-%pI+a?(ebv8L3h5L@J4TFwbS_3F_MB5r-!i5K;*daI7-#1*=lI}R^wLX zZalZe#pR-nV+}XR=H~I~xG8~mtCJU7ee(8VhZ$OnQp)LkW&GkL1x5QeYX%8FxZ2~I z!dx+JV5`BPYu`>|6za^L&-`>5o--qVvwM46WOV7>*9Uk}pLK~)ti@PtC6 zQl}4teRXqiEwhU?MQEJ*^d*Zr+dZJYz14m^M-*~|7$eMvRydr>ZAGU`s0!oG+*fmA z5J}rnWb$aj_(~DmfTP(75;uo0;@o@7zz}!C zdLt>615QOWsv{n?k}9N5?X=}^ew8?$aea*R=~}Ih$b>_IfQ^K7&AmHf8)A2|yezN^ z366bT(6p1BE{t4@`}bj$cWP7pUPG}L)0_$TBkc8E=ytTwTQ^ul=a7A$MzhKn)X*)5 z@PxW&nyFPQ7pHICQsS&QHn_|tj#s7j6AEcOZar69U*NztF2aHZr#CRv)>rPeZF zy+>)6UEXaz9UOL2NTeXb({T4i=Xc8gPF1tfFEf6;xPJ|TUy}Nd_`#Z&GY3oeGwFm` zWd*(KdG0DPhx^CTjQOV*j|4I(c_@OPZ|>_*{WI4qzSlB(6l$SzB&gmJ@Y(G(knz35 zUCHzxY;Q8jf7*(hJSxAVQiuev!L(&e0h)7c8`I6(I4F4ls2*2yeHDI`X=+dtFIw*3 z8)wd6W>mw`elRRrxuENo z`qSGcGSVBr`D)q~i)ESLmZ17$HIVx1R`rLb@5eViR5l_JRuioigCv@+=8Ht8_cwtK zBc7MyZ9d;94HfabMv5_ZBinC{4otP>USz#i{c=Cstz`ARp2+OX^8aw(aZSMUt8(AC zW!btTgW_^QYz&6Ro39>Oh2*#2q@nMaXZ@*iqH|Gh49 zHvi0dqwhs-avT!UT2fVsSqDBpgnd*`0yeKXWQ?M<;fF(%y2H$Huep=NH*4ks#G4Qo1MKY2VBkC1$c@$+Lz_`Np1Tl>1&O|X)n+!P1* z+8CNLPibjawGq6wGKO$CtOS&F>~0s@Udqv|_I)NyX1x1>@p4J+>mp;APIQgg%Jdww zUmG!*dPOW0#pMF}+G@*+jcDA34NO!5k>ei%_Ee?t*0=g?$w@@{Q>&^k?7|F= zbkU&?=;k8UT?A^SosZ1c#mP&CGbxDt!r47zG$pPG(|ny@R9yIyNX5GU0k^U{(Dk;r{Z{`qIg3+ggq;!~fb79Ok7C(Q?-+2h~(HP=*BHexA;EPRKGKCp!5 zi0|S0@64?0Ro!gYkItX{)#iIMVauPVV)N6F2Qa^>a72kkZgxC6+i=(tH$vQ?QLs6r zuAc_@vq%Iy+Umhm@aOg3Sr*44TC;wM$kTL*j-s_P1h$S`LS&J1G&?=vV(>=vELpxm zs1nv+O+9?(JAL7;ar%ALEDNDc#`>>ytxz*N>>$wi_T{%G^)NIXvO#D>kr#s=$8dog zzpetL;;==CB6WBt<&t|??Vx$$xV717kY#Q+nnW~l!`3%OHb>8Wb{Jgy`QdMHE-VPy zf@OaghQk=1#E)UjCq^!Y*B5_~Y&_Ry%&Z959x}Y7aS8wReq7-3R(gBE$n_DfU7%j# zSz{geXJ=mgih9+jnIO>aKF;lwNa9dr^>*aaZ*bJD{F{Z&dY?`MN*c>8I{IO}f$>Vs zpQ%SB$!MGLyZ78|E_-U(K0a`GD|0D9zlS#~ut{I=%-f!c9^7xWA4$4Ew!OrHyR5h= zBO6=eVEdJ-8brxBmzzCrj%NIdbcZfjtoy^A<0s!bTiN2(P=~HyZU;MCR$3Ppfo3fI zYgm*^pwj3c{#=Cci0>Matyxxn_tb_-RxCP>UCaufUr2L%hmg20*XMs**0S#jawj3} zx!j~I{YD6l68OQi7rWV~IDak zE=4NM9kWrx&81#24WIRJ`)T?vCi6$|h#~gIQ@mGLtCZhnwQAoPq~>6yl%3yjoLX40 zkJT&T*V>j=)6FbklC(Kx)Rm}XJ=YbO=_62+R%PfF$a`a)>2^-TN1av&oQKB>gDfq8 zSCVfG9y48RXk07J68K#Td^m*}Yx5r0AmS-4gah;%EE>8Zxu)>WRJZE)BeX z^jm1Oz876l+*oviSJJ#Kv~GTebuxLz8@~`YHt#ZZ84Q?JS3}418nx$+i7`_59Mt@o zy1zxAv3D#(oRg0(dCj;`MEvAkVvncq$0|$VPucQr-lSkj1g0m(y}Zds}$A z4cR}P!#!^;+MB_)?{1p^dcdq*TLH{z!(dT)$vyu%+dK$(g-owt?W0a8&do0mGrP;z z5UciOVWPLc$;f+zKx-skg#ORAe|=z*qBnt(HDqcQl6+kqiz$g#JfUMAQ>K{ z6JGv>jW2@*Q)g@hlblx#TPy1xo`?0Kb^pHMq8bSwSu~_eZ4vEdQ}b&KT4+QSVtF8- z?a@~)^JiDO=G}a(3PQ?Wlom?~3E5eF^$K!_g5ZYH^|va*e{K33iv1I>l4E&XywQ$cc#=EIelSca;b+wZlXm~DH#cHkX*Y|p9^T?=Q{Mu6a0L_{) zm?&50lf*`NOOtec6ye?aaFk4+H706dFE}S5-vo@dHJKo6PyI7D(npEMyX(l2tze{D z+Np?twbiT1vEu1PXN@jTV>{7Ot;XdB|C;JA9O+Q~?on#B zyI0wI)1%{dvx(;0OEJz9{t!Nw&%;5Pe>5~I8AIaJX7M8ze{DeZY!onQaMje9YC=~k}PjBW*9?3`?>eG-t1>=Tq~>7`tjk<00V^=gUN4P{d1oqj|EZTdOJy|`0p!r(<2tPLOK z^}tTjhUmb)zlfs5{wD5fOFbWQ^=_Xbi6bb!`@>8i2me%I0n#wTh1-rsQ?*syp`6B# z&Hj9S@0%RFdynmU)R7X8r?OoRj|JXDs}9S-FN|f=2$9ib&*6u{5q@d}jDOrN>h+u# z>h+vDULNqwwaipBak{8|@z-2^`_H~^8FEPlr1S8lMsgV!!sHffBe zo>NW#B!3*WxFH@bVZylR{?%ILWmRV_CJQ@(%e$}y8jvH#z6wI$n4^_#1EW33IF<7#MhxD&bnOy6q<9ua_5& zjq5*|&`CD75rj28@Z4|J;&^F8Au&cGVbP@LoB%M5b5sIg6MD@n>}3{CM(K*N3^s1V zF}3}?VE4Ri_b7X;(l$JY%@IRj-)@CNm1g12x;0$2b0a9Te)7+NDl2KiuBO~}4gD|A zwhbXTwSPX-Dyz!xEH(*oCjA34JzI7AZm1P4Hiw#d_6=|CZ@NM=AAJ{#j`m(J?xFeF z4r4buF)m_%qedKz@;eaKob;ho&U&tE`J2GLg(50b6643GV66vA9WpnD{aA*=j+=gt z>!0lVsre$oNX4Hwa>&$f^{T29e3~4cv zR{PfRCa?8=yJT1kJm~edtm<}_C_pa(nOyuC!o3HF_BlwGc8*`I55aG%?CoPaLif+} zq`+`M{2z9rCt=0eMQGS+&4neitUd=}ZtN)u1}iuk3my!d2!WAjcypw-JL{XO)%@DH zv7u$j%jNS;LDho5VKzAM?N$e-d#u$Cy!XmPbxf~KJrRt80L9B0?=%&%>S<9nTkgv7 z9&>l;)REw>jp_fQ>r24d>Ym1RF@h~&;MKc-RH^8y*KCP&Yd$eXJ*cv85m$s znIu;r_uF|`D)-zsT~UTlJPMAH?0@H&C#M)m!T9}nQzU*hP5zDCk^bp;4f8>~a9`-F zBe0M+BC~Pu67?RAq-KseBY>al(1KmM@K&3Tet9za_A?rwbz|#e>o3y7aFX>>&e6-p z=H|1NBKR*#;EYRRpKngzj6};O8Lze#y9bL|w)4m0}8$PNN6T z#mevg(q71_A#S-z41W6b36XkC`r;J}m#FI*&lxVaG0r@eU8-NKY7*^cgTL5Uf3hPe z8(B)%h0Wd?{b%3v+PzNJ7W)jdGiW~n$TKm~{ZxG5kq>ToB#t>wCI;Lh9F#>IaN&X8Hsq!r^s00r^c2)$_nhVB}|8h@?hU_6^VD zOCmaJ_n8VS7dgkl^EK=SVww*fWz~XcGI{%X&}s3*zQH8T=O0=1_8JNP*9-g>pkf+3 zQ`(#TW@p}>C;!6dFQ+}fc2zF#;K+k3Mk9_eB+)9b9qtbfFRHACTAE7ex9m!&0PH zjM>X4Xs4fRg?HDEi)dQqUbN2f5w$~%Ryq8qCpu=}pQ_4CDeM5BY~J(kT)nmYshh64 zv9vw(YRMLRu-Rd?6X{u9fhL$6JnPG_&CIZ;Uo%PEk#WjtdLt{rKfb+RA$`b`#h%)+4Iixn=bz!Pjx`Malc?d-3i*Z^3~@Jwu_DzXxQ^#1nHlj7 z#S83HR*Zo+8yYM2hOM(M#k&;oxZX}hwKZPDkQtATOGOKc(Z_}M_UZcfGu&_66UA2B zF2lf*<438B4Kj!WXzx%M;*T0@UXCtcHe|g#_*eZ&33Jw5QO(Gshu$q0;Tprk+>n)$@XsapW z>u7B6_=X*m1uH#b5fUgxI*G~Smd0{mCwpG`TD{$<0ux>IA$(h%feT3+!(j5&TP2Nlql^^HjH;To|^vL$EJ%gMa-paz;IS z=*96Jg^@@wZT}K|a_?{)nv~`cl1cNZA zimVNVJ(Y`>26Rm`a`l>d{WOngrG4!{TAF;GOfn`$Zwrs}#MN)qf16*tmJq)|O~_3A z)B^ZN}V+VZ41o8&O|&foR?A15iNckH}Rg3%70 z?NZ1t1fF)ib>DEjp_9>BtK^#LI?+!dM!FHsQ}dap2P1ei4C&vOa#JlRGxEvpc#=R2gz(;CL=2azw8df((Ul#%MD9LjK(A~{2BGa!-{%YnbW_fqx}}I z1v>pJ;_KBINAW#~w((-4b%hskIVkBfevvSEO@)c&y)IRXm9hoAmj}HByZaz3fDX7a zsoiwRvLk7ML*K(xp)G1CVQco95-wsc#1M*#-0h@0`rbESjUM~Wg$DX3R5!a<5s#$w zXhjCdl>>%S&$V3R!R{)fs-E)f)IvA*1Z-h-!NN9>Bl|%A!+ke={K6#amdo61d~2!B z7cJwDzDTim1h{T1>^mq^doyY$6nwon$Yyr11_13yZQM(>|5$a2-RHab>DC*35zdD? z4`sxhC4A<_3Ttg*gZIhJ6FB8Rcq0cRhl0$Wu*b?A5>B>`m6^(@n0NI+FWZMP$XlwG zd2hr&-8%&U+f=2|D{`(&F3;Xz4OlN0ex&75 za^Kphgx>@XrbU`&pDN0F+TC;bdTQ!Yhd_O8Lt>@D*~~LrC4+^0gqC-O7jG z;rAtiG&oR-P>jn6xhsszagelEo62uMl|RPC>CV>h=)u)zE1`SRkkiR#PgtK;SIwrH z9HGG?3S|e%pepo1=`83xzq3K^_b;k-=?q3{*gC~I?m^>CR+qRc6#Ob(%2po+H5VAm z3$8f%O865^-RFo$sky{#(DY_u6MMGAQhx1kd$MBg70=Mb)m+lOTuY8fzSo%Qx)5V_ ztz@rnTw=3cJ!%dK#Do+*RM^aaIOy6n(Iffxo|zFh!mGFNYd{L2!0fF?(#r;J9U!km za#dxdgu8|8L+a~$l>$?pd>2-NZ{$}wye;qbAioj1d?Rk+nI{fi9Qg8ftIp<}$GmRI zc#fgOLpQofy2b*2^cj`+ZFh#qmxPWy_b^9iZKlJBA=jQ9JEb_-CACJ;(()%~1%KG~ z)a*NyOTNR2(88jvT-JtTzS`WBzOWc^B>un+O-L)Od7#9}YDt_Sq0Zb{YWOk+4k z+Y`z#81Z2Jhst>_qw2B`ID1`aSQmFeHQ?jeS@z7~tYFi?QIgLsa`-Z*tX7tcu5yP~ zJL~)&+Z;2g4)l!rrXN5=V@xeU>Z$pSWBZMJaHlv)QdMeEPBFG!d6X3)otK;cjs+QN8$HdG#`gVrW^yTb?Wkzy13_TrYhm7YD@%+s+sFiIRDv#9@?V=*AK zsmlGB1yF-E&cuBDd`NDIHt)#(S|R19Eiu zIC;C;O<#AfA557`!Mw_ZO?hdR78PmhOgX-(Qn?;csOh0lJ%_o_OUKKD#ioll+IOXd6`5%jGX z?25^-#~=X@AJneeiM9&H)Wp<-m7!!IUPthAO3DN|!32!^K~h5x*t*5Fg?`YAs8@iT zF$F#woH$so(;JTQo_TX+WttYG>&Lv#7Ly?k^zc-Vr`KIry}}wNejk5?^sj03aI6zN zja{5*c>eOJbouSnYB1g;<%X3>C9LRrqe*?L+Gq~CR@ULI``v~GZIsYu$B)QoqH2Fv zS;+UEgmvzZkJsG5-ujHZqW=1LXBL!by)9D*H>Xb}@zPPH+18MVM_N5D8s9eN&F@s0 zs>~$HzdF#L9-Dioag%rA<)`oq3qjwG*T4eoGM*3}1=OM-p}To+r)sWRwtXm7zDLDp zZp78`GxDA%9s7q+?Q0f%0$eDasg-K?$QT+kTs2F|DjBsP|AYPa%tL{66PWkr1iMX~ zHQV5SG1hKGf!RL9CF6@(}PmUPtpa%DZG2iz4 zPWV?&qSgjC@izG8EZ$GI_FLHjaw@=pXZjvi56UdP0H+TM@g`7wQSGysBz?zX`)dRv zh3g`gQu8ftx`(AX`fk+^Q0G2yL`HFPhnKhhLN34kI?2`)h2%SW3WFtf4_J$A0h*w# zE`m&EoUhQR|8J^)#RFoLJhT$q*KsDC5??`#zkeS9wb-HKb2;TZ6edK!T1$;C4 z*Vo|G^~o8NJ{%>8I#qHy)hq%p@|*O#CR!5>P9CG;@}q8@$fb$kW;3H%%0ZcFcXV^> zf_^j;Rn8x-hF3qcTG13dAIp;Li4;DBcrBt&FlGH!eP{lNCuL~m@|bEXXTkRdzrb_X zAJYQ&%^YDaqhA`W`e5bkKjTV<{|Ny5OqSsg>-ejK|+R4ef@ z$6g}Lh@T6{me#3)4gD!h*_eOL3W z67FokE1V)iC{bun3HdzGM3jv|`#EKvmM=wst0PaIh<^~Qc|=g&9&INzeL0=8%#e9# z8!EahcQafE4QTtH8vCkVa*S+SNUdXEQ2Rg z=RdWReb60WE}XEyaa+oT670KBtWN~fJ~CKhm#*ZS2LUN#VRUkDfb_}qxfk)p>DT_gxxuQ4HZ#e z9MBd9T|S|-^wQj6TRJ-!;$G!%qh)tR6AId{woVP-d6-RZ2~ZT3>ecp+id|f|lGIZ+ z0M%0ECReRj)m$J+LAk9Fnsl-@VrHnKUf0BB@C4%(c=QQoN*TBT+cSg(V?m=d3SKU} zV3fvZXV{ebaihPW&pn%ih|W-RNu29TuaI!qhE`hBW^^}3=Fe29+Fx7Yyw_w_I_Ie^ ztk5G2$u_q4Adij0Ni{u3&?T&(lIDJ(l^m(^LUb}>tCK!TfY|o7_|8l8aB39szd2)! z%NY-vW-AasuQ%T7G#Ygxg+1Q>DA2+JO?$U|KNU!wlX4i`dvbDGb1H1_(ly1;61i+e z>=J{M{Q|RCE#;8^F`TJ}-1vxLYU+JB8DSK$yLez|Vc5SLbkqbO8Ax>hz<0iQo8lMR`VS`TXP4M$He$ueVfX;!mH3tm z5_`;H7<#k#=r8}9c&FAFAysRlT-rD(Q`KmQVx)DyPAyt;m(=KA0mhB}n}w{$$G9w% zT=lcu%hNbM9euA#uoXd#KdonQ?ups-@Y+4&cNKRlGR@H#E(|xMSCv5pbXeWFOx3{Z+gpK_G-L$jd?xY~P>0eC%sFqmnlAT?sjej0}t!fDe1n!W1kI0f@JTiUm&+) znOAP@x>OVrlqJ#{AEs{lrCv%GRVUoiQT08F{L9D%rx(jZ* zKPY2K#D~c<8uMUIX=nI` zESrj!TNJqxzwjj@A~lf=f*-Ett!!dE&1NzBX&k60oV5LsNqe1U6qq#R&0XKOyo)rV zpoQtIpC#}h!50~xSCrj zFc|xxg7Hy~ow-LZ`5d^rIShnUCyk=sqv=S))T!#vdq?t=2xN;xdr>KqUS+avDtn#X zpb9&oksM-`wi+|$ucL0OQnG_xT@%!1B%H)Pwk+@RH^(QukQCto?Db!d)hh0~f^=AS z*fCt@v~xzED2vcBQZp%%grYn^J>P;jBDoEjAvwwY4k)*^3MJp3~Vr8aOtDE**$+2+hW+g}u*# zu6YBg78b5dScEpfuECO0s0L~&%&E}GX}X&#xuY=^2C8{OfbT=_Ey|O(UY`WdUsA=| zDqj2!S^>3{pHdGky6CoRQ9{dV%wpZtdhKKfYm61zn(1$##o5axE|QG)62fmLfy7&4H!_YbCZkBL>gl+9N;=TP9MJH8I&QUwegPz zr9;*FSD7bhwX#B~X`yUlUP*2!Kmo(}n#!?Cb%IW=UZCSo)J)%rl6Ze1jL_^vUTU`_c?IDce0qRhwiT!QdIV0IHmyjy8sw{AdsuLjWC#J)7{C z9p^wNgczU%HORx1yVyD0Lj`YzyEd^AcJ3xZclaw(?pGk5hX;239W5UIc^~<`Z+7`{ z)fK-9nvYvecJn~cYwY*3qbilxl=rhjX62t{2gr0a^n#wPx^ufDAv!d?K+3-L!5w?w zM3o18FqyX_Q+k*)$lEUV(2wY!y<&|UqWwQpe?yVzxs2ugSU z;ms+~58pXDQRpJ;mQc03aKvv!kI=UA;sB}WNW^x)GI8*tLxh52Sp42J)@UdK$&RSs z;8M&O8#g*_q-jj-x2&>(?Iz2%t%Un;hDF=A{Ic2EY8KxCyg%v`_GZrur?f-ebfFP|A*<5dZuLI&*QCXwR!&_**5?;cdssi4r4)jzX!{J3-EJ}j zZmfr}G-F*kcJuDs983txPQ^xx_zGTI=N);^tg1bIHL+Mv?a4M@g1`O0%^Dv=P<^_ z83`!K>~BXrf3lJcF59xC5I%kHl>|sxQ6)ZgWq{{s#3Fdoq3OkGUIeD~`jhyJg z6lLA6r|d-QKoe ze?wP~h=*+p)~fzn!+|cCuy^Eg^6^qY{a7}B5V*DBRDSAZN3FOYg^yI8o3mr5F}4++ zi%J^1&6PDb7nL#O(7(e`D~)750Gm8$ge63NBeahstWHpy1gB_skFvKz5@gg3L#2N8 zA>6OsKw1-WcP_IxHrDG~o9lne81(di$e2aU#of9}DRQn}_{02INYev-i&juqZ>(?{|&+@gQ~SMT$okb4zo@0^8#z=7Qkz1TA! zfCt3F7BsPKG;2ZOe0MhXDXO@L@anZ0Z$$PwV~?mbZsif`>%qoqVW5ZkuhoBPxzWRIFw%eBC2G3z` zS1@MhJsU=kU+<5o+*F-Dg19a~m6mF~JKr`pxOOyLUv6UYV)ps~!mh!BCva&faIr=& z;vS)rl4Q}l|LaFD_ILOW<_d^OL6wHSWgM}@Q-HBlC~Er+smV*?lxWIAK~meJE4h2Q zh|L$PJ4RUCQ4qn2TzV9`A)Js6FUjG|UZTQRPy@M|KJk+4n{O52%e@=9gs_Kt{jNB! zkPq6G1a9w|Wo$3?FBZc%$sPe!O$^)Y%@l==$|JJF*rV~Y5$=K9bQzLWr%=ld{#3H$ z7d=&twT`FI#cxsmYe!Q-tW>B)YQ)lMK_f5fRs)wOW83slR>Sx`daE%i3=@8W*SQnv zLi0STdEbRBuDF#JF&fQbpDZev$YaTIYDvr-g^i*kd!PBx>vX%x_{s*>6Qf~Y`wbv+ z+EcQk84I=at;1<7<3lKzh0%e{Plw?1$gW`G{mS3@& ztWn_@irV?9IFu^C>a;ZxU0eG)ffJ$ z7&c?!*E^qE7@HKuC)2!jB4n6mLjy#s##w zk41a5&Rah>sgXgEhS6z^=R_lkLKT|GSqo&6ZKaojisc;)`jy2%-7*Vlq7ZA zbvW6uz342sad@!1`?YRNtdgR7ft7ZhqN4hj{QPr*{TW5=`RQU}V&;v+WTrhS@TXc^ z$kMFs?iu0>1LH;r6a1EtMDd97l00i(p%`?2_EI(wV*7TEex81D9+)vGIv}7`nn)jc zKeds&Nocu9ET8l?q?}W}hT;7oypn?2)g`y|K3zuUj1_T$EF<_nLhgOU3l@^N<_ z-{WQ*sXh8~1V*4{>CO7elajwIC7RYtm955Cw{A@ZV5R)9xe&ZYFXpEUxNEod9WeiSCF$j#b@v zY$T%|a5GX)ginV9y>btQjB(U9x^`;3m1o$wynpfh_I|Nn@Z98aQ`kEiTXHOvmuGBb z3+ckHap7vmUsGaXZui0@xTO0GcrdcX(5w_+G-~yoH$q#2+VI2?-)6CXrq`ER(B7pPhK#`5+pFdlk3N>rio(-)@~n1_hz3TPs46?erw(XDd`qv|!-n z1ePo7(=bWx#QsgZ+KF08$M34JV?6@_?mR+1Yd-v9fI%=96CSF&-HE`3ZVCT^$1-^e z<%d{jin$+Uv+JdTTHC_N#ctSQ0*9>)-B>3qY(-3hJ|4<7y2hH9EK$i=5aM^e2ghHc8I}bZh;$4Dnu?G?dg!pcTcLod6t8;VeJHs>gc0SgI zdt@a9aemuAJUq(p8*PpE^zL{*Vr=i>Q4Lueb#YIb`Oa}SBoa(awPLji3g)HlvD3JL)chCVh z-a)DE<>WN3emHK+`x+}a3-z$7RuGH;nHHC_ zRv<%iJjcG}a&M-iXK5#XyTt^)%eC!{QK8$R!aw_#?rhrmSJL)#VYbO=k1`s(qDdNL zRvobpAC4NzdS7Ngbio}j!*tzqKw5c{w?%hYov|e$s{iE`|8*EC`12%|sBrH?pyu1n ziIa}fis1~ikrA`wQ;M=uC(6BG3Q3ezVM*D?BL)p!+JPx##w?v8DeX^pgk;F8K@k&OHdfQ8o2P1PI#c7#Yjzv*LlB zf`Er}wLCnQZFDuwZu6Hko(l)?c9gU*>#ElhjV= z84OOnOZam6F?9vo;sQ>?D^K(}5hg}eG&r`@tq;vPB?YKN%H3h{&?$OFa>=#XE!M>q^ukV}# zT-?7N?QZcwDwh(Mv<+Fy)X;mZ(_)1~g>!^wuIjSdUzL|8M?b{2I8YDiz2X~ zXu}Y+eTL4~DV~A1#H}Q|0FCD+bK|yJ#VmFm-_pL&umAos>eVVWD4~D1AGq?b-xi`Yh)bK1u&7DD)`&Jx#9rKBdQnF*_ z9n~B=!2PEmd*cT-^W-+aPCO=zf18wCKY2**O7oa>Wm%D{kcW;?-9BkrP^G@+xz0#lpP)Uc!YJKEYHGF9q^r-=vhNY#un9GzL0gMu zQ<&0(>hc3q0Tr}A#d-)Qg5M^6t6Rr^27QCZt$(f<F!om%+b9x>Z4k-@ju4zWS}rf0Qh;(~96cmivv)|JZIzg)Zd7nCg4? z06c-*JXQ&1ybXn@#ioi2@EQ;SZ3%v@l*$}N8-o;FGaU%ZBy^gGdWl51Oww3n)w2s< zu~#AQ1UYkrqY3ZNiKovQvK(PQ>R62+Kb-WdU7;RKu$QXm7I^b!i~CV+HmD7N_1<1J zMt$UoOsIL<6<22eo9TJ(eSoyCc7D9oFWZuJ%gq;@$n6&Wr5E2M?=7|ap(5UByc;|4 zMk8&7DQ8fkq2k}c%F+zIDgV1mxtD7A{ti7`!#B*{yR>=x>CuaujtDa9_pRLfA2L~~ zzi)jv7PT18`B%ID*7);c9pCzVf9?lb2>isn|_>O^AgpM_$bTUG4wZRew@_uD$L zs!MxgUwtKKu*?o6d*1|Pe`ca~5|Z~nk^bMlZfpHA8P^0A!tVq(DPJwU*>34J<5>Q& ze}8>&no@WZ`nY(f;CLVQY(;s)1Zej7Y<)&S4nEyt!tU!V%~1MU=1$CTtNh)}*bhXP zW^)b#4)l*_4 zh9!~-(hEF)M9G4-rvK2~RO@|#Vl)pV*j|7i^S*q}4KQCEPF}MTa|#8o>jlR*?OyFu z)sgU#`J@*}@u%MQ=+1oI8*cBZTdt%{x_U-reBMVBCOlv;U;Nd#6=o~?w=7k3ttGit z->w~dHb7w|E95;`QB4_mDxuEAQ{hi&;o13^`uNb(Y@jTBtQcoWM2JTfk&3n;aVb0I zS720cX_d*xi8U79my0uWllza%5(ItxUn}zlQj}WxMT+O)rBOYk=AE46gf}!n{PyY@ z7Q!6L=Ww=@67flWQe~f2oBqnjrpLB&p0EN&{>7K z@JGNlj(il5dHm`uH#H!m$>Xz9K3?~Yhx??U|7qo;l#?2r#rbgyXx(XJc7`qj;RfKf zv4eX!==eL`9K&B23ZXo7>kInJ>?+`K`=nw;#r&K3k{=L(b80R`f3wDOn9$dh9?T*F zw@pQ~A>dQe#3z%GqeA{?Rih&*qB@kx`V)8Tvw;U~d2>UV;{RWi{1-s;wEQl8hj*b> zKygDUD8PU(mI;ClEcKHJ`}?qMl>55Pp2VEvp-oBS8+m{(w0r36`BtMa@Z8Q@ca#g|;3 za?By7JaveEYA15Xklj+&NchfMIIPlw9&tI-4~AbUF(ieRJjRMVq5O=v0lVbp-?U3;S7*#FN zg_sAvDbv*!w=}o<%p#Xo&YjhqQ!~dUGcRChT|p53ow+3NYv2m#=6i~>qgoX}Nv?!h zB(eQR(eQO-{lmjNvj+*aZF|*^23zrj%pVmJ%eCuHVGRNW<*U{#?{FCcFvUtgQAvq2 zu{kp*@p;9Tm?w@Y393ihdaN{@TlCXKKop#5HcY3?mqc2>XH7Fgy)=tdC)}Pm?U0K- zCU*UgkLLE#b$8Pn^`A1HzAd*?u0LNgTX;A4li~>FWym2AG{Cv;5}?Z+e8v0ba-$A( z%5S!5t+q@BzOSUBX{k@xA5OcMjZmH=PJR?VjEnlV9dbozVFap%)Y(f(0xUk&E@lnTEn zzZ8f4=%dNIir3beW>#9nZF3jLgN;3I;aG2+Qenu7)8&Gf`LoWWqSG%Z>b7_=w%KsC z_v@^{+Chq<)3*B~x{Ks_Lxq!-^4kpCfaH*`uFHZ|na zUy?mukLub|DsX4q94cfauU{Ot^ROTbh?bQ4D8yyq?t$9^?A+SkX+TKd|G~DnwHY6Z z(xx!BtOX7dLHDF@Puf0*wYW-2OO?|e zuUwE(TndV7nj;wK(pt14e3oka-tFodp`rOX#v>R1>3pI)Zr9)OOAQn z40NI^<=E(cw)4O7xZf6PZeuJt2}YNKZ!`yX`h;AH&~w}St<(LlZNWh^Dfi?D{$bV3 zyQR;)6h|;?SIfZF4eR5_DiW&Es&-QnS(q2=u8@pEerC*E*e!*i@xOdU@5x#ld|S2F zv;k)TlCGx)rZ|6xy&DBbp|NoL7Se__X(e+f()8H)_cp!&mkcOII_(S@b9Wi~fL46q z^#1~adm)eGM~N!Xd`1LQ*6rhNT(;e#)^&s8izm>wat=E2l)ftd^5XQTE)f2O9pLHA zr%m?dE$RBE&Z7eK55G{;@rq}o(Gcrva&Du!u6XY{Zbm(wQgwHM?^)nLawA^|#S+E9DjObda( zTBzQW<6}eORJAx-?F&*6pbV@^ws>wKG%ophz+d1*NuE#0`~*|zPq>LJGY9abLJ`uR z#3=>AN5PM}%#f;L+ATT~-e&A^ypzd0Jo?3Q^J;Qyv_-;k<@2=i+upGGU^Q693eJov zM!_P-&cYNDT1<{lR5a+V1%ZK2`}L<+cEXuAo`K|B#8J?q4z^~WS&w`%3EL}_WDeBGf~FZ(ua)dnH;=0|Xm`rzoat|P|Agpgb2Q$LS6-BY6ELBn)ry zXiC@u4s8wotV*&drH{v?EblmVHz6@5{6~p7lBGe*|eG3bI``K0u6*nG;0HKeLH3)s_gtW(I?UlzEMy zqXjlOP6tr%7l81Cbt$Lq1;@9H4Y_A|&szMk7G#lfb5CeuGdlLQg9Nth-&zATs5 zb+>Wrtp?QvD@Xe*g93{EZX~UvPgg-TzB_$~`&&Gio^aG`ZMM%aoqO1_GUuN$KdxZX zt-SJx%El6-z@}bVu=wp_iG<^nFw|P|x3gYZb)pbROy2Uka1K0hcT zH;Eo!4VaS>Gf>&)n(?Bq=xc|bIcrPpVjcKTl$6eX}9y%!| zoKorsw$MuXUo@`@d*8_mt#5h^m*P``FJz+st@t*WpbBH+w7 ze!b{@KvGCo$#ST3E;Gd8kGkT3Tv*){;4!#Ox?8-kpe;P-X+_N<0ry@{AN*<5Ue9Vt zNy9UcaxK)O^Q-*JNskS%{a{R3wp(9zP%?Z`WhKhOHCtRvYMDiAh?#5fh#!Y<%{>B% z?}Olm1&mocO|<4J()%ZWq=knX4!Sz)S6$=EC#u1uzt7a(be9YeWYA<;X5&^k#hv2! z(gMUBfJTyF^DUY&#rAsA3eZ4!tRXOMBEe3i6iZNi+{C=Z$MwjO<2Qx{rtBe_jAPg%-DCP zmQ506VCA1D6VgL5*4b7OgO;If2)_V@tw~zzZmC_MtfUc`fKYa)`Dv z5jc_qm=YcQvzie;+w1Da|1M-)1=1qY__$m3%Dl%90I&V9YOtkp+P#YG>kLwHx93gR zXIhEgY;(;Kz#&iYf=ZgwK?RE^bM93R8j?is_P$TCiP=`6V%fMxXji`Eh3yc)OV#UA z;(Z>g!TeYFd_OlUo3S2`^oK0p_~V=J=;3)hE)-)&ZNzUHoFkqW=ATovNJ{F@0C!a7 zw7bC6RJYCLDh2D5J3AJ|q<^S+mw;OhyCqLq-EL}@6u*S)?0}~OJlDYX*CnMd;BiH1 zo(R;gZ0NF?JIA1%`VK2a7!+Xapu=$g2k)V%z!T~Q?Gta#7ex2qtQ{J9<_zk}{2RY- z@|T?U+U^F3d1gK#pZ>)t)>diQLR?!As|A(l{&*MdN*Po^fzKp5dE6wV*G(L!47i_w z6OuqxI6;cWCLuF45eA&CafHoj5*YvoH=GOMnTtJ(^=EyvY{n@SOs#9!HyLodehJrb zhY&ymD>ZDto;HUG*T|F?>I6*H^XFFf1aKa}*GB^ufkksfIF&+XZ;+`wP5C;7J&=45@CsYnXC3{M!^utF*xXtO4x1A zFL@Pf-n&kvBk&2sjrRqO(j+kq#tSSO>2H;$#A^cn*;s0Etk3#MisTbLyA ztWRko#=Cs<(TKc*csTrprDsR)X1p=1urz5*zDlXk&KLHMyL7){85R6P^-%U($ISP` z*$5A;TjE%K7C?~rjvH$Hhiym4LM-)Ro>KkYdcz*Eh+ZBK*Q^s%-YNAtYe|{Dh2ntF zN>KFUb)GL3i6VH4ahJoo62{Rx-13?aFw7fWuwmpM0O2ZyWWQb``Kw~YfJ@I;jpc|E z;t%rxhYX++GBR3OhmplM%VC`j<#W3dyn+xi9*7o4Y)Yfd~%-D~W z`h=Vbyi7kRWOY&We?s-Ib9RBaT3F_BTk)L+Y|Xj1eP{*nRXnfJa9^2$N(HCI1ju%=ff$CJ`0tM+k0?oV*sj#!hf&j9pTOV?ZThM3Ah_eQ%XXzj)vj(P4)0uQ z7=6kt5IqUsM|FN>J$EKl*Ht~xS#PPdUPwF&hncAMUWfLPj}v@%v?gKb z0`a7{_%kpF?3y*42qM1_2h{*d)A~9H zMIqV`nyxpSq>VN>$E|-Okw#2ybgb-1A2LIr+3DY1)(?sJ-)od`$yxCAHQ0PqYA&qZ z>J}R^m4K8hyGmDkmBZwsX`LlB9^SMgd8F>7^ijEz?Ilq+hWSEG;s1VP?v;g8Q^G0? z4SU>y0_lQ`0%VbJB3S=lo= zgrp=IPHkl*A~*1bChJYV`*)~*5mnNunjo!{45oSVZ=r=K1^gO(b+N%VK5eYkCPA4J zX1>KK`9DIkqis=(gv)1TSU;;A+sT}W7+yI0{kfAzMP=XXkzYi8;{n4KP3zn}DhkxH z+(;Z?W%y(p>ZvU?McJ?QoLWqyBo2|03(ux}C^9A&UK2f3;NFX;XZ#szKgB{%M=!kx zo#{`SZU3`&wQ(x%W22{4;MSYzDK)o z(Tksn?mzbyhJNRDCX+9?(m2}I^fjIvn=F&0F*l%HPY4eMj~Fltp+_ezV$Xya7iu(@ ziFW(*UpBUTcJ9YJ`jW;U^p8q4rZ}iu|Gm?XY zsHCWQFsh9NFv~R^X)M)>y_RLyX5Mz{xr=9Ac5_%3Cb*Z`@tmF|G5blc`p-J}(J+CT zlyk!c;ra1zPnzAU_joT;h-l+4PRX^KQV>r{Ei~Ow^xP*4yH(t(s-p9#ao4iEV)MK5 z`BPSu+KT;cv-83NvJX`(uaVy?rYbni1X-Y>W??#PSAFvHKjAPEYev97Avs@EjJX%Z zFXA8QdGp+~Nxm^)Xu_Oqe|&gMc!_q_J52Hb8mT)KG>kH1bRuRdcju7guo!hy?vfuGjUvp0DTY zx~_%SaoCCV7tTIE9P>ws$?q{&9dH~Me!s6t%$w)2ppdDPTUY)%LX_0>mu&spgTALb zC)E=weD}EXI@B8u+Iib6*s0{q+Yj;3ZhPWdW@TP@Ktyy)0kUm{^Ze)A!v4edXFZeZ zmw$X?gn>Th{?u$ZMdm(>K;HE$!Jg6-Hy}Q%x3wxMBeXjXCUy1F@4ucu#XfdUyUkv* zVuh0@fetuk%M=}-IRK^)q0$SB4}=|1{JhNW{P4Le`qFc*3~^t&G&ZUX`=1UFaf0g} z!$W49-Nv^JCffYUu1f|@y9|$2SA1_hZCp?!w)M?UNV>Q8Vdv^M4c`e(gO>+L-1HEV zOQ{=R>JO91zDKr$D>ZlEGjQ3HHA_jFBwFYgT;^w;E%j)O_;UD`G=?=o{M_v;J$xvJTfMO&-kt7CDqs0n;$ zY`=>7*Xm!BaKdP1`K5`t5uXfifXzRFf}L65sIy(CAWo;Zoxi|o*|)4VVIr)|pB9#f zcpcF6)avyX>nr~-$2JS%N>bu|Wp2R#=#Am@V~K{U>WZ+eyhofZ(0^0L+CqM5r}0!R zDRE&$d;Lf5vO>kk>7Pr(sfj#jjyZ{#M~s(#w|-ocFtOJ>fF5pwC`nFFf4yl5!d*T5 zVJiW5+Mo;^*`cr5eLP(REaCE+gMQtDndyh;h#CHBaV9g{OW?n)M{wiMpV5$WU6n(J z_xxE~gt~Nud-s$0j?Yu9XvAOK7gBE@ORx|RRf>N3dpV|-C!}p%v4%e<;?AG@^tWB$ zI{Vn~n>!w~p5leq!rjtIe*}+mSC%UM{>HxJ=Tsp#koJg~V`_7oWjaOs*3bSD{11k7 z#iq4>2>j8y3=r_l{%oh-i^JB*Mh+8!tsv9@c)K$8FkP%rSvXX>Jv4d|M&*Qx6DFoR zl`Z*MZrVkvpFd6euZrV;eU3mb_+SjVKO@ib{@mAJ#u!Q$z&~0z5Vl-pEq|ZWmcGTh zxciOQ{XUkgUi;WhM*Y>;&gR(P9B`Q<^utPu$#mZ9>R-b;?@~xom~G<#E^=M&e`Qlk zPPiUDS8?7e1uZdvmXacQ? zcZ&jcv5N94X&x>Fo(iK;~pK~q$Wn_GBt0lTiPMU*IAOt7WHIYB_+GU^_@@$mbqN9S6how#o)=j?tn z00+@OH6cSnW0&Y?H4p#GYT7TfwEPyEnBVtqJog%n3O{`I_&ID0Vz>%NqZ1*vDQA?* z$E-&j+K$w-ei92F>&ronPku9AdHN4_pX6GE#>RLgR$~84AiBghZ|@$XKjKqrb`jAV zxs4YH8+ZPb{qkMKC!)!I7B9rl#7&;V&=qyGu%C)?9- z!Uo9g7N@KX<$J|Ow8gKttkm+XbGyI1{gMz;bTG)MudlDV>+<)O0YaOs?&xy%(7=<^ z&h*McW8gUx&6=__SbBBM;qYwI+)8V9jup1pVJkzEKStgE_H~f86 zGFI{UM)RInKc~HKMAC@pj^x-@)3-6Y)fSqd@rN3X$KM)HaljAh+My>X#twVM56;=J8m_)=-2RFEn=f?So(+oJ z5K+?7tevX1!^iE;i6c{C-BXrc7c2hk8E`(KRW`=;G*%7dBEv>fg?#p@i~sDl6#YqDcz(OGiqPGyk%bZSAG1RT=PP9*ZhN1yWt5xd*4An zOxd2dH;ii^`4g2-5q^7S``Gw%DQR$>_rp(1y|rZ7igS4&f{A;c4eYPVD{J80<_NOP zI=@i%z>_=7!T$OA=Y^llS%C&NYAP&L2xokH${pHZ+LASx*9w&Kezdi{iOa{}t>lp< z#HA9)@f_0(4s@&im*XjS{;!7ge|2%(SpMOC`KkR?j?=wv8S2&ZK9*gfwFpwRd6i^) zikE0F--j)To^jH7jcE$F`g2I$^e^M#xfuoeceF*OFs5hP!)Q3*v8-}SJ?rN8PXNo| zfxe9;dOLqeh6{sVJDgk7Xyud}P$vWZuZI8og_aUHyLqjLc~x-jcz4;o)VzPhFP_I+ z-;iB`JA`kzu;OgX+p|C)4=j=96MCWC_r;Ta7v6DkWpB0dYr;{0?X3K-lXma-`;pWP z3cdPQ4;{mm2kk@}Lw}U(CnMzfxZ@a`o79RHuIzHWqs@P^K7~I+cUKu|%%087-z6)70jl5rG723@Rvg{q zZ!~{luS+qyEMfBLRsC0*^ZhLP31#G5ZTL$T1g`nF-RP^PEs&u^7}?Jq^O-HRF8b~O zkfJZWmi>DS_N=ypG;;3t3nln{7oF{x6vrNkK9I31A>)_h{BBwMM~n7(GA(*4rLDY}Gc066YJG+KKknbh3TqsZf1{75CG)dRk<9hAblHiw^66 zPv1mh3HMi z$-CsM!Qg~ZkE)c2j@)v(Brz+S>JR)+SZd)-kOMvxy_=Wk(G%!E+;ZsG*#ySm8(BWi zyb4Y#k4Ru4b*j`O&r{4&YEIY0r*Jp9JNS5S+?n2)p1<b z!Eju_r1ezFy+fmXgEz|dx}plJJsYD?17G2!n|;{$xyh$@g#pDC1$hL8(Ekq;bRz6q zY#*^p1uG~~*Y7*0dFpe`JB|BOek5^+P;y3!3QO4e+pqUELJe&@sRB(*$7Nc1SrVKb zx6bxlKh3%Gr`Z?Da0GI7A#r)RY9_j9Pn-0cwj4(0g*ucpMA!)QwKx%_Bt8nLBF!K$ zUvTX67ZuN=l?9t*KJR+*kiTboPNwK&IyLo4orJL$kQ5z%|6`ka*X$ks7@ZC)p^g14 zd?}lRucYw2Bu*W$U;4Kyx}|PwfHwMXE#0X3$E@UvH(aaJ^6xm~=Ha6C1ukmuxpPn~ zIN>DZ8ZFD%=zL_IOZ=4d-+epzt^BSlB4py@&TDzTKQ{xQT-R&Aj2Y7zo{?V2?6{(X?~Fu+ z{=^j9r)>hmU4L&1U(>N#QIR#Q{5x+S3O`(d60`DZsS<0HnEk-JWO%^*)jK$7_f_9W zQ}1NLnyccB+@J$I89X85?%sd=@*N`U{(rbzH*V>fuz1e z?1+M;-4s+2Se5-4##P#A&lxW9_I4|yTugd#fg>A7rHAlEi0(55kAirSgrbAz0LUiW8=vu$8~P74@ckz*4%FEmWHgrj$X6MOYFE-?%%fh$>x|NKj)KG zGV``fbK2TzyRfoK4vp$r&>}s}>uQh^akxDD`}Y4?S9s(P-KeASfBkXG%>Vs?_1Dwx zx&F3n+m7FF7{vYl=Yt*FQ4hu*?mqg*Lzny;_w#-WSg#Yli%i81$yyB5{l02{o4D6T zHgv17a#SRVw(FamRISSW+a|2_wN=6VG;_UVU6@~x?#lsSC;bMq7mb})sg28lpTv!F z0SCElsCJh~PhD8UOt8d-F+%1&8ud3Nr7y}Temq8^9E;WK&P&)Pm3J z8^7l|y4`53;?Y9mJv`&yc`aJJf`5PfTZ39vJvEm#@P4>MO-JI?e3b}zQ0hmV^_@@F zty6s*b=D(Zj!xob(^*SLDq7GT>U|csicqkKxp35Dd%NE_d8~zgb4+pxN3ULnbQ<3* zWw1Q%#LYjlp^v@RISJ_|C95t+B8#vg;3_12>WcPIVJyEoQXMzi{Z;$-X=uhU4x#ZX z%su?HQE)#|Z>3saI-l_S%8X{g;ppYuafgKsMff2wN7PY(arcaqwUgb_!j}Zc1c@YO zaJgX4S?8i9M#-}4eH$?QP5T6JwximYzhQ}g3r1ZD`b~Q+^hK52e3hf@@BD44sm$&e zlN${1)pzp-3tH$lGKa2?Ip4c084k+J!}k7MZ^?L2_?AZtPJ5N_LXR;t3CQ{@EN`xy zHMIt^5luf^*ibV+!S0LfgUGpjx}&XQfJATM`kE0*i9p47z(?t)@20bT9*OhrXhl63 z)NQ2iJYBj=cIV|lcPPFf-yuSo81t>DZCd5^bG<%ex+qm4P8vZeHp~zHOiP=jXMi_2 z&u9Yf3daPy=mW1M+(L7b^ayT8L*AFbE_ZcqK@wg!;IPc^;}l8ixp@)YN46#DL;k4p zU45%B2+qqUW|MSfvJ^h~Q<1>RL2oWJU0bfA`ndJ$c8i6OvDi9%!>k0FZ zl6SX>oi|Q=vR26FitJv_JYm?BzifMr+Dm3#+%C{GdCb5V;*?2cvQnw=u;e!sOkz35 zaB1@sA^sVra}PWl7!#JXjq@$S>FUYeeHo{FdP)4;oV2Wb22SmW-C!E8I69++Lznr! ztNwJJ9k*7Dw{TXA5f*FG?FCM$Sd_awu~<6PFMQ3~+=AtiZGxVPMkM;Mg`0Y}WQe%> zXmgr-VDtQJB}ri&K);jRZ!GJDa@xq|Hc3O(>yu}#cg*$dvl|jr{IvZs1q?NDfOFN@ zL%^g)wW%3nJi)cT4n46xAYsB{?k!{b+2p7O(d(>P&Z)Qdbl#$`&kz;bDR#|eSuzV| z8w=tud=if62GH)Mr7>nR{Bfp}`C<{3F*MZjG$$wLzjK?%{`+L|e42p6+fL6iegJcQ z=XDk~`k9idP|BYb7$PGV?)V=?v5<@-2xK;k_}0chiB>;9dMD=vg_xSs2&r0?QAy&& zs%!Y+E@8NkMv1~iI75#c`}C-;3s&YONsznOD&9AEVuydm^%mFLB~7|i?1yM%8kwy3 zPL8EpnZ8id9Mbz~gPg8VWjW1XnHkOk9xu~J!zhO1Gzul&4F!%HK05p-9l$g<2>O`C zp1`y{Ev%21QQ-D3=Zlrdg(8TLA~cm5k$MKP_ND6DVE;9_p(%c&ZJBp&3_d&4EW2}d zZtYCijK+BqB1%y+=Cw)(XHCJ3G_Gf=q_-%`$v!uE9^ESi-k4{>cgUF#ot;y(@4I%svP&q=Sy5o^a|XMI6Qc~LXl;q=W^ z3#(MZ=S3plat<6fF^GrzJhdy>;|(1#1p1{O3C+8~Fi+^LD~(}%XwY#QKbv@P`^(3Z z0^wAbV#qW3u+!|2CqrXbidIZi(uQl7+4n`|WrOym=v zEt9rwcN&#s@7k`yNxg>X#-PVMwuQ!H)@S}nLakl#N2Fe;WlJ?+zN{{BL4;Z2d#|Ye z0~2FsGduBq*st|<1>nIC`*Q!VNpsA`Y9O@13p=;tWSL^Q=`5c+v)weVyk4guUKBld zlT)j2nka*z&$1|4BljoTZ-~&+d=-oh?EF(oNlsootas$=rhG- zInPEps^O*?CHV=%f)!jJQDeYdlw;y#1m^m#{Ip#Nr0ChMfO`h{3G3t-xo+L00ey6< zKL&fJq#)@q&?&(%1L$;EhLJ1fcgAdA2-NiH1lL-l{&*W#%T7Z0N`TVKc$shL&3?N)1#^k+u zx&9nhMF|lVnobRnDYQFoibo1R;hed`at37zkWKaPaxyNM86wn^l4eAaXtV)iywvma z1^U>Nxbe}z+PMapf+d_Wui)>`0vhP+C(rkDn3bMMJLwwCTxlE!BS6W?XedTa%%P}B zu3bEA<3^3S%Xd}lx-V}Z=d}*a^Z(3o zq1!avA8z;NF~n)wo2F(zPu{UiKHxOlZ%h`H^Uelz3>Peb#;(DCovq36DsPQvROP+kj{r~=ZXIH@;w-l=}!{Z z0Zv*6OFoY?nvlH3|rv${{ zEIY%|biT)Q##~V{-^*bpPdm>E4F+aUy3TwXPwH}>HP?POs^dJPCy?h21@hxfDF3mS zd%KR5(aZ-i0m~!q06zO~$LIMMrk0}yFD_pQ)jw8KSUTW8d@`ImHn+fEv~KQTvFNlX z#8(a$pKnNMGcFSRE3xw`?I!*mE(=41_qp(a8D;0ONPpIW&v|Z%dXcy5& z=XsQ~LBRA6!ZFu+rt_Rsu|{~nNxhsSthb|&y4KFmTJova<$`uxqM#(UK#_26F3`p~SsCRxJ@Qs@eQn}ax?Gdw=BOO03@zFLbd2i_nk2=`F+yWc=h^7Q z(b=`Bc2j<)$xcZ#yOJFJ=SD($G4#kg8Ogj!eopWmZ5-K~8T_ndCPspZ2)Lzo9H2J{ zoXX|h03(_8gb;o&prG#4!tOdIk)Zr&T-0v~P-nXaPt+eVcXC2qjeoWdLGUjuv?T~6 zxu>JT)p4GWs!KQ3v@=Eb0w(`VRI6v&;)aT{dItsu{1}5bb=IEV))SJSbeJwjCk4#R zGSt?JiVUn|h{DjfNGW5k8=qBINp^Hq=E)f+x7=v!e@bx0#|TNA7xo57;#sY$`Rq!P z+oZTbm`H~Usw>^?%j;l$>`uT|`Uw9zrZknT-8w@=B&-~nVc;Lv!`(DTuIrAW>oWkF2B6ZEdOu zbs;Kaw5`PprlO7C>yyWy;#k3^!`n8BAi_> zssI}wC)}LG{x-@@%8Ox~zwJMeE&D1QQ$#h{3Q$uQ7PS!x83soR=jJZ~h0OhKmnYr< zn!9H%L1lE@>*|Ka0!?^p4gIYF`w|t z%HYIqx!-tsC+N4@ zChWSbIgT5&3o+ca^&*!VhfO8{7-bd5@lz_AV7z0Mc;}znXi8Rxtvri0P_4)m*s}Jc=A1>5<8E)eFlwtdZVtw zIcBPczH33NO9H6Du(YyLPuuM(QJU4`&T^z%qg8pzMNRb;++VaxedweO^CGDNHq#z3 zTk+qyL1z=D*gt(z88Ln>!q`MKnlul-OQpIg2Ad1x#s?A8n2p*)=kfo#MBl5oxh_=! zO`bpkx|rhgeX~<;hL{t9-R<)1<<#J{VPb?ZGPQEYXCmpldb&D%)55MXmS&ot?Yvn; znIO5HV6KyIw)bmk7o6kKkxciy>oZUR7f-tGR}3O>&a)+Rjd4m=s(cPk*E_kVPWWN} z5YmB8p>)h6L<0l12qaRZQtd<_GRc%nD!HAa`_m)ExVPsqKeM@}laTd;o(6 zxXBWU;*Q^QwHJgfWQ6ST}R|kDBpb*$8i(p zLf`^7U1Nq0RkT@YZ{Cqsg6Kw8D=`wmS>6o>XbzHko5%O&xzwP1Z42IdGe>P-revZ3 zl#%OQ6%Z2Z@0Q`HWP~O>u%qf&-3H}dR1Q++h!;&8Ssg?0a@4dTSUNPTp`mZ4iJl3n zg_NjajE@P9*e=4vk%dTM3HQn!!@^hMtMVckZ-U>*o2z~xE*6j{4Ve3(#-l~6#`?9d z4Ka&iR9nNT$)GD#!23Mt_gOmVMy^`{w{?4q=$XJJ5w93HGFGdZIFyi2I?aURc7V&k zRN$igHrav%zU8peg*h3j`yg}M@y?%zEOgE?i#q@jQqI$xwEl~Y*frI(>u4OH(?p!- zQbCc}Aq8zRjIrwKeC#z|-Rs6RlUV3`wcW)Y&f! zYtODR;X?tKLTQnzOHoMyY%?!;8=Tggx#w;|>83d2OR4uI!cB?!xV;#M1TsG!tL@y~^mID(a#21uj<$a%|&*gnIH;ADaD zDP}HzISrPs&vo2MQVE3LsD6HDD;4c3hlWQS$rd4Xwfd)MgwKMc&RgnSx19J*jfBS4 z_$Jn&97f5QcqzqWYKC`r`NFiTZ_bXO^k$+wE9WYzyZUrNdhBLd}%IGm43)VveNDTw94 zh8_QMKxYy|2@6L>)@w9$lrH_T9@P}Rx*&7o_Pn~cJ8(mREvSz%>Aw-Y-=iHMFPXPU zSGsF6ogjB8U^|^B?oDu-a+s);M2BQF;n#eG{)5JE%P6bGx=jmM>L4%xSVQO6-m>zK1e5CkYZk{*1+Fk4LQaP+g?Q{8*UJ z{&)|JPwHDr2iljLu;{xt7GL#z$&Zh&d z+X53`g@nV%9cp-Owi?N=mZEnv4?}bpuR^(PkVIgPd56}mM0ileap7yK**Wo? z7oDiOh_!WX?Ui4KC|OSeTZsd}B(R-;4U@m<2wvNz(x9#p3kpI8^@V^@^Ey5_iU)Zh zUJ?nq@(glIGQLHVeUk5+SU3Y_cxpC5F4v^o5WiofBIH81tZj^Z^Epub9dR$y!utSO z$5*n>1MWf6hx*!(R%MYX-_Kx5R9kV8uS#^$r*cRW(FW& zZR={|@NQPy-~b_A?6MZrw4NpN(b&&O4_-Fvo!#kV?YoMkT?lkFy$AHiBICz^mVE@D zt~qT^&6;SI9Qx2e86qCnTS{W&h!ka!YQA0VEF_~H0f}|EP~2RmPiEfdit-(m{DPc$ zBFcUIvK%7)*RLM1VQ)j9hl6_Nmdtm zqUx=PgxRQQwB7{%MMq2x3I|%|NN^@p5TyKSNXB0XkU)CYkVM+4CJHr8FNBUspd?&u z?W>jlEK+`7gGKXP3L!3VgcR;q0Zo=0UhHCrAN?u#7Xlq=@l(x{3?t;v;a)tTDe&j4 zFMba*Iz;d5z|$xQ1~GsOJeRZYwrGycQ)b-@>`~?JSn)tiM(Mh8&6;u`c%F$(9t`=+ zr5*Im_jX0)oWC+Gv&tIuVgI7^T?9Nc+Xz7#9cqX1L=@@kV~O0M@K^VTRas^q!G^Vf zrR`2`TW*w!*GT}pF7^`RDNPbc!$}`fR!-wskUZ{+S$U|gZEPg#$oO;atF3w`lZR#t1DIVAd7x^4e z@n7;fW0*-jR*AVT^w|?|b8$N|V`5;Sn-2t(V5alHK@PXCH7ag{&eXcfw#hK}FSO(& zDif8OzWcIRN7Vr??SwtSQ3og98U;=&kqSQuX?hOPp$i%GC2@QNFKe@P7aa|~JRbE= z)n^z}#fx;!9pIGF`&a!ZBd`a!3sFXW&>6w;gsAQ#lGy+!ps?p`<*2>b&;;?Kf9^E2 z1qmuI2$5EZwQ-_of`wyDj9X-7-&M-n|NK5t^>At-bGn2ZRJupcr?4R#kE$A{%L^$X z>O>l+VznnIHCXeLf0%Ff-sW3qH0^sZzo32KFcZlZF-^Yav$DkvX5`(XNBe2HP#ykJR9$r-G@kqEyVdVJI((jcuh62Jt-^@khr1L36C0{zmLKaR^IuW_!?`{wfmu6tKXp zFS9>BMA(tA0Ld(g%gqFB?u35qPs?l@nl9Rk^uSe1KJV-XG?{Ro3^h@5b(atAn4OXui6QXvuSt_qa2uXL_y%Rb+5sx0g!v6MMuUy=wym__9!*g z)>B>LtI@JQEDSDmsga5PIYYG#@DU?)1+X#$2`1Wd162tlUXYglML03SBQyKoBJpm7 z9xdO67Hnv9+bg6$jfKEg@6gKZYbxsj(Iy2Bgu;10S)ch3xMpJfmbH8(i)8yIhqAgPH5s zo$h-&UW+FU3#BY(f10IwG&-qqy%r<2p5+_k-J6bHUV3?fU9U;1`mVu1K^44aLk2Ew zcSXHNpDnKfXUF+)T<>Gs)up{wnHbQ{T1)d4p^)b`&M@8eYCM1QN{gYUD<1Mnzs5Yu z)D)=3L3=+|s4uTn*~xomGhh-nukJ>`T!HF8A}ja>5D?KUsZ{4ig&F#cbI zRlDwY`zzY}HiKVGt^Z(ZssBLq4s--CB(PsrPWhycT2k$H3Gx?N2a@G2LEx)1ql*Z; z8O??}@r7V}yZ-V>y{SxSxJ->J{0~S6FD4-sybp}|hs$ayZ{zg#iNRqWpDV3a=Ly3g zJj2Hb;dGer4R#?xs|DkCE@n6hft$*_L>38Gqjg^s$-`H0_J6(yw|3UiKu7p=LMR>H zELF!MXbQ#{#J>=2cl+d?lf6m1>whl z5hfTI6DYKz8+r9!VbE6~CC#sRW~I;wJ3CRimCkjspf|gGqB^~2prRkWMfT2HS1~h_ z5N7PJo()|(Xv4B1>037c$%?mQ()%CE0`QxA97RTGW>SCtKvJtuD$koljgpT}F7`_l z&-x?m_Y@VKzd3_-y?F;ZOLSO|Dz2jwSGH-%t3f@YyF|aJb z4!M~>bmXjOQlj1^JyR`mk0gS}ApRA$mWhwD)ABq#;^lB%3fr&JW(5`lK{#ZIVbW^o zBZO`_(O>ZJc*edm1A0bJH=oVhPNOi%din!IdZG=!c}Id4O^vBw(2z*IZdLmjKbVh? za)?}e9LdcJbdLH?wz11#^nY+Jbp|sRU3x+Wl4ze|b#vKP9l%2-W;Cce+_@#Fc=puV z(E$~&e^6i6MYXZ{soDy=V3r!;UZZ)Z7P6In#NLBl3@})&#&i4%Nt5^hC?PU-)&eeynD>^BK|c#_e`opYQpwoEm);X9FyGj=2V&O{IHyye=vWj z_?M_7ijKDP7`-gjx>3XQyu#PmO_HRlwJtq=E zO$5)~ZeTVbkrQyv?$WPu_;VTH&$EI?kNTLJLS_nc$vAnD%AwqAUpZ~pq;azmQcUCn z?cf)pc;UL!1DC_|eBhilREiZjPioyZB(KGz2JLi$#Mcn90UHpK?evWo%eBwrY*JrT zwAW(hV)u|8?Z)ut-$Y*$gTvj~P!5Pu8f*RDH{W;BC084sQWOdrX7N|ZVKWsClI^Pw~?F0uS z-SP`IGAH6w#1?%lnpE1*x-Yw0e)=cc0U)Z)2Ppeg`rEz(O<4KhiT~ZhK&*EUi z9D8c&XbRoY66W`C!|-y z@DUEl78R#B>@|!B<(Y>(5ge&!f@Ts9F1wPx#F9B>mFQqQsrrcvlvG$!uqtAYqf2r_ z|5j~k(!y`ywxUfu4SXLllt|5K!Hn~%9HTOks;rk@h;oL@ifQxtX%+t=*Kc-UE4mz2 ziD<+hGHca5@0luTqCLf3`wo>r)0S6Y#U{DpY-re|D+N@LWgss^cd}f+WNWx~hjJgMcUpb%Def4k)Mk~L-U*N7AR@1!VU7mqqC=?& ze{}NLVE{qHYdwT9k+IF|VTUpJWd-Ortmr+Ri2)I40mCSm4CPOd?#kI+UmFEmeO2o6 zI;VvLjesM>$Aw0)@m1ljh*kb)Z-(CiaQ)O6aXuej4!mRH_86SoIbdA(f%mB4wlFE= zl>qBIns%?PCy~;)C{n>bj9-Oyh~6{;_mnY1K>sozD1>f*TeRoeuLGy~ z0ypX`bc%{4@xN+OT7aqFk$w$M+@%7 zpVJ7m$MwgM7QhY`?{Ie3Ym7W; zXNAjNxxcHBaY?qF{50O51n{*^9#Xtnz{fa{28g!2SU6$_`)GeH8<<^Ybvpv(N@8`$ zr4_wN=p;>&XFmGGg~mh0IylrHcFYJa)-u8M@XLk|Zlzr4t|$!>l$2AOSvzpBi>Iz! z4SQ=vG+*Qy^USmz2>cQxa?FH>)UwDitbB)mc%Px2YE@0WbYh zpCv$Lfa$I_+Jr8lWin>Iaa$)K-A_Gggf5ZQHtiMa{q`IPw;sTbL!}V=!eRWGxZ~ z#`jRvr7g`K{MF|Fn)~LeZRMY@CL%N`y{l|V67w`)_3@ryc^n8$j1=bi@x{?|1SNn~cE@ZPKomAiRIM7(rkh9b*pKe@z__wHKRAD8CVN1-h72zE#UDX2 zcIiBXG6=`6Lw%6Etak1u{gU_c^)|SD8sGR+$Uubk{)&dK(JPl6cvmc~-0+$S&Gh3% z?$L9Xe_%y&+nRVTRoZ)_CBuF{+Jl_~Eb6_P_d~&-LwQf9Fd2$Aa5r`2dQYuDa5pFC zmIlSF5KU2gDDhaV$;8zb?P1xhmY;JwXEQKAWdBgYNY|&BgtL$qenIUe)jY(WBAr@4 zyG9b>>EPq(IV87DO{G)h)z%$nLn+B?A`SnxMCk zWEtRhnfyB@QhX5!Fl(?;M@VPRQ{O|M%27Hmn9vtUZMv64?&`!sz3U3x`zx_4^XO%ZFKrR;ieU zI4VpmTFpd>;Yj_Yw<-b3bQJU(Z#hLu21>rIp;P*8N#n%tlI#I`t6gpZ_vQzv!6@jt z14)4o?29K5w^&ZB7lv6h81CayM)9C^U9M^h5w~ZU~ubnkJ?BD9vIB-`d6DJDy9xcgwVb_ z@tIkHGll>sx1vUR<5Zr7jjFtaRH|VJw1l23sJ9Ml8a3&&h&}ySeJP=-N*35Gu!fwy zR!#a&+{~wdNT1=T?n6JiP>0ZWK&xwG)~UaQ=amyMqt*HUzAal5=b=_bmR+*5Q>z+8 z?ou+#sLYwn;;KVEa9^=(!@03USi0xo?8XOun#OlmyPk^7g~BVI4vw_*j}|kT}rRMtv0tPVmk6dz@x0?z$rB z5k$&6jrTJ(YKDyzl4QNG2jyJ&d=0>l0zQ`m3Bw$zc8i8QB?9z2fx8hegrIj+FwFRG zPjf9poBzb@TQRs`ogH1M3%UlYEO94Y z=@8%`XJ6T@?eYo6=t!e(AvKE4U&`DxBkL)7b{wA|gaLv@lZNZ^h@zOgjPi;VXt}DS z%*~a&A|WRSe2of(g?SP*sFMk&M>yZC#~Va&m0%UWunAUmCeni=%%|z0x!7HpSBG`V zA*cw%I`)g6$Q_Zlh*@NwSn%&xoZtKlQ7f2nWyks`;u5_pPgVf@G%VF#gjgOUM0Kgbv2a6*pc)}_TdcV z>LI*2b+&6vcrg9-P@c~}wl60PvO?*#?6$1{CMB}uTg8|Yrc1t;`HX+x_qN!gLI(Z> zy5+d?rLra=M=_ai{zoqKN0yQHvikq|(JHw>*~wY044y;2UxKe$_YN&Tuex;T5&wfY{o~mBn;7A zR_YfETK3lbhy!QSQ0Eo!viG3x*)C*obS~y*>M>LG{-L?HXr5cO4X2=gl|m&ZiJt_5 zt^69xn4ok(i*=`kMYFcHU1TCQL<&kBPvKY@Mu zIe6v)_$emubxZ*Y3X%6s&DI? z=v{bxSW^C3s`66D@>H~HR_3w+}$y0>L@HJRg8j!EI{t{NQ5-u`7O!m?V-hK-=inbwfyWBswBnOE@xZ9a+k5N;sf zo~OE05-C1lyJ+A+Tb5H|(jMX0kRi1;snHrTc@&#YYJ2gOq}Ef*xAZ?9s*U%+ z`bm;%PjO^D!T&4GR5>2o@$Quc?`hD7;7K04+%1=wa!J#k=&7Nvh~%2B&NU-6S|#b3 zG3VZ?ZbhXx!iIzr{U~iVBW5~1ntz3*X42bYE_#h{VMZNhL{P8q4}jFy1Fd#|W!r4; z9Uv!rSgX}ea*uhxlhaA)-;WAO+S2X+`Ef+J10p+tv8>2ez+Z4~lx~Ea0VXLMtT;8C z$`#3?jnKTpYRZHy^BVHUEX?)y{>*JokV2a^SsU#UFGLCN9GGZLf`mRjmp`$}j#^M2EJGx68cn zgW*~(--`G-u`(uO8B%0nvr;@5wLf#+0uUcy~yc&Zl|0lcuN8i zLRa*Y^9#Vq3ysok#6Lc67}n+ThBjpPQYRkM9OUw-hGFX`HdN8eMJNkXc)r2l?6L~S@LT`GVNsNN-vT*|?K zRC`|Loo1dVIUyn3YYYM4<){Rf?5_w>LKz~rK%pjNJIKUiF? zxB|&N6d(*QfK)|;YoamEqp`IBk1FsL-g2^eL+7#z=qX~#Rm@~H;pJy2#4O^@%uaYd zARTT_mK<=&XeW{`6}rVXM)H?&rYO++wj>iVrt`@JS#X18BXv&}s$?EXh-3}iS*D7y z@G6w;vxr2Gv>j}+x_w=_P%E<}!aOr(ZPvhZNz}NExMcNwPsjh$0!Z2p@?745^J}`i z&aQ>8P6n;wb*4bR6a7l9R8y)X0o(&TL)G&mLRXQ>obCElKQnuF>jWqtk^WZwh3qnG zvS}mVGr!7n`HIzPC~QZ+&w!|Dm+ZGtq~fAu;^GK@Gf?1h)teDJ?ShUQZa+|E1k3 zQas9++z@Zdqrs++b>_PJ1SF|JW4TaTaE2GsA$f!QyE^`&5-M#G5@a7-&cmf`>(fet zyW28(y%pv^YEsT*Vez2b*&)M6dxO`Ouq)dCfr%PetQx3PX{7h1cVA};_dM>tO*VP-xz;b8i)!#p!) zV=0alvsrzdzaz@f{)hT7pQ7g}laz((d^^N6Jjb4oss&}p%5)54RsF6xBw_@*YAhgVu(d_UT)T7a&T}aFU zx^U)7qk^c^3{*_43M9qF0zo!)25!mi+11u1%J16@*rLH>tXNQcE{`Ki=Sj}12_1Sg@{whSvI!EaV9sgR)D@WzWwz$a~e;%O;4#p|3{HlMjp-k`$wPwx^)sEjlav7K(tZ zj|v-uZ)-I#@6;qSFC%b9jlf%eg)%F??FZLaT4}MUsSvc8Z`J^viPhaCrVR?S49z~p zOgnSB>R70Vc;9||x3wFD>JDL09$RdpMHL>~y6K!*?)SMx5(r#o8--e&*$zO>USIpu zd(uur6o<`xC-INv$r}BtpiM;PJ+3HpY6^Ov?AlSsfaeEagvB>*)z+go01nF(d_Y=R zUHZgTGmD`$ounNsgOZpg_($+b-&6{FA41cff9VH#^H(;tg?CNqlO-yR1pJIHQ7ybX zRGR^=*Ehl$8V8X?&f_nrq`ba>x!X1fciacGQgtT0BcyRnmDO*)+_<;9!}Q+$AF{qQ zAnELTzouqtYSO5t%mpVMr<&3-Get$G$)vI}bDBzAD#ly^5fv1b%1TRtR;^r^ved?u z+*sVmG^t$3Tu|9mQc?so6jTKMpYMzR3;p@Vm)y_2=bn4cbDr}YI#BLxQA>d0w;2w; zlBqy46OvV3{^|6>xfm^qPypU&*VGjgjf)(Tm-A=vmmgna+6cS&sqh^&T!$YX0+U$B z6L+)PtB=b*vQyVDCPTfc4!s0I23@Rw2$>=DC!U9+5!Aywy1D6v5Y zx3=UVYuU|^bAos*2}9wVRSUoFYQL&bznWo6zo`~q8GJ6v`jYY%fKX5IUHy*TvdLO| zRTx5fHQLLUzpTGcPfGykQD&&e&&ukdc(Y1#AVm1#4%RPv?SftBaCt(vi3{1!V zfFdYm;4Qtib8oHV2hlq&`|dYJ!m0ZQZSO8(dr@euE~5WK3jrKdW_o zhdS7mGrNmjQ#Y~_1TyeLQNtH4%tBh%XCNCzakq2J2%nf~e`o8)9D5NK<*P0*WHwpM z{?L*l)@Z&cgk5xl$nOc6?LF&!Gn&J?6ztda-G_2<{rC4}Ab#NRWnxSu&~SK)Y!XBH zDSNs>C(P36>ncnWq~m)v>NcQv{J;7}6UdT4#$`8jHDBLiG9Ij*-au4gowgJ_bF@ks zdbok8-+~5E8R(OkR!{{JB#EQ43QKGpjcJ%IIM|mslJoax2pRHw&q`bOTiv`6W!x=# zo+9X-{Y{{g$R`$KEMH4nJmpC(5944mWOd{|`i*%0>_G(SO_Ev)eI$hfNSG za=E~{|`N@E_UgIF1Ga}2QHx| zEVQwV0w>-EngEIE@wTY&{&FOG?SOhc8koPh{fi0aR$O{_@7m=9@o|syg@ja9{fG(t zb8?9C1M=#?l$^u(eJnuM*G`pGW0~}Naa~SAzCO3Nw(i|kfR(!;dp<>L3g7;1cEZg? zP5;un`~UP{&kI_>KLif{M*l$+LU~MY>Dw%nU+gz^%-T`zHBr#|?rS6u9*@0`R@BM? zzl;)i%{cb#F9Uau#H_rn+K7#2B-?T7rR6h^c3E*^xb1ISMLn)`bKb?md+L8qoOr{U zabm2IR%czz7a?+2e1y=2m!m*~<=-=v=M}zWlY*Ybk8VI3-~1nvuJU=7sQhPK)R#aj z*eUoXI_E6o)VSO4jFr-56Xt2{feeXXOX$dNLv<|}h5aViv|#KJwYd$DpU}V4U=l2~ z?yopnwFOE$z?Fi(fXSju4RF6HQ|x{hPVt_0Dv>RB=G>fFil`Ta7*zxA?al!;77>Zw zdZ`E+=F$?N&9l$lY8H+SbAllmgV9GX_9W!hAHvn0w#zhI!GY}Hp9NS0ggdOlYVwI@ zq{lbZ7sZgk+N}k}`5JwkH{MXx`uc40v^q1y;NEcPC^7p`1H@}7kjDZFiyVNHR9srr z7jdh`>2r{xEe}vXdXfzFqT^ANkE0k&z?iNE66MzFa5ynFDcM3{5~{@JvT0)$^EFym zvd>55r~H}#=70w8Mi8ad^{NQXuZdEFilJ|@db47+oPZM}2hlHIH!I_#pi%f_+ep3RBV>d_*pV|J{RsW*kcKS0^7)qk1EZDQAV zF=6*ODUwG3P3-KbG$1isenJ+0n9t4OIqCf!JJ^dc_GJ{_KCc+=P?taf*AQix6hOYw zmlCEhFD^awE8SxkClc{UZvIs+CM<(Etv3)SgoM}e=YzJW#s1P*&Ge1O`QARPsm@3Kh-Utn_2=FljaQB(9A3NUrJyzP+NDh!Z{2#hFXH#pN3R~+k6-S6_!jQt zKIa=PYahLDn~v4|By>2W0sa%zA1w*A`jkiy?wDds)8qbfK1t-FOz3EM#aC$<4cMx< zS8?mixTE=lQ`4rV`2}w!EOV&4i2E^qvkXX92Ed0}5{l-MPOj*&`8HM^W{>+#+SBek zNH40BPO8gaE&)z*24mJ;?}a+o+&nD3pcFX6i)7wa#eNxz@}C(moMq-p+t8-hoczIb zFgft_8+@;jn<}<9YOvsEJskS~4>#@4Fffj=$*(DZR-A zdWj%7Yy5Q-KlODJm|)sCTt};s#|H}2`J?G*vEiP&+FUUjY29qzwUwkB>5@si4)q{t z*r?hU307WhHLLDOXBN{8qBnMjtToVWyAw0@(V* zz|+s;NRr-Zb;b7qu$8!@zLE+`-k~~daCDTUtRUd|8@c`QI`=bHoMbEl)ttUnvs%6( zGM#ZkYoY1AGr3xnm7EpwgopxxD`{6{;2IR4v48ljEHQGL{w1sTK+P4^`ApQMp(O!r zPO)0VcPuvTl#~`N?=f|>JAJ*1lL%{)uLfyO3Isp9O|Ms)4wk}?RI~fdlC`;&_x2889Iy?MP|@*+P5t3_)g zFIF5Bxoa!xJsNIwzBdog1m%~7cZ;qFsL&rCE)FS~;da)&SH4!jj-*v1>1j#u+dTE& z$bK!M7Q7+oG&TBpZNby{wtWh9Id2*2mT05fFw6R5trud?@TDh)fY;TY!oS&3lAdH8 zMGK^Aqn5pq1Zj!<{7lMynXf9Ox^7x@EKk*$Yy( z6UM~7eFv5P?xg)oYzf;9in1mA>tv;l4yR<2vji1!pVfCFqv|U|jJws*km4>@4iMQyN)oUf{=Y0#oL) zsw8ounzWnR^OU~H)%r4DVF=Zlu|vZ|6Wyt2o)aWvdV&1{T)ot?D!XkQKa*dFE3(=T zb~$h3|W=wquH+-_8WrHl`0PRzVT-Z5!^w13@cT?Zmeti5#q!CDSSUp3^7lX1$$z+w; zZa+RcUt;1`2Es)3%Abnqlmn|GDE8ut?{C7)qJ`WS3LdO0I%DoH?K}WprZhlB1k=&> z6D`)jtZdExXYJ6XHL4R2)+F%y!buy7E)HzwNE1IfGTJ((`pidc?;_Yb19&KJMT@*` z^_&v&kHC;G%|nzY(;G(UH!zad`UO$?Zpsxjbb8C4@GQyit@@615ji<)OjB-ycc(oP z{f_x*Cq-BNXvK$-=zWq{^0uYU?)DRHl=P1<^h6%*UGH&z4hB|$&dDE(af)Vp{Mj;c z{860exysE2V~lr?E`sNBv+~=7Z?S$;>0_f9Z9RA;xW3WaDk<@r>Ku~DNQ?0vK#1DS zlgTFbgP?O@S7+q!9kNGt`F7Sc_Q`r>l?Z{eLmn0ALKpyiI7t8lD zFL(o8Mlfw4P5+%jfULX$+lWz^k(28r?^_#sZTxqaKcC_{8qv7z2fxm}OtM07Iq8Zp zsm1mj{!LXT)`a<@o)e1{$&w=KOPSBNp7dFK6|UqIfl~{uuRLjD7x*5yq*&8|>0{;5 zIl;2nxHiA8I%(UwYR({fLMGexrHcjM?Kg?fs|>cV9s#uk+#Pk^!jex3ZG;e~kL4en z(}-9PrC@h1O{y5OzvMnQr$elo3JVXi_4{k7r9BVYa>`=#z3iTUEPvCld5AX&%>s6< zJ}9-ab6qL$D0Kx&l=X=*Z+$c?rWJ-hn!V{|^NkOhGCpk>MhihcgY)wr6$;_~93*-aBSag2uO% z@vxF8<2<|0&#ocpIjGlh!v5;CbFfxq|DUfRxh^gkLKK~Y!(OTOIAh$&XIbD-GE(w7 zP`Nx};X!gQouO{ojP5A-@@BI9kTb)Y0~WNqx{=%{n$h=D^Yz{7(3Q}%RMmOP{c)w| zK>InIcje-9kM8R3OD$sUiGTbA1FvE}sfhrX11o)DB}zdpA7*O(V23Y5D#gX@b)-e~ z^ZMzpC&IRYu_OP=!dFAo+gs`PHW&Fy%-55lUy=g2bE2WHbMijJ!YIDBkbs~;PS=@x z$&=Yqe@b?EI|L=LZnR%QE`HM<(+`h^ZK~2p$;-ki!cis~r4OXj1xEtk&dDGBN#|@H zFi%1HF{^1I)6?onbibjjiyvaSP2D+vq_sEG)jwUE?l`W;9q><}gzi@d8lxW;r_G`= zOt*jtPBFnq!vlVjlpFaqAr|n+t$o&?uvcmdF& zZ>`_J8CwVoj8!qxBg%AM{(*Tr!dG>7*o^Ji$JOP%#XJ9jKZAv3+Zw_B&M|PZGM`@C zbk}@ae$R}Kg<}+=L|Oj$?5`lfOc%h$R#PizvC}{98OzMl^`|4u87OOtN`6o}r(;1A z`s2%=-@heyH5bDtWW1$7*+%)gH`dpmq!ykXix9r8ZQaCekH}2v&+_{4bgnuGIP4Kpnxcy{8tf9T=UAHsadx?{5j`I=;KeNjx?%^eD2ww`Kxe zy+4%i^Pd7+dQlp(X1(SJibs#D>W+8I|B4{}EvA2;3A>O`wSwmyzk$++fh^EgEiTs% zjD6!s=RNd}Q z$yrfdkjzX=hnXkDeg`v!s4t*B$-6lXMGb}E1`B8n)ZOh*X3^8pKJ{tFfgzg;;8h(G zh#m+&k6V!*AnG`K(R^H2Q=7FyAdUpG^hJNs4gq%dni2A5VM>T+IN_(b>%JTvSRm(C zm11!FySy^b$xSEfZ^PjTIer%%*9!hFsNg^7XBVpv$=_S+pES`S`(4v6z%DS~t>)69 zCv#wy7YFskpw1}NPeG^8&DZ1$_m%F3Jx~=jXa(opJe*FlmC;FNcfGjS#YPnE5U8g2 zBfcJh#Sq$@F0H&okSPT;f@z2xK?wyY&1}Z=B3Q9A-8W(lom^62qb^TzWF&KQky6FP)@3tkXhUnf%LZF zS)CW$fT;dTY(@xLFPGY%+{-D1*HGD1j6TkEaqZ(u&X;|KZ^DcjY81b~CZfCk5QFnK z%zLt;o|r_4ol>*4MW!Q@Ulv9Ms{_>Qm0vf45gpqkf@*$FI$=911F_7B>-gte#My*E z&en*wgQB{Iitn#;j=sw|1^zvmVCB z_NWc5A4;H^uFsy=kI>(lPg`IHDm+;932+lz@)8tnv5n7yGbgt73vvk)Kij3r5}?4- zS*!FtA^FlZM$888{j^=zt=yLQ)}h#}(qz11pIuk5>XnVZIhz*u9Gm=pPRU{~edGQu zV|%@tsoEM(9#*>xAZuzx(1skd1lUjX!~C~wXxS6xyAKB2cY&>s&y!0aWsyc&@`2$L z<^C^%j<$ViDbnp;9#b>p7kee|b(_4dJ2AFWZ)R!hIJj?lZesg^g-f!<`#t#3SDS_y zjD2W!6{|wAbIf9;IBuFZwo6gIP7_cS7sOv(KDrErw(BT(u-^;)qkD(pbM9KLS_tNo zwf-Ejj^;8m)lq4=;&Eej!)dfL?56LE+gFghG;Mv7%D)A%68s z@=cN6V7|}7x5p;yzAWLUDv)j84iUNVqTmRl5qk1FM6UBIwBnOR2`RZ9`%6vUtJvn} zk)Ed3PA1vYsONWM&MIe0-(rt2E%GU2C{nsjuYPFCv;XYm=hRP&e|aIt7q&9?mg?>& z#2)nX^-*l+>Y~SJn&-F^t{%)lcDmB<#137%j3{4cd6(qK>sDf4v%+waxGmcYhyZ#tU|D4}~ zCA_XyB-cw&w>snbhZ-Sw+(t`w{_B>O%5$}TE$qOCT){he~#z zTu~Q7z1WO_MNYY0zE$1?`nTh(^cS?Ji0>jgGoVRd#}$9raCWh?eberjZBi~azejqH z89Zam%8w)mN-AxRb<2+t8Hbe%a&GC>e#fAk)Ys5cd@&8A{V(x3!^6zpNk;x*sPl=d zX^eL_)A<$QXr#ivKO{Jr%J%3=ZGpxLq_V)4ne{iw@3)C;5_2#qzdJ3bKz9?CCFFV= ztz*=KoLAk_c9hYR^R(m`eXyz>B@{(~SL z{Eei`b9`OvN!nK}Q_Db{U*zc<_rRqnzKDD93wWmeqNqY%vWleDHH;U%dll)>Q*o16ywLfI-a>@@t$PxwnH*SAl7W8;6c_SZ=?PGEW zsInpP!bzhlyRMq7_Xoudw9d6|#14WyQYLv|TjAPTD_450S*bZg4wOPWE{=COqaYKd zPU|UqF+z3SL}W*MQ$2x6d%?~2`Ss70OTvgkK-=TfleaG;l}M!sNkGWW`{a$?pw%53 zuRHk1dOKgu-y(bI>QAFBg3XXv*YBzz<1T-e+jw<5rbWYk!o9lKjDiIu#2W0<4w>Hl z(uH;T0hbNbNq=Rmy3aA?h(;@2x9E{w$40Rhs;n`6jWWabeXjLe)z}g^#~~mK+B~4{ z8(+;VOT@>oyAyQS_;K$Jp1V_KLw|@_a+RUCyE`W*0+66tP)ExuoW6A&>=!`YF5AKP zOs+Q5#F3pYS?c=k@Tn#6Ry0c0t~Ez;RDxu&^&J5xBP<+^2u#RCNPs{fx9KzFT3x>M z>k5D{cEozIIsY$q*eeTnR-0_J5WX2{>p8NnN>yu94^eajJ}i?nT4FQGM7i#t9F=OL zLTd79ne`o={5q-t?B+COmsU=(=GHerf6wJmaWVf9jq8=THU}?L8Ko&=bYo`I$!gu= z&t5Pzg(%u>cfL(DU6wClTAzM`pxKZ+1?Cr_KL7#JilEPC)@_MV8#=7Jlk=o!d&GNo zo~%7!EY(7e=M=D68v$OXg#53{P3CsiTS>Y9UNw?T>O6Uf4Y7iXoPS8=^kFBQsQh!V z0M(M_b6VY#L(k6}t>A*hop1Pu=#f_#hohzj67dZ!t1EkL)wS;R$A`of26H%`vQ2P= znjK!xDdd~iwKoo>tF}qa4Wuzc*IpEA4(b%--Z&L?RHM!0XgW&6MI3xgCWMA$jS||e z7k?~}=`3&rHLkD|FfEGmKFIQ~cJ7yxVm&V=Op|AJomVvKCBhyQ9w>eNVp$9TZ){gJ zeEcxM<6I&{%?c(|54$v+fh?U8G3Y|=#=NTV@aV8MfMp&!_fcKGdMU8v(36h6+AVXv z#C2SeJxyD61ExX}X$pDc+&pWm*9E*A)j+C+tb{*vlII`L=6gN-A8qbnza%`fSZ@DM z5-LmYc|zHZ%#R<&^q`Hnm}2L#QQ7%g61pkKq>y9CR-0Z(veF z7Z}itJXg3Zf_1>(->6(*9+syxho@<)D}o>AL`ge_v8Bz>M*+{8H?&?Pv8ecb zc+aDhpDmXMKl-gW|)T|yAncpOtY!kM@(o;KFWRegtr`#bP&S$b8UCO zCK*ZN*DP8BkVqzErjOnnV3BbB)c0I4kbX`i4%pQlw`d&sCkxwNrBZP=3&ADOn|CPI zGfbq>NQW)U`nUjQ;cA!W!!dBG1Zj6{#QX8X$vpo?t!06XxOOjfJNc2-=gGw z;9Q6|LQ12nW*0aAy=liLn1yw7?R>p1YX1JmXFV`Ull%bQ5@t5NBIsH`?uUQTjY z-q#sW>t5?Av|>QMnx-YdUg1`vv~}31cuy+f^_+wxH4?%z@HtycXc*IfIzXcs za&jKWOHxjAkI3tItyxPW@^%okXmUK|rUdcR{|RtIy)=KwV>U?Ir+_&(uHTi~jGJ7h zJXDvrthVuSg61^6!xH4C5poY`oj>EsqDuHx@m-ya=2BlT6N+aNBXO9~>@6kTuTv^iMMyqPI z@sgl~!_T36%|P(UxRpn0ZEjr72HGEMlL#TmXBq?=*$qx$C9h?2>ufzJEB*SDAtNYa#BG{sW zvT_`k94~y8yDm3t)1CIxruu^Tl^3yHldI=|2gc3Ic(%jgUF-|kKa`|~u}EFl>wjwEGto7aip^na)Ec1CDQ-&9|q=W+3wp!)w~r+zSR zbhCN>31j&QmP|-Ld`dfWG0r-_vnDQ+nrH*h;W!#&UUEYsdSqC9Ra+T}ExDy4RY+3E&*{aO$1USif)HY; zF8L=5OAcV1ftcXPqgpe>VN*#ixX%`T+-X%Tr!9eml_+XHy96pDKU|gEQ;^azdZ)J^ z6D%R`lO`;IphmnQE;1fWfUa{~0($v%>n~o1OV52>{X#wY_1?fgK8RQLfx$G=V6^e) z-uv_c$bSS800WFEcXNAd&EjLH_?@w}6KBW4cI_IUR3`R0j@(T@ zS4iN!y8vIqR4+q9SDvMyXU<1{8I)IW9XN5)(v z_|)nj7?0R@lRhSpWgQn@9b8!az60RUguGf9?o2m`3kf4_l|>haH*?lU8yEE!mq#rh z6#S5Dc7szZQOsSLV6l88)gh5a?(2TDY#-{sS0v(H2gN_wy#AG>nYgIG`xC>=T01<}oi zo71_ctP4*~4E&muQdgI6A8|CYjo@*!7`rwa;)eTai$>a#Cs4x+88Ie_3%NHL{15XV zKUAm7xQpMJD`z`GJjs<{*YHr4&^*!tGsrS?vg%m*7Z-A1l_fmYhaXFU)=Fp_I8&pi zRN)Sj;e=>WV>lCUw49pZ&2TW#wta!bCYip4BIo3;{->Rpa;g*pyF)m7;!Qal`_sWC zrdru8GmWdk6}p zsKE|=mozZqs`zqX*ex_A9t=stw?6Lug1riKq|TcBr_j2J69rNe70F)OacL=G9;gJs z|KW!FP3~V6kUf@ilsnDFo{BSSBI9M@MQEdv7H}_gix%2Kpvc@iwh~+w`%35gLX%MI zTKBikNPAZ_CMfj!wRt#EYq&J}=v7&{BuhUMN)h)*{rG>Xl`p+Az53H-h*Fj>;{>RG zO2l-Bg<+#{NHGauvx~~KmD0li-(Eu`!+K7HEmE5iYz)&qg{EEH?>YF}fA-(| z!qzkLJ>jq`)j%oSCQB})e;>f}IqT<&uYki8<9?**d?=IBs|m!Hrrv95RNQE<` zFjq9+ECsgO$%?*gY6e=Rs|UTe;P&qP=FgCNJz_)=#)pL9zk)o1EuN$xGHf)LMg1GR z11z3Z6ag%rGx(!t`9pd^J74XP8N0c_nnj)10NR3qIBM)L1K$XB`#RVRkmjM(us9WB z9*scX3?vOI{$uFv>~YH}JHm}6b_5<;LCfQZBMjOIOQ4e-e6T-8K2t%;%ZVYZXVKWS z#C1w?uTXH0AZVXE6{T41Zb-?3Cu3#Nq|Q7y#%}4)=9)ZSjN^?Aj+<($Mx4NQbo?nh zTrZRG7TX8F(!s8*PP>Z5#|fb8WI>)Jn=-4@CXVd;{Hq*hqHPZn>9A-#YLmPCjRmw05>!WDZJ9$I%a8J*(UuRJ zmqOhgQl!jpkEHvryIx~JY6Pj3kw3A(y>aFRC#WZR#EGx%qb-Ad{#W?m2SKN2HS?9E zrhJty$qwr2Cfc#Rq_r_>@o%Eao*2G14(K;xOm!CZOrQtRlgtGZ;s{^k`wPlgO*rHV z_jNDwGp4hq&sy$etl@rq9LmYXUQt)A#nqoKD#sF)3p;7MK0o25YHIpQVSv0a1=3+wHuVD~yS4 zJdiHX=;=^GubyYW(yh$0-PO4aoubG!#{$IUxcY*Fv#}iztE52ef;f>B>z;TcLQ-Y%k6WDXpy>XTwOT3=StzMViR0nl)8)cSh$bbkSF)|fxeL#LF=rx^5su+}fR5y0ArIDdg&(#hmv}I4BDhMt)Pw^_X;P>@sXgV? z&V_X{!(!~2$+F{c5TR(Jbn@)jYC6zG;__Vy7LPM3YSH()T{2qEz01og8%Y4r)&%LF z^gY#6@y7Eg)vKo?8yt_h;gltkPTE2iUOj^*;mh77`#i+AZb>;2kTk^eB=E$y)yW3z zZo`7%cE-*Qw~k5+HCCZY64?Zz`A^0j2_No$Z4j5ILH3sFmV_g})#T>H*UH{jheT8( zwT6*_BjJ#ZD}(4Y@k14*qg9-|0;UJ}X%->4%MG)td(%m4zUx=7jr_ z0s4RZi8qdBTua{Up9cp!8(hER6p`w9@UshTGLb1o_g1`#p-7JNjD&wzb9lFHzVncva%>-kt%+wRNa=>!3iZ zXDC(AOPv$3WKZw2B~Jr8Ax@rc0U!u_^UOk|2A|YoI zu*s@bnx);t^_0oJov= zbW0G?s-Cd$O0&eUM*jmzb1t+#_Thw5Y~Qew>8M8GW+eKxT+*`xQyxlb9m0_ipYY_3 z96&kkA(&S;!KE}v%@BO4PuOU@pi!1C+?pEWFQge5?0>GzK?amS+Q3ApY+0O`pVes7R*34pQs7t zvHd+GWO@8+XR(u2xHSysvE@8_^^|Z6xtLy6Hr3)1dZLtVGY-y_SCW%6Q-tns&(z-D z?k;PUtO%Z72b#HLG&SnT#?L9wkE}zJ=hp#lA&IZ?(pCh6F+AazYkD||<0bBU+jw3` zEzv5|RZqo|xW#9N$_i?#WpEqrRA}Z$MWPJ3CXw9=8gh?8S6JMqK)fH+v*{FErnS_4 z5a96*$`K<9f&IsDEG8Ih_ZH(*+%Cg;@>$3|Er0?>gwA|Jdqt=uIl7+?VVZIzUe-1^a$w8ug|G*V5 zY;Htr33CHucvhgZ8U*_bxAKPfJVF0gq1cA}bi}P`cE5*E3RXRz;kDuy^2D1g^;?6@ zeOvO4e}2<7_9b}F*|{p}&m+51LKr%yBhgiNbK7|+zqvZv?H9J8is`|bo{MR7 zT8LWPTaRR&6bF+en#Jq*AM*n76ofP;fmf8uf^{!91BUR)!fQpe@eh{#2tbv|GIClw z${ILYiS`6C`f>?^Fd6QFB9@3{gn&X_fKc^Eol;7~CQT19>LYfxTYnyy8lh4(Z{;(&`M7*9id%Xr1ZDJs5UqDM$nW%MMMoTO0pK-(x|+2BSn@EM&sL1Gn$Ov@+~*89AE%f8Y=-1jz0Oam@)7+scAf%;uO4 zGz)ZlJur1`f!J)`jwF0?gayhr?+7v^KAnun*c@m40|kQ>Fg=?cj2m`>b+^&C;Kp_8 z@4Z}I8)uW#{Hh!sH*z+&qSpD5B3^bq3`1aHHwGn_bZ((zsYUidhfTh~m@RE^tD-WFd68f3&6Sc#(UUv+#(JY^nmxG}^9Zu*?l8-TxyxjCQ?BB9l2|<^m zHK%lhw2G=dn?70~*)qe(_YJfz%z$3^z(KkcB*;@{s?AyL|-eDia60voQO)0uT{ z=Nr90fAjI)qP)IO4xwH|X_I$W&iF;b&pC4{TOECuFdu>vvTeVQl7fY@rrHqVw;QG* zK3XDwlUpE>k&f3_TUt^K&&1}I$*o1OWW{6rq;lagUM|*E`VQO^(Lk7=3*G^GL+?T? zao4Z&UZFCK4e(%7OFW0?*_|zlPa1#C1Ao^b+>JCNeROo(MfEch`!&zDjCze`T~!+!Y^@(yg* zK%iEr=G{i+!pKw`+`}5ISBXJeEawIf3~zvV1{87;afo&GrTApU2kzVx{I|-6{Z``^ zI~v;C-(onoW2KuVpcn<=ci&4#8%N8PqHlz#Upwj>ivm9mFVUKE@*#aiGLf}=zk61> zA#N?eV;#`5p0khDh+rtK?g-jlb&I-{k|a?Ajd%SH9y6iu2q`_5nW3U@U4{1J2U<)O zfTMmrHS6)L<@B*SgNnT^f8o`h3{Xlvi8{vJj7y%Z$A}H8L!liqgi{AiZulnbTqCeb zE5W*|+)i4KMMNAW>rSH1EoMIs{#G1Wsi;WvG8WQTaV~@#7@kqK)jHMJIVf_Io$v5V z1~I5kDI>ymYXn4Ouez55-9%YfB{ucZPteGHX15XZ!rGf!CS*r#fZ%6J$`p-EP13Se zFfCy2XTTvYr2Tyq1440^B_I2H{I5> z#?$yt*3Q3kno7MhJNosW8K#amqP^FQwrpMil-A?I&rUVF5)XUUAFpOWGoKK*zi95F zsg!0s%OD;0({n0D&8E}5s7Olpy;rzO#dwN2? zTv$=90-o&wqjeRs`V44a4voI)clq*RfU>nhQlGVMrm;$?HVSRF;TNzTE8eVen-dkk@Z32Q z%Stfo&p@~x&3~{>v^RR**P2^D=N&{jfwj97mMa0$ZpDwy*^5d+e6~_~Z0xWCwQEbyW!=7T4h3 zv0sfYHw1nzwn=u`vUSNNDJ+f*j#6ZkOi1NATJ?!|QZ5~O^-RCw|8oIuCPvK%(&Agy zn)KJ|!EsrGl9=9V3_TF!Jn9=nHD3MHhy22JYTC@hMx=Siwl7np z{BkLrP@*thnKI{*ZJ9!JTiBw%P&ZH2w->)?KK#;`ph9Q9mm{5i;uaiMtWbp3H=oHw zjV9?Ks|Cj4{S75kv=@=d?u$JjDy#L;wF2Jvf5L0vmyT}xtOC-9oXN0aQt^uxsAZBH zSbyJuanmae*;5OLs0$Ta3=1;x2BmI^A(8eZi!N5yPG*iYP}v)s+`ywkHNv`6IZHYa zf$I6k1F(az*HtiIc=w^}v7R@*>rOH0Y!A*UxM1eKPji!aj@klM>bEm`a%%%b7MA*J z!KU&dpLAvfh*8$Ne)6+bR!HP>a_Nt=HZ_Uv;Dx8kTTc2n1`{0A(D^^BoAdPgcdjol z$@Sz4RzWq+Xcf0y4xphIzTw>|dmCu3>)}fd*Qf+y?y~9x@5`5q8DA+q^hNOP&p@b9ax`mJWZz;(Qu z8y?#}Jft*`@spN@>f#ruc6R+mr`C&us@9KP7DTEWcCSB?(}vV~wNwM$bzD3d#BgXF zj$fjM{N_Zt(=zH>a{gM1$PX?cl;@7=>g~J)4|Oj$*hHL%F_|+-Zqrb)sfI11iGqG$ z9&Q$DJnKd_S}SUaYnP)vybWWw_$D9t(^w@zf3$9n04$!c5R4iUo3b#Px*1{Qr4QPp zU?R2oj<(`+Ph1DMp(BrNQ-9zIkrFE8n2VB9_sOUXCGk}=bz#cXCwK;@C14$p4ZXEj5Nnq+ihcbvoEF}BY}&$g``J>T zOS@g{7)1BC2B-Knr@3#M+Nh+QE3>j2Ppk)Ds|eB732v_<&T5ApmGgS$4##7x^wS@~ zEfzyxJ3kU?xcn}FWB%{-OT=m>yRv$hkNCm_k9>Cm3qme7e;^`}(Kg$}0F=-G_(B<# z-n_+Q|0*wWv`+?lws|vETeF!xl(uKsny`8{tl{qhK%69kae1JkLsMfpi}0nU>~o(z zEH?4ALnGie!;Z#Yb>nA16!#4n+3&;84p$AVjblurGcqVC&OwG$qLqR$9qeiAcx((b z!eZc{BvB_p5OT})VNqV{XZzAG`_Bmvy;aRTEsTWh5OmzUw%Fm}M|#qayL)Z)cHR$g0+5t`1py&&w^)WcO@?Y^~qpc-(w_yyWvK*fz6TWKU-xo8W_n@P{GS$}u%bH25 zn-3IQ8XI~H?ux|Gm&_g67+*WJBL$f8+?!N>7$s{+>wKTH;uG%eBjT$fK+h#bH(d&8 zFb8#MI%(2krzNZN4$MLFj)alN)jm}9n+)R^Lr61+{X3vDYugR1&w7p97p?Xhef=a5 zh#Z>wgwv^uEtAKMq8zNiNyz3LvFS{I=R@k?hu&d$imGWZe~^)`(c_!3T;bg;;fRRW zEHQ}C8Qa|rW{90dSNp-M?e3;lBjiQp{hK=nGPo9dhV-#&2^LzVA-|r+*kJ!iSclO3 zJ+#5bPM!BIeqix72zFP8Ug0sn4y@1NC$crkd)(g#C%$Svvy1SlN_Mf^+yTn_&W+LU zl{8zFbka?YC5G(Ai7ha`)@7*DZG)j6^WShTC-5N4g}UGkloYx0HXxLvz&m_@*?Y}) zY8m^md3>%WVYW8!^3|eH_;FuhRKGZ&5EnD(1XLsR>QB)CLt43q4?i3F_m7Jf_GVXU z3wX0!URwhGP1gX6TzIo;yuUasBi%B&rr9uU2r7)U9v$F7Edf@T(>$TH8vm_Jyj5v{ z1Y2S-TYV!uZ6jARZ9&RpTr+@Bw=v6(7HD0aXwlz8$~jOB-N_T zq<>6$?^=N7!*f}8udtcz`MajrI(##Fb|?cs|F@B@LtX{F`9w)WR&ODktLCbj zLy2*2Q~m6)bvku~@N_RAQM$u+I9W-?k2hg}=4OPJRbyzxi}&a)fUvaTz(Ds+LDQT1 z<;;`IhaTnE>0V5yqb)J9^W-_8M;a)u{P5w#N6v3U3rVOAOCHY4tjtGn0HKJzjstGGs?bObkFr#)uDcedZe;kI1EHIS`Up3$SZUc>BW$# z0Rz9{17FIqyv0m(9_}#~J@zYh%wJdt-fXFx^`WF0z7e-<;U?jaTfTrLb+M+Q9KDv# zkL9}@5~j8wI%=rW4c1#N?61|u`G;iC1J8ffu%2t?ug@)kd{Nh23=l@ssJ{# zQ`i>VB@e0DMdM|fzxgTQ`}t)!?k@W$$*n0P0qMAPx#W2M2GCiY*iuQ5(lRJXZ++M) zH$u#4drEsjD^tGdKps=G7VDOa6K4)hz31r__-|tU;hn<-0nC3u-PSOYt=$NUyss=L zvL>WGhZ?PabDPHQ>AC_9OP)^_yzE<|0Ez3}ybOG`vvOVC&hf-dQb%9~(%?$Dv*N9= z^lbfa;JJHfa;Rk@-+MJD%l`B&#|46~wOvH_c1sEcsAXG>^j0z~-^x9<;NEQvo<1?v zw`aj;csyT=XpZD(9a6N{0`q4r2)CVs-=An5`Lr(Sr*mlO#t`)PWS#$UoHl6Dtz5=T zpg;e*`WAf}UA2r_S^~X(1cs0&Av48PqW&uH9f3XZKg`KPk2p7e0JT%*V~gQ+DJf3+ zK}#}EFEluU=kvuDGyO#!uVzLJZaP0PNI5s}v7TEu<)=QUnp&xNMX%PXu@j{qRmw59 z&;P}k)TUi;o$gK2bkG(nt6t%sv5s+w@+Oi#jeX54^}Am6TpDA75AaZb5A%$i(sSnq zm@{u=!vMFw&}vXC(lt#@2G1SBaMQq~)@Gh#s10nLY5 z>1Uy8#8jcjOmOqaD$9D^{SURZOdw@arNp`Ee`ed1DQa*Y56!PO$QRHq9fE#1{f|j} zyx!;=C+LBBHGT{j$(fxPhW9+J-BC_-7dykB zH3#|-Cqr!2-(DIwn;Aahnj`gd;>?WG1rIh96B)U64w|{qb2uYimTT3e#TKNG z>jTDmP1NSP?HvfiW+<7TmD%q}Y)G*S1?WLY^;nQvXTkr6Wp}nnD?PjgS_ST1PJ@y! z5p5UM-%M$B@$ct>;J+||wR>zeHjIhEnmQ>=AvlW6C(7Z&cZ0tXB!{T_!{t>WLf=T- zzu!4qo&JPdndH5@+%v=G*n?vJ*#pDfajyL~qlF`=e*J%4JqLW2JkjfXfgHnhyS%gW zUd=!7OuNC6<6%`NxRl9pJkG73$};>vy52jk3FP@7);rG**yX6AfT9AT(%UJD(gl^? zG$JL0&;x{GK~QNLsSMQNRg625)zOSAta$DKp;H%y`J;?Iq&8DwY!vL zc6MiHc4qcH`kSX@)|@uY(#jcAP7G&#SusH?Cn;VqC7aUdr!R?gHdZ>ZP4~V%$=0+& zZj_P#EPj*9NruKOaYlv}N1xiOaGr@p&Vv(qn@x1_&dG9D_j%dJ#2DmTC1R5RH(6hJ zC86BDuNg(CUW8y~f6u^t-+{Hd)wlRFE2(GIza2L|Rd1X!nDLg<^A648-td_vUE7Ji zn!G2)ekQ_0q&TDRO@{FH!El*x7g|r&aOf1d%_VZ8BWz`d;JV&QkHFYDBLTMxkq&t# z6V`RXIPFxi@v{S&c4(nrW`#d4h*`J$maOoAXZ!7GDNWG5nSz5pLxL=N8U;eigDRu6 z(Jm(^Z%)4W>-vu3RK)|*n)`mcT9kAJeniCa)YFeIEQ^A@Ui7}+pL^=L*J~~7>vD2Z z-?CopbO=q9{HS(BLlM<^yHY2F4XsiqgtUOiNV##+s4_@$G{b|Mz`WC1qHK+HG~^!$0pN_xG*y=XP>iaxG`ne zPugT`np)u(nF=cuPhPDta&XWqa5MLFaDp>u6Sry1S^q$XHK9hM|6HKSxULHe-xFfK zb^d7yOLH7pBSx0cqI2B{Q*`Y)CoA**gC?y?8}CU!BPIP!LEcc@l#@v-LkC=YwOl!3K1I+#h zw4}&Gnz&$Q-=8u@U*%LS-Y=uyiL?T|B!Av(e~(hybRZucy|;8HHS3!)`}Un44362g zgn9u^a~&qD2H3nN=oC@?IT`H7Vs}=XYHQ>;KGi^e_hW6d-9z)){rdjb%6A)vGh0U@toHoo zBvPeV%(AIec$MUW4mw!lSgr0o+lu63=^zE2oU=;zBKUSOmeYeL*Vyp23k%B~DG{!9 zsuv6;eHcEhqCtaeP@)%YJUh5{qwo|H!&?aY3*VfxblbnaG>sGPDRKsW(9EYjVv{Q>C8Z z4WoJ0Y;A@vP)&D@IzPJ@zwSnf78|3>2Bej5j;|4dY`yQ|)u$s>aECGZK#n77JP@4x zuNOD}KQ#|DtF}D|5+87U%9~q07H_iAj#Gc(Q~Zon!W=JUGOh2M8Ii!|YWBL3L5Y%- zCG!|mbB1*KzPWz-#_g!N{!MI#RrAL0$=@@y_e#a|E`bxlDR=0!-}Uk-VH)Gv6*wZ$ z_R)|5wN#SxvtIn07jxo8GH1KG>VnpZRlk*O1c{Bli@cy4Eqn-t9=yS%+B?Dj1mMFF zK~{d?78WV!JJLXV{ftE`L{^Z2=W1?NSjq}wVjhrbs!CTRmwQ4+N#s|~5I%QmaxG@B zTh73v=H>1pn)v#f+b_4p7O*kw*5!g>Y9?iQ)Jrg-ppqNM1QZ1){}CSnL?EF|`zQfz zRF{5}^O+aE3(3XI)u@I=l1soopN7vW4ZrF4q<`IExFLkhX>5)_GGfXcljb6y19}2| zj{|3FjOL_c2_@*$a3ONgcwNu2BIDOS2d&GBXS zFLR_!S&*LhB(1~%>01b%Y-=@X{{(&y(4uA8^+Kvc-?ZRD)Eq?6lrNZ46}&(+qwxub zy)k?mM`|sM|LTfvA-*t@KpoaIEcdR8ie)bTas#xCzr1UT;%;Hrbl5E@8S88ZrabHi zY;vU3g)dsb3P3(CK)k#gFr$pF0@ot8PKM{syVc64dJnUg2RElxXNEU7f;5Th@=+)J z4#~&tvS?^tNg6xLP&YN0Re-mAit8x}KA{p-{x#g!_2>J?4`~2=J@8tcs@rZ=)rwgT z5nbn&uHgWuLPYCK0T`}ML}YGNGe-nZ$p3aLKeTIpl5DPLyDS42d8P2`RfhjY0erP; znX4L8xFd?f#5673UuW}_4{i3SUXR%<6$P5r);=Z|>%lDzCs&=5A5I5s_E*qPYW@1K z)$~9l)vAm7NEjib4|Da6LxFEY*C|z`@9&Um?GBavIAM%0Aa<<+eFH2?Si9pARU{FJ z=qXvCs{KZ_^;Aq{p4sHblujn3EPriYmA#Jo(uz7aC+EdK;puI(Ho-fzNuj?Ge2r11 z@Xp5=rpvU;7~!KD<~64o>Kqj}lYV_SQ^3Cx^#A6O;E6pmM?21m5=<~2UdQhUAl&c~ zndFx87XkJmz8hV1(x`vZe0PDZMFFWIE^P6pHPMkD2;AdOw-OobPWqsak;=YXmjU>| z*+_-kMy%EttUuelZpvg{sB4Cga^mS}(d??u7y(!b#5-?hs<8tev`sf1qGm|v`Xlla zL_F0tlgInfgulu8xoOGi7n*MS$dAz)k;J9Sa+0&blgOYgA(4TJ6Q=4}*>Np1QrCr* z^1L>18$Lo zfAqPq#BovI=G(8Sq3?Y^@Jaqgdk>RFes#o-w9t zlbctSLWlRQOEVCj2Kjc;Zap<_OdbQGUl~PR)Uv#;Y#$l*FF(r<`W9_7Ggm-jYsLwS z-0h>}i#a(EUZ0Nc^S+jxI9nIP*r$ZJvEVSW*m%-IDos(UH7LXb7lqlL!2FDR0tI%? zY1x7fRtf=Cj%lQwRg%}=$cuSbCCGyhK!jRzKrnIDlHbm=*f7PL2~)vr)@Q9uHkV{4 zZmOw{(Zj{Yhe=UVJsRa_SWM}h2ZZ^BRlgZVv=m3j`9GutY+?Etfl0Xas4%GdVvdt{ z>XG6DoMpL>+3>gXeG<2%3AcA0VERzik{xq^EMrMOXPn|IpE^)pspcM1xX)jqV7own zdxZ#JO+ogD&{yU?cz)0Fd%7TKjSF9^BhywR+}@cmN6Mzk=v$% z!i86p*i=MoK4R$rFMLf0dI-BcM*WZaVztkaXZGgy`0c$#-)$$``tfIZ`mra@+D_Yg z)l2GzF_PVoR^ve=3*;)_#bCKR+uVQ(HtJ*r99GXNpB5OTWY!dp*tr$P`YbYPo?yDQ zd2H@qp!%LkgH(Ca^dwH99Vvubo`#-TJQ>{SPt|iR5026C}l&F2HJT zA?@=?d6)d&aaw#^{_myeM|eZbOO(chagO1R2=$Nm2+KTmk^_M=gI;umlKe*)nEMW} z59!>5{Ect)TkGGf%=Vu@Ge2Jc>7Hpu+{PE+vm>^|K?$D+=x!QMT;bdZ5qc{`Al$5q z%&*)7F^K&WH7s;|8dHYxog*Gt$s6%GXOR0q0cq?0HDprFB*fAB7@kN9+u9PAaMP`Q&88mfDl=6iYC60|FG6=VpftD?-5%w)A}aBFa?p~`U8NEG-D2Z@C?CtLWjI^=9jD)RWq?k zisjOTpA*dfhLEEQqNLc&O=Eo72fggO#NV(k zjjrYk9O6CsK>%o_G#lqf*N;X`ljnx#FThIeq$)Zn&Dq3%E)BAwfIsMBwc|QAnw|Ct}|s~oYwvYAO1HDGVqJr zA>;dOSeNMCPM_4%p}sR2c}5?yKVZkhNY=yitI<616=?uE;3n}Ihf}FNPuBg)}v1(e&r>PGn~Gq&TgyWB<3$? z9k$m-^x@PCw$w9erx55seY`6ZsTFIRf~XJrj?$cO-}e`S19;lsKDMbxSl$b0LdSzZ zK5hCMf4K1$x=)l$H)c(795{Kavv=b6k%pVP}sCgOY+?eh; z6;2rB)xCw|W{1;0pXNl-tm%2Z&1vclD4bhV&fsq3&bgS&J%*WzgtMs z=kA9i0bNls>g_;Q@Ql3)&KkS@5%e|IfE7Q#Alj7lax?iQy=F5^)V`;Hrspa42akR} zMV1E1En2WBc=2O_qH`IRCf&Z+MRWiGA`ioGAasHYps z<=#Lb=YS%8Tv4hFK^jmqK6r6k0AX%kJea+hBGRJnPvz-D7UG1}ekE>Is*TLA3MQy= z&OKFlrif74C86$%^zbe`Td1nKr#-tU?*1Q_C|G;4i{yuQt3m0HoArHXj4DDCsojWL zoEXXR+-(+ZO-EyjIPY^zvu6aJ8u*kH2aU217m=6EiDJajnOI-1Z_-d+dnF2a292g)eYm9PXWr@P7pZ{@zbb z;brjw{k&(7xnaIyCB)YVZ{KcK&4|>XG&F26s?q0hb)0=gT&a(iZL59ISx90f_niNx z;r0N+k#BfAWT-1}s}qnnI9RIjD05jRCobjEXj4^9I41tdB8{O=xib>Q0vHA8%)aFS zMICxX-mk9Xk}^wPFC+H<`VcBnNKN;u65BeYoh-r1kq~sjBQinYVwN&Go837c_N>lv z&*x-B3$o0%H8D!RQhT&~EQDQ)C?M11^|t#kHw6<2b>6}6audBYwxsS;s92R)<15cs zM(A<0ch>6Aw#fBhUrTntcbaG}S!dlxKS2EF{LUYOpJD-PuO!!$L-v;25_-K-n!D9T z$>Mt3BS9PJfp^-MX+0nm@rpyCxQECyX$B;F&w$kzYY?) zK{~at9L_z*sja*D)%m6O7nsSHTda%R>oV>ru^Kc@Oq8y0Dr$CgrLS+o?WC6dQ6 z8~NIY^mYUkZnGnB{6a`FfQsyV?YKlnHM1fm&o9xi89fcI&r5t#bPSaea$!zwn-nXJvG|=n0A(Co4EUwdu|;_Dr&YcwtU9Pk8*%q38NGa~AepP0_+Nf!3*bfa{@Z2Oi~tda=uyX2JHs}A230n4@8`9B zmI%Pdb5ld{!YYeZoDGqY-F3-9vXCOwQJ}5?YTZ_Sl=@hRBgx08q&oJ7Cr*$DPbZfn zC3%sX_Dl1c7#dcZZBTjSC(iyDq*(37_5puG0a})9d;CBPBG|yEA#5b>@XMrf@d^== z&=&Tq@6p!N+a4CO`~~yjM#_ zT5B!w;DVjs7bL0s+>U5w2pE_n87nN3jjsZTqcm5O%cV#ozkggdNS(Mjph4D|VgwH% zOFSdaX^W7G09iwEi@DG&==g#-Mh0Rld&Ug}Kwd{)%FJiBjY%4`0w?hk+zUs%@`AhHO zXqTCd7)9m;0&oi1Zp*M82E0I>_ug4*3|$_h)RaNkgVG%4g;L@%y=!)azgRW;D_S{d zo-OepC=KKIY@oG%{MiJ=)iLs>gM$xG)(OH-Ujw-iB5^yi`Cm37d1ZT6B4WHTnjH0X z>;C#j<3Gb1|KN$9qQVyE!F?5(5N)!K#^5Pn+-CHzDm53)uO2?Oe~0Ph{eZ%y>06O4BqIobqLD&YUy1917Od5Kk#3 zIz{p$2$o~f-38j_>kY_mV8uzs^T6mRX#n_N(dxhHk%6a)9*vlT?Ct0JmmwSFNv@U2 zO;>IJ$NgBFNV&urg?gsZiAq^EXMA}}4LUsN99H9KPgHA&1pw-=jyGg8{4ciBe7sg| z(N)M*W_XeuRpyo@sAshU57)~m-~JkSy`k!Jd=xR{q!1G-qB)blu*NIX#>79U%8C8; zrWG&J-tPGO8~ql_@73dOz$BQlJ{$r7TYV|aLNv+-Q2fxITB>vQ==PiG0+oK=D#9A`y zU?#QlPtZh4z=O5n6Xa9K7-B{Jig7(}a*vWv%OLsM%?WIg2K+M*H>$C)SgTjL=4tYL zPR|afD&{kdY6+JT91}w~X3hhF!Z483e}sX0vPISC*=7im&pCC6z8!9x z4X#aL=xv_3KfF%d#Wcq~Wr$Lx;%@I5cii*UaTku5Q+PkX!!`owBpxP(>^@+#x5vpX z>Y#Pu#|=juI5J6VX*?N@kowyD+}G$6My17+!}eEEL@w3_hRSt(D5xgYdQ_ zm|aFjQRAc~1OkbePvGo?wfA0BNGt$X)>J>buuRrjSGwRW3*G ztoPof4C8M{?#mqiIKDu@5!36>vcx6WCpAF@u9~T5%RqW$FOONH3jtWwxc6k5nCGEZ z?BMn>&mQr>DRK>cQ$8$k0t$KHGbC^7{RRJ*&czvj^y0~eThhMlX8@=+< zb)?y6|LC0%!pk3w`>CC~ULO*<*9lUNoirFQpJ8v=>6z1(P2 z2-<_2;`=tmV1RyK(<3M#tB=M~t;l75O&;%@K*-r3Y4QWg1*11%**JJ-vaq)0uTpBC-MKu?0HCddK2)qf6D zZpkr(inM1VUsNegJYR6eHK%-i4n4u!k+V=|O9|{08PlJmoIsyuq4JxRwz`40I+*N! z(%3$VkiY7>UN2a`>XMI^p$FUt8l?^SW61Z$JUFW~jmvwkL+N#w_ZKUN?Ox#C2nGp2 zV{{{3|5zlwm~OD`l~I()JHE8!%PM{h>)f6nWc}32q}+0gxKJUo(Hx)UB{GYG0x*6v z+7yXDi2M4~J7DeispLS(<>B)_d^e*CHQt!j8FoG! z>D7*mj1lQWHQ(PDu4#hYs{1f`kudcQ-;*uQ)-6wJS;WVMaGexw2`LhHD!V?)b)uea4*rt>NUk9}r&8i7K~1YZKK!(%ixTBeJON?&BZ7Bv z;f3&POW(d37}NcfeoNLU=SAPcrgVMws9f;XEq;20m_!uy)qm_l)RVb$B{{Is{Jz}C ziU;%Q#ebCz`kPoi%W`kiG-8%Ff1=nyV}~hJn2s(L#GLIVJGCN~8znw;jk#qy>{`lb zte~HLLWbP8{jL2gIjm3-e4Am&9X6I6G|fU;P2LOupAqR!$AxbKTI}SWSiE##mfgj= z_4s-u-Ny|NO)Q)`3G}egFRTd2njUUoNW78x?NiVi`is+}wpA2jQ)O9GGMXN4`-6i& zwR+ou$&VV$O>98Vk``3bi@ZS;#MS}%C*`37+;d>8&ExWyl94CkvI1sd3Rr&cXJG#Y zgd=*}LxlQ1sB|%M)6$|LRo)8yqUsNrv5qS>`*Md$be>&adCQqhLOOekRA(0-*rrmL({bD}OFf;? zv^}Q0?-3A21&FShntCiq%^{CuBbXJ|&Siwe{(Y^|gwsbUW}wmZYr8aMC1c}J;|=uh zYBaThoWhpy#3s@KZ1VR%@U6!$!=5k}K^6p9BX9W{(>&vg)8iU%FH0gdm>@>gGnXYMlpSn&deP@ouT8&A zlG-b*HSg{lWoxvEAPh;&8ueGlZ3$R){?LxpN4KXPb`7;>EA_nH=6$>Uo!poX_&jiN zX*EzcaC#l|a3nGmi5LpnITV->VB@_c&Gs(%R;vhsbJOI*MXWM6>fOo^>M@?n+s>Mp z)*gwsG}?1+<6ln$e=zxLc8QjkSURzt_S7p0e>xAR9w}jjv7H&C67M;+BH0QX7LQ?#Qy>4UmfzoWKez_$Qmv#Oa$25px(c4?k`2nzEYlo9vB?s8 zw?Xykg4X60u(y=^-h6Tr#Bi@9Ezt_EGT_q+(J)y5eF~%QiZfW6jixi)G`qzvKw#5V zg3`@%ZhOFVhQB}QHypBf2&evMPG3E2t#RL$U%Icta&46+YRgV&?6_J-ozabRF*5>r zGxHu5A@-x=<9VI5{Jc7}ty}Qn@uaaRzRt2!wEI&{(Osn6L*1{2ycHzgypNX?B~_KI zUD{8khUu;1UyYv%a&#K2Z2dFSc=9O|>%^?Sw&y-$Uv=5$X_)D;p(}fS9jyV>PaX4< zinvqSO_fnmem{DzY}@0i3kX6F1;yA0Typn`9*EPRg+Cad6wg!~iDnaZX5bnvDZLkc zTi4!P$%;w)SW$+Y6TDW7cpMnrZrY1RuT1gw7o4IGGN#nbUAftkv8CV%gxJs$pQ-pu zR+Ql?BD2Dr7O_YPeYZoKJ{?ArfYq}!M zch*k@c>R#lpW1b^+9_K)>Dr~%ps@OOTO;Iq%@X!#WHIf8iHZqXrEx{^f1@0l{0{ff<)Kj?q?eJl?E4E4hC|cj1A3^7j59o%Q!Jpn zt(HWO!=rAxMRHB~Q#$v<`;X_rl_PkMQ}c1nrZ9s|_EmT!u)p=FLJP$<^sz~&u!e}L zU@ot_Cl$r-Ev4hX*KwTd^{=R^;3ZDXWYp(dfHw+KX@b$BW#5Pu>N1WV-CJ%2S+yl# zkZ}i&S(Yr;6+xOq`|7GHY_7XSVy4HzE=zN5Ds+PSM37^~)gD^(8$&L59n%dtschD# zBo6^2@cYrw48|%zf~QmR%e&D7!r4;a!{-&cKrKZ4GylOaz_i!?pe*&P)5S^Ldsk!$ z=-$xb;LVv!vN0=I{31nmy5Gvxr*YQfxy&7l1YtP*o99d#LG$b9Pwmj$af6xGq5r5-Ad*@P#z9G8pfqyQHKd*KLdgM*w1ibIccltwEuMpOwf)NyJbyK04-PqZ=X`Obino|-L#Bvg?X6FFug?dM^qqZb9;)^uc zp-vk|e@#4Wr4|4E#UB8hJCVh8d;loDZwBy1 z>G^Dj*bfI3+nAa#7$#P9m!%2TRR~yFXGCGuNOT7{2mOX>@Ih{SPSNtc2*J0CQci`V zFgbQ3vMvV6xvPU$RtT#>a3yEbgLiqG{kM4rQ**^#JP5S2jPBDK+tU-9Cs zXlJHL= zWq+$y&emxU1FcbwKG=Tf&=?6%tSpg7Kuo~6n7#zV$Woy!2uthr;h(Vct0I^i>N|YL zbug5vTYhsE3BkO`uOm)EkqhQgJ^Y@tTr)G}c>0{;idn9g`j8Xtngn-$zyA1z{TVrr z&@Om+Y>!39eVZ%wrOfNr0*6{6f!aEP{Cx%U&8gsDk5v9%h$a)@b<=lAD18iNg*q)+ zOC4}}R4jwtf%(JS>@Q@TRTL#?&m6m08(qJgZBh5mx$ZpvD&9}-73>T5fCm1stVZ!w z9Yd!jS_*s_5VKyE-`wn@pEJ>ikH6b9HlbF*Z-{fg;O$_J%CdpU$XsTWCZOVb8M5q! z_+FU+WU`KBZKV3;^Hp6PtJx0DEF+kWF6R>?B)|oB=FN@=7M~gVu@Cqh8=Xfu0+z3P zGaEo9DWjxColTb_=>tDGGLnU+yc>@*Yn#OOL9Wn+A ze{-Z;n{;YF5nGBud_JzZY+xo#hz)w0B|4tAai(r8*GICt zqXH$$n3=?yX+`&T|C;jc6(;I3?~cgiW#0k#!qUI=&E;jjE;CUhm@&oqC}1Oot9(f2 zv~+Xv*09-b#7ozkR|N3pnfIeQkZ0(OV<0>#*PL-un1b{s4HkJ}Rq;t973xkb8FrQ3 zRPSUpD^02wr3E*bH9%{>C-lGBc;9&}2(U1;Tk6hkRUnuzWVZBg-SqI-$RJh@&^dit;KQV5oF}4ibmRfcE{XeDm|N3FVd@#R{{_*>!=PXoSjd+-T z{z{h;;bt9gom};$1in@eRn@*NxfaKFE|A)tVSWVGq#??{rWPM?yA8!ZxntpIX#(jv zlGlxW#asA{9BGtsZBS8#urm8jO9g%BVHVCQDfCC2&&w}a-&8UAe@fA^2S%)$Ubxyb zVhQ@_fhg(QH(PS!6O+~zVZ`y@oiM;sm;<~qaH6CKDW*lQS|Fu4mV!hu8IYqS)a2&aq$G0#ZOd-< zk>(yqNh1H5%aP$fb($cWGnJ;7e7^>oE+_|wAC6d^uFRALMXcg1stkIRKjM_p*X|Oq zUFMxWI)+ve+`EJQJX`%JCr5ZzpOUcDKfl7n zb4QRMsGmu)7o#6O?Wwn;?DnH!+vuF=TAa2P`~CL9AGrWkq*h}S1g0vp(PmG<+LCihiJy}wZH>K~6Eq=|8{X=>o&(5LyV?R5t@IbORD0j^ zsl=Oos~xAE%%fkj4JpeDtrqZT&;I|XB_|0vTr;p7UiqG)a_Lnox&>Jk_8|>cfA*wu zLU6Q?PM*2aD=OnUSfCplVzgV8FF}5kT0Hiw0SrXE$78>JBO_27Q(j<$@jij>hK>G_ z+)cLdzOzO#Zfw@nY!*oUa|-|0pDU?AzDHlVdD{pBD|zj;C)HRal{f@WdcAf?^Y)+K zbZ0)Qleb=R+~Pe+&vI9fqk~b_tq&iNTZhi3@AP#sb1i+Pq+HTJ@}@sEG6ecU#Vu9_ zzthFFK?d)yA1OmtDVRHD(I70uWvXb_7Z|AQIlT}_YCW3JZFLl675Id+cJFJTYg$Gc zCA{jlHpL5_awFGk-+mP)_w8?;4N+DXW9?tiuLr3pWFCk6`ZWLL!VD7-D-{=w#KS~4 ziBAK?Tz(yTQFB-{6Ps+Gvx6PC8+!L75-`M4ia#AfWTiT*nja z2+N2C?we(k(?GSdC+l~rZSo8-Y?`?SMyiQ1Nw@kVv*%zo3!?9M}D%FlInSP~#niL3() z`kM3kY*;?N?v#E7EQKfZ0mwUe@2b4>ZSrg$=re2rF1$hhJ<6-z$oxXohVgo$WyPa`%zluwRPmv-0ssFDR!d-Y#GA!O52#GaDU; zJ)BBU6A#&dywUXHqQ=EH%PJ=Ov0JqQN9N~ag$1zjt_<<kNzKl{f^U< zVO};OBg8DPT?Au1?CPGX2GbzK)UoNBnnO=Ff;kA>s!m=Q z#zwQ>-%~=bl27Ns6%dT8yHnkYHe7|0&r!J2l-*~OU!(oNDJL$dajyEA1ej*QH~PMC ztXO@=^UR>Wk-DqrZ~AJNLfaOGPc2+HKOJm&^EJ9XBOH_nM}9KWT-p#j~IZI)#SGV zJB<9x6Y?y%=IfNs-dbb7Ws8z}MTI@A(5NE?O+DvwvXh~atG#!9)q|u0#Xya~Vdn+% zK;s#U`H=`4*2gufbyX7Ni%-hAt?vJKX#Jxjw0RNW2q7%6{o?Z6G+*XGw_SuPNTiv4 z^XZUkV<<$Zx*8!Yv4V~FllxaIVP8P=fK*>4RtxNdQ4I;1SpHP%InJ#1#fRIE8Y)@E zokG5ckFg8p&Kt!}dCfQJDwPH(o0y$vDHbQx;{uh-gKhjIL^HX{Zp|L#cn8q~9JMFO ziz*BJdy09NDUX5l%lV-!6Av6RQyUI7+>{tYyrf08b*4wcMIMgPMD;fRBR}n|ZJBXI zNTR^>voc1lzO8-5V;YQ@70S*M7_2*FfcHZdzhk%{G@!Y!NPVW3yweP1SUZ|)Rvuev}uD`c*emj2wYeo(l=d?1ky?kM3U)>dRagCF4jquxM>nD{j znKYRF)T5yO`u+s=5utiYh*uG7^i|L6HnI7nIUOk55XlY~d>3iTxa{2pYWKF-Eyfb- zYdu;JMLFb$P{6i5NG%HbKIZU!L0G!vvZJ#MbeFx^GJ0Wb062uc24z;Zzu>G$wvAc- zV;lajtEUJQ&5YO+$Gzb#x?;Ta)>kxniqjPPkRL=OKL9+##l>FlHgn{H2qLbC)#VPyV8yn4;ZIl$mo13r_#Se6KEoIMi#i5*;Ls0 zhBs3@NC!Tfc$Vct;3q_52y>w#J~_AEv;rb^l_ugpY5Z>v|LDmiAmc6}Vj;j5lzO}9 z*3t1si9^W;j&+kF%BxHk5`c7<=;2A|C%yQ<5u^JhPsOLsKZ&;~B620~*kqjzyadi0 zIUE0^-|=pTlUK}Pvg;FWSN&P-BBpD8g4FEtTfPv?L4R*9TxpU}tA8yUX*Rzv0s{e6 zU1p|A6Y-;;o>ks93wM1)t*e>yEIDHhHs!u6jC$EPJ^I`|aMsb%hb& z^B2yIUp_A?90z7Np7BrWij%(zi&wfTx}Vcnua|{_+BpU#5|8xP%Cn|UC)^YnBASlQ z)pBo8s+>e7lLO_ooyojUTSuJ_QoAvm=ha1X9Y=LazRqyMN9N2Jzsz%Q8AnZJN=+dw zYO9#J>LxO<`pk0v+!ani(%43H0E^jWN{9|X(i`SR{D64Bc1et zQlBeYo5we{@j1VYmpvfd6Q15NprquCGhdwog6z@FR;^L-rJt`0g%Jt;1j&T55Xjul zbVqR_MM^P+8e86%o74Kfv%dRYAI#iatxZLE&4TV+Rq0TUhq%Caqt*9JLtN_$tkLjC z>H6gt#X5`Ur0ls}NP0YKhmtb#$&inamLYJpPAUE&6pxu5nDKVd)vk+F4Dl1bCY>@Z z+g1|4C~ZUzX#==7#zzn!246I`H~hE1LZsakVPp%C*SK74M2y?+j^sl?lVt|&;%7$C zE^M3G{G8~*Sn!E^_m$n9TU!-7yPEP12e(v6>jKSINJ7cjkgKOdMYm+81zwq0&cucW zIZO-%g1$+Ud|)3gCrp;Ou;i49?R|biM<->Ya=AMVcCX`J#{v%IP3-CJbO;9v5YTB| z_L;dCTo==$cJfLe;^_?ACObR&;5;;^t|RR;nnvsYuNZHI`Y|2USn~TDDPDAf|F!gz zm3J50eJuJy1Fl}D9NEpO8KAz5zDi3Q9|+4 z3J$t1p)35WCrQ?K-Z>O5y3+pmL$$3pE`-9sekUuADek3ynQb(t4NOrk{;rEX)fOHd4|O zmSA(LvQ5QLV!Px$5F9)ZrgL5HbfOU@juPjX2Py>tsx4uWUvtafD$bT4V`SHSHKFN- zGY$=I3oO;#{$zS+JE-ukZ}!8S?W6aRTx}1I-)8z7yQh{aAGw12E_VREOWRd7ec+SX zf7L>4f-Nw%w2NB^s5UJPXi%j#iyhf$Xwj?L{#r}=&^iWano;E5u0g*kx}R`7pY@J& zG8?R%^6SXM`bAUK&!KdwZ_?K!_n;6+i*19nyvrZE(x(Q)8g>cV1H8zwltcG92ruP^Thh#K-ejF_x0d^;xUTC*A}XKxeDx%Q9CwFv=x+XP)3N*gTV}JL z1_m8cdP8+isqwy&+;4ry=mI=7H777|d?16m#46eG@r6~9@|y6YM|Rai#V$#tJYEl@ zq7G+nb>)L5y!AMFsqLNei zR^zpfzP@du^&OoV}AU>|CFWUvcfeKIpI z^^i-|1_^D*QpesGkwXWYi=+kDriAAzSN$!bF_c`U!TeQIhe3T1 zuofthY;=nv;>$>8y@Ccof{gLdyuy~Rk$~`DGJMOIYbQEltt|S%N3B4qm_1bcJ^7XZCLNpQRkx%RE%0`p3hHdfxjCU^)K5%!Q>E8 zmrS{P|6}(*dcM&oPSV@M&0Oj)n(i5~KXLWR_e17h!KT)G)DZ;AKL6Rf#oF0Aw4sYT z;{$Hpcmc6^tD#l(_87g3v^}u%mfu195MlTnc)5xeZen?7cH*+H;{zkfkD%820ujL) zDx3tR*Z;0-vT%E7*f;~Ao07eyD!bR8G{=5s3!%OCBBj5qGAF4u`_d{B2+w;kDNI{)pyuK}|*{MUhiMZzhc z3dPG3^5G^P)dT2V#Oa}sK@_^g*umQr07}$$^%1_7><6?BZ412lLL-c1;Qj7-(L3NU zE3m4@dvB(O-siC{@$@jAtIx6>UNg;qztBb?|N7s|4Bj0&}!>76i z-N_G)Nb}D5zxEVN!C(5i-!Aa3Q?H>WjlWKsiqo0MIq|jt=Nhs8^#-!5LBmgveHXK= zUm*Dko?4}qWb`6O==-ZV`VBNy&sorU{K%Vt90ykJp>el)>$!C2K5Etur9>V{Kz`JC z4Q%b3_Pn5x`1tbSVG!{p5i~xi)ZmhD{k^j2Z5<1gJQA^U>n|^tUkqJMw+=3y%u4A; zmRt*cD)O%T$f+ck>sq1vhfH`MRnC@ctoXp~G!B=h8>hdYh{)?&9QlYF=;`5^D7ohn zZHyyWm@mmz&a< zG$io(2*>>{QX^OLaM!{9thequF(-qj(E8(Vsc(GYaJ;szPPXFI+Xlno{LR=u z0{VSxwiqQHT`XmohLi_1w`x8CxrFGCwvW> z-%pwd3gm=Q$mXoYr~iHVKYC&J!zH(Nu`oA5Z`H3oN|jO&Y2z3C1r#LhAF(!r*!2$DPLChS=J{m*_*G7c~oL zHILc{pMx$04%^LI+|thOiEn)VOVwVD4fn?2NIsX#H$t6AQI#`wI{Tby@N7uG-lUf# zW*O%?q6hKY2pNIvRplv#h%*$&rhImPv3#yt+Us{#CpbRTnKO*uO0PYM8HUVEbus$D z27YW23A+)TwtX(qdizuU!^!9g63uAuFYhbv_<0NWdhbl4b}s-tB$-Vz>X|Na!)$3#V^c{Zf2dBFApVqP_D#mr*q$ zg_bk%$cIjpGe7{+qr4K=PqXVe|B89}bC5TptAG~R#3Vmx9X0pJMXiI}8fgrVotoKR zpbHvEwkX`(5xA+Ot)WL9E2k|7s)jrcl=yRd^Uo+=KlX&LU!jy$dZ0UMS8vAquS3!7 z=hj^=9#7GG#TbxF8Uxum{;Z%kLjS<4BkrUT5?EP#cdA(-~Lk3mD*tS^(^1|9*BihOK$a0A>YR(O3MxW24$Rdx63W|^X z$k%^nYbQBhbJW87_61*>v+pR5b?)P4FTc62Io`NZ2pY}p@ZFhqwk>W2ZxJj#t|6=fg=sOuL-&}phH_$qkh$k6Ms0=`0yLwL;f zXA{({aL1UBmX?*$nkfSK+mfcH%_lL8-s=O~gAMp?8ssMR`|vjP*Js2&eXSHvGdq|< zJW>X#f|MB48LSj3<-fT=%J4bu4O!5Kc#o+6+9!3s_tpdk68tq!1Bz#`k(7PedYrbk zQPu^qpst(Xu@^c+1o+5g57;Wfn9!wKL2%!-tsRy@Y5V|xzV5`i5*?hAU08Bd-HiEe zsrWSdKzAY6UYf3K7YZ^*D7DWL`u}oWXVwbq5aL?`uI=2e%KmvBEXs?GR9>i&kX&ck zdgr|tmCl;eWVc%>{}lH5$Z98E-rY_&XYD|_9WMbCFecfbvD*sR)0Jh#lB`{y)Q@@D zxvuwAX(hvV6=^}GyLGi@7;%d}WN)v$4_lq)hd|vZ8JF3oUf{i`b>HDLKXvOTLWg6b z!!@cLN*9)u?V{n8tq*6HwOSkQ!8qhO5x>ZSW{+$suQ+d1@lqi0C%pmM7W^M`{oh}@ zPo5)Hz~TNW+M-fUK`1YcT4v!j)7{{MU1`cVkHqm6xHHzE*%@Gd5NW77!C_U4x7<<; zE^`v^9cTAolM{|~W#75_i-O?<7apn5$eURg(7Xxr?>K3?%_t6m^+n#$e) zN9=sC_31mhJr{_zaM*uxeEzFBFM7V3zKQuGJ4TT2HK$>w1`nZV&CqH zEu1;eM_n65jT^2crKfvEQd39Uoic51X?^oDnsJz}3PK;r%DMSB*3!}SRI#GPSSPmTv>zZ&I-wB~f;@&8wa;Quo)-@??FEu@>oK|j>g zx-Yu;j;MExG>?pLDvdoZ14)3h0>hU)P6zkk(FEp;a?qb#f6%Iib$FBTg-=FbJiGx4 zw`zx`qWFY~bh{+y_3Q^X<}vD@;k_5JqBLX`c@%Y?q-q5#?7?LXLaMMW7DJB}%Vc}_ z+IJF;_n@b`>yK`6CcJK(>4d4!a@j>Md(O6hJ@TrssOb3Z4B>Y2{B5P>?tNgD!!768 zKF`w=wLP`M9p#v7TG=Jwu&h!MXb|W{QTTWsBcW8JS_$}xkKa8#T>b|ouVC2X-KC=AYmCiNbxD9} zXV9;?njixA3NLSC;}@3jYVV=_n@-jKy&j&P_a|VW(TbPb4(&|~xQzHa&>H%EEBdW! z0y^N335JDMIr9Rv8^ri5PF_ED9|C-!)&VilaI9V|2KUO46R5)v>LBBKpmEZ(p56sOE4-g=#M7fEu>-9o3<%7NY zev-8Vl^Yx4J7H`$`8_&OYk=(* z$6Z4UiKxOfQWXyspN~<01D`@T;0|RJR)8Z!c*p&o2agsVt)=JR6v4Hv8_w-C{vxfqVbxSMF%ei0ulQ+R8 zCh5!d4X-AHhK^40PP}~0mJ{w5`}}{uFaGWGclu=oxT~#?1L>;my9!ag)?=y(!#}QP z+wL>9yfhqy?>uUC9Qn%I2PDX8LG|we!q>bUd~Pf`HDt+*S{;p74jPo443Ww%XZHwk z5Sag?vHjk>$IydDD?f8TbX!SZlXF;lkmtXN^8ZLQL>!RbR!4RlIb5DDsFzh&8^XN& z=6<88Bbnh!EURb4DWSfgvQ?5gu}zATOwufM60ENcmyTQyXrFSE07#0(f_w?;{6dHZ zVL8_z$h@gv6K{p6etRwH$^uMOzUucK_x`%|sG(s&kn{6y1?XlkCFz}7QSApBqh~|7 zV|&IXYWl;mCTSvte;=Gzt6Kx z)EE~HLA?Q?OxVwiCEqts+CpBx6pk(Wdul+*nWMwRBLNZy9WURb1~oL!!&J>f4$^^R z^4l$#9WQ!(W-vd#iod0PD@j14oqa|UIp~9O*}Ft22ZN7us?NT#` zXBBh}WR{Q82Hr%@H96UCsTz3V@w z3;Zu>{)kX9H(w+8G$lnaM$z;Ieco@Ty2|GNGx+~@70g=67ym-7D-*|;G-Q1$OvtxU zKL)pr4p^)`P_6!KSY}Dt?o~m3X;>a@k=hw@B6B_4`*%%^=@`$veDOVm=EpYkSFq;K zW&_nqg4kJWIP&MgAhx9apetJ5y;s@07VZ_nTHa+?er>!EaBX z2q$E?aBW^e+Z5~nl+UUQ`=5&HF&qY+))jYDzJemxca$NKcB+jHTU?-AGLxMw`d zNLPegoP@m40>gC2GI)_#EUFQz!w?EqR2|FZg*|}Pq&+XTwFq5r+&?=p9!&b~3g6)o znio-I=%6q2yIOg5W!wPuX{9)KpQ?}4E|GoNqSXS|2E(r+(=q&^Hs8Sw#n0Iy3U9`U z_{CF7#Ru0)VE+6o(LoD}AM!dpBNhJ~-$WcHju#3}A6n7(#-77l>w5n( z2Ely5Jk#W zpQDBV@9GEO)^nkg?>PZk9-d23qF+(Y4KpUC&RSBh5uu4yh6WcqY%ZsJ(4wUSw<0G# zGky5)N5suowZR>_oaB@2!W@T+2Vim(hRG$ZlGVJ_(gsh&ow$s!D>~ivcH7CJ=0AMU z_ek2icIWUAMrpPWba1yqW$^4VHS5G~%$27Mlev+7wgJBrVxo;v!V$Epv3elWMAUP4 zP(y{6!B5k5pSj#Tr&h&LI6P)h+uPjF)=ky%pk|TvGuTC~UPgC45j%z@9`T#-n#=8% zJWbO?f%JOaQg8R;#O0G*>|TntX(C{j%9>L=&a8f9+zAJP9+tbR!l-=0&KN-W=$fZv z)f~sxdXnZcEUygd-Wq7ZuC`Nz=dfEKSY`OhG z9&|a9`*YOQ&0n-trjf8%Zk^LK!e{H3MN- zwf9{ci<7^hUea`~1ku|O`5GNb3t&b?pu`i}?|}zZ0Aub5aZ>`jYfa>S5tpw;jamIp1BiQGD&d*%WkxLTO>r-*56zN`b>aCZw&QyC1BqnL>ar;4@d zZ=?dbAxU06OY(zgc^?*>NLPSN%8`DQ^D&#OJmg5^rhEC6HNcA(oB&P)(0h<%bJCh( zn}H-D;?R~EB~LeJTm5&{CqB#3fZU*%oi+8z#h@G{V&4w8oYZKu4cM=lbbt)0y+%A1 z4|}>Weo73`pP&K2Aq@sxQHkmYPdp+FAULKxS$~>sb5X8@b1t~-8mg5 zfye<`44=wYW1@C?DT*Zk3Gc@@4j(KW)M6KhEQsa(elG%ULtmrl8t6-xNUCqfZZ3_h zFi;9ZU!^&Vge_ZnEv8)-LT^j}VUMuoYU8GYRQejs_3S9YpPvw#!uVd8AU=hOjcqh7 z5>fXvFe-YF%7O)jDs$#~4rob0IDLF2a1!8H3`vhP+%j7e*+l>Eq0<#Va7g3GehA23 zt;54AIx^srX0!`vT;s&bm&d+?bm_RIkQ&v3fV*h#b7@)BUw!H%Dr)kQw1qVQme^L9 zHto8P6qrr$+}(zN*B;nquIO&R2Ry8M!6*i_;&X-|IZsqA+1-7se@|R^&_2kPj}s|n zko}a3Z}116*L*}tdcq!ArzfySkwLn8+za9BD!J}Ef|JW3-|Z3yu0&uFn8|7Z^_;8e zAZ1WrI9MBsKWjAiw}E8e3CBhYY1bST#!D}~0-oc_BgE1Fw{tsoOlA)5dlB$r*y`-W zF*Vb3jFIu{qnC>hHgIWgsUGTo!OvA{eTCm{HS7J-Z)qB+RtWI_J`8Cl$W+uSbt|_# z^w%2lPP4pJ&{+wz#5O?}u0+2g!JH&EsaA!*`%4@miKVYlp9WlIGiAS|bmdPCozEt| zvaA4<{~r5AVegC9@U2ghIXL^$(vLne`kw*n5);ecO&9VnsE{non6)cRN`a*8qY;Vq zlPpCABnV2rW2fcOx|qD}t1DO4u=ttv&+;m*^I0&Ms4V*VCJ6*%@=?#yOUZf8z^PKAC2>-fz z`>5`@@r-#){b2a4D&xd6RYLnZ2Mf3M7+#(1Fjq!Djyq{Q;DntinkYLdnQ*`vWM6Uj zkoVqgsU^Mz4E;d;Gy`XpPk*g^lSqYEGksH})|78`j11277HOm5iKFbM zY%adjqohGjtXE6pRQj`L($9O>FSCDoNBL$IZ#-Ya6=f(*|B@c@dGKLyO8F!&PX}k9 zLE(OF8A50W(&Ks*x0N9seZI`$9$hr*mU`ArFc=QOz9?rRQh%9e{_b`99KvXQ@_5qMcG%GVG22+w@-SRF+E03V%$EPo9npvXVlp{ zV)TRlOjmf2YqxdG0IkC54Y@QTjY%!qoEk65X3@p4d1V#Pq6!NJU&#gypvX?2Mkd11 zauNV$%j0e6#vw&Y?71U*tfmuiR%)&5k-rZzbG+X-CWEk|R6Iq(|A`cE8K~P1+8c z{AnEc9 zf)RLNSBwTd)i}~FGJ<Zn6zqjDCc{}H zAw?U-xXn~^M$%SDv7UfRV1#e6(*x&iHi3i)o}TWBlOC~T?r;|xYrz)w%nBxgCE^wV zOyx-5#9mFO_fvii^jPFp9>$w&i80;o1^1$8_(v!DR^P{qYiAw>aSHziOY8%z=p`H= z2fOVmOHSY!rs|@#p4zETpr)ti#cO*qu0LRQXRWA`vuR!H99P`O>+t}QH4^ad&SUM^ z;2g$Xr0y+I1_W>c!c$Wv9f5}0l7E};mT)>wj96}w+;ouVk1BEcd5yQkWL8u|$Euq8 zE+nsxS_#%p=M5p;gfS6`O`>vAjCTAU~cpmkMUz-q5^)kJr zrm>SG_l!hkcH67plsP`r6R?nybH44Xoi*iCltcfWTVmz7r9uZW@Vrxv#X;=l`{**< z6EW=6WsHSXi>I#X;(MjBR0EubWkKGR`6DrHv%T9B$FzvdF1d|R_Ie; zzm?9${LE3{Qlu~|f_|vMYkHwHP;BSZ?M7tr&uQoWH9Pfjb^G-s4R)BcHHXYu-b|Jq zYy|K6PM1)Eunq4irA30<+d58>uGQbMAy*IFhwGb}odhq3xqQ%qu4s5|jW6Tz+LY)n z74M)0;(mxX?e5A9Vk&S~e~lzf3e;{CtsX4fqo2Q?Hk9iV;NxxsZYn5pwBPy|v6v%2 zm+!}EUVB(xFT4nh6kaAT@0QwBZr3SRLx5SPUb$J7zFeo|4WrF);lf0L6 zw(H9dcuvrA7UT9OMQT<{vErkwiP>4-a(=|io^_lCy0FD}YkZ9g5uNa8M3|u$~{B*p_#w43S=bEVvi zIEksZaj5Yh;UlmD>5DqqyZfNIffg=I|IlHG#L3b(AQNq#Ag$Cq4iwY;gunI(QJ#rWY8%GKE`LX;n2Ujkl>>5O3!eVBDA zNratZ3&023cbt|k2QD@>{#r1df|cr#i+Om+0)NngBiA>A!|OjnJ`Tc&;vJ2~Ie zJpUA$oqJr(`tQL<>&HlM0FRoswfI>2M}aRGaz@89%;nysQ!%LQ^$+(*7XmD0g6}_cR!u2& z-Jah*Y-&B-qSRYJH-Ulvyp5jN;|DjFQt0YE8ut(fOBI=$Fz8B05U3?2`j$(8Z$#>= z9~_KAXF$V5fGBK4neu|aD|ixAATre|0;_-av1;{{tZcj=5qLPnP)If}>-Hc&w^3bz zz}-WuP}_c<(;rIR2fg};*dJYZsaSk|KNskEECiqCZSHM~w zc&n#+bknZ5Q?m#`Syeq&+Q}=zekN-N0I>o0L7iHsWX?;W5*AiKt6J8kxLK{Sykv~e z?;3xWu9dNtA!K40>5Pu`-|0x4Rq-Zn+tyswk3XO33o3Y9665f=#v`$3r#%4}M^-x? zFuLxo1d=jKpy~ni@cm&~uGKrAOFuHRvDob^wP;F+;_F0%q7DFxYVV9K`b4|}T7F2l zS@gG$ta~pWFXBaP&sfL`_*S=-y}V~2cLK4|1~-+A+}yuy+(4Att`wh= z*z0>CbJU%D(`$E?8RSTjnA%Xj~MM2@CNT;U40F)btmNzlSlj+87OBN_*4t( zRq=9mY?eck^0m68$u3~&L5Fb#e2=_eL|=&BV2!ogM3H6ZwD-5Vc+;+Uk26uROSTA7ebMUBgd($~*AWA5c-mgeGnNqcOu0ujf~X^m))753Fr4&?+3gbGib z#1!gE;!}5HXR9su1Yg=?kI!jo;o5)lFRcLmVb)KMc%aSW5to{~GYFYx{k1mP{Gv+5 zo!jr6*O6)zFDCwtRMqdA^zfvVOZx@L`<{00sh)AGV}w4E-Hlie=(_5A`uAS1(%Bs# ziNTSD#{3|gNKsZs6}oP={b1|oOGm8m%qPRx%QDP<4 zx;+q!RzOSe^ot2T_@9zx*vQ{Zua2Qqx*9DA7e$ohiNg(jiRkc_N)3r^$9kpp(y;|p zGKM=Au`z7;uq$^0(?oFaVlA~DR@{&-X%IZ4P(4qFFT~mp;v+tewr2t%!@X7=;lpaO zBrhn1p1nK|?J(0Cfs23;x2C>6=ozGy1Sm!gBS=lE`poJ%eT}U!JzGp5o$9cwFQDzX zjkgGDzs*5?`QE4Dc{Qd}qwA!0AF(<=o{|cL(G!E%C>UjHZY`(U}EE!C`|)9+5Gi8B!W4qNetM5{c=S9TM{|uPQBP-6LGk=yGR2T2Ee@n)<0% za|J6!K+li62)aXP@Na>#a=o-<V}CGBW;8nN*27WU#ATMugsxz;0QSq4Sut|8G21rns(di%8oV_>U;L9mUFXb<$qp+r zCot%Ayy>&Sz{t}Prp@Emq1o+*E1#vzwVsWLX9qIgy2@%DfwxqszX%&pROr#Bye-Oo z%4N;QVfU(DXMDCa%ZA|4d7+p>Bw zcVk`(C3QYFsKmZAsI*m4pf!qoA&OS7n?cp(UA1&{kY#`^B|=QD@6b$1j$)3DUJzkl zRMdRXGrVH?SA9pKmr%Kc7$?=dJ*@`c>-=o{xCOb8)ado96mdwPeh&V^XKruIAhuE% zHXd<;$hDO=HT^Yoqrfu0TFlBhemCelRKLeIrzM-F#Q)_7zv}qt?{u~x!g2-!Hn-;W z!i6&wZgm9HAANaP#HP3>cAfIS;3TCeLU*;LvFr9()Ab1PDvbI!=9fS0ZShBYQdhri zXb0vIclZQc`2JDk3Ft8QSyO^7k8UUv@(4$qhm=cwG6%z;rYXCsuX*+|Q?h&m!Q67` zxRvUGI)q0Z5BM2>JE)C=iweU(I{5|))X@z0;lj3cK)-EVP5$ghdZ5%ZAxT>8qJ9L+ zE`zkgupVDPEdOOtqZQe!3ljc~k2~I_kF3`7Tb!x={`F8g(mn4f>CND{ixexm%Vuug zJX>vA6o)}x(hdOa!9ag4{S=d4@*xKx}lO}RGiW#qz%AEW9msE zT*5ZuqnXa^Us^V(;r3IUV)KamlsZ9{XF@SjQ_RbS3-?VWIv8v6gYO8awtHveKFKlzzx(3|F=gb*G6UsKMPFbZdr`>Mlg7zuZyVX!(Jg<@@vjFt)Zg}?{2vUP zp3)etNVd_-kdKcTp^ zg(D7GlN!QFM%nP!UG6m?IfTt4vA=WpvZYLD+K`OQh3dl2hfdo}-;N#LW;lub-eccu zfz2fjvqu=?SuXGx2mM%B%pW+8YL^niu2faL(E#szF&==nl5A38n^TdUA zC!iUQ9LpwKqLtG79f~%!FG3`?*BE-IqSZfSwbrT9#hzNa4|C@VKQ5X)n;O%TO$G!2 zISy5436J+i#fHYI`Mp-Mea(b1LY8}(V-^idCd^Y#yIW>+?fZkh^;O`pUAW0U<{uNQ zDM;&62PE}#vSG{Q?l2?s!){ySOOL{~6Vr18W3~i)cg33!LX7~FZES11B-vu*f zih7Z>W37e{c zHY=a|5-j|Dw%#Iw?v%jaD4^%G#qn2fpyV&*)(CWhMDSe3u|!5J3`p3Np4~T+LzN8$ z5u9MJ2c;Cqs$)>i3-cWZIBz^!X|;KJE7PkW#Y*a zozt_4tdUSq2rtHL$AB*E6pbVqbWryy}KreGJ?mR5-cvneV184WoINH@GmD z7Q;C~s(}n^J<2HDhkIi3RDn~xXu^J#IWG;_*0?_m+Eo1o2xa(j@v;HJE8A%3r+Q0} zYVQ@?{2SRs9u?q^WIuR8uyI~d6->uca~DF%7=Wb`0;?nzL>rJ9cWcEOoTc9@Z_=7! zhMM1_SyD8{uj_hNyLEEM7!O?3ls1x5eJLvzqJOJ#EG>wQB`Ye{QP zU2o%Z)icXddbT(gwoJ+|Dg)|m2n{Ow6mixUc|fjsPbM61kI!Y#6?cs32QA8O)8Am!>3izO>|#F) zURtXV+RQ{S{zch?--s~mZIxB8vGo%3Y%iD}e9`mjOT=g#o9OPNV)E^N&HWlY%idJk9K+{_Y_G@KBT)}n>B;>Xxhz{eM~uT09z2b zD})DZH~%+5_synJ(PNo?P}!9KMFsb(??{)eazV3R8#+jtar{A7HOWA+Q09}t@cLUp z$*R3N1|4}}VSXU`uUOB2&awKgRr-ov`7ujtQlPYg4xy77uSzKuX&UedUvQSRnf=f& zkqMV3?2Q|=Y`M9=jxwM_Uu}O!7INzQHn)wWT-C3wZBn0P4EroCR6iTIdiE6qlTqB2 zblvsPmKa@z)YDO~F z?3w#COMH8Y^ zgKjNePo>|X0YK)?b_J3!J=i~%j)7$1#9 zumskAk$2CM$W)deGBPI`TS_+-Cpm`JgY7!_&NzP}%Wa|{U_!L5_*A50UK8CBLKaT< zU@vVmHyH#G+EeXJ!ajXco!|7u9<`r6Sk*iCL1Go+iRx?y!0jErR}FRMzwFWeTS!g! zcE3`eMh_`!!~cm;R|BkgwpAi^<|##R!)qPRh03y(JG?y~*GL?0U{n`1?Hp~IbI0=H zoom-W)I@M-oL??B%#P;{w4CDf&3Agi0=%b~emQ${+GzEyF&j2=r?m(*VWko>W?aLQ zI~3UQ#bz$eC{Gr!s1k~ufDol?pA&LwS`VQHK1H9aU)rb3T@1&pucH|;NXNodo3a6{ zv^wwpb^=jd&zpd8T2A787pv90M!W~?^)AXH2=2O$w1|3EY9zh=J9oaNjM7(7D5d-S6;xb9gB_403-E{}#bQBF%Ctdg7?xQG^$ zfOKnzRUg~RuxKZlxub~>^8_zTb!)-5BaC1{yc#RODX%zC98<0|Eeq~St zu_>4=i3xH@=yZ$|oj_(zINZVStBcSFaDH;~tX=rk23a654Db?5D+d=p7=aO`m--s-b>*R1A zIV(4JWOcQM)wp5?3|ndo-B{|-@IXA=N*1S^Idy!#StcBU938aql$1O8RRTaO3-~7( zP5+;ewl%rpeq_MrUX0*psX`feK=n3&f`*KDDje<(8lDWRgjY6|-dhnF?|U&N8WaH$wFV>8n}gIaAXbbIU$Wcl86ln-OPekx!6zeoG7V^msb=A;u*Y_K%&Y_FBB*;oo#8;yZDLKwxtoP@&lqX!?Iz&vy)ee5D zlzS4;0B&3YggzC1>+82BdZ5X*Bm}@~z5Ikn^U&iYecyC2FuZg`M~|*!6xy7-PJeNd zT~@wPAox|T;Wcf4u!;sZomk(sus9GE*w^Lo6?D?D92T6wY80xIp@dfAs5I^X<)tAp zG#$G-g?0EWi+=K1d1@N7#o8KLKvRli`~l*9(yi(E#C^8pr|ZiL4-LH1MuJ=Q z2}`ex=tt67EJ`2Vad9t}b1rWPDc|_GKsRZqUrd;=IZYI7ZB!g^TYJ3)EY?yU1qWeQ zU0`15yiqed<-bRC!;)|f48w35jw7{oNR1d{Uk8X~&CbcfG4&G*IMugQEBz-LD~D6`a%6OHfwL}{z}YVWk8MI* zK7aHJD9>b9G3pVp9JUG4Nevo|yM98~k{A%2+qh4>EZkkRC$We|`^J6{#`mad`whF4 z5ndA=7rI#L*q67}su#NCWi~Kjhqd()@J}+5RmRD7ZJ$~rjPiuvq-&>J1T&x1H|F+* zFKw8+^JjxRg(;0j$>US$a|un5n9VL}hfkm|J$3?*@=+x_AZ?Q&%?pYwJt@njaKl$!}lUX zac1|~8WEQA`t;p`^n3X$eD79S%<4Nhn~zfv0QM zia481o8efnpW5JRl&w%wemEAt6(d*Cp-Z$f$`O*`Fv|%fg;W z5$05X8{M*KPoN%kliZXLvsH+;cgw@`SUJWwk+_bY#j(CH$lQoSmsjHMY0y`w#a)do zH4`vV_TWW=F3x=BPsZuiZ*SZ#?x~+Go%oywd!OEN2DpSIFgno4p{9w(hyBWZ$r^G6 z;W42_=y5ZZ$D@JA%=Mv7EZmA2S@>=Gj8V~EK$Csb227qH-xz}bR3&&jUeFH?9n5rN z>Kb7mk?Jbt>Y4h1!UW3jZsr$dXjpyX`lS5aS~~byZY78pzl4c}u*pG;UbQ55=MNj! zFeZn+sn21?dS}uc>;6)RT$2oJIjf(qY(KPCxemc+iPc{5&M!yVUiHGSgjL;x1=%s* zY;j@Q^y2`}&*Gtz4Fo!)6fuIf-nuDS-e7nu#Z*N-?lAZxeN|_#G?ch zvFum=9sxBPphdiGm+^VPY!oq+NoAWHwrz?q*mO_XlGA?~X>)OG(SRII*;g*?=Rrse zD-1nNl;#wF2(H0Otkv@9=m_Zg25)@ftB5o`*>|Srv4+81t%`~Fu&l*CXRJMJ%Y@gX?z6Sh=t%kj z7=qeE_h>A18dOf^yVX6(3NARUG5&mhM$PiOCcfshtvOjjQ0(kjx*$?I)7Q%zJ)(}W z`;RO6^Z~e$sV5ee_Q|fl!!y%-%=Uw0V5{a$TTEM2sO`XA5_`*4*qd2IugF0Smrn30 zfkRgEed+83^F_I$1qYs4&N2fuJLQa_w@?UTD)!~I4{g_`9EW4|pji&}9GqYlePvib z2l7R(Ja;K+OI6qTKA=&c!BLPG>|M|zTIur&4Qe+?HtwK6BLA!9YN-nF(n$?QVx*R_ z+h&{1YO8oM$=_Udr9mVzNYc`i;az`vfJOCyjgX%;oPk-{cq-?;_C%n9X@ zR~$YiM`2U8tY5!zD@QO?;&E?aXi8bl_T;10%jS+q{m72>RdWvIy<3iQP3z01&w~@o z776Fu=xonnMlCr~Hn*EHZMw-TRo_gsZd|wFjCE)PZbd(-SXY^glGg_!$GCfK1p*r{ zc$W>Mqu-;HkX=Fv7G611|4|IVHx8dG*fK7aKcfK{hr*OMmex8Kw#&`r7Bmj+xeq$$ zDRDXmZIBHsU!IqWGgj&&MwKQ zbKxriyQCJ{oGqtYE@rb8rH7hV3O#=xywt^6L6Sq#tnj``B(qrTvtpE=MIFycI80GL zYjDqY3mZ8?5w1tQ^ABxqj-69*i*HZje5-ZryMtE$)z+p$HiDVl^CvNfjby$?o4wQD ze7DI^H5F~YnQ{)IqW~klba)=+;yh5g#?QIB;SNmZ>jeOHx2Oy)LBK*XQ}`0EoPMy| zll0SQ;Un;Y37^duz5KO2x)e=$&{4Q>a?U{`<(L z^B!f8iyKP!q*;xBoupJaJTxl+I)2WtQTg6~?vjtFc*3(p zZKvIWspFx{a@z*zLW)2&<^9lWi`J(ZLH==w6pe(slp&tk!SB>3ZU;NKd0INC!{>^$ zEKSh$`X=^pCe{qE%%(S)*QC!kg zBsz%Q?3cT;JKu<;(xCWoCzpZV{ zx&BZH_hPty{Dlx+BP|@y9`29NSXpy>E*8WX>yeM|_D;fnc0)nvWh*6CA??xHZd_O0 zh#x&0)zw_!0B~TJPu@T3d3y(*`+xg70!(9M@pr!>y}pbUMZ+MzQDWX?lGM z2=@j|)X?AGb@VQrfKmNR9L7MWFl=sKRg-yhX z_fKW-Z0c49FHMF0E0c8o-U_wHIQ;KJ;o*{@P=wQsVWi`yeZQ&w{k8c~Q^eadcZY6% z+Gi;gd?~h!;s=etU(_zTFP@ygZ|G@>W7A*a=RJRa7*!l0{O5s}e~A|gIL7}x@S9o& zgP`(o_dn17&yAw5CLCt^KR2HD{2R16^lRXGj`umkq_?ZtrpK;8o=?5@DWJuvLs>(& zh{0Z_C%z{fKb;pm@tm0y)U!l08B*4Yz|Rgb<@AGQLdo%*_{hwWa^af|!>Z;p&+)caqK&mIt*Za8g;c(?qE-FI4Ht~)8` z@27!pf8Mw3{W$s5cg{G^Jn{YWA`ja(U$?mlInD`dvwj0V1W*_{tw8BR8;CSymyJ7^ zZ?9I~aNqRg##=o!M=zWQlVtY1NJYc0X1)%bOc- z#T5ofe6XP@%(i0F2f~DuTG5hN$92xUk_CE3UyfnN`hN7f@l8j9vK?3CkuLcI^X(^P z=S^i8veId?>%7scAk8~A#5J1f&@~P1ap?p2i;_zha{+?2QG9_@Yf~q4%6hrCWBQBs z$c*|Lplp5!;^}a8d~cv_lyx@g$kt8EPcFr*8Kiy2@eoK_`eEyqIQ_0<077$tFs6TSKw1|@! ziNo>gzg#ZesspdZ*+6>q!6WbAd#$2kJjjl-kstBikIS{2Zmcz13i{i{R;O4742bJj zemelt%J}&;YWKlCF(dS$?nkCA>t{*4?Sj0=2UwZ zdy5z=OUS-NRyJI-5io?+c!Hk(QExh~*2dffpyc|QXM~~ib>D&S29I`X60af82&N9R0b$|637j_c*%2v{KKazd+St4pZ+fHj&e!mNS zz-C8K?(EQP&gj!yi14`yb*K;HBxLz5g0X==TF<=ZdJ-ChRV$Zg?5YgC&d3c%!7PE4 z8L9d40_CJ}gmRKD0w2M1Xx$L3xcGn;4l@2&oboXLBaG5j%lFyZq@?gm$% zGs7%z)mH=r)&Qt(uI_mgAx)0ZThU?0y(1+dNsM%{sWR37Wn9l1CEvcXtM2_)jMF#Q zZdgGwAqjMd^mj8j==b2N%hP!PnJm?9%6p3 zw*FeF)B4Bg3zROuQNphC!=J-$O@29792`oopX>bawQ)TC*W0)k#r;)QN|2WMs(v=^ zDG~#VVSjn=9jea#R#H%FMYc|^zDtXk^6pVmO}5M@wi(xa{IuV0mn5sd6|MUfyL17)hb8dBqD&h5m2Y$B4gcWS%f@#lrPRL$i2=3K+YN2$eggY%jh0(gl zcy0`LPemRyBFIeiw9#M=HAEn71fS9$6{qM!;v&`*mAo!w{;I1NckdAL=8A)JZUK`j z8DX1X;adGH#?Lh8a=LwqG%m6jfj%4Ek{G6UPKsEX=eTYq3=Fy``@DP?i8U-4S#7W3 zSogpsfe9f?j?h&M&PKvaS_UfN}eu}>HFXh3ecJPz;B9vYLj@aXaG`MTJ3smy?c zVl4dqp+u*ylZL&#~GD5$&E8`%Duv^w8pk91~-KXJr_)g~gBx=!V7=-nIf{8(+&oP6L> zyIg--g2tQ|4EI?)4?J?O`o2rp=6mU$m{5p2e%({Po60j}WtJQ)uC~el>2VoZY!%Ye z$Am7vnFyuok)a)^d3p#!>p5nzB1ZX+)WL>#4mL!D3LV24lpjCmhEJaGh~HC z4u!{{*HQ-VK=g(kH$s4GUGUXXb$E#QV4aOONlK*5v6~E~^tmC71qaQtfz7?KRiF68 z*!1FL2Bf>Yy5yWmM8?JcExvDPBJ}S2cKks!Ju?#H@KUL%L_8g7(HfX%a(=&0YnD3J zHu1ABirw|62!nM$GajPg|5MsrS<;{X*BkWqZ$d$Y$x8aPL`Rjll`5Zn!TLC4)gZmO0i_Mb5BV+oT3Xe{( zx`JV+*QZe0+{ewG@HBRQLx4S9hXihcWy$P*{<~ZI)J&KTmAe@mzDOrYNuI0-9CyxN7#vz* zEH)8tAZ8((zOen8dqF}qosrk-G1@bHaZUT06vuD=l+=orbd?`#wU_>!Bl!1j{QuXJ zwKueP7{yVd)F(<=N!@|s;NIhG;VKpHT|2h_UJ>DKoxAql*nPtULXmIq&8T00Chjc! zgSB04u}hb)?R<)E9)I2uuWPh%4*TW{F$3S3l=b82#PS~-^A4eYzc%RP4M~hs0Jmd@ z!u$7fnadGiI2n4dcuDTKQU#zpouurdk<#M45qm>3gAdv6y9|*#~Av)%gA0HoQ zs76MdGqQf4_BTD|&UAD*RwA2v<*HYVzFQD#uA0Um#>bls>FwT8m0wbFzo)0?vZ7)q z&*Gn6&ty{Agbn_Rm7QIwDO~;d(AJUv0A)9}udMEP_at9$g?3&dI%^NosOwI!S~}Su zo2BfqFojJk^{T!zc;J-i9!pCpvt6GTcI?>W{SPldQ`tYif2!c~=f8@w{qN(_|0C4@ z{5XDacgEp^3z_-~OLoP(3oefN-VyXtEx>NZe>yBI%YN(OZS1(pA08f_{TC0)!M<#* zfMx7|wC?xP;9R+H&mZ2!Z(J~6EIfjQRlJXJZn_v7?q<0+vS+d501#n3O_-X|$*{k4 z>;C{v|G!0?wm*Y9(dl5Qu_XOpjC#`DZ=beaDtKdFG_mt|rTB@hhVviqm)GAQ6Y06k zjrsh>Y)R2`RXn#&oakJ&{QKwD!<|{}IiA~}y_s0P;_s7*ulHu==bwKGzUI5jIXXHT zQU-xS0Sq8s*5P_N)BZZ=of~oc-W}fEd3eRf#ycMqqw-bbiq#q;jg5+uYWp6?=I=7y zu!&2Z!@_^hJm8w4uU~zC*m(H+`}g-0Zm)kcaXZMqb8%IP$NOZZWMt0V1Y62=|G9x;`bD+DQ~>_MCsw3l4ss! zIeRwb?>fGGmTjQM#S=R$!j}}M8Aya=XRl5>H)my67nh~qv73b|f_&{)FJCqm(kPWt zPyHVB?S%A|x=$xk^!Hx5dUfgA=8oLTmjT0@R-fH(s$@<4zSqQ^ z%a1LImP_pk)DQ`(uHL;yR!aOQPreIN*RdHB?O*n#_ZvCCRqyY_x;j>*$%Og9Oty6H zvne~;uC$e9KdKg!U9tI^P|le}FQVM*{nCLKf=g!ESElU3wgM+W;}Q>paL(*i9G67x zzG>92z;;Xb0q;yU;HGy67X^V6-@#1@2ciA*5xxSk3~pNdjC1()Vgp*022s^;ay5rF z!|fXVgiEW}uRjkl1l0f_Z`m3p9tLI8#XilKbai#_>9Jy{010F>3NdRF!1d)T;Lq zB*4Xr;h0KL9eVA=M8ltPr$QcQXsnohcf-2gUlz|wvr|(|AMmG@)`4_lfF;K#s(2s2 zVZ)*Qe{Pj$ElQe!DHf4Re-XT|dBq7a;jdWto-(w)|Ic_TNczhSE|#+(U7oIfF6*2U FngCQjg;4+i literal 0 HcmV?d00001 diff --git a/dev/sim/coco/tb.cpp b/dev/sim/coco/tb.cpp new file mode 100755 index 0000000..2cff571 --- /dev/null +++ b/dev/sim/coco/tb.cpp @@ -0,0 +1,250 @@ +// simple verilator top +/* +doesn't build on 4.106 (at least) +*/ + +#define TRACING + +#include +#include +#include + +#include "verilated.h" +#include "Vc.h" + +#ifdef TRACING +#include "verilated_vcd_c.h" +VerilatedVcdC *t; +#else +unsigned int t = 0; +#endif + +/* +#include "uart/uartsim.h" +*/ + +Vc* m; + +vluint64_t main_time = 0; // in units of timeprecision used in verilog or --timescale-override +// what is it? it changed to 941621251 after calling loadmem() + +double sc_time_stamp() { // $time in verilog + return main_time; +} + +const int resetCycle = 10; +const int threadRunCycle = 200; +const int runCycles = 1000; +const int hbCycles = 500; +const int threads = 1; // needs a more realistic a2l2 data return to work in smt + +/* + + 143 # ------------------------------------------------------------------------------------------------- + 144 # enable smt2 and branch in different locs (driver returns b +64 if doesnt hit actual ops) + 145 # 32b mode until msr[32]=1 + 146 + 147 0344 480000BC .align 8 + 147 60000000 + 147 60000000 + 147 60000000 + 147 60000000 + 148 boot_start: + 149 + 150 0400 38200003 li r1,0x3 + 151 0404 7C366BA6 mtspr tens,r1 # 62:63 = tid 1:0 enabled + 152 0408 7C3E6AA6 mfspr r1,tir # who am i? + *** appears to need an isync here! cr is not correct w/o it (old r1?) + 153 040c 2C010000 cmpwi r1,0x00 + 154 0410 38202000 li r1,0x2000 # change to use 660 so stay in page 0 + 155 0414 41820008 beq t0 + 156 t1: + 157 0418 5421103A slwi r1,r1,2 # change to addi so stay in page 0 + 158 t0: + 160 041c 7C2903A6 mtctr r1 + 161 0420 4E800420 bctr # off to neverneverland + + + 162 041c 7C2FCBA6 mtspr tar,r1 + 163 0420 4E800460 bctar 0x14,0,0 + + 4C00012C isync + + +*/ + +int mem[1024]; // 4B*1K + +void loadmem(void) { + int adr; + mem[0x0000/4] = 0x48000400; + adr = 0x400/4; + + mem[adr++] = threads == 1 ? 0x38200001 : 0x38200003; + mem[adr++] = 0x7C366BA6; + mem[adr++] = 0x7C366BA6; + mem[adr++] = 0x7C3E6AA6; + mem[adr++] = 0x4C00012C; + mem[adr++] = 0x2C010000; + mem[adr++] = 0x38200660; + mem[adr++] = 0x41820008; + mem[adr++] = 0x38210100; + mem[adr++] = 0x7C2903A6; + mem[adr++] = 0x4E800420; + +} + +// nclk = (clk,reset,clk2x,clk4x,-,-) + +int main(int argc, char **argv) { + using namespace std; + + loadmem(); + + cout << setfill('0'); + + Verilated::commandArgs(argc, argv); + m = new Vc; + +#ifdef TRACING + Verilated::traceEverOn(true); + t = new VerilatedVcdC; + m->trace(t, 99); + t->open("wtf.vcd"); + cout << "Tracing enabled." << endl; +#endif + + bool resetDone = false; + unsigned int threadStop = 0x3; + + unsigned int tick = 0; + unsigned int cycle = 1; + unsigned int readPending = 0; + unsigned int readAddr = 0; + unsigned int readTag = 0; + unsigned int readTID = 0; + unsigned int countReads = 0; + + m->nclk = 0x3C; // run 2x,4x = 1x + cout << setw(8) << cycle << "Resetting..." << endl; + + m->an_ac_pm_thread_stop = threadStop; + cout << setw(8) << cycle << "Thread stop=" << threadStop << endl; + + // can skip 4x with new gpr array + // 1x=4/4 2x=2/2 4x=1/1 + // 1 1 1 7 + // 1 1 0 6 + // 1 0 1 5 + // 1 0 0 4 + // 0 1 1 3 + // 0 1 0 2 + // 0 0 1 1 + // 0 0 0 0 + // (insert reset) + //const int clocks[8] = {11, 0, 11, 0, 11, 0, 11, 0}; // 2x,4x == 1x + const int clocks[8] = {11, 10, 9, 8, 3, 2, 1, 0}; // 1x, 2x, 4x + const int ticks1x = 8; + + while (!Verilated::gotFinish()) { + + if (!resetDone && (cycle > resetCycle)) { + m->nclk &= 0x2F; + cout << setw(8) << cycle << "Releasing reset." << endl; + resetDone = true; + } + + if (threadStop && (cycle > threadRunCycle)) { + threadStop = 0x0; + m->an_ac_pm_thread_stop = threadStop; + cout << setw(8) << cycle << "Thread stop=" << threadStop << endl; + } + + m->nclk = (m->nclk & 0x10) | (clocks[tick % 8] << 2); + tick++; + m->eval(); + + // bus is 1x clock + if ((tick % ticks1x) == 0) { + + if (readPending == cycle) { // i=1 + + m->an_ac_reld_data_vld = 1; + m->an_ac_reld_core_tag = readTag; + m->an_ac_reld_qw = 0; + m->an_ac_reld_crit_qw = 1; + + if (readAddr == 0xFFFFFFF0) { + + m->an_ac_reld_data[3]= 0x00000000; // 0 + m->an_ac_reld_data[2]= 0x00000000; // 4 + m->an_ac_reld_data[1]= 0x00000000; // 8 + m->an_ac_reld_data[0]= 0x48000002; // C + + } else if (readAddr < 0x0500) { + + m->an_ac_reld_data[3]= mem[readAddr/4+0]; + m->an_ac_reld_data[2]= mem[readAddr/4+1]; + m->an_ac_reld_data[1]= mem[readAddr/4+2]; + m->an_ac_reld_data[0]= mem[readAddr/4+3]; + + } else { + + m->an_ac_reld_data[3]= 0x48000040; + m->an_ac_reld_data[2]= 0x00000000; + m->an_ac_reld_data[1]= 0x00000000; + m->an_ac_reld_data[0]= 0x00000000; + + } + readPending = 0; + countReads++; + cout << setw(8) << cycle << " an_ac_rsp: data="<< hex << uppercase << setw(8) << m->an_ac_reld_data[3] + << hex << uppercase << setw(8) << m->an_ac_reld_data[2] + << hex << uppercase << setw(8) << m->an_ac_reld_data[1] + << hex << uppercase << setw(8) << m->an_ac_reld_data[0] + << dec << nouppercase << endl; + } else { + m->an_ac_reld_data_vld = 0; + } + + m->an_ac_req_ld_pop = 0; + if (!readPending && m->ac_an_req) { + readAddr = m->ac_an_req_ra; + readTag = m->ac_an_req_ld_core_tag; + readTID = m->ac_an_req_thread; + readPending = cycle + 3; + cout << setw(8) << cycle << " ac_an_req: T" << readTID << " ra=" << hex << uppercase << setw(8) << readAddr << dec << nouppercase << endl; + m->an_ac_req_ld_pop = 1; + } + + } + + // finish clock stuff + if ((tick % ticks1x) == 0) { + cycle++; + if ((cycle % hbCycles) == 0) { + cout << setw(8) << cycle << " ...tick..." << endl; + } + } + #ifdef TRACING + t->dump(tick); + t->flush(); + #endif + + // check for fails + + // hit limit + if (cycle > runCycles) { + break; + } + + } + +#ifdef TRACING + t->close(); +#endif + m->final(); + + exit(EXIT_SUCCESS); + +} \ No newline at end of file diff --git a/dev/sim/coco/tb.py b/dev/sim/coco/tb.py new file mode 100755 index 0000000..d100c6d --- /dev/null +++ b/dev/sim/coco/tb.py @@ -0,0 +1,307 @@ +# a2o test tb + +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import Timer +from cocotb.triggers import FallingEdge +from cocotb.handle import Force +from cocotb.handle import Release + +import itertools +from dotmap import DotMap + +from OPEnv import * +from A2L2 import * + +# ------------------------------------------------------------------------------------------------ +# Tasks + +# get rid of z on anything that will be sampled here +# is there a func to get all inputs? +async def init(dut, sim): + """Initialize inputs. """ + + dut.nclk.value = 0 + dut.scan_in.value = 0 + dut.an_ac_scan_type_dc.value = 0x0 + dut.an_ac_chipid_dc.value = 0x0 + dut.an_ac_coreid.value = 0x0 + dut.an_ac_scom_sat_id.value = 0x0 + + dut.an_ac_lbist_ary_wrt_thru_dc.value = 0 + dut.an_ac_gsd_test_enable_dc.value = 0 + dut.an_ac_gsd_test_acmode_dc.value = 0 + dut.an_ac_ccflush_dc.value = 0 + dut.an_ac_ccenable_dc.value = 0 + dut.an_ac_lbist_en_dc.value = 0 + dut.an_ac_lbist_ip_dc.value = 0 + dut.an_ac_lbist_ac_mode_dc.value = 0 + dut.an_ac_scan_diag_dc.value = 0 + dut.an_ac_scan_dis_dc_b.value = 0 + + dut.an_ac_rtim_sl_thold_8.value = 0 + dut.an_ac_func_sl_thold_8.value = 0 + dut.an_ac_func_nsl_thold_8.value = 0 + dut.an_ac_ary_nsl_thold_8.value = 0 + dut.an_ac_sg_8.value = 0 + dut.an_ac_fce_8.value = 0 + dut.an_ac_abst_scan_in.value = 0 + + dut.an_ac_checkstop.value = 0 + + dut.an_ac_reset_1_complete.value = 0 + dut.an_ac_reset_2_complete.value = 0 + dut.an_ac_reset_3_complete.value = 0 + dut.an_ac_reset_wd_complete.value = 0 + + dut.an_ac_pm_fetch_halt.value = 0 + dut.an_ac_debug_stop.value = 0 + + dut.an_ac_tb_update_enable.value = 1 + dut.an_ac_tb_update_pulse.value = 0 # tb clock if xucr0[tcs]=1 (must be <1/2 proc clk; tb pulse is 2x this clock) + + # why is coco turning [0] into non-vector??? or is that gpi/vpi/icarus/??? + if sim.threads == 1: + dut.an_ac_pm_thread_stop.value = 0x1 + dut.an_ac_external_mchk.value = 0 + dut.an_ac_sleep_en.value = 0 + dut.an_ac_ext_interrupt.value = 0 + dut.an_ac_crit_interrupt.value = 0 + dut.an_ac_perf_interrupt.value = 0 + dut.an_ac_hang_pulse.value = 0 + dut.an_ac_uncond_dbg_event.value = 0 + else: + for i in range(sim.threads): + dut.an_ac_pm_thread_stop[i].value = 0x1 + dut.an_ac_external_mchk[i].value = 0 + dut.an_ac_sleep_en[i].value = 0 + dut.an_ac_ext_interrupt[i].value = 0 + dut.an_ac_crit_interrupt[i].value = 0 + dut.an_ac_perf_interrupt[i].value = 0 + dut.an_ac_hang_pulse[i].value = 0 + dut.an_ac_uncond_dbg_event[i].value = 0 + + await Timer(9, units='ns') + +async def config(dut, sim): + """Configure core, etc. """ + + #wtf make A2 module to do core-specific stuff + # A2L2 load/store credits + creditsLd = dut.c0.lq0.lsq.arb.load_cred_cnt_d # 8 max + creditsLdMax = dut.c0.lq0.lsq.arb.ld_cred_max # hdw check + creditsSt = dut.c0.lq0.lsq.arb.store_cred_cnt_d # 32 max + creditsStMax = dut.c0.lq0.lsq.arb.st_cred_max # hdw check + creditsLdStSingle = dut.c0.lq0.lsq.arb.spr_xucr0_cred_d.value # 1 total credit + #wtf this affects A2L2 - default=1 + #creditsLdStSingle = dut.c0.lq0.lsq.arb.spr_lsucr0_b2b_q.value # 0=crit first, every other 1=crit first, b2b **the a2l2 spec does not say crit must be first** + + await RisingEdge(dut.clk_1x) + + if sim.config.core.creditsLd is not None: + creditsLd.value = Force(sim.config.core.creditsLd) + creditsLdMax.value = Force(sim.config.core.creditsLd) + sim.msg(f'A2L2: load credits changed from {creditsLd.value.integer} to {sim.config.core.creditsLd}.') + await RisingEdge(dut.clk_1x) + creditsLd.value = Release() + + if sim.config.core.creditsSt is not None: + creditsSt.value = Force(sim.config.core.creditsSt) + creditsStMax.value = Force(sim.config.core.creditsSt) + sim.msg(f'A2L2: store credits changed from {creditsSt.value.integer} to {sim.config.core.creditsSt}.') + await RisingEdge(dut.clk_1x) + creditsSt.value = Release() + + if sim.config.core.creditsLdStSingle: + creditsLdStSingle = Force(1) + sim.msg(f'A2L2: only one load OR store allowed when credits=1/1.') + await RisingEdge(dut.clk_1x) + creditsLdStSingle.value = Release() + + await RisingEdge(dut.clk_1x) + +async def coreMonitor(dut, sim): + """Watch for core events. """ + + me = 'a2oMonitor' + + # errors + creditsLdErr = dut.c0.lq0.lsq.arb.ld_cred_err_q + creditsStErr = dut.c0.lq0.lsq.arb.st_cred_err_q + + # watches + iu0Comp = dut.c0.iu_lq_i0_completed + iu0CompIFAR = dut.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i0_ifar + iu1Comp = dut.c0.iu_lq_i1_completed + iu1CompIFAR = dut.c0.iuq0.iuq_cpl_top0.iuq_cpl0.cp2_i1_ifar + iuCompFlushIFAR = dut.c0.cp_t0_flush_ifar + cp3NIA = dut.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.cp3_nia_q # nia after last cycle's completions + + # queue depths, etc. + + errors = [ + {'name': 'Load Credits', 'sig': creditsLdErr}, + {'name': 'Store Credits', 'sig': creditsStErr}, + ] + + done = False + + while not done: + + await RisingEdge(dut.clk_1x) + + for i in range(len(errors)): + assert errors[i]['sig'].value == 0, f'{me} Error: {errors[i]["name"]}' + + comp = '' + if iu0Comp.value == 1: + comp = f'0:{int(iu0CompIFAR.value.binstr + "00", 2):06X} ' + + if iu1Comp.value == 1: + comp = f'{comp}1:{int(iu1CompIFAR.value.binstr + "00", 2):06X} ' + + if comp != '': + comp = f'{comp}{int(iuCompFlushIFAR.value.binstr + "00", 2):016X}' + sim.msg(f'C0: CP {comp}') + + +# trilib/tri.vh:`define NCLK_WIDTH 6 // 0 1xClk, 1 Reset, 2 2xClk, 3 4xClk, 4 Even .5xClk, 5 Odd .5xClk +async def genReset(dut, sim): + """Generate reset. """ + + first = True + done = False + + while not done: + await RisingEdge(dut.clk_1x) + if sim.cycle < sim.resetCycle: + if first: + dut._log.info(f'[{sim.cycle:08d}] Resetting...') + first = False + dut.nclk[1].value = 1 + elif not done: + dut._log.info(f'[{sim.cycle:08d}] Releasing reset.') + dut.nclk[1].value = 0 + done = True + +async def genClocks(dut, sim): + """Generate 1x, 2x, 4x clock pulses, depending on parms. """ + + if sim.clk2x and sim.clk4x: + sim.clk1x = Clock(dut.nclk[0], 8, 'ns') + await cocotb.start(sim.clk1x.start()) + sim.clk2x = Clock(dut.nclk[2], 4, 'ns') + await cocotb.start(sim.clk2x.start()) + sim.clk4x = Clock(dut.nclk[3], 2, 'ns') + await cocotb.start(sim.clk4x.start()) + elif sim.clk2x: + sim.clk1x = Clock(dut.nclk[0], 8, 'ns') + await cocotb.start(sim.clk1x.start()) + sim.clk2x = Clock(dut.nclk[2], 4, 'ns') + await cocotb.start(sim.clk2x.start()) + else: + sim.clk1x = Clock(dut.nclk[0], 8, 'ns') + await cocotb.start(sim.clk1x.start()) + + + for cycle in range(sim.maxCycles): + + sim.cycle = cycle + + if cycle % sim.hbCycles == 0: + dut._log.info(f'[{cycle:08d}] ...tick...') + + await RisingEdge(dut.clk_1x) + + dut._log.info(f'[{sim.cycle:08d}] Reached max cycle. Clocks stopped.') + +# ------------------------------------------------------------------------------------------------ +# Interfaces + +# SCOM +async def scom(dut, sim): + """scom interface""" + + dut.an_ac_scom_dch.value = 0 + dut.an_ac_scom_cch.value = 0 + + +# ------------------------------------------------------------------------------------------------ +# Do something + +@cocotb.test() +async def tb(dut): + """A Vulgar Display of OpenPower""" + + sim = Sim(dut) + sim.mem = Memory(sim) + #sim.memFiles = ['../mem/boot_ieq1.bin.hex'] #wtf cmdline parm + sim.memFiles = ['../mem/boot.bin.hex'] #wtf cmdline parm + + for i in range(len(sim.memFiles)): #wtf el should be object with name, format, etc. + sim.mem.loadFile(sim.memFiles[i]) + if sim.resetAddr is not None and sim.mem.read(sim.resetAddr) == sim.mem.default: + sim.mem.write(sim.resetAddr, sim.resetOp) + sim.msg(f'Set reset fetch @{sim.resetAddr:08X} to {sim.resetOp:08X}.') + +# dut.cocotb_icarus +# dut._log.info(sim.top.__dict__) +# {'_handle': , +# '_len': None, '_sub_handles': {}, '_invalid_sub_handles': set(), '_name': 'cocotb_icarus', +# '_type': 'GPI_MODULE', '_fullname': 'cocotb_icarus(GPI_MODULE)', '_path': 'cocotb_icarus.cocotb_icarus', +# '_log': , '_def_name': 'cocotb_icarus', '_def_file': './cocotb_icarus.v', +# '_discovered': False +# } +# dut +# {'_handle': , +# '_len': None, '_sub_handles': {'an_ac_pm_thread_stop': ModifiableObject(cocotb_icarus.an_ac_pm_thread_stop), +# 'cocotb_icarus': HierarchyObject(cocotb_icarus.cocotb_icarus with definition cocotb_icarus (at ./cocotb_icarus.v))}, +# '_invalid_sub_handles': set(), '_name': 'cocotb_icarus', '_type': 'GPI_MODULE', '_fullname': 'cocotb_icarus(GPI_MODULE)', +# '_path': 'cocotb_icarus', '_log': , '_def_name': '', '_def_file': '', +# '_discovered': False + + # init stuff + await init(dut, sim) + + # start clocks,reset + await cocotb.start(genClocks(dut, sim)) + await cocotb.start(genReset(dut, sim)) + + # start interfaces + await cocotb.start(scom(dut, sim)) + + #wtf don't have to instantiate A2L2 first? + #await cocotb.start(A2L2Driver(dut, sim)) + #await cocotb.start(A2L2Checker(dut, sim)) + #await cocotb.start(A2L2Monitor(dut, sim)) + await cocotb.start(A2L2.driver(dut, sim)) + await cocotb.start(A2L2.checker(dut, sim)) + await cocotb.start(A2L2.monitor(dut, sim)) + + await Timer((sim.resetCycle + 5)*8, units='ns') + if dut.nclk[1].value != 0: + sim.ok = False + sim.fail = 'Reset active too long!' + + # config stuff + await config(dut, sim) + + # monitor stuff + await cocotb.start(coreMonitor(dut, sim)) + + # release thread(s) + dut.an_ac_pm_thread_stop.value = 0 + await RisingEdge(dut.clk_1x) + dut._log.info(f'[{sim.cycle:08d}] Threads enabled.') + + + + # should await sim.done + await Timer((sim.maxCycles+100)*8, units='ns') + + if sim.ok: + dut._log.info(f'[{sim.cycle:08d}] You has opulence.') + else: + dut._log.info(f'[{sim.cycle:08d}] You are worthless and weak!') + assert False, f'[{sim.cycle:08d}] {sim.fail}' + diff --git a/dev/sim/coco/verilog b/dev/sim/coco/verilog new file mode 120000 index 0000000..b628320 --- /dev/null +++ b/dev/sim/coco/verilog @@ -0,0 +1 @@ +../../verilog \ No newline at end of file diff --git a/dev/sim/gtkwave/gtkf-64L.py b/dev/sim/gtkwave/gtkf-64L.py new file mode 100755 index 0000000..277b200 --- /dev/null +++ b/dev/sim/gtkwave/gtkf-64L.py @@ -0,0 +1,32 @@ +#!/usr/bin/python3 +# gtkwave process filter +# +# return left 64 of binary + +import sys + +fi = sys.stdin +fo = sys.stdout +fe = sys.stderr + +def dbg(m): + fe.write(m + '\n') + fe.flush() + +def main(): + + while True: + + line = fi.readline() + if not line: + return 0 + + try: + fo.write(f'{int(line[0:32],2):08X}{int(line[32:65],2):08X}\n') + except: + fo.write('\n') + + fo.flush() + +if __name__ == '__main__': + sys.exit(main()) diff --git a/dev/sim/gtkwave/gtkf-64R.py b/dev/sim/gtkwave/gtkf-64R.py new file mode 100755 index 0000000..27d9cce --- /dev/null +++ b/dev/sim/gtkwave/gtkf-64R.py @@ -0,0 +1,32 @@ +#!/usr/bin/python3 +# gtkwave process filter +# +# return right 64 of binary + +import sys + +fi = sys.stdin +fo = sys.stdout +fe = sys.stderr + +def dbg(m): + fe.write(m + '\n') + fe.flush() + +def main(): + + while True: + + line = fi.readline() + if not line: + return 0 + + try: + fo.write(f'{int(line[-65:-33],2):08X}{int(line[-33:-1],2):08X}\n') + except: + fo.write('\n') + + fo.flush() + +if __name__ == '__main__': + sys.exit(main()) diff --git a/dev/sim/gtkwave/gtkf-a2l2.py b/dev/sim/gtkwave/gtkf-a2l2.py new file mode 100755 index 0000000..4ca32f1 --- /dev/null +++ b/dev/sim/gtkwave/gtkf-a2l2.py @@ -0,0 +1,943 @@ +#!/usr/bin/python3 +# gtkwave transaction filter + +# interpret a2l2 (req) interface +# needs: +# track multiple outstanding and out-of-order; +# update to show active tag list (credits), etc. +# +# select the signals; F4; name it; format->binary; format->transaction filter; select the signals and create group + +import sys +import tempfile +import subprocess + +fi = sys.stdin +fo = sys.stdout +fe = sys.stderr + +debug = False + +def dbg(m): + if debug: + fe.write(m + '\n') + fe.flush() + +filterName = 'A2L2 Decode' +transColor = 'DarkRed' + +colors = { + #'default':'DeepSkyBlue', + 'default':'black', + 'data':'DarkGray', + 'bctr':'DarkOrange' +} + +sigs = [None] * 30 +sigNames = { + 'ac_an_req' : None, + 'ac_an_req_ra[22:63]' : 'RA', + 'ac_an_req_thread[0:2]' : 'T', + 'ac_an_req_ttype[0:5]' : 'TT', + 'ac_an_req_tag[0:5]' : 'Tag', + 'ac_an_req_wimg_w' : 'W', + 'ac_an_req_wimg_i' : 'I', + 'ac_an_req_wimg_m' : 'M', + 'ac_an_req_wimg_g' : 'G', +} +sigTypes = { + 'RA' : ('08X',), + 'T': ('X',), + 'TT' : ('02X',), + 'Tag' : ('02X',), + 'W' : ('nz', 'X'), + 'I' : ('nz', 'X'), + 'M' : ('nz', 'X'), + 'G' : ('nz', 'X'), +} + +trans = [] +numTrans = 0 + +class Sig(): + def __init__(self, name): + self.name = name + self.values = [] + def addValue(self, t, v): + self.values.append((t,v)) + +class Trans(): + def __init__(self): + self.timeReq = 0 + self.timeDVal = 0 + self.timeLast = 0 + self.props = {} + +# the last value of each sig is in this transaction (req=1) +def addTrans(time): + global numTrans + t = Trans() + t.timeReq = time + for i in range(len(sigs)): + if sigs[i] == None: + continue + t.props[sigs[i].name] = sigs[i].values[-1][1] + trans.append(t) + numTrans += 1 + +def main(): + + t = f'$name {filterName}\n' + t += '#0\n' + + inDumpVars = False + startTrans = False + inTrans = False + + while True: + + l = fi.readline() + if not l: + return 0 + + dbg(l) + + if l.startswith('#'): # time + if startTrans: + dbg('start trans\n') + addTrans(varTime) + startTrans = False + inTrans = True + varTime = int(l[1:-1]) + elif inDumpVars: + if l.startswith('$comment data_end'): + inDumpVars = False + if inTrans: + addTrans(varTime) + inTrans = False + elif l.startswith('$'): # ? + pass + else: # value will be either 'vec num' or 'bn' (b=bit,n=num) + if ' ' in l: # vector + v = l.split()[0] + if 'x' in v or 'z' in v: + v = '0' # could mark it and check later + elif v[0] == 'b': + v = hex(int(v[1:], 2)) + elif v[0] == 'x': + v = v[1:] + n = int(l.split()[1]) + else: # bit + v = l[0] + n = int(l[1:]) + sigs[n-1].addValue(varTime, v) + dbg(f'sig {n-1} {v}\n') + if sigs[n-1].name == 'ac_an_req': + dbg(f'transig: {n-1} {v}\n') + if v == '1': + startTrans = True + dbg('about to start trans\n') + elif sigs[n-1].name == 'an_ac_reld_data_vld': + if v == '1': + trans[-1].timeDVal = varTime + trans[-1].timeLast = varTime + inTrans = False + elif l.startswith('$var '): + tokens = l.split() # $var wire 3 2 ac_an_req_thread[0:2] $end 3=width 2=index + n = int(tokens[3]) - 1 + sigs[n] = Sig(tokens[4]) + elif l.startswith('$dumpvars'): + inDumpVars = True + else: + #t += '#' + str(i) + ' ' + l + '\n' + pass + + if l.startswith('$comment data_end'): + # a transaction starts every req=1 cycle + t = '' + for i in range(len(trans)): + t += f'#{trans[i].timeReq} ?{transColor}?' + for p in trans[i].props: + if p in sigNames and sigNames[p] is not None: + n = sigNames[p] + if n in sigTypes and sigTypes[n][0] == 'nz': + if trans[i].props[p] == '1': + t += f'{n}:{int(trans[i].props[p], 16):{sigTypes[n][1]}} ' + elif n in sigTypes: + dbg(f'{trans[i].props[p]}\n') + if n == 'T': + t += f'{n}{int(trans[i].props[p], 16):{sigTypes[n][0]}} ' + elif n == 'TT' and trans[i].props[p] == '0x0': + t += 'IFETCH ' + else: + t += f'{n}:{int(trans[i].props[p], 16):{sigTypes[n][0]}} ' + else: + t += f'{n}:{trans[i].props[p]} ' + t += '\n' + t += f'#{trans[i].timeLast}\n' # may need to wait till next cyc in case req on back-back? + t += '$finish\n' + fo.write(f'{t}') + fo.flush() + + +if __name__ == '__main__': + sys.exit(main()) + +''' +rgb.c from gtkwave + +static struct wave_rgb_color colors[] = { +WAVE_RGB_COLOR("alice blue", 240, 248, 255), +WAVE_RGB_COLOR("AliceBlue", 240, 248, 255), +WAVE_RGB_COLOR("antique white", 250, 235, 215), +WAVE_RGB_COLOR("AntiqueWhite", 250, 235, 215), +WAVE_RGB_COLOR("AntiqueWhite1", 255, 239, 219), +WAVE_RGB_COLOR("AntiqueWhite2", 238, 223, 204), +WAVE_RGB_COLOR("AntiqueWhite3", 205, 192, 176), +WAVE_RGB_COLOR("AntiqueWhite4", 139, 131, 120), +WAVE_RGB_COLOR("aquamarine", 127, 255, 212), +WAVE_RGB_COLOR("aquamarine1", 127, 255, 212), +WAVE_RGB_COLOR("aquamarine2", 118, 238, 198), +WAVE_RGB_COLOR("aquamarine3", 102, 205, 170), +WAVE_RGB_COLOR("aquamarine4", 69, 139, 116), +WAVE_RGB_COLOR("azure", 240, 255, 255), +WAVE_RGB_COLOR("azure1", 240, 255, 255), +WAVE_RGB_COLOR("azure2", 224, 238, 238), +WAVE_RGB_COLOR("azure3", 193, 205, 205), +WAVE_RGB_COLOR("azure4", 131, 139, 139), +WAVE_RGB_COLOR("beige", 245, 245, 220), +WAVE_RGB_COLOR("bisque", 255, 228, 196), +WAVE_RGB_COLOR("bisque1", 255, 228, 196), +WAVE_RGB_COLOR("bisque2", 238, 213, 183), +WAVE_RGB_COLOR("bisque3", 205, 183, 158), +WAVE_RGB_COLOR("bisque4", 139, 125, 107), +WAVE_RGB_COLOR("black", 0, 0, 0), +WAVE_RGB_COLOR("blanched almond", 255, 235, 205), +WAVE_RGB_COLOR("BlanchedAlmond", 255, 235, 205), +WAVE_RGB_COLOR("blue", 0, 0, 255), +WAVE_RGB_COLOR("blue violet", 138, 43, 226), +WAVE_RGB_COLOR("blue1", 0, 0, 255), +WAVE_RGB_COLOR("blue2", 0, 0, 238), +WAVE_RGB_COLOR("blue3", 0, 0, 205), +WAVE_RGB_COLOR("blue4", 0, 0, 139), +WAVE_RGB_COLOR("BlueViolet", 138, 43, 226), +WAVE_RGB_COLOR("brown", 165, 42, 42), +WAVE_RGB_COLOR("brown1", 255, 64, 64), +WAVE_RGB_COLOR("brown2", 238, 59, 59), +WAVE_RGB_COLOR("brown3", 205, 51, 51), +WAVE_RGB_COLOR("brown4", 139, 35, 35), +WAVE_RGB_COLOR("burlywood", 222, 184, 135), +WAVE_RGB_COLOR("burlywood1", 255, 211, 155), +WAVE_RGB_COLOR("burlywood2", 238, 197, 145), +WAVE_RGB_COLOR("burlywood3", 205, 170, 125), +WAVE_RGB_COLOR("burlywood4", 139, 115, 85), +WAVE_RGB_COLOR("cadet blue", 95, 158, 160), +WAVE_RGB_COLOR("CadetBlue", 95, 158, 160), +WAVE_RGB_COLOR("CadetBlue1", 152, 245, 255), +WAVE_RGB_COLOR("CadetBlue2", 142, 229, 238), +WAVE_RGB_COLOR("CadetBlue3", 122, 197, 205), +WAVE_RGB_COLOR("CadetBlue4", 83, 134, 139), +WAVE_RGB_COLOR("chartreuse", 127, 255, 0), +WAVE_RGB_COLOR("chartreuse1", 127, 255, 0), +WAVE_RGB_COLOR("chartreuse2", 118, 238, 0), +WAVE_RGB_COLOR("chartreuse3", 102, 205, 0), +WAVE_RGB_COLOR("chartreuse4", 69, 139, 0), +WAVE_RGB_COLOR("chocolate", 210, 105, 30), +WAVE_RGB_COLOR("chocolate1", 255, 127, 36), +WAVE_RGB_COLOR("chocolate2", 238, 118, 33), +WAVE_RGB_COLOR("chocolate3", 205, 102, 29), +WAVE_RGB_COLOR("chocolate4", 139, 69, 19), +WAVE_RGB_COLOR("coral", 255, 127, 80), +WAVE_RGB_COLOR("coral1", 255, 114, 86), +WAVE_RGB_COLOR("coral2", 238, 106, 80), +WAVE_RGB_COLOR("coral3", 205, 91, 69), +WAVE_RGB_COLOR("coral4", 139, 62, 47), +WAVE_RGB_COLOR("cornflower blue", 100, 149, 237), +WAVE_RGB_COLOR("CornflowerBlue", 100, 149, 237), +WAVE_RGB_COLOR("cornsilk", 255, 248, 220), +WAVE_RGB_COLOR("cornsilk1", 255, 248, 220), +WAVE_RGB_COLOR("cornsilk2", 238, 232, 205), +WAVE_RGB_COLOR("cornsilk3", 205, 200, 177), +WAVE_RGB_COLOR("cornsilk4", 139, 136, 120), +WAVE_RGB_COLOR("cyan", 0, 255, 255), +WAVE_RGB_COLOR("cyan1", 0, 255, 255), +WAVE_RGB_COLOR("cyan2", 0, 238, 238), +WAVE_RGB_COLOR("cyan3", 0, 205, 205), +WAVE_RGB_COLOR("cyan4", 0, 139, 139), +WAVE_RGB_COLOR("dark blue", 0, 0, 139), +WAVE_RGB_COLOR("dark cyan", 0, 139, 139), +WAVE_RGB_COLOR("dark goldenrod", 184, 134, 11), +WAVE_RGB_COLOR("dark gray", 169, 169, 169), +WAVE_RGB_COLOR("dark green", 0, 100, 0), +WAVE_RGB_COLOR("dark grey", 169, 169, 169), +WAVE_RGB_COLOR("dark khaki", 189, 183, 107), +WAVE_RGB_COLOR("dark magenta", 139, 0, 139), +WAVE_RGB_COLOR("dark olive green", 85, 107, 47), +WAVE_RGB_COLOR("dark orange", 255, 140, 0), +WAVE_RGB_COLOR("dark orchid", 153, 50, 204), +WAVE_RGB_COLOR("dark red", 139, 0, 0), +WAVE_RGB_COLOR("dark salmon", 233, 150, 122), +WAVE_RGB_COLOR("dark sea green", 143, 188, 143), +WAVE_RGB_COLOR("dark slate blue", 72, 61, 139), +WAVE_RGB_COLOR("dark slate gray", 47, 79, 79), +WAVE_RGB_COLOR("dark slate grey", 47, 79, 79), +WAVE_RGB_COLOR("dark turquoise", 0, 206, 209), +WAVE_RGB_COLOR("dark violet", 148, 0, 211), +WAVE_RGB_COLOR("DarkBlue", 0, 0, 139), +WAVE_RGB_COLOR("DarkCyan", 0, 139, 139), +WAVE_RGB_COLOR("DarkGoldenrod", 184, 134, 11), +WAVE_RGB_COLOR("DarkGoldenrod1", 255, 185, 15), +WAVE_RGB_COLOR("DarkGoldenrod2", 238, 173, 14), +WAVE_RGB_COLOR("DarkGoldenrod3", 205, 149, 12), +WAVE_RGB_COLOR("DarkGoldenrod4", 139, 101, 8), +WAVE_RGB_COLOR("DarkGray", 169, 169, 169), +WAVE_RGB_COLOR("DarkGreen", 0, 100, 0), +WAVE_RGB_COLOR("DarkGrey", 169, 169, 169), +WAVE_RGB_COLOR("DarkKhaki", 189, 183, 107), +WAVE_RGB_COLOR("DarkMagenta", 139, 0, 139), +WAVE_RGB_COLOR("DarkOliveGreen", 85, 107, 47), +WAVE_RGB_COLOR("DarkOliveGreen1", 202, 255, 112), +WAVE_RGB_COLOR("DarkOliveGreen2", 188, 238, 104), +WAVE_RGB_COLOR("DarkOliveGreen3", 162, 205, 90), +WAVE_RGB_COLOR("DarkOliveGreen4", 110, 139, 61), +WAVE_RGB_COLOR("DarkOrange", 255, 140, 0), +WAVE_RGB_COLOR("DarkOrange1", 255, 127, 0), +WAVE_RGB_COLOR("DarkOrange2", 238, 118, 0), +WAVE_RGB_COLOR("DarkOrange3", 205, 102, 0), +WAVE_RGB_COLOR("DarkOrange4", 139, 69, 0), +WAVE_RGB_COLOR("DarkOrchid", 153, 50, 204), +WAVE_RGB_COLOR("DarkOrchid1", 191, 62, 255), +WAVE_RGB_COLOR("DarkOrchid2", 178, 58, 238), +WAVE_RGB_COLOR("DarkOrchid3", 154, 50, 205), +WAVE_RGB_COLOR("DarkOrchid4", 104, 34, 139), +WAVE_RGB_COLOR("DarkRed", 139, 0, 0), +WAVE_RGB_COLOR("DarkSalmon", 233, 150, 122), +WAVE_RGB_COLOR("DarkSeaGreen", 143, 188, 143), +WAVE_RGB_COLOR("DarkSeaGreen1", 193, 255, 193), +WAVE_RGB_COLOR("DarkSeaGreen2", 180, 238, 180), +WAVE_RGB_COLOR("DarkSeaGreen3", 155, 205, 155), +WAVE_RGB_COLOR("DarkSeaGreen4", 105, 139, 105), +WAVE_RGB_COLOR("DarkSlateBlue", 72, 61, 139), +WAVE_RGB_COLOR("DarkSlateGray", 47, 79, 79), +WAVE_RGB_COLOR("DarkSlateGray1", 151, 255, 255), +WAVE_RGB_COLOR("DarkSlateGray2", 141, 238, 238), +WAVE_RGB_COLOR("DarkSlateGray3", 121, 205, 205), +WAVE_RGB_COLOR("DarkSlateGray4", 82, 139, 139), +WAVE_RGB_COLOR("DarkSlateGrey", 47, 79, 79), +WAVE_RGB_COLOR("DarkTurquoise", 0, 206, 209), +WAVE_RGB_COLOR("DarkViolet", 148, 0, 211), +WAVE_RGB_COLOR("deep pink", 255, 20, 147), +WAVE_RGB_COLOR("deep sky blue", 0, 191, 255), +WAVE_RGB_COLOR("DeepPink", 255, 20, 147), +WAVE_RGB_COLOR("DeepPink1", 255, 20, 147), +WAVE_RGB_COLOR("DeepPink2", 238, 18, 137), +WAVE_RGB_COLOR("DeepPink3", 205, 16, 118), +WAVE_RGB_COLOR("DeepPink4", 139, 10, 80), +WAVE_RGB_COLOR("DeepSkyBlue", 0, 191, 255), +WAVE_RGB_COLOR("DeepSkyBlue1", 0, 191, 255), +WAVE_RGB_COLOR("DeepSkyBlue2", 0, 178, 238), +WAVE_RGB_COLOR("DeepSkyBlue3", 0, 154, 205), +WAVE_RGB_COLOR("DeepSkyBlue4", 0, 104, 139), +WAVE_RGB_COLOR("dim gray", 105, 105, 105), +WAVE_RGB_COLOR("dim grey", 105, 105, 105), +WAVE_RGB_COLOR("DimGray", 105, 105, 105), +WAVE_RGB_COLOR("DimGrey", 105, 105, 105), +WAVE_RGB_COLOR("dodger blue", 30, 144, 255), +WAVE_RGB_COLOR("DodgerBlue", 30, 144, 255), +WAVE_RGB_COLOR("DodgerBlue1", 30, 144, 255), +WAVE_RGB_COLOR("DodgerBlue2", 28, 134, 238), +WAVE_RGB_COLOR("DodgerBlue3", 24, 116, 205), +WAVE_RGB_COLOR("DodgerBlue4", 16, 78, 139), +WAVE_RGB_COLOR("firebrick", 178, 34, 34), +WAVE_RGB_COLOR("firebrick1", 255, 48, 48), +WAVE_RGB_COLOR("firebrick2", 238, 44, 44), +WAVE_RGB_COLOR("firebrick3", 205, 38, 38), +WAVE_RGB_COLOR("firebrick4", 139, 26, 26), +WAVE_RGB_COLOR("floral white", 255, 250, 240), +WAVE_RGB_COLOR("FloralWhite", 255, 250, 240), +WAVE_RGB_COLOR("forest green", 34, 139, 34), +WAVE_RGB_COLOR("ForestGreen", 34, 139, 34), +WAVE_RGB_COLOR("gainsboro", 220, 220, 220), +WAVE_RGB_COLOR("ghost white", 248, 248, 255), +WAVE_RGB_COLOR("GhostWhite", 248, 248, 255), +WAVE_RGB_COLOR("gold", 255, 215, 0), +WAVE_RGB_COLOR("gold1", 255, 215, 0), +WAVE_RGB_COLOR("gold2", 238, 201, 0), +WAVE_RGB_COLOR("gold3", 205, 173, 0), +WAVE_RGB_COLOR("gold4", 139, 117, 0), +WAVE_RGB_COLOR("goldenrod", 218, 165, 32), +WAVE_RGB_COLOR("goldenrod1", 255, 193, 37), +WAVE_RGB_COLOR("goldenrod2", 238, 180, 34), +WAVE_RGB_COLOR("goldenrod3", 205, 155, 29), +WAVE_RGB_COLOR("goldenrod4", 139, 105, 20), +WAVE_RGB_COLOR("gray", 190, 190, 190), +WAVE_RGB_COLOR("gray0", 0, 0, 0), +WAVE_RGB_COLOR("gray1", 3, 3, 3), +WAVE_RGB_COLOR("gray10", 26, 26, 26), +WAVE_RGB_COLOR("gray100", 255, 255, 255), +WAVE_RGB_COLOR("gray11", 28, 28, 28), +WAVE_RGB_COLOR("gray12", 31, 31, 31), +WAVE_RGB_COLOR("gray13", 33, 33, 33), +WAVE_RGB_COLOR("gray14", 36, 36, 36), +WAVE_RGB_COLOR("gray15", 38, 38, 38), +WAVE_RGB_COLOR("gray16", 41, 41, 41), +WAVE_RGB_COLOR("gray17", 43, 43, 43), +WAVE_RGB_COLOR("gray18", 46, 46, 46), +WAVE_RGB_COLOR("gray19", 48, 48, 48), +WAVE_RGB_COLOR("gray2", 5, 5, 5), +WAVE_RGB_COLOR("gray20", 51, 51, 51), +WAVE_RGB_COLOR("gray21", 54, 54, 54), +WAVE_RGB_COLOR("gray22", 56, 56, 56), +WAVE_RGB_COLOR("gray23", 59, 59, 59), +WAVE_RGB_COLOR("gray24", 61, 61, 61), +WAVE_RGB_COLOR("gray25", 64, 64, 64), +WAVE_RGB_COLOR("gray26", 66, 66, 66), +WAVE_RGB_COLOR("gray27", 69, 69, 69), +WAVE_RGB_COLOR("gray28", 71, 71, 71), +WAVE_RGB_COLOR("gray29", 74, 74, 74), +WAVE_RGB_COLOR("gray3", 8, 8, 8), +WAVE_RGB_COLOR("gray30", 77, 77, 77), +WAVE_RGB_COLOR("gray31", 79, 79, 79), +WAVE_RGB_COLOR("gray32", 82, 82, 82), +WAVE_RGB_COLOR("gray33", 84, 84, 84), +WAVE_RGB_COLOR("gray34", 87, 87, 87), +WAVE_RGB_COLOR("gray35", 89, 89, 89), +WAVE_RGB_COLOR("gray36", 92, 92, 92), +WAVE_RGB_COLOR("gray37", 94, 94, 94), +WAVE_RGB_COLOR("gray38", 97, 97, 97), +WAVE_RGB_COLOR("gray39", 99, 99, 99), +WAVE_RGB_COLOR("gray4", 10, 10, 10), +WAVE_RGB_COLOR("gray40", 102, 102, 102), +WAVE_RGB_COLOR("gray41", 105, 105, 105), +WAVE_RGB_COLOR("gray42", 107, 107, 107), +WAVE_RGB_COLOR("gray43", 110, 110, 110), +WAVE_RGB_COLOR("gray44", 112, 112, 112), +WAVE_RGB_COLOR("gray45", 115, 115, 115), +WAVE_RGB_COLOR("gray46", 117, 117, 117), +WAVE_RGB_COLOR("gray47", 120, 120, 120), +WAVE_RGB_COLOR("gray48", 122, 122, 122), +WAVE_RGB_COLOR("gray49", 125, 125, 125), +WAVE_RGB_COLOR("gray5", 13, 13, 13), +WAVE_RGB_COLOR("gray50", 127, 127, 127), +WAVE_RGB_COLOR("gray51", 130, 130, 130), +WAVE_RGB_COLOR("gray52", 133, 133, 133), +WAVE_RGB_COLOR("gray53", 135, 135, 135), +WAVE_RGB_COLOR("gray54", 138, 138, 138), +WAVE_RGB_COLOR("gray55", 140, 140, 140), +WAVE_RGB_COLOR("gray56", 143, 143, 143), +WAVE_RGB_COLOR("gray57", 145, 145, 145), +WAVE_RGB_COLOR("gray58", 148, 148, 148), +WAVE_RGB_COLOR("gray59", 150, 150, 150), +WAVE_RGB_COLOR("gray6", 15, 15, 15), +WAVE_RGB_COLOR("gray60", 153, 153, 153), +WAVE_RGB_COLOR("gray61", 156, 156, 156), +WAVE_RGB_COLOR("gray62", 158, 158, 158), +WAVE_RGB_COLOR("gray63", 161, 161, 161), +WAVE_RGB_COLOR("gray64", 163, 163, 163), +WAVE_RGB_COLOR("gray65", 166, 166, 166), +WAVE_RGB_COLOR("gray66", 168, 168, 168), +WAVE_RGB_COLOR("gray67", 171, 171, 171), +WAVE_RGB_COLOR("gray68", 173, 173, 173), +WAVE_RGB_COLOR("gray69", 176, 176, 176), +WAVE_RGB_COLOR("gray7", 18, 18, 18), +WAVE_RGB_COLOR("gray70", 179, 179, 179), +WAVE_RGB_COLOR("gray71", 181, 181, 181), +WAVE_RGB_COLOR("gray72", 184, 184, 184), +WAVE_RGB_COLOR("gray73", 186, 186, 186), +WAVE_RGB_COLOR("gray74", 189, 189, 189), +WAVE_RGB_COLOR("gray75", 191, 191, 191), +WAVE_RGB_COLOR("gray76", 194, 194, 194), +WAVE_RGB_COLOR("gray77", 196, 196, 196), +WAVE_RGB_COLOR("gray78", 199, 199, 199), +WAVE_RGB_COLOR("gray79", 201, 201, 201), +WAVE_RGB_COLOR("gray8", 20, 20, 20), +WAVE_RGB_COLOR("gray80", 204, 204, 204), +WAVE_RGB_COLOR("gray81", 207, 207, 207), +WAVE_RGB_COLOR("gray82", 209, 209, 209), +WAVE_RGB_COLOR("gray83", 212, 212, 212), +WAVE_RGB_COLOR("gray84", 214, 214, 214), +WAVE_RGB_COLOR("gray85", 217, 217, 217), +WAVE_RGB_COLOR("gray86", 219, 219, 219), +WAVE_RGB_COLOR("gray87", 222, 222, 222), +WAVE_RGB_COLOR("gray88", 224, 224, 224), +WAVE_RGB_COLOR("gray89", 227, 227, 227), +WAVE_RGB_COLOR("gray9", 23, 23, 23), +WAVE_RGB_COLOR("gray90", 229, 229, 229), +WAVE_RGB_COLOR("gray91", 232, 232, 232), +WAVE_RGB_COLOR("gray92", 235, 235, 235), +WAVE_RGB_COLOR("gray93", 237, 237, 237), +WAVE_RGB_COLOR("gray94", 240, 240, 240), +WAVE_RGB_COLOR("gray95", 242, 242, 242), +WAVE_RGB_COLOR("gray96", 245, 245, 245), +WAVE_RGB_COLOR("gray97", 247, 247, 247), +WAVE_RGB_COLOR("gray98", 250, 250, 250), +WAVE_RGB_COLOR("gray99", 252, 252, 252), +WAVE_RGB_COLOR("green", 0, 255, 0), +WAVE_RGB_COLOR("green yellow", 173, 255, 47), +WAVE_RGB_COLOR("green1", 0, 255, 0), +WAVE_RGB_COLOR("green2", 0, 238, 0), +WAVE_RGB_COLOR("green3", 0, 205, 0), +WAVE_RGB_COLOR("green4", 0, 139, 0), +WAVE_RGB_COLOR("GreenYellow", 173, 255, 47), +WAVE_RGB_COLOR("grey", 190, 190, 190), +WAVE_RGB_COLOR("grey0", 0, 0, 0), +WAVE_RGB_COLOR("grey1", 3, 3, 3), +WAVE_RGB_COLOR("grey10", 26, 26, 26), +WAVE_RGB_COLOR("grey100", 255, 255, 255), +WAVE_RGB_COLOR("grey11", 28, 28, 28), +WAVE_RGB_COLOR("grey12", 31, 31, 31), +WAVE_RGB_COLOR("grey13", 33, 33, 33), +WAVE_RGB_COLOR("grey14", 36, 36, 36), +WAVE_RGB_COLOR("grey15", 38, 38, 38), +WAVE_RGB_COLOR("grey16", 41, 41, 41), +WAVE_RGB_COLOR("grey17", 43, 43, 43), +WAVE_RGB_COLOR("grey18", 46, 46, 46), +WAVE_RGB_COLOR("grey19", 48, 48, 48), +WAVE_RGB_COLOR("grey2", 5, 5, 5), +WAVE_RGB_COLOR("grey20", 51, 51, 51), +WAVE_RGB_COLOR("grey21", 54, 54, 54), +WAVE_RGB_COLOR("grey22", 56, 56, 56), +WAVE_RGB_COLOR("grey23", 59, 59, 59), +WAVE_RGB_COLOR("grey24", 61, 61, 61), +WAVE_RGB_COLOR("grey25", 64, 64, 64), +WAVE_RGB_COLOR("grey26", 66, 66, 66), +WAVE_RGB_COLOR("grey27", 69, 69, 69), +WAVE_RGB_COLOR("grey28", 71, 71, 71), +WAVE_RGB_COLOR("grey29", 74, 74, 74), +WAVE_RGB_COLOR("grey3", 8, 8, 8), +WAVE_RGB_COLOR("grey30", 77, 77, 77), +WAVE_RGB_COLOR("grey31", 79, 79, 79), +WAVE_RGB_COLOR("grey32", 82, 82, 82), +WAVE_RGB_COLOR("grey33", 84, 84, 84), +WAVE_RGB_COLOR("grey34", 87, 87, 87), +WAVE_RGB_COLOR("grey35", 89, 89, 89), +WAVE_RGB_COLOR("grey36", 92, 92, 92), +WAVE_RGB_COLOR("grey37", 94, 94, 94), +WAVE_RGB_COLOR("grey38", 97, 97, 97), +WAVE_RGB_COLOR("grey39", 99, 99, 99), +WAVE_RGB_COLOR("grey4", 10, 10, 10), +WAVE_RGB_COLOR("grey40", 102, 102, 102), +WAVE_RGB_COLOR("grey41", 105, 105, 105), +WAVE_RGB_COLOR("grey42", 107, 107, 107), +WAVE_RGB_COLOR("grey43", 110, 110, 110), +WAVE_RGB_COLOR("grey44", 112, 112, 112), +WAVE_RGB_COLOR("grey45", 115, 115, 115), +WAVE_RGB_COLOR("grey46", 117, 117, 117), +WAVE_RGB_COLOR("grey47", 120, 120, 120), +WAVE_RGB_COLOR("grey48", 122, 122, 122), +WAVE_RGB_COLOR("grey49", 125, 125, 125), +WAVE_RGB_COLOR("grey5", 13, 13, 13), +WAVE_RGB_COLOR("grey50", 127, 127, 127), +WAVE_RGB_COLOR("grey51", 130, 130, 130), +WAVE_RGB_COLOR("grey52", 133, 133, 133), +WAVE_RGB_COLOR("grey53", 135, 135, 135), +WAVE_RGB_COLOR("grey54", 138, 138, 138), +WAVE_RGB_COLOR("grey55", 140, 140, 140), +WAVE_RGB_COLOR("grey56", 143, 143, 143), +WAVE_RGB_COLOR("grey57", 145, 145, 145), +WAVE_RGB_COLOR("grey58", 148, 148, 148), +WAVE_RGB_COLOR("grey59", 150, 150, 150), +WAVE_RGB_COLOR("grey6", 15, 15, 15), +WAVE_RGB_COLOR("grey60", 153, 153, 153), +WAVE_RGB_COLOR("grey61", 156, 156, 156), +WAVE_RGB_COLOR("grey62", 158, 158, 158), +WAVE_RGB_COLOR("grey63", 161, 161, 161), +WAVE_RGB_COLOR("grey64", 163, 163, 163), +WAVE_RGB_COLOR("grey65", 166, 166, 166), +WAVE_RGB_COLOR("grey66", 168, 168, 168), +WAVE_RGB_COLOR("grey67", 171, 171, 171), +WAVE_RGB_COLOR("grey68", 173, 173, 173), +WAVE_RGB_COLOR("grey69", 176, 176, 176), +WAVE_RGB_COLOR("grey7", 18, 18, 18), +WAVE_RGB_COLOR("grey70", 179, 179, 179), +WAVE_RGB_COLOR("grey71", 181, 181, 181), +WAVE_RGB_COLOR("grey72", 184, 184, 184), +WAVE_RGB_COLOR("grey73", 186, 186, 186), +WAVE_RGB_COLOR("grey74", 189, 189, 189), +WAVE_RGB_COLOR("grey75", 191, 191, 191), +WAVE_RGB_COLOR("grey76", 194, 194, 194), +WAVE_RGB_COLOR("grey77", 196, 196, 196), +WAVE_RGB_COLOR("grey78", 199, 199, 199), +WAVE_RGB_COLOR("grey79", 201, 201, 201), +WAVE_RGB_COLOR("grey8", 20, 20, 20), +WAVE_RGB_COLOR("grey80", 204, 204, 204), +WAVE_RGB_COLOR("grey81", 207, 207, 207), +WAVE_RGB_COLOR("grey82", 209, 209, 209), +WAVE_RGB_COLOR("grey83", 212, 212, 212), +WAVE_RGB_COLOR("grey84", 214, 214, 214), +WAVE_RGB_COLOR("grey85", 217, 217, 217), +WAVE_RGB_COLOR("grey86", 219, 219, 219), +WAVE_RGB_COLOR("grey87", 222, 222, 222), +WAVE_RGB_COLOR("grey88", 224, 224, 224), +WAVE_RGB_COLOR("grey89", 227, 227, 227), +WAVE_RGB_COLOR("grey9", 23, 23, 23), +WAVE_RGB_COLOR("grey90", 229, 229, 229), +WAVE_RGB_COLOR("grey91", 232, 232, 232), +WAVE_RGB_COLOR("grey92", 235, 235, 235), +WAVE_RGB_COLOR("grey93", 237, 237, 237), +WAVE_RGB_COLOR("grey94", 240, 240, 240), +WAVE_RGB_COLOR("grey95", 242, 242, 242), +WAVE_RGB_COLOR("grey96", 245, 245, 245), +WAVE_RGB_COLOR("grey97", 247, 247, 247), +WAVE_RGB_COLOR("grey98", 250, 250, 250), +WAVE_RGB_COLOR("grey99", 252, 252, 252), +WAVE_RGB_COLOR("honeydew", 240, 255, 240), +WAVE_RGB_COLOR("honeydew1", 240, 255, 240), +WAVE_RGB_COLOR("honeydew2", 224, 238, 224), +WAVE_RGB_COLOR("honeydew3", 193, 205, 193), +WAVE_RGB_COLOR("honeydew4", 131, 139, 131), +WAVE_RGB_COLOR("hot pink", 255, 105, 180), +WAVE_RGB_COLOR("HotPink", 255, 105, 180), +WAVE_RGB_COLOR("HotPink1", 255, 110, 180), +WAVE_RGB_COLOR("HotPink2", 238, 106, 167), +WAVE_RGB_COLOR("HotPink3", 205, 96, 144), +WAVE_RGB_COLOR("HotPink4", 139, 58, 98), +WAVE_RGB_COLOR("indian red", 205, 92, 92), +WAVE_RGB_COLOR("IndianRed", 205, 92, 92), +WAVE_RGB_COLOR("IndianRed1", 255, 106, 106), +WAVE_RGB_COLOR("IndianRed2", 238, 99, 99), +WAVE_RGB_COLOR("IndianRed3", 205, 85, 85), +WAVE_RGB_COLOR("IndianRed4", 139, 58, 58), +WAVE_RGB_COLOR("ivory", 255, 255, 240), +WAVE_RGB_COLOR("ivory1", 255, 255, 240), +WAVE_RGB_COLOR("ivory2", 238, 238, 224), +WAVE_RGB_COLOR("ivory3", 205, 205, 193), +WAVE_RGB_COLOR("ivory4", 139, 139, 131), +WAVE_RGB_COLOR("khaki", 240, 230, 140), +WAVE_RGB_COLOR("khaki1", 255, 246, 143), +WAVE_RGB_COLOR("khaki2", 238, 230, 133), +WAVE_RGB_COLOR("khaki3", 205, 198, 115), +WAVE_RGB_COLOR("khaki4", 139, 134, 78), +WAVE_RGB_COLOR("lavender", 230, 230, 250), +WAVE_RGB_COLOR("lavender blush", 255, 240, 245), +WAVE_RGB_COLOR("LavenderBlush", 255, 240, 245), +WAVE_RGB_COLOR("LavenderBlush1", 255, 240, 245), +WAVE_RGB_COLOR("LavenderBlush2", 238, 224, 229), +WAVE_RGB_COLOR("LavenderBlush3", 205, 193, 197), +WAVE_RGB_COLOR("LavenderBlush4", 139, 131, 134), +WAVE_RGB_COLOR("lawn green", 124, 252, 0), +WAVE_RGB_COLOR("LawnGreen", 124, 252, 0), +WAVE_RGB_COLOR("lemon chiffon", 255, 250, 205), +WAVE_RGB_COLOR("LemonChiffon", 255, 250, 205), +WAVE_RGB_COLOR("LemonChiffon1", 255, 250, 205), +WAVE_RGB_COLOR("LemonChiffon2", 238, 233, 191), +WAVE_RGB_COLOR("LemonChiffon3", 205, 201, 165), +WAVE_RGB_COLOR("LemonChiffon4", 139, 137, 112), +WAVE_RGB_COLOR("light blue", 173, 216, 230), +WAVE_RGB_COLOR("light coral", 240, 128, 128), +WAVE_RGB_COLOR("light cyan", 224, 255, 255), +WAVE_RGB_COLOR("light goldenrod", 238, 221, 130), +WAVE_RGB_COLOR("light goldenrod yellow", 250, 250, 210), +WAVE_RGB_COLOR("light gray", 211, 211, 211), +WAVE_RGB_COLOR("light green", 144, 238, 144), +WAVE_RGB_COLOR("light grey", 211, 211, 211), +WAVE_RGB_COLOR("light pink", 255, 182, 193), +WAVE_RGB_COLOR("light salmon", 255, 160, 122), +WAVE_RGB_COLOR("light sea green", 32, 178, 170), +WAVE_RGB_COLOR("light sky blue", 135, 206, 250), +WAVE_RGB_COLOR("light slate blue", 132, 112, 255), +WAVE_RGB_COLOR("light slate gray", 119, 136, 153), +WAVE_RGB_COLOR("light slate grey", 119, 136, 153), +WAVE_RGB_COLOR("light steel blue", 176, 196, 222), +WAVE_RGB_COLOR("light yellow", 255, 255, 224), +WAVE_RGB_COLOR("LightBlue", 173, 216, 230), +WAVE_RGB_COLOR("LightBlue1", 191, 239, 255), +WAVE_RGB_COLOR("LightBlue2", 178, 223, 238), +WAVE_RGB_COLOR("LightBlue3", 154, 192, 205), +WAVE_RGB_COLOR("LightBlue4", 104, 131, 139), +WAVE_RGB_COLOR("LightCoral", 240, 128, 128), +WAVE_RGB_COLOR("LightCyan", 224, 255, 255), +WAVE_RGB_COLOR("LightCyan1", 224, 255, 255), +WAVE_RGB_COLOR("LightCyan2", 209, 238, 238), +WAVE_RGB_COLOR("LightCyan3", 180, 205, 205), +WAVE_RGB_COLOR("LightCyan4", 122, 139, 139), +WAVE_RGB_COLOR("LightGoldenrod", 238, 221, 130), +WAVE_RGB_COLOR("LightGoldenrod1", 255, 236, 139), +WAVE_RGB_COLOR("LightGoldenrod2", 238, 220, 130), +WAVE_RGB_COLOR("LightGoldenrod3", 205, 190, 112), +WAVE_RGB_COLOR("LightGoldenrod4", 139, 129, 76), +WAVE_RGB_COLOR("LightGoldenrodYellow", 250, 250, 210), +WAVE_RGB_COLOR("LightGray", 211, 211, 211), +WAVE_RGB_COLOR("LightGreen", 144, 238, 144), +WAVE_RGB_COLOR("LightGrey", 211, 211, 211), +WAVE_RGB_COLOR("LightPink", 255, 182, 193), +WAVE_RGB_COLOR("LightPink1", 255, 174, 185), +WAVE_RGB_COLOR("LightPink2", 238, 162, 173), +WAVE_RGB_COLOR("LightPink3", 205, 140, 149), +WAVE_RGB_COLOR("LightPink4", 139, 95, 101), +WAVE_RGB_COLOR("LightSalmon", 255, 160, 122), +WAVE_RGB_COLOR("LightSalmon1", 255, 160, 122), +WAVE_RGB_COLOR("LightSalmon2", 238, 149, 114), +WAVE_RGB_COLOR("LightSalmon3", 205, 129, 98), +WAVE_RGB_COLOR("LightSalmon4", 139, 87, 66), +WAVE_RGB_COLOR("LightSeaGreen", 32, 178, 170), +WAVE_RGB_COLOR("LightSkyBlue", 135, 206, 250), +WAVE_RGB_COLOR("LightSkyBlue1", 176, 226, 255), +WAVE_RGB_COLOR("LightSkyBlue2", 164, 211, 238), +WAVE_RGB_COLOR("LightSkyBlue3", 141, 182, 205), +WAVE_RGB_COLOR("LightSkyBlue4", 96, 123, 139), +WAVE_RGB_COLOR("LightSlateBlue", 132, 112, 255), +WAVE_RGB_COLOR("LightSlateGray", 119, 136, 153), +WAVE_RGB_COLOR("LightSlateGrey", 119, 136, 153), +WAVE_RGB_COLOR("LightSteelBlue", 176, 196, 222), +WAVE_RGB_COLOR("LightSteelBlue1", 202, 225, 255), +WAVE_RGB_COLOR("LightSteelBlue2", 188, 210, 238), +WAVE_RGB_COLOR("LightSteelBlue3", 162, 181, 205), +WAVE_RGB_COLOR("LightSteelBlue4", 110, 123, 139), +WAVE_RGB_COLOR("LightYellow", 255, 255, 224), +WAVE_RGB_COLOR("LightYellow1", 255, 255, 224), +WAVE_RGB_COLOR("LightYellow2", 238, 238, 209), +WAVE_RGB_COLOR("LightYellow3", 205, 205, 180), +WAVE_RGB_COLOR("LightYellow4", 139, 139, 122), +WAVE_RGB_COLOR("lime green", 50, 205, 50), +WAVE_RGB_COLOR("LimeGreen", 50, 205, 50), +WAVE_RGB_COLOR("linen", 250, 240, 230), +WAVE_RGB_COLOR("magenta", 255, 0, 255), +WAVE_RGB_COLOR("magenta1", 255, 0, 255), +WAVE_RGB_COLOR("magenta2", 238, 0, 238), +WAVE_RGB_COLOR("magenta3", 205, 0, 205), +WAVE_RGB_COLOR("magenta4", 139, 0, 139), +WAVE_RGB_COLOR("maroon", 176, 48, 96), +WAVE_RGB_COLOR("maroon1", 255, 52, 179), +WAVE_RGB_COLOR("maroon2", 238, 48, 167), +WAVE_RGB_COLOR("maroon3", 205, 41, 144), +WAVE_RGB_COLOR("maroon4", 139, 28, 98), +WAVE_RGB_COLOR("medium aquamarine", 102, 205, 170), +WAVE_RGB_COLOR("medium blue", 0, 0, 205), +WAVE_RGB_COLOR("medium orchid", 186, 85, 211), +WAVE_RGB_COLOR("medium purple", 147, 112, 219), +WAVE_RGB_COLOR("medium sea green", 60, 179, 113), +WAVE_RGB_COLOR("medium slate blue", 123, 104, 238), +WAVE_RGB_COLOR("medium spring green", 0, 250, 154), +WAVE_RGB_COLOR("medium turquoise", 72, 209, 204), +WAVE_RGB_COLOR("medium violet red", 199, 21, 133), +WAVE_RGB_COLOR("MediumAquamarine", 102, 205, 170), +WAVE_RGB_COLOR("MediumBlue", 0, 0, 205), +WAVE_RGB_COLOR("MediumOrchid", 186, 85, 211), +WAVE_RGB_COLOR("MediumOrchid1", 224, 102, 255), +WAVE_RGB_COLOR("MediumOrchid2", 209, 95, 238), +WAVE_RGB_COLOR("MediumOrchid3", 180, 82, 205), +WAVE_RGB_COLOR("MediumOrchid4", 122, 55, 139), +WAVE_RGB_COLOR("MediumPurple", 147, 112, 219), +WAVE_RGB_COLOR("MediumPurple1", 171, 130, 255), +WAVE_RGB_COLOR("MediumPurple2", 159, 121, 238), +WAVE_RGB_COLOR("MediumPurple3", 137, 104, 205), +WAVE_RGB_COLOR("MediumPurple4", 93, 71, 139), +WAVE_RGB_COLOR("MediumSeaGreen", 60, 179, 113), +WAVE_RGB_COLOR("MediumSlateBlue", 123, 104, 238), +WAVE_RGB_COLOR("MediumSpringGreen", 0, 250, 154), +WAVE_RGB_COLOR("MediumTurquoise", 72, 209, 204), +WAVE_RGB_COLOR("MediumVioletRed", 199, 21, 133), +WAVE_RGB_COLOR("midnight blue", 25, 25, 112), +WAVE_RGB_COLOR("MidnightBlue", 25, 25, 112), +WAVE_RGB_COLOR("mint cream", 245, 255, 250), +WAVE_RGB_COLOR("MintCream", 245, 255, 250), +WAVE_RGB_COLOR("misty rose", 255, 228, 225), +WAVE_RGB_COLOR("MistyRose", 255, 228, 225), +WAVE_RGB_COLOR("MistyRose1", 255, 228, 225), +WAVE_RGB_COLOR("MistyRose2", 238, 213, 210), +WAVE_RGB_COLOR("MistyRose3", 205, 183, 181), +WAVE_RGB_COLOR("MistyRose4", 139, 125, 123), +WAVE_RGB_COLOR("moccasin", 255, 228, 181), +WAVE_RGB_COLOR("navajo white", 255, 222, 173), +WAVE_RGB_COLOR("NavajoWhite", 255, 222, 173), +WAVE_RGB_COLOR("NavajoWhite1", 255, 222, 173), +WAVE_RGB_COLOR("NavajoWhite2", 238, 207, 161), +WAVE_RGB_COLOR("NavajoWhite3", 205, 179, 139), +WAVE_RGB_COLOR("NavajoWhite4", 139, 121, 94), +WAVE_RGB_COLOR("navy", 0, 0, 128), +WAVE_RGB_COLOR("navy blue", 0, 0, 128), +WAVE_RGB_COLOR("NavyBlue", 0, 0, 128), +WAVE_RGB_COLOR("old lace", 253, 245, 230), +WAVE_RGB_COLOR("OldLace", 253, 245, 230), +WAVE_RGB_COLOR("olive drab", 107, 142, 35), +WAVE_RGB_COLOR("OliveDrab", 107, 142, 35), +WAVE_RGB_COLOR("OliveDrab1", 192, 255, 62), +WAVE_RGB_COLOR("OliveDrab2", 179, 238, 58), +WAVE_RGB_COLOR("OliveDrab3", 154, 205, 50), +WAVE_RGB_COLOR("OliveDrab4", 105, 139, 34), +WAVE_RGB_COLOR("orange", 255, 165, 0), +WAVE_RGB_COLOR("orange red", 255, 69, 0), +WAVE_RGB_COLOR("orange1", 255, 165, 0), +WAVE_RGB_COLOR("orange2", 238, 154, 0), +WAVE_RGB_COLOR("orange3", 205, 133, 0), +WAVE_RGB_COLOR("orange4", 139, 90, 0), +WAVE_RGB_COLOR("OrangeRed", 255, 69, 0), +WAVE_RGB_COLOR("OrangeRed1", 255, 69, 0), +WAVE_RGB_COLOR("OrangeRed2", 238, 64, 0), +WAVE_RGB_COLOR("OrangeRed3", 205, 55, 0), +WAVE_RGB_COLOR("OrangeRed4", 139, 37, 0), +WAVE_RGB_COLOR("orchid", 218, 112, 214), +WAVE_RGB_COLOR("orchid1", 255, 131, 250), +WAVE_RGB_COLOR("orchid2", 238, 122, 233), +WAVE_RGB_COLOR("orchid3", 205, 105, 201), +WAVE_RGB_COLOR("orchid4", 139, 71, 137), +WAVE_RGB_COLOR("pale goldenrod", 238, 232, 170), +WAVE_RGB_COLOR("pale green", 152, 251, 152), +WAVE_RGB_COLOR("pale turquoise", 175, 238, 238), +WAVE_RGB_COLOR("pale violet red", 219, 112, 147), +WAVE_RGB_COLOR("PaleGoldenrod", 238, 232, 170), +WAVE_RGB_COLOR("PaleGreen", 152, 251, 152), +WAVE_RGB_COLOR("PaleGreen1", 154, 255, 154), +WAVE_RGB_COLOR("PaleGreen2", 144, 238, 144), +WAVE_RGB_COLOR("PaleGreen3", 124, 205, 124), +WAVE_RGB_COLOR("PaleGreen4", 84, 139, 84), +WAVE_RGB_COLOR("PaleTurquoise", 175, 238, 238), +WAVE_RGB_COLOR("PaleTurquoise1", 187, 255, 255), +WAVE_RGB_COLOR("PaleTurquoise2", 174, 238, 238), +WAVE_RGB_COLOR("PaleTurquoise3", 150, 205, 205), +WAVE_RGB_COLOR("PaleTurquoise4", 102, 139, 139), +WAVE_RGB_COLOR("PaleVioletRed", 219, 112, 147), +WAVE_RGB_COLOR("PaleVioletRed1", 255, 130, 171), +WAVE_RGB_COLOR("PaleVioletRed2", 238, 121, 159), +WAVE_RGB_COLOR("PaleVioletRed3", 205, 104, 137), +WAVE_RGB_COLOR("PaleVioletRed4", 139, 71, 93), +WAVE_RGB_COLOR("papaya whip", 255, 239, 213), +WAVE_RGB_COLOR("PapayaWhip", 255, 239, 213), +WAVE_RGB_COLOR("peach puff", 255, 218, 185), +WAVE_RGB_COLOR("PeachPuff", 255, 218, 185), +WAVE_RGB_COLOR("PeachPuff1", 255, 218, 185), +WAVE_RGB_COLOR("PeachPuff2", 238, 203, 173), +WAVE_RGB_COLOR("PeachPuff3", 205, 175, 149), +WAVE_RGB_COLOR("PeachPuff4", 139, 119, 101), +WAVE_RGB_COLOR("peru", 205, 133, 63), +WAVE_RGB_COLOR("pink", 255, 192, 203), +WAVE_RGB_COLOR("pink1", 255, 181, 197), +WAVE_RGB_COLOR("pink2", 238, 169, 184), +WAVE_RGB_COLOR("pink3", 205, 145, 158), +WAVE_RGB_COLOR("pink4", 139, 99, 108), +WAVE_RGB_COLOR("plum", 221, 160, 221), +WAVE_RGB_COLOR("plum1", 255, 187, 255), +WAVE_RGB_COLOR("plum2", 238, 174, 238), +WAVE_RGB_COLOR("plum3", 205, 150, 205), +WAVE_RGB_COLOR("plum4", 139, 102, 139), +WAVE_RGB_COLOR("powder blue", 176, 224, 230), +WAVE_RGB_COLOR("PowderBlue", 176, 224, 230), +WAVE_RGB_COLOR("purple", 160, 32, 240), +WAVE_RGB_COLOR("purple1", 155, 48, 255), +WAVE_RGB_COLOR("purple2", 145, 44, 238), +WAVE_RGB_COLOR("purple3", 125, 38, 205), +WAVE_RGB_COLOR("purple4", 85, 26, 139), +WAVE_RGB_COLOR("red", 255, 0, 0), +WAVE_RGB_COLOR("red1", 255, 0, 0), +WAVE_RGB_COLOR("red2", 238, 0, 0), +WAVE_RGB_COLOR("red3", 205, 0, 0), +WAVE_RGB_COLOR("red4", 139, 0, 0), +WAVE_RGB_COLOR("rosy brown", 188, 143, 143), +WAVE_RGB_COLOR("RosyBrown", 188, 143, 143), +WAVE_RGB_COLOR("RosyBrown1", 255, 193, 193), +WAVE_RGB_COLOR("RosyBrown2", 238, 180, 180), +WAVE_RGB_COLOR("RosyBrown3", 205, 155, 155), +WAVE_RGB_COLOR("RosyBrown4", 139, 105, 105), +WAVE_RGB_COLOR("royal blue", 65, 105, 225), +WAVE_RGB_COLOR("RoyalBlue", 65, 105, 225), +WAVE_RGB_COLOR("RoyalBlue1", 72, 118, 255), +WAVE_RGB_COLOR("RoyalBlue2", 67, 110, 238), +WAVE_RGB_COLOR("RoyalBlue3", 58, 95, 205), +WAVE_RGB_COLOR("RoyalBlue4", 39, 64, 139), +WAVE_RGB_COLOR("saddle brown", 139, 69, 19), +WAVE_RGB_COLOR("SaddleBrown", 139, 69, 19), +WAVE_RGB_COLOR("salmon", 250, 128, 114), +WAVE_RGB_COLOR("salmon1", 255, 140, 105), +WAVE_RGB_COLOR("salmon2", 238, 130, 98), +WAVE_RGB_COLOR("salmon3", 205, 112, 84), +WAVE_RGB_COLOR("salmon4", 139, 76, 57), +WAVE_RGB_COLOR("sandy brown", 244, 164, 96), +WAVE_RGB_COLOR("SandyBrown", 244, 164, 96), +WAVE_RGB_COLOR("sea green", 46, 139, 87), +WAVE_RGB_COLOR("SeaGreen", 46, 139, 87), +WAVE_RGB_COLOR("SeaGreen1", 84, 255, 159), +WAVE_RGB_COLOR("SeaGreen2", 78, 238, 148), +WAVE_RGB_COLOR("SeaGreen3", 67, 205, 128), +WAVE_RGB_COLOR("SeaGreen4", 46, 139, 87), +WAVE_RGB_COLOR("seashell", 255, 245, 238), +WAVE_RGB_COLOR("seashell1", 255, 245, 238), +WAVE_RGB_COLOR("seashell2", 238, 229, 222), +WAVE_RGB_COLOR("seashell3", 205, 197, 191), +WAVE_RGB_COLOR("seashell4", 139, 134, 130), +WAVE_RGB_COLOR("sienna", 160, 82, 45), +WAVE_RGB_COLOR("sienna1", 255, 130, 71), +WAVE_RGB_COLOR("sienna2", 238, 121, 66), +WAVE_RGB_COLOR("sienna3", 205, 104, 57), +WAVE_RGB_COLOR("sienna4", 139, 71, 38), +WAVE_RGB_COLOR("sky blue", 135, 206, 235), +WAVE_RGB_COLOR("SkyBlue", 135, 206, 235), +WAVE_RGB_COLOR("SkyBlue1", 135, 206, 255), +WAVE_RGB_COLOR("SkyBlue2", 126, 192, 238), +WAVE_RGB_COLOR("SkyBlue3", 108, 166, 205), +WAVE_RGB_COLOR("SkyBlue4", 74, 112, 139), +WAVE_RGB_COLOR("slate blue", 106, 90, 205), +WAVE_RGB_COLOR("slate gray", 112, 128, 144), +WAVE_RGB_COLOR("slate grey", 112, 128, 144), +WAVE_RGB_COLOR("SlateBlue", 106, 90, 205), +WAVE_RGB_COLOR("SlateBlue1", 131, 111, 255), +WAVE_RGB_COLOR("SlateBlue2", 122, 103, 238), +WAVE_RGB_COLOR("SlateBlue3", 105, 89, 205), +WAVE_RGB_COLOR("SlateBlue4", 71, 60, 139), +WAVE_RGB_COLOR("SlateGray", 112, 128, 144), +WAVE_RGB_COLOR("SlateGray1", 198, 226, 255), +WAVE_RGB_COLOR("SlateGray2", 185, 211, 238), +WAVE_RGB_COLOR("SlateGray3", 159, 182, 205), +WAVE_RGB_COLOR("SlateGray4", 108, 123, 139), +WAVE_RGB_COLOR("SlateGrey", 112, 128, 144), +WAVE_RGB_COLOR("snow", 255, 250, 250), +WAVE_RGB_COLOR("snow1", 255, 250, 250), +WAVE_RGB_COLOR("snow2", 238, 233, 233), +WAVE_RGB_COLOR("snow3", 205, 201, 201), +WAVE_RGB_COLOR("snow4", 139, 137, 137), +WAVE_RGB_COLOR("spring green", 0, 255, 127), +WAVE_RGB_COLOR("SpringGreen", 0, 255, 127), +WAVE_RGB_COLOR("SpringGreen1", 0, 255, 127), +WAVE_RGB_COLOR("SpringGreen2", 0, 238, 118), +WAVE_RGB_COLOR("SpringGreen3", 0, 205, 102), +WAVE_RGB_COLOR("SpringGreen4", 0, 139, 69), +WAVE_RGB_COLOR("steel blue", 70, 130, 180), +WAVE_RGB_COLOR("SteelBlue", 70, 130, 180), +WAVE_RGB_COLOR("SteelBlue1", 99, 184, 255), +WAVE_RGB_COLOR("SteelBlue2", 92, 172, 238), +WAVE_RGB_COLOR("SteelBlue3", 79, 148, 205), +WAVE_RGB_COLOR("SteelBlue4", 54, 100, 139), +WAVE_RGB_COLOR("tan", 210, 180, 140), +WAVE_RGB_COLOR("tan1", 255, 165, 79), +WAVE_RGB_COLOR("tan2", 238, 154, 73), +WAVE_RGB_COLOR("tan3", 205, 133, 63), +WAVE_RGB_COLOR("tan4", 139, 90, 43), +WAVE_RGB_COLOR("thistle", 216, 191, 216), +WAVE_RGB_COLOR("thistle1", 255, 225, 255), +WAVE_RGB_COLOR("thistle2", 238, 210, 238), +WAVE_RGB_COLOR("thistle3", 205, 181, 205), +WAVE_RGB_COLOR("thistle4", 139, 123, 139), +WAVE_RGB_COLOR("tomato", 255, 99, 71), +WAVE_RGB_COLOR("tomato1", 255, 99, 71), +WAVE_RGB_COLOR("tomato2", 238, 92, 66), +WAVE_RGB_COLOR("tomato3", 205, 79, 57), +WAVE_RGB_COLOR("tomato4", 139, 54, 38), +WAVE_RGB_COLOR("turquoise", 64, 224, 208), +WAVE_RGB_COLOR("turquoise1", 0, 245, 255), +WAVE_RGB_COLOR("turquoise2", 0, 229, 238), +WAVE_RGB_COLOR("turquoise3", 0, 197, 205), +WAVE_RGB_COLOR("turquoise4", 0, 134, 139), +WAVE_RGB_COLOR("violet", 238, 130, 238), +WAVE_RGB_COLOR("violet red", 208, 32, 144), +WAVE_RGB_COLOR("VioletRed", 208, 32, 144), +WAVE_RGB_COLOR("VioletRed1", 255, 62, 150), +WAVE_RGB_COLOR("VioletRed2", 238, 58, 140), +WAVE_RGB_COLOR("VioletRed3", 205, 50, 120), +WAVE_RGB_COLOR("VioletRed4", 139, 34, 82), +WAVE_RGB_COLOR("wheat", 245, 222, 179), +WAVE_RGB_COLOR("wheat1", 255, 231, 186), +WAVE_RGB_COLOR("wheat2", 238, 216, 174), +WAVE_RGB_COLOR("wheat3", 205, 186, 150), +WAVE_RGB_COLOR("wheat4", 139, 126, 102), +WAVE_RGB_COLOR("white", 255, 255, 255), +WAVE_RGB_COLOR("white smoke", 245, 245, 245), +WAVE_RGB_COLOR("WhiteSmoke", 245, 245, 245), +WAVE_RGB_COLOR("yellow", 255, 255, 0), +WAVE_RGB_COLOR("yellow green", 154, 205, 50), +WAVE_RGB_COLOR("yellow1", 255, 255, 0), +WAVE_RGB_COLOR("yellow2", 238, 238, 0), +WAVE_RGB_COLOR("yellow3", 205, 205, 0), +WAVE_RGB_COLOR("yellow4", 139, 139, 0), +WAVE_RGB_COLOR("YellowGreen", 154, 205, 50), +}; +''' \ No newline at end of file diff --git a/dev/sim/gtkwave/gtkf-gprr.py b/dev/sim/gtkwave/gtkf-gprr.py new file mode 100755 index 0000000..ef834f6 --- /dev/null +++ b/dev/sim/gtkwave/gtkf-gprr.py @@ -0,0 +1,45 @@ +#!/usr/bin/python3 +# gtkwave process filter +# +# display gpr adr/dat (read, 1 cyc access) +# +# format=binary so justification and data length don't matter + +import sys + +color = '' + +fi = sys.stdin +fo = sys.stdout +fe = sys.stderr + +def dbg(m): + fe.write(m + '\n') + fe.flush() + +def main(): + + lastAdr = -1 + + while True: + + line = fi.readline() + if not line: + return 0 + + try: + if lastAdr == -1: + fo.write(f'{color}XX:XXXXXXXXXXXXXXXX\n') + else: + fo.write(f'{color}{lastAdr:02X}:{int(line[6:70],2):016X}\n') + lastAdr = int(line[0:6],2) + except Exception as e: + fe.write('error!\n') + fe.write(str(e)) + fe.flush() + fo.write('filter error!\n') + + fo.flush() + +if __name__ == '__main__': + sys.exit(main()) diff --git a/dev/sim/gtkwave/gtkf-gprw.py b/dev/sim/gtkwave/gtkf-gprw.py new file mode 100755 index 0000000..9db3944 --- /dev/null +++ b/dev/sim/gtkwave/gtkf-gprw.py @@ -0,0 +1,43 @@ +#!/usr/bin/python3 +# gtkwave process filter +# +# display gpr we/adr/dat +# +# format=binary so justification and data length don't matter + +import sys + +#colorI = '?LightGray?' +colorI = '' +colorV = '?DarkBlue?' + +fi = sys.stdin +fo = sys.stdout +fe = sys.stderr + +def dbg(m): + fe.write(m + '\n') + fe.flush() + +def main(): + + while True: + + line = fi.readline() + if not line: + return 0 + + try: + if line[0] == '0': + fo.write(f'{colorI}{int(line[1:7],2):02X}:{int(line[7:71],2):016X}\n') + else: + fo.write(f'{colorV}{int(line[1:7],2):02X}:{int(line[7:71],2):016X}\n') + except Exception as e: + fe.write('error!\n') + fe.write(str(e)) + fo.write('filter error!\n') + + fo.flush() + +if __name__ == '__main__': + sys.exit(main()) diff --git a/dev/sim/gtkwave/gtkf-ibuf.py b/dev/sim/gtkwave/gtkf-ibuf.py new file mode 100755 index 0000000..b70be0c --- /dev/null +++ b/dev/sim/gtkwave/gtkf-ibuf.py @@ -0,0 +1,37 @@ +#!/usr/bin/python3 +# gtkwave process filter +# +# split binary ibuf entry into op/bta/ifar + +import sys + +fi = sys.stdin +fo = sys.stdout +fe = sys.stderr + +def dbg(m): + fe.write(m + '\n') + fe.flush() + +# ppc 0:31, ppc+ 32:69, bta 70:89, ifar 90:109 +ibufInstrWidth = 70 +effIFARWidth = 20 +ibufIFARWidth = 20 + +def main(): + + while True: + + line = fi.readline() + if not line: + return 0 + + try: + fo.write(f'{int(line[0:32],2):08X} a={int(line[ibufInstrWidth+effIFARWidth:],2)<<2:08X} m={int(line[32:ibufInstrWidth],2):10X} t={int(line[ibufInstrWidth:ibufInstrWidth+effIFARWidth],2)<<2:08X}\n') + except: + fo.write('\n') + + fo.flush() + +if __name__ == '__main__': + sys.exit(main()) diff --git a/dev/sim/gtkwave/gtkf-nop.py b/dev/sim/gtkwave/gtkf-nop.py new file mode 100755 index 0000000..e701a05 --- /dev/null +++ b/dev/sim/gtkwave/gtkf-nop.py @@ -0,0 +1,30 @@ +#!/usr/bin/python3 +# gtkwave process filter + +# does nothing + +import sys + +fi = sys.stdin +fo = sys.stdout +fe = sys.stderr + +debug = False + +def dbg(m): + if debug: + fe.write(m + '\n') + fe.flush() + +def main(): + + while True: + + l = fi.readline() + if not l: + return 0 + fo.write(f'{l}\n') + fo.flush() + +if __name__ == '__main__': + sys.exit(main()) diff --git a/dev/sim/gtkwave/gtkf-ppc.py b/dev/sim/gtkwave/gtkf-ppc.py new file mode 100755 index 0000000..91b841d --- /dev/null +++ b/dev/sim/gtkwave/gtkf-ppc.py @@ -0,0 +1,880 @@ +#!/usr/bin/python3 +# gtkwave process filter + +# add: +# pseudo op xlate (rlwinm->shift, etc.) + +import sys +import tempfile +import subprocess + +fi = sys.stdin +fo = sys.stdout +fe = sys.stderr + +debug = False + +def dbg(m): + if debug: + fe.write(m + '\n') + fe.flush() + +colors = { + #'default':'DeepSkyBlue', + 'default':'DarkGreen', + 'data':'DarkGray', + 'bctr':'DarkOrange', + 'x':'red' +} + +def dasm(op): + oo = tempfile.NamedTemporaryFile(delete=False, mode='w') + ai = tempfile.NamedTemporaryFile(delete=False, mode='w') + ai.write(f'.long 0x{op}\n') + ai.flush() + #subprocess.run(["powerpc-linux-gnu-as", "-mpower9", "-o", oo.name, ai.name]) + subprocess.run(["powerpc-linux-gnu-as", "-ma2", "-o", oo.name, ai.name]) + result = subprocess.run(["powerpc-linux-gnu-objdump", "-d", oo.name], capture_output=True) + lines = result.stdout.splitlines() + if len(lines) < 8: + return [f'0x{op}', ''] + l = result.stdout.splitlines()[-1] + tokens = l.decode().split('\t') + op = tokens[2].split() + if op[0] == '.long': + op = [f'0x{int(op[1], 16):08X}', ''] + else: + op = massage(op) + if len(op) > 1: + return [op[0], ' '.join(op[1:])] + else: + return [op[0], ' '] + +# beautify pseudo-ops [op operand1,operand2,...] +def massage(op, hexify=False): + # li r,i = li r,hex(i) + # slwi rx,ry,a = rlwinm rx,ry,a,0,31-a + # mtspr n,r = mtspr name,r + # mfspr r,n = mfspr r,name + + sprNames = { + '438': 'tens', + '446': 'tir', + '815': 'tar' + } + + if len(op) < 2: + return op + + ops = op[1].split(',') + if op[0] == 'li': + op = ['li', f'{ops[0]},0x{int(ops[1]):04X}'] + elif op[0] == 'rlwinm': + if int(ops[3]) == 0 and int(ops[4]) == 31-int(ops[2]): + op = ['slwi', f'{ops[0]},{ops[1]},{ops[2]}'] + elif op[0] == 'mfspr': + if ops[1] in sprNames: + op = ['mfspr', f'{ops[0]},{sprNames[ops[1]]}'] + elif op[0] == 'mtspr': + if ops[0] in sprNames: + op = ['mtspr', f'{sprNames[ops[0]]},{ops[1]}'] + + if hexify: + for i in range(len(ops)): + try: + if int(ops[i]) > 10: + ops[i] = f'0x{int(ops[i]):X}' + except: + pass + op[1] = ','.join(ops) + + return op + +def main(): + + while True: + + l = fi.readline() + + if not l: + return 0 + + if l[0] == 'x' or l[0] == 'z': + fo.write(f'?{colors["x"]}?X\n') + else: + t = dasm(l) + ins = t[0] + ops = t[1] + # could convert decimals > 10 to hex in operands + if ins[0:2] == '0x' and 'data' in colors: + color = colors['data'] + elif ins in colors: + color = colors[ins] + else: + color = colors['default'] + fo.write(f'?{color}?{ins} {ops}\n') + + fo.flush() + + +if __name__ == '__main__': + sys.exit(main()) + +''' +rgb.c from gtkwave + +static struct wave_rgb_color colors[] = { +WAVE_RGB_COLOR("alice blue", 240, 248, 255), +WAVE_RGB_COLOR("AliceBlue", 240, 248, 255), +WAVE_RGB_COLOR("antique white", 250, 235, 215), +WAVE_RGB_COLOR("AntiqueWhite", 250, 235, 215), +WAVE_RGB_COLOR("AntiqueWhite1", 255, 239, 219), +WAVE_RGB_COLOR("AntiqueWhite2", 238, 223, 204), +WAVE_RGB_COLOR("AntiqueWhite3", 205, 192, 176), +WAVE_RGB_COLOR("AntiqueWhite4", 139, 131, 120), +WAVE_RGB_COLOR("aquamarine", 127, 255, 212), +WAVE_RGB_COLOR("aquamarine1", 127, 255, 212), +WAVE_RGB_COLOR("aquamarine2", 118, 238, 198), +WAVE_RGB_COLOR("aquamarine3", 102, 205, 170), +WAVE_RGB_COLOR("aquamarine4", 69, 139, 116), +WAVE_RGB_COLOR("azure", 240, 255, 255), +WAVE_RGB_COLOR("azure1", 240, 255, 255), +WAVE_RGB_COLOR("azure2", 224, 238, 238), +WAVE_RGB_COLOR("azure3", 193, 205, 205), +WAVE_RGB_COLOR("azure4", 131, 139, 139), +WAVE_RGB_COLOR("beige", 245, 245, 220), +WAVE_RGB_COLOR("bisque", 255, 228, 196), +WAVE_RGB_COLOR("bisque1", 255, 228, 196), +WAVE_RGB_COLOR("bisque2", 238, 213, 183), +WAVE_RGB_COLOR("bisque3", 205, 183, 158), +WAVE_RGB_COLOR("bisque4", 139, 125, 107), +WAVE_RGB_COLOR("black", 0, 0, 0), +WAVE_RGB_COLOR("blanched almond", 255, 235, 205), +WAVE_RGB_COLOR("BlanchedAlmond", 255, 235, 205), +WAVE_RGB_COLOR("blue", 0, 0, 255), +WAVE_RGB_COLOR("blue violet", 138, 43, 226), +WAVE_RGB_COLOR("blue1", 0, 0, 255), +WAVE_RGB_COLOR("blue2", 0, 0, 238), +WAVE_RGB_COLOR("blue3", 0, 0, 205), +WAVE_RGB_COLOR("blue4", 0, 0, 139), +WAVE_RGB_COLOR("BlueViolet", 138, 43, 226), +WAVE_RGB_COLOR("brown", 165, 42, 42), +WAVE_RGB_COLOR("brown1", 255, 64, 64), +WAVE_RGB_COLOR("brown2", 238, 59, 59), +WAVE_RGB_COLOR("brown3", 205, 51, 51), +WAVE_RGB_COLOR("brown4", 139, 35, 35), +WAVE_RGB_COLOR("burlywood", 222, 184, 135), +WAVE_RGB_COLOR("burlywood1", 255, 211, 155), +WAVE_RGB_COLOR("burlywood2", 238, 197, 145), +WAVE_RGB_COLOR("burlywood3", 205, 170, 125), +WAVE_RGB_COLOR("burlywood4", 139, 115, 85), +WAVE_RGB_COLOR("cadet blue", 95, 158, 160), +WAVE_RGB_COLOR("CadetBlue", 95, 158, 160), +WAVE_RGB_COLOR("CadetBlue1", 152, 245, 255), +WAVE_RGB_COLOR("CadetBlue2", 142, 229, 238), +WAVE_RGB_COLOR("CadetBlue3", 122, 197, 205), +WAVE_RGB_COLOR("CadetBlue4", 83, 134, 139), +WAVE_RGB_COLOR("chartreuse", 127, 255, 0), +WAVE_RGB_COLOR("chartreuse1", 127, 255, 0), +WAVE_RGB_COLOR("chartreuse2", 118, 238, 0), +WAVE_RGB_COLOR("chartreuse3", 102, 205, 0), +WAVE_RGB_COLOR("chartreuse4", 69, 139, 0), +WAVE_RGB_COLOR("chocolate", 210, 105, 30), +WAVE_RGB_COLOR("chocolate1", 255, 127, 36), +WAVE_RGB_COLOR("chocolate2", 238, 118, 33), +WAVE_RGB_COLOR("chocolate3", 205, 102, 29), +WAVE_RGB_COLOR("chocolate4", 139, 69, 19), +WAVE_RGB_COLOR("coral", 255, 127, 80), +WAVE_RGB_COLOR("coral1", 255, 114, 86), +WAVE_RGB_COLOR("coral2", 238, 106, 80), +WAVE_RGB_COLOR("coral3", 205, 91, 69), +WAVE_RGB_COLOR("coral4", 139, 62, 47), +WAVE_RGB_COLOR("cornflower blue", 100, 149, 237), +WAVE_RGB_COLOR("CornflowerBlue", 100, 149, 237), +WAVE_RGB_COLOR("cornsilk", 255, 248, 220), +WAVE_RGB_COLOR("cornsilk1", 255, 248, 220), +WAVE_RGB_COLOR("cornsilk2", 238, 232, 205), +WAVE_RGB_COLOR("cornsilk3", 205, 200, 177), +WAVE_RGB_COLOR("cornsilk4", 139, 136, 120), +WAVE_RGB_COLOR("cyan", 0, 255, 255), +WAVE_RGB_COLOR("cyan1", 0, 255, 255), +WAVE_RGB_COLOR("cyan2", 0, 238, 238), +WAVE_RGB_COLOR("cyan3", 0, 205, 205), +WAVE_RGB_COLOR("cyan4", 0, 139, 139), +WAVE_RGB_COLOR("dark blue", 0, 0, 139), +WAVE_RGB_COLOR("dark cyan", 0, 139, 139), +WAVE_RGB_COLOR("dark goldenrod", 184, 134, 11), +WAVE_RGB_COLOR("dark gray", 169, 169, 169), +WAVE_RGB_COLOR("dark green", 0, 100, 0), +WAVE_RGB_COLOR("dark grey", 169, 169, 169), +WAVE_RGB_COLOR("dark khaki", 189, 183, 107), +WAVE_RGB_COLOR("dark magenta", 139, 0, 139), +WAVE_RGB_COLOR("dark olive green", 85, 107, 47), +WAVE_RGB_COLOR("dark orange", 255, 140, 0), +WAVE_RGB_COLOR("dark orchid", 153, 50, 204), +WAVE_RGB_COLOR("dark red", 139, 0, 0), +WAVE_RGB_COLOR("dark salmon", 233, 150, 122), +WAVE_RGB_COLOR("dark sea green", 143, 188, 143), +WAVE_RGB_COLOR("dark slate blue", 72, 61, 139), +WAVE_RGB_COLOR("dark slate gray", 47, 79, 79), +WAVE_RGB_COLOR("dark slate grey", 47, 79, 79), +WAVE_RGB_COLOR("dark turquoise", 0, 206, 209), +WAVE_RGB_COLOR("dark violet", 148, 0, 211), +WAVE_RGB_COLOR("DarkBlue", 0, 0, 139), +WAVE_RGB_COLOR("DarkCyan", 0, 139, 139), +WAVE_RGB_COLOR("DarkGoldenrod", 184, 134, 11), +WAVE_RGB_COLOR("DarkGoldenrod1", 255, 185, 15), +WAVE_RGB_COLOR("DarkGoldenrod2", 238, 173, 14), +WAVE_RGB_COLOR("DarkGoldenrod3", 205, 149, 12), +WAVE_RGB_COLOR("DarkGoldenrod4", 139, 101, 8), +WAVE_RGB_COLOR("DarkGray", 169, 169, 169), +WAVE_RGB_COLOR("DarkGreen", 0, 100, 0), +WAVE_RGB_COLOR("DarkGrey", 169, 169, 169), +WAVE_RGB_COLOR("DarkKhaki", 189, 183, 107), +WAVE_RGB_COLOR("DarkMagenta", 139, 0, 139), +WAVE_RGB_COLOR("DarkOliveGreen", 85, 107, 47), +WAVE_RGB_COLOR("DarkOliveGreen1", 202, 255, 112), +WAVE_RGB_COLOR("DarkOliveGreen2", 188, 238, 104), +WAVE_RGB_COLOR("DarkOliveGreen3", 162, 205, 90), +WAVE_RGB_COLOR("DarkOliveGreen4", 110, 139, 61), +WAVE_RGB_COLOR("DarkOrange", 255, 140, 0), +WAVE_RGB_COLOR("DarkOrange1", 255, 127, 0), +WAVE_RGB_COLOR("DarkOrange2", 238, 118, 0), +WAVE_RGB_COLOR("DarkOrange3", 205, 102, 0), +WAVE_RGB_COLOR("DarkOrange4", 139, 69, 0), +WAVE_RGB_COLOR("DarkOrchid", 153, 50, 204), +WAVE_RGB_COLOR("DarkOrchid1", 191, 62, 255), +WAVE_RGB_COLOR("DarkOrchid2", 178, 58, 238), +WAVE_RGB_COLOR("DarkOrchid3", 154, 50, 205), +WAVE_RGB_COLOR("DarkOrchid4", 104, 34, 139), +WAVE_RGB_COLOR("DarkRed", 139, 0, 0), +WAVE_RGB_COLOR("DarkSalmon", 233, 150, 122), +WAVE_RGB_COLOR("DarkSeaGreen", 143, 188, 143), +WAVE_RGB_COLOR("DarkSeaGreen1", 193, 255, 193), +WAVE_RGB_COLOR("DarkSeaGreen2", 180, 238, 180), +WAVE_RGB_COLOR("DarkSeaGreen3", 155, 205, 155), +WAVE_RGB_COLOR("DarkSeaGreen4", 105, 139, 105), +WAVE_RGB_COLOR("DarkSlateBlue", 72, 61, 139), +WAVE_RGB_COLOR("DarkSlateGray", 47, 79, 79), +WAVE_RGB_COLOR("DarkSlateGray1", 151, 255, 255), +WAVE_RGB_COLOR("DarkSlateGray2", 141, 238, 238), +WAVE_RGB_COLOR("DarkSlateGray3", 121, 205, 205), +WAVE_RGB_COLOR("DarkSlateGray4", 82, 139, 139), +WAVE_RGB_COLOR("DarkSlateGrey", 47, 79, 79), +WAVE_RGB_COLOR("DarkTurquoise", 0, 206, 209), +WAVE_RGB_COLOR("DarkViolet", 148, 0, 211), +WAVE_RGB_COLOR("deep pink", 255, 20, 147), +WAVE_RGB_COLOR("deep sky blue", 0, 191, 255), +WAVE_RGB_COLOR("DeepPink", 255, 20, 147), +WAVE_RGB_COLOR("DeepPink1", 255, 20, 147), +WAVE_RGB_COLOR("DeepPink2", 238, 18, 137), +WAVE_RGB_COLOR("DeepPink3", 205, 16, 118), +WAVE_RGB_COLOR("DeepPink4", 139, 10, 80), +WAVE_RGB_COLOR("DeepSkyBlue", 0, 191, 255), +WAVE_RGB_COLOR("DeepSkyBlue1", 0, 191, 255), +WAVE_RGB_COLOR("DeepSkyBlue2", 0, 178, 238), +WAVE_RGB_COLOR("DeepSkyBlue3", 0, 154, 205), +WAVE_RGB_COLOR("DeepSkyBlue4", 0, 104, 139), +WAVE_RGB_COLOR("dim gray", 105, 105, 105), +WAVE_RGB_COLOR("dim grey", 105, 105, 105), +WAVE_RGB_COLOR("DimGray", 105, 105, 105), +WAVE_RGB_COLOR("DimGrey", 105, 105, 105), +WAVE_RGB_COLOR("dodger blue", 30, 144, 255), +WAVE_RGB_COLOR("DodgerBlue", 30, 144, 255), +WAVE_RGB_COLOR("DodgerBlue1", 30, 144, 255), +WAVE_RGB_COLOR("DodgerBlue2", 28, 134, 238), +WAVE_RGB_COLOR("DodgerBlue3", 24, 116, 205), +WAVE_RGB_COLOR("DodgerBlue4", 16, 78, 139), +WAVE_RGB_COLOR("firebrick", 178, 34, 34), +WAVE_RGB_COLOR("firebrick1", 255, 48, 48), +WAVE_RGB_COLOR("firebrick2", 238, 44, 44), +WAVE_RGB_COLOR("firebrick3", 205, 38, 38), +WAVE_RGB_COLOR("firebrick4", 139, 26, 26), +WAVE_RGB_COLOR("floral white", 255, 250, 240), +WAVE_RGB_COLOR("FloralWhite", 255, 250, 240), +WAVE_RGB_COLOR("forest green", 34, 139, 34), +WAVE_RGB_COLOR("ForestGreen", 34, 139, 34), +WAVE_RGB_COLOR("gainsboro", 220, 220, 220), +WAVE_RGB_COLOR("ghost white", 248, 248, 255), +WAVE_RGB_COLOR("GhostWhite", 248, 248, 255), +WAVE_RGB_COLOR("gold", 255, 215, 0), +WAVE_RGB_COLOR("gold1", 255, 215, 0), +WAVE_RGB_COLOR("gold2", 238, 201, 0), +WAVE_RGB_COLOR("gold3", 205, 173, 0), +WAVE_RGB_COLOR("gold4", 139, 117, 0), +WAVE_RGB_COLOR("goldenrod", 218, 165, 32), +WAVE_RGB_COLOR("goldenrod1", 255, 193, 37), +WAVE_RGB_COLOR("goldenrod2", 238, 180, 34), +WAVE_RGB_COLOR("goldenrod3", 205, 155, 29), +WAVE_RGB_COLOR("goldenrod4", 139, 105, 20), +WAVE_RGB_COLOR("gray", 190, 190, 190), +WAVE_RGB_COLOR("gray0", 0, 0, 0), +WAVE_RGB_COLOR("gray1", 3, 3, 3), +WAVE_RGB_COLOR("gray10", 26, 26, 26), +WAVE_RGB_COLOR("gray100", 255, 255, 255), +WAVE_RGB_COLOR("gray11", 28, 28, 28), +WAVE_RGB_COLOR("gray12", 31, 31, 31), +WAVE_RGB_COLOR("gray13", 33, 33, 33), +WAVE_RGB_COLOR("gray14", 36, 36, 36), +WAVE_RGB_COLOR("gray15", 38, 38, 38), +WAVE_RGB_COLOR("gray16", 41, 41, 41), +WAVE_RGB_COLOR("gray17", 43, 43, 43), +WAVE_RGB_COLOR("gray18", 46, 46, 46), +WAVE_RGB_COLOR("gray19", 48, 48, 48), +WAVE_RGB_COLOR("gray2", 5, 5, 5), +WAVE_RGB_COLOR("gray20", 51, 51, 51), +WAVE_RGB_COLOR("gray21", 54, 54, 54), +WAVE_RGB_COLOR("gray22", 56, 56, 56), +WAVE_RGB_COLOR("gray23", 59, 59, 59), +WAVE_RGB_COLOR("gray24", 61, 61, 61), +WAVE_RGB_COLOR("gray25", 64, 64, 64), +WAVE_RGB_COLOR("gray26", 66, 66, 66), +WAVE_RGB_COLOR("gray27", 69, 69, 69), +WAVE_RGB_COLOR("gray28", 71, 71, 71), +WAVE_RGB_COLOR("gray29", 74, 74, 74), +WAVE_RGB_COLOR("gray3", 8, 8, 8), +WAVE_RGB_COLOR("gray30", 77, 77, 77), +WAVE_RGB_COLOR("gray31", 79, 79, 79), +WAVE_RGB_COLOR("gray32", 82, 82, 82), +WAVE_RGB_COLOR("gray33", 84, 84, 84), +WAVE_RGB_COLOR("gray34", 87, 87, 87), +WAVE_RGB_COLOR("gray35", 89, 89, 89), +WAVE_RGB_COLOR("gray36", 92, 92, 92), +WAVE_RGB_COLOR("gray37", 94, 94, 94), +WAVE_RGB_COLOR("gray38", 97, 97, 97), +WAVE_RGB_COLOR("gray39", 99, 99, 99), +WAVE_RGB_COLOR("gray4", 10, 10, 10), +WAVE_RGB_COLOR("gray40", 102, 102, 102), +WAVE_RGB_COLOR("gray41", 105, 105, 105), +WAVE_RGB_COLOR("gray42", 107, 107, 107), +WAVE_RGB_COLOR("gray43", 110, 110, 110), +WAVE_RGB_COLOR("gray44", 112, 112, 112), +WAVE_RGB_COLOR("gray45", 115, 115, 115), +WAVE_RGB_COLOR("gray46", 117, 117, 117), +WAVE_RGB_COLOR("gray47", 120, 120, 120), +WAVE_RGB_COLOR("gray48", 122, 122, 122), +WAVE_RGB_COLOR("gray49", 125, 125, 125), +WAVE_RGB_COLOR("gray5", 13, 13, 13), +WAVE_RGB_COLOR("gray50", 127, 127, 127), +WAVE_RGB_COLOR("gray51", 130, 130, 130), +WAVE_RGB_COLOR("gray52", 133, 133, 133), +WAVE_RGB_COLOR("gray53", 135, 135, 135), +WAVE_RGB_COLOR("gray54", 138, 138, 138), +WAVE_RGB_COLOR("gray55", 140, 140, 140), +WAVE_RGB_COLOR("gray56", 143, 143, 143), +WAVE_RGB_COLOR("gray57", 145, 145, 145), +WAVE_RGB_COLOR("gray58", 148, 148, 148), +WAVE_RGB_COLOR("gray59", 150, 150, 150), +WAVE_RGB_COLOR("gray6", 15, 15, 15), +WAVE_RGB_COLOR("gray60", 153, 153, 153), +WAVE_RGB_COLOR("gray61", 156, 156, 156), +WAVE_RGB_COLOR("gray62", 158, 158, 158), +WAVE_RGB_COLOR("gray63", 161, 161, 161), +WAVE_RGB_COLOR("gray64", 163, 163, 163), +WAVE_RGB_COLOR("gray65", 166, 166, 166), +WAVE_RGB_COLOR("gray66", 168, 168, 168), +WAVE_RGB_COLOR("gray67", 171, 171, 171), +WAVE_RGB_COLOR("gray68", 173, 173, 173), +WAVE_RGB_COLOR("gray69", 176, 176, 176), +WAVE_RGB_COLOR("gray7", 18, 18, 18), +WAVE_RGB_COLOR("gray70", 179, 179, 179), +WAVE_RGB_COLOR("gray71", 181, 181, 181), +WAVE_RGB_COLOR("gray72", 184, 184, 184), +WAVE_RGB_COLOR("gray73", 186, 186, 186), +WAVE_RGB_COLOR("gray74", 189, 189, 189), +WAVE_RGB_COLOR("gray75", 191, 191, 191), +WAVE_RGB_COLOR("gray76", 194, 194, 194), +WAVE_RGB_COLOR("gray77", 196, 196, 196), +WAVE_RGB_COLOR("gray78", 199, 199, 199), +WAVE_RGB_COLOR("gray79", 201, 201, 201), +WAVE_RGB_COLOR("gray8", 20, 20, 20), +WAVE_RGB_COLOR("gray80", 204, 204, 204), +WAVE_RGB_COLOR("gray81", 207, 207, 207), +WAVE_RGB_COLOR("gray82", 209, 209, 209), +WAVE_RGB_COLOR("gray83", 212, 212, 212), +WAVE_RGB_COLOR("gray84", 214, 214, 214), +WAVE_RGB_COLOR("gray85", 217, 217, 217), +WAVE_RGB_COLOR("gray86", 219, 219, 219), +WAVE_RGB_COLOR("gray87", 222, 222, 222), +WAVE_RGB_COLOR("gray88", 224, 224, 224), +WAVE_RGB_COLOR("gray89", 227, 227, 227), +WAVE_RGB_COLOR("gray9", 23, 23, 23), +WAVE_RGB_COLOR("gray90", 229, 229, 229), +WAVE_RGB_COLOR("gray91", 232, 232, 232), +WAVE_RGB_COLOR("gray92", 235, 235, 235), +WAVE_RGB_COLOR("gray93", 237, 237, 237), +WAVE_RGB_COLOR("gray94", 240, 240, 240), +WAVE_RGB_COLOR("gray95", 242, 242, 242), +WAVE_RGB_COLOR("gray96", 245, 245, 245), +WAVE_RGB_COLOR("gray97", 247, 247, 247), +WAVE_RGB_COLOR("gray98", 250, 250, 250), +WAVE_RGB_COLOR("gray99", 252, 252, 252), +WAVE_RGB_COLOR("green", 0, 255, 0), +WAVE_RGB_COLOR("green yellow", 173, 255, 47), +WAVE_RGB_COLOR("green1", 0, 255, 0), +WAVE_RGB_COLOR("green2", 0, 238, 0), +WAVE_RGB_COLOR("green3", 0, 205, 0), +WAVE_RGB_COLOR("green4", 0, 139, 0), +WAVE_RGB_COLOR("GreenYellow", 173, 255, 47), +WAVE_RGB_COLOR("grey", 190, 190, 190), +WAVE_RGB_COLOR("grey0", 0, 0, 0), +WAVE_RGB_COLOR("grey1", 3, 3, 3), +WAVE_RGB_COLOR("grey10", 26, 26, 26), +WAVE_RGB_COLOR("grey100", 255, 255, 255), +WAVE_RGB_COLOR("grey11", 28, 28, 28), +WAVE_RGB_COLOR("grey12", 31, 31, 31), +WAVE_RGB_COLOR("grey13", 33, 33, 33), +WAVE_RGB_COLOR("grey14", 36, 36, 36), +WAVE_RGB_COLOR("grey15", 38, 38, 38), +WAVE_RGB_COLOR("grey16", 41, 41, 41), +WAVE_RGB_COLOR("grey17", 43, 43, 43), +WAVE_RGB_COLOR("grey18", 46, 46, 46), +WAVE_RGB_COLOR("grey19", 48, 48, 48), +WAVE_RGB_COLOR("grey2", 5, 5, 5), +WAVE_RGB_COLOR("grey20", 51, 51, 51), +WAVE_RGB_COLOR("grey21", 54, 54, 54), +WAVE_RGB_COLOR("grey22", 56, 56, 56), +WAVE_RGB_COLOR("grey23", 59, 59, 59), +WAVE_RGB_COLOR("grey24", 61, 61, 61), +WAVE_RGB_COLOR("grey25", 64, 64, 64), +WAVE_RGB_COLOR("grey26", 66, 66, 66), +WAVE_RGB_COLOR("grey27", 69, 69, 69), +WAVE_RGB_COLOR("grey28", 71, 71, 71), +WAVE_RGB_COLOR("grey29", 74, 74, 74), +WAVE_RGB_COLOR("grey3", 8, 8, 8), +WAVE_RGB_COLOR("grey30", 77, 77, 77), +WAVE_RGB_COLOR("grey31", 79, 79, 79), +WAVE_RGB_COLOR("grey32", 82, 82, 82), +WAVE_RGB_COLOR("grey33", 84, 84, 84), +WAVE_RGB_COLOR("grey34", 87, 87, 87), +WAVE_RGB_COLOR("grey35", 89, 89, 89), +WAVE_RGB_COLOR("grey36", 92, 92, 92), +WAVE_RGB_COLOR("grey37", 94, 94, 94), +WAVE_RGB_COLOR("grey38", 97, 97, 97), +WAVE_RGB_COLOR("grey39", 99, 99, 99), +WAVE_RGB_COLOR("grey4", 10, 10, 10), +WAVE_RGB_COLOR("grey40", 102, 102, 102), +WAVE_RGB_COLOR("grey41", 105, 105, 105), +WAVE_RGB_COLOR("grey42", 107, 107, 107), +WAVE_RGB_COLOR("grey43", 110, 110, 110), +WAVE_RGB_COLOR("grey44", 112, 112, 112), +WAVE_RGB_COLOR("grey45", 115, 115, 115), +WAVE_RGB_COLOR("grey46", 117, 117, 117), +WAVE_RGB_COLOR("grey47", 120, 120, 120), +WAVE_RGB_COLOR("grey48", 122, 122, 122), +WAVE_RGB_COLOR("grey49", 125, 125, 125), +WAVE_RGB_COLOR("grey5", 13, 13, 13), +WAVE_RGB_COLOR("grey50", 127, 127, 127), +WAVE_RGB_COLOR("grey51", 130, 130, 130), +WAVE_RGB_COLOR("grey52", 133, 133, 133), +WAVE_RGB_COLOR("grey53", 135, 135, 135), +WAVE_RGB_COLOR("grey54", 138, 138, 138), +WAVE_RGB_COLOR("grey55", 140, 140, 140), +WAVE_RGB_COLOR("grey56", 143, 143, 143), +WAVE_RGB_COLOR("grey57", 145, 145, 145), +WAVE_RGB_COLOR("grey58", 148, 148, 148), +WAVE_RGB_COLOR("grey59", 150, 150, 150), +WAVE_RGB_COLOR("grey6", 15, 15, 15), +WAVE_RGB_COLOR("grey60", 153, 153, 153), +WAVE_RGB_COLOR("grey61", 156, 156, 156), +WAVE_RGB_COLOR("grey62", 158, 158, 158), +WAVE_RGB_COLOR("grey63", 161, 161, 161), +WAVE_RGB_COLOR("grey64", 163, 163, 163), +WAVE_RGB_COLOR("grey65", 166, 166, 166), +WAVE_RGB_COLOR("grey66", 168, 168, 168), +WAVE_RGB_COLOR("grey67", 171, 171, 171), +WAVE_RGB_COLOR("grey68", 173, 173, 173), +WAVE_RGB_COLOR("grey69", 176, 176, 176), +WAVE_RGB_COLOR("grey7", 18, 18, 18), +WAVE_RGB_COLOR("grey70", 179, 179, 179), +WAVE_RGB_COLOR("grey71", 181, 181, 181), +WAVE_RGB_COLOR("grey72", 184, 184, 184), +WAVE_RGB_COLOR("grey73", 186, 186, 186), +WAVE_RGB_COLOR("grey74", 189, 189, 189), +WAVE_RGB_COLOR("grey75", 191, 191, 191), +WAVE_RGB_COLOR("grey76", 194, 194, 194), +WAVE_RGB_COLOR("grey77", 196, 196, 196), +WAVE_RGB_COLOR("grey78", 199, 199, 199), +WAVE_RGB_COLOR("grey79", 201, 201, 201), +WAVE_RGB_COLOR("grey8", 20, 20, 20), +WAVE_RGB_COLOR("grey80", 204, 204, 204), +WAVE_RGB_COLOR("grey81", 207, 207, 207), +WAVE_RGB_COLOR("grey82", 209, 209, 209), +WAVE_RGB_COLOR("grey83", 212, 212, 212), +WAVE_RGB_COLOR("grey84", 214, 214, 214), +WAVE_RGB_COLOR("grey85", 217, 217, 217), +WAVE_RGB_COLOR("grey86", 219, 219, 219), +WAVE_RGB_COLOR("grey87", 222, 222, 222), +WAVE_RGB_COLOR("grey88", 224, 224, 224), +WAVE_RGB_COLOR("grey89", 227, 227, 227), +WAVE_RGB_COLOR("grey9", 23, 23, 23), +WAVE_RGB_COLOR("grey90", 229, 229, 229), +WAVE_RGB_COLOR("grey91", 232, 232, 232), +WAVE_RGB_COLOR("grey92", 235, 235, 235), +WAVE_RGB_COLOR("grey93", 237, 237, 237), +WAVE_RGB_COLOR("grey94", 240, 240, 240), +WAVE_RGB_COLOR("grey95", 242, 242, 242), +WAVE_RGB_COLOR("grey96", 245, 245, 245), +WAVE_RGB_COLOR("grey97", 247, 247, 247), +WAVE_RGB_COLOR("grey98", 250, 250, 250), +WAVE_RGB_COLOR("grey99", 252, 252, 252), +WAVE_RGB_COLOR("honeydew", 240, 255, 240), +WAVE_RGB_COLOR("honeydew1", 240, 255, 240), +WAVE_RGB_COLOR("honeydew2", 224, 238, 224), +WAVE_RGB_COLOR("honeydew3", 193, 205, 193), +WAVE_RGB_COLOR("honeydew4", 131, 139, 131), +WAVE_RGB_COLOR("hot pink", 255, 105, 180), +WAVE_RGB_COLOR("HotPink", 255, 105, 180), +WAVE_RGB_COLOR("HotPink1", 255, 110, 180), +WAVE_RGB_COLOR("HotPink2", 238, 106, 167), +WAVE_RGB_COLOR("HotPink3", 205, 96, 144), +WAVE_RGB_COLOR("HotPink4", 139, 58, 98), +WAVE_RGB_COLOR("indian red", 205, 92, 92), +WAVE_RGB_COLOR("IndianRed", 205, 92, 92), +WAVE_RGB_COLOR("IndianRed1", 255, 106, 106), +WAVE_RGB_COLOR("IndianRed2", 238, 99, 99), +WAVE_RGB_COLOR("IndianRed3", 205, 85, 85), +WAVE_RGB_COLOR("IndianRed4", 139, 58, 58), +WAVE_RGB_COLOR("ivory", 255, 255, 240), +WAVE_RGB_COLOR("ivory1", 255, 255, 240), +WAVE_RGB_COLOR("ivory2", 238, 238, 224), +WAVE_RGB_COLOR("ivory3", 205, 205, 193), +WAVE_RGB_COLOR("ivory4", 139, 139, 131), +WAVE_RGB_COLOR("khaki", 240, 230, 140), +WAVE_RGB_COLOR("khaki1", 255, 246, 143), +WAVE_RGB_COLOR("khaki2", 238, 230, 133), +WAVE_RGB_COLOR("khaki3", 205, 198, 115), +WAVE_RGB_COLOR("khaki4", 139, 134, 78), +WAVE_RGB_COLOR("lavender", 230, 230, 250), +WAVE_RGB_COLOR("lavender blush", 255, 240, 245), +WAVE_RGB_COLOR("LavenderBlush", 255, 240, 245), +WAVE_RGB_COLOR("LavenderBlush1", 255, 240, 245), +WAVE_RGB_COLOR("LavenderBlush2", 238, 224, 229), +WAVE_RGB_COLOR("LavenderBlush3", 205, 193, 197), +WAVE_RGB_COLOR("LavenderBlush4", 139, 131, 134), +WAVE_RGB_COLOR("lawn green", 124, 252, 0), +WAVE_RGB_COLOR("LawnGreen", 124, 252, 0), +WAVE_RGB_COLOR("lemon chiffon", 255, 250, 205), +WAVE_RGB_COLOR("LemonChiffon", 255, 250, 205), +WAVE_RGB_COLOR("LemonChiffon1", 255, 250, 205), +WAVE_RGB_COLOR("LemonChiffon2", 238, 233, 191), +WAVE_RGB_COLOR("LemonChiffon3", 205, 201, 165), +WAVE_RGB_COLOR("LemonChiffon4", 139, 137, 112), +WAVE_RGB_COLOR("light blue", 173, 216, 230), +WAVE_RGB_COLOR("light coral", 240, 128, 128), +WAVE_RGB_COLOR("light cyan", 224, 255, 255), +WAVE_RGB_COLOR("light goldenrod", 238, 221, 130), +WAVE_RGB_COLOR("light goldenrod yellow", 250, 250, 210), +WAVE_RGB_COLOR("light gray", 211, 211, 211), +WAVE_RGB_COLOR("light green", 144, 238, 144), +WAVE_RGB_COLOR("light grey", 211, 211, 211), +WAVE_RGB_COLOR("light pink", 255, 182, 193), +WAVE_RGB_COLOR("light salmon", 255, 160, 122), +WAVE_RGB_COLOR("light sea green", 32, 178, 170), +WAVE_RGB_COLOR("light sky blue", 135, 206, 250), +WAVE_RGB_COLOR("light slate blue", 132, 112, 255), +WAVE_RGB_COLOR("light slate gray", 119, 136, 153), +WAVE_RGB_COLOR("light slate grey", 119, 136, 153), +WAVE_RGB_COLOR("light steel blue", 176, 196, 222), +WAVE_RGB_COLOR("light yellow", 255, 255, 224), +WAVE_RGB_COLOR("LightBlue", 173, 216, 230), +WAVE_RGB_COLOR("LightBlue1", 191, 239, 255), +WAVE_RGB_COLOR("LightBlue2", 178, 223, 238), +WAVE_RGB_COLOR("LightBlue3", 154, 192, 205), +WAVE_RGB_COLOR("LightBlue4", 104, 131, 139), +WAVE_RGB_COLOR("LightCoral", 240, 128, 128), +WAVE_RGB_COLOR("LightCyan", 224, 255, 255), +WAVE_RGB_COLOR("LightCyan1", 224, 255, 255), +WAVE_RGB_COLOR("LightCyan2", 209, 238, 238), +WAVE_RGB_COLOR("LightCyan3", 180, 205, 205), +WAVE_RGB_COLOR("LightCyan4", 122, 139, 139), +WAVE_RGB_COLOR("LightGoldenrod", 238, 221, 130), +WAVE_RGB_COLOR("LightGoldenrod1", 255, 236, 139), +WAVE_RGB_COLOR("LightGoldenrod2", 238, 220, 130), +WAVE_RGB_COLOR("LightGoldenrod3", 205, 190, 112), +WAVE_RGB_COLOR("LightGoldenrod4", 139, 129, 76), +WAVE_RGB_COLOR("LightGoldenrodYellow", 250, 250, 210), +WAVE_RGB_COLOR("LightGray", 211, 211, 211), +WAVE_RGB_COLOR("LightGreen", 144, 238, 144), +WAVE_RGB_COLOR("LightGrey", 211, 211, 211), +WAVE_RGB_COLOR("LightPink", 255, 182, 193), +WAVE_RGB_COLOR("LightPink1", 255, 174, 185), +WAVE_RGB_COLOR("LightPink2", 238, 162, 173), +WAVE_RGB_COLOR("LightPink3", 205, 140, 149), +WAVE_RGB_COLOR("LightPink4", 139, 95, 101), +WAVE_RGB_COLOR("LightSalmon", 255, 160, 122), +WAVE_RGB_COLOR("LightSalmon1", 255, 160, 122), +WAVE_RGB_COLOR("LightSalmon2", 238, 149, 114), +WAVE_RGB_COLOR("LightSalmon3", 205, 129, 98), +WAVE_RGB_COLOR("LightSalmon4", 139, 87, 66), +WAVE_RGB_COLOR("LightSeaGreen", 32, 178, 170), +WAVE_RGB_COLOR("LightSkyBlue", 135, 206, 250), +WAVE_RGB_COLOR("LightSkyBlue1", 176, 226, 255), +WAVE_RGB_COLOR("LightSkyBlue2", 164, 211, 238), +WAVE_RGB_COLOR("LightSkyBlue3", 141, 182, 205), +WAVE_RGB_COLOR("LightSkyBlue4", 96, 123, 139), +WAVE_RGB_COLOR("LightSlateBlue", 132, 112, 255), +WAVE_RGB_COLOR("LightSlateGray", 119, 136, 153), +WAVE_RGB_COLOR("LightSlateGrey", 119, 136, 153), +WAVE_RGB_COLOR("LightSteelBlue", 176, 196, 222), +WAVE_RGB_COLOR("LightSteelBlue1", 202, 225, 255), +WAVE_RGB_COLOR("LightSteelBlue2", 188, 210, 238), +WAVE_RGB_COLOR("LightSteelBlue3", 162, 181, 205), +WAVE_RGB_COLOR("LightSteelBlue4", 110, 123, 139), +WAVE_RGB_COLOR("LightYellow", 255, 255, 224), +WAVE_RGB_COLOR("LightYellow1", 255, 255, 224), +WAVE_RGB_COLOR("LightYellow2", 238, 238, 209), +WAVE_RGB_COLOR("LightYellow3", 205, 205, 180), +WAVE_RGB_COLOR("LightYellow4", 139, 139, 122), +WAVE_RGB_COLOR("lime green", 50, 205, 50), +WAVE_RGB_COLOR("LimeGreen", 50, 205, 50), +WAVE_RGB_COLOR("linen", 250, 240, 230), +WAVE_RGB_COLOR("magenta", 255, 0, 255), +WAVE_RGB_COLOR("magenta1", 255, 0, 255), +WAVE_RGB_COLOR("magenta2", 238, 0, 238), +WAVE_RGB_COLOR("magenta3", 205, 0, 205), +WAVE_RGB_COLOR("magenta4", 139, 0, 139), +WAVE_RGB_COLOR("maroon", 176, 48, 96), +WAVE_RGB_COLOR("maroon1", 255, 52, 179), +WAVE_RGB_COLOR("maroon2", 238, 48, 167), +WAVE_RGB_COLOR("maroon3", 205, 41, 144), +WAVE_RGB_COLOR("maroon4", 139, 28, 98), +WAVE_RGB_COLOR("medium aquamarine", 102, 205, 170), +WAVE_RGB_COLOR("medium blue", 0, 0, 205), +WAVE_RGB_COLOR("medium orchid", 186, 85, 211), +WAVE_RGB_COLOR("medium purple", 147, 112, 219), +WAVE_RGB_COLOR("medium sea green", 60, 179, 113), +WAVE_RGB_COLOR("medium slate blue", 123, 104, 238), +WAVE_RGB_COLOR("medium spring green", 0, 250, 154), +WAVE_RGB_COLOR("medium turquoise", 72, 209, 204), +WAVE_RGB_COLOR("medium violet red", 199, 21, 133), +WAVE_RGB_COLOR("MediumAquamarine", 102, 205, 170), +WAVE_RGB_COLOR("MediumBlue", 0, 0, 205), +WAVE_RGB_COLOR("MediumOrchid", 186, 85, 211), +WAVE_RGB_COLOR("MediumOrchid1", 224, 102, 255), +WAVE_RGB_COLOR("MediumOrchid2", 209, 95, 238), +WAVE_RGB_COLOR("MediumOrchid3", 180, 82, 205), +WAVE_RGB_COLOR("MediumOrchid4", 122, 55, 139), +WAVE_RGB_COLOR("MediumPurple", 147, 112, 219), +WAVE_RGB_COLOR("MediumPurple1", 171, 130, 255), +WAVE_RGB_COLOR("MediumPurple2", 159, 121, 238), +WAVE_RGB_COLOR("MediumPurple3", 137, 104, 205), +WAVE_RGB_COLOR("MediumPurple4", 93, 71, 139), +WAVE_RGB_COLOR("MediumSeaGreen", 60, 179, 113), +WAVE_RGB_COLOR("MediumSlateBlue", 123, 104, 238), +WAVE_RGB_COLOR("MediumSpringGreen", 0, 250, 154), +WAVE_RGB_COLOR("MediumTurquoise", 72, 209, 204), +WAVE_RGB_COLOR("MediumVioletRed", 199, 21, 133), +WAVE_RGB_COLOR("midnight blue", 25, 25, 112), +WAVE_RGB_COLOR("MidnightBlue", 25, 25, 112), +WAVE_RGB_COLOR("mint cream", 245, 255, 250), +WAVE_RGB_COLOR("MintCream", 245, 255, 250), +WAVE_RGB_COLOR("misty rose", 255, 228, 225), +WAVE_RGB_COLOR("MistyRose", 255, 228, 225), +WAVE_RGB_COLOR("MistyRose1", 255, 228, 225), +WAVE_RGB_COLOR("MistyRose2", 238, 213, 210), +WAVE_RGB_COLOR("MistyRose3", 205, 183, 181), +WAVE_RGB_COLOR("MistyRose4", 139, 125, 123), +WAVE_RGB_COLOR("moccasin", 255, 228, 181), +WAVE_RGB_COLOR("navajo white", 255, 222, 173), +WAVE_RGB_COLOR("NavajoWhite", 255, 222, 173), +WAVE_RGB_COLOR("NavajoWhite1", 255, 222, 173), +WAVE_RGB_COLOR("NavajoWhite2", 238, 207, 161), +WAVE_RGB_COLOR("NavajoWhite3", 205, 179, 139), +WAVE_RGB_COLOR("NavajoWhite4", 139, 121, 94), +WAVE_RGB_COLOR("navy", 0, 0, 128), +WAVE_RGB_COLOR("navy blue", 0, 0, 128), +WAVE_RGB_COLOR("NavyBlue", 0, 0, 128), +WAVE_RGB_COLOR("old lace", 253, 245, 230), +WAVE_RGB_COLOR("OldLace", 253, 245, 230), +WAVE_RGB_COLOR("olive drab", 107, 142, 35), +WAVE_RGB_COLOR("OliveDrab", 107, 142, 35), +WAVE_RGB_COLOR("OliveDrab1", 192, 255, 62), +WAVE_RGB_COLOR("OliveDrab2", 179, 238, 58), +WAVE_RGB_COLOR("OliveDrab3", 154, 205, 50), +WAVE_RGB_COLOR("OliveDrab4", 105, 139, 34), +WAVE_RGB_COLOR("orange", 255, 165, 0), +WAVE_RGB_COLOR("orange red", 255, 69, 0), +WAVE_RGB_COLOR("orange1", 255, 165, 0), +WAVE_RGB_COLOR("orange2", 238, 154, 0), +WAVE_RGB_COLOR("orange3", 205, 133, 0), +WAVE_RGB_COLOR("orange4", 139, 90, 0), +WAVE_RGB_COLOR("OrangeRed", 255, 69, 0), +WAVE_RGB_COLOR("OrangeRed1", 255, 69, 0), +WAVE_RGB_COLOR("OrangeRed2", 238, 64, 0), +WAVE_RGB_COLOR("OrangeRed3", 205, 55, 0), +WAVE_RGB_COLOR("OrangeRed4", 139, 37, 0), +WAVE_RGB_COLOR("orchid", 218, 112, 214), +WAVE_RGB_COLOR("orchid1", 255, 131, 250), +WAVE_RGB_COLOR("orchid2", 238, 122, 233), +WAVE_RGB_COLOR("orchid3", 205, 105, 201), +WAVE_RGB_COLOR("orchid4", 139, 71, 137), +WAVE_RGB_COLOR("pale goldenrod", 238, 232, 170), +WAVE_RGB_COLOR("pale green", 152, 251, 152), +WAVE_RGB_COLOR("pale turquoise", 175, 238, 238), +WAVE_RGB_COLOR("pale violet red", 219, 112, 147), +WAVE_RGB_COLOR("PaleGoldenrod", 238, 232, 170), +WAVE_RGB_COLOR("PaleGreen", 152, 251, 152), +WAVE_RGB_COLOR("PaleGreen1", 154, 255, 154), +WAVE_RGB_COLOR("PaleGreen2", 144, 238, 144), +WAVE_RGB_COLOR("PaleGreen3", 124, 205, 124), +WAVE_RGB_COLOR("PaleGreen4", 84, 139, 84), +WAVE_RGB_COLOR("PaleTurquoise", 175, 238, 238), +WAVE_RGB_COLOR("PaleTurquoise1", 187, 255, 255), +WAVE_RGB_COLOR("PaleTurquoise2", 174, 238, 238), +WAVE_RGB_COLOR("PaleTurquoise3", 150, 205, 205), +WAVE_RGB_COLOR("PaleTurquoise4", 102, 139, 139), +WAVE_RGB_COLOR("PaleVioletRed", 219, 112, 147), +WAVE_RGB_COLOR("PaleVioletRed1", 255, 130, 171), +WAVE_RGB_COLOR("PaleVioletRed2", 238, 121, 159), +WAVE_RGB_COLOR("PaleVioletRed3", 205, 104, 137), +WAVE_RGB_COLOR("PaleVioletRed4", 139, 71, 93), +WAVE_RGB_COLOR("papaya whip", 255, 239, 213), +WAVE_RGB_COLOR("PapayaWhip", 255, 239, 213), +WAVE_RGB_COLOR("peach puff", 255, 218, 185), +WAVE_RGB_COLOR("PeachPuff", 255, 218, 185), +WAVE_RGB_COLOR("PeachPuff1", 255, 218, 185), +WAVE_RGB_COLOR("PeachPuff2", 238, 203, 173), +WAVE_RGB_COLOR("PeachPuff3", 205, 175, 149), +WAVE_RGB_COLOR("PeachPuff4", 139, 119, 101), +WAVE_RGB_COLOR("peru", 205, 133, 63), +WAVE_RGB_COLOR("pink", 255, 192, 203), +WAVE_RGB_COLOR("pink1", 255, 181, 197), +WAVE_RGB_COLOR("pink2", 238, 169, 184), +WAVE_RGB_COLOR("pink3", 205, 145, 158), +WAVE_RGB_COLOR("pink4", 139, 99, 108), +WAVE_RGB_COLOR("plum", 221, 160, 221), +WAVE_RGB_COLOR("plum1", 255, 187, 255), +WAVE_RGB_COLOR("plum2", 238, 174, 238), +WAVE_RGB_COLOR("plum3", 205, 150, 205), +WAVE_RGB_COLOR("plum4", 139, 102, 139), +WAVE_RGB_COLOR("powder blue", 176, 224, 230), +WAVE_RGB_COLOR("PowderBlue", 176, 224, 230), +WAVE_RGB_COLOR("purple", 160, 32, 240), +WAVE_RGB_COLOR("purple1", 155, 48, 255), +WAVE_RGB_COLOR("purple2", 145, 44, 238), +WAVE_RGB_COLOR("purple3", 125, 38, 205), +WAVE_RGB_COLOR("purple4", 85, 26, 139), +WAVE_RGB_COLOR("red", 255, 0, 0), +WAVE_RGB_COLOR("red1", 255, 0, 0), +WAVE_RGB_COLOR("red2", 238, 0, 0), +WAVE_RGB_COLOR("red3", 205, 0, 0), +WAVE_RGB_COLOR("red4", 139, 0, 0), +WAVE_RGB_COLOR("rosy brown", 188, 143, 143), +WAVE_RGB_COLOR("RosyBrown", 188, 143, 143), +WAVE_RGB_COLOR("RosyBrown1", 255, 193, 193), +WAVE_RGB_COLOR("RosyBrown2", 238, 180, 180), +WAVE_RGB_COLOR("RosyBrown3", 205, 155, 155), +WAVE_RGB_COLOR("RosyBrown4", 139, 105, 105), +WAVE_RGB_COLOR("royal blue", 65, 105, 225), +WAVE_RGB_COLOR("RoyalBlue", 65, 105, 225), +WAVE_RGB_COLOR("RoyalBlue1", 72, 118, 255), +WAVE_RGB_COLOR("RoyalBlue2", 67, 110, 238), +WAVE_RGB_COLOR("RoyalBlue3", 58, 95, 205), +WAVE_RGB_COLOR("RoyalBlue4", 39, 64, 139), +WAVE_RGB_COLOR("saddle brown", 139, 69, 19), +WAVE_RGB_COLOR("SaddleBrown", 139, 69, 19), +WAVE_RGB_COLOR("salmon", 250, 128, 114), +WAVE_RGB_COLOR("salmon1", 255, 140, 105), +WAVE_RGB_COLOR("salmon2", 238, 130, 98), +WAVE_RGB_COLOR("salmon3", 205, 112, 84), +WAVE_RGB_COLOR("salmon4", 139, 76, 57), +WAVE_RGB_COLOR("sandy brown", 244, 164, 96), +WAVE_RGB_COLOR("SandyBrown", 244, 164, 96), +WAVE_RGB_COLOR("sea green", 46, 139, 87), +WAVE_RGB_COLOR("SeaGreen", 46, 139, 87), +WAVE_RGB_COLOR("SeaGreen1", 84, 255, 159), +WAVE_RGB_COLOR("SeaGreen2", 78, 238, 148), +WAVE_RGB_COLOR("SeaGreen3", 67, 205, 128), +WAVE_RGB_COLOR("SeaGreen4", 46, 139, 87), +WAVE_RGB_COLOR("seashell", 255, 245, 238), +WAVE_RGB_COLOR("seashell1", 255, 245, 238), +WAVE_RGB_COLOR("seashell2", 238, 229, 222), +WAVE_RGB_COLOR("seashell3", 205, 197, 191), +WAVE_RGB_COLOR("seashell4", 139, 134, 130), +WAVE_RGB_COLOR("sienna", 160, 82, 45), +WAVE_RGB_COLOR("sienna1", 255, 130, 71), +WAVE_RGB_COLOR("sienna2", 238, 121, 66), +WAVE_RGB_COLOR("sienna3", 205, 104, 57), +WAVE_RGB_COLOR("sienna4", 139, 71, 38), +WAVE_RGB_COLOR("sky blue", 135, 206, 235), +WAVE_RGB_COLOR("SkyBlue", 135, 206, 235), +WAVE_RGB_COLOR("SkyBlue1", 135, 206, 255), +WAVE_RGB_COLOR("SkyBlue2", 126, 192, 238), +WAVE_RGB_COLOR("SkyBlue3", 108, 166, 205), +WAVE_RGB_COLOR("SkyBlue4", 74, 112, 139), +WAVE_RGB_COLOR("slate blue", 106, 90, 205), +WAVE_RGB_COLOR("slate gray", 112, 128, 144), +WAVE_RGB_COLOR("slate grey", 112, 128, 144), +WAVE_RGB_COLOR("SlateBlue", 106, 90, 205), +WAVE_RGB_COLOR("SlateBlue1", 131, 111, 255), +WAVE_RGB_COLOR("SlateBlue2", 122, 103, 238), +WAVE_RGB_COLOR("SlateBlue3", 105, 89, 205), +WAVE_RGB_COLOR("SlateBlue4", 71, 60, 139), +WAVE_RGB_COLOR("SlateGray", 112, 128, 144), +WAVE_RGB_COLOR("SlateGray1", 198, 226, 255), +WAVE_RGB_COLOR("SlateGray2", 185, 211, 238), +WAVE_RGB_COLOR("SlateGray3", 159, 182, 205), +WAVE_RGB_COLOR("SlateGray4", 108, 123, 139), +WAVE_RGB_COLOR("SlateGrey", 112, 128, 144), +WAVE_RGB_COLOR("snow", 255, 250, 250), +WAVE_RGB_COLOR("snow1", 255, 250, 250), +WAVE_RGB_COLOR("snow2", 238, 233, 233), +WAVE_RGB_COLOR("snow3", 205, 201, 201), +WAVE_RGB_COLOR("snow4", 139, 137, 137), +WAVE_RGB_COLOR("spring green", 0, 255, 127), +WAVE_RGB_COLOR("SpringGreen", 0, 255, 127), +WAVE_RGB_COLOR("SpringGreen1", 0, 255, 127), +WAVE_RGB_COLOR("SpringGreen2", 0, 238, 118), +WAVE_RGB_COLOR("SpringGreen3", 0, 205, 102), +WAVE_RGB_COLOR("SpringGreen4", 0, 139, 69), +WAVE_RGB_COLOR("steel blue", 70, 130, 180), +WAVE_RGB_COLOR("SteelBlue", 70, 130, 180), +WAVE_RGB_COLOR("SteelBlue1", 99, 184, 255), +WAVE_RGB_COLOR("SteelBlue2", 92, 172, 238), +WAVE_RGB_COLOR("SteelBlue3", 79, 148, 205), +WAVE_RGB_COLOR("SteelBlue4", 54, 100, 139), +WAVE_RGB_COLOR("tan", 210, 180, 140), +WAVE_RGB_COLOR("tan1", 255, 165, 79), +WAVE_RGB_COLOR("tan2", 238, 154, 73), +WAVE_RGB_COLOR("tan3", 205, 133, 63), +WAVE_RGB_COLOR("tan4", 139, 90, 43), +WAVE_RGB_COLOR("thistle", 216, 191, 216), +WAVE_RGB_COLOR("thistle1", 255, 225, 255), +WAVE_RGB_COLOR("thistle2", 238, 210, 238), +WAVE_RGB_COLOR("thistle3", 205, 181, 205), +WAVE_RGB_COLOR("thistle4", 139, 123, 139), +WAVE_RGB_COLOR("tomato", 255, 99, 71), +WAVE_RGB_COLOR("tomato1", 255, 99, 71), +WAVE_RGB_COLOR("tomato2", 238, 92, 66), +WAVE_RGB_COLOR("tomato3", 205, 79, 57), +WAVE_RGB_COLOR("tomato4", 139, 54, 38), +WAVE_RGB_COLOR("turquoise", 64, 224, 208), +WAVE_RGB_COLOR("turquoise1", 0, 245, 255), +WAVE_RGB_COLOR("turquoise2", 0, 229, 238), +WAVE_RGB_COLOR("turquoise3", 0, 197, 205), +WAVE_RGB_COLOR("turquoise4", 0, 134, 139), +WAVE_RGB_COLOR("violet", 238, 130, 238), +WAVE_RGB_COLOR("violet red", 208, 32, 144), +WAVE_RGB_COLOR("VioletRed", 208, 32, 144), +WAVE_RGB_COLOR("VioletRed1", 255, 62, 150), +WAVE_RGB_COLOR("VioletRed2", 238, 58, 140), +WAVE_RGB_COLOR("VioletRed3", 205, 50, 120), +WAVE_RGB_COLOR("VioletRed4", 139, 34, 82), +WAVE_RGB_COLOR("wheat", 245, 222, 179), +WAVE_RGB_COLOR("wheat1", 255, 231, 186), +WAVE_RGB_COLOR("wheat2", 238, 216, 174), +WAVE_RGB_COLOR("wheat3", 205, 186, 150), +WAVE_RGB_COLOR("wheat4", 139, 126, 102), +WAVE_RGB_COLOR("white", 255, 255, 255), +WAVE_RGB_COLOR("white smoke", 245, 245, 245), +WAVE_RGB_COLOR("WhiteSmoke", 245, 245, 245), +WAVE_RGB_COLOR("yellow", 255, 255, 0), +WAVE_RGB_COLOR("yellow green", 154, 205, 50), +WAVE_RGB_COLOR("yellow1", 255, 255, 0), +WAVE_RGB_COLOR("yellow2", 238, 238, 0), +WAVE_RGB_COLOR("yellow3", 205, 205, 0), +WAVE_RGB_COLOR("yellow4", 139, 139, 0), +WAVE_RGB_COLOR("YellowGreen", 154, 205, 50), +}; +''' \ No newline at end of file diff --git a/dev/sim/gtkwave/gtkf-valid.py b/dev/sim/gtkwave/gtkf-valid.py new file mode 100755 index 0000000..97356c2 --- /dev/null +++ b/dev/sim/gtkwave/gtkf-valid.py @@ -0,0 +1,56 @@ +#!/usr/bin/python3 +# gtkwave process filter +# +# display valid+anything else (inc. just valid) +# +# format=binary so justification and data length don't matter +# valid is on left + +import sys + +colorI = '' +colorV = '?DarkBlue?' +colorX = '?red?' + +fi = sys.stdin +fo = sys.stdout +fe = sys.stderr + +debug = False + +def dbg(m): + if debug: + fe.write(m + '\n') + fe.flush() + +def main(): + + while True: + + line = fi.readline() + if not line: + return 0 + + try: + if line[0] == 'x' or line[0] == 'z': + fo.write(f'{colorX}{line[0]}\n') + elif line[0] == '0': + if len(line) > 2: + fo.write(f'{colorI}{int(line[1:],2):02X}\n') + else: + fo.write(f'{colorI}\n') + else: + if len(line) > 2: + fo.write(f'{colorV}{int(line[1:],2):02X}\n') + else: + fo.write(f'{colorV}\n') + + except Exception as e: + fe.write('error!\n') + fe.write(str(e)) + fo.write('filter error!\n') + + fo.flush() + +if __name__ == '__main__': + sys.exit(main()) diff --git a/dev/sim/gtkwave/gtkw.tcl b/dev/sim/gtkwave/gtkw.tcl new file mode 100755 index 0000000..60415f7 --- /dev/null +++ b/dev/sim/gtkwave/gtkw.tcl @@ -0,0 +1,33 @@ +# init for a2o + +# install acts on highlighted traces; filter=0 uninstalls + +#set which_f [gtkwave::setCurrentTranslateFile ./gtkf-alias.py] +#puts "$which_f" +#gtkwave::installFileFilter $which_f + +#set which_f [gtkwave::setCurrentTranslateProc ./gtkf-ppc.py] +#puts "$which_f" +#gtkwave::installProcFilter $which_f + +set sigs [gtkwave::getDisplayedSignals] +puts "$sigs" + +# cant figure out how to unhighlight all; somehow it is remembering after reinvoke +# unhighlight all +foreach sig $sigs { + puts "$sig off" + gtkwave::setTraceHighlightFromNameMatch $sig off +} + +# highlight bus +set h [list {A2L2_AC_AN}] ;# combined - does it work? +set n [gtkwave::highlightSignalsFromList $h] + +if {$h > 0} { + set f [gtkwave::setCurrentTranslateTransProc ./gtkf-a2l2.py] + gtkwave::installTransFilter $f +} else { + puts "Didn't apply trans filter to [lindex $h 0]" +} + diff --git a/dev/sim/gtkwave/gtkwave.ini b/dev/sim/gtkwave/gtkwave.ini new file mode 100755 index 0000000..c3665a7 --- /dev/null +++ b/dev/sim/gtkwave/gtkwave.ini @@ -0,0 +1,2 @@ +color_value white +force_toolbars on \ No newline at end of file diff --git a/dev/sim/mem/boot.bin.hex b/dev/sim/mem/boot.bin.hex new file mode 100755 index 0000000..223021d --- /dev/null +++ b/dev/sim/mem/boot.bin.hex @@ -0,0 +1,982 @@ +48000400 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000CE0 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000A00 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +480000BC +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +7CBE6AA6 +2C250000 +408200EC +3C608C00 +3800001F +38400015 +38800000 +3900025F +7C7CFBA6 +7C4011A6 +7C8009A6 +7D0001A6 +4C00012C +81400A08 +3800001E +3C801000 +3900025F +65081000 +7D4011A6 +7C8009A6 +7D0001A6 +4C00012C +3C608800 +3800000F +3840003F +38800000 +3900025F +7C7CFBA6 +7C4011A6 +7C8009A6 +7D0001A6 +4C00012C +3800000D +3C801000 +3900025F +65081000 +7D4011A6 +7C8009A6 +7D0001A6 +4C00012C +81400A00 +7D400124 +4C00012C +3C200300 +7C334BA6 +38200000 +7C3603A6 +7C3D43A6 +7C3C43A6 +3C40FE00 +7C5053A6 +7C56FAA6 +70420200 +7C56FBA6 +7C3053A6 +7C3453A6 +80200A04 +7021000F +7C366BA6 +4C00012C +48000014 +81400A00 +7D400124 +4C00012C +48000004 +80200A04 +74218000 +40820008 +480006F1 +80200A04 +3C407FFF +6042FFFF +7C211038 +90200A04 +7CBE6AA6 +78A53664 +38A50A80 +81650000 +E9850008 +E9A50010 +80200A04 +70210010 +4182001C +80400A0C +3C204400 +60210012 +F8220000 +7C2803A6 +48000014 +48000005 +7C2802A6 +38210030 +7C2803A6 +7D7B03A6 +7DBA03A6 +7D816378 +7C7E6AA6 +7C4C42A6 +F8450030 +4C000064 +60000000 +60000000 +60000000 +44000022 +7CBE6AA6 +78A53664 +38A50A80 +7C4C42A6 +F8450038 +2C230000 +41820148 +48000044 +48000040 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +480000FC +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +480000FC +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +480001DC +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +8002B000 +80000001 +000000BF +10000000 +48000070 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +8002F000 +00000000 +00000000 +1003FF00 +00000000 +100004B0 +00000000 +10030000 +00000000 +10031FFF +00000000 +10030000 +00000000 +00000000 +00000000 +00000000 +8002F000 +00000000 +00000000 +1003DF00 +00000000 +100004B0 +00000000 +10032000 +00000000 +10033FFF +00000000 +10032000 +00000000 +00000000 +00000000 +00000000 +8002F000 +00000000 +00000000 +1003BF00 +00000000 +100004B0 +00000000 +10034000 +00000000 +10035FFF +00000000 +10034000 +00000000 +00000000 +00000000 +00000000 +8002F000 +00000000 +00000000 +10039F00 +00000000 +100004B0 +00000000 +10036000 +00000000 +10037FFF +00000000 +10036000 +00000000 +00000000 +00000000 +00000000 +48000080 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +7CBE6AA6 +78A53664 +38A50A80 +38C50018 +E8E60000 +38C50020 +E9060000 +7D074050 +39080001 +7D0903A6 +38C00000 +7CE83B78 +98C80000 +39080001 +4200FFF8 +39050028 +F8E80000 +4E800020 +480000B8 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +80000A00 +7C000124 +4C00012C +4BFFF894 +480000F0 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +7C0802A6 +2C230001 +41820038 +2C230010 +41820070 +2C230100 +418200A8 +2C230107 +41820120 +3860FFFF +7C0803A6 +4C000064 +60000000 +60000000 +60000000 +60000000 +7C7E6AA6 +4C000064 +48000038 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +7C6C42A6 +4C000064 +48000038 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +7CBE6AA6 +78A53664 +38A50A80 +38C50028 +E8E60000 +98870000 +38E70001 +39050020 +E9080000 +7C274000 +38600000 +40810010 +39050018 +E8E80000 +3860FFFF +F8E60000 +4C000064 +4800003C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +7C6902A6 +4BFFFCBD +7C6903A6 +7C0803A6 +38600000 +4C000064 diff --git a/dev/sim/mem/boot_ieq1.bin.hex b/dev/sim/mem/boot_ieq1.bin.hex new file mode 100755 index 0000000..bf7eddb --- /dev/null +++ b/dev/sim/mem/boot_ieq1.bin.hex @@ -0,0 +1,982 @@ +48000400 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000CE0 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000A00 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +480000BC +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +7CBE6AA6 +2C250000 +408200EC +3C608C00 +3800001F +38400415 +38800000 +3900025F +7C7CFBA6 +7C4011A6 +7C8009A6 +7D0001A6 +4C00012C +81400A08 +3800001E +3C801000 +3900025F +65081000 +7D4011A6 +7C8009A6 +7D0001A6 +4C00012C +3C608800 +3800000F +3840043F +38800000 +3900025F +7C7CFBA6 +7C4011A6 +7C8009A6 +7D0001A6 +4C00012C +3800000D +3C801000 +3900025F +65081000 +7D4011A6 +7C8009A6 +7D0001A6 +4C00012C +81400A00 +7D400124 +4C00012C +3C200300 +7C334BA6 +38200000 +7C3603A6 +7C3D43A6 +7C3C43A6 +3C40FE00 +7C5053A6 +7C56FAA6 +70420200 +7C56FBA6 +7C3053A6 +7C3453A6 +80200A04 +7021000F +7C366BA6 +4C00012C +48000014 +81400A00 +7D400124 +4C00012C +48000004 +80200A04 +74218000 +40820008 +480006F1 +80200A04 +3C407FFF +6042FFFF +7C211038 +90200A04 +7CBE6AA6 +78A53664 +38A50A80 +81650000 +E9850008 +E9A50010 +80200A04 +70210010 +4182001C +80400A0C +3C204400 +60210012 +F8220000 +7C2803A6 +48000014 +48000005 +7C2802A6 +38210030 +7C2803A6 +7D7B03A6 +7DBA03A6 +7D816378 +7C7E6AA6 +7C4C42A6 +F8450030 +4C000064 +60000000 +60000000 +60000000 +44000022 +7CBE6AA6 +78A53664 +38A50A80 +7C4C42A6 +F8450038 +2C230000 +41820148 +48000044 +48000040 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +480000FC +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +480000FC +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +480001DC +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +8002B000 +80000001 +000000BF +10000000 +48000070 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +8002F000 +00000000 +00000000 +1003FF00 +00000000 +100004B0 +00000000 +10030000 +00000000 +10031FFF +00000000 +10030000 +00000000 +00000000 +00000000 +00000000 +8002F000 +00000000 +00000000 +1003DF00 +00000000 +100004B0 +00000000 +10032000 +00000000 +10033FFF +00000000 +10032000 +00000000 +00000000 +00000000 +00000000 +8002F000 +00000000 +00000000 +1003BF00 +00000000 +100004B0 +00000000 +10034000 +00000000 +10035FFF +00000000 +10034000 +00000000 +00000000 +00000000 +00000000 +8002F000 +00000000 +00000000 +10039F00 +00000000 +100004B0 +00000000 +10036000 +00000000 +10037FFF +00000000 +10036000 +00000000 +00000000 +00000000 +00000000 +48000080 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +7CBE6AA6 +78A53664 +38A50A80 +38C50018 +E8E60000 +38C50020 +E9060000 +7D074050 +39080001 +7D0903A6 +38C00000 +7CE83B78 +98C80000 +39080001 +4200FFF8 +39050028 +F8E80000 +4E800020 +480000B8 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +80000A00 +7C000124 +4C00012C +4BFFF894 +480000F0 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +7C0802A6 +2C230001 +41820038 +2C230010 +41820070 +2C230100 +418200A8 +2C230107 +41820120 +3860FFFF +7C0803A6 +4C000064 +60000000 +60000000 +60000000 +60000000 +7C7E6AA6 +4C000064 +48000038 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +7C6C42A6 +4C000064 +48000038 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +7CBE6AA6 +78A53664 +38A50A80 +38C50028 +E8E60000 +98870000 +38E70001 +39050020 +E9080000 +7C274000 +38600000 +40810010 +39050018 +E8E80000 +3860FFFF +F8E60000 +4C000064 +4800003C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +7C6902A6 +4BFFFCBD +7C6903A6 +7C0803A6 +38600000 +4C000064 diff --git a/dev/sim/mem/boot_normal.bin.hex b/dev/sim/mem/boot_normal.bin.hex new file mode 100755 index 0000000..223021d --- /dev/null +++ b/dev/sim/mem/boot_normal.bin.hex @@ -0,0 +1,982 @@ +48000400 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000CE0 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000A00 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +480000BC +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +7CBE6AA6 +2C250000 +408200EC +3C608C00 +3800001F +38400015 +38800000 +3900025F +7C7CFBA6 +7C4011A6 +7C8009A6 +7D0001A6 +4C00012C +81400A08 +3800001E +3C801000 +3900025F +65081000 +7D4011A6 +7C8009A6 +7D0001A6 +4C00012C +3C608800 +3800000F +3840003F +38800000 +3900025F +7C7CFBA6 +7C4011A6 +7C8009A6 +7D0001A6 +4C00012C +3800000D +3C801000 +3900025F +65081000 +7D4011A6 +7C8009A6 +7D0001A6 +4C00012C +81400A00 +7D400124 +4C00012C +3C200300 +7C334BA6 +38200000 +7C3603A6 +7C3D43A6 +7C3C43A6 +3C40FE00 +7C5053A6 +7C56FAA6 +70420200 +7C56FBA6 +7C3053A6 +7C3453A6 +80200A04 +7021000F +7C366BA6 +4C00012C +48000014 +81400A00 +7D400124 +4C00012C +48000004 +80200A04 +74218000 +40820008 +480006F1 +80200A04 +3C407FFF +6042FFFF +7C211038 +90200A04 +7CBE6AA6 +78A53664 +38A50A80 +81650000 +E9850008 +E9A50010 +80200A04 +70210010 +4182001C +80400A0C +3C204400 +60210012 +F8220000 +7C2803A6 +48000014 +48000005 +7C2802A6 +38210030 +7C2803A6 +7D7B03A6 +7DBA03A6 +7D816378 +7C7E6AA6 +7C4C42A6 +F8450030 +4C000064 +60000000 +60000000 +60000000 +44000022 +7CBE6AA6 +78A53664 +38A50A80 +7C4C42A6 +F8450038 +2C230000 +41820148 +48000044 +48000040 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +480000FC +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +480000FC +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +480001DC +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +8002B000 +80000001 +000000BF +10000000 +48000070 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +8002F000 +00000000 +00000000 +1003FF00 +00000000 +100004B0 +00000000 +10030000 +00000000 +10031FFF +00000000 +10030000 +00000000 +00000000 +00000000 +00000000 +8002F000 +00000000 +00000000 +1003DF00 +00000000 +100004B0 +00000000 +10032000 +00000000 +10033FFF +00000000 +10032000 +00000000 +00000000 +00000000 +00000000 +8002F000 +00000000 +00000000 +1003BF00 +00000000 +100004B0 +00000000 +10034000 +00000000 +10035FFF +00000000 +10034000 +00000000 +00000000 +00000000 +00000000 +8002F000 +00000000 +00000000 +10039F00 +00000000 +100004B0 +00000000 +10036000 +00000000 +10037FFF +00000000 +10036000 +00000000 +00000000 +00000000 +00000000 +48000080 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +7CBE6AA6 +78A53664 +38A50A80 +38C50018 +E8E60000 +38C50020 +E9060000 +7D074050 +39080001 +7D0903A6 +38C00000 +7CE83B78 +98C80000 +39080001 +4200FFF8 +39050028 +F8E80000 +4E800020 +480000B8 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +80000A00 +7C000124 +4C00012C +4BFFF894 +480000F0 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +7C0802A6 +2C230001 +41820038 +2C230010 +41820070 +2C230100 +418200A8 +2C230107 +41820120 +3860FFFF +7C0803A6 +4C000064 +60000000 +60000000 +60000000 +60000000 +7C7E6AA6 +4C000064 +48000038 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +7C6C42A6 +4C000064 +48000038 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +7CBE6AA6 +78A53664 +38A50A80 +38C50028 +E8E60000 +98870000 +38E70001 +39050020 +E9080000 +7C274000 +38600000 +40810010 +39050018 +E8E80000 +3860FFFF +F8E60000 +4C000064 +4800003C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +7C6902A6 +4BFFFCBD +7C6903A6 +7C0803A6 +38600000 +4C000064 diff --git a/dev/sim/readme.md b/dev/sim/readme.md new file mode 100755 index 0000000..a7235e8 --- /dev/null +++ b/dev/sim/readme.md @@ -0,0 +1,127 @@ +# Simulation + +Building with cocotb, verilator, icarus... + +``` +cd coco +``` + +## cocotb + Icarus + +* A2L2 python interface partially implemented +* original boot code makes it to jump to (missing) test +* makegtkw creates netlist + +``` +make -f Makefile.icarus run +... + 7353.00ns INFO [00000919] C0: CP 0:00056C 000000000000056C + 7369.00ns INFO [00000921] C0: CP 0:000570 0000000000000570 + 7377.00ns INFO [00000922] RELD tag=08 48000000480000FC6000000060000000 1of4 crit + 7385.00ns INFO [00000923] RELD tag=08 60000000600000006000000060000000 2of4 + 7393.00ns INFO [00000924] RELD tag=08 60000000600000006000000060000000 3of4 + 7401.00ns INFO [00000925] RELD tag=08 60000000600000006000000060000000 4of4 + 7433.00ns INFO [00000929] T0 IFETCH 00000640 tag=09 len=6 WIMG:0 reld data:935 + 7481.00ns INFO [00000935] RELD tag=09 60000000600000006000000060000000 1of4 crit + 7481.00ns INFO [00000935] C0: CP 0:000574 0000000000000574 + 7489.00ns INFO [00000936] RELD tag=09 60000000600000006000000060000000 2of4 + 7497.00ns INFO [00000937] RELD tag=09 60000000600000006000000060000000 3of4 + 7505.00ns INFO [00000938] RELD tag=09 60000000600000006000000060000000 4of4 + 7593.00ns INFO [00000949] C0: CP 0:000578 1:00057C 0000000000000578 + 7697.00ns INFO [00000962] C0: CP 0:000580 0000000000000580 + 7793.00ns INFO [00000974] C0: CP 0:000584 0000000000000584 + 7801.00ns INFO [00000975] T0 IFETCH 00000700 tag=08 len=6 WIMG:0 reld data:981 + 7849.00ns INFO [00000981] RELD tag=08 48000000480000FC6000000060000000 1of4 crit + 7857.00ns INFO [00000982] RELD tag=08 60000000600000006000000060000000 2of4 + 7857.00ns INFO [00000982] C0: CP 0:000588 1:00058C 0000000000000588 + 7865.00ns INFO [00000983] RELD tag=08 60000000600000006000000060000000 3of4 + 7873.00ns INFO [00000984] RELD tag=08 60000000600000006000000060000000 4of4 + 7905.00ns INFO [00000988] T0 IFETCH 00000740 tag=09 len=6 WIMG:0 reld data:994 + 7953.00ns INFO [00000994] RELD tag=09 60000000600000006000000060000000 1of4 crit + 7961.00ns INFO [00000995] RELD tag=09 60000000600000006000000060000000 2of4 + 7969.00ns INFO [00000996] RELD tag=09 60000000600000006000000060000000 3of4 + 7977.00ns INFO [00000997] RELD tag=09 60000000600000006000000060000000 4of4 + 8001.00ns INFO [00001000] ...tick... + 8009.00ns INFO [00001001] T0 IFETCH 100004B0 tag=08 len=6 LE WIMG:0 reld data:1007 + 8057.00ns INFO [00001007] RELD tag=08 00000000000000000000000000000000 1of4 + 8065.00ns INFO [00001008] RELD tag=08 00000000000000000000000000000000 2of4 + 8073.00ns INFO [00001009] RELD tag=08 00000000000000000000000000000000 3of4 + 8081.00ns INFO [00001010] RELD tag=08 00000000000000000000000000000000 4of4 crit + 8113.00ns INFO [00001014] T0 IFETCH 100004C0 tag=09 len=6 LE WIMG:0 reld data:1020 + 8161.00ns INFO [00001020] RELD tag=09 00000000000000000000000000000000 1of4 crit + 8169.00ns INFO [00001021] RELD tag=09 00000000000000000000000000000000 2of4 + 8177.00ns INFO [00001022] RELD tag=09 00000000000000000000000000000000 3of4 + 8185.00ns INFO [00001023] RELD tag=09 00000000000000000000000000000000 4of4 + 8257.00ns INFO [00001032] T0 IFETCH 000000E0 tag=08 len=6 WIMG:0 reld data:1038 + 8257.00ns INFO Test stopped by this forked coroutine + 8257.00ns INFO tb failed + Traceback (most recent call last): + File "/home/wtf/projects/a2o-opf/dev/sim/coco/A2L2.py", line 405, in A2L2Monitor + assert False, (f'{me}: Bad IFetch @={ra:08X}') #wtf want this to end back in main code for summary + AssertionError: A2L2 Monitor: Bad IFetch @=000000E0 + 8257.00ns INFO ************************************************************************************** + ** TEST STATUS SIM TIME (ns) REAL TIME (s) RATIO (ns/s) ** + ************************************************************************************** + ** tb.tb FAIL 8257.00 154.07 53.59 ** + ************************************************************************************** + ** TESTS=0 PASS=0 FAIL=1 SKIP=0 8257.00 154.09 53.58 ** + ************************************************************************************** + + +``` + +## Verilator (can't build with coco so far) + + +* build and run a few hardcoded ops + +``` +verilator -cc --exe --trace --Mdir obj_dir --language 1364-2001 -Wno-fatal -Wno-LITENDIAN --error-limit 1 -Iverilog/work -Iverilog/trilib_clk1x -Iverilog/trilib -Iverilog/unisims c.v tb.cpp +make -C obj_dir -f Vc.mk Vc +obj_dir/Vc +Tracing enabled. +00000001Resetting... +00000001Thread stop=3 +00000011Releasing reset. +00000201Thread stop=0 +00000213 ac_an_req: T0 ra=FFFFFFF0 +00000216 an_ac_rsp: data=00000000000000000000000048000002 +00000236 ac_an_req: T0 ra=00000000 +00000239 an_ac_rsp: data=48000400000000000000000000000000 +00000251 ac_an_req: T0 ra=00000400 +00000254 an_ac_rsp: data=382000017C366BA67C366BA67C3E6AA6 +00000263 ac_an_req: T0 ra=00000410 +00000266 an_ac_rsp: data=4C00012C2C0100003820066041820008 +00000275 ac_an_req: T0 ra=00000420 +00000278 an_ac_rsp: data=382101007C2903A64E80042000000000 +00000287 ac_an_req: T0 ra=00000430 +00000290 an_ac_rsp: data=00000000000000000000000000000000 +00000299 ac_an_req: T0 ra=00000440 +00000302 an_ac_rsp: data=00000000000000000000000000000000 +00000311 ac_an_req: T0 ra=00000450 +00000314 an_ac_rsp: data=00000000000000000000000000000000 +00000319 ac_an_req: T0 ra=00000410 +00000322 an_ac_rsp: data=4C00012C2C0100003820066041820008 +00000331 ac_an_req: T0 ra=00000420 +00000334 an_ac_rsp: data=382101007C2903A64E80042000000000 +00000344 ac_an_req: T0 ra=00000420 +00000347 an_ac_rsp: data=382101007C2903A64E80042000000000 +00000356 ac_an_req: T0 ra=00000430 +00000359 an_ac_rsp: data=00000000000000000000000000000000 +00000369 ac_an_req: T0 ra=00000660 +00000372 an_ac_rsp: data=48000040000000000000000000000000 +00000384 ac_an_req: T0 ra=000006A0 +00000387 an_ac_rsp: data=48000040000000000000000000000000 +00000399 ac_an_req: T0 ra=000006E0 +00000402 an_ac_rsp: data=48000040000000000000000000000000 +00000414 ac_an_req: T0 ra=00000720 +00000417 an_ac_rsp: data=48000040000000000000000000000000 +00000429 ac_an_req: T0 ra=00000760 +00000432 an_ac_rsp: data=48000040000000000000000000000000 +00000444 ac_an_req: T0 ra=000007A0 +00000447 an_ac_rsp: data=48000040000000000000000000000000 +00000459 ac_an_req: T0 ra=000007E0 +00000462 an_ac_rsp: data=48000040000000000000000000000000 +00000474 ac_an_req: T0 ra=00000820 +... +``` \ No newline at end of file diff --git a/dev/src/asm/boot.bin b/dev/src/asm/boot.bin new file mode 100755 index 0000000000000000000000000000000000000000..804c736789b3458f64b2ff6897147971b7012808 GIT binary patch literal 3928 zcmeHJziSgw9RJ*1+Fp-JPf_Sl?4?!AkRhOi3!e0vMhGNGq0qGlwnM8!28Vzz_9Y-X zI5;?TbIQZ9qlj7;!9POKNfU6WThQY9eRtP-ky30Umc|C&yZ8Ox_w)Ug@9{oGBv1s# zJpg+xdiS5dANhFFpMIVX<8RFO%e}sxI%Qb`xgg-<)Y+oV&(| zV-?^fai%j#Ii@rrWTdWkm(~kf^_x|8Z&k2zUUaS_QwEmeGgAO2<8dQ9 zJ3R%=G?XIwEzok~n1h}PFXw;zptydqKdJvu?sw&Vzx>}Pb#(JQu5N$>3V=Zgb(FF8ExJ8r=k5W-V0@IEy9O#po})^H<#L@TJihEev7fzCxD(-dl0A%xpO%k zN^MvZ_8Yp-T34&K*@ZDLi1_0b;|LQ8zkq}VUljF)so5jeur$M+?~VZ9@M|0iju$mimebI Lr5?#9NS{9eB(wC$ literal 0 HcmV?d00001 diff --git a/dev/src/asm/boot.bin.hex b/dev/src/asm/boot.bin.hex new file mode 100755 index 0000000..223021d --- /dev/null +++ b/dev/src/asm/boot.bin.hex @@ -0,0 +1,982 @@ +48000400 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000CE0 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000A00 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +480000BC +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +7CBE6AA6 +2C250000 +408200EC +3C608C00 +3800001F +38400015 +38800000 +3900025F +7C7CFBA6 +7C4011A6 +7C8009A6 +7D0001A6 +4C00012C +81400A08 +3800001E +3C801000 +3900025F +65081000 +7D4011A6 +7C8009A6 +7D0001A6 +4C00012C +3C608800 +3800000F +3840003F +38800000 +3900025F +7C7CFBA6 +7C4011A6 +7C8009A6 +7D0001A6 +4C00012C +3800000D +3C801000 +3900025F +65081000 +7D4011A6 +7C8009A6 +7D0001A6 +4C00012C +81400A00 +7D400124 +4C00012C +3C200300 +7C334BA6 +38200000 +7C3603A6 +7C3D43A6 +7C3C43A6 +3C40FE00 +7C5053A6 +7C56FAA6 +70420200 +7C56FBA6 +7C3053A6 +7C3453A6 +80200A04 +7021000F +7C366BA6 +4C00012C +48000014 +81400A00 +7D400124 +4C00012C +48000004 +80200A04 +74218000 +40820008 +480006F1 +80200A04 +3C407FFF +6042FFFF +7C211038 +90200A04 +7CBE6AA6 +78A53664 +38A50A80 +81650000 +E9850008 +E9A50010 +80200A04 +70210010 +4182001C +80400A0C +3C204400 +60210012 +F8220000 +7C2803A6 +48000014 +48000005 +7C2802A6 +38210030 +7C2803A6 +7D7B03A6 +7DBA03A6 +7D816378 +7C7E6AA6 +7C4C42A6 +F8450030 +4C000064 +60000000 +60000000 +60000000 +44000022 +7CBE6AA6 +78A53664 +38A50A80 +7C4C42A6 +F8450038 +2C230000 +41820148 +48000044 +48000040 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +480000FC +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +480000FC +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +4800001C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +48000000 +480001DC +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +8002B000 +80000001 +000000BF +10000000 +48000070 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +8002F000 +00000000 +00000000 +1003FF00 +00000000 +100004B0 +00000000 +10030000 +00000000 +10031FFF +00000000 +10030000 +00000000 +00000000 +00000000 +00000000 +8002F000 +00000000 +00000000 +1003DF00 +00000000 +100004B0 +00000000 +10032000 +00000000 +10033FFF +00000000 +10032000 +00000000 +00000000 +00000000 +00000000 +8002F000 +00000000 +00000000 +1003BF00 +00000000 +100004B0 +00000000 +10034000 +00000000 +10035FFF +00000000 +10034000 +00000000 +00000000 +00000000 +00000000 +8002F000 +00000000 +00000000 +10039F00 +00000000 +100004B0 +00000000 +10036000 +00000000 +10037FFF +00000000 +10036000 +00000000 +00000000 +00000000 +00000000 +48000080 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +7CBE6AA6 +78A53664 +38A50A80 +38C50018 +E8E60000 +38C50020 +E9060000 +7D074050 +39080001 +7D0903A6 +38C00000 +7CE83B78 +98C80000 +39080001 +4200FFF8 +39050028 +F8E80000 +4E800020 +480000B8 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +80000A00 +7C000124 +4C00012C +4BFFF894 +480000F0 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +7C0802A6 +2C230001 +41820038 +2C230010 +41820070 +2C230100 +418200A8 +2C230107 +41820120 +3860FFFF +7C0803A6 +4C000064 +60000000 +60000000 +60000000 +60000000 +7C7E6AA6 +4C000064 +48000038 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +7C6C42A6 +4C000064 +48000038 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +7CBE6AA6 +78A53664 +38A50A80 +38C50028 +E8E60000 +98870000 +38E70001 +39050020 +E9080000 +7C274000 +38600000 +40810010 +39050018 +E8E80000 +3860FFFF +F8E60000 +4C000064 +4800003C +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +60000000 +7C6902A6 +4BFFFCBD +7C6903A6 +7C0803A6 +38600000 +4C000064 diff --git a/dev/src/asm/boot.d b/dev/src/asm/boot.d new file mode 100755 index 0000000..b1486d8 --- /dev/null +++ b/dev/src/asm/boot.d @@ -0,0 +1,3 @@ + +boot: file format elf32-powerpc + diff --git a/dev/src/asm/boot.lst b/dev/src/asm/boot.lst new file mode 100755 index 0000000..912d354 --- /dev/null +++ b/dev/src/asm/boot.lst @@ -0,0 +1,913 @@ + 1 # © IBM Corp. 2020 + 2 # Licensed under and subject to the terms of the CC-BY 4.0 + 3 # license (https://creativecommons.org/licenses/by/4.0/legalcode). + 4 # Additional rights, including the right to physically implement a softcore + 5 # that is compliant with the required sections of the Power ISA + 6 # Specification, will be available at no cost via the OpenPOWER Foundation. + 7 # This README will be updated with additional information when OpenPOWER's + 8 # license is available. + 9 + 10 # boot kernel + 11 # set up translations + 12 # set up timer facilities + 13 # set up threads + 14 # call user code + 15 # process user rc + 16 + 17 # todo: + 18 # 1. skip_printf_init flag should be threaded + 19 + 20 .include "defines.s" + 1 # © IBM Corp. 2020 + 2 # Licensed under and subject to the terms of the CC-BY 4.0 + 3 # license (https://creativecommons.org/licenses/by/4.0/legalcode). + 4 # Additional rights, including the right to physically implement a softcore + 5 # that is compliant with the required sections of the Power ISA + 6 # Specification, will be available at no cost via the OpenPOWER Foundation. + 7 # This README will be updated with additional information when OpenPOWER's + 8 # license is available. + 9 + 10 #----------------------------------------- + 11 # Defines + 12 #----------------------------------------- + 13 + 14 # Regs + 15 + 16 .set r0, 0 + 17 .set r1, 1 + 18 .set r2, 2 + 19 .set r3, 3 + 20 .set r4, 4 + 21 .set r5, 5 + 22 .set r6, 6 + 23 .set r7, 7 + 24 .set r8, 8 + 25 .set r9, 9 + 26 .set r10,10 + 27 .set r11,11 + 28 .set r12,12 + 29 .set r13,13 + 30 .set r14,14 + 31 .set r15,15 + 32 .set r16,16 + 33 .set r17,17 + 34 .set r18,18 + 35 .set r19,19 + 36 .set r20,20 + 37 .set r21,21 + 38 .set r22,22 + 39 .set r23,23 + 40 .set r24,24 + 41 .set r25,25 + 42 .set r26,26 + 43 .set r27,27 + 44 .set r28,28 + 45 .set r29,29 + 46 .set r30,30 + 47 .set r31,31 + 48 + 49 .set f0, 0 + 50 .set f1, 1 + 51 .set f2, 2 + 52 .set f3, 3 + 53 .set f4, 4 + 54 .set f5, 5 + 55 .set f6, 6 + 56 .set f7, 7 + 57 .set f8, 8 + 58 .set f9, 9 + 59 .set f10,10 + 60 .set f11,11 + 61 .set f12,12 + 62 .set f13,13 + 63 .set f14,14 + 64 .set f15,15 + 65 .set f16,16 + 66 .set f17,17 + 67 .set f18,18 + 68 .set f19,19 + 69 .set f20,20 + 70 .set f21,21 + 71 .set f22,22 + 72 .set f23,23 + 73 .set f24,24 + 74 .set f25,25 + 75 .set f26,26 + 76 .set f27,27 + 77 .set f28,28 + 78 .set f29,29 + 79 .set f30,30 + 80 .set f31,31 + 81 + 82 .set cr0, 0 + 83 .set cr1, 1 + 84 .set cr2, 2 + 85 .set cr3, 3 + 86 .set cr4, 4 + 87 .set cr5, 5 + 88 .set cr6, 6 + 89 .set cr7, 7 + 90 + 91 # SPR numbers + 92 + 93 .set srr0, 26 + 94 .set srr1, 27 + 95 .set epcr, 307 + 96 .set tar, 815 + 97 + 98 .set dbsr, 304 + 99 .set dbcr0, 308 + 100 .set dbcr1, 309 + 101 .set dbcr2, 310 + 102 .set dbcr3, 848 + 103 + 104 .set ivpr, 63 + 105 + 106 .set iucr0, 1011 + 107 .set iucr1, 883 + 108 .set iucr2, 884 + 109 + 110 .set iudbg0, 888 + 111 .set iudbg1, 889 + 112 .set iudbg2, 890 + 113 .set iulfsr, 891 + 114 .set iullcr, 892 + 115 + 116 .set mmucr0, 1020 + 117 .set mmucr1, 1021 + 118 .set mmucr2, 1022 + 119 .set mmucr3, 1023 + 120 + 121 .set tb, 268 + 122 .set tbl, 284 + 123 .set tbh, 285 + 124 + 125 .set dec, 22 + 126 .set udec, 550 + 127 .set tsr, 336 + 128 .set tcr, 340 + 129 + 130 .set xucr0, 1014 + 131 .set xucr1, 851 + 132 .set xucr2, 1016 + 133 .set xucr3, 852 + 134 .set xucr4, 853 + 135 + 136 .set tens, 438 + 137 .set tenc, 439 + 138 .set tensr, 437 + 139 + 140 .set pid, 48 + 141 .set pir, 286 + 142 .set pvr, 287 + 143 .set tir, 446 + 144 + 21 + 22 .section .text + 23 start: + 24 + 25 int_000: + 26 0000 48000400 b boot_start + 27 + 28 # critical input + 29 0004 4800001C .align 5 + 29 60000000 + 29 60000000 + 29 60000000 + 29 60000000 + 30 int_020: + 31 0020 48000000 b . + 32 + 33 # debug + 34 0024 4800001C .align 5 + 34 60000000 + 34 60000000 + 34 60000000 + 34 60000000 + 35 int_040: + 36 0040 48000000 b . + 37 + 38 # dsi + 39 0044 4800001C .align 5 + 39 60000000 + 39 60000000 + 39 60000000 + 39 60000000 + 40 int_060: + 41 0060 48000000 b . + 42 + 43 # isi + 44 0064 4800001C .align 5 + 44 60000000 + 44 60000000 + 44 60000000 + 44 60000000 + 45 int_080: + 46 0080 48000000 b . + 47 + 48 # external + 49 0084 4800001C .align 5 + 49 60000000 + 49 60000000 + 49 60000000 + 49 60000000 + 50 int_0A0: + 51 00a0 48000000 b . + 52 + 53 # alignment + 54 00a4 4800001C .align 5 + 54 60000000 + 54 60000000 + 54 60000000 + 54 60000000 + 55 int_0C0: + 56 00c0 48000000 b . + 57 + 58 # program + 59 00c4 4800001C .align 5 + 59 60000000 + 59 60000000 + 59 60000000 + 59 60000000 + 60 int_0E0: + 61 00e0 48000000 b . + 62 + 63 # fp unavailable + 64 00e4 4800001C .align 5 + 64 60000000 + 64 60000000 + 64 60000000 + 64 60000000 + 65 int_100: + 66 0100 48000000 b . + 67 + 68 # sc + 69 0104 4800001C .align 5 + 69 60000000 + 69 60000000 + 69 60000000 + 69 60000000 + 70 int_120: + 71 0120 48000CE0 b int_120_handler + 72 + 73 # apu unavailable + 74 0124 4800001C .align 5 + 74 60000000 + 74 60000000 + 74 60000000 + 74 60000000 + 75 int_140: + 76 0140 48000000 b . + 77 + 78 # decrementer + 79 0144 4800001C .align 5 + 79 60000000 + 79 60000000 + 79 60000000 + 79 60000000 + 80 int_160: + 81 0160 48000000 b . + 82 + 83 # fit + 84 0164 4800001C .align 5 + 84 60000000 + 84 60000000 + 84 60000000 + 84 60000000 + 85 int_180: + 86 0180 48000000 b . + 87 + 88 # watchdog + 89 0184 4800001C .align 5 + 89 60000000 + 89 60000000 + 89 60000000 + 89 60000000 + 90 int_1A0: + 91 01a0 48000000 b . + 92 + 93 # dtlb + 94 01a4 4800001C .align 5 + 94 60000000 + 94 60000000 + 94 60000000 + 94 60000000 + 95 int_1C0: + 96 01c0 48000000 b . + 97 + 98 # itlb + 99 01c4 4800001C .align 5 + 99 60000000 + 99 60000000 + 99 60000000 + 99 60000000 + 100 int_1E0: + 101 01e0 48000000 b . + 102 + 103 # vector unavailable + 104 01e4 4800001C .align 5 + 104 60000000 + 104 60000000 + 104 60000000 + 104 60000000 + 105 int_200: + 106 0200 48000000 b . + 107 + 108 # + 109 0204 4800001C .align 5 + 109 60000000 + 109 60000000 + 109 60000000 + 109 60000000 + 110 int_220: + 111 0220 48000000 b . + 112 + 113 # + 114 0224 4800001C .align 5 + 114 60000000 + 114 60000000 + 114 60000000 + 114 60000000 + 115 int_240: + 116 0240 48000000 b . + 117 + 118 # + 119 0244 4800001C .align 5 + 119 60000000 + 119 60000000 + 119 60000000 + 119 60000000 + 120 int_260: + 121 0260 48000000 b . + 122 + 123 # doorbell + 124 0264 4800001C .align 5 + 124 60000000 + 124 60000000 + 124 60000000 + 124 60000000 + 125 int_280: + 126 0280 48000000 b . + 127 + 128 # doorbell critical + 129 0284 4800001C .align 5 + 129 60000000 + 129 60000000 + 129 60000000 + 129 60000000 + 130 int_2A0: + 131 02a0 48000000 b . + 132 + 133 # doorbell guest + 134 02a4 4800001C .align 5 + 134 60000000 + 134 60000000 + 134 60000000 + 134 60000000 + 135 int_2C0: + 136 02c0 48000000 b . + 137 + 138 # doorbell guest critical + 139 02c4 4800001C .align 5 + 139 60000000 + 139 60000000 + 139 60000000 + 139 60000000 + 140 int_2E0: + 141 02e0 48000000 b . + 142 + 143 # hvsc + 144 02e4 4800001C .align 8 + 144 60000000 + 144 60000000 + 144 60000000 + 144 60000000 + 145 int_300: + 146 0300 48000A00 b int_300_handler + 147 + 148 # hvpriv + 149 0304 4800001C .align 5 + 149 60000000 + 149 60000000 + 149 60000000 + 149 60000000 + 150 int_320: + 151 0320 48000000 b . + 152 + 153 # lrat + 154 0324 4800001C .align 5 + 154 60000000 + 154 60000000 + 154 60000000 + 154 60000000 + 155 int_340: + 156 0340 48000000 b . + 157 + 158 # ------------------------------------------------------------------------------------------------- + 159 # initial translation + 160 # both erats: + 161 # 00000000 1M: (boot) + 162 # 10000000 1M: (test) + 163 + 164 0344 480000BC .align 8 + 164 60000000 + 164 60000000 + 164 60000000 + 164 60000000 + 165 boot_start: + 166 + 167 0400 7CBE6AA6 mfspr r5,tir # who am i? + 168 0404 2C250000 cmpdi r5,0x00 # skip unless T0 + 169 0408 408200EC bne init_t123 + 170 + 171 040c 3C608C00 lis r3,0x8C00 # 32=ecl 36:37=tlbsel (10=i, 11=d) + 172 # derat 31 @00000000 + 173 + 174 0410 3800001F li r0,0x001F # entry #31 + 175 0414 38400015 li r2,0x0015 # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/ + 176 0418 38800000 li r4,0 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63 + 177 041c 3900025F li r8,0x025F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 s + 178 + 179 0420 7C7CFBA6 mtspr mmucr0,r3 + 180 0424 7C4011A6 eratwe r2,r0,2 + 181 0428 7C8009A6 eratwe r4,r0,1 + 182 042c 7D0001A6 eratwe r8,r0,0 + 183 0430 4C00012C isync + 184 + 185 0434 81400A08 lwz r10,CONFIG+S_ERATW2(r0) # load parms for erat settings + 186 + 187 # derat 30 @100000000 + 188 + 189 0438 3800001E li r0,0x001E # entry #30 + 190 043c 3C801000 lis r4,0x1000 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63 + 191 0440 3900025F li r8,0x025F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 s + 192 0444 65081000 oris r8,r8,0x1000 + 193 + 194 0448 7D4011A6 eratwe r10,r0,2 + 195 044c 7C8009A6 eratwe r4,r0,1 + 196 0450 7D0001A6 eratwe r8,r0,0 + 197 0454 4C00012C isync + 198 + 199 0458 3C608800 lis r3,0x8800 # 32=ecl 36:37=tlbsel (10=i, 11=d) + 200 # ierat 15 @00000000 + 201 + 202 045c 3800000F li r0,0x000F # entry #15 + 203 0460 3840003F li r2,0x003F # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/ + 204 0464 38800000 li r4,0 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63 + 205 0468 3900025F li r8,0x025F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 s + 206 + 207 046c 7C7CFBA6 mtspr mmucr0,r3 + 208 0470 7C4011A6 eratwe r2,r0,2 + 209 0474 7C8009A6 eratwe r4,r0,1 + 210 0478 7D0001A6 eratwe r8,r0,0 + 211 047c 4C00012C isync + 212 + 213 # *** leave the init'd entry 14 for MT access to FFFFFFC0 + 214 # ierat 13 @10000000 + 215 + 216 0480 3800000D li r0,0x000D # entry #13 + 217 0484 3C801000 lis r4,0x1000 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63 + 218 0488 3900025F li r8,0x025F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 s + 219 048c 65081000 oris r8,r8,0x1000 + 220 + 221 0490 7D4011A6 eratwe r10,r0,2 + 222 0494 7C8009A6 eratwe r4,r0,1 + 223 0498 7D0001A6 eratwe r8,r0,0 + 224 049c 4C00012C isync + 225 + 226 # ------------------------------------------------------------------------------------------------- + 227 # init + 228 # + 229 + 230 # T0-only + 231 # set up any core facilities, then enable the others if config'd + 232 init_t0: + 233 + 234 # switch to 64b + 235 + 236 04a0 81400A00 lwz r10,CONFIG+S_MSR(r0) + 237 04a4 7D400124 mtmsr r10 + 238 04a8 4C00012C isync + 239 + 240 # other init + 241 + 242 04ac 3C200300 lis r1,0x0300 # icm=gicm=1 + 243 04b0 7C334BA6 mtspr epcr,r1 + 244 + 245 # set up timer facs + 246 + 247 04b4 38200000 li r1,0 # clear + 248 04b8 7C3603A6 mtspr dec,r1 + 249 04bc 7C3D43A6 mtspr tbh,r1 + 250 04c0 7C3C43A6 mtspr tbl,r1 + 251 + 252 04c4 3C40FE00 lis r2,0xFE00 # mask: clear enw,wis,wrs,dis,fis,udis + 253 04c8 7C5053A6 mtspr tsr,r2 + 254 + 255 04cc 7C56FAA6 mfspr r2,xucr0 + 256 04d0 70420200 andi. r2,r2,0x0200 # set tcs=0 + 257 04d4 7C56FBA6 mtspr xucr0,r2 + 258 + 259 04d8 7C3053A6 mtspr tsr,r1 # clear tsr + 260 04dc 7C3453A6 mtspr tcr,r1 # disable all timers + 261 + 262 # set thread configuration + 263 + 264 04e0 80200A04 lwz r1,CONFIG+S_FLAGS(r0) + 265 04e4 7021000F andi. r1,r1,0xF + 266 04e8 7C366BA6 mtspr tens,r1 # 60:63 = tid 3:0 enabled + 267 #not r1,r1 + 268 #mtspr tenc,r1 # in case T0 is marked disabled + 269 04ec 4C00012C isync + 270 + 271 04f0 48000014 b boot_complete + 272 + 273 # except T0 + 274 # just worry about myself + 275 + 276 init_t123: + 277 + 278 # switch to 64b + 279 + 280 04f4 81400A00 lwz r10,CONFIG+S_MSR(r0) + 281 04f8 7D400124 mtmsr r10 + 282 04fc 4C00012C isync + 283 + 284 0500 48000004 b boot_complete + 285 + 286 # ------------------------------------------------------------------------------------------------- + 287 boot_complete: + 288 + 289 # set up thread and hop to it + 290 + 291 0504 80200A04 lwz r1,CONFIG+S_FLAGS(r0) + 292 0508 74218000 andis. r1,r1,0x8000 # 1=skip initial printf init + 293 050c 40820008 bne boot_complete_1 + 294 0510 480006F1 bl printf_reset # wipe buffer + 295 + 296 boot_complete_1: + 297 + 298 0514 80200A04 lwz r1,CONFIG+S_FLAGS(r0) + 299 0518 3C407FFF lis r2,0x7FFF # clear printf flag + 300 051c 6042FFFF ori r2,r2,0xFFFF + 301 0520 7C211038 and r1,r1,r2 + 302 0524 90200A04 stw r1,CONFIG+S_FLAGS(r0) + 303 + 304 0528 7CBE6AA6 mfspr r5,tir # who am i? + 305 052c 78A53664 sldi r5,r5,6 # 64B offset + 306 0530 38A50A80 addi r5,r5,CONFIG+T_CONFIG + 307 + 308 0534 81650000 lwz r11,T_MSR(r5) + 309 0538 E9850008 ld r12,T_STACK(r5) + 310 053c E9A50010 ld r13,T_ENTRY(r5) + 311 + 312 0540 80200A04 lwz r1,CONFIG+S_FLAGS(r0) + 313 0544 70210010 andi. r1,r1,FLAG_EOT_SC + 314 0548 4182001C beq eot_blr + 315 + 316 eot_sc: + 317 + 318 054c 80400A0C lwz r2,CONFIG+S_EOT_SC(r0) + 319 0550 3C204400 lis r1,0x4400 # 'sc 1' + 320 0554 60210012 ori r1,r1,0022 + 321 0558 F8220000 std r1,0x0(r2) + 322 055c 7C2803A6 mtlr r1 # prog will blr to sc + 323 0560 48000014 b process_start + 324 + 325 eot_blr: + 326 + 327 0564 48000005 bl 4 + 328 0568 7C2802A6 mflr r1 + 329 056c 38210030 addi r1,r1,0x30 # !!!!!!!!!!!!!!! <-- WARNING! + 330 0570 7C2803A6 mtlr r1 # prog will blr to exec_complete + 331 + 332 process_start: + 333 + 334 0574 7D7B03A6 mtspr srr1,r11 # msr + 335 0578 7DBA03A6 mtspr srr0,r13 # @entry + 336 057c 7D816378 mr r1,r12 # @stack + 337 0580 7C7E6AA6 mfspr r3,tir # tid - main(tid) if yall want it + 338 + 339 0584 7C4C42A6 mfspr r2,tb + 340 0588 F8450030 std r2,T_TIMER_START(r5) + 341 058c 4C000064 rfi + 342 0590 60000000 nop # !!!!!!!!!!!!!!! pads for lr calc + 343 0594 60000000 nop + 344 0598 60000000 nop + 345 + 346 # ------------------------------------------------------------------------------------------------- + 347 exec_complete: + 348 # allow blr to here, or it will be entered by sc directly + 349 + 350 # user blr'd here... + 351 059c 44000022 sc 1 # hvsc back to sup state + 352 + 353 exec_complete_sup: + 354 05a0 7CBE6AA6 mfspr r5,tir # who am i? + 355 05a4 78A53664 sldi r5,r5,6 # 64B offset + 356 05a8 38A50A80 addi r5,r5,CONFIG+T_CONFIG + 357 + 358 05ac 7C4C42A6 mfspr r2,tb + 359 05b0 F8450038 std r2,T_TIMER_END(r5) + 360 + 361 05b4 2C230000 cmpdi r3,0 # check rc + 362 05b8 41820148 beq pass + 363 05bc 48000044 b fail + 364 + 365 # ------------------------------------------------------------------------------------------------- + 366 # dead zone + 367 05c0 48000040 .align 8 + 367 60000000 + 367 60000000 + 367 60000000 + 367 60000000 + 368 fail: + 369 0600 48000000 b . + 370 + 371 # ------------------------------------------------------------------------------------------------- + 372 # happy ending + 373 0604 480000FC .align 8 + 373 60000000 + 373 60000000 + 373 60000000 + 373 60000000 + 374 pass: + 375 0700 48000000 b . + 376 + 377 # ------------------------------------------------------------------------------------------------- + 378 + 379 # dec + 380 0704 480000FC .align 11 + 380 60000000 + 380 60000000 + 380 60000000 + 380 60000000 + 381 int_800: + 382 0800 48000000 b . + 383 + 384 # perf + 385 0804 4800001C .align 5 + 385 60000000 + 385 60000000 + 385 60000000 + 385 60000000 + 386 int_820: + 387 0820 48000000 b . + 388 + 389 .set CONFIG,0x0A00 + 390 # ------------------------------------------------------------------------------------------------- + 391 # config info + 392 0824 480001DC .align 9 + 392 60000000 + 392 60000000 + 392 60000000 + 392 60000000 + 393 + 394 0a00 8002B000 .long 0x8002B000 # sup MSR cm=1 ce=1 ee=1 pr=0 fp=1 me=1 fe=00 de=0 is=0 ds=0 + 395 0a04 80000001 .long 0x80000001 # flags: skip_printf_init=0 eot_sc=27 thr_en=28:31(T3:T0) + 396 0a08 000000BF .long 0x000000BF # erat w2 (test) # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wi + 397 0a0c 10000000 .long 0x10000000 # @user eot sc + 398 + 399 # per-thread configs (64B each) + 400 0a10 48000070 .align 7 + 400 60000000 + 400 60000000 + 400 60000000 + 400 60000000 + 401 0a80 8002F000 .long 0x8002F000 # usr MSR cm=1 ce=1 ee=1 pr=1 fp=1 me=1 fe=00 de=0 is=0 ds=0 + 402 0a84 00000000 .long 0x00000000 # + 403 0a88 00000000 .long 0x00000000 # + 404 0a8c 1003FF00 .long 0x1003FF00 # @stack + 405 0a90 00000000 .long 0x00000000 # + 406 0a94 100004B0 .long 0x100004B0 # @entry + 407 0a98 00000000 .long 0 + 408 0a9c 10030000 .long 0x10030000 # @print_start + 409 0aa0 00000000 .long 0 + 410 0aa4 10031FFF .long 0x10031FFF # @print_end + 411 0aa8 00000000 .long 0 + 412 0aac 10030000 .long 0x10030000 # print ptr + 413 0ab0 00000000 .quad 0 # start tb + 413 00000000 + 414 0ab8 00000000 .quad 0 # end tb + 414 00000000 + 415 + 416 0ac0 8002F000 .long 0x8002F000 # usr MSR cm=1 ce=1 ee=1 pr=1 fp=1 me=1 fe=00 de=0 is=0 ds=0 + 417 0ac4 00000000 .long 0x00000000 # + 418 0ac8 00000000 .long 0x00000000 # + 419 0acc 1003DF00 .long 0x1003DF00 # @stack + 420 0ad0 00000000 .long 0x00000000 # + 421 0ad4 100004B0 .long 0x100004B0 # @entry + 422 0ad8 00000000 .long 0 + 423 0adc 10032000 .long 0x10032000 # @print_start + 424 0ae0 00000000 .long 0 + 425 0ae4 10033FFF .long 0x10033FFF # @print_end + 426 0ae8 00000000 .long 0 + 427 0aec 10032000 .long 0x10032000 # print ptr + 428 0af0 00000000 .quad 0 # start tb + 428 00000000 + 429 0af8 00000000 .quad 0 # end tb + 429 00000000 + 430 + 431 0b00 8002F000 .long 0x8002F000 # usr MSR cm=1 ce=1 ee=1 pr=1 fp=1 me=1 fe=00 de=0 is=0 ds=0 + 432 0b04 00000000 .long 0x00000000 # flags + 433 0b08 00000000 .long 0x00000000 # + 434 0b0c 1003BF00 .long 0x1003BF00 # @stack + 435 0b10 00000000 .long 0x00000000 # + 436 0b14 100004B0 .long 0x100004B0 # @entry + 437 0b18 00000000 .long 0 + 438 0b1c 10034000 .long 0x10034000 # @print_start + 439 0b20 00000000 .long 0 + 440 0b24 10035FFF .long 0x10035FFF # @print_end + 441 0b28 00000000 .long 0 + 442 0b2c 10034000 .long 0x10034000 # print ptr + 443 0b30 00000000 .quad 0 # start tb + 443 00000000 + 444 0b38 00000000 .quad 0 # end tb + 444 00000000 + 445 + 446 0b40 8002F000 .long 0x8002F000 # usr MSR cm=1 ce=1 ee=1 pr=1 fp=1 me=1 fe=00 de=0 is=0 ds=0 + 447 0b44 00000000 .long 0x00000000 # flags + 448 0b48 00000000 .long 0x00000000 # + 449 0b4c 10039F00 .long 0x10039F00 # @stack + 450 0b50 00000000 .long 0x00000000 # + 451 0b54 100004B0 .long 0x100004B0 # @entry + 452 0b58 00000000 .long 0 + 453 0b5c 10036000 .long 0x10036000 # @print_start + 454 0b60 00000000 .long 0 + 455 0b64 10037FFF .long 0x10037FFF # @print_end + 456 0b68 00000000 .long 0 + 457 0b6c 10036000 .long 0x10036000 # print ptr + 458 0b70 00000000 .quad 0 # start tb + 458 00000000 + 459 0b78 00000000 .quad 0 # end tb + 459 00000000 + 460 + 461 + 462 .set S_MSR,0x00 + 463 .set S_FLAGS,0x04 + 464 .set S_ERATW2,0x08 + 465 .set S_EOT_SC,0x0C + 466 + 467 .set T_CONFIG,0x80 + 468 .set T_MSR,0x00 + 469 .set T_FLAGS,0x04 + 470 .set T_STACK,0x08 + 471 .set T_ENTRY,0x10 + 472 .set T_TIMER_START,0x30 + 473 .set T_TIMER_END,0x38 + 474 .set T_PRINTSTART, 0x18 + 475 .set T_PRINTEND, 0x20 + 476 .set T_PRINTF, 0x28 + 477 .set FLAG_EOT_SC,0x10 + 478 + 479 + 480 # ------------------------------------------------------------------------------------------------- + 481 # other stuff + 482 0b80 48000080 .align 10 + 482 60000000 + 482 60000000 + 482 60000000 + 482 60000000 + 483 + 484 # clear buffer and reset pointer to start + 485 .align 6 + 486 printf_reset: + 487 + 488 0c00 7CBE6AA6 mfspr r5,tir # who am i? + 489 0c04 78A53664 sldi r5,r5,6 # 64B offset + 490 0c08 38A50A80 addi r5,r5,CONFIG+T_CONFIG + 491 + 492 0c0c 38C50018 addi r6,r5,T_PRINTSTART + 493 0c10 E8E60000 ld r7,0(r6) # buffer start + 494 0c14 38C50020 addi r6,r5,T_PRINTEND + 495 0c18 E9060000 ld r8,0(r6) # buffer end + 496 0c1c 7D074050 sub r8,r8,r7 + 497 0c20 39080001 addi r8,r8,1 # num bytes + 498 + 499 0c24 7D0903A6 mtctr r8 + 500 0c28 38C00000 li r6,0 + 501 0c2c 7CE83B78 mr r8,r7 + 502 printf_reset_clr: + 503 0c30 98C80000 stb r6,0(r8) + 504 0c34 39080001 addi r8,r8,1 + 505 0c38 4200FFF8 bdnz printf_reset_clr + 506 + 507 0c3c 39050028 addi r8,r5,T_PRINTF + 508 0c40 F8E80000 std r7,0(r8) # reset ptr + 509 + 510 0c44 4E800020 blr + 511 + 512 + 513 # hvsc + 514 0c48 480000B8 .align 8 + 514 60000000 + 514 60000000 + 514 60000000 + 514 60000000 + 515 # go to exec_complete_sup in sup mode + 516 int_300_handler: + 517 + 518 0d00 80000A00 lwz r0,CONFIG+S_MSR(r0) + 519 0d04 7C000124 mtmsr r0 + 520 0d08 4C00012C isync + 521 0d0c 4BFFF894 b exec_complete_sup + 522 + 523 # sc + 524 0d10 480000F0 .align 8 + 524 60000000 + 524 60000000 + 524 60000000 + 524 60000000 + 525 # r3 is id, remaining are function-specific + 526 # not preserving r0, r3-r9 right now + 527 # + 528 # 0001 whoami + 529 # 0010 tick + 530 # 0100 putchar r4=c + 531 # 0106 printf_mode *NI* + 532 # 0107 printf_rst + 533 # + 534 int_120_handler: + 535 + 536 0e00 7C0802A6 mflr r0 + 537 + 538 0e04 2C230001 cmpdi r3,0x0001 + 539 0e08 41820038 beq sc_whoami + 540 0e0c 2C230010 cmpdi r3,0x0010 + 541 0e10 41820070 beq sc_tick + 542 0e14 2C230100 cmpdi r3,0x100 + 543 0e18 418200A8 beq sc_putchar + 544 0e1c 2C230107 cmpdi r3,0x107 + 545 0e20 41820120 beq sc_printf_rst + 546 + 547 0e24 3860FFFF li r3,-1 + 548 0e28 7C0803A6 mtlr r0 + 549 0e2c 4C000064 rfi + 550 + 551 # thread id + 552 0e30 60000000 .align 6 + 552 60000000 + 552 60000000 + 552 60000000 + 553 sc_whoami: + 554 0e40 7C7E6AA6 mfspr r3,tir + 555 0e44 4C000064 rfi + 556 + 557 # tb + 558 0e48 48000038 .align 6 + 558 60000000 + 558 60000000 + 558 60000000 + 558 60000000 + 559 sc_tick: + 560 0e80 7C6C42A6 mfspr r3,tb + 561 0e84 4C000064 rfi + 562 + 563 # wrap buffer; could add flag to stop when full, or reset + 564 0e88 48000038 .align 6 + 564 60000000 + 564 60000000 + 564 60000000 + 564 60000000 + 565 sc_putchar: + 566 + 567 0ec0 7CBE6AA6 mfspr r5,tir # who am i? + 568 0ec4 78A53664 sldi r5,r5,6 # 64B offset + 569 0ec8 38A50A80 addi r5,r5,CONFIG+T_CONFIG + 570 + 571 0ecc 38C50028 addi r6,r5,T_PRINTF + 572 0ed0 E8E60000 ld r7,0(r6) # buffer ptr + 573 0ed4 98870000 stb r4,0(r7) # store char + 574 0ed8 38E70001 addi r7,r7,1 + 575 + 576 0edc 39050020 addi r8,r5,T_PRINTEND + 577 0ee0 E9080000 ld r8,0(r8) # buffer end + 578 0ee4 7C274000 cmpd r7,r8 + 579 0ee8 38600000 li r3,0 # rc=normal + 580 0eec 40810010 ble sc_putchar_ok + 581 0ef0 39050018 addi r8,r5,T_PRINTSTART + 582 0ef4 E8E80000 ld r7,0(r8) # buffer start + 583 0ef8 3860FFFF li r3,-1 # rc=full + 584 sc_putchar_ok: + 585 0efc F8E60000 std r7,0(r6) # save ptr + 586 + 587 0f00 4C000064 rfi + 588 + 589 # clear buffer and reset pointer to start + 590 0f04 4800003C .align 6 + 590 60000000 + 590 60000000 + 590 60000000 + 590 60000000 + 591 sc_printf_rst: + 592 + 593 0f40 7C6902A6 mfctr r3 + 594 + 595 0f44 4BFFFCBD bl printf_reset + 596 + 597 0f48 7C6903A6 mtctr r3 + 598 0f4c 7C0803A6 mtlr r0 + 599 0f50 38600000 li r3,0 + 600 + 601 0f54 4C000064 rfi + 602 diff --git a/dev/src/asm/boot.o b/dev/src/asm/boot.o new file mode 100755 index 0000000000000000000000000000000000000000..983e04c82f9da66a01d4ed72bcda646b6927d271 GIT binary patch literal 11952 zcmeI2U2Ggz701uaIE`b{WK&Wapfu|Qh^1O#ch+$>s;jKyI3Kd>ME26O;$dyCcWNh2 zyzFjTm#)b=QbZ9TwE{#yR5ge!@PJevfE1C|m8b+rAP@pkK2sjR5j>=71%{?I|2uQ< z%-?Ae(WIhE@Rje!{N{Yzd-lwoyPF*A?%ieEmW0KUTQMdO-oc>tynmI^?Q*%vA1yUY z5m<`AQUsPFuoQu%2wYbY*dq{eVd3xct3i@Y9kOS)b0xt?8P`HnDTn>Z|o?W=*|XTT!19tKKVC>vX265ps8Q z)MCC&p)n>?7s+%CKB{c3hOO;avIUu&uVe?lVB31X^4k%2q?+ofr{f~kcBfvwyQ^O9 z=&E;QUYF|rfqM1cf7gpUY^mOhIVW)4Hc+p{n;MGEvbx%S$e%l&<+W@R*9}Uh(p*z9 zXxt+=y`-)?GRGDMcPuPan`7z6aINArd8&OReX6N8T@X2ULK@GVl9;w1>pU*E*D_5j zJK{TKuvu=I-+(!`ICbR@by>B=uBV$Nq1e!npu!hb+u*TP7{@b0U2;iDMn7 z->x-Wi{F|wNmYXLMbEc8)ac;+wD^3Y)~e1giX(36t66(>e8;uv)42?J+oJOKthzlw$YjGt@795-eB z$z`S`2DWZ)PEB@UVIH!2?j2V%cYpn3cD-le!kOwA&ZCHt3WBmJS18!VF8TX9xP2)# zaQwZYTo74!=?zpY*a$iKu@H%nlOJmpaq?q*iFgC~`8Dxn#D7a1yGL05NPKxn{TPJv z!Q8?EUm;%+QW5BeyovZbh+`a<)x=kZROFq+Zzg^lal|An?+6-$DE%#1Zqbp^)^Zy8O z&i{`R=lrh_=lp+&IOqSzh;#l=5$F7$CeHbPf;i{@Cy8_Ze}*{c|Kr3t|36Qh^Z$#) zIscy^&iVfp;++4dh;#mblQ`%9w}^B8f15bx|96OU{y$Be^ZyKS&j06#bN)Y1ob&(3 z#5wGx~t}?P=oAMBK??O#69r>I zOvLf(3k!Y-3;jCr5Q}}9c!v0F#2a3TxPv{%JTH7qvwsqCX^iCUUy_{};=d#L2#ft9 zae83vbCI28%>PMzZDhz%?_wQi+HS>xjG4dGNFIA^$RjMyM&h(C=T73WNWn>6hHrDPBT6w61t5@!G`OB3`?ATg6L@w+*+{ zZQO@f4_-ZZ_2AWmR}Wr2c=h1bgI5n;J$Uut)q__LUOjmA;MIdy4_-ZZ_24yM+Jf4S zx>d@hQbILJDHQW1sSK55WVo!FJZ`8q>9?-mrey5FVoAo1s++1!`mKw0WcUGv&?$ya z!Eq0!(2c|N;lsX`-z9@9H|SDQ8OGl@>ZlwYDdeRBwF-15eHGOv{juw}DZg!#O5sRZ zHIT=sB*n22RP+x*8~xakN-mK|$neBOC0EAMDgi>c{9A3hZ`XZV_no@$(tUT(Ct*tI zCAB{K-00Aek?}&{Dyi)ywY{Xam(=!>+FnxIbG1EJ+jF(PtMy&2?`nNl>$_S%rS;J- znnz08OZoQ3D!ED$NimS??(fVVz^8IVp#;D^1N~@s^>*$a2x63zHD_3hfb8v|t_n;Xb>cJ-j|?#uSyFUnr7dmnI@6cG5~@si({^J)$O zFP0|qg>qScDA`*i9%1(b)3X_F=E}Y4tt6ceL5q<*c?!KK;94eQ^8yXw;KbW)* zNE!ji>UCvv`}_CyWdqatLTT#Zu0>1B boot.lst +powerpc-linux-gnu-objdump -d boot.o > boot.d + +# creat binary +powerpc-linux-gnu-objcopy -O binary boot.o boot.bin + +# create ascii hex +../bin/bin2init boot.bin + +``` \ No newline at end of file diff --git a/dev/src/bin/bin2init b/dev/src/bin/bin2init new file mode 100755 index 0000000..b89e435 --- /dev/null +++ b/dev/src/bin/bin2init @@ -0,0 +1,27 @@ +#!/usr/bin/python3 + +# read .bin (objcopy -O binary x.elf x.bin) and create ascii block file + +import sys +from binascii import hexlify, unhexlify + +def x2d(i): + return int(i, 16) + +inFile = sys.argv[1] +#size = sys.argv[2] + +outFile = inFile + '.hex' + +lines = [] +with open(inFile, 'rb') as binFile: + word = binFile.read(4) + while word: + hex = hexlify(word) + lines.append(hex.decode('utf-8').upper() + '\n') + word = binFile.read(4) + +# need to pad to full size? +with open(outFile, 'w') as txtFile: + txtFile.writelines(lines) + diff --git a/dev/synth/readme.md b/dev/synth/readme.md new file mode 100755 index 0000000..92a9dc5 --- /dev/null +++ b/dev/synth/readme.md @@ -0,0 +1,194 @@ +# Synthesis + +``` +yosys -s synth.yo &> yosys.txt +``` + +## Arrays + +``` +grep tri_1 verilog/work/* +verilog/work/fu_fpr.v: tri_144x78_2r4w fpr0( +verilog/work/fu_fpr.v: tri_144x78_2r4w fpr1( +verilog/work/iuq_ic_dir.v: tri_128x34_4w_1r1w idir( +verilog/work/mmq.v: tri_128x168_1w_0 tlb_array0( +verilog/work/mmq.v: tri_128x168_1w_0 tlb_array1( +verilog/work/mmq.v: tri_128x168_1w_0 tlb_array2( +verilog/work/mmq.v: tri_128x168_1w_0 tlb_array3( +verilog/work/mmq.v: tri_128x16_1r1w_1 lru_array0( +verilog/work/rv.v: tri_144x78_2r4w +verilog/work/xu_gpr.v: tri_144x78_2r4w gpr0( +verilog/work/xu_gpr.v: tri_144x78_2r4w gpr1( + +grep tri_2 verilog/work/* +verilog/work/lq_data.v: tri_256x144_8w_1r1w #(.addressable_ports(256), .addressbus_width(8), .port_bitwidth(144), .bit_write_type(9), .ways(8)) tridcarr( + +grep tri_3 verilog/work/* +verilog/work/lq_pfetch.v: tri_32x70_2w_1r1w rpt( + +grep tri_5 verilog/work/* +verilog/work/iuq_ic_dir.v: tri_512x162_4w_0 idata( + +grep tri_6 verilog/work/* +verilog/work/iuq_btb.v: tri_64x72_1r1w btb0( +verilog/work/lq_ctl.v: tri_64x34_8w_1r1w #(.addressable_ports(64), .addressbus_width(6), .port_bitwidth(WAYDATASIZE), .ways(8)) arr( +verilog/work/lq_ldq_relq.v: tri_64x144_1r1w rdat( +verilog/work/lq_lsq.v: tri_64x34_8w_1r1w #(.addressable_ports(64), .addressbus_width(6), .port_bitwidth(WAYDATASIZE), .ways(8)) arr( +verilog/work/xu_spr.v: tri_64x72_1r1w xu_spr_aspr( + +grep tri_bht verilog/work/* +verilog/work/iuq.v: tri_bht_1024x8_1r1w bht0( +verilog/work/iuq.v: tri_bht_1024x8_1r1w bht1( +verilog/work/iuq.v: tri_bht_512x4_1r1w bht2( + +grep tri_cam verilog/work/* +verilog/work/iuq_ic_ierat.v: tri_cam_16x143_1r1w1c ierat_cam( +verilog/work/lq_derat.v: tri_cam_32x143_1r1w1c derat_cam( + +grep tri_iuq verilog/work/* +verilog/work/iuq_cpl.v: tri_iuq_cpl_arr #(.ADDRESSABLE_PORTS(64), .ADDRESSBUS_WIDTH(6), .PORT_BITWIDTH(entry_length), .LATCHED_READ(1'b1), .LATCHED_READ_DATA(1'b1), .LATCHED_WRITE(1'b1)) +``` + +## By Unit + +* XU (GPR, SPR) +verilog/work/xu_gpr.v: tri_144x78_2r4w gpr0( +verilog/work/xu_gpr.v: tri_144x78_2r4w gpr1( +verilog/work/xu_spr.v: tri_64x72_1r1w xu_spr_aspr( + +* FU (FPR) +verilog/work/fu_fpr.v: tri_144x78_2r4w fpr0( +verilog/work/fu_fpr.v: tri_144x78_2r4w fpr1( + +* RV (LQ) +verilog/work/rv.v: tri_144x78_2r4w + +* IU (CPL, ERAT, DIR, DATA, BTB, BHT) +verilog/work/iuq_cpl.v: tri_iuq_cpl_arr #(.ADDRESSABLE_PORTS(64), .ADDRESSBUS_WIDTH(6), .PORT_BITWIDTH(entry_length), .LATCHED_READ(1'b1), .LATCHED_READ_DATA(1'b1), .LATCHED_WRITE(1'b1)) +verilog/work/iuq_ic_ierat.v: tri_cam_16x143_1r1w1c ierat_cam( +verilog/work/iuq_ic_dir.v: tri_128x34_4w_1r1w idir( +verilog/work/iuq_ic_dir.v: tri_512x162_4w_0 idata( +verilog/work/iuq_btb.v: tri_64x72_1r1w btb0( +verilog/work/iuq.v: tri_bht_1024x8_1r1w bht0( +verilog/work/iuq.v: tri_bht_1024x8_1r1w bht1( +verilog/work/iuq.v: tri_bht_512x4_1r1w bht2( + +* LQ (ERAT, DIR, DATA. PFETCH, RLDQ, STQ) +verilog/work/lq_derat.v: tri_cam_32x143_1r1w1c derat_cam( +verilog/work/lq_pfetch.v: tri_32x70_2w_1r1w rpt( +verilog/work/lq_data.v: tri_256x144_8w_1r1w #(.addressable_ports(256), .addressbus_width(8), .port_bitwidth(144), .bit_write_type(9), .ways(8)) tridcarr( +verilog/work/lq_ctl.v: tri_64x34_8w_1r1w #(.addressable_ports(64), .addressbus_width(6), .port_bitwidth(WAYDATASIZE), .ways(8)) arr( +verilog/work/lq_ldq_relq.v: tri_64x144_1r1w rdat( +verilog/work/lq_lsq.v: tri_64x34_8w_1r1w #(.addressable_ports(64), .addressbus_width(6), .port_bitwidth(WAYDATASIZE), .ways(8)) arr( + +* MMU (TLB) +verilog/work/mmq.v: tri_128x168_1w_0 tlb_array0( +verilog/work/mmq.v: tri_128x168_1w_0 tlb_array1( +verilog/work/mmq.v: tri_128x168_1w_0 tlb_array2( +verilog/work/mmq.v: tri_128x168_1w_0 tlb_array3( +verilog/work/mmq.v: tri_128x16_1r1w_1 lru_array0( + +## By Type + +### Normal + +* tri_144x78_2r4w +verilog/work/xu_gpr.v: tri_144x78_2r4w gpr0( +verilog/work/xu_gpr.v: tri_144x78_2r4w gpr1( +verilog/work/fu_fpr.v: tri_144x78_2r4w fpr0( +verilog/work/fu_fpr.v: tri_144x78_2r4w fpr1( +verilog/work/rv.v: tri_144x78_2r4w + +* tri_64x72_1r1w +verilog/work/xu_spr.v: tri_64x72_1r1w xu_spr_aspr( +verilog/work/iuq_btb.v: tri_64x72_1r1w btb0( + +* tri_512x162_4w_0 +verilog/work/iuq_ic_dir.v: tri_512x162_4w_0 idata( + +* tri_32x70_2w_1r1w +verilog/work/lq_pfetch.v: tri_32x70_2w_1r1w rpt( + +* tri_256x144_8w_1r1w +verilog/work/lq_data.v: tri_256x144_8w_1r1w #(.addressable_ports(256), .addressbus_width(8), .port_bitwidth(144), .bit_write_type(9), .ways(8)) tridcarr( + +* tri_64x34_8w_1r1w +verilog/work/lq_ctl.v: tri_64x34_8w_1r1w #(.addressable_ports(64), .addressbus_width(6), .port_bitwidth(WAYDATASIZE), .ways(8)) arr( +verilog/work/lq_lsq.v: tri_64x34_8w_1r1w #(.addressable_ports(64), .addressbus_width(6), .port_bitwidth(WAYDATASIZE), .ways(8)) arr( + +* tri_64x144_1r1w +verilog/work/lq_ldq_relq.v: tri_64x144_1r1w rdat( + +* tri_128x168_1w_0 +verilog/work/mmq.v: tri_128x168_1w_0 tlb_array0( +verilog/work/mmq.v: tri_128x168_1w_0 tlb_array1( +verilog/work/mmq.v: tri_128x168_1w_0 tlb_array2( +verilog/work/mmq.v: tri_128x168_1w_0 tlb_array3( + +* tri_128x16_1r1w_1 +verilog/work/mmq.v: tri_128x16_1r1w_1 lru_array0( + +### Complex + +#### Branch History + +* tri_bht_1024x8_1r1w +verilog/work/iuq.v: tri_bht_1024x8_1r1w bht0( +verilog/work/iuq.v: tri_bht_1024x8_1r1w bht1( + * inner array: + tri_512x16_1r1w_1 bht0( + + +* tri_bht_512x4_1r1w +verilog/work/iuq.v: tri_bht_512x4_1r1w bht2( + * inner array: + tri_512x16_1r1w_1 bht0( + + +#### Completion + +* tri_iuq_cpl_arr +verilog/work/iuq_cpl.v: tri_iuq_cpl_arr #(.ADDRESSABLE_PORTS(64), .ADDRESSBUS_WIDTH(6), .PORT_BITWIDTH(entry_length), .LATCHED_READ(1'b1), .LATCHED_READ_DATA(1'b1), .LATCHED_WRITE(1'b1)) + * inner arrays (143) + RAM64X1D #(.INIT(64'h0000000000000000)) RAM64X1D0( + RAM64X1D #(.INIT(64'h0000000000000000)) RAM64X1D1( + * =2x64x143 + +#### ERATs (CAM) + +* tri_cam_16x143_1r1w1c +verilog/work/iuq_ic_ierat.v: tri_cam_16x143_1r1w1c ierat_cam( + +* tri_cam_32x143_1r1w1c +verilog/work/lq_derat.v: tri_cam_32x143_1r1w1c derat_cam( + + +## Summary + +* the difficult arrays are the 2r4w (gpr, fpr, rv) and the cams; everything else is 1r1w + +* cpl array is 1r1w (written in iu6, read in cp0), arranged even/odd for i0/i1; CPL_Q_DEPTH=32 means 32 even + 32 odd(?) + +* some of these are directly changed with gen parameters; others may be do-able with some combo or parameters/spr settings/simple logic changes + + * GPR rename pool size + * FPR rename pool size + * completion queue depth + * IERAT size + * IC size + * IC ways + * BTB size + * BHT size + * DERAT size + * DC size + * DC ways + * TLB size + * TLB ways + +* e.g. no xlate, small caches + + * IERAT, DERAT replaced with single-entry always-hit (no CAMs) + * IC, DC 1W small data + * no TLB + * alter BTB, BHT, rename, completion as necessary + * mmu logic (and fpu if not needed) could be dropped diff --git a/dev/synth/synth.yo b/dev/synth/synth.yo new file mode 100755 index 0000000..5118f13 --- /dev/null +++ b/dev/synth/synth.yo @@ -0,0 +1,13 @@ +#read_verilog ../verilog/unisims +# blockbox versions +read_verilog ../verilog/unisims_synth + +read_verilog -I../verilog/trilib ../verilog/trilib/* +read_verilog -I../verilog/trilib ../verilog/work/* + +hierarchy -top c + +proc; opt; memory -nomap; opt -fast +#check -assert + +#synth -top c \ No newline at end of file diff --git a/dev/synth/verilog b/dev/synth/verilog new file mode 120000 index 0000000..2630032 --- /dev/null +++ b/dev/synth/verilog @@ -0,0 +1 @@ +../verilog \ No newline at end of file diff --git a/dev/verilog/smt2/tri_a2o.vh b/dev/verilog/smt2/tri_a2o.vh new file mode 100755 index 0000000..74b7210 --- /dev/null +++ b/dev/verilog/smt2/tri_a2o.vh @@ -0,0 +1,174 @@ +// © IBM Corp. 2022 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`ifndef _tri_a2o_vh_ +`define _tri_a2o_vh_ + +`include "tri.vh" + +// Use this line for 1 thread. Comment out for 2 thread design. +//`define THREADS1 + +`define gpr_t 3'b000 +`define cr_t 3'b001 +`define lr_t 3'b010 +`define ctr_t 3'b011 +`define xer_t 3'b100 +`define spr_t 3'b101 +`define axu0_t 3'b110 +`define axu1_t 3'b111 + +`ifdef THREADS1 + `define THREADS 1 + `define THREAD_POOL_ENC 0 + `define THREADS_POOL_ENC 0 +`else + `define THREADS 2 + `define THREAD_POOL_ENC 1 + `define THREADS_POOL_ENC 1 +`endif +`define EFF_IFAR_ARCH 62 +`define EFF_IFAR_WIDTH 20 +`define EFF_IFAR 20 +`define FPR_POOL_ENC 6 +`define REGMODE 6 +`define FPR_POOL 64 +`define REAL_IFAR_WIDTH 42 +`define EMQ_ENTRIES 4 +`define GPR_WIDTH 64 +`define ITAG_SIZE_ENC 7 +`define CPL_Q_DEPTH 32 +`define CPL_Q_DEPTH_ENC 6 +`define GPR_WIDTH_ENC 6 +`define GPR_POOL_ENC 6 +`define GPR_POOL 64 +`define GPR_UCODE_POOL 4 +`define CR_POOL_ENC 5 +`define CR_POOL 24 +`define CR_UCODE_POOL 1 +`define BR_POOL_ENC 3 +`define BR_POOL 8 +`define LR_POOL_ENC 3 +`define LR_POOL 8 +`define LR_UCODE_POOL 0 +`define CTR_POOL_ENC 3 +`define CTR_POOL 8 +`define CTR_UCODE_POOL 0 +`define XER_POOL_ENC 4 +`define XER_POOL 12 +`define XER_UCODE_POOL 0 +`define LDSTQ_ENTRIES 16 +`define LDSTQ_ENTRIES_ENC 4 +`define STQ_ENTRIES 12 +`define STQ_ENTRIES_ENC 4 +`define STQ_FWD_ENTRIES 4 // number of stq entries that can be forwarded from +`define STQ_DATA_SIZE 64 // 64 or 128 Bit store data sizes supported +`define DC_SIZE 15 // 14 => 16K L1D$, 15 => 32K L1D$ +`define CL_SIZE 6 // 6 => 64B CLINE, 7 => 128B CLINE +`define LMQ_ENTRIES 8 +`define LMQ_ENTRIES_ENC 3 +`define LGQ_ENTRIES 8 +`define AXU_SPARE_ENC 3 +`define RV_FX0_ENTRIES 12 +`define RV_FX1_ENTRIES 12 +`define RV_LQ_ENTRIES 16 +`define RV_AXU0_ENTRIES 12 +`define RV_AXU1_ENTRIES 0 +`define RV_FX0_ENTRIES_ENC 4 +`define RV_FX1_ENTRIES_ENC 4 +`define RV_LQ_ENTRIES_ENC 4 +`define RV_AXU0_ENTRIES_ENC 4 +`define RV_AXU1_ENTRIES_ENC 1 +`define UCODE_ENTRIES 8 +`define UCODE_ENTRIES_ENC 3 +`define FXU1_ENABLE 1 +`define TYPE_WIDTH 3 +`define IBUFF_INSTR_WIDTH 70 +`define IBUFF_IFAR_WIDTH 20 +`define IBUFF_DEPTH 16 +`define PF_IAR_BITS 12 // number of IAR bits used by prefetch +`define FXU0_PIPE_START 1 +`define FXU0_PIPE_END 8 +`define FXU1_PIPE_START 1 +`define FXU1_PIPE_END 5 +`define LQ_LOAD_PIPE_START 4 +`define LQ_LOAD_PIPE_END 8 +`define LQ_REL_PIPE_START 2 +`define LQ_REL_PIPE_END 4 +`define LOAD_CREDITS 8 +`define STORE_CREDITS 4 +`define IUQ_ENTRIES 4 // Instruction Fetch Queue Size +`define MMQ_ENTRIES 2 // MMU Queue Size +`define CR_WIDTH 4 +`define BUILD_PFETCH 1 // 1=> include pfetch in the build, 0=> build without pfetch +`define PF_IFAR_WIDTH 12 +`define PFETCH_INITIAL_DEPTH 0 // the initial value for the SPR that determines how many lines to prefetch +`define PFETCH_Q_SIZE_ENC 3 // number of bits to address queue size (3 => 8 entries, 4 => 16 entries) +`define PFETCH_Q_SIZE 8 // number of entries +`define INCLUDE_IERAT_BYPASS 1 // 0 => Removes IERAT Bypass logic, 1=> includes (power savings) +`define XER_WIDTH 10 + +`define INIT_BHT 0 // 0=> array init time set to 16 clocks, 1=> increased to 512 to init BHT +`define INIT_IUCR0 16'h00FA // BP enabled +`define INIT_MASK 2'b10 +`define RELQ_INCLUDE 0 // Reload Queue Included + +`define G_BRANCH_LEN `EFF_IFAR_WIDTH + 1 + 1 + `EFF_IFAR_WIDTH + 3 + 18 + 1 + +`define INIT_CPCR0 32'h0C0C100C // 000a aaaa 000b bbbb 000c cccc 000d dddd watermarks: a=fx0 b=fx1 c=ls d=sq ---- um p.543 wrong!; was this in vlog: hex 0C0C100C = 202117132 +//`define INIT_CPCR0 32'h01010201 // 1/1/2/1 + +`define INIT_CPCR1 32'h000C0C00 // 0000 0000 000a aaaa 000b bbbb 0000 0000 credits: a=fx0 b=fx1 c=ls d=sq ---- um p.544 wrong!; was this in vlog: hex 000C0C00 = 789504 +//`define INIT_CPCR1 32'h00010100 // 1/1 + +// IERAT boot config entry values +`define IERAT_BCFG_EPN_0TO15 0 +`define IERAT_BCFG_EPN_16TO31 0 +`define IERAT_BCFG_EPN_32TO47 (2 ** 16) - 1 // 1 for 64K, 65535 for 4G +`define IERAT_BCFG_EPN_48TO51 (2 ** 4) - 1 // 15 for 64K or 4G +`define IERAT_BCFG_RPN_22TO31 0 // (2 ** 10) - 1 for x3ff +`define IERAT_BCFG_RPN_32TO47 (2 ** 16) - 1 // 1 for 64K, 8181 for 512M, 65535 for 4G +`define IERAT_BCFG_RPN_48TO51 (2 ** 4) - 1 // 15 for 64K or 4G +`define IERAT_BCFG_RPN2_32TO47 0 // 0 to match dd1 hardwired value; (2**16)-1 for same 64K page +`define IERAT_BCFG_RPN2_48TO51 0 // 0 to match dd1 hardwired value; (2**4)-2 for adjacent 4K page +`define IERAT_BCFG_ATTR 0 // u0-u3, endian + +// DERAT boot config entry values +`define DERAT_BCFG_EPN_0TO15 0 +`define DERAT_BCFG_EPN_16TO31 0 +`define DERAT_BCFG_EPN_32TO47 (2 ** 16) - 1 // 1 for 64K, 65535 for 4G +`define DERAT_BCFG_EPN_48TO51 (2 ** 4) - 1 // 15 for 64K or 4G +`define DERAT_BCFG_RPN_22TO31 0 // (2 ** 10) - 1 for x3ff +`define DERAT_BCFG_RPN_32TO47 (2 ** 16) - 1 // 1 for 64K, 8191 for 512M, 65535 for 4G +`define DERAT_BCFG_RPN_48TO51 (2 ** 4) - 1 // 15 for 64K or 4G +`define DERAT_BCFG_RPN2_32TO47 0 // 0 to match dd1 hardwired value; (2**16)-1 for same 64K page +`define DERAT_BCFG_RPN2_48TO51 0 // 0 to match dd1 hardwired value; (2**4)-2 for adjacent 4K page +`define DERAT_BCFG_ATTR 0 // u0-u3, endian + +// Do NOT add any defines below this line +`endif //_tri_a2o_vh_ diff --git a/dev/verilog/sweetpea/tri_a2o.vh b/dev/verilog/sweetpea/tri_a2o.vh new file mode 100755 index 0000000..909b55b --- /dev/null +++ b/dev/verilog/sweetpea/tri_a2o.vh @@ -0,0 +1,266 @@ +// © IBM Corp. 2022 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +// small-core test - see what parms work +// all the _enc's should be created automatically (clog2) + +`ifndef _tri_a2o_vh_ +`define _tri_a2o_vh_ + +`include "tri.vh" + +`define THREADS1 + +// ----------------------------------------------------------------------------------------------------------------- +// updates +// * some may have restrictions (by design or by coding) +// * some may be dependent +// * some may be dependent on reg settings + +// breaks sim +//`define CPL_Q_DEPTH 8 +//`define CPL_Q_DEPTH_ENC 3 + +//`define EMQ_ENTRIES 1 +//`define LDSTQ_ENTRIES 4 +//`define LDSTQ_ENTRIES_ENC 2 +`define LMQ_ENTRIES 4 +`define LMQ_ENTRIES_ENC 2 +`define LGQ_ENTRIES 4 + +// needs src updates + +// limited to 5+: +// ../../verilog/work/iuq_ibuf.v:383: error: part select buffer_valid_q[0:-1] is out of order. +// ../../verilog/work/iuq_ibuf.v:410: error: part select buffer_head_q[0:-1] is out of order. +//`define IBUFF_DEPTH 5 + +// limited to 14/15(?) +//`define DC_SIZE 14 // fails sim + +// STQ_FWD_ENTRIES must be 1 or more less than STQ_ENTRIES: +// ../../verilog/work/lq_stq.v:2972: error: part select ex4_fwd_sel[4:3] is out of order. +//`define STQ_ENTRIES 4 +//`define STQ_ENTRIES_ENC 2 +//`define STQ_FWD_ENTRIES 3 + +//`define GPR_POOL 8 +//`define GPR_POOL_ENC 3 +//`define GPR_UCODE_POOL 2 +//`define FPR_POOL 2 +//`define FPR_POOL_ENC 1 +//`define CR_POOL 8 +//`define CR_POOL_ENC 3 +//`define CR_UCODE_POOL 1 +//`define BR_POOL 8 +//`define BR_POOL_ENC 3 +//`define LR_POOL 8 +//`define LR_POOL_ENC 3 +//`define LR_UCODE_POOL 0 +//`define CTR_POOL 8 +//`define CTR_POOL_ENC 3 +//`define CTR_UCODE_POOL 0 +//`define XER_POOL 8 +//`define XER_POOL_ENC 3 +//`define XER_UCODE_POOL 0 +//`define RV_FX0_ENTRIES 4 +//`define RV_FX0_ENTRIES_ENC 2 +//`define RV_FX1_ENTRIES 4 +//`define RV_FX1_ENTRIES_ENC 2 +//`define RV_LQ_ENTRIES 4 +//`define RV_LQ_ENTRIES_ENC 2 +//`define RV_AXU0_ENTRIES 4 +//`define RV_AXU0_ENTRIES_ENC 2 +//`define UCODE_ENTRIES 2 +//`define UCODE_ENTRIES_ENC 1 + +// other interesting to try... +//`define FXU1_ENABLE 0 +//`define BUILD_PFETCH 0 +//`define INCLUDE_IERAT_BYPASS 0 + +// things to add in code +// 1. ic_size +// 2. ierat_entries (and/or needs to be replacement code? e.g. no mmu, all hits) +// 3. derat_entries (and/or needs to be replacement code? e.g. no mmu, all hits) + +// ----------------------------------------------------------------------------------------------------------------- + + +`define gpr_t 3'b000 +`define cr_t 3'b001 +`define lr_t 3'b010 +`define ctr_t 3'b011 +`define xer_t 3'b100 +`define spr_t 3'b101 +`define axu0_t 3'b110 +`define axu1_t 3'b111 + +`ifdef THREADS1 + `define THREADS 1 + `define THREAD_POOL_ENC 0 + `define THREADS_POOL_ENC 0 +`else + `define THREADS 2 + `define THREAD_POOL_ENC 1 + `define THREADS_POOL_ENC 1 +`endif + +`define EFF_IFAR_ARCH 62 +`define EFF_IFAR_WIDTH 20 +`define EFF_IFAR 20 +`define REGMODE 6 +`define REAL_IFAR_WIDTH 42 +`define GPR_WIDTH 64 +`define GPR_WIDTH_ENC 6 +`define ITAG_SIZE_ENC 7 + +`define CPL_Q_DEPTH 32 +`define CPL_Q_DEPTH_ENC 6 +`define GPR_POOL_ENC 6 +`define GPR_POOL 64 +`define GPR_UCODE_POOL 4 +`define FPR_POOL 64 +`define FPR_POOL_ENC 6 +`define CR_POOL_ENC 5 +`define CR_POOL 24 +`define CR_UCODE_POOL 1 +`define BR_POOL_ENC 3 +`define BR_POOL 8 +`define LR_POOL_ENC 3 +`define LR_POOL 8 +`define LR_UCODE_POOL 0 +`define CTR_POOL_ENC 3 +`define CTR_POOL 8 +`define CTR_UCODE_POOL 0 +`define XER_POOL_ENC 4 +`define XER_POOL 12 +`define XER_UCODE_POOL 0 + +`define EMQ_ENTRIES 4 +`define LDSTQ_ENTRIES 16 // ls order queue +`define LDSTQ_ENTRIES_ENC 4 +//`define LMQ_ENTRIES 8 // load miss queue +//`define LMQ_ENTRIES_ENC 3 +//`define LGQ_ENTRIES 8 // load gather queue + +`define STQ_ENTRIES 12 // store queue +`define STQ_ENTRIES_ENC 4 +`define STQ_FWD_ENTRIES 4 // number of stq entries that can be forwarded from +`define STQ_DATA_SIZE 64 // 64 or 128 Bit store data sizes supported + +`define DC_SIZE 15 // 14 => 16K L1D$, 15 => 32K L1D$ +`define CL_SIZE 6 // 6 => 64B CLINE, 7 => 128B CLINE + +`define AXU_SPARE_ENC 3 + +`define RV_FX0_ENTRIES 12 +`define RV_FX0_ENTRIES_ENC 4 +`define RV_FX1_ENTRIES 12 +`define RV_FX1_ENTRIES_ENC 4 +`define RV_LQ_ENTRIES 16 +`define RV_LQ_ENTRIES_ENC 4 +`define RV_AXU0_ENTRIES 12 +`define RV_AXU0_ENTRIES_ENC 4 +`define RV_AXU1_ENTRIES 0 +`define RV_AXU1_ENTRIES_ENC 1 +`define UCODE_ENTRIES 8 +`define UCODE_ENTRIES_ENC 3 + +`define FXU1_ENABLE 1 + +`define TYPE_WIDTH 3 +`define IBUFF_INSTR_WIDTH 70 +`define IBUFF_IFAR_WIDTH 20 +`define PF_IAR_BITS 12 // number of IAR bits used by prefetch +`define FXU0_PIPE_START 1 +`define FXU0_PIPE_END 8 +`define FXU1_PIPE_START 1 +`define FXU1_PIPE_END 5 +`define LQ_LOAD_PIPE_START 4 +`define LQ_LOAD_PIPE_END 8 +`define LQ_REL_PIPE_START 2 +`define LQ_REL_PIPE_END 4 +`define IBUFF_DEPTH 16 + +`define LOAD_CREDITS 8 +`define STORE_CREDITS 32 + +`define IUQ_ENTRIES 4 // Instruction Fetch Queue Size +`define MMQ_ENTRIES 2 // MMU Queue Size + +`define CR_WIDTH 4 +`define BUILD_PFETCH 1 // 1=> include pfetch in the build, 0=> build without pfetch +`define PF_IFAR_WIDTH 12 +`define PFETCH_INITIAL_DEPTH 0 // the initial value for the SPR that determines how many lines to prefetch +`define PFETCH_Q_SIZE_ENC 3 // number of bits to address queue size (3 => 8 entries, 4 => 16 entries) +`define PFETCH_Q_SIZE 8 // number of entries +`define INCLUDE_IERAT_BYPASS 1 // 0 => Removes IERAT Bypass logic, 1=> includes (power savings) +`define XER_WIDTH 10 + +`define INIT_BHT 0 // 0=> array init time set to 16 clocks, 1=> increased to 512 to init BHT +`define INIT_IUCR0 16'h00FA // BP enabled + +`define INIT_MASK 2'b10 +`define RELQ_INCLUDE 0 // Reload Queue Included + +`define G_BRANCH_LEN `EFF_IFAR_WIDTH + 1 + 1 + `EFF_IFAR_WIDTH + 3 + 18 + 1 + +`define INIT_CPCR0 32'h0C0C100C // 000a aaaa 000b bbbb 000c cccc 000d dddd watermarks: a=fx0 b=fx1 c=ls d=sq ---- um p.543 wrong!; was this in vlog: hex 0C0C100C = 202117132 +//`define INIT_CPCR0 32'h01010201 // 1/1/2/1 + +`define INIT_CPCR1 32'h000C0C00 // 0000 0000 000a aaaa 000b bbbb 0000 0000 credits: a=fx0 b=fx1 c=ls d=sq ---- um p.544 wrong!; was this in vlog: hex 000C0C00 = 789504 +//`define INIT_CPCR1 32'h00010100 // 1/1 + +// IERAT boot config entry values +`define IERAT_BCFG_EPN_0TO15 0 +`define IERAT_BCFG_EPN_16TO31 0 +`define IERAT_BCFG_EPN_32TO47 (2 ** 16) - 1 // 1 for 64K, 65535 for 4G +`define IERAT_BCFG_EPN_48TO51 (2 ** 4) - 1 // 15 for 64K or 4G +`define IERAT_BCFG_RPN_22TO31 0 // (2 ** 10) - 1 for x3ff +`define IERAT_BCFG_RPN_32TO47 (2 ** 16) - 1 // 1 for 64K, 8181 for 512M, 65535 for 4G +`define IERAT_BCFG_RPN_48TO51 (2 ** 4) - 1 // 15 for 64K or 4G +`define IERAT_BCFG_RPN2_32TO47 0 // 0 to match dd1 hardwired value; (2**16)-1 for same 64K page +`define IERAT_BCFG_RPN2_48TO51 0 // 0 to match dd1 hardwired value; (2**4)-2 for adjacent 4K page +`define IERAT_BCFG_ATTR 0 // u0-u3, endian + +// DERAT boot config entry values +`define DERAT_BCFG_EPN_0TO15 0 +`define DERAT_BCFG_EPN_16TO31 0 +`define DERAT_BCFG_EPN_32TO47 (2 ** 16) - 1 // 1 for 64K, 65535 for 4G +`define DERAT_BCFG_EPN_48TO51 (2 ** 4) - 1 // 15 for 64K or 4G +`define DERAT_BCFG_RPN_22TO31 0 // (2 ** 10) - 1 for x3ff +`define DERAT_BCFG_RPN_32TO47 (2 ** 16) - 1 // 1 for 64K, 8191 for 512M, 65535 for 4G +`define DERAT_BCFG_RPN_48TO51 (2 ** 4) - 1 // 15 for 64K or 4G +`define DERAT_BCFG_RPN2_32TO47 0 // 0 to match dd1 hardwired value; (2**16)-1 for same 64K page +`define DERAT_BCFG_RPN2_48TO51 0 // 0 to match dd1 hardwired value; (2**4)-2 for adjacent 4K page +`define DERAT_BCFG_ATTR 0 // u0-u3, endian + +// Do NOT add any defines below this line +`endif //_tri_a2o_vh_ diff --git a/dev/verilog/trilib/tri.vh b/dev/verilog/trilib/tri.vh new file mode 100755 index 0000000..893ad12 --- /dev/null +++ b/dev/verilog/trilib/tri.vh @@ -0,0 +1,43 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +// *!**************************************************************** +// *! FILENAME : tri_a2o.param +// *! DESCRIPTION : Constants for use throughout core +// *! CONTENTS : +// *! +// *!**************************************************************** + +`ifndef _tri_vh_ +`define _tri_vh_ + +`define NCLK_WIDTH 6 // 0 1xClk, 1 Reset, 2 2xClk, 3 4xClk, 4 Even .5xClk, 5 Odd .5x Clk +//`define EXPAND_TYPE 1 + +// Do NOT add any defines below this line +`endif //_tri_vh_ diff --git a/dev/verilog/trilib/tri_128x168_1w_0.v b/dev/verilog/trilib/tri_128x168_1w_0.v new file mode 100755 index 0000000..a81df61 --- /dev/null +++ b/dev/verilog/trilib/tri_128x168_1w_0.v @@ -0,0 +1,258 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILENAME : tri_128x168_1w_0.v +// *! DESCRIPTION : 128 Entry x 168 bit x 1 way array +// *! +// *!**************************************************************** + +`include "tri_a2o.vh" + +module tri_128x168_1w_0( + gnd, + vdd, + vcs, + nclk, + act, + ccflush_dc, + scan_dis_dc_b, + scan_diag_dc, + abst_scan_in, + repr_scan_in, + time_scan_in, + abst_scan_out, + repr_scan_out, + time_scan_out, + lcb_d_mode_dc, + lcb_clkoff_dc_b, + lcb_act_dis_dc, + lcb_mpw1_dc_b, + lcb_mpw2_dc_b, + lcb_delay_lclkr_dc, + lcb_sg_1, + lcb_time_sg_0, + lcb_repr_sg_0, + lcb_abst_sl_thold_0, + lcb_repr_sl_thold_0, + lcb_time_sl_thold_0, + lcb_ary_nsl_thold_0, + lcb_bolt_sl_thold_0, + tc_lbist_ary_wrt_thru_dc, + abist_en_1, + din_abist, + abist_cmp_en, + abist_raw_b_dc, + data_cmp_abist, + addr_abist, + r_wb_abist, + pc_bo_enable_2, + pc_bo_reset, + pc_bo_unload, + pc_bo_repair, + pc_bo_shdata, + pc_bo_select, + bo_pc_failout, + bo_pc_diagloop, + tri_lcb_mpw1_dc_b, + tri_lcb_mpw2_dc_b, + tri_lcb_delay_lclkr_dc, + tri_lcb_clkoff_dc_b, + tri_lcb_act_dis_dc, + write_enable, + addr, + data_in, + data_out +); + parameter addressable_ports = 128; // number of addressable register in this array + parameter addressbus_width = 7; // width of the bus to address all ports (2^addressbus_width >= addressable_ports) + parameter port_bitwidth = 168; // bitwidth of ports + parameter ways = 1; // number of ways + + // POWER PINS + inout gnd; + inout vdd; + inout vcs; + + // CLOCK and CLOCKCONTROL ports + input [0:`NCLK_WIDTH-1] nclk; + input act; + input ccflush_dc; + input scan_dis_dc_b; + input scan_diag_dc; + + input abst_scan_in; + input repr_scan_in; + input time_scan_in; + output abst_scan_out; + output repr_scan_out; + output time_scan_out; + + input lcb_d_mode_dc; + input lcb_clkoff_dc_b; + input lcb_act_dis_dc; + input [0:4] lcb_mpw1_dc_b; + input lcb_mpw2_dc_b; + input [0:4] lcb_delay_lclkr_dc; + + input lcb_sg_1; + input lcb_time_sg_0; + input lcb_repr_sg_0; + + input lcb_abst_sl_thold_0; + input lcb_repr_sl_thold_0; + input lcb_time_sl_thold_0; + input lcb_ary_nsl_thold_0; + input lcb_bolt_sl_thold_0; // thold for any regs inside backend + + input tc_lbist_ary_wrt_thru_dc; + input abist_en_1; + input [0:3] din_abist; + input abist_cmp_en; + input abist_raw_b_dc; + input [0:3] data_cmp_abist; + input [0:6] addr_abist; + input r_wb_abist; + + // BOLT-ON + input pc_bo_enable_2; // general bolt-on enable, probably DC + input pc_bo_reset; // execute sticky bit decode + input pc_bo_unload; + input pc_bo_repair; // load repair reg + input pc_bo_shdata; // shift data for timing write + input pc_bo_select; // select for mask and hier writes + output bo_pc_failout; // fail/no-fix reg + output bo_pc_diagloop; + input tri_lcb_mpw1_dc_b; + input tri_lcb_mpw2_dc_b; + input tri_lcb_delay_lclkr_dc; + input tri_lcb_clkoff_dc_b; + input tri_lcb_act_dis_dc; + + // PORTS + input write_enable; + input [0:addressbus_width-1] addr; + input [0:port_bitwidth-1] data_in; + output [0:port_bitwidth-1] data_out; + + // tri_128x168_1w_0 + + parameter ramb_base_width = 36; + parameter ramb_base_addr = 9; + parameter ramb_width_mult = (port_bitwidth - 1)/ramb_base_width + 1; // # of RAMB's per way + + + // Configuration Statement for NCsim + //for all:RAMB16_S36_S36 use entity unisim.RAMB16_S36_S36; + + wire [0:(ramb_base_width*ramb_width_mult-1)] ramb_data_in; + wire [0:(ramb_base_width*ramb_width_mult-1)] ramb_data_out[0:ways-1]; + wire [0:ramb_base_addr-1] ramb_addr; + + wire [0:ways-1] write; + wire tidn; + (* analysis_not_referenced="true" *) + wire unused; + wire [0:(ramb_base_width*ramb_width_mult-1)] unused_dob; + + + generate + begin + assign tidn = 1'b0; + + if (addressbus_width < ramb_base_addr) + begin + assign ramb_addr[0:(ramb_base_addr - addressbus_width - 1)] = {(ramb_base_addr-addressbus_width){1'b0}}; + assign ramb_addr[ramb_base_addr - addressbus_width:ramb_base_addr - 1] = addr; + end + if (addressbus_width >= ramb_base_addr) + begin + assign ramb_addr = addr[addressbus_width - ramb_base_addr:addressbus_width - 1]; + end + + genvar i; + for (i = 0; i < (ramb_base_width * ramb_width_mult); i = i + 1) + begin : din + if (i < port_bitwidth) + begin + assign ramb_data_in[i] = data_in[i]; + end + if (i >= port_bitwidth) + begin + assign ramb_data_in[i] = 1'b0; + end + end + + genvar w; + for (w = 0; w < ways; w = w + 1) + begin : aw + assign write[w] = write_enable; + + genvar x; + for (x = 0; x < ramb_width_mult; x = x + 1) + begin : ax + + RAMB16_S36_S36 + #(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only + ram( + .DOA(ramb_data_out[w][x * ramb_base_width:x * ramb_base_width + 31]), + .DOB(unused_dob[x * ramb_base_width:x * ramb_base_width + 31]), + .DOPA(ramb_data_out[w][x * ramb_base_width + 32:x * ramb_base_width + 35]), + .DOPB(unused_dob[x * ramb_base_width + 32:x * ramb_base_width + 35]), + .ADDRA(ramb_addr), + .ADDRB(ramb_addr), + .CLKA(nclk[0]), + .CLKB(tidn), + .DIA(ramb_data_in[x * ramb_base_width:x * ramb_base_width + 31]), + .DIB(ramb_data_in[x * ramb_base_width:x * ramb_base_width + 31]), + .DIPA(ramb_data_in[x * ramb_base_width + 32:x * ramb_base_width + 35]), + .DIPB(ramb_data_in[x * ramb_base_width + 32:x * ramb_base_width + 35]), + .ENA(act), + .ENB(tidn), + .SSRA(nclk[1]), + .SSRB(tidn), + .WEA(write[w]), + .WEB(tidn) + ); + end //ax + assign data_out[w * port_bitwidth:((w + 1) * port_bitwidth) - 1] = ramb_data_out[w][0:port_bitwidth - 1]; + end //aw + end + endgenerate + + assign abst_scan_out = abst_scan_in; + assign repr_scan_out = repr_scan_in; + assign time_scan_out = time_scan_in; + + assign bo_pc_failout = 1'b0; + assign bo_pc_diagloop = 1'b0; + + assign unused = |({ramb_data_out[0][port_bitwidth:ramb_base_width * ramb_width_mult - 1], ccflush_dc, scan_dis_dc_b, scan_diag_dc, lcb_d_mode_dc, lcb_clkoff_dc_b, lcb_act_dis_dc, lcb_mpw1_dc_b, lcb_mpw2_dc_b, lcb_delay_lclkr_dc, lcb_sg_1, lcb_time_sg_0, lcb_repr_sg_0, lcb_abst_sl_thold_0, lcb_repr_sl_thold_0, lcb_time_sl_thold_0, lcb_ary_nsl_thold_0, lcb_bolt_sl_thold_0, tc_lbist_ary_wrt_thru_dc, abist_en_1, din_abist, abist_cmp_en, abist_raw_b_dc, data_cmp_abist, addr_abist, r_wb_abist, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, tri_lcb_act_dis_dc, gnd, vdd, vcs, nclk, unused_dob}); +endmodule diff --git a/dev/verilog/trilib/tri_128x16_1r1w_1.v b/dev/verilog/trilib/tri_128x16_1r1w_1.v new file mode 100755 index 0000000..4b35c1f --- /dev/null +++ b/dev/verilog/trilib/tri_128x16_1r1w_1.v @@ -0,0 +1,335 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//***************************************************************************** +// Description: Tri Array Wrapper +// +//***************************************************************************** + +`include "tri_a2o.vh" + +module tri_128x16_1r1w_1( + vdd, + vcs, + gnd, + nclk, + rd_act, + wr_act, + lcb_d_mode_dc, + lcb_clkoff_dc_b, + lcb_mpw1_dc_b, + lcb_mpw2_dc_b, + lcb_delay_lclkr_dc, + ccflush_dc, + scan_dis_dc_b, + scan_diag_dc, + func_scan_in, + func_scan_out, + lcb_sg_0, + lcb_sl_thold_0_b, + lcb_time_sl_thold_0, + lcb_abst_sl_thold_0, + lcb_ary_nsl_thold_0, + lcb_repr_sl_thold_0, + time_scan_in, + time_scan_out, + abst_scan_in, + abst_scan_out, + repr_scan_in, + repr_scan_out, + abist_di, + abist_bw_odd, + abist_bw_even, + abist_wr_adr, + wr_abst_act, + abist_rd0_adr, + rd0_abst_act, + tc_lbist_ary_wrt_thru_dc, + abist_ena_1, + abist_g8t_rd0_comp_ena, + abist_raw_dc_b, + obs0_abist_cmp, + lcb_bolt_sl_thold_0, + pc_bo_enable_2, + pc_bo_reset, + pc_bo_unload, + pc_bo_repair, + pc_bo_shdata, + pc_bo_select, + bo_pc_failout, + bo_pc_diagloop, + tri_lcb_mpw1_dc_b, + tri_lcb_mpw2_dc_b, + tri_lcb_delay_lclkr_dc, + tri_lcb_clkoff_dc_b, + tri_lcb_act_dis_dc, + bw, + wr_adr, + rd_adr, + di, + dout +); + parameter addressable_ports = 128; // number of addressable register in this array + parameter addressbus_width = 7; // width of the bus to address all ports (2^addressbus_width >= addressable_ports) + parameter port_bitwidth = 16; // bitwidth of ports + parameter ways = 1; // number of ways + + // POWER PINS + inout vdd; + inout vcs; + inout gnd; + + input [0:`NCLK_WIDTH-1] nclk; + + input rd_act; + input wr_act; + + // DC TEST PINS + input lcb_d_mode_dc; + input lcb_clkoff_dc_b; + input [0:4] lcb_mpw1_dc_b; + input lcb_mpw2_dc_b; + input [0:4] lcb_delay_lclkr_dc; + + input ccflush_dc; + input scan_dis_dc_b; + input scan_diag_dc; + input func_scan_in; + output func_scan_out; + + input lcb_sg_0; + input lcb_sl_thold_0_b; + input lcb_time_sl_thold_0; + input lcb_abst_sl_thold_0; + input lcb_ary_nsl_thold_0; + input lcb_repr_sl_thold_0; + input time_scan_in; + output time_scan_out; + input abst_scan_in; + output abst_scan_out; + input repr_scan_in; + output repr_scan_out; + + input [0:3] abist_di; + input abist_bw_odd; + input abist_bw_even; + input [0:6] abist_wr_adr; + input wr_abst_act; + input [0:6] abist_rd0_adr; + input rd0_abst_act; + input tc_lbist_ary_wrt_thru_dc; + input abist_ena_1; + input abist_g8t_rd0_comp_ena; + input abist_raw_dc_b; + input [0:3] obs0_abist_cmp; + + // BOLT-ON + input lcb_bolt_sl_thold_0; + input pc_bo_enable_2; // general bolt-on enable + input pc_bo_reset; // reset + input pc_bo_unload; // unload sticky bits + input pc_bo_repair; // execute sticky bit decode + input pc_bo_shdata; // shift data for timing write and diag loop + input pc_bo_select; // select for mask and hier writes + output bo_pc_failout; // fail/no-fix reg + output bo_pc_diagloop; + input tri_lcb_mpw1_dc_b; + input tri_lcb_mpw2_dc_b; + input tri_lcb_delay_lclkr_dc; + input tri_lcb_clkoff_dc_b; + input tri_lcb_act_dis_dc; + + input [0:15] bw; + input [0:6] wr_adr; + input [0:6] rd_adr; + input [0:15] di; + + output [0:15] dout; + + // tri_128x16_1r1w_1 + + // Configuration Statement for NCsim + //for all:ramb16_s36_s36 use entity unisim.RAMB16_S36_S36; + + wire clk; + wire clk2x; + wire [0:8] b0addra; + wire [0:8] b0addrb; + wire wea; + wire web; + wire wren_a; + // Latches + reg reset_q; + reg gate_fq; + wire gate_d; + wire [0:35] r_data_out_1_d; + reg [0:35] r_data_out_1_fq; + wire [0:35] w_data_in_0; + + wire [0:35] r_data_out_0_bram; + wire [0:35] r_data_out_1_bram; + + wire toggle_d; + reg toggle_q; + wire toggle2x_d; + reg toggle2x_q; + + (* analysis_not_referenced="true" *) + wire unused; + + assign clk = nclk[0]; + assign clk2x = nclk[2]; + + + always @(posedge clk) + begin: rlatch + reset_q <= nclk[1]; + end + + // + // NEW clk2x gate logic start + // + + always @(posedge nclk[0]) + begin: tlatch + if (reset_q == 1'b1) + toggle_q <= 1'b1; + else + toggle_q <= toggle_d; + end + + + always @(posedge nclk[2]) + begin: flatch + toggle2x_q <= toggle2x_d; + gate_fq <= gate_d; + r_data_out_1_fq <= r_data_out_1_d; + end + + assign toggle_d = (~toggle_q); + assign toggle2x_d = toggle_q; + + // should force gate_fq to be on during odd 2x clock (second half of 1x clock). + //gate_d <= toggle_q xor toggle2x_q; + // if you want the first half do the following + assign gate_d = (~(toggle_q ^ toggle2x_q)); + + assign b0addra[2:8] = wr_adr; + assign b0addrb[2:8] = rd_adr; + + // Unused Address Bits + assign b0addra[0:1] = 2'b00; + assign b0addrb[0:1] = 2'b00; + + // port a is a read-modify-write port + assign wren_a = ((bw != 16'b0000000000000000 & wr_act == 1'b1)) ? 1'b1 : + 1'b0; + assign wea = wren_a & (~(gate_fq)); // write in 2nd half of nclk + assign web = 1'b0; + assign w_data_in_0[0] = (bw[0] == 1'b1) ? di[0] : + r_data_out_0_bram[0]; + assign w_data_in_0[1] = (bw[1] == 1'b1) ? di[1] : + r_data_out_0_bram[1]; + assign w_data_in_0[2] = (bw[2] == 1'b1) ? di[2] : + r_data_out_0_bram[2]; + assign w_data_in_0[3] = (bw[3] == 1'b1) ? di[3] : + r_data_out_0_bram[3]; + assign w_data_in_0[4] = (bw[4] == 1'b1) ? di[4] : + r_data_out_0_bram[4]; + assign w_data_in_0[5] = (bw[5] == 1'b1) ? di[5] : + r_data_out_0_bram[5]; + assign w_data_in_0[6] = (bw[6] == 1'b1) ? di[6] : + r_data_out_0_bram[6]; + assign w_data_in_0[7] = (bw[7] == 1'b1) ? di[7] : + r_data_out_0_bram[7]; + assign w_data_in_0[8] = (bw[8] == 1'b1) ? di[8] : + r_data_out_0_bram[8]; + assign w_data_in_0[9] = (bw[9] == 1'b1) ? di[9] : + r_data_out_0_bram[9]; + assign w_data_in_0[10] = (bw[10] == 1'b1) ? di[10] : + r_data_out_0_bram[10]; + assign w_data_in_0[11] = (bw[11] == 1'b1) ? di[11] : + r_data_out_0_bram[11]; + assign w_data_in_0[12] = (bw[12] == 1'b1) ? di[12] : + r_data_out_0_bram[12]; + assign w_data_in_0[13] = (bw[13] == 1'b1) ? di[13] : + r_data_out_0_bram[13]; + assign w_data_in_0[14] = (bw[14] == 1'b1) ? di[14] : + r_data_out_0_bram[14]; + assign w_data_in_0[15] = (bw[15] == 1'b1) ? di[15] : + r_data_out_0_bram[15]; + assign w_data_in_0[16:35] = {20{1'b0}}; + + assign r_data_out_1_d = r_data_out_1_bram; + + + + RAMB16_S36_S36 + #(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only + bram0a( + .CLKA(clk2x), + .CLKB(clk2x), + .SSRA(reset_q), + .SSRB(reset_q), + .ADDRA(b0addra), + .ADDRB(b0addrb), + .DIA(w_data_in_0[0:31]), + .DIB({32{1'b0}}), + .DOA(r_data_out_0_bram[0:31]), + .DOB(r_data_out_1_bram[0:31]), + .DOPA(r_data_out_0_bram[32:35]), + .DOPB(r_data_out_1_bram[32:35]), + .DIPA(w_data_in_0[32:35]), + .DIPB(4'b0000), + .ENA(1'b1), + .ENB(1'b1), + .WEA(wea), + .WEB(web) + ); + + assign dout = r_data_out_1_fq[0:15]; + + assign func_scan_out = func_scan_in; + assign time_scan_out = time_scan_in; + assign abst_scan_out = abst_scan_in; + assign repr_scan_out = repr_scan_in; + + assign bo_pc_failout = 1'b0; + assign bo_pc_diagloop = 1'b0; + + assign unused = |{vdd, vcs, gnd, nclk, lcb_d_mode_dc, lcb_clkoff_dc_b, lcb_mpw1_dc_b, lcb_mpw2_dc_b, + lcb_delay_lclkr_dc, ccflush_dc, scan_dis_dc_b, scan_diag_dc, lcb_sg_0, lcb_sl_thold_0_b, + lcb_time_sl_thold_0, lcb_abst_sl_thold_0, lcb_ary_nsl_thold_0, lcb_repr_sl_thold_0, + abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, wr_abst_act, abist_rd0_adr, rd0_abst_act, + tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp, + lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, + pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, + tri_lcb_act_dis_dc, rd_act, r_data_out_0_bram[16:35], r_data_out_1_bram[16:35], r_data_out_1_fq[16:35]}; +endmodule diff --git a/dev/verilog/trilib/tri_128x34_4w_1r1w.v b/dev/verilog/trilib/tri_128x34_4w_1r1w.v new file mode 100755 index 0000000..dfd3d82 --- /dev/null +++ b/dev/verilog/trilib/tri_128x34_4w_1r1w.v @@ -0,0 +1,324 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILENAME : tri_128x34_4w_1r1w.v +// *! DESCRIPTION : 128 entry x 34 bit x 4 way array, +// *! 1 read & 1 write port +// *! +// *!**************************************************************** + +`include "tri_a2o.vh" + +module tri_128x34_4w_1r1w( + gnd, + vdd, + vcs, + nclk, + rd_act, + wr_act, + sg_0, + abst_sl_thold_0, + ary_nsl_thold_0, + time_sl_thold_0, + repr_sl_thold_0, + func_sl_thold_0_b, + func_force, + clkoff_dc_b, + ccflush_dc, + scan_dis_dc_b, + scan_diag_dc, + d_mode_dc, + mpw1_dc_b, + mpw2_dc_b, + delay_lclkr_dc, + wr_abst_act, + rd0_abst_act, + abist_di, + abist_bw_odd, + abist_bw_even, + abist_wr_adr, + abist_rd0_adr, + tc_lbist_ary_wrt_thru_dc, + abist_ena_1, + abist_g8t_rd0_comp_ena, + abist_raw_dc_b, + obs0_abist_cmp, + abst_scan_in, + time_scan_in, + repr_scan_in, + func_scan_in, + abst_scan_out, + time_scan_out, + repr_scan_out, + func_scan_out, + lcb_bolt_sl_thold_0, + pc_bo_enable_2, + pc_bo_reset, + pc_bo_unload, + pc_bo_repair, + pc_bo_shdata, + pc_bo_select, + bo_pc_failout, + bo_pc_diagloop, + tri_lcb_mpw1_dc_b, + tri_lcb_mpw2_dc_b, + tri_lcb_delay_lclkr_dc, + tri_lcb_clkoff_dc_b, + tri_lcb_act_dis_dc, + wr_way, + wr_addr, + data_in, + rd_addr, + data_out +); + parameter addressable_ports = 128; // number of addressable register in this array + parameter addressbus_width = 7; // width of the bus to address all ports (2^addressbus_width >= addressable_ports) + parameter port_bitwidth = 34; // bitwidth of ports + parameter ways = 4; // number of ways + + // POWER PINS + inout gnd; + inout vdd; + (* analysis_not_referenced="true" *) + inout vcs; + // CLOCK and CLOCKCONTROL ports + input [0:`NCLK_WIDTH-1] nclk; + input rd_act; + input wr_act; + input sg_0; + input abst_sl_thold_0; + input ary_nsl_thold_0; + input time_sl_thold_0; + input repr_sl_thold_0; + input func_sl_thold_0_b; + input func_force; + input clkoff_dc_b; + input ccflush_dc; + input scan_dis_dc_b; + input scan_diag_dc; + input d_mode_dc; + input [0:4] mpw1_dc_b; + input mpw2_dc_b; + input [0:4] delay_lclkr_dc; + // ABIST + input wr_abst_act; + input rd0_abst_act; + input [0:3] abist_di; + input abist_bw_odd; + input abist_bw_even; + input [0:addressbus_width-1] abist_wr_adr; + input [0:addressbus_width-1] abist_rd0_adr; + input tc_lbist_ary_wrt_thru_dc; + input abist_ena_1; + input abist_g8t_rd0_comp_ena; + input abist_raw_dc_b; + input [0:3] obs0_abist_cmp; + // Scan + input [0:1] abst_scan_in; + input time_scan_in; + input repr_scan_in; + input func_scan_in; + output [0:1] abst_scan_out; + output time_scan_out; + output repr_scan_out; + output func_scan_out; + // BOLT-ON + input lcb_bolt_sl_thold_0; + input pc_bo_enable_2; // general bolt-on enable + input pc_bo_reset; // reset + input pc_bo_unload; // unload sticky bits + input pc_bo_repair; // execute sticky bit decode + input pc_bo_shdata; // shift data for timing write and diag loop + input [0:1] pc_bo_select; // select for mask and hier writes + output [0:1] bo_pc_failout; // fail/no-fix reg + output [0:1] bo_pc_diagloop; + input tri_lcb_mpw1_dc_b; + input tri_lcb_mpw2_dc_b; + input tri_lcb_delay_lclkr_dc; + input tri_lcb_clkoff_dc_b; + input tri_lcb_act_dis_dc; + // Write Ports + input [0:ways-1] wr_way; + input [0:addressbus_width-1] wr_addr; + input [0:port_bitwidth*ways-1] data_in; + // Read Ports + input [0:addressbus_width-1] rd_addr; + output [0:port_bitwidth*ways-1] data_out; + + // tri_128x34_4w_1r1w + + parameter ramb_base_width = 36; + parameter ramb_base_addr = 9; + parameter ramb_width_mult = (port_bitwidth - 1)/ramb_base_width + 1; // # of RAMB's per way + + + // Configuration Statement for NCsim + //for all:RAMB16_S36_S36 use entity unisim.RAMB16_S36_S36; + + localparam rd_act_offset = 0; + localparam data_out_offset = rd_act_offset + 1; + localparam scan_right = data_out_offset + port_bitwidth*ways - 1; + + wire [0:(ramb_base_width*ramb_width_mult-1)] ramb_data_in[0:ways-1]; + wire [0:(ramb_base_width*ramb_width_mult-1)] ramb_data_out[0:ways-1]; + wire [0:ramb_base_addr-1] ramb_rd_addr; + wire [0:ramb_base_addr-1] ramb_wr_addr; + + wire rd_act_l2; + wire [0:port_bitwidth*ways-1] data_out_d; + wire [0:port_bitwidth*ways-1] data_out_l2; + + wire tidn; + (* analysis_not_referenced="true" *) + wire unused; + wire [31:0] dob; + wire [3:0] dopb; + wire [0:scan_right] func_sov; + + generate + begin + assign tidn = 1'b0; + + if (addressbus_width < ramb_base_addr) + begin + assign ramb_rd_addr[0:(ramb_base_addr - addressbus_width - 1)] = {(ramb_base_addr-addressbus_width){1'b0}}; + assign ramb_rd_addr[ramb_base_addr - addressbus_width:ramb_base_addr - 1] = rd_addr; + + assign ramb_wr_addr[0:(ramb_base_addr - addressbus_width - 1)] = {(ramb_base_addr-addressbus_width){1'b0}}; + assign ramb_wr_addr[ramb_base_addr - addressbus_width:ramb_base_addr - 1] = wr_addr; + end + if (addressbus_width >= ramb_base_addr) + begin + assign ramb_rd_addr = rd_addr[addressbus_width - ramb_base_addr:addressbus_width - 1]; + assign ramb_wr_addr = wr_addr[addressbus_width - ramb_base_addr:addressbus_width - 1]; + end + + genvar w; + for (w = 0; w < ways; w = w + 1) + begin : dw + genvar i; + for (i = 0; i < (ramb_base_width * ramb_width_mult); i = i + 1) + begin : din + if (i < port_bitwidth) + begin + assign ramb_data_in[w][i] = data_in[w * port_bitwidth + i]; + end + if (i >= port_bitwidth) + begin + assign ramb_data_in[w][i] = 1'b0; + end + end + end + + //genvar w; + for (w = 0; w < ways; w = w + 1) + begin : aw + genvar x; + for (x = 0; x < ramb_width_mult; x = x + 1) + begin : ax + + RAMB16_S36_S36 + #(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only + arr( + .DOA(ramb_data_out[w][x * ramb_base_width:x * ramb_base_width + 31]), + .DOB(dob), + .DOPA(ramb_data_out[w][x * ramb_base_width + 32:x * ramb_base_width + 35]), + .DOPB(dopb), + .ADDRA(ramb_rd_addr), + .ADDRB(ramb_wr_addr), + .CLKA(nclk[0]), + .CLKB(nclk[0]), + .DIA(ramb_data_in[w][x * ramb_base_width:x * ramb_base_width + 31]), + .DIB(ramb_data_in[w][x * ramb_base_width:x * ramb_base_width + 31]), + .DIPA(ramb_data_in[w][x * ramb_base_width + 32:x * ramb_base_width + 35]), + .DIPB(ramb_data_in[w][x * ramb_base_width + 32:x * ramb_base_width + 35]), + .ENA(rd_act), + .ENB(wr_act), + .SSRA(nclk[1]), + .SSRB(nclk[1]), + .WEA(tidn), + .WEB(wr_way[w]) + ); + end //ax + assign data_out_d[w * port_bitwidth:((w + 1) * port_bitwidth) - 1] = ramb_data_out[w][0:port_bitwidth - 1]; + end //aw + end + endgenerate + + assign data_out = data_out_l2; + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(0)) rd_act_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(1'b1), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_force), + .delay_lclkr(delay_lclkr_dc[0]), + .mpw1_b(mpw1_dc_b[0]), + .mpw2_b(mpw2_dc_b), + .d_mode(d_mode_dc), + .scin(1'b0), + .scout(func_sov[rd_act_offset]), + .din(rd_act), + .dout(rd_act_l2) + ); + + tri_rlmreg_p #(.WIDTH(port_bitwidth*ways), .INIT(0), .NEEDS_SRESET(0)) data_out_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rd_act_l2), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_force), + .delay_lclkr(delay_lclkr_dc[0]), + .mpw1_b(mpw1_dc_b[0]), + .mpw2_b(mpw2_dc_b), + .d_mode(d_mode_dc), + .scin({port_bitwidth*ways{1'b0}}), + .scout(func_sov[data_out_offset:data_out_offset + (port_bitwidth*ways) - 1]), + .din(data_out_d), + .dout(data_out_l2) + ); + + assign abst_scan_out = {tidn, tidn}; + assign time_scan_out = tidn; + assign repr_scan_out = tidn; + assign func_scan_out = tidn; + + assign bo_pc_failout = {tidn, tidn}; + assign bo_pc_diagloop = {tidn, tidn}; + + assign unused = | ({nclk[2:`NCLK_WIDTH-1], sg_0, abst_sl_thold_0, ary_nsl_thold_0, time_sl_thold_0, repr_sl_thold_0, clkoff_dc_b, ccflush_dc, scan_dis_dc_b, scan_diag_dc, d_mode_dc, mpw1_dc_b, mpw2_dc_b, delay_lclkr_dc, wr_abst_act, rd0_abst_act, abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, abist_rd0_adr, tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp, abst_scan_in, time_scan_in, repr_scan_in, func_scan_in, lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, tri_lcb_act_dis_dc, dob, dopb, func_sov, ramb_data_out[0][34:35], ramb_data_out[1][34:35], ramb_data_out[2][34:35], ramb_data_out[3][34:35]}); + +endmodule diff --git a/dev/verilog/trilib/tri_144x78_2r4w.v b/dev/verilog/trilib/tri_144x78_2r4w.v new file mode 100755 index 0000000..ef0660e --- /dev/null +++ b/dev/verilog/trilib/tri_144x78_2r4w.v @@ -0,0 +1,637 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ps / 1 ps + +//***************************************************************************** +// Description: Tri-Lam Array Wrapper +// +//***************************************************************************** + +`include "tri_a2o.vh" + +module tri_144x78_2r4w( + // Inputs + // Power + inout vdd, + inout gnd, + // Clock & Scan + input [0:`NCLK_WIDTH-1] nclk, + + //------------------------------------------------------------------- + // Pervasive + //------------------------------------------------------------------- + input delay_lclkr_dc, + input mpw1_dc_b, + input mpw2_dc_b, + input func_sl_force, + input func_sl_thold_0_b, + input func_slp_sl_force, + input func_slp_sl_thold_0_b, + input sg_0, + input scan_in, + output scan_out, + + //------------------------------------------------------------------- + // Read Port + //------------------------------------------------------------------- + input r_late_en_1, + input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r_addr_in_1, + output [64-`GPR_WIDTH:77] r_data_out_1, + input r_late_en_2, + input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r_addr_in_2, + output [64-`GPR_WIDTH:77] r_data_out_2, + + //------------------------------------------------------------------- + // Write Port + //------------------------------------------------------------------- + input w_late_en_1, + input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w_addr_in_1, + input [64-`GPR_WIDTH:77] w_data_in_1, + input w_late_en_2, + input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w_addr_in_2, + input [64-`GPR_WIDTH:77] w_data_in_2, + input w_late_en_3, + input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w_addr_in_3, + input [64-`GPR_WIDTH:77] w_data_in_3, + input w_late_en_4, + input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w_addr_in_4, + input [64-`GPR_WIDTH:77] w_data_in_4 +); + + // Configuration Statement for NCsim + //for all:RAM64X1D use entity unisim.RAM64X1D; + + parameter tiup = 1'b1; + parameter tidn = 1'b0; + + //------------------------------------------------------------------- + // Signals + //------------------------------------------------------------------- + //reg write_en; + //reg [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] write_addr; + //reg [64-`GPR_WIDTH:77] write_data; + wire write_en; + wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] write_addr; + wire [64-`GPR_WIDTH:77] write_data; + + wire [0:(`GPR_POOL*`THREADS-1)/64] write_en_arr; + wire [0:5] write_addr_arr; + wire [0:1] wr_mux_ctrl; + + //------------------------------------------------------------------- + // Latch Signals + //------------------------------------------------------------------- + wire w1e_q; + wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w1a_q; + wire [64-`GPR_WIDTH:77] w1d_q; + wire w2e_q; + wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w2a_q; + wire [64-`GPR_WIDTH:77] w2d_q; + wire w3e_q; + wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w3a_q; + wire [64-`GPR_WIDTH:77] w3d_q; + wire w4e_q; + wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w4a_q; + wire [64-`GPR_WIDTH:77] w4d_q; + wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r1a_q; + wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r2a_q; + wire [0:5] read1_addr_arr; + wire [0:5] read2_addr_arr; + wire [0:(`GPR_POOL*`THREADS-1)/64] read1_en_arr; + wire [0:(`GPR_POOL*`THREADS-1)/64] read2_en_arr; + reg [64-`GPR_WIDTH:77] read1_data; + reg [64-`GPR_WIDTH:77] read2_data; + wire [64-`GPR_WIDTH:77] r1d_array[0:(`GPR_POOL*`THREADS-1)/64]; + wire [64-`GPR_WIDTH:77] r2d_array[0:(`GPR_POOL*`THREADS-1)/64]; + wire [64-`GPR_WIDTH:77] r1d_d; + wire [64-`GPR_WIDTH:77] r2d_d; + wire [64-`GPR_WIDTH:77] r1d_q; + wire [64-`GPR_WIDTH:77] r2d_q; + + (* analysis_not_referenced="true" *) + wire unused; + wire [64-`GPR_WIDTH:77] unused_port; + wire [64-`GPR_WIDTH:77] unused_port2; + + //------------------------------------------------------------------- + // Scanchain + //------------------------------------------------------------------- + parameter w1e_offset = 0; + parameter w1a_offset = w1e_offset + 1; + parameter w1d_offset = w1a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC; + parameter w2e_offset = w1d_offset + (`GPR_WIDTH+14); + parameter w2a_offset = w2e_offset + 1; + parameter w2d_offset = w2a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC; + parameter w3e_offset = w2d_offset + (`GPR_WIDTH+14); + parameter w3a_offset = w3e_offset + 1; + parameter w3d_offset = w3a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC; + parameter w4e_offset = w3d_offset + (`GPR_WIDTH+14); + parameter w4a_offset = w4e_offset + 1; + parameter w4d_offset = w4a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC; + parameter r1a_offset = w4d_offset + (`GPR_WIDTH+14); + parameter r2a_offset = r1a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC; + parameter r1d_offset = r2a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC; + parameter r2d_offset = r1d_offset + (`GPR_WIDTH+14); + parameter scan_right = r2d_offset + (`GPR_WIDTH+14); + wire [0:scan_right-1] siv; + wire [0:scan_right-1] sov; + + generate + begin + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // Read Control + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // BYPASS + + assign r1d_d = read1_data; + + assign r2d_d = read2_data; + + assign r_data_out_1 = r1d_q; + assign r_data_out_2 = r2d_q; + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // Write Control + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + assign wr_mux_ctrl = {nclk[0], nclk[2]}; + + //wtf moved these here to try to get them to work in icarus - they seem to now + assign write_en = ((wr_mux_ctrl == 2'b00) ? w_late_en_1 : + (wr_mux_ctrl == 2'b01) ? w_late_en_2 : + (wr_mux_ctrl == 2'b10) ? w_late_en_3 : + w_late_en_4); + + assign write_addr = ((wr_mux_ctrl == 2'b00) ? w_addr_in_1 : + (wr_mux_ctrl == 2'b01) ? w_addr_in_2 : + (wr_mux_ctrl == 2'b10) ? w_addr_in_3 : + w_addr_in_4); + + assign write_data = ((wr_mux_ctrl == 2'b00) ? w_data_in_1 : + (wr_mux_ctrl == 2'b01) ? w_data_in_2 : + (wr_mux_ctrl == 2'b10) ? w_data_in_3 : + w_data_in_4); + + + //always @ ( * ) + //begin + //write_addr = #10 ((wr_mux_ctrl == 2'b00) ? w_addr_in_1 : + // (wr_mux_ctrl == 2'b01) ? w_addr_in_2 : + // (wr_mux_ctrl == 2'b10) ? w_addr_in_3 : + // w_addr_in_4); + + //write_en = #10 ((wr_mux_ctrl == 2'b00) ? w_late_en_1 : + // (wr_mux_ctrl == 2'b01) ? w_late_en_2 : + // (wr_mux_ctrl == 2'b10) ? w_late_en_3 : + // w_late_en_4); + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // Depth Control + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + + //write_data = #10 ((wr_mux_ctrl == 2'b00) ? w_data_in_1 : + // (wr_mux_ctrl == 2'b01) ? w_data_in_2 : + // (wr_mux_ctrl == 2'b10) ? w_data_in_3 : + // w_data_in_4); + //end + + if (((`GPR_POOL*`THREADS - 1)/64) == 0) + begin : depth1 + if (`GPR_POOL_ENC+`THREADS_POOL_ENC < 6) + begin + assign write_addr_arr[0:(6 - `GPR_POOL_ENC+`THREADS_POOL_ENC) - 1] = {6-`GPR_POOL_ENC+`THREADS_POOL_ENC{1'b0}}; + assign read1_addr_arr[0:(6 - `GPR_POOL_ENC+`THREADS_POOL_ENC) - 1] = {6-`GPR_POOL_ENC+`THREADS_POOL_ENC{1'b0}}; + assign read2_addr_arr[0:(6 - `GPR_POOL_ENC+`THREADS_POOL_ENC) - 1] = {6-`GPR_POOL_ENC+`THREADS_POOL_ENC{1'b0}}; + end + + assign write_addr_arr[6 - `GPR_POOL_ENC+`THREADS_POOL_ENC:5] = write_addr; + assign read1_addr_arr[6 - `GPR_POOL_ENC+`THREADS_POOL_ENC:5] = r1a_q; + assign read2_addr_arr[6 - `GPR_POOL_ENC+`THREADS_POOL_ENC:5] = r2a_q; + assign write_en_arr[0] = write_en; + assign read1_en_arr[0] = 1'b1; + assign read2_en_arr[0] = 1'b1; + end + + if (((`GPR_POOL*`THREADS - 1)/64) != 0) + begin : depthMulti + assign write_addr_arr = write_addr[`GPR_POOL_ENC+`THREADS_POOL_ENC - 6:`GPR_POOL_ENC+`THREADS_POOL_ENC - 1]; + assign read1_addr_arr = r1a_q[`GPR_POOL_ENC+`THREADS_POOL_ENC - 6:`GPR_POOL_ENC+`THREADS_POOL_ENC - 1]; + assign read2_addr_arr = r2a_q[`GPR_POOL_ENC+`THREADS_POOL_ENC - 6:`GPR_POOL_ENC+`THREADS_POOL_ENC - 1]; + + genvar wen; + for (wen = 0; wen <= ((`GPR_POOL*`THREADS - 1)/64); wen = wen + 1) + begin : wrenGen + wire wen_match = wen; + assign write_en_arr[wen] = write_en & (write_addr[0:(`GPR_POOL_ENC+`THREADS_POOL_ENC - 6) - 1] == wen_match); + assign read1_en_arr[wen] = r1a_q[0:(`GPR_POOL_ENC+`THREADS_POOL_ENC - 6) - 1] == wen_match; + assign read2_en_arr[wen] = r2a_q[0:(`GPR_POOL_ENC+`THREADS_POOL_ENC - 6) - 1] == wen_match; + end + end + + always @( * ) + begin: rdDataMux + reg [64-`GPR_WIDTH:77] rd1_data; + reg [64-`GPR_WIDTH:77] rd2_data; + //(* analysis_not_referenced="true" *) + integer rdArr; + rd1_data = {`GPR_WIDTH+14{1'b0}}; + rd2_data = {`GPR_WIDTH+14{1'b0}}; + + for (rdArr = 0; rdArr <= ((`GPR_POOL*`THREADS - 1)/64); rdArr = rdArr + 1) + begin + rd1_data = (r1d_array[rdArr] & {`GPR_WIDTH+14{read1_en_arr[rdArr]}}) | rd1_data; + rd2_data = (r2d_array[rdArr] & {`GPR_WIDTH+14{read2_en_arr[rdArr]}}) | rd2_data; + end + read1_data = rd1_data; + read2_data = rd2_data; + end + + genvar depth; + for (depth = 0; depth <= ((`GPR_POOL*`THREADS - 1)/64); depth = depth + 1) + begin : depth_loop + genvar i; + for (i = 64 - `GPR_WIDTH; i < 78; i = i + 1) + begin : r1 + RAM64X1D #(.INIT(64'h0000000000000000)) RAM64X1D_1( + .SPO(unused_port[i]), + .DPO(r1d_array[depth][i]), // Port A 1-bit data output + + .A0(write_addr_arr[5]), // Port A - Write Address (A0-A5) + .A1(write_addr_arr[4]), + .A2(write_addr_arr[3]), + .A3(write_addr_arr[2]), + .A4(write_addr_arr[1]), + .A5(write_addr_arr[0]), + + //.A(write_addr_arr), + .D(write_data[i]), // Port A 1-bit data input + + .DPRA0(read1_addr_arr[5]), // Port B - Read Address (DPRA0-DPRA5) + .DPRA1(read1_addr_arr[4]), + .DPRA2(read1_addr_arr[3]), + .DPRA3(read1_addr_arr[2]), + .DPRA4(read1_addr_arr[1]), + .DPRA5(read1_addr_arr[0]), + + //.DPRA(read1_addr_arr), + .WCLK(nclk[3]), // Port A write clock input : clk4x + .WE(write_en_arr[depth]) // Port A write enable input + ); + end + + //genvar i; + for (i = 64 - `GPR_WIDTH; i < 78; i = i + 1) + begin : r2 + RAM64X1D #(.INIT(64'h0000000000000000)) RAM64X1D_2( + .SPO(unused_port2[i]), + .DPO(r2d_array[depth][i]), // Port A 1-bit data output + + .A0(write_addr_arr[5]), // Port A - Write Address (A0-A5) + .A1(write_addr_arr[4]), + .A2(write_addr_arr[3]), + .A3(write_addr_arr[2]), + .A4(write_addr_arr[1]), + .A5(write_addr_arr[0]), + + //.A(write_addr_arr), + .D(write_data[i]), // Port A 1-bit data input + + .DPRA0(read2_addr_arr[5]), // Port B - Read Address (DPRA0-DPRA5) + .DPRA1(read2_addr_arr[4]), + .DPRA2(read2_addr_arr[3]), + .DPRA3(read2_addr_arr[2]), + .DPRA4(read2_addr_arr[1]), + .DPRA5(read2_addr_arr[0]), + + //.DPRA(read2_addr_arr), + .WCLK(nclk[3]), // Port A write clock input : clk4x + .WE(write_en_arr[depth]) // Port A write enable input + ); + end + end + end + endgenerate + + //---------------------------------------------------------------------------------------------------------------------------------------- + // Latches + //---------------------------------------------------------------------------------------------------------------------------------------- + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) w1e_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .d_mode(1'b0), + .sg(sg_0), + .scin(siv[w1e_offset]), + .scout(sov[w1e_offset]), + .din(w_late_en_1), + .dout(w1e_q) + ); + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) w1a_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .d_mode(1'b0), + .sg(sg_0), + .scin(siv[w1a_offset:w1a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]), + .scout(sov[w1a_offset:w1a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]), + .din(w_addr_in_1), + .dout(w1a_q) + ); + + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+14), .INIT(0), .NEEDS_SRESET(1)) w1d_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .d_mode(1'b0), + .sg(sg_0), + .scin(siv[w1d_offset:w1d_offset + `GPR_WIDTH+14 - 1]), + .scout(sov[w1d_offset:w1d_offset + `GPR_WIDTH+14 - 1]), + .din(w_data_in_1[64 - `GPR_WIDTH:77]), + .dout(w1d_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) w2e_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .d_mode(1'b0), + .sg(sg_0), + .scin(siv[w2e_offset]), + .scout(sov[w2e_offset]), + .din(w_late_en_2), + .dout(w2e_q) + ); + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) w2a_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .d_mode(1'b0), + .sg(sg_0), + .scin(siv[w2a_offset:w2a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]), + .scout(sov[w2a_offset:w2a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]), + .din(w_addr_in_2), + .dout(w2a_q) + ); + + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+14), .INIT(0), .NEEDS_SRESET(1)) w2d_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .d_mode(1'b0), + .sg(sg_0), + .scin(siv[w2d_offset:w2d_offset + `GPR_WIDTH+14 - 1]), + .scout(sov[w2d_offset:w2d_offset + `GPR_WIDTH+14 - 1]), + .din(w_data_in_2[64 - `GPR_WIDTH:77]), + .dout(w2d_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) w3e_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .d_mode(1'b0), + .sg(sg_0), + .scin(siv[w3e_offset]), + .scout(sov[w3e_offset]), + .din(w_late_en_3), + .dout(w3e_q) + ); + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) w3a_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .d_mode(1'b0), + .sg(sg_0), + .scin(siv[w3a_offset:w3a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]), + .scout(sov[w3a_offset:w3a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]), + .din(w_addr_in_3), + .dout(w3a_q) + ); + + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+14), .INIT(0), .NEEDS_SRESET(1)) w3d_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .d_mode(1'b0), + .sg(sg_0), + .scin(siv[w3d_offset:w3d_offset + `GPR_WIDTH+14 - 1]), + .scout(sov[w3d_offset:w3d_offset + `GPR_WIDTH+14 - 1]), + .din(w_data_in_3[64 - `GPR_WIDTH:77]), + .dout(w3d_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) w4e_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .d_mode(1'b0), + .sg(sg_0), + .scin(siv[w4e_offset]), + .scout(sov[w4e_offset]), + .din(w_late_en_4), + .dout(w4e_q) + ); + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) w4a_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .d_mode(1'b0), + .sg(sg_0), + .scin(siv[w4a_offset:w4a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]), + .scout(sov[w4a_offset:w4a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]), + .din(w_addr_in_4), + .dout(w4a_q) + ); + + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+14), .INIT(0), .NEEDS_SRESET(1)) w4d_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .d_mode(1'b0), + .sg(sg_0), + .scin(siv[w4d_offset:w4d_offset + `GPR_WIDTH+14 - 1]), + .scout(sov[w4d_offset:w4d_offset + `GPR_WIDTH+14 - 1]), + .din(w_data_in_4[64 - `GPR_WIDTH:77]), + .dout(w4d_q) + ); + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) r1a_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .d_mode(1'b0), + .sg(sg_0), + .scin(siv[r1a_offset:r1a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]), + .scout(sov[r1a_offset:r1a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]), + .din(r_addr_in_1), + .dout(r1a_q) + ); + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) r2a_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .d_mode(1'b0), + .sg(sg_0), + .scin(siv[r2a_offset:r2a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]), + .scout(sov[r2a_offset:r2a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]), + .din(r_addr_in_2), + .dout(r2a_q) + ); + + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+14), .INIT(0), .NEEDS_SRESET(1)) r1d_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .d_mode(1'b0), + .sg(sg_0), + .scin(siv[r1d_offset:r1d_offset + `GPR_WIDTH+14 - 1]), + .scout(sov[r1d_offset:r1d_offset + `GPR_WIDTH+14 - 1]), + .din(r1d_d), + .dout(r1d_q) + ); + + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+14), .INIT(0), .NEEDS_SRESET(1)) r2d_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .d_mode(1'b0), + .sg(sg_0), + .scin(siv[r2d_offset:r2d_offset + `GPR_WIDTH+14 - 1]), + .scout(sov[r2d_offset:r2d_offset + `GPR_WIDTH+14 - 1]), + .din(r2d_d), + .dout(r2d_q) + ); + + assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in}; + assign scan_out = sov[0]; + + assign unused = | {unused_port, unused_port2, func_slp_sl_force, func_slp_sl_thold_0_b}; +endmodule diff --git a/dev/verilog/trilib/tri_256x144_8w_1r1w.v b/dev/verilog/trilib/tri_256x144_8w_1r1w.v new file mode 100755 index 0000000..983d987 --- /dev/null +++ b/dev/verilog/trilib/tri_256x144_8w_1r1w.v @@ -0,0 +1,513 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILENAME : tri_256x144_8w_1r1w.v +// *! DESCRIPTION : 256 Entry x 144 bit x 8 way array, 9 bit writeable +// *! +// *!**************************************************************** + +`include "tri_a2o.vh" + +module tri_256x144_8w_1r1w( + gnd, + vdd, + vcs, + nclk, + rd_act, + wr_act, + sg_0, + abst_sl_thold_0, + ary_nsl_thold_0, + time_sl_thold_0, + repr_sl_thold_0, + func_sl_force, + func_sl_thold_0_b, + g8t_clkoff_dc_b, + ccflush_dc, + scan_dis_dc_b, + scan_diag_dc, + g8t_d_mode_dc, + g8t_mpw1_dc_b, + g8t_mpw2_dc_b, + g8t_delay_lclkr_dc, + d_mode_dc, + mpw1_dc_b, + mpw2_dc_b, + delay_lclkr_dc, + wr_abst_act, + rd0_abst_act, + abist_di, + abist_bw_odd, + abist_bw_even, + abist_wr_adr, + abist_rd0_adr, + tc_lbist_ary_wrt_thru_dc, + abist_ena_1, + abist_g8t_rd0_comp_ena, + abist_raw_dc_b, + obs0_abist_cmp, + abst_scan_in, + time_scan_in, + repr_scan_in, + func_scan_in, + abst_scan_out, + time_scan_out, + repr_scan_out, + func_scan_out, + lcb_bolt_sl_thold_0, + pc_bo_enable_2, + pc_bo_reset, + pc_bo_unload, + pc_bo_repair, + pc_bo_shdata, + pc_bo_select, + bo_pc_failout, + bo_pc_diagloop, + tri_lcb_mpw1_dc_b, + tri_lcb_mpw2_dc_b, + tri_lcb_delay_lclkr_dc, + tri_lcb_clkoff_dc_b, + tri_lcb_act_dis_dc, + wr_way, + wr_addr, + data_in0, + data_in1, + rd_addr, + data_out +); +parameter addressable_ports = 256; // number of addressable register in this array +parameter addressbus_width = 8; // width of the bus to address all ports (2^addressbus_width >= addressable_ports) +parameter port_bitwidth = 144; // bitwidth of ports (per way) +parameter bit_write_type = 9; // gives the number of bits that shares one write-enable; must divide evenly into array +parameter ways = 8; // number of ways + +// POWER PINS +inout gnd; +inout vdd; +inout vcs; + +// CLOCK and CLOCKCONTROL ports +input [0:`NCLK_WIDTH-1] nclk; +input [0:7] rd_act; +input [0:7] wr_act; +input sg_0; +input abst_sl_thold_0; +input ary_nsl_thold_0; +input time_sl_thold_0; +input repr_sl_thold_0; +input func_sl_force; +input func_sl_thold_0_b; +input g8t_clkoff_dc_b; +input ccflush_dc; +input scan_dis_dc_b; +input scan_diag_dc; +input g8t_d_mode_dc; +input [0:4] g8t_mpw1_dc_b; +input g8t_mpw2_dc_b; +input [0:4] g8t_delay_lclkr_dc; +input d_mode_dc; +input mpw1_dc_b; +input mpw2_dc_b; +input delay_lclkr_dc; + +// ABIST +input wr_abst_act; +input rd0_abst_act; +input [0:3] abist_di; +input abist_bw_odd; +input abist_bw_even; +input [0:addressbus_width-1] abist_wr_adr; +input [0:addressbus_width-1] abist_rd0_adr; +input tc_lbist_ary_wrt_thru_dc; +input abist_ena_1; +input abist_g8t_rd0_comp_ena; +input abist_raw_dc_b; +input [0:3] obs0_abist_cmp; + +// SCAN +input [0:3] abst_scan_in; +input time_scan_in; +input repr_scan_in; +input [0:3] func_scan_in; +output [0:3] abst_scan_out; +output time_scan_out; +output repr_scan_out; +output [0:3] func_scan_out; + +// BOLT-ON +input lcb_bolt_sl_thold_0; +input pc_bo_enable_2; // general bolt-on enable +input pc_bo_reset; // reset +input pc_bo_unload; // unload sticky bits +input pc_bo_repair; // execute sticky bit decode +input pc_bo_shdata; // shift data for timing write and diag loop +input [0:3] pc_bo_select; // select for mask and hier writes +output [0:3] bo_pc_failout; // fail/no-fix reg +output [0:3] bo_pc_diagloop; +input tri_lcb_mpw1_dc_b; +input tri_lcb_mpw2_dc_b; +input tri_lcb_delay_lclkr_dc; +input tri_lcb_clkoff_dc_b; +input tri_lcb_act_dis_dc; + +// FUNCTIONAL PORTS +input [0:ways-1] wr_way; +input [0:(addressbus_width-1)] wr_addr; +input [0:(port_bitwidth-1)] data_in0; +input [0:(port_bitwidth-1)] data_in1; +input [0:(addressbus_width-1)] rd_addr; +output [0:(port_bitwidth*ways-1)] data_out; + +parameter ramb_base_addr = 16; +parameter dataWidth = ((((port_bitwidth - 1)/36) + 1) * 36) - 1; +parameter numBytes = (dataWidth/9); +parameter addresswidth = addressbus_width; +parameter rd_act_offset = 0; +parameter data_out_offset = rd_act_offset + ways; +parameter scan_right = data_out_offset + (port_bitwidth*ways) - 1; + +wire [0:dataWidth] data_in0_pad; +wire [0:dataWidth] data_in1_pad; +wire [0:dataWidth] data_in_swzl[0:ways-1]; +wire [0:dataWidth] p0_data_out_pad[0:ways-1]; +wire [0:dataWidth] p1_data_out_pad[0:ways-1]; +wire [0:(dataWidth-(dataWidth)/9)-1] p0_arr_data_in[0:ways-1]; +wire [0:(dataWidth)/9] p0_arr_par_in[0:ways-1]; +wire [0:(dataWidth-(dataWidth)/9)-1] p1_arr_data_in[0:ways-1]; +wire [0:(dataWidth)/9] p1_arr_par_in[0:ways-1]; +wire [0:(dataWidth-(dataWidth)/9)-1] p0_arr_data_out[0:ways-1]; +wire [0:(dataWidth)/9] p0_arr_par_out[0:ways-1]; +wire [0:(dataWidth-(dataWidth)/9)-1] p1_arr_data_out[0:ways-1]; +wire [0:(dataWidth)/9] p1_arr_par_out[0:ways-1]; +wire [0:ramb_base_addr-1] ramb_rd_addr; +wire [0:ramb_base_addr-1] ramb_wr_addr; +wire [0:((((port_bitwidth-1)/36)+1)*4)-1] p0_wayEn[0:ways-1]; +wire [0:((((port_bitwidth-1)/36)+1)*4)-1] p1_wayEn[0:ways-1]; +wire [0:(port_bitwidth*ways-1)] p0_data_out_swzl; +wire [0:(port_bitwidth*ways-1)] p1_data_out_swzl; +wire [0:(port_bitwidth*ways-1)] data_out_fix; +wire [0:((port_bitwidth-1)/36)] cascadeoutlata; +wire [0:((port_bitwidth-1)/36)] cascadeoutlatb; +wire [0:((port_bitwidth-1)/36)] cascadeoutrega; +wire [0:((port_bitwidth-1)/36)] cascadeoutregb; +wire [0:ways-1] rd_act_d; +wire [0:ways-1] rd_act_q; +wire [0:(port_bitwidth*ways)-1] data_out_d; +wire [0:(port_bitwidth*ways)-1] data_out_b_q; + +wire [0:ways-1] my_d1clk; +wire [0:ways-1] my_d2clk; +wire [0:`NCLK_WIDTH-1] my_lclk[0:ways-1]; +wire tiup; +wire [0:scan_right] siv; +wire [0:scan_right] sov; + +(* analysis_not_referenced="true" *) +wire unused; + +generate begin + // Read/Write Port Address Generate + assign ramb_rd_addr[11:15] = 5'b0; + assign ramb_wr_addr[11:15] = 5'b0; + assign rd_act_d = rd_act; + assign tiup = 1'b1; + + genvar bb; + genvar way; + genvar b; + for (bb = 0; bb <= numBytes; bb = bb + 1) begin : swzl + for (way = 0; way < ways; way = way + 1) begin : perWay + if (way < (ways/2)) begin : fhalf + assign data_in_swzl[way][(bb * 8) + bb:(((bb * 8) + 7) + bb)] = {data_in0_pad[bb + (0 * (numBytes + 1))], data_in0_pad[bb + (1 * (numBytes + 1))], + data_in0_pad[bb + (2 * (numBytes + 1))], data_in0_pad[bb + (3 * (numBytes + 1))], + data_in0_pad[bb + (4 * (numBytes + 1))], data_in0_pad[bb + (5 * (numBytes + 1))], + data_in0_pad[bb + (6 * (numBytes + 1))], data_in0_pad[bb + (7 * (numBytes + 1))]}; + assign data_in_swzl[way][(((bb * 8) + bb) + 8)] = data_in0_pad[bb + (8 * (numBytes + 1))]; + end + if (way >= (ways/2)) begin : shalf + assign data_in_swzl[way][(bb * 8) + bb:(((bb * 8) + 7) + bb)] = {data_in1_pad[bb + (0 * (numBytes + 1))], data_in1_pad[bb + (1 * (numBytes + 1))], + data_in1_pad[bb + (2 * (numBytes + 1))], data_in1_pad[bb + (3 * (numBytes + 1))], + data_in1_pad[bb + (4 * (numBytes + 1))], data_in1_pad[bb + (5 * (numBytes + 1))], + data_in1_pad[bb + (6 * (numBytes + 1))], data_in1_pad[bb + (7 * (numBytes + 1))]}; + assign data_in_swzl[way][(((bb * 8) + bb) + 8)] = data_in1_pad[bb + (8 * (numBytes + 1))]; + end + end + end + + genvar t; + for (t = 0; t < 11; t = t + 1) begin : rambAddrCalc + if (t < (11-addresswidth)) begin + assign ramb_rd_addr[t] = 1'b0; + assign ramb_wr_addr[t] = 1'b0; + end + if (t >= (11-addresswidth)) begin + assign ramb_rd_addr[t] = rd_addr[t - (11 - addresswidth)]; + assign ramb_wr_addr[t] = wr_addr[t - (11 - addresswidth)]; + end + end + + for (b = 0; b <= dataWidth; b = b + 1) begin : dFixUp + if (b < port_bitwidth) begin + assign data_in0_pad[b] = data_in0[b]; + assign data_in1_pad[b] = data_in1[b]; + end + if (b >= port_bitwidth) begin + assign data_in0_pad[b] = 1'b0; + assign data_in1_pad[b] = 1'b0; + end + end + + //genvar way; + for (way = 0; way < ways; way = way + 1) begin : NwayDatInFix + //genvar bb; + for (bb = 0; bb <= (dataWidth)/9; bb = bb + 1) begin : dFixUp + assign p0_arr_data_in[way][bb * 8:(bb * 8) + 7] = 8'h00; + assign p0_arr_par_in[way][bb] = 1'b0; + assign p1_arr_data_in[way][bb * 8:(bb * 8) + 7] = data_in_swzl[way][(bb * 8) + bb:(((bb * 8) + 7) + bb)]; + assign p1_arr_par_in[way][bb] = data_in_swzl[way][(((bb * 8) + bb) + 8)]; + end + end + + //genvar way; + for (way = 0; way < ways; way = way + 1) begin : NwayDatOutFix + //genvar bb; + for (bb = 0; bb <= (dataWidth)/9; bb = bb + 1) begin : dFixUp + assign p0_data_out_pad[way][(bb * 8) + bb:(((bb * 8) + 7) + bb)] = p0_arr_data_out[way][bb * 8:(bb * 8) + 7]; + assign p0_data_out_pad[way][(((bb * 8) + bb) + 8)] = p0_arr_par_out[way][bb]; + assign p1_data_out_pad[way][(bb * 8) + bb:(((bb * 8) + 7) + bb)] = p1_arr_data_out[way][bb * 8:(bb * 8) + 7]; + assign p1_data_out_pad[way][(((bb * 8) + bb) + 8)] = p1_arr_par_out[way][bb]; + end + end + + //genvar way; + for (way = 0; way < ways; way = way + 1) begin : NwayDatOut + assign p0_data_out_swzl[way * port_bitwidth:(way * port_bitwidth) + port_bitwidth - 1] = p0_data_out_pad[way][0:port_bitwidth - 1]; + assign p1_data_out_swzl[way * port_bitwidth:(way * port_bitwidth) + port_bitwidth - 1] = p1_data_out_pad[way][0:port_bitwidth - 1]; + + //genvar bb; + for (bb = 0; bb <= numBytes; bb = bb + 1) begin : swzl + assign data_out_fix[(way * port_bitwidth) + (0 * (numBytes + 1)) + bb] = p0_data_out_swzl[(way * port_bitwidth) + ((bb * 8) + bb) + 0]; + assign data_out_fix[(way * port_bitwidth) + (1 * (numBytes + 1)) + bb] = p0_data_out_swzl[(way * port_bitwidth) + ((bb * 8) + bb) + 1]; + assign data_out_fix[(way * port_bitwidth) + (2 * (numBytes + 1)) + bb] = p0_data_out_swzl[(way * port_bitwidth) + ((bb * 8) + bb) + 2]; + assign data_out_fix[(way * port_bitwidth) + (3 * (numBytes + 1)) + bb] = p0_data_out_swzl[(way * port_bitwidth) + ((bb * 8) + bb) + 3]; + assign data_out_fix[(way * port_bitwidth) + (4 * (numBytes + 1)) + bb] = p0_data_out_swzl[(way * port_bitwidth) + ((bb * 8) + bb) + 4]; + assign data_out_fix[(way * port_bitwidth) + (5 * (numBytes + 1)) + bb] = p0_data_out_swzl[(way * port_bitwidth) + ((bb * 8) + bb) + 5]; + assign data_out_fix[(way * port_bitwidth) + (6 * (numBytes + 1)) + bb] = p0_data_out_swzl[(way * port_bitwidth) + ((bb * 8) + bb) + 6]; + assign data_out_fix[(way * port_bitwidth) + (7 * (numBytes + 1)) + bb] = p0_data_out_swzl[(way * port_bitwidth) + ((bb * 8) + bb) + 7]; + assign data_out_fix[(way * port_bitwidth) + (8 * (numBytes + 1)) + bb] = p0_data_out_swzl[(way * port_bitwidth) + ((bb * 8) + bb) + 8]; + end + end + assign data_out_d = data_out_fix; + + assign data_out = ~data_out_b_q; + + //genvar way; + for (way = 0; way < ways; way = way + 1) begin : Nways + //genvar bb; + for (bb = 0; bb < ((((port_bitwidth - 1)/36) + 1) * 4); bb = bb + 1) begin : BEn + if (bb <= (port_bitwidth - 1)/9) begin + assign p0_wayEn[way][bb] = 1'b0; + assign p1_wayEn[way][bb] = wr_way[way]; + end + if (bb > (port_bitwidth - 1)/9) begin + assign p0_wayEn[way][bb] = 1'b0; + assign p1_wayEn[way][bb] = 1'b0; + end + end + + // Port A => Read Port + // Port B => Write Port + genvar arr; + for (arr = 0; arr <= ((port_bitwidth - 1)/36); arr = arr + 1) begin : Narrs + RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WRITE_WIDTH_A(36), .WRITE_WIDTH_B(36), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("READ_FIRST")) wayArr( + .CASCADEOUTLATA(cascadeoutlata[arr]), + .CASCADEOUTLATB(cascadeoutlatb[arr]), + .CASCADEOUTREGA(cascadeoutrega[arr]), + .CASCADEOUTREGB(cascadeoutregb[arr]), + .DOA(p0_arr_data_out[way][(arr * 32) + 0:(arr * 32) + 31]), + .DOB(p1_arr_data_out[way][(arr * 32) + 0:(arr * 32) + 31]), + .DOPA(p0_arr_par_out[way][(arr * 4) + 0:(arr * 4) + 3]), + .DOPB(p1_arr_par_out[way][(arr * 4) + 0:(arr * 4) + 3]), + .ADDRA(ramb_rd_addr), + .ADDRB(ramb_wr_addr), + .CASCADEINLATA(1'b0), + .CASCADEINLATB(1'b0), + .CASCADEINREGA(1'b0), + .CASCADEINREGB(1'b0), + .CLKA(nclk[0]), + .CLKB(nclk[0]), + .DIA(p0_arr_data_in[way][(arr * 32) + 0:(arr * 32) + 31]), + .DIB(p1_arr_data_in[way][(arr * 32) + 0:(arr * 32) + 31]), + .DIPA(p0_arr_par_in[way][(arr * 4) + 0:(arr * 4) + 3]), + .DIPB(p1_arr_par_in[way][(arr * 4) + 0:(arr * 4) + 3]), + .ENA(rd_act[way]), + .ENB(wr_act[way]), + .REGCEA(1'b0), + .REGCEB(1'b0), + .SSRA(nclk[1]), //sreset + .SSRB(nclk[1]), //sreset + .WEA(p0_wayEn[way][(arr * 4) + 0:(arr * 4) + 3]), + .WEB(p1_wayEn[way][(arr * 4) + 0:(arr * 4) + 3]) + ); + end + end //Nways + + assign abst_scan_out = 4'b0; + assign time_scan_out = 1'b0; + assign repr_scan_out = 1'b0; + assign bo_pc_failout = 4'h0; + assign bo_pc_diagloop = 4'h0; +end +endgenerate + +assign unused = |({ + cascadeoutlata , + cascadeoutlatb , + cascadeoutrega , + cascadeoutregb , + nclk[0:`NCLK_WIDTH-1] , + gnd , + vdd , + vcs , + sg_0 , + ary_nsl_thold_0 , + abst_sl_thold_0 , + time_sl_thold_0 , + repr_sl_thold_0 , + g8t_clkoff_dc_b, + ccflush_dc, + scan_dis_dc_b, + scan_diag_dc, + g8t_d_mode_dc, + g8t_mpw1_dc_b, + g8t_mpw2_dc_b, + g8t_delay_lclkr_dc, + wr_abst_act, + rd0_abst_act, + abist_di, + abist_bw_odd, + abist_bw_even, + abist_wr_adr, + abist_rd0_adr, + tc_lbist_ary_wrt_thru_dc, + abist_ena_1, + abist_g8t_rd0_comp_ena, + abist_raw_dc_b, + obs0_abist_cmp, + abst_scan_in, + time_scan_in, + repr_scan_in, + func_scan_in, + lcb_bolt_sl_thold_0, + pc_bo_enable_2, + pc_bo_reset, + pc_bo_unload, + pc_bo_repair, + pc_bo_shdata, + pc_bo_select, + tri_lcb_mpw1_dc_b, + tri_lcb_mpw2_dc_b, + tri_lcb_delay_lclkr_dc, + tri_lcb_clkoff_dc_b, + tri_lcb_act_dis_dc, + p1_data_out_swzl}); + +// ############################################################### +// ## Latches +// ############################################################### +tri_rlmreg_p #(.WIDTH(ways), .INIT(0), .NEEDS_SRESET(1)) rd_act_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rd_act_offset:rd_act_offset + ways - 1]), + .scout(sov[rd_act_offset:rd_act_offset + ways - 1]), + .din(rd_act_d), + .dout(rd_act_q) +); + +generate begin : wayReg + genvar way; + for (way=0; way= addressable_ports) +parameter port_bitwidth = 70; // bitwidth of ports +parameter ways = 2; // number of ways + +// POWER PINS +inout gnd; +inout vdd; +inout vcs; +// CLOCK and CLOCKCONTROL ports +input [0:`NCLK_WIDTH-1] nclk; +input [0:1] rd_act; +input [0:1] wr_act; +input sg_0; +input abst_sl_thold_0; +input ary_nsl_thold_0; +input time_sl_thold_0; +input repr_sl_thold_0; +input func_sl_force; +input func_sl_thold_0_b; +input g8t_clkoff_dc_b; +input ccflush_dc; +input scan_dis_dc_b; +input scan_diag_dc; +input g8t_d_mode_dc; +input [0:4] g8t_mpw1_dc_b; +input g8t_mpw2_dc_b; +input [0:4] g8t_delay_lclkr_dc; +input d_mode_dc; +input mpw1_dc_b; +input mpw2_dc_b; +input delay_lclkr_dc; + +// ABIST +input wr_abst_act; +input rd0_abst_act; +input [0:3] abist_di; +input abist_bw_odd; +input abist_bw_even; +input [0:addressbus_width-1] abist_wr_adr; +input [0:addressbus_width-1] abist_rd0_adr; +input tc_lbist_ary_wrt_thru_dc; +input abist_ena_1; +input abist_g8t_rd0_comp_ena; +input abist_raw_dc_b; +input [0:3] obs0_abist_cmp; + +// Scan +input [0:1] abst_scan_in; +input time_scan_in; +input repr_scan_in; +input func_scan_in; +output [0:1] abst_scan_out; +output time_scan_out; +output repr_scan_out; +output func_scan_out; + +// BOLT-ON +input lcb_bolt_sl_thold_0; +input pc_bo_enable_2; // general bolt-on enable +input pc_bo_reset; // reset +input pc_bo_unload; // unload sticky bits +input pc_bo_repair; // execute sticky bit decode +input pc_bo_shdata; // shift data for timing write and diag loop +input [0:1] pc_bo_select; // select for mask and hier writes +output [0:1] bo_pc_failout; // fail/no-fix reg +output [0:1] bo_pc_diagloop; +input tri_lcb_mpw1_dc_b; +input tri_lcb_mpw2_dc_b; +input tri_lcb_delay_lclkr_dc; +input tri_lcb_clkoff_dc_b; +input tri_lcb_act_dis_dc; + +// Write Ports +input [0:ways-1] wr_way; +input [0:addressbus_width-1] wr_addr; +input [0:port_bitwidth-1] data_in; + +// Read Ports +input [0:addressbus_width-1] rd_addr; +output [0:port_bitwidth*ways-1] data_out; + +// tri_32x70_2w_1r1w + +parameter ramb_base_width = 36; +parameter ramb_base_addr = 9; + +// Configuration Statement for NCsim +//for all:RAMB16_S36_S36 use entity unisim.RAMB16_S36_S36; +parameter rd_act_offset = 0; +parameter data_out0_offset = rd_act_offset + 2; +parameter data_out1_offset = data_out0_offset + port_bitwidth - 1; +parameter scan_right = data_out1_offset + port_bitwidth - 1; + +wire [0:port_bitwidth-1] array_wr_data; +wire [0:35] ramb_data_in_l; +wire [0:35] ramb_data_in_r; +wire [0:35] ramb_data_p0_outA; +wire [0:35] ramb_data_p0_outB; +wire [0:35] ramb_data_p0_outC; +wire [0:35] ramb_data_p0_outD; +wire [0:35] ramb_data_p1_outA; +wire [0:35] ramb_data_p1_outB; +wire [0:35] ramb_data_p1_outC; +wire [0:35] ramb_data_p1_outD; +wire [0:ramb_base_addr-1] ramb_addr_rd1; +wire [0:ramb_base_addr-1] ramb_addr_wr_rd0; + +wire [0:ramb_base_addr-1] rd_addr0; +wire [0:ramb_base_addr-1] wr_addr1; +wire write_enable_AB; +wire write_enable_CD; +wire tiup; +wire [0:35] tidn; +wire [0:1] act; +wire ary_nsl_thold_0_b; +wire [0:addressable_ports-1] arrA_bit0_scanout; +wire [0:addressable_ports-1] arrC_bit0_scanout; +wire [0:addressable_ports-1] arrA_bit0_d; +wire [0:addressable_ports-1] arrA_bit0_q; +wire [0:addressable_ports-1] arrC_bit0_d; +wire [0:addressable_ports-1] arrC_bit0_q; +wire [0:addressable_ports-1] arrA_bit0_wen; +wire [0:addressable_ports-1] arrC_bit0_wen; +reg arrA_bit0_out_d; +reg arrC_bit0_out_d; +wire arrA_bit0_out_q; +wire arrC_bit0_out_q; +wire arrA_bit0_out_scanout; +wire arrC_bit0_out_scanout; +wire [0:port_bitwidth*ways-1] data_out_d; +wire [0:port_bitwidth*ways-1] data_out_q; +wire [0:1] rd_act_d; +wire [0:1] rd_act_q; +wire [0:scan_right] siv; +wire [0:scan_right] sov; + +(* analysis_not_referenced="true" *) +wire unused; + +assign unused = | {ramb_data_p1_outA[0], ramb_data_p1_outA[35], ramb_data_p1_outB[35], ramb_data_p1_outC[0], ramb_data_p1_outC[35], ramb_data_p1_outD[35], + ramb_data_p0_outA, ramb_data_p0_outB, ramb_data_p0_outC, ramb_data_p0_outD, gnd, vdd, vcs, + sg_0, abst_sl_thold_0, ary_nsl_thold_0, time_sl_thold_0, repr_sl_thold_0, g8t_clkoff_dc_b, ccflush_dc, scan_dis_dc_b, + scan_diag_dc, g8t_d_mode_dc, g8t_mpw1_dc_b, g8t_mpw2_dc_b, g8t_delay_lclkr_dc, wr_abst_act, rd0_abst_act, abist_di, abist_bw_odd, + abist_bw_even, abist_wr_adr, abist_rd0_adr, tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, + obs0_abist_cmp, abst_scan_in, time_scan_in, repr_scan_in, lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, + pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, + tri_lcb_act_dis_dc, arrA_bit0_scanout, arrC_bit0_scanout, arrA_bit0_out_scanout, arrC_bit0_out_scanout}; + +assign tiup = 1'b1; +assign tidn = 36'b0; +assign act = rd_act | wr_act; +assign rd_act_d = rd_act; + +// Data Generate +assign array_wr_data = data_in; + +assign ramb_data_in_l = {array_wr_data[0:34], 1'b0}; +assign ramb_data_in_r = {array_wr_data[35:69], 1'b0}; + +assign write_enable_AB = wr_act[0] & wr_way[0]; +assign write_enable_CD = wr_act[1] & wr_way[1]; + +// Read/Write Port Address Generate +generate +begin + genvar t; + for (t = 0; t < ramb_base_addr; t = t + 1) + begin : rambAddrCalc + if (t < ramb_base_addr - addressbus_width) + begin + assign rd_addr0[t] = 1'b0; + assign wr_addr1[t] = 1'b0; + end + if (t >= ramb_base_addr - addressbus_width) + begin + assign rd_addr0[t] = rd_addr[t - (ramb_base_addr - addressbus_width)]; + assign wr_addr1[t] = wr_addr[t - (ramb_base_addr - addressbus_width)]; + end + end +end +endgenerate + +// Writing on PortA +// Reading on PortB +assign ramb_addr_rd1 = rd_addr0; +assign ramb_addr_wr_rd0 = wr_addr1; + +assign data_out_d = {arrA_bit0_out_q, ramb_data_p1_outA[1:34], ramb_data_p1_outB[0:34], arrC_bit0_out_q, ramb_data_p1_outC[1:34], ramb_data_p1_outD[0:34]}; +assign data_out = data_out_q; + +generate + begin : arr_bit0 + genvar i; + for (i = 0; i <= addressable_ports - 1; i = i + 1) + begin : arr_bit0 + wire [0:addressbus_width-1] iDummy=i; + assign arrA_bit0_wen[i] = write_enable_AB & (wr_addr == iDummy); + assign arrC_bit0_wen[i] = write_enable_CD & (wr_addr == iDummy); + assign arrA_bit0_d[i] = (arrA_bit0_wen[i] == 1'b1) ? array_wr_data[0] : + arrA_bit0_q[i]; + assign arrC_bit0_d[i] = (arrC_bit0_wen[i] == 1'b1) ? array_wr_data[0] : + arrC_bit0_q[i]; + end + end +endgenerate + +always @(*) + begin: bit0_read_proc + reg rd_arrA_bit0; + reg rd_arrC_bit0; + //(* analysis_not_referenced="true" *) + reg [0:31] i; + rd_arrA_bit0 = 1'b0; + rd_arrC_bit0 = 1'b0; + for (i = 0; i <= addressable_ports - 1; i = i + 1) + begin + rd_arrA_bit0 = ((rd_addr == i[32-addressbus_width:31]) & arrA_bit0_q[i]) | rd_arrA_bit0; + rd_arrC_bit0 = ((rd_addr == i[32-addressbus_width:31]) & arrC_bit0_q[i]) | rd_arrC_bit0; + end + arrA_bit0_out_d = rd_arrA_bit0; + arrC_bit0_out_d = rd_arrC_bit0; + end + + +assign ary_nsl_thold_0_b = ~ ary_nsl_thold_0; + +tri_regk #(.WIDTH(addressable_ports), .INIT(0), .NEEDS_SRESET(1)) arrA_bit0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(write_enable_AB), + .force_t(tidn[0]), + .d_mode(tidn[0]), + .delay_lclkr(tidn[0]), + .mpw1_b(tidn[0]), + .mpw2_b(tidn[0]), + .thold_b(ary_nsl_thold_0_b), + .sg(tidn[0]), + .scin({addressable_ports{tidn[0]}}), + .scout(arrA_bit0_scanout), + .din(arrA_bit0_d), + .dout(arrA_bit0_q) +); + +tri_regk #(.WIDTH(addressable_ports), .INIT(0), .NEEDS_SRESET(1)) arrC_bit0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(write_enable_CD), + .force_t(tidn[0]), + .d_mode(tidn[0]), + .delay_lclkr(tidn[0]), + .mpw1_b(tidn[0]), + .mpw2_b(tidn[0]), + .thold_b(ary_nsl_thold_0_b), + .sg(tidn[0]), + .scin({addressable_ports{tidn[0]}}), + .scout(arrC_bit0_scanout), + .din(arrC_bit0_d), + .dout(arrC_bit0_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) arrA_bit0_out_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(tidn[0]), + .d_mode(tidn[0]), + .delay_lclkr(tidn[0]), + .mpw1_b(tidn[0]), + .mpw2_b(tidn[0]), + .thold_b(ary_nsl_thold_0_b), + .sg(tidn[0]), + .scin(tidn[0]), + .scout(arrA_bit0_out_scanout), + .din(arrA_bit0_out_d), + .dout(arrA_bit0_out_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) arrC_bit0_out_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(tidn[0]), + .d_mode(tidn[0]), + .delay_lclkr(tidn[0]), + .mpw1_b(tidn[0]), + .mpw2_b(tidn[0]), + .thold_b(ary_nsl_thold_0_b), + .sg(tidn[0]), + .scin(tidn[0]), + .scout(arrC_bit0_out_scanout), + .din(arrC_bit0_out_d), + .dout(arrC_bit0_out_q) +); + + +RAMB16_S36_S36 + #(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only +arr0_A( + .DOA(ramb_data_p0_outA[0:31]), + .DOB(ramb_data_p1_outA[0:31]), + .DOPA(ramb_data_p0_outA[32:35]), + .DOPB(ramb_data_p1_outA[32:35]), + .ADDRA(ramb_addr_wr_rd0), + .ADDRB(ramb_addr_rd1), + .CLKA(nclk[0]), + .CLKB(nclk[0]), + .DIA(ramb_data_in_l[0:31]), + .DIB(tidn[0:31]), + .DIPA(ramb_data_in_l[32:35]), + .DIPB(tidn[32:35]), + .ENA(act[0]), + .ENB(act[0]), + .SSRA(nclk[1]), //sreset + .SSRB(nclk[1]), //sreset + .WEA(write_enable_AB), + .WEB(tidn[0]) +); + +RAMB16_S36_S36 + #(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only +arr1_B( + .DOA(ramb_data_p0_outB[0:31]), + .DOB(ramb_data_p1_outB[0:31]), + .DOPA(ramb_data_p0_outB[32:35]), + .DOPB(ramb_data_p1_outB[32:35]), + .ADDRA(ramb_addr_wr_rd0), + .ADDRB(ramb_addr_rd1), + .CLKA(nclk[0]), + .CLKB(nclk[0]), + .DIA(ramb_data_in_r[0:31]), + .DIB(tidn[0:31]), + .DIPA(ramb_data_in_r[32:35]), + .DIPB(tidn[32:35]), + .ENA(act[0]), + .ENB(act[0]), + .SSRA(nclk[1]), + .SSRB(nclk[1]), + .WEA(write_enable_AB), + .WEB(tidn[0]) +); + +RAMB16_S36_S36 + #(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only +arr2_C( + .DOA(ramb_data_p0_outC[0:31]), + .DOB(ramb_data_p1_outC[0:31]), + .DOPA(ramb_data_p0_outC[32:35]), + .DOPB(ramb_data_p1_outC[32:35]), + .ADDRA(ramb_addr_wr_rd0), + .ADDRB(ramb_addr_rd1), + .CLKA(nclk[0]), + .CLKB(nclk[0]), + .DIA(ramb_data_in_l[0:31]), + .DIB(tidn[0:31]), + .DIPA(ramb_data_in_l[32:35]), + .DIPB(tidn[32:35]), + .ENA(act[1]), + .ENB(act[1]), + .SSRA(nclk[1]), + .SSRB(nclk[1]), + .WEA(write_enable_CD), + .WEB(tidn[0]) +); + +RAMB16_S36_S36 + #(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only +arr3_D( + .DOA(ramb_data_p0_outD[0:31]), + .DOB(ramb_data_p1_outD[0:31]), + .DOPA(ramb_data_p0_outD[32:35]), + .DOPB(ramb_data_p1_outD[32:35]), + .ADDRA(ramb_addr_wr_rd0), + .ADDRB(ramb_addr_rd1), + .CLKA(nclk[0]), + .CLKB(nclk[0]), + .DIA(ramb_data_in_r[0:31]), + .DIB(tidn[0:31]), + .DIPA(ramb_data_in_r[32:35]), + .DIPB(tidn[32:35]), + .ENA(act[1]), + .ENB(act[1]), + .SSRA(nclk[1]), + .SSRB(nclk[1]), + .WEA(write_enable_CD), + .WEB(tidn[0]) +); + +// #################################################### +// Registers +// #################################################### + +tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) rd_act_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rd_act_offset:rd_act_offset + 2 - 1]), + .scout(sov[rd_act_offset:rd_act_offset + 2 - 1]), + .din(rd_act_d), + .dout(rd_act_q) +); + +tri_rlmreg_p #(.WIDTH(port_bitwidth), .INIT(0), .NEEDS_SRESET(1)) data_out0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rd_act_q[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[data_out0_offset:data_out0_offset + port_bitwidth - 1]), + .scout(sov[data_out0_offset:data_out0_offset + port_bitwidth - 1]), + .din(data_out_d[0:port_bitwidth - 1]), + .dout(data_out_q[0:port_bitwidth - 1]) +); + +tri_rlmreg_p #(.WIDTH(port_bitwidth), .INIT(0), .NEEDS_SRESET(1)) data_out1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rd_act_q[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[data_out1_offset:data_out1_offset + port_bitwidth - 1]), + .scout(sov[data_out1_offset:data_out1_offset + port_bitwidth - 1]), + .din(data_out_d[port_bitwidth:2 * port_bitwidth - 1]), + .dout(data_out_q[port_bitwidth:2 * port_bitwidth - 1]) +); + +assign siv[0:scan_right] = {sov[1:scan_right], func_scan_in}; +assign func_scan_out = sov[0]; + +assign abst_scan_out = tidn[0:1]; +assign time_scan_out = tidn[0]; +assign repr_scan_out = tidn[0]; +assign bo_pc_failout = tidn[0:1]; +assign bo_pc_diagloop = tidn[0:1]; +endmodule diff --git a/dev/verilog/trilib/tri_512x162_4w_0.v b/dev/verilog/trilib/tri_512x162_4w_0.v new file mode 100755 index 0000000..439dd57 --- /dev/null +++ b/dev/verilog/trilib/tri_512x162_4w_0.v @@ -0,0 +1,338 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILENAME : tri_512x162_4w_0.v +// *! DESCRIPTION : 512 Entry x 162 bit x 4 way array +// *! +// *!**************************************************************** + +`include "tri_a2o.vh" + +module tri_512x162_4w_0( + gnd, + vdd, + vcs, + nclk, + ccflush_dc, + lcb_clkoff_dc_b, + lcb_d_mode_dc, + lcb_act_dis_dc, + lcb_ary_nsl_thold_0, + lcb_sg_1, + lcb_abst_sl_thold_0, + lcb_func_sl_thold_0_b, + func_force, + scan_diag_dc, + scan_dis_dc_b, + func_scan_in, + func_scan_out, + abst_scan_in, + abst_scan_out, + lcb_delay_lclkr_np_dc, + ctrl_lcb_delay_lclkr_np_dc, + dibw_lcb_delay_lclkr_np_dc, + ctrl_lcb_mpw1_np_dc_b, + dibw_lcb_mpw1_np_dc_b, + lcb_mpw1_pp_dc_b, + lcb_mpw1_2_pp_dc_b, + aodo_lcb_delay_lclkr_dc, + aodo_lcb_mpw1_dc_b, + aodo_lcb_mpw2_dc_b, + lcb_time_sg_0, + lcb_time_sl_thold_0, + time_scan_in, + time_scan_out, + bitw_abist, + lcb_repr_sl_thold_0, + lcb_repr_sg_0, + repr_scan_in, + repr_scan_out, + tc_lbist_ary_wrt_thru_dc, + abist_en_1, + din_abist, + abist_cmp_en, + abist_raw_b_dc, + data_cmp_abist, + addr_abist, + r_wb_abist, + write_thru_en_dc, + lcb_bolt_sl_thold_0, + pc_bo_enable_2, + pc_bo_reset, + pc_bo_unload, + pc_bo_repair, + pc_bo_shdata, + pc_bo_select, + bo_pc_failout, + bo_pc_diagloop, + tri_lcb_mpw1_dc_b, + tri_lcb_mpw2_dc_b, + tri_lcb_delay_lclkr_dc, + tri_lcb_clkoff_dc_b, + tri_lcb_act_dis_dc, + read_act, + write_act, + write_enable, + write_way, + addr, + data_in, + data_out +); + parameter addressable_ports = 512; // number of addressable register in this array + parameter addressbus_width = 9; // width of the bus to address all ports (2^addressbus_width >= addressable_ports) + parameter port_bitwidth = 162; // bitwidth of ports + parameter ways = 4; // number of ways + // POWER PINS + inout gnd; + inout vdd; + (* analysis_not_referenced="true" *) + inout vcs; + // CLOCK and CLOCKCONTROL ports + input [0:`NCLK_WIDTH-1] nclk; + input ccflush_dc; + input lcb_clkoff_dc_b; + input lcb_d_mode_dc; + input lcb_act_dis_dc; + input lcb_ary_nsl_thold_0; + input lcb_sg_1; + input lcb_abst_sl_thold_0; + input lcb_func_sl_thold_0_b; + input func_force; + input scan_diag_dc; + input scan_dis_dc_b; + input func_scan_in; + output func_scan_out; + input [0:1] abst_scan_in; + output [0:1] abst_scan_out; + input lcb_delay_lclkr_np_dc; + input ctrl_lcb_delay_lclkr_np_dc; + input dibw_lcb_delay_lclkr_np_dc; + input ctrl_lcb_mpw1_np_dc_b; + input dibw_lcb_mpw1_np_dc_b; + input lcb_mpw1_pp_dc_b; + input lcb_mpw1_2_pp_dc_b; + input aodo_lcb_delay_lclkr_dc; + input aodo_lcb_mpw1_dc_b; + input aodo_lcb_mpw2_dc_b; + // Timing Scan Chain Pins + input lcb_time_sg_0; + input lcb_time_sl_thold_0; + input time_scan_in; + output time_scan_out; + input [0:1] bitw_abist; + // REDUNDANCY PINS + input lcb_repr_sl_thold_0; + input lcb_repr_sg_0; + input repr_scan_in; + output repr_scan_out; + // DATA I/O RELATED PINS: + input tc_lbist_ary_wrt_thru_dc; + input abist_en_1; + input [0:3] din_abist; + input abist_cmp_en; + input abist_raw_b_dc; + input [0:3] data_cmp_abist; + input [0:addressbus_width-1] addr_abist; + input r_wb_abist; + input write_thru_en_dc; + // BOLT-ON + input lcb_bolt_sl_thold_0; // thold for any regs inside backend + input pc_bo_enable_2; // general bolt-on enable, probably DC + input pc_bo_reset; // execute sticky bit decode + input pc_bo_unload; + input pc_bo_repair; // load repair reg + input pc_bo_shdata; // shift data for timing write + input [0:1] pc_bo_select; // select for mask and hier writes + output [0:1] bo_pc_failout; // fail/no-fix reg + output [0:1] bo_pc_diagloop; + input tri_lcb_mpw1_dc_b; + input tri_lcb_mpw2_dc_b; + input tri_lcb_delay_lclkr_dc; + input tri_lcb_clkoff_dc_b; + input tri_lcb_act_dis_dc; + // FUNCTIONAL PORTS + input [0:1] read_act; + input [0:3] write_act; + input write_enable; + input [0:ways-1] write_way; + input [0:addressbus_width-1] addr; + input [0:port_bitwidth-1] data_in; + output [0:port_bitwidth*ways-1] data_out; + + // tri_512x162_4w_0 + + parameter ramb_base_width = 36; + parameter ramb_base_addr = 9; + parameter ramb_width_mult = (port_bitwidth - 1)/ramb_base_width + 1; // # of RAMB's per way + + // Configuration Statement for NCsim + //for all:RAMB16_S36_S36 use entity unisim.RAMB16_S36_S36; + + wire [0:ramb_base_width*ramb_width_mult-1] ramb_data_in; + wire [0:ramb_base_width*ramb_width_mult-1] ramb_data_out[0:ways-1]; + wire [0:ramb_base_addr-1] ramb_addr; + + wire rd_act_d; + wire rd_act_l2; + wire [0:port_bitwidth*ways-1] data_out_d; + wire [0:port_bitwidth*ways-1] data_out_l2; + + wire lcb_sg_0; + + wire [0:ways-1] act; + wire [0:ways-1] write; + wire tidn; + (* analysis_not_referenced="true" *) + wire unused; + wire [31:0] dob; + wire [3:0] dopb; + wire [0:port_bitwidth*ways-1] unused_scout; + + generate + begin + assign tidn = 1'b0; + + if (addressbus_width < ramb_base_addr) + begin + assign ramb_addr[0:(ramb_base_addr - addressbus_width - 1)] = {(ramb_base_addr-addressbus_width){1'b0}}; + assign ramb_addr[ramb_base_addr - addressbus_width:ramb_base_addr - 1] = addr; + end + if (addressbus_width >= ramb_base_addr) + begin + assign ramb_addr = addr[addressbus_width - ramb_base_addr:addressbus_width - 1]; + end + + genvar i; + for (i = 0; i < ramb_base_width*ramb_width_mult; i = i + 1) + begin : din + if (i < port_bitwidth) + assign ramb_data_in[i] = data_in[i]; + if (i >= port_bitwidth) + assign ramb_data_in[i] = 1'b0; + end + + genvar w; + for (w = 0; w < ways; w = w + 1) + begin : aw + assign act[w] = (|(read_act)) | write_way[w]; + assign write[w] = write_enable & write_way[w]; + + genvar x; + for (x = 0; x < ramb_width_mult; x = x + 1) + begin : ax + RAMB16_S36_S36 + #(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only + arr( + .DOA(ramb_data_out[w][x * ramb_base_width:x * ramb_base_width + 31]), + .DOB(dob), + .DOPA(ramb_data_out[w][x * ramb_base_width + 32:x * ramb_base_width + 35]), + .DOPB(dopb), + .ADDRA(ramb_addr), + .ADDRB(ramb_addr), + .CLKA(nclk[0]), + .CLKB(tidn), + .DIA(ramb_data_in[x * ramb_base_width:x * ramb_base_width + 31]), + .DIB(ramb_data_in[x * ramb_base_width:x * ramb_base_width + 31]), + .DIPA(ramb_data_in[x * ramb_base_width + 32:x * ramb_base_width + 35]), + .DIPB(ramb_data_in[x * ramb_base_width + 32:x * ramb_base_width + 35]), + .ENA(act[w]), + .ENB(tidn), + .SSRA(nclk[1]), + .SSRB(tidn), + .WEA(write[w]), + .WEB(tidn) + ); + end //ax + + assign data_out_d[w * port_bitwidth:((w + 1) * port_bitwidth) - 1] = ramb_data_out[w][0:port_bitwidth - 1]; + + end //aw + + assign data_out = data_out_l2; + + assign rd_act_d = |(read_act); // Use for data_out latch act + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(0)) rd_act_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(1'b1), + .thold_b(lcb_func_sl_thold_0_b), + .sg(lcb_sg_0), + .force_t(func_force), + .delay_lclkr(tri_lcb_delay_lclkr_dc), + .mpw1_b(tri_lcb_mpw1_dc_b), + .mpw2_b(tri_lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(1'b0), + .scout(func_scan_out), + .din(rd_act_d), + .dout(rd_act_l2) + ); + + tri_rlmreg_p #(.WIDTH(port_bitwidth*ways), .INIT(0), .NEEDS_SRESET(0)) data_out_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rd_act_l2), + .thold_b(lcb_func_sl_thold_0_b), + .sg(lcb_sg_0), + .force_t(func_force), + .delay_lclkr(tri_lcb_delay_lclkr_dc), + .mpw1_b(tri_lcb_mpw1_dc_b), + .mpw2_b(tri_lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin({port_bitwidth*ways{1'b0}}), + .scout(unused_scout), + .din(data_out_d), + .dout(data_out_l2) + ); + + tri_plat #(.WIDTH(1)) perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(ccflush_dc), + .din(lcb_sg_1), + .q(lcb_sg_0) + ); + + assign abst_scan_out = 2'b00; + assign time_scan_out = 1'b0; + assign repr_scan_out = 1'b0; + + assign bo_pc_failout = 2'b00; + assign bo_pc_diagloop = 2'b00; + + assign unused = | ({nclk[2:`NCLK_WIDTH-1], ramb_data_out[0][port_bitwidth:ramb_base_width * ramb_width_mult - 1], ramb_data_out[1][port_bitwidth:ramb_base_width * ramb_width_mult - 1], ramb_data_out[2][port_bitwidth:ramb_base_width * ramb_width_mult - 1], ramb_data_out[3][port_bitwidth:ramb_base_width * ramb_width_mult - 1], ccflush_dc, lcb_clkoff_dc_b, lcb_d_mode_dc, lcb_act_dis_dc, scan_dis_dc_b, scan_diag_dc, bitw_abist, lcb_sg_1, lcb_time_sg_0, lcb_repr_sg_0, lcb_abst_sl_thold_0, lcb_repr_sl_thold_0, lcb_time_sl_thold_0, lcb_ary_nsl_thold_0, tc_lbist_ary_wrt_thru_dc, abist_en_1, din_abist, abist_cmp_en, abist_raw_b_dc, data_cmp_abist, addr_abist, r_wb_abist, write_thru_en_dc, abst_scan_in, time_scan_in, repr_scan_in, func_scan_in, lcb_delay_lclkr_np_dc, ctrl_lcb_delay_lclkr_np_dc, dibw_lcb_delay_lclkr_np_dc, ctrl_lcb_mpw1_np_dc_b, dibw_lcb_mpw1_np_dc_b, lcb_mpw1_pp_dc_b, lcb_mpw1_2_pp_dc_b, aodo_lcb_delay_lclkr_dc, aodo_lcb_mpw1_dc_b, aodo_lcb_mpw2_dc_b, lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, tri_lcb_act_dis_dc, write_act, dob, dopb, unused_scout}); + end + endgenerate +endmodule diff --git a/dev/verilog/trilib/tri_512x16_1r1w_1.v b/dev/verilog/trilib/tri_512x16_1r1w_1.v new file mode 100755 index 0000000..b8c643a --- /dev/null +++ b/dev/verilog/trilib/tri_512x16_1r1w_1.v @@ -0,0 +1,333 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//***************************************************************************** +// Description: Tri Array Wrapper +// +//***************************************************************************** + +`include "tri_a2o.vh" + +module tri_512x16_1r1w_1( + vdd, + vcs, + gnd, + nclk, + rd_act, + wr_act, + lcb_d_mode_dc, + lcb_clkoff_dc_b, + lcb_mpw1_dc_b, + lcb_mpw2_dc_b, + lcb_delay_lclkr_dc, + ccflush_dc, + scan_dis_dc_b, + scan_diag_dc, + func_scan_in, + func_scan_out, + lcb_sg_0, + lcb_sl_thold_0_b, + lcb_time_sl_thold_0, + lcb_abst_sl_thold_0, + lcb_ary_nsl_thold_0, + lcb_repr_sl_thold_0, + time_scan_in, + time_scan_out, + abst_scan_in, + abst_scan_out, + repr_scan_in, + repr_scan_out, + abist_di, + abist_bw_odd, + abist_bw_even, + abist_wr_adr, + wr_abst_act, + abist_rd0_adr, + rd0_abst_act, + tc_lbist_ary_wrt_thru_dc, + abist_ena_1, + abist_g8t_rd0_comp_ena, + abist_raw_dc_b, + obs0_abist_cmp, + lcb_bolt_sl_thold_0, + pc_bo_enable_2, + pc_bo_reset, + pc_bo_unload, + pc_bo_repair, + pc_bo_shdata, + pc_bo_select, + bo_pc_failout, + bo_pc_diagloop, + tri_lcb_mpw1_dc_b, + tri_lcb_mpw2_dc_b, + tri_lcb_delay_lclkr_dc, + tri_lcb_clkoff_dc_b, + tri_lcb_act_dis_dc, + bw, + wr_adr, + rd_adr, + di, + dout +); + parameter addressable_ports = 128; // number of addressable register in this array + parameter addressbus_width = 9; // width of the bus to address all ports (2^addressbus_width >= addressable_ports) + parameter port_bitwidth = 16; // bitwidth of ports + parameter ways = 1; // number of ways + + // POWER PINS + inout vdd; + inout vcs; + inout gnd; + + input [0:`NCLK_WIDTH-1] nclk; + + input rd_act; + input wr_act; + + // DC TEST PINS + input lcb_d_mode_dc; + input lcb_clkoff_dc_b; + input [0:4] lcb_mpw1_dc_b; + input lcb_mpw2_dc_b; + input [0:4] lcb_delay_lclkr_dc; + + input ccflush_dc; + input scan_dis_dc_b; + input scan_diag_dc; + input func_scan_in; + output func_scan_out; + + input lcb_sg_0; + input lcb_sl_thold_0_b; + input lcb_time_sl_thold_0; + input lcb_abst_sl_thold_0; + input lcb_ary_nsl_thold_0; + input lcb_repr_sl_thold_0; + input time_scan_in; + output time_scan_out; + input abst_scan_in; + output abst_scan_out; + input repr_scan_in; + output repr_scan_out; + + input [0:3] abist_di; + input abist_bw_odd; + input abist_bw_even; + input [0:6] abist_wr_adr; + input wr_abst_act; + input [0:6] abist_rd0_adr; + input rd0_abst_act; + input tc_lbist_ary_wrt_thru_dc; + input abist_ena_1; + input abist_g8t_rd0_comp_ena; + input abist_raw_dc_b; + input [0:3] obs0_abist_cmp; + + // BOLT-ON + input lcb_bolt_sl_thold_0; + input pc_bo_enable_2; // general bolt-on enable + input pc_bo_reset; // reset + input pc_bo_unload; // unload sticky bits + input pc_bo_repair; // execute sticky bit decode + input pc_bo_shdata; // shift data for timing write and diag loop + input pc_bo_select; // select for mask and hier writes + output bo_pc_failout; // fail/no-fix reg + output bo_pc_diagloop; + input tri_lcb_mpw1_dc_b; + input tri_lcb_mpw2_dc_b; + input tri_lcb_delay_lclkr_dc; + input tri_lcb_clkoff_dc_b; + input tri_lcb_act_dis_dc; + + input [0:15] bw; + input [0:8] wr_adr; + input [0:8] rd_adr; + input [0:15] di; + + output [0:15] dout; + + // Configuration Statement for NCsim + //for all:RAMB16_S36_S36 use entity unisim.RAMB16_S36_S36; + + wire clk; + wire clk2x; + wire [0:8] b0addra; + wire [0:8] b0addrb; + wire wea; + wire web; + wire wren_a; + // Latches + reg reset_q; + reg gate_fq; + wire gate_d; + wire [0:35] r_data_out_1_d; + reg [0:35] r_data_out_1_fq; + wire [0:35] w_data_in_0; + + wire [0:35] r_data_out_0_bram; + wire [0:35] r_data_out_1_bram; + + wire toggle_d; + reg toggle_q; + wire toggle2x_d; + reg toggle2x_q; + + (* analysis_not_referenced="true" *) + wire unused; + + assign clk = nclk[0]; + assign clk2x = nclk[2]; + + always @(posedge clk) + begin: rlatch + reset_q <= nclk[1]; + end + + // + // NEW clk2x gate logic start + // + + always @(posedge clk) + begin: tlatch + if (reset_q == 1'b1) + toggle_q <= 1'b1; + else + toggle_q <= toggle_d; + end + + always @(posedge clk2x) + begin: flatch + toggle2x_q <= toggle2x_d; + gate_fq <= gate_d; + r_data_out_1_fq <= r_data_out_1_d; + end + + assign toggle_d = (~toggle_q); + assign toggle2x_d = toggle_q; + + // should force gate_fq to be on during odd 2x clock (second half of 1x clock). + //gate_d <= toggle_q xor toggle2x_q; + // if you want the first half do the following + assign gate_d = (~(toggle_q ^ toggle2x_q)); + + // + // NEW clk2x gate logic end + // + + assign b0addra[0:8] = wr_adr; + assign b0addrb[0:8] = rd_adr; + + // Unused Address Bits + //b0addra(0 to 1) <= "00"; + //b0addrb(0 to 1) <= "00"; + + // port a is a read-modify-write port + assign wren_a = ((bw != 16'b0000000000000000) & (wr_act == 1'b1)) ? 1'b1 : + 1'b0; + assign wea = wren_a & (~(gate_fq)); // write in 2nd half of nclk + assign web = 1'b0; + assign w_data_in_0[0] = (bw[0] == 1'b1) ? di[0] : + r_data_out_0_bram[0]; + assign w_data_in_0[1] = (bw[1] == 1'b1) ? di[1] : + r_data_out_0_bram[1]; + assign w_data_in_0[2] = (bw[2] == 1'b1) ? di[2] : + r_data_out_0_bram[2]; + assign w_data_in_0[3] = (bw[3] == 1'b1) ? di[3] : + r_data_out_0_bram[3]; + assign w_data_in_0[4] = (bw[4] == 1'b1) ? di[4] : + r_data_out_0_bram[4]; + assign w_data_in_0[5] = (bw[5] == 1'b1) ? di[5] : + r_data_out_0_bram[5]; + assign w_data_in_0[6] = (bw[6] == 1'b1) ? di[6] : + r_data_out_0_bram[6]; + assign w_data_in_0[7] = (bw[7] == 1'b1) ? di[7] : + r_data_out_0_bram[7]; + assign w_data_in_0[8] = (bw[8] == 1'b1) ? di[8] : + r_data_out_0_bram[8]; + assign w_data_in_0[9] = (bw[9] == 1'b1) ? di[9] : + r_data_out_0_bram[9]; + assign w_data_in_0[10] = (bw[10] == 1'b1) ? di[10] : + r_data_out_0_bram[10]; + assign w_data_in_0[11] = (bw[11] == 1'b1) ? di[11] : + r_data_out_0_bram[11]; + assign w_data_in_0[12] = (bw[12] == 1'b1) ? di[12] : + r_data_out_0_bram[12]; + assign w_data_in_0[13] = (bw[13] == 1'b1) ? di[13] : + r_data_out_0_bram[13]; + assign w_data_in_0[14] = (bw[14] == 1'b1) ? di[14] : + r_data_out_0_bram[14]; + assign w_data_in_0[15] = (bw[15] == 1'b1) ? di[15] : + r_data_out_0_bram[15]; + assign w_data_in_0[16:35] = 20'b0; + + assign r_data_out_1_d = r_data_out_1_bram; + + RAMB16_S36_S36 + #(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only + bram0a( + .CLKA(clk2x), + .CLKB(clk2x), + .SSRA(reset_q), + .SSRB(reset_q), + .ADDRA(b0addra), + .ADDRB(b0addrb), + .DIA(w_data_in_0[0:31]), + .DIB(32'b0), + .DOA(r_data_out_0_bram[0:31]), + .DOB(r_data_out_1_bram[0:31]), + .DOPA(r_data_out_0_bram[32:35]), + .DOPB(r_data_out_1_bram[32:35]), + .DIPA(w_data_in_0[32:35]), + .DIPB(4'h0), + .ENA(1'b1), + .ENB(1'b1), + .WEA(wea), + .WEB(web) + ); + + assign dout = r_data_out_1_fq[0:15]; + + assign func_scan_out = func_scan_in; + assign time_scan_out = time_scan_in; + assign abst_scan_out = abst_scan_in; + assign repr_scan_out = repr_scan_in; + + assign bo_pc_failout = 1'b0; + assign bo_pc_diagloop = 1'b0; + + assign unused = |{vdd, vcs, gnd, nclk, lcb_d_mode_dc, lcb_clkoff_dc_b, lcb_mpw1_dc_b, lcb_mpw2_dc_b, + lcb_delay_lclkr_dc, ccflush_dc, scan_dis_dc_b, scan_diag_dc, lcb_sg_0, lcb_sl_thold_0_b, + lcb_time_sl_thold_0, lcb_abst_sl_thold_0, lcb_ary_nsl_thold_0, lcb_repr_sl_thold_0, + abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, wr_abst_act, abist_rd0_adr, rd0_abst_act, + tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp, + lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, + pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, + tri_lcb_act_dis_dc, rd_act, r_data_out_0_bram[16:35], r_data_out_1_fq[16:35]}; +endmodule diff --git a/dev/verilog/trilib/tri_64x144_1r1w.v b/dev/verilog/trilib/tri_64x144_1r1w.v new file mode 100755 index 0000000..4144333 --- /dev/null +++ b/dev/verilog/trilib/tri_64x144_1r1w.v @@ -0,0 +1,426 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILENAME : tri_64x144_1r1w.v +// *! DESCRIPTION : 64 Entry x 144 bit array, 9 bit writeable +// *! +// *!**************************************************************** + +`include "tri_a2o.vh" + +module tri_64x144_1r1w( + gnd, + vdd, + vcs, + nclk, + rd_act, + wr_act, + sg_0, + abst_sl_thold_0, + ary_nsl_thold_0, + time_sl_thold_0, + repr_sl_thold_0, + func_sl_force, + func_sl_thold_0_b, + g8t_clkoff_dc_b, + ccflush_dc, + scan_dis_dc_b, + scan_diag_dc, + g8t_d_mode_dc, + g8t_mpw1_dc_b, + g8t_mpw2_dc_b, + g8t_delay_lclkr_dc, + d_mode_dc, + mpw1_dc_b, + mpw2_dc_b, + delay_lclkr_dc, + wr_abst_act, + rd0_abst_act, + abist_di, + abist_bw_odd, + abist_bw_even, + abist_wr_adr, + abist_rd0_adr, + tc_lbist_ary_wrt_thru_dc, + abist_ena_1, + abist_g8t_rd0_comp_ena, + abist_raw_dc_b, + obs0_abist_cmp, + abst_scan_in, + time_scan_in, + repr_scan_in, + func_scan_in, + abst_scan_out, + time_scan_out, + repr_scan_out, + func_scan_out, + lcb_bolt_sl_thold_0, + pc_bo_enable_2, + pc_bo_reset, + pc_bo_unload, + pc_bo_repair, + pc_bo_shdata, + pc_bo_select, + bo_pc_failout, + bo_pc_diagloop, + tri_lcb_mpw1_dc_b, + tri_lcb_mpw2_dc_b, + tri_lcb_delay_lclkr_dc, + tri_lcb_clkoff_dc_b, + tri_lcb_act_dis_dc, + write_enable, + addr_wr, + data_in, + addr_rd, + data_out +); +parameter addressable_ports = 64; // number of addressable register in this array +parameter addressbus_width = 6; // width of the bus to address all ports (2^addressbus_width >= addressable_ports) +parameter port_bitwidth = 144; // bitwidth of ports (per way) +parameter bit_write_type = 9; // gives the number of bits that shares one write-enable; must divide evenly into array +parameter ways = 1; // number of ways + +// POWER PINS +inout gnd; +inout vdd; +inout vcs; + +// CLOCK and CLOCKCONTROL ports +input [0:`NCLK_WIDTH-1] nclk; +input rd_act; +input wr_act; +input sg_0; +input abst_sl_thold_0; +input ary_nsl_thold_0; +input time_sl_thold_0; +input repr_sl_thold_0; +input func_sl_force; +input func_sl_thold_0_b; +input g8t_clkoff_dc_b; +input ccflush_dc; +input scan_dis_dc_b; +input scan_diag_dc; +input g8t_d_mode_dc; +input [0:4] g8t_mpw1_dc_b; +input g8t_mpw2_dc_b; +input [0:4] g8t_delay_lclkr_dc; +input d_mode_dc; +input mpw1_dc_b; +input mpw2_dc_b; +input delay_lclkr_dc; + +// ABIST +input wr_abst_act; +input rd0_abst_act; +input [0:3] abist_di; +input abist_bw_odd; +input abist_bw_even; +input [0:addressbus_width-1] abist_wr_adr; +input [0:addressbus_width-1] abist_rd0_adr; +input tc_lbist_ary_wrt_thru_dc; +input abist_ena_1; +input abist_g8t_rd0_comp_ena; +input abist_raw_dc_b; +input [0:3] obs0_abist_cmp; + +// Scan +input abst_scan_in; +input time_scan_in; +input repr_scan_in; +input func_scan_in; +output abst_scan_out; +output time_scan_out; +output repr_scan_out; +output func_scan_out; + +// BOLT-ON +input lcb_bolt_sl_thold_0; +input pc_bo_enable_2; // general bolt-on enable +input pc_bo_reset; // reset +input pc_bo_unload; // unload sticky bits +input pc_bo_repair; // execute sticky bit decode +input pc_bo_shdata; // shift data for timing write and diag loop +input [0:1] pc_bo_select; // select for mask and hier writes +output [0:1] bo_pc_failout; // fail/no-fix reg +output [0:1] bo_pc_diagloop; +input tri_lcb_mpw1_dc_b; +input tri_lcb_mpw2_dc_b; +input tri_lcb_delay_lclkr_dc; +input tri_lcb_clkoff_dc_b; +input tri_lcb_act_dis_dc; + +// Write Ports +input write_enable; +input [0:addressbus_width-1] addr_wr; +input [0:port_bitwidth-1] data_in; + +// Read Ports +input [0:addressbus_width-1] addr_rd; +output [0:port_bitwidth-1] data_out; + +// tri_64x144_1r1w + +// Configuration Statement for NCsim +//for all:RAMB36 use entity unisim.RAMB36; + +parameter data_width = ((((port_bitwidth - 1)/36) + 1) * 36) - 1; +parameter rd_act_offset = 0; +parameter data_out_offset = rd_act_offset + 1; +parameter scan_right = data_out_offset + port_bitwidth - 1; + +wire [0:data_width-(data_width/9)-1] ramb_data_in; +wire [0:data_width/9] ramb_par_in; +wire [0:data_width-(data_width/9)-1] ramb_data_out; +wire [0:data_width/9] ramb_par_out; +wire [0:data_width-(data_width/9)-1] ramb_data_dummy; +wire [0:data_width/9] ramb_par_dummy; +wire [0:15] ramb_wr_addr; +wire [0:15] ramb_rd_addr; +wire [0:data_width] data_in_pad; +wire [0:data_width] data_out_pad; +wire [0:((port_bitwidth-1)/36)] cascadeoutlata; +wire [0:((port_bitwidth-1)/36)] cascadeoutlatb; +wire [0:((port_bitwidth-1)/36)] cascadeoutrega; +wire [0:((port_bitwidth-1)/36)] cascadeoutregb; +wire rd_act_d; +wire rd_act_q; +wire [0:port_bitwidth-1] data_out_d; +wire [0:port_bitwidth-1] data_out_q; + +wire tiup; +wire tidn; +wire [0:(((((port_bitwidth-1)/36)+1)*36)/9)-1] wrt_en; +wire act; +wire [0:scan_right] siv; +wire [0:scan_right] sov; + +(* analysis_not_referenced="true" *) +wire unused; + +generate begin + assign tiup = 1'b1; + assign tidn = 1'b0; + assign wrt_en = {(((((port_bitwidth-1)/36)+1)*36)/9){write_enable}}; + assign act = rd_act | wr_act; + assign rd_act_d = rd_act; + + assign ramb_wr_addr[0] = 1'b0; + assign ramb_wr_addr[11:15] = 5'b0; + assign ramb_rd_addr[0] = 1'b0; + assign ramb_rd_addr[11:15] = 5'b0; + + genvar addr; + for (addr = 0; addr < 10; addr = addr + 1) begin : padA0 + if (addr < 10 - addressbus_width) + begin + assign ramb_wr_addr[addr + 1] = 1'b0; + assign ramb_rd_addr[addr + 1] = 1'b0; + end + if (addr >= 10 - addressbus_width) + begin + assign ramb_wr_addr[addr + 1] = addr_wr[addr - (10 - addressbus_width)]; + assign ramb_rd_addr[addr + 1] = addr_rd[addr - (10 - addressbus_width)]; + end + end + + // PORTA => Used for Writing + // PORTB => Used for Reading + genvar arr; + for (arr = 0; arr <= (port_bitwidth - 1)/36; arr = arr + 1) + begin : padD0 + genvar b; + for (b = 0; b < 36; b = b + 1) + begin : numBit + if ((arr * 36) + b < port_bitwidth) + begin + assign data_in_pad[(arr * 36) + b] = data_in[(arr * 36) + b]; + end + if ((arr * 36) + b >= port_bitwidth) + begin + assign data_in_pad[(arr * 36) + b] = 1'b0; + end + end + end + + genvar bb; + for (bb = 0; bb <= (data_width)/9; bb = bb + 1) + begin : dInFixUp + assign ramb_data_in[bb * 8:(bb * 8) + 7] = data_in_pad[(bb * 8) + bb:(bb * 8) + 7 + bb]; + assign ramb_par_in[bb] = data_in_pad[(bb * 8) + bb + 8]; + end + + for (bb = 0; bb <= (data_width)/9; bb = bb + 1) + begin : dOutFixUp + assign data_out_pad[(bb * 8) + bb:(bb * 8) + 7 + bb] = ramb_data_out[bb * 8:(bb * 8) + 7]; + assign data_out_pad[(bb * 8) + bb + 8] = ramb_par_out[bb]; + end + + genvar anum; + for (anum = 0; anum <= (port_bitwidth - 1)/36; anum = anum + 1) + begin : arrNum + + RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WRITE_WIDTH_A(36), .WRITE_WIDTH_B(36), .WRITE_MODE_A("READ_FIRST"), .WRITE_MODE_B("READ_FIRST")) ARR( + .CASCADEOUTLATA(cascadeoutlata[anum]), + .CASCADEOUTLATB(cascadeoutlatb[anum]), + .CASCADEOUTREGA(cascadeoutrega[anum]), + .CASCADEOUTREGB(cascadeoutregb[anum]), + .DOA(ramb_data_dummy[(32 * anum):31 + (32 * anum)]), + .DOB(ramb_data_out[(32 * anum):31 + (32 * anum)]), + .DOPA(ramb_par_dummy[(4 * anum):3 + (4 * anum)]), + .DOPB(ramb_par_out[(4 * anum):3 + (4 * anum)]), + .ADDRA(ramb_wr_addr), + .ADDRB(ramb_rd_addr), + .CASCADEINLATA(1'b0), + .CASCADEINLATB(1'b0), + .CASCADEINREGA(1'b0), + .CASCADEINREGB(1'b0), + .CLKA(nclk[0]), + .CLKB(nclk[0]), + .DIA(ramb_data_in[(32 * anum):31 + (32 * anum)]), + .DIB(32'b0), + .DIPA(ramb_par_in[(4 * anum):3 + (4 * anum)]), + .DIPB(4'b0), + .ENA(act), + .ENB(act), + .REGCEA(1'b0), + .REGCEB(1'b0), + .SSRA(nclk[1]), //sreset + .SSRB(nclk[1]), + .WEA(wrt_en[anum * 4:anum * 4 + 3]), + .WEB(4'b0) //' + ); + end + assign data_out_d = data_out_pad[0:port_bitwidth - 1]; + assign data_out = data_out_q; + + assign abst_scan_out = tidn; + assign time_scan_out = tidn; + assign repr_scan_out = tidn; + assign bo_pc_failout = 2'b00; + assign bo_pc_diagloop = 2'b00; +end +endgenerate + +assign unused = | { + cascadeoutlata , + cascadeoutlatb , + cascadeoutrega , + cascadeoutregb , + ramb_data_dummy , + ramb_par_dummy , + nclk[2:`NCLK_WIDTH-1] , + gnd , + vdd , + vcs , + sg_0 , + abst_sl_thold_0 , + ary_nsl_thold_0 , + time_sl_thold_0 , + repr_sl_thold_0 , + g8t_clkoff_dc_b , + ccflush_dc , + scan_dis_dc_b , + scan_diag_dc , + g8t_d_mode_dc , + g8t_mpw1_dc_b , + g8t_mpw2_dc_b , + g8t_delay_lclkr_dc , + wr_abst_act , + rd0_abst_act , + abist_di , + abist_bw_odd , + abist_bw_even , + abist_wr_adr , + abist_rd0_adr , + tc_lbist_ary_wrt_thru_dc , + abist_ena_1 , + abist_g8t_rd0_comp_ena , + abist_raw_dc_b , + obs0_abist_cmp , + abst_scan_in , + time_scan_in , + repr_scan_in , + lcb_bolt_sl_thold_0 , + pc_bo_enable_2 , + pc_bo_reset , + pc_bo_unload , + pc_bo_repair , + pc_bo_shdata , + pc_bo_select , + tri_lcb_mpw1_dc_b , + tri_lcb_mpw2_dc_b , + tri_lcb_delay_lclkr_dc , + tri_lcb_clkoff_dc_b , + tri_lcb_act_dis_dc }; + +// #################################################### +// Registers +// #################################################### +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rd_act_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rd_act_offset]), + .scout(sov[rd_act_offset]), + .din(rd_act_d), + .dout(rd_act_q) +); + +tri_rlmreg_p #(.WIDTH(port_bitwidth), .INIT(0), .NEEDS_SRESET(1)) data_out_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rd_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[data_out_offset:data_out_offset + port_bitwidth - 1]), + .scout(sov[data_out_offset:data_out_offset + port_bitwidth - 1]), + .din(data_out_d), + .dout(data_out_q) +); + +assign siv[0:scan_right] = {sov[1:scan_right], func_scan_in}; +assign func_scan_out = sov[0]; + +endmodule diff --git a/dev/verilog/trilib/tri_64x34_8w_1r1w.v b/dev/verilog/trilib/tri_64x34_8w_1r1w.v new file mode 100755 index 0000000..b7efe3e --- /dev/null +++ b/dev/verilog/trilib/tri_64x34_8w_1r1w.v @@ -0,0 +1,621 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILENAME : tri_64x34_8w_1r1w.vhdl +// *! DESCRIPTION : 32 entry x 35 bit x 8 way array +// *! +// *!**************************************************************** + +`include "tri_a2o.vh" + +module tri_64x34_8w_1r1w( + gnd, + vdd, + vcs, + nclk, + rd_act, + wr_act, + sg_0, + abst_sl_thold_0, + ary_nsl_thold_0, + time_sl_thold_0, + repr_sl_thold_0, + func_sl_force, + func_sl_thold_0_b, + g8t_clkoff_dc_b, + ccflush_dc, + scan_dis_dc_b, + scan_diag_dc, + g8t_d_mode_dc, + g8t_mpw1_dc_b, + g8t_mpw2_dc_b, + g8t_delay_lclkr_dc, + d_mode_dc, + mpw1_dc_b, + mpw2_dc_b, + delay_lclkr_dc, + wr_abst_act, + rd0_abst_act, + abist_di, + abist_bw_odd, + abist_bw_even, + abist_wr_adr, + abist_rd0_adr, + tc_lbist_ary_wrt_thru_dc, + abist_ena_1, + abist_g8t_rd0_comp_ena, + abist_raw_dc_b, + obs0_abist_cmp, + abst_scan_in, + time_scan_in, + repr_scan_in, + func_scan_in, + abst_scan_out, + time_scan_out, + repr_scan_out, + func_scan_out, + lcb_bolt_sl_thold_0, + pc_bo_enable_2, + pc_bo_reset, + pc_bo_unload, + pc_bo_repair, + pc_bo_shdata, + pc_bo_select, + bo_pc_failout, + bo_pc_diagloop, + tri_lcb_mpw1_dc_b, + tri_lcb_mpw2_dc_b, + tri_lcb_delay_lclkr_dc, + tri_lcb_clkoff_dc_b, + tri_lcb_act_dis_dc, + write_enable, + way, + addr_wr, + data_in, + addr_rd_01, + addr_rd_23, + addr_rd_45, + addr_rd_67, + data_out +); +parameter addressable_ports = 64; // number of addressable register in this array +parameter addressbus_width = 6; // width of the bus to address all ports (2^addressbus_width >= addressable_ports) +parameter port_bitwidth = 34; // bitwidth of ports +parameter ways = 8; // number of ways +// POWER PINS +inout gnd; +inout vdd; +inout vcs; + +// CLOCK and CLOCKCONTROL ports +input [0:`NCLK_WIDTH-1] nclk; +input rd_act; +input wr_act; +input sg_0; +input abst_sl_thold_0; +input ary_nsl_thold_0; +input time_sl_thold_0; +input repr_sl_thold_0; +input func_sl_force; +input func_sl_thold_0_b; +input g8t_clkoff_dc_b; +input ccflush_dc; +input scan_dis_dc_b; +input scan_diag_dc; +input g8t_d_mode_dc; +input [0:4] g8t_mpw1_dc_b; +input g8t_mpw2_dc_b; +input [0:4] g8t_delay_lclkr_dc; +input d_mode_dc; +input mpw1_dc_b; +input mpw2_dc_b; +input delay_lclkr_dc; + +// ABIST +input wr_abst_act; +input rd0_abst_act; +input [0:3] abist_di; +input abist_bw_odd; +input abist_bw_even; +input [0:addressbus_width-1] abist_wr_adr; +input [0:addressbus_width-1] abist_rd0_adr; +input tc_lbist_ary_wrt_thru_dc; +input abist_ena_1; +input abist_g8t_rd0_comp_ena; +input abist_raw_dc_b; +input [0:3] obs0_abist_cmp; + +// SCAN +input abst_scan_in; +input time_scan_in; +input repr_scan_in; +input func_scan_in; +output abst_scan_out; +output time_scan_out; +output repr_scan_out; +output func_scan_out; + +// BOLT-ON +input lcb_bolt_sl_thold_0; +input pc_bo_enable_2; // general bolt-on enable +input pc_bo_reset; // reset +input pc_bo_unload; // unload sticky bits +input pc_bo_repair; // execute sticky bit decode +input pc_bo_shdata; // shift data for timing write and diag loop +input [0:3] pc_bo_select; // select for mask and hier writes +output [0:3] bo_pc_failout; // fail/no-fix reg +output [0:3] bo_pc_diagloop; +input tri_lcb_mpw1_dc_b; +input tri_lcb_mpw2_dc_b; +input tri_lcb_delay_lclkr_dc; +input tri_lcb_clkoff_dc_b; +input tri_lcb_act_dis_dc; + +// Write Ports +input [0:3] write_enable; +input [0:ways-1] way; +input [0:addressbus_width-1] addr_wr; +input [0:port_bitwidth-1] data_in; + +// Read Ports +input [0:addressbus_width-1] addr_rd_01; +input [0:addressbus_width-1] addr_rd_23; +input [0:addressbus_width-1] addr_rd_45; +input [0:addressbus_width-1] addr_rd_67; +output [0:port_bitwidth*ways-1] data_out; + +// tri_64x34_8w_1r1w +parameter ramb_base_addr = 16; +parameter dataWidth = ((((port_bitwidth - 1)/36) + 1) * 36) - 1; +parameter numBytes = (dataWidth/9); + +// Configuration Statement for NCsim +//for all:RAMB16_S36_S36 use entity unisim.RAMB16_S36_S36; +parameter rd_act_offset = 0; +parameter data_out_offset = rd_act_offset + 1; +parameter scan_right = data_out_offset + (ways*port_bitwidth) - 1; + +wire [0:35] ramb_data_in; +wire [0:35] ramb_data_p0_out[0:ways-1]; +wire [0:(dataWidth+1)*ways-1] ramb_data_p0_concat; +wire [0:ramb_base_addr-1] ramb_addr_rd1; +wire [0:ramb_base_addr-1] ramb_addr_wr_rd0; + +wire [0:ramb_base_addr-1] rd_addr0; +wire [0:ramb_base_addr-1] wr_addr; +wire write_en; +wire [0:3] write_enable_way[0:ways-1]; +wire [0:(dataWidth-numBytes)-1] arr_data_in; +wire [0:numBytes] arr_par_in; +wire [0:(dataWidth-numBytes)-1] arr_data_out[0:ways-1]; +wire [0:numBytes] arr_par_out[0:ways-1]; +wire [0:dataWidth] arr_data_out_pad[0:ways-1]; +wire [0:(dataWidth+1)*ways-1] arr_data_concat; +wire [0:port_bitwidth*ways-1] data_out_d; +wire [0:port_bitwidth*ways-1] data_out_q; +wire [0:ways-1] cascadeoutlata; +wire [0:ways-1] cascadeoutlatb; +wire [0:ways-1] cascadeoutrega; +wire [0:ways-1] cascadeoutregb; +wire rd_act_d; +wire rd_act_q; + +(* analysis_not_referenced="true" *) +wire unused; +wire tiup; +wire [0:35] tidn; +wire [0:scan_right] siv; +wire [0:scan_right] sov; + +generate begin + + assign tiup = 1'b1; + assign tidn = 36'b0; + + // Data Generate + genvar t; + for (t = 0; t < 36; t = t + 1) + begin : addr_calc + if (t < 35 - (port_bitwidth - 1)) + begin + assign ramb_data_in[t] = 1'b0; + end + if (t >= 35 - (port_bitwidth - 1)) + begin + assign ramb_data_in[t] = data_in[t - (35 - (port_bitwidth - 1))]; + end + end + + genvar bb; + for (bb = 0; bb <= numBytes; bb = bb + 1) begin : dFixUp + assign arr_data_in[bb*8:(bb*8)+7] = ramb_data_in[(bb * 8)+bb:(((bb*8)+7)+bb)]; + assign arr_par_in[bb] = ramb_data_in[(((bb*8)+bb)+8)]; + genvar numWays; + for (numWays=0; numWays= 9 - addressbus_width) begin + assign rd_addr0[t+2] = addr_rd_01[t - (9 - addressbus_width)]; + assign wr_addr[t+2] = addr_wr[t - (9 - addressbus_width)]; + end + end + + genvar numWays; + for (numWays=0; numWays 16K L1D$, 15 => 32K L1D$ +`define CL_SIZE 6 // 6 => 64B CLINE, 7 => 128B CLINE +`define LMQ_ENTRIES 8 +`define LMQ_ENTRIES_ENC 3 +`define LGQ_ENTRIES 8 +`define AXU_SPARE_ENC 3 +`define RV_FX0_ENTRIES 12 +`define RV_FX1_ENTRIES 12 +`define RV_LQ_ENTRIES 16 +`define RV_AXU0_ENTRIES 12 +`define RV_AXU1_ENTRIES 0 +`define RV_FX0_ENTRIES_ENC 4 +`define RV_FX1_ENTRIES_ENC 4 +`define RV_LQ_ENTRIES_ENC 4 +`define RV_AXU0_ENTRIES_ENC 4 +`define RV_AXU1_ENTRIES_ENC 1 +`define UCODE_ENTRIES 8 +`define UCODE_ENTRIES_ENC 3 +`define FXU1_ENABLE 1 +`define TYPE_WIDTH 3 +`define IBUFF_INSTR_WIDTH 70 +`define IBUFF_IFAR_WIDTH 20 +`define IBUFF_DEPTH 16 +`define PF_IAR_BITS 12 // number of IAR bits used by prefetch +`define FXU0_PIPE_START 1 +`define FXU0_PIPE_END 8 +`define FXU1_PIPE_START 1 +`define FXU1_PIPE_END 5 +`define LQ_LOAD_PIPE_START 4 +`define LQ_LOAD_PIPE_END 8 +`define LQ_REL_PIPE_START 2 +`define LQ_REL_PIPE_END 4 +`define LOAD_CREDITS 8 +`define STORE_CREDITS 4 +`define IUQ_ENTRIES 4 // Instruction Fetch Queue Size +`define MMQ_ENTRIES 2 // MMU Queue Size +`define CR_WIDTH 4 +`define BUILD_PFETCH 1 // 1=> include pfetch in the build, 0=> build without pfetch +`define PF_IFAR_WIDTH 12 +`define PFETCH_INITIAL_DEPTH 0 // the initial value for the SPR that determines how many lines to prefetch +`define PFETCH_Q_SIZE_ENC 3 // number of bits to address queue size (3 => 8 entries, 4 => 16 entries) +`define PFETCH_Q_SIZE 8 // number of entries +`define INCLUDE_IERAT_BYPASS 1 // 0 => Removes IERAT Bypass logic, 1=> includes (power savings) +`define XER_WIDTH 10 + +//wtf: change for verilatorsim - didnt help +//`define INIT_BHT 1 // 0=> array init time set to 16 clocks, 1=> increased to 512 to init BHT +//`define INIT_IUCR0 16'h00FA // BP enabled +`define INIT_BHT 0 // 0=> array init time set to 16 clocks, 1=> increased to 512 to init BHT +`define INIT_IUCR0 16'h0000 // BP disabled + +`define INIT_MASK 2'b10 +`define RELQ_INCLUDE 0 // Reload Queue Included + +`define G_BRANCH_LEN `EFF_IFAR_WIDTH + 1 + 1 + `EFF_IFAR_WIDTH + 3 + 18 + 1 + +//wtf: add completion stuff +/* + assign spr_cpcr0_fx0_cnt = cpcr0_l2[35:39]; + assign spr_cpcr0_fx1_cnt = cpcr0_l2[43:47]; + assign spr_cpcr0_lq_cnt = cpcr0_l2[51:55]; + assign spr_cpcr0_sq_cnt = cpcr0_l2[59:63]; +*/ +`define INIT_CPCR0 32'h0C0C100C // 000a aaaa 000b bbbb 000c cccc 000d dddd watermarks: a=fx0 b=fx1 c=ls d=sq ---- um p.543 wrong!; was this in vlog: hex 0C0C100C = 202117132 +//`define INIT_CPCR0 32'h01010201 // 1/1/2/1 +/* + assign spr_cpcr1_fu0_cnt = cpcr1_l2[43:47]; + assign spr_cpcr1_fu1_cnt = cpcr1_l2[51:55]; +*/ +`define INIT_CPCR1 32'h000C0C00 // 0000 0000 000a aaaa 000b bbbb 0000 0000 credits: a=fx0 b=fx1 c=ls d=sq ---- um p.544 wrong!; was this in vlog: hex 000C0C00 = 789504 +//`define INIT_CPCR1 32'h00010100 // 1/1 + +// IERAT boot config entry values +`define IERAT_BCFG_EPN_0TO15 0 +`define IERAT_BCFG_EPN_16TO31 0 +`define IERAT_BCFG_EPN_32TO47 (2 ** 16) - 1 // 1 for 64K, 65535 for 4G +`define IERAT_BCFG_EPN_48TO51 (2 ** 4) - 1 // 15 for 64K or 4G +`define IERAT_BCFG_RPN_22TO31 0 // (2 ** 10) - 1 for x3ff +`define IERAT_BCFG_RPN_32TO47 (2 ** 16) - 1 // 1 for 64K, 8181 for 512M, 65535 for 4G +`define IERAT_BCFG_RPN_48TO51 (2 ** 4) - 1 // 15 for 64K or 4G +`define IERAT_BCFG_RPN2_32TO47 0 // 0 to match dd1 hardwired value; (2**16)-1 for same 64K page +`define IERAT_BCFG_RPN2_48TO51 0 // 0 to match dd1 hardwired value; (2**4)-2 for adjacent 4K page +`define IERAT_BCFG_ATTR 0 // u0-u3, endian + +// DERAT boot config entry values +`define DERAT_BCFG_EPN_0TO15 0 +`define DERAT_BCFG_EPN_16TO31 0 +`define DERAT_BCFG_EPN_32TO47 (2 ** 16) - 1 // 1 for 64K, 65535 for 4G +`define DERAT_BCFG_EPN_48TO51 (2 ** 4) - 1 // 15 for 64K or 4G +`define DERAT_BCFG_RPN_22TO31 0 // (2 ** 10) - 1 for x3ff +`define DERAT_BCFG_RPN_32TO47 (2 ** 16) - 1 // 1 for 64K, 8191 for 512M, 65535 for 4G +`define DERAT_BCFG_RPN_48TO51 (2 ** 4) - 1 // 15 for 64K or 4G +`define DERAT_BCFG_RPN2_32TO47 0 // 0 to match dd1 hardwired value; (2**16)-1 for same 64K page +`define DERAT_BCFG_RPN2_48TO51 0 // 0 to match dd1 hardwired value; (2**4)-2 for adjacent 4K page +`define DERAT_BCFG_ATTR 0 // u0-u3, endian + +// Do NOT add any defines below this line +`endif //_tri_a2o_vh_ diff --git a/dev/verilog/trilib/tri_addrcmp.v b/dev/verilog/trilib/tri_addrcmp.v new file mode 100755 index 0000000..965d970 --- /dev/null +++ b/dev/verilog/trilib/tri_addrcmp.v @@ -0,0 +1,101 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: Address Decoder +// +//***************************************************************************** + +module tri_addrcmp( + enable_lsb, + d0, + d1, + eq +); + + input enable_lsb; // when "0" the LSB is disabled + input [0:35] d0; + input [0:35] d1; + output eq; + + // tri_addrcmp + + parameter tiup = 1'b1; + parameter tidn = 1'b0; + + wire [0:35] eq01_b; + wire [0:18] eq02; + wire [0:9] eq04_b; + wire [0:4] eq08; + wire [0:1] eq24_b; + + assign eq01_b[0:35] = (d0[0:35] ^ d1[0:35]); + + assign eq02[0] = (~(eq01_b[0] | eq01_b[1])); + assign eq02[1] = (~(eq01_b[2] | eq01_b[3])); + assign eq02[2] = (~(eq01_b[4] | eq01_b[5])); + assign eq02[3] = (~(eq01_b[6] | eq01_b[7])); + assign eq02[4] = (~(eq01_b[8] | eq01_b[9])); + assign eq02[5] = (~(eq01_b[10] | eq01_b[11])); + assign eq02[6] = (~(eq01_b[12] | eq01_b[13])); + assign eq02[7] = (~(eq01_b[14] | eq01_b[15])); + assign eq02[8] = (~(eq01_b[16] | eq01_b[17])); + assign eq02[9] = (~(eq01_b[18] | eq01_b[19])); + assign eq02[10] = (~(eq01_b[20] | eq01_b[21])); + assign eq02[11] = (~(eq01_b[22] | eq01_b[23])); + assign eq02[12] = (~(eq01_b[24] | eq01_b[25])); + assign eq02[13] = (~(eq01_b[26] | eq01_b[27])); + assign eq02[14] = (~(eq01_b[28] | eq01_b[29])); + assign eq02[15] = (~(eq01_b[30] | eq01_b[31])); + assign eq02[16] = (~(eq01_b[32] | eq01_b[33])); + assign eq02[17] = (~(eq01_b[34])); + assign eq02[18] = (~(eq01_b[35] & enable_lsb)); + + assign eq04_b[0] = (~(eq02[0] & eq02[1])); + assign eq04_b[1] = (~(eq02[2] & eq02[3])); + assign eq04_b[2] = (~(eq02[4] & eq02[5])); + assign eq04_b[3] = (~(eq02[6] & eq02[7])); + assign eq04_b[4] = (~(eq02[8] & eq02[9])); + assign eq04_b[5] = (~(eq02[10] & eq02[11])); + assign eq04_b[6] = (~(eq02[12] & eq02[13])); + assign eq04_b[7] = (~(eq02[14] & eq02[15])); + assign eq04_b[8] = (~(eq02[16] & eq02[17])); + assign eq04_b[9] = (~(eq02[18])); + + assign eq08[0] = (~(eq04_b[0] | eq04_b[1])); + assign eq08[1] = (~(eq04_b[2] | eq04_b[3])); + assign eq08[2] = (~(eq04_b[4] | eq04_b[5])); + assign eq08[3] = (~(eq04_b[6] | eq04_b[7])); + assign eq08[4] = (~(eq04_b[8] | eq04_b[9])); + + assign eq24_b[0] = (~(eq08[0] & eq08[1] & eq08[2])); + assign eq24_b[1] = (~(eq08[3] & eq08[4])); + + assign eq = (~(eq24_b[0] | eq24_b[1])); // output +endmodule diff --git a/dev/verilog/trilib/tri_agecmp.v b/dev/verilog/trilib/tri_agecmp.v new file mode 100755 index 0000000..dd41064 --- /dev/null +++ b/dev/verilog/trilib/tri_agecmp.v @@ -0,0 +1,60 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: Prioritizer +// +//***************************************************************************** + +module tri_agecmp( + a, + b, + a_newer_b +); + parameter SIZE = 8; + + input [0:SIZE-1] a; + input [0:SIZE-1] b; + output a_newer_b; + + // tri_agecmp + + wire a_lt_b; + wire a_gte_b; + wire cmp_sel; + + assign a_lt_b = (a[1:SIZE - 1] < b[1:SIZE - 1]) ? 1'b1 : + 1'b0; + + assign a_gte_b = (~a_lt_b); + + assign cmp_sel = a[0] ~^ b[0]; + + assign a_newer_b = (a_lt_b & (~cmp_sel)) | (a_gte_b & cmp_sel); +endmodule diff --git a/dev/verilog/trilib/tri_aoi21.v b/dev/verilog/trilib/tri_aoi21.v new file mode 100755 index 0000000..0038adc --- /dev/null +++ b/dev/verilog/trilib/tri_aoi21.v @@ -0,0 +1,68 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILENAME : tri_nand2.v +// *! DESCRIPTION : Three input, AOI21 gate +// *! +// *!**************************************************************** + +`include "tri_a2o.vh" + +module tri_aoi21( + y, + a0, + a1, + b0 +); + parameter WIDTH = 1; + parameter BTR = "AOI21_X2M_NONE"; //Specify full BTR name, else let tool select + output [0:WIDTH-1] y; + input [0:WIDTH-1] a0; + input [0:WIDTH-1] a1; + input [0:WIDTH-1] b0; + + // tri_aoi21 + genvar i; + wire [0:WIDTH-1] outA; + + generate + begin : t + for (i = 0; i < WIDTH; i = i + 1) + begin : w + + and I0(outA[i], a0[i], a1[i]); + nor I2(y[i], outA[i], b0[i]); + + end // block: w + end + + endgenerate +endmodule diff --git a/dev/verilog/trilib/tri_aoi22.v b/dev/verilog/trilib/tri_aoi22.v new file mode 100755 index 0000000..729a54b --- /dev/null +++ b/dev/verilog/trilib/tri_aoi22.v @@ -0,0 +1,73 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILENAME : tri_aoi22.v +// *! DESCRIPTION : AOI22 gate +// *! +// *!**************************************************************** + +`include "tri_a2o.vh" + +module tri_aoi22( + y, + a0, + a1, + b0, + b1 +); + parameter WIDTH = 1; + parameter BTR = "AOI22_X2M_NONE"; //Specify full BTR name, else let tool select + output [0:WIDTH-1] y; + input [0:WIDTH-1] a0; + input [0:WIDTH-1] a1; + input [0:WIDTH-1] b0; + input [0:WIDTH-1] b1; + + // tri_aoi22 + genvar i; + wire [0:WIDTH-1] outA; + wire [0:WIDTH-1] outB; + + generate + begin : t + for (i = 0; i < WIDTH; i = i + 1) + begin : w + + and I0(outA[i], a0[i], a1[i]); + and I1(outB[i], b0[i], b1[i]); + nor I2(y[i], outA[i], outB[i]); + + + end // block: w + end + + endgenerate +endmodule diff --git a/dev/verilog/trilib/tri_aoi22_nlats_wlcb.v b/dev/verilog/trilib/tri_aoi22_nlats_wlcb.v new file mode 100755 index 0000000..9b8e8b6 --- /dev/null +++ b/dev/verilog/trilib/tri_aoi22_nlats_wlcb.v @@ -0,0 +1,145 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILENAME : tri_aoi22_nlats_wlcb.v +// *! DESCRIPTION : Multi-bit aoi22-latch, LCB included +// *! +// *!**************************************************************** + +`include "tri_a2o.vh" + +module tri_aoi22_nlats_wlcb( + vd, + gd, + nclk, + act, + force_t, + thold_b, + d_mode, + sg, + delay_lclkr, + mpw1_b, + mpw2_b, + scin, + scout, + a1, + a2, + b1, + b2, + qb +); + + parameter WIDTH = 4; + parameter OFFSET = 0; //starting bit + parameter INIT = 0; // will be converted to the least signficant + // 31 bits of init_v + parameter IBUF = 1'b0; //inverted latch IOs, if set to true. + parameter DUALSCAN = ""; // if "S", marks data ports as scan for Moebius + parameter NEEDS_SRESET = 1; // for inferred latches + parameter L2_LATCH_TYPE = 2; //L2_LATCH_TYPE = slave_latch; + //0=master_latch,1=L1,2=slave_latch,3=L2,4=flush_latch,5=L4 + parameter SYNTHCLONEDLATCH = ""; + parameter BTR = "NLL0001_X2_A12TH"; + + inout vd; + inout gd; + input [0:`NCLK_WIDTH-1] nclk; + input act; // 1: functional, 0: no clock + input force_t; // 1: force LCB active + input thold_b; // 1: functional, 0: no clock + input d_mode; // 1: disable pulse mode, 0: pulse mode + input sg; // 0: functional, 1: scan + input delay_lclkr; // 0: functional + input mpw1_b; // pulse width control bit + input mpw2_b; // pulse width control bit + input [OFFSET:OFFSET+WIDTH-1] scin; // scan in + output [OFFSET:OFFSET+WIDTH-1] scout; + input [OFFSET:OFFSET+WIDTH-1] a1; + input [OFFSET:OFFSET+WIDTH-1] a2; + input [OFFSET:OFFSET+WIDTH-1] b1; + input [OFFSET:OFFSET+WIDTH-1] b2; + output [OFFSET:OFFSET+WIDTH-1] qb; + + // tri_aoi22_nlats_wlcb + + parameter [0:WIDTH-1] init_v = INIT; + parameter [0:WIDTH-1] ZEROS = {WIDTH{1'b0}}; + + generate + begin + wire sreset; + wire [0:WIDTH-1] int_din; + wire [0:WIDTH-1] din; + reg [0:WIDTH-1] int_dout; + wire [0:WIDTH-1] vact; + wire [0:WIDTH-1] vact_b; + wire [0:WIDTH-1] vsreset; + wire [0:WIDTH-1] vsreset_b; + wire [0:WIDTH-1] vthold; + wire [0:WIDTH-1] vthold_b; + (* analysis_not_referenced="true" *) + wire unused; + + if (NEEDS_SRESET == 1) + begin : rst + assign sreset = nclk[1]; + end + if (NEEDS_SRESET != 1) + begin : no_rst + assign sreset = 1'b0; + end + + assign vsreset = {WIDTH{sreset}}; + assign vsreset_b = {WIDTH{~sreset}}; + + assign din = (a1 & a2) | (b1 & b2); // Output is inverted, so just AND-OR here + assign int_din = (vsreset_b & din) | (vsreset & init_v); + + assign vact = {WIDTH{act | force_t}}; + assign vact_b = {WIDTH{~(act | force_t)}}; + + assign vthold_b = {WIDTH{thold_b}}; + assign vthold = {WIDTH{~thold_b}}; + + + always @(posedge nclk[0]) + begin: l + int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout); + end + + assign qb = (~int_dout); + + assign scout = ZEROS; + + assign unused = d_mode | sg | delay_lclkr | mpw1_b | mpw2_b | vd | gd | (|nclk) | (|scin); + end + endgenerate +endmodule diff --git a/dev/verilog/trilib/tri_bht_1024x8_1r1w.v b/dev/verilog/trilib/tri_bht_1024x8_1r1w.v new file mode 100755 index 0000000..68fd3f1 --- /dev/null +++ b/dev/verilog/trilib/tri_bht_1024x8_1r1w.v @@ -0,0 +1,577 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// ********************************************************************* +// +// This is the ENTITY for tri_bht_1024x8_1r1w +// +// ********************************************************************* + +(* block_type="soft" *) +(* recursive_synthesis="2" *) +(* pin_default_power_domain="vdd" *) +(* pin_default_ground_domain ="gnd" *) + +`include "tri_a2o.vh" + +module tri_bht_1024x8_1r1w( + gnd, + vdd, + vcs, + nclk, + pc_iu_func_sl_thold_2, + pc_iu_sg_2, + pc_iu_time_sl_thold_2, + pc_iu_abst_sl_thold_2, + pc_iu_ary_nsl_thold_2, + pc_iu_repr_sl_thold_2, + pc_iu_bolt_sl_thold_2, + tc_ac_ccflush_dc, + tc_ac_scan_dis_dc_b, + clkoff_b, + scan_diag_dc, + act_dis, + d_mode, + delay_lclkr, + mpw1_b, + mpw2_b, + g8t_clkoff_b, + g8t_d_mode, + g8t_delay_lclkr, + g8t_mpw1_b, + g8t_mpw2_b, + func_scan_in, + time_scan_in, + abst_scan_in, + repr_scan_in, + func_scan_out, + time_scan_out, + abst_scan_out, + repr_scan_out, + pc_iu_abist_di_0, + pc_iu_abist_g8t_bw_1, + pc_iu_abist_g8t_bw_0, + pc_iu_abist_waddr_0, + pc_iu_abist_g8t_wenb, + pc_iu_abist_raddr_0, + pc_iu_abist_g8t1p_renb_0, + an_ac_lbist_ary_wrt_thru_dc, + pc_iu_abist_ena_dc, + pc_iu_abist_wl128_comp_ena, + pc_iu_abist_raw_dc_b, + pc_iu_abist_g8t_dcomp, + pc_iu_bo_enable_2, + pc_iu_bo_reset, + pc_iu_bo_unload, + pc_iu_bo_repair, + pc_iu_bo_shdata, + pc_iu_bo_select, + iu_pc_bo_fail, + iu_pc_bo_diagout, + r_act, + w_act, + r_addr, + w_addr, + data_in, + data_out0, + data_out1, + data_out2, + data_out3, + pc_iu_init_reset +); + // power pins + inout gnd; + inout vdd; + inout vcs; + + // clock and clockcontrol ports + input [0:`NCLK_WIDTH-1] nclk; + input pc_iu_func_sl_thold_2; + input pc_iu_sg_2; + input pc_iu_time_sl_thold_2; + input pc_iu_abst_sl_thold_2; + input pc_iu_ary_nsl_thold_2; + input pc_iu_repr_sl_thold_2; + input pc_iu_bolt_sl_thold_2; + input tc_ac_ccflush_dc; + input tc_ac_scan_dis_dc_b; + input clkoff_b; + input scan_diag_dc; + input act_dis; + input d_mode; + input delay_lclkr; + input mpw1_b; + input mpw2_b; + input g8t_clkoff_b; + input g8t_d_mode; + input [0:4] g8t_delay_lclkr; + input [0:4] g8t_mpw1_b; + input g8t_mpw2_b; + input func_scan_in; + input time_scan_in; + input abst_scan_in; + input repr_scan_in; + output func_scan_out; + output time_scan_out; + output abst_scan_out; + output repr_scan_out; + + input [0:3] pc_iu_abist_di_0; + input pc_iu_abist_g8t_bw_1; + input pc_iu_abist_g8t_bw_0; + input [3:9] pc_iu_abist_waddr_0; + input pc_iu_abist_g8t_wenb; + input [3:9] pc_iu_abist_raddr_0; + input pc_iu_abist_g8t1p_renb_0; + input an_ac_lbist_ary_wrt_thru_dc; + input pc_iu_abist_ena_dc; + input pc_iu_abist_wl128_comp_ena; + input pc_iu_abist_raw_dc_b; + input [0:3] pc_iu_abist_g8t_dcomp; + + // BOLT-ON + input pc_iu_bo_enable_2; // general bolt-on enable + input pc_iu_bo_reset; // reset + input pc_iu_bo_unload; // unload sticky bits + input pc_iu_bo_repair; // execute sticky bit decode + input pc_iu_bo_shdata; // shift data for timing write and diag loop + input pc_iu_bo_select; // select for mask and hier writes + output iu_pc_bo_fail; // fail/no-fix reg + output iu_pc_bo_diagout; + + // ports + input r_act; + input [0:3] w_act; + input [0:9] r_addr; + input [0:9] w_addr; + input [0:1] data_in; + output [0:1] data_out0; + output [0:1] data_out1; + output [0:1] data_out2; + + output [0:1] data_out3; + + input pc_iu_init_reset; + + //-------------------------- + // constants + //-------------------------- + + + parameter data_in_offset = 0; + parameter w_act_offset = data_in_offset + 2; + parameter r_act_offset = w_act_offset + 4; + parameter w_addr_offset = r_act_offset + 1; + parameter r_addr_offset = w_addr_offset + 10; + parameter data_out_offset = r_addr_offset + 10; + parameter reset_w_addr_offset = data_out_offset + 8; + parameter array_offset = reset_w_addr_offset + 9; + parameter scan_right = array_offset + 1 - 1; + + //-------------------------- + // signals + //-------------------------- + + wire pc_iu_func_sl_thold_1; + wire pc_iu_func_sl_thold_0; + wire pc_iu_func_sl_thold_0_b; + wire pc_iu_time_sl_thold_1; + wire pc_iu_time_sl_thold_0; + wire pc_iu_ary_nsl_thold_1; + wire pc_iu_ary_nsl_thold_0; + wire pc_iu_abst_sl_thold_1; + wire pc_iu_abst_sl_thold_0; + wire pc_iu_repr_sl_thold_1; + wire pc_iu_repr_sl_thold_0; + wire pc_iu_bolt_sl_thold_1; + wire pc_iu_bolt_sl_thold_0; + wire pc_iu_sg_1; + wire pc_iu_sg_0; + wire force_t; + + wire [0:scan_right] siv; + wire [0:scan_right] sov; + + wire tiup; + + wire [0:7] data_out_d; + wire [0:7] data_out_q; + + wire ary_w_en; + wire [0:8] ary_w_addr; + wire [0:15] ary_w_sel; + wire [0:15] ary_w_data; + + wire ary_r_en; + wire [0:8] ary_r_addr; + wire [0:15] ary_r_data; + + wire [0:7] data_out; + wire [0:3] write_thru; + + wire [0:1] data_in_d; + wire [0:1] data_in_q; + wire [0:3] w_act_d; + wire [0:3] w_act_q; + wire r_act_d; + wire r_act_q; + wire [0:9] w_addr_d; + wire [0:9] w_addr_q; + wire [0:9] r_addr_d; + wire [0:9] r_addr_q; + + wire lat_wi_act; + wire lat_ri_act; + wire lat_ro_act; + + wire reset_act; + wire [0:8] reset_w_addr_d; + wire [0:8] reset_w_addr_q; + + + assign tiup = 1'b1; + + assign reset_act = pc_iu_init_reset; + assign reset_w_addr_d[0:8] = reset_w_addr_q[0:8] + 9'b000000001; + + assign data_out0[0:1] = data_out_q[0:1]; + assign data_out1[0:1] = data_out_q[2:3]; + assign data_out2[0:1] = data_out_q[4:5]; + assign data_out3[0:1] = data_out_q[6:7]; + + assign ary_w_en = reset_act | (|(w_act[0:3]) & (~((w_addr[1:9] == r_addr[1:9]) & r_act == 1'b1))); + + assign ary_w_addr[0:8] = reset_act ? reset_w_addr_q[0:8] : w_addr[1:9]; + + assign ary_w_sel[0] = reset_act ? 1'b1 : w_act[0] & w_addr[0] == 1'b0; + assign ary_w_sel[1] = reset_act ? 1'b1 : w_act[0] & w_addr[0] == 1'b0; + assign ary_w_sel[2] = reset_act ? 1'b1 : w_act[1] & w_addr[0] == 1'b0; + assign ary_w_sel[3] = reset_act ? 1'b1 : w_act[1] & w_addr[0] == 1'b0; + assign ary_w_sel[4] = reset_act ? 1'b1 : w_act[2] & w_addr[0] == 1'b0; + assign ary_w_sel[5] = reset_act ? 1'b1 : w_act[2] & w_addr[0] == 1'b0; + assign ary_w_sel[6] = reset_act ? 1'b1 : w_act[3] & w_addr[0] == 1'b0; + assign ary_w_sel[7] = reset_act ? 1'b1 : w_act[3] & w_addr[0] == 1'b0; + assign ary_w_sel[8] = reset_act ? 1'b1 : w_act[0] & w_addr[0] == 1'b1; + assign ary_w_sel[9] = reset_act ? 1'b1 : w_act[0] & w_addr[0] == 1'b1; + assign ary_w_sel[10] = reset_act ? 1'b1 : w_act[1] & w_addr[0] == 1'b1; + assign ary_w_sel[11] = reset_act ? 1'b1 : w_act[1] & w_addr[0] == 1'b1; + assign ary_w_sel[12] = reset_act ? 1'b1 : w_act[2] & w_addr[0] == 1'b1; + assign ary_w_sel[13] = reset_act ? 1'b1 : w_act[2] & w_addr[0] == 1'b1; + assign ary_w_sel[14] = reset_act ? 1'b1 : w_act[3] & w_addr[0] == 1'b1; + assign ary_w_sel[15] = reset_act ? 1'b1 : w_act[3] & w_addr[0] == 1'b1; + + assign ary_w_data[0:15] = reset_act ? 16'b0000000000000000: + {(data_in[0:1] ^ `INIT_MASK), (data_in[0:1] ^ `INIT_MASK), (data_in[0:1] ^ `INIT_MASK), (data_in[0:1] ^ `INIT_MASK), (data_in[0:1] ^ `INIT_MASK), (data_in[0:1] ^ `INIT_MASK), (data_in[0:1] ^ `INIT_MASK), (data_in[0:1] ^ `INIT_MASK)}; + + assign ary_r_en = r_act; + + assign ary_r_addr[0:8] = r_addr[1:9]; + + assign data_out[0:7] = (r_addr_q[0] == 1'b0 ? ary_r_data[0:7] ^ ({`INIT_MASK, `INIT_MASK, `INIT_MASK, `INIT_MASK}) : 8'b00000000 ) | (r_addr_q[0] == 1'b1 ? ary_r_data[8:15] ^ ({`INIT_MASK, `INIT_MASK, `INIT_MASK, `INIT_MASK}) : 8'b00000000 ); + + //write through support + + assign data_in_d[0:1] = data_in[0:1]; + assign w_act_d[0:3] = w_act[0:3]; + assign r_act_d = r_act; + assign w_addr_d[0:9] = w_addr[0:9]; + assign r_addr_d[0:9] = r_addr[0:9]; + + assign write_thru[0:3] = ((w_addr_q[0:9] == r_addr_q[0:9]) & r_act_q == 1'b1) ? w_act_q[0:3] : + 4'b0000; + + assign data_out_d[0:1] = (write_thru[0] == 1'b1) ? data_in_q[0:1] : + data_out[0:1]; + assign data_out_d[2:3] = (write_thru[1] == 1'b1) ? data_in_q[0:1] : + data_out[2:3]; + assign data_out_d[4:5] = (write_thru[2] == 1'b1) ? data_in_q[0:1] : + data_out[4:5]; + assign data_out_d[6:7] = (write_thru[3] == 1'b1) ? data_in_q[0:1] : + data_out[6:7]; + + //latch acts + assign lat_wi_act = |(w_act[0:3]); + assign lat_ri_act = r_act; + assign lat_ro_act = r_act_q; + + //----------------------------------------------- + // array + //----------------------------------------------- + + + + tri_512x16_1r1w_1 bht0( + .gnd(gnd), + .vdd(vdd), + .vcs(vcs), + .nclk(nclk), + + .rd_act(ary_r_en), + .wr_act(ary_w_en), + + .lcb_d_mode_dc(g8t_d_mode), + .lcb_clkoff_dc_b(g8t_clkoff_b), + .lcb_mpw1_dc_b(g8t_mpw1_b), + .lcb_mpw2_dc_b(g8t_mpw2_b), + .lcb_delay_lclkr_dc(g8t_delay_lclkr), + .ccflush_dc(tc_ac_ccflush_dc), + .scan_dis_dc_b(tc_ac_scan_dis_dc_b), + .scan_diag_dc(scan_diag_dc), + .func_scan_in(siv[array_offset]), + .func_scan_out(sov[array_offset]), + + .lcb_sg_0(pc_iu_sg_0), + .lcb_sl_thold_0_b(pc_iu_func_sl_thold_0_b), + .lcb_time_sl_thold_0(pc_iu_time_sl_thold_0), + .lcb_abst_sl_thold_0(pc_iu_abst_sl_thold_0), + .lcb_ary_nsl_thold_0(pc_iu_ary_nsl_thold_0), + .lcb_repr_sl_thold_0(pc_iu_repr_sl_thold_0), + .time_scan_in(time_scan_in), + .time_scan_out(time_scan_out), + .abst_scan_in(abst_scan_in), + .abst_scan_out(abst_scan_out), + .repr_scan_in(repr_scan_in), + .repr_scan_out(repr_scan_out), + + .abist_di(pc_iu_abist_di_0), + .abist_bw_odd(pc_iu_abist_g8t_bw_1), + .abist_bw_even(pc_iu_abist_g8t_bw_0), + .abist_wr_adr(pc_iu_abist_waddr_0), + .wr_abst_act(pc_iu_abist_g8t_wenb), + .abist_rd0_adr(pc_iu_abist_raddr_0), + .rd0_abst_act(pc_iu_abist_g8t1p_renb_0), + .tc_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc), + .abist_ena_1(pc_iu_abist_ena_dc), + .abist_g8t_rd0_comp_ena(pc_iu_abist_wl128_comp_ena), + .abist_raw_dc_b(pc_iu_abist_raw_dc_b), + .obs0_abist_cmp(pc_iu_abist_g8t_dcomp), + + .lcb_bolt_sl_thold_0(pc_iu_bolt_sl_thold_0), + .pc_bo_enable_2(pc_iu_bo_enable_2), + .pc_bo_reset(pc_iu_bo_reset), + .pc_bo_unload(pc_iu_bo_unload), + .pc_bo_repair(pc_iu_bo_repair), + .pc_bo_shdata(pc_iu_bo_shdata), + .pc_bo_select(pc_iu_bo_select), + .bo_pc_failout(iu_pc_bo_fail), + .bo_pc_diagloop(iu_pc_bo_diagout), + + .tri_lcb_mpw1_dc_b(mpw1_b), + .tri_lcb_mpw2_dc_b(mpw2_b), + .tri_lcb_delay_lclkr_dc(delay_lclkr), + .tri_lcb_clkoff_dc_b(clkoff_b), + .tri_lcb_act_dis_dc(act_dis), + + .bw(ary_w_sel), + .wr_adr(ary_w_addr), + .rd_adr(ary_r_addr), + .di(ary_w_data), + .dout(ary_r_data) + ); + + //----------------------------------------------- + // latches + //----------------------------------------------- + + + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) data_in_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lat_wi_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[data_in_offset:data_in_offset + 2 - 1]), + .scout(sov[data_in_offset:data_in_offset + 2 - 1]), + .din(data_in_d), + .dout(data_in_q) + ); + + + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) w_act_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[w_act_offset:w_act_offset + 4 - 1]), + .scout(sov[w_act_offset:w_act_offset + 4 - 1]), + .din(w_act_d), + .dout(w_act_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) r_act_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[r_act_offset]), + .scout(sov[r_act_offset]), + .din(r_act_d), + .dout(r_act_q) + ); + + + tri_rlmreg_p #(.WIDTH(10), .INIT(0)) w_addr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lat_wi_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[w_addr_offset:w_addr_offset + 10 - 1]), + .scout(sov[w_addr_offset:w_addr_offset + 10 - 1]), + .din(w_addr_d), + .dout(w_addr_q) + ); + + + tri_rlmreg_p #(.WIDTH(10), .INIT(0)) r_addr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lat_ri_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[r_addr_offset:r_addr_offset + 10 - 1]), + .scout(sov[r_addr_offset:r_addr_offset + 10 - 1]), + .din(r_addr_d), + .dout(r_addr_q) + ); + + + tri_rlmreg_p #(.WIDTH(8), .INIT(0)) data_out_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lat_ro_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[data_out_offset:data_out_offset + 8 - 1]), + .scout(sov[data_out_offset:data_out_offset + 8 - 1]), + .din(data_out_d), + .dout(data_out_q) + ); + + tri_rlmreg_p #(.WIDTH(9), .INIT(0)) reset_w_addr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(reset_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[reset_w_addr_offset:reset_w_addr_offset + 9 - 1]), + .scout(sov[reset_w_addr_offset:reset_w_addr_offset + 9 - 1]), + .din(reset_w_addr_d), + .dout(reset_w_addr_q) + ); + + //----------------------------------------------- + // pervasive + //----------------------------------------------- + + + tri_plat #(.WIDTH(7)) perv_2to1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + .din({pc_iu_func_sl_thold_2, pc_iu_sg_2, pc_iu_time_sl_thold_2, pc_iu_abst_sl_thold_2, pc_iu_ary_nsl_thold_2, pc_iu_repr_sl_thold_2, pc_iu_bolt_sl_thold_2}), + .q({pc_iu_func_sl_thold_1, pc_iu_sg_1, pc_iu_time_sl_thold_1, pc_iu_abst_sl_thold_1, pc_iu_ary_nsl_thold_1, pc_iu_repr_sl_thold_1, pc_iu_bolt_sl_thold_1}) + ); + + + tri_plat #(.WIDTH(7)) perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + .din({pc_iu_func_sl_thold_1, pc_iu_sg_1, pc_iu_time_sl_thold_1, pc_iu_abst_sl_thold_1, pc_iu_ary_nsl_thold_1, pc_iu_repr_sl_thold_1, pc_iu_bolt_sl_thold_1}), + .q({pc_iu_func_sl_thold_0, pc_iu_sg_0, pc_iu_time_sl_thold_0, pc_iu_abst_sl_thold_0, pc_iu_ary_nsl_thold_0, pc_iu_repr_sl_thold_0, pc_iu_bolt_sl_thold_0}) + ); + + + tri_lcbor perv_lcbor( + .clkoff_b(clkoff_b), + .thold(pc_iu_func_sl_thold_0), + .sg(pc_iu_sg_0), + .act_dis(act_dis), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b) + ); + + //----------------------------------------------- + // scan + //----------------------------------------------- + + assign siv[0:scan_right] = {func_scan_in, sov[0:scan_right - 1]}; + assign func_scan_out = sov[scan_right]; + + +endmodule diff --git a/dev/verilog/trilib/tri_bht_512x4_1r1w.v b/dev/verilog/trilib/tri_bht_512x4_1r1w.v new file mode 100755 index 0000000..f272e5f --- /dev/null +++ b/dev/verilog/trilib/tri_bht_512x4_1r1w.v @@ -0,0 +1,577 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// ********************************************************************* +// +// This is the ENTITY for tri_bht_512x4_1r1w +// +// ********************************************************************* + +(* block_type="soft" *) +(* recursive_synthesis="2" *) +(* pin_default_power_domain="vdd" *) +(* pin_default_ground_domain ="gnd" *) + +`include "tri_a2o.vh" + +module tri_bht_512x4_1r1w( + gnd, + vdd, + vcs, + nclk, + pc_iu_func_sl_thold_2, + pc_iu_sg_2, + pc_iu_time_sl_thold_2, + pc_iu_abst_sl_thold_2, + pc_iu_ary_nsl_thold_2, + pc_iu_repr_sl_thold_2, + pc_iu_bolt_sl_thold_2, + tc_ac_ccflush_dc, + tc_ac_scan_dis_dc_b, + clkoff_b, + scan_diag_dc, + act_dis, + d_mode, + delay_lclkr, + mpw1_b, + mpw2_b, + g8t_clkoff_b, + g8t_d_mode, + g8t_delay_lclkr, + g8t_mpw1_b, + g8t_mpw2_b, + func_scan_in, + time_scan_in, + abst_scan_in, + repr_scan_in, + func_scan_out, + time_scan_out, + abst_scan_out, + repr_scan_out, + pc_iu_abist_di_0, + pc_iu_abist_g8t_bw_1, + pc_iu_abist_g8t_bw_0, + pc_iu_abist_waddr_0, + pc_iu_abist_g8t_wenb, + pc_iu_abist_raddr_0, + pc_iu_abist_g8t1p_renb_0, + an_ac_lbist_ary_wrt_thru_dc, + pc_iu_abist_ena_dc, + pc_iu_abist_wl128_comp_ena, + pc_iu_abist_raw_dc_b, + pc_iu_abist_g8t_dcomp, + pc_iu_bo_enable_2, + pc_iu_bo_reset, + pc_iu_bo_unload, + pc_iu_bo_repair, + pc_iu_bo_shdata, + pc_iu_bo_select, + iu_pc_bo_fail, + iu_pc_bo_diagout, + r_act, + w_act, + r_addr, + w_addr, + data_in, + data_out0, + data_out1, + data_out2, + data_out3, + pc_iu_init_reset +); + // power pins + inout gnd; + inout vdd; + inout vcs; + + // clock and clockcontrol ports + input [0:`NCLK_WIDTH-1] nclk; + input pc_iu_func_sl_thold_2; + input pc_iu_sg_2; + input pc_iu_time_sl_thold_2; + input pc_iu_abst_sl_thold_2; + input pc_iu_ary_nsl_thold_2; + input pc_iu_repr_sl_thold_2; + input pc_iu_bolt_sl_thold_2; + input tc_ac_ccflush_dc; + input tc_ac_scan_dis_dc_b; + input clkoff_b; + input scan_diag_dc; + input act_dis; + input d_mode; + input delay_lclkr; + input mpw1_b; + input mpw2_b; + input g8t_clkoff_b; + input g8t_d_mode; + input [0:4] g8t_delay_lclkr; + input [0:4] g8t_mpw1_b; + input g8t_mpw2_b; + input func_scan_in; + input time_scan_in; + input abst_scan_in; + input repr_scan_in; + output func_scan_out; + output time_scan_out; + output abst_scan_out; + output repr_scan_out; + + input [0:3] pc_iu_abist_di_0; + input pc_iu_abist_g8t_bw_1; + input pc_iu_abist_g8t_bw_0; + input [3:9] pc_iu_abist_waddr_0; + input pc_iu_abist_g8t_wenb; + input [3:9] pc_iu_abist_raddr_0; + input pc_iu_abist_g8t1p_renb_0; + input an_ac_lbist_ary_wrt_thru_dc; + input pc_iu_abist_ena_dc; + input pc_iu_abist_wl128_comp_ena; + input pc_iu_abist_raw_dc_b; + input [0:3] pc_iu_abist_g8t_dcomp; + + // BOLT-ON + input pc_iu_bo_enable_2; // general bolt-on enable + input pc_iu_bo_reset; // reset + input pc_iu_bo_unload; // unload sticky bits + input pc_iu_bo_repair; // execute sticky bit decode + input pc_iu_bo_shdata; // shift data for timing write and diag loop + input pc_iu_bo_select; // select for mask and hier writes + output iu_pc_bo_fail; // fail/no-fix reg + output iu_pc_bo_diagout; + + // ports + input r_act; + input [0:3] w_act; + input [0:8] r_addr; + input [0:8] w_addr; + input data_in; + output data_out0; + output data_out1; + output data_out2; + output data_out3; + + input pc_iu_init_reset; + + //-------------------------- + // constants + //-------------------------- + + + parameter data_in_offset = 0; + parameter w_act_offset = data_in_offset + 1; + parameter r_act_offset = w_act_offset + 4; + parameter w_addr_offset = r_act_offset + 1; + parameter r_addr_offset = w_addr_offset + 9; + parameter data_out_offset = r_addr_offset + 9; + parameter reset_w_addr_offset = data_out_offset + 4; + parameter array_offset = reset_w_addr_offset + 9; + parameter scan_right = array_offset + 1 - 1; + + //-------------------------- + // signals + //-------------------------- + + wire pc_iu_func_sl_thold_1; + wire pc_iu_func_sl_thold_0; + wire pc_iu_func_sl_thold_0_b; + wire pc_iu_time_sl_thold_1; + wire pc_iu_time_sl_thold_0; + wire pc_iu_ary_nsl_thold_1; + wire pc_iu_ary_nsl_thold_0; + wire pc_iu_abst_sl_thold_1; + wire pc_iu_abst_sl_thold_0; + wire pc_iu_repr_sl_thold_1; + wire pc_iu_repr_sl_thold_0; + wire pc_iu_bolt_sl_thold_1; + wire pc_iu_bolt_sl_thold_0; + wire pc_iu_sg_1; + wire pc_iu_sg_0; + wire force_t; + + wire [0:scan_right] siv; + wire [0:scan_right] sov; + + wire tiup; + + wire [0:3] data_out_d; + wire [0:3] data_out_q; + + wire ary_w_en; + wire [0:8] ary_w_addr; + wire [0:15] ary_w_sel; + wire [0:15] ary_w_data; + + wire ary_r_en; + wire [0:8] ary_r_addr; + wire [0:15] ary_r_data; + + wire [0:3] data_out; + wire [0:3] write_thru; + + wire data_in_d; + wire data_in_q; + wire [0:3] w_act_d; + wire [0:3] w_act_q; + wire r_act_d; + wire r_act_q; + wire [0:8] w_addr_d; + wire [0:8] w_addr_q; + wire [0:8] r_addr_d; + wire [0:8] r_addr_q; + + wire lat_wi_act; + wire lat_ri_act; + wire lat_ro_act; + + wire reset_act; + wire [0:8] reset_w_addr_d; + wire [0:8] reset_w_addr_q; + + + + assign tiup = 1'b1; + + assign reset_act = pc_iu_init_reset; + assign reset_w_addr_d[0:8] = reset_w_addr_q[0:8] + 9'b000000001; + + assign data_out0 = data_out_q[0]; + assign data_out1 = data_out_q[1]; + assign data_out2 = data_out_q[2]; + assign data_out3 = data_out_q[3]; + + assign ary_w_en = reset_act | (|(w_act[0:3]) & (~((w_addr[0:8] == r_addr[0:8]) & r_act == 1'b1))); + + assign ary_w_addr[0:8] = reset_act ? reset_w_addr_q[0:8] : w_addr[0:8]; + + assign ary_w_sel[0] = reset_act ? 1'b1 : w_act[0]; + assign ary_w_sel[1] = reset_act ? 1'b1 : w_act[1]; + assign ary_w_sel[2] = reset_act ? 1'b1 : w_act[2]; + assign ary_w_sel[3] = reset_act ? 1'b1 : w_act[3]; + assign ary_w_sel[4] = reset_act ? 1'b1 : 1'b0; + assign ary_w_sel[5] = reset_act ? 1'b1 : 1'b0; + assign ary_w_sel[6] = reset_act ? 1'b1 : 1'b0; + assign ary_w_sel[7] = reset_act ? 1'b1 : 1'b0; + assign ary_w_sel[8] = reset_act ? 1'b1 : 1'b0; + assign ary_w_sel[9] = reset_act ? 1'b1 : 1'b0; + assign ary_w_sel[10] = reset_act ? 1'b1 : 1'b0; + assign ary_w_sel[11] = reset_act ? 1'b1 : 1'b0; + assign ary_w_sel[12] = reset_act ? 1'b1 : 1'b0; + assign ary_w_sel[13] = reset_act ? 1'b1 : 1'b0; + assign ary_w_sel[14] = reset_act ? 1'b1 : 1'b0; + assign ary_w_sel[15] = reset_act ? 1'b1 : 1'b0; + + assign ary_w_data[0:15] = reset_act ? 16'b0000000000000000: + {data_in, data_in, data_in, data_in, 12'b000000000000}; + + assign ary_r_en = r_act; + + assign ary_r_addr[0:8] = r_addr[0:8]; + + assign data_out[0:3] = ary_r_data[0:3]; + + //write through support + + assign data_in_d = data_in; + assign w_act_d[0:3] = w_act[0:3]; + assign r_act_d = r_act; + assign w_addr_d[0:8] = w_addr[0:8]; + assign r_addr_d[0:8] = r_addr[0:8]; + + assign write_thru[0:3] = ((w_addr_q[0:8] == r_addr_q[0:8]) & r_act_q == 1'b1) ? w_act_q[0:3] : + 4'b0000; + + assign data_out_d[0] = (write_thru[0] == 1'b1) ? data_in_q : + data_out[0]; + assign data_out_d[1] = (write_thru[1] == 1'b1) ? data_in_q : + data_out[1]; + assign data_out_d[2] = (write_thru[2] == 1'b1) ? data_in_q : + data_out[2]; + assign data_out_d[3] = (write_thru[3] == 1'b1) ? data_in_q : + data_out[3]; + + //latch acts + assign lat_wi_act = |(w_act[0:3]); + assign lat_ri_act = r_act; + assign lat_ro_act = r_act_q; + + //----------------------------------------------- + // array + //----------------------------------------------- + + + + tri_512x16_1r1w_1 bht0( + .gnd(gnd), + .vdd(vdd), + .vcs(vcs), + .nclk(nclk), + + .rd_act(ary_r_en), + .wr_act(ary_w_en), + + .lcb_d_mode_dc(g8t_d_mode), + .lcb_clkoff_dc_b(g8t_clkoff_b), + .lcb_mpw1_dc_b(g8t_mpw1_b), + .lcb_mpw2_dc_b(g8t_mpw2_b), + .lcb_delay_lclkr_dc(g8t_delay_lclkr), + .ccflush_dc(tc_ac_ccflush_dc), + .scan_dis_dc_b(tc_ac_scan_dis_dc_b), + .scan_diag_dc(scan_diag_dc), + .func_scan_in(siv[array_offset]), + .func_scan_out(sov[array_offset]), + + .lcb_sg_0(pc_iu_sg_0), + .lcb_sl_thold_0_b(pc_iu_func_sl_thold_0_b), + .lcb_time_sl_thold_0(pc_iu_time_sl_thold_0), + .lcb_abst_sl_thold_0(pc_iu_abst_sl_thold_0), + .lcb_ary_nsl_thold_0(pc_iu_ary_nsl_thold_0), + .lcb_repr_sl_thold_0(pc_iu_repr_sl_thold_0), + .time_scan_in(time_scan_in), + .time_scan_out(time_scan_out), + .abst_scan_in(abst_scan_in), + .abst_scan_out(abst_scan_out), + .repr_scan_in(repr_scan_in), + .repr_scan_out(repr_scan_out), + + .abist_di(pc_iu_abist_di_0), + .abist_bw_odd(pc_iu_abist_g8t_bw_1), + .abist_bw_even(pc_iu_abist_g8t_bw_0), + .abist_wr_adr(pc_iu_abist_waddr_0), + .wr_abst_act(pc_iu_abist_g8t_wenb), + .abist_rd0_adr(pc_iu_abist_raddr_0), + .rd0_abst_act(pc_iu_abist_g8t1p_renb_0), + .tc_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc), + .abist_ena_1(pc_iu_abist_ena_dc), + .abist_g8t_rd0_comp_ena(pc_iu_abist_wl128_comp_ena), + .abist_raw_dc_b(pc_iu_abist_raw_dc_b), + .obs0_abist_cmp(pc_iu_abist_g8t_dcomp), + + .lcb_bolt_sl_thold_0(pc_iu_bolt_sl_thold_0), + .pc_bo_enable_2(pc_iu_bo_enable_2), + .pc_bo_reset(pc_iu_bo_reset), + .pc_bo_unload(pc_iu_bo_unload), + .pc_bo_repair(pc_iu_bo_repair), + .pc_bo_shdata(pc_iu_bo_shdata), + .pc_bo_select(pc_iu_bo_select), + .bo_pc_failout(iu_pc_bo_fail), + .bo_pc_diagloop(iu_pc_bo_diagout), + + .tri_lcb_mpw1_dc_b(mpw1_b), + .tri_lcb_mpw2_dc_b(mpw2_b), + .tri_lcb_delay_lclkr_dc(delay_lclkr), + .tri_lcb_clkoff_dc_b(clkoff_b), + .tri_lcb_act_dis_dc(act_dis), + + .bw(ary_w_sel), + .wr_adr(ary_w_addr), + .rd_adr(ary_r_addr), + .di(ary_w_data), + .dout(ary_r_data) + ); + + //----------------------------------------------- + // latches + //----------------------------------------------- + + + tri_rlmlatch_p #(.INIT(0)) data_in_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lat_wi_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[data_in_offset:data_in_offset]), + .scout(sov[data_in_offset:data_in_offset]), + .din(data_in_d), + .dout(data_in_q) + ); + + + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) w_act_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[w_act_offset:w_act_offset + 4 - 1]), + .scout(sov[w_act_offset:w_act_offset + 4 - 1]), + .din(w_act_d), + .dout(w_act_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) r_act_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[r_act_offset]), + .scout(sov[r_act_offset]), + .din(r_act_d), + .dout(r_act_q) + ); + + + tri_rlmreg_p #(.WIDTH(9), .INIT(0)) w_addr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lat_wi_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[w_addr_offset:w_addr_offset + 9 - 1]), + .scout(sov[w_addr_offset:w_addr_offset + 9 - 1]), + .din(w_addr_d), + .dout(w_addr_q) + ); + + + tri_rlmreg_p #(.WIDTH(9), .INIT(0)) r_addr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lat_ri_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[r_addr_offset:r_addr_offset + 9 - 1]), + .scout(sov[r_addr_offset:r_addr_offset + 9 - 1]), + .din(r_addr_d), + .dout(r_addr_q) + ); + + + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) data_out_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lat_ro_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[data_out_offset:data_out_offset + 4 - 1]), + .scout(sov[data_out_offset:data_out_offset + 4 - 1]), + .din(data_out_d), + .dout(data_out_q) + ); + + tri_rlmreg_p #(.WIDTH(9), .INIT(0)) reset_w_addr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(reset_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[reset_w_addr_offset:reset_w_addr_offset + 9 - 1]), + .scout(sov[reset_w_addr_offset:reset_w_addr_offset + 9 - 1]), + .din(reset_w_addr_d), + .dout(reset_w_addr_q) + ); + + //----------------------------------------------- + // pervasive + //----------------------------------------------- + + + tri_plat #(.WIDTH(7)) perv_2to1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + .din({pc_iu_func_sl_thold_2, pc_iu_sg_2, pc_iu_time_sl_thold_2, pc_iu_abst_sl_thold_2, pc_iu_ary_nsl_thold_2, pc_iu_repr_sl_thold_2, pc_iu_bolt_sl_thold_2}), + .q({pc_iu_func_sl_thold_1, pc_iu_sg_1, pc_iu_time_sl_thold_1, pc_iu_abst_sl_thold_1, pc_iu_ary_nsl_thold_1, pc_iu_repr_sl_thold_1, pc_iu_bolt_sl_thold_1}) + ); + + + tri_plat #(.WIDTH(7)) perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + .din({pc_iu_func_sl_thold_1, pc_iu_sg_1, pc_iu_time_sl_thold_1, pc_iu_abst_sl_thold_1, pc_iu_ary_nsl_thold_1, pc_iu_repr_sl_thold_1, pc_iu_bolt_sl_thold_1}), + .q({pc_iu_func_sl_thold_0, pc_iu_sg_0, pc_iu_time_sl_thold_0, pc_iu_abst_sl_thold_0, pc_iu_ary_nsl_thold_0, pc_iu_repr_sl_thold_0, pc_iu_bolt_sl_thold_0}) + ); + + + tri_lcbor perv_lcbor( + .clkoff_b(clkoff_b), + .thold(pc_iu_func_sl_thold_0), + .sg(pc_iu_sg_0), + .act_dis(act_dis), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b) + ); + + //----------------------------------------------- + // scan + //----------------------------------------------- + + assign siv[0:scan_right] = {func_scan_in, sov[0:scan_right - 1]}; + assign func_scan_out = sov[scan_right]; + + +endmodule diff --git a/dev/verilog/trilib/tri_bthmx.v b/dev/verilog/trilib/tri_bthmx.v new file mode 100755 index 0000000..ce6f56b --- /dev/null +++ b/dev/verilog/trilib/tri_bthmx.v @@ -0,0 +1,67 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +// Description: XU Multiplier Top +// +//***************************************************************************** + +`timescale 1 ns / 1 ns + +module tri_bthmx(x, sneg, sx, sx2, right, left, q, vd, gd); + +input x; +input sneg; +input sx; +input sx2; +input right; +output left; +output q; +(* ANALYSIS_NOT_ASSIGNED="TRUE" *) +(* ANALYSIS_NOT_REFERENCED="TRUE" *) +inout vd; +(* ANALYSIS_NOT_ASSIGNED="TRUE" *) +(* ANALYSIS_NOT_REFERENCED="TRUE" *) +inout gd; + + + +wire center, xn, spos; + +assign xn = ~x; +assign spos = ~sneg; + +assign center = ~(( xn & spos ) | + ( x & sneg )); + +assign left = center; // output + + +assign q = ( center & sx ) | + ( right & sx2 ) ; + +endmodule diff --git a/dev/verilog/trilib/tri_cam_16x143_1r1w1c.v b/dev/verilog/trilib/tri_cam_16x143_1r1w1c.v new file mode 100755 index 0000000..6f22617 --- /dev/null +++ b/dev/verilog/trilib/tri_cam_16x143_1r1w1c.v @@ -0,0 +1,2707 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// VHDL 1076 Macro Expander C version 07/11/00 +// job was run on Fri Mar 19 10:58:26 2010 + +//******************************************************************** +//* TITLE: I-ERAT CAM Tri-Library Model +//* NAME: tri_cam_16x143_1r1w1c +//******************************************************************** + +`include "tri_a2o.vh" + +module tri_cam_16x143_1r1w1c( + gnd, + vdd, + vcs, + nclk, + tc_ccflush_dc, + tc_scan_dis_dc_b, + tc_scan_diag_dc, + tc_lbist_en_dc, + an_ac_atpg_en_dc, + lcb_d_mode_dc, + lcb_clkoff_dc_b, + lcb_act_dis_dc, + lcb_mpw1_dc_b, + lcb_mpw2_dc_b, + lcb_delay_lclkr_dc, + pc_sg_2, + pc_func_slp_sl_thold_2, + pc_func_slp_nsl_thold_2, + pc_regf_slp_sl_thold_2, + pc_time_sl_thold_2, + pc_fce_2, + func_scan_in, + func_scan_out, + regfile_scan_in, + regfile_scan_out, + time_scan_in, + time_scan_out, + rd_val, + rd_val_late, + rw_entry, + wr_array_data, + wr_cam_data, + wr_array_val, + wr_cam_val, + wr_val_early, + comp_request, + comp_addr, + addr_enable, + comp_pgsize, + pgsize_enable, + comp_class, + class_enable, + comp_extclass, + extclass_enable, + comp_state, + state_enable, + comp_thdid, + thdid_enable, + comp_pid, + pid_enable, + comp_invalidate, + flash_invalidate, + array_cmp_data, + rd_array_data, + cam_cmp_data, + cam_hit, + cam_hit_entry, + entry_match, + entry_valid, + rd_cam_data, + bypass_mux_enab_np1, + bypass_attr_np1, + attr_np2, + rpn_np2 +); + parameter CAM_DATA_WIDTH = 84; + parameter ARRAY_DATA_WIDTH = 68; + parameter RPN_WIDTH = 30; + parameter NUM_ENTRY = 16; + parameter NUM_ENTRY_LOG2 = 4; + + // Power Pins + inout gnd; + inout vdd; + inout vcs; + + // Clocks and Scan Cntls + input [0:`NCLK_WIDTH-1] nclk; + input tc_ccflush_dc; + input tc_scan_dis_dc_b; + input tc_scan_diag_dc; + input tc_lbist_en_dc; + input an_ac_atpg_en_dc; + + input lcb_d_mode_dc; + input lcb_clkoff_dc_b; + input lcb_act_dis_dc; + input [0:3] lcb_mpw1_dc_b; + input lcb_mpw2_dc_b; + input [0:3] lcb_delay_lclkr_dc; + + input pc_sg_2; + input pc_func_slp_sl_thold_2; + input pc_func_slp_nsl_thold_2; + input pc_regf_slp_sl_thold_2; + input pc_time_sl_thold_2; + input pc_fce_2; + + input func_scan_in; + output func_scan_out; + input [0:4] regfile_scan_in; // 0:2 -> CAM, 3:4 -> RAM + output [0:4] regfile_scan_out; + input time_scan_in; + output time_scan_out; + + // Read Port + input rd_val; + input rd_val_late; + input [0:NUM_ENTRY_LOG2-1] rw_entry; + + // Write Port + input [0:ARRAY_DATA_WIDTH-1] wr_array_data; + input [0:CAM_DATA_WIDTH-1] wr_cam_data; + input [0:1] wr_array_val; + input [0:1] wr_cam_val; + input wr_val_early; + + // CAM Port + input comp_request; + input [0:51] comp_addr; + input [0:1] addr_enable; + input [0:2] comp_pgsize; + input pgsize_enable; + input [0:1] comp_class; + input [0:2] class_enable; + input [0:1] comp_extclass; + input [0:1] extclass_enable; + input [0:1] comp_state; + input [0:1] state_enable; + input [0:3] comp_thdid; + input [0:1] thdid_enable; + input [0:7] comp_pid; + input pid_enable; + input comp_invalidate; + input flash_invalidate; + + // Outputs + // Data Out + output [0:ARRAY_DATA_WIDTH-1] array_cmp_data; + output [0:ARRAY_DATA_WIDTH-1] rd_array_data; + + // CAM Output + output [0:CAM_DATA_WIDTH-1] cam_cmp_data; + output cam_hit; + output [0:NUM_ENTRY_LOG2-1] cam_hit_entry; + output [0:NUM_ENTRY-1] entry_match; + output [0:NUM_ENTRY-1] entry_valid; + output [0:CAM_DATA_WIDTH-1] rd_cam_data; + + //--- new ports for IO plus ----------------------- + input bypass_mux_enab_np1; + input [0:20] bypass_attr_np1; + output [0:20] attr_np2; + + output [22:51] rpn_np2; + + // tri_cam_16x143_1r1w1c + + // Configuration Statement for NCsim + //for all:RAMB16_S9_S9 use entity unisim.RAMB16_S9_S9; + //for all:RAMB16_S18_S18 use entity unisim.RAMB16_S18_S18; + //for all:RAMB16_S36_S36 use entity unisim.RAMB16_S36_S36; + + wire clk; + wire clk2x; + wire [0:8] bram0_addra; + wire [0:8] bram0_addrb; + wire [0:10] bram1_addra; + wire [0:10] bram1_addrb; + wire [0:9] bram2_addra; + wire [0:9] bram2_addrb; + wire bram0_wea; + wire bram1_wea; + wire bram2_wea; + wire [0:55] array_cmp_data_bram; + wire [66:72] array_cmp_data_bramp; + + // Latches + reg sreset_q; + reg gate_fq; + wire gate_d; + wire [52-RPN_WIDTH:51] comp_addr_np1_d; + reg [52-RPN_WIDTH:51] comp_addr_np1_q; // the internal latched np1 phase epn(22:51) from com_addr input + wire [52-RPN_WIDTH:51] rpn_np2_d; + reg [52-RPN_WIDTH:51] rpn_np2_q; + wire [0:20] attr_np2_d; + reg [0:20] attr_np2_q; + + // CAM entry signals + wire [0:51] entry0_epn_d; + reg [0:51] entry0_epn_q; + wire entry0_xbit_d; + reg entry0_xbit_q; + wire [0:2] entry0_size_d; + reg [0:2] entry0_size_q; + wire entry0_v_d; + reg entry0_v_q; + wire [0:3] entry0_thdid_d; + reg [0:3] entry0_thdid_q; + wire [0:1] entry0_class_d; + reg [0:1] entry0_class_q; + wire [0:1] entry0_extclass_d; + reg [0:1] entry0_extclass_q; + wire entry0_hv_d; + reg entry0_hv_q; + wire entry0_ds_d; + reg entry0_ds_q; + wire [0:7] entry0_pid_d; + reg [0:7] entry0_pid_q; + wire [0:8] entry0_cmpmask_d; + reg [0:8] entry0_cmpmask_q; + wire [0:9] entry0_parity_d; + reg [0:9] entry0_parity_q; + wire [0:1] wr_entry0_sel; + wire entry0_inval; + wire [0:1] entry0_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry0_cam_vec; + wire [0:51] entry1_epn_d; + reg [0:51] entry1_epn_q; + wire entry1_xbit_d; + reg entry1_xbit_q; + wire [0:2] entry1_size_d; + reg [0:2] entry1_size_q; + wire entry1_v_d; + reg entry1_v_q; + wire [0:3] entry1_thdid_d; + reg [0:3] entry1_thdid_q; + wire [0:1] entry1_class_d; + reg [0:1] entry1_class_q; + wire [0:1] entry1_extclass_d; + reg [0:1] entry1_extclass_q; + wire entry1_hv_d; + reg entry1_hv_q; + wire entry1_ds_d; + reg entry1_ds_q; + wire [0:7] entry1_pid_d; + reg [0:7] entry1_pid_q; + wire [0:8] entry1_cmpmask_d; + reg [0:8] entry1_cmpmask_q; + wire [0:9] entry1_parity_d; + reg [0:9] entry1_parity_q; + wire [0:1] wr_entry1_sel; + wire entry1_inval; + wire [0:1] entry1_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry1_cam_vec; + wire [0:51] entry2_epn_d; + reg [0:51] entry2_epn_q; + wire entry2_xbit_d; + reg entry2_xbit_q; + wire [0:2] entry2_size_d; + reg [0:2] entry2_size_q; + wire entry2_v_d; + reg entry2_v_q; + wire [0:3] entry2_thdid_d; + reg [0:3] entry2_thdid_q; + wire [0:1] entry2_class_d; + reg [0:1] entry2_class_q; + wire [0:1] entry2_extclass_d; + reg [0:1] entry2_extclass_q; + wire entry2_hv_d; + reg entry2_hv_q; + wire entry2_ds_d; + reg entry2_ds_q; + wire [0:7] entry2_pid_d; + reg [0:7] entry2_pid_q; + wire [0:8] entry2_cmpmask_d; + reg [0:8] entry2_cmpmask_q; + wire [0:9] entry2_parity_d; + reg [0:9] entry2_parity_q; + wire [0:1] wr_entry2_sel; + wire entry2_inval; + wire [0:1] entry2_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry2_cam_vec; + wire [0:51] entry3_epn_d; + reg [0:51] entry3_epn_q; + wire entry3_xbit_d; + reg entry3_xbit_q; + wire [0:2] entry3_size_d; + reg [0:2] entry3_size_q; + wire entry3_v_d; + reg entry3_v_q; + wire [0:3] entry3_thdid_d; + reg [0:3] entry3_thdid_q; + wire [0:1] entry3_class_d; + reg [0:1] entry3_class_q; + wire [0:1] entry3_extclass_d; + reg [0:1] entry3_extclass_q; + wire entry3_hv_d; + reg entry3_hv_q; + wire entry3_ds_d; + reg entry3_ds_q; + wire [0:7] entry3_pid_d; + reg [0:7] entry3_pid_q; + wire [0:8] entry3_cmpmask_d; + reg [0:8] entry3_cmpmask_q; + wire [0:9] entry3_parity_d; + reg [0:9] entry3_parity_q; + wire [0:1] wr_entry3_sel; + wire entry3_inval; + wire [0:1] entry3_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry3_cam_vec; + wire [0:51] entry4_epn_d; + reg [0:51] entry4_epn_q; + wire entry4_xbit_d; + reg entry4_xbit_q; + wire [0:2] entry4_size_d; + reg [0:2] entry4_size_q; + wire entry4_v_d; + reg entry4_v_q; + wire [0:3] entry4_thdid_d; + reg [0:3] entry4_thdid_q; + wire [0:1] entry4_class_d; + reg [0:1] entry4_class_q; + wire [0:1] entry4_extclass_d; + reg [0:1] entry4_extclass_q; + wire entry4_hv_d; + reg entry4_hv_q; + wire entry4_ds_d; + reg entry4_ds_q; + wire [0:7] entry4_pid_d; + reg [0:7] entry4_pid_q; + wire [0:8] entry4_cmpmask_d; + reg [0:8] entry4_cmpmask_q; + wire [0:9] entry4_parity_d; + reg [0:9] entry4_parity_q; + wire [0:1] wr_entry4_sel; + wire entry4_inval; + wire [0:1] entry4_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry4_cam_vec; + wire [0:51] entry5_epn_d; + reg [0:51] entry5_epn_q; + wire entry5_xbit_d; + reg entry5_xbit_q; + wire [0:2] entry5_size_d; + reg [0:2] entry5_size_q; + wire entry5_v_d; + reg entry5_v_q; + wire [0:3] entry5_thdid_d; + reg [0:3] entry5_thdid_q; + wire [0:1] entry5_class_d; + reg [0:1] entry5_class_q; + wire [0:1] entry5_extclass_d; + reg [0:1] entry5_extclass_q; + wire entry5_hv_d; + reg entry5_hv_q; + wire entry5_ds_d; + reg entry5_ds_q; + wire [0:7] entry5_pid_d; + reg [0:7] entry5_pid_q; + wire [0:8] entry5_cmpmask_d; + reg [0:8] entry5_cmpmask_q; + wire [0:9] entry5_parity_d; + reg [0:9] entry5_parity_q; + wire [0:1] wr_entry5_sel; + wire entry5_inval; + wire [0:1] entry5_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry5_cam_vec; + wire [0:51] entry6_epn_d; + reg [0:51] entry6_epn_q; + wire entry6_xbit_d; + reg entry6_xbit_q; + wire [0:2] entry6_size_d; + reg [0:2] entry6_size_q; + wire entry6_v_d; + reg entry6_v_q; + wire [0:3] entry6_thdid_d; + reg [0:3] entry6_thdid_q; + wire [0:1] entry6_class_d; + reg [0:1] entry6_class_q; + wire [0:1] entry6_extclass_d; + reg [0:1] entry6_extclass_q; + wire entry6_hv_d; + reg entry6_hv_q; + wire entry6_ds_d; + reg entry6_ds_q; + wire [0:7] entry6_pid_d; + reg [0:7] entry6_pid_q; + wire [0:8] entry6_cmpmask_d; + reg [0:8] entry6_cmpmask_q; + wire [0:9] entry6_parity_d; + reg [0:9] entry6_parity_q; + wire [0:1] wr_entry6_sel; + wire entry6_inval; + wire [0:1] entry6_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry6_cam_vec; + wire [0:51] entry7_epn_d; + reg [0:51] entry7_epn_q; + wire entry7_xbit_d; + reg entry7_xbit_q; + wire [0:2] entry7_size_d; + reg [0:2] entry7_size_q; + wire entry7_v_d; + reg entry7_v_q; + wire [0:3] entry7_thdid_d; + reg [0:3] entry7_thdid_q; + wire [0:1] entry7_class_d; + reg [0:1] entry7_class_q; + wire [0:1] entry7_extclass_d; + reg [0:1] entry7_extclass_q; + wire entry7_hv_d; + reg entry7_hv_q; + wire entry7_ds_d; + reg entry7_ds_q; + wire [0:7] entry7_pid_d; + reg [0:7] entry7_pid_q; + wire [0:8] entry7_cmpmask_d; + reg [0:8] entry7_cmpmask_q; + wire [0:9] entry7_parity_d; + reg [0:9] entry7_parity_q; + wire [0:1] wr_entry7_sel; + wire entry7_inval; + wire [0:1] entry7_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry7_cam_vec; + wire [0:51] entry8_epn_d; + reg [0:51] entry8_epn_q; + wire entry8_xbit_d; + reg entry8_xbit_q; + wire [0:2] entry8_size_d; + reg [0:2] entry8_size_q; + wire entry8_v_d; + reg entry8_v_q; + wire [0:3] entry8_thdid_d; + reg [0:3] entry8_thdid_q; + wire [0:1] entry8_class_d; + reg [0:1] entry8_class_q; + wire [0:1] entry8_extclass_d; + reg [0:1] entry8_extclass_q; + wire entry8_hv_d; + reg entry8_hv_q; + wire entry8_ds_d; + reg entry8_ds_q; + wire [0:7] entry8_pid_d; + reg [0:7] entry8_pid_q; + wire [0:8] entry8_cmpmask_d; + reg [0:8] entry8_cmpmask_q; + wire [0:9] entry8_parity_d; + reg [0:9] entry8_parity_q; + wire [0:1] wr_entry8_sel; + wire entry8_inval; + wire [0:1] entry8_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry8_cam_vec; + wire [0:51] entry9_epn_d; + reg [0:51] entry9_epn_q; + wire entry9_xbit_d; + reg entry9_xbit_q; + wire [0:2] entry9_size_d; + reg [0:2] entry9_size_q; + wire entry9_v_d; + reg entry9_v_q; + wire [0:3] entry9_thdid_d; + reg [0:3] entry9_thdid_q; + wire [0:1] entry9_class_d; + reg [0:1] entry9_class_q; + wire [0:1] entry9_extclass_d; + reg [0:1] entry9_extclass_q; + wire entry9_hv_d; + reg entry9_hv_q; + wire entry9_ds_d; + reg entry9_ds_q; + wire [0:7] entry9_pid_d; + reg [0:7] entry9_pid_q; + wire [0:8] entry9_cmpmask_d; + reg [0:8] entry9_cmpmask_q; + wire [0:9] entry9_parity_d; + reg [0:9] entry9_parity_q; + wire [0:1] wr_entry9_sel; + wire entry9_inval; + wire [0:1] entry9_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry9_cam_vec; + wire [0:51] entry10_epn_d; + reg [0:51] entry10_epn_q; + wire entry10_xbit_d; + reg entry10_xbit_q; + wire [0:2] entry10_size_d; + reg [0:2] entry10_size_q; + wire entry10_v_d; + reg entry10_v_q; + wire [0:3] entry10_thdid_d; + reg [0:3] entry10_thdid_q; + wire [0:1] entry10_class_d; + reg [0:1] entry10_class_q; + wire [0:1] entry10_extclass_d; + reg [0:1] entry10_extclass_q; + wire entry10_hv_d; + reg entry10_hv_q; + wire entry10_ds_d; + reg entry10_ds_q; + wire [0:7] entry10_pid_d; + reg [0:7] entry10_pid_q; + wire [0:8] entry10_cmpmask_d; + reg [0:8] entry10_cmpmask_q; + wire [0:9] entry10_parity_d; + reg [0:9] entry10_parity_q; + wire [0:1] wr_entry10_sel; + wire entry10_inval; + wire [0:1] entry10_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry10_cam_vec; + wire [0:51] entry11_epn_d; + reg [0:51] entry11_epn_q; + wire entry11_xbit_d; + reg entry11_xbit_q; + wire [0:2] entry11_size_d; + reg [0:2] entry11_size_q; + wire entry11_v_d; + reg entry11_v_q; + wire [0:3] entry11_thdid_d; + reg [0:3] entry11_thdid_q; + wire [0:1] entry11_class_d; + reg [0:1] entry11_class_q; + wire [0:1] entry11_extclass_d; + reg [0:1] entry11_extclass_q; + wire entry11_hv_d; + reg entry11_hv_q; + wire entry11_ds_d; + reg entry11_ds_q; + wire [0:7] entry11_pid_d; + reg [0:7] entry11_pid_q; + wire [0:8] entry11_cmpmask_d; + reg [0:8] entry11_cmpmask_q; + wire [0:9] entry11_parity_d; + reg [0:9] entry11_parity_q; + wire [0:1] wr_entry11_sel; + wire entry11_inval; + wire [0:1] entry11_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry11_cam_vec; + wire [0:51] entry12_epn_d; + reg [0:51] entry12_epn_q; + wire entry12_xbit_d; + reg entry12_xbit_q; + wire [0:2] entry12_size_d; + reg [0:2] entry12_size_q; + wire entry12_v_d; + reg entry12_v_q; + wire [0:3] entry12_thdid_d; + reg [0:3] entry12_thdid_q; + wire [0:1] entry12_class_d; + reg [0:1] entry12_class_q; + wire [0:1] entry12_extclass_d; + reg [0:1] entry12_extclass_q; + wire entry12_hv_d; + reg entry12_hv_q; + wire entry12_ds_d; + reg entry12_ds_q; + wire [0:7] entry12_pid_d; + reg [0:7] entry12_pid_q; + wire [0:8] entry12_cmpmask_d; + reg [0:8] entry12_cmpmask_q; + wire [0:9] entry12_parity_d; + reg [0:9] entry12_parity_q; + wire [0:1] wr_entry12_sel; + wire entry12_inval; + wire [0:1] entry12_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry12_cam_vec; + wire [0:51] entry13_epn_d; + reg [0:51] entry13_epn_q; + wire entry13_xbit_d; + reg entry13_xbit_q; + wire [0:2] entry13_size_d; + reg [0:2] entry13_size_q; + wire entry13_v_d; + reg entry13_v_q; + wire [0:3] entry13_thdid_d; + reg [0:3] entry13_thdid_q; + wire [0:1] entry13_class_d; + reg [0:1] entry13_class_q; + wire [0:1] entry13_extclass_d; + reg [0:1] entry13_extclass_q; + wire entry13_hv_d; + reg entry13_hv_q; + wire entry13_ds_d; + reg entry13_ds_q; + wire [0:7] entry13_pid_d; + reg [0:7] entry13_pid_q; + wire [0:8] entry13_cmpmask_d; + reg [0:8] entry13_cmpmask_q; + wire [0:9] entry13_parity_d; + reg [0:9] entry13_parity_q; + wire [0:1] wr_entry13_sel; + wire entry13_inval; + wire [0:1] entry13_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry13_cam_vec; + wire [0:51] entry14_epn_d; + reg [0:51] entry14_epn_q; + wire entry14_xbit_d; + reg entry14_xbit_q; + wire [0:2] entry14_size_d; + reg [0:2] entry14_size_q; + wire entry14_v_d; + reg entry14_v_q; + wire [0:3] entry14_thdid_d; + reg [0:3] entry14_thdid_q; + wire [0:1] entry14_class_d; + reg [0:1] entry14_class_q; + wire [0:1] entry14_extclass_d; + reg [0:1] entry14_extclass_q; + wire entry14_hv_d; + reg entry14_hv_q; + wire entry14_ds_d; + reg entry14_ds_q; + wire [0:7] entry14_pid_d; + reg [0:7] entry14_pid_q; + wire [0:8] entry14_cmpmask_d; + reg [0:8] entry14_cmpmask_q; + wire [0:9] entry14_parity_d; + reg [0:9] entry14_parity_q; + wire [0:1] wr_entry14_sel; + wire entry14_inval; + wire [0:1] entry14_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry14_cam_vec; + wire [0:51] entry15_epn_d; + reg [0:51] entry15_epn_q; + wire entry15_xbit_d; + reg entry15_xbit_q; + wire [0:2] entry15_size_d; + reg [0:2] entry15_size_q; + wire entry15_v_d; + reg entry15_v_q; + wire [0:3] entry15_thdid_d; + reg [0:3] entry15_thdid_q; + wire [0:1] entry15_class_d; + reg [0:1] entry15_class_q; + wire [0:1] entry15_extclass_d; + reg [0:1] entry15_extclass_q; + wire entry15_hv_d; + reg entry15_hv_q; + wire entry15_ds_d; + reg entry15_ds_q; + wire [0:7] entry15_pid_d; + reg [0:7] entry15_pid_q; + wire [0:8] entry15_cmpmask_d; + reg [0:8] entry15_cmpmask_q; + wire [0:9] entry15_parity_d; + reg [0:9] entry15_parity_q; + wire [0:1] wr_entry15_sel; + wire entry15_inval; + wire [0:1] entry15_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry15_cam_vec; + wire [0:4] cam_cmp_data_muxsel; + wire [0:4] rd_cam_data_muxsel; + wire [0:CAM_DATA_WIDTH-1] cam_cmp_data_np1; + wire [0:ARRAY_DATA_WIDTH-1] array_cmp_data_np1; + wire [0:72] wr_array_data_bram; + wire [0:72] rd_array_data_d_std; + wire [0:55] array_cmp_data_bram_std; + wire [66:72] array_cmp_data_bramp_std; + + // latch signals + wire [0:ARRAY_DATA_WIDTH-1] rd_array_data_d; + reg [0:ARRAY_DATA_WIDTH-1] rd_array_data_q; + wire [0:CAM_DATA_WIDTH-1] cam_cmp_data_d; + reg [0:CAM_DATA_WIDTH-1] cam_cmp_data_q; + wire [0:9] cam_cmp_parity_d; + reg [0:9] cam_cmp_parity_q; + wire [0:CAM_DATA_WIDTH-1] rd_cam_data_d; + reg [0:CAM_DATA_WIDTH-1] rd_cam_data_q; + wire [0:NUM_ENTRY-1] entry_match_d; + reg [0:NUM_ENTRY-1] entry_match_q; + wire [0:NUM_ENTRY-1] match_vec; + wire [0:NUM_ENTRY_LOG2-1] cam_hit_entry_d; + reg [0:NUM_ENTRY_LOG2-1] cam_hit_entry_q; + wire cam_hit_d; + reg cam_hit_q; + wire toggle_d; + reg toggle_q; + wire toggle2x_d; + reg toggle2x_q; + (* analysis_not_referenced="true" *) + wire unused; + + + + assign clk = (~nclk[0]); + assign clk2x = nclk[2]; + + always @(posedge clk) + begin: rlatch + sreset_q <= nclk[1]; + end + + // + // NEW clk2x gate logic start + // + + always @(posedge nclk[0]) + begin: tlatch + if (sreset_q == 1'b1) + toggle_q <= 1'b1; + else + toggle_q <= toggle_d; + end + + always @(posedge nclk[2]) + begin: flatch + toggle2x_q <= toggle2x_d; + gate_fq <= gate_d; + end + + assign toggle_d = (~toggle_q); + assign toggle2x_d = toggle_q; + + // should force gate_fq to be on during odd 2x clock (second half of 1x clock). + assign gate_d = toggle_q ^ toggle2x_q; + // if you want the first half do the following + //assign gate_d <= ~(toggle_q ^ toggle2x_q); + + // + // NEW clk2x gate logic end + // + + // Slow Latches (nclk) + always @(posedge nclk[0]) + begin: slatch + if (sreset_q == 1'b1) + begin + cam_cmp_data_q <= {CAM_DATA_WIDTH{1'b0}}; + cam_cmp_parity_q <= 10'b0; + rd_cam_data_q <= {CAM_DATA_WIDTH{1'b0}}; + rd_array_data_q <= {ARRAY_DATA_WIDTH{1'b0}}; + entry_match_q <= {NUM_ENTRY{1'b0}}; + cam_hit_entry_q <= {NUM_ENTRY_LOG2{1'b0}}; + cam_hit_q <= 1'b0; + comp_addr_np1_q <= {RPN_WIDTH{1'b0}}; + rpn_np2_q <= {RPN_WIDTH{1'b0}}; + attr_np2_q <= 21'b0; + entry0_size_q <= 3'b0; + entry0_xbit_q <= 1'b0; + entry0_epn_q <= 52'b0; + entry0_class_q <= 2'b0; + entry0_extclass_q <= 2'b0; + entry0_hv_q <= 1'b0; + entry0_ds_q <= 1'b0; + entry0_thdid_q <= 4'b0; + entry0_pid_q <= 8'b0; + entry0_v_q <= 1'b0; + entry0_parity_q <= 10'b0; + entry0_cmpmask_q <= 9'b0; + entry1_size_q <= 3'b0; + entry1_xbit_q <= 1'b0; + entry1_epn_q <= 52'b0; + entry1_class_q <= 2'b0; + entry1_extclass_q <= 2'b0; + entry1_hv_q <= 1'b0; + entry1_ds_q <= 1'b0; + entry1_thdid_q <= 4'b0; + entry1_pid_q <= 8'b0; + entry1_v_q <= 1'b0; + entry1_parity_q <= 10'b0; + entry1_cmpmask_q <= 9'b0; + entry2_size_q <= 3'b0; + entry2_xbit_q <= 1'b0; + entry2_epn_q <= 52'b0; + entry2_class_q <= 2'b0; + entry2_extclass_q <= 2'b0; + entry2_hv_q <= 1'b0; + entry2_ds_q <= 1'b0; + entry2_thdid_q <= 4'b0; + entry2_pid_q <= 8'b0; + entry2_v_q <= 1'b0; + entry2_parity_q <= 10'b0; + entry2_cmpmask_q <= 9'b0; + entry3_size_q <= 3'b0; + entry3_xbit_q <= 1'b0; + entry3_epn_q <= 52'b0; + entry3_class_q <= 2'b0; + entry3_extclass_q <= 2'b0; + entry3_hv_q <= 1'b0; + entry3_ds_q <= 1'b0; + entry3_thdid_q <= 4'b0; + entry3_pid_q <= 8'b0; + entry3_v_q <= 1'b0; + entry3_parity_q <= 10'b0; + entry3_cmpmask_q <= 9'b0; + entry4_size_q <= 3'b0; + entry4_xbit_q <= 1'b0; + entry4_epn_q <= 52'b0; + entry4_class_q <= 2'b0; + entry4_extclass_q <= 2'b0; + entry4_hv_q <= 1'b0; + entry4_ds_q <= 1'b0; + entry4_thdid_q <= 4'b0; + entry4_pid_q <= 8'b0; + entry4_v_q <= 1'b0; + entry4_parity_q <= 10'b0; + entry4_cmpmask_q <= 9'b0; + entry5_size_q <= 3'b0; + entry5_xbit_q <= 1'b0; + entry5_epn_q <= 52'b0; + entry5_class_q <= 2'b0; + entry5_extclass_q <= 2'b0; + entry5_hv_q <= 1'b0; + entry5_ds_q <= 1'b0; + entry5_thdid_q <= 4'b0; + entry5_pid_q <= 8'b0; + entry5_v_q <= 1'b0; + entry5_parity_q <= 10'b0; + entry5_cmpmask_q <= 9'b0; + entry6_size_q <= 3'b0; + entry6_xbit_q <= 1'b0; + entry6_epn_q <= 52'b0; + entry6_class_q <= 2'b0; + entry6_extclass_q <= 2'b0; + entry6_hv_q <= 1'b0; + entry6_ds_q <= 1'b0; + entry6_thdid_q <= 4'b0; + entry6_pid_q <= 8'b0; + entry6_v_q <= 1'b0; + entry6_parity_q <= 10'b0; + entry6_cmpmask_q <= 9'b0; + entry7_size_q <= 3'b0; + entry7_xbit_q <= 1'b0; + entry7_epn_q <= 52'b0; + entry7_class_q <= 2'b0; + entry7_extclass_q <= 2'b0; + entry7_hv_q <= 1'b0; + entry7_ds_q <= 1'b0; + entry7_thdid_q <= 4'b0; + entry7_pid_q <= 8'b0; + entry7_v_q <= 1'b0; + entry7_parity_q <= 10'b0; + entry7_cmpmask_q <= 9'b0; + entry8_size_q <= 3'b0; + entry8_xbit_q <= 1'b0; + entry8_epn_q <= 52'b0; + entry8_class_q <= 2'b0; + entry8_extclass_q <= 2'b0; + entry8_hv_q <= 1'b0; + entry8_ds_q <= 1'b0; + entry8_thdid_q <= 4'b0; + entry8_pid_q <= 8'b0; + entry8_v_q <= 1'b0; + entry8_parity_q <= 10'b0; + entry8_cmpmask_q <= 9'b0; + entry9_size_q <= 3'b0; + entry9_xbit_q <= 1'b0; + entry9_epn_q <= 52'b0; + entry9_class_q <= 2'b0; + entry9_extclass_q <= 2'b0; + entry9_hv_q <= 1'b0; + entry9_ds_q <= 1'b0; + entry9_thdid_q <= 4'b0; + entry9_pid_q <= 8'b0; + entry9_v_q <= 1'b0; + entry9_parity_q <= 10'b0; + entry9_cmpmask_q <= 9'b0; + entry10_size_q <= 3'b0; + entry10_xbit_q <= 1'b0; + entry10_epn_q <= 52'b0; + entry10_class_q <= 2'b0; + entry10_extclass_q <= 2'b0; + entry10_hv_q <= 1'b0; + entry10_ds_q <= 1'b0; + entry10_thdid_q <= 4'b0; + entry10_pid_q <= 8'b0; + entry10_v_q <= 1'b0; + entry10_parity_q <= 10'b0; + entry10_cmpmask_q <= 9'b0; + entry11_size_q <= 3'b0; + entry11_xbit_q <= 1'b0; + entry11_epn_q <= 52'b0; + entry11_class_q <= 2'b0; + entry11_extclass_q <= 2'b0; + entry11_hv_q <= 1'b0; + entry11_ds_q <= 1'b0; + entry11_thdid_q <= 4'b0; + entry11_pid_q <= 8'b0; + entry11_v_q <= 1'b0; + entry11_parity_q <= 10'b0; + entry11_cmpmask_q <= 9'b0; + entry12_size_q <= 3'b0; + entry12_xbit_q <= 1'b0; + entry12_epn_q <= 52'b0; + entry12_class_q <= 2'b0; + entry12_extclass_q <= 2'b0; + entry12_hv_q <= 1'b0; + entry12_ds_q <= 1'b0; + entry12_thdid_q <= 4'b0; + entry12_pid_q <= 8'b0; + entry12_v_q <= 1'b0; + entry12_parity_q <= 10'b0; + entry12_cmpmask_q <= 9'b0; + entry13_size_q <= 3'b0; + entry13_xbit_q <= 1'b0; + entry13_epn_q <= 52'b0; + entry13_class_q <= 2'b0; + entry13_extclass_q <= 2'b0; + entry13_hv_q <= 1'b0; + entry13_ds_q <= 1'b0; + entry13_thdid_q <= 4'b0; + entry13_pid_q <= 8'b0; + entry13_v_q <= 1'b0; + entry13_parity_q <= 10'b0; + entry13_cmpmask_q <= 9'b0; + entry14_size_q <= 3'b0; + entry14_xbit_q <= 1'b0; + entry14_epn_q <= 52'b0; + entry14_class_q <= 2'b0; + entry14_extclass_q <= 2'b0; + entry14_hv_q <= 1'b0; + entry14_ds_q <= 1'b0; + entry14_thdid_q <= 4'b0; + entry14_pid_q <= 8'b0; + entry14_v_q <= 1'b0; + entry14_parity_q <= 10'b0; + entry14_cmpmask_q <= 9'b0; + entry15_size_q <= 3'b0; + entry15_xbit_q <= 1'b0; + entry15_epn_q <= 52'b0; + entry15_class_q <= 2'b0; + entry15_extclass_q <= 2'b0; + entry15_hv_q <= 1'b0; + entry15_ds_q <= 1'b0; + entry15_thdid_q <= 4'b0; + entry15_pid_q <= 8'b0; + entry15_v_q <= 1'b0; + entry15_parity_q <= 10'b0; + entry15_cmpmask_q <= 9'b0; + end + else + begin + cam_cmp_data_q <= cam_cmp_data_d; + rd_cam_data_q <= rd_cam_data_d; + rd_array_data_q <= rd_array_data_d; + entry_match_q <= entry_match_d; + cam_hit_entry_q <= cam_hit_entry_d; + cam_hit_q <= cam_hit_d; + cam_cmp_parity_q <= cam_cmp_parity_d; + comp_addr_np1_q <= comp_addr_np1_d; + rpn_np2_q <= rpn_np2_d; + attr_np2_q <= attr_np2_d; + entry0_size_q <= entry0_size_d; + entry0_xbit_q <= entry0_xbit_d; + entry0_epn_q <= entry0_epn_d; + entry0_class_q <= entry0_class_d; + entry0_extclass_q <= entry0_extclass_d; + entry0_hv_q <= entry0_hv_d; + entry0_ds_q <= entry0_ds_d; + entry0_thdid_q <= entry0_thdid_d; + entry0_pid_q <= entry0_pid_d; + entry0_v_q <= entry0_v_d; + entry0_parity_q <= entry0_parity_d; + entry0_cmpmask_q <= entry0_cmpmask_d; + entry1_size_q <= entry1_size_d; + entry1_xbit_q <= entry1_xbit_d; + entry1_epn_q <= entry1_epn_d; + entry1_class_q <= entry1_class_d; + entry1_extclass_q <= entry1_extclass_d; + entry1_hv_q <= entry1_hv_d; + entry1_ds_q <= entry1_ds_d; + entry1_thdid_q <= entry1_thdid_d; + entry1_pid_q <= entry1_pid_d; + entry1_v_q <= entry1_v_d; + entry1_parity_q <= entry1_parity_d; + entry1_cmpmask_q <= entry1_cmpmask_d; + entry2_size_q <= entry2_size_d; + entry2_xbit_q <= entry2_xbit_d; + entry2_epn_q <= entry2_epn_d; + entry2_class_q <= entry2_class_d; + entry2_extclass_q <= entry2_extclass_d; + entry2_hv_q <= entry2_hv_d; + entry2_ds_q <= entry2_ds_d; + entry2_thdid_q <= entry2_thdid_d; + entry2_pid_q <= entry2_pid_d; + entry2_v_q <= entry2_v_d; + entry2_parity_q <= entry2_parity_d; + entry2_cmpmask_q <= entry2_cmpmask_d; + entry3_size_q <= entry3_size_d; + entry3_xbit_q <= entry3_xbit_d; + entry3_epn_q <= entry3_epn_d; + entry3_class_q <= entry3_class_d; + entry3_extclass_q <= entry3_extclass_d; + entry3_hv_q <= entry3_hv_d; + entry3_ds_q <= entry3_ds_d; + entry3_thdid_q <= entry3_thdid_d; + entry3_pid_q <= entry3_pid_d; + entry3_v_q <= entry3_v_d; + entry3_parity_q <= entry3_parity_d; + entry3_cmpmask_q <= entry3_cmpmask_d; + entry4_size_q <= entry4_size_d; + entry4_xbit_q <= entry4_xbit_d; + entry4_epn_q <= entry4_epn_d; + entry4_class_q <= entry4_class_d; + entry4_extclass_q <= entry4_extclass_d; + entry4_hv_q <= entry4_hv_d; + entry4_ds_q <= entry4_ds_d; + entry4_thdid_q <= entry4_thdid_d; + entry4_pid_q <= entry4_pid_d; + entry4_v_q <= entry4_v_d; + entry4_parity_q <= entry4_parity_d; + entry4_cmpmask_q <= entry4_cmpmask_d; + entry5_size_q <= entry5_size_d; + entry5_xbit_q <= entry5_xbit_d; + entry5_epn_q <= entry5_epn_d; + entry5_class_q <= entry5_class_d; + entry5_extclass_q <= entry5_extclass_d; + entry5_hv_q <= entry5_hv_d; + entry5_ds_q <= entry5_ds_d; + entry5_thdid_q <= entry5_thdid_d; + entry5_pid_q <= entry5_pid_d; + entry5_v_q <= entry5_v_d; + entry5_parity_q <= entry5_parity_d; + entry5_cmpmask_q <= entry5_cmpmask_d; + entry6_size_q <= entry6_size_d; + entry6_xbit_q <= entry6_xbit_d; + entry6_epn_q <= entry6_epn_d; + entry6_class_q <= entry6_class_d; + entry6_extclass_q <= entry6_extclass_d; + entry6_hv_q <= entry6_hv_d; + entry6_ds_q <= entry6_ds_d; + entry6_thdid_q <= entry6_thdid_d; + entry6_pid_q <= entry6_pid_d; + entry6_v_q <= entry6_v_d; + entry6_parity_q <= entry6_parity_d; + entry6_cmpmask_q <= entry6_cmpmask_d; + entry7_size_q <= entry7_size_d; + entry7_xbit_q <= entry7_xbit_d; + entry7_epn_q <= entry7_epn_d; + entry7_class_q <= entry7_class_d; + entry7_extclass_q <= entry7_extclass_d; + entry7_hv_q <= entry7_hv_d; + entry7_ds_q <= entry7_ds_d; + entry7_thdid_q <= entry7_thdid_d; + entry7_pid_q <= entry7_pid_d; + entry7_v_q <= entry7_v_d; + entry7_parity_q <= entry7_parity_d; + entry7_cmpmask_q <= entry7_cmpmask_d; + entry8_size_q <= entry8_size_d; + entry8_xbit_q <= entry8_xbit_d; + entry8_epn_q <= entry8_epn_d; + entry8_class_q <= entry8_class_d; + entry8_extclass_q <= entry8_extclass_d; + entry8_hv_q <= entry8_hv_d; + entry8_ds_q <= entry8_ds_d; + entry8_thdid_q <= entry8_thdid_d; + entry8_pid_q <= entry8_pid_d; + entry8_v_q <= entry8_v_d; + entry8_parity_q <= entry8_parity_d; + entry8_cmpmask_q <= entry8_cmpmask_d; + entry9_size_q <= entry9_size_d; + entry9_xbit_q <= entry9_xbit_d; + entry9_epn_q <= entry9_epn_d; + entry9_class_q <= entry9_class_d; + entry9_extclass_q <= entry9_extclass_d; + entry9_hv_q <= entry9_hv_d; + entry9_ds_q <= entry9_ds_d; + entry9_thdid_q <= entry9_thdid_d; + entry9_pid_q <= entry9_pid_d; + entry9_v_q <= entry9_v_d; + entry9_parity_q <= entry9_parity_d; + entry9_cmpmask_q <= entry9_cmpmask_d; + entry10_size_q <= entry10_size_d; + entry10_xbit_q <= entry10_xbit_d; + entry10_epn_q <= entry10_epn_d; + entry10_class_q <= entry10_class_d; + entry10_extclass_q <= entry10_extclass_d; + entry10_hv_q <= entry10_hv_d; + entry10_ds_q <= entry10_ds_d; + entry10_thdid_q <= entry10_thdid_d; + entry10_pid_q <= entry10_pid_d; + entry10_v_q <= entry10_v_d; + entry10_parity_q <= entry10_parity_d; + entry10_cmpmask_q <= entry10_cmpmask_d; + entry11_size_q <= entry11_size_d; + entry11_xbit_q <= entry11_xbit_d; + entry11_epn_q <= entry11_epn_d; + entry11_class_q <= entry11_class_d; + entry11_extclass_q <= entry11_extclass_d; + entry11_hv_q <= entry11_hv_d; + entry11_ds_q <= entry11_ds_d; + entry11_thdid_q <= entry11_thdid_d; + entry11_pid_q <= entry11_pid_d; + entry11_v_q <= entry11_v_d; + entry11_parity_q <= entry11_parity_d; + entry11_cmpmask_q <= entry11_cmpmask_d; + entry12_size_q <= entry12_size_d; + entry12_xbit_q <= entry12_xbit_d; + entry12_epn_q <= entry12_epn_d; + entry12_class_q <= entry12_class_d; + entry12_extclass_q <= entry12_extclass_d; + entry12_hv_q <= entry12_hv_d; + entry12_ds_q <= entry12_ds_d; + entry12_thdid_q <= entry12_thdid_d; + entry12_pid_q <= entry12_pid_d; + entry12_v_q <= entry12_v_d; + entry12_parity_q <= entry12_parity_d; + entry12_cmpmask_q <= entry12_cmpmask_d; + entry13_size_q <= entry13_size_d; + entry13_xbit_q <= entry13_xbit_d; + entry13_epn_q <= entry13_epn_d; + entry13_class_q <= entry13_class_d; + entry13_extclass_q <= entry13_extclass_d; + entry13_hv_q <= entry13_hv_d; + entry13_ds_q <= entry13_ds_d; + entry13_thdid_q <= entry13_thdid_d; + entry13_pid_q <= entry13_pid_d; + entry13_v_q <= entry13_v_d; + entry13_parity_q <= entry13_parity_d; + entry13_cmpmask_q <= entry13_cmpmask_d; + entry14_size_q <= entry14_size_d; + entry14_xbit_q <= entry14_xbit_d; + entry14_epn_q <= entry14_epn_d; + entry14_class_q <= entry14_class_d; + entry14_extclass_q <= entry14_extclass_d; + entry14_hv_q <= entry14_hv_d; + entry14_ds_q <= entry14_ds_d; + entry14_thdid_q <= entry14_thdid_d; + entry14_pid_q <= entry14_pid_d; + entry14_v_q <= entry14_v_d; + entry14_parity_q <= entry14_parity_d; + entry14_cmpmask_q <= entry14_cmpmask_d; + entry15_size_q <= entry15_size_d; + entry15_xbit_q <= entry15_xbit_d; + entry15_epn_q <= entry15_epn_d; + entry15_class_q <= entry15_class_d; + entry15_extclass_q <= entry15_extclass_d; + entry15_hv_q <= entry15_hv_d; + entry15_ds_q <= entry15_ds_d; + entry15_thdid_q <= entry15_thdid_d; + entry15_pid_q <= entry15_pid_d; + entry15_v_q <= entry15_v_d; + entry15_parity_q <= entry15_parity_d; + entry15_cmpmask_q <= entry15_cmpmask_d; + end + end + + //--------------------------------------------------------------------- + // latch input logic + //--------------------------------------------------------------------- + assign comp_addr_np1_d = comp_addr[52 - RPN_WIDTH:51]; + + assign cam_hit_d = ((match_vec != 16'b0000000000000000) & (comp_request == 1'b1)) ? 1'b1 : + 1'b0; + + assign cam_hit_entry_d = (match_vec[0:1] == 2'b01) ? 4'b0001 : + (match_vec[0:2] == 3'b001) ? 4'b0010 : + (match_vec[0:3] == 4'b0001) ? 4'b0011 : + (match_vec[0:4] == 5'b00001) ? 4'b0100 : + (match_vec[0:5] == 6'b000001) ? 4'b0101 : + (match_vec[0:6] == 7'b0000001) ? 4'b0110 : + (match_vec[0:7] == 8'b00000001) ? 4'b0111 : + (match_vec[0:8] == 9'b000000001) ? 4'b1000 : + (match_vec[0:9] == 10'b0000000001) ? 4'b1001 : + (match_vec[0:10] == 11'b00000000001) ? 4'b1010 : + (match_vec[0:11] == 12'b000000000001) ? 4'b1011 : + (match_vec[0:12] == 13'b0000000000001) ? 4'b1100 : + (match_vec[0:13] == 14'b00000000000001) ? 4'b1101 : + (match_vec[0:14] == 15'b000000000000001) ? 4'b1110 : + (match_vec[0:15] == 16'b0000000000000001) ? 4'b1111 : + 4'b0000; + + assign entry_match_d = ((comp_request == 1'b1)) ? match_vec : + {NUM_ENTRY{1'b0}}; + + // entry write next state logic + assign wr_entry0_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 4'b0000)) ? 1'b1 : + 1'b0; + assign wr_entry0_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 4'b0000)) ? 1'b1 : + 1'b0; + assign entry0_epn_d[0:31] = (wr_entry0_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry0_epn_q[0:31]; + assign entry0_epn_d[32:51] = (wr_entry0_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry0_epn_q[32:51]; + assign entry0_xbit_d = (wr_entry0_sel[0] == 1'b1) ? wr_cam_data[52] : + entry0_xbit_q; + assign entry0_size_d = (wr_entry0_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry0_size_q[0:2]; + assign entry0_class_d = (wr_entry0_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry0_class_q[0:1]; + assign entry0_extclass_d = (wr_entry0_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry0_extclass_q[0:1]; + assign entry0_hv_d = (wr_entry0_sel[1] == 1'b1) ? wr_cam_data[65] : + entry0_hv_q; + assign entry0_ds_d = (wr_entry0_sel[1] == 1'b1) ? wr_cam_data[66] : + entry0_ds_q; + assign entry0_pid_d = (wr_entry0_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry0_pid_q[0:7]; + assign entry0_cmpmask_d = (wr_entry0_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry0_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry0_parity_d[0:3] = (wr_entry0_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry0_parity_q[0:3]; + assign entry0_parity_d[4:6] = (wr_entry0_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry0_parity_q[4:6]; + assign entry0_parity_d[7] = (wr_entry0_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry0_parity_q[7]; + assign entry0_parity_d[8] = (wr_entry0_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry0_parity_q[8]; + assign entry0_parity_d[9] = (wr_entry0_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry0_parity_q[9]; + assign wr_entry1_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 4'b0001)) ? 1'b1 : + 1'b0; + assign wr_entry1_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 4'b0001)) ? 1'b1 : + 1'b0; + assign entry1_epn_d[0:31] = (wr_entry1_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry1_epn_q[0:31]; + assign entry1_epn_d[32:51] = (wr_entry1_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry1_epn_q[32:51]; + assign entry1_xbit_d = (wr_entry1_sel[0] == 1'b1) ? wr_cam_data[52] : + entry1_xbit_q; + assign entry1_size_d = (wr_entry1_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry1_size_q[0:2]; + assign entry1_class_d = (wr_entry1_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry1_class_q[0:1]; + assign entry1_extclass_d = (wr_entry1_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry1_extclass_q[0:1]; + assign entry1_hv_d = (wr_entry1_sel[1] == 1'b1) ? wr_cam_data[65] : + entry1_hv_q; + assign entry1_ds_d = (wr_entry1_sel[1] == 1'b1) ? wr_cam_data[66] : + entry1_ds_q; + assign entry1_pid_d = (wr_entry1_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry1_pid_q[0:7]; + assign entry1_cmpmask_d = (wr_entry1_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry1_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry1_parity_d[0:3] = (wr_entry1_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry1_parity_q[0:3]; + assign entry1_parity_d[4:6] = (wr_entry1_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry1_parity_q[4:6]; + assign entry1_parity_d[7] = (wr_entry1_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry1_parity_q[7]; + assign entry1_parity_d[8] = (wr_entry1_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry1_parity_q[8]; + assign entry1_parity_d[9] = (wr_entry1_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry1_parity_q[9]; + assign wr_entry2_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 4'b0010)) ? 1'b1 : + 1'b0; + assign wr_entry2_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 4'b0010)) ? 1'b1 : + 1'b0; + assign entry2_epn_d[0:31] = (wr_entry2_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry2_epn_q[0:31]; + assign entry2_epn_d[32:51] = (wr_entry2_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry2_epn_q[32:51]; + assign entry2_xbit_d = (wr_entry2_sel[0] == 1'b1) ? wr_cam_data[52] : + entry2_xbit_q; + assign entry2_size_d = (wr_entry2_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry2_size_q[0:2]; + assign entry2_class_d = (wr_entry2_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry2_class_q[0:1]; + assign entry2_extclass_d = (wr_entry2_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry2_extclass_q[0:1]; + assign entry2_hv_d = (wr_entry2_sel[1] == 1'b1) ? wr_cam_data[65] : + entry2_hv_q; + assign entry2_ds_d = (wr_entry2_sel[1] == 1'b1) ? wr_cam_data[66] : + entry2_ds_q; + assign entry2_pid_d = (wr_entry2_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry2_pid_q[0:7]; + assign entry2_cmpmask_d = (wr_entry2_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry2_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry2_parity_d[0:3] = (wr_entry2_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry2_parity_q[0:3]; + assign entry2_parity_d[4:6] = (wr_entry2_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry2_parity_q[4:6]; + assign entry2_parity_d[7] = (wr_entry2_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry2_parity_q[7]; + assign entry2_parity_d[8] = (wr_entry2_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry2_parity_q[8]; + assign entry2_parity_d[9] = (wr_entry2_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry2_parity_q[9]; + assign wr_entry3_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 4'b0011)) ? 1'b1 : + 1'b0; + assign wr_entry3_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 4'b0011)) ? 1'b1 : + 1'b0; + assign entry3_epn_d[0:31] = (wr_entry3_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry3_epn_q[0:31]; + assign entry3_epn_d[32:51] = (wr_entry3_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry3_epn_q[32:51]; + assign entry3_xbit_d = (wr_entry3_sel[0] == 1'b1) ? wr_cam_data[52] : + entry3_xbit_q; + assign entry3_size_d = (wr_entry3_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry3_size_q[0:2]; + assign entry3_class_d = (wr_entry3_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry3_class_q[0:1]; + assign entry3_extclass_d = (wr_entry3_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry3_extclass_q[0:1]; + assign entry3_hv_d = (wr_entry3_sel[1] == 1'b1) ? wr_cam_data[65] : + entry3_hv_q; + assign entry3_ds_d = (wr_entry3_sel[1] == 1'b1) ? wr_cam_data[66] : + entry3_ds_q; + assign entry3_pid_d = (wr_entry3_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry3_pid_q[0:7]; + assign entry3_cmpmask_d = (wr_entry3_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry3_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry3_parity_d[0:3] = (wr_entry3_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry3_parity_q[0:3]; + assign entry3_parity_d[4:6] = (wr_entry3_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry3_parity_q[4:6]; + assign entry3_parity_d[7] = (wr_entry3_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry3_parity_q[7]; + assign entry3_parity_d[8] = (wr_entry3_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry3_parity_q[8]; + assign entry3_parity_d[9] = (wr_entry3_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry3_parity_q[9]; + assign wr_entry4_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 4'b0100)) ? 1'b1 : + 1'b0; + assign wr_entry4_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 4'b0100)) ? 1'b1 : + 1'b0; + assign entry4_epn_d[0:31] = (wr_entry4_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry4_epn_q[0:31]; + assign entry4_epn_d[32:51] = (wr_entry4_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry4_epn_q[32:51]; + assign entry4_xbit_d = (wr_entry4_sel[0] == 1'b1) ? wr_cam_data[52] : + entry4_xbit_q; + assign entry4_size_d = (wr_entry4_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry4_size_q[0:2]; + assign entry4_class_d = (wr_entry4_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry4_class_q[0:1]; + assign entry4_extclass_d = (wr_entry4_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry4_extclass_q[0:1]; + assign entry4_hv_d = (wr_entry4_sel[1] == 1'b1) ? wr_cam_data[65] : + entry4_hv_q; + assign entry4_ds_d = (wr_entry4_sel[1] == 1'b1) ? wr_cam_data[66] : + entry4_ds_q; + assign entry4_pid_d = (wr_entry4_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry4_pid_q[0:7]; + assign entry4_cmpmask_d = (wr_entry4_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry4_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry4_parity_d[0:3] = (wr_entry4_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry4_parity_q[0:3]; + assign entry4_parity_d[4:6] = (wr_entry4_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry4_parity_q[4:6]; + assign entry4_parity_d[7] = (wr_entry4_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry4_parity_q[7]; + assign entry4_parity_d[8] = (wr_entry4_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry4_parity_q[8]; + assign entry4_parity_d[9] = (wr_entry4_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry4_parity_q[9]; + assign wr_entry5_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 4'b0101)) ? 1'b1 : + 1'b0; + assign wr_entry5_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 4'b0101)) ? 1'b1 : + 1'b0; + assign entry5_epn_d[0:31] = (wr_entry5_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry5_epn_q[0:31]; + assign entry5_epn_d[32:51] = (wr_entry5_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry5_epn_q[32:51]; + assign entry5_xbit_d = (wr_entry5_sel[0] == 1'b1) ? wr_cam_data[52] : + entry5_xbit_q; + assign entry5_size_d = (wr_entry5_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry5_size_q[0:2]; + assign entry5_class_d = (wr_entry5_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry5_class_q[0:1]; + assign entry5_extclass_d = (wr_entry5_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry5_extclass_q[0:1]; + assign entry5_hv_d = (wr_entry5_sel[1] == 1'b1) ? wr_cam_data[65] : + entry5_hv_q; + assign entry5_ds_d = (wr_entry5_sel[1] == 1'b1) ? wr_cam_data[66] : + entry5_ds_q; + assign entry5_pid_d = (wr_entry5_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry5_pid_q[0:7]; + assign entry5_cmpmask_d = (wr_entry5_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry5_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry5_parity_d[0:3] = (wr_entry5_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry5_parity_q[0:3]; + assign entry5_parity_d[4:6] = (wr_entry5_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry5_parity_q[4:6]; + assign entry5_parity_d[7] = (wr_entry5_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry5_parity_q[7]; + assign entry5_parity_d[8] = (wr_entry5_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry5_parity_q[8]; + assign entry5_parity_d[9] = (wr_entry5_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry5_parity_q[9]; + assign wr_entry6_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 4'b0110)) ? 1'b1 : + 1'b0; + assign wr_entry6_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 4'b0110)) ? 1'b1 : + 1'b0; + assign entry6_epn_d[0:31] = (wr_entry6_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry6_epn_q[0:31]; + assign entry6_epn_d[32:51] = (wr_entry6_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry6_epn_q[32:51]; + assign entry6_xbit_d = (wr_entry6_sel[0] == 1'b1) ? wr_cam_data[52] : + entry6_xbit_q; + assign entry6_size_d = (wr_entry6_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry6_size_q[0:2]; + assign entry6_class_d = (wr_entry6_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry6_class_q[0:1]; + assign entry6_extclass_d = (wr_entry6_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry6_extclass_q[0:1]; + assign entry6_hv_d = (wr_entry6_sel[1] == 1'b1) ? wr_cam_data[65] : + entry6_hv_q; + assign entry6_ds_d = (wr_entry6_sel[1] == 1'b1) ? wr_cam_data[66] : + entry6_ds_q; + assign entry6_pid_d = (wr_entry6_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry6_pid_q[0:7]; + assign entry6_cmpmask_d = (wr_entry6_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry6_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry6_parity_d[0:3] = (wr_entry6_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry6_parity_q[0:3]; + assign entry6_parity_d[4:6] = (wr_entry6_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry6_parity_q[4:6]; + assign entry6_parity_d[7] = (wr_entry6_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry6_parity_q[7]; + assign entry6_parity_d[8] = (wr_entry6_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry6_parity_q[8]; + assign entry6_parity_d[9] = (wr_entry6_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry6_parity_q[9]; + assign wr_entry7_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 4'b0111)) ? 1'b1 : + 1'b0; + assign wr_entry7_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 4'b0111)) ? 1'b1 : + 1'b0; + assign entry7_epn_d[0:31] = (wr_entry7_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry7_epn_q[0:31]; + assign entry7_epn_d[32:51] = (wr_entry7_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry7_epn_q[32:51]; + assign entry7_xbit_d = (wr_entry7_sel[0] == 1'b1) ? wr_cam_data[52] : + entry7_xbit_q; + assign entry7_size_d = (wr_entry7_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry7_size_q[0:2]; + assign entry7_class_d = (wr_entry7_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry7_class_q[0:1]; + assign entry7_extclass_d = (wr_entry7_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry7_extclass_q[0:1]; + assign entry7_hv_d = (wr_entry7_sel[1] == 1'b1) ? wr_cam_data[65] : + entry7_hv_q; + assign entry7_ds_d = (wr_entry7_sel[1] == 1'b1) ? wr_cam_data[66] : + entry7_ds_q; + assign entry7_pid_d = (wr_entry7_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry7_pid_q[0:7]; + assign entry7_cmpmask_d = (wr_entry7_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry7_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry7_parity_d[0:3] = (wr_entry7_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry7_parity_q[0:3]; + assign entry7_parity_d[4:6] = (wr_entry7_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry7_parity_q[4:6]; + assign entry7_parity_d[7] = (wr_entry7_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry7_parity_q[7]; + assign entry7_parity_d[8] = (wr_entry7_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry7_parity_q[8]; + assign entry7_parity_d[9] = (wr_entry7_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry7_parity_q[9]; + assign wr_entry8_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 4'b1000)) ? 1'b1 : + 1'b0; + assign wr_entry8_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 4'b1000)) ? 1'b1 : + 1'b0; + assign entry8_epn_d[0:31] = (wr_entry8_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry8_epn_q[0:31]; + assign entry8_epn_d[32:51] = (wr_entry8_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry8_epn_q[32:51]; + assign entry8_xbit_d = (wr_entry8_sel[0] == 1'b1) ? wr_cam_data[52] : + entry8_xbit_q; + assign entry8_size_d = (wr_entry8_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry8_size_q[0:2]; + assign entry8_class_d = (wr_entry8_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry8_class_q[0:1]; + assign entry8_extclass_d = (wr_entry8_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry8_extclass_q[0:1]; + assign entry8_hv_d = (wr_entry8_sel[1] == 1'b1) ? wr_cam_data[65] : + entry8_hv_q; + assign entry8_ds_d = (wr_entry8_sel[1] == 1'b1) ? wr_cam_data[66] : + entry8_ds_q; + assign entry8_pid_d = (wr_entry8_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry8_pid_q[0:7]; + assign entry8_cmpmask_d = (wr_entry8_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry8_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry8_parity_d[0:3] = (wr_entry8_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry8_parity_q[0:3]; + assign entry8_parity_d[4:6] = (wr_entry8_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry8_parity_q[4:6]; + assign entry8_parity_d[7] = (wr_entry8_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry8_parity_q[7]; + assign entry8_parity_d[8] = (wr_entry8_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry8_parity_q[8]; + assign entry8_parity_d[9] = (wr_entry8_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry8_parity_q[9]; + assign wr_entry9_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 4'b1001)) ? 1'b1 : + 1'b0; + assign wr_entry9_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 4'b1001)) ? 1'b1 : + 1'b0; + assign entry9_epn_d[0:31] = (wr_entry9_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry9_epn_q[0:31]; + assign entry9_epn_d[32:51] = (wr_entry9_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry9_epn_q[32:51]; + assign entry9_xbit_d = (wr_entry9_sel[0] == 1'b1) ? wr_cam_data[52] : + entry9_xbit_q; + assign entry9_size_d = (wr_entry9_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry9_size_q[0:2]; + assign entry9_class_d = (wr_entry9_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry9_class_q[0:1]; + assign entry9_extclass_d = (wr_entry9_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry9_extclass_q[0:1]; + assign entry9_hv_d = (wr_entry9_sel[1] == 1'b1) ? wr_cam_data[65] : + entry9_hv_q; + assign entry9_ds_d = (wr_entry9_sel[1] == 1'b1) ? wr_cam_data[66] : + entry9_ds_q; + assign entry9_pid_d = (wr_entry9_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry9_pid_q[0:7]; + assign entry9_cmpmask_d = (wr_entry9_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry9_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry9_parity_d[0:3] = (wr_entry9_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry9_parity_q[0:3]; + assign entry9_parity_d[4:6] = (wr_entry9_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry9_parity_q[4:6]; + assign entry9_parity_d[7] = (wr_entry9_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry9_parity_q[7]; + assign entry9_parity_d[8] = (wr_entry9_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry9_parity_q[8]; + assign entry9_parity_d[9] = (wr_entry9_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry9_parity_q[9]; + assign wr_entry10_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 4'b1010)) ? 1'b1 : + 1'b0; + assign wr_entry10_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 4'b1010)) ? 1'b1 : + 1'b0; + assign entry10_epn_d[0:31] = (wr_entry10_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry10_epn_q[0:31]; + assign entry10_epn_d[32:51] = (wr_entry10_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry10_epn_q[32:51]; + assign entry10_xbit_d = (wr_entry10_sel[0] == 1'b1) ? wr_cam_data[52] : + entry10_xbit_q; + assign entry10_size_d = (wr_entry10_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry10_size_q[0:2]; + assign entry10_class_d = (wr_entry10_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry10_class_q[0:1]; + assign entry10_extclass_d = (wr_entry10_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry10_extclass_q[0:1]; + assign entry10_hv_d = (wr_entry10_sel[1] == 1'b1) ? wr_cam_data[65] : + entry10_hv_q; + assign entry10_ds_d = (wr_entry10_sel[1] == 1'b1) ? wr_cam_data[66] : + entry10_ds_q; + assign entry10_pid_d = (wr_entry10_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry10_pid_q[0:7]; + assign entry10_cmpmask_d = (wr_entry10_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry10_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry10_parity_d[0:3] = (wr_entry10_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry10_parity_q[0:3]; + assign entry10_parity_d[4:6] = (wr_entry10_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry10_parity_q[4:6]; + assign entry10_parity_d[7] = (wr_entry10_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry10_parity_q[7]; + assign entry10_parity_d[8] = (wr_entry10_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry10_parity_q[8]; + assign entry10_parity_d[9] = (wr_entry10_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry10_parity_q[9]; + assign wr_entry11_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 4'b1011)) ? 1'b1 : + 1'b0; + assign wr_entry11_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 4'b1011)) ? 1'b1 : + 1'b0; + assign entry11_epn_d[0:31] = (wr_entry11_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry11_epn_q[0:31]; + assign entry11_epn_d[32:51] = (wr_entry11_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry11_epn_q[32:51]; + assign entry11_xbit_d = (wr_entry11_sel[0] == 1'b1) ? wr_cam_data[52] : + entry11_xbit_q; + assign entry11_size_d = (wr_entry11_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry11_size_q[0:2]; + assign entry11_class_d = (wr_entry11_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry11_class_q[0:1]; + assign entry11_extclass_d = (wr_entry11_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry11_extclass_q[0:1]; + assign entry11_hv_d = (wr_entry11_sel[1] == 1'b1) ? wr_cam_data[65] : + entry11_hv_q; + assign entry11_ds_d = (wr_entry11_sel[1] == 1'b1) ? wr_cam_data[66] : + entry11_ds_q; + assign entry11_pid_d = (wr_entry11_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry11_pid_q[0:7]; + assign entry11_cmpmask_d = (wr_entry11_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry11_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry11_parity_d[0:3] = (wr_entry11_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry11_parity_q[0:3]; + assign entry11_parity_d[4:6] = (wr_entry11_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry11_parity_q[4:6]; + assign entry11_parity_d[7] = (wr_entry11_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry11_parity_q[7]; + assign entry11_parity_d[8] = (wr_entry11_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry11_parity_q[8]; + assign entry11_parity_d[9] = (wr_entry11_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry11_parity_q[9]; + assign wr_entry12_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 4'b1100)) ? 1'b1 : + 1'b0; + assign wr_entry12_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 4'b1100)) ? 1'b1 : + 1'b0; + assign entry12_epn_d[0:31] = (wr_entry12_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry12_epn_q[0:31]; + assign entry12_epn_d[32:51] = (wr_entry12_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry12_epn_q[32:51]; + assign entry12_xbit_d = (wr_entry12_sel[0] == 1'b1) ? wr_cam_data[52] : + entry12_xbit_q; + assign entry12_size_d = (wr_entry12_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry12_size_q[0:2]; + assign entry12_class_d = (wr_entry12_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry12_class_q[0:1]; + assign entry12_extclass_d = (wr_entry12_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry12_extclass_q[0:1]; + assign entry12_hv_d = (wr_entry12_sel[1] == 1'b1) ? wr_cam_data[65] : + entry12_hv_q; + assign entry12_ds_d = (wr_entry12_sel[1] == 1'b1) ? wr_cam_data[66] : + entry12_ds_q; + assign entry12_pid_d = (wr_entry12_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry12_pid_q[0:7]; + assign entry12_cmpmask_d = (wr_entry12_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry12_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry12_parity_d[0:3] = (wr_entry12_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry12_parity_q[0:3]; + assign entry12_parity_d[4:6] = (wr_entry12_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry12_parity_q[4:6]; + assign entry12_parity_d[7] = (wr_entry12_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry12_parity_q[7]; + assign entry12_parity_d[8] = (wr_entry12_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry12_parity_q[8]; + assign entry12_parity_d[9] = (wr_entry12_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry12_parity_q[9]; + assign wr_entry13_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 4'b1101)) ? 1'b1 : + 1'b0; + assign wr_entry13_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 4'b1101)) ? 1'b1 : + 1'b0; + assign entry13_epn_d[0:31] = (wr_entry13_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry13_epn_q[0:31]; + assign entry13_epn_d[32:51] = (wr_entry13_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry13_epn_q[32:51]; + assign entry13_xbit_d = (wr_entry13_sel[0] == 1'b1) ? wr_cam_data[52] : + entry13_xbit_q; + assign entry13_size_d = (wr_entry13_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry13_size_q[0:2]; + assign entry13_class_d = (wr_entry13_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry13_class_q[0:1]; + assign entry13_extclass_d = (wr_entry13_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry13_extclass_q[0:1]; + assign entry13_hv_d = (wr_entry13_sel[1] == 1'b1) ? wr_cam_data[65] : + entry13_hv_q; + assign entry13_ds_d = (wr_entry13_sel[1] == 1'b1) ? wr_cam_data[66] : + entry13_ds_q; + assign entry13_pid_d = (wr_entry13_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry13_pid_q[0:7]; + assign entry13_cmpmask_d = (wr_entry13_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry13_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry13_parity_d[0:3] = (wr_entry13_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry13_parity_q[0:3]; + assign entry13_parity_d[4:6] = (wr_entry13_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry13_parity_q[4:6]; + assign entry13_parity_d[7] = (wr_entry13_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry13_parity_q[7]; + assign entry13_parity_d[8] = (wr_entry13_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry13_parity_q[8]; + assign entry13_parity_d[9] = (wr_entry13_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry13_parity_q[9]; + assign wr_entry14_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 4'b1110)) ? 1'b1 : + 1'b0; + assign wr_entry14_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 4'b1110)) ? 1'b1 : + 1'b0; + assign entry14_epn_d[0:31] = (wr_entry14_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry14_epn_q[0:31]; + assign entry14_epn_d[32:51] = (wr_entry14_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry14_epn_q[32:51]; + assign entry14_xbit_d = (wr_entry14_sel[0] == 1'b1) ? wr_cam_data[52] : + entry14_xbit_q; + assign entry14_size_d = (wr_entry14_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry14_size_q[0:2]; + assign entry14_class_d = (wr_entry14_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry14_class_q[0:1]; + assign entry14_extclass_d = (wr_entry14_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry14_extclass_q[0:1]; + assign entry14_hv_d = (wr_entry14_sel[1] == 1'b1) ? wr_cam_data[65] : + entry14_hv_q; + assign entry14_ds_d = (wr_entry14_sel[1] == 1'b1) ? wr_cam_data[66] : + entry14_ds_q; + assign entry14_pid_d = (wr_entry14_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry14_pid_q[0:7]; + assign entry14_cmpmask_d = (wr_entry14_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry14_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry14_parity_d[0:3] = (wr_entry14_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry14_parity_q[0:3]; + assign entry14_parity_d[4:6] = (wr_entry14_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry14_parity_q[4:6]; + assign entry14_parity_d[7] = (wr_entry14_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry14_parity_q[7]; + assign entry14_parity_d[8] = (wr_entry14_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry14_parity_q[8]; + assign entry14_parity_d[9] = (wr_entry14_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry14_parity_q[9]; + assign wr_entry15_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 4'b1111)) ? 1'b1 : + 1'b0; + assign wr_entry15_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 4'b1111)) ? 1'b1 : + 1'b0; + assign entry15_epn_d[0:31] = (wr_entry15_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry15_epn_q[0:31]; + assign entry15_epn_d[32:51] = (wr_entry15_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry15_epn_q[32:51]; + assign entry15_xbit_d = (wr_entry15_sel[0] == 1'b1) ? wr_cam_data[52] : + entry15_xbit_q; + assign entry15_size_d = (wr_entry15_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry15_size_q[0:2]; + assign entry15_class_d = (wr_entry15_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry15_class_q[0:1]; + assign entry15_extclass_d = (wr_entry15_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry15_extclass_q[0:1]; + assign entry15_hv_d = (wr_entry15_sel[1] == 1'b1) ? wr_cam_data[65] : + entry15_hv_q; + assign entry15_ds_d = (wr_entry15_sel[1] == 1'b1) ? wr_cam_data[66] : + entry15_ds_q; + assign entry15_pid_d = (wr_entry15_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry15_pid_q[0:7]; + assign entry15_cmpmask_d = (wr_entry15_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry15_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry15_parity_d[0:3] = (wr_entry15_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry15_parity_q[0:3]; + assign entry15_parity_d[4:6] = (wr_entry15_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry15_parity_q[4:6]; + assign entry15_parity_d[7] = (wr_entry15_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry15_parity_q[7]; + assign entry15_parity_d[8] = (wr_entry15_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry15_parity_q[8]; + assign entry15_parity_d[9] = (wr_entry15_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry15_parity_q[9]; + + + // entry valid and thdid next state logic + assign entry0_inval = (comp_invalidate & match_vec[0]) | flash_invalidate; + assign entry0_v_muxsel[0:1] = ({entry0_inval, wr_entry0_sel[0]}); + assign entry0_v_d = (entry0_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry0_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry0_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry0_v_q; + assign entry0_thdid_d[0:3] = (wr_entry0_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry0_thdid_q[0:3]; + assign entry1_inval = (comp_invalidate & match_vec[1]) | flash_invalidate; + assign entry1_v_muxsel[0:1] = ({entry1_inval, wr_entry1_sel[0]}); + assign entry1_v_d = (entry1_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry1_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry1_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry1_v_q; + assign entry1_thdid_d[0:3] = (wr_entry1_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry1_thdid_q[0:3]; + assign entry2_inval = (comp_invalidate & match_vec[2]) | flash_invalidate; + assign entry2_v_muxsel[0:1] = ({entry2_inval, wr_entry2_sel[0]}); + assign entry2_v_d = (entry2_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry2_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry2_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry2_v_q; + assign entry2_thdid_d[0:3] = (wr_entry2_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry2_thdid_q[0:3]; + assign entry3_inval = (comp_invalidate & match_vec[3]) | flash_invalidate; + assign entry3_v_muxsel[0:1] = ({entry3_inval, wr_entry3_sel[0]}); + assign entry3_v_d = (entry3_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry3_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry3_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry3_v_q; + assign entry3_thdid_d[0:3] = (wr_entry3_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry3_thdid_q[0:3]; + assign entry4_inval = (comp_invalidate & match_vec[4]) | flash_invalidate; + assign entry4_v_muxsel[0:1] = ({entry4_inval, wr_entry4_sel[0]}); + assign entry4_v_d = (entry4_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry4_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry4_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry4_v_q; + assign entry4_thdid_d[0:3] = (wr_entry4_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry4_thdid_q[0:3]; + assign entry5_inval = (comp_invalidate & match_vec[5]) | flash_invalidate; + assign entry5_v_muxsel[0:1] = ({entry5_inval, wr_entry5_sel[0]}); + assign entry5_v_d = (entry5_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry5_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry5_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry5_v_q; + assign entry5_thdid_d[0:3] = (wr_entry5_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry5_thdid_q[0:3]; + assign entry6_inval = (comp_invalidate & match_vec[6]) | flash_invalidate; + assign entry6_v_muxsel[0:1] = ({entry6_inval, wr_entry6_sel[0]}); + assign entry6_v_d = (entry6_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry6_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry6_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry6_v_q; + assign entry6_thdid_d[0:3] = (wr_entry6_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry6_thdid_q[0:3]; + assign entry7_inval = (comp_invalidate & match_vec[7]) | flash_invalidate; + assign entry7_v_muxsel[0:1] = ({entry7_inval, wr_entry7_sel[0]}); + assign entry7_v_d = (entry7_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry7_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry7_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry7_v_q; + assign entry7_thdid_d[0:3] = (wr_entry7_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry7_thdid_q[0:3]; + assign entry8_inval = (comp_invalidate & match_vec[8]) | flash_invalidate; + assign entry8_v_muxsel[0:1] = ({entry8_inval, wr_entry8_sel[0]}); + assign entry8_v_d = (entry8_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry8_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry8_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry8_v_q; + assign entry8_thdid_d[0:3] = (wr_entry8_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry8_thdid_q[0:3]; + assign entry9_inval = (comp_invalidate & match_vec[9]) | flash_invalidate; + assign entry9_v_muxsel[0:1] = ({entry9_inval, wr_entry9_sel[0]}); + assign entry9_v_d = (entry9_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry9_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry9_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry9_v_q; + assign entry9_thdid_d[0:3] = (wr_entry9_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry9_thdid_q[0:3]; + assign entry10_inval = (comp_invalidate & match_vec[10]) | flash_invalidate; + assign entry10_v_muxsel[0:1] = ({entry10_inval, wr_entry10_sel[0]}); + assign entry10_v_d = (entry10_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry10_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry10_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry10_v_q; + assign entry10_thdid_d[0:3] = (wr_entry10_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry10_thdid_q[0:3]; + assign entry11_inval = (comp_invalidate & match_vec[11]) | flash_invalidate; + assign entry11_v_muxsel[0:1] = ({entry11_inval, wr_entry11_sel[0]}); + assign entry11_v_d = (entry11_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry11_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry11_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry11_v_q; + assign entry11_thdid_d[0:3] = (wr_entry11_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry11_thdid_q[0:3]; + assign entry12_inval = (comp_invalidate & match_vec[12]) | flash_invalidate; + assign entry12_v_muxsel[0:1] = ({entry12_inval, wr_entry12_sel[0]}); + assign entry12_v_d = (entry12_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry12_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry12_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry12_v_q; + assign entry12_thdid_d[0:3] = (wr_entry12_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry12_thdid_q[0:3]; + assign entry13_inval = (comp_invalidate & match_vec[13]) | flash_invalidate; + assign entry13_v_muxsel[0:1] = ({entry13_inval, wr_entry13_sel[0]}); + assign entry13_v_d = (entry13_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry13_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry13_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry13_v_q; + assign entry13_thdid_d[0:3] = (wr_entry13_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry13_thdid_q[0:3]; + assign entry14_inval = (comp_invalidate & match_vec[14]) | flash_invalidate; + assign entry14_v_muxsel[0:1] = ({entry14_inval, wr_entry14_sel[0]}); + assign entry14_v_d = (entry14_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry14_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry14_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry14_v_q; + assign entry14_thdid_d[0:3] = (wr_entry14_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry14_thdid_q[0:3]; + assign entry15_inval = (comp_invalidate & match_vec[15]) | flash_invalidate; + assign entry15_v_muxsel[0:1] = ({entry15_inval, wr_entry15_sel[0]}); + assign entry15_v_d = (entry15_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry15_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry15_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry15_v_q; + assign entry15_thdid_d[0:3] = (wr_entry15_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry15_thdid_q[0:3]; + + + // CAM compare data out mux + assign entry0_cam_vec = {entry0_epn_q, entry0_xbit_q, entry0_size_q, entry0_v_q, entry0_thdid_q, entry0_class_q, entry0_extclass_q, entry0_hv_q, entry0_ds_q, entry0_pid_q, entry0_cmpmask_q}; + assign entry1_cam_vec = {entry1_epn_q, entry1_xbit_q, entry1_size_q, entry1_v_q, entry1_thdid_q, entry1_class_q, entry1_extclass_q, entry1_hv_q, entry1_ds_q, entry1_pid_q, entry1_cmpmask_q}; + assign entry2_cam_vec = {entry2_epn_q, entry2_xbit_q, entry2_size_q, entry2_v_q, entry2_thdid_q, entry2_class_q, entry2_extclass_q, entry2_hv_q, entry2_ds_q, entry2_pid_q, entry2_cmpmask_q}; + assign entry3_cam_vec = {entry3_epn_q, entry3_xbit_q, entry3_size_q, entry3_v_q, entry3_thdid_q, entry3_class_q, entry3_extclass_q, entry3_hv_q, entry3_ds_q, entry3_pid_q, entry3_cmpmask_q}; + assign entry4_cam_vec = {entry4_epn_q, entry4_xbit_q, entry4_size_q, entry4_v_q, entry4_thdid_q, entry4_class_q, entry4_extclass_q, entry4_hv_q, entry4_ds_q, entry4_pid_q, entry4_cmpmask_q}; + assign entry5_cam_vec = {entry5_epn_q, entry5_xbit_q, entry5_size_q, entry5_v_q, entry5_thdid_q, entry5_class_q, entry5_extclass_q, entry5_hv_q, entry5_ds_q, entry5_pid_q, entry5_cmpmask_q}; + assign entry6_cam_vec = {entry6_epn_q, entry6_xbit_q, entry6_size_q, entry6_v_q, entry6_thdid_q, entry6_class_q, entry6_extclass_q, entry6_hv_q, entry6_ds_q, entry6_pid_q, entry6_cmpmask_q}; + assign entry7_cam_vec = {entry7_epn_q, entry7_xbit_q, entry7_size_q, entry7_v_q, entry7_thdid_q, entry7_class_q, entry7_extclass_q, entry7_hv_q, entry7_ds_q, entry7_pid_q, entry7_cmpmask_q}; + assign entry8_cam_vec = {entry8_epn_q, entry8_xbit_q, entry8_size_q, entry8_v_q, entry8_thdid_q, entry8_class_q, entry8_extclass_q, entry8_hv_q, entry8_ds_q, entry8_pid_q, entry8_cmpmask_q}; + assign entry9_cam_vec = {entry9_epn_q, entry9_xbit_q, entry9_size_q, entry9_v_q, entry9_thdid_q, entry9_class_q, entry9_extclass_q, entry9_hv_q, entry9_ds_q, entry9_pid_q, entry9_cmpmask_q}; + assign entry10_cam_vec = {entry10_epn_q, entry10_xbit_q, entry10_size_q, entry10_v_q, entry10_thdid_q, entry10_class_q, entry10_extclass_q, entry10_hv_q, entry10_ds_q, entry10_pid_q, entry10_cmpmask_q}; + assign entry11_cam_vec = {entry11_epn_q, entry11_xbit_q, entry11_size_q, entry11_v_q, entry11_thdid_q, entry11_class_q, entry11_extclass_q, entry11_hv_q, entry11_ds_q, entry11_pid_q, entry11_cmpmask_q}; + assign entry12_cam_vec = {entry12_epn_q, entry12_xbit_q, entry12_size_q, entry12_v_q, entry12_thdid_q, entry12_class_q, entry12_extclass_q, entry12_hv_q, entry12_ds_q, entry12_pid_q, entry12_cmpmask_q}; + assign entry13_cam_vec = {entry13_epn_q, entry13_xbit_q, entry13_size_q, entry13_v_q, entry13_thdid_q, entry13_class_q, entry13_extclass_q, entry13_hv_q, entry13_ds_q, entry13_pid_q, entry13_cmpmask_q}; + assign entry14_cam_vec = {entry14_epn_q, entry14_xbit_q, entry14_size_q, entry14_v_q, entry14_thdid_q, entry14_class_q, entry14_extclass_q, entry14_hv_q, entry14_ds_q, entry14_pid_q, entry14_cmpmask_q}; + assign entry15_cam_vec = {entry15_epn_q, entry15_xbit_q, entry15_size_q, entry15_v_q, entry15_thdid_q, entry15_class_q, entry15_extclass_q, entry15_hv_q, entry15_ds_q, entry15_pid_q, entry15_cmpmask_q}; + + + assign cam_cmp_data_muxsel = {(~(comp_request)), cam_hit_entry_d}; + assign cam_cmp_data_d = (cam_cmp_data_muxsel == 5'b00000) ? entry0_cam_vec : + (cam_cmp_data_muxsel == 5'b00001) ? entry1_cam_vec : + (cam_cmp_data_muxsel == 5'b00010) ? entry2_cam_vec : + (cam_cmp_data_muxsel == 5'b00011) ? entry3_cam_vec : + (cam_cmp_data_muxsel == 5'b00100) ? entry4_cam_vec : + (cam_cmp_data_muxsel == 5'b00101) ? entry5_cam_vec : + (cam_cmp_data_muxsel == 5'b00110) ? entry6_cam_vec : + (cam_cmp_data_muxsel == 5'b00111) ? entry7_cam_vec : + (cam_cmp_data_muxsel == 5'b01000) ? entry8_cam_vec : + (cam_cmp_data_muxsel == 5'b01001) ? entry9_cam_vec : + (cam_cmp_data_muxsel == 5'b01010) ? entry10_cam_vec : + (cam_cmp_data_muxsel == 5'b01011) ? entry11_cam_vec : + (cam_cmp_data_muxsel == 5'b01100) ? entry12_cam_vec : + (cam_cmp_data_muxsel == 5'b01101) ? entry13_cam_vec : + (cam_cmp_data_muxsel == 5'b01110) ? entry14_cam_vec : + (cam_cmp_data_muxsel == 5'b01111) ? entry15_cam_vec : + cam_cmp_data_q; + + assign cam_cmp_data_np1 = cam_cmp_data_q; + + // CAM read data out mux + assign rd_cam_data_muxsel = {(~(rd_val)), rw_entry}; + + assign rd_cam_data_d = (rd_cam_data_muxsel == 5'b00000) ? entry0_cam_vec : + (rd_cam_data_muxsel == 5'b00001) ? entry1_cam_vec : + (rd_cam_data_muxsel == 5'b00010) ? entry2_cam_vec : + (rd_cam_data_muxsel == 5'b00011) ? entry3_cam_vec : + (rd_cam_data_muxsel == 5'b00100) ? entry4_cam_vec : + (rd_cam_data_muxsel == 5'b00101) ? entry5_cam_vec : + (rd_cam_data_muxsel == 5'b00110) ? entry6_cam_vec : + (rd_cam_data_muxsel == 5'b00111) ? entry7_cam_vec : + (rd_cam_data_muxsel == 5'b01000) ? entry8_cam_vec : + (rd_cam_data_muxsel == 5'b01001) ? entry9_cam_vec : + (rd_cam_data_muxsel == 5'b01010) ? entry10_cam_vec : + (rd_cam_data_muxsel == 5'b01011) ? entry11_cam_vec : + (rd_cam_data_muxsel == 5'b01100) ? entry12_cam_vec : + (rd_cam_data_muxsel == 5'b01101) ? entry13_cam_vec : + (rd_cam_data_muxsel == 5'b01110) ? entry14_cam_vec : + (rd_cam_data_muxsel == 5'b01111) ? entry15_cam_vec : + rd_cam_data_q; + + // CAM compare parity out mux + assign cam_cmp_parity_d = (cam_cmp_data_muxsel == 5'b00000) ? entry0_parity_q : + (cam_cmp_data_muxsel == 5'b00001) ? entry1_parity_q : + (cam_cmp_data_muxsel == 5'b00010) ? entry2_parity_q : + (cam_cmp_data_muxsel == 5'b00011) ? entry3_parity_q : + (cam_cmp_data_muxsel == 5'b00100) ? entry4_parity_q : + (cam_cmp_data_muxsel == 5'b00101) ? entry5_parity_q : + (cam_cmp_data_muxsel == 5'b00110) ? entry6_parity_q : + (cam_cmp_data_muxsel == 5'b00111) ? entry7_parity_q : + (cam_cmp_data_muxsel == 5'b01000) ? entry8_parity_q : + (cam_cmp_data_muxsel == 5'b01001) ? entry9_parity_q : + (cam_cmp_data_muxsel == 5'b01010) ? entry10_parity_q : + (cam_cmp_data_muxsel == 5'b01011) ? entry11_parity_q : + (cam_cmp_data_muxsel == 5'b01100) ? entry12_parity_q : + (cam_cmp_data_muxsel == 5'b01101) ? entry13_parity_q : + (cam_cmp_data_muxsel == 5'b01110) ? entry14_parity_q : + (cam_cmp_data_muxsel == 5'b01111) ? entry15_parity_q : + cam_cmp_parity_q; + + assign array_cmp_data_np1[0:50] = {array_cmp_data_bram[2:31], array_cmp_data_bram[34:39], array_cmp_data_bram[41:55]}; + assign array_cmp_data_np1[51:60] = cam_cmp_parity_q; + assign array_cmp_data_np1[61:67] = array_cmp_data_bramp[66:72]; + + assign array_cmp_data = array_cmp_data_np1; + + // CAM read parity out mux + assign rd_array_data_d[51:60] = (rd_cam_data_muxsel == 5'b00000) ? entry0_parity_q : + (rd_cam_data_muxsel == 5'b00001) ? entry1_parity_q : + (rd_cam_data_muxsel == 5'b00010) ? entry2_parity_q : + (rd_cam_data_muxsel == 5'b00011) ? entry3_parity_q : + (rd_cam_data_muxsel == 5'b00100) ? entry4_parity_q : + (rd_cam_data_muxsel == 5'b00101) ? entry5_parity_q : + (rd_cam_data_muxsel == 5'b00110) ? entry6_parity_q : + (rd_cam_data_muxsel == 5'b00111) ? entry7_parity_q : + (rd_cam_data_muxsel == 5'b01000) ? entry8_parity_q : + (rd_cam_data_muxsel == 5'b01001) ? entry9_parity_q : + (rd_cam_data_muxsel == 5'b01010) ? entry10_parity_q : + (rd_cam_data_muxsel == 5'b01011) ? entry11_parity_q : + (rd_cam_data_muxsel == 5'b01100) ? entry12_parity_q : + (rd_cam_data_muxsel == 5'b01101) ? entry13_parity_q : + (rd_cam_data_muxsel == 5'b01110) ? entry14_parity_q : + (rd_cam_data_muxsel == 5'b01111) ? entry15_parity_q : + rd_array_data_q[51:60]; + + // internal bypass latch input for rpn + // using cam_cmp_data(75:78) cmpmask bits for mux selects + assign rpn_np2_d[22:33] = (comp_addr_np1_q[22:33] & {12{bypass_mux_enab_np1}}) | + (array_cmp_data_np1[0:11] & {12{~(bypass_mux_enab_np1)}}); // real page from cam-array + + //CAM_PgSize_1GB + assign rpn_np2_d[34:39] = (comp_addr_np1_q[34:39] & {6{(~(cam_cmp_data_np1[75])) | bypass_mux_enab_np1}}) | + (array_cmp_data_np1[12:17] & {6{cam_cmp_data_np1[75] & (~bypass_mux_enab_np1)}}); + + //CAM_PgSize_1GB or CAM_PgSize_16MB + assign rpn_np2_d[40:43] = (comp_addr_np1_q[40:43] & {4{(~(cam_cmp_data_np1[76])) | bypass_mux_enab_np1}}) | + (array_cmp_data_np1[18:21] & {4{cam_cmp_data_np1[76] & (~bypass_mux_enab_np1)}}); + + //CAM_PgSize_1GB or CAM_PgSize_16MB or CAM_PgSize_1MB + assign rpn_np2_d[44:47] = (comp_addr_np1_q[44:47] & {4{(~(cam_cmp_data_np1[77])) | bypass_mux_enab_np1}}) | + (array_cmp_data_np1[22:25] & {4{cam_cmp_data_np1[77] & (~bypass_mux_enab_np1)}}); + + //CAM_PgSize_Larger_than_4K + assign rpn_np2_d[48:51] = (comp_addr_np1_q[48:51] & {4{(~(cam_cmp_data_np1[78])) | bypass_mux_enab_np1}}) | + (array_cmp_data_np1[26:29] & {4{cam_cmp_data_np1[78] & (~bypass_mux_enab_np1)}}); + + // internal bypass latch input for attributes + assign attr_np2_d[0:20] = (bypass_attr_np1[0:20] & {21{bypass_mux_enab_np1}}) | + (array_cmp_data_np1[30:50] & {21{~bypass_mux_enab_np1}}); + + // new port output assignments + assign rpn_np2[22:51] = rpn_np2_q[22:51]; + assign attr_np2[0:20] = attr_np2_q[0:20]; + + //--------------------------------------------------------------------- + // matchline component instantiations + //--------------------------------------------------------------------- + + tri_cam_16x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb0( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry0_size_q), + .entry_cmpmask(entry0_cmpmask_q[0:3]), + .entry_xbit(entry0_xbit_q), + .entry_xbitmask(entry0_cmpmask_q[4:7]), + .entry_epn(entry0_epn_q), + .comp_class(comp_class), + .entry_class(entry0_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry0_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry0_hv_q), + .entry_ds(entry0_ds_q), + .state_enable(state_enable), + .entry_thdid(entry0_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry0_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry0_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[0]) + ); + + tri_cam_16x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb1( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry1_size_q), + .entry_cmpmask(entry1_cmpmask_q[0:3]), + .entry_xbit(entry1_xbit_q), + .entry_xbitmask(entry1_cmpmask_q[4:7]), + .entry_epn(entry1_epn_q), + .comp_class(comp_class), + .entry_class(entry1_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry1_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry1_hv_q), + .entry_ds(entry1_ds_q), + .state_enable(state_enable), + .entry_thdid(entry1_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry1_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry1_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[1]) + ); + + tri_cam_16x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb2( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry2_size_q), + .entry_cmpmask(entry2_cmpmask_q[0:3]), + .entry_xbit(entry2_xbit_q), + .entry_xbitmask(entry2_cmpmask_q[4:7]), + .entry_epn(entry2_epn_q), + .comp_class(comp_class), + .entry_class(entry2_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry2_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry2_hv_q), + .entry_ds(entry2_ds_q), + .state_enable(state_enable), + .entry_thdid(entry2_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry2_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry2_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[2]) + ); + + tri_cam_16x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb3( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry3_size_q), + .entry_cmpmask(entry3_cmpmask_q[0:3]), + .entry_xbit(entry3_xbit_q), + .entry_xbitmask(entry3_cmpmask_q[4:7]), + .entry_epn(entry3_epn_q), + .comp_class(comp_class), + .entry_class(entry3_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry3_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry3_hv_q), + .entry_ds(entry3_ds_q), + .state_enable(state_enable), + .entry_thdid(entry3_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry3_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry3_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[3]) + ); + + tri_cam_16x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb4( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry4_size_q), + .entry_cmpmask(entry4_cmpmask_q[0:3]), + .entry_xbit(entry4_xbit_q), + .entry_xbitmask(entry4_cmpmask_q[4:7]), + .entry_epn(entry4_epn_q), + .comp_class(comp_class), + .entry_class(entry4_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry4_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry4_hv_q), + .entry_ds(entry4_ds_q), + .state_enable(state_enable), + .entry_thdid(entry4_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry4_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry4_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[4]) + ); + + tri_cam_16x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb5( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry5_size_q), + .entry_cmpmask(entry5_cmpmask_q[0:3]), + .entry_xbit(entry5_xbit_q), + .entry_xbitmask(entry5_cmpmask_q[4:7]), + .entry_epn(entry5_epn_q), + .comp_class(comp_class), + .entry_class(entry5_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry5_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry5_hv_q), + .entry_ds(entry5_ds_q), + .state_enable(state_enable), + .entry_thdid(entry5_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry5_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry5_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[5]) + ); + + tri_cam_16x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb6( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry6_size_q), + .entry_cmpmask(entry6_cmpmask_q[0:3]), + .entry_xbit(entry6_xbit_q), + .entry_xbitmask(entry6_cmpmask_q[4:7]), + .entry_epn(entry6_epn_q), + .comp_class(comp_class), + .entry_class(entry6_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry6_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry6_hv_q), + .entry_ds(entry6_ds_q), + .state_enable(state_enable), + .entry_thdid(entry6_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry6_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry6_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[6]) + ); + + tri_cam_16x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb7( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry7_size_q), + .entry_cmpmask(entry7_cmpmask_q[0:3]), + .entry_xbit(entry7_xbit_q), + .entry_xbitmask(entry7_cmpmask_q[4:7]), + .entry_epn(entry7_epn_q), + .comp_class(comp_class), + .entry_class(entry7_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry7_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry7_hv_q), + .entry_ds(entry7_ds_q), + .state_enable(state_enable), + .entry_thdid(entry7_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry7_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry7_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[7]) + ); + + tri_cam_16x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb8( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry8_size_q), + .entry_cmpmask(entry8_cmpmask_q[0:3]), + .entry_xbit(entry8_xbit_q), + .entry_xbitmask(entry8_cmpmask_q[4:7]), + .entry_epn(entry8_epn_q), + .comp_class(comp_class), + .entry_class(entry8_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry8_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry8_hv_q), + .entry_ds(entry8_ds_q), + .state_enable(state_enable), + .entry_thdid(entry8_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry8_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry8_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[8]) + ); + + tri_cam_16x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb9( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry9_size_q), + .entry_cmpmask(entry9_cmpmask_q[0:3]), + .entry_xbit(entry9_xbit_q), + .entry_xbitmask(entry9_cmpmask_q[4:7]), + .entry_epn(entry9_epn_q), + .comp_class(comp_class), + .entry_class(entry9_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry9_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry9_hv_q), + .entry_ds(entry9_ds_q), + .state_enable(state_enable), + .entry_thdid(entry9_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry9_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry9_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[9]) + ); + + tri_cam_16x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb10( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry10_size_q), + .entry_cmpmask(entry10_cmpmask_q[0:3]), + .entry_xbit(entry10_xbit_q), + .entry_xbitmask(entry10_cmpmask_q[4:7]), + .entry_epn(entry10_epn_q), + .comp_class(comp_class), + .entry_class(entry10_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry10_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry10_hv_q), + .entry_ds(entry10_ds_q), + .state_enable(state_enable), + .entry_thdid(entry10_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry10_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry10_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[10]) + ); + + tri_cam_16x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb11( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry11_size_q), + .entry_cmpmask(entry11_cmpmask_q[0:3]), + .entry_xbit(entry11_xbit_q), + .entry_xbitmask(entry11_cmpmask_q[4:7]), + .entry_epn(entry11_epn_q), + .comp_class(comp_class), + .entry_class(entry11_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry11_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry11_hv_q), + .entry_ds(entry11_ds_q), + .state_enable(state_enable), + .entry_thdid(entry11_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry11_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry11_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[11]) + ); + + tri_cam_16x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb12( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry12_size_q), + .entry_cmpmask(entry12_cmpmask_q[0:3]), + .entry_xbit(entry12_xbit_q), + .entry_xbitmask(entry12_cmpmask_q[4:7]), + .entry_epn(entry12_epn_q), + .comp_class(comp_class), + .entry_class(entry12_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry12_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry12_hv_q), + .entry_ds(entry12_ds_q), + .state_enable(state_enable), + .entry_thdid(entry12_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry12_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry12_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[12]) + ); + + tri_cam_16x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb13( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry13_size_q), + .entry_cmpmask(entry13_cmpmask_q[0:3]), + .entry_xbit(entry13_xbit_q), + .entry_xbitmask(entry13_cmpmask_q[4:7]), + .entry_epn(entry13_epn_q), + .comp_class(comp_class), + .entry_class(entry13_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry13_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry13_hv_q), + .entry_ds(entry13_ds_q), + .state_enable(state_enable), + .entry_thdid(entry13_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry13_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry13_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[13]) + ); + + tri_cam_16x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb14( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry14_size_q), + .entry_cmpmask(entry14_cmpmask_q[0:3]), + .entry_xbit(entry14_xbit_q), + .entry_xbitmask(entry14_cmpmask_q[4:7]), + .entry_epn(entry14_epn_q), + .comp_class(comp_class), + .entry_class(entry14_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry14_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry14_hv_q), + .entry_ds(entry14_ds_q), + .state_enable(state_enable), + .entry_thdid(entry14_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry14_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry14_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[14]) + ); + + tri_cam_16x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb15( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry15_size_q), + .entry_cmpmask(entry15_cmpmask_q[0:3]), + .entry_xbit(entry15_xbit_q), + .entry_xbitmask(entry15_cmpmask_q[4:7]), + .entry_epn(entry15_epn_q), + .comp_class(comp_class), + .entry_class(entry15_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry15_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry15_hv_q), + .entry_ds(entry15_ds_q), + .state_enable(state_enable), + .entry_thdid(entry15_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry15_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry15_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[15]) + ); + + + //--------------------------------------------------------------------- + // BRAM signal assignments + //--------------------------------------------------------------------- + assign bram0_wea = wr_array_val[0] & gate_fq; + assign bram1_wea = wr_array_val[1] & gate_fq; + assign bram2_wea = wr_array_val[1] & gate_fq; + + assign bram0_addra[9 - NUM_ENTRY_LOG2:8] = rw_entry[0:NUM_ENTRY_LOG2 - 1]; + assign bram1_addra[11 - NUM_ENTRY_LOG2:10] = rw_entry[0:NUM_ENTRY_LOG2 - 1]; + assign bram2_addra[10 - NUM_ENTRY_LOG2:9] = rw_entry[0:NUM_ENTRY_LOG2 - 1]; + + assign bram0_addrb[9 - NUM_ENTRY_LOG2:8] = cam_hit_entry_q; + assign bram1_addrb[11 - NUM_ENTRY_LOG2:10] = cam_hit_entry_q; + assign bram2_addrb[10 - NUM_ENTRY_LOG2:9] = cam_hit_entry_q; + + // Unused Address Bits + assign bram0_addra[0:8 - NUM_ENTRY_LOG2] = {9-NUM_ENTRY_LOG2{1'b0}}; + assign bram0_addrb[0:8 - NUM_ENTRY_LOG2] = {9-NUM_ENTRY_LOG2{1'b0}}; + assign bram1_addra[0:10 - NUM_ENTRY_LOG2] = {11-NUM_ENTRY_LOG2{1'b0}}; + assign bram1_addrb[0:10 - NUM_ENTRY_LOG2] = {11-NUM_ENTRY_LOG2{1'b0}}; + assign bram2_addra[0:9 - NUM_ENTRY_LOG2] = {10-NUM_ENTRY_LOG2{1'b0}}; + assign bram2_addrb[0:9 - NUM_ENTRY_LOG2] = {10-NUM_ENTRY_LOG2{1'b0}}; + + // This ram houses the RPN(20:51) bits, wr_array_data_bram(0:31) + // uses wr_array_val(0), parity is wr_array_data_bram(66:69) + RAMB16_S36_S36 + #(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only + bram0( + .CLKA(clk2x), + .CLKB(clk2x), + .SSRA(sreset_q), + .SSRB(sreset_q), + .ADDRA(bram0_addra), + .ADDRB(bram0_addrb), + .DIA(wr_array_data_bram[0:31]), + .DIB(32'b0), + .DOA(rd_array_data_d_std[0:31]), + .DOB(array_cmp_data_bram_std[0:31]), + .DOPA(rd_array_data_d_std[66:69]), + .DOPB(array_cmp_data_bramp_std[66:69]), + .DIPA(wr_array_data_bram[66:69]), + .DIPB(4'b0), + .ENA(1'b1), + .ENB(1'b1), + .WEA(bram0_wea), + .WEB(1'b0) + ); + + // This ram houses the RPN(18:19),R,C,4xResv bits, wr_array_data_bram(32:39) + // uses wr_array_val(1), parity is wr_array_data_bram(70) + RAMB16_S9_S9 + #(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only + bram1( + .CLKA(clk2x), + .CLKB(clk2x), + .SSRA(sreset_q), + .SSRB(sreset_q), + .ADDRA(bram1_addra), + .ADDRB(bram1_addrb), + .DIA(wr_array_data_bram[32:39]), + .DIB(8'b0), + .DOA(rd_array_data_d_std[32:39]), + .DOB(array_cmp_data_bram_std[32:39]), + .DOPA(rd_array_data_d_std[70:70]), + .DOPB(array_cmp_data_bramp_std[70:70]), + .DIPA(wr_array_data_bram[70:70]), + .DIPB(1'b0), + .ENA(1'b1), + .ENB(1'b1), + .WEA(bram1_wea), + .WEB(1'b0) + ); + + // This ram houses the 1xResv,U0-U3,WIMGE,UX,UW,UR,SX,SW,SR bits, wr_array_data_bram(40:55) + // uses wr_array_val(1), parity is wr_array_data_bram(71:72) + RAMB16_S18_S18 + #(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only + bram2( + .CLKA(clk2x), + .CLKB(clk2x), + .SSRA(sreset_q), + .SSRB(sreset_q), + .ADDRA(bram2_addra), + .ADDRB(bram2_addrb), + .DIA(wr_array_data_bram[40:55]), + .DIB(16'b0), + .DOA(rd_array_data_d_std[40:55]), + .DOB(array_cmp_data_bram_std[40:55]), + .DOPA(rd_array_data_d_std[71:72]), + .DOPB(array_cmp_data_bramp_std[71:72]), + .DIPA(wr_array_data_bram[71:72]), + .DIPB(2'b0), + .ENA(1'b1), + .ENB(1'b1), + .WEA(bram2_wea), + .WEB(1'b0) + ); + + // array write data swizzle -> convert 68-bit data to 73-bit bram data + // 32x143 version, 42b RA + // wr_array_data + // 0:29 - RPN + // 30:31 - R,C + // 32:35 - ResvAttr + // 36:39 - U0-U3 + // 40:44 - WIMGE + // 45:47 - UX,UW,UR + // 48:50 - SX,SW,SR + // 51:60 - CAM parity + // 61:67 - Array parity + // + // RTX layout in A2_AvpEratHelper.C + // ram0(0:31): 00 & RPN(0:29) + // ram1(0:7) : 00 & R,C,ResvAttr(0:3) + // ram2(0:15): '0' & U(0:3),WIMGE,UX,UW,UR,SX,SW,SR + assign wr_array_data_bram[0:72] = {2'b00, wr_array_data[0:29], 2'b00, wr_array_data[30:35], 1'b0, wr_array_data[36:50], wr_array_data[51:60], wr_array_data[61:67]}; + + assign rd_array_data_d_std[56:65] = 10'b0; // tie off unused bits + + assign rd_array_data_d[0:29] = rd_array_data_d_std[2:31]; + assign rd_array_data_d[30:35] = rd_array_data_d_std[34:39]; + assign rd_array_data_d[36:50] = rd_array_data_d_std[41:55]; + assign rd_array_data_d[61:67] = rd_array_data_d_std[66:72]; + assign array_cmp_data_bram = array_cmp_data_bram_std; + assign array_cmp_data_bramp = array_cmp_data_bramp_std; + + //--------------------------------------------------------------------- + // entity output assignments + //--------------------------------------------------------------------- + assign rd_array_data = rd_array_data_q; + assign cam_cmp_data = cam_cmp_data_q; + assign rd_cam_data = rd_cam_data_q; + + assign entry_valid[0] = entry0_v_q; + assign entry_valid[1] = entry1_v_q; + assign entry_valid[2] = entry2_v_q; + assign entry_valid[3] = entry3_v_q; + assign entry_valid[4] = entry4_v_q; + assign entry_valid[5] = entry5_v_q; + assign entry_valid[6] = entry6_v_q; + assign entry_valid[7] = entry7_v_q; + assign entry_valid[8] = entry8_v_q; + assign entry_valid[9] = entry9_v_q; + assign entry_valid[10] = entry10_v_q; + assign entry_valid[11] = entry11_v_q; + assign entry_valid[12] = entry12_v_q; + assign entry_valid[13] = entry13_v_q; + assign entry_valid[14] = entry14_v_q; + assign entry_valid[15] = entry15_v_q; + + assign entry_match = entry_match_q; + + assign cam_hit_entry = cam_hit_entry_q; + assign cam_hit = cam_hit_q; + + assign func_scan_out = func_scan_in; + assign regfile_scan_out = regfile_scan_in; + assign time_scan_out = time_scan_in; + + assign unused = |{gnd, vdd, vcs, nclk, tc_ccflush_dc, tc_scan_dis_dc_b, tc_scan_diag_dc, + tc_lbist_en_dc, an_ac_atpg_en_dc, lcb_d_mode_dc, lcb_clkoff_dc_b, + lcb_act_dis_dc, lcb_mpw1_dc_b, lcb_mpw2_dc_b, lcb_delay_lclkr_dc, + pc_sg_2, pc_func_slp_sl_thold_2, pc_func_slp_nsl_thold_2, pc_regf_slp_sl_thold_2, + pc_time_sl_thold_2, pc_fce_2, array_cmp_data_bram[0:1], array_cmp_data_bram[32:33], + array_cmp_data_bram[40], wr_array_data_bram[56:65], + cam_cmp_data_np1[0:74], cam_cmp_data_np1[79:CAM_DATA_WIDTH-1], + rd_array_data_d_std[0:1], rd_array_data_d_std[32:33], + rd_array_data_d_std[40], rd_array_data_d_std[56:65], rd_val_late, wr_val_early}; +endmodule diff --git a/dev/verilog/trilib/tri_cam_16x143_1r1w1c_matchline.v b/dev/verilog/trilib/tri_cam_16x143_1r1w1c_matchline.v new file mode 100755 index 0000000..f2a7fe6 --- /dev/null +++ b/dev/verilog/trilib/tri_cam_16x143_1r1w1c_matchline.v @@ -0,0 +1,471 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//******************************************************************** +//* +//* TITLE: I-ERAT CAM Match Line Logic for Functional Model +//* +//* NAME: tri_cam_16x143_1r1w1c_matchline +//* +//********************************************************************* + +module tri_cam_16x143_1r1w1c_matchline( + addr_in, + addr_enable, + comp_pgsize, + pgsize_enable, + entry_size, + entry_cmpmask, + entry_xbit, + entry_xbitmask, + entry_epn, + comp_class, + entry_class, + class_enable, + comp_extclass, + entry_extclass, + extclass_enable, + comp_state, + entry_hv, + entry_ds, + state_enable, + entry_thdid, + comp_thdid, + thdid_enable, + entry_pid, + comp_pid, + pid_enable, + entry_v, + comp_invalidate, + match +); + parameter HAVE_XBIT = 1; + parameter NUM_PGSIZES = 5; + parameter HAVE_CMPMASK = 1; + parameter CMPMASK_WIDTH = 4; + + // @{default:nclk}@ + input [0:51] addr_in; + input [0:1] addr_enable; + input [0:2] comp_pgsize; + input pgsize_enable; + input [0:2] entry_size; + input [0:CMPMASK_WIDTH-1] entry_cmpmask; + input entry_xbit; + input [0:CMPMASK_WIDTH-1] entry_xbitmask; + input [0:51] entry_epn; + input [0:1] comp_class; + input [0:1] entry_class; + input [0:2] class_enable; + input [0:1] comp_extclass; + input [0:1] entry_extclass; + input [0:1] extclass_enable; + input [0:1] comp_state; + input entry_hv; + input entry_ds; + input [0:1] state_enable; + input [0:3] entry_thdid; + input [0:3] comp_thdid; + input [0:1] thdid_enable; + input [0:7] entry_pid; + input [0:7] comp_pid; + input pid_enable; + input entry_v; + input comp_invalidate; + + output match; + + // tri_cam_16x143_1r1w1c_matchline + + //---------------------------------------------------------------------- + // Signals + //---------------------------------------------------------------------- + + wire [34:51] entry_epn_b; + wire function_50_51; + wire function_48_51; + wire function_46_51; + wire function_44_51; + wire function_40_51; + wire function_36_51; + wire function_34_51; + wire pgsize_eq_16K; + wire pgsize_eq_64K; + wire pgsize_eq_256K; + wire pgsize_eq_1M; + wire pgsize_eq_16M; + wire pgsize_eq_256M; + wire pgsize_eq_1G; + wire pgsize_gte_16K; + wire pgsize_gte_64K; + wire pgsize_gte_256K; + wire pgsize_gte_1M; + wire pgsize_gte_16M; + wire pgsize_gte_256M; + wire pgsize_gte_1G; + wire comp_or_34_35; + wire comp_or_34_39; + wire comp_or_36_39; + wire comp_or_40_43; + wire comp_or_44_45; + wire comp_or_44_47; + wire comp_or_46_47; + wire comp_or_48_49; + wire comp_or_48_51; + wire comp_or_50_51; + wire [0:72] match_line; + wire pgsize_match; + wire addr_match; + wire class_match; + wire extclass_match; + wire state_match; + wire thdid_match; + wire pid_match; + (* analysis_not_referenced="true" *) + wire [0:2] unused; + + assign match_line[0:72] = (~({entry_epn[0:51], entry_size[0:2], entry_class[0:1], entry_extclass[0:1], entry_hv, entry_ds, entry_pid[0:7], entry_thdid[0:3]} ^ + {addr_in[0:51], comp_pgsize[0:2], comp_class[0:1], comp_extclass[0:1], comp_state[0:1], comp_pid[0:7], comp_thdid[0:3]})); + + generate + begin + if (NUM_PGSIZES == 8) + begin : numpgsz8 + // tie off unused signals + assign comp_or_34_39 = 1'b0; + assign comp_or_44_47 = 1'b0; + assign comp_or_48_51 = 1'b0; + assign unused[0] = |{comp_or_34_39, comp_or_44_47, comp_or_48_51}; + + assign entry_epn_b[34:51] = (~(entry_epn[34:51])); + + if (HAVE_CMPMASK == 0) + begin + assign pgsize_eq_1G = ( entry_size[0] & entry_size[1] & entry_size[2]); + assign pgsize_eq_256M = ( entry_size[0] & entry_size[1] & (~(entry_size[2]))); + assign pgsize_eq_16M = ( entry_size[0] & (~(entry_size[1])) & entry_size[2]); + assign pgsize_eq_1M = ( entry_size[0] & (~(entry_size[1])) & (~(entry_size[2]))); + assign pgsize_eq_256K = ((~(entry_size[0])) & entry_size[1] & entry_size[2]); + assign pgsize_eq_64K = ((~(entry_size[0])) & entry_size[1] & (~(entry_size[2]))); + assign pgsize_eq_16K = ((~(entry_size[0])) & (~(entry_size[1])) & entry_size[2]); + + assign pgsize_gte_1G = ( entry_size[0] & entry_size[1] & entry_size[2]); + assign pgsize_gte_256M = ( entry_size[0] & entry_size[1] & (~(entry_size[2]))) | pgsize_gte_1G; + assign pgsize_gte_16M = ( entry_size[0] & (~(entry_size[1])) & entry_size[2]) | pgsize_gte_256M; + assign pgsize_gte_1M = ( entry_size[0] & (~(entry_size[1])) & (~(entry_size[2]))) | pgsize_gte_16M; + assign pgsize_gte_256K = ((~(entry_size[0])) & entry_size[1] & entry_size[2]) | pgsize_gte_1M; + assign pgsize_gte_64K = ((~(entry_size[0])) & entry_size[1] & (~(entry_size[2]))) | pgsize_gte_256K; + assign pgsize_gte_16K = ((~(entry_size[0])) & (~(entry_size[1])) & entry_size[2]) | pgsize_gte_64K; + + assign unused[1] = |{entry_cmpmask, entry_xbitmask}; + end + + if (HAVE_CMPMASK == 1) + begin + // size entry_cmpmask: 0123456 + // 1GB 0000000 + // 256MB 1000000 + // 16MB 1100000 + // 1MB 1110000 + // 256KB 1111000 + // 64KB 1111100 + // 16KB 1111110 + // 4KB 1111111 + assign pgsize_gte_1G = (~entry_cmpmask[0]); + assign pgsize_gte_256M = (~entry_cmpmask[1]); + assign pgsize_gte_16M = (~entry_cmpmask[2]); + assign pgsize_gte_1M = (~entry_cmpmask[3]); + assign pgsize_gte_256K = (~entry_cmpmask[4]); + assign pgsize_gte_64K = (~entry_cmpmask[5]); + assign pgsize_gte_16K = (~entry_cmpmask[6]); + + // size entry_xbitmask: 0123456 + // 1GB 1000000 + // 256MB 0100000 + // 16MB 0010000 + // 1MB 0001000 + // 256KB 0000100 + // 64KB 0000010 + // 16KB 0000001 + // 4KB 0000000 + assign pgsize_eq_1G = entry_xbitmask[0]; + assign pgsize_eq_256M = entry_xbitmask[1]; + assign pgsize_eq_16M = entry_xbitmask[2]; + assign pgsize_eq_1M = entry_xbitmask[3]; + assign pgsize_eq_256K = entry_xbitmask[4]; + assign pgsize_eq_64K = entry_xbitmask[5]; + assign pgsize_eq_16K = entry_xbitmask[6]; + + assign unused[1] = 1'b0; + end + + if (HAVE_XBIT == 0) + begin + assign function_34_51 = 1'b0; + assign function_36_51 = 1'b0; + assign function_40_51 = 1'b0; + assign function_44_51 = 1'b0; + assign function_46_51 = 1'b0; + assign function_48_51 = 1'b0; + assign function_50_51 = 1'b0; + assign unused[2] = |{function_34_51, function_36_51, function_40_51, function_44_51, + function_46_51, function_48_51, function_50_51, entry_xbit, + entry_epn_b, pgsize_eq_1G, pgsize_eq_256M, pgsize_eq_16M, + pgsize_eq_1M, pgsize_eq_256K, pgsize_eq_64K, pgsize_eq_16K}; + end + + if (HAVE_XBIT != 0) + begin + assign function_34_51 = (~(entry_xbit)) | (~(pgsize_eq_1G)) | (|(entry_epn_b[34:51] & addr_in[34:51])); + assign function_36_51 = (~(entry_xbit)) | (~(pgsize_eq_256M)) | (|(entry_epn_b[36:51] & addr_in[36:51])); + assign function_40_51 = (~(entry_xbit)) | (~(pgsize_eq_16M)) | (|(entry_epn_b[40:51] & addr_in[40:51])); + assign function_44_51 = (~(entry_xbit)) | (~(pgsize_eq_1M)) | (|(entry_epn_b[44:51] & addr_in[44:51])); + assign function_46_51 = (~(entry_xbit)) | (~(pgsize_eq_256K)) | (|(entry_epn_b[46:51] & addr_in[46:51])); + assign function_48_51 = (~(entry_xbit)) | (~(pgsize_eq_64K)) | (|(entry_epn_b[48:51] & addr_in[48:51])); + assign function_50_51 = (~(entry_xbit)) | (~(pgsize_eq_16K)) | (|(entry_epn_b[50:51] & addr_in[50:51])); + assign unused[2] = 1'b0; + end + + assign comp_or_50_51 = (&(match_line[50:51])) | pgsize_gte_16K; + assign comp_or_48_49 = (&(match_line[48:49])) | pgsize_gte_64K; + assign comp_or_46_47 = (&(match_line[46:47])) | pgsize_gte_256K; + assign comp_or_44_45 = (&(match_line[44:45])) | pgsize_gte_1M; + assign comp_or_40_43 = (&(match_line[40:43])) | pgsize_gte_16M; + assign comp_or_36_39 = (&(match_line[36:39])) | pgsize_gte_256M; + assign comp_or_34_35 = (&(match_line[34:35])) | pgsize_gte_1G; + + if (HAVE_XBIT == 0) + begin + assign addr_match = (comp_or_34_35 & // Ignore functions based on page size + comp_or_36_39 & + comp_or_40_43 & + comp_or_44_45 & + comp_or_46_47 & + comp_or_48_49 & + comp_or_50_51 & + (&(match_line[31:33])) & // Regular compare largest page size + ((&(match_line[0:30])) | (~(addr_enable[1])))) | // ignored part of epn + (~(addr_enable[0])); // Include address as part of compare, + // should never ignore for regular compare/read. + // Could ignore for compare/invalidate + end + + if (HAVE_XBIT != 0) + begin + assign addr_match = (function_50_51 & // Exclusion functions + function_48_51 & + function_46_51 & + function_44_51 & + function_40_51 & + function_36_51 & + function_34_51 & + comp_or_34_35 & // Ignore functions based on page size + comp_or_36_39 & + comp_or_40_43 & + comp_or_44_45 & + comp_or_46_47 & + comp_or_48_49 & + comp_or_50_51 & + (&(match_line[31:33])) & // Regular compare largest page size + (&(match_line[0:30]) | (~(addr_enable[1])))) | // ignored part of epn + (~(addr_enable[0])); // Include address as part of compare, + // should never ignore for regular compare/read. + // Could ignore for compare/invalidate + end + end // numpgsz8: NUM_PGSIZES = 8 + + + if (NUM_PGSIZES == 5) + begin : numpgsz5 + // tie off unused signals + assign function_50_51 = 1'b0; + assign function_46_51 = 1'b0; + assign function_36_51 = 1'b0; + assign pgsize_eq_16K = 1'b0; + assign pgsize_eq_256K = 1'b0; + assign pgsize_eq_256M = 1'b0; + assign pgsize_gte_16K = 1'b0; + assign pgsize_gte_256K = 1'b0; + assign pgsize_gte_256M = 1'b0; + assign comp_or_34_35 = 1'b0; + assign comp_or_36_39 = 1'b0; + assign comp_or_44_45 = 1'b0; + assign comp_or_46_47 = 1'b0; + assign comp_or_48_49 = 1'b0; + assign comp_or_50_51 = 1'b0; + assign unused[0] = |{function_50_51, function_46_51, function_36_51, + pgsize_eq_16K, pgsize_eq_256K, pgsize_eq_256M, + pgsize_gte_16K, pgsize_gte_256K, pgsize_gte_256M, + comp_or_34_35, comp_or_36_39, comp_or_44_45, + comp_or_46_47, comp_or_48_49, comp_or_50_51}; + + assign entry_epn_b[34:51] = (~(entry_epn[34:51])); + + if (HAVE_CMPMASK == 0) + begin + // 110 + assign pgsize_eq_1G = ( entry_size[0] & entry_size[1] & (~(entry_size[2]))); + // 111 + assign pgsize_eq_16M = ( entry_size[0] & entry_size[1] & entry_size[2]); + // 101 + assign pgsize_eq_1M = ( entry_size[0] & (~(entry_size[1])) & entry_size[2]); + // 011 + assign pgsize_eq_64K = ((~(entry_size[0])) & entry_size[1] & entry_size[2]); + + assign pgsize_gte_1G = ( entry_size[0] & entry_size[1] & (~(entry_size[2]))); + assign pgsize_gte_16M = ( entry_size[0] & entry_size[1] & entry_size[2]) | pgsize_gte_1G; + assign pgsize_gte_1M = ( entry_size[0] & (~(entry_size[1])) & entry_size[2]) | pgsize_gte_16M; + assign pgsize_gte_64K = ((~(entry_size[0])) & entry_size[1] & entry_size[2]) | pgsize_gte_1M; + + assign unused[1] = |{entry_cmpmask, entry_xbitmask}; + end + + if (HAVE_CMPMASK == 1) + begin + // size entry_cmpmask: 0123 + // 1GB 0000 + // 16MB 1000 + // 1MB 1100 + // 64KB 1110 + // 4KB 1111 + assign pgsize_gte_1G = (~entry_cmpmask[0]); + assign pgsize_gte_16M = (~entry_cmpmask[1]); + assign pgsize_gte_1M = (~entry_cmpmask[2]); + assign pgsize_gte_64K = (~entry_cmpmask[3]); + + // size entry_xbitmask: 0123 + // 1GB 1000 + // 16MB 0100 + // 1MB 0010 + // 64KB 0001 + // 4KB 0000 + assign pgsize_eq_1G = entry_xbitmask[0]; + assign pgsize_eq_16M = entry_xbitmask[1]; + assign pgsize_eq_1M = entry_xbitmask[2]; + assign pgsize_eq_64K = entry_xbitmask[3]; + + assign unused[1] = 1'b0; + end + + if (HAVE_XBIT == 0) + begin + assign function_34_51 = 1'b0; + assign function_40_51 = 1'b0; + assign function_44_51 = 1'b0; + assign function_48_51 = 1'b0; + assign unused[2] = |{function_34_51, function_40_51, function_44_51, + function_48_51, entry_xbit, entry_epn_b, + pgsize_eq_1G, pgsize_eq_16M, pgsize_eq_1M, pgsize_eq_64K}; + end + + if (HAVE_XBIT != 0) + begin + // 1G + assign function_34_51 = (~(entry_xbit)) | (~(pgsize_eq_1G)) | (|(entry_epn_b[34:51] & addr_in[34:51])); + // 16M + assign function_40_51 = (~(entry_xbit)) | (~(pgsize_eq_16M)) | (|(entry_epn_b[40:51] & addr_in[40:51])); + // 1M + assign function_44_51 = (~(entry_xbit)) | (~(pgsize_eq_1M)) | (|(entry_epn_b[44:51] & addr_in[44:51])); + // 64K + assign function_48_51 = (~(entry_xbit)) | (~(pgsize_eq_64K)) | (|(entry_epn_b[48:51] & addr_in[48:51])); + assign unused[2] = 1'b0; + end + + assign comp_or_48_51 = (&(match_line[48:51])) | pgsize_gte_64K; + assign comp_or_44_47 = (&(match_line[44:47])) | pgsize_gte_1M; + assign comp_or_40_43 = (&(match_line[40:43])) | pgsize_gte_16M; + assign comp_or_34_39 = (&(match_line[34:39])) | pgsize_gte_1G; + + if (HAVE_XBIT == 0) + begin + assign addr_match = (comp_or_34_39 & // Ignore functions based on page size + comp_or_40_43 & + comp_or_44_47 & + comp_or_48_51 & + (&(match_line[31:33])) & // Regular compare largest page size + ((&(match_line[0:30])) | (~(addr_enable[1])))) | // ignored part of epn + (~(addr_enable[0])); // Include address as part of compare, + // should never ignore for regular compare/read. + // Could ignore for compare/invalidate + end + + if (HAVE_XBIT != 0) + begin + assign addr_match = (function_48_51 & + function_44_51 & + function_40_51 & + function_34_51 & + comp_or_34_39 & // Ignore functions based on page size + comp_or_40_43 & + comp_or_44_47 & + comp_or_48_51 & + (&(match_line[31:33])) & // Regular compare largest page size + ((&(match_line[0:30])) | (~(addr_enable[1])))) | // ignored part of epn + (~(addr_enable[0])); // Include address as part of compare, + // should never ignore for regular compare/read. + // Could ignore for compare/invalidate + end + end // numpgsz5: NUM_PGSIZES = 5 + + + assign pgsize_match = (&(match_line[52:54])) | (~(pgsize_enable)); + + assign class_match = (match_line[55] | (~(class_enable[0]))) & + (match_line[56] | (~(class_enable[1]))) & + ((&(match_line[55:56])) | (~(class_enable[2])) | + ((~(entry_extclass[1])) & (~comp_invalidate))); // pid_nz bit + + assign extclass_match = (match_line[57] | (~(extclass_enable[0]))) & // iprot bit + (match_line[58] | (~(extclass_enable[1]))); // pid_nz bit + + assign state_match = (match_line[59] | (~(state_enable[0]))) & + (match_line[60] | (~(state_enable[1]))); + + assign thdid_match = (|(entry_thdid[0:3] & comp_thdid[0:3]) | (~(thdid_enable[0]))) & + (&(match_line[69:72]) | (~(thdid_enable[1])) | + ((~(entry_extclass[1])) & (~comp_invalidate))); // pid_nz bit + + assign pid_match = (&(match_line[61:68])) | + // entry_pid=0 ignores pid match for compares, + // but not for invalidates. + ((~(entry_extclass[1])) & (~comp_invalidate)) | // pid_nz bit + (~(pid_enable)); + + assign match = addr_match & // Address compare + pgsize_match & // Size compare + class_match & // Class compare + extclass_match & // ExtClass compare + state_match & // State compare + thdid_match & // ThdID compare + pid_match & // PID compare + entry_v; // Valid + end + endgenerate +endmodule diff --git a/dev/verilog/trilib/tri_cam_32x143_1r1w1c.v b/dev/verilog/trilib/tri_cam_32x143_1r1w1c.v new file mode 100755 index 0000000..71457cf --- /dev/null +++ b/dev/verilog/trilib/tri_cam_32x143_1r1w1c.v @@ -0,0 +1,4851 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// VHDL 1076 Macro Expander C version 07/11/00 +// job was run on Mon Nov 8 10:36:46 2010 + +//******************************************************************** +//* TITLE: I-ERAT CAM Tri-Library Model +//* NAME: tri_cam_32x143_1r1w1c +//******************************************************************** + +`include "tri_a2o.vh" + +module tri_cam_32x143_1r1w1c( + gnd, + vdd, + vcs, + nclk, + tc_ccflush_dc, + tc_scan_dis_dc_b, + tc_scan_diag_dc, + tc_lbist_en_dc, + an_ac_atpg_en_dc, + lcb_d_mode_dc, + lcb_clkoff_dc_b, + lcb_act_dis_dc, + lcb_mpw1_dc_b, + lcb_mpw2_dc_b, + lcb_delay_lclkr_dc, + pc_sg_2, + pc_func_slp_sl_thold_2, + pc_func_slp_nsl_thold_2, + pc_regf_slp_sl_thold_2, + pc_time_sl_thold_2, + pc_fce_2, + func_scan_in, + func_scan_out, + regfile_scan_in, + regfile_scan_out, + time_scan_in, + time_scan_out, + rd_val, + rd_val_late, + rw_entry, + wr_array_data, + wr_cam_data, + wr_array_val, + wr_cam_val, + wr_val_early, + comp_request, + comp_addr, + addr_enable, + comp_pgsize, + pgsize_enable, + comp_class, + class_enable, + comp_extclass, + extclass_enable, + comp_state, + state_enable, + comp_thdid, + thdid_enable, + comp_pid, + pid_enable, + comp_invalidate, + flash_invalidate, + array_cmp_data, + rd_array_data, + cam_cmp_data, + cam_hit, + cam_hit_entry, + entry_match, + entry_valid, + rd_cam_data, + bypass_mux_enab_np1, + bypass_attr_np1, + attr_np2, + rpn_np2 +); + parameter CAM_DATA_WIDTH = 84; + parameter ARRAY_DATA_WIDTH = 68; + parameter RPN_WIDTH = 30; + parameter NUM_ENTRY = 32; + parameter NUM_ENTRY_LOG2 = 5; + + // Power Pins + inout gnd; + inout vdd; + inout vcs; + + // Clocks and Scan Cntls + input [0:`NCLK_WIDTH-1] nclk; + input tc_ccflush_dc; + input tc_scan_dis_dc_b; + input tc_scan_diag_dc; + input tc_lbist_en_dc; + input an_ac_atpg_en_dc; + + input lcb_d_mode_dc; + input lcb_clkoff_dc_b; + input lcb_act_dis_dc; + input [0:3] lcb_mpw1_dc_b; + input lcb_mpw2_dc_b; + input [0:3] lcb_delay_lclkr_dc; + + input pc_sg_2; + input pc_func_slp_sl_thold_2; + input pc_func_slp_nsl_thold_2; + input pc_regf_slp_sl_thold_2; + input pc_time_sl_thold_2; + input pc_fce_2; + + input func_scan_in; + output func_scan_out; + input [0:6] regfile_scan_in; // 0:2 -> CAM, 3:6 -> RAM + output [0:6] regfile_scan_out; + input time_scan_in; + output time_scan_out; + + // Read Port + input rd_val; + input rd_val_late; + input [0:NUM_ENTRY_LOG2-1] rw_entry; + + // Write Port + input [0:ARRAY_DATA_WIDTH-1] wr_array_data; + input [0:CAM_DATA_WIDTH-1] wr_cam_data; + input [0:1] wr_array_val; + input [0:1] wr_cam_val; + input wr_val_early; + + // CAM Port + input comp_request; + input [0:51] comp_addr; + input [0:1] addr_enable; + input [0:2] comp_pgsize; + input pgsize_enable; + input [0:1] comp_class; + input [0:2] class_enable; + input [0:1] comp_extclass; + input [0:1] extclass_enable; + input [0:1] comp_state; + input [0:1] state_enable; + input [0:3] comp_thdid; + input [0:1] thdid_enable; + input [0:7] comp_pid; + input pid_enable; + input comp_invalidate; + input flash_invalidate; + + // Outputs + // Data Out + output [0:ARRAY_DATA_WIDTH-1] array_cmp_data; + output [0:ARRAY_DATA_WIDTH-1] rd_array_data; + + // CAM Output + output [0:CAM_DATA_WIDTH-1] cam_cmp_data; + output cam_hit; + output [0:NUM_ENTRY_LOG2-1] cam_hit_entry; + output [0:NUM_ENTRY-1] entry_match; + output [0:NUM_ENTRY-1] entry_valid; + output [0:CAM_DATA_WIDTH-1] rd_cam_data; + + //--- new ports for IO plus ----------------------- + input bypass_mux_enab_np1; + input [0:20] bypass_attr_np1; + output [0:20] attr_np2; + + output [22:51] rpn_np2; + + // tri_cam_32x143_1r1w1c + + // Configuration Statement for NCsim + //for all:RAMB16_S9_S9 use entity unisim.RAMB16_S9_S9; + //for all:RAMB16_S18_S18 use entity unisim.RAMB16_S18_S18; + //for all:RAMB16_S36_S36 use entity unisim.RAMB16_S36_S36; + + wire clk; + wire clk2x; + wire [0:8] bram0_addra; + wire [0:8] bram0_addrb; + wire [0:10] bram1_addra; + wire [0:10] bram1_addrb; + wire [0:9] bram2_addra; + wire [0:9] bram2_addrb; + wire bram0_wea; + wire bram1_wea; + wire bram2_wea; + wire [0:55] array_cmp_data_bram; + wire [66:72] array_cmp_data_bramp; + + // Latches + reg sreset_q; + reg gate_fq; + wire gate_d; + wire [52-RPN_WIDTH:51] comp_addr_np1_d; + reg [52-RPN_WIDTH:51] comp_addr_np1_q; // the internal latched np1 phase epn(22:51) from com_addr input + wire [52-RPN_WIDTH:51] rpn_np2_d; + reg [52-RPN_WIDTH:51] rpn_np2_q; + wire [0:20] attr_np2_d; + reg [0:20] attr_np2_q; + + // CAM entry signals + wire [0:51] entry0_epn_d; + reg [0:51] entry0_epn_q; + wire entry0_xbit_d; + reg entry0_xbit_q; + wire [0:2] entry0_size_d; + reg [0:2] entry0_size_q; + wire entry0_v_d; + reg entry0_v_q; + wire [0:3] entry0_thdid_d; + reg [0:3] entry0_thdid_q; + wire [0:1] entry0_class_d; + reg [0:1] entry0_class_q; + wire [0:1] entry0_extclass_d; + reg [0:1] entry0_extclass_q; + wire entry0_hv_d; + reg entry0_hv_q; + wire entry0_ds_d; + reg entry0_ds_q; + wire [0:7] entry0_pid_d; + reg [0:7] entry0_pid_q; + wire [0:8] entry0_cmpmask_d; + reg [0:8] entry0_cmpmask_q; + wire [0:9] entry0_parity_d; + reg [0:9] entry0_parity_q; + wire [0:1] wr_entry0_sel; + wire entry0_inval; + wire [0:1] entry0_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry0_cam_vec; + wire [0:51] entry1_epn_d; + reg [0:51] entry1_epn_q; + wire entry1_xbit_d; + reg entry1_xbit_q; + wire [0:2] entry1_size_d; + reg [0:2] entry1_size_q; + wire entry1_v_d; + reg entry1_v_q; + wire [0:3] entry1_thdid_d; + reg [0:3] entry1_thdid_q; + wire [0:1] entry1_class_d; + reg [0:1] entry1_class_q; + wire [0:1] entry1_extclass_d; + reg [0:1] entry1_extclass_q; + wire entry1_hv_d; + reg entry1_hv_q; + wire entry1_ds_d; + reg entry1_ds_q; + wire [0:7] entry1_pid_d; + reg [0:7] entry1_pid_q; + wire [0:8] entry1_cmpmask_d; + reg [0:8] entry1_cmpmask_q; + wire [0:9] entry1_parity_d; + reg [0:9] entry1_parity_q; + wire [0:1] wr_entry1_sel; + wire entry1_inval; + wire [0:1] entry1_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry1_cam_vec; + wire [0:51] entry2_epn_d; + reg [0:51] entry2_epn_q; + wire entry2_xbit_d; + reg entry2_xbit_q; + wire [0:2] entry2_size_d; + reg [0:2] entry2_size_q; + wire entry2_v_d; + reg entry2_v_q; + wire [0:3] entry2_thdid_d; + reg [0:3] entry2_thdid_q; + wire [0:1] entry2_class_d; + reg [0:1] entry2_class_q; + wire [0:1] entry2_extclass_d; + reg [0:1] entry2_extclass_q; + wire entry2_hv_d; + reg entry2_hv_q; + wire entry2_ds_d; + reg entry2_ds_q; + wire [0:7] entry2_pid_d; + reg [0:7] entry2_pid_q; + wire [0:8] entry2_cmpmask_d; + reg [0:8] entry2_cmpmask_q; + wire [0:9] entry2_parity_d; + reg [0:9] entry2_parity_q; + wire [0:1] wr_entry2_sel; + wire entry2_inval; + wire [0:1] entry2_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry2_cam_vec; + wire [0:51] entry3_epn_d; + reg [0:51] entry3_epn_q; + wire entry3_xbit_d; + reg entry3_xbit_q; + wire [0:2] entry3_size_d; + reg [0:2] entry3_size_q; + wire entry3_v_d; + reg entry3_v_q; + wire [0:3] entry3_thdid_d; + reg [0:3] entry3_thdid_q; + wire [0:1] entry3_class_d; + reg [0:1] entry3_class_q; + wire [0:1] entry3_extclass_d; + reg [0:1] entry3_extclass_q; + wire entry3_hv_d; + reg entry3_hv_q; + wire entry3_ds_d; + reg entry3_ds_q; + wire [0:7] entry3_pid_d; + reg [0:7] entry3_pid_q; + wire [0:8] entry3_cmpmask_d; + reg [0:8] entry3_cmpmask_q; + wire [0:9] entry3_parity_d; + reg [0:9] entry3_parity_q; + wire [0:1] wr_entry3_sel; + wire entry3_inval; + wire [0:1] entry3_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry3_cam_vec; + wire [0:51] entry4_epn_d; + reg [0:51] entry4_epn_q; + wire entry4_xbit_d; + reg entry4_xbit_q; + wire [0:2] entry4_size_d; + reg [0:2] entry4_size_q; + wire entry4_v_d; + reg entry4_v_q; + wire [0:3] entry4_thdid_d; + reg [0:3] entry4_thdid_q; + wire [0:1] entry4_class_d; + reg [0:1] entry4_class_q; + wire [0:1] entry4_extclass_d; + reg [0:1] entry4_extclass_q; + wire entry4_hv_d; + reg entry4_hv_q; + wire entry4_ds_d; + reg entry4_ds_q; + wire [0:7] entry4_pid_d; + reg [0:7] entry4_pid_q; + wire [0:8] entry4_cmpmask_d; + reg [0:8] entry4_cmpmask_q; + wire [0:9] entry4_parity_d; + reg [0:9] entry4_parity_q; + wire [0:1] wr_entry4_sel; + wire entry4_inval; + wire [0:1] entry4_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry4_cam_vec; + wire [0:51] entry5_epn_d; + reg [0:51] entry5_epn_q; + wire entry5_xbit_d; + reg entry5_xbit_q; + wire [0:2] entry5_size_d; + reg [0:2] entry5_size_q; + wire entry5_v_d; + reg entry5_v_q; + wire [0:3] entry5_thdid_d; + reg [0:3] entry5_thdid_q; + wire [0:1] entry5_class_d; + reg [0:1] entry5_class_q; + wire [0:1] entry5_extclass_d; + reg [0:1] entry5_extclass_q; + wire entry5_hv_d; + reg entry5_hv_q; + wire entry5_ds_d; + reg entry5_ds_q; + wire [0:7] entry5_pid_d; + reg [0:7] entry5_pid_q; + wire [0:8] entry5_cmpmask_d; + reg [0:8] entry5_cmpmask_q; + wire [0:9] entry5_parity_d; + reg [0:9] entry5_parity_q; + wire [0:1] wr_entry5_sel; + wire entry5_inval; + wire [0:1] entry5_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry5_cam_vec; + wire [0:51] entry6_epn_d; + reg [0:51] entry6_epn_q; + wire entry6_xbit_d; + reg entry6_xbit_q; + wire [0:2] entry6_size_d; + reg [0:2] entry6_size_q; + wire entry6_v_d; + reg entry6_v_q; + wire [0:3] entry6_thdid_d; + reg [0:3] entry6_thdid_q; + wire [0:1] entry6_class_d; + reg [0:1] entry6_class_q; + wire [0:1] entry6_extclass_d; + reg [0:1] entry6_extclass_q; + wire entry6_hv_d; + reg entry6_hv_q; + wire entry6_ds_d; + reg entry6_ds_q; + wire [0:7] entry6_pid_d; + reg [0:7] entry6_pid_q; + wire [0:8] entry6_cmpmask_d; + reg [0:8] entry6_cmpmask_q; + wire [0:9] entry6_parity_d; + reg [0:9] entry6_parity_q; + wire [0:1] wr_entry6_sel; + wire entry6_inval; + wire [0:1] entry6_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry6_cam_vec; + wire [0:51] entry7_epn_d; + reg [0:51] entry7_epn_q; + wire entry7_xbit_d; + reg entry7_xbit_q; + wire [0:2] entry7_size_d; + reg [0:2] entry7_size_q; + wire entry7_v_d; + reg entry7_v_q; + wire [0:3] entry7_thdid_d; + reg [0:3] entry7_thdid_q; + wire [0:1] entry7_class_d; + reg [0:1] entry7_class_q; + wire [0:1] entry7_extclass_d; + reg [0:1] entry7_extclass_q; + wire entry7_hv_d; + reg entry7_hv_q; + wire entry7_ds_d; + reg entry7_ds_q; + wire [0:7] entry7_pid_d; + reg [0:7] entry7_pid_q; + wire [0:8] entry7_cmpmask_d; + reg [0:8] entry7_cmpmask_q; + wire [0:9] entry7_parity_d; + reg [0:9] entry7_parity_q; + wire [0:1] wr_entry7_sel; + wire entry7_inval; + wire [0:1] entry7_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry7_cam_vec; + wire [0:51] entry8_epn_d; + reg [0:51] entry8_epn_q; + wire entry8_xbit_d; + reg entry8_xbit_q; + wire [0:2] entry8_size_d; + reg [0:2] entry8_size_q; + wire entry8_v_d; + reg entry8_v_q; + wire [0:3] entry8_thdid_d; + reg [0:3] entry8_thdid_q; + wire [0:1] entry8_class_d; + reg [0:1] entry8_class_q; + wire [0:1] entry8_extclass_d; + reg [0:1] entry8_extclass_q; + wire entry8_hv_d; + reg entry8_hv_q; + wire entry8_ds_d; + reg entry8_ds_q; + wire [0:7] entry8_pid_d; + reg [0:7] entry8_pid_q; + wire [0:8] entry8_cmpmask_d; + reg [0:8] entry8_cmpmask_q; + wire [0:9] entry8_parity_d; + reg [0:9] entry8_parity_q; + wire [0:1] wr_entry8_sel; + wire entry8_inval; + wire [0:1] entry8_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry8_cam_vec; + wire [0:51] entry9_epn_d; + reg [0:51] entry9_epn_q; + wire entry9_xbit_d; + reg entry9_xbit_q; + wire [0:2] entry9_size_d; + reg [0:2] entry9_size_q; + wire entry9_v_d; + reg entry9_v_q; + wire [0:3] entry9_thdid_d; + reg [0:3] entry9_thdid_q; + wire [0:1] entry9_class_d; + reg [0:1] entry9_class_q; + wire [0:1] entry9_extclass_d; + reg [0:1] entry9_extclass_q; + wire entry9_hv_d; + reg entry9_hv_q; + wire entry9_ds_d; + reg entry9_ds_q; + wire [0:7] entry9_pid_d; + reg [0:7] entry9_pid_q; + wire [0:8] entry9_cmpmask_d; + reg [0:8] entry9_cmpmask_q; + wire [0:9] entry9_parity_d; + reg [0:9] entry9_parity_q; + wire [0:1] wr_entry9_sel; + wire entry9_inval; + wire [0:1] entry9_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry9_cam_vec; + wire [0:51] entry10_epn_d; + reg [0:51] entry10_epn_q; + wire entry10_xbit_d; + reg entry10_xbit_q; + wire [0:2] entry10_size_d; + reg [0:2] entry10_size_q; + wire entry10_v_d; + reg entry10_v_q; + wire [0:3] entry10_thdid_d; + reg [0:3] entry10_thdid_q; + wire [0:1] entry10_class_d; + reg [0:1] entry10_class_q; + wire [0:1] entry10_extclass_d; + reg [0:1] entry10_extclass_q; + wire entry10_hv_d; + reg entry10_hv_q; + wire entry10_ds_d; + reg entry10_ds_q; + wire [0:7] entry10_pid_d; + reg [0:7] entry10_pid_q; + wire [0:8] entry10_cmpmask_d; + reg [0:8] entry10_cmpmask_q; + wire [0:9] entry10_parity_d; + reg [0:9] entry10_parity_q; + wire [0:1] wr_entry10_sel; + wire entry10_inval; + wire [0:1] entry10_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry10_cam_vec; + wire [0:51] entry11_epn_d; + reg [0:51] entry11_epn_q; + wire entry11_xbit_d; + reg entry11_xbit_q; + wire [0:2] entry11_size_d; + reg [0:2] entry11_size_q; + wire entry11_v_d; + reg entry11_v_q; + wire [0:3] entry11_thdid_d; + reg [0:3] entry11_thdid_q; + wire [0:1] entry11_class_d; + reg [0:1] entry11_class_q; + wire [0:1] entry11_extclass_d; + reg [0:1] entry11_extclass_q; + wire entry11_hv_d; + reg entry11_hv_q; + wire entry11_ds_d; + reg entry11_ds_q; + wire [0:7] entry11_pid_d; + reg [0:7] entry11_pid_q; + wire [0:8] entry11_cmpmask_d; + reg [0:8] entry11_cmpmask_q; + wire [0:9] entry11_parity_d; + reg [0:9] entry11_parity_q; + wire [0:1] wr_entry11_sel; + wire entry11_inval; + wire [0:1] entry11_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry11_cam_vec; + wire [0:51] entry12_epn_d; + reg [0:51] entry12_epn_q; + wire entry12_xbit_d; + reg entry12_xbit_q; + wire [0:2] entry12_size_d; + reg [0:2] entry12_size_q; + wire entry12_v_d; + reg entry12_v_q; + wire [0:3] entry12_thdid_d; + reg [0:3] entry12_thdid_q; + wire [0:1] entry12_class_d; + reg [0:1] entry12_class_q; + wire [0:1] entry12_extclass_d; + reg [0:1] entry12_extclass_q; + wire entry12_hv_d; + reg entry12_hv_q; + wire entry12_ds_d; + reg entry12_ds_q; + wire [0:7] entry12_pid_d; + reg [0:7] entry12_pid_q; + wire [0:8] entry12_cmpmask_d; + reg [0:8] entry12_cmpmask_q; + wire [0:9] entry12_parity_d; + reg [0:9] entry12_parity_q; + wire [0:1] wr_entry12_sel; + wire entry12_inval; + wire [0:1] entry12_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry12_cam_vec; + wire [0:51] entry13_epn_d; + reg [0:51] entry13_epn_q; + wire entry13_xbit_d; + reg entry13_xbit_q; + wire [0:2] entry13_size_d; + reg [0:2] entry13_size_q; + wire entry13_v_d; + reg entry13_v_q; + wire [0:3] entry13_thdid_d; + reg [0:3] entry13_thdid_q; + wire [0:1] entry13_class_d; + reg [0:1] entry13_class_q; + wire [0:1] entry13_extclass_d; + reg [0:1] entry13_extclass_q; + wire entry13_hv_d; + reg entry13_hv_q; + wire entry13_ds_d; + reg entry13_ds_q; + wire [0:7] entry13_pid_d; + reg [0:7] entry13_pid_q; + wire [0:8] entry13_cmpmask_d; + reg [0:8] entry13_cmpmask_q; + wire [0:9] entry13_parity_d; + reg [0:9] entry13_parity_q; + wire [0:1] wr_entry13_sel; + wire entry13_inval; + wire [0:1] entry13_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry13_cam_vec; + wire [0:51] entry14_epn_d; + reg [0:51] entry14_epn_q; + wire entry14_xbit_d; + reg entry14_xbit_q; + wire [0:2] entry14_size_d; + reg [0:2] entry14_size_q; + wire entry14_v_d; + reg entry14_v_q; + wire [0:3] entry14_thdid_d; + reg [0:3] entry14_thdid_q; + wire [0:1] entry14_class_d; + reg [0:1] entry14_class_q; + wire [0:1] entry14_extclass_d; + reg [0:1] entry14_extclass_q; + wire entry14_hv_d; + reg entry14_hv_q; + wire entry14_ds_d; + reg entry14_ds_q; + wire [0:7] entry14_pid_d; + reg [0:7] entry14_pid_q; + wire [0:8] entry14_cmpmask_d; + reg [0:8] entry14_cmpmask_q; + wire [0:9] entry14_parity_d; + reg [0:9] entry14_parity_q; + wire [0:1] wr_entry14_sel; + wire entry14_inval; + wire [0:1] entry14_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry14_cam_vec; + wire [0:51] entry15_epn_d; + reg [0:51] entry15_epn_q; + wire entry15_xbit_d; + reg entry15_xbit_q; + wire [0:2] entry15_size_d; + reg [0:2] entry15_size_q; + wire entry15_v_d; + reg entry15_v_q; + wire [0:3] entry15_thdid_d; + reg [0:3] entry15_thdid_q; + wire [0:1] entry15_class_d; + reg [0:1] entry15_class_q; + wire [0:1] entry15_extclass_d; + reg [0:1] entry15_extclass_q; + wire entry15_hv_d; + reg entry15_hv_q; + wire entry15_ds_d; + reg entry15_ds_q; + wire [0:7] entry15_pid_d; + reg [0:7] entry15_pid_q; + wire [0:8] entry15_cmpmask_d; + reg [0:8] entry15_cmpmask_q; + wire [0:9] entry15_parity_d; + reg [0:9] entry15_parity_q; + wire [0:1] wr_entry15_sel; + wire entry15_inval; + wire [0:1] entry15_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry15_cam_vec; + wire [0:51] entry16_epn_d; + reg [0:51] entry16_epn_q; + wire entry16_xbit_d; + reg entry16_xbit_q; + wire [0:2] entry16_size_d; + reg [0:2] entry16_size_q; + wire entry16_v_d; + reg entry16_v_q; + wire [0:3] entry16_thdid_d; + reg [0:3] entry16_thdid_q; + wire [0:1] entry16_class_d; + reg [0:1] entry16_class_q; + wire [0:1] entry16_extclass_d; + reg [0:1] entry16_extclass_q; + wire entry16_hv_d; + reg entry16_hv_q; + wire entry16_ds_d; + reg entry16_ds_q; + wire [0:7] entry16_pid_d; + reg [0:7] entry16_pid_q; + wire [0:8] entry16_cmpmask_d; + reg [0:8] entry16_cmpmask_q; + wire [0:9] entry16_parity_d; + reg [0:9] entry16_parity_q; + wire [0:1] wr_entry16_sel; + wire entry16_inval; + wire [0:1] entry16_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry16_cam_vec; + wire [0:51] entry17_epn_d; + reg [0:51] entry17_epn_q; + wire entry17_xbit_d; + reg entry17_xbit_q; + wire [0:2] entry17_size_d; + reg [0:2] entry17_size_q; + wire entry17_v_d; + reg entry17_v_q; + wire [0:3] entry17_thdid_d; + reg [0:3] entry17_thdid_q; + wire [0:1] entry17_class_d; + reg [0:1] entry17_class_q; + wire [0:1] entry17_extclass_d; + reg [0:1] entry17_extclass_q; + wire entry17_hv_d; + reg entry17_hv_q; + wire entry17_ds_d; + reg entry17_ds_q; + wire [0:7] entry17_pid_d; + reg [0:7] entry17_pid_q; + wire [0:8] entry17_cmpmask_d; + reg [0:8] entry17_cmpmask_q; + wire [0:9] entry17_parity_d; + reg [0:9] entry17_parity_q; + wire [0:1] wr_entry17_sel; + wire entry17_inval; + wire [0:1] entry17_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry17_cam_vec; + wire [0:51] entry18_epn_d; + reg [0:51] entry18_epn_q; + wire entry18_xbit_d; + reg entry18_xbit_q; + wire [0:2] entry18_size_d; + reg [0:2] entry18_size_q; + wire entry18_v_d; + reg entry18_v_q; + wire [0:3] entry18_thdid_d; + reg [0:3] entry18_thdid_q; + wire [0:1] entry18_class_d; + reg [0:1] entry18_class_q; + wire [0:1] entry18_extclass_d; + reg [0:1] entry18_extclass_q; + wire entry18_hv_d; + reg entry18_hv_q; + wire entry18_ds_d; + reg entry18_ds_q; + wire [0:7] entry18_pid_d; + reg [0:7] entry18_pid_q; + wire [0:8] entry18_cmpmask_d; + reg [0:8] entry18_cmpmask_q; + wire [0:9] entry18_parity_d; + reg [0:9] entry18_parity_q; + wire [0:1] wr_entry18_sel; + wire entry18_inval; + wire [0:1] entry18_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry18_cam_vec; + wire [0:51] entry19_epn_d; + reg [0:51] entry19_epn_q; + wire entry19_xbit_d; + reg entry19_xbit_q; + wire [0:2] entry19_size_d; + reg [0:2] entry19_size_q; + wire entry19_v_d; + reg entry19_v_q; + wire [0:3] entry19_thdid_d; + reg [0:3] entry19_thdid_q; + wire [0:1] entry19_class_d; + reg [0:1] entry19_class_q; + wire [0:1] entry19_extclass_d; + reg [0:1] entry19_extclass_q; + wire entry19_hv_d; + reg entry19_hv_q; + wire entry19_ds_d; + reg entry19_ds_q; + wire [0:7] entry19_pid_d; + reg [0:7] entry19_pid_q; + wire [0:8] entry19_cmpmask_d; + reg [0:8] entry19_cmpmask_q; + wire [0:9] entry19_parity_d; + reg [0:9] entry19_parity_q; + wire [0:1] wr_entry19_sel; + wire entry19_inval; + wire [0:1] entry19_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry19_cam_vec; + wire [0:51] entry20_epn_d; + reg [0:51] entry20_epn_q; + wire entry20_xbit_d; + reg entry20_xbit_q; + wire [0:2] entry20_size_d; + reg [0:2] entry20_size_q; + wire entry20_v_d; + reg entry20_v_q; + wire [0:3] entry20_thdid_d; + reg [0:3] entry20_thdid_q; + wire [0:1] entry20_class_d; + reg [0:1] entry20_class_q; + wire [0:1] entry20_extclass_d; + reg [0:1] entry20_extclass_q; + wire entry20_hv_d; + reg entry20_hv_q; + wire entry20_ds_d; + reg entry20_ds_q; + wire [0:7] entry20_pid_d; + reg [0:7] entry20_pid_q; + wire [0:8] entry20_cmpmask_d; + reg [0:8] entry20_cmpmask_q; + wire [0:9] entry20_parity_d; + reg [0:9] entry20_parity_q; + wire [0:1] wr_entry20_sel; + wire entry20_inval; + wire [0:1] entry20_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry20_cam_vec; + wire [0:51] entry21_epn_d; + reg [0:51] entry21_epn_q; + wire entry21_xbit_d; + reg entry21_xbit_q; + wire [0:2] entry21_size_d; + reg [0:2] entry21_size_q; + wire entry21_v_d; + reg entry21_v_q; + wire [0:3] entry21_thdid_d; + reg [0:3] entry21_thdid_q; + wire [0:1] entry21_class_d; + reg [0:1] entry21_class_q; + wire [0:1] entry21_extclass_d; + reg [0:1] entry21_extclass_q; + wire entry21_hv_d; + reg entry21_hv_q; + wire entry21_ds_d; + reg entry21_ds_q; + wire [0:7] entry21_pid_d; + reg [0:7] entry21_pid_q; + wire [0:8] entry21_cmpmask_d; + reg [0:8] entry21_cmpmask_q; + wire [0:9] entry21_parity_d; + reg [0:9] entry21_parity_q; + wire [0:1] wr_entry21_sel; + wire entry21_inval; + wire [0:1] entry21_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry21_cam_vec; + wire [0:51] entry22_epn_d; + reg [0:51] entry22_epn_q; + wire entry22_xbit_d; + reg entry22_xbit_q; + wire [0:2] entry22_size_d; + reg [0:2] entry22_size_q; + wire entry22_v_d; + reg entry22_v_q; + wire [0:3] entry22_thdid_d; + reg [0:3] entry22_thdid_q; + wire [0:1] entry22_class_d; + reg [0:1] entry22_class_q; + wire [0:1] entry22_extclass_d; + reg [0:1] entry22_extclass_q; + wire entry22_hv_d; + reg entry22_hv_q; + wire entry22_ds_d; + reg entry22_ds_q; + wire [0:7] entry22_pid_d; + reg [0:7] entry22_pid_q; + wire [0:8] entry22_cmpmask_d; + reg [0:8] entry22_cmpmask_q; + wire [0:9] entry22_parity_d; + reg [0:9] entry22_parity_q; + wire [0:1] wr_entry22_sel; + wire entry22_inval; + wire [0:1] entry22_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry22_cam_vec; + wire [0:51] entry23_epn_d; + reg [0:51] entry23_epn_q; + wire entry23_xbit_d; + reg entry23_xbit_q; + wire [0:2] entry23_size_d; + reg [0:2] entry23_size_q; + wire entry23_v_d; + reg entry23_v_q; + wire [0:3] entry23_thdid_d; + reg [0:3] entry23_thdid_q; + wire [0:1] entry23_class_d; + reg [0:1] entry23_class_q; + wire [0:1] entry23_extclass_d; + reg [0:1] entry23_extclass_q; + wire entry23_hv_d; + reg entry23_hv_q; + wire entry23_ds_d; + reg entry23_ds_q; + wire [0:7] entry23_pid_d; + reg [0:7] entry23_pid_q; + wire [0:8] entry23_cmpmask_d; + reg [0:8] entry23_cmpmask_q; + wire [0:9] entry23_parity_d; + reg [0:9] entry23_parity_q; + wire [0:1] wr_entry23_sel; + wire entry23_inval; + wire [0:1] entry23_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry23_cam_vec; + wire [0:51] entry24_epn_d; + reg [0:51] entry24_epn_q; + wire entry24_xbit_d; + reg entry24_xbit_q; + wire [0:2] entry24_size_d; + reg [0:2] entry24_size_q; + wire entry24_v_d; + reg entry24_v_q; + wire [0:3] entry24_thdid_d; + reg [0:3] entry24_thdid_q; + wire [0:1] entry24_class_d; + reg [0:1] entry24_class_q; + wire [0:1] entry24_extclass_d; + reg [0:1] entry24_extclass_q; + wire entry24_hv_d; + reg entry24_hv_q; + wire entry24_ds_d; + reg entry24_ds_q; + wire [0:7] entry24_pid_d; + reg [0:7] entry24_pid_q; + wire [0:8] entry24_cmpmask_d; + reg [0:8] entry24_cmpmask_q; + wire [0:9] entry24_parity_d; + reg [0:9] entry24_parity_q; + wire [0:1] wr_entry24_sel; + wire entry24_inval; + wire [0:1] entry24_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry24_cam_vec; + wire [0:51] entry25_epn_d; + reg [0:51] entry25_epn_q; + wire entry25_xbit_d; + reg entry25_xbit_q; + wire [0:2] entry25_size_d; + reg [0:2] entry25_size_q; + wire entry25_v_d; + reg entry25_v_q; + wire [0:3] entry25_thdid_d; + reg [0:3] entry25_thdid_q; + wire [0:1] entry25_class_d; + reg [0:1] entry25_class_q; + wire [0:1] entry25_extclass_d; + reg [0:1] entry25_extclass_q; + wire entry25_hv_d; + reg entry25_hv_q; + wire entry25_ds_d; + reg entry25_ds_q; + wire [0:7] entry25_pid_d; + reg [0:7] entry25_pid_q; + wire [0:8] entry25_cmpmask_d; + reg [0:8] entry25_cmpmask_q; + wire [0:9] entry25_parity_d; + reg [0:9] entry25_parity_q; + wire [0:1] wr_entry25_sel; + wire entry25_inval; + wire [0:1] entry25_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry25_cam_vec; + wire [0:51] entry26_epn_d; + reg [0:51] entry26_epn_q; + wire entry26_xbit_d; + reg entry26_xbit_q; + wire [0:2] entry26_size_d; + reg [0:2] entry26_size_q; + wire entry26_v_d; + reg entry26_v_q; + wire [0:3] entry26_thdid_d; + reg [0:3] entry26_thdid_q; + wire [0:1] entry26_class_d; + reg [0:1] entry26_class_q; + wire [0:1] entry26_extclass_d; + reg [0:1] entry26_extclass_q; + wire entry26_hv_d; + reg entry26_hv_q; + wire entry26_ds_d; + reg entry26_ds_q; + wire [0:7] entry26_pid_d; + reg [0:7] entry26_pid_q; + wire [0:8] entry26_cmpmask_d; + reg [0:8] entry26_cmpmask_q; + wire [0:9] entry26_parity_d; + reg [0:9] entry26_parity_q; + wire [0:1] wr_entry26_sel; + wire entry26_inval; + wire [0:1] entry26_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry26_cam_vec; + wire [0:51] entry27_epn_d; + reg [0:51] entry27_epn_q; + wire entry27_xbit_d; + reg entry27_xbit_q; + wire [0:2] entry27_size_d; + reg [0:2] entry27_size_q; + wire entry27_v_d; + reg entry27_v_q; + wire [0:3] entry27_thdid_d; + reg [0:3] entry27_thdid_q; + wire [0:1] entry27_class_d; + reg [0:1] entry27_class_q; + wire [0:1] entry27_extclass_d; + reg [0:1] entry27_extclass_q; + wire entry27_hv_d; + reg entry27_hv_q; + wire entry27_ds_d; + reg entry27_ds_q; + wire [0:7] entry27_pid_d; + reg [0:7] entry27_pid_q; + wire [0:8] entry27_cmpmask_d; + reg [0:8] entry27_cmpmask_q; + wire [0:9] entry27_parity_d; + reg [0:9] entry27_parity_q; + wire [0:1] wr_entry27_sel; + wire entry27_inval; + wire [0:1] entry27_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry27_cam_vec; + wire [0:51] entry28_epn_d; + reg [0:51] entry28_epn_q; + wire entry28_xbit_d; + reg entry28_xbit_q; + wire [0:2] entry28_size_d; + reg [0:2] entry28_size_q; + wire entry28_v_d; + reg entry28_v_q; + wire [0:3] entry28_thdid_d; + reg [0:3] entry28_thdid_q; + wire [0:1] entry28_class_d; + reg [0:1] entry28_class_q; + wire [0:1] entry28_extclass_d; + reg [0:1] entry28_extclass_q; + wire entry28_hv_d; + reg entry28_hv_q; + wire entry28_ds_d; + reg entry28_ds_q; + wire [0:7] entry28_pid_d; + reg [0:7] entry28_pid_q; + wire [0:8] entry28_cmpmask_d; + reg [0:8] entry28_cmpmask_q; + wire [0:9] entry28_parity_d; + reg [0:9] entry28_parity_q; + wire [0:1] wr_entry28_sel; + wire entry28_inval; + wire [0:1] entry28_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry28_cam_vec; + wire [0:51] entry29_epn_d; + reg [0:51] entry29_epn_q; + wire entry29_xbit_d; + reg entry29_xbit_q; + wire [0:2] entry29_size_d; + reg [0:2] entry29_size_q; + wire entry29_v_d; + reg entry29_v_q; + wire [0:3] entry29_thdid_d; + reg [0:3] entry29_thdid_q; + wire [0:1] entry29_class_d; + reg [0:1] entry29_class_q; + wire [0:1] entry29_extclass_d; + reg [0:1] entry29_extclass_q; + wire entry29_hv_d; + reg entry29_hv_q; + wire entry29_ds_d; + reg entry29_ds_q; + wire [0:7] entry29_pid_d; + reg [0:7] entry29_pid_q; + wire [0:8] entry29_cmpmask_d; + reg [0:8] entry29_cmpmask_q; + wire [0:9] entry29_parity_d; + reg [0:9] entry29_parity_q; + wire [0:1] wr_entry29_sel; + wire entry29_inval; + wire [0:1] entry29_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry29_cam_vec; + wire [0:51] entry30_epn_d; + reg [0:51] entry30_epn_q; + wire entry30_xbit_d; + reg entry30_xbit_q; + wire [0:2] entry30_size_d; + reg [0:2] entry30_size_q; + wire entry30_v_d; + reg entry30_v_q; + wire [0:3] entry30_thdid_d; + reg [0:3] entry30_thdid_q; + wire [0:1] entry30_class_d; + reg [0:1] entry30_class_q; + wire [0:1] entry30_extclass_d; + reg [0:1] entry30_extclass_q; + wire entry30_hv_d; + reg entry30_hv_q; + wire entry30_ds_d; + reg entry30_ds_q; + wire [0:7] entry30_pid_d; + reg [0:7] entry30_pid_q; + wire [0:8] entry30_cmpmask_d; + reg [0:8] entry30_cmpmask_q; + wire [0:9] entry30_parity_d; + reg [0:9] entry30_parity_q; + wire [0:1] wr_entry30_sel; + wire entry30_inval; + wire [0:1] entry30_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry30_cam_vec; + wire [0:51] entry31_epn_d; + reg [0:51] entry31_epn_q; + wire entry31_xbit_d; + reg entry31_xbit_q; + wire [0:2] entry31_size_d; + reg [0:2] entry31_size_q; + wire entry31_v_d; + reg entry31_v_q; + wire [0:3] entry31_thdid_d; + reg [0:3] entry31_thdid_q; + wire [0:1] entry31_class_d; + reg [0:1] entry31_class_q; + wire [0:1] entry31_extclass_d; + reg [0:1] entry31_extclass_q; + wire entry31_hv_d; + reg entry31_hv_q; + wire entry31_ds_d; + reg entry31_ds_q; + wire [0:7] entry31_pid_d; + reg [0:7] entry31_pid_q; + wire [0:8] entry31_cmpmask_d; + reg [0:8] entry31_cmpmask_q; + wire [0:9] entry31_parity_d; + reg [0:9] entry31_parity_q; + wire [0:1] wr_entry31_sel; + wire entry31_inval; + wire [0:1] entry31_v_muxsel; + wire [0:CAM_DATA_WIDTH-1] entry31_cam_vec; + wire [0:5] cam_cmp_data_muxsel; + wire [0:5] rd_cam_data_muxsel; + wire [0:CAM_DATA_WIDTH-1] cam_cmp_data_np1; + wire [0:ARRAY_DATA_WIDTH-1] array_cmp_data_np1; + wire [0:72] wr_array_data_bram; + wire [0:72] rd_array_data_d_std; + wire [0:55] array_cmp_data_bram_std; + wire [66:72] array_cmp_data_bramp_std; + + // latch signals + wire [0:ARRAY_DATA_WIDTH-1] rd_array_data_d; + reg [0:ARRAY_DATA_WIDTH-1] rd_array_data_q; + wire [0:CAM_DATA_WIDTH-1] cam_cmp_data_d; + reg [0:CAM_DATA_WIDTH-1] cam_cmp_data_q; + wire [0:9] cam_cmp_parity_d; + reg [0:9] cam_cmp_parity_q; + wire [0:CAM_DATA_WIDTH-1] rd_cam_data_d; + reg [0:CAM_DATA_WIDTH-1] rd_cam_data_q; + wire [0:NUM_ENTRY-1] entry_match_d; + reg [0:NUM_ENTRY-1] entry_match_q; + wire [0:NUM_ENTRY-1] match_vec; + wire [0:NUM_ENTRY_LOG2-1] cam_hit_entry_d; + reg [0:NUM_ENTRY_LOG2-1] cam_hit_entry_q; + wire cam_hit_d; + reg cam_hit_q; + wire toggle_d; + reg toggle_q; + wire toggle2x_d; + reg toggle2x_q; + (* analysis_not_referenced="true" *) + wire unused; + + + + assign clk = (~nclk[0]); + assign clk2x = nclk[2]; + + always @(posedge clk) + begin: rlatch + sreset_q <= nclk[1]; + end + + // + // NEW clk2x gate logic start + // + + always @(posedge nclk[0]) + begin: tlatch + if (sreset_q == 1'b1) + toggle_q <= 1'b1; + else + toggle_q <= toggle_d; + end + + always @(posedge nclk[2]) + begin: flatch + toggle2x_q <= toggle2x_d; + gate_fq <= gate_d; + end + + assign toggle_d = (~toggle_q); + assign toggle2x_d = toggle_q; + + // should force gate_fq to be on during odd 2x clock (second half of 1x clock). + assign gate_d = toggle_q ^ toggle2x_q; + // if you want the first half do the following + //assign gate_d <= ~(toggle_q ^ toggle2x_q); + + // + // NEW clk2x gate logic end + // + + // Slow Latches (nclk) + always @(posedge nclk[0]) + begin: slatch + if (sreset_q == 1'b1) + begin + cam_cmp_data_q <= {CAM_DATA_WIDTH{1'b0}}; + cam_cmp_parity_q <= 10'b0; + rd_cam_data_q <= {CAM_DATA_WIDTH{1'b0}}; + rd_array_data_q <= {ARRAY_DATA_WIDTH{1'b0}}; + entry_match_q <= {NUM_ENTRY{1'b0}}; + cam_hit_entry_q <= {NUM_ENTRY_LOG2{1'b0}}; + cam_hit_q <= 1'b0; + comp_addr_np1_q <= {RPN_WIDTH{1'b0}}; + rpn_np2_q <= {RPN_WIDTH{1'b0}}; + attr_np2_q <= 21'b0; + entry0_size_q <= 3'b0; + entry0_xbit_q <= 1'b0; + entry0_epn_q <= 52'b0; + entry0_class_q <= 2'b0; + entry0_extclass_q <= 2'b0; + entry0_hv_q <= 1'b0; + entry0_ds_q <= 1'b0; + entry0_thdid_q <= 4'b0; + entry0_pid_q <= 8'b0; + entry0_v_q <= 1'b0; + entry0_parity_q <= 10'b0; + entry0_cmpmask_q <= 9'b0; + entry1_size_q <= 3'b0; + entry1_xbit_q <= 1'b0; + entry1_epn_q <= 52'b0; + entry1_class_q <= 2'b0; + entry1_extclass_q <= 2'b0; + entry1_hv_q <= 1'b0; + entry1_ds_q <= 1'b0; + entry1_thdid_q <= 4'b0; + entry1_pid_q <= 8'b0; + entry1_v_q <= 1'b0; + entry1_parity_q <= 10'b0; + entry1_cmpmask_q <= 9'b0; + entry2_size_q <= 3'b0; + entry2_xbit_q <= 1'b0; + entry2_epn_q <= 52'b0; + entry2_class_q <= 2'b0; + entry2_extclass_q <= 2'b0; + entry2_hv_q <= 1'b0; + entry2_ds_q <= 1'b0; + entry2_thdid_q <= 4'b0; + entry2_pid_q <= 8'b0; + entry2_v_q <= 1'b0; + entry2_parity_q <= 10'b0; + entry2_cmpmask_q <= 9'b0; + entry3_size_q <= 3'b0; + entry3_xbit_q <= 1'b0; + entry3_epn_q <= 52'b0; + entry3_class_q <= 2'b0; + entry3_extclass_q <= 2'b0; + entry3_hv_q <= 1'b0; + entry3_ds_q <= 1'b0; + entry3_thdid_q <= 4'b0; + entry3_pid_q <= 8'b0; + entry3_v_q <= 1'b0; + entry3_parity_q <= 10'b0; + entry3_cmpmask_q <= 9'b0; + entry4_size_q <= 3'b0; + entry4_xbit_q <= 1'b0; + entry4_epn_q <= 52'b0; + entry4_class_q <= 2'b0; + entry4_extclass_q <= 2'b0; + entry4_hv_q <= 1'b0; + entry4_ds_q <= 1'b0; + entry4_thdid_q <= 4'b0; + entry4_pid_q <= 8'b0; + entry4_v_q <= 1'b0; + entry4_parity_q <= 10'b0; + entry4_cmpmask_q <= 9'b0; + entry5_size_q <= 3'b0; + entry5_xbit_q <= 1'b0; + entry5_epn_q <= 52'b0; + entry5_class_q <= 2'b0; + entry5_extclass_q <= 2'b0; + entry5_hv_q <= 1'b0; + entry5_ds_q <= 1'b0; + entry5_thdid_q <= 4'b0; + entry5_pid_q <= 8'b0; + entry5_v_q <= 1'b0; + entry5_parity_q <= 10'b0; + entry5_cmpmask_q <= 9'b0; + entry6_size_q <= 3'b0; + entry6_xbit_q <= 1'b0; + entry6_epn_q <= 52'b0; + entry6_class_q <= 2'b0; + entry6_extclass_q <= 2'b0; + entry6_hv_q <= 1'b0; + entry6_ds_q <= 1'b0; + entry6_thdid_q <= 4'b0; + entry6_pid_q <= 8'b0; + entry6_v_q <= 1'b0; + entry6_parity_q <= 10'b0; + entry6_cmpmask_q <= 9'b0; + entry7_size_q <= 3'b0; + entry7_xbit_q <= 1'b0; + entry7_epn_q <= 52'b0; + entry7_class_q <= 2'b0; + entry7_extclass_q <= 2'b0; + entry7_hv_q <= 1'b0; + entry7_ds_q <= 1'b0; + entry7_thdid_q <= 4'b0; + entry7_pid_q <= 8'b0; + entry7_v_q <= 1'b0; + entry7_parity_q <= 10'b0; + entry7_cmpmask_q <= 9'b0; + entry8_size_q <= 3'b0; + entry8_xbit_q <= 1'b0; + entry8_epn_q <= 52'b0; + entry8_class_q <= 2'b0; + entry8_extclass_q <= 2'b0; + entry8_hv_q <= 1'b0; + entry8_ds_q <= 1'b0; + entry8_thdid_q <= 4'b0; + entry8_pid_q <= 8'b0; + entry8_v_q <= 1'b0; + entry8_parity_q <= 10'b0; + entry8_cmpmask_q <= 9'b0; + entry9_size_q <= 3'b0; + entry9_xbit_q <= 1'b0; + entry9_epn_q <= 52'b0; + entry9_class_q <= 2'b0; + entry9_extclass_q <= 2'b0; + entry9_hv_q <= 1'b0; + entry9_ds_q <= 1'b0; + entry9_thdid_q <= 4'b0; + entry9_pid_q <= 8'b0; + entry9_v_q <= 1'b0; + entry9_parity_q <= 10'b0; + entry9_cmpmask_q <= 9'b0; + entry10_size_q <= 3'b0; + entry10_xbit_q <= 1'b0; + entry10_epn_q <= 52'b0; + entry10_class_q <= 2'b0; + entry10_extclass_q <= 2'b0; + entry10_hv_q <= 1'b0; + entry10_ds_q <= 1'b0; + entry10_thdid_q <= 4'b0; + entry10_pid_q <= 8'b0; + entry10_v_q <= 1'b0; + entry10_parity_q <= 10'b0; + entry10_cmpmask_q <= 9'b0; + entry11_size_q <= 3'b0; + entry11_xbit_q <= 1'b0; + entry11_epn_q <= 52'b0; + entry11_class_q <= 2'b0; + entry11_extclass_q <= 2'b0; + entry11_hv_q <= 1'b0; + entry11_ds_q <= 1'b0; + entry11_thdid_q <= 4'b0; + entry11_pid_q <= 8'b0; + entry11_v_q <= 1'b0; + entry11_parity_q <= 10'b0; + entry11_cmpmask_q <= 9'b0; + entry12_size_q <= 3'b0; + entry12_xbit_q <= 1'b0; + entry12_epn_q <= 52'b0; + entry12_class_q <= 2'b0; + entry12_extclass_q <= 2'b0; + entry12_hv_q <= 1'b0; + entry12_ds_q <= 1'b0; + entry12_thdid_q <= 4'b0; + entry12_pid_q <= 8'b0; + entry12_v_q <= 1'b0; + entry12_parity_q <= 10'b0; + entry12_cmpmask_q <= 9'b0; + entry13_size_q <= 3'b0; + entry13_xbit_q <= 1'b0; + entry13_epn_q <= 52'b0; + entry13_class_q <= 2'b0; + entry13_extclass_q <= 2'b0; + entry13_hv_q <= 1'b0; + entry13_ds_q <= 1'b0; + entry13_thdid_q <= 4'b0; + entry13_pid_q <= 8'b0; + entry13_v_q <= 1'b0; + entry13_parity_q <= 10'b0; + entry13_cmpmask_q <= 9'b0; + entry14_size_q <= 3'b0; + entry14_xbit_q <= 1'b0; + entry14_epn_q <= 52'b0; + entry14_class_q <= 2'b0; + entry14_extclass_q <= 2'b0; + entry14_hv_q <= 1'b0; + entry14_ds_q <= 1'b0; + entry14_thdid_q <= 4'b0; + entry14_pid_q <= 8'b0; + entry14_v_q <= 1'b0; + entry14_parity_q <= 10'b0; + entry14_cmpmask_q <= 9'b0; + entry15_size_q <= 3'b0; + entry15_xbit_q <= 1'b0; + entry15_epn_q <= 52'b0; + entry15_class_q <= 2'b0; + entry15_extclass_q <= 2'b0; + entry15_hv_q <= 1'b0; + entry15_ds_q <= 1'b0; + entry15_thdid_q <= 4'b0; + entry15_pid_q <= 8'b0; + entry15_v_q <= 1'b0; + entry15_parity_q <= 10'b0; + entry15_cmpmask_q <= 9'b0; + entry16_size_q <= 3'b0; + entry16_xbit_q <= 1'b0; + entry16_epn_q <= 52'b0; + entry16_class_q <= 2'b0; + entry16_extclass_q <= 2'b0; + entry16_hv_q <= 1'b0; + entry16_ds_q <= 1'b0; + entry16_thdid_q <= 4'b0; + entry16_pid_q <= 8'b0; + entry16_v_q <= 1'b0; + entry16_parity_q <= 10'b0; + entry16_cmpmask_q <= 9'b0; + entry17_size_q <= 3'b0; + entry17_xbit_q <= 1'b0; + entry17_epn_q <= 52'b0; + entry17_class_q <= 2'b0; + entry17_extclass_q <= 2'b0; + entry17_hv_q <= 1'b0; + entry17_ds_q <= 1'b0; + entry17_thdid_q <= 4'b0; + entry17_pid_q <= 8'b0; + entry17_v_q <= 1'b0; + entry17_parity_q <= 10'b0; + entry17_cmpmask_q <= 9'b0; + entry18_size_q <= 3'b0; + entry18_xbit_q <= 1'b0; + entry18_epn_q <= 52'b0; + entry18_class_q <= 2'b0; + entry18_extclass_q <= 2'b0; + entry18_hv_q <= 1'b0; + entry18_ds_q <= 1'b0; + entry18_thdid_q <= 4'b0; + entry18_pid_q <= 8'b0; + entry18_v_q <= 1'b0; + entry18_parity_q <= 10'b0; + entry18_cmpmask_q <= 9'b0; + entry19_size_q <= 3'b0; + entry19_xbit_q <= 1'b0; + entry19_epn_q <= 52'b0; + entry19_class_q <= 2'b0; + entry19_extclass_q <= 2'b0; + entry19_hv_q <= 1'b0; + entry19_ds_q <= 1'b0; + entry19_thdid_q <= 4'b0; + entry19_pid_q <= 8'b0; + entry19_v_q <= 1'b0; + entry19_parity_q <= 10'b0; + entry19_cmpmask_q <= 9'b0; + entry20_size_q <= 3'b0; + entry20_xbit_q <= 1'b0; + entry20_epn_q <= 52'b0; + entry20_class_q <= 2'b0; + entry20_extclass_q <= 2'b0; + entry20_hv_q <= 1'b0; + entry20_ds_q <= 1'b0; + entry20_thdid_q <= 4'b0; + entry20_pid_q <= 8'b0; + entry20_v_q <= 1'b0; + entry20_parity_q <= 10'b0; + entry20_cmpmask_q <= 9'b0; + entry21_size_q <= 3'b0; + entry21_xbit_q <= 1'b0; + entry21_epn_q <= 52'b0; + entry21_class_q <= 2'b0; + entry21_extclass_q <= 2'b0; + entry21_hv_q <= 1'b0; + entry21_ds_q <= 1'b0; + entry21_thdid_q <= 4'b0; + entry21_pid_q <= 8'b0; + entry21_v_q <= 1'b0; + entry21_parity_q <= 10'b0; + entry21_cmpmask_q <= 9'b0; + entry22_size_q <= 3'b0; + entry22_xbit_q <= 1'b0; + entry22_epn_q <= 52'b0; + entry22_class_q <= 2'b0; + entry22_extclass_q <= 2'b0; + entry22_hv_q <= 1'b0; + entry22_ds_q <= 1'b0; + entry22_thdid_q <= 4'b0; + entry22_pid_q <= 8'b0; + entry22_v_q <= 1'b0; + entry22_parity_q <= 10'b0; + entry22_cmpmask_q <= 9'b0; + entry23_size_q <= 3'b0; + entry23_xbit_q <= 1'b0; + entry23_epn_q <= 52'b0; + entry23_class_q <= 2'b0; + entry23_extclass_q <= 2'b0; + entry23_hv_q <= 1'b0; + entry23_ds_q <= 1'b0; + entry23_thdid_q <= 4'b0; + entry23_pid_q <= 8'b0; + entry23_v_q <= 1'b0; + entry23_parity_q <= 10'b0; + entry23_cmpmask_q <= 9'b0; + entry24_size_q <= 3'b0; + entry24_xbit_q <= 1'b0; + entry24_epn_q <= 52'b0; + entry24_class_q <= 2'b0; + entry24_extclass_q <= 2'b0; + entry24_hv_q <= 1'b0; + entry24_ds_q <= 1'b0; + entry24_thdid_q <= 4'b0; + entry24_pid_q <= 8'b0; + entry24_v_q <= 1'b0; + entry24_parity_q <= 10'b0; + entry24_cmpmask_q <= 9'b0; + entry25_size_q <= 3'b0; + entry25_xbit_q <= 1'b0; + entry25_epn_q <= 52'b0; + entry25_class_q <= 2'b0; + entry25_extclass_q <= 2'b0; + entry25_hv_q <= 1'b0; + entry25_ds_q <= 1'b0; + entry25_thdid_q <= 4'b0; + entry25_pid_q <= 8'b0; + entry25_v_q <= 1'b0; + entry25_parity_q <= 10'b0; + entry25_cmpmask_q <= 9'b0; + entry26_size_q <= 3'b0; + entry26_xbit_q <= 1'b0; + entry26_epn_q <= 52'b0; + entry26_class_q <= 2'b0; + entry26_extclass_q <= 2'b0; + entry26_hv_q <= 1'b0; + entry26_ds_q <= 1'b0; + entry26_thdid_q <= 4'b0; + entry26_pid_q <= 8'b0; + entry26_v_q <= 1'b0; + entry26_parity_q <= 10'b0; + entry26_cmpmask_q <= 9'b0; + entry27_size_q <= 3'b0; + entry27_xbit_q <= 1'b0; + entry27_epn_q <= 52'b0; + entry27_class_q <= 2'b0; + entry27_extclass_q <= 2'b0; + entry27_hv_q <= 1'b0; + entry27_ds_q <= 1'b0; + entry27_thdid_q <= 4'b0; + entry27_pid_q <= 8'b0; + entry27_v_q <= 1'b0; + entry27_parity_q <= 10'b0; + entry27_cmpmask_q <= 9'b0; + entry28_size_q <= 3'b0; + entry28_xbit_q <= 1'b0; + entry28_epn_q <= 52'b0; + entry28_class_q <= 2'b0; + entry28_extclass_q <= 2'b0; + entry28_hv_q <= 1'b0; + entry28_ds_q <= 1'b0; + entry28_thdid_q <= 4'b0; + entry28_pid_q <= 8'b0; + entry28_v_q <= 1'b0; + entry28_parity_q <= 10'b0; + entry28_cmpmask_q <= 9'b0; + entry29_size_q <= 3'b0; + entry29_xbit_q <= 1'b0; + entry29_epn_q <= 52'b0; + entry29_class_q <= 2'b0; + entry29_extclass_q <= 2'b0; + entry29_hv_q <= 1'b0; + entry29_ds_q <= 1'b0; + entry29_thdid_q <= 4'b0; + entry29_pid_q <= 8'b0; + entry29_v_q <= 1'b0; + entry29_parity_q <= 10'b0; + entry29_cmpmask_q <= 9'b0; + entry30_size_q <= 3'b0; + entry30_xbit_q <= 1'b0; + entry30_epn_q <= 52'b0; + entry30_class_q <= 2'b0; + entry30_extclass_q <= 2'b0; + entry30_hv_q <= 1'b0; + entry30_ds_q <= 1'b0; + entry30_thdid_q <= 4'b0; + entry30_pid_q <= 8'b0; + entry30_v_q <= 1'b0; + entry30_parity_q <= 10'b0; + entry30_cmpmask_q <= 9'b0; + entry31_size_q <= 3'b0; + entry31_xbit_q <= 1'b0; + entry31_epn_q <= 52'b0; + entry31_class_q <= 2'b0; + entry31_extclass_q <= 2'b0; + entry31_hv_q <= 1'b0; + entry31_ds_q <= 1'b0; + entry31_thdid_q <= 4'b0; + entry31_pid_q <= 8'b0; + entry31_v_q <= 1'b0; + entry31_parity_q <= 10'b0; + entry31_cmpmask_q <= 9'b0; + end + else + begin + cam_cmp_data_q <= cam_cmp_data_d; + rd_cam_data_q <= rd_cam_data_d; + rd_array_data_q <= rd_array_data_d; + entry_match_q <= entry_match_d; + cam_hit_entry_q <= cam_hit_entry_d; + cam_hit_q <= cam_hit_d; + cam_cmp_parity_q <= cam_cmp_parity_d; + comp_addr_np1_q <= comp_addr_np1_d; + rpn_np2_q <= rpn_np2_d; + attr_np2_q <= attr_np2_d; + entry0_size_q <= entry0_size_d; + entry0_xbit_q <= entry0_xbit_d; + entry0_epn_q <= entry0_epn_d; + entry0_class_q <= entry0_class_d; + entry0_extclass_q <= entry0_extclass_d; + entry0_hv_q <= entry0_hv_d; + entry0_ds_q <= entry0_ds_d; + entry0_thdid_q <= entry0_thdid_d; + entry0_pid_q <= entry0_pid_d; + entry0_v_q <= entry0_v_d; + entry0_parity_q <= entry0_parity_d; + entry0_cmpmask_q <= entry0_cmpmask_d; + entry1_size_q <= entry1_size_d; + entry1_xbit_q <= entry1_xbit_d; + entry1_epn_q <= entry1_epn_d; + entry1_class_q <= entry1_class_d; + entry1_extclass_q <= entry1_extclass_d; + entry1_hv_q <= entry1_hv_d; + entry1_ds_q <= entry1_ds_d; + entry1_thdid_q <= entry1_thdid_d; + entry1_pid_q <= entry1_pid_d; + entry1_v_q <= entry1_v_d; + entry1_parity_q <= entry1_parity_d; + entry1_cmpmask_q <= entry1_cmpmask_d; + entry2_size_q <= entry2_size_d; + entry2_xbit_q <= entry2_xbit_d; + entry2_epn_q <= entry2_epn_d; + entry2_class_q <= entry2_class_d; + entry2_extclass_q <= entry2_extclass_d; + entry2_hv_q <= entry2_hv_d; + entry2_ds_q <= entry2_ds_d; + entry2_thdid_q <= entry2_thdid_d; + entry2_pid_q <= entry2_pid_d; + entry2_v_q <= entry2_v_d; + entry2_parity_q <= entry2_parity_d; + entry2_cmpmask_q <= entry2_cmpmask_d; + entry3_size_q <= entry3_size_d; + entry3_xbit_q <= entry3_xbit_d; + entry3_epn_q <= entry3_epn_d; + entry3_class_q <= entry3_class_d; + entry3_extclass_q <= entry3_extclass_d; + entry3_hv_q <= entry3_hv_d; + entry3_ds_q <= entry3_ds_d; + entry3_thdid_q <= entry3_thdid_d; + entry3_pid_q <= entry3_pid_d; + entry3_v_q <= entry3_v_d; + entry3_parity_q <= entry3_parity_d; + entry3_cmpmask_q <= entry3_cmpmask_d; + entry4_size_q <= entry4_size_d; + entry4_xbit_q <= entry4_xbit_d; + entry4_epn_q <= entry4_epn_d; + entry4_class_q <= entry4_class_d; + entry4_extclass_q <= entry4_extclass_d; + entry4_hv_q <= entry4_hv_d; + entry4_ds_q <= entry4_ds_d; + entry4_thdid_q <= entry4_thdid_d; + entry4_pid_q <= entry4_pid_d; + entry4_v_q <= entry4_v_d; + entry4_parity_q <= entry4_parity_d; + entry4_cmpmask_q <= entry4_cmpmask_d; + entry5_size_q <= entry5_size_d; + entry5_xbit_q <= entry5_xbit_d; + entry5_epn_q <= entry5_epn_d; + entry5_class_q <= entry5_class_d; + entry5_extclass_q <= entry5_extclass_d; + entry5_hv_q <= entry5_hv_d; + entry5_ds_q <= entry5_ds_d; + entry5_thdid_q <= entry5_thdid_d; + entry5_pid_q <= entry5_pid_d; + entry5_v_q <= entry5_v_d; + entry5_parity_q <= entry5_parity_d; + entry5_cmpmask_q <= entry5_cmpmask_d; + entry6_size_q <= entry6_size_d; + entry6_xbit_q <= entry6_xbit_d; + entry6_epn_q <= entry6_epn_d; + entry6_class_q <= entry6_class_d; + entry6_extclass_q <= entry6_extclass_d; + entry6_hv_q <= entry6_hv_d; + entry6_ds_q <= entry6_ds_d; + entry6_thdid_q <= entry6_thdid_d; + entry6_pid_q <= entry6_pid_d; + entry6_v_q <= entry6_v_d; + entry6_parity_q <= entry6_parity_d; + entry6_cmpmask_q <= entry6_cmpmask_d; + entry7_size_q <= entry7_size_d; + entry7_xbit_q <= entry7_xbit_d; + entry7_epn_q <= entry7_epn_d; + entry7_class_q <= entry7_class_d; + entry7_extclass_q <= entry7_extclass_d; + entry7_hv_q <= entry7_hv_d; + entry7_ds_q <= entry7_ds_d; + entry7_thdid_q <= entry7_thdid_d; + entry7_pid_q <= entry7_pid_d; + entry7_v_q <= entry7_v_d; + entry7_parity_q <= entry7_parity_d; + entry7_cmpmask_q <= entry7_cmpmask_d; + entry8_size_q <= entry8_size_d; + entry8_xbit_q <= entry8_xbit_d; + entry8_epn_q <= entry8_epn_d; + entry8_class_q <= entry8_class_d; + entry8_extclass_q <= entry8_extclass_d; + entry8_hv_q <= entry8_hv_d; + entry8_ds_q <= entry8_ds_d; + entry8_thdid_q <= entry8_thdid_d; + entry8_pid_q <= entry8_pid_d; + entry8_v_q <= entry8_v_d; + entry8_parity_q <= entry8_parity_d; + entry8_cmpmask_q <= entry8_cmpmask_d; + entry9_size_q <= entry9_size_d; + entry9_xbit_q <= entry9_xbit_d; + entry9_epn_q <= entry9_epn_d; + entry9_class_q <= entry9_class_d; + entry9_extclass_q <= entry9_extclass_d; + entry9_hv_q <= entry9_hv_d; + entry9_ds_q <= entry9_ds_d; + entry9_thdid_q <= entry9_thdid_d; + entry9_pid_q <= entry9_pid_d; + entry9_v_q <= entry9_v_d; + entry9_parity_q <= entry9_parity_d; + entry9_cmpmask_q <= entry9_cmpmask_d; + entry10_size_q <= entry10_size_d; + entry10_xbit_q <= entry10_xbit_d; + entry10_epn_q <= entry10_epn_d; + entry10_class_q <= entry10_class_d; + entry10_extclass_q <= entry10_extclass_d; + entry10_hv_q <= entry10_hv_d; + entry10_ds_q <= entry10_ds_d; + entry10_thdid_q <= entry10_thdid_d; + entry10_pid_q <= entry10_pid_d; + entry10_v_q <= entry10_v_d; + entry10_parity_q <= entry10_parity_d; + entry10_cmpmask_q <= entry10_cmpmask_d; + entry11_size_q <= entry11_size_d; + entry11_xbit_q <= entry11_xbit_d; + entry11_epn_q <= entry11_epn_d; + entry11_class_q <= entry11_class_d; + entry11_extclass_q <= entry11_extclass_d; + entry11_hv_q <= entry11_hv_d; + entry11_ds_q <= entry11_ds_d; + entry11_thdid_q <= entry11_thdid_d; + entry11_pid_q <= entry11_pid_d; + entry11_v_q <= entry11_v_d; + entry11_parity_q <= entry11_parity_d; + entry11_cmpmask_q <= entry11_cmpmask_d; + entry12_size_q <= entry12_size_d; + entry12_xbit_q <= entry12_xbit_d; + entry12_epn_q <= entry12_epn_d; + entry12_class_q <= entry12_class_d; + entry12_extclass_q <= entry12_extclass_d; + entry12_hv_q <= entry12_hv_d; + entry12_ds_q <= entry12_ds_d; + entry12_thdid_q <= entry12_thdid_d; + entry12_pid_q <= entry12_pid_d; + entry12_v_q <= entry12_v_d; + entry12_parity_q <= entry12_parity_d; + entry12_cmpmask_q <= entry12_cmpmask_d; + entry13_size_q <= entry13_size_d; + entry13_xbit_q <= entry13_xbit_d; + entry13_epn_q <= entry13_epn_d; + entry13_class_q <= entry13_class_d; + entry13_extclass_q <= entry13_extclass_d; + entry13_hv_q <= entry13_hv_d; + entry13_ds_q <= entry13_ds_d; + entry13_thdid_q <= entry13_thdid_d; + entry13_pid_q <= entry13_pid_d; + entry13_v_q <= entry13_v_d; + entry13_parity_q <= entry13_parity_d; + entry13_cmpmask_q <= entry13_cmpmask_d; + entry14_size_q <= entry14_size_d; + entry14_xbit_q <= entry14_xbit_d; + entry14_epn_q <= entry14_epn_d; + entry14_class_q <= entry14_class_d; + entry14_extclass_q <= entry14_extclass_d; + entry14_hv_q <= entry14_hv_d; + entry14_ds_q <= entry14_ds_d; + entry14_thdid_q <= entry14_thdid_d; + entry14_pid_q <= entry14_pid_d; + entry14_v_q <= entry14_v_d; + entry14_parity_q <= entry14_parity_d; + entry14_cmpmask_q <= entry14_cmpmask_d; + entry15_size_q <= entry15_size_d; + entry15_xbit_q <= entry15_xbit_d; + entry15_epn_q <= entry15_epn_d; + entry15_class_q <= entry15_class_d; + entry15_extclass_q <= entry15_extclass_d; + entry15_hv_q <= entry15_hv_d; + entry15_ds_q <= entry15_ds_d; + entry15_thdid_q <= entry15_thdid_d; + entry15_pid_q <= entry15_pid_d; + entry15_v_q <= entry15_v_d; + entry15_parity_q <= entry15_parity_d; + entry15_cmpmask_q <= entry15_cmpmask_d; + entry16_size_q <= entry16_size_d; + entry16_xbit_q <= entry16_xbit_d; + entry16_epn_q <= entry16_epn_d; + entry16_class_q <= entry16_class_d; + entry16_extclass_q <= entry16_extclass_d; + entry16_hv_q <= entry16_hv_d; + entry16_ds_q <= entry16_ds_d; + entry16_thdid_q <= entry16_thdid_d; + entry16_pid_q <= entry16_pid_d; + entry16_v_q <= entry16_v_d; + entry16_parity_q <= entry16_parity_d; + entry16_cmpmask_q <= entry16_cmpmask_d; + entry17_size_q <= entry17_size_d; + entry17_xbit_q <= entry17_xbit_d; + entry17_epn_q <= entry17_epn_d; + entry17_class_q <= entry17_class_d; + entry17_extclass_q <= entry17_extclass_d; + entry17_hv_q <= entry17_hv_d; + entry17_ds_q <= entry17_ds_d; + entry17_thdid_q <= entry17_thdid_d; + entry17_pid_q <= entry17_pid_d; + entry17_v_q <= entry17_v_d; + entry17_parity_q <= entry17_parity_d; + entry17_cmpmask_q <= entry17_cmpmask_d; + entry18_size_q <= entry18_size_d; + entry18_xbit_q <= entry18_xbit_d; + entry18_epn_q <= entry18_epn_d; + entry18_class_q <= entry18_class_d; + entry18_extclass_q <= entry18_extclass_d; + entry18_hv_q <= entry18_hv_d; + entry18_ds_q <= entry18_ds_d; + entry18_thdid_q <= entry18_thdid_d; + entry18_pid_q <= entry18_pid_d; + entry18_v_q <= entry18_v_d; + entry18_parity_q <= entry18_parity_d; + entry18_cmpmask_q <= entry18_cmpmask_d; + entry19_size_q <= entry19_size_d; + entry19_xbit_q <= entry19_xbit_d; + entry19_epn_q <= entry19_epn_d; + entry19_class_q <= entry19_class_d; + entry19_extclass_q <= entry19_extclass_d; + entry19_hv_q <= entry19_hv_d; + entry19_ds_q <= entry19_ds_d; + entry19_thdid_q <= entry19_thdid_d; + entry19_pid_q <= entry19_pid_d; + entry19_v_q <= entry19_v_d; + entry19_parity_q <= entry19_parity_d; + entry19_cmpmask_q <= entry19_cmpmask_d; + entry20_size_q <= entry20_size_d; + entry20_xbit_q <= entry20_xbit_d; + entry20_epn_q <= entry20_epn_d; + entry20_class_q <= entry20_class_d; + entry20_extclass_q <= entry20_extclass_d; + entry20_hv_q <= entry20_hv_d; + entry20_ds_q <= entry20_ds_d; + entry20_thdid_q <= entry20_thdid_d; + entry20_pid_q <= entry20_pid_d; + entry20_v_q <= entry20_v_d; + entry20_parity_q <= entry20_parity_d; + entry20_cmpmask_q <= entry20_cmpmask_d; + entry21_size_q <= entry21_size_d; + entry21_xbit_q <= entry21_xbit_d; + entry21_epn_q <= entry21_epn_d; + entry21_class_q <= entry21_class_d; + entry21_extclass_q <= entry21_extclass_d; + entry21_hv_q <= entry21_hv_d; + entry21_ds_q <= entry21_ds_d; + entry21_thdid_q <= entry21_thdid_d; + entry21_pid_q <= entry21_pid_d; + entry21_v_q <= entry21_v_d; + entry21_parity_q <= entry21_parity_d; + entry21_cmpmask_q <= entry21_cmpmask_d; + entry22_size_q <= entry22_size_d; + entry22_xbit_q <= entry22_xbit_d; + entry22_epn_q <= entry22_epn_d; + entry22_class_q <= entry22_class_d; + entry22_extclass_q <= entry22_extclass_d; + entry22_hv_q <= entry22_hv_d; + entry22_ds_q <= entry22_ds_d; + entry22_thdid_q <= entry22_thdid_d; + entry22_pid_q <= entry22_pid_d; + entry22_v_q <= entry22_v_d; + entry22_parity_q <= entry22_parity_d; + entry22_cmpmask_q <= entry22_cmpmask_d; + entry23_size_q <= entry23_size_d; + entry23_xbit_q <= entry23_xbit_d; + entry23_epn_q <= entry23_epn_d; + entry23_class_q <= entry23_class_d; + entry23_extclass_q <= entry23_extclass_d; + entry23_hv_q <= entry23_hv_d; + entry23_ds_q <= entry23_ds_d; + entry23_thdid_q <= entry23_thdid_d; + entry23_pid_q <= entry23_pid_d; + entry23_v_q <= entry23_v_d; + entry23_parity_q <= entry23_parity_d; + entry23_cmpmask_q <= entry23_cmpmask_d; + entry24_size_q <= entry24_size_d; + entry24_xbit_q <= entry24_xbit_d; + entry24_epn_q <= entry24_epn_d; + entry24_class_q <= entry24_class_d; + entry24_extclass_q <= entry24_extclass_d; + entry24_hv_q <= entry24_hv_d; + entry24_ds_q <= entry24_ds_d; + entry24_thdid_q <= entry24_thdid_d; + entry24_pid_q <= entry24_pid_d; + entry24_v_q <= entry24_v_d; + entry24_parity_q <= entry24_parity_d; + entry24_cmpmask_q <= entry24_cmpmask_d; + entry25_size_q <= entry25_size_d; + entry25_xbit_q <= entry25_xbit_d; + entry25_epn_q <= entry25_epn_d; + entry25_class_q <= entry25_class_d; + entry25_extclass_q <= entry25_extclass_d; + entry25_hv_q <= entry25_hv_d; + entry25_ds_q <= entry25_ds_d; + entry25_thdid_q <= entry25_thdid_d; + entry25_pid_q <= entry25_pid_d; + entry25_v_q <= entry25_v_d; + entry25_parity_q <= entry25_parity_d; + entry25_cmpmask_q <= entry25_cmpmask_d; + entry26_size_q <= entry26_size_d; + entry26_xbit_q <= entry26_xbit_d; + entry26_epn_q <= entry26_epn_d; + entry26_class_q <= entry26_class_d; + entry26_extclass_q <= entry26_extclass_d; + entry26_hv_q <= entry26_hv_d; + entry26_ds_q <= entry26_ds_d; + entry26_thdid_q <= entry26_thdid_d; + entry26_pid_q <= entry26_pid_d; + entry26_v_q <= entry26_v_d; + entry26_parity_q <= entry26_parity_d; + entry26_cmpmask_q <= entry26_cmpmask_d; + entry27_size_q <= entry27_size_d; + entry27_xbit_q <= entry27_xbit_d; + entry27_epn_q <= entry27_epn_d; + entry27_class_q <= entry27_class_d; + entry27_extclass_q <= entry27_extclass_d; + entry27_hv_q <= entry27_hv_d; + entry27_ds_q <= entry27_ds_d; + entry27_thdid_q <= entry27_thdid_d; + entry27_pid_q <= entry27_pid_d; + entry27_v_q <= entry27_v_d; + entry27_parity_q <= entry27_parity_d; + entry27_cmpmask_q <= entry27_cmpmask_d; + entry28_size_q <= entry28_size_d; + entry28_xbit_q <= entry28_xbit_d; + entry28_epn_q <= entry28_epn_d; + entry28_class_q <= entry28_class_d; + entry28_extclass_q <= entry28_extclass_d; + entry28_hv_q <= entry28_hv_d; + entry28_ds_q <= entry28_ds_d; + entry28_thdid_q <= entry28_thdid_d; + entry28_pid_q <= entry28_pid_d; + entry28_v_q <= entry28_v_d; + entry28_parity_q <= entry28_parity_d; + entry28_cmpmask_q <= entry28_cmpmask_d; + entry29_size_q <= entry29_size_d; + entry29_xbit_q <= entry29_xbit_d; + entry29_epn_q <= entry29_epn_d; + entry29_class_q <= entry29_class_d; + entry29_extclass_q <= entry29_extclass_d; + entry29_hv_q <= entry29_hv_d; + entry29_ds_q <= entry29_ds_d; + entry29_thdid_q <= entry29_thdid_d; + entry29_pid_q <= entry29_pid_d; + entry29_v_q <= entry29_v_d; + entry29_parity_q <= entry29_parity_d; + entry29_cmpmask_q <= entry29_cmpmask_d; + entry30_size_q <= entry30_size_d; + entry30_xbit_q <= entry30_xbit_d; + entry30_epn_q <= entry30_epn_d; + entry30_class_q <= entry30_class_d; + entry30_extclass_q <= entry30_extclass_d; + entry30_hv_q <= entry30_hv_d; + entry30_ds_q <= entry30_ds_d; + entry30_thdid_q <= entry30_thdid_d; + entry30_pid_q <= entry30_pid_d; + entry30_v_q <= entry30_v_d; + entry30_parity_q <= entry30_parity_d; + entry30_cmpmask_q <= entry30_cmpmask_d; + entry31_size_q <= entry31_size_d; + entry31_xbit_q <= entry31_xbit_d; + entry31_epn_q <= entry31_epn_d; + entry31_class_q <= entry31_class_d; + entry31_extclass_q <= entry31_extclass_d; + entry31_hv_q <= entry31_hv_d; + entry31_ds_q <= entry31_ds_d; + entry31_thdid_q <= entry31_thdid_d; + entry31_pid_q <= entry31_pid_d; + entry31_v_q <= entry31_v_d; + entry31_parity_q <= entry31_parity_d; + entry31_cmpmask_q <= entry31_cmpmask_d; + end + end + + //--------------------------------------------------------------------- + // latch input logic + //--------------------------------------------------------------------- + assign comp_addr_np1_d = comp_addr[52 - RPN_WIDTH:51]; + + assign cam_hit_d = ((match_vec != 32'b00000000000000000000000000000000) & (comp_request == 1'b1)) ? 1'b1 : + 1'b0; + + assign cam_hit_entry_d = (match_vec[0:1] == 2'b01) ? 5'b00001 : + (match_vec[0:2] == 3'b001) ? 5'b00010 : + (match_vec[0:3] == 4'b0001) ? 5'b00011 : + (match_vec[0:4] == 5'b00001) ? 5'b00100 : + (match_vec[0:5] == 6'b000001) ? 5'b00101 : + (match_vec[0:6] == 7'b0000001) ? 5'b00110 : + (match_vec[0:7] == 8'b00000001) ? 5'b00111 : + (match_vec[0:8] == 9'b000000001) ? 5'b01000 : + (match_vec[0:9] == 10'b0000000001) ? 5'b01001 : + (match_vec[0:10] == 11'b00000000001) ? 5'b01010 : + (match_vec[0:11] == 12'b000000000001) ? 5'b01011 : + (match_vec[0:12] == 13'b0000000000001) ? 5'b01100 : + (match_vec[0:13] == 14'b00000000000001) ? 5'b01101 : + (match_vec[0:14] == 15'b000000000000001) ? 5'b01110 : + (match_vec[0:15] == 16'b0000000000000001) ? 5'b01111 : + (match_vec[0:16] == 17'b00000000000000001) ? 5'b10000 : + (match_vec[0:17] == 18'b000000000000000001) ? 5'b10001 : + (match_vec[0:18] == 19'b0000000000000000001) ? 5'b10010 : + (match_vec[0:19] == 20'b00000000000000000001) ? 5'b10011 : + (match_vec[0:20] == 21'b000000000000000000001) ? 5'b10100 : + (match_vec[0:21] == 22'b0000000000000000000001) ? 5'b10101 : + (match_vec[0:22] == 23'b00000000000000000000001) ? 5'b10110 : + (match_vec[0:23] == 24'b000000000000000000000001) ? 5'b10111 : + (match_vec[0:24] == 25'b0000000000000000000000001) ? 5'b11000 : + (match_vec[0:25] == 26'b00000000000000000000000001) ? 5'b11001 : + (match_vec[0:26] == 27'b000000000000000000000000001) ? 5'b11010 : + (match_vec[0:27] == 28'b0000000000000000000000000001) ? 5'b11011 : + (match_vec[0:28] == 29'b00000000000000000000000000001) ? 5'b11100 : + (match_vec[0:29] == 30'b000000000000000000000000000001) ? 5'b11101 : + (match_vec[0:30] == 31'b0000000000000000000000000000001) ? 5'b11110 : + (match_vec[0:31] == 32'b00000000000000000000000000000001) ? 5'b11111 : + 5'b00000; + + assign entry_match_d = ((comp_request == 1'b1)) ? match_vec : + {NUM_ENTRY{1'b0}}; + + // entry write next state logic + assign wr_entry0_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b00000)) ? 1'b1 : + 1'b0; + assign wr_entry0_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b00000)) ? 1'b1 : + 1'b0; + assign entry0_epn_d[0:31] = (wr_entry0_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry0_epn_q[0:31]; + assign entry0_epn_d[32:51] = (wr_entry0_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry0_epn_q[32:51]; + assign entry0_xbit_d = (wr_entry0_sel[0] == 1'b1) ? wr_cam_data[52] : + entry0_xbit_q; + assign entry0_size_d = (wr_entry0_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry0_size_q[0:2]; + assign entry0_class_d = (wr_entry0_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry0_class_q[0:1]; + assign entry0_extclass_d = (wr_entry0_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry0_extclass_q[0:1]; + assign entry0_hv_d = (wr_entry0_sel[1] == 1'b1) ? wr_cam_data[65] : + entry0_hv_q; + assign entry0_ds_d = (wr_entry0_sel[1] == 1'b1) ? wr_cam_data[66] : + entry0_ds_q; + assign entry0_pid_d = (wr_entry0_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry0_pid_q[0:7]; + assign entry0_cmpmask_d = (wr_entry0_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry0_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry0_parity_d[0:3] = (wr_entry0_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry0_parity_q[0:3]; + assign entry0_parity_d[4:6] = (wr_entry0_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry0_parity_q[4:6]; + assign entry0_parity_d[7] = (wr_entry0_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry0_parity_q[7]; + assign entry0_parity_d[8] = (wr_entry0_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry0_parity_q[8]; + assign entry0_parity_d[9] = (wr_entry0_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry0_parity_q[9]; + assign wr_entry1_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b00001)) ? 1'b1 : + 1'b0; + assign wr_entry1_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b00001)) ? 1'b1 : + 1'b0; + assign entry1_epn_d[0:31] = (wr_entry1_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry1_epn_q[0:31]; + assign entry1_epn_d[32:51] = (wr_entry1_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry1_epn_q[32:51]; + assign entry1_xbit_d = (wr_entry1_sel[0] == 1'b1) ? wr_cam_data[52] : + entry1_xbit_q; + assign entry1_size_d = (wr_entry1_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry1_size_q[0:2]; + assign entry1_class_d = (wr_entry1_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry1_class_q[0:1]; + assign entry1_extclass_d = (wr_entry1_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry1_extclass_q[0:1]; + assign entry1_hv_d = (wr_entry1_sel[1] == 1'b1) ? wr_cam_data[65] : + entry1_hv_q; + assign entry1_ds_d = (wr_entry1_sel[1] == 1'b1) ? wr_cam_data[66] : + entry1_ds_q; + assign entry1_pid_d = (wr_entry1_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry1_pid_q[0:7]; + assign entry1_cmpmask_d = (wr_entry1_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry1_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry1_parity_d[0:3] = (wr_entry1_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry1_parity_q[0:3]; + assign entry1_parity_d[4:6] = (wr_entry1_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry1_parity_q[4:6]; + assign entry1_parity_d[7] = (wr_entry1_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry1_parity_q[7]; + assign entry1_parity_d[8] = (wr_entry1_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry1_parity_q[8]; + assign entry1_parity_d[9] = (wr_entry1_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry1_parity_q[9]; + assign wr_entry2_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b00010)) ? 1'b1 : + 1'b0; + assign wr_entry2_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b00010)) ? 1'b1 : + 1'b0; + assign entry2_epn_d[0:31] = (wr_entry2_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry2_epn_q[0:31]; + assign entry2_epn_d[32:51] = (wr_entry2_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry2_epn_q[32:51]; + assign entry2_xbit_d = (wr_entry2_sel[0] == 1'b1) ? wr_cam_data[52] : + entry2_xbit_q; + assign entry2_size_d = (wr_entry2_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry2_size_q[0:2]; + assign entry2_class_d = (wr_entry2_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry2_class_q[0:1]; + assign entry2_extclass_d = (wr_entry2_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry2_extclass_q[0:1]; + assign entry2_hv_d = (wr_entry2_sel[1] == 1'b1) ? wr_cam_data[65] : + entry2_hv_q; + assign entry2_ds_d = (wr_entry2_sel[1] == 1'b1) ? wr_cam_data[66] : + entry2_ds_q; + assign entry2_pid_d = (wr_entry2_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry2_pid_q[0:7]; + assign entry2_cmpmask_d = (wr_entry2_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry2_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry2_parity_d[0:3] = (wr_entry2_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry2_parity_q[0:3]; + assign entry2_parity_d[4:6] = (wr_entry2_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry2_parity_q[4:6]; + assign entry2_parity_d[7] = (wr_entry2_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry2_parity_q[7]; + assign entry2_parity_d[8] = (wr_entry2_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry2_parity_q[8]; + assign entry2_parity_d[9] = (wr_entry2_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry2_parity_q[9]; + assign wr_entry3_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b00011)) ? 1'b1 : + 1'b0; + assign wr_entry3_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b00011)) ? 1'b1 : + 1'b0; + assign entry3_epn_d[0:31] = (wr_entry3_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry3_epn_q[0:31]; + assign entry3_epn_d[32:51] = (wr_entry3_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry3_epn_q[32:51]; + assign entry3_xbit_d = (wr_entry3_sel[0] == 1'b1) ? wr_cam_data[52] : + entry3_xbit_q; + assign entry3_size_d = (wr_entry3_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry3_size_q[0:2]; + assign entry3_class_d = (wr_entry3_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry3_class_q[0:1]; + assign entry3_extclass_d = (wr_entry3_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry3_extclass_q[0:1]; + assign entry3_hv_d = (wr_entry3_sel[1] == 1'b1) ? wr_cam_data[65] : + entry3_hv_q; + assign entry3_ds_d = (wr_entry3_sel[1] == 1'b1) ? wr_cam_data[66] : + entry3_ds_q; + assign entry3_pid_d = (wr_entry3_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry3_pid_q[0:7]; + assign entry3_cmpmask_d = (wr_entry3_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry3_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry3_parity_d[0:3] = (wr_entry3_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry3_parity_q[0:3]; + assign entry3_parity_d[4:6] = (wr_entry3_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry3_parity_q[4:6]; + assign entry3_parity_d[7] = (wr_entry3_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry3_parity_q[7]; + assign entry3_parity_d[8] = (wr_entry3_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry3_parity_q[8]; + assign entry3_parity_d[9] = (wr_entry3_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry3_parity_q[9]; + assign wr_entry4_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b00100)) ? 1'b1 : + 1'b0; + assign wr_entry4_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b00100)) ? 1'b1 : + 1'b0; + assign entry4_epn_d[0:31] = (wr_entry4_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry4_epn_q[0:31]; + assign entry4_epn_d[32:51] = (wr_entry4_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry4_epn_q[32:51]; + assign entry4_xbit_d = (wr_entry4_sel[0] == 1'b1) ? wr_cam_data[52] : + entry4_xbit_q; + assign entry4_size_d = (wr_entry4_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry4_size_q[0:2]; + assign entry4_class_d = (wr_entry4_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry4_class_q[0:1]; + assign entry4_extclass_d = (wr_entry4_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry4_extclass_q[0:1]; + assign entry4_hv_d = (wr_entry4_sel[1] == 1'b1) ? wr_cam_data[65] : + entry4_hv_q; + assign entry4_ds_d = (wr_entry4_sel[1] == 1'b1) ? wr_cam_data[66] : + entry4_ds_q; + assign entry4_pid_d = (wr_entry4_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry4_pid_q[0:7]; + assign entry4_cmpmask_d = (wr_entry4_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry4_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry4_parity_d[0:3] = (wr_entry4_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry4_parity_q[0:3]; + assign entry4_parity_d[4:6] = (wr_entry4_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry4_parity_q[4:6]; + assign entry4_parity_d[7] = (wr_entry4_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry4_parity_q[7]; + assign entry4_parity_d[8] = (wr_entry4_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry4_parity_q[8]; + assign entry4_parity_d[9] = (wr_entry4_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry4_parity_q[9]; + assign wr_entry5_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b00101)) ? 1'b1 : + 1'b0; + assign wr_entry5_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b00101)) ? 1'b1 : + 1'b0; + assign entry5_epn_d[0:31] = (wr_entry5_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry5_epn_q[0:31]; + assign entry5_epn_d[32:51] = (wr_entry5_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry5_epn_q[32:51]; + assign entry5_xbit_d = (wr_entry5_sel[0] == 1'b1) ? wr_cam_data[52] : + entry5_xbit_q; + assign entry5_size_d = (wr_entry5_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry5_size_q[0:2]; + assign entry5_class_d = (wr_entry5_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry5_class_q[0:1]; + assign entry5_extclass_d = (wr_entry5_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry5_extclass_q[0:1]; + assign entry5_hv_d = (wr_entry5_sel[1] == 1'b1) ? wr_cam_data[65] : + entry5_hv_q; + assign entry5_ds_d = (wr_entry5_sel[1] == 1'b1) ? wr_cam_data[66] : + entry5_ds_q; + assign entry5_pid_d = (wr_entry5_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry5_pid_q[0:7]; + assign entry5_cmpmask_d = (wr_entry5_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry5_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry5_parity_d[0:3] = (wr_entry5_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry5_parity_q[0:3]; + assign entry5_parity_d[4:6] = (wr_entry5_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry5_parity_q[4:6]; + assign entry5_parity_d[7] = (wr_entry5_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry5_parity_q[7]; + assign entry5_parity_d[8] = (wr_entry5_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry5_parity_q[8]; + assign entry5_parity_d[9] = (wr_entry5_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry5_parity_q[9]; + assign wr_entry6_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b00110)) ? 1'b1 : + 1'b0; + assign wr_entry6_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b00110)) ? 1'b1 : + 1'b0; + assign entry6_epn_d[0:31] = (wr_entry6_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry6_epn_q[0:31]; + assign entry6_epn_d[32:51] = (wr_entry6_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry6_epn_q[32:51]; + assign entry6_xbit_d = (wr_entry6_sel[0] == 1'b1) ? wr_cam_data[52] : + entry6_xbit_q; + assign entry6_size_d = (wr_entry6_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry6_size_q[0:2]; + assign entry6_class_d = (wr_entry6_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry6_class_q[0:1]; + assign entry6_extclass_d = (wr_entry6_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry6_extclass_q[0:1]; + assign entry6_hv_d = (wr_entry6_sel[1] == 1'b1) ? wr_cam_data[65] : + entry6_hv_q; + assign entry6_ds_d = (wr_entry6_sel[1] == 1'b1) ? wr_cam_data[66] : + entry6_ds_q; + assign entry6_pid_d = (wr_entry6_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry6_pid_q[0:7]; + assign entry6_cmpmask_d = (wr_entry6_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry6_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry6_parity_d[0:3] = (wr_entry6_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry6_parity_q[0:3]; + assign entry6_parity_d[4:6] = (wr_entry6_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry6_parity_q[4:6]; + assign entry6_parity_d[7] = (wr_entry6_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry6_parity_q[7]; + assign entry6_parity_d[8] = (wr_entry6_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry6_parity_q[8]; + assign entry6_parity_d[9] = (wr_entry6_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry6_parity_q[9]; + assign wr_entry7_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b00111)) ? 1'b1 : + 1'b0; + assign wr_entry7_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b00111)) ? 1'b1 : + 1'b0; + assign entry7_epn_d[0:31] = (wr_entry7_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry7_epn_q[0:31]; + assign entry7_epn_d[32:51] = (wr_entry7_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry7_epn_q[32:51]; + assign entry7_xbit_d = (wr_entry7_sel[0] == 1'b1) ? wr_cam_data[52] : + entry7_xbit_q; + assign entry7_size_d = (wr_entry7_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry7_size_q[0:2]; + assign entry7_class_d = (wr_entry7_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry7_class_q[0:1]; + assign entry7_extclass_d = (wr_entry7_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry7_extclass_q[0:1]; + assign entry7_hv_d = (wr_entry7_sel[1] == 1'b1) ? wr_cam_data[65] : + entry7_hv_q; + assign entry7_ds_d = (wr_entry7_sel[1] == 1'b1) ? wr_cam_data[66] : + entry7_ds_q; + assign entry7_pid_d = (wr_entry7_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry7_pid_q[0:7]; + assign entry7_cmpmask_d = (wr_entry7_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry7_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry7_parity_d[0:3] = (wr_entry7_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry7_parity_q[0:3]; + assign entry7_parity_d[4:6] = (wr_entry7_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry7_parity_q[4:6]; + assign entry7_parity_d[7] = (wr_entry7_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry7_parity_q[7]; + assign entry7_parity_d[8] = (wr_entry7_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry7_parity_q[8]; + assign entry7_parity_d[9] = (wr_entry7_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry7_parity_q[9]; + assign wr_entry8_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b01000)) ? 1'b1 : + 1'b0; + assign wr_entry8_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b01000)) ? 1'b1 : + 1'b0; + assign entry8_epn_d[0:31] = (wr_entry8_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry8_epn_q[0:31]; + assign entry8_epn_d[32:51] = (wr_entry8_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry8_epn_q[32:51]; + assign entry8_xbit_d = (wr_entry8_sel[0] == 1'b1) ? wr_cam_data[52] : + entry8_xbit_q; + assign entry8_size_d = (wr_entry8_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry8_size_q[0:2]; + assign entry8_class_d = (wr_entry8_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry8_class_q[0:1]; + assign entry8_extclass_d = (wr_entry8_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry8_extclass_q[0:1]; + assign entry8_hv_d = (wr_entry8_sel[1] == 1'b1) ? wr_cam_data[65] : + entry8_hv_q; + assign entry8_ds_d = (wr_entry8_sel[1] == 1'b1) ? wr_cam_data[66] : + entry8_ds_q; + assign entry8_pid_d = (wr_entry8_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry8_pid_q[0:7]; + assign entry8_cmpmask_d = (wr_entry8_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry8_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry8_parity_d[0:3] = (wr_entry8_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry8_parity_q[0:3]; + assign entry8_parity_d[4:6] = (wr_entry8_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry8_parity_q[4:6]; + assign entry8_parity_d[7] = (wr_entry8_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry8_parity_q[7]; + assign entry8_parity_d[8] = (wr_entry8_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry8_parity_q[8]; + assign entry8_parity_d[9] = (wr_entry8_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry8_parity_q[9]; + assign wr_entry9_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b01001)) ? 1'b1 : + 1'b0; + assign wr_entry9_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b01001)) ? 1'b1 : + 1'b0; + assign entry9_epn_d[0:31] = (wr_entry9_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry9_epn_q[0:31]; + assign entry9_epn_d[32:51] = (wr_entry9_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry9_epn_q[32:51]; + assign entry9_xbit_d = (wr_entry9_sel[0] == 1'b1) ? wr_cam_data[52] : + entry9_xbit_q; + assign entry9_size_d = (wr_entry9_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry9_size_q[0:2]; + assign entry9_class_d = (wr_entry9_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry9_class_q[0:1]; + assign entry9_extclass_d = (wr_entry9_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry9_extclass_q[0:1]; + assign entry9_hv_d = (wr_entry9_sel[1] == 1'b1) ? wr_cam_data[65] : + entry9_hv_q; + assign entry9_ds_d = (wr_entry9_sel[1] == 1'b1) ? wr_cam_data[66] : + entry9_ds_q; + assign entry9_pid_d = (wr_entry9_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry9_pid_q[0:7]; + assign entry9_cmpmask_d = (wr_entry9_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry9_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry9_parity_d[0:3] = (wr_entry9_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry9_parity_q[0:3]; + assign entry9_parity_d[4:6] = (wr_entry9_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry9_parity_q[4:6]; + assign entry9_parity_d[7] = (wr_entry9_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry9_parity_q[7]; + assign entry9_parity_d[8] = (wr_entry9_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry9_parity_q[8]; + assign entry9_parity_d[9] = (wr_entry9_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry9_parity_q[9]; + assign wr_entry10_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b01010)) ? 1'b1 : + 1'b0; + assign wr_entry10_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b01010)) ? 1'b1 : + 1'b0; + assign entry10_epn_d[0:31] = (wr_entry10_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry10_epn_q[0:31]; + assign entry10_epn_d[32:51] = (wr_entry10_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry10_epn_q[32:51]; + assign entry10_xbit_d = (wr_entry10_sel[0] == 1'b1) ? wr_cam_data[52] : + entry10_xbit_q; + assign entry10_size_d = (wr_entry10_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry10_size_q[0:2]; + assign entry10_class_d = (wr_entry10_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry10_class_q[0:1]; + assign entry10_extclass_d = (wr_entry10_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry10_extclass_q[0:1]; + assign entry10_hv_d = (wr_entry10_sel[1] == 1'b1) ? wr_cam_data[65] : + entry10_hv_q; + assign entry10_ds_d = (wr_entry10_sel[1] == 1'b1) ? wr_cam_data[66] : + entry10_ds_q; + assign entry10_pid_d = (wr_entry10_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry10_pid_q[0:7]; + assign entry10_cmpmask_d = (wr_entry10_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry10_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry10_parity_d[0:3] = (wr_entry10_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry10_parity_q[0:3]; + assign entry10_parity_d[4:6] = (wr_entry10_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry10_parity_q[4:6]; + assign entry10_parity_d[7] = (wr_entry10_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry10_parity_q[7]; + assign entry10_parity_d[8] = (wr_entry10_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry10_parity_q[8]; + assign entry10_parity_d[9] = (wr_entry10_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry10_parity_q[9]; + assign wr_entry11_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b01011)) ? 1'b1 : + 1'b0; + assign wr_entry11_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b01011)) ? 1'b1 : + 1'b0; + assign entry11_epn_d[0:31] = (wr_entry11_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry11_epn_q[0:31]; + assign entry11_epn_d[32:51] = (wr_entry11_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry11_epn_q[32:51]; + assign entry11_xbit_d = (wr_entry11_sel[0] == 1'b1) ? wr_cam_data[52] : + entry11_xbit_q; + assign entry11_size_d = (wr_entry11_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry11_size_q[0:2]; + assign entry11_class_d = (wr_entry11_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry11_class_q[0:1]; + assign entry11_extclass_d = (wr_entry11_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry11_extclass_q[0:1]; + assign entry11_hv_d = (wr_entry11_sel[1] == 1'b1) ? wr_cam_data[65] : + entry11_hv_q; + assign entry11_ds_d = (wr_entry11_sel[1] == 1'b1) ? wr_cam_data[66] : + entry11_ds_q; + assign entry11_pid_d = (wr_entry11_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry11_pid_q[0:7]; + assign entry11_cmpmask_d = (wr_entry11_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry11_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry11_parity_d[0:3] = (wr_entry11_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry11_parity_q[0:3]; + assign entry11_parity_d[4:6] = (wr_entry11_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry11_parity_q[4:6]; + assign entry11_parity_d[7] = (wr_entry11_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry11_parity_q[7]; + assign entry11_parity_d[8] = (wr_entry11_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry11_parity_q[8]; + assign entry11_parity_d[9] = (wr_entry11_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry11_parity_q[9]; + assign wr_entry12_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b01100)) ? 1'b1 : + 1'b0; + assign wr_entry12_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b01100)) ? 1'b1 : + 1'b0; + assign entry12_epn_d[0:31] = (wr_entry12_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry12_epn_q[0:31]; + assign entry12_epn_d[32:51] = (wr_entry12_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry12_epn_q[32:51]; + assign entry12_xbit_d = (wr_entry12_sel[0] == 1'b1) ? wr_cam_data[52] : + entry12_xbit_q; + assign entry12_size_d = (wr_entry12_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry12_size_q[0:2]; + assign entry12_class_d = (wr_entry12_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry12_class_q[0:1]; + assign entry12_extclass_d = (wr_entry12_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry12_extclass_q[0:1]; + assign entry12_hv_d = (wr_entry12_sel[1] == 1'b1) ? wr_cam_data[65] : + entry12_hv_q; + assign entry12_ds_d = (wr_entry12_sel[1] == 1'b1) ? wr_cam_data[66] : + entry12_ds_q; + assign entry12_pid_d = (wr_entry12_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry12_pid_q[0:7]; + assign entry12_cmpmask_d = (wr_entry12_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry12_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry12_parity_d[0:3] = (wr_entry12_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry12_parity_q[0:3]; + assign entry12_parity_d[4:6] = (wr_entry12_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry12_parity_q[4:6]; + assign entry12_parity_d[7] = (wr_entry12_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry12_parity_q[7]; + assign entry12_parity_d[8] = (wr_entry12_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry12_parity_q[8]; + assign entry12_parity_d[9] = (wr_entry12_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry12_parity_q[9]; + assign wr_entry13_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b01101)) ? 1'b1 : + 1'b0; + assign wr_entry13_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b01101)) ? 1'b1 : + 1'b0; + assign entry13_epn_d[0:31] = (wr_entry13_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry13_epn_q[0:31]; + assign entry13_epn_d[32:51] = (wr_entry13_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry13_epn_q[32:51]; + assign entry13_xbit_d = (wr_entry13_sel[0] == 1'b1) ? wr_cam_data[52] : + entry13_xbit_q; + assign entry13_size_d = (wr_entry13_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry13_size_q[0:2]; + assign entry13_class_d = (wr_entry13_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry13_class_q[0:1]; + assign entry13_extclass_d = (wr_entry13_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry13_extclass_q[0:1]; + assign entry13_hv_d = (wr_entry13_sel[1] == 1'b1) ? wr_cam_data[65] : + entry13_hv_q; + assign entry13_ds_d = (wr_entry13_sel[1] == 1'b1) ? wr_cam_data[66] : + entry13_ds_q; + assign entry13_pid_d = (wr_entry13_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry13_pid_q[0:7]; + assign entry13_cmpmask_d = (wr_entry13_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry13_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry13_parity_d[0:3] = (wr_entry13_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry13_parity_q[0:3]; + assign entry13_parity_d[4:6] = (wr_entry13_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry13_parity_q[4:6]; + assign entry13_parity_d[7] = (wr_entry13_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry13_parity_q[7]; + assign entry13_parity_d[8] = (wr_entry13_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry13_parity_q[8]; + assign entry13_parity_d[9] = (wr_entry13_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry13_parity_q[9]; + assign wr_entry14_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b01110)) ? 1'b1 : + 1'b0; + assign wr_entry14_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b01110)) ? 1'b1 : + 1'b0; + assign entry14_epn_d[0:31] = (wr_entry14_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry14_epn_q[0:31]; + assign entry14_epn_d[32:51] = (wr_entry14_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry14_epn_q[32:51]; + assign entry14_xbit_d = (wr_entry14_sel[0] == 1'b1) ? wr_cam_data[52] : + entry14_xbit_q; + assign entry14_size_d = (wr_entry14_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry14_size_q[0:2]; + assign entry14_class_d = (wr_entry14_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry14_class_q[0:1]; + assign entry14_extclass_d = (wr_entry14_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry14_extclass_q[0:1]; + assign entry14_hv_d = (wr_entry14_sel[1] == 1'b1) ? wr_cam_data[65] : + entry14_hv_q; + assign entry14_ds_d = (wr_entry14_sel[1] == 1'b1) ? wr_cam_data[66] : + entry14_ds_q; + assign entry14_pid_d = (wr_entry14_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry14_pid_q[0:7]; + assign entry14_cmpmask_d = (wr_entry14_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry14_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry14_parity_d[0:3] = (wr_entry14_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry14_parity_q[0:3]; + assign entry14_parity_d[4:6] = (wr_entry14_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry14_parity_q[4:6]; + assign entry14_parity_d[7] = (wr_entry14_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry14_parity_q[7]; + assign entry14_parity_d[8] = (wr_entry14_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry14_parity_q[8]; + assign entry14_parity_d[9] = (wr_entry14_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry14_parity_q[9]; + assign wr_entry15_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b01111)) ? 1'b1 : + 1'b0; + assign wr_entry15_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b01111)) ? 1'b1 : + 1'b0; + assign entry15_epn_d[0:31] = (wr_entry15_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry15_epn_q[0:31]; + assign entry15_epn_d[32:51] = (wr_entry15_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry15_epn_q[32:51]; + assign entry15_xbit_d = (wr_entry15_sel[0] == 1'b1) ? wr_cam_data[52] : + entry15_xbit_q; + assign entry15_size_d = (wr_entry15_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry15_size_q[0:2]; + assign entry15_class_d = (wr_entry15_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry15_class_q[0:1]; + assign entry15_extclass_d = (wr_entry15_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry15_extclass_q[0:1]; + assign entry15_hv_d = (wr_entry15_sel[1] == 1'b1) ? wr_cam_data[65] : + entry15_hv_q; + assign entry15_ds_d = (wr_entry15_sel[1] == 1'b1) ? wr_cam_data[66] : + entry15_ds_q; + assign entry15_pid_d = (wr_entry15_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry15_pid_q[0:7]; + assign entry15_cmpmask_d = (wr_entry15_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry15_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry15_parity_d[0:3] = (wr_entry15_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry15_parity_q[0:3]; + assign entry15_parity_d[4:6] = (wr_entry15_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry15_parity_q[4:6]; + assign entry15_parity_d[7] = (wr_entry15_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry15_parity_q[7]; + assign entry15_parity_d[8] = (wr_entry15_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry15_parity_q[8]; + assign entry15_parity_d[9] = (wr_entry15_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry15_parity_q[9]; + assign wr_entry16_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b10000)) ? 1'b1 : + 1'b0; + assign wr_entry16_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b10000)) ? 1'b1 : + 1'b0; + assign entry16_epn_d[0:31] = (wr_entry16_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry16_epn_q[0:31]; + assign entry16_epn_d[32:51] = (wr_entry16_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry16_epn_q[32:51]; + assign entry16_xbit_d = (wr_entry16_sel[0] == 1'b1) ? wr_cam_data[52] : + entry16_xbit_q; + assign entry16_size_d = (wr_entry16_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry16_size_q[0:2]; + assign entry16_class_d = (wr_entry16_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry16_class_q[0:1]; + assign entry16_extclass_d = (wr_entry16_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry16_extclass_q[0:1]; + assign entry16_hv_d = (wr_entry16_sel[1] == 1'b1) ? wr_cam_data[65] : + entry16_hv_q; + assign entry16_ds_d = (wr_entry16_sel[1] == 1'b1) ? wr_cam_data[66] : + entry16_ds_q; + assign entry16_pid_d = (wr_entry16_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry16_pid_q[0:7]; + assign entry16_cmpmask_d = (wr_entry16_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry16_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry16_parity_d[0:3] = (wr_entry16_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry16_parity_q[0:3]; + assign entry16_parity_d[4:6] = (wr_entry16_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry16_parity_q[4:6]; + assign entry16_parity_d[7] = (wr_entry16_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry16_parity_q[7]; + assign entry16_parity_d[8] = (wr_entry16_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry16_parity_q[8]; + assign entry16_parity_d[9] = (wr_entry16_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry16_parity_q[9]; + assign wr_entry17_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b10001)) ? 1'b1 : + 1'b0; + assign wr_entry17_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b10001)) ? 1'b1 : + 1'b0; + assign entry17_epn_d[0:31] = (wr_entry17_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry17_epn_q[0:31]; + assign entry17_epn_d[32:51] = (wr_entry17_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry17_epn_q[32:51]; + assign entry17_xbit_d = (wr_entry17_sel[0] == 1'b1) ? wr_cam_data[52] : + entry17_xbit_q; + assign entry17_size_d = (wr_entry17_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry17_size_q[0:2]; + assign entry17_class_d = (wr_entry17_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry17_class_q[0:1]; + assign entry17_extclass_d = (wr_entry17_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry17_extclass_q[0:1]; + assign entry17_hv_d = (wr_entry17_sel[1] == 1'b1) ? wr_cam_data[65] : + entry17_hv_q; + assign entry17_ds_d = (wr_entry17_sel[1] == 1'b1) ? wr_cam_data[66] : + entry17_ds_q; + assign entry17_pid_d = (wr_entry17_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry17_pid_q[0:7]; + assign entry17_cmpmask_d = (wr_entry17_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry17_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry17_parity_d[0:3] = (wr_entry17_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry17_parity_q[0:3]; + assign entry17_parity_d[4:6] = (wr_entry17_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry17_parity_q[4:6]; + assign entry17_parity_d[7] = (wr_entry17_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry17_parity_q[7]; + assign entry17_parity_d[8] = (wr_entry17_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry17_parity_q[8]; + assign entry17_parity_d[9] = (wr_entry17_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry17_parity_q[9]; + assign wr_entry18_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b10010)) ? 1'b1 : + 1'b0; + assign wr_entry18_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b10010)) ? 1'b1 : + 1'b0; + assign entry18_epn_d[0:31] = (wr_entry18_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry18_epn_q[0:31]; + assign entry18_epn_d[32:51] = (wr_entry18_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry18_epn_q[32:51]; + assign entry18_xbit_d = (wr_entry18_sel[0] == 1'b1) ? wr_cam_data[52] : + entry18_xbit_q; + assign entry18_size_d = (wr_entry18_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry18_size_q[0:2]; + assign entry18_class_d = (wr_entry18_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry18_class_q[0:1]; + assign entry18_extclass_d = (wr_entry18_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry18_extclass_q[0:1]; + assign entry18_hv_d = (wr_entry18_sel[1] == 1'b1) ? wr_cam_data[65] : + entry18_hv_q; + assign entry18_ds_d = (wr_entry18_sel[1] == 1'b1) ? wr_cam_data[66] : + entry18_ds_q; + assign entry18_pid_d = (wr_entry18_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry18_pid_q[0:7]; + assign entry18_cmpmask_d = (wr_entry18_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry18_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry18_parity_d[0:3] = (wr_entry18_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry18_parity_q[0:3]; + assign entry18_parity_d[4:6] = (wr_entry18_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry18_parity_q[4:6]; + assign entry18_parity_d[7] = (wr_entry18_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry18_parity_q[7]; + assign entry18_parity_d[8] = (wr_entry18_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry18_parity_q[8]; + assign entry18_parity_d[9] = (wr_entry18_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry18_parity_q[9]; + assign wr_entry19_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b10011)) ? 1'b1 : + 1'b0; + assign wr_entry19_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b10011)) ? 1'b1 : + 1'b0; + assign entry19_epn_d[0:31] = (wr_entry19_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry19_epn_q[0:31]; + assign entry19_epn_d[32:51] = (wr_entry19_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry19_epn_q[32:51]; + assign entry19_xbit_d = (wr_entry19_sel[0] == 1'b1) ? wr_cam_data[52] : + entry19_xbit_q; + assign entry19_size_d = (wr_entry19_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry19_size_q[0:2]; + assign entry19_class_d = (wr_entry19_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry19_class_q[0:1]; + assign entry19_extclass_d = (wr_entry19_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry19_extclass_q[0:1]; + assign entry19_hv_d = (wr_entry19_sel[1] == 1'b1) ? wr_cam_data[65] : + entry19_hv_q; + assign entry19_ds_d = (wr_entry19_sel[1] == 1'b1) ? wr_cam_data[66] : + entry19_ds_q; + assign entry19_pid_d = (wr_entry19_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry19_pid_q[0:7]; + assign entry19_cmpmask_d = (wr_entry19_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry19_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry19_parity_d[0:3] = (wr_entry19_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry19_parity_q[0:3]; + assign entry19_parity_d[4:6] = (wr_entry19_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry19_parity_q[4:6]; + assign entry19_parity_d[7] = (wr_entry19_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry19_parity_q[7]; + assign entry19_parity_d[8] = (wr_entry19_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry19_parity_q[8]; + assign entry19_parity_d[9] = (wr_entry19_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry19_parity_q[9]; + assign wr_entry20_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b10100)) ? 1'b1 : + 1'b0; + assign wr_entry20_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b10100)) ? 1'b1 : + 1'b0; + assign entry20_epn_d[0:31] = (wr_entry20_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry20_epn_q[0:31]; + assign entry20_epn_d[32:51] = (wr_entry20_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry20_epn_q[32:51]; + assign entry20_xbit_d = (wr_entry20_sel[0] == 1'b1) ? wr_cam_data[52] : + entry20_xbit_q; + assign entry20_size_d = (wr_entry20_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry20_size_q[0:2]; + assign entry20_class_d = (wr_entry20_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry20_class_q[0:1]; + assign entry20_extclass_d = (wr_entry20_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry20_extclass_q[0:1]; + assign entry20_hv_d = (wr_entry20_sel[1] == 1'b1) ? wr_cam_data[65] : + entry20_hv_q; + assign entry20_ds_d = (wr_entry20_sel[1] == 1'b1) ? wr_cam_data[66] : + entry20_ds_q; + assign entry20_pid_d = (wr_entry20_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry20_pid_q[0:7]; + assign entry20_cmpmask_d = (wr_entry20_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry20_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry20_parity_d[0:3] = (wr_entry20_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry20_parity_q[0:3]; + assign entry20_parity_d[4:6] = (wr_entry20_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry20_parity_q[4:6]; + assign entry20_parity_d[7] = (wr_entry20_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry20_parity_q[7]; + assign entry20_parity_d[8] = (wr_entry20_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry20_parity_q[8]; + assign entry20_parity_d[9] = (wr_entry20_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry20_parity_q[9]; + assign wr_entry21_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b10101)) ? 1'b1 : + 1'b0; + assign wr_entry21_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b10101)) ? 1'b1 : + 1'b0; + assign entry21_epn_d[0:31] = (wr_entry21_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry21_epn_q[0:31]; + assign entry21_epn_d[32:51] = (wr_entry21_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry21_epn_q[32:51]; + assign entry21_xbit_d = (wr_entry21_sel[0] == 1'b1) ? wr_cam_data[52] : + entry21_xbit_q; + assign entry21_size_d = (wr_entry21_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry21_size_q[0:2]; + assign entry21_class_d = (wr_entry21_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry21_class_q[0:1]; + assign entry21_extclass_d = (wr_entry21_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry21_extclass_q[0:1]; + assign entry21_hv_d = (wr_entry21_sel[1] == 1'b1) ? wr_cam_data[65] : + entry21_hv_q; + assign entry21_ds_d = (wr_entry21_sel[1] == 1'b1) ? wr_cam_data[66] : + entry21_ds_q; + assign entry21_pid_d = (wr_entry21_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry21_pid_q[0:7]; + assign entry21_cmpmask_d = (wr_entry21_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry21_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry21_parity_d[0:3] = (wr_entry21_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry21_parity_q[0:3]; + assign entry21_parity_d[4:6] = (wr_entry21_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry21_parity_q[4:6]; + assign entry21_parity_d[7] = (wr_entry21_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry21_parity_q[7]; + assign entry21_parity_d[8] = (wr_entry21_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry21_parity_q[8]; + assign entry21_parity_d[9] = (wr_entry21_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry21_parity_q[9]; + assign wr_entry22_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b10110)) ? 1'b1 : + 1'b0; + assign wr_entry22_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b10110)) ? 1'b1 : + 1'b0; + assign entry22_epn_d[0:31] = (wr_entry22_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry22_epn_q[0:31]; + assign entry22_epn_d[32:51] = (wr_entry22_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry22_epn_q[32:51]; + assign entry22_xbit_d = (wr_entry22_sel[0] == 1'b1) ? wr_cam_data[52] : + entry22_xbit_q; + assign entry22_size_d = (wr_entry22_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry22_size_q[0:2]; + assign entry22_class_d = (wr_entry22_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry22_class_q[0:1]; + assign entry22_extclass_d = (wr_entry22_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry22_extclass_q[0:1]; + assign entry22_hv_d = (wr_entry22_sel[1] == 1'b1) ? wr_cam_data[65] : + entry22_hv_q; + assign entry22_ds_d = (wr_entry22_sel[1] == 1'b1) ? wr_cam_data[66] : + entry22_ds_q; + assign entry22_pid_d = (wr_entry22_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry22_pid_q[0:7]; + assign entry22_cmpmask_d = (wr_entry22_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry22_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry22_parity_d[0:3] = (wr_entry22_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry22_parity_q[0:3]; + assign entry22_parity_d[4:6] = (wr_entry22_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry22_parity_q[4:6]; + assign entry22_parity_d[7] = (wr_entry22_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry22_parity_q[7]; + assign entry22_parity_d[8] = (wr_entry22_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry22_parity_q[8]; + assign entry22_parity_d[9] = (wr_entry22_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry22_parity_q[9]; + assign wr_entry23_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b10111)) ? 1'b1 : + 1'b0; + assign wr_entry23_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b10111)) ? 1'b1 : + 1'b0; + assign entry23_epn_d[0:31] = (wr_entry23_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry23_epn_q[0:31]; + assign entry23_epn_d[32:51] = (wr_entry23_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry23_epn_q[32:51]; + assign entry23_xbit_d = (wr_entry23_sel[0] == 1'b1) ? wr_cam_data[52] : + entry23_xbit_q; + assign entry23_size_d = (wr_entry23_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry23_size_q[0:2]; + assign entry23_class_d = (wr_entry23_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry23_class_q[0:1]; + assign entry23_extclass_d = (wr_entry23_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry23_extclass_q[0:1]; + assign entry23_hv_d = (wr_entry23_sel[1] == 1'b1) ? wr_cam_data[65] : + entry23_hv_q; + assign entry23_ds_d = (wr_entry23_sel[1] == 1'b1) ? wr_cam_data[66] : + entry23_ds_q; + assign entry23_pid_d = (wr_entry23_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry23_pid_q[0:7]; + assign entry23_cmpmask_d = (wr_entry23_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry23_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry23_parity_d[0:3] = (wr_entry23_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry23_parity_q[0:3]; + assign entry23_parity_d[4:6] = (wr_entry23_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry23_parity_q[4:6]; + assign entry23_parity_d[7] = (wr_entry23_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry23_parity_q[7]; + assign entry23_parity_d[8] = (wr_entry23_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry23_parity_q[8]; + assign entry23_parity_d[9] = (wr_entry23_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry23_parity_q[9]; + assign wr_entry24_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b11000)) ? 1'b1 : + 1'b0; + assign wr_entry24_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b11000)) ? 1'b1 : + 1'b0; + assign entry24_epn_d[0:31] = (wr_entry24_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry24_epn_q[0:31]; + assign entry24_epn_d[32:51] = (wr_entry24_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry24_epn_q[32:51]; + assign entry24_xbit_d = (wr_entry24_sel[0] == 1'b1) ? wr_cam_data[52] : + entry24_xbit_q; + assign entry24_size_d = (wr_entry24_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry24_size_q[0:2]; + assign entry24_class_d = (wr_entry24_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry24_class_q[0:1]; + assign entry24_extclass_d = (wr_entry24_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry24_extclass_q[0:1]; + assign entry24_hv_d = (wr_entry24_sel[1] == 1'b1) ? wr_cam_data[65] : + entry24_hv_q; + assign entry24_ds_d = (wr_entry24_sel[1] == 1'b1) ? wr_cam_data[66] : + entry24_ds_q; + assign entry24_pid_d = (wr_entry24_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry24_pid_q[0:7]; + assign entry24_cmpmask_d = (wr_entry24_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry24_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry24_parity_d[0:3] = (wr_entry24_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry24_parity_q[0:3]; + assign entry24_parity_d[4:6] = (wr_entry24_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry24_parity_q[4:6]; + assign entry24_parity_d[7] = (wr_entry24_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry24_parity_q[7]; + assign entry24_parity_d[8] = (wr_entry24_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry24_parity_q[8]; + assign entry24_parity_d[9] = (wr_entry24_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry24_parity_q[9]; + assign wr_entry25_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b11001)) ? 1'b1 : + 1'b0; + assign wr_entry25_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b11001)) ? 1'b1 : + 1'b0; + assign entry25_epn_d[0:31] = (wr_entry25_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry25_epn_q[0:31]; + assign entry25_epn_d[32:51] = (wr_entry25_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry25_epn_q[32:51]; + assign entry25_xbit_d = (wr_entry25_sel[0] == 1'b1) ? wr_cam_data[52] : + entry25_xbit_q; + assign entry25_size_d = (wr_entry25_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry25_size_q[0:2]; + assign entry25_class_d = (wr_entry25_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry25_class_q[0:1]; + assign entry25_extclass_d = (wr_entry25_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry25_extclass_q[0:1]; + assign entry25_hv_d = (wr_entry25_sel[1] == 1'b1) ? wr_cam_data[65] : + entry25_hv_q; + assign entry25_ds_d = (wr_entry25_sel[1] == 1'b1) ? wr_cam_data[66] : + entry25_ds_q; + assign entry25_pid_d = (wr_entry25_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry25_pid_q[0:7]; + assign entry25_cmpmask_d = (wr_entry25_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry25_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry25_parity_d[0:3] = (wr_entry25_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry25_parity_q[0:3]; + assign entry25_parity_d[4:6] = (wr_entry25_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry25_parity_q[4:6]; + assign entry25_parity_d[7] = (wr_entry25_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry25_parity_q[7]; + assign entry25_parity_d[8] = (wr_entry25_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry25_parity_q[8]; + assign entry25_parity_d[9] = (wr_entry25_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry25_parity_q[9]; + assign wr_entry26_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b11010)) ? 1'b1 : + 1'b0; + assign wr_entry26_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b11010)) ? 1'b1 : + 1'b0; + assign entry26_epn_d[0:31] = (wr_entry26_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry26_epn_q[0:31]; + assign entry26_epn_d[32:51] = (wr_entry26_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry26_epn_q[32:51]; + assign entry26_xbit_d = (wr_entry26_sel[0] == 1'b1) ? wr_cam_data[52] : + entry26_xbit_q; + assign entry26_size_d = (wr_entry26_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry26_size_q[0:2]; + assign entry26_class_d = (wr_entry26_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry26_class_q[0:1]; + assign entry26_extclass_d = (wr_entry26_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry26_extclass_q[0:1]; + assign entry26_hv_d = (wr_entry26_sel[1] == 1'b1) ? wr_cam_data[65] : + entry26_hv_q; + assign entry26_ds_d = (wr_entry26_sel[1] == 1'b1) ? wr_cam_data[66] : + entry26_ds_q; + assign entry26_pid_d = (wr_entry26_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry26_pid_q[0:7]; + assign entry26_cmpmask_d = (wr_entry26_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry26_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry26_parity_d[0:3] = (wr_entry26_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry26_parity_q[0:3]; + assign entry26_parity_d[4:6] = (wr_entry26_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry26_parity_q[4:6]; + assign entry26_parity_d[7] = (wr_entry26_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry26_parity_q[7]; + assign entry26_parity_d[8] = (wr_entry26_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry26_parity_q[8]; + assign entry26_parity_d[9] = (wr_entry26_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry26_parity_q[9]; + assign wr_entry27_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b11011)) ? 1'b1 : + 1'b0; + assign wr_entry27_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b11011)) ? 1'b1 : + 1'b0; + assign entry27_epn_d[0:31] = (wr_entry27_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry27_epn_q[0:31]; + assign entry27_epn_d[32:51] = (wr_entry27_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry27_epn_q[32:51]; + assign entry27_xbit_d = (wr_entry27_sel[0] == 1'b1) ? wr_cam_data[52] : + entry27_xbit_q; + assign entry27_size_d = (wr_entry27_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry27_size_q[0:2]; + assign entry27_class_d = (wr_entry27_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry27_class_q[0:1]; + assign entry27_extclass_d = (wr_entry27_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry27_extclass_q[0:1]; + assign entry27_hv_d = (wr_entry27_sel[1] == 1'b1) ? wr_cam_data[65] : + entry27_hv_q; + assign entry27_ds_d = (wr_entry27_sel[1] == 1'b1) ? wr_cam_data[66] : + entry27_ds_q; + assign entry27_pid_d = (wr_entry27_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry27_pid_q[0:7]; + assign entry27_cmpmask_d = (wr_entry27_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry27_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry27_parity_d[0:3] = (wr_entry27_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry27_parity_q[0:3]; + assign entry27_parity_d[4:6] = (wr_entry27_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry27_parity_q[4:6]; + assign entry27_parity_d[7] = (wr_entry27_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry27_parity_q[7]; + assign entry27_parity_d[8] = (wr_entry27_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry27_parity_q[8]; + assign entry27_parity_d[9] = (wr_entry27_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry27_parity_q[9]; + assign wr_entry28_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b11100)) ? 1'b1 : + 1'b0; + assign wr_entry28_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b11100)) ? 1'b1 : + 1'b0; + assign entry28_epn_d[0:31] = (wr_entry28_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry28_epn_q[0:31]; + assign entry28_epn_d[32:51] = (wr_entry28_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry28_epn_q[32:51]; + assign entry28_xbit_d = (wr_entry28_sel[0] == 1'b1) ? wr_cam_data[52] : + entry28_xbit_q; + assign entry28_size_d = (wr_entry28_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry28_size_q[0:2]; + assign entry28_class_d = (wr_entry28_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry28_class_q[0:1]; + assign entry28_extclass_d = (wr_entry28_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry28_extclass_q[0:1]; + assign entry28_hv_d = (wr_entry28_sel[1] == 1'b1) ? wr_cam_data[65] : + entry28_hv_q; + assign entry28_ds_d = (wr_entry28_sel[1] == 1'b1) ? wr_cam_data[66] : + entry28_ds_q; + assign entry28_pid_d = (wr_entry28_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry28_pid_q[0:7]; + assign entry28_cmpmask_d = (wr_entry28_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry28_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry28_parity_d[0:3] = (wr_entry28_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry28_parity_q[0:3]; + assign entry28_parity_d[4:6] = (wr_entry28_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry28_parity_q[4:6]; + assign entry28_parity_d[7] = (wr_entry28_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry28_parity_q[7]; + assign entry28_parity_d[8] = (wr_entry28_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry28_parity_q[8]; + assign entry28_parity_d[9] = (wr_entry28_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry28_parity_q[9]; + assign wr_entry29_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b11101)) ? 1'b1 : + 1'b0; + assign wr_entry29_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b11101)) ? 1'b1 : + 1'b0; + assign entry29_epn_d[0:31] = (wr_entry29_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry29_epn_q[0:31]; + assign entry29_epn_d[32:51] = (wr_entry29_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry29_epn_q[32:51]; + assign entry29_xbit_d = (wr_entry29_sel[0] == 1'b1) ? wr_cam_data[52] : + entry29_xbit_q; + assign entry29_size_d = (wr_entry29_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry29_size_q[0:2]; + assign entry29_class_d = (wr_entry29_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry29_class_q[0:1]; + assign entry29_extclass_d = (wr_entry29_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry29_extclass_q[0:1]; + assign entry29_hv_d = (wr_entry29_sel[1] == 1'b1) ? wr_cam_data[65] : + entry29_hv_q; + assign entry29_ds_d = (wr_entry29_sel[1] == 1'b1) ? wr_cam_data[66] : + entry29_ds_q; + assign entry29_pid_d = (wr_entry29_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry29_pid_q[0:7]; + assign entry29_cmpmask_d = (wr_entry29_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry29_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry29_parity_d[0:3] = (wr_entry29_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry29_parity_q[0:3]; + assign entry29_parity_d[4:6] = (wr_entry29_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry29_parity_q[4:6]; + assign entry29_parity_d[7] = (wr_entry29_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry29_parity_q[7]; + assign entry29_parity_d[8] = (wr_entry29_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry29_parity_q[8]; + assign entry29_parity_d[9] = (wr_entry29_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry29_parity_q[9]; + assign wr_entry30_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b11110)) ? 1'b1 : + 1'b0; + assign wr_entry30_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b11110)) ? 1'b1 : + 1'b0; + assign entry30_epn_d[0:31] = (wr_entry30_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry30_epn_q[0:31]; + assign entry30_epn_d[32:51] = (wr_entry30_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry30_epn_q[32:51]; + assign entry30_xbit_d = (wr_entry30_sel[0] == 1'b1) ? wr_cam_data[52] : + entry30_xbit_q; + assign entry30_size_d = (wr_entry30_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry30_size_q[0:2]; + assign entry30_class_d = (wr_entry30_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry30_class_q[0:1]; + assign entry30_extclass_d = (wr_entry30_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry30_extclass_q[0:1]; + assign entry30_hv_d = (wr_entry30_sel[1] == 1'b1) ? wr_cam_data[65] : + entry30_hv_q; + assign entry30_ds_d = (wr_entry30_sel[1] == 1'b1) ? wr_cam_data[66] : + entry30_ds_q; + assign entry30_pid_d = (wr_entry30_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry30_pid_q[0:7]; + assign entry30_cmpmask_d = (wr_entry30_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry30_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry30_parity_d[0:3] = (wr_entry30_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry30_parity_q[0:3]; + assign entry30_parity_d[4:6] = (wr_entry30_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry30_parity_q[4:6]; + assign entry30_parity_d[7] = (wr_entry30_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry30_parity_q[7]; + assign entry30_parity_d[8] = (wr_entry30_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry30_parity_q[8]; + assign entry30_parity_d[9] = (wr_entry30_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry30_parity_q[9]; + assign wr_entry31_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b11111)) ? 1'b1 : + 1'b0; + assign wr_entry31_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b11111)) ? 1'b1 : + 1'b0; + assign entry31_epn_d[0:31] = (wr_entry31_sel[0] == 1'b1) ? wr_cam_data[0:31] : + entry31_epn_q[0:31]; + assign entry31_epn_d[32:51] = (wr_entry31_sel[0] == 1'b1) ? wr_cam_data[32:51] : + entry31_epn_q[32:51]; + assign entry31_xbit_d = (wr_entry31_sel[0] == 1'b1) ? wr_cam_data[52] : + entry31_xbit_q; + assign entry31_size_d = (wr_entry31_sel[0] == 1'b1) ? wr_cam_data[53:55] : + entry31_size_q[0:2]; + assign entry31_class_d = (wr_entry31_sel[0] == 1'b1) ? wr_cam_data[61:62] : + entry31_class_q[0:1]; + assign entry31_extclass_d = (wr_entry31_sel[1] == 1'b1) ? wr_cam_data[63:64] : + entry31_extclass_q[0:1]; + assign entry31_hv_d = (wr_entry31_sel[1] == 1'b1) ? wr_cam_data[65] : + entry31_hv_q; + assign entry31_ds_d = (wr_entry31_sel[1] == 1'b1) ? wr_cam_data[66] : + entry31_ds_q; + assign entry31_pid_d = (wr_entry31_sel[1] == 1'b1) ? wr_cam_data[67:74] : + entry31_pid_q[0:7]; + assign entry31_cmpmask_d = (wr_entry31_sel[0] == 1'b1) ? wr_cam_data[75:83] : + entry31_cmpmask_q; + // the cam parity bits.. some wr_array_data bits contain parity for cam + assign entry31_parity_d[0:3] = (wr_entry31_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : + entry31_parity_q[0:3]; + assign entry31_parity_d[4:6] = (wr_entry31_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : + entry31_parity_q[4:6]; + assign entry31_parity_d[7] = (wr_entry31_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : + entry31_parity_q[7]; + assign entry31_parity_d[8] = (wr_entry31_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : + entry31_parity_q[8]; + assign entry31_parity_d[9] = (wr_entry31_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : + entry31_parity_q[9]; + + + // entry valid and thdid next state logic + assign entry0_inval = (comp_invalidate & match_vec[0]) | flash_invalidate; + assign entry0_v_muxsel[0:1] = ({entry0_inval, wr_entry0_sel[0]}); + assign entry0_v_d = (entry0_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry0_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry0_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry0_v_q; + assign entry0_thdid_d[0:3] = (wr_entry0_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry0_thdid_q[0:3]; + assign entry1_inval = (comp_invalidate & match_vec[1]) | flash_invalidate; + assign entry1_v_muxsel[0:1] = ({entry1_inval, wr_entry1_sel[0]}); + assign entry1_v_d = (entry1_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry1_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry1_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry1_v_q; + assign entry1_thdid_d[0:3] = (wr_entry1_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry1_thdid_q[0:3]; + assign entry2_inval = (comp_invalidate & match_vec[2]) | flash_invalidate; + assign entry2_v_muxsel[0:1] = ({entry2_inval, wr_entry2_sel[0]}); + assign entry2_v_d = (entry2_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry2_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry2_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry2_v_q; + assign entry2_thdid_d[0:3] = (wr_entry2_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry2_thdid_q[0:3]; + assign entry3_inval = (comp_invalidate & match_vec[3]) | flash_invalidate; + assign entry3_v_muxsel[0:1] = ({entry3_inval, wr_entry3_sel[0]}); + assign entry3_v_d = (entry3_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry3_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry3_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry3_v_q; + assign entry3_thdid_d[0:3] = (wr_entry3_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry3_thdid_q[0:3]; + assign entry4_inval = (comp_invalidate & match_vec[4]) | flash_invalidate; + assign entry4_v_muxsel[0:1] = ({entry4_inval, wr_entry4_sel[0]}); + assign entry4_v_d = (entry4_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry4_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry4_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry4_v_q; + assign entry4_thdid_d[0:3] = (wr_entry4_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry4_thdid_q[0:3]; + assign entry5_inval = (comp_invalidate & match_vec[5]) | flash_invalidate; + assign entry5_v_muxsel[0:1] = ({entry5_inval, wr_entry5_sel[0]}); + assign entry5_v_d = (entry5_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry5_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry5_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry5_v_q; + assign entry5_thdid_d[0:3] = (wr_entry5_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry5_thdid_q[0:3]; + assign entry6_inval = (comp_invalidate & match_vec[6]) | flash_invalidate; + assign entry6_v_muxsel[0:1] = ({entry6_inval, wr_entry6_sel[0]}); + assign entry6_v_d = (entry6_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry6_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry6_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry6_v_q; + assign entry6_thdid_d[0:3] = (wr_entry6_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry6_thdid_q[0:3]; + assign entry7_inval = (comp_invalidate & match_vec[7]) | flash_invalidate; + assign entry7_v_muxsel[0:1] = ({entry7_inval, wr_entry7_sel[0]}); + assign entry7_v_d = (entry7_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry7_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry7_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry7_v_q; + assign entry7_thdid_d[0:3] = (wr_entry7_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry7_thdid_q[0:3]; + assign entry8_inval = (comp_invalidate & match_vec[8]) | flash_invalidate; + assign entry8_v_muxsel[0:1] = ({entry8_inval, wr_entry8_sel[0]}); + assign entry8_v_d = (entry8_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry8_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry8_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry8_v_q; + assign entry8_thdid_d[0:3] = (wr_entry8_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry8_thdid_q[0:3]; + assign entry9_inval = (comp_invalidate & match_vec[9]) | flash_invalidate; + assign entry9_v_muxsel[0:1] = ({entry9_inval, wr_entry9_sel[0]}); + assign entry9_v_d = (entry9_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry9_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry9_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry9_v_q; + assign entry9_thdid_d[0:3] = (wr_entry9_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry9_thdid_q[0:3]; + assign entry10_inval = (comp_invalidate & match_vec[10]) | flash_invalidate; + assign entry10_v_muxsel[0:1] = ({entry10_inval, wr_entry10_sel[0]}); + assign entry10_v_d = (entry10_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry10_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry10_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry10_v_q; + assign entry10_thdid_d[0:3] = (wr_entry10_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry10_thdid_q[0:3]; + assign entry11_inval = (comp_invalidate & match_vec[11]) | flash_invalidate; + assign entry11_v_muxsel[0:1] = ({entry11_inval, wr_entry11_sel[0]}); + assign entry11_v_d = (entry11_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry11_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry11_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry11_v_q; + assign entry11_thdid_d[0:3] = (wr_entry11_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry11_thdid_q[0:3]; + assign entry12_inval = (comp_invalidate & match_vec[12]) | flash_invalidate; + assign entry12_v_muxsel[0:1] = ({entry12_inval, wr_entry12_sel[0]}); + assign entry12_v_d = (entry12_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry12_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry12_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry12_v_q; + assign entry12_thdid_d[0:3] = (wr_entry12_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry12_thdid_q[0:3]; + assign entry13_inval = (comp_invalidate & match_vec[13]) | flash_invalidate; + assign entry13_v_muxsel[0:1] = ({entry13_inval, wr_entry13_sel[0]}); + assign entry13_v_d = (entry13_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry13_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry13_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry13_v_q; + assign entry13_thdid_d[0:3] = (wr_entry13_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry13_thdid_q[0:3]; + assign entry14_inval = (comp_invalidate & match_vec[14]) | flash_invalidate; + assign entry14_v_muxsel[0:1] = ({entry14_inval, wr_entry14_sel[0]}); + assign entry14_v_d = (entry14_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry14_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry14_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry14_v_q; + assign entry14_thdid_d[0:3] = (wr_entry14_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry14_thdid_q[0:3]; + assign entry15_inval = (comp_invalidate & match_vec[15]) | flash_invalidate; + assign entry15_v_muxsel[0:1] = ({entry15_inval, wr_entry15_sel[0]}); + assign entry15_v_d = (entry15_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry15_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry15_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry15_v_q; + assign entry15_thdid_d[0:3] = (wr_entry15_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry15_thdid_q[0:3]; + assign entry16_inval = (comp_invalidate & match_vec[16]) | flash_invalidate; + assign entry16_v_muxsel[0:1] = ({entry16_inval, wr_entry16_sel[0]}); + assign entry16_v_d = (entry16_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry16_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry16_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry16_v_q; + assign entry16_thdid_d[0:3] = (wr_entry16_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry16_thdid_q[0:3]; + assign entry17_inval = (comp_invalidate & match_vec[17]) | flash_invalidate; + assign entry17_v_muxsel[0:1] = ({entry17_inval, wr_entry17_sel[0]}); + assign entry17_v_d = (entry17_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry17_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry17_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry17_v_q; + assign entry17_thdid_d[0:3] = (wr_entry17_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry17_thdid_q[0:3]; + assign entry18_inval = (comp_invalidate & match_vec[18]) | flash_invalidate; + assign entry18_v_muxsel[0:1] = ({entry18_inval, wr_entry18_sel[0]}); + assign entry18_v_d = (entry18_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry18_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry18_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry18_v_q; + assign entry18_thdid_d[0:3] = (wr_entry18_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry18_thdid_q[0:3]; + assign entry19_inval = (comp_invalidate & match_vec[19]) | flash_invalidate; + assign entry19_v_muxsel[0:1] = ({entry19_inval, wr_entry19_sel[0]}); + assign entry19_v_d = (entry19_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry19_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry19_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry19_v_q; + assign entry19_thdid_d[0:3] = (wr_entry19_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry19_thdid_q[0:3]; + assign entry20_inval = (comp_invalidate & match_vec[20]) | flash_invalidate; + assign entry20_v_muxsel[0:1] = ({entry20_inval, wr_entry20_sel[0]}); + assign entry20_v_d = (entry20_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry20_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry20_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry20_v_q; + assign entry20_thdid_d[0:3] = (wr_entry20_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry20_thdid_q[0:3]; + assign entry21_inval = (comp_invalidate & match_vec[21]) | flash_invalidate; + assign entry21_v_muxsel[0:1] = ({entry21_inval, wr_entry21_sel[0]}); + assign entry21_v_d = (entry21_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry21_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry21_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry21_v_q; + assign entry21_thdid_d[0:3] = (wr_entry21_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry21_thdid_q[0:3]; + assign entry22_inval = (comp_invalidate & match_vec[22]) | flash_invalidate; + assign entry22_v_muxsel[0:1] = ({entry22_inval, wr_entry22_sel[0]}); + assign entry22_v_d = (entry22_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry22_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry22_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry22_v_q; + assign entry22_thdid_d[0:3] = (wr_entry22_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry22_thdid_q[0:3]; + assign entry23_inval = (comp_invalidate & match_vec[23]) | flash_invalidate; + assign entry23_v_muxsel[0:1] = ({entry23_inval, wr_entry23_sel[0]}); + assign entry23_v_d = (entry23_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry23_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry23_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry23_v_q; + assign entry23_thdid_d[0:3] = (wr_entry23_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry23_thdid_q[0:3]; + assign entry24_inval = (comp_invalidate & match_vec[24]) | flash_invalidate; + assign entry24_v_muxsel[0:1] = ({entry24_inval, wr_entry24_sel[0]}); + assign entry24_v_d = (entry24_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry24_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry24_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry24_v_q; + assign entry24_thdid_d[0:3] = (wr_entry24_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry24_thdid_q[0:3]; + assign entry25_inval = (comp_invalidate & match_vec[25]) | flash_invalidate; + assign entry25_v_muxsel[0:1] = ({entry25_inval, wr_entry25_sel[0]}); + assign entry25_v_d = (entry25_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry25_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry25_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry25_v_q; + assign entry25_thdid_d[0:3] = (wr_entry25_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry25_thdid_q[0:3]; + assign entry26_inval = (comp_invalidate & match_vec[26]) | flash_invalidate; + assign entry26_v_muxsel[0:1] = ({entry26_inval, wr_entry26_sel[0]}); + assign entry26_v_d = (entry26_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry26_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry26_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry26_v_q; + assign entry26_thdid_d[0:3] = (wr_entry26_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry26_thdid_q[0:3]; + assign entry27_inval = (comp_invalidate & match_vec[27]) | flash_invalidate; + assign entry27_v_muxsel[0:1] = ({entry27_inval, wr_entry27_sel[0]}); + assign entry27_v_d = (entry27_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry27_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry27_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry27_v_q; + assign entry27_thdid_d[0:3] = (wr_entry27_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry27_thdid_q[0:3]; + assign entry28_inval = (comp_invalidate & match_vec[28]) | flash_invalidate; + assign entry28_v_muxsel[0:1] = ({entry28_inval, wr_entry28_sel[0]}); + assign entry28_v_d = (entry28_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry28_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry28_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry28_v_q; + assign entry28_thdid_d[0:3] = (wr_entry28_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry28_thdid_q[0:3]; + assign entry29_inval = (comp_invalidate & match_vec[29]) | flash_invalidate; + assign entry29_v_muxsel[0:1] = ({entry29_inval, wr_entry29_sel[0]}); + assign entry29_v_d = (entry29_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry29_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry29_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry29_v_q; + assign entry29_thdid_d[0:3] = (wr_entry29_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry29_thdid_q[0:3]; + assign entry30_inval = (comp_invalidate & match_vec[30]) | flash_invalidate; + assign entry30_v_muxsel[0:1] = ({entry30_inval, wr_entry30_sel[0]}); + assign entry30_v_d = (entry30_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry30_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry30_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry30_v_q; + assign entry30_thdid_d[0:3] = (wr_entry30_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry30_thdid_q[0:3]; + assign entry31_inval = (comp_invalidate & match_vec[31]) | flash_invalidate; + assign entry31_v_muxsel[0:1] = ({entry31_inval, wr_entry31_sel[0]}); + assign entry31_v_d = (entry31_v_muxsel[0:1] == 2'b10) ? 1'b0 : + (entry31_v_muxsel[0:1] == 2'b11) ? 1'b0 : + (entry31_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : + entry31_v_q; + assign entry31_thdid_d[0:3] = (wr_entry31_sel[0] == 1'b1) ? wr_cam_data[57:60] : + entry31_thdid_q[0:3]; + + + // CAM compare data out mux + assign entry0_cam_vec = {entry0_epn_q, entry0_xbit_q, entry0_size_q, entry0_v_q, entry0_thdid_q, entry0_class_q, entry0_extclass_q, entry0_hv_q, entry0_ds_q, entry0_pid_q, entry0_cmpmask_q}; + assign entry1_cam_vec = {entry1_epn_q, entry1_xbit_q, entry1_size_q, entry1_v_q, entry1_thdid_q, entry1_class_q, entry1_extclass_q, entry1_hv_q, entry1_ds_q, entry1_pid_q, entry1_cmpmask_q}; + assign entry2_cam_vec = {entry2_epn_q, entry2_xbit_q, entry2_size_q, entry2_v_q, entry2_thdid_q, entry2_class_q, entry2_extclass_q, entry2_hv_q, entry2_ds_q, entry2_pid_q, entry2_cmpmask_q}; + assign entry3_cam_vec = {entry3_epn_q, entry3_xbit_q, entry3_size_q, entry3_v_q, entry3_thdid_q, entry3_class_q, entry3_extclass_q, entry3_hv_q, entry3_ds_q, entry3_pid_q, entry3_cmpmask_q}; + assign entry4_cam_vec = {entry4_epn_q, entry4_xbit_q, entry4_size_q, entry4_v_q, entry4_thdid_q, entry4_class_q, entry4_extclass_q, entry4_hv_q, entry4_ds_q, entry4_pid_q, entry4_cmpmask_q}; + assign entry5_cam_vec = {entry5_epn_q, entry5_xbit_q, entry5_size_q, entry5_v_q, entry5_thdid_q, entry5_class_q, entry5_extclass_q, entry5_hv_q, entry5_ds_q, entry5_pid_q, entry5_cmpmask_q}; + assign entry6_cam_vec = {entry6_epn_q, entry6_xbit_q, entry6_size_q, entry6_v_q, entry6_thdid_q, entry6_class_q, entry6_extclass_q, entry6_hv_q, entry6_ds_q, entry6_pid_q, entry6_cmpmask_q}; + assign entry7_cam_vec = {entry7_epn_q, entry7_xbit_q, entry7_size_q, entry7_v_q, entry7_thdid_q, entry7_class_q, entry7_extclass_q, entry7_hv_q, entry7_ds_q, entry7_pid_q, entry7_cmpmask_q}; + assign entry8_cam_vec = {entry8_epn_q, entry8_xbit_q, entry8_size_q, entry8_v_q, entry8_thdid_q, entry8_class_q, entry8_extclass_q, entry8_hv_q, entry8_ds_q, entry8_pid_q, entry8_cmpmask_q}; + assign entry9_cam_vec = {entry9_epn_q, entry9_xbit_q, entry9_size_q, entry9_v_q, entry9_thdid_q, entry9_class_q, entry9_extclass_q, entry9_hv_q, entry9_ds_q, entry9_pid_q, entry9_cmpmask_q}; + assign entry10_cam_vec = {entry10_epn_q, entry10_xbit_q, entry10_size_q, entry10_v_q, entry10_thdid_q, entry10_class_q, entry10_extclass_q, entry10_hv_q, entry10_ds_q, entry10_pid_q, entry10_cmpmask_q}; + assign entry11_cam_vec = {entry11_epn_q, entry11_xbit_q, entry11_size_q, entry11_v_q, entry11_thdid_q, entry11_class_q, entry11_extclass_q, entry11_hv_q, entry11_ds_q, entry11_pid_q, entry11_cmpmask_q}; + assign entry12_cam_vec = {entry12_epn_q, entry12_xbit_q, entry12_size_q, entry12_v_q, entry12_thdid_q, entry12_class_q, entry12_extclass_q, entry12_hv_q, entry12_ds_q, entry12_pid_q, entry12_cmpmask_q}; + assign entry13_cam_vec = {entry13_epn_q, entry13_xbit_q, entry13_size_q, entry13_v_q, entry13_thdid_q, entry13_class_q, entry13_extclass_q, entry13_hv_q, entry13_ds_q, entry13_pid_q, entry13_cmpmask_q}; + assign entry14_cam_vec = {entry14_epn_q, entry14_xbit_q, entry14_size_q, entry14_v_q, entry14_thdid_q, entry14_class_q, entry14_extclass_q, entry14_hv_q, entry14_ds_q, entry14_pid_q, entry14_cmpmask_q}; + assign entry15_cam_vec = {entry15_epn_q, entry15_xbit_q, entry15_size_q, entry15_v_q, entry15_thdid_q, entry15_class_q, entry15_extclass_q, entry15_hv_q, entry15_ds_q, entry15_pid_q, entry15_cmpmask_q}; + assign entry16_cam_vec = {entry16_epn_q, entry16_xbit_q, entry16_size_q, entry16_v_q, entry16_thdid_q, entry16_class_q, entry16_extclass_q, entry16_hv_q, entry16_ds_q, entry16_pid_q, entry16_cmpmask_q}; + assign entry17_cam_vec = {entry17_epn_q, entry17_xbit_q, entry17_size_q, entry17_v_q, entry17_thdid_q, entry17_class_q, entry17_extclass_q, entry17_hv_q, entry17_ds_q, entry17_pid_q, entry17_cmpmask_q}; + assign entry18_cam_vec = {entry18_epn_q, entry18_xbit_q, entry18_size_q, entry18_v_q, entry18_thdid_q, entry18_class_q, entry18_extclass_q, entry18_hv_q, entry18_ds_q, entry18_pid_q, entry18_cmpmask_q}; + assign entry19_cam_vec = {entry19_epn_q, entry19_xbit_q, entry19_size_q, entry19_v_q, entry19_thdid_q, entry19_class_q, entry19_extclass_q, entry19_hv_q, entry19_ds_q, entry19_pid_q, entry19_cmpmask_q}; + assign entry20_cam_vec = {entry20_epn_q, entry20_xbit_q, entry20_size_q, entry20_v_q, entry20_thdid_q, entry20_class_q, entry20_extclass_q, entry20_hv_q, entry20_ds_q, entry20_pid_q, entry20_cmpmask_q}; + assign entry21_cam_vec = {entry21_epn_q, entry21_xbit_q, entry21_size_q, entry21_v_q, entry21_thdid_q, entry21_class_q, entry21_extclass_q, entry21_hv_q, entry21_ds_q, entry21_pid_q, entry21_cmpmask_q}; + assign entry22_cam_vec = {entry22_epn_q, entry22_xbit_q, entry22_size_q, entry22_v_q, entry22_thdid_q, entry22_class_q, entry22_extclass_q, entry22_hv_q, entry22_ds_q, entry22_pid_q, entry22_cmpmask_q}; + assign entry23_cam_vec = {entry23_epn_q, entry23_xbit_q, entry23_size_q, entry23_v_q, entry23_thdid_q, entry23_class_q, entry23_extclass_q, entry23_hv_q, entry23_ds_q, entry23_pid_q, entry23_cmpmask_q}; + assign entry24_cam_vec = {entry24_epn_q, entry24_xbit_q, entry24_size_q, entry24_v_q, entry24_thdid_q, entry24_class_q, entry24_extclass_q, entry24_hv_q, entry24_ds_q, entry24_pid_q, entry24_cmpmask_q}; + assign entry25_cam_vec = {entry25_epn_q, entry25_xbit_q, entry25_size_q, entry25_v_q, entry25_thdid_q, entry25_class_q, entry25_extclass_q, entry25_hv_q, entry25_ds_q, entry25_pid_q, entry25_cmpmask_q}; + assign entry26_cam_vec = {entry26_epn_q, entry26_xbit_q, entry26_size_q, entry26_v_q, entry26_thdid_q, entry26_class_q, entry26_extclass_q, entry26_hv_q, entry26_ds_q, entry26_pid_q, entry26_cmpmask_q}; + assign entry27_cam_vec = {entry27_epn_q, entry27_xbit_q, entry27_size_q, entry27_v_q, entry27_thdid_q, entry27_class_q, entry27_extclass_q, entry27_hv_q, entry27_ds_q, entry27_pid_q, entry27_cmpmask_q}; + assign entry28_cam_vec = {entry28_epn_q, entry28_xbit_q, entry28_size_q, entry28_v_q, entry28_thdid_q, entry28_class_q, entry28_extclass_q, entry28_hv_q, entry28_ds_q, entry28_pid_q, entry28_cmpmask_q}; + assign entry29_cam_vec = {entry29_epn_q, entry29_xbit_q, entry29_size_q, entry29_v_q, entry29_thdid_q, entry29_class_q, entry29_extclass_q, entry29_hv_q, entry29_ds_q, entry29_pid_q, entry29_cmpmask_q}; + assign entry30_cam_vec = {entry30_epn_q, entry30_xbit_q, entry30_size_q, entry30_v_q, entry30_thdid_q, entry30_class_q, entry30_extclass_q, entry30_hv_q, entry30_ds_q, entry30_pid_q, entry30_cmpmask_q}; + assign entry31_cam_vec = {entry31_epn_q, entry31_xbit_q, entry31_size_q, entry31_v_q, entry31_thdid_q, entry31_class_q, entry31_extclass_q, entry31_hv_q, entry31_ds_q, entry31_pid_q, entry31_cmpmask_q}; + + + assign cam_cmp_data_muxsel = {(~(comp_request)), cam_hit_entry_d}; + assign cam_cmp_data_d = (cam_cmp_data_muxsel == 6'b000000) ? entry0_cam_vec : + (cam_cmp_data_muxsel == 6'b000001) ? entry1_cam_vec : + (cam_cmp_data_muxsel == 6'b000010) ? entry2_cam_vec : + (cam_cmp_data_muxsel == 6'b000011) ? entry3_cam_vec : + (cam_cmp_data_muxsel == 6'b000100) ? entry4_cam_vec : + (cam_cmp_data_muxsel == 6'b000101) ? entry5_cam_vec : + (cam_cmp_data_muxsel == 6'b000110) ? entry6_cam_vec : + (cam_cmp_data_muxsel == 6'b000111) ? entry7_cam_vec : + (cam_cmp_data_muxsel == 6'b001000) ? entry8_cam_vec : + (cam_cmp_data_muxsel == 6'b001001) ? entry9_cam_vec : + (cam_cmp_data_muxsel == 6'b001010) ? entry10_cam_vec : + (cam_cmp_data_muxsel == 6'b001011) ? entry11_cam_vec : + (cam_cmp_data_muxsel == 6'b001100) ? entry12_cam_vec : + (cam_cmp_data_muxsel == 6'b001101) ? entry13_cam_vec : + (cam_cmp_data_muxsel == 6'b001110) ? entry14_cam_vec : + (cam_cmp_data_muxsel == 6'b001111) ? entry15_cam_vec : + (cam_cmp_data_muxsel == 6'b010000) ? entry16_cam_vec : + (cam_cmp_data_muxsel == 6'b010001) ? entry17_cam_vec : + (cam_cmp_data_muxsel == 6'b010010) ? entry18_cam_vec : + (cam_cmp_data_muxsel == 6'b010011) ? entry19_cam_vec : + (cam_cmp_data_muxsel == 6'b010100) ? entry20_cam_vec : + (cam_cmp_data_muxsel == 6'b010101) ? entry21_cam_vec : + (cam_cmp_data_muxsel == 6'b010110) ? entry22_cam_vec : + (cam_cmp_data_muxsel == 6'b010111) ? entry23_cam_vec : + (cam_cmp_data_muxsel == 6'b011000) ? entry24_cam_vec : + (cam_cmp_data_muxsel == 6'b011001) ? entry25_cam_vec : + (cam_cmp_data_muxsel == 6'b011010) ? entry26_cam_vec : + (cam_cmp_data_muxsel == 6'b011011) ? entry27_cam_vec : + (cam_cmp_data_muxsel == 6'b011100) ? entry28_cam_vec : + (cam_cmp_data_muxsel == 6'b011101) ? entry29_cam_vec : + (cam_cmp_data_muxsel == 6'b011110) ? entry30_cam_vec : + (cam_cmp_data_muxsel == 6'b011111) ? entry31_cam_vec : + cam_cmp_data_q; + + assign cam_cmp_data_np1 = cam_cmp_data_q; + + // CAM read data out mux + assign rd_cam_data_muxsel = {(~(rd_val)), rw_entry}; + + assign rd_cam_data_d = (rd_cam_data_muxsel == 6'b000000) ? entry0_cam_vec : + (rd_cam_data_muxsel == 6'b000001) ? entry1_cam_vec : + (rd_cam_data_muxsel == 6'b000010) ? entry2_cam_vec : + (rd_cam_data_muxsel == 6'b000011) ? entry3_cam_vec : + (rd_cam_data_muxsel == 6'b000100) ? entry4_cam_vec : + (rd_cam_data_muxsel == 6'b000101) ? entry5_cam_vec : + (rd_cam_data_muxsel == 6'b000110) ? entry6_cam_vec : + (rd_cam_data_muxsel == 6'b000111) ? entry7_cam_vec : + (rd_cam_data_muxsel == 6'b001000) ? entry8_cam_vec : + (rd_cam_data_muxsel == 6'b001001) ? entry9_cam_vec : + (rd_cam_data_muxsel == 6'b001010) ? entry10_cam_vec : + (rd_cam_data_muxsel == 6'b001011) ? entry11_cam_vec : + (rd_cam_data_muxsel == 6'b001100) ? entry12_cam_vec : + (rd_cam_data_muxsel == 6'b001101) ? entry13_cam_vec : + (rd_cam_data_muxsel == 6'b001110) ? entry14_cam_vec : + (rd_cam_data_muxsel == 6'b001111) ? entry15_cam_vec : + (rd_cam_data_muxsel == 6'b010000) ? entry16_cam_vec : + (rd_cam_data_muxsel == 6'b010001) ? entry17_cam_vec : + (rd_cam_data_muxsel == 6'b010010) ? entry18_cam_vec : + (rd_cam_data_muxsel == 6'b010011) ? entry19_cam_vec : + (rd_cam_data_muxsel == 6'b010100) ? entry20_cam_vec : + (rd_cam_data_muxsel == 6'b010101) ? entry21_cam_vec : + (rd_cam_data_muxsel == 6'b010110) ? entry22_cam_vec : + (rd_cam_data_muxsel == 6'b010111) ? entry23_cam_vec : + (rd_cam_data_muxsel == 6'b011000) ? entry24_cam_vec : + (rd_cam_data_muxsel == 6'b011001) ? entry25_cam_vec : + (rd_cam_data_muxsel == 6'b011010) ? entry26_cam_vec : + (rd_cam_data_muxsel == 6'b011011) ? entry27_cam_vec : + (rd_cam_data_muxsel == 6'b011100) ? entry28_cam_vec : + (rd_cam_data_muxsel == 6'b011101) ? entry29_cam_vec : + (rd_cam_data_muxsel == 6'b011110) ? entry30_cam_vec : + (rd_cam_data_muxsel == 6'b011111) ? entry31_cam_vec : + rd_cam_data_q; + + // CAM compare parity out mux + assign cam_cmp_parity_d = (cam_cmp_data_muxsel == 6'b000000) ? entry0_parity_q : + (cam_cmp_data_muxsel == 6'b000001) ? entry1_parity_q : + (cam_cmp_data_muxsel == 6'b000010) ? entry2_parity_q : + (cam_cmp_data_muxsel == 6'b000011) ? entry3_parity_q : + (cam_cmp_data_muxsel == 6'b000100) ? entry4_parity_q : + (cam_cmp_data_muxsel == 6'b000101) ? entry5_parity_q : + (cam_cmp_data_muxsel == 6'b000110) ? entry6_parity_q : + (cam_cmp_data_muxsel == 6'b000111) ? entry7_parity_q : + (cam_cmp_data_muxsel == 6'b001000) ? entry8_parity_q : + (cam_cmp_data_muxsel == 6'b001001) ? entry9_parity_q : + (cam_cmp_data_muxsel == 6'b001010) ? entry10_parity_q : + (cam_cmp_data_muxsel == 6'b001011) ? entry11_parity_q : + (cam_cmp_data_muxsel == 6'b001100) ? entry12_parity_q : + (cam_cmp_data_muxsel == 6'b001101) ? entry13_parity_q : + (cam_cmp_data_muxsel == 6'b001110) ? entry14_parity_q : + (cam_cmp_data_muxsel == 6'b001111) ? entry15_parity_q : + (cam_cmp_data_muxsel == 6'b010000) ? entry16_parity_q : + (cam_cmp_data_muxsel == 6'b010001) ? entry17_parity_q : + (cam_cmp_data_muxsel == 6'b010010) ? entry18_parity_q : + (cam_cmp_data_muxsel == 6'b010011) ? entry19_parity_q : + (cam_cmp_data_muxsel == 6'b010100) ? entry20_parity_q : + (cam_cmp_data_muxsel == 6'b010101) ? entry21_parity_q : + (cam_cmp_data_muxsel == 6'b010110) ? entry22_parity_q : + (cam_cmp_data_muxsel == 6'b010111) ? entry23_parity_q : + (cam_cmp_data_muxsel == 6'b011000) ? entry24_parity_q : + (cam_cmp_data_muxsel == 6'b011001) ? entry25_parity_q : + (cam_cmp_data_muxsel == 6'b011010) ? entry26_parity_q : + (cam_cmp_data_muxsel == 6'b011011) ? entry27_parity_q : + (cam_cmp_data_muxsel == 6'b011100) ? entry28_parity_q : + (cam_cmp_data_muxsel == 6'b011101) ? entry29_parity_q : + (cam_cmp_data_muxsel == 6'b011110) ? entry30_parity_q : + (cam_cmp_data_muxsel == 6'b011111) ? entry31_parity_q : + cam_cmp_parity_q; + + assign array_cmp_data_np1[0:50] = {array_cmp_data_bram[2:31], array_cmp_data_bram[34:39], array_cmp_data_bram[41:55]}; + assign array_cmp_data_np1[51:60] = cam_cmp_parity_q; + assign array_cmp_data_np1[61:67] = array_cmp_data_bramp[66:72]; + + assign array_cmp_data = array_cmp_data_np1; + + // CAM read parity out mux + assign rd_array_data_d[51:60] = (rd_cam_data_muxsel == 6'b000000) ? entry0_parity_q : + (rd_cam_data_muxsel == 6'b000001) ? entry1_parity_q : + (rd_cam_data_muxsel == 6'b000010) ? entry2_parity_q : + (rd_cam_data_muxsel == 6'b000011) ? entry3_parity_q : + (rd_cam_data_muxsel == 6'b000100) ? entry4_parity_q : + (rd_cam_data_muxsel == 6'b000101) ? entry5_parity_q : + (rd_cam_data_muxsel == 6'b000110) ? entry6_parity_q : + (rd_cam_data_muxsel == 6'b000111) ? entry7_parity_q : + (rd_cam_data_muxsel == 6'b001000) ? entry8_parity_q : + (rd_cam_data_muxsel == 6'b001001) ? entry9_parity_q : + (rd_cam_data_muxsel == 6'b001010) ? entry10_parity_q : + (rd_cam_data_muxsel == 6'b001011) ? entry11_parity_q : + (rd_cam_data_muxsel == 6'b001100) ? entry12_parity_q : + (rd_cam_data_muxsel == 6'b001101) ? entry13_parity_q : + (rd_cam_data_muxsel == 6'b001110) ? entry14_parity_q : + (rd_cam_data_muxsel == 6'b001111) ? entry15_parity_q : + (rd_cam_data_muxsel == 6'b010000) ? entry16_parity_q : + (rd_cam_data_muxsel == 6'b010001) ? entry17_parity_q : + (rd_cam_data_muxsel == 6'b010010) ? entry18_parity_q : + (rd_cam_data_muxsel == 6'b010011) ? entry19_parity_q : + (rd_cam_data_muxsel == 6'b010100) ? entry20_parity_q : + (rd_cam_data_muxsel == 6'b010101) ? entry21_parity_q : + (rd_cam_data_muxsel == 6'b010110) ? entry22_parity_q : + (rd_cam_data_muxsel == 6'b010111) ? entry23_parity_q : + (rd_cam_data_muxsel == 6'b011000) ? entry24_parity_q : + (rd_cam_data_muxsel == 6'b011001) ? entry25_parity_q : + (rd_cam_data_muxsel == 6'b011010) ? entry26_parity_q : + (rd_cam_data_muxsel == 6'b011011) ? entry27_parity_q : + (rd_cam_data_muxsel == 6'b011100) ? entry28_parity_q : + (rd_cam_data_muxsel == 6'b011101) ? entry29_parity_q : + (rd_cam_data_muxsel == 6'b011110) ? entry30_parity_q : + (rd_cam_data_muxsel == 6'b011111) ? entry31_parity_q : + rd_array_data_q[51:60]; + + // internal bypass latch input for rpn + // using cam_cmp_data(75:78) cmpmask bits for mux selects + assign rpn_np2_d[22:33] = (comp_addr_np1_q[22:33] & {12{bypass_mux_enab_np1}}) | + (array_cmp_data_np1[0:11] & {12{~(bypass_mux_enab_np1)}}); // real page from cam-array + + //CAM_PgSize_1GB + assign rpn_np2_d[34:39] = (comp_addr_np1_q[34:39] & {6{(~(cam_cmp_data_np1[75])) | bypass_mux_enab_np1}}) | + (array_cmp_data_np1[12:17] & {6{cam_cmp_data_np1[75] & (~bypass_mux_enab_np1)}}); + + //CAM_PgSize_1GB or CAM_PgSize_16MB + assign rpn_np2_d[40:43] = (comp_addr_np1_q[40:43] & {4{(~(cam_cmp_data_np1[76])) | bypass_mux_enab_np1}}) | + (array_cmp_data_np1[18:21] & {4{cam_cmp_data_np1[76] & (~bypass_mux_enab_np1)}}); + + //CAM_PgSize_1GB or CAM_PgSize_16MB or CAM_PgSize_1MB + assign rpn_np2_d[44:47] = (comp_addr_np1_q[44:47] & {4{(~(cam_cmp_data_np1[77])) | bypass_mux_enab_np1}}) | + (array_cmp_data_np1[22:25] & {4{cam_cmp_data_np1[77] & (~bypass_mux_enab_np1)}}); + + //CAM_PgSize_Larger_than_4K + assign rpn_np2_d[48:51] = (comp_addr_np1_q[48:51] & {4{(~(cam_cmp_data_np1[78])) | bypass_mux_enab_np1}}) | + (array_cmp_data_np1[26:29] & {4{cam_cmp_data_np1[78] & (~bypass_mux_enab_np1)}}); + + // internal bypass latch input for attributes + assign attr_np2_d[0:20] = (bypass_attr_np1[0:20] & {21{bypass_mux_enab_np1}}) | + (array_cmp_data_np1[30:50] & {21{~bypass_mux_enab_np1}}); + + // new port output assignments + assign rpn_np2[22:51] = rpn_np2_q[22:51]; + assign attr_np2[0:20] = attr_np2_q[0:20]; + + //--------------------------------------------------------------------- + // matchline component instantiations + //--------------------------------------------------------------------- + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb0( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry0_size_q), + .entry_cmpmask(entry0_cmpmask_q[0:3]), + .entry_xbit(entry0_xbit_q), + .entry_xbitmask(entry0_cmpmask_q[4:7]), + .entry_epn(entry0_epn_q), + .comp_class(comp_class), + .entry_class(entry0_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry0_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry0_hv_q), + .entry_ds(entry0_ds_q), + .state_enable(state_enable), + .entry_thdid(entry0_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry0_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry0_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[0]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb1( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry1_size_q), + .entry_cmpmask(entry1_cmpmask_q[0:3]), + .entry_xbit(entry1_xbit_q), + .entry_xbitmask(entry1_cmpmask_q[4:7]), + .entry_epn(entry1_epn_q), + .comp_class(comp_class), + .entry_class(entry1_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry1_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry1_hv_q), + .entry_ds(entry1_ds_q), + .state_enable(state_enable), + .entry_thdid(entry1_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry1_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry1_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[1]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb2( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry2_size_q), + .entry_cmpmask(entry2_cmpmask_q[0:3]), + .entry_xbit(entry2_xbit_q), + .entry_xbitmask(entry2_cmpmask_q[4:7]), + .entry_epn(entry2_epn_q), + .comp_class(comp_class), + .entry_class(entry2_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry2_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry2_hv_q), + .entry_ds(entry2_ds_q), + .state_enable(state_enable), + .entry_thdid(entry2_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry2_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry2_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[2]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb3( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry3_size_q), + .entry_cmpmask(entry3_cmpmask_q[0:3]), + .entry_xbit(entry3_xbit_q), + .entry_xbitmask(entry3_cmpmask_q[4:7]), + .entry_epn(entry3_epn_q), + .comp_class(comp_class), + .entry_class(entry3_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry3_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry3_hv_q), + .entry_ds(entry3_ds_q), + .state_enable(state_enable), + .entry_thdid(entry3_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry3_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry3_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[3]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb4( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry4_size_q), + .entry_cmpmask(entry4_cmpmask_q[0:3]), + .entry_xbit(entry4_xbit_q), + .entry_xbitmask(entry4_cmpmask_q[4:7]), + .entry_epn(entry4_epn_q), + .comp_class(comp_class), + .entry_class(entry4_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry4_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry4_hv_q), + .entry_ds(entry4_ds_q), + .state_enable(state_enable), + .entry_thdid(entry4_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry4_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry4_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[4]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb5( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry5_size_q), + .entry_cmpmask(entry5_cmpmask_q[0:3]), + .entry_xbit(entry5_xbit_q), + .entry_xbitmask(entry5_cmpmask_q[4:7]), + .entry_epn(entry5_epn_q), + .comp_class(comp_class), + .entry_class(entry5_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry5_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry5_hv_q), + .entry_ds(entry5_ds_q), + .state_enable(state_enable), + .entry_thdid(entry5_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry5_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry5_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[5]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb6( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry6_size_q), + .entry_cmpmask(entry6_cmpmask_q[0:3]), + .entry_xbit(entry6_xbit_q), + .entry_xbitmask(entry6_cmpmask_q[4:7]), + .entry_epn(entry6_epn_q), + .comp_class(comp_class), + .entry_class(entry6_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry6_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry6_hv_q), + .entry_ds(entry6_ds_q), + .state_enable(state_enable), + .entry_thdid(entry6_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry6_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry6_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[6]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb7( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry7_size_q), + .entry_cmpmask(entry7_cmpmask_q[0:3]), + .entry_xbit(entry7_xbit_q), + .entry_xbitmask(entry7_cmpmask_q[4:7]), + .entry_epn(entry7_epn_q), + .comp_class(comp_class), + .entry_class(entry7_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry7_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry7_hv_q), + .entry_ds(entry7_ds_q), + .state_enable(state_enable), + .entry_thdid(entry7_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry7_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry7_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[7]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb8( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry8_size_q), + .entry_cmpmask(entry8_cmpmask_q[0:3]), + .entry_xbit(entry8_xbit_q), + .entry_xbitmask(entry8_cmpmask_q[4:7]), + .entry_epn(entry8_epn_q), + .comp_class(comp_class), + .entry_class(entry8_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry8_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry8_hv_q), + .entry_ds(entry8_ds_q), + .state_enable(state_enable), + .entry_thdid(entry8_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry8_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry8_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[8]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb9( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry9_size_q), + .entry_cmpmask(entry9_cmpmask_q[0:3]), + .entry_xbit(entry9_xbit_q), + .entry_xbitmask(entry9_cmpmask_q[4:7]), + .entry_epn(entry9_epn_q), + .comp_class(comp_class), + .entry_class(entry9_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry9_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry9_hv_q), + .entry_ds(entry9_ds_q), + .state_enable(state_enable), + .entry_thdid(entry9_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry9_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry9_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[9]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb10( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry10_size_q), + .entry_cmpmask(entry10_cmpmask_q[0:3]), + .entry_xbit(entry10_xbit_q), + .entry_xbitmask(entry10_cmpmask_q[4:7]), + .entry_epn(entry10_epn_q), + .comp_class(comp_class), + .entry_class(entry10_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry10_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry10_hv_q), + .entry_ds(entry10_ds_q), + .state_enable(state_enable), + .entry_thdid(entry10_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry10_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry10_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[10]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb11( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry11_size_q), + .entry_cmpmask(entry11_cmpmask_q[0:3]), + .entry_xbit(entry11_xbit_q), + .entry_xbitmask(entry11_cmpmask_q[4:7]), + .entry_epn(entry11_epn_q), + .comp_class(comp_class), + .entry_class(entry11_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry11_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry11_hv_q), + .entry_ds(entry11_ds_q), + .state_enable(state_enable), + .entry_thdid(entry11_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry11_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry11_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[11]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb12( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry12_size_q), + .entry_cmpmask(entry12_cmpmask_q[0:3]), + .entry_xbit(entry12_xbit_q), + .entry_xbitmask(entry12_cmpmask_q[4:7]), + .entry_epn(entry12_epn_q), + .comp_class(comp_class), + .entry_class(entry12_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry12_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry12_hv_q), + .entry_ds(entry12_ds_q), + .state_enable(state_enable), + .entry_thdid(entry12_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry12_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry12_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[12]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb13( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry13_size_q), + .entry_cmpmask(entry13_cmpmask_q[0:3]), + .entry_xbit(entry13_xbit_q), + .entry_xbitmask(entry13_cmpmask_q[4:7]), + .entry_epn(entry13_epn_q), + .comp_class(comp_class), + .entry_class(entry13_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry13_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry13_hv_q), + .entry_ds(entry13_ds_q), + .state_enable(state_enable), + .entry_thdid(entry13_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry13_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry13_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[13]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb14( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry14_size_q), + .entry_cmpmask(entry14_cmpmask_q[0:3]), + .entry_xbit(entry14_xbit_q), + .entry_xbitmask(entry14_cmpmask_q[4:7]), + .entry_epn(entry14_epn_q), + .comp_class(comp_class), + .entry_class(entry14_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry14_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry14_hv_q), + .entry_ds(entry14_ds_q), + .state_enable(state_enable), + .entry_thdid(entry14_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry14_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry14_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[14]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb15( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry15_size_q), + .entry_cmpmask(entry15_cmpmask_q[0:3]), + .entry_xbit(entry15_xbit_q), + .entry_xbitmask(entry15_cmpmask_q[4:7]), + .entry_epn(entry15_epn_q), + .comp_class(comp_class), + .entry_class(entry15_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry15_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry15_hv_q), + .entry_ds(entry15_ds_q), + .state_enable(state_enable), + .entry_thdid(entry15_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry15_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry15_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[15]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb16( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry16_size_q), + .entry_cmpmask(entry16_cmpmask_q[0:3]), + .entry_xbit(entry16_xbit_q), + .entry_xbitmask(entry16_cmpmask_q[4:7]), + .entry_epn(entry16_epn_q), + .comp_class(comp_class), + .entry_class(entry16_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry16_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry16_hv_q), + .entry_ds(entry16_ds_q), + .state_enable(state_enable), + .entry_thdid(entry16_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry16_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry16_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[16]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb17( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry17_size_q), + .entry_cmpmask(entry17_cmpmask_q[0:3]), + .entry_xbit(entry17_xbit_q), + .entry_xbitmask(entry17_cmpmask_q[4:7]), + .entry_epn(entry17_epn_q), + .comp_class(comp_class), + .entry_class(entry17_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry17_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry17_hv_q), + .entry_ds(entry17_ds_q), + .state_enable(state_enable), + .entry_thdid(entry17_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry17_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry17_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[17]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb18( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry18_size_q), + .entry_cmpmask(entry18_cmpmask_q[0:3]), + .entry_xbit(entry18_xbit_q), + .entry_xbitmask(entry18_cmpmask_q[4:7]), + .entry_epn(entry18_epn_q), + .comp_class(comp_class), + .entry_class(entry18_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry18_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry18_hv_q), + .entry_ds(entry18_ds_q), + .state_enable(state_enable), + .entry_thdid(entry18_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry18_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry18_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[18]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb19( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry19_size_q), + .entry_cmpmask(entry19_cmpmask_q[0:3]), + .entry_xbit(entry19_xbit_q), + .entry_xbitmask(entry19_cmpmask_q[4:7]), + .entry_epn(entry19_epn_q), + .comp_class(comp_class), + .entry_class(entry19_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry19_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry19_hv_q), + .entry_ds(entry19_ds_q), + .state_enable(state_enable), + .entry_thdid(entry19_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry19_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry19_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[19]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb20( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry20_size_q), + .entry_cmpmask(entry20_cmpmask_q[0:3]), + .entry_xbit(entry20_xbit_q), + .entry_xbitmask(entry20_cmpmask_q[4:7]), + .entry_epn(entry20_epn_q), + .comp_class(comp_class), + .entry_class(entry20_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry20_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry20_hv_q), + .entry_ds(entry20_ds_q), + .state_enable(state_enable), + .entry_thdid(entry20_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry20_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry20_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[20]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb21( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry21_size_q), + .entry_cmpmask(entry21_cmpmask_q[0:3]), + .entry_xbit(entry21_xbit_q), + .entry_xbitmask(entry21_cmpmask_q[4:7]), + .entry_epn(entry21_epn_q), + .comp_class(comp_class), + .entry_class(entry21_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry21_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry21_hv_q), + .entry_ds(entry21_ds_q), + .state_enable(state_enable), + .entry_thdid(entry21_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry21_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry21_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[21]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb22( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry22_size_q), + .entry_cmpmask(entry22_cmpmask_q[0:3]), + .entry_xbit(entry22_xbit_q), + .entry_xbitmask(entry22_cmpmask_q[4:7]), + .entry_epn(entry22_epn_q), + .comp_class(comp_class), + .entry_class(entry22_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry22_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry22_hv_q), + .entry_ds(entry22_ds_q), + .state_enable(state_enable), + .entry_thdid(entry22_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry22_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry22_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[22]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb23( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry23_size_q), + .entry_cmpmask(entry23_cmpmask_q[0:3]), + .entry_xbit(entry23_xbit_q), + .entry_xbitmask(entry23_cmpmask_q[4:7]), + .entry_epn(entry23_epn_q), + .comp_class(comp_class), + .entry_class(entry23_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry23_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry23_hv_q), + .entry_ds(entry23_ds_q), + .state_enable(state_enable), + .entry_thdid(entry23_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry23_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry23_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[23]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb24( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry24_size_q), + .entry_cmpmask(entry24_cmpmask_q[0:3]), + .entry_xbit(entry24_xbit_q), + .entry_xbitmask(entry24_cmpmask_q[4:7]), + .entry_epn(entry24_epn_q), + .comp_class(comp_class), + .entry_class(entry24_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry24_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry24_hv_q), + .entry_ds(entry24_ds_q), + .state_enable(state_enable), + .entry_thdid(entry24_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry24_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry24_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[24]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb25( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry25_size_q), + .entry_cmpmask(entry25_cmpmask_q[0:3]), + .entry_xbit(entry25_xbit_q), + .entry_xbitmask(entry25_cmpmask_q[4:7]), + .entry_epn(entry25_epn_q), + .comp_class(comp_class), + .entry_class(entry25_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry25_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry25_hv_q), + .entry_ds(entry25_ds_q), + .state_enable(state_enable), + .entry_thdid(entry25_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry25_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry25_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[25]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb26( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry26_size_q), + .entry_cmpmask(entry26_cmpmask_q[0:3]), + .entry_xbit(entry26_xbit_q), + .entry_xbitmask(entry26_cmpmask_q[4:7]), + .entry_epn(entry26_epn_q), + .comp_class(comp_class), + .entry_class(entry26_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry26_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry26_hv_q), + .entry_ds(entry26_ds_q), + .state_enable(state_enable), + .entry_thdid(entry26_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry26_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry26_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[26]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb27( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry27_size_q), + .entry_cmpmask(entry27_cmpmask_q[0:3]), + .entry_xbit(entry27_xbit_q), + .entry_xbitmask(entry27_cmpmask_q[4:7]), + .entry_epn(entry27_epn_q), + .comp_class(comp_class), + .entry_class(entry27_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry27_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry27_hv_q), + .entry_ds(entry27_ds_q), + .state_enable(state_enable), + .entry_thdid(entry27_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry27_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry27_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[27]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb28( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry28_size_q), + .entry_cmpmask(entry28_cmpmask_q[0:3]), + .entry_xbit(entry28_xbit_q), + .entry_xbitmask(entry28_cmpmask_q[4:7]), + .entry_epn(entry28_epn_q), + .comp_class(comp_class), + .entry_class(entry28_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry28_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry28_hv_q), + .entry_ds(entry28_ds_q), + .state_enable(state_enable), + .entry_thdid(entry28_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry28_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry28_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[28]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb29( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry29_size_q), + .entry_cmpmask(entry29_cmpmask_q[0:3]), + .entry_xbit(entry29_xbit_q), + .entry_xbitmask(entry29_cmpmask_q[4:7]), + .entry_epn(entry29_epn_q), + .comp_class(comp_class), + .entry_class(entry29_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry29_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry29_hv_q), + .entry_ds(entry29_ds_q), + .state_enable(state_enable), + .entry_thdid(entry29_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry29_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry29_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[29]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb30( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry30_size_q), + .entry_cmpmask(entry30_cmpmask_q[0:3]), + .entry_xbit(entry30_xbit_q), + .entry_xbitmask(entry30_cmpmask_q[4:7]), + .entry_epn(entry30_epn_q), + .comp_class(comp_class), + .entry_class(entry30_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry30_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry30_hv_q), + .entry_ds(entry30_ds_q), + .state_enable(state_enable), + .entry_thdid(entry30_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry30_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry30_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[30]) + ); + + tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb31( + .addr_in(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .entry_size(entry31_size_q), + .entry_cmpmask(entry31_cmpmask_q[0:3]), + .entry_xbit(entry31_xbit_q), + .entry_xbitmask(entry31_cmpmask_q[4:7]), + .entry_epn(entry31_epn_q), + .comp_class(comp_class), + .entry_class(entry31_class_q), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(entry31_extclass_q), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .entry_hv(entry31_hv_q), + .entry_ds(entry31_ds_q), + .state_enable(state_enable), + .entry_thdid(entry31_thdid_q), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .entry_pid(entry31_pid_q), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .entry_v(entry31_v_q), + .comp_invalidate(comp_invalidate), + + .match(match_vec[31]) + ); + + + //--------------------------------------------------------------------- + // BRAM signal assignments + //--------------------------------------------------------------------- + assign bram0_wea = wr_array_val[0] & gate_fq; + assign bram1_wea = wr_array_val[1] & gate_fq; + assign bram2_wea = wr_array_val[1] & gate_fq; + + assign bram0_addra[9 - NUM_ENTRY_LOG2:8] = rw_entry[0:NUM_ENTRY_LOG2 - 1]; + assign bram1_addra[11 - NUM_ENTRY_LOG2:10] = rw_entry[0:NUM_ENTRY_LOG2 - 1]; + assign bram2_addra[10 - NUM_ENTRY_LOG2:9] = rw_entry[0:NUM_ENTRY_LOG2 - 1]; + + assign bram0_addrb[9 - NUM_ENTRY_LOG2:8] = cam_hit_entry_q; + assign bram1_addrb[11 - NUM_ENTRY_LOG2:10] = cam_hit_entry_q; + assign bram2_addrb[10 - NUM_ENTRY_LOG2:9] = cam_hit_entry_q; + + // Unused Address Bits + assign bram0_addra[0:8 - NUM_ENTRY_LOG2] = {9-NUM_ENTRY_LOG2{1'b0}}; + assign bram0_addrb[0:8 - NUM_ENTRY_LOG2] = {9-NUM_ENTRY_LOG2{1'b0}}; + assign bram1_addra[0:10 - NUM_ENTRY_LOG2] = {11-NUM_ENTRY_LOG2{1'b0}}; + assign bram1_addrb[0:10 - NUM_ENTRY_LOG2] = {11-NUM_ENTRY_LOG2{1'b0}}; + assign bram2_addra[0:9 - NUM_ENTRY_LOG2] = {10-NUM_ENTRY_LOG2{1'b0}}; + assign bram2_addrb[0:9 - NUM_ENTRY_LOG2] = {10-NUM_ENTRY_LOG2{1'b0}}; + + // This ram houses the RPN(20:51) bits, wr_array_data_bram(0:31) + // uses wr_array_val(0), parity is wr_array_data_bram(66:69) + RAMB16_S36_S36 + #(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only + bram0( + .CLKA(clk2x), + .CLKB(clk2x), + .SSRA(sreset_q), + .SSRB(sreset_q), + .ADDRA(bram0_addra), + .ADDRB(bram0_addrb), + .DIA(wr_array_data_bram[0:31]), + .DIB(32'b0), + .DOA(rd_array_data_d_std[0:31]), + .DOB(array_cmp_data_bram_std[0:31]), + .DOPA(rd_array_data_d_std[66:69]), + .DOPB(array_cmp_data_bramp_std[66:69]), + .DIPA(wr_array_data_bram[66:69]), + .DIPB(4'b0), + .ENA(1'b1), + .ENB(1'b1), + .WEA(bram0_wea), + .WEB(1'b0) + ); + + // This ram houses the RPN(18:19),R,C,4xResv bits, wr_array_data_bram(32:39) + // uses wr_array_val(1), parity is wr_array_data_bram(70) + RAMB16_S9_S9 + #(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only + bram1( + .CLKA(clk2x), + .CLKB(clk2x), + .SSRA(sreset_q), + .SSRB(sreset_q), + .ADDRA(bram1_addra), + .ADDRB(bram1_addrb), + .DIA(wr_array_data_bram[32:39]), + .DIB(8'b0), + .DOA(rd_array_data_d_std[32:39]), + .DOB(array_cmp_data_bram_std[32:39]), + .DOPA(rd_array_data_d_std[70:70]), + .DOPB(array_cmp_data_bramp_std[70:70]), + .DIPA(wr_array_data_bram[70:70]), + .DIPB(1'b0), + .ENA(1'b1), + .ENB(1'b1), + .WEA(bram1_wea), + .WEB(1'b0) + ); + + // This ram houses the 1xResv,U0-U3,WIMGE,UX,UW,UR,SX,SW,SR bits, wr_array_data_bram(40:55) + // uses wr_array_val(2), parity is wr_array_data_bram(71:72) + RAMB16_S18_S18 + #(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only + bram2( + .CLKA(clk2x), + .CLKB(clk2x), + .SSRA(sreset_q), + .SSRB(sreset_q), + .ADDRA(bram2_addra), + .ADDRB(bram2_addrb), + .DIA(wr_array_data_bram[40:55]), + .DIB(16'b0), + .DOA(rd_array_data_d_std[40:55]), + .DOB(array_cmp_data_bram_std[40:55]), + .DOPA(rd_array_data_d_std[71:72]), + .DOPB(array_cmp_data_bramp_std[71:72]), + .DIPA(wr_array_data_bram[71:72]), + .DIPB(2'b0), + .ENA(1'b1), + .ENB(1'b1), + .WEA(bram2_wea), + .WEB(1'b0) + ); + + // array write data swizzle -> convert 68-bit data to 73-bit bram data + // 32x143 version, 42b RA + // wr_array_data + // 0:29 - RPN + // 30:31 - R,C + // 32:35 - ResvAttr + // 36:39 - U0-U3 + // 40:44 - WIMGE + // 45:47 - UX,UW,UR + // 48:50 - SX,SW,SR + // 51:60 - CAM parity + // 61:67 - Array parity + // + // RTX layout in A2_AvpEratHelper.C + // ram0(0:31): 00 & RPN(0:29) + // ram1(0:7) : 00 & R,C,ResvAttr(0:3) + // ram2(0:15): '0' & U(0:3),WIMGE,UX,UW,UR,SX,SW,SR + assign wr_array_data_bram[0:72] = {2'b00, wr_array_data[0:29], 2'b00, wr_array_data[30:35], 1'b0, wr_array_data[36:50], wr_array_data[51:60], wr_array_data[61:67]}; + + assign rd_array_data_d_std[56:65] = 10'b0; // tie off unused bits + + assign rd_array_data_d[0:29] = rd_array_data_d_std[2:31]; + assign rd_array_data_d[30:35] = rd_array_data_d_std[34:39]; + assign rd_array_data_d[36:50] = rd_array_data_d_std[41:55]; + assign rd_array_data_d[61:67] = rd_array_data_d_std[66:72]; + assign array_cmp_data_bram = array_cmp_data_bram_std; + assign array_cmp_data_bramp = array_cmp_data_bramp_std; + + //--------------------------------------------------------------------- + // entity output assignments + //--------------------------------------------------------------------- + assign rd_array_data = rd_array_data_q; + assign cam_cmp_data = cam_cmp_data_q; + assign rd_cam_data = rd_cam_data_q; + + assign entry_valid[0] = entry0_v_q; + assign entry_valid[1] = entry1_v_q; + assign entry_valid[2] = entry2_v_q; + assign entry_valid[3] = entry3_v_q; + assign entry_valid[4] = entry4_v_q; + assign entry_valid[5] = entry5_v_q; + assign entry_valid[6] = entry6_v_q; + assign entry_valid[7] = entry7_v_q; + assign entry_valid[8] = entry8_v_q; + assign entry_valid[9] = entry9_v_q; + assign entry_valid[10] = entry10_v_q; + assign entry_valid[11] = entry11_v_q; + assign entry_valid[12] = entry12_v_q; + assign entry_valid[13] = entry13_v_q; + assign entry_valid[14] = entry14_v_q; + assign entry_valid[15] = entry15_v_q; + assign entry_valid[16] = entry16_v_q; + assign entry_valid[17] = entry17_v_q; + assign entry_valid[18] = entry18_v_q; + assign entry_valid[19] = entry19_v_q; + assign entry_valid[20] = entry20_v_q; + assign entry_valid[21] = entry21_v_q; + assign entry_valid[22] = entry22_v_q; + assign entry_valid[23] = entry23_v_q; + assign entry_valid[24] = entry24_v_q; + assign entry_valid[25] = entry25_v_q; + assign entry_valid[26] = entry26_v_q; + assign entry_valid[27] = entry27_v_q; + assign entry_valid[28] = entry28_v_q; + assign entry_valid[29] = entry29_v_q; + assign entry_valid[30] = entry30_v_q; + assign entry_valid[31] = entry31_v_q; + + assign entry_match = entry_match_q; + + assign cam_hit_entry = cam_hit_entry_q; + assign cam_hit = cam_hit_q; + + assign func_scan_out = func_scan_in; + assign regfile_scan_out = regfile_scan_in; + assign time_scan_out = time_scan_in; + + assign unused = |{gnd, vdd, vcs, nclk, tc_ccflush_dc, tc_scan_dis_dc_b, tc_scan_diag_dc, + tc_lbist_en_dc, an_ac_atpg_en_dc, lcb_d_mode_dc, lcb_clkoff_dc_b, + lcb_act_dis_dc, lcb_mpw1_dc_b, lcb_mpw2_dc_b, lcb_delay_lclkr_dc, + pc_sg_2, pc_func_slp_sl_thold_2, pc_func_slp_nsl_thold_2, pc_regf_slp_sl_thold_2, + pc_time_sl_thold_2, pc_fce_2, array_cmp_data_bram[0:1], array_cmp_data_bram[32:33], + array_cmp_data_bram[40], wr_array_data_bram[56:65], + cam_cmp_data_np1[0:74], cam_cmp_data_np1[79:CAM_DATA_WIDTH-1], + rd_array_data_d_std[0:1], rd_array_data_d_std[32:33], + rd_array_data_d_std[40], rd_array_data_d_std[56:65], rd_val_late, wr_val_early}; +endmodule diff --git a/dev/verilog/trilib/tri_cam_32x143_1r1w1c_matchline.v b/dev/verilog/trilib/tri_cam_32x143_1r1w1c_matchline.v new file mode 100755 index 0000000..eee2d16 --- /dev/null +++ b/dev/verilog/trilib/tri_cam_32x143_1r1w1c_matchline.v @@ -0,0 +1,471 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//******************************************************************** +//* +//* TITLE: D-ERAT CAM Match Line Logic for Functional Model +//* +//* NAME: tri_cam_32x143_1r1w1c_matchline +//* +//********************************************************************* + +module tri_cam_32x143_1r1w1c_matchline( + addr_in, + addr_enable, + comp_pgsize, + pgsize_enable, + entry_size, + entry_cmpmask, + entry_xbit, + entry_xbitmask, + entry_epn, + comp_class, + entry_class, + class_enable, + comp_extclass, + entry_extclass, + extclass_enable, + comp_state, + entry_hv, + entry_ds, + state_enable, + entry_thdid, + comp_thdid, + thdid_enable, + entry_pid, + comp_pid, + pid_enable, + entry_v, + comp_invalidate, + match +); + parameter HAVE_XBIT = 1; + parameter NUM_PGSIZES = 5; + parameter HAVE_CMPMASK = 1; + parameter CMPMASK_WIDTH = 4; + + // @{default:nclk}@ + input [0:51] addr_in; + input [0:1] addr_enable; + input [0:2] comp_pgsize; + input pgsize_enable; + input [0:2] entry_size; + input [0:CMPMASK_WIDTH-1] entry_cmpmask; + input entry_xbit; + input [0:CMPMASK_WIDTH-1] entry_xbitmask; + input [0:51] entry_epn; + input [0:1] comp_class; + input [0:1] entry_class; + input [0:2] class_enable; + input [0:1] comp_extclass; + input [0:1] entry_extclass; + input [0:1] extclass_enable; + input [0:1] comp_state; + input entry_hv; + input entry_ds; + input [0:1] state_enable; + input [0:3] entry_thdid; + input [0:3] comp_thdid; + input [0:1] thdid_enable; + input [0:7] entry_pid; + input [0:7] comp_pid; + input pid_enable; + input entry_v; + input comp_invalidate; + + output match; + + // tri_cam_32x143_1r1w1c_matchline + + //---------------------------------------------------------------------- + // Signals + //---------------------------------------------------------------------- + + wire [34:51] entry_epn_b; + wire function_50_51; + wire function_48_51; + wire function_46_51; + wire function_44_51; + wire function_40_51; + wire function_36_51; + wire function_34_51; + wire pgsize_eq_16K; + wire pgsize_eq_64K; + wire pgsize_eq_256K; + wire pgsize_eq_1M; + wire pgsize_eq_16M; + wire pgsize_eq_256M; + wire pgsize_eq_1G; + wire pgsize_gte_16K; + wire pgsize_gte_64K; + wire pgsize_gte_256K; + wire pgsize_gte_1M; + wire pgsize_gte_16M; + wire pgsize_gte_256M; + wire pgsize_gte_1G; + wire comp_or_34_35; + wire comp_or_34_39; + wire comp_or_36_39; + wire comp_or_40_43; + wire comp_or_44_45; + wire comp_or_44_47; + wire comp_or_46_47; + wire comp_or_48_49; + wire comp_or_48_51; + wire comp_or_50_51; + wire [0:72] match_line; + wire pgsize_match; + wire addr_match; + wire class_match; + wire extclass_match; + wire state_match; + wire thdid_match; + wire pid_match; + (* analysis_not_referenced="true" *) + wire [0:2] unused; + + assign match_line[0:72] = (~({entry_epn[0:51], entry_size[0:2], entry_class[0:1], entry_extclass[0:1], entry_hv, entry_ds, entry_pid[0:7], entry_thdid[0:3]} ^ + {addr_in[0:51], comp_pgsize[0:2], comp_class[0:1], comp_extclass[0:1], comp_state[0:1], comp_pid[0:7], comp_thdid[0:3]})); + + generate + begin + if (NUM_PGSIZES == 8) + begin : numpgsz8 + // tie off unused signals + assign comp_or_34_39 = 1'b0; + assign comp_or_44_47 = 1'b0; + assign comp_or_48_51 = 1'b0; + assign unused[0] = |{comp_or_34_39, comp_or_44_47, comp_or_48_51}; + + assign entry_epn_b[34:51] = (~(entry_epn[34:51])); + + if (HAVE_CMPMASK == 0) + begin + assign pgsize_eq_1G = ( entry_size[0] & entry_size[1] & entry_size[2]); + assign pgsize_eq_256M = ( entry_size[0] & entry_size[1] & (~(entry_size[2]))); + assign pgsize_eq_16M = ( entry_size[0] & (~(entry_size[1])) & entry_size[2]); + assign pgsize_eq_1M = ( entry_size[0] & (~(entry_size[1])) & (~(entry_size[2]))); + assign pgsize_eq_256K = ((~(entry_size[0])) & entry_size[1] & entry_size[2]); + assign pgsize_eq_64K = ((~(entry_size[0])) & entry_size[1] & (~(entry_size[2]))); + assign pgsize_eq_16K = ((~(entry_size[0])) & (~(entry_size[1])) & entry_size[2]); + + assign pgsize_gte_1G = ( entry_size[0] & entry_size[1] & entry_size[2]); + assign pgsize_gte_256M = ( entry_size[0] & entry_size[1] & (~(entry_size[2]))) | pgsize_gte_1G; + assign pgsize_gte_16M = ( entry_size[0] & (~(entry_size[1])) & entry_size[2]) | pgsize_gte_256M; + assign pgsize_gte_1M = ( entry_size[0] & (~(entry_size[1])) & (~(entry_size[2]))) | pgsize_gte_16M; + assign pgsize_gte_256K = ((~(entry_size[0])) & entry_size[1] & entry_size[2]) | pgsize_gte_1M; + assign pgsize_gte_64K = ((~(entry_size[0])) & entry_size[1] & (~(entry_size[2]))) | pgsize_gte_256K; + assign pgsize_gte_16K = ((~(entry_size[0])) & (~(entry_size[1])) & entry_size[2]) | pgsize_gte_64K; + + assign unused[1] = |{entry_cmpmask, entry_xbitmask}; + end + + if (HAVE_CMPMASK == 1) + begin + // size entry_cmpmask: 0123456 + // 1GB 0000000 + // 256MB 1000000 + // 16MB 1100000 + // 1MB 1110000 + // 256KB 1111000 + // 64KB 1111100 + // 16KB 1111110 + // 4KB 1111111 + assign pgsize_gte_1G = (~entry_cmpmask[0]); + assign pgsize_gte_256M = (~entry_cmpmask[1]); + assign pgsize_gte_16M = (~entry_cmpmask[2]); + assign pgsize_gte_1M = (~entry_cmpmask[3]); + assign pgsize_gte_256K = (~entry_cmpmask[4]); + assign pgsize_gte_64K = (~entry_cmpmask[5]); + assign pgsize_gte_16K = (~entry_cmpmask[6]); + + // size entry_xbitmask: 0123456 + // 1GB 1000000 + // 256MB 0100000 + // 16MB 0010000 + // 1MB 0001000 + // 256KB 0000100 + // 64KB 0000010 + // 16KB 0000001 + // 4KB 0000000 + assign pgsize_eq_1G = entry_xbitmask[0]; + assign pgsize_eq_256M = entry_xbitmask[1]; + assign pgsize_eq_16M = entry_xbitmask[2]; + assign pgsize_eq_1M = entry_xbitmask[3]; + assign pgsize_eq_256K = entry_xbitmask[4]; + assign pgsize_eq_64K = entry_xbitmask[5]; + assign pgsize_eq_16K = entry_xbitmask[6]; + + assign unused[1] = 1'b0; + end + + if (HAVE_XBIT == 0) + begin + assign function_34_51 = 1'b0; + assign function_36_51 = 1'b0; + assign function_40_51 = 1'b0; + assign function_44_51 = 1'b0; + assign function_46_51 = 1'b0; + assign function_48_51 = 1'b0; + assign function_50_51 = 1'b0; + assign unused[2] = |{function_34_51, function_36_51, function_40_51, function_44_51, + function_46_51, function_48_51, function_50_51, entry_xbit, + entry_epn_b, pgsize_eq_1G, pgsize_eq_256M, pgsize_eq_16M, + pgsize_eq_1M, pgsize_eq_256K, pgsize_eq_64K, pgsize_eq_16K}; + end + + if (HAVE_XBIT != 0) + begin + assign function_34_51 = (~(entry_xbit)) | (~(pgsize_eq_1G)) | (|(entry_epn_b[34:51] & addr_in[34:51])); + assign function_36_51 = (~(entry_xbit)) | (~(pgsize_eq_256M)) | (|(entry_epn_b[36:51] & addr_in[36:51])); + assign function_40_51 = (~(entry_xbit)) | (~(pgsize_eq_16M)) | (|(entry_epn_b[40:51] & addr_in[40:51])); + assign function_44_51 = (~(entry_xbit)) | (~(pgsize_eq_1M)) | (|(entry_epn_b[44:51] & addr_in[44:51])); + assign function_46_51 = (~(entry_xbit)) | (~(pgsize_eq_256K)) | (|(entry_epn_b[46:51] & addr_in[46:51])); + assign function_48_51 = (~(entry_xbit)) | (~(pgsize_eq_64K)) | (|(entry_epn_b[48:51] & addr_in[48:51])); + assign function_50_51 = (~(entry_xbit)) | (~(pgsize_eq_16K)) | (|(entry_epn_b[50:51] & addr_in[50:51])); + assign unused[2] = 1'b0; + end + + assign comp_or_50_51 = (&(match_line[50:51])) | pgsize_gte_16K; + assign comp_or_48_49 = (&(match_line[48:49])) | pgsize_gte_64K; + assign comp_or_46_47 = (&(match_line[46:47])) | pgsize_gte_256K; + assign comp_or_44_45 = (&(match_line[44:45])) | pgsize_gte_1M; + assign comp_or_40_43 = (&(match_line[40:43])) | pgsize_gte_16M; + assign comp_or_36_39 = (&(match_line[36:39])) | pgsize_gte_256M; + assign comp_or_34_35 = (&(match_line[34:35])) | pgsize_gte_1G; + + if (HAVE_XBIT == 0) + begin + assign addr_match = (comp_or_34_35 & // Ignore functions based on page size + comp_or_36_39 & + comp_or_40_43 & + comp_or_44_45 & + comp_or_46_47 & + comp_or_48_49 & + comp_or_50_51 & + (&(match_line[31:33])) & // Regular compare largest page size + ((&(match_line[0:30])) | (~(addr_enable[1])))) | // ignored part of epn + (~(addr_enable[0])); // Include address as part of compare, + // should never ignore for regular compare/read. + // Could ignore for compare/invalidate + end + + if (HAVE_XBIT != 0) + begin + assign addr_match = (function_50_51 & // Exclusion functions + function_48_51 & + function_46_51 & + function_44_51 & + function_40_51 & + function_36_51 & + function_34_51 & + comp_or_34_35 & // Ignore functions based on page size + comp_or_36_39 & + comp_or_40_43 & + comp_or_44_45 & + comp_or_46_47 & + comp_or_48_49 & + comp_or_50_51 & + (&(match_line[31:33])) & // Regular compare largest page size + (&(match_line[0:30]) | (~(addr_enable[1])))) | // ignored part of epn + (~(addr_enable[0])); // Include address as part of compare, + // should never ignore for regular compare/read. + // Could ignore for compare/invalidate + end + end // numpgsz8: NUM_PGSIZES = 8 + + + if (NUM_PGSIZES == 5) + begin : numpgsz5 + // tie off unused signals + assign function_50_51 = 1'b0; + assign function_46_51 = 1'b0; + assign function_36_51 = 1'b0; + assign pgsize_eq_16K = 1'b0; + assign pgsize_eq_256K = 1'b0; + assign pgsize_eq_256M = 1'b0; + assign pgsize_gte_16K = 1'b0; + assign pgsize_gte_256K = 1'b0; + assign pgsize_gte_256M = 1'b0; + assign comp_or_34_35 = 1'b0; + assign comp_or_36_39 = 1'b0; + assign comp_or_44_45 = 1'b0; + assign comp_or_46_47 = 1'b0; + assign comp_or_48_49 = 1'b0; + assign comp_or_50_51 = 1'b0; + assign unused[0] = |{function_50_51, function_46_51, function_36_51, + pgsize_eq_16K, pgsize_eq_256K, pgsize_eq_256M, + pgsize_gte_16K, pgsize_gte_256K, pgsize_gte_256M, + comp_or_34_35, comp_or_36_39, comp_or_44_45, + comp_or_46_47, comp_or_48_49, comp_or_50_51}; + + assign entry_epn_b[34:51] = (~(entry_epn[34:51])); + + if (HAVE_CMPMASK == 0) + begin + // 110 + assign pgsize_eq_1G = ( entry_size[0] & entry_size[1] & (~(entry_size[2]))); + // 111 + assign pgsize_eq_16M = ( entry_size[0] & entry_size[1] & entry_size[2]); + // 101 + assign pgsize_eq_1M = ( entry_size[0] & (~(entry_size[1])) & entry_size[2]); + // 011 + assign pgsize_eq_64K = ((~(entry_size[0])) & entry_size[1] & entry_size[2]); + + assign pgsize_gte_1G = ( entry_size[0] & entry_size[1] & (~(entry_size[2]))); + assign pgsize_gte_16M = ( entry_size[0] & entry_size[1] & entry_size[2]) | pgsize_gte_1G; + assign pgsize_gte_1M = ( entry_size[0] & (~(entry_size[1])) & entry_size[2]) | pgsize_gte_16M; + assign pgsize_gte_64K = ((~(entry_size[0])) & entry_size[1] & entry_size[2]) | pgsize_gte_1M; + + assign unused[1] = |{entry_cmpmask, entry_xbitmask}; + end + + if (HAVE_CMPMASK == 1) + begin + // size entry_cmpmask: 0123 + // 1GB 0000 + // 16MB 1000 + // 1MB 1100 + // 64KB 1110 + // 4KB 1111 + assign pgsize_gte_1G = (~entry_cmpmask[0]); + assign pgsize_gte_16M = (~entry_cmpmask[1]); + assign pgsize_gte_1M = (~entry_cmpmask[2]); + assign pgsize_gte_64K = (~entry_cmpmask[3]); + + // size entry_xbitmask: 0123 + // 1GB 1000 + // 16MB 0100 + // 1MB 0010 + // 64KB 0001 + // 4KB 0000 + assign pgsize_eq_1G = entry_xbitmask[0]; + assign pgsize_eq_16M = entry_xbitmask[1]; + assign pgsize_eq_1M = entry_xbitmask[2]; + assign pgsize_eq_64K = entry_xbitmask[3]; + + assign unused[1] = 1'b0; + end + + if (HAVE_XBIT == 0) + begin + assign function_34_51 = 1'b0; + assign function_40_51 = 1'b0; + assign function_44_51 = 1'b0; + assign function_48_51 = 1'b0; + assign unused[2] = |{function_34_51, function_40_51, function_44_51, + function_48_51, entry_xbit, entry_epn_b, + pgsize_eq_1G, pgsize_eq_16M, pgsize_eq_1M, pgsize_eq_64K}; + end + + if (HAVE_XBIT != 0) + begin + // 1G + assign function_34_51 = (~(entry_xbit)) | (~(pgsize_eq_1G)) | (|(entry_epn_b[34:51] & addr_in[34:51])); + // 16M + assign function_40_51 = (~(entry_xbit)) | (~(pgsize_eq_16M)) | (|(entry_epn_b[40:51] & addr_in[40:51])); + // 1M + assign function_44_51 = (~(entry_xbit)) | (~(pgsize_eq_1M)) | (|(entry_epn_b[44:51] & addr_in[44:51])); + // 64K + assign function_48_51 = (~(entry_xbit)) | (~(pgsize_eq_64K)) | (|(entry_epn_b[48:51] & addr_in[48:51])); + assign unused[2] = 1'b0; + end + + assign comp_or_48_51 = (&(match_line[48:51])) | pgsize_gte_64K; + assign comp_or_44_47 = (&(match_line[44:47])) | pgsize_gte_1M; + assign comp_or_40_43 = (&(match_line[40:43])) | pgsize_gte_16M; + assign comp_or_34_39 = (&(match_line[34:39])) | pgsize_gte_1G; + + if (HAVE_XBIT == 0) + begin + assign addr_match = (comp_or_34_39 & // Ignore functions based on page size + comp_or_40_43 & + comp_or_44_47 & + comp_or_48_51 & + (&(match_line[31:33])) & // Regular compare largest page size + ((&(match_line[0:30])) | (~(addr_enable[1])))) | // ignored part of epn + (~(addr_enable[0])); // Include address as part of compare, + // should never ignore for regular compare/read. + // Could ignore for compare/invalidate + end + + if (HAVE_XBIT != 0) + begin + assign addr_match = (function_48_51 & + function_44_51 & + function_40_51 & + function_34_51 & + comp_or_34_39 & // Ignore functions based on page size + comp_or_40_43 & + comp_or_44_47 & + comp_or_48_51 & + (&(match_line[31:33])) & // Regular compare largest page size + ((&(match_line[0:30])) | (~(addr_enable[1])))) | // ignored part of epn + (~(addr_enable[0])); // Include address as part of compare, + // should never ignore for regular compare/read. + // Could ignore for compare/invalidate + end + end // numpgsz5: NUM_PGSIZES = 5 + + + assign pgsize_match = (&(match_line[52:54])) | (~(pgsize_enable)); + + assign class_match = (match_line[55] | (~(class_enable[0]))) & + (match_line[56] | (~(class_enable[1]))) & + ((&(match_line[55:56])) | (~(class_enable[2])) | + ((~(entry_extclass[1])) & (~comp_invalidate))); // pid_nz bit + + assign extclass_match = (match_line[57] | (~(extclass_enable[0]))) & // iprot bit + (match_line[58] | (~(extclass_enable[1]))); // pid_nz bit + + assign state_match = (match_line[59] | (~(state_enable[0]))) & + (match_line[60] | (~(state_enable[1]))); + + assign thdid_match = (|(entry_thdid[0:3] & comp_thdid[0:3]) | (~(thdid_enable[0]))) & + (&(match_line[69:72]) | (~(thdid_enable[1])) | + ((~(entry_extclass[1])) & (~comp_invalidate))); // pid_nz bit + + assign pid_match = (&(match_line[61:68])) | + // entry_pid=0 ignores pid match for compares, + // but not for invalidates. + ((~(entry_extclass[1])) & (~comp_invalidate)) | // pid_nz bit + (~(pid_enable)); + + assign match = addr_match & // Address compare + pgsize_match & // Size compare + class_match & // Class compare + extclass_match & // ExtClass compare + state_match & // State compare + thdid_match & // ThdID compare + pid_match & // PID compare + entry_v; // Valid + end + endgenerate +endmodule diff --git a/dev/verilog/trilib/tri_csa22.v b/dev/verilog/trilib/tri_csa22.v new file mode 100755 index 0000000..8ccd3a0 --- /dev/null +++ b/dev/verilog/trilib/tri_csa22.v @@ -0,0 +1,55 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +//***************************************************************************** +// Description: XU Population Count +// +//***************************************************************************** + +`timescale 1 ns / 1 ns + +module tri_csa22( + a, + b, + car, + sum +); + input a; + input b; + output car; + output sum; + + wire car_b; + wire sum_b; + + assign car_b = (~(a & b)); + assign sum_b = (~(car_b & (a | b))); // this is equiv to an xnor + assign car = (~car_b); + assign sum = (~sum_b); + +endmodule diff --git a/dev/verilog/trilib/tri_csa32.v b/dev/verilog/trilib/tri_csa32.v new file mode 100755 index 0000000..1d7e99d --- /dev/null +++ b/dev/verilog/trilib/tri_csa32.v @@ -0,0 +1,66 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +module tri_csa32( + a, + b, + c, + car, + sum, + vd, + gd +); + input a; + input b; + input c; + output car; + output sum; + (* ANALYSIS_NOT_ASSIGNED="TRUE" *) + (* ANALYSIS_NOT_REFERENCED="TRUE" *) + inout vd; + (* ANALYSIS_NOT_ASSIGNED="TRUE" *) + (* ANALYSIS_NOT_REFERENCED="TRUE" *) + inout gd; + + wire carn1; + wire carn2; + wire carn3; + +// assign sum = a ^ b ^ c; + tri_xor3 CSA42_XOR3_1(sum, a, b, c); + +// assign car = (a & b) | (a & c) | (b & c); + tri_nand2 CSA42_NAND2_1(carn1, a, b); + tri_nand2 CSA42_NAND2_2(carn2, a, c); + tri_nand2 CSA42_NAND2_3(carn3, b, c); + tri_nand3 CSA42_NAND3_4(car, carn1, carn2, carn3); + + +endmodule diff --git a/dev/verilog/trilib/tri_csa42.v b/dev/verilog/trilib/tri_csa42.v new file mode 100755 index 0000000..249c485 --- /dev/null +++ b/dev/verilog/trilib/tri_csa42.v @@ -0,0 +1,86 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +module tri_csa42( + a, + b, + c, + d, + ki, + ko, + car, + sum, + vd, + gd +); + input a; + input b; + input c; + input d; + input ki; + output ko; + output car; + output sum; + (* ANALYSIS_NOT_ASSIGNED="TRUE" *) + (* ANALYSIS_NOT_REFERENCED="TRUE" *) + inout vd; + (* ANALYSIS_NOT_ASSIGNED="TRUE" *) + (* ANALYSIS_NOT_REFERENCED="TRUE" *) + inout gd; + + wire s1; + + wire carn1; + wire carn2; + wire carn3; + wire kon1; + wire kon2; + wire kon3; + +// assign s1 = b ^ c ^ d; + tri_xor3 CSA42_XOR3_1(s1,b,c,d); + +// assign sum = s1 ^ a ^ ki; + tri_xor3 CSA42_XOR3_2(sum,s1,a,ki); + +// assign car = (s1 & a) | (s1 & ki) | (a & ki); + tri_nand2 CSA42_NAND2_1(carn1,s1,a); + tri_nand2 CSA42_NAND2_2(carn2,s1,ki); + tri_nand2 CSA42_NAND2_3(carn3,a,ki); + tri_nand3 CSA42_NAND3_4(car,carn1,carn2,carn3); + +// assign ko = (b & c) | (b & d) | (c & d); + tri_nand2 CSA42_NAND2_5(kon1,b,c); + tri_nand2 CSA42_NAND2_6(kon2,b,d); + tri_nand2 CSA42_NAND2_7(kon3,c,d); + tri_nand3 CSA42_NAND3_8(ko,kon1,kon2,kon3); + + +endmodule diff --git a/dev/verilog/trilib/tri_debug_mux16.v b/dev/verilog/trilib/tri_debug_mux16.v new file mode 100755 index 0000000..4c542b9 --- /dev/null +++ b/dev/verilog/trilib/tri_debug_mux16.v @@ -0,0 +1,159 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//******************************************************************** +//* +//* TITLE: Debug Mux Component (16:1 Debug Groups; 4:1 Trigger Groups) +//* +//* NAME: tri_debug_mux16.vhdl +//* +//******************************************************************** + +module tri_debug_mux16( +// vd, +// gd, + select_bits, + dbg_group0, + dbg_group1, + dbg_group2, + dbg_group3, + dbg_group4, + dbg_group5, + dbg_group6, + dbg_group7, + dbg_group8, + dbg_group9, + dbg_group10, + dbg_group11, + dbg_group12, + dbg_group13, + dbg_group14, + dbg_group15, + trace_data_in, + trace_data_out, + // Instruction Trace (HTM) Controls + coretrace_ctrls_in, + coretrace_ctrls_out +); + +// Include model build parameters + parameter DBG_WIDTH = 32; // A2o=32; A2i=88 + +//===================================================================== +// Port Definitions +//===================================================================== + + input [0:10] select_bits; + input [0:DBG_WIDTH-1] dbg_group0; + input [0:DBG_WIDTH-1] dbg_group1; + input [0:DBG_WIDTH-1] dbg_group2; + input [0:DBG_WIDTH-1] dbg_group3; + input [0:DBG_WIDTH-1] dbg_group4; + input [0:DBG_WIDTH-1] dbg_group5; + input [0:DBG_WIDTH-1] dbg_group6; + input [0:DBG_WIDTH-1] dbg_group7; + input [0:DBG_WIDTH-1] dbg_group8; + input [0:DBG_WIDTH-1] dbg_group9; + input [0:DBG_WIDTH-1] dbg_group10; + input [0:DBG_WIDTH-1] dbg_group11; + input [0:DBG_WIDTH-1] dbg_group12; + input [0:DBG_WIDTH-1] dbg_group13; + input [0:DBG_WIDTH-1] dbg_group14; + input [0:DBG_WIDTH-1] dbg_group15; + input [0:DBG_WIDTH-1] trace_data_in; + output [0:DBG_WIDTH-1] trace_data_out; + +// Instruction Trace (HTM) Control Signals: +// 0 - ac_an_coretrace_first_valid +// 1 - ac_an_coretrace_valid +// 2:3 - ac_an_coretrace_type[0:1] + input [0:3] coretrace_ctrls_in; + output [0:3] coretrace_ctrls_out; + +//===================================================================== +// Signal Declarations / Misc +//===================================================================== + parameter DBG_1FOURTH = DBG_WIDTH/4; + parameter DBG_2FOURTH = DBG_WIDTH/2; + parameter DBG_3FOURTH = 3 * DBG_WIDTH/4; + + wire [0:DBG_WIDTH-1] debug_grp_selected; + wire [0:DBG_WIDTH-1] debug_grp_rotated; + +// Don't reference unused inputs: +(* analysis_not_referenced="true" *) + wire unused; + assign unused = select_bits[4]; + +// Instruction Trace controls are passed-through: + assign coretrace_ctrls_out = coretrace_ctrls_in ; + +//===================================================================== +// Mux Function +//===================================================================== + // Debug Mux + assign debug_grp_selected = (select_bits[0:3] == 4'b0000) ? dbg_group0 : + (select_bits[0:3] == 4'b0001) ? dbg_group1 : + (select_bits[0:3] == 4'b0010) ? dbg_group2 : + (select_bits[0:3] == 4'b0011) ? dbg_group3 : + (select_bits[0:3] == 4'b0100) ? dbg_group4 : + (select_bits[0:3] == 4'b0101) ? dbg_group5 : + (select_bits[0:3] == 4'b0110) ? dbg_group6 : + (select_bits[0:3] == 4'b0111) ? dbg_group7 : + (select_bits[0:3] == 4'b1000) ? dbg_group8 : + (select_bits[0:3] == 4'b1001) ? dbg_group9 : + (select_bits[0:3] == 4'b1010) ? dbg_group10 : + (select_bits[0:3] == 4'b1011) ? dbg_group11 : + (select_bits[0:3] == 4'b1100) ? dbg_group12 : + (select_bits[0:3] == 4'b1101) ? dbg_group13 : + (select_bits[0:3] == 4'b1110) ? dbg_group14 : + dbg_group15; + + assign debug_grp_rotated = (select_bits[5:6] == 2'b11) ? {debug_grp_selected[DBG_1FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_1FOURTH - 1]} : + (select_bits[5:6] == 2'b10) ? {debug_grp_selected[DBG_2FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_2FOURTH - 1]} : + (select_bits[5:6] == 2'b01) ? {debug_grp_selected[DBG_3FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_3FOURTH - 1]} : + debug_grp_selected[0:DBG_WIDTH - 1]; + + + assign trace_data_out[0:DBG_1FOURTH - 1] = (select_bits[7] == 1'b0) ? trace_data_in[0:DBG_1FOURTH - 1] : + debug_grp_rotated[0:DBG_1FOURTH - 1]; + + assign trace_data_out[DBG_1FOURTH:DBG_2FOURTH - 1] = (select_bits[8] == 1'b0) ? trace_data_in[DBG_1FOURTH:DBG_2FOURTH - 1] : + debug_grp_rotated[DBG_1FOURTH:DBG_2FOURTH - 1]; + + assign trace_data_out[DBG_2FOURTH:DBG_3FOURTH - 1] = (select_bits[9] == 1'b0) ? trace_data_in[DBG_2FOURTH:DBG_3FOURTH - 1] : + debug_grp_rotated[DBG_2FOURTH:DBG_3FOURTH - 1]; + + assign trace_data_out[DBG_3FOURTH:DBG_WIDTH - 1] = (select_bits[10] == 1'b0) ? trace_data_in[DBG_3FOURTH:DBG_WIDTH - 1] : + debug_grp_rotated[DBG_3FOURTH:DBG_WIDTH - 1]; + + +endmodule + diff --git a/dev/verilog/trilib/tri_debug_mux32.v b/dev/verilog/trilib/tri_debug_mux32.v new file mode 100755 index 0000000..c8eaaf0 --- /dev/null +++ b/dev/verilog/trilib/tri_debug_mux32.v @@ -0,0 +1,204 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//******************************************************************** +//* +//* TITLE: Debug Mux Component (32:1 Debug Groups; 4:1 Trigger Groups) +//* +//* NAME: tri_debug_mux32.vhdl +//* +//******************************************************************** + + +module tri_debug_mux32( +// vd, +// gd, + select_bits, + dbg_group0, + dbg_group1, + dbg_group2, + dbg_group3, + dbg_group4, + dbg_group5, + dbg_group6, + dbg_group7, + dbg_group8, + dbg_group9, + dbg_group10, + dbg_group11, + dbg_group12, + dbg_group13, + dbg_group14, + dbg_group15, + dbg_group16, + dbg_group17, + dbg_group18, + dbg_group19, + dbg_group20, + dbg_group21, + dbg_group22, + dbg_group23, + dbg_group24, + dbg_group25, + dbg_group26, + dbg_group27, + dbg_group28, + dbg_group29, + dbg_group30, + dbg_group31, + trace_data_in, + trace_data_out, + + // Instruction Trace (HTM) Controls + coretrace_ctrls_in, + coretrace_ctrls_out +); + +// Include model build parameters + parameter DBG_WIDTH = 32; // A2o=32; A2i=88 + +//===================================================================== +// Port Definitions +//===================================================================== + + input [0:10] select_bits; + input [0:DBG_WIDTH-1] dbg_group0; + input [0:DBG_WIDTH-1] dbg_group1; + input [0:DBG_WIDTH-1] dbg_group2; + input [0:DBG_WIDTH-1] dbg_group3; + input [0:DBG_WIDTH-1] dbg_group4; + input [0:DBG_WIDTH-1] dbg_group5; + input [0:DBG_WIDTH-1] dbg_group6; + input [0:DBG_WIDTH-1] dbg_group7; + input [0:DBG_WIDTH-1] dbg_group8; + input [0:DBG_WIDTH-1] dbg_group9; + input [0:DBG_WIDTH-1] dbg_group10; + input [0:DBG_WIDTH-1] dbg_group11; + input [0:DBG_WIDTH-1] dbg_group12; + input [0:DBG_WIDTH-1] dbg_group13; + input [0:DBG_WIDTH-1] dbg_group14; + input [0:DBG_WIDTH-1] dbg_group15; + input [0:DBG_WIDTH-1] dbg_group16; + input [0:DBG_WIDTH-1] dbg_group17; + input [0:DBG_WIDTH-1] dbg_group18; + input [0:DBG_WIDTH-1] dbg_group19; + input [0:DBG_WIDTH-1] dbg_group20; + input [0:DBG_WIDTH-1] dbg_group21; + input [0:DBG_WIDTH-1] dbg_group22; + input [0:DBG_WIDTH-1] dbg_group23; + input [0:DBG_WIDTH-1] dbg_group24; + input [0:DBG_WIDTH-1] dbg_group25; + input [0:DBG_WIDTH-1] dbg_group26; + input [0:DBG_WIDTH-1] dbg_group27; + input [0:DBG_WIDTH-1] dbg_group28; + input [0:DBG_WIDTH-1] dbg_group29; + input [0:DBG_WIDTH-1] dbg_group30; + input [0:DBG_WIDTH-1] dbg_group31; + input [0:DBG_WIDTH-1] trace_data_in; + output [0:DBG_WIDTH-1] trace_data_out; + +// Instruction Trace (HTM) Control Signals: +// 0 - ac_an_coretrace_first_valid +// 1 - ac_an_coretrace_valid +// 2:3 - ac_an_coretrace_type[0:1] + input [0:3] coretrace_ctrls_in; + output [0:3] coretrace_ctrls_out; + +//===================================================================== +// Signal Declarations / Misc +//===================================================================== + parameter DBG_1FOURTH = DBG_WIDTH/4; + parameter DBG_2FOURTH = DBG_WIDTH/2; + parameter DBG_3FOURTH = 3 * DBG_WIDTH/4; + + wire [0:DBG_WIDTH-1] debug_grp_selected; + wire [0:DBG_WIDTH-1] debug_grp_rotated; + +// Instruction Trace controls are passed-through: + assign coretrace_ctrls_out = coretrace_ctrls_in ; + +//===================================================================== +// Mux Function +//===================================================================== + // Debug Mux + assign debug_grp_selected = (select_bits[0:4] == 5'b00000) ? dbg_group0 : + (select_bits[0:4] == 5'b00001) ? dbg_group1 : + (select_bits[0:4] == 5'b00010) ? dbg_group2 : + (select_bits[0:4] == 5'b00011) ? dbg_group3 : + (select_bits[0:4] == 5'b00100) ? dbg_group4 : + (select_bits[0:4] == 5'b00101) ? dbg_group5 : + (select_bits[0:4] == 5'b00110) ? dbg_group6 : + (select_bits[0:4] == 5'b00111) ? dbg_group7 : + (select_bits[0:4] == 5'b01000) ? dbg_group8 : + (select_bits[0:4] == 5'b01001) ? dbg_group9 : + (select_bits[0:4] == 5'b01010) ? dbg_group10 : + (select_bits[0:4] == 5'b01011) ? dbg_group11 : + (select_bits[0:4] == 5'b01100) ? dbg_group12 : + (select_bits[0:4] == 5'b01101) ? dbg_group13 : + (select_bits[0:4] == 5'b01110) ? dbg_group14 : + (select_bits[0:4] == 5'b01111) ? dbg_group15 : + (select_bits[0:4] == 5'b10000) ? dbg_group16 : + (select_bits[0:4] == 5'b10001) ? dbg_group17 : + (select_bits[0:4] == 5'b10010) ? dbg_group18 : + (select_bits[0:4] == 5'b10011) ? dbg_group19 : + (select_bits[0:4] == 5'b10100) ? dbg_group20 : + (select_bits[0:4] == 5'b10101) ? dbg_group21 : + (select_bits[0:4] == 5'b10110) ? dbg_group22 : + (select_bits[0:4] == 5'b10111) ? dbg_group23 : + (select_bits[0:4] == 5'b11000) ? dbg_group24 : + (select_bits[0:4] == 5'b11001) ? dbg_group25 : + (select_bits[0:4] == 5'b11010) ? dbg_group26 : + (select_bits[0:4] == 5'b11011) ? dbg_group27 : + (select_bits[0:4] == 5'b11100) ? dbg_group28 : + (select_bits[0:4] == 5'b11101) ? dbg_group29 : + (select_bits[0:4] == 5'b11110) ? dbg_group30 : + dbg_group31; + + assign debug_grp_rotated = (select_bits[5:6] == 2'b11) ? {debug_grp_selected[DBG_1FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_1FOURTH - 1]} : + (select_bits[5:6] == 2'b10) ? {debug_grp_selected[DBG_2FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_2FOURTH - 1]} : + (select_bits[5:6] == 2'b01) ? {debug_grp_selected[DBG_3FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_3FOURTH - 1]} : + debug_grp_selected[0:DBG_WIDTH - 1]; + + + assign trace_data_out[0:DBG_1FOURTH - 1] = (select_bits[7] == 1'b0) ? trace_data_in[0:DBG_1FOURTH - 1] : + debug_grp_rotated[0:DBG_1FOURTH - 1]; + + assign trace_data_out[DBG_1FOURTH:DBG_2FOURTH - 1] = (select_bits[8] == 1'b0) ? trace_data_in[DBG_1FOURTH:DBG_2FOURTH - 1] : + debug_grp_rotated[DBG_1FOURTH:DBG_2FOURTH - 1]; + + assign trace_data_out[DBG_2FOURTH:DBG_3FOURTH - 1] = (select_bits[9] == 1'b0) ? trace_data_in[DBG_2FOURTH:DBG_3FOURTH - 1] : + debug_grp_rotated[DBG_2FOURTH:DBG_3FOURTH - 1]; + + assign trace_data_out[DBG_3FOURTH:DBG_WIDTH - 1] = (select_bits[10] == 1'b0) ? trace_data_in[DBG_3FOURTH:DBG_WIDTH - 1] : + debug_grp_rotated[DBG_3FOURTH:DBG_WIDTH - 1]; + + +endmodule + diff --git a/dev/verilog/trilib/tri_debug_mux4.v b/dev/verilog/trilib/tri_debug_mux4.v new file mode 100755 index 0000000..ab6011f --- /dev/null +++ b/dev/verilog/trilib/tri_debug_mux4.v @@ -0,0 +1,124 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//******************************************************************** +//* +//* TITLE: Debug Mux Component (4:1 Debug Groups; 4:1 Trigger Groups) +//* +//* NAME: tri_debug_mux4.vhdl +//* +//******************************************************************** + + +module tri_debug_mux4( +// vd, +// gd, + select_bits, + dbg_group0, + dbg_group1, + dbg_group2, + dbg_group3, + trace_data_in, + trace_data_out, + + // Instruction Trace (HTM) Controls + coretrace_ctrls_in, + coretrace_ctrls_out +); + +// Include model build parameters + parameter DBG_WIDTH = 32; // A2o=32; A2i=88 + +//===================================================================== +// Port Definitions +//===================================================================== + + input [0:10] select_bits; + input [0:DBG_WIDTH-1] dbg_group0; + input [0:DBG_WIDTH-1] dbg_group1; + input [0:DBG_WIDTH-1] dbg_group2; + input [0:DBG_WIDTH-1] dbg_group3; + input [0:DBG_WIDTH-1] trace_data_in; + output [0:DBG_WIDTH-1] trace_data_out; + +// Instruction Trace (HTM) Control Signals: +// 0 - ac_an_coretrace_first_valid +// 1 - ac_an_coretrace_valid +// 2:3 - ac_an_coretrace_type[0:1] + input [0:3] coretrace_ctrls_in; + output [0:3] coretrace_ctrls_out; + +//===================================================================== +// Signal Declarations / Misc +//===================================================================== + parameter DBG_1FOURTH = DBG_WIDTH/4; + parameter DBG_2FOURTH = DBG_WIDTH/2; + parameter DBG_3FOURTH = 3 * DBG_WIDTH/4; + + wire [0:DBG_WIDTH-1] debug_grp_selected; + wire [0:DBG_WIDTH-1] debug_grp_rotated; + +// Don't reference unused inputs: +(* analysis_not_referenced="true" *) + wire unused; + assign unused = (|select_bits[2:4]) ; + +// Instruction Trace controls are passed-through: + assign coretrace_ctrls_out = coretrace_ctrls_in ; + +//===================================================================== +// Mux Function +//===================================================================== + // Debug Mux + assign debug_grp_selected = (select_bits[0:1] == 2'b00) ? dbg_group0 : + (select_bits[0:1] == 2'b01) ? dbg_group1 : + (select_bits[0:1] == 2'b10) ? dbg_group2 : + dbg_group3; + + assign debug_grp_rotated = (select_bits[5:6] == 2'b11) ? {debug_grp_selected[DBG_1FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_1FOURTH - 1]} : + (select_bits[5:6] == 2'b10) ? {debug_grp_selected[DBG_2FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_2FOURTH - 1]} : + (select_bits[5:6] == 2'b01) ? {debug_grp_selected[DBG_3FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_3FOURTH - 1]} : + debug_grp_selected[0:DBG_WIDTH - 1]; + + + assign trace_data_out[0:DBG_1FOURTH - 1] = (select_bits[7] == 1'b0) ? trace_data_in[0:DBG_1FOURTH - 1] : + debug_grp_rotated[0:DBG_1FOURTH - 1]; + + assign trace_data_out[DBG_1FOURTH:DBG_2FOURTH - 1] = (select_bits[8] == 1'b0) ? trace_data_in[DBG_1FOURTH:DBG_2FOURTH - 1] : + debug_grp_rotated[DBG_1FOURTH:DBG_2FOURTH - 1]; + + assign trace_data_out[DBG_2FOURTH:DBG_3FOURTH - 1] = (select_bits[9] == 1'b0) ? trace_data_in[DBG_2FOURTH:DBG_3FOURTH - 1] : + debug_grp_rotated[DBG_2FOURTH:DBG_3FOURTH - 1]; + + assign trace_data_out[DBG_3FOURTH:DBG_WIDTH - 1] = (select_bits[10] == 1'b0) ? trace_data_in[DBG_3FOURTH:DBG_WIDTH - 1] : + debug_grp_rotated[DBG_3FOURTH:DBG_WIDTH - 1]; + + +endmodule diff --git a/dev/verilog/trilib/tri_debug_mux8.v b/dev/verilog/trilib/tri_debug_mux8.v new file mode 100755 index 0000000..2738748 --- /dev/null +++ b/dev/verilog/trilib/tri_debug_mux8.v @@ -0,0 +1,134 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//******************************************************************** +//* +//* TITLE: Debug Mux Component (8:1 Debug Groups; 4:1 Trigger Groups) +//* +//* NAME: tri_debug_mux8.vhdl +//* +//******************************************************************** + +module tri_debug_mux8( +// vd, +// gd, + select_bits, + dbg_group0, + dbg_group1, + dbg_group2, + dbg_group3, + dbg_group4, + dbg_group5, + dbg_group6, + dbg_group7, + trace_data_in, + trace_data_out, + // Instruction Trace (HTM) Controls + coretrace_ctrls_in, + coretrace_ctrls_out +); + +// Include model build parameters + parameter DBG_WIDTH = 32; // A2o=32; A2i=88 + +//===================================================================== +// Port Definitions +//===================================================================== + + input [0:10] select_bits; + input [0:DBG_WIDTH-1] dbg_group0; + input [0:DBG_WIDTH-1] dbg_group1; + input [0:DBG_WIDTH-1] dbg_group2; + input [0:DBG_WIDTH-1] dbg_group3; + input [0:DBG_WIDTH-1] dbg_group4; + input [0:DBG_WIDTH-1] dbg_group5; + input [0:DBG_WIDTH-1] dbg_group6; + input [0:DBG_WIDTH-1] dbg_group7; + input [0:DBG_WIDTH-1] trace_data_in; + output [0:DBG_WIDTH-1] trace_data_out; + +// Instruction Trace (HTM) Control Signals: +// 0 - ac_an_coretrace_first_valid +// 1 - ac_an_coretrace_valid +// 2:3 - ac_an_coretrace_type[0:1] + input [0:3] coretrace_ctrls_in; + output [0:3] coretrace_ctrls_out; + +//===================================================================== +// Signal Declarations / Misc +//===================================================================== + parameter DBG_1FOURTH = DBG_WIDTH/4; + parameter DBG_2FOURTH = DBG_WIDTH/2; + parameter DBG_3FOURTH = 3 * DBG_WIDTH/4; + + wire [0:DBG_WIDTH-1] debug_grp_selected; + wire [0:DBG_WIDTH-1] debug_grp_rotated; + +// Don't reference unused inputs: +(* analysis_not_referenced="true" *) + wire unused; + assign unused = (|select_bits[3:4]) ; + +// Instruction Trace controls are passed-through: + assign coretrace_ctrls_out = coretrace_ctrls_in ; + +//===================================================================== +// Mux Function +//===================================================================== + // Debug Mux + + assign debug_grp_selected = (select_bits[0:2] == 3'b000) ? dbg_group0 : + (select_bits[0:2] == 3'b001) ? dbg_group1 : + (select_bits[0:2] == 3'b010) ? dbg_group2 : + (select_bits[0:2] == 3'b011) ? dbg_group3 : + (select_bits[0:2] == 3'b100) ? dbg_group4 : + (select_bits[0:2] == 3'b101) ? dbg_group5 : + (select_bits[0:2] == 3'b110) ? dbg_group6 : + dbg_group7; + + assign debug_grp_rotated = (select_bits[5:6] == 2'b11) ? {debug_grp_selected[DBG_1FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_1FOURTH - 1]} : + (select_bits[5:6] == 2'b10) ? {debug_grp_selected[DBG_2FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_2FOURTH - 1]} : + (select_bits[5:6] == 2'b01) ? {debug_grp_selected[DBG_3FOURTH:DBG_WIDTH - 1], debug_grp_selected[0:DBG_3FOURTH - 1]} : + debug_grp_selected[0:DBG_WIDTH - 1]; + + + assign trace_data_out[0:DBG_1FOURTH - 1] = (select_bits[7] == 1'b0) ? trace_data_in[0:DBG_1FOURTH - 1] : + debug_grp_rotated[0:DBG_1FOURTH - 1]; + + assign trace_data_out[DBG_1FOURTH:DBG_2FOURTH - 1] = (select_bits[8] == 1'b0) ? trace_data_in[DBG_1FOURTH:DBG_2FOURTH - 1] : + debug_grp_rotated[DBG_1FOURTH:DBG_2FOURTH - 1]; + + assign trace_data_out[DBG_2FOURTH:DBG_3FOURTH - 1] = (select_bits[9] == 1'b0) ? trace_data_in[DBG_2FOURTH:DBG_3FOURTH - 1] : + debug_grp_rotated[DBG_2FOURTH:DBG_3FOURTH - 1]; + + assign trace_data_out[DBG_3FOURTH:DBG_WIDTH - 1] = (select_bits[10] == 1'b0) ? trace_data_in[DBG_3FOURTH:DBG_WIDTH - 1] : + debug_grp_rotated[DBG_3FOURTH:DBG_WIDTH - 1]; + +endmodule diff --git a/dev/verilog/trilib/tri_direct_err_rpt.v b/dev/verilog/trilib/tri_direct_err_rpt.v new file mode 100755 index 0000000..4ad6b15 --- /dev/null +++ b/dev/verilog/trilib/tri_direct_err_rpt.v @@ -0,0 +1,57 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILENAME : tri_direct_err_rpt.v +// *! DESCRIPTION : Error Reporting Component +// *!**************************************************************** + +module tri_direct_err_rpt( + vd, + gd, + err_in, + err_out +); + parameter WIDTH = 1; // use to bundle error reporting checkers of the same exact type + inout vd; + inout gd; + + input [0:WIDTH-1] err_in; + output [0:WIDTH-1] err_out; + + // tri_direct_err_rpt + + (* analysis_not_referenced="true" *) + wire unused; + + assign unused = vd | gd; + + assign err_out = err_in; +endmodule diff --git a/dev/verilog/trilib/tri_eccchk.v b/dev/verilog/trilib/tri_eccchk.v new file mode 100755 index 0000000..82976c2 --- /dev/null +++ b/dev/verilog/trilib/tri_eccchk.v @@ -0,0 +1,284 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: XU ECC Check Macro +// +//***************************************************************************** + +module tri_eccchk( + din, + encorr, + nsyn, + corrd, + sbe, + ue +); + + parameter REGSIZE = 64; + + input [0:REGSIZE-1] din; + input encorr; + input [0:8-(64/REGSIZE)] nsyn; + output [0:REGSIZE-1] corrd; + output sbe; + output ue; + + generate // syndrome bits inverted + if (REGSIZE == 64) + begin : ecc64 + wire [0:7] syn; + wire [0:71] DcdD; // decode data bits + wire synzero; + wire sbe_int; + wire [0:3] A0to1; + wire [0:3] A2to3; + wire [0:3] A4to5; + wire [0:2] A6to7; + + // ==================================================================== + // 64 Data Bits, 8 Check bits + // Single bit error correction, Double bit error detection + // ==================================================================== + // ECC Matrix Description + // ==================================================================== + // Syn 0 111011010011101001100101101101001100101101001011001101001110100110000000 + // Syn 1 110110101011010101010101011010101010101010101010101010101101010101000000 + // Syn 2 101101100110110011001100110110011001100110011001100110011011001100100000 + // Syn 3 011100011110001111000011110001111000011110000111100001111000111100010000 + // Syn 4 000011111110000000111111110000000111111110000000011111111000000000001000 + // Syn 5 000000000001111111111111110000000000000001111111111111111000000000000100 + // Syn 6 000000000000000000000000001111111111111111111111111111111000000000000010 + // Syn 7 000000000000000000000000000000000000000000000000000000000111111100000001 + + assign syn = (~nsyn[0:7]); + + assign A0to1[0] = (~(nsyn[0] & nsyn[1] & encorr)); + assign A0to1[1] = (~(nsyn[0] & syn[1] & encorr)); + assign A0to1[2] = (~( syn[0] & nsyn[1] & encorr)); + assign A0to1[3] = (~( syn[0] & syn[1] & encorr)); + + assign A2to3[0] = (~(nsyn[2] & nsyn[3])); + assign A2to3[1] = (~(nsyn[2] & syn[3])); + assign A2to3[2] = (~( syn[2] & nsyn[3])); + assign A2to3[3] = (~( syn[2] & syn[3])); + + assign A4to5[0] = (~(nsyn[4] & nsyn[5])); + assign A4to5[1] = (~(nsyn[4] & syn[5])); + assign A4to5[2] = (~( syn[4] & nsyn[5])); + assign A4to5[3] = (~( syn[4] & syn[5])); + + assign A6to7[0] = (~(nsyn[6] & nsyn[7])); + assign A6to7[1] = (~(nsyn[6] & syn[7])); + assign A6to7[2] = (~( syn[6] & nsyn[7])); + //assign A6to7[3] = (~( syn[6] & syn[7])); + + assign DcdD[0] = (~(A0to1[3] | A2to3[2] | A4to5[0] | A6to7[0])); // 11 10 00 00 + assign DcdD[1] = (~(A0to1[3] | A2to3[1] | A4to5[0] | A6to7[0])); // 11 01 00 00 + assign DcdD[2] = (~(A0to1[2] | A2to3[3] | A4to5[0] | A6to7[0])); // 10 11 00 00 + assign DcdD[3] = (~(A0to1[1] | A2to3[3] | A4to5[0] | A6to7[0])); // 01 11 00 00 + assign DcdD[4] = (~(A0to1[3] | A2to3[0] | A4to5[2] | A6to7[0])); // 11 00 10 00 + assign DcdD[5] = (~(A0to1[2] | A2to3[2] | A4to5[2] | A6to7[0])); // 10 10 10 00 + assign DcdD[6] = (~(A0to1[1] | A2to3[2] | A4to5[2] | A6to7[0])); // 01 10 10 00 + assign DcdD[7] = (~(A0to1[2] | A2to3[1] | A4to5[2] | A6to7[0])); // 10 01 10 00 + assign DcdD[8] = (~(A0to1[1] | A2to3[1] | A4to5[2] | A6to7[0])); // 01 01 10 00 + assign DcdD[9] = (~(A0to1[0] | A2to3[3] | A4to5[2] | A6to7[0])); // 00 11 10 00 + assign DcdD[10] = (~(A0to1[3] | A2to3[3] | A4to5[2] | A6to7[0])); // 11 11 10 00 + assign DcdD[11] = (~(A0to1[3] | A2to3[0] | A4to5[1] | A6to7[0])); // 11 00 01 00 + assign DcdD[12] = (~(A0to1[2] | A2to3[2] | A4to5[1] | A6to7[0])); // 10 10 01 00 + assign DcdD[13] = (~(A0to1[1] | A2to3[2] | A4to5[1] | A6to7[0])); // 01 10 01 00 + assign DcdD[14] = (~(A0to1[2] | A2to3[1] | A4to5[1] | A6to7[0])); // 10 01 01 00 + assign DcdD[15] = (~(A0to1[1] | A2to3[1] | A4to5[1] | A6to7[0])); // 01 01 01 00 + assign DcdD[16] = (~(A0to1[0] | A2to3[3] | A4to5[1] | A6to7[0])); // 00 11 01 00 + assign DcdD[17] = (~(A0to1[3] | A2to3[3] | A4to5[1] | A6to7[0])); // 11 11 01 00 + assign DcdD[18] = (~(A0to1[2] | A2to3[0] | A4to5[3] | A6to7[0])); // 10 00 11 00 + assign DcdD[19] = (~(A0to1[1] | A2to3[0] | A4to5[3] | A6to7[0])); // 01 00 11 00 + assign DcdD[20] = (~(A0to1[0] | A2to3[2] | A4to5[3] | A6to7[0])); // 00 10 11 00 + assign DcdD[21] = (~(A0to1[3] | A2to3[2] | A4to5[3] | A6to7[0])); // 11 10 11 00 + assign DcdD[22] = (~(A0to1[0] | A2to3[1] | A4to5[3] | A6to7[0])); // 00 01 11 00 + assign DcdD[23] = (~(A0to1[3] | A2to3[1] | A4to5[3] | A6to7[0])); // 11 01 11 00 + assign DcdD[24] = (~(A0to1[2] | A2to3[3] | A4to5[3] | A6to7[0])); // 10 11 11 00 + assign DcdD[25] = (~(A0to1[1] | A2to3[3] | A4to5[3] | A6to7[0])); // 01 11 11 00 + assign DcdD[26] = (~(A0to1[3] | A2to3[0] | A4to5[0] | A6to7[2])); // 11 00 00 10 + assign DcdD[27] = (~(A0to1[2] | A2to3[2] | A4to5[0] | A6to7[2])); // 10 10 00 10 + assign DcdD[28] = (~(A0to1[1] | A2to3[2] | A4to5[0] | A6to7[2])); // 01 10 00 10 + assign DcdD[29] = (~(A0to1[2] | A2to3[1] | A4to5[0] | A6to7[2])); // 10 01 00 10 + assign DcdD[30] = (~(A0to1[1] | A2to3[1] | A4to5[0] | A6to7[2])); // 01 01 00 10 + assign DcdD[31] = (~(A0to1[0] | A2to3[3] | A4to5[0] | A6to7[2])); // 00 11 00 10 + assign DcdD[32] = (~(A0to1[3] | A2to3[3] | A4to5[0] | A6to7[2])); // 11 11 00 10 + assign DcdD[33] = (~(A0to1[2] | A2to3[0] | A4to5[2] | A6to7[2])); // 10 00 10 10 + assign DcdD[34] = (~(A0to1[1] | A2to3[0] | A4to5[2] | A6to7[2])); // 01 00 10 10 + assign DcdD[35] = (~(A0to1[0] | A2to3[2] | A4to5[2] | A6to7[2])); // 00 10 10 10 + assign DcdD[36] = (~(A0to1[3] | A2to3[2] | A4to5[2] | A6to7[2])); // 11 10 10 10 + assign DcdD[37] = (~(A0to1[0] | A2to3[1] | A4to5[2] | A6to7[2])); // 00 01 10 10 + assign DcdD[38] = (~(A0to1[3] | A2to3[1] | A4to5[2] | A6to7[2])); // 11 01 10 10 + assign DcdD[39] = (~(A0to1[2] | A2to3[3] | A4to5[2] | A6to7[2])); // 10 11 10 10 + assign DcdD[40] = (~(A0to1[1] | A2to3[3] | A4to5[2] | A6to7[2])); // 01 11 10 10 + assign DcdD[41] = (~(A0to1[2] | A2to3[0] | A4to5[1] | A6to7[2])); // 10 00 01 10 + assign DcdD[42] = (~(A0to1[1] | A2to3[0] | A4to5[1] | A6to7[2])); // 01 00 01 10 + assign DcdD[43] = (~(A0to1[0] | A2to3[2] | A4to5[1] | A6to7[2])); // 00 10 01 10 + assign DcdD[44] = (~(A0to1[3] | A2to3[2] | A4to5[1] | A6to7[2])); // 11 10 01 10 + assign DcdD[45] = (~(A0to1[0] | A2to3[1] | A4to5[1] | A6to7[2])); // 00 01 01 10 + assign DcdD[46] = (~(A0to1[3] | A2to3[1] | A4to5[1] | A6to7[2])); // 11 01 01 10 + assign DcdD[47] = (~(A0to1[2] | A2to3[3] | A4to5[1] | A6to7[2])); // 10 11 01 10 + assign DcdD[48] = (~(A0to1[1] | A2to3[3] | A4to5[1] | A6to7[2])); // 01 11 01 10 + assign DcdD[49] = (~(A0to1[0] | A2to3[0] | A4to5[3] | A6to7[2])); // 00 00 11 10 + assign DcdD[50] = (~(A0to1[3] | A2to3[0] | A4to5[3] | A6to7[2])); // 11 00 11 10 + assign DcdD[51] = (~(A0to1[2] | A2to3[2] | A4to5[3] | A6to7[2])); // 10 10 11 10 + assign DcdD[52] = (~(A0to1[1] | A2to3[2] | A4to5[3] | A6to7[2])); // 01 10 11 10 + assign DcdD[53] = (~(A0to1[2] | A2to3[1] | A4to5[3] | A6to7[2])); // 10 01 11 10 + assign DcdD[54] = (~(A0to1[1] | A2to3[1] | A4to5[3] | A6to7[2])); // 01 01 11 10 + assign DcdD[55] = (~(A0to1[0] | A2to3[3] | A4to5[3] | A6to7[2])); // 00 11 11 10 + assign DcdD[56] = (~(A0to1[3] | A2to3[3] | A4to5[3] | A6to7[2])); // 11 11 11 10 + assign DcdD[57] = (~(A0to1[3] | A2to3[0] | A4to5[0] | A6to7[1])); // 11 00 00 01 + assign DcdD[58] = (~(A0to1[2] | A2to3[2] | A4to5[0] | A6to7[1])); // 10 10 00 01 + assign DcdD[59] = (~(A0to1[1] | A2to3[2] | A4to5[0] | A6to7[1])); // 01 10 00 01 + assign DcdD[60] = (~(A0to1[2] | A2to3[1] | A4to5[0] | A6to7[1])); // 10 01 00 01 + assign DcdD[61] = (~(A0to1[1] | A2to3[1] | A4to5[0] | A6to7[1])); // 01 01 00 01 + assign DcdD[62] = (~(A0to1[0] | A2to3[3] | A4to5[0] | A6to7[1])); // 00 11 00 01 + assign DcdD[63] = (~(A0to1[3] | A2to3[3] | A4to5[0] | A6to7[1])); // 11 11 00 01 + assign DcdD[64] = (~(A0to1[2] | A2to3[0] | A4to5[0] | A6to7[0])); // 10 00 00 00 + assign DcdD[65] = (~(A0to1[1] | A2to3[0] | A4to5[0] | A6to7[0])); // 01 00 00 00 + assign DcdD[66] = (~(A0to1[0] | A2to3[2] | A4to5[0] | A6to7[0])); // 00 10 00 00 + assign DcdD[67] = (~(A0to1[0] | A2to3[1] | A4to5[0] | A6to7[0])); // 00 01 00 00 + assign DcdD[68] = (~(A0to1[0] | A2to3[0] | A4to5[2] | A6to7[0])); // 00 00 10 00 + assign DcdD[69] = (~(A0to1[0] | A2to3[0] | A4to5[1] | A6to7[0])); // 00 00 01 00 + assign DcdD[70] = (~(A0to1[0] | A2to3[0] | A4to5[0] | A6to7[2])); // 00 00 00 10 + assign DcdD[71] = (~(A0to1[0] | A2to3[0] | A4to5[0] | A6to7[1])); // 00 00 00 01 + assign synzero = (~(A0to1[0] | A2to3[0] | A4to5[0] | A6to7[0])); // 00 00 00 00 + + assign corrd[0:63] = din[0:63] ^ DcdD[0:63]; + + assign sbe_int = (DcdD[0:71] != {72{1'b0}}) ? 1'b1 : + 1'b0; + assign sbe = sbe_int; + assign ue = (~sbe_int) & (~synzero) & encorr; + end + endgenerate + + generate // syndrome bits inverted + if (REGSIZE == 32) + begin : ecc32 + wire [0:6] syn; + wire [0:38] DcdD; // decode data bits + wire synzero; + wire sbe_int; + wire [0:3] A0to1; + wire [0:3] A2to3; + wire [0:7] A4to6; + + // ==================================================================== + // 32 Data Bits, 7 Check bits + // Single bit error correction, Double bit error detection + // ==================================================================== + // ECC Matrix Description + // ==================================================================== + // Syn 0 111011010011101001100101101101001000000 + // Syn 1 110110101011010101010101011010100100000 + // Syn 2 101101100110110011001100110110010010000 + // Syn 3 011100011110001111000011110001110001000 + // Syn 4 000011111110000000111111110000000000100 + // Syn 5 000000000001111111111111110000000000010 + // Syn 6 000000000000000000000000001111110000001 + + assign syn = (~nsyn[0:6]); + + assign A0to1[0] = (~(nsyn[0] & nsyn[1] & encorr)); + assign A0to1[1] = (~(nsyn[0] & syn[1] & encorr)); + assign A0to1[2] = (~( syn[0] & nsyn[1] & encorr)); + assign A0to1[3] = (~( syn[0] & syn[1] & encorr)); + + assign A2to3[0] = (~(nsyn[2] & nsyn[3])); + assign A2to3[1] = (~(nsyn[2] & syn[3])); + assign A2to3[2] = (~( syn[2] & nsyn[3])); + assign A2to3[3] = (~( syn[2] & syn[3])); + + assign A4to6[0] = (~(nsyn[4] & nsyn[5] & nsyn[6])); + assign A4to6[1] = (~(nsyn[4] & nsyn[5] & syn[6])); + assign A4to6[2] = (~(nsyn[4] & syn[5] & nsyn[6])); + assign A4to6[3] = (~(nsyn[4] & syn[5] & syn[6])); + assign A4to6[4] = (~( syn[4] & nsyn[5] & nsyn[6])); + assign A4to6[5] = (~( syn[4] & nsyn[5] & syn[6])); + assign A4to6[6] = (~( syn[4] & syn[5] & nsyn[6])); + assign A4to6[7] = (~( syn[4] & syn[5] & syn[6])); + + assign DcdD[0] = (~(A0to1[3] | A2to3[2] | A4to6[0])); // 11 10 000 + assign DcdD[1] = (~(A0to1[3] | A2to3[1] | A4to6[0])); // 11 01 000 + assign DcdD[2] = (~(A0to1[2] | A2to3[3] | A4to6[0])); // 10 11 000 + assign DcdD[3] = (~(A0to1[1] | A2to3[3] | A4to6[0])); // 01 11 000 + assign DcdD[4] = (~(A0to1[3] | A2to3[0] | A4to6[4])); // 11 00 100 + assign DcdD[5] = (~(A0to1[2] | A2to3[2] | A4to6[4])); // 10 10 100 + assign DcdD[6] = (~(A0to1[1] | A2to3[2] | A4to6[4])); // 01 10 100 + assign DcdD[7] = (~(A0to1[2] | A2to3[1] | A4to6[4])); // 10 01 100 + assign DcdD[8] = (~(A0to1[1] | A2to3[1] | A4to6[4])); // 01 01 100 + assign DcdD[9] = (~(A0to1[0] | A2to3[3] | A4to6[4])); // 00 11 100 + assign DcdD[10] = (~(A0to1[3] | A2to3[3] | A4to6[4])); // 11 11 100 + assign DcdD[11] = (~(A0to1[3] | A2to3[0] | A4to6[2])); // 11 00 010 + assign DcdD[12] = (~(A0to1[2] | A2to3[2] | A4to6[2])); // 10 10 010 + assign DcdD[13] = (~(A0to1[1] | A2to3[2] | A4to6[2])); // 01 10 010 + assign DcdD[14] = (~(A0to1[2] | A2to3[1] | A4to6[2])); // 10 01 010 + assign DcdD[15] = (~(A0to1[1] | A2to3[1] | A4to6[2])); // 01 01 010 + assign DcdD[16] = (~(A0to1[0] | A2to3[3] | A4to6[2])); // 00 11 010 + assign DcdD[17] = (~(A0to1[3] | A2to3[3] | A4to6[2])); // 11 11 010 + assign DcdD[18] = (~(A0to1[2] | A2to3[0] | A4to6[6])); // 10 00 110 + assign DcdD[19] = (~(A0to1[1] | A2to3[0] | A4to6[6])); // 01 00 110 + assign DcdD[20] = (~(A0to1[0] | A2to3[2] | A4to6[6])); // 00 10 110 + assign DcdD[21] = (~(A0to1[3] | A2to3[2] | A4to6[6])); // 11 10 110 + assign DcdD[22] = (~(A0to1[0] | A2to3[1] | A4to6[6])); // 00 01 110 + assign DcdD[23] = (~(A0to1[3] | A2to3[1] | A4to6[6])); // 11 01 110 + assign DcdD[24] = (~(A0to1[2] | A2to3[3] | A4to6[6])); // 10 11 110 + assign DcdD[25] = (~(A0to1[1] | A2to3[3] | A4to6[6])); // 01 11 110 + assign DcdD[26] = (~(A0to1[3] | A2to3[0] | A4to6[1])); // 11 00 001 + assign DcdD[27] = (~(A0to1[2] | A2to3[2] | A4to6[1])); // 10 10 001 + assign DcdD[28] = (~(A0to1[1] | A2to3[2] | A4to6[1])); // 01 10 001 + assign DcdD[29] = (~(A0to1[2] | A2to3[1] | A4to6[1])); // 10 01 001 + assign DcdD[30] = (~(A0to1[1] | A2to3[1] | A4to6[1])); // 01 01 001 + assign DcdD[31] = (~(A0to1[0] | A2to3[3] | A4to6[1])); // 00 11 001 + assign DcdD[32] = (~(A0to1[2] | A2to3[0] | A4to6[0])); // 10 00 000 + assign DcdD[33] = (~(A0to1[1] | A2to3[0] | A4to6[0])); // 01 00 000 + assign DcdD[34] = (~(A0to1[0] | A2to3[2] | A4to6[0])); // 00 10 000 + assign DcdD[35] = (~(A0to1[0] | A2to3[1] | A4to6[0])); // 00 01 000 + assign DcdD[36] = (~(A0to1[0] | A2to3[0] | A4to6[4])); // 00 00 100 + assign DcdD[37] = (~(A0to1[0] | A2to3[0] | A4to6[2])); // 00 00 010 + assign DcdD[38] = (~(A0to1[0] | A2to3[0] | A4to6[1])); // 00 00 001 + assign synzero = (~(A0to1[0] | A2to3[0] | A4to6[0])); // 00 00 000 + + assign corrd[0:31] = din[0:31] ^ DcdD[0:31]; + + assign sbe_int = (DcdD[0:38] != {39{1'b0}}) ? 1'b1 : + 1'b0; + assign sbe = sbe_int; + assign ue = (~sbe_int) & (~synzero) & encorr; + + //mark_unused(A4to6(3)); + //mark_unused(A4to6(5)); + //mark_unused(A4to6(7)); + end + endgenerate +endmodule diff --git a/dev/verilog/trilib/tri_eccgen.v b/dev/verilog/trilib/tri_eccgen.v new file mode 100755 index 0000000..e6199cd --- /dev/null +++ b/dev/verilog/trilib/tri_eccgen.v @@ -0,0 +1,145 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: XU ECC Generation Macro +// +//***************************************************************************** + +module tri_eccgen( + din, + syn +); + parameter REGSIZE = 64; + input [0:REGSIZE+8-(64/REGSIZE)] din; + output [0:8-(64/REGSIZE)] syn; + + generate // syndrome bits inverted + if (REGSIZE == 64) + begin : ecc64 + wire [0:71] e; + wire [0:22] l1term; + + // ==================================================================== + // 64 data bits, 8 check bits + // single bit error correction, double bit error detection + // ==================================================================== + // ecc matrix description + // ==================================================================== + // syn 0 111011010011101001100101101101001100101101001011001101001110100110000000 + // syn 1 110110101011010101010101011010101010101010101010101010101101010101000000 + // syn 2 101101100110110011001100110110011001100110011001100110011011001100100000 + // syn 3 011100011110001111000011110001111000011110000111100001111000111100010000 + // syn 4 000011111110000000111111110000000111111110000000011111111000000000001000 + // syn 5 000000000001111111111111110000000000000001111111111111111000000000000100 + // syn 6 000000000000000000000000001111111111111111111111111111111000000000000010 + // syn 7 000000000000000000000000000000000000000000000000000000000111111100000001 + + assign e[0:71] = din[0:71]; + + assign l1term[0] = e[0] ^ e[10] ^ e[17] ^ e[21] ^ e[32] ^ e[36] ^ e[44] ^ e[56]; + assign l1term[1] = e[22] ^ e[23] ^ e[24] ^ e[25] ^ e[53] ^ e[54] ^ e[55] ^ e[56]; + assign l1term[2] = e[1] ^ e[4] ^ e[11] ^ e[23] ^ e[26] ^ e[38] ^ e[46] ^ e[50]; + assign l1term[3] = e[2] ^ e[5] ^ e[12] ^ e[24] ^ e[27] ^ e[39] ^ e[47] ^ e[51]; + assign l1term[4] = e[3] ^ e[6] ^ e[13] ^ e[25] ^ e[28] ^ e[40] ^ e[48] ^ e[52]; + assign l1term[5] = e[7] ^ e[8] ^ e[9] ^ e[10] ^ e[37] ^ e[38] ^ e[39] ^ e[40]; + assign l1term[6] = e[14] ^ e[15] ^ e[16] ^ e[17] ^ e[45] ^ e[46] ^ e[47] ^ e[48]; + assign l1term[7] = e[18] ^ e[19] ^ e[20] ^ e[21] ^ e[49] ^ e[50] ^ e[51] ^ e[52]; + assign l1term[8] = e[7] ^ e[14] ^ e[18] ^ e[29] ^ e[33] ^ e[41] ^ e[53] ^ e[57]; + assign l1term[9] = e[58] ^ e[60] ^ e[63] ^ e[64]; + assign l1term[10] = e[8] ^ e[15] ^ e[19] ^ e[30] ^ e[34] ^ e[42] ^ e[54] ^ e[57]; + assign l1term[11] = e[59] ^ e[61] ^ e[63] ^ e[65]; + assign l1term[12] = e[9] ^ e[16] ^ e[20] ^ e[31] ^ e[35] ^ e[43] ^ e[55] ^ e[58]; + assign l1term[13] = e[59] ^ e[62] ^ e[63] ^ e[66]; + assign l1term[14] = e[1] ^ e[2] ^ e[3] ^ e[29] ^ e[30] ^ e[31] ^ e[32] ^ e[60]; + assign l1term[15] = e[61] ^ e[62] ^ e[63] ^ e[67]; + assign l1term[16] = e[4] ^ e[5] ^ e[6] ^ e[33] ^ e[34] ^ e[35] ^ e[36] ^ e[68]; + assign l1term[17] = e[11] ^ e[12] ^ e[13] ^ e[41] ^ e[42] ^ e[43] ^ e[44] ^ e[69]; + assign l1term[18] = e[26] ^ e[27] ^ e[28] ^ e[29] ^ e[30] ^ e[31] ^ e[32] ^ e[33]; + assign l1term[19] = e[34] ^ e[35] ^ e[36] ^ e[37] ^ e[38] ^ e[39] ^ e[40] ^ e[41]; + assign l1term[20] = e[42] ^ e[43] ^ e[44] ^ e[45] ^ e[46] ^ e[47] ^ e[48] ^ e[49]; + assign l1term[21] = e[50] ^ e[51] ^ e[52] ^ e[53] ^ e[54] ^ e[55] ^ e[56] ^ e[70]; + assign l1term[22] = e[57] ^ e[58] ^ e[59] ^ e[60] ^ e[61] ^ e[62] ^ e[63] ^ e[71]; + assign syn[0] = l1term[0] ^ l1term[2] ^ l1term[3] ^ l1term[8] ^ l1term[9]; + assign syn[1] = l1term[0] ^ l1term[2] ^ l1term[4] ^ l1term[10] ^ l1term[11]; + assign syn[2] = l1term[0] ^ l1term[3] ^ l1term[4] ^ l1term[12] ^ l1term[13]; + assign syn[3] = l1term[1] ^ l1term[5] ^ l1term[6] ^ l1term[14] ^ l1term[15]; + assign syn[4] = l1term[1] ^ l1term[5] ^ l1term[7] ^ l1term[16]; + assign syn[5] = l1term[1] ^ l1term[6] ^ l1term[7] ^ l1term[17]; + assign syn[6] = l1term[18] ^ l1term[19] ^ l1term[20] ^ l1term[21]; + assign syn[7] = l1term[22]; + end + endgenerate + + generate // syndrome bits inverted + if (REGSIZE == 32) + begin : ecc32 + wire [0:38] e; + wire [0:13] l1term; + + // ==================================================================== + // 32 Data Bits, 7 Check bits + // Single bit error correction, Double bit error detection + // ==================================================================== + // ECC Matrix Description + // ==================================================================== + // Syn 0 111011010011101001100101101101001000000 + // Syn 1 110110101011010101010101011010100100000 + // Syn 2 101101100110110011001100110110010010000 + // Syn 3 011100011110001111000011110001110001000 + // Syn 4 000011111110000000111111110000000000100 + // Syn 5 000000000001111111111111110000000000010 + // Syn 6 000000000000000000000000001111110000001 + + assign e[0:38] = din[0:38]; + + assign l1term[0] = e[0] ^ e[1] ^ e[4] ^ e[10] ^ e[11] ^ e[17] ^ e[21] ^ e[23]; + assign l1term[1] = e[2] ^ e[3] ^ e[9] ^ e[10] ^ e[16] ^ e[17] ^ e[24] ^ e[25]; + assign l1term[2] = e[18] ^ e[19] ^ e[20] ^ e[21] ^ e[22] ^ e[23] ^ e[24] ^ e[25]; + assign l1term[3] = e[2] ^ e[5] ^ e[7] ^ e[12] ^ e[14] ^ e[18] ^ e[24] ^ e[26]; + assign l1term[4] = e[27] ^ e[29] ^ e[32]; + assign l1term[5] = e[3] ^ e[6] ^ e[8] ^ e[13] ^ e[15] ^ e[19] ^ e[25] ^ e[26]; + assign l1term[6] = e[28] ^ e[30] ^ e[33]; + assign l1term[7] = e[0] ^ e[5] ^ e[6] ^ e[12] ^ e[13] ^ e[20] ^ e[21] ^ e[27]; + assign l1term[8] = e[28] ^ e[31] ^ e[34]; + assign l1term[9] = e[1] ^ e[7] ^ e[8] ^ e[14] ^ e[15] ^ e[22] ^ e[23] ^ e[29]; + assign l1term[10] = e[30] ^ e[31] ^ e[35]; + assign l1term[11] = e[4] ^ e[5] ^ e[6] ^ e[7] ^ e[8] ^ e[9] ^ e[10] ^ e[36]; + assign l1term[12] = e[11] ^ e[12] ^ e[13] ^ e[14] ^ e[15] ^ e[16] ^ e[17] ^ e[37]; + assign l1term[13] = e[26] ^ e[27] ^ e[28] ^ e[29] ^ e[30] ^ e[31] ^ e[38]; + assign syn[0] = l1term[0] ^ l1term[3] ^ l1term[4]; + assign syn[1] = l1term[0] ^ l1term[5] ^ l1term[6]; + assign syn[2] = l1term[1] ^ l1term[7] ^ l1term[8]; + assign syn[3] = l1term[1] ^ l1term[9] ^ l1term[10]; + assign syn[4] = l1term[2] ^ l1term[11]; + assign syn[5] = l1term[2] ^ l1term[12]; + assign syn[6] = l1term[13]; + end + endgenerate +endmodule diff --git a/dev/verilog/trilib/tri_err_rpt.v b/dev/verilog/trilib/tri_err_rpt.v new file mode 100755 index 0000000..19f2e46 --- /dev/null +++ b/dev/verilog/trilib/tri_err_rpt.v @@ -0,0 +1,142 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILENAME : tri_err_rpt.v +// *! DESCRIPTION : Error Reporting Component +// *!**************************************************************** + +`include "tri.vh" + +module tri_err_rpt( + vd, + gd, + err_d1clk, + err_d2clk, + err_lclk, + err_scan_in, + err_scan_out, + mode_dclk, + mode_lclk, + mode_scan_in, + mode_scan_out, + err_in, + err_out, + hold_out, + mask_out +); + parameter WIDTH = 1; // number of errors of the same type + parameter MASK_RESET_VALUE = 1'b0; // use to set default/flush value for mask bits + parameter INLINE = 1'b0; // make hold latch be inline; err_out is sticky -- default to shadow + parameter SHARE_MASK = 1'b0; // PERMISSION NEEDED for true + // used for WIDTH >1 to reduce area of mask (common error disable) + parameter USE_NLATS = 1'b0; // only necessary in standby area to be able to reset to init value + parameter NEEDS_SRESET = 1; // for inferred latches + + inout vd; + inout gd; + input err_d1clk; // caution1: if lcb uses powersavings, errors must always get reported + input err_d2clk; // caution2: if use_nlats is used these are also the clocks for the mask latches + input [0:`NCLK_WIDTH-1] err_lclk; // caution2: hence these have to be the mode clocks + // caution2: and all bits in the "func" chain have to be connected to the mode chain + // error scan chain (func or mode) + input [0:WIDTH-1] err_scan_in; // NOTE: connected to mode or func ring + output [0:WIDTH-1] err_scan_out; + // clock gateable mode clocks + input mode_dclk; + input [0:`NCLK_WIDTH-1] mode_lclk; + // mode scan chain + input [0:WIDTH-1] mode_scan_in; + output [0:WIDTH-1] mode_scan_out; + + input [0:WIDTH-1] err_in; + output [0:WIDTH-1] err_out; + + output [0:WIDTH-1] hold_out; // sticky error hold latch for trap usage + output [0:WIDTH-1] mask_out; + + // tri_err_rpt + + parameter [0:WIDTH-1] mask_initv = MASK_RESET_VALUE; + wire [0:WIDTH-1] hold_in; + wire [0:WIDTH-1] hold_lt; + wire [0:WIDTH-1] mask_lt; + (* analysis_not_referenced="true" *) + wire unused; + wire [0:WIDTH-1] unused_q_b; + // hold latches + assign hold_in = err_in | hold_lt; + + tri_nlat_scan #(.WIDTH(WIDTH), .NEEDS_SRESET(NEEDS_SRESET)) + hold( + .vd(vd), + .gd(gd), + .d1clk(err_d1clk), + .d2clk(err_d2clk), + .lclk(err_lclk), + .scan_in(err_scan_in[0:WIDTH - 1]), + .scan_out(err_scan_out[0:WIDTH - 1]), + .din(hold_in), + .q(hold_lt), + .q_b(unused_q_b) + ); + + generate + begin + // mask + if (SHARE_MASK == 1'b0) + begin : m + assign mask_lt = mask_initv; + end + if (SHARE_MASK == 1'b1) + begin : sm + assign mask_lt = {WIDTH{MASK_RESET_VALUE[0]}}; + end + + assign mode_scan_out = {WIDTH{1'b0}}; + + // assign outputs + assign hold_out = hold_lt; + assign mask_out = mask_lt; + + if (INLINE == 1'b1) + begin : inline_hold + assign err_out = hold_lt & (~mask_lt); + end + + if (INLINE == 1'b0) + begin : side_hold + assign err_out = err_in & (~mask_lt); + end + + assign unused = | {mode_dclk, mode_lclk, mode_scan_in, unused_q_b}; + end + endgenerate +endmodule diff --git a/dev/verilog/trilib/tri_event_mux1t.v b/dev/verilog/trilib/tri_event_mux1t.v new file mode 100755 index 0000000..31f85b8 --- /dev/null +++ b/dev/verilog/trilib/tri_event_mux1t.v @@ -0,0 +1,166 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//******************************************************************** +//* +//* TITLE: Performance Event Mux Component - 1 Thread; 4 bits +//* +//* NAME: tri_event_mux1t.v +//* +//******************************************************************** + +module tri_event_mux1t( + vd, + gd, + select_bits, + unit_events_in, + event_bus_in, + event_bus_out +); + parameter EVENTS_IN = 32; // Valid Settings: 16; 32; 64 + parameter EVENTS_OUT = 4; // Valid Settings: 4 outputs per event mux + // Select bit size depends on total events: 16 events=16, 32 events=20; 64 events=24 + input [0:((EVENTS_IN/32+4)*EVENTS_OUT)-1] select_bits; + + input [1:EVENTS_IN-1] unit_events_in; + + input [0:EVENTS_OUT-1] event_bus_in; + + output [0:EVENTS_OUT-1] event_bus_out; + + inout vd; + + inout gd; + + +//===================================================================== +// Signal and Function Declarations +//===================================================================== +// Constants used to split up select_bits for the decoder +// Mux Size: 16 32 64 + parameter INCR = EVENTS_IN/32 + 4; // INCR: 4 5 6 + + // For each output bit decode select bits to select an input mux to use. + wire [0:EVENTS_OUT*EVENTS_IN-1] inMuxDec; + wire [0:EVENTS_OUT*EVENTS_IN-1] inMuxOut; + +// Paramaterized decoder function - decode mux value based on input select_bits +// Input size based on EVENTS_IN parameter: 16=4, 32=5, 64=6 + function [0:EVENTS_IN-1] decode_a; + input [0:INCR-1] decode_input; + //(* analysis_not_referenced="true" *) + integer i; + + for(i=0; i s_neg(0) , --i-- + // SX => s_x(0) , --i-- + // SX2 => s_x2(0) , --i-- + // X => tidn , --i-- ******** + // RIGHT => left_xtd_2(0) , --i-- [n+1] + // LEFT => left_xtd_2(0) , --o-- [n] + // Q => xtd_2_sub(0)); --o-- + + + tri_fu_mul_bthrow bm_00( + .s_neg(s_neg[0]), //i-- + .s_x(s_x[0]), //i-- + .s_x2(s_x2[0]), //i-- + .x(c_frac[0:53]), //i-- + .q(pp0_00[4:58]), //o-- + .hot_one(hot_one_din) //o-- + ); + + //-------------------------------------------------------------------------- + + assign pp0_01[4] = tiup; + assign pp0_01[5] = xtd_2_add[1]; + + assign xtd_2_add[1] = (~(s_neg[1] & (s_x[1] | s_x2[1]))); + // sx_01_2: entity BTHMX_X1_A12TH port map ( + // SNEG => s_neg(1) , --i-- + // SX => s_x(1) , --i-- + // SX2 => s_x2(1) , --i-- + // X => tidn , --i-- ******** + // RIGHT => left_xtd_2(1) , --i-- [n+1] + // LEFT => left_xtd_2(1) , --o-- [n] + // Q => xtd_2_sub(1)); --o-- + + + tri_fu_mul_bthrow bm_01( + .s_neg(s_neg[1]), //i-- + .s_x(s_x[1]), //i-- + .s_x2(s_x2[1]), //i-- + .x(c_frac[0:53]), //i-- + .q(pp0_01[6:60]), //o-- + .hot_one(pp0_00[60]) //i-- + ); + assign pp0_00[59] = tidn; + + //-------------------------------------------------------------------------- + + assign pp0_02[6] = tiup; + assign pp0_02[7] = xtd_2_add[2]; + + assign xtd_2_add[2] = (~(s_neg[2] & (s_x[2] | s_x2[2]))); + // sx_02_2: entity BTHMX_X1_A12TH port map ( + // SNEG => s_neg(2) , --i-- + // SX => s_x(2) , --i-- + // SX2 => s_x2(2) , --i-- + // X => tidn , --i-- ******** + // RIGHT => left_xtd_2(2) , --i-- [n+1] + // LEFT => left_xtd_2(2) , --o-- [n] + // Q => xtd_2_sub(2)); --o-- + + + tri_fu_mul_bthrow bm_02( + .s_neg(s_neg[2]), //i-- + .s_x(s_x[2]), //i-- + .s_x2(s_x2[2]), //i-- + .x(c_frac[0:53]), //i-- + .q(pp0_02[8:62]), //o-- + .hot_one(pp0_01[62]) //i-- + ); + assign pp0_01[61] = tidn; + + //-------------------------------------------------------------------------- + + assign pp0_03[8] = tiup; + assign pp0_03[9] = xtd_2_add[3]; + + assign xtd_2_add[3] = (~(s_neg[3] & (s_x[3] | s_x2[3]))); + // sx_03_2: entity BTHMX_X1_A12TH port map ( + // SNEG => s_neg(3) , --i-- + // SX => s_x(3) , --i-- + // SX2 => s_x2(3) , --i-- + // X => tidn , --i-- ******** + // RIGHT => left_xtd_2(3) , --i-- [n+1] + // LEFT => left_xtd_2(3) , --o-- [n] + // Q => xtd_2_sub(3)); --o-- + + + tri_fu_mul_bthrow bm_03( + .s_neg(s_neg[3]), //i-- + .s_x(s_x[3]), //i-- + .s_x2(s_x2[3]), //i-- + .x(c_frac[0:53]), //i-- + .q(pp0_03[10:64]), //o-- + .hot_one(pp0_02[64]) //i-- + ); + assign pp0_02[63] = tidn; + + //-------------------------------------------------------------------------- + + assign pp0_04[10] = tiup; + assign pp0_04[11] = xtd_2_add[4]; + + assign xtd_2_add[4] = (~(s_neg[4] & (s_x[4] | s_x2[4]))); + // sx_04_2: entity BTHMX_X1_A12TH port map ( + // SNEG => s_neg(4) , --i-- + // SX => s_x(4) , --i-- + // SX2 => s_x2(4) , --i-- + // X => tidn , --i-- ******** + // RIGHT => left_xtd_2(4) , --i-- [n+1] + // LEFT => left_xtd_2(4) , --o-- [n] + // Q => xtd_2_sub(4)); --o-- + + + tri_fu_mul_bthrow bm_04( + .s_neg(s_neg[4]), //i-- + .s_x(s_x[4]), //i-- + .s_x2(s_x2[4]), //i-- + .x(c_frac[0:53]), //i-- + .q(pp0_04[12:66]), //o-- + .hot_one(pp0_03[66]) //i-- + ); + assign pp0_03[65] = tidn; + + //-------------------------------------------------------------------------- + + assign pp0_05[12] = tiup; + assign pp0_05[13] = xtd_2_add[5]; + + assign xtd_2_add[5] = (~(s_neg[5] & (s_x[5] | s_x2[5]))); + // sx_05_2: entity BTHMX_X1_A12TH port map ( + // SNEG => s_neg(5) , --i-- + // SX => s_x(5) , --i-- + // SX2 => s_x2(5) , --i-- + // X => tidn , --i-- ******** + // RIGHT => left_xtd_2(5) , --i-- [n+1] + // LEFT => left_xtd_2(5) , --o-- [n] + // Q => xtd_2_sub(5)); --o-- + + + tri_fu_mul_bthrow bm_05( + .s_neg(s_neg[5]), //i-- + .s_x(s_x[5]), //i-- + .s_x2(s_x2[5]), //i-- + .x(c_frac[0:53]), //i-- + .q(pp0_05[14:68]), //o-- + .hot_one(pp0_04[68]) //i-- + ); + assign pp0_04[67] = tidn; + + //-------------------------------------------------------------------------- + + assign pp0_06[14] = tiup; + assign pp0_06[15] = xtd_2_add[6]; + + assign xtd_2_add[6] = (~(s_neg[6] & (s_x[6] | s_x2[6]))); + // sx_06_2: entity BTHMX_X1_A12TH port map ( + // SNEG => s_neg(6) , --i-- + // SX => s_x(6) , --i-- + // SX2 => s_x2(6) , --i-- + // X => tidn , --i-- ******** + // RIGHT => left_xtd_2(6) , --i-- [n+1] + // LEFT => left_xtd_2(6) , --o-- [n] + // Q => xtd_2_sub(6)); --o-- + + + tri_fu_mul_bthrow bm_06( + .s_neg(s_neg[6]), //i-- + .s_x(s_x[6]), //i-- + .s_x2(s_x2[6]), //i-- + .x(c_frac[0:53]), //i-- + .q(pp0_06[16:70]), //o-- + .hot_one(pp0_05[70]) //i-- + ); + assign pp0_05[69] = tidn; + + //-------------------------------------------------------------------------- + + assign pp0_07[16] = tiup; + assign pp0_07[17] = xtd_2_add[7]; + + assign xtd_2_add[7] = (~(s_neg[7] & (s_x[7] | s_x2[7]))); + // sx_07_2: entity BTHMX_X1_A12TH port map ( + // SNEG => s_neg(7) , --i-- + // SX => s_x(7) , --i-- + // SX2 => s_x2(7) , --i-- + // X => tidn , --i-- ******** + // RIGHT => left_xtd_2(7) , --i-- [n+1] + // LEFT => left_xtd_2(7) , --o-- [n] + // Q => xtd_2_sub(7)); --o-- + + + tri_fu_mul_bthrow bm_07( + .s_neg(s_neg[7]), //i-- + .s_x(s_x[7]), //i-- + .s_x2(s_x2[7]), //i-- + .x(c_frac[0:53]), //i-- + .q(pp0_07[18:72]), //o-- + .hot_one(pp0_06[72]) //i-- + ); + assign pp0_06[71] = tidn; + + //-------------------------------------------------------------------------- + // LSB ROW OF LSB 9:2 HAS unique sign extension + //-------------------------------------------------------------------------- + + // to get a "1" ctl_s=1 ctl_a=1 + // to get a "0" ctl_s=0 ctl_a=0 + // to get a "A" ctl_s=0 ctl_a=1 + // to get a "S" ctl_s=1 ctl_a=0 + + // ctl_lsb_92_b <= not ctl_lsb_92; + + ///####################################################################### + ///# this is the unique part for the 3 version of tri_fu_mul_92 + ///# MSB/LSB sx_08_0 sx_08_1 sx_08_2 + ///# mul_92_0 10 '0' '1' Add + ///# mul_92_1 00 '0' '1' Add + ///# mul_92_2 01 Add Sub Sub + ///####################################################################### + + generate + if (inst == 0) + begin : g0 + //inst.0 + assign pp0_08[17] = tidn; // inst.0 + assign pp0_08[18] = tiup; // inst.0 + assign pp0_08[19] = (~(s_neg[8] & (s_x[8] | s_x2[8]))); // inst.0 + end + endgenerate + + generate + if (inst == 1) + begin : g1 + //inst.0 + assign pp0_08[17] = tidn; // inst.0 + assign pp0_08[18] = tiup; // inst.0 + assign pp0_08[19] = (~(s_neg[8] & (s_x[8] | s_x2[8]))); // inst.0 + end + endgenerate + + generate + if (inst == 2) + begin : g2 + //inst.2 + //inst.2 + //inst.2 + assign pp0_08[17] = (~(s_neg[8] & (s_x[8] | s_x2[8]))); // inst.2 + assign pp0_08[18] = (s_neg[8] & (s_x[8] | s_x2[8])); // inst.2 + assign pp0_08[19] = (s_neg[8] & (s_x[8] | s_x2[8])); // inst.2 + end + endgenerate + + + tri_fu_mul_bthrow bm_08( + .s_neg(s_neg[8]), //i-- + .s_x(s_x[8]), //i-- + .s_x2(s_x2[8]), //i-- + .x(c_frac[0:53]), //i-- + .q(pp0_08[20:74]), //o-- + .hot_one(pp0_07[74]) //i-- + ); + assign pp0_07[73] = tidn; + + ////################################################## + ////# Compressor Level 1 + ////################################################## + + ////########################################################### + ////# LEON CHART + ////########################################################### + // o: no logic done on the signal + // c: carry + // u: sum + // h: hot1 + // H: hot 1 latched + // s: sign + // a: ! sign + // d: data from the booth muxes + // wWW: 01a / ass + // Kz: 1a / 00 + + ////# 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111111 + ////# 0000000000111111111122222222223333333333444444444455555555556666666666777777777788888888889999999999000000000 + ////# 0123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678 + ////# 0 ..zzddddddddddddddddddddddddddddddddddddddddddddddddddddddd0h................................................ + ////# 1 ....1addddddddddddddddddddddddddddddddddddddddddddddddddddddd0h.............................................. + ////# 2 ......1addddddddddddddddddddddddddddddddddddddddddddddddddddddd0h............................................ + ////# 3 ........1addddddddddddddddddddddddddddddddddddddddddddddddddddddd0h.......................................... + ////# 4 ..........1addddddddddddddddddddddddddddddddddddddddddddddddddddddd0h........................................ + ////# 5 ............1addddddddddddddddddddddddddddddddddddddddddddddddddddddd0h...................................... + ////# 6 ..............1addddddddddddddddddddddddddddddddddddddddddddddddddddddd0h.................................... + ////# 7 ................1addddddddddddddddddddddddddddddddddddddddddddddddddddddd0h.................................. + ////# 8 .................wWWddddddddddddddddddddddddddddddddddddddddddddddddddddddd0h................................ + + ////# 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111111 + ////# 0000000000111111111122222222223333333333444444444455555555556666666666777777777788888888889999999999000000000 + ////# 0123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678 + ////# 8 .................wWWddddddddddddddddddddddddddddddddddddddddddddddddddddddd.................................. pp0_08 + ////# 7 ................1addddddddddddddddddddddddddddddddddddddddddddddddddddddd0h.................................. pp0_07 + ////# 6 ..............1addddddddddddddddddddddddddddddddddddddddddddddddddddddd0h.................................... pp0_06 + ////# ------------------------------------------------------------------------------------- + ////# ................233333333333333333333333333333333333333333333333333333323.... + ////# ...............ouuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuoo................................. pp1_05 + ////# ..............occccccccccccccccccccccccccccccccccccccccccccccccccccccccc__o................................. pp1_04 + + assign pp1_05[74] = pp0_08[74]; + assign pp1_05[73] = pp0_08[73]; + + assign pp1_04[74] = pp0_07[74]; + assign pp1_04[73] = tidn; + assign pp1_04[72] = tidn; + + + tri_csa32 pp1_02_csa_72( + .vd(vdd), + .gd(gnd), + .a(pp0_08[72]), //i-- + .b(pp0_07[72]), //i-- + .c(pp0_06[72]), //i-- + .sum(pp1_05[72]), //o-- + .car(pp1_04[71]) //o-- + ); + + tri_fu_csa22_h2 pp1_02_csa_71( + .a(pp0_08[71]), //i-- + .b(pp0_07[71]), //i-- + .sum(pp1_05[71]), //o-- + .car(pp1_04[70]) //o-- + ); + + tri_csa32 pp1_02_csa_70( + .vd(vdd), + .gd(gnd), + .a(pp0_08[70]), //i-- + .b(pp0_07[70]), //i-- + .c(pp0_06[70]), //i-- + .sum(pp1_05[70]), //o-- + .car(pp1_04[69]) //o-- + ); + + tri_csa32 pp1_02_csa_69( + .vd(vdd), + .gd(gnd), + .a(pp0_08[69]), //i-- + .b(pp0_07[69]), //i-- + .c(pp0_06[69]), //i-- + .sum(pp1_05[69]), //o-- + .car(pp1_04[68]) //o-- + ); + + tri_csa32 pp1_02_csa_68( + .vd(vdd), + .gd(gnd), + .a(pp0_08[68]), //i-- + .b(pp0_07[68]), //i-- + .c(pp0_06[68]), //i-- + .sum(pp1_05[68]), //o-- + .car(pp1_04[67]) //o-- + ); + + tri_csa32 pp1_02_csa_67( + .vd(vdd), + .gd(gnd), + .a(pp0_08[67]), //i-- + .b(pp0_07[67]), //i-- + .c(pp0_06[67]), //i-- + .sum(pp1_05[67]), //o-- + .car(pp1_04[66]) //o-- + ); + + tri_csa32 pp1_02_csa_66( + .vd(vdd), + .gd(gnd), + .a(pp0_08[66]), //i-- + .b(pp0_07[66]), //i-- + .c(pp0_06[66]), //i-- + .sum(pp1_05[66]), //o-- + .car(pp1_04[65]) //o-- + ); + + tri_csa32 pp1_02_csa_65( + .vd(vdd), + .gd(gnd), + .a(pp0_08[65]), //i-- + .b(pp0_07[65]), //i-- + .c(pp0_06[65]), //i-- + .sum(pp1_05[65]), //o-- + .car(pp1_04[64]) //o-- + ); + + tri_csa32 pp1_02_csa_64( + .vd(vdd), + .gd(gnd), + .a(pp0_08[64]), //i-- + .b(pp0_07[64]), //i-- + .c(pp0_06[64]), //i-- + .sum(pp1_05[64]), //o-- + .car(pp1_04[63]) //o-- + ); + + tri_csa32 pp1_02_csa_63( + .vd(vdd), + .gd(gnd), + .a(pp0_08[63]), //i-- + .b(pp0_07[63]), //i-- + .c(pp0_06[63]), //i-- + .sum(pp1_05[63]), //o-- + .car(pp1_04[62]) //o-- + ); + + tri_csa32 pp1_02_csa_62( + .vd(vdd), + .gd(gnd), + .a(pp0_08[62]), //i-- + .b(pp0_07[62]), //i-- + .c(pp0_06[62]), //i-- + .sum(pp1_05[62]), //o-- + .car(pp1_04[61]) //o-- + ); + + tri_csa32 pp1_02_csa_61( + .vd(vdd), + .gd(gnd), + .a(pp0_08[61]), //i-- + .b(pp0_07[61]), //i-- + .c(pp0_06[61]), //i-- + .sum(pp1_05[61]), //o-- + .car(pp1_04[60]) //o-- + ); + + tri_csa32 pp1_02_csa_60( + .vd(vdd), + .gd(gnd), + .a(pp0_08[60]), //i-- + .b(pp0_07[60]), //i-- + .c(pp0_06[60]), //i-- + .sum(pp1_05[60]), //o-- + .car(pp1_04[59]) //o-- + ); + + tri_csa32 pp1_02_csa_59( + .vd(vdd), + .gd(gnd), + .a(pp0_08[59]), //i-- + .b(pp0_07[59]), //i-- + .c(pp0_06[59]), //i-- + .sum(pp1_05[59]), //o-- + .car(pp1_04[58]) //o-- + ); + + tri_csa32 pp1_02_csa_58( + .vd(vdd), + .gd(gnd), + .a(pp0_08[58]), //i-- + .b(pp0_07[58]), //i-- + .c(pp0_06[58]), //i-- + .sum(pp1_05[58]), //o-- + .car(pp1_04[57]) //o-- + ); + + tri_csa32 pp1_02_csa_57( + .vd(vdd), + .gd(gnd), + .a(pp0_08[57]), //i-- + .b(pp0_07[57]), //i-- + .c(pp0_06[57]), //i-- + .sum(pp1_05[57]), //o-- + .car(pp1_04[56]) //o-- + ); + + tri_csa32 pp1_02_csa_56( + .vd(vdd), + .gd(gnd), + .a(pp0_08[56]), //i-- + .b(pp0_07[56]), //i-- + .c(pp0_06[56]), //i-- + .sum(pp1_05[56]), //o-- + .car(pp1_04[55]) //o-- + ); + + tri_csa32 pp1_02_csa_55( + .vd(vdd), + .gd(gnd), + .a(pp0_08[55]), //i-- + .b(pp0_07[55]), //i-- + .c(pp0_06[55]), //i-- + .sum(pp1_05[55]), //o-- + .car(pp1_04[54]) //o-- + ); + + tri_csa32 pp1_02_csa_54( + .vd(vdd), + .gd(gnd), + .a(pp0_08[54]), //i-- + .b(pp0_07[54]), //i-- + .c(pp0_06[54]), //i-- + .sum(pp1_05[54]), //o-- + .car(pp1_04[53]) //o-- + ); + + tri_csa32 pp1_02_csa_53( + .vd(vdd), + .gd(gnd), + .a(pp0_08[53]), //i-- + .b(pp0_07[53]), //i-- + .c(pp0_06[53]), //i-- + .sum(pp1_05[53]), //o-- + .car(pp1_04[52]) //o-- + ); + + tri_csa32 pp1_02_csa_52( + .vd(vdd), + .gd(gnd), + .a(pp0_08[52]), //i-- + .b(pp0_07[52]), //i-- + .c(pp0_06[52]), //i-- + .sum(pp1_05[52]), //o-- + .car(pp1_04[51]) //o-- + ); + + tri_csa32 pp1_02_csa_51( + .vd(vdd), + .gd(gnd), + .a(pp0_08[51]), //i-- + .b(pp0_07[51]), //i-- + .c(pp0_06[51]), //i-- + .sum(pp1_05[51]), //o-- + .car(pp1_04[50]) //o-- + ); + + tri_csa32 pp1_02_csa_50( + .vd(vdd), + .gd(gnd), + .a(pp0_08[50]), //i-- + .b(pp0_07[50]), //i-- + .c(pp0_06[50]), //i-- + .sum(pp1_05[50]), //o-- + .car(pp1_04[49]) //o-- + ); + + tri_csa32 pp1_02_csa_49( + .vd(vdd), + .gd(gnd), + .a(pp0_08[49]), //i-- + .b(pp0_07[49]), //i-- + .c(pp0_06[49]), //i-- + .sum(pp1_05[49]), //o-- + .car(pp1_04[48]) //o-- + ); + + tri_csa32 pp1_02_csa_48( + .vd(vdd), + .gd(gnd), + .a(pp0_08[48]), //i-- + .b(pp0_07[48]), //i-- + .c(pp0_06[48]), //i-- + .sum(pp1_05[48]), //o-- + .car(pp1_04[47]) //o-- + ); + + tri_csa32 pp1_02_csa_47( + .vd(vdd), + .gd(gnd), + .a(pp0_08[47]), //i-- + .b(pp0_07[47]), //i-- + .c(pp0_06[47]), //i-- + .sum(pp1_05[47]), //o-- + .car(pp1_04[46]) //o-- + ); + + tri_csa32 pp1_02_csa_46( + .vd(vdd), + .gd(gnd), + .a(pp0_08[46]), //i-- + .b(pp0_07[46]), //i-- + .c(pp0_06[46]), //i-- + .sum(pp1_05[46]), //o-- + .car(pp1_04[45]) //o-- + ); + + tri_csa32 pp1_02_csa_45( + .vd(vdd), + .gd(gnd), + .a(pp0_08[45]), //i-- + .b(pp0_07[45]), //i-- + .c(pp0_06[45]), //i-- + .sum(pp1_05[45]), //o-- + .car(pp1_04[44]) //o-- + ); + + tri_csa32 pp1_02_csa_44( + .vd(vdd), + .gd(gnd), + .a(pp0_08[44]), //i-- + .b(pp0_07[44]), //i-- + .c(pp0_06[44]), //i-- + .sum(pp1_05[44]), //o-- + .car(pp1_04[43]) //o-- + ); + + tri_csa32 pp1_02_csa_43( + .vd(vdd), + .gd(gnd), + .a(pp0_08[43]), //i-- + .b(pp0_07[43]), //i-- + .c(pp0_06[43]), //i-- + .sum(pp1_05[43]), //o-- + .car(pp1_04[42]) //o-- + ); + + tri_csa32 pp1_02_csa_42( + .vd(vdd), + .gd(gnd), + .a(pp0_08[42]), //i-- + .b(pp0_07[42]), //i-- + .c(pp0_06[42]), //i-- + .sum(pp1_05[42]), //o-- + .car(pp1_04[41]) //o-- + ); + + tri_csa32 pp1_02_csa_41( + .vd(vdd), + .gd(gnd), + .a(pp0_08[41]), //i-- + .b(pp0_07[41]), //i-- + .c(pp0_06[41]), //i-- + .sum(pp1_05[41]), //o-- + .car(pp1_04[40]) //o-- + ); + + tri_csa32 pp1_02_csa_40( + .vd(vdd), + .gd(gnd), + .a(pp0_08[40]), //i-- + .b(pp0_07[40]), //i-- + .c(pp0_06[40]), //i-- + .sum(pp1_05[40]), //o-- + .car(pp1_04[39]) //o-- + ); + + tri_csa32 pp1_02_csa_39( + .vd(vdd), + .gd(gnd), + .a(pp0_08[39]), //i-- + .b(pp0_07[39]), //i-- + .c(pp0_06[39]), //i-- + .sum(pp1_05[39]), //o-- + .car(pp1_04[38]) //o-- + ); + + tri_csa32 pp1_02_csa_38( + .vd(vdd), + .gd(gnd), + .a(pp0_08[38]), //i-- + .b(pp0_07[38]), //i-- + .c(pp0_06[38]), //i-- + .sum(pp1_05[38]), //o-- + .car(pp1_04[37]) //o-- + ); + + tri_csa32 pp1_02_csa_37( + .vd(vdd), + .gd(gnd), + .a(pp0_08[37]), //i-- + .b(pp0_07[37]), //i-- + .c(pp0_06[37]), //i-- + .sum(pp1_05[37]), //o-- + .car(pp1_04[36]) //o-- + ); + + tri_csa32 pp1_02_csa_36( + .vd(vdd), + .gd(gnd), + .a(pp0_08[36]), //i-- + .b(pp0_07[36]), //i-- + .c(pp0_06[36]), //i-- + .sum(pp1_05[36]), //o-- + .car(pp1_04[35]) //o-- + ); + + tri_csa32 pp1_02_csa_35( + .vd(vdd), + .gd(gnd), + .a(pp0_08[35]), //i-- + .b(pp0_07[35]), //i-- + .c(pp0_06[35]), //i-- + .sum(pp1_05[35]), //o-- + .car(pp1_04[34]) //o-- + ); + + tri_csa32 pp1_02_csa_34( + .vd(vdd), + .gd(gnd), + .a(pp0_08[34]), //i-- + .b(pp0_07[34]), //i-- + .c(pp0_06[34]), //i-- + .sum(pp1_05[34]), //o-- + .car(pp1_04[33]) //o-- + ); + + tri_csa32 pp1_02_csa_33( + .vd(vdd), + .gd(gnd), + .a(pp0_08[33]), //i-- + .b(pp0_07[33]), //i-- + .c(pp0_06[33]), //i-- + .sum(pp1_05[33]), //o-- + .car(pp1_04[32]) //o-- + ); + + tri_csa32 pp1_02_csa_32( + .vd(vdd), + .gd(gnd), + .a(pp0_08[32]), //i-- + .b(pp0_07[32]), //i-- + .c(pp0_06[32]), //i-- + .sum(pp1_05[32]), //o-- + .car(pp1_04[31]) //o-- + ); + + tri_csa32 pp1_02_csa_31( + .vd(vdd), + .gd(gnd), + .a(pp0_08[31]), //i-- + .b(pp0_07[31]), //i-- + .c(pp0_06[31]), //i-- + .sum(pp1_05[31]), //o-- + .car(pp1_04[30]) //o-- + ); + + tri_csa32 pp1_02_csa_30( + .vd(vdd), + .gd(gnd), + .a(pp0_08[30]), //i-- + .b(pp0_07[30]), //i-- + .c(pp0_06[30]), //i-- + .sum(pp1_05[30]), //o-- + .car(pp1_04[29]) //o-- + ); + + tri_csa32 pp1_02_csa_29( + .vd(vdd), + .gd(gnd), + .a(pp0_08[29]), //i-- + .b(pp0_07[29]), //i-- + .c(pp0_06[29]), //i-- + .sum(pp1_05[29]), //o-- + .car(pp1_04[28]) //o-- + ); + + tri_csa32 pp1_02_csa_28( + .vd(vdd), + .gd(gnd), + .a(pp0_08[28]), //i-- + .b(pp0_07[28]), //i-- + .c(pp0_06[28]), //i-- + .sum(pp1_05[28]), //o-- + .car(pp1_04[27]) //o-- + ); + + tri_csa32 pp1_02_csa_27( + .vd(vdd), + .gd(gnd), + .a(pp0_08[27]), //i-- + .b(pp0_07[27]), //i-- + .c(pp0_06[27]), //i-- + .sum(pp1_05[27]), //o-- + .car(pp1_04[26]) //o-- + ); + + tri_csa32 pp1_02_csa_26( + .vd(vdd), + .gd(gnd), + .a(pp0_08[26]), //i-- + .b(pp0_07[26]), //i-- + .c(pp0_06[26]), //i-- + .sum(pp1_05[26]), //o-- + .car(pp1_04[25]) //o-- + ); + + tri_csa32 pp1_02_csa_25( + .vd(vdd), + .gd(gnd), + .a(pp0_08[25]), //i-- + .b(pp0_07[25]), //i-- + .c(pp0_06[25]), //i-- + .sum(pp1_05[25]), //o-- + .car(pp1_04[24]) //o-- + ); + + tri_csa32 pp1_02_csa_24( + .vd(vdd), + .gd(gnd), + .a(pp0_08[24]), //i-- + .b(pp0_07[24]), //i-- + .c(pp0_06[24]), //i-- + .sum(pp1_05[24]), //o-- + .car(pp1_04[23]) //o-- + ); + + tri_csa32 pp1_02_csa_23( + .vd(vdd), + .gd(gnd), + .a(pp0_08[23]), //i-- + .b(pp0_07[23]), //i-- + .c(pp0_06[23]), //i-- + .sum(pp1_05[23]), //o-- + .car(pp1_04[22]) //o-- + ); + + tri_csa32 pp1_02_csa_22( + .vd(vdd), + .gd(gnd), + .a(pp0_08[22]), //i-- + .b(pp0_07[22]), //i-- + .c(pp0_06[22]), //i-- + .sum(pp1_05[22]), //o-- + .car(pp1_04[21]) //o-- + ); + + tri_csa32 pp1_02_csa_21( + .vd(vdd), + .gd(gnd), + .a(pp0_08[21]), //i-- + .b(pp0_07[21]), //i-- + .c(pp0_06[21]), //i-- + .sum(pp1_05[21]), //o-- + .car(pp1_04[20]) //o-- + ); + + tri_csa32 pp1_02_csa_20( + .vd(vdd), + .gd(gnd), + .a(pp0_08[20]), //i-- + .b(pp0_07[20]), //i-- + .c(pp0_06[20]), //i-- + .sum(pp1_05[20]), //o-- + .car(pp1_04[19]) //o-- + ); + + tri_csa32 pp1_02_csa_19( + .vd(vdd), + .gd(gnd), + .a(pp0_08[19]), //i-- + .b(pp0_07[19]), //i-- + .c(pp0_06[19]), //i-- + .sum(pp1_05[19]), //o-- + .car(pp1_04[18]) //o-- + ); + + tri_csa32 pp1_02_csa_18( + .vd(vdd), + .gd(gnd), + .a(pp0_08[18]), //i-- + .b(pp0_07[18]), //i-- + .c(pp0_06[18]), //i-- + .sum(pp1_05[18]), //o-- + .car(pp1_04[17]) //o-- + ); + + tri_csa32 pp1_02_csa_17( + .vd(vdd), + .gd(gnd), + .a(pp0_08[17]), //i-- + .b(pp0_07[17]), //i-- + .c(pp0_06[17]), //i-- + .sum(pp1_05[17]), //o-- + .car(pp1_04[16]) //o-- + ); + + tri_fu_csa22_h2 pp1_02_csa_16( + .a(tiup), //i-- + .b(pp0_06[16]), //i-- + .sum(pp1_05[16]), //o-- + .car(pp1_04[15]) //o-- + ); + assign pp1_05[15] = pp0_06[15]; + assign pp1_05[14] = tiup; + + ////# 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111111 + ////# 0000000000111111111122222222223333333333444444444455555555556666666666777777777788888888889999999999000000000 + ////# 0123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678 + ////# 5 ............1addddddddddddddddddddddddddddddddddddddddddddddddddddddd0h...................................... pp0_05 + ////# 4 ..........1addddddddddddddddddddddddddddddddddddddddddddddddddddddd0h........................................ pp0_04 + ////# 3 ........1addddddddddddddddddddddddddddddddddddddddddddddddddddddd0h.......................................... pp0_03 + ////# ------------------------------------------------------------------------------------- + ////# ..........223333333333333333333333333333333333333333333333333333323.... + ////# .........ouuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuoo_o..................................... pp1_03 + ////# ........occccccccccccccccccccccccccccccccccccccccccccccccccccccccc__o....................................... pp1_02 + + assign pp1_03[70] = pp0_05[70]; + assign pp1_03[69] = tidn; + assign pp1_03[68] = pp0_05[68]; + assign pp1_03[67] = pp0_05[67]; + + assign pp1_02[68] = pp0_04[68]; + assign pp1_02[67] = tidn; + assign pp1_02[66] = tidn; + + + tri_csa32 pp1_01_csa_66( + .vd(vdd), + .gd(gnd), + .a(pp0_05[66]), //i-- + .b(pp0_04[66]), //i-- + .c(pp0_03[66]), //i-- + .sum(pp1_03[66]), //o-- + .car(pp1_02[65]) //o-- + ); + + tri_fu_csa22_h2 pp1_01_csa_65( + .a(pp0_05[65]), //i-- + .b(pp0_04[65]), //i-- + .sum(pp1_03[65]), //o-- + .car(pp1_02[64]) //o-- + ); + + tri_csa32 pp1_01_csa_64( + .vd(vdd), + .gd(gnd), + .a(pp0_05[64]), //i-- + .b(pp0_04[64]), //i-- + .c(pp0_03[64]), //i-- + .sum(pp1_03[64]), //o-- + .car(pp1_02[63]) //o-- + ); + + tri_csa32 pp1_01_csa_63( + .vd(vdd), + .gd(gnd), + .a(pp0_05[63]), //i-- + .b(pp0_04[63]), //i-- + .c(pp0_03[63]), //i-- + .sum(pp1_03[63]), //o-- + .car(pp1_02[62]) //o-- + ); + + tri_csa32 pp1_01_csa_62( + .vd(vdd), + .gd(gnd), + .a(pp0_05[62]), //i-- + .b(pp0_04[62]), //i-- + .c(pp0_03[62]), //i-- + .sum(pp1_03[62]), //o-- + .car(pp1_02[61]) //o-- + ); + + tri_csa32 pp1_01_csa_61( + .vd(vdd), + .gd(gnd), + .a(pp0_05[61]), //i-- + .b(pp0_04[61]), //i-- + .c(pp0_03[61]), //i-- + .sum(pp1_03[61]), //o-- + .car(pp1_02[60]) //o-- + ); + + tri_csa32 pp1_01_csa_60( + .vd(vdd), + .gd(gnd), + .a(pp0_05[60]), //i-- + .b(pp0_04[60]), //i-- + .c(pp0_03[60]), //i-- + .sum(pp1_03[60]), //o-- + .car(pp1_02[59]) //o-- + ); + + tri_csa32 pp1_01_csa_59( + .vd(vdd), + .gd(gnd), + .a(pp0_05[59]), //i-- + .b(pp0_04[59]), //i-- + .c(pp0_03[59]), //i-- + .sum(pp1_03[59]), //o-- + .car(pp1_02[58]) //o-- + ); + + tri_csa32 pp1_01_csa_58( + .vd(vdd), + .gd(gnd), + .a(pp0_05[58]), //i-- + .b(pp0_04[58]), //i-- + .c(pp0_03[58]), //i-- + .sum(pp1_03[58]), //o-- + .car(pp1_02[57]) //o-- + ); + + tri_csa32 pp1_01_csa_57( + .vd(vdd), + .gd(gnd), + .a(pp0_05[57]), //i-- + .b(pp0_04[57]), //i-- + .c(pp0_03[57]), //i-- + .sum(pp1_03[57]), //o-- + .car(pp1_02[56]) //o-- + ); + + tri_csa32 pp1_01_csa_56( + .vd(vdd), + .gd(gnd), + .a(pp0_05[56]), //i-- + .b(pp0_04[56]), //i-- + .c(pp0_03[56]), //i-- + .sum(pp1_03[56]), //o-- + .car(pp1_02[55]) //o-- + ); + + tri_csa32 pp1_01_csa_55( + .vd(vdd), + .gd(gnd), + .a(pp0_05[55]), //i-- + .b(pp0_04[55]), //i-- + .c(pp0_03[55]), //i-- + .sum(pp1_03[55]), //o-- + .car(pp1_02[54]) //o-- + ); + + tri_csa32 pp1_01_csa_54( + .vd(vdd), + .gd(gnd), + .a(pp0_05[54]), //i-- + .b(pp0_04[54]), //i-- + .c(pp0_03[54]), //i-- + .sum(pp1_03[54]), //o-- + .car(pp1_02[53]) //o-- + ); + + tri_csa32 pp1_01_csa_53( + .vd(vdd), + .gd(gnd), + .a(pp0_05[53]), //i-- + .b(pp0_04[53]), //i-- + .c(pp0_03[53]), //i-- + .sum(pp1_03[53]), //o-- + .car(pp1_02[52]) //o-- + ); + + tri_csa32 pp1_01_csa_52( + .vd(vdd), + .gd(gnd), + .a(pp0_05[52]), //i-- + .b(pp0_04[52]), //i-- + .c(pp0_03[52]), //i-- + .sum(pp1_03[52]), //o-- + .car(pp1_02[51]) //o-- + ); + + tri_csa32 pp1_01_csa_51( + .vd(vdd), + .gd(gnd), + .a(pp0_05[51]), //i-- + .b(pp0_04[51]), //i-- + .c(pp0_03[51]), //i-- + .sum(pp1_03[51]), //o-- + .car(pp1_02[50]) //o-- + ); + + tri_csa32 pp1_01_csa_50( + .vd(vdd), + .gd(gnd), + .a(pp0_05[50]), //i-- + .b(pp0_04[50]), //i-- + .c(pp0_03[50]), //i-- + .sum(pp1_03[50]), //o-- + .car(pp1_02[49]) //o-- + ); + + tri_csa32 pp1_01_csa_49( + .vd(vdd), + .gd(gnd), + .a(pp0_05[49]), //i-- + .b(pp0_04[49]), //i-- + .c(pp0_03[49]), //i-- + .sum(pp1_03[49]), //o-- + .car(pp1_02[48]) //o-- + ); + + tri_csa32 pp1_01_csa_48( + .vd(vdd), + .gd(gnd), + .a(pp0_05[48]), //i-- + .b(pp0_04[48]), //i-- + .c(pp0_03[48]), //i-- + .sum(pp1_03[48]), //o-- + .car(pp1_02[47]) //o-- + ); + + tri_csa32 pp1_01_csa_47( + .vd(vdd), + .gd(gnd), + .a(pp0_05[47]), //i-- + .b(pp0_04[47]), //i-- + .c(pp0_03[47]), //i-- + .sum(pp1_03[47]), //o-- + .car(pp1_02[46]) //o-- + ); + + tri_csa32 pp1_01_csa_46( + .vd(vdd), + .gd(gnd), + .a(pp0_05[46]), //i-- + .b(pp0_04[46]), //i-- + .c(pp0_03[46]), //i-- + .sum(pp1_03[46]), //o-- + .car(pp1_02[45]) //o-- + ); + + tri_csa32 pp1_01_csa_45( + .vd(vdd), + .gd(gnd), + .a(pp0_05[45]), //i-- + .b(pp0_04[45]), //i-- + .c(pp0_03[45]), //i-- + .sum(pp1_03[45]), //o-- + .car(pp1_02[44]) //o-- + ); + + tri_csa32 pp1_01_csa_44( + .vd(vdd), + .gd(gnd), + .a(pp0_05[44]), //i-- + .b(pp0_04[44]), //i-- + .c(pp0_03[44]), //i-- + .sum(pp1_03[44]), //o-- + .car(pp1_02[43]) //o-- + ); + + tri_csa32 pp1_01_csa_43( + .vd(vdd), + .gd(gnd), + .a(pp0_05[43]), //i-- + .b(pp0_04[43]), //i-- + .c(pp0_03[43]), //i-- + .sum(pp1_03[43]), //o-- + .car(pp1_02[42]) //o-- + ); + + tri_csa32 pp1_01_csa_42( + .vd(vdd), + .gd(gnd), + .a(pp0_05[42]), //i-- + .b(pp0_04[42]), //i-- + .c(pp0_03[42]), //i-- + .sum(pp1_03[42]), //o-- + .car(pp1_02[41]) //o-- + ); + + tri_csa32 pp1_01_csa_41( + .vd(vdd), + .gd(gnd), + .a(pp0_05[41]), //i-- + .b(pp0_04[41]), //i-- + .c(pp0_03[41]), //i-- + .sum(pp1_03[41]), //o-- + .car(pp1_02[40]) //o-- + ); + + tri_csa32 pp1_01_csa_40( + .vd(vdd), + .gd(gnd), + .a(pp0_05[40]), //i-- + .b(pp0_04[40]), //i-- + .c(pp0_03[40]), //i-- + .sum(pp1_03[40]), //o-- + .car(pp1_02[39]) //o-- + ); + + tri_csa32 pp1_01_csa_39( + .vd(vdd), + .gd(gnd), + .a(pp0_05[39]), //i-- + .b(pp0_04[39]), //i-- + .c(pp0_03[39]), //i-- + .sum(pp1_03[39]), //o-- + .car(pp1_02[38]) //o-- + ); + + tri_csa32 pp1_01_csa_38( + .vd(vdd), + .gd(gnd), + .a(pp0_05[38]), //i-- + .b(pp0_04[38]), //i-- + .c(pp0_03[38]), //i-- + .sum(pp1_03[38]), //o-- + .car(pp1_02[37]) //o-- + ); + + tri_csa32 pp1_01_csa_37( + .vd(vdd), + .gd(gnd), + .a(pp0_05[37]), //i-- + .b(pp0_04[37]), //i-- + .c(pp0_03[37]), //i-- + .sum(pp1_03[37]), //o-- + .car(pp1_02[36]) //o-- + ); + + tri_csa32 pp1_01_csa_36( + .vd(vdd), + .gd(gnd), + .a(pp0_05[36]), //i-- + .b(pp0_04[36]), //i-- + .c(pp0_03[36]), //i-- + .sum(pp1_03[36]), //o-- + .car(pp1_02[35]) //o-- + ); + + tri_csa32 pp1_01_csa_35( + .vd(vdd), + .gd(gnd), + .a(pp0_05[35]), //i-- + .b(pp0_04[35]), //i-- + .c(pp0_03[35]), //i-- + .sum(pp1_03[35]), //o-- + .car(pp1_02[34]) //o-- + ); + + tri_csa32 pp1_01_csa_34( + .vd(vdd), + .gd(gnd), + .a(pp0_05[34]), //i-- + .b(pp0_04[34]), //i-- + .c(pp0_03[34]), //i-- + .sum(pp1_03[34]), //o-- + .car(pp1_02[33]) //o-- + ); + + tri_csa32 pp1_01_csa_33( + .vd(vdd), + .gd(gnd), + .a(pp0_05[33]), //i-- + .b(pp0_04[33]), //i-- + .c(pp0_03[33]), //i-- + .sum(pp1_03[33]), //o-- + .car(pp1_02[32]) //o-- + ); + + tri_csa32 pp1_01_csa_32( + .vd(vdd), + .gd(gnd), + .a(pp0_05[32]), //i-- + .b(pp0_04[32]), //i-- + .c(pp0_03[32]), //i-- + .sum(pp1_03[32]), //o-- + .car(pp1_02[31]) //o-- + ); + + tri_csa32 pp1_01_csa_31( + .vd(vdd), + .gd(gnd), + .a(pp0_05[31]), //i-- + .b(pp0_04[31]), //i-- + .c(pp0_03[31]), //i-- + .sum(pp1_03[31]), //o-- + .car(pp1_02[30]) //o-- + ); + + tri_csa32 pp1_01_csa_30( + .vd(vdd), + .gd(gnd), + .a(pp0_05[30]), //i-- + .b(pp0_04[30]), //i-- + .c(pp0_03[30]), //i-- + .sum(pp1_03[30]), //o-- + .car(pp1_02[29]) //o-- + ); + + tri_csa32 pp1_01_csa_29( + .vd(vdd), + .gd(gnd), + .a(pp0_05[29]), //i-- + .b(pp0_04[29]), //i-- + .c(pp0_03[29]), //i-- + .sum(pp1_03[29]), //o-- + .car(pp1_02[28]) //o-- + ); + + tri_csa32 pp1_01_csa_28( + .vd(vdd), + .gd(gnd), + .a(pp0_05[28]), //i-- + .b(pp0_04[28]), //i-- + .c(pp0_03[28]), //i-- + .sum(pp1_03[28]), //o-- + .car(pp1_02[27]) //o-- + ); + + tri_csa32 pp1_01_csa_27( + .vd(vdd), + .gd(gnd), + .a(pp0_05[27]), //i-- + .b(pp0_04[27]), //i-- + .c(pp0_03[27]), //i-- + .sum(pp1_03[27]), //o-- + .car(pp1_02[26]) //o-- + ); + + tri_csa32 pp1_01_csa_26( + .vd(vdd), + .gd(gnd), + .a(pp0_05[26]), //i-- + .b(pp0_04[26]), //i-- + .c(pp0_03[26]), //i-- + .sum(pp1_03[26]), //o-- + .car(pp1_02[25]) //o-- + ); + + tri_csa32 pp1_01_csa_25( + .vd(vdd), + .gd(gnd), + .a(pp0_05[25]), //i-- + .b(pp0_04[25]), //i-- + .c(pp0_03[25]), //i-- + .sum(pp1_03[25]), //o-- + .car(pp1_02[24]) //o-- + ); + + tri_csa32 pp1_01_csa_24( + .vd(vdd), + .gd(gnd), + .a(pp0_05[24]), //i-- + .b(pp0_04[24]), //i-- + .c(pp0_03[24]), //i-- + .sum(pp1_03[24]), //o-- + .car(pp1_02[23]) //o-- + ); + + tri_csa32 pp1_01_csa_23( + .vd(vdd), + .gd(gnd), + .a(pp0_05[23]), //i-- + .b(pp0_04[23]), //i-- + .c(pp0_03[23]), //i-- + .sum(pp1_03[23]), //o-- + .car(pp1_02[22]) //o-- + ); + + tri_csa32 pp1_01_csa_22( + .vd(vdd), + .gd(gnd), + .a(pp0_05[22]), //i-- + .b(pp0_04[22]), //i-- + .c(pp0_03[22]), //i-- + .sum(pp1_03[22]), //o-- + .car(pp1_02[21]) //o-- + ); + + tri_csa32 pp1_01_csa_21( + .vd(vdd), + .gd(gnd), + .a(pp0_05[21]), //i-- + .b(pp0_04[21]), //i-- + .c(pp0_03[21]), //i-- + .sum(pp1_03[21]), //o-- + .car(pp1_02[20]) //o-- + ); + + tri_csa32 pp1_01_csa_20( + .vd(vdd), + .gd(gnd), + .a(pp0_05[20]), //i-- + .b(pp0_04[20]), //i-- + .c(pp0_03[20]), //i-- + .sum(pp1_03[20]), //o-- + .car(pp1_02[19]) //o-- + ); + + tri_csa32 pp1_01_csa_19( + .vd(vdd), + .gd(gnd), + .a(pp0_05[19]), //i-- + .b(pp0_04[19]), //i-- + .c(pp0_03[19]), //i-- + .sum(pp1_03[19]), //o-- + .car(pp1_02[18]) //o-- + ); + + tri_csa32 pp1_01_csa_18( + .vd(vdd), + .gd(gnd), + .a(pp0_05[18]), //i-- + .b(pp0_04[18]), //i-- + .c(pp0_03[18]), //i-- + .sum(pp1_03[18]), //o-- + .car(pp1_02[17]) //o-- + ); + + tri_csa32 pp1_01_csa_17( + .vd(vdd), + .gd(gnd), + .a(pp0_05[17]), //i-- + .b(pp0_04[17]), //i-- + .c(pp0_03[17]), //i-- + .sum(pp1_03[17]), //o-- + .car(pp1_02[16]) //o-- + ); + + tri_csa32 pp1_01_csa_16( + .vd(vdd), + .gd(gnd), + .a(pp0_05[16]), //i-- + .b(pp0_04[16]), //i-- + .c(pp0_03[16]), //i-- + .sum(pp1_03[16]), //o-- + .car(pp1_02[15]) //o-- + ); + + tri_csa32 pp1_01_csa_15( + .vd(vdd), + .gd(gnd), + .a(pp0_05[15]), //i-- + .b(pp0_04[15]), //i-- + .c(pp0_03[15]), //i-- + .sum(pp1_03[15]), //o-- + .car(pp1_02[14]) //o-- + ); + + tri_csa32 pp1_01_csa_14( + .vd(vdd), + .gd(gnd), + .a(pp0_05[14]), //i-- + .b(pp0_04[14]), //i-- + .c(pp0_03[14]), //i-- + .sum(pp1_03[14]), //o-- + .car(pp1_02[13]) //o-- + ); + + tri_csa32 pp1_01_csa_13( + .vd(vdd), + .gd(gnd), + .a(pp0_05[13]), //i-- + .b(pp0_04[13]), //i-- + .c(pp0_03[13]), //i-- + .sum(pp1_03[13]), //o-- + .car(pp1_02[12]) //o-- + ); + + tri_csa32 pp1_01_csa_12( + .vd(vdd), + .gd(gnd), + .a(tiup), //i-- + .b(pp0_04[12]), //i-- + .c(pp0_03[12]), //i-- + .sum(pp1_03[12]), //o-- + .car(pp1_02[11]) //o-- + ); + + tri_fu_csa22_h2 pp1_01_csa_11( + .a(pp0_04[11]), //i-- + .b(pp0_03[11]), //i-- + .sum(pp1_03[11]), //o-- + .car(pp1_02[10]) //o-- + ); + + tri_fu_csa22_h2 pp1_01_csa_10( + .a(tiup), //i-- + .b(pp0_03[10]), //i-- + .sum(pp1_03[10]), //o-- + .car(pp1_02[9]) //o-- + ); + assign pp1_03[9] = pp0_03[9]; + assign pp1_03[8] = tiup; + + ////# 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111111 + ////# 0000000000111111111122222222223333333333444444444455555555556666666666777777777788888888889999999999000000000 + ////# 0123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678 + ////# 2 ......1addddddddddddddddddddddddddddddddddddddddddddddddddddddd0h............................................ pp0_02 + ////# 1 ....1addddddddddddddddddddddddddddddddddddddddddddddddddddddd0h.............................................. pp0_01 + ////# 0 ..zzddddddddddddddddddddddddddddddddddddddddddddddddddddddd0h................................................ pp0_00 + ////# ------------------------------------------------------------------------------------- + ////# ....223333333333333333333333333333333333333333333333333333323.... + ////# ...ouuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuoo_o............................................ pp1_01 + ////# ..occccccccccccccccccccccccccccccccccccccccccccccccccccccccc__o.............................................. pp1_00 + + assign pp1_01[64] = pp0_02[64]; + assign pp1_01[63] = tidn; + assign pp1_01[62] = pp0_02[62]; + assign pp1_01[61] = pp0_02[61]; + + assign pp1_00[62] = pp0_01[62]; + assign pp1_00[61] = tidn; + assign pp1_00[60] = tidn; + + + tri_csa32 pp1_00_csa_60( + .vd(vdd), + .gd(gnd), + .a(pp0_02[60]), //i-- + .b(pp0_01[60]), //i-- + .c(pp0_00[60]), //i-- + .sum(pp1_01[60]), //o-- + .car(pp1_00[59]) //o-- + ); + + tri_fu_csa22_h2 pp1_00_csa_59( + .a(pp0_02[59]), //i-- + .b(pp0_01[59]), //i-- + .sum(pp1_01[59]), //o-- + .car(pp1_00[58]) //o-- + ); + + tri_csa32 pp1_00_csa_58( + .vd(vdd), + .gd(gnd), + .a(pp0_02[58]), //i-- + .b(pp0_01[58]), //i-- + .c(pp0_00[58]), //i-- + .sum(pp1_01[58]), //o-- + .car(pp1_00[57]) //o-- + ); + + tri_csa32 pp1_00_csa_57( + .vd(vdd), + .gd(gnd), + .a(pp0_02[57]), //i-- + .b(pp0_01[57]), //i-- + .c(pp0_00[57]), //i-- + .sum(pp1_01[57]), //o-- + .car(pp1_00[56]) //o-- + ); + + tri_csa32 pp1_00_csa_56( + .vd(vdd), + .gd(gnd), + .a(pp0_02[56]), //i-- + .b(pp0_01[56]), //i-- + .c(pp0_00[56]), //i-- + .sum(pp1_01[56]), //o-- + .car(pp1_00[55]) //o-- + ); + + tri_csa32 pp1_00_csa_55( + .vd(vdd), + .gd(gnd), + .a(pp0_02[55]), //i-- + .b(pp0_01[55]), //i-- + .c(pp0_00[55]), //i-- + .sum(pp1_01[55]), //o-- + .car(pp1_00[54]) //o-- + ); + + tri_csa32 pp1_00_csa_54( + .vd(vdd), + .gd(gnd), + .a(pp0_02[54]), //i-- + .b(pp0_01[54]), //i-- + .c(pp0_00[54]), //i-- + .sum(pp1_01[54]), //o-- + .car(pp1_00[53]) //o-- + ); + + tri_csa32 pp1_00_csa_53( + .vd(vdd), + .gd(gnd), + .a(pp0_02[53]), //i-- + .b(pp0_01[53]), //i-- + .c(pp0_00[53]), //i-- + .sum(pp1_01[53]), //o-- + .car(pp1_00[52]) //o-- + ); + + tri_csa32 pp1_00_csa_52( + .vd(vdd), + .gd(gnd), + .a(pp0_02[52]), //i-- + .b(pp0_01[52]), //i-- + .c(pp0_00[52]), //i-- + .sum(pp1_01[52]), //o-- + .car(pp1_00[51]) //o-- + ); + + tri_csa32 pp1_00_csa_51( + .vd(vdd), + .gd(gnd), + .a(pp0_02[51]), //i-- + .b(pp0_01[51]), //i-- + .c(pp0_00[51]), //i-- + .sum(pp1_01[51]), //o-- + .car(pp1_00[50]) //o-- + ); + + tri_csa32 pp1_00_csa_50( + .vd(vdd), + .gd(gnd), + .a(pp0_02[50]), //i-- + .b(pp0_01[50]), //i-- + .c(pp0_00[50]), //i-- + .sum(pp1_01[50]), //o-- + .car(pp1_00[49]) //o-- + ); + + tri_csa32 pp1_00_csa_49( + .vd(vdd), + .gd(gnd), + .a(pp0_02[49]), //i-- + .b(pp0_01[49]), //i-- + .c(pp0_00[49]), //i-- + .sum(pp1_01[49]), //o-- + .car(pp1_00[48]) //o-- + ); + + tri_csa32 pp1_00_csa_48( + .vd(vdd), + .gd(gnd), + .a(pp0_02[48]), //i-- + .b(pp0_01[48]), //i-- + .c(pp0_00[48]), //i-- + .sum(pp1_01[48]), //o-- + .car(pp1_00[47]) //o-- + ); + + tri_csa32 pp1_00_csa_47( + .vd(vdd), + .gd(gnd), + .a(pp0_02[47]), //i-- + .b(pp0_01[47]), //i-- + .c(pp0_00[47]), //i-- + .sum(pp1_01[47]), //o-- + .car(pp1_00[46]) //o-- + ); + + tri_csa32 pp1_00_csa_46( + .vd(vdd), + .gd(gnd), + .a(pp0_02[46]), //i-- + .b(pp0_01[46]), //i-- + .c(pp0_00[46]), //i-- + .sum(pp1_01[46]), //o-- + .car(pp1_00[45]) //o-- + ); + + tri_csa32 pp1_00_csa_45( + .vd(vdd), + .gd(gnd), + .a(pp0_02[45]), //i-- + .b(pp0_01[45]), //i-- + .c(pp0_00[45]), //i-- + .sum(pp1_01[45]), //o-- + .car(pp1_00[44]) //o-- + ); + + tri_csa32 pp1_00_csa_44( + .vd(vdd), + .gd(gnd), + .a(pp0_02[44]), //i-- + .b(pp0_01[44]), //i-- + .c(pp0_00[44]), //i-- + .sum(pp1_01[44]), //o-- + .car(pp1_00[43]) //o-- + ); + + tri_csa32 pp1_00_csa_43( + .vd(vdd), + .gd(gnd), + .a(pp0_02[43]), //i-- + .b(pp0_01[43]), //i-- + .c(pp0_00[43]), //i-- + .sum(pp1_01[43]), //o-- + .car(pp1_00[42]) //o-- + ); + + tri_csa32 pp1_00_csa_42( + .vd(vdd), + .gd(gnd), + .a(pp0_02[42]), //i-- + .b(pp0_01[42]), //i-- + .c(pp0_00[42]), //i-- + .sum(pp1_01[42]), //o-- + .car(pp1_00[41]) //o-- + ); + + tri_csa32 pp1_00_csa_41( + .vd(vdd), + .gd(gnd), + .a(pp0_02[41]), //i-- + .b(pp0_01[41]), //i-- + .c(pp0_00[41]), //i-- + .sum(pp1_01[41]), //o-- + .car(pp1_00[40]) //o-- + ); + + tri_csa32 pp1_00_csa_40( + .vd(vdd), + .gd(gnd), + .a(pp0_02[40]), //i-- + .b(pp0_01[40]), //i-- + .c(pp0_00[40]), //i-- + .sum(pp1_01[40]), //o-- + .car(pp1_00[39]) //o-- + ); + + tri_csa32 pp1_00_csa_39( + .vd(vdd), + .gd(gnd), + .a(pp0_02[39]), //i-- + .b(pp0_01[39]), //i-- + .c(pp0_00[39]), //i-- + .sum(pp1_01[39]), //o-- + .car(pp1_00[38]) //o-- + ); + + tri_csa32 pp1_00_csa_38( + .vd(vdd), + .gd(gnd), + .a(pp0_02[38]), //i-- + .b(pp0_01[38]), //i-- + .c(pp0_00[38]), //i-- + .sum(pp1_01[38]), //o-- + .car(pp1_00[37]) //o-- + ); + + tri_csa32 pp1_00_csa_37( + .vd(vdd), + .gd(gnd), + .a(pp0_02[37]), //i-- + .b(pp0_01[37]), //i-- + .c(pp0_00[37]), //i-- + .sum(pp1_01[37]), //o-- + .car(pp1_00[36]) //o-- + ); + + tri_csa32 pp1_00_csa_36( + .vd(vdd), + .gd(gnd), + .a(pp0_02[36]), //i-- + .b(pp0_01[36]), //i-- + .c(pp0_00[36]), //i-- + .sum(pp1_01[36]), //o-- + .car(pp1_00[35]) //o-- + ); + + tri_csa32 pp1_00_csa_35( + .vd(vdd), + .gd(gnd), + .a(pp0_02[35]), //i-- + .b(pp0_01[35]), //i-- + .c(pp0_00[35]), //i-- + .sum(pp1_01[35]), //o-- + .car(pp1_00[34]) //o-- + ); + + tri_csa32 pp1_00_csa_34( + .vd(vdd), + .gd(gnd), + .a(pp0_02[34]), //i-- + .b(pp0_01[34]), //i-- + .c(pp0_00[34]), //i-- + .sum(pp1_01[34]), //o-- + .car(pp1_00[33]) //o-- + ); + + tri_csa32 pp1_00_csa_33( + .vd(vdd), + .gd(gnd), + .a(pp0_02[33]), //i-- + .b(pp0_01[33]), //i-- + .c(pp0_00[33]), //i-- + .sum(pp1_01[33]), //o-- + .car(pp1_00[32]) //o-- + ); + + tri_csa32 pp1_00_csa_32( + .vd(vdd), + .gd(gnd), + .a(pp0_02[32]), //i-- + .b(pp0_01[32]), //i-- + .c(pp0_00[32]), //i-- + .sum(pp1_01[32]), //o-- + .car(pp1_00[31]) //o-- + ); + + tri_csa32 pp1_00_csa_31( + .vd(vdd), + .gd(gnd), + .a(pp0_02[31]), //i-- + .b(pp0_01[31]), //i-- + .c(pp0_00[31]), //i-- + .sum(pp1_01[31]), //o-- + .car(pp1_00[30]) //o-- + ); + + tri_csa32 pp1_00_csa_30( + .vd(vdd), + .gd(gnd), + .a(pp0_02[30]), //i-- + .b(pp0_01[30]), //i-- + .c(pp0_00[30]), //i-- + .sum(pp1_01[30]), //o-- + .car(pp1_00[29]) //o-- + ); + + tri_csa32 pp1_00_csa_29( + .vd(vdd), + .gd(gnd), + .a(pp0_02[29]), //i-- + .b(pp0_01[29]), //i-- + .c(pp0_00[29]), //i-- + .sum(pp1_01[29]), //o-- + .car(pp1_00[28]) //o-- + ); + + tri_csa32 pp1_00_csa_28( + .vd(vdd), + .gd(gnd), + .a(pp0_02[28]), //i-- + .b(pp0_01[28]), //i-- + .c(pp0_00[28]), //i-- + .sum(pp1_01[28]), //o-- + .car(pp1_00[27]) //o-- + ); + + tri_csa32 pp1_00_csa_27( + .vd(vdd), + .gd(gnd), + .a(pp0_02[27]), //i-- + .b(pp0_01[27]), //i-- + .c(pp0_00[27]), //i-- + .sum(pp1_01[27]), //o-- + .car(pp1_00[26]) //o-- + ); + + tri_csa32 pp1_00_csa_26( + .vd(vdd), + .gd(gnd), + .a(pp0_02[26]), //i-- + .b(pp0_01[26]), //i-- + .c(pp0_00[26]), //i-- + .sum(pp1_01[26]), //o-- + .car(pp1_00[25]) //o-- + ); + + tri_csa32 pp1_00_csa_25( + .vd(vdd), + .gd(gnd), + .a(pp0_02[25]), //i-- + .b(pp0_01[25]), //i-- + .c(pp0_00[25]), //i-- + .sum(pp1_01[25]), //o-- + .car(pp1_00[24]) //o-- + ); + + tri_csa32 pp1_00_csa_24( + .vd(vdd), + .gd(gnd), + .a(pp0_02[24]), //i-- + .b(pp0_01[24]), //i-- + .c(pp0_00[24]), //i-- + .sum(pp1_01[24]), //o-- + .car(pp1_00[23]) //o-- + ); + + tri_csa32 pp1_00_csa_23( + .vd(vdd), + .gd(gnd), + .a(pp0_02[23]), //i-- + .b(pp0_01[23]), //i-- + .c(pp0_00[23]), //i-- + .sum(pp1_01[23]), //o-- + .car(pp1_00[22]) //o-- + ); + + tri_csa32 pp1_00_csa_22( + .vd(vdd), + .gd(gnd), + .a(pp0_02[22]), //i-- + .b(pp0_01[22]), //i-- + .c(pp0_00[22]), //i-- + .sum(pp1_01[22]), //o-- + .car(pp1_00[21]) //o-- + ); + + tri_csa32 pp1_00_csa_21( + .vd(vdd), + .gd(gnd), + .a(pp0_02[21]), //i-- + .b(pp0_01[21]), //i-- + .c(pp0_00[21]), //i-- + .sum(pp1_01[21]), //o-- + .car(pp1_00[20]) //o-- + ); + + tri_csa32 pp1_00_csa_20( + .vd(vdd), + .gd(gnd), + .a(pp0_02[20]), //i-- + .b(pp0_01[20]), //i-- + .c(pp0_00[20]), //i-- + .sum(pp1_01[20]), //o-- + .car(pp1_00[19]) //o-- + ); + + tri_csa32 pp1_00_csa_19( + .vd(vdd), + .gd(gnd), + .a(pp0_02[19]), //i-- + .b(pp0_01[19]), //i-- + .c(pp0_00[19]), //i-- + .sum(pp1_01[19]), //o-- + .car(pp1_00[18]) //o-- + ); + + tri_csa32 pp1_00_csa_18( + .vd(vdd), + .gd(gnd), + .a(pp0_02[18]), //i-- + .b(pp0_01[18]), //i-- + .c(pp0_00[18]), //i-- + .sum(pp1_01[18]), //o-- + .car(pp1_00[17]) //o-- + ); + + tri_csa32 pp1_00_csa_17( + .vd(vdd), + .gd(gnd), + .a(pp0_02[17]), //i-- + .b(pp0_01[17]), //i-- + .c(pp0_00[17]), //i-- + .sum(pp1_01[17]), //o-- + .car(pp1_00[16]) //o-- + ); + + tri_csa32 pp1_00_csa_16( + .vd(vdd), + .gd(gnd), + .a(pp0_02[16]), //i-- + .b(pp0_01[16]), //i-- + .c(pp0_00[16]), //i-- + .sum(pp1_01[16]), //o-- + .car(pp1_00[15]) //o-- + ); + + tri_csa32 pp1_00_csa_15( + .vd(vdd), + .gd(gnd), + .a(pp0_02[15]), //i-- + .b(pp0_01[15]), //i-- + .c(pp0_00[15]), //i-- + .sum(pp1_01[15]), //o-- + .car(pp1_00[14]) //o-- + ); + + tri_csa32 pp1_00_csa_14( + .vd(vdd), + .gd(gnd), + .a(pp0_02[14]), //i-- + .b(pp0_01[14]), //i-- + .c(pp0_00[14]), //i-- + .sum(pp1_01[14]), //o-- + .car(pp1_00[13]) //o-- + ); + + tri_csa32 pp1_00_csa_13( + .vd(vdd), + .gd(gnd), + .a(pp0_02[13]), //i-- + .b(pp0_01[13]), //i-- + .c(pp0_00[13]), //i-- + .sum(pp1_01[13]), //o-- + .car(pp1_00[12]) //o-- + ); + + tri_csa32 pp1_00_csa_12( + .vd(vdd), + .gd(gnd), + .a(pp0_02[12]), //i-- + .b(pp0_01[12]), //i-- + .c(pp0_00[12]), //i-- + .sum(pp1_01[12]), //o-- + .car(pp1_00[11]) //o-- + ); + + tri_csa32 pp1_00_csa_11( + .vd(vdd), + .gd(gnd), + .a(pp0_02[11]), //i-- + .b(pp0_01[11]), //i-- + .c(pp0_00[11]), //i-- + .sum(pp1_01[11]), //o-- + .car(pp1_00[10]) //o-- + ); + + tri_csa32 pp1_00_csa_10( + .vd(vdd), + .gd(gnd), + .a(pp0_02[10]), //i-- + .b(pp0_01[10]), //i-- + .c(pp0_00[10]), //i-- + .sum(pp1_01[10]), //o-- + .car(pp1_00[9]) //o-- + ); + + tri_csa32 pp1_00_csa_09( + .vd(vdd), + .gd(gnd), + .a(pp0_02[9]), //i-- + .b(pp0_01[9]), //i-- + .c(pp0_00[9]), //i-- + .sum(pp1_01[9]), //o-- + .car(pp1_00[8]) //o-- + ); + + tri_csa32 pp1_00_csa_08( + .vd(vdd), + .gd(gnd), + .a(pp0_02[8]), //i-- + .b(pp0_01[8]), //i-- + .c(pp0_00[8]), //i-- + .sum(pp1_01[8]), //o-- + .car(pp1_00[7]) //o-- + ); + + tri_csa32 pp1_00_csa_07( + .vd(vdd), + .gd(gnd), + .a(pp0_02[7]), //i-- + .b(pp0_01[7]), //i-- + .c(pp0_00[7]), //i-- + .sum(pp1_01[7]), //o-- + .car(pp1_00[6]) //o-- + ); + + tri_csa32 pp1_00_csa_06( + .vd(vdd), + .gd(gnd), + .a(tiup), //i-- + .b(pp0_01[6]), //i-- + .c(pp0_00[6]), //i-- + .sum(pp1_01[6]), //o-- + .car(pp1_00[5]) //o-- + ); + + tri_fu_csa22_h2 pp1_00_csa_05( + .a(pp0_01[5]), //i-- + .b(pp0_00[5]), //i-- + .sum(pp1_01[5]), //o-- + .car(pp1_00[4]) //o-- + ); + + tri_fu_csa22_h2 pp1_00_csa_04( + .a(tiup), //i-- + .b(pp0_00[4]), //i-- + .sum(pp1_01[4]), //o-- + .car(pp1_00[3]) //o-- + ); + + generate + if (inst == 0) + begin : gg0 + assign pp1_01[3] = tidn; //unique for different copies of tri_fu_mul_92 ("0" for msb copy) + assign pp1_01[2] = tidn; //unique for different copies of tri_fu_mul_92 ("0" for msb copy) + end + endgenerate + + generate + if (inst == 1) + begin : gg1 + assign pp1_01[3] = pp0_00[3]; //unique for different copies of tri_fu_mul_92 ("0" for msb copy) + assign pp1_01[2] = pp0_00[2]; //unique for different copies of tri_fu_mul_92 ("0" for msb copy) + end + endgenerate + + generate + if (inst == 2) + begin : gg2 + assign pp1_01[3] = pp0_00[3]; //unique for different copies of tri_fu_mul_92 ("0" for msb copy) + assign pp1_01[2] = pp0_00[2]; //unique for different copies of tri_fu_mul_92 ("0" for msb copy) + end + endgenerate + + ////################################################## + ////# Compressor Level 2 + ////################################################## + + ////# 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111111 + ////# 0000000000111111111122222222223333333333444444444455555555556666666666777777777788888888889999999999000000000 + ////# 0123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678 + ////# ...............ouuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuoo.................................. pp1_05 + ////# ..............occccccccccccccccccccccccccccccccccccccccccccccccccccccccc__o.................................. pp1_04 + ////# .........ouuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuoo_o...................................... pp1_03 + ////# ------------------------------------------------------------------------------------- + ////# ..............233333333333333333333333333333333333333333333333333333323 + ////# .........ooooouuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuoooo................................. pp2_03 + ////# .............ccccccccccccccccccccccccccccccccccccccccccccccccccccccccc_o__o................................. pp2_02 + + assign pp2_03[74] = pp1_05[74]; + assign pp2_03[73] = pp1_05[73]; + assign pp2_03[72] = pp1_05[72]; + assign pp2_03[71] = pp1_05[71]; + + assign pp2_02[74] = pp1_04[74]; + assign pp2_02[73] = tidn; + assign pp2_02[72] = tidn; + assign pp2_02[71] = pp1_04[71]; + assign pp2_02[70] = tidn; + + + tri_csa32 pp2_01_csa_70( + .vd(vdd), + .gd(gnd), + .a(pp1_05[70]), //i-- + .b(pp1_04[70]), //i-- + .c(pp1_03[70]), //i-- + .sum(pp2_03[70]), //o-- + .car(pp2_02[69]) //o-- + ); + + tri_fu_csa22_h2 pp2_01_csa_69( + .a(pp1_05[69]), //i-- + .b(pp1_04[69]), //i-- + .sum(pp2_03[69]), //o-- + .car(pp2_02[68]) //o-- + ); + + tri_csa32 pp2_01_csa_68( + .vd(vdd), + .gd(gnd), + .a(pp1_05[68]), //i-- + .b(pp1_04[68]), //i-- + .c(pp1_03[68]), //i-- + .sum(pp2_03[68]), //o-- + .car(pp2_02[67]) //o-- + ); + + tri_csa32 pp2_01_csa_67( + .vd(vdd), + .gd(gnd), + .a(pp1_05[67]), //i-- + .b(pp1_04[67]), //i-- + .c(pp1_03[67]), //i-- + .sum(pp2_03[67]), //o-- + .car(pp2_02[66]) //o-- + ); + + tri_csa32 pp2_01_csa_66( + .vd(vdd), + .gd(gnd), + .a(pp1_05[66]), //i-- + .b(pp1_04[66]), //i-- + .c(pp1_03[66]), //i-- + .sum(pp2_03[66]), //o-- + .car(pp2_02[65]) //o-- + ); + + tri_csa32 pp2_01_csa_65( + .vd(vdd), + .gd(gnd), + .a(pp1_05[65]), //i-- + .b(pp1_04[65]), //i-- + .c(pp1_03[65]), //i-- + .sum(pp2_03[65]), //o-- + .car(pp2_02[64]) //o-- + ); + + tri_csa32 pp2_01_csa_64( + .vd(vdd), + .gd(gnd), + .a(pp1_05[64]), //i-- + .b(pp1_04[64]), //i-- + .c(pp1_03[64]), //i-- + .sum(pp2_03[64]), //o-- + .car(pp2_02[63]) //o-- + ); + + tri_csa32 pp2_01_csa_63( + .vd(vdd), + .gd(gnd), + .a(pp1_05[63]), //i-- + .b(pp1_04[63]), //i-- + .c(pp1_03[63]), //i-- + .sum(pp2_03[63]), //o-- + .car(pp2_02[62]) //o-- + ); + + tri_csa32 pp2_01_csa_62( + .vd(vdd), + .gd(gnd), + .a(pp1_05[62]), //i-- + .b(pp1_04[62]), //i-- + .c(pp1_03[62]), //i-- + .sum(pp2_03[62]), //o-- + .car(pp2_02[61]) //o-- + ); + + tri_csa32 pp2_01_csa_61( + .vd(vdd), + .gd(gnd), + .a(pp1_05[61]), //i-- + .b(pp1_04[61]), //i-- + .c(pp1_03[61]), //i-- + .sum(pp2_03[61]), //o-- + .car(pp2_02[60]) //o-- + ); + + tri_csa32 pp2_01_csa_60( + .vd(vdd), + .gd(gnd), + .a(pp1_05[60]), //i-- + .b(pp1_04[60]), //i-- + .c(pp1_03[60]), //i-- + .sum(pp2_03[60]), //o-- + .car(pp2_02[59]) //o-- + ); + + tri_csa32 pp2_01_csa_59( + .vd(vdd), + .gd(gnd), + .a(pp1_05[59]), //i-- + .b(pp1_04[59]), //i-- + .c(pp1_03[59]), //i-- + .sum(pp2_03[59]), //o-- + .car(pp2_02[58]) //o-- + ); + + tri_csa32 pp2_01_csa_58( + .vd(vdd), + .gd(gnd), + .a(pp1_05[58]), //i-- + .b(pp1_04[58]), //i-- + .c(pp1_03[58]), //i-- + .sum(pp2_03[58]), //o-- + .car(pp2_02[57]) //o-- + ); + + tri_csa32 pp2_01_csa_57( + .vd(vdd), + .gd(gnd), + .a(pp1_05[57]), //i-- + .b(pp1_04[57]), //i-- + .c(pp1_03[57]), //i-- + .sum(pp2_03[57]), //o-- + .car(pp2_02[56]) //o-- + ); + + tri_csa32 pp2_01_csa_56( + .vd(vdd), + .gd(gnd), + .a(pp1_05[56]), //i-- + .b(pp1_04[56]), //i-- + .c(pp1_03[56]), //i-- + .sum(pp2_03[56]), //o-- + .car(pp2_02[55]) //o-- + ); + + tri_csa32 pp2_01_csa_55( + .vd(vdd), + .gd(gnd), + .a(pp1_05[55]), //i-- + .b(pp1_04[55]), //i-- + .c(pp1_03[55]), //i-- + .sum(pp2_03[55]), //o-- + .car(pp2_02[54]) //o-- + ); + + tri_csa32 pp2_01_csa_54( + .vd(vdd), + .gd(gnd), + .a(pp1_05[54]), //i-- + .b(pp1_04[54]), //i-- + .c(pp1_03[54]), //i-- + .sum(pp2_03[54]), //o-- + .car(pp2_02[53]) //o-- + ); + + tri_csa32 pp2_01_csa_53( + .vd(vdd), + .gd(gnd), + .a(pp1_05[53]), //i-- + .b(pp1_04[53]), //i-- + .c(pp1_03[53]), //i-- + .sum(pp2_03[53]), //o-- + .car(pp2_02[52]) //o-- + ); + + tri_csa32 pp2_01_csa_52( + .vd(vdd), + .gd(gnd), + .a(pp1_05[52]), //i-- + .b(pp1_04[52]), //i-- + .c(pp1_03[52]), //i-- + .sum(pp2_03[52]), //o-- + .car(pp2_02[51]) //o-- + ); + + tri_csa32 pp2_01_csa_51( + .vd(vdd), + .gd(gnd), + .a(pp1_05[51]), //i-- + .b(pp1_04[51]), //i-- + .c(pp1_03[51]), //i-- + .sum(pp2_03[51]), //o-- + .car(pp2_02[50]) //o-- + ); + + tri_csa32 pp2_01_csa_50( + .vd(vdd), + .gd(gnd), + .a(pp1_05[50]), //i-- + .b(pp1_04[50]), //i-- + .c(pp1_03[50]), //i-- + .sum(pp2_03[50]), //o-- + .car(pp2_02[49]) //o-- + ); + + tri_csa32 pp2_01_csa_49( + .vd(vdd), + .gd(gnd), + .a(pp1_05[49]), //i-- + .b(pp1_04[49]), //i-- + .c(pp1_03[49]), //i-- + .sum(pp2_03[49]), //o-- + .car(pp2_02[48]) //o-- + ); + + tri_csa32 pp2_01_csa_48( + .vd(vdd), + .gd(gnd), + .a(pp1_05[48]), //i-- + .b(pp1_04[48]), //i-- + .c(pp1_03[48]), //i-- + .sum(pp2_03[48]), //o-- + .car(pp2_02[47]) //o-- + ); + + tri_csa32 pp2_01_csa_47( + .vd(vdd), + .gd(gnd), + .a(pp1_05[47]), //i-- + .b(pp1_04[47]), //i-- + .c(pp1_03[47]), //i-- + .sum(pp2_03[47]), //o-- + .car(pp2_02[46]) //o-- + ); + + tri_csa32 pp2_01_csa_46( + .vd(vdd), + .gd(gnd), + .a(pp1_05[46]), //i-- + .b(pp1_04[46]), //i-- + .c(pp1_03[46]), //i-- + .sum(pp2_03[46]), //o-- + .car(pp2_02[45]) //o-- + ); + + tri_csa32 pp2_01_csa_45( + .vd(vdd), + .gd(gnd), + .a(pp1_05[45]), //i-- + .b(pp1_04[45]), //i-- + .c(pp1_03[45]), //i-- + .sum(pp2_03[45]), //o-- + .car(pp2_02[44]) //o-- + ); + + tri_csa32 pp2_01_csa_44( + .vd(vdd), + .gd(gnd), + .a(pp1_05[44]), //i-- + .b(pp1_04[44]), //i-- + .c(pp1_03[44]), //i-- + .sum(pp2_03[44]), //o-- + .car(pp2_02[43]) //o-- + ); + + tri_csa32 pp2_01_csa_43( + .vd(vdd), + .gd(gnd), + .a(pp1_05[43]), //i-- + .b(pp1_04[43]), //i-- + .c(pp1_03[43]), //i-- + .sum(pp2_03[43]), //o-- + .car(pp2_02[42]) //o-- + ); + + tri_csa32 pp2_01_csa_42( + .vd(vdd), + .gd(gnd), + .a(pp1_05[42]), //i-- + .b(pp1_04[42]), //i-- + .c(pp1_03[42]), //i-- + .sum(pp2_03[42]), //o-- + .car(pp2_02[41]) //o-- + ); + + tri_csa32 pp2_01_csa_41( + .vd(vdd), + .gd(gnd), + .a(pp1_05[41]), //i-- + .b(pp1_04[41]), //i-- + .c(pp1_03[41]), //i-- + .sum(pp2_03[41]), //o-- + .car(pp2_02[40]) //o-- + ); + + tri_csa32 pp2_01_csa_40( + .vd(vdd), + .gd(gnd), + .a(pp1_05[40]), //i-- + .b(pp1_04[40]), //i-- + .c(pp1_03[40]), //i-- + .sum(pp2_03[40]), //o-- + .car(pp2_02[39]) //o-- + ); + + tri_csa32 pp2_01_csa_39( + .vd(vdd), + .gd(gnd), + .a(pp1_05[39]), //i-- + .b(pp1_04[39]), //i-- + .c(pp1_03[39]), //i-- + .sum(pp2_03[39]), //o-- + .car(pp2_02[38]) //o-- + ); + + tri_csa32 pp2_01_csa_38( + .vd(vdd), + .gd(gnd), + .a(pp1_05[38]), //i-- + .b(pp1_04[38]), //i-- + .c(pp1_03[38]), //i-- + .sum(pp2_03[38]), //o-- + .car(pp2_02[37]) //o-- + ); + + tri_csa32 pp2_01_csa_37( + .vd(vdd), + .gd(gnd), + .a(pp1_05[37]), //i-- + .b(pp1_04[37]), //i-- + .c(pp1_03[37]), //i-- + .sum(pp2_03[37]), //o-- + .car(pp2_02[36]) //o-- + ); + + tri_csa32 pp2_01_csa_36( + .vd(vdd), + .gd(gnd), + .a(pp1_05[36]), //i-- + .b(pp1_04[36]), //i-- + .c(pp1_03[36]), //i-- + .sum(pp2_03[36]), //o-- + .car(pp2_02[35]) //o-- + ); + + tri_csa32 pp2_01_csa_35( + .vd(vdd), + .gd(gnd), + .a(pp1_05[35]), //i-- + .b(pp1_04[35]), //i-- + .c(pp1_03[35]), //i-- + .sum(pp2_03[35]), //o-- + .car(pp2_02[34]) //o-- + ); + + tri_csa32 pp2_01_csa_34( + .vd(vdd), + .gd(gnd), + .a(pp1_05[34]), //i-- + .b(pp1_04[34]), //i-- + .c(pp1_03[34]), //i-- + .sum(pp2_03[34]), //o-- + .car(pp2_02[33]) //o-- + ); + + tri_csa32 pp2_01_csa_33( + .vd(vdd), + .gd(gnd), + .a(pp1_05[33]), //i-- + .b(pp1_04[33]), //i-- + .c(pp1_03[33]), //i-- + .sum(pp2_03[33]), //o-- + .car(pp2_02[32]) //o-- + ); + + tri_csa32 pp2_01_csa_32( + .vd(vdd), + .gd(gnd), + .a(pp1_05[32]), //i-- + .b(pp1_04[32]), //i-- + .c(pp1_03[32]), //i-- + .sum(pp2_03[32]), //o-- + .car(pp2_02[31]) //o-- + ); + + tri_csa32 pp2_01_csa_31( + .vd(vdd), + .gd(gnd), + .a(pp1_05[31]), //i-- + .b(pp1_04[31]), //i-- + .c(pp1_03[31]), //i-- + .sum(pp2_03[31]), //o-- + .car(pp2_02[30]) //o-- + ); + + tri_csa32 pp2_01_csa_30( + .vd(vdd), + .gd(gnd), + .a(pp1_05[30]), //i-- + .b(pp1_04[30]), //i-- + .c(pp1_03[30]), //i-- + .sum(pp2_03[30]), //o-- + .car(pp2_02[29]) //o-- + ); + + tri_csa32 pp2_01_csa_29( + .vd(vdd), + .gd(gnd), + .a(pp1_05[29]), //i-- + .b(pp1_04[29]), //i-- + .c(pp1_03[29]), //i-- + .sum(pp2_03[29]), //o-- + .car(pp2_02[28]) //o-- + ); + + tri_csa32 pp2_01_csa_28( + .vd(vdd), + .gd(gnd), + .a(pp1_05[28]), //i-- + .b(pp1_04[28]), //i-- + .c(pp1_03[28]), //i-- + .sum(pp2_03[28]), //o-- + .car(pp2_02[27]) //o-- + ); + + tri_csa32 pp2_01_csa_27( + .vd(vdd), + .gd(gnd), + .a(pp1_05[27]), //i-- + .b(pp1_04[27]), //i-- + .c(pp1_03[27]), //i-- + .sum(pp2_03[27]), //o-- + .car(pp2_02[26]) //o-- + ); + + tri_csa32 pp2_01_csa_26( + .vd(vdd), + .gd(gnd), + .a(pp1_05[26]), //i-- + .b(pp1_04[26]), //i-- + .c(pp1_03[26]), //i-- + .sum(pp2_03[26]), //o-- + .car(pp2_02[25]) //o-- + ); + + tri_csa32 pp2_01_csa_25( + .vd(vdd), + .gd(gnd), + .a(pp1_05[25]), //i-- + .b(pp1_04[25]), //i-- + .c(pp1_03[25]), //i-- + .sum(pp2_03[25]), //o-- + .car(pp2_02[24]) //o-- + ); + + tri_csa32 pp2_01_csa_24( + .vd(vdd), + .gd(gnd), + .a(pp1_05[24]), //i-- + .b(pp1_04[24]), //i-- + .c(pp1_03[24]), //i-- + .sum(pp2_03[24]), //o-- + .car(pp2_02[23]) //o-- + ); + + tri_csa32 pp2_01_csa_23( + .vd(vdd), + .gd(gnd), + .a(pp1_05[23]), //i-- + .b(pp1_04[23]), //i-- + .c(pp1_03[23]), //i-- + .sum(pp2_03[23]), //o-- + .car(pp2_02[22]) //o-- + ); + + tri_csa32 pp2_01_csa_22( + .vd(vdd), + .gd(gnd), + .a(pp1_05[22]), //i-- + .b(pp1_04[22]), //i-- + .c(pp1_03[22]), //i-- + .sum(pp2_03[22]), //o-- + .car(pp2_02[21]) //o-- + ); + + tri_csa32 pp2_01_csa_21( + .vd(vdd), + .gd(gnd), + .a(pp1_05[21]), //i-- + .b(pp1_04[21]), //i-- + .c(pp1_03[21]), //i-- + .sum(pp2_03[21]), //o-- + .car(pp2_02[20]) //o-- + ); + + tri_csa32 pp2_01_csa_20( + .vd(vdd), + .gd(gnd), + .a(pp1_05[20]), //i-- + .b(pp1_04[20]), //i-- + .c(pp1_03[20]), //i-- + .sum(pp2_03[20]), //o-- + .car(pp2_02[19]) //o-- + ); + + tri_csa32 pp2_01_csa_19( + .vd(vdd), + .gd(gnd), + .a(pp1_05[19]), //i-- + .b(pp1_04[19]), //i-- + .c(pp1_03[19]), //i-- + .sum(pp2_03[19]), //o-- + .car(pp2_02[18]) //o-- + ); + + tri_csa32 pp2_01_csa_18( + .vd(vdd), + .gd(gnd), + .a(pp1_05[18]), //i-- + .b(pp1_04[18]), //i-- + .c(pp1_03[18]), //i-- + .sum(pp2_03[18]), //o-- + .car(pp2_02[17]) //o-- + ); + + tri_csa32 pp2_01_csa_17( + .vd(vdd), + .gd(gnd), + .a(pp1_05[17]), //i-- + .b(pp1_04[17]), //i-- + .c(pp1_03[17]), //i-- + .sum(pp2_03[17]), //o-- + .car(pp2_02[16]) //o-- + ); + + tri_csa32 pp2_01_csa_16( + .vd(vdd), + .gd(gnd), + .a(pp1_05[16]), //i-- + .b(pp1_04[16]), //i-- + .c(pp1_03[16]), //i-- + .sum(pp2_03[16]), //o-- + .car(pp2_02[15]) //o-- + ); + + tri_csa32 pp2_01_csa_15( + .vd(vdd), + .gd(gnd), + .a(pp1_05[15]), //i-- + .b(pp1_04[15]), //i-- + .c(pp1_03[15]), //i-- + .sum(pp2_03[15]), //o-- + .car(pp2_02[14]) //o-- + ); + + tri_fu_csa22_h2 pp2_01_csa_14( + .a(tiup), //i-- + .b(pp1_03[14]), //i-- + .sum(pp2_03[14]), //o-- + .car(pp2_02[13]) //o-- + ); + assign pp2_03[13] = pp1_03[13]; + assign pp2_03[12] = pp1_03[12]; + assign pp2_03[11] = pp1_03[11]; + assign pp2_03[10] = pp1_03[10]; + assign pp2_03[9] = pp1_03[9]; + assign pp2_03[8] = tiup; + + ////# 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111111 + ////# 0000000000111111111122222222223333333333444444444455555555556666666666777777777788888888889999999999000000000 + ////# 0123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678 + ////# ........occccccccccccccccccccccccccccccccccccccccccccccccccccccccc__o........................................ pp1_02 + ////# ...ouuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuoo_o............................................ pp1_01 + ////# ..occccccccccccccccccccccccccccccccccccccccccccccccccccccccc__o.............................................. pp1_00 + ////# ------------------------------------------------------------------------------------- + ////# 222223333333333333333333333333333333333333333333333333333223 + ////# ..ouuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuooo__o........................................ pp2_01 + ////# ..cccccccccccccccccccccccccccccccccccccccccccccccccccccccccccc__o............................................ pp2_00 + + assign pp2_01[68] = pp1_02[68]; + assign pp2_01[67] = tidn; + assign pp2_01[66] = tidn; + assign pp2_01[65] = pp1_02[65]; + assign pp2_01[64] = pp1_02[64]; + assign pp2_01[63] = pp1_02[63]; + + assign pp2_00[64] = pp1_01[64]; + assign pp2_00[63] = tidn; + assign pp2_00[62] = tidn; + + + tri_csa32 pp2_00_csa_62( + .vd(vdd), + .gd(gnd), + .a(pp1_02[62]), //i-- + .b(pp1_01[62]), //i-- + .c(pp1_00[62]), //i-- + .sum(pp2_01[62]), //o-- + .car(pp2_00[61]) //o-- + ); + + tri_fu_csa22_h2 pp2_00_csa_61( + .a(pp1_02[61]), //i-- + .b(pp1_01[61]), //i-- + .sum(pp2_01[61]), //o-- + .car(pp2_00[60]) //o-- + ); + + tri_fu_csa22_h2 pp2_00_csa_60( + .a(pp1_02[60]), //i-- + .b(pp1_01[60]), //i-- + .sum(pp2_01[60]), //o-- + .car(pp2_00[59]) //o-- + ); + + tri_csa32 pp2_00_csa_59( + .vd(vdd), + .gd(gnd), + .a(pp1_02[59]), //i-- + .b(pp1_01[59]), //i-- + .c(pp1_00[59]), //i-- + .sum(pp2_01[59]), //o-- + .car(pp2_00[58]) //o-- + ); + + tri_csa32 pp2_00_csa_58( + .vd(vdd), + .gd(gnd), + .a(pp1_02[58]), //i-- + .b(pp1_01[58]), //i-- + .c(pp1_00[58]), //i-- + .sum(pp2_01[58]), //o-- + .car(pp2_00[57]) //o-- + ); + + tri_csa32 pp2_00_csa_57( + .vd(vdd), + .gd(gnd), + .a(pp1_02[57]), //i-- + .b(pp1_01[57]), //i-- + .c(pp1_00[57]), //i-- + .sum(pp2_01[57]), //o-- + .car(pp2_00[56]) //o-- + ); + + tri_csa32 pp2_00_csa_56( + .vd(vdd), + .gd(gnd), + .a(pp1_02[56]), //i-- + .b(pp1_01[56]), //i-- + .c(pp1_00[56]), //i-- + .sum(pp2_01[56]), //o-- + .car(pp2_00[55]) //o-- + ); + + tri_csa32 pp2_00_csa_55( + .vd(vdd), + .gd(gnd), + .a(pp1_02[55]), //i-- + .b(pp1_01[55]), //i-- + .c(pp1_00[55]), //i-- + .sum(pp2_01[55]), //o-- + .car(pp2_00[54]) //o-- + ); + + tri_csa32 pp2_00_csa_54( + .vd(vdd), + .gd(gnd), + .a(pp1_02[54]), //i-- + .b(pp1_01[54]), //i-- + .c(pp1_00[54]), //i-- + .sum(pp2_01[54]), //o-- + .car(pp2_00[53]) //o-- + ); + + tri_csa32 pp2_00_csa_53( + .vd(vdd), + .gd(gnd), + .a(pp1_02[53]), //i-- + .b(pp1_01[53]), //i-- + .c(pp1_00[53]), //i-- + .sum(pp2_01[53]), //o-- + .car(pp2_00[52]) //o-- + ); + + tri_csa32 pp2_00_csa_52( + .vd(vdd), + .gd(gnd), + .a(pp1_02[52]), //i-- + .b(pp1_01[52]), //i-- + .c(pp1_00[52]), //i-- + .sum(pp2_01[52]), //o-- + .car(pp2_00[51]) //o-- + ); + + tri_csa32 pp2_00_csa_51( + .vd(vdd), + .gd(gnd), + .a(pp1_02[51]), //i-- + .b(pp1_01[51]), //i-- + .c(pp1_00[51]), //i-- + .sum(pp2_01[51]), //o-- + .car(pp2_00[50]) //o-- + ); + + tri_csa32 pp2_00_csa_50( + .vd(vdd), + .gd(gnd), + .a(pp1_02[50]), //i-- + .b(pp1_01[50]), //i-- + .c(pp1_00[50]), //i-- + .sum(pp2_01[50]), //o-- + .car(pp2_00[49]) //o-- + ); + + tri_csa32 pp2_00_csa_49( + .vd(vdd), + .gd(gnd), + .a(pp1_02[49]), //i-- + .b(pp1_01[49]), //i-- + .c(pp1_00[49]), //i-- + .sum(pp2_01[49]), //o-- + .car(pp2_00[48]) //o-- + ); + + tri_csa32 pp2_00_csa_48( + .vd(vdd), + .gd(gnd), + .a(pp1_02[48]), //i-- + .b(pp1_01[48]), //i-- + .c(pp1_00[48]), //i-- + .sum(pp2_01[48]), //o-- + .car(pp2_00[47]) //o-- + ); + + tri_csa32 pp2_00_csa_47( + .vd(vdd), + .gd(gnd), + .a(pp1_02[47]), //i-- + .b(pp1_01[47]), //i-- + .c(pp1_00[47]), //i-- + .sum(pp2_01[47]), //o-- + .car(pp2_00[46]) //o-- + ); + + tri_csa32 pp2_00_csa_46( + .vd(vdd), + .gd(gnd), + .a(pp1_02[46]), //i-- + .b(pp1_01[46]), //i-- + .c(pp1_00[46]), //i-- + .sum(pp2_01[46]), //o-- + .car(pp2_00[45]) //o-- + ); + + tri_csa32 pp2_00_csa_45( + .vd(vdd), + .gd(gnd), + .a(pp1_02[45]), //i-- + .b(pp1_01[45]), //i-- + .c(pp1_00[45]), //i-- + .sum(pp2_01[45]), //o-- + .car(pp2_00[44]) //o-- + ); + + tri_csa32 pp2_00_csa_44( + .vd(vdd), + .gd(gnd), + .a(pp1_02[44]), //i-- + .b(pp1_01[44]), //i-- + .c(pp1_00[44]), //i-- + .sum(pp2_01[44]), //o-- + .car(pp2_00[43]) //o-- + ); + + tri_csa32 pp2_00_csa_43( + .vd(vdd), + .gd(gnd), + .a(pp1_02[43]), //i-- + .b(pp1_01[43]), //i-- + .c(pp1_00[43]), //i-- + .sum(pp2_01[43]), //o-- + .car(pp2_00[42]) //o-- + ); + + tri_csa32 pp2_00_csa_42( + .vd(vdd), + .gd(gnd), + .a(pp1_02[42]), //i-- + .b(pp1_01[42]), //i-- + .c(pp1_00[42]), //i-- + .sum(pp2_01[42]), //o-- + .car(pp2_00[41]) //o-- + ); + + tri_csa32 pp2_00_csa_41( + .vd(vdd), + .gd(gnd), + .a(pp1_02[41]), //i-- + .b(pp1_01[41]), //i-- + .c(pp1_00[41]), //i-- + .sum(pp2_01[41]), //o-- + .car(pp2_00[40]) //o-- + ); + + tri_csa32 pp2_00_csa_40( + .vd(vdd), + .gd(gnd), + .a(pp1_02[40]), //i-- + .b(pp1_01[40]), //i-- + .c(pp1_00[40]), //i-- + .sum(pp2_01[40]), //o-- + .car(pp2_00[39]) //o-- + ); + + tri_csa32 pp2_00_csa_39( + .vd(vdd), + .gd(gnd), + .a(pp1_02[39]), //i-- + .b(pp1_01[39]), //i-- + .c(pp1_00[39]), //i-- + .sum(pp2_01[39]), //o-- + .car(pp2_00[38]) //o-- + ); + + tri_csa32 pp2_00_csa_38( + .vd(vdd), + .gd(gnd), + .a(pp1_02[38]), //i-- + .b(pp1_01[38]), //i-- + .c(pp1_00[38]), //i-- + .sum(pp2_01[38]), //o-- + .car(pp2_00[37]) //o-- + ); + + tri_csa32 pp2_00_csa_37( + .vd(vdd), + .gd(gnd), + .a(pp1_02[37]), //i-- + .b(pp1_01[37]), //i-- + .c(pp1_00[37]), //i-- + .sum(pp2_01[37]), //o-- + .car(pp2_00[36]) //o-- + ); + + tri_csa32 pp2_00_csa_36( + .vd(vdd), + .gd(gnd), + .a(pp1_02[36]), //i-- + .b(pp1_01[36]), //i-- + .c(pp1_00[36]), //i-- + .sum(pp2_01[36]), //o-- + .car(pp2_00[35]) //o-- + ); + + tri_csa32 pp2_00_csa_35( + .vd(vdd), + .gd(gnd), + .a(pp1_02[35]), //i-- + .b(pp1_01[35]), //i-- + .c(pp1_00[35]), //i-- + .sum(pp2_01[35]), //o-- + .car(pp2_00[34]) //o-- + ); + + tri_csa32 pp2_00_csa_34( + .vd(vdd), + .gd(gnd), + .a(pp1_02[34]), //i-- + .b(pp1_01[34]), //i-- + .c(pp1_00[34]), //i-- + .sum(pp2_01[34]), //o-- + .car(pp2_00[33]) //o-- + ); + + tri_csa32 pp2_00_csa_33( + .vd(vdd), + .gd(gnd), + .a(pp1_02[33]), //i-- + .b(pp1_01[33]), //i-- + .c(pp1_00[33]), //i-- + .sum(pp2_01[33]), //o-- + .car(pp2_00[32]) //o-- + ); + + tri_csa32 pp2_00_csa_32( + .vd(vdd), + .gd(gnd), + .a(pp1_02[32]), //i-- + .b(pp1_01[32]), //i-- + .c(pp1_00[32]), //i-- + .sum(pp2_01[32]), //o-- + .car(pp2_00[31]) //o-- + ); + + tri_csa32 pp2_00_csa_31( + .vd(vdd), + .gd(gnd), + .a(pp1_02[31]), //i-- + .b(pp1_01[31]), //i-- + .c(pp1_00[31]), //i-- + .sum(pp2_01[31]), //o-- + .car(pp2_00[30]) //o-- + ); + + tri_csa32 pp2_00_csa_30( + .vd(vdd), + .gd(gnd), + .a(pp1_02[30]), //i-- + .b(pp1_01[30]), //i-- + .c(pp1_00[30]), //i-- + .sum(pp2_01[30]), //o-- + .car(pp2_00[29]) //o-- + ); + + tri_csa32 pp2_00_csa_29( + .vd(vdd), + .gd(gnd), + .a(pp1_02[29]), //i-- + .b(pp1_01[29]), //i-- + .c(pp1_00[29]), //i-- + .sum(pp2_01[29]), //o-- + .car(pp2_00[28]) //o-- + ); + + tri_csa32 pp2_00_csa_28( + .vd(vdd), + .gd(gnd), + .a(pp1_02[28]), //i-- + .b(pp1_01[28]), //i-- + .c(pp1_00[28]), //i-- + .sum(pp2_01[28]), //o-- + .car(pp2_00[27]) //o-- + ); + + tri_csa32 pp2_00_csa_27( + .vd(vdd), + .gd(gnd), + .a(pp1_02[27]), //i-- + .b(pp1_01[27]), //i-- + .c(pp1_00[27]), //i-- + .sum(pp2_01[27]), //o-- + .car(pp2_00[26]) //o-- + ); + + tri_csa32 pp2_00_csa_26( + .vd(vdd), + .gd(gnd), + .a(pp1_02[26]), //i-- + .b(pp1_01[26]), //i-- + .c(pp1_00[26]), //i-- + .sum(pp2_01[26]), //o-- + .car(pp2_00[25]) //o-- + ); + + tri_csa32 pp2_00_csa_25( + .vd(vdd), + .gd(gnd), + .a(pp1_02[25]), //i-- + .b(pp1_01[25]), //i-- + .c(pp1_00[25]), //i-- + .sum(pp2_01[25]), //o-- + .car(pp2_00[24]) //o-- + ); + + tri_csa32 pp2_00_csa_24( + .vd(vdd), + .gd(gnd), + .a(pp1_02[24]), //i-- + .b(pp1_01[24]), //i-- + .c(pp1_00[24]), //i-- + .sum(pp2_01[24]), //o-- + .car(pp2_00[23]) //o-- + ); + + tri_csa32 pp2_00_csa_23( + .vd(vdd), + .gd(gnd), + .a(pp1_02[23]), //i-- + .b(pp1_01[23]), //i-- + .c(pp1_00[23]), //i-- + .sum(pp2_01[23]), //o-- + .car(pp2_00[22]) //o-- + ); + + tri_csa32 pp2_00_csa_22( + .vd(vdd), + .gd(gnd), + .a(pp1_02[22]), //i-- + .b(pp1_01[22]), //i-- + .c(pp1_00[22]), //i-- + .sum(pp2_01[22]), //o-- + .car(pp2_00[21]) //o-- + ); + + tri_csa32 pp2_00_csa_21( + .vd(vdd), + .gd(gnd), + .a(pp1_02[21]), //i-- + .b(pp1_01[21]), //i-- + .c(pp1_00[21]), //i-- + .sum(pp2_01[21]), //o-- + .car(pp2_00[20]) //o-- + ); + + tri_csa32 pp2_00_csa_20( + .vd(vdd), + .gd(gnd), + .a(pp1_02[20]), //i-- + .b(pp1_01[20]), //i-- + .c(pp1_00[20]), //i-- + .sum(pp2_01[20]), //o-- + .car(pp2_00[19]) //o-- + ); + + tri_csa32 pp2_00_csa_19( + .vd(vdd), + .gd(gnd), + .a(pp1_02[19]), //i-- + .b(pp1_01[19]), //i-- + .c(pp1_00[19]), //i-- + .sum(pp2_01[19]), //o-- + .car(pp2_00[18]) //o-- + ); + + tri_csa32 pp2_00_csa_18( + .vd(vdd), + .gd(gnd), + .a(pp1_02[18]), //i-- + .b(pp1_01[18]), //i-- + .c(pp1_00[18]), //i-- + .sum(pp2_01[18]), //o-- + .car(pp2_00[17]) //o-- + ); + + tri_csa32 pp2_00_csa_17( + .vd(vdd), + .gd(gnd), + .a(pp1_02[17]), //i-- + .b(pp1_01[17]), //i-- + .c(pp1_00[17]), //i-- + .sum(pp2_01[17]), //o-- + .car(pp2_00[16]) //o-- + ); + + tri_csa32 pp2_00_csa_16( + .vd(vdd), + .gd(gnd), + .a(pp1_02[16]), //i-- + .b(pp1_01[16]), //i-- + .c(pp1_00[16]), //i-- + .sum(pp2_01[16]), //o-- + .car(pp2_00[15]) //o-- + ); + + tri_csa32 pp2_00_csa_15( + .vd(vdd), + .gd(gnd), + .a(pp1_02[15]), //i-- + .b(pp1_01[15]), //i-- + .c(pp1_00[15]), //i-- + .sum(pp2_01[15]), //o-- + .car(pp2_00[14]) //o-- + ); + + tri_csa32 pp2_00_csa_14( + .vd(vdd), + .gd(gnd), + .a(pp1_02[14]), //i-- + .b(pp1_01[14]), //i-- + .c(pp1_00[14]), //i-- + .sum(pp2_01[14]), //o-- + .car(pp2_00[13]) //o-- + ); + + tri_csa32 pp2_00_csa_13( + .vd(vdd), + .gd(gnd), + .a(pp1_02[13]), //i-- + .b(pp1_01[13]), //i-- + .c(pp1_00[13]), //i-- + .sum(pp2_01[13]), //o-- + .car(pp2_00[12]) //o-- + ); + + tri_csa32 pp2_00_csa_12( + .vd(vdd), + .gd(gnd), + .a(pp1_02[12]), //i-- + .b(pp1_01[12]), //i-- + .c(pp1_00[12]), //i-- + .sum(pp2_01[12]), //o-- + .car(pp2_00[11]) //o-- + ); + + tri_csa32 pp2_00_csa_11( + .vd(vdd), + .gd(gnd), + .a(pp1_02[11]), //i-- + .b(pp1_01[11]), //i-- + .c(pp1_00[11]), //i-- + .sum(pp2_01[11]), //o-- + .car(pp2_00[10]) //o-- + ); + + tri_csa32 pp2_00_csa_10( + .vd(vdd), + .gd(gnd), + .a(pp1_02[10]), //i-- + .b(pp1_01[10]), //i-- + .c(pp1_00[10]), //i-- + .sum(pp2_01[10]), //o-- + .car(pp2_00[9]) //o-- + ); + + tri_csa32 pp2_00_csa_09( + .vd(vdd), + .gd(gnd), + .a(pp1_02[9]), //i-- + .b(pp1_01[9]), //i-- + .c(pp1_00[9]), //i-- + .sum(pp2_01[9]), //o-- + .car(pp2_00[8]) //o-- + ); + + tri_fu_csa22_h2 pp2_00_csa_08( + .a(pp1_01[8]), //i-- + .b(pp1_00[8]), //i-- + .sum(pp2_01[8]), //o-- + .car(pp2_00[7]) //o-- + ); + + tri_fu_csa22_h2 pp2_00_csa_07( + .a(pp1_01[7]), //i-- + .b(pp1_00[7]), //i-- + .sum(pp2_01[7]), //o-- + .car(pp2_00[6]) //o-- + ); + + tri_fu_csa22_h2 pp2_00_csa_06( + .a(pp1_01[6]), //i-- + .b(pp1_00[6]), //i-- + .sum(pp2_01[6]), //o-- + .car(pp2_00[5]) //o-- + ); + + tri_fu_csa22_h2 pp2_00_csa_05( + .a(pp1_01[5]), //i-- + .b(pp1_00[5]), //i-- + .sum(pp2_01[5]), //o-- + .car(pp2_00[4]) //o-- + ); + + tri_fu_csa22_h2 pp2_00_csa_04( + .a(pp1_01[4]), //i-- + .b(pp1_00[4]), //i-- + .sum(pp2_01[4]), //o-- + .car(pp2_00[3]) //o-- + ); + + tri_fu_csa22_h2 pp2_00_csa_03( + .a(pp1_01[3]), //i-- + .b(pp1_00[3]), //i-- + .sum(pp2_01[3]), //o-- + .car(pp2_00[2]) //o-- + ); + assign pp2_01[2] = pp1_01[2]; + + ////################################################## + ////# Compressor Level 3 + ////################################################## + + ////# 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111111 + ////# 0000000000111111111122222222223333333333444444444455555555556666666666777777777788888888889999999999000000000 + ////# 0123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678 + ////# .........ooooouuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuoooo.................................. pp2_03 + ////# .............ccccccccccccccccccccccccccccccccccccccccccccccccccccccccc_o__o.................................. pp2_02 + ////# ..ouuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuooo__o........................................ pp2_01 + ////# ..cccccccccccccccccccccccccccccccccccccccccccccccccccccccccccc__o............................................ pp2_00 + ////# ---------------------------------------------------------------------------------------------------------- + ////# ..2222223333344444444444444444444444444444444444444444444444443343223........................................ + ////# ..uuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuuoooooo.................................. pp3_01 + ////# .ccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccccc_o_o__o.................................. pp3_00 + + assign pp3_01[74] = pp2_03[74]; + assign pp3_01[73] = pp2_03[73]; + assign pp3_01[72] = pp2_03[72]; + assign pp3_01[71] = pp2_03[71]; + assign pp3_01[70] = pp2_03[70]; + assign pp3_01[69] = pp2_03[69]; + + assign pp3_00[74] = pp2_02[74]; + assign pp3_00[73] = tidn; + assign pp3_00[72] = tidn; + assign pp3_00[71] = pp2_02[71]; + assign pp3_00[70] = tidn; + assign pp3_00[69] = pp2_02[69]; + assign pp3_00[68] = tidn; + + + tri_csa32 pp3_00_csa_68( + .vd(vdd), + .gd(gnd), + .a(pp2_03[68]), //i-- + .b(pp2_02[68]), //i-- + .c(pp2_01[68]), //i-- + .sum(pp3_01[68]), //o-- + .car(pp3_00[67]) //o-- + ); + + tri_fu_csa22_h2 pp3_00_csa_67( + .a(pp2_03[67]), //i-- + .b(pp2_02[67]), //i-- + .sum(pp3_01[67]), //o-- + .car(pp3_00[66]) //o-- + ); + + tri_fu_csa22_h2 pp3_00_csa_66( + .a(pp2_03[66]), //i-- + .b(pp2_02[66]), //i-- + .sum(pp3_01[66]), //o-- + .car(pp3_00[65]) //o-- + ); + + tri_csa32 pp3_00_csa_65( + .vd(vdd), + .gd(gnd), + .a(pp2_03[65]), //i-- + .b(pp2_02[65]), //i-- + .c(pp2_01[65]), //i-- + .sum(pp3_01[65]), //o-- + .car(pp3_00[64]) //o-- + ); + + tri_csa42 pp3_00_csa_64( + .vd(vdd), + .gd(gnd), + .a(pp2_03[64]), //i-- + .b(pp2_02[64]), //i-- + .c(pp2_01[64]), //i-- + .d(pp2_00[64]), //i-- + .ki(tidn), //i-- + .ko(pp3_00_ko[63]), //o-- + .sum(pp3_01[64]), //o-- + .car(pp3_00[63]) //o-- + ); + + tri_csa42 pp3_00_csa_63( + .vd(vdd), + .gd(gnd), + .a(pp2_03[63]), //i-- + .b(pp2_02[63]), //i-- + .c(pp2_01[63]), //i-- + .d(tidn), //i-- + .ki(pp3_00_ko[63]), //i-- + .ko(pp3_00_ko[62]), //o-- + .sum(pp3_01[63]), //o-- + .car(pp3_00[62]) //o-- + ); + + tri_csa42 pp3_00_csa_62( + .vd(vdd), + .gd(gnd), + .a(pp2_03[62]), //i-- + .b(pp2_02[62]), //i-- + .c(pp2_01[62]), //i-- + .d(tidn), //i-- + .ki(pp3_00_ko[62]), //i-- + .ko(pp3_00_ko[61]), //o-- + .sum(pp3_01[62]), //o-- + .car(pp3_00[61]) //o-- + ); + + tri_csa42 pp3_00_csa_61( + .vd(vdd), + .gd(gnd), + .a(pp2_03[61]), //i-- + .b(pp2_02[61]), //i-- + .c(pp2_01[61]), //i-- + .d(pp2_00[61]), //i-- + .ki(pp3_00_ko[61]), //i-- + .ko(pp3_00_ko[60]), //o-- + .sum(pp3_01[61]), //o-- + .car(pp3_00[60]) //o-- + ); + + tri_csa42 pp3_00_csa_60( + .vd(vdd), + .gd(gnd), + .a(pp2_03[60]), //i-- + .b(pp2_02[60]), //i-- + .c(pp2_01[60]), //i-- + .d(pp2_00[60]), //i-- + .ki(pp3_00_ko[60]), //i-- + .ko(pp3_00_ko[59]), //o-- + .sum(pp3_01[60]), //o-- + .car(pp3_00[59]) //o-- + ); + + tri_csa42 pp3_00_csa_59( + .vd(vdd), + .gd(gnd), + .a(pp2_03[59]), //i-- + .b(pp2_02[59]), //i-- + .c(pp2_01[59]), //i-- + .d(pp2_00[59]), //i-- + .ki(pp3_00_ko[59]), //i-- + .ko(pp3_00_ko[58]), //o-- + .sum(pp3_01[59]), //o-- + .car(pp3_00[58]) //o-- + ); + + tri_csa42 pp3_00_csa_58( + .vd(vdd), + .gd(gnd), + .a(pp2_03[58]), //i-- + .b(pp2_02[58]), //i-- + .c(pp2_01[58]), //i-- + .d(pp2_00[58]), //i-- + .ki(pp3_00_ko[58]), //i-- + .ko(pp3_00_ko[57]), //o-- + .sum(pp3_01[58]), //o-- + .car(pp3_00[57]) //o-- + ); + + tri_csa42 pp3_00_csa_57( + .vd(vdd), + .gd(gnd), + .a(pp2_03[57]), //i-- + .b(pp2_02[57]), //i-- + .c(pp2_01[57]), //i-- + .d(pp2_00[57]), //i-- + .ki(pp3_00_ko[57]), //i-- + .ko(pp3_00_ko[56]), //o-- + .sum(pp3_01[57]), //o-- + .car(pp3_00[56]) //o-- + ); + + tri_csa42 pp3_00_csa_56( + .vd(vdd), + .gd(gnd), + .a(pp2_03[56]), //i-- + .b(pp2_02[56]), //i-- + .c(pp2_01[56]), //i-- + .d(pp2_00[56]), //i-- + .ki(pp3_00_ko[56]), //i-- + .ko(pp3_00_ko[55]), //o-- + .sum(pp3_01[56]), //o-- + .car(pp3_00[55]) //o-- + ); + + tri_csa42 pp3_00_csa_55( + .vd(vdd), + .gd(gnd), + .a(pp2_03[55]), //i-- + .b(pp2_02[55]), //i-- + .c(pp2_01[55]), //i-- + .d(pp2_00[55]), //i-- + .ki(pp3_00_ko[55]), //i-- + .ko(pp3_00_ko[54]), //o-- + .sum(pp3_01[55]), //o-- + .car(pp3_00[54]) //o-- + ); + + tri_csa42 pp3_00_csa_54( + .vd(vdd), + .gd(gnd), + .a(pp2_03[54]), //i-- + .b(pp2_02[54]), //i-- + .c(pp2_01[54]), //i-- + .d(pp2_00[54]), //i-- + .ki(pp3_00_ko[54]), //i-- + .ko(pp3_00_ko[53]), //o-- + .sum(pp3_01[54]), //o-- + .car(pp3_00[53]) //o-- + ); + + tri_csa42 pp3_00_csa_53( + .vd(vdd), + .gd(gnd), + .a(pp2_03[53]), //i-- + .b(pp2_02[53]), //i-- + .c(pp2_01[53]), //i-- + .d(pp2_00[53]), //i-- + .ki(pp3_00_ko[53]), //i-- + .ko(pp3_00_ko[52]), //o-- + .sum(pp3_01[53]), //o-- + .car(pp3_00[52]) //o-- + ); + + tri_csa42 pp3_00_csa_52( + .vd(vdd), + .gd(gnd), + .a(pp2_03[52]), //i-- + .b(pp2_02[52]), //i-- + .c(pp2_01[52]), //i-- + .d(pp2_00[52]), //i-- + .ki(pp3_00_ko[52]), //i-- + .ko(pp3_00_ko[51]), //o-- + .sum(pp3_01[52]), //o-- + .car(pp3_00[51]) //o-- + ); + + tri_csa42 pp3_00_csa_51( + .vd(vdd), + .gd(gnd), + .a(pp2_03[51]), //i-- + .b(pp2_02[51]), //i-- + .c(pp2_01[51]), //i-- + .d(pp2_00[51]), //i-- + .ki(pp3_00_ko[51]), //i-- + .ko(pp3_00_ko[50]), //o-- + .sum(pp3_01[51]), //o-- + .car(pp3_00[50]) //o-- + ); + + tri_csa42 pp3_00_csa_50( + .vd(vdd), + .gd(gnd), + .a(pp2_03[50]), //i-- + .b(pp2_02[50]), //i-- + .c(pp2_01[50]), //i-- + .d(pp2_00[50]), //i-- + .ki(pp3_00_ko[50]), //i-- + .ko(pp3_00_ko[49]), //o-- + .sum(pp3_01[50]), //o-- + .car(pp3_00[49]) //o-- + ); + + tri_csa42 pp3_00_csa_49( + .vd(vdd), + .gd(gnd), + .a(pp2_03[49]), //i-- + .b(pp2_02[49]), //i-- + .c(pp2_01[49]), //i-- + .d(pp2_00[49]), //i-- + .ki(pp3_00_ko[49]), //i-- + .ko(pp3_00_ko[48]), //o-- + .sum(pp3_01[49]), //o-- + .car(pp3_00[48]) //o-- + ); + + tri_csa42 pp3_00_csa_48( + .vd(vdd), + .gd(gnd), + .a(pp2_03[48]), //i-- + .b(pp2_02[48]), //i-- + .c(pp2_01[48]), //i-- + .d(pp2_00[48]), //i-- + .ki(pp3_00_ko[48]), //i-- + .ko(pp3_00_ko[47]), //o-- + .sum(pp3_01[48]), //o-- + .car(pp3_00[47]) //o-- + ); + + tri_csa42 pp3_00_csa_47( + .vd(vdd), + .gd(gnd), + .a(pp2_03[47]), //i-- + .b(pp2_02[47]), //i-- + .c(pp2_01[47]), //i-- + .d(pp2_00[47]), //i-- + .ki(pp3_00_ko[47]), //i-- + .ko(pp3_00_ko[46]), //o-- + .sum(pp3_01[47]), //o-- + .car(pp3_00[46]) //o-- + ); + + tri_csa42 pp3_00_csa_46( + .vd(vdd), + .gd(gnd), + .a(pp2_03[46]), //i-- + .b(pp2_02[46]), //i-- + .c(pp2_01[46]), //i-- + .d(pp2_00[46]), //i-- + .ki(pp3_00_ko[46]), //i-- + .ko(pp3_00_ko[45]), //o-- + .sum(pp3_01[46]), //o-- + .car(pp3_00[45]) //o-- + ); + + tri_csa42 pp3_00_csa_45( + .vd(vdd), + .gd(gnd), + .a(pp2_03[45]), //i-- + .b(pp2_02[45]), //i-- + .c(pp2_01[45]), //i-- + .d(pp2_00[45]), //i-- + .ki(pp3_00_ko[45]), //i-- + .ko(pp3_00_ko[44]), //o-- + .sum(pp3_01[45]), //o-- + .car(pp3_00[44]) //o-- + ); + + tri_csa42 pp3_00_csa_44( + .vd(vdd), + .gd(gnd), + .a(pp2_03[44]), //i-- + .b(pp2_02[44]), //i-- + .c(pp2_01[44]), //i-- + .d(pp2_00[44]), //i-- + .ki(pp3_00_ko[44]), //i-- + .ko(pp3_00_ko[43]), //o-- + .sum(pp3_01[44]), //o-- + .car(pp3_00[43]) //o-- + ); + + tri_csa42 pp3_00_csa_43( + .vd(vdd), + .gd(gnd), + .a(pp2_03[43]), //i-- + .b(pp2_02[43]), //i-- + .c(pp2_01[43]), //i-- + .d(pp2_00[43]), //i-- + .ki(pp3_00_ko[43]), //i-- + .ko(pp3_00_ko[42]), //o-- + .sum(pp3_01[43]), //o-- + .car(pp3_00[42]) //o-- + ); + + tri_csa42 pp3_00_csa_42( + .vd(vdd), + .gd(gnd), + .a(pp2_03[42]), //i-- + .b(pp2_02[42]), //i-- + .c(pp2_01[42]), //i-- + .d(pp2_00[42]), //i-- + .ki(pp3_00_ko[42]), //i-- + .ko(pp3_00_ko[41]), //o-- + .sum(pp3_01[42]), //o-- + .car(pp3_00[41]) //o-- + ); + + tri_csa42 pp3_00_csa_41( + .vd(vdd), + .gd(gnd), + .a(pp2_03[41]), //i-- + .b(pp2_02[41]), //i-- + .c(pp2_01[41]), //i-- + .d(pp2_00[41]), //i-- + .ki(pp3_00_ko[41]), //i-- + .ko(pp3_00_ko[40]), //o-- + .sum(pp3_01[41]), //o-- + .car(pp3_00[40]) //o-- + ); + + tri_csa42 pp3_00_csa_40( + .vd(vdd), + .gd(gnd), + .a(pp2_03[40]), //i-- + .b(pp2_02[40]), //i-- + .c(pp2_01[40]), //i-- + .d(pp2_00[40]), //i-- + .ki(pp3_00_ko[40]), //i-- + .ko(pp3_00_ko[39]), //o-- + .sum(pp3_01[40]), //o-- + .car(pp3_00[39]) //o-- + ); + + tri_csa42 pp3_00_csa_39( + .vd(vdd), + .gd(gnd), + .a(pp2_03[39]), //i-- + .b(pp2_02[39]), //i-- + .c(pp2_01[39]), //i-- + .d(pp2_00[39]), //i-- + .ki(pp3_00_ko[39]), //i-- + .ko(pp3_00_ko[38]), //o-- + .sum(pp3_01[39]), //o-- + .car(pp3_00[38]) //o-- + ); + + tri_csa42 pp3_00_csa_38( + .vd(vdd), + .gd(gnd), + .a(pp2_03[38]), //i-- + .b(pp2_02[38]), //i-- + .c(pp2_01[38]), //i-- + .d(pp2_00[38]), //i-- + .ki(pp3_00_ko[38]), //i-- + .ko(pp3_00_ko[37]), //o-- + .sum(pp3_01[38]), //o-- + .car(pp3_00[37]) //o-- + ); + + tri_csa42 pp3_00_csa_37( + .vd(vdd), + .gd(gnd), + .a(pp2_03[37]), //i-- + .b(pp2_02[37]), //i-- + .c(pp2_01[37]), //i-- + .d(pp2_00[37]), //i-- + .ki(pp3_00_ko[37]), //i-- + .ko(pp3_00_ko[36]), //o-- + .sum(pp3_01[37]), //o-- + .car(pp3_00[36]) //o-- + ); + + tri_csa42 pp3_00_csa_36( + .vd(vdd), + .gd(gnd), + .a(pp2_03[36]), //i-- + .b(pp2_02[36]), //i-- + .c(pp2_01[36]), //i-- + .d(pp2_00[36]), //i-- + .ki(pp3_00_ko[36]), //i-- + .ko(pp3_00_ko[35]), //o-- + .sum(pp3_01[36]), //o-- + .car(pp3_00[35]) //o-- + ); + + tri_csa42 pp3_00_csa_35( + .vd(vdd), + .gd(gnd), + .a(pp2_03[35]), //i-- + .b(pp2_02[35]), //i-- + .c(pp2_01[35]), //i-- + .d(pp2_00[35]), //i-- + .ki(pp3_00_ko[35]), //i-- + .ko(pp3_00_ko[34]), //o-- + .sum(pp3_01[35]), //o-- + .car(pp3_00[34]) //o-- + ); + + tri_csa42 pp3_00_csa_34( + .vd(vdd), + .gd(gnd), + .a(pp2_03[34]), //i-- + .b(pp2_02[34]), //i-- + .c(pp2_01[34]), //i-- + .d(pp2_00[34]), //i-- + .ki(pp3_00_ko[34]), //i-- + .ko(pp3_00_ko[33]), //o-- + .sum(pp3_01[34]), //o-- + .car(pp3_00[33]) //o-- + ); + + tri_csa42 pp3_00_csa_33( + .vd(vdd), + .gd(gnd), + .a(pp2_03[33]), //i-- + .b(pp2_02[33]), //i-- + .c(pp2_01[33]), //i-- + .d(pp2_00[33]), //i-- + .ki(pp3_00_ko[33]), //i-- + .ko(pp3_00_ko[32]), //o-- + .sum(pp3_01[33]), //o-- + .car(pp3_00[32]) //o-- + ); + + tri_csa42 pp3_00_csa_32( + .vd(vdd), + .gd(gnd), + .a(pp2_03[32]), //i-- + .b(pp2_02[32]), //i-- + .c(pp2_01[32]), //i-- + .d(pp2_00[32]), //i-- + .ki(pp3_00_ko[32]), //i-- + .ko(pp3_00_ko[31]), //o-- + .sum(pp3_01[32]), //o-- + .car(pp3_00[31]) //o-- + ); + + tri_csa42 pp3_00_csa_31( + .vd(vdd), + .gd(gnd), + .a(pp2_03[31]), //i-- + .b(pp2_02[31]), //i-- + .c(pp2_01[31]), //i-- + .d(pp2_00[31]), //i-- + .ki(pp3_00_ko[31]), //i-- + .ko(pp3_00_ko[30]), //o-- + .sum(pp3_01[31]), //o-- + .car(pp3_00[30]) //o-- + ); + + tri_csa42 pp3_00_csa_30( + .vd(vdd), + .gd(gnd), + .a(pp2_03[30]), //i-- + .b(pp2_02[30]), //i-- + .c(pp2_01[30]), //i-- + .d(pp2_00[30]), //i-- + .ki(pp3_00_ko[30]), //i-- + .ko(pp3_00_ko[29]), //o-- + .sum(pp3_01[30]), //o-- + .car(pp3_00[29]) //o-- + ); + + tri_csa42 pp3_00_csa_29( + .vd(vdd), + .gd(gnd), + .a(pp2_03[29]), //i-- + .b(pp2_02[29]), //i-- + .c(pp2_01[29]), //i-- + .d(pp2_00[29]), //i-- + .ki(pp3_00_ko[29]), //i-- + .ko(pp3_00_ko[28]), //o-- + .sum(pp3_01[29]), //o-- + .car(pp3_00[28]) //o-- + ); + + tri_csa42 pp3_00_csa_28( + .vd(vdd), + .gd(gnd), + .a(pp2_03[28]), //i-- + .b(pp2_02[28]), //i-- + .c(pp2_01[28]), //i-- + .d(pp2_00[28]), //i-- + .ki(pp3_00_ko[28]), //i-- + .ko(pp3_00_ko[27]), //o-- + .sum(pp3_01[28]), //o-- + .car(pp3_00[27]) //o-- + ); + + tri_csa42 pp3_00_csa_27( + .vd(vdd), + .gd(gnd), + .a(pp2_03[27]), //i-- + .b(pp2_02[27]), //i-- + .c(pp2_01[27]), //i-- + .d(pp2_00[27]), //i-- + .ki(pp3_00_ko[27]), //i-- + .ko(pp3_00_ko[26]), //o-- + .sum(pp3_01[27]), //o-- + .car(pp3_00[26]) //o-- + ); + + tri_csa42 pp3_00_csa_26( + .vd(vdd), + .gd(gnd), + .a(pp2_03[26]), //i-- + .b(pp2_02[26]), //i-- + .c(pp2_01[26]), //i-- + .d(pp2_00[26]), //i-- + .ki(pp3_00_ko[26]), //i-- + .ko(pp3_00_ko[25]), //o-- + .sum(pp3_01[26]), //o-- + .car(pp3_00[25]) //o-- + ); + + tri_csa42 pp3_00_csa_25( + .vd(vdd), + .gd(gnd), + .a(pp2_03[25]), //i-- + .b(pp2_02[25]), //i-- + .c(pp2_01[25]), //i-- + .d(pp2_00[25]), //i-- + .ki(pp3_00_ko[25]), //i-- + .ko(pp3_00_ko[24]), //o-- + .sum(pp3_01[25]), //o-- + .car(pp3_00[24]) //o-- + ); + + tri_csa42 pp3_00_csa_24( + .vd(vdd), + .gd(gnd), + .a(pp2_03[24]), //i-- + .b(pp2_02[24]), //i-- + .c(pp2_01[24]), //i-- + .d(pp2_00[24]), //i-- + .ki(pp3_00_ko[24]), //i-- + .ko(pp3_00_ko[23]), //o-- + .sum(pp3_01[24]), //o-- + .car(pp3_00[23]) //o-- + ); + + tri_csa42 pp3_00_csa_23( + .vd(vdd), + .gd(gnd), + .a(pp2_03[23]), //i-- + .b(pp2_02[23]), //i-- + .c(pp2_01[23]), //i-- + .d(pp2_00[23]), //i-- + .ki(pp3_00_ko[23]), //i-- + .ko(pp3_00_ko[22]), //o-- + .sum(pp3_01[23]), //o-- + .car(pp3_00[22]) //o-- + ); + + tri_csa42 pp3_00_csa_22( + .vd(vdd), + .gd(gnd), + .a(pp2_03[22]), //i-- + .b(pp2_02[22]), //i-- + .c(pp2_01[22]), //i-- + .d(pp2_00[22]), //i-- + .ki(pp3_00_ko[22]), //i-- + .ko(pp3_00_ko[21]), //o-- + .sum(pp3_01[22]), //o-- + .car(pp3_00[21]) //o-- + ); + + tri_csa42 pp3_00_csa_21( + .vd(vdd), + .gd(gnd), + .a(pp2_03[21]), //i-- + .b(pp2_02[21]), //i-- + .c(pp2_01[21]), //i-- + .d(pp2_00[21]), //i-- + .ki(pp3_00_ko[21]), //i-- + .ko(pp3_00_ko[20]), //o-- + .sum(pp3_01[21]), //o-- + .car(pp3_00[20]) //o-- + ); + + tri_csa42 pp3_00_csa_20( + .vd(vdd), + .gd(gnd), + .a(pp2_03[20]), //i-- + .b(pp2_02[20]), //i-- + .c(pp2_01[20]), //i-- + .d(pp2_00[20]), //i-- + .ki(pp3_00_ko[20]), //i-- + .ko(pp3_00_ko[19]), //o-- + .sum(pp3_01[20]), //o-- + .car(pp3_00[19]) //o-- + ); + + tri_csa42 pp3_00_csa_19( + .vd(vdd), + .gd(gnd), + .a(pp2_03[19]), //i-- + .b(pp2_02[19]), //i-- + .c(pp2_01[19]), //i-- + .d(pp2_00[19]), //i-- + .ki(pp3_00_ko[19]), //i-- + .ko(pp3_00_ko[18]), //o-- + .sum(pp3_01[19]), //o-- + .car(pp3_00[18]) //o-- + ); + + tri_csa42 pp3_00_csa_18( + .vd(vdd), + .gd(gnd), + .a(pp2_03[18]), //i-- + .b(pp2_02[18]), //i-- + .c(pp2_01[18]), //i-- + .d(pp2_00[18]), //i-- + .ki(pp3_00_ko[18]), //i-- + .ko(pp3_00_ko[17]), //o-- + .sum(pp3_01[18]), //o-- + .car(pp3_00[17]) //o-- + ); + + tri_csa42 pp3_00_csa_17( + .vd(vdd), + .gd(gnd), + .a(pp2_03[17]), //i-- + .b(pp2_02[17]), //i-- + .c(pp2_01[17]), //i-- + .d(pp2_00[17]), //i-- + .ki(pp3_00_ko[17]), //i-- + .ko(pp3_00_ko[16]), //o-- + .sum(pp3_01[17]), //o-- + .car(pp3_00[16]) //o-- + ); + + tri_csa42 pp3_00_csa_16( + .vd(vdd), + .gd(gnd), + .a(pp2_03[16]), //i-- + .b(pp2_02[16]), //i-- + .c(pp2_01[16]), //i-- + .d(pp2_00[16]), //i-- + .ki(pp3_00_ko[16]), //i-- + .ko(pp3_00_ko[15]), //o-- + .sum(pp3_01[16]), //o-- + .car(pp3_00[15]) //o-- + ); + + tri_csa42 pp3_00_csa_15( + .vd(vdd), + .gd(gnd), + .a(pp2_03[15]), //i-- + .b(pp2_02[15]), //i-- + .c(pp2_01[15]), //i-- + .d(pp2_00[15]), //i-- + .ki(pp3_00_ko[15]), //i-- + .ko(pp3_00_ko[14]), //o-- + .sum(pp3_01[15]), //o-- + .car(pp3_00[14]) //o-- + ); + + tri_csa42 pp3_00_csa_14( + .vd(vdd), + .gd(gnd), + .a(pp2_03[14]), //i-- + .b(pp2_02[14]), //i-- + .c(pp2_01[14]), //i-- + .d(pp2_00[14]), //i-- + .ki(pp3_00_ko[14]), //i-- + .ko(pp3_00_ko[13]), //o-- + .sum(pp3_01[14]), //o-- + .car(pp3_00[13]) //o-- + ); + + tri_csa42 pp3_00_csa_13( + .vd(vdd), + .gd(gnd), + .a(pp2_03[13]), //i-- + .b(pp2_02[13]), //i-- + .c(pp2_01[13]), //i-- + .d(pp2_00[13]), //i-- + .ki(pp3_00_ko[13]), //i-- + .ko(pp3_00_ko[12]), //o-- + .sum(pp3_01[13]), //o-- + .car(pp3_00[12]) //o-- + ); + + tri_csa42 pp3_00_csa_12( + .vd(vdd), + .gd(gnd), + .a(pp2_03[12]), //i-- + .b(pp2_01[12]), //i-- + .c(pp2_00[12]), //i-- + .d(tidn), //i-- + .ki(pp3_00_ko[12]), //i-- + .ko(pp3_00_ko[11]), //o-- + .sum(pp3_01[12]), //o-- + .car(pp3_00[11]) //o-- + ); + + tri_csa42 pp3_00_csa_11( + .vd(vdd), + .gd(gnd), + .a(pp2_03[11]), //i-- + .b(pp2_01[11]), //i-- + .c(pp2_00[11]), //i-- + .d(tidn), //i-- + .ki(pp3_00_ko[11]), //i-- + .ko(pp3_00_ko[10]), //o-- + .sum(pp3_01[11]), //o-- + .car(pp3_00[10]) //o-- + ); + + tri_csa42 pp3_00_csa_10( + .vd(vdd), + .gd(gnd), + .a(pp2_03[10]), //i-- + .b(pp2_01[10]), //i-- + .c(pp2_00[10]), //i-- + .d(tidn), //i-- + .ki(pp3_00_ko[10]), //i-- + .ko(pp3_00_ko[9]), //o-- + .sum(pp3_01[10]), //o-- + .car(pp3_00[9]) //o-- + ); + + tri_csa42 pp3_00_csa_09( + .vd(vdd), + .gd(gnd), + .a(pp2_03[9]), //i-- + .b(pp2_01[9]), //i-- + .c(pp2_00[9]), //i-- + .d(tidn), //i-- + .ki(pp3_00_ko[9]), //i-- + .ko(pp3_00_ko[8]), //o-- + .sum(pp3_01[9]), //o-- + .car(pp3_00[8]) //o-- + ); + + tri_csa42 pp3_00_csa_08( + .vd(vdd), + .gd(gnd), + .a(tiup), //i-- + .b(pp2_01[8]), //i-- + .c(pp2_00[8]), //i-- + .d(tidn), //i-- + .ki(pp3_00_ko[8]), //i-- + .ko(pp3_00_ko[7]), //o-- + .sum(pp3_01[8]), //o-- + .car(pp3_00[7]) //o-- + ); + + tri_csa32 pp3_00_csa_07( + .vd(vdd), + .gd(gnd), + .a(pp2_01[7]), //i-- + .b(pp2_00[7]), //i-- + .c(pp3_00_ko[7]), //i-- + .sum(pp3_01[7]), //o-- + .car(pp3_00[6]) //o-- + ); + + tri_fu_csa22_h2 pp3_00_csa_06( + .a(pp2_01[6]), //i-- + .b(pp2_00[6]), //i-- + .sum(pp3_01[6]), //o-- + .car(pp3_00[5]) //o-- + ); + + tri_fu_csa22_h2 pp3_00_csa_05( + .a(pp2_01[5]), //i-- + .b(pp2_00[5]), //i-- + .sum(pp3_01[5]), //o-- + .car(pp3_00[4]) //o-- + ); + + tri_fu_csa22_h2 pp3_00_csa_04( + .a(pp2_01[4]), //i-- + .b(pp2_00[4]), //i-- + .sum(pp3_01[4]), //o-- + .car(pp3_00[3]) //o-- + ); + + tri_fu_csa22_h2 pp3_00_csa_03( + .a(pp2_01[3]), //i-- + .b(pp2_00[3]), //i-- + .sum(pp3_01[3]), //o-- + .car(pp3_00[2]) //o-- + ); + + tri_fu_csa22_h2 pp3_00_csa_02( + .a(pp2_01[2]), //i-- + .b(pp2_00[2]), //i-- + .sum(pp3_01[2]), //o-- + .car(pp3_00[1]) //o-- + ); + + ////##################################################################### + ////## LATCH ROW scan(r-l-r) + ////##################################################################### + + + tri_lcbnd mul92_lcb( + .delay_lclkr(lcb_delay_lclkr), //in -- tidn , + //d_mode => --d_mode ,--in -- tiup , + .mpw1_b(lcb_mpw1_b), //in -- tidn , + .mpw2_b(lcb_mpw2_b), //in -- tidn , + .force_t(force_t), //in -- tidn , + .nclk(nclk), //in + .vd(vdd), //inout + .gd(gnd), //inout + .act(ex2_act), //in + .sg(lcb_sg), //in + .thold_b(thold_b), //in + .d1clk(mul92_d1clk), //out + .d2clk(mul92_d2clk), //out + .lclk(mul92_lclk) //out + ); + + + tri_inv_nlats #(.WIDTH(73), .NEEDS_SRESET(0)) pp3_lat_sum( + .vd(vdd), + .gd(gnd), + .lclk(mul92_lclk), //lclk.clk + .d1clk(mul92_d1clk), + .d2clk(mul92_d2clk), + .scanin({si, + pp3_lat_sum_so[0:71]}), + .scanout(pp3_lat_sum_so[0:72]), + .d(pp3_01[2:74]), + .qb(pp3_01_q_b[2:74]) + ); + + + tri_inv_nlats #(.WIDTH(71), .NEEDS_SRESET(0)) pp3_lat_car( + .vd(vdd), + .gd(gnd), + .lclk(mul92_lclk), //lclk.clk + .d1clk(mul92_d1clk), + .d2clk(mul92_d2clk), + .scanin({ pp3_lat_car_so[1:70], + pp3_lat_sum_so[72]}), + .scanout(pp3_lat_car_so[0:70]), + .d({pp3_00[1:67], + pp3_00[69], + hot_one_din, + pp3_00[71], + pp3_00[74]}), + //------------------------------ + .qb({ pp3_00_q_b[1:67], + pp3_00_q_b[69], + hot_one_out_b, + pp3_00_q_b[71], + pp3_00_q_b[74]}) + ); + + assign pp3_00_q_b[68] = tiup; + assign pp3_00_q_b[70] = tiup; + assign pp3_00_q_b[72] = tiup; + assign pp3_00_q_b[73] = tiup; + assign hot_one_out = (~hot_one_out_b); + + assign sum92[2:74] = (~pp3_01_q_b[2:74]); + assign car92[1:74] = (~pp3_00_q_b[1:74]); + + ////################################################################ + ////# scan string + ////################################################################ + assign so = pp3_lat_car_so[0]; + +endmodule diff --git a/dev/verilog/trilib/tri_fu_mul_bthdcd.v b/dev/verilog/trilib/tri_fu_mul_bthdcd.v new file mode 100755 index 0000000..6b05652 --- /dev/null +++ b/dev/verilog/trilib/tri_fu_mul_bthdcd.v @@ -0,0 +1,104 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILE NAME : tri_fu_mul_bthdcd.vhdl +// *! DESCRIPTION : Booth Decode +// *!**************************************************************** + +`include "tri_a2o.vh" + +module tri_fu_mul_bthdcd( + i0, + i1, + i2, + s_neg, + s_x, + s_x2 +); + input i0; + input i1; + input i2; + output s_neg; + output s_x; + output s_x2; + + // ATTRIBUTE btr_name OF tri_fu_mul_bthdcd : ENTITY IS "tri_fu_mul_bthdcd"; + + wire s_add; + wire sx1_a0_b; + wire sx1_a1_b; + wire sx1_t; + wire sx1_i; + wire sx2_a0_b; + wire sx2_a1_b; + wire sx2_t; + wire sx2_i; + wire i0_b; + wire i1_b; + wire i2_b; + + // i0:2 booth recode table + //-------------------------------- + // 000 add sh1=0 sh2=0 sub_adj=0 + // 001 add sh1=1 sh2=0 sub_adj=0 + // 010 add sh1=1 sh2=0 sub_adj=0 + // 011 add sh1=0 sh2=1 sub_adj=0 + // 100 sub sh1=0 sh2=1 sub_adj=1 + // 101 sub sh1=1 sh2=0 sub_adj=1 + // 110 sub sh1=1 sh2=0 sub_adj=1 + // 111 sub sh1=0 sh2=0 sub_adj=0 + + // logically correct + //---------------------------------- + // s_neg <= (i0); + // s_x <= ( not i1 and i2) or ( i1 and not i2); + // s_x2 <= (i0 and not i1 and not i2) or (not i0 and i1 and i2); + + assign i0_b = (~(i0)); + assign i1_b = (~(i1)); + assign i2_b = (~(i2)); + + assign s_add = (~(i0)); + assign s_neg = (~(s_add)); + + assign sx1_a0_b = (~(i1_b & i2)); + assign sx1_a1_b = (~(i1 & i2_b)); + assign sx1_t = (~(sx1_a0_b & sx1_a1_b)); + assign sx1_i = (~(sx1_t)); + assign s_x = (~(sx1_i)); + + assign sx2_a0_b = (~(i0 & i1_b & i2_b)); + assign sx2_a1_b = (~(i0_b & i1 & i2)); + assign sx2_t = (~(sx2_a0_b & sx2_a1_b)); + assign sx2_i = (~(sx2_t)); + assign s_x2 = (~(sx2_i)); + +endmodule diff --git a/dev/verilog/trilib/tri_fu_mul_bthmux.v b/dev/verilog/trilib/tri_fu_mul_bthmux.v new file mode 100755 index 0000000..a3743d4 --- /dev/null +++ b/dev/verilog/trilib/tri_fu_mul_bthmux.v @@ -0,0 +1,66 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILE NAME : tri_fu_mul_bthdcd.vhdl +// *! DESCRIPTION : Booth Decode +// *!**************************************************************** + +`include "tri_a2o.vh" + +module tri_fu_mul_bthmux( + x, + sneg, + sx, + sx2, + right, + left, + q +); + input x; + input sneg; // do not flip the input (add) + input sx; // shift by 1 + input sx2; // shift by 2 + input right; // bit from the right (lsb) + output left; // bit from the left + output q; // final output + + wire center; + wire q_b; + + assign center = x ^ sneg; + + assign left = center; //output-- rename, no gate + + assign q_b = (~((sx & center) | (sx2 & right))); + + assign q = (~q_b); // output-- + +endmodule diff --git a/dev/verilog/trilib/tri_fu_mul_bthrow.v b/dev/verilog/trilib/tri_fu_mul_bthrow.v new file mode 100755 index 0000000..d4c8109 --- /dev/null +++ b/dev/verilog/trilib/tri_fu_mul_bthrow.v @@ -0,0 +1,675 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILE NAME : tri_fu_mul_bthrow.vhdl +// *! DESCRIPTION : Booth Decode +// *!**************************************************************** + +module tri_fu_mul_bthrow( + x, + s_neg, + s_x, + s_x2, + hot_one, + q +); + input [0:53] x; + input s_neg; // negate the row + input s_x; // shift by 1 + input s_x2; // shift by 2 + output hot_one; // lsb term for row below + output [0:54] q; // final output + + // ENTITY + + + parameter tiup = 1'b1; + parameter tidn = 1'b0; + + wire [0:54] left; + wire unused; + + assign unused = left[0]; // dangling pin from edge bit + + ////############################################################### + //# A row of the repeated part of the booth_mux row + ////############################################################### + + tri_fu_mul_bthmux u00( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(tidn), //i-- ******** + .right(left[1]), //i-- [n+1] + .left(left[0]), //o-- [n] + .q(q[0]) //o-- + ); + + + tri_fu_mul_bthmux u01( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[0]), //i-- [n-1] + .right(left[2]), //i-- [n+1] + .left(left[1]), //o-- [n] + .q(q[1]) //o-- + ); + + + tri_fu_mul_bthmux u02( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[1]), //i-- + .right(left[3]), //i-- + .left(left[2]), //o-- + .q(q[2]) //o-- + ); + + + tri_fu_mul_bthmux u03( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[2]), //i-- + .right(left[4]), //i-- + .left(left[3]), //o-- + .q(q[3]) //o-- + ); + + + tri_fu_mul_bthmux u04( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[3]), //i-- + .right(left[5]), //i-- + .left(left[4]), //o-- + .q(q[4]) //o-- + ); + + + tri_fu_mul_bthmux u05( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[4]), //i-- + .right(left[6]), //i-- + .left(left[5]), //o-- + .q(q[5]) //o-- + ); + + + tri_fu_mul_bthmux u06( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[5]), //i-- + .right(left[7]), //i-- + .left(left[6]), //o-- + .q(q[6]) //o-- + ); + + + tri_fu_mul_bthmux u07( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[6]), //i-- + .right(left[8]), //i-- + .left(left[7]), //o-- + .q(q[7]) //o-- + ); + + + tri_fu_mul_bthmux u08( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[7]), //i-- + .right(left[9]), //i-- + .left(left[8]), //o-- + .q(q[8]) //o-- + ); + + + tri_fu_mul_bthmux u09( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[8]), //i-- + .right(left[10]), //i-- + .left(left[9]), //o-- + .q(q[9]) //o-- + ); + + + tri_fu_mul_bthmux u10( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[9]), //i-- + .right(left[11]), //i-- + .left(left[10]), //o-- + .q(q[10]) //o-- + ); + + + tri_fu_mul_bthmux u11( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[10]), //i-- + .right(left[12]), //i-- + .left(left[11]), //o-- + .q(q[11]) //o-- + ); + + + tri_fu_mul_bthmux u12( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[11]), //i-- + .right(left[13]), //i-- + .left(left[12]), //o-- + .q(q[12]) //o-- + ); + + + tri_fu_mul_bthmux u13( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[12]), //i-- + .right(left[14]), //i-- + .left(left[13]), //o-- + .q(q[13]) //o-- + ); + + + tri_fu_mul_bthmux u14( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[13]), //i-- + .right(left[15]), //i-- + .left(left[14]), //o-- + .q(q[14]) //o-- + ); + + + tri_fu_mul_bthmux u15( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[14]), //i-- + .right(left[16]), //i-- + .left(left[15]), //o-- + .q(q[15]) //o-- + ); + + + tri_fu_mul_bthmux u16( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[15]), //i-- + .right(left[17]), //i-- + .left(left[16]), //o-- + .q(q[16]) //o-- + ); + + + tri_fu_mul_bthmux u17( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[16]), //i-- + .right(left[18]), //i-- + .left(left[17]), //o-- + .q(q[17]) //o-- + ); + + + tri_fu_mul_bthmux u18( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[17]), //i-- + .right(left[19]), //i-- + .left(left[18]), //o-- + .q(q[18]) //o-- + ); + + + tri_fu_mul_bthmux u19( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[18]), //i-- + .right(left[20]), //i-- + .left(left[19]), //o-- + .q(q[19]) //o-- + ); + + + tri_fu_mul_bthmux u20( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[19]), //i-- + .right(left[21]), //i-- + .left(left[20]), //o-- + .q(q[20]) //o-- + ); + + + tri_fu_mul_bthmux u21( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[20]), //i-- + .right(left[22]), //i-- + .left(left[21]), //o-- + .q(q[21]) //o-- + ); + + + tri_fu_mul_bthmux u22( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[21]), //i-- + .right(left[23]), //i-- + .left(left[22]), //o-- + .q(q[22]) //o-- + ); + + + tri_fu_mul_bthmux u23( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[22]), //i-- + .right(left[24]), //i-- + .left(left[23]), //o-- + .q(q[23]) //o-- + ); + + + tri_fu_mul_bthmux u24( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[23]), //i-- + .right(left[25]), //i-- + .left(left[24]), //o-- + .q(q[24]) //o-- + ); + + + tri_fu_mul_bthmux u25( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[24]), //i-- + .right(left[26]), //i-- + .left(left[25]), //o-- + .q(q[25]) //o-- + ); + + + tri_fu_mul_bthmux u26( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[25]), //i-- + .right(left[27]), //i-- + .left(left[26]), //o-- + .q(q[26]) //o-- + ); + + + tri_fu_mul_bthmux u27( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[26]), //i-- + .right(left[28]), //i-- + .left(left[27]), //o-- + .q(q[27]) //o-- + ); + + + tri_fu_mul_bthmux u28( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[27]), //i-- + .right(left[29]), //i-- + .left(left[28]), //o-- + .q(q[28]) //o-- + ); + + + tri_fu_mul_bthmux u29( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[28]), //i-- + .right(left[30]), //i-- + .left(left[29]), //o-- + .q(q[29]) //o-- + ); + + + tri_fu_mul_bthmux u30( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[29]), //i-- + .right(left[31]), //i-- + .left(left[30]), //o-- + .q(q[30]) //o-- + ); + + + tri_fu_mul_bthmux u31( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[30]), //i-- + .right(left[32]), //i-- + .left(left[31]), //o-- + .q(q[31]) //o-- + ); + + + tri_fu_mul_bthmux u32( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[31]), //i-- + .right(left[33]), //i-- + .left(left[32]), //o-- + .q(q[32]) //o-- + ); + + + tri_fu_mul_bthmux u33( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[32]), //i-- + .right(left[34]), //i-- + .left(left[33]), //o-- + .q(q[33]) //o-- + ); + + + tri_fu_mul_bthmux u34( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[33]), //i-- + .right(left[35]), //i-- + .left(left[34]), //o-- + .q(q[34]) //o-- + ); + + + tri_fu_mul_bthmux u35( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[34]), //i-- + .right(left[36]), //i-- + .left(left[35]), //o-- + .q(q[35]) //o-- + ); + + + tri_fu_mul_bthmux u36( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[35]), //i-- + .right(left[37]), //i-- + .left(left[36]), //o-- + .q(q[36]) //o-- + ); + + + tri_fu_mul_bthmux u37( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[36]), //i-- + .right(left[38]), //i-- + .left(left[37]), //o-- + .q(q[37]) //o-- + ); + + + tri_fu_mul_bthmux u38( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[37]), //i-- + .right(left[39]), //i-- + .left(left[38]), //o-- + .q(q[38]) //o-- + ); + + + tri_fu_mul_bthmux u39( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[38]), //i-- + .right(left[40]), //i-- + .left(left[39]), //o-- + .q(q[39]) //o-- + ); + + + tri_fu_mul_bthmux u40( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[39]), //i-- + .right(left[41]), //i-- + .left(left[40]), //o-- + .q(q[40]) //o-- + ); + + + tri_fu_mul_bthmux u41( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[40]), //i-- + .right(left[42]), //i-- + .left(left[41]), //o-- + .q(q[41]) //o-- + ); + + + tri_fu_mul_bthmux u42( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[41]), //i-- + .right(left[43]), //i-- + .left(left[42]), //o-- + .q(q[42]) //o-- + ); + + + tri_fu_mul_bthmux u43( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[42]), //i-- + .right(left[44]), //i-- + .left(left[43]), //o-- + .q(q[43]) //o-- + ); + + + tri_fu_mul_bthmux u44( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[43]), //i-- + .right(left[45]), //i-- + .left(left[44]), //o-- + .q(q[44]) //o-- + ); + + + tri_fu_mul_bthmux u45( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[44]), //i-- + .right(left[46]), //i-- + .left(left[45]), //o-- + .q(q[45]) //o-- + ); + + + tri_fu_mul_bthmux u46( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[45]), //i-- + .right(left[47]), //i-- + .left(left[46]), //o-- + .q(q[46]) //o-- + ); + + + tri_fu_mul_bthmux u47( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[46]), //i-- + .right(left[48]), //i-- + .left(left[47]), //o-- + .q(q[47]) //o-- + ); + + + tri_fu_mul_bthmux u48( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[47]), //i-- + .right(left[49]), //i-- + .left(left[48]), //o-- + .q(q[48]) //o-- + ); + + + tri_fu_mul_bthmux u49( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[48]), //i-- + .right(left[50]), //i-- + .left(left[49]), //o-- + .q(q[49]) //o-- + ); + + + tri_fu_mul_bthmux u50( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[49]), //i-- + .right(left[51]), //i-- + .left(left[50]), //o-- + .q(q[50]) //o-- + ); + + + tri_fu_mul_bthmux u51( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[50]), //i-- + .right(left[52]), //i-- + .left(left[51]), //o-- + .q(q[51]) //o-- + ); + + + tri_fu_mul_bthmux u52( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[51]), //i-- + .right(left[53]), //i-- + .left(left[52]), //o-- + .q(q[52]) //o-- + ); + + + tri_fu_mul_bthmux u53( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[52]), //i-- + .right(left[54]), //i-- + .left(left[53]), //o-- + .q(q[53]) //o-- + ); + + + tri_fu_mul_bthmux u54( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[53]), //i-- + .right(s_neg), //i-- + .left(left[54]), //o-- + .q(q[54]) //o-- + ); + + // For negate -A = !A + 1 ... this term is the plus 1. + // this has same bit weight as LSB, so it jumps down a row to free spot in compressor tree. + + assign hot_one = (s_neg & (s_x | s_x2)); + +endmodule diff --git a/dev/verilog/trilib/tri_fu_tblmul.v b/dev/verilog/trilib/tri_fu_tblmul.v new file mode 100755 index 0000000..b778f4c --- /dev/null +++ b/dev/verilog/trilib/tri_fu_tblmul.v @@ -0,0 +1,1847 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" + +module tri_fu_tblmul( + vdd, + gnd, + x, + y, + z, + tbl_sum, + tbl_car +); + inout vdd; + inout gnd; + input [1:15] x; // rng from lookup (recode) + input [7:22] y; // b operand bits (shift) + input [0:20] z; // estimate from table + + // multiplier output msb comes out at [6] + + output [0:36] tbl_sum; + output [0:35] tbl_car; + + // ENTITY + + + parameter tiup = 1'b1; + parameter tidn = 1'b0; + + wire [1:7] sub_adj_lsb; + wire [1:7] sub_adj_lsb_b; + wire [1:7] sub_adj_msb_b; + wire sub_adj_msb_7x_b; + wire sub_adj_msb_7x; + wire sub_adj_msb_7y; + wire [0:7] s_x; + wire [0:7] s_x2; + + wire [0:7] s_neg; + + wire [6:24] pp0_0; + wire [6:26] pp0_1; + wire [8:28] pp0_2; + wire [10:30] pp0_3; + wire [12:32] pp0_4; + wire [14:34] pp0_5; + wire [16:36] pp0_6; + wire [17:36] pp0_7; + + wire [0:26] pp1_0_sum; + wire [0:24] pp1_0_car; + wire [8:32] pp1_1_sum; + wire [9:30] pp1_1_car; + wire [14:36] pp1_2_sum; + wire [15:36] pp1_2_car; + wire pp1_0_car_unused; + + wire [0:32] pp2_0_sum; + wire [0:26] pp2_0_car; + wire [9:36] pp2_1_sum; + wire [13:36] pp2_1_car; + wire pp2_0_car_unused; + + wire [0:36] pp3_0_sum; + wire [8:25] pp3_0_ko; + wire [0:35] pp3_0_car; + wire pp3_0_car_unused; + wire [0:20] z_b; + (* analysis_not_referenced="TRUE" *) + wire unused; + + assign unused = pp1_0_car_unused | pp2_0_car_unused | pp3_0_car_unused | pp0_0[23] | pp0_1[25] | pp0_2[27] | pp0_3[29] | pp0_4[31] | pp0_5[33] | pp0_6[35] | pp1_0_car[23] | pp1_0_sum[25] | pp1_1_car[28] | pp1_1_sum[31] | pp1_2_car[34] | pp2_0_car[24] | pp2_0_sum[31] | pp2_1_car[30] | pp2_1_car[34] | s_neg[0] | pp1_1_car[29] | pp1_2_car[35] | pp2_0_car[25] | pp2_1_car[35]; + + //=################################################# + //= Booth Decoders + //=################################################# + // 0 1 2 3 4 5 6 7 + // (x,1) (2,3) (4,5) (6,7) (8,9) (10,11) (12,13) (14,15) + + + tri_fu_tblmul_bthdcd bd0( + .i0(tidn), //i-- + .i1(x[1]), //i-- + .i2(x[2]), //i-- + .s_neg(s_neg[0]), //o-- + .s_x(s_x[0]), //o-- + .s_x2(s_x2[0]) //o-- + ); + + + tri_fu_tblmul_bthdcd bd1( + .i0(x[2]), //i-- + .i1(x[3]), //i-- + .i2(x[4]), //i-- + .s_neg(s_neg[1]), //o-- + .s_x(s_x[1]), //o-- + .s_x2(s_x2[1]) //o-- + ); + + + tri_fu_tblmul_bthdcd bd2( + .i0(x[4]), //i-- + .i1(x[5]), //i-- + .i2(x[6]), //i-- + .s_neg(s_neg[2]), //o-- + .s_x(s_x[2]), //o-- + .s_x2(s_x2[2]) //o-- + ); + + + tri_fu_tblmul_bthdcd bd3( + .i0(x[6]), //i-- + .i1(x[7]), //i-- + .i2(x[8]), //i-- + .s_neg(s_neg[3]), //o-- + .s_x(s_x[3]), //o-- + .s_x2(s_x2[3]) //o-- + ); + + + tri_fu_tblmul_bthdcd bd4( + .i0(x[8]), //i-- + .i1(x[9]), //i-- + .i2(x[10]), //i-- + .s_neg(s_neg[4]), //o-- + .s_x(s_x[4]), //o-- + .s_x2(s_x2[4]) //o-- + ); + + + tri_fu_tblmul_bthdcd bd5( + .i0(x[10]), //i-- + .i1(x[11]), //i-- + .i2(x[12]), //i-- + .s_neg(s_neg[5]), //o-- + .s_x(s_x[5]), //o-- + .s_x2(s_x2[5]) //o-- + ); + + + tri_fu_tblmul_bthdcd bd6( + .i0(x[12]), //i-- + .i1(x[13]), //i-- + .i2(x[14]), //i-- + .s_neg(s_neg[6]), //o-- + .s_x(s_x[6]), //o-- + .s_x2(s_x2[6]) //o-- + ); + + + tri_fu_tblmul_bthdcd bd7( + .i0(x[14]), //i-- + .i1(x[15]), //i-- + .i2(tidn), //i-- + .s_neg(s_neg[7]), //o-- + .s_x(s_x[7]), //o-- + .s_x2(s_x2[7]) //o-- + ); + + //=############################################################### + //= booth muxes + //=############################################################### + + //= NUMBERING SYSTEM RELATIVE TO COMPRESSOR TREE + //= + //= 00000000000000000000000000000000000000 + //= 00000000001111111111222222222233333333 + //= 01234567890123456789012345678901234567 + //= 0 .......DddddddddddddddddD0s................ + //= 1 .......1aDddddddddddddddddD0s.............. + //= 2 .........1aDddddddddddddddddD0s............ + //= 3 ...........1aDddddddddddddddddD0s.......... + //= 4 .............1aDddddddddddddddddD0s........ + //= 5 ...............1aDddddddddddddddddD0s...... + //= 6 .................1aDddddddddddddddddD0s.... + //= 7 ..................assDddddddddddddddddD.... + //= EST dddddddddddddddddddd (the ass from sgnXtd.7 is already added into the est. + //= + //=############################ + //= want (est - mult ) + //= will calc -(r - e) = -(r + !e + 1) + //= = -(r + !e) -1 + //= = !(r + !e) + 1 - 1 + //= = !(r + !e) + //= = !(R + ASS + !e) ... seperate out the overlapping SGNxtd piece + //= = !(R + (ASS + !e)) .... invert the final adder output + //= + //= table estimate will be : ADD !e + 100 + //= SUB !e + 011 + //= + //= more "0" in table if read out POS version of est, then invert + //= + //= !e + adj = -e -1 + adj + //= = -(e +1 -adj) + //= = -(e -adj) -1 + //= = !(e -adj) +1 -1 + //= = !(e -adj) ... invert the table input + + assign sub_adj_lsb_b[1] = (~(s_neg[1] & (s_x[1] | s_x2[1]))); + assign sub_adj_lsb_b[2] = (~(s_neg[2] & (s_x[2] | s_x2[2]))); + assign sub_adj_lsb_b[3] = (~(s_neg[3] & (s_x[3] | s_x2[3]))); + assign sub_adj_lsb_b[4] = (~(s_neg[4] & (s_x[4] | s_x2[4]))); + assign sub_adj_lsb_b[5] = (~(s_neg[5] & (s_x[5] | s_x2[5]))); + assign sub_adj_lsb_b[6] = (~(s_neg[6] & (s_x[6] | s_x2[6]))); + assign sub_adj_lsb_b[7] = (~(s_neg[7] & (s_x[7] | s_x2[7]))); + + assign sub_adj_lsb[1] = (~sub_adj_lsb_b[1]); + assign sub_adj_lsb[2] = (~sub_adj_lsb_b[2]); + assign sub_adj_lsb[3] = (~sub_adj_lsb_b[3]); + assign sub_adj_lsb[4] = (~sub_adj_lsb_b[4]); + assign sub_adj_lsb[5] = (~sub_adj_lsb_b[5]); + assign sub_adj_lsb[6] = (~sub_adj_lsb_b[6]); + assign sub_adj_lsb[7] = (~sub_adj_lsb_b[7]); + + assign sub_adj_msb_b[1] = (~(s_neg[1] & (s_x[1] | s_x2[1]))); + assign sub_adj_msb_b[2] = (~(s_neg[2] & (s_x[2] | s_x2[2]))); + assign sub_adj_msb_b[3] = (~(s_neg[3] & (s_x[3] | s_x2[3]))); + assign sub_adj_msb_b[4] = (~(s_neg[4] & (s_x[4] | s_x2[4]))); + assign sub_adj_msb_b[5] = (~(s_neg[5] & (s_x[5] | s_x2[5]))); + assign sub_adj_msb_b[6] = (~(s_neg[6] & (s_x[6] | s_x2[6]))); + assign sub_adj_msb_b[7] = (~(s_neg[7] & (s_x[7] | s_x2[7]))); + assign sub_adj_msb_7x_b = (~(s_neg[7] & (s_x[7] | s_x2[7]))); + + assign sub_adj_msb_7x = (~sub_adj_msb_7x_b); + assign sub_adj_msb_7y = (~sub_adj_msb_7x_b); + + + tri_fu_tblmul_bthrow bm0( + .s_neg(tidn), //i-- (tidn) msb term is never sub + .s_x(s_x[0]), //i-- + .s_x2(s_x2[0]), //i-- + .x(y[7:22]), //i-- + .q(pp0_0[6:22]) //o-- + ); + assign pp0_0[23] = tidn; + assign pp0_0[24] = sub_adj_lsb[1]; + + assign pp0_1[6] = tiup; + assign pp0_1[7] = sub_adj_msb_b[1]; + + tri_fu_tblmul_bthrow bm1( + .s_neg(s_neg[1]), //i-- + .s_x(s_x[1]), //i-- + .s_x2(s_x2[1]), //i-- + .x(y[7:22]), //i-- + .q(pp0_1[8:24]) //o-- + ); + assign pp0_1[25] = tidn; + assign pp0_1[26] = sub_adj_lsb[2]; + + assign pp0_2[8] = tiup; + assign pp0_2[9] = sub_adj_msb_b[2]; + + tri_fu_tblmul_bthrow bm2( + .s_neg(s_neg[2]), //i-- + .s_x(s_x[2]), //i-- + .s_x2(s_x2[2]), //i-- + .x(y[7:22]), //i-- + .q(pp0_2[10:26]) //o-- + ); + assign pp0_2[27] = tidn; + assign pp0_2[28] = sub_adj_lsb[3]; + + assign pp0_3[10] = tiup; + assign pp0_3[11] = sub_adj_msb_b[3]; + + tri_fu_tblmul_bthrow bm3( + .s_neg(s_neg[3]), //i-- + .s_x(s_x[3]), //i-- + .s_x2(s_x2[3]), //i-- + .x(y[7:22]), //i-- + .q(pp0_3[12:28]) //o-- + ); + assign pp0_3[29] = tidn; + assign pp0_3[30] = sub_adj_lsb[4]; + + assign pp0_4[12] = tiup; + assign pp0_4[13] = sub_adj_msb_b[4]; + + tri_fu_tblmul_bthrow bm4( + .s_neg(s_neg[4]), //i-- + .s_x(s_x[4]), //i-- + .s_x2(s_x2[4]), //i-- + .x(y[7:22]), //i-- + .q(pp0_4[14:30]) //o-- + ); + assign pp0_4[31] = tidn; + assign pp0_4[32] = sub_adj_lsb[5]; + + assign pp0_5[14] = tiup; + assign pp0_5[15] = sub_adj_msb_b[5]; + + tri_fu_tblmul_bthrow bm5( + .s_neg(s_neg[5]), //i-- + .s_x(s_x[5]), //i-- + .s_x2(s_x2[5]), //i-- + .x(y[7:22]), //i-- + .q(pp0_5[16:32]) //o-- + ); + assign pp0_5[33] = tidn; + assign pp0_5[34] = sub_adj_lsb[6]; + + assign pp0_6[16] = tiup; + assign pp0_6[17] = sub_adj_msb_b[6]; + + tri_fu_tblmul_bthrow bm6( + .s_neg(s_neg[6]), //i-- + .s_x(s_x[6]), //i-- + .s_x2(s_x2[6]), //i-- + .x(y[7:22]), //i-- + .q(pp0_6[18:34]) //o-- + ); + assign pp0_6[35] = tidn; + assign pp0_6[36] = sub_adj_lsb[7]; + + assign pp0_7[17] = sub_adj_msb_b[7]; + assign pp0_7[18] = sub_adj_msb_7x; + assign pp0_7[19] = sub_adj_msb_7y; + + tri_fu_tblmul_bthrow bm7( + .s_neg(s_neg[7]), //i-- + .s_x(s_x[7]), //i-- + .s_x2(s_x2[7]), //i-- + .x(y[7:22]), //i-- + .q(pp0_7[20:36]) //o-- + ); + + //=#################################################################### + //=# compressor tree level 1 + //=#################################################################### + //= 0 1 2 3 + //= 0123456789012345678901234567890123456 + //==------------------------------------- + // ddddddddddddddddddddd________________ + // 111111ddddddddddddddddd_S____________ bm0 + // ______1addddddddddddddddd_S__________ bm1 + // ________1addddddddddddddddd_S________ bm2 + // __________1addddddddddddddddd_S______ bm3 + // ____________1addddddddddddddddd_S____ bm4 + // ______________1addddddddddddddddd_S__ bm5 + // ________________1addddddddddddddddd_S bm6 + // _________________assddddddddddddddddd bm7 + + //= 0 1 2 3 + //= 0123456789012345678901234567890123456 + //==------------------------------------- + // ddddddddddddddddddddd________________ + // 111111ddddddddddddddddd_S____________ bm0 + // ______1addddddddddddddddd_S__________ bm1 + // 111111333333333333333221201 + // sssssssssssssssssssssssss_s pp1_0_sum + // ccccccccccccccccccccccc_c__ pp1_0_car + + //= 0 1 2 3 + //= 0123456789012345678901234567890123456 + //==------------------------------------- + // ________1addddddddddddddddd_S________ bm2 + // __________1addddddddddddddddd_S______ bm3 + // ____________1addddddddddddddddd_S____ bm4 + // 1122333333333333333231201 + // ________sssssssssssssssssssssss_s pp1_1_sum + // _ccccccccccccccccccc__c__ pp1_1_car + + //= 0 1 2 3 + //= 0123456789012345678901234567890123456 + //==------------------------------------- + // ______________1addddddddddddddddd_S__ bm5 + // ________________1addddddddddddddddd_S bm6 + // _________________assddddddddddddddddd bm7 + // 11233333333333333332312 + // sssssssssssssssssssssss pp1_2_sum + // _ccccccccccccccccccc__c pp1_2_car + + assign z_b[0:20] = (~z[0:20]); + + //====================================================== + //== compressor level 1 , row 0 + //====================================================== + + assign pp1_0_sum[26] = pp0_1[26]; + assign pp1_0_sum[25] = tidn; + assign pp1_0_sum[24] = pp0_0[24]; + assign pp1_0_car[24] = pp0_1[24]; + assign pp1_0_sum[23] = pp0_1[23]; + assign pp1_0_car[23] = tidn; + assign pp1_0_sum[22] = pp0_0[22]; + assign pp1_0_car[22] = pp0_1[22]; + assign pp1_0_sum[21] = pp0_0[21]; + assign pp1_0_car[21] = pp0_1[21]; + assign pp1_0_car[20] = tidn; + // MLT32_X1_A12TH + tri_csa32 pp1_0_csa_20( + .vd(vdd), + .gd(gnd), + .a(z_b[20]), //i-- + .b(pp0_0[20]), //i-- + .c(pp0_1[20]), //i-- + .sum(pp1_0_sum[20]), //o-- + .car(pp1_0_car[19]) //o-- + ); + + tri_csa32 pp1_0_csa_19( + .vd(vdd), + .gd(gnd), + .a(z_b[19]), //i-- + .b(pp0_0[19]), //i-- + .c(pp0_1[19]), //i-- + .sum(pp1_0_sum[19]), //o-- + .car(pp1_0_car[18]) //o-- + ); + + tri_csa32 pp1_0_csa_18( + .vd(vdd), + .gd(gnd), + .a(z_b[18]), //i-- + .b(pp0_0[18]), //i-- + .c(pp0_1[18]), //i-- + .sum(pp1_0_sum[18]), //o-- + .car(pp1_0_car[17]) //o-- + ); + + tri_csa32 pp1_0_csa_17( + .vd(vdd), + .gd(gnd), + .a(z_b[17]), //i-- + .b(pp0_0[17]), //i-- + .c(pp0_1[17]), //i-- + .sum(pp1_0_sum[17]), //o-- + .car(pp1_0_car[16]) //o-- + ); + + tri_csa32 pp1_0_csa_16( + .vd(vdd), + .gd(gnd), + .a(z_b[16]), //i-- + .b(pp0_0[16]), //i-- + .c(pp0_1[16]), //i-- + .sum(pp1_0_sum[16]), //o-- + .car(pp1_0_car[15]) //o-- + ); + + tri_csa32 pp1_0_csa_15( + .vd(vdd), + .gd(gnd), + .a(z_b[15]), //i-- + .b(pp0_0[15]), //i-- + .c(pp0_1[15]), //i-- + .sum(pp1_0_sum[15]), //o-- + .car(pp1_0_car[14]) //o-- + ); + + tri_csa32 pp1_0_csa_14( + .vd(vdd), + .gd(gnd), + .a(z_b[14]), //i-- + .b(pp0_0[14]), //i-- + .c(pp0_1[14]), //i-- + .sum(pp1_0_sum[14]), //o-- + .car(pp1_0_car[13]) //o-- + ); + + tri_csa32 pp1_0_csa_13( + .vd(vdd), + .gd(gnd), + .a(z_b[13]), //i-- + .b(pp0_0[13]), //i-- + .c(pp0_1[13]), //i-- + .sum(pp1_0_sum[13]), //o-- + .car(pp1_0_car[12]) //o-- + ); + + tri_csa32 pp1_0_csa_12( + .vd(vdd), + .gd(gnd), + .a(z_b[12]), //i-- + .b(pp0_0[12]), //i-- + .c(pp0_1[12]), //i-- + .sum(pp1_0_sum[12]), //o-- + .car(pp1_0_car[11]) //o-- + ); + + tri_csa32 pp1_0_csa_11( + .vd(vdd), + .gd(gnd), + .a(z_b[11]), //i-- + .b(pp0_0[11]), //i-- + .c(pp0_1[11]), //i-- + .sum(pp1_0_sum[11]), //o-- + .car(pp1_0_car[10]) //o-- + ); + + tri_csa32 pp1_0_csa_10( + .vd(vdd), + .gd(gnd), + .a(z_b[10]), //i-- + .b(pp0_0[10]), //i-- + .c(pp0_1[10]), //i-- + .sum(pp1_0_sum[10]), //o-- + .car(pp1_0_car[9]) //o-- + ); + + tri_csa32 pp1_0_csa_9( + .vd(vdd), + .gd(gnd), + .a(z_b[9]), //i-- + .b(pp0_0[9]), //i-- + .c(pp0_1[9]), //i-- + .sum(pp1_0_sum[9]), //o-- + .car(pp1_0_car[8]) //o-- + ); + + tri_csa32 pp1_0_csa_8( + .vd(vdd), + .gd(gnd), + .a(z_b[8]), //i-- + .b(pp0_0[8]), //i-- + .c(pp0_1[8]), //i-- + .sum(pp1_0_sum[8]), //o-- + .car(pp1_0_car[7]) //o-- + ); + + tri_csa32 pp1_0_csa_7( + .vd(vdd), + .gd(gnd), + .a(z_b[7]), //i-- + .b(pp0_0[7]), //i-- + .c(pp0_1[7]), //i-- + .sum(pp1_0_sum[7]), //o-- + .car(pp1_0_car[6]) //o-- + ); + + tri_csa32 pp1_0_csa_6( + .vd(vdd), + .gd(gnd), + .a(z_b[6]), //i-- + .b(pp0_0[6]), //i-- + .c(pp0_1[6]), //i-- + .sum(pp1_0_sum[6]), //o-- + .car(pp1_0_car[5]) //o-- + ); + + tri_fu_csa22_h2 pp1_0_csa_5( + .a(z_b[5]), //i-- + .b(tiup), //i-- + .sum(pp1_0_sum[5]), //o-- + .car(pp1_0_car[4]) //o-- + ); + + tri_fu_csa22_h2 pp1_0_csa_4( + .a(z_b[4]), //i-- + .b(tiup), //i-- + .sum(pp1_0_sum[4]), //o-- + .car(pp1_0_car[3]) //o-- + ); + + tri_fu_csa22_h2 pp1_0_csa_3( + .a(z_b[3]), //i-- + .b(tiup), //i-- + .sum(pp1_0_sum[3]), //o-- + .car(pp1_0_car[2]) //o-- + ); + + tri_fu_csa22_h2 pp1_0_csa_2( + .a(z_b[2]), //i-- + .b(tiup), //i-- + .sum(pp1_0_sum[2]), //o-- + .car(pp1_0_car[1]) //o-- + ); + + tri_fu_csa22_h2 pp1_0_csa_1( + .a(z_b[1]), //i-- + .b(tiup), //i-- + .sum(pp1_0_sum[1]), //o-- + .car(pp1_0_car[0]) //o-- + ); + + tri_fu_csa22_h2 pp1_0_csa_0( + .a(z_b[0]), //i-- + .b(tiup), //i-- + .sum(pp1_0_sum[0]), //o-- + .car(pp1_0_car_unused) //o-- + ); + + //====================================================== + //== compressor level 1 , row 1 + //====================================================== + + assign pp1_1_sum[32] = pp0_4[32]; + assign pp1_1_sum[31] = tidn; + assign pp1_1_sum[30] = pp0_3[30]; + assign pp1_1_car[30] = pp0_4[30]; + assign pp1_1_sum[29] = pp0_4[29]; + assign pp1_1_car[29] = tidn; + assign pp1_1_car[28] = tidn; + + tri_csa32 pp1_1_csa_28( + .vd(vdd), + .gd(gnd), + .a(pp0_2[28]), //i-- + .b(pp0_3[28]), //i-- + .c(pp0_4[28]), //i-- + .sum(pp1_1_sum[28]), //o-- + .car(pp1_1_car[27]) //o-- + ); + + tri_fu_csa22_h2 pp1_1_csa_27( + .a(pp0_3[27]), //i-- + .b(pp0_4[27]), //i-- + .sum(pp1_1_sum[27]), //o-- + .car(pp1_1_car[26]) //o-- + ); + + tri_csa32 pp1_1_csa_26( + .vd(vdd), + .gd(gnd), + .a(pp0_2[26]), //i-- + .b(pp0_3[26]), //i-- + .c(pp0_4[26]), //i-- + .sum(pp1_1_sum[26]), //o-- + .car(pp1_1_car[25]) //o-- + ); + + tri_csa32 pp1_1_csa_25( + .vd(vdd), + .gd(gnd), + .a(pp0_2[25]), //i-- + .b(pp0_3[25]), //i-- + .c(pp0_4[25]), //i-- + .sum(pp1_1_sum[25]), //o-- + .car(pp1_1_car[24]) //o-- + ); + + tri_csa32 pp1_1_csa_24( + .vd(vdd), + .gd(gnd), + .a(pp0_2[24]), //i-- + .b(pp0_3[24]), //i-- + .c(pp0_4[24]), //i-- + .sum(pp1_1_sum[24]), //o-- + .car(pp1_1_car[23]) //o-- + ); + + tri_csa32 pp1_1_csa_23( + .vd(vdd), + .gd(gnd), + .a(pp0_2[23]), //i-- + .b(pp0_3[23]), //i-- + .c(pp0_4[23]), //i-- + .sum(pp1_1_sum[23]), //o-- + .car(pp1_1_car[22]) //o-- + ); + + tri_csa32 pp1_1_csa_22( + .vd(vdd), + .gd(gnd), + .a(pp0_2[22]), //i-- + .b(pp0_3[22]), //i-- + .c(pp0_4[22]), //i-- + .sum(pp1_1_sum[22]), //o-- + .car(pp1_1_car[21]) //o-- + ); + + tri_csa32 pp1_1_csa_21( + .vd(vdd), + .gd(gnd), + .a(pp0_2[21]), //i-- + .b(pp0_3[21]), //i-- + .c(pp0_4[21]), //i-- + .sum(pp1_1_sum[21]), //o-- + .car(pp1_1_car[20]) //o-- + ); + + tri_csa32 pp1_1_csa_20( + .vd(vdd), + .gd(gnd), + .a(pp0_2[20]), //i-- + .b(pp0_3[20]), //i-- + .c(pp0_4[20]), //i-- + .sum(pp1_1_sum[20]), //o-- + .car(pp1_1_car[19]) //o-- + ); + + tri_csa32 pp1_1_csa_19( + .vd(vdd), + .gd(gnd), + .a(pp0_2[19]), //i-- + .b(pp0_3[19]), //i-- + .c(pp0_4[19]), //i-- + .sum(pp1_1_sum[19]), //o-- + .car(pp1_1_car[18]) //o-- + ); + + tri_csa32 pp1_1_csa_18( + .vd(vdd), + .gd(gnd), + .a(pp0_2[18]), //i-- + .b(pp0_3[18]), //i-- + .c(pp0_4[18]), //i-- + .sum(pp1_1_sum[18]), //o-- + .car(pp1_1_car[17]) //o-- + ); + + tri_csa32 pp1_1_csa_17( + .vd(vdd), + .gd(gnd), + .a(pp0_2[17]), //i-- + .b(pp0_3[17]), //i-- + .c(pp0_4[17]), //i-- + .sum(pp1_1_sum[17]), //o-- + .car(pp1_1_car[16]) //o-- + ); + + tri_csa32 pp1_1_csa_16( + .vd(vdd), + .gd(gnd), + .a(pp0_2[16]), //i-- + .b(pp0_3[16]), //i-- + .c(pp0_4[16]), //i-- + .sum(pp1_1_sum[16]), //o-- + .car(pp1_1_car[15]) //o-- + ); + + tri_csa32 pp1_1_csa_15( + .vd(vdd), + .gd(gnd), + .a(pp0_2[15]), //i-- + .b(pp0_3[15]), //i-- + .c(pp0_4[15]), //i-- + .sum(pp1_1_sum[15]), //o-- + .car(pp1_1_car[14]) //o-- + ); + + tri_csa32 pp1_1_csa_14( + .vd(vdd), + .gd(gnd), + .a(pp0_2[14]), //i-- + .b(pp0_3[14]), //i-- + .c(pp0_4[14]), //i-- + .sum(pp1_1_sum[14]), //o-- + .car(pp1_1_car[13]) //o-- + ); + + tri_csa32 pp1_1_csa_13( + .vd(vdd), + .gd(gnd), + .a(pp0_2[13]), //i-- + .b(pp0_3[13]), //i-- + .c(pp0_4[13]), //i-- + .sum(pp1_1_sum[13]), //o-- + .car(pp1_1_car[12]) //o-- + ); + + tri_csa32 pp1_1_csa_12( + .vd(vdd), + .gd(gnd), + .a(pp0_2[12]), //i-- + .b(pp0_3[12]), //i-- + .c(pp0_4[12]), //i-- + .sum(pp1_1_sum[12]), //o-- + .car(pp1_1_car[11]) //o-- + ); + + tri_fu_csa22_h2 pp1_1_csa_11( + .a(pp0_2[11]), //i-- + .b(pp0_3[11]), //i-- + .sum(pp1_1_sum[11]), //o-- + .car(pp1_1_car[10]) //o-- + ); + + tri_fu_csa22_h2 pp1_1_csa_10( + .a(pp0_2[10]), //i-- + .b(pp0_3[10]), //i-- + .sum(pp1_1_sum[10]), //o-- + .car(pp1_1_car[9]) //o-- + ); + assign pp1_1_sum[9] = pp0_2[9]; + assign pp1_1_sum[8] = pp0_2[8]; + + //====================================================== + //== compressor level 1 , row 2 + //====================================================== + + assign pp1_2_sum[36] = pp0_6[36]; + assign pp1_2_car[36] = pp0_7[36]; + assign pp1_2_sum[35] = pp0_7[35]; + assign pp1_2_car[35] = tidn; + assign pp1_2_car[34] = tidn; + + tri_csa32 pp1_2_csa_34( + .vd(vdd), + .gd(gnd), + .a(pp0_5[34]), //i-- + .b(pp0_6[34]), //i-- + .c(pp0_7[34]), //i-- + .sum(pp1_2_sum[34]), //o-- + .car(pp1_2_car[33]) //o-- + ); + + tri_fu_csa22_h2 pp1_2_csa_33( + .a(pp0_6[33]), //i-- + .b(pp0_7[33]), //i-- + .sum(pp1_2_sum[33]), //o-- + .car(pp1_2_car[32]) //o-- + ); + + tri_csa32 pp1_2_csa_32( + .vd(vdd), + .gd(gnd), + .a(pp0_5[32]), //i-- + .b(pp0_6[32]), //i-- + .c(pp0_7[32]), //i-- + .sum(pp1_2_sum[32]), //o-- + .car(pp1_2_car[31]) //o-- + ); + + tri_csa32 pp1_2_csa_31( + .vd(vdd), + .gd(gnd), + .a(pp0_5[31]), //i-- + .b(pp0_6[31]), //i-- + .c(pp0_7[31]), //i-- + .sum(pp1_2_sum[31]), //o-- + .car(pp1_2_car[30]) //o-- + ); + + tri_csa32 pp1_2_csa_30( + .vd(vdd), + .gd(gnd), + .a(pp0_5[30]), //i-- + .b(pp0_6[30]), //i-- + .c(pp0_7[30]), //i-- + .sum(pp1_2_sum[30]), //o-- + .car(pp1_2_car[29]) //o-- + ); + + tri_csa32 pp1_2_csa_29( + .vd(vdd), + .gd(gnd), + .a(pp0_5[29]), //i-- + .b(pp0_6[29]), //i-- + .c(pp0_7[29]), //i-- + .sum(pp1_2_sum[29]), //o-- + .car(pp1_2_car[28]) //o-- + ); + + tri_csa32 pp1_2_csa_28( + .vd(vdd), + .gd(gnd), + .a(pp0_5[28]), //i-- + .b(pp0_6[28]), //i-- + .c(pp0_7[28]), //i-- + .sum(pp1_2_sum[28]), //o-- + .car(pp1_2_car[27]) //o-- + ); + + tri_csa32 pp1_2_csa_27( + .vd(vdd), + .gd(gnd), + .a(pp0_5[27]), //i-- + .b(pp0_6[27]), //i-- + .c(pp0_7[27]), //i-- + .sum(pp1_2_sum[27]), //o-- + .car(pp1_2_car[26]) //o-- + ); + + tri_csa32 pp1_2_csa_26( + .vd(vdd), + .gd(gnd), + .a(pp0_5[26]), //i-- + .b(pp0_6[26]), //i-- + .c(pp0_7[26]), //i-- + .sum(pp1_2_sum[26]), //o-- + .car(pp1_2_car[25]) //o-- + ); + + tri_csa32 pp1_2_csa_25( + .vd(vdd), + .gd(gnd), + .a(pp0_5[25]), //i-- + .b(pp0_6[25]), //i-- + .c(pp0_7[25]), //i-- + .sum(pp1_2_sum[25]), //o-- + .car(pp1_2_car[24]) //o-- + ); + + tri_csa32 pp1_2_csa_24( + .vd(vdd), + .gd(gnd), + .a(pp0_5[24]), //i-- + .b(pp0_6[24]), //i-- + .c(pp0_7[24]), //i-- + .sum(pp1_2_sum[24]), //o-- + .car(pp1_2_car[23]) //o-- + ); + + tri_csa32 pp1_2_csa_23( + .vd(vdd), + .gd(gnd), + .a(pp0_5[23]), //i-- + .b(pp0_6[23]), //i-- + .c(pp0_7[23]), //i-- + .sum(pp1_2_sum[23]), //o-- + .car(pp1_2_car[22]) //o-- + ); + + tri_csa32 pp1_2_csa_22( + .vd(vdd), + .gd(gnd), + .a(pp0_5[22]), //i-- + .b(pp0_6[22]), //i-- + .c(pp0_7[22]), //i-- + .sum(pp1_2_sum[22]), //o-- + .car(pp1_2_car[21]) //o-- + ); + + tri_csa32 pp1_2_csa_21( + .vd(vdd), + .gd(gnd), + .a(pp0_5[21]), //i-- + .b(pp0_6[21]), //i-- + .c(pp0_7[21]), //i-- + .sum(pp1_2_sum[21]), //o-- + .car(pp1_2_car[20]) //o-- + ); + + tri_csa32 pp1_2_csa_20( + .vd(vdd), + .gd(gnd), + .a(pp0_5[20]), //i-- + .b(pp0_6[20]), //i-- + .c(pp0_7[20]), //i-- + .sum(pp1_2_sum[20]), //o-- + .car(pp1_2_car[19]) //o-- + ); + + tri_csa32 pp1_2_csa_19( + .vd(vdd), + .gd(gnd), + .a(pp0_5[19]), //i-- + .b(pp0_6[19]), //i-- + .c(pp0_7[19]), //i-- + .sum(pp1_2_sum[19]), //o-- + .car(pp1_2_car[18]) //o-- + ); + + tri_csa32 pp1_2_csa_18( + .vd(vdd), + .gd(gnd), + .a(pp0_5[18]), //i-- + .b(pp0_6[18]), //i-- + .c(pp0_7[18]), //i-- + .sum(pp1_2_sum[18]), //o-- + .car(pp1_2_car[17]) //o-- + ); + + tri_csa32 pp1_2_csa_17( + .vd(vdd), + .gd(gnd), + .a(pp0_5[17]), //i-- + .b(pp0_6[17]), //i-- + .c(pp0_7[17]), //i-- + .sum(pp1_2_sum[17]), //o-- + .car(pp1_2_car[16]) //o-- + ); + + tri_fu_csa22_h2 pp1_2_csa_16( + .a(pp0_5[16]), //i-- + .b(pp0_6[16]), //i-- + .sum(pp1_2_sum[16]), //o-- + .car(pp1_2_car[15]) //o-- + ); + assign pp1_2_sum[15] = pp0_5[15]; + assign pp1_2_sum[14] = pp0_5[14]; + + //=#################################################################### + //=# compressor tree level 2 + //=#################################################################### + + //= 0 1 2 3 + //= 0123456789012345678901234567890123456 + //==------------------------------------- + // sssssssssssssssssssssssss_s______ pp1_0_sum + // ccccccccccccccccccccccc_c________ pp1_0_car + // ________sssssssssssssssssssssss_s pp1_1_sum + // 222222223333333333333332312111101 + // sssssssssssssssssssssssssssssss_s pp2_0_sum + // cccccccccccccccccccccccc__c pp2_0_car + + //= 0 1 2 3 + //= 0123456789012345678901234567890123456 + //==------------------------------------- + // _________ccccccccccccccccccc__c______ pp1_1_car + // ______________sssssssssssssssssssssss pp1_2_sum + // _______________ccccccccccccccccccc__c pp1_2_car + // 1111123333333333333223222112 + // ssssssssssssssssssssssssssss pp2_1_sum + // ccccccccccccccccc_ccc__c pp2_1_car + + //====================================================== + //== compressor level 2 , row 0 + //====================================================== + + assign pp2_0_sum[32] = pp1_1_sum[32]; + assign pp2_0_sum[31] = tidn; + assign pp2_0_sum[30] = pp1_1_sum[30]; + assign pp2_0_sum[29] = pp1_1_sum[29]; + assign pp2_0_sum[28] = pp1_1_sum[28]; + assign pp2_0_sum[27] = pp1_1_sum[27]; + assign pp2_0_sum[26] = pp1_0_sum[26]; + assign pp2_0_car[26] = pp1_1_sum[26]; + assign pp2_0_sum[25] = pp1_1_sum[25]; + assign pp2_0_car[25] = tidn; + assign pp2_0_car[24] = tidn; + + tri_csa32 pp2_0_csa_24( + .vd(vdd), + .gd(gnd), + .a(pp1_0_sum[24]), //i-- + .b(pp1_0_car[24]), //i-- + .c(pp1_1_sum[24]), //i-- + .sum(pp2_0_sum[24]), //o-- + .car(pp2_0_car[23]) //o-- + ); + + tri_fu_csa22_h2 pp2_0_csa_23( + .a(pp1_0_sum[23]), //i-- + .b(pp1_1_sum[23]), //i-- + .sum(pp2_0_sum[23]), //o-- + .car(pp2_0_car[22]) //o-- + ); + + tri_csa32 pp2_0_csa_22( + .vd(vdd), + .gd(gnd), + .a(pp1_0_sum[22]), //i-- + .b(pp1_0_car[22]), //i-- + .c(pp1_1_sum[22]), //i-- + .sum(pp2_0_sum[22]), //o-- + .car(pp2_0_car[21]) //o-- + ); + + tri_csa32 pp2_0_csa_21( + .vd(vdd), + .gd(gnd), + .a(pp1_0_sum[21]), //i-- + .b(pp1_0_car[21]), //i-- + .c(pp1_1_sum[21]), //i-- + .sum(pp2_0_sum[21]), //o-- + .car(pp2_0_car[20]) //o-- + ); + + tri_csa32 pp2_0_csa_20( + .vd(vdd), + .gd(gnd), + .a(pp1_0_sum[20]), //i-- + .b(pp1_0_car[20]), //i-- + .c(pp1_1_sum[20]), //i-- + .sum(pp2_0_sum[20]), //o-- + .car(pp2_0_car[19]) //o-- + ); + + tri_csa32 pp2_0_csa_19( + .vd(vdd), + .gd(gnd), + .a(pp1_0_sum[19]), //i-- + .b(pp1_0_car[19]), //i-- + .c(pp1_1_sum[19]), //i-- + .sum(pp2_0_sum[19]), //o-- + .car(pp2_0_car[18]) //o-- + ); + + tri_csa32 pp2_0_csa_18( + .vd(vdd), + .gd(gnd), + .a(pp1_0_sum[18]), //i-- + .b(pp1_0_car[18]), //i-- + .c(pp1_1_sum[18]), //i-- + .sum(pp2_0_sum[18]), //o-- + .car(pp2_0_car[17]) //o-- + ); + + tri_csa32 pp2_0_csa_17( + .vd(vdd), + .gd(gnd), + .a(pp1_0_sum[17]), //i-- + .b(pp1_0_car[17]), //i-- + .c(pp1_1_sum[17]), //i-- + .sum(pp2_0_sum[17]), //o-- + .car(pp2_0_car[16]) //o-- + ); + + tri_csa32 pp2_0_csa_16( + .vd(vdd), + .gd(gnd), + .a(pp1_0_sum[16]), //i-- + .b(pp1_0_car[16]), //i-- + .c(pp1_1_sum[16]), //i-- + .sum(pp2_0_sum[16]), //o-- + .car(pp2_0_car[15]) //o-- + ); + + tri_csa32 pp2_0_csa_15( + .vd(vdd), + .gd(gnd), + .a(pp1_0_sum[15]), //i-- + .b(pp1_0_car[15]), //i-- + .c(pp1_1_sum[15]), //i-- + .sum(pp2_0_sum[15]), //o-- + .car(pp2_0_car[14]) //o-- + ); + + tri_csa32 pp2_0_csa_14( + .vd(vdd), + .gd(gnd), + .a(pp1_0_sum[14]), //i-- + .b(pp1_0_car[14]), //i-- + .c(pp1_1_sum[14]), //i-- + .sum(pp2_0_sum[14]), //o-- + .car(pp2_0_car[13]) //o-- + ); + + tri_csa32 pp2_0_csa_13( + .vd(vdd), + .gd(gnd), + .a(pp1_0_sum[13]), //i-- + .b(pp1_0_car[13]), //i-- + .c(pp1_1_sum[13]), //i-- + .sum(pp2_0_sum[13]), //o-- + .car(pp2_0_car[12]) //o-- + ); + + tri_csa32 pp2_0_csa_12( + .vd(vdd), + .gd(gnd), + .a(pp1_0_sum[12]), //i-- + .b(pp1_0_car[12]), //i-- + .c(pp1_1_sum[12]), //i-- + .sum(pp2_0_sum[12]), //o-- + .car(pp2_0_car[11]) //o-- + ); + + tri_csa32 pp2_0_csa_11( + .vd(vdd), + .gd(gnd), + .a(pp1_0_sum[11]), //i-- + .b(pp1_0_car[11]), //i-- + .c(pp1_1_sum[11]), //i-- + .sum(pp2_0_sum[11]), //o-- + .car(pp2_0_car[10]) //o-- + ); + + tri_csa32 pp2_0_csa_10( + .vd(vdd), + .gd(gnd), + .a(pp1_0_sum[10]), //i-- + .b(pp1_0_car[10]), //i-- + .c(pp1_1_sum[10]), //i-- + .sum(pp2_0_sum[10]), //o-- + .car(pp2_0_car[9]) //o-- + ); + + tri_csa32 pp2_0_csa_9( + .vd(vdd), + .gd(gnd), + .a(pp1_0_sum[9]), //i-- + .b(pp1_0_car[9]), //i-- + .c(pp1_1_sum[9]), //i-- + .sum(pp2_0_sum[9]), //o-- + .car(pp2_0_car[8]) //o-- + ); + + tri_csa32 pp2_0_csa_8( + .vd(vdd), + .gd(gnd), + .a(pp1_0_sum[8]), //i-- + .b(pp1_0_car[8]), //i-- + .c(pp1_1_sum[8]), //i-- + .sum(pp2_0_sum[8]), //o-- + .car(pp2_0_car[7]) //o-- + ); + + tri_fu_csa22_h2 pp2_0_csa_7( + .a(pp1_0_sum[7]), //i-- + .b(pp1_0_car[7]), //i-- + .sum(pp2_0_sum[7]), //o-- + .car(pp2_0_car[6]) //o-- + ); + + tri_fu_csa22_h2 pp2_0_csa_6( + .a(pp1_0_sum[6]), //i-- + .b(pp1_0_car[6]), //i-- + .sum(pp2_0_sum[6]), //o-- + .car(pp2_0_car[5]) //o-- + ); + + tri_fu_csa22_h2 pp2_0_csa_5( + .a(pp1_0_sum[5]), //i-- + .b(pp1_0_car[5]), //i-- + .sum(pp2_0_sum[5]), //o-- + .car(pp2_0_car[4]) //o-- + ); + + tri_fu_csa22_h2 pp2_0_csa_4( + .a(pp1_0_sum[4]), //i-- + .b(pp1_0_car[4]), //i-- + .sum(pp2_0_sum[4]), //o-- + .car(pp2_0_car[3]) //o-- + ); + + tri_fu_csa22_h2 pp2_0_csa_3( + .a(pp1_0_sum[3]), //i-- + .b(pp1_0_car[3]), //i-- + .sum(pp2_0_sum[3]), //o-- + .car(pp2_0_car[2]) //o-- + ); + + tri_fu_csa22_h2 pp2_0_csa_2( + .a(pp1_0_sum[2]), //i-- + .b(pp1_0_car[2]), //i-- + .sum(pp2_0_sum[2]), //o-- + .car(pp2_0_car[1]) //o-- + ); + + tri_fu_csa22_h2 pp2_0_csa_1( + .a(pp1_0_sum[1]), //i-- + .b(pp1_0_car[1]), //i-- + .sum(pp2_0_sum[1]), //o-- + .car(pp2_0_car[0]) //o-- + ); + + tri_fu_csa22_h2 pp2_0_csa_0( + .a(pp1_0_sum[0]), //i-- + .b(pp1_0_car[0]), //i-- + .sum(pp2_0_sum[0]), //o-- + .car(pp2_0_car_unused) //o-- + ); + + //====================================================== + //== compressor level 2 , row 1 + //====================================================== + + //====================================================== + //== compressor level 2 , row 1 + //====================================================== + + assign pp2_1_sum[36] = pp1_2_sum[36]; + assign pp2_1_car[36] = pp1_2_car[36]; + assign pp2_1_sum[35] = pp1_2_sum[35]; + assign pp2_1_car[35] = tidn; + assign pp2_1_sum[34] = pp1_2_sum[34]; + assign pp2_1_car[34] = tidn; + assign pp2_1_sum[33] = pp1_2_sum[33]; + assign pp2_1_car[33] = pp1_2_car[33]; + assign pp2_1_sum[32] = pp1_2_sum[32]; + assign pp2_1_car[32] = pp1_2_car[32]; + assign pp2_1_sum[31] = pp1_2_sum[31]; + assign pp2_1_car[31] = pp1_2_car[31]; + assign pp2_1_car[30] = tidn; + + tri_csa32 pp2_1_csa_30( + .vd(vdd), + .gd(gnd), + .a(pp1_1_car[30]), //i-- + .b(pp1_2_sum[30]), //i-- + .c(pp1_2_car[30]), //i-- + .sum(pp2_1_sum[30]), //o-- + .car(pp2_1_car[29]) //o-- + ); + + tri_fu_csa22_h2 pp2_1_csa_29( + .a(pp1_2_sum[29]), //i-- + .b(pp1_2_car[29]), //i-- + .sum(pp2_1_sum[29]), //o-- + .car(pp2_1_car[28]) //o-- + ); + + tri_fu_csa22_h2 pp2_1_csa_28( + .a(pp1_2_sum[28]), //i-- + .b(pp1_2_car[28]), //i-- + .sum(pp2_1_sum[28]), //o-- + .car(pp2_1_car[27]) //o-- + ); + + tri_csa32 pp2_1_csa_27( + .vd(vdd), + .gd(gnd), + .a(pp1_1_car[27]), //i-- + .b(pp1_2_sum[27]), //i-- + .c(pp1_2_car[27]), //i-- + .sum(pp2_1_sum[27]), //o-- + .car(pp2_1_car[26]) //o-- + ); + + tri_csa32 pp2_1_csa_26( + .vd(vdd), + .gd(gnd), + .a(pp1_1_car[26]), //i-- + .b(pp1_2_sum[26]), //i-- + .c(pp1_2_car[26]), //i-- + .sum(pp2_1_sum[26]), //o-- + .car(pp2_1_car[25]) //o-- + ); + + tri_csa32 pp2_1_csa_25( + .vd(vdd), + .gd(gnd), + .a(pp1_1_car[25]), //i-- + .b(pp1_2_sum[25]), //i-- + .c(pp1_2_car[25]), //i-- + .sum(pp2_1_sum[25]), //o-- + .car(pp2_1_car[24]) //o-- + ); + + tri_csa32 pp2_1_csa_24( + .vd(vdd), + .gd(gnd), + .a(pp1_1_car[24]), //i-- + .b(pp1_2_sum[24]), //i-- + .c(pp1_2_car[24]), //i-- + .sum(pp2_1_sum[24]), //o-- + .car(pp2_1_car[23]) //o-- + ); + + tri_csa32 pp2_1_csa_23( + .vd(vdd), + .gd(gnd), + .a(pp1_1_car[23]), //i-- + .b(pp1_2_sum[23]), //i-- + .c(pp1_2_car[23]), //i-- + .sum(pp2_1_sum[23]), //o-- + .car(pp2_1_car[22]) //o-- + ); + + tri_csa32 pp2_1_csa_22( + .vd(vdd), + .gd(gnd), + .a(pp1_1_car[22]), //i-- + .b(pp1_2_sum[22]), //i-- + .c(pp1_2_car[22]), //i-- + .sum(pp2_1_sum[22]), //o-- + .car(pp2_1_car[21]) //o-- + ); + + tri_csa32 pp2_1_csa_21( + .vd(vdd), + .gd(gnd), + .a(pp1_1_car[21]), //i-- + .b(pp1_2_sum[21]), //i-- + .c(pp1_2_car[21]), //i-- + .sum(pp2_1_sum[21]), //o-- + .car(pp2_1_car[20]) //o-- + ); + + tri_csa32 pp2_1_csa_20( + .vd(vdd), + .gd(gnd), + .a(pp1_1_car[20]), //i-- + .b(pp1_2_sum[20]), //i-- + .c(pp1_2_car[20]), //i-- + .sum(pp2_1_sum[20]), //o-- + .car(pp2_1_car[19]) //o-- + ); + + tri_csa32 pp2_1_csa_19( + .vd(vdd), + .gd(gnd), + .a(pp1_1_car[19]), //i-- + .b(pp1_2_sum[19]), //i-- + .c(pp1_2_car[19]), //i-- + .sum(pp2_1_sum[19]), //o-- + .car(pp2_1_car[18]) //o-- + ); + + tri_csa32 pp2_1_csa_18( + .vd(vdd), + .gd(gnd), + .a(pp1_1_car[18]), //i-- + .b(pp1_2_sum[18]), //i-- + .c(pp1_2_car[18]), //i-- + .sum(pp2_1_sum[18]), //o-- + .car(pp2_1_car[17]) //o-- + ); + + tri_csa32 pp2_1_csa_17( + .vd(vdd), + .gd(gnd), + .a(pp1_1_car[17]), //i-- + .b(pp1_2_sum[17]), //i-- + .c(pp1_2_car[17]), //i-- + .sum(pp2_1_sum[17]), //o-- + .car(pp2_1_car[16]) //o-- + ); + + tri_csa32 pp2_1_csa_16( + .vd(vdd), + .gd(gnd), + .a(pp1_1_car[16]), //i-- + .b(pp1_2_sum[16]), //i-- + .c(pp1_2_car[16]), //i-- + .sum(pp2_1_sum[16]), //o-- + .car(pp2_1_car[15]) //o-- + ); + + tri_csa32 pp2_1_csa_15( + .vd(vdd), + .gd(gnd), + .a(pp1_1_car[15]), //i-- + .b(pp1_2_sum[15]), //i-- + .c(pp1_2_car[15]), //i-- + .sum(pp2_1_sum[15]), //o-- + .car(pp2_1_car[14]) //o-- + ); + + tri_fu_csa22_h2 pp2_1_csa_14( + .a(pp1_1_car[14]), //i-- + .b(pp1_2_sum[14]), //i-- + .sum(pp2_1_sum[14]), //o-- + .car(pp2_1_car[13]) //o-- + ); + assign pp2_1_sum[13] = pp1_1_car[13]; + assign pp2_1_sum[12] = pp1_1_car[12]; + assign pp2_1_sum[11] = pp1_1_car[11]; + assign pp2_1_sum[10] = pp1_1_car[10]; + assign pp2_1_sum[9] = pp1_1_car[9]; + + //=#################################################################### + //=# compressor tree level 3 + //=#################################################################### + + //= 0 1 2 3 + //= 0123456789012345678901234567890123456 + //==------------------------------------- + // sssssssssssssssssssssssssssssss_s pp2_0_sum + // cccccccccccccccccccccccc__c pp2_0_car + // ssssssssssssssssssssssssssss pp2_1_sum + // ccccccccccccccccc_ccc__c pp2_1_car + // 2222222223333444444444443343332232112 + + //====================================================== + //== compressor level 3 , row 0 + //====================================================== + + //off + //on + + tri_fu_csa22_h2 pp3_0_csa_36( + .a(pp2_1_sum[36]), //i-- + .b(pp2_1_car[36]), //i-- + .sum(pp3_0_sum[36]), //o-- + .car(pp3_0_car[35]) //o-- + ); + assign pp3_0_sum[35] = pp2_1_sum[35]; + assign pp3_0_sum[34] = pp2_1_sum[34]; + assign pp3_0_car[34] = tidn; + assign pp3_0_sum[33] = pp2_1_sum[33]; + assign pp3_0_car[33] = pp2_1_car[33]; + assign pp3_0_car[32] = tidn; + + tri_csa32 pp3_0_csa_32( + .vd(vdd), + .gd(gnd), + .a(pp2_0_sum[32]), //i-- + .b(pp2_1_sum[32]), //i-- + .c(pp2_1_car[32]), //i-- + .sum(pp3_0_sum[32]), //o-- + .car(pp3_0_car[31]) //o-- + ); + + tri_fu_csa22_h2 pp3_0_csa_31( + .a(pp2_1_sum[31]), //i-- + .b(pp2_1_car[31]), //i-- + .sum(pp3_0_sum[31]), //o-- + .car(pp3_0_car[30]) //o-- + ); + + tri_fu_csa22_h2 pp3_0_csa_30( + .a(pp2_0_sum[30]), //i-- + .b(pp2_1_sum[30]), //i-- + .sum(pp3_0_sum[30]), //o-- + .car(pp3_0_car[29]) //o-- + ); + + tri_csa32 pp3_0_csa_29( + .vd(vdd), + .gd(gnd), + .a(pp2_0_sum[29]), //i-- + .b(pp2_1_sum[29]), //i-- + .c(pp2_1_car[29]), //i-- + .sum(pp3_0_sum[29]), //o-- + .car(pp3_0_car[28]) //--o-- + ); + + tri_csa32 pp3_0_csa_28( + .vd(vdd), + .gd(gnd), + .a(pp2_0_sum[28]), //--i-- + .b(pp2_1_sum[28]), //--i-- + .c(pp2_1_car[28]), //--i-- + .sum(pp3_0_sum[28]), //--o-- + .car(pp3_0_car[27]) //--o-- + ); + + tri_csa32 pp3_0_csa_27( + .vd(vdd), + .gd(gnd), + .a(pp2_0_sum[27]), //--i-- + .b(pp2_1_sum[27]), //--i-- + .c(pp2_1_car[27]), //--i-- + .sum(pp3_0_sum[27]), //--o-- + .car(pp3_0_car[26]) //--o-- + ); + //-- MLT42_X1_A12TH + tri_csa42 pp3_0_csa_26( + .vd(vdd), + .gd(gnd), + .a(pp2_0_sum[26]), //--i-- + .b(pp2_0_car[26]), //--i-- + .c(pp2_1_sum[26]), //--i-- + .d(pp2_1_car[26]), //--i-- + .ki(tidn), //--i-- + .ko(pp3_0_ko[25]), //--i-- + .sum(pp3_0_sum[26]), //--o-- + .car(pp3_0_car[25]) //--o-- + ); + + tri_csa42 pp3_0_csa_25( + .vd(vdd), + .gd(gnd), + .a(pp2_0_sum[25]), //--i-- + .b(tidn), //--i-- + .c(pp2_1_sum[25]), //--i-- + .d(pp2_1_car[25]), //--i-- + .ki(pp3_0_ko[25]), //--i-- + .ko(pp3_0_ko[24]), //--i-- + .sum(pp3_0_sum[25]), //--o-- + .car(pp3_0_car[24]) //--o-- + ); + + tri_csa42 pp3_0_csa_24( + .vd(vdd), + .gd(gnd), + .a(pp2_0_sum[24]), //--i-- + .b(tidn), //--i-- + .c(pp2_1_sum[24]), //--i-- + .d(pp2_1_car[24]), //--i-- + .ki(pp3_0_ko[24]), //--i-- + .ko(pp3_0_ko[23]), //--i-- + .sum(pp3_0_sum[24]), //--o-- + .car(pp3_0_car[23]) //--o-- + ); + + tri_csa42 pp3_0_csa_23( + .vd(vdd), + .gd(gnd), + .a(pp2_0_sum[23]), //--i-- + .b(pp2_0_car[23]), //--i-- + .c(pp2_1_sum[23]), //--i-- + .d(pp2_1_car[23]), //--i-- + .ki(pp3_0_ko[23]), //--i-- + .ko(pp3_0_ko[22]), //--i-- + .sum(pp3_0_sum[23]), //--o-- + .car(pp3_0_car[22]) //--o-- + ); + + tri_csa42 pp3_0_csa_22( + .vd(vdd), + .gd(gnd), + .a(pp2_0_sum[22]), //--i-- + .b(pp2_0_car[22]), //--i-- + .c(pp2_1_sum[22]), //--i-- + .d(pp2_1_car[22]), //--i-- + .ki(pp3_0_ko[22]), //--i-- + .ko(pp3_0_ko[21]), //--i-- + .sum(pp3_0_sum[22]), //--o-- + .car(pp3_0_car[21]) //--o-- + ); + + tri_csa42 pp3_0_csa_21( + .vd(vdd), + .gd(gnd), + .a(pp2_0_sum[21]), //--i-- + .b(pp2_0_car[21]), //--i-- + .c(pp2_1_sum[21]), //--i-- + .d(pp2_1_car[21]), //--i-- + .ki(pp3_0_ko[21]), //--i-- + .ko(pp3_0_ko[20]), //--i-- + .sum(pp3_0_sum[21]), //--o-- + .car(pp3_0_car[20]) //--o-- + ); + + tri_csa42 pp3_0_csa_20( + .vd(vdd), + .gd(gnd), + .a(pp2_0_sum[20]), //--i-- + .b(pp2_0_car[20]), //--i-- + .c(pp2_1_sum[20]), //--i-- + .d(pp2_1_car[20]), //--i-- + .ki(pp3_0_ko[20]), //--i-- + .ko(pp3_0_ko[19]), //--i-- + .sum(pp3_0_sum[20]), //--o-- + .car(pp3_0_car[19]) //--o-- + ); + + tri_csa42 pp3_0_csa_19( + .vd(vdd), + .gd(gnd), + .a(pp2_0_sum[19]), //--i-- + .b(pp2_0_car[19]), //--i-- + .c(pp2_1_sum[19]), //--i-- + .d(pp2_1_car[19]), //--i-- + .ki(pp3_0_ko[19]), //--i-- + .ko(pp3_0_ko[18]), //--i-- + .sum(pp3_0_sum[19]), //--o-- + .car(pp3_0_car[18]) //--o-- + ); + + tri_csa42 pp3_0_csa_18( + .vd(vdd), + .gd(gnd), + .a(pp2_0_sum[18]), //--i-- + .b(pp2_0_car[18]), //--i-- + .c(pp2_1_sum[18]), //--i-- + .d(pp2_1_car[18]), //--i-- + .ki(pp3_0_ko[18]), //--i-- + .ko(pp3_0_ko[17]), //--i-- + .sum(pp3_0_sum[18]), //--o-- + .car(pp3_0_car[17]) //--o-- + ); + + tri_csa42 pp3_0_csa_17( + .vd(vdd), + .gd(gnd), + .a(pp2_0_sum[17]), //--i-- + .b(pp2_0_car[17]), //--i-- + .c(pp2_1_sum[17]), //--i-- + .d(pp2_1_car[17]), //--i-- + .ki(pp3_0_ko[17]), //--i-- + .ko(pp3_0_ko[16]), //--i-- + .sum(pp3_0_sum[17]), //--o-- + .car(pp3_0_car[16]) //--o-- + ); + + tri_csa42 pp3_0_csa_16( + .vd(vdd), + .gd(gnd), + .a(pp2_0_sum[16]), //--i-- + .b(pp2_0_car[16]), //--i-- + .c(pp2_1_sum[16]), //--i-- + .d(pp2_1_car[16]), //--i-- + .ki(pp3_0_ko[16]), //--i-- + .ko(pp3_0_ko[15]), //--i-- + .sum(pp3_0_sum[16]), //--o-- + .car(pp3_0_car[15]) //--o-- + ); + + tri_csa42 pp3_0_csa_15( + .vd(vdd), + .gd(gnd), + .a(pp2_0_sum[15]), //--i-- + .b(pp2_0_car[15]), //--i-- + .c(pp2_1_sum[15]), //--i-- + .d(pp2_1_car[15]), //--i-- + .ki(pp3_0_ko[15]), //--i-- + .ko(pp3_0_ko[14]), //--i-- + .sum(pp3_0_sum[15]), //--o-- + .car(pp3_0_car[14]) //--o-- + ); + + tri_csa42 pp3_0_csa_14( + .vd(vdd), + .gd(gnd), + .a(pp2_0_sum[14]), //--i-- + .b(pp2_0_car[14]), //--i-- + .c(pp2_1_sum[14]), //--i-- + .d(pp2_1_car[14]), //--i-- + .ki(pp3_0_ko[14]), //--i-- + .ko(pp3_0_ko[13]), //--i-- + .sum(pp3_0_sum[14]), //--o-- + .car(pp3_0_car[13]) //--o-- + ); + + tri_csa42 pp3_0_csa_13( + .vd(vdd), + .gd(gnd), + .a(pp2_0_sum[13]), //--i-- + .b(pp2_0_car[13]), //--i-- + .c(pp2_1_sum[13]), //--i-- + .d(pp2_1_car[13]), //--i-- + .ki(pp3_0_ko[13]), //--i-- + .ko(pp3_0_ko[12]), //--i-- + .sum(pp3_0_sum[13]), //--o-- + .car(pp3_0_car[12]) //--o-- + ); + + tri_csa42 pp3_0_csa_12( + .vd(vdd), + .gd(gnd), + .a(pp2_0_sum[12]), //--i-- + .b(pp2_0_car[12]), //--i-- + .c(pp2_1_sum[12]), //--i-- + .d(tidn), //--i-- + .ki(pp3_0_ko[12]), //--i-- + .ko(pp3_0_ko[11]), //--i-- + .sum(pp3_0_sum[12]), //--o-- + .car(pp3_0_car[11]) //--o-- + ); + + tri_csa42 pp3_0_csa_11( + .vd(vdd), + .gd(gnd), + .a(pp2_0_sum[11]), //--i-- + .b(pp2_0_car[11]), //--i-- + .c(pp2_1_sum[11]), //--i-- + .d(tidn), //--i-- + .ki(pp3_0_ko[11]), //--i-- + .ko(pp3_0_ko[10]), //--i-- + .sum(pp3_0_sum[11]), //--o-- + .car(pp3_0_car[10]) //--o-- + ); + + tri_csa42 pp3_0_csa_10( + .vd(vdd), + .gd(gnd), + .a(pp2_0_sum[10]), //--i-- + .b(pp2_0_car[10]), //--i-- + .c(pp2_1_sum[10]), //--i-- + .d(tidn), //--i-- + .ki(pp3_0_ko[10]), //--i-- + .ko(pp3_0_ko[9]), //--i-- + .sum(pp3_0_sum[10]), //--o-- + .car(pp3_0_car[9]) //--o-- + ); + + tri_csa42 pp3_0_csa_9( + .vd(vdd), + .gd(gnd), + .a(pp2_0_sum[9]), //--i-- + .b(pp2_0_car[9]), //--i-- + .c(pp2_1_sum[9]), //--i-- + .d(tidn), //--i-- + .ki(pp3_0_ko[9]), //--i-- + .ko(pp3_0_ko[8]), //--i-- + .sum(pp3_0_sum[9]), //--o-- + .car(pp3_0_car[8]) //--o-- + ); + + tri_csa32 pp3_0_csa_8( + .vd(vdd), + .gd(gnd), + .a(pp2_0_sum[8]), //--i-- + .b(pp2_0_car[8]), //--i-- + .c(pp3_0_ko[8]), //--i-- + .sum(pp3_0_sum[8]), //--o-- + .car(pp3_0_car[7]) //--o-- + ); + + tri_fu_csa22_h2 pp3_0_csa_7( + .a(pp2_0_sum[7]), //--i-- + .b(pp2_0_car[7]), //--i-- + .sum(pp3_0_sum[7]), //--o-- + .car(pp3_0_car[6]) //--o-- + ); + + tri_fu_csa22_h2 pp3_0_csa_6( + .a(pp2_0_sum[6]), //--i-- + .b(pp2_0_car[6]), //--i-- + .sum(pp3_0_sum[6]), //--o-- + .car(pp3_0_car[5]) //--o-- + ); + + tri_fu_csa22_h2 pp3_0_csa_5( + .a(pp2_0_sum[5]), //--i-- + .b(pp2_0_car[5]), //--i-- + .sum(pp3_0_sum[5]), //--o-- + .car(pp3_0_car[4]) //--o-- + ); + + tri_fu_csa22_h2 pp3_0_csa_4( + .a(pp2_0_sum[4]), //--i-- + .b(pp2_0_car[4]), //--i-- + .sum(pp3_0_sum[4]), //--o-- + .car(pp3_0_car[3]) //--o-- + ); + + tri_fu_csa22_h2 pp3_0_csa_3( + .a(pp2_0_sum[3]), //--i-- + .b(pp2_0_car[3]), //--i-- + .sum(pp3_0_sum[3]), //--o-- + .car(pp3_0_car[2]) //--o-- + ); + + tri_fu_csa22_h2 pp3_0_csa_2( + .a(pp2_0_sum[2]), //--i-- + .b(pp2_0_car[2]), //--i-- + .sum(pp3_0_sum[2]), //--o-- + .car(pp3_0_car[1]) //--o-- + ); + + tri_fu_csa22_h2 pp3_0_csa_1( + .a(pp2_0_sum[1]), //--i-- + .b(pp2_0_car[1]), //--i-- + .sum(pp3_0_sum[1]), //--o-- + .car(pp3_0_car[0]) //--o-- + ); + + tri_fu_csa22_h2 pp3_0_csa_0( + .a(pp2_0_sum[0]), //--i-- + .b(pp2_0_car[0]), //--i-- + .sum(pp3_0_sum[0]), //--o-- + .car(pp3_0_car_unused) //--o-- + ); + + //===================================================================== + + assign tbl_sum[0:36] = pp3_0_sum[0:36]; + assign tbl_car[0:35] = pp3_0_car[0:35]; + +endmodule diff --git a/dev/verilog/trilib/tri_fu_tblmul_bthdcd.v b/dev/verilog/trilib/tri_fu_tblmul_bthdcd.v new file mode 100755 index 0000000..75f896c --- /dev/null +++ b/dev/verilog/trilib/tri_fu_tblmul_bthdcd.v @@ -0,0 +1,112 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILE NAME : tri_fu_tblmul_bthdcd.vhdl +// *! DESCRIPTION : Booth Decode +// *!**************************************************************** + +`include "tri_a2o.vh" + +module tri_fu_tblmul_bthdcd( + i0, + i1, + i2, + s_neg, + s_x, + s_x2 +); + input i0; + input i1; + input i2; + output s_neg; + output s_x; + output s_x2; + + wire s_add; + wire sx1_a0_b; + wire sx1_a1_b; + wire sx1_t; + wire sx1_i; + wire sx2_a0_b; + wire sx2_a1_b; + wire sx2_t; + wire sx2_i; + wire i0_b; + wire i1_b; + wire i2_b; + + + //// -- 000 add sh1=0 sh2=0 sub_adj=0 + //// -- 001 add sh1=1 sh2=0 sub_adj=0 + //// -- 010 add sh1=1 sh2=0 sub_adj=0 + //// -- 011 add sh1=0 sh2=1 sub_adj=0 + //// -- 100 sub sh1=0 sh2=1 sub_adj=1 + //// -- 101 sub sh1=1 sh2=0 sub_adj=1 + //// -- 110 sub sh1=1 sh2=0 sub_adj=1 + //// -- 111 sub sh1=0 sh2=0 sub_adj=0 + //// + //// s_neg <= ( i0 ); + //// + //// s_x <= ( not i1 and i2 ) or + //// ( i1 and not i2 ); + //// s_x2 <= ( i0 and not i1 and not i2 ) or + //// ( not i0 and i1 and i2 ); + //// + //// sub_adj <= i0 and not( i1 and i2 ); + //// + + // logically correct + //---------------------------------- + // s_neg <= (i0); + // s_x <= ( not i1 and i2) or ( i1 and not i2); + // s_x2 <= (i0 and not i1 and not i2) or (not i0 and i1 and i2); + + assign i0_b = (~(i0)); + assign i1_b = (~(i1)); + assign i2_b = (~(i2)); + + assign s_add = (~(i0)); + assign s_neg = (~(s_add)); + + assign sx1_a0_b = (~(i1_b & i2)); + assign sx1_a1_b = (~(i1 & i2_b)); + assign sx1_t = (~(sx1_a0_b & sx1_a1_b)); + assign sx1_i = (~(sx1_t)); + assign s_x = (~(sx1_i)); + + assign sx2_a0_b = (~(i0 & i1_b & i2_b)); + assign sx2_a1_b = (~(i0_b & i1 & i2)); + assign sx2_t = (~(sx2_a0_b & sx2_a1_b)); + assign sx2_i = (~(sx2_t)); + assign s_x2 = (~(sx2_i)); + + +endmodule diff --git a/dev/verilog/trilib/tri_fu_tblmul_bthrow.v b/dev/verilog/trilib/tri_fu_tblmul_bthrow.v new file mode 100755 index 0000000..95169fa --- /dev/null +++ b/dev/verilog/trilib/tri_fu_tblmul_bthrow.v @@ -0,0 +1,248 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" + +module tri_fu_tblmul_bthrow( + x, + s_neg, + s_x, + s_x2, + q +); + + input [0:15] x; // + input s_neg; // negate the row + input s_x; // shift by 1 + input s_x2; // shift by 2 + output [0:16] q; // final output + + // ENTITY + + + parameter tiup = 1'b1; + parameter tidn = 1'b0; + + wire [0:16] left; + wire unused; + + ////################################################################ + ////# A row of the repeated part of the booth_mux row + ////################################################################ + + assign unused = left[0]; + + tri_fu_mul_bthmux u00( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(tidn), //i-- ******** + .left(left[0]), //o-- [n] + .right(left[1]), //i-- [n+1] + .q(q[0]) //o-- + ); + + + tri_fu_mul_bthmux u01( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[0]), //i-- [n-1] + .left(left[1]), //o-- [n] + .right(left[2]), //i-- [n+1] + .q(q[1]) //o-- + ); + + + tri_fu_mul_bthmux u02( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[1]), //i-- + .left(left[2]), //o-- + .right(left[3]), //i-- + .q(q[2]) //o-- + ); + + + tri_fu_mul_bthmux u03( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[2]), //i-- + .left(left[3]), //o-- + .right(left[4]), //i-- + .q(q[3]) //o-- + ); + + + tri_fu_mul_bthmux u04( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[3]), //i-- + .left(left[4]), //o-- + .right(left[5]), //i-- + .q(q[4]) //o-- + ); + + + tri_fu_mul_bthmux u05( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[4]), //i-- + .left(left[5]), //o-- + .right(left[6]), //i-- + .q(q[5]) //o-- + ); + + + tri_fu_mul_bthmux u06( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[5]), //i-- + .left(left[6]), //o-- + .right(left[7]), //i-- + .q(q[6]) //o-- + ); + + + tri_fu_mul_bthmux u07( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[6]), //i-- + .left(left[7]), //o-- + .right(left[8]), //i-- + .q(q[7]) //o-- + ); + + + tri_fu_mul_bthmux u08( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[7]), //i-- + .left(left[8]), //o-- + .right(left[9]), //i-- + .q(q[8]) //o-- + ); + + + tri_fu_mul_bthmux u09( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[8]), //i-- + .left(left[9]), //o-- + .right(left[10]), //i-- + .q(q[9]) //o-- + ); + + + tri_fu_mul_bthmux u10( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[9]), //i-- + .left(left[10]), //o-- + .right(left[11]), //i-- + .q(q[10]) //o-- + ); + + + tri_fu_mul_bthmux u11( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[10]), //i-- + .left(left[11]), //o-- + .right(left[12]), //i-- + .q(q[11]) //o-- + ); + + + tri_fu_mul_bthmux u12( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[11]), //i-- + .left(left[12]), //o-- + .right(left[13]), //i-- + .q(q[12]) //o-- + ); + + + tri_fu_mul_bthmux u13( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[12]), //i-- + .left(left[13]), //o-- + .right(left[14]), //i-- + .q(q[13]) //o-- + ); + + + tri_fu_mul_bthmux u14( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[13]), //i-- + .left(left[14]), //o-- + .right(left[15]), //i-- + .q(q[14]) //o-- + ); + + + tri_fu_mul_bthmux u15( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[14]), //i-- + .left(left[15]), //o-- + .right(left[16]), //i-- + .q(q[15]) //o-- + ); + + + tri_fu_mul_bthmux u16( + .sneg(s_neg), //i-- + .sx(s_x), //i-- + .sx2(s_x2), //i-- + .x(x[15]), //i-- + .left(left[16]), //o-- + .right(s_neg), //i-- + .q(q[16]) //o-- + ); + +endmodule diff --git a/dev/verilog/trilib/tri_inv.v b/dev/verilog/trilib/tri_inv.v new file mode 100755 index 0000000..b8a281e --- /dev/null +++ b/dev/verilog/trilib/tri_inv.v @@ -0,0 +1,61 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILENAME : tri_inv.v +// *! DESCRIPTION : INVERTER gate +// *!**************************************************************** + +`include "tri_a2o.vh" + +module tri_inv( + y, + a +); + parameter WIDTH = 1; + parameter BTR = "INV_X2M_NONE"; //Specify full BTR name, else let tool select + output [0:WIDTH-1] y; + input [0:WIDTH-1] a; + + // tri_nand2 + genvar i; + + generate + begin : t + for (i = 0; i < WIDTH; i = i + 1) + begin : w + + not I0(y[i], a[i]); + + end // block: w + end + + endgenerate +endmodule diff --git a/dev/verilog/trilib/tri_inv_nlats.v b/dev/verilog/trilib/tri_inv_nlats.v new file mode 100755 index 0000000..d6381da --- /dev/null +++ b/dev/verilog/trilib/tri_inv_nlats.v @@ -0,0 +1,120 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILENAME : tri_inv_nlats.v +// *! DESCRIPTION : n-bit scannable m/s latch, for bit stacking, with inv gate in front +// *!**************************************************************** + +`include "tri_a2o.vh" + +module tri_inv_nlats( + vd, + gd, + lclk, + d1clk, + d2clk, + scanin, + scanout, + d, + qb +); + parameter OFFSET = 0; + parameter WIDTH = 1; + parameter INIT = 0; + parameter L2_LATCH_TYPE = 2; //L2_LATCH_TYPE = slave_latch; + //0=master_latch,1=L1,2=slave_latch,3=L2,4=flush_latch,5=L4 + parameter SYNTHCLONEDLATCH = ""; + parameter BTR = "NLI0001_X1_A12TH"; + parameter NEEDS_SRESET = 1; // for inferred latches + parameter DOMAIN_CROSSING = 0; + + inout vd; + inout gd; + input [0:`NCLK_WIDTH-1] lclk; + input d1clk; + input d2clk; + input [OFFSET:OFFSET+WIDTH-1] scanin; + output [OFFSET:OFFSET+WIDTH-1] scanout; + input [OFFSET:OFFSET+WIDTH-1] d; + output [OFFSET:OFFSET+WIDTH-1] qb; + + // tri_inv_nlats + + parameter [0:WIDTH-1] init_v = INIT; + parameter [0:WIDTH-1] ZEROS = {WIDTH{1'b0}}; + + generate + begin + wire sreset; + wire [0:WIDTH-1] int_din; + reg [0:WIDTH-1] int_dout; + wire [0:WIDTH-1] vact; + wire [0:WIDTH-1] vact_b; + wire [0:WIDTH-1] vsreset; + wire [0:WIDTH-1] vsreset_b; + wire [0:WIDTH-1] vthold; + wire [0:WIDTH-1] vthold_b; + wire [0:WIDTH-1] din; + (* analysis_not_referenced="true" *) + wire unused; + + if (NEEDS_SRESET == 1) + begin : rst + assign sreset = lclk[1]; + end + if (NEEDS_SRESET != 1) + begin : no_rst + assign sreset = 1'b0; + end + + assign vsreset = {WIDTH{sreset}}; + assign vsreset_b = {WIDTH{~sreset}}; + assign din = d; // Output is inverted, so don't invert here + assign int_din = (vsreset_b & din) | (vsreset & init_v); + + assign vact = {WIDTH{d1clk}}; + assign vact_b = {WIDTH{~d1clk}}; + + assign vthold_b = {WIDTH{d2clk}}; + assign vthold = {WIDTH{~d2clk}}; + + + always @(posedge lclk[0]) + begin: l + int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout); + end + assign qb = (~int_dout); + assign scanout = ZEROS; + + assign unused = | {vd, gd, lclk, scanin}; + end + endgenerate +endmodule diff --git a/dev/verilog/trilib/tri_iuq_cpl_arr.v b/dev/verilog/trilib/tri_iuq_cpl_arr.v new file mode 100755 index 0000000..baf3bc1 --- /dev/null +++ b/dev/verilog/trilib/tri_iuq_cpl_arr.v @@ -0,0 +1,343 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 fs / 1 fs + +// *!**************************************************************** +// *! FILENAME : tri_iuq_cpl_arr.v +// *! DESCRIPTION : iuq completion array (fpga model) +// *!**************************************************************** + +`include "tri_a2o.vh" + +module tri_iuq_cpl_arr(gnd, vdd, nclk, delay_lclkr_dc, mpw1_dc_b, mpw2_dc_b, force_t, thold_0_b, sg_0, scan_in, scan_out, re0, ra0, do0, re1, ra1, do1, we0, wa0, di0, we1, wa1, di1, perr); + parameter ADDRESSABLE_PORTS = 64; // number of addressable register in this array + parameter ADDRESSBUS_WIDTH = 6; // width of the bus to address all ports (2^ADDRESSBUS_WIDTH >= addressable_ports) + parameter PORT_BITWIDTH = 64; // bitwidth of ports + parameter LATCHED_READ = 1'b1; + parameter LATCHED_READ_DATA = 1'b1; + parameter LATCHED_WRITE = 1'b1; + + // POWER PINS + (* ground_pin=1 *) + inout gnd; + (* power_pin=1 *) + inout vdd; + + input [0:`NCLK_WIDTH-1] nclk; + + //------------------------------------------------------------------- + // Pervasive + //------------------------------------------------------------------- + input delay_lclkr_dc; + input mpw1_dc_b; + input mpw2_dc_b; + input force_t; + input thold_0_b; + input sg_0; + input scan_in; + output scan_out; + + //------------------------------------------------------------------- + // Functional + //------------------------------------------------------------------- + input re0; + input [0:ADDRESSBUS_WIDTH-1] ra0; + output [0:PORT_BITWIDTH-1] do0; + + input re1; + input [0:ADDRESSBUS_WIDTH-1] ra1; + output [0:PORT_BITWIDTH-1] do1; + + input we0; + input [0:ADDRESSBUS_WIDTH-1] wa0; + input [0:PORT_BITWIDTH-1] di0; + + input we1; + input [0:ADDRESSBUS_WIDTH-1] wa1; + input [0:PORT_BITWIDTH-1] di1; + + output perr; + + reg re0_q; + reg we0_q; + reg [0:ADDRESSBUS_WIDTH-1] ra0_q; + reg [0:ADDRESSBUS_WIDTH-1] wa0_q; + reg [0:PORT_BITWIDTH-1] do0_q; + wire [0:PORT_BITWIDTH-1] do0_d; + reg [0:PORT_BITWIDTH-1] di0_q; + + reg re1_q; + reg we1_q; + reg [0:ADDRESSBUS_WIDTH-1] ra1_q; + reg [0:ADDRESSBUS_WIDTH-1] wa1_q; + reg [0:PORT_BITWIDTH-1] do1_q; + wire [0:PORT_BITWIDTH-1] do1_d; + reg [0:PORT_BITWIDTH-1] di1_q; + + wire correct_clk; + wire reset; + wire reset_hi; + reg reset_q; + + wire [0:PORT_BITWIDTH-1] dout0; //std + wire wen0; //std + wire [0:ADDRESSBUS_WIDTH-1] addr_w0; //std + wire [0:ADDRESSBUS_WIDTH-1] addr_r0; //std + wire [0:PORT_BITWIDTH-1] din0; //std + + wire [0:PORT_BITWIDTH-1] dout1; //std + wire wen1; //std + wire [0:ADDRESSBUS_WIDTH-1] addr_w1; //std + wire [0:ADDRESSBUS_WIDTH-1] addr_r1; //std + wire [0:PORT_BITWIDTH-1] din1; //std + + reg we1_latch_q; + reg [0:ADDRESSBUS_WIDTH-1] wa1_latch_q; + reg [0:PORT_BITWIDTH-1] di1_latch_q; + + + (* analysis_not_referenced="true" *) + wire unused_SPO_0; + (* analysis_not_referenced="true" *) + wire unused_SPO_1; + + + generate + assign reset = nclk[1]; + assign correct_clk = nclk[0]; + + assign reset_hi = reset; + + + // Slow Latches (nclk) + + always @(posedge correct_clk or posedge reset) + begin: slatch + begin + if (reset == 1'b1) + we1_latch_q <= 1'b0; + else + begin + we1_latch_q <= we1_q; + wa1_latch_q <= wa1_q; + di1_latch_q <= di1_q; + end + end + end + + + // repower latches for resets + always @(posedge correct_clk) + begin: rlatch + reset_q <= reset_hi; + end + + // need to select which array to write based on the lowest order bit of the address which will indicate odd or even itag + // when both we0 and we1 are both asserted it is assumed that the low order bit of wa0 will not be equal to the low order + // bit of wa1 + assign addr_w0 = (wa0_q[ADDRESSBUS_WIDTH-1]) ? {wa1_q[0:ADDRESSBUS_WIDTH-2], 1'b0 } : {wa0_q[0:ADDRESSBUS_WIDTH-2], 1'b0 }; + assign wen0 = (wa0_q[ADDRESSBUS_WIDTH-1]) ? we1_q : we0_q; + assign din0 = (wa0_q[ADDRESSBUS_WIDTH-1]) ? di1_q : di0_q; + assign addr_r0 = (ra0_q[ADDRESSBUS_WIDTH-1]) ? {ra1_q[0:ADDRESSBUS_WIDTH-2], 1'b0 } : {ra0_q[0:ADDRESSBUS_WIDTH-2], 1'b0 }; + + assign addr_w1 = (wa1_q[ADDRESSBUS_WIDTH-1]) ? {wa1_q[0:ADDRESSBUS_WIDTH-2], 1'b0 } : {wa0_q[0:ADDRESSBUS_WIDTH-2], 1'b0 }; + assign wen1 = (wa1_q[ADDRESSBUS_WIDTH-1]) ? we1_q : we0_q; + assign din1 = (wa1_q[ADDRESSBUS_WIDTH-1]) ? di1_q : di0_q; + assign addr_r1 = (ra1_q[ADDRESSBUS_WIDTH-1]) ? {ra1_q[0:ADDRESSBUS_WIDTH-2], 1'b0 } : {ra0_q[0:ADDRESSBUS_WIDTH-2], 1'b0 }; + + assign perr = 1'b0; + + begin : xhdl0 + genvar i; + for (i = 0; i <= PORT_BITWIDTH - 1; i = i + 1) + begin : array_gen0 + RAM64X1D #(.INIT(64'h0000000000000000)) RAM64X1D0( + .DPO(dout0[i]), + .SPO(unused_SPO_0), + + .A0(addr_w0[0]), + .A1(addr_w0[1]), + .A2(addr_w0[2]), + .A3(addr_w0[3]), + .A4(addr_w0[4]), + .A5(addr_w0[5]), + + //.A(addr_w0), + .D(din0[i]), + + .DPRA0(addr_r0[0]), + .DPRA1(addr_r0[1]), + .DPRA2(addr_r0[2]), + .DPRA3(addr_r0[3]), + .DPRA4(addr_r0[4]), + .DPRA5(addr_r0[5]), + + //.DPRA(addr_r0), + .WCLK(correct_clk), + .WE(wen0) + ); + + RAM64X1D #(.INIT(64'h0000000000000000)) RAM64X1D1( + .DPO(dout1[i]), + .SPO(unused_SPO_1), + + .A0(addr_w1[0]), + .A1(addr_w1[1]), + .A2(addr_w1[2]), + .A3(addr_w1[3]), + .A4(addr_w1[4]), + .A5(addr_w1[5]), + + //.A(addr_w1), + .D(din1[i]), + + .DPRA0(addr_r1[0]), + .DPRA1(addr_r1[1]), + .DPRA2(addr_r1[2]), + .DPRA3(addr_r1[3]), + .DPRA4(addr_r1[4]), + .DPRA5(addr_r1[5]), + + //.DPRA(addr_r1), + .WCLK(correct_clk), + .WE(wen1) + ); + + + end + end + + assign do0_d = (ra0_q[ADDRESSBUS_WIDTH-1]) ? dout1 : dout0; + assign do1_d = (ra1_q[ADDRESSBUS_WIDTH-1]) ? dout1 : dout0; + assign do0 = do0_q; + assign do1 = do1_q; + + if (LATCHED_READ == 1'b0) + begin : read_latched_false + always @(*) + begin + re0_q <= re0; + ra0_q <= ra0; + re1_q <= re1; + ra1_q <= ra1; + end + end + if (LATCHED_READ == 1'b1) + begin : read_latched_true + always @(posedge correct_clk) + begin: read_latches + if (correct_clk == 1'b1) + begin + if (reset_q == 1'b1) + begin + re0_q <= 1'b0; + ra0_q <= {ADDRESSBUS_WIDTH{1'b0}}; + re1_q <= 1'b0; + ra1_q <= {ADDRESSBUS_WIDTH{1'b0}}; + end + else + begin + re0_q <= re0; + ra0_q <= ra0; + re1_q <= re1; + ra1_q <= ra1; + end + end + end + end + + if (LATCHED_WRITE == 1'b0) + begin : write_latched_false + always @(*) + begin + we0_q <= we0; + wa0_q <= wa0; + di0_q <= di0; + we1_q <= we1; + wa1_q <= wa1; + di1_q <= di1; + end + end + if (LATCHED_WRITE == 1'b1) + begin : write_latched_true + always @(posedge correct_clk) + begin: write_latches + if (correct_clk == 1'b1) + begin + if (reset_q == 1'b1) + begin + we0_q <= 1'b0; + wa0_q <= {ADDRESSBUS_WIDTH{1'b0}}; + di0_q <= {PORT_BITWIDTH{1'b0}}; + we1_q <= 1'b0; + wa1_q <= {ADDRESSBUS_WIDTH{1'b0}}; + di1_q <= {PORT_BITWIDTH{1'b0}}; + end + else + begin + we0_q <= we0; + wa0_q <= wa0; + di0_q <= di0; + we1_q <= we1; + wa1_q <= wa1; + di1_q <= di1; + end + end + end + end + + if (LATCHED_READ_DATA == 1'b0) + begin : read_data_latched_false + always @(*) + begin + do0_q <= do0_d; + do1_q <= do1_d; + end + end + if (LATCHED_READ_DATA == 1'b1) + begin : read_data_latched_true + always @(posedge correct_clk) + begin: read_data_latches + if (correct_clk == 1'b1) + begin + if (reset_q == 1'b1) + begin + do0_q <= {PORT_BITWIDTH{1'b0}}; + do1_q <= {PORT_BITWIDTH{1'b0}}; + end + else + begin + do0_q <= do0_d; + do1_q <= do1_d; + end + end + end + end + endgenerate +endmodule diff --git a/dev/verilog/trilib/tri_lcbcntl_array_mac.v b/dev/verilog/trilib/tri_lcbcntl_array_mac.v new file mode 100755 index 0000000..c9c39e7 --- /dev/null +++ b/dev/verilog/trilib/tri_lcbcntl_array_mac.v @@ -0,0 +1,83 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILENAME : tri_lcbcntl_array_mac.v +// *! DESCRIPTION : Used to generate control signals for LCBs +// *!**************************************************************** + +`include "tri_a2o.vh" + +module tri_lcbcntl_array_mac( + vdd, + gnd, + sg, + nclk, + scan_in, + scan_diag_dc, + thold, + clkoff_dc_b, + delay_lclkr_dc, + act_dis_dc, + d_mode_dc, + mpw1_dc_b, + mpw2_dc_b, + scan_out +); + inout vdd; + inout gnd; + input sg; + input [0:`NCLK_WIDTH-1] nclk; + input scan_in; + input scan_diag_dc; + input thold; + output clkoff_dc_b; + output [0:4] delay_lclkr_dc; + output act_dis_dc; + output d_mode_dc; + output [0:4] mpw1_dc_b; + output mpw2_dc_b; + output scan_out; + + // tri_lcbcntl_array_mac + + (* analysis_not_referenced="true" *) + wire unused; + + assign clkoff_dc_b = 1'b1; + assign delay_lclkr_dc = 5'b00000; + assign act_dis_dc = 1'b0; + assign d_mode_dc = 1'b0; + assign mpw1_dc_b = 5'b11111; + assign mpw2_dc_b = 1'b1; + assign scan_out = 1'b0; + + assign unused = vdd | gnd | sg | (|nclk) | scan_in | scan_diag_dc | thold; +endmodule diff --git a/dev/verilog/trilib/tri_lcbcntl_mac.v b/dev/verilog/trilib/tri_lcbcntl_mac.v new file mode 100755 index 0000000..7e55632 --- /dev/null +++ b/dev/verilog/trilib/tri_lcbcntl_mac.v @@ -0,0 +1,83 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILENAME : tri_lcbcntl_mac.v +// *! DESCRIPTION : Used to generate control signals for LCBs +// *!**************************************************************** + +`include "tri_a2o.vh" + +module tri_lcbcntl_mac( + vdd, + gnd, + sg, + nclk, + scan_in, + scan_diag_dc, + thold, + clkoff_dc_b, + delay_lclkr_dc, + act_dis_dc, + d_mode_dc, + mpw1_dc_b, + mpw2_dc_b, + scan_out +); + inout vdd; + inout gnd; + input sg; + input [0:`NCLK_WIDTH-1] nclk; + input scan_in; + input scan_diag_dc; + input thold; + output clkoff_dc_b; + output [0:4] delay_lclkr_dc; + output act_dis_dc; + output d_mode_dc; + output [0:4] mpw1_dc_b; + output mpw2_dc_b; + output scan_out; + + // tri_lcbcntl_mac + + (* analysis_not_referenced="true" *) + wire unused; + + assign clkoff_dc_b = 1'b1; + assign delay_lclkr_dc = 5'b00000; + assign act_dis_dc = 1'b0; + assign d_mode_dc = 1'b0; + assign mpw1_dc_b = 5'b11111; + assign mpw2_dc_b = 1'b1; + assign scan_out = 1'b0; + + assign unused = vdd | gnd | sg | (|nclk) | scan_in | scan_diag_dc | thold; +endmodule diff --git a/dev/verilog/trilib/tri_lcbnd.v b/dev/verilog/trilib/tri_lcbnd.v new file mode 100755 index 0000000..5d11dce --- /dev/null +++ b/dev/verilog/trilib/tri_lcbnd.v @@ -0,0 +1,81 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILENAME : tri_lcbnd.v +// *! DESCRIPTION : Wrapper for nlat LCB - will not run in pulsed mode +// *!**************************************************************** + +`include "tri_a2o.vh" + +module tri_lcbnd( + vd, + gd, + act, + delay_lclkr, + mpw1_b, + mpw2_b, + nclk, + force_t, + sg, + thold_b, + d1clk, + d2clk, + lclk +); + parameter DOMAIN_CROSSING = 0; + + inout vd; + inout gd; + input act; + input delay_lclkr; + input mpw1_b; + input mpw2_b; + input[0:`NCLK_WIDTH-1] nclk; + input force_t; + input sg; + input thold_b; + output d1clk; + output d2clk; + output[0:`NCLK_WIDTH-1] lclk; + + // tri_lcbnd + wire gate_b; + (* analysis_not_referenced="true" *) + wire unused; + + assign unused = vd | gd | delay_lclkr | mpw1_b | mpw2_b | sg; + + assign gate_b = force_t | act; + + assign d1clk = gate_b; + assign d2clk = thold_b; + assign lclk = nclk; +endmodule diff --git a/dev/verilog/trilib/tri_lcbor.v b/dev/verilog/trilib/tri_lcbor.v new file mode 100755 index 0000000..3b179de --- /dev/null +++ b/dev/verilog/trilib/tri_lcbor.v @@ -0,0 +1,51 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILENAME : tri_lcbor.v +// *! DESCRIPTION : Used to generate LCB controls +// *!**************************************************************** + +module tri_lcbor(clkoff_b, thold, sg, act_dis, force_t, thold_b); + input clkoff_b; + input thold; + input sg; + input act_dis; + output force_t; + output thold_b; + + (* analysis_not_referenced="true" *) + wire unused; + + assign unused = clkoff_b | sg | act_dis; + + assign force_t = 1'b0; + assign thold_b = (~thold); +endmodule diff --git a/dev/verilog/trilib/tri_lcbs.v b/dev/verilog/trilib/tri_lcbs.v new file mode 100755 index 0000000..4c2b576 --- /dev/null +++ b/dev/verilog/trilib/tri_lcbs.v @@ -0,0 +1,67 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILENAME : tri_lcbs.v +// *! DESCRIPTION : Wrapper for slat LCB +// *!**************************************************************** + +`include "tri_a2o.vh" + +module tri_lcbs( + vd, + gd, + delay_lclkr, + nclk, + force_t, + thold_b, + dclk, + lclk +); + inout vd; + inout gd; + input delay_lclkr; + input[0:`NCLK_WIDTH-1] nclk; + input force_t; + input thold_b; + output dclk; + output[0:`NCLK_WIDTH-1] lclk; + + // tri_lcbs + + (* analysis_not_referenced="true" *) + wire unused; + + assign unused = vd | gd | delay_lclkr | force_t; + + // No scan chain in this methodology + assign dclk = thold_b; + assign lclk = nclk; +endmodule diff --git a/dev/verilog/trilib/tri_lq_rmw.v b/dev/verilog/trilib/tri_lq_rmw.v new file mode 100755 index 0000000..d06fa97 --- /dev/null +++ b/dev/verilog/trilib/tri_lq_rmw.v @@ -0,0 +1,735 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: XU LSU Load Data Rotator +// +//***************************************************************************** + +// ########################################################################################## +// Contents +// 1) 16 bit Unaligned Rotate to the Right Rotator +// 2) Little/Big Endian Support +// ########################################################################################## + +`include "tri_a2o.vh" + + +module tri_lq_rmw( + ex2_stq4_rd_stg_act, + ex2_stq4_rd_addr, + stq6_rd_data_wa, + stq6_rd_data_wb, + stq6_rd_data_wc, + stq6_rd_data_wd, + stq6_rd_data_we, + stq6_rd_data_wf, + stq6_rd_data_wg, + stq6_rd_data_wh, + stq5_stg_act, + stq5_arr_wren, + stq5_arr_wr_way, + stq5_arr_wr_addr, + stq5_arr_wr_bytew, + stq5_arr_wr_data, + stq7_byp_val_wabcd, + stq7_byp_val_wefgh, + stq7_byp_data_wabcd, + stq7_byp_data_wefgh, + stq8_byp_data_wabcd, + stq8_byp_data_wefgh, + stq_byp_val_wabcd, + stq_byp_val_wefgh, + dcarr_rd_stg_act, + dcarr_wr_stg_act, + dcarr_wr_way, + dcarr_wr_addr, + dcarr_wr_data_wabcd, + dcarr_wr_data_wefgh, + nclk, + vdd, + gnd, + d_mode_dc, + delay_lclkr_dc, + mpw1_dc_b, + mpw2_dc_b, + func_sl_force, + func_sl_thold_0_b, + sg_0, + scan_in, + scan_out +); + +// EX2/STQ4 Read Operation +input ex2_stq4_rd_stg_act; +input [52:59] ex2_stq4_rd_addr; + +// Read data for Read-Modify-Write +input [0:143] stq6_rd_data_wa; +input [0:143] stq6_rd_data_wb; +input [0:143] stq6_rd_data_wc; +input [0:143] stq6_rd_data_wd; +input [0:143] stq6_rd_data_we; +input [0:143] stq6_rd_data_wf; +input [0:143] stq6_rd_data_wg; +input [0:143] stq6_rd_data_wh; + +// Write Data for Read-Modify-Write +input stq5_stg_act; +input stq5_arr_wren; +input [0:7] stq5_arr_wr_way; +input [52:59] stq5_arr_wr_addr; +input [0:15] stq5_arr_wr_bytew; +input [0:143] stq5_arr_wr_data; + +// EX4 Load Bypass Data for Read/Write Collision detected in EX2 +output [0:3] stq7_byp_val_wabcd; +output [0:3] stq7_byp_val_wefgh; +output [0:143] stq7_byp_data_wabcd; +output [0:143] stq7_byp_data_wefgh; +output [0:143] stq8_byp_data_wabcd; +output [0:143] stq8_byp_data_wefgh; +output [0:3] stq_byp_val_wabcd; +output [0:3] stq_byp_val_wefgh; + +// Data Cache Array Write +output [0:7] dcarr_rd_stg_act; +output [0:7] dcarr_wr_stg_act; +output [0:7] dcarr_wr_way; +output [52:59] dcarr_wr_addr; +output [0:143] dcarr_wr_data_wabcd; +output [0:143] dcarr_wr_data_wefgh; + +(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) +input [0:`NCLK_WIDTH-1] nclk; +inout vdd; +inout gnd; +input d_mode_dc; +input delay_lclkr_dc; +input mpw1_dc_b; +input mpw2_dc_b; +input func_sl_force; +input func_sl_thold_0_b; +input sg_0; + +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) +input scan_in; +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) +output scan_out; + +wire [52:59] ex3_stq5_rd_addr_d; +wire [52:59] ex3_stq5_rd_addr_q; +wire stq6_stg_act_d; +wire stq6_stg_act_q; +wire stq7_stg_act_d; +wire stq7_stg_act_q; +wire stq6_wren_d; +wire stq6_wren_q; +wire stq7_wren_d; +wire stq7_wren_q; +wire [0:7] stq6_way_en_d; +wire [0:7] stq6_way_en_q; +wire [0:7] stq7_way_en_d; +wire [0:7] stq7_way_en_q; +wire [0:7] stq6_wr_way; +wire [52:59] stq6_addr_d; +wire [52:59] stq6_addr_q; +wire [52:59] stq7_addr_d; +wire [52:59] stq7_addr_q; +wire [0:143] stq6_gate_rd_data_wa; +wire [0:143] stq6_gate_rd_data_wb; +wire [0:143] stq6_gate_rd_data_wc; +wire [0:143] stq6_gate_rd_data_wd; +wire [0:143] stq6_gate_rd_data_we; +wire [0:143] stq6_gate_rd_data_wf; +wire [0:143] stq6_gate_rd_data_wg; +wire [0:143] stq6_gate_rd_data_wh; +wire [0:143] stq6_rd_data_wabcd; +wire [0:143] stq6_wr_data_wabcd; +wire [0:143] stq7_wr_data_wabcd_d; +wire [0:143] stq7_wr_data_wabcd_q; +wire [0:143] stq8_wr_data_wabcd_d; +wire [0:143] stq8_wr_data_wabcd_q; +wire [0:143] stq6_rd_data_wefgh; +wire [0:143] stq6_wr_data_wefgh; +wire [0:143] stq7_wr_data_wefgh_d; +wire [0:143] stq7_wr_data_wefgh_q; +wire [0:143] stq8_wr_data_wefgh_d; +wire [0:143] stq8_wr_data_wefgh_q; +wire ex2_stq4_addr_coll; +wire [0:7] ex2_stq4_way_coll; +wire stq6_rd_byp_val; +wire stq7_rd_byp_val; +wire stq6_wr_byp_val; +wire stq7_wr_byp_val; +wire stq5_byp_val; +wire [0:143] stq5_wr_bit; +wire [0:143] stq5_msk_bit; +wire [0:15] stq5_byte_en; +wire [0:15] stq6_byte_en_wabcd_d; +wire [0:15] stq6_byte_en_wabcd_q; +wire [0:143] stq6_wr_bit_wabcd; +wire [0:143] stq6_msk_bit_wabcd; +wire [0:15] stq6_byte_en_wefgh_d; +wire [0:15] stq6_byte_en_wefgh_q; +wire [0:143] stq6_wr_bit_wefgh; +wire [0:143] stq6_msk_bit_wefgh; +wire [0:143] stq6_stq7_byp_data_wabcd; +wire [0:143] stq5_byp_wr_data_wabcd; +wire [0:143] stq6_byp_wr_data_wabcd_d; +wire [0:143] stq6_byp_wr_data_wabcd_q; +wire [0:143] stq6_stq7_byp_data_wefgh; +wire [0:143] stq5_byp_wr_data_wefgh; +wire [0:143] stq6_byp_wr_data_wefgh_d; +wire [0:143] stq6_byp_wr_data_wefgh_q; +wire [0:3] stq7_byp_val_wabcd_d; +wire [0:3] stq7_byp_val_wabcd_q; +wire [0:3] stq7_byp_val_wefgh_d; +wire [0:3] stq7_byp_val_wefgh_q; +wire [0:3] stq_byp_val_wabcd_d; +wire [0:3] stq_byp_val_wabcd_q; +wire [0:3] stq_byp_val_wefgh_d; +wire [0:3] stq_byp_val_wefgh_q; + +parameter stq6_stg_act_offset = 0; +parameter stq7_stg_act_offset = stq6_stg_act_offset + 1; +parameter ex3_stq5_rd_addr_offset = stq7_stg_act_offset + 1; +parameter stq6_wren_offset = ex3_stq5_rd_addr_offset + 8; +parameter stq7_wren_offset = stq6_wren_offset + 1; +parameter stq6_way_en_offset = stq7_wren_offset + 1; +parameter stq7_way_en_offset = stq6_way_en_offset + 8; +parameter stq6_addr_offset = stq7_way_en_offset + 8; +parameter stq7_addr_offset = stq6_addr_offset + 8; +parameter stq7_wr_data_wabcd_offset = stq7_addr_offset + 8; +parameter stq7_wr_data_wefgh_offset = stq7_wr_data_wabcd_offset + 144; +parameter stq8_wr_data_wabcd_offset = stq7_wr_data_wefgh_offset + 144; +parameter stq8_wr_data_wefgh_offset = stq8_wr_data_wabcd_offset + 144; +parameter stq6_byte_en_wabcd_offset = stq8_wr_data_wefgh_offset + 144; +parameter stq6_byte_en_wefgh_offset = stq6_byte_en_wabcd_offset + 16; +parameter stq6_byp_wr_data_wabcd_offset = stq6_byte_en_wefgh_offset + 16; +parameter stq6_byp_wr_data_wefgh_offset = stq6_byp_wr_data_wabcd_offset + 144; +parameter stq7_byp_val_wabcd_offset = stq6_byp_wr_data_wefgh_offset + 144; +parameter stq7_byp_val_wefgh_offset = stq7_byp_val_wabcd_offset + 4; +parameter stq_byp_val_wabcd_offset = stq7_byp_val_wefgh_offset + 4; +parameter stq_byp_val_wefgh_offset = stq_byp_val_wabcd_offset + 4; +parameter scan_right = stq_byp_val_wefgh_offset + 4 - 1; + +wire tiup; +wire [0:scan_right] siv; +wire [0:scan_right] sov; + +assign tiup = 1'b1; +assign ex3_stq5_rd_addr_d = ex2_stq4_rd_addr; +assign stq6_stg_act_d = stq5_stg_act; +assign stq7_stg_act_d = stq6_stg_act_q; +assign stq6_wren_d = stq5_arr_wren; +assign stq7_wren_d = stq6_wren_q; +assign stq6_way_en_d = stq5_arr_wr_way; +assign stq7_way_en_d = stq6_way_en_q; +assign stq6_wr_way = {8{stq6_wren_q}} & stq6_way_en_q; +assign stq6_addr_d = stq5_arr_wr_addr; +assign stq7_addr_d = stq6_addr_q; + +// ############################################################################################# +// Data Cache Read/Write Merge +// ############################################################################################# +// Gate Way that is being updated +assign stq6_gate_rd_data_wa = {144{stq6_way_en_q[0]}} & stq6_rd_data_wa; +assign stq6_gate_rd_data_wb = {144{stq6_way_en_q[1]}} & stq6_rd_data_wb; +assign stq6_gate_rd_data_wc = {144{stq6_way_en_q[2]}} & stq6_rd_data_wc; +assign stq6_gate_rd_data_wd = {144{stq6_way_en_q[3]}} & stq6_rd_data_wd; +assign stq6_gate_rd_data_we = {144{stq6_way_en_q[4]}} & stq6_rd_data_we; +assign stq6_gate_rd_data_wf = {144{stq6_way_en_q[5]}} & stq6_rd_data_wf; +assign stq6_gate_rd_data_wg = {144{stq6_way_en_q[6]}} & stq6_rd_data_wg; +assign stq6_gate_rd_data_wh = {144{stq6_way_en_q[7]}} & stq6_rd_data_wh; + +// Merge Data Way A,B,C,D +assign stq6_rd_data_wabcd = stq6_gate_rd_data_wa | stq6_gate_rd_data_wb | + stq6_gate_rd_data_wc | stq6_gate_rd_data_wd; +assign stq6_wr_data_wabcd = (stq6_wr_bit_wabcd & stq6_byp_wr_data_wabcd_q) | (stq6_msk_bit_wabcd & stq6_rd_data_wabcd); +assign stq7_wr_data_wabcd_d = stq6_wr_data_wabcd; +assign stq8_wr_data_wabcd_d = stq7_wr_data_wabcd_q; + +// Merge Data Way E,F,G,H +assign stq6_rd_data_wefgh = stq6_gate_rd_data_we | stq6_gate_rd_data_wf | + stq6_gate_rd_data_wg | stq6_gate_rd_data_wh; +assign stq6_wr_data_wefgh = (stq6_wr_bit_wefgh & stq6_byp_wr_data_wefgh_q) | (stq6_msk_bit_wefgh & stq6_rd_data_wefgh); +assign stq7_wr_data_wefgh_d = stq6_wr_data_wefgh; +assign stq8_wr_data_wefgh_d = stq7_wr_data_wefgh_q; + +// ############################################################################################# +// Data Cache Write Data Bypass +// ############################################################################################# +// Read/Write Address Match +assign ex2_stq4_addr_coll = (ex2_stq4_rd_addr == stq6_addr_q); +assign ex2_stq4_way_coll = {8{ex2_stq4_addr_coll}} & stq6_wr_way; + +// Bypass Select Control +assign stq6_rd_byp_val = (ex3_stq5_rd_addr_q == stq6_addr_q) & stq6_wren_q; +assign stq7_rd_byp_val = (ex3_stq5_rd_addr_q == stq7_addr_q) & stq7_wren_q; +assign stq6_wr_byp_val = stq6_rd_byp_val & |(stq5_arr_wr_way & stq6_way_en_q); +assign stq7_wr_byp_val = stq7_rd_byp_val & |(stq5_arr_wr_way & stq7_way_en_q); +assign stq5_byp_val = stq6_wr_byp_val | stq7_wr_byp_val; + +// Byte Enable and Byte Mask generation +assign stq5_wr_bit = {9{ stq5_arr_wr_bytew}}; +assign stq5_msk_bit = {9{~stq5_arr_wr_bytew}}; +assign stq5_byte_en = stq5_arr_wr_bytew | {16{stq5_byp_val}}; +assign stq6_byte_en_wabcd_d = stq5_byte_en; +assign stq6_wr_bit_wabcd = {9{ stq6_byte_en_wabcd_q}}; +assign stq6_msk_bit_wabcd = {9{~stq6_byte_en_wabcd_q}}; +assign stq6_byte_en_wefgh_d = stq5_byte_en; +assign stq6_wr_bit_wefgh = {9{ stq6_byte_en_wefgh_q}}; +assign stq6_msk_bit_wefgh = {9{~stq6_byte_en_wefgh_q}}; + +// Need to add bypass logic with merged data from stq6 and stq7 for Way A,B,C,D groups +assign stq6_stq7_byp_data_wabcd = ({144{~stq6_wr_byp_val}} & stq7_wr_data_wabcd_q) | ({144{stq6_wr_byp_val}} & stq6_wr_data_wabcd); +assign stq5_byp_wr_data_wabcd = (stq5_wr_bit & stq5_arr_wr_data) | (stq5_msk_bit & stq6_stq7_byp_data_wabcd); +assign stq6_byp_wr_data_wabcd_d = stq5_byp_wr_data_wabcd; + +// Need to add bypass logic with merged data from stq6 and stq7 for Way E,F,G,H groups +assign stq6_stq7_byp_data_wefgh = ({144{~stq6_wr_byp_val}} & stq7_wr_data_wefgh_q) | ({144{stq6_wr_byp_val}} & stq6_wr_data_wefgh); +assign stq5_byp_wr_data_wefgh = (stq5_wr_bit & stq5_arr_wr_data) | (stq5_msk_bit & stq6_stq7_byp_data_wefgh); +assign stq6_byp_wr_data_wefgh_d = stq5_byp_wr_data_wefgh; + +// Data that needs to be bypassed between EX2 Load Pipe Read collision detected with STQ6 Store Pipe Write +assign stq7_byp_val_wabcd_d = {4{stq6_rd_byp_val}} & stq6_way_en_q[0:3]; +assign stq7_byp_val_wefgh_d = {4{stq6_rd_byp_val}} & stq6_way_en_q[4:7]; +//assign stq7_byp_data_wefgh = stq7_wr_data_wefgh_q; +assign stq_byp_val_wabcd_d = ({4{stq7_rd_byp_val}} & stq7_way_en_q[0:3]) | ({4{stq6_rd_byp_val}} & stq6_way_en_q[0:3]); +assign stq_byp_val_wefgh_d = ({4{stq7_rd_byp_val}} & stq7_way_en_q[4:7]) | ({4{stq6_rd_byp_val}} & stq6_way_en_q[4:7]); + +// ############################################################################################# +// Outputs +// ############################################################################################# +// Data Cache Array Read ACT +assign dcarr_rd_stg_act = {8{ex2_stq4_rd_stg_act}} & ~ex2_stq4_way_coll; + +// Data Cache Array Update +assign dcarr_wr_stg_act = stq6_wr_way; +assign dcarr_wr_way = stq6_wr_way; +assign dcarr_wr_addr = stq6_addr_q; +assign dcarr_wr_data_wabcd = stq6_wr_data_wabcd; +assign dcarr_wr_data_wefgh = stq6_wr_data_wefgh; + +// EX4 Load Data Bypass +assign stq7_byp_val_wabcd = stq7_byp_val_wabcd_q; +assign stq7_byp_val_wefgh = stq7_byp_val_wefgh_q; +assign stq7_byp_data_wabcd = stq7_wr_data_wabcd_q; +assign stq7_byp_data_wefgh = stq7_wr_data_wefgh_q; +assign stq8_byp_data_wabcd = stq8_wr_data_wabcd_q; +assign stq8_byp_data_wefgh = stq8_wr_data_wefgh_q; +assign stq_byp_val_wabcd = stq_byp_val_wabcd_q; +assign stq_byp_val_wefgh = stq_byp_val_wefgh_q; + +// ############################################################################################# +// Registers +// ############################################################################################# +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq6_stg_act_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq6_stg_act_offset]), + .scout(sov[stq6_stg_act_offset]), + .din(stq6_stg_act_d), + .dout(stq6_stg_act_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq7_stg_act_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq7_stg_act_offset]), + .scout(sov[stq7_stg_act_offset]), + .din(stq7_stg_act_d), + .dout(stq7_stg_act_q) +); + +tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex3_stq5_rd_addr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_stq5_rd_addr_offset:ex3_stq5_rd_addr_offset + 8 - 1]), + .scout(sov[ex3_stq5_rd_addr_offset:ex3_stq5_rd_addr_offset + 8 - 1]), + .din(ex3_stq5_rd_addr_d), + .dout(ex3_stq5_rd_addr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq6_arr_wren_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq6_wren_offset]), + .scout(sov[stq6_wren_offset]), + .din(stq6_wren_d), + .dout(stq6_wren_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq7_arr_wren_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq7_wren_offset]), + .scout(sov[stq7_wren_offset]), + .din(stq7_wren_d), + .dout(stq7_wren_q) +); + +tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) stq6_way_en_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq5_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq6_way_en_offset:stq6_way_en_offset + 8 - 1]), + .scout(sov[stq6_way_en_offset:stq6_way_en_offset + 8 - 1]), + .din(stq6_way_en_d), + .dout(stq6_way_en_q) +); + +tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) stq7_way_en_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq6_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq7_way_en_offset:stq7_way_en_offset + 8 - 1]), + .scout(sov[stq7_way_en_offset:stq7_way_en_offset + 8 - 1]), + .din(stq7_way_en_d), + .dout(stq7_way_en_q) +); + +tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) stq6_addr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq5_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq6_addr_offset:stq6_addr_offset + 8 - 1]), + .scout(sov[stq6_addr_offset:stq6_addr_offset + 8 - 1]), + .din(stq6_addr_d), + .dout(stq6_addr_q) +); + +tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) stq7_addr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq6_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq7_addr_offset:stq7_addr_offset + 8 - 1]), + .scout(sov[stq7_addr_offset:stq7_addr_offset + 8 - 1]), + .din(stq7_addr_d), + .dout(stq7_addr_q) +); + +tri_rlmreg_p #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq7_wr_data_wabcd_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq6_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq7_wr_data_wabcd_offset:stq7_wr_data_wabcd_offset + 144 - 1]), + .scout(sov[stq7_wr_data_wabcd_offset:stq7_wr_data_wabcd_offset + 144 - 1]), + .din(stq7_wr_data_wabcd_d), + .dout(stq7_wr_data_wabcd_q) +); + +tri_rlmreg_p #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq7_wr_data_wefgh_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq6_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq7_wr_data_wefgh_offset:stq7_wr_data_wefgh_offset + 144 - 1]), + .scout(sov[stq7_wr_data_wefgh_offset:stq7_wr_data_wefgh_offset + 144 - 1]), + .din(stq7_wr_data_wefgh_d), + .dout(stq7_wr_data_wefgh_q) +); + +tri_rlmreg_p #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq8_wr_data_wabcd_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq7_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq8_wr_data_wabcd_offset:stq8_wr_data_wabcd_offset + 144 - 1]), + .scout(sov[stq8_wr_data_wabcd_offset:stq8_wr_data_wabcd_offset + 144 - 1]), + .din(stq8_wr_data_wabcd_d), + .dout(stq8_wr_data_wabcd_q) +); + +tri_rlmreg_p #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq8_wr_data_wefgh_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq7_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq8_wr_data_wefgh_offset:stq8_wr_data_wefgh_offset + 144 - 1]), + .scout(sov[stq8_wr_data_wefgh_offset:stq8_wr_data_wefgh_offset + 144 - 1]), + .din(stq8_wr_data_wefgh_d), + .dout(stq8_wr_data_wefgh_q) +); + +tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) stq6_byte_en_wabcd_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq5_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq6_byte_en_wabcd_offset:stq6_byte_en_wabcd_offset + 16 - 1]), + .scout(sov[stq6_byte_en_wabcd_offset:stq6_byte_en_wabcd_offset + 16 - 1]), + .din(stq6_byte_en_wabcd_d), + .dout(stq6_byte_en_wabcd_q) +); + +tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) stq6_byte_en_wefgh_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq5_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq6_byte_en_wefgh_offset:stq6_byte_en_wefgh_offset + 16 - 1]), + .scout(sov[stq6_byte_en_wefgh_offset:stq6_byte_en_wefgh_offset + 16 - 1]), + .din(stq6_byte_en_wefgh_d), + .dout(stq6_byte_en_wefgh_q) +); + +tri_rlmreg_p #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq6_byp_wr_data_wabcd_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq5_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq6_byp_wr_data_wabcd_offset:stq6_byp_wr_data_wabcd_offset + 144 - 1]), + .scout(sov[stq6_byp_wr_data_wabcd_offset:stq6_byp_wr_data_wabcd_offset + 144 - 1]), + .din(stq6_byp_wr_data_wabcd_d), + .dout(stq6_byp_wr_data_wabcd_q) +); + +tri_rlmreg_p #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq6_byp_wr_data_wefgh_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq5_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq6_byp_wr_data_wefgh_offset:stq6_byp_wr_data_wefgh_offset + 144 - 1]), + .scout(sov[stq6_byp_wr_data_wefgh_offset:stq6_byp_wr_data_wefgh_offset + 144 - 1]), + .din(stq6_byp_wr_data_wefgh_d), + .dout(stq6_byp_wr_data_wefgh_q) +); + +tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) stq7_byp_val_wabcd_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq7_byp_val_wabcd_offset:stq7_byp_val_wabcd_offset + 4 - 1]), + .scout(sov[stq7_byp_val_wabcd_offset:stq7_byp_val_wabcd_offset + 4 - 1]), + .din(stq7_byp_val_wabcd_d), + .dout(stq7_byp_val_wabcd_q) +); + +tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) stq7_byp_val_wefgh_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq7_byp_val_wefgh_offset:stq7_byp_val_wefgh_offset + 4 - 1]), + .scout(sov[stq7_byp_val_wefgh_offset:stq7_byp_val_wefgh_offset + 4 - 1]), + .din(stq7_byp_val_wefgh_d), + .dout(stq7_byp_val_wefgh_q) +); + +tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) stq_byp_val_wabcd_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq_byp_val_wabcd_offset:stq_byp_val_wabcd_offset + 4 - 1]), + .scout(sov[stq_byp_val_wabcd_offset:stq_byp_val_wabcd_offset + 4 - 1]), + .din(stq_byp_val_wabcd_d), + .dout(stq_byp_val_wabcd_q) +); + +tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) stq_byp_val_wefgh_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq_byp_val_wefgh_offset:stq_byp_val_wefgh_offset + 4 - 1]), + .scout(sov[stq_byp_val_wefgh_offset:stq_byp_val_wefgh_offset + 4 - 1]), + .din(stq_byp_val_wefgh_d), + .dout(stq_byp_val_wefgh_q) +); + +assign siv[0:scan_right] = {sov[1:scan_right], scan_in}; +assign scan_out = sov[0]; + +endmodule diff --git a/dev/verilog/trilib/tri_nand2.v b/dev/verilog/trilib/tri_nand2.v new file mode 100755 index 0000000..efd8395 --- /dev/null +++ b/dev/verilog/trilib/tri_nand2.v @@ -0,0 +1,63 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILENAME : tri_nand2.v +// *! DESCRIPTION : Two input NAND gate +// *!**************************************************************** + +`include "tri_a2o.vh" + +module tri_nand2( + y, + a, + b +); + parameter WIDTH = 1; + parameter BTR = "NAND2_X2M_NONE"; //Specify full BTR name, else let tool select + output [0:WIDTH-1] y; + input [0:WIDTH-1] a; + input [0:WIDTH-1] b; + + // tri_nand2 + genvar i; + + generate + begin : t + for (i = 0; i < WIDTH; i = i + 1) + begin : w + + nand I0(y[i], a[i], b[i]); + + end // block: w + end + + endgenerate +endmodule diff --git a/dev/verilog/trilib/tri_nand2_nlats.v b/dev/verilog/trilib/tri_nand2_nlats.v new file mode 100755 index 0000000..19b1707 --- /dev/null +++ b/dev/verilog/trilib/tri_nand2_nlats.v @@ -0,0 +1,121 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILENAME : tri_nand2_nlats.v +// *! DESCRIPTION : n-bit scannable m/s latch, for bit stacking, with nand2 gate in front +// *!**************************************************************** + +`include "tri_a2o.vh" + +module tri_nand2_nlats( + vd, + gd, + lclk, + d1clk, + d2clk, + scanin, + scanout, + a1, + a2, + qb +); + parameter OFFSET = 0; + parameter WIDTH = 1; + parameter INIT = 0; + parameter L2_LATCH_TYPE = 2; //L2_LATCH_TYPE = slave_latch; + //0=master_latch,1=L1,2=slave_latch,3=L2,4=flush_latch,5=L4 + parameter SYNTHCLONEDLATCH = ""; + parameter BTR = "NLA0001_X1_A12TH"; + parameter NEEDS_SRESET = 1; // for inferred latches + + inout vd; + inout gd; + input [0:`NCLK_WIDTH-1] lclk; + input d1clk; + input d2clk; + input [OFFSET:OFFSET+WIDTH-1] scanin; + output [OFFSET:OFFSET+WIDTH-1] scanout; + input [OFFSET:OFFSET+WIDTH-1] a1; + input [OFFSET:OFFSET+WIDTH-1] a2; + output [OFFSET:OFFSET+WIDTH-1] qb; + + // tri_nand2_nlats + + parameter [0:WIDTH-1] init_v = INIT; + parameter [0:WIDTH-1] ZEROS = {WIDTH{1'b0}}; + + generate + begin + wire sreset; + wire [0:WIDTH-1] int_din; + reg [0:WIDTH-1] int_dout; + wire [0:WIDTH-1] vact; + wire [0:WIDTH-1] vact_b; + wire [0:WIDTH-1] vsreset; + wire [0:WIDTH-1] vsreset_b; + wire [0:WIDTH-1] vthold; + wire [0:WIDTH-1] vthold_b; + wire [0:WIDTH-1] din; + (* analysis_not_referenced="true" *) + wire unused; + + if (NEEDS_SRESET == 1) + begin : rst + assign sreset = lclk[1]; + end + if (NEEDS_SRESET != 1) + begin : no_rst + assign sreset = 1'b0; + end + + assign vsreset = {WIDTH{sreset}}; + assign vsreset_b = {WIDTH{~sreset}}; + assign din = a1 & a2; // Output is inverted, so just AND2 here + assign int_din = (vsreset_b & din) | (vsreset & init_v); + + assign vact = {WIDTH{d1clk}}; + assign vact_b = {WIDTH{~d1clk}}; + + assign vthold_b = {WIDTH{d2clk}}; + assign vthold = {WIDTH{~d2clk}}; + + + always @(posedge lclk[0]) + begin: l + int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout); + end + assign qb = (~int_dout); + assign scanout = ZEROS; + + assign unused = | {vd, gd, lclk, scanin}; + end + endgenerate +endmodule diff --git a/dev/verilog/trilib/tri_nand3.v b/dev/verilog/trilib/tri_nand3.v new file mode 100755 index 0000000..02cfda3 --- /dev/null +++ b/dev/verilog/trilib/tri_nand3.v @@ -0,0 +1,66 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILENAME : tri_nand3.v +// *! DESCRIPTION : Three input NAND gate +// *!**************************************************************** + +`include "tri_a2o.vh" + +module tri_nand3( + y, + a, + b, + c +); + parameter WIDTH = 1; + parameter BTR = "NAND3_X2M_NONE"; //Specify full BTR name, else let tool select + output [0:WIDTH-1] y; + input [0:WIDTH-1] a; + input [0:WIDTH-1] b; + input [0:WIDTH-1] c; + + // tri_nand3 + genvar i; + + generate + begin : t + for (i = 0; i < WIDTH; i = i + 1) + begin : w + + nand I0(y[i], a[i], b[i], c[i]); + + + end // block: w + end + + endgenerate +endmodule diff --git a/dev/verilog/trilib/tri_nand4.v b/dev/verilog/trilib/tri_nand4.v new file mode 100755 index 0000000..892ee62 --- /dev/null +++ b/dev/verilog/trilib/tri_nand4.v @@ -0,0 +1,67 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILENAME : tri_nand4.v +// *! DESCRIPTION : Four input NAND gate +// *!**************************************************************** + +`include "tri_a2o.vh" + +module tri_nand4( + y, + a, + b, + c, + d +); + parameter WIDTH = 1; + parameter BTR = "NAND4_X2M_NONE"; //Specify full BTR name, else let tool select + output [0:WIDTH-1] y; + input [0:WIDTH-1] a; + input [0:WIDTH-1] b; + input [0:WIDTH-1] c; + input [0:WIDTH-1] d; + // tri_nand3 + genvar i; + + generate + begin : t + for (i = 0; i < WIDTH; i = i + 1) + begin : w + + nand I0(y[i], a[i], b[i], c[i], d[i]); + + + end // block: w + end + + endgenerate +endmodule diff --git a/dev/verilog/trilib/tri_nlat.v b/dev/verilog/trilib/tri_nlat.v new file mode 100755 index 0000000..b6440ae --- /dev/null +++ b/dev/verilog/trilib/tri_nlat.v @@ -0,0 +1,122 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILENAME : tri_nlat.v +// *! DESCRIPTION : Basic n-bit latch w/ internal scan +// *!**************************************************************** + +`include "tri_a2o.vh" + +module tri_nlat( + vd, + gd, + d1clk, + d2clk, + lclk, + scan_in, + din, + q, + q_b, + scan_out +); + parameter OFFSET = 0; + parameter SCAN = 0; //SCAN = normal; + //0=normal,1=interleaved,2=reversed,3=reverse_interleaved + parameter RESET_INVERTS_SCAN = 1'b1; + parameter WIDTH = 1; + parameter INIT = 0; + parameter L2_LATCH_TYPE = 2; //L2_LATCH_TYPE = slave_latch; + //0=master_latch,1=L1,2=slave_latch,3=L2,4=flush_latch,5=L4 + parameter SYNTHCLONEDLATCH = ""; + parameter NEEDS_SRESET = 1; // for inferred latches + parameter DOMAIN_CROSSING = 0; // 0 - Internal Flop, 1 - Domain Crossing Input Flop (requires extra logic for ASICs) + + inout vd; + inout gd; + input d1clk; + input d2clk; + input [0:`NCLK_WIDTH-1] lclk; + input scan_in; + input [OFFSET:OFFSET+WIDTH-1] din; + output [OFFSET:OFFSET+WIDTH-1] q; + output [OFFSET:OFFSET+WIDTH-1] q_b; + output scan_out; + + // tri_nlat + + parameter [0:WIDTH-1] init_v = INIT; + + generate + begin + wire sreset; + wire [0:WIDTH-1] int_din; + reg [0:WIDTH-1] int_dout; + wire [0:WIDTH-1] vact; + wire [0:WIDTH-1] vact_b; + wire [0:WIDTH-1] vsreset; + wire [0:WIDTH-1] vsreset_b; + wire [0:WIDTH-1] vthold; + wire [0:WIDTH-1] vthold_b; + (* analysis_not_referenced="true" *) + wire unused; + + if (NEEDS_SRESET == 1) + begin : rst + assign sreset = lclk[1]; + end + if (NEEDS_SRESET != 1) + begin : no_rst + assign sreset = 1'b0; + end + + assign vsreset = {WIDTH{sreset}}; + assign vsreset_b = {WIDTH{~sreset}}; + assign int_din = (vsreset_b & din) | (vsreset & init_v); + + assign vact = {WIDTH{d1clk}}; + assign vact_b = {WIDTH{~d1clk}}; + + assign vthold_b = {WIDTH{d2clk}}; + assign vthold = {WIDTH{~d2clk}}; + + + always @(posedge lclk[0]) + begin: l + int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout); + end + assign q = int_dout; + assign q_b = (~int_dout); + assign scan_out = 1'b0; + + assign unused = | {vd, gd, lclk, scan_in}; + end + endgenerate +endmodule diff --git a/dev/verilog/trilib/tri_nlat_scan.v b/dev/verilog/trilib/tri_nlat_scan.v new file mode 100755 index 0000000..a8f6cc2 --- /dev/null +++ b/dev/verilog/trilib/tri_nlat_scan.v @@ -0,0 +1,121 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILENAME : tri_nlat_scan.v +// *! DESCRIPTION : Basic n-bit latch +// *!**************************************************************** + +`include "tri_a2o.vh" + +module tri_nlat_scan( + vd, + gd, + d1clk, + d2clk, + lclk, + din, + scan_in, + q, + q_b, + scan_out +); + parameter OFFSET = 0; + parameter WIDTH = 1; + parameter INIT = 0; + parameter RESET_INVERTS_SCAN = 1'b1; + parameter SYNTHCLONEDLATCH = ""; + parameter L2_LATCH_TYPE = 2; //L2_LATCH_TYPE = slave_latch; + //0=master_latch,1=L1,2=slave_latch,3=L2,4=flush_latch,5=L4 + parameter NEEDS_SRESET = 1; // for inferred latches + parameter DOMAIN_CROSSING = 0; // 0 - Internal Flop, 1 - Domain Crossing Input Flop (requires extra logic for ASICs) + + inout vd; + inout gd; + input d1clk; + input d2clk; + input [0:`NCLK_WIDTH-1] lclk; + input [OFFSET:OFFSET+WIDTH-1] din; + input [OFFSET:OFFSET+WIDTH-1] scan_in; + output [OFFSET:OFFSET+WIDTH-1] q; + output [OFFSET:OFFSET+WIDTH-1] q_b; + output [OFFSET:OFFSET+WIDTH-1] scan_out; + + // tri_nlat_scan + + parameter [0:WIDTH-1] init_v = INIT; + parameter [0:WIDTH-1] ZEROS = {WIDTH{1'b0}}; + + generate + begin + wire sreset; + wire [0:WIDTH-1] int_din; + reg [0:WIDTH-1] int_dout; + wire [0:WIDTH-1] vact; + wire [0:WIDTH-1] vact_b; + wire [0:WIDTH-1] vsreset; + wire [0:WIDTH-1] vsreset_b; + wire [0:WIDTH-1] vthold; + wire [0:WIDTH-1] vthold_b; + (* analysis_not_referenced="true" *) + wire unused; + + if (NEEDS_SRESET == 1) + begin : rst + assign sreset = lclk[1]; + end + if (NEEDS_SRESET != 1) + begin : no_rst + assign sreset = 1'b0; + end + + assign vsreset = {WIDTH{sreset}}; + assign vsreset_b = {WIDTH{~sreset}}; + assign int_din = (vsreset_b & din) | (vsreset & init_v); + + assign vact = {WIDTH{d1clk}}; + assign vact_b = {WIDTH{~d1clk}}; + + assign vthold_b = {WIDTH{d2clk}}; + assign vthold = {WIDTH{~d2clk}}; + + + always @(posedge lclk[0]) + begin: l + int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout); + end + assign q = int_dout; + assign q_b = (~int_dout); + assign scan_out = ZEROS; + + assign unused = | {vd, gd, lclk, scan_in}; + end + endgenerate +endmodule diff --git a/dev/verilog/trilib/tri_nor2.v b/dev/verilog/trilib/tri_nor2.v new file mode 100755 index 0000000..95bdfb0 --- /dev/null +++ b/dev/verilog/trilib/tri_nor2.v @@ -0,0 +1,63 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILENAME : tri_nor2.v +// *! DESCRIPTION : Two input NOR gate +// *!**************************************************************** + +`include "tri_a2o.vh" + +module tri_nor2( + y, + a, + b +); + parameter WIDTH = 1; + parameter BTR = "NOR2_X2M_NONE"; //Specify full BTR name, else let tool select + output [0:WIDTH-1] y; + input [0:WIDTH-1] a; + input [0:WIDTH-1] b; + + // tri_nor2 + genvar i; + + generate + begin : t + for (i = 0; i < WIDTH; i = i + 1) + begin : w + + nor I0(y[i], a[i], b[i]); + + end // block: w + end + + endgenerate +endmodule diff --git a/dev/verilog/trilib/tri_nor3.v b/dev/verilog/trilib/tri_nor3.v new file mode 100755 index 0000000..a7b871c --- /dev/null +++ b/dev/verilog/trilib/tri_nor3.v @@ -0,0 +1,65 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILENAME : tri_nor3.v +// *! DESCRIPTION : Three input NOR gate +// *!**************************************************************** + +`include "tri_a2o.vh" + +module tri_nor3( + y, + a, + b, + c +); + parameter WIDTH = 1; + parameter BTR = "NOR3_X2M_NONE"; //Specify full BTR name, else let tool select + output [0:WIDTH-1] y; + input [0:WIDTH-1] a; + input [0:WIDTH-1] b; + input [0:WIDTH-1] c; + + // tri_nor3 + genvar i; + + generate + begin : t + for (i = 0; i < WIDTH; i = i + 1) + begin : w + + nor I0(y[i], a[i], b[i], c[i]); + + end // block: w + end + + endgenerate +endmodule diff --git a/dev/verilog/trilib/tri_oai21.v b/dev/verilog/trilib/tri_oai21.v new file mode 100755 index 0000000..9223c28 --- /dev/null +++ b/dev/verilog/trilib/tri_oai21.v @@ -0,0 +1,67 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILENAME : tri_oai21.v +// *! DESCRIPTION : OAI21 gate +// *!**************************************************************** + +`include "tri_a2o.vh" + +module tri_oai21( + y, + a0, + a1, + b0 +); + parameter WIDTH = 1; + parameter BTR = "OAI21_X2M_NONE"; //Specify full BTR name, else let tool select + output [0:WIDTH-1] y; + input [0:WIDTH-1] a0; + input [0:WIDTH-1] a1; + input [0:WIDTH-1] b0; + + // tri_oai21 + genvar i; + wire [0:WIDTH-1] outA; + + generate + begin : t + for (i = 0; i < WIDTH; i = i + 1) + begin : w + + or I0(outA[i], a0[i], a1[i]); + nand I2(y[i], outA[i], b0[i]); + + end // block: w + end + + endgenerate +endmodule diff --git a/dev/verilog/trilib/tri_parity_recovery.v b/dev/verilog/trilib/tri_parity_recovery.v new file mode 100755 index 0000000..e65bc30 --- /dev/null +++ b/dev/verilog/trilib/tri_parity_recovery.v @@ -0,0 +1,815 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//***************************************************************************** +//* +//* TITLE: TRI_PARITY_RECOVERY +//* +//* NAME: tri_parity_recovery +//* +//***************************************************************************** + + `include "tri_a2o.vh" + +module tri_parity_recovery( + perr_si, + perr_so, + delay_lclkr, + mpw1_b, + mpw2_b, + nclk, + force_t, + thold_0_b, + sg_0, + + gnd, + vdd, + + ex3_hangcounter_trigger, + + ex3_a_parity_check, + ex3_b_parity_check, + ex3_c_parity_check, + ex3_s_parity_check, + + rf0_instr_fra, + rf0_instr_frb, + rf0_instr_frc, + rf0_tid, + + rf0_dcd_fra, + rf0_dcd_frb, + rf0_dcd_frc, + rf0_dcd_tid, + + ex1_instr_fra, + ex1_instr_frb, + ex1_instr_frc, + ex1_instr_frs, + + ex3_fra_v, + ex3_frb_v, + ex3_frc_v, + ex3_str_v, + + ex3_frs_byp, + + ex3_fdivsqrt_start, + ex3_instr_v, + msr_fp_act, + + cp_flush_1d, + + ex7_is_fixperr, + + xx_ex4_regfile_err_det, + xx_ex5_regfile_err_det, + xx_ex6_regfile_err_det, + xx_ex7_regfile_err_det, + xx_ex8_regfile_err_det, + + xx_ex1_perr_sm_instr_v, + xx_ex2_perr_sm_instr_v, + xx_ex3_perr_sm_instr_v, + xx_ex4_perr_sm_instr_v, + xx_ex5_perr_sm_instr_v, + xx_ex6_perr_sm_instr_v, + xx_ex7_perr_sm_instr_v, + xx_ex8_perr_sm_instr_v, + + xx_perr_sm_running, + + xx_ex2_perr_force_c, + xx_ex2_perr_fsel_ovrd, + + xx_perr_tid_l2, + xx_perr_sm_l2, + xx_perr_addr_l2, + + ex3_sto_parity_err, + xx_rv_hold_all, + + xx_ex0_regfile_ue, + xx_ex0_regfile_ce, + + xx_pc_err_regfile_parity, + xx_pc_err_regfile_ue + + + ); + parameter THREADS = 2; + + input perr_si; + output perr_so; + input [0:9] delay_lclkr; + + input [0:9] mpw1_b; + input [0:1] mpw2_b; + input [0:`NCLK_WIDTH-1] nclk; + input force_t; + input thold_0_b; + input sg_0; + + inout gnd; + inout vdd; + + input ex3_hangcounter_trigger; + + input ex3_a_parity_check; + input ex3_b_parity_check; + input ex3_c_parity_check; + input ex3_s_parity_check; + + input [0:5] rf0_instr_fra; + input [0:5] rf0_instr_frb; + input [0:5] rf0_instr_frc; + input [0:1] rf0_tid; + + output [0:5] rf0_dcd_fra; + output [0:5] rf0_dcd_frb; + output [0:5] rf0_dcd_frc; + output [0:1] rf0_dcd_tid; + + input [0:5] ex1_instr_fra; + input [0:5] ex1_instr_frb; + input [0:5] ex1_instr_frc; + input [0:5] ex1_instr_frs; + + input ex3_fra_v; + input ex3_frb_v; + input ex3_frc_v; + input ex3_str_v; + input ex3_frs_byp; + + input [0:1] ex3_fdivsqrt_start; + input [0:1] ex3_instr_v; + input msr_fp_act; + input [0:1] cp_flush_1d; + + output ex7_is_fixperr; + + output [0:1] xx_ex4_regfile_err_det; + output [0:1] xx_ex5_regfile_err_det; + output [0:1] xx_ex6_regfile_err_det; + output [0:1] xx_ex7_regfile_err_det; + output [0:1] xx_ex8_regfile_err_det; + + output xx_ex1_perr_sm_instr_v; + output xx_ex2_perr_sm_instr_v; + output xx_ex3_perr_sm_instr_v; + output xx_ex4_perr_sm_instr_v; + output xx_ex5_perr_sm_instr_v; + output xx_ex6_perr_sm_instr_v; + output xx_ex7_perr_sm_instr_v; + output xx_ex8_perr_sm_instr_v; + + output xx_perr_sm_running; + + output xx_ex2_perr_force_c; + output xx_ex2_perr_fsel_ovrd; + output [0:1] xx_perr_tid_l2; + + output [0:2] xx_perr_sm_l2; + output [0:5] xx_perr_addr_l2; + + output ex3_sto_parity_err; + output xx_rv_hold_all; + + output xx_ex0_regfile_ue; + output xx_ex0_regfile_ce; + + output [0:`THREADS-1] xx_pc_err_regfile_parity; + output [0:`THREADS-1] xx_pc_err_regfile_ue; + + // parity err --------- + + (* analysis_not_referenced="TRUE" *) // unused + wire [0:2] spare_unused; + + wire perr_sm_running; + wire [0:23] ex3_perr_si; + + wire [0:23] ex3_perr_so; + + wire [0:1] ex3_fpr_perr; + wire [0:1] ex3_fpr_reg_perr; + wire ex3_regfile_err_det_any; + wire ex3_capture_addr; + + wire [0:1] ex4_regfile_err_det_din; + wire [0:1] ex5_regfile_err_det_din; + wire [0:1] ex6_regfile_err_det_din; + wire [0:1] ex7_regfile_err_det_din; + wire regfile_seq_beg; + wire regfile_seq_end; + + wire ex4_regfile_err_det_any; + wire ex5_regfile_err_det_any; + wire ex6_regfile_err_det_any; + + wire [0:1] ex4_sto_err_det; + + wire [0:1] ex4_regfile_err_det; + wire [0:1] ex5_regfile_err_det; + wire [0:1] ex6_regfile_err_det; + wire [0:1] ex7_regfile_err_det; + wire [0:1] ex8_regfile_err_det; + wire ex3_f0a_perr; + wire ex3_f0c_perr; + wire ex3_f1b_perr; + wire ex3_f1s_perr; + wire [0:1] ex3_sto_perr; + wire [0:0] holdall_si; + wire [0:0] holdall_so; + + wire rv_hold_all_din; + wire rv_hold_all_q; + wire [0:1] err_regfile_parity; + wire [0:1] err_regfile_ue; + wire [0:1] ex3_abc_perr; + wire [0:1] ex3_abc_perr_x; + wire [0:1] ex3_abc_perr_y; + + wire ex1_perr_move_f0_to_f1; + wire ex1_perr_move_f1_to_f0; + + wire ex0_regfile_ce; + wire ex0_regfile_ue; + + wire [0:23] ex2_perr_si; + + wire [0:23] ex2_perr_so; + + wire [0:5] ex3_instr_fra; + wire [0:5] ex3_instr_frb; + wire [0:5] ex3_instr_frc; + wire [0:5] ex3_instr_frs; + wire [0:5] ex2_instr_fra; + wire [0:5] ex2_instr_frb; + wire [0:5] ex2_instr_frc; + wire [0:5] ex2_instr_frs; + + wire new_perr_sm_instr_v; + + wire rf0_perr_sm_instr_v; + wire rf0_perr_sm_instr_v_b; + wire ex0_perr_sm_instr_v; + wire ex1_perr_sm_instr_v; + wire ex2_perr_sm_instr_v; + wire ex3_perr_sm_instr_v; + wire ex4_perr_sm_instr_v; + wire ex5_perr_sm_instr_v; + wire ex6_perr_sm_instr_v; + wire ex7_perr_sm_instr_v; + wire ex8_perr_sm_instr_v; + + wire rf0_perr_move_f0_to_f1; + wire rf0_perr_move_f1_to_f0; + wire rf0_perr_fixed_itself; + wire perr_move_f0_to_f1_l2; + wire perr_move_f1_to_f0_l2; + wire rf0_perr_force_c; + wire ex0_perr_force_c; + wire ex1_perr_force_c; + wire ex2_perr_force_c; + + wire [0:5] perr_addr_din; + wire [0:5] perr_addr_l2; + wire [0:30] perr_ctl_si; + wire [0:30] perr_ctl_so; + wire perr_move_f0_to_f1; + wire perr_move_f1_to_f0; + wire [0:2] perr_sm_din; + wire [0:2] perr_sm_l2; + wire [0:2] perr_sm_ns; + wire [0:2] perr_sm_si; + wire [0:2] perr_sm_so; + + wire [0:1] perr_tid_din; + + wire [0:1] perr_tid_l2; + + wire rf0_regfile_ce; + wire rf0_regfile_ue; + + + wire [0:3] ex4_ctl_perr_si; + wire [0:3] ex4_ctl_perr_so; + + wire [0:8] exx_regfile_err_det_si; + wire [0:8] exx_regfile_err_det_so; + + wire [0:5] rf0_frb_iu_x_b; + wire [0:5] rf0_frb_perr_x_b; + wire [0:5] rf0_frc_iu_x_b; + wire [0:5] rf0_frc_perr_x_b; + + wire ex3_a_perr_check; + wire ex3_b_perr_check; + wire ex3_c_perr_check; + wire ex3_s_perr_check; + //------------- end parity + + wire tilo; + wire tihi; + wire tidn; + wire tiup; + + //------------------------------------------------------------------------------------------------- + assign tilo = 1'b0; + assign tihi = 1'b1; + assign tidn = 1'b0; + assign tiup = 1'b1; + + //---------------------------------------------------------------------- + // Parity State Machine / parity section + assign xx_ex4_regfile_err_det = ex4_regfile_err_det; + assign xx_ex5_regfile_err_det = ex5_regfile_err_det; + assign xx_ex6_regfile_err_det = ex6_regfile_err_det; + assign xx_ex7_regfile_err_det = ex7_regfile_err_det; + assign xx_ex8_regfile_err_det = ex8_regfile_err_det; + + assign xx_ex1_perr_sm_instr_v = ex1_perr_sm_instr_v; + assign xx_ex2_perr_sm_instr_v = ex2_perr_sm_instr_v; + assign xx_ex3_perr_sm_instr_v = ex3_perr_sm_instr_v; + assign xx_ex4_perr_sm_instr_v = ex4_perr_sm_instr_v; + assign xx_ex5_perr_sm_instr_v = ex5_perr_sm_instr_v; + assign xx_ex6_perr_sm_instr_v = ex6_perr_sm_instr_v; + assign xx_ex7_perr_sm_instr_v = ex7_perr_sm_instr_v; + assign xx_ex8_perr_sm_instr_v = ex8_perr_sm_instr_v; + + assign xx_perr_tid_l2 = perr_tid_l2; + assign xx_perr_sm_l2 = perr_sm_l2; + + assign ex4_regfile_err_det_din[0:1] = ex4_regfile_err_det[0:1] & (~cp_flush_1d[0:1]); + assign ex5_regfile_err_det_din[0:1] = ex5_regfile_err_det[0:1] & (~cp_flush_1d[0:1]); + assign ex6_regfile_err_det_din[0:1] = ex6_regfile_err_det[0:1] & (~cp_flush_1d[0:1]); + assign ex7_regfile_err_det_din[0:1] = ex7_regfile_err_det[0:1] & (~cp_flush_1d[0:1]); + + assign xx_ex0_regfile_ue = ex0_regfile_ue; + assign xx_ex0_regfile_ce = ex0_regfile_ce; + + assign xx_perr_addr_l2 = perr_addr_l2; + + + tri_rlmreg_p #(.INIT(0), .WIDTH(9)) exx_regfile_err_det_lat( + .nclk(nclk), + .act(tihi), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[9]), + .mpw1_b(mpw1_b[9]), + .mpw2_b(mpw2_b[1]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(exx_regfile_err_det_si[0:8]), + .scout(exx_regfile_err_det_so[0:8]), + //------------------------------------------- + .din({ ex4_regfile_err_det_din[0:1], + ex5_regfile_err_det_din[0:1], + ex6_regfile_err_det_din[0:1], + ex7_regfile_err_det_din[0:1], + ex6_perr_sm_instr_v + }), + + //------------------------------------------- + .dout({ ex5_regfile_err_det[0:1], + ex6_regfile_err_det[0:1], + ex7_regfile_err_det[0:1], + ex8_regfile_err_det[0:1], + ex7_is_fixperr + }) + ); + //------------------------------------------- + + tri_rlmreg_p #(.INIT(0), .WIDTH(4)) ex4_ctl_perr( + .nclk(nclk), + .act(tihi), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[4]), + .mpw1_b(mpw1_b[4]), + .mpw2_b(mpw2_b[0]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(ex4_ctl_perr_si[0:3]), + .scout(ex4_ctl_perr_so[0:3]), + //------------------------------------------- + .din({ + ex3_fpr_reg_perr[0:1], + ex3_sto_perr[0:1] + }), + //------------------------------------------- + .dout( { + ex4_regfile_err_det[0:1], + ex4_sto_err_det[0:1] + }) + ); + //------------------------------------------- + + + tri_rlmreg_p #(.INIT(0), .WIDTH(24)) ex2_perr( + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[2]), + .mpw1_b(mpw1_b[2]), + .mpw2_b(mpw2_b[0]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(ex2_perr_si[0:23]), + .scout(ex2_perr_so[0:23]), + .din({ex1_instr_frs[0:5], + ex1_instr_fra[0:5], + ex1_instr_frb[0:5], + ex1_instr_frc[0:5] + }), + //------------------------------------------- + .dout({ex2_instr_frs[0:5], + ex2_instr_fra[0:5], + ex2_instr_frb[0:5], + ex2_instr_frc[0:5] + }) + ); + + //------------------------------------------- + tri_rlmreg_p #(.INIT(0), .WIDTH(24)) ex3_perr( + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[3]), + .mpw1_b(mpw1_b[3]), + .mpw2_b(mpw2_b[0]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(ex3_perr_si[0:23]), + .scout(ex3_perr_so[0:23]), + .din({ex2_instr_frs[0:5], + ex2_instr_fra[0:5], + ex2_instr_frb[0:5], + ex2_instr_frc[0:5] + }), + //------------------------------------------- + .dout( {ex3_instr_frs[0:5], + ex3_instr_fra[0:5], + ex3_instr_frb[0:5], + ex3_instr_frc[0:5] + }) + ); + //------------------------------------------- + + + // Parity Checking + + assign ex3_a_perr_check = ex3_a_parity_check; + assign ex3_b_perr_check = ex3_b_parity_check; + assign ex3_c_perr_check = ex3_c_parity_check; + assign ex3_s_perr_check = ex3_s_parity_check; + + + assign ex3_sto_perr[0:1] = {2{(ex3_s_perr_check & ex3_str_v & ~ex3_frs_byp)}} & ex3_instr_v[0:1]; + + assign ex3_sto_parity_err = |(ex3_sto_perr); + + assign ex3_abc_perr_x = {2{((ex3_a_perr_check & ex3_fra_v) | + (ex3_b_perr_check & ex3_frb_v) | + (ex3_c_perr_check & ex3_frc_v)) }}; + + assign ex3_abc_perr_y = (ex3_instr_v[0:1] | ex3_fdivsqrt_start[0:1]); + + + assign ex3_abc_perr[0:1] = ex3_abc_perr_x[0:1] & ex3_abc_perr_y[0:1]; + + + assign ex3_fpr_perr[0:1] = (ex3_sto_perr[0:1] | ex3_abc_perr[0:1]) & (~cp_flush_1d[0:1]) & {2{msr_fp_act}}; + + assign ex3_regfile_err_det_any = |(ex3_fpr_perr); + + assign ex3_fpr_reg_perr[0:1] = ( ex3_abc_perr[0:1]) & (~cp_flush_1d[0:1]) & {2{msr_fp_act}}; + + + assign ex3_f0a_perr = ex3_a_perr_check & ex3_fra_v; + assign ex3_f0c_perr = ex3_c_perr_check & (ex3_frc_v | (perr_sm_l2[1] & ex3_perr_sm_instr_v)); + assign ex3_f1b_perr = ex3_b_perr_check & (ex3_frb_v | (perr_sm_l2[1] & ex3_perr_sm_instr_v)); + + + assign ex3_f1s_perr = ex3_s_perr_check & ex3_str_v; + + + assign ex4_regfile_err_det_any = |(ex4_regfile_err_det[0:1]) | |(ex4_sto_err_det[0:1]); + + + tri_rlmreg_p #(.INIT(4), .WIDTH(3)) perr_sm( + .nclk(nclk), + .act(tihi), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[9]), + .mpw1_b(mpw1_b[9]), + .mpw2_b(mpw2_b[1]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(perr_sm_si[0:2]), + .scout(perr_sm_so[0:2]), + .din(perr_sm_din[0:2]), + //------------------------------------------- + .dout( perr_sm_l2[0:2]) + ); + //------------------------------------------- + + tri_rlmreg_p #(.INIT(0), .WIDTH(31)) perr_ctl( + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[9]), + .mpw1_b(mpw1_b[9]), + .mpw2_b(mpw2_b[1]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(perr_ctl_si[0:30]), + .scout(perr_ctl_so[0:30]), + .din({ perr_addr_din[0:5], + perr_tid_din[0:1], + spare_unused[0:1], + perr_move_f0_to_f1, + perr_move_f1_to_f0, + rf0_perr_force_c, + ex0_perr_force_c, + ex1_perr_force_c, + new_perr_sm_instr_v, + rf0_perr_sm_instr_v, + ex0_perr_sm_instr_v, + ex1_perr_sm_instr_v, + ex2_perr_sm_instr_v, + ex3_perr_sm_instr_v, + ex4_perr_sm_instr_v, + ex5_perr_sm_instr_v, + ex6_perr_sm_instr_v, + ex7_perr_sm_instr_v, + ex4_regfile_err_det_any, + ex5_regfile_err_det_any, // ex3_regfile_err_det, //xu_fu_regfile_seq_beg, // need extra cycles for holdall to take effect + ex6_regfile_err_det_any, + regfile_seq_end, + rf0_regfile_ue, + rf0_regfile_ce}), + //------------------------------------------- + .dout({ perr_addr_l2[0:5], + perr_tid_l2[0:1], + spare_unused[0:1], + perr_move_f0_to_f1_l2, + perr_move_f1_to_f0_l2, + ex0_perr_force_c, + ex1_perr_force_c, + ex2_perr_force_c, + rf0_perr_sm_instr_v, + ex0_perr_sm_instr_v, + ex1_perr_sm_instr_v, + ex2_perr_sm_instr_v, + ex3_perr_sm_instr_v, + ex4_perr_sm_instr_v, + ex5_perr_sm_instr_v, + ex6_perr_sm_instr_v, + ex7_perr_sm_instr_v, + ex8_perr_sm_instr_v, + ex5_regfile_err_det_any, + ex6_regfile_err_det_any, + regfile_seq_beg, + spare_unused[2], + ex0_regfile_ue, + ex0_regfile_ce}) + ); + //------------------------------------------- + + assign rf0_perr_sm_instr_v_b = (~rf0_perr_sm_instr_v); + + // State 0 = 100 = Default, no parity error + // State 1 = 010 = Parity error detected. Flush System, and read out both entries + // State 2 = 001 = Move good to bad, or UE + + assign perr_sm_running = (~perr_sm_l2[0]); + assign xx_perr_sm_running = (~perr_sm_l2[0]); + + // Goto State0 at the end of the sequence. That's either after a UE, or writeback is done + assign perr_sm_ns[0] = (perr_sm_l2[2] & rf0_regfile_ue) | (perr_sm_l2[2] & ex7_perr_sm_instr_v); + assign regfile_seq_end = perr_sm_ns[0]; + + // Goto State1 when a parity error is detected. + assign perr_sm_ns[1] = perr_sm_l2[0] & regfile_seq_beg; + + // Goto State2 when both sets of data have been read out + assign perr_sm_ns[2] = perr_sm_l2[1] & ex7_perr_sm_instr_v; + + // set move decision. Both means Uncorrectable Error + assign perr_move_f0_to_f1 = (ex3_f1b_perr & ( (perr_sm_l2[1] & ex3_perr_sm_instr_v))) | + (perr_move_f0_to_f1_l2 & (~(perr_sm_l2[1] & ex3_perr_sm_instr_v))); + + assign perr_move_f1_to_f0 = (ex3_f0c_perr & ( (perr_sm_l2[1] & ex3_perr_sm_instr_v))) | + (perr_move_f1_to_f0_l2 & (~(perr_sm_l2[1] & ex3_perr_sm_instr_v))); + + + assign rf0_perr_move_f0_to_f1 = perr_move_f0_to_f1_l2 & (perr_sm_l2[2] & rf0_perr_sm_instr_v); + assign rf0_perr_move_f1_to_f0 = perr_move_f1_to_f0_l2 & (perr_sm_l2[2] & rf0_perr_sm_instr_v); + assign rf0_perr_fixed_itself = (~(perr_move_f1_to_f0_l2 | perr_move_f0_to_f1_l2)) & (perr_sm_l2[2] & rf0_perr_sm_instr_v); // this is for the case where initially a parity error was detected, but when re-read out of the regfile both copies are correct. We still want to report this. + + assign rf0_perr_force_c = rf0_perr_move_f0_to_f1 & (~rf0_perr_move_f1_to_f0); + + assign xx_ex2_perr_force_c = ex2_perr_force_c; + assign xx_ex2_perr_fsel_ovrd = ex2_perr_sm_instr_v & perr_sm_l2[2]; //cyc // perr_insert + + + assign perr_sm_din[0:2] = (3'b100 & {3{perr_sm_ns[0]}}) | + (3'b010 & {3{perr_sm_ns[1]}}) | + (3'b001 & {3{perr_sm_ns[2]}}) | + (perr_sm_l2 & {3{(~(|(perr_sm_ns[0:2])))}}); + + // Send a dummy instruction down the pipe for reading or writing the regfiles + assign new_perr_sm_instr_v = perr_sm_ns[1] | perr_sm_ns[2]; + + // Save the offending address and tid on any parity error and hold. + assign ex3_capture_addr = ex3_regfile_err_det_any & perr_sm_l2[0] & + (~ex4_regfile_err_det_any) & + (~ex5_regfile_err_det_any) & // need to cover the cycles while waiting for rv to hold_all + (~ex6_regfile_err_det_any) & // safety cycle + (~regfile_seq_beg); + + + assign perr_addr_din[0:5] = ((ex3_f0a_perr & ex3_capture_addr) == 1'b1) ? ex3_instr_fra[0:5] : + ((ex3_f1b_perr & ex3_capture_addr) == 1'b1) ? ex3_instr_frb[0:5] : + ((ex3_f0c_perr & ex3_capture_addr) == 1'b1) ? ex3_instr_frc[0:5] : + ((ex3_f1s_perr & ex3_capture_addr) == 1'b1) ? ex3_instr_frs[0:5] : + perr_addr_l2[0:5]; + + assign perr_tid_din[0:1] = (ex3_fpr_perr[0:1] & {2{ (ex3_capture_addr)}}) | + (perr_tid_l2[0:1] & {2{~(ex3_capture_addr)}}); + + //Mux into the FPR address + // perr_insert + + assign rf0_frc_perr_x_b[0:5] = (~(perr_addr_l2[0:5] & {6{rf0_perr_sm_instr_v}})); + + assign rf0_frc_iu_x_b[0:5] = (~(rf0_instr_frc[0:5] & {6{rf0_perr_sm_instr_v_b}})); + + assign rf0_dcd_frc[0:5] = (~(rf0_frc_perr_x_b[0:5] & rf0_frc_iu_x_b[0:5])); + + + assign rf0_frb_perr_x_b[0:5] = (~(perr_addr_l2[0:5] & {6{rf0_perr_sm_instr_v}})); + + assign rf0_frb_iu_x_b[0:5] = (~(rf0_instr_frb[0:5] & {6{rf0_perr_sm_instr_v_b}})); + + assign rf0_dcd_frb[0:5] = (~(rf0_frb_perr_x_b[0:5] & rf0_frb_iu_x_b[0:5])); + + assign rf0_dcd_fra[0:5] = rf0_instr_fra[0:5]; + + assign rf0_dcd_tid[0:1] = (rf0_tid[0:1] & {2{rf0_perr_sm_instr_v_b}}) | + (perr_tid_l2[0:1] & {2{rf0_perr_sm_instr_v}}); + + + // Determine if we have a ue or ce to report to PC + // state prefixes are for the recirc, not relevant to PC + assign rf0_regfile_ce = (rf0_perr_move_f0_to_f1 | rf0_perr_move_f1_to_f0 | rf0_perr_fixed_itself) & (~(rf0_perr_move_f0_to_f1 & rf0_perr_move_f1_to_f0)); + assign rf0_regfile_ue = rf0_perr_move_f0_to_f1 & rf0_perr_move_f1_to_f0; + + assign err_regfile_parity[0:1] = perr_tid_l2[0:1] & {2{ex0_regfile_ce}}; + assign err_regfile_ue[0:1] = perr_tid_l2[0:1] & {2{ex0_regfile_ue}}; + + + + + generate + if (THREADS == 1) + begin : dcd_err_rpt_thr1 + + tri_direct_err_rpt #(.WIDTH(2)) fu_err_rpt( + .vd(vdd), + .gd(gnd), + .err_in({ err_regfile_parity[0], + err_regfile_ue[0]}), + .err_out({xx_pc_err_regfile_parity[0], + xx_pc_err_regfile_ue[0] }) + ); + + end + endgenerate + + generate + if (THREADS == 2) + begin : dcd_err_rpt_thr2 + + tri_direct_err_rpt #(.WIDTH(4)) fu_err_rpt( + .vd(vdd), + .gd(gnd), + .err_in({ err_regfile_parity[0], + err_regfile_parity[1], + + err_regfile_ue[0], + err_regfile_ue[1] + }), + .err_out({xx_pc_err_regfile_parity[0], + xx_pc_err_regfile_parity[1], + + xx_pc_err_regfile_ue[0], + xx_pc_err_regfile_ue[1] }) + ); + + end + endgenerate + + + + + + + //---------------------------------------------------------------------- + + + assign rv_hold_all_din = ex3_hangcounter_trigger | + ex3_regfile_err_det_any | + ex4_regfile_err_det_any | + ex5_regfile_err_det_any | + ex6_regfile_err_det_any | + regfile_seq_beg | perr_sm_running; + + + tri_rlmreg_p #(.INIT(0), .WIDTH(1)) holdall_lat( + .nclk(nclk), + .act(tihi), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[9]), + .mpw1_b(mpw1_b[9]), + .mpw2_b(mpw2_b[1]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(holdall_si[0:0]), + .scout(holdall_so[0:0]), + + .din(rv_hold_all_din), + //------------------------------------------- + .dout(rv_hold_all_q) + ); + //------------------------------------------- + + + assign xx_rv_hold_all = rv_hold_all_q; + + //------------------------------------------- + + // perr + assign ex2_perr_si[0:23] = {ex2_perr_so[1:23], perr_si}; + assign ex3_perr_si[0:23] = {ex3_perr_so[1:23], ex2_perr_so[0]}; + assign perr_sm_si[0:2] = {perr_sm_so[1:2], ex3_perr_so[0]}; + assign perr_ctl_si[0:30] = {perr_ctl_so[1:30], perr_sm_so[0]}; + assign ex4_ctl_perr_si[0:3] = {ex4_ctl_perr_so[1:3], perr_ctl_so[0]}; + assign holdall_si[0] = {ex4_ctl_perr_so[0]}; + assign exx_regfile_err_det_si[0:8] = {exx_regfile_err_det_so[1:8], holdall_so[0]}; + + assign perr_so = exx_regfile_err_det_so[0]; + + // end perr + + + endmodule diff --git a/dev/verilog/trilib/tri_plat.v b/dev/verilog/trilib/tri_plat.v new file mode 100755 index 0000000..5db3514 --- /dev/null +++ b/dev/verilog/trilib/tri_plat.v @@ -0,0 +1,66 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILENAME : tri_plat.v +// *! DESCRIPTION : Non-scannable pipeline latch +// *!**************************************************************** + +`include "tri_a2o.vh" + +module tri_plat(vd, gd, nclk, flush, din, q); + parameter WIDTH = 1; + parameter OFFSET = 0; + parameter INIT = 0; // will be converted to the least signficant 31 bits of init_v + parameter SYNTHCLONEDLATCH = ""; + + inout vd; + inout gd; + input [0:`NCLK_WIDTH-1] nclk; + input flush; + input [OFFSET:OFFSET+WIDTH-1] din; + output [OFFSET:OFFSET+WIDTH-1] q; + + // tri_plat + reg [OFFSET:OFFSET+WIDTH-1] int_dout; + + (* analysis_not_referenced="true" *) + wire unused; + assign unused = | {vd, gd, nclk[1:`NCLK_WIDTH-1]}; + + + always @ (posedge nclk[0]) + begin + int_dout <= din; + end + + assign q = (flush == 1'b1) ? din : int_dout ; + +endmodule diff --git a/dev/verilog/trilib/tri_pri.v b/dev/verilog/trilib/tri_pri.v new file mode 100755 index 0000000..e0eceb8 --- /dev/null +++ b/dev/verilog/trilib/tri_pri.v @@ -0,0 +1,129 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: Prioritizer +// +//***************************************************************************** + +module tri_pri( + cond, + pri, + or_cond +); + parameter SIZE = 32; // Size of "cond", range 3 - 32 + parameter REV = 0; // 0 = 0 is highest, 1 = 0 is lowest + parameter CMP_ZERO = 0; // 1 = include comparing cond to zero in pri vector, 0 = don't + input [0:SIZE-1] cond; + output [0:SIZE-1+CMP_ZERO] pri; + output or_cond; + + // tri_pri + + parameter s = SIZE - 1; + wire [0:s] l0; + wire [0:s] or_l1; + wire [0:s] or_l2; + wire [0:s] or_l3; + wire [0:s] or_l4; + wire [0:s] or_l5; + + generate + begin + if (REV == 0) + begin + assign l0[0:s] = cond[0:s]; + end + if (REV == 1) + begin + assign l0[0:s] = cond[s:0]; + end + + // Odd Numbered Levels are inverted + + assign or_l1[0] = ~l0[0]; + assign or_l1[1:s] = ~(l0[0:s - 1] | l0[1:s]); + + if (s >= 2) + begin + assign or_l2[0:1] = ~or_l1[0:1]; + assign or_l2[2:s] = ~(or_l1[2:s] & or_l1[0:s - 2]); + end + if (s < 2) + begin + assign or_l2 = ~or_l1; + end + + if (s >= 4) + begin + assign or_l3[0:3] = ~or_l2[0:3]; + assign or_l3[4:s] = ~(or_l2[4:s] | or_l2[0:s - 4]); + end + if (s < 4) + begin + assign or_l3 = ~or_l2; + end + + if (s >= 8) + begin + assign or_l4[0:7] = ~or_l3[0:7]; + assign or_l4[8:s] = ~(or_l3[8:s] & or_l3[0:s - 8]); + end + if (s < 8) + begin + assign or_l4 = ~or_l3; + end + + if (s >= 16) + begin + assign or_l5[0:15] = ~or_l4[0:15]; + assign or_l5[16:s] = ~(or_l4[16:s] | or_l4[0:s - 16]); + end + if (s < 16) + begin + assign or_l5 = ~or_l4; + end + + //assert SIZE > 32 report "Maximum Size of 32 Exceeded!" severity error; + + assign pri[0] = cond[0]; + assign pri[1:s] = cond[1:s] & or_l5[0:s - 1]; + + if (CMP_ZERO == 1) + begin + assign pri[s + 1] = or_l5[s]; + end + + assign or_cond = ~or_l5[s]; + end + endgenerate + +//!! [fail; tri_pri; "Priority not zero or one hot!!"] : (pri1 ) <= not zero_or_one_hot(pri); + +endmodule diff --git a/dev/verilog/trilib/tri_regk.v b/dev/verilog/trilib/tri_regk.v new file mode 100755 index 0000000..b776b29 --- /dev/null +++ b/dev/verilog/trilib/tri_regk.v @@ -0,0 +1,129 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILENAME : tri_regk.v +// *! DESCRIPTION : Multi-bit non-scannable latch, LCB included +// *!**************************************************************** + +`include "tri_a2o.vh" + +module tri_regk( + vd, + gd, + nclk, + act, + force_t, + thold_b, + d_mode, + sg, + delay_lclkr, + mpw1_b, + mpw2_b, + scin, + din, + scout, + dout +); + parameter WIDTH = 4; + parameter OFFSET = 0; //starting bit + parameter INIT = 0; // will be converted to the least signficant + // 31 bits of init_v + parameter SYNTHCLONEDLATCH = ""; + parameter NEEDS_SRESET = 1; // for inferred latches + parameter DOMAIN_CROSSING = 0; + + inout vd; + inout gd; + input [0:`NCLK_WIDTH-1] nclk; + input act; // 1: functional, 0: no clock + input force_t; // 1: force LCB active + input thold_b; // 1: functional, 0: no clock + input d_mode; // 1: disable pulse mode, 0: pulse mode + input sg; // 0: functional, 1: scan + input delay_lclkr; // 0: functional + input mpw1_b; // pulse width control bit + input mpw2_b; // pulse width control bit + input [OFFSET:OFFSET+WIDTH-1] scin; // scan in + input [OFFSET:OFFSET+WIDTH-1] din; // data in + output [OFFSET:OFFSET+WIDTH-1] scout; + output [OFFSET:OFFSET+WIDTH-1] dout; + + parameter [0:WIDTH-1] init_v = INIT; + parameter [0:WIDTH-1] ZEROS = {WIDTH{1'b0}}; + + // tri_regk + + generate + begin + wire sreset; + wire [0:WIDTH-1] int_din; + reg [0:WIDTH-1] int_dout; + wire [0:WIDTH-1] vact; + wire [0:WIDTH-1] vact_b; + wire [0:WIDTH-1] vsreset; + wire [0:WIDTH-1] vsreset_b; + wire [0:WIDTH-1] vthold; + wire [0:WIDTH-1] vthold_b; + (* analysis_not_referenced="true" *) + wire unused; + + if (NEEDS_SRESET == 1) + begin : rst + assign sreset = nclk[1]; + end + if (NEEDS_SRESET != 1) + begin : no_rst + assign sreset = 1'b0; + end + + assign vsreset = {WIDTH{sreset}}; + assign vsreset_b = {WIDTH{~sreset}}; + assign int_din = (vsreset_b & din) | (vsreset & init_v); + + assign vact = {WIDTH{act | force_t}}; + assign vact_b = {WIDTH{~(act | force_t)}}; + + assign vthold_b = {WIDTH{thold_b}}; + assign vthold = {WIDTH{~thold_b}}; + + + always @(posedge nclk[0]) + begin: l + int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout); + end + assign dout = int_dout; + + assign scout = ZEROS; + + assign unused = | {vd, gd, nclk, d_mode, sg, delay_lclkr, mpw1_b, mpw2_b, scin}; + end + endgenerate +endmodule diff --git a/dev/verilog/trilib/tri_regs.v b/dev/verilog/trilib/tri_regs.v new file mode 100755 index 0000000..03286fa --- /dev/null +++ b/dev/verilog/trilib/tri_regs.v @@ -0,0 +1,128 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILENAME : tri_regs.v +// *! DESCRIPTION : Multi-bit scan-only latch, LCB included +// *!**************************************************************** + +`include "tri_a2o.vh" + +module tri_regs( + vd, + gd, + nclk, + force_t, + thold_b, + delay_lclkr, + scin, + scout, + dout +); + parameter WIDTH = 4; + parameter OFFSET = 0; //starting bit + parameter INIT = 0; // will be converted to the least signficant + // 31 bits of init_v + parameter IBUF = 1'b0; //inverted latch IOs, if set to true. + parameter DUALSCAN = ""; // if "S", marks data ports as scan for Moebius + parameter NEEDS_SRESET = 1; // for inferred latches + parameter DOMAIN_CROSSING = 0; + + inout vd; + inout gd; + input [0:`NCLK_WIDTH-1] nclk; + input force_t; // 1: force LCB active + input thold_b; // 1: functional, 0: no clock + input delay_lclkr; // 0: functional + input [OFFSET:OFFSET+WIDTH-1] scin; // scan in + output [OFFSET:OFFSET+WIDTH-1] scout; + output [OFFSET:OFFSET+WIDTH-1] dout; + + parameter [0:WIDTH-1] init_v = INIT; + parameter [0:WIDTH-1] ZEROS = {WIDTH{1'b0}}; + + // tri_regs + + generate + begin + wire sreset; + wire [0:WIDTH-1] int_din; + reg [0:WIDTH-1] int_dout; + wire [0:WIDTH-1] vact; + wire [0:WIDTH-1] vact_b; + wire [0:WIDTH-1] vsreset; + wire [0:WIDTH-1] vsreset_b; + wire [0:WIDTH-1] vthold; + wire [0:WIDTH-1] vthold_b; + (* analysis_not_referenced="true" *) + wire unused; + + if (NEEDS_SRESET == 1) + begin : rst + assign sreset = nclk[1]; + end + if (NEEDS_SRESET != 1) + begin : no_rst + assign sreset = 1'b0; + end + + assign vsreset = {WIDTH{sreset}}; + assign vsreset_b = {WIDTH{~sreset}}; + + assign int_din = (vsreset_b & int_dout) | (vsreset & init_v); + + assign vact = {WIDTH{force_t}}; + assign vact_b = {WIDTH{~force_t}}; + + assign vthold_b = {WIDTH{thold_b}}; + assign vthold = {WIDTH{~thold_b}}; + + + always @(posedge nclk[0]) + begin: l + int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout); + end + + if (IBUF == 1'b1) + begin : cob + assign dout = (~int_dout); + end + + if (IBUF == 1'b0) + begin : cnob + assign dout = int_dout; + end + + assign scout = ZEROS; + + assign unused = | {vd, gd, nclk, delay_lclkr, scin}; + end + endgenerate +endmodule diff --git a/dev/verilog/trilib/tri_rlmlatch_p.v b/dev/verilog/trilib/tri_rlmlatch_p.v new file mode 100755 index 0000000..4628ff8 --- /dev/null +++ b/dev/verilog/trilib/tri_rlmlatch_p.v @@ -0,0 +1,113 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILENAME : tri_rlmlatch_p.v +// *! DESCRIPTION : 1-bit latch, LCB included +// *!**************************************************************** + +`include "tri_a2o.vh" + +module tri_rlmlatch_p(vd, gd, nclk, act, force_t, thold_b, d_mode, sg, delay_lclkr, mpw1_b, mpw2_b, scin, din, scout, dout); + parameter INIT = 0; // will be converted to the least signficant + // 31 bits of init_v + parameter IBUF = 1'b0; //inverted latch IOs, if set to true. + parameter DUALSCAN = ""; // if "S", marks data ports as scan for Moebius + parameter NEEDS_SRESET = 1; // for inferred latches + parameter DOMAIN_CROSSING = 0; + + inout vd; + inout gd; + input [0:`NCLK_WIDTH-1] nclk; + input act; // 1: functional, 0: no clock + input force_t; // 1: force LCB active + input thold_b; // 1: functional, 0: no clock + input d_mode; // 1: disable pulse mode, 0: pulse mode + input sg; // 0: functional, 1: scan + input delay_lclkr; // 0: functional + input mpw1_b; // pulse width control bit + input mpw2_b; // pulse width control bit + input scin; // scan in + input din; // data in + output scout; // scan out + output dout; // data out + + parameter WIDTH = 1; + parameter [0:WIDTH-1] init_v = INIT; + + // tri_rlmlatch_p + + generate + begin + wire sreset; + wire int_din; + reg int_dout; + (* analysis_not_referenced="true" *) + wire unused; + + if (NEEDS_SRESET == 1) + begin : rst + assign sreset = nclk[1]; + end + if (NEEDS_SRESET != 1) + begin : no_rst + assign sreset = 1'b0; + end + + if (IBUF == 1'b1) + begin : cib + assign int_din = ((~sreset) & (~din)) | (sreset & init_v[0]); + end + if (IBUF == 1'b0) + begin : cnib + assign int_din = ((~sreset) & din) | (sreset & init_v[0]); + end + + always @(posedge nclk[0]) + begin: l + int_dout <= ((((act | force_t) & thold_b) | sreset) & int_din) | ((((~act) & (~force_t)) | (~thold_b)) & (~sreset) & int_dout); + end + + if (IBUF == 1'b1) + begin : cob + assign dout = (~int_dout); + end + + if (IBUF == 1'b0) + begin : cnob + assign dout = int_dout; + end + + assign scout = 1'b0; + + assign unused = d_mode | sg | delay_lclkr | mpw1_b | mpw2_b | scin | vd | gd | (|nclk); + end + endgenerate +endmodule diff --git a/dev/verilog/trilib/tri_rlmreg_p.v b/dev/verilog/trilib/tri_rlmreg_p.v new file mode 100755 index 0000000..b9cfc10 --- /dev/null +++ b/dev/verilog/trilib/tri_rlmreg_p.v @@ -0,0 +1,136 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILENAME : tri_rlmreg_p.v +// *! DESCRIPTION : Multi-bit latch, LCB included +// *!**************************************************************** + +`include "tri_a2o.vh" + +module tri_rlmreg_p(vd, gd, nclk, act, force_t, thold_b, d_mode, sg, delay_lclkr, mpw1_b, mpw2_b, scin, din, scout, dout); + parameter WIDTH = 4; + parameter OFFSET = 0; //starting bit + parameter INIT = 0; // will be converted to the least signficant + // 31 bits of init_v + parameter IBUF = 1'b0; //inverted latch IOs, if set to true. + parameter DUALSCAN = ""; // if "S", marks data ports as scan for Moebius + parameter NEEDS_SRESET = 1; // for inferred latches + parameter DOMAIN_CROSSING = 0; + + //wtf trying to fix verilator clock gating bug(?) booting a2o; seeing + parameter ALWAYS_ACT = 0; //wtf 1: override clock gating - can't if truly functional! + + inout vd; + inout gd; + input [0:`NCLK_WIDTH-1] nclk; + input act; // 1: functional, 0: no clock + input force_t; // 1: force LCB active + input thold_b; // 1: functional, 0: no clock + input d_mode; // 1: disable pulse mode, 0: pulse mode + input sg; // 0: functional, 1: scan + input delay_lclkr; // 0: functional + input mpw1_b; // pulse width control bit + input mpw2_b; // pulse width control bit + input [OFFSET:OFFSET+WIDTH-1] scin; // scan in + input [OFFSET:OFFSET+WIDTH-1] din; // data in + output [OFFSET:OFFSET+WIDTH-1] scout; + output [OFFSET:OFFSET+WIDTH-1] dout; + + /* verilator lint_off WIDTH */ + parameter [0:WIDTH-1] init_v = INIT; //wtf causes width mismatch warnings; would have to handle both greater and less than 32 bit cases + /* verilator lint_on WIDTH */ + parameter [0:WIDTH-1] ZEROS = {WIDTH{1'b0}}; + + // tri_rlmreg_p + + generate + begin + wire sreset; + wire [0:WIDTH-1] int_din; + reg [0:WIDTH-1] int_dout; + wire [0:WIDTH-1] vact; + wire [0:WIDTH-1] vact_b; + wire [0:WIDTH-1] vsreset; + wire [0:WIDTH-1] vsreset_b; + wire [0:WIDTH-1] vthold; + wire [0:WIDTH-1] vthold_b; + (* analysis_not_referenced="true" *) + wire [0:WIDTH] unused; + + if (NEEDS_SRESET == 1) + begin : rst + assign sreset = nclk[1]; + end + if (NEEDS_SRESET != 1) + begin : no_rst + assign sreset = 1'b0; + end + + assign vsreset = {WIDTH{sreset}}; + assign vsreset_b = {WIDTH{~sreset}}; + + if (IBUF == 1'b1) + begin : cib + assign int_din = (vsreset_b & (~din)) | (vsreset & init_v); + end + if (IBUF == 1'b0) + begin : cnib + assign int_din = (vsreset_b & din) | (vsreset & init_v); + end + + assign vact = {WIDTH{act | force_t | ALWAYS_ACT == 1}}; + assign vact_b = {WIDTH{~(act | force_t | ALWAYS_ACT == 1)}}; + + assign vthold_b = {WIDTH{thold_b}}; + assign vthold = {WIDTH{~thold_b}}; + + always @(posedge nclk[0]) + begin: l + int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout); + end + + if (IBUF == 1'b1) + begin : cob + assign dout = (~int_dout); + end + + if (IBUF == 1'b0) + begin : cnob + assign dout = int_dout; + end + + assign scout = ZEROS; + + assign unused[0] = d_mode | sg | delay_lclkr | mpw1_b | mpw2_b | vd | gd | (|nclk); + assign unused[1:WIDTH] = scin; + end + endgenerate +endmodule diff --git a/dev/verilog/trilib/tri_rot16_lu.v b/dev/verilog/trilib/tri_rot16_lu.v new file mode 100755 index 0000000..470cbd5 --- /dev/null +++ b/dev/verilog/trilib/tri_rot16_lu.v @@ -0,0 +1,243 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: Unaligned Data Rotate to the Left +// +//***************************************************************************** + +// ########################################################################################## +// Contents +// 1) 16 bit Unaligned Rotate to the Left Rotator +// 2) Little/Big Endian Support +// ########################################################################################## + +module tri_rot16_lu( + rot_sel1, + rot_sel2, + rot_sel3, + rot_data, + data_rot, + vdd, + gnd +); + +// Rotator Controls and Data +input [0:7] rot_sel1; +input [0:7] rot_sel2; +input [0:7] rot_sel3; +input [0:15] rot_data; + +// Rotated Data +output [0:15] data_rot; + +// Pervasive +inout vdd; +inout gnd; + +// tri_rot16_lu + +wire [0:15] mxbele_d0; +wire [0:15] mxbele_d1; +wire [0:15] bele_s0; +wire [0:15] bele_s1; +wire [0:15] mxbele_b; +wire [0:15] mxbele; +wire [0:15] mx1_d0; +wire [0:15] mx1_d1; +wire [0:15] mx1_d2; +wire [0:15] mx1_d3; +wire [0:15] mx2_d0; +wire [0:15] mx2_d1; +wire [0:15] mx2_d2; +wire [0:15] mx2_d3; +wire [0:15] mx1_s0; +wire [0:15] mx1_s1; +wire [0:15] mx1_s2; +wire [0:15] mx1_s3; +wire [0:15] mx2_s0; +wire [0:15] mx2_s1; +wire [0:15] mx2_s2; +wire [0:15] mx2_s3; + +wire [0:15] mx1_0_b; +wire [0:15] mx1_1_b; +wire [0:15] mx1; +wire [0:15] mx2_0_b; +wire [0:15] mx2_1_b; +wire [0:15] mx2; + +(* analysis_not_referenced="true" *) +wire unused; + +assign unused = vdd | gnd; + +// ############################################################################################# +// 16 Byte Rotator +// B0 => data(0:7) B8 => data(64:71) +// B1 => data(8:15) B9 => data(72:79) +// B2 => data(16:23) B10 => data(80:87) +// B3 => data(24:31) B11 => data(88:95) +// B4 => data(32:39) B12 => data(96:103) +// B5 => data(40:47) B13 => data(104:111) +// B6 => data(48:55) B14 => data(112:119) +// B7 => data(56:63) B15 => data(120:127) +// ############################################################################################# + +//-- 0,1,2,3 byte rotation +//with rot_sel(2 to 3) select +// rot3210 <= rot_data(24 to 127) & rot_data(0 to 23) when "11", +// rot_data(16 to 127) & rot_data(0 to 15) when "10", +// rot_data(8 to 127) & rot_data(0 to 7) when "01", +// rot_data(0 to 127) when others; +// +//-- 0-3,4,8,12 byte rotation +//with rot_sel(0 to 1) select +// rotC840 <= rot3210(96 to 127) & rot3210(0 to 95) when "11", +// rot3210(64 to 127) & rot3210(0 to 63) when "10", +// rot3210(32 to 127) & rot3210(0 to 31) when "01", +// rot3210(0 to 127) when others; + +// ---------------------------------------------------------------------------------------- +// Little/Big Endian Muxing +// ---------------------------------------------------------------------------------------- + +assign bele_s0[0:3] = {4{rot_sel1[0]}}; +assign bele_s0[4:7] = {4{rot_sel1[2]}}; +assign bele_s0[8:11] = {4{rot_sel1[4]}}; +assign bele_s0[12:15] = {4{rot_sel1[6]}}; +assign bele_s1[0:3] = {4{rot_sel1[1]}}; +assign bele_s1[4:7] = {4{rot_sel1[3]}}; +assign bele_s1[8:11] = {4{rot_sel1[5]}}; +assign bele_s1[12:15] = {4{rot_sel1[7]}}; + +assign mxbele_d0[0] = rot_data[0]; assign mxbele_d1[0] = rot_data[15]; +assign mxbele_d0[1] = rot_data[1]; assign mxbele_d1[1] = rot_data[14]; +assign mxbele_d0[2] = rot_data[2]; assign mxbele_d1[2] = rot_data[13]; +assign mxbele_d0[3] = rot_data[3]; assign mxbele_d1[3] = rot_data[12]; +assign mxbele_d0[4] = rot_data[4]; assign mxbele_d1[4] = rot_data[11]; +assign mxbele_d0[5] = rot_data[5]; assign mxbele_d1[5] = rot_data[10]; +assign mxbele_d0[6] = rot_data[6]; assign mxbele_d1[6] = rot_data[9]; +assign mxbele_d0[7] = rot_data[7]; assign mxbele_d1[7] = rot_data[8]; +assign mxbele_d0[8] = rot_data[8]; assign mxbele_d1[8] = rot_data[7]; +assign mxbele_d0[9] = rot_data[9]; assign mxbele_d1[9] = rot_data[6]; +assign mxbele_d0[10] = rot_data[10]; assign mxbele_d1[10] = rot_data[5]; +assign mxbele_d0[11] = rot_data[11]; assign mxbele_d1[11] = rot_data[4]; +assign mxbele_d0[12] = rot_data[12]; assign mxbele_d1[12] = rot_data[3]; +assign mxbele_d0[13] = rot_data[13]; assign mxbele_d1[13] = rot_data[2]; +assign mxbele_d0[14] = rot_data[14]; assign mxbele_d1[14] = rot_data[1]; +assign mxbele_d0[15] = rot_data[15]; assign mxbele_d1[15] = rot_data[0]; + +tri_aoi22 #(.WIDTH(16)) mxbele_b_0 (.y(mxbele_b[0:15]), .a0(mxbele_d0[0:15]), .a1(bele_s0[0:15]), .b0(mxbele_d1[0:15]), .b1(bele_s1[0:15])); + +tri_inv #(.WIDTH(16)) mxbele_0 (.y(mxbele[0:15]), .a(mxbele_b[0:15])); + +// ---------------------------------------------------------------------------------------- +// First level of muxing <0,4,8,12 bytes> +// ---------------------------------------------------------------------------------------- + +assign mx1_s0[0:7] = {8{rot_sel2[0]}}; +assign mx1_s1[0:7] = {8{rot_sel2[1]}}; +assign mx1_s2[0:7] = {8{rot_sel2[2]}}; +assign mx1_s3[0:7] = {8{rot_sel2[3]}}; +assign mx1_s0[8:15] = {8{rot_sel2[4]}}; +assign mx1_s1[8:15] = {8{rot_sel2[5]}}; +assign mx1_s2[8:15] = {8{rot_sel2[6]}}; +assign mx1_s3[8:15] = {8{rot_sel2[7]}}; + +assign mx1_d0[0] = mxbele[0]; assign mx1_d1[0] = mxbele[4]; assign mx1_d2[0] = mxbele[8]; assign mx1_d3[0] = mxbele[12]; +assign mx1_d0[1] = mxbele[1]; assign mx1_d1[1] = mxbele[5]; assign mx1_d2[1] = mxbele[9]; assign mx1_d3[1] = mxbele[13]; +assign mx1_d0[2] = mxbele[2]; assign mx1_d1[2] = mxbele[6]; assign mx1_d2[2] = mxbele[10]; assign mx1_d3[2] = mxbele[14]; +assign mx1_d0[3] = mxbele[3]; assign mx1_d1[3] = mxbele[7]; assign mx1_d2[3] = mxbele[11]; assign mx1_d3[3] = mxbele[15]; +assign mx1_d0[4] = mxbele[4]; assign mx1_d1[4] = mxbele[8]; assign mx1_d2[4] = mxbele[12]; assign mx1_d3[4] = mxbele[0]; +assign mx1_d0[5] = mxbele[5]; assign mx1_d1[5] = mxbele[9]; assign mx1_d2[5] = mxbele[13]; assign mx1_d3[5] = mxbele[1]; +assign mx1_d0[6] = mxbele[6]; assign mx1_d1[6] = mxbele[10]; assign mx1_d2[6] = mxbele[14]; assign mx1_d3[6] = mxbele[2]; +assign mx1_d0[7] = mxbele[7]; assign mx1_d1[7] = mxbele[11]; assign mx1_d2[7] = mxbele[15]; assign mx1_d3[7] = mxbele[3]; +assign mx1_d0[8] = mxbele[8]; assign mx1_d1[8] = mxbele[12]; assign mx1_d2[8] = mxbele[0]; assign mx1_d3[8] = mxbele[4]; +assign mx1_d0[9] = mxbele[9]; assign mx1_d1[9] = mxbele[13]; assign mx1_d2[9] = mxbele[1]; assign mx1_d3[9] = mxbele[5]; +assign mx1_d0[10] = mxbele[10]; assign mx1_d1[10] = mxbele[14]; assign mx1_d2[10] = mxbele[2]; assign mx1_d3[10] = mxbele[6]; +assign mx1_d0[11] = mxbele[11]; assign mx1_d1[11] = mxbele[15]; assign mx1_d2[11] = mxbele[3]; assign mx1_d3[11] = mxbele[7]; +assign mx1_d0[12] = mxbele[12]; assign mx1_d1[12] = mxbele[0]; assign mx1_d2[12] = mxbele[4]; assign mx1_d3[12] = mxbele[8]; +assign mx1_d0[13] = mxbele[13]; assign mx1_d1[13] = mxbele[1]; assign mx1_d2[13] = mxbele[5]; assign mx1_d3[13] = mxbele[9]; +assign mx1_d0[14] = mxbele[14]; assign mx1_d1[14] = mxbele[2]; assign mx1_d2[14] = mxbele[6]; assign mx1_d3[14] = mxbele[10]; +assign mx1_d0[15] = mxbele[15]; assign mx1_d1[15] = mxbele[3]; assign mx1_d2[15] = mxbele[7]; assign mx1_d3[15] = mxbele[11]; + +tri_aoi22 #(.WIDTH(16)) mx1_0_b_0 (.y(mx1_0_b[0:15]), .a0(mx1_s0[0:15]), .a1(mx1_d0[0:15]), .b0(mx1_s1[0:15]), .b1(mx1_d1[0:15])); + +tri_aoi22 #(.WIDTH(16)) mx1_1_b_0 (.y(mx1_1_b[0:15]), .a0(mx1_s2[0:15]), .a1(mx1_d2[0:15]), .b0(mx1_s3[0:15]), .b1(mx1_d3[0:15])); + +tri_nand2 #(.WIDTH(16)) mx1_0 (.y(mx1[0:15]), .a(mx1_0_b[0:15]), .b(mx1_1_b[0:15])); + +// ---------------------------------------------------------------------------------------- +// third level of muxing <0,1,2,3 bytes> +// ---------------------------------------------------------------------------------------- + +assign mx2_s0[0:7] = {8{rot_sel3[0]}}; +assign mx2_s1[0:7] = {8{rot_sel3[1]}}; +assign mx2_s2[0:7] = {8{rot_sel3[2]}}; +assign mx2_s3[0:7] = {8{rot_sel3[3]}}; +assign mx2_s0[8:15] = {8{rot_sel3[4]}}; +assign mx2_s1[8:15] = {8{rot_sel3[5]}}; +assign mx2_s2[8:15] = {8{rot_sel3[6]}}; +assign mx2_s3[8:15] = {8{rot_sel3[7]}}; + +assign mx2_d0[0] = mx1[0]; assign mx2_d1[0] = mx1[1]; assign mx2_d2[0] = mx1[2]; assign mx2_d3[0] = mx1[3]; +assign mx2_d0[1] = mx1[1]; assign mx2_d1[1] = mx1[2]; assign mx2_d2[1] = mx1[3]; assign mx2_d3[1] = mx1[4]; +assign mx2_d0[2] = mx1[2]; assign mx2_d1[2] = mx1[3]; assign mx2_d2[2] = mx1[4]; assign mx2_d3[2] = mx1[5]; +assign mx2_d0[3] = mx1[3]; assign mx2_d1[3] = mx1[4]; assign mx2_d2[3] = mx1[5]; assign mx2_d3[3] = mx1[6]; +assign mx2_d0[4] = mx1[4]; assign mx2_d1[4] = mx1[5]; assign mx2_d2[4] = mx1[6]; assign mx2_d3[4] = mx1[7]; +assign mx2_d0[5] = mx1[5]; assign mx2_d1[5] = mx1[6]; assign mx2_d2[5] = mx1[7]; assign mx2_d3[5] = mx1[8]; +assign mx2_d0[6] = mx1[6]; assign mx2_d1[6] = mx1[7]; assign mx2_d2[6] = mx1[8]; assign mx2_d3[6] = mx1[9]; +assign mx2_d0[7] = mx1[7]; assign mx2_d1[7] = mx1[8]; assign mx2_d2[7] = mx1[9]; assign mx2_d3[7] = mx1[10]; +assign mx2_d0[8] = mx1[8]; assign mx2_d1[8] = mx1[9]; assign mx2_d2[8] = mx1[10]; assign mx2_d3[8] = mx1[11]; +assign mx2_d0[9] = mx1[9]; assign mx2_d1[9] = mx1[10]; assign mx2_d2[9] = mx1[11]; assign mx2_d3[9] = mx1[12]; +assign mx2_d0[10] = mx1[10]; assign mx2_d1[10] = mx1[11]; assign mx2_d2[10] = mx1[12]; assign mx2_d3[10] = mx1[13]; +assign mx2_d0[11] = mx1[11]; assign mx2_d1[11] = mx1[12]; assign mx2_d2[11] = mx1[13]; assign mx2_d3[11] = mx1[14]; +assign mx2_d0[12] = mx1[12]; assign mx2_d1[12] = mx1[13]; assign mx2_d2[12] = mx1[14]; assign mx2_d3[12] = mx1[15]; +assign mx2_d0[13] = mx1[13]; assign mx2_d1[13] = mx1[14]; assign mx2_d2[13] = mx1[15]; assign mx2_d3[13] = mx1[0]; +assign mx2_d0[14] = mx1[14]; assign mx2_d1[14] = mx1[15]; assign mx2_d2[14] = mx1[0]; assign mx2_d3[14] = mx1[1]; +assign mx2_d0[15] = mx1[15]; assign mx2_d1[15] = mx1[0]; assign mx2_d2[15] = mx1[1]; assign mx2_d3[15] = mx1[2]; + +tri_aoi22 #(.WIDTH(16)) mx2_0_b_0 (.y(mx2_0_b[0:15]), .a0(mx2_s0[0:15]), .a1(mx2_d0[0:15]), .b0(mx2_s1[0:15]), .b1(mx2_d1[0:15])); + +tri_aoi22 #(.WIDTH(16)) mx2_1_b_0 (.y(mx2_1_b[0:15]), .a0(mx2_s2[0:15]), .a1(mx2_d2[0:15]), .b0(mx2_s3[0:15]), .b1(mx2_d3[0:15])); + +tri_nand2 #(.WIDTH(16)) mx2_0 (.y(mx2[0:15]), .a(mx2_0_b[0:15]), .b(mx2_1_b[0:15])); + +// ############################################################################################# + +// ############################################################################################# +// Outputs +// ############################################################################################# + +assign data_rot = mx2; + +// ############################################################################################# + +endmodule diff --git a/dev/verilog/trilib/tri_rot16_ru.v b/dev/verilog/trilib/tri_rot16_ru.v new file mode 100755 index 0000000..3c316e6 --- /dev/null +++ b/dev/verilog/trilib/tri_rot16_ru.v @@ -0,0 +1,545 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// +// Description: XU LSU Load Data Rotator +//***************************************************************************** + +// ########################################################################################## +// Contents +// 1) 16 bit Unaligned Rotate to the Right Rotator +// 2) Little/Big Endian Support +// ########################################################################################## + +`include "tri_a2o.vh" + +module tri_rot16_ru( + opsize, + le, + le_rotate_sel, + be_rotate_sel, + arr_data, + stq7_byp_val, + stq_byp_val, + stq7_rmw_data, + stq8_rmw_data, + data_latched, + data_rot, + nclk, + vdd, + gnd, + delay_lclkr_dc, + mpw1_dc_b, + mpw2_dc_b, + func_sl_force, + func_sl_thold_0_b, + sg_0, + act, + scan_in, + scan_out +); + +input [0:4] opsize; // (0)16B (1)8B (2)4B (3)2B (4)1B +input le; +input [0:3] le_rotate_sel; +input [0:3] be_rotate_sel; + +input [0:15] arr_data; // data to rotate +input stq7_byp_val; +input stq_byp_val; +input [0:15] stq7_rmw_data; +input [0:15] stq8_rmw_data; +output [0:15] data_latched; // latched data, not rotated + +output [0:15] data_rot; // rotated data out + +(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) +input [0:`NCLK_WIDTH-1] nclk; + +inout vdd; +inout gnd; +input delay_lclkr_dc; +input mpw1_dc_b; +input mpw2_dc_b; +input func_sl_force; +input func_sl_thold_0_b; +input sg_0; +input act; + +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) +input scan_in; +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) +output scan_out; + +// tri_rot16_ru + +wire my_d1clk; +wire my_d2clk; +wire [0:`NCLK_WIDTH-1] my_lclk; + + +wire [0:15] data_latched_b; + +//signal bele_gp0_q_b, bele_gp0_q, bele_gp0_din :std_ulogic_vector(0 to 1); +wire [0:0] bele_gp0_q_b; + +wire [0:0] bele_gp0_q; +wire [0:0] bele_gp0_din; + +wire [0:3] be_shx04_gp0_q_b; + +wire [0:3] be_shx04_gp0_q; +wire [0:3] be_shx04_gp0_din; + +wire [0:3] le_shx04_gp0_q_b; + +wire [0:3] le_shx04_gp0_q; +wire [0:3] le_shx04_gp0_din; + +wire [0:3] be_shx01_gp0_q_b; + +wire [0:3] be_shx01_gp0_q; +wire [0:3] be_shx01_gp0_din; + +wire [0:3] le_shx01_gp0_q_b; + +wire [0:3] le_shx01_gp0_q; +wire [0:3] le_shx01_gp0_din; +wire [0:4] mask_q_b; +wire [0:4] mask_q; +wire [0:4] mask_din; + +wire [0:15] mxbele_b; + +wire [0:15] mxbele; + +wire [0:15] mx1_0_b; + +wire [0:15] mx1_1_b; + +wire [0:15] mx1; + +wire [0:15] mx2_0_b; + +wire [0:15] mx2_1_b; + +wire [0:15] mx2; + +wire [0:15] do_b; +wire [0:15] mxbele_d0; +wire [0:15] mxbele_d1; +wire [0:15] bele_s0; +wire [0:15] bele_s1; +wire [0:3] shx04_gp0_sel_b; +wire [0:3] shx04_gp0_sel; +wire [0:3] shx01_gp0_sel_b; +wire [0:3] shx01_gp0_sel; +wire [0:15] mx1_d0; +wire [0:15] mx1_d1; +wire [0:15] mx1_d2; +wire [0:15] mx1_d3; +wire [0:15] mx2_d0; +wire [0:15] mx2_d1; +wire [0:15] mx2_d2; +wire [0:15] mx2_d3; +wire [0:15] mx1_s0; +wire [0:15] mx1_s1; +wire [0:15] mx1_s2; +wire [0:15] mx1_s3; +wire [0:15] mx2_s0; +wire [0:15] mx2_s1; +wire [0:15] mx2_s2; +wire [0:15] mx2_s3; +wire [0:15] mask_en; +wire [0:3] be_shx04_sel; +wire [0:3] be_shx01_sel; +wire [0:3] le_shx04_sel; +wire [0:3] le_shx01_sel; +wire [0:15] stq_byp_data; +wire [0:15] rotate_data; + +//-------------------------- +// constants +//-------------------------- + +parameter bele_gp0_din_offset = 0; +parameter be_shx04_gp0_din_offset = bele_gp0_din_offset + 1; +parameter le_shx04_gp0_din_offset = be_shx04_gp0_din_offset + 4; +parameter be_shx01_gp0_din_offset = le_shx04_gp0_din_offset + 4; +parameter le_shx01_gp0_din_offset = be_shx01_gp0_din_offset + 4; +parameter mask_din_offset = le_shx01_gp0_din_offset + 4; +parameter scan_right = mask_din_offset + 5 - 1; + +wire [0:scan_right] siv; +wire [0:scan_right] sov; + + +// ############################################################################################# +// Little Endian Rotate Support +// Optype2 Optype4 Optype8 +// B31 => rot_data(248:255) +// B30 => rot_data(240:247) +// B29 => rot_data(232:239) +// B28 => rot_data(224:231) +// B31 => rot_data(248:255) B27 => rot_data(216:223) +// B30 => rot_data(240:247) B26 => rot_data(208:215) +// B15 => rot_data(248:255) B29 => rot_data(232:239) B25 => rot_data(200:207) +// B14 => rot_data(240:247) B28 => rot_data(224:231) B24 => rot_data(192:199) +// +// Optype16 +// B31 => rot_data(248:255) B23 => rot_data(184:191) +// B30 => rot_data(240:247) B22 => rot_data(176:183) +// B29 => rot_data(232:239) B21 => rot_data(168:175) +// B28 => rot_data(224:231) B20 => rot_data(160:167) +// B27 => rot_data(216:223) B19 => rot_data(152:159) +// B26 => rot_data(208:215) B18 => rot_data(144:151) +// B25 => rot_data(200:207) B17 => rot_data(136:143) +// B24 => rot_data(192:199) B16 => rot_data(128:135) +// +// ############################################################################################# + +//-- 0,1,2,3 byte rotation +//with rot_sel(2 to 3) select +// rot3210 <= rot_data(104 to 127) & rot_data(0 to 103) when "11", +// rot_data(112 to 127) & rot_data(0 to 111) when "10", +// rot_data(120 to 127) & rot_data(0 to 119) when "01", +// rot_data(0 to 127) when others; +// +//-- 0-3,4,8,12 byte rotation +//with rot_sel(0 to 1) select +// rotC840 <= rot3210(32 to 127) & rot3210(0 to 31) when "11", +// rot3210(64 to 127) & rot3210(0 to 63) when "10", +// rot3210(96 to 127) & rot3210(0 to 95) when "01", +// rot3210(0 to 127) when others; + +// ###################################################################### +// ## BEFORE ROTATE CYCLE +// ###################################################################### + +// Rotate Control +// ---------------------------------- + +assign be_shx04_sel[0] = (~be_rotate_sel[0]) & (~be_rotate_sel[1]); +assign be_shx04_sel[1] = (~be_rotate_sel[0]) & be_rotate_sel[1]; +assign be_shx04_sel[2] = be_rotate_sel[0] & (~be_rotate_sel[1]); +assign be_shx04_sel[3] = be_rotate_sel[0] & be_rotate_sel[1]; + +assign be_shx01_sel[0] = (~be_rotate_sel[2]) & (~be_rotate_sel[3]); +assign be_shx01_sel[1] = (~be_rotate_sel[2]) & be_rotate_sel[3]; +assign be_shx01_sel[2] = be_rotate_sel[2] & (~be_rotate_sel[3]); +assign be_shx01_sel[3] = be_rotate_sel[2] & be_rotate_sel[3]; + +assign le_shx04_sel[0] = (~le_rotate_sel[0]) & (~le_rotate_sel[1]); +assign le_shx04_sel[1] = (~le_rotate_sel[0]) & le_rotate_sel[1]; +assign le_shx04_sel[2] = le_rotate_sel[0] & (~le_rotate_sel[1]); +assign le_shx04_sel[3] = le_rotate_sel[0] & le_rotate_sel[1]; + +assign le_shx01_sel[0] = (~le_rotate_sel[2]) & (~le_rotate_sel[3]); +assign le_shx01_sel[1] = (~le_rotate_sel[2]) & le_rotate_sel[3]; +assign le_shx01_sel[2] = le_rotate_sel[2] & (~le_rotate_sel[3]); +assign le_shx01_sel[3] = le_rotate_sel[2] & le_rotate_sel[3]; + +// Opsize Mask Generation +// ---------------------------------- +assign mask_din[0] = opsize[0]; // for 16:23 +assign mask_din[1] = opsize[0] | opsize[1]; // for 24:27 +assign mask_din[2] = opsize[0] | opsize[1] | opsize[2]; // for 28:29 +assign mask_din[3] = opsize[0] | opsize[1] | opsize[2] | opsize[3]; // for 30 +assign mask_din[4] = opsize[0] | opsize[1] | opsize[2] | opsize[3] | opsize[4]; // for 31 + +// Latch Inputs +// ---------------------------------- +assign bele_gp0_din[0] = le; +assign be_shx04_gp0_din[0:3] = be_shx04_sel[0:3]; +assign le_shx04_gp0_din[0:3] = le_shx04_sel[0:3]; +assign be_shx01_gp0_din[0:3] = be_shx01_sel[0:3]; +assign le_shx01_gp0_din[0:3] = le_shx01_sel[0:3]; + +// ###################################################################### +// ## BIG-ENDIAN ROTATE CYCLE +// ###################################################################### + +// ------------------------------------------------------------------- +// local latch inputs +// ------------------------------------------------------------------- + +tri_inv bele_gp0_q_0 (.y(bele_gp0_q), .a(bele_gp0_q_b)); + +tri_inv #(.WIDTH(4)) be_shx04_gp0_q_0 (.y(be_shx04_gp0_q[0:3]), .a(be_shx04_gp0_q_b[0:3])); + +tri_inv #(.WIDTH(4)) le_shx04_gp0_q_0 (.y(le_shx04_gp0_q[0:3]), .a(le_shx04_gp0_q_b[0:3])); + +tri_inv #(.WIDTH(4)) be_shx01_gp0_q_0 (.y(be_shx01_gp0_q[0:3]), .a(be_shx01_gp0_q_b[0:3])); + +tri_inv #(.WIDTH(4)) le_shx01_gp0_q_0 (.y(le_shx01_gp0_q[0:3]), .a(le_shx01_gp0_q_b[0:3])); + +assign mask_q[0:4] = (~mask_q_b[0:4]); + +// ---------------------------------------------------------------------------------------- +// Read-Modify-Write Bypass Data Muxing +// ---------------------------------------------------------------------------------------- +assign stq_byp_data = ({16{stq7_byp_val}} & stq7_rmw_data) | ({16{~stq7_byp_val}} & stq8_rmw_data); +assign rotate_data = ({16{stq_byp_val}} & stq_byp_data) | ({16{~stq_byp_val}} & arr_data); + +// ---------------------------------------------------------------------------------------- +// Little/Big Endian Muxing +// ---------------------------------------------------------------------------------------- +assign bele_s0[0:15] = {16{~bele_gp0_q[0]}}; +assign bele_s1[0:15] = {16{ bele_gp0_q[0]}}; + +tri_aoi22 #(.WIDTH(4)) shx04_gp0_sel_b_0 (.y(shx04_gp0_sel_b[0:3]), .a0(be_shx04_gp0_q[0:3]), .a1(bele_s0[0:3]), .b0(le_shx04_gp0_q[0:3]), .b1(bele_s1[0:3])); +tri_aoi22 #(.WIDTH(4)) shx01_gp0_sel_b_0 (.y(shx01_gp0_sel_b[0:3]), .a0(be_shx01_gp0_q[0:3]), .a1(bele_s0[4:7]), .b0(le_shx01_gp0_q[0:3]), .b1(bele_s1[4:7])); + +assign shx04_gp0_sel = (~shx04_gp0_sel_b); +assign shx01_gp0_sel = (~shx01_gp0_sel_b); + +assign mxbele_d0[0] = rotate_data[0]; assign mxbele_d1[0] = rotate_data[15]; +assign mxbele_d0[1] = rotate_data[1]; assign mxbele_d1[1] = rotate_data[14]; +assign mxbele_d0[2] = rotate_data[2]; assign mxbele_d1[2] = rotate_data[13]; +assign mxbele_d0[3] = rotate_data[3]; assign mxbele_d1[3] = rotate_data[12]; +assign mxbele_d0[4] = rotate_data[4]; assign mxbele_d1[4] = rotate_data[11]; +assign mxbele_d0[5] = rotate_data[5]; assign mxbele_d1[5] = rotate_data[10]; +assign mxbele_d0[6] = rotate_data[6]; assign mxbele_d1[6] = rotate_data[9]; +assign mxbele_d0[7] = rotate_data[7]; assign mxbele_d1[7] = rotate_data[8]; +assign mxbele_d0[8] = rotate_data[8]; assign mxbele_d1[8] = rotate_data[7]; +assign mxbele_d0[9] = rotate_data[9]; assign mxbele_d1[9] = rotate_data[6]; +assign mxbele_d0[10] = rotate_data[10]; assign mxbele_d1[10] = rotate_data[5]; +assign mxbele_d0[11] = rotate_data[11]; assign mxbele_d1[11] = rotate_data[4]; +assign mxbele_d0[12] = rotate_data[12]; assign mxbele_d1[12] = rotate_data[3]; +assign mxbele_d0[13] = rotate_data[13]; assign mxbele_d1[13] = rotate_data[2]; +assign mxbele_d0[14] = rotate_data[14]; assign mxbele_d1[14] = rotate_data[1]; +assign mxbele_d0[15] = rotate_data[15]; assign mxbele_d1[15] = rotate_data[0]; + +tri_aoi22 #(.WIDTH(16)) mxbele_b_0 (.y(mxbele_b[0:15]), .a0(mxbele_d0[0:15]), .a1(bele_s0[0:15]), .b0(mxbele_d1[0:15]), .b1(bele_s1[0:15])); + +tri_inv #(.WIDTH(16)) mxbele_0 (.y(mxbele[0:15]), .a(mxbele_b[0:15])); + +// ---------------------------------------------------------------------------------------- +// First level of muxing <0,4,8,12 bytes> +// ---------------------------------------------------------------------------------------- + +assign mx1_s0[0:15] = {16{shx04_gp0_sel[0]}}; +assign mx1_s1[0:15] = {16{shx04_gp0_sel[1]}}; +assign mx1_s2[0:15] = {16{shx04_gp0_sel[2]}}; +assign mx1_s3[0:15] = {16{shx04_gp0_sel[3]}}; + +assign mx1_d0[0] = mxbele[0]; assign mx1_d1[0] = mxbele[12]; assign mx1_d2[0] = mxbele[8]; assign mx1_d3[0] = mxbele[4]; +assign mx1_d0[1] = mxbele[1]; assign mx1_d1[1] = mxbele[13]; assign mx1_d2[1] = mxbele[9]; assign mx1_d3[1] = mxbele[5]; +assign mx1_d0[2] = mxbele[2]; assign mx1_d1[2] = mxbele[14]; assign mx1_d2[2] = mxbele[10]; assign mx1_d3[2] = mxbele[6]; +assign mx1_d0[3] = mxbele[3]; assign mx1_d1[3] = mxbele[15]; assign mx1_d2[3] = mxbele[11]; assign mx1_d3[3] = mxbele[7]; +assign mx1_d0[4] = mxbele[4]; assign mx1_d1[4] = mxbele[0]; assign mx1_d2[4] = mxbele[12]; assign mx1_d3[4] = mxbele[8]; +assign mx1_d0[5] = mxbele[5]; assign mx1_d1[5] = mxbele[1]; assign mx1_d2[5] = mxbele[13]; assign mx1_d3[5] = mxbele[9]; +assign mx1_d0[6] = mxbele[6]; assign mx1_d1[6] = mxbele[2]; assign mx1_d2[6] = mxbele[14]; assign mx1_d3[6] = mxbele[10]; +assign mx1_d0[7] = mxbele[7]; assign mx1_d1[7] = mxbele[3]; assign mx1_d2[7] = mxbele[15]; assign mx1_d3[7] = mxbele[11]; +assign mx1_d0[8] = mxbele[8]; assign mx1_d1[8] = mxbele[4]; assign mx1_d2[8] = mxbele[0]; assign mx1_d3[8] = mxbele[12]; +assign mx1_d0[9] = mxbele[9]; assign mx1_d1[9] = mxbele[5]; assign mx1_d2[9] = mxbele[1]; assign mx1_d3[9] = mxbele[13]; +assign mx1_d0[10] = mxbele[10]; assign mx1_d1[10] = mxbele[6]; assign mx1_d2[10] = mxbele[2]; assign mx1_d3[10] = mxbele[14]; +assign mx1_d0[11] = mxbele[11]; assign mx1_d1[11] = mxbele[7]; assign mx1_d2[11] = mxbele[3]; assign mx1_d3[11] = mxbele[15]; +assign mx1_d0[12] = mxbele[12]; assign mx1_d1[12] = mxbele[8]; assign mx1_d2[12] = mxbele[4]; assign mx1_d3[12] = mxbele[0]; +assign mx1_d0[13] = mxbele[13]; assign mx1_d1[13] = mxbele[9]; assign mx1_d2[13] = mxbele[5]; assign mx1_d3[13] = mxbele[1]; +assign mx1_d0[14] = mxbele[14]; assign mx1_d1[14] = mxbele[10]; assign mx1_d2[14] = mxbele[6]; assign mx1_d3[14] = mxbele[2]; +assign mx1_d0[15] = mxbele[15]; assign mx1_d1[15] = mxbele[11]; assign mx1_d2[15] = mxbele[7]; assign mx1_d3[15] = mxbele[3]; + +tri_aoi22 #(.WIDTH(16)) mx1_0_b_0 (.y(mx1_0_b[0:15]), .a0(mx1_s0[0:15]), .a1(mx1_d0[0:15]), .b0(mx1_s1[0:15]), .b1(mx1_d1[0:15])); + +tri_aoi22 #(.WIDTH(16)) mx1_1_b_0 (.y(mx1_1_b[0:15]), .a0(mx1_s2[0:15]), .a1(mx1_d2[0:15]), .b0(mx1_s3[0:15]), .b1(mx1_d3[0:15])); + +tri_nand2 #(.WIDTH(16)) mx1_0 (.y(mx1[0:15]), .a(mx1_0_b[0:15]), .b(mx1_1_b[0:15])); + +// ---------------------------------------------------------------------------------------- +// third level of muxing <0,1,2,3 bytes> , include mask on selects +// ---------------------------------------------------------------------------------------- + +assign mask_en[0:7] = {8{mask_q[0]}}; // 128 +assign mask_en[8:11] = {4{mask_q[1]}}; // 128,64 +assign mask_en[12:13] = {2{mask_q[2]}}; // 128,64,32 +assign mask_en[14] = mask_q[3]; // 128,64,32,16 +assign mask_en[15] = mask_q[4]; // 128,64,32,16,8 + +assign mx2_s0[0:7] = {8{shx01_gp0_sel[0]}} & mask_en[0:7]; +assign mx2_s1[0:7] = {8{shx01_gp0_sel[1]}} & mask_en[0:7]; +assign mx2_s2[0:7] = {8{shx01_gp0_sel[2]}} & mask_en[0:7]; +assign mx2_s3[0:7] = {8{shx01_gp0_sel[3]}} & mask_en[0:7]; +assign mx2_s0[8:15] = {8{shx01_gp0_sel[0]}} & mask_en[8:15]; +assign mx2_s1[8:15] = {8{shx01_gp0_sel[1]}} & mask_en[8:15]; +assign mx2_s2[8:15] = {8{shx01_gp0_sel[2]}} & mask_en[8:15]; +assign mx2_s3[8:15] = {8{shx01_gp0_sel[3]}} & mask_en[8:15]; + +assign mx2_d0[0] = mx1[0]; assign mx2_d1[0] = mx1[15]; assign mx2_d2[0] = mx1[14]; assign mx2_d3[0] = mx1[13]; +assign mx2_d0[1] = mx1[1]; assign mx2_d1[1] = mx1[0]; assign mx2_d2[1] = mx1[15]; assign mx2_d3[1] = mx1[14]; +assign mx2_d0[2] = mx1[2]; assign mx2_d1[2] = mx1[1]; assign mx2_d2[2] = mx1[0]; assign mx2_d3[2] = mx1[15]; +assign mx2_d0[3] = mx1[3]; assign mx2_d1[3] = mx1[2]; assign mx2_d2[3] = mx1[1]; assign mx2_d3[3] = mx1[0]; +assign mx2_d0[4] = mx1[4]; assign mx2_d1[4] = mx1[3]; assign mx2_d2[4] = mx1[2]; assign mx2_d3[4] = mx1[1]; +assign mx2_d0[5] = mx1[5]; assign mx2_d1[5] = mx1[4]; assign mx2_d2[5] = mx1[3]; assign mx2_d3[5] = mx1[2]; +assign mx2_d0[6] = mx1[6]; assign mx2_d1[6] = mx1[5]; assign mx2_d2[6] = mx1[4]; assign mx2_d3[6] = mx1[3]; +assign mx2_d0[7] = mx1[7]; assign mx2_d1[7] = mx1[6]; assign mx2_d2[7] = mx1[5]; assign mx2_d3[7] = mx1[4]; +assign mx2_d0[8] = mx1[8]; assign mx2_d1[8] = mx1[7]; assign mx2_d2[8] = mx1[6]; assign mx2_d3[8] = mx1[5]; +assign mx2_d0[9] = mx1[9]; assign mx2_d1[9] = mx1[8]; assign mx2_d2[9] = mx1[7]; assign mx2_d3[9] = mx1[6]; +assign mx2_d0[10] = mx1[10]; assign mx2_d1[10] = mx1[9]; assign mx2_d2[10] = mx1[8]; assign mx2_d3[10] = mx1[7]; +assign mx2_d0[11] = mx1[11]; assign mx2_d1[11] = mx1[10]; assign mx2_d2[11] = mx1[9]; assign mx2_d3[11] = mx1[8]; +assign mx2_d0[12] = mx1[12]; assign mx2_d1[12] = mx1[11]; assign mx2_d2[12] = mx1[10]; assign mx2_d3[12] = mx1[9]; +assign mx2_d0[13] = mx1[13]; assign mx2_d1[13] = mx1[12]; assign mx2_d2[13] = mx1[11]; assign mx2_d3[13] = mx1[10]; +assign mx2_d0[14] = mx1[14]; assign mx2_d1[14] = mx1[13]; assign mx2_d2[14] = mx1[12]; assign mx2_d3[14] = mx1[11]; +assign mx2_d0[15] = mx1[15]; assign mx2_d1[15] = mx1[14]; assign mx2_d2[15] = mx1[13]; assign mx2_d3[15] = mx1[12]; + +tri_aoi22 #(.WIDTH(16)) mx2_0_b_0 (.y(mx2_0_b[0:15]), .a0(mx2_s0[0:15]), .a1(mx2_d0[0:15]), .b0(mx2_s1[0:15]), .b1(mx2_d1[0:15])); + +tri_aoi22 #(.WIDTH(16)) mx2_1_b_0 (.y(mx2_1_b[0:15]), .a0(mx2_s2[0:15]), .a1(mx2_d2[0:15]), .b0(mx2_s3[0:15]), .b1(mx2_d3[0:15])); + +tri_nand2 #(.WIDTH(16)) mx2_0 (.y(mx2[0:15]), .a(mx2_0_b[0:15]), .b(mx2_1_b[0:15])); + +tri_inv #(.WIDTH(16)) do_b_0 (.y(do_b[0:15]), .a(mx2[0:15])); + +tri_inv #(.WIDTH(16)) data_rot_0 (.y(data_rot[0:15]), .a(do_b[0:15])); + +tri_inv #(.WIDTH(16)) data_latched_b_0 (.y(data_latched_b), .a(arr_data)); + +tri_inv #(.WIDTH(16)) data_latched_0 (.y(data_latched), .a(data_latched_b)); + +// top funny physical placement to minimize wrap wires ... also nice for LE adjust +//--------- +// 0 31 +// 1 30 +// 2 29 +// 3 28 +// 4 27 +// 5 26 +// 6 25 +// 7 24 +//--------- +// 8 23 +// 9 22 +// 10 21 +// 11 20 +// 12 19 +// 13 18 +// 14 17 +// 15 16 +//--------- +// bot + +// ############################################################### +// ## LCBs +// ############################################################### +tri_lcbnd my_lcb( + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .force_t(func_sl_force), + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(act), + .sg(sg_0), + .thold_b(func_sl_thold_0_b), + .d1clk(my_d1clk), + .d2clk(my_d2clk), + .lclk(my_lclk) +); + +// ############################################################### +// ## Latches +// ############################################################### +tri_inv_nlats #(.WIDTH(1), .INIT(1'b0), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(0)) bele_gp0_lat( + .vd(vdd), + .gd(gnd), + .lclk(my_lclk), + .d1clk(my_d1clk), + .d2clk(my_d2clk), + .scanin(siv[bele_gp0_din_offset:bele_gp0_din_offset + 1 - 1]), + .scanout(sov[bele_gp0_din_offset:bele_gp0_din_offset + 1 - 1]), + .d(bele_gp0_din), + .qb(bele_gp0_q_b) +); + +tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(0)) be_shx04_gp0_lat( + .vd(vdd), + .gd(gnd), + .lclk(my_lclk), + .d1clk(my_d1clk), + .d2clk(my_d2clk), + .scanin(siv[be_shx04_gp0_din_offset:be_shx04_gp0_din_offset + 4 - 1]), + .scanout(sov[be_shx04_gp0_din_offset:be_shx04_gp0_din_offset + 4 - 1]), + .d(be_shx04_gp0_din), + .qb(be_shx04_gp0_q_b[0:3]) +); + +tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(0)) le_shx04_gp0_lat( + .vd(vdd), + .gd(gnd), + .lclk(my_lclk), + .d1clk(my_d1clk), + .d2clk(my_d2clk), + .scanin(siv[le_shx04_gp0_din_offset:le_shx04_gp0_din_offset + 4 - 1]), + .scanout(sov[le_shx04_gp0_din_offset:le_shx04_gp0_din_offset + 4 - 1]), + .d(le_shx04_gp0_din), + .qb(le_shx04_gp0_q_b[0:3]) +); + +tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) be_shx01_gp0_lat( + .vd(vdd), + .gd(gnd), + .lclk(my_lclk), + .d1clk(my_d1clk), + .d2clk(my_d2clk), + .scanin(siv[be_shx01_gp0_din_offset:be_shx01_gp0_din_offset + 4 - 1]), + .scanout(sov[be_shx01_gp0_din_offset:be_shx01_gp0_din_offset + 4 - 1]), + .d(be_shx01_gp0_din), + .qb(be_shx01_gp0_q_b[0:3]) +); + +tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) le_shx01_gp0_lat( + .vd(vdd), + .gd(gnd), + .lclk(my_lclk), + .d1clk(my_d1clk), + .d2clk(my_d2clk), + .scanin(siv[le_shx01_gp0_din_offset:le_shx01_gp0_din_offset + 4 - 1]), + .scanout(sov[le_shx01_gp0_din_offset:le_shx01_gp0_din_offset + 4 - 1]), + .d(le_shx01_gp0_din), + .qb(le_shx01_gp0_q_b[0:3]) +); + +tri_inv_nlats #(.WIDTH(5), .INIT(5'b0), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) mask_lat( + .vd(vdd), + .gd(gnd), + .lclk(my_lclk), + .d1clk(my_d1clk), + .d2clk(my_d2clk), + .scanin(siv[mask_din_offset:mask_din_offset + 5 - 1]), + .scanout(sov[mask_din_offset:mask_din_offset + 5 - 1]), + .d(mask_din), + .qb(mask_q_b[0:4]) +); + +assign siv[0:scan_right] = {sov[1:scan_right], scan_in}; +assign scan_out = sov[0]; + +endmodule diff --git a/dev/verilog/trilib/tri_rot16s_ru.v b/dev/verilog/trilib/tri_rot16s_ru.v new file mode 100755 index 0000000..bb9e90c --- /dev/null +++ b/dev/verilog/trilib/tri_rot16s_ru.v @@ -0,0 +1,753 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// +// Description: XU LSU Load Data Rotator +//***************************************************************************** + +// ########################################################################################## +// Contents +// 1) 16 bit Unaligned Rotate to the Right Rotator +// 2) Algebraic Sign Extension support +// 3) Little/Big Endian Support +// ########################################################################################## + +`include "tri_a2o.vh" + +module tri_rot16s_ru( + opsize, + le, + le_rotate_sel, + be_rotate_sel, + algebraic, + le_algebraic_sel, + be_algebraic_sel, + arr_data, + stq7_byp_val, + stq_byp_val, + stq7_rmw_data, + stq8_rmw_data, + data_latched, + data_rot, + algebraic_bit, + nclk, + vdd, + gnd, + delay_lclkr_dc, + mpw1_dc_b, + mpw2_dc_b, + func_sl_force, + func_sl_thold_0_b, + sg_0, + act, + scan_in, + scan_out +); + +input [0:4] opsize; // (0)16B (1)8B (2)4B (3)2B (4)1B +input le; +input [0:3] le_rotate_sel; +input [0:3] be_rotate_sel; +input algebraic; +input [0:3] le_algebraic_sel; +input [0:3] be_algebraic_sel; + +input [0:15] arr_data; // data to rotate +input stq7_byp_val; +input stq_byp_val; +input [0:15] stq7_rmw_data; +input [0:15] stq8_rmw_data; +output [0:15] data_latched; // latched data, not rotated + +output [0:15] data_rot; // rotated data out + +output [0:5] algebraic_bit; + +(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) +input [0:`NCLK_WIDTH-1] nclk; + +inout vdd; + +inout gnd; +input delay_lclkr_dc; +input mpw1_dc_b; +input mpw2_dc_b; +input func_sl_force; +input func_sl_thold_0_b; +input sg_0; +input act; + +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) +input scan_in; + +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) +output scan_out; + +// tri_rot16s_ru + +wire my_d1clk; +wire my_d2clk; +wire [0:`NCLK_WIDTH-1] my_lclk; + +wire [0:15] data_latched_b; + +wire [0:0] bele_gp0_q_b; + +wire [0:0] bele_gp0_q; +wire [0:0] bele_gp0_din; + +wire [0:3] be_shx04_gp0_q_b; + +wire [0:3] be_shx04_gp0_q; +wire [0:3] be_shx04_gp0_din; + +wire [0:3] le_shx04_gp0_q_b; + +wire [0:3] le_shx04_gp0_q; +wire [0:3] le_shx04_gp0_din; + +wire [0:3] be_shx01_gp0_q_b; + +wire [0:3] be_shx01_gp0_q; +wire [0:3] be_shx01_gp0_din; + +wire [0:3] le_shx01_gp0_q_b; + +wire [0:3] le_shx01_gp0_q; +wire [0:3] le_shx01_gp0_din; +wire [0:4] mask_q_b; +wire [0:4] mask_q; +wire [0:4] mask_din; + +wire [0:3] be_shx04_sgn0_q_b; + +wire [0:3] be_shx04_sgn0_q; +wire [0:3] be_shx04_sgn0_din; + +wire [0:3] le_shx04_sgn0_q_b; + +wire [0:3] le_shx04_sgn0_q; +wire [0:3] le_shx04_sgn0_din; + +wire [0:3] be_shx01_sgn0_q_b; + +wire [0:3] be_shx01_sgn0_q; +wire [0:3] be_shx01_sgn0_din; + +wire [0:3] le_shx01_sgn0_q_b; + +wire [0:3] le_shx01_sgn0_q; +wire [0:3] le_shx01_sgn0_din; + +wire [0:15] mxbele_b; + +wire [0:15] mxbele; + +wire [0:15] mx1_0_b; + +wire [0:15] mx1_1_b; + +wire [0:15] mx1; + +wire [0:15] mx2_0_b; + +wire [0:15] mx2_1_b; + +wire [0:15] mx2; + +wire [0:7] sx1_0_b; + +wire [0:7] sx1_1_b; + +wire [0:7] sx1; + +wire [0:5] sx2_0_b; + +wire [0:5] sx2_1_b; + +wire [0:5] sx2; + +wire [0:15] do_b; + +wire [0:5] sign_copy_b; +wire [0:15] mxbele_d0; +wire [0:15] mxbele_d1; +wire [0:15] bele_s0; +wire [0:15] bele_s1; +wire [0:3] shx04_gp0_sel_b; +wire [0:3] shx04_gp0_sel; +wire [0:3] shx04_sgn0_sel_b; +wire [0:3] shx04_sgn0_sel; +wire [0:3] shx01_gp0_sel_b; +wire [0:3] shx01_gp0_sel; +wire [0:3] shx01_sgn0_sel_b; +wire [0:3] shx01_sgn0_sel; +wire [0:15] mx1_d0; +wire [0:15] mx1_d1; +wire [0:15] mx1_d2; +wire [0:15] mx1_d3; +wire [0:15] mx2_d0; +wire [0:15] mx2_d1; +wire [0:15] mx2_d2; +wire [0:15] mx2_d3; +wire [0:15] mx1_s0; +wire [0:15] mx1_s1; +wire [0:15] mx1_s2; +wire [0:15] mx1_s3; +wire [0:15] mx2_s0; +wire [0:15] mx2_s1; +wire [0:15] mx2_s2; +wire [0:15] mx2_s3; +wire [0:7] sx1_d0; +wire [0:7] sx1_d1; +wire [0:7] sx1_d2; +wire [0:7] sx1_d3; +wire [0:5] sx2_d0; +wire [0:5] sx2_d1; +wire [0:5] sx2_d2; +wire [0:5] sx2_d3; +wire [0:7] sx1_s0; +wire [0:7] sx1_s1; +wire [0:7] sx1_s2; +wire [0:7] sx1_s3; +wire [0:5] sx2_s0; +wire [0:5] sx2_s1; +wire [0:5] sx2_s2; +wire [0:5] sx2_s3; +wire [0:15] mask_en; +wire [0:3] be_shx04_sel; +wire [0:3] be_shx01_sel; +wire [0:3] le_shx04_sel; +wire [0:3] le_shx01_sel; +wire [0:3] be_shx04_sgn; +wire [0:3] be_shx01_sgn; +wire [0:3] le_shx04_sgn; +wire [0:3] le_shx01_sgn; +wire [0:15] stq_byp_data; +wire [0:15] rotate_data; + +//-------------------------- +// constants +//-------------------------- + +parameter bele_gp0_din_offset = 0; +parameter be_shx04_gp0_din_offset = bele_gp0_din_offset + 1; +parameter le_shx04_gp0_din_offset = be_shx04_gp0_din_offset + 4; +parameter be_shx01_gp0_din_offset = le_shx04_gp0_din_offset + 4; +parameter le_shx01_gp0_din_offset = be_shx01_gp0_din_offset + 4; +parameter mask_din_offset = le_shx01_gp0_din_offset + 4; +parameter be_shx04_sgn0_din_offset = mask_din_offset + 5; +parameter be_shx01_sgn0_din_offset = be_shx04_sgn0_din_offset + 4; +parameter le_shx04_sgn0_din_offset = be_shx01_sgn0_din_offset + 4; +parameter le_shx01_sgn0_din_offset = le_shx04_sgn0_din_offset + 4; +parameter scan_right = le_shx01_sgn0_din_offset + 4 - 1; + +wire [0:scan_right] siv; +wire [0:scan_right] sov; + +// ############################################################################################# +// Little Endian Rotate Support +// Optype2 Optype4 Optype8 +// B31 => rot_data(248:255) +// B30 => rot_data(240:247) +// B29 => rot_data(232:239) +// B28 => rot_data(224:231) +// B31 => rot_data(248:255) B27 => rot_data(216:223) +// B30 => rot_data(240:247) B26 => rot_data(208:215) +// B15 => rot_data(248:255) B29 => rot_data(232:239) B25 => rot_data(200:207) +// B14 => rot_data(240:247) B28 => rot_data(224:231) B24 => rot_data(192:199) +// +// Optype16 +// B31 => rot_data(248:255) B23 => rot_data(184:191) +// B30 => rot_data(240:247) B22 => rot_data(176:183) +// B29 => rot_data(232:239) B21 => rot_data(168:175) +// B28 => rot_data(224:231) B20 => rot_data(160:167) +// B27 => rot_data(216:223) B19 => rot_data(152:159) +// B26 => rot_data(208:215) B18 => rot_data(144:151) +// B25 => rot_data(200:207) B17 => rot_data(136:143) +// B24 => rot_data(192:199) B16 => rot_data(128:135) +// +// ############################################################################################# + +//-- 0,1,2,3 byte rotation +//with rot_sel(2 to 3) select +// rot3210 <= rot_data(104 to 127) & rot_data(0 to 103) when "11", +// rot_data(112 to 127) & rot_data(0 to 111) when "10", +// rot_data(120 to 127) & rot_data(0 to 119) when "01", +// rot_data(0 to 127) when others; +// +//-- 0-3,4,8,12 byte rotation +//with rot_sel(0 to 1) select +// rotC840 <= rot3210(32 to 127) & rot3210(0 to 31) when "11", +// rot3210(64 to 127) & rot3210(0 to 63) when "10", +// rot3210(96 to 127) & rot3210(0 to 95) when "01", +// rot3210(0 to 127) when others; + +// ###################################################################### +// ## BEFORE ROTATE CYCLE +// ###################################################################### + +// Rotate Control +// ---------------------------------- + +assign be_shx04_sel[0] = (~be_rotate_sel[0]) & (~be_rotate_sel[1]); +assign be_shx04_sel[1] = (~be_rotate_sel[0]) & be_rotate_sel[1]; +assign be_shx04_sel[2] = be_rotate_sel[0] & (~be_rotate_sel[1]); +assign be_shx04_sel[3] = be_rotate_sel[0] & be_rotate_sel[1]; + +assign be_shx01_sel[0] = (~be_rotate_sel[2]) & (~be_rotate_sel[3]); +assign be_shx01_sel[1] = (~be_rotate_sel[2]) & be_rotate_sel[3]; +assign be_shx01_sel[2] = be_rotate_sel[2] & (~be_rotate_sel[3]); +assign be_shx01_sel[3] = be_rotate_sel[2] & be_rotate_sel[3]; + +assign le_shx04_sel[0] = (~le_rotate_sel[0]) & (~le_rotate_sel[1]); +assign le_shx04_sel[1] = (~le_rotate_sel[0]) & le_rotate_sel[1]; +assign le_shx04_sel[2] = le_rotate_sel[0] & (~le_rotate_sel[1]); +assign le_shx04_sel[3] = le_rotate_sel[0] & le_rotate_sel[1]; + +assign le_shx01_sel[0] = (~le_rotate_sel[2]) & (~le_rotate_sel[3]); +assign le_shx01_sel[1] = (~le_rotate_sel[2]) & le_rotate_sel[3]; +assign le_shx01_sel[2] = le_rotate_sel[2] & (~le_rotate_sel[3]); +assign le_shx01_sel[3] = le_rotate_sel[2] & le_rotate_sel[3]; + +// Algebraic Sign Extension Control +// ---------------------------------- +// come up with amount to pick the sign extend bit hw(0->30), wd(0->28) 1_1110,1_1100 + +assign be_shx04_sgn[0] = (~be_algebraic_sel[0]) & (~be_algebraic_sel[1]); +assign be_shx04_sgn[1] = (~be_algebraic_sel[0]) & be_algebraic_sel[1]; +assign be_shx04_sgn[2] = be_algebraic_sel[0] & (~be_algebraic_sel[1]); +assign be_shx04_sgn[3] = be_algebraic_sel[0] & be_algebraic_sel[1]; +assign le_shx04_sgn[0] = (~le_algebraic_sel[0]) & (~le_algebraic_sel[1]); +assign le_shx04_sgn[1] = (~le_algebraic_sel[0]) & le_algebraic_sel[1]; +assign le_shx04_sgn[2] = le_algebraic_sel[0] & (~le_algebraic_sel[1]); +assign le_shx04_sgn[3] = le_algebraic_sel[0] & le_algebraic_sel[1]; + +assign be_shx01_sgn[0] = (~be_algebraic_sel[2]) & (~be_algebraic_sel[3]) & algebraic; +assign be_shx01_sgn[1] = (~be_algebraic_sel[2]) & be_algebraic_sel[3] & algebraic; +assign be_shx01_sgn[2] = be_algebraic_sel[2] & (~be_algebraic_sel[3]) & algebraic; +assign be_shx01_sgn[3] = be_algebraic_sel[2] & be_algebraic_sel[3] & algebraic; +assign le_shx01_sgn[0] = (~le_algebraic_sel[2]) & (~le_algebraic_sel[3]) & algebraic; +assign le_shx01_sgn[1] = (~le_algebraic_sel[2]) & le_algebraic_sel[3] & algebraic; +assign le_shx01_sgn[2] = le_algebraic_sel[2] & (~le_algebraic_sel[3]) & algebraic; +assign le_shx01_sgn[3] = le_algebraic_sel[2] & le_algebraic_sel[3] & algebraic; + +// Opsize Mask Generation +// ---------------------------------- +assign mask_din[0] = opsize[0]; // for 16:23 +assign mask_din[1] = opsize[0] | opsize[1]; // for 24:27 +assign mask_din[2] = opsize[0] | opsize[1] | opsize[2]; // for 28:29 +assign mask_din[3] = opsize[0] | opsize[1] | opsize[2] | opsize[3]; // for 30 +assign mask_din[4] = opsize[0] | opsize[1] | opsize[2] | opsize[3] | opsize[4]; // for 31 + +// Latch Inputs +// ---------------------------------- +assign bele_gp0_din[0] = le; +assign be_shx04_gp0_din[0:3] = be_shx04_sel[0:3]; +assign le_shx04_gp0_din[0:3] = le_shx04_sel[0:3]; +assign be_shx01_gp0_din[0:3] = be_shx01_sel[0:3]; +assign le_shx01_gp0_din[0:3] = le_shx01_sel[0:3]; +assign be_shx04_sgn0_din[0:3] = be_shx04_sgn[0:3]; +assign be_shx01_sgn0_din[0:3] = be_shx01_sgn[0:3]; +assign le_shx04_sgn0_din[0:3] = le_shx04_sgn[0:3]; +assign le_shx01_sgn0_din[0:3] = le_shx01_sgn[0:3]; + +// ###################################################################### +// ## BIG-ENDIAN ROTATE CYCLE +// ###################################################################### + +// ------------------------------------------------------------------- +// local latch inputs +// ------------------------------------------------------------------- + +tri_inv bele_gp0_q_0 (.y(bele_gp0_q), .a(bele_gp0_q_b)); + +tri_inv #(.WIDTH(4)) be_shx04_gp0_q_0 (.y(be_shx04_gp0_q[0:3]), .a(be_shx04_gp0_q_b[0:3])); + +tri_inv #(.WIDTH(4)) le_shx04_gp0_q_0 (.y(le_shx04_gp0_q[0:3]), .a(le_shx04_gp0_q_b[0:3])); + +tri_inv #(.WIDTH(4)) be_shx01_gp0_q_0 (.y(be_shx01_gp0_q[0:3]), .a(be_shx01_gp0_q_b[0:3])); + +tri_inv #(.WIDTH(4)) le_shx01_gp0_q_0 (.y(le_shx01_gp0_q[0:3]), .a(le_shx01_gp0_q_b[0:3])); + +tri_inv #(.WIDTH(4)) be_shx04_sgn0_q_0 (.y(be_shx04_sgn0_q[0:3]), .a(be_shx04_sgn0_q_b[0:3])); + +tri_inv #(.WIDTH(4)) le_shx04_sgn0_q_0 (.y(le_shx04_sgn0_q[0:3]), .a(le_shx04_sgn0_q_b[0:3])); + +tri_inv #(.WIDTH(4)) be_shx01_sgn0_q_0 (.y(be_shx01_sgn0_q[0:3]), .a(be_shx01_sgn0_q_b[0:3])); + +tri_inv #(.WIDTH(4)) le_shx01_sgn0_q_0 (.y(le_shx01_sgn0_q[0:3]), .a(le_shx01_sgn0_q_b[0:3])); + +assign mask_q[0:4] = (~mask_q_b[0:4]); + +// ---------------------------------------------------------------------------------------- +// Read-Modify-Write Bypass Data Muxing +// ---------------------------------------------------------------------------------------- +assign stq_byp_data = ({16{stq7_byp_val}} & stq7_rmw_data) | ({16{~stq7_byp_val}} & stq8_rmw_data); +assign rotate_data = ({16{stq_byp_val}} & stq_byp_data) | ({16{~stq_byp_val}} & arr_data); + +// ---------------------------------------------------------------------------------------- +// Little/Big Endian Muxing +// ---------------------------------------------------------------------------------------- +assign bele_s0[0:15] = {16{~bele_gp0_q[0]}}; +assign bele_s1[0:15] = {16{ bele_gp0_q[0]}}; + +tri_aoi22 #(.WIDTH(4)) shx04_gp0_sel_b_0 (.y(shx04_gp0_sel_b[0:3]), .a0(be_shx04_gp0_q[0:3]), .a1(bele_s0[0:3]), .b0(le_shx04_gp0_q[0:3]), .b1(bele_s1[0:3])); + +tri_aoi22 #(.WIDTH(4)) shx01_gp0_sel_b_0 (.y(shx01_gp0_sel_b[0:3]), .a0(be_shx01_gp0_q[0:3]), .a1(bele_s0[4:7]), .b0(le_shx01_gp0_q[0:3]), .b1(bele_s1[4:7])); + +tri_aoi22 #(.WIDTH(4)) shx04_sgn0_sel_b_0 (.y(shx04_sgn0_sel_b[0:3]), .a0(be_shx04_sgn0_q[0:3]), .a1(bele_s0[8:11]), .b0(le_shx04_sgn0_q[0:3]), .b1(bele_s1[8:11])); + +tri_aoi22 #(.WIDTH(4)) shx01_sgn0_sel_b_0 (.y(shx01_sgn0_sel_b[0:3]), .a0(be_shx01_sgn0_q[0:3]), .a1(bele_s0[12:15]), .b0(le_shx01_sgn0_q[0:3]), .b1(bele_s1[12:15])); + +assign shx04_gp0_sel = (~shx04_gp0_sel_b); +assign shx01_gp0_sel = (~shx01_gp0_sel_b); +assign shx04_sgn0_sel = (~shx04_sgn0_sel_b); +assign shx01_sgn0_sel = (~shx01_sgn0_sel_b); + +assign mxbele_d0[0] = rotate_data[0]; assign mxbele_d1[0] = rotate_data[15]; +assign mxbele_d0[1] = rotate_data[1]; assign mxbele_d1[1] = rotate_data[14]; +assign mxbele_d0[2] = rotate_data[2]; assign mxbele_d1[2] = rotate_data[13]; +assign mxbele_d0[3] = rotate_data[3]; assign mxbele_d1[3] = rotate_data[12]; +assign mxbele_d0[4] = rotate_data[4]; assign mxbele_d1[4] = rotate_data[11]; +assign mxbele_d0[5] = rotate_data[5]; assign mxbele_d1[5] = rotate_data[10]; +assign mxbele_d0[6] = rotate_data[6]; assign mxbele_d1[6] = rotate_data[9]; +assign mxbele_d0[7] = rotate_data[7]; assign mxbele_d1[7] = rotate_data[8]; +assign mxbele_d0[8] = rotate_data[8]; assign mxbele_d1[8] = rotate_data[7]; +assign mxbele_d0[9] = rotate_data[9]; assign mxbele_d1[9] = rotate_data[6]; +assign mxbele_d0[10] = rotate_data[10]; assign mxbele_d1[10] = rotate_data[5]; +assign mxbele_d0[11] = rotate_data[11]; assign mxbele_d1[11] = rotate_data[4]; +assign mxbele_d0[12] = rotate_data[12]; assign mxbele_d1[12] = rotate_data[3]; +assign mxbele_d0[13] = rotate_data[13]; assign mxbele_d1[13] = rotate_data[2]; +assign mxbele_d0[14] = rotate_data[14]; assign mxbele_d1[14] = rotate_data[1]; +assign mxbele_d0[15] = rotate_data[15]; assign mxbele_d1[15] = rotate_data[0]; + +tri_aoi22 #(.WIDTH(16)) mxbele_b_0 (.y(mxbele_b[0:15]), .a0(mxbele_d0[0:15]), .a1(bele_s0[0:15]), .b0(mxbele_d1[0:15]), .b1(bele_s1[0:15])); + +tri_inv #(.WIDTH(16)) mxbele_0 (.y(mxbele[0:15]), .a(mxbele_b[0:15])); + +// ---------------------------------------------------------------------------------------- +// First level of muxing <0,4,8,12 bytes> +// ---------------------------------------------------------------------------------------- + +assign mx1_s0[0:15] = {16{shx04_gp0_sel[0]}}; +assign mx1_s1[0:15] = {16{shx04_gp0_sel[1]}}; +assign mx1_s2[0:15] = {16{shx04_gp0_sel[2]}}; +assign mx1_s3[0:15] = {16{shx04_gp0_sel[3]}}; + +assign mx1_d0[0] = mxbele[0]; assign mx1_d1[0] = mxbele[12]; assign mx1_d2[0] = mxbele[8]; assign mx1_d3[0] = mxbele[4]; +assign mx1_d0[1] = mxbele[1]; assign mx1_d1[1] = mxbele[13]; assign mx1_d2[1] = mxbele[9]; assign mx1_d3[1] = mxbele[5]; +assign mx1_d0[2] = mxbele[2]; assign mx1_d1[2] = mxbele[14]; assign mx1_d2[2] = mxbele[10]; assign mx1_d3[2] = mxbele[6]; +assign mx1_d0[3] = mxbele[3]; assign mx1_d1[3] = mxbele[15]; assign mx1_d2[3] = mxbele[11]; assign mx1_d3[3] = mxbele[7]; +assign mx1_d0[4] = mxbele[4]; assign mx1_d1[4] = mxbele[0]; assign mx1_d2[4] = mxbele[12]; assign mx1_d3[4] = mxbele[8]; +assign mx1_d0[5] = mxbele[5]; assign mx1_d1[5] = mxbele[1]; assign mx1_d2[5] = mxbele[13]; assign mx1_d3[5] = mxbele[9]; +assign mx1_d0[6] = mxbele[6]; assign mx1_d1[6] = mxbele[2]; assign mx1_d2[6] = mxbele[14]; assign mx1_d3[6] = mxbele[10]; +assign mx1_d0[7] = mxbele[7]; assign mx1_d1[7] = mxbele[3]; assign mx1_d2[7] = mxbele[15]; assign mx1_d3[7] = mxbele[11]; +assign mx1_d0[8] = mxbele[8]; assign mx1_d1[8] = mxbele[4]; assign mx1_d2[8] = mxbele[0]; assign mx1_d3[8] = mxbele[12]; +assign mx1_d0[9] = mxbele[9]; assign mx1_d1[9] = mxbele[5]; assign mx1_d2[9] = mxbele[1]; assign mx1_d3[9] = mxbele[13]; +assign mx1_d0[10] = mxbele[10]; assign mx1_d1[10] = mxbele[6]; assign mx1_d2[10] = mxbele[2]; assign mx1_d3[10] = mxbele[14]; +assign mx1_d0[11] = mxbele[11]; assign mx1_d1[11] = mxbele[7]; assign mx1_d2[11] = mxbele[3]; assign mx1_d3[11] = mxbele[15]; +assign mx1_d0[12] = mxbele[12]; assign mx1_d1[12] = mxbele[8]; assign mx1_d2[12] = mxbele[4]; assign mx1_d3[12] = mxbele[0]; +assign mx1_d0[13] = mxbele[13]; assign mx1_d1[13] = mxbele[9]; assign mx1_d2[13] = mxbele[5]; assign mx1_d3[13] = mxbele[1]; +assign mx1_d0[14] = mxbele[14]; assign mx1_d1[14] = mxbele[10]; assign mx1_d2[14] = mxbele[6]; assign mx1_d3[14] = mxbele[2]; +assign mx1_d0[15] = mxbele[15]; assign mx1_d1[15] = mxbele[11]; assign mx1_d2[15] = mxbele[7]; assign mx1_d3[15] = mxbele[3]; + +tri_aoi22 #(.WIDTH(16)) mx1_0_b_0 (.y(mx1_0_b[0:15]), .a0(mx1_s0[0:15]), .a1(mx1_d0[0:15]), .b0(mx1_s1[0:15]), .b1(mx1_d1[0:15])); + +tri_aoi22 #(.WIDTH(16)) mx1_1_b_0 (.y(mx1_1_b[0:15]), .a0(mx1_s2[0:15]), .a1(mx1_d2[0:15]), .b0(mx1_s3[0:15]), .b1(mx1_d3[0:15])); + +tri_nand2 #(.WIDTH(16)) mx1_0 (.y(mx1[0:15]), .a(mx1_0_b[0:15]), .b(mx1_1_b[0:15])); + +assign sx1_s0[0:7] = {8{shx04_sgn0_sel[0]}}; +assign sx1_s1[0:7] = {8{shx04_sgn0_sel[1]}}; +assign sx1_s2[0:7] = {8{shx04_sgn0_sel[2]}}; +assign sx1_s3[0:7] = {8{shx04_sgn0_sel[3]}}; + +assign sx1_d0[0] = rotate_data[0]; assign sx1_d1[0] = rotate_data[4]; assign sx1_d2[0] = rotate_data[8]; assign sx1_d3[0] = rotate_data[12]; +assign sx1_d0[1] = rotate_data[1]; assign sx1_d1[1] = rotate_data[5]; assign sx1_d2[1] = rotate_data[9]; assign sx1_d3[1] = rotate_data[13]; +assign sx1_d0[2] = rotate_data[2]; assign sx1_d1[2] = rotate_data[6]; assign sx1_d2[2] = rotate_data[10]; assign sx1_d3[2] = rotate_data[14]; +assign sx1_d0[3] = rotate_data[3]; assign sx1_d1[3] = rotate_data[7]; assign sx1_d2[3] = rotate_data[11]; assign sx1_d3[3] = rotate_data[15]; +assign sx1_d0[4] = rotate_data[0]; assign sx1_d1[4] = rotate_data[4]; assign sx1_d2[4] = rotate_data[8]; assign sx1_d3[4] = rotate_data[12]; +assign sx1_d0[5] = rotate_data[1]; assign sx1_d1[5] = rotate_data[5]; assign sx1_d2[5] = rotate_data[9]; assign sx1_d3[5] = rotate_data[13]; +assign sx1_d0[6] = rotate_data[2]; assign sx1_d1[6] = rotate_data[6]; assign sx1_d2[6] = rotate_data[10]; assign sx1_d3[6] = rotate_data[14]; +assign sx1_d0[7] = rotate_data[3]; assign sx1_d1[7] = rotate_data[7]; assign sx1_d2[7] = rotate_data[11]; assign sx1_d3[7] = rotate_data[15]; + +tri_aoi22 #(.WIDTH(8)) sx1_0_b_0 (.y(sx1_0_b[0:7]), .a0(sx1_s0[0:7]), .a1(sx1_d0[0:7]), .b0(sx1_s1[0:7]), .b1(sx1_d1[0:7])); + +tri_aoi22 #(.WIDTH(8)) sx1_1_b_0 (.y(sx1_1_b[0:7]), .a0(sx1_s2[0:7]), .a1(sx1_d2[0:7]), .b0(sx1_s3[0:7]), .b1(sx1_d3[0:7])); + +tri_nand2 #(.WIDTH(8)) sx1_0 (.y(sx1[0:7]), .a(sx1_0_b[0:7]), .b(sx1_1_b[0:7])); + +// ---------------------------------------------------------------------------------------- +// third level of muxing <0,1,2,3 bytes> , include mask on selects +// ---------------------------------------------------------------------------------------- + +assign mask_en[0:7] = {8{mask_q[0]}}; // 128 +assign mask_en[8:11] = {4{mask_q[1]}}; // 128,64 +assign mask_en[12:13] = {2{mask_q[2]}}; // 128,64,32 +assign mask_en[14] = mask_q[3]; // 128,64,32,16 +assign mask_en[15] = mask_q[4]; // 128,64,32,16,8 + +assign mx2_s0[0:7] = {8{shx01_gp0_sel[0]}} & mask_en[0:7]; +assign mx2_s1[0:7] = {8{shx01_gp0_sel[1]}} & mask_en[0:7]; +assign mx2_s2[0:7] = {8{shx01_gp0_sel[2]}} & mask_en[0:7]; +assign mx2_s3[0:7] = {8{shx01_gp0_sel[3]}} & mask_en[0:7]; +assign mx2_s0[8:15] = {8{shx01_gp0_sel[0]}} & mask_en[8:15]; +assign mx2_s1[8:15] = {8{shx01_gp0_sel[1]}} & mask_en[8:15]; +assign mx2_s2[8:15] = {8{shx01_gp0_sel[2]}} & mask_en[8:15]; +assign mx2_s3[8:15] = {8{shx01_gp0_sel[3]}} & mask_en[8:15]; + +assign mx2_d0[0] = mx1[0]; assign mx2_d1[0] = mx1[15]; assign mx2_d2[0] = mx1[14]; assign mx2_d3[0] = mx1[13]; +assign mx2_d0[1] = mx1[1]; assign mx2_d1[1] = mx1[0]; assign mx2_d2[1] = mx1[15]; assign mx2_d3[1] = mx1[14]; +assign mx2_d0[2] = mx1[2]; assign mx2_d1[2] = mx1[1]; assign mx2_d2[2] = mx1[0]; assign mx2_d3[2] = mx1[15]; +assign mx2_d0[3] = mx1[3]; assign mx2_d1[3] = mx1[2]; assign mx2_d2[3] = mx1[1]; assign mx2_d3[3] = mx1[0]; +assign mx2_d0[4] = mx1[4]; assign mx2_d1[4] = mx1[3]; assign mx2_d2[4] = mx1[2]; assign mx2_d3[4] = mx1[1]; +assign mx2_d0[5] = mx1[5]; assign mx2_d1[5] = mx1[4]; assign mx2_d2[5] = mx1[3]; assign mx2_d3[5] = mx1[2]; +assign mx2_d0[6] = mx1[6]; assign mx2_d1[6] = mx1[5]; assign mx2_d2[6] = mx1[4]; assign mx2_d3[6] = mx1[3]; +assign mx2_d0[7] = mx1[7]; assign mx2_d1[7] = mx1[6]; assign mx2_d2[7] = mx1[5]; assign mx2_d3[7] = mx1[4]; +assign mx2_d0[8] = mx1[8]; assign mx2_d1[8] = mx1[7]; assign mx2_d2[8] = mx1[6]; assign mx2_d3[8] = mx1[5]; +assign mx2_d0[9] = mx1[9]; assign mx2_d1[9] = mx1[8]; assign mx2_d2[9] = mx1[7]; assign mx2_d3[9] = mx1[6]; +assign mx2_d0[10] = mx1[10]; assign mx2_d1[10] = mx1[9]; assign mx2_d2[10] = mx1[8]; assign mx2_d3[10] = mx1[7]; +assign mx2_d0[11] = mx1[11]; assign mx2_d1[11] = mx1[10]; assign mx2_d2[11] = mx1[9]; assign mx2_d3[11] = mx1[8]; +assign mx2_d0[12] = mx1[12]; assign mx2_d1[12] = mx1[11]; assign mx2_d2[12] = mx1[10]; assign mx2_d3[12] = mx1[9]; +assign mx2_d0[13] = mx1[13]; assign mx2_d1[13] = mx1[12]; assign mx2_d2[13] = mx1[11]; assign mx2_d3[13] = mx1[10]; +assign mx2_d0[14] = mx1[14]; assign mx2_d1[14] = mx1[13]; assign mx2_d2[14] = mx1[12]; assign mx2_d3[14] = mx1[11]; +assign mx2_d0[15] = mx1[15]; assign mx2_d1[15] = mx1[14]; assign mx2_d2[15] = mx1[13]; assign mx2_d3[15] = mx1[12]; + +tri_aoi22 #(.WIDTH(16)) mx2_0_b_0 (.y(mx2_0_b[0:15]), .a0(mx2_s0[0:15]), .a1(mx2_d0[0:15]), .b0(mx2_s1[0:15]), .b1(mx2_d1[0:15])); + +tri_aoi22 #(.WIDTH(16)) mx2_1_b_0 (.y(mx2_1_b[0:15]), .a0(mx2_s2[0:15]), .a1(mx2_d2[0:15]), .b0(mx2_s3[0:15]), .b1(mx2_d3[0:15])); + +tri_nand2 #(.WIDTH(16)) mx2_0 (.y(mx2[0:15]), .a(mx2_0_b[0:15]), .b(mx2_1_b[0:15])); + +tri_inv #(.WIDTH(16)) do_b_0 (.y(do_b[0:15]), .a(mx2[0:15])); + +tri_inv #(.WIDTH(16)) data_rot_0 (.y(data_rot[0:15]), .a(do_b[0:15])); + +tri_inv #(.WIDTH(16)) data_latched_b_0 (.y(data_latched_b), .a(arr_data)); + +tri_inv #(.WIDTH(16)) data_latched_0 (.y(data_latched), .a(data_latched_b)); + +assign sx2_s0[0:3] = {4{shx01_sgn0_sel[0]}}; +assign sx2_s1[0:3] = {4{shx01_sgn0_sel[1]}}; +assign sx2_s2[0:3] = {4{shx01_sgn0_sel[2]}}; +assign sx2_s3[0:3] = {4{shx01_sgn0_sel[3]}}; + +assign sx2_s0[4:5] = {2{shx01_sgn0_sel[0] & (~mask_q[2])}}; +assign sx2_s1[4:5] = {2{shx01_sgn0_sel[1] & (~mask_q[2])}}; +assign sx2_s2[4:5] = {2{shx01_sgn0_sel[2] & (~mask_q[2])}}; +assign sx2_s3[4:5] = {2{shx01_sgn0_sel[3] & (~mask_q[2])}}; + +// 6 logically identical copies (1 per byte needing extension) +assign sx2_d0[0] = sx1[0]; assign sx2_d1[0] = sx1[1]; assign sx2_d2[0] = sx1[2]; assign sx2_d3[0] = sx1[3]; +assign sx2_d0[1] = sx1[0]; assign sx2_d1[1] = sx1[1]; assign sx2_d2[1] = sx1[2]; assign sx2_d3[1] = sx1[3]; +assign sx2_d0[2] = sx1[0]; assign sx2_d1[2] = sx1[1]; assign sx2_d2[2] = sx1[2]; assign sx2_d3[2] = sx1[3]; +assign sx2_d0[3] = sx1[4]; assign sx2_d1[3] = sx1[5]; assign sx2_d2[3] = sx1[6]; assign sx2_d3[3] = sx1[7]; +assign sx2_d0[4] = sx1[4]; assign sx2_d1[4] = sx1[5]; assign sx2_d2[4] = sx1[6]; assign sx2_d3[4] = sx1[7]; +assign sx2_d0[5] = sx1[4]; assign sx2_d1[5] = sx1[5]; assign sx2_d2[5] = sx1[6]; assign sx2_d3[5] = sx1[7]; + +tri_aoi22 #(.WIDTH(6)) sx2_0_b_0 (.y(sx2_0_b[0:5]), .a0(sx2_s0[0:5]), .a1(sx2_d0[0:5]), .b0(sx2_s1[0:5]), .b1(sx2_d1[0:5])); + +tri_aoi22 #(.WIDTH(6)) sx2_1_b_0 (.y(sx2_1_b[0:5]), .a0(sx2_s2[0:5]), .a1(sx2_d2[0:5]), .b0(sx2_s3[0:5]), .b1(sx2_d3[0:5])); + +tri_nand2 #(.WIDTH(6)) sx2_0 (.y(sx2[0:5]), .a(sx2_0_b[0:5]), .b(sx2_1_b[0:5])); + +tri_inv #(.WIDTH(6)) sign_copy_b_0 (.y(sign_copy_b[0:5]), .a(sx2[0:5])); + +tri_inv #(.WIDTH(6)) algebraic_bit_0 (.y(algebraic_bit[0:5]), .a(sign_copy_b[0:5])); + +// top funny physical placement to minimize wrap wires ... also nice for LE adjust +//--------- +// 0 31 +// 1 30 +// 2 29 +// 3 28 +// 4 27 +// 5 26 +// 6 25 +// 7 24 +//--------- +// 8 23 +// 9 22 +// 10 21 +// 11 20 +// 12 19 +// 13 18 +// 14 17 +// 15 16 +//--------- +// bot + +// ############################################################### +// ## LCBs +// ############################################################### +tri_lcbnd my_lcb( + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .force_t(func_sl_force), + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(act), + .sg(sg_0), + .thold_b(func_sl_thold_0_b), + .d1clk(my_d1clk), + .d2clk(my_d2clk), + .lclk(my_lclk) +); + +// ############################################################### +// ## Latches +// ############################################################### +tri_inv_nlats #(.WIDTH(1), .INIT(1'b0), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(0)) bele_gp0_lat( + .vd(vdd), + .gd(gnd), + .lclk(my_lclk), + .d1clk(my_d1clk), + .d2clk(my_d2clk), + .scanin(siv[bele_gp0_din_offset:bele_gp0_din_offset + 1 - 1]), + .scanout(sov[bele_gp0_din_offset:bele_gp0_din_offset + 1 - 1]), + .d(bele_gp0_din), + .qb(bele_gp0_q_b) +); + +tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(0)) be_shx04_gp0_lat( + .vd(vdd), + .gd(gnd), + .lclk(my_lclk), + .d1clk(my_d1clk), + .d2clk(my_d2clk), + .scanin(siv[be_shx04_gp0_din_offset:be_shx04_gp0_din_offset + 4 - 1]), + .scanout(sov[be_shx04_gp0_din_offset:be_shx04_gp0_din_offset + 4 - 1]), + .d(be_shx04_gp0_din), + .qb(be_shx04_gp0_q_b[0:3]) +); + +tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(0)) le_shx04_gp0_lat( + .vd(vdd), + .gd(gnd), + .lclk(my_lclk), + .d1clk(my_d1clk), + .d2clk(my_d2clk), + .scanin(siv[le_shx04_gp0_din_offset:le_shx04_gp0_din_offset + 4 - 1]), + .scanout(sov[le_shx04_gp0_din_offset:le_shx04_gp0_din_offset + 4 - 1]), + .d(le_shx04_gp0_din), + .qb(le_shx04_gp0_q_b[0:3]) +); + +tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) be_shx01_gp0_lat( + .vd(vdd), + .gd(gnd), + .lclk(my_lclk), + .d1clk(my_d1clk), + .d2clk(my_d2clk), + .scanin(siv[be_shx01_gp0_din_offset:be_shx01_gp0_din_offset + 4 - 1]), + .scanout(sov[be_shx01_gp0_din_offset:be_shx01_gp0_din_offset + 4 - 1]), + .d(be_shx01_gp0_din), + .qb(be_shx01_gp0_q_b[0:3]) +); + +tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) le_shx01_gp0_lat( + .vd(vdd), + .gd(gnd), + .lclk(my_lclk), + .d1clk(my_d1clk), + .d2clk(my_d2clk), + .scanin(siv[le_shx01_gp0_din_offset:le_shx01_gp0_din_offset + 4 - 1]), + .scanout(sov[le_shx01_gp0_din_offset:le_shx01_gp0_din_offset + 4 - 1]), + .d(le_shx01_gp0_din), + .qb(le_shx01_gp0_q_b[0:3]) +); + +tri_inv_nlats #(.WIDTH(5), .INIT(5'b0), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) mask_lat( + .vd(vdd), + .gd(gnd), + .lclk(my_lclk), + .d1clk(my_d1clk), + .d2clk(my_d2clk), + .scanin(siv[mask_din_offset:mask_din_offset + 5 - 1]), + .scanout(sov[mask_din_offset:mask_din_offset + 5 - 1]), + .d(mask_din), + .qb(mask_q_b[0:4]) +); + +tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(0)) be_shx04_sgn0_lat( + .vd(vdd), + .gd(gnd), + .lclk(my_lclk), + .d1clk(my_d1clk), + .d2clk(my_d2clk), + .scanin(siv[be_shx04_sgn0_din_offset:be_shx04_sgn0_din_offset + 4 - 1]), + .scanout(sov[be_shx04_sgn0_din_offset:be_shx04_sgn0_din_offset + 4 - 1]), + .d(be_shx04_sgn0_din), + .qb(be_shx04_sgn0_q_b) +); + +tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) be_shx01_sgn0_lat( + .vd(vdd), + .gd(gnd), + .lclk(my_lclk), + .d1clk(my_d1clk), + .d2clk(my_d2clk), + .scanin(siv[be_shx01_sgn0_din_offset:be_shx01_sgn0_din_offset + 4 - 1]), + .scanout(sov[be_shx01_sgn0_din_offset:be_shx01_sgn0_din_offset + 4 - 1]), + .d(be_shx01_sgn0_din), + .qb(be_shx01_sgn0_q_b) +); + +tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(0)) le_shx04_sgn0_lat( + .vd(vdd), + .gd(gnd), + .lclk(my_lclk), + .d1clk(my_d1clk), + .d2clk(my_d2clk), + .scanin(siv[le_shx04_sgn0_din_offset:le_shx04_sgn0_din_offset + 4 - 1]), + .scanout(sov[le_shx04_sgn0_din_offset:le_shx04_sgn0_din_offset + 4 - 1]), + .d(le_shx04_sgn0_din), + .qb(le_shx04_sgn0_q_b) +); + +tri_inv_nlats #(.WIDTH(4), .INIT(4'h0), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) le_shx01_sgn0_lat( + .vd(vdd), + .gd(gnd), + .lclk(my_lclk), + .d1clk(my_d1clk), + .d2clk(my_d2clk), + .scanin(siv[le_shx01_sgn0_din_offset:le_shx01_sgn0_din_offset + 4 - 1]), + .scanout(sov[le_shx01_sgn0_din_offset:le_shx01_sgn0_din_offset + 4 - 1]), + .d(le_shx01_sgn0_din), + .qb(le_shx01_sgn0_q_b) +); + +assign siv[0:scan_right] = {sov[1:scan_right], scan_in}; +assign scan_out = sov[0]; + +endmodule diff --git a/dev/verilog/trilib/tri_scom_addr_decode.v b/dev/verilog/trilib/tri_scom_addr_decode.v new file mode 100755 index 0000000..cc7084c --- /dev/null +++ b/dev/verilog/trilib/tri_scom_addr_decode.v @@ -0,0 +1,107 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +// *!**************************************************************** +// *! FILENAME : tri_scom_addr_decode.vhdl +// *! TITLE : +// *! DESCRIPTION : Generic SCOM address decoder +// *!**************************************************************** + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" + +module tri_scom_addr_decode( + sc_addr, + scaddr_dec, + sc_req, + sc_r_nw, + scaddr_nvld, + sc_wr_nvld, + sc_rd_nvld, + vd, + gd +); + +//===================================================================== +// I/O and Signal Declarations +//===================================================================== + parameter ADDR_SIZE = 64; + parameter SATID_NOBITS = 5; // should not be set by user + +// Set the USE_ADDR, ADDR_IS_RDABLE, ADDR_IS_WRABLE vectors to generate a SCOM address +// HEX >>>>> "0000000000000000111111111111111122222222222222223333333333333333" +// ADDR >>>>> "0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF0123456789ABCDEF" +// +// DEC >>>>> "0000000000111111111122222222223333333333444444444455555555556666" +// ADDR >>>>> "0123456789012345678901234567890123456789012345678901234567890123" + parameter [0:ADDR_SIZE-1] USE_ADDR = 64'b1000000000000000000000000000000000000000000000000000000000000000; + parameter [0:ADDR_SIZE-1] ADDR_IS_RDABLE = 64'b1000000000000000000000000000000000000000000000000000000000000000; + parameter [0:ADDR_SIZE-1] ADDR_IS_WRABLE = 64'b1000000000000000000000000000000000000000000000000000000000000000; + + input [0:11-SATID_NOBITS-1] sc_addr; // binary coded scom address + output [0:ADDR_SIZE-1] scaddr_dec; // one hot coded scom address; not latched + + input sc_req; // scom request + input sc_r_nw; // read / not write bit + output scaddr_nvld; // scom address not valid; not latched + output sc_wr_nvld; // scom write not allowed; not latched + output sc_rd_nvld; // scom read not allowed; not latched + + inout vd; + inout gd; + + + +//===================================================================== + wire [0:ADDR_SIZE-1] address; + + +// Don't reference unused inputs: +(* analysis_not_referenced="true" *) + wire unused; + assign unused = vd | gd; + + +//===================================================================== + generate + begin : decode_it + genvar i; + for (i=0; i parallel => serial state machine + // + always @(state_lt or got_head or gor_eofwdata or got_eofwpar or got_ulhead or sent_rdata or + p0_err or any_ack_error or match or do_write or do_read or cch_lt[0] or dch_lt or + sc_ack or wpar_err or read_nvld) + + begin: fsm_transition + next_state = state_lt; + + case (state_lt) + IDLE : + if (dch_lt == 1'b1) + next_state = REC_HEAD; + + REC_HEAD : + if ((got_head) == 1'b1) + next_state = CHECK_BEFORE; + + CHECK_BEFORE : + if (match == 1'b0) + next_state = NOT_SELECTED; + else if (((read_nvld | p0_err) & do_read) == 1'b1) + next_state = FILLER0; + else if (((~p0_err) & (~read_nvld) & do_read) == 1'b1) + next_state = EXE_CMD; + else + next_state = REC_WDATA; + + REC_WDATA : + if (gor_eofwdata == 1'b1) + next_state = REC_WPAR; + + REC_WPAR : + if ((got_eofwpar & (~p0_err)) == 1'b1) + // next_state = EXE_CMD; + next_state = CHECK_WPAR; + else if ((got_eofwpar & p0_err) == 1'b1) + next_state = FILLER0; + + CHECK_WPAR : + if (wpar_err == 1'b0) + next_state = EXE_CMD; + else + next_state = FILLER1; + + EXE_CMD : + if (sc_ack == 1'b1) + next_state = FILLER1; + + FILLER0 : + next_state = FILLER1; + + FILLER1 : + next_state = GEN_ULINFO; + + GEN_ULINFO : + next_state = SEND_ULINFO; + + SEND_ULINFO : + if ((got_ulhead & (do_write | (do_read & any_ack_error))) == 1'b1) + next_state = SEND_0; + else if ((got_ulhead & do_read & (~any_ack_error)) == 1'b1) + next_state = SEND_RDATA; + + SEND_RDATA : + if (sent_rdata == 1'b1) + next_state = SEND_0; + + SEND_0 : + next_state = SEND_1; + + SEND_1 : + next_state = IDLE; + + NOT_SELECTED : + if (cch_lt[0] == 1'b0) + next_state = IDLE; + + default : + next_state = IDLE; + endcase + end + + assign state_in = (local_act == 1'b0) ? state_lt : + (reset == 1'b1) ? IDLE : + next_state; + + assign state_par_error = (^state_lt); + + //----------------------------------------------------------------------------- + assign is_idle = (state_lt == IDLE); + assign is_rec_head = (state_lt == REC_HEAD); + assign is_check_before = (state_lt == CHECK_BEFORE); + assign is_rec_wdata = (state_lt == REC_WDATA); + assign is_rec_wpar = (state_lt == REC_WPAR); + assign is_exe_cmd = (state_lt == EXE_CMD); + assign is_gen_ulinfo = (state_lt == GEN_ULINFO); + assign is_send_ulinfo = (state_lt == SEND_ULINFO); + assign is_send_rdata = (state_lt == SEND_RDATA); + assign is_send_0 = (state_lt == SEND_0); + assign is_send_1 = (state_lt == SEND_1); + assign is_filler_0 = (state_lt == FILLER0); + assign is_filler_1 = (state_lt == FILLER1); + + //----------------------------------------------------------------------------- + assign cnt_in = ((is_idle | is_gen_ulinfo) == 1'b1) ? 7'b0000000 : + ((is_rec_head | is_check_before | is_rec_wdata | + is_rec_wpar | is_send_ulinfo | is_send_rdata | + is_send_0 | is_send_1) == 1'b1) ? cnt_lt + 7'b0000001 : + cnt_lt; + + // downlink head (command) has been received when start bit, satellite id and register id have been received + assign got_head = ({{32-CNT_SIZE{1'b0}},cnt_lt} == (1 + SATID_NOBITS + REGID_NOBITS)); + + // uplink head (response) has been received when start bit, satellite id, register id and 4 ack bits have been received + assign got_ulhead = ({{32-CNT_SIZE{1'b0}},cnt_lt} == (1 + SATID_NOBITS + REGID_NOBITS + 4)); + + assign gor_eofwdata = ({{32-CNT_SIZE{1'b0}},cnt_lt} == EOF_WDATA); + assign got_eofwpar = ({{32-CNT_SIZE{1'b0}},cnt_lt} == EOF_WPAR); + + // for sent_rdata: 1 start, 10 sat_id + reg, 4 ack, 1 p, 64 data = 84, but count from 0 is 1st bit => 83 is end + assign sent_rdata = (cnt_lt == 7'd83); + + assign cntgtheadpluswidth = ({{32-CNT_SIZE{1'b0}},cnt_lt} > EOF_WDATA_N); + assign cntgteofwdataplusparity = ({{32-CNT_SIZE{1'b0}},cnt_lt} > EOF_WPAR_M); + + assign do_send_par = ({{32-CNT_SIZE{1'b0}},cnt_lt} > 79); // 78 bits=15 ulhead + 64 data + + //----------------------------------------------------------------------------- + // shift downlink command (for this or any subsequent satellite) or uplink response (from previous satellite) + assign head_in[HEAD_WIDTH-2:HEAD_WIDTH-1] = ((is_rec_head | (is_idle & dch_lt)) == 1'b1) ? {head_lt[HEAD_WIDTH-1], dch_lt} : + head_lt[HEAD_WIDTH-2:HEAD_WIDTH-1]; + + assign head_in[0:SATID_REGID_NOBITS] = ((is_rec_head | is_send_ulinfo) == 1'b1) ? {head_lt[1:SATID_REGID_NOBITS], head_mux} : + head_lt[0:SATID_REGID_NOBITS]; + + assign head_mux = (is_rec_head == 1'b1) ? head_lt[RW_BIT_INDEX] : + tail_lt[0]; + + // calculate parity P0 of uplink frame + assign tail_in[4] = (is_gen_ulinfo == 1'b1 & (INTERNAL_ADDR_DECODE == 1'b0)) ? (^({parity_satid_regaddr, tail_lt[0], (wpar_err & do_write), sc_ack_info_lt[0:1]})) : + (is_gen_ulinfo == 1'b1 & (INTERNAL_ADDR_DECODE == 1'b1)) ? (^({parity_satid_regaddr, tail_lt[0], (wpar_err & do_write), (write_nvld | read_nvld), addr_nvld})) : + tail_lt[4]; + + // copy sampled ack_info coming from logic + assign tail_in[2:3] = (is_gen_ulinfo == 1'b1 & INTERNAL_ADDR_DECODE == 1'b0) ? sc_ack_info_lt[0:1] : + (is_gen_ulinfo == 1'b1 & INTERNAL_ADDR_DECODE == 1'b1) ? {(write_nvld | read_nvld), addr_nvld} : + (is_send_ulinfo == 1'b1) ? tail_lt[3:4] : // shift out + tail_lt[2:3]; + + // Write Data Parity error + assign tail_in[1] = (is_gen_ulinfo == 1'b1) ? (wpar_err & do_write) : // parity error on write operation + (is_send_ulinfo == 1'b1) ? tail_lt[2] : // shift out + tail_lt[1]; + + // parity check of of downlink P0 yields error + assign tail_in[0] = (is_check_before == 1'b1) ? (~p0_err) : // set to '1' if a downlink parity error is detected by satellite, otherwise '0' + (is_send_ulinfo == 1'b1) ? tail_lt[1] : // shift out + tail_lt[0]; + + // sample and hold ack_info, one spare bit + assign sc_ack_info_in = ((is_exe_cmd & sc_ack) == 1'b1) ? sc_ack_info : + (is_idle == 1'b1) ? 2'b00 : + sc_ack_info_lt; + + //----------------------------------------------------------------------------- + assign do_write = (~do_read); + assign do_read = head_lt[RW_BIT_INDEX]; + assign match = (head_lt[1:SATID_NOBITS] == sat_id_net); + + // if downlink parity error then set p0_err + assign p0_err = (is_check_before & (^(head_lt[1:PARBIT_INDEX]))); + // why constant 11 here: ??? + // first part sat id; second part reg address (curr. 6 bits) => 10 instead of 11 + // now new constant SATID_REGID_NOBITS + assign parity_satid_regaddr = (^{sat_id_net, head_lt[SATID_NOBITS+1:SATID_REGID_NOBITS]}); + + assign any_ack_error = (|sc_ack_info_lt); + + //----------------------------------------------------------------------------- + assign data_mux = ((is_check_before | is_rec_wdata) == 1'b1) ? dch_lt : 1'b0; + + assign data_shifter_in = ((is_check_before | (is_rec_wdata & (~cntgtheadpluswidth)) | is_send_rdata) == 1'b1) ? {data_shifter_lt[1:WIDTH-1], data_mux} : + ((is_exe_cmd & sc_ack & do_read) == 1'b1) ? sc_rdata : + data_shifter_lt; + + //----------------------------------------------------------------------------- + // parity handling + assign par_mux = ((is_rec_wpar) == 1'b1) ? dch_lt : 1'b0; + + // receiving parity: shift when receiving write data parity + // sending parity of read data: shift when sending read data parity + // latch generated parity of read data when read data is accepted + assign datapar_shifter_in = (((is_rec_wpar & (~cntgteofwdataplusparity)) | (is_send_rdata & do_send_par)) == 1'b1) ? {datapar_shifter_lt[1:PAR_NOBITS-1], par_mux} : + ((is_filler_1 == 1'b1)) ? sc_rparity : + datapar_shifter_lt; + + //---------------------------------------------------------------------------- + assign data_shifter_lt_tmp[0:WIDTH-1] = data_shifter_lt; + + generate + if (WIDTH < 64) + begin : data_shifter_padding + assign data_shifter_lt_tmp[WIDTH:63] = {64-WIDTH {1'b0}}; + end + endgenerate + + generate + begin : xhdl0 + genvar i; + for (i=0; i<=PAR_NOBITS-1; i=i+1) + begin : wdata_par_check + assign par_data_in[i] = (^data_shifter_lt_tmp[16*i:16*(i+1)-1]); + end + end + endgenerate + + generate + if (PIPELINE_PARITYCHK == 1'b1) + begin : wdata_par_check_pipe + tri_nlat_scan #(.WIDTH(PAR_NOBITS), .NEEDS_SRESET(1)) state( + .d1clk(d1clk), + .vd(vdd), + .gd(gnd), + .lclk(lclk), + .d2clk(d2clk), + .scan_in(func_scan_in[ STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+22:STATE_WIDTH+WIDTH+(2*PAR_NOBITS)+HEAD_WIDTH+21]), + .scan_out(func_scan_out[STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+22:STATE_WIDTH+WIDTH+(2*PAR_NOBITS)+HEAD_WIDTH+21]), + .din(par_data_in), + .q(par_data_lt) + ); + end + endgenerate + + generate + if (PIPELINE_PARITYCHK == 1'b0) + begin : wdata_par_check_nopipe + assign par_data_lt = par_data_in; + assign func_scan_out[STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+22:STATE_WIDTH+WIDTH+(2*PAR_NOBITS)+HEAD_WIDTH+21] = + func_scan_in[ STATE_WIDTH+WIDTH+PAR_NOBITS+HEAD_WIDTH+22:STATE_WIDTH+WIDTH+(2*PAR_NOBITS)+HEAD_WIDTH+21]; + end + endgenerate + + assign wpar_err = (^{par_data_lt, datapar_shifter_lt}); + + //----------------------------------------------------------------------------- + generate + begin : xhdl1 + genvar i; + for (i=0; i<=PAR_NOBITS-1; i=i+1) + begin : rdata_parity_gen + assign sc_rparity[i] = (^data_shifter_lt_tmp[16*i:16*(i+1)-1]); + end + end + endgenerate + //----------------------------------------------------------------------------- + + //----------------------------------------------------------------- + // address decoding section + // Generate onehot Address (binary to one-hot) + //----------------------------------------------------------------- + //----------------------------------------------------------------------------- + generate + if (INTERNAL_ADDR_DECODE == 1'b1) + begin : internal_addr_decoding + //----------------------------------------------------------------------------- + genvar i; + for (i=0; iex1_spr_msr_cm ,act=>ex1_mul_val + wire ex3_spr_msr_cm_q; //input=>ex2_spr_msr_cm_q ,act=>ex2_mul_val_q + wire ex4_spr_msr_cm_q; //input=>ex3_spr_msr_cm_q ,act=>ex3_act + wire ex5_spr_msr_cm_q; //input=>ex4_spr_msr_cm_q ,act=>ex4_act + wire ex2_mul_is_ord_q; //input=>dec_mul_ex1_mul_ord ,act=>ex1_mul_val + wire ex3_mul_is_ord_q; //input=>ex2_mul_is_ord_q ,act=>ex2_mul_val_q + wire ex4_mul_is_ord_q; //input=>ex3_mul_is_ord_q ,act=>ex3_act + wire ex5_mul_is_ord_q; //input=>ex4_mul_is_ord_q ,act=>ex4_act + wire [0:9] ex3_xer_src_q; //input=>byp_mul_ex2_xer + wire [0:9] ex4_xer_src_q; //input=>ex3_xer_src_q + wire [0:9] ex5_xer_src_q; //input=>ex4_xer_src_q + wire [0:9] ex6_xer_src_q; //input=>ex5_xer_src_q + wire ex2_mul_val_q; // Valid multiply op + wire [0:3] ex3_mulstage_d; // Stage of multiplication + wire [0:3] ex4_mulstage_d; + wire [0:3] ex5_mulstage_d; + wire [0:3] ex6_mulstage_d; + wire [0:3] ex3_mulstage_q; // Stage of multiplication + wire [0:3] ex4_mulstage_q; + wire [0:3] ex5_mulstage_q; + wire [0:3] ex6_mulstage_q; + wire ex2_is_recform_q; // Multiply is a record form + wire ex3_is_recform_q; + wire ex4_is_recform_q; + wire ex5_is_recform_q; + wire ex6_is_recform_q; + wire [0:2] ex2_retsel_q; // Select which data to return + wire [0:2] ex2_retsel_d; + wire [0:2] ex3_retsel_q; + wire [0:2] ex4_retsel_q; + wire [0:2] ex5_retsel_q; + wire [3:8] exx_mul_abort_d; + wire [3:8] exx_mul_abort_q; + wire ex2_mul_size_q; + wire ex2_mul_sign_q; + wire ex4_mul_done_q; // Multiply result is done + wire ex4_mul_done_d; + wire ex5_mul_done_q; + wire ex2_xer_ov_update_q; // Update XER[OV] + wire ex3_xer_ov_update_q; + wire ex4_xer_ov_update_q; + wire ex5_xer_ov_update_q; + wire ex6_xer_ov_update_q; + wire ex3_bs_lo_sign_q; // Sign of operands + wire ex3_bs_lo_sign_d; + wire ex3_bd_lo_sign_q; + wire ex3_bd_lo_sign_d; + wire ex5_ci_q; + wire ex5_ci_d; + wire [0:63] ex6_res_q; + wire ex6_all0_q; // Check different pieces of result for ovf/cr + wire ex6_all1_q; + wire ex6_all0_lo_q; + wire ex6_all0_hi_q; + wire ex6_all1_hi_q; + wire carry_32_dly1_q; // Delayed carry bit for adder + wire all0_lo_dly1_q; // Delay low all 0 + wire all0_lo_dly2_q; + wire all0_lo_dly3_q; + wire [0:31] rslt_lo_q; // Result holding latches + wire [0:31] rslt_lo_d; + wire [0:31] rslt_lo_dly_q; // delay low half of result for mulldo + wire [0:31] rslt_lo_dly_d; + wire [0:63] ex3_mulsrc_0_q; // act=>ex2_mulsrc0_act + wire [0:63] ex2_mulsrc_0; + wire [0:63] ex3_mulsrc_1_q; // act=>ex2_mulsrc1_act + wire [0:63] ex2_mulsrc_1; + wire [0:7] ex6_rslt_hw_q; + wire [0:7] ex6_rslt_hw_d; + wire [0:7] ex6_rslt_ld_li_q; + wire [0:7] ex6_rslt_ld_li_d; + wire [0:7] ex6_rslt_ldo_q; + wire [0:7] ex6_rslt_ldo_d; + wire [0:7] ex6_rslt_lw_hd_q; + wire [0:7] ex6_rslt_lw_hd_d; + wire ex6_cmp0_sel_reshi_q; + wire ex6_cmp0_sel_reshi_d; + wire ex6_cmp0_sel_reslo_q; + wire ex6_cmp0_sel_reslo_d; + wire ex6_cmp0_sel_reslodly_q; + wire ex6_cmp0_sel_reslodly_d; + wire ex6_cmp0_sel_reslodly2_q; + wire ex6_cmp0_sel_reslodly2_d; + wire ex6_eq_sel_all0_b_q; + wire ex6_eq_sel_all0_b_d; + wire ex6_eq_sel_all0_hi_b_q; + wire ex6_eq_sel_all0_hi_b_d; + wire ex6_eq_sel_all0_lo_b_q; + wire ex6_eq_sel_all0_lo_b_d; + wire ex6_eq_sel_all0_lo1_b_q; + wire ex6_eq_sel_all0_lo1_b_d; + wire ex6_eq_sel_all0_lo2_b_q; + wire ex6_eq_sel_all0_lo2_b_d; + wire ex6_eq_sel_all0_lo3_b_q; + wire ex6_eq_sel_all0_lo3_b_d; + wire ex6_ret_mullw_q; + wire ex6_ret_mulldo_q; + wire ex6_cmp0_undef_q; + wire ex6_cmp0_undef_d; + wire [0:`THREADS-1] cp_flush_q; //input=>cp_flush + wire [0:`THREADS-1] ex2_mul_tid_q; //input=>dec_mul_ex1_mul_val + wire [0:`THREADS-1] ex3_mul_tid_q; //input=>ex2_mul_tid_q ,act=>ex2_mul_val_q + wire [0:`THREADS-1] ex4_mul_tid_q; // input=>ex3_mul_tid_q ,act=>ex3_act + wire [0:`THREADS-1] ex5_mul_tid_q; // input=>ex4_mul_tid_q ,act=>ex4_act + wire rslt_lo_act_q; //input=>rslt_lo_act ,act=>1 + // Scanchain + localparam ex2_spr_msr_cm_offset = 1; + localparam ex3_spr_msr_cm_offset = ex2_spr_msr_cm_offset + 1; + localparam ex4_spr_msr_cm_offset = ex3_spr_msr_cm_offset + 1; + localparam ex5_spr_msr_cm_offset = ex4_spr_msr_cm_offset + 1; + localparam ex2_mul_is_ord_offset = ex5_spr_msr_cm_offset + 1; + localparam ex3_mul_is_ord_offset = ex2_mul_is_ord_offset + 1; + localparam ex4_mul_is_ord_offset = ex3_mul_is_ord_offset + 1; + localparam ex5_mul_is_ord_offset = ex4_mul_is_ord_offset + 1; + localparam ex3_xer_src_offset = ex5_mul_is_ord_offset + 1; + localparam ex4_xer_src_offset = ex3_xer_src_offset + 10; + localparam ex5_xer_src_offset = ex4_xer_src_offset + 10; + localparam ex6_xer_src_offset = ex5_xer_src_offset + 10; + localparam ex2_mul_val_offset = ex6_xer_src_offset + 10; + localparam ex3_mulstage_offset = ex2_mul_val_offset + 1; + localparam ex4_mulstage_offset = ex3_mulstage_offset + 4; + localparam ex5_mulstage_offset = ex4_mulstage_offset + 4; + localparam ex6_mulstage_offset = ex5_mulstage_offset + 4; + localparam ex2_retsel_offset = ex6_mulstage_offset + 4; + localparam ex3_retsel_offset = ex2_retsel_offset + 3; + localparam ex4_retsel_offset = ex3_retsel_offset + 3; + localparam ex5_retsel_offset = ex4_retsel_offset + 3; + localparam exx_mul_abort_offset = ex4_retsel_offset + 3; + localparam ex4_mul_done_offset = exx_mul_abort_offset + 6; + localparam ex5_mul_done_offset = ex4_mul_done_offset + 1; + localparam ex2_is_recform_offset = ex5_mul_done_offset + 1; + localparam ex3_is_recform_offset = ex2_is_recform_offset + 1; + localparam ex4_is_recform_offset = ex3_is_recform_offset + 1; + localparam ex5_is_recform_offset = ex4_is_recform_offset + 1; + localparam ex6_is_recform_offset = ex5_is_recform_offset + 1; + localparam ex2_xer_ov_update_offset = ex6_is_recform_offset + 1; + localparam ex3_xer_ov_update_offset = ex2_xer_ov_update_offset + 1; + localparam ex4_xer_ov_update_offset = ex3_xer_ov_update_offset + 1; + localparam ex5_xer_ov_update_offset = ex4_xer_ov_update_offset + 1; + localparam ex6_xer_ov_update_offset = ex5_xer_ov_update_offset + 1; + localparam ex2_mul_size_offset = ex6_xer_ov_update_offset + 1; + localparam ex2_mul_sign_offset = ex2_mul_size_offset + 1; + localparam ex3_bs_lo_sign_offset = ex2_mul_sign_offset + 1; + localparam ex3_bd_lo_sign_offset = ex3_bs_lo_sign_offset + 1; + localparam ex6_all0_offset = ex3_bd_lo_sign_offset + 1; + localparam ex6_all1_offset = ex6_all0_offset + 1; + localparam ex6_all0_lo_offset = ex6_all1_offset + 1; + localparam ex6_all0_hi_offset = ex6_all0_lo_offset + 1; + localparam ex6_all1_hi_offset = ex6_all0_hi_offset + 1; + localparam ex5_ci_offset = ex6_all1_hi_offset + 1; + localparam ex6_res_offset = ex5_ci_offset + 1; + localparam carry_32_dly1_offset = ex6_res_offset + 64; + localparam all0_lo_dly1_offset = carry_32_dly1_offset + 1; + localparam all0_lo_dly2_offset = all0_lo_dly1_offset + 1; + localparam all0_lo_dly3_offset = all0_lo_dly2_offset + 1; + localparam rslt_lo_offset = all0_lo_dly3_offset + 1; + localparam rslt_lo_dly_offset = rslt_lo_offset + 32; + localparam ex3_mulsrc_0_offset = rslt_lo_dly_offset + 32; + localparam ex3_mulsrc_1_offset = ex3_mulsrc_0_offset + 64; + localparam ex6_rslt_hw_offset = ex3_mulsrc_1_offset + 64; + localparam ex6_rslt_ld_li_offset = ex6_rslt_hw_offset + 8; + localparam ex6_rslt_ldo_offset = ex6_rslt_ld_li_offset + 8; + localparam ex6_rslt_lw_hd_offset = ex6_rslt_ldo_offset + 8; + localparam ex6_cmp0_sel_reshi_offset = ex6_rslt_lw_hd_offset + 8; + localparam ex6_cmp0_sel_reslo_offset = ex6_cmp0_sel_reshi_offset + 1; + localparam ex6_cmp0_sel_reslodly_offset = ex6_cmp0_sel_reslo_offset + 1; + localparam ex6_cmp0_sel_reslodly2_offset = ex6_cmp0_sel_reslodly_offset + 1; + localparam ex6_eq_sel_all0_b_offset = ex6_cmp0_sel_reslodly2_offset + 1; + localparam ex6_eq_sel_all0_hi_b_offset = ex6_eq_sel_all0_b_offset + 1; + localparam ex6_eq_sel_all0_lo_b_offset = ex6_eq_sel_all0_hi_b_offset + 1; + localparam ex6_eq_sel_all0_lo1_b_offset = ex6_eq_sel_all0_lo_b_offset + 1; + localparam ex6_eq_sel_all0_lo2_b_offset = ex6_eq_sel_all0_lo1_b_offset + 1; + localparam ex6_eq_sel_all0_lo3_b_offset = ex6_eq_sel_all0_lo2_b_offset + 1; + localparam ex6_ret_mullw_offset = ex6_eq_sel_all0_lo3_b_offset + 1; + localparam ex6_ret_mulldo_offset = ex6_ret_mullw_offset + 1; + localparam ex6_cmp0_undef_offset = ex6_ret_mulldo_offset + 1; + localparam cp_flush_offset = ex6_cmp0_undef_offset + 1; + localparam ex2_mul_tid_offset = cp_flush_offset + `THREADS; + localparam ex3_mul_tid_offset = ex2_mul_tid_offset + `THREADS; + localparam ex4_mul_tid_offset = ex3_mul_tid_offset + `THREADS; + localparam ex5_mul_tid_offset = ex4_mul_tid_offset + `THREADS; + localparam rslt_lo_act_offset = ex5_mul_tid_offset + `THREADS; + localparam scan_right = rslt_lo_act_offset + 1; + wire [0:scan_right-1] siv; + wire [0:scan_right-1] sov; + + //------------------------------------------------------------------- + // Other signals + //------------------------------------------------------------------- + assign ex2_retsel_d = {dec_mul_ex1_mul_ret, dec_mul_ex1_mul_size, dec_mul_ex1_mul_imm}; + + //------------------------------------------------------------------- + // Multiply Stage Counter + //------------------------------------------------------------------- + generate + if (`GPR_WIDTH == 64) + begin : mult_64b_stagecnt + assign ex2_mulstage_shift = {1'b0,ex3_mulstage_q[0:2]}; + end + endgenerate + generate + if (`GPR_WIDTH == 32) + begin : mult_32b_stagecnt + assign ex2_mulstage_shift = 4'b0000; + end + endgenerate + + assign ex1_mul_val = | dec_mul_ex1_mul_val; + + assign ex2_mulstage = (ex2_mul_val_q == 1'b1) ? 4'b1000 : ex2_mulstage_shift; + + wire ex2_flush = |(ex2_mul_tid_q & cp_flush_q); + wire ex3_flush = |(ex3_mul_tid_q & cp_flush_q); + wire ex4_flush = |(ex4_mul_tid_q & cp_flush_q); + wire ex5_flush = |(ex5_mul_tid_q & cp_flush_q); + + assign ex3_mulstage_d = ex2_mulstage & ~{4{ex2_flush}}; + assign ex4_mulstage_d = ex3_mulstage_q & ~{4{ex3_flush}}; + assign ex5_mulstage_d = ex4_mulstage_q & ~{4{ex4_flush}}; + assign ex6_mulstage_d = ex5_mulstage_q & ~{4{ex5_flush}}; + + assign mul_spr_running = ex5_mul_tid_q & {`THREADS{|ex5_mulstage_q}}; + + assign exx_mul_abort_d[3] = byp_mul_ex2_abort; + assign exx_mul_abort_d[4] = exx_mul_abort_q[3]; + assign exx_mul_abort_d[5] = exx_mul_abort_q[4]; + assign exx_mul_abort_d[6] = exx_mul_abort_q[5]; + assign exx_mul_abort_d[7] = exx_mul_abort_q[6]; + assign exx_mul_abort_d[8] = exx_mul_abort_q[7]; + + assign mul_byp_ex5_abort = (exx_mul_abort_q[5] & (ex5_ret_mulhw | ex5_ret_mullw)) | + (exx_mul_abort_q[6] & (ex5_ret_mulli)) | + (exx_mul_abort_q[7] & (ex5_ret_mulld)) | + (exx_mul_abort_q[8] & (ex5_ret_mulldo | ex5_ret_mulhd)) ; + + + //---------------------------------------------------------------------------------------------------------------------------------------- + //---------------------------------------------------------------------------------------------------------------------------------------- + // NEW MULTIPLIER ------------------------------------------------------------------------------------------------------------------------ + //---------------------------------------------------------------------------------------------------------------------------------------- + //---------------------------------------------------------------------------------------------------------------------------------------- + + //------------------------------------------------------------------- + // Signs + //------------------------------------------------------------------- + + // Signs (zero out for unsigned) + // with ex2_mulstage select + // ex2_bs_sign <= byp_mul_ex2_rs1(32) when "1000", + // byp_mul_ex2_rs1( 0) when "0100", + // byp_mul_ex2_rs1(32) when "0010", + // byp_mul_ex2_rs1( 0) when "0001", + // '0' when others; + // + // with ex2_mulstage select + // ex2_bd_sign <= byp_mul_ex2_rs2(32) when "1000", + // byp_mul_ex2_rs2(32) when "0100", + // byp_mul_ex2_rs2( 0) when "0010", + // byp_mul_ex2_rs2( 0) when "0001", + // '0' when others; + + assign ex3_bs_lo_sign_d = ((ex2_bs_sign & ex2_mul_sign_q & (ex2_mulstage[1] | ex2_mulstage[3])) & ex2_mul_size_q) | (ex2_bs_sign & ex2_mul_sign_q & (~ex2_mul_size_q)) | (ex2_bs_sign & ex2_mul_sign_q & ex2_mulstage[1] & ex2_retsel_q[2]); + assign ex3_bd_lo_sign_d = ((ex2_bd_sign & ex2_mul_sign_q & (ex2_mulstage[2] | ex2_mulstage[3])) & ex2_mul_size_q) | (ex2_bd_sign & ex2_mul_sign_q & (~ex2_mul_size_q)) | (ex2_bd_sign & ex2_mul_sign_q & ex2_retsel_q[2]); + + //------------------------------------------------------------------- + // Operands + //------------------------------------------------------------------- + assign ex2_mulsrc0_act = |(ex2_mulstage); + assign ex2_mulsrc1_act = ex2_mulstage[0] | ex2_mulstage[2]; + + assign ex2_mulsrc_0[0:63] = (ex2_mul_val_q == 1'b1) ? byp_mul_ex2_rs1[0:63] : + {ex3_mulsrc_0_q[32:63], ex3_mulsrc_0_q[0:31]}; + + // Use the saved value for bd_sign when mulsrc1 is clock gated + assign ex2_mulsrc_1[0:63] = (ex2_mul_val_q == 1'b1) ? byp_mul_ex2_rs2[0:63] : + {ex3_mulsrc_1_q[32:63], ex3_mulsrc_1_q[0:31]}; + + assign ex2_bd_sign = ((ex2_mulstage[1] | ex2_mulstage[3]) == 1'b1) ? ex3_mulsrc_1_q[32] : + ex2_mulsrc_1[32]; + assign ex2_bs_sign = ex2_mulsrc_0[32]; + assign ex3_bs_lo = ex3_mulsrc_0_q[32:63]; + assign ex3_bd_lo = ex3_mulsrc_1_q[32:63]; + + // with ex2_mulstage select + // ex3_bs_lo_d(0 to 31) <= byp_mul_ex2_rs1(32 to 63) when "1000", + // byp_mul_ex2_rs1( 0 to 31) when "0100", + // byp_mul_ex2_rs1(32 to 63) when "0010", + // byp_mul_ex2_rs1( 0 to 31) when "0001", + // (others => 0) when others; + // + // with ex2_mulstage select + // ex3_bd_lo_d(0 to 31) <= byp_mul_ex2_rs2(32 to 63) when "1000", + // byp_mul_ex2_rs2(32 to 63) when "0100", + // byp_mul_ex2_rs2( 0 to 31) when "0010", + // byp_mul_ex2_rs2( 0 to 31) when "0001", + // (others => 0) when others; + + //------------------------------------------------------------------- + // Multiply Core + //------------------------------------------------------------------- + + tri_st_mult_core mcore( + .nclk(nclk), + .vdd(vdd), + .gnd(gnd), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .func_sl_force(func_sl_force), + .func_sl_thold_0_b(func_sl_thold_0_b), + .sg_0(sg_0), + .scan_in(siv[0]), + .scan_out(sov[0]), + .ex3_act(ex3_act), + .ex4_act(ex4_act), + .ex3_bs_lo_sign(ex3_bs_lo_sign_q), + .ex3_bd_lo_sign(ex3_bd_lo_sign_q), + .ex3_bs_lo(ex3_bs_lo), + .ex3_bd_lo(ex3_bd_lo), + .ex4_recycle_s(ex4_recycle_s[196:264]), + .ex4_recycle_c(ex4_recycle_c[196:263]), + .ex5_pp5_0s_out(ex5_pp5_0s), + .ex5_pp5_0c_out(ex5_pp5_0c[196:263]) + ); + + assign ex5_pp5_0c[264] = 0; + + assign ex3_act = | ex3_mulstage_q; + assign ex4_act = | ex4_mulstage_q; + assign ex5_act = | ex5_mulstage_q; + + //------------------------------------------------------------------- + // Carry In + //------------------------------------------------------------------- + // |---------|---------| + // |---------|---------| dly <--/ * for mulli + // |---------|---------| dly1 <-/ * for mulld + // |---------|---------| dly <--/ * for mulhd + + assign ex5_ci_d = (carry_32_dly1_q & ex4_mulstage_q[2]) | (ex5_cout_32 & ((ex4_mulstage_q[3] & ex4_retsel_q[1]) | (ex4_mulstage_q[1] & ex4_retsel_q[2]))); // feedback from previous previous add + + //------------------------------------------------------------------- + // Adder (ripple carry for simulation, replace with carry look ahead + //------------------------------------------------------------------- + assign ex5_xi = ex5_pp5_0s[200:263]; + assign ex5_yi = ex5_pp5_0c[200:263]; + + assign ex5_p = ex5_xi[0:63] ^ ex5_yi[0:63]; + assign ex5_g = ex5_xi[1:63] & ex5_yi[1:63]; + assign ex5_t = ex5_xi[1:63] | ex5_yi[1:63]; + + assign ex5_xi_b[0:63] = (~ex5_xi[0:63]); + assign ex5_yi_b[0:63] = (~ex5_yi[0:63]); + + + tri_st_add cla64ci( + .x_b(ex5_xi_b[0:63]), + .y_b(ex5_yi_b[0:63]), + .ci(ex5_ci_q), + .sum(ex5_res[0:63]), + .cout_32(ex5_cout_32), + .cout_0() + ); + + //------------------------------------------------------------------- + // Determine Recirculation + //------------------------------------------------------------------- + // Shift amount + assign ex4_recyc_sh32 = ex4_retsel_q[1] & (ex4_mulstage_q[1] | ex4_mulstage_q[3]); + assign ex4_recyc_sh00 = ex4_retsel_q[1] & (ex4_mulstage_q[2]); + + // Get rid of "bogus" bit + assign ex4_xtd_196_or = ex5_pp5_0s[196] | ex5_pp5_0c[196]; + assign ex4_xtd_196_and = ex5_pp5_0s[196] & ex5_pp5_0c[196]; + assign ex4_xtd_197_or = ex5_pp5_0s[197] | ex5_pp5_0c[197]; + assign ex4_xtd_197_and = ex5_pp5_0s[197] & ex5_pp5_0c[197]; + + assign ex4_xtd_ge1 = ex4_xtd_196_or | ex4_xtd_197_or; + assign ex4_xtd_ge2 = ex4_xtd_196_or | ex4_xtd_197_and; + assign ex4_xtd_ge3 = ex4_xtd_196_and | (ex4_xtd_196_or & ex4_xtd_197_or); + + assign ex4_xtd = (ex4_mulstage_q[1] & ex4_retsel_q[1] & (~ex4_xtd_ge1)) | (ex4_mulstage_q[2] & ex4_retsel_q[1] & (~ex4_xtd_ge2)) | (ex4_mulstage_q[3] & ex4_retsel_q[1] & (~ex4_xtd_ge3)); + + assign ex4_recycle_s[196] = ex5_pp5_0s[196] & (ex4_retsel_q[1] & (~ex4_mulstage_q[0])); + assign ex4_recycle_c[196] = ex5_pp5_0c[196] & (ex4_retsel_q[1] & (~ex4_mulstage_q[0])); + + assign ex4_recycle_s[197] = ex5_pp5_0s[197] & (ex4_retsel_q[1] & (~ex4_mulstage_q[0])); + assign ex4_recycle_c[197] = ex5_pp5_0c[197] & (ex4_retsel_q[1] & (~ex4_mulstage_q[0])); + + assign ex4_recycle_s[198:264] = ({67{ex4_recyc_sh00}} & (ex5_pp5_0s[198:264])) | + ({67{ex4_recyc_sh32}} & ({{32{ex4_xtd}}, ex5_pp5_0s[198:231], 1'b0})); + + assign ex4_recycle_c[198:264] = ({67{ex4_recyc_sh00}} & (ex5_pp5_0c[198:264])) | + ({67{ex4_recyc_sh32}} & ({32'b0, ex5_pp5_0c[198:231], 1'b0})); + + //------------------------------------------------------------------- + // Result + //------------------------------------------------------------------- + assign rslt_lo_act = ex6_mulstage_q[0] | ex6_mulstage_q[2]; + + assign rslt_lo_d = ex6_res_q[32:63]; + assign rslt_lo_dly_d = rslt_lo_q; + + // RETURN RET SIZE IMM OVF READY + // mulhw (0 to 31 => '0') & ex6_res_q(0 to 31) 1 0 0 . 1000 + // mullw ex6_res_q 0 0 0 . 1000 + // mulli ex6_res_q(32 to 63) & rslt_lo_q . . 1 . 0100 + // mulld ex6_res_q(32 to 63) & rslt_lo_q 0 1 0 0 0010 + // mulldo rslt_lo_q & rslt_lo_dly_q 0 1 0 1 0001 + // mulhd ex6_res_q 1 1 0 . 0001 + + assign ex5_ret_mulhw = ex5_retsel_q[0] & (~ex5_retsel_q[1]) & (~ex5_retsel_q[2]); + assign ex5_ret_mullw = (~ex5_retsel_q[0]) & (~ex5_retsel_q[1]) & (~ex5_retsel_q[2]); + assign ex5_ret_mulli = ex5_retsel_q[2]; + assign ex5_ret_mulld = (~ex5_retsel_q[0]) & ex5_retsel_q[1] & (~ex5_retsel_q[2]) & (~ex5_xer_ov_update_q); + assign ex5_ret_mulldo = (~ex5_retsel_q[0]) & ex5_retsel_q[1] & (~ex5_retsel_q[2]) & ex5_xer_ov_update_q; + assign ex5_ret_mulhd = ex5_retsel_q[0] & ex5_retsel_q[1] & (~ex5_retsel_q[2]); + + assign ex6_rslt_hw_d = {8{(ex5_ret_mulhw)}}; + assign ex6_rslt_ld_li_d = {8{(ex5_ret_mulli | ex5_ret_mulld)}}; + assign ex6_rslt_ldo_d = {8{(ex5_ret_mulldo)}}; + assign ex6_rslt_lw_hd_d = {8{(ex5_ret_mullw | ex5_ret_mulhd)}}; + + generate + genvar i; + for (i = 0; i <= 7; i = i + 1) + begin : fanout_gen + assign ex6_rslt_hw[8*i:8*i+7] = {8{ex6_rslt_hw_q[i]}}; + assign ex6_rslt_ld_li[8*i:8*i+7] = {8{ex6_rslt_ld_li_q[i]}}; + assign ex6_rslt_ldo[8*i:8*i+7] = {8{ex6_rslt_ldo_q[i]}}; + assign ex6_rslt_lw_hd[8*i:8*i+7] = {8{ex6_rslt_lw_hd_q[i]}}; + end + endgenerate + + assign ex6_result = ({32'b0, ex6_res_q[0:31]} & ex6_rslt_hw) | + ({ex6_res_q[32:63], rslt_lo_q} & ex6_rslt_ld_li) | + ({rslt_lo_q, rslt_lo_dly_q} & ex6_rslt_ldo) | + (ex6_res_q & ex6_rslt_lw_hd); + + //------------------------------------------------------------------- + // Overflow + //------------------------------------------------------------------- + assign ex5_all0_test[0:62] = ((~ex5_p[0:62]) & (~ex5_t[1:63])) | (ex5_p[0:62] & ex5_t[1:63]); + assign ex5_all0_test[63] = ((~ex5_p[63]) & (~ex5_ci_q)) | (ex5_p[63] & ex5_ci_q); + assign ex5_all0_test_mid = ((~ex5_p[31]) & (~ex5_cout_32)) | (ex5_p[31] & ex5_cout_32); + + assign ex5_all1_test[0:62] = (ex5_p[0:62] & (~ex5_g[1:63])) | ((~ex5_p[0:62]) & ex5_g[1:63]); + assign ex5_all1_test[63] = (ex5_p[63] & (~ex5_ci_q)) | ((~ex5_p[63]) & ex5_ci_q); + assign ex5_all1_test_mid = (ex5_p[31] & (~ex5_cout_32)) | ((~ex5_p[31]) & ex5_cout_32); + + assign ex5_all0 = &(ex5_all0_test[0:63]); + assign ex5_all1 = &(ex5_all1_test[0:63]); + assign ex5_all0_lo = &(ex5_all0_test[32:63]); + assign ex5_all0_hi = &({ex5_all0_test[0:30], ex5_all0_test_mid}); + assign ex5_all1_hi = &({ex5_all1_test[0:30], ex5_all1_test_mid}); + + // What sign bit to use for compare to zero? + // + // | CM = 1 (64b) | CM = 0 (32b) | + // hw | '0' | ex6_res_q(0) | <- 64b case is undefined ,return zero + // lw | ex6_res_q(0) | ex6_res_q(32) | + // hd | ex6_res_q(0) | ex6_res_q(32) | + // ld | ex6_res_q(32) | rslt_lo_q(0) | + // ldo | rslt_lo_q(0) | rslt_lo_dly_q(0) | + + assign ex6_cmp0_undef_d = ex5_ret_mulhw & ex5_spr_msr_cm_q; + + assign ex6_cmp0_sel_reshi_d = (ex5_ret_mulhw) | ((ex5_ret_mullw | ex5_ret_mulhd) & ex5_spr_msr_cm_q); + assign ex6_cmp0_sel_reslo_d = ((ex5_ret_mullw | ex5_ret_mulhd) & (~ex5_spr_msr_cm_q)) | (ex5_ret_mulld & ex5_spr_msr_cm_q); + assign ex6_cmp0_sel_reslodly_d = (ex5_ret_mulld & (~ex5_spr_msr_cm_q)) | (ex5_ret_mulldo & ex5_spr_msr_cm_q); + assign ex6_cmp0_sel_reslodly2_d = (ex5_ret_mulldo & (~ex5_spr_msr_cm_q)); + + assign ex6_sign_rt_cmp0 = (ex6_cmp0_sel_reshi_q & ex6_res_q[0]) | (ex6_cmp0_sel_reslo_q & ex6_res_q[32]) | (ex6_cmp0_sel_reslodly_q & rslt_lo_q[0]) | (ex6_cmp0_sel_reslodly2_q & rslt_lo_dly_q[0]); + + // +-----------------------------+-----------------------------+ + // | CM = 1 (64b) | CM = 0 (32b) | + // +-----------------------------+-----------------------------+ + // lw | all0 | all0_lo + // hd | all0 | all0 & all0_lo + // ld | all0_lo & all0_lo_dly2 | all0_lo_dly2 + // ldo | all0_lo_dly1 & all0_lo_dly3 | all0_lo_dly3 + // hw | all0_hi | all0_hi <- 64b case is undefined ,return zero + // +-----------------------------+-----------------------------+ + + assign ex6_eq_sel_all0_hi_b_d = (~(ex5_ret_mulhw)); + + assign ex6_eq_sel_all0_b_d = (~((ex5_ret_mullw & ex5_spr_msr_cm_q) | (ex5_ret_mulhd & ex5_spr_msr_cm_q))); + + assign ex6_eq_sel_all0_lo_b_d = (~((ex5_ret_mullw & (~ex5_spr_msr_cm_q)) | (ex5_ret_mulhd & (~ex5_spr_msr_cm_q)) | (ex5_ret_mulld & ex5_spr_msr_cm_q))); + + assign ex6_eq_sel_all0_lo1_b_d = (~((ex5_ret_mulldo & ex5_spr_msr_cm_q))); + + assign ex6_eq_sel_all0_lo2_b_d = (~(ex5_ret_mulld)); + + assign ex6_eq_sel_all0_lo3_b_d = (~(ex5_ret_mulldo)); + + assign ex6_eq = (ex6_eq_sel_all0_b_q | ex6_all0_q) & (ex6_eq_sel_all0_lo_b_q | ex6_all0_lo_q) & (ex6_eq_sel_all0_lo1_b_q | all0_lo_dly1_q) & (ex6_eq_sel_all0_lo2_b_q | all0_lo_dly2_q) & (ex6_eq_sel_all0_lo3_b_q | all0_lo_dly3_q) & (ex6_eq_sel_all0_hi_b_q | ex6_all0_hi_q); + + assign ex6_cmp0_eq = ex6_eq & (~ex6_cmp0_undef_q); + assign ex6_cmp0_gt = (~ex6_sign_rt_cmp0) & (~ex6_eq) & (~ex6_cmp0_undef_q); + assign ex6_cmp0_lt = ex6_sign_rt_cmp0 & (~ex6_eq) & (~ex6_cmp0_undef_q); + + // What sign bit to use for overflow detection? + // + // lwo - ex6_res_q(32) + // ldo - rslt_lo_q(0) + + assign ex6_xer_ov = (ex6_ret_mullw_q & (((~ex6_res_q[32]) & (~ex6_all0_hi_q)) | (ex6_res_q[32] & (~ex6_all1_hi_q)))) | (ex6_ret_mulldo_q & (((~rslt_lo_q[0]) & (~ex6_all0_q)) | (rslt_lo_q[0] & (~ex6_all1_q)))); + + //------------------------------------------------------------------- + // Return + //------------------------------------------------------------------- + assign ex6_xer_ov_gated = (ex6_xer_ov & ex6_xer_ov_update_q) | (ex6_xer_src_q[1] & (~ex6_xer_ov_update_q)); + + assign ex6_xer_so = (ex6_xer_src_q[0] | (ex6_xer_ov & ex6_xer_ov_update_q)); + + assign mul_byp_ex6_rt = ex6_result[64 - (`GPR_WIDTH):63]; + assign mul_byp_ex6_cr = {ex6_cmp0_lt, ex6_cmp0_gt, ex6_cmp0_eq, ex6_xer_so}; + assign mul_byp_ex6_xer = {ex6_xer_so, ex6_xer_ov_gated, ex6_xer_src_q[2:9]}; + + //------------------------------------------------------------------- + // Assert a signal when the result is ready + //------------------------------------------------------------------- + + // READY RET SIZE IMM OVERFLOW + // mulhw 1000 . 0 0 . + // mullw 1000 . 0 0 . + // mulli 0100 . . 1 . + // mulld 0010 0 1 0 0 + // mulldo 0001 0 1 0 1 + // mulhd 0001 1 1 0 . + + assign ex3_ready_stage[0] = ((~ex3_retsel_q[1]) & (~ex3_retsel_q[2])); + assign ex3_ready_stage[1] = (ex3_retsel_q[2]); + assign ex3_ready_stage[2] = ((~ex3_retsel_q[0]) & ex3_retsel_q[1] & (~ex3_retsel_q[2]) & (~ex3_xer_ov_update_q)); + assign ex3_ready_stage[3] = ((~ex3_retsel_q[0]) & ex3_retsel_q[1] & (~ex3_retsel_q[2]) & ex3_xer_ov_update_q) | (ex3_retsel_q[0] & ex3_retsel_q[1] & (~ex3_retsel_q[2])); + + assign ex4_mul_done_d = |(ex3_ready_stage & ex3_mulstage_q); + + assign mul_byp_ex5_ord_done = ex5_mul_done_q & ex5_mul_is_ord_q & ~ex5_flush; + assign mul_byp_ex5_done = ex5_mul_done_q & ~ex5_mul_is_ord_q & ~ex5_flush; + + //---------------------------------------------------------------------------------------------------------------------------------------- + + //------------------------------------------------------------------- + // Latch Instances + //------------------------------------------------------------------- + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_spr_msr_cm_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_mul_val), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_spr_msr_cm_offset]), + .scout(sov[ex2_spr_msr_cm_offset]), + .din(ex1_spr_msr_cm), + .dout(ex2_spr_msr_cm_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_spr_msr_cm_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_mul_val_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_spr_msr_cm_offset]), + .scout(sov[ex3_spr_msr_cm_offset]), + .din(ex2_spr_msr_cm_q), + .dout(ex3_spr_msr_cm_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_spr_msr_cm_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_spr_msr_cm_offset]), + .scout(sov[ex4_spr_msr_cm_offset]), + .din(ex3_spr_msr_cm_q), + .dout(ex4_spr_msr_cm_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_spr_msr_cm_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex4_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_spr_msr_cm_offset]), + .scout(sov[ex5_spr_msr_cm_offset]), + .din(ex4_spr_msr_cm_q), + .dout(ex5_spr_msr_cm_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_mul_is_ord_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_mul_val), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_mul_is_ord_offset]), + .scout(sov[ex2_mul_is_ord_offset]), + .din(dec_mul_ex1_mul_ord), + .dout(ex2_mul_is_ord_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_mul_is_ord_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_mul_val_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_mul_is_ord_offset]), + .scout(sov[ex3_mul_is_ord_offset]), + .din(ex2_mul_is_ord_q), + .dout(ex3_mul_is_ord_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_mul_is_ord_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_mul_is_ord_offset]), + .scout(sov[ex4_mul_is_ord_offset]), + .din(ex3_mul_is_ord_q), + .dout(ex4_mul_is_ord_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_mul_is_ord_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex4_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_mul_is_ord_offset]), + .scout(sov[ex5_mul_is_ord_offset]), + .din(ex4_mul_is_ord_q), + .dout(ex5_mul_is_ord_q) + ); + + tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) ex3_xer_src_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_mul_val_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_xer_src_offset:ex3_xer_src_offset + 10 - 1]), + .scout(sov[ex3_xer_src_offset:ex3_xer_src_offset + 10 - 1]), + .din(byp_mul_ex2_xer), + .dout(ex3_xer_src_q) + ); + + tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) ex4_xer_src_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_xer_src_offset:ex4_xer_src_offset + 10 - 1]), + .scout(sov[ex4_xer_src_offset:ex4_xer_src_offset + 10 - 1]), + .din(ex3_xer_src_q), + .dout(ex4_xer_src_q) + ); + + tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) ex5_xer_src_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex4_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_xer_src_offset:ex5_xer_src_offset + 10 - 1]), + .scout(sov[ex5_xer_src_offset:ex5_xer_src_offset + 10 - 1]), + .din(ex4_xer_src_q), + .dout(ex5_xer_src_q) + ); + + tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) ex6_xer_src_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex5_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_xer_src_offset:ex6_xer_src_offset + 10 - 1]), + .scout(sov[ex6_xer_src_offset:ex6_xer_src_offset + 10 - 1]), + .din(ex5_xer_src_q), + .dout(ex6_xer_src_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_mul_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_mul_val_offset]), + .scout(sov[ex2_mul_val_offset]), + .din(ex1_mul_val), + .dout(ex2_mul_val_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ex3_mulstage_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_mulstage_offset:ex3_mulstage_offset + 4 - 1]), + .scout(sov[ex3_mulstage_offset:ex3_mulstage_offset + 4 - 1]), + .din(ex3_mulstage_d), + .dout(ex3_mulstage_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ex4_mulstage_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_mulstage_offset:ex4_mulstage_offset + 4 - 1]), + .scout(sov[ex4_mulstage_offset:ex4_mulstage_offset + 4 - 1]), + .din(ex4_mulstage_d), + .dout(ex4_mulstage_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ex5_mulstage_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_mulstage_offset:ex5_mulstage_offset + 4 - 1]), + .scout(sov[ex5_mulstage_offset:ex5_mulstage_offset + 4 - 1]), + .din(ex5_mulstage_d), + .dout(ex5_mulstage_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ex6_mulstage_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_mulstage_offset:ex6_mulstage_offset + 4 - 1]), + .scout(sov[ex6_mulstage_offset:ex6_mulstage_offset + 4 - 1]), + .din(ex6_mulstage_d), + .dout(ex6_mulstage_q) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex2_retsel_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_mul_val), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_retsel_offset:ex2_retsel_offset + 3 - 1]), + .scout(sov[ex2_retsel_offset:ex2_retsel_offset + 3 - 1]), + .din(ex2_retsel_d), + .dout(ex2_retsel_q) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex3_retsel_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_mul_val_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_retsel_offset:ex3_retsel_offset + 3 - 1]), + .scout(sov[ex3_retsel_offset:ex3_retsel_offset + 3 - 1]), + .din(ex2_retsel_q), + .dout(ex3_retsel_q) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex4_retsel_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_retsel_offset:ex4_retsel_offset + 3 - 1]), + .scout(sov[ex4_retsel_offset:ex4_retsel_offset + 3 - 1]), + .din(ex3_retsel_q), + .dout(ex4_retsel_q) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex5_retsel_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_retsel_offset:ex5_retsel_offset + 3 - 1]), + .scout(sov[ex5_retsel_offset:ex5_retsel_offset + 3 - 1]), + .din(ex4_retsel_q), + .dout(ex5_retsel_q) + ); + + tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) exx_mul_abort_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[exx_mul_abort_offset:exx_mul_abort_offset + 6 -1]), + .scout(sov[exx_mul_abort_offset:exx_mul_abort_offset + 6 -1]), + .din(exx_mul_abort_d), + .dout(exx_mul_abort_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_mul_done_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_mul_done_offset]), + .scout(sov[ex4_mul_done_offset]), + .din(ex4_mul_done_d), + .dout(ex4_mul_done_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_mul_done_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_mul_done_offset]), + .scout(sov[ex5_mul_done_offset]), + .din(ex4_mul_done_q), + .dout(ex5_mul_done_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_is_recform_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_mul_val), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_is_recform_offset]), + .scout(sov[ex2_is_recform_offset]), + .din(dec_mul_ex1_mul_recform), + .dout(ex2_is_recform_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_is_recform_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_is_recform_offset]), + .scout(sov[ex3_is_recform_offset]), + .din(ex2_is_recform_q), + .dout(ex3_is_recform_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_is_recform_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_is_recform_offset]), + .scout(sov[ex4_is_recform_offset]), + .din(ex3_is_recform_q), + .dout(ex4_is_recform_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_is_recform_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_is_recform_offset]), + .scout(sov[ex5_is_recform_offset]), + .din(ex4_is_recform_q), + .dout(ex5_is_recform_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_is_recform_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_is_recform_offset]), + .scout(sov[ex6_is_recform_offset]), + .din(ex5_is_recform_q), + .dout(ex6_is_recform_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_xer_ov_update_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_mul_val), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_xer_ov_update_offset]), + .scout(sov[ex2_xer_ov_update_offset]), + .din(dec_mul_ex1_xer_ov_update), + .dout(ex2_xer_ov_update_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_xer_ov_update_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_xer_ov_update_offset]), + .scout(sov[ex3_xer_ov_update_offset]), + .din(ex2_xer_ov_update_q), + .dout(ex3_xer_ov_update_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_xer_ov_update_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_xer_ov_update_offset]), + .scout(sov[ex4_xer_ov_update_offset]), + .din(ex3_xer_ov_update_q), + .dout(ex4_xer_ov_update_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_xer_ov_update_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_xer_ov_update_offset]), + .scout(sov[ex5_xer_ov_update_offset]), + .din(ex4_xer_ov_update_q), + .dout(ex5_xer_ov_update_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_xer_ov_update_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_xer_ov_update_offset]), + .scout(sov[ex6_xer_ov_update_offset]), + .din(ex5_xer_ov_update_q), + .dout(ex6_xer_ov_update_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_mul_size_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_mul_val), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_mul_size_offset]), + .scout(sov[ex2_mul_size_offset]), + .din(dec_mul_ex1_mul_size), + .dout(ex2_mul_size_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_mul_sign_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_mul_val), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_mul_sign_offset]), + .scout(sov[ex2_mul_sign_offset]), + .din(dec_mul_ex1_mul_sign), + .dout(ex2_mul_sign_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_bs_lo_sign_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_bs_lo_sign_offset]), + .scout(sov[ex3_bs_lo_sign_offset]), + .din(ex3_bs_lo_sign_d), + .dout(ex3_bs_lo_sign_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_bd_lo_sign_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_bd_lo_sign_offset]), + .scout(sov[ex3_bd_lo_sign_offset]), + .din(ex3_bd_lo_sign_d), + .dout(ex3_bd_lo_sign_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_all0_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_all0_offset]), + .scout(sov[ex6_all0_offset]), + .din(ex5_all0), + .dout(ex6_all0_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_all1_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_all1_offset]), + .scout(sov[ex6_all1_offset]), + .din(ex5_all1), + .dout(ex6_all1_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_all0_lo_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_all0_lo_offset]), + .scout(sov[ex6_all0_lo_offset]), + .din(ex5_all0_lo), + .dout(ex6_all0_lo_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_all0_hi_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_all0_hi_offset]), + .scout(sov[ex6_all0_hi_offset]), + .din(ex5_all0_hi), + .dout(ex6_all0_hi_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_all1_hi_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_all1_hi_offset]), + .scout(sov[ex6_all1_hi_offset]), + .din(ex5_all1_hi), + .dout(ex6_all1_hi_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_ci_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_ci_offset]), + .scout(sov[ex5_ci_offset]), + .din(ex5_ci_d), + .dout(ex5_ci_q) + ); + + tri_rlmreg_p #(.WIDTH(64), .INIT(0), .NEEDS_SRESET(1)) ex6_res_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex5_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_res_offset:ex6_res_offset + 64 - 1]), + .scout(sov[ex6_res_offset:ex6_res_offset + 64 - 1]), + .din(ex5_res), + .dout(ex6_res_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) carry_32_dly1_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[carry_32_dly1_offset]), + .scout(sov[carry_32_dly1_offset]), + .din(ex5_cout_32), + .dout(carry_32_dly1_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) all0_lo_dly1_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[all0_lo_dly1_offset]), + .scout(sov[all0_lo_dly1_offset]), + .din(ex6_all0_lo_q), + .dout(all0_lo_dly1_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) all0_lo_dly2_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[all0_lo_dly2_offset]), + .scout(sov[all0_lo_dly2_offset]), + .din(all0_lo_dly1_q), + .dout(all0_lo_dly2_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) all0_lo_dly3_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[all0_lo_dly3_offset]), + .scout(sov[all0_lo_dly3_offset]), + .din(all0_lo_dly2_q), + .dout(all0_lo_dly3_q) + ); + + tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) rslt_lo_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rslt_lo_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rslt_lo_offset:rslt_lo_offset + 32 - 1]), + .scout(sov[rslt_lo_offset:rslt_lo_offset + 32 - 1]), + .din(rslt_lo_d), + .dout(rslt_lo_q) + ); + + tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) rslt_lo_dly_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rslt_lo_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rslt_lo_dly_offset:rslt_lo_dly_offset + 32 - 1]), + .scout(sov[rslt_lo_dly_offset:rslt_lo_dly_offset + 32 - 1]), + .din(rslt_lo_dly_d), + .dout(rslt_lo_dly_q) + ); + + tri_rlmreg_p #(.WIDTH(64), .INIT(0), .NEEDS_SRESET(1)) ex3_mulsrc_0_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_mulsrc0_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_mulsrc_0_offset:ex3_mulsrc_0_offset + 64 - 1]), + .scout(sov[ex3_mulsrc_0_offset:ex3_mulsrc_0_offset + 64 - 1]), + .din(ex2_mulsrc_0), + .dout(ex3_mulsrc_0_q) + ); + + tri_rlmreg_p #(.WIDTH(64), .INIT(0), .NEEDS_SRESET(1)) ex3_mulsrc_1_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_mulsrc1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_mulsrc_1_offset:ex3_mulsrc_1_offset + 64 - 1]), + .scout(sov[ex3_mulsrc_1_offset:ex3_mulsrc_1_offset + 64 - 1]), + .din(ex2_mulsrc_1), + .dout(ex3_mulsrc_1_q) + ); + + tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex6_rslt_hw_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex5_mul_done_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_rslt_hw_offset:ex6_rslt_hw_offset + 8 - 1]), + .scout(sov[ex6_rslt_hw_offset:ex6_rslt_hw_offset + 8 - 1]), + .din(ex6_rslt_hw_d), + .dout(ex6_rslt_hw_q) + ); + + tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex6_rslt_ld_li_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex5_mul_done_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_rslt_ld_li_offset:ex6_rslt_ld_li_offset + 8 - 1]), + .scout(sov[ex6_rslt_ld_li_offset:ex6_rslt_ld_li_offset + 8 - 1]), + .din(ex6_rslt_ld_li_d), + .dout(ex6_rslt_ld_li_q) + ); + + tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex6_rslt_ldo_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex5_mul_done_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_rslt_ldo_offset:ex6_rslt_ldo_offset + 8 - 1]), + .scout(sov[ex6_rslt_ldo_offset:ex6_rslt_ldo_offset + 8 - 1]), + .din(ex6_rslt_ldo_d), + .dout(ex6_rslt_ldo_q) + ); + + tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex6_rslt_lw_hd_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex5_mul_done_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_rslt_lw_hd_offset:ex6_rslt_lw_hd_offset + 8 - 1]), + .scout(sov[ex6_rslt_lw_hd_offset:ex6_rslt_lw_hd_offset + 8 - 1]), + .din(ex6_rslt_lw_hd_d), + .dout(ex6_rslt_lw_hd_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_cmp0_sel_reshi_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex5_mul_done_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_cmp0_sel_reshi_offset]), + .scout(sov[ex6_cmp0_sel_reshi_offset]), + .din(ex6_cmp0_sel_reshi_d), + .dout(ex6_cmp0_sel_reshi_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_cmp0_sel_reslo_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex5_mul_done_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_cmp0_sel_reslo_offset]), + .scout(sov[ex6_cmp0_sel_reslo_offset]), + .din(ex6_cmp0_sel_reslo_d), + .dout(ex6_cmp0_sel_reslo_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_cmp0_sel_reslodly_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex5_mul_done_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_cmp0_sel_reslodly_offset]), + .scout(sov[ex6_cmp0_sel_reslodly_offset]), + .din(ex6_cmp0_sel_reslodly_d), + .dout(ex6_cmp0_sel_reslodly_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_cmp0_sel_reslodly2_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex5_mul_done_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_cmp0_sel_reslodly2_offset]), + .scout(sov[ex6_cmp0_sel_reslodly2_offset]), + .din(ex6_cmp0_sel_reslodly2_d), + .dout(ex6_cmp0_sel_reslodly2_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_eq_sel_all0_b_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex5_mul_done_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_eq_sel_all0_b_offset]), + .scout(sov[ex6_eq_sel_all0_b_offset]), + .din(ex6_eq_sel_all0_b_d), + .dout(ex6_eq_sel_all0_b_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_eq_sel_all0_lo_b_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex5_mul_done_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_eq_sel_all0_lo_b_offset]), + .scout(sov[ex6_eq_sel_all0_lo_b_offset]), + .din(ex6_eq_sel_all0_lo_b_d), + .dout(ex6_eq_sel_all0_lo_b_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_eq_sel_all0_hi_b_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex5_mul_done_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_eq_sel_all0_hi_b_offset]), + .scout(sov[ex6_eq_sel_all0_hi_b_offset]), + .din(ex6_eq_sel_all0_hi_b_d), + .dout(ex6_eq_sel_all0_hi_b_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_eq_sel_all0_lo1_b_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex5_mul_done_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_eq_sel_all0_lo1_b_offset]), + .scout(sov[ex6_eq_sel_all0_lo1_b_offset]), + .din(ex6_eq_sel_all0_lo1_b_d), + .dout(ex6_eq_sel_all0_lo1_b_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_eq_sel_all0_lo2_b_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex5_mul_done_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_eq_sel_all0_lo2_b_offset]), + .scout(sov[ex6_eq_sel_all0_lo2_b_offset]), + .din(ex6_eq_sel_all0_lo2_b_d), + .dout(ex6_eq_sel_all0_lo2_b_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_eq_sel_all0_lo3_b_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex5_mul_done_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_eq_sel_all0_lo3_b_offset]), + .scout(sov[ex6_eq_sel_all0_lo3_b_offset]), + .din(ex6_eq_sel_all0_lo3_b_d), + .dout(ex6_eq_sel_all0_lo3_b_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_ret_mullw_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex5_mul_done_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_ret_mullw_offset]), + .scout(sov[ex6_ret_mullw_offset]), + .din(ex5_ret_mullw), + .dout(ex6_ret_mullw_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_ret_mulldo_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex5_mul_done_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_ret_mulldo_offset]), + .scout(sov[ex6_ret_mulldo_offset]), + .din(ex5_ret_mulldo), + .dout(ex6_ret_mulldo_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_cmp0_undef_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex5_mul_done_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_cmp0_undef_offset]), + .scout(sov[ex6_cmp0_undef_offset]), + .din(ex6_cmp0_undef_d), + .dout(ex6_cmp0_undef_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) cp_flush_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[cp_flush_offset:cp_flush_offset + `THREADS - 1]), + .scout(sov[cp_flush_offset:cp_flush_offset + `THREADS - 1]), + .din(cp_flush), + .dout(cp_flush_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex2_mul_tid_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_mul_tid_offset:ex2_mul_tid_offset + `THREADS - 1]), + .scout(sov[ex2_mul_tid_offset:ex2_mul_tid_offset + `THREADS - 1]), + .din(dec_mul_ex1_mul_val), + .dout(ex2_mul_tid_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex3_mul_tid_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_mul_val_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_mul_tid_offset:ex3_mul_tid_offset + `THREADS - 1]), + .scout(sov[ex3_mul_tid_offset:ex3_mul_tid_offset + `THREADS - 1]), + .din(ex2_mul_tid_q), + .dout(ex3_mul_tid_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_mul_tid_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ex3_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex4_mul_tid_offset : ex4_mul_tid_offset + `THREADS-1]), + .scout(sov[ex4_mul_tid_offset : ex4_mul_tid_offset + `THREADS-1]), + .din(ex3_mul_tid_q), + .dout(ex4_mul_tid_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex5_mul_tid_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ex4_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex5_mul_tid_offset : ex5_mul_tid_offset + `THREADS-1]), + .scout(sov[ex5_mul_tid_offset : ex5_mul_tid_offset + `THREADS-1]), + .din(ex4_mul_tid_q), + .dout(ex5_mul_tid_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rslt_lo_act_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rslt_lo_act_offset]), + .scout(sov[rslt_lo_act_offset]), + .din(rslt_lo_act), + .dout(rslt_lo_act_q) + ); + + assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in}; + assign scan_out = sov[0]; + +endmodule diff --git a/dev/verilog/trilib/tri_st_mult_boothdcd.v b/dev/verilog/trilib/tri_st_mult_boothdcd.v new file mode 100755 index 0000000..0c5cd15 --- /dev/null +++ b/dev/verilog/trilib/tri_st_mult_boothdcd.v @@ -0,0 +1,100 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +// Description: XU Multiplier Top +// +//***************************************************************************** + +`timescale 1 ns / 1 ns + +module tri_st_mult_boothdcd( + i0, + i1, + i2, + s_neg, + s_x, + s_x2 +); + input i0; + input i1; + input i2; + output s_neg; + output s_x; + output s_x2; + + wire s_add; + wire sx1_a0_b; + wire sx1_a1_b; + wire sx1_t; + wire sx1_i; + wire sx2_a0_b; + wire sx2_a1_b; + wire sx2_t; + wire sx2_i; + wire i0_b; + wire i1_b; + wire i2_b; + + + // i0:2 booth recode table + //-------------------------------- + // 000 add sh1=0 sh2=0 sub_adj=0 + // 001 add sh1=1 sh2=0 sub_adj=0 + // 010 add sh1=1 sh2=0 sub_adj=0 + // 011 add sh1=0 sh2=1 sub_adj=0 + // 100 sub sh1=0 sh2=1 sub_adj=1 + // 101 sub sh1=1 sh2=0 sub_adj=1 + // 110 sub sh1=1 sh2=0 sub_adj=1 + // 111 sub sh1=0 sh2=0 sub_adj=0 + + // logically correct + //---------------------------------- + // s_neg <= (i0); + // s_x <= ( not i1 and i2) or ( i1 and not i2); + // s_x2 <= (i0 and not i1 and not i2) or (not i0 and i1 and i2); + + assign i0_b = (~(i0)); + assign i1_b = (~(i1)); + assign i2_b = (~(i2)); + + assign s_add = (~(i0)); + assign s_neg = (~(s_add)); + + assign sx1_a0_b = (~(i1_b & i2)); + assign sx1_a1_b = (~(i1 & i2_b)); + assign sx1_t = (~(sx1_a0_b & sx1_a1_b)); + assign sx1_i = (~(sx1_t)); + assign s_x = (~(sx1_i)); + + assign sx2_a0_b = (~(i0 & i1_b & i2_b)); + assign sx2_a1_b = (~(i0_b & i1 & i2)); + assign sx2_t = (~(sx2_a0_b & sx2_a1_b)); + assign sx2_i = (~(sx2_t)); + assign s_x2 = (~(sx2_i)); + +endmodule diff --git a/dev/verilog/trilib/tri_st_mult_boothrow.v b/dev/verilog/trilib/tri_st_mult_boothrow.v new file mode 100755 index 0000000..f167f89 --- /dev/null +++ b/dev/verilog/trilib/tri_st_mult_boothrow.v @@ -0,0 +1,423 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +// Description: XU Multiplier Top +// +//***************************************************************************** + +`timescale 1 ns / 1 ns + +module tri_st_mult_boothrow( + s_neg, + s_x, + s_x2, + sign_bit_adj, + x, + q, + hot_one +); + input s_neg; // negate the row + input s_x; // shift by 0 + input s_x2; // shift by 1 + input sign_bit_adj; + input [0:31] x; // input (multiplicand) + output [0:32] q; // final output + // lsb term for row below + output hot_one; + + wire [1:32] left; + + //------------------------------------------------------------------- + // Build the booth mux row bit by bit + //------------------------------------------------------------------- + + tri_bthmx u00( + .sneg(s_neg), + .sx(s_x), + .sx2(s_x2), + .x(sign_bit_adj), + .right(left[1]), + .left(), + .q(q[0]) + ); + + + tri_bthmx u01( + .sneg(s_neg), + .sx(s_x), + .sx2(s_x2), + .x(x[0]), + .right(left[2]), + .left(left[1]), + .q(q[1]) + ); + + + tri_bthmx u02( + .sneg(s_neg), + .sx(s_x), + .sx2(s_x2), + .x(x[1]), + .right(left[3]), + .left(left[2]), + .q(q[2]) + ); + + + tri_bthmx u03( + .sneg(s_neg), + .sx(s_x), + .sx2(s_x2), + .x(x[2]), + .right(left[4]), + .left(left[3]), + .q(q[3]) + ); + + + tri_bthmx u04( + .sneg(s_neg), + .sx(s_x), + .sx2(s_x2), + .x(x[3]), + .right(left[5]), + .left(left[4]), + .q(q[4]) + ); + + + tri_bthmx u05( + .sneg(s_neg), + .sx(s_x), + .sx2(s_x2), + .x(x[4]), + .right(left[6]), + .left(left[5]), + .q(q[5]) + ); + + + tri_bthmx u06( + .sneg(s_neg), + .sx(s_x), + .sx2(s_x2), + .x(x[5]), + .right(left[7]), + .left(left[6]), + .q(q[6]) + ); + + + tri_bthmx u07( + .sneg(s_neg), + .sx(s_x), + .sx2(s_x2), + .x(x[6]), + .right(left[8]), + .left(left[7]), + .q(q[7]) + ); + + + tri_bthmx u08( + .sneg(s_neg), + .sx(s_x), + .sx2(s_x2), + .x(x[7]), + .right(left[9]), + .left(left[8]), + .q(q[8]) + ); + + + tri_bthmx u09( + .sneg(s_neg), + .sx(s_x), + .sx2(s_x2), + .x(x[8]), + .right(left[10]), + .left(left[9]), + .q(q[9]) + ); + + + tri_bthmx u10( + .sneg(s_neg), + .sx(s_x), + .sx2(s_x2), + .x(x[9]), + .right(left[11]), + .left(left[10]), + .q(q[10]) + ); + + + tri_bthmx u11( + .sneg(s_neg), + .sx(s_x), + .sx2(s_x2), + .x(x[10]), + .right(left[12]), + .left(left[11]), + .q(q[11]) + ); + + + tri_bthmx u12( + .sneg(s_neg), + .sx(s_x), + .sx2(s_x2), + .x(x[11]), + .right(left[13]), + .left(left[12]), + .q(q[12]) + ); + + + tri_bthmx u13( + .sneg(s_neg), + .sx(s_x), + .sx2(s_x2), + .x(x[12]), + .right(left[14]), + .left(left[13]), + .q(q[13]) + ); + + + tri_bthmx u14( + .sneg(s_neg), + .sx(s_x), + .sx2(s_x2), + .x(x[13]), + .right(left[15]), + .left(left[14]), + .q(q[14]) + ); + + + tri_bthmx u15( + .sneg(s_neg), + .sx(s_x), + .sx2(s_x2), + .x(x[14]), + .right(left[16]), + .left(left[15]), + .q(q[15]) + ); + + + tri_bthmx u16( + .sneg(s_neg), + .sx(s_x), + .sx2(s_x2), + .x(x[15]), + .right(left[17]), + .left(left[16]), + .q(q[16]) + ); + + + tri_bthmx u17( + .sneg(s_neg), + .sx(s_x), + .sx2(s_x2), + .x(x[16]), + .right(left[18]), + .left(left[17]), + .q(q[17]) + ); + + + tri_bthmx u18( + .sneg(s_neg), + .sx(s_x), + .sx2(s_x2), + .x(x[17]), + .right(left[19]), + .left(left[18]), + .q(q[18]) + ); + + + tri_bthmx u19( + .sneg(s_neg), + .sx(s_x), + .sx2(s_x2), + .x(x[18]), + .right(left[20]), + .left(left[19]), + .q(q[19]) + ); + + + tri_bthmx u20( + .sneg(s_neg), + .sx(s_x), + .sx2(s_x2), + .x(x[19]), + .right(left[21]), + .left(left[20]), + .q(q[20]) + ); + + + tri_bthmx u21( + .sneg(s_neg), + .sx(s_x), + .sx2(s_x2), + .x(x[20]), + .right(left[22]), + .left(left[21]), + .q(q[21]) + ); + + + tri_bthmx u22( + .sneg(s_neg), + .sx(s_x), + .sx2(s_x2), + .x(x[21]), + .right(left[23]), + .left(left[22]), + .q(q[22]) + ); + + + tri_bthmx u23( + .sneg(s_neg), + .sx(s_x), + .sx2(s_x2), + .x(x[22]), + .right(left[24]), + .left(left[23]), + .q(q[23]) + ); + + + tri_bthmx u24( + .sneg(s_neg), + .sx(s_x), + .sx2(s_x2), + .x(x[23]), + .right(left[25]), + .left(left[24]), + .q(q[24]) + ); + + + tri_bthmx u25( + .sneg(s_neg), + .sx(s_x), + .sx2(s_x2), + .x(x[24]), + .right(left[26]), + .left(left[25]), + .q(q[25]) + ); + + + tri_bthmx u26( + .sneg(s_neg), + .sx(s_x), + .sx2(s_x2), + .x(x[25]), + .right(left[27]), + .left(left[26]), + .q(q[26]) + ); + + + tri_bthmx u27( + .sneg(s_neg), + .sx(s_x), + .sx2(s_x2), + .x(x[26]), + .right(left[28]), + .left(left[27]), + .q(q[27]) + ); + + + tri_bthmx u28( + .sneg(s_neg), + .sx(s_x), + .sx2(s_x2), + .x(x[27]), + .right(left[29]), + .left(left[28]), + .q(q[28]) + ); + + + tri_bthmx u29( + .sneg(s_neg), + .sx(s_x), + .sx2(s_x2), + .x(x[28]), + .right(left[30]), + .left(left[29]), + .q(q[29]) + ); + + + tri_bthmx u30( + .sneg(s_neg), + .sx(s_x), + .sx2(s_x2), + .x(x[29]), + .right(left[31]), + .left(left[30]), + .q(q[30]) + ); + + + tri_bthmx u31( + .sneg(s_neg), + .sx(s_x), + .sx2(s_x2), + .x(x[30]), + .right(left[32]), + .left(left[31]), + .q(q[31]) + ); + + + tri_bthmx u32( + .sneg(s_neg), + .sx(s_x), + .sx2(s_x2), + .x(x[31]), + .right(s_neg), + .left(left[32]), + .q(q[32]) + ); + + assign hot_one = s_neg & (s_x | s_x2); + +endmodule diff --git a/dev/verilog/trilib/tri_st_mult_core.v b/dev/verilog/trilib/tri_st_mult_core.v new file mode 100755 index 0000000..08e467c --- /dev/null +++ b/dev/verilog/trilib/tri_st_mult_core.v @@ -0,0 +1,7387 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: XU Multiplier Top +// +//***************************************************************************** + +// ##################################################################### +// ## multiplier with intermediate latches and output latches. +// ## feedback so that 4 32bit multiplies emulate a 64 bit multiply +// ##################################################################### + +`include "tri_a2o.vh" + +module tri_st_mult_core( + nclk, + vdd, + gnd, + delay_lclkr_dc, + mpw1_dc_b, + mpw2_dc_b, + func_sl_force, + func_sl_thold_0_b, + sg_0, + scan_in, + scan_out, + ex3_act, + ex4_act, + ex3_bs_lo_sign, + ex3_bd_lo_sign, + ex3_bd_lo, + ex3_bs_lo, + ex4_recycle_s, + ex4_recycle_c, + ex5_pp5_0s_out, + ex5_pp5_0c_out +); + // Pervasive --------------------------------------- + input [0:`NCLK_WIDTH-1] nclk; + inout vdd; + inout gnd; + input delay_lclkr_dc; + input mpw1_dc_b; + input mpw2_dc_b; + input func_sl_force; + input func_sl_thold_0_b; + input sg_0; + input scan_in; + output scan_out; + + input ex3_act; // for latches at end of first multiply cycle + input ex4_act; // for latches at end of second multiply cycle + + // Numbers to multiply (with separate sign bit) --------------------------- + input ex3_bs_lo_sign; // input data to multiply + input ex3_bd_lo_sign; // input data to multiply + input [0:31] ex3_bd_lo; // input data to multiply + input [0:31] ex3_bs_lo; // input data to multiply + + // Feedback recirculation for multiple cycle multiply --------------------- + input [196:264] ex4_recycle_s; //compressor feedback + input [196:263] ex4_recycle_c; //compressor feedback + + // result vectors ---------------(adder 0:63 uses my number 200:263) + output [196:264] ex5_pp5_0s_out; // compressor output to adder + output [196:263] ex5_pp5_0c_out; // compressor output to adder + + + wire ex4_d1clk; + wire ex5_d1clk; + wire ex4_d2clk; + wire ex5_d2clk; + wire [0:`NCLK_WIDTH-1] ex4_lclk; + wire [0:`NCLK_WIDTH-1] ex5_lclk; + + wire [198:240] ex4_pp2_0c_din; + wire [198:240] ex4_pp2_0c; + wire [198:240] ex4_pp2_0c_q_b; + wire [198:240] ex4_pp2_0c_lat_so; + wire [198:240] ex4_pp2_0c_lat_si; + wire [198:242] ex4_pp2_0s_din; + wire [198:242] ex4_pp2_0s; + wire [198:242] ex4_pp2_0s_q_b; + wire [198:242] ex4_pp2_0s_lat_so; + wire [198:242] ex4_pp2_0s_lat_si; + wire [208:252] ex4_pp2_1c_din; + wire [208:252] ex4_pp2_1c; + wire [208:252] ex4_pp2_1c_x; + wire [208:252] ex4_pp2_1c_x_b; + wire [208:252] ex4_pp2_1c_q_b; + wire [208:252] ex4_pp2_1c_lat_so; + wire [208:252] ex4_pp2_1c_lat_si; + wire [208:254] ex4_pp2_1s_din; + wire [208:254] ex4_pp2_1s; + wire [208:254] ex4_pp2_1s_x; + wire [208:254] ex4_pp2_1s_x_b; + wire [208:254] ex4_pp2_1s_q_b; + wire [208:254] ex4_pp2_1s_lat_so; + wire [208:254] ex4_pp2_1s_lat_si; + wire [220:263] ex4_pp2_2c_din; + wire [220:263] ex4_pp2_2c; + wire [220:263] ex4_pp2_2c_x; + wire [220:263] ex4_pp2_2c_x_b; + wire [220:263] ex4_pp2_2c_q_b; + wire [220:263] ex4_pp2_2c_lat_so; + wire [220:263] ex4_pp2_2c_lat_si; + wire [220:264] ex4_pp2_2s_din; + wire [220:264] ex4_pp2_2s; + wire [220:264] ex4_pp2_2s_x; + wire [220:264] ex4_pp2_2s_x_b; + wire [220:264] ex4_pp2_2s_q_b; + wire [220:264] ex4_pp2_2s_lat_so; + wire [220:264] ex4_pp2_2s_lat_si; + + wire [196:264] ex5_pp5_0s_din; + wire [196:264] ex5_pp5_0s; + wire [196:264] ex5_pp5_0s_q_b; + wire [196:264] ex5_pp5_0s_lat_so; + wire [196:264] ex5_pp5_0s_lat_si; + wire [196:263] ex5_pp5_0c_din; + wire [196:263] ex5_pp5_0c; + wire [196:263] ex5_pp5_0c_q_b; + wire [196:263] ex5_pp5_0c_lat_so; + wire [196:263] ex5_pp5_0c_lat_si; + + wire [0:16] ex3_bd_neg; + wire [0:16] ex3_bd_sh0; + wire [0:16] ex3_bd_sh1; + + wire [0:32] ex3_br_00_out; + wire [0:32] ex3_br_01_out; + wire [0:32] ex3_br_02_out; + wire [0:32] ex3_br_03_out; + wire [0:32] ex3_br_04_out; + wire [0:32] ex3_br_05_out; + wire [0:32] ex3_br_06_out; + wire [0:32] ex3_br_07_out; + wire [0:32] ex3_br_08_out; + wire [0:32] ex3_br_09_out; + wire [0:32] ex3_br_10_out; + wire [0:32] ex3_br_11_out; + wire [0:32] ex3_br_12_out; + wire [0:32] ex3_br_13_out; + wire [0:32] ex3_br_14_out; + wire [0:32] ex3_br_15_out; + wire [0:32] ex3_br_16_out; + wire [0:16] ex3_hot_one; + + wire [199:234] ex3_pp1_0c; + wire [198:236] ex3_pp1_0s; + wire [203:240] ex3_pp1_1c; + wire [202:242] ex3_pp1_1s; + wire [209:246] ex3_pp1_2c; + wire [208:248] ex3_pp1_2s; + wire [215:252] ex3_pp1_3c; + wire [214:254] ex3_pp1_3s; + wire [221:258] ex3_pp1_4c; + wire [220:260] ex3_pp1_4s; + wire [227:264] ex3_pp1_5c; + wire [226:264] ex3_pp1_5s; + + wire [198:240] ex3_pp2_0c; + wire [198:242] ex3_pp2_0s; + wire [208:252] ex3_pp2_1c; + wire [208:254] ex3_pp2_1s; + wire [220:263] ex3_pp2_2c; + wire [220:264] ex3_pp2_2s; + + wire [201:234] ex3_pp2_0k; + wire [213:246] ex3_pp2_1k; + wire [225:258] ex3_pp2_2k; + + wire [197:242] ex4_pp3_0c; + wire [198:252] ex4_pp3_0s; + wire [219:262] ex4_pp3_1c; + wire [208:264] ex4_pp3_1s; + + wire [207:242] ex4_pp4_0k; + wire [197:262] ex4_pp4_0c; + wire [197:264] ex4_pp4_0s; + + wire [196:262] ex4_pp5_0k; + wire [195:263] ex4_pp5_0c; + wire [196:264] ex4_pp5_0s; + wire ex3_br_00_add; + wire ex3_br_01_add; + wire ex3_br_02_add; + wire ex3_br_03_add; + wire ex3_br_04_add; + wire ex3_br_05_add; + wire ex3_br_06_add; + wire ex3_br_07_add; + wire ex3_br_08_add; + wire ex3_br_09_add; + wire ex3_br_10_add; + wire ex3_br_11_add; + wire ex3_br_12_add; + wire ex3_br_13_add; + wire ex3_br_14_add; + wire ex3_br_15_add; + wire ex3_br_16_add; + wire ex3_br_16_sub; + + (* analysis_not_referenced="true" *) + wire unused_stuff; + + wire [198:234] ex3_pp0_00; + wire [200:236] ex3_pp0_01; + wire [202:238] ex3_pp0_02; + wire [204:240] ex3_pp0_03; + wire [206:242] ex3_pp0_04; + wire [208:244] ex3_pp0_05; + wire [210:246] ex3_pp0_06; + wire [212:248] ex3_pp0_07; + wire [214:250] ex3_pp0_08; + wire [216:252] ex3_pp0_09; + wire [218:254] ex3_pp0_10; + wire [220:256] ex3_pp0_11; + wire [222:258] ex3_pp0_12; + wire [224:260] ex3_pp0_13; + wire [226:262] ex3_pp0_14; + wire [228:264] ex3_pp0_15; + wire [229:264] ex3_pp0_16; + wire [232:232] ex3_pp0_17; + + wire ex3_br_00_sign_xor; + wire ex3_br_01_sign_xor; + wire ex3_br_02_sign_xor; + wire ex3_br_03_sign_xor; + wire ex3_br_04_sign_xor; + wire ex3_br_05_sign_xor; + wire ex3_br_06_sign_xor; + wire ex3_br_07_sign_xor; + wire ex3_br_08_sign_xor; + wire ex3_br_09_sign_xor; + wire ex3_br_10_sign_xor; + wire ex3_br_11_sign_xor; + wire ex3_br_12_sign_xor; + wire ex3_br_13_sign_xor; + wire ex3_br_14_sign_xor; + wire ex3_br_15_sign_xor; + wire ex3_br_16_sign_xor; + + wire [0:7] version; + + assign unused_stuff = ex3_pp1_1s[241] | ex3_pp1_1c[238] | ex3_pp1_1c[239] | ex3_pp1_2s[247] | ex3_pp1_2c[244] | ex3_pp1_2c[245] | ex3_pp1_3s[253] | ex3_pp1_3c[250] | ex3_pp1_3c[251] | ex3_pp1_4s[259] | ex3_pp1_4c[256] | ex3_pp1_4c[257] | ex3_pp1_5c[262] | ex3_pp1_5c[263] | ex4_pp2_0s[241] | ex4_pp2_0c[236] | ex4_pp2_0c[238] | ex4_pp2_0c[239] | ex4_pp2_1s[253] | ex4_pp2_1c[248] | ex4_pp2_1c[250] | ex4_pp2_1c[251] | ex4_pp2_2c[260] | ex4_pp2_2c[262] | ex4_pp3_0s[248] | ex4_pp3_0s[250] | ex4_pp3_0s[251] | ex4_pp3_0c[240] | ex4_pp3_0c[241] | ex4_pp3_1c[254] | ex4_pp3_1c[260] | ex4_pp4_0c[252] | ex4_pp4_0c[254] | ex4_pp4_0c[260] | ex3_pp1_0c[232] | ex3_pp1_0c[233] | ex3_pp0_00[233] | ex3_pp0_01[235] | ex3_pp0_02[237] | ex3_pp0_03[239] | ex3_pp0_04[241] | ex3_pp0_05[243] | ex3_pp0_06[245] | ex3_pp0_07[247] | ex3_pp0_08[249] | ex3_pp0_09[251] | ex3_pp0_10[253] | ex3_pp0_11[255] | ex3_pp0_12[257] | ex3_pp0_13[259] | ex3_pp0_14[261] | ex3_pp0_15[263] | ex3_pp1_0s[235] | ex4_pp5_0c[195] | (|version[0:7]); + + assign version = 8'b00010000; + + //*********************************** + //** booth decoders + //*********************************** + + + tri_st_mult_boothdcd bd_00( + .i0(ex3_bd_lo_sign), //i-- + .i1(ex3_bd_lo[0]), //i-- + .i2(ex3_bd_lo[1]), //i-- + .s_neg(ex3_bd_neg[0]), //o-- + .s_x(ex3_bd_sh0[0]), //o-- + .s_x2(ex3_bd_sh1[0]) //o-- + ); + + tri_st_mult_boothdcd bd_01( + .i0(ex3_bd_lo[1]), //i-- + .i1(ex3_bd_lo[2]), //i-- + .i2(ex3_bd_lo[3]), //i-- + .s_neg(ex3_bd_neg[1]), //o-- + .s_x(ex3_bd_sh0[1]), //o-- + .s_x2(ex3_bd_sh1[1]) //o-- + ); + + tri_st_mult_boothdcd bd_02( + .i0(ex3_bd_lo[3]), //i-- + .i1(ex3_bd_lo[4]), //i-- + .i2(ex3_bd_lo[5]), //i-- + .s_neg(ex3_bd_neg[2]), //o-- + .s_x(ex3_bd_sh0[2]), //o-- + .s_x2(ex3_bd_sh1[2]) //o-- + ); + + tri_st_mult_boothdcd bd_03( + .i0(ex3_bd_lo[5]), //i-- + .i1(ex3_bd_lo[6]), //i-- + .i2(ex3_bd_lo[7]), //i-- + .s_neg(ex3_bd_neg[3]), //o-- + .s_x(ex3_bd_sh0[3]), //o-- + .s_x2(ex3_bd_sh1[3]) //o-- + ); + + tri_st_mult_boothdcd bd_04( + .i0(ex3_bd_lo[7]), //i-- + .i1(ex3_bd_lo[8]), //i-- + .i2(ex3_bd_lo[9]), //i-- + .s_neg(ex3_bd_neg[4]), //o-- + .s_x(ex3_bd_sh0[4]), //o-- + .s_x2(ex3_bd_sh1[4]) //o-- + ); + + tri_st_mult_boothdcd bd_05( + .i0(ex3_bd_lo[9]), //i-- + .i1(ex3_bd_lo[10]), //i-- + .i2(ex3_bd_lo[11]), //i-- + .s_neg(ex3_bd_neg[5]), //o-- + .s_x(ex3_bd_sh0[5]), //o-- + .s_x2(ex3_bd_sh1[5]) //o-- + ); + + tri_st_mult_boothdcd bd_06( + .i0(ex3_bd_lo[11]), //i-- + .i1(ex3_bd_lo[12]), //i-- + .i2(ex3_bd_lo[13]), //i-- + .s_neg(ex3_bd_neg[6]), //o-- + .s_x(ex3_bd_sh0[6]), //o-- + .s_x2(ex3_bd_sh1[6]) //o-- + ); + + tri_st_mult_boothdcd bd_07( + .i0(ex3_bd_lo[13]), //i-- + .i1(ex3_bd_lo[14]), //i-- + .i2(ex3_bd_lo[15]), //i-- + .s_neg(ex3_bd_neg[7]), //o-- + .s_x(ex3_bd_sh0[7]), //o-- + .s_x2(ex3_bd_sh1[7]) //o-- + ); + + tri_st_mult_boothdcd bd_08( + .i0(ex3_bd_lo[15]), //i-- + .i1(ex3_bd_lo[16]), //i-- + .i2(ex3_bd_lo[17]), //i-- + .s_neg(ex3_bd_neg[8]), //o-- + .s_x(ex3_bd_sh0[8]), //o-- + .s_x2(ex3_bd_sh1[8]) //o-- + ); + + tri_st_mult_boothdcd bd_09( + .i0(ex3_bd_lo[17]), //i-- + .i1(ex3_bd_lo[18]), //i-- + .i2(ex3_bd_lo[19]), //i-- + .s_neg(ex3_bd_neg[9]), //o-- + .s_x(ex3_bd_sh0[9]), //o-- + .s_x2(ex3_bd_sh1[9]) //o-- + ); + + tri_st_mult_boothdcd bd_10( + .i0(ex3_bd_lo[19]), //i-- + .i1(ex3_bd_lo[20]), //i-- + .i2(ex3_bd_lo[21]), //i-- + .s_neg(ex3_bd_neg[10]), //o-- + .s_x(ex3_bd_sh0[10]), //o-- + .s_x2(ex3_bd_sh1[10]) //o-- + ); + + tri_st_mult_boothdcd bd_11( + .i0(ex3_bd_lo[21]), //i-- + .i1(ex3_bd_lo[22]), //i-- + .i2(ex3_bd_lo[23]), //i-- + .s_neg(ex3_bd_neg[11]), //o-- + .s_x(ex3_bd_sh0[11]), //o-- + .s_x2(ex3_bd_sh1[11]) //o-- + ); + + tri_st_mult_boothdcd bd_12( + .i0(ex3_bd_lo[23]), //i-- + .i1(ex3_bd_lo[24]), //i-- + .i2(ex3_bd_lo[25]), //i-- + .s_neg(ex3_bd_neg[12]), //o-- + .s_x(ex3_bd_sh0[12]), //o-- + .s_x2(ex3_bd_sh1[12]) //o-- + ); + + tri_st_mult_boothdcd bd_13( + .i0(ex3_bd_lo[25]), //i-- + .i1(ex3_bd_lo[26]), //i-- + .i2(ex3_bd_lo[27]), //i-- + .s_neg(ex3_bd_neg[13]), //o-- + .s_x(ex3_bd_sh0[13]), //o-- + .s_x2(ex3_bd_sh1[13]) //o-- + ); + + tri_st_mult_boothdcd bd_14( + .i0(ex3_bd_lo[27]), //i-- + .i1(ex3_bd_lo[28]), //i-- + .i2(ex3_bd_lo[29]), //i-- + .s_neg(ex3_bd_neg[14]), //o-- + .s_x(ex3_bd_sh0[14]), //o-- + .s_x2(ex3_bd_sh1[14]) //o-- + ); + + tri_st_mult_boothdcd bd_15( + .i0(ex3_bd_lo[29]), //i-- + .i1(ex3_bd_lo[30]), //i-- + .i2(ex3_bd_lo[31]), //i-- + .s_neg(ex3_bd_neg[15]), //o-- + .s_x(ex3_bd_sh0[15]), //o-- + .s_x2(ex3_bd_sh1[15]) //o-- + ); + + tri_st_mult_boothdcd bd_16( + .i0(ex3_bd_lo[31]), //i-- + .i1(1'b0), //i-- + .i2(1'b0), //i-- + .s_neg(ex3_bd_neg[16]), //o-- + .s_x(ex3_bd_sh0[16]), //o-- + .s_x2(ex3_bd_sh1[16]) //o-- + ); + + //*********************************** + //** booth muxes + //*********************************** + + + tri_st_mult_boothrow br_00( + .s_neg(ex3_bd_neg[0]), //i-- + .s_x(ex3_bd_sh0[0]), //i-- + .s_x2(ex3_bd_sh1[0]), //i-- + .sign_bit_adj(ex3_bs_lo_sign), //i-- + .x(ex3_bs_lo[0:31]), //i-- + .q(ex3_br_00_out[0:32]), //o-- + .hot_one(ex3_hot_one[0]) //o-- + ); + + tri_st_mult_boothrow br_01( + .s_neg(ex3_bd_neg[1]), //i-- + .s_x(ex3_bd_sh0[1]), //i-- + .s_x2(ex3_bd_sh1[1]), //i-- + .sign_bit_adj(ex3_bs_lo_sign), //i-- + .x(ex3_bs_lo[0:31]), //i-- + .q(ex3_br_01_out[0:32]), //o-- + .hot_one(ex3_hot_one[1]) //o-- + ); + + tri_st_mult_boothrow br_02( + .s_neg(ex3_bd_neg[2]), //i-- + .s_x(ex3_bd_sh0[2]), //i-- + .s_x2(ex3_bd_sh1[2]), //i-- + .sign_bit_adj(ex3_bs_lo_sign), //i-- + .x(ex3_bs_lo[0:31]), //i-- + .q(ex3_br_02_out[0:32]), //o-- + .hot_one(ex3_hot_one[2]) //o-- + ); + + tri_st_mult_boothrow br_03( + .s_neg(ex3_bd_neg[3]), //i-- + .s_x(ex3_bd_sh0[3]), //i-- + .s_x2(ex3_bd_sh1[3]), //i-- + .sign_bit_adj(ex3_bs_lo_sign), //i-- + .x(ex3_bs_lo[0:31]), //i-- + .q(ex3_br_03_out[0:32]), //o-- + .hot_one(ex3_hot_one[3]) //o-- + ); + + tri_st_mult_boothrow br_04( + .s_neg(ex3_bd_neg[4]), //i-- + .s_x(ex3_bd_sh0[4]), //i-- + .s_x2(ex3_bd_sh1[4]), //i-- + .sign_bit_adj(ex3_bs_lo_sign), //i-- + .x(ex3_bs_lo[0:31]), //i-- + .q(ex3_br_04_out[0:32]), //o-- + .hot_one(ex3_hot_one[4]) //o-- + ); + + tri_st_mult_boothrow br_05( + .s_neg(ex3_bd_neg[5]), //i-- + .s_x(ex3_bd_sh0[5]), //i-- + .s_x2(ex3_bd_sh1[5]), //i-- + .sign_bit_adj(ex3_bs_lo_sign), //i-- + .x(ex3_bs_lo[0:31]), //i-- + .q(ex3_br_05_out[0:32]), //o-- + .hot_one(ex3_hot_one[5]) //o-- + ); + + tri_st_mult_boothrow br_06( + .s_neg(ex3_bd_neg[6]), //i-- + .s_x(ex3_bd_sh0[6]), //i-- + .s_x2(ex3_bd_sh1[6]), //i-- + .sign_bit_adj(ex3_bs_lo_sign), //i-- + .x(ex3_bs_lo[0:31]), //i-- + .q(ex3_br_06_out[0:32]), //o-- + .hot_one(ex3_hot_one[6]) //o-- + ); + + tri_st_mult_boothrow br_07( + .s_neg(ex3_bd_neg[7]), //i-- + .s_x(ex3_bd_sh0[7]), //i-- + .s_x2(ex3_bd_sh1[7]), //i-- + .sign_bit_adj(ex3_bs_lo_sign), //i-- + .x(ex3_bs_lo[0:31]), //i-- + .q(ex3_br_07_out[0:32]), //o-- + .hot_one(ex3_hot_one[7]) //o-- + ); + + tri_st_mult_boothrow br_08( + .s_neg(ex3_bd_neg[8]), //i-- + .s_x(ex3_bd_sh0[8]), //i-- + .s_x2(ex3_bd_sh1[8]), //i-- + .sign_bit_adj(ex3_bs_lo_sign), //i-- + .x(ex3_bs_lo[0:31]), //i-- + .q(ex3_br_08_out[0:32]), //o-- + .hot_one(ex3_hot_one[8]) //o-- + ); + + tri_st_mult_boothrow br_09( + .s_neg(ex3_bd_neg[9]), //i-- + .s_x(ex3_bd_sh0[9]), //i-- + .s_x2(ex3_bd_sh1[9]), //i-- + .sign_bit_adj(ex3_bs_lo_sign), //i-- + .x(ex3_bs_lo[0:31]), //i-- + .q(ex3_br_09_out[0:32]), //o-- + .hot_one(ex3_hot_one[9]) //o-- + ); + + tri_st_mult_boothrow br_10( + .s_neg(ex3_bd_neg[10]), //i-- + .s_x(ex3_bd_sh0[10]), //i-- + .s_x2(ex3_bd_sh1[10]), //i-- + .sign_bit_adj(ex3_bs_lo_sign), //i-- + .x(ex3_bs_lo[0:31]), //i-- + .q(ex3_br_10_out[0:32]), //o-- + .hot_one(ex3_hot_one[10]) //o-- + ); + + tri_st_mult_boothrow br_11( + .s_neg(ex3_bd_neg[11]), //i-- + .s_x(ex3_bd_sh0[11]), //i-- + .s_x2(ex3_bd_sh1[11]), //i-- + .sign_bit_adj(ex3_bs_lo_sign), //i-- + .x(ex3_bs_lo[0:31]), //i-- + .q(ex3_br_11_out[0:32]), //o-- + .hot_one(ex3_hot_one[11]) //o-- + ); + + tri_st_mult_boothrow br_12( + .s_neg(ex3_bd_neg[12]), //i-- + .s_x(ex3_bd_sh0[12]), //i-- + .s_x2(ex3_bd_sh1[12]), //i-- + .sign_bit_adj(ex3_bs_lo_sign), //i-- + .x(ex3_bs_lo[0:31]), //i-- + .q(ex3_br_12_out[0:32]), //o-- + .hot_one(ex3_hot_one[12]) //o-- + ); + + tri_st_mult_boothrow br_13( + .s_neg(ex3_bd_neg[13]), //i-- + .s_x(ex3_bd_sh0[13]), //i-- + .s_x2(ex3_bd_sh1[13]), //i-- + .sign_bit_adj(ex3_bs_lo_sign), //i-- + .x(ex3_bs_lo[0:31]), //i-- + .q(ex3_br_13_out[0:32]), //o-- + .hot_one(ex3_hot_one[13]) //o-- + ); + + tri_st_mult_boothrow br_14( + .s_neg(ex3_bd_neg[14]), //i-- + .s_x(ex3_bd_sh0[14]), //i-- + .s_x2(ex3_bd_sh1[14]), //i-- + .sign_bit_adj(ex3_bs_lo_sign), //i-- + .x(ex3_bs_lo[0:31]), //i-- + .q(ex3_br_14_out[0:32]), //o-- + .hot_one(ex3_hot_one[14]) //o-- + ); + + tri_st_mult_boothrow br_15( + .s_neg(ex3_bd_neg[15]), //i-- + .s_x(ex3_bd_sh0[15]), //i-- + .s_x2(ex3_bd_sh1[15]), //i-- + .sign_bit_adj(ex3_bs_lo_sign), //i-- + .x(ex3_bs_lo[0:31]), //i-- + .q(ex3_br_15_out[0:32]), //o-- + .hot_one(ex3_hot_one[15]) //o-- + ); + + tri_st_mult_boothrow br_16( + .s_neg(ex3_bd_neg[16]), //i-- + .s_x(ex3_bd_sh0[16]), //i-- + .s_x2(ex3_bd_sh1[16]), //i-- + .sign_bit_adj(ex3_bs_lo_sign), //i-- + .x(ex3_bs_lo[0:31]), //i-- + .q(ex3_br_16_out[0:32]), //o-- + .hot_one(ex3_hot_one[16]) //o-- + ); + + assign ex3_br_00_sign_xor = ex3_bs_lo_sign ^ ex3_bd_neg[0]; + assign ex3_br_01_sign_xor = ex3_bs_lo_sign ^ ex3_bd_neg[1]; + assign ex3_br_02_sign_xor = ex3_bs_lo_sign ^ ex3_bd_neg[2]; + assign ex3_br_03_sign_xor = ex3_bs_lo_sign ^ ex3_bd_neg[3]; + assign ex3_br_04_sign_xor = ex3_bs_lo_sign ^ ex3_bd_neg[4]; + assign ex3_br_05_sign_xor = ex3_bs_lo_sign ^ ex3_bd_neg[5]; + assign ex3_br_06_sign_xor = ex3_bs_lo_sign ^ ex3_bd_neg[6]; + assign ex3_br_07_sign_xor = ex3_bs_lo_sign ^ ex3_bd_neg[7]; + assign ex3_br_08_sign_xor = ex3_bs_lo_sign ^ ex3_bd_neg[8]; + assign ex3_br_09_sign_xor = ex3_bs_lo_sign ^ ex3_bd_neg[9]; + assign ex3_br_10_sign_xor = ex3_bs_lo_sign ^ ex3_bd_neg[10]; + assign ex3_br_11_sign_xor = ex3_bs_lo_sign ^ ex3_bd_neg[11]; + assign ex3_br_12_sign_xor = ex3_bs_lo_sign ^ ex3_bd_neg[12]; + assign ex3_br_13_sign_xor = ex3_bs_lo_sign ^ ex3_bd_neg[13]; + assign ex3_br_14_sign_xor = ex3_bs_lo_sign ^ ex3_bd_neg[14]; + assign ex3_br_15_sign_xor = ex3_bs_lo_sign ^ ex3_bd_neg[15]; + assign ex3_br_16_sign_xor = ex3_bs_lo_sign ^ ex3_bd_neg[16]; + + assign ex3_br_00_add = (~(ex3_br_00_sign_xor & (ex3_bd_sh0[0] | ex3_bd_sh1[0]))); // add + assign ex3_br_01_add = (~(ex3_br_01_sign_xor & (ex3_bd_sh0[1] | ex3_bd_sh1[1]))); // add + assign ex3_br_02_add = (~(ex3_br_02_sign_xor & (ex3_bd_sh0[2] | ex3_bd_sh1[2]))); // add + assign ex3_br_03_add = (~(ex3_br_03_sign_xor & (ex3_bd_sh0[3] | ex3_bd_sh1[3]))); // add + assign ex3_br_04_add = (~(ex3_br_04_sign_xor & (ex3_bd_sh0[4] | ex3_bd_sh1[4]))); // add + assign ex3_br_05_add = (~(ex3_br_05_sign_xor & (ex3_bd_sh0[5] | ex3_bd_sh1[5]))); // add + assign ex3_br_06_add = (~(ex3_br_06_sign_xor & (ex3_bd_sh0[6] | ex3_bd_sh1[6]))); // add + assign ex3_br_07_add = (~(ex3_br_07_sign_xor & (ex3_bd_sh0[7] | ex3_bd_sh1[7]))); // add + assign ex3_br_08_add = (~(ex3_br_08_sign_xor & (ex3_bd_sh0[8] | ex3_bd_sh1[8]))); // add + assign ex3_br_09_add = (~(ex3_br_09_sign_xor & (ex3_bd_sh0[9] | ex3_bd_sh1[9]))); // add + assign ex3_br_10_add = (~(ex3_br_10_sign_xor & (ex3_bd_sh0[10] | ex3_bd_sh1[10]))); // add + assign ex3_br_11_add = (~(ex3_br_11_sign_xor & (ex3_bd_sh0[11] | ex3_bd_sh1[11]))); // add + assign ex3_br_12_add = (~(ex3_br_12_sign_xor & (ex3_bd_sh0[12] | ex3_bd_sh1[12]))); // add + assign ex3_br_13_add = (~(ex3_br_13_sign_xor & (ex3_bd_sh0[13] | ex3_bd_sh1[13]))); // add + assign ex3_br_14_add = (~(ex3_br_14_sign_xor & (ex3_bd_sh0[14] | ex3_bd_sh1[14]))); // add + assign ex3_br_15_add = (~(ex3_br_15_sign_xor & (ex3_bd_sh0[15] | ex3_bd_sh1[15]))); // add + assign ex3_br_16_add = (~(ex3_br_16_sign_xor & (ex3_bd_sh0[16] | ex3_bd_sh1[16]))); // add + assign ex3_br_16_sub = ex3_br_16_sign_xor & (ex3_bd_sh0[16] | ex3_bd_sh1[16]); // sub + + assign ex3_pp0_00[198] = 1; + assign ex3_pp0_00[199] = ex3_br_00_add; + assign ex3_pp0_00[200:232] = ex3_br_00_out[0:32]; + assign ex3_pp0_00[233] = 0; + assign ex3_pp0_00[234] = ex3_hot_one[1]; + + assign ex3_pp0_01[200] = 1; + assign ex3_pp0_01[201] = ex3_br_01_add; + assign ex3_pp0_01[202:234] = ex3_br_01_out[0:32]; + assign ex3_pp0_01[235] = 0; + assign ex3_pp0_01[236] = ex3_hot_one[2]; + + assign ex3_pp0_02[202] = 1; + assign ex3_pp0_02[203] = ex3_br_02_add; + assign ex3_pp0_02[204:236] = ex3_br_02_out[0:32]; + assign ex3_pp0_02[237] = 0; + assign ex3_pp0_02[238] = ex3_hot_one[3]; + + assign ex3_pp0_03[204] = 1; + assign ex3_pp0_03[205] = ex3_br_03_add; + assign ex3_pp0_03[206:238] = ex3_br_03_out[0:32]; + assign ex3_pp0_03[239] = 0; + assign ex3_pp0_03[240] = ex3_hot_one[4]; + + assign ex3_pp0_04[206] = 1; + assign ex3_pp0_04[207] = ex3_br_04_add; + assign ex3_pp0_04[208:240] = ex3_br_04_out[0:32]; + assign ex3_pp0_04[241] = 0; + assign ex3_pp0_04[242] = ex3_hot_one[5]; + + assign ex3_pp0_05[208] = 1; + assign ex3_pp0_05[209] = ex3_br_05_add; + assign ex3_pp0_05[210:242] = ex3_br_05_out[0:32]; + assign ex3_pp0_05[243] = 0; + assign ex3_pp0_05[244] = ex3_hot_one[6]; + + assign ex3_pp0_06[210] = 1; + assign ex3_pp0_06[211] = ex3_br_06_add; + assign ex3_pp0_06[212:244] = ex3_br_06_out[0:32]; + assign ex3_pp0_06[245] = 0; + assign ex3_pp0_06[246] = ex3_hot_one[7]; + + assign ex3_pp0_07[212] = 1; + assign ex3_pp0_07[213] = ex3_br_07_add; + assign ex3_pp0_07[214:246] = ex3_br_07_out[0:32]; + assign ex3_pp0_07[247] = 0; + assign ex3_pp0_07[248] = ex3_hot_one[8]; + + assign ex3_pp0_08[214] = 1; + assign ex3_pp0_08[215] = ex3_br_08_add; + assign ex3_pp0_08[216:248] = ex3_br_08_out[0:32]; + assign ex3_pp0_08[249] = 0; + assign ex3_pp0_08[250] = ex3_hot_one[9]; + + assign ex3_pp0_09[216] = 1; + assign ex3_pp0_09[217] = ex3_br_09_add; + assign ex3_pp0_09[218:250] = ex3_br_09_out[0:32]; + assign ex3_pp0_09[251] = 0; + assign ex3_pp0_09[252] = ex3_hot_one[10]; + + assign ex3_pp0_10[218] = 1; + assign ex3_pp0_10[219] = ex3_br_10_add; + assign ex3_pp0_10[220:252] = ex3_br_10_out[0:32]; + assign ex3_pp0_10[253] = 0; + assign ex3_pp0_10[254] = ex3_hot_one[11]; + + assign ex3_pp0_11[220] = 1; + assign ex3_pp0_11[221] = ex3_br_11_add; + assign ex3_pp0_11[222:254] = ex3_br_11_out[0:32]; + assign ex3_pp0_11[255] = 0; + assign ex3_pp0_11[256] = ex3_hot_one[12]; + + assign ex3_pp0_12[222] = 1; + assign ex3_pp0_12[223] = ex3_br_12_add; + assign ex3_pp0_12[224:256] = ex3_br_12_out[0:32]; + assign ex3_pp0_12[257] = 0; + assign ex3_pp0_12[258] = ex3_hot_one[13]; + + assign ex3_pp0_13[224] = 1; + assign ex3_pp0_13[225] = ex3_br_13_add; + assign ex3_pp0_13[226:258] = ex3_br_13_out[0:32]; + assign ex3_pp0_13[259] = 0; + assign ex3_pp0_13[260] = ex3_hot_one[14]; + + assign ex3_pp0_14[226] = 1; + assign ex3_pp0_14[227] = ex3_br_14_add; + assign ex3_pp0_14[228:260] = ex3_br_14_out[0:32]; + assign ex3_pp0_14[261] = 0; + assign ex3_pp0_14[262] = ex3_hot_one[15]; + + assign ex3_pp0_15[228] = 1; + assign ex3_pp0_15[229] = ex3_br_15_add; + assign ex3_pp0_15[230:262] = ex3_br_15_out[0:32]; + assign ex3_pp0_15[263] = 0; + assign ex3_pp0_15[264] = ex3_hot_one[16]; + + assign ex3_pp0_16[229] = ex3_br_16_add; + assign ex3_pp0_16[230] = ex3_br_16_sub; + assign ex3_pp0_16[231] = ex3_br_16_sub; + assign ex3_pp0_16[232:264] = ex3_br_16_out[0:32]; + + assign ex3_pp0_17[232] = ex3_hot_one[0]; + + //*********************************** + //** compression level 1 + //*********************************** + //=== g1 : for i in 196 to 264 generate + //=== csa1_0: entity c_prism_csa32 generic map( btr => "MLT32_X1_A12TH" ) port map( + //=== a => ex3_pp0_17(i) ,--i-- + //=== b => ex3_pp0_00(i) ,--i-- + //=== c => ex3_pp0_01(i) ,--i-- + //=== sum => ex3_pp1_0s(i) ,--o-- + //=== car => ex3_pp1_0cex3_pp1_0c(23(i-1) );--o-- + //=== csa1_1: entity c_prism_csa32 generic map( btr => "MLT32_X1_A12TH" ) port map( + //=== a => ex3_pp0_02(i) ,--i-- + //=== b => ex3_pp0_03(i) ,--i-- + //=== c => ex3_pp0_04(i) ,--i-- + //=== sum => ex3_pp1_1s(i) ,--o-- + //=== car => ex3_pp1_1c(i-1) );--o-- + //=== csa1_2: entity c_prism_csa32 generic map( btr => "MLT32_X1_A12TH" ) port map( + //=== a => ex3_pp0_05(i) ,--i-- + //=== b => ex3_pp0_06(i) ,--i-- + //=== c => ex3_pp0_07(i) ,--i-- + //=== sum => ex3_pp1_2s(i) ,--o-- + //=== car => ex3_pp1_2c(i-1) );--o-- + //=== csa1_3: entity c_prism_csa32 generic map( btr => "MLT32_X1_A12TH" ) port map( + //=== a => ex3_pp0_08(i) ,--i-- + //=== b => ex3_pp0_09(i) ,--i-- + //=== c => ex3_pp0_10(i) ,--i-- + //=== sum => ex3_pp1_3s(i) ,--o-- + //=== car => ex3_pp1_3c(i-1) );--o-- + //=== csa1_4: entity c_prism_csa32 generic map( btr => "MLT32_X1_A12TH" ) port map( + //=== a => ex3_pp0_11(i) ,--i-- + //=== b => ex3_pp0_12(i) ,--i-- + //=== c => ex3_pp0_13(i) ,--i-- + //=== sum => ex3_pp1_4s(i) ,--o-- + //=== car => ex3_pp1_4c(i-1) );--o-- + //=== csa1_5: entity c_prism_csa32 generic map( btr => "MLT32_X1_A12TH" ) port map( + //=== a => ex3_pp0_14(i) ,--i-- + //=== b => ex3_pp0_15(i) ,--i-- + //=== c => ex3_pp0_16(i) ,--i-- + //=== sum => ex3_pp1_5s(i) ,--o-- + //=== car => ex3_pp1_5c(i-1) );--o-- + //=== end generate; + //=== ex3_pp1_0c(264) <= 0 ; + //=== ex3_pp1_1c(264) <= 0 ; + //=== ex3_pp1_2c(264) <= 0 ; + //=== ex3_pp1_3c(264) <= 0 ; + //=== ex3_pp1_4c(264) <= 0 ; + //=== ex3_pp1_5c(264) <= 0 ; + + //----- ----- + + assign ex3_pp1_0s[236] = ex3_pp0_01[236]; //pass_s + assign ex3_pp1_0s[235] = 0; //pass_none + assign ex3_pp1_0c[234] = ex3_pp0_01[234]; //pass_cs + assign ex3_pp1_0s[234] = ex3_pp0_00[234]; //pass_cs + assign ex3_pp1_0c[233] = 0; //pass_s + assign ex3_pp1_0s[233] = ex3_pp0_01[233]; //pass_s + assign ex3_pp1_0c[232] = 0; //wr_csa32 + + // MLT32_X1_A12TH + tri_csa32 csa1_0_232( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_00[232]), //i-- + .b(ex3_pp0_01[232]), //i-- + .c(ex3_pp0_17[232]), //i-- + .sum(ex3_pp1_0s[232]), //o-- + .car(ex3_pp1_0c[231]) //o-- + ); + + tri_csa22 csa1_0_231( + .a(ex3_pp0_00[231]), //i-- + .b(ex3_pp0_01[231]), //i-- + .sum(ex3_pp1_0s[231]), //o-- + .car(ex3_pp1_0c[230]) //o-- + ); + + tri_csa22 csa1_0_230( + .a(ex3_pp0_00[230]), //i-- + .b(ex3_pp0_01[230]), //i-- + .sum(ex3_pp1_0s[230]), //o-- + .car(ex3_pp1_0c[229]) //o-- + ); + + tri_csa22 csa1_0_229( + .a(ex3_pp0_00[229]), //i-- + .b(ex3_pp0_01[229]), //i-- + .sum(ex3_pp1_0s[229]), //o-- + .car(ex3_pp1_0c[228]) //o-- + ); + + tri_csa22 csa1_0_228( + .a(ex3_pp0_00[228]), //i-- + .b(ex3_pp0_01[228]), //i-- + .sum(ex3_pp1_0s[228]), //o-- + .car(ex3_pp1_0c[227]) //o-- + ); + + tri_csa22 csa1_0_227( + .a(ex3_pp0_00[227]), //i-- + .b(ex3_pp0_01[227]), //i-- + .sum(ex3_pp1_0s[227]), //o-- + .car(ex3_pp1_0c[226]) //o-- + ); + + tri_csa22 csa1_0_226( + .a(ex3_pp0_00[226]), //i-- + .b(ex3_pp0_01[226]), //i-- + .sum(ex3_pp1_0s[226]), //o-- + .car(ex3_pp1_0c[225]) //o-- + ); + + tri_csa22 csa1_0_225( + .a(ex3_pp0_00[225]), //i-- + .b(ex3_pp0_01[225]), //i-- + .sum(ex3_pp1_0s[225]), //o-- + .car(ex3_pp1_0c[224]) //o-- + ); + + tri_csa22 csa1_0_224( + .a(ex3_pp0_00[224]), //i-- + .b(ex3_pp0_01[224]), //i-- + .sum(ex3_pp1_0s[224]), //o-- + .car(ex3_pp1_0c[223]) //o-- + ); + + tri_csa22 csa1_0_223( + .a(ex3_pp0_00[223]), //i-- + .b(ex3_pp0_01[223]), //i-- + .sum(ex3_pp1_0s[223]), //o-- + .car(ex3_pp1_0c[222]) //o-- + ); + + tri_csa22 csa1_0_222( + .a(ex3_pp0_00[222]), //i-- + .b(ex3_pp0_01[222]), //i-- + .sum(ex3_pp1_0s[222]), //o-- + .car(ex3_pp1_0c[221]) //o-- + ); + + tri_csa22 csa1_0_221( + .a(ex3_pp0_00[221]), //i-- + .b(ex3_pp0_01[221]), //i-- + .sum(ex3_pp1_0s[221]), //o-- + .car(ex3_pp1_0c[220]) //o-- + ); + + tri_csa22 csa1_0_220( + .a(ex3_pp0_00[220]), //i-- + .b(ex3_pp0_01[220]), //i-- + .sum(ex3_pp1_0s[220]), //o-- + .car(ex3_pp1_0c[219]) //o-- + ); + + tri_csa22 csa1_0_219( + .a(ex3_pp0_00[219]), //i-- + .b(ex3_pp0_01[219]), //i-- + .sum(ex3_pp1_0s[219]), //o-- + .car(ex3_pp1_0c[218]) //o-- + ); + + tri_csa22 csa1_0_218( + .a(ex3_pp0_00[218]), //i-- + .b(ex3_pp0_01[218]), //i-- + .sum(ex3_pp1_0s[218]), //o-- + .car(ex3_pp1_0c[217]) //o-- + ); + + tri_csa22 csa1_0_217( + .a(ex3_pp0_00[217]), //i-- + .b(ex3_pp0_01[217]), //i-- + .sum(ex3_pp1_0s[217]), //o-- + .car(ex3_pp1_0c[216]) //o-- + ); + + tri_csa22 csa1_0_216( + .a(ex3_pp0_00[216]), //i-- + .b(ex3_pp0_01[216]), //i-- + .sum(ex3_pp1_0s[216]), //o-- + .car(ex3_pp1_0c[215]) //o-- + ); + + tri_csa22 csa1_0_215( + .a(ex3_pp0_00[215]), //i-- + .b(ex3_pp0_01[215]), //i-- + .sum(ex3_pp1_0s[215]), //o-- + .car(ex3_pp1_0c[214]) //o-- + ); + + tri_csa22 csa1_0_214( + .a(ex3_pp0_00[214]), //i-- + .b(ex3_pp0_01[214]), //i-- + .sum(ex3_pp1_0s[214]), //o-- + .car(ex3_pp1_0c[213]) //o-- + ); + + tri_csa22 csa1_0_213( + .a(ex3_pp0_00[213]), //i-- + .b(ex3_pp0_01[213]), //i-- + .sum(ex3_pp1_0s[213]), //o-- + .car(ex3_pp1_0c[212]) //o-- + ); + + tri_csa22 csa1_0_212( + .a(ex3_pp0_00[212]), //i-- + .b(ex3_pp0_01[212]), //i-- + .sum(ex3_pp1_0s[212]), //o-- + .car(ex3_pp1_0c[211]) //o-- + ); + + tri_csa22 csa1_0_211( + .a(ex3_pp0_00[211]), //i-- + .b(ex3_pp0_01[211]), //i-- + .sum(ex3_pp1_0s[211]), //o-- + .car(ex3_pp1_0c[210]) //o-- + ); + + tri_csa22 csa1_0_210( + .a(ex3_pp0_00[210]), //i-- + .b(ex3_pp0_01[210]), //i-- + .sum(ex3_pp1_0s[210]), //o-- + .car(ex3_pp1_0c[209]) //o-- + ); + + tri_csa22 csa1_0_209( + .a(ex3_pp0_00[209]), //i-- + .b(ex3_pp0_01[209]), //i-- + .sum(ex3_pp1_0s[209]), //o-- + .car(ex3_pp1_0c[208]) //o-- + ); + + tri_csa22 csa1_0_208( + .a(ex3_pp0_00[208]), //i-- + .b(ex3_pp0_01[208]), //i-- + .sum(ex3_pp1_0s[208]), //o-- + .car(ex3_pp1_0c[207]) //o-- + ); + + tri_csa22 csa1_0_207( + .a(ex3_pp0_00[207]), //i-- + .b(ex3_pp0_01[207]), //i-- + .sum(ex3_pp1_0s[207]), //o-- + .car(ex3_pp1_0c[206]) //o-- + ); + + tri_csa22 csa1_0_206( + .a(ex3_pp0_00[206]), //i-- + .b(ex3_pp0_01[206]), //i-- + .sum(ex3_pp1_0s[206]), //o-- + .car(ex3_pp1_0c[205]) //o-- + ); + + tri_csa22 csa1_0_205( + .a(ex3_pp0_00[205]), //i-- + .b(ex3_pp0_01[205]), //i-- + .sum(ex3_pp1_0s[205]), //o-- + .car(ex3_pp1_0c[204]) //o-- + ); + + tri_csa22 csa1_0_204( + .a(ex3_pp0_00[204]), //i-- + .b(ex3_pp0_01[204]), //i-- + .sum(ex3_pp1_0s[204]), //o-- + .car(ex3_pp1_0c[203]) //o-- + ); + + tri_csa22 csa1_0_203( + .a(ex3_pp0_00[203]), //i-- + .b(ex3_pp0_01[203]), //i-- + .sum(ex3_pp1_0s[203]), //o-- + .car(ex3_pp1_0c[202]) //o-- + ); + + tri_csa22 csa1_0_202( + .a(ex3_pp0_00[202]), //i-- + .b(ex3_pp0_01[202]), //i-- + .sum(ex3_pp1_0s[202]), //o-- + .car(ex3_pp1_0c[201]) //o-- + ); + + tri_csa22 csa1_0_201( + .a(ex3_pp0_00[201]), //i-- + .b(ex3_pp0_01[201]), //i-- + .sum(ex3_pp1_0s[201]), //o-- + .car(ex3_pp1_0c[200]) //o-- + ); + + tri_csa22 csa1_0_200( + .a(ex3_pp0_00[200]), //i-- + .b(ex3_pp0_01[200]), //i-- + .sum(ex3_pp1_0s[200]), //o-- + .car(ex3_pp1_0c[199]) //o-- + ); + assign ex3_pp1_0s[199] = ex3_pp0_00[199]; //pass_x_s + assign ex3_pp1_0s[198] = ex3_pp0_00[198]; //pass_s + + //----- ----- + + assign ex3_pp1_1s[242] = ex3_pp0_04[242]; //pass_s + assign ex3_pp1_1s[241] = 0; //pass_none + assign ex3_pp1_1c[240] = ex3_pp0_04[240]; //pass_cs + assign ex3_pp1_1s[240] = ex3_pp0_03[240]; //pass_cs + assign ex3_pp1_1c[239] = 0; //pass_s + assign ex3_pp1_1s[239] = ex3_pp0_04[239]; //pass_s + assign ex3_pp1_1c[238] = 0; //wr_csa32 + + + tri_csa32 csa1_1_238( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_02[238]), //i-- + .b(ex3_pp0_03[238]), //i-- + .c(ex3_pp0_04[238]), //i-- + .sum(ex3_pp1_1s[238]), //o-- + .car(ex3_pp1_1c[237]) //o-- + ); + + tri_csa22 csa1_1_237( + .a(ex3_pp0_03[237]), //i-- + .b(ex3_pp0_04[237]), //i-- + .sum(ex3_pp1_1s[237]), //o-- + .car(ex3_pp1_1c[236]) //o-- + ); + + + tri_csa32 csa1_1_236( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_02[236]), //i-- + .b(ex3_pp0_03[236]), //i-- + .c(ex3_pp0_04[236]), //i-- + .sum(ex3_pp1_1s[236]), //o-- + .car(ex3_pp1_1c[235]) //o-- + ); + + tri_csa32 csa1_1_235( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_02[235]), //i-- + .b(ex3_pp0_03[235]), //i-- + .c(ex3_pp0_04[235]), //i-- + .sum(ex3_pp1_1s[235]), //o-- + .car(ex3_pp1_1c[234]) //o-- + ); + + + tri_csa32 csa1_1_234( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_02[234]), //i-- + .b(ex3_pp0_03[234]), //i-- + .c(ex3_pp0_04[234]), //i-- + .sum(ex3_pp1_1s[234]), //o-- + .car(ex3_pp1_1c[233]) //o-- + ); + + + tri_csa32 csa1_1_233( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_02[233]), //i-- + .b(ex3_pp0_03[233]), //i-- + .c(ex3_pp0_04[233]), //i-- + .sum(ex3_pp1_1s[233]), //o-- + .car(ex3_pp1_1c[232]) //o-- + ); + + + tri_csa32 csa1_1_232( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_02[232]), //i-- + .b(ex3_pp0_03[232]), //i-- + .c(ex3_pp0_04[232]), //i-- + .sum(ex3_pp1_1s[232]), //o-- + .car(ex3_pp1_1c[231]) //o-- + ); + + + tri_csa32 csa1_1_231( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_02[231]), //i-- + .b(ex3_pp0_03[231]), //i-- + .c(ex3_pp0_04[231]), //i-- + .sum(ex3_pp1_1s[231]), //o-- + .car(ex3_pp1_1c[230]) //o-- + ); + + + tri_csa32 csa1_1_230( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_02[230]), //i-- + .b(ex3_pp0_03[230]), //i-- + .c(ex3_pp0_04[230]), //i-- + .sum(ex3_pp1_1s[230]), //o-- + .car(ex3_pp1_1c[229]) //o-- + ); + + + tri_csa32 csa1_1_229( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_02[229]), //i-- + .b(ex3_pp0_03[229]), //i-- + .c(ex3_pp0_04[229]), //i-- + .sum(ex3_pp1_1s[229]), //o-- + .car(ex3_pp1_1c[228]) //o-- + ); + + + tri_csa32 csa1_1_228( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_02[228]), //i-- + .b(ex3_pp0_03[228]), //i-- + .c(ex3_pp0_04[228]), //i-- + .sum(ex3_pp1_1s[228]), //o-- + .car(ex3_pp1_1c[227]) //o-- + ); + + + tri_csa32 csa1_1_227( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_02[227]), //i-- + .b(ex3_pp0_03[227]), //i-- + .c(ex3_pp0_04[227]), //i-- + .sum(ex3_pp1_1s[227]), //o-- + .car(ex3_pp1_1c[226]) //o-- + ); + + + tri_csa32 csa1_1_226( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_02[226]), //i-- + .b(ex3_pp0_03[226]), //i-- + .c(ex3_pp0_04[226]), //i-- + .sum(ex3_pp1_1s[226]), //o-- + .car(ex3_pp1_1c[225]) //o-- + ); + + + tri_csa32 csa1_1_225( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_02[225]), //i-- + .b(ex3_pp0_03[225]), //i-- + .c(ex3_pp0_04[225]), //i-- + .sum(ex3_pp1_1s[225]), //o-- + .car(ex3_pp1_1c[224]) //o-- + ); + + + tri_csa32 csa1_1_224( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_02[224]), //i-- + .b(ex3_pp0_03[224]), //i-- + .c(ex3_pp0_04[224]), //i-- + .sum(ex3_pp1_1s[224]), //o-- + .car(ex3_pp1_1c[223]) //o-- + ); + + + tri_csa32 csa1_1_223( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_02[223]), //i-- + .b(ex3_pp0_03[223]), //i-- + .c(ex3_pp0_04[223]), //i-- + .sum(ex3_pp1_1s[223]), //o-- + .car(ex3_pp1_1c[222]) //o-- + ); + + + tri_csa32 csa1_1_222( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_02[222]), //i-- + .b(ex3_pp0_03[222]), //i-- + .c(ex3_pp0_04[222]), //i-- + .sum(ex3_pp1_1s[222]), //o-- + .car(ex3_pp1_1c[221]) //o-- + ); + + + tri_csa32 csa1_1_221( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_02[221]), //i-- + .b(ex3_pp0_03[221]), //i-- + .c(ex3_pp0_04[221]), //i-- + .sum(ex3_pp1_1s[221]), //o-- + .car(ex3_pp1_1c[220]) //o-- + ); + + + tri_csa32 csa1_1_220( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_02[220]), //i-- + .b(ex3_pp0_03[220]), //i-- + .c(ex3_pp0_04[220]), //i-- + .sum(ex3_pp1_1s[220]), //o-- + .car(ex3_pp1_1c[219]) //o-- + ); + + + tri_csa32 csa1_1_219( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_02[219]), //i-- + .b(ex3_pp0_03[219]), //i-- + .c(ex3_pp0_04[219]), //i-- + .sum(ex3_pp1_1s[219]), //o-- + .car(ex3_pp1_1c[218]) //o-- + ); + + + tri_csa32 csa1_1_218( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_02[218]), //i-- + .b(ex3_pp0_03[218]), //i-- + .c(ex3_pp0_04[218]), //i-- + .sum(ex3_pp1_1s[218]), //o-- + .car(ex3_pp1_1c[217]) //o-- + ); + + + tri_csa32 csa1_1_217( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_02[217]), //i-- + .b(ex3_pp0_03[217]), //i-- + .c(ex3_pp0_04[217]), //i-- + .sum(ex3_pp1_1s[217]), //o-- + .car(ex3_pp1_1c[216]) //o-- + ); + + + tri_csa32 csa1_1_216( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_02[216]), //i-- + .b(ex3_pp0_03[216]), //i-- + .c(ex3_pp0_04[216]), //i-- + .sum(ex3_pp1_1s[216]), //o-- + .car(ex3_pp1_1c[215]) //o-- + ); + + + tri_csa32 csa1_1_215( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_02[215]), //i-- + .b(ex3_pp0_03[215]), //i-- + .c(ex3_pp0_04[215]), //i-- + .sum(ex3_pp1_1s[215]), //o-- + .car(ex3_pp1_1c[214]) //o-- + ); + + + tri_csa32 csa1_1_214( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_02[214]), //i-- + .b(ex3_pp0_03[214]), //i-- + .c(ex3_pp0_04[214]), //i-- + .sum(ex3_pp1_1s[214]), //o-- + .car(ex3_pp1_1c[213]) //o-- + ); + + + tri_csa32 csa1_1_213( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_02[213]), //i-- + .b(ex3_pp0_03[213]), //i-- + .c(ex3_pp0_04[213]), //i-- + .sum(ex3_pp1_1s[213]), //o-- + .car(ex3_pp1_1c[212]) //o-- + ); + + + tri_csa32 csa1_1_212( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_02[212]), //i-- + .b(ex3_pp0_03[212]), //i-- + .c(ex3_pp0_04[212]), //i-- + .sum(ex3_pp1_1s[212]), //o-- + .car(ex3_pp1_1c[211]) //o-- + ); + + + tri_csa32 csa1_1_211( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_02[211]), //i-- + .b(ex3_pp0_03[211]), //i-- + .c(ex3_pp0_04[211]), //i-- + .sum(ex3_pp1_1s[211]), //o-- + .car(ex3_pp1_1c[210]) //o-- + ); + + + tri_csa32 csa1_1_210( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_02[210]), //i-- + .b(ex3_pp0_03[210]), //i-- + .c(ex3_pp0_04[210]), //i-- + .sum(ex3_pp1_1s[210]), //o-- + .car(ex3_pp1_1c[209]) //o-- + ); + + + tri_csa32 csa1_1_209( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_02[209]), //i-- + .b(ex3_pp0_03[209]), //i-- + .c(ex3_pp0_04[209]), //i-- + .sum(ex3_pp1_1s[209]), //o-- + .car(ex3_pp1_1c[208]) //o-- + ); + + + tri_csa32 csa1_1_208( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_02[208]), //i-- + .b(ex3_pp0_03[208]), //i-- + .c(ex3_pp0_04[208]), //i-- + .sum(ex3_pp1_1s[208]), //o-- + .car(ex3_pp1_1c[207]) //o-- + ); + + + tri_csa32 csa1_1_207( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_02[207]), //i-- + .b(ex3_pp0_03[207]), //i-- + .c(ex3_pp0_04[207]), //i-- + .sum(ex3_pp1_1s[207]), //o-- + .car(ex3_pp1_1c[206]) //o-- + ); + + + tri_csa32 csa1_1_206( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_02[206]), //i-- + .b(ex3_pp0_03[206]), //i-- + .c(ex3_pp0_04[206]), //i-- + .sum(ex3_pp1_1s[206]), //o-- + .car(ex3_pp1_1c[205]) //o-- + ); + + tri_csa22 csa1_1_205( + .a(ex3_pp0_02[205]), //i-- + .b(ex3_pp0_03[205]), //i-- + .sum(ex3_pp1_1s[205]), //o-- + .car(ex3_pp1_1c[204]) //o-- + ); + + tri_csa22 csa1_1_204( + .a(ex3_pp0_02[204]), //i-- + .b(ex3_pp0_03[204]), //i-- + .sum(ex3_pp1_1s[204]), //o-- + .car(ex3_pp1_1c[203]) //o-- + ); + assign ex3_pp1_1s[203] = ex3_pp0_02[203]; //pass_x_s + assign ex3_pp1_1s[202] = ex3_pp0_02[202]; //pass_s + + //----- ----- + + assign ex3_pp1_2s[248] = ex3_pp0_07[248]; //pass_s + assign ex3_pp1_2s[247] = 0; //pass_none + assign ex3_pp1_2c[246] = ex3_pp0_07[246]; //pass_cs + assign ex3_pp1_2s[246] = ex3_pp0_06[246]; //pass_cs + assign ex3_pp1_2c[245] = 0; //pass_s + assign ex3_pp1_2s[245] = ex3_pp0_07[245]; //pass_s + assign ex3_pp1_2c[244] = 0; //wr_csa32 + + + tri_csa32 csa1_2_244( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_05[244]), //i-- + .b(ex3_pp0_06[244]), //i-- + .c(ex3_pp0_07[244]), //i-- + .sum(ex3_pp1_2s[244]), //o-- + .car(ex3_pp1_2c[243]) //o-- + ); + + tri_csa22 csa1_2_243( + .a(ex3_pp0_06[243]), //i-- + .b(ex3_pp0_07[243]), //i-- + .sum(ex3_pp1_2s[243]), //o-- + .car(ex3_pp1_2c[242]) //o-- + ); + + + tri_csa32 csa1_2_242( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_05[242]), //i-- + .b(ex3_pp0_06[242]), //i-- + .c(ex3_pp0_07[242]), //i-- + .sum(ex3_pp1_2s[242]), //o-- + .car(ex3_pp1_2c[241]) //o-- + ); + + + tri_csa32 csa1_2_241( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_05[241]), //i-- + .b(ex3_pp0_06[241]), //i-- + .c(ex3_pp0_07[241]), //i-- + .sum(ex3_pp1_2s[241]), //o-- + .car(ex3_pp1_2c[240]) //o-- + ); + + + tri_csa32 csa1_2_240( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_05[240]), //i-- + .b(ex3_pp0_06[240]), //i-- + .c(ex3_pp0_07[240]), //i-- + .sum(ex3_pp1_2s[240]), //o-- + .car(ex3_pp1_2c[239]) //o-- + ); + + + tri_csa32 csa1_2_239( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_05[239]), //i-- + .b(ex3_pp0_06[239]), //i-- + .c(ex3_pp0_07[239]), //i-- + .sum(ex3_pp1_2s[239]), //o-- + .car(ex3_pp1_2c[238]) //o-- + ); + + + tri_csa32 csa1_2_238( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_05[238]), //i-- + .b(ex3_pp0_06[238]), //i-- + .c(ex3_pp0_07[238]), //i-- + .sum(ex3_pp1_2s[238]), //o-- + .car(ex3_pp1_2c[237]) //o-- + ); + + + tri_csa32 csa1_2_237( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_05[237]), //i-- + .b(ex3_pp0_06[237]), //i-- + .c(ex3_pp0_07[237]), //i-- + .sum(ex3_pp1_2s[237]), //o-- + .car(ex3_pp1_2c[236]) //o-- + ); + + + tri_csa32 csa1_2_236( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_05[236]), //i-- + .b(ex3_pp0_06[236]), //i-- + .c(ex3_pp0_07[236]), //i-- + .sum(ex3_pp1_2s[236]), //o-- + .car(ex3_pp1_2c[235]) //o-- + ); + + + tri_csa32 csa1_2_235( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_05[235]), //i-- + .b(ex3_pp0_06[235]), //i-- + .c(ex3_pp0_07[235]), //i-- + .sum(ex3_pp1_2s[235]), //o-- + .car(ex3_pp1_2c[234]) //o-- + ); + + + tri_csa32 csa1_2_234( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_05[234]), //i-- + .b(ex3_pp0_06[234]), //i-- + .c(ex3_pp0_07[234]), //i-- + .sum(ex3_pp1_2s[234]), //o-- + .car(ex3_pp1_2c[233]) //o-- + ); + + + tri_csa32 csa1_2_233( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_05[233]), //i-- + .b(ex3_pp0_06[233]), //i-- + .c(ex3_pp0_07[233]), //i-- + .sum(ex3_pp1_2s[233]), //o-- + .car(ex3_pp1_2c[232]) //o-- + ); + + + tri_csa32 csa1_2_232( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_05[232]), //i-- + .b(ex3_pp0_06[232]), //i-- + .c(ex3_pp0_07[232]), //i-- + .sum(ex3_pp1_2s[232]), //o-- + .car(ex3_pp1_2c[231]) //o-- + ); + + + tri_csa32 csa1_2_231( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_05[231]), //i-- + .b(ex3_pp0_06[231]), //i-- + .c(ex3_pp0_07[231]), //i-- + .sum(ex3_pp1_2s[231]), //o-- + .car(ex3_pp1_2c[230]) //o-- + ); + + + tri_csa32 csa1_2_230( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_05[230]), //i-- + .b(ex3_pp0_06[230]), //i-- + .c(ex3_pp0_07[230]), //i-- + .sum(ex3_pp1_2s[230]), //o-- + .car(ex3_pp1_2c[229]) //o-- + ); + + + tri_csa32 csa1_2_229( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_05[229]), //i-- + .b(ex3_pp0_06[229]), //i-- + .c(ex3_pp0_07[229]), //i-- + .sum(ex3_pp1_2s[229]), //o-- + .car(ex3_pp1_2c[228]) //o-- + ); + + + tri_csa32 csa1_2_228( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_05[228]), //i-- + .b(ex3_pp0_06[228]), //i-- + .c(ex3_pp0_07[228]), //i-- + .sum(ex3_pp1_2s[228]), //o-- + .car(ex3_pp1_2c[227]) //o-- + ); + + + tri_csa32 csa1_2_227( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_05[227]), //i-- + .b(ex3_pp0_06[227]), //i-- + .c(ex3_pp0_07[227]), //i-- + .sum(ex3_pp1_2s[227]), //o-- + .car(ex3_pp1_2c[226]) //o-- + ); + + + tri_csa32 csa1_2_226( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_05[226]), //i-- + .b(ex3_pp0_06[226]), //i-- + .c(ex3_pp0_07[226]), //i-- + .sum(ex3_pp1_2s[226]), //o-- + .car(ex3_pp1_2c[225]) //o-- + ); + + + tri_csa32 csa1_2_225( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_05[225]), //i-- + .b(ex3_pp0_06[225]), //i-- + .c(ex3_pp0_07[225]), //i-- + .sum(ex3_pp1_2s[225]), //o-- + .car(ex3_pp1_2c[224]) //o-- + ); + + + tri_csa32 csa1_2_224( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_05[224]), //i-- + .b(ex3_pp0_06[224]), //i-- + .c(ex3_pp0_07[224]), //i-- + .sum(ex3_pp1_2s[224]), //o-- + .car(ex3_pp1_2c[223]) //o-- + ); + + + tri_csa32 csa1_2_223( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_05[223]), //i-- + .b(ex3_pp0_06[223]), //i-- + .c(ex3_pp0_07[223]), //i-- + .sum(ex3_pp1_2s[223]), //o-- + .car(ex3_pp1_2c[222]) //o-- + ); + + + tri_csa32 csa1_2_222( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_05[222]), //i-- + .b(ex3_pp0_06[222]), //i-- + .c(ex3_pp0_07[222]), //i-- + .sum(ex3_pp1_2s[222]), //o-- + .car(ex3_pp1_2c[221]) //o-- + ); + + + tri_csa32 csa1_2_221( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_05[221]), //i-- + .b(ex3_pp0_06[221]), //i-- + .c(ex3_pp0_07[221]), //i-- + .sum(ex3_pp1_2s[221]), //o-- + .car(ex3_pp1_2c[220]) //o-- + ); + + + tri_csa32 csa1_2_220( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_05[220]), //i-- + .b(ex3_pp0_06[220]), //i-- + .c(ex3_pp0_07[220]), //i-- + .sum(ex3_pp1_2s[220]), //o-- + .car(ex3_pp1_2c[219]) //o-- + ); + + + tri_csa32 csa1_2_219( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_05[219]), //i-- + .b(ex3_pp0_06[219]), //i-- + .c(ex3_pp0_07[219]), //i-- + .sum(ex3_pp1_2s[219]), //o-- + .car(ex3_pp1_2c[218]) //o-- + ); + + + tri_csa32 csa1_2_218( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_05[218]), //i-- + .b(ex3_pp0_06[218]), //i-- + .c(ex3_pp0_07[218]), //i-- + .sum(ex3_pp1_2s[218]), //o-- + .car(ex3_pp1_2c[217]) //o-- + ); + + + tri_csa32 csa1_2_217( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_05[217]), //i-- + .b(ex3_pp0_06[217]), //i-- + .c(ex3_pp0_07[217]), //i-- + .sum(ex3_pp1_2s[217]), //o-- + .car(ex3_pp1_2c[216]) //o-- + ); + + + tri_csa32 csa1_2_216( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_05[216]), //i-- + .b(ex3_pp0_06[216]), //i-- + .c(ex3_pp0_07[216]), //i-- + .sum(ex3_pp1_2s[216]), //o-- + .car(ex3_pp1_2c[215]) //o-- + ); + + + tri_csa32 csa1_2_215( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_05[215]), //i-- + .b(ex3_pp0_06[215]), //i-- + .c(ex3_pp0_07[215]), //i-- + .sum(ex3_pp1_2s[215]), //o-- + .car(ex3_pp1_2c[214]) //o-- + ); + + + tri_csa32 csa1_2_214( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_05[214]), //i-- + .b(ex3_pp0_06[214]), //i-- + .c(ex3_pp0_07[214]), //i-- + .sum(ex3_pp1_2s[214]), //o-- + .car(ex3_pp1_2c[213]) //o-- + ); + + + tri_csa32 csa1_2_213( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_05[213]), //i-- + .b(ex3_pp0_06[213]), //i-- + .c(ex3_pp0_07[213]), //i-- + .sum(ex3_pp1_2s[213]), //o-- + .car(ex3_pp1_2c[212]) //o-- + ); + + + tri_csa32 csa1_2_212( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_05[212]), //i-- + .b(ex3_pp0_06[212]), //i-- + .c(ex3_pp0_07[212]), //i-- + .sum(ex3_pp1_2s[212]), //o-- + .car(ex3_pp1_2c[211]) //o-- + ); + + tri_csa22 csa1_2_211( + .a(ex3_pp0_05[211]), //i-- + .b(ex3_pp0_06[211]), //i-- + .sum(ex3_pp1_2s[211]), //o-- + .car(ex3_pp1_2c[210]) //o-- + ); + + tri_csa22 csa1_2_210( + .a(ex3_pp0_05[210]), //i-- + .b(ex3_pp0_06[210]), //i-- + .sum(ex3_pp1_2s[210]), //o-- + .car(ex3_pp1_2c[209]) //o-- + ); + assign ex3_pp1_2s[209] = ex3_pp0_05[209]; //pass_x_s + assign ex3_pp1_2s[208] = ex3_pp0_05[208]; //pass_s + + //----- ----- + + assign ex3_pp1_3s[254] = ex3_pp0_10[254]; //pass_s + assign ex3_pp1_3s[253] = 0; //pass_none + assign ex3_pp1_3c[252] = ex3_pp0_10[252]; //pass_cs + assign ex3_pp1_3s[252] = ex3_pp0_09[252]; //pass_cs + assign ex3_pp1_3c[251] = 0; //pass_s + assign ex3_pp1_3s[251] = ex3_pp0_10[251]; //pass_s + assign ex3_pp1_3c[250] = 0; //wr_csa32 + + + tri_csa32 csa1_3_250( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_08[250]), //i-- + .b(ex3_pp0_09[250]), //i-- + .c(ex3_pp0_10[250]), //i-- + .sum(ex3_pp1_3s[250]), //o-- + .car(ex3_pp1_3c[249]) //o-- + ); + + tri_csa22 csa1_3_249( + .a(ex3_pp0_09[249]), //i-- + .b(ex3_pp0_10[249]), //i-- + .sum(ex3_pp1_3s[249]), //o-- + .car(ex3_pp1_3c[248]) //o-- + ); + + + tri_csa32 csa1_3_248( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_08[248]), //i-- + .b(ex3_pp0_09[248]), //i-- + .c(ex3_pp0_10[248]), //i-- + .sum(ex3_pp1_3s[248]), //o-- + .car(ex3_pp1_3c[247]) //o-- + ); + + + tri_csa32 csa1_3_247( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_08[247]), //i-- + .b(ex3_pp0_09[247]), //i-- + .c(ex3_pp0_10[247]), //i-- + .sum(ex3_pp1_3s[247]), //o-- + .car(ex3_pp1_3c[246]) //o-- + ); + + + tri_csa32 csa1_3_246( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_08[246]), //i-- + .b(ex3_pp0_09[246]), //i-- + .c(ex3_pp0_10[246]), //i-- + .sum(ex3_pp1_3s[246]), //o-- + .car(ex3_pp1_3c[245]) //o-- + ); + + + tri_csa32 csa1_3_245( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_08[245]), //i-- + .b(ex3_pp0_09[245]), //i-- + .c(ex3_pp0_10[245]), //i-- + .sum(ex3_pp1_3s[245]), //o-- + .car(ex3_pp1_3c[244]) //o-- + ); + + + tri_csa32 csa1_3_244( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_08[244]), //i-- + .b(ex3_pp0_09[244]), //i-- + .c(ex3_pp0_10[244]), //i-- + .sum(ex3_pp1_3s[244]), //o-- + .car(ex3_pp1_3c[243]) //o-- + ); + + + tri_csa32 csa1_3_243( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_08[243]), //i-- + .b(ex3_pp0_09[243]), //i-- + .c(ex3_pp0_10[243]), //i-- + .sum(ex3_pp1_3s[243]), //o-- + .car(ex3_pp1_3c[242]) //o-- + ); + + + tri_csa32 csa1_3_242( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_08[242]), //i-- + .b(ex3_pp0_09[242]), //i-- + .c(ex3_pp0_10[242]), //i-- + .sum(ex3_pp1_3s[242]), //o-- + .car(ex3_pp1_3c[241]) //o-- + ); + + + tri_csa32 csa1_3_241( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_08[241]), //i-- + .b(ex3_pp0_09[241]), //i-- + .c(ex3_pp0_10[241]), //i-- + .sum(ex3_pp1_3s[241]), //o-- + .car(ex3_pp1_3c[240]) //o-- + ); + + + tri_csa32 csa1_3_240( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_08[240]), //i-- + .b(ex3_pp0_09[240]), //i-- + .c(ex3_pp0_10[240]), //i-- + .sum(ex3_pp1_3s[240]), //o-- + .car(ex3_pp1_3c[239]) //o-- + ); + + + tri_csa32 csa1_3_239( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_08[239]), //i-- + .b(ex3_pp0_09[239]), //i-- + .c(ex3_pp0_10[239]), //i-- + .sum(ex3_pp1_3s[239]), //o-- + .car(ex3_pp1_3c[238]) //o-- + ); + + + tri_csa32 csa1_3_238( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_08[238]), //i-- + .b(ex3_pp0_09[238]), //i-- + .c(ex3_pp0_10[238]), //i-- + .sum(ex3_pp1_3s[238]), //o-- + .car(ex3_pp1_3c[237]) //o-- + ); + + + tri_csa32 csa1_3_237( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_08[237]), //i-- + .b(ex3_pp0_09[237]), //i-- + .c(ex3_pp0_10[237]), //i-- + .sum(ex3_pp1_3s[237]), //o-- + .car(ex3_pp1_3c[236]) //o-- + ); + + + tri_csa32 csa1_3_236( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_08[236]), //i-- + .b(ex3_pp0_09[236]), //i-- + .c(ex3_pp0_10[236]), //i-- + .sum(ex3_pp1_3s[236]), //o-- + .car(ex3_pp1_3c[235]) //o-- + ); + + + tri_csa32 csa1_3_235( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_08[235]), //i-- + .b(ex3_pp0_09[235]), //i-- + .c(ex3_pp0_10[235]), //i-- + .sum(ex3_pp1_3s[235]), //o-- + .car(ex3_pp1_3c[234]) //o-- + ); + + + tri_csa32 csa1_3_234( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_08[234]), //i-- + .b(ex3_pp0_09[234]), //i-- + .c(ex3_pp0_10[234]), //i-- + .sum(ex3_pp1_3s[234]), //o-- + .car(ex3_pp1_3c[233]) //o-- + ); + + + tri_csa32 csa1_3_233( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_08[233]), //i-- + .b(ex3_pp0_09[233]), //i-- + .c(ex3_pp0_10[233]), //i-- + .sum(ex3_pp1_3s[233]), //o-- + .car(ex3_pp1_3c[232]) //o-- + ); + + + tri_csa32 csa1_3_232( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_08[232]), //i-- + .b(ex3_pp0_09[232]), //i-- + .c(ex3_pp0_10[232]), //i-- + .sum(ex3_pp1_3s[232]), //o-- + .car(ex3_pp1_3c[231]) //o-- + ); + + + tri_csa32 csa1_3_231( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_08[231]), //i-- + .b(ex3_pp0_09[231]), //i-- + .c(ex3_pp0_10[231]), //i-- + .sum(ex3_pp1_3s[231]), //o-- + .car(ex3_pp1_3c[230]) //o-- + ); + + + tri_csa32 csa1_3_230( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_08[230]), //i-- + .b(ex3_pp0_09[230]), //i-- + .c(ex3_pp0_10[230]), //i-- + .sum(ex3_pp1_3s[230]), //o-- + .car(ex3_pp1_3c[229]) //o-- + ); + + + tri_csa32 csa1_3_229( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_08[229]), //i-- + .b(ex3_pp0_09[229]), //i-- + .c(ex3_pp0_10[229]), //i-- + .sum(ex3_pp1_3s[229]), //o-- + .car(ex3_pp1_3c[228]) //o-- + ); + + + tri_csa32 csa1_3_228( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_08[228]), //i-- + .b(ex3_pp0_09[228]), //i-- + .c(ex3_pp0_10[228]), //i-- + .sum(ex3_pp1_3s[228]), //o-- + .car(ex3_pp1_3c[227]) //o-- + ); + + + tri_csa32 csa1_3_227( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_08[227]), //i-- + .b(ex3_pp0_09[227]), //i-- + .c(ex3_pp0_10[227]), //i-- + .sum(ex3_pp1_3s[227]), //o-- + .car(ex3_pp1_3c[226]) //o-- + ); + + + tri_csa32 csa1_3_226( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_08[226]), //i-- + .b(ex3_pp0_09[226]), //i-- + .c(ex3_pp0_10[226]), //i-- + .sum(ex3_pp1_3s[226]), //o-- + .car(ex3_pp1_3c[225]) //o-- + ); + + + tri_csa32 csa1_3_225( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_08[225]), //i-- + .b(ex3_pp0_09[225]), //i-- + .c(ex3_pp0_10[225]), //i-- + .sum(ex3_pp1_3s[225]), //o-- + .car(ex3_pp1_3c[224]) //o-- + ); + + + tri_csa32 csa1_3_224( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_08[224]), //i-- + .b(ex3_pp0_09[224]), //i-- + .c(ex3_pp0_10[224]), //i-- + .sum(ex3_pp1_3s[224]), //o-- + .car(ex3_pp1_3c[223]) //o-- + ); + + + tri_csa32 csa1_3_223( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_08[223]), //i-- + .b(ex3_pp0_09[223]), //i-- + .c(ex3_pp0_10[223]), //i-- + .sum(ex3_pp1_3s[223]), //o-- + .car(ex3_pp1_3c[222]) //o-- + ); + + + tri_csa32 csa1_3_222( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_08[222]), //i-- + .b(ex3_pp0_09[222]), //i-- + .c(ex3_pp0_10[222]), //i-- + .sum(ex3_pp1_3s[222]), //o-- + .car(ex3_pp1_3c[221]) //o-- + ); + + + tri_csa32 csa1_3_221( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_08[221]), //i-- + .b(ex3_pp0_09[221]), //i-- + .c(ex3_pp0_10[221]), //i-- + .sum(ex3_pp1_3s[221]), //o-- + .car(ex3_pp1_3c[220]) //o-- + ); + + + tri_csa32 csa1_3_220( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_08[220]), //i-- + .b(ex3_pp0_09[220]), //i-- + .c(ex3_pp0_10[220]), //i-- + .sum(ex3_pp1_3s[220]), //o-- + .car(ex3_pp1_3c[219]) //o-- + ); + + + tri_csa32 csa1_3_219( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_08[219]), //i-- + .b(ex3_pp0_09[219]), //i-- + .c(ex3_pp0_10[219]), //i-- + .sum(ex3_pp1_3s[219]), //o-- + .car(ex3_pp1_3c[218]) //o-- + ); + + + tri_csa32 csa1_3_218( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_08[218]), //i-- + .b(ex3_pp0_09[218]), //i-- + .c(ex3_pp0_10[218]), //i-- + .sum(ex3_pp1_3s[218]), //o-- + .car(ex3_pp1_3c[217]) //o-- + ); + + tri_csa22 csa1_3_217( + .a(ex3_pp0_08[217]), //i-- + .b(ex3_pp0_09[217]), //i-- + .sum(ex3_pp1_3s[217]), //o-- + .car(ex3_pp1_3c[216]) //o-- + ); + + tri_csa22 csa1_3_216( + .a(ex3_pp0_08[216]), //i-- + .b(ex3_pp0_09[216]), //i-- + .sum(ex3_pp1_3s[216]), //o-- + .car(ex3_pp1_3c[215]) //o-- + ); + assign ex3_pp1_3s[215] = ex3_pp0_08[215]; //pass_x_s + assign ex3_pp1_3s[214] = ex3_pp0_08[214]; //pass_s + + //----- ----- + + assign ex3_pp1_4s[260] = ex3_pp0_13[260]; //pass_s + assign ex3_pp1_4s[259] = 0; //pass_none + assign ex3_pp1_4c[258] = ex3_pp0_13[258]; //pass_cs + assign ex3_pp1_4s[258] = ex3_pp0_12[258]; //pass_cs + assign ex3_pp1_4c[257] = 0; //pass_s + assign ex3_pp1_4s[257] = ex3_pp0_13[257]; //pass_s + assign ex3_pp1_4c[256] = 0; //wr_csa32 + + + tri_csa32 csa1_4_256( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_11[256]), //i-- + .b(ex3_pp0_12[256]), //i-- + .c(ex3_pp0_13[256]), //i-- + .sum(ex3_pp1_4s[256]), //o-- + .car(ex3_pp1_4c[255]) //o-- + ); + + tri_csa22 csa1_4_255( + .a(ex3_pp0_12[255]), //i-- + .b(ex3_pp0_13[255]), //i-- + .sum(ex3_pp1_4s[255]), //o-- + .car(ex3_pp1_4c[254]) //o-- + ); + + + tri_csa32 csa1_4_254( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_11[254]), //i-- + .b(ex3_pp0_12[254]), //i-- + .c(ex3_pp0_13[254]), //i-- + .sum(ex3_pp1_4s[254]), //o-- + .car(ex3_pp1_4c[253]) //o-- + ); + + + tri_csa32 csa1_4_253( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_11[253]), //i-- + .b(ex3_pp0_12[253]), //i-- + .c(ex3_pp0_13[253]), //i-- + .sum(ex3_pp1_4s[253]), //o-- + .car(ex3_pp1_4c[252]) //o-- + ); + + + tri_csa32 csa1_4_252( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_11[252]), //i-- + .b(ex3_pp0_12[252]), //i-- + .c(ex3_pp0_13[252]), //i-- + .sum(ex3_pp1_4s[252]), //o-- + .car(ex3_pp1_4c[251]) //o-- + ); + + + tri_csa32 csa1_4_251( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_11[251]), //i-- + .b(ex3_pp0_12[251]), //i-- + .c(ex3_pp0_13[251]), //i-- + .sum(ex3_pp1_4s[251]), //o-- + .car(ex3_pp1_4c[250]) //o-- + ); + + + tri_csa32 csa1_4_250( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_11[250]), //i-- + .b(ex3_pp0_12[250]), //i-- + .c(ex3_pp0_13[250]), //i-- + .sum(ex3_pp1_4s[250]), //o-- + .car(ex3_pp1_4c[249]) //o-- + ); + + + tri_csa32 csa1_4_249( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_11[249]), //i-- + .b(ex3_pp0_12[249]), //i-- + .c(ex3_pp0_13[249]), //i-- + .sum(ex3_pp1_4s[249]), //o-- + .car(ex3_pp1_4c[248]) //o-- + ); + + + tri_csa32 csa1_4_248( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_11[248]), //i-- + .b(ex3_pp0_12[248]), //i-- + .c(ex3_pp0_13[248]), //i-- + .sum(ex3_pp1_4s[248]), //o-- + .car(ex3_pp1_4c[247]) //o-- + ); + + + tri_csa32 csa1_4_247( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_11[247]), //i-- + .b(ex3_pp0_12[247]), //i-- + .c(ex3_pp0_13[247]), //i-- + .sum(ex3_pp1_4s[247]), //o-- + .car(ex3_pp1_4c[246]) //o-- + ); + + + tri_csa32 csa1_4_246( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_11[246]), //i-- + .b(ex3_pp0_12[246]), //i-- + .c(ex3_pp0_13[246]), //i-- + .sum(ex3_pp1_4s[246]), //o-- + .car(ex3_pp1_4c[245]) //o-- + ); + + + tri_csa32 csa1_4_245( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_11[245]), //i-- + .b(ex3_pp0_12[245]), //i-- + .c(ex3_pp0_13[245]), //i-- + .sum(ex3_pp1_4s[245]), //o-- + .car(ex3_pp1_4c[244]) //o-- + ); + + + tri_csa32 csa1_4_244( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_11[244]), //i-- + .b(ex3_pp0_12[244]), //i-- + .c(ex3_pp0_13[244]), //i-- + .sum(ex3_pp1_4s[244]), //o-- + .car(ex3_pp1_4c[243]) //o-- + ); + + + tri_csa32 csa1_4_243( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_11[243]), //i-- + .b(ex3_pp0_12[243]), //i-- + .c(ex3_pp0_13[243]), //i-- + .sum(ex3_pp1_4s[243]), //o-- + .car(ex3_pp1_4c[242]) //o-- + ); + + + tri_csa32 csa1_4_242( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_11[242]), //i-- + .b(ex3_pp0_12[242]), //i-- + .c(ex3_pp0_13[242]), //i-- + .sum(ex3_pp1_4s[242]), //o-- + .car(ex3_pp1_4c[241]) //o-- + ); + + + tri_csa32 csa1_4_241( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_11[241]), //i-- + .b(ex3_pp0_12[241]), //i-- + .c(ex3_pp0_13[241]), //i-- + .sum(ex3_pp1_4s[241]), //o-- + .car(ex3_pp1_4c[240]) //o-- + ); + + + tri_csa32 csa1_4_240( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_11[240]), //i-- + .b(ex3_pp0_12[240]), //i-- + .c(ex3_pp0_13[240]), //i-- + .sum(ex3_pp1_4s[240]), //o-- + .car(ex3_pp1_4c[239]) //o-- + ); + + + tri_csa32 csa1_4_239( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_11[239]), //i-- + .b(ex3_pp0_12[239]), //i-- + .c(ex3_pp0_13[239]), //i-- + .sum(ex3_pp1_4s[239]), //o-- + .car(ex3_pp1_4c[238]) //o-- + ); + + + tri_csa32 csa1_4_238( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_11[238]), //i-- + .b(ex3_pp0_12[238]), //i-- + .c(ex3_pp0_13[238]), //i-- + .sum(ex3_pp1_4s[238]), //o-- + .car(ex3_pp1_4c[237]) //o-- + ); + + + tri_csa32 csa1_4_237( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_11[237]), //i-- + .b(ex3_pp0_12[237]), //i-- + .c(ex3_pp0_13[237]), //i-- + .sum(ex3_pp1_4s[237]), //o-- + .car(ex3_pp1_4c[236]) //o-- + ); + + + tri_csa32 csa1_4_236( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_11[236]), //i-- + .b(ex3_pp0_12[236]), //i-- + .c(ex3_pp0_13[236]), //i-- + .sum(ex3_pp1_4s[236]), //o-- + .car(ex3_pp1_4c[235]) //o-- + ); + + + tri_csa32 csa1_4_235( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_11[235]), //i-- + .b(ex3_pp0_12[235]), //i-- + .c(ex3_pp0_13[235]), //i-- + .sum(ex3_pp1_4s[235]), //o-- + .car(ex3_pp1_4c[234]) //o-- + ); + + + tri_csa32 csa1_4_234( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_11[234]), //i-- + .b(ex3_pp0_12[234]), //i-- + .c(ex3_pp0_13[234]), //i-- + .sum(ex3_pp1_4s[234]), //o-- + .car(ex3_pp1_4c[233]) //o-- + ); + + + tri_csa32 csa1_4_233( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_11[233]), //i-- + .b(ex3_pp0_12[233]), //i-- + .c(ex3_pp0_13[233]), //i-- + .sum(ex3_pp1_4s[233]), //o-- + .car(ex3_pp1_4c[232]) //o-- + ); + + + tri_csa32 csa1_4_232( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_11[232]), //i-- + .b(ex3_pp0_12[232]), //i-- + .c(ex3_pp0_13[232]), //i-- + .sum(ex3_pp1_4s[232]), //o-- + .car(ex3_pp1_4c[231]) //o-- + ); + + + tri_csa32 csa1_4_231( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_11[231]), //i-- + .b(ex3_pp0_12[231]), //i-- + .c(ex3_pp0_13[231]), //i-- + .sum(ex3_pp1_4s[231]), //o-- + .car(ex3_pp1_4c[230]) //o-- + ); + + + tri_csa32 csa1_4_230( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_11[230]), //i-- + .b(ex3_pp0_12[230]), //i-- + .c(ex3_pp0_13[230]), //i-- + .sum(ex3_pp1_4s[230]), //o-- + .car(ex3_pp1_4c[229]) //o-- + ); + + + tri_csa32 csa1_4_229( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_11[229]), //i-- + .b(ex3_pp0_12[229]), //i-- + .c(ex3_pp0_13[229]), //i-- + .sum(ex3_pp1_4s[229]), //o-- + .car(ex3_pp1_4c[228]) //o-- + ); + + + tri_csa32 csa1_4_228( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_11[228]), //i-- + .b(ex3_pp0_12[228]), //i-- + .c(ex3_pp0_13[228]), //i-- + .sum(ex3_pp1_4s[228]), //o-- + .car(ex3_pp1_4c[227]) //o-- + ); + + + tri_csa32 csa1_4_227( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_11[227]), //i-- + .b(ex3_pp0_12[227]), //i-- + .c(ex3_pp0_13[227]), //i-- + .sum(ex3_pp1_4s[227]), //o-- + .car(ex3_pp1_4c[226]) //o-- + ); + + + tri_csa32 csa1_4_226( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_11[226]), //i-- + .b(ex3_pp0_12[226]), //i-- + .c(ex3_pp0_13[226]), //i-- + .sum(ex3_pp1_4s[226]), //o-- + .car(ex3_pp1_4c[225]) //o-- + ); + + + tri_csa32 csa1_4_225( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_11[225]), //i-- + .b(ex3_pp0_12[225]), //i-- + .c(ex3_pp0_13[225]), //i-- + .sum(ex3_pp1_4s[225]), //o-- + .car(ex3_pp1_4c[224]) //o-- + ); + + + tri_csa32 csa1_4_224( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_11[224]), //i-- + .b(ex3_pp0_12[224]), //i-- + .c(ex3_pp0_13[224]), //i-- + .sum(ex3_pp1_4s[224]), //o-- + .car(ex3_pp1_4c[223]) //o-- + ); + + tri_csa22 csa1_4_223( + .a(ex3_pp0_11[223]), //i-- + .b(ex3_pp0_12[223]), //i-- + .sum(ex3_pp1_4s[223]), //o-- + .car(ex3_pp1_4c[222]) //o-- + ); + + tri_csa22 csa1_4_222( + .a(ex3_pp0_11[222]), //i-- + .b(ex3_pp0_12[222]), //i-- + .sum(ex3_pp1_4s[222]), //o-- + .car(ex3_pp1_4c[221]) //o-- + ); + assign ex3_pp1_4s[221] = ex3_pp0_11[221]; //pass_x_s + assign ex3_pp1_4s[220] = ex3_pp0_11[220]; //pass_s + + //----- ----- + + assign ex3_pp1_5c[264] = ex3_pp0_16[264]; //pass_cs + assign ex3_pp1_5s[264] = ex3_pp0_15[264]; //pass_cs + assign ex3_pp1_5c[263] = 0; //pass_s + assign ex3_pp1_5s[263] = ex3_pp0_16[263]; //pass_s + assign ex3_pp1_5c[262] = 0; //wr_csa32 + + + tri_csa32 csa1_5_262( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_14[262]), //i-- + .b(ex3_pp0_15[262]), //i-- + .c(ex3_pp0_16[262]), //i-- + .sum(ex3_pp1_5s[262]), //o-- + .car(ex3_pp1_5c[261]) //o-- + ); + + tri_csa22 csa1_5_261( + .a(ex3_pp0_15[261]), //i-- + .b(ex3_pp0_16[261]), //i-- + .sum(ex3_pp1_5s[261]), //o-- + .car(ex3_pp1_5c[260]) //o-- + ); + + tri_csa32 csa1_5_260( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_14[260]), //i-- + .b(ex3_pp0_15[260]), //i-- + .c(ex3_pp0_16[260]), //i-- + .sum(ex3_pp1_5s[260]), //o-- + .car(ex3_pp1_5c[259]) //o-- + ); + + + tri_csa32 csa1_5_259( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_14[259]), //i-- + .b(ex3_pp0_15[259]), //i-- + .c(ex3_pp0_16[259]), //i-- + .sum(ex3_pp1_5s[259]), //o-- + .car(ex3_pp1_5c[258]) //o-- + ); + + + tri_csa32 csa1_5_258( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_14[258]), //i-- + .b(ex3_pp0_15[258]), //i-- + .c(ex3_pp0_16[258]), //i-- + .sum(ex3_pp1_5s[258]), //o-- + .car(ex3_pp1_5c[257]) //o-- + ); + + + tri_csa32 csa1_5_257( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_14[257]), //i-- + .b(ex3_pp0_15[257]), //i-- + .c(ex3_pp0_16[257]), //i-- + .sum(ex3_pp1_5s[257]), //o-- + .car(ex3_pp1_5c[256]) //o-- + ); + + + tri_csa32 csa1_5_256( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_14[256]), //i-- + .b(ex3_pp0_15[256]), //i-- + .c(ex3_pp0_16[256]), //i-- + .sum(ex3_pp1_5s[256]), //o-- + .car(ex3_pp1_5c[255]) //o-- + ); + + + tri_csa32 csa1_5_255( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_14[255]), //i-- + .b(ex3_pp0_15[255]), //i-- + .c(ex3_pp0_16[255]), //i-- + .sum(ex3_pp1_5s[255]), //o-- + .car(ex3_pp1_5c[254]) //o-- + ); + + + tri_csa32 csa1_5_254( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_14[254]), //i-- + .b(ex3_pp0_15[254]), //i-- + .c(ex3_pp0_16[254]), //i-- + .sum(ex3_pp1_5s[254]), //o-- + .car(ex3_pp1_5c[253]) //o-- + ); + + + tri_csa32 csa1_5_253( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_14[253]), //i-- + .b(ex3_pp0_15[253]), //i-- + .c(ex3_pp0_16[253]), //i-- + .sum(ex3_pp1_5s[253]), //o-- + .car(ex3_pp1_5c[252]) //o-- + ); + + + tri_csa32 csa1_5_252( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_14[252]), //i-- + .b(ex3_pp0_15[252]), //i-- + .c(ex3_pp0_16[252]), //i-- + .sum(ex3_pp1_5s[252]), //o-- + .car(ex3_pp1_5c[251]) //o-- + ); + + + tri_csa32 csa1_5_251( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_14[251]), //i-- + .b(ex3_pp0_15[251]), //i-- + .c(ex3_pp0_16[251]), //i-- + .sum(ex3_pp1_5s[251]), //o-- + .car(ex3_pp1_5c[250]) //o-- + ); + + + tri_csa32 csa1_5_250( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_14[250]), //i-- + .b(ex3_pp0_15[250]), //i-- + .c(ex3_pp0_16[250]), //i-- + .sum(ex3_pp1_5s[250]), //o-- + .car(ex3_pp1_5c[249]) //o-- + ); + + + tri_csa32 csa1_5_249( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_14[249]), //i-- + .b(ex3_pp0_15[249]), //i-- + .c(ex3_pp0_16[249]), //i-- + .sum(ex3_pp1_5s[249]), //o-- + .car(ex3_pp1_5c[248]) //o-- + ); + + + tri_csa32 csa1_5_248( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_14[248]), //i-- + .b(ex3_pp0_15[248]), //i-- + .c(ex3_pp0_16[248]), //i-- + .sum(ex3_pp1_5s[248]), //o-- + .car(ex3_pp1_5c[247]) //o-- + ); + + + tri_csa32 csa1_5_247( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_14[247]), //i-- + .b(ex3_pp0_15[247]), //i-- + .c(ex3_pp0_16[247]), //i-- + .sum(ex3_pp1_5s[247]), //o-- + .car(ex3_pp1_5c[246]) //o-- + ); + + + tri_csa32 csa1_5_246( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_14[246]), //i-- + .b(ex3_pp0_15[246]), //i-- + .c(ex3_pp0_16[246]), //i-- + .sum(ex3_pp1_5s[246]), //o-- + .car(ex3_pp1_5c[245]) //o-- + ); + + + tri_csa32 csa1_5_245( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_14[245]), //i-- + .b(ex3_pp0_15[245]), //i-- + .c(ex3_pp0_16[245]), //i-- + .sum(ex3_pp1_5s[245]), //o-- + .car(ex3_pp1_5c[244]) //o-- + ); + + + tri_csa32 csa1_5_244( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_14[244]), //i-- + .b(ex3_pp0_15[244]), //i-- + .c(ex3_pp0_16[244]), //i-- + .sum(ex3_pp1_5s[244]), //o-- + .car(ex3_pp1_5c[243]) //o-- + ); + + + tri_csa32 csa1_5_243( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_14[243]), //i-- + .b(ex3_pp0_15[243]), //i-- + .c(ex3_pp0_16[243]), //i-- + .sum(ex3_pp1_5s[243]), //o-- + .car(ex3_pp1_5c[242]) //o-- + ); + + + tri_csa32 csa1_5_242( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_14[242]), //i-- + .b(ex3_pp0_15[242]), //i-- + .c(ex3_pp0_16[242]), //i-- + .sum(ex3_pp1_5s[242]), //o-- + .car(ex3_pp1_5c[241]) //o-- + ); + + + tri_csa32 csa1_5_241( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_14[241]), //i-- + .b(ex3_pp0_15[241]), //i-- + .c(ex3_pp0_16[241]), //i-- + .sum(ex3_pp1_5s[241]), //o-- + .car(ex3_pp1_5c[240]) //o-- + ); + + + tri_csa32 csa1_5_240( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_14[240]), //i-- + .b(ex3_pp0_15[240]), //i-- + .c(ex3_pp0_16[240]), //i-- + .sum(ex3_pp1_5s[240]), //o-- + .car(ex3_pp1_5c[239]) //o-- + ); + + + tri_csa32 csa1_5_239( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_14[239]), //i-- + .b(ex3_pp0_15[239]), //i-- + .c(ex3_pp0_16[239]), //i-- + .sum(ex3_pp1_5s[239]), //o-- + .car(ex3_pp1_5c[238]) //o-- + ); + + + tri_csa32 csa1_5_238( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_14[238]), //i-- + .b(ex3_pp0_15[238]), //i-- + .c(ex3_pp0_16[238]), //i-- + .sum(ex3_pp1_5s[238]), //o-- + .car(ex3_pp1_5c[237]) //o-- + ); + + + tri_csa32 csa1_5_237( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_14[237]), //i-- + .b(ex3_pp0_15[237]), //i-- + .c(ex3_pp0_16[237]), //i-- + .sum(ex3_pp1_5s[237]), //o-- + .car(ex3_pp1_5c[236]) //o-- + ); + + + tri_csa32 csa1_5_236( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_14[236]), //i-- + .b(ex3_pp0_15[236]), //i-- + .c(ex3_pp0_16[236]), //i-- + .sum(ex3_pp1_5s[236]), //o-- + .car(ex3_pp1_5c[235]) //o-- + ); + + + tri_csa32 csa1_5_235( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_14[235]), //i-- + .b(ex3_pp0_15[235]), //i-- + .c(ex3_pp0_16[235]), //i-- + .sum(ex3_pp1_5s[235]), //o-- + .car(ex3_pp1_5c[234]) //o-- + ); + + + tri_csa32 csa1_5_234( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_14[234]), //i-- + .b(ex3_pp0_15[234]), //i-- + .c(ex3_pp0_16[234]), //i-- + .sum(ex3_pp1_5s[234]), //o-- + .car(ex3_pp1_5c[233]) //o-- + ); + + + tri_csa32 csa1_5_233( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_14[233]), //i-- + .b(ex3_pp0_15[233]), //i-- + .c(ex3_pp0_16[233]), //i-- + .sum(ex3_pp1_5s[233]), //o-- + .car(ex3_pp1_5c[232]) //o-- + ); + + + tri_csa32 csa1_5_232( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_14[232]), //i-- + .b(ex3_pp0_15[232]), //i-- + .c(ex3_pp0_16[232]), //i-- + .sum(ex3_pp1_5s[232]), //o-- + .car(ex3_pp1_5c[231]) //o-- + ); + + + tri_csa32 csa1_5_231( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_14[231]), //i-- + .b(ex3_pp0_15[231]), //i-- + .c(ex3_pp0_16[231]), //i-- + .sum(ex3_pp1_5s[231]), //o-- + .car(ex3_pp1_5c[230]) //o-- + ); + + + tri_csa32 csa1_5_230( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_14[230]), //i-- + .b(ex3_pp0_15[230]), //i-- + .c(ex3_pp0_16[230]), //i-- + .sum(ex3_pp1_5s[230]), //o-- + .car(ex3_pp1_5c[229]) //o-- + ); + + + tri_csa32 csa1_5_229( + .vd(vdd), + .gd(gnd), + .a(ex3_pp0_14[229]), //i-- + .b(ex3_pp0_15[229]), //i-- + .c(ex3_pp0_16[229]), //i-- + .sum(ex3_pp1_5s[229]), //o-- + .car(ex3_pp1_5c[228]) //o-- + ); + + tri_csa22 csa1_5_228( + .a(ex3_pp0_14[228]), //i-- + .b(ex3_pp0_15[228]), //i-- + .sum(ex3_pp1_5s[228]), //o-- + .car(ex3_pp1_5c[227]) //o-- + ); + assign ex3_pp1_5s[227] = ex3_pp0_14[227]; //pass_x_s + assign ex3_pp1_5s[226] = ex3_pp0_14[226]; //pass_s + + //*********************************** + //** compression level 2 + //*********************************** + + // g2 : for i in 196 to 264 generate + + // csa2_0: entity c_prism_csa42 generic map( btr => "MLT42_X1_A12TH" ) port map( + // a => ex3_pp1_0s(i) ,--i-- + // b => ex3_pp1_0c(i) ,--i-- + // c => ex3_pp1_1s(i) ,--i-- + // d => ex3_pp1_1c(i) ,--i-- + // ki => ex3_pp2_0k(i) ,--i-- + // ko => ex3_pp2_0k(i - 1) ,--o-- + // sum => ex3_pp2_0s(i) ,--o-- + // car => ex3_pp2_0c(i - 1) );--o-- + // + // csa2_1: entity c_prism_csa42 generic map( btr => "MLT42_X1_A12TH" ) port map( + // a => ex3_pp1_2s(i) ,--i-- + // b => ex3_pp1_2c(i) ,--i-- + // c => ex3_pp1_3s(i) ,--i-- + // d => ex3_pp1_3c(i) ,--i-- + // ki => ex3_pp2_1k(i) ,--i-- + // ko => ex3_pp2_1k(i - 1) ,--o-- + // sum => ex3_pp2_1s(i) ,--o-- + // car => ex3_pp2_1c(i - 1) );--o-- + // + // csa2_2: entity c_prism_csa42 generic map( btr => "MLT42_X1_A12TH" ) port map( + // a => ex3_pp1_4s(i) ,--i-- + // b => ex3_pp1_4c(i) ,--i-- + // c => ex3_pp1_5s(i) ,--i-- + // d => ex3_pp1_5c(i) ,--i-- + // ki => ex3_pp2_2k(i) ,--i-- + // ko => ex3_pp2_2k(i - 1) ,--o-- + // sum => ex3_pp2_2s(i) ,--o-- + // car => ex3_pp2_2c(i - 1) );--o-- + // + // end generate; + + //----- ----- + + assign ex3_pp2_0s[242] = ex3_pp1_1s[242]; //pass_s + assign ex3_pp2_0s[241] = 0; //pass_none + assign ex3_pp2_0c[240] = ex3_pp1_1s[240]; //pass_cs + assign ex3_pp2_0s[240] = ex3_pp1_1c[240]; //pass_cs + assign ex3_pp2_0c[239] = 0; //pass_s + assign ex3_pp2_0s[239] = ex3_pp1_1s[239]; //pass_s + assign ex3_pp2_0c[238] = 0; //pass_s + assign ex3_pp2_0s[238] = ex3_pp1_1s[238]; //pass_s + assign ex3_pp2_0c[237] = ex3_pp1_1s[237]; //pass_cs + assign ex3_pp2_0s[237] = ex3_pp1_1c[237]; //pass_cs + assign ex3_pp2_0c[236] = 0; //wr_csa32 + + + tri_csa32 csa2_0_236( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_0s[236]), //i-- + .b(ex3_pp1_1c[236]), //i-- + .c(ex3_pp1_1s[236]), //i-- + .sum(ex3_pp2_0s[236]), //o-- + .car(ex3_pp2_0c[235]) //o-- + ); + + tri_csa22 csa2_0_235( + .a(ex3_pp1_1c[235]), //i-- + .b(ex3_pp1_1s[235]), //i-- + .sum(ex3_pp2_0s[235]), //o-- + .car(ex3_pp2_0c[234]) //o-- + ); + assign ex3_pp2_0k[234] = 0; //start_k + + // MLT42_X1_A12TH + tri_csa42 csa2_0_234( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_0c[234]), //i-- + .b(ex3_pp1_0s[234]), //i-- + .c(ex3_pp1_1c[234]), //i-- + .d(ex3_pp1_1s[234]), //i-- + .ki(ex3_pp2_0k[234]), //i-- + .ko(ex3_pp2_0k[233]), //o-- + .sum(ex3_pp2_0s[234]), //o-- + .car(ex3_pp2_0c[233]) //o-- + ); + + + tri_csa42 csa2_0_233( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_0s[233]), //i-- + .b(ex3_pp1_1c[233]), //i-- + .c(ex3_pp1_1s[233]), //i-- + .d(1'b0), //i-- + .ki(ex3_pp2_0k[233]), //i-- + .ko(ex3_pp2_0k[232]), //o-- + .sum(ex3_pp2_0s[233]), //o-- + .car(ex3_pp2_0c[232]) //o-- + ); + + + tri_csa42 csa2_0_232( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_0s[232]), //i-- + .b(ex3_pp1_1c[232]), //i-- + .c(ex3_pp1_1s[232]), //i-- + .d(1'b0), //i-- + .ki(ex3_pp2_0k[232]), //i-- + .ko(ex3_pp2_0k[231]), //o-- + .sum(ex3_pp2_0s[232]), //o-- + .car(ex3_pp2_0c[231]) //o-- + ); + + + tri_csa42 csa2_0_231( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_0c[231]), //i-- + .b(ex3_pp1_0s[231]), //i-- + .c(ex3_pp1_1c[231]), //i-- + .d(ex3_pp1_1s[231]), //i-- + .ki(ex3_pp2_0k[231]), //i-- + .ko(ex3_pp2_0k[230]), //o-- + .sum(ex3_pp2_0s[231]), //o-- + .car(ex3_pp2_0c[230]) //o-- + ); + + + tri_csa42 csa2_0_230( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_0c[230]), //i-- + .b(ex3_pp1_0s[230]), //i-- + .c(ex3_pp1_1c[230]), //i-- + .d(ex3_pp1_1s[230]), //i-- + .ki(ex3_pp2_0k[230]), //i-- + .ko(ex3_pp2_0k[229]), //o-- + .sum(ex3_pp2_0s[230]), //o-- + .car(ex3_pp2_0c[229]) //o-- + ); + + + tri_csa42 csa2_0_229( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_0c[229]), //i-- + .b(ex3_pp1_0s[229]), //i-- + .c(ex3_pp1_1c[229]), //i-- + .d(ex3_pp1_1s[229]), //i-- + .ki(ex3_pp2_0k[229]), //i-- + .ko(ex3_pp2_0k[228]), //o-- + .sum(ex3_pp2_0s[229]), //o-- + .car(ex3_pp2_0c[228]) //o-- + ); + + + tri_csa42 csa2_0_228( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_0c[228]), //i-- + .b(ex3_pp1_0s[228]), //i-- + .c(ex3_pp1_1c[228]), //i-- + .d(ex3_pp1_1s[228]), //i-- + .ki(ex3_pp2_0k[228]), //i-- + .ko(ex3_pp2_0k[227]), //o-- + .sum(ex3_pp2_0s[228]), //o-- + .car(ex3_pp2_0c[227]) //o-- + ); + + + tri_csa42 csa2_0_227( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_0c[227]), //i-- + .b(ex3_pp1_0s[227]), //i-- + .c(ex3_pp1_1c[227]), //i-- + .d(ex3_pp1_1s[227]), //i-- + .ki(ex3_pp2_0k[227]), //i-- + .ko(ex3_pp2_0k[226]), //o-- + .sum(ex3_pp2_0s[227]), //o-- + .car(ex3_pp2_0c[226]) //o-- + ); + + + tri_csa42 csa2_0_226( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_0c[226]), //i-- + .b(ex3_pp1_0s[226]), //i-- + .c(ex3_pp1_1c[226]), //i-- + .d(ex3_pp1_1s[226]), //i-- + .ki(ex3_pp2_0k[226]), //i-- + .ko(ex3_pp2_0k[225]), //o-- + .sum(ex3_pp2_0s[226]), //o-- + .car(ex3_pp2_0c[225]) //o-- + ); + + + tri_csa42 csa2_0_225( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_0c[225]), //i-- + .b(ex3_pp1_0s[225]), //i-- + .c(ex3_pp1_1c[225]), //i-- + .d(ex3_pp1_1s[225]), //i-- + .ki(ex3_pp2_0k[225]), //i-- + .ko(ex3_pp2_0k[224]), //o-- + .sum(ex3_pp2_0s[225]), //o-- + .car(ex3_pp2_0c[224]) //o-- + ); + + + tri_csa42 csa2_0_224( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_0c[224]), //i-- + .b(ex3_pp1_0s[224]), //i-- + .c(ex3_pp1_1c[224]), //i-- + .d(ex3_pp1_1s[224]), //i-- + .ki(ex3_pp2_0k[224]), //i-- + .ko(ex3_pp2_0k[223]), //o-- + .sum(ex3_pp2_0s[224]), //o-- + .car(ex3_pp2_0c[223]) //o-- + ); + + + tri_csa42 csa2_0_223( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_0c[223]), //i-- + .b(ex3_pp1_0s[223]), //i-- + .c(ex3_pp1_1c[223]), //i-- + .d(ex3_pp1_1s[223]), //i-- + .ki(ex3_pp2_0k[223]), //i-- + .ko(ex3_pp2_0k[222]), //o-- + .sum(ex3_pp2_0s[223]), //o-- + .car(ex3_pp2_0c[222]) //o-- + ); + + + tri_csa42 csa2_0_222( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_0c[222]), //i-- + .b(ex3_pp1_0s[222]), //i-- + .c(ex3_pp1_1c[222]), //i-- + .d(ex3_pp1_1s[222]), //i-- + .ki(ex3_pp2_0k[222]), //i-- + .ko(ex3_pp2_0k[221]), //o-- + .sum(ex3_pp2_0s[222]), //o-- + .car(ex3_pp2_0c[221]) //o-- + ); + + + tri_csa42 csa2_0_221( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_0c[221]), //i-- + .b(ex3_pp1_0s[221]), //i-- + .c(ex3_pp1_1c[221]), //i-- + .d(ex3_pp1_1s[221]), //i-- + .ki(ex3_pp2_0k[221]), //i-- + .ko(ex3_pp2_0k[220]), //o-- + .sum(ex3_pp2_0s[221]), //o-- + .car(ex3_pp2_0c[220]) //o-- + ); + + + tri_csa42 csa2_0_220( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_0c[220]), //i-- + .b(ex3_pp1_0s[220]), //i-- + .c(ex3_pp1_1c[220]), //i-- + .d(ex3_pp1_1s[220]), //i-- + .ki(ex3_pp2_0k[220]), //i-- + .ko(ex3_pp2_0k[219]), //o-- + .sum(ex3_pp2_0s[220]), //o-- + .car(ex3_pp2_0c[219]) //o-- + ); + + + tri_csa42 csa2_0_219( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_0c[219]), //i-- + .b(ex3_pp1_0s[219]), //i-- + .c(ex3_pp1_1c[219]), //i-- + .d(ex3_pp1_1s[219]), //i-- + .ki(ex3_pp2_0k[219]), //i-- + .ko(ex3_pp2_0k[218]), //o-- + .sum(ex3_pp2_0s[219]), //o-- + .car(ex3_pp2_0c[218]) //o-- + ); + + + tri_csa42 csa2_0_218( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_0c[218]), //i-- + .b(ex3_pp1_0s[218]), //i-- + .c(ex3_pp1_1c[218]), //i-- + .d(ex3_pp1_1s[218]), //i-- + .ki(ex3_pp2_0k[218]), //i-- + .ko(ex3_pp2_0k[217]), //o-- + .sum(ex3_pp2_0s[218]), //o-- + .car(ex3_pp2_0c[217]) //o-- + ); + + + tri_csa42 csa2_0_217( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_0c[217]), //i-- + .b(ex3_pp1_0s[217]), //i-- + .c(ex3_pp1_1c[217]), //i-- + .d(ex3_pp1_1s[217]), //i-- + .ki(ex3_pp2_0k[217]), //i-- + .ko(ex3_pp2_0k[216]), //o-- + .sum(ex3_pp2_0s[217]), //o-- + .car(ex3_pp2_0c[216]) //o-- + ); + + + tri_csa42 csa2_0_216( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_0c[216]), //i-- + .b(ex3_pp1_0s[216]), //i-- + .c(ex3_pp1_1c[216]), //i-- + .d(ex3_pp1_1s[216]), //i-- + .ki(ex3_pp2_0k[216]), //i-- + .ko(ex3_pp2_0k[215]), //o-- + .sum(ex3_pp2_0s[216]), //o-- + .car(ex3_pp2_0c[215]) //o-- + ); + + + tri_csa42 csa2_0_215( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_0c[215]), //i-- + .b(ex3_pp1_0s[215]), //i-- + .c(ex3_pp1_1c[215]), //i-- + .d(ex3_pp1_1s[215]), //i-- + .ki(ex3_pp2_0k[215]), //i-- + .ko(ex3_pp2_0k[214]), //o-- + .sum(ex3_pp2_0s[215]), //o-- + .car(ex3_pp2_0c[214]) //o-- + ); + + + tri_csa42 csa2_0_214( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_0c[214]), //i-- + .b(ex3_pp1_0s[214]), //i-- + .c(ex3_pp1_1c[214]), //i-- + .d(ex3_pp1_1s[214]), //i-- + .ki(ex3_pp2_0k[214]), //i-- + .ko(ex3_pp2_0k[213]), //o-- + .sum(ex3_pp2_0s[214]), //o-- + .car(ex3_pp2_0c[213]) //o-- + ); + + + tri_csa42 csa2_0_213( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_0c[213]), //i-- + .b(ex3_pp1_0s[213]), //i-- + .c(ex3_pp1_1c[213]), //i-- + .d(ex3_pp1_1s[213]), //i-- + .ki(ex3_pp2_0k[213]), //i-- + .ko(ex3_pp2_0k[212]), //o-- + .sum(ex3_pp2_0s[213]), //o-- + .car(ex3_pp2_0c[212]) //o-- + ); + + + tri_csa42 csa2_0_212( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_0c[212]), //i-- + .b(ex3_pp1_0s[212]), //i-- + .c(ex3_pp1_1c[212]), //i-- + .d(ex3_pp1_1s[212]), //i-- + .ki(ex3_pp2_0k[212]), //i-- + .ko(ex3_pp2_0k[211]), //o-- + .sum(ex3_pp2_0s[212]), //o-- + .car(ex3_pp2_0c[211]) //o-- + ); + + + tri_csa42 csa2_0_211( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_0c[211]), //i-- + .b(ex3_pp1_0s[211]), //i-- + .c(ex3_pp1_1c[211]), //i-- + .d(ex3_pp1_1s[211]), //i-- + .ki(ex3_pp2_0k[211]), //i-- + .ko(ex3_pp2_0k[210]), //o-- + .sum(ex3_pp2_0s[211]), //o-- + .car(ex3_pp2_0c[210]) //o-- + ); + + + tri_csa42 csa2_0_210( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_0c[210]), //i-- + .b(ex3_pp1_0s[210]), //i-- + .c(ex3_pp1_1c[210]), //i-- + .d(ex3_pp1_1s[210]), //i-- + .ki(ex3_pp2_0k[210]), //i-- + .ko(ex3_pp2_0k[209]), //o-- + .sum(ex3_pp2_0s[210]), //o-- + .car(ex3_pp2_0c[209]) //o-- + ); + + + tri_csa42 csa2_0_209( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_0c[209]), //i-- + .b(ex3_pp1_0s[209]), //i-- + .c(ex3_pp1_1c[209]), //i-- + .d(ex3_pp1_1s[209]), //i-- + .ki(ex3_pp2_0k[209]), //i-- + .ko(ex3_pp2_0k[208]), //o-- + .sum(ex3_pp2_0s[209]), //o-- + .car(ex3_pp2_0c[208]) //o-- + ); + + + tri_csa42 csa2_0_208( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_0c[208]), //i-- + .b(ex3_pp1_0s[208]), //i-- + .c(ex3_pp1_1c[208]), //i-- + .d(ex3_pp1_1s[208]), //i-- + .ki(ex3_pp2_0k[208]), //i-- + .ko(ex3_pp2_0k[207]), //o-- + .sum(ex3_pp2_0s[208]), //o-- + .car(ex3_pp2_0c[207]) //o-- + ); + + + tri_csa42 csa2_0_207( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_0c[207]), //i-- + .b(ex3_pp1_0s[207]), //i-- + .c(ex3_pp1_1c[207]), //i-- + .d(ex3_pp1_1s[207]), //i-- + .ki(ex3_pp2_0k[207]), //i-- + .ko(ex3_pp2_0k[206]), //o-- + .sum(ex3_pp2_0s[207]), //o-- + .car(ex3_pp2_0c[206]) //o-- + ); + + + tri_csa42 csa2_0_206( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_0c[206]), //i-- + .b(ex3_pp1_0s[206]), //i-- + .c(ex3_pp1_1c[206]), //i-- + .d(ex3_pp1_1s[206]), //i-- + .ki(ex3_pp2_0k[206]), //i-- + .ko(ex3_pp2_0k[205]), //o-- + .sum(ex3_pp2_0s[206]), //o-- + .car(ex3_pp2_0c[205]) //o-- + ); + + + tri_csa42 csa2_0_205( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_0c[205]), //i-- + .b(ex3_pp1_0s[205]), //i-- + .c(ex3_pp1_1c[205]), //i-- + .d(ex3_pp1_1s[205]), //i-- + .ki(ex3_pp2_0k[205]), //i-- + .ko(ex3_pp2_0k[204]), //o-- + .sum(ex3_pp2_0s[205]), //o-- + .car(ex3_pp2_0c[204]) //o-- + ); + + + tri_csa42 csa2_0_204( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_0c[204]), //i-- + .b(ex3_pp1_0s[204]), //i-- + .c(ex3_pp1_1c[204]), //i-- + .d(ex3_pp1_1s[204]), //i-- + .ki(ex3_pp2_0k[204]), //i-- + .ko(ex3_pp2_0k[203]), //o-- + .sum(ex3_pp2_0s[204]), //o-- + .car(ex3_pp2_0c[203]) //o-- + ); + + + tri_csa42 csa2_0_203( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_0c[203]), //i-- + .b(ex3_pp1_0s[203]), //i-- + .c(ex3_pp1_1c[203]), //i-- + .d(ex3_pp1_1s[203]), //i-- + .ki(ex3_pp2_0k[203]), //i-- + .ko(ex3_pp2_0k[202]), //o-- + .sum(ex3_pp2_0s[203]), //o-- + .car(ex3_pp2_0c[202]) //o-- + ); + + + tri_csa42 csa2_0_202( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_0c[202]), //i-- + .b(ex3_pp1_0s[202]), //i-- + .c(ex3_pp1_1s[202]), //i-- + .d(1'b0), //i-- + .ki(ex3_pp2_0k[202]), //i-- + .ko(ex3_pp2_0k[201]), //o-- + .sum(ex3_pp2_0s[202]), //o-- + .car(ex3_pp2_0c[201]) //o-- + ); + + + tri_csa32 csa2_0_201( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_0c[201]), //i-- + .b(ex3_pp1_0s[201]), //i-- + .c(ex3_pp2_0k[201]), //i-- + .sum(ex3_pp2_0s[201]), //o-- + .car(ex3_pp2_0c[200]) //o-- + ); + + tri_csa22 csa2_0_200( + .a(ex3_pp1_0c[200]), //i-- + .b(ex3_pp1_0s[200]), //i-- + .sum(ex3_pp2_0s[200]), //o-- + .car(ex3_pp2_0c[199]) //o-- + ); + + tri_csa22 csa2_0_199( + .a(ex3_pp1_0c[199]), //i-- + .b(ex3_pp1_0s[199]), //i-- + .sum(ex3_pp2_0s[199]), //o-- + .car(ex3_pp2_0c[198]) //o-- + ); + assign ex3_pp2_0s[198] = ex3_pp1_0s[198]; //pass_x_s + + //----- ----- + + assign ex3_pp2_1s[254] = ex3_pp1_3s[254]; //pass_s + assign ex3_pp2_1s[253] = 0; //pass_none + assign ex3_pp2_1c[252] = ex3_pp1_3s[252]; //pass_cs + assign ex3_pp2_1s[252] = ex3_pp1_3c[252]; //pass_cs + assign ex3_pp2_1c[251] = 0; //pass_s + assign ex3_pp2_1s[251] = ex3_pp1_3s[251]; //pass_s + assign ex3_pp2_1c[250] = 0; //pass_s + assign ex3_pp2_1s[250] = ex3_pp1_3s[250]; //pass_s + assign ex3_pp2_1c[249] = ex3_pp1_3s[249]; //pass_cs + assign ex3_pp2_1s[249] = ex3_pp1_3c[249]; //pass_cs + assign ex3_pp2_1c[248] = 0; //wr_csa32 + + + tri_csa32 csa2_1_248( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_2s[248]), //i-- + .b(ex3_pp1_3c[248]), //i-- + .c(ex3_pp1_3s[248]), //i-- + .sum(ex3_pp2_1s[248]), //o-- + .car(ex3_pp2_1c[247]) //o-- + ); + + tri_csa22 csa2_1_247( + .a(ex3_pp1_3c[247]), //i-- + .b(ex3_pp1_3s[247]), //i-- + .sum(ex3_pp2_1s[247]), //o-- + .car(ex3_pp2_1c[246]) //o-- + ); + assign ex3_pp2_1k[246] = 0; //start_k + + + tri_csa42 csa2_1_246( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_2c[246]), //i-- + .b(ex3_pp1_2s[246]), //i-- + .c(ex3_pp1_3c[246]), //i-- + .d(ex3_pp1_3s[246]), //i-- + .ki(ex3_pp2_1k[246]), //i-- + .ko(ex3_pp2_1k[245]), //o-- + .sum(ex3_pp2_1s[246]), //o-- + .car(ex3_pp2_1c[245]) //o-- + ); + + + tri_csa42 csa2_1_245( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_2s[245]), //i-- + .b(ex3_pp1_3c[245]), //i-- + .c(ex3_pp1_3s[245]), //i-- + .d(1'b0), //i-- + .ki(ex3_pp2_1k[245]), //i-- + .ko(ex3_pp2_1k[244]), //o-- + .sum(ex3_pp2_1s[245]), //o-- + .car(ex3_pp2_1c[244]) //o-- + ); + + + tri_csa42 csa2_1_244( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_2s[244]), //i-- + .b(ex3_pp1_3c[244]), //i-- + .c(ex3_pp1_3s[244]), //i-- + .d(1'b0), //i-- + .ki(ex3_pp2_1k[244]), //i-- + .ko(ex3_pp2_1k[243]), //o-- + .sum(ex3_pp2_1s[244]), //o-- + .car(ex3_pp2_1c[243]) //o-- + ); + + + tri_csa42 csa2_1_243( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_2c[243]), //i-- + .b(ex3_pp1_2s[243]), //i-- + .c(ex3_pp1_3c[243]), //i-- + .d(ex3_pp1_3s[243]), //i-- + .ki(ex3_pp2_1k[243]), //i-- + .ko(ex3_pp2_1k[242]), //o-- + .sum(ex3_pp2_1s[243]), //o-- + .car(ex3_pp2_1c[242]) //o-- + ); + + + tri_csa42 csa2_1_242( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_2c[242]), //i-- + .b(ex3_pp1_2s[242]), //i-- + .c(ex3_pp1_3c[242]), //i-- + .d(ex3_pp1_3s[242]), //i-- + .ki(ex3_pp2_1k[242]), //i-- + .ko(ex3_pp2_1k[241]), //o-- + .sum(ex3_pp2_1s[242]), //o-- + .car(ex3_pp2_1c[241]) //o-- + ); + + + tri_csa42 csa2_1_241( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_2c[241]), //i-- + .b(ex3_pp1_2s[241]), //i-- + .c(ex3_pp1_3c[241]), //i-- + .d(ex3_pp1_3s[241]), //i-- + .ki(ex3_pp2_1k[241]), //i-- + .ko(ex3_pp2_1k[240]), //o-- + .sum(ex3_pp2_1s[241]), //o-- + .car(ex3_pp2_1c[240]) //o-- + ); + + + tri_csa42 csa2_1_240( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_2c[240]), //i-- + .b(ex3_pp1_2s[240]), //i-- + .c(ex3_pp1_3c[240]), //i-- + .d(ex3_pp1_3s[240]), //i-- + .ki(ex3_pp2_1k[240]), //i-- + .ko(ex3_pp2_1k[239]), //o-- + .sum(ex3_pp2_1s[240]), //o-- + .car(ex3_pp2_1c[239]) //o-- + ); + + + tri_csa42 csa2_1_239( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_2c[239]), //i-- + .b(ex3_pp1_2s[239]), //i-- + .c(ex3_pp1_3c[239]), //i-- + .d(ex3_pp1_3s[239]), //i-- + .ki(ex3_pp2_1k[239]), //i-- + .ko(ex3_pp2_1k[238]), //o-- + .sum(ex3_pp2_1s[239]), //o-- + .car(ex3_pp2_1c[238]) //o-- + ); + + + tri_csa42 csa2_1_238( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_2c[238]), //i-- + .b(ex3_pp1_2s[238]), //i-- + .c(ex3_pp1_3c[238]), //i-- + .d(ex3_pp1_3s[238]), //i-- + .ki(ex3_pp2_1k[238]), //i-- + .ko(ex3_pp2_1k[237]), //o-- + .sum(ex3_pp2_1s[238]), //o-- + .car(ex3_pp2_1c[237]) //o-- + ); + + + tri_csa42 csa2_1_237( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_2c[237]), //i-- + .b(ex3_pp1_2s[237]), //i-- + .c(ex3_pp1_3c[237]), //i-- + .d(ex3_pp1_3s[237]), //i-- + .ki(ex3_pp2_1k[237]), //i-- + .ko(ex3_pp2_1k[236]), //o-- + .sum(ex3_pp2_1s[237]), //o-- + .car(ex3_pp2_1c[236]) //o-- + ); + + + tri_csa42 csa2_1_236( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_2c[236]), //i-- + .b(ex3_pp1_2s[236]), //i-- + .c(ex3_pp1_3c[236]), //i-- + .d(ex3_pp1_3s[236]), //i-- + .ki(ex3_pp2_1k[236]), //i-- + .ko(ex3_pp2_1k[235]), //o-- + .sum(ex3_pp2_1s[236]), //o-- + .car(ex3_pp2_1c[235]) //o-- + ); + + + tri_csa42 csa2_1_235( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_2c[235]), //i-- + .b(ex3_pp1_2s[235]), //i-- + .c(ex3_pp1_3c[235]), //i-- + .d(ex3_pp1_3s[235]), //i-- + .ki(ex3_pp2_1k[235]), //i-- + .ko(ex3_pp2_1k[234]), //o-- + .sum(ex3_pp2_1s[235]), //o-- + .car(ex3_pp2_1c[234]) //o-- + ); + + + tri_csa42 csa2_1_234( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_2c[234]), //i-- + .b(ex3_pp1_2s[234]), //i-- + .c(ex3_pp1_3c[234]), //i-- + .d(ex3_pp1_3s[234]), //i-- + .ki(ex3_pp2_1k[234]), //i-- + .ko(ex3_pp2_1k[233]), //o-- + .sum(ex3_pp2_1s[234]), //o-- + .car(ex3_pp2_1c[233]) //o-- + ); + + + tri_csa42 csa2_1_233( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_2c[233]), //i-- + .b(ex3_pp1_2s[233]), //i-- + .c(ex3_pp1_3c[233]), //i-- + .d(ex3_pp1_3s[233]), //i-- + .ki(ex3_pp2_1k[233]), //i-- + .ko(ex3_pp2_1k[232]), //o-- + .sum(ex3_pp2_1s[233]), //o-- + .car(ex3_pp2_1c[232]) //o-- + ); + + + tri_csa42 csa2_1_232( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_2c[232]), //i-- + .b(ex3_pp1_2s[232]), //i-- + .c(ex3_pp1_3c[232]), //i-- + .d(ex3_pp1_3s[232]), //i-- + .ki(ex3_pp2_1k[232]), //i-- + .ko(ex3_pp2_1k[231]), //o-- + .sum(ex3_pp2_1s[232]), //o-- + .car(ex3_pp2_1c[231]) //o-- + ); + + + tri_csa42 csa2_1_231( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_2c[231]), //i-- + .b(ex3_pp1_2s[231]), //i-- + .c(ex3_pp1_3c[231]), //i-- + .d(ex3_pp1_3s[231]), //i-- + .ki(ex3_pp2_1k[231]), //i-- + .ko(ex3_pp2_1k[230]), //o-- + .sum(ex3_pp2_1s[231]), //o-- + .car(ex3_pp2_1c[230]) //o-- + ); + + + tri_csa42 csa2_1_230( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_2c[230]), //i-- + .b(ex3_pp1_2s[230]), //i-- + .c(ex3_pp1_3c[230]), //i-- + .d(ex3_pp1_3s[230]), //i-- + .ki(ex3_pp2_1k[230]), //i-- + .ko(ex3_pp2_1k[229]), //o-- + .sum(ex3_pp2_1s[230]), //o-- + .car(ex3_pp2_1c[229]) //o-- + ); + + + tri_csa42 csa2_1_229( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_2c[229]), //i-- + .b(ex3_pp1_2s[229]), //i-- + .c(ex3_pp1_3c[229]), //i-- + .d(ex3_pp1_3s[229]), //i-- + .ki(ex3_pp2_1k[229]), //i-- + .ko(ex3_pp2_1k[228]), //o-- + .sum(ex3_pp2_1s[229]), //o-- + .car(ex3_pp2_1c[228]) //o-- + ); + + + tri_csa42 csa2_1_228( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_2c[228]), //i-- + .b(ex3_pp1_2s[228]), //i-- + .c(ex3_pp1_3c[228]), //i-- + .d(ex3_pp1_3s[228]), //i-- + .ki(ex3_pp2_1k[228]), //i-- + .ko(ex3_pp2_1k[227]), //o-- + .sum(ex3_pp2_1s[228]), //o-- + .car(ex3_pp2_1c[227]) //o-- + ); + + + tri_csa42 csa2_1_227( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_2c[227]), //i-- + .b(ex3_pp1_2s[227]), //i-- + .c(ex3_pp1_3c[227]), //i-- + .d(ex3_pp1_3s[227]), //i-- + .ki(ex3_pp2_1k[227]), //i-- + .ko(ex3_pp2_1k[226]), //o-- + .sum(ex3_pp2_1s[227]), //o-- + .car(ex3_pp2_1c[226]) //o-- + ); + + + tri_csa42 csa2_1_226( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_2c[226]), //i-- + .b(ex3_pp1_2s[226]), //i-- + .c(ex3_pp1_3c[226]), //i-- + .d(ex3_pp1_3s[226]), //i-- + .ki(ex3_pp2_1k[226]), //i-- + .ko(ex3_pp2_1k[225]), //o-- + .sum(ex3_pp2_1s[226]), //o-- + .car(ex3_pp2_1c[225]) //o-- + ); + + + tri_csa42 csa2_1_225( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_2c[225]), //i-- + .b(ex3_pp1_2s[225]), //i-- + .c(ex3_pp1_3c[225]), //i-- + .d(ex3_pp1_3s[225]), //i-- + .ki(ex3_pp2_1k[225]), //i-- + .ko(ex3_pp2_1k[224]), //o-- + .sum(ex3_pp2_1s[225]), //o-- + .car(ex3_pp2_1c[224]) //o-- + ); + + + tri_csa42 csa2_1_224( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_2c[224]), //i-- + .b(ex3_pp1_2s[224]), //i-- + .c(ex3_pp1_3c[224]), //i-- + .d(ex3_pp1_3s[224]), //i-- + .ki(ex3_pp2_1k[224]), //i-- + .ko(ex3_pp2_1k[223]), //o-- + .sum(ex3_pp2_1s[224]), //o-- + .car(ex3_pp2_1c[223]) //o-- + ); + + + tri_csa42 csa2_1_223( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_2c[223]), //i-- + .b(ex3_pp1_2s[223]), //i-- + .c(ex3_pp1_3c[223]), //i-- + .d(ex3_pp1_3s[223]), //i-- + .ki(ex3_pp2_1k[223]), //i-- + .ko(ex3_pp2_1k[222]), //o-- + .sum(ex3_pp2_1s[223]), //o-- + .car(ex3_pp2_1c[222]) //o-- + ); + + + tri_csa42 csa2_1_222( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_2c[222]), //i-- + .b(ex3_pp1_2s[222]), //i-- + .c(ex3_pp1_3c[222]), //i-- + .d(ex3_pp1_3s[222]), //i-- + .ki(ex3_pp2_1k[222]), //i-- + .ko(ex3_pp2_1k[221]), //o-- + .sum(ex3_pp2_1s[222]), //o-- + .car(ex3_pp2_1c[221]) //o-- + ); + + + tri_csa42 csa2_1_221( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_2c[221]), //i-- + .b(ex3_pp1_2s[221]), //i-- + .c(ex3_pp1_3c[221]), //i-- + .d(ex3_pp1_3s[221]), //i-- + .ki(ex3_pp2_1k[221]), //i-- + .ko(ex3_pp2_1k[220]), //o-- + .sum(ex3_pp2_1s[221]), //o-- + .car(ex3_pp2_1c[220]) //o-- + ); + + + tri_csa42 csa2_1_220( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_2c[220]), //i-- + .b(ex3_pp1_2s[220]), //i-- + .c(ex3_pp1_3c[220]), //i-- + .d(ex3_pp1_3s[220]), //i-- + .ki(ex3_pp2_1k[220]), //i-- + .ko(ex3_pp2_1k[219]), //o-- + .sum(ex3_pp2_1s[220]), //o-- + .car(ex3_pp2_1c[219]) //o-- + ); + + + tri_csa42 csa2_1_219( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_2c[219]), //i-- + .b(ex3_pp1_2s[219]), //i-- + .c(ex3_pp1_3c[219]), //i-- + .d(ex3_pp1_3s[219]), //i-- + .ki(ex3_pp2_1k[219]), //i-- + .ko(ex3_pp2_1k[218]), //o-- + .sum(ex3_pp2_1s[219]), //o-- + .car(ex3_pp2_1c[218]) //o-- + ); + + + tri_csa42 csa2_1_218( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_2c[218]), //i-- + .b(ex3_pp1_2s[218]), //i-- + .c(ex3_pp1_3c[218]), //i-- + .d(ex3_pp1_3s[218]), //i-- + .ki(ex3_pp2_1k[218]), //i-- + .ko(ex3_pp2_1k[217]), //o-- + .sum(ex3_pp2_1s[218]), //o-- + .car(ex3_pp2_1c[217]) //o-- + ); + + + tri_csa42 csa2_1_217( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_2c[217]), //i-- + .b(ex3_pp1_2s[217]), //i-- + .c(ex3_pp1_3c[217]), //i-- + .d(ex3_pp1_3s[217]), //i-- + .ki(ex3_pp2_1k[217]), //i-- + .ko(ex3_pp2_1k[216]), //o-- + .sum(ex3_pp2_1s[217]), //o-- + .car(ex3_pp2_1c[216]) //o-- + ); + + + tri_csa42 csa2_1_216( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_2c[216]), //i-- + .b(ex3_pp1_2s[216]), //i-- + .c(ex3_pp1_3c[216]), //i-- + .d(ex3_pp1_3s[216]), //i-- + .ki(ex3_pp2_1k[216]), //i-- + .ko(ex3_pp2_1k[215]), //o-- + .sum(ex3_pp2_1s[216]), //o-- + .car(ex3_pp2_1c[215]) //o-- + ); + + + tri_csa42 csa2_1_215( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_2c[215]), //i-- + .b(ex3_pp1_2s[215]), //i-- + .c(ex3_pp1_3c[215]), //i-- + .d(ex3_pp1_3s[215]), //i-- + .ki(ex3_pp2_1k[215]), //i-- + .ko(ex3_pp2_1k[214]), //o-- + .sum(ex3_pp2_1s[215]), //o-- + .car(ex3_pp2_1c[214]) //o-- + ); + + + tri_csa42 csa2_1_214( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_2c[214]), //i-- + .b(ex3_pp1_2s[214]), //i-- + .c(ex3_pp1_3s[214]), //i-- + .d(1'b0), //i-- + .ki(ex3_pp2_1k[214]), //i-- + .ko(ex3_pp2_1k[213]), //o-- + .sum(ex3_pp2_1s[214]), //o-- + .car(ex3_pp2_1c[213]) //o-- + ); + + + tri_csa32 csa2_1_213( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_2c[213]), //i-- + .b(ex3_pp1_2s[213]), //i-- + .c(ex3_pp2_1k[213]), //i-- + .sum(ex3_pp2_1s[213]), //o-- + .car(ex3_pp2_1c[212]) //o-- + ); + + tri_csa22 csa2_1_212( + .a(ex3_pp1_2c[212]), //i-- + .b(ex3_pp1_2s[212]), //i-- + .sum(ex3_pp2_1s[212]), //o-- + .car(ex3_pp2_1c[211]) //o-- + ); + + tri_csa22 csa2_1_211( + .a(ex3_pp1_2c[211]), //i-- + .b(ex3_pp1_2s[211]), //i-- + .sum(ex3_pp2_1s[211]), //o-- + .car(ex3_pp2_1c[210]) //o-- + ); + + tri_csa22 csa2_1_210( + .a(ex3_pp1_2c[210]), //i-- + .b(ex3_pp1_2s[210]), //i-- + .sum(ex3_pp2_1s[210]), //o-- + .car(ex3_pp2_1c[209]) //o-- + ); + + tri_csa22 csa2_1_209( + .a(ex3_pp1_2c[209]), //i-- + .b(ex3_pp1_2s[209]), //i-- + .sum(ex3_pp2_1s[209]), //o-- + .car(ex3_pp2_1c[208]) //o-- + ); + assign ex3_pp2_1s[208] = ex3_pp1_2s[208]; //pass_x_s + + //----- ----- + + + tri_csa22 csa2_2_264( + .a(ex3_pp1_5c[264]), //i-- + .b(ex3_pp1_5s[264]), //i-- + .sum(ex3_pp2_2s[264]), //o-- + .car(ex3_pp2_2c[263]) //o-- + ); + assign ex3_pp2_2s[263] = ex3_pp1_5s[263]; //pass_x_s + assign ex3_pp2_2c[262] = 0; //pass_s + assign ex3_pp2_2s[262] = ex3_pp1_5s[262]; //pass_s + assign ex3_pp2_2c[261] = ex3_pp1_5s[261]; //pass_cs + assign ex3_pp2_2s[261] = ex3_pp1_5c[261]; //pass_cs + assign ex3_pp2_2c[260] = 0; //wr_csa32 + + + tri_csa32 csa2_2_260( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_4s[260]), //i-- + .b(ex3_pp1_5c[260]), //i-- + .c(ex3_pp1_5s[260]), //i-- + .sum(ex3_pp2_2s[260]), //o-- + .car(ex3_pp2_2c[259]) //o-- + ); + + tri_csa22 csa2_2_259( + .a(ex3_pp1_5c[259]), //i-- + .b(ex3_pp1_5s[259]), //i-- + .sum(ex3_pp2_2s[259]), //o-- + .car(ex3_pp2_2c[258]) //o-- + ); + assign ex3_pp2_2k[258] = 0; //start_k + + + tri_csa42 csa2_2_258( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_4c[258]), //i-- + .b(ex3_pp1_4s[258]), //i-- + .c(ex3_pp1_5c[258]), //i-- + .d(ex3_pp1_5s[258]), //i-- + .ki(ex3_pp2_2k[258]), //i-- + .ko(ex3_pp2_2k[257]), //o-- + .sum(ex3_pp2_2s[258]), //o-- + .car(ex3_pp2_2c[257]) //o-- + ); + + + tri_csa42 csa2_2_257( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_4s[257]), //i-- + .b(ex3_pp1_5c[257]), //i-- + .c(ex3_pp1_5s[257]), //i-- + .d(1'b0), //i-- + .ki(ex3_pp2_2k[257]), //i-- + .ko(ex3_pp2_2k[256]), //o-- + .sum(ex3_pp2_2s[257]), //o-- + .car(ex3_pp2_2c[256]) //o-- + ); + + + tri_csa42 csa2_2_256( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_4s[256]), //i-- + .b(ex3_pp1_5c[256]), //i-- + .c(ex3_pp1_5s[256]), //i-- + .d(1'b0), //i-- + .ki(ex3_pp2_2k[256]), //i-- + .ko(ex3_pp2_2k[255]), //o-- + .sum(ex3_pp2_2s[256]), //o-- + .car(ex3_pp2_2c[255]) //o-- + ); + + + tri_csa42 csa2_2_255( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_4c[255]), //i-- + .b(ex3_pp1_4s[255]), //i-- + .c(ex3_pp1_5c[255]), //i-- + .d(ex3_pp1_5s[255]), //i-- + .ki(ex3_pp2_2k[255]), //i-- + .ko(ex3_pp2_2k[254]), //o-- + .sum(ex3_pp2_2s[255]), //o-- + .car(ex3_pp2_2c[254]) //o-- + ); + + + tri_csa42 csa2_2_254( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_4c[254]), //i-- + .b(ex3_pp1_4s[254]), //i-- + .c(ex3_pp1_5c[254]), //i-- + .d(ex3_pp1_5s[254]), //i-- + .ki(ex3_pp2_2k[254]), //i-- + .ko(ex3_pp2_2k[253]), //o-- + .sum(ex3_pp2_2s[254]), //o-- + .car(ex3_pp2_2c[253]) //o-- + ); + + + tri_csa42 csa2_2_253( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_4c[253]), //i-- + .b(ex3_pp1_4s[253]), //i-- + .c(ex3_pp1_5c[253]), //i-- + .d(ex3_pp1_5s[253]), //i-- + .ki(ex3_pp2_2k[253]), //i-- + .ko(ex3_pp2_2k[252]), //o-- + .sum(ex3_pp2_2s[253]), //o-- + .car(ex3_pp2_2c[252]) //o-- + ); + + + tri_csa42 csa2_2_252( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_4c[252]), //i-- + .b(ex3_pp1_4s[252]), //i-- + .c(ex3_pp1_5c[252]), //i-- + .d(ex3_pp1_5s[252]), //i-- + .ki(ex3_pp2_2k[252]), //i-- + .ko(ex3_pp2_2k[251]), //o-- + .sum(ex3_pp2_2s[252]), //o-- + .car(ex3_pp2_2c[251]) //o-- + ); + + + tri_csa42 csa2_2_251( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_4c[251]), //i-- + .b(ex3_pp1_4s[251]), //i-- + .c(ex3_pp1_5c[251]), //i-- + .d(ex3_pp1_5s[251]), //i-- + .ki(ex3_pp2_2k[251]), //i-- + .ko(ex3_pp2_2k[250]), //o-- + .sum(ex3_pp2_2s[251]), //o-- + .car(ex3_pp2_2c[250]) //o-- + ); + + + tri_csa42 csa2_2_250( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_4c[250]), //i-- + .b(ex3_pp1_4s[250]), //i-- + .c(ex3_pp1_5c[250]), //i-- + .d(ex3_pp1_5s[250]), //i-- + .ki(ex3_pp2_2k[250]), //i-- + .ko(ex3_pp2_2k[249]), //o-- + .sum(ex3_pp2_2s[250]), //o-- + .car(ex3_pp2_2c[249]) //o-- + ); + + + tri_csa42 csa2_2_249( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_4c[249]), //i-- + .b(ex3_pp1_4s[249]), //i-- + .c(ex3_pp1_5c[249]), //i-- + .d(ex3_pp1_5s[249]), //i-- + .ki(ex3_pp2_2k[249]), //i-- + .ko(ex3_pp2_2k[248]), //o-- + .sum(ex3_pp2_2s[249]), //o-- + .car(ex3_pp2_2c[248]) //o-- + ); + + + tri_csa42 csa2_2_248( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_4c[248]), //i-- + .b(ex3_pp1_4s[248]), //i-- + .c(ex3_pp1_5c[248]), //i-- + .d(ex3_pp1_5s[248]), //i-- + .ki(ex3_pp2_2k[248]), //i-- + .ko(ex3_pp2_2k[247]), //o-- + .sum(ex3_pp2_2s[248]), //o-- + .car(ex3_pp2_2c[247]) //o-- + ); + + + tri_csa42 csa2_2_247( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_4c[247]), //i-- + .b(ex3_pp1_4s[247]), //i-- + .c(ex3_pp1_5c[247]), //i-- + .d(ex3_pp1_5s[247]), //i-- + .ki(ex3_pp2_2k[247]), //i-- + .ko(ex3_pp2_2k[246]), //o-- + .sum(ex3_pp2_2s[247]), //o-- + .car(ex3_pp2_2c[246]) //o-- + ); + + + tri_csa42 csa2_2_246( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_4c[246]), //i-- + .b(ex3_pp1_4s[246]), //i-- + .c(ex3_pp1_5c[246]), //i-- + .d(ex3_pp1_5s[246]), //i-- + .ki(ex3_pp2_2k[246]), //i-- + .ko(ex3_pp2_2k[245]), //o-- + .sum(ex3_pp2_2s[246]), //o-- + .car(ex3_pp2_2c[245]) //o-- + ); + + + tri_csa42 csa2_2_245( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_4c[245]), //i-- + .b(ex3_pp1_4s[245]), //i-- + .c(ex3_pp1_5c[245]), //i-- + .d(ex3_pp1_5s[245]), //i-- + .ki(ex3_pp2_2k[245]), //i-- + .ko(ex3_pp2_2k[244]), //o-- + .sum(ex3_pp2_2s[245]), //o-- + .car(ex3_pp2_2c[244]) //o-- + ); + + + tri_csa42 csa2_2_244( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_4c[244]), //i-- + .b(ex3_pp1_4s[244]), //i-- + .c(ex3_pp1_5c[244]), //i-- + .d(ex3_pp1_5s[244]), //i-- + .ki(ex3_pp2_2k[244]), //i-- + .ko(ex3_pp2_2k[243]), //o-- + .sum(ex3_pp2_2s[244]), //o-- + .car(ex3_pp2_2c[243]) //o-- + ); + + + tri_csa42 csa2_2_243( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_4c[243]), //i-- + .b(ex3_pp1_4s[243]), //i-- + .c(ex3_pp1_5c[243]), //i-- + .d(ex3_pp1_5s[243]), //i-- + .ki(ex3_pp2_2k[243]), //i-- + .ko(ex3_pp2_2k[242]), //o-- + .sum(ex3_pp2_2s[243]), //o-- + .car(ex3_pp2_2c[242]) //o-- + ); + + + tri_csa42 csa2_2_242( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_4c[242]), //i-- + .b(ex3_pp1_4s[242]), //i-- + .c(ex3_pp1_5c[242]), //i-- + .d(ex3_pp1_5s[242]), //i-- + .ki(ex3_pp2_2k[242]), //i-- + .ko(ex3_pp2_2k[241]), //o-- + .sum(ex3_pp2_2s[242]), //o-- + .car(ex3_pp2_2c[241]) //o-- + ); + + + tri_csa42 csa2_2_241( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_4c[241]), //i-- + .b(ex3_pp1_4s[241]), //i-- + .c(ex3_pp1_5c[241]), //i-- + .d(ex3_pp1_5s[241]), //i-- + .ki(ex3_pp2_2k[241]), //i-- + .ko(ex3_pp2_2k[240]), //o-- + .sum(ex3_pp2_2s[241]), //o-- + .car(ex3_pp2_2c[240]) //o-- + ); + + + tri_csa42 csa2_2_240( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_4c[240]), //i-- + .b(ex3_pp1_4s[240]), //i-- + .c(ex3_pp1_5c[240]), //i-- + .d(ex3_pp1_5s[240]), //i-- + .ki(ex3_pp2_2k[240]), //i-- + .ko(ex3_pp2_2k[239]), //o-- + .sum(ex3_pp2_2s[240]), //o-- + .car(ex3_pp2_2c[239]) //o-- + ); + + + tri_csa42 csa2_2_239( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_4c[239]), //i-- + .b(ex3_pp1_4s[239]), //i-- + .c(ex3_pp1_5c[239]), //i-- + .d(ex3_pp1_5s[239]), //i-- + .ki(ex3_pp2_2k[239]), //i-- + .ko(ex3_pp2_2k[238]), //o-- + .sum(ex3_pp2_2s[239]), //o-- + .car(ex3_pp2_2c[238]) //o-- + ); + + + tri_csa42 csa2_2_238( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_4c[238]), //i-- + .b(ex3_pp1_4s[238]), //i-- + .c(ex3_pp1_5c[238]), //i-- + .d(ex3_pp1_5s[238]), //i-- + .ki(ex3_pp2_2k[238]), //i-- + .ko(ex3_pp2_2k[237]), //o-- + .sum(ex3_pp2_2s[238]), //o-- + .car(ex3_pp2_2c[237]) //o-- + ); + + + tri_csa42 csa2_2_237( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_4c[237]), //i-- + .b(ex3_pp1_4s[237]), //i-- + .c(ex3_pp1_5c[237]), //i-- + .d(ex3_pp1_5s[237]), //i-- + .ki(ex3_pp2_2k[237]), //i-- + .ko(ex3_pp2_2k[236]), //o-- + .sum(ex3_pp2_2s[237]), //o-- + .car(ex3_pp2_2c[236]) //o-- + ); + + + tri_csa42 csa2_2_236( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_4c[236]), //i-- + .b(ex3_pp1_4s[236]), //i-- + .c(ex3_pp1_5c[236]), //i-- + .d(ex3_pp1_5s[236]), //i-- + .ki(ex3_pp2_2k[236]), //i-- + .ko(ex3_pp2_2k[235]), //o-- + .sum(ex3_pp2_2s[236]), //o-- + .car(ex3_pp2_2c[235]) //o-- + ); + + + tri_csa42 csa2_2_235( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_4c[235]), //i-- + .b(ex3_pp1_4s[235]), //i-- + .c(ex3_pp1_5c[235]), //i-- + .d(ex3_pp1_5s[235]), //i-- + .ki(ex3_pp2_2k[235]), //i-- + .ko(ex3_pp2_2k[234]), //o-- + .sum(ex3_pp2_2s[235]), //o-- + .car(ex3_pp2_2c[234]) //o-- + ); + + + tri_csa42 csa2_2_234( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_4c[234]), //i-- + .b(ex3_pp1_4s[234]), //i-- + .c(ex3_pp1_5c[234]), //i-- + .d(ex3_pp1_5s[234]), //i-- + .ki(ex3_pp2_2k[234]), //i-- + .ko(ex3_pp2_2k[233]), //o-- + .sum(ex3_pp2_2s[234]), //o-- + .car(ex3_pp2_2c[233]) //o-- + ); + + + tri_csa42 csa2_2_233( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_4c[233]), //i-- + .b(ex3_pp1_4s[233]), //i-- + .c(ex3_pp1_5c[233]), //i-- + .d(ex3_pp1_5s[233]), //i-- + .ki(ex3_pp2_2k[233]), //i-- + .ko(ex3_pp2_2k[232]), //o-- + .sum(ex3_pp2_2s[233]), //o-- + .car(ex3_pp2_2c[232]) //o-- + ); + + + tri_csa42 csa2_2_232( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_4c[232]), //i-- + .b(ex3_pp1_4s[232]), //i-- + .c(ex3_pp1_5c[232]), //i-- + .d(ex3_pp1_5s[232]), //i-- + .ki(ex3_pp2_2k[232]), //i-- + .ko(ex3_pp2_2k[231]), //o-- + .sum(ex3_pp2_2s[232]), //o-- + .car(ex3_pp2_2c[231]) //o-- + ); + + + tri_csa42 csa2_2_231( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_4c[231]), //i-- + .b(ex3_pp1_4s[231]), //i-- + .c(ex3_pp1_5c[231]), //i-- + .d(ex3_pp1_5s[231]), //i-- + .ki(ex3_pp2_2k[231]), //i-- + .ko(ex3_pp2_2k[230]), //o-- + .sum(ex3_pp2_2s[231]), //o-- + .car(ex3_pp2_2c[230]) //o-- + ); + + + tri_csa42 csa2_2_230( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_4c[230]), //i-- + .b(ex3_pp1_4s[230]), //i-- + .c(ex3_pp1_5c[230]), //i-- + .d(ex3_pp1_5s[230]), //i-- + .ki(ex3_pp2_2k[230]), //i-- + .ko(ex3_pp2_2k[229]), //o-- + .sum(ex3_pp2_2s[230]), //o-- + .car(ex3_pp2_2c[229]) //o-- + ); + + + tri_csa42 csa2_2_229( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_4c[229]), //i-- + .b(ex3_pp1_4s[229]), //i-- + .c(ex3_pp1_5c[229]), //i-- + .d(ex3_pp1_5s[229]), //i-- + .ki(ex3_pp2_2k[229]), //i-- + .ko(ex3_pp2_2k[228]), //o-- + .sum(ex3_pp2_2s[229]), //o-- + .car(ex3_pp2_2c[228]) //o-- + ); + + + tri_csa42 csa2_2_228( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_4c[228]), //i-- + .b(ex3_pp1_4s[228]), //i-- + .c(ex3_pp1_5c[228]), //i-- + .d(ex3_pp1_5s[228]), //i-- + .ki(ex3_pp2_2k[228]), //i-- + .ko(ex3_pp2_2k[227]), //o-- + .sum(ex3_pp2_2s[228]), //o-- + .car(ex3_pp2_2c[227]) //o-- + ); + + + tri_csa42 csa2_2_227( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_4c[227]), //i-- + .b(ex3_pp1_4s[227]), //i-- + .c(ex3_pp1_5c[227]), //i-- + .d(ex3_pp1_5s[227]), //i-- + .ki(ex3_pp2_2k[227]), //i-- + .ko(ex3_pp2_2k[226]), //o-- + .sum(ex3_pp2_2s[227]), //o-- + .car(ex3_pp2_2c[226]) //o-- + ); + + + tri_csa42 csa2_2_226( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_4c[226]), //i-- + .b(ex3_pp1_4s[226]), //i-- + .c(ex3_pp1_5s[226]), //i-- + .d(1'b0), //i-- + .ki(ex3_pp2_2k[226]), //i-- + .ko(ex3_pp2_2k[225]), //o-- + .sum(ex3_pp2_2s[226]), //o-- + .car(ex3_pp2_2c[225]) //o-- + ); + + + tri_csa32 csa2_2_225( + .vd(vdd), + .gd(gnd), + .a(ex3_pp1_4c[225]), //i-- + .b(ex3_pp1_4s[225]), //i-- + .c(ex3_pp2_2k[225]), //i-- + .sum(ex3_pp2_2s[225]), //o-- + .car(ex3_pp2_2c[224]) //o-- + ); + + tri_csa22 csa2_2_224( + .a(ex3_pp1_4c[224]), //i-- + .b(ex3_pp1_4s[224]), //i-- + .sum(ex3_pp2_2s[224]), //o-- + .car(ex3_pp2_2c[223]) //o-- + ); + + tri_csa22 csa2_2_223( + .a(ex3_pp1_4c[223]), //i-- + .b(ex3_pp1_4s[223]), //i-- + .sum(ex3_pp2_2s[223]), //o-- + .car(ex3_pp2_2c[222]) //o-- + ); + + tri_csa22 csa2_2_222( + .a(ex3_pp1_4c[222]), //i-- + .b(ex3_pp1_4s[222]), //i-- + .sum(ex3_pp2_2s[222]), //o-- + .car(ex3_pp2_2c[221]) //o-- + ); + + tri_csa22 csa2_2_221( + .a(ex3_pp1_4c[221]), //i-- + .b(ex3_pp1_4s[221]), //i-- + .sum(ex3_pp2_2s[221]), //o-- + .car(ex3_pp2_2c[220]) //o-- + ); + assign ex3_pp2_2s[220] = ex3_pp1_4s[220]; //pass_x_s + + //--------------------------------------------- + //--------------------------------------------- + //--------------------------------------------- + + assign ex4_pp2_0s_din[198:242] = ex3_pp2_0s[198:242]; + assign ex4_pp2_0c_din[198:240] = ex3_pp2_0c[198:240]; + assign ex4_pp2_1s_din[208:254] = ex3_pp2_1s[208:254]; + assign ex4_pp2_1c_din[208:252] = ex3_pp2_1c[208:252]; + assign ex4_pp2_2s_din[220:264] = ex3_pp2_2s[220:264]; + assign ex4_pp2_2c_din[220:263] = ex3_pp2_2c[220:263]; + + //================================================================================== + //== EX3 ( finish compression <6:2> , feedback compression with previous result ) + //================================================================================== + + assign ex4_pp2_0s[198:242] = (~ex4_pp2_0s_q_b[198:242]); + assign ex4_pp2_0c[198:240] = (~ex4_pp2_0c_q_b[198:240]); + + assign ex4_pp2_1s_x[208:254] = (~ex4_pp2_1s_q_b[208:254]); + assign ex4_pp2_1c_x[208:252] = (~ex4_pp2_1c_q_b[208:252]); + assign ex4_pp2_2s_x[220:264] = (~ex4_pp2_2s_q_b[220:264]); + assign ex4_pp2_2c_x[220:263] = (~ex4_pp2_2c_q_b[220:263]); + + assign ex4_pp2_1s_x_b[208:254] = (~ex4_pp2_1s_x[208:254]); + assign ex4_pp2_1c_x_b[208:252] = (~ex4_pp2_1c_x[208:252]); + assign ex4_pp2_2s_x_b[220:264] = (~ex4_pp2_2s_x[220:264]); + assign ex4_pp2_2c_x_b[220:263] = (~ex4_pp2_2c_x[220:263]); + + assign ex4_pp2_1s[208:254] = (~ex4_pp2_1s_x_b[208:254]); + assign ex4_pp2_1c[208:252] = (~ex4_pp2_1c_x_b[208:252]); + assign ex4_pp2_2s[220:264] = (~ex4_pp2_2s_x_b[220:264]); + assign ex4_pp2_2c[220:263] = (~ex4_pp2_2c_x_b[220:263]); + + //*********************************** + //** compression level 3 + //*********************************** + + // g3 : for i in 196 to 264 generate + // + // csa3_0: entity c_prism_csa32 port map( + // a => ex4_pp2_0s(i) ,--i-- + // b => ex4_pp2_0c(i) ,--i-- + // c => ex4_pp2_1s(i) ,--i-- + // sum => ex4_pp3_0s(i) ,--o-- + // car => ex4_pp3_0c(i-1) );--o-- + // + // csa3_1: entity c_prism_csa32 port map( + // a => ex4_pp2_1c(i) ,--i-- + // b => ex4_pp2_2s(i) ,--i-- + // c => ex4_pp2_2c(i) ,--i-- + // sum => ex4_pp3_1s(i) ,--o-- + // car => ex4_pp3_1c(i-1) );--o-- + // + // end generate; + + //----- ----- + + assign ex4_pp3_0s[252] = ex4_pp2_1c[252]; //pass_s + assign ex4_pp3_0s[251] = 0; //pass_none + assign ex4_pp3_0s[250] = 0; //pass_none + assign ex4_pp3_0s[249] = ex4_pp2_1c[249]; //pass_s + assign ex4_pp3_0s[248] = 0; //pass_none + assign ex4_pp3_0s[247] = ex4_pp2_1c[247]; //pass_s + assign ex4_pp3_0s[246] = ex4_pp2_1c[246]; //pass_s + assign ex4_pp3_0s[245] = ex4_pp2_1c[245]; //pass_s + assign ex4_pp3_0s[244] = ex4_pp2_1c[244]; //pass_s + assign ex4_pp3_0s[243] = ex4_pp2_1c[243]; //pass_s + assign ex4_pp3_0c[242] = ex4_pp2_1c[242]; //pass_cs + assign ex4_pp3_0s[242] = ex4_pp2_0s[242]; //pass_cs + assign ex4_pp3_0c[241] = 0; //pass_s + assign ex4_pp3_0s[241] = ex4_pp2_1c[241]; //pass_s + assign ex4_pp3_0c[240] = 0; //wr_csa32 + + + tri_csa32 csa3_0_240( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_0c[240]), //i-- + .b(ex4_pp2_0s[240]), //i-- + .c(ex4_pp2_1c[240]), //i-- + .sum(ex4_pp3_0s[240]), //o-- + .car(ex4_pp3_0c[239]) //o-- + ); + + tri_csa22 csa3_0_239( + .a(ex4_pp2_0s[239]), //i-- + .b(ex4_pp2_1c[239]), //i-- + .sum(ex4_pp3_0s[239]), //o-- + .car(ex4_pp3_0c[238]) //o-- + ); + + tri_csa22 csa3_0_238( + .a(ex4_pp2_0s[238]), //i-- + .b(ex4_pp2_1c[238]), //i-- + .sum(ex4_pp3_0s[238]), //o-- + .car(ex4_pp3_0c[237]) //o-- + ); + + + tri_csa32 csa3_0_237( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_0c[237]), //i-- + .b(ex4_pp2_0s[237]), //i-- + .c(ex4_pp2_1c[237]), //i-- + .sum(ex4_pp3_0s[237]), //o-- + .car(ex4_pp3_0c[236]) //o-- + ); + + tri_csa22 csa3_0_236( + .a(ex4_pp2_0s[236]), //i-- + .b(ex4_pp2_1c[236]), //i-- + .sum(ex4_pp3_0s[236]), //o-- + .car(ex4_pp3_0c[235]) //o-- + ); + + + tri_csa32 csa3_0_235( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_0c[235]), //i-- + .b(ex4_pp2_0s[235]), //i-- + .c(ex4_pp2_1c[235]), //i-- + .sum(ex4_pp3_0s[235]), //o-- + .car(ex4_pp3_0c[234]) //o-- + ); + + + tri_csa32 csa3_0_234( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_0c[234]), //i-- + .b(ex4_pp2_0s[234]), //i-- + .c(ex4_pp2_1c[234]), //i-- + .sum(ex4_pp3_0s[234]), //o-- + .car(ex4_pp3_0c[233]) //o-- + ); + + + tri_csa32 csa3_0_233( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_0c[233]), //i-- + .b(ex4_pp2_0s[233]), //i-- + .c(ex4_pp2_1c[233]), //i-- + .sum(ex4_pp3_0s[233]), //o-- + .car(ex4_pp3_0c[232]) //o-- + ); + + + tri_csa32 csa3_0_232( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_0c[232]), //i-- + .b(ex4_pp2_0s[232]), //i-- + .c(ex4_pp2_1c[232]), //i-- + .sum(ex4_pp3_0s[232]), //o-- + .car(ex4_pp3_0c[231]) //o-- + ); + + + tri_csa32 csa3_0_231( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_0c[231]), //i-- + .b(ex4_pp2_0s[231]), //i-- + .c(ex4_pp2_1c[231]), //i-- + .sum(ex4_pp3_0s[231]), //o-- + .car(ex4_pp3_0c[230]) //o-- + ); + + + tri_csa32 csa3_0_230( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_0c[230]), //i-- + .b(ex4_pp2_0s[230]), //i-- + .c(ex4_pp2_1c[230]), //i-- + .sum(ex4_pp3_0s[230]), //o-- + .car(ex4_pp3_0c[229]) //o-- + ); + + + tri_csa32 csa3_0_229( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_0c[229]), //i-- + .b(ex4_pp2_0s[229]), //i-- + .c(ex4_pp2_1c[229]), //i-- + .sum(ex4_pp3_0s[229]), //o-- + .car(ex4_pp3_0c[228]) //o-- + ); + + + tri_csa32 csa3_0_228( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_0c[228]), //i-- + .b(ex4_pp2_0s[228]), //i-- + .c(ex4_pp2_1c[228]), //i-- + .sum(ex4_pp3_0s[228]), //o-- + .car(ex4_pp3_0c[227]) //o-- + ); + + + tri_csa32 csa3_0_227( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_0c[227]), //i-- + .b(ex4_pp2_0s[227]), //i-- + .c(ex4_pp2_1c[227]), //i-- + .sum(ex4_pp3_0s[227]), //o-- + .car(ex4_pp3_0c[226]) //o-- + ); + + + tri_csa32 csa3_0_226( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_0c[226]), //i-- + .b(ex4_pp2_0s[226]), //i-- + .c(ex4_pp2_1c[226]), //i-- + .sum(ex4_pp3_0s[226]), //o-- + .car(ex4_pp3_0c[225]) //o-- + ); + + + tri_csa32 csa3_0_225( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_0c[225]), //i-- + .b(ex4_pp2_0s[225]), //i-- + .c(ex4_pp2_1c[225]), //i-- + .sum(ex4_pp3_0s[225]), //o-- + .car(ex4_pp3_0c[224]) //o-- + ); + + + tri_csa32 csa3_0_224( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_0c[224]), //i-- + .b(ex4_pp2_0s[224]), //i-- + .c(ex4_pp2_1c[224]), //i-- + .sum(ex4_pp3_0s[224]), //o-- + .car(ex4_pp3_0c[223]) //o-- + ); + + + tri_csa32 csa3_0_223( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_0c[223]), //i-- + .b(ex4_pp2_0s[223]), //i-- + .c(ex4_pp2_1c[223]), //i-- + .sum(ex4_pp3_0s[223]), //o-- + .car(ex4_pp3_0c[222]) //o-- + ); + + + tri_csa32 csa3_0_222( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_0c[222]), //i-- + .b(ex4_pp2_0s[222]), //i-- + .c(ex4_pp2_1c[222]), //i-- + .sum(ex4_pp3_0s[222]), //o-- + .car(ex4_pp3_0c[221]) //o-- + ); + + + tri_csa32 csa3_0_221( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_0c[221]), //i-- + .b(ex4_pp2_0s[221]), //i-- + .c(ex4_pp2_1c[221]), //i-- + .sum(ex4_pp3_0s[221]), //o-- + .car(ex4_pp3_0c[220]) //o-- + ); + + + tri_csa32 csa3_0_220( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_0c[220]), //i-- + .b(ex4_pp2_0s[220]), //i-- + .c(ex4_pp2_1c[220]), //i-- + .sum(ex4_pp3_0s[220]), //o-- + .car(ex4_pp3_0c[219]) //o-- + ); + + + tri_csa32 csa3_0_219( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_0c[219]), //i-- + .b(ex4_pp2_0s[219]), //i-- + .c(ex4_pp2_1c[219]), //i-- + .sum(ex4_pp3_0s[219]), //o-- + .car(ex4_pp3_0c[218]) //o-- + ); + + + tri_csa32 csa3_0_218( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_0c[218]), //i-- + .b(ex4_pp2_0s[218]), //i-- + .c(ex4_pp2_1c[218]), //i-- + .sum(ex4_pp3_0s[218]), //o-- + .car(ex4_pp3_0c[217]) //o-- + ); + + + tri_csa32 csa3_0_217( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_0c[217]), //i-- + .b(ex4_pp2_0s[217]), //i-- + .c(ex4_pp2_1c[217]), //i-- + .sum(ex4_pp3_0s[217]), //o-- + .car(ex4_pp3_0c[216]) //o-- + ); + + + tri_csa32 csa3_0_216( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_0c[216]), //i-- + .b(ex4_pp2_0s[216]), //i-- + .c(ex4_pp2_1c[216]), //i-- + .sum(ex4_pp3_0s[216]), //o-- + .car(ex4_pp3_0c[215]) //o-- + ); + + + tri_csa32 csa3_0_215( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_0c[215]), //i-- + .b(ex4_pp2_0s[215]), //i-- + .c(ex4_pp2_1c[215]), //i-- + .sum(ex4_pp3_0s[215]), //o-- + .car(ex4_pp3_0c[214]) //o-- + ); + + + tri_csa32 csa3_0_214( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_0c[214]), //i-- + .b(ex4_pp2_0s[214]), //i-- + .c(ex4_pp2_1c[214]), //i-- + .sum(ex4_pp3_0s[214]), //o-- + .car(ex4_pp3_0c[213]) //o-- + ); + + + tri_csa32 csa3_0_213( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_0c[213]), //i-- + .b(ex4_pp2_0s[213]), //i-- + .c(ex4_pp2_1c[213]), //i-- + .sum(ex4_pp3_0s[213]), //o-- + .car(ex4_pp3_0c[212]) //o-- + ); + + + tri_csa32 csa3_0_212( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_0c[212]), //i-- + .b(ex4_pp2_0s[212]), //i-- + .c(ex4_pp2_1c[212]), //i-- + .sum(ex4_pp3_0s[212]), //o-- + .car(ex4_pp3_0c[211]) //o-- + ); + + + tri_csa32 csa3_0_211( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_0c[211]), //i-- + .b(ex4_pp2_0s[211]), //i-- + .c(ex4_pp2_1c[211]), //i-- + .sum(ex4_pp3_0s[211]), //o-- + .car(ex4_pp3_0c[210]) //o-- + ); + + + tri_csa32 csa3_0_210( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_0c[210]), //i-- + .b(ex4_pp2_0s[210]), //i-- + .c(ex4_pp2_1c[210]), //i-- + .sum(ex4_pp3_0s[210]), //o-- + .car(ex4_pp3_0c[209]) //o-- + ); + + + tri_csa32 csa3_0_209( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_0c[209]), //i-- + .b(ex4_pp2_0s[209]), //i-- + .c(ex4_pp2_1c[209]), //i-- + .sum(ex4_pp3_0s[209]), //o-- + .car(ex4_pp3_0c[208]) //o-- + ); + + + tri_csa32 csa3_0_208( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_0c[208]), //i-- + .b(ex4_pp2_0s[208]), //i-- + .c(ex4_pp2_1c[208]), //i-- + .sum(ex4_pp3_0s[208]), //o-- + .car(ex4_pp3_0c[207]) //o-- + ); + + tri_csa22 csa3_0_207( + .a(ex4_pp2_0c[207]), //i-- + .b(ex4_pp2_0s[207]), //i-- + .sum(ex4_pp3_0s[207]), //o-- + .car(ex4_pp3_0c[206]) //o-- + ); + + tri_csa22 csa3_0_206( + .a(ex4_pp2_0c[206]), //i-- + .b(ex4_pp2_0s[206]), //i-- + .sum(ex4_pp3_0s[206]), //o-- + .car(ex4_pp3_0c[205]) //o-- + ); + + tri_csa22 csa3_0_205( + .a(ex4_pp2_0c[205]), //i-- + .b(ex4_pp2_0s[205]), //i-- + .sum(ex4_pp3_0s[205]), //o-- + .car(ex4_pp3_0c[204]) //o-- + ); + + tri_csa22 csa3_0_204( + .a(ex4_pp2_0c[204]), //i-- + .b(ex4_pp2_0s[204]), //i-- + .sum(ex4_pp3_0s[204]), //o-- + .car(ex4_pp3_0c[203]) //o-- + ); + + tri_csa22 csa3_0_203( + .a(ex4_pp2_0c[203]), //i-- + .b(ex4_pp2_0s[203]), //i-- + .sum(ex4_pp3_0s[203]), //o-- + .car(ex4_pp3_0c[202]) //o-- + ); + + tri_csa22 csa3_0_202( + .a(ex4_pp2_0c[202]), //i-- + .b(ex4_pp2_0s[202]), //i-- + .sum(ex4_pp3_0s[202]), //o-- + .car(ex4_pp3_0c[201]) //o-- + ); + + tri_csa22 csa3_0_201( + .a(ex4_pp2_0c[201]), //i-- + .b(ex4_pp2_0s[201]), //i-- + .sum(ex4_pp3_0s[201]), //o-- + .car(ex4_pp3_0c[200]) //o-- + ); + + tri_csa22 csa3_0_200( + .a(ex4_pp2_0c[200]), //i-- + .b(ex4_pp2_0s[200]), //i-- + .sum(ex4_pp3_0s[200]), //o-- + .car(ex4_pp3_0c[199]) //o-- + ); + + tri_csa22 csa3_0_199( + .a(ex4_pp2_0c[199]), //i-- + .b(ex4_pp2_0s[199]), //i-- + .sum(ex4_pp3_0s[199]), //o-- + .car(ex4_pp3_0c[198]) //o-- + ); + + tri_csa22 csa3_0_198( + .a(ex4_pp2_0c[198]), //i-- + .b(ex4_pp2_0s[198]), //i-- + .sum(ex4_pp3_0s[198]), //o-- + .car(ex4_pp3_0c[197]) //o-- + ); + + //----- ----- + + assign ex4_pp3_1s[264] = ex4_pp2_2s[264]; //pass_s + + tri_csa22 csa3_1_263( + .a(ex4_pp2_2c[263]), //i-- + .b(ex4_pp2_2s[263]), //i-- + .sum(ex4_pp3_1s[263]), //o-- + .car(ex4_pp3_1c[262]) //o-- + ); + assign ex4_pp3_1s[262] = ex4_pp2_2s[262]; //pass_x_s + assign ex4_pp3_1c[261] = ex4_pp2_2s[261]; //pass_cs + assign ex4_pp3_1s[261] = ex4_pp2_2c[261]; //pass_cs + assign ex4_pp3_1c[260] = 0; //pass_s + assign ex4_pp3_1s[260] = ex4_pp2_2s[260]; //pass_s + assign ex4_pp3_1c[259] = ex4_pp2_2s[259]; //pass_cs + assign ex4_pp3_1s[259] = ex4_pp2_2c[259]; //pass_cs + assign ex4_pp3_1c[258] = ex4_pp2_2s[258]; //pass_cs + assign ex4_pp3_1s[258] = ex4_pp2_2c[258]; //pass_cs + assign ex4_pp3_1c[257] = ex4_pp2_2s[257]; //pass_cs + assign ex4_pp3_1s[257] = ex4_pp2_2c[257]; //pass_cs + assign ex4_pp3_1c[256] = ex4_pp2_2s[256]; //pass_cs + assign ex4_pp3_1s[256] = ex4_pp2_2c[256]; //pass_cs + assign ex4_pp3_1c[255] = ex4_pp2_2s[255]; //pass_cs + assign ex4_pp3_1s[255] = ex4_pp2_2c[255]; //pass_cs + assign ex4_pp3_1c[254] = 0; //wr_csa32 + + + tri_csa32 csa3_1_254( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_1s[254]), //i-- + .b(ex4_pp2_2c[254]), //i-- + .c(ex4_pp2_2s[254]), //i-- + .sum(ex4_pp3_1s[254]), //o-- + .car(ex4_pp3_1c[253]) //o-- + ); + + tri_csa22 csa3_1_253( + .a(ex4_pp2_2c[253]), //i-- + .b(ex4_pp2_2s[253]), //i-- + .sum(ex4_pp3_1s[253]), //o-- + .car(ex4_pp3_1c[252]) //o-- + ); + + + tri_csa32 csa3_1_252( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_1s[252]), //i-- + .b(ex4_pp2_2c[252]), //i-- + .c(ex4_pp2_2s[252]), //i-- + .sum(ex4_pp3_1s[252]), //o-- + .car(ex4_pp3_1c[251]) //o-- + ); + + + tri_csa32 csa3_1_251( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_1s[251]), //i-- + .b(ex4_pp2_2c[251]), //i-- + .c(ex4_pp2_2s[251]), //i-- + .sum(ex4_pp3_1s[251]), //o-- + .car(ex4_pp3_1c[250]) //o-- + ); + + + tri_csa32 csa3_1_250( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_1s[250]), //i-- + .b(ex4_pp2_2c[250]), //i-- + .c(ex4_pp2_2s[250]), //i-- + .sum(ex4_pp3_1s[250]), //o-- + .car(ex4_pp3_1c[249]) //o-- + ); + + + tri_csa32 csa3_1_249( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_1s[249]), //i-- + .b(ex4_pp2_2c[249]), //i-- + .c(ex4_pp2_2s[249]), //i-- + .sum(ex4_pp3_1s[249]), //o-- + .car(ex4_pp3_1c[248]) //o-- + ); + + + tri_csa32 csa3_1_248( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_1s[248]), //i-- + .b(ex4_pp2_2c[248]), //i-- + .c(ex4_pp2_2s[248]), //i-- + .sum(ex4_pp3_1s[248]), //o-- + .car(ex4_pp3_1c[247]) //o-- + ); + + + tri_csa32 csa3_1_247( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_1s[247]), //i-- + .b(ex4_pp2_2c[247]), //i-- + .c(ex4_pp2_2s[247]), //i-- + .sum(ex4_pp3_1s[247]), //o-- + .car(ex4_pp3_1c[246]) //o-- + ); + + + tri_csa32 csa3_1_246( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_1s[246]), //i-- + .b(ex4_pp2_2c[246]), //i-- + .c(ex4_pp2_2s[246]), //i-- + .sum(ex4_pp3_1s[246]), //o-- + .car(ex4_pp3_1c[245]) //o-- + ); + + + tri_csa32 csa3_1_245( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_1s[245]), //i-- + .b(ex4_pp2_2c[245]), //i-- + .c(ex4_pp2_2s[245]), //i-- + .sum(ex4_pp3_1s[245]), //o-- + .car(ex4_pp3_1c[244]) //o-- + ); + + + tri_csa32 csa3_1_244( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_1s[244]), //i-- + .b(ex4_pp2_2c[244]), //i-- + .c(ex4_pp2_2s[244]), //i-- + .sum(ex4_pp3_1s[244]), //o-- + .car(ex4_pp3_1c[243]) //o-- + ); + + + tri_csa32 csa3_1_243( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_1s[243]), //i-- + .b(ex4_pp2_2c[243]), //i-- + .c(ex4_pp2_2s[243]), //i-- + .sum(ex4_pp3_1s[243]), //o-- + .car(ex4_pp3_1c[242]) //o-- + ); + + + tri_csa32 csa3_1_242( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_1s[242]), //i-- + .b(ex4_pp2_2c[242]), //i-- + .c(ex4_pp2_2s[242]), //i-- + .sum(ex4_pp3_1s[242]), //o-- + .car(ex4_pp3_1c[241]) //o-- + ); + + + tri_csa32 csa3_1_241( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_1s[241]), //i-- + .b(ex4_pp2_2c[241]), //i-- + .c(ex4_pp2_2s[241]), //i-- + .sum(ex4_pp3_1s[241]), //o-- + .car(ex4_pp3_1c[240]) //o-- + ); + + + tri_csa32 csa3_1_240( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_1s[240]), //i-- + .b(ex4_pp2_2c[240]), //i-- + .c(ex4_pp2_2s[240]), //i-- + .sum(ex4_pp3_1s[240]), //o-- + .car(ex4_pp3_1c[239]) //o-- + ); + + + tri_csa32 csa3_1_239( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_1s[239]), //i-- + .b(ex4_pp2_2c[239]), //i-- + .c(ex4_pp2_2s[239]), //i-- + .sum(ex4_pp3_1s[239]), //o-- + .car(ex4_pp3_1c[238]) //o-- + ); + + + tri_csa32 csa3_1_238( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_1s[238]), //i-- + .b(ex4_pp2_2c[238]), //i-- + .c(ex4_pp2_2s[238]), //i-- + .sum(ex4_pp3_1s[238]), //o-- + .car(ex4_pp3_1c[237]) //o-- + ); + + + tri_csa32 csa3_1_237( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_1s[237]), //i-- + .b(ex4_pp2_2c[237]), //i-- + .c(ex4_pp2_2s[237]), //i-- + .sum(ex4_pp3_1s[237]), //o-- + .car(ex4_pp3_1c[236]) //o-- + ); + + + tri_csa32 csa3_1_236( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_1s[236]), //i-- + .b(ex4_pp2_2c[236]), //i-- + .c(ex4_pp2_2s[236]), //i-- + .sum(ex4_pp3_1s[236]), //o-- + .car(ex4_pp3_1c[235]) //o-- + ); + + + tri_csa32 csa3_1_235( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_1s[235]), //i-- + .b(ex4_pp2_2c[235]), //i-- + .c(ex4_pp2_2s[235]), //i-- + .sum(ex4_pp3_1s[235]), //o-- + .car(ex4_pp3_1c[234]) //o-- + ); + + + tri_csa32 csa3_1_234( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_1s[234]), //i-- + .b(ex4_pp2_2c[234]), //i-- + .c(ex4_pp2_2s[234]), //i-- + .sum(ex4_pp3_1s[234]), //o-- + .car(ex4_pp3_1c[233]) //o-- + ); + + + tri_csa32 csa3_1_233( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_1s[233]), //i-- + .b(ex4_pp2_2c[233]), //i-- + .c(ex4_pp2_2s[233]), //i-- + .sum(ex4_pp3_1s[233]), //o-- + .car(ex4_pp3_1c[232]) //o-- + ); + + + tri_csa32 csa3_1_232( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_1s[232]), //i-- + .b(ex4_pp2_2c[232]), //i-- + .c(ex4_pp2_2s[232]), //i-- + .sum(ex4_pp3_1s[232]), //o-- + .car(ex4_pp3_1c[231]) //o-- + ); + + + tri_csa32 csa3_1_231( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_1s[231]), //i-- + .b(ex4_pp2_2c[231]), //i-- + .c(ex4_pp2_2s[231]), //i-- + .sum(ex4_pp3_1s[231]), //o-- + .car(ex4_pp3_1c[230]) //o-- + ); + + + tri_csa32 csa3_1_230( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_1s[230]), //i-- + .b(ex4_pp2_2c[230]), //i-- + .c(ex4_pp2_2s[230]), //i-- + .sum(ex4_pp3_1s[230]), //o-- + .car(ex4_pp3_1c[229]) //o-- + ); + + + tri_csa32 csa3_1_229( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_1s[229]), //i-- + .b(ex4_pp2_2c[229]), //i-- + .c(ex4_pp2_2s[229]), //i-- + .sum(ex4_pp3_1s[229]), //o-- + .car(ex4_pp3_1c[228]) //o-- + ); + + + tri_csa32 csa3_1_228( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_1s[228]), //i-- + .b(ex4_pp2_2c[228]), //i-- + .c(ex4_pp2_2s[228]), //i-- + .sum(ex4_pp3_1s[228]), //o-- + .car(ex4_pp3_1c[227]) //o-- + ); + + + tri_csa32 csa3_1_227( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_1s[227]), //i-- + .b(ex4_pp2_2c[227]), //i-- + .c(ex4_pp2_2s[227]), //i-- + .sum(ex4_pp3_1s[227]), //o-- + .car(ex4_pp3_1c[226]) //o-- + ); + + + tri_csa32 csa3_1_226( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_1s[226]), //i-- + .b(ex4_pp2_2c[226]), //i-- + .c(ex4_pp2_2s[226]), //i-- + .sum(ex4_pp3_1s[226]), //o-- + .car(ex4_pp3_1c[225]) //o-- + ); + + + tri_csa32 csa3_1_225( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_1s[225]), //i-- + .b(ex4_pp2_2c[225]), //i-- + .c(ex4_pp2_2s[225]), //i-- + .sum(ex4_pp3_1s[225]), //o-- + .car(ex4_pp3_1c[224]) //o-- + ); + + + tri_csa32 csa3_1_224( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_1s[224]), //i-- + .b(ex4_pp2_2c[224]), //i-- + .c(ex4_pp2_2s[224]), //i-- + .sum(ex4_pp3_1s[224]), //o-- + .car(ex4_pp3_1c[223]) //o-- + ); + + + tri_csa32 csa3_1_223( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_1s[223]), //i-- + .b(ex4_pp2_2c[223]), //i-- + .c(ex4_pp2_2s[223]), //i-- + .sum(ex4_pp3_1s[223]), //o-- + .car(ex4_pp3_1c[222]) //o-- + ); + + + tri_csa32 csa3_1_222( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_1s[222]), //i-- + .b(ex4_pp2_2c[222]), //i-- + .c(ex4_pp2_2s[222]), //i-- + .sum(ex4_pp3_1s[222]), //o-- + .car(ex4_pp3_1c[221]) //o-- + ); + + + tri_csa32 csa3_1_221( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_1s[221]), //i-- + .b(ex4_pp2_2c[221]), //i-- + .c(ex4_pp2_2s[221]), //i-- + .sum(ex4_pp3_1s[221]), //o-- + .car(ex4_pp3_1c[220]) //o-- + ); + + + tri_csa32 csa3_1_220( + .vd(vdd), + .gd(gnd), + .a(ex4_pp2_1s[220]), //i-- + .b(ex4_pp2_2c[220]), //i-- + .c(ex4_pp2_2s[220]), //i-- + .sum(ex4_pp3_1s[220]), //o-- + .car(ex4_pp3_1c[219]) //o-- + ); + assign ex4_pp3_1s[219] = ex4_pp2_1s[219]; //pass_x_s + //ex4_pp3_1c(218) <= 0 ; --pass_s + assign ex4_pp3_1s[218] = ex4_pp2_1s[218]; //pass_s + //ex4_pp3_1c(217) <= 0 ; --pass_s + assign ex4_pp3_1s[217] = ex4_pp2_1s[217]; //pass_s + //ex4_pp3_1c(216) <= 0 ; --pass_s + assign ex4_pp3_1s[216] = ex4_pp2_1s[216]; //pass_s + //ex4_pp3_1c(215) <= 0 ; --pass_s + assign ex4_pp3_1s[215] = ex4_pp2_1s[215]; //pass_s + //ex4_pp3_1c(214) <= 0 ; --pass_s + assign ex4_pp3_1s[214] = ex4_pp2_1s[214]; //pass_s + //ex4_pp3_1c(213) <= 0 ; --pass_s + assign ex4_pp3_1s[213] = ex4_pp2_1s[213]; //pass_s + //ex4_pp3_1c(212) <= 0 ; --pass_s + assign ex4_pp3_1s[212] = ex4_pp2_1s[212]; //pass_s + //ex4_pp3_1c(211) <= 0 ; --pass_s + assign ex4_pp3_1s[211] = ex4_pp2_1s[211]; //pass_s + //ex4_pp3_1c(210) <= 0 ; --pass_s + assign ex4_pp3_1s[210] = ex4_pp2_1s[210]; //pass_s + //ex4_pp3_1c(209) <= 0 ; --pass_s + assign ex4_pp3_1s[209] = ex4_pp2_1s[209]; //pass_s + assign ex4_pp3_1s[208] = ex4_pp2_1s[208]; //pass_s + + //*********************************** + //** compression level 4 + //*********************************** + + // g4 : for i in 196 to 264 generate + // csa4_0: entity c_prism_csa42 port map( + // a => ex4_pp3_0s(i) ,--i-- + // b => ex4_pp3_0c(i) ,--i-- + // c => ex4_pp3_1s(i) ,--i-- + // d => ex4_pp3_1c(i) ,--i-- + // ki => ex4_pp4_0k(i) ,--i-- + // ko => ex4_pp4_0k(i - 1) ,--o-- + // sum => ex4_pp4_0s(i) ,--o-- + // car => ex4_pp4_0c(i - 1) );--o-- + // end generate; + // ex4_pp4_0k(264) <= 0 ; + // ex4_pp4_0c(264) <= 0 ; + + //----- ----- + + assign ex4_pp4_0s[264] = ex4_pp3_1s[264]; //pass_s + assign ex4_pp4_0s[263] = ex4_pp3_1s[263]; //pass_s + assign ex4_pp4_0c[262] = ex4_pp3_1s[262]; //pass_cs + assign ex4_pp4_0s[262] = ex4_pp3_1c[262]; //pass_cs + assign ex4_pp4_0c[261] = ex4_pp3_1s[261]; //pass_cs + assign ex4_pp4_0s[261] = ex4_pp3_1c[261]; //pass_cs + assign ex4_pp4_0c[260] = 0; //pass_s + assign ex4_pp4_0s[260] = ex4_pp3_1s[260]; //pass_s + assign ex4_pp4_0c[259] = ex4_pp3_1s[259]; //pass_cs + assign ex4_pp4_0s[259] = ex4_pp3_1c[259]; //pass_cs + assign ex4_pp4_0c[258] = ex4_pp3_1s[258]; //pass_cs + assign ex4_pp4_0s[258] = ex4_pp3_1c[258]; //pass_cs + assign ex4_pp4_0c[257] = ex4_pp3_1s[257]; //pass_cs + assign ex4_pp4_0s[257] = ex4_pp3_1c[257]; //pass_cs + assign ex4_pp4_0c[256] = ex4_pp3_1s[256]; //pass_cs + assign ex4_pp4_0s[256] = ex4_pp3_1c[256]; //pass_cs + assign ex4_pp4_0c[255] = ex4_pp3_1s[255]; //pass_cs + assign ex4_pp4_0s[255] = ex4_pp3_1c[255]; //pass_cs + assign ex4_pp4_0c[254] = 0; //pass_s + assign ex4_pp4_0s[254] = ex4_pp3_1s[254]; //pass_s + assign ex4_pp4_0c[253] = ex4_pp3_1s[253]; //pass_cs + assign ex4_pp4_0s[253] = ex4_pp3_1c[253]; //pass_cs + assign ex4_pp4_0c[252] = 0; //wr_csa32 + + + tri_csa32 csa4_0_252( + .vd(vdd), + .gd(gnd), + .a(ex4_pp3_0s[252]), //i-- + .b(ex4_pp3_1c[252]), //i-- + .c(ex4_pp3_1s[252]), //i-- + .sum(ex4_pp4_0s[252]), //o-- + .car(ex4_pp4_0c[251]) //o-- + ); + + tri_csa22 csa4_0_251( + .a(ex4_pp3_1c[251]), //i-- + .b(ex4_pp3_1s[251]), //i-- + .sum(ex4_pp4_0s[251]), //o-- + .car(ex4_pp4_0c[250]) //o-- + ); + + tri_csa22 csa4_0_250( + .a(ex4_pp3_1c[250]), //i-- + .b(ex4_pp3_1s[250]), //i-- + .sum(ex4_pp4_0s[250]), //o-- + .car(ex4_pp4_0c[249]) //o-- + ); + + + tri_csa32 csa4_0_249( + .vd(vdd), + .gd(gnd), + .a(ex4_pp3_0s[249]), //i-- + .b(ex4_pp3_1c[249]), //i-- + .c(ex4_pp3_1s[249]), //i-- + .sum(ex4_pp4_0s[249]), //o-- + .car(ex4_pp4_0c[248]) //o-- + ); + + tri_csa22 csa4_0_248( + .a(ex4_pp3_1c[248]), //i-- + .b(ex4_pp3_1s[248]), //i-- + .sum(ex4_pp4_0s[248]), //o-- + .car(ex4_pp4_0c[247]) //o-- + ); + + + tri_csa32 csa4_0_247( + .vd(vdd), + .gd(gnd), + .a(ex4_pp3_0s[247]), //i-- + .b(ex4_pp3_1c[247]), //i-- + .c(ex4_pp3_1s[247]), //i-- + .sum(ex4_pp4_0s[247]), //o-- + .car(ex4_pp4_0c[246]) //o-- + ); + + + tri_csa32 csa4_0_246( + .vd(vdd), + .gd(gnd), + .a(ex4_pp3_0s[246]), //i-- + .b(ex4_pp3_1c[246]), //i-- + .c(ex4_pp3_1s[246]), //i-- + .sum(ex4_pp4_0s[246]), //o-- + .car(ex4_pp4_0c[245]) //o-- + ); + + + tri_csa32 csa4_0_245( + .vd(vdd), + .gd(gnd), + .a(ex4_pp3_0s[245]), //i-- + .b(ex4_pp3_1c[245]), //i-- + .c(ex4_pp3_1s[245]), //i-- + .sum(ex4_pp4_0s[245]), //o-- + .car(ex4_pp4_0c[244]) //o-- + ); + + + tri_csa32 csa4_0_244( + .vd(vdd), + .gd(gnd), + .a(ex4_pp3_0s[244]), //i-- + .b(ex4_pp3_1c[244]), //i-- + .c(ex4_pp3_1s[244]), //i-- + .sum(ex4_pp4_0s[244]), //o-- + .car(ex4_pp4_0c[243]) //o-- + ); + + + tri_csa32 csa4_0_243( + .vd(vdd), + .gd(gnd), + .a(ex4_pp3_0s[243]), //i-- + .b(ex4_pp3_1c[243]), //i-- + .c(ex4_pp3_1s[243]), //i-- + .sum(ex4_pp4_0s[243]), //o-- + .car(ex4_pp4_0c[242]) //o-- + ); + assign ex4_pp4_0k[242] = 0; //start_k + + + tri_csa42 csa4_0_242( + .vd(vdd), + .gd(gnd), + .a(ex4_pp3_0c[242]), //i-- + .b(ex4_pp3_0s[242]), //i-- + .c(ex4_pp3_1c[242]), //i-- + .d(ex4_pp3_1s[242]), //i-- + .ki(ex4_pp4_0k[242]), //i-- + .ko(ex4_pp4_0k[241]), //o-- + .sum(ex4_pp4_0s[242]), //o-- + .car(ex4_pp4_0c[241]) //o-- + ); + + + tri_csa42 csa4_0_241( + .vd(vdd), + .gd(gnd), + .a(ex4_pp3_0s[241]), //i-- + .b(ex4_pp3_1c[241]), //i-- + .c(ex4_pp3_1s[241]), //i-- + .d(1'b0), //i-- + .ki(ex4_pp4_0k[241]), //i-- + .ko(ex4_pp4_0k[240]), //o-- + .sum(ex4_pp4_0s[241]), //o-- + .car(ex4_pp4_0c[240]) //o-- + ); + + + tri_csa42 csa4_0_240( + .vd(vdd), + .gd(gnd), + .a(ex4_pp3_0s[240]), //i-- + .b(ex4_pp3_1c[240]), //i-- + .c(ex4_pp3_1s[240]), //i-- + .d(1'b0), //i-- + .ki(ex4_pp4_0k[240]), //i-- + .ko(ex4_pp4_0k[239]), //o-- + .sum(ex4_pp4_0s[240]), //o-- + .car(ex4_pp4_0c[239]) //o-- + ); + + + tri_csa42 csa4_0_239( + .vd(vdd), + .gd(gnd), + .a(ex4_pp3_0c[239]), //i-- + .b(ex4_pp3_0s[239]), //i-- + .c(ex4_pp3_1c[239]), //i-- + .d(ex4_pp3_1s[239]), //i-- + .ki(ex4_pp4_0k[239]), //i-- + .ko(ex4_pp4_0k[238]), //o-- + .sum(ex4_pp4_0s[239]), //o-- + .car(ex4_pp4_0c[238]) //o-- + ); + + + tri_csa42 csa4_0_238( + .vd(vdd), + .gd(gnd), + .a(ex4_pp3_0c[238]), //i-- + .b(ex4_pp3_0s[238]), //i-- + .c(ex4_pp3_1c[238]), //i-- + .d(ex4_pp3_1s[238]), //i-- + .ki(ex4_pp4_0k[238]), //i-- + .ko(ex4_pp4_0k[237]), //o-- + .sum(ex4_pp4_0s[238]), //o-- + .car(ex4_pp4_0c[237]) //o-- + ); + + + tri_csa42 csa4_0_237( + .vd(vdd), + .gd(gnd), + .a(ex4_pp3_0c[237]), //i-- + .b(ex4_pp3_0s[237]), //i-- + .c(ex4_pp3_1c[237]), //i-- + .d(ex4_pp3_1s[237]), //i-- + .ki(ex4_pp4_0k[237]), //i-- + .ko(ex4_pp4_0k[236]), //o-- + .sum(ex4_pp4_0s[237]), //o-- + .car(ex4_pp4_0c[236]) //o-- + ); + + + tri_csa42 csa4_0_236( + .vd(vdd), + .gd(gnd), + .a(ex4_pp3_0c[236]), //i-- + .b(ex4_pp3_0s[236]), //i-- + .c(ex4_pp3_1c[236]), //i-- + .d(ex4_pp3_1s[236]), //i-- + .ki(ex4_pp4_0k[236]), //i-- + .ko(ex4_pp4_0k[235]), //o-- + .sum(ex4_pp4_0s[236]), //o-- + .car(ex4_pp4_0c[235]) //o-- + ); + + + tri_csa42 csa4_0_235( + .vd(vdd), + .gd(gnd), + .a(ex4_pp3_0c[235]), //i-- + .b(ex4_pp3_0s[235]), //i-- + .c(ex4_pp3_1c[235]), //i-- + .d(ex4_pp3_1s[235]), //i-- + .ki(ex4_pp4_0k[235]), //i-- + .ko(ex4_pp4_0k[234]), //o-- + .sum(ex4_pp4_0s[235]), //o-- + .car(ex4_pp4_0c[234]) //o-- + ); + + + tri_csa42 csa4_0_234( + .vd(vdd), + .gd(gnd), + .a(ex4_pp3_0c[234]), //i-- + .b(ex4_pp3_0s[234]), //i-- + .c(ex4_pp3_1c[234]), //i-- + .d(ex4_pp3_1s[234]), //i-- + .ki(ex4_pp4_0k[234]), //i-- + .ko(ex4_pp4_0k[233]), //o-- + .sum(ex4_pp4_0s[234]), //o-- + .car(ex4_pp4_0c[233]) //o-- + ); + + + tri_csa42 csa4_0_233( + .vd(vdd), + .gd(gnd), + .a(ex4_pp3_0c[233]), //i-- + .b(ex4_pp3_0s[233]), //i-- + .c(ex4_pp3_1c[233]), //i-- + .d(ex4_pp3_1s[233]), //i-- + .ki(ex4_pp4_0k[233]), //i-- + .ko(ex4_pp4_0k[232]), //o-- + .sum(ex4_pp4_0s[233]), //o-- + .car(ex4_pp4_0c[232]) //o-- + ); + + + tri_csa42 csa4_0_232( + .vd(vdd), + .gd(gnd), + .a(ex4_pp3_0c[232]), //i-- + .b(ex4_pp3_0s[232]), //i-- + .c(ex4_pp3_1c[232]), //i-- + .d(ex4_pp3_1s[232]), //i-- + .ki(ex4_pp4_0k[232]), //i-- + .ko(ex4_pp4_0k[231]), //o-- + .sum(ex4_pp4_0s[232]), //o-- + .car(ex4_pp4_0c[231]) //o-- + ); + + + tri_csa42 csa4_0_231( + .vd(vdd), + .gd(gnd), + .a(ex4_pp3_0c[231]), //i-- + .b(ex4_pp3_0s[231]), //i-- + .c(ex4_pp3_1c[231]), //i-- + .d(ex4_pp3_1s[231]), //i-- + .ki(ex4_pp4_0k[231]), //i-- + .ko(ex4_pp4_0k[230]), //o-- + .sum(ex4_pp4_0s[231]), //o-- + .car(ex4_pp4_0c[230]) //o-- + ); + + + tri_csa42 csa4_0_230( + .vd(vdd), + .gd(gnd), + .a(ex4_pp3_0c[230]), //i-- + .b(ex4_pp3_0s[230]), //i-- + .c(ex4_pp3_1c[230]), //i-- + .d(ex4_pp3_1s[230]), //i-- + .ki(ex4_pp4_0k[230]), //i-- + .ko(ex4_pp4_0k[229]), //o-- + .sum(ex4_pp4_0s[230]), //o-- + .car(ex4_pp4_0c[229]) //o-- + ); + + + tri_csa42 csa4_0_229( + .vd(vdd), + .gd(gnd), + .a(ex4_pp3_0c[229]), //i-- + .b(ex4_pp3_0s[229]), //i-- + .c(ex4_pp3_1c[229]), //i-- + .d(ex4_pp3_1s[229]), //i-- + .ki(ex4_pp4_0k[229]), //i-- + .ko(ex4_pp4_0k[228]), //o-- + .sum(ex4_pp4_0s[229]), //o-- + .car(ex4_pp4_0c[228]) //o-- + ); + + + tri_csa42 csa4_0_228( + .vd(vdd), + .gd(gnd), + .a(ex4_pp3_0c[228]), //i-- + .b(ex4_pp3_0s[228]), //i-- + .c(ex4_pp3_1c[228]), //i-- + .d(ex4_pp3_1s[228]), //i-- + .ki(ex4_pp4_0k[228]), //i-- + .ko(ex4_pp4_0k[227]), //o-- + .sum(ex4_pp4_0s[228]), //o-- + .car(ex4_pp4_0c[227]) //o-- + ); + + + tri_csa42 csa4_0_227( + .vd(vdd), + .gd(gnd), + .a(ex4_pp3_0c[227]), //i-- + .b(ex4_pp3_0s[227]), //i-- + .c(ex4_pp3_1c[227]), //i-- + .d(ex4_pp3_1s[227]), //i-- + .ki(ex4_pp4_0k[227]), //i-- + .ko(ex4_pp4_0k[226]), //o-- + .sum(ex4_pp4_0s[227]), //o-- + .car(ex4_pp4_0c[226]) //o-- + ); + + + tri_csa42 csa4_0_226( + .vd(vdd), + .gd(gnd), + .a(ex4_pp3_0c[226]), //i-- + .b(ex4_pp3_0s[226]), //i-- + .c(ex4_pp3_1c[226]), //i-- + .d(ex4_pp3_1s[226]), //i-- + .ki(ex4_pp4_0k[226]), //i-- + .ko(ex4_pp4_0k[225]), //o-- + .sum(ex4_pp4_0s[226]), //o-- + .car(ex4_pp4_0c[225]) //o-- + ); + + + tri_csa42 csa4_0_225( + .vd(vdd), + .gd(gnd), + .a(ex4_pp3_0c[225]), //i-- + .b(ex4_pp3_0s[225]), //i-- + .c(ex4_pp3_1c[225]), //i-- + .d(ex4_pp3_1s[225]), //i-- + .ki(ex4_pp4_0k[225]), //i-- + .ko(ex4_pp4_0k[224]), //o-- + .sum(ex4_pp4_0s[225]), //o-- + .car(ex4_pp4_0c[224]) //o-- + ); + + + tri_csa42 csa4_0_224( + .vd(vdd), + .gd(gnd), + .a(ex4_pp3_0c[224]), //i-- + .b(ex4_pp3_0s[224]), //i-- + .c(ex4_pp3_1c[224]), //i-- + .d(ex4_pp3_1s[224]), //i-- + .ki(ex4_pp4_0k[224]), //i-- + .ko(ex4_pp4_0k[223]), //o-- + .sum(ex4_pp4_0s[224]), //o-- + .car(ex4_pp4_0c[223]) //o-- + ); + + + tri_csa42 csa4_0_223( + .vd(vdd), + .gd(gnd), + .a(ex4_pp3_0c[223]), //i-- + .b(ex4_pp3_0s[223]), //i-- + .c(ex4_pp3_1c[223]), //i-- + .d(ex4_pp3_1s[223]), //i-- + .ki(ex4_pp4_0k[223]), //i-- + .ko(ex4_pp4_0k[222]), //o-- + .sum(ex4_pp4_0s[223]), //o-- + .car(ex4_pp4_0c[222]) //o-- + ); + + + tri_csa42 csa4_0_222( + .vd(vdd), + .gd(gnd), + .a(ex4_pp3_0c[222]), //i-- + .b(ex4_pp3_0s[222]), //i-- + .c(ex4_pp3_1c[222]), //i-- + .d(ex4_pp3_1s[222]), //i-- + .ki(ex4_pp4_0k[222]), //i-- + .ko(ex4_pp4_0k[221]), //o-- + .sum(ex4_pp4_0s[222]), //o-- + .car(ex4_pp4_0c[221]) //o-- + ); + + + tri_csa42 csa4_0_221( + .vd(vdd), + .gd(gnd), + .a(ex4_pp3_0c[221]), //i-- + .b(ex4_pp3_0s[221]), //i-- + .c(ex4_pp3_1c[221]), //i-- + .d(ex4_pp3_1s[221]), //i-- + .ki(ex4_pp4_0k[221]), //i-- + .ko(ex4_pp4_0k[220]), //o-- + .sum(ex4_pp4_0s[221]), //o-- + .car(ex4_pp4_0c[220]) //o-- + ); + + + tri_csa42 csa4_0_220( + .vd(vdd), + .gd(gnd), + .a(ex4_pp3_0c[220]), //i-- + .b(ex4_pp3_0s[220]), //i-- + .c(ex4_pp3_1c[220]), //i-- + .d(ex4_pp3_1s[220]), //i-- + .ki(ex4_pp4_0k[220]), //i-- + .ko(ex4_pp4_0k[219]), //o-- + .sum(ex4_pp4_0s[220]), //o-- + .car(ex4_pp4_0c[219]) //o-- + ); + + + tri_csa42 csa4_0_219( + .vd(vdd), + .gd(gnd), + .a(ex4_pp3_0c[219]), //i-- + .b(ex4_pp3_0s[219]), //i-- + .c(ex4_pp3_1c[219]), //i-- + .d(ex4_pp3_1s[219]), //i-- + .ki(ex4_pp4_0k[219]), //i-- + .ko(ex4_pp4_0k[218]), //o-- + .sum(ex4_pp4_0s[219]), //o-- + .car(ex4_pp4_0c[218]) //o-- + ); + + + tri_csa42 csa4_0_218( + .vd(vdd), + .gd(gnd), + .a(ex4_pp3_0c[218]), //i-- + .b(ex4_pp3_0s[218]), //i-- + .c(ex4_pp3_1s[218]), //i-- + .d(1'b0), //i-- + .ki(ex4_pp4_0k[218]), //i-- + .ko(ex4_pp4_0k[217]), //o-- + .sum(ex4_pp4_0s[218]), //o-- + .car(ex4_pp4_0c[217]) //o-- + ); + + + tri_csa42 csa4_0_217( + .vd(vdd), + .gd(gnd), + .a(ex4_pp3_0c[217]), //i-- + .b(ex4_pp3_0s[217]), //i-- + .c(ex4_pp3_1s[217]), //i-- + .d(1'b0), //i-- + .ki(ex4_pp4_0k[217]), //i-- + .ko(ex4_pp4_0k[216]), //o-- + .sum(ex4_pp4_0s[217]), //o-- + .car(ex4_pp4_0c[216]) //o-- + ); + + + tri_csa42 csa4_0_216( + .vd(vdd), + .gd(gnd), + .a(ex4_pp3_0c[216]), //i-- + .b(ex4_pp3_0s[216]), //i-- + .c(ex4_pp3_1s[216]), //i-- + .d(1'b0), //i-- + .ki(ex4_pp4_0k[216]), //i-- + .ko(ex4_pp4_0k[215]), //o-- + .sum(ex4_pp4_0s[216]), //o-- + .car(ex4_pp4_0c[215]) //o-- + ); + + + tri_csa42 csa4_0_215( + .vd(vdd), + .gd(gnd), + .a(ex4_pp3_0c[215]), //i-- + .b(ex4_pp3_0s[215]), //i-- + .c(ex4_pp3_1s[215]), //i-- + .d(1'b0), //i-- + .ki(ex4_pp4_0k[215]), //i-- + .ko(ex4_pp4_0k[214]), //o-- + .sum(ex4_pp4_0s[215]), //o-- + .car(ex4_pp4_0c[214]) //o-- + ); + + + tri_csa42 csa4_0_214( + .vd(vdd), + .gd(gnd), + .a(ex4_pp3_0c[214]), //i-- + .b(ex4_pp3_0s[214]), //i-- + .c(ex4_pp3_1s[214]), //i-- + .d(1'b0), //i-- + .ki(ex4_pp4_0k[214]), //i-- + .ko(ex4_pp4_0k[213]), //o-- + .sum(ex4_pp4_0s[214]), //o-- + .car(ex4_pp4_0c[213]) //o-- + ); + + + tri_csa42 csa4_0_213( + .vd(vdd), + .gd(gnd), + .a(ex4_pp3_0c[213]), //i-- + .b(ex4_pp3_0s[213]), //i-- + .c(ex4_pp3_1s[213]), //i-- + .d(1'b0), //i-- + .ki(ex4_pp4_0k[213]), //i-- + .ko(ex4_pp4_0k[212]), //o-- + .sum(ex4_pp4_0s[213]), //o-- + .car(ex4_pp4_0c[212]) //o-- + ); + + + tri_csa42 csa4_0_212( + .vd(vdd), + .gd(gnd), + .a(ex4_pp3_0c[212]), //i-- + .b(ex4_pp3_0s[212]), //i-- + .c(ex4_pp3_1s[212]), //i-- + .d(1'b0), //i-- + .ki(ex4_pp4_0k[212]), //i-- + .ko(ex4_pp4_0k[211]), //o-- + .sum(ex4_pp4_0s[212]), //o-- + .car(ex4_pp4_0c[211]) //o-- + ); + + + tri_csa42 csa4_0_211( + .vd(vdd), + .gd(gnd), + .a(ex4_pp3_0c[211]), //i-- + .b(ex4_pp3_0s[211]), //i-- + .c(ex4_pp3_1s[211]), //i-- + .d(1'b0), //i-- + .ki(ex4_pp4_0k[211]), //i-- + .ko(ex4_pp4_0k[210]), //o-- + .sum(ex4_pp4_0s[211]), //o-- + .car(ex4_pp4_0c[210]) //o-- + ); + + + tri_csa42 csa4_0_210( + .vd(vdd), + .gd(gnd), + .a(ex4_pp3_0c[210]), //i-- + .b(ex4_pp3_0s[210]), //i-- + .c(ex4_pp3_1s[210]), //i-- + .d(1'b0), //i-- + .ki(ex4_pp4_0k[210]), //i-- + .ko(ex4_pp4_0k[209]), //o-- + .sum(ex4_pp4_0s[210]), //o-- + .car(ex4_pp4_0c[209]) //o-- + ); + + + tri_csa42 csa4_0_209( + .vd(vdd), + .gd(gnd), + .a(ex4_pp3_0c[209]), //i-- + .b(ex4_pp3_0s[209]), //i-- + .c(ex4_pp3_1s[209]), //i-- + .d(1'b0), //i-- + .ki(ex4_pp4_0k[209]), //i-- + .ko(ex4_pp4_0k[208]), //o-- + .sum(ex4_pp4_0s[209]), //o-- + .car(ex4_pp4_0c[208]) //o-- + ); + + + tri_csa42 csa4_0_208( + .vd(vdd), + .gd(gnd), + .a(ex4_pp3_0c[208]), //i-- + .b(ex4_pp3_0s[208]), //i-- + .c(ex4_pp3_1s[208]), //i-- + .d(1'b0), //i-- + .ki(ex4_pp4_0k[208]), //i-- + .ko(ex4_pp4_0k[207]), //o-- + .sum(ex4_pp4_0s[208]), //o-- + .car(ex4_pp4_0c[207]) //o-- + ); + + + tri_csa32 csa4_0_207( + .vd(vdd), + .gd(gnd), + .a(ex4_pp3_0c[207]), //i-- + .b(ex4_pp3_0s[207]), //i-- + .c(ex4_pp4_0k[207]), //i-- + .sum(ex4_pp4_0s[207]), //o-- + .car(ex4_pp4_0c[206]) //o-- + ); + + tri_csa22 csa4_0_206( + .a(ex4_pp3_0c[206]), //i-- + .b(ex4_pp3_0s[206]), //i-- + .sum(ex4_pp4_0s[206]), //o-- + .car(ex4_pp4_0c[205]) //o-- + ); + + tri_csa22 csa4_0_205( + .a(ex4_pp3_0c[205]), //i-- + .b(ex4_pp3_0s[205]), //i-- + .sum(ex4_pp4_0s[205]), //o-- + .car(ex4_pp4_0c[204]) //o-- + ); + + tri_csa22 csa4_0_204( + .a(ex4_pp3_0c[204]), //i-- + .b(ex4_pp3_0s[204]), //i-- + .sum(ex4_pp4_0s[204]), //o-- + .car(ex4_pp4_0c[203]) //o-- + ); + + tri_csa22 csa4_0_203( + .a(ex4_pp3_0c[203]), //i-- + .b(ex4_pp3_0s[203]), //i-- + .sum(ex4_pp4_0s[203]), //o-- + .car(ex4_pp4_0c[202]) //o-- + ); + + tri_csa22 csa4_0_202( + .a(ex4_pp3_0c[202]), //i-- + .b(ex4_pp3_0s[202]), //i-- + .sum(ex4_pp4_0s[202]), //o-- + .car(ex4_pp4_0c[201]) //o-- + ); + + tri_csa22 csa4_0_201( + .a(ex4_pp3_0c[201]), //i-- + .b(ex4_pp3_0s[201]), //i-- + .sum(ex4_pp4_0s[201]), //o-- + .car(ex4_pp4_0c[200]) //o-- + ); + + tri_csa22 csa4_0_200( + .a(ex4_pp3_0c[200]), //i-- + .b(ex4_pp3_0s[200]), //i-- + .sum(ex4_pp4_0s[200]), //o-- + .car(ex4_pp4_0c[199]) //o-- + ); + + tri_csa22 csa4_0_199( + .a(ex4_pp3_0c[199]), //i-- + .b(ex4_pp3_0s[199]), //i-- + .sum(ex4_pp4_0s[199]), //o-- + .car(ex4_pp4_0c[198]) //o-- + ); + + tri_csa22 csa4_0_198( + .a(ex4_pp3_0c[198]), //i-- + .b(ex4_pp3_0s[198]), //i-- + .sum(ex4_pp4_0s[198]), //o-- + .car(ex4_pp4_0c[197]) //o-- + ); + assign ex4_pp4_0s[197] = ex4_pp3_0c[197]; //pass_x_s + + //*********************************** + //** compression recycle + //*********************************** + + // g5 : for i in 196 to 264 generate + // + // csa5_0: entity c_prism_csa42 port map( + // a => ex4_pp4_0s(i) ,--i-- + // b => ex4_pp4_0c(i) ,--i-- + // c => ex4_recycle_s(i) ,--i-- + // d => ex4_recycle_c(i) ,--i-- + // ki => ex4_pp5_0k(i) ,--i-- + // ko => ex4_pp5_0k(i - 1) ,--o-- + // sum => ex4_pp5_0s(i) ,--o-- + // car => ex4_pp5_0c(i - 1) );--o-- + // + // end generate; + // + // ex4_pp5_0k(264) <= 0 ; + // ex4_pp5_0c(264) <= 0 ; + + //----- ----- + + + tri_csa22 csa5_0_264( + .a(ex4_pp4_0s[264]), //i-- + .b(ex4_recycle_s[264]), //i-- + .sum(ex4_pp5_0s[264]), //o-- + .car(ex4_pp5_0c[263]) //o-- + ); + + + tri_csa32 csa5_0_263( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0s[263]), //i-- + .b(ex4_recycle_c[263]), //i-- + .c(ex4_recycle_s[263]), //i-- + .sum(ex4_pp5_0s[263]), //o-- + .car(ex4_pp5_0c[262]) //o-- + ); + assign ex4_pp5_0k[262] = 0; //start_k + + + tri_csa42 csa5_0_262( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[262]), //i-- + .b(ex4_pp4_0s[262]), //i-- + .c(ex4_recycle_c[262]), //i-- + .d(ex4_recycle_s[262]), //i-- + .ki(ex4_pp5_0k[262]), //i-- + .ko(ex4_pp5_0k[261]), //o-- + .sum(ex4_pp5_0s[262]), //o-- + .car(ex4_pp5_0c[261]) //o-- + ); + + + tri_csa42 csa5_0_261( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[261]), //i-- + .b(ex4_pp4_0s[261]), //i-- + .c(ex4_recycle_c[261]), //i-- + .d(ex4_recycle_s[261]), //i-- + .ki(ex4_pp5_0k[261]), //i-- + .ko(ex4_pp5_0k[260]), //o-- + .sum(ex4_pp5_0s[261]), //o-- + .car(ex4_pp5_0c[260]) //o-- + ); + + + tri_csa42 csa5_0_260( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0s[260]), //i-- + .b(ex4_recycle_c[260]), //i-- + .c(ex4_recycle_s[260]), //i-- + .d(1'b0), //i-- + .ki(ex4_pp5_0k[260]), //i-- + .ko(ex4_pp5_0k[259]), //o-- + .sum(ex4_pp5_0s[260]), //o-- + .car(ex4_pp5_0c[259]) //o-- + ); + + + tri_csa42 csa5_0_259( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[259]), //i-- + .b(ex4_pp4_0s[259]), //i-- + .c(ex4_recycle_c[259]), //i-- + .d(ex4_recycle_s[259]), //i-- + .ki(ex4_pp5_0k[259]), //i-- + .ko(ex4_pp5_0k[258]), //o-- + .sum(ex4_pp5_0s[259]), //o-- + .car(ex4_pp5_0c[258]) //o-- + ); + + + tri_csa42 csa5_0_258( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[258]), //i-- + .b(ex4_pp4_0s[258]), //i-- + .c(ex4_recycle_c[258]), //i-- + .d(ex4_recycle_s[258]), //i-- + .ki(ex4_pp5_0k[258]), //i-- + .ko(ex4_pp5_0k[257]), //o-- + .sum(ex4_pp5_0s[258]), //o-- + .car(ex4_pp5_0c[257]) //o-- + ); + + + tri_csa42 csa5_0_257( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[257]), //i-- + .b(ex4_pp4_0s[257]), //i-- + .c(ex4_recycle_c[257]), //i-- + .d(ex4_recycle_s[257]), //i-- + .ki(ex4_pp5_0k[257]), //i-- + .ko(ex4_pp5_0k[256]), //o-- + .sum(ex4_pp5_0s[257]), //o-- + .car(ex4_pp5_0c[256]) //o-- + ); + + + tri_csa42 csa5_0_256( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[256]), //i-- + .b(ex4_pp4_0s[256]), //i-- + .c(ex4_recycle_c[256]), //i-- + .d(ex4_recycle_s[256]), //i-- + .ki(ex4_pp5_0k[256]), //i-- + .ko(ex4_pp5_0k[255]), //o-- + .sum(ex4_pp5_0s[256]), //o-- + .car(ex4_pp5_0c[255]) //o-- + ); + + + tri_csa42 csa5_0_255( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[255]), //i-- + .b(ex4_pp4_0s[255]), //i-- + .c(ex4_recycle_c[255]), //i-- + .d(ex4_recycle_s[255]), //i-- + .ki(ex4_pp5_0k[255]), //i-- + .ko(ex4_pp5_0k[254]), //o-- + .sum(ex4_pp5_0s[255]), //o-- + .car(ex4_pp5_0c[254]) //o-- + ); + + + tri_csa42 csa5_0_254( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0s[254]), //i-- + .b(ex4_recycle_c[254]), //i-- + .c(ex4_recycle_s[254]), //i-- + .d(1'b0), //i-- + .ki(ex4_pp5_0k[254]), //i-- + .ko(ex4_pp5_0k[253]), //o-- + .sum(ex4_pp5_0s[254]), //o-- + .car(ex4_pp5_0c[253]) //o-- + ); + + + tri_csa42 csa5_0_253( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[253]), //i-- + .b(ex4_pp4_0s[253]), //i-- + .c(ex4_recycle_c[253]), //i-- + .d(ex4_recycle_s[253]), //i-- + .ki(ex4_pp5_0k[253]), //i-- + .ko(ex4_pp5_0k[252]), //o-- + .sum(ex4_pp5_0s[253]), //o-- + .car(ex4_pp5_0c[252]) //o-- + ); + + + tri_csa42 csa5_0_252( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0s[252]), //i-- + .b(ex4_recycle_c[252]), //i-- + .c(ex4_recycle_s[252]), //i-- + .d(1'b0), //i-- + .ki(ex4_pp5_0k[252]), //i-- + .ko(ex4_pp5_0k[251]), //o-- + .sum(ex4_pp5_0s[252]), //o-- + .car(ex4_pp5_0c[251]) //o-- + ); + + + tri_csa42 csa5_0_251( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[251]), //i-- + .b(ex4_pp4_0s[251]), //i-- + .c(ex4_recycle_c[251]), //i-- + .d(ex4_recycle_s[251]), //i-- + .ki(ex4_pp5_0k[251]), //i-- + .ko(ex4_pp5_0k[250]), //o-- + .sum(ex4_pp5_0s[251]), //o-- + .car(ex4_pp5_0c[250]) //o-- + ); + + + tri_csa42 csa5_0_250( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[250]), //i-- + .b(ex4_pp4_0s[250]), //i-- + .c(ex4_recycle_c[250]), //i-- + .d(ex4_recycle_s[250]), //i-- + .ki(ex4_pp5_0k[250]), //i-- + .ko(ex4_pp5_0k[249]), //o-- + .sum(ex4_pp5_0s[250]), //o-- + .car(ex4_pp5_0c[249]) //o-- + ); + + + tri_csa42 csa5_0_249( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[249]), //i-- + .b(ex4_pp4_0s[249]), //i-- + .c(ex4_recycle_c[249]), //i-- + .d(ex4_recycle_s[249]), //i-- + .ki(ex4_pp5_0k[249]), //i-- + .ko(ex4_pp5_0k[248]), //o-- + .sum(ex4_pp5_0s[249]), //o-- + .car(ex4_pp5_0c[248]) //o-- + ); + + + tri_csa42 csa5_0_248( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[248]), //i-- + .b(ex4_pp4_0s[248]), //i-- + .c(ex4_recycle_c[248]), //i-- + .d(ex4_recycle_s[248]), //i-- + .ki(ex4_pp5_0k[248]), //i-- + .ko(ex4_pp5_0k[247]), //o-- + .sum(ex4_pp5_0s[248]), //o-- + .car(ex4_pp5_0c[247]) //o-- + ); + + + tri_csa42 csa5_0_247( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[247]), //i-- + .b(ex4_pp4_0s[247]), //i-- + .c(ex4_recycle_c[247]), //i-- + .d(ex4_recycle_s[247]), //i-- + .ki(ex4_pp5_0k[247]), //i-- + .ko(ex4_pp5_0k[246]), //o-- + .sum(ex4_pp5_0s[247]), //o-- + .car(ex4_pp5_0c[246]) //o-- + ); + + + tri_csa42 csa5_0_246( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[246]), //i-- + .b(ex4_pp4_0s[246]), //i-- + .c(ex4_recycle_c[246]), //i-- + .d(ex4_recycle_s[246]), //i-- + .ki(ex4_pp5_0k[246]), //i-- + .ko(ex4_pp5_0k[245]), //o-- + .sum(ex4_pp5_0s[246]), //o-- + .car(ex4_pp5_0c[245]) //o-- + ); + + + tri_csa42 csa5_0_245( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[245]), //i-- + .b(ex4_pp4_0s[245]), //i-- + .c(ex4_recycle_c[245]), //i-- + .d(ex4_recycle_s[245]), //i-- + .ki(ex4_pp5_0k[245]), //i-- + .ko(ex4_pp5_0k[244]), //o-- + .sum(ex4_pp5_0s[245]), //o-- + .car(ex4_pp5_0c[244]) //o-- + ); + + + tri_csa42 csa5_0_244( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[244]), //i-- + .b(ex4_pp4_0s[244]), //i-- + .c(ex4_recycle_c[244]), //i-- + .d(ex4_recycle_s[244]), //i-- + .ki(ex4_pp5_0k[244]), //i-- + .ko(ex4_pp5_0k[243]), //o-- + .sum(ex4_pp5_0s[244]), //o-- + .car(ex4_pp5_0c[243]) //o-- + ); + + + tri_csa42 csa5_0_243( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[243]), //i-- + .b(ex4_pp4_0s[243]), //i-- + .c(ex4_recycle_c[243]), //i-- + .d(ex4_recycle_s[243]), //i-- + .ki(ex4_pp5_0k[243]), //i-- + .ko(ex4_pp5_0k[242]), //o-- + .sum(ex4_pp5_0s[243]), //o-- + .car(ex4_pp5_0c[242]) //o-- + ); + + + tri_csa42 csa5_0_242( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[242]), //i-- + .b(ex4_pp4_0s[242]), //i-- + .c(ex4_recycle_c[242]), //i-- + .d(ex4_recycle_s[242]), //i-- + .ki(ex4_pp5_0k[242]), //i-- + .ko(ex4_pp5_0k[241]), //o-- + .sum(ex4_pp5_0s[242]), //o-- + .car(ex4_pp5_0c[241]) //o-- + ); + + + tri_csa42 csa5_0_241( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[241]), //i-- + .b(ex4_pp4_0s[241]), //i-- + .c(ex4_recycle_c[241]), //i-- + .d(ex4_recycle_s[241]), //i-- + .ki(ex4_pp5_0k[241]), //i-- + .ko(ex4_pp5_0k[240]), //o-- + .sum(ex4_pp5_0s[241]), //o-- + .car(ex4_pp5_0c[240]) //o-- + ); + + + tri_csa42 csa5_0_240( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[240]), //i-- + .b(ex4_pp4_0s[240]), //i-- + .c(ex4_recycle_c[240]), //i-- + .d(ex4_recycle_s[240]), //i-- + .ki(ex4_pp5_0k[240]), //i-- + .ko(ex4_pp5_0k[239]), //o-- + .sum(ex4_pp5_0s[240]), //o-- + .car(ex4_pp5_0c[239]) //o-- + ); + + + tri_csa42 csa5_0_239( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[239]), //i-- + .b(ex4_pp4_0s[239]), //i-- + .c(ex4_recycle_c[239]), //i-- + .d(ex4_recycle_s[239]), //i-- + .ki(ex4_pp5_0k[239]), //i-- + .ko(ex4_pp5_0k[238]), //o-- + .sum(ex4_pp5_0s[239]), //o-- + .car(ex4_pp5_0c[238]) //o-- + ); + + + tri_csa42 csa5_0_238( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[238]), //i-- + .b(ex4_pp4_0s[238]), //i-- + .c(ex4_recycle_c[238]), //i-- + .d(ex4_recycle_s[238]), //i-- + .ki(ex4_pp5_0k[238]), //i-- + .ko(ex4_pp5_0k[237]), //o-- + .sum(ex4_pp5_0s[238]), //o-- + .car(ex4_pp5_0c[237]) //o-- + ); + + + tri_csa42 csa5_0_237( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[237]), //i-- + .b(ex4_pp4_0s[237]), //i-- + .c(ex4_recycle_c[237]), //i-- + .d(ex4_recycle_s[237]), //i-- + .ki(ex4_pp5_0k[237]), //i-- + .ko(ex4_pp5_0k[236]), //o-- + .sum(ex4_pp5_0s[237]), //o-- + .car(ex4_pp5_0c[236]) //o-- + ); + + + tri_csa42 csa5_0_236( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[236]), //i-- + .b(ex4_pp4_0s[236]), //i-- + .c(ex4_recycle_c[236]), //i-- + .d(ex4_recycle_s[236]), //i-- + .ki(ex4_pp5_0k[236]), //i-- + .ko(ex4_pp5_0k[235]), //o-- + .sum(ex4_pp5_0s[236]), //o-- + .car(ex4_pp5_0c[235]) //o-- + ); + + + tri_csa42 csa5_0_235( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[235]), //i-- + .b(ex4_pp4_0s[235]), //i-- + .c(ex4_recycle_c[235]), //i-- + .d(ex4_recycle_s[235]), //i-- + .ki(ex4_pp5_0k[235]), //i-- + .ko(ex4_pp5_0k[234]), //o-- + .sum(ex4_pp5_0s[235]), //o-- + .car(ex4_pp5_0c[234]) //o-- + ); + + + tri_csa42 csa5_0_234( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[234]), //i-- + .b(ex4_pp4_0s[234]), //i-- + .c(ex4_recycle_c[234]), //i-- + .d(ex4_recycle_s[234]), //i-- + .ki(ex4_pp5_0k[234]), //i-- + .ko(ex4_pp5_0k[233]), //o-- + .sum(ex4_pp5_0s[234]), //o-- + .car(ex4_pp5_0c[233]) //o-- + ); + + + tri_csa42 csa5_0_233( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[233]), //i-- + .b(ex4_pp4_0s[233]), //i-- + .c(ex4_recycle_c[233]), //i-- + .d(ex4_recycle_s[233]), //i-- + .ki(ex4_pp5_0k[233]), //i-- + .ko(ex4_pp5_0k[232]), //o-- + .sum(ex4_pp5_0s[233]), //o-- + .car(ex4_pp5_0c[232]) //o-- + ); + + + tri_csa42 csa5_0_232( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[232]), //i-- + .b(ex4_pp4_0s[232]), //i-- + .c(ex4_recycle_c[232]), //i-- + .d(ex4_recycle_s[232]), //i-- + .ki(ex4_pp5_0k[232]), //i-- + .ko(ex4_pp5_0k[231]), //o-- + .sum(ex4_pp5_0s[232]), //o-- + .car(ex4_pp5_0c[231]) //o-- + ); + + + tri_csa42 csa5_0_231( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[231]), //i-- + .b(ex4_pp4_0s[231]), //i-- + .c(ex4_recycle_c[231]), //i-- + .d(ex4_recycle_s[231]), //i-- + .ki(ex4_pp5_0k[231]), //i-- + .ko(ex4_pp5_0k[230]), //o-- + .sum(ex4_pp5_0s[231]), //o-- + .car(ex4_pp5_0c[230]) //o-- + ); + + + tri_csa42 csa5_0_230( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[230]), //i-- + .b(ex4_pp4_0s[230]), //i-- + .c(ex4_recycle_c[230]), //i-- + .d(ex4_recycle_s[230]), //i-- + .ki(ex4_pp5_0k[230]), //i-- + .ko(ex4_pp5_0k[229]), //o-- + .sum(ex4_pp5_0s[230]), //o-- + .car(ex4_pp5_0c[229]) //o-- + ); + + + tri_csa42 csa5_0_229( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[229]), //i-- + .b(ex4_pp4_0s[229]), //i-- + .c(ex4_recycle_c[229]), //i-- + .d(ex4_recycle_s[229]), //i-- + .ki(ex4_pp5_0k[229]), //i-- + .ko(ex4_pp5_0k[228]), //o-- + .sum(ex4_pp5_0s[229]), //o-- + .car(ex4_pp5_0c[228]) //o-- + ); + + + tri_csa42 csa5_0_228( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[228]), //i-- + .b(ex4_pp4_0s[228]), //i-- + .c(ex4_recycle_c[228]), //i-- + .d(ex4_recycle_s[228]), //i-- + .ki(ex4_pp5_0k[228]), //i-- + .ko(ex4_pp5_0k[227]), //o-- + .sum(ex4_pp5_0s[228]), //o-- + .car(ex4_pp5_0c[227]) //o-- + ); + + + tri_csa42 csa5_0_227( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[227]), //i-- + .b(ex4_pp4_0s[227]), //i-- + .c(ex4_recycle_c[227]), //i-- + .d(ex4_recycle_s[227]), //i-- + .ki(ex4_pp5_0k[227]), //i-- + .ko(ex4_pp5_0k[226]), //o-- + .sum(ex4_pp5_0s[227]), //o-- + .car(ex4_pp5_0c[226]) //o-- + ); + + + tri_csa42 csa5_0_226( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[226]), //i-- + .b(ex4_pp4_0s[226]), //i-- + .c(ex4_recycle_c[226]), //i-- + .d(ex4_recycle_s[226]), //i-- + .ki(ex4_pp5_0k[226]), //i-- + .ko(ex4_pp5_0k[225]), //o-- + .sum(ex4_pp5_0s[226]), //o-- + .car(ex4_pp5_0c[225]) //o-- + ); + + + tri_csa42 csa5_0_225( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[225]), //i-- + .b(ex4_pp4_0s[225]), //i-- + .c(ex4_recycle_c[225]), //i-- + .d(ex4_recycle_s[225]), //i-- + .ki(ex4_pp5_0k[225]), //i-- + .ko(ex4_pp5_0k[224]), //o-- + .sum(ex4_pp5_0s[225]), //o-- + .car(ex4_pp5_0c[224]) //o-- + ); + + + tri_csa42 csa5_0_224( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[224]), //i-- + .b(ex4_pp4_0s[224]), //i-- + .c(ex4_recycle_c[224]), //i-- + .d(ex4_recycle_s[224]), //i-- + .ki(ex4_pp5_0k[224]), //i-- + .ko(ex4_pp5_0k[223]), //o-- + .sum(ex4_pp5_0s[224]), //o-- + .car(ex4_pp5_0c[223]) //o-- + ); + + + tri_csa42 csa5_0_223( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[223]), //i-- + .b(ex4_pp4_0s[223]), //i-- + .c(ex4_recycle_c[223]), //i-- + .d(ex4_recycle_s[223]), //i-- + .ki(ex4_pp5_0k[223]), //i-- + .ko(ex4_pp5_0k[222]), //o-- + .sum(ex4_pp5_0s[223]), //o-- + .car(ex4_pp5_0c[222]) //o-- + ); + + + tri_csa42 csa5_0_222( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[222]), //i-- + .b(ex4_pp4_0s[222]), //i-- + .c(ex4_recycle_c[222]), //i-- + .d(ex4_recycle_s[222]), //i-- + .ki(ex4_pp5_0k[222]), //i-- + .ko(ex4_pp5_0k[221]), //o-- + .sum(ex4_pp5_0s[222]), //o-- + .car(ex4_pp5_0c[221]) //o-- + ); + + + tri_csa42 csa5_0_221( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[221]), //i-- + .b(ex4_pp4_0s[221]), //i-- + .c(ex4_recycle_c[221]), //i-- + .d(ex4_recycle_s[221]), //i-- + .ki(ex4_pp5_0k[221]), //i-- + .ko(ex4_pp5_0k[220]), //o-- + .sum(ex4_pp5_0s[221]), //o-- + .car(ex4_pp5_0c[220]) //o-- + ); + + + tri_csa42 csa5_0_220( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[220]), //i-- + .b(ex4_pp4_0s[220]), //i-- + .c(ex4_recycle_c[220]), //i-- + .d(ex4_recycle_s[220]), //i-- + .ki(ex4_pp5_0k[220]), //i-- + .ko(ex4_pp5_0k[219]), //o-- + .sum(ex4_pp5_0s[220]), //o-- + .car(ex4_pp5_0c[219]) //o-- + ); + + + tri_csa42 csa5_0_219( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[219]), //i-- + .b(ex4_pp4_0s[219]), //i-- + .c(ex4_recycle_c[219]), //i-- + .d(ex4_recycle_s[219]), //i-- + .ki(ex4_pp5_0k[219]), //i-- + .ko(ex4_pp5_0k[218]), //o-- + .sum(ex4_pp5_0s[219]), //o-- + .car(ex4_pp5_0c[218]) //o-- + ); + + + tri_csa42 csa5_0_218( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[218]), //i-- + .b(ex4_pp4_0s[218]), //i-- + .c(ex4_recycle_c[218]), //i-- + .d(ex4_recycle_s[218]), //i-- + .ki(ex4_pp5_0k[218]), //i-- + .ko(ex4_pp5_0k[217]), //o-- + .sum(ex4_pp5_0s[218]), //o-- + .car(ex4_pp5_0c[217]) //o-- + ); + + + tri_csa42 csa5_0_217( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[217]), //i-- + .b(ex4_pp4_0s[217]), //i-- + .c(ex4_recycle_c[217]), //i-- + .d(ex4_recycle_s[217]), //i-- + .ki(ex4_pp5_0k[217]), //i-- + .ko(ex4_pp5_0k[216]), //o-- + .sum(ex4_pp5_0s[217]), //o-- + .car(ex4_pp5_0c[216]) //o-- + ); + + + tri_csa42 csa5_0_216( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[216]), //i-- + .b(ex4_pp4_0s[216]), //i-- + .c(ex4_recycle_c[216]), //i-- + .d(ex4_recycle_s[216]), //i-- + .ki(ex4_pp5_0k[216]), //i-- + .ko(ex4_pp5_0k[215]), //o-- + .sum(ex4_pp5_0s[216]), //o-- + .car(ex4_pp5_0c[215]) //o-- + ); + + + tri_csa42 csa5_0_215( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[215]), //i-- + .b(ex4_pp4_0s[215]), //i-- + .c(ex4_recycle_c[215]), //i-- + .d(ex4_recycle_s[215]), //i-- + .ki(ex4_pp5_0k[215]), //i-- + .ko(ex4_pp5_0k[214]), //o-- + .sum(ex4_pp5_0s[215]), //o-- + .car(ex4_pp5_0c[214]) //o-- + ); + + + tri_csa42 csa5_0_214( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[214]), //i-- + .b(ex4_pp4_0s[214]), //i-- + .c(ex4_recycle_c[214]), //i-- + .d(ex4_recycle_s[214]), //i-- + .ki(ex4_pp5_0k[214]), //i-- + .ko(ex4_pp5_0k[213]), //o-- + .sum(ex4_pp5_0s[214]), //o-- + .car(ex4_pp5_0c[213]) //o-- + ); + + + tri_csa42 csa5_0_213( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[213]), //i-- + .b(ex4_pp4_0s[213]), //i-- + .c(ex4_recycle_c[213]), //i-- + .d(ex4_recycle_s[213]), //i-- + .ki(ex4_pp5_0k[213]), //i-- + .ko(ex4_pp5_0k[212]), //o-- + .sum(ex4_pp5_0s[213]), //o-- + .car(ex4_pp5_0c[212]) //o-- + ); + + + tri_csa42 csa5_0_212( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[212]), //i-- + .b(ex4_pp4_0s[212]), //i-- + .c(ex4_recycle_c[212]), //i-- + .d(ex4_recycle_s[212]), //i-- + .ki(ex4_pp5_0k[212]), //i-- + .ko(ex4_pp5_0k[211]), //o-- + .sum(ex4_pp5_0s[212]), //o-- + .car(ex4_pp5_0c[211]) //o-- + ); + + + tri_csa42 csa5_0_211( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[211]), //i-- + .b(ex4_pp4_0s[211]), //i-- + .c(ex4_recycle_c[211]), //i-- + .d(ex4_recycle_s[211]), //i-- + .ki(ex4_pp5_0k[211]), //i-- + .ko(ex4_pp5_0k[210]), //o-- + .sum(ex4_pp5_0s[211]), //o-- + .car(ex4_pp5_0c[210]) //o-- + ); + + + tri_csa42 csa5_0_210( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[210]), //i-- + .b(ex4_pp4_0s[210]), //i-- + .c(ex4_recycle_c[210]), //i-- + .d(ex4_recycle_s[210]), //i-- + .ki(ex4_pp5_0k[210]), //i-- + .ko(ex4_pp5_0k[209]), //o-- + .sum(ex4_pp5_0s[210]), //o-- + .car(ex4_pp5_0c[209]) //o-- + ); + + + tri_csa42 csa5_0_209( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[209]), //i-- + .b(ex4_pp4_0s[209]), //i-- + .c(ex4_recycle_c[209]), //i-- + .d(ex4_recycle_s[209]), //i-- + .ki(ex4_pp5_0k[209]), //i-- + .ko(ex4_pp5_0k[208]), //o-- + .sum(ex4_pp5_0s[209]), //o-- + .car(ex4_pp5_0c[208]) //o-- + ); + + + tri_csa42 csa5_0_208( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[208]), //i-- + .b(ex4_pp4_0s[208]), //i-- + .c(ex4_recycle_c[208]), //i-- + .d(ex4_recycle_s[208]), //i-- + .ki(ex4_pp5_0k[208]), //i-- + .ko(ex4_pp5_0k[207]), //o-- + .sum(ex4_pp5_0s[208]), //o-- + .car(ex4_pp5_0c[207]) //o-- + ); + + + tri_csa42 csa5_0_207( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[207]), //i-- + .b(ex4_pp4_0s[207]), //i-- + .c(ex4_recycle_c[207]), //i-- + .d(ex4_recycle_s[207]), //i-- + .ki(ex4_pp5_0k[207]), //i-- + .ko(ex4_pp5_0k[206]), //o-- + .sum(ex4_pp5_0s[207]), //o-- + .car(ex4_pp5_0c[206]) //o-- + ); + + + tri_csa42 csa5_0_206( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[206]), //i-- + .b(ex4_pp4_0s[206]), //i-- + .c(ex4_recycle_c[206]), //i-- + .d(ex4_recycle_s[206]), //i-- + .ki(ex4_pp5_0k[206]), //i-- + .ko(ex4_pp5_0k[205]), //o-- + .sum(ex4_pp5_0s[206]), //o-- + .car(ex4_pp5_0c[205]) //o-- + ); + + + tri_csa42 csa5_0_205( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[205]), //i-- + .b(ex4_pp4_0s[205]), //i-- + .c(ex4_recycle_c[205]), //i-- + .d(ex4_recycle_s[205]), //i-- + .ki(ex4_pp5_0k[205]), //i-- + .ko(ex4_pp5_0k[204]), //o-- + .sum(ex4_pp5_0s[205]), //o-- + .car(ex4_pp5_0c[204]) //o-- + ); + + + tri_csa42 csa5_0_204( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[204]), //i-- + .b(ex4_pp4_0s[204]), //i-- + .c(ex4_recycle_c[204]), //i-- + .d(ex4_recycle_s[204]), //i-- + .ki(ex4_pp5_0k[204]), //i-- + .ko(ex4_pp5_0k[203]), //o-- + .sum(ex4_pp5_0s[204]), //o-- + .car(ex4_pp5_0c[203]) //o-- + ); + + + tri_csa42 csa5_0_203( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[203]), //i-- + .b(ex4_pp4_0s[203]), //i-- + .c(ex4_recycle_c[203]), //i-- + .d(ex4_recycle_s[203]), //i-- + .ki(ex4_pp5_0k[203]), //i-- + .ko(ex4_pp5_0k[202]), //o-- + .sum(ex4_pp5_0s[203]), //o-- + .car(ex4_pp5_0c[202]) //o-- + ); + + + tri_csa42 csa5_0_202( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[202]), //i-- + .b(ex4_pp4_0s[202]), //i-- + .c(ex4_recycle_c[202]), //i-- + .d(ex4_recycle_s[202]), //i-- + .ki(ex4_pp5_0k[202]), //i-- + .ko(ex4_pp5_0k[201]), //o-- + .sum(ex4_pp5_0s[202]), //o-- + .car(ex4_pp5_0c[201]) //o-- + ); + + + tri_csa42 csa5_0_201( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[201]), //i-- + .b(ex4_pp4_0s[201]), //i-- + .c(ex4_recycle_c[201]), //i-- + .d(ex4_recycle_s[201]), //i-- + .ki(ex4_pp5_0k[201]), //i-- + .ko(ex4_pp5_0k[200]), //o-- + .sum(ex4_pp5_0s[201]), //o-- + .car(ex4_pp5_0c[200]) //o-- + ); + + + tri_csa42 csa5_0_200( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[200]), //i-- + .b(ex4_pp4_0s[200]), //i-- + .c(ex4_recycle_c[200]), //i-- + .d(ex4_recycle_s[200]), //i-- + .ki(ex4_pp5_0k[200]), //i-- + .ko(ex4_pp5_0k[199]), //o-- + .sum(ex4_pp5_0s[200]), //o-- + .car(ex4_pp5_0c[199]) //o-- + ); + + + tri_csa42 csa5_0_199( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[199]), //i-- + .b(ex4_pp4_0s[199]), //i-- + .c(ex4_recycle_c[199]), //i-- + .d(ex4_recycle_s[199]), //i-- + .ki(ex4_pp5_0k[199]), //i-- + .ko(ex4_pp5_0k[198]), //o-- + .sum(ex4_pp5_0s[199]), //o-- + .car(ex4_pp5_0c[198]) //o-- + ); + + + tri_csa42 csa5_0_198( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[198]), //i-- + .b(ex4_pp4_0s[198]), //i-- + .c(ex4_recycle_c[198]), //i-- + .d(ex4_recycle_s[198]), //i-- + .ki(ex4_pp5_0k[198]), //i-- + .ko(ex4_pp5_0k[197]), //o-- + .sum(ex4_pp5_0s[198]), //o-- + .car(ex4_pp5_0c[197]) //o-- + ); + + + tri_csa42 csa5_0_197( + .vd(vdd), + .gd(gnd), + .a(ex4_pp4_0c[197]), //i-- + .b(ex4_pp4_0s[197]), //i-- + .c(ex4_recycle_c[197]), //i-- + .d(ex4_recycle_s[197]), //i-- + .ki(ex4_pp5_0k[197]), //i-- + .ko(ex4_pp5_0k[196]), //o-- + .sum(ex4_pp5_0s[197]), //o-- + .car(ex4_pp5_0c[196]) //o-- + ); + + + tri_csa32 csa5_0_196( + .vd(vdd), + .gd(gnd), + .a(ex4_recycle_c[196]), //i-- + .b(ex4_recycle_s[196]), //i-- + .c(ex4_pp5_0k[196]), //i-- + .sum(ex4_pp5_0s[196]), //o-- + .car(ex4_pp5_0c[195]) //o-- + ); + + assign ex5_pp5_0s_din[196:264] = ex4_pp5_0s[196:264]; + assign ex5_pp5_0c_din[196:263] = ex4_pp5_0c[196:263]; + + //================================================================================== + //== EX4 (adder ... 64 bit) part of overflow detection + //================================================================================== + + assign ex5_pp5_0s[196:264] = (~ex5_pp5_0s_q_b[196:264]); + assign ex5_pp5_0c[196:263] = (~ex5_pp5_0c_q_b[196:263]); + + assign ex5_pp5_0s_out[196:264] = ex5_pp5_0s[196:264]; //output-- + assign ex5_pp5_0c_out[196:263] = ex5_pp5_0c[196:263]; //output-- + + //================================================================================== + //== Pervasive stuff + //================================================================================== + + + tri_lcbnd ex4_lcb( + .delay_lclkr(delay_lclkr_dc), //in -- 0 , + .mpw1_b(mpw1_dc_b), //in -- 0 , + .mpw2_b(mpw2_dc_b), //in -- 0 , + .force_t(func_sl_force), //in -- 0 , + .nclk(nclk), //in + .vd(vdd), //inout + .gd(gnd), //inout + .act(ex3_act), //in + .sg(sg_0), //in + .thold_b(func_sl_thold_0_b), //in + .d1clk(ex4_d1clk), //out + .d2clk(ex4_d2clk), //out + .lclk(ex4_lclk) //out + ); + + + tri_lcbnd ex5_lcb( + .delay_lclkr(delay_lclkr_dc), //in -- 0 , + .mpw1_b(mpw1_dc_b), //in -- 0 , + .mpw2_b(mpw2_dc_b), //in -- 0 , + .force_t(func_sl_force), //in -- 0 , + .nclk(nclk), //in + .vd(vdd), //inout + .gd(gnd), //inout + .act(ex4_act), //in + .sg(sg_0), //in + .thold_b(func_sl_thold_0_b), //in + .d1clk(ex5_d1clk), //out + .d2clk(ex5_d2clk), //out + .lclk(ex5_lclk) //out + ); + + //================================================================================== + //== Latches + //================================================================================== + + + tri_inv_nlats #(.WIDTH(45), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) ex4_pp2_0s_lat( + .vd(vdd), //inout + .gd(gnd), //inout + .lclk(ex4_lclk), //lclk.clk + .d1clk(ex4_d1clk), + .d2clk(ex4_d2clk), + .scanin(ex4_pp2_0s_lat_si), + .scanout(ex4_pp2_0s_lat_so), + .d(ex4_pp2_0s_din[198:242]), + .qb(ex4_pp2_0s_q_b[198:242]) + ); + + tri_inv_nlats #(.WIDTH(43), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) ex4_pp2_0c_lat( + .vd(vdd), //inout + .gd(gnd), //inout + .lclk(ex4_lclk), //lclk.clk + .d1clk(ex4_d1clk), + .d2clk(ex4_d2clk), + .scanin(ex4_pp2_0c_lat_si), + .scanout(ex4_pp2_0c_lat_so), + .d(ex4_pp2_0c_din[198:240]), + .qb(ex4_pp2_0c_q_b[198:240]) + ); + + + tri_inv_nlats #(.WIDTH(47), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) ex4_pp2_1s_lat( + .vd(vdd), //inout + .gd(gnd), //inout + .lclk(ex4_lclk), //lclk.clk + .d1clk(ex4_d1clk), + .d2clk(ex4_d2clk), + .scanin(ex4_pp2_1s_lat_si), + .scanout(ex4_pp2_1s_lat_so), + .d(ex4_pp2_1s_din[208:254]), + .qb(ex4_pp2_1s_q_b[208:254]) + ); + + + tri_inv_nlats #(.WIDTH(45), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) ex4_pp2_1c_lat( + .vd(vdd), //inout + .gd(gnd), //inout + .lclk(ex4_lclk), //lclk.clk + .d1clk(ex4_d1clk), + .d2clk(ex4_d2clk), + .scanin(ex4_pp2_1c_lat_si), + .scanout(ex4_pp2_1c_lat_so), + .d(ex4_pp2_1c_din[208:252]), + .qb(ex4_pp2_1c_q_b[208:252]) + ); + + + tri_inv_nlats #(.WIDTH(45), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) ex4_pp2_2s_lat( + .vd(vdd), //inout + .gd(gnd), //inout + .lclk(ex4_lclk), //lclk.clk + .d1clk(ex4_d1clk), + .d2clk(ex4_d2clk), + .scanin(ex4_pp2_2s_lat_si), + .scanout(ex4_pp2_2s_lat_so), + .d(ex4_pp2_2s_din[220:264]), + .qb(ex4_pp2_2s_q_b[220:264]) + ); + + + tri_inv_nlats #(.WIDTH(44), .BTR("NLI0001_X1_A12TH"), .NEEDS_SRESET(0)) ex4_pp2_2c_lat( + .vd(vdd), //inout + .gd(gnd), //inout + .lclk(ex4_lclk), //lclk.clk + .d1clk(ex4_d1clk), + .d2clk(ex4_d2clk), + .scanin(ex4_pp2_2c_lat_si), + .scanout(ex4_pp2_2c_lat_so), + .d(ex4_pp2_2c_din[220:263]), + .qb(ex4_pp2_2c_q_b[220:263]) + ); + + + tri_inv_nlats #(.WIDTH(69), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(0)) ex5_pp5_0s_lat( + .vd(vdd), //inout + .gd(gnd), //inout + .lclk(ex5_lclk), //lclk.clk + .d1clk(ex5_d1clk), + .d2clk(ex5_d2clk), + .scanin(ex5_pp5_0s_lat_si), + .scanout(ex5_pp5_0s_lat_so), + .d(ex5_pp5_0s_din[196:264]), + .qb(ex5_pp5_0s_q_b[196:264]) + ); + + + tri_inv_nlats #(.WIDTH(68), .BTR("NLI0001_X2_A12TH"), .NEEDS_SRESET(0)) ex5_pp5_0c_lat( + .vd(vdd), //inout + .gd(gnd), //inout + .lclk(ex5_lclk), //lclk.clk + .d1clk(ex5_d1clk), + .d2clk(ex5_d2clk), + .scanin(ex5_pp5_0c_lat_si), + .scanout(ex5_pp5_0c_lat_so), + .d(ex5_pp5_0c_din[196:263]), + .qb(ex5_pp5_0c_q_b[196:263]) + ); + + //================================================================================== + //== scan string (serpentine) + //================================================================================== + + assign ex4_pp2_0s_lat_si[198:242] = {scan_in, ex4_pp2_0s_lat_so[198:241]}; + assign ex4_pp2_0c_lat_si[198:240] = {ex4_pp2_0c_lat_so[199:240], ex4_pp2_0s_lat_so[242]}; + assign ex4_pp2_1s_lat_si[208:254] = {ex4_pp2_0c_lat_so[198], ex4_pp2_1s_lat_so[208:253]}; + assign ex4_pp2_1c_lat_si[208:252] = {ex4_pp2_1c_lat_so[209:252], ex4_pp2_1s_lat_so[254]}; + assign ex4_pp2_2s_lat_si[220:264] = {ex4_pp2_1c_lat_so[208], ex4_pp2_2s_lat_so[220:263]}; + assign ex4_pp2_2c_lat_si[220:263] = {ex4_pp2_2c_lat_so[221:263], ex4_pp2_2s_lat_so[264]}; + + assign ex5_pp5_0s_lat_si[196:264] = {ex4_pp2_2c_lat_so[220], ex5_pp5_0s_lat_so[196:263]}; + assign ex5_pp5_0c_lat_si[196:263] = {ex5_pp5_0c_lat_so[197:263], ex5_pp5_0s_lat_so[264]}; + + assign scan_out = ex5_pp5_0c_lat_so[196]; + + + +endmodule diff --git a/dev/verilog/trilib/tri_st_or3232.v b/dev/verilog/trilib/tri_st_or3232.v new file mode 100755 index 0000000..2e446e3 --- /dev/null +++ b/dev/verilog/trilib/tri_st_or3232.v @@ -0,0 +1,120 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: XU ALU or reduce component +// +//***************************************************************************** +module tri_st_or3232( + d, + or_hi_b, + or_lo_b +); + input [0:63] d; //data + output or_hi_b; // upper 32 ORed together + output or_lo_b; // lower 32 ORed together + + + wire [0:31] or_lv1_b; + wire [0:15] or_lv2; + wire [0:7] or_lv3_b; + wire [0:3] or_lv4; + wire [0:1] or_lv5_b; + + assign or_lv1_b[0] = (~(d[0] | d[1])); + assign or_lv1_b[1] = (~(d[2] | d[3])); + assign or_lv1_b[2] = (~(d[4] | d[5])); + assign or_lv1_b[3] = (~(d[6] | d[7])); + assign or_lv1_b[4] = (~(d[8] | d[9])); + assign or_lv1_b[5] = (~(d[10] | d[11])); + assign or_lv1_b[6] = (~(d[12] | d[13])); + assign or_lv1_b[7] = (~(d[14] | d[15])); + assign or_lv1_b[8] = (~(d[16] | d[17])); + assign or_lv1_b[9] = (~(d[18] | d[19])); + assign or_lv1_b[10] = (~(d[20] | d[21])); + assign or_lv1_b[11] = (~(d[22] | d[23])); + assign or_lv1_b[12] = (~(d[24] | d[25])); + assign or_lv1_b[13] = (~(d[26] | d[27])); + assign or_lv1_b[14] = (~(d[28] | d[29])); + assign or_lv1_b[15] = (~(d[30] | d[31])); + assign or_lv1_b[16] = (~(d[32] | d[33])); + assign or_lv1_b[17] = (~(d[34] | d[35])); + assign or_lv1_b[18] = (~(d[36] | d[37])); + assign or_lv1_b[19] = (~(d[38] | d[39])); + assign or_lv1_b[20] = (~(d[40] | d[41])); + assign or_lv1_b[21] = (~(d[42] | d[43])); + assign or_lv1_b[22] = (~(d[44] | d[45])); + assign or_lv1_b[23] = (~(d[46] | d[47])); + assign or_lv1_b[24] = (~(d[48] | d[49])); + assign or_lv1_b[25] = (~(d[50] | d[51])); + assign or_lv1_b[26] = (~(d[52] | d[53])); + assign or_lv1_b[27] = (~(d[54] | d[55])); + assign or_lv1_b[28] = (~(d[56] | d[57])); + assign or_lv1_b[29] = (~(d[58] | d[59])); + assign or_lv1_b[30] = (~(d[60] | d[61])); + assign or_lv1_b[31] = (~(d[62] | d[63])); + + assign or_lv2[0] = (~(or_lv1_b[0] & or_lv1_b[1])); + assign or_lv2[1] = (~(or_lv1_b[2] & or_lv1_b[3])); + assign or_lv2[2] = (~(or_lv1_b[4] & or_lv1_b[5])); + assign or_lv2[3] = (~(or_lv1_b[6] & or_lv1_b[7])); + assign or_lv2[4] = (~(or_lv1_b[8] & or_lv1_b[9])); + assign or_lv2[5] = (~(or_lv1_b[10] & or_lv1_b[11])); + assign or_lv2[6] = (~(or_lv1_b[12] & or_lv1_b[13])); + assign or_lv2[7] = (~(or_lv1_b[14] & or_lv1_b[15])); + assign or_lv2[8] = (~(or_lv1_b[16] & or_lv1_b[17])); + assign or_lv2[9] = (~(or_lv1_b[18] & or_lv1_b[19])); + assign or_lv2[10] = (~(or_lv1_b[20] & or_lv1_b[21])); + assign or_lv2[11] = (~(or_lv1_b[22] & or_lv1_b[23])); + assign or_lv2[12] = (~(or_lv1_b[24] & or_lv1_b[25])); + assign or_lv2[13] = (~(or_lv1_b[26] & or_lv1_b[27])); + assign or_lv2[14] = (~(or_lv1_b[28] & or_lv1_b[29])); + assign or_lv2[15] = (~(or_lv1_b[30] & or_lv1_b[31])); + + assign or_lv3_b[0] = (~(or_lv2[0] | or_lv2[1])); + assign or_lv3_b[1] = (~(or_lv2[2] | or_lv2[3])); + assign or_lv3_b[2] = (~(or_lv2[4] | or_lv2[5])); + assign or_lv3_b[3] = (~(or_lv2[6] | or_lv2[7])); + assign or_lv3_b[4] = (~(or_lv2[8] | or_lv2[9])); + assign or_lv3_b[5] = (~(or_lv2[10] | or_lv2[11])); + assign or_lv3_b[6] = (~(or_lv2[12] | or_lv2[13])); + assign or_lv3_b[7] = (~(or_lv2[14] | or_lv2[15])); + + assign or_lv4[0] = (~(or_lv3_b[0] & or_lv3_b[1])); + assign or_lv4[1] = (~(or_lv3_b[2] & or_lv3_b[3])); + assign or_lv4[2] = (~(or_lv3_b[4] & or_lv3_b[5])); + assign or_lv4[3] = (~(or_lv3_b[6] & or_lv3_b[7])); + + assign or_lv5_b[0] = (~(or_lv4[0] | or_lv4[1])); + assign or_lv5_b[1] = (~(or_lv4[2] | or_lv4[3])); + + assign or_hi_b = or_lv5_b[0]; // rename --output-- + assign or_lo_b = or_lv5_b[1]; // rename --output-- + +endmodule diff --git a/dev/verilog/trilib/tri_st_or3232_b.v b/dev/verilog/trilib/tri_st_or3232_b.v new file mode 100755 index 0000000..28605cd --- /dev/null +++ b/dev/verilog/trilib/tri_st_or3232_b.v @@ -0,0 +1,188 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: XU Merge Or-Reduce Component +// +//***************************************************************************** +module tri_st_or3232_b( + d_b, + or_hi, + or_lo +); + + input [0:63] d_b; //data + output or_hi; // upper 32 ORed together + output or_lo; // lower 32 ORed together + + + wire [0:31] ca_or_lv1; + wire [0:15] ca_or_lv2_b; + wire [0:7] ca_or_lv3; + wire [0:3] ca_or_lv4_b; + wire [0:1] ca_or_lv5; + + + assign ca_or_lv1[0] = (~(d_b[0] & d_b[1])); + assign ca_or_lv1[1] = (~(d_b[2] & d_b[3])); + assign ca_or_lv1[2] = (~(d_b[4] & d_b[5])); + assign ca_or_lv1[3] = (~(d_b[6] & d_b[7])); + assign ca_or_lv1[4] = (~(d_b[8] & d_b[9])); + assign ca_or_lv1[5] = (~(d_b[10] & d_b[11])); + assign ca_or_lv1[6] = (~(d_b[12] & d_b[13])); + assign ca_or_lv1[7] = (~(d_b[14] & d_b[15])); + assign ca_or_lv1[8] = (~(d_b[16] & d_b[17])); + assign ca_or_lv1[9] = (~(d_b[18] & d_b[19])); + assign ca_or_lv1[10] = (~(d_b[20] & d_b[21])); + assign ca_or_lv1[11] = (~(d_b[22] & d_b[23])); + assign ca_or_lv1[12] = (~(d_b[24] & d_b[25])); + assign ca_or_lv1[13] = (~(d_b[26] & d_b[27])); + assign ca_or_lv1[14] = (~(d_b[28] & d_b[29])); + assign ca_or_lv1[15] = (~(d_b[30] & d_b[31])); + assign ca_or_lv1[16] = (~(d_b[32] & d_b[33])); + assign ca_or_lv1[17] = (~(d_b[34] & d_b[35])); + assign ca_or_lv1[18] = (~(d_b[36] & d_b[37])); + assign ca_or_lv1[19] = (~(d_b[38] & d_b[39])); + assign ca_or_lv1[20] = (~(d_b[40] & d_b[41])); + assign ca_or_lv1[21] = (~(d_b[42] & d_b[43])); + assign ca_or_lv1[22] = (~(d_b[44] & d_b[45])); + assign ca_or_lv1[23] = (~(d_b[46] & d_b[47])); + assign ca_or_lv1[24] = (~(d_b[48] & d_b[49])); + assign ca_or_lv1[25] = (~(d_b[50] & d_b[51])); + assign ca_or_lv1[26] = (~(d_b[52] & d_b[53])); + assign ca_or_lv1[27] = (~(d_b[54] & d_b[55])); + assign ca_or_lv1[28] = (~(d_b[56] & d_b[57])); + assign ca_or_lv1[29] = (~(d_b[58] & d_b[59])); + assign ca_or_lv1[30] = (~(d_b[60] & d_b[61])); + assign ca_or_lv1[31] = (~(d_b[62] & d_b[63])); + + assign ca_or_lv2_b[0] = (~(ca_or_lv1[0] | ca_or_lv1[1])); + assign ca_or_lv2_b[1] = (~(ca_or_lv1[2] | ca_or_lv1[3])); + assign ca_or_lv2_b[2] = (~(ca_or_lv1[4] | ca_or_lv1[5])); + assign ca_or_lv2_b[3] = (~(ca_or_lv1[6] | ca_or_lv1[7])); + assign ca_or_lv2_b[4] = (~(ca_or_lv1[8] | ca_or_lv1[9])); + assign ca_or_lv2_b[5] = (~(ca_or_lv1[10] | ca_or_lv1[11])); + assign ca_or_lv2_b[6] = (~(ca_or_lv1[12] | ca_or_lv1[13])); + assign ca_or_lv2_b[7] = (~(ca_or_lv1[14] | ca_or_lv1[15])); + assign ca_or_lv2_b[8] = (~(ca_or_lv1[16] | ca_or_lv1[17])); + assign ca_or_lv2_b[9] = (~(ca_or_lv1[18] | ca_or_lv1[19])); + assign ca_or_lv2_b[10] = (~(ca_or_lv1[20] | ca_or_lv1[21])); + assign ca_or_lv2_b[11] = (~(ca_or_lv1[22] | ca_or_lv1[23])); + assign ca_or_lv2_b[12] = (~(ca_or_lv1[24] | ca_or_lv1[25])); + assign ca_or_lv2_b[13] = (~(ca_or_lv1[26] | ca_or_lv1[27])); + assign ca_or_lv2_b[14] = (~(ca_or_lv1[28] | ca_or_lv1[29])); + assign ca_or_lv2_b[15] = (~(ca_or_lv1[30] | ca_or_lv1[31])); + + assign ca_or_lv3[0] = (~(ca_or_lv2_b[0] & ca_or_lv2_b[1])); + assign ca_or_lv3[1] = (~(ca_or_lv2_b[2] & ca_or_lv2_b[3])); + assign ca_or_lv3[2] = (~(ca_or_lv2_b[4] & ca_or_lv2_b[5])); + assign ca_or_lv3[3] = (~(ca_or_lv2_b[6] & ca_or_lv2_b[7])); + assign ca_or_lv3[4] = (~(ca_or_lv2_b[8] & ca_or_lv2_b[9])); + assign ca_or_lv3[5] = (~(ca_or_lv2_b[10] & ca_or_lv2_b[11])); + assign ca_or_lv3[6] = (~(ca_or_lv2_b[12] & ca_or_lv2_b[13])); + assign ca_or_lv3[7] = (~(ca_or_lv2_b[14] & ca_or_lv2_b[15])); + + assign ca_or_lv4_b[0] = (~(ca_or_lv3[0] | ca_or_lv3[1])); + assign ca_or_lv4_b[1] = (~(ca_or_lv3[2] | ca_or_lv3[3])); + assign ca_or_lv4_b[2] = (~(ca_or_lv3[4] | ca_or_lv3[5])); + assign ca_or_lv4_b[3] = (~(ca_or_lv3[6] | ca_or_lv3[7])); + + assign ca_or_lv5[0] = (~(ca_or_lv4_b[0] & ca_or_lv4_b[1])); + assign ca_or_lv5[1] = (~(ca_or_lv4_b[2] & ca_or_lv4_b[3])); + + assign or_hi = ca_or_lv5[0]; // rename + assign or_lo = ca_or_lv5[1]; // rename + +// ///////// in placement order ////////////////////////////////////////////// +// u_ca_or_00: ca_or_lv1 ( 0) <= not( d_b ( 0) and d_b ( 1) ); +// u_ca_or_01: ca_or_lv2_b( 0) <= not( ca_or_lv1 ( 0) or ca_or_lv1 ( 1) ); +// u_ca_or_02: ca_or_lv1 ( 1) <= not( d_b ( 2) and d_b ( 3) ); +// u_ca_or_03: ca_or_lv3 ( 0) <= not( ca_or_lv2_b( 0) and ca_or_lv2_b( 1) ); +// u_ca_or_04: ca_or_lv1 ( 2 <= not( d_b ( 4) and d_b ( 5) ); +// u_ca_or_05: ca_or_lv2_b( 1) <= not( ca_or_lv1 ( 2) or ca_or_lv1 ( 3) ); +// u_ca_or_06: ca_or_lv1 ( 3) <= not( d_b ( 6) and d_b ( 7) ); +// u_ca_or_07: ca_or_lv4_b( 0) <= not( ca_or_lv3 ( 0) or ca_or_lv3 ( 1) ); +// u_ca_or_08: ca_or_lv1 ( 4) <= not( d_b ( 8) and d_b ( 9) ); +// u_ca_or_09: ca_or_lv2_b( 2) <= not( ca_or_lv1 ( 4) or ca_or_lv1 ( 5) ); +// u_ca_or_10: ca_or_lv1 ( 5) <= not( d_b (10) and d_b (11) ); +// u_ca_or_11: ca_or_lv3 ( 1) <= not( ca_or_lv2_b( 2) and ca_or_lv2_b( 3) ); +// u_ca_or_12: ca_or_lv1 ( 6) <= not( d_b (12) and d_b (13) ); +// u_ca_or_13: ca_or_lv2_b( 3) <= not( ca_or_lv1 ( 6) or ca_or_lv1 ( 7) ); +// u_ca_or_14: ca_or_lv1 ( 7) <= not( d_b (14) and d_b (15) ); +// u_ca_or_15: ca_or_lv5 ( 0) <= not( ca_or_lv4_b( 0) and ca_or_lv4_b( 1) ); +// u_ca_or_16: ca_or_lv1 ( 8) <= not( d_b (16) and d_b (17) ); +// u_ca_or_17: ca_or_lv2_b( 4) <= not( ca_or_lv1 ( 8) or ca_or_lv1 ( 9) ); +// u_ca_or_18: ca_or_lv1 ( 9) <= not( d_b (18) and d_b (19) ); +// u_ca_or_19: ca_or_lv3 ( 2) <= not( ca_or_lv2_b( 4) and ca_or_lv2_b( 5) ); +// u_ca_or_20: ca_or_lv1 (10) <= not( d_b (20) and d_b (21) ); +// u_ca_or_21: ca_or_lv2_b( 5) <= not( ca_or_lv1 (10) or ca_or_lv1 (11) ); +// u_ca_or_22: ca_or_lv1 (11) <= not( d_b (22) and d_b (23) ); +// u_ca_or_23: ca_or_lv4_b( 1) <= not( ca_or_lv3 ( 2) or ca_or_lv3 ( 3) ); +// u_ca_or_24: ca_or_lv1 (12) <= not( d_b (24) and d_b (25) ); +// u_ca_or_25: ca_or_lv2_b( 6) <= not( ca_or_lv1 (12) or ca_or_lv1 (13) ); +// u_ca_or_26: ca_or_lv1 (13) <= not( d_b (26) and d_b (27) ); +// u_ca_or_27: ca_or_lv3 ( 3) <= not( ca_or_lv2_b( 6) and ca_or_lv2_b( 7) ); +// u_ca_or_28: ca_or_lv1 (14) <= not( d_b (28) and d_b (29) ); +// u_ca_or_29: ca_or_lv2_b( 7) <= not( ca_or_lv1 (14) or ca_or_lv1 (15) ); +// u_ca_or_30: ca_or_lv1 (15) <= not( d_b (30) and d_b (31) ); +// u_ca_or_32: ca_or_lv1 (16) <= not( d_b (32) and d_b (33) ); +// u_ca_or_33: ca_or_lv2_b( 8) <= not( ca_or_lv1 (16) or ca_or_lv1 (17) ); +// u_ca_or_34: ca_or_lv1 (17) <= not( d_b (34) and d_b (35) ); +// u_ca_or_35: ca_or_lv3 ( 4) <= not( ca_or_lv2_b( 8) and ca_or_lv2_b( 9) ); +// u_ca_or_36: ca_or_lv1 (18) <= not( d_b (36) and d_b (37) ); +// u_ca_or_37: ca_or_lv2_b( 9) <= not( ca_or_lv1 (18) or ca_or_lv1 (19) ); +// u_ca_or_38: ca_or_lv1 (19) <= not( d_b (38) and d_b (39) ); +// u_ca_or_39: ca_or_lv4_b( 2) <= not( ca_or_lv3 ( 4) or ca_or_lv3 ( 5) ); +// u_ca_or_40: ca_or_lv1 (20) <= not( d_b (40) and d_b (41) ); +// u_ca_or_41: ca_or_lv2_b(10) <= not( ca_or_lv1 (20) or ca_or_lv1 (21) ); +// u_ca_or_42: ca_or_lv1 (21) <= not( d_b (42) and d_b (43) ); +// u_ca_or_43: ca_or_lv3 ( 5) <= not( ca_or_lv2_b(10) and ca_or_lv2_b(11) ); +// u_ca_or_44: ca_or_lv1 (22) <= not( d_b (44) and d_b (45) ); +// u_ca_or_45: ca_or_lv2_b(11) <= not( ca_or_lv1 (22) or ca_or_lv1 (23) ); +// u_ca_or_46: ca_or_lv1 (23) <= not( d_b (46) and d_b (47) ); +// u_ca_or_47: ca_or_lv5 ( 1) <= not( ca_or_lv4_b( 2) and ca_or_lv4_b( 3) ); +// u_ca_or_48: ca_or_lv1 (24) <= not( d_b (48) and d_b (49) ); +// u_ca_or_49: ca_or_lv2_b(12) <= not( ca_or_lv1 (24) or ca_or_lv1 (25) ); +// u_ca_or_50: ca_or_lv1 (25) <= not( d_b (50) and d_b (51) ); +// u_ca_or_51: ca_or_lv3 ( 6) <= not( ca_or_lv2_b(12) and ca_or_lv2_b(13) ); +// u_ca_or_52: ca_or_lv1 (26) <= not( d_b (52) and d_b (53) ); +// u_ca_or_53: ca_or_lv2_b(13) <= not( ca_or_lv1 (26) or ca_or_lv1 (27) ); +// u_ca_or_54: ca_or_lv1 (27) <= not( d_b (54) and d_b (55) ); +// u_ca_or_55: ca_or_lv4_b( 3) <= not( ca_or_lv3 ( 6) or ca_or_lv3 ( 7) ); +// u_ca_or_56: ca_or_lv1 (28) <= not( d_b (56) and d_b (57) ); +// u_ca_or_57: ca_or_lv2_b(14) <= not( ca_or_lv1 (28) or ca_or_lv1 (29) ); +// u_ca_or_58: ca_or_lv1 (29) <= not( d_b (58) and d_b (59) ); +// u_ca_or_59: ca_or_lv3 ( 7) <= not( ca_or_lv2_b(14) and ca_or_lv2_b(15) ); +// u_ca_or_60: ca_or_lv1 (30) <= not( d_b (60) and d_b (61) ); +// u_ca_or_61: ca_or_lv2_b(15) <= not( ca_or_lv1 (30) or ca_or_lv1 (31) ); +// u_ca_or_62: ca_or_lv1 (31) <= not( d_b (62) and d_b (63) ); +// +// -- -- + +endmodule diff --git a/dev/verilog/trilib/tri_st_popcnt.v b/dev/verilog/trilib/tri_st_popcnt.v new file mode 100755 index 0000000..a6f3cb3 --- /dev/null +++ b/dev/verilog/trilib/tri_st_popcnt.v @@ -0,0 +1,451 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//***************************************************************************** +// Description: XU Population Count +// +//***************************************************************************** + +`include "tri_a2o.vh" + +module tri_st_popcnt( + nclk, + vdd, + gnd, + delay_lclkr_dc, + mpw1_dc_b, + mpw2_dc_b, + d_mode_dc, + func_sl_force, + func_sl_thold_0_b, + sg_0, + scan_in, + scan_out, + ex1_act, + ex1_instr, + ex2_popcnt_rs1, + ex4_popcnt_rt +); + //------------------------------------------------------------------- + // Clocks & Power + //------------------------------------------------------------------- + input [0:`NCLK_WIDTH-1] nclk; + inout vdd; + inout gnd; + + //------------------------------------------------------------------- + // Pervasive + //------------------------------------------------------------------- + input delay_lclkr_dc; + input mpw1_dc_b; + input mpw2_dc_b; + input d_mode_dc; + input func_sl_force; + input func_sl_thold_0_b; + input sg_0; + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) // scan_in + input scan_in; + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) // scan_out + output scan_out; + + input ex1_act; + input [22:23] ex1_instr; + input [0:63] ex2_popcnt_rs1; + output [0:63] ex4_popcnt_rt; + + // Latches + wire [2:3] exx_act_q; // input=>exx_act_d ,act=>1 + wire [2:3] exx_act_d; + wire [22:23] ex2_instr_q; // input=>ex1_instr ,act=>exx_act(1) + wire [0:2] ex3_popcnt_sel_q; // input=>ex2_popcnt_sel ,act=>exx_act(2) + wire [0:2] ex2_popcnt_sel; + wire [0:7] ex3_b3_q; // input=>ex2_b3 ,act=>exx_act(2) + wire [0:7] ex2_b3; + wire [0:7] ex3_b2_q; // input=>ex2_b2 ,act=>exx_act(2) + wire [0:7] ex2_b2; + wire [0:7] ex3_b1_q; // input=>ex2_b1 ,act=>exx_act(2) + wire [0:7] ex2_b1; + wire [0:7] ex3_b0_q; // input=>ex2_b0 ,act=>exx_act(2) + wire [0:7] ex2_b0; + wire [0:7] ex4_b3_q; // input=>ex3_b3_q ,act=>exx_act(3) + wire [0:7] ex4_b2_q; // input=>ex3_b2_q ,act=>exx_act(3) + wire [0:7] ex4_b1_q; // input=>ex3_b1_q ,act=>exx_act(3) + wire [0:7] ex4_b0_q; // input=>ex3_b0_q ,act=>exx_act(3) + wire [0:5] ex4_word0_q; // input=>ex3_word0 ,act=>exx_act(3) + wire [0:5] ex3_word0; + wire [0:5] ex4_word1_q; // input=>ex3_word1 ,act=>exx_act(3) + wire [0:5] ex3_word1; + wire [0:2] ex4_popcnt_sel_q; // input=>ex3_popcnt_sel_q ,act=>exx_act(3) + // Scanchain + parameter exx_act_offset = 0; + parameter ex2_instr_offset = exx_act_offset + 2; + parameter ex3_popcnt_sel_offset = ex2_instr_offset + 2; + parameter ex3_b3_offset = ex3_popcnt_sel_offset + 3; + parameter ex3_b2_offset = ex3_b3_offset + 8; + parameter ex3_b1_offset = ex3_b2_offset + 8; + parameter ex3_b0_offset = ex3_b1_offset + 8; + parameter ex4_b3_offset = ex3_b0_offset + 8; + parameter ex4_b2_offset = ex4_b3_offset + 8; + parameter ex4_b1_offset = ex4_b2_offset + 8; + parameter ex4_b0_offset = ex4_b1_offset + 8; + parameter ex4_word0_offset = ex4_b0_offset + 8; + parameter ex4_word1_offset = ex4_word0_offset + 6; + parameter ex4_popcnt_sel_offset = ex4_word1_offset + 6; + parameter scan_right = ex4_popcnt_sel_offset + 3; + wire [0:scan_right-1] siv; + wire [0:scan_right-1] sov; + // Signals + wire [0:63] ex4_popcnt_byte; + wire [0:63] ex4_popcnt_word; + wire [0:63] ex4_popcnt_dword; + wire [1:3] exx_act; + + assign exx_act_d[2:3] = exx_act[1:2]; + assign exx_act[1:3] = {ex1_act, exx_act_q[2:3]}; + + generate + genvar i; + for (i = 0; i <= 7; i = i + 1) + begin : byte_gen + + tri_st_popcnt_byte bytes( + .b0(ex2_popcnt_rs1[8*i:8*i+7]), + .y({ex2_b3[i],ex2_b2[i],ex2_b1[i],ex2_b0[i]}), + .vdd(vdd), + .gnd(gnd) + ); + + assign ex4_popcnt_byte[8*i+0:8*i+3] = 0; + assign ex4_popcnt_byte[8*i+4] = ex4_b3_q[i]; + assign ex4_popcnt_byte[8*i+5] = ex4_b2_q[i]; + assign ex4_popcnt_byte[8*i+6] = ex4_b1_q[i]; + assign ex4_popcnt_byte[8*i+7] = ex4_b0_q[i]; + end + endgenerate + + + tri_st_popcnt_word word0( + .b0(ex3_b0_q[0:3]), + .b1(ex3_b1_q[0:3]), + .b2(ex3_b2_q[0:3]), + .b3(ex3_b3_q[0:3]), + .y(ex3_word0), + .vdd(vdd), + .gnd(gnd) + ); + + + tri_st_popcnt_word word1( + .b0(ex3_b0_q[4:7]), + .b1(ex3_b1_q[4:7]), + .b2(ex3_b2_q[4:7]), + .b3(ex3_b3_q[4:7]), + .y(ex3_word1), + .vdd(vdd), + .gnd(gnd) + ); + + assign ex4_popcnt_word[00:25] = {26{1'b0}}; + assign ex4_popcnt_word[26:31] = ex4_word0_q; + assign ex4_popcnt_word[32:57] = {26{1'b0}}; + assign ex4_popcnt_word[58:63] = ex4_word1_q; + + assign ex4_popcnt_dword[00:56] = {57{1'b0}}; + assign ex4_popcnt_dword[57:63] = {1'b0, ex4_word0_q} + {1'b0, ex4_word1_q}; + + assign ex2_popcnt_sel[0] = (ex2_instr_q == 2'b00) ? 1'b1 : 1'b0; + assign ex2_popcnt_sel[1] = (ex2_instr_q == 2'b10) ? 1'b1 : 1'b0; + assign ex2_popcnt_sel[2] = (ex2_instr_q == 2'b11) ? 1'b1 : 1'b0; + + assign ex4_popcnt_rt = (ex4_popcnt_byte & {64{ex4_popcnt_sel_q[0]}}) | + (ex4_popcnt_word & {64{ex4_popcnt_sel_q[1]}}) | + (ex4_popcnt_dword & {64{ex4_popcnt_sel_q[2]}}); + + //------------------------------------------------------------------- + // Latch instances + //------------------------------------------------------------------- + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) exx_act_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[exx_act_offset:exx_act_offset + 2 - 1]), + .scout(sov[exx_act_offset:exx_act_offset + 2 - 1]), + .din(exx_act_d), + .dout(exx_act_q) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex2_instr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_instr_offset:ex2_instr_offset + 2 - 1]), + .scout(sov[ex2_instr_offset:ex2_instr_offset + 2 - 1]), + .din(ex1_instr), + .dout(ex2_instr_q) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex3_popcnt_sel_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_popcnt_sel_offset:ex3_popcnt_sel_offset + 3 - 1]), + .scout(sov[ex3_popcnt_sel_offset:ex3_popcnt_sel_offset + 3 - 1]), + .din(ex2_popcnt_sel), + .dout(ex3_popcnt_sel_q) + ); + + tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex3_b3_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_b3_offset:ex3_b3_offset + 8 - 1]), + .scout(sov[ex3_b3_offset:ex3_b3_offset + 8 - 1]), + .din(ex2_b3), + .dout(ex3_b3_q) + ); + + tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex3_b2_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_b2_offset:ex3_b2_offset + 8 - 1]), + .scout(sov[ex3_b2_offset:ex3_b2_offset + 8 - 1]), + .din(ex2_b2), + .dout(ex3_b2_q) + ); + + tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex3_b1_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_b1_offset:ex3_b1_offset + 8 - 1]), + .scout(sov[ex3_b1_offset:ex3_b1_offset + 8 - 1]), + .din(ex2_b1), + .dout(ex3_b1_q) + ); + + tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex3_b0_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_b0_offset:ex3_b0_offset + 8 - 1]), + .scout(sov[ex3_b0_offset:ex3_b0_offset + 8 - 1]), + .din(ex2_b0), + .dout(ex3_b0_q) + ); + + tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex4_b3_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(exx_act[3]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_b3_offset:ex4_b3_offset + 8 - 1]), + .scout(sov[ex4_b3_offset:ex4_b3_offset + 8 - 1]), + .din(ex3_b3_q), + .dout(ex4_b3_q) + ); + + tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex4_b2_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(exx_act[3]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_b2_offset:ex4_b2_offset + 8 - 1]), + .scout(sov[ex4_b2_offset:ex4_b2_offset + 8 - 1]), + .din(ex3_b2_q), + .dout(ex4_b2_q) + ); + + tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex4_b1_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(exx_act[3]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_b1_offset:ex4_b1_offset + 8 - 1]), + .scout(sov[ex4_b1_offset:ex4_b1_offset + 8 - 1]), + .din(ex3_b1_q), + .dout(ex4_b1_q) + ); + + tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex4_b0_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(exx_act[3]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_b0_offset:ex4_b0_offset + 8 - 1]), + .scout(sov[ex4_b0_offset:ex4_b0_offset + 8 - 1]), + .din(ex3_b0_q), + .dout(ex4_b0_q) + ); + + tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) ex4_word0_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(exx_act[3]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_word0_offset:ex4_word0_offset + 6 - 1]), + .scout(sov[ex4_word0_offset:ex4_word0_offset + 6 - 1]), + .din(ex3_word0), + .dout(ex4_word0_q) + ); + + tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) ex4_word1_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(exx_act[3]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_word1_offset:ex4_word1_offset + 6 - 1]), + .scout(sov[ex4_word1_offset:ex4_word1_offset + 6 - 1]), + .din(ex3_word1), + .dout(ex4_word1_q) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex4_popcnt_sel_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(exx_act[3]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_popcnt_sel_offset:ex4_popcnt_sel_offset + 3 - 1]), + .scout(sov[ex4_popcnt_sel_offset:ex4_popcnt_sel_offset + 3 - 1]), + .din(ex3_popcnt_sel_q), + .dout(ex4_popcnt_sel_q) + ); + + assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in}; + assign scan_out = sov[0]; + + +endmodule diff --git a/dev/verilog/trilib/tri_st_popcnt_byte.v b/dev/verilog/trilib/tri_st_popcnt_byte.v new file mode 100755 index 0000000..189c466 --- /dev/null +++ b/dev/verilog/trilib/tri_st_popcnt_byte.v @@ -0,0 +1,124 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//***************************************************************************** +// Description: XU Population Count - Byte Phase +// +//***************************************************************************** + +module tri_st_popcnt_byte( + b0, + y, + vdd, + gnd +); + input [0:7] b0; + output [0:3] y; + inout vdd; + inout gnd; + + wire [0:2] s0; + wire [0:3] c1; + wire [0:0] s1; + wire [0:1] c2; + + // Level 0 + + tri_csa32 csa_l0_0( + .vd(vdd), + .gd(gnd), + .a(b0[0]), + .b(b0[1]), + .c(b0[2]), + .sum(s0[0]), + .car(c1[0]) + ); + + + tri_csa32 csa_l0_1( + .vd(vdd), + .gd(gnd), + .a(b0[3]), + .b(b0[4]), + .c(b0[5]), + .sum(s0[1]), + .car(c1[1]) + ); + + + tri_csa22 csa_l0_2( + .a(b0[6]), + .b(b0[7]), + .sum(s0[2]), + .car(c1[2]) + ); + + + tri_csa32 csa_l0_3( + .vd(vdd), + .gd(gnd), + .a(s0[0]), + .b(s0[1]), + .c(s0[2]), + .sum(y[3]), + .car(c1[3]) + ); + + // Level 1 + + tri_csa32 csa_l1_0( + .vd(vdd), + .gd(gnd), + .a(c1[0]), + .b(c1[1]), + .c(c1[2]), + .sum(s1[0]), + .car(c2[0]) + ); + + + tri_csa22 csa_l1_1( + .a(c1[3]), + .b(s1[0]), + .sum(y[2]), + .car(c2[1]) + ); + + // Level 2/3 + + tri_csa22 csa_l2_0( + .a(c2[0]), + .b(c2[1]), + .sum(y[1]), + .car(y[0]) + ); + + +endmodule diff --git a/dev/verilog/trilib/tri_st_popcnt_word.v b/dev/verilog/trilib/tri_st_popcnt_word.v new file mode 100755 index 0000000..f0a9c7d --- /dev/null +++ b/dev/verilog/trilib/tri_st_popcnt_word.v @@ -0,0 +1,193 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//***************************************************************************** +// Description: XU Population Count - Word Phase +// +//***************************************************************************** + +module tri_st_popcnt_word( + b0, + b1, + b2, + b3, + y, + vdd, + gnd +); + input [0:3] b0; + input [0:3] b1; + input [0:3] b2; + input [0:3] b3; + output [0:5] y; + inout vdd; + inout gnd; + + wire [0:0] s0; + wire [0:1] c1; + wire [0:1] s1; + wire [0:2] c2; + wire [0:1] s2; + wire [0:2] c3; + wire [0:1] s3; + wire [0:2] c4; + + // Level 0 + + tri_csa32 csa_l0_0( + .vd(vdd), + .gd(gnd), + .a(b0[0]), + .b(b0[1]), + .c(b0[2]), + .sum(s0[0]), + .car(c1[0]) + ); + + + tri_csa22 csa_l0_1( + .a(b0[3]), + .b(s0[0]), + .sum(y[5]), + .car(c1[1]) + ); + + // Level 1 + + tri_csa32 csa_l1_0( + .vd(vdd), + .gd(gnd), + .a(b1[0]), + .b(b1[1]), + .c(b1[2]), + .sum(s1[0]), + .car(c2[0]) + ); + + + tri_csa32 csa_l1_1( + .vd(vdd), + .gd(gnd), + .a(b1[3]), + .b(c1[0]), + .c(c1[1]), + .sum(s1[1]), + .car(c2[1]) + ); + + + tri_csa22 csa_l1_2( + .a(s1[0]), + .b(s1[1]), + .sum(y[4]), + .car(c2[2]) + ); + + // Level 2 + + tri_csa32 csa_l2_0( + .vd(vdd), + .gd(gnd), + .a(b2[0]), + .b(b2[1]), + .c(b2[2]), + .sum(s2[0]), + .car(c3[0]) + ); + + + tri_csa32 csa_l2_1( + .vd(vdd), + .gd(gnd), + .a(b2[3]), + .b(c2[0]), + .c(c2[1]), + .sum(s2[1]), + .car(c3[1]) + ); + + + tri_csa32 csa_l2_2( + .vd(vdd), + .gd(gnd), + .a(c2[2]), + .b(s2[0]), + .c(s2[1]), + .sum(y[3]), + .car(c3[2]) + ); + + // Level 3 + + tri_csa32 csa_l3_0( + .vd(vdd), + .gd(gnd), + .a(b3[0]), + .b(b3[1]), + .c(b3[2]), + .sum(s3[0]), + .car(c4[0]) + ); + + + tri_csa32 csa_l3_1( + .vd(vdd), + .gd(gnd), + .a(b3[3]), + .b(c3[0]), + .c(c3[1]), + .sum(s3[1]), + .car(c4[1]) + ); + + + tri_csa32 csa_l3_2( + .vd(vdd), + .gd(gnd), + .a(c3[2]), + .b(s3[0]), + .c(s3[1]), + .sum(y[2]), + .car(c4[2]) + ); + + // Level 4 + + tri_csa32 csa_l4_0( + .vd(vdd), + .gd(gnd), + .a(c4[0]), + .b(c4[1]), + .c(c4[2]), + .sum(y[1]), + .car(y[0]) + ); + +endmodule diff --git a/dev/verilog/trilib/tri_st_rot.v b/dev/verilog/trilib/tri_st_rot.v new file mode 100755 index 0000000..3bbd2eb --- /dev/null +++ b/dev/verilog/trilib/tri_st_rot.v @@ -0,0 +1,1127 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: XU Rotate/Logical Unit +// +//***************************************************************************** + +`include "tri_a2o.vh" + +module tri_st_rot( + nclk, + vdd, + gnd, + d_mode_dc, + delay_lclkr_dc, + mpw1_dc_b, + mpw2_dc_b, + func_sl_force, + func_sl_thold_0_b, + sg_0, + scan_in, + scan_out, + ex1_act, + ex1_instr, + ex2_isel_fcn, + ex2_sel_rot_log, + ex2_rs0_b, + ex2_rs1_b, + ex2_alu_rt, + ex3_rt, + ex2_log_rt, + ex3_xer_ca, + ex3_cr_eq +); + input [0:`NCLK_WIDTH-1] nclk; + inout vdd; + inout gnd; + input d_mode_dc; + input delay_lclkr_dc; + input mpw1_dc_b; + input mpw2_dc_b; + input func_sl_force; + input func_sl_thold_0_b; + input sg_0; + input scan_in; + output scan_out; + + input ex1_act; + input [0:31] ex1_instr; + + input [0:3] ex2_isel_fcn; + output ex2_sel_rot_log; + + // Source Inputs + input [0:63] ex2_rs0_b; //rb/ra + input [0:63] ex2_rs1_b; //rs + + // Other ALU Inputs for muxing + input [0:63] ex2_alu_rt; + + // EX2 Bypass Tap + output [0:63] ex3_rt; + // EX1 Bypass Tap (logicals only) + output [0:63] ex2_log_rt; + + output ex3_xer_ca; + + output [0:1] ex3_cr_eq; + + //!! bugspray include: tri_st_rot + + + // Latches + wire ex2_act_q; // input=>ex1_act ,act=>1 + wire [0:5] ex2_mb_ins_q; // input=>ex1_mb_ins ,act=>ex1_act + wire [0:5] ex2_me_ins_b_q; // input=>ex1_me_ins_b ,act=>ex1_act + wire [0:5] ex2_sh_amt_q; // input=>ex1_sh_amt ,act=>ex1_act + wire [0:2] ex2_sh_right_q; // input=>ex1_sh_rgt_vec ,act=>ex1_act + wire [0:2] ex1_sh_right_vec; + wire [0:1] ex2_sh_word_q; // input=>ex1_sh_word_vec ,act=>ex1_act + wire [0:1] ex1_sh_word_vec; + wire ex2_zm_ins_q; // input=>ex1_zm_ins ,act=>ex1_act + wire ex2_chk_shov_wd_q; // input=>ex1_chk_shov_wd ,act=>ex1_act + wire ex2_chk_shov_dw_q; // input=>ex1_chk_shov_dw ,act=>ex1_act + wire ex2_use_sh_amt_hi_q; // act=>ex1_act + wire ex1_use_sh_amt_hi; + wire ex2_use_sh_amt_lo_q; // act=>ex1_act + wire ex1_use_sh_amt_lo; + wire ex2_use_rb_amt_hi_q; // input=>ex1_use_rb_amt_hi ,act=>ex1_act + wire ex2_use_rb_amt_lo_q; // input=>ex1_use_rb_amt_lo ,act=>ex1_act + wire ex2_use_me_rb_hi_q; // input=>ex1_use_me_rb_hi ,act=>ex1_act + wire ex2_use_me_rb_lo_q; // input=>ex1_use_me_rb_lo ,act=>ex1_act + wire ex2_use_mb_rb_hi_q; // input=>ex1_use_mb_rb_hi ,act=>ex1_act + wire ex2_use_mb_rb_lo_q; // input=>ex1_use_mb_rb_lo ,act=>ex1_act + wire ex2_use_me_ins_hi_q; // input=>ex1_use_me_ins_hi ,act=>ex1_act + wire ex2_use_me_ins_lo_q; // input=>ex1_use_me_ins_lo ,act=>ex1_act + wire ex2_use_mb_ins_hi_q; // input=>ex1_use_mb_ins_hi ,act=>ex1_act + wire ex2_use_mb_ins_lo_q; // input=>ex1_use_mb_ins_lo ,act=>ex1_act + wire ex2_ins_prtyw_q; // input=>ex1_ins_prtyw ,act=>ex1_act + wire ex2_ins_prtyd_q; // input=>ex1_ins_prtyd ,act=>ex1_act + wire ex2_mb_gt_me_q; // input=>ex1_mb_gt_me ,act=>ex1_act + wire ex2_cmp_byte_q; // input=>ex1_cmp_byt ,act=>ex1_act + wire ex2_sgnxtd_byte_q; // input=>ex1_sgnxtd_byte ,act=>ex1_act + wire ex2_sgnxtd_half_q; // input=>ex1_sgnxtd_half ,act=>ex1_act + wire ex2_sgnxtd_wd_q; // input=>ex1_sgnxtd_wd ,act=>ex1_act + wire ex2_sra_wd_q; // input=>ex1_sra_wd ,act=>ex1_act + wire ex2_sra_dw_q; // input=>ex1_sra_dw ,act=>ex1_act + wire [0:3] ex2_log_fcn_q; // input=>ex2_log_fcn_d ,act=>ex1_act + wire [0:3] ex2_log_fcn_d; + wire ex2_sel_rot_log_q; // input=>ex1_sel_rot_log ,act=>ex1_act + wire ex3_sh_word_q; // input=>ex2_sh_word_q(1) ,act=>ex2_act_q + wire [0:63] ex3_rotate_b_q; // act=>ex2_act_q + wire [0:63] ex2_result; + wire [0:63] ex3_result_b_q; // act=>ex2_act_q + wire [0:63] ex2_rotate; + wire [0:63] ex3_mask_b_q; // act=>ex2_act_q + wire [0:63] ex2_mask; + wire [0:0] ex3_sra_se_q; // act=>ex2_act_q + wire [0:0] ex2_sra_se; + wire [0:0] dummy_q; + // Scanchains + localparam ex2_act_offset = 0; + localparam ex2_mb_ins_offset = ex2_act_offset + 1; + localparam ex2_me_ins_b_offset = ex2_mb_ins_offset + 6; + localparam ex2_sh_amt_offset = ex2_me_ins_b_offset + 6; + localparam ex2_sh_right_offset = ex2_sh_amt_offset + 6; + localparam ex2_sh_word_offset = ex2_sh_right_offset + 3; + localparam ex2_zm_ins_offset = ex2_sh_word_offset + 2; + localparam ex2_chk_shov_wd_offset = ex2_zm_ins_offset + 1; + localparam ex2_chk_shov_dw_offset = ex2_chk_shov_wd_offset + 1; + localparam ex2_use_sh_amt_hi_offset = ex2_chk_shov_dw_offset + 1; + localparam ex2_use_sh_amt_lo_offset = ex2_use_sh_amt_hi_offset + 1; + localparam ex2_use_rb_amt_hi_offset = ex2_use_sh_amt_lo_offset + 1; + localparam ex2_use_rb_amt_lo_offset = ex2_use_rb_amt_hi_offset + 1; + localparam ex2_use_me_rb_hi_offset = ex2_use_rb_amt_lo_offset + 1; + localparam ex2_use_me_rb_lo_offset = ex2_use_me_rb_hi_offset + 1; + localparam ex2_use_mb_rb_hi_offset = ex2_use_me_rb_lo_offset + 1; + localparam ex2_use_mb_rb_lo_offset = ex2_use_mb_rb_hi_offset + 1; + localparam ex2_use_me_ins_hi_offset = ex2_use_mb_rb_lo_offset + 1; + localparam ex2_use_me_ins_lo_offset = ex2_use_me_ins_hi_offset + 1; + localparam ex2_use_mb_ins_hi_offset = ex2_use_me_ins_lo_offset + 1; + localparam ex2_use_mb_ins_lo_offset = ex2_use_mb_ins_hi_offset + 1; + localparam ex2_ins_prtyw_offset = ex2_use_mb_ins_lo_offset + 1; + localparam ex2_ins_prtyd_offset = ex2_ins_prtyw_offset + 1; + localparam ex2_mb_gt_me_offset = ex2_ins_prtyd_offset + 1; + localparam ex2_cmp_byte_offset = ex2_mb_gt_me_offset + 1; + localparam ex2_sgnxtd_byte_offset = ex2_cmp_byte_offset + 1; + localparam ex2_sgnxtd_half_offset = ex2_sgnxtd_byte_offset + 1; + localparam ex2_sgnxtd_wd_offset = ex2_sgnxtd_half_offset + 1; + localparam ex2_sra_wd_offset = ex2_sgnxtd_wd_offset + 1; + localparam ex2_sra_dw_offset = ex2_sra_wd_offset + 1; + localparam ex2_log_fcn_offset = ex2_sra_dw_offset + 1; + localparam ex2_sel_rot_log_offset = ex2_log_fcn_offset + 4; + localparam ex3_sh_word_offset = ex2_sel_rot_log_offset + 1; + localparam ex3_rotate_b_offset = ex3_sh_word_offset + 1; + localparam ex3_result_b_offset = ex3_rotate_b_offset + 64; + localparam ex3_mask_b_offset = ex3_result_b_offset + 64; + localparam ex3_sra_se_offset = ex3_mask_b_offset + 64; + localparam dummy_offset = ex3_sra_se_offset + 1; + localparam scan_right = dummy_offset + 1; + wire [0:scan_right-1] siv; + wire [0:scan_right-1] sov; + wire [0:`NCLK_WIDTH-1] rot_lclk_int; + wire rot_d1clk_int; + wire rot_d2clk_int; + wire ex2_zm; + wire [0:5] ex2_use_sh_amt; + wire [0:5] ex2_use_rb_amt; + wire [0:5] ex2_use_me_rb; + wire [0:5] ex2_use_mb_rb; + wire [0:5] ex2_use_me_ins; + wire [0:5] ex2_use_mb_ins; + wire [0:5] ex2_sh_amt0_b; + wire [0:5] ex2_sh_amt1_b; + wire [0:5] ex2_sh_amt; + wire [0:5] ex2_mb0_b; + wire [0:5] ex2_mb1_b; + wire [0:5] ex2_mb; + wire [0:5] ex2_me0; + wire [0:5] ex2_me1; + wire [0:5] ex2_me_b; + wire [0:63] ex2_mask_b; + wire [0:63] ex2_insert; + wire ex2_sel_add; + wire [0:63] ex2_msk_rot_b; + wire [0:63] ex2_msk_ins_b; + wire [0:63] ex2_msk_rot; + wire [0:63] ex2_msk_ins; + wire [0:63] ex2_result_0_b; + wire [0:63] ex2_result_1_b; + wire [0:63] ex2_result_2_b; + wire [0:63] ca_root_b; + wire ca_or_hi; + wire ca_or_lo; + wire ex2_act_unqiue; + wire [0:63] ex2_ins_rs0; + wire [0:63] ex2_ins_rs1; + wire [0:63] ex2_rot_rs0; + wire [57:63] ex2_rot_rs1; + wire [0:63] ex3_result_q; + wire [0:63] ex3_rotate_q; + wire ex1_zm_ins; + wire [0:5] ex1_mb_ins; + wire [0:5] ex1_me_ins_b; + wire [0:5] ex1_sh_amt; + wire ex1_sh_right; + wire ex1_sh_word; + wire ex1_use_rb_amt_hi; + wire ex1_use_rb_amt_lo; + wire ex1_use_me_rb_hi; + wire ex1_use_me_rb_lo; + wire ex1_use_mb_rb_hi; + wire ex1_use_mb_rb_lo; + wire ex1_use_me_ins_hi; + wire ex1_use_me_ins_lo; + wire ex1_use_mb_ins_hi; + wire ex1_use_mb_ins_lo; + wire ex1_ins_prtyw; + wire ex1_ins_prtyd; + wire ex1_chk_shov_wd; + wire ex1_chk_shov_dw; + wire ex1_mb_gt_me; + wire ex1_cmp_byt; + wire ex1_sgnxtd_byte; + wire ex1_sgnxtd_half; + wire ex1_sgnxtd_wd; + wire ex1_sra_wd; + wire ex1_sra_dw; + wire [0:3] ex1_log_fcn; + wire [0:3] ex2_log_fcn; + wire ex1_sel_rot_log; + + //------------------------------------------------------------------- + // Source Buffering + //------------------------------------------------------------------- + assign ex2_ins_rs0 = (~ex2_rs0_b); + assign ex2_ins_rs1 = (~ex2_rs1_b); + assign ex2_rot_rs0 = (~ex2_rs0_b); + assign ex2_rot_rs1 = (~ex2_rs1_b[57:63]); + + //------------------------------------------------------------------- + // Rotator / merge control generation + //------------------------------------------------------------------- + + tri_st_rot_dec dec( + .i(ex1_instr), + .ex1_zm_ins(ex1_zm_ins), + .ex1_mb_ins(ex1_mb_ins), + .ex1_me_ins_b(ex1_me_ins_b), + .ex1_sh_amt(ex1_sh_amt), + .ex1_sh_right(ex1_sh_right), + .ex1_sh_word(ex1_sh_word), + .ex1_use_rb_amt_hi(ex1_use_rb_amt_hi), + .ex1_use_rb_amt_lo(ex1_use_rb_amt_lo), + .ex1_use_me_rb_hi(ex1_use_me_rb_hi), + .ex1_use_me_rb_lo(ex1_use_me_rb_lo), + .ex1_use_mb_rb_hi(ex1_use_mb_rb_hi), + .ex1_use_mb_rb_lo(ex1_use_mb_rb_lo), + .ex1_use_me_ins_hi(ex1_use_me_ins_hi), + .ex1_use_me_ins_lo(ex1_use_me_ins_lo), + .ex1_use_mb_ins_hi(ex1_use_mb_ins_hi), + .ex1_use_mb_ins_lo(ex1_use_mb_ins_lo), + .ex1_ins_prtyw(ex1_ins_prtyw), + .ex1_ins_prtyd(ex1_ins_prtyd), + .ex1_chk_shov_wd(ex1_chk_shov_wd), + .ex1_chk_shov_dw(ex1_chk_shov_dw), + .ex1_mb_gt_me(ex1_mb_gt_me), + .ex1_cmp_byt(ex1_cmp_byt), + .ex1_sgnxtd_byte(ex1_sgnxtd_byte), + .ex1_sgnxtd_half(ex1_sgnxtd_half), + .ex1_sgnxtd_wd(ex1_sgnxtd_wd), + .ex1_sra_dw(ex1_sra_dw), + .ex1_sra_wd(ex1_sra_wd), + .ex1_log_fcn(ex1_log_fcn), + .ex1_sel_rot_log(ex1_sel_rot_log) + ); + + assign ex1_sh_right_vec = {3{ex1_sh_right}}; + assign ex1_sh_word_vec = {2{ex1_sh_word}}; + assign ex1_use_sh_amt_hi = (~ex1_use_rb_amt_hi); + assign ex1_use_sh_amt_lo = (~ex1_use_rb_amt_lo); + + assign ex2_use_sh_amt = {ex2_use_sh_amt_hi_q, {5{ex2_use_sh_amt_lo_q}}}; + assign ex2_use_rb_amt = {ex2_use_rb_amt_hi_q, {5{ex2_use_rb_amt_lo_q}}}; + assign ex2_use_me_rb = {ex2_use_me_rb_hi_q, {5{ex2_use_me_rb_lo_q}}}; + assign ex2_use_mb_rb = {ex2_use_mb_rb_hi_q, {5{ex2_use_mb_rb_lo_q}}}; + assign ex2_use_me_ins = {ex2_use_me_ins_hi_q, {5{ex2_use_me_ins_lo_q}}}; + assign ex2_use_mb_ins = {ex2_use_mb_ins_hi_q, {5{ex2_use_mb_ins_lo_q}}}; + + // instr does not use the rotator (dont care if adder used) + assign ex2_zm = (ex2_zm_ins_q) | (ex2_chk_shov_wd_q & ex2_rot_rs1[58]) | (ex2_chk_shov_dw_q & ex2_rot_rs1[57]); // word shift with amount from RB + // doubleword shift with amount from RB + + assign ex2_sh_amt0_b = ~(ex2_rot_rs1[58:63] & ex2_use_rb_amt); + assign ex2_sh_amt1_b = ~(ex2_sh_amt_q & ex2_use_sh_amt); + + assign ex2_sh_amt = ~(ex2_sh_amt0_b & ex2_sh_amt1_b); + + assign ex2_mb0_b = ~(ex2_rot_rs1[58:63] & ex2_use_mb_rb); + assign ex2_mb1_b = ~(ex2_mb_ins_q & ex2_use_mb_ins); + + assign ex2_mb = ~(ex2_mb0_b & ex2_mb1_b); + + assign ex2_me0 = ~(ex2_rot_rs1[58:63] & ex2_use_me_rb); + assign ex2_me1 = ~(ex2_me_ins_b_q & ex2_use_me_ins); + + assign ex2_me_b = ~(ex2_me0 & ex2_me1); + + //------------------------------------------------------------------- + // Mask unit + //------------------------------------------------------------------- + + tri_st_rot_mask msk( + .mb(ex2_mb), + .me_b(ex2_me_b), + .zm(ex2_zm), + .mb_gt_me(ex2_mb_gt_me_q), + .mask(ex2_mask) + ); + + //------------------------------------------------------------------- + // Insert data (includes logicals, sign extend, cmpb) + //------------------------------------------------------------------- + assign ex2_log_fcn_d = ex1_log_fcn; + assign ex2_log_fcn = ex2_log_fcn_q | ex2_isel_fcn; + + + tri_st_rot_ins ins( + .ins_log_fcn(ex2_log_fcn), + .ins_cmp_byt(ex2_cmp_byte_q), + .ins_sra_dw(ex2_sra_dw_q), + .ins_sra_wd(ex2_sra_wd_q), + .ins_xtd_byte(ex2_sgnxtd_byte_q), + .ins_xtd_half(ex2_sgnxtd_half_q), + .ins_xtd_wd(ex2_sgnxtd_wd_q), + .ins_prtyw(ex2_ins_prtyw_q), + .ins_prtyd(ex2_ins_prtyd_q), + .data0_i(ex2_ins_rs0), + .data1_i(ex2_ins_rs1), + .mrg_byp_log(ex2_log_rt), + .res_ins(ex2_insert) + ); + + //------------------------------------------------------------------- + // Rotate unit + //------------------------------------------------------------------- + + tri_st_rot_rol64 rol64( + .word(ex2_sh_word_q), + .right(ex2_sh_right_q), + .amt(ex2_sh_amt), + .data_i(ex2_rot_rs0), + .res_rot(ex2_rotate) + ); + + //------------------------------------------------------------------- + // Final muxing + //------------------------------------------------------------------- + assign ex2_mask_b = (~ex2_mask); + assign ex2_sel_add = (~ex2_sel_rot_log_q); + + assign ex2_msk_rot_b = ~(ex2_mask & {64{ex2_sel_rot_log_q}}); + assign ex2_msk_ins_b = ~(ex2_mask_b & {64{ex2_sel_rot_log_q}}); + + assign ex2_msk_rot = (~ex2_msk_rot_b); + assign ex2_msk_ins = (~ex2_msk_ins_b); + + assign ex2_result_0_b = ~(ex2_rotate & ex2_msk_rot); + assign ex2_result_1_b = ~(ex2_insert & ex2_msk_ins); + assign ex2_result_2_b = ~(ex2_alu_rt & {64{ex2_sel_add}}); + assign ex2_result = (~(ex2_result_0_b & ex2_result_1_b & ex2_result_2_b)); + + assign ex3_result_q = (~ex3_result_b_q); + + assign ex3_rt = ex3_result_q; + + //------------------------------------------------------------------- + // CA Generation + //------------------------------------------------------------------- + + tri_st_or3232_b or3232( + .d_b(ca_root_b), + .or_hi(ca_or_hi), + .or_lo(ca_or_lo) + ); + + assign ex3_rotate_q = (~ex3_rotate_b_q); + assign ca_root_b = (~(ex3_rotate_q & ex3_mask_b_q)); + + assign ex2_sra_se[0] = (ex2_ins_rs0[0] & (~ex2_sh_word_q[0])) | (ex2_ins_rs0[32] & ex2_sh_word_q[0]); + + assign ex3_xer_ca = (ca_or_lo & ex3_sra_se_q[0] & ex3_sh_word_q) | ((ca_or_lo | ca_or_hi) & ex3_sra_se_q[0] & (~ex3_sh_word_q)); + + assign ex3_cr_eq = {ca_or_hi, ca_or_lo}; + + assign ex2_sel_rot_log = ex2_sel_rot_log_q; + + // To generate a unique LCB for placement + assign ex2_act_unqiue = ex2_act_q | dummy_q[0]; + + //------------------------------------------------------------------- + // Latch Instances + //------------------------------------------------------------------- + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_act_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_act_offset]), + .scout(sov[ex2_act_offset]), + .din(ex1_act), + .dout(ex2_act_q) + ); + + tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) ex2_mb_ins_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_mb_ins_offset:ex2_mb_ins_offset + 6 - 1]), + .scout(sov[ex2_mb_ins_offset:ex2_mb_ins_offset + 6 - 1]), + .din(ex1_mb_ins), + .dout(ex2_mb_ins_q) + ); + + tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) ex2_me_ins_b_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_me_ins_b_offset:ex2_me_ins_b_offset + 6 - 1]), + .scout(sov[ex2_me_ins_b_offset:ex2_me_ins_b_offset + 6 - 1]), + .din(ex1_me_ins_b), + .dout(ex2_me_ins_b_q) + ); + + tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) ex2_sh_amt_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_sh_amt_offset:ex2_sh_amt_offset + 6 - 1]), + .scout(sov[ex2_sh_amt_offset:ex2_sh_amt_offset + 6 - 1]), + .din(ex1_sh_amt), + .dout(ex2_sh_amt_q) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex2_sh_right_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_sh_right_offset:ex2_sh_right_offset + 3 - 1]), + .scout(sov[ex2_sh_right_offset:ex2_sh_right_offset + 3 - 1]), + .din(ex1_sh_right_vec), + .dout(ex2_sh_right_q) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex2_sh_word_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_sh_word_offset:ex2_sh_word_offset + 2 - 1]), + .scout(sov[ex2_sh_word_offset:ex2_sh_word_offset + 2 - 1]), + .din(ex1_sh_word_vec), + .dout(ex2_sh_word_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_zm_ins_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_zm_ins_offset]), + .scout(sov[ex2_zm_ins_offset]), + .din(ex1_zm_ins), + .dout(ex2_zm_ins_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_chk_shov_wd_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_chk_shov_wd_offset]), + .scout(sov[ex2_chk_shov_wd_offset]), + .din(ex1_chk_shov_wd), + .dout(ex2_chk_shov_wd_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_chk_shov_dw_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_chk_shov_dw_offset]), + .scout(sov[ex2_chk_shov_dw_offset]), + .din(ex1_chk_shov_dw), + .dout(ex2_chk_shov_dw_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_use_sh_amt_hi_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_use_sh_amt_hi_offset]), + .scout(sov[ex2_use_sh_amt_hi_offset]), + .din(ex1_use_sh_amt_hi), + .dout(ex2_use_sh_amt_hi_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_use_sh_amt_lo_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_use_sh_amt_lo_offset]), + .scout(sov[ex2_use_sh_amt_lo_offset]), + .din(ex1_use_sh_amt_lo), + .dout(ex2_use_sh_amt_lo_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_use_rb_amt_hi_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_use_rb_amt_hi_offset]), + .scout(sov[ex2_use_rb_amt_hi_offset]), + .din(ex1_use_rb_amt_hi), + .dout(ex2_use_rb_amt_hi_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_use_rb_amt_lo_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_use_rb_amt_lo_offset]), + .scout(sov[ex2_use_rb_amt_lo_offset]), + .din(ex1_use_rb_amt_lo), + .dout(ex2_use_rb_amt_lo_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_use_me_rb_hi_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_use_me_rb_hi_offset]), + .scout(sov[ex2_use_me_rb_hi_offset]), + .din(ex1_use_me_rb_hi), + .dout(ex2_use_me_rb_hi_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_use_me_rb_lo_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_use_me_rb_lo_offset]), + .scout(sov[ex2_use_me_rb_lo_offset]), + .din(ex1_use_me_rb_lo), + .dout(ex2_use_me_rb_lo_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_use_mb_rb_hi_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_use_mb_rb_hi_offset]), + .scout(sov[ex2_use_mb_rb_hi_offset]), + .din(ex1_use_mb_rb_hi), + .dout(ex2_use_mb_rb_hi_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_use_mb_rb_lo_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_use_mb_rb_lo_offset]), + .scout(sov[ex2_use_mb_rb_lo_offset]), + .din(ex1_use_mb_rb_lo), + .dout(ex2_use_mb_rb_lo_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_use_me_ins_hi_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_use_me_ins_hi_offset]), + .scout(sov[ex2_use_me_ins_hi_offset]), + .din(ex1_use_me_ins_hi), + .dout(ex2_use_me_ins_hi_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_use_me_ins_lo_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_use_me_ins_lo_offset]), + .scout(sov[ex2_use_me_ins_lo_offset]), + .din(ex1_use_me_ins_lo), + .dout(ex2_use_me_ins_lo_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_use_mb_ins_hi_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_use_mb_ins_hi_offset]), + .scout(sov[ex2_use_mb_ins_hi_offset]), + .din(ex1_use_mb_ins_hi), + .dout(ex2_use_mb_ins_hi_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_use_mb_ins_lo_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_use_mb_ins_lo_offset]), + .scout(sov[ex2_use_mb_ins_lo_offset]), + .din(ex1_use_mb_ins_lo), + .dout(ex2_use_mb_ins_lo_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ins_prtyw_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_ins_prtyw_offset]), + .scout(sov[ex2_ins_prtyw_offset]), + .din(ex1_ins_prtyw), + .dout(ex2_ins_prtyw_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ins_prtyd_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_ins_prtyd_offset]), + .scout(sov[ex2_ins_prtyd_offset]), + .din(ex1_ins_prtyd), + .dout(ex2_ins_prtyd_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_mb_gt_me_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_mb_gt_me_offset]), + .scout(sov[ex2_mb_gt_me_offset]), + .din(ex1_mb_gt_me), + .dout(ex2_mb_gt_me_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_cmp_byte_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_cmp_byte_offset]), + .scout(sov[ex2_cmp_byte_offset]), + .din(ex1_cmp_byt), + .dout(ex2_cmp_byte_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sgnxtd_byte_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_sgnxtd_byte_offset]), + .scout(sov[ex2_sgnxtd_byte_offset]), + .din(ex1_sgnxtd_byte), + .dout(ex2_sgnxtd_byte_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sgnxtd_half_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_sgnxtd_half_offset]), + .scout(sov[ex2_sgnxtd_half_offset]), + .din(ex1_sgnxtd_half), + .dout(ex2_sgnxtd_half_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sgnxtd_wd_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_sgnxtd_wd_offset]), + .scout(sov[ex2_sgnxtd_wd_offset]), + .din(ex1_sgnxtd_wd), + .dout(ex2_sgnxtd_wd_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sra_wd_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_sra_wd_offset]), + .scout(sov[ex2_sra_wd_offset]), + .din(ex1_sra_wd), + .dout(ex2_sra_wd_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sra_dw_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_sra_dw_offset]), + .scout(sov[ex2_sra_dw_offset]), + .din(ex1_sra_dw), + .dout(ex2_sra_dw_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ex2_log_fcn_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_log_fcn_offset:ex2_log_fcn_offset + 4 - 1]), + .scout(sov[ex2_log_fcn_offset:ex2_log_fcn_offset + 4 - 1]), + .din(ex2_log_fcn_d), + .dout(ex2_log_fcn_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sel_rot_log_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_sel_rot_log_offset]), + .scout(sov[ex2_sel_rot_log_offset]), + .din(ex1_sel_rot_log), + .dout(ex2_sel_rot_log_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_sh_word_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_sh_word_offset]), + .scout(sov[ex3_sh_word_offset]), + .din(ex2_sh_word_q[1]), + .dout(ex3_sh_word_q) + ); + //------------------------------------------------------------------- + // Placed Latches + //------------------------------------------------------------------- + + tri_lcbnd ex3_mrg_lcb( + .vd(vdd), + .gd(gnd), + .act(ex2_act_unqiue), + .nclk(nclk), + .force_t(func_sl_force), + .thold_b(func_sl_thold_0_b), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .sg(sg_0), + .lclk(rot_lclk_int), + .d1clk(rot_d1clk_int), + .d2clk(rot_d2clk_int) + ); + + + tri_inv_nlats #(.WIDTH(64), .BTR("NLI0001_X1_A12TH"), .INIT(0)) rot_lat( + .vd(vdd), + .gd(gnd), + .lclk(rot_lclk_int), + .d1clk(rot_d1clk_int), + .d2clk(rot_d2clk_int), + .scanin(siv[ex3_rotate_b_offset:ex3_rotate_b_offset + 64 - 1]), + .scanout(sov[ex3_rotate_b_offset:ex3_rotate_b_offset + 64 - 1]), + .d(ex2_rotate), + .qb(ex3_rotate_b_q) + ); + + tri_inv_nlats #(.WIDTH(64), .BTR("NLI0001_X2_A12TH"), .INIT(0)) res_lat( + .vd(vdd), + .gd(gnd), + .lclk(rot_lclk_int), + .d1clk(rot_d1clk_int), + .d2clk(rot_d2clk_int), + .scanin(siv[ex3_result_b_offset:ex3_result_b_offset + 64 - 1]), + .scanout(sov[ex3_result_b_offset:ex3_result_b_offset + 64 - 1]), + .d(ex2_result), + .qb(ex3_result_b_q) + ); + + tri_inv_nlats #(.WIDTH(64), .BTR("NLI0001_X1_A12TH"), .INIT(0)) msk_lat( + .vd(vdd), + .gd(gnd), + .lclk(rot_lclk_int), + .d1clk(rot_d1clk_int), + .d2clk(rot_d2clk_int), + .scanin(siv[ex3_mask_b_offset:ex3_mask_b_offset + 64 - 1]), + .scanout(sov[ex3_mask_b_offset:ex3_mask_b_offset + 64 - 1]), + .d(ex2_mask), + .qb(ex3_mask_b_q) + ); + //------------------------------------------------------------------- + // End Placed Latches + //------------------------------------------------------------------- + + tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_sra_se_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_sra_se_offset:ex3_sra_se_offset + 1 - 1]), + .scout(sov[ex3_sra_se_offset:ex3_sra_se_offset + 1 - 1]), + .din(ex2_sra_se), + .dout(ex3_sra_se_q) + ); + + + tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) dummy_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b0), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[dummy_offset:dummy_offset + 1 - 1]), + .scout(sov[dummy_offset:dummy_offset + 1 - 1]), + .din(dummy_q), + .dout(dummy_q) + ); + + assign siv[0:scan_right - 1] = {sov[1:scan_right - 1], scan_in}; + assign scan_out = sov[0]; + + + +endmodule diff --git a/dev/verilog/trilib/tri_st_rot_dec.v b/dev/verilog/trilib/tri_st_rot_dec.v new file mode 100755 index 0000000..87fbb85 --- /dev/null +++ b/dev/verilog/trilib/tri_st_rot_dec.v @@ -0,0 +1,467 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: XU Rotate/Logical Unit +// +//***************************************************************************** + +module tri_st_rot_dec( + i, + ex1_zm_ins, + ex1_mb_ins, + ex1_me_ins_b, + ex1_sh_amt, + ex1_sh_right, + ex1_sh_word, + ex1_use_rb_amt_hi, + ex1_use_rb_amt_lo, + ex1_use_me_rb_hi, + ex1_use_me_rb_lo, + ex1_use_mb_rb_hi, + ex1_use_mb_rb_lo, + ex1_use_me_ins_hi, + ex1_use_me_ins_lo, + ex1_use_mb_ins_hi, + ex1_use_mb_ins_lo, + ex1_ins_prtyw, + ex1_ins_prtyd, + ex1_chk_shov_wd, + ex1_chk_shov_dw, + ex1_mb_gt_me, + ex1_cmp_byt, + ex1_sgnxtd_byte, + ex1_sgnxtd_half, + ex1_sgnxtd_wd, + ex1_sra_dw, + ex1_sra_wd, + ex1_log_fcn, + ex1_sel_rot_log +); + input [0:31] i; + + output ex1_zm_ins; + output [0:5] ex1_mb_ins; + output [0:5] ex1_me_ins_b; + output [0:5] ex1_sh_amt; + output ex1_sh_right; + output ex1_sh_word; + + output ex1_use_rb_amt_hi; + output ex1_use_rb_amt_lo; + output ex1_use_me_rb_hi; + output ex1_use_me_rb_lo; + output ex1_use_mb_rb_hi; + output ex1_use_mb_rb_lo; + output ex1_use_me_ins_hi; + output ex1_use_me_ins_lo; + output ex1_use_mb_ins_hi; + output ex1_use_mb_ins_lo; + output ex1_ins_prtyw; + output ex1_ins_prtyd; + + output ex1_chk_shov_wd; + output ex1_chk_shov_dw; + output ex1_mb_gt_me; + + output ex1_cmp_byt; + + output ex1_sgnxtd_byte; + output ex1_sgnxtd_half; + output ex1_sgnxtd_wd; + output ex1_sra_dw; + output ex1_sra_wd; + + output [0:3] ex1_log_fcn; + + output ex1_sel_rot_log; + + wire cmp_byt; + wire rotlw; + wire imm_log; + wire rotld; + wire x31; + wire f0_xxxx00; + wire f0_xxx0xx; + wire f0_xxxx0x; + wire f1_1xxxx; + wire f1_111xx; + wire f1_110xx; + wire f1_x1x1x; + wire f1_x1xx0; + wire f1_x1xx1; + wire f1_xxx00; + wire f1_xxx11; + wire f1_xx10x; + wire f2_11xxx; + wire f2_xx0xx; + wire f2_xxx00; + wire f2_xxx0x; + wire f2_111xx; + wire f1_xxx01; + wire f1_xxx10; + wire f2_xx01x; + wire f2_xx00x; + wire rotlw_nm; + wire rotlw_pass; + wire rotld_pass; + wire sh_lft_rb; + wire sh_lft_rb_dw; + wire sh_rgt; + wire sh_rgt_rb; + wire sh_rgt_rb_dw; + wire shift_imm; + wire sh_rb; + wire sh_rb_dw; + wire sh_rb_wd; + wire x31_sh_log_sgn; + wire op_sgn_xtd; + wire op_sra; + wire wd_if_sh; + wire xtd_log; + wire sh_word_int; + wire imm_xor_or; + wire imm_and_or; + wire xtd_nor; + wire xtd_eqv_orc_nand; + wire xtd_nand; + wire xtd_andc_xor_or; + wire xtd_and_eqv_orc; + wire xtd_or_orc; + wire xtd_xor_or; + wire sel_ins_amt_hi; + wire sel_ins_me_lo_wd; + wire sel_ins_me_lo_dw; + wire sel_ins_amt_lo; + wire sel_ins_me_hi; + wire rot_imm_mb; + wire gt5_g_45; + wire gt5_g_23; + wire gt5_g_1; + wire gt5_t_23; + wire gt5_t_1; + wire mb_gt_me_cmp_wd0_b; + wire mb_gt_me_cmp_wd1_b; + wire mb_gt_me_cmp_wd2_b; + wire mb_gt_me_cmp_wd; + wire gt6_g_45; + wire gt6_g_23; + wire gt6_g_01; + wire gt6_t_23; + wire gt6_t_01; + wire mb_gt_me_cmp_dw0_b; + wire mb_gt_me_cmp_dw1_b; + wire mb_gt_me_cmp_dw2_b; + wire mb_gt_me_cmp_dw; + wire [0:5] me_ins; + wire [1:5] gt5_in0; + wire [1:5] gt5_in1; + wire [0:5] gt6_in0; + wire [0:5] gt6_in1; + wire [1:5] gt5_g_b; + wire [1:4] gt5_t_b; + wire [0:5] gt6_g_b; + wire [0:4] gt6_t_b; + wire f0_xxxx11; + wire f1_0xxxx; + wire f1_1xxx0; + wire f1_xxxx0; + wire f1_xxxx1; + wire f2_xxx1x; + wire f1_xx1xx; + wire xtd_nand_or_orc; + wire rld_cr; + wire rld_cl; + wire rld_icr; + wire rld_icl; + wire rld_ic; + wire rld_imi; + wire sh_lft_imm_dw; + wire sh_lft_imm; + wire sh_rgt_imm_dw; + wire sh_rgt_imm; + wire rotld_en_mbgtme; + wire [0:3] rf1_log_fcn; + wire isel; + wire prtyw; + wire prtyd; + + //-------------------------------------------------- + // decode primary field opcode bits [0:5] --- + //-------------------------------------------------- + assign ex1_ins_prtyw = prtyw; + assign ex1_ins_prtyd = prtyd; + + assign isel = (x31 == 1'b1 & i[26:30] == 5'b01111) ? 1'b1 : + 1'b0; + + assign cmp_byt = (x31 == 1'b1 & i[21:30] == 10'b0111111100) ? 1'b1 : // 31/508 + 1'b0; + assign prtyw = (x31 == 1'b1 & i[21:30] == 10'b0010011010) ? 1'b1 : // 31/154 + 1'b0; + assign prtyd = (x31 == 1'b1 & i[21:30] == 10'b0010111010) ? 1'b1 : // 31/186 + 1'b0; + + assign rotlw = (~i[0]) & i[1] & (~i[2]) & i[3]; //0101xx (20:23) + assign imm_log = (~i[0]) & i[1] & i[2] & ((~i[3]) | (~i[4])); //0110xx (24:27) + //01110x (28,29) + assign rotld = (~i[0]) & i[1] & i[2] & i[3] & i[4] & (~i[5]); //011110 (30) + assign x31 = (~i[0]) & i[1] & i[2] & i[3] & i[4] & i[5]; //011111 (31) + + assign f0_xxxx00 = (~i[4]) & (~i[5]); + assign f0_xxx0xx = (~i[3]); + assign f0_xxxx0x = (~i[4]); + assign f0_xxxx11 = i[4] & i[5]; + + //--------------------------------------------------- + // decode i(21:25) + //--------------------------------------------------- + + assign f1_0xxxx = (~i[21]); + assign f1_110xx = i[21] & i[22] & (~i[23]); + assign f1_111xx = i[21] & i[22] & i[23]; + assign f1_1xxx0 = i[21] & (~i[25]); + assign f1_1xxxx = i[21]; + assign f1_x1x1x = i[22] & i[24]; + assign f1_xx1xx = i[23]; + assign f1_x1xx0 = i[22] & (~i[25]); + assign f1_x1xx1 = i[22] & i[25]; + assign f1_xx10x = i[23] & (~i[24]); + assign f1_xxx01 = (~i[24]) & i[25]; + assign f1_xxx11 = i[24] & i[25]; + assign f1_xxxx0 = (~i[25]); + assign f1_xxxx1 = i[25]; + assign f1_xxx00 = (~i[24]) & (~i[25]); + assign f1_xxx10 = i[24] & (~i[25]); + + //--------------------------------------------------- + // decode i(26:30) + //--------------------------------------------------- + + assign f2_11xxx = i[26] & i[27]; // shifts / logicals / sign_xtd + assign f2_xxx0x = (~i[29]); // word / double + assign f2_111xx = i[26] & i[27] & i[28]; + assign f2_xx01x = (~i[28]) & i[29]; + assign f2_xx00x = (~i[28]) & (~i[29]); + assign f2_xxx1x = i[29]; + + assign f2_xx0xx = (~i[28]); + assign f2_xxx00 = (~i[29]) & (~i[30]); + + assign rotlw_nm = rotlw & f0_xxxx11; + assign rotlw_pass = rotlw & f0_xxxx00; + + assign rotld_pass = rld_imi; + + assign sh_lft_rb = x31 & f1_0xxxx; + assign sh_lft_rb_dw = x31 & f1_0xxxx & f2_xxx1x; + assign sh_rgt = x31 & f1_1xxxx; + assign sh_rgt_rb = x31 & f1_1xxx0; + assign sh_rgt_rb_dw = x31 & f1_1xxx0 & f2_xxx1x; + assign shift_imm = x31 & f1_xxxx1; + assign sh_rb = x31 & f1_xxxx0; + assign sh_rb_dw = x31 & f1_xxxx0 & f2_xxx1x; + assign sh_rb_wd = x31 & f1_xxxx0 & f2_xxx0x; + assign x31_sh_log_sgn = x31 & f2_11xxx & (f2_xx0xx | f2_xxx00); // Exclude loads/stores + assign op_sgn_xtd = x31 & f1_111xx; + assign op_sra = x31 & f1_110xx; + assign wd_if_sh = x31 & f2_xxx0x; + assign xtd_log = x31 & f2_111xx; + + assign sh_lft_imm_dw = 0; + assign sh_lft_imm = 0; + assign sh_rgt_imm_dw = x31 & i[21] & i[25] & i[29]; + assign sh_rgt_imm = x31 & i[21] & i[25]; + + //--------------------------------------------------- + // output signal + //--------------------------------------------------- + assign ex1_cmp_byt = cmp_byt; + + // (select to rot/log result instead of the adder result) + assign ex1_sel_rot_log = (cmp_byt) | (rotlw) | (imm_log) | (rotld) | (isel) | (x31_sh_log_sgn); + // prtyw, prtyd already included here.... + + // (zero out the mask to pass "insert_data" as the result) + // This latched, full decode ok. + assign ex1_zm_ins = (isel) | (cmp_byt) | (xtd_log) | (imm_log) | (op_sgn_xtd) | (prtyw) | (prtyd); // sgn extends + + // (only needs to be correct when shifting) + assign ex1_sh_right = sh_rgt; + + assign sh_word_int = (rotlw) | (wd_if_sh); + + // (only needs to be correct when shifting) + assign ex1_sh_word = sh_word_int; + + assign ex1_sgnxtd_byte = op_sgn_xtd & f1_xxx01 & (~isel); + assign ex1_sgnxtd_half = op_sgn_xtd & f1_xxx00 & (~isel); + assign ex1_sgnxtd_wd = op_sgn_xtd & f1_xxx10 & (~isel); + assign ex1_sra_dw = op_sra & f2_xx01x & (~isel); + assign ex1_sra_wd = op_sra & f2_xx00x & (~isel); + + assign imm_xor_or = f0_xxx0xx; + assign imm_and_or = f0_xxxx0x; + assign xtd_nor = f1_xxx11; + assign xtd_eqv_orc_nand = f1_x1xx0; + assign xtd_nand = f1_x1x1x; + assign xtd_nand_or_orc = f1_xx1xx; + assign xtd_andc_xor_or = f1_xxx01; + assign xtd_and_eqv_orc = f1_xxx00; + assign xtd_or_orc = f1_xx10x; + assign xtd_xor_or = f1_x1xx1; + + assign ex1_log_fcn = (cmp_byt == 1'b1) ? 4'b1001 : // xtd_log nor + rf1_log_fcn; + assign rf1_log_fcn[0] = (xtd_log & xtd_nor) | (xtd_log & xtd_eqv_orc_nand) | (cmp_byt); // xtd_log eqv,orc,nand + // xnor + + // xtd_log xor,or + // xor,or + // pass rlwimi + assign rf1_log_fcn[1] = (xtd_log & xtd_xor_or) | (xtd_log & xtd_nand) | (imm_log & imm_xor_or) | (rotlw_pass) | (rotld_pass); // xtd_log nand + // pass rldimi + + // xtd_log andc,xor,or + assign rf1_log_fcn[2] = (xtd_log & xtd_andc_xor_or) | (xtd_log & xtd_nand_or_orc) | (imm_log & imm_xor_or); // xtd_log nand_or_orc + // xor,or + + // xnor + // xtd_log or,orc + // and,or + // pass rlwimi + assign rf1_log_fcn[3] = (cmp_byt) | (xtd_log & xtd_and_eqv_orc) | (xtd_log & xtd_or_orc) | (imm_log & imm_and_or) | (rotlw_pass) | (rotld_pass); // xtd_log and,eqv_orc + // pass rldimi + + assign ex1_chk_shov_dw = (sh_rb_dw); + assign ex1_chk_shov_wd = (sh_rb_wd); + + //--------------------------------------------- + + assign ex1_me_ins_b[0:5] = (~me_ins[0:5]); + + assign me_ins[0] = (rotlw) | (i[26] & sel_ins_me_hi) | ((~i[30]) & sel_ins_amt_hi); // force_msb + + assign me_ins[1:5] = (i[26:30] & {5{sel_ins_me_lo_wd}}) | (i[21:25] & {5{sel_ins_me_lo_dw}}) | ((~i[16:20]) & {5{sel_ins_amt_lo}}); + + assign sel_ins_me_lo_wd = rotlw; + assign sel_ins_me_lo_dw = rld_cr | rld_icr; + + assign sel_ins_amt_lo = rld_ic | rld_imi | sh_lft_rb; + assign sel_ins_amt_hi = rld_ic | rld_imi | sh_lft_rb_dw; + assign sel_ins_me_hi = rld_cr | rld_icr; + + assign ex1_use_me_rb_hi = (sh_lft_rb_dw); + assign ex1_use_me_rb_lo = (sh_lft_rb); + + assign ex1_use_me_ins_hi = rld_cr | rld_icr | rld_imi | rld_ic | rotlw | sh_lft_imm_dw; + assign ex1_use_me_ins_lo = rld_cr | rld_icr | rld_imi | rld_ic | rotlw | sh_lft_imm; + + assign rld_icl = rotld & (~i[27]) & (~i[28]) & (~i[29]); + assign rld_icr = rotld & (~i[27]) & (~i[28]) & i[29]; + assign rld_ic = rotld & (~i[27]) & i[28] & (~i[29]); + assign rld_imi = rotld & (~i[27]) & i[28] & i[29]; + assign rld_cl = rotld & i[27] & (~i[30]); + assign rld_cr = rotld & i[27] & i[30]; + + //--------------------------------------------- + + assign ex1_mb_ins[0] = (i[26] & rot_imm_mb) | (i[30] & shift_imm) | (rotlw) | (wd_if_sh); // force_msb + // force_msb + + assign ex1_mb_ins[1:5] = (i[21:25] & {5{rot_imm_mb}}) | (i[16:20] & {5{shift_imm}}); + + assign rot_imm_mb = (rotlw) | (rld_cl | rld_icl | rld_ic | rld_imi); + + assign ex1_use_mb_rb_lo = sh_rgt_rb; + assign ex1_use_mb_rb_hi = sh_rgt_rb_dw; + assign ex1_use_mb_ins_hi = rld_cl | rld_icl | rld_imi | rld_ic | rotlw | sh_rgt_imm_dw | wd_if_sh; + assign ex1_use_mb_ins_lo = rld_cl | rld_icl | rld_imi | rld_ic | rotlw | sh_rgt_imm; + + //--------------------------------------------- + + assign ex1_use_rb_amt_hi = (rld_cr) | (rld_cl) | (sh_rb_dw); + + assign ex1_use_rb_amt_lo = (rld_cr) | (rld_cl) | (rotlw_nm) | (sh_rb); // rlwnm + + assign ex1_sh_amt[0] = i[30] & (~sh_word_int); + assign ex1_sh_amt[1:5] = i[16:20]; + + //--------------------------------------------- + + assign rotld_en_mbgtme = rld_imi | rld_ic; + + assign ex1_mb_gt_me = (mb_gt_me_cmp_wd & rotlw) | (mb_gt_me_cmp_dw & rotld_en_mbgtme); // rldic,rldimi + + //------------------------------------------- + + assign gt5_in1[1:5] = i[21:25]; // mb + assign gt5_in0[1:5] = (~i[26:30]); // me + + assign gt6_in1[0:5] = {i[26], i[21:25]}; // mb + assign gt6_in0[0:5] = {i[30], i[16:20]}; // me not( not amt ) + + //------------------------------------------ + + assign gt5_g_b[1:5] = (~(gt5_in0[1:5] & gt5_in1[1:5])); + assign gt5_t_b[1:4] = (~(gt5_in0[1:4] | gt5_in1[1:4])); + + assign gt5_g_45 = (~(gt5_g_b[4] & (gt5_t_b[4] | gt5_g_b[5]))); + assign gt5_g_23 = (~(gt5_g_b[2] & (gt5_t_b[2] | gt5_g_b[3]))); + assign gt5_g_1 = (~(gt5_g_b[1])); + + assign gt5_t_23 = (~(gt5_t_b[2] | gt5_t_b[3])); + assign gt5_t_1 = (~(gt5_t_b[1])); + + assign mb_gt_me_cmp_wd0_b = (~(gt5_g_1)); + assign mb_gt_me_cmp_wd1_b = (~(gt5_g_23 & gt5_t_1)); + assign mb_gt_me_cmp_wd2_b = (~(gt5_g_45 & gt5_t_1 & gt5_t_23)); + + assign mb_gt_me_cmp_wd = (~(mb_gt_me_cmp_wd0_b & mb_gt_me_cmp_wd1_b & mb_gt_me_cmp_wd2_b)); + + //-------------------------------------------- + + assign gt6_g_b[0:5] = (~(gt6_in0[0:5] & gt6_in1[0:5])); + assign gt6_t_b[0:4] = (~(gt6_in0[0:4] | gt6_in1[0:4])); + + assign gt6_g_45 = (~(gt6_g_b[4] & (gt6_t_b[4] | gt6_g_b[5]))); + assign gt6_g_23 = (~(gt6_g_b[2] & (gt6_t_b[2] | gt6_g_b[3]))); + assign gt6_g_01 = (~(gt6_g_b[0] & (gt6_t_b[0] | gt6_g_b[1]))); + + assign gt6_t_23 = (~(gt6_t_b[2] | gt6_t_b[3])); + assign gt6_t_01 = (~(gt6_t_b[0] | gt6_t_b[1])); + + assign mb_gt_me_cmp_dw0_b = (~(gt6_g_01)); + assign mb_gt_me_cmp_dw1_b = (~(gt6_g_23 & gt6_t_01)); + assign mb_gt_me_cmp_dw2_b = (~(gt6_g_45 & gt6_t_01 & gt6_t_23)); + + assign mb_gt_me_cmp_dw = (~(mb_gt_me_cmp_dw0_b & mb_gt_me_cmp_dw1_b & mb_gt_me_cmp_dw2_b)); + + +endmodule diff --git a/dev/verilog/trilib/tri_st_rot_ins.v b/dev/verilog/trilib/tri_st_rot_ins.v new file mode 100755 index 0000000..b7b96c2 --- /dev/null +++ b/dev/verilog/trilib/tri_st_rot_ins.v @@ -0,0 +1,282 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: XU Rotate - Insert Component +// +//***************************************************************************** + +module tri_st_rot_ins( + ins_log_fcn, + ins_cmp_byt, + ins_sra_wd, + ins_sra_dw, + ins_xtd_byte, + ins_xtd_half, + ins_xtd_wd, + ins_prtyw, + ins_prtyd, + data0_i, + data1_i, + mrg_byp_log, + res_ins +); + input [0:3] ins_log_fcn; // use pass ra for rlwimi + // rs, ra/rb + // 0000 => "0" + // 0001 => rs AND rb + // 0010 => rs AND !rb + // 0011 => rs + // 0100 => !rs and RB + // 0101 => RB + // 0110 => rs xor RB + // 0111 => rs or RB + // 1000 => rs nor RB + // 1001 => rs xnor RB (use for cmp-byt) + // 1010 => !RB + // 1011 => rs or !rb + // 1100 => !rs + // 1101 => rs nand !rb, !rs or rb + // 1110 => rs nand rb ... + // 1111 => "1" + + input ins_cmp_byt; + input ins_sra_wd; + input ins_sra_dw; + + input ins_xtd_byte; // use with xtd + input ins_xtd_half; // use with xtd + input ins_xtd_wd; // use with xtd, sra + + input ins_prtyw; + input ins_prtyd; + + input [0:63] data0_i; //data input (rs) + input [0:63] data1_i; //data input (ra|rb) + output [0:63] mrg_byp_log; + output [0:63] res_ins; //insert data (also result of logicals) + + + wire [0:63] mrg_byp_log_b; + + wire [0:63] res_log; + wire [0:7] byt_cmp; + wire [0:7] byt_cmp_b; + wire [0:63] byt_cmp_bus; + wire [0:63] sign_xtd_bus; + wire [0:63] xtd_byte_bus; + wire [0:63] xtd_half_bus; + wire [0:63] xtd_wd_bus; + wire [0:63] sra_dw_bus; + wire [0:63] sra_wd_bus; + wire [0:63] res_ins0_b; + wire [0:63] res_ins1_b; + wire [0:63] res_ins2_b; + wire [0:63] res_log0_b; + wire [0:63] res_log1_b; + wire [0:63] res_log2_b; + wire [0:63] res_log3_b; + wire [0:63] res_log_o0; + wire [0:63] res_log_o1; + wire [0:63] res_log_b; + wire [0:63] res_log2; + wire [0:3] byt0_cmp2_b; + wire [0:3] byt1_cmp2_b; + wire [0:3] byt2_cmp2_b; + wire [0:3] byt3_cmp2_b; + wire [0:3] byt4_cmp2_b; + wire [0:3] byt5_cmp2_b; + wire [0:3] byt6_cmp2_b; + wire [0:3] byt7_cmp2_b; + + wire [0:1] byt0_cmp4; + wire [0:1] byt1_cmp4; + wire [0:1] byt2_cmp4; + wire [0:1] byt3_cmp4; + wire [0:1] byt4_cmp4; + wire [0:1] byt5_cmp4; + wire [0:1] byt6_cmp4; + wire [0:1] byt7_cmp4; + + wire [0:63] sel_cmp_byt; + wire [0:63] sel_cmp_byt_b; + + wire [0:63] data0_b; + wire [0:63] data1_b; + wire [0:63] data0; + wire [0:63] data1; + + wire prtyhw0; + wire prtyhw1; + wire prtyhw2; + wire prtyhw3; + wire prtyw0; + wire prtyw1; + wire prtyd; + wire prty0; + wire prty1; + + assign data0_b = (~data0_i); + assign data1_b = (~data1_i); + assign data0 = (~data0_b); + assign data1 = (~data1_b); + + assign prtyhw0 = data0_i[7] ^ data0_i[15]; + assign prtyhw1 = data0_i[23] ^ data0_i[31]; + assign prtyhw2 = data0_i[39] ^ data0_i[47]; + assign prtyhw3 = data0_i[55] ^ data0_i[63]; + + assign prtyw0 = prtyhw0 ^ prtyhw1; + assign prtyw1 = prtyhw2 ^ prtyhw3; + + assign prtyd = prtyw0 ^ prtyw1; + + assign prty1 = (prtyw1 & ins_prtyw) | (prtyd & ins_prtyd); + + assign prty0 = (prtyw0 & ins_prtyw); + + assign res_log2[31] = res_log[31] | prty0; + assign res_log2[63] = res_log[63] | prty1; + assign res_log2[0:30] = res_log[0:30]; + assign res_log2[32:62] = res_log[32:62]; + + assign res_log0_b[0:63] = (~({64{ins_log_fcn[0]}} & data0_b[0:63] & data1_b[0:63])); + assign res_log1_b[0:63] = (~({64{ins_log_fcn[1]}} & data0_b[0:63] & data1[0:63])); + assign res_log2_b[0:63] = (~({64{ins_log_fcn[2]}} & data0[0:63] & data1_b[0:63])); + assign res_log3_b[0:63] = (~({64{ins_log_fcn[3]}} & data0[0:63] & data1[0:63])); + assign res_log_o0[0:63] = (~(res_log0_b[0:63] & res_log1_b[0:63])); + assign res_log_o1[0:63] = (~(res_log2_b[0:63] & res_log3_b[0:63])); + assign res_log_b[0:63] = (~(res_log_o0[0:63] | res_log_o1[0:63])); + assign res_log[0:63] = (~(res_log_b[0:63])); + + assign mrg_byp_log_b[0:63] = (~(res_log[0:63])); + assign mrg_byp_log[0:63] = (~(mrg_byp_log_b[0:63])); + + assign byt0_cmp2_b[0] = (~(res_log[0] & res_log[1])); + assign byt0_cmp2_b[1] = (~(res_log[2] & res_log[3])); + assign byt0_cmp2_b[2] = (~(res_log[4] & res_log[5])); + assign byt0_cmp2_b[3] = (~(res_log[6] & res_log[7])); + assign byt1_cmp2_b[0] = (~(res_log[8] & res_log[9])); + assign byt1_cmp2_b[1] = (~(res_log[10] & res_log[11])); + assign byt1_cmp2_b[2] = (~(res_log[12] & res_log[13])); + assign byt1_cmp2_b[3] = (~(res_log[14] & res_log[15])); + assign byt2_cmp2_b[0] = (~(res_log[16] & res_log[17])); + assign byt2_cmp2_b[1] = (~(res_log[18] & res_log[19])); + assign byt2_cmp2_b[2] = (~(res_log[20] & res_log[21])); + assign byt2_cmp2_b[3] = (~(res_log[22] & res_log[23])); + assign byt3_cmp2_b[0] = (~(res_log[24] & res_log[25])); + assign byt3_cmp2_b[1] = (~(res_log[26] & res_log[27])); + assign byt3_cmp2_b[2] = (~(res_log[28] & res_log[29])); + assign byt3_cmp2_b[3] = (~(res_log[30] & res_log[31])); + assign byt4_cmp2_b[0] = (~(res_log[32] & res_log[33])); + assign byt4_cmp2_b[1] = (~(res_log[34] & res_log[35])); + assign byt4_cmp2_b[2] = (~(res_log[36] & res_log[37])); + assign byt4_cmp2_b[3] = (~(res_log[38] & res_log[39])); + assign byt5_cmp2_b[0] = (~(res_log[40] & res_log[41])); + assign byt5_cmp2_b[1] = (~(res_log[42] & res_log[43])); + assign byt5_cmp2_b[2] = (~(res_log[44] & res_log[45])); + assign byt5_cmp2_b[3] = (~(res_log[46] & res_log[47])); + assign byt6_cmp2_b[0] = (~(res_log[48] & res_log[49])); + assign byt6_cmp2_b[1] = (~(res_log[50] & res_log[51])); + assign byt6_cmp2_b[2] = (~(res_log[52] & res_log[53])); + assign byt6_cmp2_b[3] = (~(res_log[54] & res_log[55])); + assign byt7_cmp2_b[0] = (~(res_log[56] & res_log[57])); + assign byt7_cmp2_b[1] = (~(res_log[58] & res_log[59])); + assign byt7_cmp2_b[2] = (~(res_log[60] & res_log[61])); + assign byt7_cmp2_b[3] = (~(res_log[62] & res_log[63])); + + assign byt0_cmp4[0] = (~(byt0_cmp2_b[0] | byt0_cmp2_b[1])); + assign byt0_cmp4[1] = (~(byt0_cmp2_b[2] | byt0_cmp2_b[3])); + assign byt1_cmp4[0] = (~(byt1_cmp2_b[0] | byt1_cmp2_b[1])); + assign byt1_cmp4[1] = (~(byt1_cmp2_b[2] | byt1_cmp2_b[3])); + assign byt2_cmp4[0] = (~(byt2_cmp2_b[0] | byt2_cmp2_b[1])); + assign byt2_cmp4[1] = (~(byt2_cmp2_b[2] | byt2_cmp2_b[3])); + assign byt3_cmp4[0] = (~(byt3_cmp2_b[0] | byt3_cmp2_b[1])); + assign byt3_cmp4[1] = (~(byt3_cmp2_b[2] | byt3_cmp2_b[3])); + assign byt4_cmp4[0] = (~(byt4_cmp2_b[0] | byt4_cmp2_b[1])); + assign byt4_cmp4[1] = (~(byt4_cmp2_b[2] | byt4_cmp2_b[3])); + assign byt5_cmp4[0] = (~(byt5_cmp2_b[0] | byt5_cmp2_b[1])); + assign byt5_cmp4[1] = (~(byt5_cmp2_b[2] | byt5_cmp2_b[3])); + assign byt6_cmp4[0] = (~(byt6_cmp2_b[0] | byt6_cmp2_b[1])); + assign byt6_cmp4[1] = (~(byt6_cmp2_b[2] | byt6_cmp2_b[3])); + assign byt7_cmp4[0] = (~(byt7_cmp2_b[0] | byt7_cmp2_b[1])); + assign byt7_cmp4[1] = (~(byt7_cmp2_b[2] | byt7_cmp2_b[3])); + + assign byt_cmp_b[0] = (~(byt0_cmp4[0] & byt0_cmp4[1])); + assign byt_cmp_b[1] = (~(byt1_cmp4[0] & byt1_cmp4[1])); + assign byt_cmp_b[2] = (~(byt2_cmp4[0] & byt2_cmp4[1])); + assign byt_cmp_b[3] = (~(byt3_cmp4[0] & byt3_cmp4[1])); + assign byt_cmp_b[4] = (~(byt4_cmp4[0] & byt4_cmp4[1])); + assign byt_cmp_b[5] = (~(byt5_cmp4[0] & byt5_cmp4[1])); + assign byt_cmp_b[6] = (~(byt6_cmp4[0] & byt6_cmp4[1])); + assign byt_cmp_b[7] = (~(byt7_cmp4[0] & byt7_cmp4[1])); + + assign byt_cmp[0] = (~(byt_cmp_b[0])); + assign byt_cmp[1] = (~(byt_cmp_b[1])); + assign byt_cmp[2] = (~(byt_cmp_b[2])); + assign byt_cmp[3] = (~(byt_cmp_b[3])); + assign byt_cmp[4] = (~(byt_cmp_b[4])); + assign byt_cmp[5] = (~(byt_cmp_b[5])); + assign byt_cmp[6] = (~(byt_cmp_b[6])); + assign byt_cmp[7] = (~(byt_cmp_b[7])); + + assign byt_cmp_bus[0:7] = {8{byt_cmp[0]}}; + assign byt_cmp_bus[8:15] = {8{byt_cmp[1]}}; + assign byt_cmp_bus[16:23] = {8{byt_cmp[2]}}; + assign byt_cmp_bus[24:31] = {8{byt_cmp[3]}}; + assign byt_cmp_bus[32:39] = {8{byt_cmp[4]}}; + assign byt_cmp_bus[40:47] = {8{byt_cmp[5]}}; + assign byt_cmp_bus[48:55] = {8{byt_cmp[6]}}; + assign byt_cmp_bus[56:63] = {8{byt_cmp[7]}}; + + assign xtd_byte_bus[0:63] = {{57{data0[56]}}, data0[57:63]}; + assign xtd_half_bus[0:63] = {{49{data0[48]}}, data0[49:63]}; + + assign xtd_wd_bus[0:63] = {{33{data0[32]}}, data0[33:63]}; + assign sra_wd_bus[0:63] = {64{data0[32]}}; // all the bits for sra + assign sra_dw_bus[0:63] = {64{data0[0]}}; // all the bits for sra + + assign sign_xtd_bus[0:63] = ({64{ins_xtd_byte}} & xtd_byte_bus[0:63]) | + ({64{ins_xtd_half}} & xtd_half_bus[0:63]) | + ({64{ins_xtd_wd}} & xtd_wd_bus[0:63]) | + ({64{ins_sra_wd}} & sra_wd_bus[0:63]) | + ({64{ins_sra_dw}} & sra_dw_bus[0:63]); + + assign sel_cmp_byt = {64{ins_cmp_byt}}; + assign sel_cmp_byt_b = ~{64{ins_cmp_byt}}; + + assign res_ins0_b[0:63] = (~(sel_cmp_byt & byt_cmp_bus[0:63])); + assign res_ins1_b[0:63] = (~(sel_cmp_byt_b & res_log2[0:63])); + assign res_ins2_b[0:63] = (~(sign_xtd_bus[0:63])); + + assign res_ins[0:63] = (~(res_ins0_b[0:63] & res_ins1_b[0:63] & res_ins2_b[0:63])); //output-- + + + +endmodule diff --git a/dev/verilog/trilib/tri_st_rot_mask.v b/dev/verilog/trilib/tri_st_rot_mask.v new file mode 100755 index 0000000..c8545c2 --- /dev/null +++ b/dev/verilog/trilib/tri_st_rot_mask.v @@ -0,0 +1,375 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: XU Rotate - Mask Component +// +//***************************************************************************** + +module tri_st_rot_mask( + mb, + me_b, + zm, + mb_gt_me, + mask +); + input [0:5] mb; // where the mask begins + input [0:5] me_b; // where the mask ends + input zm; // set mask to all zeroes. ... not a rot/sh op ... all bits are shifted out + input mb_gt_me; + output [0:63] mask; // mask shows which rotator bits to keep in the result. + + wire mask_en_and; + wire mask_en_mb; + wire mask_en_me; + wire [0:63] mask0_b; + wire [0:63] mask1_b; + wire [0:63] mask2_b; + wire [0:63] mb_mask; + wire [0:63] me_mask; + + wire [0:2] mb_msk45; + wire [0:2] mb_msk45_b; + wire [0:2] mb_msk23; + wire [0:2] mb_msk23_b; + wire [0:2] mb_msk01; + wire [0:2] mb_msk01_b; + wire [0:14] mb_msk25; + wire [0:14] mb_msk25_b; + wire [0:2] mb_msk01bb; + wire [0:2] mb_msk01bbb; + wire [1:3] me_msk01; + wire [1:3] me_msk01_b; + wire [1:3] me_msk23; + wire [1:3] me_msk23_b; + wire [1:3] me_msk45; + wire [1:3] me_msk45_b; + wire [1:15] me_msk25; + wire [1:15] me_msk25_b; + wire [1:3] me_msk01bbb; + wire [1:3] me_msk01bb; + + // ----------------------------------------------------------------------------------------- + // generate the MB mask + // ----------------------------------------------------------------------------------------- + // 0123 + // ------ + // 00 => 1111 (ge) + // 01 => 0111 + // 10 => 0011 + // 11 => 0001 + + // level 1 (4 bit results) ------------ <3 loads on input> + + assign mb_msk45[0] = (~(mb[4] | mb[5])); + assign mb_msk45[1] = (~(mb[4])); + assign mb_msk45[2] = (~(mb[4] & mb[5])); + assign mb_msk23[0] = (~(mb[2] | mb[3])); + assign mb_msk23[1] = (~(mb[2])); + assign mb_msk23[2] = (~(mb[2] & mb[3])); + assign mb_msk01[0] = (~(mb[0] | mb[1])); + assign mb_msk01[1] = (~(mb[0])); + assign mb_msk01[2] = (~(mb[0] & mb[1])); + + assign mb_msk45_b[0] = (~(mb_msk45[0])); + assign mb_msk45_b[1] = (~(mb_msk45[1])); + assign mb_msk45_b[2] = (~(mb_msk45[2])); + assign mb_msk23_b[0] = (~(mb_msk23[0])); // 7 loads on output + assign mb_msk23_b[1] = (~(mb_msk23[1])); + assign mb_msk23_b[2] = (~(mb_msk23[2])); + assign mb_msk01_b[0] = (~(mb_msk01[0])); + assign mb_msk01_b[1] = (~(mb_msk01[1])); + assign mb_msk01_b[2] = (~(mb_msk01[2])); + + // level 2 (16 bit results) ------------- + + assign mb_msk25[0] = (~(mb_msk23_b[0] | mb_msk45_b[0])); + assign mb_msk25[1] = (~(mb_msk23_b[0] | mb_msk45_b[1])); + assign mb_msk25[2] = (~(mb_msk23_b[0] | mb_msk45_b[2])); + assign mb_msk25[3] = (~(mb_msk23_b[0])); + assign mb_msk25[4] = (~(mb_msk23_b[0] & (mb_msk23_b[1] | mb_msk45_b[0]))); + assign mb_msk25[5] = (~(mb_msk23_b[0] & (mb_msk23_b[1] | mb_msk45_b[1]))); + assign mb_msk25[6] = (~(mb_msk23_b[0] & (mb_msk23_b[1] | mb_msk45_b[2]))); + assign mb_msk25[7] = (~(mb_msk23_b[1])); + assign mb_msk25[8] = (~(mb_msk23_b[1] & (mb_msk23_b[2] | mb_msk45_b[0]))); + assign mb_msk25[9] = (~(mb_msk23_b[1] & (mb_msk23_b[2] | mb_msk45_b[1]))); + assign mb_msk25[10] = (~(mb_msk23_b[1] & (mb_msk23_b[2] | mb_msk45_b[2]))); + assign mb_msk25[11] = (~(mb_msk23_b[2])); + assign mb_msk25[12] = (~(mb_msk23_b[2] & mb_msk45_b[0])); + assign mb_msk25[13] = (~(mb_msk23_b[2] & mb_msk45_b[1])); + assign mb_msk25[14] = (~(mb_msk23_b[2] & mb_msk45_b[2])); + + assign mb_msk01bb[0] = (~(mb_msk01_b[0])); + assign mb_msk01bb[1] = (~(mb_msk01_b[1])); + assign mb_msk01bb[2] = (~(mb_msk01_b[2])); + + assign mb_msk25_b[0] = (~(mb_msk25[0])); + assign mb_msk25_b[1] = (~(mb_msk25[1])); + assign mb_msk25_b[2] = (~(mb_msk25[2])); + assign mb_msk25_b[3] = (~(mb_msk25[3])); + assign mb_msk25_b[4] = (~(mb_msk25[4])); + assign mb_msk25_b[5] = (~(mb_msk25[5])); + assign mb_msk25_b[6] = (~(mb_msk25[6])); + assign mb_msk25_b[7] = (~(mb_msk25[7])); + assign mb_msk25_b[8] = (~(mb_msk25[8])); + assign mb_msk25_b[9] = (~(mb_msk25[9])); + assign mb_msk25_b[10] = (~(mb_msk25[10])); + assign mb_msk25_b[11] = (~(mb_msk25[11])); + assign mb_msk25_b[12] = (~(mb_msk25[12])); + assign mb_msk25_b[13] = (~(mb_msk25[13])); + assign mb_msk25_b[14] = (~(mb_msk25[14])); + + assign mb_msk01bbb[0] = (~(mb_msk01bb[0])); + assign mb_msk01bbb[1] = (~(mb_msk01bb[1])); + assign mb_msk01bbb[2] = (~(mb_msk01bb[2])); + + // level 3 ------------------------------------------------------- + assign mb_mask[0] = (~(mb_msk01bbb[0] | mb_msk25_b[0])); + assign mb_mask[1] = (~(mb_msk01bbb[0] | mb_msk25_b[1])); + assign mb_mask[2] = (~(mb_msk01bbb[0] | mb_msk25_b[2])); + assign mb_mask[3] = (~(mb_msk01bbb[0] | mb_msk25_b[3])); + assign mb_mask[4] = (~(mb_msk01bbb[0] | mb_msk25_b[4])); + assign mb_mask[5] = (~(mb_msk01bbb[0] | mb_msk25_b[5])); + assign mb_mask[6] = (~(mb_msk01bbb[0] | mb_msk25_b[6])); + assign mb_mask[7] = (~(mb_msk01bbb[0] | mb_msk25_b[7])); + assign mb_mask[8] = (~(mb_msk01bbb[0] | mb_msk25_b[8])); + assign mb_mask[9] = (~(mb_msk01bbb[0] | mb_msk25_b[9])); + assign mb_mask[10] = (~(mb_msk01bbb[0] | mb_msk25_b[10])); + assign mb_mask[11] = (~(mb_msk01bbb[0] | mb_msk25_b[11])); + assign mb_mask[12] = (~(mb_msk01bbb[0] | mb_msk25_b[12])); + assign mb_mask[13] = (~(mb_msk01bbb[0] | mb_msk25_b[13])); + assign mb_mask[14] = (~(mb_msk01bbb[0] | mb_msk25_b[14])); + assign mb_mask[15] = (~(mb_msk01bbb[0])); + assign mb_mask[16] = (~(mb_msk01bbb[0] & (mb_msk01bbb[1] | mb_msk25_b[0]))); + assign mb_mask[17] = (~(mb_msk01bbb[0] & (mb_msk01bbb[1] | mb_msk25_b[1]))); + assign mb_mask[18] = (~(mb_msk01bbb[0] & (mb_msk01bbb[1] | mb_msk25_b[2]))); + assign mb_mask[19] = (~(mb_msk01bbb[0] & (mb_msk01bbb[1] | mb_msk25_b[3]))); + assign mb_mask[20] = (~(mb_msk01bbb[0] & (mb_msk01bbb[1] | mb_msk25_b[4]))); + assign mb_mask[21] = (~(mb_msk01bbb[0] & (mb_msk01bbb[1] | mb_msk25_b[5]))); + assign mb_mask[22] = (~(mb_msk01bbb[0] & (mb_msk01bbb[1] | mb_msk25_b[6]))); + assign mb_mask[23] = (~(mb_msk01bbb[0] & (mb_msk01bbb[1] | mb_msk25_b[7]))); + assign mb_mask[24] = (~(mb_msk01bbb[0] & (mb_msk01bbb[1] | mb_msk25_b[8]))); + assign mb_mask[25] = (~(mb_msk01bbb[0] & (mb_msk01bbb[1] | mb_msk25_b[9]))); + assign mb_mask[26] = (~(mb_msk01bbb[0] & (mb_msk01bbb[1] | mb_msk25_b[10]))); + assign mb_mask[27] = (~(mb_msk01bbb[0] & (mb_msk01bbb[1] | mb_msk25_b[11]))); + assign mb_mask[28] = (~(mb_msk01bbb[0] & (mb_msk01bbb[1] | mb_msk25_b[12]))); + assign mb_mask[29] = (~(mb_msk01bbb[0] & (mb_msk01bbb[1] | mb_msk25_b[13]))); + assign mb_mask[30] = (~(mb_msk01bbb[0] & (mb_msk01bbb[1] | mb_msk25_b[14]))); + assign mb_mask[31] = (~(mb_msk01bbb[1])); + assign mb_mask[32] = (~(mb_msk01bbb[1] & (mb_msk01bbb[2] | mb_msk25_b[0]))); + assign mb_mask[33] = (~(mb_msk01bbb[1] & (mb_msk01bbb[2] | mb_msk25_b[1]))); + assign mb_mask[34] = (~(mb_msk01bbb[1] & (mb_msk01bbb[2] | mb_msk25_b[2]))); + assign mb_mask[35] = (~(mb_msk01bbb[1] & (mb_msk01bbb[2] | mb_msk25_b[3]))); + assign mb_mask[36] = (~(mb_msk01bbb[1] & (mb_msk01bbb[2] | mb_msk25_b[4]))); + assign mb_mask[37] = (~(mb_msk01bbb[1] & (mb_msk01bbb[2] | mb_msk25_b[5]))); + assign mb_mask[38] = (~(mb_msk01bbb[1] & (mb_msk01bbb[2] | mb_msk25_b[6]))); + assign mb_mask[39] = (~(mb_msk01bbb[1] & (mb_msk01bbb[2] | mb_msk25_b[7]))); + assign mb_mask[40] = (~(mb_msk01bbb[1] & (mb_msk01bbb[2] | mb_msk25_b[8]))); + assign mb_mask[41] = (~(mb_msk01bbb[1] & (mb_msk01bbb[2] | mb_msk25_b[9]))); + assign mb_mask[42] = (~(mb_msk01bbb[1] & (mb_msk01bbb[2] | mb_msk25_b[10]))); + assign mb_mask[43] = (~(mb_msk01bbb[1] & (mb_msk01bbb[2] | mb_msk25_b[11]))); + assign mb_mask[44] = (~(mb_msk01bbb[1] & (mb_msk01bbb[2] | mb_msk25_b[12]))); + assign mb_mask[45] = (~(mb_msk01bbb[1] & (mb_msk01bbb[2] | mb_msk25_b[13]))); + assign mb_mask[46] = (~(mb_msk01bbb[1] & (mb_msk01bbb[2] | mb_msk25_b[14]))); + assign mb_mask[47] = (~(mb_msk01bbb[2])); + assign mb_mask[48] = (~(mb_msk01bbb[2] & mb_msk25_b[0])); + assign mb_mask[49] = (~(mb_msk01bbb[2] & mb_msk25_b[1])); + assign mb_mask[50] = (~(mb_msk01bbb[2] & mb_msk25_b[2])); + assign mb_mask[51] = (~(mb_msk01bbb[2] & mb_msk25_b[3])); + assign mb_mask[52] = (~(mb_msk01bbb[2] & mb_msk25_b[4])); + assign mb_mask[53] = (~(mb_msk01bbb[2] & mb_msk25_b[5])); + assign mb_mask[54] = (~(mb_msk01bbb[2] & mb_msk25_b[6])); + assign mb_mask[55] = (~(mb_msk01bbb[2] & mb_msk25_b[7])); + assign mb_mask[56] = (~(mb_msk01bbb[2] & mb_msk25_b[8])); + assign mb_mask[57] = (~(mb_msk01bbb[2] & mb_msk25_b[9])); + assign mb_mask[58] = (~(mb_msk01bbb[2] & mb_msk25_b[10])); + assign mb_mask[59] = (~(mb_msk01bbb[2] & mb_msk25_b[11])); + assign mb_mask[60] = (~(mb_msk01bbb[2] & mb_msk25_b[12])); + assign mb_mask[61] = (~(mb_msk01bbb[2] & mb_msk25_b[13])); + assign mb_mask[62] = (~(mb_msk01bbb[2] & mb_msk25_b[14])); + assign mb_mask[63] = 1; + + // ----------------------------------------------------------------------------------------- + // generate the ME mask + // ----------------------------------------------------------------------------------------- + + // level 1 (4 bit results) ------------ <3 loads on input> + + assign me_msk45[1] = (~(me_b[4] & me_b[5])); + assign me_msk45[2] = (~(me_b[4])); + assign me_msk45[3] = (~(me_b[4] | me_b[5])); + + assign me_msk23[1] = (~(me_b[2] & me_b[3])); + assign me_msk23[2] = (~(me_b[2])); + assign me_msk23[3] = (~(me_b[2] | me_b[3])); + + assign me_msk01[1] = (~(me_b[0] & me_b[1])); + assign me_msk01[2] = (~(me_b[0])); + assign me_msk01[3] = (~(me_b[0] | me_b[1])); + + assign me_msk45_b[1] = (~(me_msk45[1])); + assign me_msk45_b[2] = (~(me_msk45[2])); + assign me_msk45_b[3] = (~(me_msk45[3])); + assign me_msk23_b[1] = (~(me_msk23[1])); // 7 loads on output + assign me_msk23_b[2] = (~(me_msk23[2])); + assign me_msk23_b[3] = (~(me_msk23[3])); + assign me_msk01_b[1] = (~(me_msk01[1])); + assign me_msk01_b[2] = (~(me_msk01[2])); + assign me_msk01_b[3] = (~(me_msk01[3])); + + // level 2 (16 bit results) ------------- + + assign me_msk25[1] = (~(me_msk23_b[1] & me_msk45_b[1])); // amt >= 1 4:15 + 1:3 + assign me_msk25[2] = (~(me_msk23_b[1] & me_msk45_b[2])); // amt >= 2 4:15 + 2:3 + assign me_msk25[3] = (~(me_msk23_b[1] & me_msk45_b[3])); // amt >= 3 4:15 + 3:3 + assign me_msk25[4] = (~(me_msk23_b[1])); // amt >= 4 4:15 + assign me_msk25[5] = (~(me_msk23_b[2] & (me_msk23_b[1] | me_msk45_b[1]))); // amt >= 5 8:15 + (4:15 * 1:3) + assign me_msk25[6] = (~(me_msk23_b[2] & (me_msk23_b[1] | me_msk45_b[2]))); // amt >= 6 8:15 + (4:15 * 2:3) + assign me_msk25[7] = (~(me_msk23_b[2] & (me_msk23_b[1] | me_msk45_b[3]))); // amt >= 7 8:15 + (4:15 * 3:3) + assign me_msk25[8] = (~(me_msk23_b[2])); // amt >= 8 8:15 + assign me_msk25[9] = (~(me_msk23_b[3] & (me_msk23_b[2] | me_msk45_b[1]))); // amt >= 9 12:15 + (8:15 * 1:3) + assign me_msk25[10] = (~(me_msk23_b[3] & (me_msk23_b[2] | me_msk45_b[2]))); // amt >= 10 12:15 + (8:15 * 2:3) + assign me_msk25[11] = (~(me_msk23_b[3] & (me_msk23_b[2] | me_msk45_b[3]))); // amt >= 11 12:15 + (8:15 * 3:3) + assign me_msk25[12] = (~(me_msk23_b[3])); // amt >= 12 12:15 + assign me_msk25[13] = (~(me_msk23_b[3] | me_msk45_b[1])); // amt >= 13 12:15 & 1:3 + assign me_msk25[14] = (~(me_msk23_b[3] | me_msk45_b[2])); // amt >= 14 12:15 & 2:3 + assign me_msk25[15] = (~(me_msk23_b[3] | me_msk45_b[3])); // amt >= 15 12:15 & 3:3 + + assign me_msk01bb[1] = (~(me_msk01_b[1])); + assign me_msk01bb[2] = (~(me_msk01_b[2])); + assign me_msk01bb[3] = (~(me_msk01_b[3])); + + assign me_msk25_b[1] = (~(me_msk25[1])); + assign me_msk25_b[2] = (~(me_msk25[2])); + assign me_msk25_b[3] = (~(me_msk25[3])); + assign me_msk25_b[4] = (~(me_msk25[4])); + assign me_msk25_b[5] = (~(me_msk25[5])); + assign me_msk25_b[6] = (~(me_msk25[6])); + assign me_msk25_b[7] = (~(me_msk25[7])); + assign me_msk25_b[8] = (~(me_msk25[8])); + assign me_msk25_b[9] = (~(me_msk25[9])); + assign me_msk25_b[10] = (~(me_msk25[10])); + assign me_msk25_b[11] = (~(me_msk25[11])); + assign me_msk25_b[12] = (~(me_msk25[12])); + assign me_msk25_b[13] = (~(me_msk25[13])); + assign me_msk25_b[14] = (~(me_msk25[14])); + assign me_msk25_b[15] = (~(me_msk25[15])); + + assign me_msk01bbb[1] = (~(me_msk01bb[1])); + assign me_msk01bbb[2] = (~(me_msk01bb[2])); + assign me_msk01bbb[3] = (~(me_msk01bb[3])); + + // level 3 (16 bit results) ------------- + + assign me_mask[0] = 1; + assign me_mask[1] = (~(me_msk01bbb[1] & me_msk25_b[1])); + assign me_mask[2] = (~(me_msk01bbb[1] & me_msk25_b[2])); + assign me_mask[3] = (~(me_msk01bbb[1] & me_msk25_b[3])); + assign me_mask[4] = (~(me_msk01bbb[1] & me_msk25_b[4])); + assign me_mask[5] = (~(me_msk01bbb[1] & me_msk25_b[5])); + assign me_mask[6] = (~(me_msk01bbb[1] & me_msk25_b[6])); + assign me_mask[7] = (~(me_msk01bbb[1] & me_msk25_b[7])); + assign me_mask[8] = (~(me_msk01bbb[1] & me_msk25_b[8])); + assign me_mask[9] = (~(me_msk01bbb[1] & me_msk25_b[9])); + assign me_mask[10] = (~(me_msk01bbb[1] & me_msk25_b[10])); + assign me_mask[11] = (~(me_msk01bbb[1] & me_msk25_b[11])); + assign me_mask[12] = (~(me_msk01bbb[1] & me_msk25_b[12])); + assign me_mask[13] = (~(me_msk01bbb[1] & me_msk25_b[13])); + assign me_mask[14] = (~(me_msk01bbb[1] & me_msk25_b[14])); + assign me_mask[15] = (~(me_msk01bbb[1] & me_msk25_b[15])); + assign me_mask[16] = (~(me_msk01bbb[1])); + assign me_mask[17] = (~(me_msk01bbb[2] & (me_msk01bbb[1] | me_msk25_b[1]))); + assign me_mask[18] = (~(me_msk01bbb[2] & (me_msk01bbb[1] | me_msk25_b[2]))); + assign me_mask[19] = (~(me_msk01bbb[2] & (me_msk01bbb[1] | me_msk25_b[3]))); + assign me_mask[20] = (~(me_msk01bbb[2] & (me_msk01bbb[1] | me_msk25_b[4]))); + assign me_mask[21] = (~(me_msk01bbb[2] & (me_msk01bbb[1] | me_msk25_b[5]))); + assign me_mask[22] = (~(me_msk01bbb[2] & (me_msk01bbb[1] | me_msk25_b[6]))); + assign me_mask[23] = (~(me_msk01bbb[2] & (me_msk01bbb[1] | me_msk25_b[7]))); + assign me_mask[24] = (~(me_msk01bbb[2] & (me_msk01bbb[1] | me_msk25_b[8]))); + assign me_mask[25] = (~(me_msk01bbb[2] & (me_msk01bbb[1] | me_msk25_b[9]))); + assign me_mask[26] = (~(me_msk01bbb[2] & (me_msk01bbb[1] | me_msk25_b[10]))); + assign me_mask[27] = (~(me_msk01bbb[2] & (me_msk01bbb[1] | me_msk25_b[11]))); + assign me_mask[28] = (~(me_msk01bbb[2] & (me_msk01bbb[1] | me_msk25_b[12]))); + assign me_mask[29] = (~(me_msk01bbb[2] & (me_msk01bbb[1] | me_msk25_b[13]))); + assign me_mask[30] = (~(me_msk01bbb[2] & (me_msk01bbb[1] | me_msk25_b[14]))); + assign me_mask[31] = (~(me_msk01bbb[2] & (me_msk01bbb[1] | me_msk25_b[15]))); + assign me_mask[32] = (~(me_msk01bbb[2])); + assign me_mask[33] = (~(me_msk01bbb[3] & (me_msk01bbb[2] | me_msk25_b[1]))); + assign me_mask[34] = (~(me_msk01bbb[3] & (me_msk01bbb[2] | me_msk25_b[2]))); + assign me_mask[35] = (~(me_msk01bbb[3] & (me_msk01bbb[2] | me_msk25_b[3]))); + assign me_mask[36] = (~(me_msk01bbb[3] & (me_msk01bbb[2] | me_msk25_b[4]))); + assign me_mask[37] = (~(me_msk01bbb[3] & (me_msk01bbb[2] | me_msk25_b[5]))); + assign me_mask[38] = (~(me_msk01bbb[3] & (me_msk01bbb[2] | me_msk25_b[6]))); + assign me_mask[39] = (~(me_msk01bbb[3] & (me_msk01bbb[2] | me_msk25_b[7]))); + assign me_mask[40] = (~(me_msk01bbb[3] & (me_msk01bbb[2] | me_msk25_b[8]))); + assign me_mask[41] = (~(me_msk01bbb[3] & (me_msk01bbb[2] | me_msk25_b[9]))); + assign me_mask[42] = (~(me_msk01bbb[3] & (me_msk01bbb[2] | me_msk25_b[10]))); + assign me_mask[43] = (~(me_msk01bbb[3] & (me_msk01bbb[2] | me_msk25_b[11]))); + assign me_mask[44] = (~(me_msk01bbb[3] & (me_msk01bbb[2] | me_msk25_b[12]))); + assign me_mask[45] = (~(me_msk01bbb[3] & (me_msk01bbb[2] | me_msk25_b[13]))); + assign me_mask[46] = (~(me_msk01bbb[3] & (me_msk01bbb[2] | me_msk25_b[14]))); + assign me_mask[47] = (~(me_msk01bbb[3] & (me_msk01bbb[2] | me_msk25_b[15]))); + assign me_mask[48] = (~(me_msk01bbb[3])); + assign me_mask[49] = (~(me_msk01bbb[3] | me_msk25_b[1])); + assign me_mask[50] = (~(me_msk01bbb[3] | me_msk25_b[2])); + assign me_mask[51] = (~(me_msk01bbb[3] | me_msk25_b[3])); + assign me_mask[52] = (~(me_msk01bbb[3] | me_msk25_b[4])); + assign me_mask[53] = (~(me_msk01bbb[3] | me_msk25_b[5])); + assign me_mask[54] = (~(me_msk01bbb[3] | me_msk25_b[6])); + assign me_mask[55] = (~(me_msk01bbb[3] | me_msk25_b[7])); + assign me_mask[56] = (~(me_msk01bbb[3] | me_msk25_b[8])); + assign me_mask[57] = (~(me_msk01bbb[3] | me_msk25_b[9])); + assign me_mask[58] = (~(me_msk01bbb[3] | me_msk25_b[10])); + assign me_mask[59] = (~(me_msk01bbb[3] | me_msk25_b[11])); + assign me_mask[60] = (~(me_msk01bbb[3] | me_msk25_b[12])); + assign me_mask[61] = (~(me_msk01bbb[3] | me_msk25_b[13])); + assign me_mask[62] = (~(me_msk01bbb[3] | me_msk25_b[14])); + assign me_mask[63] = (~(me_msk01bbb[3] | me_msk25_b[15])); + + // ------------------------------------------------------------------------------------------ + // Generally the mask starts at bit MB[] and ends at bit ME[] ... (MB[] and ME[]) + // For non-rotate/shift operations the mask is forced to zero by the ZM control. + // There are 3 rotate-word operations where MB could be greater than ME. + // in that case the mask is speced to be (MB[] or ME[]). + // For those cases, the mask always comes from the instruction bits, is always word mode, + // and the MB>ME compare can be done during the instruction decode cycle. + // ------------------------------------------------------------------------------------------- + + assign mask_en_and = (~mb_gt_me) & (~zm); // could restrict this to only rotates if shifts included below + assign mask_en_mb = mb_gt_me & (~zm); // could alternatively include shift right + assign mask_en_me = mb_gt_me & (~zm); // could alternatively include shift left + + assign mask0_b[0:63] = (~(mb_mask[0:63] & me_mask[0:63] & {64{mask_en_and}})); + assign mask1_b[0:63] = (~(mb_mask[0:63] & {64{mask_en_mb}})); + assign mask2_b[0:63] = (~(me_mask[0:63] & {64{mask_en_me}})); + + assign mask[0:63] = (~(mask0_b[0:63] & mask1_b[0:63] & mask2_b[0:63])); + + +endmodule diff --git a/dev/verilog/trilib/tri_st_rot_rol64.v b/dev/verilog/trilib/tri_st_rot_rol64.v new file mode 100755 index 0000000..88105dc --- /dev/null +++ b/dev/verilog/trilib/tri_st_rot_rol64.v @@ -0,0 +1,259 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: XU Rotate - Rotate Component +// +//***************************************************************************** + +module tri_st_rot_rol64( + word, + right, + amt, + data_i, + res_rot +); + input [0:1] word; // PPC word mode rotate <2 copies> + input [0:2] right; // emulate a shift right with a rotate left <2 copies> + input [0:5] amt; // shift amout [0:63] + input [0:63] data_i; // data to be shifted + output [0:63] res_rot; // mask shows which rotator bits to keep in the result. + + wire [0:2] right_b; + wire [0:5] amt_b; + wire [0:1] word_b; + wire [0:31] word_bus; + wire [0:31] word_bus_b; + wire [0:31] data_i0_adj_b; + wire [0:63] data_i_adj; + wire [0:63] data_i1_adj_b; + + wire [0:63] rolx16_0; + wire [0:63] rolx16_1; + wire [0:63] rolx16_2; + wire [0:63] rolx16_3; + wire [0:63] rolx04_0; + wire [0:63] rolx04_1; + wire [0:63] rolx04_2; + wire [0:63] rolx04_3; + wire [0:63] rolx01_0; + wire [0:63] rolx01_1; + wire [0:63] rolx01_2; + wire [0:63] rolx01_3; + wire [0:63] rolx01_4; + wire [0:63] shd16; + wire [0:63] shd16_0_b; + wire [0:63] shd16_1_b; + wire [0:63] shd04; + wire [0:63] shd04_0_b; + wire [0:63] shd04_1_b; + wire [0:63] shd01_0_b; + wire [0:63] shd01_1_b; + wire [0:63] shd01_2_b; + wire [0:3] x16_lft_b; + wire [0:3] x16_rgt_b; + wire [0:3] lftx16; + wire [0:3] x04_lft_b; + wire [0:3] x04_rgt_b; + wire [0:3] lftx04; + wire [0:3] x01_lft_b; + wire [0:3] x01_rgt_b; + wire [0:4] lftx01; + + wire [0:4] lftx01_inv; + wire [0:4] lftx01_buf0; + wire [0:4] lftx01_buf1; + wire [0:3] lftx04_inv; + wire [0:3] lftx04_buf0; + wire [0:3] lftx04_buf1; + wire [0:3] lftx16_inv; + wire [0:3] lftx16_buf0; + wire [0:3] lftx16_buf1; + wire [0:63] lftx16_0_bus; + wire [0:63] lftx16_1_bus; + wire [0:63] lftx16_2_bus; + wire [0:63] lftx16_3_bus; + wire [0:63] lftx04_0_bus; + wire [0:63] lftx04_1_bus; + wire [0:63] lftx04_2_bus; + wire [0:63] lftx04_3_bus; + wire [0:63] lftx01_0_bus; + wire [0:63] lftx01_1_bus; + wire [0:63] lftx01_2_bus; + wire [0:63] lftx01_3_bus; + wire [0:63] lftx01_4_bus; + // ------------------------------------------------------------- + // how the ppc emulates a rot32 using rot64 hardware. + // this makes the wrapping corect for the low order 32 bits. + // upper 32 result bits a garbage + //-------------------------------------------------------------- + + assign word_b[0:1] = (~word[0:1]); + + assign word_bus_b[0:15] = {16{word_b[0]}}; + assign word_bus_b[16:31] = {16{word_b[1]}}; + assign word_bus[0:15] = {16{word[0]}}; + assign word_bus[16:31] = {16{word[1]}}; + + assign data_i0_adj_b[0:31] = (~(data_i[0:31] & word_bus_b[0:31])); + assign data_i1_adj_b[0:31] = (~(data_i[32:63] & word_bus[0:31])); + assign data_i_adj[0:31] = (~(data_i0_adj_b[0:31] & data_i1_adj_b[0:31])); + + assign data_i1_adj_b[32:63] = (~(data_i[32:63])); + assign data_i_adj[32:63] = (~(data_i1_adj_b[32:63])); + + //--------------------------------------------------------------- + // decoder without the adder + //--------------------------------------------------------------- + //rotate right by [n] == rotate_left by width -[n] == !n + 1 + + assign right_b[0:2] = (~right[0:2]); + assign amt_b[0:5] = (~amt[0:5]); + + assign x16_lft_b[0] = (~(right_b[0] & amt_b[0] & amt_b[1])); + assign x16_lft_b[1] = (~(right_b[0] & amt_b[0] & amt[1])); + assign x16_lft_b[2] = (~(right_b[0] & amt[0] & amt_b[1])); + assign x16_lft_b[3] = (~(right_b[0] & amt[0] & amt[1])); + + assign x16_rgt_b[0] = (~(right[0] & amt_b[0] & amt_b[1])); + assign x16_rgt_b[1] = (~(right[0] & amt_b[0] & amt[1])); + assign x16_rgt_b[2] = (~(right[0] & amt[0] & amt_b[1])); + assign x16_rgt_b[3] = (~(right[0] & amt[0] & amt[1])); + + assign lftx16[0] = (~(x16_lft_b[0] & x16_rgt_b[3])); + assign lftx16[1] = (~(x16_lft_b[1] & x16_rgt_b[2])); + assign lftx16[2] = (~(x16_lft_b[2] & x16_rgt_b[1])); + assign lftx16[3] = (~(x16_lft_b[3] & x16_rgt_b[0])); + + assign x04_lft_b[0] = (~(right_b[1] & amt_b[2] & amt_b[3])); + assign x04_lft_b[1] = (~(right_b[1] & amt_b[2] & amt[3])); + assign x04_lft_b[2] = (~(right_b[1] & amt[2] & amt_b[3])); + assign x04_lft_b[3] = (~(right_b[1] & amt[2] & amt[3])); + + assign x04_rgt_b[0] = (~(right[1] & amt_b[2] & amt_b[3])); + assign x04_rgt_b[1] = (~(right[1] & amt_b[2] & amt[3])); + assign x04_rgt_b[2] = (~(right[1] & amt[2] & amt_b[3])); + assign x04_rgt_b[3] = (~(right[1] & amt[2] & amt[3])); + + assign lftx04[0] = (~(x04_lft_b[0] & x04_rgt_b[3])); + assign lftx04[1] = (~(x04_lft_b[1] & x04_rgt_b[2])); + assign lftx04[2] = (~(x04_lft_b[2] & x04_rgt_b[1])); + assign lftx04[3] = (~(x04_lft_b[3] & x04_rgt_b[0])); + + assign x01_lft_b[0] = (~(right_b[2] & amt_b[4] & amt_b[5])); + assign x01_lft_b[1] = (~(right_b[2] & amt_b[4] & amt[5])); + assign x01_lft_b[2] = (~(right_b[2] & amt[4] & amt_b[5])); + assign x01_lft_b[3] = (~(right_b[2] & amt[4] & amt[5])); + + assign x01_rgt_b[0] = (~(right[2] & amt_b[4] & amt_b[5])); + assign x01_rgt_b[1] = (~(right[2] & amt_b[4] & amt[5])); + assign x01_rgt_b[2] = (~(right[2] & amt[4] & amt_b[5])); + assign x01_rgt_b[3] = (~(right[2] & amt[4] & amt[5])); + + assign lftx01[0] = (~(x01_lft_b[0])); // the shift is like the +1 + assign lftx01[1] = (~(x01_lft_b[1] & x01_rgt_b[3])); + assign lftx01[2] = (~(x01_lft_b[2] & x01_rgt_b[2])); + assign lftx01[3] = (~(x01_lft_b[3] & x01_rgt_b[1])); + assign lftx01[4] = (~(x01_rgt_b[0])); + + assign lftx16_inv[0:3] = (~(lftx16[0:3])); + assign lftx16_buf0[0:3] = (~(lftx16_inv[0:3])); + assign lftx16_buf1[0:3] = (~(lftx16_inv[0:3])); + + assign lftx04_inv[0:3] = (~(lftx04[0:3])); + assign lftx04_buf0[0:3] = (~(lftx04_inv[0:3])); + assign lftx04_buf1[0:3] = (~(lftx04_inv[0:3])); + + assign lftx01_inv[0:4] = (~(lftx01[0:4])); + assign lftx01_buf0[0:4] = (~(lftx01_inv[0:4])); + assign lftx01_buf1[0:4] = (~(lftx01_inv[0:4])); + + assign lftx16_0_bus[0:31] = {32{lftx16_buf0[0]}}; + assign lftx16_0_bus[32:63] = {32{lftx16_buf1[0]}}; + assign lftx16_1_bus[0:31] = {32{lftx16_buf0[1]}}; + assign lftx16_1_bus[32:63] = {32{lftx16_buf1[1]}}; + assign lftx16_2_bus[0:31] = {32{lftx16_buf0[2]}}; + assign lftx16_2_bus[32:63] = {32{lftx16_buf1[2]}}; + assign lftx16_3_bus[0:31] = {32{lftx16_buf0[3]}}; + assign lftx16_3_bus[32:63] = {32{lftx16_buf1[3]}}; + + assign lftx04_0_bus[0:31] = {32{lftx04_buf0[0]}}; + assign lftx04_0_bus[32:63] = {32{lftx04_buf1[0]}}; + assign lftx04_1_bus[0:31] = {32{lftx04_buf0[1]}}; + assign lftx04_1_bus[32:63] = {32{lftx04_buf1[1]}}; + assign lftx04_2_bus[0:31] = {32{lftx04_buf0[2]}}; + assign lftx04_2_bus[32:63] = {32{lftx04_buf1[2]}}; + assign lftx04_3_bus[0:31] = {32{lftx04_buf0[3]}}; + assign lftx04_3_bus[32:63] = {32{lftx04_buf1[3]}}; + + assign lftx01_0_bus[0:31] = {32{lftx01_buf0[0]}}; + assign lftx01_0_bus[32:63] = {32{lftx01_buf1[0]}}; + assign lftx01_1_bus[0:31] = {32{lftx01_buf0[1]}}; + assign lftx01_1_bus[32:63] = {32{lftx01_buf1[1]}}; + assign lftx01_2_bus[0:31] = {32{lftx01_buf0[2]}}; + assign lftx01_2_bus[32:63] = {32{lftx01_buf1[2]}}; + assign lftx01_3_bus[0:31] = {32{lftx01_buf0[3]}}; + assign lftx01_3_bus[32:63] = {32{lftx01_buf1[3]}}; + assign lftx01_4_bus[0:31] = {32{lftx01_buf0[4]}}; + assign lftx01_4_bus[32:63] = {32{lftx01_buf1[4]}}; + + //--------------------------------------------------------------- + // the shifter + //--------------------------------------------------------------- + + assign rolx16_0[0:63] = data_i_adj[0:63]; + assign rolx16_1[0:63] = {data_i_adj[16:63], data_i_adj[0:15]}; + assign rolx16_2[0:63] = {data_i_adj[32:63], data_i_adj[0:31]}; + assign rolx16_3[0:63] = {data_i_adj[48:63], data_i_adj[0:47]}; + + assign shd16_0_b[0:63] = (~((lftx16_0_bus[0:63] & rolx16_0[0:63]) | (lftx16_1_bus[0:63] & rolx16_1[0:63]))); + assign shd16_1_b[0:63] = (~((lftx16_2_bus[0:63] & rolx16_2[0:63]) | (lftx16_3_bus[0:63] & rolx16_3[0:63]))); + assign shd16[0:63] = (~(shd16_0_b[0:63] & shd16_1_b[0:63])); + + assign rolx04_0[0:63] = shd16[0:63]; + assign rolx04_1[0:63] = {shd16[4:63], shd16[0:3]}; + assign rolx04_2[0:63] = {shd16[8:63], shd16[0:7]}; + assign rolx04_3[0:63] = {shd16[12:63], shd16[0:11]}; + + assign shd04_0_b[0:63] = (~((lftx04_0_bus[0:63] & rolx04_0[0:63]) | (lftx04_1_bus[0:63] & rolx04_1[0:63]))); + assign shd04_1_b[0:63] = (~((lftx04_2_bus[0:63] & rolx04_2[0:63]) | (lftx04_3_bus[0:63] & rolx04_3[0:63]))); + assign shd04[0:63] = (~(shd04_0_b[0:63] & shd04_1_b[0:63])); + + assign rolx01_0[0:63] = shd04[0:63]; + assign rolx01_1[0:63] = {shd04[1:63], shd04[0]}; + assign rolx01_2[0:63] = {shd04[2:63], shd04[0:1]}; + assign rolx01_3[0:63] = {shd04[3:63], shd04[0:2]}; + assign rolx01_4[0:63] = {shd04[4:63], shd04[0:3]}; + + assign shd01_0_b[0:63] = (~((lftx01_0_bus[0:63] & rolx01_0[0:63]) | (lftx01_1_bus[0:63] & rolx01_1[0:63]))); + assign shd01_1_b[0:63] = (~((lftx01_2_bus[0:63] & rolx01_2[0:63]) | (lftx01_3_bus[0:63] & rolx01_3[0:63]))); + assign shd01_2_b[0:63] = (~(lftx01_4_bus[0:63] & rolx01_4[0:63])); + assign res_rot[0:63] = (~(shd01_0_b[0:63] & shd01_1_b[0:63] & shd01_2_b[0:63])); + +endmodule diff --git a/dev/verilog/trilib/tri_xnor2.v b/dev/verilog/trilib/tri_xnor2.v new file mode 100755 index 0000000..9b04670 --- /dev/null +++ b/dev/verilog/trilib/tri_xnor2.v @@ -0,0 +1,63 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILENAME : tri_xnor2.v +// *! DESCRIPTION : Two input XNOR gate +// *! +// *!**************************************************************** + +`include "tri_a2o.vh" + +module tri_xnor2( + y, + a, + b +); + parameter WIDTH = 1; + parameter BTR = "XNOR2_X2M_NONE"; //Specify full BTR name, else let tool select + output [0:WIDTH-1] y; + input [0:WIDTH-1] a; + input [0:WIDTH-1] b; + + genvar i; + + generate + begin : t + for (i = 0; i < WIDTH; i = i + 1) + begin : w + + xnor I0(y[i], a[i], b[i]); + + end // block: w + end + + endgenerate +endmodule diff --git a/dev/verilog/trilib/tri_xor2.v b/dev/verilog/trilib/tri_xor2.v new file mode 100755 index 0000000..3a42be9 --- /dev/null +++ b/dev/verilog/trilib/tri_xor2.v @@ -0,0 +1,63 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILENAME : tri_xor2.v +// *! DESCRIPTION : Two input XOR gate +// *! +// *!**************************************************************** + +`include "tri_a2o.vh" + +module tri_xor2( + y, + a, + b +); + parameter WIDTH = 1; + parameter BTR = "XOR2_X2M_NONE"; //Specify full BTR name, else let tool select + output [0:WIDTH-1] y; + input [0:WIDTH-1] a; + input [0:WIDTH-1] b; + + genvar i; + + generate + begin : t + for (i = 0; i < WIDTH; i = i + 1) + begin : w + + xor I0(y[i], a[i], b[i]); + + end // block: w + end + + endgenerate +endmodule diff --git a/dev/verilog/trilib/tri_xor3.v b/dev/verilog/trilib/tri_xor3.v new file mode 100755 index 0000000..3cd931a --- /dev/null +++ b/dev/verilog/trilib/tri_xor3.v @@ -0,0 +1,64 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// *!**************************************************************** +// *! FILENAME : tri_xor3.v +// *! DESCRIPTION : Three input XOR gate +// *! +// *!**************************************************************** + +`include "tri_a2o.vh" + +module tri_xor3( + y, + a, + b, + c +); + parameter WIDTH = 1; + parameter BTR = "XOR2_X2M_NONE"; //Specify full BTR name, else let tool select + output [0:WIDTH-1] y; + input [0:WIDTH-1] a; + input [0:WIDTH-1] b; + input [0:WIDTH-1] c; + genvar i; + + generate + begin : t + for (i = 0; i < WIDTH; i = i + 1) + begin : w + + xor I0(y[i], a[i], b[i], c[i]); + + end // block: w + end + + endgenerate +endmodule diff --git a/dev/verilog/trilib_clk1x/tri_144x78_2r4w.v b/dev/verilog/trilib_clk1x/tri_144x78_2r4w.v new file mode 100755 index 0000000..6c8de0c --- /dev/null +++ b/dev/verilog/trilib_clk1x/tri_144x78_2r4w.v @@ -0,0 +1,143 @@ +//wtf rewrite as sim-only using only clk1x + +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ps / 1 ps + +//***************************************************************************** +// Description: Tri-Lam Array Wrapper +// +//***************************************************************************** + +`include "tri_a2o.vh" + +module tri_144x78_2r4w( + // Inputs + // Power + inout vdd, + inout gnd, + // Clock & Scan + input [0:`NCLK_WIDTH-1] nclk, + + //------------------------------------------------------------------- + // Pervasive + //------------------------------------------------------------------- + input delay_lclkr_dc, + input mpw1_dc_b, + input mpw2_dc_b, + input func_sl_force, + input func_sl_thold_0_b, + input func_slp_sl_force, + input func_slp_sl_thold_0_b, + input sg_0, + input scan_in, + output scan_out, + + //------------------------------------------------------------------- + // Read Port + //------------------------------------------------------------------- + input r_late_en_1, + input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r_addr_in_1, + output [64-`GPR_WIDTH:77] r_data_out_1, + input r_late_en_2, + input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r_addr_in_2, + output [64-`GPR_WIDTH:77] r_data_out_2, + + //------------------------------------------------------------------- + // Write Port + //------------------------------------------------------------------- + input w_late_en_1, + input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w_addr_in_1, + input [64-`GPR_WIDTH:77] w_data_in_1, + input w_late_en_2, + input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w_addr_in_2, + input [64-`GPR_WIDTH:77] w_data_in_2, + input w_late_en_3, + input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w_addr_in_3, + input [64-`GPR_WIDTH:77] w_data_in_3, + input w_late_en_4, + input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w_addr_in_4, + input [64-`GPR_WIDTH:77] w_data_in_4 +); + + // sim array + reg [64-`GPR_WIDTH:77] mem[0:143]; + + reg [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r1a_q; + wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r1a_d; + reg [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r2a_q; + wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r2a_d; + + reg [64-`GPR_WIDTH:77] r1d_q; + wire [64-`GPR_WIDTH:77] r1d_d; + reg [64-`GPR_WIDTH:77] r2d_q; + wire [64-`GPR_WIDTH:77] r2d_d; + + integer i; + initial begin + for (i = 0; i < 144; i = i + 1) + mem[i] = 0; + end + + assign r1a_d = r_addr_in_1; + assign r2a_d = r_addr_in_2; + + always @(posedge nclk[0]) begin + + r1a_q <= r1a_d; + r2a_q <= r2a_d; + + r1d_q <= r1d_d; + r2d_q <= r2d_d; + + if (w_late_en_1) begin + mem[w_addr_in_1] <= w_data_in_1; + end + if (w_late_en_2) begin + mem[w_addr_in_2] <= w_data_in_2; + end + if (w_late_en_3) begin + mem[w_addr_in_3] <= w_data_in_3; + end + if (w_late_en_4) begin + mem[w_addr_in_4] <= w_data_in_4; + end + + end + + // r_late_en_x are unused in original also + assign r1d_d = mem[r1a_q]; + assign r2d_d = mem[r2a_q]; + + assign r_data_out_1 = r1d_q; + assign r_data_out_2 = r2d_q; + + assign unused = | {func_slp_sl_force, func_slp_sl_thold_0_b}; + +endmodule diff --git a/dev/verilog/unisims/RAM64X1D.v b/dev/verilog/unisims/RAM64X1D.v new file mode 100755 index 0000000..01c9029 --- /dev/null +++ b/dev/verilog/unisims/RAM64X1D.v @@ -0,0 +1,34 @@ +`timescale 1 ps / 1 ps + +module RAM64X1D #( + parameter [63:0] INIT = 64'h0 +) ( + input WCLK, + input WE, + input A0, A1, A2, A3, A4, A5, + input D, + output SPO, + input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5, + output DPO +); + + reg [63:0] mem; + wire [5:0] A; + wire [5:0] DPRA; + + assign A = {A5, A4, A3, A2, A1, A0}; + assign DPO = mem[{DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}]; + + initial begin : INIT_STATE + mem = INIT; + end + + always @(posedge WCLK) begin + if (WE == 1'b1) begin + mem[A] <= D; + end + end + + assign SPO = mem[A]; + +endmodule diff --git a/dev/verilog/unisims/RAMB16_S18_S18.v b/dev/verilog/unisims/RAMB16_S18_S18.v new file mode 100755 index 0000000..1710e11 --- /dev/null +++ b/dev/verilog/unisims/RAMB16_S18_S18.v @@ -0,0 +1,79 @@ +`timescale 1 ps / 1 ps + +module RAMB16_S18_S18 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter bramAddrWidth = 9; + parameter SIM_COLLISION_CHECK = ""; + + output [15:0] DOA; + output [15:0] DOB; + output [1:0] DOPA; + output [1:0] DOPB; + input [9:0] ADDRA; + input [9:0] ADDRB; + input CLKA; + input CLKB; + input [15:0] DIA; + input [15:0] DIB; + input [1:0] DIPA; + input [1:0] DIPB; + input ENA; + input ENB; + input SSRA; + input SSRB; + input WEA; + input WEB; + + wire [17:0] dina; + wire [17:0] dinb; + wire [17:0] douta; + wire [17:0] doutb; + wire [bramAddrWidth-1:0] bAddrA; + wire [bramAddrWidth-1:0] bAddrB; + wire unused; + + assign unused = |ADDRA[9:bramAddrWidth] | |ADDRB[9:bramAddrWidth]; + + assign dina[17:9] = {DIPA[1], DIA[15:8]}; + assign dina[8:0] = {DIPA[0], DIA[7:0]}; + + assign dinb[17:9] = {DIPB[1], DIB[15:8]}; + assign dinb[8:0] = {DIPB[0], DIB[7:0]}; + + assign DOA[15:8] = douta[16:9]; + assign DOA[7:0] = douta[7:0]; + + assign DOPA[1:0] = {douta[17], douta[8]}; + + assign DOB[15:8] = doutb[16:9]; + assign DOB[7:0] = doutb[7:0]; + + assign DOPB[1:0] = {doutb[17], doutb[8]}; + + assign bAddrA = ADDRA[(bramAddrWidth)-1:0]; + assign bAddrB = ADDRB[(bramAddrWidth)-1:0]; + + generate begin + genvar i; + for (i = 1; i >= 0; i = i - 1) begin : ra + bram_model #(.data_w(9), .addr_w(bramAddrWidth)) bram_model( + .DIA(dina[((i + 1) * 9) - 1:i * 9]), + .DIB(dinb[((i + 1) * 9) - 1:i * 9]), + .ADDRA(bAddrA), + .ADDRB(bAddrB), + .CLKA(CLKA), + .CLKB(CLKB), + .DOA(douta[((i + 1) * 9) - 1:i * 9]), + .DOB(doutb[((i + 1) * 9) - 1:i * 9]), + .SSRA(SSRA), + .SSRB(SSRB), + .WEA(WEA), + .WEB(WEB), + .ENA(ENA), + .ENB(ENB) + ); + end + end + endgenerate + +endmodule diff --git a/dev/verilog/unisims/RAMB16_S36_S36.v b/dev/verilog/unisims/RAMB16_S36_S36.v new file mode 100755 index 0000000..b503401 --- /dev/null +++ b/dev/verilog/unisims/RAMB16_S36_S36.v @@ -0,0 +1,90 @@ +`timescale 1 ps / 1 ps + +module RAMB16_S36_S36 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter bramAddrWidth = 9; + parameter INIT_A = 36'h0; + parameter INIT_B = 36'h0; + parameter SRVAL_A = 36'h0; + parameter SRVAL_B = 36'h0; + parameter SIM_COLLISION_CHECK = ""; + parameter WRITE_MODE_A = "T"; + parameter WRITE_MODE_B = "T"; + + output [31:0] DOA; + output [31:0] DOB; + output [3:0] DOPA; + output [3:0] DOPB; + input [8:0] ADDRA; + input [8:0] ADDRB; + input CLKA; + input CLKB; + input [31:0] DIA; + input [31:0] DIB; + input [3:0] DIPA; + input [3:0] DIPB; + input ENA; + input ENB; + input SSRA; + input SSRB; + input WEA; + input WEB; + + wire [35:0] dina; + wire [35:0] dinb; + wire [35:0] douta; + wire [35:0] doutb; + wire [bramAddrWidth-1:0] bAddrA; + wire [bramAddrWidth-1:0] bAddrB; + + assign dina[35:27] = {DIPA[3], DIA[31:24]}; + assign dina[26:18] = {DIPA[2], DIA[23:16]}; + assign dina[17:9] = {DIPA[1], DIA[15:8]}; + assign dina[8:0] = {DIPA[0], DIA[7:0]}; + + assign dinb[35:27] = {DIPB[3], DIB[31:24]}; + assign dinb[26:18] = {DIPB[2], DIB[23:16]}; + assign dinb[17:9] = {DIPB[1], DIB[15:8]}; + assign dinb[8:0] = {DIPB[0], DIB[7:0]}; + + assign DOA[31:24] = douta[34:27]; + assign DOA[23:16] = douta[25:18]; + assign DOA[15:8] = douta[16:9]; + assign DOA[7:0] = douta[7:0]; + + assign DOPA[3:0] = {douta[35], douta[26], douta[17], douta[8]}; + + assign DOB[31:24] = doutb[34:27]; + assign DOB[23:16] = doutb[25:18]; + assign DOB[15:8] = doutb[16:9]; + assign DOB[7:0] = doutb[7:0]; + + assign DOPB[3:0] = {doutb[35], doutb[26], doutb[17], doutb[8]}; + + assign bAddrA = ADDRA[(bramAddrWidth)-1:0]; + assign bAddrB = ADDRB[(bramAddrWidth)-1:0]; + + generate begin + genvar i; + for (i = 3; i >= 0; i = i - 1) begin: ra + bram_model #(.data_w(9), .addr_w(bramAddrWidth)) bram_model( + .DIA(dina[((i + 1) * 9) - 1:i * 9]), + .DIB(dinb[((i + 1) * 9) - 1:i * 9]), + .ADDRA(bAddrA), + .ADDRB(bAddrB), + .CLKA(CLKA), + .CLKB(CLKB), + .DOA(douta[((i + 1) * 9) - 1:i * 9]), + .DOB(doutb[((i + 1) * 9) - 1:i * 9]), + .SSRA(SSRA), + .SSRB(SSRB), + .WEA(WEA), + .WEB(WEB), + .ENA(ENA), + .ENB(ENB) + ); + end + end + endgenerate + +endmodule diff --git a/dev/verilog/unisims/RAMB16_S9_S9.v b/dev/verilog/unisims/RAMB16_S9_S9.v new file mode 100755 index 0000000..d6430d2 --- /dev/null +++ b/dev/verilog/unisims/RAMB16_S9_S9.v @@ -0,0 +1,76 @@ +`timescale 1 ps / 1 ps + +module RAMB16_S9_S9 (DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, SSRA, SSRB, WEA, WEB); + + parameter bramAddrWidth = 9; + parameter SIM_COLLISION_CHECK = ""; + + output [7:0] DOA; + output [7:0] DOB; + output DOPA; + output DOPB; + + input [10:0] ADDRA; + input [10:0] ADDRB; + input CLKA; + input CLKB; + input [7:0] DIA; + input [7:0] DIB; + input DIPA; + input DIPB; + input ENA; + input ENB; + input SSRA; + input SSRB; + input WEA; + input WEB; + + wire [8:0] dina; + wire [8:0] dinb; + wire [8:0] douta; + wire [8:0] doutb; + wire [bramAddrWidth-1:0] bAddrA; + wire [bramAddrWidth-1:0] bAddrB; + wire unused; + + assign unused = |ADDRA[10:bramAddrWidth] | |ADDRB[10:bramAddrWidth]; + + assign dina[8:0] = {DIPA, DIA[7:0]}; + + assign dinb[8:0] = {DIPB, DIB[7:0]}; + + assign DOA[7:0] = douta[7:0]; + + assign DOPA = douta[8]; + + assign DOB[7:0] = doutb[7:0]; + + assign DOPB = doutb[8]; + + assign bAddrA = ADDRA[(bramAddrWidth)-1:0]; + assign bAddrB = ADDRB[(bramAddrWidth)-1:0]; + + generate begin + genvar i; + for (i = 0; i >= 0; i = i - 1) begin : ra + bram_model #(.data_w(9), .addr_w(bramAddrWidth)) bram_model( + .DIA(dina[((i + 1) * 9) - 1:i * 9]), + .DIB(dinb[((i + 1) * 9) - 1:i * 9]), + .ADDRA(bAddrA), + .ADDRB(bAddrB), + .CLKA(CLKA), + .CLKB(CLKB), + .DOA(douta[((i + 1) * 9) - 1:i * 9]), + .DOB(doutb[((i + 1) * 9) - 1:i * 9]), + .SSRA(SSRA), + .SSRB(SSRB), + .WEA(WEA), + .WEB(WEB), + .ENA(ENA), + .ENB(ENB) + ); + end + end + endgenerate + +endmodule diff --git a/dev/verilog/unisims/RAMB36.v b/dev/verilog/unisims/RAMB36.v new file mode 100755 index 0000000..be406c0 --- /dev/null +++ b/dev/verilog/unisims/RAMB36.v @@ -0,0 +1,111 @@ +`timescale 1 ps / 1 ps + +module RAMB36(CASCADEOUTLATA, CASCADEOUTLATB, CASCADEOUTREGA, CASCADEOUTREGB, DOA, DOB, DOPA, DOPB, ADDRA, ADDRB, CASCADEINLATA, CASCADEINLATB, CASCADEINREGA, CASCADEINREGB, + CLKA, CLKB, DIA, DIB, DIPA, DIPB, ENA, ENB, REGCEA, REGCEB, SSRA, SSRB, WEA, WEB); + + parameter bramAddrWidth = 10; + parameter READ_WIDTH_A = 0; + parameter READ_WIDTH_B = 0; + parameter WRITE_WIDTH_A = 0; + parameter WRITE_WIDTH_B = 0; + parameter SIM_COLLISION_CHECK = ""; + parameter WRITE_MODE_A = ""; + parameter WRITE_MODE_B = ""; + + output CASCADEOUTLATA; + output CASCADEOUTLATB; + output CASCADEOUTREGA; + output CASCADEOUTREGB; + output [31:0] DOA; + output [31:0] DOB; + output [3:0] DOPA; + output [3:0] DOPB; + + input [15:0] ADDRA; + input [15:0] ADDRB; + input CASCADEINLATA; + input CASCADEINLATB; + input CASCADEINREGA; + input CASCADEINREGB; + input CLKA; + input CLKB; + input [31:0] DIA; + input [31:0] DIB; + input [3:0] DIPA; + input [3:0] DIPB; + input ENA; + input ENB; + input REGCEA; + input REGCEB; + input SSRA; + input SSRB; + input [3:0] WEA; + input [3:0] WEB; + + wire [35:0] dina; + wire [35:0] dinb; + wire [35:0] douta; + wire [35:0] doutb; + wire [bramAddrWidth-1:0] bAddrA; + wire [bramAddrWidth-1:0] bAddrB; + + wire unused; + + assign dina[35:27] = {DIPA[3], DIA[31:24]}; + assign dina[26:18] = {DIPA[2], DIA[23:16]}; + assign dina[17:9] = {DIPA[1], DIA[15:8]}; + assign dina[8:0] = {DIPA[0], DIA[7:0]}; + + assign dinb[35:27] = {DIPB[3], DIB[31:24]}; + assign dinb[26:18] = {DIPB[2], DIB[23:16]}; + assign dinb[17:9] = {DIPB[1], DIB[15:8]}; + assign dinb[8:0] = {DIPB[0], DIB[7:0]}; + + assign DOA[31:24] = douta[34:27]; + assign DOA[23:16] = douta[25:18]; + assign DOA[15:8] = douta[16:9]; + assign DOA[7:0] = douta[7:0]; + + assign DOPA[3:0] = {douta[35], douta[26], douta[17], douta[8]}; + + assign DOB[31:24] = doutb[34:27]; + assign DOB[23:16] = doutb[25:18]; + assign DOB[15:8] = doutb[16:9]; + assign DOB[7:0] = doutb[7:0]; + + assign DOPB[3:0] = {doutb[35], doutb[26], doutb[17], doutb[8]}; + + assign bAddrA = ADDRA[(bramAddrWidth+5)-1:5]; + assign bAddrB = ADDRB[(bramAddrWidth+5)-1:5]; + + generate begin + genvar i; + for (i = 3; i >= 0; i = i - 1) begin: ra + bram_model #(.data_w(9), .addr_w(bramAddrWidth)) bram_model( + .DIA(dina[((i + 1) * 9) - 1:i * 9]), + .DIB(dinb[((i + 1) * 9) - 1:i * 9]), + .ADDRA(bAddrA), + .ADDRB(bAddrB), + .CLKA(CLKA), + .CLKB(CLKB), + .DOA(douta[((i + 1) * 9) - 1:i * 9]), + .DOB(doutb[((i + 1) * 9) - 1:i * 9]), + .SSRA(SSRA), + .SSRB(SSRB), + .WEA(WEA[i]), + .WEB(WEB[i]), + .ENA(ENA), + .ENB(ENB) + ); + end + end + endgenerate + + assign CASCADEOUTLATA = 1'b0; + assign CASCADEOUTLATB = 1'b0; + assign CASCADEOUTREGA = 1'b0; + assign CASCADEOUTREGB = 1'b0; + + assign unused = CASCADEINLATA | CASCADEINLATB | CASCADEINREGA | CASCADEINREGB | |ADDRA[15:14] | |ADDRA[4:0] | |ADDRB[15:14] | |ADDRB[4:0] | REGCEA | REGCEB; + +endmodule diff --git a/dev/verilog/unisims/bram_model.v b/dev/verilog/unisims/bram_model.v new file mode 100755 index 0000000..c9b32fc --- /dev/null +++ b/dev/verilog/unisims/bram_model.v @@ -0,0 +1,65 @@ +`timescale 1 ps / 1 ps + +module bram_model (DIA, DIB, ENA, ENB, WEA, WEB, SSRA, SSRB, CLKA, CLKB, ADDRA, ADDRB, DOA, DOB); + + parameter data_w = 2; + parameter addr_w = 13; + input [data_w-1:0] DIA; + input [data_w-1:0] DIB; + input ENA; + input ENB; + input WEA; + input WEB; + input SSRA; + input SSRB; + input CLKA; + input CLKB; + input [addr_w-1:0] ADDRA; + input [addr_w-1:0] ADDRB; + output [data_w-1:0] DOA; + output [data_w-1:0] DOB; + + reg [data_w-1:0] MEM[2**addr_w-1:0]; + reg [data_w-1:0] DOA_q; + reg [data_w-1:0] DOB_q; + + + initial begin + integer i; + for (i = 0; i < 2**addr_w; i = i + 1) + MEM[i] <= 0; + end + + always @(posedge CLKA, posedge CLKB) begin: BRAM_MODEL + if (ENA) begin + if (WEA) begin + MEM[ADDRA] <= DIA; + end + end + + if (ENB) begin + if (WEB) begin + MEM[ADDRB] <= DIB; + end + end + + end + + always @(posedge CLKA) begin + if (SSRA) + DOA_q <= {data_w{1'b0}}; + else + DOA_q <= MEM[ADDRA]; + end + + always @(posedge CLKB) begin + if (SSRB) + DOB_q <= {data_w{1'b0}}; + else + DOB_q <= MEM[ADDRB]; + end + + assign DOA = DOA_q; + assign DOB = DOB_q; + +endmodule diff --git a/dev/verilog/unisims_synth/RAM64X1D.v b/dev/verilog/unisims_synth/RAM64X1D.v new file mode 100755 index 0000000..6a9cc9b --- /dev/null +++ b/dev/verilog/unisims_synth/RAM64X1D.v @@ -0,0 +1,14 @@ +(* blackbox *) +module RAM64X1D #( + parameter [63:0] INIT = 64'h0 +) +( + input WCLK, + input WE, + input A0, A1, A2, A3, A4, A5, + input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5, + input D, + output SPO, + output DPO +); +endmodule diff --git a/dev/verilog/unisims_synth/RAMB16_S18_S18.v b/dev/verilog/unisims_synth/RAMB16_S18_S18.v new file mode 100755 index 0000000..6bf226a --- /dev/null +++ b/dev/verilog/unisims_synth/RAMB16_S18_S18.v @@ -0,0 +1,18 @@ +(* blackbox *) +module RAMB16_S18_S18 #( + parameter SIM_COLLISION_CHECK = "ALL", +) ( + input ENA, CLKA, WEA, SSRA, + input [9:0] ADDRA, + input [15:0] DIA, + input [1:0] DIPA, + output [15:0] DOA, + output [1:0] DOPA, + input ENB, CLKB, WEB, SSRB, + input [9:0] ADDRB, + input [15:0] DIB, + input [1:0] DIPB, + output [15:0] DOB, + output [1:0] DOPB +); +endmodule diff --git a/dev/verilog/unisims_synth/RAMB16_S36_S36.v b/dev/verilog/unisims_synth/RAMB16_S36_S36.v new file mode 100755 index 0000000..23fda7e --- /dev/null +++ b/dev/verilog/unisims_synth/RAMB16_S36_S36.v @@ -0,0 +1,18 @@ +(* blackbox *) +module RAMB16_S36_S36 #( + parameter SIM_COLLISION_CHECK = "ALL", +) ( + input ENA, CLKA, WEA, SSRA, + input [8:0] ADDRA, + input [31:0] DIA, + input [3:0] DIPA, + output [31:0] DOA, + output [3:0] DOPA, + input [8:0] ADDRB, + input [31:0] DIB, + input [3:0] DIPB, + input ENB, CLKB, WEB, SSRB, + output [31:0] DOB, + output [3:0] DOPB +); +endmodule diff --git a/dev/verilog/unisims_synth/RAMB16_S9_S9.v b/dev/verilog/unisims_synth/RAMB16_S9_S9.v new file mode 100755 index 0000000..17108d8 --- /dev/null +++ b/dev/verilog/unisims_synth/RAMB16_S9_S9.v @@ -0,0 +1,18 @@ +(* blackbox *) +module RAMB16_S9_S9 #( + parameter SIM_COLLISION_CHECK = "ALL", +) ( + input ENA, CLKA, WEA, SSRA, + input [10:0] ADDRA, + input [7:0] DIA, + input [0:0] DIPA, + output [7:0] DOA, + output [0:0] DOPA, + input ENB, CLKB, WEB, SSRB, + input [10:0] ADDRB, + input [7:0] DIB, + input [0:0] DIPB, + output [7:0] DOB, + output [0:0] DOPB +); +endmodule diff --git a/dev/verilog/unisims_synth/RAMB36.v b/dev/verilog/unisims_synth/RAMB36.v new file mode 100755 index 0000000..a3c09c6 --- /dev/null +++ b/dev/verilog/unisims_synth/RAMB36.v @@ -0,0 +1,28 @@ +(* blackbox *) +module RAMB36 #( + parameter integer READ_WIDTH_A = 0, + parameter integer READ_WIDTH_B = 0, + parameter SIM_COLLISION_CHECK = "ALL", + parameter WRITE_MODE_A = "WRITE_FIRST", + parameter WRITE_MODE_B = "WRITE_FIRST", + parameter integer WRITE_WIDTH_A = 0, + parameter integer WRITE_WIDTH_B = 0 +) ( + input ENA, CLKA, SSRA, CASCADEINLATA, CASCADEINREGA, REGCEA, + input [3:0] WEA, + input [15:0] ADDRA, + input [31:0] DIA, + input [3:0] DIPA, + output [31:0] DOA, + output [3:0] DOPA, + output [3:0] DOPB, + input ENB, CLKB, SSRB, CASCADEINLATB, CASCADEINREGB, REGCEB, + input [15:0] ADDRB, + input [31:0] DIB, + input [3:0] DIPB, + input [3:0] WEB, + output [31:0] DOB, + output CASCADEOUTLATA, CASCADEOUTREGA, + output CASCADEOUTLATB, CASCADEOUTREGB +); +endmodule diff --git a/dev/verilog/work/c.v b/dev/verilog/work/c.v new file mode 100755 index 0000000..4033ed0 --- /dev/null +++ b/dev/verilog/work/c.v @@ -0,0 +1,5062 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +//******************************************************************** +//* +//* TITLE: +//* +//* NAME: c.v +//* +//********************************************************************* + +`timescale 1 ns / 1 ns + +// For RLMs & Top-level only +(* recursive_synthesis="0" *) + +module c( +`include "tri_a2o.vh" +// inout vcs, +// inout vdd, +// inout gnd, + input[0:`NCLK_WIDTH-1] nclk, + input scan_in, + output scan_out, + + // Pervasive clock control + input an_ac_rtim_sl_thold_8, + input an_ac_func_sl_thold_8, + input an_ac_func_nsl_thold_8, + input an_ac_ary_nsl_thold_8, + input an_ac_sg_8, + input an_ac_fce_8, + input [0:7] an_ac_abst_scan_in, + + // L2 STCX complete + input [0:`THREADS-1] an_ac_stcx_complete, + input [0:`THREADS-1] an_ac_stcx_pass, + + // ICBI ACK Interface + input an_ac_icbi_ack, + input [0:1] an_ac_icbi_ack_thread, + + // Back invalidate interface + input an_ac_back_inv, + input [64-`REAL_IFAR_WIDTH:63] an_ac_back_inv_addr, + input [0:4] an_ac_back_inv_target, // connect to bit(0) + input an_ac_back_inv_local, + input an_ac_back_inv_lbit, + input an_ac_back_inv_gs, + input an_ac_back_inv_ind, + input [0:7] an_ac_back_inv_lpar_id, + output ac_an_back_inv_reject, + output [0:7] ac_an_lpar_id, + + // L2 Reload Inputs + input an_ac_reld_data_vld, // reload data is coming next cycle + input [0:4] an_ac_reld_core_tag, // reload data destinatoin tag (which load queue) + input [0:127] an_ac_reld_data, // Reload Data + input [58:59] an_ac_reld_qw, // quadword address of reload data beat + input an_ac_reld_ecc_err, // Reload Data contains a Correctable ECC error + input an_ac_reld_ecc_err_ue, // Reload Data contains an Uncorrectable ECC error + input an_ac_reld_data_coming, + input an_ac_reld_ditc, + input an_ac_reld_crit_qw, + input an_ac_reld_l1_dump, + input [0:3] an_ac_req_spare_ctrl_a1, // spare control bits from L2 + + // load/store credit control + input an_ac_flh2l2_gate, // Gate L1 Hit forwarding SPR config bit + input an_ac_req_ld_pop, // credit for a load (L2 can take a load command) + input an_ac_req_st_pop, // credit for a store (L2 can take a store command) + input an_ac_req_st_gather, // credit for a store due to L2 gathering of store commands + input [0:`THREADS-1] an_ac_sync_ack, + + //SCOM Satellite + input [0:3] an_ac_scom_sat_id, + input an_ac_scom_dch, + input an_ac_scom_cch, + output ac_an_scom_dch, + output ac_an_scom_cch, + + // FIR and Error Signals + output [0:`THREADS-1] ac_an_special_attn, + output [0:2] ac_an_checkstop, + output [0:2] ac_an_local_checkstop, + output [0:2] ac_an_recov_err, + output ac_an_trace_error, + output ac_an_livelock_active, + input an_ac_checkstop, + input [0:`THREADS-1] an_ac_external_mchk, + + // Perfmon Event Bus + output [0:4*`THREADS-1] ac_an_event_bus0, + output [0:4*`THREADS-1] ac_an_event_bus1, + + // Reset related + input an_ac_reset_1_complete, + input an_ac_reset_2_complete, + input an_ac_reset_3_complete, + input an_ac_reset_wd_complete, + + // Power Management + output [0:`THREADS-1] ac_an_pm_thread_running, + input [0:`THREADS-1] an_ac_pm_thread_stop, + input [0:`THREADS-1] an_ac_pm_fetch_halt, + output ac_an_power_managed, + output ac_an_rvwinkle_mode, + + // Clock, Test, and LCB Controls + input an_ac_gsd_test_enable_dc, + input an_ac_gsd_test_acmode_dc, + input an_ac_ccflush_dc, + input an_ac_ccenable_dc, + input an_ac_lbist_en_dc, + input an_ac_lbist_ip_dc, + input an_ac_lbist_ac_mode_dc, + input an_ac_scan_diag_dc, + input an_ac_scan_dis_dc_b, + + //Thold input to clock control macro + input [0:8] an_ac_scan_type_dc, + + // Pervasive + output ac_an_reset_1_request, + output ac_an_reset_2_request, + output ac_an_reset_3_request, + output ac_an_reset_wd_request, + input an_ac_lbist_ary_wrt_thru_dc, + input [0:`THREADS-1] an_ac_reservation_vld, + input [0:`THREADS-1] an_ac_sleep_en, + input [0:`THREADS-1] an_ac_ext_interrupt, + input [0:`THREADS-1] an_ac_crit_interrupt, + input [0:`THREADS-1] an_ac_perf_interrupt, + input [0:`THREADS-1] an_ac_hang_pulse, + input an_ac_tb_update_enable, + input an_ac_tb_update_pulse, + input [0:3] an_ac_chipid_dc, + input [0:7] an_ac_coreid, + output [0:`THREADS-1] ac_an_machine_check, + input an_ac_debug_stop, + output [0:`THREADS-1] ac_an_debug_trigger, + input [0:`THREADS-1] an_ac_uncond_dbg_event, + output [0:31] ac_an_debug_bus, + output ac_an_coretrace_first_valid, // coretrace_ctrls[0] + output ac_an_coretrace_valid, // coretrace_ctrls[1] + output [0:1] ac_an_coretrace_type, // coretrace_ctrls[2:3] + + // L2 Outputs + output ac_an_req_pwr_token, // power token for command coming next cycle + output ac_an_req, // command request valid + output [64-`REAL_IFAR_WIDTH:63] ac_an_req_ra, // real address for request + output [0:5] ac_an_req_ttype, // command (transaction) type + output [0:2] ac_an_req_thread, // encoded thread ID + output ac_an_req_wimg_w, // write-through + output ac_an_req_wimg_i, // cache-inhibited + output ac_an_req_wimg_m, // memory coherence required + output ac_an_req_wimg_g, // guarded memory + output [0:3] ac_an_req_user_defined, // User Defined Bits + output [0:3] ac_an_req_spare_ctrl_a0, // Spare bits + output [0:4] ac_an_req_ld_core_tag, // load command tag (which load Q) + output [0:2] ac_an_req_ld_xfr_len, // transfer length for non-cacheable load + output [0:31] ac_an_st_byte_enbl, // byte enables for store data + output [0:255] ac_an_st_data, // store data + output ac_an_req_endian, // endian mode (0=big endian, 1=little endian) + output ac_an_st_data_pwr_token // store data power token + + ); + + + parameter float_type = 1; + + // I$ + // Cache inject + wire iu_pc_err_icache_parity; + wire iu_pc_err_icachedir_parity; + wire iu_pc_err_icachedir_multihit; + wire iu_pc_err_ierat_multihit; + wire iu_pc_err_ierat_parity; + wire pc_iu_inj_icache_parity; + wire pc_iu_inj_icachedir_parity; + wire pc_iu_init_reset; + // spr ring + wire iu_slowspr_val_out; + wire iu_slowspr_rw_out; + wire [0:1] iu_slowspr_etid_out; + wire [0:9] iu_slowspr_addr_out; + wire [64-`GPR_WIDTH:63] iu_slowspr_data_out; + wire iu_slowspr_done_out; + wire iu_slowspr_val_in; + wire iu_slowspr_rw_in; + wire [0:1] iu_slowspr_etid_in; + wire [0:9] iu_slowspr_addr_in; + wire [64-`GPR_WIDTH:63] iu_slowspr_data_in; + wire iu_slowspr_done_in; + wire xu_slowspr_val_out; + wire xu_slowspr_rw_out; + wire [0:1] xu_slowspr_etid_out; + wire [0:9] xu_slowspr_addr_out; + wire [64-`GPR_WIDTH:63] xu_slowspr_data_out; + wire xu_slowspr_val_in; + wire xu_slowspr_rw_in; + wire [0:1] xu_slowspr_etid_in; + wire [0:9] xu_slowspr_addr_in; + wire [64-`GPR_WIDTH:63] xu_slowspr_data_in; + wire xu_slowspr_done_in; + wire lq_slowspr_val_out; + wire lq_slowspr_rw_out; + wire [0:1] lq_slowspr_etid_out; + wire [0:9] lq_slowspr_addr_out; + wire [64-`GPR_WIDTH:63] lq_slowspr_data_out; + wire lq_slowspr_done_out; + wire lq_slowspr_val_in; + wire lq_slowspr_rw_in; + wire [0:1] lq_slowspr_etid_in; + wire [0:9] lq_slowspr_addr_in; + wire [64-`GPR_WIDTH:63] lq_slowspr_data_in; + wire lq_slowspr_done_in; + wire pc_slowspr_val_out; + wire pc_slowspr_rw_out; + wire [0:1] pc_slowspr_etid_out; + wire [0:9] pc_slowspr_addr_out; + wire [64-`GPR_WIDTH:63] pc_slowspr_data_out; + wire pc_slowspr_done_out; + wire pc_slowspr_val_in; + wire pc_slowspr_rw_in; + wire [0:1] pc_slowspr_etid_in; + wire [0:9] pc_slowspr_addr_in; + wire [64-`GPR_WIDTH:63] pc_slowspr_data_in; + wire pc_slowspr_done_in; + wire fu_slowspr_val_out; + wire fu_slowspr_rw_out; + wire [0:1] fu_slowspr_etid_out; + wire [0:9] fu_slowspr_addr_out; + wire [64-`GPR_WIDTH:63] fu_slowspr_data_out; + wire fu_slowspr_done_out; + wire fu_slowspr_val_in; + wire fu_slowspr_rw_in; + wire [0:1] fu_slowspr_etid_in; + wire [0:9] fu_slowspr_addr_in; + wire [64-`GPR_WIDTH:63] fu_slowspr_data_in; + wire fu_slowspr_done_in; + wire mm_slowspr_val_out; + wire mm_slowspr_rw_out; + wire [0:1] mm_slowspr_etid_out; + wire [0:9] mm_slowspr_addr_out; + wire [64-`GPR_WIDTH:63] mm_slowspr_data_out; + wire mm_slowspr_done_out; + wire mm_slowspr_val_in; + wire mm_slowspr_rw_in; + wire [0:1] mm_slowspr_etid_in; + wire [0:9] mm_slowspr_addr_in; + wire [64-`GPR_WIDTH:63] mm_slowspr_data_in; + wire mm_slowspr_done_in; + + // XU-IU interface + wire xu_iu_hid_mmu_mode; + + // IU-ERAT interface + wire iu_mm_ierat_req; + wire iu_mm_ierat_req_nonspec; + wire [0:51] iu_mm_ierat_epn; + wire [0:`THREADS-1] iu_mm_ierat_thdid; + wire [0:3] iu_mm_ierat_state; + wire [0:13] iu_mm_ierat_tid; + wire [0:`THREADS-1] iu_mm_ierat_flush; + wire [0:`THREADS-1] iu_mm_perf_itlb; + wire [0:4] mm_iu_ierat_rel_val; + wire [0:131] mm_iu_ierat_rel_data; + wire [0:13] mm_iu_t0_ierat_pid; + wire [0:19] mm_iu_t0_ierat_mmucr0; +`ifndef THREADS1 + wire [0:13] mm_iu_t1_ierat_pid; + wire [0:19] mm_iu_t1_ierat_mmucr0; +`endif + wire mm_iu_tlbwe_binv; + wire [0:5] cp_mm_except_taken_t0; +`ifndef THREADS1 + wire [0:5] cp_mm_except_taken_t1; +`endif + + wire [0:17] iu_mm_ierat_mmucr0; + wire [0:`THREADS-1] iu_mm_ierat_mmucr0_we; + wire [0:8] mm_iu_ierat_mmucr1; + wire [0:3] iu_mm_ierat_mmucr1; + wire [0:`THREADS-1] iu_mm_ierat_mmucr1_we; + wire mm_iu_ierat_snoop_coming; + wire mm_iu_ierat_snoop_val; + wire [0:25] mm_iu_ierat_snoop_attr; + wire [(62-`EFF_IFAR_ARCH):51] mm_iu_ierat_snoop_vpn; + wire iu_mm_ierat_snoop_ack; + wire [0:`THREADS-1] iu_mm_hold_ack; + wire [0:`THREADS-1] iu_mm_bus_snoop_hold_ack; + wire [0:`THREADS-1] mm_iu_bus_snoop_hold_req; + wire [0:`THREADS-1] mm_iu_bus_snoop_hold_done; + wire [0:`THREADS-1] mm_iu_tlbi_complete; + wire [0:`THREADS-1] mm_iu_hold_req; + wire [0:`THREADS-1] mm_iu_hold_done; + wire [0:`THREADS-1] mm_iu_flush_req; + + // IU-LQ interface + wire [0:`THREADS-1] iu_lq_request; + wire [0:1] iu_lq_cTag; + wire [64-`REAL_IFAR_WIDTH:59] iu_lq_ra; + wire [0:4] iu_lq_wimge; + wire [0:3] iu_lq_userdef; + wire [0:`THREADS-1] lq_iu_icbi_val; + wire [64-`REAL_IFAR_WIDTH:57] lq_iu_icbi_addr; + wire [0:`THREADS-1] iu_lq_icbi_complete; + wire lq_iu_ici_val; + // IU-RV interface + wire iu_rv_iu6_t0_i0_vld; + wire iu_rv_iu6_t0_i0_act; + wire iu_rv_iu6_t0_i0_rte_lq; + wire iu_rv_iu6_t0_i0_rte_sq; + wire iu_rv_iu6_t0_i0_rte_fx0; + wire iu_rv_iu6_t0_i0_rte_fx1; + wire iu_rv_iu6_t0_i0_rte_axu0; + wire iu_rv_iu6_t0_i0_rte_axu1; + wire [0:31] iu_rv_iu6_t0_i0_instr; + wire [0:`EFF_IFAR_WIDTH-1] iu_rv_iu6_t0_i0_ifar; + wire [0:2] iu_rv_iu6_t0_i0_ucode; + wire iu_rv_iu6_t0_i0_2ucode; + wire [0:`UCODE_ENTRIES_ENC-1] iu_rv_iu6_t0_i0_ucode_cnt; + wire [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i0_itag; + wire iu_rv_iu6_t0_i0_ord; + wire iu_rv_iu6_t0_i0_cord; + wire iu_rv_iu6_t0_i0_spec; + wire iu_rv_iu6_t0_i0_t1_v; + wire [0:2] iu_rv_iu6_t0_i0_t1_t; + wire [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_t1_p; + wire iu_rv_iu6_t0_i0_t2_v; + wire [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_t2_p; + wire [0:2] iu_rv_iu6_t0_i0_t2_t; + wire iu_rv_iu6_t0_i0_t3_v; + wire [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_t3_p; + wire [0:2] iu_rv_iu6_t0_i0_t3_t; + wire iu_rv_iu6_t0_i0_s1_v; + wire [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_s1_p; + wire [0:2] iu_rv_iu6_t0_i0_s1_t; + wire iu_rv_iu6_t0_i0_s2_v; + wire [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_s2_p; + wire [0:2] iu_rv_iu6_t0_i0_s2_t; + wire iu_rv_iu6_t0_i0_s3_v; + wire [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_s3_p; + wire [0:2] iu_rv_iu6_t0_i0_s3_t; + wire [0:3] iu_rv_iu6_t0_i0_ilat; + wire [0:`EFF_IFAR_WIDTH-1] iu_rv_iu6_t0_i0_bta; + wire iu_rv_iu6_t0_i0_bta_val; + wire iu_rv_iu6_t0_i0_br_pred; + wire [0:`EFF_IFAR_WIDTH-1] iu_rv_iu6_t0_i0_fusion; + wire [0:2] iu_rv_iu6_t0_i0_ls_ptr; + wire [0:17] iu_rv_iu6_t0_i0_gshare; + wire iu_rv_iu6_t0_i0_bh_update; + wire iu_rv_iu6_t0_i0_isLoad; + wire iu_rv_iu6_t0_i0_isStore; + wire [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i0_s1_itag; + wire [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i0_s2_itag; + wire [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i0_s3_itag; + + wire iu_rv_iu6_t0_i1_vld; + wire iu_rv_iu6_t0_i1_act; + wire iu_rv_iu6_t0_i1_rte_lq; + wire iu_rv_iu6_t0_i1_rte_sq; + wire iu_rv_iu6_t0_i1_rte_fx0; + wire iu_rv_iu6_t0_i1_rte_fx1; + wire iu_rv_iu6_t0_i1_rte_axu0; + wire iu_rv_iu6_t0_i1_rte_axu1; + wire [0:31] iu_rv_iu6_t0_i1_instr; + wire [0:`EFF_IFAR_WIDTH-1] iu_rv_iu6_t0_i1_ifar; + wire [0:2] iu_rv_iu6_t0_i1_ucode; + wire [0:`UCODE_ENTRIES_ENC-1] iu_rv_iu6_t0_i1_ucode_cnt; + wire [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i1_itag; + wire iu_rv_iu6_t0_i1_ord; + wire iu_rv_iu6_t0_i1_cord; + wire iu_rv_iu6_t0_i1_spec; + wire iu_rv_iu6_t0_i1_t1_v; + wire [0:2] iu_rv_iu6_t0_i1_t1_t; + wire [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_t1_p; + wire iu_rv_iu6_t0_i1_t2_v; + wire [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_t2_p; + wire [0:2] iu_rv_iu6_t0_i1_t2_t; + wire iu_rv_iu6_t0_i1_t3_v; + wire [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_t3_p; + wire [0:2] iu_rv_iu6_t0_i1_t3_t; + wire iu_rv_iu6_t0_i1_s1_v; + wire [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_s1_p; + wire [0:2] iu_rv_iu6_t0_i1_s1_t; + wire iu_rv_iu6_t0_i1_s1_dep_hit; + wire iu_rv_iu6_t0_i1_s2_v; + wire [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_s2_p; + wire [0:2] iu_rv_iu6_t0_i1_s2_t; + wire iu_rv_iu6_t0_i1_s2_dep_hit; + wire iu_rv_iu6_t0_i1_s3_v; + wire [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_s3_p; + wire [0:2] iu_rv_iu6_t0_i1_s3_t; + wire iu_rv_iu6_t0_i1_s3_dep_hit; + wire [0:3] iu_rv_iu6_t0_i1_ilat; + wire [0:`EFF_IFAR_WIDTH-1] iu_rv_iu6_t0_i1_bta; + wire iu_rv_iu6_t0_i1_bta_val; + wire iu_rv_iu6_t0_i1_br_pred; + wire [0:`EFF_IFAR_WIDTH-1] iu_rv_iu6_t0_i1_fusion; + wire [0:2] iu_rv_iu6_t0_i1_ls_ptr; + wire [0:17] iu_rv_iu6_t0_i1_gshare; + wire iu_rv_iu6_t0_i1_bh_update; + wire iu_rv_iu6_t0_i1_isLoad; + wire iu_rv_iu6_t0_i1_isStore; + wire [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i1_s1_itag; + wire [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i1_s2_itag; + wire [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i1_s3_itag; + +`ifndef THREADS1 + + wire iu_rv_iu6_t1_i0_vld; + wire iu_rv_iu6_t1_i0_act; + wire iu_rv_iu6_t1_i0_rte_lq; + wire iu_rv_iu6_t1_i0_rte_sq; + wire iu_rv_iu6_t1_i0_rte_fx0; + wire iu_rv_iu6_t1_i0_rte_fx1; + wire iu_rv_iu6_t1_i0_rte_axu0; + wire iu_rv_iu6_t1_i0_rte_axu1; + wire [0:31] iu_rv_iu6_t1_i0_instr; + wire [0:`EFF_IFAR_WIDTH-1] iu_rv_iu6_t1_i0_ifar; + wire [0:2] iu_rv_iu6_t1_i0_ucode; + wire iu_rv_iu6_t1_i0_2ucode; + wire [0:`UCODE_ENTRIES_ENC-1] iu_rv_iu6_t1_i0_ucode_cnt; + wire [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i0_itag; + wire iu_rv_iu6_t1_i0_ord; + wire iu_rv_iu6_t1_i0_cord; + wire iu_rv_iu6_t1_i0_spec; + wire iu_rv_iu6_t1_i0_t1_v; + wire [0:2] iu_rv_iu6_t1_i0_t1_t; + wire [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_t1_p; + wire iu_rv_iu6_t1_i0_t2_v; + wire [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_t2_p; + wire [0:2] iu_rv_iu6_t1_i0_t2_t; + wire iu_rv_iu6_t1_i0_t3_v; + wire [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_t3_p; + wire [0:2] iu_rv_iu6_t1_i0_t3_t; + wire iu_rv_iu6_t1_i0_s1_v; + wire [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_s1_p; + wire [0:2] iu_rv_iu6_t1_i0_s1_t; + wire iu_rv_iu6_t1_i0_s1_dep_hit; + wire iu_rv_iu6_t1_i0_s2_v; + wire [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_s2_p; + wire [0:2] iu_rv_iu6_t1_i0_s2_t; + wire iu_rv_iu6_t1_i0_s2_dep_hit; + wire iu_rv_iu6_t1_i0_s3_v; + wire [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_s3_p; + wire [0:2] iu_rv_iu6_t1_i0_s3_t; + wire iu_rv_iu6_t1_i0_s3_dep_hit; + wire [0:3] iu_rv_iu6_t1_i0_ilat; + wire [0:`EFF_IFAR_WIDTH-1] iu_rv_iu6_t1_i0_bta; + wire iu_rv_iu6_t1_i0_bta_val; + wire iu_rv_iu6_t1_i0_br_pred; + wire [0:`EFF_IFAR_WIDTH-1] iu_rv_iu6_t1_i0_fusion; + wire [0:2] iu_rv_iu6_t1_i0_ls_ptr; + wire [0:17] iu_rv_iu6_t1_i0_gshare; + wire iu_rv_iu6_t1_i0_bh_update; + wire iu_rv_iu6_t1_i0_isLoad; + wire iu_rv_iu6_t1_i0_isStore; + wire [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i0_s1_itag; + wire [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i0_s2_itag; + wire [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i0_s3_itag; + + wire iu_rv_iu6_t1_i1_vld; + wire iu_rv_iu6_t1_i1_act; + wire iu_rv_iu6_t1_i1_rte_lq; + wire iu_rv_iu6_t1_i1_rte_sq; + wire iu_rv_iu6_t1_i1_rte_fx0; + wire iu_rv_iu6_t1_i1_rte_fx1; + wire iu_rv_iu6_t1_i1_rte_axu0; + wire iu_rv_iu6_t1_i1_rte_axu1; + wire [0:31] iu_rv_iu6_t1_i1_instr; + wire [0:`EFF_IFAR_WIDTH-1] iu_rv_iu6_t1_i1_ifar; + wire [0:2] iu_rv_iu6_t1_i1_ucode; + wire [0:`UCODE_ENTRIES_ENC-1] iu_rv_iu6_t1_i1_ucode_cnt; + wire [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i1_itag; + wire iu_rv_iu6_t1_i1_ord; + wire iu_rv_iu6_t1_i1_cord; + wire iu_rv_iu6_t1_i1_spec; + wire iu_rv_iu6_t1_i1_t1_v; + wire [0:2] iu_rv_iu6_t1_i1_t1_t; + wire [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_t1_p; + wire iu_rv_iu6_t1_i1_t2_v; + wire [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_t2_p; + wire [0:2] iu_rv_iu6_t1_i1_t2_t; + wire iu_rv_iu6_t1_i1_t3_v; + wire [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_t3_p; + wire [0:2] iu_rv_iu6_t1_i1_t3_t; + wire iu_rv_iu6_t1_i1_s1_v; + wire [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_s1_p; + wire [0:2] iu_rv_iu6_t1_i1_s1_t; + wire iu_rv_iu6_t1_i1_s2_v; + wire [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_s2_p; + wire [0:2] iu_rv_iu6_t1_i1_s2_t; + wire iu_rv_iu6_t1_i1_s3_v; + wire [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_s3_p; + wire [0:2] iu_rv_iu6_t1_i1_s3_t; + wire [0:3] iu_rv_iu6_t1_i1_ilat; + wire [0:`EFF_IFAR_WIDTH-1] iu_rv_iu6_t1_i1_bta; + wire iu_rv_iu6_t1_i1_bta_val; + wire iu_rv_iu6_t1_i1_br_pred; + wire [0:`EFF_IFAR_WIDTH-1] iu_rv_iu6_t1_i1_fusion; + wire [0:2] iu_rv_iu6_t1_i1_ls_ptr; + wire [0:17] iu_rv_iu6_t1_i1_gshare; + wire iu_rv_iu6_t1_i1_bh_update; + wire iu_rv_iu6_t1_i1_isLoad; + wire iu_rv_iu6_t1_i1_isStore; + wire [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i1_s1_itag; + wire [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i1_s2_itag; + wire [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i1_s3_itag; + +`endif + + // Credit Interface with IU + wire [0:`THREADS-1] rv_iu_fx0_credit_free; + wire [0:`THREADS-1] rv_iu_fx1_credit_free; + wire [0:`THREADS-1] rv_iu_axu0_credit_free; + wire [0:`THREADS-1] rv_iu_axu1_credit_free; + + // LQ Instruction Executed + wire [0:`THREADS-1] lq0_iu_execute_vld; + wire [0:`ITAG_SIZE_ENC-1] lq0_iu_itag; + wire lq0_iu_n_flush; + wire lq0_iu_np1_flush; + wire lq0_iu_dacr_type; + wire [0:3] lq0_iu_dacrw; + wire [0:31] lq0_iu_instr; + wire [64-`GPR_WIDTH:63] lq0_iu_eff_addr; + wire lq0_iu_exception_val; + wire [0:5] lq0_iu_exception; + wire lq0_iu_flush2ucode; + wire lq0_iu_flush2ucode_type; + wire [0:`THREADS-1] lq0_iu_recirc_val; + wire [0:`THREADS-1] lq0_iu_dear_val; + wire [0:`THREADS-1] lq1_iu_execute_vld; + wire [0:`ITAG_SIZE_ENC-1] lq1_iu_itag; + wire lq1_iu_n_flush; + wire lq1_iu_np1_flush; + wire lq1_iu_exception_val; + wire [0:5] lq1_iu_exception; + wire lq1_iu_dacr_type; + wire [0:3] lq1_iu_dacrw; + wire [0:3] lq1_iu_perf_events; + wire [0:`THREADS-1] lq_iu_credit_free; + wire [0:`THREADS-1] sq_iu_credit_free; + wire pc_lq_init_reset; + + // BR Instruction Executed + wire [0:`THREADS-1] br_iu_execute_vld; + wire [0:`ITAG_SIZE_ENC-1] br_iu_itag; + wire [62-`EFF_IFAR_ARCH:61] br_iu_bta; + wire br_iu_taken; + wire [0:`THREADS-1] br_iu_redirect; + wire [0:3] br_iu_perf_events; + + //br unit repairs + wire [0:17] br_iu_gshare; + wire [0:2] br_iu_ls_ptr; + wire [62-`EFF_IFAR_WIDTH:61] br_iu_ls_data; + wire br_iu_ls_update; + + // AXU Instruction Executed + wire [0:`THREADS-1] axu0_rv_itag_vld; + wire [0:`ITAG_SIZE_ENC-1] axu0_rv_itag; + wire [0:`THREADS-1] axu1_rv_itag_vld; + wire [0:`ITAG_SIZE_ENC-1] axu1_rv_itag; + wire axu0_rv_hold_all; + wire axu1_rv_hold_all; + + + // Abort + wire lq_rv_ex2_s1_abort; + wire lq_rv_ex2_s2_abort; + wire fx0_rv_ex2_s1_abort; + wire fx0_rv_ex2_s2_abort; + wire fx0_rv_ex2_s3_abort; + wire fx1_rv_ex2_s1_abort; + wire fx1_rv_ex2_s2_abort; + wire fx1_rv_ex2_s3_abort; + wire axu0_rv_ex2_s1_abort; + wire axu0_rv_ex2_s2_abort; + wire axu0_rv_ex2_s3_abort; + wire fu_lq_ex3_abort; + + + + // XU Instruction Executed + wire [0:`THREADS-1] xu_iu_ucode_xer_val; + wire [`XER_WIDTH-7:`XER_WIDTH-1] xu_iu_ucode_xer; + wire [0:`THREADS-1] xu_iu_execute_vld; + wire [0:`ITAG_SIZE_ENC-1] xu_iu_itag; + wire xu_iu_n_flush; + wire xu_iu_np1_flush; + wire xu_iu_flush2ucode; + wire [0:3] xu0_iu_perf_events; + wire xu_iu_exception_val; + wire [0:4] xu_iu_exception; + wire [0:`THREADS-1] xu_iu_mtiar; + wire [62-`EFF_IFAR_ARCH:61] xu_iu_bta; + wire [0:`THREADS-1] xu1_iu_execute_vld; + wire [0:`ITAG_SIZE_ENC-1] xu1_iu_itag; + wire [0:`THREADS-1] xu_iu_val; + wire [0:`THREADS-1] xu_iu_pri_val; + wire [0:2] xu_iu_pri; + wire xu_iu_is_eratre; + wire xu_iu_is_eratwe; + wire xu_iu_is_eratsx; + wire xu_iu_is_eratilx; + wire xu_iu_is_erativax; + wire [0:1] xu_iu_ws; + wire [0:2] xu_iu_t; + wire [0:8] xu_iu_rs_is; // Never see this used in IERAT + wire [0:3] xu_iu_ra_entry; + wire [64-`GPR_WIDTH:51] xu_iu_rb; + wire [64-`GPR_WIDTH:63] xu_iu_rs_data; + wire xu_iu_ord_ready; + wire iu_xu_ord_read_done; + wire iu_xu_ord_write_done; + wire iu_xu_ord_n_flush_req; + wire iu_xu_ord_par_err; + wire [0:`THREADS-1] mm_xu_ord_read_done; + wire [0:`THREADS-1] mm_xu_ord_write_done; + wire [0:`THREADS-1] mm_xu_ord_n_flush_req; + wire [0:`THREADS-1] mm_xu_ord_np1_flush_req; + wire mm_xu_ord_tlb_multihit; + wire mm_xu_ord_tlb_par_err; + wire mm_xu_ord_lru_par_err; + wire mm_xu_local_snoop_reject; + wire [0:`ITAG_SIZE_ENC-1] mm_xu_itag; + wire xu_mm_ord_ready; + wire [0:`THREADS-1] mm_xu_cr0_eq; // for record forms + wire [0:`THREADS-1] mm_xu_cr0_eq_valid; // for record forms + wire [0:`THREADS-1] mm_xu_tlb_miss; + wire [0:`THREADS-1] mm_xu_lrat_miss; + wire [0:`THREADS-1] mm_xu_tlb_inelig; + wire [0:`THREADS-1] mm_xu_pt_fault; + wire [0:`THREADS-1] mm_xu_hv_priv; + wire [0:`THREADS-1] mm_xu_illeg_instr; + wire [0:1] mm_xu_t0_mmucr0_tlbsel; +`ifndef THREADS1 + wire [0:1] mm_xu_t1_mmucr0_tlbsel; +`endif + wire mm_xu_tlb_miss_ored; + wire mm_xu_lrat_miss_ored; + wire mm_xu_tlb_inelig_ored; + wire mm_xu_pt_fault_ored; + wire mm_xu_hv_priv_ored; + wire mm_xu_illeg_instr_ored; + wire mm_xu_cr0_eq_ored; // for record forms + wire mm_xu_cr0_eq_valid_ored; // for record forms + wire mm_xu_ord_n_flush_req_ored; + wire mm_xu_ord_np1_flush_req_ored; + wire mm_xu_ord_read_done_ored; + wire mm_xu_ord_write_done_ored; + wire mm_pc_tlb_multihit_err_ored; + wire mm_pc_tlb_par_err_ored; + wire mm_pc_lru_par_err_ored; + wire mm_pc_local_snoop_reject_ored; + + wire [0:`THREADS-1] mm_tlb_multihit_err; + wire [0:`THREADS-1] mm_tlb_par_err; + wire [0:`THREADS-1] mm_lru_par_err; + wire [0:`THREADS-1] mm_iu_local_snoop_reject; + wire [64-`GPR_WIDTH:63] iu_xu_ex5_data; + wire xu_lq_act; + wire [0:`THREADS-1] xu_lq_val; + wire xu_lq_is_eratre; + wire xu_lq_is_eratwe; + wire xu_lq_is_eratsx; + wire xu_lq_is_eratilx; + wire [0:1] xu_lq_ws; + wire [0:2] xu_lq_t; + wire [0:8] xu_lq_rs_is; // Never see this used in IERAT + wire [0:4] xu_lq_ra_entry; + wire [64-`GPR_WIDTH:51] xu_lq_rb; + wire [64-`GPR_WIDTH:63] xu_lq_rs_data; + wire xu_lq_ord_ready; + wire xu_lq_hold_req; + wire lq_xu_ord_read_done; + wire lq_xu_ord_write_done; + wire lq_xu_ord_n_flush_req; + wire lq_xu_ord_par_err; + wire [64-`GPR_WIDTH:63] lq_xu_ex5_data; + wire lq_xu_dbell_val; + wire [0:4] lq_xu_dbell_type; + wire lq_xu_dbell_brdcast; + wire lq_xu_dbell_lpid_match; + wire [50:63] lq_xu_dbell_pirtag; + wire xu_mm_is_tlbre; + wire xu_mm_is_tlbwe; + wire xu_mm_is_tlbsx; + wire xu_mm_is_tlbsxr; + wire xu_mm_is_tlbsrx; + wire xu_mm_is_tlbivax; + wire xu_mm_is_tlbilx; + wire [0:11] xu_mm_ra_entry; + wire [64-`GPR_WIDTH:63] xu_mm_rb; + wire lq_xu_spr_xucr0_cslc_xuop; + wire lq_xu_spr_xucr0_cslc_binv; + wire lq_xu_spr_xucr0_clo; + wire lq_xu_spr_xucr0_cul; + wire [0:`THREADS-1] lq_iu_spr_dbcr3_ivc; + // FU Instruction Executed + wire [0:`THREADS-1] axu0_iu_execute_vld; + wire [0:`ITAG_SIZE_ENC-1] axu0_iu_itag; + wire axu0_iu_n_flush; + wire axu0_iu_np1_flush; + wire axu0_iu_n_np1_flush; + wire axu0_iu_flush2ucode; + wire axu0_iu_flush2ucode_type; + wire axu0_iu_exception_val; + wire [0:3] axu0_iu_exception; + wire [0:`THREADS-1] axu0_iu_async_fex; + wire [0:3] axu0_iu_perf_events; + + wire [0:`THREADS-1] axu1_iu_execute_vld; + wire [0:`ITAG_SIZE_ENC-1] axu1_iu_itag; + wire axu1_iu_n_flush; + wire axu1_iu_np1_flush; + wire axu1_iu_flush2ucode; + wire axu1_iu_flush2ucode_type; + wire axu1_iu_exception_val; + wire [0:3] axu1_iu_exception; + wire [0:3] axu1_iu_perf_events; + + wire [0:`THREADS-1] cp_flush; + wire [0:`ITAG_SIZE_ENC-1] cp_t0_next_itag; + wire [0:`ITAG_SIZE_ENC-1] cp_t0_flush_itag; + wire [62-`EFF_IFAR_ARCH:61] cp_t0_flush_ifar; + wire [0:`THREADS-1] cp_axu_i0_t1_v; + wire [0:`THREADS-1] cp_axu_i1_t1_v; + + wire [0:2] cp_axu_t0_i0_t1_t; + wire [0:`GPR_WIDTH_ENC-1] cp_axu_t0_i0_t1_p; + wire [0:2] cp_axu_t0_i1_t1_t; + wire [0:`GPR_WIDTH_ENC-1] cp_axu_t0_i1_t1_p; + + wire [0:`ITAG_SIZE_ENC-1] cp_t1_next_itag; + wire [0:`ITAG_SIZE_ENC-1] cp_t1_flush_itag; + wire [62-`EFF_IFAR_ARCH:61] cp_t1_flush_ifar; + wire [0:2] cp_axu_t1_i0_t1_t; + wire [0:`GPR_WIDTH_ENC-1] cp_axu_t1_i0_t1_p; + wire [0:2] cp_axu_t1_i1_t1_t; + wire [0:`GPR_WIDTH_ENC-1] cp_axu_t1_i1_t1_p; + + wire cp_is_isync; + wire cp_is_csync; + + wire [64-`GPR_WIDTH:63+`GPR_WIDTH/8] gpr_xu0_ex1_r0d; + wire [64-`GPR_WIDTH:63+`GPR_WIDTH/8] gpr_xu0_ex1_r1d; + wire [64-`GPR_WIDTH:63+`GPR_WIDTH/8] gpr_xu0_ex1_r2d; + wire xu0_gpr_ex6_we; + wire [0:`GPR_WIDTH_ENC+`THREADS_POOL_ENC-1] xu0_gpr_ex6_wa; + wire [64-`GPR_WIDTH:63+`GPR_WIDTH/8] xu0_gpr_ex6_wd; + wire [64-`GPR_WIDTH:63+`GPR_WIDTH/8] gpr_xu1_ex1_r0d; + wire [64-`GPR_WIDTH:63+`GPR_WIDTH/8] gpr_xu1_ex1_r1d; + wire [64-`GPR_WIDTH:63+`GPR_WIDTH/8] gpr_xu1_ex1_r2d; + wire xu1_gpr_ex3_we; + wire [0:`GPR_WIDTH_ENC+`THREADS_POOL_ENC-1] xu1_gpr_ex3_wa; + wire [64-`GPR_WIDTH:63+`GPR_WIDTH/8] xu1_gpr_ex3_wd; + wire [64-`GPR_WIDTH:63+`GPR_WIDTH/8] rv_lq_gpr_ex1_r0d; + wire [64-`GPR_WIDTH:63+`GPR_WIDTH/8] rv_lq_gpr_ex1_r1d; + wire [64-`GPR_WIDTH:63+`GPR_WIDTH/8] gpr_lq_ex1_r2d; + wire lq_rv_gpr_ex6_we; + wire [0:`GPR_WIDTH_ENC+`THREADS_POOL_ENC-1] lq_rv_gpr_ex6_wa; + wire [64-`GPR_WIDTH:63+`GPR_WIDTH/8] lq_rv_gpr_ex6_wd; + wire lq_xu_gpr_ex5_we; + wire [0:`AXU_SPARE_ENC+`GPR_WIDTH_ENC+`THREADS_POOL_ENC-1] lq_xu_gpr_ex5_wa; + wire lq_rv_gpr_rel_we; + wire [0:`GPR_WIDTH_ENC+`THREADS_POOL_ENC-1] lq_rv_gpr_rel_wa; + wire [64-`GPR_WIDTH:63+`GPR_WIDTH/8] lq_rv_gpr_rel_wd; + wire lq_xu_gpr_rel_we; + wire [0:`AXU_SPARE_ENC+`GPR_WIDTH_ENC+`THREADS_POOL_ENC-1] lq_xu_gpr_rel_wa; + wire [64-`GPR_WIDTH:63+`GPR_WIDTH/8] lq_xu_gpr_rel_wd; + + wire lq_xu_cr_ex5_we; + wire [0:`CR_POOL_ENC+`THREADS_POOL_ENC-1] lq_xu_cr_ex5_wa; + wire lq_xu_cr_l2_we; + wire [0:`CR_POOL_ENC+`THREADS_POOL_ENC-1] lq_xu_cr_l2_wa; + wire [0:3] lq_xu_cr_l2_wd; + wire [0:`XER_POOL_ENC-1] iu_rf_t0_xer_p; +`ifndef THREADS1 + wire [0:`XER_POOL_ENC-1] iu_rf_t1_xer_p; +`endif + wire [0:`THREADS-1] xu_lq_xer_cp_rd; + + // Interface to FX0 + wire [0:`THREADS-1] rv_fx0_vld; + wire rv_fx0_s1_v; + wire [0:`GPR_POOL_ENC-1] rv_fx0_s1_p; + wire [0:2] rv_fx0_s1_t; + wire rv_fx0_s2_v; + wire [0:`GPR_POOL_ENC-1] rv_fx0_s2_p; + wire [0:2] rv_fx0_s2_t; + wire rv_fx0_s3_v; + wire [0:`GPR_POOL_ENC-1] rv_fx0_s3_p; + wire [0:2] rv_fx0_s3_t; + wire [0:31] rv_fx0_ex0_instr; + wire [62-`EFF_IFAR_WIDTH:61] rv_fx0_ex0_ifar; + wire [0:`ITAG_SIZE_ENC-1] rv_fx0_ex0_itag; + wire [0:2] rv_fx0_ex0_ucode; + wire [0:`UCODE_ENTRIES_ENC-1] rv_fx0_ex0_ucode_cnt; + wire rv_fx0_ex0_ord; + wire rv_fx0_ex0_t1_v; + wire [0:`GPR_POOL_ENC-1] rv_fx0_ex0_t1_p; + wire [0:2] rv_fx0_ex0_t1_t; + wire rv_fx0_ex0_t2_v; + wire [0:`GPR_POOL_ENC-1] rv_fx0_ex0_t2_p; + wire [0:2] rv_fx0_ex0_t2_t; + wire rv_fx0_ex0_t3_v; + wire [0:`GPR_POOL_ENC-1] rv_fx0_ex0_t3_p; + wire [0:2] rv_fx0_ex0_t3_t; + wire rv_fx0_ex0_s1_v; + wire rv_fx0_ex0_s2_v; + wire [0:2] rv_fx0_ex0_s2_t; + wire rv_fx0_ex0_s3_v; + wire [0:2] rv_fx0_ex0_s3_t; + wire [0:19] rv_fx0_ex0_fusion; + wire [62-`EFF_IFAR_WIDTH:61] rv_fx0_ex0_pred_bta; + wire rv_fx0_ex0_bta_val; + wire rv_fx0_ex0_br_pred; + wire [0:2] rv_fx0_ex0_ls_ptr; + wire rv_fx0_ex0_bh_update; + wire [0:17] rv_fx0_ex0_gshare; + wire [0:`THREADS-1] rv_fx0_ex0_spec_flush; + wire [0:`THREADS-1] rv_fx0_ex1_spec_flush; + wire [0:`THREADS-1] rv_fx0_ex2_spec_flush; + wire fx0_rv_hold_all; + wire [0:`ITAG_SIZE_ENC-1] fx0_rv_ord_itag; + wire fx0_rv_ord_complete; + + // Interface to FX1 + wire [0:`THREADS-1] rv_fx1_vld; + wire rv_fx1_s1_v; + wire [0:`GPR_POOL_ENC-1] rv_fx1_s1_p; + wire [0:2] rv_fx1_s1_t; + wire rv_fx1_s2_v; + wire [0:`GPR_POOL_ENC-1] rv_fx1_s2_p; + wire [0:2] rv_fx1_s2_t; + wire rv_fx1_s3_v; + wire [0:`GPR_POOL_ENC-1] rv_fx1_s3_p; + wire [0:2] rv_fx1_s3_t; + wire [0:31] rv_fx1_ex0_instr; + wire [0:`ITAG_SIZE_ENC-1] rv_fx1_ex0_itag; + wire [0:2] rv_fx1_ex0_ucode; + wire rv_fx1_ex0_t1_v; + wire [0:`GPR_POOL_ENC-1] rv_fx1_ex0_t1_p; + wire rv_fx1_ex0_t2_v; + wire [0:`GPR_POOL_ENC-1] rv_fx1_ex0_t2_p; + wire rv_fx1_ex0_t3_v; + wire [0:`GPR_POOL_ENC-1] rv_fx1_ex0_t3_p; + wire rv_fx1_ex0_s1_v; + wire [0:2] rv_fx1_ex0_s3_t; + wire rv_fx1_ex0_isStore; + + wire [0:`THREADS-1] rv_fx1_ex0_spec_flush; + wire [0:`THREADS-1] rv_fx1_ex1_spec_flush; + wire [0:`THREADS-1] rv_fx1_ex2_spec_flush; + wire fx1_rv_hold_all; + wire fx1_rv_hold_ordered; + + //------------------------------------------------------------------ + // AXU Pass Thru Interface + //------------------------------------------------------------------ + wire [59:63] lq_xu_axu_ex4_addr; + wire lq_xu_axu_ex5_we; + wire lq_xu_axu_ex5_le; + wire [59:63] xu_axu_lq_ex4_addr; + wire xu_axu_lq_ex5_we; + wire xu_axu_lq_ex5_le; + wire [0:`AXU_SPARE_ENC+`GPR_POOL_ENC+`THREADS_POOL_ENC-1] xu_axu_lq_ex5_wa; + wire [(128-`STQ_DATA_SIZE):127] xu_axu_lq_ex5_wd; + wire lq_xu_axu_rel_we; + wire lq_xu_axu_rel_le; + wire xu_axu_lq_rel_we; + wire xu_axu_lq_rel_le; + wire [0:`AXU_SPARE_ENC+`GPR_POOL_ENC+`THREADS_POOL_ENC-1] xu_axu_lq_rel_wa; + wire [(128-`STQ_DATA_SIZE):128+((`STQ_DATA_SIZE-1)/8)] xu_axu_lq_rel_wd; + wire [0:`THREADS-1] axu_xu_lq_ex_stq_val; + wire [0:`ITAG_SIZE_ENC-1] axu_xu_lq_ex_stq_itag; + wire [128-`STQ_DATA_SIZE:127] axu_xu_lq_exp1_stq_data; + wire [0:`THREADS-1] xu_lq_axu_ex_stq_val; + wire [0:`ITAG_SIZE_ENC-1] xu_lq_axu_ex_stq_itag; + wire [128-`STQ_DATA_SIZE:127] xu_lq_axu_exp1_stq_data; + wire axu_xu_lq_exp1_sto_parity_err; + + // Interface to LQ + wire [0:`THREADS-1] rv_lq_rvs_empty; + wire [0:`THREADS-1] rv_lq_vld; + wire [0:`ITAG_SIZE_ENC-1] rv_lq_ex0_itag; + wire rv_lq_isLoad; + + wire [0:`THREADS-1] rv_lq_rv1_i0_vld; + wire rv_lq_rv1_i0_ucode_preissue; + wire rv_lq_rv1_i0_2ucode; + wire [0:`UCODE_ENTRIES_ENC-1] rv_lq_rv1_i0_ucode_cnt; + wire [0:2] rv_lq_rv1_i0_s3_t; + wire rv_lq_rv1_i0_isLoad; + wire rv_lq_rv1_i0_isStore; + wire [0:`ITAG_SIZE_ENC-1] rv_lq_rv1_i0_itag; + wire rv_lq_rv1_i0_rte_lq; + wire rv_lq_rv1_i0_rte_sq; + wire [61-`PF_IAR_BITS+1:61] rv_lq_rv1_i0_ifar; + + wire [0:`THREADS-1] rv_lq_rv1_i1_vld; + wire rv_lq_rv1_i1_ucode_preissue; + wire rv_lq_rv1_i1_2ucode; + wire [0:`UCODE_ENTRIES_ENC-1] rv_lq_rv1_i1_ucode_cnt; + wire [0:2] rv_lq_rv1_i1_s3_t; + wire rv_lq_rv1_i1_isLoad; + wire rv_lq_rv1_i1_isStore; + wire [0:`ITAG_SIZE_ENC-1] rv_lq_rv1_i1_itag; + wire rv_lq_rv1_i1_rte_lq; + wire rv_lq_rv1_i1_rte_sq; + wire [61-`PF_IAR_BITS+1:61] rv_lq_rv1_i1_ifar; + wire [0:31] rv_lq_ex0_instr; + wire [0:2] rv_lq_ex0_ucode; + wire [0:`UCODE_ENTRIES_ENC-1] rv_lq_ex0_ucode_cnt; + wire rv_lq_ex0_spec; + wire rv_lq_ex0_t1_v; + wire [0:`GPR_POOL_ENC-1] rv_lq_ex0_t1_p; + wire [0:`GPR_POOL_ENC-1] rv_lq_ex0_t3_p; + wire rv_lq_ex0_s1_v; + wire rv_lq_ex0_s2_v; + wire [0:2] rv_lq_ex0_s2_t; + + wire lq_rv_hold_all; + wire [0:`THREADS-1] lq_rv_itag0_vld; + wire [0:`ITAG_SIZE_ENC-1] lq_rv_itag0; + wire [0:`THREADS-1] lq_rv_itag1_vld; + wire [0:`ITAG_SIZE_ENC-1] lq_rv_itag1; + wire [0:`THREADS-1] lq_rv_itag2_vld; + wire [0:`ITAG_SIZE_ENC-1] lq_rv_itag2; + wire lq_rv_itag0_spec; + wire lq_rv_itag0_abort; + wire lq_rv_itag1_restart; + wire lq_rv_itag1_abort; + wire lq_rv_itag1_hold; + wire lq_rv_itag1_cord; + wire [0:`THREADS-1] lq_rv_clr_hold; + wire lq_rv_ord_complete; + + wire [0:`GPR_POOL_ENC-1] rv_sq_s3_p; + + wire [0:`THREADS-1] rv_axu0_vld; + wire rv_axu0_s1_v; + wire [0:`GPR_POOL_ENC-1] rv_axu0_s1_p; + wire [0:2] rv_axu0_s1_t; + wire rv_axu0_s2_v; + wire [0:`GPR_POOL_ENC-1] rv_axu0_s2_p; + wire [0:2] rv_axu0_s2_t; + wire rv_axu0_s3_v; + wire [0:`GPR_POOL_ENC-1] rv_axu0_s3_p; + wire [0:2] rv_axu0_s3_t; + wire rv_axu0_s1_spec; + wire [0:`ITAG_SIZE_ENC-1] rv_axu0_s1_itag; + wire rv_axu0_s2_spec; + wire [0:`ITAG_SIZE_ENC-1] rv_axu0_s2_itag; + wire rv_axu0_s3_spec; + wire [0:`ITAG_SIZE_ENC-1] rv_axu0_s3_itag; + + wire [0:`ITAG_SIZE_ENC-1] rv_axu0_ex0_itag; + wire [0:31] rv_axu0_ex0_instr; + wire [0:2] rv_axu0_ex0_ucode; + wire rv_axu0_ex0_t1_v; + wire [0:`GPR_POOL_ENC-1] rv_axu0_ex0_t1_p; + wire [0:`GPR_POOL_ENC-1] rv_axu0_ex0_t2_p; + wire [0:`GPR_POOL_ENC-1] rv_axu0_ex0_t3_p; + + + wire axu0_rv_ord_complete; + + wire sq_rv_itag0_vld; + wire [0:`ITAG_SIZE_ENC-1] sq_rv_itag0; + wire [0:`THREADS-1] iu_lq_i0_completed; + wire [0:`THREADS-1] iu_lq_i1_completed; + wire [0:`ITAG_SIZE_ENC-1] iu_lq_t0_i0_completed_itag; + wire [0:`ITAG_SIZE_ENC-1] iu_lq_t0_i1_completed_itag; +`ifndef THREADS1 + wire [0:`ITAG_SIZE_ENC-1] iu_lq_t1_i0_completed_itag; + wire [0:`ITAG_SIZE_ENC-1] iu_lq_t1_i1_completed_itag; +`endif + wire [0:`THREADS-1] iu_lq_recirc_val; + wire [64-(2**`GPR_WIDTH_ENC):63] iu_lq_ls5_tlb_data; + wire [0:`THREADS-1] fu_lq_ex2_store_data_val; + wire [0:`ITAG_SIZE_ENC-1] fu_lq_ex2_store_itag; + wire [(128-`STQ_DATA_SIZE):127] fu_lq_ex3_store_data; + wire [0:`THREADS-1] mm_lq_lsu_req; + wire [0:1] mm_lq_lsu_ttype; + wire [0:4] mm_lq_lsu_wimge; + wire [0:3] mm_lq_lsu_u; + wire [64-`REAL_IFAR_WIDTH:63] mm_lq_lsu_addr; + wire [0:7] mm_lq_lsu_lpid; + wire [0:7] mm_lq_lsu_lpidr; + wire mm_lq_lsu_gs; + wire mm_lq_lsu_ind; + wire mm_lq_lsu_lbit; + wire lq_mm_lsu_token; + wire xu_lq_xucr0_aflsta; + wire xu_lq_xucr0_cred; + wire xu_lq_xucr0_rel; + wire xu_lq_xucr0_flsta; + wire xu_lq_xucr0_l2siw; + wire xu_lq_xucr0_flh2l2; + wire xu_lq_xucr0_dc_dis; + wire xu_lq_xucr0_wlk; + wire xu_lq_xucr0_clfc; + wire xu_lq_xucr0_bypErat; + wire lq_mm_derat_req; + wire [0:51] lq_mm_derat_epn; + wire [0:`THREADS-1] lq_mm_derat_thdid; + wire [0:`EMQ_ENTRIES-1] lq_mm_derat_req_emq; + wire [0:1] lq_mm_derat_ttype; + wire [0:3] lq_mm_derat_state; + wire [0:7] lq_mm_derat_lpid; + wire [0:13] lq_mm_derat_tid; + wire lq_mm_derat_req_nonspec; + wire [0:`ITAG_SIZE_ENC-1] lq_mm_derat_req_itag; + wire [0:`THREADS-1] lq_mm_perf_dtlb; + wire [0:4] mm_lq_derat_rel_val; + wire [0:131] mm_lq_derat_rel_data; + wire [0:`EMQ_ENTRIES-1] mm_lq_derat_rel_emq; + wire [0:`ITAG_SIZE_ENC-1] mm_lq_derat_rel_itag; + wire mm_lq_derat_snoop_coming; + wire mm_lq_derat_snoop_val; + wire [0:25] mm_lq_derat_snoop_attr; + wire [(62-`EFF_IFAR_ARCH):51] mm_lq_derat_snoop_vpn; + wire lq_mm_derat_snoop_ack; + wire [0:13] mm_lq_t0_derat_pid; + wire [0:19] mm_lq_t0_derat_mmucr0; +`ifndef THREADS1 + wire [0:13] mm_lq_t1_derat_pid; + wire [0:19] mm_lq_t1_derat_mmucr0; +`endif + wire [0:17] lq_mm_derat_mmucr0; + wire [0:`THREADS-1] lq_mm_derat_mmucr0_we; + wire [0:9] mm_lq_derat_mmucr1; + wire [0:4] lq_mm_derat_mmucr1; + wire [0:`THREADS-1] lq_mm_derat_mmucr1_we; + wire lq_mm_lmq_stq_empty; + // Interface to BR + // Interface to AXU + wire [59:63] lq_fu_ex4_eff_addr; + wire lq_fu_ex5_load_val; + wire lq_fu_ex5_load_le; + wire [(128-`STQ_DATA_SIZE):127] lq_fu_ex5_load_data; + + // Ram interface + wire [0:31] pc_iu_ram_instr; + wire [0:3] pc_iu_ram_instr_ext; + wire [0:`THREADS-1] pc_iu_ram_active; + wire [0:`THREADS-1] pc_iu_ram_flush_thread; + wire pc_iu_ram_issue; + wire iu_pc_ram_done; + wire iu_pc_ram_interrupt; + wire iu_pc_ram_unsupported; + wire xu_pc_ram_data_val; + wire [64-(2**`GPR_WIDTH_ENC):63] xu_pc_ram_data; + wire xu_pc_ram_exception; + wire [0:`THREADS-1] pc_xu_ram_active; + wire pc_xu_msrovride_enab; + wire [0:`THREADS-1] xu_iu_msrovride_enab; + wire pc_xu_msrovride_pr; + wire pc_xu_msrovride_gs; + wire pc_xu_msrovride_de; + wire [0:`THREADS-1] pc_lq_ram_active; + wire lq_pc_ram_data_val; + wire [64-(2**`GPR_WIDTH_ENC):63] lq_pc_ram_data; + // PC control + wire [0:`THREADS-1] pc_iu_stop; + wire [0:`THREADS-1] pc_iu_step; + wire [0:`THREADS-1] iu_pc_step_done; + wire [0:`THREADS-1] iu_pc_stop_dbg_event; + wire [0:`THREADS-1] xu_pc_stop_dnh_instr; + wire [0:2] pc_iu_t0_dbg_action; +`ifndef THREADS1 + wire [0:2] pc_iu_t1_dbg_action; +`endif + wire [0:3*`THREADS-1] pc_iu_dbg_action_int; + wire pc_xu_extirpts_dis_on_stop; + wire pc_xu_timebase_dis_on_stop; + wire pc_xu_decrem_dis_on_stop; + wire ac_an_power_managed_int; + wire [0:`THREADS-1] pc_xu_spr_dbcr0_edm; + wire [0:`THREADS-1] pc_iu_spr_dbcr0_edm; + + // MSR connections + wire [0:`THREADS-1] spr_msr_ucle; + wire [0:`THREADS-1] spr_msr_spv; + wire [0:`THREADS-1] spr_msr_fp; + wire [0:`THREADS-1] spr_msr_fe0; + wire [0:`THREADS-1] spr_msr_fe1; + wire [0:`THREADS-1] spr_msr_de; + wire [0:`THREADS-1] spr_msrp_uclep; + wire [0:`THREADS-1] spr_msr_pr; + wire [0:`THREADS-1] spr_msr_is; + wire [0:`THREADS-1] spr_msr_cm; + wire [0:`THREADS-1] spr_msr_gs; + wire [0:`THREADS-1] spr_msr_ee; + wire [0:`THREADS-1] spr_msr_ce; + wire [0:`THREADS-1] spr_msr_me; + wire [0:`THREADS-1] spr_msr_ds; + wire [0:`THREADS-1] spr_dbcr0_idm; + wire [0:`THREADS-1] spr_dbcr0_icmp; + wire [0:`THREADS-1] spr_dbcr0_brt; + wire [0:`THREADS-1] spr_dbcr0_irpt; + wire [0:`THREADS-1] spr_dbcr0_trap; + wire [0:`THREADS-1] xu_iu_iac1_en; + wire [0:`THREADS-1] xu_iu_iac2_en; + wire [0:`THREADS-1] xu_iu_iac3_en; + wire [0:`THREADS-1] xu_iu_iac4_en; + wire [0:`THREADS*2-1] spr_dbcr0_dac1; + wire [0:`THREADS*2-1] spr_dbcr0_dac2; + wire [0:`THREADS*2-1] spr_dbcr0_dac3; + wire [0:`THREADS*2-1] spr_dbcr0_dac4; + wire [0:`THREADS-1] spr_dbcr0_ret; + wire [0:`THREADS-1] spr_dbcr1_iac12m; + wire [0:`THREADS-1] spr_dbcr1_iac34m; + wire spr_ccr2_en_dcr; + wire spr_ccr2_en_trace; + wire spr_ccr2_en_pc; + wire [0:8] spr_ccr2_ifratsc; + wire spr_ccr2_ifrat; + wire [0:8] spr_ccr2_dfratsc; + wire spr_ccr2_dfrat; + wire spr_ccr2_ucode_dis; + wire [0:3] spr_ccr2_ap; + wire spr_ccr2_en_attn; + wire spr_ccr2_en_ditc; + wire spr_ccr2_en_icswx; + wire spr_ccr2_notlb; + wire spr_xucr0_clfc; + wire spr_xucr0_cls; + wire spr_xucr0_mbar_ack; + wire spr_xucr0_tlbsync; + wire spr_xucr0_aflsta; + wire spr_xucr0_mddp; + wire spr_xucr0_cred; + wire spr_xucr0_rel; + wire spr_xucr0_mdcp; + wire spr_xucr0_flsta; + wire spr_xucr0_l2siw; + wire spr_xucr0_flh2l2; + wire spr_xucr0_dc_dis; + wire spr_xucr0_wlk; + wire [0:3] spr_xucr0_trace_um; + wire spr_cpcr2_lsu_inorder; + + wire [0:`THREADS-1] xu_iu_epcr_extgs; + wire [0:`THREADS-1] xu_iu_epcr_dtlbgs; + wire [0:`THREADS-1] xu_iu_epcr_itlbgs; + wire [0:`THREADS-1] xu_iu_epcr_dsigs; + wire [0:`THREADS-1] xu_iu_epcr_isigs; + wire [0:`THREADS-1] xu_iu_epcr_duvd; + wire [0:`THREADS-1] spr_epcr_dgtmi; + wire [0:`THREADS-1] xu_iu_epcr_icm; + wire [0:`THREADS-1] xu_iu_epcr_gicm; + wire [0:`THREADS-1] xu_mm_spr_epcr_dmiuh; + wire iu_lq_spr_iucr0_icbi_ack; + + //------------------------------------------------------------------- + // Interface from bypass to units + //------------------------------------------------------------------- + // Interface with FXU0 + //------------------------------------------------------------------- + wire [1:11] rv_fx0_ex0_s1_fx0_sel; + wire [1:11] rv_fx0_ex0_s2_fx0_sel; + wire [1:11] rv_fx0_ex0_s3_fx0_sel; + wire [4:8] rv_fx0_ex0_s1_lq_sel; + wire [4:8] rv_fx0_ex0_s2_lq_sel; + wire [4:8] rv_fx0_ex0_s3_lq_sel; + wire [1:6] rv_fx0_ex0_s1_fx1_sel; + wire [1:6] rv_fx0_ex0_s2_fx1_sel; + wire [1:6] rv_fx0_ex0_s3_fx1_sel; + + //------------------------------------------------------------------- + // Interface with LQ + //------------------------------------------------------------------- + wire [2:12] rv_lq_ex0_s1_fx0_sel; + wire [2:12] rv_lq_ex0_s2_fx0_sel; + wire [4:8] rv_lq_ex0_s1_lq_sel; + wire [4:8] rv_lq_ex0_s2_lq_sel; + wire [2:7] rv_lq_ex0_s1_fx1_sel; + wire [2:7] rv_lq_ex0_s2_fx1_sel; + + //------------------------------------------------------------------- + // Interface with FXU1 + //------------------------------------------------------------------- + wire [1:11] rv_fx1_ex0_s1_fx0_sel; + wire [1:11] rv_fx1_ex0_s2_fx0_sel; + wire [1:11] rv_fx1_ex0_s3_fx0_sel; + wire [4:8] rv_fx1_ex0_s1_lq_sel; + wire [4:8] rv_fx1_ex0_s2_lq_sel; + wire [4:8] rv_fx1_ex0_s3_lq_sel; + wire [1:6] rv_fx1_ex0_s1_fx1_sel; + wire [1:6] rv_fx1_ex0_s2_fx1_sel; + wire [1:6] rv_fx1_ex0_s3_fx1_sel; + + wire [2:3] rv_fx0_ex0_s1_rel_sel; + wire [2:3] rv_fx0_ex0_s2_rel_sel; + wire [2:3] rv_fx0_ex0_s3_rel_sel; + wire [2:3] rv_lq_ex0_s1_rel_sel; + wire [2:3] rv_lq_ex0_s2_rel_sel; + wire [2:3] rv_fx1_ex0_s1_rel_sel; + wire [2:3] rv_fx1_ex0_s2_rel_sel; + wire [2:3] rv_fx1_ex0_s3_rel_sel; + + + + wire [0:3] lq_xu_ex5_cr; + wire [64-`GPR_WIDTH:63] fxu0_fxu1_ex3_rt; + wire [0:3] fxu0_fxu1_ex3_cr; + wire [0:9] fxu0_fxu1_ex3_xer; + wire [64-`GPR_WIDTH:63] fxu1_fxu0_ex3_rt; + wire [0:3] fxu1_fxu0_ex3_cr; + wire [0:9] fxu1_fxu0_ex3_xer; + wire [64-`GPR_WIDTH:63] xu0_lq_ex3_rt; + wire [64-`GPR_WIDTH:63] xu0_lq_ex4_rt; + wire xu1_lq_ex3_act; + wire [64-`GPR_WIDTH:63] xu0_lq_ex6_rt; + wire xu1_lq_ex6_act; + wire xu1_lq_ex3_abort; + wire [64-`GPR_WIDTH:63] xu1_lq_ex3_rt; + wire xu0_lq_ex3_act; + wire xu0_lq_ex3_abort; + wire xu1_lq_ex3_illeg_lswx; + wire xu1_lq_ex3_strg_noop; + wire [0:`THREADS-1] xu1_lq_ex2_stq_val; + wire [0:`ITAG_SIZE_ENC-1] xu1_lq_ex2_stq_itag; + wire [1:4] xu1_lq_ex2_stq_size; + wire [(64-`GPR_WIDTH)/8:7] xu1_lq_ex2_stq_dvc1_cmp; + wire [(64-`GPR_WIDTH)/8:7] xu1_lq_ex2_stq_dvc2_cmp; + + wire lq_xu_ex5_act; + wire [64-`GPR_WIDTH:63] lq_xu_ex5_rt; + wire lq_xu_ex5_abort; + wire xu_axu_lq_ex5_abort; + + // REMOVE THESE AS REAL CONNECTIONS COME IN + wire [0:`CR_POOL_ENC-1] cr_r3a; + wire [0:3] cr_r3d; + wire axu0_cr_w4e; + wire [0:`CR_POOL_ENC+`THREADS_POOL_ENC-1] axu0_cr_w4a; + wire [0:3] axu0_cr_w4d; + wire [0:`XER_POOL_ENC-1] xer_r1a; + wire [0:9] xer_r1d; + wire [0:`XER_POOL_ENC-1] xer_r2a; + wire [0:9] xer_r2d; + wire [0:`XER_POOL_ENC-1] xer_r3a; + wire [0:9] xer_r3d; + wire [0:`XER_POOL_ENC-1] xer_r4a; + wire [0:9] xer_r4d; + wire [0:`XER_POOL_ENC-1] xer_r5a; + wire [0:9] xer_r5d; + wire [0:`XER_POOL_ENC-1] xer_r6a; + wire [0:9] xer_r6d; + + // Scan connections + wire scan_in_ic; + wire scan_out_ic; + wire scan_in_rv; + wire scan_out_rv; + wire [0:3] scan_in_xu; + wire [0:3] scan_out_xu; + wire [0:24] scan_in_lq; + wire [0:24] scan_out_lq; + wire scan_in_rf_gpr; + wire scan_out_rf_gpr; + wire scan_in_rf_ctr; + wire scan_out_rf_ctr; + wire scan_in_rf_lr; + wire scan_out_rf_lr; + wire scan_in_rf_cr; + wire scan_out_rf_cr; + wire scan_in_rf_xer; + wire scan_out_rf_xer; + wire scan_in_br; + wire scan_out_br; + wire scan_in_rv_byp; + wire scan_out_rv_byp; + + // Need to think about where these go + wire [0:`THREADS-1] iu_xu_icache_quiesce; + wire [0:`THREADS-1] iu_pc_icache_quiesce; + wire iu_mm_lmq_empty; + wire force_xhdl0; + wire [0:`THREADS-1] iu_xu_stop; + wire [0:`THREADS-1] xu_iu_run_thread; + wire [0:`THREADS-1] xu_iu_single_instr_mode; + wire [0:`THREADS-1] xu_iu_raise_iss_pri; + wire [0:`THREADS-1] xu_iu_np1_async_flush; + wire [0:`THREADS-1] iu_xu_async_complete; + wire iu_xu_credits_returned; + wire [0:`THREADS-1] iu_xu_quiesce; + wire [0:`THREADS-1] iu_pc_quiesce; + wire [0:`THREADS-1] iu_xu_act; + wire [0:`THREADS-1] iu_xu_rfi; + wire [0:`THREADS-1] iu_xu_rfgi; + wire [0:`THREADS-1] iu_xu_rfci; + wire [0:`THREADS-1] iu_xu_rfmci; + wire [0:`THREADS-1] iu_xu_int; + wire [0:`THREADS-1] iu_xu_gint; + wire [0:`THREADS-1] iu_xu_cint; + wire [0:`THREADS-1] iu_xu_mcint; + wire [62-`EFF_IFAR_ARCH:61] iu_xu_t0_nia; + wire [0:16] iu_xu_t0_esr; + wire [0:14] iu_xu_t0_mcsr; + wire [0:18] iu_xu_t0_dbsr; + wire [64-`GPR_WIDTH:63] iu_xu_t0_dear; +`ifndef THREADS1 + wire [62-`EFF_IFAR_ARCH:61] iu_xu_t1_nia; + wire [0:16] iu_xu_t1_esr; + wire [0:14] iu_xu_t1_mcsr; + wire [0:18] iu_xu_t1_dbsr; + wire [64-`GPR_WIDTH:63] iu_xu_t1_dear; +`endif + wire [0:`THREADS-1] iu_xu_dear_update; + wire [0:`THREADS-1] iu_xu_dbsr_update; + wire [0:`THREADS-1] iu_xu_dbsr_ude; + wire [0:`THREADS-1] iu_xu_dbsr_ide; + wire [0:`THREADS-1] iu_xu_esr_update; + wire [0:`THREADS-1] iu_xu_dbell_taken; + wire [0:`THREADS-1] iu_xu_cdbell_taken; + wire [0:`THREADS-1] iu_xu_gdbell_taken; + wire [0:`THREADS-1] iu_xu_gcdbell_taken; + wire [0:`THREADS-1] iu_xu_gmcdbell_taken; + wire [0:`THREADS-1] xu_iu_dbsr_ide; + wire [0:`THREADS-1] iu_xu_instr_cpl; + + wire [0:`THREADS-1] xu_iu_external_mchk; + wire [0:`THREADS-1] xu_iu_ext_interrupt; + wire [0:`THREADS-1] xu_iu_dec_interrupt; + wire [0:`THREADS-1] xu_iu_udec_interrupt; + wire [0:`THREADS-1] xu_iu_perf_interrupt; + wire [0:`THREADS-1] xu_iu_fit_interrupt; + wire [0:`THREADS-1] xu_iu_crit_interrupt; + wire [0:`THREADS-1] xu_iu_wdog_interrupt; + wire [0:`THREADS-1] xu_iu_gwdog_interrupt; + wire [0:`THREADS-1] xu_iu_gfit_interrupt; + wire [0:`THREADS-1] xu_iu_gdec_interrupt; + wire [0:`THREADS-1] xu_iu_dbell_interrupt; + wire [0:`THREADS-1] xu_iu_cdbell_interrupt; + wire [0:`THREADS-1] xu_iu_gdbell_interrupt; + wire [0:`THREADS-1] xu_iu_gcdbell_interrupt; + wire [0:`THREADS-1] xu_iu_gmcdbell_interrupt; + wire [62-`EFF_IFAR_ARCH:61] xu_iu_t0_rest_ifar; +`ifndef THREADS1 + wire [62-`EFF_IFAR_ARCH:61] xu_iu_t1_rest_ifar; +`endif + wire [0:`THREADS-1] lq_xu_quiesce; + wire [0:`THREADS-1] mm_xu_quiesce; + wire [0:`THREADS-1] mm_pc_tlb_req_quiesce; + wire [0:`THREADS-1] mm_pc_tlb_ctl_quiesce; + wire [0:`THREADS-1] mm_pc_htw_quiesce; + wire [0:`THREADS-1] mm_pc_inval_quiesce; + wire [0:`THREADS-1] xu_pc_running; + wire [0:`THREADS-1] lq_pc_ldq_quiesce; + wire [0:`THREADS-1] lq_pc_stq_quiesce; + wire [0:`THREADS-1] lq_pc_pfetch_quiesce; + + // PCQ Signals + wire rp_pc_scom_dch_q; + wire rp_pc_scom_cch_q; + wire pc_rp_scom_dch; + wire pc_rp_scom_cch; + // pcq error related and FIRs + wire [0:`THREADS-1] pc_rp_special_attn; + wire [0:2] pc_rp_checkstop; + wire [0:2] pc_rp_local_checkstop; + wire [0:2] pc_rp_recov_err; + wire pc_rp_trace_error; + wire pc_rp_livelock_active; + wire rp_pc_checkstop_q; + wire lq_pc_err_dcache_parity; + wire lq_pc_err_dcachedir_ldp_parity; + wire lq_pc_err_dcachedir_stp_parity; + wire lq_pc_err_dcachedir_ldp_multihit; + wire lq_pc_err_dcachedir_stp_multihit; + wire lq_pc_err_prefetcher_parity; + wire iu_pc_err_btb_parity; + wire lq_pc_err_relq_parity; + wire [0:`THREADS-1] xu_pc_err_sprg_ecc; + wire [0:`THREADS-1] xu_pc_err_sprg_ue; + wire [0:`THREADS-1] xu_pc_err_regfile_parity; + wire [0:`THREADS-1] xu_pc_err_regfile_ue; + wire [0:`THREADS-1] lq_pc_err_regfile_parity; + wire [0:`THREADS-1] lq_pc_err_regfile_ue; + wire lq_pc_err_l2intrf_ecc; + wire lq_pc_err_l2intrf_ue; + wire lq_pc_err_l2credit_overrun; + wire lq_pc_err_invld_reld; + wire [0:`THREADS-1] xu_pc_err_llbust_attempt; + wire [0:`THREADS-1] xu_pc_err_llbust_failed; + wire [0:`THREADS-1] xu_pc_err_wdt_reset; + wire [0:`THREADS-1] iu_pc_err_cpArray_parity; + wire [0:`THREADS-1] iu_pc_err_debug_event; + wire [0:`THREADS-1] iu_pc_err_ucode_illegal; + wire [0:`THREADS-1] iu_pc_err_mchk_disabled; + wire lq_pc_err_derat_parity; + wire lq_pc_err_derat_multihit; + wire [0:`THREADS-1] iu_pc_err_attention_instr; + wire pc_iu_inj_icachedir_multihit; + wire pc_lq_inj_dcache_parity; + wire pc_lq_inj_dcachedir_ldp_parity; + wire pc_lq_inj_dcachedir_stp_parity; + wire pc_lq_inj_dcachedir_ldp_multihit; + wire pc_lq_inj_dcachedir_stp_multihit; + wire pc_lq_inj_prefetcher_parity; + wire pc_lq_inj_relq_parity; + wire [0:`THREADS-1] pc_lq_inj_regfile_parity; + wire [0:`THREADS-1] pc_xu_inj_sprg_ecc; + wire [0:`THREADS-1] pc_fx0_inj_regfile_parity; + wire [0:`THREADS-1] pc_fx1_inj_regfile_parity; + wire [0:`THREADS-1] pc_xu_inj_llbust_attempt; + wire [0:`THREADS-1] pc_xu_inj_llbust_failed; + wire [0:`THREADS-1] pc_iu_inj_cpArray_parity; + // pcq power management + resets + wire [0:`THREADS-1] rp_pc_pm_thread_stop_q; + wire [0:`THREADS-1] rp_pc_pm_fetch_halt_q; + wire [0:1] xu_pc_spr_ccr0_pme; + wire [0:`THREADS-1] pc_iu_pm_fetch_halt; + wire [0:`THREADS-1] xu_pc_spr_ccr0_we; + wire [0:`THREADS-1] pc_rp_pm_thread_running; + wire pc_rp_power_managed; + wire pc_rp_rvwinkle_mode; + wire pc_xu_pm_hold_thread; + // pcq debug + perf events + wire rp_pc_debug_stop_q; + wire pc_iu_trace_bus_enable; + wire pc_rv_trace_bus_enable; + wire pc_mm_trace_bus_enable; + wire pc_xu_trace_bus_enable; + wire pc_lq_trace_bus_enable; + wire [0:`THREADS-1] xu_pc_perfmon_alert; + wire [0:`THREADS-1] pc_xu_spr_cesr1_pmae; + wire [0:10] pc_iu_debug_mux1_ctrls; + wire [0:10] pc_iu_debug_mux2_ctrls; + wire [0:10] pc_rv_debug_mux_ctrls; + wire [0:10] pc_mm_debug_mux_ctrls; + wire [0:10] pc_xu_debug_mux_ctrls; + wire [0:10] pc_lq_debug_mux1_ctrls; + wire [0:10] pc_lq_debug_mux2_ctrls; + wire pc_xu_cache_par_err_event; + wire pc_iu_event_bus_enable; + wire pc_rv_event_bus_enable; + wire pc_rp_event_bus_enable; + wire pc_mm_event_bus_enable; + wire pc_xu_event_bus_enable; + wire pc_lq_event_bus_enable; + wire [0:2] pc_iu_event_count_mode; + wire [0:2] pc_rv_event_count_mode; + wire [0:2] pc_mm_event_count_mode; + wire [0:2] pc_xu_event_count_mode; + wire [0:2] pc_lq_event_count_mode; + + wire [0:39] pc_rv_event_mux_ctrls; + wire [0:7] rv_rp_event_bus; + + wire pc_iu_instr_trace_mode; + wire [0:1] pc_iu_instr_trace_tid; + wire pc_lq_instr_trace_mode; + wire [0:`THREADS-1] pc_lq_instr_trace_tid; + wire pc_xu_instr_trace_mode; + wire [0:1] pc_xu_instr_trace_tid; + wire pc_lq_event_bus_seldbghi; + wire pc_lq_event_bus_seldbglo; + // pcq clock + scan controls + wire rp_pc_rtim_sl_thold_7; + wire rp_pc_func_sl_thold_7; + wire rp_pc_func_nsl_thold_7; + wire rp_pc_ary_nsl_thold_7; + wire rp_pc_sg_7; + wire rp_pc_fce_7; + wire pc_rp_ccflush_out_dc; + wire pc_rp_gptr_sl_thold_4; + wire pc_rp_time_sl_thold_4; + wire pc_rp_repr_sl_thold_4; + wire pc_rp_abst_sl_thold_4; + wire pc_rp_abst_slp_sl_thold_4; + wire pc_rp_regf_sl_thold_4; + wire pc_rp_regf_slp_sl_thold_4; + wire pc_rp_func_sl_thold_4; + wire pc_rp_func_slp_sl_thold_4; + wire pc_rp_cfg_sl_thold_4; + wire pc_rp_cfg_slp_sl_thold_4; + wire pc_rp_func_nsl_thold_4; + wire pc_rp_func_slp_nsl_thold_4; + wire pc_rp_ary_nsl_thold_4; + wire pc_rp_ary_slp_nsl_thold_4; + wire pc_rp_rtim_sl_thold_4; + wire pc_rp_sg_4; + wire pc_rp_fce_4; + wire rp_iu_ccflush_dc; + wire rp_iu_gptr_sl_thold_3; + wire rp_iu_time_sl_thold_3; + wire rp_iu_repr_sl_thold_3; + wire rp_iu_abst_sl_thold_3; + wire rp_iu_abst_slp_sl_thold_3; + wire rp_iu_regf_slp_sl_thold_3; + wire rp_iu_func_sl_thold_3; + wire rp_iu_func_slp_sl_thold_3; + wire rp_iu_cfg_sl_thold_3; + wire rp_iu_cfg_slp_sl_thold_3; + wire rp_iu_func_nsl_thold_3; + wire rp_iu_func_slp_nsl_thold_3; + wire rp_iu_ary_nsl_thold_3; + wire rp_iu_ary_slp_nsl_thold_3; + wire rp_iu_sg_3; + wire rp_iu_fce_3; + wire rp_rv_ccflush_dc; + wire rp_rv_gptr_sl_thold_3; + wire rp_rv_time_sl_thold_3; + wire rp_rv_repr_sl_thold_3; + wire rp_rv_abst_sl_thold_3; + wire rp_rv_abst_slp_sl_thold_3; + wire rp_rv_func_sl_thold_3; + wire rp_rv_func_slp_sl_thold_3; + wire rp_rv_cfg_sl_thold_3; + wire rp_rv_cfg_slp_sl_thold_3; + wire rp_rv_func_nsl_thold_3; + wire rp_rv_func_slp_nsl_thold_3; + wire rp_rv_ary_nsl_thold_3; + wire rp_rv_ary_slp_nsl_thold_3; + wire rp_rv_sg_3; + wire rp_rv_fce_3; + wire rp_xu_ccflush_dc; + wire rp_xu_gptr_sl_thold_3; + wire rp_xu_time_sl_thold_3; + wire rp_xu_repr_sl_thold_3; + wire rp_xu_abst_sl_thold_3; + wire rp_xu_abst_slp_sl_thold_3; + wire rp_xu_regf_slp_sl_thold_3; + wire rp_xu_func_sl_thold_3; + wire rp_xu_func_slp_sl_thold_3; + wire rp_xu_cfg_sl_thold_3; + wire rp_xu_cfg_slp_sl_thold_3; + wire rp_xu_func_nsl_thold_3; + wire rp_xu_func_slp_nsl_thold_3; + wire rp_xu_ary_nsl_thold_3; + wire rp_xu_ary_slp_nsl_thold_3; + wire rp_xu_sg_3; + wire rp_xu_fce_3; + wire [0:4] TEMP_rp_xu_func_sl_thold_3; + wire [0:4] TEMP_rp_xu_func_slp_sl_thold_3; + wire [0:4] TEMP_rp_xu_sg_3; + wire [0:1] TEMP_rp_xu_fce_3; + wire rp_lq_ccflush_dc; + wire rp_lq_gptr_sl_thold_3; + wire rp_lq_time_sl_thold_3; + wire rp_lq_repr_sl_thold_3; + wire rp_lq_abst_sl_thold_3; + wire rp_lq_abst_slp_sl_thold_3; + wire rp_lq_regf_slp_sl_thold_3; + wire rp_lq_func_sl_thold_3; + wire rp_lq_func_slp_sl_thold_3; + wire rp_lq_cfg_sl_thold_3; + wire rp_lq_cfg_slp_sl_thold_3; + wire rp_lq_func_nsl_thold_3; + wire rp_lq_func_slp_nsl_thold_3; + wire rp_lq_ary_nsl_thold_3; + wire rp_lq_ary_slp_nsl_thold_3; + wire rp_lq_sg_3; + wire rp_lq_fce_3; + wire rp_mm_ccflush_dc; + wire rp_mm_gptr_sl_thold_3; + wire rp_mm_time_sl_thold_3; + wire rp_mm_repr_sl_thold_3; + wire rp_mm_abst_sl_thold_3; + wire rp_mm_abst_slp_sl_thold_3; + wire rp_mm_func_sl_thold_3; + wire rp_mm_func_slp_sl_thold_3; + wire rp_mm_cfg_sl_thold_3; + wire rp_mm_cfg_slp_sl_thold_3; + wire rp_mm_func_nsl_thold_3; + wire rp_mm_func_slp_nsl_thold_3; + wire rp_mm_ary_nsl_thold_3; + wire rp_mm_ary_slp_nsl_thold_3; + wire rp_mm_sg_3; + wire rp_mm_fce_3; + wire [0:1] TEMP_rp_mm_func_sl_thold_3; + wire [0:1] TEMP_rp_mm_func_slp_sl_thold_3; + wire [0:1] TEMP_rp_mm_sg_3; + wire [8:15] spr_pvr_version_dc; + wire [12:15] spr_pvr_revision_dc; + wire [16:19] spr_pvr_revision_minor_dc; + wire spr_xucr4_mmu_mchk; + wire spr_xucr4_mddmh; + // Unit Trace bus signals + wire [0:31] fu_debug_bus_in; + wire [0:31] fu_debug_bus_out; + wire [0:3] fu_coretrace_ctrls_in; + wire [0:3] fu_coretrace_ctrls_out; + wire [0:31] mm_debug_bus_in; + wire [0:31] mm_debug_bus_out; + wire [0:3] mm_coretrace_ctrls_in; + wire [0:3] mm_coretrace_ctrls_out; + wire [0:31] xu_debug_bus_in; + wire [0:31] xu_debug_bus_out; + wire [0:3] xu_coretrace_ctrls_in; + wire [0:3] xu_coretrace_ctrls_out; + wire [0:31] lq_debug_bus_in; + wire [0:31] lq_debug_bus_out; + wire [0:3] lq_coretrace_ctrls_in; + wire [0:3] lq_coretrace_ctrls_out; + wire [0:31] rv_debug_bus_in; + wire [0:31] rv_debug_bus_out; + wire [0:3] rv_coretrace_ctrls_in; + wire [0:3] rv_coretrace_ctrls_out; + wire [0:31] iu_debug_bus_in; + wire [0:31] iu_debug_bus_out; + wire [0:3] iu_coretrace_ctrls_in; + wire [0:3] iu_coretrace_ctrls_out; + wire [0:31] pc_debug_bus_in; + wire [0:31] pc_debug_bus_out; + wire [0:3] pc_coretrace_ctrls_in; + wire [0:3] pc_coretrace_ctrls_out; + // Unit Event bus signals + wire [0:4*`THREADS-1] fu_event_bus_in; + wire [0:4*`THREADS-1] fu_event_bus_out; + wire [0:4*`THREADS-1] mm_event_bus_in; + wire [0:4*`THREADS-1] mm_event_bus_out; + wire [0:4*`THREADS-1] xu_event_bus_in; + wire [0:4*`THREADS-1] xu_event_bus_out; + wire [0:4*`THREADS-1] lq_event_bus_in; + wire [0:4*`THREADS-1] lq_event_bus_out; + wire [0:4*`THREADS-1] rv_event_bus_in; + wire [0:4*`THREADS-1] rv_event_bus_out; + wire [0:4*`THREADS-1] iu_event_bus_in; + wire [0:4*`THREADS-1] iu_event_bus0_out; + wire [0:4*`THREADS-1] iu_event_bus1_out; + + + wire [0:`THREADS-1] iu_pc_fx0_credit_ok; + wire [0:`THREADS-1] iu_pc_fx1_credit_ok; + wire [0:`THREADS-1] iu_pc_axu0_credit_ok; + wire [0:`THREADS-1] iu_pc_axu1_credit_ok; + wire [0:`THREADS-1] iu_pc_lq_credit_ok; + wire [0:`THREADS-1] iu_pc_sq_credit_ok; + + + + wire [0:`THREADS-1] xu_mm_val; + wire [0:`ITAG_SIZE_ENC-1] xu_mm_itag; + + wire [0:`THREADS-1] bx_xu_quiesce; // inbox and outbox are empty + + wire func_sl_thold_0_b; + wire func_slp_sl_thold_0_b; + wire xu0_lq_ex6_act; + wire axu0_rv_itag_abort; + wire axu1_rv_itag_abort; + + wire [0:63] tidn; + wire [0:63] tiup; + + // Temporary because of 2D arrays + wire [62-`EFF_IFAR_ARCH : 61-`EFF_IFAR_WIDTH] iu_br_t0_flush_ifar; +`ifndef THREADS1 + wire [62-`EFF_IFAR_ARCH : 61-`EFF_IFAR_WIDTH] iu_br_t1_flush_ifar; +`endif + + assign tidn = {64{1'b0}}; + assign tiup = {64{1'b1}}; + assign spr_pvr_version_dc = 8'h4c; + assign spr_pvr_revision_dc = 4'h1; + assign spr_pvr_revision_minor_dc = 4'h0; + + assign ac_an_power_managed = ac_an_power_managed_int; + + // XU-IU interface + assign xu_iu_hid_mmu_mode = 1'b1; + + assign force_xhdl0 = 1'b0; + + + // TEMP TEMP TEMP TEMP TEMP TEMP TEMP TEMP TEMP + assign lq_rv_itag0_spec = 1'b0; + // TEMP TEMP TEMP TEMP TEMP TEMP TEMP TEMP TEMP + + + // LQ + assign bx_xu_quiesce = {`THREADS{1'b1}}; + assign iu_lq_ls5_tlb_data = {(63-(64 - (2 ** `GPR_WIDTH_ENC))+1){1'b0}}; + assign lq_xu_ord_n_flush_req = 1'b0; + + // PC + assign TEMP_rp_mm_func_sl_thold_3 = {2{rp_mm_func_sl_thold_3}}; + assign TEMP_rp_mm_func_slp_sl_thold_3 = {2{rp_mm_func_slp_sl_thold_3}}; + assign TEMP_rp_mm_sg_3 = {2{rp_mm_sg_3}}; + + // Slow SPR ring connections + assign lq_slowspr_val_in = xu_slowspr_val_out; + assign lq_slowspr_rw_in = xu_slowspr_rw_out; + assign lq_slowspr_etid_in = xu_slowspr_etid_out; + assign lq_slowspr_addr_in = xu_slowspr_addr_out; + assign lq_slowspr_data_in = xu_slowspr_data_out; + assign lq_slowspr_done_in = 1'b0; + assign iu_slowspr_val_in = lq_slowspr_val_out; + assign iu_slowspr_rw_in = lq_slowspr_rw_out; + assign iu_slowspr_etid_in = lq_slowspr_etid_out; + assign iu_slowspr_addr_in = lq_slowspr_addr_out; + assign iu_slowspr_data_in = lq_slowspr_data_out; + assign iu_slowspr_done_in = lq_slowspr_done_out; + assign mm_slowspr_val_in = iu_slowspr_val_out; + assign mm_slowspr_rw_in = iu_slowspr_rw_out; + assign mm_slowspr_etid_in = iu_slowspr_etid_out; + assign mm_slowspr_addr_in = iu_slowspr_addr_out; + assign mm_slowspr_data_in = iu_slowspr_data_out; + assign mm_slowspr_done_in = iu_slowspr_done_out; + assign pc_slowspr_val_in = mm_slowspr_val_out; + assign pc_slowspr_rw_in = mm_slowspr_rw_out; + assign pc_slowspr_etid_in = mm_slowspr_etid_out; + assign pc_slowspr_addr_in = mm_slowspr_addr_out; + assign pc_slowspr_data_in = mm_slowspr_data_out; + assign pc_slowspr_done_in = mm_slowspr_done_out; + assign fu_slowspr_val_in = pc_slowspr_val_out; + assign fu_slowspr_rw_in = pc_slowspr_rw_out; + assign fu_slowspr_etid_in = pc_slowspr_etid_out; + assign fu_slowspr_addr_in = pc_slowspr_addr_out; + assign fu_slowspr_data_in = pc_slowspr_data_out; + assign fu_slowspr_done_in = pc_slowspr_done_out; + assign xu_slowspr_val_in = fu_slowspr_val_out; + assign xu_slowspr_rw_in = fu_slowspr_rw_out; + assign xu_slowspr_etid_in = fu_slowspr_etid_out; + assign xu_slowspr_addr_in = fu_slowspr_addr_out; + assign xu_slowspr_data_in = fu_slowspr_data_out; + assign xu_slowspr_done_in = fu_slowspr_done_out; + + // Trace bus connections + assign mm_debug_bus_in = {32{1'b0}}; + assign fu_debug_bus_in = mm_debug_bus_out; + assign pc_debug_bus_in = fu_debug_bus_out; + assign rv_debug_bus_in = pc_debug_bus_out; + assign iu_debug_bus_in = rv_debug_bus_out; + assign xu_debug_bus_in = iu_debug_bus_out; + assign lq_debug_bus_in = xu_debug_bus_out; + assign ac_an_debug_bus = lq_debug_bus_out; + + assign mm_coretrace_ctrls_in = { 4{1'b0}}; + assign fu_coretrace_ctrls_in = mm_coretrace_ctrls_out; + assign pc_coretrace_ctrls_in = fu_coretrace_ctrls_out; + assign rv_coretrace_ctrls_in = pc_coretrace_ctrls_out; + assign iu_coretrace_ctrls_in = rv_coretrace_ctrls_out; + assign xu_coretrace_ctrls_in = iu_coretrace_ctrls_out; + assign lq_coretrace_ctrls_in = xu_coretrace_ctrls_out; + assign ac_an_coretrace_first_valid = lq_coretrace_ctrls_out[0]; + assign ac_an_coretrace_valid = lq_coretrace_ctrls_out[1]; + assign ac_an_coretrace_type = lq_coretrace_ctrls_out[2:3]; + + // Performance Event bus connections + assign mm_event_bus_in = {4*`THREADS{1'b0}}; + assign fu_event_bus_in = mm_event_bus_out; + assign rv_event_bus_in = fu_event_bus_out; + assign xu_event_bus_in = rv_event_bus_out; + assign lq_event_bus_in = xu_event_bus_out; + assign iu_event_bus_in = lq_event_bus_out; + assign ac_an_event_bus0 = iu_event_bus0_out; + assign ac_an_event_bus1 = iu_event_bus1_out; + + // TEMP TEMP TEMP TEMP TEMP TEMP TEMP TEMP TEMP + assign iu_event_bus1_out = {4*`THREADS{1'b0}}; + // TEMP TEMP TEMP TEMP TEMP TEMP TEMP TEMP TEMP + + + // PC errors + assign xu_pc_err_regfile_parity = {`THREADS{1'b0}}; + assign xu_pc_err_regfile_ue = {`THREADS{1'b0}}; + assign lq_pc_err_regfile_parity = {`THREADS{1'b0}}; + assign lq_pc_err_regfile_ue = {`THREADS{1'b0}}; + assign iu_pc_err_cpArray_parity = 1'b0; + + + + // Ties + assign fx1_rv_hold_all = 1'b0; + + assign mm_xu_local_snoop_reject = |mm_iu_local_snoop_reject; + + assign pc_iu_t0_dbg_action = pc_iu_dbg_action_int[0:2]; + assign mm_xu_t0_mmucr0_tlbsel = mm_lq_t0_derat_mmucr0[4:5]; + assign iu_br_t0_flush_ifar = cp_t0_flush_ifar[62 - `EFF_IFAR_ARCH:61 - `EFF_IFAR_WIDTH]; +`ifndef THREADS1 + assign pc_iu_t1_dbg_action = pc_iu_dbg_action_int[3:5]; + assign mm_xu_t1_mmucr0_tlbsel = mm_lq_t1_derat_mmucr0[4:5]; + assign iu_br_t1_flush_ifar = cp_t1_flush_ifar[62 - `EFF_IFAR_ARCH:61 - `EFF_IFAR_WIDTH]; +`endif + + iuq + iuq0( + //.vcs(vcs), + //.vdd(vdd), + //.gnd(gnd), + .nclk(nclk), + .pc_iu_sg_3(rp_iu_sg_3), + .pc_iu_fce_3(rp_iu_fce_3), + .pc_iu_func_slp_sl_thold_3(rp_iu_func_slp_sl_thold_3), + .pc_iu_func_nsl_thold_3(rp_iu_func_nsl_thold_3), + .pc_iu_cfg_slp_sl_thold_3(rp_iu_cfg_slp_sl_thold_3), + .pc_iu_regf_slp_sl_thold_3(rp_iu_regf_slp_sl_thold_3), + .pc_iu_func_sl_thold_3(rp_iu_func_sl_thold_3), + .pc_iu_time_sl_thold_3(rp_iu_time_sl_thold_3), + .pc_iu_abst_sl_thold_3(rp_iu_abst_sl_thold_3), + .pc_iu_abst_slp_sl_thold_3(rp_iu_abst_slp_sl_thold_3), + .pc_iu_repr_sl_thold_3(rp_iu_repr_sl_thold_3), + .pc_iu_ary_nsl_thold_3(rp_iu_ary_nsl_thold_3), + .pc_iu_ary_slp_nsl_thold_3(rp_iu_ary_slp_nsl_thold_3), + .pc_iu_func_slp_nsl_thold_3(rp_iu_func_slp_nsl_thold_3), + .pc_iu_bolt_sl_thold_3(1'b0), + .clkoff_b(1'b1), + .act_dis(1'b0), + .tc_ac_ccflush_dc(rp_iu_ccflush_dc), + .tc_ac_scan_dis_dc_b(an_ac_scan_dis_dc_b), + .tc_ac_scan_diag_dc(an_ac_scan_diag_dc), + .d_mode(1'b0), + .delay_lclkr(1'b0), + .mpw1_b(1'b0), + .mpw2_b(1'b0), + .scan_in(scan_in_ic), + .scan_out(scan_out_ic), + + .pc_iu_abist_dcomp_g6t_2r({4{1'b0}}), + .pc_iu_abist_di_0({4{1'b0}}), + .pc_iu_abist_di_g6t_2r({4{1'b0}}), + .pc_iu_abist_ena_dc(1'b0), + .pc_iu_abist_g6t_bw(2'b0), + .pc_iu_abist_g6t_r_wb(1'b0), + .pc_iu_abist_g8t1p_renb_0(1'b0), + .pc_iu_abist_g8t_bw_0(1'b0), + .pc_iu_abist_g8t_bw_1(1'b0), + .pc_iu_abist_g8t_dcomp({4{1'b0}}), + .pc_iu_abist_g8t_wenb(1'b0), + .pc_iu_abist_raddr_0({9{1'b0}}), + .pc_iu_abist_raw_dc_b(1'b0), + .pc_iu_abist_waddr_0({7{1'b0}}), + .pc_iu_abist_wl128_comp_ena(1'b0), + .pc_iu_abist_wl512_comp_ena(1'b0), + .an_ac_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc), + .an_ac_lbist_en_dc(an_ac_lbist_en_dc), + .an_ac_atpg_en_dc(1'b0), + .an_ac_grffence_en_dc(1'b0), + + .pc_iu_bo_enable_3(1'b0), + .pc_iu_bo_reset(1'b0), + .pc_iu_bo_unload(1'b0), + .pc_iu_bo_repair(1'b0), + .pc_iu_bo_shdata(1'b0), + .pc_iu_bo_select({5{1'b0}}), + .iu_pc_bo_fail(), + .iu_pc_bo_diagout(), + + .iu_pc_err_ucode_illegal(iu_pc_err_ucode_illegal), + + // Cache inject + .iu_pc_err_icache_parity(iu_pc_err_icache_parity), + .iu_pc_err_icachedir_parity(iu_pc_err_icachedir_parity), + .iu_pc_err_icachedir_multihit(iu_pc_err_icachedir_multihit), + .iu_pc_err_ierat_multihit(iu_pc_err_ierat_multihit), + .iu_pc_err_ierat_parity(iu_pc_err_ierat_parity), + .pc_iu_inj_icache_parity(pc_iu_inj_icache_parity), + .pc_iu_inj_icachedir_parity(pc_iu_inj_icachedir_parity), + .pc_iu_inj_icachedir_multihit(pc_iu_inj_icachedir_multihit), + .pc_iu_init_reset(pc_iu_init_reset), + + // spr ring + .iu_slowspr_val_in(iu_slowspr_val_in), + .iu_slowspr_rw_in(iu_slowspr_rw_in), + .iu_slowspr_etid_in(iu_slowspr_etid_in), + .iu_slowspr_addr_in(iu_slowspr_addr_in), + .iu_slowspr_data_in(iu_slowspr_data_in), + .iu_slowspr_done_in(iu_slowspr_done_in), + .iu_slowspr_val_out(iu_slowspr_val_out), + .iu_slowspr_rw_out(iu_slowspr_rw_out), + .iu_slowspr_etid_out(iu_slowspr_etid_out), + .iu_slowspr_addr_out(iu_slowspr_addr_out), + .iu_slowspr_data_out(iu_slowspr_data_out), + .iu_slowspr_done_out(iu_slowspr_done_out), + + .xu_iu_msr_ucle(spr_msr_ucle), + .xu_iu_msr_de(spr_msr_de), + .xu_iu_msr_pr(spr_msr_pr), + .xu_iu_msr_is(spr_msr_is), + .xu_iu_msr_cm(spr_msr_cm), + .xu_iu_msr_gs(spr_msr_gs), + .xu_iu_msr_me(spr_msr_me), + .xu_iu_dbcr0_edm(pc_iu_spr_dbcr0_edm), + .xu_iu_dbcr0_idm(spr_dbcr0_idm), + .xu_iu_dbcr0_icmp(spr_dbcr0_icmp), + .xu_iu_dbcr0_brt(spr_dbcr0_brt), + .xu_iu_dbcr0_irpt(spr_dbcr0_irpt), + .xu_iu_dbcr0_trap(spr_dbcr0_trap), + .xu_iu_iac1_en(xu_iu_iac1_en), + .xu_iu_iac2_en(xu_iu_iac2_en), + .xu_iu_iac3_en(xu_iu_iac3_en), + .xu_iu_iac4_en(xu_iu_iac4_en), + .xu_iu_t0_dbcr0_dac1(spr_dbcr0_dac1[0:1]), + .xu_iu_t0_dbcr0_dac2(spr_dbcr0_dac2[0:1]), + .xu_iu_t0_dbcr0_dac3(spr_dbcr0_dac3[0:1]), + .xu_iu_t0_dbcr0_dac4(spr_dbcr0_dac4[0:1]), +`ifndef THREADS1 + .xu_iu_t1_dbcr0_dac1(spr_dbcr0_dac1[2:3]), + .xu_iu_t1_dbcr0_dac2(spr_dbcr0_dac2[2:3]), + .xu_iu_t1_dbcr0_dac3(spr_dbcr0_dac3[2:3]), + .xu_iu_t1_dbcr0_dac4(spr_dbcr0_dac4[2:3]), +`endif + .xu_iu_dbcr0_ret(spr_dbcr0_ret), + .xu_iu_dbcr1_iac12m(spr_dbcr1_iac12m), + .xu_iu_dbcr1_iac34m(spr_dbcr1_iac34m), + .lq_iu_spr_dbcr3_ivc(lq_iu_spr_dbcr3_ivc), + .xu_iu_epcr_extgs(xu_iu_epcr_extgs), + .xu_iu_epcr_dtlbgs(xu_iu_epcr_dtlbgs), + .xu_iu_epcr_itlbgs(xu_iu_epcr_itlbgs), + .xu_iu_epcr_dsigs(xu_iu_epcr_dsigs), + .xu_iu_epcr_isigs(xu_iu_epcr_isigs), + .xu_iu_epcr_duvd(xu_iu_epcr_duvd), + .xu_iu_epcr_dgtmi(spr_epcr_dgtmi), + .xu_iu_epcr_icm(xu_iu_epcr_icm), + .xu_iu_epcr_gicm(xu_iu_epcr_gicm), + .xu_iu_msrp_uclep(spr_msrp_uclep), + .xu_iu_hid_mmu_mode(spr_ccr2_notlb), + .xu_iu_spr_ccr2_en_dcr(spr_ccr2_en_dcr), + .xu_iu_spr_ccr2_ifrat(spr_ccr2_ifrat), + .xu_iu_spr_ccr2_ifratsc(spr_ccr2_ifratsc), + .xu_iu_spr_ccr2_ucode_dis(spr_ccr2_ucode_dis), + .xu_iu_xucr4_mmu_mchk(spr_xucr4_mmu_mchk), + + .iu_mm_ierat_req(iu_mm_ierat_req), + .iu_mm_ierat_req_nonspec(iu_mm_ierat_req_nonspec), + .iu_mm_ierat_epn(iu_mm_ierat_epn), + .iu_mm_ierat_thdid(iu_mm_ierat_thdid), + .iu_mm_perf_itlb(iu_mm_perf_itlb), + .iu_mm_ierat_state(iu_mm_ierat_state), + .iu_mm_ierat_tid(iu_mm_ierat_tid), + .iu_mm_ierat_flush(iu_mm_ierat_flush), + + .mm_iu_ierat_rel_val(mm_iu_ierat_rel_val), + .mm_iu_ierat_rel_data(mm_iu_ierat_rel_data), + .mm_iu_ierat_pt_fault(mm_xu_pt_fault), + .mm_iu_ierat_lrat_miss(mm_xu_lrat_miss), + .mm_iu_ierat_tlb_inelig(mm_xu_tlb_inelig), + .mm_iu_tlb_multihit_err(mm_tlb_multihit_err), + .mm_iu_tlb_par_err(mm_tlb_par_err), + .mm_iu_lru_par_err(mm_lru_par_err), + .mm_iu_tlb_miss(mm_xu_tlb_miss), + + .mm_iu_t0_ierat_pid(mm_iu_t0_ierat_pid), + .mm_iu_t0_ierat_mmucr0(mm_iu_t0_ierat_mmucr0), +`ifndef THREADS1 + .mm_iu_t1_ierat_pid(mm_iu_t1_ierat_pid), + .mm_iu_t1_ierat_mmucr0(mm_iu_t1_ierat_mmucr0), +`endif + .iu_mm_ierat_mmucr0(iu_mm_ierat_mmucr0), + .iu_mm_ierat_mmucr0_we(iu_mm_ierat_mmucr0_we), + .mm_iu_ierat_mmucr1(mm_iu_ierat_mmucr1), + .iu_mm_ierat_mmucr1(iu_mm_ierat_mmucr1), + .iu_mm_ierat_mmucr1_we(iu_mm_ierat_mmucr1_we), + + .mm_iu_ierat_snoop_coming(mm_iu_ierat_snoop_coming), + .mm_iu_ierat_snoop_val(mm_iu_ierat_snoop_val), + .mm_iu_ierat_snoop_attr(mm_iu_ierat_snoop_attr), + .mm_iu_ierat_snoop_vpn(mm_iu_ierat_snoop_vpn), + .iu_mm_ierat_snoop_ack(iu_mm_ierat_snoop_ack), + + .mm_iu_flush_req(mm_iu_flush_req), + .iu_mm_bus_snoop_hold_ack(iu_mm_bus_snoop_hold_ack), + .mm_iu_bus_snoop_hold_req(mm_iu_bus_snoop_hold_req), + .mm_iu_bus_snoop_hold_done(mm_iu_bus_snoop_hold_done), + .mm_iu_tlbi_complete(mm_iu_tlbi_complete), + .iu_mm_hold_ack(iu_mm_hold_ack), + .mm_iu_hold_req(mm_iu_hold_req), + .mm_iu_hold_done(mm_iu_hold_done), + .mm_iu_tlbwe_binv(mm_iu_tlbwe_binv), + .cp_mm_except_taken_t0(cp_mm_except_taken_t0), + `ifndef THREADS1 + .cp_mm_except_taken_t1(cp_mm_except_taken_t1), + `endif + + .an_ac_back_inv(an_ac_back_inv), + .an_ac_back_inv_addr(an_ac_back_inv_addr[64 - `REAL_IFAR_WIDTH:57]), + .an_ac_back_inv_target(an_ac_back_inv_target[0]), + + .iu_lq_request(iu_lq_request), + .iu_lq_ctag(iu_lq_cTag), + .iu_lq_ra(iu_lq_ra), + .iu_lq_wimge(iu_lq_wimge), + .iu_lq_userdef(iu_lq_userdef), + + .an_ac_reld_data_vld(an_ac_reld_data_vld), + .an_ac_reld_core_tag(an_ac_reld_core_tag), + .an_ac_reld_qw(an_ac_reld_qw), + .an_ac_reld_data(an_ac_reld_data), + .an_ac_reld_ecc_err(an_ac_reld_ecc_err), + .an_ac_reld_ecc_err_ue(an_ac_reld_ecc_err_ue), + + .iu_mm_lmq_empty(iu_mm_lmq_empty), + .iu_xu_icache_quiesce(iu_xu_icache_quiesce), + .iu_pc_icache_quiesce(iu_pc_icache_quiesce), + .iu_pc_err_btb_parity(iu_pc_err_btb_parity), + + + // Interface to reservation stations + .iu_rv_iu6_t0_i0_vld(iu_rv_iu6_t0_i0_vld), + .iu_rv_iu6_t0_i0_act(iu_rv_iu6_t0_i0_act), + .iu_rv_iu6_t0_i0_rte_lq(iu_rv_iu6_t0_i0_rte_lq), + .iu_rv_iu6_t0_i0_rte_sq(iu_rv_iu6_t0_i0_rte_sq), + .iu_rv_iu6_t0_i0_rte_fx0(iu_rv_iu6_t0_i0_rte_fx0), + .iu_rv_iu6_t0_i0_rte_fx1(iu_rv_iu6_t0_i0_rte_fx1), + .iu_rv_iu6_t0_i0_rte_axu0(iu_rv_iu6_t0_i0_rte_axu0), + .iu_rv_iu6_t0_i0_rte_axu1(iu_rv_iu6_t0_i0_rte_axu1), + .iu_rv_iu6_t0_i0_instr(iu_rv_iu6_t0_i0_instr), + .iu_rv_iu6_t0_i0_ifar(iu_rv_iu6_t0_i0_ifar), + .iu_rv_iu6_t0_i0_ucode(iu_rv_iu6_t0_i0_ucode), + .iu_rv_iu6_t0_i0_2ucode(iu_rv_iu6_t0_i0_2ucode), + .iu_rv_iu6_t0_i0_ucode_cnt(iu_rv_iu6_t0_i0_ucode_cnt), + .iu_rv_iu6_t0_i0_itag(iu_rv_iu6_t0_i0_itag), + .iu_rv_iu6_t0_i0_ord(iu_rv_iu6_t0_i0_ord), + .iu_rv_iu6_t0_i0_cord(iu_rv_iu6_t0_i0_cord), + .iu_rv_iu6_t0_i0_spec(iu_rv_iu6_t0_i0_spec), + .iu_rv_iu6_t0_i0_t1_v(iu_rv_iu6_t0_i0_t1_v), + .iu_rv_iu6_t0_i0_t1_p(iu_rv_iu6_t0_i0_t1_p), + .iu_rv_iu6_t0_i0_t1_t(iu_rv_iu6_t0_i0_t1_t), + .iu_rv_iu6_t0_i0_t2_v(iu_rv_iu6_t0_i0_t2_v), + .iu_rv_iu6_t0_i0_t2_p(iu_rv_iu6_t0_i0_t2_p), + .iu_rv_iu6_t0_i0_t2_t(iu_rv_iu6_t0_i0_t2_t), + .iu_rv_iu6_t0_i0_t3_v(iu_rv_iu6_t0_i0_t3_v), + .iu_rv_iu6_t0_i0_t3_p(iu_rv_iu6_t0_i0_t3_p), + .iu_rv_iu6_t0_i0_t3_t(iu_rv_iu6_t0_i0_t3_t), + .iu_rv_iu6_t0_i0_s1_v(iu_rv_iu6_t0_i0_s1_v), + .iu_rv_iu6_t0_i0_s1_p(iu_rv_iu6_t0_i0_s1_p), + .iu_rv_iu6_t0_i0_s1_t(iu_rv_iu6_t0_i0_s1_t), + .iu_rv_iu6_t0_i0_s2_v(iu_rv_iu6_t0_i0_s2_v), + .iu_rv_iu6_t0_i0_s2_p(iu_rv_iu6_t0_i0_s2_p), + .iu_rv_iu6_t0_i0_s2_t(iu_rv_iu6_t0_i0_s2_t), + .iu_rv_iu6_t0_i0_s3_v(iu_rv_iu6_t0_i0_s3_v), + .iu_rv_iu6_t0_i0_s3_p(iu_rv_iu6_t0_i0_s3_p), + .iu_rv_iu6_t0_i0_s3_t(iu_rv_iu6_t0_i0_s3_t), + .iu_rv_iu6_t0_i0_ilat(iu_rv_iu6_t0_i0_ilat), + .iu_rv_iu6_t0_i0_isload(iu_rv_iu6_t0_i0_isLoad), + .iu_rv_iu6_t0_i0_isstore(iu_rv_iu6_t0_i0_isStore), + .iu_rv_iu6_t0_i0_s1_itag(iu_rv_iu6_t0_i0_s1_itag), + .iu_rv_iu6_t0_i0_s2_itag(iu_rv_iu6_t0_i0_s2_itag), + .iu_rv_iu6_t0_i0_s3_itag(iu_rv_iu6_t0_i0_s3_itag), + .iu_rv_iu6_t0_i0_fusion(iu_rv_iu6_t0_i0_fusion), + .iu_rv_iu6_t0_i0_bta_val(iu_rv_iu6_t0_i0_bta_val), + .iu_rv_iu6_t0_i0_bta(iu_rv_iu6_t0_i0_bta), + .iu_rv_iu6_t0_i0_br_pred(iu_rv_iu6_t0_i0_br_pred), + .iu_rv_iu6_t0_i0_ls_ptr(iu_rv_iu6_t0_i0_ls_ptr), + .iu_rv_iu6_t0_i0_bh_update(iu_rv_iu6_t0_i0_bh_update), + .iu_rv_iu6_t0_i0_gshare(iu_rv_iu6_t0_i0_gshare), + + .iu_rv_iu6_t0_i1_vld(iu_rv_iu6_t0_i1_vld), + .iu_rv_iu6_t0_i1_act(iu_rv_iu6_t0_i1_act), + .iu_rv_iu6_t0_i1_rte_lq(iu_rv_iu6_t0_i1_rte_lq), + .iu_rv_iu6_t0_i1_rte_sq(iu_rv_iu6_t0_i1_rte_sq), + .iu_rv_iu6_t0_i1_rte_fx0(iu_rv_iu6_t0_i1_rte_fx0), + .iu_rv_iu6_t0_i1_rte_fx1(iu_rv_iu6_t0_i1_rte_fx1), + .iu_rv_iu6_t0_i1_rte_axu0(iu_rv_iu6_t0_i1_rte_axu0), + .iu_rv_iu6_t0_i1_rte_axu1(iu_rv_iu6_t0_i1_rte_axu1), + .iu_rv_iu6_t0_i1_instr(iu_rv_iu6_t0_i1_instr), + .iu_rv_iu6_t0_i1_ifar(iu_rv_iu6_t0_i1_ifar), + .iu_rv_iu6_t0_i1_ucode(iu_rv_iu6_t0_i1_ucode), + .iu_rv_iu6_t0_i1_ucode_cnt(iu_rv_iu6_t0_i1_ucode_cnt), + .iu_rv_iu6_t0_i1_itag(iu_rv_iu6_t0_i1_itag), + .iu_rv_iu6_t0_i1_ord(iu_rv_iu6_t0_i1_ord), + .iu_rv_iu6_t0_i1_cord(iu_rv_iu6_t0_i1_cord), + .iu_rv_iu6_t0_i1_spec(iu_rv_iu6_t0_i1_spec), + .iu_rv_iu6_t0_i1_t1_v(iu_rv_iu6_t0_i1_t1_v), + .iu_rv_iu6_t0_i1_t1_p(iu_rv_iu6_t0_i1_t1_p), + .iu_rv_iu6_t0_i1_t1_t(iu_rv_iu6_t0_i1_t1_t), + .iu_rv_iu6_t0_i1_t2_v(iu_rv_iu6_t0_i1_t2_v), + .iu_rv_iu6_t0_i1_t2_p(iu_rv_iu6_t0_i1_t2_p), + .iu_rv_iu6_t0_i1_t2_t(iu_rv_iu6_t0_i1_t2_t), + .iu_rv_iu6_t0_i1_t3_v(iu_rv_iu6_t0_i1_t3_v), + .iu_rv_iu6_t0_i1_t3_p(iu_rv_iu6_t0_i1_t3_p), + .iu_rv_iu6_t0_i1_t3_t(iu_rv_iu6_t0_i1_t3_t), + .iu_rv_iu6_t0_i1_s1_v(iu_rv_iu6_t0_i1_s1_v), + .iu_rv_iu6_t0_i1_s1_p(iu_rv_iu6_t0_i1_s1_p), + .iu_rv_iu6_t0_i1_s1_t(iu_rv_iu6_t0_i1_s1_t), + .iu_rv_iu6_t0_i1_s1_dep_hit(iu_rv_iu6_t0_i1_s1_dep_hit), + .iu_rv_iu6_t0_i1_s2_v(iu_rv_iu6_t0_i1_s2_v), + .iu_rv_iu6_t0_i1_s2_p(iu_rv_iu6_t0_i1_s2_p), + .iu_rv_iu6_t0_i1_s2_t(iu_rv_iu6_t0_i1_s2_t), + .iu_rv_iu6_t0_i1_s2_dep_hit(iu_rv_iu6_t0_i1_s2_dep_hit), + .iu_rv_iu6_t0_i1_s3_v(iu_rv_iu6_t0_i1_s3_v), + .iu_rv_iu6_t0_i1_s3_p(iu_rv_iu6_t0_i1_s3_p), + .iu_rv_iu6_t0_i1_s3_t(iu_rv_iu6_t0_i1_s3_t), + .iu_rv_iu6_t0_i1_s3_dep_hit(iu_rv_iu6_t0_i1_s3_dep_hit), + .iu_rv_iu6_t0_i1_ilat(iu_rv_iu6_t0_i1_ilat), + .iu_rv_iu6_t0_i1_isload(iu_rv_iu6_t0_i1_isLoad), + .iu_rv_iu6_t0_i1_isstore(iu_rv_iu6_t0_i1_isStore), + .iu_rv_iu6_t0_i1_s1_itag(iu_rv_iu6_t0_i1_s1_itag), + .iu_rv_iu6_t0_i1_s2_itag(iu_rv_iu6_t0_i1_s2_itag), + .iu_rv_iu6_t0_i1_s3_itag(iu_rv_iu6_t0_i1_s3_itag), + .iu_rv_iu6_t0_i1_fusion(iu_rv_iu6_t0_i1_fusion), + .iu_rv_iu6_t0_i1_bta_val(iu_rv_iu6_t0_i1_bta_val), + .iu_rv_iu6_t0_i1_bta(iu_rv_iu6_t0_i1_bta), + .iu_rv_iu6_t0_i1_br_pred(iu_rv_iu6_t0_i1_br_pred), + .iu_rv_iu6_t0_i1_ls_ptr(iu_rv_iu6_t0_i1_ls_ptr), + .iu_rv_iu6_t0_i1_bh_update(iu_rv_iu6_t0_i1_bh_update), + .iu_rv_iu6_t0_i1_gshare(iu_rv_iu6_t0_i1_gshare), +`ifndef THREADS1 + .iu_rv_iu6_t1_i0_vld(iu_rv_iu6_t1_i0_vld), + .iu_rv_iu6_t1_i0_act(iu_rv_iu6_t1_i0_act), + .iu_rv_iu6_t1_i0_rte_lq(iu_rv_iu6_t1_i0_rte_lq), + .iu_rv_iu6_t1_i0_rte_sq(iu_rv_iu6_t1_i0_rte_sq), + .iu_rv_iu6_t1_i0_rte_fx0(iu_rv_iu6_t1_i0_rte_fx0), + .iu_rv_iu6_t1_i0_rte_fx1(iu_rv_iu6_t1_i0_rte_fx1), + .iu_rv_iu6_t1_i0_rte_axu0(iu_rv_iu6_t1_i0_rte_axu0), + .iu_rv_iu6_t1_i0_rte_axu1(iu_rv_iu6_t1_i0_rte_axu1), + .iu_rv_iu6_t1_i0_instr(iu_rv_iu6_t1_i0_instr), + .iu_rv_iu6_t1_i0_ifar(iu_rv_iu6_t1_i0_ifar), + .iu_rv_iu6_t1_i0_ucode(iu_rv_iu6_t1_i0_ucode), + .iu_rv_iu6_t1_i0_2ucode(iu_rv_iu6_t1_i0_2ucode), + .iu_rv_iu6_t1_i0_ucode_cnt(iu_rv_iu6_t1_i0_ucode_cnt), + .iu_rv_iu6_t1_i0_itag(iu_rv_iu6_t1_i0_itag), + .iu_rv_iu6_t1_i0_ord(iu_rv_iu6_t1_i0_ord), + .iu_rv_iu6_t1_i0_cord(iu_rv_iu6_t1_i0_cord), + .iu_rv_iu6_t1_i0_spec(iu_rv_iu6_t1_i0_spec), + .iu_rv_iu6_t1_i0_t1_v(iu_rv_iu6_t1_i0_t1_v), + .iu_rv_iu6_t1_i0_t1_p(iu_rv_iu6_t1_i0_t1_p), + .iu_rv_iu6_t1_i0_t1_t(iu_rv_iu6_t1_i0_t1_t), + .iu_rv_iu6_t1_i0_t2_v(iu_rv_iu6_t1_i0_t2_v), + .iu_rv_iu6_t1_i0_t2_p(iu_rv_iu6_t1_i0_t2_p), + .iu_rv_iu6_t1_i0_t2_t(iu_rv_iu6_t1_i0_t2_t), + .iu_rv_iu6_t1_i0_t3_v(iu_rv_iu6_t1_i0_t3_v), + .iu_rv_iu6_t1_i0_t3_p(iu_rv_iu6_t1_i0_t3_p), + .iu_rv_iu6_t1_i0_t3_t(iu_rv_iu6_t1_i0_t3_t), + .iu_rv_iu6_t1_i0_s1_v(iu_rv_iu6_t1_i0_s1_v), + .iu_rv_iu6_t1_i0_s1_p(iu_rv_iu6_t1_i0_s1_p), + .iu_rv_iu6_t1_i0_s1_t(iu_rv_iu6_t1_i0_s1_t), + .iu_rv_iu6_t1_i0_s2_v(iu_rv_iu6_t1_i0_s2_v), + .iu_rv_iu6_t1_i0_s2_p(iu_rv_iu6_t1_i0_s2_p), + .iu_rv_iu6_t1_i0_s2_t(iu_rv_iu6_t1_i0_s2_t), + .iu_rv_iu6_t1_i0_s3_v(iu_rv_iu6_t1_i0_s3_v), + .iu_rv_iu6_t1_i0_s3_p(iu_rv_iu6_t1_i0_s3_p), + .iu_rv_iu6_t1_i0_s3_t(iu_rv_iu6_t1_i0_s3_t), + .iu_rv_iu6_t1_i0_ilat(iu_rv_iu6_t1_i0_ilat), + .iu_rv_iu6_t1_i0_isload(iu_rv_iu6_t1_i0_isLoad), + .iu_rv_iu6_t1_i0_isstore(iu_rv_iu6_t1_i0_isStore), + .iu_rv_iu6_t1_i0_s1_itag(iu_rv_iu6_t1_i0_s1_itag), + .iu_rv_iu6_t1_i0_s2_itag(iu_rv_iu6_t1_i0_s2_itag), + .iu_rv_iu6_t1_i0_s3_itag(iu_rv_iu6_t1_i0_s3_itag), + .iu_rv_iu6_t1_i0_fusion(iu_rv_iu6_t1_i0_fusion), + .iu_rv_iu6_t1_i0_bta_val(iu_rv_iu6_t1_i0_bta_val), + .iu_rv_iu6_t1_i0_bta(iu_rv_iu6_t1_i0_bta), + .iu_rv_iu6_t1_i0_br_pred(iu_rv_iu6_t1_i0_br_pred), + .iu_rv_iu6_t1_i0_ls_ptr(iu_rv_iu6_t1_i0_ls_ptr), + .iu_rv_iu6_t1_i0_bh_update(iu_rv_iu6_t1_i0_bh_update), + .iu_rv_iu6_t1_i0_gshare(iu_rv_iu6_t1_i0_gshare), + + .iu_rv_iu6_t1_i1_vld(iu_rv_iu6_t1_i1_vld), + .iu_rv_iu6_t1_i1_act(iu_rv_iu6_t1_i1_act), + .iu_rv_iu6_t1_i1_rte_lq(iu_rv_iu6_t1_i1_rte_lq), + .iu_rv_iu6_t1_i1_rte_sq(iu_rv_iu6_t1_i1_rte_sq), + .iu_rv_iu6_t1_i1_rte_fx0(iu_rv_iu6_t1_i1_rte_fx0), + .iu_rv_iu6_t1_i1_rte_fx1(iu_rv_iu6_t1_i1_rte_fx1), + .iu_rv_iu6_t1_i1_rte_axu0(iu_rv_iu6_t1_i1_rte_axu0), + .iu_rv_iu6_t1_i1_rte_axu1(iu_rv_iu6_t1_i1_rte_axu1), + .iu_rv_iu6_t1_i1_instr(iu_rv_iu6_t1_i1_instr), + .iu_rv_iu6_t1_i1_ifar(iu_rv_iu6_t1_i1_ifar), + .iu_rv_iu6_t1_i1_ucode(iu_rv_iu6_t1_i1_ucode), + .iu_rv_iu6_t1_i1_ucode_cnt(iu_rv_iu6_t1_i1_ucode_cnt), + .iu_rv_iu6_t1_i1_itag(iu_rv_iu6_t1_i1_itag), + .iu_rv_iu6_t1_i1_ord(iu_rv_iu6_t1_i1_ord), + .iu_rv_iu6_t1_i1_cord(iu_rv_iu6_t1_i1_cord), + .iu_rv_iu6_t1_i1_spec(iu_rv_iu6_t1_i1_spec), + .iu_rv_iu6_t1_i1_t1_v(iu_rv_iu6_t1_i1_t1_v), + .iu_rv_iu6_t1_i1_t1_p(iu_rv_iu6_t1_i1_t1_p), + .iu_rv_iu6_t1_i1_t1_t(iu_rv_iu6_t1_i1_t1_t), + .iu_rv_iu6_t1_i1_t2_v(iu_rv_iu6_t1_i1_t2_v), + .iu_rv_iu6_t1_i1_t2_p(iu_rv_iu6_t1_i1_t2_p), + .iu_rv_iu6_t1_i1_t2_t(iu_rv_iu6_t1_i1_t2_t), + .iu_rv_iu6_t1_i1_t3_v(iu_rv_iu6_t1_i1_t3_v), + .iu_rv_iu6_t1_i1_t3_p(iu_rv_iu6_t1_i1_t3_p), + .iu_rv_iu6_t1_i1_t3_t(iu_rv_iu6_t1_i1_t3_t), + .iu_rv_iu6_t1_i1_s1_v(iu_rv_iu6_t1_i1_s1_v), + .iu_rv_iu6_t1_i1_s1_p(iu_rv_iu6_t1_i1_s1_p), + .iu_rv_iu6_t1_i1_s1_t(iu_rv_iu6_t1_i1_s1_t), + .iu_rv_iu6_t1_i1_s1_dep_hit(iu_rv_iu6_t1_i1_s1_dep_hit), + .iu_rv_iu6_t1_i1_s2_v(iu_rv_iu6_t1_i1_s2_v), + .iu_rv_iu6_t1_i1_s2_p(iu_rv_iu6_t1_i1_s2_p), + .iu_rv_iu6_t1_i1_s2_t(iu_rv_iu6_t1_i1_s2_t), + .iu_rv_iu6_t1_i1_s2_dep_hit(iu_rv_iu6_t1_i1_s2_dep_hit), + .iu_rv_iu6_t1_i1_s3_v(iu_rv_iu6_t1_i1_s3_v), + .iu_rv_iu6_t1_i1_s3_p(iu_rv_iu6_t1_i1_s3_p), + .iu_rv_iu6_t1_i1_s3_t(iu_rv_iu6_t1_i1_s3_t), + .iu_rv_iu6_t1_i1_s3_dep_hit(iu_rv_iu6_t1_i1_s3_dep_hit), + .iu_rv_iu6_t1_i1_ilat(iu_rv_iu6_t1_i1_ilat), + .iu_rv_iu6_t1_i1_isload(iu_rv_iu6_t1_i1_isLoad), + .iu_rv_iu6_t1_i1_isstore(iu_rv_iu6_t1_i1_isStore), + .iu_rv_iu6_t1_i1_s1_itag(iu_rv_iu6_t1_i1_s1_itag), + .iu_rv_iu6_t1_i1_s2_itag(iu_rv_iu6_t1_i1_s2_itag), + .iu_rv_iu6_t1_i1_s3_itag(iu_rv_iu6_t1_i1_s3_itag), + .iu_rv_iu6_t1_i1_fusion(iu_rv_iu6_t1_i1_fusion), + .iu_rv_iu6_t1_i1_bta_val(iu_rv_iu6_t1_i1_bta_val), + .iu_rv_iu6_t1_i1_bta(iu_rv_iu6_t1_i1_bta), + .iu_rv_iu6_t1_i1_br_pred(iu_rv_iu6_t1_i1_br_pred), + .iu_rv_iu6_t1_i1_ls_ptr(iu_rv_iu6_t1_i1_ls_ptr), + .iu_rv_iu6_t1_i1_bh_update(iu_rv_iu6_t1_i1_bh_update), + .iu_rv_iu6_t1_i1_gshare(iu_rv_iu6_t1_i1_gshare), + +`endif + + // XER read bus to RF for store conditionals + .iu_rf_t0_xer_p(iu_rf_t0_xer_p), +`ifndef THREADS1 + .iu_rf_t1_xer_p(iu_rf_t1_xer_p), +`endif + // Credit Interface with IU + .rv_iu_fx0_credit_free(rv_iu_fx0_credit_free), + .rv_iu_fx1_credit_free(rv_iu_fx1_credit_free), + .axu0_iu_credit_free(rv_iu_axu0_credit_free), + .axu1_iu_credit_free(rv_iu_axu1_credit_free), + + // LQ Instruction Executed + .lq0_iu_execute_vld(lq0_iu_execute_vld), + .lq0_iu_itag(lq0_iu_itag), + .lq0_iu_n_flush(lq0_iu_n_flush), + .lq0_iu_np1_flush(lq0_iu_np1_flush), + .lq0_iu_dacr_type(lq0_iu_dacr_type), + .lq0_iu_dacrw(lq0_iu_dacrw), + .lq0_iu_instr(lq0_iu_instr), + .lq0_iu_eff_addr(lq0_iu_eff_addr), + .lq0_iu_exception_val(lq0_iu_exception_val), + .lq0_iu_exception(lq0_iu_exception), + .lq0_iu_flush2ucode(lq0_iu_flush2ucode), + .lq0_iu_flush2ucode_type(lq0_iu_flush2ucode_type), + .lq0_iu_recirc_val(lq0_iu_recirc_val), + .lq0_iu_dear_val(lq0_iu_dear_val), + + .lq1_iu_execute_vld(lq1_iu_execute_vld), + .lq1_iu_itag(lq1_iu_itag), + .lq1_iu_n_flush(lq1_iu_n_flush), + .lq1_iu_np1_flush(lq1_iu_np1_flush), + .lq1_iu_exception_val(lq1_iu_exception_val), + .lq1_iu_exception(lq1_iu_exception), + .lq1_iu_dacr_type(lq1_iu_dacr_type), + .lq1_iu_dacrw(lq1_iu_dacrw), + .lq1_iu_perf_events(lq1_iu_perf_events), + + .lq_iu_credit_free(lq_iu_credit_free), + .sq_iu_credit_free(sq_iu_credit_free), + + // Interface IU ucode + .xu_iu_ucode_xer_val(xu_iu_ucode_xer_val), + .xu_iu_ucode_xer(xu_iu_ucode_xer), + + // Complete iTag + .iu_lq_i0_completed(iu_lq_i0_completed), + .iu_lq_i1_completed(iu_lq_i1_completed), + .iu_lq_t0_i0_completed_itag(iu_lq_t0_i0_completed_itag), + .iu_lq_t0_i1_completed_itag(iu_lq_t0_i1_completed_itag), +`ifndef THREADS1 + .iu_lq_t1_i0_completed_itag(iu_lq_t1_i0_completed_itag), + .iu_lq_t1_i1_completed_itag(iu_lq_t1_i1_completed_itag), +`endif + .iu_lq_recirc_val(iu_lq_recirc_val), + + // ICBI Interface to IU + .lq_iu_icbi_val(lq_iu_icbi_val), + .lq_iu_icbi_addr(lq_iu_icbi_addr), + .iu_lq_icbi_complete(iu_lq_icbi_complete), + .lq_iu_ici_val(lq_iu_ici_val), + .iu_lq_spr_iucr0_icbi_ack(iu_lq_spr_iucr0_icbi_ack), + + // BR Instruction Executed + .br_iu_execute_vld(br_iu_execute_vld), + .br_iu_itag(br_iu_itag), + .br_iu_bta(br_iu_bta), + .br_iu_taken(br_iu_taken), + .br_iu_redirect(br_iu_redirect), + .br_iu_perf_events(br_iu_perf_events), + + .br_iu_gshare(br_iu_gshare), + .br_iu_ls_ptr(br_iu_ls_ptr), + .br_iu_ls_data(br_iu_ls_data), + .br_iu_ls_update(br_iu_ls_update), + + // XU0 Instruction Executed + .xu_iu_execute_vld(xu_iu_execute_vld), + .xu_iu_itag(xu_iu_itag), + .xu_iu_n_flush(xu_iu_n_flush), + .xu_iu_np1_flush(xu_iu_np1_flush), + .xu_iu_flush2ucode(xu_iu_flush2ucode), + .xu_iu_exception_val(xu_iu_exception_val), + .xu_iu_exception(xu_iu_exception), + .xu_iu_mtiar(xu_iu_mtiar), + .xu_iu_bta(xu_iu_bta), + .xu_iu_perf_events(xu0_iu_perf_events), + + // XU1 Instruction Executed + .xu1_iu_execute_vld(xu1_iu_execute_vld), + .xu1_iu_itag(xu1_iu_itag), + + // XU IERAT interface + .xu_iu_val(xu_iu_val), + .xu_iu_pri_val(xu_iu_pri_val), + .xu_iu_pri(xu_iu_pri), + .xu_iu_is_eratre(xu_iu_is_eratre), + .xu_iu_is_eratwe(xu_iu_is_eratwe), + .xu_iu_is_eratsx(xu_iu_is_eratsx), + .xu_iu_is_eratilx(xu_iu_is_eratilx), + .xu_iu_ws(xu_iu_ws), + .xu_iu_ra_entry(xu_iu_ra_entry), + .xu_iu_rb(xu_iu_rb), + .xu_iu_rs_data(xu_iu_rs_data), + .iu_xu_ord_read_done(iu_xu_ord_read_done), + .iu_xu_ord_write_done(iu_xu_ord_write_done), + .iu_xu_ord_par_err(iu_xu_ord_par_err), + .iu_xu_ord_n_flush_req(iu_xu_ord_n_flush_req), + .iu_xu_ex5_data(iu_xu_ex5_data), + + // AXU0 Instruction Executed + .axu0_iu_execute_vld(axu0_iu_execute_vld), + .axu0_iu_itag(axu0_iu_itag), + .axu0_iu_n_flush(axu0_iu_n_flush), + .axu0_iu_np1_flush(axu0_iu_np1_flush), + .axu0_iu_n_np1_flush(axu0_iu_n_np1_flush), + .axu0_iu_flush2ucode(axu0_iu_flush2ucode), + .axu0_iu_flush2ucode_type(axu0_iu_flush2ucode_type), + .axu0_iu_exception_val(axu0_iu_exception_val), + .axu0_iu_exception(axu0_iu_exception), + .axu0_iu_async_fex(axu0_iu_async_fex), + .axu0_iu_perf_events(axu0_iu_perf_events), + + // AXU1 Instruction Executed + .axu1_iu_execute_vld(axu1_iu_execute_vld), + .axu1_iu_itag(axu1_iu_itag), + .axu1_iu_n_flush(axu1_iu_n_flush), + .axu1_iu_np1_flush(axu1_iu_np1_flush), + .axu1_iu_flush2ucode(axu1_iu_flush2ucode), + .axu1_iu_flush2ucode_type(axu1_iu_flush2ucode_type), + .axu1_iu_exception_val(axu1_iu_exception_val), + .axu1_iu_exception(axu1_iu_exception), + .axu1_iu_perf_events(axu1_iu_perf_events), + + // Completion and XU + // Run State + .iu_xu_stop(iu_xu_stop), + .xu_iu_run_thread(xu_iu_run_thread), + .iu_xu_credits_returned(iu_xu_credits_returned), + .xu_iu_single_instr_mode(xu_iu_single_instr_mode), + .xu_iu_raise_iss_pri(xu_iu_raise_iss_pri), + .iu_xu_quiesce(iu_xu_quiesce), + .iu_pc_quiesce(iu_pc_quiesce), + // Interrupt Interface + .iu_xu_rfi(iu_xu_rfi), + .iu_xu_rfgi(iu_xu_rfgi), + .iu_xu_rfci(iu_xu_rfci), + .iu_xu_rfmci(iu_xu_rfmci), + .iu_xu_int(iu_xu_int), + .iu_xu_gint(iu_xu_gint), + .iu_xu_cint(iu_xu_cint), + .iu_xu_mcint(iu_xu_mcint), + .iu_xu_t0_nia(iu_xu_t0_nia), + .iu_xu_t0_esr(iu_xu_t0_esr), + .iu_xu_t0_mcsr(iu_xu_t0_mcsr), + .iu_xu_t0_dbsr(iu_xu_t0_dbsr), + .iu_xu_t0_dear(iu_xu_t0_dear), +`ifndef THREADS1 + .iu_xu_t1_nia(iu_xu_t1_nia), + .iu_xu_t1_esr(iu_xu_t1_esr), + .iu_xu_t1_mcsr(iu_xu_t1_mcsr), + .iu_xu_t1_dbsr(iu_xu_t1_dbsr), + .iu_xu_t1_dear(iu_xu_t1_dear), +`endif + .iu_xu_dear_update(iu_xu_dear_update), + .iu_xu_dbsr_update(iu_xu_dbsr_update), + .iu_xu_dbsr_ude(iu_xu_dbsr_ude), + .iu_xu_dbsr_ide(iu_xu_dbsr_ide), + .iu_xu_esr_update(iu_xu_esr_update), + .iu_xu_act(iu_xu_act), + .iu_xu_dbell_taken(iu_xu_dbell_taken), + .iu_xu_cdbell_taken(iu_xu_cdbell_taken), + .iu_xu_gdbell_taken(iu_xu_gdbell_taken), + .iu_xu_gcdbell_taken(iu_xu_gcdbell_taken), + .iu_xu_gmcdbell_taken(iu_xu_gmcdbell_taken), + .iu_xu_instr_cpl(iu_xu_instr_cpl), + .xu_iu_np1_async_flush(xu_iu_np1_async_flush), + .iu_xu_async_complete(iu_xu_async_complete), + + // Interrupts + .an_ac_uncond_dbg_event(an_ac_uncond_dbg_event), + .xu_iu_external_mchk(xu_iu_external_mchk), + .xu_iu_ext_interrupt(xu_iu_ext_interrupt), + .xu_iu_dec_interrupt(xu_iu_dec_interrupt), + .xu_iu_udec_interrupt(xu_iu_udec_interrupt), + .xu_iu_perf_interrupt(xu_iu_perf_interrupt), + .xu_iu_fit_interrupt(xu_iu_fit_interrupt), + .xu_iu_crit_interrupt(xu_iu_crit_interrupt), + .xu_iu_wdog_interrupt(xu_iu_wdog_interrupt), + .xu_iu_gwdog_interrupt(xu_iu_gwdog_interrupt), + .xu_iu_gfit_interrupt(xu_iu_gfit_interrupt), + .xu_iu_gdec_interrupt(xu_iu_gdec_interrupt), + .xu_iu_dbell_interrupt(xu_iu_dbell_interrupt), + .xu_iu_cdbell_interrupt(xu_iu_cdbell_interrupt), + .xu_iu_gdbell_interrupt(xu_iu_gdbell_interrupt), + .xu_iu_gcdbell_interrupt(xu_iu_gcdbell_interrupt), + .xu_iu_gmcdbell_interrupt(xu_iu_gmcdbell_interrupt), + .xu_iu_dbsr_ide(xu_iu_dbsr_ide), + .xu_iu_t0_rest_ifar(xu_iu_t0_rest_ifar), +`ifndef THREADS1 + .xu_iu_t1_rest_ifar(xu_iu_t1_rest_ifar), +`endif + + .pc_iu_pm_fetch_halt(pc_iu_pm_fetch_halt), + //Ram interface + .pc_iu_ram_instr(pc_iu_ram_instr), + .pc_iu_ram_instr_ext(pc_iu_ram_instr_ext), + .pc_iu_ram_issue(pc_iu_ram_issue), + .iu_pc_ram_done(iu_pc_ram_done), + .iu_pc_ram_interrupt(iu_pc_ram_interrupt), + .iu_pc_ram_unsupported(iu_pc_ram_unsupported), + + .pc_iu_ram_active(pc_iu_ram_active), + .pc_iu_ram_flush_thread(pc_iu_ram_flush_thread), + .xu_iu_msrovride_enab(xu_iu_msrovride_enab), + .pc_iu_stop(pc_iu_stop), + .pc_iu_step(pc_iu_step), + .pc_iu_t0_dbg_action(pc_iu_t0_dbg_action), +`ifndef THREADS1 + .pc_iu_t1_dbg_action(pc_iu_t1_dbg_action), +`endif + .iu_pc_step_done(iu_pc_step_done), + .iu_pc_stop_dbg_event(iu_pc_stop_dbg_event), + .iu_pc_err_debug_event(iu_pc_err_debug_event), + .iu_pc_attention_instr(iu_pc_err_attention_instr), + .iu_pc_err_mchk_disabled(iu_pc_err_mchk_disabled), + .ac_an_debug_trigger(ac_an_debug_trigger), + + .cp_axu_i0_t1_v(cp_axu_i0_t1_v), + .cp_axu_i1_t1_v(cp_axu_i1_t1_v), + .cp_axu_t0_i0_t1_t(cp_axu_t0_i0_t1_t), + .cp_axu_t0_i0_t1_p(cp_axu_t0_i0_t1_p), + .cp_axu_t0_i1_t1_t(cp_axu_t0_i1_t1_t), + .cp_axu_t0_i1_t1_p(cp_axu_t0_i1_t1_p), +`ifndef THREADS1 + .cp_axu_t1_i0_t1_t(cp_axu_t1_i0_t1_t), + .cp_axu_t1_i0_t1_p(cp_axu_t1_i0_t1_p), + .cp_axu_t1_i1_t1_t(cp_axu_t1_i1_t1_t), + .cp_axu_t1_i1_t1_p(cp_axu_t1_i1_t1_p), +`endif + .cp_is_isync(cp_is_isync), + .cp_is_csync(cp_is_csync), + + // Completion flush + .cp_t0_next_itag(cp_t0_next_itag), + .cp_t0_flush_itag(cp_t0_flush_itag), + .cp_t0_flush_ifar(cp_t0_flush_ifar), +`ifndef THREADS1 + .cp_t1_next_itag(cp_t1_next_itag), + .cp_t1_flush_itag(cp_t1_flush_itag), + .cp_t1_flush_ifar(cp_t1_flush_ifar), +`endif + .cp_flush(cp_flush), + + // Performance + .pc_iu_event_bus_enable(pc_iu_event_bus_enable), + .pc_iu_event_count_mode(pc_iu_event_count_mode), + .iu_event_bus_in(iu_event_bus_in), + .iu_event_bus_out(iu_event_bus0_out), + + .iu_pc_fx0_credit_ok(iu_pc_fx0_credit_ok), + .iu_pc_fx1_credit_ok(iu_pc_fx1_credit_ok), + .iu_pc_lq_credit_ok(iu_pc_lq_credit_ok), + .iu_pc_sq_credit_ok(iu_pc_sq_credit_ok), + .iu_pc_axu0_credit_ok(iu_pc_axu0_credit_ok), + .iu_pc_axu1_credit_ok(iu_pc_axu1_credit_ok), + + + // Debug Trace + .pc_iu_trace_bus_enable(pc_iu_trace_bus_enable), + .pc_iu_debug_mux1_ctrls(pc_iu_debug_mux1_ctrls), + .pc_iu_debug_mux2_ctrls(pc_iu_debug_mux2_ctrls), + .debug_bus_in(iu_debug_bus_in), + .debug_bus_out(iu_debug_bus_out), + .coretrace_ctrls_in(iu_coretrace_ctrls_in), + .coretrace_ctrls_out(iu_coretrace_ctrls_out) + ); + + + assign func_sl_thold_0_b = (~rp_xu_func_sl_thold_3); + assign func_slp_sl_thold_0_b = (~rp_xu_func_slp_sl_thold_3); + + + + xu + xu0( + //------------------------------------------------------------------- + // Clocks & Power + //------------------------------------------------------------------- + .nclk(nclk), +// .vcs(vcs), +// .vdd(vdd), +// .gnd(gnd), + + //------------------------------------------------------------------- + // Pervasive + //------------------------------------------------------------------- + .pc_xu_ccflush_dc(rp_xu_ccflush_dc), + .clkoff_dc_b(1'b1), + .d_mode_dc(1'b0), + .delay_lclkr_dc(1'b0), + .mpw1_dc_b(1'b0), + .mpw2_dc_b(1'b0), + .func_sl_force(1'b0), + .func_sl_thold_0_b(func_sl_thold_0_b), + .func_slp_sl_thold_0_b(func_slp_sl_thold_0_b), + .sg_0(rp_xu_sg_3), + .fce_0(rp_xu_fce_3), + .scan_in(1'b0), + .scan_out(), + + .xu_pc_ram_done(xu_pc_ram_data_val), + .xu_pc_ram_data(xu_pc_ram_data), + + //------------------------------------------------------------------- + // Interface with CP + //------------------------------------------------------------------- + .cp_flush(cp_flush), + .iu_br_t0_flush_ifar(iu_br_t0_flush_ifar), + .cp_next_itag_t0(cp_t0_next_itag), +`ifndef THREADS1 + .iu_br_t1_flush_ifar(iu_br_t1_flush_ifar), + .cp_next_itag_t1(cp_t1_next_itag), +`endif + //------------------------------------------------------------------- + // BR's Interface with CP + //------------------------------------------------------------------- + .br_iu_execute_vld(br_iu_execute_vld), + .br_iu_itag(br_iu_itag), + .br_iu_taken(br_iu_taken), + .br_iu_bta(br_iu_bta), + .br_iu_gshare(br_iu_gshare), + .br_iu_ls_ptr(br_iu_ls_ptr), + .br_iu_ls_data(br_iu_ls_data), + .br_iu_ls_update(br_iu_ls_update), + .br_iu_redirect(br_iu_redirect), + .br_iu_perf_events(br_iu_perf_events), + + //------------------------------------------------------------------- + // Interface with RV + //------------------------------------------------------------------- + .rv_xu0_s1_v(rv_fx0_s1_v), + .rv_xu0_s1_p(rv_fx0_s1_p), + .rv_xu0_s2_v(rv_fx0_s2_v), + .rv_xu0_s2_p(rv_fx0_s2_p), + .rv_xu0_s3_v(rv_fx0_s3_v), + .rv_xu0_s3_p(rv_fx0_s3_p), + + .rv_xu0_vld(rv_fx0_vld), + .rv_xu0_ex0_ord(rv_fx0_ex0_ord), + .rv_xu0_ex0_fusion(rv_fx0_ex0_fusion), + .rv_xu0_ex0_instr(rv_fx0_ex0_instr), + .rv_xu0_ex0_ifar(rv_fx0_ex0_ifar), + .rv_xu0_ex0_itag(rv_fx0_ex0_itag), + .rv_xu0_ex0_ucode(rv_fx0_ex0_ucode), + .rv_xu0_ex0_bta_val(rv_fx0_ex0_bta_val), + .rv_xu0_ex0_pred_bta(rv_fx0_ex0_pred_bta), + .rv_xu0_ex0_pred(rv_fx0_ex0_br_pred), + .rv_xu0_ex0_ls_ptr(rv_fx0_ex0_ls_ptr), + .rv_xu0_ex0_bh_update(rv_fx0_ex0_bh_update), + .rv_xu0_ex0_gshare(rv_fx0_ex0_gshare), + .rv_xu0_ex0_s1_v(rv_fx0_ex0_s1_v), + .rv_xu0_ex0_s2_v(rv_fx0_ex0_s2_v), + .rv_xu0_ex0_s2_t(rv_fx0_ex0_s2_t), + .rv_xu0_ex0_s3_v(rv_fx0_ex0_s3_v), + .rv_xu0_ex0_s3_t(rv_fx0_ex0_s3_t), + .rv_xu0_ex0_t1_v(rv_fx0_ex0_t1_v), + .rv_xu0_ex0_t1_p(rv_fx0_ex0_t1_p), + .rv_xu0_ex0_t1_t(rv_fx0_ex0_t1_t), + .rv_xu0_ex0_t2_v(rv_fx0_ex0_t2_v), + .rv_xu0_ex0_t2_p(rv_fx0_ex0_t2_p), + .rv_xu0_ex0_t2_t(rv_fx0_ex0_t2_t), + .rv_xu0_ex0_t3_v(rv_fx0_ex0_t3_v), + .rv_xu0_ex0_t3_p(rv_fx0_ex0_t3_p), + .rv_xu0_ex0_t3_t(rv_fx0_ex0_t3_t), + .rv_xu0_ex0_spec_flush(rv_fx0_ex0_spec_flush), + .rv_xu0_ex1_spec_flush(rv_fx0_ex1_spec_flush), + .rv_xu0_ex2_spec_flush(rv_fx0_ex2_spec_flush), + .rv_xu0_s1_fxu0_sel(rv_fx0_ex0_s1_fx0_sel), + .rv_xu0_s2_fxu0_sel(rv_fx0_ex0_s2_fx0_sel), + .rv_xu0_s3_fxu0_sel(rv_fx0_ex0_s3_fx0_sel[2:11]), + .rv_xu0_s1_fxu1_sel(rv_fx0_ex0_s1_fx1_sel), + .rv_xu0_s2_fxu1_sel(rv_fx0_ex0_s2_fx1_sel), + .rv_xu0_s3_fxu1_sel(rv_fx0_ex0_s3_fx1_sel[2:6]), + .rv_xu0_s1_lq_sel(rv_fx0_ex0_s1_lq_sel), + .rv_xu0_s2_lq_sel(rv_fx0_ex0_s2_lq_sel), + .rv_xu0_s3_lq_sel(rv_fx0_ex0_s3_lq_sel), + .rv_xu0_s1_rel_sel(rv_fx0_ex0_s1_rel_sel), + .rv_xu0_s2_rel_sel(rv_fx0_ex0_s2_rel_sel), + .xu0_rv_ord_complete(fx0_rv_ord_complete), + .xu0_rv_ord_itag(fx0_rv_ord_itag), + .xu0_rv_hold_all(fx0_rv_hold_all), + .xu0_rv_ex2_s1_abort(fx0_rv_ex2_s1_abort), + .xu0_rv_ex2_s2_abort(fx0_rv_ex2_s2_abort), + .xu0_rv_ex2_s3_abort(fx0_rv_ex2_s3_abort), + //------------------------------------------------------------------- + // Bypass Inputs + //------------------------------------------------------------------- + .lq_xu_ex5_act(lq_xu_ex5_act), + .lq_xu_ex5_rt(lq_xu_ex5_rt), + .lq_xu_ex5_abort(lq_xu_ex5_abort), + .lq_xu_ex5_data(lq_xu_ex5_data), + .iu_xu_ex5_data(iu_xu_ex5_data), + .lq_xu_ex5_cr(lq_xu_ex5_cr), + + //------------------------------------------------------------------- + // Interface with MMU / ERATs + //------------------------------------------------------------------- + .xu_iu_ord_ready(xu_iu_ord_ready), + .xu_iu_val(xu_iu_val), + .xu_iu_is_eratre(xu_iu_is_eratre), + .xu_iu_is_eratwe(xu_iu_is_eratwe), + .xu_iu_is_eratsx(xu_iu_is_eratsx), + .xu_iu_is_eratilx(xu_iu_is_eratilx), + .xu_iu_is_erativax(xu_iu_is_erativax), + .xu_iu_ws(xu_iu_ws), + .xu_iu_t(xu_iu_t), + .xu_iu_rs_is(xu_iu_rs_is), + .xu_iu_ra_entry(xu_iu_ra_entry), + .xu_iu_rb(xu_iu_rb), + .xu_iu_rs_data(xu_iu_rs_data), + .iu_xu_ord_read_done(iu_xu_ord_read_done), + .iu_xu_ord_write_done(iu_xu_ord_write_done), + .iu_xu_ord_n_flush_req(iu_xu_ord_n_flush_req), + .iu_xu_ord_par_err(iu_xu_ord_par_err), + + .xu_lq_ord_ready(xu_lq_ord_ready), + .xu_lq_act(xu_lq_act), + .xu_lq_val(xu_lq_val), + .xu_lq_hold_req(xu_lq_hold_req), + .xu_lq_is_eratre(xu_lq_is_eratre), + .xu_lq_is_eratwe(xu_lq_is_eratwe), + .xu_lq_is_eratsx(xu_lq_is_eratsx), + .xu_lq_is_eratilx(xu_lq_is_eratilx), + .xu_lq_ws(xu_lq_ws), + .xu_lq_t(xu_lq_t), + .xu_lq_rs_is(xu_lq_rs_is), + .xu_lq_ra_entry(xu_lq_ra_entry), + .xu_lq_rb(xu_lq_rb), + .xu_lq_rs_data(xu_lq_rs_data), + .lq_xu_ord_read_done(lq_xu_ord_read_done), + .lq_xu_ord_write_done(lq_xu_ord_write_done), + .lq_xu_ord_n_flush_req(lq_xu_ord_n_flush_req), + .lq_xu_ord_par_err(lq_xu_ord_par_err), + + .xu_mm_ord_ready(xu_mm_ord_ready), + .xu_mm_val(xu_mm_val), + .xu_mm_itag(xu_mm_itag), + .xu_mm_is_tlbre(xu_mm_is_tlbre), + .xu_mm_is_tlbwe(xu_mm_is_tlbwe), + .xu_mm_is_tlbsx(xu_mm_is_tlbsx), + .xu_mm_is_tlbsxr(xu_mm_is_tlbsxr), + .xu_mm_is_tlbsrx(xu_mm_is_tlbsrx), + .xu_mm_is_tlbivax(xu_mm_is_tlbivax), + .xu_mm_is_tlbilx(xu_mm_is_tlbilx), + .xu_mm_ra_entry(xu_mm_ra_entry), + .xu_mm_rb(xu_mm_rb), + .mm_xu_itag(mm_xu_itag), + + .mm_xu_ord_n_flush_req(mm_xu_ord_n_flush_req_ored), + .mm_xu_ord_read_done(mm_xu_ord_read_done_ored), + .mm_xu_ord_write_done(mm_xu_ord_write_done_ored), + .mm_xu_tlb_miss(mm_xu_tlb_miss_ored), + .mm_xu_lrat_miss(mm_xu_lrat_miss_ored), + .mm_xu_tlb_inelig(mm_xu_tlb_inelig_ored), + .mm_xu_pt_fault(mm_xu_pt_fault_ored), + .mm_xu_hv_priv(mm_xu_hv_priv_ored), + .mm_xu_illeg_instr(mm_xu_illeg_instr_ored), + .mm_xu_tlb_multihit(mm_xu_ord_tlb_multihit), + .mm_xu_tlb_par_err(mm_xu_ord_tlb_par_err), + .mm_xu_lru_par_err(mm_xu_ord_lru_par_err), + .mm_xu_local_snoop_reject(mm_xu_local_snoop_reject), + .mm_xu_mmucr0_tlbsel_t0(mm_xu_t0_mmucr0_tlbsel), +`ifndef THREADS1 + .mm_xu_mmucr0_tlbsel_t1(mm_xu_t1_mmucr0_tlbsel), +`endif + .mm_xu_tlbwe_binv(mm_iu_tlbwe_binv), + .mm_xu_cr0_eq(mm_xu_cr0_eq_ored), // for record forms + .mm_xu_cr0_eq_valid(mm_xu_cr0_eq_valid_ored), // for record forms + + //------------------------------------------------------------------- + // Bypass Outputs + //------------------------------------------------------------------- + .xu0_lq_ex3_act(xu0_lq_ex3_act), + .xu0_lq_ex3_abort(xu0_lq_ex3_abort), + .xu0_lq_ex3_rt(xu0_lq_ex3_rt), + .xu0_lq_ex4_rt(xu0_lq_ex4_rt), + .xu0_lq_ex6_rt(xu0_lq_ex6_rt), + .xu0_lq_ex6_act(xu0_lq_ex6_act), + + //------------------------------------------------------------------- + // Interface with IU + //------------------------------------------------------------------- + .xu0_iu_execute_vld(xu_iu_execute_vld), + .xu0_iu_itag(xu_iu_itag), + .xu0_iu_mtiar(xu_iu_mtiar), + .xu0_iu_bta(xu_iu_bta), + .xu0_iu_exception_val(xu_iu_exception_val), + .xu0_iu_exception(xu_iu_exception), + .xu0_iu_n_flush(xu_iu_n_flush), + .xu0_iu_np1_flush(xu_iu_np1_flush), + .xu0_iu_flush2ucode(xu_iu_flush2ucode), + .xu0_iu_perf_events(xu0_iu_perf_events), + .xu_iu_pri_val(xu_iu_pri_val), + .xu_iu_pri(xu_iu_pri), + .xu_iu_ucode_xer_val(xu_iu_ucode_xer_val), + .xu_iu_ucode_xer(xu_iu_ucode_xer), + + // Abort + .xu1_rv_ex2_s1_abort(fx1_rv_ex2_s1_abort), + .xu1_rv_ex2_s2_abort(fx1_rv_ex2_s2_abort), + .xu1_rv_ex2_s3_abort(fx1_rv_ex2_s3_abort), + .xu1_lq_ex3_abort(xu1_lq_ex3_abort), + //------------------------------------------------------------------- + // SlowSPRs + //------------------------------------------------------------------- + .xu_slowspr_val_in(xu_slowspr_val_in), + .xu_slowspr_rw_in(xu_slowspr_rw_in), + .xu_slowspr_data_in(xu_slowspr_data_in), + .xu_slowspr_done_in(xu_slowspr_done_in), + + //------------------------------------------------------------------- + // Interface with RV + //------------------------------------------------------------------- + .rv_xu1_s1_v(rv_fx1_s1_v), + .rv_xu1_s1_p(rv_fx1_s1_p), + .rv_xu1_s2_v(rv_fx1_s2_v), + .rv_xu1_s2_p(rv_fx1_s2_p), + .rv_xu1_s3_v(rv_fx1_s3_v), + .rv_xu1_s3_p(rv_fx1_s3_p), + + .rv_xu1_vld(rv_fx1_vld), + .rv_xu1_ex0_instr(rv_fx1_ex0_instr), + .rv_xu1_ex0_itag(rv_fx1_ex0_itag), + .rv_xu1_ex0_isstore(rv_fx1_ex0_isStore), + .rv_xu1_ex0_ucode(rv_fx1_ex0_ucode[1:1]), + .rv_xu1_ex0_t1_v(rv_fx1_ex0_t1_v), + .rv_xu1_ex0_t1_p(rv_fx1_ex0_t1_p), + .rv_xu1_ex0_t2_v(rv_fx1_ex0_t2_v), + .rv_xu1_ex0_t2_p(rv_fx1_ex0_t2_p), + .rv_xu1_ex0_t3_v(rv_fx1_ex0_t3_v), + .rv_xu1_ex0_t3_p(rv_fx1_ex0_t3_p), + .rv_xu1_ex0_s1_v(rv_fx1_ex0_s1_v), + .rv_xu1_ex0_s3_t(rv_fx1_ex0_s3_t), + .rv_xu1_ex0_spec_flush(rv_fx1_ex0_spec_flush), + .rv_xu1_ex1_spec_flush(rv_fx1_ex1_spec_flush), + .rv_xu1_ex2_spec_flush(rv_fx1_ex2_spec_flush), + + //------------------------------------------------------------------- + // Interface with Bypass Controller + //------------------------------------------------------------------- + .rv_xu1_s1_fxu0_sel(rv_fx1_ex0_s1_fx0_sel), + .rv_xu1_s2_fxu0_sel(rv_fx1_ex0_s2_fx0_sel), + .rv_xu1_s3_fxu0_sel(rv_fx1_ex0_s3_fx0_sel[2:11]), + .rv_xu1_s1_fxu1_sel(rv_fx1_ex0_s1_fx1_sel), + .rv_xu1_s2_fxu1_sel(rv_fx1_ex0_s2_fx1_sel), + .rv_xu1_s3_fxu1_sel(rv_fx1_ex0_s3_fx1_sel[2:6]), + .rv_xu1_s1_lq_sel(rv_fx1_ex0_s1_lq_sel), + .rv_xu1_s2_lq_sel(rv_fx1_ex0_s2_lq_sel), + .rv_xu1_s3_lq_sel(rv_fx1_ex0_s3_lq_sel), + .rv_xu1_s1_rel_sel(rv_fx1_ex0_s1_rel_sel), + .rv_xu1_s2_rel_sel(rv_fx1_ex0_s2_rel_sel), + + //------------------------------------------------------------------- + // Interface with LQ + //------------------------------------------------------------------- + .xu1_lq_ex2_stq_val(xu1_lq_ex2_stq_val), + .xu1_lq_ex2_stq_itag(xu1_lq_ex2_stq_itag), + .xu1_lq_ex2_stq_size(xu1_lq_ex2_stq_size), + .xu1_lq_ex3_illeg_lswx(xu1_lq_ex3_illeg_lswx), + .xu1_lq_ex3_strg_noop(xu1_lq_ex3_strg_noop), + .xu1_lq_ex2_stq_dvc1_cmp(xu1_lq_ex2_stq_dvc1_cmp), + .xu1_lq_ex2_stq_dvc2_cmp(xu1_lq_ex2_stq_dvc2_cmp), + + //------------------------------------------------------------------- + // Interface with IU + //------------------------------------------------------------------- + .xu1_iu_execute_vld(xu1_iu_execute_vld), + .xu1_iu_itag(xu1_iu_itag), + + //------------------------------------------------------------------- + // Bypass Outputs + //------------------------------------------------------------------- + .xu1_lq_ex3_act(xu1_lq_ex3_act), + .xu1_lq_ex3_rt(xu1_lq_ex3_rt), + + //------------------------------------------------------------------- + // Unit Write Ports + //------------------------------------------------------------------- + .xu0_gpr_ex6_we(xu0_gpr_ex6_we), + .xu0_gpr_ex6_wa(xu0_gpr_ex6_wa), + .xu0_gpr_ex6_wd(xu0_gpr_ex6_wd), + .xu1_gpr_ex3_we(xu1_gpr_ex3_we), + .xu1_gpr_ex3_wa(xu1_gpr_ex3_wa), + .xu1_gpr_ex3_wd(xu1_gpr_ex3_wd), + + .lq_xu_gpr_ex5_we(lq_xu_gpr_ex5_we), + .lq_xu_gpr_ex5_wa(lq_xu_gpr_ex5_wa), + .lq_xu_gpr_rel_we(lq_xu_gpr_rel_we), + .lq_xu_gpr_rel_wa(lq_xu_gpr_rel_wa), + .lq_xu_gpr_rel_wd(lq_xu_gpr_rel_wd), + + .lq_xu_cr_l2_we(lq_xu_cr_l2_we), + .lq_xu_cr_l2_wa(lq_xu_cr_l2_wa), + .lq_xu_cr_l2_wd(lq_xu_cr_l2_wd), + .lq_xu_cr_ex5_we(lq_xu_cr_ex5_we), + .lq_xu_cr_ex5_wa(lq_xu_cr_ex5_wa), + .axu_xu_cr_w0e(axu0_cr_w4e), + .axu_xu_cr_w0a(axu0_cr_w4a), + .axu_xu_cr_w0d(axu0_cr_w4d), + + .iu_rf_xer_p_t0(iu_rf_t0_xer_p), +`ifndef THREADS1 + .iu_rf_xer_p_t1(iu_rf_t1_xer_p), +`endif + .xer_lq_cp_rd(xu_lq_xer_cp_rd), + + //------------------------------------------------------------------- + // AXU Pass Thru Interface + //------------------------------------------------------------------- + .lq_xu_axu_ex4_addr(lq_xu_axu_ex4_addr), + .lq_xu_axu_ex5_we(lq_xu_axu_ex5_we), + .lq_xu_axu_ex5_le(lq_xu_axu_ex5_le), + .xu_axu_lq_ex4_addr(xu_axu_lq_ex4_addr), + .xu_axu_lq_ex5_we(xu_axu_lq_ex5_we), + .xu_axu_lq_ex5_le(xu_axu_lq_ex5_le), + .xu_axu_lq_ex5_wa(xu_axu_lq_ex5_wa), + .xu_axu_lq_ex5_wd(xu_axu_lq_ex5_wd), + .xu_axu_lq_ex5_abort(xu_axu_lq_ex5_abort), + + .lq_xu_axu_rel_we(lq_xu_axu_rel_we), + .lq_xu_axu_rel_le(lq_xu_axu_rel_le), + .xu_axu_lq_rel_we(xu_axu_lq_rel_we), + .xu_axu_lq_rel_le(xu_axu_lq_rel_le), + .xu_axu_lq_rel_wa(xu_axu_lq_rel_wa), + .xu_axu_lq_rel_wd(xu_axu_lq_rel_wd), + + .axu_xu_lq_ex_stq_val(axu_xu_lq_ex_stq_val), + .axu_xu_lq_ex_stq_itag(axu_xu_lq_ex_stq_itag), + .axu_xu_lq_exp1_stq_data(axu_xu_lq_exp1_stq_data), + .xu_lq_axu_ex_stq_val(xu_lq_axu_ex_stq_val), + .xu_lq_axu_ex_stq_itag(xu_lq_axu_ex_stq_itag), + .xu_lq_axu_exp1_stq_data(xu_lq_axu_exp1_stq_data), + + //------------------------------------------------------------------- + // SPR + //------------------------------------------------------------------- + // PERF + .pc_xu_event_count_mode(pc_xu_event_count_mode), + .pc_xu_event_bus_enable(pc_xu_event_bus_enable), + .xu_event_bus_in(xu_event_bus_in), + .xu_event_bus_out(xu_event_bus_out), + // Debug + .pc_xu_debug_mux_ctrls(pc_xu_debug_mux_ctrls), + .xu_debug_bus_in(xu_debug_bus_in), + .xu_debug_bus_out(xu_debug_bus_out), + .xu_coretrace_ctrls_in(xu_coretrace_ctrls_in), + .xu_coretrace_ctrls_out(xu_coretrace_ctrls_out), + + .an_ac_coreid(an_ac_coreid), + .an_ac_chipid_dc(an_ac_chipid_dc), + .spr_pvr_version_dc(spr_pvr_version_dc), + .spr_pvr_revision_dc(spr_pvr_revision_dc), + .spr_pvr_revision_minor_dc(spr_pvr_revision_minor_dc), + .an_ac_ext_interrupt(an_ac_ext_interrupt), + .an_ac_crit_interrupt(an_ac_crit_interrupt), + .an_ac_perf_interrupt(an_ac_perf_interrupt), + .an_ac_reservation_vld(an_ac_reservation_vld), + .an_ac_tb_update_pulse(an_ac_tb_update_pulse), + .an_ac_tb_update_enable(an_ac_tb_update_enable), + .an_ac_sleep_en(an_ac_sleep_en), + .an_ac_hang_pulse(an_ac_hang_pulse), + .ac_tc_machine_check(ac_an_machine_check), + .an_ac_external_mchk(an_ac_external_mchk), + .pc_xu_instr_trace_mode(pc_xu_instr_trace_mode), + .pc_xu_instr_trace_tid(pc_xu_instr_trace_tid), + + .an_ac_scan_dis_dc_b(an_ac_scan_dis_dc_b), + .an_ac_scan_diag_dc(an_ac_scan_diag_dc), + + // Interrupt Interface + .iu_xu_rfi(iu_xu_rfi), + .iu_xu_rfgi(iu_xu_rfgi), + .iu_xu_rfci(iu_xu_rfci), + .iu_xu_rfmci(iu_xu_rfmci), + .iu_xu_act(iu_xu_act), + .iu_xu_int(iu_xu_int), + .iu_xu_gint(iu_xu_gint), + .iu_xu_cint(iu_xu_cint), + .iu_xu_mcint(iu_xu_mcint), + .iu_xu_dear_update(iu_xu_dear_update), + .iu_xu_dbsr_update(iu_xu_dbsr_update), + .iu_xu_dbsr_ude(iu_xu_dbsr_ude), + .iu_xu_dbsr_ide(iu_xu_dbsr_ide), + .iu_xu_esr_update(iu_xu_esr_update), + .iu_xu_force_gsrr(iu_xu_gdbell_taken), + .xu_iu_dbsr_ide(xu_iu_dbsr_ide), + .xu_iu_rest_ifar_t0(xu_iu_t0_rest_ifar), + .iu_xu_nia_t0(iu_xu_t0_nia), + .iu_xu_esr_t0(iu_xu_t0_esr), + .iu_xu_mcsr_t0(iu_xu_t0_mcsr), + .iu_xu_dbsr_t0(iu_xu_t0_dbsr), + .iu_xu_dear_t0(iu_xu_t0_dear), +`ifndef THREADS1 + .xu_iu_rest_ifar_t1(xu_iu_t1_rest_ifar), + .iu_xu_nia_t1(iu_xu_t1_nia), + .iu_xu_esr_t1(iu_xu_t1_esr), + .iu_xu_mcsr_t1(iu_xu_t1_mcsr), + .iu_xu_dbsr_t1(iu_xu_t1_dbsr), + .iu_xu_dear_t1(iu_xu_t1_dear), +`endif + // Async Interrupt Req Interface + .xu_iu_external_mchk(xu_iu_external_mchk), + .xu_iu_ext_interrupt(xu_iu_ext_interrupt), + .xu_iu_dec_interrupt(xu_iu_dec_interrupt), + .xu_iu_udec_interrupt(xu_iu_udec_interrupt), + .xu_iu_perf_interrupt(xu_iu_perf_interrupt), + .xu_iu_fit_interrupt(xu_iu_fit_interrupt), + .xu_iu_crit_interrupt(xu_iu_crit_interrupt), + .xu_iu_wdog_interrupt(xu_iu_wdog_interrupt), + .xu_iu_gwdog_interrupt(xu_iu_gwdog_interrupt), + .xu_iu_gfit_interrupt(xu_iu_gfit_interrupt), + .xu_iu_gdec_interrupt(xu_iu_gdec_interrupt), + .xu_iu_dbell_interrupt(xu_iu_dbell_interrupt), + .xu_iu_cdbell_interrupt(xu_iu_cdbell_interrupt), + .xu_iu_gdbell_interrupt(xu_iu_gdbell_interrupt), + .xu_iu_gcdbell_interrupt(xu_iu_gcdbell_interrupt), + .xu_iu_gmcdbell_interrupt(xu_iu_gmcdbell_interrupt), + .iu_xu_dbell_taken(iu_xu_dbell_taken), + .iu_xu_cdbell_taken(iu_xu_cdbell_taken), + .iu_xu_gdbell_taken(iu_xu_gdbell_taken), + .iu_xu_gcdbell_taken(iu_xu_gcdbell_taken), + .iu_xu_gmcdbell_taken(iu_xu_gmcdbell_taken), + + // DBELL Int + .lq_xu_dbell_val(lq_xu_dbell_val), + .lq_xu_dbell_type(lq_xu_dbell_type), + .lq_xu_dbell_brdcast(lq_xu_dbell_brdcast), + .lq_xu_dbell_lpid_match(lq_xu_dbell_lpid_match), + .lq_xu_dbell_pirtag(lq_xu_dbell_pirtag), + + // Slow SPR Bus + .xu_slowspr_val_out(xu_slowspr_val_out), + .xu_slowspr_rw_out(xu_slowspr_rw_out), + .xu_slowspr_etid_out(xu_slowspr_etid_out), + .xu_slowspr_addr_out(xu_slowspr_addr_out), + .xu_slowspr_data_out(xu_slowspr_data_out), + + // Trap + .xu_iu_fp_precise(), + // Run State + .pc_xu_pm_hold_thread(pc_xu_pm_hold_thread), + .iu_xu_stop(iu_xu_stop), + .xu_pc_running(xu_pc_running), + .xu_iu_run_thread(xu_iu_run_thread), + .xu_iu_single_instr_mode(xu_iu_single_instr_mode), + .xu_iu_raise_iss_pri(xu_iu_raise_iss_pri), + .xu_iu_np1_async_flush(xu_iu_np1_async_flush), + .iu_xu_async_complete(iu_xu_async_complete), + .iu_xu_credits_returned(iu_xu_credits_returned), + .xu_pc_spr_ccr0_we(xu_pc_spr_ccr0_we), + .xu_pc_stop_dnh_instr(xu_pc_stop_dnh_instr), + + // Quiesce + .iu_xu_icache_quiesce(iu_xu_icache_quiesce), + .iu_xu_quiesce(iu_xu_quiesce), + .lq_xu_quiesce(lq_xu_quiesce), + .mm_xu_quiesce(mm_xu_quiesce), + .bx_xu_quiesce(bx_xu_quiesce), + + // PCCR0 + .pc_xu_extirpts_dis_on_stop(pc_xu_extirpts_dis_on_stop), + .pc_xu_timebase_dis_on_stop(pc_xu_timebase_dis_on_stop), + .pc_xu_decrem_dis_on_stop(pc_xu_decrem_dis_on_stop), + + // MSR Override + .pc_xu_ram_active(pc_xu_ram_active), + .pc_xu_msrovride_enab(pc_xu_msrovride_enab), + .xu_iu_msrovride_enab(xu_iu_msrovride_enab), + .pc_xu_msrovride_pr(pc_xu_msrovride_pr), + .pc_xu_msrovride_gs(pc_xu_msrovride_gs), + .pc_xu_msrovride_de(pc_xu_msrovride_de), + // SIAR + .pc_xu_spr_cesr1_pmae(pc_xu_spr_cesr1_pmae), + .xu_pc_perfmon_alert(xu_pc_perfmon_alert), + + // LiveLock + .iu_xu_instr_cpl(iu_xu_instr_cpl), + .xu_pc_err_llbust_attempt(xu_pc_err_llbust_attempt), + .xu_pc_err_llbust_failed(xu_pc_err_llbust_failed), + + // Resets + .pc_xu_reset_wd_complete(an_ac_reset_wd_complete), + .pc_xu_reset_1_complete(an_ac_reset_1_complete), + .pc_xu_reset_2_complete(an_ac_reset_2_complete), + .pc_xu_reset_3_complete(an_ac_reset_3_complete), + .ac_tc_reset_1_request(ac_an_reset_1_request), + .ac_tc_reset_2_request(ac_an_reset_2_request), + .ac_tc_reset_3_request(ac_an_reset_3_request), + .ac_tc_reset_wd_request(ac_an_reset_wd_request), + + // Err Inject + .pc_xu_inj_llbust_attempt(pc_xu_inj_llbust_attempt), + .pc_xu_inj_llbust_failed(pc_xu_inj_llbust_failed), + .pc_xu_inj_wdt_reset({`THREADS{1'b0}}), + .xu_pc_err_wdt_reset(xu_pc_err_wdt_reset), + + // Parity + .pc_xu_inj_sprg_ecc(pc_xu_inj_sprg_ecc), + .xu_pc_err_sprg_ecc(xu_pc_err_sprg_ecc), + .xu_pc_err_sprg_ue(xu_pc_err_sprg_ue), + + // SPRs + .spr_dbcr0_edm(pc_xu_spr_dbcr0_edm), + .spr_xucr0_clkg_ctl(), + .xu_iu_iac1_en(xu_iu_iac1_en), + .xu_iu_iac2_en(xu_iu_iac2_en), + .xu_iu_iac3_en(xu_iu_iac3_en), + .xu_iu_iac4_en(xu_iu_iac4_en), + .lq_xu_spr_xucr0_cslc_xuop(lq_xu_spr_xucr0_cslc_xuop), + .lq_xu_spr_xucr0_cslc_binv(lq_xu_spr_xucr0_cslc_binv), + .lq_xu_spr_xucr0_clo(lq_xu_spr_xucr0_clo), + .lq_xu_spr_xucr0_cul(lq_xu_spr_xucr0_cul), + .spr_epcr_extgs(xu_iu_epcr_extgs), + .spr_epcr_icm(xu_iu_epcr_icm), + .spr_epcr_gicm(xu_iu_epcr_gicm), + .spr_msr_de(spr_msr_de), + .spr_msr_pr(spr_msr_pr), + .spr_msr_is(spr_msr_is), + .spr_msr_cm(spr_msr_cm), + .spr_msr_gs(spr_msr_gs), + .spr_msr_ee(spr_msr_ee), + .spr_msr_ce(spr_msr_ce), + .spr_msr_me(spr_msr_me), + .spr_msr_fe0(spr_msr_fe0), + .spr_msr_fe1(spr_msr_fe1), + .xu_lsu_spr_xucr0_clfc(spr_xucr0_clfc), + .xu_pc_spr_ccr0_pme(xu_pc_spr_ccr0_pme), + .spr_ccr2_en_dcr(spr_ccr2_en_dcr), + .spr_ccr2_en_trace(spr_ccr2_en_trace), + .spr_ccr2_ifratsc(spr_ccr2_ifratsc), + .spr_ccr2_ifrat(spr_ccr2_ifrat), + .spr_ccr2_dfratsc(spr_ccr2_dfratsc), + .spr_ccr2_dfrat(spr_ccr2_dfrat), + .spr_ccr2_ucode_dis(spr_ccr2_ucode_dis), + .spr_ccr2_ap(spr_ccr2_ap), + .spr_ccr2_en_ditc(spr_ccr2_en_ditc), + .spr_ccr2_en_icswx(spr_ccr2_en_icswx), + .spr_ccr2_notlb(spr_ccr2_notlb), + .spr_ccr2_en_pc(spr_ccr2_en_pc), + .spr_xucr0_trace_um(spr_xucr0_trace_um), + .xu_lsu_spr_xucr0_mbar_ack(spr_xucr0_mbar_ack), + .xu_lsu_spr_xucr0_tlbsync(spr_xucr0_tlbsync), + .spr_xucr0_cls(spr_xucr0_cls), + .xu_lsu_spr_xucr0_aflsta(spr_xucr0_aflsta), + .spr_xucr0_mddp(spr_xucr0_mddp), + .xu_lsu_spr_xucr0_cred(spr_xucr0_cred), + .xu_lsu_spr_xucr0_rel(spr_xucr0_rel), + .spr_xucr0_mdcp(spr_xucr0_mdcp), + .xu_lsu_spr_xucr0_flsta(spr_xucr0_flsta), + .xu_lsu_spr_xucr0_l2siw(spr_xucr0_l2siw), + .xu_lsu_spr_xucr0_flh2l2(spr_xucr0_flh2l2), + .xu_lsu_spr_xucr0_dcdis(spr_xucr0_dc_dis), + .xu_lsu_spr_xucr0_wlk(spr_xucr0_wlk), + .spr_dbcr0_idm(spr_dbcr0_idm), + .spr_dbcr0_icmp(spr_dbcr0_icmp), + .spr_dbcr0_brt(spr_dbcr0_brt), + .spr_dbcr0_irpt(spr_dbcr0_irpt), + .spr_dbcr0_trap(spr_dbcr0_trap), + .spr_dbcr0_dac1(spr_dbcr0_dac1), + .spr_dbcr0_dac2(spr_dbcr0_dac2), + .spr_dbcr0_ret(spr_dbcr0_ret), + .spr_dbcr0_dac3(spr_dbcr0_dac3), + .spr_dbcr0_dac4(spr_dbcr0_dac4), + .spr_dbcr1_iac12m(spr_dbcr1_iac12m), + .spr_dbcr1_iac34m(spr_dbcr1_iac34m), + .spr_epcr_dtlbgs(xu_iu_epcr_dtlbgs), + .spr_epcr_itlbgs(xu_iu_epcr_itlbgs), + .spr_epcr_dsigs(xu_iu_epcr_dsigs), + .spr_epcr_isigs(xu_iu_epcr_isigs), + .spr_epcr_duvd(xu_iu_epcr_duvd), + .spr_epcr_dgtmi(spr_epcr_dgtmi), + .xu_mm_spr_epcr_dmiuh(xu_mm_spr_epcr_dmiuh), + .spr_msr_ucle(spr_msr_ucle), + .spr_msr_spv(spr_msr_spv), + .spr_msr_fp(spr_msr_fp), + .spr_msr_ds(spr_msr_ds), + .spr_msrp_uclep(spr_msrp_uclep), + .spr_xucr4_mmu_mchk(spr_xucr4_mmu_mchk), + .spr_xucr4_mddmh(spr_xucr4_mddmh), + + .xu_iu_act(), + .xu_mm_act(), + + // BOLT-ON + .bo_enable_2(1'b0), // general bolt-on enable + .pc_xu_bo_reset(1'b0), // reset + .pc_xu_bo_unload(1'b0), // unload sticky bits + .pc_xu_bo_repair(1'b0), // execute sticky bit decode + .pc_xu_bo_shdata(1'b0), // shift data for timing write and diag loop + .pc_xu_bo_select(1'b0), // select for mask and hier writes + .xu_pc_bo_fail(), // fail/no-fix reg + .xu_pc_bo_diagout(), + // ABIST + .an_ac_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc), + .pc_xu_abist_ena_dc(1'b0), + .pc_xu_abist_g8t_wenb(1'b0), + .pc_xu_abist_waddr_0({6{1'b0}}), + .pc_xu_abist_di_0({4{1'b0}}), + .pc_xu_abist_g8t1p_renb_0(1'b0), + .pc_xu_abist_raddr_0({6{1'b0}}), + .pc_xu_abist_wl32_comp_ena(1'b0), + .pc_xu_abist_raw_dc_b(1'b0), + .pc_xu_abist_g8t_dcomp({4{1'b0}}), + .pc_xu_abist_g8t_bw_1(1'b0), + .pc_xu_abist_g8t_bw_0(1'b0), + + .pc_xu_trace_bus_enable(pc_xu_trace_bus_enable) + ); + + + + assign lq_rv_ord_complete = 1'b0; + assign rv_fx0_ex0_spec_flush = {`THREADS{1'b0}}; + assign rv_fx0_ex1_spec_flush = {`THREADS{1'b0}}; + assign rv_fx0_ex2_spec_flush = {`THREADS{1'b0}}; + assign rv_fx1_ex0_spec_flush = {`THREADS{1'b0}}; + assign rv_fx1_ex1_spec_flush = {`THREADS{1'b0}}; + assign rv_fx1_ex2_spec_flush = {`THREADS{1'b0}}; + + + + rv + rv0( + + //------------------------------------------------------------------- + // Instructions from IU + //------------------------------------------------------------------- + .iu_rv_iu6_t0_i0_vld(iu_rv_iu6_t0_i0_vld), + .iu_rv_iu6_t0_i0_rte_lq(iu_rv_iu6_t0_i0_rte_lq), + .iu_rv_iu6_t0_i0_rte_sq(iu_rv_iu6_t0_i0_rte_sq), + .iu_rv_iu6_t0_i0_rte_fx0(iu_rv_iu6_t0_i0_rte_fx0), + .iu_rv_iu6_t0_i0_rte_fx1(iu_rv_iu6_t0_i0_rte_fx1), + .iu_rv_iu6_t0_i0_rte_axu0(iu_rv_iu6_t0_i0_rte_axu0), + .iu_rv_iu6_t0_i0_rte_axu1(iu_rv_iu6_t0_i0_rte_axu1), + .iu_rv_iu6_t0_i0_act(iu_rv_iu6_t0_i0_act), + .iu_rv_iu6_t0_i0_instr(iu_rv_iu6_t0_i0_instr), + .iu_rv_iu6_t0_i0_ifar(iu_rv_iu6_t0_i0_ifar), + .iu_rv_iu6_t0_i0_ucode(iu_rv_iu6_t0_i0_ucode), + .iu_rv_iu6_t0_i0_2ucode(iu_rv_iu6_t0_i0_2ucode), + .iu_rv_iu6_t0_i0_ucode_cnt(iu_rv_iu6_t0_i0_ucode_cnt), + .iu_rv_iu6_t0_i0_itag(iu_rv_iu6_t0_i0_itag), + .iu_rv_iu6_t0_i0_ord(iu_rv_iu6_t0_i0_ord), + .iu_rv_iu6_t0_i0_cord(iu_rv_iu6_t0_i0_cord), + .iu_rv_iu6_t0_i0_spec(iu_rv_iu6_t0_i0_spec), + .iu_rv_iu6_t0_i0_t1_v(iu_rv_iu6_t0_i0_t1_v), + .iu_rv_iu6_t0_i0_t1_p(iu_rv_iu6_t0_i0_t1_p), + .iu_rv_iu6_t0_i0_t1_t(iu_rv_iu6_t0_i0_t1_t), + .iu_rv_iu6_t0_i0_t2_v(iu_rv_iu6_t0_i0_t2_v), + .iu_rv_iu6_t0_i0_t2_p(iu_rv_iu6_t0_i0_t2_p), + .iu_rv_iu6_t0_i0_t2_t(iu_rv_iu6_t0_i0_t2_t), + .iu_rv_iu6_t0_i0_t3_v(iu_rv_iu6_t0_i0_t3_v), + .iu_rv_iu6_t0_i0_t3_p(iu_rv_iu6_t0_i0_t3_p), + .iu_rv_iu6_t0_i0_t3_t(iu_rv_iu6_t0_i0_t3_t), + .iu_rv_iu6_t0_i0_s1_v(iu_rv_iu6_t0_i0_s1_v), + .iu_rv_iu6_t0_i0_s1_p(iu_rv_iu6_t0_i0_s1_p), + .iu_rv_iu6_t0_i0_s1_t(iu_rv_iu6_t0_i0_s1_t), + .iu_rv_iu6_t0_i0_s2_v(iu_rv_iu6_t0_i0_s2_v), + .iu_rv_iu6_t0_i0_s2_p(iu_rv_iu6_t0_i0_s2_p), + .iu_rv_iu6_t0_i0_s2_t(iu_rv_iu6_t0_i0_s2_t), + .iu_rv_iu6_t0_i0_s3_v(iu_rv_iu6_t0_i0_s3_v), + .iu_rv_iu6_t0_i0_s3_p(iu_rv_iu6_t0_i0_s3_p), + .iu_rv_iu6_t0_i0_s3_t(iu_rv_iu6_t0_i0_s3_t), + .iu_rv_iu6_t0_i0_ilat(iu_rv_iu6_t0_i0_ilat), + .iu_rv_iu6_t0_i0_isLoad(iu_rv_iu6_t0_i0_isLoad), + .iu_rv_iu6_t0_i0_isStore(iu_rv_iu6_t0_i0_isStore), + .iu_rv_iu6_t0_i0_s1_itag(iu_rv_iu6_t0_i0_s1_itag), + .iu_rv_iu6_t0_i0_s2_itag(iu_rv_iu6_t0_i0_s2_itag), + .iu_rv_iu6_t0_i0_s3_itag(iu_rv_iu6_t0_i0_s3_itag), + .iu_rv_iu6_t0_i0_fusion(iu_rv_iu6_t0_i0_fusion), + .iu_rv_iu6_t0_i0_bta_val(iu_rv_iu6_t0_i0_bta_val), + .iu_rv_iu6_t0_i0_bta(iu_rv_iu6_t0_i0_bta), + .iu_rv_iu6_t0_i0_br_pred(iu_rv_iu6_t0_i0_br_pred), + .iu_rv_iu6_t0_i0_ls_ptr(iu_rv_iu6_t0_i0_ls_ptr), + .iu_rv_iu6_t0_i0_bh_update(iu_rv_iu6_t0_i0_bh_update), + .iu_rv_iu6_t0_i0_gshare(iu_rv_iu6_t0_i0_gshare), + + .iu_rv_iu6_t0_i1_vld(iu_rv_iu6_t0_i1_vld), + .iu_rv_iu6_t0_i1_rte_lq(iu_rv_iu6_t0_i1_rte_lq), + .iu_rv_iu6_t0_i1_rte_sq(iu_rv_iu6_t0_i1_rte_sq), + .iu_rv_iu6_t0_i1_rte_fx0(iu_rv_iu6_t0_i1_rte_fx0), + .iu_rv_iu6_t0_i1_rte_fx1(iu_rv_iu6_t0_i1_rte_fx1), + .iu_rv_iu6_t0_i1_rte_axu0(iu_rv_iu6_t0_i1_rte_axu0), + .iu_rv_iu6_t0_i1_rte_axu1(iu_rv_iu6_t0_i1_rte_axu1), + .iu_rv_iu6_t0_i1_act(iu_rv_iu6_t0_i1_act), + .iu_rv_iu6_t0_i1_instr(iu_rv_iu6_t0_i1_instr), + .iu_rv_iu6_t0_i1_ifar(iu_rv_iu6_t0_i1_ifar), + .iu_rv_iu6_t0_i1_ucode(iu_rv_iu6_t0_i1_ucode), + .iu_rv_iu6_t0_i1_ucode_cnt(iu_rv_iu6_t0_i1_ucode_cnt), + .iu_rv_iu6_t0_i1_itag(iu_rv_iu6_t0_i1_itag), + .iu_rv_iu6_t0_i1_ord(iu_rv_iu6_t0_i1_ord), + .iu_rv_iu6_t0_i1_cord(iu_rv_iu6_t0_i1_cord), + .iu_rv_iu6_t0_i1_spec(iu_rv_iu6_t0_i1_spec), + .iu_rv_iu6_t0_i1_t1_v(iu_rv_iu6_t0_i1_t1_v), + .iu_rv_iu6_t0_i1_t1_p(iu_rv_iu6_t0_i1_t1_p), + .iu_rv_iu6_t0_i1_t1_t(iu_rv_iu6_t0_i1_t1_t), + .iu_rv_iu6_t0_i1_t2_v(iu_rv_iu6_t0_i1_t2_v), + .iu_rv_iu6_t0_i1_t2_p(iu_rv_iu6_t0_i1_t2_p), + .iu_rv_iu6_t0_i1_t2_t(iu_rv_iu6_t0_i1_t2_t), + .iu_rv_iu6_t0_i1_t3_v(iu_rv_iu6_t0_i1_t3_v), + .iu_rv_iu6_t0_i1_t3_p(iu_rv_iu6_t0_i1_t3_p), + .iu_rv_iu6_t0_i1_t3_t(iu_rv_iu6_t0_i1_t3_t), + .iu_rv_iu6_t0_i1_s1_v(iu_rv_iu6_t0_i1_s1_v), + .iu_rv_iu6_t0_i1_s1_p(iu_rv_iu6_t0_i1_s1_p), + .iu_rv_iu6_t0_i1_s1_t(iu_rv_iu6_t0_i1_s1_t), + .iu_rv_iu6_t0_i1_s2_v(iu_rv_iu6_t0_i1_s2_v), + .iu_rv_iu6_t0_i1_s2_p(iu_rv_iu6_t0_i1_s2_p), + .iu_rv_iu6_t0_i1_s2_t(iu_rv_iu6_t0_i1_s2_t), + .iu_rv_iu6_t0_i1_s3_v(iu_rv_iu6_t0_i1_s3_v), + .iu_rv_iu6_t0_i1_s3_p(iu_rv_iu6_t0_i1_s3_p), + .iu_rv_iu6_t0_i1_s3_t(iu_rv_iu6_t0_i1_s3_t), + .iu_rv_iu6_t0_i1_ilat(iu_rv_iu6_t0_i1_ilat), + .iu_rv_iu6_t0_i1_isLoad(iu_rv_iu6_t0_i1_isLoad), + .iu_rv_iu6_t0_i1_isStore(iu_rv_iu6_t0_i1_isStore), + .iu_rv_iu6_t0_i1_s1_itag(iu_rv_iu6_t0_i1_s1_itag), + .iu_rv_iu6_t0_i1_s2_itag(iu_rv_iu6_t0_i1_s2_itag), + .iu_rv_iu6_t0_i1_s3_itag(iu_rv_iu6_t0_i1_s3_itag), + .iu_rv_iu6_t0_i1_s1_dep_hit(iu_rv_iu6_t0_i1_s1_dep_hit), + .iu_rv_iu6_t0_i1_s2_dep_hit(iu_rv_iu6_t0_i1_s2_dep_hit), + .iu_rv_iu6_t0_i1_s3_dep_hit(iu_rv_iu6_t0_i1_s3_dep_hit), + .iu_rv_iu6_t0_i1_fusion(iu_rv_iu6_t0_i1_fusion), + .iu_rv_iu6_t0_i1_bta_val(iu_rv_iu6_t0_i1_bta_val), + .iu_rv_iu6_t0_i1_bta(iu_rv_iu6_t0_i1_bta), + .iu_rv_iu6_t0_i1_br_pred(iu_rv_iu6_t0_i1_br_pred), + .iu_rv_iu6_t0_i1_ls_ptr(iu_rv_iu6_t0_i1_ls_ptr), + .iu_rv_iu6_t0_i1_bh_update(iu_rv_iu6_t0_i1_bh_update), + .iu_rv_iu6_t0_i1_gshare(iu_rv_iu6_t0_i1_gshare), +`ifndef THREADS1 + .iu_rv_iu6_t1_i0_vld(iu_rv_iu6_t1_i0_vld), + .iu_rv_iu6_t1_i0_rte_lq(iu_rv_iu6_t1_i0_rte_lq), + .iu_rv_iu6_t1_i0_rte_sq(iu_rv_iu6_t1_i0_rte_sq), + .iu_rv_iu6_t1_i0_rte_fx0(iu_rv_iu6_t1_i0_rte_fx0), + .iu_rv_iu6_t1_i0_rte_fx1(iu_rv_iu6_t1_i0_rte_fx1), + .iu_rv_iu6_t1_i0_rte_axu0(iu_rv_iu6_t1_i0_rte_axu0), + .iu_rv_iu6_t1_i0_rte_axu1(iu_rv_iu6_t1_i0_rte_axu1), + .iu_rv_iu6_t1_i0_act(iu_rv_iu6_t1_i0_act), + .iu_rv_iu6_t1_i0_instr(iu_rv_iu6_t1_i0_instr), + .iu_rv_iu6_t1_i0_ifar(iu_rv_iu6_t1_i0_ifar), + .iu_rv_iu6_t1_i0_ucode(iu_rv_iu6_t1_i0_ucode), + .iu_rv_iu6_t1_i0_2ucode(iu_rv_iu6_t1_i0_2ucode), + .iu_rv_iu6_t1_i0_ucode_cnt(iu_rv_iu6_t1_i0_ucode_cnt), + .iu_rv_iu6_t1_i0_itag(iu_rv_iu6_t1_i0_itag), + .iu_rv_iu6_t1_i0_ord(iu_rv_iu6_t1_i0_ord), + .iu_rv_iu6_t1_i0_cord(iu_rv_iu6_t1_i0_cord), + .iu_rv_iu6_t1_i0_spec(iu_rv_iu6_t1_i0_spec), + .iu_rv_iu6_t1_i0_t1_v(iu_rv_iu6_t1_i0_t1_v), + .iu_rv_iu6_t1_i0_t1_p(iu_rv_iu6_t1_i0_t1_p), + .iu_rv_iu6_t1_i0_t1_t(iu_rv_iu6_t1_i0_t1_t), + .iu_rv_iu6_t1_i0_t2_v(iu_rv_iu6_t1_i0_t2_v), + .iu_rv_iu6_t1_i0_t2_p(iu_rv_iu6_t1_i0_t2_p), + .iu_rv_iu6_t1_i0_t2_t(iu_rv_iu6_t1_i0_t2_t), + .iu_rv_iu6_t1_i0_t3_v(iu_rv_iu6_t1_i0_t3_v), + .iu_rv_iu6_t1_i0_t3_p(iu_rv_iu6_t1_i0_t3_p), + .iu_rv_iu6_t1_i0_t3_t(iu_rv_iu6_t1_i0_t3_t), + .iu_rv_iu6_t1_i0_s1_v(iu_rv_iu6_t1_i0_s1_v), + .iu_rv_iu6_t1_i0_s1_p(iu_rv_iu6_t1_i0_s1_p), + .iu_rv_iu6_t1_i0_s1_t(iu_rv_iu6_t1_i0_s1_t), + .iu_rv_iu6_t1_i0_s2_v(iu_rv_iu6_t1_i0_s2_v), + .iu_rv_iu6_t1_i0_s2_p(iu_rv_iu6_t1_i0_s2_p), + .iu_rv_iu6_t1_i0_s2_t(iu_rv_iu6_t1_i0_s2_t), + .iu_rv_iu6_t1_i0_s3_v(iu_rv_iu6_t1_i0_s3_v), + .iu_rv_iu6_t1_i0_s3_p(iu_rv_iu6_t1_i0_s3_p), + .iu_rv_iu6_t1_i0_s3_t(iu_rv_iu6_t1_i0_s3_t), + .iu_rv_iu6_t1_i0_ilat(iu_rv_iu6_t1_i0_ilat), + .iu_rv_iu6_t1_i0_isLoad(iu_rv_iu6_t1_i0_isLoad), + .iu_rv_iu6_t1_i0_isStore(iu_rv_iu6_t1_i0_isStore), + .iu_rv_iu6_t1_i0_s1_itag(iu_rv_iu6_t1_i0_s1_itag), + .iu_rv_iu6_t1_i0_s2_itag(iu_rv_iu6_t1_i0_s2_itag), + .iu_rv_iu6_t1_i0_s3_itag(iu_rv_iu6_t1_i0_s3_itag), + .iu_rv_iu6_t1_i0_fusion(iu_rv_iu6_t1_i0_fusion), + .iu_rv_iu6_t1_i0_bta_val(iu_rv_iu6_t1_i0_bta_val), + .iu_rv_iu6_t1_i0_bta(iu_rv_iu6_t1_i0_bta), + .iu_rv_iu6_t1_i0_br_pred(iu_rv_iu6_t1_i0_br_pred), + .iu_rv_iu6_t1_i0_ls_ptr(iu_rv_iu6_t1_i0_ls_ptr), + .iu_rv_iu6_t1_i0_bh_update(iu_rv_iu6_t1_i0_bh_update), + .iu_rv_iu6_t1_i0_gshare(iu_rv_iu6_t1_i0_gshare), + + .iu_rv_iu6_t1_i1_vld(iu_rv_iu6_t1_i1_vld), + .iu_rv_iu6_t1_i1_rte_lq(iu_rv_iu6_t1_i1_rte_lq), + .iu_rv_iu6_t1_i1_rte_sq(iu_rv_iu6_t1_i1_rte_sq), + .iu_rv_iu6_t1_i1_rte_fx0(iu_rv_iu6_t1_i1_rte_fx0), + .iu_rv_iu6_t1_i1_rte_fx1(iu_rv_iu6_t1_i1_rte_fx1), + .iu_rv_iu6_t1_i1_rte_axu0(iu_rv_iu6_t1_i1_rte_axu0), + .iu_rv_iu6_t1_i1_rte_axu1(iu_rv_iu6_t1_i1_rte_axu1), + .iu_rv_iu6_t1_i1_act(iu_rv_iu6_t1_i1_act), + .iu_rv_iu6_t1_i1_instr(iu_rv_iu6_t1_i1_instr), + .iu_rv_iu6_t1_i1_ifar(iu_rv_iu6_t1_i1_ifar), + .iu_rv_iu6_t1_i1_ucode(iu_rv_iu6_t1_i1_ucode), + .iu_rv_iu6_t1_i1_ucode_cnt(iu_rv_iu6_t1_i1_ucode_cnt), + .iu_rv_iu6_t1_i1_itag(iu_rv_iu6_t1_i1_itag), + .iu_rv_iu6_t1_i1_ord(iu_rv_iu6_t1_i1_ord), + .iu_rv_iu6_t1_i1_cord(iu_rv_iu6_t1_i1_cord), + .iu_rv_iu6_t1_i1_spec(iu_rv_iu6_t1_i1_spec), + .iu_rv_iu6_t1_i1_t1_v(iu_rv_iu6_t1_i1_t1_v), + .iu_rv_iu6_t1_i1_t1_p(iu_rv_iu6_t1_i1_t1_p), + .iu_rv_iu6_t1_i1_t1_t(iu_rv_iu6_t1_i1_t1_t), + .iu_rv_iu6_t1_i1_t2_v(iu_rv_iu6_t1_i1_t2_v), + .iu_rv_iu6_t1_i1_t2_p(iu_rv_iu6_t1_i1_t2_p), + .iu_rv_iu6_t1_i1_t2_t(iu_rv_iu6_t1_i1_t2_t), + .iu_rv_iu6_t1_i1_t3_v(iu_rv_iu6_t1_i1_t3_v), + .iu_rv_iu6_t1_i1_t3_p(iu_rv_iu6_t1_i1_t3_p), + .iu_rv_iu6_t1_i1_t3_t(iu_rv_iu6_t1_i1_t3_t), + .iu_rv_iu6_t1_i1_s1_v(iu_rv_iu6_t1_i1_s1_v), + .iu_rv_iu6_t1_i1_s1_p(iu_rv_iu6_t1_i1_s1_p), + .iu_rv_iu6_t1_i1_s1_t(iu_rv_iu6_t1_i1_s1_t), + .iu_rv_iu6_t1_i1_s2_v(iu_rv_iu6_t1_i1_s2_v), + .iu_rv_iu6_t1_i1_s2_p(iu_rv_iu6_t1_i1_s2_p), + .iu_rv_iu6_t1_i1_s2_t(iu_rv_iu6_t1_i1_s2_t), + .iu_rv_iu6_t1_i1_s3_v(iu_rv_iu6_t1_i1_s3_v), + .iu_rv_iu6_t1_i1_s3_p(iu_rv_iu6_t1_i1_s3_p), + .iu_rv_iu6_t1_i1_s3_t(iu_rv_iu6_t1_i1_s3_t), + .iu_rv_iu6_t1_i1_ilat(iu_rv_iu6_t1_i1_ilat), + .iu_rv_iu6_t1_i1_isLoad(iu_rv_iu6_t1_i1_isLoad), + .iu_rv_iu6_t1_i1_isStore(iu_rv_iu6_t1_i1_isStore), + .iu_rv_iu6_t1_i1_s1_itag(iu_rv_iu6_t1_i1_s1_itag), + .iu_rv_iu6_t1_i1_s2_itag(iu_rv_iu6_t1_i1_s2_itag), + .iu_rv_iu6_t1_i1_s3_itag(iu_rv_iu6_t1_i1_s3_itag), + .iu_rv_iu6_t1_i1_s1_dep_hit(iu_rv_iu6_t1_i1_s1_dep_hit), + .iu_rv_iu6_t1_i1_s2_dep_hit(iu_rv_iu6_t1_i1_s2_dep_hit), + .iu_rv_iu6_t1_i1_s3_dep_hit(iu_rv_iu6_t1_i1_s3_dep_hit), + .iu_rv_iu6_t1_i1_fusion(iu_rv_iu6_t1_i1_fusion), + .iu_rv_iu6_t1_i1_bta_val(iu_rv_iu6_t1_i1_bta_val), + .iu_rv_iu6_t1_i1_bta(iu_rv_iu6_t1_i1_bta), + .iu_rv_iu6_t1_i1_br_pred(iu_rv_iu6_t1_i1_br_pred), + .iu_rv_iu6_t1_i1_ls_ptr(iu_rv_iu6_t1_i1_ls_ptr), + .iu_rv_iu6_t1_i1_bh_update(iu_rv_iu6_t1_i1_bh_update), + .iu_rv_iu6_t1_i1_gshare(iu_rv_iu6_t1_i1_gshare), + .cp_t1_next_itag(cp_t1_next_itag), + +`endif + + .cp_t0_next_itag(cp_t0_next_itag), + + .rv_iu_lq_credit_free(), + .rv_iu_fx0_credit_free(rv_iu_fx0_credit_free), + .rv_iu_fx1_credit_free(rv_iu_fx1_credit_free), + .rv_iu_axu0_credit_free(rv_iu_axu0_credit_free), + .rv_iu_axu1_credit_free(rv_iu_axu1_credit_free), + + //------------------------------------------------------------------- + // Machine zap interface + //------------------------------------------------------------------- + .cp_flush(cp_flush), + + //------------------------------------------------------------------- + // Interface to FX0 + //------------------------------------------------------------------- + .rv_fx0_vld(rv_fx0_vld), + .rv_fx0_s1_v(rv_fx0_s1_v), + .rv_fx0_s1_p(rv_fx0_s1_p), + .rv_fx0_s2_v(rv_fx0_s2_v), + .rv_fx0_s2_p(rv_fx0_s2_p), + .rv_fx0_s3_v(rv_fx0_s3_v), + .rv_fx0_s3_p(rv_fx0_s3_p), + + .rv_fx0_ex0_instr(rv_fx0_ex0_instr), + .rv_fx0_ex0_ifar(rv_fx0_ex0_ifar), + .rv_fx0_ex0_itag(rv_fx0_ex0_itag), + .rv_fx0_ex0_ucode(rv_fx0_ex0_ucode), + .rv_fx0_ex0_ucode_cnt(rv_fx0_ex0_ucode_cnt), + .rv_fx0_ex0_ord(rv_fx0_ex0_ord), + .rv_fx0_ex0_t1_v(rv_fx0_ex0_t1_v), + .rv_fx0_ex0_t1_p(rv_fx0_ex0_t1_p), + .rv_fx0_ex0_t1_t(rv_fx0_ex0_t1_t), + .rv_fx0_ex0_t2_v(rv_fx0_ex0_t2_v), + .rv_fx0_ex0_t2_p(rv_fx0_ex0_t2_p), + .rv_fx0_ex0_t2_t(rv_fx0_ex0_t2_t), + .rv_fx0_ex0_t3_v(rv_fx0_ex0_t3_v), + .rv_fx0_ex0_t3_p(rv_fx0_ex0_t3_p), + .rv_fx0_ex0_t3_t(rv_fx0_ex0_t3_t), + .rv_fx0_ex0_s1_v(rv_fx0_ex0_s1_v), + .rv_fx0_ex0_s2_v(rv_fx0_ex0_s2_v), + .rv_fx0_ex0_s2_t(rv_fx0_ex0_s2_t), + .rv_fx0_ex0_s3_v(rv_fx0_ex0_s3_v), + .rv_fx0_ex0_s3_t(rv_fx0_ex0_s3_t), + .rv_fx0_ex0_fusion(rv_fx0_ex0_fusion), + .rv_fx0_ex0_pred_bta(rv_fx0_ex0_pred_bta), + .rv_fx0_ex0_bta_val(rv_fx0_ex0_bta_val), + .rv_fx0_ex0_br_pred(rv_fx0_ex0_br_pred), + .rv_fx0_ex0_ls_ptr(rv_fx0_ex0_ls_ptr), + .rv_fx0_ex0_gshare(rv_fx0_ex0_gshare), + .rv_fx0_ex0_bh_update(rv_fx0_ex0_bh_update), + + .fx0_rv_ord_itag(fx0_rv_ord_itag), + .fx0_rv_ord_complete(fx0_rv_ord_complete), + .fx0_rv_hold_all(fx0_rv_hold_all), + + //------------------------------------------------------------------- + // Interface to FX1 + //------------------------------------------------------------------- + .rv_fx1_vld(rv_fx1_vld), + .rv_fx1_s1_v(rv_fx1_s1_v), + .rv_fx1_s1_p(rv_fx1_s1_p), + .rv_fx1_s2_v(rv_fx1_s2_v), + .rv_fx1_s2_p(rv_fx1_s2_p), + .rv_fx1_s3_v(rv_fx1_s3_v), + .rv_fx1_s3_p(rv_fx1_s3_p), + + .rv_fx1_ex0_instr(rv_fx1_ex0_instr), + .rv_fx1_ex0_itag(rv_fx1_ex0_itag), + .rv_fx1_ex0_ucode(rv_fx1_ex0_ucode), + .rv_fx1_ex0_t1_v(rv_fx1_ex0_t1_v), + .rv_fx1_ex0_t1_p(rv_fx1_ex0_t1_p), + .rv_fx1_ex0_t2_v(rv_fx1_ex0_t2_v), + .rv_fx1_ex0_t2_p(rv_fx1_ex0_t2_p), + .rv_fx1_ex0_t3_v(rv_fx1_ex0_t3_v), + .rv_fx1_ex0_t3_p(rv_fx1_ex0_t3_p), + .rv_fx1_ex0_s1_v(rv_fx1_ex0_s1_v), + .rv_fx1_ex0_s3_t(rv_fx1_ex0_s3_t), + .rv_fx1_ex0_isStore(rv_fx1_ex0_isStore), + + .fx1_rv_hold_all(fx1_rv_hold_all), + + //------------------------------------------------------------------- + // Interface to LQ + //------------------------------------------------------------------- + .rv_lq_vld(rv_lq_vld), + .rv_lq_isLoad(rv_lq_isLoad), + .rv_lq_ex0_itag(rv_lq_ex0_itag), + .rv_lq_ex0_instr(rv_lq_ex0_instr), + .rv_lq_ex0_ucode(rv_lq_ex0_ucode), + .rv_lq_ex0_ucode_cnt(rv_lq_ex0_ucode_cnt), + .rv_lq_ex0_spec(rv_lq_ex0_spec), + .rv_lq_ex0_t1_v(rv_lq_ex0_t1_v), + .rv_lq_ex0_t1_p(rv_lq_ex0_t1_p), + .rv_lq_ex0_t3_p(rv_lq_ex0_t3_p), + .rv_lq_ex0_s1_v(rv_lq_ex0_s1_v), + .rv_lq_ex0_s2_v(rv_lq_ex0_s2_v), + .rv_lq_ex0_s2_t(rv_lq_ex0_s2_t), + .rv_lq_rvs_empty(rv_lq_rvs_empty), + + // LQ Release Interface + .lq_rv_itag0_vld(lq_rv_itag0_vld), + .lq_rv_itag0(lq_rv_itag0), + .lq_rv_itag0_abort(lq_rv_itag0_abort), + + .lq_rv_itag1_vld(lq_rv_itag1_vld), + .lq_rv_itag1(lq_rv_itag1), + .lq_rv_itag1_restart(lq_rv_itag1_restart), + .lq_rv_itag1_abort(lq_rv_itag1_abort), + .lq_rv_itag1_hold(lq_rv_itag1_hold), + .lq_rv_itag1_cord(lq_rv_itag1_cord), + + .lq_rv_itag2_vld(lq_rv_itag2_vld), + .lq_rv_itag2(lq_rv_itag2), + + .lq_rv_clr_hold(lq_rv_clr_hold), + .lq_rv_ord_complete(lq_rv_ord_complete), + .lq_rv_hold_all(lq_rv_hold_all), + + .rv_lq_rv1_i0_vld(rv_lq_rv1_i0_vld), + .rv_lq_rv1_i0_ucode_preissue(rv_lq_rv1_i0_ucode_preissue), + .rv_lq_rv1_i0_ucode_cnt(rv_lq_rv1_i0_ucode_cnt), + .rv_lq_rv1_i0_2ucode(rv_lq_rv1_i0_2ucode), + .rv_lq_rv1_i0_s3_t(rv_lq_rv1_i0_s3_t), + .rv_lq_rv1_i0_isLoad(rv_lq_rv1_i0_isLoad), + .rv_lq_rv1_i0_isStore(rv_lq_rv1_i0_isStore), + .rv_lq_rv1_i0_itag(rv_lq_rv1_i0_itag), + .rv_lq_rv1_i0_rte_lq(rv_lq_rv1_i0_rte_lq), + .rv_lq_rv1_i0_rte_sq(rv_lq_rv1_i0_rte_sq), + .rv_lq_rv1_i0_ifar(rv_lq_rv1_i0_ifar), + + .rv_lq_rv1_i1_vld(rv_lq_rv1_i1_vld), + .rv_lq_rv1_i1_ucode_preissue(rv_lq_rv1_i1_ucode_preissue), + .rv_lq_rv1_i1_ucode_cnt(rv_lq_rv1_i1_ucode_cnt), + .rv_lq_rv1_i1_2ucode(rv_lq_rv1_i1_2ucode), + .rv_lq_rv1_i1_s3_t(rv_lq_rv1_i1_s3_t), + .rv_lq_rv1_i1_isLoad(rv_lq_rv1_i1_isLoad), + .rv_lq_rv1_i1_isStore(rv_lq_rv1_i1_isStore), + .rv_lq_rv1_i1_itag(rv_lq_rv1_i1_itag), + .rv_lq_rv1_i1_rte_lq(rv_lq_rv1_i1_rte_lq), + .rv_lq_rv1_i1_rte_sq(rv_lq_rv1_i1_rte_sq), + .rv_lq_rv1_i1_ifar(rv_lq_rv1_i1_ifar), + + //------------------------------------------------------------------- + // Interface to AXU0 + //------------------------------------------------------------------- + .rv_axu0_vld(rv_axu0_vld), + .rv_axu0_s1_v(rv_axu0_s1_v), + .rv_axu0_s1_p(rv_axu0_s1_p), + .rv_axu0_s2_v(rv_axu0_s2_v), + .rv_axu0_s2_p(rv_axu0_s2_p), + .rv_axu0_s3_v(rv_axu0_s3_v), + .rv_axu0_s3_p(rv_axu0_s3_p), + + .rv_axu0_ex0_itag(rv_axu0_ex0_itag), + .rv_axu0_ex0_instr(rv_axu0_ex0_instr), + .rv_axu0_ex0_ucode(rv_axu0_ex0_ucode), + .rv_axu0_ex0_t1_v(rv_axu0_ex0_t1_v), + .rv_axu0_ex0_t1_p(rv_axu0_ex0_t1_p), + .rv_axu0_ex0_t2_p(rv_axu0_ex0_t2_p), + .rv_axu0_ex0_t3_p(rv_axu0_ex0_t3_p), + + .axu0_rv_ord_complete(axu0_rv_ord_complete), + //------------------------------------------------------------------- + // Interface to AXU + //------------------------------------------------------------------- + .axu0_rv_itag_vld(axu0_rv_itag_vld), + .axu0_rv_itag(axu0_rv_itag), + .axu0_rv_itag_abort(axu0_rv_itag_abort), + .axu0_rv_hold_all(axu0_rv_hold_all), + .axu1_rv_itag_vld(axu1_rv_itag_vld), + .axu1_rv_itag(axu1_rv_itag), + .axu1_rv_itag_abort(axu1_rv_itag_abort), + .axu1_rv_hold_all(axu1_rv_hold_all), + //------------------------------------------------------------------- + // Abort + //------------------------------------------------------------------- + .lq_rv_ex2_s1_abort(lq_rv_ex2_s1_abort) , + .lq_rv_ex2_s2_abort(lq_rv_ex2_s2_abort) , + .fx0_rv_ex2_s1_abort(fx0_rv_ex2_s1_abort) , + .fx0_rv_ex2_s2_abort(fx0_rv_ex2_s2_abort) , + .fx0_rv_ex2_s3_abort(fx0_rv_ex2_s3_abort) , + .fx1_rv_ex2_s1_abort(fx1_rv_ex2_s1_abort) , + .fx1_rv_ex2_s2_abort(fx1_rv_ex2_s2_abort) , + .fx1_rv_ex2_s3_abort(fx1_rv_ex2_s3_abort) , + .axu0_rv_ex2_s1_abort(axu0_rv_ex2_s1_abort) , + .axu0_rv_ex2_s2_abort(axu0_rv_ex2_s2_abort) , + .axu0_rv_ex2_s3_abort(axu0_rv_ex2_s3_abort) , + + + //------------------------------------------------------------------- + // Bypass + //------------------------------------------------------------------- + .rv_fx0_ex0_s1_fx0_sel(rv_fx0_ex0_s1_fx0_sel), + .rv_fx0_ex0_s2_fx0_sel(rv_fx0_ex0_s2_fx0_sel), + .rv_fx0_ex0_s3_fx0_sel(rv_fx0_ex0_s3_fx0_sel), + .rv_fx0_ex0_s1_lq_sel(rv_fx0_ex0_s1_lq_sel), + .rv_fx0_ex0_s2_lq_sel(rv_fx0_ex0_s2_lq_sel), + .rv_fx0_ex0_s3_lq_sel(rv_fx0_ex0_s3_lq_sel), + .rv_fx0_ex0_s1_fx1_sel(rv_fx0_ex0_s1_fx1_sel), + .rv_fx0_ex0_s2_fx1_sel(rv_fx0_ex0_s2_fx1_sel), + .rv_fx0_ex0_s3_fx1_sel(rv_fx0_ex0_s3_fx1_sel), + .rv_lq_ex0_s1_fx0_sel(rv_lq_ex0_s1_fx0_sel), + .rv_lq_ex0_s2_fx0_sel(rv_lq_ex0_s2_fx0_sel), + .rv_lq_ex0_s1_lq_sel(rv_lq_ex0_s1_lq_sel), + .rv_lq_ex0_s2_lq_sel(rv_lq_ex0_s2_lq_sel), + .rv_lq_ex0_s1_fx1_sel(rv_lq_ex0_s1_fx1_sel), + .rv_lq_ex0_s2_fx1_sel(rv_lq_ex0_s2_fx1_sel), + .rv_fx1_ex0_s1_fx0_sel(rv_fx1_ex0_s1_fx0_sel), + .rv_fx1_ex0_s2_fx0_sel(rv_fx1_ex0_s2_fx0_sel), + .rv_fx1_ex0_s3_fx0_sel(rv_fx1_ex0_s3_fx0_sel), + .rv_fx1_ex0_s1_lq_sel(rv_fx1_ex0_s1_lq_sel), + .rv_fx1_ex0_s2_lq_sel(rv_fx1_ex0_s2_lq_sel), + .rv_fx1_ex0_s3_lq_sel(rv_fx1_ex0_s3_lq_sel), + .rv_fx1_ex0_s1_fx1_sel(rv_fx1_ex0_s1_fx1_sel), + .rv_fx1_ex0_s2_fx1_sel(rv_fx1_ex0_s2_fx1_sel), + .rv_fx1_ex0_s3_fx1_sel(rv_fx1_ex0_s3_fx1_sel), + .rv_fx0_ex0_s1_rel_sel(rv_fx0_ex0_s1_rel_sel), + .rv_fx0_ex0_s2_rel_sel(rv_fx0_ex0_s2_rel_sel), + .rv_fx0_ex0_s3_rel_sel(rv_fx0_ex0_s3_rel_sel), + .rv_lq_ex0_s1_rel_sel(rv_lq_ex0_s1_rel_sel), + .rv_lq_ex0_s2_rel_sel(rv_lq_ex0_s2_rel_sel), + .rv_fx1_ex0_s1_rel_sel(rv_fx1_ex0_s1_rel_sel), + .rv_fx1_ex0_s2_rel_sel(rv_fx1_ex0_s2_rel_sel), + .rv_fx1_ex0_s3_rel_sel(rv_fx1_ex0_s3_rel_sel), + + //------------------------------------------------------------------- + // LQ Regfile + //------------------------------------------------------------------- + .xu0_gpr_ex6_we(xu0_gpr_ex6_we), + .xu0_gpr_ex6_wa(xu0_gpr_ex6_wa), + .xu0_gpr_ex6_wd(xu0_gpr_ex6_wd), + .xu1_gpr_ex3_we(xu1_gpr_ex3_we), + .xu1_gpr_ex3_wa(xu1_gpr_ex3_wa), + .xu1_gpr_ex3_wd(xu1_gpr_ex3_wd), + + .lq_rv_gpr_ex6_we(lq_rv_gpr_ex6_we), + .lq_rv_gpr_ex6_wa(lq_rv_gpr_ex6_wa), + .lq_rv_gpr_ex6_wd(lq_rv_gpr_ex6_wd), + + .lq_rv_gpr_rel_we(lq_rv_gpr_rel_we), + .lq_rv_gpr_rel_wa(lq_rv_gpr_rel_wa), + .lq_rv_gpr_rel_wd(lq_rv_gpr_rel_wd), + + .rv_lq_gpr_ex1_r0d(rv_lq_gpr_ex1_r0d), + .rv_lq_gpr_ex1_r1d(rv_lq_gpr_ex1_r1d), + + //------------------------------------------------------------------- + // Debug and perf + //------------------------------------------------------------------- + .pc_rv_trace_bus_enable(pc_rv_trace_bus_enable), + .pc_rv_debug_mux_ctrls(pc_rv_debug_mux_ctrls), + .pc_rv_event_bus_enable(pc_rv_event_bus_enable), + .pc_rv_event_count_mode(pc_rv_event_count_mode), + .pc_rv_event_mux_ctrls(pc_rv_event_mux_ctrls), + .spr_msr_gs(spr_msr_gs), + .spr_msr_pr(spr_msr_pr), + + .rv_event_bus_in(rv_event_bus_in), + .rv_event_bus_out(rv_event_bus_out), + + .debug_bus_out(rv_debug_bus_out), + .coretrace_ctrls_out(rv_coretrace_ctrls_out), + .debug_bus_in(rv_debug_bus_in), + .coretrace_ctrls_in(rv_coretrace_ctrls_in), + + //------------------------------------------------------------------- + // Pervasive + //------------------------------------------------------------------- + //.vdd(vdd), + //.gnd(gnd), + .nclk(nclk), + + .rp_rv_ccflush_dc(rp_rv_ccflush_dc), + .rp_rv_func_sl_thold_3(rp_rv_func_sl_thold_3), + .rp_rv_gptr_sl_thold_3(rp_rv_gptr_sl_thold_3), + .rp_rv_sg_3(rp_rv_sg_3), + .rp_rv_fce_3(rp_rv_fce_3), + .an_ac_scan_dis_dc_b(an_ac_scan_dis_dc_b), + .an_ac_scan_diag_dc(an_ac_scan_diag_dc), + + .scan_in(scan_in_rv), + .scan_out(scan_out_rv) + ); + + + lq + lq0( + //-------------------------------------------------------------- + // SPR Interface + //-------------------------------------------------------------- + .xu_lq_spr_ccr2_en_trace(spr_ccr2_en_trace), + .xu_lq_spr_ccr2_en_pc(spr_ccr2_en_pc), + .xu_lq_spr_ccr2_en_ditc(spr_ccr2_en_ditc), + .xu_lq_spr_ccr2_en_icswx(spr_ccr2_en_icswx), + .xu_lq_spr_ccr2_dfrat(spr_ccr2_dfrat), + .xu_lq_spr_ccr2_dfratsc(spr_ccr2_dfratsc), + .xu_lq_spr_ccr2_ap(spr_ccr2_ap[0]), + .xu_lq_spr_ccr2_ucode_dis(spr_ccr2_ucode_dis), + .xu_lq_spr_xucr0_clkg_ctl(1'b0), + .xu_lq_spr_xucr0_wlk(spr_xucr0_wlk), + .xu_lq_spr_xucr0_mbar_ack(spr_xucr0_mbar_ack), + .xu_lq_spr_xucr0_tlbsync(spr_xucr0_tlbsync), + .xu_lq_spr_xucr0_dcdis(spr_xucr0_dc_dis), + .xu_lq_spr_xucr0_aflsta(spr_xucr0_aflsta), + .xu_lq_spr_xucr0_flsta(spr_xucr0_flsta), + .xu_lq_spr_xucr0_clfc(spr_xucr0_clfc), + .xu_lq_spr_xucr0_cls(spr_xucr0_cls), + .xu_lq_spr_xucr0_trace_um(spr_xucr0_trace_um[0:`THREADS - 1]), + .xu_lq_spr_xucr0_cred(spr_xucr0_cred), + .xu_lq_spr_xucr0_mddp(spr_xucr0_mddp), + .xu_lq_spr_xucr0_mdcp(spr_xucr0_mdcp), + .xu_lq_spr_ccr2_notlb(spr_ccr2_notlb), + .xu_lq_spr_xucr4_mmu_mchk(spr_xucr4_mmu_mchk), + .xu_lq_spr_xucr4_mddmh(spr_xucr4_mddmh), + .xu_lq_spr_dbcr0_dac1(spr_dbcr0_dac1), + .xu_lq_spr_dbcr0_dac2(spr_dbcr0_dac2), + .xu_lq_spr_dbcr0_dac3(spr_dbcr0_dac3), + .xu_lq_spr_dbcr0_dac4(spr_dbcr0_dac4), + .xu_lq_spr_dbcr0_idm(spr_dbcr0_idm), + .xu_lq_spr_epcr_duvd(xu_iu_epcr_duvd), + .xu_lq_spr_msr_cm(spr_msr_cm), + .xu_lq_spr_msr_fp(spr_msr_fp), + .xu_lq_spr_msr_spv(spr_msr_spv), + .xu_lq_spr_msr_gs(spr_msr_gs), + .xu_lq_spr_msr_pr(spr_msr_pr), + .xu_lq_spr_msr_ds(spr_msr_ds), + .xu_lq_spr_msr_ucle(spr_msr_ucle), + .xu_lq_spr_msr_de(spr_msr_de), + .xu_lq_spr_msrp_uclep(spr_msrp_uclep), + .iu_lq_spr_iucr0_icbi_ack(iu_lq_spr_iucr0_icbi_ack), + .lq_xu_spr_xucr0_cul(lq_xu_spr_xucr0_cul), + .lq_xu_spr_xucr0_cslc_xuop(lq_xu_spr_xucr0_cslc_xuop), + .lq_xu_spr_xucr0_cslc_binv(lq_xu_spr_xucr0_cslc_binv), + .lq_xu_spr_xucr0_clo(lq_xu_spr_xucr0_clo), + .lq_iu_spr_dbcr3_ivc(lq_iu_spr_dbcr3_ivc), + .slowspr_val_in(lq_slowspr_val_in), + .slowspr_rw_in(lq_slowspr_rw_in), + .slowspr_etid_in(lq_slowspr_etid_in), + .slowspr_addr_in(lq_slowspr_addr_in), + .slowspr_data_in(lq_slowspr_data_in), + .slowspr_done_in(lq_slowspr_done_in), + .slowspr_val_out(lq_slowspr_val_out), + .slowspr_rw_out(lq_slowspr_rw_out), + .slowspr_etid_out(lq_slowspr_etid_out), + .slowspr_addr_out(lq_slowspr_addr_out), + .slowspr_data_out(lq_slowspr_data_out), + .slowspr_done_out(lq_slowspr_done_out), + + //-------------------------------------------------------------- + // CP Interface + //-------------------------------------------------------------- + .iu_lq_cp_flush(cp_flush), + .iu_lq_recirc_val(iu_lq_recirc_val), + .iu_lq_cp_next_itag_t0(cp_t0_next_itag), +`ifndef THREADS1 + .iu_lq_cp_next_itag_t1(cp_t1_next_itag), +`endif + .iu_lq_isync(cp_is_isync), + .iu_lq_csync(cp_is_csync), + .lq0_iu_execute_vld(lq0_iu_execute_vld), + .lq0_iu_recirc_val(lq0_iu_recirc_val), + .lq0_iu_dear_val(lq0_iu_dear_val), + .lq0_iu_itag(lq0_iu_itag), + .lq0_iu_flush2ucode(lq0_iu_flush2ucode), + .lq0_iu_flush2ucode_type(lq0_iu_flush2ucode_type), + .lq0_iu_exception_val(lq0_iu_exception_val), + .lq0_iu_exception(lq0_iu_exception), + .lq0_iu_n_flush(lq0_iu_n_flush), + .lq0_iu_np1_flush(lq0_iu_np1_flush), + .lq0_iu_dacr_type(lq0_iu_dacr_type), + .lq0_iu_dacrw(lq0_iu_dacrw), + .lq0_iu_instr(lq0_iu_instr), + .lq0_iu_eff_addr(lq0_iu_eff_addr), + .lq1_iu_execute_vld(lq1_iu_execute_vld), + .lq1_iu_itag(lq1_iu_itag), + .lq1_iu_exception_val(lq1_iu_exception_val), + .lq1_iu_exception(lq1_iu_exception), + .lq1_iu_n_flush(lq1_iu_n_flush), + .lq1_iu_np1_flush(lq1_iu_np1_flush), + .lq1_iu_dacr_type(lq1_iu_dacr_type), + .lq1_iu_dacrw(lq1_iu_dacrw), + .lq1_iu_perf_events(lq1_iu_perf_events), + .rv_lq_rv1_i0_vld(rv_lq_rv1_i0_vld), + .rv_lq_rv1_i0_ucode_preissue(rv_lq_rv1_i0_ucode_preissue), + .rv_lq_rv1_i0_2ucode(rv_lq_rv1_i0_2ucode), + .rv_lq_rv1_i0_ucode_cnt(rv_lq_rv1_i0_ucode_cnt), + .rv_lq_rv1_i0_s3_t(rv_lq_rv1_i0_s3_t), + .rv_lq_rv1_i0_isLoad(rv_lq_rv1_i0_isLoad), + .rv_lq_rv1_i0_isStore(rv_lq_rv1_i0_isStore), + .rv_lq_rv1_i0_itag(rv_lq_rv1_i0_itag), + .rv_lq_rv1_i0_rte_lq(rv_lq_rv1_i0_rte_lq), + .rv_lq_rv1_i0_rte_sq(rv_lq_rv1_i0_rte_sq), + .rv_lq_rv1_i0_ifar(rv_lq_rv1_i0_ifar), + .rv_lq_rv1_i1_vld(rv_lq_rv1_i1_vld), + .rv_lq_rv1_i1_ucode_preissue(rv_lq_rv1_i1_ucode_preissue), + .rv_lq_rv1_i1_2ucode(rv_lq_rv1_i1_2ucode), + .rv_lq_rv1_i1_ucode_cnt(rv_lq_rv1_i1_ucode_cnt), + .rv_lq_rv1_i1_s3_t(rv_lq_rv1_i1_s3_t), + .rv_lq_rv1_i1_isLoad(rv_lq_rv1_i1_isLoad), + .rv_lq_rv1_i1_isStore(rv_lq_rv1_i1_isStore), + .rv_lq_rv1_i1_itag(rv_lq_rv1_i1_itag), + .rv_lq_rv1_i1_rte_lq(rv_lq_rv1_i1_rte_lq), + .rv_lq_rv1_i1_rte_sq(rv_lq_rv1_i1_rte_sq), + .rv_lq_rv1_i1_ifar(rv_lq_rv1_i1_ifar), + .lq_iu_credit_free(lq_iu_credit_free), + .sq_iu_credit_free(sq_iu_credit_free), + .iu_lq_i0_completed(iu_lq_i0_completed), + .iu_lq_i1_completed(iu_lq_i1_completed), + .iu_lq_i0_completed_itag_t0(iu_lq_t0_i0_completed_itag), + .iu_lq_i1_completed_itag_t0(iu_lq_t0_i1_completed_itag), +`ifndef THREADS1 + .iu_lq_i0_completed_itag_t1(iu_lq_t1_i0_completed_itag), + .iu_lq_i1_completed_itag_t1(iu_lq_t1_i1_completed_itag), +`endif + .iu_lq_request(iu_lq_request), + .iu_lq_cTag(iu_lq_cTag), + .iu_lq_ra(iu_lq_ra), + .iu_lq_wimge(iu_lq_wimge), + .iu_lq_userdef(iu_lq_userdef), + .lq_iu_icbi_val(lq_iu_icbi_val), + .lq_iu_icbi_addr(lq_iu_icbi_addr), + .iu_lq_icbi_complete(iu_lq_icbi_complete), + .lq_iu_ici_val(lq_iu_ici_val), + + //-------------------------------------------------------------- + // Interface with XU DERAT + //-------------------------------------------------------------- + .xu_lq_act(xu_lq_act), + .xu_lq_val(xu_lq_val), + .xu_lq_is_eratre(xu_lq_is_eratre), + .xu_lq_is_eratwe(xu_lq_is_eratwe), + .xu_lq_is_eratsx(xu_lq_is_eratsx), + .xu_lq_is_eratilx(xu_lq_is_eratilx), + .xu_lq_ws(xu_lq_ws), + .xu_lq_ra_entry(xu_lq_ra_entry), + .xu_lq_rs_data(xu_lq_rs_data), + .xu_lq_hold_req(xu_lq_hold_req), + .lq_xu_ex5_data(lq_xu_ex5_data), + .lq_xu_ord_par_err(lq_xu_ord_par_err), + .lq_xu_ord_read_done(lq_xu_ord_read_done), + .lq_xu_ord_write_done(lq_xu_ord_write_done), + + //-------------------------------------------------------------- + // Doorbell Interface with XU + //-------------------------------------------------------------- + .lq_xu_dbell_val(lq_xu_dbell_val), + .lq_xu_dbell_type(lq_xu_dbell_type), + .lq_xu_dbell_brdcast(lq_xu_dbell_brdcast), + .lq_xu_dbell_lpid_match(lq_xu_dbell_lpid_match), + .lq_xu_dbell_pirtag(lq_xu_dbell_pirtag), + + //-------------------------------------------------------------- + // Interface with RV + //-------------------------------------------------------------- + .rv_lq_rvs_empty(rv_lq_rvs_empty), + .rv_lq_vld(rv_lq_vld), + .rv_lq_ex0_itag(rv_lq_ex0_itag), + .rv_lq_isLoad(rv_lq_isLoad), + .rv_lq_ex0_instr(rv_lq_ex0_instr), + .rv_lq_ex0_ucode(rv_lq_ex0_ucode[0:1]), + .rv_lq_ex0_ucode_cnt(rv_lq_ex0_ucode_cnt), + .rv_lq_ex0_t1_v(rv_lq_ex0_t1_v), + .rv_lq_ex0_t1_p(rv_lq_ex0_t1_p), + .rv_lq_ex0_t3_p(rv_lq_ex0_t3_p), + .rv_lq_ex0_s1_v(rv_lq_ex0_s1_v), + .rv_lq_ex0_s2_v(rv_lq_ex0_s2_v), + + .lq_rv_itag0(lq_rv_itag0), + .lq_rv_itag0_vld(lq_rv_itag0_vld), + .lq_rv_itag0_abort(lq_rv_itag0_abort), + .lq_rv_ex2_s1_abort(lq_rv_ex2_s1_abort), + .lq_rv_ex2_s2_abort(lq_rv_ex2_s2_abort), + .lq_rv_hold_all(lq_rv_hold_all), + .lq_rv_itag1_vld(lq_rv_itag1_vld), + .lq_rv_itag1(lq_rv_itag1), + .lq_rv_itag1_restart(lq_rv_itag1_restart), + .lq_rv_itag1_abort(lq_rv_itag1_abort), + .lq_rv_itag1_hold(lq_rv_itag1_hold), + .lq_rv_itag1_cord(lq_rv_itag1_cord), + .lq_rv_itag2_vld(lq_rv_itag2_vld), + .lq_rv_itag2(lq_rv_itag2), + .lq_rv_clr_hold(lq_rv_clr_hold), + + //------------------------------------------------------------------- + // Interface with Bypass Controller + //------------------------------------------------------------------- + .rv_lq_ex0_s1_xu0_sel(rv_lq_ex0_s1_fx0_sel), + .rv_lq_ex0_s2_xu0_sel(rv_lq_ex0_s2_fx0_sel), + .rv_lq_ex0_s1_xu1_sel(rv_lq_ex0_s1_fx1_sel), + .rv_lq_ex0_s2_xu1_sel(rv_lq_ex0_s2_fx1_sel), + .rv_lq_ex0_s1_lq_sel(rv_lq_ex0_s1_lq_sel), + .rv_lq_ex0_s2_lq_sel(rv_lq_ex0_s2_lq_sel), + .rv_lq_ex0_s1_rel_sel(rv_lq_ex0_s1_rel_sel), + .rv_lq_ex0_s2_rel_sel(rv_lq_ex0_s2_rel_sel), + + //-------------------------------------------------------------- + // Interface with Regfiles + //-------------------------------------------------------------- + .xu_lq_xer_cp_rd(xu_lq_xer_cp_rd), + .rv_lq_gpr_ex1_r0d(rv_lq_gpr_ex1_r0d[64 - `GPR_WIDTH:63]), + .rv_lq_gpr_ex1_r1d(rv_lq_gpr_ex1_r1d[64 - `GPR_WIDTH:63]), + .lq_rv_gpr_ex6_we(lq_rv_gpr_ex6_we), + .lq_rv_gpr_ex6_wa(lq_rv_gpr_ex6_wa), + .lq_rv_gpr_ex6_wd(lq_rv_gpr_ex6_wd), + .lq_xu_gpr_ex5_we(lq_xu_gpr_ex5_we), + .lq_xu_gpr_ex5_wa(lq_xu_gpr_ex5_wa), + .lq_rv_gpr_rel_we(lq_rv_gpr_rel_we), + .lq_rv_gpr_rel_wa(lq_rv_gpr_rel_wa), + .lq_rv_gpr_rel_wd(lq_rv_gpr_rel_wd), + .lq_xu_gpr_rel_we(lq_xu_gpr_rel_we), + .lq_xu_gpr_rel_wa(lq_xu_gpr_rel_wa), + .lq_xu_gpr_rel_wd(lq_xu_gpr_rel_wd), + .lq_xu_axu_rel_we(lq_xu_axu_rel_we), + .lq_xu_axu_rel_le(lq_xu_axu_rel_le), + .lq_xu_cr_l2_we(lq_xu_cr_l2_we), + .lq_xu_cr_l2_wa(lq_xu_cr_l2_wa), + .lq_xu_cr_l2_wd(lq_xu_cr_l2_wd), + .lq_xu_cr_ex5_we(lq_xu_cr_ex5_we), + .lq_xu_cr_ex5_wa(lq_xu_cr_ex5_wa), + + //------------------------------------------------------------------- + // Interface with FXU0 + //------------------------------------------------------------------- + .xu0_lq_ex3_act(xu0_lq_ex3_act), + .xu0_lq_ex3_abort(xu0_lq_ex3_abort), + .xu0_lq_ex3_rt(xu0_lq_ex3_rt), + .xu0_lq_ex4_rt(xu0_lq_ex4_rt), + .xu0_lq_ex6_rt(xu0_lq_ex6_rt), + .xu0_lq_ex6_act(xu0_lq_ex6_act), + .lq_xu_ex5_act(lq_xu_ex5_act), + .lq_xu_ex5_cr(lq_xu_ex5_cr), + .lq_xu_ex5_rt(lq_xu_ex5_rt), + .lq_xu_ex5_abort(lq_xu_ex5_abort), + + //------------------------------------------------------------------- + // Interface with FXU1 + //------------------------------------------------------------------- + .xu1_lq_ex3_act(xu1_lq_ex3_act), + .xu1_lq_ex3_abort(xu1_lq_ex3_abort), + .xu1_lq_ex3_rt(xu1_lq_ex3_rt), + .xu1_lq_ex2_stq_val(xu1_lq_ex2_stq_val), + .xu1_lq_ex2_stq_itag(xu1_lq_ex2_stq_itag), + .xu1_lq_ex2_stq_size(xu1_lq_ex2_stq_size), + .xu1_lq_ex2_stq_dvc1_cmp(xu1_lq_ex2_stq_dvc1_cmp), + .xu1_lq_ex2_stq_dvc2_cmp(xu1_lq_ex2_stq_dvc2_cmp), + .xu1_lq_ex3_illeg_lswx(xu1_lq_ex3_illeg_lswx), + .xu1_lq_ex3_strg_noop(xu1_lq_ex3_strg_noop), + + //-------------------------------------------------------------- + // Interface with FU + //-------------------------------------------------------------- + .xu_lq_axu_ex_stq_val(xu_lq_axu_ex_stq_val), + .xu_lq_axu_ex_stq_itag(xu_lq_axu_ex_stq_itag), + .xu_lq_axu_exp1_stq_data(xu_lq_axu_exp1_stq_data), + .lq_xu_axu_ex4_addr(lq_xu_axu_ex4_addr), + .lq_xu_axu_ex5_we(lq_xu_axu_ex5_we), + .lq_xu_axu_ex5_le(lq_xu_axu_ex5_le), + + //-------------------------------------------------------------- + // Interface with MMU + //-------------------------------------------------------------- + .mm_lq_lsu_req(mm_lq_lsu_req), + .mm_lq_lsu_ttype(mm_lq_lsu_ttype), + .mm_lq_lsu_wimge(mm_lq_lsu_wimge), + .mm_lq_lsu_u(mm_lq_lsu_u), + .mm_lq_lsu_addr(mm_lq_lsu_addr), + .mm_lq_lsu_lpid(mm_lq_lsu_lpid), + .mm_lq_lsu_gs(mm_lq_lsu_gs), + .mm_lq_lsu_ind(mm_lq_lsu_ind), + .mm_lq_lsu_lbit(mm_lq_lsu_lbit), + .mm_lq_lsu_lpidr(mm_lq_lsu_lpidr), + .lq_mm_lsu_token(lq_mm_lsu_token), + .mm_lq_hold_req(mm_iu_hold_req[0]), + .mm_lq_hold_done(mm_iu_hold_done[0]), + .mm_lq_pid_t0(mm_lq_t0_derat_pid), + .mm_lq_mmucr0_t0(mm_lq_t0_derat_mmucr0), +`ifndef THREADS1 + .mm_lq_pid_t1(mm_lq_t1_derat_pid), + .mm_lq_mmucr0_t1(mm_lq_t1_derat_mmucr0), +`endif + .mm_lq_mmucr1(mm_lq_derat_mmucr1), + .mm_lq_rel_val(mm_lq_derat_rel_val), + .mm_lq_rel_data(mm_lq_derat_rel_data), + .mm_lq_rel_emq(mm_lq_derat_rel_emq), + .mm_lq_itag(mm_lq_derat_rel_itag), + .mm_lq_tlb_miss(mm_xu_tlb_miss), + .mm_lq_tlb_inelig(mm_xu_tlb_inelig), + .mm_lq_pt_fault(mm_xu_pt_fault), + .mm_lq_lrat_miss(mm_xu_lrat_miss), + .mm_lq_tlb_multihit(mm_tlb_multihit_err), + .mm_lq_tlb_par_err(mm_tlb_par_err), + .mm_lq_lru_par_err(mm_lru_par_err), + .mm_lq_snoop_coming(mm_lq_derat_snoop_coming), + .mm_lq_snoop_val(mm_lq_derat_snoop_val), + .mm_lq_snoop_attr(mm_lq_derat_snoop_attr), + .mm_lq_snoop_vpn(mm_lq_derat_snoop_vpn), + .lq_mm_snoop_ack(lq_mm_derat_snoop_ack), + .lq_mm_req(lq_mm_derat_req), + .lq_mm_req_nonspec(lq_mm_derat_req_nonspec), + .lq_mm_req_itag(lq_mm_derat_req_itag), + .lq_mm_req_epn(lq_mm_derat_epn), + .lq_mm_thdid(lq_mm_derat_thdid), + .lq_mm_req_emq(lq_mm_derat_req_emq), + .lq_mm_ttype(lq_mm_derat_ttype), + .lq_mm_state(lq_mm_derat_state), + .lq_mm_lpid(lq_mm_derat_lpid), + .lq_mm_tid(lq_mm_derat_tid), + .lq_mm_mmucr0_we(lq_mm_derat_mmucr0_we), + .lq_mm_mmucr0(lq_mm_derat_mmucr0), + .lq_mm_mmucr1_we(lq_mm_derat_mmucr1_we), + .lq_mm_mmucr1(lq_mm_derat_mmucr1), + .lq_mm_lmq_stq_empty(lq_mm_lmq_stq_empty), + .lq_mm_perf_dtlb(lq_mm_perf_dtlb), + .lq_xu_quiesce(lq_xu_quiesce), + .lq_pc_ldq_quiesce(lq_pc_ldq_quiesce), + .lq_pc_stq_quiesce(lq_pc_stq_quiesce), + .lq_pc_pfetch_quiesce(lq_pc_pfetch_quiesce), + + //-------------------------------------------------------------- + // Interface with PC + //-------------------------------------------------------------- + .pc_lq_inj_dcachedir_ldp_parity(pc_lq_inj_dcachedir_ldp_parity), + .pc_lq_inj_dcachedir_ldp_multihit(pc_lq_inj_dcachedir_ldp_multihit), + .pc_lq_inj_dcachedir_stp_parity(pc_lq_inj_dcachedir_stp_parity), + .pc_lq_inj_dcachedir_stp_multihit(pc_lq_inj_dcachedir_stp_multihit), + .pc_lq_inj_dcache_parity(pc_lq_inj_dcache_parity), + .pc_lq_inj_relq_parity(pc_lq_inj_relq_parity), + .lq_pc_err_derat_parity(lq_pc_err_derat_parity), + .lq_pc_err_dir_ldp_parity(lq_pc_err_dcachedir_ldp_parity), + .lq_pc_err_dir_stp_parity(lq_pc_err_dcachedir_stp_parity), + .lq_pc_err_relq_parity(lq_pc_err_relq_parity), + .lq_pc_err_dcache_parity(lq_pc_err_dcache_parity), + .lq_pc_err_derat_multihit(lq_pc_err_derat_multihit), + .lq_pc_err_dir_ldp_multihit(lq_pc_err_dcachedir_ldp_multihit), + .lq_pc_err_dir_stp_multihit(lq_pc_err_dcachedir_stp_multihit), + .lq_pc_err_invld_reld(lq_pc_err_invld_reld), + .lq_pc_err_l2intrf_ecc(lq_pc_err_l2intrf_ecc), + .lq_pc_err_l2intrf_ue(lq_pc_err_l2intrf_ue), + .lq_pc_err_l2credit_overrun(lq_pc_err_l2credit_overrun), + .pc_lq_ram_active(pc_lq_ram_active), + .lq_pc_ram_data_val(lq_pc_ram_data_val), + .lq_pc_ram_data(lq_pc_ram_data), + .pc_lq_inj_prefetcher_parity(pc_lq_inj_prefetcher_parity), + .lq_pc_err_prefetcher_parity(lq_pc_err_prefetcher_parity), + + //-------------------------------------------------------------- + // Debug Bus Control + //-------------------------------------------------------------- + // Pervasive Debug Control + .pc_lq_trace_bus_enable(pc_lq_trace_bus_enable), + .pc_lq_debug_mux1_ctrls(pc_lq_debug_mux1_ctrls), + .pc_lq_debug_mux2_ctrls(pc_lq_debug_mux2_ctrls), + .pc_lq_instr_trace_mode(pc_lq_instr_trace_mode), + .pc_lq_instr_trace_tid(pc_lq_instr_trace_tid), + + // Pass Thru Debug Trace Bus + .debug_bus_in(lq_debug_bus_in), + .coretrace_ctrls_in(lq_coretrace_ctrls_in), + + .debug_bus_out(lq_debug_bus_out), + .coretrace_ctrls_out(lq_coretrace_ctrls_out), + + //-------------------------------------------------------------- + // Performance Event Control + //-------------------------------------------------------------- + .pc_lq_event_bus_enable(pc_lq_event_bus_enable), + .pc_lq_event_count_mode(pc_lq_event_count_mode), + .event_bus_in(lq_event_bus_in), + .event_bus_out(lq_event_bus_out), + + //-------------------------------------------------------------- + // Interface with L2 + //-------------------------------------------------------------- + .an_ac_coreid(an_ac_coreid[6:7]), + .an_ac_sync_ack(an_ac_sync_ack), + .an_ac_stcx_complete(an_ac_stcx_complete), + .an_ac_stcx_pass(an_ac_stcx_pass), + .an_ac_icbi_ack(an_ac_icbi_ack), + .an_ac_icbi_ack_thread(an_ac_icbi_ack_thread), + .an_ac_back_inv(an_ac_back_inv), + .an_ac_back_inv_addr(an_ac_back_inv_addr), + .an_ac_back_inv_target_bit1(an_ac_back_inv_target[1]), + .an_ac_back_inv_target_bit3(an_ac_back_inv_target[3]), + .an_ac_back_inv_target_bit4(an_ac_back_inv_target[4]), + .an_ac_flh2l2_gate(an_ac_flh2l2_gate), + .an_ac_req_ld_pop(an_ac_req_ld_pop), + .an_ac_req_st_pop(an_ac_req_st_pop), + .an_ac_req_st_gather(an_ac_req_st_gather), + .an_ac_reld_data_vld(an_ac_reld_data_vld), + .an_ac_reld_core_tag(an_ac_reld_core_tag), + .an_ac_reld_data(an_ac_reld_data), + .an_ac_reld_qw(an_ac_reld_qw), + .an_ac_reld_ecc_err(an_ac_reld_ecc_err), + .an_ac_reld_ecc_err_ue(an_ac_reld_ecc_err_ue), + .an_ac_reld_data_coming(an_ac_reld_data_coming), + .an_ac_reld_ditc(an_ac_reld_ditc), + .an_ac_reld_crit_qw(an_ac_reld_crit_qw), + .an_ac_reld_l1_dump(an_ac_reld_l1_dump), + .an_ac_req_spare_ctrl_a1(an_ac_req_spare_ctrl_a1), + .ac_an_req_pwr_token(ac_an_req_pwr_token), + .ac_an_req(ac_an_req), + .ac_an_req_ra(ac_an_req_ra), + .ac_an_req_ttype(ac_an_req_ttype), + .ac_an_req_thread(ac_an_req_thread), + .ac_an_req_wimg_w(ac_an_req_wimg_w), + .ac_an_req_wimg_i(ac_an_req_wimg_i), + .ac_an_req_wimg_m(ac_an_req_wimg_m), + .ac_an_req_wimg_g(ac_an_req_wimg_g), + .ac_an_req_user_defined(ac_an_req_user_defined), + .ac_an_req_spare_ctrl_a0(ac_an_req_spare_ctrl_a0), + .ac_an_req_ld_core_tag(ac_an_req_ld_core_tag), + .ac_an_req_ld_xfr_len(ac_an_req_ld_xfr_len), + .ac_an_st_byte_enbl(ac_an_st_byte_enbl), + .ac_an_st_data(ac_an_st_data), + .ac_an_req_endian(ac_an_req_endian), + .ac_an_st_data_pwr_token(ac_an_st_data_pwr_token), + + // Pervasive + //.vcs(vcs), + //.vdd(vdd), + //.gnd(gnd), + .nclk(nclk), + + //--Thold inputs + .pc_lq_init_reset(pc_lq_init_reset), + .pc_lq_ccflush_dc(rp_lq_ccflush_dc), + .pc_lq_gptr_sl_thold_3(rp_lq_gptr_sl_thold_3), + .pc_lq_time_sl_thold_3(rp_lq_time_sl_thold_3), + .pc_lq_repr_sl_thold_3(rp_lq_repr_sl_thold_3), + .pc_lq_bolt_sl_thold_3(1'b0), + .pc_lq_abst_sl_thold_3(rp_lq_abst_sl_thold_3), + .pc_lq_abst_slp_sl_thold_3(rp_lq_abst_slp_sl_thold_3), + .pc_lq_func_sl_thold_3(rp_lq_func_sl_thold_3), + .pc_lq_func_slp_sl_thold_3(rp_lq_func_slp_sl_thold_3), + .pc_lq_cfg_sl_thold_3(rp_lq_cfg_sl_thold_3), + .pc_lq_cfg_slp_sl_thold_3(rp_lq_cfg_slp_sl_thold_3), + .pc_lq_regf_slp_sl_thold_3(rp_lq_regf_slp_sl_thold_3), + .pc_lq_func_nsl_thold_3(rp_lq_func_nsl_thold_3), + .pc_lq_func_slp_nsl_thold_3(rp_lq_func_slp_nsl_thold_3), + .pc_lq_ary_nsl_thold_3(rp_lq_ary_nsl_thold_3), + .pc_lq_ary_slp_nsl_thold_3(rp_lq_ary_slp_nsl_thold_3), + .pc_lq_sg_3(rp_lq_sg_3), + .pc_lq_fce_3(rp_lq_fce_3), + + // G8T ABIST Control + .pc_lq_abist_wl64_comp_ena(1'b0), + .pc_lq_abist_g8t_wenb(1'b0), + .pc_lq_abist_g8t1p_renb_0(1'b0), + .pc_lq_abist_g8t_dcomp({4{1'b0}}), + .pc_lq_abist_g8t_bw_1(1'b0), + .pc_lq_abist_g8t_bw_0(1'b0), + .pc_lq_abist_di_0({4{1'b0}}), + .pc_lq_abist_waddr_0({8{1'b0}}), + + // G6T ABIST Control + .pc_lq_abist_ena_dc(1'b0), + .pc_lq_abist_raw_dc_b(1'b0), + .pc_lq_abist_g6t_bw({2{1'b0}}), + .pc_lq_abist_di_g6t_2r({4{1'b0}}), + .pc_lq_abist_wl256_comp_ena(1'b0), + .pc_lq_abist_dcomp_g6t_2r({4{1'b0}}), + .pc_lq_abist_raddr_0({8{1'b0}}), + .pc_lq_abist_g6t_r_wb(1'b0), + + .pc_lq_bo_enable_3(1'b0), + .pc_lq_bo_unload(1'b0), + .pc_lq_bo_repair(1'b0), + .pc_lq_bo_reset(1'b0), + .pc_lq_bo_shdata(1'b0), + .pc_lq_bo_select({14{1'b0}}), + .lq_pc_bo_fail(), + .lq_pc_bo_diagout(), + + // Core Level Signals + .an_ac_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc), + .an_ac_scan_dis_dc_b(an_ac_scan_dis_dc_b), + .an_ac_scan_diag_dc(an_ac_scan_diag_dc), + .an_ac_lbist_en_dc(an_ac_lbist_en_dc), + .an_ac_atpg_en_dc(1'b0), + .an_ac_grffence_en_dc(1'b0), + + + // SCAN + .gptr_scan_in(1'b0), + .gptr_scan_out(), + .abst_scan_in({6{1'b0}}), + .abst_scan_out(), + .time_scan_in(1'b0), + .time_scan_out(), + .repr_scan_in(1'b0), + .repr_scan_out(), + .regf_scan_in({7{1'b0}}), + .regf_scan_out(), + .ccfg_scan_in(1'b0), + .ccfg_scan_out(), + .func_scan_in(scan_in_lq), + .func_scan_out(scan_out_lq) + ); + + // 6=64-bit model, 5=32-bit model + mmq + mmu0( +// .vcs(vcs), +// .vdd(vdd), +// .gnd(gnd), + .nclk(nclk), + + .tc_ac_ccflush_dc(rp_mm_ccflush_dc), + .tc_ac_scan_dis_dc_b(an_ac_scan_dis_dc_b), + .tc_ac_scan_diag_dc(an_ac_scan_diag_dc), + .tc_ac_lbist_en_dc(1'b0), + .pc_mm_gptr_sl_thold_3(rp_mm_gptr_sl_thold_3), + .pc_mm_time_sl_thold_3(rp_mm_time_sl_thold_3), + .pc_mm_repr_sl_thold_3(rp_mm_repr_sl_thold_3), + .pc_mm_abst_sl_thold_3(rp_mm_abst_sl_thold_3), + .pc_mm_abst_slp_sl_thold_3(rp_mm_abst_slp_sl_thold_3), + .pc_mm_func_sl_thold_3(TEMP_rp_mm_func_sl_thold_3), + .pc_mm_func_slp_sl_thold_3(TEMP_rp_mm_func_slp_sl_thold_3), + .pc_mm_cfg_sl_thold_3(rp_mm_cfg_sl_thold_3), + .pc_mm_cfg_slp_sl_thold_3(rp_mm_cfg_slp_sl_thold_3), + .pc_mm_func_nsl_thold_3(rp_mm_func_nsl_thold_3), + .pc_mm_func_slp_nsl_thold_3(rp_mm_func_slp_nsl_thold_3), + .pc_mm_ary_nsl_thold_3(rp_mm_ary_nsl_thold_3), + .pc_mm_ary_slp_nsl_thold_3(rp_mm_ary_slp_nsl_thold_3), + .pc_mm_sg_3(TEMP_rp_mm_sg_3), + .pc_mm_fce_3(rp_mm_fce_3), + .debug_bus_in(mm_debug_bus_in), + .debug_bus_out(mm_debug_bus_out), + .coretrace_ctrls_in(mm_coretrace_ctrls_in), + .coretrace_ctrls_out(mm_coretrace_ctrls_out), + + .pc_mm_debug_mux1_ctrls(pc_mm_debug_mux_ctrls), + .pc_mm_trace_bus_enable(pc_mm_trace_bus_enable), + .pc_mm_event_count_mode(pc_mm_event_count_mode), + .rp_mm_event_bus_enable_q(pc_mm_event_bus_enable), + .mm_event_bus_in(mm_event_bus_in), + .mm_event_bus_out(mm_event_bus_out), + .an_ac_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc), + .pc_mm_abist_dcomp_g6t_2r({4{1'b0}}), + .pc_mm_abist_di_0({4{1'b0}}), + .pc_mm_abist_di_g6t_2r({4{1'b0}}), + .pc_mm_abist_ena_dc(1'b0), + .pc_mm_abist_g6t_r_wb(1'b0), + .pc_mm_abist_g8t1p_renb_0(1'b0), + .pc_mm_abist_g8t_bw_0(1'b0), + .pc_mm_abist_g8t_bw_1(1'b0), + .pc_mm_abist_g8t_dcomp({4{1'b0}}), + .pc_mm_abist_g8t_wenb(1'b0), + .pc_mm_abist_raddr_0({10{1'b0}}), + .pc_mm_abist_raw_dc_b(1'b0), + .pc_mm_abist_waddr_0({10{1'b0}}), + .pc_mm_abist_wl128_comp_ena(1'b0), + .pc_mm_bolt_sl_thold_3(1'b0), + .pc_mm_bo_enable_3(1'b0), + .pc_mm_bo_reset(1'b0), + .pc_mm_bo_unload(1'b0), + .pc_mm_bo_repair(1'b0), + .pc_mm_bo_shdata(1'b0), + .pc_mm_bo_select({5{1'b0}}), + .mm_pc_bo_fail(), + .mm_pc_bo_diagout(), + .iu_mm_ierat_req(iu_mm_ierat_req), + .iu_mm_ierat_req_nonspec(iu_mm_ierat_req_nonspec), + .iu_mm_ierat_epn(iu_mm_ierat_epn), + .iu_mm_ierat_thdid(iu_mm_ierat_thdid), + .iu_mm_ierat_state(iu_mm_ierat_state), + .iu_mm_ierat_tid(iu_mm_ierat_tid), + .iu_mm_ierat_flush({`THREADS{1'b0}}), + .mm_iu_ierat_snoop_coming(mm_iu_ierat_snoop_coming), + .mm_iu_ierat_rel_val(mm_iu_ierat_rel_val), + .mm_iu_ierat_rel_data(mm_iu_ierat_rel_data), + .mm_iu_ierat_snoop_val(mm_iu_ierat_snoop_val), + .mm_iu_ierat_snoop_attr(mm_iu_ierat_snoop_attr), + .mm_iu_ierat_snoop_vpn(mm_iu_ierat_snoop_vpn), + .iu_mm_ierat_snoop_ack(iu_mm_ierat_snoop_ack), + .mm_iu_t0_ierat_pid(mm_iu_t0_ierat_pid), + .mm_iu_t0_ierat_mmucr0(mm_iu_t0_ierat_mmucr0), +`ifndef THREADS1 + .mm_iu_t1_ierat_pid(mm_iu_t1_ierat_pid), + .mm_iu_t1_ierat_mmucr0(mm_iu_t1_ierat_mmucr0), +`endif + .iu_mm_ierat_mmucr0(iu_mm_ierat_mmucr0), + .iu_mm_ierat_mmucr0_we(iu_mm_ierat_mmucr0_we), + .mm_iu_ierat_mmucr1(mm_iu_ierat_mmucr1), + .mm_iu_tlbwe_binv(mm_iu_tlbwe_binv), + .iu_mm_ierat_mmucr1(iu_mm_ierat_mmucr1), + .iu_mm_ierat_mmucr1_we(iu_mm_ierat_mmucr1_we), + .xu_mm_derat_req(lq_mm_derat_req), + .xu_mm_derat_epn(lq_mm_derat_epn), + .xu_mm_derat_thdid(lq_mm_derat_thdid), + .xu_mm_derat_ttype(lq_mm_derat_ttype), + .xu_mm_derat_state(lq_mm_derat_state), + .xu_mm_derat_lpid(lq_mm_derat_lpid), + .xu_mm_derat_tid(lq_mm_derat_tid), + .lq_mm_derat_req_nonspec(lq_mm_derat_req_nonspec), + .lq_mm_derat_req_itag(lq_mm_derat_req_itag), + .lq_mm_derat_req_emq(lq_mm_derat_req_emq), + .mm_xu_derat_rel_val(mm_lq_derat_rel_val), + .mm_xu_derat_rel_data(mm_lq_derat_rel_data), + .mm_xu_derat_rel_itag(mm_lq_derat_rel_itag), + .mm_xu_derat_rel_emq(mm_lq_derat_rel_emq), + .mm_xu_derat_snoop_coming(mm_lq_derat_snoop_coming), + .mm_xu_derat_snoop_val(mm_lq_derat_snoop_val), + .mm_xu_derat_snoop_attr(mm_lq_derat_snoop_attr), + .mm_xu_derat_snoop_vpn(mm_lq_derat_snoop_vpn), + .xu_mm_derat_snoop_ack(lq_mm_derat_snoop_ack), + .mm_xu_t0_derat_pid(mm_lq_t0_derat_pid), + .mm_xu_t0_derat_mmucr0(mm_lq_t0_derat_mmucr0), +`ifndef THREADS1 + .mm_xu_t1_derat_pid(mm_lq_t1_derat_pid), + .mm_xu_t1_derat_mmucr0(mm_lq_t1_derat_mmucr0), +`endif + .xu_mm_derat_mmucr0(lq_mm_derat_mmucr0), + .xu_mm_derat_mmucr0_we(lq_mm_derat_mmucr0_we), + .mm_xu_derat_mmucr1(mm_lq_derat_mmucr1), + .xu_mm_derat_mmucr1(lq_mm_derat_mmucr1), + .xu_mm_derat_mmucr1_we(lq_mm_derat_mmucr1_we), + .xu_mm_rf1_val(xu_mm_val), + .xu_mm_rf1_is_tlbre(xu_mm_is_tlbre), + .xu_mm_rf1_is_tlbwe(xu_mm_is_tlbwe), + .xu_mm_rf1_is_tlbsx(xu_mm_is_tlbsx), + .xu_mm_rf1_is_tlbsxr(xu_mm_is_tlbsxr), + .xu_mm_rf1_is_tlbsrx(xu_mm_is_tlbsrx), + .xu_mm_rf1_is_tlbivax(xu_mm_is_tlbivax), + .xu_mm_rf1_is_tlbilx(xu_mm_is_tlbilx), + .xu_mm_rf1_is_erativax(xu_iu_is_erativax), + .xu_mm_rf1_is_eratilx(xu_iu_is_eratilx), + .xu_mm_ex1_is_isync(cp_is_isync), + .xu_mm_ex1_is_csync(cp_is_csync), + .xu_mm_rf1_t(xu_iu_t), + .xu_mm_ex1_rs_is(xu_iu_rs_is), + .xu_mm_ex2_eff_addr(xu_mm_rb), + .xu_mm_msr_gs(spr_msr_gs), + .xu_mm_msr_pr(spr_msr_pr), + .xu_mm_msr_is(spr_msr_is), + .xu_mm_msr_ds(spr_msr_ds), + .xu_mm_msr_cm(spr_msr_cm), + .xu_mm_spr_epcr_dmiuh(xu_mm_spr_epcr_dmiuh), + .xu_mm_spr_epcr_dgtmi(spr_epcr_dgtmi), + .xu_mm_hid_mmu_mode(spr_ccr2_notlb), + .xu_mm_xucr4_mmu_mchk(spr_xucr4_mmu_mchk), + .xu_mm_lmq_stq_empty(lq_mm_lmq_stq_empty), + .iu_mm_lmq_empty(iu_mm_lmq_empty), + + .xu_rf1_flush(cp_flush), + .xu_ex1_flush(cp_flush), + .xu_ex2_flush(cp_flush), + .xu_ex3_flush(cp_flush), + .xu_ex4_flush(cp_flush), + .xu_ex5_flush(cp_flush), + .xu_mm_ex4_flush(cp_flush), + .xu_mm_ex5_flush(cp_flush), + + .xu_mm_ierat_miss({`THREADS{1'b1}}), + .xu_mm_ierat_flush({`THREADS{1'b0}}), + .iu_mm_perf_itlb(iu_mm_perf_itlb), + .lq_mm_perf_dtlb(lq_mm_perf_dtlb), + .mm_xu_eratmiss_done(), + .mm_xu_cr0_eq(mm_xu_cr0_eq), + .mm_xu_cr0_eq_valid(mm_xu_cr0_eq_valid), + .mm_xu_tlb_miss(mm_xu_tlb_miss), + .mm_xu_lrat_miss(mm_xu_lrat_miss), + .mm_xu_tlb_inelig(mm_xu_tlb_inelig), + .mm_xu_pt_fault(mm_xu_pt_fault), + .mm_xu_hv_priv(mm_xu_hv_priv), + .mm_xu_illeg_instr(mm_xu_illeg_instr), + + .mm_xu_tlb_miss_ored(mm_xu_tlb_miss_ored), + .mm_xu_lrat_miss_ored(mm_xu_lrat_miss_ored), + .mm_xu_tlb_inelig_ored(mm_xu_tlb_inelig_ored), + .mm_xu_pt_fault_ored(mm_xu_pt_fault_ored), + .mm_xu_hv_priv_ored(mm_xu_hv_priv_ored), + .mm_xu_cr0_eq_ored(mm_xu_cr0_eq_ored), + .mm_xu_cr0_eq_valid_ored(mm_xu_cr0_eq_valid_ored), + + .mm_xu_esr_pt(), + .mm_xu_esr_data(), + .mm_xu_esr_epid(), + .mm_xu_esr_st(), + .mm_xu_quiesce(mm_xu_quiesce), + .mm_pc_tlb_req_quiesce(mm_pc_tlb_req_quiesce), + .mm_pc_tlb_ctl_quiesce(mm_pc_tlb_ctl_quiesce), + .mm_pc_htw_quiesce(mm_pc_htw_quiesce), + .mm_pc_inval_quiesce(mm_pc_inval_quiesce), + + .cp_mm_except_taken_t0(cp_mm_except_taken_t0), + `ifndef THREADS1 + .cp_mm_except_taken_t1(cp_mm_except_taken_t1), + `endif + + .mm_xu_tlb_multihit_err(mm_tlb_multihit_err), + .mm_xu_tlb_par_err(mm_tlb_par_err), + .mm_xu_lru_par_err(mm_lru_par_err), + .mm_xu_ord_tlb_multihit(mm_xu_ord_tlb_multihit), + .mm_xu_ord_tlb_par_err(mm_xu_ord_tlb_par_err), + .mm_xu_ord_lru_par_err(mm_xu_ord_lru_par_err), + .mm_xu_local_snoop_reject(mm_iu_local_snoop_reject), + + .mm_pc_tlb_multihit_err_ored(mm_pc_tlb_multihit_err_ored), + .mm_pc_tlb_par_err_ored(mm_pc_tlb_par_err_ored), + .mm_pc_lru_par_err_ored(mm_pc_lru_par_err_ored), + .mm_pc_local_snoop_reject_ored(mm_pc_local_snoop_reject_ored), + + .mm_xu_ex3_flush_req(), + .mm_xu_lsu_req(mm_lq_lsu_req), + .mm_xu_lsu_ttype(mm_lq_lsu_ttype), + .mm_xu_lsu_wimge(mm_lq_lsu_wimge), + .mm_xu_lsu_u(mm_lq_lsu_u), + .mm_xu_lsu_addr(mm_lq_lsu_addr), + .mm_xu_lsu_lpid(mm_lq_lsu_lpid), + .mm_xu_lsu_lpidr(mm_lq_lsu_lpidr), + .mm_xu_lsu_gs(mm_lq_lsu_gs), + .mm_xu_lsu_ind(mm_lq_lsu_ind), + .mm_xu_lsu_lbit(mm_lq_lsu_lbit), + .xu_mm_lsu_token(lq_mm_lsu_token), + .slowspr_val_in(mm_slowspr_val_in), + .slowspr_rw_in(mm_slowspr_rw_in), + .slowspr_etid_in(mm_slowspr_etid_in), + .slowspr_addr_in(mm_slowspr_addr_in), + .slowspr_data_in(mm_slowspr_data_in), + .slowspr_done_in(mm_slowspr_done_in), + .slowspr_val_out(mm_slowspr_val_out), + .slowspr_rw_out(mm_slowspr_rw_out), + .slowspr_etid_out(mm_slowspr_etid_out), + .slowspr_addr_out(mm_slowspr_addr_out), + .slowspr_data_out(mm_slowspr_data_out), + .slowspr_done_out(mm_slowspr_done_out), + + .gptr_scan_in(1'b0), + .time_scan_in(1'b0), + .repr_scan_in(1'b0), + .abst_scan_in({2{1'b0}}), + .func_scan_in({10{1'b0}}), + .bcfg_scan_in(1'b0), + .ccfg_scan_in(1'b0), + .dcfg_scan_in(1'b0), + .gptr_scan_out(), + .time_scan_out(), + .repr_scan_out(), + .abst_scan_out(), + .func_scan_out(), + .bcfg_scan_out(), + .ccfg_scan_out(), + .dcfg_scan_out(), + + .ac_an_power_managed_imm(ac_an_power_managed_int), + .an_ac_back_inv(an_ac_back_inv), + .an_ac_back_inv_target(an_ac_back_inv_target[2]), + .an_ac_back_inv_local(an_ac_back_inv_local), + .an_ac_back_inv_lbit(an_ac_back_inv_lbit), + .an_ac_back_inv_gs(an_ac_back_inv_gs), + .an_ac_back_inv_ind(an_ac_back_inv_ind), + .an_ac_back_inv_addr(an_ac_back_inv_addr), + .an_ac_back_inv_lpar_id(an_ac_back_inv_lpar_id), + .ac_an_back_inv_reject(ac_an_back_inv_reject), + .ac_an_lpar_id(ac_an_lpar_id), + .an_ac_reld_core_tag(an_ac_reld_core_tag), + .an_ac_reld_data(an_ac_reld_data), + .an_ac_reld_data_vld(an_ac_reld_data_vld), + .an_ac_reld_ecc_err(an_ac_reld_ecc_err), + .an_ac_reld_ecc_err_ue(an_ac_reld_ecc_err_ue), + .an_ac_reld_qw(an_ac_reld_qw), + .an_ac_reld_ditc(an_ac_reld_ditc), + .an_ac_reld_crit_qw(an_ac_reld_crit_qw), + + // some new a2o mmu sigs + .xu_mm_rf1_itag(xu_mm_itag), + .mm_xu_ord_n_flush_req(mm_xu_ord_n_flush_req), + .mm_xu_ord_np1_flush_req(mm_xu_ord_np1_flush_req), + .mm_xu_ord_read_done(mm_xu_ord_read_done), + .mm_xu_ord_write_done(mm_xu_ord_write_done), + .iu_mm_hold_ack(iu_mm_hold_ack), + .mm_iu_hold_req(mm_iu_hold_req), + .mm_iu_hold_done(mm_iu_hold_done), + .mm_iu_flush_req(mm_iu_flush_req), + .iu_mm_bus_snoop_hold_ack(iu_mm_bus_snoop_hold_ack), + .mm_iu_bus_snoop_hold_req(mm_iu_bus_snoop_hold_req), + .mm_iu_bus_snoop_hold_done(mm_iu_bus_snoop_hold_done), + .mm_iu_tlbi_complete(mm_iu_tlbi_complete), + .mm_xu_illeg_instr_ored(mm_xu_illeg_instr_ored), + .mm_xu_ord_n_flush_req_ored(mm_xu_ord_n_flush_req_ored), + .mm_xu_ord_np1_flush_req_ored(mm_xu_ord_np1_flush_req_ored), // out std_ulogic_vector(0 to thdid_width-1); + .mm_xu_ord_read_done_ored(mm_xu_ord_read_done_ored), + .mm_xu_ord_write_done_ored(mm_xu_ord_write_done_ored), + + .mm_xu_itag(mm_xu_itag) + + ); + + + c_fu_pc #(.float_type(float_type)) + fupc( + // .vdd(vdd), + // .gnd(gnd), + .nclk(nclk), + + .fu_debug_bus_in(fu_debug_bus_in), + .fu_debug_bus_out(fu_debug_bus_out), + .fu_coretrace_ctrls_in(fu_coretrace_ctrls_in), + .fu_coretrace_ctrls_out(fu_coretrace_ctrls_out), + .fu_event_bus_in(fu_event_bus_in), + .fu_event_bus_out(fu_event_bus_out), + + .pc_debug_bus_in(pc_debug_bus_in), + .pc_debug_bus_out(pc_debug_bus_out), + .pc_coretrace_ctrls_in(pc_coretrace_ctrls_in), + .pc_coretrace_ctrls_out(pc_coretrace_ctrls_out), + + .fu_gptr_scan_in(1'b0), + .fu_time_scan_in(1'b0), + .fu_repr_scan_in(1'b0), + .fu_bcfg_scan_in(1'b0), + .fu_ccfg_scan_in(1'b0), + .fu_dcfg_scan_in(1'b0), + .fu_func_scan_in({4{1'b0}}), + .fu_abst_scan_in(1'b0), + .fu_gptr_scan_out(), + .fu_time_scan_out(), + .fu_repr_scan_out(), + .fu_bcfg_scan_out(), + .fu_ccfg_scan_out(), + .fu_dcfg_scan_out(), + .fu_func_scan_out(), + .fu_abst_scan_out(), + + .pc_gptr_scan_in(1'b0), + .pc_ccfg_scan_in(1'b0), + .pc_bcfg_scan_in(1'b0), + .pc_dcfg_scan_in(1'b0), + .pc_func_scan_in(2'b00), + .pc_gptr_scan_out(), + .pc_ccfg_scan_out(), + .pc_bcfg_scan_out(), + .pc_dcfg_scan_out(), + .pc_func_scan_out(), + + .cp_flush(cp_flush), + .fu_slowspr_addr_in(fu_slowspr_addr_in), + .fu_slowspr_data_in(fu_slowspr_data_in), + .fu_slowspr_done_in(fu_slowspr_done_in), + .fu_slowspr_etid_in(fu_slowspr_etid_in), + .fu_slowspr_rw_in(fu_slowspr_rw_in), + .fu_slowspr_val_in(fu_slowspr_val_in), + .fu_slowspr_addr_out(fu_slowspr_addr_out), + .fu_slowspr_data_out(fu_slowspr_data_out), + .fu_slowspr_done_out(fu_slowspr_done_out), + .fu_slowspr_etid_out(fu_slowspr_etid_out), + .fu_slowspr_rw_out(fu_slowspr_rw_out), + .fu_slowspr_val_out(fu_slowspr_val_out), + + .pc_slowspr_addr_in(pc_slowspr_addr_in), + .pc_slowspr_data_in(pc_slowspr_data_in), + .pc_slowspr_done_in(pc_slowspr_done_in), + .pc_slowspr_etid_in(pc_slowspr_etid_in), + .pc_slowspr_rw_in(pc_slowspr_rw_in), + .pc_slowspr_val_in(pc_slowspr_val_in), + .pc_slowspr_addr_out(pc_slowspr_addr_out), + .pc_slowspr_data_out(pc_slowspr_data_out), + .pc_slowspr_done_out(pc_slowspr_done_out), + .pc_slowspr_etid_out(pc_slowspr_etid_out), + .pc_slowspr_rw_out(pc_slowspr_rw_out), + .pc_slowspr_val_out(pc_slowspr_val_out), + + // FU Interface + .cp_t0_next_itag(cp_t0_next_itag), + .cp_t1_next_itag(cp_t1_next_itag), + .cp_axu_i0_t1_v(cp_axu_i0_t1_v), + .cp_axu_i0_t0_t1_t(cp_axu_t0_i0_t1_t), + .cp_axu_i0_t0_t1_p(cp_axu_t0_i0_t1_p), + .cp_axu_i0_t1_t1_t(cp_axu_t1_i0_t1_t), + .cp_axu_i0_t1_t1_p(cp_axu_t1_i0_t1_p), + .cp_axu_i1_t1_v(cp_axu_i1_t1_v), + .cp_axu_i1_t0_t1_t(cp_axu_t0_i1_t1_t), + .cp_axu_i1_t0_t1_p(cp_axu_t0_i1_t1_p), + .cp_axu_i1_t1_t1_t(cp_axu_t1_i1_t1_t), + .cp_axu_i1_t1_t1_p(cp_axu_t1_i1_t1_p), + + .iu_xx_t0_zap_itag(cp_t0_flush_itag), + .iu_xx_t1_zap_itag(cp_t1_flush_itag), + .axu0_iu_async_fex(axu0_iu_async_fex), + .axu0_iu_perf_events(axu0_iu_perf_events), + .axu0_iu_exception(axu0_iu_exception), + .axu0_iu_exception_val(axu0_iu_exception_val), + .axu0_iu_execute_vld(axu0_iu_execute_vld), + .axu0_iu_flush2ucode(axu0_iu_flush2ucode), + .axu0_iu_flush2ucode_type(axu0_iu_flush2ucode_type), + .axu0_iu_itag(axu0_iu_itag), + .axu0_iu_n_flush(axu0_iu_n_flush), + .axu0_iu_n_np1_flush(axu0_iu_n_np1_flush), + .axu0_iu_np1_flush(axu0_iu_np1_flush), + .axu1_iu_perf_events(axu1_iu_perf_events), + .axu1_iu_exception(axu1_iu_exception), + .axu1_iu_exception_val(axu1_iu_exception_val), + .axu1_iu_execute_vld(axu1_iu_execute_vld), + .axu1_iu_flush2ucode(axu1_iu_flush2ucode), + .axu1_iu_flush2ucode_type(axu1_iu_flush2ucode_type), + .axu1_iu_itag(axu1_iu_itag), + .axu1_iu_n_flush(axu1_iu_n_flush), + .axu1_iu_np1_flush(axu1_iu_np1_flush), + + .lq_fu_ex4_eff_addr(xu_axu_lq_ex4_addr), + .lq_fu_ex5_load_le(xu_axu_lq_ex5_le), + .lq_fu_ex5_load_data(xu_axu_lq_ex5_wd), + .lq_fu_ex5_load_tag(xu_axu_lq_ex5_wa), + .lq_fu_ex5_load_val(xu_axu_lq_ex5_we), + .lq_fu_ex5_abort(xu_axu_lq_ex5_abort), + .lq_gpr_rel_we(xu_axu_lq_rel_we), + .lq_gpr_rel_le(xu_axu_lq_rel_le), + .lq_gpr_rel_wa(xu_axu_lq_rel_wa), + .lq_gpr_rel_wd(xu_axu_lq_rel_wd[64:127]), // Fix me + .lq_rv_itag0(lq_rv_itag0), + .lq_rv_itag0_vld(lq_rv_itag0_vld[0]), + .lq_rv_itag0_spec(lq_rv_itag0_spec), + .lq_rv_itag1_restart(lq_rv_itag1_restart), + .fu_lq_ex2_store_data_val(axu_xu_lq_ex_stq_val), + .fu_lq_ex2_store_itag(axu_xu_lq_ex_stq_itag), + .fu_lq_ex3_store_data(axu_xu_lq_exp1_stq_data), + .fu_lq_ex3_sto_parity_err(axu_xu_lq_exp1_sto_parity_err), + .fu_lq_ex3_abort(fu_lq_ex3_abort), + + .rv_axu0_vld(rv_axu0_vld), + .rv_axu0_ex0_instr(rv_axu0_ex0_instr), + .rv_axu0_ex0_itag(rv_axu0_ex0_itag), + .rv_axu0_ex0_ucode(rv_axu0_ex0_ucode), + .rv_axu0_ex0_t1_v(rv_axu0_ex0_t1_v), + .rv_axu0_ex0_t1_p(rv_axu0_ex0_t1_p), + .rv_axu0_ex0_t2_p(rv_axu0_ex0_t2_p), + .rv_axu0_ex0_t3_p(rv_axu0_ex0_t3_p), + .rv_axu0_s1_v(rv_axu0_s1_v), + .rv_axu0_s1_p(rv_axu0_s1_p), + .rv_axu0_s1_t(rv_axu0_s1_t), + .rv_axu0_s2_v(rv_axu0_s2_v), + .rv_axu0_s2_p(rv_axu0_s2_p), + .rv_axu0_s2_t(rv_axu0_s2_t), + .rv_axu0_s3_v(rv_axu0_s3_v), + .rv_axu0_s3_p(rv_axu0_s3_p), + .rv_axu0_s3_t(rv_axu0_s3_t), + .axu0_rv_ex2_s1_abort(axu0_rv_ex2_s1_abort), + .axu0_rv_ex2_s2_abort(axu0_rv_ex2_s2_abort), + .axu0_rv_ex2_s3_abort(axu0_rv_ex2_s3_abort), + .axu0_rv_itag(axu0_rv_itag), + .axu0_rv_itag_vld(axu0_rv_itag_vld), + .axu0_rv_itag_abort(axu0_rv_itag_abort), + .axu0_rv_ord_complete(axu0_rv_ord_complete), + .axu0_rv_hold_all(axu0_rv_hold_all), + .axu1_rv_itag(axu1_rv_itag), + .axu1_rv_itag_vld(axu1_rv_itag_vld), + .axu1_rv_itag_abort(axu1_rv_itag_abort), + .axu1_rv_hold_all(axu1_rv_hold_all), + + .pc_fu_abist_di_0({4{1'b0}}), + .pc_fu_abist_di_1({4{1'b0}}), + .pc_fu_abist_ena_dc(1'b0), + .pc_fu_abist_grf_renb_0(1'b0), + .pc_fu_abist_grf_renb_1(1'b0), + .pc_fu_abist_grf_wenb_0(1'b0), + .pc_fu_abist_grf_wenb_1(1'b0), + .pc_fu_abist_raddr_0({10{1'b0}}), + .pc_fu_abist_raddr_1({10{1'b0}}), + .pc_fu_abist_raw_dc_b(1'b0), + .pc_fu_abist_waddr_0({10{1'b0}}), + .pc_fu_abist_waddr_1({10{1'b0}}), + .pc_fu_abist_wl144_comp_ena(1'b0), + + .xu_fu_msr_fe0(spr_msr_fe0), + .xu_fu_msr_fe1(spr_msr_fe1), + .xu_fu_msr_fp(spr_msr_fp), + .xu_fu_msr_gs(spr_msr_gs), + .xu_fu_msr_pr(spr_msr_pr), + .axu0_cr_w4e(axu0_cr_w4e), + .axu0_cr_w4a(axu0_cr_w4a), + .axu0_cr_w4d(axu0_cr_w4d), + + + // PC Interface + // SCOM Satellite + .an_ac_scom_sat_id(an_ac_scom_sat_id), + .an_ac_scom_dch(rp_pc_scom_dch_q), + .an_ac_scom_cch(rp_pc_scom_cch_q), + .ac_an_scom_dch(pc_rp_scom_dch), + .ac_an_scom_cch(pc_rp_scom_cch), + // FIR and Error Signals + .ac_an_special_attn(pc_rp_special_attn), + .ac_an_checkstop(pc_rp_checkstop), + .ac_an_local_checkstop(pc_rp_local_checkstop), + .ac_an_recov_err(pc_rp_recov_err), + .ac_an_trace_error(pc_rp_trace_error), + .ac_an_livelock_active(pc_rp_livelock_active), + .an_ac_checkstop(rp_pc_checkstop_q), + .iu_pc_err_attention_instr(iu_pc_err_attention_instr), + .iu_pc_err_icache_parity(iu_pc_err_icache_parity), + .iu_pc_err_icachedir_parity(iu_pc_err_icachedir_parity), + .iu_pc_err_icachedir_multihit(iu_pc_err_icachedir_multihit), + .iu_pc_err_ierat_parity(iu_pc_err_ierat_parity), + .iu_pc_err_ierat_multihit(iu_pc_err_ierat_multihit), + .iu_pc_err_btb_parity(iu_pc_err_btb_parity), + .iu_pc_err_cpArray_parity(iu_pc_err_cpArray_parity), + .iu_pc_err_ucode_illegal(iu_pc_err_ucode_illegal), + .iu_pc_err_mchk_disabled(iu_pc_err_mchk_disabled), + .iu_pc_err_debug_event(iu_pc_err_debug_event), + .lq_pc_err_dcache_parity(lq_pc_err_dcache_parity), + .lq_pc_err_dcachedir_ldp_parity(lq_pc_err_dcachedir_ldp_parity), + .lq_pc_err_dcachedir_stp_parity(lq_pc_err_dcachedir_stp_parity), + .lq_pc_err_dcachedir_ldp_multihit(lq_pc_err_dcachedir_ldp_multihit), + .lq_pc_err_dcachedir_stp_multihit(lq_pc_err_dcachedir_stp_multihit), + .lq_pc_err_derat_parity(lq_pc_err_derat_parity), + .lq_pc_err_derat_multihit(lq_pc_err_derat_multihit), + .lq_pc_err_l2intrf_ecc(lq_pc_err_l2intrf_ecc), + .lq_pc_err_l2intrf_ue(lq_pc_err_l2intrf_ue), + .lq_pc_err_invld_reld(lq_pc_err_invld_reld), + .lq_pc_err_l2credit_overrun(lq_pc_err_l2credit_overrun), + .lq_pc_err_regfile_parity(lq_pc_err_regfile_parity), + .lq_pc_err_regfile_ue(lq_pc_err_regfile_ue), + .lq_pc_err_prefetcher_parity(lq_pc_err_prefetcher_parity), + .lq_pc_err_relq_parity(lq_pc_err_relq_parity), + .mm_pc_err_tlb_parity(mm_pc_tlb_par_err_ored), + .mm_pc_err_tlb_multihit(mm_pc_tlb_multihit_err_ored), + .mm_pc_err_tlb_lru_parity(mm_pc_lru_par_err_ored), + .mm_pc_err_local_snoop_reject(mm_pc_local_snoop_reject_ored), + .xu_pc_err_sprg_ecc(xu_pc_err_sprg_ecc), + .xu_pc_err_sprg_ue(xu_pc_err_sprg_ue), + .xu_pc_err_regfile_parity(xu_pc_err_regfile_parity), + .xu_pc_err_regfile_ue(xu_pc_err_regfile_ue), + .xu_pc_err_llbust_attempt(xu_pc_err_llbust_attempt), + .xu_pc_err_llbust_failed(xu_pc_err_llbust_failed), + .xu_pc_err_wdt_reset(xu_pc_err_wdt_reset), + .pc_iu_inj_icache_parity(pc_iu_inj_icache_parity), + .pc_iu_inj_icachedir_parity(pc_iu_inj_icachedir_parity), + .pc_iu_inj_icachedir_multihit(pc_iu_inj_icachedir_multihit), + .pc_iu_inj_cpArray_parity(pc_iu_inj_cpArray_parity), + .pc_lq_inj_dcache_parity(pc_lq_inj_dcache_parity), + .pc_lq_inj_dcachedir_ldp_parity(pc_lq_inj_dcachedir_ldp_parity), + .pc_lq_inj_dcachedir_stp_parity(pc_lq_inj_dcachedir_stp_parity), + .pc_lq_inj_dcachedir_ldp_multihit(pc_lq_inj_dcachedir_ldp_multihit), + .pc_lq_inj_dcachedir_stp_multihit(pc_lq_inj_dcachedir_stp_multihit), + .pc_lq_inj_prefetcher_parity(pc_lq_inj_prefetcher_parity), + .pc_lq_inj_regfile_parity(pc_lq_inj_regfile_parity), + .pc_lq_inj_relq_parity(pc_lq_inj_relq_parity), + .pc_fx0_inj_regfile_parity(pc_fx0_inj_regfile_parity), + .pc_fx1_inj_regfile_parity(pc_fx1_inj_regfile_parity), + .pc_xu_inj_sprg_ecc(pc_xu_inj_sprg_ecc), + .pc_xu_inj_llbust_attempt(pc_xu_inj_llbust_attempt), + .pc_xu_inj_llbust_failed(pc_xu_inj_llbust_failed), + // Unit quiesce and credit status bits + .iu_pc_quiesce(iu_pc_quiesce), + .iu_pc_icache_quiesce(iu_pc_icache_quiesce), + .lq_pc_ldq_quiesce(lq_pc_ldq_quiesce), + .lq_pc_stq_quiesce(lq_pc_stq_quiesce), + .lq_pc_pfetch_quiesce(lq_pc_pfetch_quiesce), + .mm_pc_tlb_req_quiesce(mm_pc_tlb_req_quiesce), + .mm_pc_tlb_ctl_quiesce(mm_pc_tlb_ctl_quiesce), + .mm_pc_htw_quiesce(mm_pc_htw_quiesce), + .mm_pc_inval_quiesce(mm_pc_inval_quiesce), + .iu_pc_fx0_credit_ok(iu_pc_fx0_credit_ok), + .iu_pc_fx1_credit_ok(iu_pc_fx1_credit_ok), + .iu_pc_axu0_credit_ok(iu_pc_axu0_credit_ok), + .iu_pc_axu1_credit_ok(iu_pc_axu1_credit_ok), + .iu_pc_lq_credit_ok(iu_pc_lq_credit_ok), + .iu_pc_sq_credit_ok(iu_pc_sq_credit_ok), + // RAM Command/Data + .pc_iu_ram_instr(pc_iu_ram_instr), + .pc_iu_ram_instr_ext(pc_iu_ram_instr_ext), + .pc_iu_ram_active(pc_iu_ram_active), + .pc_iu_ram_issue(pc_iu_ram_issue), + .iu_pc_ram_done(iu_pc_ram_done), + .iu_pc_ram_interrupt(iu_pc_ram_interrupt), + .iu_pc_ram_unsupported(iu_pc_ram_unsupported), + .pc_xu_ram_active(pc_xu_ram_active), + .xu_pc_ram_data_val(xu_pc_ram_data_val), + .xu_pc_ram_data(xu_pc_ram_data), + .pc_lq_ram_active(pc_lq_ram_active), + .lq_pc_ram_data_val(lq_pc_ram_data_val), + .lq_pc_ram_data(lq_pc_ram_data), + .pc_xu_msrovride_enab(pc_xu_msrovride_enab), + .pc_xu_msrovride_pr(pc_xu_msrovride_pr), + .pc_xu_msrovride_gs(pc_xu_msrovride_gs), + .pc_xu_msrovride_de(pc_xu_msrovride_de), + .pc_iu_ram_force_cmplt(), + .pc_iu_ram_flush_thread(pc_iu_ram_flush_thread), + // THRCTL + PCCR0 Registers + .an_ac_debug_stop(rp_pc_debug_stop_q), + .xu_pc_running(xu_pc_running), + .iu_pc_stop_dbg_event(iu_pc_stop_dbg_event), + .xu_pc_stop_dnh_instr(xu_pc_stop_dnh_instr), + .iu_pc_step_done(iu_pc_step_done), + .pc_iu_stop(pc_iu_stop), + .pc_iu_step(pc_iu_step), + .pc_xu_extirpts_dis_on_stop(pc_xu_extirpts_dis_on_stop), + .pc_xu_timebase_dis_on_stop(pc_xu_timebase_dis_on_stop), + .pc_xu_decrem_dis_on_stop(pc_xu_decrem_dis_on_stop), + .pc_iu_dbg_action(pc_iu_dbg_action_int), + .pc_iu_spr_dbcr0_edm(pc_iu_spr_dbcr0_edm), + .pc_xu_spr_dbcr0_edm(pc_xu_spr_dbcr0_edm), + // Debug Bus Controls + .pc_iu_trace_bus_enable(pc_iu_trace_bus_enable), + .pc_rv_trace_bus_enable(pc_rv_trace_bus_enable), + .pc_mm_trace_bus_enable(pc_mm_trace_bus_enable), + .pc_xu_trace_bus_enable(pc_xu_trace_bus_enable), + .pc_lq_trace_bus_enable(pc_lq_trace_bus_enable), + .pc_iu_debug_mux1_ctrls(pc_iu_debug_mux1_ctrls), + .pc_iu_debug_mux2_ctrls(pc_iu_debug_mux2_ctrls), + .pc_rv_debug_mux_ctrls(pc_rv_debug_mux_ctrls), + .pc_mm_debug_mux_ctrls(pc_mm_debug_mux_ctrls), + .pc_xu_debug_mux_ctrls(pc_xu_debug_mux_ctrls), + .pc_lq_debug_mux1_ctrls(pc_lq_debug_mux1_ctrls), + .pc_lq_debug_mux2_ctrls(pc_lq_debug_mux2_ctrls), + // Event Bus Controls + .pc_rv_event_mux_ctrls(pc_rv_event_mux_ctrls), + .pc_iu_event_bus_enable(pc_iu_event_bus_enable), + .pc_rv_event_bus_enable(pc_rv_event_bus_enable), + .pc_mm_event_bus_enable(pc_mm_event_bus_enable), + .pc_xu_event_bus_enable(pc_xu_event_bus_enable), + .pc_lq_event_bus_enable(pc_lq_event_bus_enable), + .pc_iu_event_count_mode(pc_iu_event_count_mode), + .pc_rv_event_count_mode(pc_rv_event_count_mode), + .pc_mm_event_count_mode(pc_mm_event_count_mode), + .pc_xu_event_count_mode(pc_xu_event_count_mode), + .pc_lq_event_count_mode(pc_lq_event_count_mode), + .pc_iu_instr_trace_mode(pc_iu_instr_trace_mode), + .pc_iu_instr_trace_tid(pc_iu_instr_trace_tid[0]), + .pc_lq_instr_trace_mode(pc_lq_instr_trace_mode), + .pc_lq_instr_trace_tid(pc_lq_instr_trace_tid[0]), + .pc_xu_instr_trace_mode(pc_xu_instr_trace_mode), + .pc_xu_instr_trace_tid(pc_xu_instr_trace_tid[0]), + .xu_pc_perfmon_alert(xu_pc_perfmon_alert), + .pc_xu_spr_cesr1_pmae(pc_xu_spr_cesr1_pmae), + .pc_lq_event_bus_seldbghi(pc_lq_event_bus_seldbghi), + .pc_lq_event_bus_seldbglo(pc_lq_event_bus_seldbglo), + // Reset related + .pc_lq_init_reset(pc_lq_init_reset), + .pc_iu_init_reset(pc_iu_init_reset), + // Power Management + .ac_an_pm_thread_running(pc_rp_pm_thread_running), + .an_ac_pm_thread_stop(rp_pc_pm_thread_stop_q), + .an_ac_pm_fetch_halt(rp_pc_pm_fetch_halt_q), + .pc_iu_pm_fetch_halt(pc_iu_pm_fetch_halt), + .ac_an_power_managed(pc_rp_power_managed), + .ac_an_rvwinkle_mode(pc_rp_rvwinkle_mode), + .pc_xu_pm_hold_thread(pc_xu_pm_hold_thread), + .xu_pc_spr_ccr0_pme(xu_pc_spr_ccr0_pme), + .xu_pc_spr_ccr0_we(xu_pc_spr_ccr0_we), + // Clock, Test, and LCB Controls + .an_ac_gsd_test_enable_dc(an_ac_gsd_test_enable_dc), + .an_ac_gsd_test_acmode_dc(an_ac_gsd_test_acmode_dc), + .an_ac_ccflush_dc(an_ac_ccflush_dc), + .an_ac_ccenable_dc(an_ac_ccenable_dc), + .an_ac_lbist_en_dc(an_ac_lbist_en_dc), + .an_ac_lbist_ip_dc(an_ac_lbist_ip_dc), + .an_ac_lbist_ac_mode_dc(an_ac_lbist_ac_mode_dc), + .an_ac_scan_diag_dc(an_ac_scan_diag_dc), + .an_ac_scan_dis_dc_b(an_ac_scan_dis_dc_b), + .an_ac_rtim_sl_thold_7(rp_pc_rtim_sl_thold_7), + .an_ac_func_sl_thold_7(rp_pc_func_sl_thold_7), + .an_ac_func_nsl_thold_7(rp_pc_func_nsl_thold_7), + .an_ac_ary_nsl_thold_7(rp_pc_ary_nsl_thold_7), + .an_ac_sg_7(rp_pc_sg_7), + .an_ac_fce_7(rp_pc_fce_7), + .an_ac_scan_type_dc(an_ac_scan_type_dc), + // Thold outputs to clock staging + .pc_rp_ccflush_out_dc(pc_rp_ccflush_out_dc), + .pc_rp_gptr_sl_thold_4(pc_rp_gptr_sl_thold_4), + .pc_rp_time_sl_thold_4(pc_rp_time_sl_thold_4), + .pc_rp_repr_sl_thold_4(pc_rp_repr_sl_thold_4), + .pc_rp_abst_sl_thold_4(pc_rp_abst_sl_thold_4), + .pc_rp_abst_slp_sl_thold_4(pc_rp_abst_slp_sl_thold_4), + .pc_rp_regf_sl_thold_4(pc_rp_regf_sl_thold_4), + .pc_rp_regf_slp_sl_thold_4(pc_rp_regf_slp_sl_thold_4), + .pc_rp_func_sl_thold_4(pc_rp_func_sl_thold_4), + .pc_rp_func_slp_sl_thold_4(pc_rp_func_slp_sl_thold_4), + .pc_rp_cfg_sl_thold_4(pc_rp_cfg_sl_thold_4), + .pc_rp_cfg_slp_sl_thold_4(pc_rp_cfg_slp_sl_thold_4), + .pc_rp_func_nsl_thold_4(pc_rp_func_nsl_thold_4), + .pc_rp_func_slp_nsl_thold_4(pc_rp_func_slp_nsl_thold_4), + .pc_rp_ary_nsl_thold_4(pc_rp_ary_nsl_thold_4), + .pc_rp_ary_slp_nsl_thold_4(pc_rp_ary_slp_nsl_thold_4), + .pc_rp_rtim_sl_thold_4(pc_rp_rtim_sl_thold_4), + .pc_rp_sg_4(pc_rp_sg_4), + .pc_rp_fce_4(pc_rp_fce_4) + ); + + //%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + + c_perv_rp + perv_rp( +// .vdd(vdd), +// .gnd(gnd), + .nclk(nclk), + + //CLOCK CONTROLS + //Top level clock controls + .an_ac_ccflush_dc(an_ac_ccflush_dc), + .rtim_sl_thold_8(an_ac_rtim_sl_thold_8), + .func_sl_thold_8(an_ac_func_sl_thold_8), + .func_nsl_thold_8(an_ac_func_nsl_thold_8), + .ary_nsl_thold_8(an_ac_ary_nsl_thold_8), + .sg_8(an_ac_sg_8), + .fce_8(an_ac_fce_8), + .rtim_sl_thold_7(rp_pc_rtim_sl_thold_7), + .func_sl_thold_7(rp_pc_func_sl_thold_7), + .func_nsl_thold_7(rp_pc_func_nsl_thold_7), + .ary_nsl_thold_7(rp_pc_ary_nsl_thold_7), + .sg_7(rp_pc_sg_7), + .fce_7(rp_pc_fce_7), + //Thold inputs from pcq clock controls + .pc_rp_ccflush_out_dc(pc_rp_ccflush_out_dc), + .pc_rp_gptr_sl_thold_4(pc_rp_gptr_sl_thold_4), + .pc_rp_time_sl_thold_4(pc_rp_time_sl_thold_4), + .pc_rp_repr_sl_thold_4(pc_rp_repr_sl_thold_4), + .pc_rp_abst_sl_thold_4(pc_rp_abst_sl_thold_4), + .pc_rp_abst_slp_sl_thold_4(pc_rp_abst_slp_sl_thold_4), + .pc_rp_regf_sl_thold_4(pc_rp_regf_sl_thold_4), + .pc_rp_regf_slp_sl_thold_4(pc_rp_regf_slp_sl_thold_4), + .pc_rp_func_sl_thold_4(pc_rp_func_sl_thold_4), + .pc_rp_func_slp_sl_thold_4(pc_rp_func_slp_sl_thold_4), + .pc_rp_cfg_sl_thold_4(pc_rp_cfg_sl_thold_4), + .pc_rp_cfg_slp_sl_thold_4(pc_rp_cfg_slp_sl_thold_4), + .pc_rp_func_nsl_thold_4(pc_rp_func_nsl_thold_4), + .pc_rp_func_slp_nsl_thold_4(pc_rp_func_slp_nsl_thold_4), + .pc_rp_ary_nsl_thold_4(pc_rp_ary_nsl_thold_4), + .pc_rp_ary_slp_nsl_thold_4(pc_rp_ary_slp_nsl_thold_4), + .pc_rp_rtim_sl_thold_4(pc_rp_rtim_sl_thold_4), + .pc_rp_sg_4(pc_rp_sg_4), + .pc_rp_fce_4(pc_rp_fce_4), + //Thold outputs to the units + .rp_iu_ccflush_dc(rp_iu_ccflush_dc), + .rp_iu_gptr_sl_thold_3(rp_iu_gptr_sl_thold_3), + .rp_iu_time_sl_thold_3(rp_iu_time_sl_thold_3), + .rp_iu_repr_sl_thold_3(rp_iu_repr_sl_thold_3), + .rp_iu_abst_sl_thold_3(rp_iu_abst_sl_thold_3), + .rp_iu_abst_slp_sl_thold_3(rp_iu_abst_slp_sl_thold_3), + .rp_iu_regf_slp_sl_thold_3(rp_iu_regf_slp_sl_thold_3), + .rp_iu_func_sl_thold_3(rp_iu_func_sl_thold_3), + .rp_iu_func_slp_sl_thold_3(rp_iu_func_slp_sl_thold_3), + .rp_iu_cfg_sl_thold_3(rp_iu_cfg_sl_thold_3), + .rp_iu_cfg_slp_sl_thold_3(rp_iu_cfg_slp_sl_thold_3), + .rp_iu_func_nsl_thold_3(rp_iu_func_nsl_thold_3), + .rp_iu_func_slp_nsl_thold_3(rp_iu_func_slp_nsl_thold_3), + .rp_iu_ary_nsl_thold_3(rp_iu_ary_nsl_thold_3), + .rp_iu_ary_slp_nsl_thold_3(rp_iu_ary_slp_nsl_thold_3), + .rp_iu_sg_3(rp_iu_sg_3), + .rp_iu_fce_3(rp_iu_fce_3), + // + .rp_rv_ccflush_dc(rp_rv_ccflush_dc), + .rp_rv_gptr_sl_thold_3(rp_rv_gptr_sl_thold_3), + .rp_rv_time_sl_thold_3(rp_rv_time_sl_thold_3), + .rp_rv_repr_sl_thold_3(rp_rv_repr_sl_thold_3), + .rp_rv_abst_sl_thold_3(rp_rv_abst_sl_thold_3), + .rp_rv_abst_slp_sl_thold_3(rp_rv_abst_slp_sl_thold_3), + .rp_rv_func_sl_thold_3(rp_rv_func_sl_thold_3), + .rp_rv_func_slp_sl_thold_3(rp_rv_func_slp_sl_thold_3), + .rp_rv_cfg_sl_thold_3(rp_rv_cfg_sl_thold_3), + .rp_rv_cfg_slp_sl_thold_3(rp_rv_cfg_slp_sl_thold_3), + .rp_rv_func_nsl_thold_3(rp_rv_func_nsl_thold_3), + .rp_rv_func_slp_nsl_thold_3(rp_rv_func_slp_nsl_thold_3), + .rp_rv_ary_nsl_thold_3(rp_rv_ary_nsl_thold_3), + .rp_rv_ary_slp_nsl_thold_3(rp_rv_ary_slp_nsl_thold_3), + .rp_rv_sg_3(rp_rv_sg_3), + .rp_rv_fce_3(rp_rv_fce_3), + // + .rp_xu_ccflush_dc(rp_xu_ccflush_dc), + .rp_xu_gptr_sl_thold_3(rp_xu_gptr_sl_thold_3), + .rp_xu_time_sl_thold_3(rp_xu_time_sl_thold_3), + .rp_xu_repr_sl_thold_3(rp_xu_repr_sl_thold_3), + .rp_xu_abst_sl_thold_3(rp_xu_abst_sl_thold_3), + .rp_xu_abst_slp_sl_thold_3(rp_xu_abst_slp_sl_thold_3), + .rp_xu_regf_slp_sl_thold_3(rp_xu_regf_slp_sl_thold_3), + .rp_xu_func_sl_thold_3(rp_xu_func_sl_thold_3), + .rp_xu_func_slp_sl_thold_3(rp_xu_func_slp_sl_thold_3), + .rp_xu_cfg_sl_thold_3(rp_xu_cfg_sl_thold_3), + .rp_xu_cfg_slp_sl_thold_3(rp_xu_cfg_slp_sl_thold_3), + .rp_xu_func_nsl_thold_3(rp_xu_func_nsl_thold_3), + .rp_xu_func_slp_nsl_thold_3(rp_xu_func_slp_nsl_thold_3), + .rp_xu_ary_nsl_thold_3(rp_xu_ary_nsl_thold_3), + .rp_xu_ary_slp_nsl_thold_3(rp_xu_ary_slp_nsl_thold_3), + .rp_xu_sg_3(rp_xu_sg_3), + .rp_xu_fce_3(rp_xu_fce_3), + // + .rp_lq_ccflush_dc(rp_lq_ccflush_dc), + .rp_lq_gptr_sl_thold_3(rp_lq_gptr_sl_thold_3), + .rp_lq_time_sl_thold_3(rp_lq_time_sl_thold_3), + .rp_lq_repr_sl_thold_3(rp_lq_repr_sl_thold_3), + .rp_lq_abst_sl_thold_3(rp_lq_abst_sl_thold_3), + .rp_lq_abst_slp_sl_thold_3(rp_lq_abst_slp_sl_thold_3), + .rp_lq_regf_slp_sl_thold_3(rp_lq_regf_slp_sl_thold_3), + .rp_lq_func_sl_thold_3(rp_lq_func_sl_thold_3), + .rp_lq_func_slp_sl_thold_3(rp_lq_func_slp_sl_thold_3), + .rp_lq_cfg_sl_thold_3(rp_lq_cfg_sl_thold_3), + .rp_lq_cfg_slp_sl_thold_3(rp_lq_cfg_slp_sl_thold_3), + .rp_lq_func_nsl_thold_3(rp_lq_func_nsl_thold_3), + .rp_lq_func_slp_nsl_thold_3(rp_lq_func_slp_nsl_thold_3), + .rp_lq_ary_nsl_thold_3(rp_lq_ary_nsl_thold_3), + .rp_lq_ary_slp_nsl_thold_3(rp_lq_ary_slp_nsl_thold_3), + .rp_lq_sg_3(rp_lq_sg_3), + .rp_lq_fce_3(rp_lq_fce_3), + // + .rp_mm_ccflush_dc(rp_mm_ccflush_dc), + .rp_mm_gptr_sl_thold_3(rp_mm_gptr_sl_thold_3), + .rp_mm_time_sl_thold_3(rp_mm_time_sl_thold_3), + .rp_mm_repr_sl_thold_3(rp_mm_repr_sl_thold_3), + .rp_mm_abst_sl_thold_3(rp_mm_abst_sl_thold_3), + .rp_mm_abst_slp_sl_thold_3(rp_mm_abst_slp_sl_thold_3), + .rp_mm_func_sl_thold_3(rp_mm_func_sl_thold_3), + .rp_mm_func_slp_sl_thold_3(rp_mm_func_slp_sl_thold_3), + .rp_mm_cfg_sl_thold_3(rp_mm_cfg_sl_thold_3), + .rp_mm_cfg_slp_sl_thold_3(rp_mm_cfg_slp_sl_thold_3), + .rp_mm_func_nsl_thold_3(rp_mm_func_nsl_thold_3), + .rp_mm_func_slp_nsl_thold_3(rp_mm_func_slp_nsl_thold_3), + .rp_mm_ary_nsl_thold_3(rp_mm_ary_nsl_thold_3), + .rp_mm_ary_slp_nsl_thold_3(rp_mm_ary_slp_nsl_thold_3), + .rp_mm_sg_3(rp_mm_sg_3), + .rp_mm_fce_3(rp_mm_fce_3), + + //SCANRING REPOWERING + .pc_bcfg_scan_in(1'b0), + .pc_bcfg_scan_in_q(), + .pc_dcfg_scan_in(1'b0), + .pc_dcfg_scan_in_q(), + .pc_bcfg_scan_out(1'b0), + .pc_bcfg_scan_out_q(), + .pc_ccfg_scan_out(1'b0), + .pc_ccfg_scan_out_q(), + .pc_dcfg_scan_out(1'b0), + .pc_dcfg_scan_out_q(), + .pc_func_scan_in(2'b00), + .pc_func_scan_in_q(), + .pc_func_scan_out(2'b00), + .pc_func_scan_out_q(), + // + .fu_abst_scan_in(1'b0), + .fu_abst_scan_in_q(), + .fu_abst_scan_out(1'b0), + .fu_abst_scan_out_q(), + .fu_ccfg_scan_out(1'b0), + .fu_ccfg_scan_out_q(), + .fu_bcfg_scan_out(1'b0), + .fu_bcfg_scan_out_q(), + .fu_dcfg_scan_out(1'b0), + .fu_dcfg_scan_out_q(), + .fu_func_scan_in(4'b0000), + .fu_func_scan_in_q(), + .fu_func_scan_out(4'b0000), + .fu_func_scan_out_q(), + + //MISCELLANEOUS FUNCTIONAL SIGNALS + // node inputs going to pcq + .an_ac_scom_dch(an_ac_scom_dch), + .an_ac_scom_cch(an_ac_scom_cch), + .an_ac_checkstop(an_ac_checkstop), + .an_ac_debug_stop(an_ac_debug_stop), + .an_ac_pm_thread_stop(an_ac_pm_thread_stop), + .an_ac_pm_fetch_halt(an_ac_pm_fetch_halt), + // + .rp_pc_scom_dch_q(rp_pc_scom_dch_q), + .rp_pc_scom_cch_q(rp_pc_scom_cch_q), + .rp_pc_checkstop_q(rp_pc_checkstop_q), + .rp_pc_debug_stop_q(rp_pc_debug_stop_q), + .rp_pc_pm_thread_stop_q(rp_pc_pm_thread_stop_q), + .rp_pc_pm_fetch_halt_q(rp_pc_pm_fetch_halt_q), + // pcq outputs going to node + .pc_rp_scom_dch(pc_rp_scom_dch), + .pc_rp_scom_cch(pc_rp_scom_cch), + .pc_rp_special_attn(pc_rp_special_attn), + .pc_rp_checkstop(pc_rp_checkstop), + .pc_rp_local_checkstop(pc_rp_local_checkstop), + .pc_rp_recov_err(pc_rp_recov_err), + .pc_rp_trace_error(pc_rp_trace_error), + .pc_rp_pm_thread_running(pc_rp_pm_thread_running), + .pc_rp_power_managed(pc_rp_power_managed), + .pc_rp_rvwinkle_mode(pc_rp_rvwinkle_mode), + .pc_rp_livelock_active(pc_rp_livelock_active), + // + .ac_an_scom_dch_q(ac_an_scom_dch), + .ac_an_scom_cch_q(ac_an_scom_cch), + .ac_an_special_attn_q(ac_an_special_attn), + .ac_an_checkstop_q(ac_an_checkstop), + .ac_an_local_checkstop_q(ac_an_local_checkstop), + .ac_an_recov_err_q(ac_an_recov_err), + .ac_an_trace_error_q(ac_an_trace_error), + .ac_an_pm_thread_running_q(ac_an_pm_thread_running), + .ac_an_power_managed_q(ac_an_power_managed_int), + .ac_an_rvwinkle_mode_q(ac_an_rvwinkle_mode), + .ac_an_livelock_active_q(ac_an_livelock_active), + + // SCAN CHAINS + .scan_diag_dc(an_ac_scan_diag_dc), + .scan_dis_dc_b(an_ac_scan_dis_dc_b), + .func_scan_in(1'b0), + .gptr_scan_in(1'b0), + .func_scan_out(), + .gptr_scan_out() + ); + +endmodule diff --git a/dev/verilog/work/c_fu_pc.v b/dev/verilog/work/c_fu_pc.v new file mode 100755 index 0000000..6e28f77 --- /dev/null +++ b/dev/verilog/work/c_fu_pc.v @@ -0,0 +1,1036 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//***************************************************************************** +//* +//* TITLE: c_fu_pc +//* +//* DESC: Top level interface for a combined fu and pcq RLM +//* +//***************************************************************************** + +(* recursive_synthesis=0 *) + + +module c_fu_pc( + `include "tri_a2o.vh" +// ---------------------------------------------------------------------- +// Common I/O Ports +// ---------------------------------------------------------------------- + // inout vdd, + // inout gnd, + (* PIN_DATA="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) // nclk + input [0:`NCLK_WIDTH-1] nclk, + + input [0:31] fu_debug_bus_in, + output [0:31] fu_debug_bus_out, + input [0:3] fu_coretrace_ctrls_in, + output [0:3] fu_coretrace_ctrls_out, + input [0:4*`THREADS-1] fu_event_bus_in, + output [0:4*`THREADS-1] fu_event_bus_out, + + input [0:31] pc_debug_bus_in, + output [0:31] pc_debug_bus_out, + input [0:3] pc_coretrace_ctrls_in, + output [0:3] pc_coretrace_ctrls_out, + + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) // scan_in + input fu_gptr_scan_in, + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) // scan_in + input fu_time_scan_in, + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) // scan_in + input fu_repr_scan_in, + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) // scan_in + input fu_bcfg_scan_in, + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) // scan_in + input fu_ccfg_scan_in, + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) // scan_in + input fu_dcfg_scan_in, + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) // scan_in + input [0:3] fu_func_scan_in, + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) // scan_in + input fu_abst_scan_in, + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) // scan_out + output fu_gptr_scan_out, + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) // scan_out + output fu_time_scan_out, + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) // scan_out + output fu_repr_scan_out, + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) // scan_out + output fu_bcfg_scan_out, + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) // scan_out + output fu_ccfg_scan_out, + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) // scan_out + output fu_dcfg_scan_out, + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) // scan_out + output [0:3] fu_func_scan_out, + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) // scan_out + output fu_abst_scan_out, + + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) // scan_in + input pc_gptr_scan_in, + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) // scan_in + input pc_ccfg_scan_in, + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) // scan_in + input pc_bcfg_scan_in, + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) // scan_in + input pc_dcfg_scan_in, + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) // scan_in + input [0:1] pc_func_scan_in, + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) // scan_out + output pc_gptr_scan_out, + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) // scan_out + output pc_ccfg_scan_out, + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) // scan_out + output pc_bcfg_scan_out, + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) // scan_out + output pc_dcfg_scan_out, + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) // scan_out + output [0:1] pc_func_scan_out, + + input [0:`THREADS-1] cp_flush, + input [0:9] fu_slowspr_addr_in, + input [64-(2**`REGMODE):63] fu_slowspr_data_in, + input fu_slowspr_done_in, + input [0:1] fu_slowspr_etid_in, + input fu_slowspr_rw_in, + input fu_slowspr_val_in, + output [0:9] fu_slowspr_addr_out, + output [64-(2**`REGMODE):63] fu_slowspr_data_out, + output fu_slowspr_done_out, + output [0:1] fu_slowspr_etid_out, + output fu_slowspr_rw_out, + output fu_slowspr_val_out, + + input [0:9] pc_slowspr_addr_in, + input [64-`GPR_WIDTH:63] pc_slowspr_data_in, + input pc_slowspr_done_in, + input [0:1] pc_slowspr_etid_in, + input pc_slowspr_rw_in, + input pc_slowspr_val_in, + output [0:9] pc_slowspr_addr_out, + output [64-`GPR_WIDTH:63] pc_slowspr_data_out, + output pc_slowspr_done_out, + output [0:1] pc_slowspr_etid_out, + output pc_slowspr_rw_out, + output pc_slowspr_val_out, + + +// ---------------------------------------------------------------------- +// FU Interface +// ---------------------------------------------------------------------- + input [0:6] cp_t0_next_itag, + input [0:6] cp_t1_next_itag, + input [0:`THREADS-1] cp_axu_i0_t1_v, + input [0:2] cp_axu_i0_t0_t1_t, + input [0:5] cp_axu_i0_t0_t1_p, + input [0:2] cp_axu_i0_t1_t1_t, + input [0:5] cp_axu_i0_t1_t1_p, + input [0:`THREADS-1] cp_axu_i1_t1_v, + input [0:2] cp_axu_i1_t0_t1_t, + input [0:5] cp_axu_i1_t0_t1_p, + input [0:2] cp_axu_i1_t1_t1_t, + input [0:5] cp_axu_i1_t1_t1_p, + + input [0:6] iu_xx_t0_zap_itag, + input [0:6] iu_xx_t1_zap_itag, + output [0:`THREADS-1] axu0_iu_async_fex, + output [0:3] axu0_iu_perf_events, + output [0:3] axu0_iu_exception, + output axu0_iu_exception_val, + output [0:`THREADS-1] axu0_iu_execute_vld, + output axu0_iu_flush2ucode, + output axu0_iu_flush2ucode_type, + output [0:`ITAG_SIZE_ENC-1] axu0_iu_itag, + output axu0_iu_n_flush, + output axu0_iu_n_np1_flush, + output axu0_iu_np1_flush, + output [0:3] axu1_iu_perf_events, + output [0:3] axu1_iu_exception, + output axu1_iu_exception_val, + output [0:`THREADS-1] axu1_iu_execute_vld, + output axu1_iu_flush2ucode, + output axu1_iu_flush2ucode_type, + output [0:`ITAG_SIZE_ENC-1] axu1_iu_itag, + output axu1_iu_n_flush, + output axu1_iu_np1_flush, + + input [59:63] lq_fu_ex4_eff_addr, + input lq_fu_ex5_load_le, + input [192:255] lq_fu_ex5_load_data, + input [0:7+`THREADS] lq_fu_ex5_load_tag, + input lq_fu_ex5_load_val, + input lq_fu_ex5_abort, + input lq_gpr_rel_we, + input lq_gpr_rel_le, + input [0:7+`THREADS] lq_gpr_rel_wa, + input [64:127] lq_gpr_rel_wd, + input [0:`ITAG_SIZE_ENC-1] lq_rv_itag0, + input lq_rv_itag0_vld, + input lq_rv_itag0_spec, + input lq_rv_itag1_restart, + output [0:`THREADS-1] fu_lq_ex2_store_data_val, + output [0:`ITAG_SIZE_ENC-1] fu_lq_ex2_store_itag, + output [0:63] fu_lq_ex3_store_data, + output fu_lq_ex3_sto_parity_err, + output fu_lq_ex3_abort, + + input [0:`THREADS-1] rv_axu0_vld, + input [0:31] rv_axu0_ex0_instr, + input [0:`ITAG_SIZE_ENC-1] rv_axu0_ex0_itag, + input [0:2] rv_axu0_ex0_ucode, + input rv_axu0_ex0_t1_v, + input [0:`FPR_POOL_ENC-1] rv_axu0_ex0_t1_p, + input [0:`FPR_POOL_ENC-1] rv_axu0_ex0_t2_p, + input [0:`FPR_POOL_ENC-1] rv_axu0_ex0_t3_p, + input rv_axu0_s1_v, + input [0:`FPR_POOL_ENC-1] rv_axu0_s1_p, + input [0:2] rv_axu0_s1_t, + input rv_axu0_s2_v, + input [0:`FPR_POOL_ENC-1] rv_axu0_s2_p, + input [0:2] rv_axu0_s2_t, + input rv_axu0_s3_v, + input [0:`FPR_POOL_ENC-1] rv_axu0_s3_p, + input [0:2] rv_axu0_s3_t, + output axu0_rv_ex2_s1_abort, + output axu0_rv_ex2_s2_abort, + output axu0_rv_ex2_s3_abort, + output [0:`ITAG_SIZE_ENC-1] axu0_rv_itag, + output [0:`THREADS-1] axu0_rv_itag_vld, + output axu0_rv_itag_abort, + output axu0_rv_ord_complete, + output axu0_rv_hold_all, + output [0:`ITAG_SIZE_ENC-1] axu1_rv_itag, + output [0:`THREADS-1] axu1_rv_itag_vld, + output axu1_rv_itag_abort, + output axu1_rv_hold_all, + + input [0:3] pc_fu_abist_di_0, + input [0:3] pc_fu_abist_di_1, + input pc_fu_abist_ena_dc, + input pc_fu_abist_grf_renb_0, + input pc_fu_abist_grf_renb_1, + input pc_fu_abist_grf_wenb_0, + input pc_fu_abist_grf_wenb_1, + input [0:9] pc_fu_abist_raddr_0, + input [0:9] pc_fu_abist_raddr_1, + input pc_fu_abist_raw_dc_b, + input [0:9] pc_fu_abist_waddr_0, + input [0:9] pc_fu_abist_waddr_1, + input pc_fu_abist_wl144_comp_ena, + + input [0:`THREADS-1] xu_fu_msr_fe0, + input [0:`THREADS-1] xu_fu_msr_fe1, + input [0:`THREADS-1] xu_fu_msr_fp, + input [0:`THREADS-1] xu_fu_msr_gs, + input [0:`THREADS-1] xu_fu_msr_pr, + output axu0_cr_w4e, + output [0:`CR_POOL_ENC+`THREAD_POOL_ENC-1] axu0_cr_w4a, + output [0:3] axu0_cr_w4d, + +// ---------------------------------------------------------------------- +// PC Interface +// ---------------------------------------------------------------------- + //SCOM Satellite + input [0:3] an_ac_scom_sat_id, + input an_ac_scom_dch, + input an_ac_scom_cch, + output ac_an_scom_dch, + output ac_an_scom_cch, + // FIR and Error Signals + output [0:`THREADS-1] ac_an_special_attn, + output [0:2] ac_an_checkstop, + output [0:2] ac_an_local_checkstop, + output [0:2] ac_an_recov_err, + output ac_an_trace_error, + output ac_an_livelock_active, + input an_ac_checkstop, + input [0:`THREADS-1] iu_pc_err_attention_instr, + input iu_pc_err_icache_parity, + input iu_pc_err_icachedir_parity, + input iu_pc_err_icachedir_multihit, + input iu_pc_err_ierat_parity, + input iu_pc_err_ierat_multihit, + input iu_pc_err_btb_parity, + input [0:`THREADS-1] iu_pc_err_cpArray_parity, + input [0:`THREADS-1] iu_pc_err_ucode_illegal, + input [0:`THREADS-1] iu_pc_err_mchk_disabled, + input [0:`THREADS-1] iu_pc_err_debug_event, + input lq_pc_err_dcache_parity, + input lq_pc_err_dcachedir_ldp_parity, + input lq_pc_err_dcachedir_stp_parity, + input lq_pc_err_dcachedir_ldp_multihit, + input lq_pc_err_dcachedir_stp_multihit, + input lq_pc_err_derat_parity, + input lq_pc_err_derat_multihit, + input lq_pc_err_l2intrf_ecc, + input lq_pc_err_l2intrf_ue, + input lq_pc_err_invld_reld, + input lq_pc_err_l2credit_overrun, + input [0:`THREADS-1] lq_pc_err_regfile_parity, + input [0:`THREADS-1] lq_pc_err_regfile_ue, + input lq_pc_err_prefetcher_parity, + input lq_pc_err_relq_parity, + input mm_pc_err_tlb_parity, + input mm_pc_err_tlb_multihit, + input mm_pc_err_tlb_lru_parity, + input mm_pc_err_local_snoop_reject, + input [0:`THREADS-1] xu_pc_err_sprg_ecc, + input [0:`THREADS-1] xu_pc_err_sprg_ue, + input [0:`THREADS-1] xu_pc_err_regfile_parity, + input [0:`THREADS-1] xu_pc_err_regfile_ue, + input [0:`THREADS-1] xu_pc_err_llbust_attempt, + input [0:`THREADS-1] xu_pc_err_llbust_failed, + input [0:`THREADS-1] xu_pc_err_wdt_reset, + output pc_iu_inj_icache_parity, + output pc_iu_inj_icachedir_parity, + output pc_iu_inj_icachedir_multihit, + output [0:`THREADS-1] pc_iu_inj_cpArray_parity, + output pc_lq_inj_dcache_parity, + output pc_lq_inj_dcachedir_ldp_parity, + output pc_lq_inj_dcachedir_stp_parity, + output pc_lq_inj_dcachedir_ldp_multihit, + output pc_lq_inj_dcachedir_stp_multihit, + output pc_lq_inj_prefetcher_parity, + output [0:`THREADS-1] pc_lq_inj_regfile_parity, + output pc_lq_inj_relq_parity, + output [0:`THREADS-1] pc_fx0_inj_regfile_parity, + output [0:`THREADS-1] pc_fx1_inj_regfile_parity, + output [0:`THREADS-1] pc_xu_inj_sprg_ecc, + output [0:`THREADS-1] pc_xu_inj_llbust_attempt, + output [0:`THREADS-1] pc_xu_inj_llbust_failed, + // Unit quiesce and credit status bits + input [0:`THREADS-1] iu_pc_quiesce, + input [0:`THREADS-1] iu_pc_icache_quiesce, + input [0:`THREADS-1] lq_pc_ldq_quiesce, + input [0:`THREADS-1] lq_pc_stq_quiesce, + input [0:`THREADS-1] lq_pc_pfetch_quiesce, + input [0:`THREADS-1] mm_pc_tlb_req_quiesce, + input [0:`THREADS-1] mm_pc_tlb_ctl_quiesce, + input [0:`THREADS-1] mm_pc_htw_quiesce, + input [0:`THREADS-1] mm_pc_inval_quiesce, + input [0:`THREADS-1] iu_pc_fx0_credit_ok, + input [0:`THREADS-1] iu_pc_fx1_credit_ok, + input [0:`THREADS-1] iu_pc_axu0_credit_ok, + input [0:`THREADS-1] iu_pc_axu1_credit_ok, + input [0:`THREADS-1] iu_pc_lq_credit_ok, + input [0:`THREADS-1] iu_pc_sq_credit_ok, + // RAM Command/Data + output [0:31] pc_iu_ram_instr, + output [0:3] pc_iu_ram_instr_ext, + output [0:`THREADS-1] pc_iu_ram_active, + output pc_iu_ram_issue, + input iu_pc_ram_done, + input iu_pc_ram_interrupt, + input iu_pc_ram_unsupported, + output [0:`THREADS-1] pc_xu_ram_active, + input xu_pc_ram_data_val, + input [64-`GPR_WIDTH:63] xu_pc_ram_data, + output [0:`THREADS-1] pc_lq_ram_active, + input lq_pc_ram_data_val, + input [64-`GPR_WIDTH:63] lq_pc_ram_data, + output pc_xu_msrovride_enab, + output pc_xu_msrovride_pr, + output pc_xu_msrovride_gs, + output pc_xu_msrovride_de, + output pc_iu_ram_force_cmplt, + output [0:`THREADS-1] pc_iu_ram_flush_thread, + // THRCTL + PCCR0 Registers + input an_ac_debug_stop, + input [0:`THREADS-1] xu_pc_running, + input [0:`THREADS-1] iu_pc_stop_dbg_event, + input [0:`THREADS-1] xu_pc_stop_dnh_instr, + input [0:`THREADS-1] iu_pc_step_done, + output [0:`THREADS-1] pc_iu_stop, + output [0:`THREADS-1] pc_iu_step, + output pc_xu_extirpts_dis_on_stop, + output pc_xu_timebase_dis_on_stop, + output pc_xu_decrem_dis_on_stop, + output [0:3*`THREADS-1] pc_iu_dbg_action, + output [0:`THREADS-1] pc_iu_spr_dbcr0_edm, + output [0:`THREADS-1] pc_xu_spr_dbcr0_edm, + //Debug Bus Controls + output pc_iu_trace_bus_enable, + output pc_rv_trace_bus_enable, + output pc_mm_trace_bus_enable, + output pc_xu_trace_bus_enable, + output pc_lq_trace_bus_enable, + output [0:10] pc_iu_debug_mux1_ctrls, + output [0:10] pc_iu_debug_mux2_ctrls, + output [0:10] pc_rv_debug_mux_ctrls, + output [0:10] pc_mm_debug_mux_ctrls, + output [0:10] pc_xu_debug_mux_ctrls, + output [0:10] pc_lq_debug_mux1_ctrls, + output [0:10] pc_lq_debug_mux2_ctrls, + // Event Bus Controls + output [0:39] pc_rv_event_mux_ctrls, + output pc_iu_event_bus_enable, + output pc_rv_event_bus_enable, + output pc_mm_event_bus_enable, + output pc_xu_event_bus_enable, + output pc_lq_event_bus_enable, + output [0:2] pc_iu_event_count_mode, + output [0:2] pc_rv_event_count_mode, + output [0:2] pc_mm_event_count_mode, + output [0:2] pc_xu_event_count_mode, + output [0:2] pc_lq_event_count_mode, + output pc_iu_instr_trace_mode, + output pc_iu_instr_trace_tid, + output pc_lq_instr_trace_mode, + output pc_lq_instr_trace_tid, + output pc_xu_instr_trace_mode, + output pc_xu_instr_trace_tid, + input [0:`THREADS-1] xu_pc_perfmon_alert, + output [0:`THREADS-1] pc_xu_spr_cesr1_pmae, + output pc_lq_event_bus_seldbghi, + output pc_lq_event_bus_seldbglo, + // Reset related + output pc_lq_init_reset, + output pc_iu_init_reset, + // Power Management + output [0:`THREADS-1] ac_an_pm_thread_running, + input [0:`THREADS-1] an_ac_pm_thread_stop, + input [0:`THREADS-1] an_ac_pm_fetch_halt, + output [0:`THREADS-1] pc_iu_pm_fetch_halt, + output ac_an_power_managed, + output ac_an_rvwinkle_mode, + output pc_xu_pm_hold_thread, + input [0:1] xu_pc_spr_ccr0_pme, + input [0:`THREADS-1] xu_pc_spr_ccr0_we, + // Clock, Test, and LCB Controls + input an_ac_gsd_test_enable_dc, + input an_ac_gsd_test_acmode_dc, + input an_ac_ccflush_dc, + input an_ac_ccenable_dc, + input an_ac_lbist_en_dc, + input an_ac_lbist_ip_dc, + input an_ac_lbist_ac_mode_dc, + input an_ac_scan_diag_dc, + input an_ac_scan_dis_dc_b, + input an_ac_rtim_sl_thold_7, + input an_ac_func_sl_thold_7, + input an_ac_func_nsl_thold_7, + input an_ac_ary_nsl_thold_7, + input an_ac_sg_7, + input an_ac_fce_7, + input [0:8] an_ac_scan_type_dc, + //Thold outputs to clock staging + output pc_rp_ccflush_out_dc, + output pc_rp_gptr_sl_thold_4, + output pc_rp_time_sl_thold_4, + output pc_rp_repr_sl_thold_4, + output pc_rp_abst_sl_thold_4, + output pc_rp_abst_slp_sl_thold_4, + output pc_rp_regf_sl_thold_4, + output pc_rp_regf_slp_sl_thold_4, + output pc_rp_func_sl_thold_4, + output pc_rp_func_slp_sl_thold_4, + output pc_rp_cfg_sl_thold_4, + output pc_rp_cfg_slp_sl_thold_4, + output pc_rp_func_nsl_thold_4, + output pc_rp_func_slp_nsl_thold_4, + output pc_rp_ary_nsl_thold_4, + output pc_rp_ary_slp_nsl_thold_4, + output pc_rp_rtim_sl_thold_4, + output pc_rp_sg_4, + output pc_rp_fce_4 + +); + + + // ###################### CONSTANTS ###################### -- + parameter float_type = 1; + + + + // ####################### SIGNALS ####################### -- + // Internal Connections Between PC + FU + wire [0:`THREADS-1] pc_fu_ram_active; + wire [0:63] fu_pc_ram_data; + wire fu_pc_ram_data_val; + + wire pc_fu_trace_bus_enable; + wire [0:10] pc_fu_debug_mux_ctrls; + wire pc_fu_instr_trace_mode; + wire [0:1] pc_fu_instr_trace_tid; + + wire pc_fu_event_bus_enable; + wire [0:2] pc_fu_event_count_mode; + + wire [0:`THREADS-1] pc_fu_inj_regfile_parity; + wire [0:`THREADS-1] fu_pc_err_regfile_parity; + wire [0:`THREADS-1] fu_pc_err_regfile_ue; + + wire pc_fu_ccflush_dc; + wire pc_fu_gptr_sl_thold_3; + wire pc_fu_time_sl_thold_3; + wire pc_fu_repr_sl_thold_3; + wire pc_fu_cfg_sl_thold_3; + wire pc_fu_cfg_slp_sl_thold_3; + wire pc_fu_func_nsl_thold_3; + wire [0:1] pc_fu_func_sl_thold_3; + wire pc_fu_func_slp_nsl_thold_3; + wire [0:1] pc_fu_func_slp_sl_thold_3; + wire pc_fu_abst_sl_thold_3; + wire pc_fu_abst_slp_sl_thold_3; + wire pc_fu_ary_nsl_thold_3; + wire pc_fu_ary_slp_nsl_thold_3; + wire [0:1] pc_fu_sg_3; + wire pc_fu_fce_3; + + + + assign pc_fu_instr_trace_mode = 1'b0; + assign pc_fu_instr_trace_tid[0:1] = 2'b00; + + + // ####################### START ######################### -- + pcq + pc0( + // .vdd(vdd), + // .gnd(gnd), + .nclk(nclk), + //SCOM Satellite + .an_ac_scom_sat_id(an_ac_scom_sat_id), + .an_ac_scom_dch(an_ac_scom_dch), + .an_ac_scom_cch(an_ac_scom_cch), + .ac_an_scom_dch(ac_an_scom_dch), + .ac_an_scom_cch(ac_an_scom_cch), + //Slow SPR + .cp_flush(cp_flush), + .slowspr_addr_in(pc_slowspr_addr_in), + .slowspr_data_in(pc_slowspr_data_in), + .slowspr_done_in(pc_slowspr_done_in), + .slowspr_etid_in(pc_slowspr_etid_in), + .slowspr_rw_in(pc_slowspr_rw_in), + .slowspr_val_in(pc_slowspr_val_in), + .slowspr_addr_out(pc_slowspr_addr_out), + .slowspr_data_out(pc_slowspr_data_out), + .slowspr_done_out(pc_slowspr_done_out), + .slowspr_etid_out(pc_slowspr_etid_out), + .slowspr_rw_out(pc_slowspr_rw_out), + .slowspr_val_out(pc_slowspr_val_out), + // FIR and Error Signals + .ac_an_special_attn(ac_an_special_attn), + .ac_an_checkstop(ac_an_checkstop), + .ac_an_local_checkstop(ac_an_local_checkstop), + .ac_an_recov_err(ac_an_recov_err), + .ac_an_trace_error(ac_an_trace_error), + .ac_an_livelock_active(ac_an_livelock_active), + .an_ac_checkstop(an_ac_checkstop), + .fu_pc_err_regfile_parity(fu_pc_err_regfile_parity), + .fu_pc_err_regfile_ue(fu_pc_err_regfile_ue), + .iu_pc_err_attention_instr(iu_pc_err_attention_instr), + .iu_pc_err_icache_parity(iu_pc_err_icache_parity), + .iu_pc_err_icachedir_parity(iu_pc_err_icachedir_parity), + .iu_pc_err_icachedir_multihit(iu_pc_err_icachedir_multihit), + .iu_pc_err_ierat_parity(iu_pc_err_ierat_parity), + .iu_pc_err_ierat_multihit(iu_pc_err_ierat_multihit), + .iu_pc_err_btb_parity(iu_pc_err_btb_parity), + .iu_pc_err_cpArray_parity(iu_pc_err_cpArray_parity), + .iu_pc_err_ucode_illegal(iu_pc_err_ucode_illegal), + .iu_pc_err_mchk_disabled(iu_pc_err_mchk_disabled), + .iu_pc_err_debug_event(iu_pc_err_debug_event), + .lq_pc_err_dcache_parity(lq_pc_err_dcache_parity), + .lq_pc_err_dcachedir_ldp_parity(lq_pc_err_dcachedir_ldp_parity), + .lq_pc_err_dcachedir_stp_parity(lq_pc_err_dcachedir_stp_parity), + .lq_pc_err_dcachedir_ldp_multihit(lq_pc_err_dcachedir_ldp_multihit), + .lq_pc_err_dcachedir_stp_multihit(lq_pc_err_dcachedir_stp_multihit), + .lq_pc_err_derat_parity(lq_pc_err_derat_parity), + .lq_pc_err_derat_multihit(lq_pc_err_derat_multihit), + .lq_pc_err_l2intrf_ecc(lq_pc_err_l2intrf_ecc), + .lq_pc_err_l2intrf_ue(lq_pc_err_l2intrf_ue), + .lq_pc_err_invld_reld(lq_pc_err_invld_reld), + .lq_pc_err_l2credit_overrun(lq_pc_err_l2credit_overrun), + .lq_pc_err_regfile_parity(lq_pc_err_regfile_parity), + .lq_pc_err_regfile_ue(lq_pc_err_regfile_ue), + .lq_pc_err_prefetcher_parity(lq_pc_err_prefetcher_parity), + .lq_pc_err_relq_parity(lq_pc_err_relq_parity), + .mm_pc_err_tlb_parity(mm_pc_err_tlb_parity), + .mm_pc_err_tlb_lru_parity(mm_pc_err_tlb_lru_parity), + .mm_pc_err_tlb_multihit(mm_pc_err_tlb_multihit), + .mm_pc_err_local_snoop_reject(mm_pc_err_local_snoop_reject), + .xu_pc_err_sprg_ecc(xu_pc_err_sprg_ecc), + .xu_pc_err_sprg_ue(xu_pc_err_sprg_ue), + .xu_pc_err_regfile_parity(xu_pc_err_regfile_parity), + .xu_pc_err_regfile_ue(xu_pc_err_regfile_ue), + .xu_pc_err_llbust_attempt(xu_pc_err_llbust_attempt), + .xu_pc_err_llbust_failed(xu_pc_err_llbust_failed), + .xu_pc_err_wdt_reset(xu_pc_err_wdt_reset), + .pc_fu_inj_regfile_parity(pc_fu_inj_regfile_parity), + .pc_iu_inj_cpArray_parity(pc_iu_inj_cpArray_parity), + .pc_iu_inj_icache_parity(pc_iu_inj_icache_parity), + .pc_iu_inj_icachedir_parity(pc_iu_inj_icachedir_parity), + .pc_iu_inj_icachedir_multihit(pc_iu_inj_icachedir_multihit), + .pc_lq_inj_dcache_parity(pc_lq_inj_dcache_parity), + .pc_lq_inj_dcachedir_ldp_parity(pc_lq_inj_dcachedir_ldp_parity), + .pc_lq_inj_dcachedir_stp_parity(pc_lq_inj_dcachedir_stp_parity), + .pc_lq_inj_dcachedir_ldp_multihit(pc_lq_inj_dcachedir_ldp_multihit), + .pc_lq_inj_dcachedir_stp_multihit(pc_lq_inj_dcachedir_stp_multihit), + .pc_lq_inj_prefetcher_parity(pc_lq_inj_prefetcher_parity), + .pc_lq_inj_regfile_parity(pc_lq_inj_regfile_parity), + .pc_lq_inj_relq_parity(pc_lq_inj_relq_parity), + .pc_fx0_inj_regfile_parity(pc_fx0_inj_regfile_parity), + .pc_fx1_inj_regfile_parity(pc_fx1_inj_regfile_parity), + .pc_xu_inj_sprg_ecc(pc_xu_inj_sprg_ecc), + .pc_xu_inj_llbust_attempt(pc_xu_inj_llbust_attempt), + .pc_xu_inj_llbust_failed(pc_xu_inj_llbust_failed), + // Unit quiesce and credit status bits + .iu_pc_quiesce(iu_pc_quiesce), + .iu_pc_icache_quiesce(iu_pc_icache_quiesce), + .lq_pc_ldq_quiesce(lq_pc_ldq_quiesce), + .lq_pc_stq_quiesce(lq_pc_stq_quiesce), + .lq_pc_pfetch_quiesce(lq_pc_pfetch_quiesce), + .mm_pc_tlb_req_quiesce(mm_pc_tlb_req_quiesce), + .mm_pc_tlb_ctl_quiesce(mm_pc_tlb_ctl_quiesce), + .mm_pc_htw_quiesce(mm_pc_htw_quiesce), + .mm_pc_inval_quiesce(mm_pc_inval_quiesce), + .iu_pc_fx0_credit_ok(iu_pc_fx0_credit_ok), + .iu_pc_fx1_credit_ok(iu_pc_fx1_credit_ok), + .iu_pc_axu0_credit_ok(iu_pc_axu0_credit_ok), + .iu_pc_axu1_credit_ok(iu_pc_axu1_credit_ok), + .iu_pc_lq_credit_ok(iu_pc_lq_credit_ok), + .iu_pc_sq_credit_ok(iu_pc_sq_credit_ok), + // RAM Command/Data + .pc_iu_ram_instr(pc_iu_ram_instr), + .pc_iu_ram_instr_ext(pc_iu_ram_instr_ext), + .pc_iu_ram_active(pc_iu_ram_active), + .pc_iu_ram_execute(pc_iu_ram_issue), + .iu_pc_ram_done(iu_pc_ram_done), + .iu_pc_ram_interrupt(iu_pc_ram_interrupt), + .iu_pc_ram_unsupported(iu_pc_ram_unsupported), + .pc_xu_ram_active(pc_xu_ram_active), + .xu_pc_ram_data_val(xu_pc_ram_data_val), + .xu_pc_ram_data(xu_pc_ram_data), + .pc_fu_ram_active(pc_fu_ram_active), + .fu_pc_ram_data_val(fu_pc_ram_data_val), + .fu_pc_ram_data(fu_pc_ram_data), + .pc_lq_ram_active(pc_lq_ram_active), + .lq_pc_ram_data_val(lq_pc_ram_data_val), + .lq_pc_ram_data(lq_pc_ram_data), + .pc_xu_msrovride_enab(pc_xu_msrovride_enab), + .pc_xu_msrovride_pr(pc_xu_msrovride_pr), + .pc_xu_msrovride_gs(pc_xu_msrovride_gs), + .pc_xu_msrovride_de(pc_xu_msrovride_de), + .pc_iu_ram_force_cmplt(pc_iu_ram_force_cmplt), + .pc_iu_ram_flush_thread(pc_iu_ram_flush_thread), + // THRCTL + PCCR0 Registers + .xu_pc_running(xu_pc_running), + .iu_pc_stop_dbg_event(iu_pc_stop_dbg_event), + .xu_pc_stop_dnh_instr(xu_pc_stop_dnh_instr), + .iu_pc_step_done(iu_pc_step_done), + .pc_iu_stop(pc_iu_stop), + .pc_iu_step(pc_iu_step), + .pc_xu_extirpts_dis_on_stop(pc_xu_extirpts_dis_on_stop), + .pc_xu_timebase_dis_on_stop(pc_xu_timebase_dis_on_stop), + .pc_xu_decrem_dis_on_stop(pc_xu_decrem_dis_on_stop), + .an_ac_debug_stop(an_ac_debug_stop), + .pc_iu_dbg_action(pc_iu_dbg_action), + .pc_iu_spr_dbcr0_edm(pc_iu_spr_dbcr0_edm), + .pc_xu_spr_dbcr0_edm(pc_xu_spr_dbcr0_edm), + + // Trace/Debug Bus + .debug_bus_in(pc_debug_bus_in), + .debug_bus_out(pc_debug_bus_out), + .coretrace_ctrls_in(pc_coretrace_ctrls_in), + .coretrace_ctrls_out(pc_coretrace_ctrls_out), + //Debug Select Register outputs to units for debug grouping + .pc_fu_trace_bus_enable(pc_fu_trace_bus_enable), + .pc_iu_trace_bus_enable(pc_iu_trace_bus_enable), + .pc_rv_trace_bus_enable(pc_rv_trace_bus_enable), + .pc_mm_trace_bus_enable(pc_mm_trace_bus_enable), + .pc_xu_trace_bus_enable(pc_xu_trace_bus_enable), + .pc_lq_trace_bus_enable(pc_lq_trace_bus_enable), + .pc_iu_debug_mux1_ctrls(pc_iu_debug_mux1_ctrls), + .pc_iu_debug_mux2_ctrls(pc_iu_debug_mux2_ctrls), + .pc_fu_debug_mux_ctrls(pc_fu_debug_mux_ctrls), + .pc_rv_debug_mux_ctrls(pc_rv_debug_mux_ctrls), + .pc_mm_debug_mux_ctrls(pc_mm_debug_mux_ctrls), + .pc_xu_debug_mux_ctrls(pc_xu_debug_mux_ctrls), + .pc_lq_debug_mux1_ctrls(pc_lq_debug_mux1_ctrls), + .pc_lq_debug_mux2_ctrls(pc_lq_debug_mux2_ctrls), + + // Performance Bus and Event Mux Controls + .pc_rv_event_mux_ctrls(pc_rv_event_mux_ctrls), + .pc_iu_event_bus_enable(pc_iu_event_bus_enable), + .pc_fu_event_bus_enable(pc_fu_event_bus_enable), + .pc_rv_event_bus_enable(pc_rv_event_bus_enable), + .pc_mm_event_bus_enable(pc_mm_event_bus_enable), + .pc_xu_event_bus_enable(pc_xu_event_bus_enable), + .pc_lq_event_bus_enable(pc_lq_event_bus_enable), + .pc_iu_event_count_mode(pc_iu_event_count_mode), + .pc_fu_event_count_mode(pc_fu_event_count_mode), + .pc_rv_event_count_mode(pc_rv_event_count_mode), + .pc_mm_event_count_mode(pc_mm_event_count_mode), + .pc_xu_event_count_mode(pc_xu_event_count_mode), + .pc_lq_event_count_mode(pc_lq_event_count_mode), + .pc_lq_event_bus_seldbghi(pc_lq_event_bus_seldbghi), + .pc_lq_event_bus_seldbglo(pc_lq_event_bus_seldbglo), + .pc_iu_instr_trace_mode(pc_iu_instr_trace_mode), + .pc_iu_instr_trace_tid(pc_iu_instr_trace_tid), + .pc_lq_instr_trace_mode(pc_lq_instr_trace_mode), + .pc_lq_instr_trace_tid(pc_lq_instr_trace_tid), + .pc_xu_instr_trace_mode(pc_xu_instr_trace_mode), + .pc_xu_instr_trace_tid(pc_xu_instr_trace_tid), + .xu_pc_perfmon_alert(xu_pc_perfmon_alert), + .pc_xu_spr_cesr1_pmae(pc_xu_spr_cesr1_pmae), + // Reset related + .pc_lq_init_reset(pc_lq_init_reset), + .pc_iu_init_reset(pc_iu_init_reset), + + // Power Management + .ac_an_pm_thread_running(ac_an_pm_thread_running), + .an_ac_pm_thread_stop(an_ac_pm_thread_stop), + .an_ac_pm_fetch_halt(an_ac_pm_fetch_halt), + .pc_iu_pm_fetch_halt(pc_iu_pm_fetch_halt), + .ac_an_power_managed(ac_an_power_managed), + .ac_an_rvwinkle_mode(ac_an_rvwinkle_mode), + .pc_xu_pm_hold_thread(pc_xu_pm_hold_thread), + .xu_pc_spr_ccr0_pme(xu_pc_spr_ccr0_pme), + .xu_pc_spr_ccr0_we(xu_pc_spr_ccr0_we), + + // Clock, Test, and LCB Controls + .an_ac_gsd_test_enable_dc(an_ac_gsd_test_enable_dc), + .an_ac_gsd_test_acmode_dc(an_ac_gsd_test_acmode_dc), + .an_ac_ccflush_dc(an_ac_ccflush_dc), + .an_ac_ccenable_dc(an_ac_ccenable_dc), + .an_ac_lbist_en_dc(an_ac_lbist_en_dc), + .an_ac_lbist_ip_dc(an_ac_lbist_ip_dc), + .an_ac_lbist_ac_mode_dc(an_ac_lbist_ac_mode_dc), + .an_ac_scan_diag_dc(an_ac_scan_diag_dc), + .an_ac_scan_dis_dc_b(an_ac_scan_dis_dc_b), + //Thold input to clock control macro + .an_ac_rtim_sl_thold_7(an_ac_rtim_sl_thold_7), + .an_ac_func_sl_thold_7(an_ac_func_sl_thold_7), + .an_ac_func_nsl_thold_7(an_ac_func_nsl_thold_7), + .an_ac_ary_nsl_thold_7(an_ac_ary_nsl_thold_7), + .an_ac_sg_7(an_ac_sg_7), + .an_ac_fce_7(an_ac_fce_7), + .an_ac_scan_type_dc(an_ac_scan_type_dc), + //Clock control outputs to clock staging logic + .pc_rp_ccflush_out_dc(pc_rp_ccflush_out_dc), + .pc_rp_gptr_sl_thold_4(pc_rp_gptr_sl_thold_4), + .pc_rp_time_sl_thold_4(pc_rp_time_sl_thold_4), + .pc_rp_repr_sl_thold_4(pc_rp_repr_sl_thold_4), + .pc_rp_abst_sl_thold_4(pc_rp_abst_sl_thold_4), + .pc_rp_abst_slp_sl_thold_4(pc_rp_abst_slp_sl_thold_4), + .pc_rp_regf_sl_thold_4(pc_rp_regf_sl_thold_4), + .pc_rp_regf_slp_sl_thold_4(pc_rp_regf_slp_sl_thold_4), + .pc_rp_func_sl_thold_4(pc_rp_func_sl_thold_4), + .pc_rp_func_slp_sl_thold_4(pc_rp_func_slp_sl_thold_4), + .pc_rp_cfg_sl_thold_4(pc_rp_cfg_sl_thold_4), + .pc_rp_cfg_slp_sl_thold_4(pc_rp_cfg_slp_sl_thold_4), + .pc_rp_func_nsl_thold_4(pc_rp_func_nsl_thold_4), + .pc_rp_func_slp_nsl_thold_4(pc_rp_func_slp_nsl_thold_4), + .pc_rp_ary_nsl_thold_4(pc_rp_ary_nsl_thold_4), + .pc_rp_ary_slp_nsl_thold_4(pc_rp_ary_slp_nsl_thold_4), + .pc_rp_rtim_sl_thold_4(pc_rp_rtim_sl_thold_4), + .pc_rp_sg_4(pc_rp_sg_4), + .pc_rp_fce_4(pc_rp_fce_4), + .pc_fu_ccflush_dc(pc_fu_ccflush_dc), + .pc_fu_gptr_sl_thold_3(pc_fu_gptr_sl_thold_3), + .pc_fu_time_sl_thold_3(pc_fu_time_sl_thold_3), + .pc_fu_repr_sl_thold_3(pc_fu_repr_sl_thold_3), + .pc_fu_cfg_sl_thold_3(pc_fu_cfg_sl_thold_3), + .pc_fu_cfg_slp_sl_thold_3(pc_fu_cfg_slp_sl_thold_3), + .pc_fu_func_nsl_thold_3(pc_fu_func_nsl_thold_3), + .pc_fu_func_sl_thold_3(pc_fu_func_sl_thold_3), + .pc_fu_func_slp_nsl_thold_3(pc_fu_func_slp_nsl_thold_3), + .pc_fu_func_slp_sl_thold_3(pc_fu_func_slp_sl_thold_3), + .pc_fu_abst_sl_thold_3(pc_fu_abst_sl_thold_3), + .pc_fu_abst_slp_sl_thold_3(pc_fu_abst_slp_sl_thold_3), + .pc_fu_ary_nsl_thold_3(pc_fu_ary_nsl_thold_3), + .pc_fu_ary_slp_nsl_thold_3(pc_fu_ary_slp_nsl_thold_3), + .pc_fu_sg_3(pc_fu_sg_3), + .pc_fu_fce_3(pc_fu_fce_3), + + // Scanning + .gptr_scan_in(pc_gptr_scan_in), + .ccfg_scan_in(pc_ccfg_scan_in), + .bcfg_scan_in(pc_bcfg_scan_in), + .dcfg_scan_in(pc_dcfg_scan_in), + .func_scan_in(pc_func_scan_in), + .gptr_scan_out(pc_gptr_scan_out), + .ccfg_scan_out(pc_ccfg_scan_out), + .bcfg_scan_out(pc_bcfg_scan_out), + .dcfg_scan_out(pc_dcfg_scan_out), + .func_scan_out(pc_func_scan_out) + ); + + + + // DP Float + generate + if (float_type == 1) + begin : dp + fu + a_fuq( + //.gnd(gnd), + //.vcs(vcs), + //.vdd(vdd), + .nclk(nclk), + + .debug_bus_in(fu_debug_bus_in), + .debug_bus_out(fu_debug_bus_out), + .coretrace_ctrls_in(fu_coretrace_ctrls_in), + .coretrace_ctrls_out(fu_coretrace_ctrls_out), + .event_bus_in(fu_event_bus_in), + .event_bus_out(fu_event_bus_out), + + .gptr_scan_in(fu_gptr_scan_in), + .time_scan_in(fu_time_scan_in), + .repr_scan_in(fu_repr_scan_in), + .bcfg_scan_in(fu_bcfg_scan_in), + .ccfg_scan_in(fu_ccfg_scan_in), + .dcfg_scan_in(fu_dcfg_scan_in), + .func_scan_in(fu_func_scan_in), + .abst_scan_in(fu_abst_scan_in), + .gptr_scan_out(fu_gptr_scan_out), + .time_scan_out(fu_time_scan_out), + .repr_scan_out(fu_repr_scan_out), + .bcfg_scan_out(fu_bcfg_scan_out), + .ccfg_scan_out(fu_ccfg_scan_out), + .dcfg_scan_out(fu_dcfg_scan_out), + .func_scan_out(fu_func_scan_out), + .abst_scan_out(fu_abst_scan_out), + .tc_ac_scan_dis_dc_b(an_ac_scan_dis_dc_b), + .tc_ac_scan_diag_dc(an_ac_scan_diag_dc), + + .cp_flush(cp_flush), + .slowspr_addr_in(fu_slowspr_addr_in), + .slowspr_data_in(fu_slowspr_data_in), + .slowspr_done_in(fu_slowspr_done_in), + .slowspr_etid_in(fu_slowspr_etid_in), + .slowspr_rw_in(fu_slowspr_rw_in), + .slowspr_val_in(fu_slowspr_val_in), + .slowspr_addr_out(fu_slowspr_addr_out), + .slowspr_data_out(fu_slowspr_data_out), + .slowspr_done_out(fu_slowspr_done_out), + .slowspr_etid_out(fu_slowspr_etid_out), + .slowspr_rw_out(fu_slowspr_rw_out), + .slowspr_val_out(fu_slowspr_val_out), + + .cp_t0_next_itag(cp_t0_next_itag), + .cp_t1_next_itag(cp_t1_next_itag), + .cp_axu_i0_t1_v(cp_axu_i0_t1_v), + .cp_axu_i0_t0_t1_t(cp_axu_i0_t0_t1_t), + .cp_axu_i0_t0_t1_p(cp_axu_i0_t0_t1_p), + .cp_axu_i1_t0_t1_t(cp_axu_i1_t0_t1_t), + .cp_axu_i1_t0_t1_p(cp_axu_i1_t0_t1_p), + .cp_axu_i1_t1_v(cp_axu_i1_t1_v), + .cp_axu_i0_t1_t1_t(cp_axu_i0_t1_t1_t), + .cp_axu_i0_t1_t1_p(cp_axu_i0_t1_t1_p), + .cp_axu_i1_t1_t1_t(cp_axu_i1_t1_t1_t), + .cp_axu_i1_t1_t1_p(cp_axu_i1_t1_t1_p), + + .iu_xx_t0_zap_itag(iu_xx_t0_zap_itag), + .iu_xx_t1_zap_itag(iu_xx_t1_zap_itag), + .axu0_iu_async_fex(axu0_iu_async_fex), + .axu0_iu_perf_events(axu0_iu_perf_events), + .axu0_iu_exception(axu0_iu_exception), + .axu0_iu_exception_val(axu0_iu_exception_val), + .axu0_iu_execute_vld(axu0_iu_execute_vld), + .axu0_iu_flush2ucode(axu0_iu_flush2ucode), + .axu0_iu_flush2ucode_type(axu0_iu_flush2ucode_type), + .axu0_iu_itag(axu0_iu_itag), + .axu0_iu_n_flush(axu0_iu_n_flush), + .axu0_iu_n_np1_flush(axu0_iu_n_np1_flush), + .axu0_iu_np1_flush(axu0_iu_np1_flush), + .axu1_iu_perf_events(axu1_iu_perf_events), + .axu1_iu_exception(axu1_iu_exception), + .axu1_iu_exception_val(axu1_iu_exception_val), + .axu1_iu_execute_vld(axu1_iu_execute_vld), + .axu1_iu_flush2ucode(axu1_iu_flush2ucode), + .axu1_iu_flush2ucode_type(axu1_iu_flush2ucode_type), + .axu1_iu_itag(axu1_iu_itag), + .axu1_iu_np1_flush(axu1_iu_np1_flush), + .axu1_iu_n_flush(axu1_iu_n_flush), + + .lq_fu_ex4_eff_addr(lq_fu_ex4_eff_addr), + .lq_fu_ex5_load_le(lq_fu_ex5_load_le), + .lq_fu_ex5_load_data(lq_fu_ex5_load_data), + .lq_fu_ex5_load_tag(lq_fu_ex5_load_tag), + .lq_fu_ex5_load_val(lq_fu_ex5_load_val), + .lq_fu_ex5_abort(lq_fu_ex5_abort), + .lq_gpr_rel_we(lq_gpr_rel_we), + .lq_gpr_rel_le(lq_gpr_rel_le), + .lq_gpr_rel_wa(lq_gpr_rel_wa), + .lq_gpr_rel_wd(lq_gpr_rel_wd), + .lq_rv_itag0(lq_rv_itag0), + .lq_rv_itag0_vld(lq_rv_itag0_vld), + .lq_rv_itag0_spec(lq_rv_itag0_spec), + .lq_rv_itag1_restart(lq_rv_itag1_restart), + .fu_lq_ex2_store_data_val(fu_lq_ex2_store_data_val), + .fu_lq_ex2_store_itag(fu_lq_ex2_store_itag), + .fu_lq_ex3_store_data(fu_lq_ex3_store_data), + .fu_lq_ex3_sto_parity_err(fu_lq_ex3_sto_parity_err), + .fu_lq_ex3_abort(fu_lq_ex3_abort), + + .rv_axu0_vld(rv_axu0_vld), + .rv_axu0_ex0_instr(rv_axu0_ex0_instr), + .rv_axu0_ex0_itag(rv_axu0_ex0_itag), + .rv_axu0_ex0_ucode(rv_axu0_ex0_ucode), + .rv_axu0_ex0_t1_v(rv_axu0_ex0_t1_v), + .rv_axu0_ex0_t1_p(rv_axu0_ex0_t1_p), + .rv_axu0_ex0_t2_p(rv_axu0_ex0_t2_p), + .rv_axu0_ex0_t3_p(rv_axu0_ex0_t3_p), + .rv_axu0_s1_v(rv_axu0_s1_v), + .rv_axu0_s1_p(rv_axu0_s1_p), + .rv_axu0_s1_t(rv_axu0_s1_t), + .rv_axu0_s2_v(rv_axu0_s2_v), + .rv_axu0_s2_p(rv_axu0_s2_p), + .rv_axu0_s2_t(rv_axu0_s2_t), + .rv_axu0_s3_v(rv_axu0_s3_v), + .rv_axu0_s3_p(rv_axu0_s3_p), + .rv_axu0_s3_t(rv_axu0_s3_t), + .axu0_rv_ex2_s1_abort(axu0_rv_ex2_s1_abort), + .axu0_rv_ex2_s2_abort(axu0_rv_ex2_s2_abort), + .axu0_rv_ex2_s3_abort(axu0_rv_ex2_s3_abort), + .axu0_rv_itag(axu0_rv_itag), + .axu0_rv_itag_vld(axu0_rv_itag_vld), + .axu0_rv_itag_abort(axu0_rv_itag_abort), + .axu0_rv_ord_complete(axu0_rv_ord_complete), + .axu0_rv_hold_all(axu0_rv_hold_all), + .axu1_rv_itag(axu1_rv_itag), + .axu1_rv_itag_vld(axu1_rv_itag_vld), + .axu1_rv_itag_abort(axu1_rv_itag_abort), + .axu1_rv_hold_all(axu1_rv_hold_all), + + .pc_fu_ram_active(pc_fu_ram_active), + .fu_pc_ram_data(fu_pc_ram_data), + .fu_pc_ram_data_val(fu_pc_ram_data_val), + .pc_fu_trace_bus_enable(pc_fu_trace_bus_enable), + .pc_fu_debug_mux_ctrls(pc_fu_debug_mux_ctrls), + .pc_fu_instr_trace_mode(pc_fu_instr_trace_mode), + .pc_fu_instr_trace_tid(pc_fu_instr_trace_tid), + .pc_fu_event_bus_enable(pc_fu_event_bus_enable), + .pc_fu_event_count_mode(pc_fu_event_count_mode), + .pc_fu_inj_regfile_parity(pc_fu_inj_regfile_parity), + .fu_pc_err_regfile_parity(fu_pc_err_regfile_parity), + .fu_pc_err_regfile_ue(fu_pc_err_regfile_ue), + .an_ac_lbist_en_dc(an_ac_lbist_en_dc), + .pc_fu_ccflush_dc(pc_fu_ccflush_dc), + .pc_fu_gptr_sl_thold_3(pc_fu_gptr_sl_thold_3), + .pc_fu_time_sl_thold_3(pc_fu_time_sl_thold_3), + .pc_fu_repr_sl_thold_3(pc_fu_repr_sl_thold_3), + .pc_fu_cfg_sl_thold_3(pc_fu_cfg_sl_thold_3), + .pc_fu_cfg_slp_sl_thold_3(pc_fu_cfg_slp_sl_thold_3), + .pc_fu_func_nsl_thold_3(pc_fu_func_nsl_thold_3), + .pc_fu_func_sl_thold_3(pc_fu_func_sl_thold_3), + .pc_fu_func_slp_nsl_thold_3(pc_fu_func_slp_nsl_thold_3), + .pc_fu_func_slp_sl_thold_3(pc_fu_func_slp_sl_thold_3), + .pc_fu_abst_sl_thold_3(pc_fu_abst_sl_thold_3), + .pc_fu_abst_slp_sl_thold_3(pc_fu_abst_slp_sl_thold_3), + .pc_fu_ary_nsl_thold_3(pc_fu_ary_nsl_thold_3), + .pc_fu_ary_slp_nsl_thold_3(pc_fu_ary_slp_nsl_thold_3), + .pc_fu_sg_3(pc_fu_sg_3), + .pc_fu_fce_3(pc_fu_fce_3), + + .pc_fu_abist_di_0(pc_fu_abist_di_0), + .pc_fu_abist_di_1(pc_fu_abist_di_1), + .pc_fu_abist_ena_dc(pc_fu_abist_ena_dc), + .pc_fu_abist_grf_renb_0(pc_fu_abist_grf_renb_0), + .pc_fu_abist_grf_renb_1(pc_fu_abist_grf_renb_1), + .pc_fu_abist_grf_wenb_0(pc_fu_abist_grf_wenb_0), + .pc_fu_abist_grf_wenb_1(pc_fu_abist_grf_wenb_1), + .pc_fu_abist_raddr_0(pc_fu_abist_raddr_0), + .pc_fu_abist_raddr_1(pc_fu_abist_raddr_1), + .pc_fu_abist_raw_dc_b(pc_fu_abist_raw_dc_b), + .pc_fu_abist_waddr_0(pc_fu_abist_waddr_0), + .pc_fu_abist_waddr_1(pc_fu_abist_waddr_1), + .pc_fu_abist_wl144_comp_ena(pc_fu_abist_wl144_comp_ena), + + .xu_fu_msr_fe0(xu_fu_msr_fe0), + .xu_fu_msr_fe1(xu_fu_msr_fe1), + .xu_fu_msr_fp(xu_fu_msr_fp), + .xu_fu_msr_pr(xu_fu_msr_pr), + .xu_fu_msr_gs(xu_fu_msr_gs), + .axu0_cr_w4e(axu0_cr_w4e), + .axu0_cr_w4a(axu0_cr_w4a), + .axu0_cr_w4d(axu0_cr_w4d) + + ); + end + endgenerate + // end component a_fuq + + // No Float! + generate + if (float_type == 0) + begin : nf + assign axu0_iu_execute_vld = {`THREADS{1'b0}}; + assign axu0_iu_itag = {`ITAG_SIZE_ENC{1'b0}}; + assign axu0_iu_n_flush = 1'b0; + assign axu0_iu_np1_flush = 1'b0; + assign axu0_iu_exception = {4{1'b0}}; + assign axu0_iu_exception_val = 1'b0; + assign axu0_iu_flush2ucode = 1'b0; + assign axu0_iu_flush2ucode_type = 1'b0; + assign axu0_iu_async_fex = {`THREADS{1'b0}}; + assign axu0_iu_perf_events = {4{1'b0}}; + + assign axu1_iu_execute_vld = {`THREADS{1'b0}}; + assign axu1_iu_itag = {`ITAG_SIZE_ENC{1'b0}}; + assign axu1_iu_n_flush = 1'b0; + assign axu1_iu_np1_flush = 1'b0; + assign axu1_iu_exception = {4{1'b0}}; + assign axu1_iu_exception_val = 1'b0; + assign axu1_iu_flush2ucode = 1'b0; + assign axu1_iu_flush2ucode_type = 1'b0; + assign axu1_iu_perf_events = {4{1'b0}}; + + assign axu0_rv_itag_vld = {`THREADS{1'b0}}; + assign axu1_rv_itag_vld = {`THREADS{1'b0}}; + + assign fu_slowspr_val_out = fu_slowspr_val_in; + assign fu_slowspr_rw_out = fu_slowspr_rw_in; + assign fu_slowspr_etid_out = fu_slowspr_etid_in; + assign fu_slowspr_addr_out = fu_slowspr_addr_in; + assign fu_slowspr_data_out = fu_slowspr_data_in; + assign fu_slowspr_done_out = fu_slowspr_done_in; + + assign fu_debug_bus_out = fu_debug_bus_in; + assign fu_coretrace_ctrls_out = fu_coretrace_ctrls_in; + + assign fu_event_bus_out = fu_event_bus_in; + + assign fu_pc_err_regfile_parity = {`THREADS{1'b0}}; + assign fu_pc_err_regfile_ue = {`THREADS{1'b0}}; + + assign fu_lq_ex3_abort = 1'b0; + assign axu0_rv_ex2_s1_abort = 1'b0; + assign axu0_rv_ex2_s2_abort = 1'b0; + assign axu0_rv_ex2_s3_abort = 1'b0; + + assign fu_pc_ram_data_val = 1'b0; + end + endgenerate + +endmodule diff --git a/dev/verilog/work/c_perv_rp.v b/dev/verilog/work/c_perv_rp.v new file mode 100755 index 0000000..3a59c5a --- /dev/null +++ b/dev/verilog/work/c_perv_rp.v @@ -0,0 +1,704 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: Pervasive Repower Logic + +(* recursive_synthesis="0" *) +module c_perv_rp( +// Include model build parameters +`include "tri_a2o.vh" + +// inout vdd, +// inout gnd, + input [0:`NCLK_WIDTH-1] nclk, + //CLOCK CONTROLS + //Top level clock controls + input an_ac_ccflush_dc, + input rtim_sl_thold_8, + input func_sl_thold_8, + input func_nsl_thold_8, + input ary_nsl_thold_8, + input sg_8, + input fce_8, + output rtim_sl_thold_7, + output func_sl_thold_7, + output func_nsl_thold_7, + output ary_nsl_thold_7, + output sg_7, + output fce_7, + //Thold inputs from pcq clock controls + input pc_rp_ccflush_out_dc, + input pc_rp_gptr_sl_thold_4, + input pc_rp_time_sl_thold_4, + input pc_rp_repr_sl_thold_4, + input pc_rp_abst_sl_thold_4, + input pc_rp_abst_slp_sl_thold_4, + input pc_rp_regf_sl_thold_4, + input pc_rp_regf_slp_sl_thold_4, + input pc_rp_func_sl_thold_4, + input pc_rp_func_slp_sl_thold_4, + input pc_rp_cfg_sl_thold_4, + input pc_rp_cfg_slp_sl_thold_4, + input pc_rp_func_nsl_thold_4, + input pc_rp_func_slp_nsl_thold_4, + input pc_rp_ary_nsl_thold_4, + input pc_rp_ary_slp_nsl_thold_4, + input pc_rp_rtim_sl_thold_4, + input pc_rp_sg_4, + input pc_rp_fce_4, + //Thold outputs to the units + output rp_iu_ccflush_dc, + output rp_iu_gptr_sl_thold_3, + output rp_iu_time_sl_thold_3, + output rp_iu_repr_sl_thold_3, + output rp_iu_abst_sl_thold_3, + output rp_iu_abst_slp_sl_thold_3, + output rp_iu_regf_slp_sl_thold_3, + output rp_iu_func_sl_thold_3, + output rp_iu_func_slp_sl_thold_3, + output rp_iu_cfg_sl_thold_3, + output rp_iu_cfg_slp_sl_thold_3, + output rp_iu_func_nsl_thold_3, + output rp_iu_func_slp_nsl_thold_3, + output rp_iu_ary_nsl_thold_3, + output rp_iu_ary_slp_nsl_thold_3, + output rp_iu_sg_3, + output rp_iu_fce_3, + // + output rp_rv_ccflush_dc, + output rp_rv_gptr_sl_thold_3, + output rp_rv_time_sl_thold_3, + output rp_rv_repr_sl_thold_3, + output rp_rv_abst_sl_thold_3, + output rp_rv_abst_slp_sl_thold_3, + output rp_rv_func_sl_thold_3, + output rp_rv_func_slp_sl_thold_3, + output rp_rv_cfg_sl_thold_3, + output rp_rv_cfg_slp_sl_thold_3, + output rp_rv_func_nsl_thold_3, + output rp_rv_func_slp_nsl_thold_3, + output rp_rv_ary_nsl_thold_3, + output rp_rv_ary_slp_nsl_thold_3, + output rp_rv_sg_3, + output rp_rv_fce_3, + // + output rp_xu_ccflush_dc, + output rp_xu_gptr_sl_thold_3, + output rp_xu_time_sl_thold_3, + output rp_xu_repr_sl_thold_3, + output rp_xu_abst_sl_thold_3, + output rp_xu_abst_slp_sl_thold_3, + output rp_xu_regf_slp_sl_thold_3, + output rp_xu_func_sl_thold_3, + output rp_xu_func_slp_sl_thold_3, + output rp_xu_cfg_sl_thold_3, + output rp_xu_cfg_slp_sl_thold_3, + output rp_xu_func_nsl_thold_3, + output rp_xu_func_slp_nsl_thold_3, + output rp_xu_ary_nsl_thold_3, + output rp_xu_ary_slp_nsl_thold_3, + output rp_xu_sg_3, + output rp_xu_fce_3, + // + output rp_lq_ccflush_dc, + output rp_lq_gptr_sl_thold_3, + output rp_lq_time_sl_thold_3, + output rp_lq_repr_sl_thold_3, + output rp_lq_abst_sl_thold_3, + output rp_lq_abst_slp_sl_thold_3, + output rp_lq_regf_slp_sl_thold_3, + output rp_lq_func_sl_thold_3, + output rp_lq_func_slp_sl_thold_3, + output rp_lq_cfg_sl_thold_3, + output rp_lq_cfg_slp_sl_thold_3, + output rp_lq_func_nsl_thold_3, + output rp_lq_func_slp_nsl_thold_3, + output rp_lq_ary_nsl_thold_3, + output rp_lq_ary_slp_nsl_thold_3, + output rp_lq_sg_3, + output rp_lq_fce_3, + // + output rp_mm_ccflush_dc, + output rp_mm_gptr_sl_thold_3, + output rp_mm_time_sl_thold_3, + output rp_mm_repr_sl_thold_3, + output rp_mm_abst_sl_thold_3, + output rp_mm_abst_slp_sl_thold_3, + output rp_mm_func_sl_thold_3, + output rp_mm_func_slp_sl_thold_3, + output rp_mm_cfg_sl_thold_3, + output rp_mm_cfg_slp_sl_thold_3, + output rp_mm_func_nsl_thold_3, + output rp_mm_func_slp_nsl_thold_3, + output rp_mm_ary_nsl_thold_3, + output rp_mm_ary_slp_nsl_thold_3, + output rp_mm_sg_3, + output rp_mm_fce_3, + + //SCANRING REPOWERING + input pc_bcfg_scan_in, + output pc_bcfg_scan_in_q, + input pc_dcfg_scan_in, + output pc_dcfg_scan_in_q, + input pc_bcfg_scan_out, + output pc_bcfg_scan_out_q, + input pc_ccfg_scan_out, + output pc_ccfg_scan_out_q, + input pc_dcfg_scan_out, + output pc_dcfg_scan_out_q, + input [0:1] pc_func_scan_in, + output [0:1] pc_func_scan_in_q, + input [0:1] pc_func_scan_out, + output [0:1] pc_func_scan_out_q, + // + input fu_abst_scan_in, + output fu_abst_scan_in_q, + input fu_abst_scan_out, + output fu_abst_scan_out_q, + input fu_ccfg_scan_out, + output fu_ccfg_scan_out_q, + input fu_bcfg_scan_out, + output fu_bcfg_scan_out_q, + input fu_dcfg_scan_out, + output fu_dcfg_scan_out_q, + input [0:3] fu_func_scan_in, + output [0:3] fu_func_scan_in_q, + input [0:3] fu_func_scan_out, + output [0:3] fu_func_scan_out_q, + + //MISCELLANEOUS FUNCTIONAL SIGNALS + // node inputs going to pcq + input an_ac_scom_dch, + input an_ac_scom_cch, + input an_ac_checkstop, + input an_ac_debug_stop, + input [0:`THREADS-1] an_ac_pm_thread_stop, + input [0:`THREADS-1] an_ac_pm_fetch_halt, + // + output rp_pc_scom_dch_q, + output rp_pc_scom_cch_q, + output rp_pc_checkstop_q, + output rp_pc_debug_stop_q, + output [0:`THREADS-1] rp_pc_pm_thread_stop_q, + output [0:`THREADS-1] rp_pc_pm_fetch_halt_q, + // pcq outputs going to node + input pc_rp_scom_dch, + input pc_rp_scom_cch, + input [0:`THREADS-1] pc_rp_special_attn, + input [0:2] pc_rp_checkstop, + input [0:2] pc_rp_local_checkstop, + input [0:2] pc_rp_recov_err, + input pc_rp_trace_error, + input [0:`THREADS-1] pc_rp_pm_thread_running, + input pc_rp_power_managed, + input pc_rp_rvwinkle_mode, + input pc_rp_livelock_active, + // + output ac_an_scom_dch_q, + output ac_an_scom_cch_q, + output [0:`THREADS-1] ac_an_special_attn_q, + output [0:2] ac_an_checkstop_q, + output [0:2] ac_an_local_checkstop_q, + output [0:2] ac_an_recov_err_q, + output ac_an_trace_error_q, + output [0:`THREADS-1] ac_an_pm_thread_running_q, + output ac_an_power_managed_q, + output ac_an_rvwinkle_mode_q, + output ac_an_livelock_active_q, + + // SCAN CHAINS + input scan_diag_dc, + input scan_dis_dc_b, + input func_scan_in, + input gptr_scan_in, + output func_scan_out, + output gptr_scan_out +); + + +//===================================================================== +// Signal Declarations +//===================================================================== + // FUNC Scan Ring + parameter FUNC2_T0_SIZE = 23; + parameter FUNC2_T1_SIZE = 4 * (`THREADS - 1); + // start of func scan chain ordering + parameter FUNC2_T0_OFFSET = 0; + parameter FUNC2_T1_OFFSET = FUNC2_T0_OFFSET + FUNC2_T0_SIZE; + parameter FUNC_RIGHT = FUNC2_T1_OFFSET + FUNC2_T1_SIZE - 1; + // end of func scan chain ordering + + // Power signals + wire vdd; + wire gnd; + assign vdd = 1'b1; + assign gnd = 1'b0; + + // Clock and Scan Signals + wire [0:FUNC_RIGHT] func_siv; + wire [0:FUNC_RIGHT] func_sov; + // + wire slat_force; + wire func_slat_thold_b; + wire func_slat_d2clk; + wire [0:`NCLK_WIDTH-1] func_slat_lclk; + wire abst_slat_thold_b; + wire abst_slat_d2clk; + wire [0:`NCLK_WIDTH-1] abst_slat_lclk; + wire cfg_slat_thold_b; + wire cfg_slat_d2clk; + wire [0:`NCLK_WIDTH-1] cfg_slat_lclk; + // + wire sg_3_int; + wire func_sl_thold_3_int; + wire func_slp_sl_thold_3_int; + wire abst_sl_thold_3_int; + wire gptr_sl_thold_3_int; + wire cfg_sl_thold_3_int; + wire sg_2; + wire func_sl_thold_2; + wire func_slp_sl_thold_2; + wire abst_sl_thold_2; + wire gptr_sl_thold_2; + wire cfg_sl_thold_2; + wire sg_1; + wire func_sl_thold_1; + wire func_slp_sl_thold_1; + wire gptr_sl_thold_1; + wire abst_sl_thold_1; + wire cfg_sl_thold_1; + wire sg_0; + wire func_sl_thold_0; + wire func_sl_thold_0_b; + wire force_func; + wire func_slp_sl_thold_0; + wire func_slp_sl_thold_0_b; + wire force_func_slp; + wire gptr_sl_thold_0; + wire abst_sl_thold_0; + wire abst_sl_thold_0_b; + wire force_abst; + wire cfg_sl_thold_0; + // + wire clkoff_b; + wire act_dis; + wire d_mode; + wire [0:4] delay_lclkr; + wire [0:4] mpw1_b; + wire mpw2_b; + +// Get rid of sinkless net messages +(* analysis_not_referenced="true" *) + wire unused; + assign unused = pc_rp_regf_sl_thold_4 | pc_rp_rtim_sl_thold_4 | d_mode | (|delay_lclkr[1:4]) | (|mpw1_b[1:4]); + + +// ***************************************************************************** +// INTERNALLY USED CLOCK CONTROLS +// ***************************************************************************** + // Thold/Sg Staging latches + tri_plat #(.WIDTH(6)) perv_4to3_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(pc_rp_ccflush_out_dc), + + .din({pc_rp_func_sl_thold_4, pc_rp_func_slp_sl_thold_4, pc_rp_gptr_sl_thold_4, + pc_rp_abst_sl_thold_4, pc_rp_cfg_sl_thold_4, pc_rp_sg_4 }), + + .q( {func_sl_thold_3_int, func_slp_sl_thold_3_int, gptr_sl_thold_3_int, + abst_sl_thold_3_int, cfg_sl_thold_3_int, sg_3_int }) + ); + + tri_plat #(.WIDTH(6)) perv_3to2_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(pc_rp_ccflush_out_dc), + + .din({func_sl_thold_3_int, func_slp_sl_thold_3_int, gptr_sl_thold_3_int, + abst_sl_thold_3_int, cfg_sl_thold_3_int, sg_3_int }), + + .q( {func_sl_thold_2, func_slp_sl_thold_2, gptr_sl_thold_2, + abst_sl_thold_2, cfg_sl_thold_2, sg_2 }) + ); + + tri_plat #(.WIDTH(6)) perv_2to1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(pc_rp_ccflush_out_dc), + + .din({func_sl_thold_2, func_slp_sl_thold_2, gptr_sl_thold_2, + abst_sl_thold_2, cfg_sl_thold_2, sg_2 }), + + .q( {func_sl_thold_1, func_slp_sl_thold_1, gptr_sl_thold_1, + abst_sl_thold_1, cfg_sl_thold_1, sg_1 }) + ); + + tri_plat #(.WIDTH(6)) perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(pc_rp_ccflush_out_dc), + + .din({func_sl_thold_1, func_slp_sl_thold_1, gptr_sl_thold_1, + abst_sl_thold_1, cfg_sl_thold_1, sg_1 }), + + .q( {func_sl_thold_0, func_slp_sl_thold_0, gptr_sl_thold_0, + abst_sl_thold_0, cfg_sl_thold_0, sg_0 }) + ); + + // LCBCNTRL Macro + tri_lcbcntl_mac perv_lcbcntl( + .vdd(vdd), + .gnd(gnd), + .sg(sg_0), + .nclk(nclk), + .scan_in(gptr_scan_in), + .scan_diag_dc(scan_diag_dc), + .thold(gptr_sl_thold_0), + .clkoff_dc_b(clkoff_b), + .delay_lclkr_dc(delay_lclkr[0:4]), + .act_dis_dc(act_dis), + .d_mode_dc(d_mode), + .mpw1_dc_b(mpw1_b[0:4]), + .mpw2_dc_b(mpw2_b), + .scan_out(gptr_scan_out) + ); + + // LCBORs + tri_lcbor abst_lcbor( + .clkoff_b(clkoff_b), + .thold(abst_sl_thold_0), + .sg(sg_0), + .act_dis(act_dis), + .force_t(force_abst), + .thold_b(abst_sl_thold_0_b) + ); + + tri_lcbor func_lcbor( + .clkoff_b(clkoff_b), + .thold(func_sl_thold_0), + .sg(sg_0), + .act_dis(act_dis), + .force_t(force_func), + .thold_b(func_sl_thold_0_b) + ); + + tri_lcbor func_slp_lcbor( + .clkoff_b(clkoff_b), + .thold(func_slp_sl_thold_0), + .sg(sg_0), + .act_dis(act_dis), + .force_t(force_func_slp), + .thold_b(func_slp_sl_thold_0_b) + ); + + // LCBs for scan only staging latches + assign slat_force = sg_0; + assign func_slat_thold_b = (~func_sl_thold_0); + assign abst_slat_thold_b = (~abst_sl_thold_0); + assign cfg_slat_thold_b = (~cfg_sl_thold_0); + + tri_lcbs lcbs_func( + .vd(vdd), + .gd(gnd), + .delay_lclkr(delay_lclkr[0]), + .nclk(nclk), + .force_t(slat_force), + .thold_b(func_slat_thold_b), + .dclk(func_slat_d2clk), + .lclk(func_slat_lclk) + ); + + tri_lcbs lcbs_abst( + .vd(vdd), + .gd(gnd), + .delay_lclkr(delay_lclkr[0]), + .nclk(nclk), + .force_t(slat_force), + .thold_b(abst_slat_thold_b), + .dclk(abst_slat_d2clk), + .lclk(abst_slat_lclk) + ); + + tri_lcbs lcbs_cfg( + .vd(vdd), + .gd(gnd), + .delay_lclkr(delay_lclkr[0]), + .nclk(nclk), + .force_t(slat_force), + .thold_b(cfg_slat_thold_b), + .dclk(cfg_slat_d2clk), + .lclk(cfg_slat_lclk) + ); + +// ***************************************************************************** +// CLOCK REPOWERING LOGIC +// ***************************************************************************** + // Stages pcq clock control inputs + tri_plat #(.WIDTH(6)) pcq_lvl8to7( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(an_ac_ccflush_dc), + + .din({rtim_sl_thold_8, func_sl_thold_8, func_nsl_thold_8, + ary_nsl_thold_8, sg_8, fce_8 }), + + .q( {rtim_sl_thold_7, func_sl_thold_7, func_nsl_thold_7, + ary_nsl_thold_7, sg_7, fce_7 }) + ); + + // Other units use the ccflush signal after being gated for power-savings operation + assign rp_iu_ccflush_dc = pc_rp_ccflush_out_dc; + assign rp_rv_ccflush_dc = pc_rp_ccflush_out_dc; + assign rp_xu_ccflush_dc = pc_rp_ccflush_out_dc; + assign rp_lq_ccflush_dc = pc_rp_ccflush_out_dc; + assign rp_mm_ccflush_dc = pc_rp_ccflush_out_dc; + + // Clock control 4to3 output staging + tri_plat #(.WIDTH(16)) iu_clkstg_4to3( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(pc_rp_ccflush_out_dc), + + .din({pc_rp_gptr_sl_thold_4, pc_rp_time_sl_thold_4, pc_rp_repr_sl_thold_4, + pc_rp_abst_sl_thold_4, pc_rp_abst_slp_sl_thold_4, pc_rp_regf_slp_sl_thold_4, + pc_rp_func_sl_thold_4, pc_rp_func_slp_sl_thold_4, pc_rp_cfg_sl_thold_4, + pc_rp_cfg_slp_sl_thold_4, pc_rp_func_nsl_thold_4, pc_rp_func_slp_nsl_thold_4, + pc_rp_ary_nsl_thold_4, pc_rp_ary_slp_nsl_thold_4, pc_rp_sg_4, pc_rp_fce_4 }), + + .q( {rp_iu_gptr_sl_thold_3, rp_iu_time_sl_thold_3, rp_iu_repr_sl_thold_3, + rp_iu_abst_sl_thold_3, rp_iu_abst_slp_sl_thold_3, rp_iu_regf_slp_sl_thold_3, + rp_iu_func_sl_thold_3, rp_iu_func_slp_sl_thold_3, rp_iu_cfg_sl_thold_3, + rp_iu_cfg_slp_sl_thold_3, rp_iu_func_nsl_thold_3, rp_iu_func_slp_nsl_thold_3, + rp_iu_ary_nsl_thold_3, rp_iu_ary_slp_nsl_thold_3, rp_iu_sg_3, rp_iu_fce_3 }) + ); + + tri_plat #(.WIDTH(15)) rv_clkstg_4to3( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(pc_rp_ccflush_out_dc), + + .din({pc_rp_gptr_sl_thold_4, pc_rp_time_sl_thold_4, pc_rp_repr_sl_thold_4, + pc_rp_abst_sl_thold_4, pc_rp_abst_slp_sl_thold_4, pc_rp_func_sl_thold_4, + pc_rp_func_slp_sl_thold_4, pc_rp_cfg_sl_thold_4, pc_rp_cfg_slp_sl_thold_4, + pc_rp_func_nsl_thold_4, pc_rp_func_slp_nsl_thold_4, pc_rp_ary_nsl_thold_4, + pc_rp_ary_slp_nsl_thold_4, pc_rp_sg_4, pc_rp_fce_4 }), + + .q( {rp_rv_gptr_sl_thold_3, rp_rv_time_sl_thold_3, rp_rv_repr_sl_thold_3, + rp_rv_abst_sl_thold_3, rp_rv_abst_slp_sl_thold_3, rp_rv_func_sl_thold_3, + rp_rv_func_slp_sl_thold_3, rp_rv_cfg_sl_thold_3, rp_rv_cfg_slp_sl_thold_3, + rp_rv_func_nsl_thold_3, rp_rv_func_slp_nsl_thold_3, rp_rv_ary_nsl_thold_3, + rp_rv_ary_slp_nsl_thold_3, rp_rv_sg_3, rp_rv_fce_3 }) + ); + + tri_plat #(.WIDTH(16)) xu_clkstg_4to3( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(pc_rp_ccflush_out_dc), + + .din({pc_rp_gptr_sl_thold_4, pc_rp_time_sl_thold_4, pc_rp_repr_sl_thold_4, + pc_rp_abst_sl_thold_4, pc_rp_abst_slp_sl_thold_4, pc_rp_regf_slp_sl_thold_4, + pc_rp_func_sl_thold_4, pc_rp_func_slp_sl_thold_4, pc_rp_cfg_sl_thold_4, + pc_rp_cfg_slp_sl_thold_4, pc_rp_func_nsl_thold_4, pc_rp_func_slp_nsl_thold_4, + pc_rp_ary_nsl_thold_4, pc_rp_ary_slp_nsl_thold_4, pc_rp_sg_4, pc_rp_fce_4 }), + + .q( {rp_xu_gptr_sl_thold_3, rp_xu_time_sl_thold_3, rp_xu_repr_sl_thold_3, + rp_xu_abst_sl_thold_3, rp_xu_abst_slp_sl_thold_3, rp_xu_regf_slp_sl_thold_3, + rp_xu_func_sl_thold_3, rp_xu_func_slp_sl_thold_3, rp_xu_cfg_sl_thold_3, + rp_xu_cfg_slp_sl_thold_3, rp_xu_func_nsl_thold_3, rp_xu_func_slp_nsl_thold_3, + rp_xu_ary_nsl_thold_3, rp_xu_ary_slp_nsl_thold_3, rp_xu_sg_3, rp_xu_fce_3 }) + ); + + tri_plat #(.WIDTH(16)) lq_clkstg_4to3( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(pc_rp_ccflush_out_dc), + + .din({pc_rp_gptr_sl_thold_4, pc_rp_time_sl_thold_4, pc_rp_repr_sl_thold_4, + pc_rp_abst_sl_thold_4, pc_rp_abst_slp_sl_thold_4, pc_rp_regf_slp_sl_thold_4, + pc_rp_func_sl_thold_4, pc_rp_func_slp_sl_thold_4, pc_rp_cfg_sl_thold_4, + pc_rp_cfg_slp_sl_thold_4, pc_rp_func_nsl_thold_4, pc_rp_func_slp_nsl_thold_4, + pc_rp_ary_nsl_thold_4, pc_rp_ary_slp_nsl_thold_4, pc_rp_sg_4, pc_rp_fce_4 }), + + .q( {rp_lq_gptr_sl_thold_3, rp_lq_time_sl_thold_3, rp_lq_repr_sl_thold_3, + rp_lq_abst_sl_thold_3, rp_lq_abst_slp_sl_thold_3, rp_lq_regf_slp_sl_thold_3, + rp_lq_func_sl_thold_3, rp_lq_func_slp_sl_thold_3, rp_lq_cfg_sl_thold_3, + rp_lq_cfg_slp_sl_thold_3, rp_lq_func_nsl_thold_3, rp_lq_func_slp_nsl_thold_3, + rp_lq_ary_nsl_thold_3, rp_lq_ary_slp_nsl_thold_3, rp_lq_sg_3, rp_lq_fce_3 }) + ); + + tri_plat #(.WIDTH(15)) mm_clkstg_4to3( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(pc_rp_ccflush_out_dc), + + .din({pc_rp_gptr_sl_thold_4, pc_rp_time_sl_thold_4, pc_rp_repr_sl_thold_4, + pc_rp_abst_sl_thold_4, pc_rp_abst_slp_sl_thold_4, pc_rp_func_sl_thold_4, + pc_rp_func_slp_sl_thold_4, pc_rp_cfg_sl_thold_4, pc_rp_cfg_slp_sl_thold_4, + pc_rp_func_nsl_thold_4, pc_rp_func_slp_nsl_thold_4, pc_rp_ary_nsl_thold_4, + pc_rp_ary_slp_nsl_thold_4, pc_rp_sg_4, pc_rp_fce_4 }), + + .q( {rp_mm_gptr_sl_thold_3, rp_mm_time_sl_thold_3, rp_mm_repr_sl_thold_3, + rp_mm_abst_sl_thold_3, rp_mm_abst_slp_sl_thold_3, rp_mm_func_sl_thold_3, + rp_mm_func_slp_sl_thold_3, rp_mm_cfg_sl_thold_3, rp_mm_cfg_slp_sl_thold_3, + rp_mm_func_nsl_thold_3, rp_mm_func_slp_nsl_thold_3, rp_mm_ary_nsl_thold_3, + rp_mm_ary_slp_nsl_thold_3, rp_mm_sg_3, rp_mm_fce_3 }) + ); + +// ***************************************************************************** +// SCANRING REPOWERING +// ***************************************************************************** + // Staging latches for scan_in/out signals on abist rings + tri_slat_scan #(.WIDTH(2), .INIT(2'b00)) fu_abst_stg( + .vd(vdd), + .gd(gnd), + .dclk(abst_slat_d2clk), + .lclk(abst_slat_lclk), + .scan_in( {fu_abst_scan_in, fu_abst_scan_out }), + .scan_out({fu_abst_scan_in_q, fu_abst_scan_out_q }) + ); + + // Staging latches for scan_in/out signals on func rings + tri_slat_scan #(.WIDTH(4), .INIT(4'b0000)) pc_func_stg( + .vd(vdd), + .gd(gnd), + .dclk(func_slat_d2clk), + .lclk(func_slat_lclk), + .scan_in( {pc_func_scan_in[0:1], pc_func_scan_out[0:1] }), + .scan_out({pc_func_scan_in_q[0:1], pc_func_scan_out_q[0:1] }) + ); + + tri_slat_scan #(.WIDTH(8), .INIT(8'b00000000)) fu_func_stg( + .vd(vdd), + .gd(gnd), + .dclk(func_slat_d2clk), + .lclk(func_slat_lclk), + .scan_in( {fu_func_scan_in[0:3], fu_func_scan_out[0:3] }), + .scan_out({fu_func_scan_in_q[0:3], fu_func_scan_out_q[0:3] }) + ); + + // Staging latches for scan_in/out signals on config rings + tri_slat_scan #(.WIDTH(5), .INIT(5'b00000)) pc_cfg_stg( + .vd(vdd), + .gd(gnd), + .dclk(cfg_slat_d2clk), + .lclk(cfg_slat_lclk), + + .scan_in( {pc_bcfg_scan_in, pc_dcfg_scan_in, pc_bcfg_scan_out, + pc_ccfg_scan_out, pc_dcfg_scan_out }), + + .scan_out({pc_bcfg_scan_in_q, pc_dcfg_scan_in_q, pc_bcfg_scan_out_q, + pc_ccfg_scan_out_q, pc_dcfg_scan_out_q }) + ); + + tri_slat_scan #(.WIDTH(3), .INIT(3'b000)) fu_cfg_stg( + .vd(vdd), + .gd(gnd), + .dclk(cfg_slat_d2clk), + .lclk(cfg_slat_lclk), + .scan_in( {fu_bcfg_scan_out, fu_ccfg_scan_out, fu_dcfg_scan_out }), + .scan_out({fu_bcfg_scan_out_q, fu_ccfg_scan_out_q, fu_dcfg_scan_out_q }) + ); + +// ***************************************************************************** +// MISCELLANEOUS FUNCTIONAL SIGNALS +// ***************************************************************************** + tri_rlmreg_p #(.WIDTH(FUNC2_T0_SIZE), .INIT(0)) func2_t0_rp( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(1'b1), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .force_t(force_func_slp), + .delay_lclkr(delay_lclkr[0]), + .mpw1_b(mpw1_b[0]), + .mpw2_b(mpw2_b), + .scin(func_siv[ FUNC2_T0_OFFSET:FUNC2_T0_OFFSET + FUNC2_T0_SIZE - 1]), + .scout(func_sov[FUNC2_T0_OFFSET:FUNC2_T0_OFFSET + FUNC2_T0_SIZE - 1]), + + .din( {an_ac_scom_dch, an_ac_scom_cch, an_ac_checkstop, + an_ac_debug_stop, pc_rp_scom_dch, pc_rp_scom_cch, + pc_rp_checkstop, pc_rp_local_checkstop, pc_rp_recov_err, + pc_rp_power_managed, pc_rp_rvwinkle_mode, pc_rp_trace_error, + pc_rp_livelock_active, an_ac_pm_thread_stop[0], pc_rp_pm_thread_running[0], + pc_rp_special_attn[0], an_ac_pm_fetch_halt[0] }), + + .dout({rp_pc_scom_dch_q, rp_pc_scom_cch_q, rp_pc_checkstop_q, + rp_pc_debug_stop_q, ac_an_scom_dch_q, ac_an_scom_cch_q, + ac_an_checkstop_q, ac_an_local_checkstop_q, ac_an_recov_err_q, + ac_an_power_managed_q, ac_an_rvwinkle_mode_q, ac_an_trace_error_q, + ac_an_livelock_active_q, rp_pc_pm_thread_stop_q[0], ac_an_pm_thread_running_q[0], + ac_an_special_attn_q[0], rp_pc_pm_fetch_halt_q[0] }) + ); + + generate + if (`THREADS == 2) + begin : t1_rp + tri_rlmreg_p #(.WIDTH(FUNC2_T1_SIZE), .INIT(0)) func2_t1_rp( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(1'b1), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .force_t(force_func_slp), + .delay_lclkr(delay_lclkr[0]), + .mpw1_b(mpw1_b[0]), + .mpw2_b(mpw2_b), + .scin(func_siv[ FUNC2_T1_OFFSET:FUNC2_T1_OFFSET + FUNC2_T1_SIZE - 1]), + .scout(func_sov[FUNC2_T1_OFFSET:FUNC2_T1_OFFSET + FUNC2_T1_SIZE - 1]), + + .din( {an_ac_pm_thread_stop[1], pc_rp_pm_thread_running[1], pc_rp_special_attn[1], + an_ac_pm_fetch_halt[1] }), + .dout({rp_pc_pm_thread_stop_q[1], ac_an_pm_thread_running_q[1], ac_an_special_attn_q[1], + rp_pc_pm_fetch_halt_q[1] }) + ); + end + endgenerate + +// ***************************************************************************** +// SCAN RING CONNECTIONS +// ***************************************************************************** + //func ring + assign func_siv[0:FUNC_RIGHT] = {func_scan_in, func_sov[0:FUNC_RIGHT - 1]}; + assign func_scan_out = func_sov[FUNC_RIGHT] & scan_dis_dc_b; + + +endmodule diff --git a/dev/verilog/work/c_wrapper.v b/dev/verilog/work/c_wrapper.v new file mode 100755 index 0000000..2d028f4 --- /dev/null +++ b/dev/verilog/work/c_wrapper.v @@ -0,0 +1,533 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`define THREADS1 +`include "tri_a2o.vh" + +module c_wrapper( +// vcs, +// vdd, +// gnd, + clk, + clk2x, + clk4x, + reset, + an_ac_coreid, + an_ac_pm_thread_stop, + an_ac_ext_interrupt, + an_ac_crit_interrupt, + an_ac_perf_interrupt, + an_ac_external_mchk, + an_ac_flh2l2_gate, + an_ac_reservation_vld, + ac_an_debug_trigger, + an_ac_debug_stop, + an_ac_tb_update_enable, + an_ac_tb_update_pulse, + an_ac_hang_pulse, + ac_an_pm_thread_running, + ac_an_machine_check, + ac_an_recov_err, + ac_an_checkstop, + ac_an_local_checkstop, + + an_ac_stcx_complete, + an_ac_stcx_pass, + + an_ac_reld_data_vld, + an_ac_reld_core_tag, + an_ac_reld_data, + an_ac_reld_qw, + an_ac_reld_ecc_err, + an_ac_reld_ecc_err_ue, + an_ac_reld_data_coming, + + an_ac_reld_crit_qw, + an_ac_reld_l1_dump, + + an_ac_req_ld_pop, + an_ac_req_st_pop, + an_ac_req_st_gather, + an_ac_sync_ack, + + ac_an_req_pwr_token, + ac_an_req, + ac_an_req_ra, + ac_an_req_ttype, + ac_an_req_thread, + ac_an_req_wimg_w, + ac_an_req_wimg_i, + ac_an_req_wimg_m, + ac_an_req_wimg_g, + ac_an_req_user_defined, + ac_an_req_ld_core_tag, + ac_an_req_ld_xfr_len, + ac_an_st_byte_enbl, + ac_an_st_data, + ac_an_req_endian, + ac_an_st_data_pwr_token +); + + input clk; + input clk2x; + input clk4x; + input reset; + input [0:7] an_ac_coreid; + input [0:3] an_ac_pm_thread_stop; + input [0:3] an_ac_ext_interrupt; + input [0:3] an_ac_crit_interrupt; + input [0:3] an_ac_perf_interrupt; + input [0:3] an_ac_external_mchk; + input an_ac_flh2l2_gate; // Gate L1 Hit forwarding SPR config bit + input [0:3] an_ac_reservation_vld; + output [0:3] ac_an_debug_trigger; + input an_ac_debug_stop; + input an_ac_tb_update_enable; + input an_ac_tb_update_pulse; + input [0:3] an_ac_hang_pulse; + output [0:3] ac_an_pm_thread_running; + output [0:3] ac_an_machine_check; + output [0:2] ac_an_recov_err; + output [0:2] ac_an_checkstop; + output [0:2] ac_an_local_checkstop; + + wire scan_in; + wire scan_out; + + // Pervasive clock control + wire an_ac_rtim_sl_thold_8; + wire an_ac_func_sl_thold_8; + wire an_ac_func_nsl_thold_8; + wire an_ac_ary_nsl_thold_8; + wire an_ac_sg_8; + wire an_ac_fce_8; + wire [0:7] an_ac_abst_scan_in; + + // L2 STCX complete + input [0:3] an_ac_stcx_complete; + input [0:3] an_ac_stcx_pass; + + // ICBI ACK Interface + wire an_ac_icbi_ack; + wire [0:1] an_ac_icbi_ack_thread; + + // Back invalidate interface + wire an_ac_back_inv; + wire [22:63] an_ac_back_inv_addr; + wire [0:4] an_ac_back_inv_target; // connect to bit(0) + wire an_ac_back_inv_local; + wire an_ac_back_inv_lbit; + wire an_ac_back_inv_gs; + wire an_ac_back_inv_ind; + wire [0:7] an_ac_back_inv_lpar_id; + wire ac_an_back_inv_reject; + wire [0:7] ac_an_lpar_id; + + // L2 Reload Inputs + input an_ac_reld_data_vld; // reload data is coming next cycle + input [0:4] an_ac_reld_core_tag; // reload data destinatoin tag (which load queue) + input [0:127] an_ac_reld_data; // Reload Data + input [57:59] an_ac_reld_qw; // quadword address of reload data beat + input an_ac_reld_ecc_err; // Reload Data contains a Correctable ECC error + input an_ac_reld_ecc_err_ue; // Reload Data contains an Uncorrectable ECC error + input an_ac_reld_data_coming; + wire an_ac_reld_ditc; + input an_ac_reld_crit_qw; + input an_ac_reld_l1_dump; + wire [0:3] an_ac_req_spare_ctrl_a1; // spare control bits from L2 + + // load/store credit control + input an_ac_req_ld_pop; // credit for a load (L2 can take a load command) + input an_ac_req_st_pop; // credit for a store (L2 can take a store command) + input an_ac_req_st_gather; // credit for a store due to L2 gathering of store commands + input [0:3] an_ac_sync_ack; + + //SCOM Satellite + wire [0:3] an_ac_scom_sat_id; + wire an_ac_scom_dch; + wire an_ac_scom_cch; + wire ac_an_scom_dch; + wire ac_an_scom_cch; + + // FIR and Error Signals + wire [0:0] ac_an_special_attn; + wire ac_an_trace_error; + wire ac_an_livelock_active; + wire an_ac_checkstop; + + // Perfmon Event Bus + wire [0:3] ac_an_event_bus0; + wire [0:3] ac_an_event_bus1; + + // Reset related + wire an_ac_reset_1_complete; + wire an_ac_reset_2_complete; + wire an_ac_reset_3_complete; + wire an_ac_reset_wd_complete; + + // Power Management + wire [0:0] an_ac_pm_fetch_halt; + wire ac_an_power_managed; + wire ac_an_rvwinkle_mode; + + // Clock, Test, and LCB Controls + wire an_ac_gsd_test_enable_dc; + wire an_ac_gsd_test_acmode_dc; + wire an_ac_ccflush_dc; + wire an_ac_ccenable_dc; + wire an_ac_lbist_en_dc; + wire an_ac_lbist_ip_dc; + wire an_ac_lbist_ac_mode_dc; + wire an_ac_scan_diag_dc; + wire an_ac_scan_dis_dc_b; + + //Thold input to clock control macro + wire [0:8] an_ac_scan_type_dc; + + // Pervasive + wire ac_an_reset_1_request; + wire ac_an_reset_2_request; + wire ac_an_reset_3_request; + wire ac_an_reset_wd_request; + wire an_ac_lbist_ary_wrt_thru_dc; + wire [0:0] an_ac_sleep_en; + wire [0:3] an_ac_chipid_dc; + wire [0:0] an_ac_uncond_dbg_event; + wire [0:31] ac_an_debug_bus; + wire ac_an_coretrace_first_valid; // coretrace_ctrls[0] + wire ac_an_coretrace_valid; // coretrace_ctrls[1] + wire [0:1] ac_an_coretrace_type; // coretrace_ctrls[2:3] + + // L2 Outputs + output ac_an_req_pwr_token; // power token for command coming next cycle + output ac_an_req; // command request valid + output [22:63] ac_an_req_ra; // real address for request + output [0:5] ac_an_req_ttype; // command (transaction) type + output [0:2] ac_an_req_thread; // encoded thread ID + output ac_an_req_wimg_w; // write-through + output ac_an_req_wimg_i; // cache-inhibited + output ac_an_req_wimg_m; // memory coherence required + output ac_an_req_wimg_g; // guarded memory + output [0:3] ac_an_req_user_defined; // User Defined Bits + wire [0:3] ac_an_req_spare_ctrl_a0; // Spare bits + output [0:4] ac_an_req_ld_core_tag; // load command tag (which load Q) + output [0:2] ac_an_req_ld_xfr_len; // transfer length for non-cacheable load + output [0:31] ac_an_st_byte_enbl; // byte enables for store data + output [0:255] ac_an_st_data; // store data + output ac_an_req_endian; // endian mode (0=big endian, 1=little endian) + output ac_an_st_data_pwr_token; // store data power token + + + // constant EXPAND_TYPE : integer $ 1; + + wire clk_reset; + wire [0:15] rate; + wire [0:3] div2; + wire [0:3] div3; + wire [0:`NCLK_WIDTH-1] nclk; + wire [1:3] osc; + + + // component variable_osc + + // Pervasive clock control + + // L2 STCX complete + + // ICBI ACK Interface + + // Back invalidate interface + // connect to bit(0) + + // L2 Reload Inputs + // reload data is coming next cycle + // reload data destinatoin tag (which load queue) + // Reload Data + // quadword address of reload data beat + // Reload Data contains a Correctable ECC error + // Reload Data contains an Uncorrectable ECC error + // spare control bits from L2 + + // load/store credit control + // Gate L1 Hit forwarding SPR config bit + // credit for a load (L2 can take a load command) + // credit for a store (L2 can take a store command) + // credit for a store due to L2 gathering of store commands + + //SCOM Satellite + + // FIR and Error Signals + + // Perfmon Event Bus + + // Reset related + + // Power Management + + // Clock, Test, and LCB Controls + + //Thold input to clock control macro + + // PSRO Sensors + + // ABIST Engine + + // Bolt-On ABIST system interface + + // Pervasive + + // L2 Outputs + // power token for command coming next cycle + // command request valid + // real address for request + // command (transaction) type + // encoded thread ID + // write-through + // cache-inhibited + // memory coherence required + // guarded memory + // User Defined Bits + // Spare bits + // load command tag (which load Q) + // transfer length for non-cacheable load + // byte enables for store data + // store data + // endian mode (0=big endian, 1=little endian) + // store data power token + + assign rate = 16'b0000000100000000; + assign div2 = 4'b0010; + assign div3 = 4'b0100; + assign clk_reset = 1'b1; + + assign an_ac_ccflush_dc = 1'b0; + assign an_ac_rtim_sl_thold_8= 1'b0; + assign an_ac_func_sl_thold_8= 1'b0; + assign an_ac_func_nsl_thold_8= 1'b0; + assign an_ac_ary_nsl_thold_8= 1'b0; + assign an_ac_sg_8= 1'b0; + assign an_ac_fce_8= 1'b0; + assign scan_in = 'b0; + assign an_ac_abst_scan_in = 'b0; + assign an_ac_icbi_ack = 'b0; + assign an_ac_icbi_ack_thread = 'b0; + assign an_ac_back_inv = 'b0; + assign an_ac_back_inv_addr = 'b0; + assign an_ac_back_inv_target = 'b0; + assign an_ac_back_inv_local = 'b0; + assign an_ac_back_inv_lbit = 'b0; + assign an_ac_back_inv_gs = 'b0; + assign an_ac_back_inv_ind = 'b0; + assign an_ac_back_inv_lpar_id = 'b0; + assign an_ac_reld_ditc = 'b0; + assign an_ac_req_spare_ctrl_a1 = 'b0; + assign an_ac_scom_sat_id = 'b0; + assign an_ac_scom_dch = 'b0; + assign an_ac_scom_cch = 'b0; + assign an_ac_checkstop = 'b0; + assign an_ac_reset_1_complete = 'b0; + assign an_ac_reset_2_complete = 'b0; + assign an_ac_reset_3_complete = 'b0; + assign an_ac_reset_wd_complete = 'b0; + assign an_ac_pm_fetch_halt = 'b0; + assign an_ac_gsd_test_enable_dc = 'b0; + assign an_ac_gsd_test_acmode_dc = 'b0; + assign an_ac_ccflush_dc = 'b0; + assign an_ac_ccenable_dc = 'b0; + assign an_ac_lbist_en_dc = 'b0; + assign an_ac_lbist_ip_dc = 'b0; + assign an_ac_lbist_ac_mode_dc = 'b0; + assign an_ac_scan_diag_dc = 'b0; + assign an_ac_scan_dis_dc_b = 'b0; + assign an_ac_scan_type_dc = 'b0; + assign an_ac_lbist_ary_wrt_thru_dc = 'b0; + assign an_ac_sleep_en = 'b0; + assign an_ac_chipid_dc = 'b0; + assign an_ac_uncond_dbg_event = 'b0; + + assign nclk[0] = clk; + assign nclk[1] = reset; + assign nclk[2] = clk2x; + assign nclk[3] = clk4x; + assign nclk[4] = 'b0; + assign nclk[5] = 'b0; + + + + +(*dont_touch = "true" *) c c0( +// .vcs(vcs), +// .vdd(vdd), +// .gnd(gnd), + .nclk(nclk), + .scan_in(scan_in), + .scan_out(scan_out), + + // Pervasive clock control + .an_ac_rtim_sl_thold_8(an_ac_rtim_sl_thold_8), + .an_ac_func_sl_thold_8(an_ac_func_sl_thold_8), + .an_ac_func_nsl_thold_8(an_ac_func_nsl_thold_8), + .an_ac_ary_nsl_thold_8(an_ac_ary_nsl_thold_8), + .an_ac_sg_8(an_ac_sg_8), + .an_ac_fce_8(an_ac_fce_8), + .an_ac_abst_scan_in(an_ac_abst_scan_in), + + // L2 STCX complete + .an_ac_stcx_complete(an_ac_stcx_complete[0:`THREADS-1]), + .an_ac_stcx_pass(an_ac_stcx_pass[0:`THREADS-1]), + + // ICBI ACK Interface + .an_ac_icbi_ack(an_ac_icbi_ack), + .an_ac_icbi_ack_thread(an_ac_icbi_ack_thread), + + // Back invalidate interface + .an_ac_back_inv(an_ac_back_inv), + .an_ac_back_inv_addr(an_ac_back_inv_addr), + .an_ac_back_inv_target(an_ac_back_inv_target), + .an_ac_back_inv_local(an_ac_back_inv_local), + .an_ac_back_inv_lbit(an_ac_back_inv_lbit), + .an_ac_back_inv_gs(an_ac_back_inv_gs), + .an_ac_back_inv_ind(an_ac_back_inv_ind), + .an_ac_back_inv_lpar_id(an_ac_back_inv_lpar_id), + .ac_an_back_inv_reject(ac_an_back_inv_reject), + .ac_an_lpar_id(ac_an_lpar_id), + + // L2 Reload Inputs + .an_ac_reld_data_vld(an_ac_reld_data_vld), + .an_ac_reld_core_tag(an_ac_reld_core_tag), + .an_ac_reld_data(an_ac_reld_data), + .an_ac_reld_qw(an_ac_reld_qw[58:59]), + .an_ac_reld_ecc_err(an_ac_reld_ecc_err), + .an_ac_reld_ecc_err_ue(an_ac_reld_ecc_err_ue), + .an_ac_reld_data_coming(an_ac_reld_data_coming), + .an_ac_reld_ditc(an_ac_reld_ditc), + .an_ac_reld_crit_qw(an_ac_reld_crit_qw), + .an_ac_reld_l1_dump(an_ac_reld_l1_dump), + .an_ac_req_spare_ctrl_a1(an_ac_req_spare_ctrl_a1), + + // load/store credit control + .an_ac_flh2l2_gate(an_ac_flh2l2_gate), + .an_ac_req_ld_pop(an_ac_req_ld_pop), + .an_ac_req_st_pop(an_ac_req_st_pop), + .an_ac_req_st_gather(an_ac_req_st_gather), + .an_ac_sync_ack(an_ac_sync_ack[0:`THREADS-1]), + + //SCOM Satellite + .an_ac_scom_sat_id(an_ac_scom_sat_id), + .an_ac_scom_dch(an_ac_scom_dch), + .an_ac_scom_cch(an_ac_scom_cch), + .ac_an_scom_dch(ac_an_scom_dch), + .ac_an_scom_cch(ac_an_scom_cch), + + // FIR and Error Signals + .ac_an_special_attn(ac_an_special_attn), + .ac_an_checkstop(ac_an_checkstop), + .ac_an_local_checkstop(ac_an_local_checkstop), + .ac_an_recov_err(ac_an_recov_err), + .ac_an_trace_error(ac_an_trace_error), + .ac_an_livelock_active(ac_an_livelock_active), + .an_ac_checkstop(an_ac_checkstop), + .an_ac_external_mchk(an_ac_external_mchk[0:`THREADS-1]), + + // Perfmon Event Bus + .ac_an_event_bus0(ac_an_event_bus0), + .ac_an_event_bus1(ac_an_event_bus1), + + // Reset related + .an_ac_reset_1_complete(an_ac_reset_1_complete), + .an_ac_reset_2_complete(an_ac_reset_2_complete), + .an_ac_reset_3_complete(an_ac_reset_3_complete), + .an_ac_reset_wd_complete(an_ac_reset_wd_complete), + + // Power Management + .ac_an_pm_thread_running(ac_an_pm_thread_running[0:`THREADS-1]), + .an_ac_pm_thread_stop(an_ac_pm_thread_stop[0:`THREADS-1]), + .an_ac_pm_fetch_halt(an_ac_pm_fetch_halt), + .ac_an_power_managed(ac_an_power_managed), + .ac_an_rvwinkle_mode(ac_an_rvwinkle_mode), + + // Clock, Test, and LCB Controls + .an_ac_gsd_test_enable_dc(an_ac_gsd_test_enable_dc), + .an_ac_gsd_test_acmode_dc(an_ac_gsd_test_acmode_dc), + .an_ac_ccflush_dc(an_ac_ccflush_dc), + .an_ac_ccenable_dc(an_ac_ccenable_dc), + .an_ac_lbist_en_dc(an_ac_lbist_en_dc), + .an_ac_lbist_ip_dc(an_ac_lbist_ip_dc), + .an_ac_lbist_ac_mode_dc(an_ac_lbist_ac_mode_dc), + .an_ac_scan_diag_dc(an_ac_scan_diag_dc), + .an_ac_scan_dis_dc_b(an_ac_scan_dis_dc_b), + + //Thold input to clock control macro + .an_ac_scan_type_dc(an_ac_scan_type_dc), + + // Pervasive + .ac_an_reset_1_request(ac_an_reset_1_request), + .ac_an_reset_2_request(ac_an_reset_2_request), + .ac_an_reset_3_request(ac_an_reset_3_request), + .ac_an_reset_wd_request(ac_an_reset_wd_request), + .an_ac_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc), + .an_ac_reservation_vld(an_ac_reservation_vld[0:`THREADS-1]), + .an_ac_sleep_en(an_ac_sleep_en), + .an_ac_ext_interrupt(an_ac_ext_interrupt[0:`THREADS-1]), + .an_ac_crit_interrupt(an_ac_crit_interrupt[0:`THREADS-1]), + .an_ac_perf_interrupt(an_ac_perf_interrupt[0:`THREADS-1]), + .an_ac_hang_pulse(an_ac_hang_pulse[0:`THREADS-1]), + .an_ac_tb_update_enable(an_ac_tb_update_enable), + .an_ac_tb_update_pulse(an_ac_tb_update_pulse), + .an_ac_chipid_dc(an_ac_chipid_dc), + .an_ac_coreid(an_ac_coreid), + .ac_an_machine_check(ac_an_machine_check[0:`THREADS-1]), + .an_ac_debug_stop(an_ac_debug_stop), + .ac_an_debug_trigger(ac_an_debug_trigger[0:`THREADS-1]), + .an_ac_uncond_dbg_event(an_ac_uncond_dbg_event), + .ac_an_debug_bus(ac_an_debug_bus), + .ac_an_coretrace_first_valid(ac_an_coretrace_first_valid), + .ac_an_coretrace_valid(ac_an_coretrace_valid), + .ac_an_coretrace_type(ac_an_coretrace_type), + + // L2 Outputs + .ac_an_req_pwr_token(ac_an_req_pwr_token), + .ac_an_req(ac_an_req), + .ac_an_req_ra(ac_an_req_ra), + .ac_an_req_ttype(ac_an_req_ttype), + .ac_an_req_thread(ac_an_req_thread), + .ac_an_req_wimg_w(ac_an_req_wimg_w), + .ac_an_req_wimg_i(ac_an_req_wimg_i), + .ac_an_req_wimg_m(ac_an_req_wimg_m), + .ac_an_req_wimg_g(ac_an_req_wimg_g), + .ac_an_req_user_defined(ac_an_req_user_defined), + .ac_an_req_spare_ctrl_a0(ac_an_req_spare_ctrl_a0), + .ac_an_req_ld_core_tag(ac_an_req_ld_core_tag), + .ac_an_req_ld_xfr_len(ac_an_req_ld_xfr_len), + .ac_an_st_byte_enbl(ac_an_st_byte_enbl), + .ac_an_st_data(ac_an_st_data), + .ac_an_req_endian(ac_an_req_endian), + .ac_an_st_data_pwr_token(ac_an_st_data_pwr_token) + ); + +endmodule diff --git a/dev/verilog/work/fu.v b/dev/verilog/work/fu.v new file mode 100755 index 0000000..20bc552 --- /dev/null +++ b/dev/verilog/work/fu.v @@ -0,0 +1,1579 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//***************************************************************************** +//* +//* TITLE: fu +//* +//* NAME: fu.vhdl +//* +//* DESC: OO Top level Double Precision Floating Point Unit +//* +//***************************************************************************** + + `include "tri_a2o.vh" + + +module fu( + abst_scan_in, + an_ac_lbist_en_dc, + bcfg_scan_in, + ccfg_scan_in, + cp_axu_i0_t1_v, + cp_axu_i0_t0_t1_t, + cp_axu_i0_t1_t1_t, + cp_axu_i0_t0_t1_p, + cp_axu_i0_t1_t1_p, + cp_axu_i1_t1_v, + cp_axu_i1_t0_t1_t, + cp_axu_i1_t1_t1_t, + cp_axu_i1_t0_t1_p, + cp_axu_i1_t1_t1_p, + cp_flush, + cp_t0_next_itag, + cp_t1_next_itag, + + dcfg_scan_in, + func_scan_in, + gptr_scan_in, + iu_xx_t0_zap_itag, + iu_xx_t1_zap_itag, + + debug_bus_in, + coretrace_ctrls_in, + debug_bus_out, + coretrace_ctrls_out, + event_bus_in, + event_bus_out, + lq_fu_ex4_eff_addr, + lq_fu_ex5_load_data, + lq_fu_ex5_load_le, + lq_fu_ex5_load_tag, + lq_fu_ex5_load_val, + lq_fu_ex5_abort, + fu_lq_ex3_abort, + axu0_rv_ex2_s1_abort, + axu0_rv_ex2_s2_abort, + axu0_rv_ex2_s3_abort, + lq_gpr_rel_we, + lq_gpr_rel_le, + lq_gpr_rel_wa, + lq_gpr_rel_wd, + lq_rv_itag0, + lq_rv_itag0_spec, + lq_rv_itag0_vld, + lq_rv_itag1_restart, + nclk, + pc_fu_abist_di_0, + pc_fu_abist_di_1, + pc_fu_abist_ena_dc, + pc_fu_abist_grf_renb_0, + pc_fu_abist_grf_renb_1, + pc_fu_abist_grf_wenb_0, + pc_fu_abist_grf_wenb_1, + pc_fu_abist_raddr_0, + pc_fu_abist_raddr_1, + pc_fu_abist_raw_dc_b, + pc_fu_abist_waddr_0, + pc_fu_abist_waddr_1, + pc_fu_abist_wl144_comp_ena, + pc_fu_abst_sl_thold_3, + pc_fu_abst_slp_sl_thold_3, + pc_fu_ary_nsl_thold_3, + pc_fu_ary_slp_nsl_thold_3, + pc_fu_ccflush_dc, + pc_fu_cfg_sl_thold_3, + pc_fu_cfg_slp_sl_thold_3, + pc_fu_debug_mux_ctrls, + pc_fu_event_count_mode, + pc_fu_fce_3, + pc_fu_func_nsl_thold_3, + pc_fu_func_sl_thold_3, + pc_fu_func_slp_nsl_thold_3, + pc_fu_func_slp_sl_thold_3, + pc_fu_gptr_sl_thold_3, + pc_fu_inj_regfile_parity, + pc_fu_ram_active, + pc_fu_repr_sl_thold_3, + pc_fu_sg_3, + pc_fu_time_sl_thold_3, + pc_fu_trace_bus_enable, + pc_fu_event_bus_enable, + pc_fu_instr_trace_mode, + pc_fu_instr_trace_tid, + repr_scan_in, + + rv_axu0_ex0_instr, + rv_axu0_ex0_itag, + rv_axu0_s1_p, + rv_axu0_s1_t, + rv_axu0_s1_v, + rv_axu0_s2_p, + rv_axu0_s2_t, + rv_axu0_s2_v, + rv_axu0_s3_p, + rv_axu0_s3_t, + rv_axu0_s3_v, + rv_axu0_ex0_t1_p, + rv_axu0_ex0_t1_v, + rv_axu0_ex0_t2_p, + rv_axu0_ex0_t3_p, + rv_axu0_ex0_ucode, + rv_axu0_vld, + slowspr_addr_in, + slowspr_data_in, + slowspr_done_in, + slowspr_etid_in, + slowspr_rw_in, + slowspr_val_in, + tc_ac_scan_diag_dc, + tc_ac_scan_dis_dc_b, + time_scan_in, + + xu_fu_msr_fe0, + xu_fu_msr_fe1, + xu_fu_msr_fp, + xu_fu_msr_gs, + xu_fu_msr_pr, + +// gnd, +// vcs, +// vdd, + abst_scan_out, + axu0_cr_w4a, + axu0_cr_w4d, + axu0_cr_w4e, + axu0_iu_async_fex, + axu0_iu_exception, + axu0_iu_exception_val, + axu0_iu_execute_vld, + axu0_iu_flush2ucode, + axu0_iu_flush2ucode_type, + axu0_iu_itag, + axu0_iu_n_flush, + axu0_iu_n_np1_flush, + axu0_iu_np1_flush, + axu0_iu_perf_events, + axu0_rv_itag, + axu0_rv_itag_vld, + axu0_rv_itag_abort, + axu0_rv_ord_complete, + axu0_rv_hold_all, + + axu1_iu_exception, + axu1_iu_exception_val, + axu1_iu_execute_vld, + axu1_iu_flush2ucode, + axu1_iu_flush2ucode_type, + axu1_iu_itag, + axu1_iu_n_flush, + axu1_iu_np1_flush, + axu1_rv_itag, + axu1_rv_itag_vld, + axu1_rv_itag_abort, + axu1_iu_perf_events, + axu1_rv_hold_all, + + bcfg_scan_out, + ccfg_scan_out, + dcfg_scan_out, + fu_lq_ex2_store_data_val, + fu_lq_ex2_store_itag, + fu_lq_ex3_store_data, + fu_lq_ex3_sto_parity_err, + fu_pc_err_regfile_parity, + fu_pc_err_regfile_ue, + + fu_pc_ram_data, + fu_pc_ram_data_val, + + func_scan_out, + gptr_scan_out, + repr_scan_out, + slowspr_addr_out, + slowspr_data_out, + slowspr_done_out, + slowspr_etid_out, + slowspr_rw_out, + slowspr_val_out, + time_scan_out +); +// parameter expand_type = 2; // 0 - ibm tech, 1 - other, 2 - MPG); +// parameter EFF_IFAR = 20; +// parameter EFF_IFAR_WIDTH = 20; +// parameter ITAG_SIZE_ENC = 7; +// parameter THREADS = 2; +// parameter FPR_POOL_ENC = 6; +// parameter FPR_POOL = 64; +// parameter THREAD_POOL_ENC = 1; +// parameter CR_POOL_ENC = 5; +// parameter AXU_SPARE_ENC = 3; +// parameter UCODE_ENTRIES_ENC = 3; +// parameter REGMODE = 6; //32 or 64 bit mode + //INPUTS + input abst_scan_in; + input an_ac_lbist_en_dc; + input bcfg_scan_in; + input ccfg_scan_in; + + // Pass Thru Debug Trace Bus + // input [0:11] trace_triggers_in; + input [0:31] debug_bus_in; + input [0:3] coretrace_ctrls_in; + + // output [0:11] trace_triggers_out; + output [0:31] debug_bus_out; + output [0:3] coretrace_ctrls_out; + + input [0:4*`THREADS-1] event_bus_in; + output [0:4*`THREADS-1] event_bus_out; + + + input [0:`THREADS-1] cp_axu_i0_t1_v; + input [0:2] cp_axu_i0_t0_t1_t; + input [0:2] cp_axu_i0_t1_t1_t; + input [0:5] cp_axu_i0_t0_t1_p; + input [0:5] cp_axu_i0_t1_t1_p; + + input [0:`THREADS-1] cp_axu_i1_t1_v; + input [0:2] cp_axu_i1_t0_t1_t; + input [0:2] cp_axu_i1_t1_t1_t; + input [0:5] cp_axu_i1_t0_t1_p; + input [0:5] cp_axu_i1_t1_t1_p; + + + input [0:`THREADS-1] cp_flush; + input [0:6] cp_t0_next_itag; //: in std_ulogic_vector(0 to 6); + input [0:6] cp_t1_next_itag; //: in std_ulogic_vector(0 to 6); + + input dcfg_scan_in; + input [0:3] func_scan_in; + input gptr_scan_in; + input [0:6] iu_xx_t0_zap_itag; + input [0:6] iu_xx_t1_zap_itag; + + input [59:63] lq_fu_ex4_eff_addr; + input [192:255] lq_fu_ex5_load_data; + input lq_fu_ex5_load_le; + input [0:7+`THREADS] lq_fu_ex5_load_tag; // 0 to 9 for 2 threads + input lq_fu_ex5_load_val; + + input lq_fu_ex5_abort; + output fu_lq_ex3_abort; + output axu0_rv_ex2_s1_abort; + output axu0_rv_ex2_s2_abort; + output axu0_rv_ex2_s3_abort; + + input lq_gpr_rel_we; + input lq_gpr_rel_le; + input [0:7+`THREADS] lq_gpr_rel_wa; + input [64:127] lq_gpr_rel_wd; // :out std_ulogic_vector((128-STQ_DATA_SIZE) to 127); + + input [0:`ITAG_SIZE_ENC-1] lq_rv_itag0; + input lq_rv_itag0_spec; + input lq_rv_itag0_vld; + input lq_rv_itag1_restart; + (* PIN_DATA="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) // nclk + input [0:`NCLK_WIDTH-1] nclk; + input [0:3] pc_fu_abist_di_0; + input [0:3] pc_fu_abist_di_1; + input pc_fu_abist_ena_dc; + input pc_fu_abist_grf_renb_0; + input pc_fu_abist_grf_renb_1; + input pc_fu_abist_grf_wenb_0; + input pc_fu_abist_grf_wenb_1; + input [0:9] pc_fu_abist_raddr_0; + input [0:9] pc_fu_abist_raddr_1; + input pc_fu_abist_raw_dc_b; + input [0:9] pc_fu_abist_waddr_0; + input [0:9] pc_fu_abist_waddr_1; + input pc_fu_abist_wl144_comp_ena; + input pc_fu_abst_sl_thold_3; + input pc_fu_abst_slp_sl_thold_3; + input pc_fu_ary_nsl_thold_3; + input pc_fu_ary_slp_nsl_thold_3; + input pc_fu_ccflush_dc; + input pc_fu_cfg_sl_thold_3; + input pc_fu_cfg_slp_sl_thold_3; + input [0:10] pc_fu_debug_mux_ctrls; + input [0:2] pc_fu_event_count_mode; + input pc_fu_fce_3; + input pc_fu_func_nsl_thold_3; + input [0:1] pc_fu_func_sl_thold_3; + input pc_fu_func_slp_nsl_thold_3; + input [0:1] pc_fu_func_slp_sl_thold_3; + input pc_fu_gptr_sl_thold_3; + input [0:`THREADS-1] pc_fu_inj_regfile_parity; + input [0:`THREADS-1] pc_fu_ram_active; + input pc_fu_repr_sl_thold_3; + input [0:1] pc_fu_sg_3; + input pc_fu_time_sl_thold_3; + input pc_fu_trace_bus_enable; + input pc_fu_event_bus_enable; + input pc_fu_instr_trace_mode; + input [0:1] pc_fu_instr_trace_tid; + + input repr_scan_in; + + input [0:31] rv_axu0_ex0_instr; + input [0:`ITAG_SIZE_ENC-1] rv_axu0_ex0_itag; + input [0:`FPR_POOL_ENC-1] rv_axu0_s1_p; + input [0:2] rv_axu0_s1_t; + input rv_axu0_s1_v; + input [0:`FPR_POOL_ENC-1] rv_axu0_s2_p; + input [0:2] rv_axu0_s2_t; + input rv_axu0_s2_v; + input [0:`FPR_POOL_ENC-1] rv_axu0_s3_p; + input [0:2] rv_axu0_s3_t; + input rv_axu0_s3_v; + input [0:`FPR_POOL_ENC-1] rv_axu0_ex0_t1_p; + input rv_axu0_ex0_t1_v; + input [0:`FPR_POOL_ENC-1] rv_axu0_ex0_t2_p; + input [0:`FPR_POOL_ENC-1] rv_axu0_ex0_t3_p; + input [0:2] rv_axu0_ex0_ucode; + input [0:`THREADS-1] rv_axu0_vld; + input [0:9] slowspr_addr_in; + input [64-(2**`REGMODE):63] slowspr_data_in; + input slowspr_done_in; + input [0:1] slowspr_etid_in; + input slowspr_rw_in; + input slowspr_val_in; + input tc_ac_scan_diag_dc; + input tc_ac_scan_dis_dc_b; + input time_scan_in; + + input [0:`THREADS-1] xu_fu_msr_fe0; + input [0:`THREADS-1] xu_fu_msr_fe1; + input [0:`THREADS-1] xu_fu_msr_fp; + input [0:`THREADS-1] xu_fu_msr_gs; + input [0:`THREADS-1] xu_fu_msr_pr; + + + //OUTPUTS + output abst_scan_out; + output [0:`CR_POOL_ENC+`THREAD_POOL_ENC-1] axu0_cr_w4a; //: out std_ulogic_vector(0 to 4); + output [0:3] axu0_cr_w4d; + output axu0_cr_w4e; + output [0:`THREADS-1] axu0_iu_async_fex; + output [0:3] axu0_iu_perf_events; + + output [0:3] axu0_iu_exception; + output axu0_iu_exception_val; + output [0:`THREADS-1] axu0_iu_execute_vld; + output axu0_iu_flush2ucode; + output axu0_iu_flush2ucode_type; + output [0:`ITAG_SIZE_ENC-1] axu0_iu_itag; + output axu0_iu_n_flush; + output axu0_iu_n_np1_flush; + output axu0_iu_np1_flush; + output [0:`ITAG_SIZE_ENC-1] axu0_rv_itag; + output [0:`THREADS-1] axu0_rv_itag_vld; + output axu0_rv_itag_abort; + output axu0_rv_ord_complete; + output axu0_rv_hold_all; + + output [0:3] axu1_iu_exception; + output axu1_iu_exception_val; + output [0:`THREADS-1] axu1_iu_execute_vld; + output axu1_iu_flush2ucode; + output axu1_iu_flush2ucode_type; + output [0:`ITAG_SIZE_ENC-1] axu1_iu_itag; + output axu1_iu_n_flush; + output axu1_iu_np1_flush; + output [0:`ITAG_SIZE_ENC-1] axu1_rv_itag; + output [0:`THREADS-1] axu1_rv_itag_vld; + output axu1_rv_itag_abort; + output [0:3] axu1_iu_perf_events; + output axu1_rv_hold_all; + + output bcfg_scan_out; + output ccfg_scan_out; + output dcfg_scan_out; + output [0:`THREADS-1] fu_lq_ex2_store_data_val; + output [0:`ITAG_SIZE_ENC-1] fu_lq_ex2_store_itag; + output [0:63] fu_lq_ex3_store_data; + output fu_lq_ex3_sto_parity_err; + + output [0:`THREADS-1] fu_pc_err_regfile_parity; + output [0:`THREADS-1] fu_pc_err_regfile_ue; + + output [0:63] fu_pc_ram_data; + output fu_pc_ram_data_val; + + output [0:3] func_scan_out; + output gptr_scan_out; + output repr_scan_out; + output [0:9] slowspr_addr_out; + output [64-(2**`REGMODE):63] slowspr_data_out; + output slowspr_done_out; + output [0:1] slowspr_etid_out; + output slowspr_rw_out; + output slowspr_val_out; + output time_scan_out; + + + // ###################### CONSTANTS ###################### -- + + // ####################### SIGNALS ####################### -- + wire vdd; + wire gnd; + wire vcs; + + + wire abst_sl_thold_1; + wire act_dis; + wire ary_nsl_thold_1; + wire cfg_sl_thold_1; + wire clkoff_dc_b; + wire gptr_scan_io; + wire [0:9] delay_lclkr_dc; + wire [0:3] f_add_ex5_fpcc_iu; + wire [1:11] f_byp_ex1_s_expo; + wire [0:52] f_byp_ex1_s_frac; + wire f_byp_ex1_s_sign; + wire f_dcd_ex1_act; + wire f_dcd_ex1_aop_valid; + wire f_dcd_ex1_bop_valid; + wire [0:1] f_dcd_ex1_thread; + wire f_dcd_ex1_bypsel_a_load0; + wire f_dcd_ex1_bypsel_a_load1; + wire f_dcd_ex1_bypsel_a_load2; + wire f_dcd_ex1_bypsel_a_reload0; + wire f_dcd_ex1_bypsel_a_reload1; + wire f_dcd_ex1_bypsel_a_reload2; + + wire f_dcd_ex1_bypsel_a_res0; + wire f_dcd_ex1_bypsel_a_res1; + wire f_dcd_ex1_bypsel_a_res2; + wire f_dcd_ex1_bypsel_b_load0; + wire f_dcd_ex1_bypsel_b_load1; + wire f_dcd_ex1_bypsel_b_load2; + wire f_dcd_ex1_bypsel_b_reload0; + wire f_dcd_ex1_bypsel_b_reload1; + wire f_dcd_ex1_bypsel_b_reload2; + + wire f_dcd_ex1_bypsel_b_res0; + wire f_dcd_ex1_bypsel_b_res1; + wire f_dcd_ex1_bypsel_b_res2; + wire f_dcd_ex1_bypsel_c_load0; + wire f_dcd_ex1_bypsel_c_load1; + wire f_dcd_ex1_bypsel_c_load2; + wire f_dcd_ex1_bypsel_c_reload0; + wire f_dcd_ex1_bypsel_c_reload1; + wire f_dcd_ex1_bypsel_c_reload2; + + wire f_dcd_ex1_bypsel_c_res0; + wire f_dcd_ex1_bypsel_c_res1; + wire f_dcd_ex1_bypsel_c_res2; + wire f_dcd_ex1_bypsel_s_load0; + wire f_dcd_ex1_bypsel_s_load1; + wire f_dcd_ex1_bypsel_s_load2; + wire f_dcd_ex1_bypsel_s_reload0; + wire f_dcd_ex1_bypsel_s_reload1; + wire f_dcd_ex1_bypsel_s_reload2; + wire f_dcd_msr_fp_act; + + wire f_dcd_ex1_bypsel_s_res0; + wire f_dcd_ex1_bypsel_s_res1; + wire f_dcd_ex1_bypsel_s_res2; + wire f_dcd_ex1_compare_b; // fcomp* + wire f_dcd_ex1_cop_valid; + wire [0:4] f_dcd_ex1_divsqrt_cr_bf; + wire f_dcd_axucr0_deno; + + wire f_dcd_ex1_emin_dp; // prenorm_dp + wire f_dcd_ex1_emin_sp; // prenorm_sp, frsp + wire f_dcd_ex1_est_recip_b; // fres + wire f_dcd_ex1_est_rsqrt_b; // frsqrte + wire f_dcd_ex1_force_excp_dis; // + wire f_dcd_ex1_force_pass_b; // fmr,fnabbs,fabs,fneg,mtfsf + wire [0:5] f_dcd_ex1_fpscr_addr; + wire [0:3] f_dcd_ex1_fpscr_bit_data_b; // data to write to nibble (other than mtfsf) + wire [0:3] f_dcd_ex1_fpscr_bit_mask_b; // enable update of bit with the nibble + wire [0:8] f_dcd_ex1_fpscr_nib_mask_b; // enable update of this nibble + wire f_dcd_ex1_from_integer_b; // fcfid (signed integer) + wire f_dcd_ex1_frsp_b; // round-to-sgle-precision ?? need + wire f_dcd_ex1_fsel_b; // fsel + wire f_dcd_ex1_ftdiv; + wire f_dcd_ex1_ftsqrt; + wire [0:5] f_dcd_ex1_instr_frt; + wire [0:3] f_dcd_ex1_instr_tid; + wire f_dcd_ex1_inv_sign_b; // fnmsub fnmadd + wire [0:6] f_dcd_ex1_itag; + wire f_dcd_ex1_log2e_b; + wire f_dcd_ex1_math_b; // fmul,fmad,fmsub,fadd,fsub,fnmsub,fnmadd + wire f_dcd_ex1_mcrfs_b; // move fpscr field to cr and reset exceptions + wire f_dcd_ex1_move_b; // fmr,fneg,fabs,fnabs + wire f_dcd_ex1_mtfsbx_b; // fpscr set bit, reset bit + wire f_dcd_ex1_mtfsf_b; // move fpr data to fpscr + wire f_dcd_ex1_mtfsfi_b; // move immediate data to fpscr + wire f_dcd_ex1_mv_from_scr_b; // mffs + wire f_dcd_ex1_mv_to_scr_b; // mcrfs,mtfsf,mtfsfi,mtfsb0,mtfsb1 + wire f_dcd_ex1_nj_deni; // force output den to zero + wire f_dcd_ex1_nj_deno; // force output den to zero + wire [0:1] f_dcd_ex1_op_rnd_b; // roundg mode = positive infinity + wire f_dcd_ex1_op_rnd_v_b; // roundg mode = nearest + wire f_dcd_ex1_ordered_b; // fcompo + wire f_dcd_ex1_pow2e_b; + wire f_dcd_ex1_prenorm_b; // prenorm ?? need + wire f_dcd_ex1_rnd_to_int_b; // fri* + wire f_dcd_ex1_sgncpy_b; // for sgncpy instruction : + wire [0:1] f_dcd_ex1_sign_ctl_b; // 0:fmr/fneg 1:fneg/fnabs + wire f_dcd_ex1_sp; // off for frsp + wire f_dcd_ex1_sp_conv_b; // for sp/dp convert + wire f_dcd_ex1_sto_dp; + wire f_dcd_ex1_sto_sp; + wire f_dcd_ex1_sto_wd; + wire f_dcd_ex1_sub_op_b; // fsub, fnmsub, fmsub + wire [0:3] f_dcd_ex1_thread_b; + wire f_dcd_ex1_to_integer_b; // fcti* (signed integer 32/64) + wire f_dcd_ex1_uc_end; + wire f_dcd_ex1_uc_fa_pos; + wire f_dcd_ex1_uc_fb_0_5; + wire f_dcd_ex1_uc_fb_0_75; + wire f_dcd_ex1_uc_fb_1_0; + wire f_dcd_ex1_uc_fb_pos; + wire f_dcd_ex1_uc_fc_0_5; + wire f_dcd_ex1_uc_fc_1_0; + wire f_dcd_ex1_uc_fc_1_minus; + wire f_dcd_ex1_uc_fc_hulp; + wire f_dcd_ex1_uc_fc_pos; + wire f_dcd_ex1_uc_ft_neg; + wire f_dcd_ex1_uc_ft_pos; + wire f_dcd_ex1_uc_mid; + wire f_dcd_ex1_uc_special; + wire f_dcd_ex1_uns_b; // for converts unsigned + wire f_dcd_ex1_word_b; // fctiw* + wire f_dcd_ex2_divsqrt_v; + wire f_dcd_ex2_divsqrt_hole_v; + wire [0:1] f_dcd_ex3_uc_gs; + wire f_dcd_ex3_uc_gs_v; + wire f_dcd_ex3_uc_inc_lsb; + wire f_dcd_ex3_uc_vxidi; + wire f_dcd_ex3_uc_vxsnan; + wire f_dcd_ex3_uc_vxsqrt; + wire f_dcd_ex3_uc_vxzdz; + wire f_dcd_ex3_uc_zx; + wire [0:1] f_dcd_ex6_frt_tid; + wire f_dcd_ex7_cancel; + wire [0:5] f_dcd_ex7_fpscr_addr; + wire f_dcd_ex7_fpscr_wr; + wire [0:5] f_dcd_ex7_frt_addr; + wire [0:1] f_dcd_ex7_frt_tid; + wire f_dcd_ex7_frt_wen; + wire [0:1] f_dcd_flush; + wire [0:5] f_dcd_rf0_fra; + wire [0:5] f_dcd_rf0_frb; + wire [0:5] f_dcd_rf0_frc; + wire [0:1] f_dcd_rf0_tid; + wire f_dcd_ex0_div; + wire f_dcd_ex0_divs; + wire f_dcd_ex0_record_v; + wire f_dcd_ex0_sqrt; + wire f_dcd_ex0_sqrts; + wire f_dcd_si; + wire f_dcd_so; + wire [0:6] f_dsq_ex5_divsqrt_itag; + wire [0:1] f_dsq_ex5_divsqrt_v; + wire [0:4] f_dsq_ex6_divsqrt_cr_bf; + wire [0:5] f_dsq_ex6_divsqrt_fpscr_addr; + wire [0:5] f_dsq_ex6_divsqrt_instr_frt; + wire [0:3] f_dsq_ex6_divsqrt_instr_tid; + wire f_dsq_ex3_hangcounter_trigger_int; + wire f_dcd_rv_hold_all_int; + + + wire f_dsq_ex6_divsqrt_record_v; + wire [0:1] f_dsq_ex6_divsqrt_v; + wire f_dsq_ex6_divsqrt_v_suppress; + wire [0:63] f_dsq_debug; + + wire f_ex3_b_den_flush; + wire [1:13] f_fpr_ex1_a_expo; + wire [0:52] f_fpr_ex1_a_frac; + wire f_fpr_ex1_a_sign; + wire [1:13] f_fpr_ex1_b_expo; + wire [0:52] f_fpr_ex1_b_frac; + wire f_fpr_ex1_b_sign; + wire [1:13] f_fpr_ex1_c_expo; + wire [0:52] f_fpr_ex1_c_frac; + wire f_fpr_ex1_c_sign; + wire [1:11] f_fpr_ex1_s_expo; + wire [0:52] f_fpr_ex1_s_frac; + wire f_fpr_ex1_s_sign; + wire [0:7] f_fpr_ex2_a_par; + wire [0:7] f_fpr_ex2_b_par; + wire [0:7] f_fpr_ex2_c_par; + wire [0:1] f_fpr_ex2_s_expo_extra; + wire [0:7] f_fpr_ex2_s_par; + wire [0:7] f_fpr_ex6_load_addr; + wire [3:13] f_fpr_ex6_load_expo; + wire [0:52] f_fpr_ex6_load_frac; + wire f_fpr_ex6_load_sign; + wire f_fpr_ex6_load_v; + wire [3:13] f_fpr_ex7_load_expo; + wire [0:52] f_fpr_ex7_load_frac; + wire f_fpr_ex7_load_sign; + wire [3:13] f_fpr_ex8_load_expo; + wire [0:52] f_fpr_ex8_load_frac; + wire f_fpr_ex8_load_sign; + + wire [1:13] f_fpr_ex8_frt_expo; + wire [0:52] f_fpr_ex8_frt_frac; + wire f_fpr_ex8_frt_sign; + + + wire f_fpr_ex6_reload_v; + wire [0:7] f_fpr_ex6_reload_addr; + + wire [3:13] f_fpr_ex6_reload_expo; + wire [0:52] f_fpr_ex6_reload_frac; + wire f_fpr_ex6_reload_sign; + wire [3:13] f_fpr_ex7_reload_expo; + wire [0:52] f_fpr_ex7_reload_frac; + wire f_fpr_ex7_reload_sign; + wire [3:13] f_fpr_ex8_reload_expo; + wire [0:52] f_fpr_ex8_reload_frac; + wire f_fpr_ex8_reload_sign; + + wire f_dcd_ex1_sto_act; + wire f_dcd_ex1_sto_v; + wire f_dcd_ex1_mad_act; + + + wire [1:13] f_fpr_ex9_frt_expo; + wire [0:52] f_fpr_ex9_frt_frac; + wire f_fpr_ex9_frt_sign; + wire f_fpr_si; + wire f_fpr_so; + wire f_mad_ex3_a_parity_check; + wire f_mad_ex3_b_parity_check; + wire f_mad_ex3_c_parity_check; + wire f_mad_ex4_uc_res_sign; + wire [0:1] f_mad_ex4_uc_round_mode; + wire f_mad_ex4_uc_special; + wire f_mad_ex4_uc_vxidi; + wire f_mad_ex4_uc_vxsnan; + wire f_mad_ex4_uc_vxsqrt; + wire f_mad_ex4_uc_vxzdz; + wire f_mad_ex4_uc_zx; + wire f_mad_ex7_uc_sign; + wire f_mad_ex7_uc_zero; + wire [0:18] f_mad_si; + wire [0:18] f_mad_so; + wire f_pic_ex6_fpr_wr_dis_b; + wire f_pic_ex6_scr_upd_move_b; + wire [1:13] f_rnd_ex7_res_expo; + wire [0:52] f_rnd_ex7_res_frac; + wire f_rnd_ex7_res_sign; + wire f_rv_si; + wire f_rv_so; + wire [0:3] f_scr_cpl_fx_thread0; + wire [0:3] f_scr_cpl_fx_thread1; + wire [0:3] f_scr_ex8_cr_fld; + wire [0:3] f_scr_ex8_fx_thread0; + wire [0:3] f_scr_ex8_fx_thread1; + wire f_scr_ex6_fpscr_ni_thr0_int; + wire f_scr_ex6_fpscr_ni_thr1_int; + wire f_sto_ex3_s_parity_check; + wire f_sto_si; + wire f_sto_so; + wire fce_1; + wire fpu_enable; //dc_act + wire [0:1] func_sl_thold_1; + + wire gptr_sl_thold_0; + wire func_slp_sl_thold_1; + + wire [0:3] axu0_iu_perf_events_int; + wire [0:3] axu1_iu_perf_events_int; + + wire iu_fu_rf0_instr_match; + wire [0:`THREADS-1] iu_fu_rf0_instr_v; + wire [0:`THREADS-1] iu_fu_rf0_tid; + wire [0:6] iu_fu_ex0_itag; + wire [0:9] iu_fu_rf0_ldst_tag; + wire [0:9] mpw1_dc_b; + wire [0:1] mpw2_dc_b; + wire [0:1] sg_1; + wire tidn; + wire time_sl_thold_1; + wire tiup; + wire rf0_act_b; + + wire f_dcd_perr_sm_running; + wire f_dcd_ex2_perr_force_c; + wire f_dcd_ex2_perr_fsel_ovrd; + + //---------------------------------------------------------------------- + //------------------------------------------------------------------------------------------------- + //------------------------------------------------------------------------------------------------- + assign tidn = 1'b0; + assign tiup = 1'b1; + + assign vdd = 1'b1; + assign vcs = 1'b1; + assign gnd = 1'b0; + + + // TEMP TEMP todo + assign iu_fu_rf0_instr_match = tidn; + + generate + if (`THREADS == 1) + begin : addr_gen_1 + assign iu_fu_rf0_ldst_tag[0:9] = {4'b0000, rv_axu0_s3_p[0:5]}; + end + endgenerate + + generate + if (`THREADS == 2) + begin : addr_gen_2 + assign iu_fu_rf0_ldst_tag[0:9] = {3'b000, rv_axu0_s3_p[0:5], rv_axu0_vld[1]}; + end + endgenerate + + //---------------------------------------------------------------------- + // Floating Point Pervasive staging, lcbctrl's + + fu_perv prv( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .pc_fu_sg_3(pc_fu_sg_3), + .pc_fu_abst_sl_thold_3(pc_fu_abst_sl_thold_3), + .pc_fu_func_sl_thold_3(pc_fu_func_sl_thold_3), + .pc_fu_func_slp_sl_thold_3(pc_fu_func_slp_sl_thold_3), + .pc_fu_gptr_sl_thold_3(pc_fu_gptr_sl_thold_3), + .pc_fu_time_sl_thold_3(pc_fu_time_sl_thold_3), + .pc_fu_ary_nsl_thold_3(pc_fu_ary_nsl_thold_3), + .pc_fu_cfg_sl_thold_3(pc_fu_cfg_sl_thold_3), + .pc_fu_repr_sl_thold_3(pc_fu_repr_sl_thold_3), + .pc_fu_fce_3(pc_fu_fce_3), + .gptr_sl_thold_0(gptr_sl_thold_0), + .func_slp_sl_thold_1(func_slp_sl_thold_1), + .tc_ac_ccflush_dc(pc_fu_ccflush_dc), + .tc_ac_scan_diag_dc(tc_ac_scan_diag_dc), + .abst_sl_thold_1(abst_sl_thold_1), + .func_sl_thold_1(func_sl_thold_1), + .time_sl_thold_1(time_sl_thold_1), + .ary_nsl_thold_1(ary_nsl_thold_1), + .cfg_sl_thold_1(cfg_sl_thold_1), + .fce_1(fce_1), + .sg_1(sg_1), + .clkoff_dc_b(clkoff_dc_b), + .act_dis(act_dis), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .repr_scan_in(repr_scan_in), + .repr_scan_out(repr_scan_out), + .gptr_scan_in(gptr_scan_in), + .gptr_scan_out(gptr_scan_out) + ); + + //---------------------------------------------------------------------- + // Floating Point Register, ex0 + + fu_fpr #( .fpr_pool(`FPR_POOL * `THREADS), .fpr_pool_enc(`FPR_POOL_ENC + `THREAD_POOL_ENC), .axu_spare_enc(`AXU_SPARE_ENC), .threads(`THREADS)) fpr( + .nclk(nclk), + .clkoff_b(clkoff_dc_b), + .act_dis(act_dis), + .flush(pc_fu_ccflush_dc), + .delay_lclkra(delay_lclkr_dc[0:1]), + .delay_lclkrb(delay_lclkr_dc[6:7]), + .mpw1_ba(mpw1_dc_b[0:1]), + .mpw1_bb(mpw1_dc_b[6:7]), + .mpw2_b(mpw2_dc_b), + .sg_1(sg_1[1]), + .abst_sl_thold_1(abst_sl_thold_1), + .time_sl_thold_1(time_sl_thold_1), + .ary_nsl_thold_1(ary_nsl_thold_1), + .gptr_sl_thold_0(gptr_sl_thold_0), + .fce_1(fce_1), + .thold_1(func_sl_thold_1[1]), + .scan_dis_dc_b(tc_ac_scan_dis_dc_b), + .scan_diag_dc(tc_ac_scan_diag_dc), + .lbist_en_dc(an_ac_lbist_en_dc), + .f_fpr_si(f_fpr_si), + .f_fpr_so(f_fpr_so), + .f_fpr_ab_si(abst_scan_in), + .f_fpr_ab_so(abst_scan_out), + .time_scan_in(time_scan_in), + .time_scan_out(time_scan_out), + .vdd(vdd), + //.vcs(vcs), + .gnd(gnd), + .pc_fu_abist_di_0(pc_fu_abist_di_0), + .pc_fu_abist_di_1(pc_fu_abist_di_1), + .pc_fu_abist_ena_dc(pc_fu_abist_ena_dc), + .pc_fu_abist_grf_renb_0(pc_fu_abist_grf_renb_0), + .pc_fu_abist_grf_renb_1(pc_fu_abist_grf_renb_1), + .pc_fu_abist_grf_wenb_0(pc_fu_abist_grf_wenb_0), + .pc_fu_abist_grf_wenb_1(pc_fu_abist_grf_wenb_1), + .pc_fu_abist_raddr_0(pc_fu_abist_raddr_0), + .pc_fu_abist_raddr_1(pc_fu_abist_raddr_1), + .pc_fu_abist_raw_dc_b(pc_fu_abist_raw_dc_b), + .pc_fu_abist_waddr_0(pc_fu_abist_waddr_0), + .pc_fu_abist_waddr_1(pc_fu_abist_waddr_1), + .pc_fu_abist_wl144_comp_ena(pc_fu_abist_wl144_comp_ena), + .pc_fu_inj_regfile_parity(pc_fu_inj_regfile_parity), + .f_dcd_msr_fp_act(f_dcd_msr_fp_act), + .iu_fu_rf0_fra_v(rv_axu0_s1_v), + .iu_fu_rf0_frb_v(rv_axu0_s2_v), + .iu_fu_rf0_frc_v(rv_axu0_s3_v), + .iu_fu_rf0_str_v(tiup), //todo act + .iu_fu_rf0_tid(iu_fu_rf0_tid), + .f_dcd_rf0_fra(f_dcd_rf0_fra), + .f_dcd_rf0_frb(f_dcd_rf0_frb), + .f_dcd_rf0_frc(f_dcd_rf0_frc), + .f_dcd_rf0_tid(f_dcd_rf0_tid), + .iu_fu_rf0_ldst_tag(iu_fu_rf0_ldst_tag), + .f_dcd_ex7_frt_addr(f_dcd_ex7_frt_addr), + .f_dcd_ex6_frt_tid(f_dcd_ex6_frt_tid), + .f_dcd_ex7_frt_tid(f_dcd_ex7_frt_tid), + .f_dcd_ex7_frt_wen(f_dcd_ex7_frt_wen), + .f_rnd_ex7_res_expo(f_rnd_ex7_res_expo), + .f_rnd_ex7_res_frac(f_rnd_ex7_res_frac), + .f_rnd_ex7_res_sign(f_rnd_ex7_res_sign), + .xu_fu_ex5_load_tag(lq_fu_ex5_load_tag), + .xu_fu_ex5_load_val(lq_fu_ex5_load_val), + .xu_fu_ex5_load_data(lq_fu_ex5_load_data), + .lq_gpr_rel_we(lq_gpr_rel_we), + .lq_gpr_rel_le(lq_gpr_rel_le), + .lq_gpr_rel_wa(lq_gpr_rel_wa), + .lq_gpr_rel_wd(lq_gpr_rel_wd), + .f_fpr_ex6_load_addr(f_fpr_ex6_load_addr), + .f_fpr_ex6_load_v(f_fpr_ex6_load_v), + .f_fpr_ex6_reload_addr(f_fpr_ex6_reload_addr), + .f_fpr_ex6_reload_v(f_fpr_ex6_reload_v), + .f_fpr_ex6_load_sign(f_fpr_ex6_load_sign), + .f_fpr_ex6_load_expo(f_fpr_ex6_load_expo), + .f_fpr_ex6_load_frac(f_fpr_ex6_load_frac), + .f_fpr_ex7_load_sign(f_fpr_ex7_load_sign), + .f_fpr_ex7_load_expo(f_fpr_ex7_load_expo), + .f_fpr_ex7_load_frac(f_fpr_ex7_load_frac), + .f_fpr_ex8_load_sign(f_fpr_ex8_load_sign), + .f_fpr_ex8_load_expo(f_fpr_ex8_load_expo), + .f_fpr_ex8_load_frac(f_fpr_ex8_load_frac), + .f_fpr_ex6_reload_sign(f_fpr_ex6_reload_sign), + .f_fpr_ex6_reload_expo(f_fpr_ex6_reload_expo), + .f_fpr_ex6_reload_frac(f_fpr_ex6_reload_frac), + .f_fpr_ex7_reload_sign(f_fpr_ex7_reload_sign), + .f_fpr_ex7_reload_expo(f_fpr_ex7_reload_expo), + .f_fpr_ex7_reload_frac(f_fpr_ex7_reload_frac), + .f_fpr_ex8_reload_sign(f_fpr_ex8_reload_sign), + .f_fpr_ex8_reload_expo(f_fpr_ex8_reload_expo), + .f_fpr_ex8_reload_frac(f_fpr_ex8_reload_frac), + .f_fpr_ex1_s_sign(f_fpr_ex1_s_sign), + .f_fpr_ex1_s_expo(f_fpr_ex1_s_expo), + .f_fpr_ex1_s_frac(f_fpr_ex1_s_frac), + .f_fpr_ex1_a_sign(f_fpr_ex1_a_sign), + .f_fpr_ex1_a_expo(f_fpr_ex1_a_expo), + .f_fpr_ex1_a_frac(f_fpr_ex1_a_frac), + .f_fpr_ex1_c_sign(f_fpr_ex1_c_sign), + .f_fpr_ex1_c_expo(f_fpr_ex1_c_expo), + .f_fpr_ex1_c_frac(f_fpr_ex1_c_frac), + .f_fpr_ex1_b_sign(f_fpr_ex1_b_sign), + .f_fpr_ex1_b_expo(f_fpr_ex1_b_expo), + .f_fpr_ex1_b_frac(f_fpr_ex1_b_frac), + .f_fpr_ex8_frt_sign(f_fpr_ex8_frt_sign), + .f_fpr_ex8_frt_expo(f_fpr_ex8_frt_expo), + .f_fpr_ex8_frt_frac(f_fpr_ex8_frt_frac), + .f_fpr_ex9_frt_sign(f_fpr_ex9_frt_sign), + .f_fpr_ex9_frt_expo(f_fpr_ex9_frt_expo), + .f_fpr_ex9_frt_frac(f_fpr_ex9_frt_frac), + + .f_fpr_ex2_s_expo_extra(f_fpr_ex2_s_expo_extra), + .f_fpr_ex2_s_par(f_fpr_ex2_s_par), + .f_fpr_ex2_a_par(f_fpr_ex2_a_par), + .f_fpr_ex2_b_par(f_fpr_ex2_b_par), + .f_fpr_ex2_c_par(f_fpr_ex2_c_par) + ); + + //---------------------------------------------------------------------- + // Store + + fu_sto sto( + .vdd(vdd), + .gnd(gnd), + .clkoff_b(clkoff_dc_b), + .act_dis(act_dis), + .flush(pc_fu_ccflush_dc), + .delay_lclkr(delay_lclkr_dc[1:2]), + .mpw1_b(mpw1_dc_b[1:2]), + .mpw2_b(mpw2_dc_b[0:0]), + .sg_1(sg_1[1]), + .thold_1(func_sl_thold_1[1]), + .fpu_enable(fpu_enable), + .nclk(nclk), + .f_sto_si(f_sto_si), + .f_sto_so(f_sto_so), + .f_dcd_ex1_sto_act(f_dcd_ex1_sto_act), + .f_dcd_ex1_sto_v(f_dcd_ex1_sto_v), + .f_fpr_ex2_s_expo_extra(f_fpr_ex2_s_expo_extra), + .f_fpr_ex2_s_par(f_fpr_ex2_s_par), + .f_sto_ex3_s_parity_check(f_sto_ex3_s_parity_check), + .f_dcd_ex1_sto_dp(f_dcd_ex1_sto_dp), + .f_dcd_ex1_sto_sp(f_dcd_ex1_sto_sp), + .f_dcd_ex1_sto_wd(f_dcd_ex1_sto_wd), + .f_byp_ex1_s_sign(f_byp_ex1_s_sign), + .f_byp_ex1_s_expo(f_byp_ex1_s_expo), + .f_byp_ex1_s_frac(f_byp_ex1_s_frac), + .f_sto_ex3_sto_data(fu_lq_ex3_store_data) + ); + + //---------------------------------------------------------------------- + // Main Pipe + + assign fpu_enable = f_dcd_msr_fp_act; + + + + + fu_mad #( .THREADS(`THREADS)) mad( + .f_dcd_ex7_cancel(f_dcd_ex7_cancel), + .f_dcd_ex1_bypsel_a_res0(f_dcd_ex1_bypsel_a_res0), + .f_dcd_ex1_bypsel_a_res1(f_dcd_ex1_bypsel_a_res1), + .f_dcd_ex1_bypsel_a_res2(f_dcd_ex1_bypsel_a_res2), + .f_dcd_ex1_bypsel_a_load0(f_dcd_ex1_bypsel_a_load0), + .f_dcd_ex1_bypsel_a_load1(f_dcd_ex1_bypsel_a_load1), + .f_dcd_ex1_bypsel_a_load2(f_dcd_ex1_bypsel_a_load2), + .f_dcd_ex1_bypsel_a_reload0(f_dcd_ex1_bypsel_a_reload0), + .f_dcd_ex1_bypsel_a_reload1(f_dcd_ex1_bypsel_a_reload1), + .f_dcd_ex1_bypsel_a_reload2(f_dcd_ex1_bypsel_a_reload2), + + .f_dcd_ex1_bypsel_b_res0(f_dcd_ex1_bypsel_b_res0), + .f_dcd_ex1_bypsel_b_res1(f_dcd_ex1_bypsel_b_res1), + .f_dcd_ex1_bypsel_b_res2(f_dcd_ex1_bypsel_b_res2), + .f_dcd_ex1_bypsel_b_load0(f_dcd_ex1_bypsel_b_load0), + .f_dcd_ex1_bypsel_b_load1(f_dcd_ex1_bypsel_b_load1), + .f_dcd_ex1_bypsel_b_load2(f_dcd_ex1_bypsel_b_load2), + .f_dcd_ex1_bypsel_b_reload0(f_dcd_ex1_bypsel_b_reload0), + .f_dcd_ex1_bypsel_b_reload1(f_dcd_ex1_bypsel_b_reload1), + .f_dcd_ex1_bypsel_b_reload2(f_dcd_ex1_bypsel_b_reload2), + + .f_dcd_ex1_bypsel_c_res0(f_dcd_ex1_bypsel_c_res0), + .f_dcd_ex1_bypsel_c_res1(f_dcd_ex1_bypsel_c_res1), + .f_dcd_ex1_bypsel_c_res2(f_dcd_ex1_bypsel_c_res2), + .f_dcd_ex1_bypsel_c_load0(f_dcd_ex1_bypsel_c_load0), + .f_dcd_ex1_bypsel_c_load1(f_dcd_ex1_bypsel_c_load1), + .f_dcd_ex1_bypsel_c_load2(f_dcd_ex1_bypsel_c_load2), + .f_dcd_ex1_bypsel_c_reload0(f_dcd_ex1_bypsel_c_reload0), + .f_dcd_ex1_bypsel_c_reload1(f_dcd_ex1_bypsel_c_reload1), + .f_dcd_ex1_bypsel_c_reload2(f_dcd_ex1_bypsel_c_reload2), + + .f_dcd_ex1_bypsel_s_res0(f_dcd_ex1_bypsel_s_res0), + .f_dcd_ex1_bypsel_s_res1(f_dcd_ex1_bypsel_s_res1), + .f_dcd_ex1_bypsel_s_res2(f_dcd_ex1_bypsel_s_res2), + .f_dcd_ex1_bypsel_s_load0(f_dcd_ex1_bypsel_s_load0), + .f_dcd_ex1_bypsel_s_load1(f_dcd_ex1_bypsel_s_load1), + .f_dcd_ex1_bypsel_s_load2(f_dcd_ex1_bypsel_s_load2), + .f_dcd_ex1_bypsel_s_reload0(f_dcd_ex1_bypsel_s_reload0), + .f_dcd_ex1_bypsel_s_reload1(f_dcd_ex1_bypsel_s_reload1), + .f_dcd_ex1_bypsel_s_reload2(f_dcd_ex1_bypsel_s_reload2), + + .f_dcd_ex2_perr_force_c(f_dcd_ex2_perr_force_c), + .f_dcd_ex2_perr_fsel_ovrd(f_dcd_ex2_perr_fsel_ovrd), + + .f_fpr_ex1_s_sign(f_fpr_ex1_s_sign), + .f_fpr_ex1_s_expo(f_fpr_ex1_s_expo[1:11]), + .f_fpr_ex1_s_frac(f_fpr_ex1_s_frac), + .f_byp_ex1_s_sign(f_byp_ex1_s_sign), + .f_byp_ex1_s_expo(f_byp_ex1_s_expo[1:11]), + .f_byp_ex1_s_frac(f_byp_ex1_s_frac), + .f_dcd_ex1_force_excp_dis(f_dcd_ex1_force_excp_dis), + //---------------------------------------------- + .f_fpr_ex8_frt_sign(f_fpr_ex8_frt_sign), + .f_fpr_ex8_frt_expo(f_fpr_ex8_frt_expo[1:13]), + .f_fpr_ex8_frt_frac(f_fpr_ex8_frt_frac[0:52]), + .f_fpr_ex9_frt_sign(f_fpr_ex9_frt_sign), + .f_fpr_ex9_frt_expo(f_fpr_ex9_frt_expo[1:13]), + .f_fpr_ex9_frt_frac(f_fpr_ex9_frt_frac[0:52]), + + .f_fpr_ex6_load_sign(f_fpr_ex6_load_sign), + .f_fpr_ex6_load_expo(f_fpr_ex6_load_expo), + .f_fpr_ex6_load_frac(f_fpr_ex6_load_frac), + .f_fpr_ex7_load_sign(f_fpr_ex7_load_sign), + .f_fpr_ex7_load_expo(f_fpr_ex7_load_expo[3:13]), + .f_fpr_ex7_load_frac(f_fpr_ex7_load_frac[0:52]), + .f_fpr_ex8_load_sign(f_fpr_ex8_load_sign), + .f_fpr_ex8_load_expo(f_fpr_ex8_load_expo[3:13]), + .f_fpr_ex8_load_frac(f_fpr_ex8_load_frac[0:52]), + .f_fpr_ex6_reload_sign(f_fpr_ex6_reload_sign), + .f_fpr_ex6_reload_expo(f_fpr_ex6_reload_expo), + .f_fpr_ex6_reload_frac(f_fpr_ex6_reload_frac), + .f_fpr_ex7_reload_sign(f_fpr_ex7_reload_sign), + .f_fpr_ex7_reload_expo(f_fpr_ex7_reload_expo[3:13]), + .f_fpr_ex7_reload_frac(f_fpr_ex7_reload_frac[0:52]), + .f_fpr_ex8_reload_sign(f_fpr_ex8_reload_sign), + .f_fpr_ex8_reload_expo(f_fpr_ex8_reload_expo[3:13]), + .f_fpr_ex8_reload_frac(f_fpr_ex8_reload_frac[0:52]), + //---------------------------------------------- + + .f_fpr_ex1_a_sign(f_fpr_ex1_a_sign), + .f_fpr_ex1_a_expo(f_fpr_ex1_a_expo), + .f_fpr_ex1_a_frac(f_fpr_ex1_a_frac), + .f_fpr_ex1_c_sign(f_fpr_ex1_c_sign), + .f_fpr_ex1_c_expo(f_fpr_ex1_c_expo), + .f_fpr_ex1_c_frac(f_fpr_ex1_c_frac), + .f_fpr_ex1_b_sign(f_fpr_ex1_b_sign), + .f_fpr_ex1_b_expo(f_fpr_ex1_b_expo), + .f_fpr_ex1_b_frac(f_fpr_ex1_b_frac), + //---------------------------------------------- + .f_dcd_ex1_instr_frt(f_dcd_ex1_instr_frt), + .f_dcd_ex1_instr_tid(f_dcd_ex1_instr_tid), + .f_dsq_ex6_divsqrt_instr_frt(f_dsq_ex6_divsqrt_instr_frt), + .f_dsq_ex6_divsqrt_instr_tid(f_dsq_ex6_divsqrt_instr_tid), + .f_dsq_ex3_hangcounter_trigger(f_dsq_ex3_hangcounter_trigger_int), + .f_dcd_ex1_aop_valid(f_dcd_ex1_aop_valid), + .f_dcd_ex1_cop_valid(f_dcd_ex1_cop_valid), + .f_dcd_ex1_bop_valid(f_dcd_ex1_bop_valid), + .f_dcd_ex1_thread(f_dcd_ex1_thread), + .f_dcd_ex1_sp(f_dcd_ex1_sp), + .f_dcd_ex1_emin_dp(f_dcd_ex1_emin_dp), + .f_dcd_ex1_emin_sp(f_dcd_ex1_emin_sp), + .f_dcd_ex1_force_pass_b(f_dcd_ex1_force_pass_b), + .f_dcd_ex1_fsel_b(f_dcd_ex1_fsel_b), + .f_dcd_ex1_from_integer_b(f_dcd_ex1_from_integer_b), + .f_dcd_ex1_to_integer_b(f_dcd_ex1_to_integer_b), + .f_dcd_ex1_rnd_to_int_b(f_dcd_ex1_rnd_to_int_b), + .f_dcd_ex1_math_b(f_dcd_ex1_math_b), + .f_dcd_ex1_est_recip_b(f_dcd_ex1_est_recip_b), + .f_dcd_ex1_est_rsqrt_b(f_dcd_ex1_est_rsqrt_b), + .f_dcd_ex1_move_b(f_dcd_ex1_move_b), + .f_dcd_ex1_prenorm_b(f_dcd_ex1_prenorm_b), + .f_dcd_ex1_frsp_b(f_dcd_ex1_frsp_b), + .f_dcd_ex1_compare_b(f_dcd_ex1_compare_b), + .f_dcd_ex1_ordered_b(f_dcd_ex1_ordered_b), + .f_dcd_ex1_nj_deni(f_dcd_ex1_nj_deni), + .f_dcd_ex1_nj_deno(f_dcd_ex1_nj_deno), + .f_dcd_ex1_sp_conv_b(f_dcd_ex1_sp_conv_b), + .f_dcd_ex1_word_b(f_dcd_ex1_word_b), + .f_dcd_ex1_uns_b(f_dcd_ex1_uns_b), + .f_dcd_ex1_sub_op_b(f_dcd_ex1_sub_op_b), + .f_dcd_ex1_op_rnd_v_b(f_dcd_ex1_op_rnd_v_b), + .f_dcd_ex1_op_rnd_b(f_dcd_ex1_op_rnd_b), + .f_dcd_ex1_inv_sign_b(f_dcd_ex1_inv_sign_b), + .f_dcd_ex1_sign_ctl_b(f_dcd_ex1_sign_ctl_b), + .f_dcd_ex1_sgncpy_b(f_dcd_ex1_sgncpy_b), + .f_dcd_ex1_fpscr_bit_data_b(f_dcd_ex1_fpscr_bit_data_b), + .f_dcd_ex1_fpscr_bit_mask_b(f_dcd_ex1_fpscr_bit_mask_b), + .f_dcd_ex1_fpscr_nib_mask_b(f_dcd_ex1_fpscr_nib_mask_b), + .f_dcd_ex1_mv_to_scr_b(f_dcd_ex1_mv_to_scr_b), + .f_dcd_ex1_mv_from_scr_b(f_dcd_ex1_mv_from_scr_b), + .f_dcd_ex1_mtfsbx_b(f_dcd_ex1_mtfsbx_b), + .f_dcd_ex1_mcrfs_b(f_dcd_ex1_mcrfs_b), + .f_dcd_ex1_mtfsf_b(f_dcd_ex1_mtfsf_b), + .f_dcd_ex1_mtfsfi_b(f_dcd_ex1_mtfsfi_b), + .f_dcd_ex1_log2e_b(f_dcd_ex1_log2e_b), + .f_dcd_ex1_pow2e_b(f_dcd_ex1_pow2e_b), + .f_dcd_ex1_ftdiv(f_dcd_ex1_ftdiv), + .f_dcd_ex1_ftsqrt(f_dcd_ex1_ftsqrt), + .f_dcd_ex0_div(f_dcd_ex0_div), //i--fdsq -- :in std_ulogic; + .f_dcd_ex0_divs(f_dcd_ex0_divs), //i--fdsq -- :in std_ulogic; + .f_dcd_ex0_sqrt(f_dcd_ex0_sqrt), //i--fdsq -- :in std_ulogic; + .f_dcd_ex0_sqrts(f_dcd_ex0_sqrts), //i--fdsq -- :in std_ulogic; + .f_dcd_ex0_record_v(f_dcd_ex0_record_v), //i--fdsq -- :in std_ulogic; + .f_dcd_ex2_divsqrt_v(f_dcd_ex2_divsqrt_v), + .f_dcd_ex2_divsqrt_hole_v(f_dcd_ex2_divsqrt_hole_v), //i--fdsq + .f_dcd_flush(f_dcd_flush), //i--fdsq -- :in std_ulogic; + .f_dcd_ex1_itag(f_dcd_ex1_itag), //i--fdsq -- :in std_ulogic_vector(0 to 6); + .f_dcd_ex1_fpscr_addr(f_dcd_ex1_fpscr_addr), //i--fdsq -- :in std_ulogic_vector(0 to 6); + .f_dsq_ex5_divsqrt_v(f_dsq_ex5_divsqrt_v), + .f_dsq_ex6_divsqrt_v_suppress(f_dsq_ex6_divsqrt_v_suppress), + .f_dsq_debug(f_dsq_debug), + .f_dsq_ex6_divsqrt_v(f_dsq_ex6_divsqrt_v), + .f_dsq_ex6_divsqrt_record_v(f_dsq_ex6_divsqrt_record_v), + .f_dsq_ex5_divsqrt_itag(f_dsq_ex5_divsqrt_itag), + .f_dsq_ex6_divsqrt_fpscr_addr(f_dsq_ex6_divsqrt_fpscr_addr), + .f_dcd_ex1_divsqrt_cr_bf(f_dcd_ex1_divsqrt_cr_bf), //i--fdsq + .f_dcd_axucr0_deno(f_dcd_axucr0_deno), + .f_dsq_ex6_divsqrt_cr_bf(f_dsq_ex6_divsqrt_cr_bf), + .f_add_ex5_fpcc_iu(f_add_ex5_fpcc_iu), + .f_pic_ex6_fpr_wr_dis_b(f_pic_ex6_fpr_wr_dis_b), + .f_scr_ex8_cr_fld(f_scr_ex8_cr_fld), + .f_scr_ex6_fpscr_ni_thr0(f_scr_ex6_fpscr_ni_thr0_int), + .f_scr_ex6_fpscr_ni_thr1(f_scr_ex6_fpscr_ni_thr1_int), + .f_rnd_ex7_res_expo(f_rnd_ex7_res_expo), + .f_rnd_ex7_res_frac(f_rnd_ex7_res_frac), + .f_rnd_ex7_res_sign(f_rnd_ex7_res_sign), + .f_ex3_b_den_flush(f_ex3_b_den_flush), + .f_scr_ex8_fx_thread0(f_scr_ex8_fx_thread0), + .f_scr_ex8_fx_thread1(f_scr_ex8_fx_thread1), + .f_scr_cpl_fx_thread0(f_scr_cpl_fx_thread0), + .f_scr_cpl_fx_thread1(f_scr_cpl_fx_thread1), + //---------------------------------------------- + .f_dcd_ex1_uc_ft_pos(f_dcd_ex1_uc_ft_pos), //i--mad + .f_dcd_ex1_uc_ft_neg(f_dcd_ex1_uc_ft_neg), //i--mad + .f_dcd_ex1_uc_fa_pos(f_dcd_ex1_uc_fa_pos), //i--mad + .f_dcd_ex1_uc_fc_pos(f_dcd_ex1_uc_fc_pos), //i--mad + .f_dcd_ex1_uc_fb_pos(f_dcd_ex1_uc_fb_pos), //i--mad + .f_dcd_ex1_uc_fc_hulp(f_dcd_ex1_uc_fc_hulp), //i--mad + .f_dcd_ex1_uc_fc_0_5(f_dcd_ex1_uc_fc_0_5), //i--mad + .f_dcd_ex1_uc_fc_1_0(f_dcd_ex1_uc_fc_1_0), //i--mad + .f_dcd_ex1_uc_fc_1_minus(f_dcd_ex1_uc_fc_1_minus), //i--mad + .f_dcd_ex1_uc_fb_1_0(f_dcd_ex1_uc_fb_1_0), //i--mad + .f_dcd_ex1_uc_fb_0_75(f_dcd_ex1_uc_fb_0_75), //i--mad + .f_dcd_ex1_uc_fb_0_5(f_dcd_ex1_uc_fb_0_5), //i--mad + .f_dcd_ex3_uc_inc_lsb(f_dcd_ex3_uc_inc_lsb), //i--mad + .f_dcd_ex3_uc_gs_v(f_dcd_ex3_uc_gs_v), //i--mad + .f_dcd_ex3_uc_gs(f_dcd_ex3_uc_gs), //i--mad + + .f_dcd_ex1_uc_mid(f_dcd_ex1_uc_mid), //i--mad + .f_dcd_ex1_uc_end(f_dcd_ex1_uc_end), //i--mad + .f_dcd_ex1_uc_special(f_dcd_ex1_uc_special), //i--mad + .f_dcd_ex3_uc_vxsnan(f_dcd_ex3_uc_vxsnan), + .f_dcd_ex3_uc_zx(f_dcd_ex3_uc_zx), //i--mad + .f_dcd_ex3_uc_vxidi(f_dcd_ex3_uc_vxidi), //i--mad + .f_dcd_ex3_uc_vxzdz(f_dcd_ex3_uc_vxzdz), //i--mad + .f_dcd_ex3_uc_vxsqrt(f_dcd_ex3_uc_vxsqrt), //i--mad + //---------------------------------------------------------------- + .f_mad_ex7_uc_sign(f_mad_ex7_uc_sign), //o--mad + .f_mad_ex7_uc_zero(f_mad_ex7_uc_zero), //o--mad + .f_mad_ex4_uc_special(f_mad_ex4_uc_special), //o--mad + .f_mad_ex4_uc_vxsnan(f_mad_ex4_uc_vxsnan), + .f_mad_ex4_uc_zx(f_mad_ex4_uc_zx), //o--mad + .f_mad_ex4_uc_vxsqrt(f_mad_ex4_uc_vxsqrt), //o--mad + .f_mad_ex4_uc_vxidi(f_mad_ex4_uc_vxidi), //o--mad + .f_mad_ex4_uc_vxzdz(f_mad_ex4_uc_vxzdz), //o--mad + .f_mad_ex4_uc_res_sign(f_mad_ex4_uc_res_sign), //o--mad + .f_mad_ex4_uc_round_mode(f_mad_ex4_uc_round_mode[0:1]), //o--mad + //----------------------------------------- + .f_fpr_ex2_a_par(f_fpr_ex2_a_par), + .f_fpr_ex2_b_par(f_fpr_ex2_b_par), + .f_fpr_ex2_c_par(f_fpr_ex2_c_par), + .f_mad_ex3_a_parity_check(f_mad_ex3_a_parity_check), + .f_mad_ex3_c_parity_check(f_mad_ex3_c_parity_check), + .f_mad_ex3_b_parity_check(f_mad_ex3_b_parity_check), + //---------------------------------------------- + .ex1_thread_b(f_dcd_ex1_thread_b), + .f_dcd_ex7_fpscr_wr(f_dcd_ex7_fpscr_wr), + .f_dcd_ex7_fpscr_addr(f_dcd_ex7_fpscr_addr), + .f_pic_ex6_scr_upd_move_b(f_pic_ex6_scr_upd_move_b), + + .cp_axu_i0_t1_v(cp_axu_i0_t1_v), + .cp_axu_i0_t0_t1_t(cp_axu_i0_t0_t1_t), + .cp_axu_i0_t1_t1_t(cp_axu_i0_t1_t1_t), + .cp_axu_i0_t0_t1_p(cp_axu_i0_t0_t1_p), + .cp_axu_i0_t1_t1_p(cp_axu_i0_t1_t1_p), + .cp_axu_i1_t1_v(cp_axu_i1_t1_v), + .cp_axu_i1_t0_t1_t(cp_axu_i1_t0_t1_t), + .cp_axu_i1_t1_t1_t(cp_axu_i1_t1_t1_t), + .cp_axu_i1_t0_t1_p(cp_axu_i1_t0_t1_p), + .cp_axu_i1_t1_t1_p(cp_axu_i1_t1_t1_p), + //-------------------------------------------- + .vdd(vdd), + .gnd(gnd), + .scan_in(f_mad_si[0:18]), + .scan_out(f_mad_so[0:18]), + .clkoff_b(clkoff_dc_b), + .act_dis(act_dis), + .flush(pc_fu_ccflush_dc), + .delay_lclkr(delay_lclkr_dc[1:7]), + .mpw1_b(mpw1_dc_b[1:7]), + .mpw2_b(mpw2_dc_b[0:1]), + .sg_1(sg_1[0]), + .thold_1(func_sl_thold_1[0]), + .fpu_enable(fpu_enable), + .f_dcd_ex1_act(f_dcd_ex1_mad_act), + .nclk(nclk) + ); + + //Needed for RTX + assign iu_fu_ex0_itag = rv_axu0_ex0_itag; + assign iu_fu_rf0_instr_v = rv_axu0_vld; + assign iu_fu_rf0_tid = rv_axu0_vld; // one hot + + assign axu0_rv_hold_all = f_dcd_rv_hold_all_int; + + assign axu1_rv_hold_all = tidn; + + //---------------------------------------------------------------------- + // Control and Decode + + fu_dcd #(.ITAG_SIZE_ENC(`ITAG_SIZE_ENC), .EFF_IFAR(`EFF_IFAR), .REGMODE(`REGMODE), .THREAD_POOL_ENC(`THREAD_POOL_ENC), .CR_POOL_ENC(`CR_POOL_ENC), .THREADS(`THREADS)) dcd( + // INPUTS + .act_dis(act_dis), + .bcfg_scan_in(bcfg_scan_in), + .ccfg_scan_in(ccfg_scan_in), + .cfg_sl_thold_1(cfg_sl_thold_1), + .func_slp_sl_thold_1(func_slp_sl_thold_1), + .clkoff_b(clkoff_dc_b), + .cp_flush(cp_flush), + .dcfg_scan_in(dcfg_scan_in), + // Trace/Debug Bus + .debug_bus_in(debug_bus_in), + .debug_bus_out(debug_bus_out), + .coretrace_ctrls_in(coretrace_ctrls_in), + .coretrace_ctrls_out(coretrace_ctrls_out), + .event_bus_in(event_bus_in), + .event_bus_out(event_bus_out), + + .f_dcd_perr_sm_running(f_dcd_perr_sm_running), + .f_dcd_ex2_perr_force_c(f_dcd_ex2_perr_force_c), + .f_dcd_ex2_perr_fsel_ovrd(f_dcd_ex2_perr_fsel_ovrd), + + + .delay_lclkr(delay_lclkr_dc[0:9]), + .f_add_ex5_fpcc_iu(f_add_ex5_fpcc_iu), + .f_dcd_si(f_dcd_si), + .f_dsq_ex5_divsqrt_itag(f_dsq_ex5_divsqrt_itag), + .f_dsq_ex5_divsqrt_v(f_dsq_ex5_divsqrt_v), + .f_dsq_ex6_divsqrt_cr_bf(f_dsq_ex6_divsqrt_cr_bf), + .f_dsq_ex6_divsqrt_fpscr_addr(f_dsq_ex6_divsqrt_fpscr_addr), + .f_dsq_ex6_divsqrt_instr_frt(f_dsq_ex6_divsqrt_instr_frt), + .f_dsq_ex6_divsqrt_instr_tid(f_dsq_ex6_divsqrt_instr_tid), + .f_dsq_ex6_divsqrt_record_v(f_dsq_ex6_divsqrt_record_v), + .f_dsq_ex6_divsqrt_v(f_dsq_ex6_divsqrt_v), + .f_dsq_ex6_divsqrt_v_suppress(f_dsq_ex6_divsqrt_v_suppress), + .f_dsq_ex3_hangcounter_trigger(f_dsq_ex3_hangcounter_trigger_int), + .f_dcd_rv_hold_all(f_dcd_rv_hold_all_int), + .f_dsq_debug(f_dsq_debug), + .f_ex3_b_den_flush(f_ex3_b_den_flush), + .f_fpr_ex6_load_addr(f_fpr_ex6_load_addr), + .f_fpr_ex6_load_v(f_fpr_ex6_load_v), + .f_fpr_ex6_reload_addr(f_fpr_ex6_reload_addr), + .f_fpr_ex6_reload_v(f_fpr_ex6_reload_v), + .f_mad_ex3_a_parity_check(f_mad_ex3_a_parity_check), + .f_mad_ex3_b_parity_check(f_mad_ex3_b_parity_check), + .f_mad_ex3_c_parity_check(f_mad_ex3_c_parity_check), + .f_mad_ex4_uc_res_sign(f_mad_ex4_uc_res_sign), + .f_mad_ex4_uc_round_mode(f_mad_ex4_uc_round_mode), + .f_mad_ex4_uc_special(f_mad_ex4_uc_special), + .f_mad_ex4_uc_vxidi(f_mad_ex4_uc_vxidi), + .f_mad_ex4_uc_vxsnan(f_mad_ex4_uc_vxsnan), + .f_mad_ex4_uc_vxsqrt(f_mad_ex4_uc_vxsqrt), + .f_mad_ex4_uc_vxzdz(f_mad_ex4_uc_vxzdz), + .f_mad_ex4_uc_zx(f_mad_ex4_uc_zx), + .f_mad_ex7_uc_sign(f_mad_ex7_uc_sign), + .f_mad_ex7_uc_zero(f_mad_ex7_uc_zero), + .f_pic_ex6_fpr_wr_dis_b(f_pic_ex6_fpr_wr_dis_b), + .f_pic_ex6_scr_upd_move_b(f_pic_ex6_scr_upd_move_b), + .f_rnd_ex7_res_expo(f_rnd_ex7_res_expo), + .f_rnd_ex7_res_frac(f_rnd_ex7_res_frac), + .f_rnd_ex7_res_sign(f_rnd_ex7_res_sign), + .f_scr_cpl_fx_thread0(f_scr_cpl_fx_thread0), + .f_scr_cpl_fx_thread1(f_scr_cpl_fx_thread1), + .f_scr_ex8_cr_fld(f_scr_ex8_cr_fld), + .f_scr_ex8_fx_thread0(f_scr_ex8_fx_thread0), + .f_scr_ex8_fx_thread1(f_scr_ex8_fx_thread1), + .f_scr_ex6_fpscr_ni_thr0(f_scr_ex6_fpscr_ni_thr0_int), + .f_scr_ex6_fpscr_ni_thr1(f_scr_ex6_fpscr_ni_thr1_int), + .f_sto_ex3_s_parity_check(f_sto_ex3_s_parity_check), + .flush(pc_fu_ccflush_dc), + .rv_axu0_ex0_t3_p(rv_axu0_ex0_t3_p), + .iu_fu_rf0_tid(iu_fu_rf0_tid), + .iu_fu_rf0_fra(rv_axu0_s1_p), + .iu_fu_rf0_fra_v(rv_axu0_s1_v), + .iu_fu_rf0_frb(rv_axu0_s2_p), + .iu_fu_rf0_frb_v(rv_axu0_s2_v), + .iu_fu_rf0_frc(rv_axu0_s3_p), + .iu_fu_rf0_frc_v(rv_axu0_s3_v), + .rv_axu0_ex0_t2_p(rv_axu0_ex0_t2_p), + .iu_fu_rf0_instr_match(iu_fu_rf0_instr_match), + .mpw1_b(mpw1_dc_b[0:9]), + .mpw2_b(mpw2_dc_b[0:1]), + .nclk(nclk), + .pc_fu_debug_mux_ctrls(pc_fu_debug_mux_ctrls), + .pc_fu_event_count_mode(pc_fu_event_count_mode), + .pc_fu_ram_active(pc_fu_ram_active), + .pc_fu_trace_bus_enable(pc_fu_trace_bus_enable), + .pc_fu_event_bus_enable(pc_fu_event_bus_enable), + .pc_fu_instr_trace_mode(pc_fu_instr_trace_mode), + .pc_fu_instr_trace_tid(pc_fu_instr_trace_tid), + .fu_lq_ex3_sto_parity_err(fu_lq_ex3_sto_parity_err), + .rv_axu0_ex0_instr(rv_axu0_ex0_instr), + .rv_axu0_ex0_itag(rv_axu0_ex0_itag), + .rv_axu0_ex0_t1_p(rv_axu0_ex0_t1_p), + .rv_axu0_ex0_t1_v(rv_axu0_ex0_t1_v), + .rv_axu0_ex0_ucode(rv_axu0_ex0_ucode), + .rv_axu0_vld(rv_axu0_vld), + .sg_1(sg_1[1]), + .slowspr_addr_in(slowspr_addr_in), + .slowspr_data_in(slowspr_data_in), + .slowspr_done_in(slowspr_done_in), + .slowspr_etid_in(slowspr_etid_in), + .slowspr_rw_in(slowspr_rw_in), + .slowspr_val_in(slowspr_val_in), + .thold_1(func_sl_thold_1[1]), + + .lq_fu_ex5_abort(lq_fu_ex5_abort), + .fu_lq_ex3_abort(fu_lq_ex3_abort), + .axu0_rv_ex2_s1_abort(axu0_rv_ex2_s1_abort), + .axu0_rv_ex2_s2_abort(axu0_rv_ex2_s2_abort), + .axu0_rv_ex2_s3_abort(axu0_rv_ex2_s3_abort), + + .xu_fu_ex4_eff_addr(lq_fu_ex4_eff_addr), + .xu_fu_msr_fe0(xu_fu_msr_fe0), + .xu_fu_msr_fe1(xu_fu_msr_fe1), + .xu_fu_msr_fp(xu_fu_msr_fp), + .xu_fu_msr_gs(xu_fu_msr_gs), + .xu_fu_msr_pr(xu_fu_msr_pr), + + + // INOUTS + .vdd(vdd), + .gnd(gnd), + // OUTPUTS + .axu0_cr_w4a(axu0_cr_w4a), + .axu0_cr_w4d(axu0_cr_w4d), + .axu0_cr_w4e(axu0_cr_w4e), + .axu0_iu_async_fex(axu0_iu_async_fex), + .axu0_iu_exception(axu0_iu_exception), + .axu0_iu_exception_val(axu0_iu_exception_val), + .axu0_iu_execute_vld(axu0_iu_execute_vld), + .axu0_iu_flush2ucode(axu0_iu_flush2ucode), + .axu0_iu_flush2ucode_type(axu0_iu_flush2ucode_type), + .axu0_iu_itag(axu0_iu_itag), + .axu0_iu_n_flush(axu0_iu_n_flush), + .axu0_iu_n_np1_flush(axu0_iu_n_np1_flush), + .axu0_iu_np1_flush(axu0_iu_np1_flush), + .axu0_iu_perf_events(axu0_iu_perf_events_int), + .axu0_rv_itag(axu0_rv_itag), + .axu0_rv_itag_vld(axu0_rv_itag_vld), + .axu0_rv_itag_abort(axu0_rv_itag_abort), + .axu0_rv_ord_complete(axu0_rv_ord_complete), + .axu1_iu_exception(axu1_iu_exception), + .axu1_iu_exception_val(axu1_iu_exception_val), + .axu1_iu_execute_vld(axu1_iu_execute_vld), + .axu1_iu_flush2ucode(axu1_iu_flush2ucode), + .axu1_iu_flush2ucode_type(axu1_iu_flush2ucode_type), + .axu1_iu_itag(axu1_iu_itag), + .axu1_iu_n_flush(axu1_iu_n_flush), + .axu1_iu_np1_flush(axu1_iu_np1_flush), + .axu1_rv_itag(axu1_rv_itag), + .axu1_rv_itag_vld(axu1_rv_itag_vld), + .axu1_rv_itag_abort(axu1_rv_itag_abort), + .axu1_iu_perf_events(axu1_iu_perf_events_int), + .bcfg_scan_out(bcfg_scan_out), + .ccfg_scan_out(ccfg_scan_out), + .dcfg_scan_out(dcfg_scan_out), + .f_dcd_ex1_sto_act(f_dcd_ex1_sto_act), + .f_dcd_ex1_mad_act(f_dcd_ex1_mad_act), + .f_dcd_msr_fp_act(f_dcd_msr_fp_act), + .f_dcd_ex1_aop_valid(f_dcd_ex1_aop_valid), + .f_dcd_ex1_bop_valid(f_dcd_ex1_bop_valid), + .f_dcd_ex1_thread(f_dcd_ex1_thread), + .f_dcd_ex1_bypsel_a_load0(f_dcd_ex1_bypsel_a_load0), + .f_dcd_ex1_bypsel_a_load1(f_dcd_ex1_bypsel_a_load1), + .f_dcd_ex1_bypsel_a_load2(f_dcd_ex1_bypsel_a_load2), + .f_dcd_ex1_bypsel_a_reload0(f_dcd_ex1_bypsel_a_reload0), + .f_dcd_ex1_bypsel_a_reload1(f_dcd_ex1_bypsel_a_reload1), + .f_dcd_ex1_bypsel_a_reload2(f_dcd_ex1_bypsel_a_reload2), + + .f_dcd_ex1_bypsel_a_res0(f_dcd_ex1_bypsel_a_res0), + .f_dcd_ex1_bypsel_a_res1(f_dcd_ex1_bypsel_a_res1), + .f_dcd_ex1_bypsel_a_res2(f_dcd_ex1_bypsel_a_res2), + .f_dcd_ex1_bypsel_b_load0(f_dcd_ex1_bypsel_b_load0), + .f_dcd_ex1_bypsel_b_load1(f_dcd_ex1_bypsel_b_load1), + .f_dcd_ex1_bypsel_b_load2(f_dcd_ex1_bypsel_b_load2), + .f_dcd_ex1_bypsel_b_reload0(f_dcd_ex1_bypsel_b_reload0), + .f_dcd_ex1_bypsel_b_reload1(f_dcd_ex1_bypsel_b_reload1), + .f_dcd_ex1_bypsel_b_reload2(f_dcd_ex1_bypsel_b_reload2), + + .f_dcd_ex1_bypsel_b_res0(f_dcd_ex1_bypsel_b_res0), + .f_dcd_ex1_bypsel_b_res1(f_dcd_ex1_bypsel_b_res1), + .f_dcd_ex1_bypsel_b_res2(f_dcd_ex1_bypsel_b_res2), + .f_dcd_ex1_bypsel_c_load0(f_dcd_ex1_bypsel_c_load0), + .f_dcd_ex1_bypsel_c_load1(f_dcd_ex1_bypsel_c_load1), + .f_dcd_ex1_bypsel_c_load2(f_dcd_ex1_bypsel_c_load2), + .f_dcd_ex1_bypsel_c_reload0(f_dcd_ex1_bypsel_c_reload0), + .f_dcd_ex1_bypsel_c_reload1(f_dcd_ex1_bypsel_c_reload1), + .f_dcd_ex1_bypsel_c_reload2(f_dcd_ex1_bypsel_c_reload2), + + .f_dcd_ex1_bypsel_c_res0(f_dcd_ex1_bypsel_c_res0), + .f_dcd_ex1_bypsel_c_res1(f_dcd_ex1_bypsel_c_res1), + .f_dcd_ex1_bypsel_c_res2(f_dcd_ex1_bypsel_c_res2), + .f_dcd_ex1_bypsel_s_load0(f_dcd_ex1_bypsel_s_load0), + .f_dcd_ex1_bypsel_s_load1(f_dcd_ex1_bypsel_s_load1), + .f_dcd_ex1_bypsel_s_load2(f_dcd_ex1_bypsel_s_load2), + .f_dcd_ex1_bypsel_s_reload0(f_dcd_ex1_bypsel_s_reload0), + .f_dcd_ex1_bypsel_s_reload1(f_dcd_ex1_bypsel_s_reload1), + .f_dcd_ex1_bypsel_s_reload2(f_dcd_ex1_bypsel_s_reload2), + + .f_dcd_ex1_bypsel_s_res0(f_dcd_ex1_bypsel_s_res0), + .f_dcd_ex1_bypsel_s_res1(f_dcd_ex1_bypsel_s_res1), + .f_dcd_ex1_bypsel_s_res2(f_dcd_ex1_bypsel_s_res2), + .f_dcd_ex1_compare_b(f_dcd_ex1_compare_b), + .f_dcd_ex1_cop_valid(f_dcd_ex1_cop_valid), + .f_dcd_ex1_divsqrt_cr_bf(f_dcd_ex1_divsqrt_cr_bf), + .f_dcd_axucr0_deno(f_dcd_axucr0_deno), + .f_dcd_ex1_emin_dp(f_dcd_ex1_emin_dp), + .f_dcd_ex1_emin_sp(f_dcd_ex1_emin_sp), + .f_dcd_ex1_est_recip_b(f_dcd_ex1_est_recip_b), + .f_dcd_ex1_est_rsqrt_b(f_dcd_ex1_est_rsqrt_b), + .f_dcd_ex1_force_excp_dis(f_dcd_ex1_force_excp_dis), + .f_dcd_ex1_force_pass_b(f_dcd_ex1_force_pass_b), + .f_dcd_ex1_fpscr_addr(f_dcd_ex1_fpscr_addr), + .f_dcd_ex1_fpscr_bit_data_b(f_dcd_ex1_fpscr_bit_data_b), + .f_dcd_ex1_fpscr_bit_mask_b(f_dcd_ex1_fpscr_bit_mask_b), + .f_dcd_ex1_fpscr_nib_mask_b(f_dcd_ex1_fpscr_nib_mask_b), + .f_dcd_ex1_from_integer_b(f_dcd_ex1_from_integer_b), + .f_dcd_ex1_frsp_b(f_dcd_ex1_frsp_b), + .f_dcd_ex1_fsel_b(f_dcd_ex1_fsel_b), + .f_dcd_ex1_ftdiv(f_dcd_ex1_ftdiv), + .f_dcd_ex1_ftsqrt(f_dcd_ex1_ftsqrt), + .f_dcd_ex1_instr_frt(f_dcd_ex1_instr_frt), + .f_dcd_ex1_instr_tid(f_dcd_ex1_instr_tid), + .f_dcd_ex1_inv_sign_b(f_dcd_ex1_inv_sign_b), + .f_dcd_ex1_itag(f_dcd_ex1_itag), + .f_dcd_ex1_log2e_b(f_dcd_ex1_log2e_b), + .f_dcd_ex1_math_b(f_dcd_ex1_math_b), + .f_dcd_ex1_mcrfs_b(f_dcd_ex1_mcrfs_b), + .f_dcd_ex1_move_b(f_dcd_ex1_move_b), + .f_dcd_ex1_mtfsbx_b(f_dcd_ex1_mtfsbx_b), + .f_dcd_ex1_mtfsf_b(f_dcd_ex1_mtfsf_b), + .f_dcd_ex1_mtfsfi_b(f_dcd_ex1_mtfsfi_b), + .f_dcd_ex1_mv_from_scr_b(f_dcd_ex1_mv_from_scr_b), + .f_dcd_ex1_mv_to_scr_b(f_dcd_ex1_mv_to_scr_b), + .f_dcd_ex1_nj_deni(f_dcd_ex1_nj_deni), + .f_dcd_ex1_nj_deno(f_dcd_ex1_nj_deno), + .f_dcd_ex1_op_rnd_b(f_dcd_ex1_op_rnd_b), + .f_dcd_ex1_op_rnd_v_b(f_dcd_ex1_op_rnd_v_b), + .f_dcd_ex1_ordered_b(f_dcd_ex1_ordered_b), + .f_dcd_ex1_pow2e_b(f_dcd_ex1_pow2e_b), + .f_dcd_ex1_prenorm_b(f_dcd_ex1_prenorm_b), + .f_dcd_ex1_rnd_to_int_b(f_dcd_ex1_rnd_to_int_b), + .f_dcd_ex1_sgncpy_b(f_dcd_ex1_sgncpy_b), + .f_dcd_ex1_sign_ctl_b(f_dcd_ex1_sign_ctl_b), + .f_dcd_ex1_sp(f_dcd_ex1_sp), + .f_dcd_ex1_sp_conv_b(f_dcd_ex1_sp_conv_b), + .f_dcd_ex1_sto_dp(f_dcd_ex1_sto_dp), + .f_dcd_ex1_sto_sp(f_dcd_ex1_sto_sp), + .f_dcd_ex1_sto_wd(f_dcd_ex1_sto_wd), + .f_dcd_ex1_sub_op_b(f_dcd_ex1_sub_op_b), + .f_dcd_ex1_thread_b(f_dcd_ex1_thread_b), + .f_dcd_ex1_to_integer_b(f_dcd_ex1_to_integer_b), + .f_dcd_ex1_uc_end(f_dcd_ex1_uc_end), + .f_dcd_ex1_uc_fa_pos(f_dcd_ex1_uc_fa_pos), + .f_dcd_ex1_uc_fb_0_5(f_dcd_ex1_uc_fb_0_5), + .f_dcd_ex1_uc_fb_0_75(f_dcd_ex1_uc_fb_0_75), + .f_dcd_ex1_uc_fb_1_0(f_dcd_ex1_uc_fb_1_0), + .f_dcd_ex1_uc_fb_pos(f_dcd_ex1_uc_fb_pos), + .f_dcd_ex1_uc_fc_0_5(f_dcd_ex1_uc_fc_0_5), + .f_dcd_ex1_uc_fc_1_0(f_dcd_ex1_uc_fc_1_0), + .f_dcd_ex1_uc_fc_1_minus(f_dcd_ex1_uc_fc_1_minus), + .f_dcd_ex1_uc_fc_hulp(f_dcd_ex1_uc_fc_hulp), + .f_dcd_ex1_uc_fc_pos(f_dcd_ex1_uc_fc_pos), + .f_dcd_ex1_uc_ft_neg(f_dcd_ex1_uc_ft_neg), + .f_dcd_ex1_uc_ft_pos(f_dcd_ex1_uc_ft_pos), + .f_dcd_ex1_uc_mid(f_dcd_ex1_uc_mid), + .f_dcd_ex1_uc_special(f_dcd_ex1_uc_special), + .f_dcd_ex1_uns_b(f_dcd_ex1_uns_b), + .f_dcd_ex1_word_b(f_dcd_ex1_word_b), + .f_dcd_ex2_divsqrt_v(f_dcd_ex2_divsqrt_v), + .f_dcd_ex2_divsqrt_hole_v(f_dcd_ex2_divsqrt_hole_v), + .f_dcd_ex3_uc_gs(f_dcd_ex3_uc_gs), + .f_dcd_ex3_uc_gs_v(f_dcd_ex3_uc_gs_v), + .f_dcd_ex3_uc_inc_lsb(f_dcd_ex3_uc_inc_lsb), + .f_dcd_ex3_uc_vxidi(f_dcd_ex3_uc_vxidi), + .f_dcd_ex3_uc_vxsnan(f_dcd_ex3_uc_vxsnan), + .f_dcd_ex3_uc_vxsqrt(f_dcd_ex3_uc_vxsqrt), + .f_dcd_ex3_uc_vxzdz(f_dcd_ex3_uc_vxzdz), + .f_dcd_ex3_uc_zx(f_dcd_ex3_uc_zx), + .f_dcd_ex6_frt_tid(f_dcd_ex6_frt_tid), + .f_dcd_ex7_cancel(f_dcd_ex7_cancel), + .f_dcd_ex7_fpscr_addr(f_dcd_ex7_fpscr_addr), + .f_dcd_ex7_fpscr_wr(f_dcd_ex7_fpscr_wr), + .f_dcd_ex7_frt_addr(f_dcd_ex7_frt_addr), + .f_dcd_ex7_frt_tid(f_dcd_ex7_frt_tid), + .f_dcd_ex7_frt_wen(f_dcd_ex7_frt_wen), + .f_dcd_flush(f_dcd_flush), + .f_dcd_rf0_fra(f_dcd_rf0_fra), + .f_dcd_rf0_frb(f_dcd_rf0_frb), + .f_dcd_rf0_frc(f_dcd_rf0_frc), + .f_dcd_rf0_tid(f_dcd_rf0_tid), + .f_dcd_ex0_div(f_dcd_ex0_div), + .f_dcd_ex0_divs(f_dcd_ex0_divs), + .f_dcd_ex0_record_v(f_dcd_ex0_record_v), + .f_dcd_ex0_sqrt(f_dcd_ex0_sqrt), + .f_dcd_ex0_sqrts(f_dcd_ex0_sqrts), + .f_dcd_ex1_sto_v(f_dcd_ex1_sto_v), + .f_dcd_so(f_dcd_so), + .fu_lq_ex2_store_data_val(fu_lq_ex2_store_data_val), + .fu_lq_ex2_store_itag(fu_lq_ex2_store_itag), + .fu_pc_err_regfile_parity(fu_pc_err_regfile_parity), + .fu_pc_err_regfile_ue(fu_pc_err_regfile_ue), + + .fu_pc_ram_data(fu_pc_ram_data), + .fu_pc_ram_data_val(fu_pc_ram_data_val), + + .slowspr_addr_out(slowspr_addr_out), + .slowspr_data_out(slowspr_data_out), + .slowspr_done_out(slowspr_done_out), + .slowspr_etid_out(slowspr_etid_out), + .slowspr_rw_out(slowspr_rw_out), + .slowspr_val_out(slowspr_val_out), + + .rf0_act_b(rf0_act_b) + ); + + assign axu0_iu_perf_events = axu0_iu_perf_events_int; + assign axu1_iu_perf_events = axu1_iu_perf_events_int; + + //---------------------------------------------------------------------- + // Scan Chains + + assign f_fpr_si = func_scan_in[0]; + assign f_sto_si = f_fpr_so; + assign f_dcd_si = f_sto_so; + assign func_scan_out[0] = tc_ac_scan_dis_dc_b & f_dcd_so; + + assign f_mad_si[0] = func_scan_in[1]; + assign f_mad_si[1] = f_mad_so[0]; + assign f_mad_si[2] = f_mad_so[1]; + assign f_mad_si[3] = f_mad_so[2]; + assign f_mad_si[4] = f_mad_so[3]; + assign f_mad_si[5] = f_mad_so[4]; + assign func_scan_out[1] = tc_ac_scan_dis_dc_b & f_mad_so[5]; + + assign f_mad_si[6] = func_scan_in[2]; + assign f_mad_si[7] = f_mad_so[6]; + assign f_mad_si[8] = f_mad_so[7]; + assign f_mad_si[9] = f_mad_so[8]; + assign f_mad_si[10] = f_mad_so[9]; + assign f_mad_si[11] = f_mad_so[10]; + assign func_scan_out[2] = tc_ac_scan_dis_dc_b & f_mad_so[11]; + + assign f_mad_si[12] = func_scan_in[3]; + assign f_mad_si[13] = f_mad_so[12]; + assign f_mad_si[14] = f_mad_so[13]; + assign f_mad_si[15] = f_mad_so[14]; + assign f_mad_si[16] = f_mad_so[15]; + assign f_mad_si[17] = f_mad_so[16]; + assign f_mad_si[18] = f_mad_so[17]; + + assign f_rv_si = f_mad_so[18]; + assign f_rv_so = f_rv_si; + + assign func_scan_out[3] = tc_ac_scan_dis_dc_b & f_rv_so; + +endmodule diff --git a/dev/verilog/work/fu_add.v b/dev/verilog/work/fu_add.v new file mode 100755 index 0000000..d0bccf3 --- /dev/null +++ b/dev/verilog/work/fu_add.v @@ -0,0 +1,705 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + + `include "tri_a2o.vh" + + +module fu_add( + vdd, + gnd, + clkoff_b, + act_dis, + flush, + delay_lclkr, + mpw1_b, + mpw2_b, + sg_1, + thold_1, + fpu_enable, + nclk, + f_add_si, + f_add_so, + ex2_act_b, + f_sa3_ex4_s, + f_sa3_ex4_c, + f_alg_ex4_frc_sel_p1, + f_alg_ex4_sticky, + f_alg_ex3_effsub_eac_b, + f_alg_ex3_prod_z, + f_pic_ex4_is_gt, + f_pic_ex4_is_lt, + f_pic_ex4_is_eq, + f_pic_ex4_is_nan, + f_pic_ex4_cmp_sgnpos, + f_pic_ex4_cmp_sgnneg, + f_add_ex5_res, + f_add_ex5_flag_nan, + f_add_ex5_flag_gt, + f_add_ex5_flag_lt, + f_add_ex5_flag_eq, + f_add_ex5_fpcc_iu, + f_add_ex5_sign_carry, + f_add_ex5_to_int_ovf_wd, + f_add_ex5_to_int_ovf_dw, + f_add_ex5_sticky +); + // parameter expand_type = 2; // 0 - ibm tech, 1 - other ); + + inout vdd; + inout gnd; + input clkoff_b; // tiup + input act_dis; // ??tidn?? + input flush; // ??tidn?? + input [3:4] delay_lclkr; // tidn, + input [3:4] mpw1_b; // tidn, + input [0:0] mpw2_b; // tidn, + input sg_1; + input thold_1; + input fpu_enable; //dc_act + input [0:`NCLK_WIDTH-1] nclk; + + input f_add_si; //perv + output f_add_so; //perv + input ex2_act_b; //act + + input [0:162] f_sa3_ex4_s; // data + input [53:161] f_sa3_ex4_c; // data + + input f_alg_ex4_frc_sel_p1; // rounding converts + input f_alg_ex4_sticky; // part of eac control + input f_alg_ex3_effsub_eac_b; // already shut off for algByp + input f_alg_ex3_prod_z; + + input f_pic_ex4_is_gt; // compare + input f_pic_ex4_is_lt; // compare + input f_pic_ex4_is_eq; // compare + input f_pic_ex4_is_nan; // compare + input f_pic_ex4_cmp_sgnpos; // compare + input f_pic_ex4_cmp_sgnneg; // compare + + output [0:162] f_add_ex5_res; // RESULT + output f_add_ex5_flag_nan; // compare for fpscr + output f_add_ex5_flag_gt; // compare for fpscr + output f_add_ex5_flag_lt; // compare for fpscr + output f_add_ex5_flag_eq; // compare for fpscr + output [0:3] f_add_ex5_fpcc_iu; // compare for iu + output f_add_ex5_sign_carry; // select sign from product/addend + output [0:1] f_add_ex5_to_int_ovf_wd; // raw data + output [0:1] f_add_ex5_to_int_ovf_dw; // raw data + output f_add_ex5_sticky; // for nrm + + + parameter tiup = 1'b1; + parameter tidn = 1'b0; + + ////################################# + ////# sigdef : non-functional + ////################################# + + wire thold_0_b; + wire thold_0; + wire sg_0; + wire force_t; + + wire ex2_act; + wire ex3_act; + wire ex4_act; + + wire [0:8] act_si; + wire [0:8] act_so; + wire [0:162] ex5_res_so; + wire [0:162] ex5_res_si; + wire [0:9] ex5_cmp_so; + wire [0:9] ex5_cmp_si; + + wire [0:3] spare_unused; + + ////################################# + ////# sigdef : functional + ////################################# + + wire [0:162] ex4_s; + wire [53:161] ex4_c; + + wire ex4_flag_nan; + wire ex4_flag_gt; + wire ex4_flag_lt; + wire ex4_flag_eq; + wire ex4_sign_carry; + + wire ex4_inc_all1; + wire [1:6] ex4_inc_byt_c_glb; + wire [1:6] ex4_inc_byt_c_glb_b; + wire [0:52] ex4_inc_p1; + wire [0:52] ex4_inc_p0; + + wire [53:162] ex4_s_p0; + wire [53:162] ex4_s_p1; + wire [0:162] ex4_res; + + wire ex3_effsub; + wire ex4_effsub; + + wire ex3_effadd_npz; + wire ex3_effsub_npz; + wire ex4_effsub_npz; + wire ex4_effadd_npz; + wire ex4_flip_inc_p0; + wire ex4_flip_inc_p1; + wire ex4_inc_sel_p0; + wire ex4_inc_sel_p1; + + wire [0:162] ex5_res; + wire [0:162] ex5_res_b; + wire [0:162] ex5_res_l2_b; + wire ex5_flag_nan_b; + wire ex5_flag_gt_b; + wire ex5_flag_lt_b; + wire ex5_flag_eq_b; + wire [0:3] ex5_fpcc_iu_b; + wire ex5_sign_carry_b; + wire ex5_sticky_b; + + wire [0:6] ex4_g16; + wire [0:6] ex4_t16; + wire [1:6] ex4_g128; + wire [1:6] ex4_t128; + wire [1:6] ex4_g128_b; + wire [1:6] ex4_t128_b; + wire [0:6] ex4_inc_byt_c_b; + wire [0:6] ex4_eac_sel_p0n; + wire [0:6] ex4_eac_sel_p0; + wire [0:6] ex4_eac_sel_p1; + wire ex4_flag_nan_cp1; + wire ex4_flag_gt_cp1; + wire ex4_flag_lt_cp1; + wire ex4_flag_eq_cp1; + wire add_ex5_d1clk; + wire add_ex5_d2clk; + wire [0:`NCLK_WIDTH-1] add_ex5_lclk; + + wire [53:162] ex4_s_p0n; + wire [53:162] ex4_res_p0n_b; + wire [53:162] ex4_res_p0_b; + wire [53:162] ex4_res_p1_b; + wire [0:52] ex4_inc_p0_x; + wire [0:52] ex4_inc_p1_x; + wire [0:52] ex4_incx_p0_b; + wire [0:52] ex4_incx_p1_b; + wire [53:162] ex4_sel_a1; + wire [53:162] ex4_sel_a2; + wire [53:162] ex4_sel_a3; + + + ////################################################################ + ////# pervasive + ////################################################################ + + + tri_plat thold_reg_0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(flush), + .din(thold_1), + .q(thold_0) + ); + + + tri_plat sg_reg_0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(flush), + .din(sg_1), + .q(sg_0) + ); + + + tri_lcbor lcbor_0( + .clkoff_b(clkoff_b), + .thold(thold_0), + .sg(sg_0), + .act_dis(act_dis), + .force_t(force_t), + .thold_b(thold_0_b) + ); + + ////################################################################ + ////# act + ////################################################################ + + assign ex2_act = (~ex2_act_b); + assign ex3_effsub = (~f_alg_ex3_effsub_eac_b); + assign ex3_effsub_npz = (~f_alg_ex3_effsub_eac_b) & (~f_alg_ex3_prod_z); + assign ex3_effadd_npz = f_alg_ex3_effsub_eac_b & (~f_alg_ex3_prod_z); + + + tri_rlmreg_p #(.WIDTH(9), .NEEDS_SRESET(0)) act_lat( + .force_t(force_t), //i-- tidn, + .d_mode(tiup), + .delay_lclkr(delay_lclkr[3]), //i-- tidn, + .mpw1_b(mpw1_b[3]), //i-- tidn, + .mpw2_b(mpw2_b[0]), //i-- tidn, + .nclk(nclk), + .act(fpu_enable), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scout(act_so), + .scin(act_si), + //----------------- + .din({ spare_unused[0], + spare_unused[1], + ex2_act, + ex3_act, + ex3_effsub, + ex3_effsub_npz, + ex3_effadd_npz, + spare_unused[2], + spare_unused[3]}), + //----------------- + .dout({ spare_unused[0], + spare_unused[1], + ex3_act, + ex4_act, + ex4_effsub, + ex4_effsub_npz, + ex4_effadd_npz, + spare_unused[2], + spare_unused[3]}) + ); + + + tri_lcbnd add_ex5_lcb( + .delay_lclkr(delay_lclkr[4]), // tidn ,--in + .mpw1_b(mpw1_b[4]), // tidn ,--in + .mpw2_b(mpw2_b[0]), // tidn ,--in + .force_t(force_t), // tidn ,--in + .nclk(nclk), //in + .vd(vdd), //inout + .gd(gnd), //inout + .act(ex4_act), //in + .sg(sg_0), //in + .thold_b(thold_0_b), //in + .d1clk(add_ex5_d1clk), //out + .d2clk(add_ex5_d2clk), //out + .lclk(add_ex5_lclk) //out + ); + + ////################################################################ + ////# ex4 logic + ////################################################################ + + assign ex4_s[0:162] = f_sa3_ex4_s[0:162]; + assign ex4_c[53:161] = f_sa3_ex4_c[53:161]; + + //ex4 incrementer----------------------------------------- + + //ex4 incr (global carry)--------------------------------- + + + fu_add_all1 all1( + .ex4_inc_byt_c_b(ex4_inc_byt_c_b[0:6]), //i-- + .ex4_inc_byt_c_glb(ex4_inc_byt_c_glb[1:6]), //o-- + .ex4_inc_byt_c_glb_b(ex4_inc_byt_c_glb_b[1:6]), //o-- + .ex4_inc_all1(ex4_inc_all1) //o-- + ); + + //ex4 incr (byte sections) ------------------------------------------------- + + + fu_loc8inc_lsb inc8_6( + .co_b(ex4_inc_byt_c_b[6]), //o-- + .x(ex4_s[48:52]), //i-- + .s0(ex4_inc_p0[48:52]), //o-- + .s1(ex4_inc_p1[48:52]) //o-- + ); + + + fu_loc8inc inc8_5( + .ci(ex4_inc_byt_c_glb[6]), //i-- + .ci_b(ex4_inc_byt_c_glb_b[6]), //i-- + .co_b(ex4_inc_byt_c_b[5]), //o-- + .x(ex4_s[40:47]), //i-- + .s0(ex4_inc_p0[40:47]), //o-- + .s1(ex4_inc_p1[40:47]) //o-- + ); + + + fu_loc8inc inc8_4( + .ci(ex4_inc_byt_c_glb[5]), //i-- + .ci_b(ex4_inc_byt_c_glb_b[5]), //i-- + .co_b(ex4_inc_byt_c_b[4]), //o-- + .x(ex4_s[32:39]), //i-- + .s0(ex4_inc_p0[32:39]), //o-- + .s1(ex4_inc_p1[32:39]) //o-- + ); + + + fu_loc8inc inc8_3( + .ci(ex4_inc_byt_c_glb[4]), //i-- + .ci_b(ex4_inc_byt_c_glb_b[4]), //i-- + .co_b(ex4_inc_byt_c_b[3]), //o-- + .x(ex4_s[24:31]), //i-- + .s0(ex4_inc_p0[24:31]), //o-- + .s1(ex4_inc_p1[24:31]) //o-- + ); + + + fu_loc8inc inc8_2( + .ci(ex4_inc_byt_c_glb[3]), //i-- + .ci_b(ex4_inc_byt_c_glb_b[3]), //i-- + .co_b(ex4_inc_byt_c_b[2]), //o-- + .x(ex4_s[16:23]), //i-- + .s0(ex4_inc_p0[16:23]), //o-- + .s1(ex4_inc_p1[16:23]) //o-- + ); + + + fu_loc8inc inc8_1( + .ci(ex4_inc_byt_c_glb[2]), //i-- + .ci_b(ex4_inc_byt_c_glb_b[2]), //i-- + .co_b(ex4_inc_byt_c_b[1]), //o-- + .x(ex4_s[8:15]), //i-- + .s0(ex4_inc_p0[8:15]), //o-- + .s1(ex4_inc_p1[8:15]) //o-- + ); + + + fu_loc8inc inc8_0( + .ci(ex4_inc_byt_c_glb[1]), //i-- + .ci_b(ex4_inc_byt_c_glb_b[1]), //i-- + .co_b(ex4_inc_byt_c_b[0]), //o-- + .x(ex4_s[0:7]), //i-- + .s0(ex4_inc_p0[0:7]), //o-- + .s1(ex4_inc_p1[0:7]) //o-- + ); + + //ex4 adder----------------------------------------------- + + // sum[53] is the raw aligner bit + // car[53] includes the bogus bit + // position 53 also includes a "1" to push out the bogus bit + // + // [0:52] needs "111...111" to push out the bogus bit + // but the first co of [53] is suppressed instead + // + // ex4_53 => s53, c53, "1", ci : 2nd co : s53 * c53 * ci + + // sums + // [0] 053:068 + // [1] 069:084 + // [2] 085:100 + // [3] 101:116 + // [4] 117:132 + // [5] 133:148 + // [6] 149:164 <162,"1","1"> + + + fu_hc16pp_msb hc16_0( + .x(ex4_s[53:68]), //i-- + .y(ex4_c[53:68]), //i-- + .ci0(ex4_g128[1]), //i-- + .ci0_b(ex4_g128_b[1]), //i-- + .ci1(ex4_t128[1]), //i-- + .ci1_b(ex4_t128_b[1]), //i-- + .s0(ex4_s_p0[53:68]), //o-- + .s1(ex4_s_p1[53:68]), //o-- + .g16(ex4_g16[0]), //o-- + .t16(ex4_t16[0]) //o-- + ); + + + fu_hc16pp hc16_1( + .x(ex4_s[69:84]), //i-- + .y(ex4_c[69:84]), //i-- + .ci0(ex4_g128[2]), //i-- + .ci0_b(ex4_g128_b[2]), //i-- + .ci1(ex4_t128[2]), //i-- + .ci1_b(ex4_t128_b[2]), //i-- + .s0(ex4_s_p0[69:84]), //o-- + .s1(ex4_s_p1[69:84]), //o-- + .g16(ex4_g16[1]), //o-- + .t16(ex4_t16[1]) //o-- + ); + + + fu_hc16pp hc16_2( + .x(ex4_s[85:100]), //i-- + .y(ex4_c[85:100]), //i-- + .ci0(ex4_g128[3]), //i-- + .ci0_b(ex4_g128_b[3]), //i-- + .ci1(ex4_t128[3]), //i-- + .ci1_b(ex4_t128_b[3]), //i-- + .s0(ex4_s_p0[85:100]), //o-- + .s1(ex4_s_p1[85:100]), //o-- + .g16(ex4_g16[2]), //o-- + .t16(ex4_t16[2]) //o-- + ); + + + fu_hc16pp hc16_3( + .x(ex4_s[101:116]), //i-- + .y(ex4_c[101:116]), //i-- + .ci0(ex4_g128[4]), //i-- + .ci0_b(ex4_g128_b[4]), //i-- + .ci1(ex4_t128[4]), //i-- + .ci1_b(ex4_t128_b[4]), //i-- + .s0(ex4_s_p0[101:116]), //o-- + .s1(ex4_s_p1[101:116]), //o-- + .g16(ex4_g16[3]), //o-- + .t16(ex4_t16[3]) //o-- + ); + + + fu_hc16pp hc16_4( + .x(ex4_s[117:132]), //i-- + .y(ex4_c[117:132]), //i-- + .ci0(ex4_g128[5]), //i-- + .ci0_b(ex4_g128_b[5]), //i-- + .ci1(ex4_t128[5]), //i-- + .ci1_b(ex4_t128_b[5]), //i-- + .s0(ex4_s_p0[117:132]), //o-- + .s1(ex4_s_p1[117:132]), //o-- + .g16(ex4_g16[4]), //o-- + .t16(ex4_t16[4]) //o-- + ); + + + fu_hc16pp hc16_5( + .x(ex4_s[133:148]), //i-- + .y(ex4_c[133:148]), //i-- + .ci0(ex4_g128[6]), //i-- + .ci0_b(ex4_g128_b[6]), //i-- + .ci1(ex4_t128[6]), //i-- + .ci1_b(ex4_t128_b[6]), //i-- + .s0(ex4_s_p0[133:148]), //o-- + .s1(ex4_s_p1[133:148]), //o-- + .g16(ex4_g16[5]), //o-- + .t16(ex4_t16[5]) //o-- + ); + + + fu_hc16pp_lsb hc16_6( + .x(ex4_s[149:162]), //i-- + .y(ex4_c[149:161]), //i-- + .s0(ex4_s_p0[149:162]), //o-- + .s1(ex4_s_p1[149:162]), //o-- + .g16(ex4_g16[6]), //o-- + .t16(ex4_t16[6]) //o-- + ); + + //=######################################################################################### + //=## EACMUX (move the nand3 into technology dependent latch ... latch not yet available) + //=######################################################################################### + + //------------------------------------------------ + // EACMUX: incrementer bits + //------------------------------------------------ + + assign ex4_inc_p0_x[0:52] = ex4_inc_p0[0:52] ^ {53{ex4_flip_inc_p0}}; + assign ex4_inc_p1_x[0:52] = ex4_inc_p1[0:52] ^ {53{ex4_flip_inc_p1}}; + + assign ex4_incx_p0_b[0:52] = (~({53{ex4_inc_sel_p0}} & ex4_inc_p0_x[0:52])); + assign ex4_incx_p1_b[0:52] = (~({53{ex4_inc_sel_p1}} & ex4_inc_p1_x[0:52])); + assign ex4_res[0:52] = (~(ex4_incx_p0_b[0:52] & ex4_incx_p1_b[0:52])); + + //------------------------------------------------ + // EACMUX: adder bits + //------------------------------------------------ + + assign ex4_sel_a1[53:68] = {16{ex4_eac_sel_p0n[0]}}; //rename + assign ex4_sel_a1[69:84] = {16{ex4_eac_sel_p0n[1]}}; //rename + assign ex4_sel_a1[85:100] = {16{ex4_eac_sel_p0n[2]}}; //rename + assign ex4_sel_a1[101:116] = {16{ex4_eac_sel_p0n[3]}}; //rename + assign ex4_sel_a1[117:132] = {16{ex4_eac_sel_p0n[4]}}; //rename + assign ex4_sel_a1[133:148] = {16{ex4_eac_sel_p0n[5]}}; //rename + assign ex4_sel_a1[149:162] = {14{ex4_eac_sel_p0n[6]}}; //rename + + assign ex4_sel_a2[53:68] = {16{ex4_eac_sel_p0[0]}}; //rename + assign ex4_sel_a2[69:84] = {16{ex4_eac_sel_p0[1]}}; //rename + assign ex4_sel_a2[85:100] = {16{ex4_eac_sel_p0[2]}}; //rename + assign ex4_sel_a2[101:116] = {16{ex4_eac_sel_p0[3]}}; //rename + assign ex4_sel_a2[117:132] = {16{ex4_eac_sel_p0[4]}}; //rename + assign ex4_sel_a2[133:148] = {16{ex4_eac_sel_p0[5]}}; //rename + assign ex4_sel_a2[149:162] = {14{ex4_eac_sel_p0[6]}}; //rename + + assign ex4_sel_a3[53:68] = {16{ex4_eac_sel_p1[0]}}; //rename + assign ex4_sel_a3[69:84] = {16{ex4_eac_sel_p1[1]}}; //rename + assign ex4_sel_a3[85:100] = {16{ex4_eac_sel_p1[2]}}; //rename + assign ex4_sel_a3[101:116] = {16{ex4_eac_sel_p1[3]}}; //rename + assign ex4_sel_a3[117:132] = {16{ex4_eac_sel_p1[4]}}; //rename + assign ex4_sel_a3[133:148] = {16{ex4_eac_sel_p1[5]}}; //rename + assign ex4_sel_a3[149:162] = {14{ex4_eac_sel_p1[6]}}; //rename + + assign ex4_s_p0n[53:162] = (~(ex4_s_p0[53:162])); + assign ex4_res_p0n_b[53:162] = (~(ex4_sel_a1[53:162] & ex4_s_p0n[53:162])); + assign ex4_res_p0_b[53:162] = (~(ex4_sel_a2[53:162] & ex4_s_p0[53:162])); + assign ex4_res_p1_b[53:162] = (~(ex4_sel_a3[53:162] & ex4_s_p1[53:162])); + assign ex4_res[53:162] = (~(ex4_res_p0n_b[53:162] & ex4_res_p0_b[53:162] & ex4_res_p1_b[53:162])); + + //=################################################################################## + //=# global carry chain, eac_selects, compare, sign_carry + //=################################################################################## + + + fu_add_glbc glbc( + .ex4_g16(ex4_g16[0:6]), //i-- + .ex4_t16(ex4_t16[0:6]), //i-- + .ex4_inc_all1(ex4_inc_all1), //i-- + .ex4_effsub(ex4_effsub), //i-- + .ex4_effsub_npz(ex4_effsub_npz), //i-- + .ex4_effadd_npz(ex4_effadd_npz), //i-- + .f_alg_ex4_frc_sel_p1(f_alg_ex4_frc_sel_p1), //i-- + .f_alg_ex4_sticky(f_alg_ex4_sticky), //i-- + .f_pic_ex4_is_nan(f_pic_ex4_is_nan), //i-- + .f_pic_ex4_is_gt(f_pic_ex4_is_gt), //i-- + .f_pic_ex4_is_lt(f_pic_ex4_is_lt), //i-- + .f_pic_ex4_is_eq(f_pic_ex4_is_eq), //i-- + .f_pic_ex4_cmp_sgnpos(f_pic_ex4_cmp_sgnpos), //i-- + .f_pic_ex4_cmp_sgnneg(f_pic_ex4_cmp_sgnneg), //i-- + .ex4_g128(ex4_g128[1:6]), //o-- + .ex4_g128_b(ex4_g128_b[1:6]), //o-- + .ex4_t128(ex4_t128[1:6]), //o-- + .ex4_t128_b(ex4_t128_b[1:6]), //o-- + .ex4_flip_inc_p0(ex4_flip_inc_p0), //o-- + .ex4_flip_inc_p1(ex4_flip_inc_p1), //o-- + .ex4_inc_sel_p0(ex4_inc_sel_p0), //o-- + .ex4_inc_sel_p1(ex4_inc_sel_p1), //o-- + .ex4_eac_sel_p0n(ex4_eac_sel_p0n), //o-- + .ex4_eac_sel_p0(ex4_eac_sel_p0), //o-- + .ex4_eac_sel_p1(ex4_eac_sel_p1), //o-- + .ex4_sign_carry(ex4_sign_carry), //o-- + .ex4_flag_nan_cp1(ex4_flag_nan_cp1), //o-- duplicate lat driven by unique gate + .ex4_flag_gt_cp1(ex4_flag_gt_cp1), //o-- duplicate lat driven by unique gate + .ex4_flag_lt_cp1(ex4_flag_lt_cp1), //o-- duplicate lat driven by unique gate + .ex4_flag_eq_cp1(ex4_flag_eq_cp1), //o-- duplicate lat driven by unique gate + .ex4_flag_nan(ex4_flag_nan), //o-- + .ex4_flag_gt(ex4_flag_gt), //o-- + .ex4_flag_lt(ex4_flag_lt), //o-- + .ex4_flag_eq(ex4_flag_eq) //o-- + ); + + ////################################################################ + ////# ex5 latches + ////################################################################ + + + tri_inv_nlats #(.WIDTH(53), .NEEDS_SRESET(0)) ex5_res_hi_lat( + .vd(vdd), + .gd(gnd), + .lclk(add_ex5_lclk), // lclk.clk + .d1clk(add_ex5_d1clk), + .d2clk(add_ex5_d2clk), + .scanin(ex5_res_si[0:52]), + .scanout(ex5_res_so[0:52]), + .d(ex4_res[0:52]), + .qb(ex5_res_l2_b[0:52]) //LAT + ); + + + tri_inv_nlats #(.WIDTH(110), .NEEDS_SRESET(0)) ex5_res_lo_lat( + .vd(vdd), + .gd(gnd), + .lclk(add_ex5_lclk), // lclk.clk + .d1clk(add_ex5_d1clk), + .d2clk(add_ex5_d2clk), + .scanin(ex5_res_si[53:162]), + .scanout(ex5_res_so[53:162]), + .d(ex4_res[53:162]), + .qb(ex5_res_l2_b[53:162]) //LAT + ); + + assign ex5_res[0:162] = (~ex5_res_l2_b[0:162]); + assign ex5_res_b[0:162] = (~ex5_res[0:162]); + assign f_add_ex5_res[0:162] = (~ex5_res_b[0:162]); // output + + + tri_inv_nlats #(.WIDTH(10), .NEEDS_SRESET(0)) ex5_cmp_lat( + .vd(vdd), + .gd(gnd), + .lclk(add_ex5_lclk), // lclk.clk + .d1clk(add_ex5_d1clk), + .d2clk(add_ex5_d2clk), + .scanin(ex5_cmp_si), + .scanout(ex5_cmp_so), + //----------------- + .d({ ex4_flag_lt, + ex4_flag_lt_cp1, + ex4_flag_gt, + ex4_flag_gt_cp1, + ex4_flag_eq, + ex4_flag_eq_cp1, + ex4_flag_nan, + ex4_flag_nan_cp1, + ex4_sign_carry, + f_alg_ex4_sticky}), + //----------------- + .qb({ ex5_flag_lt_b, //LAT + ex5_fpcc_iu_b[0], //LAT + ex5_flag_gt_b, //LAT + ex5_fpcc_iu_b[1], //LAT + ex5_flag_eq_b, //LAT + ex5_fpcc_iu_b[2], //LAT + ex5_flag_nan_b, //LAT + ex5_fpcc_iu_b[3], //LAT + ex5_sign_carry_b, //LAT + ex5_sticky_b}) //LAT + ); + + assign f_add_ex5_flag_nan = (~ex5_flag_nan_b); //output + assign f_add_ex5_flag_gt = (~ex5_flag_gt_b); //output + assign f_add_ex5_flag_lt = (~ex5_flag_lt_b); //output + assign f_add_ex5_flag_eq = (~ex5_flag_eq_b); //output + assign f_add_ex5_fpcc_iu[0:3] = (~ex5_fpcc_iu_b[0:3]); //output + assign f_add_ex5_sign_carry = (~ex5_sign_carry_b); //output + assign f_add_ex5_sticky = (~ex5_sticky_b); //output + + assign f_add_ex5_to_int_ovf_wd[0] = ex5_res[130]; //output + assign f_add_ex5_to_int_ovf_wd[1] = ex5_res[131]; //output + assign f_add_ex5_to_int_ovf_dw[0] = ex5_res[98]; //output + assign f_add_ex5_to_int_ovf_dw[1] = ex5_res[99]; //output + + ////################################################################ + ////# ex5 logic + ////################################################################ + + ////################################################################ + ////# scan string + ////################################################################ + + assign act_si[0:8] = {act_so[1:8], f_add_si}; + assign ex5_res_si[0:162] = {ex5_res_so[1:162], act_so[0]}; + assign ex5_cmp_si[0:9] = {ex5_cmp_so[1:9], ex5_res_so[0]}; + assign f_add_so = ex5_cmp_so[0]; + +endmodule diff --git a/dev/verilog/work/fu_add_all1.v b/dev/verilog/work/fu_add_all1.v new file mode 100755 index 0000000..9c8f99a --- /dev/null +++ b/dev/verilog/work/fu_add_all1.v @@ -0,0 +1,106 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + + `include "tri_a2o.vh" + + +module fu_add_all1( + ex4_inc_byt_c_b, + ex4_inc_byt_c_glb, + ex4_inc_byt_c_glb_b, + ex4_inc_all1 +); + input [0:6] ex4_inc_byt_c_b; // from each byte section + output [1:6] ex4_inc_byt_c_glb; + output [1:6] ex4_inc_byt_c_glb_b; + output ex4_inc_all1; + // ATTRIBUTE BTR_NAME OF fu_add_all1 : ENTITY IS "fu_add_all1"; + + parameter tiup = 1'b1; + parameter tidn = 1'b0; + + wire [0:6] ex4_inc_byt_g1; + wire [0:6] ex4_inc_byt_g2_b; + wire [0:6] ex4_inc_byt_g4; + wire [0:6] ex4_inc_byt_g8_b; + wire [1:6] ex4_inc_byt_g_glb_int; + + + + assign ex4_inc_byt_g1[0:6] = (~ex4_inc_byt_c_b[0:6]); //expect some wire distance between latches + // drive to a common location + + assign ex4_inc_byt_g2_b[6] = (~(ex4_inc_byt_g1[6])); + assign ex4_inc_byt_g2_b[5] = (~(ex4_inc_byt_g1[5] & ex4_inc_byt_g1[6])); + assign ex4_inc_byt_g2_b[4] = (~(ex4_inc_byt_g1[4] & ex4_inc_byt_g1[5])); + assign ex4_inc_byt_g2_b[3] = (~(ex4_inc_byt_g1[3] & ex4_inc_byt_g1[4])); + assign ex4_inc_byt_g2_b[2] = (~(ex4_inc_byt_g1[2] & ex4_inc_byt_g1[3])); + assign ex4_inc_byt_g2_b[1] = (~(ex4_inc_byt_g1[1] & ex4_inc_byt_g1[2])); + assign ex4_inc_byt_g2_b[0] = (~(ex4_inc_byt_g1[0] & ex4_inc_byt_g1[1])); + + assign ex4_inc_byt_g4[6] = (~(ex4_inc_byt_g2_b[6])); + assign ex4_inc_byt_g4[5] = (~(ex4_inc_byt_g2_b[5])); + assign ex4_inc_byt_g4[4] = (~(ex4_inc_byt_g2_b[4] | ex4_inc_byt_g2_b[6])); + assign ex4_inc_byt_g4[3] = (~(ex4_inc_byt_g2_b[3] | ex4_inc_byt_g2_b[5])); + assign ex4_inc_byt_g4[2] = (~(ex4_inc_byt_g2_b[2] | ex4_inc_byt_g2_b[4])); + assign ex4_inc_byt_g4[1] = (~(ex4_inc_byt_g2_b[1] | ex4_inc_byt_g2_b[3])); + assign ex4_inc_byt_g4[0] = (~(ex4_inc_byt_g2_b[0] | ex4_inc_byt_g2_b[2])); + + assign ex4_inc_byt_g8_b[6] = (~(ex4_inc_byt_g4[6])); + assign ex4_inc_byt_g8_b[5] = (~(ex4_inc_byt_g4[5])); + assign ex4_inc_byt_g8_b[4] = (~(ex4_inc_byt_g4[4])); + assign ex4_inc_byt_g8_b[3] = (~(ex4_inc_byt_g4[3])); + assign ex4_inc_byt_g8_b[2] = (~(ex4_inc_byt_g4[2] & ex4_inc_byt_g4[6])); + assign ex4_inc_byt_g8_b[1] = (~(ex4_inc_byt_g4[1] & ex4_inc_byt_g4[5])); + assign ex4_inc_byt_g8_b[0] = (~(ex4_inc_byt_g4[0] & ex4_inc_byt_g4[4])); + + assign ex4_inc_all1 = (~ex4_inc_byt_g8_b[0]); + assign ex4_inc_byt_c_glb[1] = (~ex4_inc_byt_g8_b[1]); // drive back from common + assign ex4_inc_byt_c_glb[2] = (~ex4_inc_byt_g8_b[2]); // drive back from common + assign ex4_inc_byt_c_glb[3] = (~ex4_inc_byt_g8_b[3]); // drive back from common + assign ex4_inc_byt_c_glb[4] = (~ex4_inc_byt_g8_b[4]); // drive back from common + assign ex4_inc_byt_c_glb[5] = (~ex4_inc_byt_g8_b[5]); // drive back from common + assign ex4_inc_byt_c_glb[6] = (~ex4_inc_byt_g8_b[6]); // drive back from common + + assign ex4_inc_byt_g_glb_int[1] = (~ex4_inc_byt_g8_b[1]); + assign ex4_inc_byt_g_glb_int[2] = (~ex4_inc_byt_g8_b[2]); + assign ex4_inc_byt_g_glb_int[3] = (~ex4_inc_byt_g8_b[3]); + assign ex4_inc_byt_g_glb_int[4] = (~ex4_inc_byt_g8_b[4]); + assign ex4_inc_byt_g_glb_int[5] = (~ex4_inc_byt_g8_b[5]); + assign ex4_inc_byt_g_glb_int[6] = (~ex4_inc_byt_g8_b[6]); + + assign ex4_inc_byt_c_glb_b[1] = (~ex4_inc_byt_g_glb_int[1]); // drive back from common + assign ex4_inc_byt_c_glb_b[2] = (~ex4_inc_byt_g_glb_int[2]); // drive back from common + assign ex4_inc_byt_c_glb_b[3] = (~ex4_inc_byt_g_glb_int[3]); // drive back from common + assign ex4_inc_byt_c_glb_b[4] = (~ex4_inc_byt_g_glb_int[4]); // drive back from common + assign ex4_inc_byt_c_glb_b[5] = (~ex4_inc_byt_g_glb_int[5]); // drive back from common + assign ex4_inc_byt_c_glb_b[6] = (~ex4_inc_byt_g_glb_int[6]); // drive back from common + +endmodule diff --git a/dev/verilog/work/fu_add_glbc.v b/dev/verilog/work/fu_add_glbc.v new file mode 100755 index 0000000..9a83e2e --- /dev/null +++ b/dev/verilog/work/fu_add_glbc.v @@ -0,0 +1,781 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + + `include "tri_a2o.vh" + +module fu_add_glbc( + ex4_g16, + ex4_t16, + ex4_inc_all1, + ex4_effsub, + ex4_effsub_npz, + ex4_effadd_npz, + f_alg_ex4_frc_sel_p1, + f_alg_ex4_sticky, + f_pic_ex4_is_nan, + f_pic_ex4_is_gt, + f_pic_ex4_is_lt, + f_pic_ex4_is_eq, + f_pic_ex4_cmp_sgnpos, + f_pic_ex4_cmp_sgnneg, + ex4_g128, + ex4_g128_b, + ex4_t128, + ex4_t128_b, + ex4_flip_inc_p0, + ex4_flip_inc_p1, + ex4_inc_sel_p0, + ex4_inc_sel_p1, + ex4_eac_sel_p0n, + ex4_eac_sel_p0, + ex4_eac_sel_p1, + ex4_sign_carry, + ex4_flag_nan_cp1, + ex4_flag_gt_cp1, + ex4_flag_lt_cp1, + ex4_flag_eq_cp1, + ex4_flag_nan, + ex4_flag_gt, + ex4_flag_lt, + ex4_flag_eq +); + input [0:6] ex4_g16; // from each byte section + input [0:6] ex4_t16; // from each byte section + + input ex4_inc_all1; + input ex4_effsub; + input ex4_effsub_npz; + input ex4_effadd_npz; + input f_alg_ex4_frc_sel_p1; + input f_alg_ex4_sticky; + input f_pic_ex4_is_nan; + input f_pic_ex4_is_gt; + input f_pic_ex4_is_lt; + input f_pic_ex4_is_eq; + input f_pic_ex4_cmp_sgnpos; + input f_pic_ex4_cmp_sgnneg; + //------------------ + output [1:6] ex4_g128; // to each byte section + output [1:6] ex4_g128_b; // to each byte section + output [1:6] ex4_t128; // to each byte section + output [1:6] ex4_t128_b; // to each byte section + //------------------ + output ex4_flip_inc_p0; + output ex4_flip_inc_p1; + output ex4_inc_sel_p0; + output ex4_inc_sel_p1; + output [0:6] ex4_eac_sel_p0n; + output [0:6] ex4_eac_sel_p0; + output [0:6] ex4_eac_sel_p1; + + output ex4_sign_carry; + output ex4_flag_nan_cp1; + output ex4_flag_gt_cp1; + output ex4_flag_lt_cp1; + output ex4_flag_eq_cp1; + output ex4_flag_nan; + output ex4_flag_gt; + output ex4_flag_lt; + output ex4_flag_eq; + + parameter tiup = 1'b1; + parameter tidn = 1'b0; + + wire cp0_g32_01_b; + wire cp0_g32_23_b; + wire cp0_g32_45_b; + wire cp0_g32_66_b; + wire cp0_t32_01_b; + wire cp0_t32_23_b; + wire cp0_t32_45_b; + wire cp0_t32_66_b; + wire cp0_g64_03; + wire cp0_g64_46; + wire cp0_t64_03; + wire cp0_t64_46; + wire cp0_g128_06_b; + wire cp0_t128_06_b; + wire cp0_all1_b; + wire cp0_all1_p; + wire cp0_co_p0; + wire cp0_co_p1; + wire cp0_flip_inc_p1_b; + wire ex4_inc_sel_p0_b; + wire ex4_sign_carry_b; + wire ex4_my_gt_b; + wire ex4_my_lt; + wire ex4_my_eq_b; + wire ex4_my_gt; + wire ex4_my_eq; + wire ex4_gt_pos_b; + wire ex4_gt_neg_b; + wire ex4_lt_pos_b; + wire ex4_lt_neg_b; + wire ex4_eq_eq_b; + wire ex4_is_gt_b; + wire ex4_is_lt_b; + wire ex4_is_eq_b; + wire ex4_sgn_eq; + + wire cp7_g32_00_b; + wire cp7_g32_12_b; + wire cp7_g32_34_b; + wire cp7_g32_56_b; + wire cp7_t32_00_b; + wire cp7_t32_12_b; + wire cp7_t32_34_b; + wire cp7_g64_02; + wire cp7_g64_36; + wire cp7_t64_02; + wire cp7_g128_06_b; + wire cp7_all1_b; + wire cp7_all1_p; + wire cp7_co_p0; + wire cp7_sel_p0n_x_b; + wire cp7_sel_p0n_y_b; + wire cp7_sel_p0_b; + wire cp7_sel_p1_b; + wire cp7_sub_sticky; + wire cp7_sub_stickyn; + wire cp7_add_frcp1_b; + wire cp7_add_frcp0_b; + + wire cp6_g32_00_b; + wire cp6_g32_12_b; + wire cp6_g32_34_b; + wire cp6_g32_56_b; + wire cp6_t32_00_b; + wire cp6_t32_12_b; + wire cp6_t32_34_b; + wire cp6_g64_02; + wire cp6_g64_36; + wire cp6_t64_02; + wire cp6_g128_06_b; + wire cp6_all1_b; + wire cp6_all1_p; + wire cp6_co_p0; + wire cp6_sel_p0n_x_b; + wire cp6_sel_p0n_y_b; + wire cp6_sel_p0_b; + wire cp6_sel_p1_b; + wire cp6_sub_sticky; + wire cp6_sub_stickyn; + wire cp6_add_frcp1_b; + wire cp6_add_frcp0_b; + + wire cp5_g32_00_b; + wire cp5_g32_12_b; + wire cp5_g32_34_b; + wire cp5_g32_56_b; + wire cp5_t32_00_b; + wire cp5_t32_12_b; + wire cp5_t32_34_b; + wire cp5_t32_56_b; + wire cp5_g64_02; + wire cp5_g64_36; + wire cp5_t64_02; + wire cp5_g128_06_b; + wire cp5_all1_b; + wire cp5_all1_p; + wire cp5_co_p0; + wire cp5_sel_p0n_x_b; + wire cp5_sel_p0n_y_b; + wire cp5_sel_p0_b; + wire cp5_sel_p1_b; + wire cp5_sub_sticky; + wire cp5_sub_stickyn; + wire cp5_add_frcp1_b; + wire cp5_add_frcp0_b; + + wire cp4_g32_01_b; + wire cp4_g32_23_b; + wire cp4_g32_45_b; + wire cp4_g32_66_b; + wire cp4_t32_01_b; + wire cp4_t32_23_b; + wire cp4_t32_45_b; + wire cp4_t32_66_b; + wire cp4_g64_03; + wire cp4_g64_46; + wire cp4_t64_03; + wire cp4_t64_46; + wire cp4_g128_06_b; + wire cp4_all1_b; + wire cp4_all1_p; + wire cp4_co_p0; + wire cp4_sel_p0n_x_b; + wire cp4_sel_p0n_y_b; + wire cp4_sel_p0_b; + wire cp4_sel_p1_b; + wire cp4_sub_sticky; + wire cp4_sub_stickyn; + wire cp4_add_frcp1_b; + wire cp4_add_frcp0_b; + + wire cp3_g32_00_b; + wire cp3_g32_12_b; + wire cp3_g32_34_b; + wire cp3_g32_56_b; + wire cp3_t32_00_b; + wire cp3_t32_12_b; + wire cp3_t32_34_b; + wire cp3_t32_56_b; + wire cp3_g64_02; + wire cp3_g64_36; + wire cp3_t64_02; + wire cp3_t64_36; + wire cp3_g128_06_b; + wire cp3_all1_b; + wire cp3_all1_p; + wire cp3_co_p0; + wire cp3_sel_p0n_x_b; + wire cp3_sel_p0n_y_b; + wire cp3_sel_p0_b; + wire cp3_sel_p1_b; + wire cp3_sub_sticky; + wire cp3_sub_stickyn; + wire cp3_add_frcp1_b; + wire cp3_add_frcp0_b; + + wire cp2_g32_01_b; + wire cp2_g32_23_b; + wire cp2_g32_45_b; + wire cp2_g32_66_b; + wire cp2_t32_01_b; + wire cp2_t32_23_b; + wire cp2_t32_45_b; + wire cp2_t32_66_b; + wire cp2_g64_03; + wire cp2_g64_46; + wire cp2_t64_03; + wire cp2_t64_46; + wire cp2_g128_06_b; + wire cp2_all1_b; + wire cp2_all1_p; + wire cp2_co_p0; + wire cp2_sel_p0n_x_b; + wire cp2_sel_p0n_y_b; + wire cp2_sel_p0_b; + wire cp2_sel_p1_b; + wire cp2_sub_sticky; + wire cp2_sub_stickyn; + wire cp2_add_frcp1_b; + wire cp2_add_frcp0_b; + + wire cp1_g32_01_b; + wire cp1_g32_23_b; + wire cp1_g32_45_b; + wire cp1_g32_66_b; + wire cp1_t32_01_b; + wire cp1_t32_23_b; + wire cp1_t32_45_b; + wire cp1_t32_66_b; + wire cp1_g64_03; + wire cp1_g64_46; + wire cp1_t64_03; + wire cp1_t64_46; + wire cp1_g128_06_b; + wire cp1_all1_b; + wire cp1_all1_p; + wire cp1_co_p0; + wire cp1_sel_p0n_x_b; + wire cp1_sel_p0n_y_b; + wire cp1_sel_p0_b; + wire cp1_sel_p1_b; + wire cp1_sub_sticky; + wire cp1_sub_stickyn; + wire cp1_add_frcp1_b; + wire cp1_add_frcp0_b; + + wire cp1_g32_11_b; //EXTRA + wire cp1_t32_11_b; + wire cp1_g64_13; + wire cp1_t64_13; + wire cp1_g128_16_b; + wire cp1_t128_16_b; + wire cp2_g64_23; + wire cp2_t64_23; + wire cp2_g128_26_b; + wire cp2_t128_26_b; + wire cp3_g128_36_b; + wire cp3_t128_36_b; + wire cp4_g128_46_b; + wire cp4_t128_46_b; + wire cp5_g64_56; + wire cp5_t64_56; + wire cp5_g128_56_b; + wire cp5_t128_56_b; + wire cp6_g32_66_b; + wire cp6_t32_66_b; + + wire cp1_g128_16; //DRIVER + wire cp1_t128_16; + wire cp2_g128_26; + wire cp2_t128_26; + wire cp3_g128_36; + wire cp3_t128_36; + wire cp4_g128_46; + wire cp4_t128_46; + wire cp5_g128_56; + wire cp5_t128_56; + wire cp6_g128_66; + wire cp6_t128_66; + + + //=######################################### + //= global carry chain + //=######################################### + // try to put all long wire from BYT to global + // parallel copies should allow for smaller aoi/oai blocks + + //=######################################### + //= CMP COPY + //=######################################### + + // --compare stuff---- + // -- c0 : gt + // -- c1 : ge + // + // ex4_my_eq <= (ex4_add_co_p1 and ex4_inc_all1 ) and not ex4_add_co_p0; -- ge * !gt + // ex4_my_gt <= (ex4_add_co_p0 and ex4_inc_all1 ) ; -- gt + // ex4_my_lt <= not(ex4_add_co_p1 and ex4_inc_all1 ) ; -- !ge + // + // ex4_flag_nan <= f_pic_ex4_is_nan; + // ex4_flag_gt <= f_pic_ex4_is_gt or (f_pic_ex4_cmp_sgnpos and ex4_my_gt) or (f_pic_ex4_cmp_sgnneg and ex4_my_lt) ; + // ex4_flag_lt <= f_pic_ex4_is_lt or (f_pic_ex4_cmp_sgnpos and ex4_my_lt) or (f_pic_ex4_cmp_sgnneg and ex4_my_gt) ; + // ex4_flag_eq <= f_pic_ex4_is_eq or (f_pic_ex4_cmp_sgnpos and ex4_my_eq) or (f_pic_ex4_cmp_sgnneg and ex4_my_eq) ; + + assign cp0_g32_01_b = (~(ex4_g16[0] | (ex4_t16[0] & ex4_g16[1]))); //cw_aoi21 + assign cp0_g32_23_b = (~(ex4_g16[2] | (ex4_t16[2] & ex4_g16[3]))); //cw_aoi21 + assign cp0_g32_45_b = (~(ex4_g16[4] | (ex4_t16[4] & ex4_g16[5]))); //cw_aoi21 + assign cp0_g32_66_b = (~(ex4_g16[6])); //cw_invert --done + + assign cp0_t32_01_b = (~(ex4_t16[0] & ex4_t16[1])); //cw_nand2 + assign cp0_t32_23_b = (~(ex4_t16[2] & ex4_t16[3])); //cw_nand2 + assign cp0_t32_45_b = (~(ex4_t16[4] & ex4_t16[5])); //cw_nand2 + assign cp0_t32_66_b = (~(ex4_t16[6])); //cw_invert + + assign cp0_g64_03 = (~(cp0_g32_01_b & (cp0_t32_01_b | cp0_g32_23_b))); //cw_oai21 + assign cp0_g64_46 = (~(cp0_g32_45_b & (cp0_t32_45_b | cp0_g32_66_b))); //cw_oai21 + + assign cp0_t64_03 = (~(cp0_t32_01_b | cp0_t32_23_b)); //cw_nor2 + assign cp0_t64_46 = (~(cp0_g32_45_b & (cp0_t32_45_b | cp0_t32_66_b))); //cw_oai21 + + assign cp0_g128_06_b = (~(cp0_g64_03 | (cp0_t64_03 & cp0_g64_46))); //cw_aoi21 + assign cp0_t128_06_b = (~(cp0_g64_03 | (cp0_t64_03 & cp0_t64_46))); //cw_aoi21 + + assign cp0_all1_b = (~ex4_inc_all1); //cw_invert + assign cp0_all1_p = (~cp0_all1_b); //cw_invert + assign cp0_co_p0 = (~(cp0_g128_06_b)); //cw_invert + assign cp0_co_p1 = (~(cp0_t128_06_b)); //cw_invert + + //-------------- incr eac selects -------------------- + + assign ex4_flip_inc_p0 = ex4_effsub; //NOT MAPPED --output-- + assign cp0_flip_inc_p1_b = (~(ex4_effsub & cp0_all1_b)); //cw_nand2 + assign ex4_flip_inc_p1 = (~(cp0_flip_inc_p1_b)); //cw_invert --output-- + + assign ex4_inc_sel_p1 = (~cp0_g128_06_b); //cw_invert --OUTPUT-- + assign ex4_inc_sel_p0_b = (~cp0_g128_06_b); //cw_invert + assign ex4_inc_sel_p0 = (~ex4_inc_sel_p0_b); //cw_invert --OUTPUT-- + + //-------------- sign selects -------------------- + + assign ex4_sign_carry_b = (~(ex4_effsub & cp0_all1_p & cp0_co_p0)); //cw_nand3 + assign ex4_sign_carry = (~(ex4_sign_carry_b)); //cw_invert --OUTPUT-- + + //--------------- compares --------------------------- + + assign ex4_my_gt_b = (~(cp0_co_p0 & cp0_all1_p)); //cw_nand2 + assign ex4_my_lt = (~(cp0_co_p1 & cp0_all1_p)); //cw_nand2 + assign ex4_my_eq_b = (~(cp0_co_p1 & cp0_all1_p & cp0_g128_06_b)); //cw_nand3 + + assign ex4_my_gt = (~ex4_my_gt_b); //cw_invert + assign ex4_my_eq = (~ex4_my_eq_b); //cw_invert + + assign ex4_gt_pos_b = (~(ex4_my_gt & f_pic_ex4_cmp_sgnpos)); //cw_nand2 + assign ex4_gt_neg_b = (~(ex4_my_lt & f_pic_ex4_cmp_sgnneg)); //cw_nand2 + assign ex4_lt_pos_b = (~(ex4_my_lt & f_pic_ex4_cmp_sgnpos)); //cw_nand2 + assign ex4_lt_neg_b = (~(ex4_my_gt & f_pic_ex4_cmp_sgnneg)); //cw_nand2 + assign ex4_eq_eq_b = (~(ex4_my_eq & ex4_sgn_eq)); //cw_nand3 + + assign ex4_flag_gt = (~(ex4_gt_pos_b & ex4_gt_neg_b & ex4_is_gt_b)); //cw_nand3 --output-- + assign ex4_flag_gt_cp1 = (~(ex4_gt_pos_b & ex4_gt_neg_b & ex4_is_gt_b)); //cw_nand3 --output-- + assign ex4_flag_lt = (~(ex4_lt_pos_b & ex4_lt_neg_b & ex4_is_lt_b)); //cw_nand3 --output-- + assign ex4_flag_lt_cp1 = (~(ex4_lt_pos_b & ex4_lt_neg_b & ex4_is_lt_b)); //cw_nand3 --output-- + assign ex4_flag_eq = (~(ex4_eq_eq_b & ex4_is_eq_b)); //cw_nand2 --output-- + assign ex4_flag_eq_cp1 = (~(ex4_eq_eq_b & ex4_is_eq_b)); //cw_nand2 --output-- + + assign ex4_flag_nan = f_pic_ex4_is_nan; //NOT MAPPED --output-- + assign ex4_flag_nan_cp1 = f_pic_ex4_is_nan; //NOT MAPPED --output-- + + assign ex4_is_gt_b = (~(f_pic_ex4_is_gt)); //NOT MAPPED + assign ex4_is_lt_b = (~(f_pic_ex4_is_lt)); //NOT MAPPED + assign ex4_is_eq_b = (~(f_pic_ex4_is_eq)); //NOT MAPPED + assign ex4_sgn_eq = f_pic_ex4_cmp_sgnpos | f_pic_ex4_cmp_sgnneg; //NOT MAPPED + + //=######################################### + //= BYT_0 MSB COPY + //=######################################### + + assign cp1_g32_11_b = (~(ex4_g16[1])); //cw_aoi21 --EXTRA + assign cp1_g32_01_b = (~(ex4_g16[0] | (ex4_t16[0] & ex4_g16[1]))); //cw_aoi21 + assign cp1_g32_23_b = (~(ex4_g16[2] | (ex4_t16[2] & ex4_g16[3]))); //cw_aoi21 + assign cp1_g32_45_b = (~(ex4_g16[4] | (ex4_t16[4] & ex4_g16[5]))); //cw_aoi21 + assign cp1_g32_66_b = (~(ex4_g16[6])); //cw_invert --done + + assign cp1_t32_11_b = (~(ex4_t16[1])); //cw_invert --EXTRA + assign cp1_t32_01_b = (~(ex4_t16[0] & ex4_t16[1])); //cw_nand2 + assign cp1_t32_23_b = (~(ex4_t16[2] & ex4_t16[3])); //cw_nand2 + assign cp1_t32_45_b = (~(ex4_t16[4] & ex4_t16[5])); //cw_nand2 + assign cp1_t32_66_b = (~(ex4_t16[6])); //cw_invert + + assign cp1_g64_03 = (~(cp1_g32_01_b & (cp1_t32_01_b | cp1_g32_23_b))); //cw_oai21 + assign cp1_g64_13 = (~(cp1_g32_11_b & (cp1_t32_11_b | cp1_g32_23_b))); //cw_oai21 --EXTRA + assign cp1_g64_46 = (~(cp1_g32_45_b & (cp1_t32_45_b | cp1_g32_66_b))); //cw_oai21 + + assign cp1_t64_03 = (~(cp1_t32_01_b | cp1_t32_23_b)); //cw_nor2 + assign cp1_t64_13 = (~(cp1_t32_11_b | cp1_t32_23_b)); //cw_nor2 --EXTRA + assign cp1_t64_46 = (~(cp1_g32_45_b & (cp1_t32_45_b | cp1_t32_66_b))); //cw_oai21 + + assign cp1_g128_06_b = (~(cp1_g64_03 | (cp1_t64_03 & cp1_g64_46))); //cw_aoi21 + assign cp1_g128_16_b = (~(cp1_g64_13 | (cp1_t64_13 & cp1_g64_46))); //cw_aoi21 --EXTRA + assign cp1_t128_16_b = (~(cp1_g64_13 | (cp1_t64_13 & cp1_t64_46))); //cw_aoi21 --EXTRA + + assign ex4_g128[1] = (~(cp1_g128_16_b)); //cw_invert --OUTPUT-- + assign cp1_g128_16 = (~(cp1_g128_16_b)); //cw_invert + assign ex4_g128_b[1] = (~(cp1_g128_16)); //cw_invert --OUTPUT-- + assign ex4_t128[1] = (~(cp1_t128_16_b)); //cw_invert --OUTPUT-- + assign cp1_t128_16 = (~(cp1_t128_16_b)); //cw_invert + assign ex4_t128_b[1] = (~(cp1_t128_16)); //cw_invert --OUTPUT-- + + assign cp1_all1_b = (~ex4_inc_all1); //cw_invert + assign cp1_all1_p = (~cp1_all1_b); //cw_invert + assign cp1_co_p0 = (~(cp1_g128_06_b)); //cw_invert + + assign cp1_sel_p0n_x_b = (~(cp1_all1_b & ex4_effsub_npz)); //cw_nand2 + assign cp1_sel_p0n_y_b = (~(cp1_g128_06_b & ex4_effsub_npz)); //cw_nand2 + assign cp1_sel_p0_b = (~(cp1_co_p0 & cp1_all1_p & cp1_sub_sticky)); //cw_nand3 + assign cp1_sel_p1_b = (~(cp1_co_p0 & cp1_all1_p & cp1_sub_stickyn)); //cw_nand3 + + assign ex4_eac_sel_p0n[0] = (~(cp1_sel_p0n_x_b & cp1_sel_p0n_y_b)); //cw_nand2 --OUTPUT-- + assign ex4_eac_sel_p0[0] = (~(cp1_sel_p0_b & cp1_add_frcp0_b)); //cw_nand2 --OUTPUT-- + assign ex4_eac_sel_p1[0] = (~(cp1_sel_p1_b & cp1_add_frcp1_b)); //cw_nand2 --OUTPUT-- + + assign cp1_sub_sticky = ex4_effsub_npz & f_alg_ex4_sticky; //NOT MAPPED + assign cp1_sub_stickyn = ex4_effsub_npz & (~f_alg_ex4_sticky); //NOT MAPPED + assign cp1_add_frcp1_b = (~(ex4_effadd_npz & f_alg_ex4_frc_sel_p1)); //NOT MAPPED + assign cp1_add_frcp0_b = (~(ex4_effadd_npz & (~f_alg_ex4_frc_sel_p1))); //NOT MAPPED + + //=######################################### + //= BYT_1 MSB COPY + //=######################################### + + assign cp2_g32_01_b = (~(ex4_g16[0] | (ex4_t16[0] & ex4_g16[1]))); //cw_aoi21 + assign cp2_g32_23_b = (~(ex4_g16[2] | (ex4_t16[2] & ex4_g16[3]))); //cw_aoi21 + assign cp2_g32_45_b = (~(ex4_g16[4] | (ex4_t16[4] & ex4_g16[5]))); //cw_aoi21 + assign cp2_g32_66_b = (~(ex4_g16[6])); //cw_invert --done + + assign cp2_t32_01_b = (~(ex4_t16[0] & ex4_t16[1])); //cw_nand2 + assign cp2_t32_23_b = (~(ex4_t16[2] & ex4_t16[3])); //cw_nand2 + assign cp2_t32_45_b = (~(ex4_t16[4] & ex4_t16[5])); //cw_nand2 + assign cp2_t32_66_b = (~(ex4_t16[6])); //cw_invert + + assign cp2_g64_23 = (~(cp2_g32_23_b)); //cw_invert --EXTRA + assign cp2_g64_03 = (~(cp2_g32_01_b & (cp2_t32_01_b | cp2_g32_23_b))); //cw_oai21 + assign cp2_g64_46 = (~(cp2_g32_45_b & (cp2_t32_45_b | cp2_g32_66_b))); //cw_oai21 + + assign cp2_t64_23 = (~(cp2_t32_23_b)); //cw_invert --EXTRA + assign cp2_t64_03 = (~(cp2_t32_01_b | cp2_t32_23_b)); //cw_nor2 + assign cp2_t64_46 = (~(cp2_g32_45_b & (cp2_t32_45_b | cp2_t32_66_b))); //cw_oai21 + + assign cp2_g128_06_b = (~(cp2_g64_03 | (cp2_t64_03 & cp2_g64_46))); //cw_aoi21 + assign cp2_g128_26_b = (~(cp2_g64_23 | (cp2_t64_23 & cp2_g64_46))); //cw_aoi21 --EXTRA + assign cp2_t128_26_b = (~(cp2_g64_23 | (cp2_t64_23 & cp2_t64_46))); //cw_aoi21 --EXTRA + + assign ex4_g128[2] = (~(cp2_g128_26_b)); //cw_invert --OUTPUT-- + assign cp2_g128_26 = (~(cp2_g128_26_b)); //cw_invert + assign ex4_g128_b[2] = (~(cp2_g128_26)); //cw_invert --OUTPUT-- + assign ex4_t128[2] = (~(cp2_t128_26_b)); //cw_invert --OUTPUT-- + assign cp2_t128_26 = (~(cp2_t128_26_b)); //cw_invert + assign ex4_t128_b[2] = (~(cp2_t128_26)); //cw_invert --OUTPUT-- + + assign cp2_all1_b = (~ex4_inc_all1); //cw_invert + assign cp2_all1_p = (~cp2_all1_b); //cw_invert + assign cp2_co_p0 = (~(cp2_g128_06_b)); //cw_invert + + assign cp2_sel_p0n_x_b = (~(cp2_all1_b & ex4_effsub_npz)); //cw_nand2 + assign cp2_sel_p0n_y_b = (~(cp2_g128_06_b & ex4_effsub_npz)); //cw_nand2 + assign cp2_sel_p0_b = (~(cp2_co_p0 & cp2_all1_p & cp2_sub_sticky)); //cw_nand3 + assign cp2_sel_p1_b = (~(cp2_co_p0 & cp2_all1_p & cp2_sub_stickyn)); //cw_nand3 + + assign ex4_eac_sel_p0n[1] = (~(cp2_sel_p0n_x_b & cp2_sel_p0n_y_b)); //cw_nand2 --OUTPUT-- + assign ex4_eac_sel_p0[1] = (~(cp2_sel_p0_b & cp2_add_frcp0_b)); //cw_nand2 --OUTPUT-- + assign ex4_eac_sel_p1[1] = (~(cp2_sel_p1_b & cp2_add_frcp1_b)); //cw_nand2 --OUTPUT-- + + assign cp2_sub_sticky = ex4_effsub_npz & f_alg_ex4_sticky; //NOT MAPPED + assign cp2_sub_stickyn = ex4_effsub_npz & (~f_alg_ex4_sticky); //NOT MAPPED + assign cp2_add_frcp1_b = (~(ex4_effadd_npz & f_alg_ex4_frc_sel_p1)); //NOT MAPPED + assign cp2_add_frcp0_b = (~(ex4_effadd_npz & (~f_alg_ex4_frc_sel_p1))); //NOT MAPPED + + //=######################################### + //= BYT_2 MSB COPY + //=######################################### + + assign cp3_g32_00_b = (~(ex4_g16[0])); //cw_invert + assign cp3_g32_12_b = (~(ex4_g16[1] | (ex4_t16[1] & ex4_g16[2]))); //cw_aoi21 + assign cp3_g32_34_b = (~(ex4_g16[3] | (ex4_t16[3] & ex4_g16[4]))); //cw_aoi21 + assign cp3_g32_56_b = (~(ex4_g16[5] | (ex4_t16[5] & ex4_g16[6]))); //cw_aoi21 + + assign cp3_t32_00_b = (~(ex4_t16[0])); //cw_invert + assign cp3_t32_12_b = (~(ex4_t16[1] & ex4_t16[2])); //cw_nand2 + assign cp3_t32_34_b = (~(ex4_t16[3] & ex4_t16[4])); //cw_nand2 + assign cp3_t32_56_b = (~(ex4_g16[5] | (ex4_t16[5] & ex4_t16[6]))); //cw_aoi21 + + assign cp3_g64_02 = (~(cp3_g32_00_b & (cp3_t32_00_b | cp3_g32_12_b))); //cw_oai21 + assign cp3_g64_36 = (~(cp3_g32_34_b & (cp3_t32_34_b | cp3_g32_56_b))); //cw_oai21 + + assign cp3_t64_02 = (~(cp3_t32_00_b | cp3_t32_12_b)); //cw_nor2 + assign cp3_t64_36 = (~(cp3_g32_34_b & (cp3_t32_34_b | cp3_t32_56_b))); //cw_oai21 + + assign cp3_g128_06_b = (~(cp3_g64_02 | (cp3_t64_02 & cp3_g64_36))); //cw_aoi21 + assign cp3_g128_36_b = (~(cp3_g64_36)); //cw_invert --EXTRA + assign cp3_t128_36_b = (~(cp3_t64_36)); //cw_invert --EXTRA + + assign ex4_g128[3] = (~(cp3_g128_36_b)); //cw_invert --OUTPUT-- + assign cp3_g128_36 = (~(cp3_g128_36_b)); //cw_invert + assign ex4_g128_b[3] = (~(cp3_g128_36)); //cw_invert --OUTPUT-- + assign ex4_t128[3] = (~(cp3_t128_36_b)); //cw_invert --OUTPUT-- + assign cp3_t128_36 = (~(cp3_t128_36_b)); //cw_invert + assign ex4_t128_b[3] = (~(cp3_t128_36)); //cw_invert --OUTPUT-- + + assign cp3_all1_b = (~ex4_inc_all1); //cw_invert + assign cp3_all1_p = (~cp3_all1_b); //cw_invert + assign cp3_co_p0 = (~(cp3_g128_06_b)); //cw_invert + + assign cp3_sel_p0n_x_b = (~(cp3_all1_b & ex4_effsub_npz)); //cw_nand2 + assign cp3_sel_p0n_y_b = (~(cp3_g128_06_b & ex4_effsub_npz)); //cw_nand2 + assign cp3_sel_p0_b = (~(cp3_co_p0 & cp3_all1_p & cp3_sub_sticky)); //cw_nand3 + assign cp3_sel_p1_b = (~(cp3_co_p0 & cp3_all1_p & cp3_sub_stickyn)); //cw_nand3 + + assign ex4_eac_sel_p0n[2] = (~(cp3_sel_p0n_x_b & cp3_sel_p0n_y_b)); //cw_nand2 --OUTPUT-- + assign ex4_eac_sel_p0[2] = (~(cp3_sel_p0_b & cp3_add_frcp0_b)); //cw_nand2 --OUTPUT-- + assign ex4_eac_sel_p1[2] = (~(cp3_sel_p1_b & cp3_add_frcp1_b)); //cw_nand2 --OUTPUT-- + + assign cp3_sub_sticky = ex4_effsub_npz & f_alg_ex4_sticky; //NOT MAPPED + assign cp3_sub_stickyn = ex4_effsub_npz & (~f_alg_ex4_sticky); //NOT MAPPED + assign cp3_add_frcp1_b = (~(ex4_effadd_npz & f_alg_ex4_frc_sel_p1)); //NOT MAPPED + assign cp3_add_frcp0_b = (~(ex4_effadd_npz & (~f_alg_ex4_frc_sel_p1))); //NOT MAPPED + + //=######################################### + //= BYT_3 MSB COPY + //=######################################### + + assign cp4_g32_01_b = (~(ex4_g16[0] | (ex4_t16[0] & ex4_g16[1]))); //cw_aoi21 + assign cp4_g32_23_b = (~(ex4_g16[2] | (ex4_t16[2] & ex4_g16[3]))); //cw_aoi21 + assign cp4_g32_45_b = (~(ex4_g16[4] | (ex4_t16[4] & ex4_g16[5]))); //cw_aoi21 + assign cp4_g32_66_b = (~(ex4_g16[6])); //cw_invert --done + + assign cp4_t32_01_b = (~(ex4_t16[0] & ex4_t16[1])); //cw_nand2 + assign cp4_t32_23_b = (~(ex4_t16[2] & ex4_t16[3])); //cw_nand2 + assign cp4_t32_45_b = (~(ex4_t16[4] & ex4_t16[5])); //cw_nand2 + assign cp4_t32_66_b = (~(ex4_t16[6])); //cw_invert + + assign cp4_g64_03 = (~(cp4_g32_01_b & (cp4_t32_01_b | cp4_g32_23_b))); //cw_oai21 + assign cp4_g64_46 = (~(cp4_g32_45_b & (cp4_t32_45_b | cp4_g32_66_b))); //cw_oai21 + + assign cp4_t64_03 = (~(cp4_t32_01_b | cp4_t32_23_b)); //cw_nor2 + assign cp4_t64_46 = (~(cp4_g32_45_b & (cp4_t32_45_b | cp4_t32_66_b))); //cw_oai21 + + assign cp4_g128_06_b = (~(cp4_g64_03 | (cp4_t64_03 & cp4_g64_46))); //cw_aoi21 + assign cp4_g128_46_b = (~(cp4_g64_46)); //cw_invert --EXTRA + assign cp4_t128_46_b = (~(cp4_t64_46)); //cw_invert --EXTRA + + assign ex4_g128[4] = (~(cp4_g128_46_b)); //cw_invert --OUTPUT-- + assign cp4_g128_46 = (~(cp4_g128_46_b)); //cw_invert + assign ex4_g128_b[4] = (~(cp4_g128_46)); //cw_invert --OUTPUT-- + assign ex4_t128[4] = (~(cp4_t128_46_b)); //cw_invert --OUTPUT-- + assign cp4_t128_46 = (~(cp4_t128_46_b)); //cw_invert + assign ex4_t128_b[4] = (~(cp4_t128_46)); //cw_invert --OUTPUT-- + + assign cp4_all1_b = (~ex4_inc_all1); //cw_invert + assign cp4_all1_p = (~cp4_all1_b); //cw_invert + assign cp4_co_p0 = (~(cp4_g128_06_b)); //cw_invert + + assign cp4_sel_p0n_x_b = (~(cp4_all1_b & ex4_effsub_npz)); //cw_nand2 + assign cp4_sel_p0n_y_b = (~(cp4_g128_06_b & ex4_effsub_npz)); //cw_nand2 + assign cp4_sel_p0_b = (~(cp4_co_p0 & cp4_all1_p & cp4_sub_sticky)); //cw_nand3 + assign cp4_sel_p1_b = (~(cp4_co_p0 & cp4_all1_p & cp4_sub_stickyn)); //cw_nand3 + + assign ex4_eac_sel_p0n[3] = (~(cp4_sel_p0n_x_b & cp4_sel_p0n_y_b)); //cw_nand2 --OUTPUT-- + assign ex4_eac_sel_p0[3] = (~(cp4_sel_p0_b & cp4_add_frcp0_b)); //cw_nand2 --OUTPUT-- + assign ex4_eac_sel_p1[3] = (~(cp4_sel_p1_b & cp4_add_frcp1_b)); //cw_nand2 --OUTPUT-- + + assign cp4_sub_sticky = ex4_effsub_npz & f_alg_ex4_sticky; //NOT MAPPED + assign cp4_sub_stickyn = ex4_effsub_npz & (~f_alg_ex4_sticky); //NOT MAPPED + assign cp4_add_frcp1_b = (~(ex4_effadd_npz & f_alg_ex4_frc_sel_p1)); //NOT MAPPED + assign cp4_add_frcp0_b = (~(ex4_effadd_npz & (~f_alg_ex4_frc_sel_p1))); //NOT MAPPED + + //=######################################### + //= BYT_4 + //=######################################### + + assign cp5_g32_00_b = (~(ex4_g16[0])); //cw_invert + assign cp5_g32_12_b = (~(ex4_g16[1] | (ex4_t16[1] & ex4_g16[2]))); //cw_aoi21 + assign cp5_g32_34_b = (~(ex4_g16[3] | (ex4_t16[3] & ex4_g16[4]))); //cw_aoi21 + assign cp5_g32_56_b = (~(ex4_g16[5] | (ex4_t16[5] & ex4_g16[6]))); //cw_aoi21 + + assign cp5_t32_00_b = (~(ex4_t16[0])); //cw_invert + assign cp5_t32_12_b = (~(ex4_t16[1] & ex4_t16[2])); //cw_nand2 + assign cp5_t32_34_b = (~(ex4_t16[3] & ex4_t16[4])); //cw_nand2 + assign cp5_t32_56_b = (~(ex4_g16[5] | (ex4_t16[5] & ex4_t16[6]))); //cw_aoi21 + + assign cp5_g64_02 = (~(cp5_g32_00_b & (cp5_t32_00_b | cp5_g32_12_b))); //cw_oai21 + assign cp5_g64_36 = (~(cp5_g32_34_b & (cp5_t32_34_b | cp5_g32_56_b))); //cw_oai21 + assign cp5_g64_56 = (~(cp5_g32_56_b)); //cw_invert --EXTRA + + assign cp5_t64_02 = (~(cp5_t32_00_b | cp5_t32_12_b)); //cw_nor2 + assign cp5_t64_56 = (~(cp5_t32_56_b)); //cw_invert --EXTRA + + assign cp5_g128_06_b = (~(cp5_g64_02 | (cp5_t64_02 & cp5_g64_36))); //cw_aoi21 + assign cp5_g128_56_b = (~(cp5_g64_56)); //cw_invert --EXTRA + assign cp5_t128_56_b = (~(cp5_t64_56)); //cw_invert --EXTRA + + assign ex4_g128[5] = (~(cp5_g128_56_b)); //cw_invert --OUTPUT-- + assign cp5_g128_56 = (~(cp5_g128_56_b)); //cw_invert + assign ex4_g128_b[5] = (~(cp5_g128_56)); //cw_invert --OUTPUT-- + assign ex4_t128[5] = (~(cp5_t128_56_b)); //cw_invert --OUTPUT-- + assign cp5_t128_56 = (~(cp5_t128_56_b)); //cw_invert + assign ex4_t128_b[5] = (~(cp5_t128_56)); //cw_invert --OUTPUT-- + + assign cp5_all1_b = (~ex4_inc_all1); //cw_invert + assign cp5_all1_p = (~cp5_all1_b); //cw_invert + assign cp5_co_p0 = (~(cp5_g128_06_b)); //cw_invert + + assign cp5_sel_p0n_x_b = (~(cp5_all1_b & ex4_effsub_npz)); //cw_nand2 + assign cp5_sel_p0n_y_b = (~(cp5_g128_06_b & ex4_effsub_npz)); //cw_nand2 + assign cp5_sel_p0_b = (~(cp5_co_p0 & cp5_all1_p & cp5_sub_sticky)); //cw_nand3 + assign cp5_sel_p1_b = (~(cp5_co_p0 & cp5_all1_p & cp5_sub_stickyn)); //cw_nand3 + + assign ex4_eac_sel_p0n[4] = (~(cp5_sel_p0n_x_b & cp5_sel_p0n_y_b)); //cw_nand2 --OUTPUT-- + assign ex4_eac_sel_p0[4] = (~(cp5_sel_p0_b & cp5_add_frcp0_b)); //cw_nand2 --OUTPUT-- + assign ex4_eac_sel_p1[4] = (~(cp5_sel_p1_b & cp5_add_frcp1_b)); //cw_nand2 --OUTPUT-- + + assign cp5_sub_sticky = ex4_effsub_npz & f_alg_ex4_sticky; //NOT MAPPED + assign cp5_sub_stickyn = ex4_effsub_npz & (~f_alg_ex4_sticky); //NOT MAPPED + assign cp5_add_frcp1_b = (~(ex4_effadd_npz & f_alg_ex4_frc_sel_p1)); //NOT MAPPED + assign cp5_add_frcp0_b = (~(ex4_effadd_npz & (~f_alg_ex4_frc_sel_p1))); //NOT MAPPED + + //=######################################### + //= BYT_5 + //=######################################### + + assign cp6_g32_00_b = (~(ex4_g16[0])); //cw_invert + assign cp6_g32_12_b = (~(ex4_g16[1] | (ex4_t16[1] & ex4_g16[2]))); //cw_aoi21 + assign cp6_g32_34_b = (~(ex4_g16[3] | (ex4_t16[3] & ex4_g16[4]))); //cw_aoi21 + assign cp6_g32_56_b = (~(ex4_g16[5] | (ex4_t16[5] & ex4_g16[6]))); //cw_aoi21 + assign cp6_g32_66_b = (~(ex4_g16[6])); //cw_invert EXTRA + + assign cp6_t32_00_b = (~(ex4_t16[0])); //cw_invert + assign cp6_t32_12_b = (~(ex4_t16[1] & ex4_t16[2])); //cw_nand2 + assign cp6_t32_34_b = (~(ex4_t16[3] & ex4_t16[4])); //cw_nand2 + assign cp6_t32_66_b = (~(ex4_t16[6])); //cw_invert EXTRA + + assign cp6_g64_02 = (~(cp6_g32_00_b & (cp6_t32_00_b | cp6_g32_12_b))); //cw_oai21 + assign cp6_g64_36 = (~(cp6_g32_34_b & (cp6_t32_34_b | cp6_g32_56_b))); //cw_oai21 + + assign cp6_t64_02 = (~(cp6_t32_00_b | cp6_t32_12_b)); //cw_nor2 + + assign cp6_g128_06_b = (~(cp6_g64_02 | (cp6_t64_02 & cp6_g64_36))); //cw_aoi21 + + assign ex4_g128[6] = (~(cp6_g32_66_b)); //cw_invert --OUTPUT-- + assign cp6_g128_66 = (~(cp6_g32_66_b)); //cw_invert + assign ex4_g128_b[6] = (~(cp6_g128_66)); //cw_invert --OUTPUT-- + assign ex4_t128[6] = (~(cp6_t32_66_b)); //cw_invert --OUTPUT-- + assign cp6_t128_66 = (~(cp6_t32_66_b)); //cw_invert + assign ex4_t128_b[6] = (~(cp6_t128_66)); //cw_invert --OUTPUT-- + + assign cp6_all1_b = (~ex4_inc_all1); //cw_invert + assign cp6_all1_p = (~cp6_all1_b); //cw_invert + assign cp6_co_p0 = (~(cp6_g128_06_b)); //cw_invert + + assign cp6_sel_p0n_x_b = (~(cp6_all1_b & ex4_effsub_npz)); //cw_nand2 + assign cp6_sel_p0n_y_b = (~(cp6_g128_06_b & ex4_effsub_npz)); //cw_nand2 + assign cp6_sel_p0_b = (~(cp6_co_p0 & cp6_all1_p & cp6_sub_sticky)); //cw_nand3 + assign cp6_sel_p1_b = (~(cp6_co_p0 & cp6_all1_p & cp6_sub_stickyn)); //cw_nand3 + + assign ex4_eac_sel_p0n[5] = (~(cp6_sel_p0n_x_b & cp6_sel_p0n_y_b)); //cw_nand2 --OUTPUT-- + assign ex4_eac_sel_p0[5] = (~(cp6_sel_p0_b & cp6_add_frcp0_b)); //cw_nand2 --OUTPUT-- + assign ex4_eac_sel_p1[5] = (~(cp6_sel_p1_b & cp6_add_frcp1_b)); //cw_nand2 --OUTPUT-- + + assign cp6_sub_sticky = ex4_effsub_npz & f_alg_ex4_sticky; //NOT MAPPED + assign cp6_sub_stickyn = ex4_effsub_npz & (~f_alg_ex4_sticky); //NOT MAPPED + assign cp6_add_frcp1_b = (~(ex4_effadd_npz & f_alg_ex4_frc_sel_p1)); //NOT MAPPED + assign cp6_add_frcp0_b = (~(ex4_effadd_npz & (~f_alg_ex4_frc_sel_p1))); //NOT MAPPED + + //=######################################### + //= BYT_6 LSB COPY + //=######################################### + + assign cp7_g32_00_b = (~(ex4_g16[0])); //cw_invert + assign cp7_g32_12_b = (~(ex4_g16[1] | (ex4_t16[1] & ex4_g16[2]))); //cw_aoi21 + assign cp7_g32_34_b = (~(ex4_g16[3] | (ex4_t16[3] & ex4_g16[4]))); //cw_aoi21 + assign cp7_g32_56_b = (~(ex4_g16[5] | (ex4_t16[5] & ex4_g16[6]))); //cw_aoi21 + + assign cp7_t32_00_b = (~(ex4_t16[0])); //cw_invert + assign cp7_t32_12_b = (~(ex4_t16[1] & ex4_t16[2])); //cw_nand2 + assign cp7_t32_34_b = (~(ex4_t16[3] & ex4_t16[4])); //cw_nand2 + + assign cp7_g64_02 = (~(cp7_g32_00_b & (cp7_t32_00_b | cp7_g32_12_b))); //cw_oai21 + assign cp7_g64_36 = (~(cp7_g32_34_b & (cp7_t32_34_b | cp7_g32_56_b))); //cw_oai21 + + assign cp7_t64_02 = (~(cp7_t32_00_b | cp7_t32_12_b)); //cw_nor2 + + assign cp7_g128_06_b = (~(cp7_g64_02 | (cp7_t64_02 & cp7_g64_36))); //cw_aoi21 + + assign cp7_all1_b = (~ex4_inc_all1); //cw_invert + assign cp7_all1_p = (~cp7_all1_b); //cw_invert + assign cp7_co_p0 = (~(cp7_g128_06_b)); //cw_invert + + assign cp7_sel_p0n_x_b = (~(cp7_all1_b & ex4_effsub_npz)); //cw_nand2 + assign cp7_sel_p0n_y_b = (~(cp7_g128_06_b & ex4_effsub_npz)); //cw_nand2 + assign cp7_sel_p0_b = (~(cp7_co_p0 & cp7_all1_p & cp7_sub_sticky)); //cw_nand3 + assign cp7_sel_p1_b = (~(cp7_co_p0 & cp7_all1_p & cp7_sub_stickyn)); //cw_nand3 + + assign ex4_eac_sel_p0n[6] = (~(cp7_sel_p0n_x_b & cp7_sel_p0n_y_b)); //cw_nand2 --OUTPUT-- + assign ex4_eac_sel_p0[6] = (~(cp7_sel_p0_b & cp7_add_frcp0_b)); //cw_nand2 --OUTPUT-- + assign ex4_eac_sel_p1[6] = (~(cp7_sel_p1_b & cp7_add_frcp1_b)); //cw_nand2 --OUTPUT-- + + assign cp7_sub_sticky = ex4_effsub_npz & f_alg_ex4_sticky; //NOT MAPPED + assign cp7_sub_stickyn = ex4_effsub_npz & (~f_alg_ex4_sticky); //NOT MAPPED + assign cp7_add_frcp1_b = (~(ex4_effadd_npz & f_alg_ex4_frc_sel_p1)); //NOT MAPPED + assign cp7_add_frcp0_b = (~(ex4_effadd_npz & (~f_alg_ex4_frc_sel_p1))); //NOT MAPPED + +endmodule diff --git a/dev/verilog/work/fu_alg.v b/dev/verilog/work/fu_alg.v new file mode 100755 index 0000000..c143664 --- /dev/null +++ b/dev/verilog/work/fu_alg.v @@ -0,0 +1,1078 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + + `include "tri_a2o.vh" + +module fu_alg( + vdd, + gnd, + clkoff_b, + act_dis, + flush, + delay_lclkr, + mpw1_b, + mpw2_b, + sg_1, + thold_1, + fpu_enable, + nclk, + f_alg_si, + f_alg_so, + ex1_act, + ex2_act, + f_byp_alg_ex2_b_expo, + f_byp_alg_ex2_a_expo, + f_byp_alg_ex2_c_expo, + f_byp_alg_ex2_b_frac, + f_byp_alg_ex2_b_sign, + f_fmt_ex2_prod_zero, + f_fmt_ex2_b_zero, + f_fmt_ex2_pass_sel, + f_fmt_ex3_pass_frac, + f_dcd_ex1_sp, + f_dcd_ex1_from_integer_b, + f_dcd_ex1_to_integer_b, + f_dcd_ex1_word_b, + f_dcd_ex1_uns_b, + f_pic_ex2_rnd_to_int, + f_pic_ex2_frsp_ue1, + f_pic_ex2_effsub_raw, + f_pic_ex2_sh_unf_ig_b, + f_pic_ex2_sh_unf_do, + f_pic_ex2_sh_ovf_ig_b, + f_pic_ex2_sh_ovf_do, + f_pic_ex3_rnd_nr, + f_pic_ex3_rnd_inf_ok, + f_alg_ex2_sign_frmw, + f_alg_ex3_byp_nonflip, + f_alg_ex3_res, + f_alg_ex3_sel_byp, + f_alg_ex3_effsub_eac_b, + f_alg_ex3_prod_z, + f_alg_ex3_sh_unf, + f_alg_ex3_sh_ovf, + f_alg_ex4_frc_sel_p1, + f_alg_ex4_sticky, + f_alg_ex4_int_fr, + f_alg_ex4_int_fi +); +// parameter expand_type = 2; // 0 - ibm tech, 1 - other ); + inout vdd; + inout gnd; + input clkoff_b; // tiup + input act_dis; // ??tidn?? + input flush; // ??tidn?? + input [1:3] delay_lclkr; // tidn, + input [1:3] mpw1_b; // tidn, + input [0:0] mpw2_b; // tidn, + input sg_1; + input thold_1; + input fpu_enable; //dc_act + input [0:`NCLK_WIDTH-1] nclk; + + input f_alg_si; //perv + output f_alg_so; //perv + input ex1_act; //act + input ex2_act; //act + + input [1:13] f_byp_alg_ex2_b_expo; + input [1:13] f_byp_alg_ex2_a_expo; + input [1:13] f_byp_alg_ex2_c_expo; + input [0:52] f_byp_alg_ex2_b_frac; + input f_byp_alg_ex2_b_sign; + + input f_fmt_ex2_prod_zero; // valid and Zero (Madd/Mul) + input f_fmt_ex2_b_zero; // valid and zero (could be denorm, so zero out B) + input f_fmt_ex2_pass_sel; + input [0:52] f_fmt_ex3_pass_frac; + + input f_dcd_ex1_sp; + input f_dcd_ex1_from_integer_b; // K, spec, round + input f_dcd_ex1_to_integer_b; // K, spec, round + input f_dcd_ex1_word_b; + input f_dcd_ex1_uns_b; + + input f_pic_ex2_rnd_to_int; + input f_pic_ex2_frsp_ue1; // K, spec, round + input f_pic_ex2_effsub_raw; // + input f_pic_ex2_sh_unf_ig_b; // fcfid + input f_pic_ex2_sh_unf_do; // (do not know why want this) + input f_pic_ex2_sh_ovf_ig_b; // fcfid + input f_pic_ex2_sh_ovf_do; // fsel, fpscr, fmr, + input f_pic_ex3_rnd_nr; // + input f_pic_ex3_rnd_inf_ok; // pi/pos, ni/neg + + output f_alg_ex2_sign_frmw; // sign bit for from_integer_word_signed + output f_alg_ex3_byp_nonflip; + output [0:162] f_alg_ex3_res; //sad3/add + output f_alg_ex3_sel_byp; // all eac selects off + output f_alg_ex3_effsub_eac_b; // includes cancelations + output f_alg_ex3_prod_z; + output f_alg_ex3_sh_unf; // f_pic + output f_alg_ex3_sh_ovf; // f_pic + output f_alg_ex4_frc_sel_p1; // rounding converts + output f_alg_ex4_sticky; // part of eac control + output f_alg_ex4_int_fr; // f_pic + output f_alg_ex4_int_fi; // f_pic + + + parameter tiup = 1'b1; + parameter tidn = 1'b0; + + wire thold_0_b; + wire thold_0; + wire force_t; + wire sg_0; + + wire ex3_act; + + (* analysis_not_referenced="TRUE" *) // unused + wire [0:3] spare_unused; + //-------------------------------------- + wire [0:4] act_so; //SCAN + wire [0:4] act_si; //SCAN + wire [0:4] ex2_ctl_so; //SCAN + wire [0:4] ex2_ctl_si; //SCAN + wire [0:67] ex3_shd_so; //SCAN + wire [0:67] ex3_shd_si; + wire [0:24] ex3_shc_so; //SCAN + wire [0:24] ex3_shc_si; + wire [0:14] ex3_ctl_so; //SCAN + wire [0:14] ex3_ctl_si; //SCAN + wire [0:10] ex4_ctl_so; //SCAN + wire [0:10] ex4_ctl_si; //SCAN + //-------------------------------------- + wire ex2_from_integer; + wire ex3_from_integer; + wire ex2_to_integer; + wire ex2_sel_special; + wire ex2_sel_special_b; + wire ex3_sel_special_b; + wire ex2_sh_ovf; + wire ex2_sh_unf_x; + wire ex3_sh_unf_x; + wire ex2_sel_byp_nonflip; + wire ex2_sel_byp_nonflip_lze; + wire ex2_from_integer_neg; + wire ex2_integer_op; + wire ex2_to_integer_neg; + wire ex2_negate; + wire ex2_effsub_alg; + wire ex3_sh_unf; + wire ex3_sel_byp; + wire ex3_effsub_alg; + wire ex3_prd_sel_pos_hi; + wire ex3_prd_sel_neg_hi; + wire ex3_prd_sel_pos_lo; + wire ex3_prd_sel_neg_lo; + wire ex3_prd_sel_pos_lohi; + wire ex3_prd_sel_neg_lohi; + wire ex3_byp_sel_pos; + wire ex3_byp_sel_neg; + wire ex3_byp_sel_byp_pos; + wire ex3_byp_sel_byp_neg; + wire ex3_b_sign; + wire ex3_to_integer; + wire [0:67] ex2_sh_lvl2; + wire [0:67] ex3_sh_lvl2; + wire [0:67] ex3_sh_lvl2_b; + wire [6:9] ex3_bsha; + wire [0:4] ex3_sticky_en16_x; + wire ex3_xthrm_6_ns_b; + wire ex3_xthrm_7_ns_b; + wire ex3_xthrm_8_b; + wire ex3_xthrm_8a9_b; + wire ex3_xthrm_8o9_b; + wire ex3_xthrm7o8a9; + wire ex3_xthrm7o8; + wire ex3_xthrm7o8o9; + wire ex3_xthrm7a8a9; + wire ex3_xthrm_6_ns; + wire ex3_ge176_b; + wire ex3_ge160_b; + wire ex3_ge144_b; + wire ex3_ge128_b; + wire ex3_ge112_b; + wire ex2_bsha_6; + wire ex2_bsha_7; + wire ex2_bsha_8; + wire ex2_bsha_9; + wire ex3_bsha_pos; + wire [0:162] ex3_sh_lvl3; + wire [0:4] ex3_sticky_or16; + wire ex2_b_zero; + wire ex3_b_zero; + wire ex3_b_zero_b; + + wire ex2_dp; + + wire ex3_byp_nonflip_lze; + wire ex3_sel_byp_nonflip; + wire ex3_prod_zero; + wire ex3_sh_ovf_en; + wire ex3_sh_unf_en; + wire ex3_sh_unf_do; + wire ex3_sh_ovf; + wire ex3_integer_op; + wire ex3_negate; + wire ex3_unf_bz; + wire ex3_all1_x; + wire ex3_ovf_pz; + wire ex3_all1_y; + wire ex3_sel_special; + wire ex1_from_integer; + wire ex1_to_integer; + wire ex1_dp; + wire ex1_uns; + wire ex1_word; + wire ex2_uns; + wire ex2_word; + wire ex2_word_from; + wire ex3_word_from; + wire ex3_rnd_to_int; + wire ex2_sign_from; + wire [0:52] ex2_b_frac; + wire [1:13] ex2_b_expo; + wire ex2_b_sign; + wire ex2_bsha_neg; + wire ex3_bsha_neg; + + wire ex2_lvl1_shdcd000_b; + wire ex2_lvl1_shdcd001_b; + wire ex2_lvl1_shdcd002_b; + wire ex2_lvl1_shdcd003_b; + wire ex2_lvl2_shdcd000; + wire ex2_lvl2_shdcd004; + wire ex2_lvl2_shdcd008; + wire ex2_lvl2_shdcd012; + wire ex2_lvl3_shdcd000; + wire ex2_lvl3_shdcd016; + wire ex2_lvl3_shdcd032; + wire ex2_lvl3_shdcd048; + wire ex2_lvl3_shdcd064; + wire ex2_lvl3_shdcd080; + wire ex2_lvl3_shdcd096; + wire ex2_lvl3_shdcd112; + wire ex2_lvl3_shdcd128; + wire ex2_lvl3_shdcd144; + wire ex2_lvl3_shdcd160; + wire ex2_lvl3_shdcd176; + wire ex2_lvl3_shdcd192; // -64 + wire ex2_lvl3_shdcd208; // -48 + wire ex2_lvl3_shdcd224; // -32 + wire ex2_lvl3_shdcd240; // -16 + + wire ex3_lvl3_shdcd000; + wire ex3_lvl3_shdcd016; + wire ex3_lvl3_shdcd032; + wire ex3_lvl3_shdcd048; + wire ex3_lvl3_shdcd064; + wire ex3_lvl3_shdcd080; + wire ex3_lvl3_shdcd096; + wire ex3_lvl3_shdcd112; + wire ex3_lvl3_shdcd128; + wire ex3_lvl3_shdcd144; + wire ex3_lvl3_shdcd160; + wire ex3_lvl3_shdcd176; + wire ex3_lvl3_shdcd192; + wire ex3_lvl3_shdcd208; + wire ex3_lvl3_shdcd224; + wire ex3_lvl3_shdcd240; + + wire ex4_int_fr_nr1_b; + wire ex4_int_fr_nr2_b; + wire ex4_int_fr_ok_b; + wire ex4_int_fr; + wire ex4_sel_p1_0_b; + wire ex4_sel_p1_1_b; + wire ex4_sticky_math; + wire ex4_sticky_toint; + wire ex4_sticky_toint_nr; + wire ex4_sticky_toint_ok; + wire ex4_frmneg_o_toneg; + wire ex4_frmneg_o_topos; + wire ex4_lsb_toint_nr; + wire ex4_g_math; + wire ex4_g_toint; + wire ex4_g_toint_nr; + wire ex4_g_toint_ok; + wire ex3_frmneg; + wire ex3_toneg; + wire ex3_topos; + wire ex3_frmneg_o_toneg; + wire ex3_frmneg_o_topos; + wire ex3_toint_gate_x; + wire ex3_toint_gate_g; + wire ex3_toint_gt_nr_x; + wire ex3_toint_gt_nr_g; + wire ex3_toint_gt_ok_x; + wire ex3_toint_gt_ok_g; + wire ex3_math_gate_x; + wire ex3_math_gate_g; + wire ex3_sticky_eac_x; + wire ex3_sticky_math; + wire ex3_sticky_toint; + wire ex3_sticky_toint_nr; + wire ex3_sticky_toint_ok; + wire ex3_lsb_toint_nr; + wire ex3_g_math; + wire ex3_g_toint; + wire ex3_g_toint_nr; + wire ex3_g_toint_ok; + wire ex3_sh16_162; + wire ex3_sh16_163; + wire alg_ex3_d1clk; + wire alg_ex3_d2clk; + + wire [0:`NCLK_WIDTH-1] alg_ex3_lclk; + + wire [6:9] ex3_bsha_b; + wire ex3_bsha_neg_b; + wire ex3_sh_ovf_b; + wire ex3_sh_unf_x_b; + wire ex3_lvl3_shdcd000_b; + wire ex3_lvl3_shdcd016_b; + wire ex3_lvl3_shdcd032_b; + wire ex3_lvl3_shdcd048_b; + wire ex3_lvl3_shdcd064_b; + wire ex3_lvl3_shdcd080_b; + wire ex3_lvl3_shdcd096_b; + wire ex3_lvl3_shdcd112_b; + wire ex3_lvl3_shdcd128_b; + wire ex3_lvl3_shdcd144_b; + wire ex3_lvl3_shdcd160_b; + wire ex3_lvl3_shdcd176_b; + wire ex3_lvl3_shdcd192_b; + wire ex3_lvl3_shdcd208_b; + wire ex3_lvl3_shdcd224_b; + wire ex3_lvl3_shdcd240_b; + wire ex3_b_zero_l2_b; + wire ex3_prod_zero_b; + wire ex3_byp_nonflip_lze_b; + wire ex3_sel_byp_nonflip_b; + wire ex3_sh_unf_do_b; + wire ex3_sh_unf_en_b; + wire ex3_sh_ovf_en_b; + wire ex3_effsub_alg_b; + wire ex3_negate_b; + wire ex3_b_sign_b; + wire ex3_to_integer_b; + wire ex3_from_integer_b; + wire ex3_rnd_to_int_b; + wire ex3_integer_op_b; + wire ex3_word_from_b; + (* analysis_not_referenced="TRUE" *) // unused + wire unused; + + //==############################################################## + //# map block attributes + //==############################################################## + + assign unused = ex2_b_expo[1] | ex2_b_expo[2] | ex2_dp | ex3_lvl3_shdcd176; //latch output + // latch output + + assign ex2_b_frac[0:52] = f_byp_alg_ex2_b_frac[0:52]; //RENAME + assign ex2_b_sign = f_byp_alg_ex2_b_sign; //RENAME + assign ex2_b_expo[1:13] = f_byp_alg_ex2_b_expo[1:13]; //RENAME + + //==############################################################## + //# pervasive + //==############################################################## + + + tri_plat thold_reg_0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(flush), + .din(thold_1), + .q(thold_0) + ); + + + tri_plat sg_reg_0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(flush), + .din(sg_1), + .q(sg_0) + ); + + + tri_lcbor lcbor_0( + .clkoff_b(clkoff_b), + .thold(thold_0), + .sg(sg_0), + .act_dis(act_dis), + .force_t(force_t), + .thold_b(thold_0_b) + ); + + //==############################################################## + //# act + //==############################################################## + + + + tri_rlmreg_p #(.WIDTH(5), .NEEDS_SRESET(0)) act_lat( + .vd(vdd), + .gd(gnd), + .force_t(force_t), //i-- tidn, + .d_mode(tiup), //d_mode => d_mode ,--i-- tiup, + .delay_lclkr(delay_lclkr[2]), //i-- tidn, + .mpw1_b(mpw1_b[2]), //i-- tidn, + .mpw2_b(mpw2_b[0]), //i-- tidn, + .nclk(nclk), + .act(fpu_enable), + .thold_b(thold_0_b), + .sg(sg_0), + .scout(act_so), + .scin(act_si), + //----------------- + .din({ spare_unused[0], + spare_unused[1], + ex2_act, + spare_unused[2], + spare_unused[3]}), + //----------------- + .dout({ spare_unused[0], + spare_unused[1], + ex3_act, + spare_unused[2], + spare_unused[3]}) + ); + + + tri_lcbnd alg_ex3_lcb( + .delay_lclkr(delay_lclkr[2]), // tidn ,--in + .mpw1_b(mpw1_b[2]), // tidn ,--in + .mpw2_b(mpw2_b[0]), // tidn ,--in + .force_t(force_t), // tidn ,--in + .nclk(nclk), //in + .vd(vdd), //inout + .gd(gnd), //inout + .act(ex2_act), //in + .sg(sg_0), //in + .thold_b(thold_0_b), //in + .d1clk(alg_ex3_d1clk), //out + .d2clk(alg_ex3_d2clk), //out + .lclk(alg_ex3_lclk) //out + ); + + //==############################################################## + //# ex1 logic + //==############################################################## + + //#------------------------------------------------------------- + //# shift amount calculation :start with exponent difference + //#------------------------------------------------------------- + + //==############################################################## + //# ex2 latches (from ex1 logic) + //==############################################################## + + assign ex1_from_integer = (~f_dcd_ex1_from_integer_b); + assign ex1_to_integer = (~f_dcd_ex1_to_integer_b); + assign ex1_dp = (~f_dcd_ex1_sp); + assign ex1_word = (~f_dcd_ex1_word_b); + assign ex1_uns = (~f_dcd_ex1_uns_b); + + + tri_rlmreg_p #(.WIDTH(5), .NEEDS_SRESET(0)) ex2_ctl_lat( + .force_t(force_t), //tidn, + .d_mode(tiup), //d_mode => d_mode ,--tiup, + .delay_lclkr(delay_lclkr[1]), //tidn, + .mpw1_b(mpw1_b[1]), //tidn, + .mpw2_b(mpw2_b[0]), //tidn, + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + .act(ex1_act), + .scout(ex2_ctl_so), + .scin(ex2_ctl_si), + //--------------- + .din({ ex1_from_integer, + ex1_to_integer, + ex1_dp, + ex1_word, + ex1_uns}), + //--------------- + .dout({ex2_from_integer, + ex2_to_integer, + ex2_dp, + ex2_word, + ex2_uns}) + ); + + //==############################################################## + //# ex2 logic + //==############################################################## + + + fu_alg_add sha( + .vdd(vdd), + .gnd(gnd), + .f_byp_alg_ex2_b_expo(f_byp_alg_ex2_b_expo), //i-- + .f_byp_alg_ex2_a_expo(f_byp_alg_ex2_a_expo), //i-- + .f_byp_alg_ex2_c_expo(f_byp_alg_ex2_c_expo), //i-- + .ex2_sel_special_b(ex2_sel_special_b), //i-- + .ex2_bsha_6_o(ex2_bsha_6), //o-- + .ex2_bsha_7_o(ex2_bsha_7), //o-- + .ex2_bsha_8_o(ex2_bsha_8), //o-- + .ex2_bsha_9_o(ex2_bsha_9), //o-- + .ex2_bsha_neg_o(ex2_bsha_neg), //o-- + .ex2_sh_ovf(ex2_sh_ovf), //o-- + .ex2_sh_unf_x(ex2_sh_unf_x), //o-- + .ex2_lvl1_shdcd000_b(ex2_lvl1_shdcd000_b), //o-- + .ex2_lvl1_shdcd001_b(ex2_lvl1_shdcd001_b), //o-- + .ex2_lvl1_shdcd002_b(ex2_lvl1_shdcd002_b), //o-- + .ex2_lvl1_shdcd003_b(ex2_lvl1_shdcd003_b), //o-- + .ex2_lvl2_shdcd000(ex2_lvl2_shdcd000), //o-- + .ex2_lvl2_shdcd004(ex2_lvl2_shdcd004), //o-- + .ex2_lvl2_shdcd008(ex2_lvl2_shdcd008), //o-- + .ex2_lvl2_shdcd012(ex2_lvl2_shdcd012), //o-- + .ex2_lvl3_shdcd000(ex2_lvl3_shdcd000), //o-- + .ex2_lvl3_shdcd016(ex2_lvl3_shdcd016), //o-- + .ex2_lvl3_shdcd032(ex2_lvl3_shdcd032), //o-- + .ex2_lvl3_shdcd048(ex2_lvl3_shdcd048), //o-- + .ex2_lvl3_shdcd064(ex2_lvl3_shdcd064), //o-- + .ex2_lvl3_shdcd080(ex2_lvl3_shdcd080), //o-- + .ex2_lvl3_shdcd096(ex2_lvl3_shdcd096), //o-- + .ex2_lvl3_shdcd112(ex2_lvl3_shdcd112), //o-- + .ex2_lvl3_shdcd128(ex2_lvl3_shdcd128), //o-- + .ex2_lvl3_shdcd144(ex2_lvl3_shdcd144), //o-- + .ex2_lvl3_shdcd160(ex2_lvl3_shdcd160), //o-- + .ex2_lvl3_shdcd176(ex2_lvl3_shdcd176), //o-- + .ex2_lvl3_shdcd192(ex2_lvl3_shdcd192), //o-- + .ex2_lvl3_shdcd208(ex2_lvl3_shdcd208), //o-- + .ex2_lvl3_shdcd224(ex2_lvl3_shdcd224), //o-- + .ex2_lvl3_shdcd240(ex2_lvl3_shdcd240) //o-- + ); + + assign ex2_sel_special = ex2_from_integer; + assign ex2_sel_special_b = (~ex2_from_integer); + + //#------------------------------------------------- + //# determine bypass selects, operand flip + //#------------------------------------------------- + + ////---------------------------------- + //// ex2 + ////---------------------------------- + + // nan pass + assign ex2_sel_byp_nonflip_lze = (f_fmt_ex2_pass_sel) | (f_pic_ex2_sh_ovf_do); // fsel, fpscr, fmr, + + // <<<< move all this stuff to ex3 + assign ex2_sel_byp_nonflip = (f_pic_ex2_frsp_ue1) | (f_fmt_ex2_pass_sel) | (f_pic_ex2_sh_ovf_do); // nan pass + // fsel, fpscr, fmr, + + assign ex2_integer_op = ex2_from_integer | (ex2_to_integer & (~f_pic_ex2_rnd_to_int)); + + // the negate for from_integer should only catch the last 64 bits (because it is not sign extended) + + assign f_alg_ex2_sign_frmw = ex2_b_frac[21]; // output (for sign logic) + + assign ex2_sign_from = (ex2_from_integer & ex2_word & ex2_b_frac[21]) | (ex2_from_integer & (~ex2_word) & ex2_b_sign); // 32 from left 52 - 31 = 21 + + assign ex2_from_integer_neg = ex2_from_integer & ex2_sign_from & (~ex2_uns); + + assign ex2_word_from = ex2_word & ex2_from_integer; + + assign ex2_to_integer_neg = ex2_to_integer & ex2_b_sign & (~f_pic_ex2_rnd_to_int); + + assign ex2_negate = f_pic_ex2_effsub_raw | ex2_from_integer_neg | ex2_to_integer_neg; // subtract op + + assign ex2_effsub_alg = f_pic_ex2_effsub_raw & (~f_fmt_ex2_pass_sel); + + assign ex2_b_zero = f_fmt_ex2_b_zero; + + // for sh_unf/b_zero effadd: alg_res = 00...00 (turn off all selects) + // for sh_unf/b_zero effsub: alg_res = 11...11 (turn on pos/neg selects) + // + // 0:52 53:54 55:98 99:163 + // to_int 0 0 0 ssssss + // from_int 0 0 0 ssssss + // bypass{nan,fmr} d 0 ? ?????? + // sh_ov + // sh_unf + // effadd + // effsub + + //#--------------------------------------------------------------- + //# first 2 levels of shifting (1) 0/1/2/3 (2) 0/4/8/12 + //#--------------------------------------------------------------- + + + fu_alg_sh4 sh4( + .ex2_lvl1_shdcd000_b(ex2_lvl1_shdcd000_b), //i-- + .ex2_lvl1_shdcd001_b(ex2_lvl1_shdcd001_b), //i-- + .ex2_lvl1_shdcd002_b(ex2_lvl1_shdcd002_b), //i-- + .ex2_lvl1_shdcd003_b(ex2_lvl1_shdcd003_b), //i-- + .ex2_lvl2_shdcd000(ex2_lvl2_shdcd000), //i-- + .ex2_lvl2_shdcd004(ex2_lvl2_shdcd004), //i-- + .ex2_lvl2_shdcd008(ex2_lvl2_shdcd008), //i-- + .ex2_lvl2_shdcd012(ex2_lvl2_shdcd012), //i-- + .ex2_sel_special(ex2_sel_special), //i-- + .ex2_b_sign(ex2_b_sign), //i-- + .ex2_b_expo(ex2_b_expo[3:13]), //i-- + .ex2_b_frac(ex2_b_frac[0:52]), //i-- + .ex2_sh_lvl2(ex2_sh_lvl2[0:67]) //o-- + ); + + //==############################################################## + //# ex3 latches (from ex2 logic) + //==############################################################## + + + tri_inv_nlats #(.WIDTH(68), .NEEDS_SRESET(0)) ex3_shd_lat( + .vd(vdd), + .gd(gnd), + .lclk(alg_ex3_lclk), // lclk.clk + .d1clk(alg_ex3_d1clk), + .d2clk(alg_ex3_d2clk), + .scanin(ex3_shd_si), + .scanout(ex3_shd_so), + .d(ex2_sh_lvl2[0:67]), + .qb(ex3_sh_lvl2_b[0:67]) + ); + + assign ex3_sh_lvl2[0:67] = (~ex3_sh_lvl2_b[0:67]); + + + tri_inv_nlats #(.WIDTH(25), .NEEDS_SRESET(0)) ex3_shc_lat( + .vd(vdd), + .gd(gnd), + .lclk(alg_ex3_lclk), // lclk.clk + .d1clk(alg_ex3_d1clk), + .d2clk(alg_ex3_d2clk), + .scanin(ex3_shc_si), + .scanout(ex3_shc_so), + //----------------- + .d({ ex2_bsha_neg, + ex2_sh_ovf, + ex2_sh_unf_x, + ex2_sel_special, + ex2_sel_special_b, + ex2_bsha_6, + ex2_bsha_7, + ex2_bsha_8, + ex2_bsha_9, + ex2_lvl3_shdcd000, + ex2_lvl3_shdcd016, + ex2_lvl3_shdcd032, + ex2_lvl3_shdcd048, + ex2_lvl3_shdcd064, + ex2_lvl3_shdcd080, + ex2_lvl3_shdcd096, + ex2_lvl3_shdcd112, + ex2_lvl3_shdcd128, + ex2_lvl3_shdcd144, + ex2_lvl3_shdcd160, + ex2_lvl3_shdcd176, + ex2_lvl3_shdcd192, + ex2_lvl3_shdcd208, + ex2_lvl3_shdcd224, + ex2_lvl3_shdcd240}), + //-------------------- + .qb({ex3_bsha_neg_b, + ex3_sh_ovf_b, + ex3_sh_unf_x_b, + ex3_sel_special_b, + ex3_sel_special, + ex3_bsha_b[6], + ex3_bsha_b[7], + ex3_bsha_b[8], + ex3_bsha_b[9], + ex3_lvl3_shdcd000_b, + ex3_lvl3_shdcd016_b, + ex3_lvl3_shdcd032_b, + ex3_lvl3_shdcd048_b, + ex3_lvl3_shdcd064_b, + ex3_lvl3_shdcd080_b, + ex3_lvl3_shdcd096_b, + ex3_lvl3_shdcd112_b, + ex3_lvl3_shdcd128_b, + ex3_lvl3_shdcd144_b, + ex3_lvl3_shdcd160_b, + ex3_lvl3_shdcd176_b, + ex3_lvl3_shdcd192_b, + ex3_lvl3_shdcd208_b, + ex3_lvl3_shdcd224_b, + ex3_lvl3_shdcd240_b}) + ); + + assign ex3_bsha_neg = (~ex3_bsha_neg_b); + assign ex3_sh_ovf = (~ex3_sh_ovf_b); + assign ex3_sh_unf_x = (~ex3_sh_unf_x_b); + assign ex3_bsha[6] = (~ex3_bsha_b[6]); + assign ex3_bsha[7] = (~ex3_bsha_b[7]); + assign ex3_bsha[8] = (~ex3_bsha_b[8]); + assign ex3_bsha[9] = (~ex3_bsha_b[9]); + assign ex3_lvl3_shdcd000 = (~ex3_lvl3_shdcd000_b); + assign ex3_lvl3_shdcd016 = (~ex3_lvl3_shdcd016_b); + assign ex3_lvl3_shdcd032 = (~ex3_lvl3_shdcd032_b); + assign ex3_lvl3_shdcd048 = (~ex3_lvl3_shdcd048_b); + assign ex3_lvl3_shdcd064 = (~ex3_lvl3_shdcd064_b); + assign ex3_lvl3_shdcd080 = (~ex3_lvl3_shdcd080_b); + assign ex3_lvl3_shdcd096 = (~ex3_lvl3_shdcd096_b); + assign ex3_lvl3_shdcd112 = (~ex3_lvl3_shdcd112_b); + assign ex3_lvl3_shdcd128 = (~ex3_lvl3_shdcd128_b); + assign ex3_lvl3_shdcd144 = (~ex3_lvl3_shdcd144_b); + assign ex3_lvl3_shdcd160 = (~ex3_lvl3_shdcd160_b); + assign ex3_lvl3_shdcd176 = (~ex3_lvl3_shdcd176_b); + assign ex3_lvl3_shdcd192 = (~ex3_lvl3_shdcd192_b); + assign ex3_lvl3_shdcd208 = (~ex3_lvl3_shdcd208_b); + assign ex3_lvl3_shdcd224 = (~ex3_lvl3_shdcd224_b); + assign ex3_lvl3_shdcd240 = (~ex3_lvl3_shdcd240_b); + + + tri_inv_nlats #(.WIDTH(15), .NEEDS_SRESET(0)) ex3_ctl_lat( + .vd(vdd), + .gd(gnd), + .lclk(alg_ex3_lclk), // lclk.clk + .d1clk(alg_ex3_d1clk), + .d2clk(alg_ex3_d2clk), + .scanin(ex3_ctl_si), + .scanout(ex3_ctl_so), + //----------------- + .d({ ex2_b_zero, + f_fmt_ex2_prod_zero, + ex2_sel_byp_nonflip_lze, + ex2_sel_byp_nonflip, + f_pic_ex2_sh_unf_do, + f_pic_ex2_sh_unf_ig_b, + f_pic_ex2_sh_ovf_ig_b, + ex2_effsub_alg, + ex2_negate, + ex2_b_sign, + ex2_to_integer, + ex2_from_integer, + f_pic_ex2_rnd_to_int, + ex2_integer_op, + ex2_word_from}), + //----------------- + .qb({ ex3_b_zero_l2_b, + ex3_prod_zero_b, + ex3_byp_nonflip_lze_b, + ex3_sel_byp_nonflip_b, + ex3_sh_unf_do_b, + ex3_sh_unf_en_b, + ex3_sh_ovf_en_b, + ex3_effsub_alg_b, + ex3_negate_b, + ex3_b_sign_b, + ex3_to_integer_b, + ex3_from_integer_b, + ex3_rnd_to_int_b, + ex3_integer_op_b, + ex3_word_from_b}) + ); + + assign ex3_b_zero = (~ex3_b_zero_l2_b); + assign ex3_prod_zero = (~ex3_prod_zero_b); + assign ex3_byp_nonflip_lze = (~ex3_byp_nonflip_lze_b); + assign ex3_sel_byp_nonflip = (~ex3_sel_byp_nonflip_b); + assign ex3_sh_unf_do = (~ex3_sh_unf_do_b); + assign ex3_sh_unf_en = (~ex3_sh_unf_en_b); + assign ex3_sh_ovf_en = (~ex3_sh_ovf_en_b); + assign ex3_effsub_alg = (~ex3_effsub_alg_b); + assign ex3_negate = (~ex3_negate_b); + assign ex3_b_sign = (~ex3_b_sign_b); + assign ex3_to_integer = (~ex3_to_integer_b); + assign ex3_from_integer = (~ex3_from_integer_b); + assign ex3_rnd_to_int = (~ex3_rnd_to_int_b); + assign ex3_integer_op = (~ex3_integer_op_b); + assign ex3_word_from = (~ex3_word_from_b); + + //$$ sticky enable for 16 bit groups ------------------------ + //$$ + //$$ ex2_sticky_en16_x(0) <= + //$$ (ex2_lvl3_shdcd176 ) or -- == 176 + //$$ (ex2_bsha( 6) and ex2_bsha( 7) ) or -- >= 176 + //$$ (ex2_bsha( 6) and ex2_bsha( 8) and ex2_bsha( 9) ) ; -- >= 176 + //$$ ex2_sticky_en16_x(1) <= ex2_sticky_en16_x(0) or ex2_lvl3_shdcd160_x ; + //$$ ex2_sticky_en16_x(2) <= ex2_sticky_en16_x(1) or ex2_lvl3_shdcd144_x ; + //$$ ex2_sticky_en16_x(3) <= ex2_sticky_en16_x(2) or ex2_lvl3_shdcd128_x ; + //$$ ex2_sticky_en16_x(4) <= ex2_sticky_en16_x(3) or ex2_lvl3_shdcd112_x ; + + //------------------------------ + // Sticky Bit Thermometer + //------------------------------ + // bhsa(6789) + // 176 1011 GE_176: 6 * (7 | (8*9) ) + // 160 1010 GE_160: 6 * (7 | (8) ) + // 144 1001 GE_144 6 * (7 | (8|9) ) + // 128 1000 GE_128: 6 + // 112 0111 GE_112: 6 | (7 * (8*9) ) + + assign ex3_xthrm_6_ns_b = (~(ex3_bsha[6] & ex3_sel_special_b)); + assign ex3_xthrm_7_ns_b = (~(ex3_bsha[7] & ex3_sel_special_b)); + assign ex3_xthrm_8_b = (~(ex3_bsha[8])); + assign ex3_xthrm_8a9_b = (~(ex3_bsha[8] & ex3_bsha[9])); + assign ex3_xthrm_8o9_b = (~(ex3_bsha[8] | ex3_bsha[9])); + + assign ex3_xthrm7o8a9 = (~(ex3_xthrm_7_ns_b & ex3_xthrm_8a9_b)); + assign ex3_xthrm7o8 = (~(ex3_xthrm_7_ns_b & ex3_xthrm_8_b)); + assign ex3_xthrm7o8o9 = (~(ex3_xthrm_7_ns_b & ex3_xthrm_8o9_b)); + assign ex3_xthrm7a8a9 = (~(ex3_xthrm_7_ns_b | ex3_xthrm_8a9_b)); + assign ex3_xthrm_6_ns = (~(ex3_xthrm_6_ns_b)); + + assign ex3_ge176_b = (~(ex3_xthrm_6_ns & ex3_xthrm7o8a9)); + assign ex3_ge160_b = (~(ex3_xthrm_6_ns & ex3_xthrm7o8)); + assign ex3_ge144_b = (~(ex3_xthrm_6_ns & ex3_xthrm7o8o9)); + assign ex3_ge128_b = (~(ex3_xthrm_6_ns)); + assign ex3_ge112_b = (~(ex3_xthrm_6_ns | ex3_xthrm7a8a9)); + + assign ex3_sticky_en16_x[0] = (~ex3_ge176_b); + assign ex3_sticky_en16_x[1] = (~ex3_ge160_b); + assign ex3_sticky_en16_x[2] = (~ex3_ge144_b); + assign ex3_sticky_en16_x[3] = (~ex3_ge128_b); + assign ex3_sticky_en16_x[4] = (~ex3_ge112_b); + + assign ex3_b_zero_b = (~ex3_b_zero); + + assign f_alg_ex3_byp_nonflip = ex3_byp_nonflip_lze; + assign f_alg_ex3_sel_byp = ex3_sel_byp; //output-- all eac selects off + assign f_alg_ex3_effsub_eac_b = (~ex3_effsub_alg); //output-- includes cancelations + assign f_alg_ex3_prod_z = ex3_prod_zero; //output + assign f_alg_ex3_sh_unf = ex3_sh_unf; //output--f_pic-- + assign f_alg_ex3_sh_ovf = ex3_ovf_pz; //output--f_pic-- + + //==############################################################## + //# ex3 logic + //==############################################################## + + //#------------------------------------------------- + //# start sticky (passed 163 ... passed 162 for math, but need guard for fcti rounding) + //#------------------------------------------------- + + + fu_alg_or16 or16( + .ex3_sh_lvl2(ex3_sh_lvl2[0:67]), //i-- + .ex3_sticky_or16(ex3_sticky_or16[0:4]) //o-- + ); + + //#------------------------------------------------- + //# finish shifting + //#------------------------------------------------- + // this looks more like a 53:1 mux than a shifter to shrink it, and lower load on selects + // real implementation should be nand/nand/nor ... ?? integrate nor into latch ?? + + + fu_alg_sh16 sh16( + .ex3_lvl3_shdcd000(ex3_lvl3_shdcd000), //i-- + .ex3_lvl3_shdcd016(ex3_lvl3_shdcd016), //i-- + .ex3_lvl3_shdcd032(ex3_lvl3_shdcd032), //i-- + .ex3_lvl3_shdcd048(ex3_lvl3_shdcd048), //i-- + .ex3_lvl3_shdcd064(ex3_lvl3_shdcd064), //i-- + .ex3_lvl3_shdcd080(ex3_lvl3_shdcd080), //i-- + .ex3_lvl3_shdcd096(ex3_lvl3_shdcd096), //i-- + .ex3_lvl3_shdcd112(ex3_lvl3_shdcd112), //i-- + .ex3_lvl3_shdcd128(ex3_lvl3_shdcd128), //i-- + .ex3_lvl3_shdcd144(ex3_lvl3_shdcd144), //i-- + .ex3_lvl3_shdcd160(ex3_lvl3_shdcd160), //i-- + .ex3_lvl3_shdcd192(ex3_lvl3_shdcd192), //i-- + .ex3_lvl3_shdcd208(ex3_lvl3_shdcd208), //i-- + .ex3_lvl3_shdcd224(ex3_lvl3_shdcd224), //i-- + .ex3_lvl3_shdcd240(ex3_lvl3_shdcd240), //i-- + .ex3_sel_special(ex3_sel_special), //i-- + .ex3_sh_lvl2(ex3_sh_lvl2[0:67]), //i-- [0:63] is also data for from integer + .ex3_sh16_162(ex3_sh16_162), //o-- + .ex3_sh16_163(ex3_sh16_163), //o-- + .ex3_sh_lvl3(ex3_sh_lvl3[0:162]) //o-- + ); + + //==--------------------------------------------- + //== finish bypass controls + //==---------------------------------------------- + + assign ex3_ovf_pz = ex3_prod_zero | (ex3_sh_ovf & ex3_sh_ovf_en & (~ex3_b_zero)); + assign ex3_sel_byp = ex3_sel_byp_nonflip | ex3_ovf_pz; + assign ex3_all1_y = ex3_negate & ex3_ovf_pz; + assign ex3_all1_x = ex3_negate & ex3_unf_bz; + assign ex3_sh_unf = ex3_sh_unf_do | (ex3_sh_unf_en & ex3_sh_unf_x & (~ex3_prod_zero)); + assign ex3_unf_bz = ex3_b_zero | ex3_sh_unf; + + assign ex3_byp_sel_byp_pos = (ex3_sel_byp_nonflip) | (ex3_ovf_pz & (~ex3_integer_op) & (~ex3_negate) & (~ex3_unf_bz)) | (ex3_ovf_pz & (~ex3_integer_op) & ex3_all1_x); + + assign ex3_byp_sel_byp_neg = (~ex3_sel_byp_nonflip) & ex3_ovf_pz & (~ex3_integer_op) & ex3_negate; + + assign ex3_byp_sel_pos = ((~ex3_sel_byp) & (~ex3_integer_op) & (~ex3_negate) & (~ex3_unf_bz)) | ((~ex3_sel_byp) & (~ex3_integer_op) & ex3_all1_x); + assign ex3_byp_sel_neg = ((~ex3_sel_byp) & (~ex3_integer_op) & ex3_negate); + + assign ex3_prd_sel_pos_hi = ex3_prd_sel_pos_lo & (~ex3_integer_op); + assign ex3_prd_sel_neg_hi = ex3_prd_sel_neg_lo & (~ex3_integer_op); + + assign ex3_prd_sel_pos_lohi = ex3_prd_sel_pos_lo & (~ex3_word_from); + assign ex3_prd_sel_neg_lohi = ex3_prd_sel_neg_lo & (~ex3_word_from); + + assign ex3_prd_sel_pos_lo = ((~ex3_sel_byp_nonflip) & (~ex3_ovf_pz) & (~ex3_unf_bz) & (~ex3_negate)) | ((~ex3_sel_byp_nonflip) & ex3_all1_x) | ((~ex3_sel_byp_nonflip) & ex3_all1_y); + assign ex3_prd_sel_neg_lo = ((~ex3_sel_byp_nonflip) & ex3_negate); + + //#------------------------------------------------- + //# bypass mux & operand flip + //#------------------------------------------------- + //# integer operation positions + //# 32 32 + //# 99:130 131:162 + + + fu_alg_bypmux bymx( + .ex3_byp_sel_byp_neg(ex3_byp_sel_byp_neg), //i-- + .ex3_byp_sel_byp_pos(ex3_byp_sel_byp_pos), //i-- + .ex3_byp_sel_neg(ex3_byp_sel_neg), //i-- + .ex3_byp_sel_pos(ex3_byp_sel_pos), //i-- + .ex3_prd_sel_neg_hi(ex3_prd_sel_neg_hi), //i-- + .ex3_prd_sel_neg_lo(ex3_prd_sel_neg_lo), //i-- + .ex3_prd_sel_neg_lohi(ex3_prd_sel_neg_lohi), //i-- + .ex3_prd_sel_pos_hi(ex3_prd_sel_pos_hi), //i-- + .ex3_prd_sel_pos_lo(ex3_prd_sel_pos_lo), //i-- + .ex3_prd_sel_pos_lohi(ex3_prd_sel_pos_lohi), //i-- + .ex3_sh_lvl3(ex3_sh_lvl3[0:162]), //i-- + .f_fmt_ex3_pass_frac(f_fmt_ex3_pass_frac[0:52]), //i-- + .f_alg_ex3_res(f_alg_ex3_res[0:162]) //o-- + ); + + //#------------------------------------------------- + //# finish sticky + //#------------------------------------------------- + + assign ex3_frmneg = ex3_from_integer & ex3_negate; //need +1 as part of negate + assign ex3_toneg = (ex3_to_integer & (~ex3_rnd_to_int) & ex3_b_sign); //reverse rounding for toint/neg + assign ex3_topos = (ex3_to_integer & (~ex3_rnd_to_int) & (~ex3_b_sign)) | ex3_rnd_to_int; + assign ex3_frmneg_o_toneg = ex3_frmneg | ex3_toneg; + assign ex3_frmneg_o_topos = ex3_frmneg | ex3_topos; + + assign ex3_math_gate_x = (~ex3_sel_byp_nonflip) & ex3_b_zero_b & (~ex3_ovf_pz); + assign ex3_toint_gate_x = ex3_to_integer & ex3_b_zero_b; + assign ex3_toint_gt_nr_x = ex3_to_integer & ex3_b_zero_b & f_pic_ex3_rnd_nr; + assign ex3_toint_gt_ok_x = ex3_to_integer & ex3_b_zero_b & f_pic_ex3_rnd_inf_ok; + + assign ex3_math_gate_g = (~ex3_sel_byp_nonflip) & (~ex3_ovf_pz) & ex3_b_zero_b & (ex3_prd_sel_pos_lo | ex3_prd_sel_neg_lo); + assign ex3_toint_gate_g = ex3_to_integer & (~ex3_ovf_pz) & (~ex3_sh_unf) & ex3_b_zero_b; + assign ex3_toint_gt_nr_g = ex3_to_integer & (~ex3_ovf_pz) & (~ex3_sh_unf) & ex3_b_zero_b & f_pic_ex3_rnd_nr; + assign ex3_toint_gt_ok_g = ex3_to_integer & (~ex3_ovf_pz) & (~ex3_sh_unf) & ex3_b_zero_b & f_pic_ex3_rnd_inf_ok; + + assign ex3_bsha_pos = (~ex3_bsha_neg); + + assign ex3_sticky_eac_x = ((ex3_sh_unf | ex3_sticky_en16_x[0]) & ex3_sticky_or16[0] & ex3_bsha_pos) | ((ex3_sh_unf | ex3_sticky_en16_x[1]) & ex3_sticky_or16[1] & ex3_bsha_pos) | ((ex3_sh_unf | ex3_sticky_en16_x[2]) & ex3_sticky_or16[2] & ex3_bsha_pos) | ((ex3_sh_unf | ex3_sticky_en16_x[3]) & ex3_sticky_or16[3] & ex3_bsha_pos) | ((ex3_sh_unf | ex3_sticky_en16_x[4]) & ex3_sticky_or16[4] & ex3_bsha_pos); // shift underflow enables all sticky + + assign ex3_sticky_math = ex3_sticky_eac_x & ex3_math_gate_x; + assign ex3_sticky_toint = ex3_sticky_eac_x & ex3_toint_gate_x; + assign ex3_sticky_toint_nr = ex3_sticky_eac_x & ex3_toint_gt_nr_x; + assign ex3_sticky_toint_ok = ex3_sticky_eac_x & ex3_toint_gt_ok_x; + + // round-to-int goes up if guard is ON (this fakes it out) + assign ex3_lsb_toint_nr = (ex3_sh16_162 | ex3_rnd_to_int) & ex3_toint_gt_nr_g; + + assign ex3_g_math = ex3_sh16_163 & ex3_math_gate_g; + assign ex3_g_toint = ex3_sh16_163 & ex3_toint_gate_g; + assign ex3_g_toint_nr = ex3_sh16_163 & ex3_toint_gt_nr_g; + assign ex3_g_toint_ok = ex3_sh16_163 & ex3_toint_gt_ok_g; + + //==############################################################## + //# ex4 latches (from ex3 logic) + //==############################################################## + + + tri_rlmreg_p #(.WIDTH(11), .NEEDS_SRESET(0)) ex4_ctl_lat( + .force_t(force_t), //tidn, + .d_mode(tiup), //d_mode => d_mode ,--tiup, + .delay_lclkr(delay_lclkr[3]), //tidn, + .mpw1_b(mpw1_b[3]), //tidn, + .mpw2_b(mpw2_b[0]), //tidn, + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + .act(ex3_act), + .scout(ex4_ctl_so), + .scin(ex4_ctl_si), + //--------------- + .din({ ex3_sticky_math, + ex3_sticky_toint, + ex3_sticky_toint_nr, + ex3_sticky_toint_ok, + ex3_frmneg_o_toneg, + ex3_frmneg_o_topos, + ex3_lsb_toint_nr, + ex3_g_math, + ex3_g_toint, + ex3_g_toint_nr, + ex3_g_toint_ok}), + //-------------- + .dout({ ex4_sticky_math, + ex4_sticky_toint, + ex4_sticky_toint_nr, + ex4_sticky_toint_ok, + ex4_frmneg_o_toneg, + ex4_frmneg_o_topos, + ex4_lsb_toint_nr, + ex4_g_math, + ex4_g_toint, + ex4_g_toint_nr, + ex4_g_toint_ok}) + ); + + //==############################################################## + //== ex4 logic + //==############################################################## + + assign f_alg_ex4_sticky = ex4_sticky_math | ex4_g_math; //output-- + assign f_alg_ex4_int_fi = ex4_sticky_toint | ex4_g_toint; //outpt-- + + assign ex4_int_fr_nr1_b = (~(ex4_g_toint_nr & ex4_sticky_toint_nr)); + assign ex4_int_fr_nr2_b = (~(ex4_g_toint_nr & ex4_lsb_toint_nr)); + assign ex4_int_fr_ok_b = (~(ex4_g_toint_ok | ex4_sticky_toint_ok)); + assign ex4_int_fr = (~(ex4_int_fr_nr1_b & ex4_int_fr_nr2_b & ex4_int_fr_ok_b)); + assign f_alg_ex4_int_fr = ex4_int_fr; //output-- f_pic + + assign ex4_sel_p1_0_b = (~((~ex4_int_fr) & ex4_frmneg_o_toneg)); + assign ex4_sel_p1_1_b = (~(ex4_int_fr & ex4_frmneg_o_topos)); + assign f_alg_ex4_frc_sel_p1 = (~(ex4_sel_p1_0_b & ex4_sel_p1_1_b)); //output-- rounding converts + + //==############################################################## + //# scan string + //==############################################################## + + assign ex2_ctl_si[0:4] = {ex2_ctl_so[1:4], f_alg_si}; //SCAN + assign ex3_shd_si[0:67] = {ex3_shd_so[1:67], ex2_ctl_so[0]}; //SCAN + assign ex3_shc_si[0:24] = {ex3_shc_so[1:24], ex3_shd_so[0]}; //SCAN + assign ex3_ctl_si[0:14] = {ex3_ctl_so[1:14], ex3_shc_so[0]}; //SCAN + assign ex4_ctl_si[0:10] = {ex4_ctl_so[1:10], ex3_ctl_so[0]}; //SCAN + assign act_si[0:4] = {act_so[1:4], ex4_ctl_so[0]}; //SCAN + assign f_alg_so = act_so[0]; //SCAN + +endmodule diff --git a/dev/verilog/work/fu_alg_add.v b/dev/verilog/work/fu_alg_add.v new file mode 100755 index 0000000..b94770a --- /dev/null +++ b/dev/verilog/work/fu_alg_add.v @@ -0,0 +1,744 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + + `include "tri_a2o.vh" + +module fu_alg_add( + vdd, + gnd, + f_byp_alg_ex2_b_expo, + f_byp_alg_ex2_a_expo, + f_byp_alg_ex2_c_expo, + ex2_sel_special_b, + ex2_bsha_6_o, + ex2_bsha_7_o, + ex2_bsha_8_o, + ex2_bsha_9_o, + ex2_bsha_neg_o, + ex2_sh_ovf, + ex2_sh_unf_x, + ex2_lvl1_shdcd000_b, + ex2_lvl1_shdcd001_b, + ex2_lvl1_shdcd002_b, + ex2_lvl1_shdcd003_b, + ex2_lvl2_shdcd000, + ex2_lvl2_shdcd004, + ex2_lvl2_shdcd008, + ex2_lvl2_shdcd012, + ex2_lvl3_shdcd000, + ex2_lvl3_shdcd016, + ex2_lvl3_shdcd032, + ex2_lvl3_shdcd048, + ex2_lvl3_shdcd064, + ex2_lvl3_shdcd080, + ex2_lvl3_shdcd096, + ex2_lvl3_shdcd112, + ex2_lvl3_shdcd128, + ex2_lvl3_shdcd144, + ex2_lvl3_shdcd160, + ex2_lvl3_shdcd176, + ex2_lvl3_shdcd192, + ex2_lvl3_shdcd208, + ex2_lvl3_shdcd224, + ex2_lvl3_shdcd240 +); + inout vdd; + inout gnd; + input [1:13] f_byp_alg_ex2_b_expo; + input [1:13] f_byp_alg_ex2_a_expo; + input [1:13] f_byp_alg_ex2_c_expo; + + input ex2_sel_special_b; + + output ex2_bsha_6_o; + output ex2_bsha_7_o; + output ex2_bsha_8_o; + output ex2_bsha_9_o; + + output ex2_bsha_neg_o; + output ex2_sh_ovf; + output ex2_sh_unf_x; + + output ex2_lvl1_shdcd000_b; + output ex2_lvl1_shdcd001_b; + output ex2_lvl1_shdcd002_b; + output ex2_lvl1_shdcd003_b; + + output ex2_lvl2_shdcd000; + output ex2_lvl2_shdcd004; + output ex2_lvl2_shdcd008; + output ex2_lvl2_shdcd012; + + output ex2_lvl3_shdcd000; // 0000 +000 + output ex2_lvl3_shdcd016; // 0001 +016 + output ex2_lvl3_shdcd032; // 0010 +032 + output ex2_lvl3_shdcd048; // 0011 +048 + output ex2_lvl3_shdcd064; // 0100 +064 + output ex2_lvl3_shdcd080; // 0101 +080 + output ex2_lvl3_shdcd096; // 0110 +096 + output ex2_lvl3_shdcd112; // 0111 +112 + output ex2_lvl3_shdcd128; // 1000 +128 + output ex2_lvl3_shdcd144; // 1001 +144 + output ex2_lvl3_shdcd160; // 1010 +160 + output ex2_lvl3_shdcd176; // 1011 + output ex2_lvl3_shdcd192; // 1100 -064 + output ex2_lvl3_shdcd208; // 1101 -048 + output ex2_lvl3_shdcd224; // 1110 -032 + output ex2_lvl3_shdcd240; // 1111 -016 + //----------------------------------------------------------------- + + // ENTITY + + parameter tiup = 1'b1; + parameter tidn = 1'b0; + wire [2:14] ex2_bsha_sim_c; + wire [1:13] ex2_bsha_sim_p; + wire [2:13] ex2_bsha_sim_g; + wire [1:13] ex2_bsha_sim; + + wire [1:13] ex2_b_expo_b; + wire [2:13] ex2_a_expo_b; + wire [2:13] ex2_c_expo_b; + wire ex2_bsha_neg; + wire ex2_sh_ovf_b; + wire [1:13] ex2_alg_sx; + + (* analysis_not_referenced="<0:0>TRUE" *) + wire [0:12] ex2_alg_cx; + wire [1:12] ex2_alg_add_p; + wire [2:12] ex2_alg_add_g_b; + wire [2:11] ex2_alg_add_t_b; + + wire ex2_bsha_6_b; + wire ex2_bsha_7_b; + wire ex2_bsha_8_b; + wire ex2_bsha_9_b; + wire ex2_67_dcd00_b; + wire ex2_67_dcd01_b; + wire ex2_67_dcd10_b; + wire ex2_67_dcd11_b; + wire ex2_89_dcd00_b; + wire ex2_89_dcd01_b; + wire ex2_89_dcd10_b; + wire ex2_89_dcd11_b; + + wire ex2_lv2_0pg0_b; + wire ex2_lv2_0pg1_b; + wire ex2_lv2_0pk0_b; + wire ex2_lv2_0pk1_b; + wire ex2_lv2_0pp0_b; + wire ex2_lv2_0pp1_b; + wire ex2_lv2_1pg0_b; + wire ex2_lv2_1pg1_b; + wire ex2_lv2_1pk0_b; + wire ex2_lv2_1pk1_b; + wire ex2_lv2_1pp0_b; + wire ex2_lv2_1pp1_b; + wire ex2_lv2_shdcd000; + wire ex2_lv2_shdcd004; + wire ex2_lv2_shdcd008; + wire ex2_lv2_shdcd012; + wire ex2_lvl2_shdcd000_b; + wire ex2_lvl2_shdcd004_b; + wire ex2_lvl2_shdcd008_b; + wire ex2_lvl2_shdcd012_b; + + wire [7:10] ex2_alg_add_c_b; + wire ex2_g02_12; + wire ex2_g02_12_b; + wire ex2_bsha_13_b; + wire ex2_bsha_13; + wire ex2_bsha_12_b; + wire ex2_bsha_12; + wire ex2_lv2_ci11n_en_b; + wire ex2_lv2_ci11p_en_b; + wire ex2_lv2_ci11n_en; + wire ex2_lv2_ci11p_en; + wire ex2_g02_10; + wire ex2_t02_10; + wire ex2_g04_10_b; + wire ex2_lv2_g11_x; + wire ex2_lv2_g11_b; + wire ex2_lv2_g11; + wire ex2_lv2_k11_b; + wire ex2_lv2_k11; + wire ex2_lv2_p11_b; + wire ex2_lv2_p11; + wire ex2_lv2_p10_b; + wire ex2_lv2_p10; + wire ex2_g04_10; + wire ex2_g02_6; + wire ex2_g02_7; + wire ex2_g02_8; + wire ex2_g02_9; + wire ex2_t02_6; + wire ex2_t02_7; + wire ex2_t02_8; + wire ex2_t02_9; + wire ex2_g04_6_b; + wire ex2_g04_7_b; + wire ex2_g04_8_b; + wire ex2_g04_9_b; + wire ex2_t04_6_b; + wire ex2_t04_7_b; + wire ex2_t04_8_b; + wire ex2_t04_9_b; + wire ex2_g08_6; + wire ex2_g04_7; + wire ex2_g04_8; + wire ex2_g04_9; + wire ex2_t04_7; + wire ex2_t04_8; + wire ex2_t04_9; + wire ex2_bsha_6; + wire ex2_bsha_7; + wire ex2_bsha_8; + wire ex2_bsha_9; + wire ex2_g02_4; + wire ex2_g02_2; + wire ex2_t02_4; + wire ex2_t02_2; + wire ex2_g04_2_b; + wire ex2_t04_2_b; + wire ex2_ones_2t3_b; + wire ex2_ones_4t5_b; + wire ex2_ones_2t5; + wire ex2_ones_2t5_b; + wire ex2_zero_2_b; + wire ex2_zero_3_b; + wire ex2_zero_4_b; + wire ex2_zero_5; + wire ex2_zero_5_b; + wire ex2_zero_2t3; + wire ex2_zero_4t5; + wire ex2_zero_2t5_b; + wire pos_if_pco6; + wire pos_if_nco6; + wire pos_if_pco6_b; + wire pos_if_nco6_b; + wire unf_if_nco6_b; + wire unf_if_pco6_b; + wire ex2_g08_6_b; + wire ex2_bsha_pos; + wire ex2_bsha_6_i; + wire ex2_bsha_7_i; + wire ex2_bsha_8_i; + wire ex2_bsha_9_i; + wire [1:13] ex2_ack_s; + wire [1:12] ex2_ack_c; + + + + //==############################################################## + //# map block attributes + //==############################################################## + + //----------------------------------------------------- + // FOR simulation only : will not generate any logic + //----------------------------------------------------- + + assign ex2_bsha_sim_p[1:12] = ex2_alg_sx[1:12] ^ ex2_alg_cx[1:12]; + assign ex2_bsha_sim_p[13] = ex2_alg_sx[13]; + assign ex2_bsha_sim_g[2:12] = ex2_alg_sx[2:12] & ex2_alg_cx[2:12]; + assign ex2_bsha_sim_g[13] = tidn; + assign ex2_bsha_sim[1:13] = ex2_bsha_sim_p[1:13] ^ ex2_bsha_sim_c[2:14]; + + assign ex2_bsha_sim_c[14] = tidn; + assign ex2_bsha_sim_c[13] = ex2_bsha_sim_g[13] | (ex2_bsha_sim_p[13] & ex2_bsha_sim_c[14]); + assign ex2_bsha_sim_c[12] = ex2_bsha_sim_g[12] | (ex2_bsha_sim_p[12] & ex2_bsha_sim_c[13]); + assign ex2_bsha_sim_c[11] = ex2_bsha_sim_g[11] | (ex2_bsha_sim_p[11] & ex2_bsha_sim_c[12]); + assign ex2_bsha_sim_c[10] = ex2_bsha_sim_g[10] | (ex2_bsha_sim_p[10] & ex2_bsha_sim_c[11]); + assign ex2_bsha_sim_c[9] = ex2_bsha_sim_g[9] | (ex2_bsha_sim_p[9] & ex2_bsha_sim_c[10]); + assign ex2_bsha_sim_c[8] = ex2_bsha_sim_g[8] | (ex2_bsha_sim_p[8] & ex2_bsha_sim_c[9]); + assign ex2_bsha_sim_c[7] = ex2_bsha_sim_g[7] | (ex2_bsha_sim_p[7] & ex2_bsha_sim_c[8]); + assign ex2_bsha_sim_c[6] = ex2_bsha_sim_g[6] | (ex2_bsha_sim_p[6] & ex2_bsha_sim_c[7]); + assign ex2_bsha_sim_c[5] = ex2_bsha_sim_g[5] | (ex2_bsha_sim_p[5] & ex2_bsha_sim_c[6]); + assign ex2_bsha_sim_c[4] = ex2_bsha_sim_g[4] | (ex2_bsha_sim_p[4] & ex2_bsha_sim_c[5]); + assign ex2_bsha_sim_c[3] = ex2_bsha_sim_g[3] | (ex2_bsha_sim_p[3] & ex2_bsha_sim_c[4]); + assign ex2_bsha_sim_c[2] = ex2_bsha_sim_g[2] | (ex2_bsha_sim_p[2] & ex2_bsha_sim_c[3]); + + //==############################################################## + //# ex2 logic + //==############################################################## + //==-------------------------------------- + //== timing ? long-cut to make sha have correct meaning + //==-------------------------------------- + // for MADD operations SHA = (Ea+Ec+!Eb) + 1 -bias + 56 + // (Ea+Ec+!Eb) + 57 +!bias + 1 + // (Ea+Ec+!Eb) + 58 +!bias + // 0_0011_1111_1111 bias = 1023 + // 1_1100_0000_0000 !bias + // 11_1010 58 + // ----------------------- + // 1_1100_0011_1010 ( !bias + 58 ) + // + // leading bit [1] is a sign bit, but the compressor creates bit 0. + // 13 bits should be enough to hold the entire result, therefore throw away bit 0. + + assign ex2_a_expo_b[2:13] = (~f_byp_alg_ex2_a_expo[2:13]); + assign ex2_c_expo_b[2:13] = (~f_byp_alg_ex2_c_expo[2:13]); + assign ex2_b_expo_b[1:13] = (~f_byp_alg_ex2_b_expo[1:13]); + + assign ex2_ack_s[1] = (~(f_byp_alg_ex2_a_expo[1] ^ f_byp_alg_ex2_c_expo[1])); //K[ 1]==1 + assign ex2_ack_s[2] = (~(f_byp_alg_ex2_a_expo[2] ^ f_byp_alg_ex2_c_expo[2])); //K[ 2]==1 + assign ex2_ack_s[3] = (~(f_byp_alg_ex2_a_expo[3] ^ f_byp_alg_ex2_c_expo[3])); //K[ 3]==1 + assign ex2_ack_s[4] = (f_byp_alg_ex2_a_expo[4] ^ f_byp_alg_ex2_c_expo[4]); //K[ 4]==0 + assign ex2_ack_s[5] = (f_byp_alg_ex2_a_expo[5] ^ f_byp_alg_ex2_c_expo[5]); //K[ 5]==0 + assign ex2_ack_s[6] = (f_byp_alg_ex2_a_expo[6] ^ f_byp_alg_ex2_c_expo[6]); //K[ 6]==0 + assign ex2_ack_s[7] = (f_byp_alg_ex2_a_expo[7] ^ f_byp_alg_ex2_c_expo[7]); //K[ 7]==0 + assign ex2_ack_s[8] = (~(f_byp_alg_ex2_a_expo[8] ^ f_byp_alg_ex2_c_expo[8])); //K[ 8]==1 + assign ex2_ack_s[9] = (~(f_byp_alg_ex2_a_expo[9] ^ f_byp_alg_ex2_c_expo[9])); //K[ 9]==1 1 + assign ex2_ack_s[10] = (~(f_byp_alg_ex2_a_expo[10] ^ f_byp_alg_ex2_c_expo[10])); //K[10]==1 1 + assign ex2_ack_s[11] = (f_byp_alg_ex2_a_expo[11] ^ f_byp_alg_ex2_c_expo[11]); //K[11]==0 + assign ex2_ack_s[12] = (~(f_byp_alg_ex2_a_expo[12] ^ f_byp_alg_ex2_c_expo[12])); //K[12]==1 + assign ex2_ack_s[13] = (f_byp_alg_ex2_a_expo[13] ^ f_byp_alg_ex2_c_expo[13]); //K[13]==0 + + // cx00: ex2_ack_c( 0) <= not( ex2_a_expo_b( 1) and ex2_c_expo_b( 1) ); --K[ 1]==1 +or + assign ex2_ack_c[1] = (~(ex2_a_expo_b[2] & ex2_c_expo_b[2])); //K[ 2]==1 +or + assign ex2_ack_c[2] = (~(ex2_a_expo_b[3] & ex2_c_expo_b[3])); //K[ 3]==1 +or + assign ex2_ack_c[3] = (~(ex2_a_expo_b[4] | ex2_c_expo_b[4])); //K[ 4]==0 +and + assign ex2_ack_c[4] = (~(ex2_a_expo_b[5] | ex2_c_expo_b[5])); //K[ 5]==0 +and + assign ex2_ack_c[5] = (~(ex2_a_expo_b[6] | ex2_c_expo_b[6])); //K[ 6]==0 +and + assign ex2_ack_c[6] = (~(ex2_a_expo_b[7] | ex2_c_expo_b[7])); //K[ 7]==0 +and + assign ex2_ack_c[7] = (~(ex2_a_expo_b[8] & ex2_c_expo_b[8])); //K[ 8]==1 +or + assign ex2_ack_c[8] = (~(ex2_a_expo_b[9] & ex2_c_expo_b[9])); //K[ 9]==1 +or + assign ex2_ack_c[9] = (~(ex2_a_expo_b[10] & ex2_c_expo_b[10])); //K[10]==1 +or + assign ex2_ack_c[10] = (~(ex2_a_expo_b[11] | ex2_c_expo_b[11])); //K[11]==0 +and + assign ex2_ack_c[11] = (~(ex2_a_expo_b[12] & ex2_c_expo_b[12])); //K[12]==1 +or + assign ex2_ack_c[12] = (~(ex2_a_expo_b[13] | ex2_c_expo_b[13])); //K[13]==0 + + // fu_csa32s_h2 + tri_csa32 sha32_01( // #(.btr("MLT32_X1_A12TH")) c_prism_csa32 + .vd(vdd), + .gd(gnd), + .a(ex2_b_expo_b[1]), //i-- + .b(ex2_ack_s[1]), //i-- + .c(ex2_ack_c[1]), //i-- + .sum(ex2_alg_sx[1]), //o-- + .car(ex2_alg_cx[0]) //o-- + ); + + tri_csa32 sha32_02( // #(.btr("MLT32_X1_A12TH")) c_prism_csa32 + .vd(vdd), + .gd(gnd), + .a(ex2_b_expo_b[2]), //i-- + .b(ex2_ack_s[2]), //i-- + .c(ex2_ack_c[2]), //i-- + .sum(ex2_alg_sx[2]), //o-- + .car(ex2_alg_cx[1]) //o-- + ); + + tri_csa32 sha32_03( // #(.btr("MLT32_X1_A12TH")) c_prism_csa32 + .vd(vdd), + .gd(gnd), + .a(ex2_b_expo_b[3]), //i-- + .b(ex2_ack_s[3]), //i-- + .c(ex2_ack_c[3]), //i-- + .sum(ex2_alg_sx[3]), //o-- + .car(ex2_alg_cx[2]) //o-- + ); + + tri_csa32 sha32_04( // #(.btr("MLT32_X1_A12TH")) c_prism_csa32 + .vd(vdd), + .gd(gnd), + .a(ex2_b_expo_b[4]), //i-- + .b(ex2_ack_s[4]), //i-- + .c(ex2_ack_c[4]), //i-- + .sum(ex2_alg_sx[4]), //o-- + .car(ex2_alg_cx[3]) //o-- + ); + + tri_csa32 sha32_05( // #(.btr("MLT32_X1_A12TH")) c_prism_csa32 + .vd(vdd), + .gd(gnd), + .a(ex2_b_expo_b[5]), //i-- + .b(ex2_ack_s[5]), //i-- + .c(ex2_ack_c[5]), //i-- + .sum(ex2_alg_sx[5]), //o-- + .car(ex2_alg_cx[4]) //o-- + ); + + tri_csa32 sha32_06( // #(.btr("MLT32_X1_A12TH")) c_prism_csa32 + .vd(vdd), + .gd(gnd), + .a(ex2_b_expo_b[6]), //i-- + .b(ex2_ack_s[6]), //i-- + .c(ex2_ack_c[6]), //i-- + .sum(ex2_alg_sx[6]), //o-- + .car(ex2_alg_cx[5]) //o-- + ); + + tri_csa32 sha32_07( // #(.btr("MLT32_X1_A12TH")) c_prism_csa32 + .vd(vdd), + .gd(gnd), + .a(ex2_b_expo_b[7]), //i-- + .b(ex2_ack_s[7]), //i-- + .c(ex2_ack_c[7]), //i-- + .sum(ex2_alg_sx[7]), //o-- + .car(ex2_alg_cx[6]) //o-- + ); + + tri_csa32 sha32_08( // #(.btr("MLT32_X1_A12TH")) c_prism_csa32 + .vd(vdd), + .gd(gnd), + .a(ex2_b_expo_b[8]), //i-- + .b(ex2_ack_s[8]), //i-- + .c(ex2_ack_c[8]), //i-- + .sum(ex2_alg_sx[8]), //o-- + .car(ex2_alg_cx[7]) //o-- + ); + + tri_csa32 sha32_09( // #(.btr("MLT32_X1_A12TH")) c_prism_csa32 + .vd(vdd), + .gd(gnd), + .a(ex2_b_expo_b[9]), //i-- + .b(ex2_ack_s[9]), //i-- + .c(ex2_ack_c[9]), //i-- + .sum(ex2_alg_sx[9]), //o-- + .car(ex2_alg_cx[8]) //o-- + ); + + tri_csa32 sha32_10( // #(.btr("MLT32_X1_A12TH")) c_prism_csa32 + .vd(vdd), + .gd(gnd), + .a(ex2_b_expo_b[10]), //i-- + .b(ex2_ack_s[10]), //i-- + .c(ex2_ack_c[10]), //i-- + .sum(ex2_alg_sx[10]), //o-- + .car(ex2_alg_cx[9]) //o-- + ); + + tri_csa32 sha32_11( // #(.btr("MLT32_X1_A12TH")) c_prism_csa32 + .vd(vdd), + .gd(gnd), + .a(ex2_b_expo_b[11]), //i-- + .b(ex2_ack_s[11]), //i-- + .c(ex2_ack_c[11]), //i-- + .sum(ex2_alg_sx[11]), //o-- + .car(ex2_alg_cx[10]) //o-- + ); + + tri_csa32 sha32_12( // #(.btr("MLT32_X1_A12TH")) c_prism_csa32 + .vd(vdd), + .gd(gnd), + .a(ex2_b_expo_b[12]), //i-- + .b(ex2_ack_s[12]), //i-- + .c(ex2_ack_c[12]), //i-- + .sum(ex2_alg_sx[12]), //o-- + .car(ex2_alg_cx[11]) //o-- + ); + + tri_csa32 sha32_13( // #(.btr("MLT32_X1_A12TH")) c_prism_csa32 + .vd(vdd), + .gd(gnd), + .a(ex2_b_expo_b[13]), //i-- + .b(ex2_ack_s[13]), //i-- + .c(tidn), //i-- + .sum(ex2_alg_sx[13]), //o-- + .car(ex2_alg_cx[12]) //o-- + ); + + // now finish the add (for sha==0 means shift 0) + + assign ex2_alg_add_p[1] = ex2_alg_sx[1] ^ ex2_alg_cx[1]; + assign ex2_alg_add_p[2] = ex2_alg_sx[2] ^ ex2_alg_cx[2]; + assign ex2_alg_add_p[3] = ex2_alg_sx[3] ^ ex2_alg_cx[3]; + assign ex2_alg_add_p[4] = ex2_alg_sx[4] ^ ex2_alg_cx[4]; + assign ex2_alg_add_p[5] = ex2_alg_sx[5] ^ ex2_alg_cx[5]; + assign ex2_alg_add_p[6] = ex2_alg_sx[6] ^ ex2_alg_cx[6]; + assign ex2_alg_add_p[7] = ex2_alg_sx[7] ^ ex2_alg_cx[7]; + assign ex2_alg_add_p[8] = ex2_alg_sx[8] ^ ex2_alg_cx[8]; + assign ex2_alg_add_p[9] = ex2_alg_sx[9] ^ ex2_alg_cx[9]; + assign ex2_alg_add_p[10] = ex2_alg_sx[10] ^ ex2_alg_cx[10]; + assign ex2_alg_add_p[11] = ex2_alg_sx[11] ^ ex2_alg_cx[11]; + assign ex2_alg_add_p[12] = ex2_alg_sx[12] ^ ex2_alg_cx[12]; + // ex2_alg_add_p(13) <= ex2_alg_sx(13); + + //g1_01: ex2_alg_add_g_b( 1) <= not( ex2_alg_sx( 1) and ex2_alg_cx( 1) ); + assign ex2_alg_add_g_b[2] = (~(ex2_alg_sx[2] & ex2_alg_cx[2])); + assign ex2_alg_add_g_b[3] = (~(ex2_alg_sx[3] & ex2_alg_cx[3])); + assign ex2_alg_add_g_b[4] = (~(ex2_alg_sx[4] & ex2_alg_cx[4])); + assign ex2_alg_add_g_b[5] = (~(ex2_alg_sx[5] & ex2_alg_cx[5])); + assign ex2_alg_add_g_b[6] = (~(ex2_alg_sx[6] & ex2_alg_cx[6])); + assign ex2_alg_add_g_b[7] = (~(ex2_alg_sx[7] & ex2_alg_cx[7])); + assign ex2_alg_add_g_b[8] = (~(ex2_alg_sx[8] & ex2_alg_cx[8])); + assign ex2_alg_add_g_b[9] = (~(ex2_alg_sx[9] & ex2_alg_cx[9])); + assign ex2_alg_add_g_b[10] = (~(ex2_alg_sx[10] & ex2_alg_cx[10])); + assign ex2_alg_add_g_b[11] = (~(ex2_alg_sx[11] & ex2_alg_cx[11])); + assign ex2_alg_add_g_b[12] = (~(ex2_alg_sx[12] & ex2_alg_cx[12])); + + //t1_01: ex2_alg_add_t_b( 1) <= not( ex2_alg_sx( 1) or ex2_alg_cx( 1) ); + assign ex2_alg_add_t_b[2] = (~(ex2_alg_sx[2] | ex2_alg_cx[2])); + assign ex2_alg_add_t_b[3] = (~(ex2_alg_sx[3] | ex2_alg_cx[3])); + assign ex2_alg_add_t_b[4] = (~(ex2_alg_sx[4] | ex2_alg_cx[4])); + assign ex2_alg_add_t_b[5] = (~(ex2_alg_sx[5] | ex2_alg_cx[5])); + assign ex2_alg_add_t_b[6] = (~(ex2_alg_sx[6] | ex2_alg_cx[6])); + assign ex2_alg_add_t_b[7] = (~(ex2_alg_sx[7] | ex2_alg_cx[7])); + assign ex2_alg_add_t_b[8] = (~(ex2_alg_sx[8] | ex2_alg_cx[8])); + assign ex2_alg_add_t_b[9] = (~(ex2_alg_sx[9] | ex2_alg_cx[9])); + assign ex2_alg_add_t_b[10] = (~(ex2_alg_sx[10] | ex2_alg_cx[10])); + assign ex2_alg_add_t_b[11] = (~(ex2_alg_sx[11] | ex2_alg_cx[11])); + + //--------------------------------------------------------------------- + // 12:13 are a decode group (12,13) are known before adder starts ) + //--------------------------------------------------------------------- + + assign ex2_g02_12 = (~ex2_alg_add_g_b[12]); // main carry chain + assign ex2_g02_12_b = (~ex2_g02_12); // main carry chain + + assign ex2_bsha_13_b = (~ex2_alg_sx[13]); // direct from compressor + assign ex2_bsha_13 = (~ex2_bsha_13_b); // to decoder 0/1/2/3 + assign ex2_bsha_12_b = (~ex2_alg_add_p[12]); + assign ex2_bsha_12 = (~ex2_bsha_12_b); // to decoder 0/1/2/3 + + assign ex2_lv2_ci11n_en_b = (~(ex2_sel_special_b & ex2_g02_12_b)); + assign ex2_lv2_ci11p_en_b = (~(ex2_sel_special_b & ex2_g02_12)); + assign ex2_lv2_ci11n_en = (~(ex2_lv2_ci11n_en_b)); // to decoder 0/4/8/12 + assign ex2_lv2_ci11p_en = (~(ex2_lv2_ci11p_en_b)); // to decoder 0/4/8/12 + + //--------------------------------------------------------------------- + // 10:11 are a decode group, do not compute adder result (send signal direct to decode) + //--------------------------------------------------------------------- + + assign ex2_g02_10 = (~(ex2_alg_add_g_b[10] & (ex2_alg_add_t_b[10] | ex2_alg_add_g_b[11]))); //main carry chain + assign ex2_t02_10 = (~(ex2_alg_add_t_b[10] | ex2_alg_add_t_b[11])); //main carry chain + assign ex2_g04_10_b = (~(ex2_g02_10 | (ex2_t02_10 & ex2_g02_12))); //main carry chain + + assign ex2_lv2_g11_x = (~(ex2_alg_add_g_b[11])); + assign ex2_lv2_g11_b = (~(ex2_lv2_g11_x)); + assign ex2_lv2_g11 = (~(ex2_lv2_g11_b)); // to decoder 0/4/8/12 + assign ex2_lv2_k11_b = (~(ex2_alg_add_t_b[11])); + assign ex2_lv2_k11 = (~(ex2_lv2_k11_b)); // to decoder 0/4/8/12 + assign ex2_lv2_p11_b = (~(ex2_alg_add_p[11])); + assign ex2_lv2_p11 = (~(ex2_lv2_p11_b)); // to decoder 0/4/8/12 + assign ex2_lv2_p10_b = (~(ex2_alg_add_p[10])); // to decoder 0/4/8/12 + assign ex2_lv2_p10 = (~(ex2_lv2_p10_b)); // to decoder 0/4/8/12 + + //--------------------------------------------------------------------- + // 6:9 are a decode group, not used until next cycle: (get add result then decode) + //---------------------------------------------------------------------- + + assign ex2_g04_10 = (~ex2_g04_10_b); // use this buffered of version to finish the local carry chain + + assign ex2_g02_6 = (~(ex2_alg_add_g_b[6] & (ex2_alg_add_t_b[6] | ex2_alg_add_g_b[7]))); + assign ex2_g02_7 = (~(ex2_alg_add_g_b[7] & (ex2_alg_add_t_b[7] | ex2_alg_add_g_b[8]))); + assign ex2_g02_8 = (~(ex2_alg_add_g_b[8] & (ex2_alg_add_t_b[8] | ex2_alg_add_g_b[9]))); + assign ex2_g02_9 = (~(ex2_alg_add_g_b[9])); + assign ex2_t02_6 = (~(ex2_alg_add_t_b[6] | ex2_alg_add_t_b[7])); + assign ex2_t02_7 = (~(ex2_alg_add_t_b[7] | ex2_alg_add_t_b[8])); + assign ex2_t02_8 = (~(ex2_alg_add_t_b[8] | ex2_alg_add_t_b[9])); + assign ex2_t02_9 = (~(ex2_alg_add_t_b[9])); + + assign ex2_g04_6_b = (~(ex2_g02_6 | (ex2_t02_6 & ex2_g02_8))); + assign ex2_g04_7_b = (~(ex2_g02_7 | (ex2_t02_7 & ex2_g02_9))); + assign ex2_g04_8_b = (~(ex2_g02_8)); + assign ex2_g04_9_b = (~(ex2_g02_9)); + assign ex2_t04_6_b = (~(ex2_t02_6 & ex2_t02_8)); + assign ex2_t04_7_b = (~(ex2_t02_7 & ex2_t02_9)); + assign ex2_t04_8_b = (~(ex2_t02_8)); + assign ex2_t04_9_b = (~(ex2_t02_9)); + + assign ex2_g08_6 = (~(ex2_g04_6_b & (ex2_t04_6_b | ex2_g04_10_b))); //main carry chain + assign ex2_g04_7 = (~(ex2_g04_7_b)); + assign ex2_g04_8 = (~(ex2_g04_8_b)); + assign ex2_g04_9 = (~(ex2_g04_9_b)); + assign ex2_t04_7 = (~(ex2_t04_7_b)); + assign ex2_t04_8 = (~(ex2_t04_8_b)); + assign ex2_t04_9 = (~(ex2_t04_9_b)); + + assign ex2_alg_add_c_b[7] = (~(ex2_g04_7 | (ex2_t04_7 & ex2_g04_10))); + assign ex2_alg_add_c_b[8] = (~(ex2_g04_8 | (ex2_t04_8 & ex2_g04_10))); + assign ex2_alg_add_c_b[9] = (~(ex2_g04_9 | (ex2_t04_9 & ex2_g04_10))); + assign ex2_alg_add_c_b[10] = (~(ex2_g04_10)); + + assign ex2_bsha_6 = (~(ex2_alg_add_p[6] ^ ex2_alg_add_c_b[7])); //to multiple of 16 decoder + assign ex2_bsha_7 = (~(ex2_alg_add_p[7] ^ ex2_alg_add_c_b[8])); //to multiple of 16 decoder + assign ex2_bsha_8 = (~(ex2_alg_add_p[8] ^ ex2_alg_add_c_b[9])); //to multiple of 16 decoder + assign ex2_bsha_9 = (~(ex2_alg_add_p[9] ^ ex2_alg_add_c_b[10])); //to multiple of 16 decoder + + assign ex2_bsha_6_i = (~ex2_bsha_6); + assign ex2_bsha_7_i = (~ex2_bsha_7); + assign ex2_bsha_8_i = (~ex2_bsha_8); + assign ex2_bsha_9_i = (~ex2_bsha_9); + + assign ex2_bsha_6_o = (~ex2_bsha_6_i); + assign ex2_bsha_7_o = (~ex2_bsha_7_i); + assign ex2_bsha_8_o = (~ex2_bsha_8_i); + assign ex2_bsha_9_o = (~ex2_bsha_9_i); + + //----------------------------------------------------------------------- + // Just need to know if 2/3/4/5 != 0000 for unf, produce that signal directly + //----------------------------------------------------------------------- + + assign ex2_g02_2 = (~(ex2_alg_add_g_b[2] & (ex2_alg_add_t_b[2] | ex2_alg_add_g_b[3]))); //for carry select + assign ex2_g02_4 = (~(ex2_alg_add_g_b[4] & (ex2_alg_add_t_b[4] | ex2_alg_add_g_b[5]))); //for carry select + + assign ex2_t02_2 = (~((ex2_alg_add_t_b[2] | ex2_alg_add_t_b[3]))); //for carry select + assign ex2_t02_4 = (~(ex2_alg_add_g_b[4] & (ex2_alg_add_t_b[4] | ex2_alg_add_t_b[5]))); //for carry select + + assign ex2_g04_2_b = (~(ex2_g02_2 | (ex2_t02_2 & ex2_g02_4))); //for carry select + assign ex2_t04_2_b = (~(ex2_g02_2 | (ex2_t02_2 & ex2_t02_4))); //for carry select + + assign ex2_ones_2t3_b = (~(ex2_alg_add_p[2] & ex2_alg_add_p[3])); // for unf calculation + assign ex2_ones_4t5_b = (~(ex2_alg_add_p[4] & ex2_alg_add_p[5])); // for unf calculation + assign ex2_ones_2t5 = (~(ex2_ones_2t3_b | ex2_ones_4t5_b)); // for unf calculation + assign ex2_ones_2t5_b = (~(ex2_ones_2t5)); + + assign ex2_zero_2_b = (~(ex2_alg_add_p[2] ^ ex2_alg_add_t_b[3])); // for unf calc + assign ex2_zero_3_b = (~(ex2_alg_add_p[3] ^ ex2_alg_add_t_b[4])); // for unf calc + assign ex2_zero_4_b = (~(ex2_alg_add_p[4] ^ ex2_alg_add_t_b[5])); // for unf calc + assign ex2_zero_5 = (~(ex2_alg_add_p[5])); // for unf calc + assign ex2_zero_5_b = (~(ex2_zero_5)); // for unf calc + assign ex2_zero_2t3 = (~(ex2_zero_2_b | ex2_zero_3_b)); // for unf calc + assign ex2_zero_4t5 = (~(ex2_zero_4_b | ex2_zero_5_b)); // for unf calc + assign ex2_zero_2t5_b = (~(ex2_zero_2t3 & ex2_zero_4t5)); // for unf calc + + //-------------------------------------------------------------------------- + // [1] is really the sign bit .. needed to indicate ovf/underflow + //----------------------------------------------- + // finish shift underflow + // if sha > 162 all the bits should become sticky and the aligner output should be zero + // from 163:255 the shifter does this, so just need to detect the upper bits + + assign pos_if_pco6 = (ex2_alg_add_p[1] ^ ex2_t04_2_b); + assign pos_if_nco6 = (ex2_alg_add_p[1] ^ ex2_g04_2_b); + assign pos_if_pco6_b = (~pos_if_pco6); + assign pos_if_nco6_b = (~pos_if_nco6); + + assign unf_if_nco6_b = (~(pos_if_nco6 & ex2_zero_2t5_b)); + assign unf_if_pco6_b = (~(pos_if_pco6 & ex2_ones_2t5_b)); + + assign ex2_g08_6_b = (~ex2_g08_6); + assign ex2_bsha_pos = (~((pos_if_pco6_b & ex2_g08_6) | (pos_if_nco6_b & ex2_g08_6_b))); // same as neg + assign ex2_sh_ovf_b = (~((pos_if_pco6_b & ex2_g08_6) | (pos_if_nco6_b & ex2_g08_6_b))); // same as neg + assign ex2_sh_unf_x = (~((unf_if_pco6_b & ex2_g08_6) | (unf_if_nco6_b & ex2_g08_6_b))); + assign ex2_bsha_neg = (~(ex2_bsha_pos)); + assign ex2_bsha_neg_o = (~(ex2_bsha_pos)); + assign ex2_sh_ovf = (~(ex2_sh_ovf_b)); + + //==------------------------------------------------------------------------------- + //== decode for first level shifter (0/1/2/3) + //==------------------------------------------------------------------------------- + + assign ex2_lvl1_shdcd000_b = (~(ex2_bsha_12_b & ex2_bsha_13_b)); + assign ex2_lvl1_shdcd001_b = (~(ex2_bsha_12_b & ex2_bsha_13)); + assign ex2_lvl1_shdcd002_b = (~(ex2_bsha_12 & ex2_bsha_13_b)); + assign ex2_lvl1_shdcd003_b = (~(ex2_bsha_12 & ex2_bsha_13)); + + //==------------------------------------------------------------------------------- + //== decode for second level shifter (0/4/8/12) + //==------------------------------------------------------------------------------- + // ex2_lvl2_shdcd000 <= not ex2_bsha(10) and not ex2_bsha(11) ; + // ex2_lvl2_shdcd004 <= not ex2_bsha(10) and ex2_bsha(11) ; + // ex2_lvl2_shdcd008 <= ex2_bsha(10) and not ex2_bsha(11) ; + // ex2_lvl2_shdcd012 <= ex2_bsha(10) and ex2_bsha(11) ; + //-------------------------------------------------------------------- + // p10 (11) ci11 DCD p10 (11) ci11 DCD + // !p k 0 00 !p k 0 00 + // !P p 0 01 p g 0 00 + // !p g 0 10 P p 1 00 + // + // p k 0 10 !P p 0 01 + // P p 0 11 !p k 1 01 + // p g 0 00 p g 1 01 + // + // !p k 1 01 !p g 0 10 + // !P p 1 10 p k 0 10 + // !p g 1 11 !P p 1 10 + // + // p k 1 11 P p 0 11 + // P p 1 00 !p g 1 11 + // p g 1 01 p k 1 11 + + assign ex2_lv2_0pg0_b = (~(ex2_lv2_p10_b & ex2_lv2_g11 & ex2_lv2_ci11n_en)); + assign ex2_lv2_0pg1_b = (~(ex2_lv2_p10_b & ex2_lv2_g11 & ex2_lv2_ci11p_en)); + assign ex2_lv2_0pk0_b = (~(ex2_lv2_p10_b & ex2_lv2_k11 & ex2_lv2_ci11n_en)); + assign ex2_lv2_0pk1_b = (~(ex2_lv2_p10_b & ex2_lv2_k11 & ex2_lv2_ci11p_en)); + assign ex2_lv2_0pp0_b = (~(ex2_lv2_p10_b & ex2_lv2_p11 & ex2_lv2_ci11n_en)); + assign ex2_lv2_0pp1_b = (~(ex2_lv2_p10_b & ex2_lv2_p11 & ex2_lv2_ci11p_en)); + assign ex2_lv2_1pg0_b = (~(ex2_lv2_p10 & ex2_lv2_g11 & ex2_lv2_ci11n_en)); + assign ex2_lv2_1pg1_b = (~(ex2_lv2_p10 & ex2_lv2_g11 & ex2_lv2_ci11p_en)); + assign ex2_lv2_1pk0_b = (~(ex2_lv2_p10 & ex2_lv2_k11 & ex2_lv2_ci11n_en)); + assign ex2_lv2_1pk1_b = (~(ex2_lv2_p10 & ex2_lv2_k11 & ex2_lv2_ci11p_en)); + assign ex2_lv2_1pp0_b = (~(ex2_lv2_p10 & ex2_lv2_p11 & ex2_lv2_ci11n_en)); + assign ex2_lv2_1pp1_b = (~(ex2_lv2_p10 & ex2_lv2_p11 & ex2_lv2_ci11p_en)); + + assign ex2_lv2_shdcd000 = (~(ex2_lv2_0pk0_b & ex2_lv2_1pg0_b & ex2_lv2_1pp1_b)); + assign ex2_lv2_shdcd004 = (~(ex2_lv2_0pp0_b & ex2_lv2_0pk1_b & ex2_lv2_1pg1_b)); + assign ex2_lv2_shdcd008 = (~(ex2_lv2_0pg0_b & ex2_lv2_1pk0_b & ex2_lv2_0pp1_b)); + assign ex2_lv2_shdcd012 = (~(ex2_lv2_1pp0_b & ex2_lv2_0pg1_b & ex2_lv2_1pk1_b)); + + assign ex2_lvl2_shdcd000_b = (~ex2_lv2_shdcd000); + assign ex2_lvl2_shdcd004_b = (~ex2_lv2_shdcd004); + assign ex2_lvl2_shdcd008_b = (~ex2_lv2_shdcd008); + assign ex2_lvl2_shdcd012_b = (~ex2_lv2_shdcd012); + + assign ex2_lvl2_shdcd000 = (~ex2_lvl2_shdcd000_b); + assign ex2_lvl2_shdcd004 = (~ex2_lvl2_shdcd004_b); + assign ex2_lvl2_shdcd008 = (~ex2_lvl2_shdcd008_b); + assign ex2_lvl2_shdcd012 = (~ex2_lvl2_shdcd012_b); + + //==-------------------------------------------- + //== decode to control ex3 shifting + //==-------------------------------------------- + + assign ex2_bsha_6_b = (~ex2_bsha_6); + assign ex2_bsha_7_b = (~ex2_bsha_7); + assign ex2_bsha_8_b = (~ex2_bsha_8); + assign ex2_bsha_9_b = (~ex2_bsha_9); + + assign ex2_67_dcd00_b = (~(ex2_bsha_6_b & ex2_bsha_7_b)); + assign ex2_67_dcd01_b = (~(ex2_bsha_6_b & ex2_bsha_7)); + assign ex2_67_dcd10_b = (~(ex2_bsha_6 & ex2_bsha_7_b)); + assign ex2_67_dcd11_b = (~(ex2_bsha_6 & ex2_bsha_7 & ex2_bsha_neg)); + + assign ex2_89_dcd00_b = (~(ex2_bsha_8_b & ex2_bsha_9_b & ex2_sel_special_b)); + assign ex2_89_dcd01_b = (~(ex2_bsha_8_b & ex2_bsha_9 & ex2_sel_special_b)); + assign ex2_89_dcd10_b = (~(ex2_bsha_8 & ex2_bsha_9_b & ex2_sel_special_b)); + assign ex2_89_dcd11_b = (~(ex2_bsha_8 & ex2_bsha_9 & ex2_sel_special_b)); + + assign ex2_lvl3_shdcd000 = (~(ex2_67_dcd00_b | ex2_89_dcd00_b)); // 0000 +000 + assign ex2_lvl3_shdcd016 = (~(ex2_67_dcd00_b | ex2_89_dcd01_b)); // 0001 +016 + assign ex2_lvl3_shdcd032 = (~(ex2_67_dcd00_b | ex2_89_dcd10_b)); // 0010 +032 + assign ex2_lvl3_shdcd048 = (~(ex2_67_dcd00_b | ex2_89_dcd11_b)); // 0011 +048 + assign ex2_lvl3_shdcd064 = (~(ex2_67_dcd01_b | ex2_89_dcd00_b)); // 0100 +064 + assign ex2_lvl3_shdcd080 = (~(ex2_67_dcd01_b | ex2_89_dcd01_b)); // 0101 +080 + assign ex2_lvl3_shdcd096 = (~(ex2_67_dcd01_b | ex2_89_dcd10_b)); // 0110 +096 + assign ex2_lvl3_shdcd112 = (~(ex2_67_dcd01_b | ex2_89_dcd11_b)); // 0111 +112 + assign ex2_lvl3_shdcd128 = (~(ex2_67_dcd10_b | ex2_89_dcd00_b)); // 1000 +128 + assign ex2_lvl3_shdcd144 = (~(ex2_67_dcd10_b | ex2_89_dcd01_b)); // 1001 +144 + assign ex2_lvl3_shdcd160 = (~(ex2_67_dcd10_b | ex2_89_dcd10_b)); // 1010 +160 + assign ex2_lvl3_shdcd176 = (~(ex2_67_dcd10_b | ex2_89_dcd11_b)); // 1011 + assign ex2_lvl3_shdcd192 = (~(ex2_67_dcd11_b | ex2_89_dcd00_b)); // 1100 -064 + assign ex2_lvl3_shdcd208 = (~(ex2_67_dcd11_b | ex2_89_dcd01_b)); // 1101 -048 + assign ex2_lvl3_shdcd224 = (~(ex2_67_dcd11_b | ex2_89_dcd10_b)); // 1110 -032 + assign ex2_lvl3_shdcd240 = (~(ex2_67_dcd11_b | ex2_89_dcd11_b)); // 1111 -016 + +endmodule diff --git a/dev/verilog/work/fu_alg_bypmux.v b/dev/verilog/work/fu_alg_bypmux.v new file mode 100755 index 0000000..39a8acb --- /dev/null +++ b/dev/verilog/work/fu_alg_bypmux.v @@ -0,0 +1,120 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + + `include "tri_a2o.vh" + +module fu_alg_bypmux( + ex3_byp_sel_byp_neg, + ex3_byp_sel_byp_pos, + ex3_byp_sel_neg, + ex3_byp_sel_pos, + ex3_prd_sel_neg_hi, + ex3_prd_sel_neg_lo, + ex3_prd_sel_neg_lohi, + ex3_prd_sel_pos_hi, + ex3_prd_sel_pos_lo, + ex3_prd_sel_pos_lohi, + ex3_sh_lvl3, + f_fmt_ex3_pass_frac, + f_alg_ex3_res +); + //--------- BYPASS CONTROLS ----------------- + input ex3_byp_sel_byp_neg; + input ex3_byp_sel_byp_pos; + input ex3_byp_sel_neg; + input ex3_byp_sel_pos; + input ex3_prd_sel_neg_hi; + input ex3_prd_sel_neg_lo; + input ex3_prd_sel_neg_lohi; + input ex3_prd_sel_pos_hi; + input ex3_prd_sel_pos_lo; + input ex3_prd_sel_pos_lohi; + + //--------- BYPASS DATA ----------------- + input [0:162] ex3_sh_lvl3; + input [0:52] f_fmt_ex3_pass_frac; + + //-------- BYPASS OUTPUT --------------- + output [0:162] f_alg_ex3_res; + + // ENTITY + + + parameter tiup = 1'b1; + parameter tidn = 1'b0; + + wire [0:162] m0_b; + wire [0:162] m1_b; + wire [0:162] ex3_sh_lvl3_b; + wire [0:52] f_fmt_ex3_pass_frac_b; + + + //#------------------------------------------------- + //# bypass mux & operand flip + //#------------------------------------------------- + //# integer operation positions + //# 32 32 + //# 99:130 131:162 + + assign ex3_sh_lvl3_b[0:162] = (~(ex3_sh_lvl3[0:162])); + assign f_fmt_ex3_pass_frac_b[0:52] = (~(f_fmt_ex3_pass_frac[0:52])); + + //-------------------------------------------------------------- + + assign m0_b[0:52] = (~(({53{ex3_byp_sel_pos}} & ex3_sh_lvl3[0:52]) | + ({53{ex3_byp_sel_neg}} & ex3_sh_lvl3_b[0:52]))); + + assign m1_b[0:52] = (~(({53{ex3_byp_sel_byp_pos}} & f_fmt_ex3_pass_frac[0:52]) | + ({53{ex3_byp_sel_byp_neg}} & f_fmt_ex3_pass_frac_b[0:52]))); + //--------------------------------------------------------------- + //--------------------------------------------------------------- + + assign m0_b[53:98] = (~({46{ex3_prd_sel_pos_hi}} & ex3_sh_lvl3[53:98])); + + assign m1_b[53:98] = (~({46{ex3_prd_sel_neg_hi}} & ex3_sh_lvl3_b[53:98])); + + //--------------------------------------------------------------- + + assign m0_b[99:130] = (~({32{ex3_prd_sel_pos_lohi}} & ex3_sh_lvl3[99:130])); + + assign m1_b[99:130] = (~({32{ex3_prd_sel_neg_lohi}} & ex3_sh_lvl3_b[99:130])); + + //--------------------------------------------------------------- + + assign m0_b[131:162] = (~({32{ex3_prd_sel_pos_lo}} & ex3_sh_lvl3[131:162])); + + assign m1_b[131:162] = (~({32{ex3_prd_sel_neg_lo}} & ex3_sh_lvl3_b[131:162])); + + //--------------------------------------------------------------- + + assign f_alg_ex3_res[0:162] = (~(m0_b[0:162] & m1_b[0:162])); + + +endmodule diff --git a/dev/verilog/work/fu_alg_or16.v b/dev/verilog/work/fu_alg_or16.v new file mode 100755 index 0000000..70d8d53 --- /dev/null +++ b/dev/verilog/work/fu_alg_or16.v @@ -0,0 +1,171 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + + `include "tri_a2o.vh" + +module fu_alg_or16( + ex3_sh_lvl2, + ex3_sticky_or16 +); + input [0:67] ex3_sh_lvl2; + output [0:4] ex3_sticky_or16; + + // ENTITY + + + parameter tiup = 1'b1; + parameter tidn = 1'b0; + wire [0:7] ex3_g1o2_b; + wire [0:7] ex3_g2o2_b; + wire [0:7] ex3_g3o2_b; + wire [0:7] ex3_g4o2_b; + wire [0:3] ex3_g1o4; + wire [0:3] ex3_g2o4; + wire [0:3] ex3_g3o4; + wire [0:3] ex3_g4o4; + wire [0:1] ex3_g0o8_b; + wire [0:1] ex3_g1o8_b; + wire [0:1] ex3_g2o8_b; + wire [0:1] ex3_g3o8_b; + wire [0:1] ex3_g4o8_b; + wire [0:4] ex3_o16; + wire [0:4] ex3_o16_b; + + + //---------------------------------------------------------- + // UnMapped original equations + //---------------------------------------------------------- + // ex3_sticky_or16(4) <= OR( ex3_sh_lvl2[52:67] ); + // ex3_sticky_or16(3) <= OR( ex3_sh_lvl2[36:51] ); + // ex3_sticky_or16(2) <= OR( ex3_sh_lvl2[20:35] ); + // ex3_sticky_or16(1) <= OR( ex3_sh_lvl2[ 4:19] ); + // ex3_sticky_or16(0) <= OR( ex3_sh_lvl2[ 0: 3] ); + //--------------------------------------------------------- + assign ex3_g1o2_b[0] = (~(ex3_sh_lvl2[4] | ex3_sh_lvl2[5])); + assign ex3_g1o2_b[1] = (~(ex3_sh_lvl2[6] | ex3_sh_lvl2[7])); + assign ex3_g1o2_b[2] = (~(ex3_sh_lvl2[8] | ex3_sh_lvl2[9])); + assign ex3_g1o2_b[3] = (~(ex3_sh_lvl2[10] | ex3_sh_lvl2[11])); + assign ex3_g1o2_b[4] = (~(ex3_sh_lvl2[12] | ex3_sh_lvl2[13])); + assign ex3_g1o2_b[5] = (~(ex3_sh_lvl2[14] | ex3_sh_lvl2[15])); + assign ex3_g1o2_b[6] = (~(ex3_sh_lvl2[16] | ex3_sh_lvl2[17])); + assign ex3_g1o2_b[7] = (~(ex3_sh_lvl2[18] | ex3_sh_lvl2[19])); + + assign ex3_g2o2_b[0] = (~(ex3_sh_lvl2[20] | ex3_sh_lvl2[21])); + assign ex3_g2o2_b[1] = (~(ex3_sh_lvl2[22] | ex3_sh_lvl2[23])); + assign ex3_g2o2_b[2] = (~(ex3_sh_lvl2[24] | ex3_sh_lvl2[25])); + assign ex3_g2o2_b[3] = (~(ex3_sh_lvl2[26] | ex3_sh_lvl2[27])); + assign ex3_g2o2_b[4] = (~(ex3_sh_lvl2[28] | ex3_sh_lvl2[29])); + assign ex3_g2o2_b[5] = (~(ex3_sh_lvl2[30] | ex3_sh_lvl2[31])); + assign ex3_g2o2_b[6] = (~(ex3_sh_lvl2[32] | ex3_sh_lvl2[33])); + assign ex3_g2o2_b[7] = (~(ex3_sh_lvl2[34] | ex3_sh_lvl2[35])); + + assign ex3_g3o2_b[0] = (~(ex3_sh_lvl2[36] | ex3_sh_lvl2[37])); + assign ex3_g3o2_b[1] = (~(ex3_sh_lvl2[38] | ex3_sh_lvl2[39])); + assign ex3_g3o2_b[2] = (~(ex3_sh_lvl2[40] | ex3_sh_lvl2[41])); + assign ex3_g3o2_b[3] = (~(ex3_sh_lvl2[42] | ex3_sh_lvl2[43])); + assign ex3_g3o2_b[4] = (~(ex3_sh_lvl2[44] | ex3_sh_lvl2[45])); + assign ex3_g3o2_b[5] = (~(ex3_sh_lvl2[46] | ex3_sh_lvl2[47])); + assign ex3_g3o2_b[6] = (~(ex3_sh_lvl2[48] | ex3_sh_lvl2[49])); + assign ex3_g3o2_b[7] = (~(ex3_sh_lvl2[50] | ex3_sh_lvl2[51])); + + assign ex3_g4o2_b[0] = (~(ex3_sh_lvl2[52] | ex3_sh_lvl2[53])); + assign ex3_g4o2_b[1] = (~(ex3_sh_lvl2[54] | ex3_sh_lvl2[55])); + assign ex3_g4o2_b[2] = (~(ex3_sh_lvl2[56] | ex3_sh_lvl2[57])); + assign ex3_g4o2_b[3] = (~(ex3_sh_lvl2[58] | ex3_sh_lvl2[59])); + assign ex3_g4o2_b[4] = (~(ex3_sh_lvl2[60] | ex3_sh_lvl2[61])); + assign ex3_g4o2_b[5] = (~(ex3_sh_lvl2[62] | ex3_sh_lvl2[63])); + assign ex3_g4o2_b[6] = (~(ex3_sh_lvl2[64] | ex3_sh_lvl2[65])); + assign ex3_g4o2_b[7] = (~(ex3_sh_lvl2[66] | ex3_sh_lvl2[67])); + + //------------------------------------------ + + assign ex3_g1o4[0] = (~(ex3_g1o2_b[0] & ex3_g1o2_b[1])); + assign ex3_g1o4[1] = (~(ex3_g1o2_b[2] & ex3_g1o2_b[3])); + assign ex3_g1o4[2] = (~(ex3_g1o2_b[4] & ex3_g1o2_b[5])); + assign ex3_g1o4[3] = (~(ex3_g1o2_b[6] & ex3_g1o2_b[7])); + + assign ex3_g2o4[0] = (~(ex3_g2o2_b[0] & ex3_g2o2_b[1])); + assign ex3_g2o4[1] = (~(ex3_g2o2_b[2] & ex3_g2o2_b[3])); + assign ex3_g2o4[2] = (~(ex3_g2o2_b[4] & ex3_g2o2_b[5])); + assign ex3_g2o4[3] = (~(ex3_g2o2_b[6] & ex3_g2o2_b[7])); + + assign ex3_g3o4[0] = (~(ex3_g3o2_b[0] & ex3_g3o2_b[1])); + assign ex3_g3o4[1] = (~(ex3_g3o2_b[2] & ex3_g3o2_b[3])); + assign ex3_g3o4[2] = (~(ex3_g3o2_b[4] & ex3_g3o2_b[5])); + assign ex3_g3o4[3] = (~(ex3_g3o2_b[6] & ex3_g3o2_b[7])); + + assign ex3_g4o4[0] = (~(ex3_g4o2_b[0] & ex3_g4o2_b[1])); + assign ex3_g4o4[1] = (~(ex3_g4o2_b[2] & ex3_g4o2_b[3])); + assign ex3_g4o4[2] = (~(ex3_g4o2_b[4] & ex3_g4o2_b[5])); + assign ex3_g4o4[3] = (~(ex3_g4o2_b[6] & ex3_g4o2_b[7])); + + //--------------------------------------------- + + assign ex3_g0o8_b[0] = (~(ex3_sh_lvl2[0] | ex3_sh_lvl2[1])); + assign ex3_g0o8_b[1] = (~(ex3_sh_lvl2[2] | ex3_sh_lvl2[3])); + + assign ex3_g1o8_b[0] = (~(ex3_g1o4[0] | ex3_g1o4[1])); + assign ex3_g1o8_b[1] = (~(ex3_g1o4[2] | ex3_g1o4[3])); + + assign ex3_g2o8_b[0] = (~(ex3_g2o4[0] | ex3_g2o4[1])); + assign ex3_g2o8_b[1] = (~(ex3_g2o4[2] | ex3_g2o4[3])); + + assign ex3_g3o8_b[0] = (~(ex3_g3o4[0] | ex3_g3o4[1])); + assign ex3_g3o8_b[1] = (~(ex3_g3o4[2] | ex3_g3o4[3])); + + assign ex3_g4o8_b[0] = (~(ex3_g4o4[0] | ex3_g4o4[1])); + assign ex3_g4o8_b[1] = (~(ex3_g4o4[2] | ex3_g4o4[3])); + + //------------------------------------------------ + + assign ex3_o16[0] = (~(ex3_g0o8_b[0] & ex3_g0o8_b[1])); + assign ex3_o16[1] = (~(ex3_g1o8_b[0] & ex3_g1o8_b[1])); + assign ex3_o16[2] = (~(ex3_g2o8_b[0] & ex3_g2o8_b[1])); + assign ex3_o16[3] = (~(ex3_g3o8_b[0] & ex3_g3o8_b[1])); + assign ex3_o16[4] = (~(ex3_g4o8_b[0] & ex3_g4o8_b[1])); + + //------------------------------------------------ + + assign ex3_o16_b[0] = (~(ex3_o16[0])); + assign ex3_o16_b[1] = (~(ex3_o16[1])); + assign ex3_o16_b[2] = (~(ex3_o16[2])); + assign ex3_o16_b[3] = (~(ex3_o16[3])); + assign ex3_o16_b[4] = (~(ex3_o16[4])); + + //------------------------------------------------ + + assign ex3_sticky_or16[0] = (~(ex3_o16_b[0])); + assign ex3_sticky_or16[1] = (~(ex3_o16_b[1])); + assign ex3_sticky_or16[2] = (~(ex3_o16_b[2])); + assign ex3_sticky_or16[3] = (~(ex3_o16_b[3])); + assign ex3_sticky_or16[4] = (~(ex3_o16_b[4])); + + +endmodule diff --git a/dev/verilog/work/fu_alg_sh16.v b/dev/verilog/work/fu_alg_sh16.v new file mode 100755 index 0000000..a671040 --- /dev/null +++ b/dev/verilog/work/fu_alg_sh16.v @@ -0,0 +1,980 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + + `include "tri_a2o.vh" + +module fu_alg_sh16( + ex3_lvl3_shdcd000, + ex3_lvl3_shdcd016, + ex3_lvl3_shdcd032, + ex3_lvl3_shdcd048, + ex3_lvl3_shdcd064, + ex3_lvl3_shdcd080, + ex3_lvl3_shdcd096, + ex3_lvl3_shdcd112, + ex3_lvl3_shdcd128, + ex3_lvl3_shdcd144, + ex3_lvl3_shdcd160, + ex3_lvl3_shdcd192, + ex3_lvl3_shdcd208, + ex3_lvl3_shdcd224, + ex3_lvl3_shdcd240, + ex3_sel_special, + ex3_sh_lvl2, + ex3_sh16_162, + ex3_sh16_163, + ex3_sh_lvl3 +); + //--------- SHIFT CONTROLS ----------------- + input ex3_lvl3_shdcd000; + input ex3_lvl3_shdcd016; + input ex3_lvl3_shdcd032; + input ex3_lvl3_shdcd048; + input ex3_lvl3_shdcd064; + input ex3_lvl3_shdcd080; + input ex3_lvl3_shdcd096; + input ex3_lvl3_shdcd112; + input ex3_lvl3_shdcd128; + input ex3_lvl3_shdcd144; + input ex3_lvl3_shdcd160; + input ex3_lvl3_shdcd192; + input ex3_lvl3_shdcd208; + input ex3_lvl3_shdcd224; + input ex3_lvl3_shdcd240; + input ex3_sel_special; + + //--------- SHIFT DATA ----------------- + input [0:67] ex3_sh_lvl2; + + //-------- SHIFT OUTPUT --------------- + output ex3_sh16_162; + output ex3_sh16_163; + output [0:162] ex3_sh_lvl3; + + // ENTITY + + + parameter tiup = 1'b1; + parameter tidn = 1'b0; + + wire [0:162] ex3_sh16_r1_b; + wire [0:162] ex3_sh16_r2_b; + wire [0:162] ex3_sh16_r3_b; + + wire [99:162] ex3_special; + + wire cpx_spc_b; + wire cpx_000_b; + wire cpx_016_b; + wire cpx_032_b; + wire cpx_048_b; + wire cpx_064_b; + wire cpx_080_b; + wire cpx_096_b; + wire cpx_112_b; + wire cpx_128_b; + wire cpx_144_b; + wire cpx_160_b; + wire cpx_192_b; + wire cpx_208_b; + wire cpx_224_b; + wire cpx_240_b; + wire cp1_spc; + wire cp1_000; + wire cp1_016; + wire cp1_032; + wire cp1_048; + wire cp1_064; + wire cp1_080; + wire cp1_096; + wire cp1_112; + wire cp1_128; + wire cp1_144; + wire cp1_160; + wire cp1_192; + wire cp1_208; + wire cp1_224; + wire cp1_240; + wire cp2_spc; + wire cp2_000; + wire cp2_016; + wire cp2_032; + wire cp2_048; + wire cp2_064; + wire cp2_080; + wire cp2_096; + wire cp2_112; + wire cp2_128; + wire cp2_144; + wire cp2_208; + wire cp2_224; + wire cp2_240; + wire cp3_spc; + wire cp3_000; + wire cp3_016; + wire cp3_032; + wire cp3_048; + wire cp3_064; + wire cp3_080; + wire cp3_096; + wire cp3_112; + wire cp3_128; + wire cp3_224; + wire cp3_240; + wire cp4_spc; + wire cp4_000; + wire cp4_016; + wire cp4_032; + wire cp4_048; + wire cp4_064; + wire cp4_080; + wire cp4_096; + wire cp4_112; + wire cp4_240; + wire cp5_spc; + wire cp5_000; + wire cp5_016; + wire cp5_032; + wire cp5_048; + wire cp5_064; + wire cp5_080; + wire cp5_096; + wire ex3_sh16_r1_162_b; + wire ex3_sh16_r2_162_b; + wire ex3_sh16_r3_162_b; + wire ex3_sh16_r1_163_b; + wire ex3_sh16_r2_163_b; + wire ex3_sh16_r3_163_b; + + +////################################################################ +////# map block attributes +////################################################################ + +////#------------------------------------------------- +////# finish shifting +////#------------------------------------------------- +// this looks more like a 53:1 mux than a shifter to shrink it, and lower load on selects +// real implementation should be nand/nand/nor ... ?? integrate nor into latch ?? + + assign ex3_special[99:162] = ex3_sh_lvl2[0:63]; // just a rename + + ////#----------------------------------------------------------------- + ////# repower select signal + ////#----------------------------------------------------------------- + + + assign cpx_spc_b = (~ex3_sel_special); + assign cpx_000_b = (~ex3_lvl3_shdcd000); + assign cpx_016_b = (~ex3_lvl3_shdcd016); + assign cpx_032_b = (~ex3_lvl3_shdcd032); + assign cpx_048_b = (~ex3_lvl3_shdcd048); + assign cpx_064_b = (~ex3_lvl3_shdcd064); + assign cpx_080_b = (~ex3_lvl3_shdcd080); + assign cpx_096_b = (~ex3_lvl3_shdcd096); + assign cpx_112_b = (~ex3_lvl3_shdcd112); + assign cpx_128_b = (~ex3_lvl3_shdcd128); + assign cpx_144_b = (~ex3_lvl3_shdcd144); + assign cpx_160_b = (~ex3_lvl3_shdcd160); + assign cpx_192_b = (~ex3_lvl3_shdcd192); + assign cpx_208_b = (~ex3_lvl3_shdcd208); + assign cpx_224_b = (~ex3_lvl3_shdcd224); + assign cpx_240_b = (~ex3_lvl3_shdcd240); + + assign cp1_spc = (~cpx_spc_b); + assign cp1_000 = (~cpx_000_b); + assign cp1_016 = (~cpx_016_b); + assign cp1_032 = (~cpx_032_b); + assign cp1_048 = (~cpx_048_b); + assign cp1_064 = (~cpx_064_b); + assign cp1_080 = (~cpx_080_b); + assign cp1_096 = (~cpx_096_b); + assign cp1_112 = (~cpx_112_b); + assign cp1_128 = (~cpx_128_b); + assign cp1_144 = (~cpx_144_b); + assign cp1_160 = (~cpx_160_b); + assign cp1_192 = (~cpx_192_b); + assign cp1_208 = (~cpx_208_b); + assign cp1_224 = (~cpx_224_b); + assign cp1_240 = (~cpx_240_b); + + assign cp2_spc = (~cpx_spc_b); + assign cp2_000 = (~cpx_000_b); + assign cp2_016 = (~cpx_016_b); + assign cp2_032 = (~cpx_032_b); + assign cp2_048 = (~cpx_048_b); + assign cp2_064 = (~cpx_064_b); + assign cp2_080 = (~cpx_080_b); + assign cp2_096 = (~cpx_096_b); + assign cp2_112 = (~cpx_112_b); + assign cp2_128 = (~cpx_128_b); + assign cp2_144 = (~cpx_144_b); + assign cp2_208 = (~cpx_208_b); + assign cp2_224 = (~cpx_224_b); + assign cp2_240 = (~cpx_240_b); + + assign cp3_spc = (~cpx_spc_b); + assign cp3_000 = (~cpx_000_b); + assign cp3_016 = (~cpx_016_b); + assign cp3_032 = (~cpx_032_b); + assign cp3_048 = (~cpx_048_b); + assign cp3_064 = (~cpx_064_b); + assign cp3_080 = (~cpx_080_b); + assign cp3_096 = (~cpx_096_b); + assign cp3_112 = (~cpx_112_b); + assign cp3_128 = (~cpx_128_b); + assign cp3_224 = (~cpx_224_b); + assign cp3_240 = (~cpx_240_b); + + assign cp4_spc = (~cpx_spc_b); + assign cp4_000 = (~cpx_000_b); + assign cp4_016 = (~cpx_016_b); + assign cp4_032 = (~cpx_032_b); + assign cp4_048 = (~cpx_048_b); + assign cp4_064 = (~cpx_064_b); + assign cp4_080 = (~cpx_080_b); + assign cp4_096 = (~cpx_096_b); + assign cp4_112 = (~cpx_112_b); + assign cp4_240 = (~cpx_240_b); + + assign cp5_spc = (~cpx_spc_b); + assign cp5_000 = (~cpx_000_b); + assign cp5_016 = (~cpx_016_b); + assign cp5_032 = (~cpx_032_b); + assign cp5_048 = (~cpx_048_b); + assign cp5_064 = (~cpx_064_b); + assign cp5_080 = (~cpx_080_b); + assign cp5_096 = (~cpx_096_b); + + //------------------------------------------------------------------- + + assign ex3_sh16_r1_b[0] = (~((cp1_192 & ex3_sh_lvl2[64]) | (cp1_208 & ex3_sh_lvl2[48]))); + assign ex3_sh16_r1_b[1] = (~((cp1_192 & ex3_sh_lvl2[65]) | (cp1_208 & ex3_sh_lvl2[49]))); + assign ex3_sh16_r1_b[2] = (~((cp1_192 & ex3_sh_lvl2[66]) | (cp1_208 & ex3_sh_lvl2[50]))); + assign ex3_sh16_r1_b[3] = (~((cp1_192 & ex3_sh_lvl2[67]) | (cp1_208 & ex3_sh_lvl2[51]))); + assign ex3_sh16_r1_b[4] = (~(cp1_208 & ex3_sh_lvl2[52])); + assign ex3_sh16_r1_b[5] = (~(cp1_208 & ex3_sh_lvl2[53])); + assign ex3_sh16_r1_b[6] = (~(cp1_208 & ex3_sh_lvl2[54])); + assign ex3_sh16_r1_b[7] = (~(cp1_208 & ex3_sh_lvl2[55])); + assign ex3_sh16_r1_b[8] = (~(cp1_208 & ex3_sh_lvl2[56])); + assign ex3_sh16_r1_b[9] = (~(cp1_208 & ex3_sh_lvl2[57])); + assign ex3_sh16_r1_b[10] = (~(cp1_208 & ex3_sh_lvl2[58])); + assign ex3_sh16_r1_b[11] = (~(cp1_208 & ex3_sh_lvl2[59])); + assign ex3_sh16_r1_b[12] = (~(cp1_208 & ex3_sh_lvl2[60])); + assign ex3_sh16_r1_b[13] = (~(cp1_208 & ex3_sh_lvl2[61])); + assign ex3_sh16_r1_b[14] = (~(cp1_208 & ex3_sh_lvl2[62])); + assign ex3_sh16_r1_b[15] = (~(cp1_208 & ex3_sh_lvl2[63])); + + assign ex3_sh16_r1_b[16] = (~((cp2_208 & ex3_sh_lvl2[64]) | (cp2_224 & ex3_sh_lvl2[48]))); + assign ex3_sh16_r1_b[17] = (~((cp2_208 & ex3_sh_lvl2[65]) | (cp2_224 & ex3_sh_lvl2[49]))); + assign ex3_sh16_r1_b[18] = (~((cp2_208 & ex3_sh_lvl2[66]) | (cp2_224 & ex3_sh_lvl2[50]))); + assign ex3_sh16_r1_b[19] = (~((cp2_208 & ex3_sh_lvl2[67]) | (cp2_224 & ex3_sh_lvl2[51]))); + assign ex3_sh16_r1_b[20] = (~(cp2_224 & ex3_sh_lvl2[52])); + assign ex3_sh16_r1_b[21] = (~(cp2_224 & ex3_sh_lvl2[53])); + assign ex3_sh16_r1_b[22] = (~(cp2_224 & ex3_sh_lvl2[54])); + assign ex3_sh16_r1_b[23] = (~(cp2_224 & ex3_sh_lvl2[55])); + assign ex3_sh16_r1_b[24] = (~(cp2_224 & ex3_sh_lvl2[56])); + assign ex3_sh16_r1_b[25] = (~(cp2_224 & ex3_sh_lvl2[57])); + assign ex3_sh16_r1_b[26] = (~(cp2_224 & ex3_sh_lvl2[58])); + assign ex3_sh16_r1_b[27] = (~(cp2_224 & ex3_sh_lvl2[59])); + assign ex3_sh16_r1_b[28] = (~(cp2_224 & ex3_sh_lvl2[60])); + assign ex3_sh16_r1_b[29] = (~(cp2_224 & ex3_sh_lvl2[61])); + assign ex3_sh16_r1_b[30] = (~(cp2_224 & ex3_sh_lvl2[62])); + assign ex3_sh16_r1_b[31] = (~(cp2_224 & ex3_sh_lvl2[63])); + + assign ex3_sh16_r1_b[32] = (~((cp3_224 & ex3_sh_lvl2[64]) | (cp3_240 & ex3_sh_lvl2[48]))); + assign ex3_sh16_r1_b[33] = (~((cp3_224 & ex3_sh_lvl2[65]) | (cp3_240 & ex3_sh_lvl2[49]))); + assign ex3_sh16_r1_b[34] = (~((cp3_224 & ex3_sh_lvl2[66]) | (cp3_240 & ex3_sh_lvl2[50]))); + assign ex3_sh16_r1_b[35] = (~((cp3_224 & ex3_sh_lvl2[67]) | (cp3_240 & ex3_sh_lvl2[51]))); + assign ex3_sh16_r1_b[36] = (~(cp3_240 & ex3_sh_lvl2[52])); + assign ex3_sh16_r1_b[37] = (~(cp3_240 & ex3_sh_lvl2[53])); + assign ex3_sh16_r1_b[38] = (~(cp3_240 & ex3_sh_lvl2[54])); + assign ex3_sh16_r1_b[39] = (~(cp3_240 & ex3_sh_lvl2[55])); + assign ex3_sh16_r1_b[40] = (~(cp3_240 & ex3_sh_lvl2[56])); + assign ex3_sh16_r1_b[41] = (~(cp3_240 & ex3_sh_lvl2[57])); + assign ex3_sh16_r1_b[42] = (~(cp3_240 & ex3_sh_lvl2[58])); + assign ex3_sh16_r1_b[43] = (~(cp3_240 & ex3_sh_lvl2[59])); + assign ex3_sh16_r1_b[44] = (~(cp3_240 & ex3_sh_lvl2[60])); + assign ex3_sh16_r1_b[45] = (~(cp3_240 & ex3_sh_lvl2[61])); + assign ex3_sh16_r1_b[46] = (~(cp3_240 & ex3_sh_lvl2[62])); + assign ex3_sh16_r1_b[47] = (~(cp3_240 & ex3_sh_lvl2[63])); + + assign ex3_sh16_r1_b[48] = (~((cp4_240 & ex3_sh_lvl2[64]) | (cp4_000 & ex3_sh_lvl2[48]))); + assign ex3_sh16_r1_b[49] = (~((cp4_240 & ex3_sh_lvl2[65]) | (cp4_000 & ex3_sh_lvl2[49]))); + assign ex3_sh16_r1_b[50] = (~((cp4_240 & ex3_sh_lvl2[66]) | (cp4_000 & ex3_sh_lvl2[50]))); + assign ex3_sh16_r1_b[51] = (~((cp4_240 & ex3_sh_lvl2[67]) | (cp4_000 & ex3_sh_lvl2[51]))); + assign ex3_sh16_r1_b[52] = (~(cp4_000 & ex3_sh_lvl2[52])); + assign ex3_sh16_r1_b[53] = (~(cp4_000 & ex3_sh_lvl2[53])); + assign ex3_sh16_r1_b[54] = (~(cp4_000 & ex3_sh_lvl2[54])); + assign ex3_sh16_r1_b[55] = (~(cp4_000 & ex3_sh_lvl2[55])); + assign ex3_sh16_r1_b[56] = (~(cp4_000 & ex3_sh_lvl2[56])); + assign ex3_sh16_r1_b[57] = (~(cp4_000 & ex3_sh_lvl2[57])); + assign ex3_sh16_r1_b[58] = (~(cp4_000 & ex3_sh_lvl2[58])); + assign ex3_sh16_r1_b[59] = (~(cp4_000 & ex3_sh_lvl2[59])); + assign ex3_sh16_r1_b[60] = (~(cp4_000 & ex3_sh_lvl2[60])); + assign ex3_sh16_r1_b[61] = (~(cp4_000 & ex3_sh_lvl2[61])); + assign ex3_sh16_r1_b[62] = (~(cp4_000 & ex3_sh_lvl2[62])); + assign ex3_sh16_r1_b[63] = (~(cp4_000 & ex3_sh_lvl2[63])); + + assign ex3_sh16_r1_b[64] = (~((cp5_000 & ex3_sh_lvl2[64]) | (cp4_016 & ex3_sh_lvl2[48]))); + assign ex3_sh16_r1_b[65] = (~((cp5_000 & ex3_sh_lvl2[65]) | (cp4_016 & ex3_sh_lvl2[49]))); + assign ex3_sh16_r1_b[66] = (~((cp5_000 & ex3_sh_lvl2[66]) | (cp4_016 & ex3_sh_lvl2[50]))); + assign ex3_sh16_r1_b[67] = (~((cp5_000 & ex3_sh_lvl2[67]) | (cp4_016 & ex3_sh_lvl2[51]))); + assign ex3_sh16_r1_b[68] = (~(cp4_016 & ex3_sh_lvl2[52])); + assign ex3_sh16_r1_b[69] = (~(cp4_016 & ex3_sh_lvl2[53])); + assign ex3_sh16_r1_b[70] = (~(cp4_016 & ex3_sh_lvl2[54])); + assign ex3_sh16_r1_b[71] = (~(cp4_016 & ex3_sh_lvl2[55])); + assign ex3_sh16_r1_b[72] = (~(cp4_016 & ex3_sh_lvl2[56])); + assign ex3_sh16_r1_b[73] = (~(cp4_016 & ex3_sh_lvl2[57])); + assign ex3_sh16_r1_b[74] = (~(cp4_016 & ex3_sh_lvl2[58])); + assign ex3_sh16_r1_b[75] = (~(cp4_016 & ex3_sh_lvl2[59])); + assign ex3_sh16_r1_b[76] = (~(cp4_016 & ex3_sh_lvl2[60])); + assign ex3_sh16_r1_b[77] = (~(cp4_016 & ex3_sh_lvl2[61])); + assign ex3_sh16_r1_b[78] = (~(cp4_016 & ex3_sh_lvl2[62])); + assign ex3_sh16_r1_b[79] = (~(cp4_016 & ex3_sh_lvl2[63])); + + assign ex3_sh16_r1_b[80] = (~((cp5_016 & ex3_sh_lvl2[64]) | (cp4_032 & ex3_sh_lvl2[48]))); + assign ex3_sh16_r1_b[81] = (~((cp5_016 & ex3_sh_lvl2[65]) | (cp4_032 & ex3_sh_lvl2[49]))); + assign ex3_sh16_r1_b[82] = (~((cp5_016 & ex3_sh_lvl2[66]) | (cp4_032 & ex3_sh_lvl2[50]))); + assign ex3_sh16_r1_b[83] = (~((cp5_016 & ex3_sh_lvl2[67]) | (cp4_032 & ex3_sh_lvl2[51]))); + assign ex3_sh16_r1_b[84] = (~(cp4_032 & ex3_sh_lvl2[52])); + assign ex3_sh16_r1_b[85] = (~(cp4_032 & ex3_sh_lvl2[53])); + assign ex3_sh16_r1_b[86] = (~(cp4_032 & ex3_sh_lvl2[54])); + assign ex3_sh16_r1_b[87] = (~(cp4_032 & ex3_sh_lvl2[55])); + assign ex3_sh16_r1_b[88] = (~(cp4_032 & ex3_sh_lvl2[56])); + assign ex3_sh16_r1_b[89] = (~(cp4_032 & ex3_sh_lvl2[57])); + assign ex3_sh16_r1_b[90] = (~(cp4_032 & ex3_sh_lvl2[58])); + assign ex3_sh16_r1_b[91] = (~(cp4_032 & ex3_sh_lvl2[59])); + assign ex3_sh16_r1_b[92] = (~(cp4_032 & ex3_sh_lvl2[60])); + assign ex3_sh16_r1_b[93] = (~(cp4_032 & ex3_sh_lvl2[61])); + assign ex3_sh16_r1_b[94] = (~(cp4_032 & ex3_sh_lvl2[62])); + assign ex3_sh16_r1_b[95] = (~(cp4_032 & ex3_sh_lvl2[63])); + + assign ex3_sh16_r1_b[96] = (~((cp5_032 & ex3_sh_lvl2[64]) | (cp4_048 & ex3_sh_lvl2[48]))); + assign ex3_sh16_r1_b[97] = (~((cp5_032 & ex3_sh_lvl2[65]) | (cp4_048 & ex3_sh_lvl2[49]))); + assign ex3_sh16_r1_b[98] = (~((cp5_032 & ex3_sh_lvl2[66]) | (cp4_048 & ex3_sh_lvl2[50]))); + assign ex3_sh16_r1_b[99] = (~((cp5_032 & ex3_sh_lvl2[67]) | (cp4_048 & ex3_sh_lvl2[51]))); + assign ex3_sh16_r1_b[100] = (~(cp4_048 & ex3_sh_lvl2[52])); + assign ex3_sh16_r1_b[101] = (~(cp4_048 & ex3_sh_lvl2[53])); + assign ex3_sh16_r1_b[102] = (~(cp4_048 & ex3_sh_lvl2[54])); + assign ex3_sh16_r1_b[103] = (~(cp4_048 & ex3_sh_lvl2[55])); + assign ex3_sh16_r1_b[104] = (~(cp4_048 & ex3_sh_lvl2[56])); + assign ex3_sh16_r1_b[105] = (~(cp4_048 & ex3_sh_lvl2[57])); + assign ex3_sh16_r1_b[106] = (~(cp4_048 & ex3_sh_lvl2[58])); + assign ex3_sh16_r1_b[107] = (~(cp4_048 & ex3_sh_lvl2[59])); + assign ex3_sh16_r1_b[108] = (~(cp4_048 & ex3_sh_lvl2[60])); + assign ex3_sh16_r1_b[109] = (~(cp4_048 & ex3_sh_lvl2[61])); + assign ex3_sh16_r1_b[110] = (~(cp4_048 & ex3_sh_lvl2[62])); + assign ex3_sh16_r1_b[111] = (~(cp4_048 & ex3_sh_lvl2[63])); + + assign ex3_sh16_r1_b[112] = (~((cp5_048 & ex3_sh_lvl2[64]) | (cp4_064 & ex3_sh_lvl2[48]))); + assign ex3_sh16_r1_b[113] = (~((cp5_048 & ex3_sh_lvl2[65]) | (cp4_064 & ex3_sh_lvl2[49]))); + assign ex3_sh16_r1_b[114] = (~((cp5_048 & ex3_sh_lvl2[66]) | (cp4_064 & ex3_sh_lvl2[50]))); + assign ex3_sh16_r1_b[115] = (~((cp5_048 & ex3_sh_lvl2[67]) | (cp4_064 & ex3_sh_lvl2[51]))); + assign ex3_sh16_r1_b[116] = (~(cp4_064 & ex3_sh_lvl2[52])); + assign ex3_sh16_r1_b[117] = (~(cp4_064 & ex3_sh_lvl2[53])); + assign ex3_sh16_r1_b[118] = (~(cp4_064 & ex3_sh_lvl2[54])); + assign ex3_sh16_r1_b[119] = (~(cp4_064 & ex3_sh_lvl2[55])); + assign ex3_sh16_r1_b[120] = (~(cp4_064 & ex3_sh_lvl2[56])); + assign ex3_sh16_r1_b[121] = (~(cp4_064 & ex3_sh_lvl2[57])); + assign ex3_sh16_r1_b[122] = (~(cp4_064 & ex3_sh_lvl2[58])); + assign ex3_sh16_r1_b[123] = (~(cp4_064 & ex3_sh_lvl2[59])); + assign ex3_sh16_r1_b[124] = (~(cp4_064 & ex3_sh_lvl2[60])); + assign ex3_sh16_r1_b[125] = (~(cp4_064 & ex3_sh_lvl2[61])); + assign ex3_sh16_r1_b[126] = (~(cp4_064 & ex3_sh_lvl2[62])); + assign ex3_sh16_r1_b[127] = (~(cp4_064 & ex3_sh_lvl2[63])); + + assign ex3_sh16_r1_b[128] = (~((cp5_064 & ex3_sh_lvl2[64]) | (cp4_080 & ex3_sh_lvl2[48]))); + assign ex3_sh16_r1_b[129] = (~((cp5_064 & ex3_sh_lvl2[65]) | (cp4_080 & ex3_sh_lvl2[49]))); + assign ex3_sh16_r1_b[130] = (~((cp5_064 & ex3_sh_lvl2[66]) | (cp4_080 & ex3_sh_lvl2[50]))); + assign ex3_sh16_r1_b[131] = (~((cp5_064 & ex3_sh_lvl2[67]) | (cp4_080 & ex3_sh_lvl2[51]))); + assign ex3_sh16_r1_b[132] = (~(cp4_080 & ex3_sh_lvl2[52])); + assign ex3_sh16_r1_b[133] = (~(cp4_080 & ex3_sh_lvl2[53])); + assign ex3_sh16_r1_b[134] = (~(cp4_080 & ex3_sh_lvl2[54])); + assign ex3_sh16_r1_b[135] = (~(cp4_080 & ex3_sh_lvl2[55])); + assign ex3_sh16_r1_b[136] = (~(cp4_080 & ex3_sh_lvl2[56])); + assign ex3_sh16_r1_b[137] = (~(cp4_080 & ex3_sh_lvl2[57])); + assign ex3_sh16_r1_b[138] = (~(cp4_080 & ex3_sh_lvl2[58])); + assign ex3_sh16_r1_b[139] = (~(cp4_080 & ex3_sh_lvl2[59])); + assign ex3_sh16_r1_b[140] = (~(cp4_080 & ex3_sh_lvl2[60])); + assign ex3_sh16_r1_b[141] = (~(cp4_080 & ex3_sh_lvl2[61])); + assign ex3_sh16_r1_b[142] = (~(cp4_080 & ex3_sh_lvl2[62])); + assign ex3_sh16_r1_b[143] = (~(cp4_080 & ex3_sh_lvl2[63])); + + assign ex3_sh16_r1_b[144] = (~((cp5_080 & ex3_sh_lvl2[64]) | (cp4_096 & ex3_sh_lvl2[48]))); + assign ex3_sh16_r1_b[145] = (~((cp5_080 & ex3_sh_lvl2[65]) | (cp4_096 & ex3_sh_lvl2[49]))); + assign ex3_sh16_r1_b[146] = (~((cp5_080 & ex3_sh_lvl2[66]) | (cp4_096 & ex3_sh_lvl2[50]))); + assign ex3_sh16_r1_b[147] = (~((cp5_080 & ex3_sh_lvl2[67]) | (cp4_096 & ex3_sh_lvl2[51]))); + assign ex3_sh16_r1_b[148] = (~(cp4_096 & ex3_sh_lvl2[52])); + assign ex3_sh16_r1_b[149] = (~(cp4_096 & ex3_sh_lvl2[53])); + assign ex3_sh16_r1_b[150] = (~(cp4_096 & ex3_sh_lvl2[54])); + assign ex3_sh16_r1_b[151] = (~(cp4_096 & ex3_sh_lvl2[55])); + assign ex3_sh16_r1_b[152] = (~(cp4_096 & ex3_sh_lvl2[56])); + assign ex3_sh16_r1_b[153] = (~(cp4_096 & ex3_sh_lvl2[57])); + assign ex3_sh16_r1_b[154] = (~(cp4_096 & ex3_sh_lvl2[58])); + assign ex3_sh16_r1_b[155] = (~(cp4_096 & ex3_sh_lvl2[59])); + assign ex3_sh16_r1_b[156] = (~(cp4_096 & ex3_sh_lvl2[60])); + assign ex3_sh16_r1_b[157] = (~(cp4_096 & ex3_sh_lvl2[61])); + assign ex3_sh16_r1_b[158] = (~(cp4_096 & ex3_sh_lvl2[62])); + assign ex3_sh16_r1_b[159] = (~(cp4_096 & ex3_sh_lvl2[63])); + + assign ex3_sh16_r1_b[160] = (~((cp5_096 & ex3_sh_lvl2[64]) | (cp4_112 & ex3_sh_lvl2[48]))); + assign ex3_sh16_r1_b[161] = (~((cp5_096 & ex3_sh_lvl2[65]) | (cp4_112 & ex3_sh_lvl2[49]))); + assign ex3_sh16_r1_b[162] = (~((cp5_096 & ex3_sh_lvl2[66]) | (cp4_112 & ex3_sh_lvl2[50]))); + + assign ex3_sh16_r2_b[0] = (~((cp1_224 & ex3_sh_lvl2[32]) | (cp1_240 & ex3_sh_lvl2[16]))); + assign ex3_sh16_r2_b[1] = (~((cp1_224 & ex3_sh_lvl2[33]) | (cp1_240 & ex3_sh_lvl2[17]))); + assign ex3_sh16_r2_b[2] = (~((cp1_224 & ex3_sh_lvl2[34]) | (cp1_240 & ex3_sh_lvl2[18]))); + assign ex3_sh16_r2_b[3] = (~((cp1_224 & ex3_sh_lvl2[35]) | (cp1_240 & ex3_sh_lvl2[19]))); + assign ex3_sh16_r2_b[4] = (~((cp1_224 & ex3_sh_lvl2[36]) | (cp1_240 & ex3_sh_lvl2[20]))); + assign ex3_sh16_r2_b[5] = (~((cp1_224 & ex3_sh_lvl2[37]) | (cp1_240 & ex3_sh_lvl2[21]))); + assign ex3_sh16_r2_b[6] = (~((cp1_224 & ex3_sh_lvl2[38]) | (cp1_240 & ex3_sh_lvl2[22]))); + assign ex3_sh16_r2_b[7] = (~((cp1_224 & ex3_sh_lvl2[39]) | (cp1_240 & ex3_sh_lvl2[23]))); + assign ex3_sh16_r2_b[8] = (~((cp1_224 & ex3_sh_lvl2[40]) | (cp1_240 & ex3_sh_lvl2[24]))); + assign ex3_sh16_r2_b[9] = (~((cp1_224 & ex3_sh_lvl2[41]) | (cp1_240 & ex3_sh_lvl2[25]))); + assign ex3_sh16_r2_b[10] = (~((cp1_224 & ex3_sh_lvl2[42]) | (cp1_240 & ex3_sh_lvl2[26]))); + assign ex3_sh16_r2_b[11] = (~((cp1_224 & ex3_sh_lvl2[43]) | (cp1_240 & ex3_sh_lvl2[27]))); + assign ex3_sh16_r2_b[12] = (~((cp1_224 & ex3_sh_lvl2[44]) | (cp1_240 & ex3_sh_lvl2[28]))); + assign ex3_sh16_r2_b[13] = (~((cp1_224 & ex3_sh_lvl2[45]) | (cp1_240 & ex3_sh_lvl2[29]))); + assign ex3_sh16_r2_b[14] = (~((cp1_224 & ex3_sh_lvl2[46]) | (cp1_240 & ex3_sh_lvl2[30]))); + assign ex3_sh16_r2_b[15] = (~((cp1_224 & ex3_sh_lvl2[47]) | (cp1_240 & ex3_sh_lvl2[31]))); + + assign ex3_sh16_r2_b[16] = (~((cp2_240 & ex3_sh_lvl2[32]) | (cp2_000 & ex3_sh_lvl2[16]))); + assign ex3_sh16_r2_b[17] = (~((cp2_240 & ex3_sh_lvl2[33]) | (cp2_000 & ex3_sh_lvl2[17]))); + assign ex3_sh16_r2_b[18] = (~((cp2_240 & ex3_sh_lvl2[34]) | (cp2_000 & ex3_sh_lvl2[18]))); + assign ex3_sh16_r2_b[19] = (~((cp2_240 & ex3_sh_lvl2[35]) | (cp2_000 & ex3_sh_lvl2[19]))); + assign ex3_sh16_r2_b[20] = (~((cp2_240 & ex3_sh_lvl2[36]) | (cp2_000 & ex3_sh_lvl2[20]))); + assign ex3_sh16_r2_b[21] = (~((cp2_240 & ex3_sh_lvl2[37]) | (cp2_000 & ex3_sh_lvl2[21]))); + assign ex3_sh16_r2_b[22] = (~((cp2_240 & ex3_sh_lvl2[38]) | (cp2_000 & ex3_sh_lvl2[22]))); + assign ex3_sh16_r2_b[23] = (~((cp2_240 & ex3_sh_lvl2[39]) | (cp2_000 & ex3_sh_lvl2[23]))); + assign ex3_sh16_r2_b[24] = (~((cp2_240 & ex3_sh_lvl2[40]) | (cp2_000 & ex3_sh_lvl2[24]))); + assign ex3_sh16_r2_b[25] = (~((cp2_240 & ex3_sh_lvl2[41]) | (cp2_000 & ex3_sh_lvl2[25]))); + assign ex3_sh16_r2_b[26] = (~((cp2_240 & ex3_sh_lvl2[42]) | (cp2_000 & ex3_sh_lvl2[26]))); + assign ex3_sh16_r2_b[27] = (~((cp2_240 & ex3_sh_lvl2[43]) | (cp2_000 & ex3_sh_lvl2[27]))); + assign ex3_sh16_r2_b[28] = (~((cp2_240 & ex3_sh_lvl2[44]) | (cp2_000 & ex3_sh_lvl2[28]))); + assign ex3_sh16_r2_b[29] = (~((cp2_240 & ex3_sh_lvl2[45]) | (cp2_000 & ex3_sh_lvl2[29]))); + assign ex3_sh16_r2_b[30] = (~((cp2_240 & ex3_sh_lvl2[46]) | (cp2_000 & ex3_sh_lvl2[30]))); + assign ex3_sh16_r2_b[31] = (~((cp2_240 & ex3_sh_lvl2[47]) | (cp2_000 & ex3_sh_lvl2[31]))); + + assign ex3_sh16_r2_b[32] = (~((cp3_000 & ex3_sh_lvl2[32]) | (cp2_016 & ex3_sh_lvl2[16]))); + assign ex3_sh16_r2_b[33] = (~((cp3_000 & ex3_sh_lvl2[33]) | (cp2_016 & ex3_sh_lvl2[17]))); + assign ex3_sh16_r2_b[34] = (~((cp3_000 & ex3_sh_lvl2[34]) | (cp2_016 & ex3_sh_lvl2[18]))); + assign ex3_sh16_r2_b[35] = (~((cp3_000 & ex3_sh_lvl2[35]) | (cp2_016 & ex3_sh_lvl2[19]))); + assign ex3_sh16_r2_b[36] = (~((cp3_000 & ex3_sh_lvl2[36]) | (cp2_016 & ex3_sh_lvl2[20]))); + assign ex3_sh16_r2_b[37] = (~((cp3_000 & ex3_sh_lvl2[37]) | (cp2_016 & ex3_sh_lvl2[21]))); + assign ex3_sh16_r2_b[38] = (~((cp3_000 & ex3_sh_lvl2[38]) | (cp2_016 & ex3_sh_lvl2[22]))); + assign ex3_sh16_r2_b[39] = (~((cp3_000 & ex3_sh_lvl2[39]) | (cp2_016 & ex3_sh_lvl2[23]))); + assign ex3_sh16_r2_b[40] = (~((cp3_000 & ex3_sh_lvl2[40]) | (cp2_016 & ex3_sh_lvl2[24]))); + assign ex3_sh16_r2_b[41] = (~((cp3_000 & ex3_sh_lvl2[41]) | (cp2_016 & ex3_sh_lvl2[25]))); + assign ex3_sh16_r2_b[42] = (~((cp3_000 & ex3_sh_lvl2[42]) | (cp2_016 & ex3_sh_lvl2[26]))); + assign ex3_sh16_r2_b[43] = (~((cp3_000 & ex3_sh_lvl2[43]) | (cp2_016 & ex3_sh_lvl2[27]))); + assign ex3_sh16_r2_b[44] = (~((cp3_000 & ex3_sh_lvl2[44]) | (cp2_016 & ex3_sh_lvl2[28]))); + assign ex3_sh16_r2_b[45] = (~((cp3_000 & ex3_sh_lvl2[45]) | (cp2_016 & ex3_sh_lvl2[29]))); + assign ex3_sh16_r2_b[46] = (~((cp3_000 & ex3_sh_lvl2[46]) | (cp2_016 & ex3_sh_lvl2[30]))); + assign ex3_sh16_r2_b[47] = (~((cp3_000 & ex3_sh_lvl2[47]) | (cp2_016 & ex3_sh_lvl2[31]))); + + assign ex3_sh16_r2_b[48] = (~((cp3_016 & ex3_sh_lvl2[32]) | (cp2_032 & ex3_sh_lvl2[16]))); + assign ex3_sh16_r2_b[49] = (~((cp3_016 & ex3_sh_lvl2[33]) | (cp2_032 & ex3_sh_lvl2[17]))); + assign ex3_sh16_r2_b[50] = (~((cp3_016 & ex3_sh_lvl2[34]) | (cp2_032 & ex3_sh_lvl2[18]))); + assign ex3_sh16_r2_b[51] = (~((cp3_016 & ex3_sh_lvl2[35]) | (cp2_032 & ex3_sh_lvl2[19]))); + assign ex3_sh16_r2_b[52] = (~((cp3_016 & ex3_sh_lvl2[36]) | (cp2_032 & ex3_sh_lvl2[20]))); + assign ex3_sh16_r2_b[53] = (~((cp3_016 & ex3_sh_lvl2[37]) | (cp2_032 & ex3_sh_lvl2[21]))); + assign ex3_sh16_r2_b[54] = (~((cp3_016 & ex3_sh_lvl2[38]) | (cp2_032 & ex3_sh_lvl2[22]))); + assign ex3_sh16_r2_b[55] = (~((cp3_016 & ex3_sh_lvl2[39]) | (cp2_032 & ex3_sh_lvl2[23]))); + assign ex3_sh16_r2_b[56] = (~((cp3_016 & ex3_sh_lvl2[40]) | (cp2_032 & ex3_sh_lvl2[24]))); + assign ex3_sh16_r2_b[57] = (~((cp3_016 & ex3_sh_lvl2[41]) | (cp2_032 & ex3_sh_lvl2[25]))); + assign ex3_sh16_r2_b[58] = (~((cp3_016 & ex3_sh_lvl2[42]) | (cp2_032 & ex3_sh_lvl2[26]))); + assign ex3_sh16_r2_b[59] = (~((cp3_016 & ex3_sh_lvl2[43]) | (cp2_032 & ex3_sh_lvl2[27]))); + assign ex3_sh16_r2_b[60] = (~((cp3_016 & ex3_sh_lvl2[44]) | (cp2_032 & ex3_sh_lvl2[28]))); + assign ex3_sh16_r2_b[61] = (~((cp3_016 & ex3_sh_lvl2[45]) | (cp2_032 & ex3_sh_lvl2[29]))); + assign ex3_sh16_r2_b[62] = (~((cp3_016 & ex3_sh_lvl2[46]) | (cp2_032 & ex3_sh_lvl2[30]))); + assign ex3_sh16_r2_b[63] = (~((cp3_016 & ex3_sh_lvl2[47]) | (cp2_032 & ex3_sh_lvl2[31]))); + + assign ex3_sh16_r2_b[64] = (~((cp3_032 & ex3_sh_lvl2[32]) | (cp2_048 & ex3_sh_lvl2[16]))); + assign ex3_sh16_r2_b[65] = (~((cp3_032 & ex3_sh_lvl2[33]) | (cp2_048 & ex3_sh_lvl2[17]))); + assign ex3_sh16_r2_b[66] = (~((cp3_032 & ex3_sh_lvl2[34]) | (cp2_048 & ex3_sh_lvl2[18]))); + assign ex3_sh16_r2_b[67] = (~((cp3_032 & ex3_sh_lvl2[35]) | (cp2_048 & ex3_sh_lvl2[19]))); + assign ex3_sh16_r2_b[68] = (~((cp3_032 & ex3_sh_lvl2[36]) | (cp2_048 & ex3_sh_lvl2[20]))); + assign ex3_sh16_r2_b[69] = (~((cp3_032 & ex3_sh_lvl2[37]) | (cp2_048 & ex3_sh_lvl2[21]))); + assign ex3_sh16_r2_b[70] = (~((cp3_032 & ex3_sh_lvl2[38]) | (cp2_048 & ex3_sh_lvl2[22]))); + assign ex3_sh16_r2_b[71] = (~((cp3_032 & ex3_sh_lvl2[39]) | (cp2_048 & ex3_sh_lvl2[23]))); + assign ex3_sh16_r2_b[72] = (~((cp3_032 & ex3_sh_lvl2[40]) | (cp2_048 & ex3_sh_lvl2[24]))); + assign ex3_sh16_r2_b[73] = (~((cp3_032 & ex3_sh_lvl2[41]) | (cp2_048 & ex3_sh_lvl2[25]))); + assign ex3_sh16_r2_b[74] = (~((cp3_032 & ex3_sh_lvl2[42]) | (cp2_048 & ex3_sh_lvl2[26]))); + assign ex3_sh16_r2_b[75] = (~((cp3_032 & ex3_sh_lvl2[43]) | (cp2_048 & ex3_sh_lvl2[27]))); + assign ex3_sh16_r2_b[76] = (~((cp3_032 & ex3_sh_lvl2[44]) | (cp2_048 & ex3_sh_lvl2[28]))); + assign ex3_sh16_r2_b[77] = (~((cp3_032 & ex3_sh_lvl2[45]) | (cp2_048 & ex3_sh_lvl2[29]))); + assign ex3_sh16_r2_b[78] = (~((cp3_032 & ex3_sh_lvl2[46]) | (cp2_048 & ex3_sh_lvl2[30]))); + assign ex3_sh16_r2_b[79] = (~((cp3_032 & ex3_sh_lvl2[47]) | (cp2_048 & ex3_sh_lvl2[31]))); + + assign ex3_sh16_r2_b[80] = (~((cp3_048 & ex3_sh_lvl2[32]) | (cp2_064 & ex3_sh_lvl2[16]))); + assign ex3_sh16_r2_b[81] = (~((cp3_048 & ex3_sh_lvl2[33]) | (cp2_064 & ex3_sh_lvl2[17]))); + assign ex3_sh16_r2_b[82] = (~((cp3_048 & ex3_sh_lvl2[34]) | (cp2_064 & ex3_sh_lvl2[18]))); + assign ex3_sh16_r2_b[83] = (~((cp3_048 & ex3_sh_lvl2[35]) | (cp2_064 & ex3_sh_lvl2[19]))); + assign ex3_sh16_r2_b[84] = (~((cp3_048 & ex3_sh_lvl2[36]) | (cp2_064 & ex3_sh_lvl2[20]))); + assign ex3_sh16_r2_b[85] = (~((cp3_048 & ex3_sh_lvl2[37]) | (cp2_064 & ex3_sh_lvl2[21]))); + assign ex3_sh16_r2_b[86] = (~((cp3_048 & ex3_sh_lvl2[38]) | (cp2_064 & ex3_sh_lvl2[22]))); + assign ex3_sh16_r2_b[87] = (~((cp3_048 & ex3_sh_lvl2[39]) | (cp2_064 & ex3_sh_lvl2[23]))); + assign ex3_sh16_r2_b[88] = (~((cp3_048 & ex3_sh_lvl2[40]) | (cp2_064 & ex3_sh_lvl2[24]))); + assign ex3_sh16_r2_b[89] = (~((cp3_048 & ex3_sh_lvl2[41]) | (cp2_064 & ex3_sh_lvl2[25]))); + assign ex3_sh16_r2_b[90] = (~((cp3_048 & ex3_sh_lvl2[42]) | (cp2_064 & ex3_sh_lvl2[26]))); + assign ex3_sh16_r2_b[91] = (~((cp3_048 & ex3_sh_lvl2[43]) | (cp2_064 & ex3_sh_lvl2[27]))); + assign ex3_sh16_r2_b[92] = (~((cp3_048 & ex3_sh_lvl2[44]) | (cp2_064 & ex3_sh_lvl2[28]))); + assign ex3_sh16_r2_b[93] = (~((cp3_048 & ex3_sh_lvl2[45]) | (cp2_064 & ex3_sh_lvl2[29]))); + assign ex3_sh16_r2_b[94] = (~((cp3_048 & ex3_sh_lvl2[46]) | (cp2_064 & ex3_sh_lvl2[30]))); + assign ex3_sh16_r2_b[95] = (~((cp3_048 & ex3_sh_lvl2[47]) | (cp2_064 & ex3_sh_lvl2[31]))); + + assign ex3_sh16_r2_b[96] = (~((cp3_064 & ex3_sh_lvl2[32]) | (cp2_080 & ex3_sh_lvl2[16]))); + assign ex3_sh16_r2_b[97] = (~((cp3_064 & ex3_sh_lvl2[33]) | (cp2_080 & ex3_sh_lvl2[17]))); + assign ex3_sh16_r2_b[98] = (~((cp3_064 & ex3_sh_lvl2[34]) | (cp2_080 & ex3_sh_lvl2[18]))); + assign ex3_sh16_r2_b[99] = (~((cp3_064 & ex3_sh_lvl2[35]) | (cp2_080 & ex3_sh_lvl2[19]))); + assign ex3_sh16_r2_b[100] = (~((cp3_064 & ex3_sh_lvl2[36]) | (cp2_080 & ex3_sh_lvl2[20]))); + assign ex3_sh16_r2_b[101] = (~((cp3_064 & ex3_sh_lvl2[37]) | (cp2_080 & ex3_sh_lvl2[21]))); + assign ex3_sh16_r2_b[102] = (~((cp3_064 & ex3_sh_lvl2[38]) | (cp2_080 & ex3_sh_lvl2[22]))); + assign ex3_sh16_r2_b[103] = (~((cp3_064 & ex3_sh_lvl2[39]) | (cp2_080 & ex3_sh_lvl2[23]))); + assign ex3_sh16_r2_b[104] = (~((cp3_064 & ex3_sh_lvl2[40]) | (cp2_080 & ex3_sh_lvl2[24]))); + assign ex3_sh16_r2_b[105] = (~((cp3_064 & ex3_sh_lvl2[41]) | (cp2_080 & ex3_sh_lvl2[25]))); + assign ex3_sh16_r2_b[106] = (~((cp3_064 & ex3_sh_lvl2[42]) | (cp2_080 & ex3_sh_lvl2[26]))); + assign ex3_sh16_r2_b[107] = (~((cp3_064 & ex3_sh_lvl2[43]) | (cp2_080 & ex3_sh_lvl2[27]))); + assign ex3_sh16_r2_b[108] = (~((cp3_064 & ex3_sh_lvl2[44]) | (cp2_080 & ex3_sh_lvl2[28]))); + assign ex3_sh16_r2_b[109] = (~((cp3_064 & ex3_sh_lvl2[45]) | (cp2_080 & ex3_sh_lvl2[29]))); + assign ex3_sh16_r2_b[110] = (~((cp3_064 & ex3_sh_lvl2[46]) | (cp2_080 & ex3_sh_lvl2[30]))); + assign ex3_sh16_r2_b[111] = (~((cp3_064 & ex3_sh_lvl2[47]) | (cp2_080 & ex3_sh_lvl2[31]))); + + assign ex3_sh16_r2_b[112] = (~((cp3_080 & ex3_sh_lvl2[32]) | (cp2_096 & ex3_sh_lvl2[16]))); + assign ex3_sh16_r2_b[113] = (~((cp3_080 & ex3_sh_lvl2[33]) | (cp2_096 & ex3_sh_lvl2[17]))); + assign ex3_sh16_r2_b[114] = (~((cp3_080 & ex3_sh_lvl2[34]) | (cp2_096 & ex3_sh_lvl2[18]))); + assign ex3_sh16_r2_b[115] = (~((cp3_080 & ex3_sh_lvl2[35]) | (cp2_096 & ex3_sh_lvl2[19]))); + assign ex3_sh16_r2_b[116] = (~((cp3_080 & ex3_sh_lvl2[36]) | (cp2_096 & ex3_sh_lvl2[20]))); + assign ex3_sh16_r2_b[117] = (~((cp3_080 & ex3_sh_lvl2[37]) | (cp2_096 & ex3_sh_lvl2[21]))); + assign ex3_sh16_r2_b[118] = (~((cp3_080 & ex3_sh_lvl2[38]) | (cp2_096 & ex3_sh_lvl2[22]))); + assign ex3_sh16_r2_b[119] = (~((cp3_080 & ex3_sh_lvl2[39]) | (cp2_096 & ex3_sh_lvl2[23]))); + assign ex3_sh16_r2_b[120] = (~((cp3_080 & ex3_sh_lvl2[40]) | (cp2_096 & ex3_sh_lvl2[24]))); + assign ex3_sh16_r2_b[121] = (~((cp3_080 & ex3_sh_lvl2[41]) | (cp2_096 & ex3_sh_lvl2[25]))); + assign ex3_sh16_r2_b[122] = (~((cp3_080 & ex3_sh_lvl2[42]) | (cp2_096 & ex3_sh_lvl2[26]))); + assign ex3_sh16_r2_b[123] = (~((cp3_080 & ex3_sh_lvl2[43]) | (cp2_096 & ex3_sh_lvl2[27]))); + assign ex3_sh16_r2_b[124] = (~((cp3_080 & ex3_sh_lvl2[44]) | (cp2_096 & ex3_sh_lvl2[28]))); + assign ex3_sh16_r2_b[125] = (~((cp3_080 & ex3_sh_lvl2[45]) | (cp2_096 & ex3_sh_lvl2[29]))); + assign ex3_sh16_r2_b[126] = (~((cp3_080 & ex3_sh_lvl2[46]) | (cp2_096 & ex3_sh_lvl2[30]))); + assign ex3_sh16_r2_b[127] = (~((cp3_080 & ex3_sh_lvl2[47]) | (cp2_096 & ex3_sh_lvl2[31]))); + + assign ex3_sh16_r2_b[128] = (~((cp3_096 & ex3_sh_lvl2[32]) | (cp2_112 & ex3_sh_lvl2[16]))); + assign ex3_sh16_r2_b[129] = (~((cp3_096 & ex3_sh_lvl2[33]) | (cp2_112 & ex3_sh_lvl2[17]))); + assign ex3_sh16_r2_b[130] = (~((cp3_096 & ex3_sh_lvl2[34]) | (cp2_112 & ex3_sh_lvl2[18]))); + assign ex3_sh16_r2_b[131] = (~((cp3_096 & ex3_sh_lvl2[35]) | (cp2_112 & ex3_sh_lvl2[19]))); + assign ex3_sh16_r2_b[132] = (~((cp3_096 & ex3_sh_lvl2[36]) | (cp2_112 & ex3_sh_lvl2[20]))); + assign ex3_sh16_r2_b[133] = (~((cp3_096 & ex3_sh_lvl2[37]) | (cp2_112 & ex3_sh_lvl2[21]))); + assign ex3_sh16_r2_b[134] = (~((cp3_096 & ex3_sh_lvl2[38]) | (cp2_112 & ex3_sh_lvl2[22]))); + assign ex3_sh16_r2_b[135] = (~((cp3_096 & ex3_sh_lvl2[39]) | (cp2_112 & ex3_sh_lvl2[23]))); + assign ex3_sh16_r2_b[136] = (~((cp3_096 & ex3_sh_lvl2[40]) | (cp2_112 & ex3_sh_lvl2[24]))); + assign ex3_sh16_r2_b[137] = (~((cp3_096 & ex3_sh_lvl2[41]) | (cp2_112 & ex3_sh_lvl2[25]))); + assign ex3_sh16_r2_b[138] = (~((cp3_096 & ex3_sh_lvl2[42]) | (cp2_112 & ex3_sh_lvl2[26]))); + assign ex3_sh16_r2_b[139] = (~((cp3_096 & ex3_sh_lvl2[43]) | (cp2_112 & ex3_sh_lvl2[27]))); + assign ex3_sh16_r2_b[140] = (~((cp3_096 & ex3_sh_lvl2[44]) | (cp2_112 & ex3_sh_lvl2[28]))); + assign ex3_sh16_r2_b[141] = (~((cp3_096 & ex3_sh_lvl2[45]) | (cp2_112 & ex3_sh_lvl2[29]))); + assign ex3_sh16_r2_b[142] = (~((cp3_096 & ex3_sh_lvl2[46]) | (cp2_112 & ex3_sh_lvl2[30]))); + assign ex3_sh16_r2_b[143] = (~((cp3_096 & ex3_sh_lvl2[47]) | (cp2_112 & ex3_sh_lvl2[31]))); + + assign ex3_sh16_r2_b[144] = (~((cp3_112 & ex3_sh_lvl2[32]) | (cp2_128 & ex3_sh_lvl2[16]))); + assign ex3_sh16_r2_b[145] = (~((cp3_112 & ex3_sh_lvl2[33]) | (cp2_128 & ex3_sh_lvl2[17]))); + assign ex3_sh16_r2_b[146] = (~((cp3_112 & ex3_sh_lvl2[34]) | (cp2_128 & ex3_sh_lvl2[18]))); + assign ex3_sh16_r2_b[147] = (~((cp3_112 & ex3_sh_lvl2[35]) | (cp2_128 & ex3_sh_lvl2[19]))); + assign ex3_sh16_r2_b[148] = (~((cp3_112 & ex3_sh_lvl2[36]) | (cp2_128 & ex3_sh_lvl2[20]))); + assign ex3_sh16_r2_b[149] = (~((cp3_112 & ex3_sh_lvl2[37]) | (cp2_128 & ex3_sh_lvl2[21]))); + assign ex3_sh16_r2_b[150] = (~((cp3_112 & ex3_sh_lvl2[38]) | (cp2_128 & ex3_sh_lvl2[22]))); + assign ex3_sh16_r2_b[151] = (~((cp3_112 & ex3_sh_lvl2[39]) | (cp2_128 & ex3_sh_lvl2[23]))); + assign ex3_sh16_r2_b[152] = (~((cp3_112 & ex3_sh_lvl2[40]) | (cp2_128 & ex3_sh_lvl2[24]))); + assign ex3_sh16_r2_b[153] = (~((cp3_112 & ex3_sh_lvl2[41]) | (cp2_128 & ex3_sh_lvl2[25]))); + assign ex3_sh16_r2_b[154] = (~((cp3_112 & ex3_sh_lvl2[42]) | (cp2_128 & ex3_sh_lvl2[26]))); + assign ex3_sh16_r2_b[155] = (~((cp3_112 & ex3_sh_lvl2[43]) | (cp2_128 & ex3_sh_lvl2[27]))); + assign ex3_sh16_r2_b[156] = (~((cp3_112 & ex3_sh_lvl2[44]) | (cp2_128 & ex3_sh_lvl2[28]))); + assign ex3_sh16_r2_b[157] = (~((cp3_112 & ex3_sh_lvl2[45]) | (cp2_128 & ex3_sh_lvl2[29]))); + assign ex3_sh16_r2_b[158] = (~((cp3_112 & ex3_sh_lvl2[46]) | (cp2_128 & ex3_sh_lvl2[30]))); + assign ex3_sh16_r2_b[159] = (~((cp3_112 & ex3_sh_lvl2[47]) | (cp2_128 & ex3_sh_lvl2[31]))); + + assign ex3_sh16_r2_b[160] = (~((cp3_128 & ex3_sh_lvl2[32]) | (cp2_144 & ex3_sh_lvl2[16]))); + assign ex3_sh16_r2_b[161] = (~((cp3_128 & ex3_sh_lvl2[33]) | (cp2_144 & ex3_sh_lvl2[17]))); + assign ex3_sh16_r2_b[162] = (~((cp3_128 & ex3_sh_lvl2[34]) | (cp2_144 & ex3_sh_lvl2[18]))); + + assign ex3_sh16_r3_b[0] = (~(cp1_000 & ex3_sh_lvl2[0])); + assign ex3_sh16_r3_b[1] = (~(cp1_000 & ex3_sh_lvl2[1])); + assign ex3_sh16_r3_b[2] = (~(cp1_000 & ex3_sh_lvl2[2])); + assign ex3_sh16_r3_b[3] = (~(cp1_000 & ex3_sh_lvl2[3])); + assign ex3_sh16_r3_b[4] = (~(cp1_000 & ex3_sh_lvl2[4])); + assign ex3_sh16_r3_b[5] = (~(cp1_000 & ex3_sh_lvl2[5])); + assign ex3_sh16_r3_b[6] = (~(cp1_000 & ex3_sh_lvl2[6])); + assign ex3_sh16_r3_b[7] = (~(cp1_000 & ex3_sh_lvl2[7])); + assign ex3_sh16_r3_b[8] = (~(cp1_000 & ex3_sh_lvl2[8])); + assign ex3_sh16_r3_b[9] = (~(cp1_000 & ex3_sh_lvl2[9])); + assign ex3_sh16_r3_b[10] = (~(cp1_000 & ex3_sh_lvl2[10])); + assign ex3_sh16_r3_b[11] = (~(cp1_000 & ex3_sh_lvl2[11])); + assign ex3_sh16_r3_b[12] = (~(cp1_000 & ex3_sh_lvl2[12])); + assign ex3_sh16_r3_b[13] = (~(cp1_000 & ex3_sh_lvl2[13])); + assign ex3_sh16_r3_b[14] = (~(cp1_000 & ex3_sh_lvl2[14])); + assign ex3_sh16_r3_b[15] = (~(cp1_000 & ex3_sh_lvl2[15])); + + assign ex3_sh16_r3_b[16] = (~(cp1_016 & ex3_sh_lvl2[0])); + assign ex3_sh16_r3_b[17] = (~(cp1_016 & ex3_sh_lvl2[1])); + assign ex3_sh16_r3_b[18] = (~(cp1_016 & ex3_sh_lvl2[2])); + assign ex3_sh16_r3_b[19] = (~(cp1_016 & ex3_sh_lvl2[3])); + assign ex3_sh16_r3_b[20] = (~(cp1_016 & ex3_sh_lvl2[4])); + assign ex3_sh16_r3_b[21] = (~(cp1_016 & ex3_sh_lvl2[5])); + assign ex3_sh16_r3_b[22] = (~(cp1_016 & ex3_sh_lvl2[6])); + assign ex3_sh16_r3_b[23] = (~(cp1_016 & ex3_sh_lvl2[7])); + assign ex3_sh16_r3_b[24] = (~(cp1_016 & ex3_sh_lvl2[8])); + assign ex3_sh16_r3_b[25] = (~(cp1_016 & ex3_sh_lvl2[9])); + assign ex3_sh16_r3_b[26] = (~(cp1_016 & ex3_sh_lvl2[10])); + assign ex3_sh16_r3_b[27] = (~(cp1_016 & ex3_sh_lvl2[11])); + assign ex3_sh16_r3_b[28] = (~(cp1_016 & ex3_sh_lvl2[12])); + assign ex3_sh16_r3_b[29] = (~(cp1_016 & ex3_sh_lvl2[13])); + assign ex3_sh16_r3_b[30] = (~(cp1_016 & ex3_sh_lvl2[14])); + assign ex3_sh16_r3_b[31] = (~(cp1_016 & ex3_sh_lvl2[15])); + + assign ex3_sh16_r3_b[32] = (~(cp1_032 & ex3_sh_lvl2[0])); + assign ex3_sh16_r3_b[33] = (~(cp1_032 & ex3_sh_lvl2[1])); + assign ex3_sh16_r3_b[34] = (~(cp1_032 & ex3_sh_lvl2[2])); + assign ex3_sh16_r3_b[35] = (~(cp1_032 & ex3_sh_lvl2[3])); + assign ex3_sh16_r3_b[36] = (~(cp1_032 & ex3_sh_lvl2[4])); + assign ex3_sh16_r3_b[37] = (~(cp1_032 & ex3_sh_lvl2[5])); + assign ex3_sh16_r3_b[38] = (~(cp1_032 & ex3_sh_lvl2[6])); + assign ex3_sh16_r3_b[39] = (~(cp1_032 & ex3_sh_lvl2[7])); + assign ex3_sh16_r3_b[40] = (~(cp1_032 & ex3_sh_lvl2[8])); + assign ex3_sh16_r3_b[41] = (~(cp1_032 & ex3_sh_lvl2[9])); + assign ex3_sh16_r3_b[42] = (~(cp1_032 & ex3_sh_lvl2[10])); + assign ex3_sh16_r3_b[43] = (~(cp1_032 & ex3_sh_lvl2[11])); + assign ex3_sh16_r3_b[44] = (~(cp1_032 & ex3_sh_lvl2[12])); + assign ex3_sh16_r3_b[45] = (~(cp1_032 & ex3_sh_lvl2[13])); + assign ex3_sh16_r3_b[46] = (~(cp1_032 & ex3_sh_lvl2[14])); + assign ex3_sh16_r3_b[47] = (~(cp1_032 & ex3_sh_lvl2[15])); + + assign ex3_sh16_r3_b[48] = (~(cp1_048 & ex3_sh_lvl2[0])); + assign ex3_sh16_r3_b[49] = (~(cp1_048 & ex3_sh_lvl2[1])); + assign ex3_sh16_r3_b[50] = (~(cp1_048 & ex3_sh_lvl2[2])); + assign ex3_sh16_r3_b[51] = (~(cp1_048 & ex3_sh_lvl2[3])); + assign ex3_sh16_r3_b[52] = (~(cp1_048 & ex3_sh_lvl2[4])); + assign ex3_sh16_r3_b[53] = (~(cp1_048 & ex3_sh_lvl2[5])); + assign ex3_sh16_r3_b[54] = (~(cp1_048 & ex3_sh_lvl2[6])); + assign ex3_sh16_r3_b[55] = (~(cp1_048 & ex3_sh_lvl2[7])); + assign ex3_sh16_r3_b[56] = (~(cp1_048 & ex3_sh_lvl2[8])); + assign ex3_sh16_r3_b[57] = (~(cp1_048 & ex3_sh_lvl2[9])); + assign ex3_sh16_r3_b[58] = (~(cp1_048 & ex3_sh_lvl2[10])); + assign ex3_sh16_r3_b[59] = (~(cp1_048 & ex3_sh_lvl2[11])); + assign ex3_sh16_r3_b[60] = (~(cp1_048 & ex3_sh_lvl2[12])); + assign ex3_sh16_r3_b[61] = (~(cp1_048 & ex3_sh_lvl2[13])); + assign ex3_sh16_r3_b[62] = (~(cp1_048 & ex3_sh_lvl2[14])); + assign ex3_sh16_r3_b[63] = (~(cp1_048 & ex3_sh_lvl2[15])); + + assign ex3_sh16_r3_b[64] = (~(cp1_064 & ex3_sh_lvl2[0])); + assign ex3_sh16_r3_b[65] = (~(cp1_064 & ex3_sh_lvl2[1])); + assign ex3_sh16_r3_b[66] = (~(cp1_064 & ex3_sh_lvl2[2])); + assign ex3_sh16_r3_b[67] = (~(cp1_064 & ex3_sh_lvl2[3])); + assign ex3_sh16_r3_b[68] = (~(cp1_064 & ex3_sh_lvl2[4])); + assign ex3_sh16_r3_b[69] = (~(cp1_064 & ex3_sh_lvl2[5])); + assign ex3_sh16_r3_b[70] = (~(cp1_064 & ex3_sh_lvl2[6])); + assign ex3_sh16_r3_b[71] = (~(cp1_064 & ex3_sh_lvl2[7])); + assign ex3_sh16_r3_b[72] = (~(cp1_064 & ex3_sh_lvl2[8])); + assign ex3_sh16_r3_b[73] = (~(cp1_064 & ex3_sh_lvl2[9])); + assign ex3_sh16_r3_b[74] = (~(cp1_064 & ex3_sh_lvl2[10])); + assign ex3_sh16_r3_b[75] = (~(cp1_064 & ex3_sh_lvl2[11])); + assign ex3_sh16_r3_b[76] = (~(cp1_064 & ex3_sh_lvl2[12])); + assign ex3_sh16_r3_b[77] = (~(cp1_064 & ex3_sh_lvl2[13])); + assign ex3_sh16_r3_b[78] = (~(cp1_064 & ex3_sh_lvl2[14])); + assign ex3_sh16_r3_b[79] = (~(cp1_064 & ex3_sh_lvl2[15])); + + assign ex3_sh16_r3_b[80] = (~(cp1_080 & ex3_sh_lvl2[0])); + assign ex3_sh16_r3_b[81] = (~(cp1_080 & ex3_sh_lvl2[1])); + assign ex3_sh16_r3_b[82] = (~(cp1_080 & ex3_sh_lvl2[2])); + assign ex3_sh16_r3_b[83] = (~(cp1_080 & ex3_sh_lvl2[3])); + assign ex3_sh16_r3_b[84] = (~(cp1_080 & ex3_sh_lvl2[4])); + assign ex3_sh16_r3_b[85] = (~(cp1_080 & ex3_sh_lvl2[5])); + assign ex3_sh16_r3_b[86] = (~(cp1_080 & ex3_sh_lvl2[6])); + assign ex3_sh16_r3_b[87] = (~(cp1_080 & ex3_sh_lvl2[7])); + assign ex3_sh16_r3_b[88] = (~(cp1_080 & ex3_sh_lvl2[8])); + assign ex3_sh16_r3_b[89] = (~(cp1_080 & ex3_sh_lvl2[9])); + assign ex3_sh16_r3_b[90] = (~(cp1_080 & ex3_sh_lvl2[10])); + assign ex3_sh16_r3_b[91] = (~(cp1_080 & ex3_sh_lvl2[11])); + assign ex3_sh16_r3_b[92] = (~(cp1_080 & ex3_sh_lvl2[12])); + assign ex3_sh16_r3_b[93] = (~(cp1_080 & ex3_sh_lvl2[13])); + assign ex3_sh16_r3_b[94] = (~(cp1_080 & ex3_sh_lvl2[14])); + assign ex3_sh16_r3_b[95] = (~(cp1_080 & ex3_sh_lvl2[15])); + + assign ex3_sh16_r3_b[96] = (~(cp1_096 & ex3_sh_lvl2[0])); + assign ex3_sh16_r3_b[97] = (~(cp1_096 & ex3_sh_lvl2[1])); + assign ex3_sh16_r3_b[98] = (~(cp1_096 & ex3_sh_lvl2[2])); + assign ex3_sh16_r3_b[99] = (~((cp1_096 & ex3_sh_lvl2[3]) | (cp1_spc & ex3_special[99]))); + assign ex3_sh16_r3_b[100] = (~((cp1_096 & ex3_sh_lvl2[4]) | (cp1_spc & ex3_special[100]))); + assign ex3_sh16_r3_b[101] = (~((cp1_096 & ex3_sh_lvl2[5]) | (cp1_spc & ex3_special[101]))); + assign ex3_sh16_r3_b[102] = (~((cp1_096 & ex3_sh_lvl2[6]) | (cp1_spc & ex3_special[102]))); + assign ex3_sh16_r3_b[103] = (~((cp1_096 & ex3_sh_lvl2[7]) | (cp1_spc & ex3_special[103]))); + assign ex3_sh16_r3_b[104] = (~((cp1_096 & ex3_sh_lvl2[8]) | (cp1_spc & ex3_special[104]))); + assign ex3_sh16_r3_b[105] = (~((cp1_096 & ex3_sh_lvl2[9]) | (cp1_spc & ex3_special[105]))); + assign ex3_sh16_r3_b[106] = (~((cp1_096 & ex3_sh_lvl2[10]) | (cp1_spc & ex3_special[106]))); + assign ex3_sh16_r3_b[107] = (~((cp1_096 & ex3_sh_lvl2[11]) | (cp1_spc & ex3_special[107]))); + assign ex3_sh16_r3_b[108] = (~((cp1_096 & ex3_sh_lvl2[12]) | (cp1_spc & ex3_special[108]))); + assign ex3_sh16_r3_b[109] = (~((cp1_096 & ex3_sh_lvl2[13]) | (cp1_spc & ex3_special[109]))); + assign ex3_sh16_r3_b[110] = (~((cp1_096 & ex3_sh_lvl2[14]) | (cp1_spc & ex3_special[110]))); + assign ex3_sh16_r3_b[111] = (~((cp1_096 & ex3_sh_lvl2[15]) | (cp1_spc & ex3_special[111]))); + + assign ex3_sh16_r3_b[112] = (~((cp1_112 & ex3_sh_lvl2[0]) | (cp2_spc & ex3_special[112]))); + assign ex3_sh16_r3_b[113] = (~((cp1_112 & ex3_sh_lvl2[1]) | (cp2_spc & ex3_special[113]))); + assign ex3_sh16_r3_b[114] = (~((cp1_112 & ex3_sh_lvl2[2]) | (cp2_spc & ex3_special[114]))); + assign ex3_sh16_r3_b[115] = (~((cp1_112 & ex3_sh_lvl2[3]) | (cp2_spc & ex3_special[115]))); + assign ex3_sh16_r3_b[116] = (~((cp1_112 & ex3_sh_lvl2[4]) | (cp2_spc & ex3_special[116]))); + assign ex3_sh16_r3_b[117] = (~((cp1_112 & ex3_sh_lvl2[5]) | (cp2_spc & ex3_special[117]))); + assign ex3_sh16_r3_b[118] = (~((cp1_112 & ex3_sh_lvl2[6]) | (cp2_spc & ex3_special[118]))); + assign ex3_sh16_r3_b[119] = (~((cp1_112 & ex3_sh_lvl2[7]) | (cp2_spc & ex3_special[119]))); + assign ex3_sh16_r3_b[120] = (~((cp1_112 & ex3_sh_lvl2[8]) | (cp2_spc & ex3_special[120]))); + assign ex3_sh16_r3_b[121] = (~((cp1_112 & ex3_sh_lvl2[9]) | (cp2_spc & ex3_special[121]))); + assign ex3_sh16_r3_b[122] = (~((cp1_112 & ex3_sh_lvl2[10]) | (cp2_spc & ex3_special[122]))); + assign ex3_sh16_r3_b[123] = (~((cp1_112 & ex3_sh_lvl2[11]) | (cp2_spc & ex3_special[123]))); + assign ex3_sh16_r3_b[124] = (~((cp1_112 & ex3_sh_lvl2[12]) | (cp2_spc & ex3_special[124]))); + assign ex3_sh16_r3_b[125] = (~((cp1_112 & ex3_sh_lvl2[13]) | (cp2_spc & ex3_special[125]))); + assign ex3_sh16_r3_b[126] = (~((cp1_112 & ex3_sh_lvl2[14]) | (cp2_spc & ex3_special[126]))); + assign ex3_sh16_r3_b[127] = (~((cp1_112 & ex3_sh_lvl2[15]) | (cp2_spc & ex3_special[127]))); + + assign ex3_sh16_r3_b[128] = (~((cp1_128 & ex3_sh_lvl2[0]) | (cp3_spc & ex3_special[128]))); + assign ex3_sh16_r3_b[129] = (~((cp1_128 & ex3_sh_lvl2[1]) | (cp3_spc & ex3_special[129]))); + assign ex3_sh16_r3_b[130] = (~((cp1_128 & ex3_sh_lvl2[2]) | (cp3_spc & ex3_special[130]))); + assign ex3_sh16_r3_b[131] = (~((cp1_128 & ex3_sh_lvl2[3]) | (cp3_spc & ex3_special[131]))); + assign ex3_sh16_r3_b[132] = (~((cp1_128 & ex3_sh_lvl2[4]) | (cp3_spc & ex3_special[132]))); + assign ex3_sh16_r3_b[133] = (~((cp1_128 & ex3_sh_lvl2[5]) | (cp3_spc & ex3_special[133]))); + assign ex3_sh16_r3_b[134] = (~((cp1_128 & ex3_sh_lvl2[6]) | (cp3_spc & ex3_special[134]))); + assign ex3_sh16_r3_b[135] = (~((cp1_128 & ex3_sh_lvl2[7]) | (cp3_spc & ex3_special[135]))); + assign ex3_sh16_r3_b[136] = (~((cp1_128 & ex3_sh_lvl2[8]) | (cp3_spc & ex3_special[136]))); + assign ex3_sh16_r3_b[137] = (~((cp1_128 & ex3_sh_lvl2[9]) | (cp3_spc & ex3_special[137]))); + assign ex3_sh16_r3_b[138] = (~((cp1_128 & ex3_sh_lvl2[10]) | (cp3_spc & ex3_special[138]))); + assign ex3_sh16_r3_b[139] = (~((cp1_128 & ex3_sh_lvl2[11]) | (cp3_spc & ex3_special[139]))); + assign ex3_sh16_r3_b[140] = (~((cp1_128 & ex3_sh_lvl2[12]) | (cp3_spc & ex3_special[140]))); + assign ex3_sh16_r3_b[141] = (~((cp1_128 & ex3_sh_lvl2[13]) | (cp3_spc & ex3_special[141]))); + assign ex3_sh16_r3_b[142] = (~((cp1_128 & ex3_sh_lvl2[14]) | (cp3_spc & ex3_special[142]))); + assign ex3_sh16_r3_b[143] = (~((cp1_128 & ex3_sh_lvl2[15]) | (cp3_spc & ex3_special[143]))); + + assign ex3_sh16_r3_b[144] = (~((cp1_144 & ex3_sh_lvl2[0]) | (cp4_spc & ex3_special[144]))); + assign ex3_sh16_r3_b[145] = (~((cp1_144 & ex3_sh_lvl2[1]) | (cp4_spc & ex3_special[145]))); + assign ex3_sh16_r3_b[146] = (~((cp1_144 & ex3_sh_lvl2[2]) | (cp4_spc & ex3_special[146]))); + assign ex3_sh16_r3_b[147] = (~((cp1_144 & ex3_sh_lvl2[3]) | (cp4_spc & ex3_special[147]))); + assign ex3_sh16_r3_b[148] = (~((cp1_144 & ex3_sh_lvl2[4]) | (cp4_spc & ex3_special[148]))); + assign ex3_sh16_r3_b[149] = (~((cp1_144 & ex3_sh_lvl2[5]) | (cp4_spc & ex3_special[149]))); + assign ex3_sh16_r3_b[150] = (~((cp1_144 & ex3_sh_lvl2[6]) | (cp4_spc & ex3_special[150]))); + assign ex3_sh16_r3_b[151] = (~((cp1_144 & ex3_sh_lvl2[7]) | (cp4_spc & ex3_special[151]))); + assign ex3_sh16_r3_b[152] = (~((cp1_144 & ex3_sh_lvl2[8]) | (cp4_spc & ex3_special[152]))); + assign ex3_sh16_r3_b[153] = (~((cp1_144 & ex3_sh_lvl2[9]) | (cp4_spc & ex3_special[153]))); + assign ex3_sh16_r3_b[154] = (~((cp1_144 & ex3_sh_lvl2[10]) | (cp4_spc & ex3_special[154]))); + assign ex3_sh16_r3_b[155] = (~((cp1_144 & ex3_sh_lvl2[11]) | (cp4_spc & ex3_special[155]))); + assign ex3_sh16_r3_b[156] = (~((cp1_144 & ex3_sh_lvl2[12]) | (cp4_spc & ex3_special[156]))); + assign ex3_sh16_r3_b[157] = (~((cp1_144 & ex3_sh_lvl2[13]) | (cp4_spc & ex3_special[157]))); + assign ex3_sh16_r3_b[158] = (~((cp1_144 & ex3_sh_lvl2[14]) | (cp4_spc & ex3_special[158]))); + assign ex3_sh16_r3_b[159] = (~((cp1_144 & ex3_sh_lvl2[15]) | (cp4_spc & ex3_special[159]))); + + assign ex3_sh16_r3_b[160] = (~((cp1_160 & ex3_sh_lvl2[0]) | (cp5_spc & ex3_special[160]))); + assign ex3_sh16_r3_b[161] = (~((cp1_160 & ex3_sh_lvl2[1]) | (cp5_spc & ex3_special[161]))); + assign ex3_sh16_r3_b[162] = (~((cp1_160 & ex3_sh_lvl2[2]) | (cp5_spc & ex3_special[162]))); + + assign ex3_sh_lvl3[0] = (~(ex3_sh16_r1_b[0] & ex3_sh16_r2_b[0] & ex3_sh16_r3_b[0])); + assign ex3_sh_lvl3[1] = (~(ex3_sh16_r1_b[1] & ex3_sh16_r2_b[1] & ex3_sh16_r3_b[1])); + assign ex3_sh_lvl3[2] = (~(ex3_sh16_r1_b[2] & ex3_sh16_r2_b[2] & ex3_sh16_r3_b[2])); + assign ex3_sh_lvl3[3] = (~(ex3_sh16_r1_b[3] & ex3_sh16_r2_b[3] & ex3_sh16_r3_b[3])); + assign ex3_sh_lvl3[4] = (~(ex3_sh16_r1_b[4] & ex3_sh16_r2_b[4] & ex3_sh16_r3_b[4])); + assign ex3_sh_lvl3[5] = (~(ex3_sh16_r1_b[5] & ex3_sh16_r2_b[5] & ex3_sh16_r3_b[5])); + assign ex3_sh_lvl3[6] = (~(ex3_sh16_r1_b[6] & ex3_sh16_r2_b[6] & ex3_sh16_r3_b[6])); + assign ex3_sh_lvl3[7] = (~(ex3_sh16_r1_b[7] & ex3_sh16_r2_b[7] & ex3_sh16_r3_b[7])); + assign ex3_sh_lvl3[8] = (~(ex3_sh16_r1_b[8] & ex3_sh16_r2_b[8] & ex3_sh16_r3_b[8])); + assign ex3_sh_lvl3[9] = (~(ex3_sh16_r1_b[9] & ex3_sh16_r2_b[9] & ex3_sh16_r3_b[9])); + assign ex3_sh_lvl3[10] = (~(ex3_sh16_r1_b[10] & ex3_sh16_r2_b[10] & ex3_sh16_r3_b[10])); + assign ex3_sh_lvl3[11] = (~(ex3_sh16_r1_b[11] & ex3_sh16_r2_b[11] & ex3_sh16_r3_b[11])); + assign ex3_sh_lvl3[12] = (~(ex3_sh16_r1_b[12] & ex3_sh16_r2_b[12] & ex3_sh16_r3_b[12])); + assign ex3_sh_lvl3[13] = (~(ex3_sh16_r1_b[13] & ex3_sh16_r2_b[13] & ex3_sh16_r3_b[13])); + assign ex3_sh_lvl3[14] = (~(ex3_sh16_r1_b[14] & ex3_sh16_r2_b[14] & ex3_sh16_r3_b[14])); + assign ex3_sh_lvl3[15] = (~(ex3_sh16_r1_b[15] & ex3_sh16_r2_b[15] & ex3_sh16_r3_b[15])); + assign ex3_sh_lvl3[16] = (~(ex3_sh16_r1_b[16] & ex3_sh16_r2_b[16] & ex3_sh16_r3_b[16])); + assign ex3_sh_lvl3[17] = (~(ex3_sh16_r1_b[17] & ex3_sh16_r2_b[17] & ex3_sh16_r3_b[17])); + assign ex3_sh_lvl3[18] = (~(ex3_sh16_r1_b[18] & ex3_sh16_r2_b[18] & ex3_sh16_r3_b[18])); + assign ex3_sh_lvl3[19] = (~(ex3_sh16_r1_b[19] & ex3_sh16_r2_b[19] & ex3_sh16_r3_b[19])); + assign ex3_sh_lvl3[20] = (~(ex3_sh16_r1_b[20] & ex3_sh16_r2_b[20] & ex3_sh16_r3_b[20])); + assign ex3_sh_lvl3[21] = (~(ex3_sh16_r1_b[21] & ex3_sh16_r2_b[21] & ex3_sh16_r3_b[21])); + assign ex3_sh_lvl3[22] = (~(ex3_sh16_r1_b[22] & ex3_sh16_r2_b[22] & ex3_sh16_r3_b[22])); + assign ex3_sh_lvl3[23] = (~(ex3_sh16_r1_b[23] & ex3_sh16_r2_b[23] & ex3_sh16_r3_b[23])); + assign ex3_sh_lvl3[24] = (~(ex3_sh16_r1_b[24] & ex3_sh16_r2_b[24] & ex3_sh16_r3_b[24])); + assign ex3_sh_lvl3[25] = (~(ex3_sh16_r1_b[25] & ex3_sh16_r2_b[25] & ex3_sh16_r3_b[25])); + assign ex3_sh_lvl3[26] = (~(ex3_sh16_r1_b[26] & ex3_sh16_r2_b[26] & ex3_sh16_r3_b[26])); + assign ex3_sh_lvl3[27] = (~(ex3_sh16_r1_b[27] & ex3_sh16_r2_b[27] & ex3_sh16_r3_b[27])); + assign ex3_sh_lvl3[28] = (~(ex3_sh16_r1_b[28] & ex3_sh16_r2_b[28] & ex3_sh16_r3_b[28])); + assign ex3_sh_lvl3[29] = (~(ex3_sh16_r1_b[29] & ex3_sh16_r2_b[29] & ex3_sh16_r3_b[29])); + assign ex3_sh_lvl3[30] = (~(ex3_sh16_r1_b[30] & ex3_sh16_r2_b[30] & ex3_sh16_r3_b[30])); + assign ex3_sh_lvl3[31] = (~(ex3_sh16_r1_b[31] & ex3_sh16_r2_b[31] & ex3_sh16_r3_b[31])); + assign ex3_sh_lvl3[32] = (~(ex3_sh16_r1_b[32] & ex3_sh16_r2_b[32] & ex3_sh16_r3_b[32])); + assign ex3_sh_lvl3[33] = (~(ex3_sh16_r1_b[33] & ex3_sh16_r2_b[33] & ex3_sh16_r3_b[33])); + assign ex3_sh_lvl3[34] = (~(ex3_sh16_r1_b[34] & ex3_sh16_r2_b[34] & ex3_sh16_r3_b[34])); + assign ex3_sh_lvl3[35] = (~(ex3_sh16_r1_b[35] & ex3_sh16_r2_b[35] & ex3_sh16_r3_b[35])); + assign ex3_sh_lvl3[36] = (~(ex3_sh16_r1_b[36] & ex3_sh16_r2_b[36] & ex3_sh16_r3_b[36])); + assign ex3_sh_lvl3[37] = (~(ex3_sh16_r1_b[37] & ex3_sh16_r2_b[37] & ex3_sh16_r3_b[37])); + assign ex3_sh_lvl3[38] = (~(ex3_sh16_r1_b[38] & ex3_sh16_r2_b[38] & ex3_sh16_r3_b[38])); + assign ex3_sh_lvl3[39] = (~(ex3_sh16_r1_b[39] & ex3_sh16_r2_b[39] & ex3_sh16_r3_b[39])); + assign ex3_sh_lvl3[40] = (~(ex3_sh16_r1_b[40] & ex3_sh16_r2_b[40] & ex3_sh16_r3_b[40])); + assign ex3_sh_lvl3[41] = (~(ex3_sh16_r1_b[41] & ex3_sh16_r2_b[41] & ex3_sh16_r3_b[41])); + assign ex3_sh_lvl3[42] = (~(ex3_sh16_r1_b[42] & ex3_sh16_r2_b[42] & ex3_sh16_r3_b[42])); + assign ex3_sh_lvl3[43] = (~(ex3_sh16_r1_b[43] & ex3_sh16_r2_b[43] & ex3_sh16_r3_b[43])); + assign ex3_sh_lvl3[44] = (~(ex3_sh16_r1_b[44] & ex3_sh16_r2_b[44] & ex3_sh16_r3_b[44])); + assign ex3_sh_lvl3[45] = (~(ex3_sh16_r1_b[45] & ex3_sh16_r2_b[45] & ex3_sh16_r3_b[45])); + assign ex3_sh_lvl3[46] = (~(ex3_sh16_r1_b[46] & ex3_sh16_r2_b[46] & ex3_sh16_r3_b[46])); + assign ex3_sh_lvl3[47] = (~(ex3_sh16_r1_b[47] & ex3_sh16_r2_b[47] & ex3_sh16_r3_b[47])); + assign ex3_sh_lvl3[48] = (~(ex3_sh16_r1_b[48] & ex3_sh16_r2_b[48] & ex3_sh16_r3_b[48])); + assign ex3_sh_lvl3[49] = (~(ex3_sh16_r1_b[49] & ex3_sh16_r2_b[49] & ex3_sh16_r3_b[49])); + assign ex3_sh_lvl3[50] = (~(ex3_sh16_r1_b[50] & ex3_sh16_r2_b[50] & ex3_sh16_r3_b[50])); + assign ex3_sh_lvl3[51] = (~(ex3_sh16_r1_b[51] & ex3_sh16_r2_b[51] & ex3_sh16_r3_b[51])); + assign ex3_sh_lvl3[52] = (~(ex3_sh16_r1_b[52] & ex3_sh16_r2_b[52] & ex3_sh16_r3_b[52])); + assign ex3_sh_lvl3[53] = (~(ex3_sh16_r1_b[53] & ex3_sh16_r2_b[53] & ex3_sh16_r3_b[53])); + assign ex3_sh_lvl3[54] = (~(ex3_sh16_r1_b[54] & ex3_sh16_r2_b[54] & ex3_sh16_r3_b[54])); + assign ex3_sh_lvl3[55] = (~(ex3_sh16_r1_b[55] & ex3_sh16_r2_b[55] & ex3_sh16_r3_b[55])); + assign ex3_sh_lvl3[56] = (~(ex3_sh16_r1_b[56] & ex3_sh16_r2_b[56] & ex3_sh16_r3_b[56])); + assign ex3_sh_lvl3[57] = (~(ex3_sh16_r1_b[57] & ex3_sh16_r2_b[57] & ex3_sh16_r3_b[57])); + assign ex3_sh_lvl3[58] = (~(ex3_sh16_r1_b[58] & ex3_sh16_r2_b[58] & ex3_sh16_r3_b[58])); + assign ex3_sh_lvl3[59] = (~(ex3_sh16_r1_b[59] & ex3_sh16_r2_b[59] & ex3_sh16_r3_b[59])); + assign ex3_sh_lvl3[60] = (~(ex3_sh16_r1_b[60] & ex3_sh16_r2_b[60] & ex3_sh16_r3_b[60])); + assign ex3_sh_lvl3[61] = (~(ex3_sh16_r1_b[61] & ex3_sh16_r2_b[61] & ex3_sh16_r3_b[61])); + assign ex3_sh_lvl3[62] = (~(ex3_sh16_r1_b[62] & ex3_sh16_r2_b[62] & ex3_sh16_r3_b[62])); + assign ex3_sh_lvl3[63] = (~(ex3_sh16_r1_b[63] & ex3_sh16_r2_b[63] & ex3_sh16_r3_b[63])); + assign ex3_sh_lvl3[64] = (~(ex3_sh16_r1_b[64] & ex3_sh16_r2_b[64] & ex3_sh16_r3_b[64])); + assign ex3_sh_lvl3[65] = (~(ex3_sh16_r1_b[65] & ex3_sh16_r2_b[65] & ex3_sh16_r3_b[65])); + assign ex3_sh_lvl3[66] = (~(ex3_sh16_r1_b[66] & ex3_sh16_r2_b[66] & ex3_sh16_r3_b[66])); + assign ex3_sh_lvl3[67] = (~(ex3_sh16_r1_b[67] & ex3_sh16_r2_b[67] & ex3_sh16_r3_b[67])); + assign ex3_sh_lvl3[68] = (~(ex3_sh16_r1_b[68] & ex3_sh16_r2_b[68] & ex3_sh16_r3_b[68])); + assign ex3_sh_lvl3[69] = (~(ex3_sh16_r1_b[69] & ex3_sh16_r2_b[69] & ex3_sh16_r3_b[69])); + assign ex3_sh_lvl3[70] = (~(ex3_sh16_r1_b[70] & ex3_sh16_r2_b[70] & ex3_sh16_r3_b[70])); + assign ex3_sh_lvl3[71] = (~(ex3_sh16_r1_b[71] & ex3_sh16_r2_b[71] & ex3_sh16_r3_b[71])); + assign ex3_sh_lvl3[72] = (~(ex3_sh16_r1_b[72] & ex3_sh16_r2_b[72] & ex3_sh16_r3_b[72])); + assign ex3_sh_lvl3[73] = (~(ex3_sh16_r1_b[73] & ex3_sh16_r2_b[73] & ex3_sh16_r3_b[73])); + assign ex3_sh_lvl3[74] = (~(ex3_sh16_r1_b[74] & ex3_sh16_r2_b[74] & ex3_sh16_r3_b[74])); + assign ex3_sh_lvl3[75] = (~(ex3_sh16_r1_b[75] & ex3_sh16_r2_b[75] & ex3_sh16_r3_b[75])); + assign ex3_sh_lvl3[76] = (~(ex3_sh16_r1_b[76] & ex3_sh16_r2_b[76] & ex3_sh16_r3_b[76])); + assign ex3_sh_lvl3[77] = (~(ex3_sh16_r1_b[77] & ex3_sh16_r2_b[77] & ex3_sh16_r3_b[77])); + assign ex3_sh_lvl3[78] = (~(ex3_sh16_r1_b[78] & ex3_sh16_r2_b[78] & ex3_sh16_r3_b[78])); + assign ex3_sh_lvl3[79] = (~(ex3_sh16_r1_b[79] & ex3_sh16_r2_b[79] & ex3_sh16_r3_b[79])); + assign ex3_sh_lvl3[80] = (~(ex3_sh16_r1_b[80] & ex3_sh16_r2_b[80] & ex3_sh16_r3_b[80])); + assign ex3_sh_lvl3[81] = (~(ex3_sh16_r1_b[81] & ex3_sh16_r2_b[81] & ex3_sh16_r3_b[81])); + assign ex3_sh_lvl3[82] = (~(ex3_sh16_r1_b[82] & ex3_sh16_r2_b[82] & ex3_sh16_r3_b[82])); + assign ex3_sh_lvl3[83] = (~(ex3_sh16_r1_b[83] & ex3_sh16_r2_b[83] & ex3_sh16_r3_b[83])); + assign ex3_sh_lvl3[84] = (~(ex3_sh16_r1_b[84] & ex3_sh16_r2_b[84] & ex3_sh16_r3_b[84])); + assign ex3_sh_lvl3[85] = (~(ex3_sh16_r1_b[85] & ex3_sh16_r2_b[85] & ex3_sh16_r3_b[85])); + assign ex3_sh_lvl3[86] = (~(ex3_sh16_r1_b[86] & ex3_sh16_r2_b[86] & ex3_sh16_r3_b[86])); + assign ex3_sh_lvl3[87] = (~(ex3_sh16_r1_b[87] & ex3_sh16_r2_b[87] & ex3_sh16_r3_b[87])); + assign ex3_sh_lvl3[88] = (~(ex3_sh16_r1_b[88] & ex3_sh16_r2_b[88] & ex3_sh16_r3_b[88])); + assign ex3_sh_lvl3[89] = (~(ex3_sh16_r1_b[89] & ex3_sh16_r2_b[89] & ex3_sh16_r3_b[89])); + assign ex3_sh_lvl3[90] = (~(ex3_sh16_r1_b[90] & ex3_sh16_r2_b[90] & ex3_sh16_r3_b[90])); + assign ex3_sh_lvl3[91] = (~(ex3_sh16_r1_b[91] & ex3_sh16_r2_b[91] & ex3_sh16_r3_b[91])); + assign ex3_sh_lvl3[92] = (~(ex3_sh16_r1_b[92] & ex3_sh16_r2_b[92] & ex3_sh16_r3_b[92])); + assign ex3_sh_lvl3[93] = (~(ex3_sh16_r1_b[93] & ex3_sh16_r2_b[93] & ex3_sh16_r3_b[93])); + assign ex3_sh_lvl3[94] = (~(ex3_sh16_r1_b[94] & ex3_sh16_r2_b[94] & ex3_sh16_r3_b[94])); + assign ex3_sh_lvl3[95] = (~(ex3_sh16_r1_b[95] & ex3_sh16_r2_b[95] & ex3_sh16_r3_b[95])); + assign ex3_sh_lvl3[96] = (~(ex3_sh16_r1_b[96] & ex3_sh16_r2_b[96] & ex3_sh16_r3_b[96])); + assign ex3_sh_lvl3[97] = (~(ex3_sh16_r1_b[97] & ex3_sh16_r2_b[97] & ex3_sh16_r3_b[97])); + assign ex3_sh_lvl3[98] = (~(ex3_sh16_r1_b[98] & ex3_sh16_r2_b[98] & ex3_sh16_r3_b[98])); + assign ex3_sh_lvl3[99] = (~(ex3_sh16_r1_b[99] & ex3_sh16_r2_b[99] & ex3_sh16_r3_b[99])); + assign ex3_sh_lvl3[100] = (~(ex3_sh16_r1_b[100] & ex3_sh16_r2_b[100] & ex3_sh16_r3_b[100])); + assign ex3_sh_lvl3[101] = (~(ex3_sh16_r1_b[101] & ex3_sh16_r2_b[101] & ex3_sh16_r3_b[101])); + assign ex3_sh_lvl3[102] = (~(ex3_sh16_r1_b[102] & ex3_sh16_r2_b[102] & ex3_sh16_r3_b[102])); + assign ex3_sh_lvl3[103] = (~(ex3_sh16_r1_b[103] & ex3_sh16_r2_b[103] & ex3_sh16_r3_b[103])); + assign ex3_sh_lvl3[104] = (~(ex3_sh16_r1_b[104] & ex3_sh16_r2_b[104] & ex3_sh16_r3_b[104])); + assign ex3_sh_lvl3[105] = (~(ex3_sh16_r1_b[105] & ex3_sh16_r2_b[105] & ex3_sh16_r3_b[105])); + assign ex3_sh_lvl3[106] = (~(ex3_sh16_r1_b[106] & ex3_sh16_r2_b[106] & ex3_sh16_r3_b[106])); + assign ex3_sh_lvl3[107] = (~(ex3_sh16_r1_b[107] & ex3_sh16_r2_b[107] & ex3_sh16_r3_b[107])); + assign ex3_sh_lvl3[108] = (~(ex3_sh16_r1_b[108] & ex3_sh16_r2_b[108] & ex3_sh16_r3_b[108])); + assign ex3_sh_lvl3[109] = (~(ex3_sh16_r1_b[109] & ex3_sh16_r2_b[109] & ex3_sh16_r3_b[109])); + assign ex3_sh_lvl3[110] = (~(ex3_sh16_r1_b[110] & ex3_sh16_r2_b[110] & ex3_sh16_r3_b[110])); + assign ex3_sh_lvl3[111] = (~(ex3_sh16_r1_b[111] & ex3_sh16_r2_b[111] & ex3_sh16_r3_b[111])); + assign ex3_sh_lvl3[112] = (~(ex3_sh16_r1_b[112] & ex3_sh16_r2_b[112] & ex3_sh16_r3_b[112])); + assign ex3_sh_lvl3[113] = (~(ex3_sh16_r1_b[113] & ex3_sh16_r2_b[113] & ex3_sh16_r3_b[113])); + assign ex3_sh_lvl3[114] = (~(ex3_sh16_r1_b[114] & ex3_sh16_r2_b[114] & ex3_sh16_r3_b[114])); + assign ex3_sh_lvl3[115] = (~(ex3_sh16_r1_b[115] & ex3_sh16_r2_b[115] & ex3_sh16_r3_b[115])); + assign ex3_sh_lvl3[116] = (~(ex3_sh16_r1_b[116] & ex3_sh16_r2_b[116] & ex3_sh16_r3_b[116])); + assign ex3_sh_lvl3[117] = (~(ex3_sh16_r1_b[117] & ex3_sh16_r2_b[117] & ex3_sh16_r3_b[117])); + assign ex3_sh_lvl3[118] = (~(ex3_sh16_r1_b[118] & ex3_sh16_r2_b[118] & ex3_sh16_r3_b[118])); + assign ex3_sh_lvl3[119] = (~(ex3_sh16_r1_b[119] & ex3_sh16_r2_b[119] & ex3_sh16_r3_b[119])); + assign ex3_sh_lvl3[120] = (~(ex3_sh16_r1_b[120] & ex3_sh16_r2_b[120] & ex3_sh16_r3_b[120])); + assign ex3_sh_lvl3[121] = (~(ex3_sh16_r1_b[121] & ex3_sh16_r2_b[121] & ex3_sh16_r3_b[121])); + assign ex3_sh_lvl3[122] = (~(ex3_sh16_r1_b[122] & ex3_sh16_r2_b[122] & ex3_sh16_r3_b[122])); + assign ex3_sh_lvl3[123] = (~(ex3_sh16_r1_b[123] & ex3_sh16_r2_b[123] & ex3_sh16_r3_b[123])); + assign ex3_sh_lvl3[124] = (~(ex3_sh16_r1_b[124] & ex3_sh16_r2_b[124] & ex3_sh16_r3_b[124])); + assign ex3_sh_lvl3[125] = (~(ex3_sh16_r1_b[125] & ex3_sh16_r2_b[125] & ex3_sh16_r3_b[125])); + assign ex3_sh_lvl3[126] = (~(ex3_sh16_r1_b[126] & ex3_sh16_r2_b[126] & ex3_sh16_r3_b[126])); + assign ex3_sh_lvl3[127] = (~(ex3_sh16_r1_b[127] & ex3_sh16_r2_b[127] & ex3_sh16_r3_b[127])); + assign ex3_sh_lvl3[128] = (~(ex3_sh16_r1_b[128] & ex3_sh16_r2_b[128] & ex3_sh16_r3_b[128])); + assign ex3_sh_lvl3[129] = (~(ex3_sh16_r1_b[129] & ex3_sh16_r2_b[129] & ex3_sh16_r3_b[129])); + assign ex3_sh_lvl3[130] = (~(ex3_sh16_r1_b[130] & ex3_sh16_r2_b[130] & ex3_sh16_r3_b[130])); + assign ex3_sh_lvl3[131] = (~(ex3_sh16_r1_b[131] & ex3_sh16_r2_b[131] & ex3_sh16_r3_b[131])); + assign ex3_sh_lvl3[132] = (~(ex3_sh16_r1_b[132] & ex3_sh16_r2_b[132] & ex3_sh16_r3_b[132])); + assign ex3_sh_lvl3[133] = (~(ex3_sh16_r1_b[133] & ex3_sh16_r2_b[133] & ex3_sh16_r3_b[133])); + assign ex3_sh_lvl3[134] = (~(ex3_sh16_r1_b[134] & ex3_sh16_r2_b[134] & ex3_sh16_r3_b[134])); + assign ex3_sh_lvl3[135] = (~(ex3_sh16_r1_b[135] & ex3_sh16_r2_b[135] & ex3_sh16_r3_b[135])); + assign ex3_sh_lvl3[136] = (~(ex3_sh16_r1_b[136] & ex3_sh16_r2_b[136] & ex3_sh16_r3_b[136])); + assign ex3_sh_lvl3[137] = (~(ex3_sh16_r1_b[137] & ex3_sh16_r2_b[137] & ex3_sh16_r3_b[137])); + assign ex3_sh_lvl3[138] = (~(ex3_sh16_r1_b[138] & ex3_sh16_r2_b[138] & ex3_sh16_r3_b[138])); + assign ex3_sh_lvl3[139] = (~(ex3_sh16_r1_b[139] & ex3_sh16_r2_b[139] & ex3_sh16_r3_b[139])); + assign ex3_sh_lvl3[140] = (~(ex3_sh16_r1_b[140] & ex3_sh16_r2_b[140] & ex3_sh16_r3_b[140])); + assign ex3_sh_lvl3[141] = (~(ex3_sh16_r1_b[141] & ex3_sh16_r2_b[141] & ex3_sh16_r3_b[141])); + assign ex3_sh_lvl3[142] = (~(ex3_sh16_r1_b[142] & ex3_sh16_r2_b[142] & ex3_sh16_r3_b[142])); + assign ex3_sh_lvl3[143] = (~(ex3_sh16_r1_b[143] & ex3_sh16_r2_b[143] & ex3_sh16_r3_b[143])); + assign ex3_sh_lvl3[144] = (~(ex3_sh16_r1_b[144] & ex3_sh16_r2_b[144] & ex3_sh16_r3_b[144])); + assign ex3_sh_lvl3[145] = (~(ex3_sh16_r1_b[145] & ex3_sh16_r2_b[145] & ex3_sh16_r3_b[145])); + assign ex3_sh_lvl3[146] = (~(ex3_sh16_r1_b[146] & ex3_sh16_r2_b[146] & ex3_sh16_r3_b[146])); + assign ex3_sh_lvl3[147] = (~(ex3_sh16_r1_b[147] & ex3_sh16_r2_b[147] & ex3_sh16_r3_b[147])); + assign ex3_sh_lvl3[148] = (~(ex3_sh16_r1_b[148] & ex3_sh16_r2_b[148] & ex3_sh16_r3_b[148])); + assign ex3_sh_lvl3[149] = (~(ex3_sh16_r1_b[149] & ex3_sh16_r2_b[149] & ex3_sh16_r3_b[149])); + assign ex3_sh_lvl3[150] = (~(ex3_sh16_r1_b[150] & ex3_sh16_r2_b[150] & ex3_sh16_r3_b[150])); + assign ex3_sh_lvl3[151] = (~(ex3_sh16_r1_b[151] & ex3_sh16_r2_b[151] & ex3_sh16_r3_b[151])); + assign ex3_sh_lvl3[152] = (~(ex3_sh16_r1_b[152] & ex3_sh16_r2_b[152] & ex3_sh16_r3_b[152])); + assign ex3_sh_lvl3[153] = (~(ex3_sh16_r1_b[153] & ex3_sh16_r2_b[153] & ex3_sh16_r3_b[153])); + assign ex3_sh_lvl3[154] = (~(ex3_sh16_r1_b[154] & ex3_sh16_r2_b[154] & ex3_sh16_r3_b[154])); + assign ex3_sh_lvl3[155] = (~(ex3_sh16_r1_b[155] & ex3_sh16_r2_b[155] & ex3_sh16_r3_b[155])); + assign ex3_sh_lvl3[156] = (~(ex3_sh16_r1_b[156] & ex3_sh16_r2_b[156] & ex3_sh16_r3_b[156])); + assign ex3_sh_lvl3[157] = (~(ex3_sh16_r1_b[157] & ex3_sh16_r2_b[157] & ex3_sh16_r3_b[157])); + assign ex3_sh_lvl3[158] = (~(ex3_sh16_r1_b[158] & ex3_sh16_r2_b[158] & ex3_sh16_r3_b[158])); + assign ex3_sh_lvl3[159] = (~(ex3_sh16_r1_b[159] & ex3_sh16_r2_b[159] & ex3_sh16_r3_b[159])); + assign ex3_sh_lvl3[160] = (~(ex3_sh16_r1_b[160] & ex3_sh16_r2_b[160] & ex3_sh16_r3_b[160])); + assign ex3_sh_lvl3[161] = (~(ex3_sh16_r1_b[161] & ex3_sh16_r2_b[161] & ex3_sh16_r3_b[161])); + assign ex3_sh_lvl3[162] = (~(ex3_sh16_r1_b[162] & ex3_sh16_r2_b[162] & ex3_sh16_r3_b[162])); + + //-------------------------------------- + // replicated logic for sticky bit + //-------------------------------------- + + assign ex3_sh16_r3_162_b = (~((ex3_lvl3_shdcd160 & ex3_sh_lvl2[2]) | (ex3_sel_special & ex3_special[162]))); + assign ex3_sh16_r3_163_b = (~(ex3_lvl3_shdcd160 & ex3_sh_lvl2[3])); + + assign ex3_sh16_r2_162_b = (~((ex3_lvl3_shdcd128 & ex3_sh_lvl2[34]) | (ex3_lvl3_shdcd144 & ex3_sh_lvl2[18]))); + assign ex3_sh16_r2_163_b = (~((ex3_lvl3_shdcd128 & ex3_sh_lvl2[35]) | (ex3_lvl3_shdcd144 & ex3_sh_lvl2[19]))); + + assign ex3_sh16_r1_162_b = (~((ex3_lvl3_shdcd096 & ex3_sh_lvl2[66]) | (ex3_lvl3_shdcd112 & ex3_sh_lvl2[50]))); + assign ex3_sh16_r1_163_b = (~((ex3_lvl3_shdcd096 & ex3_sh_lvl2[67]) | (ex3_lvl3_shdcd112 & ex3_sh_lvl2[51]))); + + assign ex3_sh16_162 = (~(ex3_sh16_r1_162_b & ex3_sh16_r2_162_b & ex3_sh16_r3_162_b)); + assign ex3_sh16_163 = (~(ex3_sh16_r1_163_b & ex3_sh16_r2_163_b & ex3_sh16_r3_163_b)); + +endmodule diff --git a/dev/verilog/work/fu_alg_sh4.v b/dev/verilog/work/fu_alg_sh4.v new file mode 100755 index 0000000..531c8ab --- /dev/null +++ b/dev/verilog/work/fu_alg_sh4.v @@ -0,0 +1,691 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + + `include "tri_a2o.vh" + +module fu_alg_sh4( + ex2_lvl1_shdcd000_b, + ex2_lvl1_shdcd001_b, + ex2_lvl1_shdcd002_b, + ex2_lvl1_shdcd003_b, + ex2_lvl2_shdcd000, + ex2_lvl2_shdcd004, + ex2_lvl2_shdcd008, + ex2_lvl2_shdcd012, + ex2_sel_special, + ex2_b_sign, + ex2_b_expo, + ex2_b_frac, + ex2_sh_lvl2 +); + //--------- SHIFT CONTROLS ----------------- + input ex2_lvl1_shdcd000_b; + input ex2_lvl1_shdcd001_b; + input ex2_lvl1_shdcd002_b; + input ex2_lvl1_shdcd003_b; + input ex2_lvl2_shdcd000; + input ex2_lvl2_shdcd004; + input ex2_lvl2_shdcd008; + input ex2_lvl2_shdcd012; + input ex2_sel_special; + + //--------- SHIFT DATA ----------------- + input ex2_b_sign; + input [3:13] ex2_b_expo; + input [0:52] ex2_b_frac; + + //-------- SHIFT OUTPUT --------------- + output [0:67] ex2_sh_lvl2; + + // ENTITY + + + parameter tiup = 1'b1; + parameter tidn = 1'b0; + + wire [0:63] ex2_special_fcfid; + wire [0:55] ex2_sh_lv1; + wire [0:53] ex2_sh_lv1x_b; + wire [2:55] ex2_sh_lv1y_b; + wire [0:59] ex2_sh_lv2x_b; + wire [8:67] ex2_sh_lv2y_b; + wire [0:63] ex2_sh_lv2z_b; + + // signal sh1v1dcd0_cp1_b :std_ulogic;--decode signals + wire sh1v2dcd0_cp1; + wire sh1v3dcd0_cp1_b; + wire sh1v3dcd0_cp2_b; + wire sh1v4dcd0_cp1; + wire sh1v4dcd0_cp2; + wire sh1v4dcd0_cp3; + wire sh1v4dcd0_cp4; + // signal sh1v1dcd1_cp1_b :std_ulogic; + wire sh1v2dcd1_cp1; + wire sh1v3dcd1_cp1_b; + wire sh1v3dcd1_cp2_b; + wire sh1v4dcd1_cp1; + wire sh1v4dcd1_cp2; + wire sh1v4dcd1_cp3; + wire sh1v4dcd1_cp4; + // signal sh1v1dcd2_cp1_b :std_ulogic; + wire sh1v2dcd2_cp1; + wire sh1v3dcd2_cp1_b; + wire sh1v3dcd2_cp2_b; + wire sh1v4dcd2_cp1; + wire sh1v4dcd2_cp2; + wire sh1v4dcd2_cp3; + wire sh1v4dcd2_cp4; + // signal sh1v1dcd3_cp1_b :std_ulogic; + wire sh1v2dcd3_cp1; + wire sh1v3dcd3_cp1_b; + wire sh1v3dcd3_cp2_b; + wire sh1v4dcd3_cp1; + wire sh1v4dcd3_cp2; + wire sh1v4dcd3_cp3; + wire sh1v4dcd3_cp4; + wire sh2v1dcd00_cp1_b; + wire sh2v2dcd00_cp1; + wire sh2v3dcd00_cp1_b; + wire sh2v3dcd00_cp2_b; + wire sh2v4dcd00_cp1; + wire sh2v4dcd00_cp2; + wire sh2v4dcd00_cp3; + wire sh2v4dcd00_cp4; + wire sh2v1dcd04_cp1_b; + wire sh2v2dcd04_cp1; + wire sh2v3dcd04_cp1_b; + wire sh2v3dcd04_cp2_b; + wire sh2v4dcd04_cp1; + wire sh2v4dcd04_cp2; + wire sh2v4dcd04_cp3; + wire sh2v4dcd04_cp4; + wire sh2v1dcd08_cp1_b; + wire sh2v2dcd08_cp1; + wire sh2v3dcd08_cp1_b; + wire sh2v3dcd08_cp2_b; + wire sh2v4dcd08_cp1; + wire sh2v4dcd08_cp2; + wire sh2v4dcd08_cp3; + wire sh2v4dcd08_cp4; + wire sh2v1dcd12_cp1_b; + wire sh2v2dcd12_cp1; + wire sh2v3dcd12_cp1_b; + wire sh2v3dcd12_cp2_b; + wire sh2v4dcd12_cp1; + wire sh2v4dcd12_cp2; + wire sh2v4dcd12_cp3; + wire sh2v4dcd12_cp4; + wire sh2v1dcdpp_cp1_b; + wire sh2v2dcdpp_cp1; + wire sh2v3dcdpp_cp1_b; + wire sh2v3dcdpp_cp2_b; + wire sh2v4dcdpp_cp1; + wire sh2v4dcdpp_cp2; + wire sh2v4dcdpp_cp3; + wire sh2v4dcdpp_cp4; + + + + //#------------------------------------------------- + //# adjust B for fcfid specials + //#------------------------------------------------- + // if implicit bit is off: exponent should be 0 instead of x001, x381 (1/897) + // frac(0) is the implicit bit. + // 0_0000_0000_0001 1 + // 0_0011_1000_0001 897 + + assign ex2_special_fcfid[0] = ex2_b_sign; // fcfid integer + assign ex2_special_fcfid[1] = ex2_b_expo[3]; + assign ex2_special_fcfid[2] = ex2_b_expo[4] & ex2_b_frac[0]; + assign ex2_special_fcfid[3] = ex2_b_expo[5] & ex2_b_frac[0]; + assign ex2_special_fcfid[4] = ex2_b_expo[6] & ex2_b_frac[0]; + assign ex2_special_fcfid[5] = ex2_b_expo[7]; + assign ex2_special_fcfid[6] = ex2_b_expo[8]; + assign ex2_special_fcfid[7] = ex2_b_expo[9]; + assign ex2_special_fcfid[8] = ex2_b_expo[10]; + assign ex2_special_fcfid[9] = ex2_b_expo[11]; + assign ex2_special_fcfid[10] = ex2_b_expo[12]; + assign ex2_special_fcfid[11] = ex2_b_expo[13] & ex2_b_frac[0]; + assign ex2_special_fcfid[12:63] = ex2_b_frac[1:52]; // fcfid integer + + //#--------------------------------------- + //# repower the selects for sh 0/1/2/3 + //#--------------------------------------- + + + assign sh1v2dcd0_cp1 = (~ex2_lvl1_shdcd000_b); + assign sh1v3dcd0_cp1_b = (~sh1v2dcd0_cp1); + assign sh1v3dcd0_cp2_b = (~sh1v2dcd0_cp1); + assign sh1v4dcd0_cp1 = (~sh1v3dcd0_cp1_b); //drive 0:13 + assign sh1v4dcd0_cp2 = (~sh1v3dcd0_cp1_b); //drive 14:27 + assign sh1v4dcd0_cp3 = (~sh1v3dcd0_cp2_b); //drive 28:41 + assign sh1v4dcd0_cp4 = (~sh1v3dcd0_cp2_b); //drive 42:55 + + assign sh1v2dcd1_cp1 = (~ex2_lvl1_shdcd001_b); + assign sh1v3dcd1_cp1_b = (~sh1v2dcd1_cp1); + assign sh1v3dcd1_cp2_b = (~sh1v2dcd1_cp1); + assign sh1v4dcd1_cp1 = (~sh1v3dcd1_cp1_b); //drive 0:13 + assign sh1v4dcd1_cp2 = (~sh1v3dcd1_cp1_b); //drive 14:27 + assign sh1v4dcd1_cp3 = (~sh1v3dcd1_cp2_b); //drive 28:41 + assign sh1v4dcd1_cp4 = (~sh1v3dcd1_cp2_b); //drive 42:55 + + assign sh1v2dcd2_cp1 = (~ex2_lvl1_shdcd002_b); + assign sh1v3dcd2_cp1_b = (~sh1v2dcd2_cp1); + assign sh1v3dcd2_cp2_b = (~sh1v2dcd2_cp1); + assign sh1v4dcd2_cp1 = (~sh1v3dcd2_cp1_b); //drive 0:13 + assign sh1v4dcd2_cp2 = (~sh1v3dcd2_cp1_b); //drive 14:27 + assign sh1v4dcd2_cp3 = (~sh1v3dcd2_cp2_b); //drive 28:41 + assign sh1v4dcd2_cp4 = (~sh1v3dcd2_cp2_b); //drive 42:55 + + assign sh1v2dcd3_cp1 = (~ex2_lvl1_shdcd003_b); + assign sh1v3dcd3_cp1_b = (~sh1v2dcd3_cp1); + assign sh1v3dcd3_cp2_b = (~sh1v2dcd3_cp1); + assign sh1v4dcd3_cp1 = (~sh1v3dcd3_cp1_b); //drive 0:13 + assign sh1v4dcd3_cp2 = (~sh1v3dcd3_cp1_b); //drive 14:27 + assign sh1v4dcd3_cp3 = (~sh1v3dcd3_cp2_b); //drive 28:41 + assign sh1v4dcd3_cp4 = (~sh1v3dcd3_cp2_b); //drive 42:55 + + //#--------------------------------------- + //# repower the selects for sh 0/4/8/12 + //#--------------------------------------- + + assign sh2v1dcd00_cp1_b = (~ex2_lvl2_shdcd000); + assign sh2v2dcd00_cp1 = (~sh2v1dcd00_cp1_b); + assign sh2v3dcd00_cp1_b = (~sh2v2dcd00_cp1); + assign sh2v3dcd00_cp2_b = (~sh2v2dcd00_cp1); + assign sh2v4dcd00_cp1 = (~sh2v3dcd00_cp1_b); //drive 0:16 + assign sh2v4dcd00_cp2 = (~sh2v3dcd00_cp1_b); //drive 17:33 + assign sh2v4dcd00_cp3 = (~sh2v3dcd00_cp2_b); //drive 34:50 + assign sh2v4dcd00_cp4 = (~sh2v3dcd00_cp2_b); //drive 57:67 + + assign sh2v1dcd04_cp1_b = (~ex2_lvl2_shdcd004); + assign sh2v2dcd04_cp1 = (~sh2v1dcd04_cp1_b); + assign sh2v3dcd04_cp1_b = (~sh2v2dcd04_cp1); + assign sh2v3dcd04_cp2_b = (~sh2v2dcd04_cp1); + assign sh2v4dcd04_cp1 = (~sh2v3dcd04_cp1_b); //drive 0:16 + assign sh2v4dcd04_cp2 = (~sh2v3dcd04_cp1_b); //drive 17:33 + assign sh2v4dcd04_cp3 = (~sh2v3dcd04_cp2_b); //drive 34:50 + assign sh2v4dcd04_cp4 = (~sh2v3dcd04_cp2_b); //drive 57:67 + + assign sh2v1dcd08_cp1_b = (~ex2_lvl2_shdcd008); + assign sh2v2dcd08_cp1 = (~sh2v1dcd08_cp1_b); + assign sh2v3dcd08_cp1_b = (~sh2v2dcd08_cp1); + assign sh2v3dcd08_cp2_b = (~sh2v2dcd08_cp1); + assign sh2v4dcd08_cp1 = (~sh2v3dcd08_cp1_b); //drive 0:16 + assign sh2v4dcd08_cp2 = (~sh2v3dcd08_cp1_b); //drive 17:33 + assign sh2v4dcd08_cp3 = (~sh2v3dcd08_cp2_b); //drive 34:50 + assign sh2v4dcd08_cp4 = (~sh2v3dcd08_cp2_b); //drive 57:67 + + assign sh2v1dcd12_cp1_b = (~ex2_lvl2_shdcd012); + assign sh2v2dcd12_cp1 = (~sh2v1dcd12_cp1_b); + assign sh2v3dcd12_cp1_b = (~sh2v2dcd12_cp1); + assign sh2v3dcd12_cp2_b = (~sh2v2dcd12_cp1); + assign sh2v4dcd12_cp1 = (~sh2v3dcd12_cp1_b); //drive 0:16 + assign sh2v4dcd12_cp2 = (~sh2v3dcd12_cp1_b); //drive 17:33 + assign sh2v4dcd12_cp3 = (~sh2v3dcd12_cp2_b); //drive 34:50 + assign sh2v4dcd12_cp4 = (~sh2v3dcd12_cp2_b); //drive 57:67 + + assign sh2v1dcdpp_cp1_b = (~ex2_sel_special); + assign sh2v2dcdpp_cp1 = (~sh2v1dcdpp_cp1_b); + assign sh2v3dcdpp_cp1_b = (~sh2v2dcdpp_cp1); + assign sh2v3dcdpp_cp2_b = (~sh2v2dcdpp_cp1); + assign sh2v4dcdpp_cp1 = (~sh2v3dcdpp_cp1_b); //drive 0:16 + assign sh2v4dcdpp_cp2 = (~sh2v3dcdpp_cp1_b); //drive 17:33 + assign sh2v4dcdpp_cp3 = (~sh2v3dcdpp_cp2_b); //drive 34:50 + assign sh2v4dcdpp_cp4 = (~sh2v3dcdpp_cp2_b); //drive 57:67 + + //------------------------------------- + + assign ex2_sh_lv1x_b[0] = (~(sh1v4dcd0_cp1 & ex2_b_frac[0])); + assign ex2_sh_lv1x_b[1] = (~((sh1v4dcd0_cp1 & ex2_b_frac[1]) | (sh1v4dcd1_cp1 & ex2_b_frac[0]))); + assign ex2_sh_lv1x_b[2] = (~((sh1v4dcd0_cp1 & ex2_b_frac[2]) | (sh1v4dcd1_cp1 & ex2_b_frac[1]))); + assign ex2_sh_lv1x_b[3] = (~((sh1v4dcd0_cp1 & ex2_b_frac[3]) | (sh1v4dcd1_cp1 & ex2_b_frac[2]))); + assign ex2_sh_lv1x_b[4] = (~((sh1v4dcd0_cp1 & ex2_b_frac[4]) | (sh1v4dcd1_cp1 & ex2_b_frac[3]))); + assign ex2_sh_lv1x_b[5] = (~((sh1v4dcd0_cp1 & ex2_b_frac[5]) | (sh1v4dcd1_cp1 & ex2_b_frac[4]))); + assign ex2_sh_lv1x_b[6] = (~((sh1v4dcd0_cp1 & ex2_b_frac[6]) | (sh1v4dcd1_cp1 & ex2_b_frac[5]))); + assign ex2_sh_lv1x_b[7] = (~((sh1v4dcd0_cp1 & ex2_b_frac[7]) | (sh1v4dcd1_cp1 & ex2_b_frac[6]))); + assign ex2_sh_lv1x_b[8] = (~((sh1v4dcd0_cp1 & ex2_b_frac[8]) | (sh1v4dcd1_cp1 & ex2_b_frac[7]))); + assign ex2_sh_lv1x_b[9] = (~((sh1v4dcd0_cp1 & ex2_b_frac[9]) | (sh1v4dcd1_cp1 & ex2_b_frac[8]))); + assign ex2_sh_lv1x_b[10] = (~((sh1v4dcd0_cp1 & ex2_b_frac[10]) | (sh1v4dcd1_cp1 & ex2_b_frac[9]))); + assign ex2_sh_lv1x_b[11] = (~((sh1v4dcd0_cp1 & ex2_b_frac[11]) | (sh1v4dcd1_cp1 & ex2_b_frac[10]))); + assign ex2_sh_lv1x_b[12] = (~((sh1v4dcd0_cp1 & ex2_b_frac[12]) | (sh1v4dcd1_cp1 & ex2_b_frac[11]))); + assign ex2_sh_lv1x_b[13] = (~((sh1v4dcd0_cp1 & ex2_b_frac[13]) | (sh1v4dcd1_cp1 & ex2_b_frac[12]))); + assign ex2_sh_lv1x_b[14] = (~((sh1v4dcd0_cp2 & ex2_b_frac[14]) | (sh1v4dcd1_cp2 & ex2_b_frac[13]))); + assign ex2_sh_lv1x_b[15] = (~((sh1v4dcd0_cp2 & ex2_b_frac[15]) | (sh1v4dcd1_cp2 & ex2_b_frac[14]))); + assign ex2_sh_lv1x_b[16] = (~((sh1v4dcd0_cp2 & ex2_b_frac[16]) | (sh1v4dcd1_cp2 & ex2_b_frac[15]))); + assign ex2_sh_lv1x_b[17] = (~((sh1v4dcd0_cp2 & ex2_b_frac[17]) | (sh1v4dcd1_cp2 & ex2_b_frac[16]))); + assign ex2_sh_lv1x_b[18] = (~((sh1v4dcd0_cp2 & ex2_b_frac[18]) | (sh1v4dcd1_cp2 & ex2_b_frac[17]))); + assign ex2_sh_lv1x_b[19] = (~((sh1v4dcd0_cp2 & ex2_b_frac[19]) | (sh1v4dcd1_cp2 & ex2_b_frac[18]))); + assign ex2_sh_lv1x_b[20] = (~((sh1v4dcd0_cp2 & ex2_b_frac[20]) | (sh1v4dcd1_cp2 & ex2_b_frac[19]))); + assign ex2_sh_lv1x_b[21] = (~((sh1v4dcd0_cp2 & ex2_b_frac[21]) | (sh1v4dcd1_cp2 & ex2_b_frac[20]))); + assign ex2_sh_lv1x_b[22] = (~((sh1v4dcd0_cp2 & ex2_b_frac[22]) | (sh1v4dcd1_cp2 & ex2_b_frac[21]))); + assign ex2_sh_lv1x_b[23] = (~((sh1v4dcd0_cp2 & ex2_b_frac[23]) | (sh1v4dcd1_cp2 & ex2_b_frac[22]))); + assign ex2_sh_lv1x_b[24] = (~((sh1v4dcd0_cp2 & ex2_b_frac[24]) | (sh1v4dcd1_cp2 & ex2_b_frac[23]))); + assign ex2_sh_lv1x_b[25] = (~((sh1v4dcd0_cp2 & ex2_b_frac[25]) | (sh1v4dcd1_cp2 & ex2_b_frac[24]))); + assign ex2_sh_lv1x_b[26] = (~((sh1v4dcd0_cp2 & ex2_b_frac[26]) | (sh1v4dcd1_cp2 & ex2_b_frac[25]))); + assign ex2_sh_lv1x_b[27] = (~((sh1v4dcd0_cp2 & ex2_b_frac[27]) | (sh1v4dcd1_cp2 & ex2_b_frac[26]))); + assign ex2_sh_lv1x_b[28] = (~((sh1v4dcd0_cp3 & ex2_b_frac[28]) | (sh1v4dcd1_cp3 & ex2_b_frac[27]))); + assign ex2_sh_lv1x_b[29] = (~((sh1v4dcd0_cp3 & ex2_b_frac[29]) | (sh1v4dcd1_cp3 & ex2_b_frac[28]))); + assign ex2_sh_lv1x_b[30] = (~((sh1v4dcd0_cp3 & ex2_b_frac[30]) | (sh1v4dcd1_cp3 & ex2_b_frac[29]))); + assign ex2_sh_lv1x_b[31] = (~((sh1v4dcd0_cp3 & ex2_b_frac[31]) | (sh1v4dcd1_cp3 & ex2_b_frac[30]))); + assign ex2_sh_lv1x_b[32] = (~((sh1v4dcd0_cp3 & ex2_b_frac[32]) | (sh1v4dcd1_cp3 & ex2_b_frac[31]))); + assign ex2_sh_lv1x_b[33] = (~((sh1v4dcd0_cp3 & ex2_b_frac[33]) | (sh1v4dcd1_cp3 & ex2_b_frac[32]))); + assign ex2_sh_lv1x_b[34] = (~((sh1v4dcd0_cp3 & ex2_b_frac[34]) | (sh1v4dcd1_cp3 & ex2_b_frac[33]))); + assign ex2_sh_lv1x_b[35] = (~((sh1v4dcd0_cp3 & ex2_b_frac[35]) | (sh1v4dcd1_cp3 & ex2_b_frac[34]))); + assign ex2_sh_lv1x_b[36] = (~((sh1v4dcd0_cp3 & ex2_b_frac[36]) | (sh1v4dcd1_cp3 & ex2_b_frac[35]))); + assign ex2_sh_lv1x_b[37] = (~((sh1v4dcd0_cp3 & ex2_b_frac[37]) | (sh1v4dcd1_cp3 & ex2_b_frac[36]))); + assign ex2_sh_lv1x_b[38] = (~((sh1v4dcd0_cp3 & ex2_b_frac[38]) | (sh1v4dcd1_cp3 & ex2_b_frac[37]))); + assign ex2_sh_lv1x_b[39] = (~((sh1v4dcd0_cp3 & ex2_b_frac[39]) | (sh1v4dcd1_cp3 & ex2_b_frac[38]))); + assign ex2_sh_lv1x_b[40] = (~((sh1v4dcd0_cp3 & ex2_b_frac[40]) | (sh1v4dcd1_cp3 & ex2_b_frac[39]))); + assign ex2_sh_lv1x_b[41] = (~((sh1v4dcd0_cp3 & ex2_b_frac[41]) | (sh1v4dcd1_cp3 & ex2_b_frac[40]))); + assign ex2_sh_lv1x_b[42] = (~((sh1v4dcd0_cp4 & ex2_b_frac[42]) | (sh1v4dcd1_cp4 & ex2_b_frac[41]))); + assign ex2_sh_lv1x_b[43] = (~((sh1v4dcd0_cp4 & ex2_b_frac[43]) | (sh1v4dcd1_cp4 & ex2_b_frac[42]))); + assign ex2_sh_lv1x_b[44] = (~((sh1v4dcd0_cp4 & ex2_b_frac[44]) | (sh1v4dcd1_cp4 & ex2_b_frac[43]))); + assign ex2_sh_lv1x_b[45] = (~((sh1v4dcd0_cp4 & ex2_b_frac[45]) | (sh1v4dcd1_cp4 & ex2_b_frac[44]))); + assign ex2_sh_lv1x_b[46] = (~((sh1v4dcd0_cp4 & ex2_b_frac[46]) | (sh1v4dcd1_cp4 & ex2_b_frac[45]))); + assign ex2_sh_lv1x_b[47] = (~((sh1v4dcd0_cp4 & ex2_b_frac[47]) | (sh1v4dcd1_cp4 & ex2_b_frac[46]))); + assign ex2_sh_lv1x_b[48] = (~((sh1v4dcd0_cp4 & ex2_b_frac[48]) | (sh1v4dcd1_cp4 & ex2_b_frac[47]))); + assign ex2_sh_lv1x_b[49] = (~((sh1v4dcd0_cp4 & ex2_b_frac[49]) | (sh1v4dcd1_cp4 & ex2_b_frac[48]))); + assign ex2_sh_lv1x_b[50] = (~((sh1v4dcd0_cp4 & ex2_b_frac[50]) | (sh1v4dcd1_cp4 & ex2_b_frac[49]))); + assign ex2_sh_lv1x_b[51] = (~((sh1v4dcd0_cp4 & ex2_b_frac[51]) | (sh1v4dcd1_cp4 & ex2_b_frac[50]))); + assign ex2_sh_lv1x_b[52] = (~((sh1v4dcd0_cp4 & ex2_b_frac[52]) | (sh1v4dcd1_cp4 & ex2_b_frac[51]))); + assign ex2_sh_lv1x_b[53] = (~(sh1v4dcd1_cp4 & ex2_b_frac[52])); + + assign ex2_sh_lv1y_b[2] = (~(sh1v4dcd2_cp1 & ex2_b_frac[0])); + assign ex2_sh_lv1y_b[3] = (~((sh1v4dcd2_cp1 & ex2_b_frac[1]) | (sh1v4dcd3_cp1 & ex2_b_frac[0]))); + assign ex2_sh_lv1y_b[4] = (~((sh1v4dcd2_cp1 & ex2_b_frac[2]) | (sh1v4dcd3_cp1 & ex2_b_frac[1]))); + assign ex2_sh_lv1y_b[5] = (~((sh1v4dcd2_cp1 & ex2_b_frac[3]) | (sh1v4dcd3_cp1 & ex2_b_frac[2]))); + assign ex2_sh_lv1y_b[6] = (~((sh1v4dcd2_cp1 & ex2_b_frac[4]) | (sh1v4dcd3_cp1 & ex2_b_frac[3]))); + assign ex2_sh_lv1y_b[7] = (~((sh1v4dcd2_cp1 & ex2_b_frac[5]) | (sh1v4dcd3_cp1 & ex2_b_frac[4]))); + assign ex2_sh_lv1y_b[8] = (~((sh1v4dcd2_cp1 & ex2_b_frac[6]) | (sh1v4dcd3_cp1 & ex2_b_frac[5]))); + assign ex2_sh_lv1y_b[9] = (~((sh1v4dcd2_cp1 & ex2_b_frac[7]) | (sh1v4dcd3_cp1 & ex2_b_frac[6]))); + assign ex2_sh_lv1y_b[10] = (~((sh1v4dcd2_cp1 & ex2_b_frac[8]) | (sh1v4dcd3_cp1 & ex2_b_frac[7]))); + assign ex2_sh_lv1y_b[11] = (~((sh1v4dcd2_cp1 & ex2_b_frac[9]) | (sh1v4dcd3_cp1 & ex2_b_frac[8]))); + assign ex2_sh_lv1y_b[12] = (~((sh1v4dcd2_cp1 & ex2_b_frac[10]) | (sh1v4dcd3_cp1 & ex2_b_frac[9]))); + assign ex2_sh_lv1y_b[13] = (~((sh1v4dcd2_cp1 & ex2_b_frac[11]) | (sh1v4dcd3_cp1 & ex2_b_frac[10]))); + assign ex2_sh_lv1y_b[14] = (~((sh1v4dcd2_cp2 & ex2_b_frac[12]) | (sh1v4dcd3_cp2 & ex2_b_frac[11]))); + assign ex2_sh_lv1y_b[15] = (~((sh1v4dcd2_cp2 & ex2_b_frac[13]) | (sh1v4dcd3_cp2 & ex2_b_frac[12]))); + assign ex2_sh_lv1y_b[16] = (~((sh1v4dcd2_cp2 & ex2_b_frac[14]) | (sh1v4dcd3_cp2 & ex2_b_frac[13]))); + assign ex2_sh_lv1y_b[17] = (~((sh1v4dcd2_cp2 & ex2_b_frac[15]) | (sh1v4dcd3_cp2 & ex2_b_frac[14]))); + assign ex2_sh_lv1y_b[18] = (~((sh1v4dcd2_cp2 & ex2_b_frac[16]) | (sh1v4dcd3_cp2 & ex2_b_frac[15]))); + assign ex2_sh_lv1y_b[19] = (~((sh1v4dcd2_cp2 & ex2_b_frac[17]) | (sh1v4dcd3_cp2 & ex2_b_frac[16]))); + assign ex2_sh_lv1y_b[20] = (~((sh1v4dcd2_cp2 & ex2_b_frac[18]) | (sh1v4dcd3_cp2 & ex2_b_frac[17]))); + assign ex2_sh_lv1y_b[21] = (~((sh1v4dcd2_cp2 & ex2_b_frac[19]) | (sh1v4dcd3_cp2 & ex2_b_frac[18]))); + assign ex2_sh_lv1y_b[22] = (~((sh1v4dcd2_cp2 & ex2_b_frac[20]) | (sh1v4dcd3_cp2 & ex2_b_frac[19]))); + assign ex2_sh_lv1y_b[23] = (~((sh1v4dcd2_cp2 & ex2_b_frac[21]) | (sh1v4dcd3_cp2 & ex2_b_frac[20]))); + assign ex2_sh_lv1y_b[24] = (~((sh1v4dcd2_cp2 & ex2_b_frac[22]) | (sh1v4dcd3_cp2 & ex2_b_frac[21]))); + assign ex2_sh_lv1y_b[25] = (~((sh1v4dcd2_cp2 & ex2_b_frac[23]) | (sh1v4dcd3_cp2 & ex2_b_frac[22]))); + assign ex2_sh_lv1y_b[26] = (~((sh1v4dcd2_cp2 & ex2_b_frac[24]) | (sh1v4dcd3_cp2 & ex2_b_frac[23]))); + assign ex2_sh_lv1y_b[27] = (~((sh1v4dcd2_cp2 & ex2_b_frac[25]) | (sh1v4dcd3_cp2 & ex2_b_frac[24]))); + assign ex2_sh_lv1y_b[28] = (~((sh1v4dcd2_cp3 & ex2_b_frac[26]) | (sh1v4dcd3_cp3 & ex2_b_frac[25]))); + assign ex2_sh_lv1y_b[29] = (~((sh1v4dcd2_cp3 & ex2_b_frac[27]) | (sh1v4dcd3_cp3 & ex2_b_frac[26]))); + assign ex2_sh_lv1y_b[30] = (~((sh1v4dcd2_cp3 & ex2_b_frac[28]) | (sh1v4dcd3_cp3 & ex2_b_frac[27]))); + assign ex2_sh_lv1y_b[31] = (~((sh1v4dcd2_cp3 & ex2_b_frac[29]) | (sh1v4dcd3_cp3 & ex2_b_frac[28]))); + assign ex2_sh_lv1y_b[32] = (~((sh1v4dcd2_cp3 & ex2_b_frac[30]) | (sh1v4dcd3_cp3 & ex2_b_frac[29]))); + assign ex2_sh_lv1y_b[33] = (~((sh1v4dcd2_cp3 & ex2_b_frac[31]) | (sh1v4dcd3_cp3 & ex2_b_frac[30]))); + assign ex2_sh_lv1y_b[34] = (~((sh1v4dcd2_cp3 & ex2_b_frac[32]) | (sh1v4dcd3_cp3 & ex2_b_frac[31]))); + assign ex2_sh_lv1y_b[35] = (~((sh1v4dcd2_cp3 & ex2_b_frac[33]) | (sh1v4dcd3_cp3 & ex2_b_frac[32]))); + assign ex2_sh_lv1y_b[36] = (~((sh1v4dcd2_cp3 & ex2_b_frac[34]) | (sh1v4dcd3_cp3 & ex2_b_frac[33]))); + assign ex2_sh_lv1y_b[37] = (~((sh1v4dcd2_cp3 & ex2_b_frac[35]) | (sh1v4dcd3_cp3 & ex2_b_frac[34]))); + assign ex2_sh_lv1y_b[38] = (~((sh1v4dcd2_cp3 & ex2_b_frac[36]) | (sh1v4dcd3_cp3 & ex2_b_frac[35]))); + assign ex2_sh_lv1y_b[39] = (~((sh1v4dcd2_cp3 & ex2_b_frac[37]) | (sh1v4dcd3_cp3 & ex2_b_frac[36]))); + assign ex2_sh_lv1y_b[40] = (~((sh1v4dcd2_cp3 & ex2_b_frac[38]) | (sh1v4dcd3_cp3 & ex2_b_frac[37]))); + assign ex2_sh_lv1y_b[41] = (~((sh1v4dcd2_cp4 & ex2_b_frac[39]) | (sh1v4dcd3_cp4 & ex2_b_frac[38]))); + assign ex2_sh_lv1y_b[42] = (~((sh1v4dcd2_cp4 & ex2_b_frac[40]) | (sh1v4dcd3_cp4 & ex2_b_frac[39]))); + assign ex2_sh_lv1y_b[43] = (~((sh1v4dcd2_cp4 & ex2_b_frac[41]) | (sh1v4dcd3_cp4 & ex2_b_frac[40]))); + assign ex2_sh_lv1y_b[44] = (~((sh1v4dcd2_cp4 & ex2_b_frac[42]) | (sh1v4dcd3_cp4 & ex2_b_frac[41]))); + assign ex2_sh_lv1y_b[45] = (~((sh1v4dcd2_cp4 & ex2_b_frac[43]) | (sh1v4dcd3_cp4 & ex2_b_frac[42]))); + assign ex2_sh_lv1y_b[46] = (~((sh1v4dcd2_cp4 & ex2_b_frac[44]) | (sh1v4dcd3_cp4 & ex2_b_frac[43]))); + assign ex2_sh_lv1y_b[47] = (~((sh1v4dcd2_cp4 & ex2_b_frac[45]) | (sh1v4dcd3_cp4 & ex2_b_frac[44]))); + assign ex2_sh_lv1y_b[48] = (~((sh1v4dcd2_cp4 & ex2_b_frac[46]) | (sh1v4dcd3_cp4 & ex2_b_frac[45]))); + assign ex2_sh_lv1y_b[49] = (~((sh1v4dcd2_cp4 & ex2_b_frac[47]) | (sh1v4dcd3_cp4 & ex2_b_frac[46]))); + assign ex2_sh_lv1y_b[50] = (~((sh1v4dcd2_cp4 & ex2_b_frac[48]) | (sh1v4dcd3_cp4 & ex2_b_frac[47]))); + assign ex2_sh_lv1y_b[51] = (~((sh1v4dcd2_cp4 & ex2_b_frac[49]) | (sh1v4dcd3_cp4 & ex2_b_frac[48]))); + assign ex2_sh_lv1y_b[52] = (~((sh1v4dcd2_cp4 & ex2_b_frac[50]) | (sh1v4dcd3_cp4 & ex2_b_frac[49]))); + assign ex2_sh_lv1y_b[53] = (~((sh1v4dcd2_cp4 & ex2_b_frac[51]) | (sh1v4dcd3_cp4 & ex2_b_frac[50]))); + assign ex2_sh_lv1y_b[54] = (~((sh1v4dcd2_cp4 & ex2_b_frac[52]) | (sh1v4dcd3_cp4 & ex2_b_frac[51]))); + assign ex2_sh_lv1y_b[55] = (~(sh1v4dcd3_cp4 & ex2_b_frac[52])); + + assign ex2_sh_lv1[0] = (~(ex2_sh_lv1x_b[0])); + assign ex2_sh_lv1[1] = (~(ex2_sh_lv1x_b[1])); + assign ex2_sh_lv1[2] = (~(ex2_sh_lv1x_b[2] & ex2_sh_lv1y_b[2])); + assign ex2_sh_lv1[3] = (~(ex2_sh_lv1x_b[3] & ex2_sh_lv1y_b[3])); + assign ex2_sh_lv1[4] = (~(ex2_sh_lv1x_b[4] & ex2_sh_lv1y_b[4])); + assign ex2_sh_lv1[5] = (~(ex2_sh_lv1x_b[5] & ex2_sh_lv1y_b[5])); + assign ex2_sh_lv1[6] = (~(ex2_sh_lv1x_b[6] & ex2_sh_lv1y_b[6])); + assign ex2_sh_lv1[7] = (~(ex2_sh_lv1x_b[7] & ex2_sh_lv1y_b[7])); + assign ex2_sh_lv1[8] = (~(ex2_sh_lv1x_b[8] & ex2_sh_lv1y_b[8])); + assign ex2_sh_lv1[9] = (~(ex2_sh_lv1x_b[9] & ex2_sh_lv1y_b[9])); + assign ex2_sh_lv1[10] = (~(ex2_sh_lv1x_b[10] & ex2_sh_lv1y_b[10])); + assign ex2_sh_lv1[11] = (~(ex2_sh_lv1x_b[11] & ex2_sh_lv1y_b[11])); + assign ex2_sh_lv1[12] = (~(ex2_sh_lv1x_b[12] & ex2_sh_lv1y_b[12])); + assign ex2_sh_lv1[13] = (~(ex2_sh_lv1x_b[13] & ex2_sh_lv1y_b[13])); + assign ex2_sh_lv1[14] = (~(ex2_sh_lv1x_b[14] & ex2_sh_lv1y_b[14])); + assign ex2_sh_lv1[15] = (~(ex2_sh_lv1x_b[15] & ex2_sh_lv1y_b[15])); + assign ex2_sh_lv1[16] = (~(ex2_sh_lv1x_b[16] & ex2_sh_lv1y_b[16])); + assign ex2_sh_lv1[17] = (~(ex2_sh_lv1x_b[17] & ex2_sh_lv1y_b[17])); + assign ex2_sh_lv1[18] = (~(ex2_sh_lv1x_b[18] & ex2_sh_lv1y_b[18])); + assign ex2_sh_lv1[19] = (~(ex2_sh_lv1x_b[19] & ex2_sh_lv1y_b[19])); + assign ex2_sh_lv1[20] = (~(ex2_sh_lv1x_b[20] & ex2_sh_lv1y_b[20])); + assign ex2_sh_lv1[21] = (~(ex2_sh_lv1x_b[21] & ex2_sh_lv1y_b[21])); + assign ex2_sh_lv1[22] = (~(ex2_sh_lv1x_b[22] & ex2_sh_lv1y_b[22])); + assign ex2_sh_lv1[23] = (~(ex2_sh_lv1x_b[23] & ex2_sh_lv1y_b[23])); + assign ex2_sh_lv1[24] = (~(ex2_sh_lv1x_b[24] & ex2_sh_lv1y_b[24])); + assign ex2_sh_lv1[25] = (~(ex2_sh_lv1x_b[25] & ex2_sh_lv1y_b[25])); + assign ex2_sh_lv1[26] = (~(ex2_sh_lv1x_b[26] & ex2_sh_lv1y_b[26])); + assign ex2_sh_lv1[27] = (~(ex2_sh_lv1x_b[27] & ex2_sh_lv1y_b[27])); + assign ex2_sh_lv1[28] = (~(ex2_sh_lv1x_b[28] & ex2_sh_lv1y_b[28])); + assign ex2_sh_lv1[29] = (~(ex2_sh_lv1x_b[29] & ex2_sh_lv1y_b[29])); + assign ex2_sh_lv1[30] = (~(ex2_sh_lv1x_b[30] & ex2_sh_lv1y_b[30])); + assign ex2_sh_lv1[31] = (~(ex2_sh_lv1x_b[31] & ex2_sh_lv1y_b[31])); + assign ex2_sh_lv1[32] = (~(ex2_sh_lv1x_b[32] & ex2_sh_lv1y_b[32])); + assign ex2_sh_lv1[33] = (~(ex2_sh_lv1x_b[33] & ex2_sh_lv1y_b[33])); + assign ex2_sh_lv1[34] = (~(ex2_sh_lv1x_b[34] & ex2_sh_lv1y_b[34])); + assign ex2_sh_lv1[35] = (~(ex2_sh_lv1x_b[35] & ex2_sh_lv1y_b[35])); + assign ex2_sh_lv1[36] = (~(ex2_sh_lv1x_b[36] & ex2_sh_lv1y_b[36])); + assign ex2_sh_lv1[37] = (~(ex2_sh_lv1x_b[37] & ex2_sh_lv1y_b[37])); + assign ex2_sh_lv1[38] = (~(ex2_sh_lv1x_b[38] & ex2_sh_lv1y_b[38])); + assign ex2_sh_lv1[39] = (~(ex2_sh_lv1x_b[39] & ex2_sh_lv1y_b[39])); + assign ex2_sh_lv1[40] = (~(ex2_sh_lv1x_b[40] & ex2_sh_lv1y_b[40])); + assign ex2_sh_lv1[41] = (~(ex2_sh_lv1x_b[41] & ex2_sh_lv1y_b[41])); + assign ex2_sh_lv1[42] = (~(ex2_sh_lv1x_b[42] & ex2_sh_lv1y_b[42])); + assign ex2_sh_lv1[43] = (~(ex2_sh_lv1x_b[43] & ex2_sh_lv1y_b[43])); + assign ex2_sh_lv1[44] = (~(ex2_sh_lv1x_b[44] & ex2_sh_lv1y_b[44])); + assign ex2_sh_lv1[45] = (~(ex2_sh_lv1x_b[45] & ex2_sh_lv1y_b[45])); + assign ex2_sh_lv1[46] = (~(ex2_sh_lv1x_b[46] & ex2_sh_lv1y_b[46])); + assign ex2_sh_lv1[47] = (~(ex2_sh_lv1x_b[47] & ex2_sh_lv1y_b[47])); + assign ex2_sh_lv1[48] = (~(ex2_sh_lv1x_b[48] & ex2_sh_lv1y_b[48])); + assign ex2_sh_lv1[49] = (~(ex2_sh_lv1x_b[49] & ex2_sh_lv1y_b[49])); + assign ex2_sh_lv1[50] = (~(ex2_sh_lv1x_b[50] & ex2_sh_lv1y_b[50])); + assign ex2_sh_lv1[51] = (~(ex2_sh_lv1x_b[51] & ex2_sh_lv1y_b[51])); + assign ex2_sh_lv1[52] = (~(ex2_sh_lv1x_b[52] & ex2_sh_lv1y_b[52])); + assign ex2_sh_lv1[53] = (~(ex2_sh_lv1x_b[53] & ex2_sh_lv1y_b[53])); + assign ex2_sh_lv1[54] = (~(ex2_sh_lv1y_b[54])); + assign ex2_sh_lv1[55] = (~(ex2_sh_lv1y_b[55])); + + //-------------------------------------------------------------------------------------------- + + assign ex2_sh_lv2x_b[0] = (~(sh2v4dcd00_cp1 & ex2_sh_lv1[0])); + assign ex2_sh_lv2x_b[1] = (~(sh2v4dcd00_cp1 & ex2_sh_lv1[1])); + assign ex2_sh_lv2x_b[2] = (~(sh2v4dcd00_cp1 & ex2_sh_lv1[2])); + assign ex2_sh_lv2x_b[3] = (~(sh2v4dcd00_cp1 & ex2_sh_lv1[3])); + assign ex2_sh_lv2x_b[4] = (~((sh2v4dcd00_cp1 & ex2_sh_lv1[4]) | (sh2v4dcd04_cp1 & ex2_sh_lv1[0]))); + assign ex2_sh_lv2x_b[5] = (~((sh2v4dcd00_cp1 & ex2_sh_lv1[5]) | (sh2v4dcd04_cp1 & ex2_sh_lv1[1]))); + assign ex2_sh_lv2x_b[6] = (~((sh2v4dcd00_cp1 & ex2_sh_lv1[6]) | (sh2v4dcd04_cp1 & ex2_sh_lv1[2]))); + assign ex2_sh_lv2x_b[7] = (~((sh2v4dcd00_cp1 & ex2_sh_lv1[7]) | (sh2v4dcd04_cp1 & ex2_sh_lv1[3]))); + assign ex2_sh_lv2x_b[8] = (~((sh2v4dcd00_cp1 & ex2_sh_lv1[8]) | (sh2v4dcd04_cp1 & ex2_sh_lv1[4]))); + assign ex2_sh_lv2x_b[9] = (~((sh2v4dcd00_cp1 & ex2_sh_lv1[9]) | (sh2v4dcd04_cp1 & ex2_sh_lv1[5]))); + assign ex2_sh_lv2x_b[10] = (~((sh2v4dcd00_cp1 & ex2_sh_lv1[10]) | (sh2v4dcd04_cp1 & ex2_sh_lv1[6]))); + assign ex2_sh_lv2x_b[11] = (~((sh2v4dcd00_cp1 & ex2_sh_lv1[11]) | (sh2v4dcd04_cp1 & ex2_sh_lv1[7]))); + assign ex2_sh_lv2x_b[12] = (~((sh2v4dcd00_cp1 & ex2_sh_lv1[12]) | (sh2v4dcd04_cp1 & ex2_sh_lv1[8]))); + assign ex2_sh_lv2x_b[13] = (~((sh2v4dcd00_cp1 & ex2_sh_lv1[13]) | (sh2v4dcd04_cp1 & ex2_sh_lv1[9]))); + assign ex2_sh_lv2x_b[14] = (~((sh2v4dcd00_cp1 & ex2_sh_lv1[14]) | (sh2v4dcd04_cp1 & ex2_sh_lv1[10]))); + assign ex2_sh_lv2x_b[15] = (~((sh2v4dcd00_cp2 & ex2_sh_lv1[15]) | (sh2v4dcd04_cp2 & ex2_sh_lv1[11]))); + assign ex2_sh_lv2x_b[16] = (~((sh2v4dcd00_cp2 & ex2_sh_lv1[16]) | (sh2v4dcd04_cp2 & ex2_sh_lv1[12]))); + assign ex2_sh_lv2x_b[17] = (~((sh2v4dcd00_cp2 & ex2_sh_lv1[17]) | (sh2v4dcd04_cp2 & ex2_sh_lv1[13]))); + assign ex2_sh_lv2x_b[18] = (~((sh2v4dcd00_cp2 & ex2_sh_lv1[18]) | (sh2v4dcd04_cp2 & ex2_sh_lv1[14]))); + assign ex2_sh_lv2x_b[19] = (~((sh2v4dcd00_cp2 & ex2_sh_lv1[19]) | (sh2v4dcd04_cp2 & ex2_sh_lv1[15]))); + assign ex2_sh_lv2x_b[20] = (~((sh2v4dcd00_cp2 & ex2_sh_lv1[20]) | (sh2v4dcd04_cp2 & ex2_sh_lv1[16]))); // + assign ex2_sh_lv2x_b[21] = (~((sh2v4dcd00_cp2 & ex2_sh_lv1[21]) | (sh2v4dcd04_cp2 & ex2_sh_lv1[17]))); + assign ex2_sh_lv2x_b[22] = (~((sh2v4dcd00_cp2 & ex2_sh_lv1[22]) | (sh2v4dcd04_cp2 & ex2_sh_lv1[18]))); + assign ex2_sh_lv2x_b[23] = (~((sh2v4dcd00_cp2 & ex2_sh_lv1[23]) | (sh2v4dcd04_cp2 & ex2_sh_lv1[19]))); + assign ex2_sh_lv2x_b[24] = (~((sh2v4dcd00_cp2 & ex2_sh_lv1[24]) | (sh2v4dcd04_cp2 & ex2_sh_lv1[20]))); + assign ex2_sh_lv2x_b[25] = (~((sh2v4dcd00_cp2 & ex2_sh_lv1[25]) | (sh2v4dcd04_cp2 & ex2_sh_lv1[21]))); + assign ex2_sh_lv2x_b[26] = (~((sh2v4dcd00_cp2 & ex2_sh_lv1[26]) | (sh2v4dcd04_cp2 & ex2_sh_lv1[22]))); + assign ex2_sh_lv2x_b[27] = (~((sh2v4dcd00_cp2 & ex2_sh_lv1[27]) | (sh2v4dcd04_cp2 & ex2_sh_lv1[23]))); + assign ex2_sh_lv2x_b[28] = (~((sh2v4dcd00_cp2 & ex2_sh_lv1[28]) | (sh2v4dcd04_cp2 & ex2_sh_lv1[24]))); + assign ex2_sh_lv2x_b[29] = (~((sh2v4dcd00_cp2 & ex2_sh_lv1[29]) | (sh2v4dcd04_cp2 & ex2_sh_lv1[25]))); + assign ex2_sh_lv2x_b[30] = (~((sh2v4dcd00_cp3 & ex2_sh_lv1[30]) | (sh2v4dcd04_cp3 & ex2_sh_lv1[26]))); + assign ex2_sh_lv2x_b[31] = (~((sh2v4dcd00_cp3 & ex2_sh_lv1[31]) | (sh2v4dcd04_cp3 & ex2_sh_lv1[27]))); + assign ex2_sh_lv2x_b[32] = (~((sh2v4dcd00_cp3 & ex2_sh_lv1[32]) | (sh2v4dcd04_cp3 & ex2_sh_lv1[28]))); + assign ex2_sh_lv2x_b[33] = (~((sh2v4dcd00_cp3 & ex2_sh_lv1[33]) | (sh2v4dcd04_cp3 & ex2_sh_lv1[29]))); + assign ex2_sh_lv2x_b[34] = (~((sh2v4dcd00_cp3 & ex2_sh_lv1[34]) | (sh2v4dcd04_cp3 & ex2_sh_lv1[30]))); + assign ex2_sh_lv2x_b[35] = (~((sh2v4dcd00_cp3 & ex2_sh_lv1[35]) | (sh2v4dcd04_cp3 & ex2_sh_lv1[31]))); + assign ex2_sh_lv2x_b[36] = (~((sh2v4dcd00_cp3 & ex2_sh_lv1[36]) | (sh2v4dcd04_cp3 & ex2_sh_lv1[32]))); + assign ex2_sh_lv2x_b[37] = (~((sh2v4dcd00_cp3 & ex2_sh_lv1[37]) | (sh2v4dcd04_cp3 & ex2_sh_lv1[33]))); + assign ex2_sh_lv2x_b[38] = (~((sh2v4dcd00_cp3 & ex2_sh_lv1[38]) | (sh2v4dcd04_cp3 & ex2_sh_lv1[34]))); + assign ex2_sh_lv2x_b[39] = (~((sh2v4dcd00_cp3 & ex2_sh_lv1[39]) | (sh2v4dcd04_cp3 & ex2_sh_lv1[35]))); + assign ex2_sh_lv2x_b[40] = (~((sh2v4dcd00_cp3 & ex2_sh_lv1[40]) | (sh2v4dcd04_cp3 & ex2_sh_lv1[36]))); + assign ex2_sh_lv2x_b[41] = (~((sh2v4dcd00_cp3 & ex2_sh_lv1[41]) | (sh2v4dcd04_cp3 & ex2_sh_lv1[37]))); + assign ex2_sh_lv2x_b[42] = (~((sh2v4dcd00_cp3 & ex2_sh_lv1[42]) | (sh2v4dcd04_cp3 & ex2_sh_lv1[38]))); + assign ex2_sh_lv2x_b[43] = (~((sh2v4dcd00_cp3 & ex2_sh_lv1[43]) | (sh2v4dcd04_cp3 & ex2_sh_lv1[39]))); + assign ex2_sh_lv2x_b[44] = (~((sh2v4dcd00_cp3 & ex2_sh_lv1[44]) | (sh2v4dcd04_cp3 & ex2_sh_lv1[40]))); + assign ex2_sh_lv2x_b[45] = (~((sh2v4dcd00_cp4 & ex2_sh_lv1[45]) | (sh2v4dcd04_cp4 & ex2_sh_lv1[41]))); + assign ex2_sh_lv2x_b[46] = (~((sh2v4dcd00_cp4 & ex2_sh_lv1[46]) | (sh2v4dcd04_cp4 & ex2_sh_lv1[42]))); + assign ex2_sh_lv2x_b[47] = (~((sh2v4dcd00_cp4 & ex2_sh_lv1[47]) | (sh2v4dcd04_cp4 & ex2_sh_lv1[43]))); + assign ex2_sh_lv2x_b[48] = (~((sh2v4dcd00_cp4 & ex2_sh_lv1[48]) | (sh2v4dcd04_cp4 & ex2_sh_lv1[44]))); + assign ex2_sh_lv2x_b[49] = (~((sh2v4dcd00_cp4 & ex2_sh_lv1[49]) | (sh2v4dcd04_cp4 & ex2_sh_lv1[45]))); + assign ex2_sh_lv2x_b[50] = (~((sh2v4dcd00_cp4 & ex2_sh_lv1[50]) | (sh2v4dcd04_cp4 & ex2_sh_lv1[46]))); + assign ex2_sh_lv2x_b[51] = (~((sh2v4dcd00_cp4 & ex2_sh_lv1[51]) | (sh2v4dcd04_cp4 & ex2_sh_lv1[47]))); + assign ex2_sh_lv2x_b[52] = (~((sh2v4dcd00_cp4 & ex2_sh_lv1[52]) | (sh2v4dcd04_cp4 & ex2_sh_lv1[48]))); + assign ex2_sh_lv2x_b[53] = (~((sh2v4dcd00_cp4 & ex2_sh_lv1[53]) | (sh2v4dcd04_cp4 & ex2_sh_lv1[49]))); + assign ex2_sh_lv2x_b[54] = (~((sh2v4dcd00_cp4 & ex2_sh_lv1[54]) | (sh2v4dcd04_cp4 & ex2_sh_lv1[50]))); + assign ex2_sh_lv2x_b[55] = (~((sh2v4dcd00_cp4 & ex2_sh_lv1[55]) | (sh2v4dcd04_cp4 & ex2_sh_lv1[51]))); + assign ex2_sh_lv2x_b[56] = (~(sh2v4dcd04_cp4 & ex2_sh_lv1[52])); + assign ex2_sh_lv2x_b[57] = (~(sh2v4dcd04_cp4 & ex2_sh_lv1[53])); + assign ex2_sh_lv2x_b[58] = (~(sh2v4dcd04_cp4 & ex2_sh_lv1[54])); + assign ex2_sh_lv2x_b[59] = (~(sh2v4dcd04_cp4 & ex2_sh_lv1[55])); + + assign ex2_sh_lv2y_b[8] = (~(sh2v4dcd08_cp1 & ex2_sh_lv1[0])); + assign ex2_sh_lv2y_b[9] = (~(sh2v4dcd08_cp1 & ex2_sh_lv1[1])); + assign ex2_sh_lv2y_b[10] = (~(sh2v4dcd08_cp1 & ex2_sh_lv1[2])); + assign ex2_sh_lv2y_b[11] = (~(sh2v4dcd08_cp1 & ex2_sh_lv1[3])); + assign ex2_sh_lv2y_b[12] = (~((sh2v4dcd08_cp1 & ex2_sh_lv1[4]) | (sh2v4dcd12_cp1 & ex2_sh_lv1[0]))); + assign ex2_sh_lv2y_b[13] = (~((sh2v4dcd08_cp1 & ex2_sh_lv1[5]) | (sh2v4dcd12_cp1 & ex2_sh_lv1[1]))); + assign ex2_sh_lv2y_b[14] = (~((sh2v4dcd08_cp1 & ex2_sh_lv1[6]) | (sh2v4dcd12_cp1 & ex2_sh_lv1[2]))); + assign ex2_sh_lv2y_b[15] = (~((sh2v4dcd08_cp1 & ex2_sh_lv1[7]) | (sh2v4dcd12_cp1 & ex2_sh_lv1[3]))); + assign ex2_sh_lv2y_b[16] = (~((sh2v4dcd08_cp1 & ex2_sh_lv1[8]) | (sh2v4dcd12_cp1 & ex2_sh_lv1[4]))); + assign ex2_sh_lv2y_b[17] = (~((sh2v4dcd08_cp1 & ex2_sh_lv1[9]) | (sh2v4dcd12_cp1 & ex2_sh_lv1[5]))); + assign ex2_sh_lv2y_b[18] = (~((sh2v4dcd08_cp1 & ex2_sh_lv1[10]) | (sh2v4dcd12_cp1 & ex2_sh_lv1[6]))); + assign ex2_sh_lv2y_b[19] = (~((sh2v4dcd08_cp1 & ex2_sh_lv1[11]) | (sh2v4dcd12_cp1 & ex2_sh_lv1[7]))); + assign ex2_sh_lv2y_b[20] = (~((sh2v4dcd08_cp1 & ex2_sh_lv1[12]) | (sh2v4dcd12_cp1 & ex2_sh_lv1[8]))); + assign ex2_sh_lv2y_b[21] = (~((sh2v4dcd08_cp1 & ex2_sh_lv1[13]) | (sh2v4dcd12_cp1 & ex2_sh_lv1[9]))); + assign ex2_sh_lv2y_b[22] = (~((sh2v4dcd08_cp2 & ex2_sh_lv1[14]) | (sh2v4dcd12_cp2 & ex2_sh_lv1[10]))); + assign ex2_sh_lv2y_b[23] = (~((sh2v4dcd08_cp2 & ex2_sh_lv1[15]) | (sh2v4dcd12_cp2 & ex2_sh_lv1[11]))); + assign ex2_sh_lv2y_b[24] = (~((sh2v4dcd08_cp2 & ex2_sh_lv1[16]) | (sh2v4dcd12_cp2 & ex2_sh_lv1[12]))); + assign ex2_sh_lv2y_b[25] = (~((sh2v4dcd08_cp2 & ex2_sh_lv1[17]) | (sh2v4dcd12_cp2 & ex2_sh_lv1[13]))); + assign ex2_sh_lv2y_b[26] = (~((sh2v4dcd08_cp2 & ex2_sh_lv1[18]) | (sh2v4dcd12_cp2 & ex2_sh_lv1[14]))); + assign ex2_sh_lv2y_b[27] = (~((sh2v4dcd08_cp2 & ex2_sh_lv1[19]) | (sh2v4dcd12_cp2 & ex2_sh_lv1[15]))); + assign ex2_sh_lv2y_b[28] = (~((sh2v4dcd08_cp2 & ex2_sh_lv1[20]) | (sh2v4dcd12_cp2 & ex2_sh_lv1[16]))); + assign ex2_sh_lv2y_b[29] = (~((sh2v4dcd08_cp2 & ex2_sh_lv1[21]) | (sh2v4dcd12_cp2 & ex2_sh_lv1[17]))); + assign ex2_sh_lv2y_b[30] = (~((sh2v4dcd08_cp2 & ex2_sh_lv1[22]) | (sh2v4dcd12_cp2 & ex2_sh_lv1[18]))); + assign ex2_sh_lv2y_b[31] = (~((sh2v4dcd08_cp2 & ex2_sh_lv1[23]) | (sh2v4dcd12_cp2 & ex2_sh_lv1[19]))); + assign ex2_sh_lv2y_b[32] = (~((sh2v4dcd08_cp2 & ex2_sh_lv1[24]) | (sh2v4dcd12_cp2 & ex2_sh_lv1[20]))); + assign ex2_sh_lv2y_b[33] = (~((sh2v4dcd08_cp2 & ex2_sh_lv1[25]) | (sh2v4dcd12_cp2 & ex2_sh_lv1[21]))); + assign ex2_sh_lv2y_b[34] = (~((sh2v4dcd08_cp2 & ex2_sh_lv1[26]) | (sh2v4dcd12_cp2 & ex2_sh_lv1[22]))); + assign ex2_sh_lv2y_b[35] = (~((sh2v4dcd08_cp2 & ex2_sh_lv1[27]) | (sh2v4dcd12_cp2 & ex2_sh_lv1[23]))); + assign ex2_sh_lv2y_b[36] = (~((sh2v4dcd08_cp2 & ex2_sh_lv1[28]) | (sh2v4dcd12_cp2 & ex2_sh_lv1[24]))); + assign ex2_sh_lv2y_b[37] = (~((sh2v4dcd08_cp3 & ex2_sh_lv1[29]) | (sh2v4dcd12_cp3 & ex2_sh_lv1[25]))); + assign ex2_sh_lv2y_b[38] = (~((sh2v4dcd08_cp3 & ex2_sh_lv1[30]) | (sh2v4dcd12_cp3 & ex2_sh_lv1[26]))); + assign ex2_sh_lv2y_b[39] = (~((sh2v4dcd08_cp3 & ex2_sh_lv1[31]) | (sh2v4dcd12_cp3 & ex2_sh_lv1[27]))); + assign ex2_sh_lv2y_b[40] = (~((sh2v4dcd08_cp3 & ex2_sh_lv1[32]) | (sh2v4dcd12_cp3 & ex2_sh_lv1[28]))); + assign ex2_sh_lv2y_b[41] = (~((sh2v4dcd08_cp3 & ex2_sh_lv1[33]) | (sh2v4dcd12_cp3 & ex2_sh_lv1[29]))); + assign ex2_sh_lv2y_b[42] = (~((sh2v4dcd08_cp3 & ex2_sh_lv1[34]) | (sh2v4dcd12_cp3 & ex2_sh_lv1[30]))); + assign ex2_sh_lv2y_b[43] = (~((sh2v4dcd08_cp3 & ex2_sh_lv1[35]) | (sh2v4dcd12_cp3 & ex2_sh_lv1[31]))); + assign ex2_sh_lv2y_b[44] = (~((sh2v4dcd08_cp3 & ex2_sh_lv1[36]) | (sh2v4dcd12_cp3 & ex2_sh_lv1[32]))); + assign ex2_sh_lv2y_b[45] = (~((sh2v4dcd08_cp3 & ex2_sh_lv1[37]) | (sh2v4dcd12_cp3 & ex2_sh_lv1[33]))); + assign ex2_sh_lv2y_b[46] = (~((sh2v4dcd08_cp3 & ex2_sh_lv1[38]) | (sh2v4dcd12_cp3 & ex2_sh_lv1[34]))); + assign ex2_sh_lv2y_b[47] = (~((sh2v4dcd08_cp3 & ex2_sh_lv1[39]) | (sh2v4dcd12_cp3 & ex2_sh_lv1[35]))); + assign ex2_sh_lv2y_b[48] = (~((sh2v4dcd08_cp3 & ex2_sh_lv1[40]) | (sh2v4dcd12_cp3 & ex2_sh_lv1[36]))); + assign ex2_sh_lv2y_b[49] = (~((sh2v4dcd08_cp3 & ex2_sh_lv1[41]) | (sh2v4dcd12_cp3 & ex2_sh_lv1[37]))); + assign ex2_sh_lv2y_b[50] = (~((sh2v4dcd08_cp3 & ex2_sh_lv1[42]) | (sh2v4dcd12_cp3 & ex2_sh_lv1[38]))); + assign ex2_sh_lv2y_b[51] = (~((sh2v4dcd08_cp3 & ex2_sh_lv1[43]) | (sh2v4dcd12_cp3 & ex2_sh_lv1[39]))); + assign ex2_sh_lv2y_b[52] = (~((sh2v4dcd08_cp4 & ex2_sh_lv1[44]) | (sh2v4dcd12_cp4 & ex2_sh_lv1[40]))); + assign ex2_sh_lv2y_b[53] = (~((sh2v4dcd08_cp4 & ex2_sh_lv1[45]) | (sh2v4dcd12_cp4 & ex2_sh_lv1[41]))); + assign ex2_sh_lv2y_b[54] = (~((sh2v4dcd08_cp4 & ex2_sh_lv1[46]) | (sh2v4dcd12_cp4 & ex2_sh_lv1[42]))); + assign ex2_sh_lv2y_b[55] = (~((sh2v4dcd08_cp4 & ex2_sh_lv1[47]) | (sh2v4dcd12_cp4 & ex2_sh_lv1[43]))); + assign ex2_sh_lv2y_b[56] = (~((sh2v4dcd08_cp4 & ex2_sh_lv1[48]) | (sh2v4dcd12_cp4 & ex2_sh_lv1[44]))); + assign ex2_sh_lv2y_b[57] = (~((sh2v4dcd08_cp4 & ex2_sh_lv1[49]) | (sh2v4dcd12_cp4 & ex2_sh_lv1[45]))); + assign ex2_sh_lv2y_b[58] = (~((sh2v4dcd08_cp4 & ex2_sh_lv1[50]) | (sh2v4dcd12_cp4 & ex2_sh_lv1[46]))); + assign ex2_sh_lv2y_b[59] = (~((sh2v4dcd08_cp4 & ex2_sh_lv1[51]) | (sh2v4dcd12_cp4 & ex2_sh_lv1[47]))); + assign ex2_sh_lv2y_b[60] = (~((sh2v4dcd08_cp4 & ex2_sh_lv1[52]) | (sh2v4dcd12_cp4 & ex2_sh_lv1[48]))); + assign ex2_sh_lv2y_b[61] = (~((sh2v4dcd08_cp4 & ex2_sh_lv1[53]) | (sh2v4dcd12_cp4 & ex2_sh_lv1[49]))); + assign ex2_sh_lv2y_b[62] = (~((sh2v4dcd08_cp4 & ex2_sh_lv1[54]) | (sh2v4dcd12_cp4 & ex2_sh_lv1[50]))); + assign ex2_sh_lv2y_b[63] = (~((sh2v4dcd08_cp4 & ex2_sh_lv1[55]) | (sh2v4dcd12_cp4 & ex2_sh_lv1[51]))); + assign ex2_sh_lv2y_b[64] = (~(sh2v4dcd12_cp4 & ex2_sh_lv1[52])); + assign ex2_sh_lv2y_b[65] = (~(sh2v4dcd12_cp4 & ex2_sh_lv1[53])); + assign ex2_sh_lv2y_b[66] = (~(sh2v4dcd12_cp4 & ex2_sh_lv1[54])); + assign ex2_sh_lv2y_b[67] = (~(sh2v4dcd12_cp4 & ex2_sh_lv1[55])); + + assign ex2_sh_lv2z_b[0] = (~(sh2v4dcdpp_cp1 & ex2_special_fcfid[0])); + assign ex2_sh_lv2z_b[1] = (~(sh2v4dcdpp_cp1 & ex2_special_fcfid[1])); + assign ex2_sh_lv2z_b[2] = (~(sh2v4dcdpp_cp1 & ex2_special_fcfid[2])); + assign ex2_sh_lv2z_b[3] = (~(sh2v4dcdpp_cp1 & ex2_special_fcfid[3])); + assign ex2_sh_lv2z_b[4] = (~(sh2v4dcdpp_cp1 & ex2_special_fcfid[4])); + assign ex2_sh_lv2z_b[5] = (~(sh2v4dcdpp_cp1 & ex2_special_fcfid[5])); + assign ex2_sh_lv2z_b[6] = (~(sh2v4dcdpp_cp1 & ex2_special_fcfid[6])); + assign ex2_sh_lv2z_b[7] = (~(sh2v4dcdpp_cp1 & ex2_special_fcfid[7])); + assign ex2_sh_lv2z_b[8] = (~(sh2v4dcdpp_cp1 & ex2_special_fcfid[8])); + assign ex2_sh_lv2z_b[9] = (~(sh2v4dcdpp_cp1 & ex2_special_fcfid[9])); + assign ex2_sh_lv2z_b[10] = (~(sh2v4dcdpp_cp1 & ex2_special_fcfid[10])); + assign ex2_sh_lv2z_b[11] = (~(sh2v4dcdpp_cp1 & ex2_special_fcfid[11])); + assign ex2_sh_lv2z_b[12] = (~(sh2v4dcdpp_cp1 & ex2_special_fcfid[12])); + assign ex2_sh_lv2z_b[13] = (~(sh2v4dcdpp_cp1 & ex2_special_fcfid[13])); + assign ex2_sh_lv2z_b[14] = (~(sh2v4dcdpp_cp1 & ex2_special_fcfid[14])); + assign ex2_sh_lv2z_b[15] = (~(sh2v4dcdpp_cp1 & ex2_special_fcfid[15])); + assign ex2_sh_lv2z_b[16] = (~(sh2v4dcdpp_cp2 & ex2_special_fcfid[16])); + assign ex2_sh_lv2z_b[17] = (~(sh2v4dcdpp_cp2 & ex2_special_fcfid[17])); + assign ex2_sh_lv2z_b[18] = (~(sh2v4dcdpp_cp2 & ex2_special_fcfid[18])); + assign ex2_sh_lv2z_b[19] = (~(sh2v4dcdpp_cp2 & ex2_special_fcfid[19])); + assign ex2_sh_lv2z_b[20] = (~(sh2v4dcdpp_cp2 & ex2_special_fcfid[20])); + assign ex2_sh_lv2z_b[21] = (~(sh2v4dcdpp_cp2 & ex2_special_fcfid[21])); + assign ex2_sh_lv2z_b[22] = (~(sh2v4dcdpp_cp2 & ex2_special_fcfid[22])); + assign ex2_sh_lv2z_b[23] = (~(sh2v4dcdpp_cp2 & ex2_special_fcfid[23])); + assign ex2_sh_lv2z_b[24] = (~(sh2v4dcdpp_cp2 & ex2_special_fcfid[24])); + assign ex2_sh_lv2z_b[25] = (~(sh2v4dcdpp_cp2 & ex2_special_fcfid[25])); + assign ex2_sh_lv2z_b[26] = (~(sh2v4dcdpp_cp2 & ex2_special_fcfid[26])); + assign ex2_sh_lv2z_b[27] = (~(sh2v4dcdpp_cp2 & ex2_special_fcfid[27])); + assign ex2_sh_lv2z_b[28] = (~(sh2v4dcdpp_cp2 & ex2_special_fcfid[28])); + assign ex2_sh_lv2z_b[29] = (~(sh2v4dcdpp_cp2 & ex2_special_fcfid[29])); + assign ex2_sh_lv2z_b[30] = (~(sh2v4dcdpp_cp2 & ex2_special_fcfid[30])); + assign ex2_sh_lv2z_b[31] = (~(sh2v4dcdpp_cp2 & ex2_special_fcfid[31])); + assign ex2_sh_lv2z_b[32] = (~(sh2v4dcdpp_cp3 & ex2_special_fcfid[32])); + assign ex2_sh_lv2z_b[33] = (~(sh2v4dcdpp_cp3 & ex2_special_fcfid[33])); + assign ex2_sh_lv2z_b[34] = (~(sh2v4dcdpp_cp3 & ex2_special_fcfid[34])); + assign ex2_sh_lv2z_b[35] = (~(sh2v4dcdpp_cp3 & ex2_special_fcfid[35])); + assign ex2_sh_lv2z_b[36] = (~(sh2v4dcdpp_cp3 & ex2_special_fcfid[36])); + assign ex2_sh_lv2z_b[37] = (~(sh2v4dcdpp_cp3 & ex2_special_fcfid[37])); + assign ex2_sh_lv2z_b[38] = (~(sh2v4dcdpp_cp3 & ex2_special_fcfid[38])); + assign ex2_sh_lv2z_b[39] = (~(sh2v4dcdpp_cp3 & ex2_special_fcfid[39])); + assign ex2_sh_lv2z_b[40] = (~(sh2v4dcdpp_cp3 & ex2_special_fcfid[40])); + assign ex2_sh_lv2z_b[41] = (~(sh2v4dcdpp_cp3 & ex2_special_fcfid[41])); + assign ex2_sh_lv2z_b[42] = (~(sh2v4dcdpp_cp3 & ex2_special_fcfid[42])); + assign ex2_sh_lv2z_b[43] = (~(sh2v4dcdpp_cp3 & ex2_special_fcfid[43])); + assign ex2_sh_lv2z_b[44] = (~(sh2v4dcdpp_cp3 & ex2_special_fcfid[44])); + assign ex2_sh_lv2z_b[45] = (~(sh2v4dcdpp_cp3 & ex2_special_fcfid[45])); + assign ex2_sh_lv2z_b[46] = (~(sh2v4dcdpp_cp3 & ex2_special_fcfid[46])); + assign ex2_sh_lv2z_b[47] = (~(sh2v4dcdpp_cp3 & ex2_special_fcfid[47])); + assign ex2_sh_lv2z_b[48] = (~(sh2v4dcdpp_cp4 & ex2_special_fcfid[48])); + assign ex2_sh_lv2z_b[49] = (~(sh2v4dcdpp_cp4 & ex2_special_fcfid[49])); + assign ex2_sh_lv2z_b[50] = (~(sh2v4dcdpp_cp4 & ex2_special_fcfid[50])); + assign ex2_sh_lv2z_b[51] = (~(sh2v4dcdpp_cp4 & ex2_special_fcfid[51])); + assign ex2_sh_lv2z_b[52] = (~(sh2v4dcdpp_cp4 & ex2_special_fcfid[52])); + assign ex2_sh_lv2z_b[53] = (~(sh2v4dcdpp_cp4 & ex2_special_fcfid[53])); + assign ex2_sh_lv2z_b[54] = (~(sh2v4dcdpp_cp4 & ex2_special_fcfid[54])); + assign ex2_sh_lv2z_b[55] = (~(sh2v4dcdpp_cp4 & ex2_special_fcfid[55])); + assign ex2_sh_lv2z_b[56] = (~(sh2v4dcdpp_cp4 & ex2_special_fcfid[56])); + assign ex2_sh_lv2z_b[57] = (~(sh2v4dcdpp_cp4 & ex2_special_fcfid[57])); + assign ex2_sh_lv2z_b[58] = (~(sh2v4dcdpp_cp4 & ex2_special_fcfid[58])); + assign ex2_sh_lv2z_b[59] = (~(sh2v4dcdpp_cp4 & ex2_special_fcfid[59])); + assign ex2_sh_lv2z_b[60] = (~(sh2v4dcdpp_cp4 & ex2_special_fcfid[60])); + assign ex2_sh_lv2z_b[61] = (~(sh2v4dcdpp_cp4 & ex2_special_fcfid[61])); + assign ex2_sh_lv2z_b[62] = (~(sh2v4dcdpp_cp4 & ex2_special_fcfid[62])); + assign ex2_sh_lv2z_b[63] = (~(sh2v4dcdpp_cp4 & ex2_special_fcfid[63])); + + assign ex2_sh_lvl2[00] = (~(ex2_sh_lv2x_b[00] & ex2_sh_lv2z_b[00])); + assign ex2_sh_lvl2[01] = (~(ex2_sh_lv2x_b[01] & ex2_sh_lv2z_b[01])); + assign ex2_sh_lvl2[02] = (~(ex2_sh_lv2x_b[02] & ex2_sh_lv2z_b[02])); + assign ex2_sh_lvl2[03] = (~(ex2_sh_lv2x_b[03] & ex2_sh_lv2z_b[03])); + assign ex2_sh_lvl2[04] = (~(ex2_sh_lv2x_b[04] & ex2_sh_lv2z_b[04])); + assign ex2_sh_lvl2[05] = (~(ex2_sh_lv2x_b[05] & ex2_sh_lv2z_b[05])); + assign ex2_sh_lvl2[06] = (~(ex2_sh_lv2x_b[06] & ex2_sh_lv2z_b[06])); + assign ex2_sh_lvl2[07] = (~(ex2_sh_lv2x_b[07] & ex2_sh_lv2z_b[07])); + assign ex2_sh_lvl2[08] = (~(ex2_sh_lv2x_b[08] & ex2_sh_lv2y_b[08] & ex2_sh_lv2z_b[08])); + assign ex2_sh_lvl2[09] = (~(ex2_sh_lv2x_b[09] & ex2_sh_lv2y_b[09] & ex2_sh_lv2z_b[09])); + assign ex2_sh_lvl2[10] = (~(ex2_sh_lv2x_b[10] & ex2_sh_lv2y_b[10] & ex2_sh_lv2z_b[10])); + assign ex2_sh_lvl2[11] = (~(ex2_sh_lv2x_b[11] & ex2_sh_lv2y_b[11] & ex2_sh_lv2z_b[11])); + assign ex2_sh_lvl2[12] = (~(ex2_sh_lv2x_b[12] & ex2_sh_lv2y_b[12] & ex2_sh_lv2z_b[12])); + assign ex2_sh_lvl2[13] = (~(ex2_sh_lv2x_b[13] & ex2_sh_lv2y_b[13] & ex2_sh_lv2z_b[13])); + assign ex2_sh_lvl2[14] = (~(ex2_sh_lv2x_b[14] & ex2_sh_lv2y_b[14] & ex2_sh_lv2z_b[14])); + assign ex2_sh_lvl2[15] = (~(ex2_sh_lv2x_b[15] & ex2_sh_lv2y_b[15] & ex2_sh_lv2z_b[15])); + assign ex2_sh_lvl2[16] = (~(ex2_sh_lv2x_b[16] & ex2_sh_lv2y_b[16] & ex2_sh_lv2z_b[16])); + assign ex2_sh_lvl2[17] = (~(ex2_sh_lv2x_b[17] & ex2_sh_lv2y_b[17] & ex2_sh_lv2z_b[17])); + assign ex2_sh_lvl2[18] = (~(ex2_sh_lv2x_b[18] & ex2_sh_lv2y_b[18] & ex2_sh_lv2z_b[18])); + assign ex2_sh_lvl2[19] = (~(ex2_sh_lv2x_b[19] & ex2_sh_lv2y_b[19] & ex2_sh_lv2z_b[19])); + assign ex2_sh_lvl2[20] = (~(ex2_sh_lv2x_b[20] & ex2_sh_lv2y_b[20] & ex2_sh_lv2z_b[20])); + assign ex2_sh_lvl2[21] = (~(ex2_sh_lv2x_b[21] & ex2_sh_lv2y_b[21] & ex2_sh_lv2z_b[21])); + assign ex2_sh_lvl2[22] = (~(ex2_sh_lv2x_b[22] & ex2_sh_lv2y_b[22] & ex2_sh_lv2z_b[22])); + assign ex2_sh_lvl2[23] = (~(ex2_sh_lv2x_b[23] & ex2_sh_lv2y_b[23] & ex2_sh_lv2z_b[23])); + assign ex2_sh_lvl2[24] = (~(ex2_sh_lv2x_b[24] & ex2_sh_lv2y_b[24] & ex2_sh_lv2z_b[24])); + assign ex2_sh_lvl2[25] = (~(ex2_sh_lv2x_b[25] & ex2_sh_lv2y_b[25] & ex2_sh_lv2z_b[25])); + assign ex2_sh_lvl2[26] = (~(ex2_sh_lv2x_b[26] & ex2_sh_lv2y_b[26] & ex2_sh_lv2z_b[26])); + assign ex2_sh_lvl2[27] = (~(ex2_sh_lv2x_b[27] & ex2_sh_lv2y_b[27] & ex2_sh_lv2z_b[27])); + assign ex2_sh_lvl2[28] = (~(ex2_sh_lv2x_b[28] & ex2_sh_lv2y_b[28] & ex2_sh_lv2z_b[28])); + assign ex2_sh_lvl2[29] = (~(ex2_sh_lv2x_b[29] & ex2_sh_lv2y_b[29] & ex2_sh_lv2z_b[29])); + assign ex2_sh_lvl2[30] = (~(ex2_sh_lv2x_b[30] & ex2_sh_lv2y_b[30] & ex2_sh_lv2z_b[30])); + assign ex2_sh_lvl2[31] = (~(ex2_sh_lv2x_b[31] & ex2_sh_lv2y_b[31] & ex2_sh_lv2z_b[31])); + assign ex2_sh_lvl2[32] = (~(ex2_sh_lv2x_b[32] & ex2_sh_lv2y_b[32] & ex2_sh_lv2z_b[32])); + assign ex2_sh_lvl2[33] = (~(ex2_sh_lv2x_b[33] & ex2_sh_lv2y_b[33] & ex2_sh_lv2z_b[33])); + assign ex2_sh_lvl2[34] = (~(ex2_sh_lv2x_b[34] & ex2_sh_lv2y_b[34] & ex2_sh_lv2z_b[34])); + assign ex2_sh_lvl2[35] = (~(ex2_sh_lv2x_b[35] & ex2_sh_lv2y_b[35] & ex2_sh_lv2z_b[35])); + assign ex2_sh_lvl2[36] = (~(ex2_sh_lv2x_b[36] & ex2_sh_lv2y_b[36] & ex2_sh_lv2z_b[36])); + assign ex2_sh_lvl2[37] = (~(ex2_sh_lv2x_b[37] & ex2_sh_lv2y_b[37] & ex2_sh_lv2z_b[37])); + assign ex2_sh_lvl2[38] = (~(ex2_sh_lv2x_b[38] & ex2_sh_lv2y_b[38] & ex2_sh_lv2z_b[38])); + assign ex2_sh_lvl2[39] = (~(ex2_sh_lv2x_b[39] & ex2_sh_lv2y_b[39] & ex2_sh_lv2z_b[39])); + assign ex2_sh_lvl2[40] = (~(ex2_sh_lv2x_b[40] & ex2_sh_lv2y_b[40] & ex2_sh_lv2z_b[40])); + assign ex2_sh_lvl2[41] = (~(ex2_sh_lv2x_b[41] & ex2_sh_lv2y_b[41] & ex2_sh_lv2z_b[41])); + assign ex2_sh_lvl2[42] = (~(ex2_sh_lv2x_b[42] & ex2_sh_lv2y_b[42] & ex2_sh_lv2z_b[42])); + assign ex2_sh_lvl2[43] = (~(ex2_sh_lv2x_b[43] & ex2_sh_lv2y_b[43] & ex2_sh_lv2z_b[43])); + assign ex2_sh_lvl2[44] = (~(ex2_sh_lv2x_b[44] & ex2_sh_lv2y_b[44] & ex2_sh_lv2z_b[44])); + assign ex2_sh_lvl2[45] = (~(ex2_sh_lv2x_b[45] & ex2_sh_lv2y_b[45] & ex2_sh_lv2z_b[45])); + assign ex2_sh_lvl2[46] = (~(ex2_sh_lv2x_b[46] & ex2_sh_lv2y_b[46] & ex2_sh_lv2z_b[46])); + assign ex2_sh_lvl2[47] = (~(ex2_sh_lv2x_b[47] & ex2_sh_lv2y_b[47] & ex2_sh_lv2z_b[47])); + assign ex2_sh_lvl2[48] = (~(ex2_sh_lv2x_b[48] & ex2_sh_lv2y_b[48] & ex2_sh_lv2z_b[48])); + assign ex2_sh_lvl2[49] = (~(ex2_sh_lv2x_b[49] & ex2_sh_lv2y_b[49] & ex2_sh_lv2z_b[49])); + assign ex2_sh_lvl2[50] = (~(ex2_sh_lv2x_b[50] & ex2_sh_lv2y_b[50] & ex2_sh_lv2z_b[50])); + assign ex2_sh_lvl2[51] = (~(ex2_sh_lv2x_b[51] & ex2_sh_lv2y_b[51] & ex2_sh_lv2z_b[51])); + assign ex2_sh_lvl2[52] = (~(ex2_sh_lv2x_b[52] & ex2_sh_lv2y_b[52] & ex2_sh_lv2z_b[52])); + assign ex2_sh_lvl2[53] = (~(ex2_sh_lv2x_b[53] & ex2_sh_lv2y_b[53] & ex2_sh_lv2z_b[53])); + assign ex2_sh_lvl2[54] = (~(ex2_sh_lv2x_b[54] & ex2_sh_lv2y_b[54] & ex2_sh_lv2z_b[54])); + assign ex2_sh_lvl2[55] = (~(ex2_sh_lv2x_b[55] & ex2_sh_lv2y_b[55] & ex2_sh_lv2z_b[55])); + assign ex2_sh_lvl2[56] = (~(ex2_sh_lv2x_b[56] & ex2_sh_lv2y_b[56] & ex2_sh_lv2z_b[56])); + assign ex2_sh_lvl2[57] = (~(ex2_sh_lv2x_b[57] & ex2_sh_lv2y_b[57] & ex2_sh_lv2z_b[57])); + assign ex2_sh_lvl2[58] = (~(ex2_sh_lv2x_b[58] & ex2_sh_lv2y_b[58] & ex2_sh_lv2z_b[58])); + assign ex2_sh_lvl2[59] = (~(ex2_sh_lv2x_b[59] & ex2_sh_lv2y_b[59] & ex2_sh_lv2z_b[59])); + assign ex2_sh_lvl2[60] = (~(ex2_sh_lv2y_b[60] & ex2_sh_lv2z_b[60])); + assign ex2_sh_lvl2[61] = (~(ex2_sh_lv2y_b[61] & ex2_sh_lv2z_b[61])); + assign ex2_sh_lvl2[62] = (~(ex2_sh_lv2y_b[62] & ex2_sh_lv2z_b[62])); + assign ex2_sh_lvl2[63] = (~(ex2_sh_lv2y_b[63] & ex2_sh_lv2z_b[63])); + assign ex2_sh_lvl2[64] = (~(ex2_sh_lv2y_b[64])); + assign ex2_sh_lvl2[65] = (~(ex2_sh_lv2y_b[65])); + assign ex2_sh_lvl2[66] = (~(ex2_sh_lv2y_b[66])); + assign ex2_sh_lvl2[67] = (~(ex2_sh_lv2y_b[67])); + +endmodule diff --git a/dev/verilog/work/fu_byp.v b/dev/verilog/work/fu_byp.v new file mode 100755 index 0000000..c412c9f --- /dev/null +++ b/dev/verilog/work/fu_byp.v @@ -0,0 +1,2381 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + + `include "tri_a2o.vh" + + +module fu_byp( + vdd, + gnd, + clkoff_b, + act_dis, + flush, + delay_lclkr, + mpw1_b, + mpw2_b, + sg_1, + thold_1, + fpu_enable, + nclk, + f_byp_si, + f_byp_so, + ex1_act, + f_dcd_ex1_bypsel_a_res0, + f_dcd_ex1_bypsel_a_res1, + f_dcd_ex1_bypsel_a_res2, + f_dcd_ex1_bypsel_a_load0, + f_dcd_ex1_bypsel_a_load1, + f_dcd_ex1_bypsel_a_load2, + f_dcd_ex1_bypsel_a_reload0, + f_dcd_ex1_bypsel_a_reload1, + f_dcd_ex1_bypsel_a_reload2, + + f_dcd_ex1_bypsel_b_res0, + f_dcd_ex1_bypsel_b_res1, + f_dcd_ex1_bypsel_b_res2, + f_dcd_ex1_bypsel_b_load0, + f_dcd_ex1_bypsel_b_load1, + f_dcd_ex1_bypsel_b_load2, + f_dcd_ex1_bypsel_b_reload0, + f_dcd_ex1_bypsel_b_reload1, + f_dcd_ex1_bypsel_b_reload2, + + f_dcd_ex1_bypsel_c_res0, + f_dcd_ex1_bypsel_c_res1, + f_dcd_ex1_bypsel_c_res2, + f_dcd_ex1_bypsel_c_load0, + f_dcd_ex1_bypsel_c_load1, + f_dcd_ex1_bypsel_c_load2, + f_dcd_ex1_bypsel_c_reload0, + f_dcd_ex1_bypsel_c_reload1, + f_dcd_ex1_bypsel_c_reload2, + + f_dcd_ex1_bypsel_s_res0, + f_dcd_ex1_bypsel_s_res1, + f_dcd_ex1_bypsel_s_res2, + f_dcd_ex1_bypsel_s_load0, + f_dcd_ex1_bypsel_s_load1, + f_dcd_ex1_bypsel_s_load2, + f_dcd_ex1_bypsel_s_reload0, + f_dcd_ex1_bypsel_s_reload1, + f_dcd_ex1_bypsel_s_reload2, + + f_rnd_ex7_res_sign, + f_rnd_ex7_res_expo, + f_rnd_ex7_res_frac, + f_dcd_ex1_uc_fc_hulp, + f_dcd_ex1_div_beg, + f_dcd_ex1_uc_fa_pos, + f_dcd_ex1_uc_fc_pos, + f_dcd_ex1_uc_fb_pos, + f_dcd_ex1_uc_fc_0_5, + f_dcd_ex1_uc_fc_1_0, + f_dcd_ex1_uc_fc_1_minus, + f_dcd_ex1_uc_fb_1_0, + f_dcd_ex1_uc_fb_0_75, + f_dcd_ex1_uc_fb_0_5, + f_fpr_ex8_frt_sign, + f_fpr_ex8_frt_expo, + f_fpr_ex8_frt_frac, + f_fpr_ex9_frt_sign, + f_fpr_ex9_frt_expo, + f_fpr_ex9_frt_frac, + + f_fpr_ex6_load_sign, + f_fpr_ex6_load_expo, + f_fpr_ex6_load_frac, + f_fpr_ex7_load_sign, + f_fpr_ex7_load_expo, + f_fpr_ex7_load_frac, + f_fpr_ex8_load_sign, + f_fpr_ex8_load_expo, + f_fpr_ex8_load_frac, + + f_fpr_ex6_reload_sign, + f_fpr_ex6_reload_expo, + f_fpr_ex6_reload_frac, + f_fpr_ex7_reload_sign, + f_fpr_ex7_reload_expo, + f_fpr_ex7_reload_frac, + f_fpr_ex8_reload_sign, + f_fpr_ex8_reload_expo, + f_fpr_ex8_reload_frac, + + f_fpr_ex1_a_sign, + f_fpr_ex1_a_expo, + f_fpr_ex1_a_frac, + f_fpr_ex1_c_sign, + f_fpr_ex1_c_expo, + f_fpr_ex1_c_frac, + f_fpr_ex1_b_sign, + f_fpr_ex1_b_expo, + f_fpr_ex1_b_frac, + f_fpr_ex1_s_sign, + f_fpr_ex1_s_expo, + f_fpr_ex1_s_frac, + f_dcd_ex1_aop_valid, + f_dcd_ex1_cop_valid, + f_dcd_ex1_bop_valid, + f_dcd_ex1_sp, + f_dcd_ex1_to_integer_b, + f_dcd_ex1_emin_dp, + f_dcd_ex1_emin_sp, + f_byp_ex1_s_sign, + f_byp_ex1_s_expo, + f_byp_ex1_s_frac, + f_byp_fmt_ex2_a_expo, + f_byp_fmt_ex2_c_expo, + f_byp_fmt_ex2_b_expo, + f_byp_eie_ex2_a_expo, + f_byp_eie_ex2_c_expo, + f_byp_eie_ex2_b_expo, + f_byp_alg_ex2_a_expo, + f_byp_alg_ex2_c_expo, + f_byp_alg_ex2_b_expo, + f_byp_fmt_ex2_a_sign, + f_byp_fmt_ex2_c_sign, + f_byp_fmt_ex2_b_sign, + f_byp_pic_ex2_a_sign, + f_byp_pic_ex2_c_sign, + f_byp_pic_ex2_b_sign, + f_byp_alg_ex2_b_sign, + f_byp_fmt_ex2_a_frac, + f_byp_fmt_ex2_c_frac, + f_byp_fmt_ex2_b_frac, + f_byp_alg_ex2_b_frac, + f_byp_mul_ex2_a_frac, + f_byp_mul_ex2_a_frac_17, + f_byp_mul_ex2_a_frac_35, + f_byp_mul_ex2_c_frac +); + inout vdd; + inout gnd; + input clkoff_b; // tiup + input act_dis; // ??tidn?? + input flush; // ??tidn?? + input delay_lclkr; // tidn, + input mpw1_b; // tidn, + input mpw2_b; // tidn, + input sg_1; + input thold_1; + input fpu_enable; //dc_act + input [0:`NCLK_WIDTH-1] nclk; + + input f_byp_si; //perv + output f_byp_so; //perv + input ex1_act; //act + + input f_dcd_ex1_bypsel_a_res0; + input f_dcd_ex1_bypsel_a_res1; + input f_dcd_ex1_bypsel_a_res2; + input f_dcd_ex1_bypsel_a_load0; + input f_dcd_ex1_bypsel_a_load1; + input f_dcd_ex1_bypsel_a_load2; + input f_dcd_ex1_bypsel_a_reload0; + input f_dcd_ex1_bypsel_a_reload1; + input f_dcd_ex1_bypsel_a_reload2; + + input f_dcd_ex1_bypsel_b_res0; + input f_dcd_ex1_bypsel_b_res1; + input f_dcd_ex1_bypsel_b_res2; + input f_dcd_ex1_bypsel_b_load0; + input f_dcd_ex1_bypsel_b_load1; + input f_dcd_ex1_bypsel_b_load2; + input f_dcd_ex1_bypsel_b_reload0; + input f_dcd_ex1_bypsel_b_reload1; + input f_dcd_ex1_bypsel_b_reload2; + + input f_dcd_ex1_bypsel_c_res0; + input f_dcd_ex1_bypsel_c_res1; + input f_dcd_ex1_bypsel_c_res2; + input f_dcd_ex1_bypsel_c_load0; + input f_dcd_ex1_bypsel_c_load1; + input f_dcd_ex1_bypsel_c_load2; + input f_dcd_ex1_bypsel_c_reload0; + input f_dcd_ex1_bypsel_c_reload1; + input f_dcd_ex1_bypsel_c_reload2; + + input f_dcd_ex1_bypsel_s_res0; + input f_dcd_ex1_bypsel_s_res1; + input f_dcd_ex1_bypsel_s_res2; + input f_dcd_ex1_bypsel_s_load0; + input f_dcd_ex1_bypsel_s_load1; + input f_dcd_ex1_bypsel_s_load2; + input f_dcd_ex1_bypsel_s_reload0; + input f_dcd_ex1_bypsel_s_reload1; + input f_dcd_ex1_bypsel_s_reload2; + + input f_rnd_ex7_res_sign; + input [1:13] f_rnd_ex7_res_expo; + input [0:52] f_rnd_ex7_res_frac; + input f_dcd_ex1_uc_fc_hulp; + + input f_dcd_ex1_div_beg; + input f_dcd_ex1_uc_fa_pos; + input f_dcd_ex1_uc_fc_pos; + input f_dcd_ex1_uc_fb_pos; + input f_dcd_ex1_uc_fc_0_5; + input f_dcd_ex1_uc_fc_1_0; + input f_dcd_ex1_uc_fc_1_minus; + input f_dcd_ex1_uc_fb_1_0; + input f_dcd_ex1_uc_fb_0_75; + input f_dcd_ex1_uc_fb_0_5; + + input f_fpr_ex8_frt_sign; + input [1:13] f_fpr_ex8_frt_expo; + input [0:52] f_fpr_ex8_frt_frac; + input f_fpr_ex9_frt_sign; + input [1:13] f_fpr_ex9_frt_expo; + input [0:52] f_fpr_ex9_frt_frac; + + input f_fpr_ex6_load_sign; + input [3:13] f_fpr_ex6_load_expo; + input [0:52] f_fpr_ex6_load_frac; + input f_fpr_ex7_load_sign; + input [3:13] f_fpr_ex7_load_expo; + input [0:52] f_fpr_ex7_load_frac; + input f_fpr_ex8_load_sign; + input [3:13] f_fpr_ex8_load_expo; + input [0:52] f_fpr_ex8_load_frac; + + input f_fpr_ex6_reload_sign; + input [3:13] f_fpr_ex6_reload_expo; + input [0:52] f_fpr_ex6_reload_frac; + input f_fpr_ex7_reload_sign; + input [3:13] f_fpr_ex7_reload_expo; + input [0:52] f_fpr_ex7_reload_frac; + input f_fpr_ex8_reload_sign; + input [3:13] f_fpr_ex8_reload_expo; + input [0:52] f_fpr_ex8_reload_frac; + + + input f_fpr_ex1_a_sign; + input [1:13] f_fpr_ex1_a_expo; + input [0:52] f_fpr_ex1_a_frac; //[0] is implicit bit + + input f_fpr_ex1_c_sign; + input [1:13] f_fpr_ex1_c_expo; + input [0:52] f_fpr_ex1_c_frac; //[0] is implicit bit + + input f_fpr_ex1_b_sign; + input [1:13] f_fpr_ex1_b_expo; + input [0:52] f_fpr_ex1_b_frac; //[0] is implicit bit + + input f_fpr_ex1_s_sign; + input [3:13] f_fpr_ex1_s_expo; + input [0:52] f_fpr_ex1_s_frac; //[0] is implicit bit + + input f_dcd_ex1_aop_valid; + input f_dcd_ex1_cop_valid; + input f_dcd_ex1_bop_valid; + input f_dcd_ex1_sp; + input f_dcd_ex1_to_integer_b; + input f_dcd_ex1_emin_dp; + input f_dcd_ex1_emin_sp; + + output f_byp_ex1_s_sign; + output [3:13] f_byp_ex1_s_expo; + output [0:52] f_byp_ex1_s_frac; + + output [1:13] f_byp_fmt_ex2_a_expo; + output [1:13] f_byp_fmt_ex2_c_expo; + output [1:13] f_byp_fmt_ex2_b_expo; + output [1:13] f_byp_eie_ex2_a_expo; + output [1:13] f_byp_eie_ex2_c_expo; + output [1:13] f_byp_eie_ex2_b_expo; + output [1:13] f_byp_alg_ex2_a_expo; + output [1:13] f_byp_alg_ex2_c_expo; + output [1:13] f_byp_alg_ex2_b_expo; + + output f_byp_fmt_ex2_a_sign; + output f_byp_fmt_ex2_c_sign; + output f_byp_fmt_ex2_b_sign; + output f_byp_pic_ex2_a_sign; + output f_byp_pic_ex2_c_sign; + output f_byp_pic_ex2_b_sign; + output f_byp_alg_ex2_b_sign; + + output [0:52] f_byp_fmt_ex2_a_frac; + output [0:52] f_byp_fmt_ex2_c_frac; + output [0:52] f_byp_fmt_ex2_b_frac; + output [0:52] f_byp_alg_ex2_b_frac; + output [0:52] f_byp_mul_ex2_a_frac; //mul + output f_byp_mul_ex2_a_frac_17; //mul + output f_byp_mul_ex2_a_frac_35; //mul + output [0:53] f_byp_mul_ex2_c_frac; //mul + + // ENTITY + + + parameter tiup = 1'b1; + parameter tidn = 1'b0; + parameter [1:13] k_emin_dp = 13'b0000000000001; + parameter [1:13] k_emin_sp = 13'b0001110000001; + parameter [1:13] k_toint = 13'b0010001101001; + parameter [1:13] expo_zero = 13'b0000000000001; + parameter [1:13] expo_bias = 13'b0001111111111; + parameter [1:13] expo_bias_m1 = 13'b0001111111110; + //-------------------------------- + // 57-bias is done after Ea+Ec-Eb + //-------------------------------- + // bias + 162 - 56 + // bias + 106 1023+106 = 1129 + // + // 0_0011_1111_1111 + // 110 1010 106 = + //----------------------------- + // 0 0100 0110 1001 + //----------------------------- + + wire [1:13] ex1_c_k_expo; + wire [1:13] ex1_b_k_expo; + wire [1:13] ex1_a_k_expo; + wire [0:52] ex1_a_k_frac; + wire [0:52] ex1_c_k_frac; + wire [0:52] ex1_b_k_frac; + + wire [1:13] ex1_a_expo_prebyp; + wire [1:13] ex1_c_expo_prebyp; + wire [1:13] ex1_b_expo_prebyp; + wire [1:13] ex1_s_expo_prebyp; + wire [0:52] ex1_a_frac_prebyp; + wire [0:52] ex1_c_frac_prebyp; + wire [0:52] ex1_b_frac_prebyp; + wire [0:52] ex1_s_frac_prebyp; + wire ex1_a_sign_prebyp; + wire ex1_c_sign_prebyp; + wire ex1_b_sign_prebyp; + wire ex1_s_sign_prebyp; + + wire ex1_a_sign_pre1_b; + wire ex1_a_sign_pre2_b; + wire ex1_a_sign_pre; + wire ex1_c_sign_pre1_b; + wire ex1_c_sign_pre2_b; + wire ex1_c_sign_pre; + wire ex1_b_sign_pre1_b; + wire ex1_b_sign_pre2_b; + wire ex1_b_sign_pre; + wire ex1_s_sign_pre1_b; + wire ex1_s_sign_pre2_b; + wire ex1_s_sign_pre; + + wire aop_valid_sign; + wire cop_valid_sign; + wire bop_valid_sign; + wire aop_valid_plus; + wire cop_valid_plus; + wire bop_valid_plus; + + wire [0:3] spare_unused; + wire unused; + wire thold_0; + wire force_t; + wire thold_0_b; + wire sg_0; + + wire [0:52] ex2_b_frac_si; + wire [0:52] ex2_b_frac_so; + wire [0:52] ex2_frac_a_fmt_si; + wire [0:52] ex2_frac_a_fmt_so; + wire [0:52] ex2_frac_c_fmt_si; + wire [0:52] ex2_frac_c_fmt_so; + wire [0:52] ex2_frac_b_fmt_si; + wire [0:52] ex2_frac_b_fmt_so; + wire [0:53] frac_mul_c_si; + wire [0:53] frac_mul_c_so; + wire [0:54] frac_mul_a_si; + wire [0:54] frac_mul_a_so; + + wire [0:13] ex2_expo_a_eie_si; + wire [0:13] ex2_expo_a_eie_so; + wire [0:13] ex2_expo_b_eie_si; + wire [0:13] ex2_expo_b_eie_so; + wire [0:13] ex2_expo_c_eie_si; + wire [0:13] ex2_expo_c_eie_so; + wire [0:13] ex2_expo_a_fmt_si; + wire [0:13] ex2_expo_a_fmt_so; + wire [0:13] ex2_expo_b_fmt_si; + wire [0:13] ex2_expo_b_fmt_so; + wire [0:13] ex2_expo_c_fmt_si; + wire [0:13] ex2_expo_c_fmt_so; + wire [0:13] ex2_expo_b_alg_si; + wire [0:13] ex2_expo_b_alg_so; + wire [0:12] ex2_expo_a_alg_si; + wire [0:12] ex2_expo_a_alg_so; + wire [0:12] ex2_expo_c_alg_si; + wire [0:12] ex2_expo_c_alg_so; + + wire [0:3] act_si; + wire [0:3] act_so; + + + wire sel_a_no_byp_s; + wire sel_c_no_byp_s; + wire sel_b_no_byp_s; + wire sel_s_no_byp_s; + wire sel_a_res0_s; + wire sel_a_res1_s; + wire sel_a_load0_s; + wire sel_a_reload0_s; + wire sel_a_load1_s; + wire sel_c_res0_s; + wire sel_c_res1_s; + wire sel_c_load0_s; + wire sel_c_reload0_s; + wire sel_c_load1_s; + wire sel_b_res0_s; + wire sel_b_res1_s; + wire sel_b_load0_s; + wire sel_b_reload0_s; + wire sel_b_load1_s; + wire sel_s_res0_s; + wire sel_s_res1_s; + wire sel_s_load0_s; + wire sel_s_reload0_s; + wire sel_s_load1_s; + + wire sel_a_no_byp; + wire sel_c_no_byp; + wire sel_b_no_byp; + wire sel_s_no_byp; + + wire sel_a_imm; + wire sel_a_res0; + wire sel_a_res1; + wire sel_a_load0; + wire sel_a_reload0; + wire sel_b_reload0; + wire sel_c_reload0; + wire sel_s_reload0; + + wire sel_a_load1; + wire sel_c_imm; + wire sel_c_res0; + wire sel_c_res1; + wire sel_c_load0; + wire sel_c_load1; + wire sel_b_imm; + wire sel_b_res0; + wire sel_b_res1; + wire sel_b_load0; + wire sel_b_load1; + wire sel_s_imm; + wire sel_s_res0; + wire sel_s_res1; + wire sel_s_load0; + wire sel_s_load1; + + wire [1:13] ex6_load_expo; + wire [1:13] ex6_reload_expo; + + wire [0:52] ex1_b_frac_alg_b; + wire [0:52] ex2_b_frac_alg_b; + wire [0:52] ex1_a_frac_fmt_b; + wire [0:52] ex2_a_frac_fmt_b; + wire [0:52] ex1_c_frac_fmt_b; + wire [0:52] ex2_c_frac_fmt_b; + wire [0:52] ex1_b_frac_fmt_b; + wire [0:52] ex2_b_frac_fmt_b; + wire ex2_a_frac_mul_17_b; + wire ex2_a_frac_mul_35_b; + wire [0:52] ex2_a_frac_mul_b; + wire [0:53] ex2_c_frac_mul_b; + wire ex1_a_frac_mul_17_b; + wire ex1_a_frac_mul_35_b; + wire [0:52] ex1_a_frac_mul_b; + wire [0:53] ex1_c_frac_mul_b; + wire ex1_b_sign_alg_b; + wire ex2_b_sign_alg_b; + wire [1:13] ex1_b_expo_alg_b; + wire [1:13] ex2_b_expo_alg_b; + wire [1:13] ex1_c_expo_alg_b; + wire [1:13] ex2_c_expo_alg_b; + wire [1:13] ex1_a_expo_alg_b; + wire [1:13] ex2_a_expo_alg_b; + wire ex1_a_sign_fmt_b; + wire ex2_a_sign_fmt_b; + wire [1:13] ex1_a_expo_fmt_b; + wire [1:13] ex2_a_expo_fmt_b; + wire ex1_c_sign_fmt_b; + wire ex2_c_sign_fmt_b; + wire [1:13] ex1_c_expo_fmt_b; + wire [1:13] ex2_c_expo_fmt_b; + wire ex1_b_sign_fmt_b; + wire ex2_b_sign_fmt_b; + wire [1:13] ex1_b_expo_fmt_b; + wire [1:13] ex2_b_expo_fmt_b; + wire ex1_a_sign_pic_b; + wire ex2_a_sign_pic_b; + wire [1:13] ex1_a_expo_eie_b; + wire [1:13] ex2_a_expo_eie_b; + wire ex1_c_sign_pic_b; + wire ex2_c_sign_pic_b; + wire [1:13] ex1_c_expo_eie_b; + wire [1:13] ex2_c_expo_eie_b; + wire ex1_b_sign_pic_b; + wire ex2_b_sign_pic_b; + wire [1:13] ex1_b_expo_eie_b; + wire [1:13] ex2_b_expo_eie_b; + wire cop_uc_imm; + wire bop_uc_imm; + + wire ex1_a_sign_fpr; + wire ex1_c_sign_fpr; + wire ex1_b_sign_fpr; + wire ex1_s_sign_fpr; + wire [1:13] ex1_a_expo_fpr; + wire [1:13] ex1_c_expo_fpr; + wire [1:13] ex1_b_expo_fpr; + wire [1:13] ex1_s_expo_fpr; + wire [0:52] ex1_a_frac_fpr; + wire [0:52] ex1_c_frac_fpr; + wire [0:52] ex1_b_frac_fpr; + wire [0:52] ex1_s_frac_fpr; + + wire ex7_sign_res_ear; + wire ex7_sign_a_res_dly; + wire ex7_sign_c_res_dly; + wire ex7_sign_b_res_dly; + wire ex7_sign_s_res_dly; + wire ex6_sign_lod_ear; + wire ex6_sign_relod_ear; + + wire ex7_sign_a_lod_dly; + wire ex7_sign_c_lod_dly; + wire ex7_sign_b_lod_dly; + wire ex7_sign_s_lod_dly; + + wire [1:13] ex7_expo_res_ear; + wire [1:13] ex7_expo_a_res_dly; + wire [1:13] ex7_expo_c_res_dly; + wire [1:13] ex7_expo_b_res_dly; + wire [1:13] ex7_expo_s_res_dly; + wire [1:13] ex6_expo_lod_ear; + wire [1:13] ex6_expo_relod_ear; + wire [1:13] ex7_expo_a_lod_dly; + wire [1:13] ex7_expo_c_lod_dly; + wire [1:13] ex7_expo_b_lod_dly; + wire [1:13] ex7_expo_s_lod_dly; + wire [0:52] ex7_frac_res_ear; + wire [0:52] ex7_frac_a_res_dly; + wire [0:52] ex7_frac_c_res_dly; + wire [0:52] ex7_frac_b_res_dly; + wire [0:52] ex7_frac_s_res_dly; + wire [0:52] ex6_frac_lod_ear; + wire [0:52] ex6_frac_relod_ear; + wire [0:52] ex7_frac_a_lod_dly; + wire [0:52] ex7_frac_c_lod_dly; + wire [0:52] ex7_frac_b_lod_dly; + wire [0:52] ex7_frac_s_lod_dly; + wire [1:13] ex1_a_expo_pre1_b; + wire [1:13] ex1_c_expo_pre1_b; + wire [1:13] ex1_b_expo_pre1_b; + wire [1:13] ex1_s_expo_pre1_b; + wire [1:13] ex1_a_expo_pre2_b; + wire [1:13] ex1_c_expo_pre2_b; + wire [1:13] ex1_b_expo_pre2_b; + wire [1:13] ex1_s_expo_pre2_b; + wire [1:13] ex1_a_expo_pre3_b; + wire [1:13] ex1_c_expo_pre3_b; + wire [1:13] ex1_b_expo_pre3_b; + wire [1:13] ex1_s_expo_pre3_b; + wire [1:13] ex1_a_expo_pre; + wire [1:13] ex1_c_expo_pre; + wire [1:13] ex1_s_expo_pre; + wire [1:13] ex1_b_expo_pre; + wire [0:52] ex1_a_frac_pre; + wire [0:52] ex1_c_frac_pre; + wire [0:52] ex1_b_frac_pre; + wire [0:52] ex1_s_frac_pre; + wire [0:52] ex1_a_frac_pre1_b; + wire [0:52] ex1_a_frac_pre2_b; + wire [0:52] ex1_c_frac_pre1_b; + wire [0:52] ex1_c_frac_pre2_b; + wire [0:52] ex1_c_frac_pre3_b; + wire [0:52] ex1_b_frac_pre1_b; + wire [0:52] ex1_b_frac_pre2_b; + wire [0:1] ex1_b_frac_pre3_b; + wire [0:52] ex1_s_frac_pre1_b; + wire [0:52] ex1_s_frac_pre2_b; + + wire byp_ex2_d1clk; + wire byp_ex2_d2clk; + wire [0:`NCLK_WIDTH-1] byp_ex2_lclk; + wire ex1_c_frac_pre3_hulp_b; + wire ex1_hulp_sp; + wire ex1_c_frac_pre_hulp; + wire ex1_c_frac_prebyp_hulp; + + wire [0:53] temp_ex1_c_frac_mul; + wire [0:52] temp_ex1_a_frac_mul; + wire temp_ex1_a_frac_mul_17; + wire temp_ex1_a_frac_mul_35; + + + // REPOWER_MODE=/SERIAL/ + + //AOI22_e5n_sn08b SP/UNDEF + //AOI22_e5n_sn08b SP/UNDEF + //AOI22_e5n_sn08b SP/UNDEF + //AOI22_e5n_sn08b SP/UNDEF + + // unique aoi to latch input + + + wire [0:52] ex2_b_frac_alg; + wire [0:52] ex2_b_frac_fmt; + wire [0:52] ex2_a_frac_fmt; + wire [0:52] ex2_c_frac_fmt; + wire ex2_b_sign_alg; + wire ex2_b_sign_fmt; + wire ex2_a_sign_fmt; + wire ex2_c_sign_fmt; + wire ex2_b_sign_pic; + wire ex2_a_sign_pic; + wire ex2_c_sign_pic; + wire [1:13] ex2_b_expo_alg; + wire [1:13] ex2_a_expo_alg; + wire [1:13] ex2_c_expo_alg; + wire [1:13] ex2_b_expo_fmt; + wire [1:13] ex2_a_expo_fmt; + wire [1:13] ex2_c_expo_fmt; + wire [1:13] ex2_b_expo_eie; + wire [1:13] ex2_a_expo_eie; + wire [1:13] ex2_c_expo_eie; + + assign unused = ex1_a_expo_pre3_b[1] | ex1_a_expo_pre3_b[2] | ex1_c_expo_pre3_b[1] | ex1_c_expo_pre3_b[2] | ex1_c_expo_pre3_b[3] | ex1_b_expo_pre3_b[1] | + ex1_b_expo_pre3_b[2] | ex1_b_expo_pre3_b[3] | ex1_a_k_expo[1] | ex1_a_k_expo[2] | |(ex1_c_k_expo[1:12]) | |(ex1_b_k_expo[1:3]) | + |(ex1_a_k_frac[0:52]) | |(ex1_b_k_frac[2:52]); + + //#=############################################################## + //# pervasive + //#=############################################################## + + + tri_plat thold_reg_0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(flush), + .din(thold_1), + .q(thold_0) + ); + + + tri_plat sg_reg_0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(flush), + .din(sg_1), + .q(sg_0) + ); + + + tri_lcbor lcbor_0( + .clkoff_b(clkoff_b), + .thold(thold_0), + .sg(sg_0), + .act_dis(act_dis), + .force_t(force_t), + .thold_b(thold_0_b) + ); + + //#=############################################################## + //# act + //#=############################################################## + + + tri_rlmreg_p #(.WIDTH(4), .NEEDS_SRESET(0)) act_lat( + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(fpu_enable), + .thold_b(thold_0_b), + .sg(sg_0), + .scout(act_so), + .scin(act_si), + //----------------- + .din({spare_unused[0], + spare_unused[1], + spare_unused[2], + spare_unused[3]}), + //----------------- + .dout({spare_unused[0], + spare_unused[1], + spare_unused[2], + spare_unused[3]}) + ); + + + tri_lcbnd byp_ex2_lcb( + .delay_lclkr(delay_lclkr), // tidn ,--in + .mpw1_b(mpw1_b), // tidn ,--in + .mpw2_b(mpw2_b), // tidn ,--in + .force_t(force_t), // tidn ,--in + .nclk(nclk), //in + .vd(vdd), //inout + .gd(gnd), //inout + .act(ex1_act), //in + .sg(sg_0), //in + .thold_b(thold_0_b), //in + .d1clk(byp_ex2_d1clk), //out + .d2clk(byp_ex2_d2clk), //out + .lclk(byp_ex2_lclk) //out + ); + + //================================================= + // Constants for the immediate data + //================================================= + + // k_emin_dp "0000000000001"; + // k_emin_sp(1 to 13) "0001110000001"; + // k_toint (1 to 13) "0010001101001"; + + assign ex1_a_k_expo[1:2] = {tidn, tidn}; + assign ex1_a_k_expo[3:13] = ({11{(~f_dcd_ex1_to_integer_b)}} & k_toint[3:13]) | + ({11{f_dcd_ex1_emin_dp}} & k_emin_dp[3:13]) | + ({11{f_dcd_ex1_emin_sp}} & k_emin_sp[3:13]); + + // expo_bias "0001111111111"; + // expo_bias_m1 "0001111111110"; + + assign ex1_c_k_expo[1:3] = {tidn, tidn, tidn}; + assign ex1_c_k_expo[4:12] = {9{tiup}}; + // non divide + // div/sqrt + assign ex1_c_k_expo[13] = ((~cop_uc_imm) & expo_bias[13]) | + (f_dcd_ex1_uc_fc_1_0 & expo_bias[13]) | + (f_dcd_ex1_uc_fc_0_5 & expo_bias_m1[13]) | + (f_dcd_ex1_uc_fc_1_minus & expo_bias_m1[13]); // div/sqrt + // div/sqrt + + // expo_zero(1 to 13) "0000000000001"; + // expo_bias "0001111111111"; + // expo_bias_m1 "0001111111110"; + + assign ex1_b_k_expo[1:3] = {tidn, tidn, tidn}; + // non divide + // div/sqrt + assign ex1_b_k_expo[4:13] = ({10{(~bop_uc_imm)}} & expo_zero[4:13]) | + ({10{f_dcd_ex1_uc_fb_1_0}} & expo_bias[4:13]) | + ({10{f_dcd_ex1_uc_fb_0_5}} & expo_bias_m1[4:13]) | + ({10{f_dcd_ex1_uc_fb_0_75}} & expo_bias_m1[4:13]); // div/sqrt + // div/sqrt + + assign ex1_a_k_frac[0:52] = {53{tidn}}; + + // c is invalid for divide , a is valid ... but want multiplier output to be zero for divide first step (prenorm) + assign ex1_c_k_frac[0] = (~f_dcd_ex1_div_beg); // tiup ; + assign ex1_c_k_frac[1:52] = {52{f_dcd_ex1_uc_fc_1_minus}}; + + assign ex1_b_k_frac[0] = bop_uc_imm; + assign ex1_b_k_frac[1] = f_dcd_ex1_uc_fb_0_75; + assign ex1_b_k_frac[2:52] = {51{tidn}}; + + //===================================================================== + // selects for operand bypass muxes (also known as: data forwarding ) + //===================================================================== + + // forcing invalid causes selection of immediate data + + assign cop_uc_imm = f_dcd_ex1_uc_fc_0_5 | f_dcd_ex1_uc_fc_1_0 | f_dcd_ex1_uc_fc_1_minus; + assign bop_uc_imm = f_dcd_ex1_uc_fb_0_5 | f_dcd_ex1_uc_fb_1_0 | f_dcd_ex1_uc_fb_0_75; + + assign aop_valid_sign = (f_dcd_ex1_aop_valid & (~f_dcd_ex1_uc_fa_pos)); // or (not f_dcd_ex1_sgncpy_b) + assign cop_valid_sign = (f_dcd_ex1_cop_valid & (~f_dcd_ex1_uc_fc_pos) & (~cop_uc_imm)); + assign bop_valid_sign = (f_dcd_ex1_bop_valid & (~f_dcd_ex1_uc_fb_pos) & (~bop_uc_imm)); + + assign aop_valid_plus = (f_dcd_ex1_aop_valid); // or (not f_dcd_ex1_sgncpy_b) ; + assign cop_valid_plus = (f_dcd_ex1_cop_valid & (~cop_uc_imm)); + assign bop_valid_plus = (f_dcd_ex1_bop_valid & (~bop_uc_imm)); + + assign sel_a_no_byp_s = (~(f_dcd_ex1_bypsel_a_res0 | f_dcd_ex1_bypsel_a_res1 | f_dcd_ex1_bypsel_a_res2 | f_dcd_ex1_bypsel_a_reload0 | f_dcd_ex1_bypsel_a_reload1 | f_dcd_ex1_bypsel_a_reload2 | f_dcd_ex1_bypsel_a_load0 | f_dcd_ex1_bypsel_a_load1 | f_dcd_ex1_bypsel_a_load2 | (~aop_valid_sign))); + assign sel_c_no_byp_s = (~(f_dcd_ex1_bypsel_c_res0 | f_dcd_ex1_bypsel_c_res1 | f_dcd_ex1_bypsel_c_res2 | f_dcd_ex1_bypsel_c_reload0 | f_dcd_ex1_bypsel_c_reload1 | f_dcd_ex1_bypsel_c_reload2 | f_dcd_ex1_bypsel_c_load0 | f_dcd_ex1_bypsel_c_load1 | f_dcd_ex1_bypsel_c_load2 | (~cop_valid_sign))); + assign sel_b_no_byp_s = (~(f_dcd_ex1_bypsel_b_res0 | f_dcd_ex1_bypsel_b_res1 | f_dcd_ex1_bypsel_b_res2 | f_dcd_ex1_bypsel_b_reload0 | f_dcd_ex1_bypsel_b_reload1 | f_dcd_ex1_bypsel_b_reload2 | f_dcd_ex1_bypsel_b_load0 | f_dcd_ex1_bypsel_b_load1 | f_dcd_ex1_bypsel_b_load2 | (~bop_valid_sign))); + assign sel_s_no_byp_s = (~(f_dcd_ex1_bypsel_s_res0 | f_dcd_ex1_bypsel_s_res1 | f_dcd_ex1_bypsel_s_res2 | f_dcd_ex1_bypsel_s_reload0 | f_dcd_ex1_bypsel_s_reload1 | f_dcd_ex1_bypsel_s_reload2 | f_dcd_ex1_bypsel_s_load0 | f_dcd_ex1_bypsel_s_load1 | f_dcd_ex1_bypsel_s_load2 )); + + assign sel_a_no_byp = (~(f_dcd_ex1_bypsel_a_res0 | f_dcd_ex1_bypsel_a_res1 | f_dcd_ex1_bypsel_a_res2 | f_dcd_ex1_bypsel_a_reload0 | f_dcd_ex1_bypsel_a_reload1 | f_dcd_ex1_bypsel_a_reload2 | f_dcd_ex1_bypsel_a_load0 | f_dcd_ex1_bypsel_a_load1 | f_dcd_ex1_bypsel_a_load2 | (~aop_valid_plus))); + assign sel_c_no_byp = (~(f_dcd_ex1_bypsel_c_res0 | f_dcd_ex1_bypsel_c_res1 | f_dcd_ex1_bypsel_c_res2 | f_dcd_ex1_bypsel_c_reload0 | f_dcd_ex1_bypsel_c_reload1 | f_dcd_ex1_bypsel_c_reload2 | f_dcd_ex1_bypsel_c_load0 | f_dcd_ex1_bypsel_c_load1 | f_dcd_ex1_bypsel_c_load2 | (~cop_valid_plus))); + assign sel_b_no_byp = (~(f_dcd_ex1_bypsel_b_res0 | f_dcd_ex1_bypsel_b_res1 | f_dcd_ex1_bypsel_b_res2 | f_dcd_ex1_bypsel_b_reload0 | f_dcd_ex1_bypsel_b_reload1 | f_dcd_ex1_bypsel_b_reload2 | f_dcd_ex1_bypsel_b_load0 | f_dcd_ex1_bypsel_b_load1 | f_dcd_ex1_bypsel_b_load2 | (~bop_valid_plus))); + assign sel_s_no_byp = (~(f_dcd_ex1_bypsel_s_res0 | f_dcd_ex1_bypsel_s_res1 | f_dcd_ex1_bypsel_s_res2 | f_dcd_ex1_bypsel_s_reload0 | f_dcd_ex1_bypsel_s_reload1 | f_dcd_ex1_bypsel_s_reload2 | f_dcd_ex1_bypsel_s_load0 | f_dcd_ex1_bypsel_s_load1 | f_dcd_ex1_bypsel_s_load2)); + + assign sel_a_res0_s = aop_valid_sign & f_dcd_ex1_bypsel_a_res0; + assign sel_a_res1_s = aop_valid_sign & (f_dcd_ex1_bypsel_a_res1 | f_dcd_ex1_bypsel_a_res2); + assign sel_a_load0_s = aop_valid_sign & f_dcd_ex1_bypsel_a_load0; + assign sel_a_reload0_s = aop_valid_sign & f_dcd_ex1_bypsel_a_reload0; + + assign sel_a_load1_s = aop_valid_sign & (f_dcd_ex1_bypsel_a_load1 | f_dcd_ex1_bypsel_a_load2 | f_dcd_ex1_bypsel_a_reload1 | f_dcd_ex1_bypsel_a_reload2); + + assign sel_c_res0_s = cop_valid_sign & f_dcd_ex1_bypsel_c_res0; + assign sel_c_res1_s = cop_valid_sign & (f_dcd_ex1_bypsel_c_res1 | f_dcd_ex1_bypsel_c_res2); + assign sel_c_load0_s = cop_valid_sign & f_dcd_ex1_bypsel_c_load0; + assign sel_c_reload0_s = cop_valid_sign & f_dcd_ex1_bypsel_c_reload0; + assign sel_c_load1_s = cop_valid_sign & (f_dcd_ex1_bypsel_c_load1 | f_dcd_ex1_bypsel_c_load2 | f_dcd_ex1_bypsel_c_reload1 | f_dcd_ex1_bypsel_c_reload2); + + assign sel_b_res0_s = bop_valid_sign & f_dcd_ex1_bypsel_b_res0; + assign sel_b_res1_s = bop_valid_sign & (f_dcd_ex1_bypsel_b_res1 | f_dcd_ex1_bypsel_b_res2); + assign sel_b_load0_s = bop_valid_sign & f_dcd_ex1_bypsel_b_load0; + assign sel_b_reload0_s = bop_valid_sign & f_dcd_ex1_bypsel_b_reload0; + assign sel_b_load1_s = bop_valid_sign & (f_dcd_ex1_bypsel_b_load1 | f_dcd_ex1_bypsel_b_load2 | f_dcd_ex1_bypsel_b_reload1 | f_dcd_ex1_bypsel_b_reload2); + + assign sel_s_res0_s = f_dcd_ex1_bypsel_s_res0; + assign sel_s_res1_s = (f_dcd_ex1_bypsel_s_res1 | f_dcd_ex1_bypsel_s_res2); + assign sel_s_load0_s = f_dcd_ex1_bypsel_s_load0; + assign sel_s_reload0_s = f_dcd_ex1_bypsel_s_reload0; + assign sel_s_load1_s = (f_dcd_ex1_bypsel_s_load1 | f_dcd_ex1_bypsel_s_load2 | f_dcd_ex1_bypsel_s_reload1 | f_dcd_ex1_bypsel_s_reload2); + + assign sel_a_imm = (~aop_valid_plus); + assign sel_a_res0 = aop_valid_plus & f_dcd_ex1_bypsel_a_res0; + assign sel_a_res1 = aop_valid_plus & (f_dcd_ex1_bypsel_a_res1 | f_dcd_ex1_bypsel_a_res2); + assign sel_a_load0 = aop_valid_plus & f_dcd_ex1_bypsel_a_load0; + assign sel_a_reload0 = aop_valid_plus & f_dcd_ex1_bypsel_a_reload0; + + assign sel_a_load1 = aop_valid_plus & (f_dcd_ex1_bypsel_a_load1 | f_dcd_ex1_bypsel_a_load2 | f_dcd_ex1_bypsel_a_reload1 | f_dcd_ex1_bypsel_a_reload2); + // sel_a_fpr <= aop_valid_plus and sel_a_no_byp ; + + assign sel_c_imm = (~cop_valid_plus); + assign sel_c_res0 = cop_valid_plus & f_dcd_ex1_bypsel_c_res0; + assign sel_c_res1 = cop_valid_plus & (f_dcd_ex1_bypsel_c_res1 | f_dcd_ex1_bypsel_c_res2); + assign sel_c_load0 = cop_valid_plus & f_dcd_ex1_bypsel_c_load0; + assign sel_c_reload0 = cop_valid_plus & f_dcd_ex1_bypsel_c_reload0; + + assign sel_c_load1 = cop_valid_plus & (f_dcd_ex1_bypsel_c_load1 | f_dcd_ex1_bypsel_c_load2 | f_dcd_ex1_bypsel_c_reload1 | f_dcd_ex1_bypsel_c_reload2); + // sel_c_fpr <= cop_valid_plus and sel_c_no_byp ; + + assign sel_b_imm = (~bop_valid_plus); + assign sel_b_res0 = bop_valid_plus & f_dcd_ex1_bypsel_b_res0; + assign sel_b_res1 = bop_valid_plus & (f_dcd_ex1_bypsel_b_res1 | f_dcd_ex1_bypsel_b_res2); + assign sel_b_load0 = bop_valid_plus & f_dcd_ex1_bypsel_b_load0; + assign sel_b_reload0 = bop_valid_plus & f_dcd_ex1_bypsel_b_reload0; + + assign sel_b_load1 = bop_valid_plus & (f_dcd_ex1_bypsel_b_load1 | f_dcd_ex1_bypsel_b_load2 | f_dcd_ex1_bypsel_b_reload1 | f_dcd_ex1_bypsel_b_reload2); + // sel_b_fpr <= bop_valid_plus and sel_b_no_byp ; + + assign sel_s_imm = 1'b0; + assign sel_s_res0 = f_dcd_ex1_bypsel_s_res0; + assign sel_s_res1 = (f_dcd_ex1_bypsel_s_res1 | f_dcd_ex1_bypsel_s_res2); + assign sel_s_load0 = f_dcd_ex1_bypsel_s_load0; + assign sel_s_reload0 = f_dcd_ex1_bypsel_s_reload0; + assign sel_s_load1 = (f_dcd_ex1_bypsel_s_load1 | f_dcd_ex1_bypsel_s_load2 | f_dcd_ex1_bypsel_s_reload1 | f_dcd_ex1_bypsel_s_reload2); + // sel_s_fpr <= bop_valid_plus and sel_b_no_byp ; + + //------------------------ + // sign bit data forwarding + //------------------------ + + assign ex7_sign_res_ear = f_rnd_ex7_res_sign; // may need to manually rebuffer + assign ex7_sign_a_res_dly = (f_fpr_ex8_frt_sign & f_dcd_ex1_bypsel_a_res1) | (f_fpr_ex9_frt_sign & f_dcd_ex1_bypsel_a_res2); + assign ex7_sign_b_res_dly = (f_fpr_ex8_frt_sign & f_dcd_ex1_bypsel_b_res1) | (f_fpr_ex9_frt_sign & f_dcd_ex1_bypsel_b_res2); + assign ex7_sign_c_res_dly = (f_fpr_ex8_frt_sign & f_dcd_ex1_bypsel_c_res1) | (f_fpr_ex9_frt_sign & f_dcd_ex1_bypsel_c_res2); + assign ex7_sign_s_res_dly = (f_fpr_ex8_frt_sign & f_dcd_ex1_bypsel_s_res1) | (f_fpr_ex9_frt_sign & f_dcd_ex1_bypsel_s_res2); + assign ex6_sign_lod_ear = f_fpr_ex6_load_sign; + assign ex6_sign_relod_ear = f_fpr_ex6_reload_sign; + assign ex7_sign_a_lod_dly = (f_fpr_ex7_load_sign & f_dcd_ex1_bypsel_a_load1) | (f_fpr_ex8_load_sign & f_dcd_ex1_bypsel_a_load2 | f_fpr_ex7_reload_sign & f_dcd_ex1_bypsel_a_reload1) | (f_fpr_ex8_reload_sign & f_dcd_ex1_bypsel_a_reload2); + assign ex7_sign_b_lod_dly = (f_fpr_ex7_load_sign & f_dcd_ex1_bypsel_b_load1) | (f_fpr_ex8_load_sign & f_dcd_ex1_bypsel_b_load2 | f_fpr_ex7_reload_sign & f_dcd_ex1_bypsel_b_reload1) | (f_fpr_ex8_reload_sign & f_dcd_ex1_bypsel_b_reload2); + assign ex7_sign_c_lod_dly = (f_fpr_ex7_load_sign & f_dcd_ex1_bypsel_c_load1) | (f_fpr_ex8_load_sign & f_dcd_ex1_bypsel_c_load2 | f_fpr_ex7_reload_sign & f_dcd_ex1_bypsel_c_reload1) | (f_fpr_ex8_reload_sign & f_dcd_ex1_bypsel_c_reload2); + assign ex7_sign_s_lod_dly = (f_fpr_ex7_load_sign & f_dcd_ex1_bypsel_s_load1) | (f_fpr_ex8_load_sign & f_dcd_ex1_bypsel_s_load2 | f_fpr_ex7_reload_sign & f_dcd_ex1_bypsel_s_reload1) | (f_fpr_ex8_reload_sign & f_dcd_ex1_bypsel_s_reload2); + + assign ex1_a_sign_pre1_b = (~((sel_a_res0_s & ex7_sign_res_ear) | (sel_a_res1_s & ex7_sign_a_res_dly))); + assign ex1_a_sign_pre2_b = (~((sel_a_load0_s & ex6_sign_lod_ear) | (sel_a_reload0_s & ex6_sign_relod_ear) | (sel_a_load1_s & ex7_sign_a_lod_dly))); + assign ex1_a_sign_pre = (~(ex1_a_sign_pre1_b & ex1_a_sign_pre2_b)); + + assign ex1_c_sign_pre1_b = (~((sel_c_res0_s & ex7_sign_res_ear) | (sel_c_res1_s & ex7_sign_c_res_dly))); + assign ex1_c_sign_pre2_b = (~((sel_c_load0_s & ex6_sign_lod_ear) | (sel_c_reload0_s & ex6_sign_relod_ear) | (sel_c_load1_s & ex7_sign_c_lod_dly))); + assign ex1_c_sign_pre = (~(ex1_c_sign_pre1_b & ex1_c_sign_pre2_b)); + + assign ex1_b_sign_pre1_b = (~((sel_b_res0_s & ex7_sign_res_ear) | (sel_b_res1_s & ex7_sign_b_res_dly))); + assign ex1_b_sign_pre2_b = (~((sel_b_load0_s & ex6_sign_lod_ear) | (sel_b_reload0_s & ex6_sign_relod_ear) | (sel_b_load1_s & ex7_sign_b_lod_dly))); + assign ex1_b_sign_pre = (~(ex1_b_sign_pre1_b & ex1_b_sign_pre2_b)); + + assign ex1_s_sign_pre1_b = (~((sel_s_res0_s & ex7_sign_res_ear) | (sel_s_res1_s & ex7_sign_s_res_dly))); + assign ex1_s_sign_pre2_b = (~((sel_s_load0_s & ex6_sign_lod_ear) | (sel_s_reload0_s & ex6_sign_relod_ear) | (sel_s_load1_s & ex7_sign_s_lod_dly))); + assign ex1_s_sign_pre = (~(ex1_s_sign_pre1_b & ex1_s_sign_pre2_b)); + + assign ex1_a_sign_prebyp = ex1_a_sign_pre; // may need to manually rebuffer + assign ex1_c_sign_prebyp = ex1_c_sign_pre; // may need to manually rebuffer + assign ex1_b_sign_prebyp = ex1_b_sign_pre; // may need to manually rebuffer + assign ex1_s_sign_prebyp = ex1_s_sign_pre; // may need to manually rebuffer + + //------------------------ + // exponent data forwarding + //------------------------ + + assign ex6_load_expo[1:13] = {tidn, tidn, f_fpr_ex6_load_expo[3:13]}; + assign ex6_reload_expo[1:13] = {tidn, tidn, f_fpr_ex6_reload_expo[3:13]}; + + assign ex7_expo_res_ear[1:13] = f_rnd_ex7_res_expo[1:13]; + assign ex7_expo_a_res_dly[1:13] = (f_fpr_ex8_frt_expo[1:13] & {13{f_dcd_ex1_bypsel_a_res1}}) | (f_fpr_ex9_frt_expo[1:13] & {13{f_dcd_ex1_bypsel_a_res2}}); + assign ex7_expo_c_res_dly[1:13] = (f_fpr_ex8_frt_expo[1:13] & {13{f_dcd_ex1_bypsel_c_res1}}) | (f_fpr_ex9_frt_expo[1:13] & {13{f_dcd_ex1_bypsel_c_res2}}); + assign ex7_expo_b_res_dly[1:13] = (f_fpr_ex8_frt_expo[1:13] & {13{f_dcd_ex1_bypsel_b_res1}}) | (f_fpr_ex9_frt_expo[1:13] & {13{f_dcd_ex1_bypsel_b_res2}}); + assign ex7_expo_s_res_dly[1:13] = (f_fpr_ex8_frt_expo[1:13] & {13{f_dcd_ex1_bypsel_s_res1}}) | (f_fpr_ex9_frt_expo[1:13] & {13{f_dcd_ex1_bypsel_s_res2}}); + + assign ex6_expo_lod_ear[1:13] = ex6_load_expo[1:13]; + assign ex6_expo_relod_ear[1:13] = ex6_reload_expo[1:13]; + assign ex7_expo_a_lod_dly[1:13] = (({tidn, tidn, f_fpr_ex7_load_expo[3:13]}) & {13{f_dcd_ex1_bypsel_a_load1}}) | (({tidn, tidn, f_fpr_ex8_load_expo[3:13]}) & {13{f_dcd_ex1_bypsel_a_load2}}) | (({tidn, tidn, f_fpr_ex7_reload_expo[3:13]}) & {13{f_dcd_ex1_bypsel_a_reload1}}) | (({tidn, tidn, f_fpr_ex8_reload_expo[3:13]}) & {13{f_dcd_ex1_bypsel_a_reload2}}); + assign ex7_expo_c_lod_dly[1:13] = (({tidn, tidn, f_fpr_ex7_load_expo[3:13]}) & {13{f_dcd_ex1_bypsel_c_load1}}) | (({tidn, tidn, f_fpr_ex8_load_expo[3:13]}) & {13{f_dcd_ex1_bypsel_c_load2}}) | (({tidn, tidn, f_fpr_ex7_reload_expo[3:13]}) & {13{f_dcd_ex1_bypsel_c_reload1}}) | (({tidn, tidn, f_fpr_ex8_reload_expo[3:13]}) & {13{f_dcd_ex1_bypsel_c_reload2}}); + assign ex7_expo_b_lod_dly[1:13] = (({tidn, tidn, f_fpr_ex7_load_expo[3:13]}) & {13{f_dcd_ex1_bypsel_b_load1}}) | (({tidn, tidn, f_fpr_ex8_load_expo[3:13]}) & {13{f_dcd_ex1_bypsel_b_load2}}) | (({tidn, tidn, f_fpr_ex7_reload_expo[3:13]}) & {13{f_dcd_ex1_bypsel_b_reload1}}) | (({tidn, tidn, f_fpr_ex8_reload_expo[3:13]}) & {13{f_dcd_ex1_bypsel_b_reload2}}); + assign ex7_expo_s_lod_dly[1:13] = (({tidn, tidn, f_fpr_ex7_load_expo[3:13]}) & {13{f_dcd_ex1_bypsel_s_load1}}) | (({tidn, tidn, f_fpr_ex8_load_expo[3:13]}) & {13{f_dcd_ex1_bypsel_s_load2}}) | (({tidn, tidn, f_fpr_ex7_reload_expo[3:13]}) & {13{f_dcd_ex1_bypsel_s_reload1}}) | (({tidn, tidn, f_fpr_ex8_reload_expo[3:13]}) & {13{f_dcd_ex1_bypsel_s_reload2}}); + + assign ex1_a_expo_pre1_b[1] = (~((sel_a_res0 & ex7_expo_res_ear[1]) | (sel_a_res1 & ex7_expo_a_res_dly[1]))); + assign ex1_a_expo_pre1_b[2] = (~((sel_a_res0 & ex7_expo_res_ear[2]) | (sel_a_res1 & ex7_expo_a_res_dly[2]))); + assign ex1_a_expo_pre1_b[3] = (~((sel_a_res0 & ex7_expo_res_ear[3]) | (sel_a_res1 & ex7_expo_a_res_dly[3]))); + assign ex1_a_expo_pre1_b[4] = (~((sel_a_res0 & ex7_expo_res_ear[4]) | (sel_a_res1 & ex7_expo_a_res_dly[4]))); + assign ex1_a_expo_pre1_b[5] = (~((sel_a_res0 & ex7_expo_res_ear[5]) | (sel_a_res1 & ex7_expo_a_res_dly[5]))); + assign ex1_a_expo_pre1_b[6] = (~((sel_a_res0 & ex7_expo_res_ear[6]) | (sel_a_res1 & ex7_expo_a_res_dly[6]))); + assign ex1_a_expo_pre1_b[7] = (~((sel_a_res0 & ex7_expo_res_ear[7]) | (sel_a_res1 & ex7_expo_a_res_dly[7]))); + assign ex1_a_expo_pre1_b[8] = (~((sel_a_res0 & ex7_expo_res_ear[8]) | (sel_a_res1 & ex7_expo_a_res_dly[8]))); + assign ex1_a_expo_pre1_b[9] = (~((sel_a_res0 & ex7_expo_res_ear[9]) | (sel_a_res1 & ex7_expo_a_res_dly[9]))); + assign ex1_a_expo_pre1_b[10] = (~((sel_a_res0 & ex7_expo_res_ear[10]) | (sel_a_res1 & ex7_expo_a_res_dly[10]))); + assign ex1_a_expo_pre1_b[11] = (~((sel_a_res0 & ex7_expo_res_ear[11]) | (sel_a_res1 & ex7_expo_a_res_dly[11]))); + assign ex1_a_expo_pre1_b[12] = (~((sel_a_res0 & ex7_expo_res_ear[12]) | (sel_a_res1 & ex7_expo_a_res_dly[12]))); + assign ex1_a_expo_pre1_b[13] = (~((sel_a_res0 & ex7_expo_res_ear[13]) | (sel_a_res1 & ex7_expo_a_res_dly[13]))); + + assign ex1_c_expo_pre1_b[1] = (~((sel_c_res0 & ex7_expo_res_ear[1]) | (sel_c_res1 & ex7_expo_c_res_dly[1]))); + assign ex1_c_expo_pre1_b[2] = (~((sel_c_res0 & ex7_expo_res_ear[2]) | (sel_c_res1 & ex7_expo_c_res_dly[2]))); + assign ex1_c_expo_pre1_b[3] = (~((sel_c_res0 & ex7_expo_res_ear[3]) | (sel_c_res1 & ex7_expo_c_res_dly[3]))); + assign ex1_c_expo_pre1_b[4] = (~((sel_c_res0 & ex7_expo_res_ear[4]) | (sel_c_res1 & ex7_expo_c_res_dly[4]))); + assign ex1_c_expo_pre1_b[5] = (~((sel_c_res0 & ex7_expo_res_ear[5]) | (sel_c_res1 & ex7_expo_c_res_dly[5]))); + assign ex1_c_expo_pre1_b[6] = (~((sel_c_res0 & ex7_expo_res_ear[6]) | (sel_c_res1 & ex7_expo_c_res_dly[6]))); + assign ex1_c_expo_pre1_b[7] = (~((sel_c_res0 & ex7_expo_res_ear[7]) | (sel_c_res1 & ex7_expo_c_res_dly[7]))); + assign ex1_c_expo_pre1_b[8] = (~((sel_c_res0 & ex7_expo_res_ear[8]) | (sel_c_res1 & ex7_expo_c_res_dly[8]))); + assign ex1_c_expo_pre1_b[9] = (~((sel_c_res0 & ex7_expo_res_ear[9]) | (sel_c_res1 & ex7_expo_c_res_dly[9]))); + assign ex1_c_expo_pre1_b[10] = (~((sel_c_res0 & ex7_expo_res_ear[10]) | (sel_c_res1 & ex7_expo_c_res_dly[10]))); + assign ex1_c_expo_pre1_b[11] = (~((sel_c_res0 & ex7_expo_res_ear[11]) | (sel_c_res1 & ex7_expo_c_res_dly[11]))); + assign ex1_c_expo_pre1_b[12] = (~((sel_c_res0 & ex7_expo_res_ear[12]) | (sel_c_res1 & ex7_expo_c_res_dly[12]))); + assign ex1_c_expo_pre1_b[13] = (~((sel_c_res0 & ex7_expo_res_ear[13]) | (sel_c_res1 & ex7_expo_c_res_dly[13]))); + + assign ex1_b_expo_pre1_b[1] = (~((sel_b_res0 & ex7_expo_res_ear[1]) | (sel_b_res1 & ex7_expo_b_res_dly[1]))); + assign ex1_b_expo_pre1_b[2] = (~((sel_b_res0 & ex7_expo_res_ear[2]) | (sel_b_res1 & ex7_expo_b_res_dly[2]))); + assign ex1_b_expo_pre1_b[3] = (~((sel_b_res0 & ex7_expo_res_ear[3]) | (sel_b_res1 & ex7_expo_b_res_dly[3]))); + assign ex1_b_expo_pre1_b[4] = (~((sel_b_res0 & ex7_expo_res_ear[4]) | (sel_b_res1 & ex7_expo_b_res_dly[4]))); + assign ex1_b_expo_pre1_b[5] = (~((sel_b_res0 & ex7_expo_res_ear[5]) | (sel_b_res1 & ex7_expo_b_res_dly[5]))); + assign ex1_b_expo_pre1_b[6] = (~((sel_b_res0 & ex7_expo_res_ear[6]) | (sel_b_res1 & ex7_expo_b_res_dly[6]))); + assign ex1_b_expo_pre1_b[7] = (~((sel_b_res0 & ex7_expo_res_ear[7]) | (sel_b_res1 & ex7_expo_b_res_dly[7]))); + assign ex1_b_expo_pre1_b[8] = (~((sel_b_res0 & ex7_expo_res_ear[8]) | (sel_b_res1 & ex7_expo_b_res_dly[8]))); + assign ex1_b_expo_pre1_b[9] = (~((sel_b_res0 & ex7_expo_res_ear[9]) | (sel_b_res1 & ex7_expo_b_res_dly[9]))); + assign ex1_b_expo_pre1_b[10] = (~((sel_b_res0 & ex7_expo_res_ear[10]) | (sel_b_res1 & ex7_expo_b_res_dly[10]))); + assign ex1_b_expo_pre1_b[11] = (~((sel_b_res0 & ex7_expo_res_ear[11]) | (sel_b_res1 & ex7_expo_b_res_dly[11]))); + assign ex1_b_expo_pre1_b[12] = (~((sel_b_res0 & ex7_expo_res_ear[12]) | (sel_b_res1 & ex7_expo_b_res_dly[12]))); + assign ex1_b_expo_pre1_b[13] = (~((sel_b_res0 & ex7_expo_res_ear[13]) | (sel_b_res1 & ex7_expo_b_res_dly[13]))); + + assign ex1_s_expo_pre1_b[1] = (~((sel_s_res0 & ex7_expo_res_ear[1]) | (sel_s_res1 & ex7_expo_s_res_dly[1]))); + assign ex1_s_expo_pre1_b[2] = (~((sel_s_res0 & ex7_expo_res_ear[2]) | (sel_s_res1 & ex7_expo_s_res_dly[2]))); + assign ex1_s_expo_pre1_b[3] = (~((sel_s_res0 & ex7_expo_res_ear[3]) | (sel_s_res1 & ex7_expo_s_res_dly[3]))); + assign ex1_s_expo_pre1_b[4] = (~((sel_s_res0 & ex7_expo_res_ear[4]) | (sel_s_res1 & ex7_expo_s_res_dly[4]))); + assign ex1_s_expo_pre1_b[5] = (~((sel_s_res0 & ex7_expo_res_ear[5]) | (sel_s_res1 & ex7_expo_s_res_dly[5]))); + assign ex1_s_expo_pre1_b[6] = (~((sel_s_res0 & ex7_expo_res_ear[6]) | (sel_s_res1 & ex7_expo_s_res_dly[6]))); + assign ex1_s_expo_pre1_b[7] = (~((sel_s_res0 & ex7_expo_res_ear[7]) | (sel_s_res1 & ex7_expo_s_res_dly[7]))); + assign ex1_s_expo_pre1_b[8] = (~((sel_s_res0 & ex7_expo_res_ear[8]) | (sel_s_res1 & ex7_expo_s_res_dly[8]))); + assign ex1_s_expo_pre1_b[9] = (~((sel_s_res0 & ex7_expo_res_ear[9]) | (sel_s_res1 & ex7_expo_s_res_dly[9]))); + assign ex1_s_expo_pre1_b[10] = (~((sel_s_res0 & ex7_expo_res_ear[10]) | (sel_s_res1 & ex7_expo_s_res_dly[10]))); + assign ex1_s_expo_pre1_b[11] = (~((sel_s_res0 & ex7_expo_res_ear[11]) | (sel_s_res1 & ex7_expo_s_res_dly[11]))); + assign ex1_s_expo_pre1_b[12] = (~((sel_s_res0 & ex7_expo_res_ear[12]) | (sel_s_res1 & ex7_expo_s_res_dly[12]))); + assign ex1_s_expo_pre1_b[13] = (~((sel_s_res0 & ex7_expo_res_ear[13]) | (sel_s_res1 & ex7_expo_s_res_dly[13]))); + + assign ex1_a_expo_pre2_b[1] = (~((sel_a_load0 & ex6_expo_lod_ear[1]) | (sel_a_reload0 & ex6_expo_relod_ear[1]) | (sel_a_load1 & ex7_expo_a_lod_dly[1]))); + assign ex1_a_expo_pre2_b[2] = (~((sel_a_load0 & ex6_expo_lod_ear[2]) | (sel_a_reload0 & ex6_expo_relod_ear[2]) | (sel_a_load1 & ex7_expo_a_lod_dly[2]))); + assign ex1_a_expo_pre2_b[3] = (~((sel_a_load0 & ex6_expo_lod_ear[3]) | (sel_a_reload0 & ex6_expo_relod_ear[3]) | (sel_a_load1 & ex7_expo_a_lod_dly[3]))); + assign ex1_a_expo_pre2_b[4] = (~((sel_a_load0 & ex6_expo_lod_ear[4]) | (sel_a_reload0 & ex6_expo_relod_ear[4]) | (sel_a_load1 & ex7_expo_a_lod_dly[4]))); + assign ex1_a_expo_pre2_b[5] = (~((sel_a_load0 & ex6_expo_lod_ear[5]) | (sel_a_reload0 & ex6_expo_relod_ear[5]) | (sel_a_load1 & ex7_expo_a_lod_dly[5]))); + assign ex1_a_expo_pre2_b[6] = (~((sel_a_load0 & ex6_expo_lod_ear[6]) | (sel_a_reload0 & ex6_expo_relod_ear[6]) | (sel_a_load1 & ex7_expo_a_lod_dly[6]))); + assign ex1_a_expo_pre2_b[7] = (~((sel_a_load0 & ex6_expo_lod_ear[7]) | (sel_a_reload0 & ex6_expo_relod_ear[7]) | (sel_a_load1 & ex7_expo_a_lod_dly[7]))); + assign ex1_a_expo_pre2_b[8] = (~((sel_a_load0 & ex6_expo_lod_ear[8]) | (sel_a_reload0 & ex6_expo_relod_ear[8]) | (sel_a_load1 & ex7_expo_a_lod_dly[8]))); + assign ex1_a_expo_pre2_b[9] = (~((sel_a_load0 & ex6_expo_lod_ear[9]) | (sel_a_reload0 & ex6_expo_relod_ear[9]) | (sel_a_load1 & ex7_expo_a_lod_dly[9]))); + assign ex1_a_expo_pre2_b[10] = (~((sel_a_load0 & ex6_expo_lod_ear[10]) | (sel_a_reload0 & ex6_expo_relod_ear[10]) | (sel_a_load1 & ex7_expo_a_lod_dly[10]))); + assign ex1_a_expo_pre2_b[11] = (~((sel_a_load0 & ex6_expo_lod_ear[11]) | (sel_a_reload0 & ex6_expo_relod_ear[11]) | (sel_a_load1 & ex7_expo_a_lod_dly[11]))); + assign ex1_a_expo_pre2_b[12] = (~((sel_a_load0 & ex6_expo_lod_ear[12]) | (sel_a_reload0 & ex6_expo_relod_ear[12]) | (sel_a_load1 & ex7_expo_a_lod_dly[12]))); + assign ex1_a_expo_pre2_b[13] = (~((sel_a_load0 & ex6_expo_lod_ear[13]) | (sel_a_reload0 & ex6_expo_relod_ear[13]) | (sel_a_load1 & ex7_expo_a_lod_dly[13]))); + + assign ex1_c_expo_pre2_b[1] = (~((sel_c_load0 & ex6_expo_lod_ear[1]) | (sel_c_reload0 & ex6_expo_relod_ear[1]) | (sel_c_load1 & ex7_expo_c_lod_dly[1]))); + assign ex1_c_expo_pre2_b[2] = (~((sel_c_load0 & ex6_expo_lod_ear[2]) | (sel_c_reload0 & ex6_expo_relod_ear[2]) | (sel_c_load1 & ex7_expo_c_lod_dly[2]))); + assign ex1_c_expo_pre2_b[3] = (~((sel_c_load0 & ex6_expo_lod_ear[3]) | (sel_c_reload0 & ex6_expo_relod_ear[3]) | (sel_c_load1 & ex7_expo_c_lod_dly[3]))); + assign ex1_c_expo_pre2_b[4] = (~((sel_c_load0 & ex6_expo_lod_ear[4]) | (sel_c_reload0 & ex6_expo_relod_ear[4]) | (sel_c_load1 & ex7_expo_c_lod_dly[4]))); + assign ex1_c_expo_pre2_b[5] = (~((sel_c_load0 & ex6_expo_lod_ear[5]) | (sel_c_reload0 & ex6_expo_relod_ear[5]) | (sel_c_load1 & ex7_expo_c_lod_dly[5]))); + assign ex1_c_expo_pre2_b[6] = (~((sel_c_load0 & ex6_expo_lod_ear[6]) | (sel_c_reload0 & ex6_expo_relod_ear[6]) | (sel_c_load1 & ex7_expo_c_lod_dly[6]))); + assign ex1_c_expo_pre2_b[7] = (~((sel_c_load0 & ex6_expo_lod_ear[7]) | (sel_c_reload0 & ex6_expo_relod_ear[7]) | (sel_c_load1 & ex7_expo_c_lod_dly[7]))); + assign ex1_c_expo_pre2_b[8] = (~((sel_c_load0 & ex6_expo_lod_ear[8]) | (sel_c_reload0 & ex6_expo_relod_ear[8]) | (sel_c_load1 & ex7_expo_c_lod_dly[8]))); + assign ex1_c_expo_pre2_b[9] = (~((sel_c_load0 & ex6_expo_lod_ear[9]) | (sel_c_reload0 & ex6_expo_relod_ear[9]) | (sel_c_load1 & ex7_expo_c_lod_dly[9]))); + assign ex1_c_expo_pre2_b[10] = (~((sel_c_load0 & ex6_expo_lod_ear[10]) | (sel_c_reload0 & ex6_expo_relod_ear[10]) | (sel_c_load1 & ex7_expo_c_lod_dly[10]))); + assign ex1_c_expo_pre2_b[11] = (~((sel_c_load0 & ex6_expo_lod_ear[11]) | (sel_c_reload0 & ex6_expo_relod_ear[11]) | (sel_c_load1 & ex7_expo_c_lod_dly[11]))); + assign ex1_c_expo_pre2_b[12] = (~((sel_c_load0 & ex6_expo_lod_ear[12]) | (sel_c_reload0 & ex6_expo_relod_ear[12]) | (sel_c_load1 & ex7_expo_c_lod_dly[12]))); + assign ex1_c_expo_pre2_b[13] = (~((sel_c_load0 & ex6_expo_lod_ear[13]) | (sel_c_reload0 & ex6_expo_relod_ear[13]) | (sel_c_load1 & ex7_expo_c_lod_dly[13]))); + + assign ex1_b_expo_pre2_b[1] = (~((sel_b_load0 & ex6_expo_lod_ear[1]) | (sel_b_reload0 & ex6_expo_relod_ear[1]) | (sel_b_load1 & ex7_expo_b_lod_dly[1]))); + assign ex1_b_expo_pre2_b[2] = (~((sel_b_load0 & ex6_expo_lod_ear[2]) | (sel_b_reload0 & ex6_expo_relod_ear[2]) | (sel_b_load1 & ex7_expo_b_lod_dly[2]))); + assign ex1_b_expo_pre2_b[3] = (~((sel_b_load0 & ex6_expo_lod_ear[3]) | (sel_b_reload0 & ex6_expo_relod_ear[3]) | (sel_b_load1 & ex7_expo_b_lod_dly[3]))); + assign ex1_b_expo_pre2_b[4] = (~((sel_b_load0 & ex6_expo_lod_ear[4]) | (sel_b_reload0 & ex6_expo_relod_ear[4]) | (sel_b_load1 & ex7_expo_b_lod_dly[4]))); + assign ex1_b_expo_pre2_b[5] = (~((sel_b_load0 & ex6_expo_lod_ear[5]) | (sel_b_reload0 & ex6_expo_relod_ear[5]) | (sel_b_load1 & ex7_expo_b_lod_dly[5]))); + assign ex1_b_expo_pre2_b[6] = (~((sel_b_load0 & ex6_expo_lod_ear[6]) | (sel_b_reload0 & ex6_expo_relod_ear[6]) | (sel_b_load1 & ex7_expo_b_lod_dly[6]))); + assign ex1_b_expo_pre2_b[7] = (~((sel_b_load0 & ex6_expo_lod_ear[7]) | (sel_b_reload0 & ex6_expo_relod_ear[7]) | (sel_b_load1 & ex7_expo_b_lod_dly[7]))); + assign ex1_b_expo_pre2_b[8] = (~((sel_b_load0 & ex6_expo_lod_ear[8]) | (sel_b_reload0 & ex6_expo_relod_ear[8]) | (sel_b_load1 & ex7_expo_b_lod_dly[8]))); + assign ex1_b_expo_pre2_b[9] = (~((sel_b_load0 & ex6_expo_lod_ear[9]) | (sel_b_reload0 & ex6_expo_relod_ear[9]) | (sel_b_load1 & ex7_expo_b_lod_dly[9]))); + assign ex1_b_expo_pre2_b[10] = (~((sel_b_load0 & ex6_expo_lod_ear[10]) | (sel_b_reload0 & ex6_expo_relod_ear[10]) | (sel_b_load1 & ex7_expo_b_lod_dly[10]))); + assign ex1_b_expo_pre2_b[11] = (~((sel_b_load0 & ex6_expo_lod_ear[11]) | (sel_b_reload0 & ex6_expo_relod_ear[11]) | (sel_b_load1 & ex7_expo_b_lod_dly[11]))); + assign ex1_b_expo_pre2_b[12] = (~((sel_b_load0 & ex6_expo_lod_ear[12]) | (sel_b_reload0 & ex6_expo_relod_ear[12]) | (sel_b_load1 & ex7_expo_b_lod_dly[12]))); + assign ex1_b_expo_pre2_b[13] = (~((sel_b_load0 & ex6_expo_lod_ear[13]) | (sel_b_reload0 & ex6_expo_relod_ear[13]) | (sel_b_load1 & ex7_expo_b_lod_dly[13]))); + + assign ex1_s_expo_pre2_b[1] = (~((sel_s_load0 & ex6_expo_lod_ear[1]) | (sel_s_reload0 & ex6_expo_relod_ear[1]) | (sel_s_load1 & ex7_expo_s_lod_dly[1]) )) ; + assign ex1_s_expo_pre2_b[2] = (~((sel_s_load0 & ex6_expo_lod_ear[2]) | (sel_s_reload0 & ex6_expo_relod_ear[2]) | (sel_s_load1 & ex7_expo_s_lod_dly[2]) )) ; + assign ex1_s_expo_pre2_b[3] = (~((sel_s_load0 & ex6_expo_lod_ear[3]) | (sel_s_reload0 & ex6_expo_relod_ear[3]) | (sel_s_load1 & ex7_expo_s_lod_dly[3]) )) ; + assign ex1_s_expo_pre2_b[4] = (~((sel_s_load0 & ex6_expo_lod_ear[4]) | (sel_s_reload0 & ex6_expo_relod_ear[4]) | (sel_s_load1 & ex7_expo_s_lod_dly[4]) )) ; + assign ex1_s_expo_pre2_b[5] = (~((sel_s_load0 & ex6_expo_lod_ear[5]) | (sel_s_reload0 & ex6_expo_relod_ear[5]) | (sel_s_load1 & ex7_expo_s_lod_dly[5]) )) ; + assign ex1_s_expo_pre2_b[6] = (~((sel_s_load0 & ex6_expo_lod_ear[6]) | (sel_s_reload0 & ex6_expo_relod_ear[6]) | (sel_s_load1 & ex7_expo_s_lod_dly[6]) )) ; + assign ex1_s_expo_pre2_b[7] = (~((sel_s_load0 & ex6_expo_lod_ear[7]) | (sel_s_reload0 & ex6_expo_relod_ear[7]) | (sel_s_load1 & ex7_expo_s_lod_dly[7]) )) ; + assign ex1_s_expo_pre2_b[8] = (~((sel_s_load0 & ex6_expo_lod_ear[8]) | (sel_s_reload0 & ex6_expo_relod_ear[8]) | (sel_s_load1 & ex7_expo_s_lod_dly[8]) )) ; + assign ex1_s_expo_pre2_b[9] = (~((sel_s_load0 & ex6_expo_lod_ear[9]) | (sel_s_reload0 & ex6_expo_relod_ear[9]) | (sel_s_load1 & ex7_expo_s_lod_dly[9]) )) ; + assign ex1_s_expo_pre2_b[10] = (~((sel_s_load0 & ex6_expo_lod_ear[10]) | (sel_s_reload0 & ex6_expo_relod_ear[10]) | (sel_s_load1 & ex7_expo_s_lod_dly[10]))); + assign ex1_s_expo_pre2_b[11] = (~((sel_s_load0 & ex6_expo_lod_ear[11]) | (sel_s_reload0 & ex6_expo_relod_ear[11]) | (sel_s_load1 & ex7_expo_s_lod_dly[11]))); + assign ex1_s_expo_pre2_b[12] = (~((sel_s_load0 & ex6_expo_lod_ear[12]) | (sel_s_reload0 & ex6_expo_relod_ear[12]) | (sel_s_load1 & ex7_expo_s_lod_dly[12]))); + assign ex1_s_expo_pre2_b[13] = (~((sel_s_load0 & ex6_expo_lod_ear[13]) | (sel_s_reload0 & ex6_expo_relod_ear[13]) | (sel_s_load1 & ex7_expo_s_lod_dly[13]))); + + assign ex1_a_expo_pre3_b[1] = (~(tidn)); + assign ex1_a_expo_pre3_b[2] = (~(tidn)); + assign ex1_a_expo_pre3_b[3] = (~(sel_a_imm & ex1_a_k_expo[3])); + assign ex1_a_expo_pre3_b[4] = (~(sel_a_imm & ex1_a_k_expo[4])); + assign ex1_a_expo_pre3_b[5] = (~(sel_a_imm & ex1_a_k_expo[5])); + assign ex1_a_expo_pre3_b[6] = (~(sel_a_imm & ex1_a_k_expo[6])); + assign ex1_a_expo_pre3_b[7] = (~(sel_a_imm & ex1_a_k_expo[7])); + assign ex1_a_expo_pre3_b[8] = (~(sel_a_imm & ex1_a_k_expo[8])); + assign ex1_a_expo_pre3_b[9] = (~(sel_a_imm & ex1_a_k_expo[9])); + assign ex1_a_expo_pre3_b[10] = (~(sel_a_imm & ex1_a_k_expo[10])); + assign ex1_a_expo_pre3_b[11] = (~(sel_a_imm & ex1_a_k_expo[11])); + assign ex1_a_expo_pre3_b[12] = (~(sel_a_imm & ex1_a_k_expo[12])); + assign ex1_a_expo_pre3_b[13] = (~(sel_a_imm & ex1_a_k_expo[13])); + + assign ex1_c_expo_pre3_b[1] = (~(tidn)); + assign ex1_c_expo_pre3_b[2] = (~(tidn)); + assign ex1_c_expo_pre3_b[3] = (~(tidn)); + assign ex1_c_expo_pre3_b[4] = (~(sel_c_imm)); + assign ex1_c_expo_pre3_b[5] = (~(sel_c_imm)); + assign ex1_c_expo_pre3_b[6] = (~(sel_c_imm)); + assign ex1_c_expo_pre3_b[7] = (~(sel_c_imm)); + assign ex1_c_expo_pre3_b[8] = (~(sel_c_imm)); + assign ex1_c_expo_pre3_b[9] = (~(sel_c_imm)); + assign ex1_c_expo_pre3_b[10] = (~(sel_c_imm)); + assign ex1_c_expo_pre3_b[11] = (~(sel_c_imm)); + assign ex1_c_expo_pre3_b[12] = (~(sel_c_imm)); + assign ex1_c_expo_pre3_b[13] = (~(sel_c_imm & ex1_c_k_expo[13])); + + assign ex1_b_expo_pre3_b[1] = (~(tidn)); + assign ex1_b_expo_pre3_b[2] = (~(tidn)); + assign ex1_b_expo_pre3_b[3] = (~(tidn)); + assign ex1_b_expo_pre3_b[4] = (~(sel_b_imm & ex1_b_k_expo[4])); + assign ex1_b_expo_pre3_b[5] = (~(sel_b_imm & ex1_b_k_expo[5])); + assign ex1_b_expo_pre3_b[6] = (~(sel_b_imm & ex1_b_k_expo[6])); + assign ex1_b_expo_pre3_b[7] = (~(sel_b_imm & ex1_b_k_expo[7])); + assign ex1_b_expo_pre3_b[8] = (~(sel_b_imm & ex1_b_k_expo[8])); + assign ex1_b_expo_pre3_b[9] = (~(sel_b_imm & ex1_b_k_expo[9])); + assign ex1_b_expo_pre3_b[10] = (~(sel_b_imm & ex1_b_k_expo[10])); + assign ex1_b_expo_pre3_b[11] = (~(sel_b_imm & ex1_b_k_expo[11])); + assign ex1_b_expo_pre3_b[12] = (~(sel_b_imm & ex1_b_k_expo[12])); + assign ex1_b_expo_pre3_b[13] = (~(sel_b_imm & ex1_b_k_expo[13])); + + assign ex1_s_expo_pre3_b[1:13] = {13{tiup}}; + + assign ex1_a_expo_pre[1] = (~(ex1_a_expo_pre1_b[1] & ex1_a_expo_pre2_b[1])); + assign ex1_a_expo_pre[2] = (~(ex1_a_expo_pre1_b[2] & ex1_a_expo_pre2_b[2])); + assign ex1_a_expo_pre[3] = (~(ex1_a_expo_pre1_b[3] & ex1_a_expo_pre2_b[3] & ex1_a_expo_pre3_b[3])); + assign ex1_a_expo_pre[4] = (~(ex1_a_expo_pre1_b[4] & ex1_a_expo_pre2_b[4] & ex1_a_expo_pre3_b[4])); + assign ex1_a_expo_pre[5] = (~(ex1_a_expo_pre1_b[5] & ex1_a_expo_pre2_b[5] & ex1_a_expo_pre3_b[5])); + assign ex1_a_expo_pre[6] = (~(ex1_a_expo_pre1_b[6] & ex1_a_expo_pre2_b[6] & ex1_a_expo_pre3_b[6])); + assign ex1_a_expo_pre[7] = (~(ex1_a_expo_pre1_b[7] & ex1_a_expo_pre2_b[7] & ex1_a_expo_pre3_b[7])); + assign ex1_a_expo_pre[8] = (~(ex1_a_expo_pre1_b[8] & ex1_a_expo_pre2_b[8] & ex1_a_expo_pre3_b[8])); + assign ex1_a_expo_pre[9] = (~(ex1_a_expo_pre1_b[9] & ex1_a_expo_pre2_b[9] & ex1_a_expo_pre3_b[9])); + assign ex1_a_expo_pre[10] = (~(ex1_a_expo_pre1_b[10] & ex1_a_expo_pre2_b[10] & ex1_a_expo_pre3_b[10])); + assign ex1_a_expo_pre[11] = (~(ex1_a_expo_pre1_b[11] & ex1_a_expo_pre2_b[11] & ex1_a_expo_pre3_b[11])); + assign ex1_a_expo_pre[12] = (~(ex1_a_expo_pre1_b[12] & ex1_a_expo_pre2_b[12] & ex1_a_expo_pre3_b[12])); + assign ex1_a_expo_pre[13] = (~(ex1_a_expo_pre1_b[13] & ex1_a_expo_pre2_b[13] & ex1_a_expo_pre3_b[13])); + + assign ex1_c_expo_pre[1] = (~(ex1_c_expo_pre1_b[1] & ex1_c_expo_pre2_b[1])); + assign ex1_c_expo_pre[2] = (~(ex1_c_expo_pre1_b[2] & ex1_c_expo_pre2_b[2])); + assign ex1_c_expo_pre[3] = (~(ex1_c_expo_pre1_b[3] & ex1_c_expo_pre2_b[3])); + assign ex1_c_expo_pre[4] = (~(ex1_c_expo_pre1_b[4] & ex1_c_expo_pre2_b[4] & ex1_c_expo_pre3_b[4])); + assign ex1_c_expo_pre[5] = (~(ex1_c_expo_pre1_b[5] & ex1_c_expo_pre2_b[5] & ex1_c_expo_pre3_b[5])); + assign ex1_c_expo_pre[6] = (~(ex1_c_expo_pre1_b[6] & ex1_c_expo_pre2_b[6] & ex1_c_expo_pre3_b[6])); + assign ex1_c_expo_pre[7] = (~(ex1_c_expo_pre1_b[7] & ex1_c_expo_pre2_b[7] & ex1_c_expo_pre3_b[7])); + assign ex1_c_expo_pre[8] = (~(ex1_c_expo_pre1_b[8] & ex1_c_expo_pre2_b[8] & ex1_c_expo_pre3_b[8])); + assign ex1_c_expo_pre[9] = (~(ex1_c_expo_pre1_b[9] & ex1_c_expo_pre2_b[9] & ex1_c_expo_pre3_b[9])); + assign ex1_c_expo_pre[10] = (~(ex1_c_expo_pre1_b[10] & ex1_c_expo_pre2_b[10] & ex1_c_expo_pre3_b[10])); + assign ex1_c_expo_pre[11] = (~(ex1_c_expo_pre1_b[11] & ex1_c_expo_pre2_b[11] & ex1_c_expo_pre3_b[11])); + assign ex1_c_expo_pre[12] = (~(ex1_c_expo_pre1_b[12] & ex1_c_expo_pre2_b[12] & ex1_c_expo_pre3_b[12])); + assign ex1_c_expo_pre[13] = (~(ex1_c_expo_pre1_b[13] & ex1_c_expo_pre2_b[13] & ex1_c_expo_pre3_b[13])); + + assign ex1_b_expo_pre[1] = (~(ex1_b_expo_pre1_b[1] & ex1_b_expo_pre2_b[1])); + assign ex1_b_expo_pre[2] = (~(ex1_b_expo_pre1_b[2] & ex1_b_expo_pre2_b[2])); + assign ex1_b_expo_pre[3] = (~(ex1_b_expo_pre1_b[3] & ex1_b_expo_pre2_b[3])); + assign ex1_b_expo_pre[4] = (~(ex1_b_expo_pre1_b[4] & ex1_b_expo_pre2_b[4] & ex1_b_expo_pre3_b[4])); + assign ex1_b_expo_pre[5] = (~(ex1_b_expo_pre1_b[5] & ex1_b_expo_pre2_b[5] & ex1_b_expo_pre3_b[5])); + assign ex1_b_expo_pre[6] = (~(ex1_b_expo_pre1_b[6] & ex1_b_expo_pre2_b[6] & ex1_b_expo_pre3_b[6])); + assign ex1_b_expo_pre[7] = (~(ex1_b_expo_pre1_b[7] & ex1_b_expo_pre2_b[7] & ex1_b_expo_pre3_b[7])); + assign ex1_b_expo_pre[8] = (~(ex1_b_expo_pre1_b[8] & ex1_b_expo_pre2_b[8] & ex1_b_expo_pre3_b[8])); + assign ex1_b_expo_pre[9] = (~(ex1_b_expo_pre1_b[9] & ex1_b_expo_pre2_b[9] & ex1_b_expo_pre3_b[9])); + assign ex1_b_expo_pre[10] = (~(ex1_b_expo_pre1_b[10] & ex1_b_expo_pre2_b[10] & ex1_b_expo_pre3_b[10])); + assign ex1_b_expo_pre[11] = (~(ex1_b_expo_pre1_b[11] & ex1_b_expo_pre2_b[11] & ex1_b_expo_pre3_b[11])); + assign ex1_b_expo_pre[12] = (~(ex1_b_expo_pre1_b[12] & ex1_b_expo_pre2_b[12] & ex1_b_expo_pre3_b[12])); + assign ex1_b_expo_pre[13] = (~(ex1_b_expo_pre1_b[13] & ex1_b_expo_pre2_b[13] & ex1_b_expo_pre3_b[13])); + + assign ex1_s_expo_pre[1] = (~(ex1_s_expo_pre1_b[1] & ex1_s_expo_pre2_b[1])); + assign ex1_s_expo_pre[2] = (~(ex1_s_expo_pre1_b[2] & ex1_s_expo_pre2_b[2])); + assign ex1_s_expo_pre[3] = (~(ex1_s_expo_pre1_b[3] & ex1_s_expo_pre2_b[3])); + assign ex1_s_expo_pre[4] = (~(ex1_s_expo_pre1_b[4] & ex1_s_expo_pre2_b[4] & ex1_s_expo_pre3_b[4])); + assign ex1_s_expo_pre[5] = (~(ex1_s_expo_pre1_b[5] & ex1_s_expo_pre2_b[5] & ex1_s_expo_pre3_b[5])); + assign ex1_s_expo_pre[6] = (~(ex1_s_expo_pre1_b[6] & ex1_s_expo_pre2_b[6] & ex1_s_expo_pre3_b[6])); + assign ex1_s_expo_pre[7] = (~(ex1_s_expo_pre1_b[7] & ex1_s_expo_pre2_b[7] & ex1_s_expo_pre3_b[7])); + assign ex1_s_expo_pre[8] = (~(ex1_s_expo_pre1_b[8] & ex1_s_expo_pre2_b[8] & ex1_s_expo_pre3_b[8])); + assign ex1_s_expo_pre[9] = (~(ex1_s_expo_pre1_b[9] & ex1_s_expo_pre2_b[9] & ex1_s_expo_pre3_b[9])); + assign ex1_s_expo_pre[10] = (~(ex1_s_expo_pre1_b[10] & ex1_s_expo_pre2_b[10] & ex1_s_expo_pre3_b[10])); + assign ex1_s_expo_pre[11] = (~(ex1_s_expo_pre1_b[11] & ex1_s_expo_pre2_b[11] & ex1_s_expo_pre3_b[11])); + assign ex1_s_expo_pre[12] = (~(ex1_s_expo_pre1_b[12] & ex1_s_expo_pre2_b[12] & ex1_s_expo_pre3_b[12])); + assign ex1_s_expo_pre[13] = (~(ex1_s_expo_pre1_b[13] & ex1_s_expo_pre2_b[13] & ex1_s_expo_pre3_b[13])); + + assign ex1_a_expo_prebyp[1:13] = ex1_a_expo_pre[1:13]; // may need to manually repower + assign ex1_c_expo_prebyp[1:13] = ex1_c_expo_pre[1:13]; // may need to manually repower + assign ex1_b_expo_prebyp[1:13] = ex1_b_expo_pre[1:13]; // may need to manually repower + assign ex1_s_expo_prebyp[1:13] = ex1_s_expo_pre[1:13]; // may need to manually repower + + //------------------------ + // fraction + //------------------------ + + assign ex7_frac_res_ear[0:52] = f_rnd_ex7_res_frac[0:52]; + assign ex7_frac_a_res_dly[0:52] = (f_fpr_ex8_frt_frac[0:52] & {53{f_dcd_ex1_bypsel_a_res1}}) | (f_fpr_ex9_frt_frac[0:52] & {53{f_dcd_ex1_bypsel_a_res2}}); + assign ex7_frac_c_res_dly[0:52] = (f_fpr_ex8_frt_frac[0:52] & {53{f_dcd_ex1_bypsel_c_res1}}) | (f_fpr_ex9_frt_frac[0:52] & {53{f_dcd_ex1_bypsel_c_res2}}); + assign ex7_frac_b_res_dly[0:52] = (f_fpr_ex8_frt_frac[0:52] & {53{f_dcd_ex1_bypsel_b_res1}}) | (f_fpr_ex9_frt_frac[0:52] & {53{f_dcd_ex1_bypsel_b_res2}}); + assign ex7_frac_s_res_dly[0:52] = (f_fpr_ex8_frt_frac[0:52] & {53{f_dcd_ex1_bypsel_s_res1}}) | (f_fpr_ex9_frt_frac[0:52] & {53{f_dcd_ex1_bypsel_s_res2}}); + assign ex6_frac_lod_ear[0:52] = f_fpr_ex6_load_frac[0:52]; + assign ex6_frac_relod_ear[0:52] = f_fpr_ex6_reload_frac[0:52]; + assign ex7_frac_a_lod_dly[0:52] = (f_fpr_ex7_load_frac[0:52] & {53{f_dcd_ex1_bypsel_a_load1}}) | (f_fpr_ex8_load_frac[0:52] & {53{f_dcd_ex1_bypsel_a_load2}}) | (f_fpr_ex7_reload_frac[0:52] & {53{f_dcd_ex1_bypsel_a_reload1}}) | (f_fpr_ex8_reload_frac[0:52] & {53{f_dcd_ex1_bypsel_a_reload2}}); + assign ex7_frac_c_lod_dly[0:52] = (f_fpr_ex7_load_frac[0:52] & {53{f_dcd_ex1_bypsel_c_load1}}) | (f_fpr_ex8_load_frac[0:52] & {53{f_dcd_ex1_bypsel_c_load2}}) | (f_fpr_ex7_reload_frac[0:52] & {53{f_dcd_ex1_bypsel_c_reload1}}) | (f_fpr_ex8_reload_frac[0:52] & {53{f_dcd_ex1_bypsel_c_reload2}}); + assign ex7_frac_b_lod_dly[0:52] = (f_fpr_ex7_load_frac[0:52] & {53{f_dcd_ex1_bypsel_b_load1}}) | (f_fpr_ex8_load_frac[0:52] & {53{f_dcd_ex1_bypsel_b_load2}}) | (f_fpr_ex7_reload_frac[0:52] & {53{f_dcd_ex1_bypsel_b_reload1}}) | (f_fpr_ex8_reload_frac[0:52] & {53{f_dcd_ex1_bypsel_b_reload2}}); + assign ex7_frac_s_lod_dly[0:52] = (f_fpr_ex7_load_frac[0:52] & {53{f_dcd_ex1_bypsel_s_load1}}) | (f_fpr_ex8_load_frac[0:52] & {53{f_dcd_ex1_bypsel_s_load2}}) | (f_fpr_ex7_reload_frac[0:52] & {53{f_dcd_ex1_bypsel_s_reload1}}) | (f_fpr_ex8_reload_frac[0:52] & {53{f_dcd_ex1_bypsel_s_reload2}}); + + assign ex1_c_frac_pre3_b[0] = (~(sel_c_imm & ex1_c_k_frac[0])); + assign ex1_c_frac_pre3_b[1] = (~(sel_c_imm & ex1_c_k_frac[1])); + assign ex1_c_frac_pre3_b[2] = (~(sel_c_imm & ex1_c_k_frac[2])); + assign ex1_c_frac_pre3_b[3] = (~(sel_c_imm & ex1_c_k_frac[3])); + assign ex1_c_frac_pre3_b[4] = (~(sel_c_imm & ex1_c_k_frac[4])); + assign ex1_c_frac_pre3_b[5] = (~(sel_c_imm & ex1_c_k_frac[5])); + assign ex1_c_frac_pre3_b[6] = (~(sel_c_imm & ex1_c_k_frac[6])); + assign ex1_c_frac_pre3_b[7] = (~(sel_c_imm & ex1_c_k_frac[7])); + assign ex1_c_frac_pre3_b[8] = (~(sel_c_imm & ex1_c_k_frac[8])); + assign ex1_c_frac_pre3_b[9] = (~(sel_c_imm & ex1_c_k_frac[9])); + assign ex1_c_frac_pre3_b[10] = (~(sel_c_imm & ex1_c_k_frac[10])); + assign ex1_c_frac_pre3_b[11] = (~(sel_c_imm & ex1_c_k_frac[11])); + assign ex1_c_frac_pre3_b[12] = (~(sel_c_imm & ex1_c_k_frac[12])); + assign ex1_c_frac_pre3_b[13] = (~(sel_c_imm & ex1_c_k_frac[13])); + assign ex1_c_frac_pre3_b[14] = (~(sel_c_imm & ex1_c_k_frac[14])); + assign ex1_c_frac_pre3_b[15] = (~(sel_c_imm & ex1_c_k_frac[15])); + assign ex1_c_frac_pre3_b[16] = (~(sel_c_imm & ex1_c_k_frac[16])); + assign ex1_c_frac_pre3_b[17] = (~(sel_c_imm & ex1_c_k_frac[17])); + assign ex1_c_frac_pre3_b[18] = (~(sel_c_imm & ex1_c_k_frac[18])); + assign ex1_c_frac_pre3_b[19] = (~(sel_c_imm & ex1_c_k_frac[19])); + assign ex1_c_frac_pre3_b[20] = (~(sel_c_imm & ex1_c_k_frac[20])); + assign ex1_c_frac_pre3_b[21] = (~(sel_c_imm & ex1_c_k_frac[21])); + assign ex1_c_frac_pre3_b[22] = (~(sel_c_imm & ex1_c_k_frac[22])); + assign ex1_c_frac_pre3_b[23] = (~(sel_c_imm & ex1_c_k_frac[23])); + assign ex1_c_frac_pre3_b[24] = (~(sel_c_imm & ex1_c_k_frac[24])); + assign ex1_c_frac_pre3_b[25] = (~(sel_c_imm & ex1_c_k_frac[25])); + assign ex1_c_frac_pre3_b[26] = (~(sel_c_imm & ex1_c_k_frac[26])); + assign ex1_c_frac_pre3_b[27] = (~(sel_c_imm & ex1_c_k_frac[27])); + assign ex1_c_frac_pre3_b[28] = (~(sel_c_imm & ex1_c_k_frac[28])); + assign ex1_c_frac_pre3_b[29] = (~(sel_c_imm & ex1_c_k_frac[29])); + assign ex1_c_frac_pre3_b[30] = (~(sel_c_imm & ex1_c_k_frac[30])); + assign ex1_c_frac_pre3_b[31] = (~(sel_c_imm & ex1_c_k_frac[31])); + assign ex1_c_frac_pre3_b[32] = (~(sel_c_imm & ex1_c_k_frac[32])); + assign ex1_c_frac_pre3_b[33] = (~(sel_c_imm & ex1_c_k_frac[33])); + assign ex1_c_frac_pre3_b[34] = (~(sel_c_imm & ex1_c_k_frac[34])); + assign ex1_c_frac_pre3_b[35] = (~(sel_c_imm & ex1_c_k_frac[35])); + assign ex1_c_frac_pre3_b[36] = (~(sel_c_imm & ex1_c_k_frac[36])); + assign ex1_c_frac_pre3_b[37] = (~(sel_c_imm & ex1_c_k_frac[37])); + assign ex1_c_frac_pre3_b[38] = (~(sel_c_imm & ex1_c_k_frac[38])); + assign ex1_c_frac_pre3_b[39] = (~(sel_c_imm & ex1_c_k_frac[39])); + assign ex1_c_frac_pre3_b[40] = (~(sel_c_imm & ex1_c_k_frac[40])); + assign ex1_c_frac_pre3_b[41] = (~(sel_c_imm & ex1_c_k_frac[41])); + assign ex1_c_frac_pre3_b[42] = (~(sel_c_imm & ex1_c_k_frac[42])); + assign ex1_c_frac_pre3_b[43] = (~(sel_c_imm & ex1_c_k_frac[43])); + assign ex1_c_frac_pre3_b[44] = (~(sel_c_imm & ex1_c_k_frac[44])); + assign ex1_c_frac_pre3_b[45] = (~(sel_c_imm & ex1_c_k_frac[45])); + assign ex1_c_frac_pre3_b[46] = (~(sel_c_imm & ex1_c_k_frac[46])); + assign ex1_c_frac_pre3_b[47] = (~(sel_c_imm & ex1_c_k_frac[47])); + assign ex1_c_frac_pre3_b[48] = (~(sel_c_imm & ex1_c_k_frac[48])); + assign ex1_c_frac_pre3_b[49] = (~(sel_c_imm & ex1_c_k_frac[49])); + assign ex1_c_frac_pre3_b[50] = (~(sel_c_imm & ex1_c_k_frac[50])); + assign ex1_c_frac_pre3_b[51] = (~(sel_c_imm & ex1_c_k_frac[51])); + assign ex1_c_frac_pre3_b[52] = (~(sel_c_imm & ex1_c_k_frac[52])); + + assign ex1_c_frac_pre3_hulp_b = (~((sel_c_imm & ex1_c_k_frac[24]) | ex1_hulp_sp)); + + assign ex1_hulp_sp = f_dcd_ex1_sp & f_dcd_ex1_uc_fc_hulp; + + assign ex1_b_frac_pre3_b[0] = (~(sel_b_imm & ex1_b_k_frac[0])); + assign ex1_b_frac_pre3_b[1] = (~(sel_b_imm & ex1_b_k_frac[1])); + + assign ex1_a_frac_pre1_b[0] = (~((sel_a_res0 & ex7_frac_res_ear[0]) | (sel_a_res1 & ex7_frac_a_res_dly[0]))); + assign ex1_a_frac_pre1_b[1] = (~((sel_a_res0 & ex7_frac_res_ear[1]) | (sel_a_res1 & ex7_frac_a_res_dly[1]))); + assign ex1_a_frac_pre1_b[2] = (~((sel_a_res0 & ex7_frac_res_ear[2]) | (sel_a_res1 & ex7_frac_a_res_dly[2]))); + assign ex1_a_frac_pre1_b[3] = (~((sel_a_res0 & ex7_frac_res_ear[3]) | (sel_a_res1 & ex7_frac_a_res_dly[3]))); + assign ex1_a_frac_pre1_b[4] = (~((sel_a_res0 & ex7_frac_res_ear[4]) | (sel_a_res1 & ex7_frac_a_res_dly[4]))); + assign ex1_a_frac_pre1_b[5] = (~((sel_a_res0 & ex7_frac_res_ear[5]) | (sel_a_res1 & ex7_frac_a_res_dly[5]))); + assign ex1_a_frac_pre1_b[6] = (~((sel_a_res0 & ex7_frac_res_ear[6]) | (sel_a_res1 & ex7_frac_a_res_dly[6]))); + assign ex1_a_frac_pre1_b[7] = (~((sel_a_res0 & ex7_frac_res_ear[7]) | (sel_a_res1 & ex7_frac_a_res_dly[7]))); + assign ex1_a_frac_pre1_b[8] = (~((sel_a_res0 & ex7_frac_res_ear[8]) | (sel_a_res1 & ex7_frac_a_res_dly[8]))); + assign ex1_a_frac_pre1_b[9] = (~((sel_a_res0 & ex7_frac_res_ear[9]) | (sel_a_res1 & ex7_frac_a_res_dly[9]))); + assign ex1_a_frac_pre1_b[10] = (~((sel_a_res0 & ex7_frac_res_ear[10]) | (sel_a_res1 & ex7_frac_a_res_dly[10]))); + assign ex1_a_frac_pre1_b[11] = (~((sel_a_res0 & ex7_frac_res_ear[11]) | (sel_a_res1 & ex7_frac_a_res_dly[11]))); + assign ex1_a_frac_pre1_b[12] = (~((sel_a_res0 & ex7_frac_res_ear[12]) | (sel_a_res1 & ex7_frac_a_res_dly[12]))); + assign ex1_a_frac_pre1_b[13] = (~((sel_a_res0 & ex7_frac_res_ear[13]) | (sel_a_res1 & ex7_frac_a_res_dly[13]))); + assign ex1_a_frac_pre1_b[14] = (~((sel_a_res0 & ex7_frac_res_ear[14]) | (sel_a_res1 & ex7_frac_a_res_dly[14]))); + assign ex1_a_frac_pre1_b[15] = (~((sel_a_res0 & ex7_frac_res_ear[15]) | (sel_a_res1 & ex7_frac_a_res_dly[15]))); + assign ex1_a_frac_pre1_b[16] = (~((sel_a_res0 & ex7_frac_res_ear[16]) | (sel_a_res1 & ex7_frac_a_res_dly[16]))); + assign ex1_a_frac_pre1_b[17] = (~((sel_a_res0 & ex7_frac_res_ear[17]) | (sel_a_res1 & ex7_frac_a_res_dly[17]))); + assign ex1_a_frac_pre1_b[18] = (~((sel_a_res0 & ex7_frac_res_ear[18]) | (sel_a_res1 & ex7_frac_a_res_dly[18]))); + assign ex1_a_frac_pre1_b[19] = (~((sel_a_res0 & ex7_frac_res_ear[19]) | (sel_a_res1 & ex7_frac_a_res_dly[19]))); + assign ex1_a_frac_pre1_b[20] = (~((sel_a_res0 & ex7_frac_res_ear[20]) | (sel_a_res1 & ex7_frac_a_res_dly[20]))); + assign ex1_a_frac_pre1_b[21] = (~((sel_a_res0 & ex7_frac_res_ear[21]) | (sel_a_res1 & ex7_frac_a_res_dly[21]))); + assign ex1_a_frac_pre1_b[22] = (~((sel_a_res0 & ex7_frac_res_ear[22]) | (sel_a_res1 & ex7_frac_a_res_dly[22]))); + assign ex1_a_frac_pre1_b[23] = (~((sel_a_res0 & ex7_frac_res_ear[23]) | (sel_a_res1 & ex7_frac_a_res_dly[23]))); + assign ex1_a_frac_pre1_b[24] = (~((sel_a_res0 & ex7_frac_res_ear[24]) | (sel_a_res1 & ex7_frac_a_res_dly[24]))); + assign ex1_a_frac_pre1_b[25] = (~((sel_a_res0 & ex7_frac_res_ear[25]) | (sel_a_res1 & ex7_frac_a_res_dly[25]))); + assign ex1_a_frac_pre1_b[26] = (~((sel_a_res0 & ex7_frac_res_ear[26]) | (sel_a_res1 & ex7_frac_a_res_dly[26]))); + assign ex1_a_frac_pre1_b[27] = (~((sel_a_res0 & ex7_frac_res_ear[27]) | (sel_a_res1 & ex7_frac_a_res_dly[27]))); + assign ex1_a_frac_pre1_b[28] = (~((sel_a_res0 & ex7_frac_res_ear[28]) | (sel_a_res1 & ex7_frac_a_res_dly[28]))); + assign ex1_a_frac_pre1_b[29] = (~((sel_a_res0 & ex7_frac_res_ear[29]) | (sel_a_res1 & ex7_frac_a_res_dly[29]))); + assign ex1_a_frac_pre1_b[30] = (~((sel_a_res0 & ex7_frac_res_ear[30]) | (sel_a_res1 & ex7_frac_a_res_dly[30]))); + assign ex1_a_frac_pre1_b[31] = (~((sel_a_res0 & ex7_frac_res_ear[31]) | (sel_a_res1 & ex7_frac_a_res_dly[31]))); + assign ex1_a_frac_pre1_b[32] = (~((sel_a_res0 & ex7_frac_res_ear[32]) | (sel_a_res1 & ex7_frac_a_res_dly[32]))); + assign ex1_a_frac_pre1_b[33] = (~((sel_a_res0 & ex7_frac_res_ear[33]) | (sel_a_res1 & ex7_frac_a_res_dly[33]))); + assign ex1_a_frac_pre1_b[34] = (~((sel_a_res0 & ex7_frac_res_ear[34]) | (sel_a_res1 & ex7_frac_a_res_dly[34]))); + assign ex1_a_frac_pre1_b[35] = (~((sel_a_res0 & ex7_frac_res_ear[35]) | (sel_a_res1 & ex7_frac_a_res_dly[35]))); + assign ex1_a_frac_pre1_b[36] = (~((sel_a_res0 & ex7_frac_res_ear[36]) | (sel_a_res1 & ex7_frac_a_res_dly[36]))); + assign ex1_a_frac_pre1_b[37] = (~((sel_a_res0 & ex7_frac_res_ear[37]) | (sel_a_res1 & ex7_frac_a_res_dly[37]))); + assign ex1_a_frac_pre1_b[38] = (~((sel_a_res0 & ex7_frac_res_ear[38]) | (sel_a_res1 & ex7_frac_a_res_dly[38]))); + assign ex1_a_frac_pre1_b[39] = (~((sel_a_res0 & ex7_frac_res_ear[39]) | (sel_a_res1 & ex7_frac_a_res_dly[39]))); + assign ex1_a_frac_pre1_b[40] = (~((sel_a_res0 & ex7_frac_res_ear[40]) | (sel_a_res1 & ex7_frac_a_res_dly[40]))); + assign ex1_a_frac_pre1_b[41] = (~((sel_a_res0 & ex7_frac_res_ear[41]) | (sel_a_res1 & ex7_frac_a_res_dly[41]))); + assign ex1_a_frac_pre1_b[42] = (~((sel_a_res0 & ex7_frac_res_ear[42]) | (sel_a_res1 & ex7_frac_a_res_dly[42]))); + assign ex1_a_frac_pre1_b[43] = (~((sel_a_res0 & ex7_frac_res_ear[43]) | (sel_a_res1 & ex7_frac_a_res_dly[43]))); + assign ex1_a_frac_pre1_b[44] = (~((sel_a_res0 & ex7_frac_res_ear[44]) | (sel_a_res1 & ex7_frac_a_res_dly[44]))); + assign ex1_a_frac_pre1_b[45] = (~((sel_a_res0 & ex7_frac_res_ear[45]) | (sel_a_res1 & ex7_frac_a_res_dly[45]))); + assign ex1_a_frac_pre1_b[46] = (~((sel_a_res0 & ex7_frac_res_ear[46]) | (sel_a_res1 & ex7_frac_a_res_dly[46]))); + assign ex1_a_frac_pre1_b[47] = (~((sel_a_res0 & ex7_frac_res_ear[47]) | (sel_a_res1 & ex7_frac_a_res_dly[47]))); + assign ex1_a_frac_pre1_b[48] = (~((sel_a_res0 & ex7_frac_res_ear[48]) | (sel_a_res1 & ex7_frac_a_res_dly[48]))); + assign ex1_a_frac_pre1_b[49] = (~((sel_a_res0 & ex7_frac_res_ear[49]) | (sel_a_res1 & ex7_frac_a_res_dly[49]))); + assign ex1_a_frac_pre1_b[50] = (~((sel_a_res0 & ex7_frac_res_ear[50]) | (sel_a_res1 & ex7_frac_a_res_dly[50]))); + assign ex1_a_frac_pre1_b[51] = (~((sel_a_res0 & ex7_frac_res_ear[51]) | (sel_a_res1 & ex7_frac_a_res_dly[51]))); + assign ex1_a_frac_pre1_b[52] = (~((sel_a_res0 & ex7_frac_res_ear[52]) | (sel_a_res1 & ex7_frac_a_res_dly[52]))); + + assign ex1_c_frac_pre1_b[0] = (~((sel_c_res0 & ex7_frac_res_ear[0]) | (sel_c_res1 & ex7_frac_c_res_dly[0]))); + assign ex1_c_frac_pre1_b[1] = (~((sel_c_res0 & ex7_frac_res_ear[1]) | (sel_c_res1 & ex7_frac_c_res_dly[1]))); + assign ex1_c_frac_pre1_b[2] = (~((sel_c_res0 & ex7_frac_res_ear[2]) | (sel_c_res1 & ex7_frac_c_res_dly[2]))); + assign ex1_c_frac_pre1_b[3] = (~((sel_c_res0 & ex7_frac_res_ear[3]) | (sel_c_res1 & ex7_frac_c_res_dly[3]))); + assign ex1_c_frac_pre1_b[4] = (~((sel_c_res0 & ex7_frac_res_ear[4]) | (sel_c_res1 & ex7_frac_c_res_dly[4]))); + assign ex1_c_frac_pre1_b[5] = (~((sel_c_res0 & ex7_frac_res_ear[5]) | (sel_c_res1 & ex7_frac_c_res_dly[5]))); + assign ex1_c_frac_pre1_b[6] = (~((sel_c_res0 & ex7_frac_res_ear[6]) | (sel_c_res1 & ex7_frac_c_res_dly[6]))); + assign ex1_c_frac_pre1_b[7] = (~((sel_c_res0 & ex7_frac_res_ear[7]) | (sel_c_res1 & ex7_frac_c_res_dly[7]))); + assign ex1_c_frac_pre1_b[8] = (~((sel_c_res0 & ex7_frac_res_ear[8]) | (sel_c_res1 & ex7_frac_c_res_dly[8]))); + assign ex1_c_frac_pre1_b[9] = (~((sel_c_res0 & ex7_frac_res_ear[9]) | (sel_c_res1 & ex7_frac_c_res_dly[9]))); + assign ex1_c_frac_pre1_b[10] = (~((sel_c_res0 & ex7_frac_res_ear[10]) | (sel_c_res1 & ex7_frac_c_res_dly[10]))); + assign ex1_c_frac_pre1_b[11] = (~((sel_c_res0 & ex7_frac_res_ear[11]) | (sel_c_res1 & ex7_frac_c_res_dly[11]))); + assign ex1_c_frac_pre1_b[12] = (~((sel_c_res0 & ex7_frac_res_ear[12]) | (sel_c_res1 & ex7_frac_c_res_dly[12]))); + assign ex1_c_frac_pre1_b[13] = (~((sel_c_res0 & ex7_frac_res_ear[13]) | (sel_c_res1 & ex7_frac_c_res_dly[13]))); + assign ex1_c_frac_pre1_b[14] = (~((sel_c_res0 & ex7_frac_res_ear[14]) | (sel_c_res1 & ex7_frac_c_res_dly[14]))); + assign ex1_c_frac_pre1_b[15] = (~((sel_c_res0 & ex7_frac_res_ear[15]) | (sel_c_res1 & ex7_frac_c_res_dly[15]))); + assign ex1_c_frac_pre1_b[16] = (~((sel_c_res0 & ex7_frac_res_ear[16]) | (sel_c_res1 & ex7_frac_c_res_dly[16]))); + assign ex1_c_frac_pre1_b[17] = (~((sel_c_res0 & ex7_frac_res_ear[17]) | (sel_c_res1 & ex7_frac_c_res_dly[17]))); + assign ex1_c_frac_pre1_b[18] = (~((sel_c_res0 & ex7_frac_res_ear[18]) | (sel_c_res1 & ex7_frac_c_res_dly[18]))); + assign ex1_c_frac_pre1_b[19] = (~((sel_c_res0 & ex7_frac_res_ear[19]) | (sel_c_res1 & ex7_frac_c_res_dly[19]))); + assign ex1_c_frac_pre1_b[20] = (~((sel_c_res0 & ex7_frac_res_ear[20]) | (sel_c_res1 & ex7_frac_c_res_dly[20]))); + assign ex1_c_frac_pre1_b[21] = (~((sel_c_res0 & ex7_frac_res_ear[21]) | (sel_c_res1 & ex7_frac_c_res_dly[21]))); + assign ex1_c_frac_pre1_b[22] = (~((sel_c_res0 & ex7_frac_res_ear[22]) | (sel_c_res1 & ex7_frac_c_res_dly[22]))); + assign ex1_c_frac_pre1_b[23] = (~((sel_c_res0 & ex7_frac_res_ear[23]) | (sel_c_res1 & ex7_frac_c_res_dly[23]))); + assign ex1_c_frac_pre1_b[24] = (~((sel_c_res0 & ex7_frac_res_ear[24]) | (sel_c_res1 & ex7_frac_c_res_dly[24]))); + assign ex1_c_frac_pre1_b[25] = (~((sel_c_res0 & ex7_frac_res_ear[25]) | (sel_c_res1 & ex7_frac_c_res_dly[25]))); + assign ex1_c_frac_pre1_b[26] = (~((sel_c_res0 & ex7_frac_res_ear[26]) | (sel_c_res1 & ex7_frac_c_res_dly[26]))); + assign ex1_c_frac_pre1_b[27] = (~((sel_c_res0 & ex7_frac_res_ear[27]) | (sel_c_res1 & ex7_frac_c_res_dly[27]))); + assign ex1_c_frac_pre1_b[28] = (~((sel_c_res0 & ex7_frac_res_ear[28]) | (sel_c_res1 & ex7_frac_c_res_dly[28]))); + assign ex1_c_frac_pre1_b[29] = (~((sel_c_res0 & ex7_frac_res_ear[29]) | (sel_c_res1 & ex7_frac_c_res_dly[29]))); + assign ex1_c_frac_pre1_b[30] = (~((sel_c_res0 & ex7_frac_res_ear[30]) | (sel_c_res1 & ex7_frac_c_res_dly[30]))); + assign ex1_c_frac_pre1_b[31] = (~((sel_c_res0 & ex7_frac_res_ear[31]) | (sel_c_res1 & ex7_frac_c_res_dly[31]))); + assign ex1_c_frac_pre1_b[32] = (~((sel_c_res0 & ex7_frac_res_ear[32]) | (sel_c_res1 & ex7_frac_c_res_dly[32]))); + assign ex1_c_frac_pre1_b[33] = (~((sel_c_res0 & ex7_frac_res_ear[33]) | (sel_c_res1 & ex7_frac_c_res_dly[33]))); + assign ex1_c_frac_pre1_b[34] = (~((sel_c_res0 & ex7_frac_res_ear[34]) | (sel_c_res1 & ex7_frac_c_res_dly[34]))); + assign ex1_c_frac_pre1_b[35] = (~((sel_c_res0 & ex7_frac_res_ear[35]) | (sel_c_res1 & ex7_frac_c_res_dly[35]))); + assign ex1_c_frac_pre1_b[36] = (~((sel_c_res0 & ex7_frac_res_ear[36]) | (sel_c_res1 & ex7_frac_c_res_dly[36]))); + assign ex1_c_frac_pre1_b[37] = (~((sel_c_res0 & ex7_frac_res_ear[37]) | (sel_c_res1 & ex7_frac_c_res_dly[37]))); + assign ex1_c_frac_pre1_b[38] = (~((sel_c_res0 & ex7_frac_res_ear[38]) | (sel_c_res1 & ex7_frac_c_res_dly[38]))); + assign ex1_c_frac_pre1_b[39] = (~((sel_c_res0 & ex7_frac_res_ear[39]) | (sel_c_res1 & ex7_frac_c_res_dly[39]))); + assign ex1_c_frac_pre1_b[40] = (~((sel_c_res0 & ex7_frac_res_ear[40]) | (sel_c_res1 & ex7_frac_c_res_dly[40]))); + assign ex1_c_frac_pre1_b[41] = (~((sel_c_res0 & ex7_frac_res_ear[41]) | (sel_c_res1 & ex7_frac_c_res_dly[41]))); + assign ex1_c_frac_pre1_b[42] = (~((sel_c_res0 & ex7_frac_res_ear[42]) | (sel_c_res1 & ex7_frac_c_res_dly[42]))); + assign ex1_c_frac_pre1_b[43] = (~((sel_c_res0 & ex7_frac_res_ear[43]) | (sel_c_res1 & ex7_frac_c_res_dly[43]))); + assign ex1_c_frac_pre1_b[44] = (~((sel_c_res0 & ex7_frac_res_ear[44]) | (sel_c_res1 & ex7_frac_c_res_dly[44]))); + assign ex1_c_frac_pre1_b[45] = (~((sel_c_res0 & ex7_frac_res_ear[45]) | (sel_c_res1 & ex7_frac_c_res_dly[45]))); + assign ex1_c_frac_pre1_b[46] = (~((sel_c_res0 & ex7_frac_res_ear[46]) | (sel_c_res1 & ex7_frac_c_res_dly[46]))); + assign ex1_c_frac_pre1_b[47] = (~((sel_c_res0 & ex7_frac_res_ear[47]) | (sel_c_res1 & ex7_frac_c_res_dly[47]))); + assign ex1_c_frac_pre1_b[48] = (~((sel_c_res0 & ex7_frac_res_ear[48]) | (sel_c_res1 & ex7_frac_c_res_dly[48]))); + assign ex1_c_frac_pre1_b[49] = (~((sel_c_res0 & ex7_frac_res_ear[49]) | (sel_c_res1 & ex7_frac_c_res_dly[49]))); + assign ex1_c_frac_pre1_b[50] = (~((sel_c_res0 & ex7_frac_res_ear[50]) | (sel_c_res1 & ex7_frac_c_res_dly[50]))); + assign ex1_c_frac_pre1_b[51] = (~((sel_c_res0 & ex7_frac_res_ear[51]) | (sel_c_res1 & ex7_frac_c_res_dly[51]))); + assign ex1_c_frac_pre1_b[52] = (~((sel_c_res0 & ex7_frac_res_ear[52]) | (sel_c_res1 & ex7_frac_c_res_dly[52]))); + + assign ex1_b_frac_pre1_b[0] = (~((sel_b_res0 & ex7_frac_res_ear[0]) | (sel_b_res1 & ex7_frac_b_res_dly[0]))); + assign ex1_b_frac_pre1_b[1] = (~((sel_b_res0 & ex7_frac_res_ear[1]) | (sel_b_res1 & ex7_frac_b_res_dly[1]))); + assign ex1_b_frac_pre1_b[2] = (~((sel_b_res0 & ex7_frac_res_ear[2]) | (sel_b_res1 & ex7_frac_b_res_dly[2]))); + assign ex1_b_frac_pre1_b[3] = (~((sel_b_res0 & ex7_frac_res_ear[3]) | (sel_b_res1 & ex7_frac_b_res_dly[3]))); + assign ex1_b_frac_pre1_b[4] = (~((sel_b_res0 & ex7_frac_res_ear[4]) | (sel_b_res1 & ex7_frac_b_res_dly[4]))); + assign ex1_b_frac_pre1_b[5] = (~((sel_b_res0 & ex7_frac_res_ear[5]) | (sel_b_res1 & ex7_frac_b_res_dly[5]))); + assign ex1_b_frac_pre1_b[6] = (~((sel_b_res0 & ex7_frac_res_ear[6]) | (sel_b_res1 & ex7_frac_b_res_dly[6]))); + assign ex1_b_frac_pre1_b[7] = (~((sel_b_res0 & ex7_frac_res_ear[7]) | (sel_b_res1 & ex7_frac_b_res_dly[7]))); + assign ex1_b_frac_pre1_b[8] = (~((sel_b_res0 & ex7_frac_res_ear[8]) | (sel_b_res1 & ex7_frac_b_res_dly[8]))); + assign ex1_b_frac_pre1_b[9] = (~((sel_b_res0 & ex7_frac_res_ear[9]) | (sel_b_res1 & ex7_frac_b_res_dly[9]))); + assign ex1_b_frac_pre1_b[10] = (~((sel_b_res0 & ex7_frac_res_ear[10]) | (sel_b_res1 & ex7_frac_b_res_dly[10]))); + assign ex1_b_frac_pre1_b[11] = (~((sel_b_res0 & ex7_frac_res_ear[11]) | (sel_b_res1 & ex7_frac_b_res_dly[11]))); + assign ex1_b_frac_pre1_b[12] = (~((sel_b_res0 & ex7_frac_res_ear[12]) | (sel_b_res1 & ex7_frac_b_res_dly[12]))); + assign ex1_b_frac_pre1_b[13] = (~((sel_b_res0 & ex7_frac_res_ear[13]) | (sel_b_res1 & ex7_frac_b_res_dly[13]))); + assign ex1_b_frac_pre1_b[14] = (~((sel_b_res0 & ex7_frac_res_ear[14]) | (sel_b_res1 & ex7_frac_b_res_dly[14]))); + assign ex1_b_frac_pre1_b[15] = (~((sel_b_res0 & ex7_frac_res_ear[15]) | (sel_b_res1 & ex7_frac_b_res_dly[15]))); + assign ex1_b_frac_pre1_b[16] = (~((sel_b_res0 & ex7_frac_res_ear[16]) | (sel_b_res1 & ex7_frac_b_res_dly[16]))); + assign ex1_b_frac_pre1_b[17] = (~((sel_b_res0 & ex7_frac_res_ear[17]) | (sel_b_res1 & ex7_frac_b_res_dly[17]))); + assign ex1_b_frac_pre1_b[18] = (~((sel_b_res0 & ex7_frac_res_ear[18]) | (sel_b_res1 & ex7_frac_b_res_dly[18]))); + assign ex1_b_frac_pre1_b[19] = (~((sel_b_res0 & ex7_frac_res_ear[19]) | (sel_b_res1 & ex7_frac_b_res_dly[19]))); + assign ex1_b_frac_pre1_b[20] = (~((sel_b_res0 & ex7_frac_res_ear[20]) | (sel_b_res1 & ex7_frac_b_res_dly[20]))); + assign ex1_b_frac_pre1_b[21] = (~((sel_b_res0 & ex7_frac_res_ear[21]) | (sel_b_res1 & ex7_frac_b_res_dly[21]))); + assign ex1_b_frac_pre1_b[22] = (~((sel_b_res0 & ex7_frac_res_ear[22]) | (sel_b_res1 & ex7_frac_b_res_dly[22]))); + assign ex1_b_frac_pre1_b[23] = (~((sel_b_res0 & ex7_frac_res_ear[23]) | (sel_b_res1 & ex7_frac_b_res_dly[23]))); + assign ex1_b_frac_pre1_b[24] = (~((sel_b_res0 & ex7_frac_res_ear[24]) | (sel_b_res1 & ex7_frac_b_res_dly[24]))); + assign ex1_b_frac_pre1_b[25] = (~((sel_b_res0 & ex7_frac_res_ear[25]) | (sel_b_res1 & ex7_frac_b_res_dly[25]))); + assign ex1_b_frac_pre1_b[26] = (~((sel_b_res0 & ex7_frac_res_ear[26]) | (sel_b_res1 & ex7_frac_b_res_dly[26]))); + assign ex1_b_frac_pre1_b[27] = (~((sel_b_res0 & ex7_frac_res_ear[27]) | (sel_b_res1 & ex7_frac_b_res_dly[27]))); + assign ex1_b_frac_pre1_b[28] = (~((sel_b_res0 & ex7_frac_res_ear[28]) | (sel_b_res1 & ex7_frac_b_res_dly[28]))); + assign ex1_b_frac_pre1_b[29] = (~((sel_b_res0 & ex7_frac_res_ear[29]) | (sel_b_res1 & ex7_frac_b_res_dly[29]))); + assign ex1_b_frac_pre1_b[30] = (~((sel_b_res0 & ex7_frac_res_ear[30]) | (sel_b_res1 & ex7_frac_b_res_dly[30]))); + assign ex1_b_frac_pre1_b[31] = (~((sel_b_res0 & ex7_frac_res_ear[31]) | (sel_b_res1 & ex7_frac_b_res_dly[31]))); + assign ex1_b_frac_pre1_b[32] = (~((sel_b_res0 & ex7_frac_res_ear[32]) | (sel_b_res1 & ex7_frac_b_res_dly[32]))); + assign ex1_b_frac_pre1_b[33] = (~((sel_b_res0 & ex7_frac_res_ear[33]) | (sel_b_res1 & ex7_frac_b_res_dly[33]))); + assign ex1_b_frac_pre1_b[34] = (~((sel_b_res0 & ex7_frac_res_ear[34]) | (sel_b_res1 & ex7_frac_b_res_dly[34]))); + assign ex1_b_frac_pre1_b[35] = (~((sel_b_res0 & ex7_frac_res_ear[35]) | (sel_b_res1 & ex7_frac_b_res_dly[35]))); + assign ex1_b_frac_pre1_b[36] = (~((sel_b_res0 & ex7_frac_res_ear[36]) | (sel_b_res1 & ex7_frac_b_res_dly[36]))); + assign ex1_b_frac_pre1_b[37] = (~((sel_b_res0 & ex7_frac_res_ear[37]) | (sel_b_res1 & ex7_frac_b_res_dly[37]))); + assign ex1_b_frac_pre1_b[38] = (~((sel_b_res0 & ex7_frac_res_ear[38]) | (sel_b_res1 & ex7_frac_b_res_dly[38]))); + assign ex1_b_frac_pre1_b[39] = (~((sel_b_res0 & ex7_frac_res_ear[39]) | (sel_b_res1 & ex7_frac_b_res_dly[39]))); + assign ex1_b_frac_pre1_b[40] = (~((sel_b_res0 & ex7_frac_res_ear[40]) | (sel_b_res1 & ex7_frac_b_res_dly[40]))); + assign ex1_b_frac_pre1_b[41] = (~((sel_b_res0 & ex7_frac_res_ear[41]) | (sel_b_res1 & ex7_frac_b_res_dly[41]))); + assign ex1_b_frac_pre1_b[42] = (~((sel_b_res0 & ex7_frac_res_ear[42]) | (sel_b_res1 & ex7_frac_b_res_dly[42]))); + assign ex1_b_frac_pre1_b[43] = (~((sel_b_res0 & ex7_frac_res_ear[43]) | (sel_b_res1 & ex7_frac_b_res_dly[43]))); + assign ex1_b_frac_pre1_b[44] = (~((sel_b_res0 & ex7_frac_res_ear[44]) | (sel_b_res1 & ex7_frac_b_res_dly[44]))); + assign ex1_b_frac_pre1_b[45] = (~((sel_b_res0 & ex7_frac_res_ear[45]) | (sel_b_res1 & ex7_frac_b_res_dly[45]))); + assign ex1_b_frac_pre1_b[46] = (~((sel_b_res0 & ex7_frac_res_ear[46]) | (sel_b_res1 & ex7_frac_b_res_dly[46]))); + assign ex1_b_frac_pre1_b[47] = (~((sel_b_res0 & ex7_frac_res_ear[47]) | (sel_b_res1 & ex7_frac_b_res_dly[47]))); + assign ex1_b_frac_pre1_b[48] = (~((sel_b_res0 & ex7_frac_res_ear[48]) | (sel_b_res1 & ex7_frac_b_res_dly[48]))); + assign ex1_b_frac_pre1_b[49] = (~((sel_b_res0 & ex7_frac_res_ear[49]) | (sel_b_res1 & ex7_frac_b_res_dly[49]))); + assign ex1_b_frac_pre1_b[50] = (~((sel_b_res0 & ex7_frac_res_ear[50]) | (sel_b_res1 & ex7_frac_b_res_dly[50]))); + assign ex1_b_frac_pre1_b[51] = (~((sel_b_res0 & ex7_frac_res_ear[51]) | (sel_b_res1 & ex7_frac_b_res_dly[51]))); + assign ex1_b_frac_pre1_b[52] = (~((sel_b_res0 & ex7_frac_res_ear[52]) | (sel_b_res1 & ex7_frac_b_res_dly[52]))); + + assign ex1_s_frac_pre1_b[0] = (~((sel_s_res0 & ex7_frac_res_ear[0]) | (sel_s_res1 & ex7_frac_s_res_dly[0]))); + assign ex1_s_frac_pre1_b[1] = (~((sel_s_res0 & ex7_frac_res_ear[1]) | (sel_s_res1 & ex7_frac_s_res_dly[1]))); + assign ex1_s_frac_pre1_b[2] = (~((sel_s_res0 & ex7_frac_res_ear[2]) | (sel_s_res1 & ex7_frac_s_res_dly[2]))); + assign ex1_s_frac_pre1_b[3] = (~((sel_s_res0 & ex7_frac_res_ear[3]) | (sel_s_res1 & ex7_frac_s_res_dly[3]))); + assign ex1_s_frac_pre1_b[4] = (~((sel_s_res0 & ex7_frac_res_ear[4]) | (sel_s_res1 & ex7_frac_s_res_dly[4]))); + assign ex1_s_frac_pre1_b[5] = (~((sel_s_res0 & ex7_frac_res_ear[5]) | (sel_s_res1 & ex7_frac_s_res_dly[5]))); + assign ex1_s_frac_pre1_b[6] = (~((sel_s_res0 & ex7_frac_res_ear[6]) | (sel_s_res1 & ex7_frac_s_res_dly[6]))); + assign ex1_s_frac_pre1_b[7] = (~((sel_s_res0 & ex7_frac_res_ear[7]) | (sel_s_res1 & ex7_frac_s_res_dly[7]))); + assign ex1_s_frac_pre1_b[8] = (~((sel_s_res0 & ex7_frac_res_ear[8]) | (sel_s_res1 & ex7_frac_s_res_dly[8]))); + assign ex1_s_frac_pre1_b[9] = (~((sel_s_res0 & ex7_frac_res_ear[9]) | (sel_s_res1 & ex7_frac_s_res_dly[9]))); + assign ex1_s_frac_pre1_b[10] = (~((sel_s_res0 & ex7_frac_res_ear[10]) | (sel_s_res1 & ex7_frac_s_res_dly[10]))); + assign ex1_s_frac_pre1_b[11] = (~((sel_s_res0 & ex7_frac_res_ear[11]) | (sel_s_res1 & ex7_frac_s_res_dly[11]))); + assign ex1_s_frac_pre1_b[12] = (~((sel_s_res0 & ex7_frac_res_ear[12]) | (sel_s_res1 & ex7_frac_s_res_dly[12]))); + assign ex1_s_frac_pre1_b[13] = (~((sel_s_res0 & ex7_frac_res_ear[13]) | (sel_s_res1 & ex7_frac_s_res_dly[13]))); + assign ex1_s_frac_pre1_b[14] = (~((sel_s_res0 & ex7_frac_res_ear[14]) | (sel_s_res1 & ex7_frac_s_res_dly[14]))); + assign ex1_s_frac_pre1_b[15] = (~((sel_s_res0 & ex7_frac_res_ear[15]) | (sel_s_res1 & ex7_frac_s_res_dly[15]))); + assign ex1_s_frac_pre1_b[16] = (~((sel_s_res0 & ex7_frac_res_ear[16]) | (sel_s_res1 & ex7_frac_s_res_dly[16]))); + assign ex1_s_frac_pre1_b[17] = (~((sel_s_res0 & ex7_frac_res_ear[17]) | (sel_s_res1 & ex7_frac_s_res_dly[17]))); + assign ex1_s_frac_pre1_b[18] = (~((sel_s_res0 & ex7_frac_res_ear[18]) | (sel_s_res1 & ex7_frac_s_res_dly[18]))); + assign ex1_s_frac_pre1_b[19] = (~((sel_s_res0 & ex7_frac_res_ear[19]) | (sel_s_res1 & ex7_frac_s_res_dly[19]))); + assign ex1_s_frac_pre1_b[20] = (~((sel_s_res0 & ex7_frac_res_ear[20]) | (sel_s_res1 & ex7_frac_s_res_dly[20]))); + assign ex1_s_frac_pre1_b[21] = (~((sel_s_res0 & ex7_frac_res_ear[21]) | (sel_s_res1 & ex7_frac_s_res_dly[21]))); + assign ex1_s_frac_pre1_b[22] = (~((sel_s_res0 & ex7_frac_res_ear[22]) | (sel_s_res1 & ex7_frac_s_res_dly[22]))); + assign ex1_s_frac_pre1_b[23] = (~((sel_s_res0 & ex7_frac_res_ear[23]) | (sel_s_res1 & ex7_frac_s_res_dly[23]))); + assign ex1_s_frac_pre1_b[24] = (~((sel_s_res0 & ex7_frac_res_ear[24]) | (sel_s_res1 & ex7_frac_s_res_dly[24]))); + assign ex1_s_frac_pre1_b[25] = (~((sel_s_res0 & ex7_frac_res_ear[25]) | (sel_s_res1 & ex7_frac_s_res_dly[25]))); + assign ex1_s_frac_pre1_b[26] = (~((sel_s_res0 & ex7_frac_res_ear[26]) | (sel_s_res1 & ex7_frac_s_res_dly[26]))); + assign ex1_s_frac_pre1_b[27] = (~((sel_s_res0 & ex7_frac_res_ear[27]) | (sel_s_res1 & ex7_frac_s_res_dly[27]))); + assign ex1_s_frac_pre1_b[28] = (~((sel_s_res0 & ex7_frac_res_ear[28]) | (sel_s_res1 & ex7_frac_s_res_dly[28]))); + assign ex1_s_frac_pre1_b[29] = (~((sel_s_res0 & ex7_frac_res_ear[29]) | (sel_s_res1 & ex7_frac_s_res_dly[29]))); + assign ex1_s_frac_pre1_b[30] = (~((sel_s_res0 & ex7_frac_res_ear[30]) | (sel_s_res1 & ex7_frac_s_res_dly[30]))); + assign ex1_s_frac_pre1_b[31] = (~((sel_s_res0 & ex7_frac_res_ear[31]) | (sel_s_res1 & ex7_frac_s_res_dly[31]))); + assign ex1_s_frac_pre1_b[32] = (~((sel_s_res0 & ex7_frac_res_ear[32]) | (sel_s_res1 & ex7_frac_s_res_dly[32]))); + assign ex1_s_frac_pre1_b[33] = (~((sel_s_res0 & ex7_frac_res_ear[33]) | (sel_s_res1 & ex7_frac_s_res_dly[33]))); + assign ex1_s_frac_pre1_b[34] = (~((sel_s_res0 & ex7_frac_res_ear[34]) | (sel_s_res1 & ex7_frac_s_res_dly[34]))); + assign ex1_s_frac_pre1_b[35] = (~((sel_s_res0 & ex7_frac_res_ear[35]) | (sel_s_res1 & ex7_frac_s_res_dly[35]))); + assign ex1_s_frac_pre1_b[36] = (~((sel_s_res0 & ex7_frac_res_ear[36]) | (sel_s_res1 & ex7_frac_s_res_dly[36]))); + assign ex1_s_frac_pre1_b[37] = (~((sel_s_res0 & ex7_frac_res_ear[37]) | (sel_s_res1 & ex7_frac_s_res_dly[37]))); + assign ex1_s_frac_pre1_b[38] = (~((sel_s_res0 & ex7_frac_res_ear[38]) | (sel_s_res1 & ex7_frac_s_res_dly[38]))); + assign ex1_s_frac_pre1_b[39] = (~((sel_s_res0 & ex7_frac_res_ear[39]) | (sel_s_res1 & ex7_frac_s_res_dly[39]))); + assign ex1_s_frac_pre1_b[40] = (~((sel_s_res0 & ex7_frac_res_ear[40]) | (sel_s_res1 & ex7_frac_s_res_dly[40]))); + assign ex1_s_frac_pre1_b[41] = (~((sel_s_res0 & ex7_frac_res_ear[41]) | (sel_s_res1 & ex7_frac_s_res_dly[41]))); + assign ex1_s_frac_pre1_b[42] = (~((sel_s_res0 & ex7_frac_res_ear[42]) | (sel_s_res1 & ex7_frac_s_res_dly[42]))); + assign ex1_s_frac_pre1_b[43] = (~((sel_s_res0 & ex7_frac_res_ear[43]) | (sel_s_res1 & ex7_frac_s_res_dly[43]))); + assign ex1_s_frac_pre1_b[44] = (~((sel_s_res0 & ex7_frac_res_ear[44]) | (sel_s_res1 & ex7_frac_s_res_dly[44]))); + assign ex1_s_frac_pre1_b[45] = (~((sel_s_res0 & ex7_frac_res_ear[45]) | (sel_s_res1 & ex7_frac_s_res_dly[45]))); + assign ex1_s_frac_pre1_b[46] = (~((sel_s_res0 & ex7_frac_res_ear[46]) | (sel_s_res1 & ex7_frac_s_res_dly[46]))); + assign ex1_s_frac_pre1_b[47] = (~((sel_s_res0 & ex7_frac_res_ear[47]) | (sel_s_res1 & ex7_frac_s_res_dly[47]))); + assign ex1_s_frac_pre1_b[48] = (~((sel_s_res0 & ex7_frac_res_ear[48]) | (sel_s_res1 & ex7_frac_s_res_dly[48]))); + assign ex1_s_frac_pre1_b[49] = (~((sel_s_res0 & ex7_frac_res_ear[49]) | (sel_s_res1 & ex7_frac_s_res_dly[49]))); + assign ex1_s_frac_pre1_b[50] = (~((sel_s_res0 & ex7_frac_res_ear[50]) | (sel_s_res1 & ex7_frac_s_res_dly[50]))); + assign ex1_s_frac_pre1_b[51] = (~((sel_s_res0 & ex7_frac_res_ear[51]) | (sel_s_res1 & ex7_frac_s_res_dly[51]))); + assign ex1_s_frac_pre1_b[52] = (~((sel_s_res0 & ex7_frac_res_ear[52]) | (sel_s_res1 & ex7_frac_s_res_dly[52]))); + + assign ex1_a_frac_pre2_b[0] = (~((sel_a_load0 & ex6_frac_lod_ear[0]) | (sel_a_reload0 & ex6_frac_relod_ear[0]) | (sel_a_load1 & ex7_frac_a_lod_dly[0]))); + assign ex1_a_frac_pre2_b[1] = (~((sel_a_load0 & ex6_frac_lod_ear[1]) | (sel_a_reload0 & ex6_frac_relod_ear[1]) | (sel_a_load1 & ex7_frac_a_lod_dly[1]))); + assign ex1_a_frac_pre2_b[2] = (~((sel_a_load0 & ex6_frac_lod_ear[2]) | (sel_a_reload0 & ex6_frac_relod_ear[2]) | (sel_a_load1 & ex7_frac_a_lod_dly[2]))); + assign ex1_a_frac_pre2_b[3] = (~((sel_a_load0 & ex6_frac_lod_ear[3]) | (sel_a_reload0 & ex6_frac_relod_ear[3]) | (sel_a_load1 & ex7_frac_a_lod_dly[3]))); + assign ex1_a_frac_pre2_b[4] = (~((sel_a_load0 & ex6_frac_lod_ear[4]) | (sel_a_reload0 & ex6_frac_relod_ear[4]) | (sel_a_load1 & ex7_frac_a_lod_dly[4]))); + assign ex1_a_frac_pre2_b[5] = (~((sel_a_load0 & ex6_frac_lod_ear[5]) | (sel_a_reload0 & ex6_frac_relod_ear[5]) | (sel_a_load1 & ex7_frac_a_lod_dly[5]))); + assign ex1_a_frac_pre2_b[6] = (~((sel_a_load0 & ex6_frac_lod_ear[6]) | (sel_a_reload0 & ex6_frac_relod_ear[6]) | (sel_a_load1 & ex7_frac_a_lod_dly[6]))); + assign ex1_a_frac_pre2_b[7] = (~((sel_a_load0 & ex6_frac_lod_ear[7]) | (sel_a_reload0 & ex6_frac_relod_ear[7]) | (sel_a_load1 & ex7_frac_a_lod_dly[7]))); + assign ex1_a_frac_pre2_b[8] = (~((sel_a_load0 & ex6_frac_lod_ear[8]) | (sel_a_reload0 & ex6_frac_relod_ear[8]) | (sel_a_load1 & ex7_frac_a_lod_dly[8]))); + assign ex1_a_frac_pre2_b[9] = (~((sel_a_load0 & ex6_frac_lod_ear[9]) | (sel_a_reload0 & ex6_frac_relod_ear[9]) | (sel_a_load1 & ex7_frac_a_lod_dly[9]))); + assign ex1_a_frac_pre2_b[10] = (~((sel_a_load0 & ex6_frac_lod_ear[10]) | (sel_a_reload0 & ex6_frac_relod_ear[10]) | (sel_a_load1 & ex7_frac_a_lod_dly[10]))); + assign ex1_a_frac_pre2_b[11] = (~((sel_a_load0 & ex6_frac_lod_ear[11]) | (sel_a_reload0 & ex6_frac_relod_ear[11]) | (sel_a_load1 & ex7_frac_a_lod_dly[11]))); + assign ex1_a_frac_pre2_b[12] = (~((sel_a_load0 & ex6_frac_lod_ear[12]) | (sel_a_reload0 & ex6_frac_relod_ear[12]) | (sel_a_load1 & ex7_frac_a_lod_dly[12]))); + assign ex1_a_frac_pre2_b[13] = (~((sel_a_load0 & ex6_frac_lod_ear[13]) | (sel_a_reload0 & ex6_frac_relod_ear[13]) | (sel_a_load1 & ex7_frac_a_lod_dly[13]))); + assign ex1_a_frac_pre2_b[14] = (~((sel_a_load0 & ex6_frac_lod_ear[14]) | (sel_a_reload0 & ex6_frac_relod_ear[14]) | (sel_a_load1 & ex7_frac_a_lod_dly[14]))); + assign ex1_a_frac_pre2_b[15] = (~((sel_a_load0 & ex6_frac_lod_ear[15]) | (sel_a_reload0 & ex6_frac_relod_ear[15]) | (sel_a_load1 & ex7_frac_a_lod_dly[15]))); + assign ex1_a_frac_pre2_b[16] = (~((sel_a_load0 & ex6_frac_lod_ear[16]) | (sel_a_reload0 & ex6_frac_relod_ear[16]) | (sel_a_load1 & ex7_frac_a_lod_dly[16]))); + assign ex1_a_frac_pre2_b[17] = (~((sel_a_load0 & ex6_frac_lod_ear[17]) | (sel_a_reload0 & ex6_frac_relod_ear[17]) | (sel_a_load1 & ex7_frac_a_lod_dly[17]))); + assign ex1_a_frac_pre2_b[18] = (~((sel_a_load0 & ex6_frac_lod_ear[18]) | (sel_a_reload0 & ex6_frac_relod_ear[18]) | (sel_a_load1 & ex7_frac_a_lod_dly[18]))); + assign ex1_a_frac_pre2_b[19] = (~((sel_a_load0 & ex6_frac_lod_ear[19]) | (sel_a_reload0 & ex6_frac_relod_ear[19]) | (sel_a_load1 & ex7_frac_a_lod_dly[19]))); + assign ex1_a_frac_pre2_b[20] = (~((sel_a_load0 & ex6_frac_lod_ear[20]) | (sel_a_reload0 & ex6_frac_relod_ear[20]) | (sel_a_load1 & ex7_frac_a_lod_dly[20]))); + assign ex1_a_frac_pre2_b[21] = (~((sel_a_load0 & ex6_frac_lod_ear[21]) | (sel_a_reload0 & ex6_frac_relod_ear[21]) | (sel_a_load1 & ex7_frac_a_lod_dly[21]))); + assign ex1_a_frac_pre2_b[22] = (~((sel_a_load0 & ex6_frac_lod_ear[22]) | (sel_a_reload0 & ex6_frac_relod_ear[22]) | (sel_a_load1 & ex7_frac_a_lod_dly[22]))); + assign ex1_a_frac_pre2_b[23] = (~((sel_a_load0 & ex6_frac_lod_ear[23]) | (sel_a_reload0 & ex6_frac_relod_ear[23]) | (sel_a_load1 & ex7_frac_a_lod_dly[23]))); + assign ex1_a_frac_pre2_b[24] = (~((sel_a_load0 & ex6_frac_lod_ear[24]) | (sel_a_reload0 & ex6_frac_relod_ear[24]) | (sel_a_load1 & ex7_frac_a_lod_dly[24]))); + assign ex1_a_frac_pre2_b[25] = (~((sel_a_load0 & ex6_frac_lod_ear[25]) | (sel_a_reload0 & ex6_frac_relod_ear[25]) | (sel_a_load1 & ex7_frac_a_lod_dly[25]))); + assign ex1_a_frac_pre2_b[26] = (~((sel_a_load0 & ex6_frac_lod_ear[26]) | (sel_a_reload0 & ex6_frac_relod_ear[26]) | (sel_a_load1 & ex7_frac_a_lod_dly[26]))); + assign ex1_a_frac_pre2_b[27] = (~((sel_a_load0 & ex6_frac_lod_ear[27]) | (sel_a_reload0 & ex6_frac_relod_ear[27]) | (sel_a_load1 & ex7_frac_a_lod_dly[27]))); + assign ex1_a_frac_pre2_b[28] = (~((sel_a_load0 & ex6_frac_lod_ear[28]) | (sel_a_reload0 & ex6_frac_relod_ear[28]) | (sel_a_load1 & ex7_frac_a_lod_dly[28]))); + assign ex1_a_frac_pre2_b[29] = (~((sel_a_load0 & ex6_frac_lod_ear[29]) | (sel_a_reload0 & ex6_frac_relod_ear[29]) | (sel_a_load1 & ex7_frac_a_lod_dly[29]))); + assign ex1_a_frac_pre2_b[30] = (~((sel_a_load0 & ex6_frac_lod_ear[30]) | (sel_a_reload0 & ex6_frac_relod_ear[30]) | (sel_a_load1 & ex7_frac_a_lod_dly[30]))); + assign ex1_a_frac_pre2_b[31] = (~((sel_a_load0 & ex6_frac_lod_ear[31]) | (sel_a_reload0 & ex6_frac_relod_ear[31]) | (sel_a_load1 & ex7_frac_a_lod_dly[31]))); + assign ex1_a_frac_pre2_b[32] = (~((sel_a_load0 & ex6_frac_lod_ear[32]) | (sel_a_reload0 & ex6_frac_relod_ear[32]) | (sel_a_load1 & ex7_frac_a_lod_dly[32]))); + assign ex1_a_frac_pre2_b[33] = (~((sel_a_load0 & ex6_frac_lod_ear[33]) | (sel_a_reload0 & ex6_frac_relod_ear[33]) | (sel_a_load1 & ex7_frac_a_lod_dly[33]))); + assign ex1_a_frac_pre2_b[34] = (~((sel_a_load0 & ex6_frac_lod_ear[34]) | (sel_a_reload0 & ex6_frac_relod_ear[34]) | (sel_a_load1 & ex7_frac_a_lod_dly[34]))); + assign ex1_a_frac_pre2_b[35] = (~((sel_a_load0 & ex6_frac_lod_ear[35]) | (sel_a_reload0 & ex6_frac_relod_ear[35]) | (sel_a_load1 & ex7_frac_a_lod_dly[35]))); + assign ex1_a_frac_pre2_b[36] = (~((sel_a_load0 & ex6_frac_lod_ear[36]) | (sel_a_reload0 & ex6_frac_relod_ear[36]) | (sel_a_load1 & ex7_frac_a_lod_dly[36]))); + assign ex1_a_frac_pre2_b[37] = (~((sel_a_load0 & ex6_frac_lod_ear[37]) | (sel_a_reload0 & ex6_frac_relod_ear[37]) | (sel_a_load1 & ex7_frac_a_lod_dly[37]))); + assign ex1_a_frac_pre2_b[38] = (~((sel_a_load0 & ex6_frac_lod_ear[38]) | (sel_a_reload0 & ex6_frac_relod_ear[38]) | (sel_a_load1 & ex7_frac_a_lod_dly[38]))); + assign ex1_a_frac_pre2_b[39] = (~((sel_a_load0 & ex6_frac_lod_ear[39]) | (sel_a_reload0 & ex6_frac_relod_ear[39]) | (sel_a_load1 & ex7_frac_a_lod_dly[39]))); + assign ex1_a_frac_pre2_b[40] = (~((sel_a_load0 & ex6_frac_lod_ear[40]) | (sel_a_reload0 & ex6_frac_relod_ear[40]) | (sel_a_load1 & ex7_frac_a_lod_dly[40]))); + assign ex1_a_frac_pre2_b[41] = (~((sel_a_load0 & ex6_frac_lod_ear[41]) | (sel_a_reload0 & ex6_frac_relod_ear[41]) | (sel_a_load1 & ex7_frac_a_lod_dly[41]))); + assign ex1_a_frac_pre2_b[42] = (~((sel_a_load0 & ex6_frac_lod_ear[42]) | (sel_a_reload0 & ex6_frac_relod_ear[42]) | (sel_a_load1 & ex7_frac_a_lod_dly[42]))); + assign ex1_a_frac_pre2_b[43] = (~((sel_a_load0 & ex6_frac_lod_ear[43]) | (sel_a_reload0 & ex6_frac_relod_ear[43]) | (sel_a_load1 & ex7_frac_a_lod_dly[43]))); + assign ex1_a_frac_pre2_b[44] = (~((sel_a_load0 & ex6_frac_lod_ear[44]) | (sel_a_reload0 & ex6_frac_relod_ear[44]) | (sel_a_load1 & ex7_frac_a_lod_dly[44]))); + assign ex1_a_frac_pre2_b[45] = (~((sel_a_load0 & ex6_frac_lod_ear[45]) | (sel_a_reload0 & ex6_frac_relod_ear[45]) | (sel_a_load1 & ex7_frac_a_lod_dly[45]))); + assign ex1_a_frac_pre2_b[46] = (~((sel_a_load0 & ex6_frac_lod_ear[46]) | (sel_a_reload0 & ex6_frac_relod_ear[46]) | (sel_a_load1 & ex7_frac_a_lod_dly[46]))); + assign ex1_a_frac_pre2_b[47] = (~((sel_a_load0 & ex6_frac_lod_ear[47]) | (sel_a_reload0 & ex6_frac_relod_ear[47]) | (sel_a_load1 & ex7_frac_a_lod_dly[47]))); + assign ex1_a_frac_pre2_b[48] = (~((sel_a_load0 & ex6_frac_lod_ear[48]) | (sel_a_reload0 & ex6_frac_relod_ear[48]) | (sel_a_load1 & ex7_frac_a_lod_dly[48]))); + assign ex1_a_frac_pre2_b[49] = (~((sel_a_load0 & ex6_frac_lod_ear[49]) | (sel_a_reload0 & ex6_frac_relod_ear[49]) | (sel_a_load1 & ex7_frac_a_lod_dly[49]))); + assign ex1_a_frac_pre2_b[50] = (~((sel_a_load0 & ex6_frac_lod_ear[50]) | (sel_a_reload0 & ex6_frac_relod_ear[50]) | (sel_a_load1 & ex7_frac_a_lod_dly[50]))); + assign ex1_a_frac_pre2_b[51] = (~((sel_a_load0 & ex6_frac_lod_ear[51]) | (sel_a_reload0 & ex6_frac_relod_ear[51]) | (sel_a_load1 & ex7_frac_a_lod_dly[51]))); + assign ex1_a_frac_pre2_b[52] = (~((sel_a_load0 & ex6_frac_lod_ear[52]) | (sel_a_reload0 & ex6_frac_relod_ear[52]) | (sel_a_load1 & ex7_frac_a_lod_dly[52]))); + + assign ex1_c_frac_pre2_b[0] = (~((sel_c_load0 & ex6_frac_lod_ear[0]) | (sel_c_reload0 & ex6_frac_relod_ear[0]) | (sel_c_load1 & ex7_frac_c_lod_dly[0]))); + assign ex1_c_frac_pre2_b[1] = (~((sel_c_load0 & ex6_frac_lod_ear[1]) | (sel_c_reload0 & ex6_frac_relod_ear[1]) | (sel_c_load1 & ex7_frac_c_lod_dly[1]))); + assign ex1_c_frac_pre2_b[2] = (~((sel_c_load0 & ex6_frac_lod_ear[2]) | (sel_c_reload0 & ex6_frac_relod_ear[2]) | (sel_c_load1 & ex7_frac_c_lod_dly[2]))); + assign ex1_c_frac_pre2_b[3] = (~((sel_c_load0 & ex6_frac_lod_ear[3]) | (sel_c_reload0 & ex6_frac_relod_ear[3]) | (sel_c_load1 & ex7_frac_c_lod_dly[3]))); + assign ex1_c_frac_pre2_b[4] = (~((sel_c_load0 & ex6_frac_lod_ear[4]) | (sel_c_reload0 & ex6_frac_relod_ear[4]) | (sel_c_load1 & ex7_frac_c_lod_dly[4]))); + assign ex1_c_frac_pre2_b[5] = (~((sel_c_load0 & ex6_frac_lod_ear[5]) | (sel_c_reload0 & ex6_frac_relod_ear[5]) | (sel_c_load1 & ex7_frac_c_lod_dly[5]))); + assign ex1_c_frac_pre2_b[6] = (~((sel_c_load0 & ex6_frac_lod_ear[6]) | (sel_c_reload0 & ex6_frac_relod_ear[6]) | (sel_c_load1 & ex7_frac_c_lod_dly[6]))); + assign ex1_c_frac_pre2_b[7] = (~((sel_c_load0 & ex6_frac_lod_ear[7]) | (sel_c_reload0 & ex6_frac_relod_ear[7]) | (sel_c_load1 & ex7_frac_c_lod_dly[7]))); + assign ex1_c_frac_pre2_b[8] = (~((sel_c_load0 & ex6_frac_lod_ear[8]) | (sel_c_reload0 & ex6_frac_relod_ear[8]) | (sel_c_load1 & ex7_frac_c_lod_dly[8]))); + assign ex1_c_frac_pre2_b[9] = (~((sel_c_load0 & ex6_frac_lod_ear[9]) | (sel_c_reload0 & ex6_frac_relod_ear[9]) | (sel_c_load1 & ex7_frac_c_lod_dly[9]))); + assign ex1_c_frac_pre2_b[10] = (~((sel_c_load0 & ex6_frac_lod_ear[10]) | (sel_c_reload0 & ex6_frac_relod_ear[10]) | (sel_c_load1 & ex7_frac_c_lod_dly[10]))); + assign ex1_c_frac_pre2_b[11] = (~((sel_c_load0 & ex6_frac_lod_ear[11]) | (sel_c_reload0 & ex6_frac_relod_ear[11]) | (sel_c_load1 & ex7_frac_c_lod_dly[11]))); + assign ex1_c_frac_pre2_b[12] = (~((sel_c_load0 & ex6_frac_lod_ear[12]) | (sel_c_reload0 & ex6_frac_relod_ear[12]) | (sel_c_load1 & ex7_frac_c_lod_dly[12]))); + assign ex1_c_frac_pre2_b[13] = (~((sel_c_load0 & ex6_frac_lod_ear[13]) | (sel_c_reload0 & ex6_frac_relod_ear[13]) | (sel_c_load1 & ex7_frac_c_lod_dly[13]))); + assign ex1_c_frac_pre2_b[14] = (~((sel_c_load0 & ex6_frac_lod_ear[14]) | (sel_c_reload0 & ex6_frac_relod_ear[14]) | (sel_c_load1 & ex7_frac_c_lod_dly[14]))); + assign ex1_c_frac_pre2_b[15] = (~((sel_c_load0 & ex6_frac_lod_ear[15]) | (sel_c_reload0 & ex6_frac_relod_ear[15]) | (sel_c_load1 & ex7_frac_c_lod_dly[15]))); + assign ex1_c_frac_pre2_b[16] = (~((sel_c_load0 & ex6_frac_lod_ear[16]) | (sel_c_reload0 & ex6_frac_relod_ear[16]) | (sel_c_load1 & ex7_frac_c_lod_dly[16]))); + assign ex1_c_frac_pre2_b[17] = (~((sel_c_load0 & ex6_frac_lod_ear[17]) | (sel_c_reload0 & ex6_frac_relod_ear[17]) | (sel_c_load1 & ex7_frac_c_lod_dly[17]))); + assign ex1_c_frac_pre2_b[18] = (~((sel_c_load0 & ex6_frac_lod_ear[18]) | (sel_c_reload0 & ex6_frac_relod_ear[18]) | (sel_c_load1 & ex7_frac_c_lod_dly[18]))); + assign ex1_c_frac_pre2_b[19] = (~((sel_c_load0 & ex6_frac_lod_ear[19]) | (sel_c_reload0 & ex6_frac_relod_ear[19]) | (sel_c_load1 & ex7_frac_c_lod_dly[19]))); + assign ex1_c_frac_pre2_b[20] = (~((sel_c_load0 & ex6_frac_lod_ear[20]) | (sel_c_reload0 & ex6_frac_relod_ear[20]) | (sel_c_load1 & ex7_frac_c_lod_dly[20]))); + assign ex1_c_frac_pre2_b[21] = (~((sel_c_load0 & ex6_frac_lod_ear[21]) | (sel_c_reload0 & ex6_frac_relod_ear[21]) | (sel_c_load1 & ex7_frac_c_lod_dly[21]))); + assign ex1_c_frac_pre2_b[22] = (~((sel_c_load0 & ex6_frac_lod_ear[22]) | (sel_c_reload0 & ex6_frac_relod_ear[22]) | (sel_c_load1 & ex7_frac_c_lod_dly[22]))); + assign ex1_c_frac_pre2_b[23] = (~((sel_c_load0 & ex6_frac_lod_ear[23]) | (sel_c_reload0 & ex6_frac_relod_ear[23]) | (sel_c_load1 & ex7_frac_c_lod_dly[23]))); + assign ex1_c_frac_pre2_b[24] = (~((sel_c_load0 & ex6_frac_lod_ear[24]) | (sel_c_reload0 & ex6_frac_relod_ear[24]) | (sel_c_load1 & ex7_frac_c_lod_dly[24]))); + assign ex1_c_frac_pre2_b[25] = (~((sel_c_load0 & ex6_frac_lod_ear[25]) | (sel_c_reload0 & ex6_frac_relod_ear[25]) | (sel_c_load1 & ex7_frac_c_lod_dly[25]))); + assign ex1_c_frac_pre2_b[26] = (~((sel_c_load0 & ex6_frac_lod_ear[26]) | (sel_c_reload0 & ex6_frac_relod_ear[26]) | (sel_c_load1 & ex7_frac_c_lod_dly[26]))); + assign ex1_c_frac_pre2_b[27] = (~((sel_c_load0 & ex6_frac_lod_ear[27]) | (sel_c_reload0 & ex6_frac_relod_ear[27]) | (sel_c_load1 & ex7_frac_c_lod_dly[27]))); + assign ex1_c_frac_pre2_b[28] = (~((sel_c_load0 & ex6_frac_lod_ear[28]) | (sel_c_reload0 & ex6_frac_relod_ear[28]) | (sel_c_load1 & ex7_frac_c_lod_dly[28]))); + assign ex1_c_frac_pre2_b[29] = (~((sel_c_load0 & ex6_frac_lod_ear[29]) | (sel_c_reload0 & ex6_frac_relod_ear[29]) | (sel_c_load1 & ex7_frac_c_lod_dly[29]))); + assign ex1_c_frac_pre2_b[30] = (~((sel_c_load0 & ex6_frac_lod_ear[30]) | (sel_c_reload0 & ex6_frac_relod_ear[30]) | (sel_c_load1 & ex7_frac_c_lod_dly[30]))); + assign ex1_c_frac_pre2_b[31] = (~((sel_c_load0 & ex6_frac_lod_ear[31]) | (sel_c_reload0 & ex6_frac_relod_ear[31]) | (sel_c_load1 & ex7_frac_c_lod_dly[31]))); + assign ex1_c_frac_pre2_b[32] = (~((sel_c_load0 & ex6_frac_lod_ear[32]) | (sel_c_reload0 & ex6_frac_relod_ear[32]) | (sel_c_load1 & ex7_frac_c_lod_dly[32]))); + assign ex1_c_frac_pre2_b[33] = (~((sel_c_load0 & ex6_frac_lod_ear[33]) | (sel_c_reload0 & ex6_frac_relod_ear[33]) | (sel_c_load1 & ex7_frac_c_lod_dly[33]))); + assign ex1_c_frac_pre2_b[34] = (~((sel_c_load0 & ex6_frac_lod_ear[34]) | (sel_c_reload0 & ex6_frac_relod_ear[34]) | (sel_c_load1 & ex7_frac_c_lod_dly[34]))); + assign ex1_c_frac_pre2_b[35] = (~((sel_c_load0 & ex6_frac_lod_ear[35]) | (sel_c_reload0 & ex6_frac_relod_ear[35]) | (sel_c_load1 & ex7_frac_c_lod_dly[35]))); + assign ex1_c_frac_pre2_b[36] = (~((sel_c_load0 & ex6_frac_lod_ear[36]) | (sel_c_reload0 & ex6_frac_relod_ear[36]) | (sel_c_load1 & ex7_frac_c_lod_dly[36]))); + assign ex1_c_frac_pre2_b[37] = (~((sel_c_load0 & ex6_frac_lod_ear[37]) | (sel_c_reload0 & ex6_frac_relod_ear[37]) | (sel_c_load1 & ex7_frac_c_lod_dly[37]))); + assign ex1_c_frac_pre2_b[38] = (~((sel_c_load0 & ex6_frac_lod_ear[38]) | (sel_c_reload0 & ex6_frac_relod_ear[38]) | (sel_c_load1 & ex7_frac_c_lod_dly[38]))); + assign ex1_c_frac_pre2_b[39] = (~((sel_c_load0 & ex6_frac_lod_ear[39]) | (sel_c_reload0 & ex6_frac_relod_ear[39]) | (sel_c_load1 & ex7_frac_c_lod_dly[39]))); + assign ex1_c_frac_pre2_b[40] = (~((sel_c_load0 & ex6_frac_lod_ear[40]) | (sel_c_reload0 & ex6_frac_relod_ear[40]) | (sel_c_load1 & ex7_frac_c_lod_dly[40]))); + assign ex1_c_frac_pre2_b[41] = (~((sel_c_load0 & ex6_frac_lod_ear[41]) | (sel_c_reload0 & ex6_frac_relod_ear[41]) | (sel_c_load1 & ex7_frac_c_lod_dly[41]))); + assign ex1_c_frac_pre2_b[42] = (~((sel_c_load0 & ex6_frac_lod_ear[42]) | (sel_c_reload0 & ex6_frac_relod_ear[42]) | (sel_c_load1 & ex7_frac_c_lod_dly[42]))); + assign ex1_c_frac_pre2_b[43] = (~((sel_c_load0 & ex6_frac_lod_ear[43]) | (sel_c_reload0 & ex6_frac_relod_ear[43]) | (sel_c_load1 & ex7_frac_c_lod_dly[43]))); + assign ex1_c_frac_pre2_b[44] = (~((sel_c_load0 & ex6_frac_lod_ear[44]) | (sel_c_reload0 & ex6_frac_relod_ear[44]) | (sel_c_load1 & ex7_frac_c_lod_dly[44]))); + assign ex1_c_frac_pre2_b[45] = (~((sel_c_load0 & ex6_frac_lod_ear[45]) | (sel_c_reload0 & ex6_frac_relod_ear[45]) | (sel_c_load1 & ex7_frac_c_lod_dly[45]))); + assign ex1_c_frac_pre2_b[46] = (~((sel_c_load0 & ex6_frac_lod_ear[46]) | (sel_c_reload0 & ex6_frac_relod_ear[46]) | (sel_c_load1 & ex7_frac_c_lod_dly[46]))); + assign ex1_c_frac_pre2_b[47] = (~((sel_c_load0 & ex6_frac_lod_ear[47]) | (sel_c_reload0 & ex6_frac_relod_ear[47]) | (sel_c_load1 & ex7_frac_c_lod_dly[47]))); + assign ex1_c_frac_pre2_b[48] = (~((sel_c_load0 & ex6_frac_lod_ear[48]) | (sel_c_reload0 & ex6_frac_relod_ear[48]) | (sel_c_load1 & ex7_frac_c_lod_dly[48]))); + assign ex1_c_frac_pre2_b[49] = (~((sel_c_load0 & ex6_frac_lod_ear[49]) | (sel_c_reload0 & ex6_frac_relod_ear[49]) | (sel_c_load1 & ex7_frac_c_lod_dly[49]))); + assign ex1_c_frac_pre2_b[50] = (~((sel_c_load0 & ex6_frac_lod_ear[50]) | (sel_c_reload0 & ex6_frac_relod_ear[50]) | (sel_c_load1 & ex7_frac_c_lod_dly[50]))); + assign ex1_c_frac_pre2_b[51] = (~((sel_c_load0 & ex6_frac_lod_ear[51]) | (sel_c_reload0 & ex6_frac_relod_ear[51]) | (sel_c_load1 & ex7_frac_c_lod_dly[51]))); + assign ex1_c_frac_pre2_b[52] = (~((sel_c_load0 & ex6_frac_lod_ear[52]) | (sel_c_reload0 & ex6_frac_relod_ear[52]) | (sel_c_load1 & ex7_frac_c_lod_dly[52]))); + + assign ex1_b_frac_pre2_b[0] = (~((sel_b_load0 & ex6_frac_lod_ear[0]) | (sel_b_reload0 & ex6_frac_relod_ear[0]) | (sel_b_load1 & ex7_frac_b_lod_dly[0]))); + assign ex1_b_frac_pre2_b[1] = (~((sel_b_load0 & ex6_frac_lod_ear[1]) | (sel_b_reload0 & ex6_frac_relod_ear[1]) | (sel_b_load1 & ex7_frac_b_lod_dly[1]))); + assign ex1_b_frac_pre2_b[2] = (~((sel_b_load0 & ex6_frac_lod_ear[2]) | (sel_b_reload0 & ex6_frac_relod_ear[2]) | (sel_b_load1 & ex7_frac_b_lod_dly[2]))); + assign ex1_b_frac_pre2_b[3] = (~((sel_b_load0 & ex6_frac_lod_ear[3]) | (sel_b_reload0 & ex6_frac_relod_ear[3]) | (sel_b_load1 & ex7_frac_b_lod_dly[3]))); + assign ex1_b_frac_pre2_b[4] = (~((sel_b_load0 & ex6_frac_lod_ear[4]) | (sel_b_reload0 & ex6_frac_relod_ear[4]) | (sel_b_load1 & ex7_frac_b_lod_dly[4]))); + assign ex1_b_frac_pre2_b[5] = (~((sel_b_load0 & ex6_frac_lod_ear[5]) | (sel_b_reload0 & ex6_frac_relod_ear[5]) | (sel_b_load1 & ex7_frac_b_lod_dly[5]))); + assign ex1_b_frac_pre2_b[6] = (~((sel_b_load0 & ex6_frac_lod_ear[6]) | (sel_b_reload0 & ex6_frac_relod_ear[6]) | (sel_b_load1 & ex7_frac_b_lod_dly[6]))); + assign ex1_b_frac_pre2_b[7] = (~((sel_b_load0 & ex6_frac_lod_ear[7]) | (sel_b_reload0 & ex6_frac_relod_ear[7]) | (sel_b_load1 & ex7_frac_b_lod_dly[7]))); + assign ex1_b_frac_pre2_b[8] = (~((sel_b_load0 & ex6_frac_lod_ear[8]) | (sel_b_reload0 & ex6_frac_relod_ear[8]) | (sel_b_load1 & ex7_frac_b_lod_dly[8]))); + assign ex1_b_frac_pre2_b[9] = (~((sel_b_load0 & ex6_frac_lod_ear[9]) | (sel_b_reload0 & ex6_frac_relod_ear[9]) | (sel_b_load1 & ex7_frac_b_lod_dly[9]))); + assign ex1_b_frac_pre2_b[10] = (~((sel_b_load0 & ex6_frac_lod_ear[10]) | (sel_b_reload0 & ex6_frac_relod_ear[10]) | (sel_b_load1 & ex7_frac_b_lod_dly[10]))); + assign ex1_b_frac_pre2_b[11] = (~((sel_b_load0 & ex6_frac_lod_ear[11]) | (sel_b_reload0 & ex6_frac_relod_ear[11]) | (sel_b_load1 & ex7_frac_b_lod_dly[11]))); + assign ex1_b_frac_pre2_b[12] = (~((sel_b_load0 & ex6_frac_lod_ear[12]) | (sel_b_reload0 & ex6_frac_relod_ear[12]) | (sel_b_load1 & ex7_frac_b_lod_dly[12]))); + assign ex1_b_frac_pre2_b[13] = (~((sel_b_load0 & ex6_frac_lod_ear[13]) | (sel_b_reload0 & ex6_frac_relod_ear[13]) | (sel_b_load1 & ex7_frac_b_lod_dly[13]))); + assign ex1_b_frac_pre2_b[14] = (~((sel_b_load0 & ex6_frac_lod_ear[14]) | (sel_b_reload0 & ex6_frac_relod_ear[14]) | (sel_b_load1 & ex7_frac_b_lod_dly[14]))); + assign ex1_b_frac_pre2_b[15] = (~((sel_b_load0 & ex6_frac_lod_ear[15]) | (sel_b_reload0 & ex6_frac_relod_ear[15]) | (sel_b_load1 & ex7_frac_b_lod_dly[15]))); + assign ex1_b_frac_pre2_b[16] = (~((sel_b_load0 & ex6_frac_lod_ear[16]) | (sel_b_reload0 & ex6_frac_relod_ear[16]) | (sel_b_load1 & ex7_frac_b_lod_dly[16]))); + assign ex1_b_frac_pre2_b[17] = (~((sel_b_load0 & ex6_frac_lod_ear[17]) | (sel_b_reload0 & ex6_frac_relod_ear[17]) | (sel_b_load1 & ex7_frac_b_lod_dly[17]))); + assign ex1_b_frac_pre2_b[18] = (~((sel_b_load0 & ex6_frac_lod_ear[18]) | (sel_b_reload0 & ex6_frac_relod_ear[18]) | (sel_b_load1 & ex7_frac_b_lod_dly[18]))); + assign ex1_b_frac_pre2_b[19] = (~((sel_b_load0 & ex6_frac_lod_ear[19]) | (sel_b_reload0 & ex6_frac_relod_ear[19]) | (sel_b_load1 & ex7_frac_b_lod_dly[19]))); + assign ex1_b_frac_pre2_b[20] = (~((sel_b_load0 & ex6_frac_lod_ear[20]) | (sel_b_reload0 & ex6_frac_relod_ear[20]) | (sel_b_load1 & ex7_frac_b_lod_dly[20]))); + assign ex1_b_frac_pre2_b[21] = (~((sel_b_load0 & ex6_frac_lod_ear[21]) | (sel_b_reload0 & ex6_frac_relod_ear[21]) | (sel_b_load1 & ex7_frac_b_lod_dly[21]))); + assign ex1_b_frac_pre2_b[22] = (~((sel_b_load0 & ex6_frac_lod_ear[22]) | (sel_b_reload0 & ex6_frac_relod_ear[22]) | (sel_b_load1 & ex7_frac_b_lod_dly[22]))); + assign ex1_b_frac_pre2_b[23] = (~((sel_b_load0 & ex6_frac_lod_ear[23]) | (sel_b_reload0 & ex6_frac_relod_ear[23]) | (sel_b_load1 & ex7_frac_b_lod_dly[23]))); + assign ex1_b_frac_pre2_b[24] = (~((sel_b_load0 & ex6_frac_lod_ear[24]) | (sel_b_reload0 & ex6_frac_relod_ear[24]) | (sel_b_load1 & ex7_frac_b_lod_dly[24]))); + assign ex1_b_frac_pre2_b[25] = (~((sel_b_load0 & ex6_frac_lod_ear[25]) | (sel_b_reload0 & ex6_frac_relod_ear[25]) | (sel_b_load1 & ex7_frac_b_lod_dly[25]))); + assign ex1_b_frac_pre2_b[26] = (~((sel_b_load0 & ex6_frac_lod_ear[26]) | (sel_b_reload0 & ex6_frac_relod_ear[26]) | (sel_b_load1 & ex7_frac_b_lod_dly[26]))); + assign ex1_b_frac_pre2_b[27] = (~((sel_b_load0 & ex6_frac_lod_ear[27]) | (sel_b_reload0 & ex6_frac_relod_ear[27]) | (sel_b_load1 & ex7_frac_b_lod_dly[27]))); + assign ex1_b_frac_pre2_b[28] = (~((sel_b_load0 & ex6_frac_lod_ear[28]) | (sel_b_reload0 & ex6_frac_relod_ear[28]) | (sel_b_load1 & ex7_frac_b_lod_dly[28]))); + assign ex1_b_frac_pre2_b[29] = (~((sel_b_load0 & ex6_frac_lod_ear[29]) | (sel_b_reload0 & ex6_frac_relod_ear[29]) | (sel_b_load1 & ex7_frac_b_lod_dly[29]))); + assign ex1_b_frac_pre2_b[30] = (~((sel_b_load0 & ex6_frac_lod_ear[30]) | (sel_b_reload0 & ex6_frac_relod_ear[30]) | (sel_b_load1 & ex7_frac_b_lod_dly[30]))); + assign ex1_b_frac_pre2_b[31] = (~((sel_b_load0 & ex6_frac_lod_ear[31]) | (sel_b_reload0 & ex6_frac_relod_ear[31]) | (sel_b_load1 & ex7_frac_b_lod_dly[31]))); + assign ex1_b_frac_pre2_b[32] = (~((sel_b_load0 & ex6_frac_lod_ear[32]) | (sel_b_reload0 & ex6_frac_relod_ear[32]) | (sel_b_load1 & ex7_frac_b_lod_dly[32]))); + assign ex1_b_frac_pre2_b[33] = (~((sel_b_load0 & ex6_frac_lod_ear[33]) | (sel_b_reload0 & ex6_frac_relod_ear[33]) | (sel_b_load1 & ex7_frac_b_lod_dly[33]))); + assign ex1_b_frac_pre2_b[34] = (~((sel_b_load0 & ex6_frac_lod_ear[34]) | (sel_b_reload0 & ex6_frac_relod_ear[34]) | (sel_b_load1 & ex7_frac_b_lod_dly[34]))); + assign ex1_b_frac_pre2_b[35] = (~((sel_b_load0 & ex6_frac_lod_ear[35]) | (sel_b_reload0 & ex6_frac_relod_ear[35]) | (sel_b_load1 & ex7_frac_b_lod_dly[35]))); + assign ex1_b_frac_pre2_b[36] = (~((sel_b_load0 & ex6_frac_lod_ear[36]) | (sel_b_reload0 & ex6_frac_relod_ear[36]) | (sel_b_load1 & ex7_frac_b_lod_dly[36]))); + assign ex1_b_frac_pre2_b[37] = (~((sel_b_load0 & ex6_frac_lod_ear[37]) | (sel_b_reload0 & ex6_frac_relod_ear[37]) | (sel_b_load1 & ex7_frac_b_lod_dly[37]))); + assign ex1_b_frac_pre2_b[38] = (~((sel_b_load0 & ex6_frac_lod_ear[38]) | (sel_b_reload0 & ex6_frac_relod_ear[38]) | (sel_b_load1 & ex7_frac_b_lod_dly[38]))); + assign ex1_b_frac_pre2_b[39] = (~((sel_b_load0 & ex6_frac_lod_ear[39]) | (sel_b_reload0 & ex6_frac_relod_ear[39]) | (sel_b_load1 & ex7_frac_b_lod_dly[39]))); + assign ex1_b_frac_pre2_b[40] = (~((sel_b_load0 & ex6_frac_lod_ear[40]) | (sel_b_reload0 & ex6_frac_relod_ear[40]) | (sel_b_load1 & ex7_frac_b_lod_dly[40]))); + assign ex1_b_frac_pre2_b[41] = (~((sel_b_load0 & ex6_frac_lod_ear[41]) | (sel_b_reload0 & ex6_frac_relod_ear[41]) | (sel_b_load1 & ex7_frac_b_lod_dly[41]))); + assign ex1_b_frac_pre2_b[42] = (~((sel_b_load0 & ex6_frac_lod_ear[42]) | (sel_b_reload0 & ex6_frac_relod_ear[42]) | (sel_b_load1 & ex7_frac_b_lod_dly[42]))); + assign ex1_b_frac_pre2_b[43] = (~((sel_b_load0 & ex6_frac_lod_ear[43]) | (sel_b_reload0 & ex6_frac_relod_ear[43]) | (sel_b_load1 & ex7_frac_b_lod_dly[43]))); + assign ex1_b_frac_pre2_b[44] = (~((sel_b_load0 & ex6_frac_lod_ear[44]) | (sel_b_reload0 & ex6_frac_relod_ear[44]) | (sel_b_load1 & ex7_frac_b_lod_dly[44]))); + assign ex1_b_frac_pre2_b[45] = (~((sel_b_load0 & ex6_frac_lod_ear[45]) | (sel_b_reload0 & ex6_frac_relod_ear[45]) | (sel_b_load1 & ex7_frac_b_lod_dly[45]))); + assign ex1_b_frac_pre2_b[46] = (~((sel_b_load0 & ex6_frac_lod_ear[46]) | (sel_b_reload0 & ex6_frac_relod_ear[46]) | (sel_b_load1 & ex7_frac_b_lod_dly[46]))); + assign ex1_b_frac_pre2_b[47] = (~((sel_b_load0 & ex6_frac_lod_ear[47]) | (sel_b_reload0 & ex6_frac_relod_ear[47]) | (sel_b_load1 & ex7_frac_b_lod_dly[47]))); + assign ex1_b_frac_pre2_b[48] = (~((sel_b_load0 & ex6_frac_lod_ear[48]) | (sel_b_reload0 & ex6_frac_relod_ear[48]) | (sel_b_load1 & ex7_frac_b_lod_dly[48]))); + assign ex1_b_frac_pre2_b[49] = (~((sel_b_load0 & ex6_frac_lod_ear[49]) | (sel_b_reload0 & ex6_frac_relod_ear[49]) | (sel_b_load1 & ex7_frac_b_lod_dly[49]))); + assign ex1_b_frac_pre2_b[50] = (~((sel_b_load0 & ex6_frac_lod_ear[50]) | (sel_b_reload0 & ex6_frac_relod_ear[50]) | (sel_b_load1 & ex7_frac_b_lod_dly[50]))); + assign ex1_b_frac_pre2_b[51] = (~((sel_b_load0 & ex6_frac_lod_ear[51]) | (sel_b_reload0 & ex6_frac_relod_ear[51]) | (sel_b_load1 & ex7_frac_b_lod_dly[51]))); + assign ex1_b_frac_pre2_b[52] = (~((sel_b_load0 & ex6_frac_lod_ear[52]) | (sel_b_reload0 & ex6_frac_relod_ear[52]) | (sel_b_load1 & ex7_frac_b_lod_dly[52]))); + + assign ex1_s_frac_pre2_b[0] = (~((sel_s_load0 & ex6_frac_lod_ear[0]) | (sel_s_reload0 & ex6_frac_relod_ear[0]) | (sel_s_load1 & ex7_frac_s_lod_dly[0]))); + assign ex1_s_frac_pre2_b[1] = (~((sel_s_load0 & ex6_frac_lod_ear[1]) | (sel_s_reload0 & ex6_frac_relod_ear[1]) | (sel_s_load1 & ex7_frac_s_lod_dly[1]))); + assign ex1_s_frac_pre2_b[2] = (~((sel_s_load0 & ex6_frac_lod_ear[2]) | (sel_s_reload0 & ex6_frac_relod_ear[2]) | (sel_s_load1 & ex7_frac_s_lod_dly[2]))); + assign ex1_s_frac_pre2_b[3] = (~((sel_s_load0 & ex6_frac_lod_ear[3]) | (sel_s_reload0 & ex6_frac_relod_ear[3]) | (sel_s_load1 & ex7_frac_s_lod_dly[3]))); + assign ex1_s_frac_pre2_b[4] = (~((sel_s_load0 & ex6_frac_lod_ear[4]) | (sel_s_reload0 & ex6_frac_relod_ear[4]) | (sel_s_load1 & ex7_frac_s_lod_dly[4]))); + assign ex1_s_frac_pre2_b[5] = (~((sel_s_load0 & ex6_frac_lod_ear[5]) | (sel_s_reload0 & ex6_frac_relod_ear[5]) | (sel_s_load1 & ex7_frac_s_lod_dly[5]))); + assign ex1_s_frac_pre2_b[6] = (~((sel_s_load0 & ex6_frac_lod_ear[6]) | (sel_s_reload0 & ex6_frac_relod_ear[6]) | (sel_s_load1 & ex7_frac_s_lod_dly[6]))); + assign ex1_s_frac_pre2_b[7] = (~((sel_s_load0 & ex6_frac_lod_ear[7]) | (sel_s_reload0 & ex6_frac_relod_ear[7]) | (sel_s_load1 & ex7_frac_s_lod_dly[7]))); + assign ex1_s_frac_pre2_b[8] = (~((sel_s_load0 & ex6_frac_lod_ear[8]) | (sel_s_reload0 & ex6_frac_relod_ear[8]) | (sel_s_load1 & ex7_frac_s_lod_dly[8]))); + assign ex1_s_frac_pre2_b[9] = (~((sel_s_load0 & ex6_frac_lod_ear[9]) | (sel_s_reload0 & ex6_frac_relod_ear[9]) | (sel_s_load1 & ex7_frac_s_lod_dly[9]))); + assign ex1_s_frac_pre2_b[10] = (~((sel_s_load0 & ex6_frac_lod_ear[10]) | (sel_s_reload0 & ex6_frac_relod_ear[10]) | (sel_s_load1 & ex7_frac_s_lod_dly[10]))); + assign ex1_s_frac_pre2_b[11] = (~((sel_s_load0 & ex6_frac_lod_ear[11]) | (sel_s_reload0 & ex6_frac_relod_ear[11]) | (sel_s_load1 & ex7_frac_s_lod_dly[11]))); + assign ex1_s_frac_pre2_b[12] = (~((sel_s_load0 & ex6_frac_lod_ear[12]) | (sel_s_reload0 & ex6_frac_relod_ear[12]) | (sel_s_load1 & ex7_frac_s_lod_dly[12]))); + assign ex1_s_frac_pre2_b[13] = (~((sel_s_load0 & ex6_frac_lod_ear[13]) | (sel_s_reload0 & ex6_frac_relod_ear[13]) | (sel_s_load1 & ex7_frac_s_lod_dly[13]))); + assign ex1_s_frac_pre2_b[14] = (~((sel_s_load0 & ex6_frac_lod_ear[14]) | (sel_s_reload0 & ex6_frac_relod_ear[14]) | (sel_s_load1 & ex7_frac_s_lod_dly[14]))); + assign ex1_s_frac_pre2_b[15] = (~((sel_s_load0 & ex6_frac_lod_ear[15]) | (sel_s_reload0 & ex6_frac_relod_ear[15]) | (sel_s_load1 & ex7_frac_s_lod_dly[15]))); + assign ex1_s_frac_pre2_b[16] = (~((sel_s_load0 & ex6_frac_lod_ear[16]) | (sel_s_reload0 & ex6_frac_relod_ear[16]) | (sel_s_load1 & ex7_frac_s_lod_dly[16]))); + assign ex1_s_frac_pre2_b[17] = (~((sel_s_load0 & ex6_frac_lod_ear[17]) | (sel_s_reload0 & ex6_frac_relod_ear[17]) | (sel_s_load1 & ex7_frac_s_lod_dly[17]))); + assign ex1_s_frac_pre2_b[18] = (~((sel_s_load0 & ex6_frac_lod_ear[18]) | (sel_s_reload0 & ex6_frac_relod_ear[18]) | (sel_s_load1 & ex7_frac_s_lod_dly[18]))); + assign ex1_s_frac_pre2_b[19] = (~((sel_s_load0 & ex6_frac_lod_ear[19]) | (sel_s_reload0 & ex6_frac_relod_ear[19]) | (sel_s_load1 & ex7_frac_s_lod_dly[19]))); + assign ex1_s_frac_pre2_b[20] = (~((sel_s_load0 & ex6_frac_lod_ear[20]) | (sel_s_reload0 & ex6_frac_relod_ear[20]) | (sel_s_load1 & ex7_frac_s_lod_dly[20]))); + assign ex1_s_frac_pre2_b[21] = (~((sel_s_load0 & ex6_frac_lod_ear[21]) | (sel_s_reload0 & ex6_frac_relod_ear[21]) | (sel_s_load1 & ex7_frac_s_lod_dly[21]))); + assign ex1_s_frac_pre2_b[22] = (~((sel_s_load0 & ex6_frac_lod_ear[22]) | (sel_s_reload0 & ex6_frac_relod_ear[22]) | (sel_s_load1 & ex7_frac_s_lod_dly[22]))); + assign ex1_s_frac_pre2_b[23] = (~((sel_s_load0 & ex6_frac_lod_ear[23]) | (sel_s_reload0 & ex6_frac_relod_ear[23]) | (sel_s_load1 & ex7_frac_s_lod_dly[23]))); + assign ex1_s_frac_pre2_b[24] = (~((sel_s_load0 & ex6_frac_lod_ear[24]) | (sel_s_reload0 & ex6_frac_relod_ear[24]) | (sel_s_load1 & ex7_frac_s_lod_dly[24]))); + assign ex1_s_frac_pre2_b[25] = (~((sel_s_load0 & ex6_frac_lod_ear[25]) | (sel_s_reload0 & ex6_frac_relod_ear[25]) | (sel_s_load1 & ex7_frac_s_lod_dly[25]))); + assign ex1_s_frac_pre2_b[26] = (~((sel_s_load0 & ex6_frac_lod_ear[26]) | (sel_s_reload0 & ex6_frac_relod_ear[26]) | (sel_s_load1 & ex7_frac_s_lod_dly[26]))); + assign ex1_s_frac_pre2_b[27] = (~((sel_s_load0 & ex6_frac_lod_ear[27]) | (sel_s_reload0 & ex6_frac_relod_ear[27]) | (sel_s_load1 & ex7_frac_s_lod_dly[27]))); + assign ex1_s_frac_pre2_b[28] = (~((sel_s_load0 & ex6_frac_lod_ear[28]) | (sel_s_reload0 & ex6_frac_relod_ear[28]) | (sel_s_load1 & ex7_frac_s_lod_dly[28]))); + assign ex1_s_frac_pre2_b[29] = (~((sel_s_load0 & ex6_frac_lod_ear[29]) | (sel_s_reload0 & ex6_frac_relod_ear[29]) | (sel_s_load1 & ex7_frac_s_lod_dly[29]))); + assign ex1_s_frac_pre2_b[30] = (~((sel_s_load0 & ex6_frac_lod_ear[30]) | (sel_s_reload0 & ex6_frac_relod_ear[30]) | (sel_s_load1 & ex7_frac_s_lod_dly[30]))); + assign ex1_s_frac_pre2_b[31] = (~((sel_s_load0 & ex6_frac_lod_ear[31]) | (sel_s_reload0 & ex6_frac_relod_ear[31]) | (sel_s_load1 & ex7_frac_s_lod_dly[31]))); + assign ex1_s_frac_pre2_b[32] = (~((sel_s_load0 & ex6_frac_lod_ear[32]) | (sel_s_reload0 & ex6_frac_relod_ear[32]) | (sel_s_load1 & ex7_frac_s_lod_dly[32]))); + assign ex1_s_frac_pre2_b[33] = (~((sel_s_load0 & ex6_frac_lod_ear[33]) | (sel_s_reload0 & ex6_frac_relod_ear[33]) | (sel_s_load1 & ex7_frac_s_lod_dly[33]))); + assign ex1_s_frac_pre2_b[34] = (~((sel_s_load0 & ex6_frac_lod_ear[34]) | (sel_s_reload0 & ex6_frac_relod_ear[34]) | (sel_s_load1 & ex7_frac_s_lod_dly[34]))); + assign ex1_s_frac_pre2_b[35] = (~((sel_s_load0 & ex6_frac_lod_ear[35]) | (sel_s_reload0 & ex6_frac_relod_ear[35]) | (sel_s_load1 & ex7_frac_s_lod_dly[35]))); + assign ex1_s_frac_pre2_b[36] = (~((sel_s_load0 & ex6_frac_lod_ear[36]) | (sel_s_reload0 & ex6_frac_relod_ear[36]) | (sel_s_load1 & ex7_frac_s_lod_dly[36]))); + assign ex1_s_frac_pre2_b[37] = (~((sel_s_load0 & ex6_frac_lod_ear[37]) | (sel_s_reload0 & ex6_frac_relod_ear[37]) | (sel_s_load1 & ex7_frac_s_lod_dly[37]))); + assign ex1_s_frac_pre2_b[38] = (~((sel_s_load0 & ex6_frac_lod_ear[38]) | (sel_s_reload0 & ex6_frac_relod_ear[38]) | (sel_s_load1 & ex7_frac_s_lod_dly[38]))); + assign ex1_s_frac_pre2_b[39] = (~((sel_s_load0 & ex6_frac_lod_ear[39]) | (sel_s_reload0 & ex6_frac_relod_ear[39]) | (sel_s_load1 & ex7_frac_s_lod_dly[39]))); + assign ex1_s_frac_pre2_b[40] = (~((sel_s_load0 & ex6_frac_lod_ear[40]) | (sel_s_reload0 & ex6_frac_relod_ear[40]) | (sel_s_load1 & ex7_frac_s_lod_dly[40]))); + assign ex1_s_frac_pre2_b[41] = (~((sel_s_load0 & ex6_frac_lod_ear[41]) | (sel_s_reload0 & ex6_frac_relod_ear[41]) | (sel_s_load1 & ex7_frac_s_lod_dly[41]))); + assign ex1_s_frac_pre2_b[42] = (~((sel_s_load0 & ex6_frac_lod_ear[42]) | (sel_s_reload0 & ex6_frac_relod_ear[42]) | (sel_s_load1 & ex7_frac_s_lod_dly[42]))); + assign ex1_s_frac_pre2_b[43] = (~((sel_s_load0 & ex6_frac_lod_ear[43]) | (sel_s_reload0 & ex6_frac_relod_ear[43]) | (sel_s_load1 & ex7_frac_s_lod_dly[43]))); + assign ex1_s_frac_pre2_b[44] = (~((sel_s_load0 & ex6_frac_lod_ear[44]) | (sel_s_reload0 & ex6_frac_relod_ear[44]) | (sel_s_load1 & ex7_frac_s_lod_dly[44]))); + assign ex1_s_frac_pre2_b[45] = (~((sel_s_load0 & ex6_frac_lod_ear[45]) | (sel_s_reload0 & ex6_frac_relod_ear[45]) | (sel_s_load1 & ex7_frac_s_lod_dly[45]))); + assign ex1_s_frac_pre2_b[46] = (~((sel_s_load0 & ex6_frac_lod_ear[46]) | (sel_s_reload0 & ex6_frac_relod_ear[46]) | (sel_s_load1 & ex7_frac_s_lod_dly[46]))); + assign ex1_s_frac_pre2_b[47] = (~((sel_s_load0 & ex6_frac_lod_ear[47]) | (sel_s_reload0 & ex6_frac_relod_ear[47]) | (sel_s_load1 & ex7_frac_s_lod_dly[47]))); + assign ex1_s_frac_pre2_b[48] = (~((sel_s_load0 & ex6_frac_lod_ear[48]) | (sel_s_reload0 & ex6_frac_relod_ear[48]) | (sel_s_load1 & ex7_frac_s_lod_dly[48]))); + assign ex1_s_frac_pre2_b[49] = (~((sel_s_load0 & ex6_frac_lod_ear[49]) | (sel_s_reload0 & ex6_frac_relod_ear[49]) | (sel_s_load1 & ex7_frac_s_lod_dly[49]))); + assign ex1_s_frac_pre2_b[50] = (~((sel_s_load0 & ex6_frac_lod_ear[50]) | (sel_s_reload0 & ex6_frac_relod_ear[50]) | (sel_s_load1 & ex7_frac_s_lod_dly[50]))); + assign ex1_s_frac_pre2_b[51] = (~((sel_s_load0 & ex6_frac_lod_ear[51]) | (sel_s_reload0 & ex6_frac_relod_ear[51]) | (sel_s_load1 & ex7_frac_s_lod_dly[51]))); + assign ex1_s_frac_pre2_b[52] = (~((sel_s_load0 & ex6_frac_lod_ear[52]) | (sel_s_reload0 & ex6_frac_relod_ear[52]) | (sel_s_load1 & ex7_frac_s_lod_dly[52]))); + + assign ex1_a_frac_pre[0] = (~(ex1_a_frac_pre1_b[0] & ex1_a_frac_pre2_b[0])); //and ex1_a_frac_pre3_b( 0) + assign ex1_a_frac_pre[1] = (~(ex1_a_frac_pre1_b[1] & ex1_a_frac_pre2_b[1])); //and ex1_a_frac_pre3_b( 1) + assign ex1_a_frac_pre[2] = (~(ex1_a_frac_pre1_b[2] & ex1_a_frac_pre2_b[2])); //and ex1_a_frac_pre3_b( 2) + assign ex1_a_frac_pre[3] = (~(ex1_a_frac_pre1_b[3] & ex1_a_frac_pre2_b[3])); //and ex1_a_frac_pre3_b( 3) + assign ex1_a_frac_pre[4] = (~(ex1_a_frac_pre1_b[4] & ex1_a_frac_pre2_b[4])); //and ex1_a_frac_pre3_b( 4) + assign ex1_a_frac_pre[5] = (~(ex1_a_frac_pre1_b[5] & ex1_a_frac_pre2_b[5])); //and ex1_a_frac_pre3_b( 5) + assign ex1_a_frac_pre[6] = (~(ex1_a_frac_pre1_b[6] & ex1_a_frac_pre2_b[6])); //and ex1_a_frac_pre3_b( 6) + assign ex1_a_frac_pre[7] = (~(ex1_a_frac_pre1_b[7] & ex1_a_frac_pre2_b[7])); //and ex1_a_frac_pre3_b( 7) + assign ex1_a_frac_pre[8] = (~(ex1_a_frac_pre1_b[8] & ex1_a_frac_pre2_b[8])); //and ex1_a_frac_pre3_b( 8) + assign ex1_a_frac_pre[9] = (~(ex1_a_frac_pre1_b[9] & ex1_a_frac_pre2_b[9])); //and ex1_a_frac_pre3_b( 9) + assign ex1_a_frac_pre[10] = (~(ex1_a_frac_pre1_b[10] & ex1_a_frac_pre2_b[10])); //and ex1_a_frac_pre3_b(10) + assign ex1_a_frac_pre[11] = (~(ex1_a_frac_pre1_b[11] & ex1_a_frac_pre2_b[11])); //and ex1_a_frac_pre3_b(11) + assign ex1_a_frac_pre[12] = (~(ex1_a_frac_pre1_b[12] & ex1_a_frac_pre2_b[12])); //and ex1_a_frac_pre3_b(12) + assign ex1_a_frac_pre[13] = (~(ex1_a_frac_pre1_b[13] & ex1_a_frac_pre2_b[13])); //and ex1_a_frac_pre3_b(13) + assign ex1_a_frac_pre[14] = (~(ex1_a_frac_pre1_b[14] & ex1_a_frac_pre2_b[14])); //and ex1_a_frac_pre3_b(14) + assign ex1_a_frac_pre[15] = (~(ex1_a_frac_pre1_b[15] & ex1_a_frac_pre2_b[15])); //and ex1_a_frac_pre3_b(15) + assign ex1_a_frac_pre[16] = (~(ex1_a_frac_pre1_b[16] & ex1_a_frac_pre2_b[16])); //and ex1_a_frac_pre3_b(16) + assign ex1_a_frac_pre[17] = (~(ex1_a_frac_pre1_b[17] & ex1_a_frac_pre2_b[17])); //and ex1_a_frac_pre3_b(17) + assign ex1_a_frac_pre[18] = (~(ex1_a_frac_pre1_b[18] & ex1_a_frac_pre2_b[18])); //and ex1_a_frac_pre3_b(18) + assign ex1_a_frac_pre[19] = (~(ex1_a_frac_pre1_b[19] & ex1_a_frac_pre2_b[19])); //and ex1_a_frac_pre3_b(19) + assign ex1_a_frac_pre[20] = (~(ex1_a_frac_pre1_b[20] & ex1_a_frac_pre2_b[20])); //and ex1_a_frac_pre3_b(20) + assign ex1_a_frac_pre[21] = (~(ex1_a_frac_pre1_b[21] & ex1_a_frac_pre2_b[21])); //and ex1_a_frac_pre3_b(21) + assign ex1_a_frac_pre[22] = (~(ex1_a_frac_pre1_b[22] & ex1_a_frac_pre2_b[22])); //and ex1_a_frac_pre3_b(22) + assign ex1_a_frac_pre[23] = (~(ex1_a_frac_pre1_b[23] & ex1_a_frac_pre2_b[23])); //and ex1_a_frac_pre3_b(23) + assign ex1_a_frac_pre[24] = (~(ex1_a_frac_pre1_b[24] & ex1_a_frac_pre2_b[24])); //and ex1_a_frac_pre3_b(24) + assign ex1_a_frac_pre[25] = (~(ex1_a_frac_pre1_b[25] & ex1_a_frac_pre2_b[25])); //and ex1_a_frac_pre3_b(25) + assign ex1_a_frac_pre[26] = (~(ex1_a_frac_pre1_b[26] & ex1_a_frac_pre2_b[26])); //and ex1_a_frac_pre3_b(26) + assign ex1_a_frac_pre[27] = (~(ex1_a_frac_pre1_b[27] & ex1_a_frac_pre2_b[27])); //and ex1_a_frac_pre3_b(27) + assign ex1_a_frac_pre[28] = (~(ex1_a_frac_pre1_b[28] & ex1_a_frac_pre2_b[28])); //and ex1_a_frac_pre3_b(28) + assign ex1_a_frac_pre[29] = (~(ex1_a_frac_pre1_b[29] & ex1_a_frac_pre2_b[29])); //and ex1_a_frac_pre3_b(29) + assign ex1_a_frac_pre[30] = (~(ex1_a_frac_pre1_b[30] & ex1_a_frac_pre2_b[30])); //and ex1_a_frac_pre3_b(30) + assign ex1_a_frac_pre[31] = (~(ex1_a_frac_pre1_b[31] & ex1_a_frac_pre2_b[31])); //and ex1_a_frac_pre3_b(31) + assign ex1_a_frac_pre[32] = (~(ex1_a_frac_pre1_b[32] & ex1_a_frac_pre2_b[32])); //and ex1_a_frac_pre3_b(32) + assign ex1_a_frac_pre[33] = (~(ex1_a_frac_pre1_b[33] & ex1_a_frac_pre2_b[33])); //and ex1_a_frac_pre3_b(33) + assign ex1_a_frac_pre[34] = (~(ex1_a_frac_pre1_b[34] & ex1_a_frac_pre2_b[34])); //and ex1_a_frac_pre3_b(34) + assign ex1_a_frac_pre[35] = (~(ex1_a_frac_pre1_b[35] & ex1_a_frac_pre2_b[35])); //and ex1_a_frac_pre3_b(35) + assign ex1_a_frac_pre[36] = (~(ex1_a_frac_pre1_b[36] & ex1_a_frac_pre2_b[36])); //and ex1_a_frac_pre3_b(36) + assign ex1_a_frac_pre[37] = (~(ex1_a_frac_pre1_b[37] & ex1_a_frac_pre2_b[37])); //and ex1_a_frac_pre3_b(37) + assign ex1_a_frac_pre[38] = (~(ex1_a_frac_pre1_b[38] & ex1_a_frac_pre2_b[38])); //and ex1_a_frac_pre3_b(38) + assign ex1_a_frac_pre[39] = (~(ex1_a_frac_pre1_b[39] & ex1_a_frac_pre2_b[39])); //and ex1_a_frac_pre3_b(39) + assign ex1_a_frac_pre[40] = (~(ex1_a_frac_pre1_b[40] & ex1_a_frac_pre2_b[40])); //and ex1_a_frac_pre3_b(40) + assign ex1_a_frac_pre[41] = (~(ex1_a_frac_pre1_b[41] & ex1_a_frac_pre2_b[41])); //and ex1_a_frac_pre3_b(41) + assign ex1_a_frac_pre[42] = (~(ex1_a_frac_pre1_b[42] & ex1_a_frac_pre2_b[42])); //and ex1_a_frac_pre3_b(42) + assign ex1_a_frac_pre[43] = (~(ex1_a_frac_pre1_b[43] & ex1_a_frac_pre2_b[43])); //and ex1_a_frac_pre3_b(43) + assign ex1_a_frac_pre[44] = (~(ex1_a_frac_pre1_b[44] & ex1_a_frac_pre2_b[44])); //and ex1_a_frac_pre3_b(44) + assign ex1_a_frac_pre[45] = (~(ex1_a_frac_pre1_b[45] & ex1_a_frac_pre2_b[45])); //and ex1_a_frac_pre3_b(45) + assign ex1_a_frac_pre[46] = (~(ex1_a_frac_pre1_b[46] & ex1_a_frac_pre2_b[46])); //and ex1_a_frac_pre3_b(46) + assign ex1_a_frac_pre[47] = (~(ex1_a_frac_pre1_b[47] & ex1_a_frac_pre2_b[47])); //and ex1_a_frac_pre3_b(47) + assign ex1_a_frac_pre[48] = (~(ex1_a_frac_pre1_b[48] & ex1_a_frac_pre2_b[48])); //and ex1_a_frac_pre3_b(48) + assign ex1_a_frac_pre[49] = (~(ex1_a_frac_pre1_b[49] & ex1_a_frac_pre2_b[49])); //and ex1_a_frac_pre3_b(49) + assign ex1_a_frac_pre[50] = (~(ex1_a_frac_pre1_b[50] & ex1_a_frac_pre2_b[50])); //and ex1_a_frac_pre3_b(50) + assign ex1_a_frac_pre[51] = (~(ex1_a_frac_pre1_b[51] & ex1_a_frac_pre2_b[51])); //and ex1_a_frac_pre3_b(51) + assign ex1_a_frac_pre[52] = (~(ex1_a_frac_pre1_b[52] & ex1_a_frac_pre2_b[52])); //and ex1_a_frac_pre3_b(52) + + assign ex1_c_frac_pre[0] = (~(ex1_c_frac_pre1_b[0] & ex1_c_frac_pre2_b[0] & ex1_c_frac_pre3_b[0])); + assign ex1_c_frac_pre[1] = (~(ex1_c_frac_pre1_b[1] & ex1_c_frac_pre2_b[1] & ex1_c_frac_pre3_b[1])); + assign ex1_c_frac_pre[2] = (~(ex1_c_frac_pre1_b[2] & ex1_c_frac_pre2_b[2] & ex1_c_frac_pre3_b[2])); + assign ex1_c_frac_pre[3] = (~(ex1_c_frac_pre1_b[3] & ex1_c_frac_pre2_b[3] & ex1_c_frac_pre3_b[3])); + assign ex1_c_frac_pre[4] = (~(ex1_c_frac_pre1_b[4] & ex1_c_frac_pre2_b[4] & ex1_c_frac_pre3_b[4])); + assign ex1_c_frac_pre[5] = (~(ex1_c_frac_pre1_b[5] & ex1_c_frac_pre2_b[5] & ex1_c_frac_pre3_b[5])); + assign ex1_c_frac_pre[6] = (~(ex1_c_frac_pre1_b[6] & ex1_c_frac_pre2_b[6] & ex1_c_frac_pre3_b[6])); + assign ex1_c_frac_pre[7] = (~(ex1_c_frac_pre1_b[7] & ex1_c_frac_pre2_b[7] & ex1_c_frac_pre3_b[7])); + assign ex1_c_frac_pre[8] = (~(ex1_c_frac_pre1_b[8] & ex1_c_frac_pre2_b[8] & ex1_c_frac_pre3_b[8])); + assign ex1_c_frac_pre[9] = (~(ex1_c_frac_pre1_b[9] & ex1_c_frac_pre2_b[9] & ex1_c_frac_pre3_b[9])); + assign ex1_c_frac_pre[10] = (~(ex1_c_frac_pre1_b[10] & ex1_c_frac_pre2_b[10] & ex1_c_frac_pre3_b[10])); + assign ex1_c_frac_pre[11] = (~(ex1_c_frac_pre1_b[11] & ex1_c_frac_pre2_b[11] & ex1_c_frac_pre3_b[11])); + assign ex1_c_frac_pre[12] = (~(ex1_c_frac_pre1_b[12] & ex1_c_frac_pre2_b[12] & ex1_c_frac_pre3_b[12])); + assign ex1_c_frac_pre[13] = (~(ex1_c_frac_pre1_b[13] & ex1_c_frac_pre2_b[13] & ex1_c_frac_pre3_b[13])); + assign ex1_c_frac_pre[14] = (~(ex1_c_frac_pre1_b[14] & ex1_c_frac_pre2_b[14] & ex1_c_frac_pre3_b[14])); + assign ex1_c_frac_pre[15] = (~(ex1_c_frac_pre1_b[15] & ex1_c_frac_pre2_b[15] & ex1_c_frac_pre3_b[15])); + assign ex1_c_frac_pre[16] = (~(ex1_c_frac_pre1_b[16] & ex1_c_frac_pre2_b[16] & ex1_c_frac_pre3_b[16])); + assign ex1_c_frac_pre[17] = (~(ex1_c_frac_pre1_b[17] & ex1_c_frac_pre2_b[17] & ex1_c_frac_pre3_b[17])); + assign ex1_c_frac_pre[18] = (~(ex1_c_frac_pre1_b[18] & ex1_c_frac_pre2_b[18] & ex1_c_frac_pre3_b[18])); + assign ex1_c_frac_pre[19] = (~(ex1_c_frac_pre1_b[19] & ex1_c_frac_pre2_b[19] & ex1_c_frac_pre3_b[19])); + assign ex1_c_frac_pre[20] = (~(ex1_c_frac_pre1_b[20] & ex1_c_frac_pre2_b[20] & ex1_c_frac_pre3_b[20])); + assign ex1_c_frac_pre[21] = (~(ex1_c_frac_pre1_b[21] & ex1_c_frac_pre2_b[21] & ex1_c_frac_pre3_b[21])); + assign ex1_c_frac_pre[22] = (~(ex1_c_frac_pre1_b[22] & ex1_c_frac_pre2_b[22] & ex1_c_frac_pre3_b[22])); + assign ex1_c_frac_pre[23] = (~(ex1_c_frac_pre1_b[23] & ex1_c_frac_pre2_b[23] & ex1_c_frac_pre3_b[23])); + assign ex1_c_frac_pre[24] = (~(ex1_c_frac_pre1_b[24] & ex1_c_frac_pre2_b[24] & ex1_c_frac_pre3_b[24])); + assign ex1_c_frac_pre[25] = (~(ex1_c_frac_pre1_b[25] & ex1_c_frac_pre2_b[25] & ex1_c_frac_pre3_b[25])); + assign ex1_c_frac_pre[26] = (~(ex1_c_frac_pre1_b[26] & ex1_c_frac_pre2_b[26] & ex1_c_frac_pre3_b[26])); + assign ex1_c_frac_pre[27] = (~(ex1_c_frac_pre1_b[27] & ex1_c_frac_pre2_b[27] & ex1_c_frac_pre3_b[27])); + assign ex1_c_frac_pre[28] = (~(ex1_c_frac_pre1_b[28] & ex1_c_frac_pre2_b[28] & ex1_c_frac_pre3_b[28])); + assign ex1_c_frac_pre[29] = (~(ex1_c_frac_pre1_b[29] & ex1_c_frac_pre2_b[29] & ex1_c_frac_pre3_b[29])); + assign ex1_c_frac_pre[30] = (~(ex1_c_frac_pre1_b[30] & ex1_c_frac_pre2_b[30] & ex1_c_frac_pre3_b[30])); + assign ex1_c_frac_pre[31] = (~(ex1_c_frac_pre1_b[31] & ex1_c_frac_pre2_b[31] & ex1_c_frac_pre3_b[31])); + assign ex1_c_frac_pre[32] = (~(ex1_c_frac_pre1_b[32] & ex1_c_frac_pre2_b[32] & ex1_c_frac_pre3_b[32])); + assign ex1_c_frac_pre[33] = (~(ex1_c_frac_pre1_b[33] & ex1_c_frac_pre2_b[33] & ex1_c_frac_pre3_b[33])); + assign ex1_c_frac_pre[34] = (~(ex1_c_frac_pre1_b[34] & ex1_c_frac_pre2_b[34] & ex1_c_frac_pre3_b[34])); + assign ex1_c_frac_pre[35] = (~(ex1_c_frac_pre1_b[35] & ex1_c_frac_pre2_b[35] & ex1_c_frac_pre3_b[35])); + assign ex1_c_frac_pre[36] = (~(ex1_c_frac_pre1_b[36] & ex1_c_frac_pre2_b[36] & ex1_c_frac_pre3_b[36])); + assign ex1_c_frac_pre[37] = (~(ex1_c_frac_pre1_b[37] & ex1_c_frac_pre2_b[37] & ex1_c_frac_pre3_b[37])); + assign ex1_c_frac_pre[38] = (~(ex1_c_frac_pre1_b[38] & ex1_c_frac_pre2_b[38] & ex1_c_frac_pre3_b[38])); + assign ex1_c_frac_pre[39] = (~(ex1_c_frac_pre1_b[39] & ex1_c_frac_pre2_b[39] & ex1_c_frac_pre3_b[39])); + assign ex1_c_frac_pre[40] = (~(ex1_c_frac_pre1_b[40] & ex1_c_frac_pre2_b[40] & ex1_c_frac_pre3_b[40])); + assign ex1_c_frac_pre[41] = (~(ex1_c_frac_pre1_b[41] & ex1_c_frac_pre2_b[41] & ex1_c_frac_pre3_b[41])); + assign ex1_c_frac_pre[42] = (~(ex1_c_frac_pre1_b[42] & ex1_c_frac_pre2_b[42] & ex1_c_frac_pre3_b[42])); + assign ex1_c_frac_pre[43] = (~(ex1_c_frac_pre1_b[43] & ex1_c_frac_pre2_b[43] & ex1_c_frac_pre3_b[43])); + assign ex1_c_frac_pre[44] = (~(ex1_c_frac_pre1_b[44] & ex1_c_frac_pre2_b[44] & ex1_c_frac_pre3_b[44])); + assign ex1_c_frac_pre[45] = (~(ex1_c_frac_pre1_b[45] & ex1_c_frac_pre2_b[45] & ex1_c_frac_pre3_b[45])); + assign ex1_c_frac_pre[46] = (~(ex1_c_frac_pre1_b[46] & ex1_c_frac_pre2_b[46] & ex1_c_frac_pre3_b[46])); + assign ex1_c_frac_pre[47] = (~(ex1_c_frac_pre1_b[47] & ex1_c_frac_pre2_b[47] & ex1_c_frac_pre3_b[47])); + assign ex1_c_frac_pre[48] = (~(ex1_c_frac_pre1_b[48] & ex1_c_frac_pre2_b[48] & ex1_c_frac_pre3_b[48])); + assign ex1_c_frac_pre[49] = (~(ex1_c_frac_pre1_b[49] & ex1_c_frac_pre2_b[49] & ex1_c_frac_pre3_b[49])); + assign ex1_c_frac_pre[50] = (~(ex1_c_frac_pre1_b[50] & ex1_c_frac_pre2_b[50] & ex1_c_frac_pre3_b[50])); + assign ex1_c_frac_pre[51] = (~(ex1_c_frac_pre1_b[51] & ex1_c_frac_pre2_b[51] & ex1_c_frac_pre3_b[51])); + assign ex1_c_frac_pre[52] = (~(ex1_c_frac_pre1_b[52] & ex1_c_frac_pre2_b[52] & ex1_c_frac_pre3_b[52])); + + assign ex1_c_frac_pre_hulp = (~(ex1_c_frac_pre1_b[24] & ex1_c_frac_pre2_b[24] & ex1_c_frac_pre3_hulp_b)); + + assign ex1_b_frac_pre[0] = (~(ex1_b_frac_pre1_b[0] & ex1_b_frac_pre2_b[0] & ex1_b_frac_pre3_b[0])); + assign ex1_b_frac_pre[1] = (~(ex1_b_frac_pre1_b[1] & ex1_b_frac_pre2_b[1] & ex1_b_frac_pre3_b[1])); + assign ex1_b_frac_pre[2] = (~(ex1_b_frac_pre1_b[2] & ex1_b_frac_pre2_b[2])); + assign ex1_b_frac_pre[3] = (~(ex1_b_frac_pre1_b[3] & ex1_b_frac_pre2_b[3])); + assign ex1_b_frac_pre[4] = (~(ex1_b_frac_pre1_b[4] & ex1_b_frac_pre2_b[4])); + assign ex1_b_frac_pre[5] = (~(ex1_b_frac_pre1_b[5] & ex1_b_frac_pre2_b[5])); + assign ex1_b_frac_pre[6] = (~(ex1_b_frac_pre1_b[6] & ex1_b_frac_pre2_b[6])); + assign ex1_b_frac_pre[7] = (~(ex1_b_frac_pre1_b[7] & ex1_b_frac_pre2_b[7])); + assign ex1_b_frac_pre[8] = (~(ex1_b_frac_pre1_b[8] & ex1_b_frac_pre2_b[8])); + assign ex1_b_frac_pre[9] = (~(ex1_b_frac_pre1_b[9] & ex1_b_frac_pre2_b[9])); + assign ex1_b_frac_pre[10] = (~(ex1_b_frac_pre1_b[10] & ex1_b_frac_pre2_b[10])); + assign ex1_b_frac_pre[11] = (~(ex1_b_frac_pre1_b[11] & ex1_b_frac_pre2_b[11])); + assign ex1_b_frac_pre[12] = (~(ex1_b_frac_pre1_b[12] & ex1_b_frac_pre2_b[12])); + assign ex1_b_frac_pre[13] = (~(ex1_b_frac_pre1_b[13] & ex1_b_frac_pre2_b[13])); + assign ex1_b_frac_pre[14] = (~(ex1_b_frac_pre1_b[14] & ex1_b_frac_pre2_b[14])); + assign ex1_b_frac_pre[15] = (~(ex1_b_frac_pre1_b[15] & ex1_b_frac_pre2_b[15])); + assign ex1_b_frac_pre[16] = (~(ex1_b_frac_pre1_b[16] & ex1_b_frac_pre2_b[16])); + assign ex1_b_frac_pre[17] = (~(ex1_b_frac_pre1_b[17] & ex1_b_frac_pre2_b[17])); + assign ex1_b_frac_pre[18] = (~(ex1_b_frac_pre1_b[18] & ex1_b_frac_pre2_b[18])); + assign ex1_b_frac_pre[19] = (~(ex1_b_frac_pre1_b[19] & ex1_b_frac_pre2_b[19])); + assign ex1_b_frac_pre[20] = (~(ex1_b_frac_pre1_b[20] & ex1_b_frac_pre2_b[20])); + assign ex1_b_frac_pre[21] = (~(ex1_b_frac_pre1_b[21] & ex1_b_frac_pre2_b[21])); + assign ex1_b_frac_pre[22] = (~(ex1_b_frac_pre1_b[22] & ex1_b_frac_pre2_b[22])); + assign ex1_b_frac_pre[23] = (~(ex1_b_frac_pre1_b[23] & ex1_b_frac_pre2_b[23])); + assign ex1_b_frac_pre[24] = (~(ex1_b_frac_pre1_b[24] & ex1_b_frac_pre2_b[24])); + assign ex1_b_frac_pre[25] = (~(ex1_b_frac_pre1_b[25] & ex1_b_frac_pre2_b[25])); + assign ex1_b_frac_pre[26] = (~(ex1_b_frac_pre1_b[26] & ex1_b_frac_pre2_b[26])); + assign ex1_b_frac_pre[27] = (~(ex1_b_frac_pre1_b[27] & ex1_b_frac_pre2_b[27])); + assign ex1_b_frac_pre[28] = (~(ex1_b_frac_pre1_b[28] & ex1_b_frac_pre2_b[28])); + assign ex1_b_frac_pre[29] = (~(ex1_b_frac_pre1_b[29] & ex1_b_frac_pre2_b[29])); + assign ex1_b_frac_pre[30] = (~(ex1_b_frac_pre1_b[30] & ex1_b_frac_pre2_b[30])); + assign ex1_b_frac_pre[31] = (~(ex1_b_frac_pre1_b[31] & ex1_b_frac_pre2_b[31])); + assign ex1_b_frac_pre[32] = (~(ex1_b_frac_pre1_b[32] & ex1_b_frac_pre2_b[32])); + assign ex1_b_frac_pre[33] = (~(ex1_b_frac_pre1_b[33] & ex1_b_frac_pre2_b[33])); + assign ex1_b_frac_pre[34] = (~(ex1_b_frac_pre1_b[34] & ex1_b_frac_pre2_b[34])); + assign ex1_b_frac_pre[35] = (~(ex1_b_frac_pre1_b[35] & ex1_b_frac_pre2_b[35])); + assign ex1_b_frac_pre[36] = (~(ex1_b_frac_pre1_b[36] & ex1_b_frac_pre2_b[36])); + assign ex1_b_frac_pre[37] = (~(ex1_b_frac_pre1_b[37] & ex1_b_frac_pre2_b[37])); + assign ex1_b_frac_pre[38] = (~(ex1_b_frac_pre1_b[38] & ex1_b_frac_pre2_b[38])); + assign ex1_b_frac_pre[39] = (~(ex1_b_frac_pre1_b[39] & ex1_b_frac_pre2_b[39])); + assign ex1_b_frac_pre[40] = (~(ex1_b_frac_pre1_b[40] & ex1_b_frac_pre2_b[40])); + assign ex1_b_frac_pre[41] = (~(ex1_b_frac_pre1_b[41] & ex1_b_frac_pre2_b[41])); + assign ex1_b_frac_pre[42] = (~(ex1_b_frac_pre1_b[42] & ex1_b_frac_pre2_b[42])); + assign ex1_b_frac_pre[43] = (~(ex1_b_frac_pre1_b[43] & ex1_b_frac_pre2_b[43])); + assign ex1_b_frac_pre[44] = (~(ex1_b_frac_pre1_b[44] & ex1_b_frac_pre2_b[44])); + assign ex1_b_frac_pre[45] = (~(ex1_b_frac_pre1_b[45] & ex1_b_frac_pre2_b[45])); + assign ex1_b_frac_pre[46] = (~(ex1_b_frac_pre1_b[46] & ex1_b_frac_pre2_b[46])); + assign ex1_b_frac_pre[47] = (~(ex1_b_frac_pre1_b[47] & ex1_b_frac_pre2_b[47])); + assign ex1_b_frac_pre[48] = (~(ex1_b_frac_pre1_b[48] & ex1_b_frac_pre2_b[48])); + assign ex1_b_frac_pre[49] = (~(ex1_b_frac_pre1_b[49] & ex1_b_frac_pre2_b[49])); + assign ex1_b_frac_pre[50] = (~(ex1_b_frac_pre1_b[50] & ex1_b_frac_pre2_b[50])); + assign ex1_b_frac_pre[51] = (~(ex1_b_frac_pre1_b[51] & ex1_b_frac_pre2_b[51])); + assign ex1_b_frac_pre[52] = (~(ex1_b_frac_pre1_b[52] & ex1_b_frac_pre2_b[52])); + + assign ex1_s_frac_pre[0] = (~(ex1_s_frac_pre1_b[0] & ex1_s_frac_pre2_b[0])); + assign ex1_s_frac_pre[1] = (~(ex1_s_frac_pre1_b[1] & ex1_s_frac_pre2_b[1])); + assign ex1_s_frac_pre[2] = (~(ex1_s_frac_pre1_b[2] & ex1_s_frac_pre2_b[2])); + assign ex1_s_frac_pre[3] = (~(ex1_s_frac_pre1_b[3] & ex1_s_frac_pre2_b[3])); + assign ex1_s_frac_pre[4] = (~(ex1_s_frac_pre1_b[4] & ex1_s_frac_pre2_b[4])); + assign ex1_s_frac_pre[5] = (~(ex1_s_frac_pre1_b[5] & ex1_s_frac_pre2_b[5])); + assign ex1_s_frac_pre[6] = (~(ex1_s_frac_pre1_b[6] & ex1_s_frac_pre2_b[6])); + assign ex1_s_frac_pre[7] = (~(ex1_s_frac_pre1_b[7] & ex1_s_frac_pre2_b[7])); + assign ex1_s_frac_pre[8] = (~(ex1_s_frac_pre1_b[8] & ex1_s_frac_pre2_b[8])); + assign ex1_s_frac_pre[9] = (~(ex1_s_frac_pre1_b[9] & ex1_s_frac_pre2_b[9])); + assign ex1_s_frac_pre[10] = (~(ex1_s_frac_pre1_b[10] & ex1_s_frac_pre2_b[10])); + assign ex1_s_frac_pre[11] = (~(ex1_s_frac_pre1_b[11] & ex1_s_frac_pre2_b[11])); + assign ex1_s_frac_pre[12] = (~(ex1_s_frac_pre1_b[12] & ex1_s_frac_pre2_b[12])); + assign ex1_s_frac_pre[13] = (~(ex1_s_frac_pre1_b[13] & ex1_s_frac_pre2_b[13])); + assign ex1_s_frac_pre[14] = (~(ex1_s_frac_pre1_b[14] & ex1_s_frac_pre2_b[14])); + assign ex1_s_frac_pre[15] = (~(ex1_s_frac_pre1_b[15] & ex1_s_frac_pre2_b[15])); + assign ex1_s_frac_pre[16] = (~(ex1_s_frac_pre1_b[16] & ex1_s_frac_pre2_b[16])); + assign ex1_s_frac_pre[17] = (~(ex1_s_frac_pre1_b[17] & ex1_s_frac_pre2_b[17])); + assign ex1_s_frac_pre[18] = (~(ex1_s_frac_pre1_b[18] & ex1_s_frac_pre2_b[18])); + assign ex1_s_frac_pre[19] = (~(ex1_s_frac_pre1_b[19] & ex1_s_frac_pre2_b[19])); + assign ex1_s_frac_pre[20] = (~(ex1_s_frac_pre1_b[20] & ex1_s_frac_pre2_b[20])); + assign ex1_s_frac_pre[21] = (~(ex1_s_frac_pre1_b[21] & ex1_s_frac_pre2_b[21])); + assign ex1_s_frac_pre[22] = (~(ex1_s_frac_pre1_b[22] & ex1_s_frac_pre2_b[22])); + assign ex1_s_frac_pre[23] = (~(ex1_s_frac_pre1_b[23] & ex1_s_frac_pre2_b[23])); + assign ex1_s_frac_pre[24] = (~(ex1_s_frac_pre1_b[24] & ex1_s_frac_pre2_b[24])); + assign ex1_s_frac_pre[25] = (~(ex1_s_frac_pre1_b[25] & ex1_s_frac_pre2_b[25])); + assign ex1_s_frac_pre[26] = (~(ex1_s_frac_pre1_b[26] & ex1_s_frac_pre2_b[26])); + assign ex1_s_frac_pre[27] = (~(ex1_s_frac_pre1_b[27] & ex1_s_frac_pre2_b[27])); + assign ex1_s_frac_pre[28] = (~(ex1_s_frac_pre1_b[28] & ex1_s_frac_pre2_b[28])); + assign ex1_s_frac_pre[29] = (~(ex1_s_frac_pre1_b[29] & ex1_s_frac_pre2_b[29])); + assign ex1_s_frac_pre[30] = (~(ex1_s_frac_pre1_b[30] & ex1_s_frac_pre2_b[30])); + assign ex1_s_frac_pre[31] = (~(ex1_s_frac_pre1_b[31] & ex1_s_frac_pre2_b[31])); + assign ex1_s_frac_pre[32] = (~(ex1_s_frac_pre1_b[32] & ex1_s_frac_pre2_b[32])); + assign ex1_s_frac_pre[33] = (~(ex1_s_frac_pre1_b[33] & ex1_s_frac_pre2_b[33])); + assign ex1_s_frac_pre[34] = (~(ex1_s_frac_pre1_b[34] & ex1_s_frac_pre2_b[34])); + assign ex1_s_frac_pre[35] = (~(ex1_s_frac_pre1_b[35] & ex1_s_frac_pre2_b[35])); + assign ex1_s_frac_pre[36] = (~(ex1_s_frac_pre1_b[36] & ex1_s_frac_pre2_b[36])); + assign ex1_s_frac_pre[37] = (~(ex1_s_frac_pre1_b[37] & ex1_s_frac_pre2_b[37])); + assign ex1_s_frac_pre[38] = (~(ex1_s_frac_pre1_b[38] & ex1_s_frac_pre2_b[38])); + assign ex1_s_frac_pre[39] = (~(ex1_s_frac_pre1_b[39] & ex1_s_frac_pre2_b[39])); + assign ex1_s_frac_pre[40] = (~(ex1_s_frac_pre1_b[40] & ex1_s_frac_pre2_b[40])); + assign ex1_s_frac_pre[41] = (~(ex1_s_frac_pre1_b[41] & ex1_s_frac_pre2_b[41])); + assign ex1_s_frac_pre[42] = (~(ex1_s_frac_pre1_b[42] & ex1_s_frac_pre2_b[42])); + assign ex1_s_frac_pre[43] = (~(ex1_s_frac_pre1_b[43] & ex1_s_frac_pre2_b[43])); + assign ex1_s_frac_pre[44] = (~(ex1_s_frac_pre1_b[44] & ex1_s_frac_pre2_b[44])); + assign ex1_s_frac_pre[45] = (~(ex1_s_frac_pre1_b[45] & ex1_s_frac_pre2_b[45])); + assign ex1_s_frac_pre[46] = (~(ex1_s_frac_pre1_b[46] & ex1_s_frac_pre2_b[46])); + assign ex1_s_frac_pre[47] = (~(ex1_s_frac_pre1_b[47] & ex1_s_frac_pre2_b[47])); + assign ex1_s_frac_pre[48] = (~(ex1_s_frac_pre1_b[48] & ex1_s_frac_pre2_b[48])); + assign ex1_s_frac_pre[49] = (~(ex1_s_frac_pre1_b[49] & ex1_s_frac_pre2_b[49])); + assign ex1_s_frac_pre[50] = (~(ex1_s_frac_pre1_b[50] & ex1_s_frac_pre2_b[50])); + assign ex1_s_frac_pre[51] = (~(ex1_s_frac_pre1_b[51] & ex1_s_frac_pre2_b[51])); + assign ex1_s_frac_pre[52] = (~(ex1_s_frac_pre1_b[52] & ex1_s_frac_pre2_b[52])); + + assign ex1_a_frac_prebyp[0:52] = ex1_a_frac_pre[0:52]; // may need to manually repower + assign ex1_c_frac_prebyp[0:52] = ex1_c_frac_pre[0:52]; + assign ex1_b_frac_prebyp[0:52] = ex1_b_frac_pre[0:52]; + assign ex1_s_frac_prebyp[0:52] = ex1_s_frac_pre[0:52]; + assign ex1_c_frac_prebyp_hulp = ex1_c_frac_pre_hulp; + + assign ex1_a_sign_fpr = f_fpr_ex1_a_sign; // later on we may map in some inverters + assign ex1_c_sign_fpr = f_fpr_ex1_c_sign; + assign ex1_b_sign_fpr = f_fpr_ex1_b_sign; + assign ex1_s_sign_fpr = f_fpr_ex1_s_sign; + assign ex1_a_expo_fpr[1:13] = f_fpr_ex1_a_expo[1:13]; + assign ex1_c_expo_fpr[1:13] = f_fpr_ex1_c_expo[1:13]; + assign ex1_b_expo_fpr[1:13] = f_fpr_ex1_b_expo[1:13]; + assign ex1_s_expo_fpr[1:13] = {2'b00, f_fpr_ex1_s_expo[3:13]}; + assign ex1_a_frac_fpr[0:52] = f_fpr_ex1_a_frac[0:52]; + assign ex1_c_frac_fpr[0:52] = f_fpr_ex1_c_frac[0:52]; + assign ex1_b_frac_fpr[0:52] = f_fpr_ex1_b_frac[0:52]; + assign ex1_s_frac_fpr[0:52] = f_fpr_ex1_s_frac[0:52]; + + //--------------------------------------------------------------------------------------- + // for the last level, need a seperate copy for each latch for the pass gate rules + // (fpr is the late path ... so the mux is hierarchical to speed up that path) + //--------------------------------------------------------------------------------------- + + assign ex1_a_sign_fmt_b = (~((sel_a_no_byp_s & ex1_a_sign_fpr) | ex1_a_sign_prebyp)); + assign ex1_a_sign_pic_b = (~((sel_a_no_byp_s & ex1_a_sign_fpr) | ex1_a_sign_prebyp)); + assign ex1_c_sign_fmt_b = (~((sel_c_no_byp_s & ex1_c_sign_fpr) | ex1_c_sign_prebyp)); + assign ex1_c_sign_pic_b = (~((sel_c_no_byp_s & ex1_c_sign_fpr) | ex1_c_sign_prebyp)); + assign ex1_b_sign_fmt_b = (~((sel_b_no_byp_s & ex1_b_sign_fpr) | ex1_b_sign_prebyp)); + assign ex1_b_sign_pic_b = (~((sel_b_no_byp_s & ex1_b_sign_fpr) | ex1_b_sign_prebyp)); + assign ex1_b_sign_alg_b = (~((sel_b_no_byp_s & ex1_b_sign_fpr) | ex1_b_sign_prebyp)); + + assign ex1_a_expo_fmt_b[1:13] = (~(({13{sel_a_no_byp}} & ex1_a_expo_fpr[1:13]) | ex1_a_expo_prebyp[1:13])); + assign ex1_a_expo_eie_b[1:13] = (~(({13{sel_a_no_byp}} & ex1_a_expo_fpr[1:13]) | ex1_a_expo_prebyp[1:13])); + assign ex1_a_expo_alg_b[1:13] = (~(({13{sel_a_no_byp}} & ex1_a_expo_fpr[1:13]) | ex1_a_expo_prebyp[1:13])); + assign ex1_c_expo_fmt_b[1:13] = (~(({13{sel_c_no_byp}} & ex1_c_expo_fpr[1:13]) | ex1_c_expo_prebyp[1:13])); + assign ex1_c_expo_eie_b[1:13] = (~(({13{sel_c_no_byp}} & ex1_c_expo_fpr[1:13]) | ex1_c_expo_prebyp[1:13])); + assign ex1_c_expo_alg_b[1:13] = (~(({13{sel_c_no_byp}} & ex1_c_expo_fpr[1:13]) | ex1_c_expo_prebyp[1:13])); + assign ex1_b_expo_fmt_b[1:13] = (~(({13{sel_b_no_byp}} & ex1_b_expo_fpr[1:13]) | ex1_b_expo_prebyp[1:13])); + assign ex1_b_expo_eie_b[1:13] = (~(({13{sel_b_no_byp}} & ex1_b_expo_fpr[1:13]) | ex1_b_expo_prebyp[1:13])); + assign ex1_b_expo_alg_b[1:13] = (~(({13{sel_b_no_byp}} & ex1_b_expo_fpr[1:13]) | ex1_b_expo_prebyp[1:13])); + + assign ex1_a_frac_fmt_b[0:23] = (~(({24{sel_a_no_byp}} & ex1_a_frac_fpr[0:23]) | ex1_a_frac_prebyp[0:23])); + assign ex1_a_frac_mul_b[0:23] = (~(({24{sel_a_no_byp}} & ex1_a_frac_fpr[0:23]) | ex1_a_frac_prebyp[0:23])); + assign ex1_a_frac_mul_17_b = (~((sel_a_no_byp & ex1_a_frac_fpr[17]) | ex1_a_frac_prebyp[17])); + assign ex1_a_frac_fmt_b[24:52] = (~(({29{sel_a_no_byp}} & ex1_a_frac_fpr[24:52]) | ex1_a_frac_prebyp[24:52])); + assign ex1_a_frac_mul_b[24:52] = (~(({29{sel_a_no_byp}} & ex1_a_frac_fpr[24:52]) | ex1_a_frac_prebyp[24:52])); //SP/UNDEF and (24 to 52=> sel_a_dp )) ); + assign ex1_a_frac_mul_35_b = (~((sel_a_no_byp & ex1_a_frac_fpr[35]) | ex1_a_frac_prebyp[35])); //SP/UNDEF and sel_a_dp ) ); + + assign ex1_c_frac_fmt_b[0:23] = (~(({24{sel_c_no_byp}} & ex1_c_frac_fpr[0:23]) | ex1_c_frac_prebyp[0:23])); + assign ex1_c_frac_mul_b[0:23] = (~(({24{sel_c_no_byp}} & ex1_c_frac_fpr[0:23]) | ex1_c_frac_prebyp[0:23])); + + assign ex1_c_frac_fmt_b[24] = (~((sel_c_no_byp & ex1_c_frac_fpr[24]) | ex1_c_frac_prebyp[24])); + assign ex1_c_frac_mul_b[24] = (~((sel_c_no_byp & ex1_c_frac_fpr[24]) | ex1_c_frac_prebyp_hulp)); //SP/UNDEF and (24 to 52=> sel_c_dp )) ); + + assign ex1_c_frac_fmt_b[25:52] = (~(({28{sel_c_no_byp}} & ex1_c_frac_fpr[25:52]) | ex1_c_frac_prebyp[25:52])); + assign ex1_c_frac_mul_b[25:52] = (~(({28{sel_c_no_byp}} & ex1_c_frac_fpr[25:52]) | ex1_c_frac_prebyp[25:52])); //SP/UNDEF and (25 to 52=> sel_c_dp )) ); + assign ex1_c_frac_mul_b[53] = (~(f_dcd_ex1_uc_fc_hulp & (~f_dcd_ex1_sp))); + + assign ex1_b_frac_fmt_b[0:23] = (~(({24{sel_b_no_byp}} & ex1_b_frac_fpr[0:23]) | ex1_b_frac_prebyp[0:23])); + assign ex1_b_frac_alg_b[0:23] = (~(({24{sel_b_no_byp}} & ex1_b_frac_fpr[0:23]) | ex1_b_frac_prebyp[0:23])); + assign ex1_b_frac_fmt_b[24:52] = (~(({29{sel_b_no_byp}} & ex1_b_frac_fpr[24:52]) | ex1_b_frac_prebyp[24:52])); + assign ex1_b_frac_alg_b[24:52] = (~(({29{sel_b_no_byp}} & ex1_b_frac_fpr[24:52]) | ex1_b_frac_prebyp[24:52])); //SP/UNDEF ex1_b_frac_prebyp_dp(24 to 52) ); + + assign f_byp_ex1_s_sign = ((sel_s_no_byp_s & ex1_s_sign_fpr) | ex1_s_sign_prebyp); + assign f_byp_ex1_s_expo[3:13] = (({11{sel_s_no_byp}} & ex1_s_expo_fpr[3:13]) | ex1_s_expo_prebyp[3:13]); + assign f_byp_ex1_s_frac[0:23] = (({24{sel_s_no_byp}} & ex1_s_frac_fpr[0:23]) | ex1_s_frac_prebyp[0:23]); + assign f_byp_ex1_s_frac[24:52] = (({29{sel_s_no_byp}} & ex1_s_frac_fpr[24:52]) | ex1_s_frac_prebyp[24:52]); //SP/UNDEF ex1_b_frac_prebyp_dp(24 to 52) ); + + //==================================================================== + //== ex2 operand latches + //==================================================================== + + //---------------- FRACTION --------------------------------------- + + // force => tidn, + // --d_mode => tiup, + // delay_lclkr => tidn, + // mpw1_b => tidn, + // mpw2_b => tidn, + // nclk => nclk, + // act => ex1_act, + // thold_b => thold_0_b, + // sg => sg_0, + + + tri_inv_nlats #(.WIDTH(53), .NEEDS_SRESET(0)) ex2_frac_b_alg_lat( + .vd(vdd), + .gd(gnd), + .lclk(byp_ex2_lclk), //in --lclk.clk + .d1clk(byp_ex2_d1clk), //in + .d2clk(byp_ex2_d2clk), //in + .scanin(ex2_b_frac_si), //in + .scanout(ex2_b_frac_so), //in + .d(ex1_b_frac_alg_b[0:52]), //in + .qb(ex2_b_frac_alg[0:52]) //out + ); + + + tri_inv_nlats #(.WIDTH(53), .NEEDS_SRESET(0)) ex2_frac_a_fmt_lat( + .vd(vdd), + .gd(gnd), + .lclk(byp_ex2_lclk), //in --lclk.clk + .d1clk(byp_ex2_d1clk), //in + .d2clk(byp_ex2_d2clk), //in + .scanin(ex2_frac_a_fmt_si), //in + .scanout(ex2_frac_a_fmt_so), //in + .d(ex1_a_frac_fmt_b[0:52]), + .qb(ex2_a_frac_fmt[0:52]) + ); + + + tri_inv_nlats #(.WIDTH(53), .NEEDS_SRESET(0)) ex2_frac_c_fmt_lat( + .vd(vdd), + .gd(gnd), + .lclk(byp_ex2_lclk), //in --lclk.clk + .d1clk(byp_ex2_d1clk), //in + .d2clk(byp_ex2_d2clk), //in + .scanin(ex2_frac_c_fmt_si), //in + .scanout(ex2_frac_c_fmt_so), //in + .d(ex1_c_frac_fmt_b[0:52]), + .qb(ex2_c_frac_fmt[0:52]) + ); + + + tri_inv_nlats #(.WIDTH(53), .NEEDS_SRESET(0)) ex2_frac_b_fmt_lat( + .vd(vdd), + .gd(gnd), + .lclk(byp_ex2_lclk), //in --lclk.clk + .d1clk(byp_ex2_d1clk), //in + .d2clk(byp_ex2_d2clk), //in + .scanin(ex2_frac_b_fmt_si), //in + .scanout(ex2_frac_b_fmt_so), //in + .d(ex1_b_frac_fmt_b[0:52]), + .qb(ex2_b_frac_fmt[0:52]) + ); + + assign ex2_b_frac_alg_b[0:52] = (~ex2_b_frac_alg[0:52]); + assign ex2_b_frac_fmt_b[0:52] = (~ex2_b_frac_fmt[0:52]); + assign ex2_c_frac_fmt_b[0:52] = (~ex2_c_frac_fmt[0:52]); + assign ex2_a_frac_fmt_b[0:52] = (~ex2_a_frac_fmt[0:52]); + + assign temp_ex1_c_frac_mul[0:53] = (~ex1_c_frac_mul_b[0:53]); + assign temp_ex1_a_frac_mul[0:52] = (~ex1_a_frac_mul_b[0:52]); + assign temp_ex1_a_frac_mul_17 = (~ex1_a_frac_mul_17_b); + assign temp_ex1_a_frac_mul_35 = (~ex1_a_frac_mul_35_b); + + + tri_inv_nlats #(.WIDTH(54), .NEEDS_SRESET(0)) ex2_frac_c_mul_lat( + .vd(vdd), + .gd(gnd), + .lclk(byp_ex2_lclk), //in --lclk.clk + .d1clk(byp_ex2_d1clk), //in + .d2clk(byp_ex2_d2clk), //in + .scanin(frac_mul_c_si), //in + .scanout(frac_mul_c_so), //in + .d({temp_ex1_c_frac_mul[0:52], //in + temp_ex1_c_frac_mul[53]}), //in -- f_dcd_ex1_uc_fc_hulp, + .qb(ex2_c_frac_mul_b[0:53]) //out + ); + + + tri_inv_nlats #(.WIDTH(55), .NEEDS_SRESET(0)) ex2_frac_a_mul_lat( + .vd(vdd), + .gd(gnd), + .lclk(byp_ex2_lclk), //in --lclk.clk + .d1clk(byp_ex2_d1clk), //in + .d2clk(byp_ex2_d2clk), //in + .scanin(frac_mul_a_si), //in + .scanout(frac_mul_a_so), //in + .d({ temp_ex1_a_frac_mul[0], + temp_ex1_a_frac_mul[17], + temp_ex1_a_frac_mul[35], + temp_ex1_a_frac_mul[1], + temp_ex1_a_frac_mul[18], + temp_ex1_a_frac_mul[36], + temp_ex1_a_frac_mul[2], + temp_ex1_a_frac_mul[19], + temp_ex1_a_frac_mul[37], + temp_ex1_a_frac_mul[3], + temp_ex1_a_frac_mul[20], + temp_ex1_a_frac_mul[38], + temp_ex1_a_frac_mul[4], + temp_ex1_a_frac_mul[21], + temp_ex1_a_frac_mul[39], + temp_ex1_a_frac_mul[5], + temp_ex1_a_frac_mul[22], + temp_ex1_a_frac_mul[40], + temp_ex1_a_frac_mul[6], + temp_ex1_a_frac_mul[23], + temp_ex1_a_frac_mul[41], + temp_ex1_a_frac_mul[7], + temp_ex1_a_frac_mul[24], + temp_ex1_a_frac_mul[42], + temp_ex1_a_frac_mul[8], + temp_ex1_a_frac_mul[25], + temp_ex1_a_frac_mul[43], + temp_ex1_a_frac_mul[9], + temp_ex1_a_frac_mul[26], + temp_ex1_a_frac_mul[44], + temp_ex1_a_frac_mul[10], + temp_ex1_a_frac_mul[27], + temp_ex1_a_frac_mul[45], + temp_ex1_a_frac_mul[11], + temp_ex1_a_frac_mul[28], + temp_ex1_a_frac_mul[46], + temp_ex1_a_frac_mul[12], + temp_ex1_a_frac_mul[29], + temp_ex1_a_frac_mul[47], + temp_ex1_a_frac_mul[13], + temp_ex1_a_frac_mul[30], + temp_ex1_a_frac_mul[48], + temp_ex1_a_frac_mul[14], + temp_ex1_a_frac_mul[31], + temp_ex1_a_frac_mul[49], + temp_ex1_a_frac_mul[15], + temp_ex1_a_frac_mul[32], + temp_ex1_a_frac_mul[50], + temp_ex1_a_frac_mul[16], + temp_ex1_a_frac_mul[33], + temp_ex1_a_frac_mul[51], + temp_ex1_a_frac_mul_17, // copy of 17 for bit stacking + temp_ex1_a_frac_mul[34], + temp_ex1_a_frac_mul[52], + temp_ex1_a_frac_mul_35}), // copy of 35 for bit stacking + //---------------------------------------- + .qb({ ex2_a_frac_mul_b[0], + ex2_a_frac_mul_b[17], // real copy of bit 17 + ex2_a_frac_mul_b[35], // real copy of bit 35 + ex2_a_frac_mul_b[1], + ex2_a_frac_mul_b[18], + ex2_a_frac_mul_b[36], + ex2_a_frac_mul_b[2], + ex2_a_frac_mul_b[19], + ex2_a_frac_mul_b[37], + ex2_a_frac_mul_b[3], + ex2_a_frac_mul_b[20], + ex2_a_frac_mul_b[38], + ex2_a_frac_mul_b[4], + ex2_a_frac_mul_b[21], + ex2_a_frac_mul_b[39], + ex2_a_frac_mul_b[5], + ex2_a_frac_mul_b[22], + ex2_a_frac_mul_b[40], + ex2_a_frac_mul_b[6], + ex2_a_frac_mul_b[23], + ex2_a_frac_mul_b[41], + ex2_a_frac_mul_b[7], + ex2_a_frac_mul_b[24], + ex2_a_frac_mul_b[42], + ex2_a_frac_mul_b[8], + ex2_a_frac_mul_b[25], + ex2_a_frac_mul_b[43], + ex2_a_frac_mul_b[9], + ex2_a_frac_mul_b[26], + ex2_a_frac_mul_b[44], + ex2_a_frac_mul_b[10], + ex2_a_frac_mul_b[27], + ex2_a_frac_mul_b[45], + ex2_a_frac_mul_b[11], + ex2_a_frac_mul_b[28], + ex2_a_frac_mul_b[46], + ex2_a_frac_mul_b[12], + ex2_a_frac_mul_b[29], + ex2_a_frac_mul_b[47], + ex2_a_frac_mul_b[13], + ex2_a_frac_mul_b[30], + ex2_a_frac_mul_b[48], + ex2_a_frac_mul_b[14], + ex2_a_frac_mul_b[31], + ex2_a_frac_mul_b[49], + ex2_a_frac_mul_b[15], + ex2_a_frac_mul_b[32], + ex2_a_frac_mul_b[50], + ex2_a_frac_mul_b[16], + ex2_a_frac_mul_b[33], + ex2_a_frac_mul_b[51], + ex2_a_frac_mul_17_b, // copy of 17 for bit stacking + ex2_a_frac_mul_b[34], + ex2_a_frac_mul_b[52], + ex2_a_frac_mul_35_b}) // copy of 35 for bit stacking + ); + + assign f_byp_alg_ex2_b_frac[0:52] = (~ex2_b_frac_alg_b[0:52]); + assign f_byp_fmt_ex2_a_frac[0:52] = (~ex2_a_frac_fmt_b[0:52]); + assign f_byp_fmt_ex2_c_frac[0:52] = (~ex2_c_frac_fmt_b[0:52]); + assign f_byp_fmt_ex2_b_frac[0:52] = (~ex2_b_frac_fmt_b[0:52]); + assign f_byp_mul_ex2_a_frac[0:52] = (~ex2_a_frac_mul_b[0:52]); + assign f_byp_mul_ex2_a_frac_17 = (~ex2_a_frac_mul_17_b); + assign f_byp_mul_ex2_a_frac_35 = (~ex2_a_frac_mul_35_b); + assign f_byp_mul_ex2_c_frac[0:53] = (~ex2_c_frac_mul_b[0:53]); + + //---------------- EXPONENT SIGN ---------------------------------- + + + tri_inv_nlats #(.WIDTH(14), .NEEDS_SRESET(0)) ex2_expo_b_alg_lat( + .vd(vdd), + .gd(gnd), + .lclk(byp_ex2_lclk), //in --lclk.clk + .d1clk(byp_ex2_d1clk), //in + .d2clk(byp_ex2_d2clk), //in + .scanin(ex2_expo_b_alg_si), //in + .scanout(ex2_expo_b_alg_so), //in + .d({ex1_b_sign_alg_b, + ex1_b_expo_alg_b[1:13]}), + .qb({ex2_b_sign_alg, + ex2_b_expo_alg[1:13]}) + ); + + + tri_inv_nlats #(.WIDTH(13), .NEEDS_SRESET(0)) ex2_expo_c_alg_lat( + .vd(vdd), + .gd(gnd), + .lclk(byp_ex2_lclk), //in --lclk.clk + .d1clk(byp_ex2_d1clk), //in + .d2clk(byp_ex2_d2clk), //in + .scanin(ex2_expo_c_alg_si), //in + .scanout(ex2_expo_c_alg_so), //in + .d(ex1_c_expo_alg_b[1:13]), + .qb(ex2_c_expo_alg[1:13]) + ); + + + tri_inv_nlats #(.WIDTH(13), .NEEDS_SRESET(0)) ex2_expo_a_alg_lat( + .vd(vdd), + .gd(gnd), + .lclk(byp_ex2_lclk), //in --lclk.clk + .d1clk(byp_ex2_d1clk), //in + .d2clk(byp_ex2_d2clk), //in + .scanin(ex2_expo_a_alg_si), //in + .scanout(ex2_expo_a_alg_so), //in + .d(ex1_a_expo_alg_b[1:13]), + .qb(ex2_a_expo_alg[1:13]) + ); + + + tri_inv_nlats #(.WIDTH(14), .NEEDS_SRESET(0)) ex2_expo_b_fmt_lat( + .vd(vdd), + .gd(gnd), + .lclk(byp_ex2_lclk), //in --lclk.clk + .d1clk(byp_ex2_d1clk), //in + .d2clk(byp_ex2_d2clk), //in + .scanin(ex2_expo_b_fmt_si), //in + .scanout(ex2_expo_b_fmt_so), //in + .d({ex1_b_sign_fmt_b, + ex1_b_expo_fmt_b[1:13]}), + .qb({ex2_b_sign_fmt, + ex2_b_expo_fmt[1:13]}) + ); + + + tri_inv_nlats #(.WIDTH(14), .NEEDS_SRESET(0)) ex2_expo_a_fmt_lat( + .vd(vdd), + .gd(gnd), + .lclk(byp_ex2_lclk), //in --lclk.clk + .d1clk(byp_ex2_d1clk), //in + .d2clk(byp_ex2_d2clk), //in + .scanin(ex2_expo_a_fmt_si), //in + .scanout(ex2_expo_a_fmt_so), //in + .d({ex1_a_sign_fmt_b, + ex1_a_expo_fmt_b[1:13]}), + .qb({ex2_a_sign_fmt, + ex2_a_expo_fmt[1:13]}) + ); + + + tri_inv_nlats #(.WIDTH(14), .NEEDS_SRESET(0)) ex2_expo_c_fmt_lat( + .vd(vdd), + .gd(gnd), + .lclk(byp_ex2_lclk), //in --lclk.clk + .d1clk(byp_ex2_d1clk), //in + .d2clk(byp_ex2_d2clk), //in + .scanin(ex2_expo_c_fmt_si), //in + .scanout(ex2_expo_c_fmt_so), //in + .d({ex1_c_sign_fmt_b, + ex1_c_expo_fmt_b[1:13]}), + .qb({ex2_c_sign_fmt, + ex2_c_expo_fmt[1:13]}) + ); + + + tri_inv_nlats #(.WIDTH(14), .NEEDS_SRESET(0)) ex2_expo_b_eie_lat( + .vd(vdd), + .gd(gnd), + .lclk(byp_ex2_lclk), //in --lclk.clk + .d1clk(byp_ex2_d1clk), //in + .d2clk(byp_ex2_d2clk), //in + .scanin(ex2_expo_b_eie_si), //in + .scanout(ex2_expo_b_eie_so), //in + .d({ex1_b_sign_pic_b, + ex1_b_expo_eie_b[1:13]}), + .qb({ex2_b_sign_pic, + ex2_b_expo_eie[1:13]}) + ); + + + tri_inv_nlats #(.WIDTH(14),.NEEDS_SRESET(0)) ex2_expo_a_eie_lat( + .vd(vdd), + .gd(gnd), + .lclk(byp_ex2_lclk), //in --lclk.clk + .d1clk(byp_ex2_d1clk), //in + .d2clk(byp_ex2_d2clk), //in + .scanin(ex2_expo_a_eie_si), //in + .scanout(ex2_expo_a_eie_so), //in + .d({ex1_a_sign_pic_b, + ex1_a_expo_eie_b[1:13]}), + .qb({ex2_a_sign_pic, + ex2_a_expo_eie[1:13]}) + ); + + + tri_inv_nlats #(.WIDTH(14), .NEEDS_SRESET(0)) ex2_expo_c_eie_lat( + .vd(vdd), + .gd(gnd), + .lclk(byp_ex2_lclk), //in --lclk.clk + .d1clk(byp_ex2_d1clk), //in + .d2clk(byp_ex2_d2clk), //in + .scanin(ex2_expo_c_eie_si), //in + .scanout(ex2_expo_c_eie_so), //in + .d({ex1_c_sign_pic_b, + ex1_c_expo_eie_b[1:13]}), + .qb({ex2_c_sign_pic, + ex2_c_expo_eie[1:13]}) + ); + + assign ex2_b_sign_alg_b = (~ex2_b_sign_alg); + assign ex2_b_sign_fmt_b = (~ex2_b_sign_fmt); + assign ex2_a_sign_fmt_b = (~ex2_a_sign_fmt); + assign ex2_c_sign_fmt_b = (~ex2_c_sign_fmt); + assign ex2_b_sign_pic_b = (~ex2_b_sign_pic); + assign ex2_a_sign_pic_b = (~ex2_a_sign_pic); + assign ex2_c_sign_pic_b = (~ex2_c_sign_pic); + + assign ex2_b_expo_alg_b[1:13] = (~ex2_b_expo_alg[1:13]); + assign ex2_c_expo_alg_b[1:13] = (~ex2_c_expo_alg[1:13]); + assign ex2_a_expo_alg_b[1:13] = (~ex2_a_expo_alg[1:13]); + assign ex2_b_expo_fmt_b[1:13] = (~ex2_b_expo_fmt[1:13]); + assign ex2_c_expo_fmt_b[1:13] = (~ex2_c_expo_fmt[1:13]); + assign ex2_a_expo_fmt_b[1:13] = (~ex2_a_expo_fmt[1:13]); + assign ex2_b_expo_eie_b[1:13] = (~ex2_b_expo_eie[1:13]); + assign ex2_c_expo_eie_b[1:13] = (~ex2_c_expo_eie[1:13]); + assign ex2_a_expo_eie_b[1:13] = (~ex2_a_expo_eie[1:13]); + + assign f_byp_alg_ex2_b_sign = (~ex2_b_sign_alg_b); + assign f_byp_alg_ex2_b_expo[1:13] = (~ex2_b_expo_alg_b[1:13]); + assign f_byp_alg_ex2_c_expo[1:13] = (~ex2_c_expo_alg_b[1:13]); + assign f_byp_alg_ex2_a_expo[1:13] = (~ex2_a_expo_alg_b[1:13]); + + assign f_byp_fmt_ex2_a_sign = (~ex2_a_sign_fmt_b); + assign f_byp_fmt_ex2_a_expo[1:13] = (~ex2_a_expo_fmt_b[1:13]); + assign f_byp_fmt_ex2_c_sign = (~ex2_c_sign_fmt_b); + assign f_byp_fmt_ex2_c_expo[1:13] = (~ex2_c_expo_fmt_b[1:13]); + assign f_byp_fmt_ex2_b_sign = (~ex2_b_sign_fmt_b); + assign f_byp_fmt_ex2_b_expo[1:13] = (~ex2_b_expo_fmt_b[1:13]); + + assign f_byp_pic_ex2_a_sign = (~ex2_a_sign_pic_b); + assign f_byp_eie_ex2_a_expo[1:13] = (~ex2_a_expo_eie_b[1:13]); + assign f_byp_pic_ex2_c_sign = (~ex2_c_sign_pic_b); + assign f_byp_eie_ex2_c_expo[1:13] = (~ex2_c_expo_eie_b[1:13]); + assign f_byp_pic_ex2_b_sign = (~ex2_b_sign_pic_b); + assign f_byp_eie_ex2_b_expo[1:13] = (~ex2_b_expo_eie_b[1:13]); + + //==================================================================== + //== scan chain + //==================================================================== + + assign act_si[0:3] = {act_so[1:3], f_byp_si}; + assign ex2_b_frac_si[0:52] = {ex2_b_frac_so[1:52], act_so[0]}; + assign ex2_frac_a_fmt_si[0:52] = {ex2_frac_a_fmt_so[1:52], ex2_b_frac_so[0]}; + assign ex2_frac_c_fmt_si[0:52] = {ex2_frac_c_fmt_so[1:52], ex2_frac_a_fmt_so[0]}; + assign ex2_frac_b_fmt_si[0:52] = {ex2_frac_b_fmt_so[1:52], ex2_frac_c_fmt_so[0]}; + assign frac_mul_c_si[0:53] = {frac_mul_c_so[1:53], ex2_frac_b_fmt_so[0]}; + assign frac_mul_a_si[0:54] = {frac_mul_a_so[1:54], frac_mul_c_so[0]}; + assign ex2_expo_a_eie_si[0:13] = {ex2_expo_a_eie_so[1:13], frac_mul_a_so[0]}; + assign ex2_expo_c_eie_si[0:13] = {ex2_expo_c_eie_so[1:13], ex2_expo_a_eie_so[0]}; + assign ex2_expo_b_eie_si[0:13] = {ex2_expo_b_eie_so[1:13], ex2_expo_c_eie_so[0]}; + assign ex2_expo_a_fmt_si[0:13] = {ex2_expo_a_fmt_so[1:13], ex2_expo_b_eie_so[0]}; + assign ex2_expo_c_fmt_si[0:13] = {ex2_expo_c_fmt_so[1:13], ex2_expo_a_fmt_so[0]}; + assign ex2_expo_b_fmt_si[0:13] = {ex2_expo_b_fmt_so[1:13], ex2_expo_c_fmt_so[0]}; + assign ex2_expo_b_alg_si[0:13] = {ex2_expo_b_alg_so[1:13], ex2_expo_b_fmt_so[0]}; + assign ex2_expo_a_alg_si[0:12] = {ex2_expo_a_alg_so[1:12], ex2_expo_b_alg_so[0]}; + assign ex2_expo_c_alg_si[0:12] = {ex2_expo_c_alg_so[1:12], ex2_expo_a_alg_so[0]}; + assign f_byp_so = ex2_expo_c_alg_so[0]; + +endmodule diff --git a/dev/verilog/work/fu_cr2.v b/dev/verilog/work/fu_cr2.v new file mode 100755 index 0000000..9118640 --- /dev/null +++ b/dev/verilog/work/fu_cr2.v @@ -0,0 +1,871 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// FPSCR BIT DEFINITIONS +// -------------- control +// [24] ve +// [25] oe +// [26] ue +// [27] ze +// [28] xe +// [29] non-ieee +// [30:31] rnd_mode 00:nr 01:zr 02:pi 03:ni +// +// the rnd_mode must be read in ex3 of the using op +// the rnd_mode is set in ex4 of the sending op (to_integer only) +// there must be a 2 cycle bubble after update op +// +// set 1 2 3 +// read x x 1 2 + + `include "tri_a2o.vh" + +module fu_cr2( + vdd, + gnd, + clkoff_b, + act_dis, + flush, + delay_lclkr, + mpw1_b, + mpw2_b, + sg_1, + thold_1, + fpu_enable, + nclk, + f_cr2_si, + f_cr2_so, + ex1_act, + ex2_act, + ex1_thread_b, + f_dcd_ex7_cancel, + f_fmt_ex2_bop_byt, + f_dcd_ex1_fpscr_bit_data_b, + f_dcd_ex1_fpscr_bit_mask_b, + f_dcd_ex1_fpscr_nib_mask_b, + f_dcd_ex1_mtfsbx_b, + f_dcd_ex1_mcrfs_b, + f_dcd_ex1_mtfsf_b, + f_dcd_ex1_mtfsfi_b, + f_cr2_ex4_thread_b, + f_cr2_ex4_fpscr_bit_data_b, + f_cr2_ex4_fpscr_bit_mask_b, + f_cr2_ex4_fpscr_nib_mask_b, + f_cr2_ex4_mtfsbx_b, + f_cr2_ex4_mcrfs_b, + f_cr2_ex4_mtfsf_b, + f_cr2_ex4_mtfsfi_b, + f_cr2_ex6_fpscr_rd_dat, + f_cr2_ex7_fpscr_rd_dat, + f_cr2_ex2_fpscr_shadow +); + + inout vdd; + inout gnd; + input clkoff_b; // tiup + input act_dis; // ??tidn?? + input flush; // ??tidn?? + input [1:7] delay_lclkr; // tidn, + input [1:7] mpw1_b; // tidn, + input [0:1] mpw2_b; // tidn, + input sg_1; + input thold_1; + input fpu_enable; //dc_act + input [0:`NCLK_WIDTH-1] nclk; + + input f_cr2_si; // perv + output f_cr2_so; // perv + input ex1_act; // act writes + input ex2_act; // act writes + + input [0:3] ex1_thread_b; // thread write + input f_dcd_ex7_cancel; + + input [45:52] f_fmt_ex2_bop_byt; //for mtfsf to shadow reg + input [0:3] f_dcd_ex1_fpscr_bit_data_b; //data to write to nibble (other than mtfsf) + input [0:3] f_dcd_ex1_fpscr_bit_mask_b; //enable update of bit within the nibble + input [0:8] f_dcd_ex1_fpscr_nib_mask_b; //enable update of this nibble + input f_dcd_ex1_mtfsbx_b; //fpscr set bit, reset bit + input f_dcd_ex1_mcrfs_b; //move fpscr field to cr and reset exceptions + input f_dcd_ex1_mtfsf_b; //move fpr data to fpscr + input f_dcd_ex1_mtfsfi_b; //move immediate data to fpscr + + output [0:3] f_cr2_ex4_thread_b; //scr + output [0:3] f_cr2_ex4_fpscr_bit_data_b; //data to write to nibble (other than mtfsf) + output [0:3] f_cr2_ex4_fpscr_bit_mask_b; //enable update of bit within the nibble + output [0:8] f_cr2_ex4_fpscr_nib_mask_b; //enable update of this nibble + output f_cr2_ex4_mtfsbx_b; //fpscr set bit, reset bit + output f_cr2_ex4_mcrfs_b; //move fpscr field to cr and reset exceptions + output f_cr2_ex4_mtfsf_b; //move fpr data to fpscr + output f_cr2_ex4_mtfsfi_b; //move immediate data to fpscr + + output [24:31] f_cr2_ex6_fpscr_rd_dat; //scr + output [24:31] f_cr2_ex7_fpscr_rd_dat; //scr + output [0:7] f_cr2_ex2_fpscr_shadow; //fpic + + // end ports + + // ENTITY + + + parameter tiup = 1'b1; + parameter tidn = 1'b0; + + wire sg_0; + wire thold_0_b; + wire thold_0; + wire force_t; + wire ex7_th0_act; + wire ex7_th1_act; + wire ex7_th2_act; + wire ex7_th3_act; + + wire ex3_act; + wire ex4_act; + wire ex5_act; + wire ex6_act; + wire ex7_act; + wire ex5_mv_to_op; + wire ex6_mv_to_op; + wire ex7_mv_to_op; + + wire [0:3] ex2_thread; + wire [0:3] ex3_thread; + wire [0:3] ex4_thread; + wire [0:3] ex5_thread; + wire [0:3] ex6_thread; + wire [0:3] ex7_thread; + + (* analysis_not_referenced="TRUE" *) + wire [0:2] act_spare_unused; + //----------------- + wire [0:6] act_so; //SCAN + wire [0:6] act_si; + wire [0:33] ex2_ctl_so; //SCAN + wire [0:33] ex2_ctl_si; + wire [0:24] ex3_ctl_so; //SCAN + wire [0:24] ex3_ctl_si; + wire [0:24] ex4_ctl_so; //SCAN + wire [0:24] ex4_ctl_si; + wire [0:4] ex5_ctl_so; //SCAN + wire [0:4] ex5_ctl_si; + wire [0:4] ex6_ctl_so; //SCAN + wire [0:4] ex6_ctl_si; + wire [0:4] ex7_ctl_so; //SCAN + wire [0:4] ex7_ctl_si; + wire [0:7] shadow0_so; //SCAN + wire [0:7] shadow0_si; + wire [0:7] shadow1_so; //SCAN + wire [0:7] shadow1_si; + wire [0:7] shadow2_so; //SCAN + wire [0:7] shadow2_si; + wire [0:7] shadow3_so; //SCAN + wire [0:7] shadow3_si; + wire [0:7] shadow_byp2_so; //SCAN + wire [0:7] shadow_byp2_si; + wire [0:7] shadow_byp3_so; //SCAN + wire [0:7] shadow_byp3_si; + wire [0:7] shadow_byp4_so; //SCAN + wire [0:7] shadow_byp4_si; + wire [0:7] shadow_byp5_so; //SCAN + wire [0:7] shadow_byp5_si; + wire [0:7] shadow_byp6_so; //SCAN + wire [0:7] shadow_byp6_si; + //----------------- + wire [0:7] shadow0; + wire [0:7] shadow1; + wire [0:7] shadow2; + wire [0:7] shadow3; + wire [0:7] shadow_byp2; + wire [0:7] shadow_byp3; + wire [0:7] shadow_byp4; + wire [0:7] shadow_byp5; + wire [0:7] shadow_byp6; + wire [0:7] shadow_byp2_din; + + wire [0:7] ex2_bit_sel; + wire [0:3] ex2_fpscr_bit_data; + wire [0:3] ex2_fpscr_bit_mask; + wire [0:8] ex2_fpscr_nib_mask; + wire ex2_mtfsbx; + wire ex2_mcrfs; + wire ex2_mtfsf; + wire ex2_mtfsfi; + wire [0:3] ex3_fpscr_bit_data; + wire [0:3] ex3_fpscr_bit_mask; + wire [0:8] ex3_fpscr_nib_mask; + wire ex3_mtfsbx; + wire ex3_mcrfs; + wire ex3_mtfsf; + wire ex3_mtfsfi; + + wire [0:3] ex4_fpscr_bit_data; + wire [0:3] ex4_fpscr_bit_mask; + wire [0:8] ex4_fpscr_nib_mask; + wire ex4_mtfsbx; + wire ex4_mcrfs; + wire ex4_mtfsf; + wire ex4_mtfsfi; + wire ex2_mv_to_op; + wire ex3_mv_to_op; + wire ex4_mv_to_op; + wire [0:7] ex2_fpscr_data; + wire [0:3] ex1_thread; + wire ex1_rd_sel_0; + wire ex2_rd_sel_0; + wire ex1_rd_sel_1; + wire ex2_rd_sel_1; + wire ex1_rd_sel_2; + wire ex2_rd_sel_2; + wire ex1_rd_sel_3; + wire ex2_rd_sel_3; + wire ex1_rd_sel_byp2; + wire ex2_rd_sel_byp2; + wire ex1_rd_sel_byp3; + wire ex2_rd_sel_byp3; + wire ex1_rd_sel_byp4; + wire ex2_rd_sel_byp4; + wire ex1_rd_sel_byp5; + wire ex2_rd_sel_byp5; + wire ex1_rd_sel_byp6; + wire ex2_rd_sel_byp6; + + wire ex1_rd_sel_byp2_pri; + wire ex1_rd_sel_byp3_pri; + wire ex1_rd_sel_byp4_pri; + wire ex1_rd_sel_byp5_pri; + wire ex1_rd_sel_byp6_pri; + + wire [0:7] ex2_fpscr_shadow_mux; + wire ex1_thread_match_1; + wire ex1_thread_match_2; + wire ex1_thread_match_3; + wire ex1_thread_match_4; + wire ex1_thread_match_5; + wire [0:3] ex1_fpscr_bit_data; + wire [0:3] ex1_fpscr_bit_mask; + wire [0:8] ex1_fpscr_nib_mask; + wire ex1_mtfsbx; + wire ex1_mcrfs; + wire ex1_mtfsf; + wire ex1_mtfsfi; + wire ex7_cancel; + wire [24:31] ex7_fpscr_rd_dat_no_byp; + + ////############################################ + ////# pervasive + ////############################################ + + + tri_plat thold_reg_0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(flush), + .din(thold_1), + .q(thold_0) + ); + + + tri_plat sg_reg_0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(flush), + .din(sg_1), + .q(sg_0) + ); + + + tri_lcbor lcbor_0( + .clkoff_b(clkoff_b), + .thold(thold_0), + .sg(sg_0), + .act_dis(act_dis), + .force_t(force_t), + .thold_b(thold_0_b) + ); + + ////############################################ + ////# ACT LATCHES + ////############################################ + + + + tri_rlmreg_p #(.WIDTH(7), .NEEDS_SRESET(0)) act_lat( + .force_t(force_t), // tidn, + .d_mode(tiup), + .delay_lclkr(delay_lclkr[6]), // tidn, + .mpw1_b(mpw1_b[6]), // tidn, + .mpw2_b(mpw2_b[1]), // tidn, + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + .act(fpu_enable), + .scout(act_so), + .scin(act_si), + //--------------- + .din({ act_spare_unused[0], + act_spare_unused[1], + ex2_act, + ex3_act, + ex4_act, + ex5_act, + ex6_act}), + //----------------- + .dout({ act_spare_unused[0], + act_spare_unused[1], + ex3_act, + ex4_act, + ex5_act, + ex6_act, + ex7_act}) + ); + + + assign act_spare_unused[2] = ex1_act; // take this out? + + ////############################################# + ////## ex2 latches + ////############################################# + + assign ex1_thread[0:3] = (~ex1_thread_b[0:3]); + assign ex1_fpscr_bit_data[0:3] = (~f_dcd_ex1_fpscr_bit_data_b[0:3]); + assign ex1_fpscr_bit_mask[0:3] = (~f_dcd_ex1_fpscr_bit_mask_b[0:3]); + assign ex1_fpscr_nib_mask[0:8] = (~f_dcd_ex1_fpscr_nib_mask_b[0:8]); + assign ex1_mtfsbx = (~f_dcd_ex1_mtfsbx_b); + assign ex1_mcrfs = (~f_dcd_ex1_mcrfs_b); + assign ex1_mtfsf = (~f_dcd_ex1_mtfsf_b); + assign ex1_mtfsfi = (~f_dcd_ex1_mtfsfi_b); + + + tri_rlmreg_p #(.WIDTH(34)) ex2_ctl_lat( + .force_t(force_t), // tidn, + .d_mode(tiup), + .delay_lclkr(delay_lclkr[1]), // tidn, + .mpw1_b(mpw1_b[1]), // tidn, + .mpw2_b(mpw2_b[0]), // tidn, + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + .act(fpu_enable), //ex1_act + .scout(ex2_ctl_so), + .scin(ex2_ctl_si), + //----------------- + .din({ ex1_thread[0:3], + ex1_fpscr_bit_data[0:3], + ex1_fpscr_bit_mask[0:3], + ex1_fpscr_nib_mask[0:8], + ex1_mtfsbx, + ex1_mcrfs, + ex1_mtfsf, + ex1_mtfsfi, + ex1_rd_sel_0, + ex1_rd_sel_1, + ex1_rd_sel_2, + ex1_rd_sel_3, + ex1_rd_sel_byp2_pri, + ex1_rd_sel_byp3_pri, + ex1_rd_sel_byp4_pri, + ex1_rd_sel_byp5_pri, + ex1_rd_sel_byp6_pri}), + //----------------- + .dout({ ex2_thread[0:3], + ex2_fpscr_bit_data[0:3], + ex2_fpscr_bit_mask[0:3], + ex2_fpscr_nib_mask[0:8], + ex2_mtfsbx, + ex2_mcrfs, + ex2_mtfsf, + ex2_mtfsfi, + ex2_rd_sel_0, + ex2_rd_sel_1, + ex2_rd_sel_2, + ex2_rd_sel_3, + ex2_rd_sel_byp2, + ex2_rd_sel_byp3, + ex2_rd_sel_byp4, + ex2_rd_sel_byp5, + ex2_rd_sel_byp6}) + ); + + ////############################################# + ////## ex3 latches + ////############################################# + + + tri_rlmreg_p #(.WIDTH(25)) ex3_ctl_lat( + .force_t(force_t), // tidn, + .d_mode(tiup), + .delay_lclkr(delay_lclkr[2]), // tidn, + .mpw1_b(mpw1_b[2]), // tidn, + .mpw2_b(mpw2_b[0]), // tidn, + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + .act(fpu_enable),//ex2_act + .scout(ex3_ctl_so), + .scin(ex3_ctl_si), + //----------------- + .din({ ex2_thread[0:3], + ex2_fpscr_bit_data[0:3], + ex2_fpscr_bit_mask[0:3], + ex2_fpscr_nib_mask[0:8], + ex2_mtfsbx, + ex2_mcrfs, + ex2_mtfsf, + ex2_mtfsfi}), + //----------------- + .dout({ ex3_thread[0:3], + ex3_fpscr_bit_data[0:3], + ex3_fpscr_bit_mask[0:3], + ex3_fpscr_nib_mask[0:8], + ex3_mtfsbx, + ex3_mcrfs, + ex3_mtfsf, + ex3_mtfsfi}) + ); + + ////############################################# + ////## ex4 latches + ////############################################# + + + tri_rlmreg_p #(.WIDTH(25)) ex4_ctl_lat( + .force_t(force_t), // tidn, + .d_mode(tiup), + .delay_lclkr(delay_lclkr[3]), // tidn, + .mpw1_b(mpw1_b[3]), // tidn, + .mpw2_b(mpw2_b[0]), // tidn, + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + .act(fpu_enable),//ex3_act + .scout(ex4_ctl_so), + .scin(ex4_ctl_si), + //----------------- + .din({ ex3_thread[0:3], + ex3_fpscr_bit_data[0:3], + ex3_fpscr_bit_mask[0:3], + ex3_fpscr_nib_mask[0:8], + ex3_mtfsbx, + ex3_mcrfs, + ex3_mtfsf, + ex3_mtfsfi}), + //----------------- + .dout({ ex4_thread[0:3], + ex4_fpscr_bit_data[0:3], + ex4_fpscr_bit_mask[0:3], + ex4_fpscr_nib_mask[0:8], + ex4_mtfsbx, + ex4_mcrfs, + ex4_mtfsf, + ex4_mtfsfi}) + ); + + assign f_cr2_ex4_thread_b[0:3] = (~ex4_thread[0:3]); //output-- + assign f_cr2_ex4_fpscr_bit_data_b[0:3] = (~ex4_fpscr_bit_data[0:3]); //output-- + assign f_cr2_ex4_fpscr_bit_mask_b[0:3] = (~ex4_fpscr_bit_mask[0:3]); //output-- + assign f_cr2_ex4_fpscr_nib_mask_b[0:8] = (~ex4_fpscr_nib_mask[0:8]); //output-- + assign f_cr2_ex4_mtfsbx_b = (~ex4_mtfsbx); //output-- + assign f_cr2_ex4_mcrfs_b = (~ex4_mcrfs); //output-- + assign f_cr2_ex4_mtfsf_b = (~ex4_mtfsf); //output-- + assign f_cr2_ex4_mtfsfi_b = (~ex4_mtfsfi); //output-- + + + tri_rlmreg_p #(.WIDTH(5)) ex5_ctl_lat( + .force_t(force_t), // tidn, + .d_mode(tiup), + .delay_lclkr(delay_lclkr[4]), // tidn, + .mpw1_b(mpw1_b[4]), // tidn, + .mpw2_b(mpw2_b[0]), // tidn, + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + .act(fpu_enable),//ex4_act + .scout(ex5_ctl_so), + .scin(ex5_ctl_si), + //----------------- + .din({ ex4_thread[0:3], + ex4_mv_to_op}), + //----------------- + .dout({ ex5_thread[0:3], + ex5_mv_to_op}) + ); + + tri_rlmreg_p #(.WIDTH(5)) ex6_ctl_lat( + .force_t(force_t), // tidn, + .d_mode(tiup), + .delay_lclkr(delay_lclkr[5]), // tidn, + .mpw1_b(mpw1_b[5]), // tidn, + .mpw2_b(mpw2_b[1]), // tidn, + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + .act(fpu_enable),//ex5_act + .scout(ex6_ctl_so), + .scin(ex6_ctl_si), + //----------------- + .din({ ex5_thread[0:3], + ex5_mv_to_op}), + //----------------- + .dout({ ex6_thread[0:3], + ex6_mv_to_op}) + ); + + + tri_rlmreg_p #(.WIDTH(5)) ex7_ctl_lat( + .force_t(force_t), // tidn, + .d_mode(tiup), + .delay_lclkr(delay_lclkr[6]), // tidn, + .mpw1_b(mpw1_b[6]), // tidn, + .mpw2_b(mpw2_b[1]), // tidn, + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + .act(fpu_enable),//ex6_act + .scout(ex7_ctl_so), + .scin(ex7_ctl_si), + //----------------- + .din({ ex6_thread[0:3], + ex6_mv_to_op}), + .dout({ ex7_thread[0:3], + ex7_mv_to_op}) + ); + + assign ex7_cancel = f_dcd_ex7_cancel; + + ////############################################## + ////# read mux for mffs instruction + ////############################################## + + assign f_cr2_ex6_fpscr_rd_dat[24:31] = ({8{ex6_thread[0]}} & shadow0[0:7]) | + ({8{ex6_thread[1]}} & shadow1[0:7]) | + ({8{ex6_thread[2]}} & shadow2[0:7]) | + ({8{ex6_thread[3]}} & shadow3[0:7]); // output to rounder + + assign ex7_fpscr_rd_dat_no_byp[24:31] = ({8{ex7_thread[0]}} & shadow0[0:7]) | + ({8{ex7_thread[1]}} & shadow1[0:7]) | + ({8{ex7_thread[2]}} & shadow2[0:7]) | + ({8{ex7_thread[3]}} & shadow3[0:7]); + + assign f_cr2_ex7_fpscr_rd_dat[24:31] = ({8{ex7_mv_to_op}} & shadow_byp6[0:7]) | + ({8{(~ex7_mv_to_op)}} & ex7_fpscr_rd_dat_no_byp[24:31]); + ////############################################## + ////# fpscr write data / merge + ////############################################## + + assign ex2_bit_sel[0:3] = ex2_fpscr_bit_mask[0:3] & {4{ex2_mv_to_op & ex2_fpscr_nib_mask[6]}}; + assign ex2_bit_sel[4:7] = ex2_fpscr_bit_mask[0:3] & {4{ex2_mv_to_op & ex2_fpscr_nib_mask[7]}}; + + assign ex2_fpscr_data[0:3] = (f_fmt_ex2_bop_byt[45:48] & {4{ex2_mtfsf}}) | + (ex2_fpscr_bit_data[0:3] & {4{(~ex2_mtfsf)}}); + assign ex2_fpscr_data[4:7] = (f_fmt_ex2_bop_byt[49:52] & {4{ex2_mtfsf}}) | + (ex2_fpscr_bit_data[0:3] & {4{(~ex2_mtfsf)}}); + + assign shadow_byp2_din[0:7] = (ex2_fpscr_shadow_mux[0:7] & (~ex2_bit_sel[0:7])) | + (ex2_fpscr_data[0:7] & ex2_bit_sel[0:7]); // may not update all the bits + + ////############################################## + ////# read mux select generation (for pipeline control bits) + ////############################################## + + assign ex2_mv_to_op = ex2_mtfsbx | ex2_mtfsf | ex2_mtfsfi; + assign ex3_mv_to_op = ex3_mtfsbx | ex3_mtfsf | ex3_mtfsfi; + assign ex4_mv_to_op = ex4_mtfsbx | ex4_mtfsf | ex4_mtfsfi; + + assign ex1_thread_match_1 = (ex1_thread[0] & ex2_thread[0]) | (ex1_thread[1] & ex2_thread[1]) | (ex1_thread[2] & ex2_thread[2]) | (ex1_thread[3] & ex2_thread[3]); + + assign ex1_thread_match_2 = (ex1_thread[0] & ex3_thread[0]) | (ex1_thread[1] & ex3_thread[1]) | (ex1_thread[2] & ex3_thread[2]) | (ex1_thread[3] & ex3_thread[3]); + + assign ex1_thread_match_3 = (ex1_thread[0] & ex4_thread[0]) | (ex1_thread[1] & ex4_thread[1]) | (ex1_thread[2] & ex4_thread[2]) | (ex1_thread[3] & ex4_thread[3]); + + assign ex1_thread_match_4 = (ex1_thread[0] & ex5_thread[0]) | (ex1_thread[1] & ex5_thread[1]) | (ex1_thread[2] & ex5_thread[2]) | (ex1_thread[3] & ex5_thread[3]); + + assign ex1_thread_match_5 = (ex1_thread[0] & ex6_thread[0]) | (ex1_thread[1] & ex6_thread[1]) | (ex1_thread[2] & ex6_thread[2]) | (ex1_thread[3] & ex6_thread[3]); + + assign ex1_rd_sel_byp2 = ex1_thread_match_1 & ex2_mv_to_op; + assign ex1_rd_sel_byp3 = ex1_thread_match_2 & ex3_mv_to_op; + assign ex1_rd_sel_byp4 = ex1_thread_match_3 & ex4_mv_to_op; + assign ex1_rd_sel_byp5 = ex1_thread_match_4 & ex5_mv_to_op; + assign ex1_rd_sel_byp6 = ex1_thread_match_5 & ex6_mv_to_op; + + assign ex1_rd_sel_0 = ex1_thread[0] & (~ex1_rd_sel_byp2) & (~ex1_rd_sel_byp3) & (~ex1_rd_sel_byp4) & (~ex1_rd_sel_byp5) & (~ex1_rd_sel_byp6); + assign ex1_rd_sel_1 = ex1_thread[1] & (~ex1_rd_sel_byp2) & (~ex1_rd_sel_byp3) & (~ex1_rd_sel_byp4) & (~ex1_rd_sel_byp5) & (~ex1_rd_sel_byp6); + assign ex1_rd_sel_2 = ex1_thread[2] & (~ex1_rd_sel_byp2) & (~ex1_rd_sel_byp3) & (~ex1_rd_sel_byp4) & (~ex1_rd_sel_byp5) & (~ex1_rd_sel_byp6); + assign ex1_rd_sel_3 = ex1_thread[3] & (~ex1_rd_sel_byp2) & (~ex1_rd_sel_byp3) & (~ex1_rd_sel_byp4) & (~ex1_rd_sel_byp5) & (~ex1_rd_sel_byp6); + + assign ex1_rd_sel_byp2_pri = ex1_rd_sel_byp2; + assign ex1_rd_sel_byp3_pri = (~ex1_rd_sel_byp2) & ex1_rd_sel_byp3; + assign ex1_rd_sel_byp4_pri = (~ex1_rd_sel_byp2) & (~ex1_rd_sel_byp3) & ex1_rd_sel_byp4; + assign ex1_rd_sel_byp5_pri = (~ex1_rd_sel_byp2) & (~ex1_rd_sel_byp3) & (~ex1_rd_sel_byp4) & ex1_rd_sel_byp5; + assign ex1_rd_sel_byp6_pri = (~ex1_rd_sel_byp2) & (~ex1_rd_sel_byp3) & (~ex1_rd_sel_byp4) & (~ex1_rd_sel_byp5) & ex1_rd_sel_byp6; + + ////############################################## + ////# read mux for pipeline control bits + ////############################################## + + assign ex2_fpscr_shadow_mux[0:7] = ({8{ex2_rd_sel_0}} & shadow0[0:7]) | + ({8{ex2_rd_sel_1}} & shadow1[0:7]) | + ({8{ex2_rd_sel_2}} & shadow2[0:7]) | + ({8{ex2_rd_sel_3}} & shadow3[0:7]) | + ({8{ex2_rd_sel_byp2}} & shadow_byp2[0:7]) | + ({8{ex2_rd_sel_byp3}} & shadow_byp3[0:7]) | + ({8{ex2_rd_sel_byp4}} & shadow_byp4[0:7]) | + ({8{ex2_rd_sel_byp5}} & shadow_byp5[0:7]) | + ({8{ex2_rd_sel_byp6}} & shadow_byp6[0:7]); + assign f_cr2_ex2_fpscr_shadow[0:7] = ex2_fpscr_shadow_mux[0:7]; + + ////############################################## + ////# latches + ////############################################## + + + tri_rlmreg_p #(.WIDTH(8)) shadow_byp2_lat( + .force_t(force_t), // tidn, + .d_mode(tiup), + .delay_lclkr(delay_lclkr[2]), // tidn, + .mpw1_b(mpw1_b[2]), // tidn, + .mpw2_b(mpw2_b[0]), // tidn, + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + .act(ex2_act), + .scout(shadow_byp2_so), + .scin(shadow_byp2_si), + //---------------- + .din(shadow_byp2_din[0:7]), + .dout(shadow_byp2[0:7]) //LAT-- + ); + + + tri_rlmreg_p #(.WIDTH(8)) shadow_byp3_lat( + .force_t(force_t), // tidn, + .d_mode(tiup), + .delay_lclkr(delay_lclkr[3]), // tidn, + .mpw1_b(mpw1_b[3]), // tidn, + .mpw2_b(mpw2_b[0]), // tidn, + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + .act(ex3_act), + .scout(shadow_byp3_so), + .scin(shadow_byp3_si), + //----------------- + .din(shadow_byp2[0:7]), + .dout(shadow_byp3[0:7]) //LAT-- + ); + + + tri_rlmreg_p #(.WIDTH(8)) shadow_byp4_lat( + .force_t(force_t), // tidn, + .d_mode(tiup), + .delay_lclkr(delay_lclkr[4]), // tidn, + .mpw1_b(mpw1_b[4]), // tidn, + .mpw2_b(mpw2_b[0]), // tidn, + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + .act(ex4_act), + .scout(shadow_byp4_so), + .scin(shadow_byp4_si), + //----------------- + .din(shadow_byp3[0:7]), + .dout(shadow_byp4[0:7]) //LAT-- + ); + + + tri_rlmreg_p #(.WIDTH(8)) shadow_byp5_lat( + .force_t(force_t), // tidn, + .d_mode(tiup), + .delay_lclkr(delay_lclkr[5]), // tidn, + .mpw1_b(mpw1_b[5]), // tidn, + .mpw2_b(mpw2_b[1]), // tidn, + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + .act(ex5_act), + .scout(shadow_byp5_so), + .scin(shadow_byp5_si), + //----------------- + .din(shadow_byp4[0:7]), + .dout(shadow_byp5[0:7]) //LAT-- + ); + + tri_rlmreg_p #(.WIDTH(8)) shadow_byp6_lat( + .force_t(force_t), // tidn, + .d_mode(tiup), + .delay_lclkr(delay_lclkr[6]), // tidn, + .mpw1_b(mpw1_b[6]), // tidn, + .mpw2_b(mpw2_b[1]), // tidn, + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + .act(ex6_act), + .scout(shadow_byp6_so), + .scin(shadow_byp6_si), + //----------------- + .din(shadow_byp5[0:7]), + .dout(shadow_byp6[0:7]) //LAT-- + ); + + assign ex7_th0_act = ex7_act & ex7_thread[0] & (~ex7_cancel) & ex7_mv_to_op; + assign ex7_th1_act = ex7_act & ex7_thread[1] & (~ex7_cancel) & ex7_mv_to_op; + assign ex7_th2_act = ex7_act & ex7_thread[2] & (~ex7_cancel) & ex7_mv_to_op; + assign ex7_th3_act = ex7_act & ex7_thread[3] & (~ex7_cancel) & ex7_mv_to_op; + + tri_rlmreg_p #(.WIDTH(8)) shadow0_lat( + .force_t(force_t), // tidn, + .d_mode(tiup), + .delay_lclkr(delay_lclkr[7]), // tidn, + .mpw1_b(mpw1_b[7]), // tidn, + .mpw2_b(mpw2_b[1]), // tidn, + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + .act(ex7_th0_act), + .scout(shadow0_so), + .scin(shadow0_si), + //----------------- + .din(shadow_byp6[0:7]), + .dout(shadow0[0:7]) //LAT-- + ); + + + tri_rlmreg_p #(.WIDTH(8)) shadow1_lat( + .force_t(force_t), // tidn, + .d_mode(tiup), + .delay_lclkr(delay_lclkr[7]), // tidn, + .mpw1_b(mpw1_b[7]), // tidn, + .mpw2_b(mpw2_b[1]), // tidn, + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + .act(ex7_th1_act), + .scout(shadow1_so), + .scin(shadow1_si), + //----------------- + .din(shadow_byp6[0:7]), + .dout(shadow1[0:7]) //LAT-- + ); + + + tri_rlmreg_p #(.WIDTH(8)) shadow2_lat( + .force_t(force_t), // tidn, + .d_mode(tiup), + .delay_lclkr(delay_lclkr[7]), // tidn, + .mpw1_b(mpw1_b[7]), // tidn, + .mpw2_b(mpw2_b[1]), // tidn, + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + .act(ex7_th2_act), + .scout(shadow2_so), + .scin(shadow2_si), + //----------------- + .din(shadow_byp6[0:7]), + .dout(shadow2[0:7]) //LAT-- + ); + + + tri_rlmreg_p #(.WIDTH(8)) shadow3_lat( + .force_t(force_t), // tidn, + .d_mode(tiup), + .delay_lclkr(delay_lclkr[7]), // tidn, + .mpw1_b(mpw1_b[7]), // tidn, + .mpw2_b(mpw2_b[1]), // tidn, + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + .act(ex7_th3_act), + .scout(shadow3_so), + .scin(shadow3_si), + //----------------- + .din(shadow_byp6[0:7]), + .dout(shadow3[0:7]) //LAT-- + ); + + ////############################################ + ////# scan + ////############################################ + + // initial value must be "11111" for _b latches -- + + assign ex2_ctl_si[0:33] = {ex2_ctl_so[1:33], f_cr2_si}; + assign ex3_ctl_si[0:24] = {ex3_ctl_so[1:24], ex2_ctl_so[0]}; + assign ex4_ctl_si[0:24] = {ex4_ctl_so[1:24], ex3_ctl_so[0]}; + assign ex5_ctl_si[0:4] = {ex5_ctl_so[1:4], ex4_ctl_so[0]}; + assign ex6_ctl_si[0:4] = {ex6_ctl_so[1:4], ex5_ctl_so[0]}; + assign ex7_ctl_si[0:4] = {ex7_ctl_so[1:4], ex6_ctl_so[0]}; + assign shadow0_si[0:7] = {shadow0_so[1:7], ex7_ctl_so[0]}; + assign shadow1_si[0:7] = {shadow1_so[1:7], shadow0_so[0]}; + assign shadow2_si[0:7] = {shadow2_so[1:7], shadow1_so[0]}; + assign shadow3_si[0:7] = {shadow3_so[1:7], shadow2_so[0]}; + assign shadow_byp2_si[0:7] = {shadow_byp2_so[1:7], shadow3_so[0]}; + assign shadow_byp3_si[0:7] = {shadow_byp3_so[1:7], shadow_byp2_so[0]}; + assign shadow_byp4_si[0:7] = {shadow_byp4_so[1:7], shadow_byp3_so[0]}; + assign shadow_byp5_si[0:7] = {shadow_byp5_so[1:7], shadow_byp4_so[0]}; + assign shadow_byp6_si[0:7] = {shadow_byp6_so[1:7], shadow_byp5_so[0]}; + assign act_si[0:6] = {act_so[1:6], shadow_byp6_so[0]}; + assign f_cr2_so = act_so[0]; + +endmodule diff --git a/dev/verilog/work/fu_dcd.v b/dev/verilog/work/fu_dcd.v new file mode 100755 index 0000000..a7e2ffa --- /dev/null +++ b/dev/verilog/work/fu_dcd.v @@ -0,0 +1,4671 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//***************************************************************************** +//* +//* TITLE: F_DP_DCD +//* +//* NAME: fuq_dcd.vhdl +//* +//* DESC: This is Control and Decode +//* +//***************************************************************************** + `include "tri_a2o.vh" + +module fu_dcd( + act_dis, + bcfg_scan_in, + ccfg_scan_in, + cfg_sl_thold_1, + func_slp_sl_thold_1, + clkoff_b, + cp_flush, + dcfg_scan_in, + + debug_bus_in, + coretrace_ctrls_in, + debug_bus_out, + coretrace_ctrls_out, + + f_dcd_perr_sm_running, + f_dcd_ex2_perr_force_c, + f_dcd_ex2_perr_fsel_ovrd, + + + delay_lclkr, + f_add_ex5_fpcc_iu, + f_dcd_si, + f_dsq_ex5_divsqrt_itag, + f_dsq_ex5_divsqrt_v, + f_dsq_ex6_divsqrt_cr_bf, + f_dsq_ex6_divsqrt_fpscr_addr, + f_dsq_ex6_divsqrt_instr_frt, + f_dsq_ex6_divsqrt_instr_tid, + f_dsq_ex6_divsqrt_record_v, + f_dsq_ex6_divsqrt_v, + f_dsq_ex6_divsqrt_v_suppress, + f_dcd_rv_hold_all, + f_dsq_ex3_hangcounter_trigger, + f_dsq_debug, + f_ex3_b_den_flush, + f_fpr_ex6_load_addr, + f_fpr_ex6_load_v, + f_fpr_ex6_reload_addr, + f_fpr_ex6_reload_v, + f_mad_ex3_a_parity_check, + f_mad_ex3_b_parity_check, + f_mad_ex3_c_parity_check, + f_mad_ex4_uc_res_sign, + f_mad_ex4_uc_round_mode, + f_mad_ex4_uc_special, + f_mad_ex4_uc_vxidi, + f_mad_ex4_uc_vxsnan, + f_mad_ex4_uc_vxsqrt, + f_mad_ex4_uc_vxzdz, + f_mad_ex4_uc_zx, + f_mad_ex7_uc_sign, + f_mad_ex7_uc_zero, + f_pic_ex6_fpr_wr_dis_b, + f_pic_ex6_scr_upd_move_b, + f_rnd_ex7_res_expo, + f_rnd_ex7_res_frac, + f_rnd_ex7_res_sign, + f_scr_cpl_fx_thread0, + f_scr_cpl_fx_thread1, + f_scr_ex8_cr_fld, + f_scr_ex8_fx_thread0, + f_scr_ex8_fx_thread1, + f_scr_ex6_fpscr_ni_thr0, + f_scr_ex6_fpscr_ni_thr1, + f_sto_ex3_s_parity_check, + flush, + iu_fu_rf0_tid, + iu_fu_rf0_fra, + iu_fu_rf0_fra_v, + iu_fu_rf0_frb, + iu_fu_rf0_frb_v, + iu_fu_rf0_frc, + iu_fu_rf0_frc_v, + iu_fu_rf0_instr_match, + mpw1_b, + mpw2_b, + nclk, + pc_fu_debug_mux_ctrls, + pc_fu_event_count_mode, + pc_fu_instr_trace_mode, + pc_fu_instr_trace_tid, + pc_fu_ram_active, + pc_fu_trace_bus_enable, + pc_fu_event_bus_enable, + event_bus_in, + event_bus_out, + rv_axu0_ex0_instr, + + rv_axu0_ex0_t1_p, + rv_axu0_ex0_t1_v, + rv_axu0_ex0_t2_p, + rv_axu0_ex0_t3_p, + rv_axu0_ex0_ucode, + + rv_axu0_ex0_itag, + rv_axu0_vld, + sg_1, + slowspr_addr_in, + slowspr_data_in, + slowspr_done_in, + slowspr_etid_in, + slowspr_rw_in, + slowspr_val_in, + thold_1, + + lq_fu_ex5_abort, + xu_fu_ex4_eff_addr, + xu_fu_msr_fe0, + xu_fu_msr_fe1, + xu_fu_msr_fp, + xu_fu_msr_gs, + xu_fu_msr_pr, + + + gnd, + + vdd, + + axu0_cr_w4a, + axu0_cr_w4d, + axu0_cr_w4e, + axu0_iu_async_fex, + axu0_iu_exception, + axu0_iu_exception_val, + axu0_iu_execute_vld, + axu0_iu_flush2ucode, + axu0_iu_flush2ucode_type, + axu0_iu_itag, + axu0_iu_n_flush, + axu0_iu_n_np1_flush, + axu0_iu_np1_flush, + axu0_iu_perf_events, + axu0_rv_itag, + axu0_rv_itag_vld, + axu0_rv_itag_abort, + axu0_rv_ord_complete, + axu1_iu_exception, + axu1_iu_exception_val, + axu1_iu_execute_vld, + axu1_iu_flush2ucode, + axu1_iu_flush2ucode_type, + axu1_iu_itag, + axu1_iu_n_flush, + axu1_iu_np1_flush, + axu1_iu_perf_events, + axu1_rv_itag, + axu1_rv_itag_vld, + axu1_rv_itag_abort, + bcfg_scan_out, + ccfg_scan_out, + dcfg_scan_out, + f_dcd_msr_fp_act, + f_dcd_ex1_sto_act, + f_dcd_ex1_mad_act, + + f_dcd_ex1_aop_valid, + f_dcd_ex1_bop_valid, + f_dcd_ex1_thread, + f_dcd_ex1_bypsel_a_load0, + f_dcd_ex1_bypsel_a_load1, + f_dcd_ex1_bypsel_a_load2, + f_dcd_ex1_bypsel_a_reload0, + f_dcd_ex1_bypsel_a_reload1, + f_dcd_ex1_bypsel_a_reload2, + + f_dcd_ex1_bypsel_a_res0, + f_dcd_ex1_bypsel_a_res1, + f_dcd_ex1_bypsel_a_res2, + f_dcd_ex1_bypsel_b_load0, + f_dcd_ex1_bypsel_b_load1, + f_dcd_ex1_bypsel_b_load2, + f_dcd_ex1_bypsel_b_reload0, + f_dcd_ex1_bypsel_b_reload1, + f_dcd_ex1_bypsel_b_reload2, + + f_dcd_ex1_bypsel_b_res0, + f_dcd_ex1_bypsel_b_res1, + f_dcd_ex1_bypsel_b_res2, + f_dcd_ex1_bypsel_c_load0, + f_dcd_ex1_bypsel_c_load1, + f_dcd_ex1_bypsel_c_load2, + f_dcd_ex1_bypsel_c_reload0, + f_dcd_ex1_bypsel_c_reload1, + f_dcd_ex1_bypsel_c_reload2, + + f_dcd_ex1_bypsel_c_res0, + f_dcd_ex1_bypsel_c_res1, + f_dcd_ex1_bypsel_c_res2, + f_dcd_ex1_bypsel_s_load0, + f_dcd_ex1_bypsel_s_load1, + f_dcd_ex1_bypsel_s_load2, + f_dcd_ex1_bypsel_s_reload0, + f_dcd_ex1_bypsel_s_reload1, + f_dcd_ex1_bypsel_s_reload2, + + f_dcd_ex1_bypsel_s_res0, + f_dcd_ex1_bypsel_s_res1, + f_dcd_ex1_bypsel_s_res2, + f_dcd_ex1_compare_b, + f_dcd_ex1_cop_valid, + f_dcd_ex1_divsqrt_cr_bf, + f_dcd_axucr0_deno, + f_dcd_ex1_emin_dp, + f_dcd_ex1_emin_sp, + f_dcd_ex1_est_recip_b, + f_dcd_ex1_est_rsqrt_b, + f_dcd_ex1_force_excp_dis, + f_dcd_ex1_force_pass_b, + f_dcd_ex1_fpscr_addr, + f_dcd_ex1_fpscr_bit_data_b, + f_dcd_ex1_fpscr_bit_mask_b, + f_dcd_ex1_fpscr_nib_mask_b, + f_dcd_ex1_from_integer_b, + f_dcd_ex1_frsp_b, + f_dcd_ex1_fsel_b, + f_dcd_ex1_ftdiv, + f_dcd_ex1_ftsqrt, + f_dcd_ex1_instr_frt, + f_dcd_ex1_instr_tid, + f_dcd_ex1_inv_sign_b, + f_dcd_ex1_itag, + f_dcd_ex1_log2e_b, + f_dcd_ex1_math_b, + f_dcd_ex1_mcrfs_b, + f_dcd_ex1_move_b, + f_dcd_ex1_mtfsbx_b, + f_dcd_ex1_mtfsf_b, + f_dcd_ex1_mtfsfi_b, + f_dcd_ex1_mv_from_scr_b, + f_dcd_ex1_mv_to_scr_b, + f_dcd_ex1_nj_deni, + f_dcd_ex1_nj_deno, + f_dcd_ex1_op_rnd_b, + f_dcd_ex1_op_rnd_v_b, + f_dcd_ex1_ordered_b, + f_dcd_ex1_pow2e_b, + f_dcd_ex1_prenorm_b, + f_dcd_ex1_rnd_to_int_b, + f_dcd_ex1_sgncpy_b, + f_dcd_ex1_sign_ctl_b, + f_dcd_ex1_sp, + f_dcd_ex1_sp_conv_b, + f_dcd_ex1_sto_dp, + f_dcd_ex1_sto_sp, + f_dcd_ex1_sto_wd, + f_dcd_ex1_sub_op_b, + f_dcd_ex1_thread_b, + f_dcd_ex1_to_integer_b, + f_dcd_ex1_uc_end, + f_dcd_ex1_uc_fa_pos, + f_dcd_ex1_uc_fb_0_5, + f_dcd_ex1_uc_fb_0_75, + f_dcd_ex1_uc_fb_1_0, + f_dcd_ex1_uc_fb_pos, + f_dcd_ex1_uc_fc_0_5, + f_dcd_ex1_uc_fc_1_0, + f_dcd_ex1_uc_fc_1_minus, + f_dcd_ex1_uc_fc_hulp, + f_dcd_ex1_uc_fc_pos, + f_dcd_ex1_uc_ft_neg, + f_dcd_ex1_uc_ft_pos, + f_dcd_ex1_uc_mid, + f_dcd_ex1_uc_special, + f_dcd_ex1_uns_b, + f_dcd_ex1_word_b, + f_dcd_ex2_divsqrt_v, + f_dcd_ex2_divsqrt_hole_v, + f_dcd_ex3_uc_gs, + f_dcd_ex3_uc_gs_v, + f_dcd_ex3_uc_inc_lsb, + f_dcd_ex3_uc_vxidi, + f_dcd_ex3_uc_vxsnan, + f_dcd_ex3_uc_vxsqrt, + f_dcd_ex3_uc_vxzdz, + f_dcd_ex3_uc_zx, + f_dcd_ex6_frt_tid, + f_dcd_ex7_cancel, + f_dcd_ex7_fpscr_addr, + f_dcd_ex7_fpscr_wr, + f_dcd_ex7_frt_addr, + f_dcd_ex7_frt_tid, + f_dcd_ex7_frt_wen, + f_dcd_flush, + f_dcd_rf0_fra, + f_dcd_rf0_frb, + f_dcd_rf0_frc, + f_dcd_rf0_tid, + f_dcd_ex0_div, + f_dcd_ex0_divs, + f_dcd_ex0_record_v, + f_dcd_ex0_sqrt, + f_dcd_ex0_sqrts, + f_dcd_ex1_sto_v, + f_dcd_so, + fu_lq_ex2_store_data_val, + fu_lq_ex2_store_itag, + fu_lq_ex3_abort, + fu_lq_ex3_sto_parity_err, + axu0_rv_ex2_s1_abort, + axu0_rv_ex2_s2_abort, + axu0_rv_ex2_s3_abort, + + fu_pc_err_regfile_parity, + fu_pc_err_regfile_ue, + + fu_pc_ram_data, + fu_pc_ram_data_val, + + slowspr_addr_out, + slowspr_data_out, + slowspr_done_out, + slowspr_etid_out, + slowspr_rw_out, + slowspr_val_out, + rf0_act_b +); + parameter EFF_IFAR = 62; + parameter THREADS = 2; + parameter ITAG_SIZE_ENC = 7; + parameter THREAD_POOL_ENC = 1; + parameter CR_POOL_ENC = 5; + parameter REGMODE = 6; //32 or 64 bit mode + // INPUTS + input act_dis; + input bcfg_scan_in; + input ccfg_scan_in; + input cfg_sl_thold_1; + input func_slp_sl_thold_1; + + input clkoff_b; // tiup + input [0:`THREADS-1] cp_flush; + input dcfg_scan_in; + + // Pass Thru Debug Trace Bus + input [0:31] debug_bus_in; + input [0:3] coretrace_ctrls_in; + + output [0:31] debug_bus_out; + output [0:3] coretrace_ctrls_out; + + output f_dcd_perr_sm_running; + output f_dcd_ex2_perr_force_c; + output f_dcd_ex2_perr_fsel_ovrd; + + + input [0:9] delay_lclkr; // tidn, + input [0:3] f_add_ex5_fpcc_iu; + input f_dcd_si; + input [0:6] f_dsq_ex5_divsqrt_itag; + input [0:1] f_dsq_ex5_divsqrt_v; + input [0:4] f_dsq_ex6_divsqrt_cr_bf; + input [0:5] f_dsq_ex6_divsqrt_fpscr_addr; + input [0:5] f_dsq_ex6_divsqrt_instr_frt; + input [0:3] f_dsq_ex6_divsqrt_instr_tid; + input f_dsq_ex6_divsqrt_record_v; + input [0:1] f_dsq_ex6_divsqrt_v; + input f_dsq_ex6_divsqrt_v_suppress; + + input [0:63] f_dsq_debug; + + input f_dsq_ex3_hangcounter_trigger; + + output f_dcd_rv_hold_all; + + + input f_ex3_b_den_flush; + input [0:7] f_fpr_ex6_load_addr; + input f_fpr_ex6_load_v; + input [0:7] f_fpr_ex6_reload_addr; + input f_fpr_ex6_reload_v; + input f_mad_ex3_a_parity_check; + input f_mad_ex3_b_parity_check; + input f_mad_ex3_c_parity_check; + input f_mad_ex4_uc_res_sign; + input [0:1] f_mad_ex4_uc_round_mode; + input f_mad_ex4_uc_special; + input f_mad_ex4_uc_vxidi; + input f_mad_ex4_uc_vxsnan; + input f_mad_ex4_uc_vxsqrt; + input f_mad_ex4_uc_vxzdz; + input f_mad_ex4_uc_zx; + input f_mad_ex7_uc_sign; + input f_mad_ex7_uc_zero; + input f_pic_ex6_fpr_wr_dis_b; + input f_pic_ex6_scr_upd_move_b; + input [1:13] f_rnd_ex7_res_expo; + input [0:52] f_rnd_ex7_res_frac; + input f_rnd_ex7_res_sign; + input [0:3] f_scr_cpl_fx_thread0; + input [0:3] f_scr_cpl_fx_thread1; + input [0:3] f_scr_ex8_cr_fld; + input [0:3] f_scr_ex8_fx_thread0; + input [0:3] f_scr_ex8_fx_thread1; + input f_scr_ex6_fpscr_ni_thr0; + input f_scr_ex6_fpscr_ni_thr1; + input f_sto_ex3_s_parity_check; + input flush; // ??tidn?? + input [0:`THREADS-1] iu_fu_rf0_tid; + input [0:5] iu_fu_rf0_fra; + input iu_fu_rf0_fra_v; + input [0:5] iu_fu_rf0_frb; + input iu_fu_rf0_frb_v; + input [0:5] iu_fu_rf0_frc; + input iu_fu_rf0_frc_v; + input iu_fu_rf0_instr_match; + input [0:9] mpw1_b; + input [0:1] mpw2_b; + input [0:`NCLK_WIDTH-1] nclk; + input [0:10] pc_fu_debug_mux_ctrls; + input [0:2] pc_fu_event_count_mode; + input pc_fu_instr_trace_mode; + input [0:1] pc_fu_instr_trace_tid; + input [0:`THREADS-1] pc_fu_ram_active; + input pc_fu_trace_bus_enable; + input pc_fu_event_bus_enable; + input [0:4*`THREADS-1] event_bus_in; + output [0:4*`THREADS-1] event_bus_out; + + + input [0:31] rv_axu0_ex0_instr; + + input [0:5] rv_axu0_ex0_t1_p; + input rv_axu0_ex0_t1_v; + input [0:5] rv_axu0_ex0_t2_p; + input [0:5] rv_axu0_ex0_t3_p; + input [0:2] rv_axu0_ex0_ucode; + + input [0:6] rv_axu0_ex0_itag; + input [0:`THREADS-1] rv_axu0_vld; + input sg_1; + input [0:9] slowspr_addr_in; + input [64-(2**REGMODE):63] slowspr_data_in; + input slowspr_done_in; + input [0:1] slowspr_etid_in; + input slowspr_rw_in; + input slowspr_val_in; + input thold_1; + + input [59:63] xu_fu_ex4_eff_addr; + input [0:`THREADS-1] xu_fu_msr_fe0; + input [0:`THREADS-1] xu_fu_msr_fe1; + input [0:`THREADS-1] xu_fu_msr_fp; + input [0:`THREADS-1] xu_fu_msr_gs; + input [0:`THREADS-1] xu_fu_msr_pr; + + input lq_fu_ex5_abort; + + // INOUTS + inout gnd; + inout vdd; + + // OUTPUTS + output [0:CR_POOL_ENC+THREAD_POOL_ENC-1] axu0_cr_w4a; //: out std_ulogic_vector(0 to 4); + output [0:3] axu0_cr_w4d; + output axu0_cr_w4e; + output [0:`THREADS-1] axu0_iu_async_fex; + output [0:3] axu0_iu_exception; + output axu0_iu_exception_val; + output [0:`THREADS-1] axu0_iu_execute_vld; + output axu0_iu_flush2ucode; + output axu0_iu_flush2ucode_type; + output [0:6] axu0_iu_itag; + output axu0_iu_n_flush; + output axu0_iu_n_np1_flush; + output axu0_iu_np1_flush; + output [0:6] axu0_rv_itag; + output [0:`THREADS-1] axu0_rv_itag_vld; + output axu0_rv_itag_abort; + output axu0_rv_ord_complete; + output [0:3] axu0_iu_perf_events; + + output [0:3] axu1_iu_exception; + output axu1_iu_exception_val; + output [0:`THREADS-1] axu1_iu_execute_vld; + output axu1_iu_flush2ucode; + output axu1_iu_flush2ucode_type; + output [0:6] axu1_iu_itag; + output axu1_iu_n_flush; + output axu1_iu_np1_flush; + output [0:6] axu1_rv_itag; + output [0:`THREADS-1] axu1_rv_itag_vld; + output axu1_rv_itag_abort; + output [0:3] axu1_iu_perf_events; + + output bcfg_scan_out; + output ccfg_scan_out; + output dcfg_scan_out; + output f_dcd_ex1_sto_act; + output f_dcd_ex1_mad_act; + output f_dcd_msr_fp_act; + + output f_dcd_ex1_aop_valid; + output f_dcd_ex1_bop_valid; + output [0:1] f_dcd_ex1_thread; + output f_dcd_ex1_bypsel_a_load0; + output f_dcd_ex1_bypsel_a_load1; + output f_dcd_ex1_bypsel_a_load2; + output f_dcd_ex1_bypsel_a_reload0; + output f_dcd_ex1_bypsel_a_reload1; + output f_dcd_ex1_bypsel_a_reload2; + + output f_dcd_ex1_bypsel_a_res0; + output f_dcd_ex1_bypsel_a_res1; + output f_dcd_ex1_bypsel_a_res2; + output f_dcd_ex1_bypsel_b_load0; + output f_dcd_ex1_bypsel_b_load1; + output f_dcd_ex1_bypsel_b_load2; + output f_dcd_ex1_bypsel_b_reload0; + output f_dcd_ex1_bypsel_b_reload1; + output f_dcd_ex1_bypsel_b_reload2; + + output f_dcd_ex1_bypsel_b_res0; + output f_dcd_ex1_bypsel_b_res1; + output f_dcd_ex1_bypsel_b_res2; + output f_dcd_ex1_bypsel_c_load0; + output f_dcd_ex1_bypsel_c_load1; + output f_dcd_ex1_bypsel_c_load2; + output f_dcd_ex1_bypsel_c_reload0; + output f_dcd_ex1_bypsel_c_reload1; + output f_dcd_ex1_bypsel_c_reload2; + + output f_dcd_ex1_bypsel_c_res0; + output f_dcd_ex1_bypsel_c_res1; + output f_dcd_ex1_bypsel_c_res2; + output f_dcd_ex1_bypsel_s_load0; + output f_dcd_ex1_bypsel_s_load1; + output f_dcd_ex1_bypsel_s_load2; + output f_dcd_ex1_bypsel_s_reload0; + output f_dcd_ex1_bypsel_s_reload1; + output f_dcd_ex1_bypsel_s_reload2; + + output f_dcd_ex1_bypsel_s_res0; + output f_dcd_ex1_bypsel_s_res1; + output f_dcd_ex1_bypsel_s_res2; + output f_dcd_ex1_compare_b; // fcomp* + output f_dcd_ex1_cop_valid; + output [0:4] f_dcd_ex1_divsqrt_cr_bf; + output f_dcd_axucr0_deno; + + output f_dcd_ex1_emin_dp; // prenorm_dp + output f_dcd_ex1_emin_sp; // prenorm_sp, frsp + output f_dcd_ex1_est_recip_b; // fres + output f_dcd_ex1_est_rsqrt_b; // frsqrte + output f_dcd_ex1_force_excp_dis; // force all exceptions disabled + + + output f_dcd_ex1_force_pass_b; // fmr,fnabbs,fabs,fneg,mtfsf + output [0:5] f_dcd_ex1_fpscr_addr; + output [0:3] f_dcd_ex1_fpscr_bit_data_b; //data to write to nibble (other than mtfsf) + output [0:3] f_dcd_ex1_fpscr_bit_mask_b; //enable update of bit within the nibble + output [0:8] f_dcd_ex1_fpscr_nib_mask_b; //enable update of this nibble + output f_dcd_ex1_from_integer_b; // fcfid (signed integer) + output f_dcd_ex1_frsp_b; // round-to-single-precision ?? need + output f_dcd_ex1_fsel_b; // fsel + output f_dcd_ex1_ftdiv; + output f_dcd_ex1_ftsqrt; + output [0:5] f_dcd_ex1_instr_frt; + output [0:3] f_dcd_ex1_instr_tid; + output f_dcd_ex1_inv_sign_b; // fnmsub fnmadd + output [0:6] f_dcd_ex1_itag; + output f_dcd_ex1_log2e_b; + output f_dcd_ex1_math_b; // fmul,fmad,fmsub,fadd,fsub,fnmsub,fnmadd + output f_dcd_ex1_mcrfs_b; //move fpscr field to cr and reset exceptions + output f_dcd_ex1_move_b; // fmr,fneg,fabs,fnabs + output f_dcd_ex1_mtfsbx_b; //fpscr set bit, reset bit + output f_dcd_ex1_mtfsf_b; //move fpr data to fpscr + output f_dcd_ex1_mtfsfi_b; //move immediate data to fpscr + output f_dcd_ex1_mv_from_scr_b; //mffs + output f_dcd_ex1_mv_to_scr_b; //mcrfs,mtfsf,mtfsfi,mtfsb0,mtfsb1 + output f_dcd_ex1_nj_deni; // force input den to zero + output f_dcd_ex1_nj_deno; // force output den to zero + output [0:1] f_dcd_ex1_op_rnd_b; // rounding mode = positive infinity + output f_dcd_ex1_op_rnd_v_b; // rounding mode = nearest + output f_dcd_ex1_ordered_b; // fcompo + output f_dcd_ex1_pow2e_b; + output f_dcd_ex1_prenorm_b; // prenorm ?? need + output f_dcd_ex1_rnd_to_int_b; // fri* + output f_dcd_ex1_sgncpy_b; // for sgncpy instruction : + output [0:1] f_dcd_ex1_sign_ctl_b; // 0:fmr/fnabs 1:fneg/fnabs + output f_dcd_ex1_sp; // off for frsp + output f_dcd_ex1_sp_conv_b; // for sp/dp convert + output f_dcd_ex1_sto_dp; + output f_dcd_ex1_sto_sp; + output f_dcd_ex1_sto_wd; + output f_dcd_ex1_sub_op_b; // fsub, fnmsub, fmsub + output [0:3] f_dcd_ex1_thread_b; + output f_dcd_ex1_to_integer_b; // fcti* (signed integer 32/64) + output f_dcd_ex1_uc_end; + output f_dcd_ex1_uc_fa_pos; + output f_dcd_ex1_uc_fb_0_5; + output f_dcd_ex1_uc_fb_0_75; + output f_dcd_ex1_uc_fb_1_0; + output f_dcd_ex1_uc_fb_pos; + output f_dcd_ex1_uc_fc_0_5; + output f_dcd_ex1_uc_fc_1_0; + output f_dcd_ex1_uc_fc_1_minus; + output f_dcd_ex1_uc_fc_hulp; + output f_dcd_ex1_uc_fc_pos; + output f_dcd_ex1_uc_ft_neg; + output f_dcd_ex1_uc_ft_pos; + output f_dcd_ex1_uc_mid; + output f_dcd_ex1_uc_special; + output f_dcd_ex1_uns_b; // for converts unsigned + output f_dcd_ex1_word_b; // fctiw* + output f_dcd_ex2_divsqrt_v; + output f_dcd_ex2_divsqrt_hole_v; + output [0:1] f_dcd_ex3_uc_gs; + output f_dcd_ex3_uc_gs_v; + output f_dcd_ex3_uc_inc_lsb; + output f_dcd_ex3_uc_vxidi; + output f_dcd_ex3_uc_vxsnan; + output f_dcd_ex3_uc_vxsqrt; + output f_dcd_ex3_uc_vxzdz; + output f_dcd_ex3_uc_zx; + output [0:1] f_dcd_ex6_frt_tid; + output f_dcd_ex7_cancel; + output [0:5] f_dcd_ex7_fpscr_addr; + output f_dcd_ex7_fpscr_wr; + output [0:5] f_dcd_ex7_frt_addr; + output [0:1] f_dcd_ex7_frt_tid; + output f_dcd_ex7_frt_wen; + output [0:1] f_dcd_flush; + output [0:5] f_dcd_rf0_fra; + output [0:5] f_dcd_rf0_frb; + output [0:5] f_dcd_rf0_frc; + output [0:1] f_dcd_rf0_tid; + + output f_dcd_ex0_div; + output f_dcd_ex0_divs; + output f_dcd_ex0_record_v; + output f_dcd_ex0_sqrt; + output f_dcd_ex0_sqrts; + output f_dcd_ex1_sto_v; + + output f_dcd_so; + output [0:`THREADS-1] fu_lq_ex2_store_data_val; + output [0:ITAG_SIZE_ENC-1] fu_lq_ex2_store_itag; + output fu_lq_ex3_abort; + output fu_lq_ex3_sto_parity_err; + output axu0_rv_ex2_s1_abort; + output axu0_rv_ex2_s2_abort; + output axu0_rv_ex2_s3_abort; + output [0:`THREADS-1] fu_pc_err_regfile_parity; + output [0:`THREADS-1] fu_pc_err_regfile_ue; + + output [0:63] fu_pc_ram_data; + output fu_pc_ram_data_val; + + output [0:9] slowspr_addr_out; + output [64-(2**REGMODE):63] slowspr_data_out; + output slowspr_done_out; + output [0:1] slowspr_etid_out; + output slowspr_rw_out; + output slowspr_val_out; + + output rf0_act_b; + // This entity contains macros + + + // ###################### CONSTANTS ###################### -- + parameter [32:63] EVENTMUX_32_MASK = 32'b11111111111111111111111111111111; + + // ####################### SIGNALS ####################### -- + wire [0:7] act_lat_si; + wire [0:7] act_lat_so; + wire [0:3] axu_ex_si; + wire [0:3] axu_ex_so; + wire cp_flush_reg0_si; + wire cp_flush_reg0_so; + wire cp_flush_reg1_si; + wire cp_flush_reg1_so; + wire axucr0_dec; + wire [60:63] axucr0_din; + wire [0:3] axucr0_lat_si; + wire [0:3] axucr0_lat_so; + wire [60:63] axucr0_q; + wire [32:63] axucr0_out; + wire axucr0_rd; + wire axucr0_wr; + wire a0esr_dec; + wire [32:63] a0esr_din; + wire [0:31] a0esr_lat_si; + wire [0:31] a0esr_lat_so; + wire [32:63] a0esr_q; + wire a0esr_rd; + wire a0esr_wr; + wire [0:31] a0esr_event_mux_ctrls; + + wire cfg_sl_force; + wire cfg_sl_thold_0; + wire cfg_sl_thold_0_b; + wire [0:1] cp_flush_q; + wire [0:1] cp_flush_int; + wire dbg0_act; + wire event_act; + + wire [0:67] dbg0_data_si; + wire [0:67] dbg0_data_so; + + wire [0:4] dbg1_data_si; + wire [0:4] dbg1_data_so; + wire [0:63] dbg_group0; + wire [0:63] dbg_group1; + wire [0:63] dbg_group2; + wire [0:63] dbg_group3; + wire [0:31] dbg_group3_din; + wire [0:31] dbg_group3_q; + + wire [0:31] debug_data_d; + wire [0:31] debug_data_q; + wire [0:10] debug_mux_ctrls_muxed; + wire [0:10] debug_mux_ctrls_q; + wire [0:10] debug_mux_ctrls_d; + + wire [0:3] coretrace_ctrls_out_d; + wire [0:3] coretrace_ctrls_out_q; + + + wire [0:1] evnt_axu_cr_cmt; + wire [0:1] evnt_axu_idle; + wire [0:1] evnt_axu_instr_cmt; + wire [0:1] evnt_denrm_flush; + wire [0:1] evnt_div_sqrt_ip; + wire [0:1] evnt_fpu_fex; + wire [0:1] evnt_fpu_fx; + wire [0:1] evnt_fpu_cpl_fex; + wire [0:1] evnt_fpu_cpl_fx; + + wire ex2_axu_v; + + + wire [0:1] evnt_uc_instr_cmt; + + + wire [0:23] ex0_frt_si; + wire [0:23] ex0_frt_so; + + wire [0:5] ex0_instr_fra; + wire ex0_instr_fra_v; + wire [0:5] ex0_instr_frb; + wire ex0_instr_frb_v; + wire [0:5] ex0_instr_frc; + wire ex0_instr_frc_v; + wire [0:5] ex0_instr_frs; + wire ex0_instr_match; + wire ex1_instr_act; + + wire [0:3] ex0_instr_v; + wire [0:3] ex0_instr_valid; + wire ex0_instr_vld; + wire ex0_isRam; + wire ex0_is_ucode; + wire [0:6] ex0_itag; + + wire [64-(2**REGMODE):63] slowspr_data_out_int; + wire slowspr_done_out_int; + + wire [0:7] ex0_iu_si; + wire [0:7] ex0_iu_so; + + wire ex0_ucode_preissue; + + wire ex1_axu_v; + wire ex1_byp_a; + wire ex1_byp_b; + wire ex1_byp_c; + + wire ex1_bypsel_a_load3; + wire ex1_bypsel_b_load3; + wire ex1_bypsel_c_load3; + wire ex1_bypsel_s_load3; + + wire ex1_bypsel_a_load0; + wire ex1_bypsel_a_load1; + wire ex1_bypsel_a_load2; + wire ex1_bypsel_a_reload0; + wire ex1_bypsel_a_reload1; + wire ex1_bypsel_a_reload2; + + wire ex1_bypsel_a_res0; + wire ex1_bypsel_a_res1; + wire ex1_bypsel_a_res2; + wire ex1_bypsel_b_load0; + wire ex1_bypsel_b_load1; + wire ex1_bypsel_b_load2; + wire ex1_bypsel_b_reload0; + wire ex1_bypsel_b_reload1; + wire ex1_bypsel_b_reload2; + + wire ex1_bypsel_b_res0; + wire ex1_bypsel_b_res1; + wire ex1_bypsel_b_res2; + wire ex1_bypsel_c_load0; + wire ex1_bypsel_c_load1; + wire ex1_bypsel_c_load2; + wire ex1_bypsel_c_reload0; + wire ex1_bypsel_c_reload1; + wire ex1_bypsel_c_reload2; + + wire ex1_bypsel_c_res0; + wire ex1_bypsel_c_res1; + wire ex1_bypsel_c_res2; + wire ex1_bypsel_s_load0; + wire ex1_bypsel_s_load1; + wire ex1_bypsel_s_load2; + wire ex1_bypsel_s_reload0; + wire ex1_bypsel_s_reload1; + wire ex1_bypsel_s_reload2; + + wire ex1_bypsel_s_res0; + wire ex1_bypsel_s_res1; + wire ex1_bypsel_s_res2; + wire [0:4] ex1_cr_bf; + wire ex1_cr_val; + wire [0:4] ex1_crbf_si; + wire [0:4] ex1_crbf_so; + + wire ex1_dp; + wire ex1_dporsp; + wire ex1_expte; + wire ex1_fabs; + wire ex1_fadd; + wire ex1_fcfid; + wire ex1_fcfids; + wire ex1_fcfidu; + wire ex1_fcfidus; + wire ex1_fcfiwu; + wire ex1_fcfiwus; + wire ex1_fcmpo; + wire ex1_fcmpu; + wire ex1_fcpsgn; + wire ex1_fctid; + wire ex1_fctidu; + wire ex1_fctiduz; + wire ex1_fctidz; + wire ex1_fctiw; + wire ex1_fctiwu; + wire ex1_fctiwuz; + wire ex1_fctiwz; + wire ex1_fdiv; + wire ex1_fdivs; + wire [0:1] ex1_fdivsqrt_start; + wire [0:1] ex1_fdivsqrt_start_din; + wire ex1_fmadd; + wire ex1_fmr; + wire ex1_fmsub; + wire ex1_fmul; + wire ex1_fnabs; + wire ex1_fneg; + wire ex1_fnmadd; + wire ex1_fnmsub; + wire [0:5] ex1_fpscr_addr; + wire [0:3] ex1_fpscr_bit_data; + wire [0:3] ex1_fpscr_bit_mask; + wire ex1_fpscr_moves; + wire [0:8] ex1_fpscr_nib_mask; + wire ex1_fpscr_wen; + wire ex1_fpscr_wen_din; + wire ex1_fra_v; + wire ex1_frb_v; + wire ex1_frc_v; + wire ex1_fres; + wire ex1_frim; + wire ex1_frin; + wire ex1_frip; + wire ex1_friz; + wire ex1_from_ints; + wire ex1_frs_byp; + wire ex1_frsp; + wire ex1_frsqrte; + wire [0:29] ex1_frt_si; + wire [0:29] ex1_frt_so; + wire ex1_fsel; + wire ex1_fsqrt; + wire ex1_fsqrts; + wire ex1_fsub; + wire ex1_ftdiv; + wire ex1_ftsqrt; + + wire [0:31] ex1_instl_si; + wire [0:31] ex1_instl_so; + wire [0:31] ex1_instr; + wire [0:5] ex1_instr_fra; + wire ex1_instr_fra_v; + wire [0:5] ex1_instr_frb; + wire ex1_instr_frb_v; + wire [0:5] ex1_instr_frc; + wire ex1_instr_frc_v; + wire [0:5] ex1_instr_frs; + wire [0:5] ex1_instr_frt; + wire ex1_instr_match; + wire [0:3] ex1_instr_v; + wire [0:3] ex1_instr_valid; + + wire ex1_instr_v1_bufw; + wire ex1_instr_v1_bufx; + wire ex1_instr_v1_bufy; + wire ex1_instr_v1_bufz; + + wire ex1_isRam; + wire ex1_is_ucode; + wire [0:6] ex1_itag; + wire [0:13] ex1_itag_si; + wire [0:13] ex1_itag_so; + wire [0:14] ex1_iu_si; + wire [0:14] ex1_iu_so; + wire ex1_kill_wen; + + + wire ex1_instr_vld; + + wire ex1_loge; + + wire ex1_mcrfs; + wire [0:7] ex1_mcrfs_bfa; + wire ex1_mffs; + wire ex1_moves; + wire [0:7] ex1_mtfs_bf; + wire ex1_mtfsb0; + wire ex1_mtfsb1; + wire [0:3] ex1_mtfsb_bt; + wire ex1_mtfsf; + wire ex1_mtfsf_l; + wire [0:7] ex1_mtfsf_nib; + wire ex1_mtfsf_w; + wire ex1_mtfsfi; + + wire ex1_prenorm; + wire [0:5] ex1_primary; + wire ex1_record; + + wire ex1_rnd0; + wire ex1_rnd1; + wire [0:4] ex1_sec_aform; + wire [0:9] ex1_sec_xform; + wire ex1_sp; + wire ex1_str_v; + wire [0:1] ex1_tid; + wire [0:1] ex1_tid_bufw; + wire [0:1] ex1_tid_bufx; + wire [0:1] ex1_tid_bufy; + wire [0:1] ex1_tid_bufz ; + + wire ex1_to_ints; + + wire ex1_ucode_preissue; + wire ex1_ucode_preissue_din; + wire ex1_v; + wire [0:4] ex2_cr_bf; + wire ex2_cr_val; + wire ex2_cr_val_din; + wire [0:4] ex2_crbf_si; + wire [0:4] ex2_crbf_so; + wire [0:20] ex2_ctl_si; + wire [0:20] ex2_ctl_so; + wire [0:1] ex2_fdivsqrt_start; + wire [0:1] ex2_fdivsqrt_start_din; + wire [0:5] ex2_fpscr_addr; + wire ex2_fpscr_wen; + wire ex2_fra_v; + wire ex2_fra_valid; + wire ex2_frb_v; + wire ex2_frb_valid; + wire ex2_frc_v; + wire ex2_frc_valid; + wire ex2_frs_byp; + wire ex2_frs_byp_din; + wire [0:5] ex2_frt_si; + wire [0:5] ex2_frt_so; + + wire [0:3] ex2_ifar_val; + + wire [0:5] ex2_instr_frt; + wire ex2_instr_match; + wire [0:3] ex2_instr_v; + wire [0:3] ex2_instr_valid; + wire ex2_instr_vld; + wire ex2_isRam; + wire ex2_is_ucode; + wire [0:6] ex2_itag; + wire [0:15] ex2_itag_si; + wire [0:15] ex2_itag_so; + wire ex2_kill_wen; + + wire ex2_mcrfs; + + wire ex2_record; + wire ex2_str_v; + wire ex2_str_valid; + + wire ex2_ucode_preissue; + wire ex2_ucode_preissue_din; + wire ex2_v; + + wire [0:4] ex3_cr_bf; + wire ex3_cr_val; + wire [0:4] ex3_crbf_si; + wire [0:4] ex3_crbf_so; + wire [0:6] ex3_ctlng_si; + wire [0:6] ex3_ctlng_so; + wire [0:23] ex3_ctl_si; + wire [0:23] ex3_ctl_so; + + wire [0:1] ex3_fdivsqrt_start; + + + wire [0:1] ex3_fdivsqrt_start_din; + wire [0:3] ex3_flush2ucode; + + + + + wire [0:5] ex3_fpscr_addr; + wire ex3_fpscr_wen; + wire ex3_fra_v; + wire ex3_frb_v; + wire ex3_frc_v; + wire ex3_frs_byp; + + wire [0:3] ex3_ifar_val; + + wire [0:5] ex3_instr_frt; + wire ex3_instr_match; + wire [0:3] ex3_instr_v; + wire [0:3] ex3_instr_vns; + + wire ex3_instr_vld; + wire ex4_instr_vld; + wire ex5_instr_vld; + wire ex6_instr_vld; + wire ex7_instr_vld; + wire ex8_instr_vld; + wire ex9_instr_vld; + + wire [0:7] event_bus_d; + wire [0:7] event_bus_q; + + wire [0:3] ex3_instr_valid; + wire ex3_isRam; + wire ex3_is_ucode; + wire [0:6] ex3_itag; + wire [0:15] ex3_itag_si; + wire [0:15] ex3_itag_so; + wire ex3_kill_wen; + wire ex3_mcrfs; + wire [0:3] ex3_n_flush; + + wire ex3_record; + + + wire ex3_stdv_si; + wire ex3_stdv_so; + + wire ex3_store_v; + wire ex3_store_valid; + wire ex3_str_v; + wire ex3_ucode_preissue; + wire ex3_ucode_preissue_din; + wire ex4_b_den_flush; + wire [0:4] ex4_cr_bf; + wire ex4_cr_val; + wire [0:4] ex4_crbf_si; + wire [0:4] ex4_crbf_so; + wire [0:29] ex4_ctl_si; + wire [0:29] ex4_ctl_so; + wire [0:6] ex5_divsqrt_itag; + wire [0:1] ex4_fdivsqrt_start; + wire [0:1] ex4_fdivsqrt_start_din; + wire [0:3] ex4_flush2ucode; + wire [0:5] ex4_fpscr_addr; + wire ex4_fpscr_wen; + wire [0:5] ex4_instr_frt; + wire ex4_instr_match; + wire [0:3] ex4_instr_v; + wire [0:3] ex4_instr_vns; + wire [0:3] ex5_instr_vns; + wire ex3_instr_vns_taken; + wire ex4_instr_vns_taken_din; + wire ex4_instr_vns_taken; + wire ex5_instr_vns_taken; + + wire [0:3] ex4_instr_valid; + wire ex4_isRam; + wire ex4_is_ucode; + wire [0:6] ex4_itag; + wire [0:15] ex4_itag_si; + wire [0:15] ex4_itag_so; + wire ex4_kill_wen; + wire ex4_mcrfs; + wire [0:3] ex4_n_flush; + wire ex4_record; + wire ex7_perr_cancel; + + + // parity err --------- + wire perr_sm_running; + wire [0:5] perr_addr_l2; + + wire [0:1] ex4_regfile_err_det; + wire [0:1] ex5_regfile_err_det; + wire [0:1] ex6_regfile_err_det; + wire [0:1] ex7_regfile_err_det; + wire [0:1] ex8_regfile_err_det; + + wire ex0_regfile_ce; + wire ex0_regfile_ue; + + wire ex1_perr_sm_instr_v; + wire ex2_perr_sm_instr_v; + wire ex3_perr_sm_instr_v; + wire ex4_perr_sm_instr_v; + wire ex5_perr_sm_instr_v; + wire ex6_perr_sm_instr_v; + wire ex7_perr_sm_instr_v; + wire ex8_perr_sm_instr_v; + + wire [0:2] perr_sm_l2; + + wire [0:1] perr_tid_l2; + + wire ex7_is_fixperr; + + wire perr_si; + wire perr_so; + + //------------- end parity + + wire ex4_store_valid; + wire ex4_ucode_preissue; + wire ex4_ucode_preissue_din; + wire ex5_b_den_flush; + wire ex5_b_den_flush_din; + wire [0:3] ex5_cr; + wire [0:4] ex5_cr_bf; + wire ex5_cr_val; + wire ex5_cr_val_cp; + wire [0:4] ex5_crbf_si; + wire [0:4] ex5_crbf_so; + wire [0:21] ex5_ctl_si; + wire [0:21] ex5_ctl_so; + wire [0:5] ex6_divsqrt_fpscr_addr; + wire [59:63] ex5_eff_addr; + wire [0:1] ex5_fdivsqrt_start; + wire [0:1] ex5_fdivsqrt_start_din; + wire [0:5] ex5_fpscr_addr; + wire ex5_fpscr_wen; + wire ex5_fu_unavail; + wire [0:5] ex5_instr_frt; + wire [0:1] ex5_instr_tid; + wire [0:3] ex5_instr_v; + wire [0:1] ex5_cr_or_divsqrt_v; + wire [0:3] ex5_instr_valid; + wire ex5_isRam; + wire ex5_is_ucode; + wire [0:6] ex5_itag; + wire [0:6] ex5_itag_din; + wire [0:16] ex5_itag_si; + wire [0:16] ex5_itag_so; + wire ex5_kill_wen; + wire ex5_mcrfs; + + wire ex5_record; + wire ex5_ucode_preissue; + wire ex5_ucode_preissue_din; + + wire ex1_abort_a_din; + wire ex1_abort_b_din; + wire ex1_abort_c_din; + wire ex1_abort_s_din; + wire ex2_abort_a_din; + wire ex2_abort_b_din; + wire ex2_abort_c_din; + wire ex2_abort_s_din; + wire ex2_abort_a; + wire ex2_abort_b; + wire ex2_abort_c; + wire ex2_abort_s; + wire ex2_abort_a_q; + wire ex2_abort_b_q; + wire ex2_abort_c_q; + wire ex2_abort_s_q; + + wire ex3_abort_a; + wire ex3_abort_b; + wire ex3_abort_c; + wire ex3_abort_s; + wire ex3_abort_din; + wire ex4_abort; + + wire ex5_abort_l2; + wire ex6_abort; + wire ex6_abort_lq; + wire ex7_abort; + wire ex7_abort_lq; + wire ex8_abort; + wire ex8_abort_lq; + wire ex9_abort; + wire ex9_abort_q; + wire ex9_abort_lq; + wire ex4_abort_din; + wire ex5_abort_din; + wire ex5_abort_lq_din; + wire ex6_abort_din; + wire ex7_abort_din; + wire ex8_abort_din; + + + wire ex6_b_den_flush; + wire [0:3] ex6_cr; + wire [0:4] ex6_cr_bf; + wire [0:4] ex6_cr_bf_din; + wire ex6_cr_val; + wire ex5_cr_val_din; + wire [0:8] ex6_crbf_si; + wire [0:8] ex6_crbf_so; + wire [0:20] ex6_ctl_si; + wire [0:20] ex6_ctl_so; + wire [0:1] ex6_fdivsqrt_start; + wire [0:1] ex6_fdivsqrt_start_din; + wire ex6_fpr_wr_dis; + wire [0:5] ex6_fpscr_addr; + wire [0:5] ex6_fpscr_addr_din; + wire ex6_fpscr_move; + wire ex6_fpscr_wen; + wire ex6_fpscr_wen_din; + wire ex6_fu_unavail; + wire ex6_iflush_01; + wire ex6_iflush_23; + wire [0:3] ex6_iflush_b; + wire [0:3] ex6_instr_bypval; + wire ex6_instr_flush; + wire ex6_instr_flush_b; + wire [0:5] ex6_instr_frt; + wire [0:5] ex5_instr_frt_din; + wire [0:1] ex6_instr_tid; + wire [0:3] ex6_instr_v; + wire [0:3] ex6_instr_valid; + wire [0:3] ex5_instr_valid_din; + wire [0:3] ex6_instr_valid_din; + wire ex6_isRam; + wire ex6_is_ucode; + wire [0:6] ex6_itag; + wire [0:16] ex6_itag_si; + wire [0:16] ex6_itag_so; + wire ex6_kill_wen; + wire ex5_kill_wen_din; + wire ex6_kill_wen_q; + wire [0:7] ex6_load_addr; + wire ex6_load_v; + wire [0:7] ex6_reload_addr; + wire ex6_reload_v; + wire ex6_mcrfs; + wire ex5_mcrfs_din; + wire ex6_record; + wire ex5_record_din; + + + wire ex6_ucode_preissue; + wire ex6_ucode_preissue_din; + wire [0:1] ex7_ram_active; + wire ex7_b_den_flush; + wire [0:3] ex7_cr; + wire [0:4] ex7_cr_bf; + wire ex7_cr_val; + wire ex7_cr_val_din; + wire [0:8] ex7_crbf_si; + wire [0:8] ex7_crbf_so; + wire [0:22] ex7_ctl_si; + wire [0:22] ex7_ctl_so; + wire [0:1] ex7_fdivsqrt_start; + wire [0:1] ex7_fdivsqrt_start_din; + wire ex7_fpr_wr_dis; + wire [0:5] ex7_fpscr_addr; + wire ex7_fpscr_move; + wire ex7_fpscr_wen; + wire ex7_fu_unavail; + wire [0:5] ex7_instr_frt; + wire [0:5] ex7_instr_frt_din; + wire [0:1] ex7_instr_tid; + wire [0:3] ex7_instr_v; + wire [0:1] ex7_instr_v_din; + wire ex7_instr_valid; + wire ex7_isRam; + wire ex7_is_ucode; + wire [0:6] ex7_itag; + wire [0:17] ex7_itag_si; + wire [0:17] ex7_itag_so; + wire ex7_kill_wen; + wire ex6_kill_wen_din; + wire [0:17] ex7_laddr_si; + wire [0:17] ex7_laddr_so; + wire [0:7] ex7_load_addr; + wire ex7_load_v; + wire [0:7] ex7_reload_addr; + wire ex7_reload_v; + wire ex7_mcrfs; + wire ex7_mcrfs_din; + wire ex7_ram_done; + wire [3:13] ex7_ram_expo; + wire [0:52] ex7_ram_frac; + wire ex7_ram_sign; + wire ex7_record; + wire ex7_record_din; + wire ex7_record_v; + wire ex7_ucode_preissue; + wire ex7_ucode_preissue_din; + + wire ex8_b_den_flush; + wire ex8_b_den_flush_din; + wire [0:3] ex8_cr; + wire [0:4] ex8_cr_bf; + wire ex8_cr_val; + wire [0:31] ex8_ctl_si; + wire [0:31] ex8_ctl_so; + wire [0:1] ex8_fdivsqrt_start; + wire [0:1] ex8_fdivsqrt_start_din; + wire [0:1] ex9_fdivsqrt_start; + wire [0:1] ex8_fp_enabled; + wire ex8_fpr_wr_dis; + wire ex8_fpr_wr_dis_din; + wire ex8_fpscr_move; + wire ex8_fpscr_move_din; + wire [0:1] ex8_fu_unavail; + wire [0:5] ex8_instr_frt; + wire [0:1] ex8_instr_tid; + wire ex8_instr_v; + wire [0:1] ex8_instr_valid; + + wire [0:6] ex8_itag; + wire [0:7] ex8_itag_si; + wire [0:7] ex8_itag_so; + wire ex8_kill_wen; + wire [0:17] ex8_laddr_si; + wire [0:17] ex8_laddr_so; + wire [0:8] ex9_laddr_si; + wire [0:8] ex9_laddr_so; + wire [0:7] ex8_load_addr; + wire [0:7] ex9_load_addr; + wire ex9_load_v; + wire ex8_load_v; + wire [0:7] ex8_reload_addr; + wire ex8_reload_v; + wire [0:63] ex8_ram_data; + wire ex8_ram_done; + wire [3:13] ex8_ram_expo; + wire [0:52] ex8_ram_frac; + wire ex8_ram_sign; + wire ex8_record_v; + wire ex8_ucode_preissue; + wire ex8_ucode_preissue_din; + + wire [0:13] ex9_ctl_si; + wire [0:13] ex9_ctl_so; + wire [0:5] ex9_instr_frt; + wire [0:1] ex9_instr_tid; + wire ex9_instr_v; + wire [0:1] ex9_instr_valid; + wire ex9_kill_wen; + + wire force_t; + wire [0:1] fp_async_fex_d; + wire [0:1] fp_async_fex_q; + wire [0:1] fp_except_en_d; + wire [0:1] fp_except_en_q; + wire [0:1] fp_except_fex; + wire [0:1] fp_except_fex_async; + wire [0:1] fp_except_fx; + + wire int_word_ldst; + wire sign_ext_ldst; + + wire [0:1] msr_fe0; + wire [0:1] msr_fe1; + wire [0:1] msr_fp; + wire [0:1] fu_msr_fe0; + wire [0:1] fu_msr_fe1; + wire [0:1] fu_msr_fp; + + wire msr_fp_act; + wire [0:1] msr_gs_q; + wire [0:1] msr_pr_q; + wire [0:1] msr_gs_d; + wire [0:1] msr_pr_d; + + + wire [0:5] pri_ex1; + wire [0:64] ram_data_si; + wire [0:64] ram_data_so; + wire [0:34] perf_data_si; + wire [0:34] perf_data_so; + wire [0:7] event_bus_out_si; + wire [0:7] event_bus_out_so; + wire [0:0] ram_datav_si; + wire [0:0] ram_datav_so; + + wire [0:5] rf0_instr_fra; + wire [0:5] rf0_instr_frb; + wire [0:5] rf0_instr_frc; + wire [0:5] rf0_instr_frs; + wire rf0_instr_match; + wire [0:3] rf0_instr_tid_1hot; + wire [0:3] rf1_instr_iss; + wire [0:3] ex1_instr_iss; + wire [0:3] ex2_instr_iss; + + wire [0:3] rf0_instr_valid; + + wire [0:31] dbg_group3_lat_si; + wire [0:31] dbg_group3_lat_so; + + wire [0:1] rf0_tid; + wire ex0_fdiv; + wire ex0_fdivs; + wire ex0_fsqrt; + wire ex0_fsqrts; + wire [20:31] sec_ex1; + wire sg_0; + wire single_precision_ldst; + wire [0:9] slowspr_in_addr; + wire [64-(2**REGMODE):63] slowspr_in_data; + wire slowspr_in_done; + wire [0:1] slowspr_in_etid; + wire slowspr_in_rw; + wire slowspr_in_val; + wire [0:9] slowspr_out_addr; + wire [64-(2**REGMODE):63] slowspr_out_data; + wire slowspr_out_done; + wire [0:1] slowspr_out_etid; + wire slowspr_out_rw; + wire slowspr_out_val; + wire slowspr_val_in_int; + wire [64-(2**REGMODE):63] slowspr_data_in_int; + + (* analysis_not_referenced="TRUE" *) // unused + wire [0:47] spare_unused; + wire [0:14] spr_ctl_si; + wire [0:14] spr_ctl_so; + wire [64-(2**REGMODE):63] spr_data_si; + wire [64-(2**REGMODE):63] spr_data_so; + wire st_ex1; + wire [0:3] event_en_d; + wire [0:3] event_en_q; + wire [0:2] event_count_mode_q; + + wire [0:14] unit_bus_in_t0; + wire [0:14] unit_bus_in_t1; + wire [0:3] event_bus_out_t0; + wire [0:3] event_bus_out_t1; + + + wire [0:14] t0_events; + wire [0:14] t1_events; + + wire instr_trace_mode_q; + wire [0:1] instr_trace_tid_q; + + wire thold_0; + wire thold_0_b; + wire tihi; + wire tiup; + wire tilo; + wire tidn; + wire [0:31] trace_data_in; + wire [0:31] trace_data_out; + wire [0:11] trg_group0; + wire [0:11] trg_group1; + wire [0:11] trg_group2; + wire [0:11] trg_group3; + wire [0:63] divsqrt_debug; + wire [0:3] xu_ex0_flush; + wire [0:3] xu_ex1_flush; + wire [0:3] xu_ex2_flush; + wire [0:3] xu_ex3_flush; + wire [0:3] xu_ex4_flush; + wire [0:3] xu_ex5_flush; + wire [0:3] xu_ex6_flush; + wire [0:3] xu_ex7_flush; + wire [0:3] xu_ex8_flush; + wire [0:3] xu_ex9_flush; + wire [0:3] xu_rf0_flush; + wire ex6_divsqrt_v; + wire ex6_divsqrt_v_suppress; + wire ex5_divsqrt_v; + wire ex5_any_cr_v; + + wire func_slp_sl_thold_0; + wire func_slp_sl_force; + wire func_slp_sl_thold_0_b; + wire cfg_slat_d2clk; + wire [0:`NCLK_WIDTH-1] cfg_slat_lclk; + + assign tilo = 1'b0; + assign tihi = 1'b1; + assign tidn = 1'b0; + assign tiup = 1'b1; + + + assign rf0_act_b = ~(|(rv_axu0_vld)); + + // cp flush + assign cp_flush_int[0] = cp_flush[0]; + + generate + if (THREADS == 1) + begin : dcd_flush_thr1_1 + assign cp_flush_int[1] = tilo; + end + endgenerate + generate + if (THREADS == 2) + begin : dcd_flush_thr2_1 + assign cp_flush_int[1] = cp_flush[1]; + end + endgenerate + + // Latches + + tri_rlmlatch_p #(.INIT(0) ) cp_flush_reg0( + .nclk(nclk), + .act(tihi), + .force_t(force_t), + .delay_lclkr(delay_lclkr[9]), + .d_mode(tiup), + .mpw1_b(mpw1_b[9]), + .mpw2_b(mpw2_b[1]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(cp_flush_reg0_si), + .scout(cp_flush_reg0_so), + //------------------------------------------- + .din(cp_flush_int[0]), + //------------------------------------------- + .dout(cp_flush_q[0]) + ); + //------------------------------------------- + + // Latches + + tri_rlmlatch_p #(.INIT(0) ) cp_flush_reg1( + .nclk(nclk), + .act(tihi), + .force_t(force_t), + .delay_lclkr(delay_lclkr[9]), + .d_mode(tiup), + .mpw1_b(mpw1_b[9]), + .mpw2_b(mpw2_b[1]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(cp_flush_reg1_si), + .scout(cp_flush_reg1_so), + //------------------------------------------- + .din(cp_flush_int[1]), + //------------------------------------------- + .dout(cp_flush_q[1]) + ); + //------------------------------------------- + + generate + if (THREADS == 1) + begin : dcd_flush_thr1_2 + assign xu_rf0_flush[0] = cp_flush_q[0]; + assign xu_ex0_flush[0] = cp_flush_q[0]; + assign xu_ex1_flush[0] = cp_flush_q[0]; + assign xu_ex2_flush[0] = cp_flush_q[0]; + assign xu_ex3_flush[0] = cp_flush_q[0]; + assign xu_ex4_flush[0] = cp_flush_q[0]; + assign xu_ex5_flush[0] = cp_flush_q[0]; + assign xu_ex6_flush[0] = cp_flush_q[0]; + assign xu_ex7_flush[0] = cp_flush_q[0]; + assign xu_ex8_flush[0] = cp_flush_q[0]; + assign xu_ex9_flush[0] = cp_flush_q[0]; + assign xu_rf0_flush[1:3] = {3{tilo}}; + assign xu_ex0_flush[1:3] = {3{tilo}}; + assign xu_ex1_flush[1:3] = {3{tilo}}; + assign xu_ex2_flush[1:3] = {3{tilo}}; + assign xu_ex3_flush[1:3] = {3{tilo}}; + assign xu_ex4_flush[1:3] = {3{tilo}}; + assign xu_ex5_flush[1:3] = {3{tilo}}; + assign xu_ex6_flush[1:3] = {3{tilo}}; + assign xu_ex7_flush[1:3] = {3{tilo}}; + assign xu_ex8_flush[1:3] = {3{tilo}}; + assign xu_ex9_flush[1:3] = {3{tilo}}; + end + endgenerate + + generate + if (THREADS == 2) + begin : dcd_flush_thr2_2 + assign xu_rf0_flush[0:1] = cp_flush_q[0:1]; + assign xu_ex0_flush[0:1] = cp_flush_q[0:1]; + assign xu_ex1_flush[0:1] = cp_flush_q[0:1]; + assign xu_ex2_flush[0:1] = cp_flush_q[0:1]; + assign xu_ex3_flush[0:1] = cp_flush_q[0:1]; + assign xu_ex4_flush[0:1] = cp_flush_q[0:1]; + assign xu_ex5_flush[0:1] = cp_flush_q[0:1]; + assign xu_ex6_flush[0:1] = cp_flush_q[0:1]; + assign xu_ex7_flush[0:1] = cp_flush_q[0:1]; + assign xu_ex8_flush[0:1] = cp_flush_q[0:1]; + assign xu_ex9_flush[0:1] = cp_flush_q[0:1]; + assign xu_rf0_flush[2:3] = {2{tilo}}; + assign xu_ex0_flush[2:3] = {2{tilo}}; + assign xu_ex1_flush[2:3] = {2{tilo}}; + assign xu_ex2_flush[2:3] = {2{tilo}}; + assign xu_ex3_flush[2:3] = {2{tilo}}; + assign xu_ex4_flush[2:3] = {2{tilo}}; + assign xu_ex5_flush[2:3] = {2{tilo}}; + assign xu_ex6_flush[2:3] = {2{tilo}}; + assign xu_ex7_flush[2:3] = {2{tilo}}; + assign xu_ex8_flush[2:3] = {2{tilo}}; + assign xu_ex9_flush[2:3] = {2{tilo}}; + end + endgenerate + + //---------------------------------------------------------------------- + // Pervasive + + + tri_plat #( .WIDTH(3)) thold_reg_0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(flush), + .din({thold_1, + cfg_sl_thold_1, + func_slp_sl_thold_1}), + .q({thold_0, + cfg_sl_thold_0, + func_slp_sl_thold_0}) + ); + + + tri_plat sg_reg_0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(flush), + .din(sg_1), + .q(sg_0) + ); + + + tri_lcbor lcbor_0( + .clkoff_b(clkoff_b), + .thold(thold_0), + .sg(sg_0), + .act_dis(act_dis), + .force_t(force_t), + .thold_b(thold_0_b) + ); + + + tri_lcbor cfg_sl_lcbor_0( + .clkoff_b(clkoff_b), + .thold(cfg_sl_thold_0), + .sg(sg_0), + .act_dis(act_dis), + .force_t(cfg_sl_force), + .thold_b(cfg_sl_thold_0_b) + ); + + tri_lcbor func_slp_sl_lcbor_0( + .clkoff_b(clkoff_b), + .thold(func_slp_sl_thold_0), + .sg(sg_0), + .act_dis(act_dis), + .force_t(func_slp_sl_force), + .thold_b(func_slp_sl_thold_0_b) + ); + + tri_lcbs lcbs_cfg( + .vd(vdd), + .gd(gnd), + .delay_lclkr(delay_lclkr[9]), + .nclk(nclk), + .force_t(cfg_sl_force), + .thold_b(cfg_sl_thold_0_b), + .dclk(cfg_slat_d2clk), + .lclk(cfg_slat_lclk) + ); + + tri_slat_scan #(.WIDTH(2), .INIT(0), .RESET_INVERTS_SCAN(1'b1)) cfg_stg( + .vd(vdd), + .gd(gnd), + .dclk(cfg_slat_d2clk), + .lclk(cfg_slat_lclk), + .scan_in({ccfg_scan_in, bcfg_scan_in}), + .scan_out({ccfg_scan_out,bcfg_scan_out}) + ); + + + //---------------------------------------------------------------------- + // Act Latches + + generate + if (THREADS == 1) + begin : dcd_msr_bits_thr1_2 + assign fu_msr_fp[0] = xu_fu_msr_fp[0]; + assign fu_msr_fp[1] = tidn; + assign fu_msr_fe0[0] = xu_fu_msr_fe0[0]; + assign fu_msr_fe0[1] = tidn; + assign fu_msr_fe1[0] = xu_fu_msr_fe1[0]; + assign fu_msr_fe1[1] = tidn; + end + endgenerate + + generate + if (THREADS == 2) + begin : dcd_msr_bits_thr2_2 + assign fu_msr_fp = xu_fu_msr_fp; + assign fu_msr_fe0 = xu_fu_msr_fe0; + assign fu_msr_fe1 = xu_fu_msr_fe1; + end + endgenerate + + tri_rlmreg_p #(.INIT(0), .WIDTH(8)) act_lat( + .nclk(nclk), + .act(tihi), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[9]), + .mpw1_b(mpw1_b[9]), + .mpw2_b(mpw2_b[1]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(act_lat_si[0:7]), + .scout(act_lat_so[0:7]), + .din({ pc_fu_trace_bus_enable, + pc_fu_event_bus_enable, + fu_msr_fp, + fu_msr_fe0, + fu_msr_fe1 + }), + .dout({dbg0_act, + event_act, + msr_fp, + msr_fe0, + msr_fe1}) + ); + + assign msr_fp_act = |(msr_fp) | axucr0_q[60]; // note this was defaulted the other way in A2i + assign f_dcd_msr_fp_act = msr_fp_act; + + //---------------------------------------------------------------------- + // RF0 + + + + assign rf0_instr_match = iu_fu_rf0_instr_match; + + generate + if (THREADS == 1) + begin : dcd_tid_thr1_1 + assign rf0_tid[0] = iu_fu_rf0_tid[0]; + assign rf0_tid[1] = tidn; + end + endgenerate + + generate + if (THREADS == 2) + begin : dcd_tid_thr2_1 + assign rf0_tid[0:1] = iu_fu_rf0_tid[0:1]; + end + endgenerate + + generate + if (THREADS == 1) + begin : dcd_axu0_vld_thr1_1 + assign rf0_instr_tid_1hot[0] = rv_axu0_vld[0]; + assign rf0_instr_tid_1hot[1] = 1'b0; //rv_axu0_v(1); + assign rf0_instr_tid_1hot[2] = 1'b0; + assign rf0_instr_tid_1hot[3] = 1'b0; + end + endgenerate + + generate + if (THREADS == 2) + begin : dcd_axu0_vld_thr2_1 + assign rf0_instr_tid_1hot[0] = rv_axu0_vld[0]; + assign rf0_instr_tid_1hot[1] = rv_axu0_vld[1]; //rv_axu0_v(1); + assign rf0_instr_tid_1hot[2] = 1'b0; + assign rf0_instr_tid_1hot[3] = 1'b0; + end + endgenerate + + assign rf0_instr_valid[0:3] = rf0_instr_tid_1hot[0:3] & (~xu_rf0_flush[0:3]); + + + assign rf0_instr_fra[0:5] = iu_fu_rf0_fra[0:5]; + assign rf0_instr_frb[0:5] = iu_fu_rf0_frb[0:5]; + assign rf0_instr_frc[0:5] = iu_fu_rf0_frc[0:5]; + assign rf0_instr_frs[0:5] = iu_fu_rf0_frc[0:5]; // Store rides on s3!! (frc) + + //---------------------------------------------------------------------- + // EX0 + assign ex0_is_ucode = (rv_axu0_ex0_ucode[0] | rv_axu0_ex0_ucode[1]) & (~rv_axu0_ex0_ucode[2]); + assign ex0_ucode_preissue = rv_axu0_ex0_ucode[1] & ex0_instr_vld; + + // Flush Due to Speculative Loadhit + + // Latches + + + tri_rlmreg_p #(.INIT(0), .WIDTH(8), .NEEDS_SRESET(1)) ex0_iu( + .nclk(nclk), + .act(tihi), + .force_t(force_t), + .delay_lclkr(delay_lclkr[0]), + .d_mode(tiup), + .mpw1_b(mpw1_b[0]), + .mpw2_b(mpw2_b[0]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(ex0_iu_si[0:7]), + .scout(ex0_iu_so[0:7]), + //------------------------------------------- + .din({iu_fu_rf0_fra_v, + iu_fu_rf0_frb_v, + iu_fu_rf0_frc_v, + rf0_instr_valid[0:3], + rf0_instr_match + }), + //------------------------------------------- + .dout({ex0_instr_fra_v, + ex0_instr_frb_v, + ex0_instr_frc_v, + ex0_instr_v[0:3], + ex0_instr_match + }) + ); + //------------------------------------------- + + tri_rlmreg_p #(.INIT(0), .WIDTH(24)) ex0_frt( + .nclk(nclk), + .act(msr_fp_act), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[0]), + .mpw1_b(mpw1_b[0]), + .mpw2_b(mpw2_b[0]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(ex0_frt_si[0:23]), + .scout(ex0_frt_so[0:23]), + .din({rf0_instr_fra[0:5], + rf0_instr_frb[0:5], + rf0_instr_frc[0:5], + rf0_instr_frs[0:5]}), + //------------------------------------------- + .dout({ex0_instr_fra[0:5], + ex0_instr_frb[0:5], + ex0_instr_frc[0:5], + ex0_instr_frs[0:5] + }) + ); + //------------------------------------------- + + + + assign ex0_itag = rv_axu0_ex0_itag; + + assign ex0_instr_valid[0:3] = ex0_instr_v[0:3] & (~xu_ex0_flush[0:3]); + + assign ex1_fpscr_wen_din = rv_axu0_ex0_t1_v & (~ex0_ucode_preissue); + + //---------------------------------------------------------------------- + // EX1 + + // Latches + + tri_rlmreg_p #(.INIT(0), .WIDTH(15), .NEEDS_SRESET(1)) ex1_iu( + .nclk(nclk), + .act(tihi), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[1]), + .mpw1_b(mpw1_b[1]), + .mpw2_b(mpw2_b[0]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(ex1_iu_si[0:14]), + .scout(ex1_iu_so[0:14]), + //------------------------------------------- + .din({ex0_instr_fra_v, + ex0_instr_frb_v, + ex0_instr_frc_v, + ex0_instr_valid[0:3], + ex0_instr_match, + ex0_is_ucode, + ex0_ucode_preissue, + ex0_isRam, + ex0_instr_valid[1], + ex0_instr_valid[1], + ex0_instr_valid[1], + ex0_instr_valid[1] + }), + //------------------------------------------- + .dout({ ex1_instr_fra_v, + ex1_instr_frb_v, + ex1_instr_frc_v, + ex1_instr_v[0:3], + ex1_instr_match, + ex1_is_ucode, + ex1_ucode_preissue, + ex1_isRam, + ex1_instr_v1_bufw, + ex1_instr_v1_bufx, + ex1_instr_v1_bufy, + ex1_instr_v1_bufz +}) + ); + //------------------------------------------- + + assign ex0_isRam = tidn; + + + + + tri_rlmreg_p #(.INIT(0), .WIDTH(30)) ex1_frt( + .nclk(nclk), + .act(ex1_instr_act), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[1]), + .mpw1_b(mpw1_b[1]), + .mpw2_b(mpw2_b[0]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(ex1_frt_si[0:29]), + .scout(ex1_frt_so[0:29]), + .din({ rv_axu0_ex0_t2_p[0:5], + ex0_instr_fra[0:5], + ex0_instr_frb[0:5], + ex0_instr_frc[0:5], + ex0_instr_frs[0:5]}), + //------------------------------------------- + .dout({ ex1_instr_frt[0:5], + ex1_instr_fra[0:5], + ex1_instr_frb[0:5], + ex1_instr_frc[0:5], + ex1_instr_frs[0:5]}) + ); + //------------------------------------------- + + assign ex1_instr_act = ex0_instr_v[0] | ex0_instr_v[1] | ex1_instr_v[0] | ex1_instr_v[1]; + + + tri_rlmreg_p #(.INIT(0), .WIDTH(32)) ex1_instl( + .nclk(nclk), + .act(ex1_instr_act), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[1]), + .mpw1_b(mpw1_b[1]), + .mpw2_b(mpw2_b[0]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(ex1_instl_si[0:31]), + .scout(ex1_instl_so[0:31]), + .din(rv_axu0_ex0_instr[0:31]), + .dout(ex1_instr[0:31]) + ); + + + tri_rlmreg_p #(.INIT(0), .WIDTH(14)) ex1_itagl( + .nclk(nclk), + .act(tihi), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[1]), + .mpw1_b(mpw1_b[1]), + .mpw2_b(mpw2_b[0]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(ex1_itag_si), + .scout(ex1_itag_so), + //------------------------------------------- + .din({ex0_itag[0:6], + rv_axu0_ex0_t1_p[0:5], + ex1_fpscr_wen_din}), + //------------------------------------------- + .dout({ex1_itag[0:6], + ex1_fpscr_addr[0:5], + ex1_fpscr_wen}) + ); + //------------------------------------------- + + assign f_dcd_ex1_fpscr_addr = ex1_fpscr_addr; + assign f_dcd_ex1_instr_frt = ex1_instr_frt; + assign f_dcd_ex1_instr_tid = ex1_instr_v[0:3] & (~xu_ex1_flush[0:3]); + assign f_dcd_ex1_divsqrt_cr_bf = ex1_cr_bf; + + + tri_rlmreg_p #(.INIT(0), .WIDTH(5)) ex1_crbf( + .nclk(nclk), + .act(tihi), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[1]), + .mpw1_b(mpw1_b[1]), + .mpw2_b(mpw2_b[0]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(ex1_crbf_si[0:4]), + .scout(ex1_crbf_so[0:4]), + .din(rv_axu0_ex0_t3_p[1:5]), + .dout(ex1_cr_bf[0:4]) + ); + + // Flushes + + assign ex1_instr_valid[0:3] = ex1_instr_v[0:3] & (~xu_ex1_flush[0:3]) & {4{((~|(ex1_fdivsqrt_start)) | ex1_ucode_preissue)}}; + + assign ex1_instr_vld = (ex1_instr_v[0] & (~xu_ex1_flush[0])) | (ex1_instr_v[1] & (~xu_ex1_flush[1])) ; + assign ex1_str_v = |(ex1_instr_valid[0:3]) & st_ex1; + assign f_dcd_ex1_sto_v = ex1_str_v; + +// temp: assumes only 2 threads for timing (this is encoded) + assign ex1_tid[0] = tidn; + assign ex1_tid[1] = ex1_instr_v[1]; + + assign ex1_tid_bufw[0] = tidn; + assign ex1_tid_bufw[1] = ex1_instr_v1_bufw; + + assign ex1_tid_bufx[0] = tidn; + assign ex1_tid_bufx[1] = ex1_instr_v1_bufx; + + assign ex1_tid_bufy[0] = tidn; + assign ex1_tid_bufy[1] = ex1_instr_v1_bufy; + + assign ex1_tid_bufz[0] = tidn; + assign ex1_tid_bufz[1] = ex1_instr_v1_bufz; + + //---------------------------------------------------------------------- + // Bypass Writethru Detect in EX1 + + // 000000 <= FPR lev0 + // 100000 <= ex7 load bypass into A lev1 + // 010000 <= ex7 load bypass into c lev1 + // 001000 <= ex7 load bypass into B lev1 + // 000100 <= ex7 bypass into A lev1 + // 000010 <= ex7 bypass into c lev1 + // 000001 <= ex7 bypass into B lev1 + + // Result Bypass, res EX7 and dep in EX1 + assign ex1_bypsel_a_res0 = ({ex7_instr_tid[0:1], ex7_instr_frt[0:5]}) == ({ex1_tid_bufw[0:1], ex1_instr_fra[0:5]}) & (ex7_instr_valid & (~ex7_kill_wen)) & ex1_instr_fra_v; + assign ex1_bypsel_c_res0 = ({ex7_instr_tid[0:1], ex7_instr_frt[0:5]}) == ({ex1_tid_bufw[0:1], ex1_instr_frc[0:5]}) & (ex7_instr_valid & (~ex7_kill_wen)) & ex1_instr_frc_v; + assign ex1_bypsel_b_res0 = ({ex7_instr_tid[0:1], ex7_instr_frt[0:5]}) == ({ex1_tid_bufw[0:1], ex1_instr_frb[0:5]}) & (ex7_instr_valid & (~ex7_kill_wen)) & ex1_instr_frb_v; + + assign ex1_bypsel_s_res0 = ({ex7_instr_tid[0:1], ex7_instr_frt[0:5]}) == ({ex1_tid_bufw[0:1], ex1_instr_frs[0:5]}) & (ex7_instr_valid & (~ex7_kill_wen)) & ex1_str_v; + + // Writethru case, res EX8 dep EX1 + assign ex1_bypsel_a_res1 = ({ex8_instr_tid[0:1], ex8_instr_frt[0:5]}) == ({ex1_tid_bufw[0:1], ex1_instr_fra[0:5]}) & ex8_instr_v & (~ex8_kill_wen) & ex1_instr_fra_v & (~ex1_bypsel_a_res0) & (~ex1_bypsel_a_load0); + assign ex1_bypsel_c_res1 = ({ex8_instr_tid[0:1], ex8_instr_frt[0:5]}) == ({ex1_tid_bufw[0:1], ex1_instr_frc[0:5]}) & ex8_instr_v & (~ex8_kill_wen) & ex1_instr_frc_v & (~ex1_bypsel_c_res0) & (~ex1_bypsel_c_load0); + assign ex1_bypsel_b_res1 = ({ex8_instr_tid[0:1], ex8_instr_frt[0:5]}) == ({ex1_tid_bufw[0:1], ex1_instr_frb[0:5]}) & ex8_instr_v & (~ex8_kill_wen) & ex1_instr_frb_v & (~ex1_bypsel_b_res0) & (~ex1_bypsel_b_load0); + + assign ex1_bypsel_s_res1 = ({ex8_instr_tid[0:1], ex8_instr_frt[0:5]}) == ({ex1_tid_bufw[0:1], ex1_instr_frs[0:5]}) & ex8_instr_v & (~ex8_kill_wen) & ex1_str_v; + + // Writethru case, res EX9 dep EX1 + assign ex1_bypsel_a_res2 = ({ex9_instr_tid[0:1], ex9_instr_frt[0:5]}) == ({ex1_tid_bufw[0:1], ex1_instr_fra[0:5]}) & ex9_instr_v & (~ex9_kill_wen) & ex1_instr_fra_v & (~ex1_bypsel_a_res0) & (~ex1_bypsel_a_load0) & (~ex1_bypsel_a_res1) & (~ex1_bypsel_a_load1); + assign ex1_bypsel_c_res2 = ({ex9_instr_tid[0:1], ex9_instr_frt[0:5]}) == ({ex1_tid_bufw[0:1], ex1_instr_frc[0:5]}) & ex9_instr_v & (~ex9_kill_wen) & ex1_instr_frc_v & (~ex1_bypsel_c_res0) & (~ex1_bypsel_c_load0) & (~ex1_bypsel_c_res1) & (~ex1_bypsel_c_load1); + assign ex1_bypsel_b_res2 = ({ex9_instr_tid[0:1], ex9_instr_frt[0:5]}) == ({ex1_tid_bufw[0:1], ex1_instr_frb[0:5]}) & ex9_instr_v & (~ex9_kill_wen) & ex1_instr_frb_v & (~ex1_bypsel_b_res0) & (~ex1_bypsel_b_load0) & (~ex1_bypsel_b_res1) & (~ex1_bypsel_b_load1); + + assign ex1_bypsel_s_res2 = ({ex9_instr_tid[0:1], ex9_instr_frt[0:5]}) == ({ex1_tid_bufw[0:1], ex1_instr_frs[0:5]}) & ex9_instr_v & (~ex9_kill_wen) & ex1_str_v; + + // LOADS + + generate + if (THREADS == 1) + begin : dcd_loadaddr_thr_1 + assign ex6_load_addr[0:7] = f_fpr_ex6_load_addr[0:7]; // no tid bit + assign ex6_reload_addr[0:7] = f_fpr_ex6_reload_addr[0:7]; // no tid bit + end + endgenerate + + generate + if (THREADS == 2) + begin : dcd_loadaddr_thr_2 + assign ex6_load_addr[0:7] = {f_fpr_ex6_load_addr[0], f_fpr_ex6_load_addr[7], f_fpr_ex6_load_addr[1:6]}; // bit 7 is the tid but only in the 2 thread model + assign ex6_reload_addr[0:7] = {f_fpr_ex6_reload_addr[0], f_fpr_ex6_reload_addr[7], f_fpr_ex6_reload_addr[1:6]}; // bit 7 is the tid but only in the 2 thread model + + end + endgenerate + + assign ex6_load_v = f_fpr_ex6_load_v; + + assign ex6_reload_v = f_fpr_ex6_reload_v; + + // Load Bypass, Load in EX6, dep EX1 ==> Load Use = 5 cycles, 4 bubbles + assign ex1_bypsel_a_load0 = (ex6_load_addr[0:7]) == ({ex1_tid_bufx[0:1], ex1_instr_fra[0:5]}) & ex6_load_v & ex1_instr_fra_v; + assign ex1_bypsel_c_load0 = (ex6_load_addr[0:7]) == ({ex1_tid_bufx[0:1], ex1_instr_frc[0:5]}) & ex6_load_v & ex1_instr_frc_v; + assign ex1_bypsel_b_load0 = (ex6_load_addr[0:7]) == ({ex1_tid_bufx[0:1], ex1_instr_frb[0:5]}) & ex6_load_v & ex1_instr_frb_v; + assign ex1_bypsel_s_load0 = (ex6_load_addr[0:7]) == ({ex1_tid_bufx[0:1], ex1_instr_frs[0:5]}) & ex6_load_v & ex1_str_v; + + // Writethru case, Load EX7 dep EX1 + assign ex1_bypsel_a_load1 = (ex7_load_addr[0:7]) == ({ex1_tid_bufx[0:1], ex1_instr_fra[0:5]}) & ex7_load_v & ex1_instr_fra_v & (~ex1_bypsel_a_load0) & (~ex1_bypsel_a_res0); + assign ex1_bypsel_c_load1 = (ex7_load_addr[0:7]) == ({ex1_tid_bufx[0:1], ex1_instr_frc[0:5]}) & ex7_load_v & ex1_instr_frc_v & (~ex1_bypsel_c_load0) & (~ex1_bypsel_c_res0); + assign ex1_bypsel_b_load1 = (ex7_load_addr[0:7]) == ({ex1_tid_bufx[0:1], ex1_instr_frb[0:5]}) & ex7_load_v & ex1_instr_frb_v & (~ex1_bypsel_b_load0) & (~ex1_bypsel_b_res0); + assign ex1_bypsel_s_load1 = (ex7_load_addr[0:7]) == ({ex1_tid_bufx[0:1], ex1_instr_frs[0:5]}) & ex7_load_v & ex1_str_v; + + // Writethru case, Load EX8 dep EX1 + assign ex1_bypsel_a_load2 = (ex8_load_addr[0:7]) == ({ex1_tid_bufy[0:1], ex1_instr_fra[0:5]}) & ex8_load_v & ex1_instr_fra_v & (~ex1_bypsel_a_load0) & (~ex1_bypsel_a_res0) & (~ex1_bypsel_a_load1) & (~ex1_bypsel_a_res1); + assign ex1_bypsel_c_load2 = (ex8_load_addr[0:7]) == ({ex1_tid_bufy[0:1], ex1_instr_frc[0:5]}) & ex8_load_v & ex1_instr_frc_v & (~ex1_bypsel_c_load0) & (~ex1_bypsel_c_res0) & (~ex1_bypsel_c_load1) & (~ex1_bypsel_c_res1); + assign ex1_bypsel_b_load2 = (ex8_load_addr[0:7]) == ({ex1_tid_bufy[0:1], ex1_instr_frb[0:5]}) & ex8_load_v & ex1_instr_frb_v & (~ex1_bypsel_b_load0) & (~ex1_bypsel_b_res0) & (~ex1_bypsel_b_load1) & (~ex1_bypsel_b_res1); + assign ex1_bypsel_s_load2 = (ex8_load_addr[0:7]) == ({ex1_tid_bufy[0:1], ex1_instr_frs[0:5]}) & ex8_load_v & ex1_str_v; + + // Writethru case, just for abort, Load EX9 dep EX1 + assign ex1_bypsel_a_load3 = (ex9_load_addr[0:7]) == ({ex1_tid_bufy[0:1], ex1_instr_fra[0:5]}) & ex9_load_v & ex1_instr_fra_v ; + assign ex1_bypsel_c_load3 = (ex9_load_addr[0:7]) == ({ex1_tid_bufy[0:1], ex1_instr_frc[0:5]}) & ex9_load_v & ex1_instr_frc_v ; + assign ex1_bypsel_b_load3 = (ex9_load_addr[0:7]) == ({ex1_tid_bufy[0:1], ex1_instr_frb[0:5]}) & ex9_load_v & ex1_instr_frb_v ; + assign ex1_bypsel_s_load3 = (ex9_load_addr[0:7]) == ({ex1_tid_bufy[0:1], ex1_instr_frs[0:5]}) & ex9_load_v & ex1_str_v; + + + + // reLoad Bypass, Load in EX6, dep EX1 ==> Load Use = 5 cycles, 4 bubbles + assign ex1_bypsel_a_reload0 = (ex6_reload_addr[0:7]) == ({ex1_tid_bufz[0:1], ex1_instr_fra[0:5]}) & ex6_reload_v & ex1_instr_fra_v & (~ex1_bypsel_a_load0) & (~ex1_bypsel_a_res0) & (~ex1_bypsel_a_load1) & (~ex1_bypsel_a_res1); + assign ex1_bypsel_c_reload0 = (ex6_reload_addr[0:7]) == ({ex1_tid_bufz[0:1], ex1_instr_frc[0:5]}) & ex6_reload_v & ex1_instr_frc_v & (~ex1_bypsel_c_load0) & (~ex1_bypsel_c_res0) & (~ex1_bypsel_c_load1) & (~ex1_bypsel_c_res1); + assign ex1_bypsel_b_reload0 = (ex6_reload_addr[0:7]) == ({ex1_tid_bufz[0:1], ex1_instr_frb[0:5]}) & ex6_reload_v & ex1_instr_frb_v & (~ex1_bypsel_b_load0) & (~ex1_bypsel_b_res0) & (~ex1_bypsel_b_load1) & (~ex1_bypsel_b_res1); + assign ex1_bypsel_s_reload0 = (ex6_reload_addr[0:7]) == ({ex1_tid_bufz[0:1], ex1_instr_frs[0:5]}) & ex6_reload_v & ex1_str_v; + + // reLoad Writethru case, Load EX7 dep EX1 + assign ex1_bypsel_a_reload1 = (ex7_reload_addr[0:7]) == ({ex1_tid_bufz[0:1], ex1_instr_fra[0:5]}) & ex7_reload_v & ex1_instr_fra_v & (~ex1_bypsel_a_reload0) & (~ex1_bypsel_a_res0) & (~ex1_bypsel_a_load0) & (~ex1_bypsel_a_res0) & (~ex1_bypsel_a_load1) & (~ex1_bypsel_a_res1); + assign ex1_bypsel_c_reload1 = (ex7_reload_addr[0:7]) == ({ex1_tid_bufz[0:1], ex1_instr_frc[0:5]}) & ex7_reload_v & ex1_instr_frc_v & (~ex1_bypsel_c_reload0) & (~ex1_bypsel_c_res0) & (~ex1_bypsel_c_load0) & (~ex1_bypsel_c_res0) & (~ex1_bypsel_c_load1) & (~ex1_bypsel_c_res1); + assign ex1_bypsel_b_reload1 = (ex7_reload_addr[0:7]) == ({ex1_tid_bufz[0:1], ex1_instr_frb[0:5]}) & ex7_reload_v & ex1_instr_frb_v & (~ex1_bypsel_b_reload0) & (~ex1_bypsel_b_res0) & (~ex1_bypsel_b_load0) & (~ex1_bypsel_b_res0) & (~ex1_bypsel_b_load1) & (~ex1_bypsel_b_res1); + assign ex1_bypsel_s_reload1 = (ex7_reload_addr[0:7]) == ({ex1_tid_bufz[0:1], ex1_instr_frs[0:5]}) & ex7_reload_v & ex1_str_v; + + // reLoad Writethru case, Load EX8 dep EX1 + assign ex1_bypsel_a_reload2 = (ex8_reload_addr[0:7]) == ({ex1_tid_bufz[0:1], ex1_instr_fra[0:5]}) & ex8_reload_v & ex1_instr_fra_v & (~ex1_bypsel_a_reload0) & (~ex1_bypsel_a_res0) & (~ex1_bypsel_a_reload1) & (~ex1_bypsel_a_res1) & (~ex1_bypsel_a_load0) & (~ex1_bypsel_a_res0) & (~ex1_bypsel_a_load1) & (~ex1_bypsel_a_res1); + assign ex1_bypsel_c_reload2 = (ex8_reload_addr[0:7]) == ({ex1_tid_bufz[0:1], ex1_instr_frc[0:5]}) & ex8_reload_v & ex1_instr_frc_v & (~ex1_bypsel_c_reload0) & (~ex1_bypsel_c_res0) & (~ex1_bypsel_c_reload1) & (~ex1_bypsel_c_res1) & (~ex1_bypsel_c_load0) & (~ex1_bypsel_c_res0) & (~ex1_bypsel_c_load1) & (~ex1_bypsel_c_res1); + assign ex1_bypsel_b_reload2 = (ex8_reload_addr[0:7]) == ({ex1_tid_bufz[0:1], ex1_instr_frb[0:5]}) & ex8_reload_v & ex1_instr_frb_v & (~ex1_bypsel_b_reload0) & (~ex1_bypsel_b_res0) & (~ex1_bypsel_b_reload1) & (~ex1_bypsel_b_res1) & (~ex1_bypsel_b_load0) & (~ex1_bypsel_b_res0) & (~ex1_bypsel_b_load1) & (~ex1_bypsel_b_res1); + assign ex1_bypsel_s_reload2 = (ex8_reload_addr[0:7]) == ({ex1_tid_bufz[0:1], ex1_instr_frs[0:5]}) & ex8_reload_v & ex1_str_v; + + + + + assign f_dcd_ex1_bypsel_a_res1 = ex1_bypsel_a_res1; + assign f_dcd_ex1_bypsel_b_res1 = ex1_bypsel_b_res1; + assign f_dcd_ex1_bypsel_c_res1 = ex1_bypsel_c_res1; + assign f_dcd_ex1_bypsel_a_load1 = ex1_bypsel_a_load1; + assign f_dcd_ex1_bypsel_b_load1 = ex1_bypsel_b_load1; + assign f_dcd_ex1_bypsel_c_load1 = ex1_bypsel_c_load1; + assign f_dcd_ex1_bypsel_a_reload1 = ex1_bypsel_a_reload1; + assign f_dcd_ex1_bypsel_b_reload1 = ex1_bypsel_b_reload1; + assign f_dcd_ex1_bypsel_c_reload1 = ex1_bypsel_c_reload1; + + assign f_dcd_ex1_bypsel_s_res1 = ex1_bypsel_s_res1; + assign f_dcd_ex1_bypsel_s_load1 = ex1_bypsel_s_load1; + assign f_dcd_ex1_bypsel_s_reload1 = ex1_bypsel_s_reload1; + + assign f_dcd_ex1_bypsel_a_res2 = ex1_bypsel_a_res2; + assign f_dcd_ex1_bypsel_b_res2 = ex1_bypsel_b_res2; + assign f_dcd_ex1_bypsel_c_res2 = ex1_bypsel_c_res2; + assign f_dcd_ex1_bypsel_a_load2 = ex1_bypsel_a_load2; + assign f_dcd_ex1_bypsel_b_load2 = ex1_bypsel_b_load2; + assign f_dcd_ex1_bypsel_c_load2 = ex1_bypsel_c_load2; + assign f_dcd_ex1_bypsel_a_reload2 = ex1_bypsel_a_reload2; + assign f_dcd_ex1_bypsel_b_reload2 = ex1_bypsel_b_reload2; + assign f_dcd_ex1_bypsel_c_reload2 = ex1_bypsel_c_reload2; + + assign f_dcd_ex1_bypsel_s_res2 = ex1_bypsel_s_res2; + assign f_dcd_ex1_bypsel_s_load2 = ex1_bypsel_s_load2; + assign f_dcd_ex1_bypsel_s_reload2 = ex1_bypsel_s_reload2; + + + assign f_dcd_ex1_bypsel_a_res0 = ex1_bypsel_a_res0; + assign f_dcd_ex1_bypsel_a_load0 = ex1_bypsel_a_load0; + assign f_dcd_ex1_bypsel_a_reload0 = ex1_bypsel_a_reload0; + + assign f_dcd_ex1_bypsel_b_res0 = ex1_bypsel_b_res0; + assign f_dcd_ex1_bypsel_b_load0 = ex1_bypsel_b_load0; + assign f_dcd_ex1_bypsel_b_reload0 = ex1_bypsel_b_reload0; + + assign f_dcd_ex1_bypsel_c_res0 = ex1_bypsel_c_res0; + assign f_dcd_ex1_bypsel_c_load0 = ex1_bypsel_c_load0; + assign f_dcd_ex1_bypsel_c_reload0 = ex1_bypsel_c_reload0; + + assign f_dcd_ex1_bypsel_s_res0 = ex1_bypsel_s_res0; + assign f_dcd_ex1_bypsel_s_load0 = ex1_bypsel_s_load0; + assign f_dcd_ex1_bypsel_s_reload0 = ex1_bypsel_s_reload0; + + // operand valids for parity checking + assign ex1_byp_a = ex1_bypsel_a_res0 | ex1_bypsel_a_res1 | ex1_bypsel_a_res2 | ex1_bypsel_a_load0 | ex1_bypsel_a_load1 | ex1_bypsel_a_load2 | ex1_bypsel_a_reload0 | ex1_bypsel_a_reload1 | ex1_bypsel_a_reload2; + assign ex1_byp_b = ex1_bypsel_b_res0 | ex1_bypsel_b_res1 | ex1_bypsel_b_res2 | ex1_bypsel_b_load0 | ex1_bypsel_b_load1 | ex1_bypsel_b_load2 | ex1_bypsel_b_reload0 | ex1_bypsel_b_reload1 | ex1_bypsel_b_reload2; + assign ex1_byp_c = ex1_bypsel_c_res0 | ex1_bypsel_c_res1 | ex1_bypsel_c_res2 | ex1_bypsel_c_load0 | ex1_bypsel_c_load1 | ex1_bypsel_c_load2 | ex1_bypsel_c_reload0 | ex1_bypsel_c_reload1 | ex1_bypsel_c_reload2; + assign ex1_fra_v = ex1_instr_fra_v & (~ex1_byp_a); + assign ex1_frb_v = ex1_instr_frb_v & (~ex1_byp_b); + assign ex1_frc_v = ex1_instr_frc_v & (~ex1_byp_c); + assign ex1_frs_byp = ex1_bypsel_s_res0 | ex1_bypsel_s_res1 | ex1_bypsel_s_res2 | + ex1_bypsel_s_load0 | ex1_bypsel_s_load1 | ex1_bypsel_s_load2 | + ex1_bypsel_s_reload0 | ex1_bypsel_s_reload1 | ex1_bypsel_s_reload2; + + assign ex2_frs_byp_din = ex1_frs_byp & ex1_str_v; + + // grandchild stuff + assign ex1_abort_a_din = ((ex1_bypsel_a_load0 & ex6_abort_lq) | (ex1_bypsel_a_load1 & ex7_abort_lq) | (ex1_bypsel_a_load2 & ex8_abort_lq) | (ex1_bypsel_a_load3 & ex9_abort_lq) | + (ex1_bypsel_a_res0 & ex7_abort) | (ex1_bypsel_a_res1 & ex8_abort) | (ex1_bypsel_a_res2 & ex9_abort)) & ex1_instr_vld ; + + assign ex1_abort_b_din = ((ex1_bypsel_b_load0 & ex6_abort_lq) | (ex1_bypsel_b_load1 & ex7_abort_lq) | (ex1_bypsel_b_load2 & ex8_abort_lq) | (ex1_bypsel_b_load3 & ex9_abort_lq) | + (ex1_bypsel_b_res0 & ex7_abort) | (ex1_bypsel_b_res1 & ex8_abort) | (ex1_bypsel_b_res2 & ex9_abort)) & ex1_instr_vld ; + + assign ex1_abort_c_din = ((ex1_bypsel_c_load0 & ex6_abort_lq) | (ex1_bypsel_c_load1 & ex7_abort_lq) | (ex1_bypsel_c_load2 & ex8_abort_lq) | (ex1_bypsel_c_load3 & ex9_abort_lq) | + (ex1_bypsel_c_res0 & ex7_abort) | (ex1_bypsel_c_res1 & ex8_abort) | (ex1_bypsel_c_res2 & ex9_abort)) & ex1_instr_vld ; + + assign ex1_abort_s_din = ((ex1_bypsel_s_load0 & ex6_abort_lq) | (ex1_bypsel_s_load1 & ex7_abort_lq) | (ex1_bypsel_s_load2 & ex8_abort_lq) | (ex1_bypsel_s_load3 & ex9_abort_lq) | + (ex1_bypsel_s_res0 & ex7_abort) | (ex1_bypsel_s_res1 & ex8_abort) | (ex1_bypsel_s_res2 & ex9_abort)) & ex1_instr_vld ; + + + + + //------------------------------------------------------------------- + // Decode IOP + + assign ex1_primary[0:5] = ex1_instr[0:5]; + assign ex1_sec_xform[0:9] = ex1_instr[21:30]; + assign ex1_sec_aform[0:4] = ex1_instr[26:30]; + assign ex1_v = ex1_instr_v[0] | ex1_instr_v[1]; + assign ex1_axu_v = ex1_v | ex1_perr_sm_instr_v; + assign ex1_dp = (ex1_primary[0:5] == 6'b111111) & ex1_v & (~ex1_perr_sm_instr_v); + assign ex1_sp = (ex1_primary[0:5] == 6'b111011) & ex1_v & (~ex1_perr_sm_instr_v); + assign ex1_dporsp = ex1_dp | ex1_sp; + + assign ex1_fabs = ex1_dp & (ex1_sec_xform[0:9] == 10'b0100001000); + assign ex1_fadd = ex1_dporsp & (ex1_sec_aform[0:4] == 5'b10101); + assign ex1_fcfid = ex1_dp & (ex1_sec_xform[0:9] == 10'b1101001110); + assign ex1_fcfidu = ex1_dp & (ex1_sec_xform[0:9] == 10'b1111001110); + assign ex1_fcfids = ex1_sp & (ex1_sec_xform[0:9] == 10'b1101001110); + assign ex1_fcfidus = ex1_sp & (ex1_sec_xform[0:9] == 10'b1111001110); + assign ex1_fcfiwu = ex1_dp & (ex1_sec_xform[0:9] == 10'b0011001110); + assign ex1_fcfiwus = ex1_sp & (ex1_sec_xform[0:9] == 10'b0011001110); + assign ex1_fcmpo = ex1_dp & (ex1_sec_xform[0:9] == 10'b0000100000); + assign ex1_fcmpu = ex1_dp & (ex1_sec_xform[0:9] == 10'b0000000000); + assign ex1_fcpsgn = ex1_dp & (ex1_sec_xform[0:9] == 10'b0000001000); + assign ex1_fctid = ex1_dp & (ex1_sec_xform[0:9] == 10'b1100101110); + assign ex1_fctidu = ex1_dp & (ex1_sec_xform[0:9] == 10'b1110101110); + assign ex1_fctidz = ex1_dp & (ex1_sec_xform[0:9] == 10'b1100101111); + assign ex1_fctiduz = ex1_dp & (ex1_sec_xform[0:9] == 10'b1110101111); + assign ex1_fctiw = ex1_dp & (ex1_sec_xform[0:9] == 10'b0000001110); + assign ex1_fctiwu = ex1_dp & (ex1_sec_xform[0:9] == 10'b0010001110); + assign ex1_fctiwz = ex1_dp & (ex1_sec_xform[0:9] == 10'b0000001111); + assign ex1_fctiwuz = ex1_dp & (ex1_sec_xform[0:9] == 10'b0010001111); + assign ex1_fdiv = ex1_dp & (ex1_sec_aform[0:4] == 5'b10010); + assign ex1_fdivs = ex1_sp & (ex1_sec_aform[0:4] == 5'b10010); + assign ex0_fdiv = (rv_axu0_ex0_instr[0:5] == 6'b111111) & (rv_axu0_ex0_instr[26:30] == 5'b10010); + assign ex0_fdivs = (rv_axu0_ex0_instr[0:5] == 6'b111011) & (rv_axu0_ex0_instr[26:30] == 5'b10010); + + assign ex1_fmadd = ex1_dporsp & (ex1_sec_aform[0:4] == 5'b11101); + assign ex1_fmr = ex1_dp & (ex1_sec_xform[0:9] == 10'b0001001000); + assign ex1_fmsub = ex1_dporsp & (ex1_sec_aform[0:4] == 5'b11100); + assign ex1_fmul = ex1_dporsp & ((ex1_sec_aform[0:4] == 5'b11001) | (ex1_sec_aform[0:4] == 5'b10001)); //This is for the last divide op + assign ex1_fnabs = ex1_dp & (ex1_sec_xform[0:9] == 10'b0010001000); + assign ex1_fneg = ex1_dp & (ex1_sec_xform[0:9] == 10'b0000101000); + assign ex1_fnmadd = ex1_dporsp & (ex1_sec_aform[0:4] == 5'b11111); + assign ex1_fnmsub = ex1_dporsp & (ex1_sec_aform[0:4] == 5'b11110); + assign ex1_fres = ex1_dporsp & (ex1_sec_aform[0:4] == 5'b11000); + assign ex1_frim = ex1_dp & (ex1_sec_xform[0:9] == 10'b0111101000); + assign ex1_frin = ex1_dp & (ex1_sec_xform[0:9] == 10'b0110001000); + assign ex1_frip = ex1_dp & (ex1_sec_xform[0:9] == 10'b0111001000); + assign ex1_friz = ex1_dp & (ex1_sec_xform[0:9] == 10'b0110101000); + assign ex1_frsp = ex1_dp & (ex1_sec_xform[0:9] == 10'b0000001100); + assign ex1_frsqrte = ex1_dporsp & (ex1_sec_aform[0:4] == 5'b11010); + assign ex1_fsel = (ex1_dp & (ex1_sec_aform[0:4] == 5'b10111)) | (~perr_sm_l2[0]); // perr_insert + + assign ex1_fsqrt = ex1_dp & (ex1_sec_aform[0:4] == 5'b10110); + assign ex1_fsqrts = ex1_sp & (ex1_sec_aform[0:4] == 5'b10110); + assign ex0_fsqrt = (rv_axu0_ex0_instr[0:5] == 6'b111111) & (rv_axu0_ex0_instr[26:30] == 5'b10110); + assign ex0_fsqrts = (rv_axu0_ex0_instr[0:5] == 6'b111011) & (rv_axu0_ex0_instr[26:30] == 5'b10110); + + assign ex1_fsub = ex1_dporsp & (ex1_sec_aform[0:4] == 5'b10100); + assign ex1_mcrfs = ex1_dp & (ex1_sec_xform[0:9] == 10'b0001000000); + assign ex1_mffs = ex1_dp & (ex1_sec_xform[0:9] == 10'b1001000111); + assign ex1_mtfsb0 = ex1_dp & (ex1_sec_xform[0:9] == 10'b0001000110); + assign ex1_mtfsb1 = ex1_dp & (ex1_sec_xform[0:9] == 10'b0000100110); + assign ex1_mtfsf = ex1_dp & (ex1_sec_xform[0:9] == 10'b1011000111); + assign ex1_mtfsfi = ex1_dp & (ex1_sec_xform[0:9] == 10'b0010000110); + assign ex1_loge = ex1_dporsp & (ex1_sec_xform[0:9] == 10'b0011100101); + assign ex1_expte = ex1_dporsp & (ex1_sec_xform[0:9] == 10'b0011000101); + assign ex1_prenorm = ex1_dporsp & (ex1_sec_xform[5:9] == 5'b10000); + + assign ex1_ftdiv = ex1_dp & (ex1_sec_xform[0:9] == 10'b0010000000); + assign ex1_ftsqrt = ex1_dp & (ex1_sec_xform[0:9] == 10'b0010100000); + + assign ex1_cr_val = ex1_fcmpu | ex1_fcmpo; + assign ex1_record = (ex1_dporsp & ex1_instr[31]) & (~ex1_cr_val) & (~ex1_mcrfs) & (~ex1_ftdiv) & (~ex1_ftsqrt); + + assign ex1_moves = ex1_fmr | ex1_fabs | ex1_fnabs | ex1_fneg | ex1_fcpsgn; // | ((~perr_sm_l2[0])); //perr state machine, don't update the fpscr, only move. + + assign ex1_to_ints = ex1_fctid | ex1_fctidu | ex1_fctidz | ex1_fctiduz | ex1_fctiw | ex1_fctiwu | ex1_fctiwz | ex1_fctiwuz; + assign ex1_from_ints = ex1_fcfid | ex1_fcfidu | ex1_fcfids | ex1_fcfidus | ex1_fcfiwu | ex1_fcfiwus; + assign ex1_fpscr_moves = ex1_mtfsb0 | ex1_mtfsb1 | ex1_mtfsf | ex1_mtfsfi | ex1_mcrfs; + + assign ex1_kill_wen = ex1_cr_val | ex1_fpscr_moves | ex1_ftdiv | ex1_ftsqrt | ex1_ucode_preissue; + + assign ex1_fdivsqrt_start[0] = (ex1_fdiv | ex1_fdivs | ex1_fsqrt | ex1_fsqrts) & ex1_instr_v[0] & (~xu_ex1_flush[0]); + assign ex1_fdivsqrt_start[1] = (ex1_fdiv | ex1_fdivs | ex1_fsqrt | ex1_fsqrts) & ex1_instr_v[1] & (~xu_ex1_flush[1]); + + assign ex1_fdivsqrt_start_din = ex1_fdivsqrt_start & {2{(~ex1_ucode_preissue)}}; + + // ex1_instr_imm defs + assign ex1_mtfsb_bt[0] = (~ex1_instr[9]) & (~ex1_instr[10]); //00 + assign ex1_mtfsb_bt[1] = (~ex1_instr[9]) & ex1_instr[10]; //01 + assign ex1_mtfsb_bt[2] = ex1_instr[9] & (~ex1_instr[10]); //10 + assign ex1_mtfsb_bt[3] = ex1_instr[9] & ex1_instr[10]; //11 + + assign ex1_mtfs_bf[0] = (~ex1_instr[6]) & (~ex1_instr[7]) & (~ex1_instr[8]); //000 + assign ex1_mtfs_bf[1] = (~ex1_instr[6]) & (~ex1_instr[7]) & ex1_instr[8]; //001 + assign ex1_mtfs_bf[2] = (~ex1_instr[6]) & ex1_instr[7] & (~ex1_instr[8]); //010 + assign ex1_mtfs_bf[3] = (~ex1_instr[6]) & ex1_instr[7] & ex1_instr[8]; //011 + assign ex1_mtfs_bf[4] = ex1_instr[6] & (~ex1_instr[7]) & (~ex1_instr[8]); //100 + assign ex1_mtfs_bf[5] = ex1_instr[6] & (~ex1_instr[7]) & ex1_instr[8]; //101 + assign ex1_mtfs_bf[6] = ex1_instr[6] & ex1_instr[7] & (~ex1_instr[8]); //110 + assign ex1_mtfs_bf[7] = ex1_instr[6] & ex1_instr[7] & ex1_instr[8]; //111 + + assign ex1_mcrfs_bfa[0] = (~ex1_instr[11]) & (~ex1_instr[12]) & (~ex1_instr[13]); //000 + assign ex1_mcrfs_bfa[1] = (~ex1_instr[11]) & (~ex1_instr[12]) & ex1_instr[13]; //001 + assign ex1_mcrfs_bfa[2] = (~ex1_instr[11]) & ex1_instr[12] & (~ex1_instr[13]); //010 + assign ex1_mcrfs_bfa[3] = (~ex1_instr[11]) & ex1_instr[12] & ex1_instr[13]; //011 + assign ex1_mcrfs_bfa[4] = ex1_instr[11] & (~ex1_instr[12]) & (~ex1_instr[13]); //100 + assign ex1_mcrfs_bfa[5] = ex1_instr[11] & (~ex1_instr[12]) & ex1_instr[13]; //101 + assign ex1_mcrfs_bfa[6] = ex1_instr[11] & ex1_instr[12] & (~ex1_instr[13]); //110 + assign ex1_mcrfs_bfa[7] = ex1_instr[11] & ex1_instr[12] & ex1_instr[13]; //111 + + assign ex1_mtfsf_l = ex1_instr[6]; + assign ex1_mtfsf_w = ex1_instr[15]; + + // Instr bitdata bitmask nibmask + // mtfsb1 1111 dcd(instr[9:10]) dcd(instr[6:8]) + // mtfsb0 0000 dcd(instr[9:10]) dcd(instr[6:8]) + // mtfsfi nstr[16:19] 1111 dcd(instr[6:8]) + // mtfsf 0000 1111 instr[7:14] + // mcrfs 0000 1111 dcd(instr[11:13]) + + assign ex1_fpscr_bit_data[0:3] = (ex1_instr[16:19] | {4{ex1_mtfsb1}}) & {4{~(ex1_mtfsb0 | ex1_mtfsf | ex1_mcrfs)}}; + + assign ex1_fpscr_bit_mask[0:3] = ex1_mtfsb_bt[0:3] | {4{ex1_mtfsfi}} | {4{ex1_mtfsf}} | {4{ex1_mcrfs}}; + + assign ex1_fpscr_nib_mask[0:7] = (ex1_mtfs_bf[0:7] & {8{(ex1_mtfsb1 | ex1_mtfsb0)}}) | + (ex1_mtfs_bf[0:7] & {8{(ex1_mtfsfi & (~ex1_mtfsf_w))}}) | + (ex1_mtfsf_nib[0:7] & {8{ex1_mtfsf}}) | + (ex1_mcrfs_bfa[0:7] & {8{ex1_mcrfs}}); + + // nib mask[8] is "0" except : + // if (mtfsfi and W=0) : nib_mask[0:7] <= dcd(BF); nib_mask[8] <= 0 + // if (mtfsfi and W=1) : nib_mask[0:7] <= 0000_0000; nib_mask[8] <= dcd(BF)=="111" + // if (mtfsff and L=1) : nib_mask[0:7] <= 1111_1111; nib_mask[8] <= 1 + // if (mtfsff and L=0 and W=0) : nib_mask[0:7] <= FLM[0:7]; nib_mask[8] <= 0 + // if (mtfsff and L=0 and W=1) : nib_mask[0:7] <= 0000_0000; nib_mask[8] <= FLM[7] + + assign ex1_mtfsf_nib[0:7] = (ex1_instr[7:14] | {8{ex1_mtfsf_l}}) & + (~({8{((~ex1_mtfsf_l) & ex1_mtfsf_w)}})); + + assign ex1_fpscr_nib_mask[8] = (ex1_mtfsfi & ex1_mtfsf_w & ex1_mtfs_bf[7]) | (ex1_mtfsf & ex1_mtfsf_l) | (ex1_mtfsf & (~ex1_mtfsf_l) & ex1_mtfsf_w & ex1_instr[14]); + + assign f_dcd_ex1_fpscr_bit_data_b[0:3] = (~ex1_fpscr_bit_data[0:3]); + assign f_dcd_ex1_fpscr_bit_mask_b[0:3] = (~ex1_fpscr_bit_mask[0:3]); + assign f_dcd_ex1_fpscr_nib_mask_b[0:8] = (~ex1_fpscr_nib_mask[0:8]); + + //------------------------------------------------------------------- + // Outputs to Mad + assign f_dcd_ex1_thread = ex1_instr_v[0:1]; // one hot + + assign f_dcd_ex1_aop_valid = ex1_instr_fra_v; + assign f_dcd_ex1_cop_valid = ex1_instr_frc_v | ((~perr_sm_l2[0]) & ex1_perr_sm_instr_v); //Reading out parity // perr_insert + + assign f_dcd_ex1_bop_valid = ex1_instr_frb_v | ((~perr_sm_l2[0]) & ex1_perr_sm_instr_v); //Reading out parity // perr_insert + + + assign f_dcd_ex1_sp = ex1_sp & (~(ex1_fcfids | ex1_fcfiwus | ex1_fcfidus)); + assign f_dcd_ex1_emin_dp = tilo; + assign f_dcd_ex1_emin_sp = ex1_frsp; + assign f_dcd_ex1_force_pass_b = (~(ex1_fmr | ex1_fabs | ex1_fnabs | ex1_fneg | ex1_mtfsf | ex1_fcpsgn)); + assign f_dcd_ex1_fsel_b = (~ex1_fsel); + assign f_dcd_ex1_from_integer_b = (~ex1_from_ints); + assign f_dcd_ex1_to_integer_b = (~(ex1_to_ints | ex1_frim | ex1_frin | ex1_frip | ex1_friz)); + assign f_dcd_ex1_rnd_to_int_b = (~(ex1_frim | ex1_frin | ex1_frip | ex1_friz)); + assign f_dcd_ex1_math_b = (~(ex1_fmul | ex1_fmadd | ex1_fmsub | ex1_fadd | ex1_fsub | ex1_fnmsub | ex1_fnmadd)); + assign f_dcd_ex1_est_recip_b = (~ex1_fres); + assign f_dcd_ex1_est_rsqrt_b = (~ex1_frsqrte); + assign f_dcd_ex1_move_b = (~(ex1_moves)); + assign f_dcd_ex1_prenorm_b = (~(ex1_prenorm)); + assign f_dcd_ex1_frsp_b = (~ex1_frsp); + assign f_dcd_ex1_compare_b = (~ex1_cr_val); + assign f_dcd_ex1_ordered_b = (~ex1_fcmpo); + assign f_dcd_ex1_sp_conv_b = (~(ex1_fcfids | ex1_fcfidus | ex1_fcfiwus)); + assign f_dcd_ex1_uns_b = (~(ex1_fcfidu | ex1_fcfidus | ex1_fcfiwu | ex1_fcfiwus | ex1_fctidu | ex1_fctiduz | ex1_fctiwu | ex1_fctiwuz)); + assign f_dcd_ex1_word_b = (~(ex1_fctiw | ex1_fctiwu | ex1_fctiwz | ex1_fctiwuz | ex1_fcfiwu | ex1_fcfiwus)); + assign f_dcd_ex1_sub_op_b = (~(ex1_fsub | ex1_fmsub | ex1_fnmsub | ex1_cr_val)); + assign f_dcd_ex1_inv_sign_b = (~(ex1_fnmadd | ex1_fnmsub)); + assign f_dcd_ex1_sign_ctl_b[0] = (~(ex1_fmr | ex1_fnabs)); + assign f_dcd_ex1_sign_ctl_b[1] = (~(ex1_fneg | ex1_fnabs)); + assign f_dcd_ex1_sgncpy_b = (~ex1_fcpsgn); + assign f_dcd_ex1_mv_to_scr_b = (~(ex1_mcrfs | ex1_mtfsf | ex1_mtfsfi | ex1_mtfsb0 | ex1_mtfsb1)); + assign f_dcd_ex1_mv_from_scr_b = (~ex1_mffs); + assign f_dcd_ex1_mtfsbx_b = (~(ex1_mtfsb0 | ex1_mtfsb1)); + assign f_dcd_ex1_mcrfs_b = (~ex1_mcrfs); + assign f_dcd_ex1_mtfsf_b = (~ex1_mtfsf); + assign f_dcd_ex1_mtfsfi_b = (~ex1_mtfsfi); + + assign ex0_instr_vld = |(ex0_instr_valid[0:3]); + assign f_dcd_ex0_div = ex0_fdiv & ex0_instr_vld & (~ex0_ucode_preissue); + assign f_dcd_ex0_divs = ex0_fdivs & ex0_instr_vld & (~ex0_ucode_preissue); + assign f_dcd_ex0_sqrt = ex0_fsqrt & ex0_instr_vld & (~ex0_ucode_preissue); + assign f_dcd_ex0_sqrts = ex0_fsqrts & ex0_instr_vld & (~ex0_ucode_preissue); + assign f_dcd_ex0_record_v = rv_axu0_ex0_instr[31]; + + assign f_dcd_ex2_divsqrt_v = |(ex2_fdivsqrt_start); + + assign f_dcd_ex1_itag = ex1_itag; + + assign f_dcd_flush[0:1] = cp_flush_q | + xu_ex3_flush[0:1] | + (ex3_fdivsqrt_start & {2{f_ex3_b_den_flush}}) | + (ex3_fdivsqrt_start & {2{(ex3_abort_a | ex3_abort_b)}}); // kill fdiv/fsqrt on an abort + + assign f_dcd_ex1_mad_act = ex1_v | ex2_axu_v | ex1_perr_sm_instr_v; + assign f_dcd_ex1_sto_act = ex1_str_v; + + + // Force rounding mode. + // 00 - round to nearest + // 01 - round toward zero + // 10 - round toward +Inf + // 11 - round toward -Inf + assign ex1_rnd0 = (ex1_frim | ex1_frip); + + assign ex1_rnd1 = (ex1_fctidz | ex1_fctiwz | ex1_fctiduz | ex1_fctiwuz | ex1_friz | ex1_frim); + + assign f_dcd_ex1_op_rnd_v_b = (~(ex1_fctidz | ex1_fctiwz | ex1_fctiduz | ex1_fctiwuz | ex1_frim | ex1_frin | ex1_frip | ex1_friz)); + assign f_dcd_ex1_op_rnd_b[0:1] = (~({ex1_rnd0, ex1_rnd1})); + + assign f_dcd_ex1_thread_b[0:3] = (~ex1_instr_v[0:3]); + + //---------------------------------------------------------------------- + // Store Decode + assign pri_ex1[0:5] = ex1_instr[0:5]; + assign sec_ex1[20:31] = ex1_instr[20:31]; + + assign st_ex1 = ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[20] & (~sec_ex1[21]) & (~sec_ex1[22]) & (~sec_ex1[23]) & sec_ex1[24] & (~sec_ex1[26]) & (~sec_ex1[27]) & (~sec_ex1[28]) & sec_ex1[29] & sec_ex1[30]) | ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[21] & (~sec_ex1[22]) & sec_ex1[23] & sec_ex1[24] & sec_ex1[25] & sec_ex1[26] & sec_ex1[27] & sec_ex1[28] & sec_ex1[29]) | ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[21] & (~sec_ex1[22]) & sec_ex1[23] & sec_ex1[24] & (~sec_ex1[25]) & sec_ex1[26] & sec_ex1[27] & sec_ex1[28] & sec_ex1[30]) | ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[21] & sec_ex1[23] & sec_ex1[24] & (~sec_ex1[25]) & sec_ex1[26] & (~sec_ex1[27]) & sec_ex1[28] & sec_ex1[29] & sec_ex1[30]) | ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[21] & (~sec_ex1[22]) & sec_ex1[23] & sec_ex1[26] & (~sec_ex1[27]) & sec_ex1[28] & sec_ex1[29] & sec_ex1[30]) | (pri_ex1[0] & pri_ex1[1] & (~pri_ex1[2]) & pri_ex1[3]); + assign single_precision_ldst = ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[21] & (~sec_ex1[22]) & sec_ex1[28] & sec_ex1[29] & (~sec_ex1[30])) | ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[21] & (~sec_ex1[22]) & (~sec_ex1[24])) | (pri_ex1[0] & (~pri_ex1[2]) & (~pri_ex1[4])); + + assign int_word_ldst = ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[20] & (~sec_ex1[22]) & (~sec_ex1[23]) & (~sec_ex1[26]) & (~sec_ex1[27]) & (~sec_ex1[28]) & sec_ex1[29] & sec_ex1[30]) | ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[22] & sec_ex1[24] & sec_ex1[26] & (~sec_ex1[27]) & sec_ex1[28] & sec_ex1[29] & sec_ex1[30]) | ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[21] & (~sec_ex1[22]) & (~sec_ex1[23]) & sec_ex1[28] & (~sec_ex1[29])) | ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[21] & (~sec_ex1[25]) & (~sec_ex1[29])); + + // store_tag[0:1] + // 00 store DP + // 10 store SP + // 11 store SP Word + assign f_dcd_ex1_sto_dp = (~single_precision_ldst); + assign f_dcd_ex1_sto_sp = single_precision_ldst & (~int_word_ldst); + assign f_dcd_ex1_sto_wd = single_precision_ldst & int_word_ldst; + + assign sign_ext_ldst = ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[21] & + (~sec_ex1[22]) & (~sec_ex1[23]) & sec_ex1[28] & (~sec_ex1[29]) & (~sec_ex1[30])) | + ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[22] & + (~sec_ex1[23]) & sec_ex1[24] & (~sec_ex1[25])); + assign f_dcd_ex1_log2e_b = (~ex1_loge); + assign f_dcd_ex1_pow2e_b = (~ex1_expte); + + assign f_dcd_ex1_ftdiv = ex1_ftdiv; + assign f_dcd_ex1_ftsqrt = ex1_ftsqrt; + + //---------------------------------------------------------------------- + // ex2 + + assign ex2_cr_val_din = ex1_cr_val | ex1_ftdiv | ex1_ftsqrt; + + // Latches + + + + tri_rlmreg_p #(.INIT(0), .WIDTH(21)) ex2_ctl( + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[2]), + .mpw1_b(mpw1_b[2]), + .mpw2_b(mpw2_b[0]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(ex2_ctl_si[0:20]), + .scout(ex2_ctl_so[0:20]), + //------------------------------------------- + .din({ ex1_instr_valid[0:3], + ex2_cr_val_din, + ex1_record, + ex1_kill_wen, + ex1_mcrfs, + ex1_instr_match, + ex1_is_ucode, + ex1_fdivsqrt_start_din, + ex1_fra_v, + ex1_frb_v, + ex1_frc_v, + ex1_str_v, + ex2_frs_byp_din, + ex1_abort_a_din, + ex1_abort_b_din, + ex1_abort_c_din, + ex1_abort_s_din}), + //------------------------------------------- + .dout({ ex2_instr_v[0:3], + ex2_cr_val, + ex2_record, + ex2_kill_wen, + ex2_mcrfs, + ex2_instr_match, + ex2_is_ucode, + ex2_fdivsqrt_start, + ex2_fra_v, + ex2_frb_v, + ex2_frc_v, + ex2_str_v, + ex2_frs_byp, + ex2_abort_a_q, + ex2_abort_b_q, + ex2_abort_c_q, + ex2_abort_s_q}) + ); + //------------------------------------------- + + + tri_rlmreg_p #(.INIT(0), .WIDTH(6)) ex2_frt( + .nclk(nclk), + .act(ex1_v), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[2]), + .mpw1_b(mpw1_b[2]), + .mpw2_b(mpw2_b[0]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(ex2_frt_si[0:5]), + .scout(ex2_frt_so[0:5]), + //------------------------------------------- + .din(ex1_instr_frt[0:5]), + //------------------------------------------- + .dout(ex2_instr_frt[0:5]) + ); + //------------------------------------------- + + + + + assign ex1_ucode_preissue_din = ex1_ucode_preissue & |(ex1_instr_valid); + + + tri_rlmreg_p #(.INIT(0), .WIDTH(16)) ex2_itagl( + .nclk(nclk), + .act(tihi), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[2]), + .mpw1_b(mpw1_b[2]), + .mpw2_b(mpw2_b[0]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(ex2_itag_si), + .scout(ex2_itag_so), + //------------------------------------------- + .din({ ex1_itag[0:6], + ex1_fpscr_addr[0:5], + ex1_fpscr_wen, + ex1_ucode_preissue_din, + ex1_isRam}), + //------------------------------------------- + .dout({ ex2_itag[0:6], + ex2_fpscr_addr[0:5], + ex2_fpscr_wen, + ex2_ucode_preissue, + ex2_isRam}) + ); + //------------------------------------------- + + tri_rlmreg_p #(.INIT(0), .WIDTH(5)) ex2_crbf( + .nclk(nclk), + .act(tihi), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[2]), + .mpw1_b(mpw1_b[2]), + .mpw2_b(mpw2_b[0]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(ex2_crbf_si[0:4]), + .scout(ex2_crbf_so[0:4]), + .din(ex1_cr_bf[0:4]), + .dout(ex2_cr_bf[0:4]) + ); + + // Flushes + assign ex2_instr_valid[0:3] = ex2_instr_v[0:3] & (~xu_ex2_flush[0:3]); + assign ex2_v = ex2_instr_v[0] | ex2_instr_v[1]; + assign ex2_axu_v = ex2_v | ex2_fdivsqrt_start[0] | ex2_fdivsqrt_start[1]; + + assign ex2_instr_vld = (ex2_instr_v[0] & (~xu_ex2_flush[0])) | (ex2_instr_v[1] & (~xu_ex2_flush[1])) ; + + // Loads/Stores + + + assign ex2_str_valid = ex2_str_v & |(ex2_instr_valid[0:3]); + assign ex2_fra_valid = ex2_fra_v & ( |(ex2_instr_valid[0:3]) | |(ex2_fdivsqrt_start)); + assign ex2_frb_valid = ex2_frb_v & ( |(ex2_instr_valid[0:3]) | |(ex2_fdivsqrt_start)); + assign ex2_frc_valid = ex2_frc_v & |(ex2_instr_valid[0:3]); + + // Completion to XU + assign ex2_ifar_val[0:3] = ex2_instr_valid[0:3]; + + generate + if (THREADS == 1) + begin : dcd_store_data_val_thr1_1 + assign fu_lq_ex2_store_data_val[0] = ex2_str_valid & ex2_instr_valid[0] & (~ex2_ucode_preissue) & (~ex2_abort_s); + end + endgenerate + + generate + if (THREADS == 2) + begin : dcd_store_data_val_thr2_1 + assign fu_lq_ex2_store_data_val[0] = ex2_str_valid & ex2_instr_valid[0] & (~ex2_ucode_preissue) & (~ex2_abort_s); + assign fu_lq_ex2_store_data_val[1] = ex2_str_valid & ex2_instr_valid[1] & (~ex2_ucode_preissue) & (~ex2_abort_s); + end + endgenerate + + assign fu_lq_ex2_store_itag = ex2_itag; + + assign ex2_fdivsqrt_start_din = ex2_fdivsqrt_start & (~xu_ex2_flush[0:1]); + + assign ex2_abort_a = ex2_abort_a_q; + assign ex2_abort_b = ex2_abort_b_q; + assign ex2_abort_c = ex2_abort_c_q; + assign ex2_abort_s = ex2_abort_s_q; + + assign ex2_abort_a_din = ex2_abort_a & (ex2_instr_vld | |(ex2_fdivsqrt_start_din)); + assign ex2_abort_b_din = ex2_abort_b & (ex2_instr_vld | |(ex2_fdivsqrt_start_din)); + assign ex2_abort_c_din = ex2_abort_c & ex2_instr_vld; + assign ex2_abort_s_din = ex2_abort_s & ex2_instr_vld; + + assign axu0_rv_ex2_s1_abort = ex2_abort_a; // these do not need to be gated with cp_flush + assign axu0_rv_ex2_s2_abort = ex2_abort_b; + assign axu0_rv_ex2_s3_abort = ex2_abort_c | ex2_abort_s; + + //---------------------------------------------------------------------- + // ex3 + + // Latches + + tri_rlmreg_p #(.INIT(0), .WIDTH(7)) ex3_ctlng_lat( + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[3]), + .mpw1_b(mpw1_b[3]), + .mpw2_b(mpw2_b[0]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(ex3_ctlng_si[0:6]), + .scout(ex3_ctlng_so[0:6]), + //------------------------------------------- + .din({ ex2_instr_valid[0:3], + ex2_instr_match, + ex2_fdivsqrt_start_din[0:1]}), + //------------------------------------------- + .dout({ ex3_instr_v[0:3], + ex3_instr_match, + ex3_fdivsqrt_start[0:1] }) + ); + + //------------------------------------------- + tri_rlmreg_p #(.INIT(0), .WIDTH(24)) ex3_ctl_lat( + .nclk(nclk), + .act(ex2_axu_v), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[3]), + .mpw1_b(mpw1_b[3]), + .mpw2_b(mpw2_b[0]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(ex3_ctl_si[0:23]), + .scout(ex3_ctl_so[0:23]), + //------------------------------------------- + .din({ + ex2_instr_frt[0:5], + ex2_cr_val, + ex2_record, + ex2_str_valid, + ex2_kill_wen, + ex2_mcrfs, + ex2_is_ucode, + ex2_ifar_val[0:3], + ex2_fra_valid, + ex2_frb_valid, + ex2_frc_valid, + ex2_frs_byp, + ex2_abort_a_din, + ex2_abort_b_din, + ex2_abort_c_din, + ex2_abort_s_din}), + //------------------------------------------- + .dout({ + ex3_instr_frt[0:5], + ex3_cr_val, + ex3_record, + ex3_str_v, + ex3_kill_wen, + ex3_mcrfs, + ex3_is_ucode, + ex3_ifar_val[0:3], + ex3_fra_v, + ex3_frb_v, + ex3_frc_v, + ex3_frs_byp, + ex3_abort_a, + ex3_abort_b, + ex3_abort_c, + ex3_abort_s }) + ); + + //------------------------------------------- + + + tri_rlmreg_p #(.INIT(0), .WIDTH(1)) ex3_stdv_lat( + .nclk(nclk), + .act(tihi), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[3]), + .mpw1_b(mpw1_b[3]), + .mpw2_b(mpw2_b[0]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(ex3_stdv_si), + .scout(ex3_stdv_so), + //------------------------------------------- + .din(ex2_str_valid), + .dout(ex3_store_v) + ); + + assign ex2_ucode_preissue_din = ex2_ucode_preissue & |(ex2_instr_valid); + + + tri_rlmreg_p #(.INIT(0), .WIDTH(16)) ex3_itagl( + .nclk(nclk), + .act(tihi), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[3]), + .mpw1_b(mpw1_b[3]), + .mpw2_b(mpw2_b[0]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(ex3_itag_si), + .scout(ex3_itag_so), + //------------------------------------------- + .din({ ex2_itag[0:6], + ex2_fpscr_addr[0:5], + ex2_fpscr_wen, + ex2_ucode_preissue_din, + ex2_isRam}), + //------------------------------------------- + .dout({ ex3_itag[0:6], + ex3_fpscr_addr[0:5], + ex3_fpscr_wen, + ex3_ucode_preissue, + ex3_isRam}) + ); + //------------------------------------------- + + + tri_rlmreg_p #(.INIT(0), .WIDTH(5)) ex3_crbf( + .nclk(nclk), + .act(tihi), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[3]), + .mpw1_b(mpw1_b[3]), + .mpw2_b(mpw2_b[0]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(ex3_crbf_si[0:4]), + .scout(ex3_crbf_so[0:4]), + .din(ex2_cr_bf[0:4]), + .dout(ex3_cr_bf[0:4]) + ); + + + + // Flushes + assign ex3_instr_valid[0:3] = ex3_instr_v[0:3] & (~xu_ex3_flush[0:3]); + assign f_dcd_ex2_divsqrt_hole_v = ((~|(ex2_instr_v[0:3]))) & ((~|(ex0_instr_v[0:3]))) & (perr_sm_l2[0]); // in case there is a denormal result, need both cycles free + + // The n flush for next cycle + // The N flush can come from either an FU instruction, or a load in the XU pipe + + assign ex3_n_flush[0:3] = ((ex3_instr_valid[0:3] | {4{|({4{ex3_fdivsqrt_start}})}}) & {4{f_ex3_b_den_flush}} & (~({4{ex3_ucode_preissue}}))); + + // flush2ucode + assign ex3_flush2ucode[0:3] = (ex3_instr_v[0:3] | {4{|({4{ex3_fdivsqrt_start}})}}) & {4{f_ex3_b_den_flush}} & (~xu_ex3_flush[0:3]); + + assign ex3_store_valid = ex3_store_v; + + assign ex3_fdivsqrt_start_din = ex3_fdivsqrt_start & (~xu_ex3_flush[0:1]); + + assign ex3_instr_vld = |((ex3_instr_v[0:1] & (~xu_ex3_flush[0:1])) | (ex3_fdivsqrt_start & (~xu_ex3_flush[0:1]))); + assign ex3_abort_din = (ex3_abort_a | ex3_abort_b | ex3_abort_c | ex3_abort_s) & ex3_instr_vld; + + assign fu_lq_ex3_abort = ex3_abort_s; + + //---------------------------------------------------------------------- + // ex4 + + // Latches + + tri_rlmreg_p #(.INIT(0), .WIDTH(30)) ex4_ctl( + .nclk(nclk), + .act(tihi), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[4]), + .mpw1_b(mpw1_b[4]), + .mpw2_b(mpw2_b[0]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(ex4_ctl_si[0:29]), + .scout(ex4_ctl_so[0:29]), + //------------------------------------------- + .din({ ex3_instr_valid[0:3], + ex3_instr_frt[0:5], + ex3_cr_val, + ex3_record, + f_ex3_b_den_flush, + ex3_kill_wen, + ex3_mcrfs, + ex3_instr_match, + ex3_is_ucode, + ex3_n_flush[0:3], + ex3_flush2ucode[0:3], + ex3_store_valid, + ex3_fdivsqrt_start_din, + ex3_instr_vns_taken, + ex3_abort_din}), + //------------------------------------------- + .dout( { ex4_instr_v[0:3], + ex4_instr_frt[0:5], + ex4_cr_val, + ex4_record, + ex4_b_den_flush, + ex4_kill_wen, + ex4_mcrfs, + ex4_instr_match, + ex4_is_ucode, + ex4_n_flush[0:3], + ex4_flush2ucode[0:3], + ex4_store_valid, + ex4_fdivsqrt_start, + ex4_instr_vns_taken, + ex4_abort}) + ); + //------------------------------------------- + + assign ex3_ucode_preissue_din = ex3_ucode_preissue & |(ex3_instr_valid); + + + tri_rlmreg_p #(.INIT(0), .WIDTH(16)) ex4_itagl( + .nclk(nclk), + .act(tihi), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[4]), + .mpw1_b(mpw1_b[4]), + .mpw2_b(mpw2_b[0]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(ex4_itag_si), + .scout(ex4_itag_so), + //------------------------------------------- + .din({ ex3_itag[0:6], + ex3_fpscr_addr[0:5], + ex3_fpscr_wen, + ex3_ucode_preissue_din, + ex3_isRam}), + //------------------------------------------- + .dout({ ex4_itag[0:6], + ex4_fpscr_addr[0:5], + ex4_fpscr_wen, + ex4_ucode_preissue, + ex4_isRam}) + ); + //------------------------------------------- + + + tri_rlmreg_p #(.INIT(0), .WIDTH(5)) ex4_crbf( + .nclk(nclk), + .act(tihi), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[4]), + .mpw1_b(mpw1_b[4]), + .mpw2_b(mpw2_b[0]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(ex4_crbf_si[0:4]), + .scout(ex4_crbf_so[0:4]), + .din(ex3_cr_bf[0:4]), + .dout(ex4_cr_bf[0:4]) + ); + + // Flushes + assign ex4_instr_valid[0:3] = ex4_instr_v[0:3] & (~xu_ex4_flush[0:3]) & (~({4{ex4_store_valid}})); + + assign ex4_fdivsqrt_start_din = ex4_fdivsqrt_start & (~xu_ex4_flush[0:1]); + + + // Outputs + assign ex4_instr_vld = |((ex4_instr_v[0:1] & (~xu_ex4_flush[0:1])) | (ex4_fdivsqrt_start & (~xu_ex4_flush[0:1]))); + assign ex4_abort_din = ex4_abort & ex4_instr_vld; + + + //---------------------------------------------------------------------- + // ex5 + + // Latches + + tri_rlmreg_p #(.INIT(0), .WIDTH(22)) ex5_ctl_lat( + .nclk(nclk), + .act(tihi), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[5]), + .mpw1_b(mpw1_b[5]), + .mpw2_b(mpw2_b[1]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(ex5_ctl_si), + .scout(ex5_ctl_so), + //------------------------------------------- + .din({ ex4_instr_valid[0:3], + ex4_instr_frt[0:5], + ex4_cr_val, + ex4_cr_val, + ex4_record, + ex4_kill_wen, + ex4_mcrfs, + ex4_is_ucode, + ex4_fdivsqrt_start_din, + ex4_instr_vns_taken_din, + ex4_abort_din, + spare_unused[22:23] }), + + //------------------------------------------- + .dout({ ex5_instr_v[0:3], + ex5_instr_frt[0:5], + ex5_cr_val, + ex5_cr_val_cp, + ex5_record, + ex5_kill_wen, + ex5_mcrfs, + ex5_is_ucode, + ex5_fdivsqrt_start, + ex5_instr_vns_taken, + ex5_abort_l2, + spare_unused[22:23] }) + ); + //------------------------------------------- + assign ex4_ucode_preissue_din = ex4_ucode_preissue & |(ex4_instr_valid); + + + tri_rlmreg_p #(.INIT(0), .WIDTH(17)) ex5_itagl( + .nclk(nclk), + .act(tihi), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[5]), + .mpw1_b(mpw1_b[5]), + .mpw2_b(mpw2_b[1]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(ex5_itag_si), + .scout(ex5_itag_so), + //------------------------------------------- + .din({ ex4_itag[0:6], + ex5_b_den_flush_din, + ex4_fpscr_addr[0:5], + ex4_fpscr_wen, + ex4_ucode_preissue_din, + ex4_isRam}), + //------------------------------------------- + .dout({ ex5_itag[0:6], + ex5_b_den_flush, + ex5_fpscr_addr[0:5], + ex5_fpscr_wen, + ex5_ucode_preissue, + ex5_isRam}) + ); + //------------------------------------------- + + + tri_rlmreg_p #(.INIT(0), .WIDTH(5)) ex5_crbf( + .nclk(nclk), + .act(tihi), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[5]), + .mpw1_b(mpw1_b[5]), + .mpw2_b(mpw2_b[1]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(ex5_crbf_si[0:4]), + .scout(ex5_crbf_so[0:4]), + .din(ex4_cr_bf[0:4]), + .dout(ex5_cr_bf[0:4]) + ); + + // Pipe the CR + assign ex5_cr[0:3] = f_add_ex5_fpcc_iu[0:3]; + + // Flushes + assign ex5_instr_valid[0:3] = (ex5_instr_v[0:3]) & (~xu_ex5_flush[0:3]); + + // This creates ex5_cr_val, make sure it wasn't flushed + assign ex5_record_din = ex5_record & |(ex5_instr_valid[0:3]); + assign ex5_mcrfs_din = ex5_mcrfs & |(ex5_instr_valid[0:3]); + assign ex5_cr_val_din = ex5_cr_val & |(ex5_instr_valid[0:3]); + + assign ex5_instr_tid[0] = ex5_instr_v[2] | ex5_instr_v[3]; + assign ex5_instr_tid[1] = ex5_instr_v[1] | ex5_instr_v[3]; + + // ex6_kill_wen_din <= ex5_kill_wen or ex5_uc_special;--Preserve s1 on special fdiv/fsqrt + assign ex5_kill_wen_din = ex5_kill_wen; //Preserve s1 on special fdiv/fsqrt + + + assign ex5_instr_valid_din[0] = ex5_instr_valid[0]; + assign ex5_instr_valid_din[1] = ex5_instr_valid[1]; + assign ex5_instr_valid_din[2] = ex5_instr_valid[2]; + assign ex5_instr_valid_din[3] = ex5_instr_valid[3]; + + assign ex5_instr_frt_din[0:5] = (ex5_instr_frt[0:5] & (~{6{perr_sm_l2[2]}})) | (perr_addr_l2[0:5] & {6{perr_sm_l2[2]}}); // perr_insert + + + assign ex5_fdivsqrt_start_din = ex5_fdivsqrt_start & (~xu_ex5_flush[0:1]); + + assign ex5_instr_vld = |((ex5_instr_v[0:1] & (~xu_ex5_flush[0:1])) | (ex5_fdivsqrt_start & (~xu_ex5_flush[0:1]))); + assign ex5_abort_din = ex5_abort_l2 & ex5_instr_vld; + assign ex5_abort_lq_din = lq_fu_ex5_abort ; + + //---------------------------------------------------------------------- + // ex6 + + // Latches + + tri_rlmreg_p #(.INIT(0), .WIDTH(21)) ex6_ctl( + .nclk(nclk), + .act(tihi), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[6]), + .mpw1_b(mpw1_b[6]), + .mpw2_b(mpw2_b[1]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(ex6_ctl_si[0:20]), + .scout(ex6_ctl_so[0:20]), + //------------------------------------------- + .din({ ex5_instr_valid_din[0:3], + ex5_instr_frt_din[0:5], + ex5_record_din, + ex5_mcrfs_din, + ex5_is_ucode, + ex5_cr_val_din, + ex5_kill_wen_din, + ex5_fdivsqrt_start_din, + ex5_abort_din, + ex5_abort_lq_din, + spare_unused[24:25]}), + //------------------------------------------- + .dout({ ex6_instr_v[0:3], + ex6_instr_frt[0:5], + ex6_record, + ex6_mcrfs, + ex6_is_ucode, + ex6_cr_val, + ex6_kill_wen_q, + ex6_fdivsqrt_start, + ex6_abort, + ex6_abort_lq, + spare_unused[24:25]}) + ); + //------------------------------------------- + + assign ex5_ucode_preissue_din = ex5_ucode_preissue & |(ex5_instr_valid); + + + tri_rlmreg_p #(.INIT(0), .WIDTH(17)) ex6_itagl( + .nclk(nclk), + .act(tihi), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[6]), + .mpw1_b(mpw1_b[6]), + .mpw2_b(mpw2_b[1]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(ex6_itag_si), + .scout(ex6_itag_so), + //------------------------------------------- + .din({ ex5_itag_din[0:6], + ex5_b_den_flush, + ex5_fpscr_addr[0:5], + ex5_fpscr_wen, + ex5_ucode_preissue_din, + ex5_isRam}), + //------------------------------------------- + .dout({ ex6_itag[0:6], + ex6_b_den_flush, + ex6_fpscr_addr[0:5], + ex6_fpscr_wen, + ex6_ucode_preissue, + ex6_isRam}) + ); + //------------------------------------------- + + + tri_rlmreg_p #(.INIT(0), .WIDTH(9)) ex6_crbf( + .nclk(nclk), + .act(tihi), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[6]), + .mpw1_b(mpw1_b[6]), + .mpw2_b(mpw2_b[1]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(ex6_crbf_si[0:8]), + .scout(ex6_crbf_so[0:8]), + .din({ ex5_cr_bf[0:4], + ex5_cr[0:3]}), + .dout({ ex6_cr_bf[0:4], + ex6_cr[0:3]}) + ); + + assign ex6_instr_tid[0] = ((ex6_instr_v[0] | (f_dsq_ex6_divsqrt_instr_tid[0] & ex6_divsqrt_v)) & (~xu_ex6_flush[0])); + assign ex6_instr_tid[1] = ((ex6_instr_v[1] | (f_dsq_ex6_divsqrt_instr_tid[1] & ex6_divsqrt_v)) & (~xu_ex6_flush[1])); + + assign ex6_iflush_b[0] = (~(xu_ex6_flush[0] & ex6_instr_v[0])); //big + assign ex6_iflush_b[1] = (~(xu_ex6_flush[1] & ex6_instr_v[1])); //big + assign ex6_iflush_b[2] = (~(xu_ex6_flush[2] & ex6_instr_v[2])); //big + assign ex6_iflush_b[3] = (~(xu_ex6_flush[3] & ex6_instr_v[3])); //big + + assign ex6_iflush_01 = (~(ex6_iflush_b[0] & ex6_iflush_b[1])); + assign ex6_iflush_23 = (~(ex6_iflush_b[2] & ex6_iflush_b[3])); + + assign ex6_instr_flush_b = (~(ex6_iflush_01 | ex6_iflush_23)); + + assign ex6_instr_flush = (~ex6_instr_flush_b); //small + + assign ex6_divsqrt_v = |(f_dsq_ex6_divsqrt_v); + assign ex6_divsqrt_v_suppress = f_dsq_ex6_divsqrt_v_suppress; + + // perr_insert + assign ex6_instr_valid[0] = ((ex6_instr_v[0] | (f_dsq_ex6_divsqrt_instr_tid[0] & ex6_divsqrt_v)) & (~xu_ex6_flush[0])) | (perr_sm_l2[2] & ex6_perr_sm_instr_v & perr_tid_l2[0:1] == 2'b10); + assign ex6_instr_valid[1] = ((ex6_instr_v[1] | (f_dsq_ex6_divsqrt_instr_tid[1] & ex6_divsqrt_v)) & (~xu_ex6_flush[1])) | (perr_sm_l2[2] & ex6_perr_sm_instr_v & perr_tid_l2[0:1] == 2'b01); + assign ex6_instr_valid[2] = ((ex6_instr_v[2] | (f_dsq_ex6_divsqrt_instr_tid[2] & ex6_divsqrt_v)) & (~xu_ex6_flush[2])) ; + assign ex6_instr_valid[3] = ((ex6_instr_v[3] | (f_dsq_ex6_divsqrt_instr_tid[3] & ex6_divsqrt_v)) & (~xu_ex6_flush[3])) ; + + assign ex6_instr_valid_din[0] = ex6_instr_valid[0]; + assign ex6_instr_valid_din[1] = ex6_instr_valid[1]; + assign ex6_instr_valid_din[2] = ex6_instr_valid[2]; + assign ex6_instr_valid_din[3] = ex6_instr_valid[3]; + + + assign ex6_kill_wen = (ex6_kill_wen_q & (~(ex6_divsqrt_v & (~ex6_divsqrt_v_suppress)))) | (ex6_divsqrt_v & ex6_divsqrt_v_suppress); + + assign ex6_kill_wen_din = (ex6_kill_wen | (((~f_pic_ex6_fpr_wr_dis_b)) & (~ex6_divsqrt_v))) & (~(perr_sm_l2[2] & ex6_perr_sm_instr_v)); // parity merge + assign ex6_fpr_wr_dis = ((((~f_pic_ex6_fpr_wr_dis_b)) & (~ex6_divsqrt_v)) & (~ex6_kill_wen)) | (ex6_divsqrt_v & ex6_divsqrt_v_suppress); + + //Make a copy without the flush for bypass + assign ex6_instr_bypval[0] = ex6_instr_v[0] & f_pic_ex6_fpr_wr_dis_b & (~ex6_kill_wen); + assign ex6_instr_bypval[1] = ex6_instr_v[1] & f_pic_ex6_fpr_wr_dis_b & (~ex6_kill_wen); + assign ex6_instr_bypval[2] = ex6_instr_v[2] & f_pic_ex6_fpr_wr_dis_b & (~ex6_kill_wen); + assign ex6_instr_bypval[3] = ex6_instr_v[3] & f_pic_ex6_fpr_wr_dis_b & (~ex6_kill_wen); + + assign f_dcd_ex6_frt_tid[0:1] = ex6_instr_tid[0:1]; + + // Don't update CR during certain exceptions + assign ex7_record_din = (ex6_record | (ex6_divsqrt_v & f_dsq_ex6_divsqrt_record_v)) & (~ex6_instr_flush); + assign ex7_mcrfs_din = ex6_mcrfs & (~ex6_instr_flush); + assign ex7_cr_val_din = ex6_cr_val & (~ex6_instr_flush); + + assign ex6_cr_bf_din = (ex6_cr_bf & {5{(~ex6_divsqrt_v)}}) | (f_dsq_ex6_divsqrt_cr_bf & {5{ex6_divsqrt_v}}); + // Outputs + assign ex6_fpscr_move = (~(f_pic_ex6_scr_upd_move_b)); + + assign ex6_fdivsqrt_start_din = ex6_fdivsqrt_start & (~xu_ex6_flush[0:1]); + + assign ex6_instr_vld = |((ex6_instr_v[0:1] & (~xu_ex6_flush[0:1])) | (ex6_fdivsqrt_start & (~xu_ex6_flush[0:1]))); + assign ex6_abort_din = ex6_abort & ex6_instr_vld; + + //---------------------------------------------------------------------- + // ex7 + + // Latches + + tri_rlmreg_p #(.INIT(0), .WIDTH(23)) ex7_ctl( + .nclk(nclk), + .act(tihi), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[7]), + .mpw1_b(mpw1_b[7]), + .mpw2_b(mpw2_b[1]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(ex7_ctl_si[0:22]), + .scout(ex7_ctl_so[0:22]), + //------------------------------------------- + .din({ ex6_instr_valid_din[0:3], + ex7_instr_frt_din[0:5], + ex7_record_din, + ex7_mcrfs_din, + ex6_is_ucode, + ex7_cr_val_din, + ex6_kill_wen_din, + ex6_fpr_wr_dis, + ex6_fdivsqrt_start_din, + ex6_abort_din, + ex6_abort_lq, + spare_unused[26:27], + spare_unused[30]}), + //------------------------------------------- + .dout({ ex7_instr_v[0:3], + ex7_instr_frt[0:5], + ex7_record, + ex7_mcrfs, + ex7_is_ucode, + ex7_cr_val, + ex7_kill_wen, + ex7_fpr_wr_dis, + ex7_fdivsqrt_start, + ex7_abort, + ex7_abort_lq, + spare_unused[26:27], + spare_unused[30] }) + ); + //------------------------------------------- + + assign ex7_fdivsqrt_start_din = ex7_fdivsqrt_start & (~xu_ex7_flush[0:1]); + + assign ex6_ucode_preissue_din = ex6_ucode_preissue & |(ex6_instr_valid); + + + tri_rlmreg_p #(.INIT(0), .WIDTH(18)) ex7_itagl( + .nclk(nclk), + .act(tihi), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[7]), + .mpw1_b(mpw1_b[7]), + .mpw2_b(mpw2_b[1]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(ex7_itag_si), + .scout(ex7_itag_so), + //------------------------------------------- + .din({ ex6_itag[0:6], + ex6_b_den_flush, + ex6_fpscr_addr_din[0:5], + ex6_fpscr_wen_din, + ex6_fpscr_move, + ex6_ucode_preissue_din, + ex6_isRam}), + //------------------------------------------- + .dout({ ex7_itag[0:6], + ex7_b_den_flush, + ex7_fpscr_addr[0:5], + ex7_fpscr_wen, + ex7_fpscr_move, + ex7_ucode_preissue, + ex7_isRam}) + ); + //------------------------------------------- + + + tri_rlmreg_p #(.INIT(0), .WIDTH(18)) ex7_la( + .nclk(nclk), + .act(tihi), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[7]), + .mpw1_b(mpw1_b[7]), + .mpw2_b(mpw2_b[1]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(ex7_laddr_si), + .scout(ex7_laddr_so), + //------------------------------------------- + .din({ ex6_load_addr[0:7], + ex6_reload_addr[0:7], + ex6_load_v, + ex6_reload_v }), + //------------------------------------------- + .dout({ ex7_load_addr[0:7], + ex7_reload_addr[0:7], + ex7_load_v, + ex7_reload_v}) + ); + //------------------------------------------- + + + tri_rlmreg_p #(.INIT(0), .WIDTH(9)) ex7_crbf( + .nclk(nclk), + .act(tihi), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[7]), + .mpw1_b(mpw1_b[7]), + .mpw2_b(mpw2_b[1]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(ex7_crbf_si[0:8]), + .scout(ex7_crbf_so[0:8]), + .din({ ex6_cr_bf_din[0:4], + ex6_cr[0:3]}), + .dout({ ex7_cr_bf[0:4], + ex7_cr[0:3]}) + ); + + assign ex7_instr_tid[0] = ex7_instr_v[2] | ex7_instr_v[3]; + assign ex7_instr_tid[1] = ex7_instr_v[1] | ex7_instr_v[3]; + + // Flushes - flushes in ex7 + + // perr_insert + assign ex7_instr_valid = |(ex7_instr_v[0:1] & (~cp_flush_q[0:1])) | (perr_sm_l2[2] & ex7_perr_sm_instr_v); + + assign ex7_instr_v_din[0] = (ex7_instr_v[0] & (~cp_flush_q[0])) | (perr_sm_l2[2] & ex7_perr_sm_instr_v & perr_tid_l2[0]); + assign ex7_instr_v_din[1] = (ex7_instr_v[1] & (~cp_flush_q[1])) | (perr_sm_l2[2] & ex7_perr_sm_instr_v & perr_tid_l2[1]); + + // Outputs ex7 + assign f_dcd_ex7_frt_addr[0:5] = ex7_instr_frt[0:5]; + assign f_dcd_ex7_frt_tid[0:1] = ex7_instr_tid[0:1]; + assign f_dcd_ex7_frt_wen = ex7_instr_valid & (~ex7_kill_wen) & (~ex7_ucode_preissue) & (~ex7_fu_unavail) & (~ex7_abort) & (~ex7_perr_cancel); + + assign f_dcd_ex7_fpscr_wr = ex7_fpscr_wen & ex7_instr_valid & (~ex7_ucode_preissue) & (~ex7_fu_unavail) & (~ex7_abort); + assign f_dcd_ex7_fpscr_addr[0:5] = ex7_fpscr_addr[0:5]; + + assign ex7_perr_cancel = |(ex7_regfile_err_det[0:1] & ex7_instr_v[0:1]); + + assign f_dcd_ex7_cancel = ((~ex7_instr_valid)) | ex7_ucode_preissue | ex7_fu_unavail | ex7_b_den_flush | ex7_perr_cancel; + + // Records + assign ex7_record_v = ex7_instr_valid & (ex7_record | ex7_mcrfs); + + assign ex8_b_den_flush_din = ex7_b_den_flush & (ex7_instr_valid | |(ex7_fdivsqrt_start)); + + assign ex8_fpr_wr_dis_din = ex7_fpr_wr_dis & ex7_instr_valid & (~ex7_fu_unavail); + + assign ex8_fpscr_move_din = ex7_fpscr_move & ex7_instr_valid; + + //---------------------------------------------------------------------- + // ex8 FPSCR, Record Forms + + assign ex7_ucode_preissue_din = ex7_ucode_preissue & ex7_instr_valid; + assign ex7_instr_vld = |((ex7_instr_v[0:1] & (~xu_ex7_flush[0:1])) | (ex7_fdivsqrt_start & (~xu_ex7_flush[0:1]))); + assign ex7_abort_din = ex7_abort & ex7_instr_vld; + + + // Latches + + tri_rlmreg_p #(.INIT(0), .WIDTH(32)) ex8_ctl( + .nclk(nclk), + .act(tihi), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[8]), + .mpw1_b(mpw1_b[8]), + .mpw2_b(mpw2_b[1]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(ex8_ctl_si[0:31]), + .scout(ex8_ctl_so[0:31]), + //------------------------------------------- + .din({ ex7_record_v, + ex7_cr_bf[0:4], + ex7_instr_valid, + ex7_instr_frt[0:5], + ex7_cr[0:3], + ex7_cr_val, + ex7_instr_tid[0:1], + ex8_fpr_wr_dis_din, + ex7_kill_wen, + ex8_fpscr_move_din, + ex7_ucode_preissue_din, + ex7_fdivsqrt_start_din, + ex7_instr_v_din[0:1], + ex7_abort_din, + ex7_abort_lq, + spare_unused[28:29] + }), + + //------------------------------------------- + .dout({ ex8_record_v, + ex8_cr_bf[0:4], + ex8_instr_v, + ex8_instr_frt[0:5], + ex8_cr[0:3], + ex8_cr_val, + ex8_instr_tid[0:1], + ex8_fpr_wr_dis, + ex8_kill_wen, + ex8_fpscr_move, + ex8_ucode_preissue, + ex8_fdivsqrt_start, + ex8_instr_valid, + ex8_abort, + ex8_abort_lq, + spare_unused[28:29] + }) + ); + //------------------------------------------- + + + tri_rlmreg_p #(.INIT(0), .WIDTH(8)) ex8_itagl( + .nclk(nclk), + .act(tihi), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[8]), + .mpw1_b(mpw1_b[8]), + .mpw2_b(mpw2_b[1]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(ex8_itag_si), + .scout(ex8_itag_so), + //------------------------------------------- + .din({ ex7_itag[0:6], + ex8_b_den_flush_din}), + //------------------------------------------- + .dout({ ex8_itag[0:6], + ex8_b_den_flush}) + ); + //------------------------------------------- + + tri_rlmreg_p #(.INIT(0), .WIDTH(18)) ex8_la( + .nclk(nclk), + .act(tihi), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[8]), + .mpw1_b(mpw1_b[8]), + .mpw2_b(mpw2_b[1]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(ex8_laddr_si), + .scout(ex8_laddr_so), + //------------------------------------------- + .din({ ex7_load_addr[0:7], + ex7_reload_addr[0:7], + ex7_load_v, + ex7_reload_v}), + //------------------------------------------- + .dout({ ex8_load_addr[0:7], + ex8_reload_addr[0:7], + ex8_load_v, + ex8_reload_v}) + ); + //------------------------------------------- + + //---------------------------------------------------------------------- + // ex9 + + // Latches + assign ex8_instr_vld = |((ex8_instr_valid[0:1] & (~xu_ex8_flush[0:1])) | (ex8_fdivsqrt_start & (~xu_ex8_flush[0:1]))); + assign ex8_abort_din = ex8_abort & ex8_instr_vld; + + assign ex8_fdivsqrt_start_din = ex8_fdivsqrt_start & (~xu_ex8_flush[0:1]); + + + tri_rlmreg_p #(.INIT(0), .WIDTH(14)) ex9_ctl( + .nclk(nclk), + .act(tihi), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[9]), + .mpw1_b(mpw1_b[9]), + .mpw2_b(mpw2_b[1]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(ex9_ctl_si[0:13]), + .scout(ex9_ctl_so[0:13]), + //------------------------------------------- + .din({ ex8_instr_v, + ex8_instr_frt[0:5], + ex8_instr_tid[0:1], + ex8_kill_wen, + ex8_abort_din, + ex8_abort_lq, + ex8_fdivsqrt_start_din}), + //------------------------------------------- + .dout({ ex9_instr_v, + ex9_instr_frt[0:5], + ex9_instr_tid[0:1], + ex9_kill_wen, + ex9_abort_q, + ex9_abort_lq, + ex9_fdivsqrt_start}) + ); + //------------------------------------------- + //------------------------------------------- + + tri_rlmreg_p #(.INIT(0), .WIDTH(9)) ex9_la( + .nclk(nclk), + .act(tihi), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[9]), + .mpw1_b(mpw1_b[9]), + .mpw2_b(mpw2_b[1]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(ex9_laddr_si), + .scout(ex9_laddr_so), + //------------------------------------------- + .din({ ex8_load_addr[0:7], + ex8_load_v + }), + //------------------------------------------- + .dout({ ex9_load_addr[0:7], + ex9_load_v + }) + ); + //------------------------------------------- + assign ex9_instr_valid[0:1] = {(ex9_instr_v & (~ex9_instr_tid[1])),(ex9_instr_v & (ex9_instr_tid[1]))}; + + assign ex9_instr_vld = |((ex9_instr_valid[0:1] & (~xu_ex9_flush[0:1])) | (ex9_fdivsqrt_start & (~xu_ex9_flush[0:1]))); + assign ex9_abort = ex9_abort_q & ex9_instr_vld; + + //---------------------------------------------------------------------- + // COMPLETION + + // Send update to completion at ealiest bypass point + + // CR + assign axu0_cr_w4e = ex8_cr_val | ex8_record_v; + + generate + if (THREADS == 1) + begin : dcd_cr_w4a_thr1_1 + assign axu0_cr_w4a[0:4] = ex8_cr_bf[0:4]; + end + endgenerate + + generate + if (THREADS == 2) + begin : dcd_cr_w4a_thr2_1 + assign axu0_cr_w4a[0:5] = {ex8_cr_bf[0:4], ex8_instr_tid[1]}; + end + endgenerate + + assign axu0_cr_w4d[0:3] = (f_scr_ex8_cr_fld[0:3] & {4{ex8_record_v}}) | (ex8_cr[0:3] & ({4{~ex8_record_v}})); + + assign ex5_divsqrt_itag[0:6] = f_dsq_ex5_divsqrt_itag; + assign ex6_divsqrt_fpscr_addr[0:5] = f_dsq_ex6_divsqrt_fpscr_addr; + + assign ex3_instr_vns_taken = (ex3_instr_vns[0] & (~|(ex4_instr_vns)) & (~|(ex5_cr_or_divsqrt_v))) | (ex3_instr_vns[1] & (~|(ex4_instr_vns)) & (~|(ex5_cr_or_divsqrt_v))); + + assign ex4_instr_vns_taken_din = ex4_instr_vns_taken | ((ex4_instr_vns[0] & (~|(ex5_cr_or_divsqrt_v))) | (ex4_instr_vns[1] & (~|(ex5_cr_or_divsqrt_v)))); + + assign ex3_instr_vns = ex3_instr_v & (~{4{ex3_store_valid}}) & {4{~(ex3_cr_val | ex3_record | ex3_mcrfs)}}; + assign ex4_instr_vns = ex4_instr_v & (~{4{ex4_store_valid}}) & {4{~(ex4_cr_val | ex4_record | ex4_mcrfs)}} & (~{4{ex4_instr_vns_taken}}); + assign ex5_instr_vns = ex5_instr_v & {4{(~ex5_cr_val | ex5_record | ex5_mcrfs)}} & (~{4{ex5_instr_vns_taken}}); // ex5_instr_v was gated off by ex4_store_valid the prev cycle + + assign ex5_cr_or_divsqrt_v[0] = f_dsq_ex5_divsqrt_v[0] | (ex5_instr_v[0] & (ex5_cr_val | ex5_record | ex5_mcrfs)) | ex5_instr_vns[0]; + assign ex5_cr_or_divsqrt_v[1] = f_dsq_ex5_divsqrt_v[1] | (ex5_instr_v[1] & (ex5_cr_val | ex5_record | ex5_mcrfs)) | ex5_instr_vns[1]; + assign ex5_any_cr_v = (|(ex5_instr_v) & (~ex5_divsqrt_v)) & (ex5_cr_val | ex5_record | ex5_mcrfs); + + generate + if (THREADS == 1) + begin : dcd_axu0_itag_vld_thr1_1 + + assign axu0_rv_itag_vld[0] = (ex3_instr_vns[0] & (~ex4_instr_vns[0]) & (~ex5_cr_or_divsqrt_v[0])) | + (ex4_instr_vns[0] & (~ex5_cr_or_divsqrt_v[0])) | + (ex5_cr_or_divsqrt_v[0]); + end + endgenerate + + generate + if (THREADS == 2) + begin : dcd_axu0_itag_vld_thr2_1 + + assign axu0_rv_itag_vld[0] = (ex3_instr_vns[0] & (~(|(ex4_instr_vns))) & (~(|(ex5_cr_or_divsqrt_v)))) | + (ex4_instr_vns[0] & (~(|(ex5_cr_or_divsqrt_v)))) | + (ex5_cr_or_divsqrt_v[0]); + + assign axu0_rv_itag_vld[1] = (ex3_instr_vns[1] & (~(|(ex4_instr_vns))) & (~(|(ex5_cr_or_divsqrt_v)))) | + (ex4_instr_vns[1] & (~(|(ex5_cr_or_divsqrt_v)))) | + (ex5_cr_or_divsqrt_v[1]); + end + endgenerate + + assign axu0_rv_itag = (ex3_itag[0:6] & {7{ ((~(ex5_divsqrt_v | ex5_any_cr_v | |(ex5_instr_vns))) & (~|(ex4_instr_vns)) & |(ex3_instr_vns)) }} ) | + (ex4_itag[0:6] & {7{ ((~(ex5_divsqrt_v | ex5_any_cr_v | |(ex5_instr_vns))) & |(ex4_instr_vns))}} ) | + (ex5_itag[0:6] & {7{ ((ex5_any_cr_v | |(ex5_instr_vns)) & (~ex5_divsqrt_v))}} ) | + (ex5_divsqrt_itag[0:6] & {7{ (ex5_divsqrt_v)}}); + + assign axu0_rv_itag_abort = (ex3_abort_din & ((~(ex5_divsqrt_v | ex5_any_cr_v | |(ex5_instr_vns))) & (~|(ex4_instr_vns)) & |(ex3_instr_vns)) ) | + (ex4_abort & ((~(ex5_divsqrt_v | ex5_any_cr_v | |(ex5_instr_vns))) & |(ex4_instr_vns)) ) | + (ex5_abort_l2 & ((ex5_any_cr_v | |(ex5_instr_vns)) & (~ex5_divsqrt_v)) ) ; + + assign ex5_divsqrt_v = |(f_dsq_ex5_divsqrt_v); + assign axu0_rv_ord_complete = ex5_divsqrt_v; + + assign ex5_itag_din = (ex5_itag[0:6] & {7{ (~ex5_divsqrt_v)}}) | + (ex5_divsqrt_itag[0:6] & {7{ ex5_divsqrt_v}}); + + assign ex6_fpscr_wen_din = ex6_fpscr_wen | ex6_divsqrt_v; + assign ex6_fpscr_addr_din = (ex6_fpscr_addr & {6{(~ex6_divsqrt_v)}}) | + (ex6_divsqrt_fpscr_addr & {6{ex6_divsqrt_v}}); + + assign ex7_instr_frt_din = (ex6_instr_frt & {6{(~ex6_divsqrt_v)}}) | + (f_dsq_ex6_divsqrt_instr_frt & {6{ ex6_divsqrt_v}}); + + generate + if (THREADS == 1) + begin : dcd_itag_vld_thr1_1 + assign axu1_rv_itag_vld[0] = tidn; + end + endgenerate + + generate + if (THREADS == 2) + begin : dcd_itag_vld_thr2_1 + assign axu1_rv_itag_vld = 2'b00; + end + endgenerate + + assign axu1_rv_itag = 7'b0000000; + assign axu1_rv_itag_abort = 1'b0; + + assign ex5_fu_unavail = |((ex5_instr_v[0:1] | ex5_fdivsqrt_start_din[0:1]) & (~msr_fp[0:1])); + assign ex6_fu_unavail = |((ex6_instr_v[0:1] | ex6_fdivsqrt_start_din[0:1]) & (~msr_fp[0:1])); + assign ex7_fu_unavail = |((ex7_instr_v[0:1] | ex7_fdivsqrt_start_din[0:1]) & (~msr_fp[0:1])); + assign ex8_fu_unavail = (ex8_instr_valid[0:1] | ex8_fdivsqrt_start_din[0:1]) & (~msr_fp[0:1]); + + // AXU0 Instruction Executed + generate + if (THREADS == 2) + begin : dcd_exe0_vld_thr2_1 + assign axu0_iu_execute_vld[0] = (ex8_instr_valid[0] | (ex8_fdivsqrt_start[0] & (ex8_b_den_flush | ex8_regfile_err_det[0]))) & (~ex8_abort) & (~ex8_perr_sm_instr_v); + assign axu0_iu_execute_vld[1] = (ex8_instr_valid[1] | (ex8_fdivsqrt_start[1] & (ex8_b_den_flush | ex8_regfile_err_det[1]))) & (~ex8_abort) & (~ex8_perr_sm_instr_v); + end + endgenerate + generate + if (THREADS == 1) + begin : dcd_exe0_vld_thr1_1 + assign axu0_iu_execute_vld[0] = (ex8_instr_valid[0] | (ex8_fdivsqrt_start[0] & (ex8_b_den_flush | ex8_regfile_err_det[0]))) & (~ex8_abort) & (~ex8_perr_sm_instr_v); + end + endgenerate + + assign ex8_ucode_preissue_din = ex8_ucode_preissue & |(ex8_instr_valid); + + assign axu0_iu_itag = ex8_itag[0:6]; + assign axu0_iu_n_flush = (|(ex8_fu_unavail) | ex8_b_den_flush | |(ex8_regfile_err_det) ) & (~ex8_ucode_preissue); + assign axu0_iu_np1_flush = (ex8_fpr_wr_dis | |(ex8_fp_enabled) | ex8_fpscr_move) & (~ex8_ucode_preissue); + assign axu0_iu_n_np1_flush = |(ex8_fp_enabled) & (~ex8_ucode_preissue); + assign axu0_iu_flush2ucode = ex8_b_den_flush & (~ex8_ucode_preissue) & (~|(ex8_fu_unavail)); + assign axu0_iu_flush2ucode_type = 1'b0; + + // Exception vector encodes + //| 1 0000 AP Unavailable + //| 1 0001 FP Unavailable + //| 1 0010 Vector Unavailable + //| 1 0011 Progam AP Enabled + //| 1 0100 Progam FP Enabled + //| 1 0101 Progam FP Enabled, gate FPR write + + assign fp_except_fx[0] = f_scr_ex8_fx_thread0[0]; + assign fp_except_fx[1] = f_scr_ex8_fx_thread1[0]; + assign fp_except_fex[0] = f_scr_ex8_fx_thread0[1]; + assign fp_except_fex[1] = f_scr_ex8_fx_thread1[1]; + assign fp_except_fex_async[0] = f_scr_cpl_fx_thread0[1]; + assign fp_except_fex_async[1] = f_scr_cpl_fx_thread1[1]; + + // Denorm flushes take priority over fp_enabled exceptions + assign ex8_fp_enabled = ex8_instr_valid & fp_except_en_q & fp_except_fex & (~ex8_fu_unavail) & (~{2{(ex8_b_den_flush)}}); + + // async fex (AP Enabled) exception occurs when the fex bit was set previously, but exceptions weren't enabled + // until a later time. This exception is imprecise. + //rising edge sets + assign fp_async_fex_d = (fp_except_fex_async & fp_except_en_d & (~fp_except_en_q)) | (fp_async_fex_q & (~(fp_except_en_q & (~fp_except_en_d)))); //falling edge clears + + assign axu0_iu_exception_val = (|(ex8_fu_unavail) | |(ex8_fp_enabled)) & (~ex8_ucode_preissue); + assign axu0_iu_exception[0:3] = {1'b0, + (|(ex8_fp_enabled) | ex8_fpr_wr_dis), + 1'b0, + (|(ex8_fu_unavail) | ex8_fpr_wr_dis)}; + + generate + if (THREADS == 1) + begin : dcd_async_fex_thr1_1 + assign axu0_iu_async_fex[0] = fp_async_fex_q[0]; + assign spare_unused[12] = fp_async_fex_q[1]; + assign msr_pr_d[0] = xu_fu_msr_pr[0]; + assign msr_pr_d[1] = tidn; + assign msr_gs_d[0] = xu_fu_msr_gs[0]; + assign msr_gs_d[1] = tidn; + + end + endgenerate + + generate + if (THREADS == 2) + begin : dcd_async_fex_thr2_1 + assign axu0_iu_async_fex[0] = fp_async_fex_q[0]; + assign axu0_iu_async_fex[1] = fp_async_fex_q[1]; + assign spare_unused[12] = tidn; + assign msr_pr_d[0] = xu_fu_msr_pr[0]; + assign msr_pr_d[1] = xu_fu_msr_pr[1]; + assign msr_gs_d[0] = xu_fu_msr_gs[0]; + assign msr_gs_d[1] = xu_fu_msr_gs[1]; + + end + endgenerate + + assign fp_except_en_d = msr_fe0 | msr_fe1; + + + tri_rlmreg_p #(.INIT(0), .WIDTH(4)) axu_ex( + .nclk(nclk), + .act(tihi), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[9]), + .mpw1_b(mpw1_b[9]), + .mpw2_b(mpw2_b[1]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(axu_ex_si[0:3]), + .scout(axu_ex_so[0:3]), + //------------------------------------------- + .din({fp_except_en_d, + fp_async_fex_d }), + //------------------------------------------- + .dout({ fp_except_en_q, + fp_async_fex_q}) + ); + //------------------------------------------- + + // AXU1 Instruction Executed + generate + if (THREADS == 1) + begin : dcd_exe_vld_thr1_1 + assign axu1_iu_execute_vld = 1'b0; + end + endgenerate + + generate + if (THREADS == 2) + begin : dcd_exe_vld_thr2_1 + assign axu1_iu_execute_vld = 2'b00; + end + endgenerate + + assign axu1_iu_itag = 7'b0000000; + assign axu1_iu_n_flush = 1'b0; + assign axu1_iu_np1_flush = 1'b0; + assign axu1_iu_exception[0:3] = 4'b0000; + assign axu1_iu_flush2ucode = 1'b0; + assign axu1_iu_flush2ucode_type = 1'b0; + assign axu1_iu_exception_val = 1'b0; + + //---------------------------------------------------------------------- + // Parity State Machine / parity section + + tri_parity_recovery #(.THREADS(`THREADS)) fu_parity_recovery( + .perr_si(perr_si), + .perr_so(perr_so), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .nclk(nclk), + .force_t(force_t), + .thold_0_b(thold_0_b), + .sg_0(sg_0), + .gnd(gnd), + .vdd(vdd), + + .ex3_hangcounter_trigger(f_dsq_ex3_hangcounter_trigger), + + .ex3_a_parity_check(f_mad_ex3_a_parity_check), + .ex3_b_parity_check(f_mad_ex3_b_parity_check), + .ex3_c_parity_check(f_mad_ex3_c_parity_check), + .ex3_s_parity_check(f_sto_ex3_s_parity_check), + + .rf0_instr_fra(rf0_instr_fra), + .rf0_instr_frb(rf0_instr_frb), + .rf0_instr_frc(rf0_instr_frc), + .rf0_tid(rf0_tid), + + .rf0_dcd_fra(f_dcd_rf0_fra), + .rf0_dcd_frb(f_dcd_rf0_frb), + .rf0_dcd_frc(f_dcd_rf0_frc), + .rf0_dcd_tid(f_dcd_rf0_tid), + + .ex1_instr_fra(ex1_instr_fra), + .ex1_instr_frb(ex1_instr_frb), + .ex1_instr_frc(ex1_instr_frc), + .ex1_instr_frs(ex1_instr_frs), + + .ex3_fra_v(ex3_fra_v), + .ex3_frb_v(ex3_frb_v), + .ex3_frc_v(ex3_frc_v), + .ex3_str_v(ex3_str_v), + .ex3_frs_byp(ex3_frs_byp), + + .ex3_fdivsqrt_start(ex3_fdivsqrt_start), + .ex3_instr_v(ex3_instr_v[0:1]), + .msr_fp_act(msr_fp_act), + .cp_flush_1d(cp_flush_q), + + .ex7_is_fixperr(ex7_is_fixperr), + + .xx_ex4_regfile_err_det(ex4_regfile_err_det), + .xx_ex5_regfile_err_det(ex5_regfile_err_det), + .xx_ex6_regfile_err_det(ex6_regfile_err_det), + .xx_ex7_regfile_err_det(ex7_regfile_err_det), + .xx_ex8_regfile_err_det(ex8_regfile_err_det), + + .xx_ex1_perr_sm_instr_v(ex1_perr_sm_instr_v), + .xx_ex2_perr_sm_instr_v(ex2_perr_sm_instr_v), + .xx_ex3_perr_sm_instr_v(ex3_perr_sm_instr_v), + .xx_ex4_perr_sm_instr_v(ex4_perr_sm_instr_v), + .xx_ex5_perr_sm_instr_v(ex5_perr_sm_instr_v), + .xx_ex6_perr_sm_instr_v(ex6_perr_sm_instr_v), + .xx_ex7_perr_sm_instr_v(ex7_perr_sm_instr_v), + .xx_ex8_perr_sm_instr_v(ex8_perr_sm_instr_v), + + .xx_perr_sm_running(perr_sm_running), + + .xx_ex2_perr_force_c(f_dcd_ex2_perr_force_c), + .xx_ex2_perr_fsel_ovrd(f_dcd_ex2_perr_fsel_ovrd), + + .xx_perr_tid_l2(perr_tid_l2), + .xx_perr_sm_l2(perr_sm_l2), + .xx_perr_addr_l2(perr_addr_l2), + + .ex3_sto_parity_err(fu_lq_ex3_sto_parity_err), + .xx_rv_hold_all(f_dcd_rv_hold_all), + + .xx_ex0_regfile_ue(ex0_regfile_ue), + .xx_ex0_regfile_ce(ex0_regfile_ce), + + .xx_pc_err_regfile_parity(fu_pc_err_regfile_parity), + .xx_pc_err_regfile_ue(fu_pc_err_regfile_ue) + + + ); + + assign f_dcd_perr_sm_running = perr_sm_running; + + //---------------------------------------------------------------------- + // Microcode Hooks for Divide and Square Root + + //removed uc_hooks for a2o + + // Buffer outputs + + assign f_dcd_ex1_uc_ft_pos = 1'b0; + assign f_dcd_ex1_uc_ft_neg = 1'b0; + assign f_dcd_ex1_uc_fa_pos = 1'b0; + assign f_dcd_ex1_uc_fc_pos = 1'b0; + assign f_dcd_ex1_uc_fb_pos = 1'b0; + assign f_dcd_ex1_uc_fc_hulp = 1'b0; + assign f_dcd_ex1_uc_fc_0_5 = 1'b0; + assign f_dcd_ex1_uc_fc_1_0 = 1'b0; + assign f_dcd_ex1_uc_fc_1_minus = 1'b0; + assign f_dcd_ex1_uc_fb_1_0 = 1'b0; + assign f_dcd_ex1_uc_fb_0_75 = 1'b0; + assign f_dcd_ex1_uc_fb_0_5 = 1'b0; + assign f_dcd_ex1_uc_mid = 1'b0; + assign f_dcd_ex1_uc_end = 1'b0; + assign f_dcd_ex1_uc_special = 1'b0; + + assign f_dcd_ex3_uc_inc_lsb = 1'b0; + assign f_dcd_ex3_uc_gs_v = 1'b0; + assign f_dcd_ex3_uc_gs = 2'b00; + assign f_dcd_ex3_uc_vxsnan = 1'b0; + assign f_dcd_ex3_uc_zx = 1'b0; + assign f_dcd_ex3_uc_vxidi = 1'b0; + assign f_dcd_ex3_uc_vxzdz = 1'b0; + assign f_dcd_ex3_uc_vxsqrt = 1'b0; + + //---------------------------------------------------------------------- + // Slow SPR Bus + + // Latches + + tri_rlmreg_p #(.INIT(0), .WIDTH(15)) spr_ctl( + .nclk(nclk), + .act(tihi), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[9]), + .mpw1_b(mpw1_b[9]), + .mpw2_b(mpw2_b[1]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(spr_ctl_si[0:14]), + .scout(spr_ctl_so[0:14]), + //------------------------------------------- + .din({ slowspr_in_val, + slowspr_in_rw, + slowspr_in_etid[0:1], + slowspr_in_addr[0:9], + slowspr_in_done}), + //------------------------------------------- + .dout({ slowspr_out_val, + slowspr_out_rw, + slowspr_out_etid[0:1], + slowspr_out_addr[0:9], + slowspr_out_done}) + ); + //------------------------------------------- + + tri_rlmreg_p #(.INIT(0), .WIDTH(2 ** REGMODE)) spr_data( + .nclk(nclk), + .act(tihi), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[9]), + .mpw1_b(mpw1_b[9]), + .mpw2_b(mpw2_b[1]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(spr_data_si[64 - (2 ** REGMODE):63]), + .scout(spr_data_so[64 - (2 ** REGMODE):63]), + //------------------------------------------- + .din(slowspr_in_data), + //------------------------------------------- + .dout(slowspr_out_data) + ); + //------------------------------------------- + + + tri_rlmreg_p #(.INIT(0), .WIDTH(4)) axucr0_lat( + .nclk(nclk), + .act(tihi), + .force_t(cfg_sl_force), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[9]), + .mpw1_b(mpw1_b[9]), + .mpw2_b(mpw2_b[1]), + .thold_b(cfg_sl_thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(axucr0_lat_si[0:3]), + .scout(axucr0_lat_so[0:3]), + //------------------------------------------- + .din(axucr0_din[60:63]), + //------------------------------------------- + .dout( axucr0_q[60:63]) + ); + //------------------------------------------- + + + tri_ser_rlmreg_p #(.WIDTH(32), .INIT(0)) a0esr_lat( + .nclk(nclk), + .act(a0esr_wr), + .force_t(cfg_sl_force), + .delay_lclkr(delay_lclkr[9]), + .d_mode(tiup), + .mpw1_b(mpw1_b[9]), + .mpw2_b(mpw2_b[1]), + .thold_b(cfg_sl_thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(a0esr_lat_si[0:31]), + .scout(a0esr_lat_so[0:31]), + .din(a0esr_din), + .dout(a0esr_q) + ); + + assign f_dcd_ex1_force_excp_dis = axucr0_q[61]; + assign f_dcd_ex1_nj_deni = axucr0_q[62] ; + assign f_dcd_ex1_nj_deno = axucr0_q[63] ; + assign f_dcd_axucr0_deno = axucr0_q[63] ; + + assign a0esr_event_mux_ctrls = a0esr_q[32:63]; + + // slowSPR bus inputs + // slowspr_in_val <= slowspr_val_in and not ((cp_flush_q(0) and slowspr_etid_in(0)) or + // (cp_flush_q(1) and slowspr_etid_in(1))); + assign slowspr_in_val = slowspr_val_in & (~((cp_flush_q[0] & (~slowspr_etid_in[1])) | (cp_flush_q[1] & slowspr_etid_in[1]))); // etid is encoded tid, not one hot + assign slowspr_in_rw = slowspr_rw_in; + assign slowspr_in_etid = slowspr_etid_in; + assign slowspr_in_addr = slowspr_addr_in; + assign slowspr_in_data = slowspr_data_in; + assign slowspr_in_done = slowspr_done_in; + + // for RTX + assign slowspr_val_in_int = slowspr_val_in; + assign slowspr_data_in_int = slowspr_in_data; + + + // AXUCR0 is SPR 976 + assign axucr0_dec = slowspr_out_addr[0:9] == 10'b1111010000; + assign axucr0_rd = slowspr_out_val & axucr0_dec & slowspr_out_rw; + assign axucr0_wr = slowspr_out_val & axucr0_dec & (~slowspr_out_rw); + + assign axucr0_din[60:63] = (slowspr_out_data[60:63] & {4{axucr0_wr}}) | + (axucr0_q[60:63] & {4{(~axucr0_wr)}}); + + assign axucr0_out[32:63] = {slowspr_out_data[32:59], axucr0_q[60:63]}; + + // AOESR is SPR 913 + assign a0esr_dec = slowspr_out_addr[0:9] == 10'b1110010001; + assign a0esr_rd = slowspr_out_val & a0esr_dec & slowspr_out_rw; + assign a0esr_wr = slowspr_out_val & a0esr_dec & (~slowspr_out_rw); + + assign a0esr_din[32:63] = (slowspr_out_data[32:63] & {32{a0esr_wr}}) | + (a0esr_q[32:63] & {32{(~a0esr_wr)}}); + + // slowSPR bus outputs + generate + if (2 ** REGMODE > 32) + begin : r64 + assign slowspr_data_out_int[0:31] = slowspr_out_data[0:31]; + assign slowspr_data_out[0:31] = slowspr_data_out_int[0:31]; + + end + endgenerate + + assign slowspr_data_out_int[32:63] = (axucr0_rd == 1'b1) ? axucr0_out[32:63] : + (a0esr_rd == 1'b1) ? a0esr_q[32:63] : + slowspr_out_data[32:63]; + assign slowspr_data_out[32:63] = slowspr_data_out_int[32:63]; + + assign slowspr_val_out = slowspr_out_val; + assign slowspr_rw_out = slowspr_out_rw; + assign slowspr_etid_out = slowspr_out_etid; + assign slowspr_addr_out = slowspr_out_addr; + assign slowspr_done_out_int = slowspr_out_done | axucr0_rd | axucr0_wr | a0esr_rd | a0esr_wr; + assign slowspr_done_out = slowspr_done_out_int; + + //---------------------------------------------------------------------- + // RAM + + assign ex7_ram_sign = f_rnd_ex7_res_sign; + assign ex7_ram_frac[0:52] = f_rnd_ex7_res_frac[0:52]; + assign ex7_ram_expo[3:13] = f_rnd_ex7_res_expo[3:13]; + + generate + if (THREADS == 1) + begin : dcd_ramactive_thr1_1 + assign ex7_ram_active[0] = pc_fu_ram_active[0]; + assign ex7_ram_active[1] = tilo; + end + endgenerate + generate + if (THREADS == 2) + begin : dcd_ramactive_thr2_1 + assign ex7_ram_active[0] = pc_fu_ram_active[0]; + assign ex7_ram_active[1] = pc_fu_ram_active[1]; + end + endgenerate + + // Better be the only instr in the pipe for that thread. Bugspray event fail if not + //and not pc_fu_ram_thread -- (pc_fu_ram_thread(0 to 1) = ex7_instr_tid(0 to 1)) + assign ex7_ram_done = |(ex7_ram_active & (ex7_instr_v[0:1] & (~cp_flush_q[0:1]))) & (~ex7_is_ucode) & (~ex7_is_fixperr); // Only report the end of the ucode seq + + + tri_rlmreg_p #(.INIT(0), .WIDTH(65)) ex8_ram_lat( + .nclk(nclk), + .act(ex7_instr_valid), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[9]), + .mpw1_b(mpw1_b[9]), + .mpw2_b(mpw2_b[1]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(ram_data_si[0:64]), + .scout(ram_data_so[0:64]), + //------------------------------------------- + .din({ ex7_ram_sign, + ex7_ram_expo[3:13], + ex7_ram_frac[0:52]}), + //------------------------------------------- + .dout({ ex8_ram_sign, + ex8_ram_expo[3:13], + ex8_ram_frac[0:52]}) + ); + //------------------------------------------- + + + tri_rlmreg_p #(.INIT(0), .WIDTH(1)) ex8_ramv_lat( + .nclk(nclk), + .act(tihi), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[9]), + .mpw1_b(mpw1_b[9]), + .mpw2_b(mpw2_b[1]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(ram_datav_si[0]), + .scout(ram_datav_so[0]), + //------------------------------------------- + .din(ex7_ram_done), + //------------------------------------------- + .dout(ex8_ram_done) + ); + + assign ex8_ram_data[0] = ex8_ram_sign; + assign ex8_ram_data[1:11] = ex8_ram_expo[3:13] & {11{ex8_ram_frac[0]}}; + assign ex8_ram_data[12:63] = ex8_ram_frac[1:52]; + + assign fu_pc_ram_data_val = ex8_ram_done & ex8_instr_v; + assign fu_pc_ram_data[0:63] = ex8_ram_data[0:63]; + + //---------------------------------------------------------------------- + // Event Bus + + + // Perf events + assign evnt_axu_instr_cmt[0] = ex7_instr_valid & (ex7_instr_tid[0:1] == 2'b00) & (~ex7_is_ucode) & (~ex7_is_fixperr); + assign evnt_axu_instr_cmt[1] = ex7_instr_valid & (ex7_instr_tid[0:1] == 2'b01) & (~ex7_is_ucode) & (~ex7_is_fixperr); + + assign evnt_axu_cr_cmt[0] = ex7_instr_valid & (ex7_instr_tid[0:1] == 2'b00) & (ex7_cr_val | ex7_record | ex7_mcrfs); + assign evnt_axu_cr_cmt[1] = ex7_instr_valid & (ex7_instr_tid[0:1] == 2'b01) & (ex7_cr_val | ex7_record | ex7_mcrfs); + + assign evnt_axu_idle[0] = (ex7_instr_tid[0:1] == 2'b00) & (~(ex7_instr_valid | ex7_cr_val | ex7_record | ex7_mcrfs)); //includes ucode + assign evnt_axu_idle[1] = (ex7_instr_tid[0:1] == 2'b01) & (~(ex7_instr_valid | ex7_cr_val | ex7_record | ex7_mcrfs)); //includes ucode + + assign evnt_denrm_flush[0] = (ex5_instr_tid[0:1] == 2'b00) & ex5_b_den_flush; + assign evnt_denrm_flush[1] = (ex5_instr_tid[0:1] == 2'b01) & ex5_b_den_flush; + + assign evnt_uc_instr_cmt[0] = ex7_instr_valid & (ex7_instr_tid[0:1] == 2'b00) & ex7_is_ucode; + assign evnt_uc_instr_cmt[1] = ex7_instr_valid & (ex7_instr_tid[0:1] == 2'b01) & ex7_is_ucode; + + assign evnt_fpu_fx[0:1] = {f_scr_ex8_fx_thread0[0], f_scr_ex8_fx_thread1[0]}; + assign evnt_fpu_fex[0:1] = {f_scr_ex8_fx_thread0[1], f_scr_ex8_fx_thread1[1]}; + + assign evnt_fpu_cpl_fx[0:1] = {f_scr_cpl_fx_thread0[0], f_scr_cpl_fx_thread1[0]}; + assign evnt_fpu_cpl_fex[0:1] = {f_scr_cpl_fx_thread0[1], f_scr_cpl_fx_thread1[1]}; + + assign evnt_div_sqrt_ip[0] = (ex5_instr_tid[0:1] == 2'b00) & f_dsq_debug[10]; // todo: need to cover later cycles? this is only up to ex5 + assign evnt_div_sqrt_ip[1] = (ex5_instr_tid[0:1] == 2'b01) & f_dsq_debug[10]; + + assign event_en_d[0:1] = ( msr_pr_q & {2{event_count_mode_q[0]}}) | //-- User + ((~msr_pr_q) & msr_gs_q & {2{event_count_mode_q[1]}}) | //-- Guest Supervisor + ((~msr_pr_q) & (~msr_gs_q) & {2{event_count_mode_q[2]}}); //-- Hypervisor + assign event_en_d[2:3] = {2{tidn}}; + + + assign t0_events[0:14] = {evnt_axu_instr_cmt[0], evnt_axu_cr_cmt[0], evnt_axu_idle[0], evnt_div_sqrt_ip[0], evnt_denrm_flush[0], evnt_uc_instr_cmt[0], evnt_fpu_fx[0], evnt_fpu_fex[0], + evnt_fpu_cpl_fx[0], evnt_fpu_cpl_fex[0], tidn, tidn, tidn, tidn, tidn} & {15{event_en_q[0]}}; + + assign t1_events[0:14] = {evnt_axu_instr_cmt[1], evnt_axu_cr_cmt[1], evnt_axu_idle[1], evnt_div_sqrt_ip[1], evnt_denrm_flush[1], evnt_uc_instr_cmt[1], evnt_fpu_fx[1], evnt_fpu_fex[1], + evnt_fpu_cpl_fx[1], evnt_fpu_cpl_fex[1], tidn, tidn, tidn, tidn, tidn} & {15{event_en_q[1]}}; + + // perf event mux + assign unit_bus_in_t0 = t0_events[0:14] ; + assign unit_bus_in_t1 = t1_events[0:14] ; + + + tri_event_mux1t #(.EVENTS_IN(16), .EVENTS_OUT(4)) + event_mux_t0( + .vd(vdd), + .gd(gnd), + .unit_events_in(unit_bus_in_t0), + .select_bits(a0esr_event_mux_ctrls[0:15]), + .event_bus_in(event_bus_in[0:3]), + .event_bus_out(event_bus_d[0:3]) + ); + +`ifndef THREADS1 + + tri_event_mux1t #(.EVENTS_IN(16), .EVENTS_OUT(4)) + event_mux_t1( + .vd(vdd), + .gd(gnd), + .unit_events_in(unit_bus_in_t1), + .select_bits(a0esr_event_mux_ctrls[16:31]), + .event_bus_in(event_bus_in[4:7]), + .event_bus_out(event_bus_d[4:7]) + ); + + assign event_bus_out[0:7] = event_bus_q[0:7]; + + + `else + + assign event_bus_d[4:7] = {4{tidn}}; + assign event_bus_out[0:3] = event_bus_q[0:3]; + + `endif + + + + tri_rlmreg_p #(.INIT(0), .WIDTH(8)) event_bus_out_lat( + .nclk(nclk), + .act(event_act), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[9]), + .mpw1_b(mpw1_b[9]), + .mpw2_b(mpw2_b[1]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(event_bus_out_si), + .scout(event_bus_out_so), + //------------------------------------------- + .din({event_bus_d }), + //------------------------------------------- + .dout({event_bus_q }) + ); + + + + + tri_rlmreg_p #(.INIT(0), .WIDTH(35)) perf_data( + .nclk(nclk), + .act(event_act), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[9]), + .mpw1_b(mpw1_b[9]), + .mpw2_b(mpw2_b[1]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(perf_data_si), + .scout(perf_data_so), + //------------------------------------------- + .din({ spare_unused[13:20], + event_en_d[0:3], + spare_unused[4], + pc_fu_event_count_mode[0:2], + msr_pr_d[0:1], + msr_gs_d[0:1], + pc_fu_instr_trace_mode, + pc_fu_instr_trace_tid[0:1], + rf0_instr_tid_1hot[0:3], + rf1_instr_iss[0:3], + ex1_instr_iss[0:3] }), + //------------------------------------------- + .dout({spare_unused[13:20], + event_en_q[0:3], + spare_unused[4], + event_count_mode_q[0:2], + msr_pr_q[0:1], + msr_gs_q[0:1], + instr_trace_mode_q, // todo + instr_trace_tid_q[0:1], // todo + rf1_instr_iss[0:3], + ex1_instr_iss[0:3], + ex2_instr_iss[0:3] }) + ); + + + //---------------------------------------------------------------------- + // Debug Bus + + tri_rlmreg_p #(.INIT(0), .WIDTH(32)) dbg_group3_lat( + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[9]), + .mpw1_b(mpw1_b[9]), + .mpw2_b(mpw2_b[1]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(dbg_group3_lat_si), + .scout(dbg_group3_lat_so), + //------------------------------------------- + .din({ dbg_group3_din[00:31] }), + //------------------------------------------- + .dout({ dbg_group3_q[00:31] }) + ); + + + + + assign divsqrt_debug[0:63] = f_dsq_debug; + + + // FU is the first unit in the DBG chain + //assign trace_data_in[0:87] = debug_data_in[0:87]; + assign trace_data_in[0:31] = debug_bus_in[0:31]; + //assign trigger_data_in[0:11] = trace_triggers_in[0:11]; + + // Debug Events + // todo: width is only 32 bits now, might want to reorder this stuff + + assign dbg_group0[0:63] = ex8_ram_data[0:63]; + + assign dbg_group1[0:63] = divsqrt_debug[0:63]; + + assign dbg_group2[0:31] = ex1_instr[0:31] & {32{ (instr_trace_mode_q & (instr_trace_tid_q != ex1_tid)) }}; // gate instr if not tid; + + assign dbg_group2[32:35] = (f_scr_ex8_fx_thread0[0:3] & (~{4{instr_trace_mode_q}})); + assign dbg_group2[36:39] = (f_scr_ex8_fx_thread1[0:3] & (~{4{instr_trace_mode_q}})) | (4'b1010 & (~{4{instr_trace_mode_q}})); //a + assign dbg_group2[40:43] = (f_scr_cpl_fx_thread0[0:3] & (~{4{instr_trace_mode_q}})) | (4'b1011 & (~{4{instr_trace_mode_q}})); //b + assign dbg_group2[44:47] = (f_scr_cpl_fx_thread1[0:3] & (~{4{instr_trace_mode_q}})) | (4'b1100 & (~{4{instr_trace_mode_q}})); //c + assign dbg_group2[48:51] = (ex5_eff_addr[59:62] & (~{4{instr_trace_mode_q}})) | (4'b1101 & (~{4{instr_trace_mode_q}})); //d + + assign dbg_group2[52:55] = ({ex5_eff_addr[63], perr_sm_l2[0:2]} & (~{4{instr_trace_mode_q}})) | (4'b1110 & (~{4{instr_trace_mode_q}}));//e + assign dbg_group2[56:61] = perr_addr_l2[0:5] & (~{6{instr_trace_mode_q}}); + assign dbg_group2[62:63] = perr_tid_l2[0:1] & (~{2{instr_trace_mode_q}}); + + assign dbg_group3_din[00] = ex0_regfile_ce; + assign dbg_group3_din[01] = ex0_regfile_ue; + assign dbg_group3_din[02] = ex1_bypsel_a_res0; + assign dbg_group3_din[03] = ex1_bypsel_c_res0; + assign dbg_group3_din[04] = ex1_bypsel_b_res0; + assign dbg_group3_din[05] = ex1_bypsel_a_res1; + assign dbg_group3_din[06] = ex1_bypsel_c_res1; + assign dbg_group3_din[07] = ex1_bypsel_b_res1; + assign dbg_group3_din[08] = ex1_bypsel_a_load0; + assign dbg_group3_din[09] = ex1_bypsel_c_load0; + assign dbg_group3_din[10] = ex1_bypsel_b_load0; + assign dbg_group3_din[11] = ex1_bypsel_a_load1; + assign dbg_group3_din[12] = ex1_bypsel_c_load1; + assign dbg_group3_din[13] = ex1_bypsel_b_load1; + assign dbg_group3_din[14] = ex1_frs_byp; + assign dbg_group3_din[15] = ex1_v; + assign dbg_group3_din[16] = ex1_bypsel_a_res2; + assign dbg_group3_din[17] = ex1_bypsel_c_res2; + assign dbg_group3_din[18] = ex1_bypsel_b_res2; + assign dbg_group3_din[19] = ex1_bypsel_a_load2; + assign dbg_group3_din[20] = ex1_bypsel_c_load2; + assign dbg_group3_din[21] = ex1_bypsel_b_load2; + assign dbg_group3_din[22] = ex1_bypsel_a_load3; + assign dbg_group3_din[23] = ex1_bypsel_c_load3; + assign dbg_group3_din[24] = ex1_bypsel_b_load3; + assign dbg_group3_din[25] = ex1_bypsel_a_reload0; + assign dbg_group3_din[26] = ex1_bypsel_c_reload0; + assign dbg_group3_din[27] = ex1_bypsel_b_reload0; + assign dbg_group3_din[28] = ex1_bypsel_a_reload1; + assign dbg_group3_din[29] = ex1_bypsel_c_reload1; + assign dbg_group3_din[30] = ex1_bypsel_b_reload1; + assign dbg_group3_din[31] = tidn; + + assign dbg_group3[00:31] = dbg_group3_q[00:31]; + + assign dbg_group3[32:63] = {t0_events[0:7], t1_events[0:7], {16{tidn}} }; + + assign trg_group0[0:1] = evnt_fpu_fx[0:1]; + assign trg_group0[2:3] = evnt_fpu_cpl_fx[0:1]; + + assign trg_group0[4:5] = evnt_fpu_fex[0:1]; + assign trg_group0[6:7] = evnt_fpu_cpl_fex[0:1]; + assign trg_group0[8] = ex7_instr_valid; + assign trg_group0[9] = ex7_is_ucode; + assign trg_group0[10:11] = ex7_instr_tid[0:1]; + + assign trg_group1[0:2] = perr_sm_l2[0:2]; + assign trg_group1[3] = ex0_regfile_ce; + assign trg_group1[4] = ex0_regfile_ue; + assign trg_group1[5] = ex7_instr_valid; + assign trg_group1[6:7] = ex7_instr_tid[0:1]; + assign trg_group1[8] = ex4_instr_match; + assign trg_group1[9] = ex7_record; + assign trg_group1[10] = ex7_mcrfs; + assign trg_group1[11] = ex5_b_den_flush; + + assign trg_group2[0:11] = divsqrt_debug[0:11]; + assign trg_group3[0:11] = divsqrt_debug[12:23]; + + + assign debug_mux_ctrls_d = pc_fu_debug_mux_ctrls; // ARDSR[32:47] + + //sel2 unused rot sel tsel trot trigssel + assign debug_mux_ctrls_muxed[0:10] = debug_mux_ctrls_q[0:10]; + + // + tri_debug_mux4 #(.DBG_WIDTH(32)) dbgmux( + //.vd(vdd), + //.gd(gnd), + .select_bits(debug_mux_ctrls_muxed), + .dbg_group0(dbg_group0[0:31]), + .dbg_group1(dbg_group1[0:31]), + .dbg_group2(dbg_group2[0:31]), + .dbg_group3(dbg_group3[0:31]), + .trace_data_in(trace_data_in[0:31]), + .trace_data_out(trace_data_out[0:31]), + .coretrace_ctrls_in(coretrace_ctrls_in), + .coretrace_ctrls_out(coretrace_ctrls_out_d[0:3]) + + + ); + + assign debug_data_d[0:31] = trace_data_out[0:31]; + + assign coretrace_ctrls_out[0:3] = coretrace_ctrls_out_q; + + + assign ex5_b_den_flush_din = ex4_b_den_flush & |({ex4_instr_v[0:3], ex4_fdivsqrt_start}) & (~ex4_is_ucode); //don't flush on ucode preIssue + + // Trace Bus latches, using pc_fu_trace_bus_enable for act + + tri_rlmreg_p #(.INIT(0), .WIDTH(68)) dbg0_data( + .nclk(nclk), + .act(dbg0_act), + .force_t(func_slp_sl_force), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[9]), + .mpw1_b(mpw1_b[9]), + .mpw2_b(mpw2_b[1]), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(dbg0_data_si[0:67]), + .scout(dbg0_data_so[0:67]), + //------------------------------------------- + .din({ debug_data_d[0:31], + spare_unused[0:3], + spare_unused[31:42],//debug_trig_d[0:11], + coretrace_ctrls_out_d[0:3], + debug_mux_ctrls_d[0:10], + spare_unused[43:47]}), + //------------------------------------------- + .dout({ debug_data_q[0:31], + spare_unused[0:3], + spare_unused[31:42],//debug_trig_q[0:11], + coretrace_ctrls_out_q[0:3], + debug_mux_ctrls_q[0:10], + spare_unused[43:47]}) + ); + //------------------------------------------- + //Another set, closer to the I/O on the bottom + + tri_rlmreg_p #(.INIT(0), .WIDTH(5)) dbg1_data( + .nclk(nclk), + .act(tihi), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[9]), + .mpw1_b(mpw1_b[9]), + .mpw2_b(mpw2_b[1]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(dbg1_data_si[0:4]), + .scout(dbg1_data_so[0:4]), + //------------------------------------------- + .din(xu_fu_ex4_eff_addr[59:63]), + //------------------------------------------- + .dout(ex5_eff_addr[59:63]) + ); + //------------------------------------------- + + // To MMU, i'm the first in the chain + //assign debug_data_out[0:87] = debug_data_q[0:87]; + assign debug_bus_out[0:31] = debug_data_q[0:31]; + + assign axu0_iu_perf_events = {4{1'b0}}; + assign axu1_iu_perf_events = {4{1'b0}}; + + + //---------------------------------------------------------------------- + // unused + //todo + assign spare_unused[5:8] = {4{tidn}}; + assign spare_unused[9:11] = {3{tidn}}; + + //---------------------------------------------------------------------- + // Scan Connections + + assign ex1_iu_si[0:14] = {ex1_iu_so[1:14], f_dcd_si}; + assign act_lat_si[0:7] = {act_lat_so[1:7], ex1_iu_so[0]}; + assign cp_flush_reg0_si = act_lat_so[0]; + assign cp_flush_reg1_si = cp_flush_reg0_so; + assign ex1_frt_si[0:29] = {ex1_frt_so[1:29], cp_flush_reg1_so}; + assign ex1_instl_si[0:31] = {ex1_instl_so[1:31], ex1_frt_so[0]}; + assign ex1_itag_si[0:13] = {ex1_itag_so[1:13],ex1_instl_so[0]}; + assign ex2_itag_si[0:15] = {ex2_itag_so[1:15],ex1_itag_so[0]}; + assign ex3_itag_si[0:15] = {ex3_itag_so[1:15],ex2_itag_so[0]}; + assign ex4_itag_si[0:15] = {ex4_itag_so[1:15],ex3_itag_so[0]}; + assign ex5_itag_si[0:16] = {ex5_itag_so[1:16],ex4_itag_so[0]}; + assign ex6_itag_si[0:16] = {ex6_itag_so[1:16],ex5_itag_so[0]}; + assign ex7_itag_si[0:17] = {ex7_itag_so[1:17],ex6_itag_so[0]}; + assign ex8_itag_si[0:7] = {ex8_itag_so[1:7],ex7_itag_so[0]}; + + assign ex1_crbf_si[0:4] = {ex1_crbf_so[1:4],ex8_itag_so[0]}; + assign ex2_crbf_si[0:4] = {ex2_crbf_so[1:4],ex1_crbf_so[0]}; + assign ex3_crbf_si[0:4] = {ex3_crbf_so[1:4],ex2_crbf_so[0]}; + assign ex4_crbf_si[0:4] = {ex4_crbf_so[1:4],ex3_crbf_so[0]}; + assign ex5_crbf_si[0:4] = {ex5_crbf_so[1:4],ex4_crbf_so[0]}; + assign ex6_crbf_si[0:8] = {ex6_crbf_so[1:8],ex5_crbf_so[0]}; + assign ex7_crbf_si[0:8] = {ex7_crbf_so[1:8],ex6_crbf_so[0]}; + + + assign ex2_ctl_si[0:20] = {ex2_ctl_so[1:20], ex7_crbf_so[0]}; + assign ex2_frt_si[0:5] = {ex2_frt_so[1:5], ex2_ctl_so[0]}; + + assign ex0_iu_si[0:7] = {ex0_iu_so[1:7], ex2_frt_so[0]}; + assign ex0_frt_si[0:23] = {ex0_frt_so[1:23], ex0_iu_so[0]}; + + assign ex3_ctl_si[0:23] = {ex3_ctl_so[1:23], ex0_frt_so[0]}; + assign ex3_ctlng_si[0:6] = {ex3_ctlng_so[1:6], ex3_ctl_so[0]}; + + assign ex3_stdv_si = ex3_ctlng_so[0]; + assign ex4_ctl_si[0:29] = {ex4_ctl_so[1:29], ex3_stdv_so}; + assign ex5_ctl_si[0:21] = {ex5_ctl_so[1:21], ex4_ctl_so[0]}; + assign ex6_ctl_si[0:20] = {ex6_ctl_so[1:20], ex5_ctl_so[0]}; + assign ex7_ctl_si[0:22] = {ex7_ctl_so[1:22], ex6_ctl_so[0]}; + assign ex8_ctl_si[0:31] = {ex8_ctl_so[1:31], ex7_ctl_so[0]}; + assign ex9_ctl_si[0:13] = {ex9_ctl_so[1:13], ex8_ctl_so[0]}; + + assign ex7_laddr_si[0:17] = {ex7_laddr_so[1:17],ex9_ctl_so[0]}; + assign ex8_laddr_si[0:17] = {ex8_laddr_so[1:17],ex7_laddr_so[0]}; + assign ex9_laddr_si[0:8] = {ex9_laddr_so[1:8],ex8_laddr_so[0]}; + + assign axu_ex_si[0:3] = {axu_ex_so[1:3],ex9_laddr_so[0]}; + + + assign perr_si = axu_ex_so[0]; + + assign spr_ctl_si[0:14] = {spr_ctl_so[1:14], perr_so}; + assign spr_data_si[64 - (2 ** REGMODE):63] = {spr_data_so[65 - (2 ** REGMODE):63], spr_ctl_so[0]}; + assign ram_data_si[0:64] = {ram_data_so[1:64], spr_data_so[64 - (2 ** REGMODE)]}; + assign ram_datav_si[0] = ram_data_so[0]; + assign perf_data_si[0:34] = {perf_data_so[1:34], ram_datav_so[0]}; + assign event_bus_out_si[0:7] = {event_bus_out_so[1:7], perf_data_so[0]}; + assign dbg0_data_si[0:67] = {dbg0_data_so[1:67], event_bus_out_so[0]}; + assign dbg1_data_si[0:4] = {dbg1_data_so[1:4], dbg0_data_so[0]}; + + assign dbg_group3_lat_si[00:31] = {dbg_group3_lat_so[1:31], dbg1_data_so[0]}; + + assign f_dcd_so = dbg_group3_lat_so[0]; + + //dcfg ring + assign axucr0_lat_si[0:3] = {axucr0_lat_so[1:3], dcfg_scan_in}; + assign a0esr_lat_si[0:31] = {a0esr_lat_so[1:31], axucr0_lat_so[0]}; + assign dcfg_scan_out = a0esr_lat_so[0]; + +endmodule diff --git a/dev/verilog/work/fu_divsqrt.v b/dev/verilog/work/fu_divsqrt.v new file mode 100755 index 0000000..604cf35 --- /dev/null +++ b/dev/verilog/work/fu_divsqrt.v @@ -0,0 +1,3254 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//==########################################################################## +//==### FU_DIVSQRT.VHDL ######### +//==### ######### +//==########################################################################## + +`include "tri_a2o.vh" + +module fu_divsqrt( + vdd, + gnd, + clkoff_b, + act_dis, + flush, + delay_lclkr, + mpw1_b, + mpw2_b, + sg_1, + thold_1, + fpu_enable, + nclk, + f_dsq_si, + f_dsq_so, + ex0_act_b, + f_dcd_ex0_div, + f_dcd_ex0_divs, + f_dcd_ex0_sqrt, + f_dcd_ex0_sqrts, + f_dcd_ex0_record_v, + f_dcd_ex2_divsqrt_hole_v, + f_dcd_flush, + f_dcd_ex1_itag, + f_dcd_ex1_fpscr_addr, + f_dcd_ex1_instr_frt, + f_dcd_ex1_instr_tid, + f_dcd_ex1_divsqrt_cr_bf, + f_dcd_axucr0_deno, + f_scr_ex6_fpscr_rm_thr0, + f_scr_ex6_fpscr_ee_thr0, + f_scr_ex6_fpscr_rm_thr1, + f_scr_ex6_fpscr_ee_thr1, + f_fmt_ex2_a_sign_div, + f_fmt_ex2_a_expo_div_b, + f_fmt_ex2_a_frac_div, + f_fmt_ex2_b_sign_div, + f_fmt_ex2_b_expo_div_b, + f_fmt_ex2_b_frac_div, + f_fmt_ex2_a_zero, + f_fmt_ex2_a_zero_dsq, + f_fmt_ex2_a_expo_max, + f_fmt_ex2_a_expo_max_dsq, + f_fmt_ex2_a_frac_zero, + f_fmt_ex2_b_zero, + f_fmt_ex2_b_zero_dsq, + f_fmt_ex2_b_expo_max, + f_fmt_ex2_b_expo_max_dsq, + f_fmt_ex2_b_frac_zero, + f_dsq_ex3_hangcounter_trigger, + f_dsq_ex5_divsqrt_v, + f_dsq_ex6_divsqrt_v, + f_dsq_ex6_divsqrt_record_v, + f_dsq_ex6_divsqrt_v_suppress, + f_dsq_ex5_divsqrt_itag, + f_dsq_ex6_divsqrt_fpscr_addr, + f_dsq_ex6_divsqrt_instr_frt, + f_dsq_ex6_divsqrt_instr_tid, + f_dsq_ex6_divsqrt_cr_bf, + f_dsq_ex6_divsqrt_sign, + f_dsq_ex6_divsqrt_exp, + f_dsq_ex6_divsqrt_fract, + f_dsq_ex6_divsqrt_flag_fpscr, + f_dsq_debug +); + + inout vdd; + inout gnd; + + input clkoff_b; // tiup + input act_dis; // ??tidn?? + input flush; // ??tidn?? + input delay_lclkr; // tidn, + input mpw1_b; // tidn, + input mpw2_b; // tidn, + input sg_1; + input thold_1; + input fpu_enable; //dc_act + + input [0:`NCLK_WIDTH-1] nclk; + + //-------------------------------------------------------------------------- + input f_dsq_si; //perv scan + output f_dsq_so; //perv scan + input ex0_act_b; + //-------------------------------------------------------------------------- + input f_dcd_ex0_div; + input f_dcd_ex0_divs; + input f_dcd_ex0_sqrt; + input f_dcd_ex0_sqrts; + input f_dcd_ex0_record_v; + input f_dcd_ex2_divsqrt_hole_v; + //-------------------------------------------------------------------------- + input [0:1] f_dcd_flush; + input [0:6] f_dcd_ex1_itag; + input [0:5] f_dcd_ex1_fpscr_addr; + input [0:5] f_dcd_ex1_instr_frt; + input [0:3] f_dcd_ex1_instr_tid; + input [0:4] f_dcd_ex1_divsqrt_cr_bf; + input f_dcd_axucr0_deno; + + input [0:1] f_scr_ex6_fpscr_rm_thr0; + input [0:4] f_scr_ex6_fpscr_ee_thr0; // FPSCR VE,OE,UE,ZE,XE + input [0:1] f_scr_ex6_fpscr_rm_thr1; + input [0:4] f_scr_ex6_fpscr_ee_thr1; // FPSCR VE,OE,UE,ZE,XE + //-------------------------------------------------------------------------- + + input f_fmt_ex2_a_sign_div; // these operands are actually ex2 + input [01:13] f_fmt_ex2_a_expo_div_b; + input [01:52] f_fmt_ex2_a_frac_div; + + input f_fmt_ex2_b_sign_div; + input [01:13] f_fmt_ex2_b_expo_div_b; + input [01:52] f_fmt_ex2_b_frac_div; + + input f_fmt_ex2_a_zero; + input f_fmt_ex2_a_zero_dsq; + input f_fmt_ex2_a_expo_max; + input f_fmt_ex2_a_expo_max_dsq; + input f_fmt_ex2_a_frac_zero; + + input f_fmt_ex2_b_zero; + input f_fmt_ex2_b_zero_dsq; + input f_fmt_ex2_b_expo_max; + input f_fmt_ex2_b_expo_max_dsq; + input f_fmt_ex2_b_frac_zero; + + output f_dsq_ex3_hangcounter_trigger; + + //-------------------------------------------------------------------------- + output [0:1] f_dsq_ex5_divsqrt_v; + output [0:1] f_dsq_ex6_divsqrt_v; + output f_dsq_ex6_divsqrt_record_v; + output f_dsq_ex6_divsqrt_v_suppress; + output [0:6] f_dsq_ex5_divsqrt_itag; + output [0:5] f_dsq_ex6_divsqrt_fpscr_addr; + output [0:5] f_dsq_ex6_divsqrt_instr_frt; + output [0:3] f_dsq_ex6_divsqrt_instr_tid; + output [0:4] f_dsq_ex6_divsqrt_cr_bf; + output f_dsq_ex6_divsqrt_sign; // needs to be right off of a latch + output [01:13] f_dsq_ex6_divsqrt_exp; // needs to be right off of a latch + output [00:52] f_dsq_ex6_divsqrt_fract; // needs to be right off of a latch + output [00:15] f_dsq_ex6_divsqrt_flag_fpscr; + output [00:63] f_dsq_debug; + + //-------------------------------------------------------------------------- + + + + + + //==################################################ + + parameter tiup = 1'b1; + parameter tidn = 1'b0; + + wire sg_0; + wire thold_0_b; + wire thold_0; + wire force_t; + + //---------------------------------------------------------------------- + // todo items: + + + //---------------------------------------------------------------------- + + wire [00:56] zeros; + wire [00:27] ones; + + wire ex0_act; + wire ex1_act; + wire ex2_act; + wire ex3_act; + wire ex4_act; + wire [0:7] act_so; + wire [0:7] act_si; + + wire [0:14] ex1_div_instr_lat_scin; + wire [0:14] ex1_div_instr_lat_scout; + wire [0:5] ex2_div_instr_lat_scin; + wire [0:5] ex2_div_instr_lat_scout; + wire [0:8] ex2_itag_lat_scin; + wire [0:8] ex2_itag_lat_scout; + wire [0:27] ex2_fpscr_addr_lat_scin; + wire [0:27] ex2_fpscr_addr_lat_scout; + + wire [0:18] ex1_div_ctr_lat_scin; + wire [0:18] ex1_div_ctr_lat_scout; + wire [0:95] ex5_div_result_lat_scin; + wire [0:95] ex5_div_result_lat_scout; + wire [0:65] ex6_div_result_lat_scin; + wire [0:65] ex6_div_result_lat_scout; + wire [0:162] ex5_special_case_lat_scin; + wire [0:162] ex5_special_case_lat_scout; + wire [0:3] ex5_div_done_lat_scout; + wire [0:3] ex5_div_done_lat_scin; + wire HW165073_bits; + wire HW165073_hit; + + wire ex1_divsqrt_running_d; + wire exx_divsqrt_running_q; + wire ex1_divsqrt_done; + wire ex2_divsqrt_done; + wire ex2_divsqrt_done_din; + wire ex2_waiting_for_hole; + + wire ex2_divsqrt_zero; + wire ex3_divsqrt_done_din; + wire ex4_divsqrt_done_din; + wire ex5_divsqrt_done_din; + wire ex3_divsqrt_done; + wire ex4_divsqrt_done; + wire ex4_divsqrt_done_q; + wire ex5_divsqrt_done; + wire ex6_divsqrt_done; + wire ex4_start_a_denorm_result; + wire ex4_start_denorm_result; + wire ex4_denormalizing_result; + wire ex4_denormalizing_result_done; + wire ex4_denormalizing_result_done_din; + wire ex5_denormalizing_result_done; + wire ex4_denormalizing_result_shifting; + wire ex4_divsqrt_denorm_hold; + wire ex4_denormalizing_result_rounding; + wire ex4_start_sp_denorm_result; + wire exp_eq_369; + wire exp_eq_380; + wire exp_eq_368; + wire exp_eq_367; + wire exp_eq_367to9; + wire ex4_force_36A; + wire ex4_force; + wire ex4_dnr_roundup_incexp; + wire ex4_roundup_incexp; + + wire ex4_x_roundup_incexp; + wire ex5_x_roundup_incexp; + + wire [0:70] ex2_div_a_stage_lat_scout; + wire [0:70] ex2_div_a_stage_lat_scin; + wire [0:70] ex2_div_b_stage_lat_scout; + wire [0:70] ex2_div_b_stage_lat_scin; + wire [0:113] ex3_div_PR_sumcarry_lat_scout; + wire [0:113] ex3_div_PR_sumcarry_lat_scin; + wire [0:7] ex3_div_PR_sum4carry4_lat_scout; + wire [0:7] ex3_div_PR_sum4carry4_lat_scin; + wire [0:113] ex3_div_Q_QM_lat_scin; + wire [0:113] ex3_div_Q_QM_lat_scout; + wire [0:113] ex3_div_bQ_QM_lat_scin; + wire [0:113] ex3_div_bQ_QM_lat_scout; + + wire [0:167] ex3_sqrt_bitmask_lat_scin; + wire [0:167] ex3_sqrt_bitmask_lat_scout; + wire [0:51] ex2_div_exp_lat_scout; + wire [0:51] ex2_div_exp_lat_scin; + + wire [0:55] ex3_denom_lat_scout; + wire [0:55] ex3_denom_lat_scin; + wire [0:26] exx_div_denorm_lat_scout; + wire [0:26] exx_div_denorm_lat_scin; + wire ex4_deno_force_zero; + + wire exx_running_act_d; + wire exx_running_act_q; + + (* analysis_not_referenced="TRUE" *) + wire [0:3] act_spare_unused; + (* analysis_not_referenced="TRUE" *) + wire [0:880] spare_unused; + + wire ex0_record_v; + wire ex1_record_v; + wire ex2_record_v; + wire exx_record_v_din; + wire exx_record_v_q; + wire ex0_div; + wire ex0_divs; + wire ex0_sqrt; + wire ex0_sqrts; + wire ex1_div; + wire ex1_divs; + wire ex1_sqrt; + wire ex1_sqrts; + wire ex1_div_dout; + wire ex1_divs_dout; + wire ex1_sqrt_dout; + wire ex1_sqrts_dout; + + wire ex2_div; + wire ex2_divs; + wire ex2_sqrt; + wire ex2_sqrts; + wire ex2_sp; + wire ex1_instr_v; + + wire ex2_div_or_divs; + wire ex2_sqrt_or_sqrts; + wire ex0_anydivsqrt; + wire ex1_anydivsqrt; + wire ex2_anydivsqrt; + wire ex3_anydivsqrt; + wire ex4_anydivsqrt; + wire ex5_anydivsqrt; + wire ex6_anydivsqrt; + wire [0:6] ex1_itag_din; + wire [0:6] exx_itag_q; + wire [0:5] ex1_fpscr_addr_din; + wire [0:5] exx_fpscr_addr_q; + wire [0:5] ex1_instr_frt_din; + wire [0:5] exx_instr_frt_q; + wire [0:3] ex1_instr_tid_din; + wire [0:3] exx_instr_tid_q; + wire [0:1] tid_init; + wire [0:1] tid_hold; + wire [0:1] tid_clear; + wire [0:4] ex1_cr_bf_din; + wire [0:4] exx_cr_bf_q; + + wire [0:7] ex0_op_cyc_count_din; + wire [0:7] ex1_op_cyc_count; + + wire [0:7] ex2_hangcounter_din; + wire [0:7] ex3_hangcounter_q; + + wire [0:7] ex3_div_hangcounter_lat_scout; + wire [0:7] ex3_div_hangcounter_lat_scin; + + wire [0:63] f_dsq_debug_din; + wire [0:63] f_dsq_debug_q; + wire [0:63] f_dsq_debug_lat_scin; + wire [0:63] f_dsq_debug_lat_scout; + + wire ex2_hangcounter_clear; + wire ex2_hangcounter_incr; + wire ex3_hangcounter_trigger; + + wire ex4_sp; + wire ex4_dp; + wire exx_sp; + wire exx_dp; + + wire ex1_cycles_init; + wire ex1_cycles_decr; + wire ex1_cycles_hold; + wire ex1_cycles_clear; + wire exx_single_precision_d; + wire exx_single_precision_q; + + wire ex2_a_zero; + wire ex2_a_SPunderflow_zero; + wire ex2_a_expo_max; + wire ex2_a_SPoverflow_expo_max; + wire ex2_b_SPoverflow_expo_max; + + wire ex2_a_frac_zero; + wire ex2_b_zero; + wire ex2_b_SPunderflow_zero; + + wire ex2_b_expo_max; + wire ex2_b_frac_zero; + + wire exx_a_zero_d; + wire exx_a_expo_max_d; + wire exx_a_frac_zero_d; + wire exx_b_zero_d; + wire exx_a_SPunderflow_zero_d; + wire exx_b_SPunderflow_zero_d; + wire exx_a_SPoverflow_expo_max_d; + wire exx_b_SPoverflow_expo_max_d; + wire exx_a_SPoverflow_expo_max_q; + wire exx_b_SPoverflow_expo_max_q; + + wire exx_b_expo_max_d; + wire exx_b_frac_zero_d; + + wire exx_a_zero_q; + wire exx_b_SPunderflow_zero_q; + wire exx_a_SPunderflow_zero_q; + + wire exx_a_expo_max_q; + wire exx_a_frac_zero_q; + wire exx_b_zero_q; + wire exx_b_expo_max_q; + wire exx_b_frac_zero_q; + + wire exx_a_NAN; + wire exx_b_NAN; + wire exx_a_INF; + wire exx_b_INF; + wire exx_a_SPoverflowINF; + wire exx_b_SPoverflowINF; + wire exx_b_ZER; + wire exx_a_ZER; + wire exx_b_SPunderflowZER; + wire exx_a_SPunderflowZER; + wire ex4_a_snan; + wire ex4_b_snan; + wire ex4_snan; + wire exx_hard_spec_case; + + wire ex4_div_by_zero_zx; + wire ex4_zero_div_zero; + wire ex4_inf_div_inf; + wire ex4_sqrt_neg; + + wire ex4_pass_a_nan; + wire ex4_pass_b_nan; + wire ex4_pass_nan; + wire ex4_pass_a_nan_sp; + wire ex4_pass_b_nan_sp; + wire ex4_pass_a_nan_dp; + wire ex4_pass_b_nan_dp; + + wire exx_divsqrt_v_suppress_d; + wire exx_divsqrt_v_suppress_q; + + wire ex4_force_zero; + wire ex4_force_zeroone; + wire ex4_force_inf; + wire ex5_force_inf; + wire ex4_force_maxnorm; + wire ex4_force_maxnorm_sp; + wire ex4_force_maxnorm_dp; + wire ex4_force_qnan; + wire ex4_div_special_case; + wire ex5_div_special_case; + wire exx_sqrt_d; + wire exx_div_d; + + wire [00:03] exx_div_q; + wire [00:03] exx_sqrt_q; + wire [00:06] exx_fpscr_din; + wire [00:06] exx_fpscr_q; + + wire [00:52] ex4_divsqrt_fract; + wire [00:56] ex4_divsqrt_fract_cur; + wire [00:56] ex4_divsqrt_fract_shifted; + wire [00:56] ex4_divsqrt_fract_shifted_dp; + wire [00:56] ex4_divsqrt_fract_shifted_spmasked; + wire [00:56] ex4_divsqrt_fract_stickymask; + wire [00:53] ex4_divsqrt_fract_dnr; + + wire dn_lv1sh00; + wire dn_lv1sh01; + wire dn_lv1sh10; + wire dn_lv1sh11; + wire dn_lv2sh00; + wire dn_lv2sh01; + wire dn_lv2sh10; + wire dn_lv2sh11; + wire dn_lv3sh00; + wire dn_lv3sh01; + wire dn_lv3sh10; + wire dn_lv3sh11; + wire dnsp_lv1sh00; + wire dnsp_lv1sh01; + wire dnsp_lv1sh10; + wire dnsp_lv1sh11; + wire dnsp_lv2sh00; + wire dnsp_lv2sh01; + wire dnsp_lv2sh10; + wire dnsp_lv2sh11; + wire dnsp_lv3sh00; + wire dnsp_lv3sh01; + wire dnsp_lv3sh10; + wire dnsp_lv3sh11; + + wire [00:59] ex4_divsqrt_fract_shifted_00to03; + wire [00:71] ex4_divsqrt_fract_shifted_00to12; + wire [00:119] ex4_divsqrt_fract_shifted_00to48; + wire [00:56] ex4_spdenorm_mask; + wire [00:59] ex4_spdenorm_mask_shifted_00to03; + wire [00:71] ex4_spdenorm_mask_shifted_00to12; + wire [00:119] ex4_spdenorm_mask_shifted_00to48; + wire [00:56] ex4_spdenorm_mask_lsb; + wire [00:59] ex4_spdenorm_mask_lsb_shifted_00to03; + wire [00:71] ex4_spdenorm_mask_lsb_shifted_00to12; + wire [00:119] ex4_spdenorm_mask_lsb_shifted_00to48; + wire [00:56] ex4_spdenorm_mask_guard; + wire [00:59] ex4_spdenorm_mask_guard_shifted_00to03; + wire [00:71] ex4_spdenorm_mask_guard_shifted_00to12; + wire [00:119] ex4_spdenorm_mask_guard_shifted_00to48; + wire [00:56] ex4_spdenorm_mask_round; + wire [00:59] ex4_spdenorm_mask_round_shifted_00to03; + wire [00:71] ex4_spdenorm_mask_round_shifted_00to12; + wire [00:119] ex4_spdenorm_mask_round_shifted_00to48; + + wire [00:52] ex4_divsqrt_fract_special; + wire [00:52] ex5_divsqrt_fract_special; + wire [00:52] ex5_divsqrt_fract_d; + wire [00:52] ex6_divsqrt_fract_q; + + wire [01:13] ex4_divsqrt_exp; + wire [01:13] ex4_divsqrt_exp_special; + wire [01:13] ex5_divsqrt_exp_special; + wire [01:13] ex5_divsqrt_exp_d; + wire [01:13] ex6_divsqrt_exp_q; + wire ex4_maxnorm_sign; + wire ex4_divsqrt_sign; + wire ex4_divsqrt_sign_special; + + wire [1:52] ex2_b_fract; + + wire [1:52] ex2_a_fract; + + wire exx_a_sign_d; + wire [1:13] exx_a_biased_13exp_d; + wire [1:52] exx_a_fract_d; + + wire exx_b_sign_d; + wire [1:13] exx_b_biased_13exp_d; + wire [1:52] exx_b_fract_d; + + wire exx_a_sign_q; + wire [1:13] exx_a_biased_13exp_q; + wire [1:52] exx_a_fract_q; + + wire exx_b_sign_q; + wire [1:13] exx_b_biased_13exp_q; + wire [1:52] exx_b_fract_q; + + wire [1:13] exx_exp_ux_adj; + wire [1:13] exx_exp_ux_adj_dp; + wire [1:13] exx_exp_ux_adj_sp; + wire [1:13] exx_exp_ox_adj; + wire [1:13] exx_exp_ox_adj_dp; + wire [1:13] exx_exp_ox_adj_sp; + wire exx_invalid_mixed_precision; + + wire [1:13] exx_b_ubexp; + wire [1:13] exy_b_ubexp; + wire [1:13] exx_exp_adj; + wire [1:13] exx_exp_adj_p1; + wire [0:12] exz_exp_addres_x0; + wire [0:12] exx_exp_addres_ux; + wire [0:12] exx_exp_addres_ox; + wire [0:12] exx_exp_addres; + wire [0:12] exx_exp_addres_div_x0; + wire [0:12] exx_exp_addres_sqrt_x0; + wire [0:12] exy_exp_addres_div_x0; + wire [0:12] exy_exp_addres_div_x0_m1; + wire [0:12] exz_exp_addres_div_x0_m1; + wire [0:12] exz_exp_addres_div_x0_adj; + wire [0:12] exy_exp_addres_sqrt_x0; + + wire [0:12] exx_exp_addres_x0_p1; + wire [0:12] exx_exp_addres_ux_p1; + wire [0:12] exx_exp_addres_ox_p1; + wire [0:12] exy_exp_addres_x0_p1; + wire [0:12] exy_exp_addres_ux_p1; + wire [0:12] exy_exp_addres_ox_p1; + wire [0:12] exy_exp_addres_p1; + wire [0:12] exx_exp_addres_div_x0_p1; + wire [0:12] exx_exp_addres_sqrt_x0_p1; + + wire ex4_expresult_zero; + wire [7:12] denorm_count_start; + wire [0:5] denorm_shift_amt; + wire [0:5] denorm_shift_amt_din; + wire [0:5] denorm_shift_amt_q; + wire [0:5] sp_denorm_shift_amt; + wire [0:5] sp_denorm_shift_amt_din; + wire [0:5] sp_denorm_shift_amt_q; + wire ex2_divsqrt_hole_v_b; + + + wire overflow; + wire underflow; + wire ueux; + wire oeox; + wire zezx; + wire vevx; + wire not_ueux_or_oeox; + wire exy_not_ueux_or_oeox; + wire exy_oeox; + wire exy_ueux; + + wire overflow_sp; + wire sp_overflow_brink_x47E; + wire ex4_incexp_to_sp_overflow; + wire dp_overflow_brink_x7FE; + wire ex4_incexp_to_dp_overflow; + wire ex4_incexp_to_overflow; + wire underflow_sp; + wire overflow_dp; + wire underflow_dp; + wire underflow_denorm; + wire underflow_denorm_dp; + wire underflow_denorm_sp; + wire underflow_force_zero; + wire underflow_force_36A; + wire underflow_force_zeroone; + wire overflow_force_inf; + wire special_force_zero; + wire special_force_inf; + wire overflow_force_maxnorm; + wire underflow_sp_denorm; + wire sp_denorm_0x369roundup; + wire sp_denorm_underflow_zero; + wire sp_denorm_0x380roundup; + + wire exx_q_bit0; + wire exx_q_bit0_cin; + wire exx_q_bit1; + wire exx_q_bit1_div; + wire exx_q_bit1_sqrt; + wire exx_q_bit1_cin_div; + wire exx_q_bit1_cin_sqrt; + wire exx_q_bit2; + wire exx_q_bit2_cin; + wire exx_q_bit3_div; + wire exx_q_bit3_cin_div; + wire exx_q_bit3_sqrt; + wire exx_q_bit3_cin_sqrt; + wire exx_q_bit3; + wire exx_nq_bit3; + wire [0:1] exx_q_bit22_sel; + + wire exx_nq_bit0; + wire exx_nq_bit1; + wire exx_nq_bit1_div; + wire exx_nq_bit1_sqrt; + wire exx_nq_bit2; + wire exx_nq_bit3_div; + wire exx_nq_bit3_sqrt; + + wire exx_notqornq_bit1_sqrt; + wire exx_notqornq_bit2; + wire exx_notqornq_bit3_sqrt; + + wire exx_notqornq_bit1_div; + wire exx_notqornq_bit3_div; + + wire exx_q_bit22; + wire exx_nq_bit22; + wire exx_q_bit22_div; + wire exx_nq_bit22_div; + wire exx_q_bit22_sqrt; + wire exx_nq_bit22_sqrt; + + wire exx_notqornq_bit22_sqrt; + wire exx_notqornq_bit22_div; + + wire exx_q_bit0_b; + wire exx_nq_bit0_b; + wire exx_q_bit0_prebuf; + wire exx_nq_bit0_prebuf; + + + wire [0:56] exx_Q_q; + wire [0:56] exx_Q_d; + wire [0:56] exx_QM_q; + wire [0:56] exx_QM_d; + wire [0:56] exx_bQ_q; + wire [0:56] exx_bQ_d; + wire [0:56] exx_bQM_q; + wire [0:56] exx_bQM_d; + + wire [0:56] exx_lev0_csaout_sum; + wire [0:56] exx_lev0_csaout_carry; + wire [0:56] exx_lev0_csaoutsh_sum; + wire [0:56] exx_lev0_csaoutsh_carry; + wire exx_lev0_selD; + wire exx_lev0_selnD; + wire exx_lev0_selneg; + wire exx_lev0_selD_b; + wire exx_lev0_selnD_b; + + wire exx_lev0_selQ; + wire exx_lev0_selMQ; + wire exx_lev0_selQ_b; + wire exx_lev0_selMQ_b; + + wire exx_lev22_selD; + wire exx_lev22_selnD; + wire exx_lev22_selneg; + wire exx_lev22_selQ; + wire exx_lev22_selMQ; + + wire [0:56] exx_lev0_csaout_carryout; + + wire [0:56] exx_lev0_divsqrt_csaout_xor; + wire [0:56] exx_lev1_divsqrt_csaout_xor; + wire [0:56] exx_lev3_divsqrt_csaout_xor; + + + wire [0:56] exx_lev1_div_oper; + wire [0:56] exx_lev1_sqrt_oper; + wire [0:56] exx_lev3_div_oper; + wire [0:56] exx_lev3_sqrt_oper; + + wire [0:56] exx_lev1_div_csaout_sum; + wire [0:56] exx_lev1_div_csaout_carry; + wire [0:56] exx_lev1_sqrt_csaout_sum; + wire [0:56] exx_lev1_sqrt_csaout_carry; + + wire [0:56] exx_lev2_csaout_sum; + wire [0:56] exx_lev2_csaout_carry; + + wire [0:56] exx_lev3_div_csaout_sum; + wire [0:56] exx_lev3_div_csaout_carry; + wire [0:56] exx_lev3_sqrt_csaout_sum; + wire [0:56] exx_lev3_sqrt_csaout_carry; + + wire [0:56] exx_lev1_div_csaout_carryout; + wire [0:56] exx_lev1_sqrt_csaout_carryout; + + wire [0:56] exx_lev2_csaout_carryout; + wire [0:56] exx_lev3_div_csaout_carryout; + wire [0:56] exx_lev3_sqrt_csaout_carryout; + wire [0:56] exx_lev22_csaout_carryout_div; + wire [0:56] exx_lev22_csaout_carryout_sqrt; + wire [0:56] exx_lev22_csaout_sum_sqrt; + + wire [0:56] exx_lev22_csaout_carry_sqrt; + wire [0:56] exx_lev22_csaout_sum_div; + + wire [0:56] exx_lev22_csaout_carry_div; + wire [0:56] exx_lev22_csaout_sum_xor; + + wire [0:56] exx_PR_sum_d; + wire [0:56] exx_PR_sum_q; + wire [0:56] exx_PR_sum_d_late; + wire [0:56] exx_PR_sum_d_early; + wire [0:3] exx_PR_sum4_q; + + wire [0:56] ex3_divsqrt_remainder; + wire [0:56] ex4_divsqrt_remainder; + + wire ex3_rem_neg; + wire ex3_rem_neg_b; + + wire [0:3] ex4_rem_neg; + wire [0:3] ex4_rem_neg_b; + + wire [0:56] ex4_rem_neg_buf; + wire [0:56] ex4_rem_neg_buf_b; + + wire ex4_rem_nonzero; + wire ex4_rem_nonzero_fi; + wire underflow_fi; + wire ex4_round_up; + wire ex4_round_up_underflow; + wire ex4_round_up_dnr; + wire ex3_norm_shl1; + wire ex3_norm_shl1_dp; + wire ex3_norm_shl1_sp; + wire ex4_norm_shl1; + wire ex4_norm_shl1_q; + wire ex4_norm_shl1_d; + wire ex4_norm_shl1_test; + + wire [0:56] exx_PR_carry_d; + wire [0:56] exx_PR_carry_q; + wire [0:3] exx_PR_carry4_q; + + wire [0:56] exx_PR_sum_shift; + wire [0:56] exx_PR_sum_final; + wire [0:56] exx_PR_carry_shift; + wire [0:56] exx_PR_carry_final; + wire [0:56] exx_PR_sum_q_shifted; + wire [0:56] exx_PR_carry_q_shifted; + + wire [0:56] exx_Qin_lev0; + wire [0:56] exx_QMin_lev0; + wire [0:56] exx_Qin_lev1_sqrt; + wire [0:56] exx_QMin_lev1_sqrt; + wire [0:56] exx_Qin_lev1_div; + wire [0:56] exx_QMin_lev1_div; + + wire [0:56] exx_bQin_lev1_sqrt; + wire [0:56] exx_bQMin_lev1_sqrt; + wire [0:56] exx_bQ_q_t; + wire [0:56] exx_bQM_q_t; + + wire exx_Qin_lev0_sel0; + wire exx_Qin_lev0_sel1; + wire exx_QMin_lev0_sel0; + wire exx_QMin_lev0_sel1; + wire exx_QMin_lev0_sel2; + wire exx_Qin_lev1_sel0_sqrt; + wire exx_Qin_lev1_sel1_sqrt; + wire exx_Qin_lev1_sel0_div; + wire exx_Qin_lev1_sel1_div; + + wire exx_QMin_lev1_sel0_div; + wire exx_QMin_lev1_sel1_div; + wire exx_QMin_lev1_sel2_div; + wire exx_QMin_lev1_sel0_sqrt; + wire exx_QMin_lev1_sel1_sqrt; + wire exx_QMin_lev1_sel2_sqrt; + + wire [0:3] exx_sum4; + wire [0:3] exx_sum4_lev1_div; + wire [0:3] exx_sum4_lev1_sqrt; + wire [0:3] exx_sum4_lev2; + wire [0:3] exx_sum4_lev3_div; + wire [0:3] exx_sum4_lev3_sqrt; + + wire [0:55] exx_denom_d; + wire [0:55] exx_denom_q; + wire [0:55] exx_denomQ_lev0; + wire [0:55] exx_denomQ_lev22_div; + wire [0:55] exx_denomQ_lev22_sqrt; + wire [0:55] exx_denomQ_lev0_nD_b; + wire [0:55] exx_denomQ_lev0_D_b; + wire [0:55] exx_denomQ_lev0_Q_b; + wire [0:55] exx_denomQ_lev0_MQ_b; + wire [0:55] exx_sqrtlev0_Q; + wire [0:55] exx_sqrtlev0_MQ; + wire [0:55] exx_sqrt_newbitmask_din; + wire [0:55] exx_sqrt_newbitmask_q; + wire [0:55] exx_sqrt_Qbitmask_din; + wire [0:55] exx_sqrt_Qbitmask_q; + wire [0:55] exx_sqrt_QMbitmask_din; + wire [0:55] exx_sqrt_QMbitmask_q; + + wire [0:55] exx_sqrt_Qmaskvec; + wire [0:55] exx_sqrt_QMmaskvec; + wire wQ; + wire wMQ; + wire [0:55] exx_sqrtlev22_Q; + wire [0:55] exx_sqrtlev22_MQ; + wire [0:55] exx_bQin_lev0; + wire [0:55] exx_bQMin_lev0; + wire [0:55] exx_bQin_lev0_t; + wire [0:55] exx_bQMin_lev0_t; + + wire ex2_PR_sum_sel0; + wire ex2_PR_sum_sel1; + wire ex2_PR_sum_sel2; + wire ex2_PR_sum_sel3; + wire ex2_PR_sum_sel4; + wire ex2_PR_sum_sel_late; + wire ex2_PR_sum_sel_early; + wire ex2_PR_carry_sel0; + wire ex2_PR_carry_sel1; + wire ex2_PR_carry_sel2; + + wire [00:56] ex4_divsqrt_fract_preround; + wire [00:56] ex4_divsqrt_fract_preround_prenorm; + + wire [00:53] ex4_divsqrt_fract_p0; + wire [00:53] ex4_divsqrt_fract_p1; + wire [00:53] ex5_divsqrt_fract_p1; + wire ex5_round_up; + + wire [00:53] ex4_divsqrt_fract_dnr_p0; + wire [00:53] ex4_divsqrt_fract_dnr_p1; + wire [00:53] ex4_divsqrt_fract_dnr_sp_p0; + wire [00:53] ex4_divsqrt_fract_dnr_sp_p1; + wire [00:53] ex4_divsqrt_fract_dnr_dp; + wire [00:53] ex4_divsqrt_fract_dnr_sp; + wire [00:53] ex4_divsqrt_fract_dnr_sp_prem; + + wire denorm_res_shiftoff_exp; + wire denorm_res_shiftoff_din; + wire denorm_res_shiftoff_q; + wire ex4_denorm_res_shiftoff_zero; + wire [00:53] ex4_divsqrt_fract_p0_sp; + wire [00:53] ex4_divsqrt_fract_p1_sp; + wire [00:53] ex4_divsqrt_fract_p0_dp; + wire [00:53] ex4_divsqrt_fract_p1_dp; + wire [00:53] ex4_divsqrt_fract_rounded; + + wire exx_divsqrt_sign_d; + wire [01:13] exx_divsqrt_exp_d; + wire [00:56] exx_divsqrt_fract_d; + wire [00:15] exx_divsqrt_flag_fpscr_d; + + wire exx_divsqrt_sign_q; + wire [01:13] exx_divsqrt_exp_q; + wire [00:56] exx_divsqrt_fract_q; + wire [00:15] exx_divsqrt_flag_fpscr_q; + + wire n_flush_d; + wire n_flush; + + wire [01:13] f_fmt_ex2_b_expo_div; + wire [01:13] f_fmt_ex2_a_expo_div; + + wire [0:7] ex1_cycles_d; + wire [0:7] ex2_cycles_q; + wire lsb; + wire guard; + wire round; + wire sticky; + wire sticky_w_underflow; + wire denorm_sticky; + wire denorm_sticky_q; + wire denorm_sticky_din; + wire sign; + wire denorm_sticky_sp; + wire denorm_sticky_sp_q; + wire denorm_sticky_sp_din; + wire lsb_dnr; + wire guard_dnr; + wire round_dnr; + wire sticky_dnr; + wire lsb_dnr_sp; + wire guard_dnr_sp; + wire round_dnr_sp; + wire sticky_dnr_sp; + wire ex4_round_up_dnr_sp; + + wire RNEmode; + wire RTZmode; + wire RPImode; + wire RNImode; + + wire ex4_sp_inexact_roundbits; + wire ex4_denorm_result_det; + wire exp_gt_cap; + wire ex4_sp_denorm_result_det; + wire ex4_exp_le_896; + wire [00:13] denorm_exp_addres; + wire [00:13] denorm_exp_addres_sp; + wire [00:05] denorm_count_din; + wire [00:05] denorm_count_q; + wire VE; // FPSCR VE,OE,UE,ZE,XE + wire OE; + wire UE; + wire ZE; + wire XE; + + //==########################################## + //# pervasive + //==########################################## + + tri_plat #(.WIDTH(1)) thold_reg_0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(flush), + .din(thold_1), + .q(thold_0) + ); + + + tri_plat #(.WIDTH(1)) sg_reg_0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(flush), + .din(sg_1), + .q(sg_0) + ); + + + tri_lcbor lcbor_0( + .clkoff_b(clkoff_b), + .thold(thold_0), + .sg(sg_0), + .act_dis(act_dis), + .force_t(force_t), + .thold_b(thold_0_b) + ); + + //==########################################## + + assign ex0_act = (~ex0_act_b); + + assign n_flush_d = (f_dcd_flush[0] & exx_instr_tid_q[0]) | (f_dcd_flush[1] & exx_instr_tid_q[1]); + + assign exx_running_act_d = (ex0_anydivsqrt | exx_running_act_q) & (~(ex4_divsqrt_done | n_flush)); + + + tri_rlmreg_p #(.INIT(0), .WIDTH(8), .NEEDS_SRESET(0)) act_lat( + .force_t(force_t), + .d_mode(tiup), + + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(thold_0_b), + .sg(sg_0), + .scout(act_so), + .scin(act_si), + //----------------- + .din({ + exx_running_act_d, + tidn, + ex0_act, + ex1_act, + ex2_act, + ex3_act, + n_flush_d, + tidn + }), + //----------------- + .dout({ + exx_running_act_q, + act_spare_unused[1], + ex1_act, + ex2_act, + ex3_act, + ex4_act, + n_flush, + act_spare_unused[3] + }) + ); + + //==########################################## + + assign zeros = {57{1'b0}}; + assign ones = {28{1'b1}}; + + + assign act_spare_unused[0] = tidn; + assign act_spare_unused[2] = tidn; + + //---------------------------------------------------------------------- + //---------------------------------------------------------------------- + // Algorithm + // + // + + // cyc xx ex1_divsqrt_done=1, final cycle that the fract path is functioning for the main fract bits + // cyc xx ex2_divsqrt_done=1, extra 2 rounding bits generated, initial normalize (possible SHL by 1) + // cyc xx ex3_divsqrt_done=1, round + // cyc xx ex4_divsqrt_done=1, renormalize after rounding, compute the final exponent (+expadj) + // cyc xx ex5_divsqrt_done=1, final result is on the bus, directly off of the latch + // cyc xx + //---------------------------------------------------------------------- + //---------------------------------------------------------------------- + + //---------------------------------------------------------------------- + + assign ex0_div = f_dcd_ex0_div; + assign ex0_divs = f_dcd_ex0_divs; + assign ex0_sqrt = f_dcd_ex0_sqrt; + assign ex0_sqrts = f_dcd_ex0_sqrts; + assign ex0_record_v = f_dcd_ex0_record_v; + + assign ex0_anydivsqrt = ex0_div | ex0_sqrt | ex0_divs | ex0_sqrts; + + assign ex0_op_cyc_count_din[0:7] = (8'b00011110 & {8{ex0_div}}) | //0d30 + (8'b00010000 & {8{ex0_divs}}) | //0d16 + (8'b00011101 & {8{ex0_sqrt}}) | //0d29 + (8'b00001111 & {8{ex0_sqrts}}); //0d15 + + + + tri_rlmreg_p #(.INIT(0), .WIDTH(15), .NEEDS_SRESET(0)) ex1_div_instr_lat( + .force_t(force_t), .d_mode(tiup), .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + //----------------- + .act(tiup), + //----------------- + .scout(ex1_div_instr_lat_scout), + .scin(ex1_div_instr_lat_scin), + //----------------- + .din({ + ex0_div, + ex0_divs, + ex0_sqrt, + ex0_sqrts, + ex0_record_v, + ex0_op_cyc_count_din, + ex4_anydivsqrt, + ex5_anydivsqrt}), + //----------------- + .dout({ + ex1_div_dout, + ex1_divs_dout, + ex1_sqrt_dout, + ex1_sqrts_dout, + ex1_record_v, + ex1_op_cyc_count, + ex5_anydivsqrt, + ex6_anydivsqrt}) + ); + + + + assign ex1_instr_v = |(f_dcd_ex1_instr_tid[0:3]); //or_reduce(f_dcd_ex1_instr_tid[0:3]); + assign ex1_div = ex1_div_dout & ex1_instr_v; + assign ex1_divs = ex1_divs_dout & ex1_instr_v; + assign ex1_sqrt = ex1_sqrt_dout & ex1_instr_v; + assign ex1_sqrts = ex1_sqrts_dout & ex1_instr_v; + + assign ex1_anydivsqrt = ex1_div | ex1_sqrt | ex1_divs | ex1_sqrts; + + + tri_rlmreg_p #(.INIT(0), .WIDTH(6), .NEEDS_SRESET(0)) ex2_div_instr_lat( + .force_t(force_t), .d_mode(tiup), .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + //----------------- + .act(tiup), + //----------------- + .scout(ex2_div_instr_lat_scout), + .scin(ex2_div_instr_lat_scin), + //----------------- + .din({ + ex1_div, + ex1_divs, + ex1_sqrt, + ex1_sqrts, + ex1_record_v, + ex1_anydivsqrt}), + //----------------- + .dout({ + ex2_div, + ex2_divs, + ex2_sqrt, + ex2_sqrts, + ex2_record_v, + ex2_anydivsqrt}) + ); + + assign ex2_div_or_divs = ex2_div | ex2_divs; + assign ex2_sqrt_or_sqrts = ex2_sqrt | ex2_sqrts; + + assign ex2_sp = ex2_divs | ex2_sqrts; + + //---------------------------------------------------------------------- + + assign ex1_itag_din = (f_dcd_ex1_itag & {7{ex1_anydivsqrt}}) | (exx_itag_q & {7{(~ex1_anydivsqrt)}}); + + + tri_rlmreg_p #(.INIT(0), .WIDTH(9), .NEEDS_SRESET(0)) ex2_div_itag_lat( + .force_t(force_t), .d_mode(tiup), .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + //----------------- + .act(tiup), + //----------------- + .scout(ex2_itag_lat_scout), + .scin(ex2_itag_lat_scin), + //----------------- + .din({ + ex1_itag_din, + ex2_anydivsqrt, + ex3_anydivsqrt}), + //----------------- + .dout({ + exx_itag_q, + ex3_anydivsqrt, + ex4_anydivsqrt}) + ); + + + + assign ex1_fpscr_addr_din = (f_dcd_ex1_fpscr_addr & {6{ex1_anydivsqrt}}) | + (exx_fpscr_addr_q & {6{(~ex1_anydivsqrt)}}); + + assign exx_fpscr_din = (({f_scr_ex6_fpscr_ee_thr0, f_scr_ex6_fpscr_rm_thr0}) & {7{(ex6_anydivsqrt & exx_instr_tid_q[0])}}) | + (({f_scr_ex6_fpscr_ee_thr1, f_scr_ex6_fpscr_rm_thr1}) & {7{(ex6_anydivsqrt & exx_instr_tid_q[1])}}) | + ((exx_fpscr_q) & {7{(~ex6_anydivsqrt)}}); + + assign ex1_instr_frt_din = (f_dcd_ex1_instr_frt & {6{ex1_anydivsqrt}}) | + (exx_instr_frt_q & {6{(~ex1_anydivsqrt)}}); + + assign tid_init = {2{(ex1_anydivsqrt)}} & (~f_dcd_flush[0:1]); // new one can be starting in ex1 while ex6 finishing + assign tid_hold = {2{((~ex1_anydivsqrt) & (~ex6_divsqrt_done))}} & (~f_dcd_flush[0:1]); + assign tid_clear = ({2{(~ex1_anydivsqrt)}} & {2{ex6_divsqrt_done}}) | f_dcd_flush[0:1]; + + assign ex1_instr_tid_din[0:1] = (f_dcd_ex1_instr_tid[0:1] & tid_init) | (exx_instr_tid_q[0:1] & tid_hold) | (2'b00 & tid_clear); + + assign ex1_instr_tid_din[2:3] = 2'b00; + + assign ex1_cr_bf_din = (f_dcd_ex1_divsqrt_cr_bf & {5{ex1_anydivsqrt}}) | + (exx_cr_bf_q & {5{(~ex1_anydivsqrt)}}); + + + tri_rlmreg_p #(.INIT(0), .WIDTH(28), .NEEDS_SRESET(1)) ex2_div_fpscr_addr_cr_bf_lat( + .force_t(force_t), .d_mode(tiup), .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + //----------------- + .act(tiup), + //----------------- + .scout(ex2_fpscr_addr_lat_scout), + .scin(ex2_fpscr_addr_lat_scin), + //----------------- + .din({ ex1_fpscr_addr_din, + ex1_cr_bf_din, + ex1_instr_frt_din, + ex1_instr_tid_din, + exx_fpscr_din}), + //----------------- + .dout({ exx_fpscr_addr_q, + exx_cr_bf_q, + exx_instr_frt_q, + exx_instr_tid_q, + exx_fpscr_q}) + ); + + //---------------------------------------------------------------------- + + assign f_fmt_ex2_a_expo_div = (~f_fmt_ex2_a_expo_div_b); + assign f_fmt_ex2_b_expo_div = (~f_fmt_ex2_b_expo_div_b); + + assign exx_a_sign_d = (f_fmt_ex2_a_sign_div & ex2_anydivsqrt) | (exx_a_sign_q & (~ex2_anydivsqrt)); + + assign exx_a_biased_13exp_d = (f_fmt_ex2_a_expo_div & {13{ex2_anydivsqrt}}) | + (exx_a_biased_13exp_q & {13{(~ex2_anydivsqrt)}}); + + assign exx_a_fract_d = (f_fmt_ex2_a_frac_div & {52{ex2_anydivsqrt}}) | + (exx_a_fract_q & {52{(~ex2_anydivsqrt)}}); + + assign ex2_a_zero = f_fmt_ex2_a_zero; + assign ex2_a_SPunderflow_zero = (f_fmt_ex2_a_zero_dsq & ex2_sp) & (~f_fmt_ex2_a_zero); + + assign ex2_a_expo_max = f_fmt_ex2_a_expo_max; + assign ex2_a_SPoverflow_expo_max = (f_fmt_ex2_a_expo_max_dsq & ex2_sp) & (~ex2_a_expo_max); + + assign ex2_a_frac_zero = f_fmt_ex2_a_frac_zero; + + assign exx_a_zero_d = (ex2_a_zero & ex2_anydivsqrt) | (exx_a_zero_q & (~ex2_anydivsqrt)); + assign exx_a_SPunderflow_zero_d = (ex2_a_SPunderflow_zero & ex2_anydivsqrt) | (exx_a_SPunderflow_zero_q & (~ex2_anydivsqrt)); + + assign exx_a_expo_max_d = (ex2_a_expo_max & ex2_anydivsqrt) | (exx_a_expo_max_q & (~ex2_anydivsqrt)); + assign exx_a_SPoverflow_expo_max_d = (ex2_a_SPoverflow_expo_max & ex2_anydivsqrt) | (exx_a_SPoverflow_expo_max_q & (~ex2_anydivsqrt)); + + assign exx_a_frac_zero_d = (ex2_a_frac_zero & ex2_anydivsqrt) | (exx_a_frac_zero_q & (~ex2_anydivsqrt)); + + assign VE = exx_fpscr_q[0]; + assign OE = exx_fpscr_q[1]; + assign UE = exx_fpscr_q[2]; + assign ZE = exx_fpscr_q[3]; + assign XE = exx_fpscr_q[4]; + + assign spare_unused[0] = XE; + + //--------------------------------------------------------------------- + + tri_rlmreg_p #(.INIT(0), .WIDTH(71), .NEEDS_SRESET(0)) ex2_div_a_stage_lat( + .force_t(force_t), .d_mode(tiup), .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + //----------------- + .act(exx_running_act_q), + //----------------- + .scout(ex2_div_a_stage_lat_scout), + .scin(ex2_div_a_stage_lat_scin), + //----------------- + .din({ + exx_a_sign_d, + exx_a_biased_13exp_d, + exx_a_fract_d, + exx_a_zero_d, + exx_a_expo_max_d, + exx_a_frac_zero_d, + exx_a_SPunderflow_zero_d, + exx_a_SPoverflow_expo_max_d}), + + //----------------- + .dout({ + exx_a_sign_q, + exx_a_biased_13exp_q, + exx_a_fract_q, + exx_a_zero_q, + exx_a_expo_max_q, + exx_a_frac_zero_q, + exx_a_SPunderflow_zero_q, + exx_a_SPoverflow_expo_max_q}) + ); + + + + assign ex2_a_fract = f_fmt_ex2_a_frac_div[1:52]; + + assign exx_b_sign_d = (f_fmt_ex2_b_sign_div & ex2_anydivsqrt) | (exx_b_sign_q & (~ex2_anydivsqrt)); + + assign exx_b_biased_13exp_d = (f_fmt_ex2_b_expo_div & {13{ex2_anydivsqrt}}) | + (exx_b_biased_13exp_q & {13{(~ex2_anydivsqrt)}}); + + assign exx_b_fract_d = (f_fmt_ex2_b_frac_div & {52{ex2_anydivsqrt}}) | + (exx_b_fract_q & {52{(~ex2_anydivsqrt)}}); + + assign ex2_b_zero = f_fmt_ex2_b_zero; + assign ex2_b_SPunderflow_zero = (f_fmt_ex2_b_zero_dsq & ex2_sp) & (~f_fmt_ex2_b_zero); + assign ex2_b_expo_max = f_fmt_ex2_b_expo_max; + assign ex2_b_SPoverflow_expo_max = (f_fmt_ex2_b_expo_max_dsq & ex2_sp) & (~ex2_b_expo_max); + + assign ex2_b_frac_zero = f_fmt_ex2_b_frac_zero; + + assign exx_b_zero_d = (ex2_b_zero & ex2_anydivsqrt) | (exx_b_zero_q & (~ex2_anydivsqrt)); + assign exx_b_SPunderflow_zero_d = (ex2_b_SPunderflow_zero & ex2_anydivsqrt) | (exx_b_SPunderflow_zero_q & (~ex2_anydivsqrt)); + + assign exx_b_expo_max_d = (ex2_b_expo_max & ex2_anydivsqrt) | (exx_b_expo_max_q & (~ex2_anydivsqrt)); + assign exx_b_SPoverflow_expo_max_d = (ex2_b_SPoverflow_expo_max & ex2_anydivsqrt) | (exx_b_SPoverflow_expo_max_q & (~ex2_anydivsqrt)); + + assign exx_b_frac_zero_d = (ex2_b_frac_zero & ex2_anydivsqrt) | (exx_b_frac_zero_q & (~ex2_anydivsqrt)); + + //--------------------------------------------------------------------- + + tri_rlmreg_p #(.INIT(0), .WIDTH(71), .NEEDS_SRESET(0)) ex2_div_b_stage_lat( + .force_t(force_t), .d_mode(tiup), .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + //----------------- + .act(exx_running_act_q), + //----------------- + .scout(ex2_div_b_stage_lat_scout), + .scin(ex2_div_b_stage_lat_scin), + //----------------- + .din({ + exx_b_sign_d, + exx_b_biased_13exp_d, + exx_b_fract_d, + exx_b_zero_d, + exx_b_expo_max_d, + exx_b_frac_zero_d, + exx_b_SPunderflow_zero_d, + exx_b_SPoverflow_expo_max_d}), + //----------------- + .dout({ exx_b_sign_q, + exx_b_biased_13exp_q, + exx_b_fract_q, + exx_b_zero_q, + exx_b_expo_max_q, + exx_b_frac_zero_q, + exx_b_SPunderflow_zero_q, + exx_b_SPoverflow_expo_max_q}) + ); + + + assign ex2_b_fract = (f_fmt_ex2_b_frac_div[1:52]); + + //------------------------------------------------------------------------------ + // unbias the exponents + //------------------------------------------------------------------------------ + // bias is DP, so subtract 1023 + + assign exx_b_ubexp = exx_b_biased_13exp_q[1:13] + 13'b1110000000001; + + + tri_rlmreg_p #(.INIT(0), .WIDTH(52), .NEEDS_SRESET(0)) ex2_div_exp_lat( + .force_t(force_t), .d_mode(tiup), .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + //----------------- + .act(exx_running_act_q), + //----------------- + .scout(ex2_div_exp_lat_scout), + .scin(ex2_div_exp_lat_scin), + //----------------- + .din({ exx_b_ubexp, + exx_exp_addres_div_x0, + exx_exp_addres_sqrt_x0, + exy_exp_addres_div_x0_m1 + }), + //----------------- + .dout({ exy_b_ubexp, + exy_exp_addres_div_x0, + exy_exp_addres_sqrt_x0, + exz_exp_addres_div_x0_m1 + }) + ); + + //------------------------------------------------------------------------------ + // counter/state machine + + assign ex2_divsqrt_hole_v_b = (~f_dcd_ex2_divsqrt_hole_v); + + assign ex1_cycles_init = (ex1_div | ex1_divs | ex1_sqrt | ex1_sqrts) & (~n_flush); + assign ex1_cycles_hold = (ex2_divsqrt_zero | (ex2_divsqrt_done & ex2_divsqrt_hole_v_b)) & (~ex1_cycles_init) & (~n_flush); + assign ex1_cycles_decr = exx_divsqrt_running_q & (~ex1_cycles_hold) & (~ex1_cycles_init) & (~n_flush); + assign ex1_cycles_clear = n_flush; + + // + assign ex1_cycles_d = (ex1_op_cyc_count & {8{ex1_cycles_init}}) | + (ex2_cycles_q & {8{ex1_cycles_hold}}) | + (8'b00000000 & {8{ex1_cycles_clear}}) | + ((ex2_cycles_q - 8'b00000001) & {8{ex1_cycles_decr}}); + + assign ex2_divsqrt_zero = (ex2_cycles_q == 8'b00000000) ? 1'b1 : + 1'b0; + assign ex1_divsqrt_done = (ex2_cycles_q == 8'b00000010) ? 1'b1 : + 1'b0; + assign ex2_divsqrt_done = (ex2_cycles_q == 8'b00000001) ? 1'b1 : + 1'b0; + + assign ex2_divsqrt_done_din = ex2_divsqrt_done & (~ex2_divsqrt_hole_v_b) & (~n_flush); + + assign ex2_waiting_for_hole = (ex2_divsqrt_done & ex2_divsqrt_hole_v_b) & (~ex1_cycles_init) & (~n_flush); + + assign ex2_hangcounter_incr = ex2_waiting_for_hole & (~ex3_hangcounter_trigger); + assign ex2_hangcounter_clear = (ex2_divsqrt_done & (~ex2_divsqrt_hole_v_b)) | ex1_cycles_init | ex3_hangcounter_trigger | n_flush; + + assign ex3_hangcounter_trigger = (ex3_hangcounter_q == 8'b00100000) ? 1'b1 : + 1'b0; + + assign f_dsq_ex3_hangcounter_trigger = ex3_hangcounter_trigger; + + assign ex2_hangcounter_din = (8'b00000000 & {8{ex2_hangcounter_clear}}) | + ((ex3_hangcounter_q + 8'b00000001) & {8{ex2_hangcounter_incr}}); + assign ex1_divsqrt_running_d = ((ex1_div | ex1_divs | ex1_sqrt | ex1_sqrts) | exx_divsqrt_running_q) & (~(ex2_divsqrt_done_din | n_flush)); + + assign exx_single_precision_d = ((ex1_divs | ex1_sqrts) | (exx_single_precision_q & (~ex1_anydivsqrt))) & (~(n_flush)); + + assign exx_record_v_din = ((ex1_record_v & ex1_anydivsqrt) | (exx_record_v_q & (~ex1_anydivsqrt))) & (~(n_flush)); + + assign ex4_sp = exx_single_precision_q; + assign ex4_dp = (~exx_single_precision_q); + assign exx_sp = exx_single_precision_q; + assign exx_dp = (~exx_single_precision_q); + + assign exx_sqrt_d = ((ex1_sqrt | ex1_sqrts) | (exx_sqrt_q[0] & (~ex1_anydivsqrt))) & (~(n_flush)); + assign exx_div_d = ((ex1_div | ex1_divs) | (exx_div_q[0] & (~ex1_anydivsqrt))) & (~(n_flush)); + + + tri_rlmreg_p #(.INIT(0), .WIDTH(8), .NEEDS_SRESET(1)) ex3_div_hangcounter_lat( + .force_t(force_t), .d_mode(tiup), .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + //----------------- + .act(tiup), + //----------------- + .scout(ex3_div_hangcounter_lat_scout), + .scin(ex3_div_hangcounter_lat_scin), + //----------------- + .din({ex2_hangcounter_din}), + //----------------- + .dout({ex3_hangcounter_q}) + ); + + + tri_rlmreg_p #(.INIT(0), .WIDTH(19), .NEEDS_SRESET(1)) ex1_div_ctr_lat( + .force_t(force_t), .d_mode(tiup), .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + //----------------- + .act(tiup), + //----------------- + .scout(ex1_div_ctr_lat_scout), + .scin(ex1_div_ctr_lat_scin), + //----------------- + .din({ ex1_cycles_d, + ex1_divsqrt_running_d, + exx_single_precision_d, + exx_sqrt_d, + exx_sqrt_d, + exx_sqrt_d, + exx_sqrt_d, + exx_div_d, + exx_div_d, + exx_div_d, + exx_div_d, + exx_record_v_din}), + //----------------- + .dout({ ex2_cycles_q, + exx_divsqrt_running_q, + exx_single_precision_q, + exx_sqrt_q[0:3], + exx_div_q[0:3], + exx_record_v_q}) + ); + + //------------------------------------------------------------------------------ + // fraction path + //------------------------------------------------------------------------------ + //------------------------------------------------------------------- + // Initial 4-bit add and quotient select + //------------------------------------------------------------------- + + assign exx_denom_d = (exx_denom_q & {56{(exx_divsqrt_running_q & (~ex2_anydivsqrt))}}) | + ({{({1'b1, ex2_b_fract, 3'b000})}} & {56{(ex2_anydivsqrt)}}); + + //------------------------------------------------------------------------------------------------------------------------------------------------ + assign exx_PR_sum_shift = exx_PR_sum_final; + + assign ex2_PR_sum_sel0 = ex2_div_or_divs; // initialize div + assign ex2_PR_sum_sel1 = ex2_sqrt_or_sqrts & (~f_fmt_ex2_b_expo_div_b[13]); // initialize sqrt, even exponent + assign ex2_PR_sum_sel2 = ex2_sqrt_or_sqrts & f_fmt_ex2_b_expo_div_b[13]; // initialize sqrt, odd exponent + assign ex2_PR_sum_sel3 = (~ex2_anydivsqrt) & (~(ex2_divsqrt_done & ex2_divsqrt_hole_v_b)); + assign ex2_PR_sum_sel4 = ex2_divsqrt_done & ex2_divsqrt_hole_v_b; + + assign ex2_PR_sum_sel_late = ex2_PR_sum_sel3; + assign ex2_PR_sum_sel_early = ex2_PR_sum_sel0 | ex2_PR_sum_sel1 | ex2_PR_sum_sel2 | ex2_PR_sum_sel4; + + // div + // sqrt even exponent + assign exx_PR_sum_d_early = (({4'b0001, ex2_a_fract[1:52], 1'b0}) & {57{ex2_PR_sum_sel0}}) | + (({4'b0001, ex2_b_fract[1:52], 1'b0}) & {57{ex2_PR_sum_sel1}}) | + (({3'b001, ex2_b_fract[1:52], 2'b00}) & {57{ex2_PR_sum_sel2}}) | + (exx_PR_sum_q & {57{ex2_PR_sum_sel4}}); // sqrt odd exponent + // hold + + assign exx_PR_sum_d_late = exx_PR_sum_shift; + + assign exx_PR_sum_d = (exx_PR_sum_d_late & {57{ex2_PR_sum_sel_late}}) | + (exx_PR_sum_d_early & {57{ex2_PR_sum_sel_early}}); + + assign exx_PR_carry_shift = exx_PR_carry_final; + + assign ex2_PR_carry_sel0 = ex2_anydivsqrt; + assign ex2_PR_carry_sel1 = (~ex2_anydivsqrt) & (~(ex2_divsqrt_done & ex2_divsqrt_hole_v_b)); + assign ex2_PR_carry_sel2 = ex2_divsqrt_done & ex2_divsqrt_hole_v_b; // hold + + assign exx_PR_carry_d = ({57{1'b0}} & {57{ex2_PR_carry_sel0}}) | + (exx_PR_carry_shift & {57{ex2_PR_carry_sel1}}) | + (exx_PR_carry_q & {57{ex2_PR_carry_sel2}}); + + + tri_rlmreg_p #(.INIT(0), .WIDTH(114), .NEEDS_SRESET(0)) ex3_div_PR_sumcarry_lat( + .force_t(force_t), .d_mode(tiup), .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + //----------------- + .act(exx_running_act_q), + //----------------- + .scout(ex3_div_PR_sumcarry_lat_scout), + .scin(ex3_div_PR_sumcarry_lat_scin), + //----------------- + .din({exx_PR_sum_d, exx_PR_carry_d}), + //----------------- + .dout({exx_PR_sum_q, exx_PR_carry_q}) + ); + + + tri_rlmreg_p #(.INIT(0), .WIDTH(8), .NEEDS_SRESET(0)) ex3_div_PR_sum4carry4_lat( + .force_t(force_t), .d_mode(tiup), .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + //----------------- + .act(tiup), + //----------------- + .scout(ex3_div_PR_sum4carry4_lat_scout), + .scin(ex3_div_PR_sum4carry4_lat_scin), + //----------------- + .din({exx_PR_sum_d[0:3],exx_PR_carry_d[0:3]}), + //----------------- + .dout({exx_PR_sum4_q, exx_PR_carry4_q }) + ); + + + tri_rlmreg_p #(.INIT(0), .WIDTH(114), .NEEDS_SRESET(0)) ex3_div_Q_QM_lat( + .force_t(force_t), .d_mode(tiup), .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + //----------------- + .act(exx_running_act_q), + //----------------- + .scout(ex3_div_Q_QM_lat_scout), + .scin(ex3_div_Q_QM_lat_scin), + //----------------- + .din({exx_Q_d, exx_QM_d }), + //----------------- + .dout({exx_Q_q, exx_QM_q}) + ); + + + tri_rlmreg_p #(.INIT(0), .WIDTH(114), .NEEDS_SRESET(0)) ex3_div_bQ_QM_lat( + .force_t(force_t), .d_mode(tiup), .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + //----------------- + .act(exx_running_act_q), + //----------------- + .scout(ex3_div_bQ_QM_lat_scout), + .scin(ex3_div_bQ_QM_lat_scin), + //----------------- + .din({exx_bQ_d, exx_bQM_d }), + //----------------- + .dout({exx_bQ_q,exx_bQM_q }) + ); + + + tri_rlmreg_p #(.INIT(0), .WIDTH(168), .NEEDS_SRESET(0)) ex3_sqrt_bitmask_lat( + .force_t(force_t), .d_mode(tiup), .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + //----------------- + .act(exx_running_act_q), + //----------------- + .scout(ex3_sqrt_bitmask_lat_scout), + .scin(ex3_sqrt_bitmask_lat_scin), + //----------------- + .din({exx_sqrt_newbitmask_din, + exx_sqrt_Qbitmask_din, + exx_sqrt_QMbitmask_din }), + //----------------- + .dout({exx_sqrt_newbitmask_q, + exx_sqrt_Qbitmask_q, + exx_sqrt_QMbitmask_q }) + ); + + + tri_rlmreg_p #(.INIT(0), .WIDTH(56), .NEEDS_SRESET(0)) ex3_div_denom_lat( + .force_t(force_t), .d_mode(tiup), .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + //----------------- + .act(exx_running_act_q), + //----------------- + .scout(ex3_denom_lat_scout), + .scin(ex3_denom_lat_scin), + //----------------- + .din(exx_denom_d), + //----------------- + .dout(exx_denom_q) + ); + + //---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + + fu_divsqrt_add4 lev0_add4( + .x(exx_PR_sum4_q[0:3]), + .y(exx_PR_carry4_q[0:3]), + //------------------------------------------------------ + .s(exx_sum4) + ); + + assign exx_q_bit0_cin = exx_PR_sum_q[5] | exx_PR_carry_q[5]; + + fu_divsqrt_q_table lev0_div_q_table( + .x(exx_sum4[0:3]), + .cin(exx_q_bit0_cin), + //------------------------------------------------------ + .q(exx_q_bit0_prebuf) + ); + + fu_divsqrt_nq_table lev0_div_nq_table( + .x(exx_sum4[0:3]), + //------------------------------------------------------ + .nq(exx_nq_bit0_prebuf) + ); + + + assign exx_q_bit0_b = (~exx_q_bit0_prebuf); + assign exx_nq_bit0_b = (~exx_nq_bit0_prebuf); + + assign exx_q_bit0 = (~exx_q_bit0_b); + assign exx_nq_bit0 = (~exx_nq_bit0_b); + + //---------------------------------------------------------------------------------------------------------------------------------------------------- + + //------------------------------------------------------------------- + // on-the-fly quotient digit conversion logic for level 0 + //------------------------------------------------------------------- + // Qin=(Q & q) if q >= 0. Qin=(QM & 1) if q < 0 + + assign exx_Qin_lev0_sel0 = exx_q_bit0 | ((~exx_nq_bit0)); + assign exx_Qin_lev0_sel1 = exx_nq_bit0; + + assign exx_Qin_lev0[0:56] = (({exx_Q_q[1:56], exx_q_bit0}) & {57{exx_Qin_lev0_sel0}}) | + (({exx_QM_q[1:56], 1'b1}) & {57{exx_Qin_lev0_sel1}}); + + // QMin=(Q & 0) if q > 0. QMin=(QM & 0) if q < 0. QMin=(QM & 1) if q = 0 + assign exx_QMin_lev0_sel0 = exx_q_bit0; + assign exx_QMin_lev0_sel1 = exx_nq_bit0; + assign exx_QMin_lev0_sel2 = (~(exx_nq_bit0 | exx_q_bit0)); + + assign exx_QMin_lev0[0:56] = (({exx_Q_q[1:56], 1'b0}) & {57{exx_QMin_lev0_sel0}}) | + (({exx_QM_q[1:56], 1'b0}) & {57{exx_QMin_lev0_sel1}}) | + (({exx_QM_q[1:56], 1'b1}) & {57{exx_QMin_lev0_sel2}}); + + // massage Q and QM for use with square root + // sel_denom_pre1 = ~(((Q << 2) | 1) << 29-i); + // sel_denom_pre3 = (((QM << 2) | 3) << 29-i); + + assign exx_sqrtlev0_Q[0:55] = exx_bQ_q_t[0:55]; + assign exx_sqrtlev0_MQ[0:55] = exx_bQM_q_t[0:55]; + //------------------------------------------------------------------- + // Initial Denominator mux and 3:2 CSA + //------------------------------------------------------------------- + + assign exx_PR_sum_q_shifted = {exx_PR_sum_q[1:56], 1'b0}; + assign exx_PR_carry_q_shifted = {exx_PR_carry_q[1:56], 1'b0}; + + assign exx_lev0_selneg = exx_q_bit0 & (~exx_nq_bit0); + + assign exx_lev0_selD_b = (~(exx_nq_bit0 & exx_div_q[0])); + assign exx_lev0_selnD_b = (~(exx_q_bit0 & exx_div_q[0])); + assign exx_lev0_selD = (~exx_lev0_selD_b); + assign exx_lev0_selnD = (~exx_lev0_selnD_b); + + assign exx_lev0_selQ_b = (~(exx_q_bit0 & exx_sqrt_q[0])); + assign exx_lev0_selMQ_b = (~(exx_nq_bit0 & exx_sqrt_q[0])); + assign exx_lev0_selQ = (~exx_lev0_selQ_b); + assign exx_lev0_selMQ = (~exx_lev0_selMQ_b); + + assign exx_denomQ_lev0_nD_b = (~((~exx_denom_q) & {56{exx_lev0_selnD}})); + assign exx_denomQ_lev0_D_b = (~(exx_denom_q & {56{exx_lev0_selD}})); + assign exx_denomQ_lev0_Q_b = (~((~exx_sqrtlev0_Q) & {56{exx_lev0_selQ}})); + assign exx_denomQ_lev0_MQ_b = (~(exx_sqrtlev0_MQ & {56{exx_lev0_selMQ}})); + + assign exx_denomQ_lev0 = (~(exx_denomQ_lev0_nD_b & exx_denomQ_lev0_D_b & exx_denomQ_lev0_Q_b & exx_denomQ_lev0_MQ_b)); + + tri_xor2 #(.WIDTH(57)) DIVSQRT_XOR2_exx_lev0_div_csaout_sum(exx_lev0_csaoutsh_sum, + {exx_lev0_selneg, exx_denomQ_lev0}, + exx_lev0_divsqrt_csaout_xor); + + assign exx_lev0_csaout_carryout = (({exx_lev0_selneg, exx_denomQ_lev0}) & exx_PR_sum_q_shifted) | + (({exx_lev0_selneg, exx_denomQ_lev0}) & exx_PR_carry_q_shifted) | + (exx_PR_sum_q_shifted & exx_PR_carry_q_shifted); + + assign exx_lev0_csaoutsh_carry[0:56] = {exx_lev0_csaout_carryout[1:56], exx_lev0_selneg}; + + + tri_xor2 #(.WIDTH(57)) DIVSQRT_XOR2_exx_lev0_div_csaout_xor(exx_lev0_divsqrt_csaout_xor, + exx_PR_sum_q_shifted, + exx_PR_carry_q_shifted); + + tri_xor2 #(.WIDTH(57)) DIVSQRT_XOR2_exx_lev1_div_csaout_xor(exx_lev1_divsqrt_csaout_xor, + exx_PR_sum_q_shifted, + exx_PR_carry_q_shifted); + + tri_xor2 #(.WIDTH(57)) DIVSQRT_XOR2_exx_lev3_div_csaout_xor(exx_lev3_divsqrt_csaout_xor, + exx_PR_sum_q_shifted, + exx_PR_carry_q_shifted); + + + //------------------------------------------------------------------- + // Pick -d, 0, +d + //------------------------------------------------------------------- + // lev1: neg d, +q ======================================================== + assign exx_lev1_div_oper = ({1'b1, (~exx_denom_q)}); + assign exx_lev1_sqrt_oper = ({1'b1, (~exx_sqrtlev0_Q)}); + + tri_xor2 #(.WIDTH(57)) DIVSQRT_XOR2_exx_lev1_div_csaout_sum(exx_lev1_div_csaout_sum, + exx_lev1_div_oper, + exx_lev1_divsqrt_csaout_xor); + + tri_xor2 #(.WIDTH(57)) DIVSQRT_XOR2_exx_lev1_sqrt_csaout_sum(exx_lev1_sqrt_csaout_sum, + exx_lev1_sqrt_oper, + exx_lev1_divsqrt_csaout_xor); + + + assign exx_lev1_div_csaout_carryout = (exx_lev1_div_oper & exx_PR_sum_q_shifted) | (exx_lev1_div_oper & exx_PR_carry_q_shifted) | (exx_PR_sum_q_shifted & exx_PR_carry_q_shifted); + assign exx_lev1_sqrt_csaout_carryout = (exx_lev1_sqrt_oper & exx_PR_sum_q_shifted) | (exx_lev1_sqrt_oper & exx_PR_carry_q_shifted) | (exx_PR_sum_q_shifted & exx_PR_carry_q_shifted); + + assign exx_lev1_div_csaout_carry[0:56] = {exx_lev1_div_csaout_carryout[1:56], 1'b1}; + assign exx_lev1_sqrt_csaout_carry[0:56] = {exx_lev1_sqrt_csaout_carryout[1:56], 1'b1}; + + fu_divsqrt_add4 lev1_div_add4( + .x(exx_lev1_div_csaout_sum[0:3]), + .y(exx_lev1_div_csaout_carry[0:3]), + //------------------------------------------------------ + .s(exx_sum4_lev1_div) + ); + + fu_divsqrt_add4 lev1_sqrt_add4( + .x(exx_lev1_sqrt_csaout_sum[0:3]), + .y(exx_lev1_sqrt_csaout_carry[0:3]), + //------------------------------------------------------ + .s(exx_sum4_lev1_sqrt) + ); + + assign exx_q_bit1_cin_div = exx_lev1_div_csaout_sum[5] | exx_lev1_div_csaout_carry[5]; + assign exx_q_bit1_cin_sqrt = exx_lev1_sqrt_csaout_sum[5] | exx_lev1_sqrt_csaout_carry[5]; + + fu_divsqrt_q_table lev1_div_q_table( + .x(exx_sum4_lev1_div[0:3]), + .cin(exx_q_bit1_cin_div), + //------------------------------------------------------ + .q(exx_q_bit1_div) + ); + + fu_divsqrt_q_table lev1_sqrt_q_table( + .x(exx_sum4_lev1_sqrt[0:3]), + .cin(exx_q_bit1_cin_sqrt ), + //------------------------------------------------------ + .q(exx_q_bit1_sqrt) + ); + + fu_divsqrt_nq_table lev1_div_nq_table( + .x(exx_sum4_lev1_div[0:3]), + //------------------------------------------------------ + .nq(exx_nq_bit1_div ) + ); + + fu_divsqrt_nq_table lev1_sqrt_nq_table( + .x(exx_sum4_lev1_sqrt[0:3]), + //------------------------------------------------------ + .nq(exx_nq_bit1_sqrt ) + ); + + + + + assign exx_notqornq_bit1_sqrt = ((exx_sum4_lev1_sqrt == 4'b0000) & (~exx_q_bit1_cin_sqrt)) | + (exx_sum4_lev1_sqrt == 4'b1111) ; + + assign exx_notqornq_bit1_div = ((exx_sum4_lev1_div == 4'b0000) & (~exx_q_bit1_cin_div)) | + (exx_sum4_lev1_div == 4'b1111) ; + + + + assign exx_q_bit1 = (exx_q_bit1_div & exx_div_q[1]) | (exx_q_bit1_sqrt & exx_sqrt_q[1]); + assign exx_nq_bit1 = (exx_nq_bit1_div & exx_div_q[1]) | (exx_nq_bit1_sqrt & exx_sqrt_q[1]); + + // zero: lev2 =========================================================== + + assign exx_lev2_csaout_sum = exx_PR_sum_q_shifted ^ exx_PR_carry_q_shifted; + + assign exx_lev2_csaout_carryout = (exx_PR_sum_q_shifted & exx_PR_carry_q_shifted); + + assign exx_lev2_csaout_carry[0:56] = {exx_lev2_csaout_carryout[1:56], 1'b0}; + + fu_divsqrt_add4 lev2_add4( + .x(exx_lev2_csaout_sum[0:3]), + .y(exx_lev2_csaout_carry[0:3]), + //------------------------------------------------------ + .s(exx_sum4_lev2) + ); + + assign exx_q_bit2_cin = exx_lev2_csaout_sum[5] | exx_lev2_csaout_carry[5]; + + fu_divsqrt_q_table lev2_div_q_table( + .x(exx_sum4_lev2[0:3]), + .cin(exx_q_bit2_cin), + //------------------------------------------------------ + .q(exx_q_bit2) + ); + + fu_divsqrt_nq_table lev2_nq_table( + .x(exx_sum4_lev2[0:3]), + //------------------------------------------------------ + .nq(exx_nq_bit2 ) + ); + + + assign exx_notqornq_bit2 = ((exx_sum4_lev2 == 4'b0000) & (~exx_q_bit2_cin)) | + (exx_sum4_lev2 == 4'b1111) ; + + + + + // pos d, -q: lev3 ======================================================= + assign exx_lev3_div_oper = ({1'b0, exx_denom_q}); + assign exx_lev3_sqrt_oper = ({1'b0, exx_sqrtlev0_MQ}); + + tri_xor2 #(.WIDTH(57)) DIVSQRT_XOR2_exx_lev3_div_csaout_sum(exx_lev3_div_csaout_sum, + exx_lev3_div_oper, + exx_lev3_divsqrt_csaout_xor); + + tri_xor2 #(.WIDTH(57)) DIVSQRT_XOR2_exx_lev3_sqrt_csaout_sum(exx_lev3_sqrt_csaout_sum, + exx_lev3_sqrt_oper, + exx_lev3_divsqrt_csaout_xor); + + + + + + assign exx_lev3_div_csaout_carryout = (exx_lev3_div_oper & exx_PR_sum_q_shifted) | (exx_lev3_div_oper & exx_PR_carry_q_shifted) | (exx_PR_sum_q_shifted & exx_PR_carry_q_shifted); + assign exx_lev3_sqrt_csaout_carryout = (exx_lev3_sqrt_oper & exx_PR_sum_q_shifted) | (exx_lev3_sqrt_oper & exx_PR_carry_q_shifted) | (exx_PR_sum_q_shifted & exx_PR_carry_q_shifted); + + assign exx_lev3_div_csaout_carry[0:56] = {exx_lev3_div_csaout_carryout[1:56], 1'b0}; + assign exx_lev3_sqrt_csaout_carry[0:56] = {exx_lev3_sqrt_csaout_carryout[1:56], 1'b0}; + + fu_divsqrt_add4 lev3_div_add4( + .x(exx_lev3_div_csaout_sum[0:3]), + .y(exx_lev3_div_csaout_carry[0:3]), + //------------------------------------------------------ + .s(exx_sum4_lev3_div) + ); + + fu_divsqrt_add4 lev3_sqrt_add4( + .x(exx_lev3_sqrt_csaout_sum[0:3]), + .y(exx_lev3_sqrt_csaout_carry[0:3]), + //------------------------------------------------------ + .s(exx_sum4_lev3_sqrt) + ); + + assign exx_q_bit3_cin_div = exx_lev3_div_csaout_sum[5] | exx_lev3_div_csaout_carry[5]; + assign exx_q_bit3_cin_sqrt = exx_lev3_sqrt_csaout_sum[5] | exx_lev3_sqrt_csaout_carry[5]; + + fu_divsqrt_q_table lev3_div_q_table( + .x(exx_sum4_lev3_div[0:3]), + .cin(exx_q_bit3_cin_div), + //------------------------------------------------------ + .q(exx_q_bit3_div) + ); + + fu_divsqrt_q_table lev3_sqrt_q_table( + .x(exx_sum4_lev3_sqrt[0:3]), + .cin(exx_q_bit3_cin_sqrt), + //------------------------------------------------------ + .q(exx_q_bit3_sqrt) + ); + + fu_divsqrt_nq_table lev3_div_nq_table( + .x(exx_sum4_lev3_div[0:3]), + //------------------------------------------------------ + .nq(exx_nq_bit3_div ) + ); + + fu_divsqrt_nq_table lev3_sqrt_nq_table( + .x(exx_sum4_lev3_sqrt[0:3]), + //------------------------------------------------------ + .nq(exx_nq_bit3_sqrt ) + ); + + + assign exx_notqornq_bit3_sqrt = ((exx_sum4_lev3_sqrt == 4'b0000) & (~exx_q_bit3_cin_sqrt)) | + (exx_sum4_lev3_sqrt == 4'b1111) ; + assign exx_notqornq_bit3_div = ((exx_sum4_lev3_div == 4'b0000) & (~exx_q_bit3_cin_div)) | + (exx_sum4_lev3_div == 4'b1111) ; + + + + assign exx_q_bit3 = (exx_q_bit3_div & exx_div_q[2]) | (exx_q_bit3_sqrt & exx_sqrt_q[2]); + assign exx_nq_bit3 = (exx_nq_bit3_div & exx_div_q[2]) | (exx_nq_bit3_sqrt & exx_sqrt_q[2]); + + //------------------------------------------------------------------- + // Mux between these three to get the next quotient bit + //------------------------------------------------------------------- + assign exx_q_bit22_sel = {exx_q_bit0, exx_nq_bit0}; + + assign exx_q_bit22_sqrt = (exx_q_bit22_sel == 2'b10) ? exx_q_bit1_sqrt : + (exx_q_bit22_sel == 2'b00) ? exx_q_bit2 : + (exx_q_bit22_sel == 2'b01) ? exx_q_bit3_sqrt : + 1'b0; + + assign exx_nq_bit22_sqrt = (exx_q_bit22_sel == 2'b10) ? exx_nq_bit1_sqrt : + (exx_q_bit22_sel == 2'b00) ? exx_nq_bit2 : + (exx_q_bit22_sel == 2'b01) ? exx_nq_bit3_sqrt : + 1'b0; + + assign exx_notqornq_bit22_sqrt = (exx_q_bit22_sel == 2'b10) ? exx_notqornq_bit1_sqrt : + (exx_q_bit22_sel == 2'b00) ? exx_notqornq_bit2 : + (exx_q_bit22_sel == 2'b01) ? exx_notqornq_bit3_sqrt : + 1'b0; + + + + assign exx_q_bit22_div = (exx_q_bit22_sel == 2'b10) ? exx_q_bit1_div : + (exx_q_bit22_sel == 2'b00) ? exx_q_bit2 : + (exx_q_bit22_sel == 2'b01) ? exx_q_bit3_div : + 1'b0; + + assign exx_nq_bit22_div = (exx_q_bit22_sel == 2'b10) ? exx_nq_bit1_div : + (exx_q_bit22_sel == 2'b00) ? exx_nq_bit2 : + (exx_q_bit22_sel == 2'b01) ? exx_nq_bit3_div : + 1'b0; + + assign exx_notqornq_bit22_div = (exx_q_bit22_sel == 2'b10) ? exx_notqornq_bit1_div : + (exx_q_bit22_sel == 2'b00) ? exx_notqornq_bit2 : + (exx_q_bit22_sel == 2'b01) ? exx_notqornq_bit3_div : + 1'b0; + + + + assign exx_q_bit22 = (exx_q_bit22_div & exx_div_q[2]) | (exx_q_bit22_sqrt & exx_sqrt_q[2]); + assign exx_nq_bit22 = (exx_nq_bit22_div & exx_div_q[2]) | (exx_nq_bit22_sqrt & exx_sqrt_q[2]); + + // massage Q and QM for use with square root + // sel_denom_pre1 = ~(((Q << 2) | 1) << 29-i); + // sel_denom_pre3 = (((QM << 2) | 3) << 29-i); + // sel_denom_1 = ~(((Q << 2) | 1) << 28-i); + // sel_denom_3 = (((QM << 2) | 3) << 28-i); + + assign exx_bQin_lev0[0:55] = ((exx_bQ_q[0:55]) & {56{exx_Qin_lev0_sel0}}) | + ((exx_bQM_q[0:55]) & {56{exx_Qin_lev0_sel1}}); + + assign exx_bQMin_lev0[0:55] = ((exx_bQ_q[0:55]) & {56{exx_QMin_lev0_sel0}}) | + ((exx_bQM_q[0:55]) & {56{(~exx_QMin_lev0_sel0)}}); + + assign exx_bQin_lev0_t[0:55] = exx_bQin_lev0 | ({exx_sqrt_Qbitmask_q[1:55], 1'b0}); + assign exx_bQMin_lev0_t[0:55] = exx_bQMin_lev0 | ({exx_sqrt_QMbitmask_q[1:55], 1'b0}); + + assign exx_sqrtlev22_Q[0:55] = (exx_sqrt_Qmaskvec[0:55] & exx_sqrt_newbitmask_q[0:55]) | + ({56{1'b1}} & exx_sqrt_Qbitmask_q[0:55]) | + (exx_bQin_lev0_t[0:55] & (~(exx_sqrt_newbitmask_q[0:55] | exx_sqrt_QMbitmask_q[0:55]))); // need QM for 3 bit mask + + assign exx_sqrtlev22_MQ[0:55] = (exx_sqrt_QMmaskvec[0:55] & exx_sqrt_newbitmask_q[0:55]) | + ({56{1'b1}} & exx_sqrt_QMbitmask_q[0:55]) | + (exx_bQMin_lev0_t[0:55] & (~(exx_sqrt_newbitmask_q[0:55] | exx_sqrt_QMbitmask_q[0:55]))); + + assign exx_sqrt_Qmaskvec[0:55] = {56{wQ}}; + + assign exx_sqrt_QMmaskvec[0:55] = {56{wMQ}}; + + assign wQ = exx_Qin_lev0[56]; + assign wMQ = exx_QMin_lev0[56]; + + //------------------------------------------------------------------- + // Final Denominator mux and 3:2 CSA + //------------------------------------------------------------------- + // shift left by 1 again + assign exx_lev0_csaout_sum[0:56] = {exx_lev0_csaoutsh_sum[1:56], 1'b0}; + assign exx_lev0_csaout_carry[0:56] = {exx_lev0_csaoutsh_carry[1:56], 1'b0}; + + assign exx_lev22_selneg = exx_q_bit22; //exx_q_bit22 & (~exx_nq_bit22); + assign exx_lev22_selD = exx_nq_bit22_div; // and not exx_q_bit22_div and exx_div_q(0); + assign exx_lev22_selnD = exx_q_bit22_div; // and not exx_nq_bit22_div and exx_div_q(0); + + assign exx_lev22_selQ = exx_q_bit22_sqrt; // and not exx_nq_bit22_sqrt and exx_sqrt_q(0); + assign exx_lev22_selMQ = exx_nq_bit22_sqrt; // and not exx_q_bit22_sqrt and exx_sqrt_q(0); + + assign exx_denomQ_lev22_div = ((~exx_denom_q) & {56{exx_lev22_selnD}}) | + (exx_denom_q & {56{exx_lev22_selD}}); + + assign exx_denomQ_lev22_sqrt = ((~exx_sqrtlev22_Q) & {56{exx_lev22_selQ}}) | + (exx_sqrtlev22_MQ & {56{exx_lev22_selMQ}}); + + tri_xor2 #(.WIDTH(57)) DIVSQRT_XOR2_exx_lev22_csaout_sum_xor(exx_lev22_csaout_sum_xor, + exx_lev0_csaout_sum, + exx_lev0_csaout_carry ); + + tri_xor2 #(.WIDTH(57)) DIVSQRT_XOR2_exx_lev22_csaout_sum_div(exx_lev22_csaout_sum_div, + {exx_lev22_selneg, exx_denomQ_lev22_div}, + exx_lev22_csaout_sum_xor ); + + tri_xor2 #(.WIDTH(57)) DIVSQRT_XOR2_exx_lev22_csaout_sum_sqrt(exx_lev22_csaout_sum_sqrt, + {exx_lev22_selneg, exx_denomQ_lev22_sqrt}, + exx_lev22_csaout_sum_xor ); + + + assign exx_lev22_csaout_carryout_div = (({exx_lev22_selneg, exx_denomQ_lev22_div}) & exx_lev0_csaout_sum) | + (({exx_lev22_selneg, exx_denomQ_lev22_div}) & exx_lev0_csaout_carry) | + (exx_lev0_csaout_sum & exx_lev0_csaout_carry); + + assign exx_lev22_csaout_carryout_sqrt = (({exx_lev22_selneg, exx_denomQ_lev22_sqrt}) & exx_lev0_csaout_sum) | + (({exx_lev22_selneg, exx_denomQ_lev22_sqrt}) & exx_lev0_csaout_carry) | + (exx_lev0_csaout_sum & exx_lev0_csaout_carry); + + assign exx_lev22_csaout_carry_div[0:56] = {exx_lev22_csaout_carryout_div[1:56], exx_lev22_selneg}; + assign exx_lev22_csaout_carry_sqrt[0:56] = {exx_lev22_csaout_carryout_sqrt[1:56], exx_lev22_selneg}; + + assign exx_PR_sum_final = (exx_lev22_csaout_sum_div & {57{exx_div_q[0]}}) | + (exx_lev22_csaout_sum_sqrt & {57{exx_sqrt_q[0]}}); + assign exx_PR_carry_final = (exx_lev22_csaout_carry_div & {57{exx_div_q[0]}}) | + (exx_lev22_csaout_carry_sqrt & {57{exx_sqrt_q[0]}}); + + //------------------------------------------------------------------- + // on-the-fly quotient digit conversion logic + //------------------------------------------------------------------- + // Qin=(Q & q) if q >= 0. Qin=(QM & 1) if q < 0 + //timing: split out seperate sqrt Q latch? + + assign exx_Qin_lev1_sel0_div = (~exx_nq_bit22_div); // (exx_q_bit22_div | ((~exx_nq_bit22_div)));this combination will never be 11 + assign exx_Qin_lev1_sel1_div = exx_nq_bit22_div; + assign exx_Qin_lev1_sel0_sqrt = (~exx_nq_bit22_sqrt); // (exx_q_bit22_sqrt | ((~exx_nq_bit22_sqrt))); this combination will never be 11 + assign exx_Qin_lev1_sel1_sqrt = exx_nq_bit22_sqrt; + + assign exx_Qin_lev1_div[0:56] = (({exx_Qin_lev0[1:56], exx_q_bit22_div}) & {57{exx_Qin_lev1_sel0_div}}) | + (({exx_QMin_lev0[1:56], 1'b1}) & {57{exx_Qin_lev1_sel1_div}}); + assign exx_Qin_lev1_sqrt[0:56] = (({exx_Qin_lev0[1:56], exx_q_bit22_sqrt}) & {57{exx_Qin_lev1_sel0_sqrt}}) | + (({exx_QMin_lev0[1:56], 1'b1}) & {57{exx_Qin_lev1_sel1_sqrt}}); + + // QMin=(Q & 0) if q > 0. QMin=(QM & 0) if q < 0. QMin=(QM & 1) if q = 0 + assign exx_QMin_lev1_sel0_div = exx_q_bit22_div; + assign exx_QMin_lev1_sel1_div = exx_nq_bit22_div; + assign exx_QMin_lev1_sel2_div = exx_notqornq_bit22_div; //((~(exx_nq_bit22_div | exx_q_bit22_div))); + assign exx_QMin_lev1_sel0_sqrt = exx_q_bit22_sqrt; + assign exx_QMin_lev1_sel1_sqrt = exx_nq_bit22_sqrt; + assign exx_QMin_lev1_sel2_sqrt = exx_notqornq_bit22_sqrt; + + assign exx_QMin_lev1_div[0:56] = (({exx_Qin_lev0[1:56], 1'b0}) & {57{exx_QMin_lev1_sel0_div}}) | + (({exx_QMin_lev0[1:56], 1'b0}) & {57{exx_QMin_lev1_sel1_div}}) | + (({exx_QMin_lev0[1:56], 1'b1}) & {57{exx_QMin_lev1_sel2_div}}); + + assign exx_QMin_lev1_sqrt[0:56] = (({exx_Qin_lev0[1:56], 1'b0}) & {57{exx_QMin_lev1_sel0_sqrt}}) | + (({exx_QMin_lev0[1:56], 1'b0}) & {57{exx_QMin_lev1_sel1_sqrt}}) | + (({exx_QMin_lev0[1:56], 1'b1}) & {57{exx_QMin_lev1_sel2_sqrt}}); + + assign exx_Q_d = (exx_Qin_lev1_div & {57{(exx_div_q[0] & exx_divsqrt_running_q & (~ex3_divsqrt_done) & (~ex2_anydivsqrt) & (~(ex2_divsqrt_done & ex2_divsqrt_hole_v_b)))}}) | // normal running mode + (exx_Qin_lev1_sqrt & {57{(exx_sqrt_q[0] & exx_divsqrt_running_q & (~ex3_divsqrt_done) & (~ex2_anydivsqrt) & (~(ex2_divsqrt_done & ex2_divsqrt_hole_v_b)))}}) | // normal running mode + (exx_Q_q & {57{(ex2_divsqrt_done & ex2_divsqrt_hole_v_b)}}) | // hold + (exx_Q_q & {57{(ex3_divsqrt_done & (~ex2_anydivsqrt))}}) | // hold for rounding + ({57{1'b0}} & {57{ex2_anydivsqrt}}); // init + + + assign exx_QM_d = (exx_QMin_lev1_div & {57{(exx_div_q[0] & exx_divsqrt_running_q & (~ex3_divsqrt_done) & (~ex2_anydivsqrt) & (~(ex2_divsqrt_done & ex2_divsqrt_hole_v_b)))}}) | + (exx_QMin_lev1_sqrt & {57{(exx_sqrt_q[0] & exx_divsqrt_running_q & (~ex3_divsqrt_done) & (~ex2_anydivsqrt) & (~(ex2_divsqrt_done & ex2_divsqrt_hole_v_b)))}}) | + (exx_QM_q & {57{(ex2_divsqrt_done & ex2_divsqrt_hole_v_b)}}) | + (exx_QM_q & {57{(ex3_divsqrt_done & (~ex2_anydivsqrt))}}) | + ({57{1'b1}} & {57{ex2_anydivsqrt}}); // hold for rounding + + //------------------------------------------------------------------------------------------------------------- + // massage Q and QM for use with square root + // sel_denom_pre1 = ~(((Q << 2) | 1) << 29-i); + // sel_denom_pre3 = (((QM << 2) | 3) << 29-i); + + // sel_denom_1 = ~(((Q << 2) | 1) << 28-i); + // sel_denom_3 = ((QM << 2) | 3) << 28-i; + + // left justify Q, QM and append 01, 11 for use in square root + + + //--------------------------------------------------------------------------------------------------------------------------------------------------------------------- + + assign exx_bQ_q_t = exx_bQ_q[00:56] | ({exx_sqrt_Qbitmask_q[1:55], 2'b00}); + assign exx_bQM_q_t = exx_bQM_q[00:56] | ({exx_sqrt_QMbitmask_q[1:55], 2'b00}); + + + assign exx_bQin_lev1_sqrt[0:56] = (({exx_bQin_lev0[00:55], 1'b0}) & {57{exx_Qin_lev1_sel0_sqrt}}) | + (({exx_bQMin_lev0[00:55], 1'b0}) & {57{exx_Qin_lev1_sel1_sqrt}}); + + assign exx_bQMin_lev1_sqrt[0:56] = (({exx_bQin_lev0[00:55], 1'b0}) & {57{exx_QMin_lev1_sel0_sqrt}}) | + (({exx_bQMin_lev0[00:55], 1'b0}) & {57{exx_QMin_lev1_sel1_sqrt}}) | + (({exx_bQMin_lev0[00:55], 1'b0}) & {57{exx_QMin_lev1_sel2_sqrt}}); + + // lev0 + assign exx_bQ_d[00:56] = (({exx_sqrt_newbitmask_q[0:55], 1'b0}) & {57{exx_Qin_lev1_sqrt[55]}}) | + (({1'b0, exx_sqrt_newbitmask_q[0:55]}) & {57{exx_Qin_lev1_sqrt[56]}}) | + ((exx_bQin_lev1_sqrt) & {57{(exx_divsqrt_running_q & (~ex2_anydivsqrt))}}); // lev1 + + // lev0 + assign exx_bQM_d[00:56] = (({exx_sqrt_newbitmask_q[0:55], 1'b0}) & {57{exx_QMin_lev1_sqrt[55]}}) | + ({{({1'b0, exx_sqrt_newbitmask_q[0:55]})}} & {57{exx_QMin_lev1_sqrt[56]}}) | + ((exx_bQMin_lev1_sqrt) & {57{(exx_divsqrt_running_q & (~ex2_anydivsqrt))}}); // lev1 + + assign exx_sqrt_newbitmask_din[0:55] = (({2'b00, exx_sqrt_newbitmask_q[0:53]}) & {56{(exx_divsqrt_running_q & (~ex2_anydivsqrt))}}) | + ({{({1'b1, zeros[1:55]})}} & {56{ex2_anydivsqrt}}); + + assign exx_sqrt_Qbitmask_din[0:55] = (({2'b00, exx_sqrt_Qbitmask_q[0:53]}) & {56{(exx_divsqrt_running_q & (~ex2_anydivsqrt))}}) | + (({3'b001, zeros[3:55]}) & {56{ex2_anydivsqrt}}); + + assign exx_sqrt_QMbitmask_din[0:55] = (({2'b00, exx_sqrt_QMbitmask_q[0:53]}) & {56{(exx_divsqrt_running_q & (~ex2_anydivsqrt))}}) | + (({3'b011, zeros[3:55]}) & {56{ex2_anydivsqrt}}); + + // todo: probably don't need both newbitmask and Qbitmask + //------------------------------------------------------------------- + // + //------------------------------------------------------------------- + + //------------------------------------------------------------------- + // exponent logic + //------------------------------------------------------------------- + assign exx_exp_adj[1:13] = (13'b1111111111111 & {13{(ex4_norm_shl1_d)}}) | + (13'b0000000000000 & {13{(~(ex4_norm_shl1_d))}}); + + assign exx_exp_addres_div_x0 = (exx_a_biased_13exp_q) - (exy_b_ubexp[1:13]); + + assign exy_exp_addres_div_x0_m1 = exy_exp_addres_div_x0 - 13'b0000000000001; + assign exz_exp_addres_div_x0_adj = (exz_exp_addres_div_x0_m1 & {13{(ex4_norm_shl1_d)}}) | + (exy_exp_addres_div_x0 & {13{((~ex4_norm_shl1_d))}}); + + assign exx_exp_addres_sqrt_x0 = ({exy_b_ubexp[1], exy_b_ubexp[1:12]}) + 13'b0001111111111; + + assign exz_exp_addres_x0 = (exz_exp_addres_div_x0_adj & {13{exx_div_q[0]}}) | + (exy_exp_addres_sqrt_x0 & {13{exx_sqrt_q[0]}}); + + assign exx_exp_addres_ux = (exx_a_biased_13exp_q) - (exy_b_ubexp[1:13]) + (exx_exp_adj[1:13]) + exx_exp_ux_adj; + + assign exx_exp_addres_ox = (exx_a_biased_13exp_q) - (exy_b_ubexp[1:13]) + (exx_exp_adj[1:13]) + exx_exp_ox_adj; + + assign exx_exp_adj_p1[1:13] = (13'b0000000000000 & {13{(ex4_norm_shl1_d)}}) | + (13'b0000000000001 & {13{(~(ex4_norm_shl1_d))}}); + + assign exx_exp_addres_div_x0_p1 = (exx_a_biased_13exp_q) - (exy_b_ubexp[1:13]) + (exx_exp_adj_p1[1:13]); + + assign exx_exp_addres_sqrt_x0_p1 = ({exy_b_ubexp[1], exy_b_ubexp[1:12]}) + 13'b0010000000000; + + assign exx_exp_addres_x0_p1 = (exx_exp_addres_div_x0_p1 & {13{exx_div_q[0]}}) | + (exx_exp_addres_sqrt_x0_p1 & {13{exx_sqrt_q[0]}}); + + assign exx_exp_addres_ux_p1 = (exx_a_biased_13exp_q) - (exy_b_ubexp[1:13]) + (exx_exp_adj_p1[1:13]) + exx_exp_ux_adj; + + assign exx_exp_addres_ox_p1 = (exx_a_biased_13exp_q) - (exy_b_ubexp[1:13]) + (exx_exp_adj_p1[1:13]) + exx_exp_ox_adj; + + assign ueux = (underflow & (~special_force_zero)) & UE; + assign oeox = (overflow & (~exx_hard_spec_case)) & OE; + assign zezx = ex4_div_by_zero_zx & ZE; + assign vevx = (ex4_zero_div_zero | ex4_inf_div_inf | ex4_sqrt_neg | ex4_snan) & VE; + + assign not_ueux_or_oeox = ~(ueux | oeox); + + assign exx_exp_addres = (exz_exp_addres_x0 & {13{(~(ueux | oeox))}}) | + (exx_exp_addres_ux & {13{ueux}}) | + (exx_exp_addres_ox & {13{oeox}}); + + assign ex4_expresult_zero = (~|(exz_exp_addres_x0)); //or_reduce + + // + assign exx_exp_ux_adj_dp = 13'b0011000000000; // 1536 + assign exx_exp_ux_adj_sp = 13'b0000011000000; // 192 + assign exx_exp_ox_adj_dp = 13'b1101000000000; // -1536 + assign exx_exp_ox_adj_sp = 13'b1111101000000; // -192 + + assign exx_exp_ux_adj = (exx_exp_ux_adj_dp & {13{exx_dp}}) | + (exx_exp_ux_adj_sp & {13{exx_sp}}); + + assign exx_exp_ox_adj = (exx_exp_ox_adj_dp & {13{exx_dp}}) | + (exx_exp_ox_adj_sp & {13{exx_sp}}); + + // underflow + assign underflow_dp = exz_exp_addres_x0[0] | ex4_expresult_zero; + + // neg + // < -127+1023 0b000000xxxxxxx + assign underflow_sp = (exz_exp_addres_x0[0]) | (((~exz_exp_addres_x0[0]) & (~exz_exp_addres_x0[1]) & (~exz_exp_addres_x0[2]) & (~exz_exp_addres_x0[3]) & (~exz_exp_addres_x0[4]) & (~exz_exp_addres_x0[5])) & (exz_exp_addres_x0[6] | exz_exp_addres_x0[7] | exz_exp_addres_x0[8] | exz_exp_addres_x0[9] | exz_exp_addres_x0[10] | exz_exp_addres_x0[11] | exz_exp_addres_x0[12])) | (((~exz_exp_addres_x0[0]) & (~exz_exp_addres_x0[1]) & (~exz_exp_addres_x0[2])) & (((exz_exp_addres_x0[3] | exz_exp_addres_x0[4]) & (~exz_exp_addres_x0[5])) | ((exz_exp_addres_x0[5] | exz_exp_addres_x0[3]) & (~exz_exp_addres_x0[4])) | ((exz_exp_addres_x0[4] | exz_exp_addres_x0[5]) & (~exz_exp_addres_x0[3])))) | ((~exz_exp_addres_x0[0]) & (~exz_exp_addres_x0[1]) & (~exz_exp_addres_x0[2]) & exz_exp_addres_x0[3] & exz_exp_addres_x0[4] & exz_exp_addres_x0[5] & (~exz_exp_addres_x0[6]) & (~exz_exp_addres_x0[7]) & (~exz_exp_addres_x0[8]) & (~exz_exp_addres_x0[9]) & (~exz_exp_addres_x0[10]) & (~exz_exp_addres_x0[11]) & (~exz_exp_addres_x0[12])); // < -127+1023 0b000xxxXXXXXXX + // -127+1023 0b0001110000000 + + assign underflow_denorm_dp = (denorm_sticky | exx_divsqrt_fract_q[53]); // guard bit also + assign underflow_denorm_sp = (denorm_sticky_sp | guard_dnr_sp | round_dnr_sp); + + assign underflow_denorm = (underflow_denorm_dp & exx_dp) | (underflow_denorm_sp & exx_sp); + + assign underflow_fi = (underflow & (~ex4_denormalizing_result_done)) | (underflow_denorm & ex4_denormalizing_result_done); + + // overflow + assign sp_overflow_brink_x47E = ((~exz_exp_addres_x0[0]) & (~exz_exp_addres_x0[1]) & exz_exp_addres_x0[2] & + (~exz_exp_addres_x0[3]) & (~exz_exp_addres_x0[4]) & (~exz_exp_addres_x0[5]) & + exz_exp_addres_x0[6] & exz_exp_addres_x0[7] & exz_exp_addres_x0[8] & exz_exp_addres_x0[9] & exz_exp_addres_x0[10] & exz_exp_addres_x0[11] & (~exz_exp_addres_x0[12])); + // 0b0010001111110 128+1023-1 + + assign ex4_incexp_to_sp_overflow = ex4_divsqrt_fract_rounded[0] & sp_overflow_brink_x47E & exx_sp; // rounded up past the implicit bit (which is bit 1 here) and into sp overflow + + assign dp_overflow_brink_x7FE = ((~exz_exp_addres_x0[0]) & (~exz_exp_addres_x0[1]) & + exz_exp_addres_x0[2] & exz_exp_addres_x0[3] & exz_exp_addres_x0[4] & exz_exp_addres_x0[5] & exz_exp_addres_x0[6] & exz_exp_addres_x0[7] & exz_exp_addres_x0[8] & exz_exp_addres_x0[9] & exz_exp_addres_x0[10] & exz_exp_addres_x0[11] & (~exz_exp_addres_x0[12])); // 0b0011111111110 1024+1023-1 + + assign ex4_incexp_to_dp_overflow = ex4_divsqrt_fract_rounded[0] & dp_overflow_brink_x7FE & exx_dp; + + assign ex4_incexp_to_overflow = ex4_incexp_to_sp_overflow | ex4_incexp_to_dp_overflow; + + + assign overflow_dp = ex4_incexp_to_dp_overflow | + (((~exz_exp_addres_x0[0]) & exz_exp_addres_x0[1]) | // 0b01XXXXXXXXXXX > 1024+1023 + ((~exz_exp_addres_x0[0]) & (~exz_exp_addres_x0[1]) & + exz_exp_addres_x0[2] & exz_exp_addres_x0[3] & exz_exp_addres_x0[4] & exz_exp_addres_x0[5] & exz_exp_addres_x0[6] & exz_exp_addres_x0[7] & exz_exp_addres_x0[8] & exz_exp_addres_x0[9] & exz_exp_addres_x0[10] & exz_exp_addres_x0[11] & exz_exp_addres_x0[12])); // 0b0011111111111 1024+1023 + + + assign overflow_sp = ex4_incexp_to_sp_overflow | + ((((~exz_exp_addres_x0[0]) & (~exz_exp_addres_x0[1]) & exz_exp_addres_x0[2]) & + (exz_exp_addres_x0[3] | exz_exp_addres_x0[4] | exz_exp_addres_x0[5])) | // 0b001xxxXXXXXXX > 128+1023 + (((~exz_exp_addres_x0[0]) & exz_exp_addres_x0[1])) | // 0b01xxxxXXXXXXX > 128+1023 + ((~exz_exp_addres_x0[0]) & (~exz_exp_addres_x0[1]) & exz_exp_addres_x0[2] & (~exz_exp_addres_x0[3]) & (~exz_exp_addres_x0[4]) & (~exz_exp_addres_x0[5]) & exz_exp_addres_x0[6] & exz_exp_addres_x0[7] & exz_exp_addres_x0[8] & exz_exp_addres_x0[9] & exz_exp_addres_x0[10] & exz_exp_addres_x0[11] & exz_exp_addres_x0[12])); + // 0b0010001111111 128+1023 + + + assign overflow = (overflow_sp & exx_sp) | (overflow_dp & exx_dp); + + assign underflow = (underflow_sp & exx_sp) | (underflow_dp & exx_dp); + + //------------------------------------------------------------------- + // result staging latch + //------------------------------------------------------------------- + assign ex3_divsqrt_done_din = ex3_divsqrt_done & (~n_flush); + assign ex4_divsqrt_done_din = ex4_divsqrt_done & (~n_flush); + assign ex5_divsqrt_done_din = ex5_divsqrt_done & (~n_flush); + + + tri_rlmreg_p #(.INIT(0), .WIDTH(4), .NEEDS_SRESET(0)) ex4_div_done_lat( + .force_t(force_t), .d_mode(tiup), .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + //----------------- + .act(tiup), + //----------------- + .scout(ex5_div_done_lat_scout), + .scin(ex5_div_done_lat_scin), + //----------------- + .din({ ex2_divsqrt_done_din, + ex3_divsqrt_done_din, + ex4_divsqrt_done_din, + ex5_divsqrt_done_din}), + //----------------- + .dout({ ex3_divsqrt_done, + ex4_divsqrt_done_q, + ex5_divsqrt_done, + ex6_divsqrt_done}) + ); + + //------------------------------------------------------------------------------------------------------------------------------------ + // final fixup stages: normalize, round, final staging + + // generate the remainder + assign ex3_divsqrt_remainder[00:56] = exx_PR_sum_q[0:56] + exx_PR_carry_q[0:56]; + + //----------------------------------------------------------------------- + assign ex4_divsqrt_remainder[00:56] = exx_divsqrt_fract_q[00:56]; + + assign ex4_rem_neg_buf[00:14] = {15{ex4_rem_neg[0]}}; + assign ex4_rem_neg_buf[15:28] = {14{ex4_rem_neg[1]}}; + assign ex4_rem_neg_buf[29:42] = {14{ex4_rem_neg[2]}}; + assign ex4_rem_neg_buf[43:56] = {14{ex4_rem_neg[3]}}; + + assign ex4_rem_neg_buf_b[00:14] = {15{ex4_rem_neg_b[0]}}; + assign ex4_rem_neg_buf_b[15:28] = {14{ex4_rem_neg_b[1]}}; + assign ex4_rem_neg_buf_b[29:42] = {14{ex4_rem_neg_b[2]}}; + assign ex4_rem_neg_buf_b[43:56] = {14{ex4_rem_neg_b[3]}}; + + + //assign ex4_rem_neg = ex4_divsqrt_remainder[00]; + assign ex4_rem_nonzero = |(ex4_divsqrt_remainder[00:56]); // or_reduce + assign ex4_rem_nonzero_fi = (ex4_rem_nonzero | ex4_sp_inexact_roundbits) & (~ex4_denormalizing_result_done); + + assign ex4_divsqrt_fract_preround_prenorm[00:56] = (exx_Q_q[00:56] & ex4_rem_neg_buf_b ) | + (exx_QM_q[00:56] & ex4_rem_neg_buf ); + + assign ex4_norm_shl1_test = (((~ex4_divsqrt_fract_preround_prenorm[00])) & exx_dp) | (((~ex4_divsqrt_fract_preround_prenorm[28])) & exx_sp); // normalize + + assign ex3_norm_shl1_dp = (exx_Q_d[0] & (~ex3_divsqrt_remainder[0])) | (exx_QM_d[0] & ex3_divsqrt_remainder[0]); + assign ex3_norm_shl1_sp = (exx_Q_d[28] & (~ex3_divsqrt_remainder[0])) | (exx_QM_d[28] & ex3_divsqrt_remainder[0]); + + assign ex3_norm_shl1 = (~((ex3_norm_shl1_dp & exx_dp) | (ex3_norm_shl1_sp & exx_sp))); + + assign ex4_norm_shl1_d = ((ex4_norm_shl1 & ex4_divsqrt_done_q) | ex4_norm_shl1_q) & (~(n_flush | ex2_anydivsqrt | ex6_divsqrt_done)); + + assign ex4_divsqrt_fract_preround[00:56] = (ex4_divsqrt_fract_preround_prenorm[00:56] & {57{(~ex4_norm_shl1)}}) | + ({ex4_divsqrt_fract_preround_prenorm[01:56], 1'b0} & {57{ex4_norm_shl1}}); + + assign ex4_divsqrt_fract_p0_dp = {1'b0, ex4_divsqrt_fract_preround[00:52]}; + assign ex4_divsqrt_fract_p1_dp = ({1'b0, ex4_divsqrt_fract_preround[00:52]}) + ({{53{1'b0}}, 1'b1}); + + assign ex4_divsqrt_fract_p0_sp = {1'b0, ex4_divsqrt_fract_preround[28:51], {29{1'b0}}}; + assign ex4_divsqrt_fract_p1_sp = ({1'b0, ex4_divsqrt_fract_preround[28:51], {29{1'b0}}}) + + ({{24{1'b0}}, 1'b1, {29{1'b0}}}); + + assign HW165073_bits = (ex4_divsqrt_fract_preround_prenorm[52:56] == 5'b10000) ? 1'b1 : + 1'b0; + + assign HW165073_hit = HW165073_bits & exx_sp & ex4_divsqrt_done & ex4_norm_shl1; + assign spare_unused[1] = HW165073_hit; + assign ex4_sp_inexact_roundbits = |(ex4_divsqrt_fract_preround[52:56]) & ex4_sp; // or_reduce + + assign ex4_divsqrt_fract_p0 = (ex4_divsqrt_fract_p0_sp & {54{exx_sp}}) | + (ex4_divsqrt_fract_p0_dp & {54{exx_dp}}); + assign ex4_divsqrt_fract_p1 = (ex4_divsqrt_fract_p1_sp & {54{exx_sp}}) | + (ex4_divsqrt_fract_p1_dp & {54{exx_dp}}); + + assign sign = ex4_divsqrt_sign; //exx_divsqrt_sign_d; + + assign lsb = (ex4_divsqrt_fract_preround[52] & ex4_dp) | (ex4_divsqrt_fract_preround[51] & ex4_sp); + + assign guard = (ex4_divsqrt_fract_preround[53] & ex4_dp) | (ex4_divsqrt_fract_preround[52] & ex4_sp); + + assign round = sticky | ((ex4_divsqrt_fract_preround[54] & ex4_dp) | (ex4_divsqrt_fract_preround[53] & ex4_sp)); + + assign sticky = ex4_rem_nonzero; + + assign sticky_w_underflow = ex4_rem_nonzero | (underflow & (~exx_hard_spec_case) & (~UE)); + + + assign RNEmode = (~exx_fpscr_q[5]) & (~exx_fpscr_q[6]); // 00 + assign RTZmode = (~exx_fpscr_q[5]) & exx_fpscr_q[6]; // 01 + assign RPImode = exx_fpscr_q[5] & (~exx_fpscr_q[6]); // 10 + assign RNImode = exx_fpscr_q[5] & exx_fpscr_q[6]; // 11 + + assign ex4_round_up = ((guard & (lsb | round)) & RNEmode) | ((1'b0) & RTZmode) | (((guard | round) & (~sign)) & RPImode) | (((guard | round) & sign) & RNImode); // round to nearest mode + + assign ex4_round_up_underflow = (((sticky_w_underflow) & (~sign)) & RPImode) | (((sticky_w_underflow) & sign) & RNImode); + + //timing todo: don't need this whole vector + assign ex4_divsqrt_fract_rounded = (ex4_divsqrt_fract_p0 & {54{(~ex4_round_up)}}) | + (ex4_divsqrt_fract_p1 & {54{ex4_round_up}}); + + assign ex4_roundup_incexp = ex4_divsqrt_fract_rounded[0] & (~ex4_start_a_denorm_result) & (~exx_hard_spec_case) & (~ex4_force); // rounded up past the implicit bit (which is bit 1 here) + + assign ex4_x_roundup_incexp = ex4_dnr_roundup_incexp | ex4_roundup_incexp; + + + //----------------------------------------------------------------------- + // Denormal result handling + + // exx_exp_addres <= std_ulogic_vector(unsigned((exx_a_biased_13exp_q) - + // (exx_b_ubexp(1) & exx_b_ubexp(1) & exx_b_ubexp(1 to 11)) + + // (exx_exp_adj(1) & exx_exp_adj(1) & exx_exp_adj(1 to 11)))); + // underflow + // underflow <= exx_exp_addres(0); + // ex4_divsqrt_denorm_hold + + // exp_gt_cap <= (exx_exp_addres(0 to 12) < "1111111001011"); -- < -53 + // result is too small to denormalize = exp_gt_cap + + assign denorm_exp_addres = (({exz_exp_addres_x0[0], exz_exp_addres_x0[0:12]})) + (14'b00000000110101); + assign denorm_exp_addres_sp = (({exz_exp_addres_x0[0], exz_exp_addres_x0[0:12]})) + (14'b11110010011001); // -(896-25)=-871 + //denorm_exp_addres_sp_lsb <= std_ulogic_vector(((exx_exp_addres_x0(0) & exx_exp_addres_x0(0 to 12))) + ("11110010010111")); -- -(896-23)=-873 + + // denormal result shiftoff zero case + assign denorm_res_shiftoff_exp = (denorm_exp_addres[0:12] == 13'b0000000000000) ? 1'b1 : // 0 or 1: implicit bit shifted to Guard or Round position + 1'b0; + assign denorm_res_shiftoff_din = ((denorm_res_shiftoff_exp & ex4_start_denorm_result) | denorm_res_shiftoff_q) & (~ex2_anydivsqrt); + + assign exp_gt_cap = (denorm_exp_addres[0] & ex4_dp) | (denorm_exp_addres_sp[0] & ex4_sp); + + assign ex4_denorm_result_det = exx_dp & (exz_exp_addres_x0[0] | ex4_expresult_zero) & (~exp_gt_cap); + assign ex4_sp_denorm_result_det = exx_sp & ex4_exp_le_896 & (~exp_gt_cap); // if the exponent is in the range [871 to 896] [0x367 to 0x380] 0x369 puts the lsb one to the left of the implicit bit + + assign ex4_exp_le_896 = +((~exz_exp_addres_x0[0]) & (~exz_exp_addres_x0[1]) & +(~exz_exp_addres_x0[2]) & exz_exp_addres_x0[3] & +exz_exp_addres_x0[4] & exz_exp_addres_x0[5] & +(~|(exz_exp_addres_x0[6:12]))) | +((~|(exz_exp_addres_x0[0:2])) & +((~(exz_exp_addres_x0[3] & exz_exp_addres_x0[4] & exz_exp_addres_x0[5])) & (exz_exp_addres_x0[3] | exz_exp_addres_x0[4] | exz_exp_addres_x0[5]))); // =0b0001110000000 + // less than or equal to 0b0001110000000 + + assign exp_eq_369 = (exz_exp_addres_x0[0:12] == 13'b0001101101001) ? 1'b1 : + 1'b0; + assign exp_eq_368 = (exz_exp_addres_x0[0:12] == 13'b0001101101000) ? 1'b1 : + 1'b0; + assign exp_eq_367 = (exz_exp_addres_x0[0:12] == 13'b0001101100111) ? 1'b1 : + 1'b0; + assign exp_eq_367to9 = exp_eq_367 | exp_eq_368 | exp_eq_369; + assign exp_eq_380 = (exz_exp_addres_x0[0:12] == 13'b0001110000000) ? 1'b1 : + 1'b0; + + assign ex4_start_denorm_result = ((ex4_denorm_result_det & (~UE)) & ex4_divsqrt_done_q & (~exx_hard_spec_case)) & (~n_flush); + assign ex4_start_sp_denorm_result = ((ex4_sp_denorm_result_det & (~UE)) & ex4_divsqrt_done_q & (~exx_hard_spec_case)) & (~n_flush); + assign ex4_start_a_denorm_result = (((ex4_sp_denorm_result_det | ex4_denorm_result_det) & (~UE)) & ex4_divsqrt_done_q & (~exx_hard_spec_case)) & (~n_flush); + + assign ex4_denormalizing_result = |(denorm_count_q); // or_reduce + + assign ex4_denormalizing_result_shifting = (denorm_count_q == 6'b000010) ? 1'b1 : + 1'b0; + assign ex4_denormalizing_result_rounding = (denorm_count_q == 6'b000001) ? 1'b1 : + 1'b0; + assign ex4_denormalizing_result_done = (denorm_count_q == 6'b000001) ? 1'b1 : + 1'b0; + assign ex4_divsqrt_denorm_hold = ex4_denormalizing_result; + + assign ex4_denormalizing_result_done_din = ex4_denormalizing_result_done & (~f_dcd_axucr0_deno); + + assign denorm_sticky_din = ((ex4_denormalizing_result & |(ex4_divsqrt_fract_shifted_00to48[54:119])) | + denorm_sticky_q | (ex4_rem_nonzero & ex4_start_denorm_result)) & (~ex2_anydivsqrt); + + assign denorm_sticky_sp_din = ((ex4_denormalizing_result & |(ex4_divsqrt_fract_stickymask[0:56])) | + denorm_sticky_sp_q | (ex4_rem_nonzero & ex4_start_sp_denorm_result)) & (~ex2_anydivsqrt); + + assign denorm_sticky = denorm_sticky_q; + assign denorm_sticky_sp = denorm_sticky_sp_q; + + assign denorm_count_start = 6'b000010; + + assign denorm_shift_amt_din = (((~exz_exp_addres_x0[7:12]) + (6'b000010))); + assign sp_denorm_shift_amt_din = (((~exz_exp_addres_x0[7:12]) + (6'b000100))); // exp is in the range [871 to 896] + + assign denorm_shift_amt = denorm_shift_amt_q; + assign sp_denorm_shift_amt = sp_denorm_shift_amt_q; + + assign denorm_count_din = ((denorm_count_start) & {6{ex4_start_a_denorm_result}}) | + (((denorm_count_q) - 6'b000001) & {6{ex4_denormalizing_result}}) | + (6'b000000 & {6{ex4_denormalizing_result_done}}); + //-------------------------------------------------------------------------------------------------------------------------------- + // shift the fraction + assign ex4_divsqrt_fract_cur[00:56] = exx_divsqrt_fract_q[00:56]; + + // lev1 + assign dn_lv1sh00 = (~denorm_shift_amt[4]) & (~denorm_shift_amt[5]); //00 + assign dn_lv1sh01 = (~denorm_shift_amt[4]) & denorm_shift_amt[5]; //01 + assign dn_lv1sh10 = denorm_shift_amt[4] & (~denorm_shift_amt[5]); //10 + assign dn_lv1sh11 = denorm_shift_amt[4] & denorm_shift_amt[5]; //11 + + assign ex4_divsqrt_fract_shifted_00to03[00:59] = (({ex4_divsqrt_fract_cur[00:56], 3'b000}) & {60{dn_lv1sh00}}) | + (({1'b0, ex4_divsqrt_fract_cur[00:56], 2'b00}) & {60{dn_lv1sh01}}) | + (({2'b00, ex4_divsqrt_fract_cur[00:56], 1'b0}) & {60{dn_lv1sh10}}) | + (({3'b000, ex4_divsqrt_fract_cur[00:56]}) & {60{dn_lv1sh11}}); + // lev2 + assign dn_lv2sh00 = (~denorm_shift_amt[2]) & (~denorm_shift_amt[3]); //00 + assign dn_lv2sh01 = (~denorm_shift_amt[2]) & denorm_shift_amt[3]; //01 + assign dn_lv2sh10 = denorm_shift_amt[2] & (~denorm_shift_amt[3]); //10 + assign dn_lv2sh11 = denorm_shift_amt[2] & denorm_shift_amt[3]; //11 + + assign ex4_divsqrt_fract_shifted_00to12[00:71] = (({ex4_divsqrt_fract_shifted_00to03[00:59], 12'b000000000000}) & {72{dn_lv2sh00}}) | +(({4'b0000, ex4_divsqrt_fract_shifted_00to03[00:59], 8'b00000000}) & {72{dn_lv2sh01}}) | +(({8'b00000000, ex4_divsqrt_fract_shifted_00to03[00:59], 4'b0000}) & {72{dn_lv2sh10}}) | +(({12'b000000000000, ex4_divsqrt_fract_shifted_00to03[00:59]}) & {72{dn_lv2sh11}}); + // lev3 + assign dn_lv3sh00 = (~denorm_shift_amt[0]) & (~denorm_shift_amt[1]); //00 + assign dn_lv3sh01 = (~denorm_shift_amt[0]) & denorm_shift_amt[1]; //01 + assign dn_lv3sh10 = denorm_shift_amt[0] & (~denorm_shift_amt[1]); //10 + assign dn_lv3sh11 = denorm_shift_amt[0] & denorm_shift_amt[1]; //11 + + assign ex4_divsqrt_fract_shifted_00to48[00:119] = (({ex4_divsqrt_fract_shifted_00to12[00:71], {48{1'b0}}}) & {120{dn_lv3sh00}}) | + ({{16{1'b0}}, ({ex4_divsqrt_fract_shifted_00to12[00:71], {32{1'b0}}})} & {120{dn_lv3sh01}}) | + ({{32{1'b0}}, ({ex4_divsqrt_fract_shifted_00to12[00:71], {16{1'b0}}})} & {120{dn_lv3sh10}}) | + ({{48{1'b0}}, (ex4_divsqrt_fract_shifted_00to12[00:71])} & {120{dn_lv3sh11}}); + + assign ex4_divsqrt_fract_shifted_dp[00:56] = ex4_divsqrt_fract_shifted_00to48[00:56]; + //-------------------------------------------------------------------------------------------------------------------------------- + //-------------------------------------------------------------------------------------------------------------------------------- + // shift the sp denorm mask + assign ex4_spdenorm_mask[00:56] = {ones[0:27], zeros[28:56]}; + assign ex4_spdenorm_mask_lsb[00:56] = {zeros[0:24], 1'b1, zeros[26:56]}; + assign ex4_spdenorm_mask_guard[00:56] = {zeros[0:25], 1'b1, zeros[27:56]}; + assign ex4_spdenorm_mask_round[00:56] = {zeros[0:26], 1'b1, zeros[28:56]}; + + // todo: get rid of the cruft below + + // lev1 + assign dnsp_lv1sh00 = (~sp_denorm_shift_amt[4]) & (~sp_denorm_shift_amt[5]); //00 + assign dnsp_lv1sh01 = (~sp_denorm_shift_amt[4]) & sp_denorm_shift_amt[5]; //01 + assign dnsp_lv1sh10 = sp_denorm_shift_amt[4] & (~sp_denorm_shift_amt[5]); //10 + assign dnsp_lv1sh11 = sp_denorm_shift_amt[4] & sp_denorm_shift_amt[5]; //11 + + assign ex4_spdenorm_mask_shifted_00to03[00:59] = (({ex4_spdenorm_mask[00:56], 3'b000}) & {60{dnsp_lv1sh00}}) | + (({ex4_spdenorm_mask[01:56], 4'b0000}) & {60{dnsp_lv1sh01}}) | + (({ex4_spdenorm_mask[02:56], 5'b00000}) & {60{dnsp_lv1sh10}}) | + (({ex4_spdenorm_mask[03:56], 6'b000000}) & {60{dnsp_lv1sh11}}); + + assign ex4_spdenorm_mask_lsb_shifted_00to03[00:59] = (({ex4_spdenorm_mask_lsb[00:56], 3'b000}) & {60{dnsp_lv1sh00}}) | + (({ex4_spdenorm_mask_lsb[01:56], 4'b0000}) & {60{dnsp_lv1sh01}}) | + (({ex4_spdenorm_mask_lsb[02:56], 5'b00000}) & {60{dnsp_lv1sh10}}) | + (({ex4_spdenorm_mask_lsb[03:56], 6'b000000}) & {60{dnsp_lv1sh11}}); + + assign ex4_spdenorm_mask_guard_shifted_00to03[00:59] = (({ex4_spdenorm_mask_guard[00:56], 3'b000}) & {60{dnsp_lv1sh00}}) | + (({ex4_spdenorm_mask_guard[01:56], 4'b0000}) & {60{dnsp_lv1sh01}}) | + (({ex4_spdenorm_mask_guard[02:56], 5'b00000}) & {60{dnsp_lv1sh10}}) | + (({ex4_spdenorm_mask_guard[03:56], 6'b000000}) & {60{dnsp_lv1sh11}}); + + assign ex4_spdenorm_mask_round_shifted_00to03[00:59] = (({ex4_spdenorm_mask_round[00:56], 3'b000}) & {60{dnsp_lv1sh00}}) | + (({ex4_spdenorm_mask_round[01:56], 4'b0000}) & {60{dnsp_lv1sh01}}) | + (({ex4_spdenorm_mask_round[02:56], 5'b00000}) & {60{dnsp_lv1sh10}}) | + (({ex4_spdenorm_mask_round[03:56], 6'b000000}) & {60{dnsp_lv1sh11}}); + + // lev2 + assign dnsp_lv2sh00 = (~sp_denorm_shift_amt[2]) & (~sp_denorm_shift_amt[3]); //00 + assign dnsp_lv2sh01 = (~sp_denorm_shift_amt[2]) & sp_denorm_shift_amt[3]; //01 + assign dnsp_lv2sh10 = sp_denorm_shift_amt[2] & (~sp_denorm_shift_amt[3]); //10 + assign dnsp_lv2sh11 = sp_denorm_shift_amt[2] & sp_denorm_shift_amt[3]; //11 + + assign ex4_spdenorm_mask_shifted_00to12[00:71] = (({ex4_spdenorm_mask_shifted_00to03[00:59], 12'b000000000000}) & {72{dnsp_lv2sh00}}) | + (({ex4_spdenorm_mask_shifted_00to03[04:59], 16'b0000000000000000}) & {72{dnsp_lv2sh01}}) | + (({ex4_spdenorm_mask_shifted_00to03[08:59], 20'b00000000000000000000}) & {72{dnsp_lv2sh10}}) | + (({ex4_spdenorm_mask_shifted_00to03[12:59], 24'b000000000000000000000000}) & {72{dnsp_lv2sh11}}); + + assign ex4_spdenorm_mask_lsb_shifted_00to12[00:71] = (({ex4_spdenorm_mask_lsb_shifted_00to03[00:59], 12'b000000000000}) & {72{dnsp_lv2sh00}}) | + (({ex4_spdenorm_mask_lsb_shifted_00to03[04:59], 16'b0000000000000000}) & {72{dnsp_lv2sh01}}) | + (({ex4_spdenorm_mask_lsb_shifted_00to03[08:59], 20'b00000000000000000000}) & {72{dnsp_lv2sh10}}) | + (({ex4_spdenorm_mask_lsb_shifted_00to03[12:59], 24'b000000000000000000000000}) & {72{dnsp_lv2sh11}}); + + assign ex4_spdenorm_mask_guard_shifted_00to12[00:71] = (({ex4_spdenorm_mask_guard_shifted_00to03[00:59], 12'b000000000000}) & {72{dnsp_lv2sh00}}) | + (({ex4_spdenorm_mask_guard_shifted_00to03[04:59], 16'b0000000000000000}) & {72{dnsp_lv2sh01}}) | + (({ex4_spdenorm_mask_guard_shifted_00to03[08:59], 20'b00000000000000000000}) & {72{dnsp_lv2sh10}}) | + (({ex4_spdenorm_mask_guard_shifted_00to03[12:59], 24'b000000000000000000000000}) & {72{dnsp_lv2sh11}}); + + assign ex4_spdenorm_mask_round_shifted_00to12[00:71] = (({ex4_spdenorm_mask_round_shifted_00to03[00:59], 12'b000000000000}) & {72{dnsp_lv2sh00}}) | + (({ex4_spdenorm_mask_round_shifted_00to03[04:59], 16'b0000000000000000}) & {72{dnsp_lv2sh01}}) | + (({ex4_spdenorm_mask_round_shifted_00to03[08:59], 20'b00000000000000000000}) & {72{dnsp_lv2sh10}}) | + (({ex4_spdenorm_mask_round_shifted_00to03[12:59], 24'b000000000000000000000000}) & {72{dnsp_lv2sh11}}); + + // lev3 + assign dnsp_lv3sh00 = (~sp_denorm_shift_amt[0]) & (~sp_denorm_shift_amt[1]); //00 + assign dnsp_lv3sh01 = (~sp_denorm_shift_amt[0]) & sp_denorm_shift_amt[1]; //01 + assign dnsp_lv3sh10 = sp_denorm_shift_amt[0] & (~sp_denorm_shift_amt[1]); //10 + assign dnsp_lv3sh11 = sp_denorm_shift_amt[0] & sp_denorm_shift_amt[1]; //11 + + assign ex4_spdenorm_mask_shifted_00to48[00:119] = (({ex4_spdenorm_mask_shifted_00to12[00:71], {48{1'b0}}}) & {120{dnsp_lv3sh00}}) | + (({ex4_spdenorm_mask_shifted_00to12[16:71], {64{1'b0}}}) & {120{dnsp_lv3sh01}}); + + assign ex4_spdenorm_mask_lsb_shifted_00to48[00:119] = (({ex4_spdenorm_mask_lsb_shifted_00to12[00:71], {48{1'b0}}}) & {120{dnsp_lv3sh00}}) | + (({ex4_spdenorm_mask_lsb_shifted_00to12[16:71], {64{1'b0}}}) & {120{dnsp_lv3sh01}}); + + assign ex4_spdenorm_mask_guard_shifted_00to48[00:119] = (({ex4_spdenorm_mask_guard_shifted_00to12[00:71], {48{1'b0}}}) & {120{dnsp_lv3sh00}}) | + (({ex4_spdenorm_mask_guard_shifted_00to12[16:71], {64{1'b0}}}) & {120{dnsp_lv3sh01}}); + + assign ex4_spdenorm_mask_round_shifted_00to48[00:119] = (({ex4_spdenorm_mask_round_shifted_00to12[00:71], {48{1'b0}}}) & {120{dnsp_lv3sh00}}) | + (({ex4_spdenorm_mask_round_shifted_00to12[16:71], {64{1'b0}}}) & {120{dnsp_lv3sh01}}); + + assign ex4_divsqrt_fract_shifted_spmasked[00:56] = ex4_spdenorm_mask_shifted_00to48[00:56] & ex4_divsqrt_fract_cur[00:56]; + assign ex4_divsqrt_fract_stickymask[00:56] = (~ex4_spdenorm_mask_shifted_00to48[00:56]) & ex4_divsqrt_fract_cur[00:56]; + + //-------------------------------------------------------------------------------------------------------------------------------- + assign ex4_divsqrt_fract_shifted[00:56] = (ex4_divsqrt_fract_shifted_spmasked[00:56] & {57{ex4_sp}}) | + (ex4_divsqrt_fract_shifted_dp[00:56] & {57{ex4_dp}}); + //-------------------------------------------------------------------------------------------------------------------------------- + + // round after denorm result + //ex4_denormalizing_result_rounding + + assign ex4_divsqrt_fract_dnr_p0 = {1'b0, exx_divsqrt_fract_q[00:52]}; + assign ex4_divsqrt_fract_dnr_p1 = ({1'b0, exx_divsqrt_fract_q[00:52]}) + ({{53{1'b0}}, 1'b1}); + + assign lsb_dnr = exx_divsqrt_fract_q[52]; + + assign guard_dnr = exx_divsqrt_fract_q[53]; + + assign round_dnr = sticky_dnr | exx_divsqrt_fract_q[54]; + + assign sticky_dnr = denorm_sticky; + + assign ex4_round_up_dnr = ((guard_dnr & (lsb_dnr | sticky_dnr | round_dnr)) & RNEmode) | ((1'b0) & RTZmode) | (((guard_dnr | round_dnr) & (~sign)) & RPImode) | (((guard_dnr | round_dnr) & sign) & RNImode); // round to nearest mode + + assign ex4_divsqrt_fract_dnr_dp = (ex4_divsqrt_fract_dnr_p0 & {54{(~ex4_round_up_dnr)}}) | + (ex4_divsqrt_fract_dnr_p1 & {54{ex4_round_up_dnr}}); + + // sp denorm rounding ---------------- + assign ex4_divsqrt_fract_dnr_sp_p0 = {1'b0, exx_divsqrt_fract_q[00:52]}; + assign ex4_divsqrt_fract_dnr_sp_p1 = ({1'b0, exx_divsqrt_fract_q[00:52]}) + ({1'b0, ex4_spdenorm_mask_lsb_shifted_00to48[00:52]}); + + assign lsb_dnr_sp = |(ex4_spdenorm_mask_lsb_shifted_00to48[00:25] & exx_divsqrt_fract_q[00:25]); + + assign guard_dnr_sp = |(ex4_spdenorm_mask_guard_shifted_00to48[00:26] & exx_divsqrt_fract_q[00:26]); + + assign round_dnr_sp = sticky_dnr_sp | |(ex4_spdenorm_mask_round_shifted_00to48[00:27] & exx_divsqrt_fract_q[00:27]); + + assign sticky_dnr_sp = denorm_sticky_sp; + + assign ex4_round_up_dnr_sp = ((guard_dnr_sp & (lsb_dnr_sp | sticky_dnr_sp | round_dnr_sp)) & RNEmode) | + ((1'b0) & RTZmode) | + (((guard_dnr_sp | round_dnr_sp) & (~sign)) & RPImode) | + (((guard_dnr_sp | round_dnr_sp) & sign) & RNImode); + + assign ex4_divsqrt_fract_dnr_sp_prem = (ex4_divsqrt_fract_dnr_sp_p0 & {54{(~ex4_round_up_dnr_sp)}}) | + (ex4_divsqrt_fract_dnr_sp_p1 & {54{ex4_round_up_dnr_sp}}); + + assign ex4_divsqrt_fract_dnr_sp = ex4_divsqrt_fract_dnr_sp_prem & + (~({1'b0, ex4_spdenorm_mask_guard_shifted_00to48[00:52]})) & + (~({1'b0, ex4_spdenorm_mask_round_shifted_00to48[00:52]})); + + assign ex4_divsqrt_fract_dnr = (ex4_divsqrt_fract_dnr_sp & {54{exx_sp}}) | + (ex4_divsqrt_fract_dnr_dp & {54{exx_dp}}); + + assign ex4_dnr_roundup_incexp = ex4_divsqrt_fract_dnr[0] & ex4_denormalizing_result_done & (~exx_hard_spec_case) & (~ex4_force); // rounded up past the implicit bit (which is bit 1 here) + + assign ex4_denorm_res_shiftoff_zero = denorm_res_shiftoff_q & (~ex4_round_up_dnr) & ex4_denormalizing_result_done; + + //------------------------------------------------------------------------------------------------------------------ + + + tri_rlmreg_p #(.INIT(0), .WIDTH(27), .NEEDS_SRESET(1)) exx_div_denorm_lat( + .force_t(force_t), .d_mode(tiup), .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + //----------------- + .act(tiup), + //----------------- + .scout(exx_div_denorm_lat_scout), + .scin(exx_div_denorm_lat_scin), + //----------------- + .din({ + denorm_sticky_sp_din, + ex4_norm_shl1_d, + denorm_res_shiftoff_din, + denorm_sticky_din, + denorm_count_din, + denorm_shift_amt_din, + sp_denorm_shift_amt_din, + ex3_norm_shl1, + ex4_div_special_case, + ex4_round_up, + ex4_denormalizing_result_done_din, + ex4_force_inf}), + //----------------- + .dout({ denorm_sticky_sp_q, + ex4_norm_shl1_q, + denorm_res_shiftoff_q, + denorm_sticky_q, + denorm_count_q, + denorm_shift_amt_q, + sp_denorm_shift_amt_q, + ex4_norm_shl1, + ex5_div_special_case, + ex5_round_up, + ex5_denormalizing_result_done, + ex5_force_inf}) + ); + + + //----------------------------------------------------------------------- + //----------------------------------------------------------------------- + // Special cases: NaN, etc + assign exx_a_NAN = exx_a_expo_max_q & (~exx_a_frac_zero_q); + assign exx_b_NAN = exx_b_expo_max_q & (~exx_b_frac_zero_q); + assign exx_a_INF = exx_a_expo_max_q & exx_a_frac_zero_q; + assign exx_b_INF = exx_b_expo_max_q & exx_b_frac_zero_q; + assign exx_a_SPoverflowINF = exx_a_SPoverflow_expo_max_q; + assign exx_b_SPoverflowINF = exx_b_SPoverflow_expo_max_q; + + assign exx_b_ZER = exx_b_zero_q; + assign exx_a_ZER = exx_a_zero_q; + assign exx_a_SPunderflowZER = exx_a_SPunderflow_zero_q; + assign exx_b_SPunderflowZER = exx_b_SPunderflow_zero_q; + assign exx_invalid_mixed_precision = ((exx_b_SPunderflowZER | exx_b_SPoverflowINF) | (exx_div_q[3] & (exx_a_SPunderflowZER | exx_a_SPoverflowINF))) & (~((exx_div_q[3] & (exx_a_NAN | exx_a_INF | exx_a_ZER)) | (exx_b_NAN | exx_b_INF | exx_b_ZER))); + + assign exx_hard_spec_case = (exx_div_q[3] & (exx_a_NAN | exx_a_INF | exx_a_ZER | exx_a_SPunderflowZER | exx_a_SPoverflowINF)) | (exx_b_NAN | exx_b_INF | exx_b_ZER | exx_b_SPunderflowZER | exx_b_SPoverflowINF) | (exx_sqrt_q[3] & exx_b_sign_q); + + assign ex4_div_by_zero_zx = exx_b_ZER & (~(exx_div_q[3] & exx_a_INF)) & (~(exx_a_SPunderflowZER | exx_a_SPoverflowINF)) & (~exx_sqrt_q[3]) & (~ex4_zero_div_zero) & (~ex4_pass_nan); + assign ex4_zero_div_zero = (exx_a_ZER & exx_b_ZER) & exx_div_q[3]; + assign ex4_inf_div_inf = (exx_a_INF & exx_b_INF) & exx_div_q[3]; + assign ex4_sqrt_neg = exx_sqrt_q[3] & exx_b_sign_q & (~exx_b_ZER) & (~ex4_pass_nan); + + assign ex4_div_special_case = ex4_pass_a_nan | + ex4_pass_b_nan | + ex4_force_qnan | + ex4_force_zero | + ex4_force_zeroone | + ex4_force_36A | + ex4_force_maxnorm; + + assign underflow_force_zero = underflow & exp_gt_cap & (~ex4_round_up_underflow) & (~UE) & (~exx_hard_spec_case); + assign underflow_force_zeroone = underflow_dp & exp_gt_cap & ex4_round_up_underflow & exx_dp & (~UE) & (~exx_hard_spec_case); + assign underflow_force_36A = underflow_sp & exp_gt_cap & ex4_round_up_underflow & exx_sp & (~UE) & (~exx_hard_spec_case); + + assign sp_denorm_0x369roundup = ex4_denormalizing_result_rounding & ex4_round_up_dnr_sp & exx_sp & exp_eq_367to9; + assign sp_denorm_0x380roundup = ex4_denormalizing_result_rounding & ex4_divsqrt_fract_dnr[0] & exx_sp & exp_eq_380; + assign sp_denorm_underflow_zero = ex4_denormalizing_result_rounding & (~ex4_round_up_dnr_sp) & exx_sp & exp_eq_367to9 & (~UE); + + assign underflow_sp_denorm = underflow & (~exp_gt_cap) & (~UE) & (~exx_hard_spec_case) & ex4_sp; + + assign overflow_force_inf = ((overflow & RNEmode) | (overflow & RPImode & (~ex4_divsqrt_sign)) | (overflow & RNImode & ex4_divsqrt_sign)) & (~exx_hard_spec_case) & (~OE); + + assign overflow_force_maxnorm = ((overflow & RTZmode) | (overflow & RPImode & ex4_divsqrt_sign) | (overflow & RNImode & (~ex4_divsqrt_sign))) & (~exx_hard_spec_case) & (~OE); + + assign ex4_maxnorm_sign = ex4_divsqrt_sign; + + assign special_force_zero = (exx_b_INF & (~exx_sqrt_q[3])) | (exx_a_ZER & (~exx_sqrt_q[3])) | (exx_b_ZER & exx_sqrt_q[3]); + assign special_force_inf = (exx_a_INF & (~exx_sqrt_q[3])) | (exx_b_ZER & (~exx_sqrt_q[3])) | (exx_b_INF & exx_sqrt_q[3]); + + assign ex4_force_36A = (sp_denorm_0x369roundup | underflow_force_36A) & (~(ex4_force_qnan | ex4_pass_nan)); + assign ex4_force_zeroone = underflow_force_zeroone & (~(ex4_force_qnan | ex4_pass_nan)); + assign ex4_force_zero = (underflow_force_zero | special_force_zero | sp_denorm_underflow_zero | ex4_deno_force_zero) & (~(ex4_force_qnan | ex4_pass_nan)); + assign ex4_force_inf = (overflow_force_inf | special_force_inf) & (~(ex4_force_qnan | ex4_pass_nan)); + assign ex4_force_maxnorm = overflow_force_maxnorm & (~(ex4_force_qnan | ex4_pass_nan)); + assign ex4_force_maxnorm_dp = ex4_force_maxnorm & ex4_dp; + assign ex4_force_maxnorm_sp = ex4_force_maxnorm & ex4_sp; + assign ex4_force_qnan = ex4_zero_div_zero | ex4_inf_div_inf | ex4_sqrt_neg | exx_b_SPunderflowZER | exx_b_SPoverflowINF | ((exx_a_SPunderflowZER | exx_a_SPoverflowINF) & exx_div_q[3]); + + assign ex4_force = ex4_force_36A | ex4_force_zeroone | ex4_force_zero | ex4_force_maxnorm | ex4_force_qnan; + + assign ex4_deno_force_zero = ex4_denormalizing_result_done & f_dcd_axucr0_deno; + + assign ex4_pass_a_nan = exx_a_NAN & (~exx_sqrt_q[3]); + assign ex4_pass_b_nan = exx_b_NAN & (~ex4_pass_a_nan); + assign ex4_pass_a_nan_sp = ex4_pass_a_nan & exx_sp; + assign ex4_pass_b_nan_sp = ex4_pass_b_nan & exx_sp; + assign ex4_pass_a_nan_dp = ex4_pass_a_nan & exx_dp; + assign ex4_pass_b_nan_dp = ex4_pass_b_nan & exx_dp; + + assign ex4_a_snan = exx_a_NAN & (~exx_a_fract_q[1]) & (~exx_sqrt_q[3]); + assign ex4_b_snan = exx_b_NAN & (~exx_b_fract_q[1]); + assign ex4_pass_nan = ex4_pass_a_nan | ex4_pass_b_nan; + assign ex4_snan = ex4_a_snan | ex4_b_snan; + + assign ex4_divsqrt_sign_special = (exx_a_sign_q & ex4_pass_a_nan) | + (exx_b_sign_q & ex4_pass_b_nan) | + (1'b0 & ex4_force_qnan) | + (ex4_divsqrt_sign & ex4_force_zero) | + (ex4_divsqrt_sign & ex4_force_zeroone) | + (ex4_divsqrt_sign & ex4_force_36A) | + (ex4_divsqrt_sign & ex4_force_inf) | + (ex4_divsqrt_sign & ex4_dnr_roundup_incexp) | + (ex4_divsqrt_sign & ex4_roundup_incexp) | + (ex4_maxnorm_sign & ex4_force_maxnorm); + + assign ex4_divsqrt_exp_special[01:13] = ({13{1'b0}} & {13{ex4_force_zero}}) | + ({{12{1'b0}}, 1'b1} & {13{ex4_force_zeroone}}) | + ({2'b00, ones[03:13]} & {13{ex4_pass_nan}}) | + ({2'b00, ones[03:13]} & {13{ex4_force_qnan}}) | + ({2'b00, ones[03:12], 1'b0} & {13{ex4_force_maxnorm_dp}}) | + (13'b0001101101010 & {13{ex4_force_36A}}) | + (13'b0010001111110 & {13{ex4_force_maxnorm_sp}}); + + assign ex4_divsqrt_fract_special[00:52] = ({53{1'b0}} & {53{ex4_force_zero}}) | + ({{52{1'b0}}, 1'b1} & {53{ex4_force_zeroone}}) | + ({1'b1, {52{1'b0}}} & {53{ex4_force_36A}}) | + (({2'b11, zeros[2:52]}) & {53{ex4_force_qnan}}) | + (({2'b11, exx_a_fract_q[2:23], zeros[24:52]}) & {53{ex4_pass_a_nan_sp}}) | + (({2'b11, exx_b_fract_q[2:23], zeros[24:52]}) & {53{ex4_pass_b_nan_sp}}) | + (({2'b11, exx_a_fract_q[2:52]}) & {53{ex4_pass_a_nan_dp}}) | + (({2'b11, exx_b_fract_q[2:52]}) & {53{ex4_pass_b_nan_dp}}) | + ({53{1'b1}} & {53{ex4_force_maxnorm_dp}}) | + ({{24{1'b1}}, {29{1'b0}}} & {53{ex4_force_maxnorm_sp}}); + + //----------------------------------------------------------------------- + // some final result muxing + //----------------------------------------------------------------------- + + assign ex4_divsqrt_sign = exx_a_sign_q ^ exx_b_sign_q; + + assign exx_divsqrt_sign_d = (ex4_divsqrt_sign & (~ex4_div_special_case)) | (ex4_divsqrt_sign_special & ex4_div_special_case); + + assign ex4_divsqrt_exp = ((exx_exp_addres) & {13{(ex4_divsqrt_done_q & (~ex4_denormalizing_result_done))}}) | + ((exx_exp_addres) & {13{(ex4_denormalizing_result_done & ex4_sp)}}) | + (13'b0000000000001 & {13{(ex4_denormalizing_result_done & (~ex4_sp))}}); + + assign exx_divsqrt_exp_d = ex4_divsqrt_exp; + + assign ex4_divsqrt_fract = ex4_divsqrt_fract_p0[01:53]; + + // generate the remainder + assign exx_divsqrt_fract_d = (ex3_divsqrt_remainder[00:56] & {57{(ex3_divsqrt_done & (~ex4_denormalizing_result) & (~ex4_start_a_denorm_result))}}) | + ({ex4_divsqrt_fract[00:52], 4'b0000} & {57{(ex4_divsqrt_done_q & (~ex4_denormalizing_result) & (~ex4_start_a_denorm_result))}}) | + ({ex4_divsqrt_fract_dnr[01:53], 4'b0000} & {57{(ex4_denormalizing_result_rounding & (~ex4_denormalizing_result_shifting) & (~ex4_start_a_denorm_result))}}) | + (ex4_divsqrt_fract_shifted[00:56] & {57{(ex4_denormalizing_result_shifting & (~ex4_denormalizing_result_rounding) & (~ex4_start_a_denorm_result))}}) | + (ex4_divsqrt_fract_preround[00:56] & {57{(ex4_start_denorm_result)}}) | + (({ex4_divsqrt_fract_preround[28:56], zeros[0:27]}) & {57{(ex4_start_sp_denorm_result)}}); // grab the rounded/corrected result + + //----------------------------------------------------------------------- + //----------------------------------------------------------------------- + ////#------------------------------------------------------------------------ + ////# decode fprf field for pipe settings + ////#------------------------------------------------------------------------ + // FPRF + // 10001 QNAN [0] qnan | den | (sign*zero) + // 01001 -INF [1] sign * !zero + // 01000 -norm [2] !sign * !zero * !qnan + // 11000 -den [3] zero + // 10010 -zero [4] inf | qnan + // 00010 +zero + // 10100 +den + // 00100 +norm + // 00101 +inf + + // FPSCR status bits + // [ 0] ox 0 + // [ 1] ux 0 + // [ 2] zx 0 + // [ 3] xx 1 (not needed, comes from FI) + // [ 4] FR 1 + // [ 5] FI 1 + + // [ 6] sign + // [ 7] not sign and not zero, redundant in rnd? + // [ 8] zer + // [ 9] inf + // [10] den + // [11] vxidi + // [12] vxzdz + // [13] vxsqrt + // [14] nan + // [15] vxsnan + + assign exx_divsqrt_flag_fpscr_d[0] = overflow & (~exx_hard_spec_case); + assign exx_divsqrt_flag_fpscr_d[1] = underflow_fi & (~exx_hard_spec_case) & (~ex4_deno_force_zero); + assign exx_divsqrt_flag_fpscr_d[2] = ex4_div_by_zero_zx; + assign exx_divsqrt_flag_fpscr_d[3] = ex4_rem_nonzero_fi & (~exx_hard_spec_case) & (~ex4_deno_force_zero); + assign exx_divsqrt_flag_fpscr_d[4] = ((((ex4_round_up & (~(underflow & (~UE)))) | ex4_force_zeroone | ex4_force_36A) & (~ex4_denormalizing_result_done)) | (((ex4_round_up_dnr & exx_dp) | (ex4_round_up_dnr_sp & exx_sp)) & ex4_denormalizing_result_done) | (overflow & (~OE))) & (~exx_hard_spec_case) & (~ex4_deno_force_zero); // and not underflow_fi; + assign exx_divsqrt_flag_fpscr_d[5] = (ex4_rem_nonzero_fi | (overflow & (~OE)) | (underflow_fi & (~UE))) & (~exx_hard_spec_case) & (~ex4_deno_force_zero); + assign exx_divsqrt_flag_fpscr_d[6] = exx_divsqrt_sign_d; // and not (ex4_pass_nan or ex4_force_qnan); + assign exx_divsqrt_flag_fpscr_d[7] = ((~exx_divsqrt_sign_d)) & (~ex4_force_zero) & (~(ex4_pass_nan | ex4_force_qnan)); + assign exx_divsqrt_flag_fpscr_d[8] = (ex4_force_zero | ex4_denorm_res_shiftoff_zero) & (~(ex4_pass_nan | ex4_force_qnan)); + assign exx_divsqrt_flag_fpscr_d[9] = ex4_force_inf; + assign exx_divsqrt_flag_fpscr_d[10] = ((((ex4_denormalizing_result_done & ((~exx_divsqrt_fract_d[0]) & exx_dp)) | underflow_sp_denorm) & (~sp_denorm_0x380roundup)) | ex4_force_zeroone | ex4_force_36A) & (~ex4_deno_force_zero); + assign exx_divsqrt_flag_fpscr_d[11] = ex4_inf_div_inf; + assign exx_divsqrt_flag_fpscr_d[12] = ex4_zero_div_zero; + assign exx_divsqrt_flag_fpscr_d[13] = ex4_sqrt_neg & (~exx_b_SPunderflow_zero_q) & (~exx_b_SPoverflow_expo_max_q); + assign exx_divsqrt_flag_fpscr_d[14] = ex4_force_qnan | ex4_pass_nan; + assign exx_divsqrt_flag_fpscr_d[15] = ex4_snan; + + assign exx_divsqrt_v_suppress_d = (zezx | vevx) & (~exx_invalid_mixed_precision); + + assign ex3_rem_neg = ex3_divsqrt_remainder[0]; + assign ex3_rem_neg_b = (~ex3_divsqrt_remainder[0]); + + + tri_rlmreg_p #(.INIT(0), .WIDTH(96), .NEEDS_SRESET(0)) ex5_div_result_lat( + .force_t(force_t), .d_mode(tiup), .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + //----------------- + .act(exx_running_act_q), + //----------------- + .scout(ex5_div_result_lat_scout), + .scin(ex5_div_result_lat_scin), + //----------------- + .din({ + exx_divsqrt_sign_d, + exx_divsqrt_exp_d, + exx_divsqrt_fract_d, + exx_divsqrt_flag_fpscr_d, + exx_divsqrt_v_suppress_d, + ex3_rem_neg, + ex3_rem_neg, + ex3_rem_neg, + ex3_rem_neg, + ex3_rem_neg_b, + ex3_rem_neg_b, + ex3_rem_neg_b, + ex3_rem_neg_b }), + //----------------- + .dout({ exx_divsqrt_sign_q, + exx_divsqrt_exp_q[1:13], + exx_divsqrt_fract_q[00:56], + exx_divsqrt_flag_fpscr_q, + exx_divsqrt_v_suppress_q, + ex4_rem_neg[0], + ex4_rem_neg[1], + ex4_rem_neg[2], + ex4_rem_neg[3], + ex4_rem_neg_b[0], + ex4_rem_neg_b[1], + ex4_rem_neg_b[2], + ex4_rem_neg_b[3] }) + ); + + tri_rlmreg_p #(.INIT(0), .WIDTH(163), .NEEDS_SRESET(0)) ex5_special_case_lat( + .force_t(force_t), .d_mode(tiup), .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + //----------------- + .act(exx_running_act_q), + //----------------- + .scout(ex5_special_case_lat_scout), + .scin(ex5_special_case_lat_scin), + //----------------- + + .din({ex4_divsqrt_fract_special, + ex4_divsqrt_fract_p1, + ex4_divsqrt_exp_special, + exx_exp_addres_x0_p1, + exx_exp_addres_ux_p1, + exx_exp_addres_ox_p1, + ueux, + oeox, + not_ueux_or_oeox, + ex4_x_roundup_incexp + }), + //----------------- + .dout({ + ex5_divsqrt_fract_special, + ex5_divsqrt_fract_p1, + ex5_divsqrt_exp_special, + exy_exp_addres_x0_p1, + exy_exp_addres_ux_p1, + exy_exp_addres_ox_p1, + exy_ueux, + exy_oeox, + exy_not_ueux_or_oeox, + ex5_x_roundup_incexp + }) + ); + + assign exy_exp_addres_p1 = (exy_exp_addres_x0_p1 & {13{exy_not_ueux_or_oeox}}) | + (exy_exp_addres_ux_p1 & {13{exy_ueux}}) | + (exy_exp_addres_ox_p1 & {13{exy_oeox}}); + + + + assign ex5_divsqrt_fract_d = (exx_divsqrt_fract_q[00:52] & {53{(((~(ex5_div_special_case | ex5_force_inf | ex5_round_up | ex5_x_roundup_incexp))) | ex5_denormalizing_result_done)}}) | + (ex5_divsqrt_fract_special[00:52] & {53{(ex5_div_special_case & (~ex5_force_inf))}}) | + ({1'b1, {52{1'b0}}} & {53{ex5_x_roundup_incexp}}) | + ({1'b1, {52{1'b0}}} & {53{(ex5_force_inf)}}) | + (ex5_divsqrt_fract_p1[01:53] & {53{((~(ex5_div_special_case | ex5_force_inf | ex5_x_roundup_incexp)) & ex5_round_up & (~ex5_denormalizing_result_done))}}); + + assign ex5_divsqrt_exp_d = (exx_divsqrt_exp_q[01:13] & {13{((~ex5_denormalizing_result_done) & (~(ex5_div_special_case | ex5_force_inf | ex5_x_roundup_incexp)))}}) | + (exx_divsqrt_exp_q[01:13] & {13{(ex5_denormalizing_result_done & (~(ex5_div_special_case | ex5_force_inf | ex5_x_roundup_incexp)))}}) | + (exy_exp_addres_p1[0:12] & {13{(ex5_x_roundup_incexp & (~ex5_force_inf))}}) | + ({2'b00, ones[03:13]} & {13{(ex5_force_inf)}}) | + (ex5_divsqrt_exp_special[01:13] & {13{(ex5_div_special_case & (~ex5_force_inf))}}); + + + tri_rlmreg_p #(.INIT(0), .WIDTH(66), .NEEDS_SRESET(0)) ex6_div_result_lat( + .force_t(force_t), .d_mode(tiup), .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + //----------------- + .act(tiup), + //----------------- + .scout(ex6_div_result_lat_scout), + .scin(ex6_div_result_lat_scin), + //----------------- + + .din({ex5_divsqrt_fract_d, + ex5_divsqrt_exp_d}), + //----------------- + .dout({ ex6_divsqrt_fract_q, + ex6_divsqrt_exp_q}) + ); + + assign ex4_divsqrt_done = (ex4_divsqrt_done_q | ex4_denormalizing_result_done) & (~ex4_start_a_denorm_result); + + assign f_dsq_ex5_divsqrt_v[0] = ex5_divsqrt_done & exx_instr_tid_q[0]; + assign f_dsq_ex5_divsqrt_v[1] = ex5_divsqrt_done & exx_instr_tid_q[1]; + assign f_dsq_ex6_divsqrt_v[0] = ex6_divsqrt_done & exx_instr_tid_q[0]; + assign f_dsq_ex6_divsqrt_v[1] = ex6_divsqrt_done & exx_instr_tid_q[1]; + + assign f_dsq_ex6_divsqrt_record_v = exx_record_v_q & ex6_divsqrt_done; + assign f_dsq_ex6_divsqrt_v_suppress = exx_divsqrt_v_suppress_q; + assign f_dsq_ex5_divsqrt_itag = exx_itag_q; + assign f_dsq_ex6_divsqrt_fpscr_addr = exx_fpscr_addr_q; + assign f_dsq_ex6_divsqrt_instr_frt = exx_instr_frt_q; + assign f_dsq_ex6_divsqrt_instr_tid = exx_instr_tid_q; + assign f_dsq_ex6_divsqrt_cr_bf = exx_cr_bf_q; + assign f_dsq_ex6_divsqrt_sign = exx_divsqrt_sign_q; + assign f_dsq_ex6_divsqrt_exp[01:13] = ex6_divsqrt_exp_q; //exx_divsqrt_exp_q; + assign f_dsq_ex6_divsqrt_fract[00:52] = ex6_divsqrt_fract_q; //exx_divsqrt_fract_q(00 to 52); + assign f_dsq_ex6_divsqrt_flag_fpscr = exx_divsqrt_flag_fpscr_q; + + assign f_dsq_debug_din[00] = ex1_cycles_init; // 0:11 are on trigger group 2, 12:23 on 3 + assign f_dsq_debug_din[01] = ex1_cycles_hold; + assign f_dsq_debug_din[02] = ex1_divsqrt_done; + assign f_dsq_debug_din[03] = ex2_divsqrt_done; + assign f_dsq_debug_din[04] = ex3_divsqrt_done; + assign f_dsq_debug_din[05] = ex4_divsqrt_done; + assign f_dsq_debug_din[06] = ex5_divsqrt_done; + assign f_dsq_debug_din[07] = ex6_divsqrt_done; + assign f_dsq_debug_din[08] = ex1_cycles_clear; + assign f_dsq_debug_din[09] = exx_divsqrt_running_q; + assign f_dsq_debug_din[10] = exx_running_act_q; + assign f_dsq_debug_din[11] = ex1_sqrt; + assign f_dsq_debug_din[12] = ex2_cycles_q[0]; // 0:11 are on trigger group 2, 12:23 on 3 + assign f_dsq_debug_din[13] = ex2_cycles_q[1]; + assign f_dsq_debug_din[14] = ex2_cycles_q[2]; + assign f_dsq_debug_din[15] = ex2_cycles_q[3]; + assign f_dsq_debug_din[16] = ex2_cycles_q[4]; + assign f_dsq_debug_din[17] = ex2_cycles_q[5]; + assign f_dsq_debug_din[18] = ex2_cycles_q[6]; + assign f_dsq_debug_din[19] = ex2_cycles_q[7]; + assign f_dsq_debug_din[20] = ex1_cycles_hold; + assign f_dsq_debug_din[21] = ex1_cycles_init; + assign f_dsq_debug_din[22] = exx_single_precision_d; + assign f_dsq_debug_din[23] = exx_sqrt_d; + assign f_dsq_debug_din[24] = exx_sum4[0]; + assign f_dsq_debug_din[25] = exx_sum4[1]; + assign f_dsq_debug_din[26] = exx_sum4[2]; + assign f_dsq_debug_din[27] = exx_sum4[3]; + assign f_dsq_debug_din[28] = exx_q_bit0_cin; + assign f_dsq_debug_din[29:63] = exx_Q_q[22:56]; + + + tri_rlmreg_p #(.INIT(0), .WIDTH(64), .NEEDS_SRESET(0)) f_dsq_debug_lat( + .force_t(force_t), .d_mode(tiup), .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + //----------------- + .act(tiup), + //----------------- + .scout(f_dsq_debug_lat_scout), + .scin(f_dsq_debug_lat_scin), + //----------------- + + .din(f_dsq_debug_din), + //----------------- + .dout(f_dsq_debug_q) + ); + + assign f_dsq_debug = f_dsq_debug_q; + + //------------------------------------------------------------------------------ + // sinkless + //------------------------------------------------------------------------------ + +assign spare_unused[2] = exx_Qin_lev0[0]; +assign spare_unused[3] = exx_QMin_lev0[0]; +assign spare_unused[4] = exx_bQ_q_t[56]; +assign spare_unused[5] = exx_bQM_q_t[56]; +assign spare_unused[6] = exx_lev0_csaout_carryout[0]; +assign spare_unused[7] = fpu_enable; +assign spare_unused[8] = exx_lev0_csaoutsh_carry[0]; +assign spare_unused[9] = exx_lev1_div_csaout_carryout[0]; +assign spare_unused[10] = exx_lev1_sqrt_csaout_carryout[0]; +assign spare_unused[11] = exx_lev1_div_csaout_carry[4]; +assign spare_unused[12:62] = exx_lev1_div_csaout_carry[6:56]; +assign spare_unused[63] = exx_lev1_sqrt_csaout_carry[4]; +assign spare_unused[64:114] = exx_lev1_sqrt_csaout_carry[6:56]; +assign spare_unused[115] = exx_lev1_div_csaout_sum[4]; +assign spare_unused[116:166] = exx_lev1_div_csaout_sum[6:56]; +assign spare_unused[167] = exx_lev1_sqrt_csaout_sum[4]; +assign spare_unused[168:218] = exx_lev1_sqrt_csaout_sum[6:56]; +assign spare_unused[219] = exx_q_bit1; +assign spare_unused[220] = exx_nq_bit1; +assign spare_unused[221] = exx_lev2_csaout_sum[4]; +assign spare_unused[222:272] = exx_lev2_csaout_sum[6:56]; +assign spare_unused[273] = exx_lev2_csaout_carryout[0]; +assign spare_unused[274] = exx_lev2_csaout_carry[4]; +assign spare_unused[275:325] = exx_lev2_csaout_carry[6:56]; +assign spare_unused[326] = exx_lev3_div_csaout_carryout[0]; +assign spare_unused[327] = exx_lev3_sqrt_csaout_carryout[0]; +assign spare_unused[328] = exx_lev3_div_csaout_carry[4]; +assign spare_unused[329:379] = exx_lev3_div_csaout_carry[6:56]; +assign spare_unused[380] = exx_lev3_sqrt_csaout_carry[4]; +assign spare_unused[381:431] = exx_lev3_sqrt_csaout_carry[6:56]; +assign spare_unused[432] = exx_lev3_div_csaout_sum[4]; +assign spare_unused[433:483] = exx_lev3_div_csaout_sum[6:56]; +assign spare_unused[484] = exx_lev3_sqrt_csaout_sum[4]; +assign spare_unused[485:535] = exx_lev3_sqrt_csaout_sum[6:56]; +assign spare_unused[536] = exx_q_bit3; +assign spare_unused[537] = exx_nq_bit3; +assign spare_unused[538] = exx_nq_bit22; +assign spare_unused[539] = exx_lev0_csaoutsh_sum[0]; +assign spare_unused[540] = exx_lev22_csaout_carryout_div[0]; +assign spare_unused[541] = exx_lev22_csaout_carryout_sqrt[0]; +assign spare_unused[542:594] = ex4_divsqrt_fract_rounded[1:53]; +assign spare_unused[595] = ex4_incexp_to_overflow; +assign spare_unused[596] = ex4_norm_shl1_test; +assign spare_unused[597] = denorm_exp_addres[13]; +assign spare_unused[598:610] = denorm_exp_addres_sp[1:13]; +assign spare_unused[611] = ex4_divsqrt_denorm_hold; +assign spare_unused[612] = dnsp_lv3sh10; +assign spare_unused[613] = dnsp_lv3sh11; +assign spare_unused[614:676] = ex4_spdenorm_mask_shifted_00to48[57:119]; +assign spare_unused[677:743] = ex4_spdenorm_mask_lsb_shifted_00to48[53:119]; +assign spare_unused[744:810] = ex4_spdenorm_mask_guard_shifted_00to48[53:119]; +assign spare_unused[811:877] = ex4_spdenorm_mask_round_shifted_00to48[53:119]; +assign spare_unused[878] = ex5_divsqrt_fract_p1[0]; +assign spare_unused[879] = ex4_act; +assign spare_unused[880] = ex2_record_v; + + //------------------------------------------------------------------------------ + // scan chain + //------------------------------------------------------------------------------ + + assign ex1_div_ctr_lat_scin[0:18] = {ex1_div_ctr_lat_scout[1:18], f_dsq_si}; + + assign ex3_div_hangcounter_lat_scin[0:7] = {ex3_div_hangcounter_lat_scout[1:7], ex1_div_ctr_lat_scout[0]}; + assign ex2_div_b_stage_lat_scin[0:70] = {ex2_div_b_stage_lat_scout[1:70], ex3_div_hangcounter_lat_scout[0]}; + assign ex2_div_exp_lat_scin[0:51] = {ex2_div_exp_lat_scout[1:51], ex2_div_b_stage_lat_scout[0]}; + assign ex2_div_a_stage_lat_scin[0:70] = {ex2_div_a_stage_lat_scout[1:70], ex2_div_exp_lat_scout[0]}; + assign ex1_div_instr_lat_scin[0:14] = {ex1_div_instr_lat_scout[1:14], ex2_div_a_stage_lat_scout[0]}; + assign ex2_div_instr_lat_scin[0:5] = {ex2_div_instr_lat_scout[1:5], ex1_div_instr_lat_scout[0]}; + + assign ex2_itag_lat_scin[0:8] = {ex2_itag_lat_scout[1:8], ex2_div_instr_lat_scout[0]}; + + assign ex2_fpscr_addr_lat_scin[0:27] = {ex2_fpscr_addr_lat_scout[1:27], ex2_itag_lat_scout[0]}; + assign exx_div_denorm_lat_scin[0:26] = {exx_div_denorm_lat_scout[1:26], ex2_fpscr_addr_lat_scout[0]}; + + assign ex3_div_PR_sumcarry_lat_scin[0:113] = {ex3_div_PR_sumcarry_lat_scout[1:113], exx_div_denorm_lat_scout[0]}; + assign ex3_div_PR_sum4carry4_lat_scin[0:7] = {ex3_div_PR_sum4carry4_lat_scout[1:7], ex3_div_PR_sumcarry_lat_scout[0]}; + + assign ex3_div_Q_QM_lat_scin[0:113] = {ex3_div_Q_QM_lat_scout[1:113], ex3_div_PR_sum4carry4_lat_scout[0]}; + assign ex3_div_bQ_QM_lat_scin[0:113] = {ex3_div_bQ_QM_lat_scout[1:113], ex3_div_Q_QM_lat_scout[0]}; + + assign ex3_sqrt_bitmask_lat_scin[0:167] = {ex3_sqrt_bitmask_lat_scout[1:167], ex3_div_bQ_QM_lat_scout[0]}; + + assign ex3_denom_lat_scin[0:55] = {ex3_denom_lat_scout[1:55], ex3_sqrt_bitmask_lat_scout[0]}; + assign ex5_div_result_lat_scin[00:95] = {ex5_div_result_lat_scout[01:95], ex3_denom_lat_scout[0]}; + assign ex6_div_result_lat_scin[00:65] = {ex6_div_result_lat_scout[01:65], ex5_div_result_lat_scout[0]}; + assign ex5_special_case_lat_scin[00:162] = {ex5_special_case_lat_scout[01:162], ex6_div_result_lat_scout[0]}; + + assign ex5_div_done_lat_scin[0:3] = {ex5_div_done_lat_scout[1:3], ex5_special_case_lat_scout[0]}; + + assign act_si[0:7] = {act_so[1:7], ex5_div_done_lat_scout[0]}; + assign f_dsq_debug_lat_scin[0:63] = {f_dsq_debug_lat_scout[1:63], act_so[0]}; + + assign f_dsq_so = f_dsq_debug_lat_scout[0]; + +endmodule diff --git a/dev/verilog/work/fu_divsqrt_add4.v b/dev/verilog/work/fu_divsqrt_add4.v new file mode 100755 index 0000000..07169fc --- /dev/null +++ b/dev/verilog/work/fu_divsqrt_add4.v @@ -0,0 +1,131 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +////############################################################################ +////##### Quotient digit selection logic ######### +////############################################################################ + +module fu_divsqrt_add4( + x, + y, + s +); +`include "tri_a2o.vh" + + input [0:3] x; + input [0:3] y; + output [0:3] s; + + wire [0:3] h; + wire [1:3] g_b; + wire [1:2] t_b; + wire g2_3t3; + wire g2_2t3; + wire g2_1t2; + wire t2_1t2; + + wire g4_1t3_b; + + wire g8_1t3; + + //VHDL is below in comments to preserve the labels + //sum4_l1xor: h(0 to 3) <= ( x(0 to 3) xor y(0 to 3) ) ;--Lvl 1/2 P + //sum4_l1nor: t_b(1 to 2) <= not( x(1 to 2) or y(1 to 2) ) ;--Lvl 1 P or G ... -KILL + //sum4_l1nand: g_b(1 to 3) <= not( x(1 to 3) and y(1 to 3) ) ;--Lvl 1 G + + //sum4_l2not: g2_3t3 <= not( g_b(3) );--kogge-stone carry tree + //sum4_l2oai1: g2_2t3 <= not(g_b(2) and (t_b(2) or g_b(3)) ); + //sum4_l2oai2: g2_1t2 <= not(g_b(1) and (t_b(1) or g_b(2)) ); + + //sum4_l2nor: t2_1t2 <= not( (t_b(1) or t_b(2)) ); + + //sum4_l3aoi: g4_1t3_b <= not(g2_1t2 or (t2_1t2 and g2_3t3) ); + + //sum4_l4not3: g8_1t3 <= not( g4_1t3_b ); + + //sum4_l5xor0: s(0) <= ( g8_1t3 xor h(0) );--output + //sum4_l5xor1: s(1) <= ( g2_2t3 xor h(1) );--output + //sum4_l5xor2: s(2) <= ( g2_3t3 xor h(2) );--output + // s(3) <= ( h(3) );--output + + // EXAMPLE + // tri_xor2 #(.WIDTH(1), .BTR("XOR2_X2M_A9TH")) DIVSQRT_XOR2_0(s[0], g8_1t3, h[0]); + + //////////////////////////////////////////////////////////////////////////////////////////////// + //assign h[0:3] = (x[0:3] ^ y[0:3]); //Lvl 1/2 P + tri_xor2 #(.WIDTH(4), .BTR("XOR2_X4M_A9TH")) DIVSQRT_XOR2_00(h[0:3], x[0:3], y[0:3]); + + //assign t_b[1:2] = (~(x[1:2] | y[1:2])); //Lvl 1 P or G ... -KILL + tri_nor2 #(.WIDTH(1), .BTR("NOR2_X4M_A9TH")) DIVSQRT_NOR2_t_b_1(t_b[1], x[1], y[1]); + tri_nor2 #(.WIDTH(1), .BTR("NOR2_X2M_A9TH")) DIVSQRT_NOR2_t_b_2(t_b[2], x[2], y[2]); + + + //assign g_b[1:3] = (~(x[1:3] & y[1:3])); //Lvl 1 G + tri_nand2 #(.WIDTH(1), .BTR("NAND2_X1M_A9TH")) DIVSQRT_NAND2_g_b_1(g_b[1], x[1], y[1]); + tri_nand2 #(.WIDTH(1), .BTR("NAND2_X2M_A9TH")) DIVSQRT_NAND2_g_b_2(g_b[2], x[2], y[2]); + tri_nand2 #(.WIDTH(1), .BTR("NAND2_X4M_A9TH")) DIVSQRT_NAND2_g_b_3(g_b[3], x[3], y[3]); + + + //assign g2_3t3 = (~(g_b[3])); //kogge-stone carry tree + tri_inv #(.WIDTH(1), .BTR("INV_X6M_A9TH")) DIVSQRT_INV_g2_3t3(g2_3t3, g_b[3]); + + + //assign g2_2t3 = (~(g_b[2] & (t_b[2] | g_b[3]))); + tri_oai21 #(.WIDTH(1), .BTR("OAI21_X3M_A9TH")) DIVSQRT_OAI21_g2_2t3(g2_2t3, t_b[2], g_b[3], g_b[2]); + + + //assign g2_1t2 = (~(g_b[1] & (t_b[1] | g_b[2]))); + tri_oai21 #(.WIDTH(1), .BTR("OAI21_X4M_A9TH")) DIVSQRT_OAI21_g2_1t2(g2_1t2, t_b[1], g_b[2], g_b[1]); + + + + //assign t2_1t2 = (~((t_b[1] | t_b[2]))); + tri_nor2 #(.WIDTH(1), .BTR("NOR2_X2M_A9TH")) DIVSQRT_NOR2_t2_1t2(t2_1t2, t_b[1], t_b[2]); + + //assign g4_1t3_b = (~(g2_1t2 | (t2_1t2 & g2_3t3))); + tri_aoi21 #(.WIDTH(1), .BTR("AOI21_X4M_A9TH")) DIVSQRT_AOI21_g4_1t3_b(g4_1t3_b, t2_1t2, g2_3t3, g2_1t2); + + //assign g8_1t3 = (~(g4_1t3_b)); + tri_inv #(.WIDTH(1), .BTR("INV_X6M_A9TH")) DIVSQRT_INV_g8_1t3(g8_1t3, g4_1t3_b); + + + + //assign s[0] = (g8_1t3 ^ h[0]); //output + tri_xor2 #(.WIDTH(1), .BTR("XOR2_X4M_A9TH")) DIVSQRT_XOR2_10(s[0], g8_1t3, h[0]); + + //assign s[1] = (g2_2t3 ^ h[1]); //output + tri_xor2 #(.WIDTH(1), .BTR("XOR2_X4M_A9TH")) DIVSQRT_XOR2_11(s[1], g2_2t3, h[1]); + + //assign s[2] = (g2_3t3 ^ h[2]); //output + tri_xor2 #(.WIDTH(1), .BTR("XOR2_X4M_A9TH")) DIVSQRT_XOR2_12(s[2], g2_3t3, h[2]); + + assign s[3] = (h[3]); //output + +endmodule diff --git a/dev/verilog/work/fu_divsqrt_nq_table.v b/dev/verilog/work/fu_divsqrt_nq_table.v new file mode 100755 index 0000000..2580397 --- /dev/null +++ b/dev/verilog/work/fu_divsqrt_nq_table.v @@ -0,0 +1,64 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +////############################################################################ +////##### NQ Quotient digit selection logic ######### +////############################################################################ + +module fu_divsqrt_nq_table( + x, + nq +); +`include "tri_a2o.vh" + + input [0:3] x; + output nq; + + wire not1111; + wire nq_b; + +//// Implements this table: +// assign exx_nq_bit0 = (exx_sum4 == 4'b1000) ? 1'b1 : +// (exx_sum4 == 4'b1001) ? 1'b1 : +// (exx_sum4 == 4'b1010) ? 1'b1 : +// (exx_sum4 == 4'b1011) ? 1'b1 : +// (exx_sum4 == 4'b1100) ? 1'b1 : +// (exx_sum4 == 4'b1101) ? 1'b1 : +// (exx_sum4 == 4'b1110) ? 1'b1 : +// 1'b0; + + + tri_nand4 #(.WIDTH(1), .BTR("NAND4_X4M_A9TH")) DIVSQRT_NQ_TABLE_NAND4_00(not1111, x[0], x[1], x[2], x[3]); + + tri_nand2 #(.WIDTH(1), .BTR("NAND2_X6A_A9TH")) DIVSQRT_NQ_TABLE_NAND2_00(nq_b, x[0], not1111); + + tri_inv #(.WIDTH(1), .BTR("INV_X11M_A9TH")) DIVSQRT_NQ_TABLE_INV_00(nq, nq_b); + +endmodule diff --git a/dev/verilog/work/fu_divsqrt_q_table.v b/dev/verilog/work/fu_divsqrt_q_table.v new file mode 100755 index 0000000..f796a8c --- /dev/null +++ b/dev/verilog/work/fu_divsqrt_q_table.v @@ -0,0 +1,84 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +////############################################################################ +////##### Q Quotient digit selection logic ####### +////############################################################################ + +module fu_divsqrt_q_table( + x, + cin, + q +); +`include "tri_a2o.vh" + + input [0:3] x; + input cin; + + output q; + + wire nor123; + wire nor123_b; + + wire x0_b; + wire not0and1or2or3_b; + wire nor01; + wire nor23; + wire not0or1or2or3_and_cin_b; + + +//// Implements this table: +// assign exx_q_bit0_prebuf = (exx_sum4 == 4'b0000) ? exx_q_bit0_cin : +// (exx_sum4 == 4'b0001) ? 1'b1 : +// (exx_sum4 == 4'b0010) ? 1'b1 : +// (exx_sum4 == 4'b0011) ? 1'b1 : +// (exx_sum4 == 4'b0100) ? 1'b1 : +// (exx_sum4 == 4'b0101) ? 1'b1 : +// (exx_sum4 == 4'b0110) ? 1'b1 : +// (exx_sum4 == 4'b0111) ? 1'b1 : +// 1'b0; + + + tri_nor3 #(.WIDTH(1), .BTR("NOR3_X4M_A9TH")) DIVSQRT_N_TABLE_NOR3_01(nor123, x[1], x[2], x[3]); + tri_inv #(.WIDTH(1), .BTR("INV_X3M_A9TH")) DIVSQRT_N_TABLE_INV_02a(nor123_b, nor123); + tri_inv #(.WIDTH(1), .BTR("INV_X5B_A9TH")) DIVSQRT_N_TABLE_INV_02b(x0_b, x[0]); + + tri_nand2 #(.WIDTH(1), .BTR("NAND2_X4A_A9TH")) DIVSQRT_N_TABLE_NAND2_03(not0and1or2or3_b, x0_b, nor123_b); +// + tri_nor2 #(.WIDTH(1), .BTR("NOR2_X8B_A9TH")) DIVSQRT_N_TABLE_NOR2_01a(nor01, x[0], x[1]); + tri_nor2 #(.WIDTH(1), .BTR("NOR2_X4B_A9TH")) DIVSQRT_N_TABLE_NOR2_01b(nor23, x[2], x[3]); + + tri_nand3 #(.WIDTH(1), .BTR("NAND3_X6M_A9TH")) DIVSQRT_N_TABLE_NAND3_02(not0or1or2or3_and_cin_b, nor01, nor23, cin); +// + + tri_nand2 #(.WIDTH(1), .BTR("NAND2_X8A_A9TH")) DIVSQRT_N_TABLE_NAND2_04(q, not0or1or2or3_and_cin_b, not0and1or2or3_b); + + +endmodule diff --git a/dev/verilog/work/fu_eie.v b/dev/verilog/work/fu_eie.v new file mode 100755 index 0000000..139b34b --- /dev/null +++ b/dev/verilog/work/fu_eie.v @@ -0,0 +1,739 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + + `include "tri_a2o.vh" + + +module fu_eie( + vdd, + gnd, + clkoff_b, + act_dis, + flush, + delay_lclkr, + mpw1_b, + mpw2_b, + sg_1, + thold_1, + fpu_enable, + nclk, + f_eie_si, + f_eie_so, + ex2_act, + f_byp_eie_ex2_a_expo, + f_byp_eie_ex2_c_expo, + f_byp_eie_ex2_b_expo, + f_pic_ex2_from_integer, + f_pic_ex2_fsel, + f_pic_ex3_frsp_ue1, + f_alg_ex3_sel_byp, + f_fmt_ex3_fsel_bsel, + f_pic_ex3_force_sel_bexp, + f_pic_ex3_sp_b, + f_pic_ex3_math_bzer_b, + f_eie_ex3_tbl_expo, + f_eie_ex3_lt_bias, + f_eie_ex3_eq_bias_m1, + f_eie_ex3_wd_ov, + f_eie_ex3_dw_ov, + f_eie_ex3_wd_ov_if, + f_eie_ex3_dw_ov_if, + f_eie_ex3_lzo_expo, + f_eie_ex3_b_expo, + f_eie_ex3_use_bexp, + f_eie_ex4_iexp +); + + inout vdd; + inout gnd; + input clkoff_b; // tiup + input act_dis; // ??tidn?? + input flush; // ??tidn?? + input [2:3] delay_lclkr; // tidn, + input [2:3] mpw1_b; // tidn, + input [0:0] mpw2_b; // tidn, + input sg_1; + input thold_1; + input fpu_enable; //dc_act + input [0:`NCLK_WIDTH-1] nclk; + + input f_eie_si; // perv + output f_eie_so; // perv + input ex2_act; // act + + input [1:13] f_byp_eie_ex2_a_expo; + input [1:13] f_byp_eie_ex2_c_expo; + input [1:13] f_byp_eie_ex2_b_expo; + + input f_pic_ex2_from_integer; + input f_pic_ex2_fsel; + input f_pic_ex3_frsp_ue1; + + input f_alg_ex3_sel_byp; + input f_fmt_ex3_fsel_bsel; + input f_pic_ex3_force_sel_bexp; + input f_pic_ex3_sp_b; + input f_pic_ex3_math_bzer_b; + + output [1:13] f_eie_ex3_tbl_expo; + + output f_eie_ex3_lt_bias; //f_pic + output f_eie_ex3_eq_bias_m1; //f_pic + output f_eie_ex3_wd_ov; //f_pic + output f_eie_ex3_dw_ov; //f_pic + output f_eie_ex3_wd_ov_if; //f_pic + output f_eie_ex3_dw_ov_if; //f_pic + output [1:13] f_eie_ex3_lzo_expo; //dlza to lzo + output [1:13] f_eie_ex3_b_expo; //dlza to lzo + output f_eie_ex3_use_bexp; + output [1:13] f_eie_ex4_iexp; //deov to lzasub + + // end ports + + // ENTITY + + + parameter tiup = 1'b1; + parameter tidn = 1'b0; + + wire sg_0; + wire thold_0_b; + wire thold_0; + wire force_t; + + + wire ex3_act; + wire [0:3] act_spare_unused; + //----------------- + wire [0:4] act_so; //SCAN + wire [0:4] act_si; //SCAN + wire [0:12] ex3_bop_so; //SCAN + wire [0:12] ex3_bop_si; //SCAN + wire [0:12] ex3_pop_so; //SCAN + wire [0:12] ex3_pop_si; //SCAN + wire [0:6] ex3_ctl_so; //SCAN + wire [0:6] ex3_ctl_si; //SCAN + wire [0:13] ex4_iexp_so; //SCAN + wire [0:13] ex4_iexp_si; //SCAN + //----------------- + wire [1:13] ex2_a_expo; + wire [1:13] ex2_c_expo; + wire [1:13] ex2_b_expo; + wire [1:13] ex2_ep56_sum; + wire [1:12] ex2_ep56_car; + wire [1:13] ex2_ep56_p; + wire [2:12] ex2_ep56_g; + wire [2:11] ex2_ep56_t; + wire [1:13] ex2_ep56_s; + wire [2:12] ex2_ep56_c; + wire [1:13] ex2_p_expo_adj; + wire [1:13] ex2_from_k; + wire [1:13] ex2_b_expo_adj; + wire [1:13] ex3_p_expo; + wire [1:13] ex3_b_expo; + wire [1:13] ex3_iexp; + wire [1:13] ex3_b_expo_adj; + wire [1:13] ex3_p_expo_adj; + wire [1:13] ex4_iexp; + wire ex2_wd_ge_bot; + wire ex2_dw_ge_bot; + wire ex2_ge_2048; + wire ex2_ge_1024; + wire ex2_dw_ge_mid; + wire ex2_wd_ge_mid; + wire ex2_dw_ge; + wire ex2_wd_ge; + wire ex2_dw_eq_top; + wire ex2_wd_eq_bot; + wire ex2_wd_eq; + wire ex2_dw_eq; + wire ex3_iexp_b_sel; + wire ex3_dw_ge; + wire ex3_wd_ge; + wire ex3_wd_eq; + wire ex3_dw_eq; + wire ex3_fsel; + wire ex4_sp_b; + wire [1:13] ex3_b_expo_fixed; //experiment sp_den/dp_fmt + wire ex2_ge_bias; + wire ex2_lt_bias; + wire ex2_eq_bias_m1; + wire ex3_lt_bias; + wire ex3_eq_bias_m1; + wire [2:12] ex2_ep56_g2; + wire [2:10] ex2_ep56_t2; + wire [2:12] ex2_ep56_g4; + wire [2:8] ex2_ep56_t4; + wire [2:12] ex2_ep56_g8; + wire [2:4] ex2_ep56_t8; + + ////############################################ + ////# pervasive + ////############################################ + + + tri_plat thold_reg_0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(flush), + .din(thold_1), + .q(thold_0) + ); + + + tri_plat sg_reg_0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(flush), + .din(sg_1), + .q(sg_0) + ); + + + tri_lcbor lcbor_0( + .clkoff_b(clkoff_b), + .thold(thold_0), + .sg(sg_0), + .act_dis(act_dis), + .force_t(force_t), + .thold_b(thold_0_b) + ); + + ////############################################ + ////# ACT LATCHES + ////############################################ + + tri_rlmreg_p #(.WIDTH(5), .NEEDS_SRESET(0)) act_lat( + .force_t(force_t), //tidn, + .d_mode(tiup), + .delay_lclkr(delay_lclkr[2]), //tidn, + .mpw1_b(mpw1_b[2]), //tidn, + .mpw2_b(mpw2_b[0]), //tidn, + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + .act(fpu_enable), + .scout(act_so), + .scin(act_si), + //----------------- + .din({ act_spare_unused[0], + act_spare_unused[1], + ex2_act, + act_spare_unused[2], + act_spare_unused[3]}), + //----------------- + .dout({ act_spare_unused[0], + act_spare_unused[1], + ex3_act, + act_spare_unused[2], + act_spare_unused[3]}) + ); + + ////############################################## + ////# EX2 latch inputs from rf1 + ////############################################## + + assign ex2_a_expo[1:13] = f_byp_eie_ex2_a_expo[1:13]; + assign ex2_c_expo[1:13] = f_byp_eie_ex2_c_expo[1:13]; + assign ex2_b_expo[1:13] = f_byp_eie_ex2_b_expo[1:13]; + + ////############################################## + ////# EX2 logic + ////############################################## + + ////##------------------------------------------------------------------------- + ////## Product Exponent adder (+56 scouta subtract gives final resutl) + ////##------------------------------------------------------------------------- + // rebiased from 1023 to 4095 ... (append 2 ones) + // ep56 : Ec + Ea -bias + // ep0 : Ec + Ea -bias + 56 = Ec + Ea -4095 + 56 + // + // 0_0011_1111_1111 + // 1_1100_0000_0001 !1023 + 1 = -1023 + // 11_1000 56 + //------------------ + // 1_1100_0011_1001 + Ea + Ec + // + + // ex2_ep56_sum( 0) <= tiup; -- 1 + assign ex2_ep56_sum[1] = (~(ex2_a_expo[1] ^ ex2_c_expo[1])); // 1 + assign ex2_ep56_sum[2] = (~(ex2_a_expo[2] ^ ex2_c_expo[2])); // 1 + assign ex2_ep56_sum[3] = (~(ex2_a_expo[3] ^ ex2_c_expo[3])); // 1 + assign ex2_ep56_sum[4] = (ex2_a_expo[4] ^ ex2_c_expo[4]); // 0 + assign ex2_ep56_sum[5] = (ex2_a_expo[5] ^ ex2_c_expo[5]); // 0 + assign ex2_ep56_sum[6] = (ex2_a_expo[6] ^ ex2_c_expo[6]); // 0 + assign ex2_ep56_sum[7] = (ex2_a_expo[7] ^ ex2_c_expo[7]); // 0 + assign ex2_ep56_sum[8] = (~(ex2_a_expo[8] ^ ex2_c_expo[8])); // 1 + assign ex2_ep56_sum[9] = (~(ex2_a_expo[9] ^ ex2_c_expo[9])); // 1 + assign ex2_ep56_sum[10] = (~(ex2_a_expo[10] ^ ex2_c_expo[10])); // 1 + assign ex2_ep56_sum[11] = (ex2_a_expo[11] ^ ex2_c_expo[11]); // 0 + assign ex2_ep56_sum[12] = (ex2_a_expo[12] ^ ex2_c_expo[12]); // 0 + assign ex2_ep56_sum[13] = (~(ex2_a_expo[13] ^ ex2_c_expo[13])); // 1 + + // ex2_ep56_car( 0) <= ( ex2_a_expo( 1) or ex2_c_expo( 1) ); -- 1 + assign ex2_ep56_car[1] = (ex2_a_expo[2] | ex2_c_expo[2]); // 1 + assign ex2_ep56_car[2] = (ex2_a_expo[3] | ex2_c_expo[3]); // 1 + assign ex2_ep56_car[3] = (ex2_a_expo[4] & ex2_c_expo[4]); // 0 + assign ex2_ep56_car[4] = (ex2_a_expo[5] & ex2_c_expo[5]); // 0 + assign ex2_ep56_car[5] = (ex2_a_expo[6] & ex2_c_expo[6]); // 0 + assign ex2_ep56_car[6] = (ex2_a_expo[7] & ex2_c_expo[7]); // 0 + assign ex2_ep56_car[7] = (ex2_a_expo[8] | ex2_c_expo[8]); // 1 + assign ex2_ep56_car[8] = (ex2_a_expo[9] | ex2_c_expo[9]); // 1 + assign ex2_ep56_car[9] = (ex2_a_expo[10] | ex2_c_expo[10]); // 1 + assign ex2_ep56_car[10] = (ex2_a_expo[11] & ex2_c_expo[11]); // 0 + assign ex2_ep56_car[11] = (ex2_a_expo[12] & ex2_c_expo[12]); // 0 + assign ex2_ep56_car[12] = (ex2_a_expo[13] | ex2_c_expo[13]); // 1 + + assign ex2_ep56_p[1:12] = ex2_ep56_sum[1:12] ^ ex2_ep56_car[1:12]; + assign ex2_ep56_p[13] = ex2_ep56_sum[13]; + assign ex2_ep56_g[2:12] = ex2_ep56_sum[2:12] & ex2_ep56_car[2:12]; + assign ex2_ep56_t[2:11] = ex2_ep56_sum[2:11] | ex2_ep56_car[2:11]; + + assign ex2_ep56_s[1:11] = ex2_ep56_p[1:11] ^ ex2_ep56_c[2:12]; + assign ex2_ep56_s[12] = ex2_ep56_p[12]; + assign ex2_ep56_s[13] = ex2_ep56_p[13]; + + assign ex2_ep56_g2[12] = ex2_ep56_g[12]; + assign ex2_ep56_g2[11] = ex2_ep56_g[11] | (ex2_ep56_t[11] & ex2_ep56_g[12]); + assign ex2_ep56_g2[10] = ex2_ep56_g[10] | (ex2_ep56_t[10] & ex2_ep56_g[11]); + assign ex2_ep56_g2[9] = ex2_ep56_g[9] | (ex2_ep56_t[9] & ex2_ep56_g[10]); + assign ex2_ep56_g2[8] = ex2_ep56_g[8] | (ex2_ep56_t[8] & ex2_ep56_g[9]); + assign ex2_ep56_g2[7] = ex2_ep56_g[7] | (ex2_ep56_t[7] & ex2_ep56_g[8]); + assign ex2_ep56_g2[6] = ex2_ep56_g[6] | (ex2_ep56_t[6] & ex2_ep56_g[7]); + assign ex2_ep56_g2[5] = ex2_ep56_g[5] | (ex2_ep56_t[5] & ex2_ep56_g[6]); + assign ex2_ep56_g2[4] = ex2_ep56_g[4] | (ex2_ep56_t[4] & ex2_ep56_g[5]); + assign ex2_ep56_g2[3] = ex2_ep56_g[3] | (ex2_ep56_t[3] & ex2_ep56_g[4]); + assign ex2_ep56_g2[2] = ex2_ep56_g[2] | (ex2_ep56_t[2] & ex2_ep56_g[3]); + // ex2_ep56_g2( 1) <= ex2_ep56_g( 1) or (ex2_ep56_t( 1) and ex2_ep56_g( 2)) ; + + assign ex2_ep56_t2[10] = (ex2_ep56_t[10] & ex2_ep56_t[11]); + assign ex2_ep56_t2[9] = (ex2_ep56_t[9] & ex2_ep56_t[10]); + assign ex2_ep56_t2[8] = (ex2_ep56_t[8] & ex2_ep56_t[9]); + assign ex2_ep56_t2[7] = (ex2_ep56_t[7] & ex2_ep56_t[8]); + assign ex2_ep56_t2[6] = (ex2_ep56_t[6] & ex2_ep56_t[7]); + assign ex2_ep56_t2[5] = (ex2_ep56_t[5] & ex2_ep56_t[6]); + assign ex2_ep56_t2[4] = (ex2_ep56_t[4] & ex2_ep56_t[5]); + assign ex2_ep56_t2[3] = (ex2_ep56_t[3] & ex2_ep56_t[4]); + assign ex2_ep56_t2[2] = (ex2_ep56_t[2] & ex2_ep56_t[3]); + // ex2_ep56_t2( 1) <= (ex2_ep56_t( 1) and ex2_ep56_t( 2)) ; + + assign ex2_ep56_g4[12] = ex2_ep56_g2[12]; + assign ex2_ep56_g4[11] = ex2_ep56_g2[11]; + assign ex2_ep56_g4[10] = ex2_ep56_g2[10] | (ex2_ep56_t2[10] & ex2_ep56_g2[12]); + assign ex2_ep56_g4[9] = ex2_ep56_g2[9] | (ex2_ep56_t2[9] & ex2_ep56_g2[11]); + assign ex2_ep56_g4[8] = ex2_ep56_g2[8] | (ex2_ep56_t2[8] & ex2_ep56_g2[10]); + assign ex2_ep56_g4[7] = ex2_ep56_g2[7] | (ex2_ep56_t2[7] & ex2_ep56_g2[9]); + assign ex2_ep56_g4[6] = ex2_ep56_g2[6] | (ex2_ep56_t2[6] & ex2_ep56_g2[8]); + assign ex2_ep56_g4[5] = ex2_ep56_g2[5] | (ex2_ep56_t2[5] & ex2_ep56_g2[7]); + assign ex2_ep56_g4[4] = ex2_ep56_g2[4] | (ex2_ep56_t2[4] & ex2_ep56_g2[6]); + assign ex2_ep56_g4[3] = ex2_ep56_g2[3] | (ex2_ep56_t2[3] & ex2_ep56_g2[5]); + assign ex2_ep56_g4[2] = ex2_ep56_g2[2] | (ex2_ep56_t2[2] & ex2_ep56_g2[4]); + // ex2_ep56_g4( 1) <= ex2_ep56_g2( 1) or (ex2_ep56_t2( 1) and ex2_ep56_g2( 3)) ; + + assign ex2_ep56_t4[8] = (ex2_ep56_t2[8] & ex2_ep56_t2[10]); + assign ex2_ep56_t4[7] = (ex2_ep56_t2[7] & ex2_ep56_t2[9]); + assign ex2_ep56_t4[6] = (ex2_ep56_t2[6] & ex2_ep56_t2[8]); + assign ex2_ep56_t4[5] = (ex2_ep56_t2[5] & ex2_ep56_t2[7]); + assign ex2_ep56_t4[4] = (ex2_ep56_t2[4] & ex2_ep56_t2[6]); + assign ex2_ep56_t4[3] = (ex2_ep56_t2[3] & ex2_ep56_t2[5]); + assign ex2_ep56_t4[2] = (ex2_ep56_t2[2] & ex2_ep56_t2[4]); + // ex2_ep56_t4( 1) <= (ex2_ep56_t2( 1) and ex2_ep56_t2( 3)) ; + + assign ex2_ep56_g8[12] = ex2_ep56_g4[12]; + assign ex2_ep56_g8[11] = ex2_ep56_g4[11]; + assign ex2_ep56_g8[10] = ex2_ep56_g4[10]; + assign ex2_ep56_g8[9] = ex2_ep56_g4[9]; + assign ex2_ep56_g8[8] = ex2_ep56_g4[8] | (ex2_ep56_t4[8] & ex2_ep56_g4[12]); + assign ex2_ep56_g8[7] = ex2_ep56_g4[7] | (ex2_ep56_t4[7] & ex2_ep56_g4[11]); + assign ex2_ep56_g8[6] = ex2_ep56_g4[6] | (ex2_ep56_t4[6] & ex2_ep56_g4[10]); + assign ex2_ep56_g8[5] = ex2_ep56_g4[5] | (ex2_ep56_t4[5] & ex2_ep56_g4[9]); + assign ex2_ep56_g8[4] = ex2_ep56_g4[4] | (ex2_ep56_t4[4] & ex2_ep56_g4[8]); + assign ex2_ep56_g8[3] = ex2_ep56_g4[3] | (ex2_ep56_t4[3] & ex2_ep56_g4[7]); + assign ex2_ep56_g8[2] = ex2_ep56_g4[2] | (ex2_ep56_t4[2] & ex2_ep56_g4[6]); + // ex2_ep56_g8( 1) <= ex2_ep56_g4( 1) or (ex2_ep56_t4( 1) and ex2_ep56_g4( 5)) ; + + assign ex2_ep56_t8[4] = (ex2_ep56_t4[4] & ex2_ep56_t4[8]); + assign ex2_ep56_t8[3] = (ex2_ep56_t4[3] & ex2_ep56_t4[7]); + assign ex2_ep56_t8[2] = (ex2_ep56_t4[2] & ex2_ep56_t4[6]); + // ex2_ep56_t8( 1) <= (ex2_ep56_t4( 1) and ex2_ep56_t4( 5)) ; + + assign ex2_ep56_c[12] = ex2_ep56_g8[12]; + assign ex2_ep56_c[11] = ex2_ep56_g8[11]; + assign ex2_ep56_c[10] = ex2_ep56_g8[10]; + assign ex2_ep56_c[9] = ex2_ep56_g8[9]; + assign ex2_ep56_c[8] = ex2_ep56_g8[8]; + assign ex2_ep56_c[7] = ex2_ep56_g8[7]; + assign ex2_ep56_c[6] = ex2_ep56_g8[6]; + assign ex2_ep56_c[5] = ex2_ep56_g8[5]; + assign ex2_ep56_c[4] = ex2_ep56_g8[4] | (ex2_ep56_t8[4] & ex2_ep56_g8[12]); + assign ex2_ep56_c[3] = ex2_ep56_g8[3] | (ex2_ep56_t8[3] & ex2_ep56_g8[11]); + assign ex2_ep56_c[2] = ex2_ep56_g8[2] | (ex2_ep56_t8[2] & ex2_ep56_g8[10]); + // ex2_ep56_c( 1) <= ex2_ep56_g8( 1) or (ex2_ep56_t8( 1) and ex2_ep56_g8( 9)) ; + + ////##--------------------------------------- + ////## hold onto c_exponent for fsel + ////##--------------------------------------- + + assign ex2_p_expo_adj[1:13] = (ex2_ep56_s[1:13] & {13{(~f_pic_ex2_fsel)}}) | + (ex2_c_expo[1:13] & {13{f_pic_ex2_fsel}}); + + ////##--------------------------------------- + ////## select b exponent + ////##--------------------------------------- + + // From integer exponent + // lsb is at position 162, and value = bias + // therefore set b_expo to (bias+162) + // 0_1111_1111_1111 1023 = bias + // 101_0010 162 + // ---------------- ---- + // 1_0000_0101_0001 4096+57 + // 1 2345 6789 0123 + + assign ex2_from_k[1] = tidn; // 4096 + assign ex2_from_k[2] = tidn; // 2048 + assign ex2_from_k[3] = tiup; // 1024 + assign ex2_from_k[4] = tidn; // 512 + assign ex2_from_k[5] = tidn; // 256 + assign ex2_from_k[6] = tiup; // 128 + assign ex2_from_k[7] = tidn; // 64 + assign ex2_from_k[8] = tiup; // 32 + assign ex2_from_k[9] = tidn; // 16 + assign ex2_from_k[10] = tidn; // 8 + assign ex2_from_k[11] = tidn; // 4 + assign ex2_from_k[12] = tidn; // 2 + assign ex2_from_k[13] = tiup; // 1 + + assign ex2_b_expo_adj[1:13] = (ex2_from_k[1:13] & {13{f_pic_ex2_from_integer}}) | + (ex2_b_expo[1:13] & {13{(~f_pic_ex2_from_integer)}}); + + ////##--------------------------------------- + ////## to integer overflow boundaries + ////##--------------------------------------- + // convert to signed_word: + // pos int ov ge 2**31 1023+31 + // ov eq 2**30 * rnd_up 1023+30 <= just look at final MSB position + // neg int ov gt 2**31 1023+31 + // neg int ov eq 2**31 1023+31 & frac[1:*] != 0 + + // convert to signed_doubleword: + // pos int ov ge 2**63 1023+63 1086 + // ov eq 2**62 * rnd_up 1023+62 1085 <=== just look at final msb position + // neg int ov gt 2**63 1023+63 1086 + // neg int ov eq 2**63 1023+63 1086 & frac[1:*] != 0; + // + // 0_0011_1111_1111 bias 1023 + // 10_0000 32 + // 0_0100 0001 1111 <=== ge + // + // 0_0011_1111_1111 bias 1023 + // 1_1111 31 + // 0_0100 0001 1110 <=== eq + // + // 0_0011_1111_1111 bias 1023 + // 100_0000 64 + // 0_0100 0011 1111 <==== ge 1087 + // + // 0_0011_1111_1111 bias 1023 + // 11_1111 63 + // 0_0100 0011 1110 <==== eq 1086 + // + // 1111 + // 1 2345 6789 0123 + // + // if exponent less than bias (1023) + // positive input if +rnd_up result = +ulp (ok) int 1 + // positive input if -rnd_up result = +0 (ok) int 0 + // negative input if +rnd_up result = -ulp (ok) int -1 (no increment) + // negative input if -rnd_up result = +0 <== ??force sign?? + // normalizer shifts wrong (98)=1 + + assign ex2_wd_ge_bot = ex2_b_expo[9] & ex2_b_expo[10] & ex2_b_expo[11] & ex2_b_expo[12] & ex2_b_expo[13]; + + assign ex2_dw_ge_bot = ex2_b_expo[8] & ex2_wd_ge_bot; + + assign ex2_ge_2048 = (~ex2_b_expo[1]) & ex2_b_expo[2]; + assign ex2_ge_1024 = (~ex2_b_expo[1]) & ex2_b_expo[3]; + + assign ex2_dw_ge_mid = ex2_b_expo[4] | ex2_b_expo[5] | ex2_b_expo[6] | ex2_b_expo[7]; + + assign ex2_wd_ge_mid = ex2_b_expo[8] | ex2_dw_ge_mid; + + assign ex2_dw_ge = (ex2_ge_2048) | (ex2_ge_1024 & ex2_dw_ge_mid) | (ex2_ge_1024 & ex2_dw_ge_bot); + + assign ex2_wd_ge = (ex2_ge_2048) | (ex2_ge_1024 & ex2_wd_ge_mid) | (ex2_ge_1024 & ex2_wd_ge_bot); + + assign ex2_dw_eq_top = (~ex2_b_expo[1]) & (~ex2_b_expo[2]) & ex2_b_expo[3] & (~ex2_b_expo[4]) & (~ex2_b_expo[5]) & (~ex2_b_expo[6]) & (~ex2_b_expo[7]); + + assign ex2_wd_eq_bot = ex2_b_expo[9] & ex2_b_expo[10] & ex2_b_expo[11] & ex2_b_expo[12] & (~ex2_b_expo[13]); + + assign ex2_wd_eq = ex2_dw_eq_top & (~ex2_b_expo[8]) & ex2_wd_eq_bot; + + assign ex2_dw_eq = ex2_dw_eq_top & ex2_b_expo[8] & ex2_wd_eq_bot; + + assign ex2_ge_bias = ((~ex2_b_expo[1]) & ex2_b_expo[2]) | ((~ex2_b_expo[1]) & ex2_b_expo[3]) | ((~ex2_b_expo[1]) & ex2_b_expo[4] & ex2_b_expo[5] & ex2_b_expo[6] & ex2_b_expo[7] & ex2_b_expo[8] & ex2_b_expo[9] & ex2_b_expo[10] & ex2_b_expo[11] & ex2_b_expo[12] & ex2_b_expo[13]); // for rnd_to_int + + assign ex2_lt_bias = (~ex2_ge_bias); + // rnd-to-int nearest rounds up + // sign + // 2048 + // 1024 + // 512 + // 256 + // 128 + // 64 + // 32 + // 16 + // 8 + // 4 + assign ex2_eq_bias_m1 = (~ex2_b_expo[1]) & (~ex2_b_expo[2]) & (~ex2_b_expo[3]) & ex2_b_expo[4] & ex2_b_expo[5] & ex2_b_expo[6] & ex2_b_expo[7] & ex2_b_expo[8] & ex2_b_expo[9] & ex2_b_expo[10] & ex2_b_expo[11] & ex2_b_expo[12] & (~ex2_b_expo[13]); // 2 + // 1 + + ////############################################## + ////# EX3 latches + ////############################################## + + + tri_rlmreg_p #(.WIDTH(13), .NEEDS_SRESET(0)) ex3_bop_lat( + .force_t(force_t), //tidn, + .d_mode(tiup), // + .delay_lclkr(delay_lclkr[2]), //tidn, + .mpw1_b(mpw1_b[2]), //tidn, + .mpw2_b(mpw2_b[0]), //tidn, + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + .act(ex2_act), + .scout(ex3_bop_so), + .scin(ex3_bop_si), + //----------------- + .din(ex2_b_expo_adj[1:13]), + .dout(ex3_b_expo_adj[1:13]) //LAT-- + ); + + + tri_rlmreg_p #(.WIDTH(13), .NEEDS_SRESET(0)) ex3_pop_lat( + .force_t(force_t), //tidn, + .d_mode(tiup), + .delay_lclkr(delay_lclkr[2]), //tidn, + .mpw1_b(mpw1_b[2]), //tidn, + .mpw2_b(mpw2_b[0]), //tidn, + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + .act(ex2_act), + .scout(ex3_pop_so), + .scin(ex3_pop_si), + //----------------- + .din(ex2_p_expo_adj[1:13]), + .dout(ex3_p_expo_adj[1:13]) //LAT-- + ); + + + tri_rlmreg_p #(.WIDTH(7), .NEEDS_SRESET(0)) ex3_ctl_lat( + .force_t(force_t), //tidn, + .d_mode(tiup), + .delay_lclkr(delay_lclkr[2]), //tidn, + .mpw1_b(mpw1_b[2]), //tidn, + .mpw2_b(mpw2_b[0]), //tidn, + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + .act(ex2_act), + .scout(ex3_ctl_so), + .scin(ex3_ctl_si), + //----------------- + .din({ ex2_dw_ge, + ex2_wd_ge, + ex2_wd_eq, + ex2_dw_eq, + f_pic_ex2_fsel, + ex2_lt_bias, + ex2_eq_bias_m1}), + //----------------- + .dout({ex3_dw_ge, //LAT-- + ex3_wd_ge, //LAT-- + ex3_wd_eq, //LAT-- + ex3_dw_eq, //LAT-- + ex3_fsel, //LAT-- + ex3_lt_bias, //LAT-- + ex3_eq_bias_m1}) //LAT-- + ); + + assign f_eie_ex3_lt_bias = ex3_lt_bias; //output --f_pic + assign f_eie_ex3_eq_bias_m1 = ex3_eq_bias_m1; //output --f_pic + + assign ex3_p_expo[1:13] = ex3_p_expo_adj[1:13]; + assign ex3_b_expo[1:13] = ex3_b_expo_adj[1:13]; + + assign f_eie_ex3_wd_ov = ex3_wd_ge; //output --f_pic + assign f_eie_ex3_dw_ov = ex3_dw_ge; //output --f_pic + assign f_eie_ex3_wd_ov_if = ex3_wd_eq; //output --f_pic + assign f_eie_ex3_dw_ov_if = ex3_dw_eq; //output --f_pic + + assign f_eie_ex3_lzo_expo[1:13] = ex3_p_expo_adj[1:13]; //output --dlza for lzo + assign f_eie_ex3_b_expo[1:13] = ex3_b_expo[1:13]; + assign f_eie_ex3_tbl_expo[1:13] = ex3_b_expo[1:13]; + ////############################################## + ////# EX3 logic + ////############################################## + + // --++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + // --experiment sp_den/dp_fmt + // -- experimental -- (add 24 for bypass B cases) shift 24 positions to avoid shift right + // -- SP_den in DP format is normalized, but SP op must give denorm result. + // -- do not want to shift right in normalizer, scoutdent in aligner. + // -- ?? problem: LZO positions for bypass case : + // -- UE=0: set LZO 24 instead of LZO 0 .... ??? can [0:23] be an alias ??? + // -- UE=1: always normalize, LZO does not matter + // -- + // -- (changed from 24 to 26) for the offset + // + // + // ex3_bexp26(13) <= ex3_b_expo(13); -- 0001 + // ex3_bexp26(12) <= not ex3_b_expo(12); -- 0002 + // ex3_bexp26(11) <= ex3_b_expo(11) xor ex3_bexp26_c(12); -- 0004 + // ex3_bexp26(10) <= not ex3_b_expo(10) xor ex3_bexp26_c(11) ; -- 0008 + // ex3_bexp26(9) <= not ex3_b_expo(9) xor ex3_bexp26_c(10); -- 0016 + // ex3_bexp26(1 to 8) <= ex3_b_expo(1 to 8) xor ex3_bexp26_c(2 to 9) ; -- 0032 ... + // + // ex3_bexpo26_9_o_10 <= ex3_b_expo(9) or ex3_b_expo(10) ; + // + // ex3_bexp26_c(12) <= ex3_b_expo(12); + // ex3_bexp26_c(11) <= ex3_b_expo(11) and ex3_b_expo(12); + // ex3_bexp26_c(10) <= ex3_b_expo(10) or (ex3_b_expo(11) and ex3_b_expo(12) ); + // ex3_bexp26_c(9) <= ex3_bexpo26_9_o_10 or (ex3_b_expo(11) and ex3_b_expo(12) ); + // ex3_bexp26_c(8) <= ex3_bexp26_gg(8) and ex3_bexp26_c(9); + // ex3_bexp26_c(7) <= ex3_bexp26_gg(7) and ex3_bexp26_c(9); + // ex3_bexp26_c(6) <= ex3_bexp26_gg(6) and ex3_bexp26_c(9); + // ex3_bexp26_c(5) <= ex3_bexp26_gg(5) and ex3_bexp26_c(9); + // ex3_bexp26_c(4) <= ex3_bexp26_gg(4) and ex3_bexp26_c(9); + // ex3_bexp26_c(3) <= ex3_bexp26_gg(3) and ex3_bexp26_c(9); + // ex3_bexp26_c(2) <= ex3_bexp26_gg(2) and ex3_bexp26_c(9); + // + // ex3_bexp26_gg2(8) <= ex3_b_expo(8) ; + // ex3_bexp26_gg2(7) <= ex3_b_expo(7) and ex3_b_expo(8) ; + // ex3_bexp26_gg2(6) <= ex3_b_expo(6) and ex3_b_expo(7) ; + // ex3_bexp26_gg2(5) <= ex3_b_expo(5) and ex3_b_expo(6) ; + // ex3_bexp26_gg2(4) <= ex3_b_expo(4) and ex3_b_expo(5) ; + // ex3_bexp26_gg2(3) <= ex3_b_expo(3) and ex3_b_expo(4) ; + // ex3_bexp26_gg2(2) <= ex3_b_expo(2) and ex3_b_expo(3) ; + // + // ex3_bexp26_gg4(8) <= ex3_bexp26_gg2(8) ; + // ex3_bexp26_gg4(7) <= ex3_bexp26_gg2(7) ; + // ex3_bexp26_gg4(6) <= ex3_bexp26_gg2(6) and ex3_bexp26_gg2(8) ; + // ex3_bexp26_gg4(5) <= ex3_bexp26_gg2(5) and ex3_bexp26_gg2(7) ; + // ex3_bexp26_gg4(4) <= ex3_bexp26_gg2(4) and ex3_bexp26_gg2(6) ; + // ex3_bexp26_gg4(3) <= ex3_bexp26_gg2(3) and ex3_bexp26_gg2(5) ; + // ex3_bexp26_gg4(2) <= ex3_bexp26_gg2(2) and ex3_bexp26_gg2(4) ; + // + // ex3_bexp26_gg(8) <= ex3_bexp26_gg4(8) ; + // ex3_bexp26_gg(7) <= ex3_bexp26_gg4(7) ; + // ex3_bexp26_gg(6) <= ex3_bexp26_gg4(6) ; + // ex3_bexp26_gg(5) <= ex3_bexp26_gg4(5) ; + // ex3_bexp26_gg(4) <= ex3_bexp26_gg4(4) and ex3_bexp26_gg4(8) ; + // ex3_bexp26_gg(3) <= ex3_bexp26_gg4(3) and ex3_bexp26_gg4(7) ; + // ex3_bexp26_gg(2) <= ex3_bexp26_gg4(2) and ex3_bexp26_gg4(6) ; + // + // + // + // ex3_b_expo_fixed(1 to 13) <= --experiment sp_den/dp_fmt + // ( ex3_b_expo(1 to 13) and (1 to 13 => f_pic_ex3_sp_b) ) or -- DP --experiment sp_den/dp_fmt + // ( ex3_bexp26(1 to 13) and (1 to 13 => not f_pic_ex3_sp_b) ) ; -- SP --experiment sp_den/dp_fmt + // --++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + + assign ex3_b_expo_fixed[1:13] = ex3_b_expo[1:13]; + + assign f_eie_ex3_use_bexp = ex3_iexp_b_sel; + + //NAN/shOv + // fsel + assign ex3_iexp_b_sel = (f_alg_ex3_sel_byp & (~ex3_fsel) & f_pic_ex3_math_bzer_b) | f_fmt_ex3_fsel_bsel | f_pic_ex3_force_sel_bexp | f_pic_ex3_frsp_ue1; // by opcode + // frsp with ue=1 always does bypass because must normalize anyway + // if frsp(ue=1) has a shift unf, then loose bits and canot normalize) + + assign ex3_iexp[1:13] = (ex3_b_expo_fixed[1:13] & {13{ex3_iexp_b_sel}}) | + (ex3_p_expo[1:13] & {13{(~ex3_iexp_b_sel)}}); //experiment sp_den/dp_fmt + + ////############################################## + ////# EX4 latches + ////############################################## + + + tri_rlmreg_p #(.WIDTH(14), .NEEDS_SRESET(0)) ex4_iexp_lat( + .force_t(force_t), //tidn, + .d_mode(tiup), + .delay_lclkr(delay_lclkr[3]), //tidn, + .mpw1_b(mpw1_b[3]), //tidn, + .mpw2_b(mpw2_b[0]), //tidn, + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + .act(ex3_act), + .scout(ex4_iexp_so), + .scin(ex4_iexp_si), + //----------------- + .din({f_pic_ex3_sp_b, + ex3_iexp[1:13]}), + //----------------- + .dout({ex4_sp_b, //LAT-- + ex4_iexp[1:13]}) //LAT-- + ); + + assign f_eie_ex4_iexp[1:13] = ex4_iexp[1:13]; //output--feov + + ////############################################## + ////# EX4 logic + ////############################################## + + ////############################################ + ////# scan + ////############################################ + + assign ex3_bop_si[0:12] = {ex3_bop_so[1:12], f_eie_si}; + assign ex3_pop_si[0:12] = {ex3_pop_so[1:12], ex3_bop_so[0]}; + assign ex3_ctl_si[0:6] = {ex3_ctl_so[1:6], ex3_pop_so[0]}; + assign ex4_iexp_si[0:13] = {ex4_iexp_so[1:13], ex3_ctl_so[0]}; + assign act_si[0:4] = {act_so[1:4], ex4_iexp_so[0]}; + assign f_eie_so = act_so[0]; + +endmodule diff --git a/dev/verilog/work/fu_eov.v b/dev/verilog/work/fu_eov.v new file mode 100755 index 0000000..703fb22 --- /dev/null +++ b/dev/verilog/work/fu_eov.v @@ -0,0 +1,1134 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" + +module fu_eov( + vdd, + gnd, + clkoff_b, + act_dis, + flush, + delay_lclkr, + mpw1_b, + mpw2_b, + sg_1, + thold_1, + fpu_enable, + nclk, + f_eov_si, + f_eov_so, + ex3_act_b, + f_tbl_ex5_unf_expo, + f_tbe_ex4_may_ov, + f_tbe_ex4_expo, + f_pic_ex4_sel_est, + f_eie_ex4_iexp, + f_pic_ex4_sp_b, + f_pic_ex5_oe, + f_pic_ex5_ue, + f_pic_ex5_ov_en, + f_pic_ex5_uf_en, + f_pic_ex5_spec_sel_k_e, + f_pic_ex5_spec_sel_k_f, + f_pic_ex5_sel_ov_spec, + f_pic_ex5_to_int_ov_all, + f_lza_ex5_sh_rgt_en_eov, + f_lza_ex5_lza_amt_eov, + f_lza_ex5_no_lza_edge, + f_nrm_ex5_extra_shift, + f_eov_ex5_may_ovf, + f_eov_ex6_sel_k_f, + f_eov_ex6_sel_k_e, + f_eov_ex6_sel_kif_f, + f_eov_ex6_sel_kif_e, + f_eov_ex6_unf_expo, + f_eov_ex6_ovf_expo, + f_eov_ex6_ovf_if_expo, + f_eov_ex6_expo_p0, + f_eov_ex6_expo_p1, + f_eov_ex6_expo_p0_ue1oe1, + f_eov_ex6_expo_p1_ue1oe1 +); + parameter expand_type = 2; // 0 - ibm tech, 1 - other ); + + inout vdd; + inout gnd; + input clkoff_b; // tiup + input act_dis; // ??tidn?? + input flush; // ??tidn?? + input [4:5] delay_lclkr; // tidn, + input [4:5] mpw1_b; // tidn, + input [0:1] mpw2_b; // tidn, + input sg_1; + input thold_1; + input fpu_enable; //dc_act + input [0:`NCLK_WIDTH-1] nclk; + + input f_eov_si; // perv + output f_eov_so; // perv + input ex3_act_b; // act + + input f_tbl_ex5_unf_expo; + input f_tbe_ex4_may_ov; + input [1:13] f_tbe_ex4_expo; + input f_pic_ex4_sel_est; + input [1:13] f_eie_ex4_iexp; + + input f_pic_ex4_sp_b; + input f_pic_ex5_oe; + input f_pic_ex5_ue; + input f_pic_ex5_ov_en; + input f_pic_ex5_uf_en; + input f_pic_ex5_spec_sel_k_e; + input f_pic_ex5_spec_sel_k_f; + input f_pic_ex5_sel_ov_spec; + input f_pic_ex5_to_int_ov_all; + + input f_lza_ex5_sh_rgt_en_eov; + input [0:7] f_lza_ex5_lza_amt_eov; + input f_lza_ex5_no_lza_edge; + input f_nrm_ex5_extra_shift; + output f_eov_ex5_may_ovf; ////#pic generate constant + + output f_eov_ex6_sel_k_f; ////#rnd + output f_eov_ex6_sel_k_e; ////#rnd + output f_eov_ex6_sel_kif_f; ////#rnd + output f_eov_ex6_sel_kif_e; ////#rnd + output f_eov_ex6_unf_expo; ////#rnd for ux + output f_eov_ex6_ovf_expo; ////#rnd for INF,ox + output f_eov_ex6_ovf_if_expo; ////#rnd for INF,ox + output [1:13] f_eov_ex6_expo_p0; ////#rnd result exponent + output [1:13] f_eov_ex6_expo_p1; ////#rnd result exponent if rnd_up_all1 + output [3:7] f_eov_ex6_expo_p0_ue1oe1; ////#rnd + output [3:7] f_eov_ex6_expo_p1_ue1oe1; ////#rnd + + // end ports + + // ENTITY + + + parameter tiup = 1'b1; + parameter tidn = 1'b0; + + wire sg_0; + wire thold_0_b; + wire thold_0; + wire force_t; + wire ex4_act; + wire ex3_act; + wire ex5_act; + (* analysis_not_referenced="TRUE" *) // unused + wire [0:2] act_spare_unused; + //----------------- + wire [0:4] act_so; //SCAN + wire [0:4] act_si; //SCAN + wire [0:15] ex5_iexp_so; //SCAN + wire [0:15] ex5_iexp_si; //SCAN + wire [0:2] ex6_ovctl_so; //SCAN + wire [0:2] ex6_ovctl_si; //SCAN + wire [0:12] ex6_misc_so; //SCAN + wire [0:12] ex6_misc_si; //SCAN + wire [0:12] ex6_urnd0_so; //SCAN + wire [0:12] ex6_urnd0_si; //SCAN + wire [0:12] ex6_urnd1_so; //SCAN + wire [0:12] ex6_urnd1_si; //SCAN + //----------------- + wire ex5_sp; + wire ex5_unf_m1_co12; + wire ex5_unf_p0_co12; + wire ex5_ovf_m1_co12; + wire ex5_ovf_p0_co12; + wire ex5_ovf_p1_co12; + wire ex5_ovf_m1; + wire ex5_ovf_p0; + wire ex5_ovf_p1; + wire ex5_unf_m1; + wire ex5_unf_p0; + wire [1:13] ex5_i_exp; + wire [3:7] ex5_ue1oe1_k; + wire [1:13] ex5_lzasub_sum; + wire [1:12] ex5_lzasub_car; + wire [1:12] ex5_lzasub_p; + wire [2:12] ex5_lzasub_t; + wire [2:12] ex5_lzasub_g; + wire [1:13] ex5_lzasub_m1; + wire [1:13] ex5_lzasub_p0; + wire [1:13] ex5_lzasub_p1; + wire [2:11] ex5_lzasub_c0; + wire [2:11] ex5_lzasub_c1; + wire [1:11] ex5_lzasub_s0; + wire [1:11] ex5_lzasub_s1; + wire [1:13] ex5_ovf_sum; + wire [1:12] ex5_ovf_car; + wire [2:12] ex5_ovf_g; + wire [2:12] ex5_ovf_t; + wire [1:1] ex5_ovf_p; + wire [1:13] ex5_unf_sum; + wire [1:12] ex5_unf_car; + wire [2:12] ex5_unf_g; + wire [2:12] ex5_unf_t; + wire [1:1] ex5_unf_p; + wire ex5_unf_ci0_02t11; + wire ex5_unf_ci1_02t11; + wire [1:13] ex5_expo_p0; + wire [1:13] ex5_expo_p1; + wire [1:13] ex6_expo_p0; + wire [1:13] ex6_expo_p1; + wire [3:7] ex6_ue1oe1_k; + wire [3:7] ex6_ue1oe1_p0_p; + wire [4:6] ex6_ue1oe1_p0_t; + wire [4:7] ex6_ue1oe1_p0_g; + wire [4:7] ex6_ue1oe1_p0_c; + wire [3:7] ex6_ue1oe1_p1_p; + wire [4:6] ex6_ue1oe1_p1_t; + wire [4:7] ex6_ue1oe1_p1_g; + wire [4:7] ex6_ue1oe1_p1_c; + wire ex5_lzasub_m1_c12; + wire ex5_lzasub_p0_c12; + wire ex5_lzasub_p1_c12; + wire ex5_may_ovf; + wire [0:7] ex5_lza_amt_b; + wire [0:7] ex5_lza_amt; + wire [1:13] ex4_iexp; + wire ex4_sp; + wire ex4_may_ovf; + wire ex5_unf_c2_m1; + wire ex5_unf_c2_p0; + wire ex5_c2_m1; + wire ex5_c2_p0; + wire ex5_c2_p1; + wire [4:7] ex6_ue1oe1_p0_g2_b; + wire [4:5] ex6_ue1oe1_p0_t2_b; + wire [4:7] ex6_ue1oe1_p1_g2_b; + wire [4:5] ex6_ue1oe1_p1_t2_b; + wire ex5_unf_g2_02t03; + wire ex5_unf_g2_04t05; + wire ex5_unf_g2_06t07; + wire ex5_unf_g2_08t09; + wire ex5_unf_g2_10t11; + wire ex5_unf_ci0_g2; + wire ex5_unf_ci1_g2; + wire ex5_unf_t2_02t03; + wire ex5_unf_t2_04t05; + wire ex5_unf_t2_06t07; + wire ex5_unf_t2_08t09; + wire ex5_unf_t2_10t11; + wire ex5_unf_g4_02t05; + wire ex5_unf_g4_06t09; + wire ex5_unf_ci0_g4; + wire ex5_unf_ci1_g4; + wire ex5_unf_t4_02t05; + wire ex5_unf_t4_06t09; + wire ex5_unf_g8_02t09; + wire ex5_unf_ci0_g8; + wire ex5_unf_ci1_g8; + wire ex5_unf_t8_02t09; + + wire ex5_ovf_ci0_02t11; + wire ex5_ovf_ci1_02t11; + + wire ex5_ovf_g2_02t03; + wire ex5_ovf_g2_04t05; + wire ex5_ovf_g2_06t07; + wire ex5_ovf_g2_08t09; + wire ex5_ovf_g2_ci0; + wire ex5_ovf_g2_ci1; + wire ex5_ovf_t2_02t03; + wire ex5_ovf_t2_04t05; + wire ex5_ovf_t2_06t07; + wire ex5_ovf_t2_08t09; + wire ex5_ovf_g4_02t05; + wire ex5_ovf_g4_06t09; + wire ex5_ovf_g4_ci0; + wire ex5_ovf_g4_ci1; + wire ex5_ovf_t4_02t05; + wire ex5_ovf_t4_06t09; + wire ex5_ovf_g8_02t09; + wire ex5_ovf_g8_ci0; + wire ex5_ovf_g8_ci1; + wire ex5_ovf_t8_02t09; + + wire [2:11] ex5_lzasub_gg02; + wire [2:11] ex5_lzasub_gt02; + wire [2:11] ex5_lzasub_gg04; + wire [2:11] ex5_lzasub_gt04; + wire [2:11] ex5_lzasub_gg08; + wire [2:11] ex5_lzasub_gt08; + wire ex5_sh_rgt_en_b; + + wire ex4_may_ov_usual; + + wire ex5_ovf_calc; + wire ex5_ovf_if_calc; + wire ex5_unf_calc; + wire ex5_unf_tbl; + wire ex5_unf_tbl_spec_e; + wire ex5_ov_en; + wire ex5_ov_en_oe0; + wire ex5_sel_ov_spec; + wire ex5_unf_en_nedge; + wire ex5_unf_ue0_nestsp; + wire ex5_sel_k_part_f; + wire ex5_sel_k_part_e; + wire ex6_ovf_calc; + wire ex6_ovf_if_calc; + wire ex6_unf_calc; + wire ex6_unf_tbl; + wire ex6_unf_tbl_b; + wire ex6_unf_tbl_spec_e; + wire ex6_ov_en; + wire ex6_ov_en_oe0; + wire ex6_sel_ov_spec; + wire ex6_unf_en_nedge; + wire ex6_unf_ue0_nestsp; + wire ex6_sel_k_part_f; + wire ex6_sel_ov_spec_b; + wire ex6_ovf_b; + wire ex6_ovf_if_b; + wire ex6_ovf_oe0_b; + wire ex6_ovf_if_oe0_b; + wire ex6_unf_b; + wire ex6_unf_ue0_b; + wire ex6_sel_k_part_f_b; + wire ex6_unf_tbl_spec_e_b; + wire ex5_sel_est; + wire ex5_est_sp; + + wire [1:13] ex5_expo_p0_0_b; + wire [1:13] ex5_expo_p0_1_b; + wire [1:13] ex5_expo_p1_0_b; + wire [1:13] ex5_expo_p1_1_b; + wire ex5_ovf_calc_0_b; + wire ex5_ovf_calc_1_b; + wire ex5_ovf_if_calc_0_b; + wire ex5_ovf_if_calc_1_b; + wire ex5_unf_calc_0_b; + wire ex5_unf_calc_1_b; + wire ex6_d1clk; + wire ex6_d2clk; + wire [0:`NCLK_WIDTH-1] ex6_lclk; + (* analysis_not_referenced="TRUE" *) // unused + wire unused; + + assign unused = |(ex5_expo_p0[1:13]) | |(ex5_expo_p1[1:13]) | ex5_ovf_calc | ex5_ovf_if_calc | ex5_unf_calc; + + ////############################################ + ////# pervasive + ////############################################ + + + tri_plat thold_reg_0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(flush), + .din(thold_1), + .q(thold_0) + ); + + + tri_plat sg_reg_0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(flush), + .din(sg_1), + .q(sg_0) + ); + + + tri_lcbor lcbor_0( + .clkoff_b(clkoff_b), + .thold(thold_0), + .sg(sg_0), + .act_dis(act_dis), + .force_t(force_t), + .thold_b(thold_0_b) + ); + + tri_lcbnd ex6_lcb( + .delay_lclkr(delay_lclkr[5]), // tidn + .mpw1_b(mpw1_b[5]), // tidn + .mpw2_b(mpw2_b[1]), // tidn + .force_t(force_t), // tidn + .nclk(nclk), //in + .vd(vdd), //inout + .gd(gnd), //inout + .act(ex5_act), //in + .sg(sg_0), //in + .thold_b(thold_0_b), //in + .d1clk(ex6_d1clk), //out + .d2clk(ex6_d2clk), //out + .lclk(ex6_lclk) //out + ); + + ////############################################ + ////# ACT LATCHES + ////############################################ + + assign ex3_act = (~ex3_act_b); + + + tri_rlmreg_p #(.WIDTH(5), .NEEDS_SRESET(0)) act_lat( + .force_t(force_t), // tidn, + .d_mode(tiup), + .delay_lclkr(delay_lclkr[4]), // tidn, + .mpw1_b(mpw1_b[4]), // tidn, + .mpw2_b(mpw2_b[0]), // tidn, + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + .act(fpu_enable), + .scout(act_so), + .scin(act_si), + //----------------- + .din({ act_spare_unused[0], + act_spare_unused[1], + ex3_act, + ex4_act, + act_spare_unused[2]}), + //----------------- + .dout({ act_spare_unused[0], + act_spare_unused[1], + ex4_act, + ex5_act, + act_spare_unused[2]}) + ); + + ////############################################## + ////# EX4 logic + ////############################################## + + assign ex4_iexp[1:13] = ({13{(~f_pic_ex4_sel_est)}} & f_eie_ex4_iexp[1:13]) | + ({13{f_pic_ex4_sel_est}} & f_tbe_ex4_expo[1:13]); + + assign ex4_sp = (~f_pic_ex4_sp_b); + + // for bias 1023 ... dp underflow = 0, 1 <1+163> = 164 + // for bias 2047 ... dp underflow = 1024, 1025 <1025+163> = 1188 + // + // for bias 1023 ... sp underflow = 896, 897 <897+163> = 1060 + // for bias 2047 ... sp underflow = 1920, 1921 <1921+163> = 2084 + // + // lza can subtract at most 163, if expo is > 163, then it will not underflow. + // (round up a little to make it easier ... sp is the problem ) + // + // 0_0100_0010_0100 1060 1024 + 36 + // 0_1000_0010_0100 2084 + // 0_1000_0011_0000 <= round up a little to look at less bits + // 0_0100_0011_0000 <= round up a little to look at less bits + //---------------------- + // 1111 + // 1 2345 6789 0123 + + assign ex4_may_ovf = (ex4_may_ov_usual & (~f_pic_ex4_sel_est)) | (f_tbe_ex4_may_ov & f_pic_ex4_sel_est); + + assign ex4_may_ov_usual = ((~f_eie_ex4_iexp[1]) & f_eie_ex4_iexp[2]) | ((~f_eie_ex4_iexp[1]) & f_eie_ex4_iexp[3] & f_eie_ex4_iexp[4]) | ((~f_eie_ex4_iexp[1]) & f_eie_ex4_iexp[3] & f_eie_ex4_iexp[5]) | ((~f_eie_ex4_iexp[1]) & f_eie_ex4_iexp[3] & f_eie_ex4_iexp[6]) | ((~f_eie_ex4_iexp[1]) & f_eie_ex4_iexp[3] & f_eie_ex4_iexp[7]) | ((~f_eie_ex4_iexp[1]) & f_eie_ex4_iexp[3] & f_eie_ex4_iexp[8] & f_eie_ex4_iexp[9]); + + ////############################################## + ////# EX5 latch inputs from ex4 + ////############################################## + + + tri_rlmreg_p #(.WIDTH(16), .NEEDS_SRESET(0)) ex5_iexp_lat( + .force_t(force_t), // tidn, + .d_mode(tiup), + .delay_lclkr(delay_lclkr[4]), // tidn, + .mpw1_b(mpw1_b[4]), // tidn, + .mpw2_b(mpw2_b[0]), // tidn, + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + .act(ex4_act), + .scout(ex5_iexp_so), + .scin(ex5_iexp_si), + //----------------- + .din({ ex4_sp, + ex4_iexp[1:13], + ex4_may_ovf, + f_pic_ex4_sel_est}), + //----------------- + .dout({ ex5_sp, //LAT-- + ex5_i_exp[1:13], //LAT-- + ex5_may_ovf, //LAT-- + ex5_sel_est}) //LAT-- + ); + + assign f_eov_ex5_may_ovf = ex5_may_ovf; + + ////############################################## + ////# EX5 logic + ////############################################## + + ////#------------------------------------------- + ////# ue1oe1 constant + ////#------------------------------------------- + // need to know constant (sp/dp +/-192 +/-1536 ) + // +1536 11000 UNF + // -1536 01000 OVF + // +192 00011 UNF + // -192 11101 OVF + + assign ex5_ue1oe1_k[3] = ((~ex5_may_ovf) & (~ex5_sp)) | (ex5_may_ovf & ex5_sp); + + assign ex5_ue1oe1_k[4] = ((~ex5_sp)) | (ex5_may_ovf & ex5_sp); + + assign ex5_ue1oe1_k[5] = (ex5_may_ovf & ex5_sp); + + assign ex5_ue1oe1_k[6] = ((~ex5_may_ovf) & ex5_sp); + assign ex5_ue1oe1_k[7] = (ex5_sp); + + ////#------------------------------------------- + ////# subtract the lza (lza is an early signal) + ////#------------------------------------------- + // rnd_up=0 extra=1 +0-1 = -1 + // rnd_up=0 extra=0 +0-0 = -0 + // rnd_up=1 extra=1 +1-1 = -0 + // rnd_up=1 extra=0 +1-0 = +1 + // + // (a - b) = a + !b + 1 + // (a - b) -1 = a + !b + // + // need to calculate (A+!B), (A+!B+1), (A+!B+2) + // calculate lower 2 bits (A+!B) then determine the co for the 3 seperate cases + // compound add the upper bits (ci=0) (ci+1), then use the lower cases to select the combinations + // + + // sort of 3:2 compresor to make room for extra carry for +1 +2; + + assign ex5_lza_amt_b[0:7] = (~f_lza_ex5_lza_amt_eov[0:7]); + assign ex5_lza_amt[0:7] = f_lza_ex5_lza_amt_eov[0:7]; + assign ex5_sh_rgt_en_b = (~f_lza_ex5_sh_rgt_en_eov); + + // ex5_lzasub_sum( 0) <= ex5_sh_rgt_en_b xor ex5_i_exp( 1); + assign ex5_lzasub_sum[1] = ex5_sh_rgt_en_b ^ ex5_i_exp[1]; + assign ex5_lzasub_sum[2] = ex5_sh_rgt_en_b ^ ex5_i_exp[2]; + assign ex5_lzasub_sum[3] = ex5_sh_rgt_en_b ^ ex5_i_exp[3]; + assign ex5_lzasub_sum[4] = ex5_sh_rgt_en_b ^ ex5_i_exp[4]; + assign ex5_lzasub_sum[5] = ex5_sh_rgt_en_b ^ ex5_i_exp[5]; + assign ex5_lzasub_sum[6] = ex5_lza_amt_b[0] ^ ex5_i_exp[6]; + assign ex5_lzasub_sum[7] = ex5_lza_amt_b[1] ^ ex5_i_exp[7]; + assign ex5_lzasub_sum[8] = ex5_lza_amt_b[2] ^ ex5_i_exp[8]; + assign ex5_lzasub_sum[9] = ex5_lza_amt_b[3] ^ ex5_i_exp[9]; + assign ex5_lzasub_sum[10] = ex5_lza_amt_b[4] ^ ex5_i_exp[10]; + assign ex5_lzasub_sum[11] = ex5_lza_amt_b[5] ^ ex5_i_exp[11]; + assign ex5_lzasub_sum[12] = ex5_lza_amt_b[6] ^ ex5_i_exp[12]; + assign ex5_lzasub_sum[13] = (~(ex5_lza_amt_b[7] ^ ex5_i_exp[13])); //!!!!!!!! +1 for negation + + // ex5_lzasub_car( 0) <= ex5_sh_rgt_en_b and ex5_i_exp( 1); + assign ex5_lzasub_car[1] = ex5_sh_rgt_en_b & ex5_i_exp[2]; + assign ex5_lzasub_car[2] = ex5_sh_rgt_en_b & ex5_i_exp[3]; + assign ex5_lzasub_car[3] = ex5_sh_rgt_en_b & ex5_i_exp[4]; + assign ex5_lzasub_car[4] = ex5_sh_rgt_en_b & ex5_i_exp[5]; + assign ex5_lzasub_car[5] = ex5_lza_amt_b[0] & ex5_i_exp[6]; + assign ex5_lzasub_car[6] = ex5_lza_amt_b[1] & ex5_i_exp[7]; + assign ex5_lzasub_car[7] = ex5_lza_amt_b[2] & ex5_i_exp[8]; + assign ex5_lzasub_car[8] = ex5_lza_amt_b[3] & ex5_i_exp[9]; + assign ex5_lzasub_car[9] = ex5_lza_amt_b[4] & ex5_i_exp[10]; + assign ex5_lzasub_car[10] = ex5_lza_amt_b[5] & ex5_i_exp[11]; + assign ex5_lzasub_car[11] = ex5_lza_amt_b[6] & ex5_i_exp[12]; + assign ex5_lzasub_car[12] = ex5_lza_amt_b[7] | ex5_i_exp[13]; //!!!!!! +1 for negation + + assign ex5_lzasub_p[1:12] = ex5_lzasub_car[1:12] ^ ex5_lzasub_sum[1:12]; + assign ex5_lzasub_t[2:12] = ex5_lzasub_car[2:12] | ex5_lzasub_sum[2:12]; + assign ex5_lzasub_g[2:12] = ex5_lzasub_car[2:12] & ex5_lzasub_sum[2:12]; + + ////##------------------------------ + ////##-- add the 2 lower bits for the different conditions (+0,+1.+2) + ////##------------------------------ + + assign ex5_lzasub_m1_c12 = ex5_lzasub_g[12]; + assign ex5_lzasub_p0_c12 = ex5_lzasub_g[12] | (ex5_lzasub_t[12] & ex5_lzasub_sum[13]); + assign ex5_lzasub_p1_c12 = ex5_lzasub_t[12]; + + assign ex5_lzasub_m1[13] = ex5_lzasub_sum[13]; //LSB is done +0 + assign ex5_lzasub_p0[13] = (~ex5_lzasub_sum[13]); //LSB is done +1 + assign ex5_lzasub_p1[13] = ex5_lzasub_sum[13]; //LSB is done +2 + + assign ex5_lzasub_m1[12] = ex5_lzasub_p[12]; // +0 + assign ex5_lzasub_p0[12] = ex5_lzasub_p[12] ^ ex5_lzasub_sum[13]; // +1 + assign ex5_lzasub_p1[12] = (~ex5_lzasub_p[12]); // +2 + + ////##----------------------------------- + ////## the conditional carry chain (+ci,-ci) + ////##----------------------------------- + + assign ex5_lzasub_gg02[11] = ex5_lzasub_g[11]; + assign ex5_lzasub_gg02[10] = ex5_lzasub_g[10] | (ex5_lzasub_t[10] & ex5_lzasub_g[11]); //final + assign ex5_lzasub_gg02[9] = ex5_lzasub_g[9] | (ex5_lzasub_t[9] & ex5_lzasub_g[10]); + assign ex5_lzasub_gg02[8] = ex5_lzasub_g[8] | (ex5_lzasub_t[8] & ex5_lzasub_g[9]); + assign ex5_lzasub_gg02[7] = ex5_lzasub_g[7] | (ex5_lzasub_t[7] & ex5_lzasub_g[8]); + assign ex5_lzasub_gg02[6] = ex5_lzasub_g[6] | (ex5_lzasub_t[6] & ex5_lzasub_g[7]); + assign ex5_lzasub_gg02[5] = ex5_lzasub_g[5] | (ex5_lzasub_t[5] & ex5_lzasub_g[6]); + assign ex5_lzasub_gg02[4] = ex5_lzasub_g[4] | (ex5_lzasub_t[4] & ex5_lzasub_g[5]); + assign ex5_lzasub_gg02[3] = ex5_lzasub_g[3] | (ex5_lzasub_t[3] & ex5_lzasub_g[4]); + assign ex5_lzasub_gg02[2] = ex5_lzasub_g[2] | (ex5_lzasub_t[2] & ex5_lzasub_g[3]); + + assign ex5_lzasub_gt02[11] = ex5_lzasub_t[11]; + assign ex5_lzasub_gt02[10] = ex5_lzasub_g[10] | (ex5_lzasub_t[10] & ex5_lzasub_t[11]); //final + assign ex5_lzasub_gt02[9] = (ex5_lzasub_t[9] & ex5_lzasub_t[10]); + assign ex5_lzasub_gt02[8] = (ex5_lzasub_t[8] & ex5_lzasub_t[9]); + assign ex5_lzasub_gt02[7] = (ex5_lzasub_t[7] & ex5_lzasub_t[8]); + assign ex5_lzasub_gt02[6] = (ex5_lzasub_t[6] & ex5_lzasub_t[7]); + assign ex5_lzasub_gt02[5] = (ex5_lzasub_t[5] & ex5_lzasub_t[6]); + assign ex5_lzasub_gt02[4] = (ex5_lzasub_t[4] & ex5_lzasub_t[5]); + assign ex5_lzasub_gt02[3] = (ex5_lzasub_t[3] & ex5_lzasub_t[4]); + assign ex5_lzasub_gt02[2] = (ex5_lzasub_t[2] & ex5_lzasub_t[3]); + + assign ex5_lzasub_gg04[11] = ex5_lzasub_gg02[11]; + assign ex5_lzasub_gg04[10] = ex5_lzasub_gg02[10]; + assign ex5_lzasub_gg04[9] = ex5_lzasub_gg02[9] | (ex5_lzasub_gt02[9] & ex5_lzasub_gg02[11]); //final + assign ex5_lzasub_gg04[8] = ex5_lzasub_gg02[8] | (ex5_lzasub_gt02[8] & ex5_lzasub_gg02[10]); //final + assign ex5_lzasub_gg04[7] = ex5_lzasub_gg02[7] | (ex5_lzasub_gt02[7] & ex5_lzasub_gg02[9]); + assign ex5_lzasub_gg04[6] = ex5_lzasub_gg02[6] | (ex5_lzasub_gt02[6] & ex5_lzasub_gg02[8]); + assign ex5_lzasub_gg04[5] = ex5_lzasub_gg02[5] | (ex5_lzasub_gt02[5] & ex5_lzasub_gg02[7]); + assign ex5_lzasub_gg04[4] = ex5_lzasub_gg02[4] | (ex5_lzasub_gt02[4] & ex5_lzasub_gg02[6]); + assign ex5_lzasub_gg04[3] = ex5_lzasub_gg02[3] | (ex5_lzasub_gt02[3] & ex5_lzasub_gg02[5]); + assign ex5_lzasub_gg04[2] = ex5_lzasub_gg02[2] | (ex5_lzasub_gt02[2] & ex5_lzasub_gg02[4]); + + assign ex5_lzasub_gt04[11] = ex5_lzasub_gt02[11]; + assign ex5_lzasub_gt04[10] = ex5_lzasub_gt02[10]; + assign ex5_lzasub_gt04[9] = ex5_lzasub_gg02[9] | (ex5_lzasub_gt02[9] & ex5_lzasub_gt02[11]); //final + assign ex5_lzasub_gt04[8] = ex5_lzasub_gg02[8] | (ex5_lzasub_gt02[8] & ex5_lzasub_gt02[10]); //final + assign ex5_lzasub_gt04[7] = (ex5_lzasub_gt02[7] & ex5_lzasub_gt02[9]); + assign ex5_lzasub_gt04[6] = (ex5_lzasub_gt02[6] & ex5_lzasub_gt02[8]); + assign ex5_lzasub_gt04[5] = (ex5_lzasub_gt02[5] & ex5_lzasub_gt02[7]); + assign ex5_lzasub_gt04[4] = (ex5_lzasub_gt02[4] & ex5_lzasub_gt02[6]); + assign ex5_lzasub_gt04[3] = (ex5_lzasub_gt02[3] & ex5_lzasub_gt02[5]); + assign ex5_lzasub_gt04[2] = (ex5_lzasub_gt02[2] & ex5_lzasub_gt02[4]); + + assign ex5_lzasub_gg08[11] = ex5_lzasub_gg04[11]; + assign ex5_lzasub_gg08[10] = ex5_lzasub_gg04[10]; + assign ex5_lzasub_gg08[9] = ex5_lzasub_gg04[9]; + assign ex5_lzasub_gg08[8] = ex5_lzasub_gg04[8]; + assign ex5_lzasub_gg08[7] = ex5_lzasub_gg04[7] | (ex5_lzasub_gt04[7] & ex5_lzasub_gg04[11]); //final + assign ex5_lzasub_gg08[6] = ex5_lzasub_gg04[6] | (ex5_lzasub_gt04[6] & ex5_lzasub_gg04[10]); //final + assign ex5_lzasub_gg08[5] = ex5_lzasub_gg04[5] | (ex5_lzasub_gt04[5] & ex5_lzasub_gg04[9]); //final + assign ex5_lzasub_gg08[4] = ex5_lzasub_gg04[4] | (ex5_lzasub_gt04[4] & ex5_lzasub_gg04[8]); //final + assign ex5_lzasub_gg08[3] = ex5_lzasub_gg04[3] | (ex5_lzasub_gt04[3] & ex5_lzasub_gg04[7]); + assign ex5_lzasub_gg08[2] = ex5_lzasub_gg04[2] | (ex5_lzasub_gt04[2] & ex5_lzasub_gg04[6]); + + assign ex5_lzasub_gt08[11] = ex5_lzasub_gt04[11]; + assign ex5_lzasub_gt08[10] = ex5_lzasub_gt04[10]; + assign ex5_lzasub_gt08[9] = ex5_lzasub_gt04[9]; + assign ex5_lzasub_gt08[8] = ex5_lzasub_gt04[8]; + assign ex5_lzasub_gt08[7] = ex5_lzasub_gg04[7] | (ex5_lzasub_gt04[7] & ex5_lzasub_gt04[11]); //final + assign ex5_lzasub_gt08[6] = ex5_lzasub_gg04[6] | (ex5_lzasub_gt04[6] & ex5_lzasub_gt04[10]); //final + assign ex5_lzasub_gt08[5] = ex5_lzasub_gg04[5] | (ex5_lzasub_gt04[5] & ex5_lzasub_gt04[9]); //final + assign ex5_lzasub_gt08[4] = ex5_lzasub_gg04[4] | (ex5_lzasub_gt04[4] & ex5_lzasub_gt04[8]); //final + assign ex5_lzasub_gt08[3] = (ex5_lzasub_gt04[3] & ex5_lzasub_gt04[7]); + assign ex5_lzasub_gt08[2] = (ex5_lzasub_gt04[2] & ex5_lzasub_gt04[6]); + + assign ex5_lzasub_c0[11] = ex5_lzasub_gg08[11]; + assign ex5_lzasub_c0[10] = ex5_lzasub_gg08[10]; + assign ex5_lzasub_c0[9] = ex5_lzasub_gg08[9]; + assign ex5_lzasub_c0[8] = ex5_lzasub_gg08[8]; + assign ex5_lzasub_c0[7] = ex5_lzasub_gg08[7]; + assign ex5_lzasub_c0[6] = ex5_lzasub_gg08[6]; + assign ex5_lzasub_c0[5] = ex5_lzasub_gg08[5]; + assign ex5_lzasub_c0[4] = ex5_lzasub_gg08[4]; + assign ex5_lzasub_c0[3] = ex5_lzasub_gg08[3] | (ex5_lzasub_gt08[3] & ex5_lzasub_gg08[11]); //final + assign ex5_lzasub_c0[2] = ex5_lzasub_gg08[2] | (ex5_lzasub_gt08[2] & ex5_lzasub_gg08[10]); //final + + assign ex5_lzasub_c1[11] = ex5_lzasub_gt08[11]; + assign ex5_lzasub_c1[10] = ex5_lzasub_gt08[10]; + assign ex5_lzasub_c1[9] = ex5_lzasub_gt08[9]; + assign ex5_lzasub_c1[8] = ex5_lzasub_gt08[8]; + assign ex5_lzasub_c1[7] = ex5_lzasub_gt08[7]; + assign ex5_lzasub_c1[6] = ex5_lzasub_gt08[6]; + assign ex5_lzasub_c1[5] = ex5_lzasub_gt08[5]; + assign ex5_lzasub_c1[4] = ex5_lzasub_gt08[4]; + assign ex5_lzasub_c1[3] = ex5_lzasub_gg08[3] | (ex5_lzasub_gt08[3] & ex5_lzasub_gt08[11]); //final + assign ex5_lzasub_c1[2] = ex5_lzasub_gg08[2] | (ex5_lzasub_gt08[2] & ex5_lzasub_gt08[10]); //final + + assign ex5_lzasub_s0[1:11] = ex5_lzasub_p[1:11] ^ ({ex5_lzasub_c0[2:11], tidn}); + assign ex5_lzasub_s1[1:11] = ex5_lzasub_p[1:11] ^ ({ex5_lzasub_c1[2:11], tiup}); + + assign ex5_lzasub_m1[1:11] = (ex5_lzasub_s0[1:11] & {11{(~ex5_lzasub_m1_c12)}}) | + (ex5_lzasub_s1[1:11] & {11{ex5_lzasub_m1_c12}}); + + assign ex5_lzasub_p0[1:11] = (ex5_lzasub_s0[1:11] & {11{(~ex5_lzasub_p0_c12)}}) | + (ex5_lzasub_s1[1:11] & {11{ex5_lzasub_p0_c12}}); + + assign ex5_lzasub_p1[1:11] = (ex5_lzasub_s0[1:11] & {11{(~ex5_lzasub_p1_c12)}}) | + (ex5_lzasub_s1[1:11] & {11{ex5_lzasub_p1_c12}}); + + ////#------------------------------------------- + ////# determine overflow (expo bias = 1023, with signed bit) + ////#------------------------------------------- + // + // dp overflow: ge 2047 = 2047 ge 2047 + // sp overflow: ge 255 + 896 = 1151 ge 1151 + // + // using expo_m1 as the base: + // m1 p0 p1 + // dp ovf: ge 2047 ge 2046 ge 2045 + // sp ovf: ge 1151 ge 1150 ge 1149 + // + // could just do the subtract, then decode the result. (triple compound add becomes critical). + // doingg compare before the add (faster) + // + // 2047 0_0111_1111_1111 + // 1151 0_0100_0111_1111 + // + // 0 0000 0000 1111 + // 1 2345 6789 0123 + // + //------------------------------- + // 0_01dd_d111_1111 (minimum) + // 1_10ss_s000_0000 !(minimum) + // 1_10ss_s000_0001 -(minimum) + // 1_10ss_s000_0010 BOUNDRY +1 for -lza = !lza+1 + // 1_11 add the lza sign xtd + //-------------------------------- + //- 1_01ss_s000_0100 + //-------------------------------- + // overflow if (iexp-lza) >= 2047 + // overflow if (iexp-lza) - 2047 >= 0 + // POSITIVE result means overflow. + // NEGATIVE result means no overflow. + + assign ex5_ovf_sum[1] = ex5_sh_rgt_en_b ^ (~ex5_i_exp[1]); // 1 !R [1] + assign ex5_ovf_sum[2] = ex5_sh_rgt_en_b ^ (~ex5_i_exp[2]); // 1 !R [2] + assign ex5_ovf_sum[3] = ex5_sh_rgt_en_b ^ ex5_i_exp[3]; // 0 !R [3] + assign ex5_ovf_sum[4] = ex5_sh_rgt_en_b ^ ex5_i_exp[4] ^ ex5_sp; // s !R [4] + assign ex5_ovf_sum[5] = ex5_sh_rgt_en_b ^ ex5_i_exp[5] ^ ex5_sp; // s !R [5] + assign ex5_ovf_sum[6] = (~ex5_lza_amt[0]) ^ ex5_i_exp[6] ^ ex5_sp; // s ![0] [6] + assign ex5_ovf_sum[7] = (~ex5_lza_amt[1]) ^ ex5_i_exp[7]; // 0 ![1] [7] + assign ex5_ovf_sum[8] = (~ex5_lza_amt[2]) ^ ex5_i_exp[8]; // 0 ![2] [8] + assign ex5_ovf_sum[9] = (~ex5_lza_amt[3]) ^ ex5_i_exp[9]; // 0 ![3] [9] + assign ex5_ovf_sum[10] = (~ex5_lza_amt[4]) ^ ex5_i_exp[10]; // 0 ![4] [10] + assign ex5_ovf_sum[11] = (~ex5_lza_amt[5]) ^ ex5_i_exp[11]; // 0 ![5] [11] + assign ex5_ovf_sum[12] = (~ex5_lza_amt[6]) ^ (~ex5_i_exp[12]); // 1 ![6] [12] + assign ex5_ovf_sum[13] = (~ex5_lza_amt[7]) ^ ex5_i_exp[13]; // 0 ![7] [13] + + assign ex5_ovf_car[1] = ex5_sh_rgt_en_b | ex5_i_exp[2]; // 1 !R [2] + assign ex5_ovf_car[2] = ex5_sh_rgt_en_b & ex5_i_exp[3]; // 0 !R [3] + + assign ex5_ovf_car[3] = (ex5_sp & ex5_i_exp[4]) | (ex5_sh_rgt_en_b & ex5_i_exp[4]) | (ex5_sh_rgt_en_b & ex5_sp); // s !R [4] + + assign ex5_ovf_car[4] = (ex5_sp & ex5_i_exp[5]) | (ex5_sh_rgt_en_b & ex5_i_exp[5]) | (ex5_sh_rgt_en_b & ex5_sp); // s !R [5] + + assign ex5_ovf_car[5] = ((~ex5_lza_amt[0]) & ex5_i_exp[6]) | ((~ex5_lza_amt[0]) & ex5_sp) | (ex5_sp & ex5_i_exp[6]); // s ![0] [6] + assign ex5_ovf_car[6] = (~ex5_lza_amt[1]) & ex5_i_exp[7]; // 0 ![1] [7] + assign ex5_ovf_car[7] = (~ex5_lza_amt[2]) & ex5_i_exp[8]; // 0 ![2] [8] + assign ex5_ovf_car[8] = (~ex5_lza_amt[3]) & ex5_i_exp[9]; // 0 ![3] [9] + assign ex5_ovf_car[9] = (~ex5_lza_amt[4]) & ex5_i_exp[10]; // 0 ![4] [10] + assign ex5_ovf_car[10] = (~ex5_lza_amt[5]) & ex5_i_exp[11]; // 0 ![5] [11] + assign ex5_ovf_car[11] = (~ex5_lza_amt[6]) | ex5_i_exp[12]; // 1 ![6] [12] + assign ex5_ovf_car[12] = (~ex5_lza_amt[7]) & ex5_i_exp[13]; // 0 ![7] [13] + + assign ex5_ovf_g[2:12] = ex5_ovf_car[2:12] & ex5_ovf_sum[2:12]; + assign ex5_ovf_t[2:12] = ex5_ovf_car[2:12] | ex5_ovf_sum[2:12]; + assign ex5_ovf_p[1] = ex5_ovf_car[1] ^ ex5_ovf_sum[1]; + + // lower bits (compute 3 possible combinations) + + assign ex5_ovf_m1_co12 = ex5_ovf_g[12]; + assign ex5_ovf_p0_co12 = ex5_ovf_g[12] | (ex5_ovf_t[12] & ex5_ovf_sum[13]); + assign ex5_ovf_p1_co12 = ex5_ovf_t[12]; + + // upper bits (compute 2 possible combinations) + + assign ex5_ovf_g2_02t03 = ex5_ovf_g[2] | (ex5_ovf_t[2] & ex5_ovf_g[3]); + assign ex5_ovf_g2_04t05 = ex5_ovf_g[4] | (ex5_ovf_t[4] & ex5_ovf_g[5]); + assign ex5_ovf_g2_06t07 = ex5_ovf_g[6] | (ex5_ovf_t[6] & ex5_ovf_g[7]); + assign ex5_ovf_g2_08t09 = ex5_ovf_g[8] | (ex5_ovf_t[8] & ex5_ovf_g[9]); + assign ex5_ovf_g2_ci0 = ex5_ovf_g[10] | (ex5_ovf_t[10] & ex5_ovf_g[11]); + assign ex5_ovf_g2_ci1 = ex5_ovf_g[10] | (ex5_ovf_t[10] & ex5_ovf_t[11]); + + assign ex5_ovf_t2_02t03 = (ex5_ovf_t[2] & ex5_ovf_t[3]); + assign ex5_ovf_t2_04t05 = (ex5_ovf_t[4] & ex5_ovf_t[5]); + assign ex5_ovf_t2_06t07 = (ex5_ovf_t[6] & ex5_ovf_t[7]); + assign ex5_ovf_t2_08t09 = (ex5_ovf_t[8] & ex5_ovf_t[9]); + + assign ex5_ovf_g4_02t05 = ex5_ovf_g2_02t03 | (ex5_ovf_t2_02t03 & ex5_ovf_g2_04t05); + assign ex5_ovf_g4_06t09 = ex5_ovf_g2_06t07 | (ex5_ovf_t2_06t07 & ex5_ovf_g2_08t09); + assign ex5_ovf_g4_ci0 = ex5_ovf_g2_ci0; + assign ex5_ovf_g4_ci1 = ex5_ovf_g2_ci1; + + assign ex5_ovf_t4_02t05 = (ex5_ovf_t2_02t03 & ex5_ovf_t2_04t05); + assign ex5_ovf_t4_06t09 = (ex5_ovf_t2_06t07 & ex5_ovf_t2_08t09); + + assign ex5_ovf_g8_02t09 = ex5_ovf_g4_02t05 | (ex5_ovf_t4_02t05 & ex5_ovf_g4_06t09); + assign ex5_ovf_g8_ci0 = ex5_ovf_g4_ci0; + assign ex5_ovf_g8_ci1 = ex5_ovf_g4_ci1; + + assign ex5_ovf_t8_02t09 = (ex5_ovf_t4_02t05 & ex5_ovf_t4_06t09); + + assign ex5_ovf_ci0_02t11 = ex5_ovf_g8_02t09 | (ex5_ovf_t8_02t09 & ex5_ovf_g8_ci0); + assign ex5_ovf_ci1_02t11 = ex5_ovf_g8_02t09 | (ex5_ovf_t8_02t09 & ex5_ovf_g8_ci1); + + // 13 BITS HOLDS EVERYTHING -- positive result means overflow + assign ex5_c2_m1 = (ex5_ovf_ci0_02t11 | (ex5_ovf_ci1_02t11 & ex5_ovf_m1_co12)); + assign ex5_c2_p0 = (ex5_ovf_ci0_02t11 | (ex5_ovf_ci1_02t11 & ex5_ovf_p0_co12)); + assign ex5_c2_p1 = (ex5_ovf_ci0_02t11 | (ex5_ovf_ci1_02t11 & ex5_ovf_p1_co12)); + + assign ex5_ovf_m1 = (~ex5_ovf_p[1]) ^ ex5_c2_m1; + assign ex5_ovf_p0 = (~ex5_ovf_p[1]) ^ ex5_c2_p0; + assign ex5_ovf_p1 = (~ex5_ovf_p[1]) ^ ex5_c2_p1; + + ////#------------------------------------------- + ////# determine underflow (expo bias = 1023, with signed bit) + ////#------------------------------------------- + // dp underflow: le 0 = le 0 => !ge 1 + // sp underflow: le 0 + 896 = le 896 => !ge 897 + // + // if the exponent will be incremented (then there are less overflows). + // just need for m1, p0 because underflow is determined before rounding. + // if there is an underflow exception it cannot round up the exponent. + // m1 p0 + // dp unf: !ge 1 !ge 0 + // sp unf: !ge 897 !ge 896 + // + // 1 0_0000_0000_0001 dp: 0_0000_0000_0001 sp: 0_0011_1000_0001 emin + // 0 0_0000_0000_0000 1_1111_1111_1110 1_1100_0111_1110 !emin + // 1_1111_1111_1111 1_1100_0111_1111 -emin + // 0 0000 0000 1111 0_0000_0000_0000 1_1100_1000_0000 <= +1 -lza=!lza+1 + // 1 2345 6789 0123 + // + // 897 0_0011_1000_0001 + // 896 0_0011_1000_0000 + //------------------------------- + // if (exp-lza) >= emin NO_UNDERFLOW + // if (exp-lza) - emin >= 0 UNDERFLOW {sign bit = "1"} + + assign ex5_unf_sum[1] = ex5_sh_rgt_en_b ^ ex5_i_exp[1] ^ ex5_sp; // s !R [1] + assign ex5_unf_sum[2] = ex5_sh_rgt_en_b ^ ex5_i_exp[2] ^ ex5_sp; // s !R [2] + assign ex5_unf_sum[3] = ex5_sh_rgt_en_b ^ ex5_i_exp[3] ^ ex5_sp; // s !R [3] + assign ex5_unf_sum[4] = ex5_sh_rgt_en_b ^ ex5_i_exp[4]; // 0 !R [4] + assign ex5_unf_sum[5] = ex5_sh_rgt_en_b ^ ex5_i_exp[5]; // 0 !R [5] + assign ex5_unf_sum[6] = (~ex5_lza_amt[0]) ^ ex5_i_exp[6] ^ ex5_sp; // s ![0] [6] + assign ex5_unf_sum[7] = (~ex5_lza_amt[1]) ^ ex5_i_exp[7]; // 0 ![1] [7] + assign ex5_unf_sum[8] = (~ex5_lza_amt[2]) ^ ex5_i_exp[8]; // 0 ![2] [8] + assign ex5_unf_sum[9] = (~ex5_lza_amt[3]) ^ ex5_i_exp[9]; // 0 ![3] [9] + assign ex5_unf_sum[10] = (~ex5_lza_amt[4]) ^ ex5_i_exp[10]; // 0 ![4] [10] + assign ex5_unf_sum[11] = (~ex5_lza_amt[5]) ^ ex5_i_exp[11]; // 0 ![5] [11] + assign ex5_unf_sum[12] = (~ex5_lza_amt[6]) ^ ex5_i_exp[12]; // 0 ![6] [12] + assign ex5_unf_sum[13] = (~ex5_lza_amt[7]) ^ ex5_i_exp[13]; // 0 ![7] [13] + + assign ex5_unf_car[1] = (ex5_sp & ex5_i_exp[2]) | (ex5_sh_rgt_en_b & ex5_i_exp[2]) | (ex5_sh_rgt_en_b & ex5_sp); // s !R [2] + assign ex5_unf_car[2] = (ex5_sp & ex5_i_exp[3]) | (ex5_sh_rgt_en_b & ex5_i_exp[3]) | (ex5_sh_rgt_en_b & ex5_sp); // s !R [3] + assign ex5_unf_car[3] = ex5_sh_rgt_en_b & ex5_i_exp[4]; // 0 !R [4] + assign ex5_unf_car[4] = ex5_sh_rgt_en_b & ex5_i_exp[5]; // 0 !R [5] + assign ex5_unf_car[5] = ((~ex5_lza_amt[0]) & ex5_i_exp[6]) | ((~ex5_lza_amt[0]) & ex5_sp) | (ex5_sp & ex5_i_exp[6]); // s ![0] [6] + assign ex5_unf_car[6] = (~ex5_lza_amt[1]) & ex5_i_exp[7]; // 0 ![1] [7] + assign ex5_unf_car[7] = (~ex5_lza_amt[2]) & ex5_i_exp[8]; // 0 ![2] [8] + assign ex5_unf_car[8] = (~ex5_lza_amt[3]) & ex5_i_exp[9]; // 0 ![3] [9] + assign ex5_unf_car[9] = (~ex5_lza_amt[4]) & ex5_i_exp[10]; // 0 ![4] [10] + assign ex5_unf_car[10] = (~ex5_lza_amt[5]) & ex5_i_exp[11]; // 0 ![5] [11] + assign ex5_unf_car[11] = (~ex5_lza_amt[6]) & ex5_i_exp[12]; // 0 ![6] [12] + assign ex5_unf_car[12] = (~ex5_lza_amt[7]) & ex5_i_exp[13]; // 0 ![7] [13] + + assign ex5_unf_g[2:12] = ex5_unf_car[2:12] & ex5_unf_sum[2:12]; + assign ex5_unf_t[2:12] = ex5_unf_car[2:12] | ex5_unf_sum[2:12]; + assign ex5_unf_p[1] = ex5_unf_car[1] ^ ex5_unf_sum[1]; + + assign ex5_unf_m1_co12 = ex5_unf_g[12]; + assign ex5_unf_p0_co12 = ex5_unf_g[12] | (ex5_unf_t[12] & ex5_unf_sum[13]); + + assign ex5_unf_g2_02t03 = ex5_unf_g[2] | (ex5_unf_t[2] & ex5_unf_g[3]); + assign ex5_unf_g2_04t05 = ex5_unf_g[4] | (ex5_unf_t[4] & ex5_unf_g[5]); + assign ex5_unf_g2_06t07 = ex5_unf_g[6] | (ex5_unf_t[6] & ex5_unf_g[7]); + assign ex5_unf_g2_08t09 = ex5_unf_g[8] | (ex5_unf_t[8] & ex5_unf_g[9]); + assign ex5_unf_g2_10t11 = ex5_unf_g[10] | (ex5_unf_t[10] & ex5_unf_g[11]); + assign ex5_unf_ci0_g2 = ex5_unf_g[12]; + assign ex5_unf_ci1_g2 = ex5_unf_t[12]; + + assign ex5_unf_t2_02t03 = (ex5_unf_t[2] & ex5_unf_t[3]); + assign ex5_unf_t2_04t05 = (ex5_unf_t[4] & ex5_unf_t[5]); + assign ex5_unf_t2_06t07 = (ex5_unf_t[6] & ex5_unf_t[7]); + assign ex5_unf_t2_08t09 = (ex5_unf_t[8] & ex5_unf_t[9]); + assign ex5_unf_t2_10t11 = (ex5_unf_t[10] & ex5_unf_t[11]); + assign ex5_unf_g4_02t05 = ex5_unf_g2_02t03 | (ex5_unf_t2_02t03 & ex5_unf_g2_04t05); + assign ex5_unf_g4_06t09 = ex5_unf_g2_06t07 | (ex5_unf_t2_06t07 & ex5_unf_g2_08t09); + assign ex5_unf_ci0_g4 = ex5_unf_g2_10t11 | (ex5_unf_t2_10t11 & ex5_unf_ci0_g2); + assign ex5_unf_ci1_g4 = ex5_unf_g2_10t11 | (ex5_unf_t2_10t11 & ex5_unf_ci1_g2); + + assign ex5_unf_t4_02t05 = (ex5_unf_t2_02t03 & ex5_unf_t2_04t05); + assign ex5_unf_t4_06t09 = (ex5_unf_t2_06t07 & ex5_unf_t2_08t09); + + assign ex5_unf_g8_02t09 = ex5_unf_g4_02t05 | (ex5_unf_t4_02t05 & ex5_unf_g4_06t09); + assign ex5_unf_ci0_g8 = ex5_unf_ci0_g4; + assign ex5_unf_ci1_g8 = ex5_unf_ci1_g4; + + assign ex5_unf_t8_02t09 = (ex5_unf_t4_02t05 & ex5_unf_t4_06t09); + + assign ex5_unf_ci0_02t11 = ex5_unf_g8_02t09 | (ex5_unf_t8_02t09 & ex5_unf_ci0_g8); + assign ex5_unf_ci1_02t11 = ex5_unf_g8_02t09 | (ex5_unf_t8_02t09 & ex5_unf_ci1_g8); + + assign ex5_unf_c2_m1 = (ex5_unf_ci0_02t11 | (ex5_unf_ci1_02t11 & ex5_unf_m1_co12)); + assign ex5_unf_c2_p0 = (ex5_unf_ci0_02t11 | (ex5_unf_ci1_02t11 & ex5_unf_p0_co12)); + + // 13 BITS HOLDS EVERYTHING (sign==1 {neg} means underflow) + assign ex5_unf_m1 = ex5_unf_p[1] ^ ex5_unf_c2_m1; + assign ex5_unf_p0 = ex5_unf_p[1] ^ ex5_unf_c2_p0; + + ////#----------------------------------- + ////# adjust for the lza extra shift (late signal) + ////#----------------------------------- + + // ex5_expo_p0(1 to 13) <= + // (ex5_lzasub_m1(1 to 13) and (1 to 13 => f_nrm_ex5_extra_shift) ) or --sim-only + // (ex5_lzasub_p0(1 to 13) and (1 to 13 => not f_nrm_ex5_extra_shift) ) ; --sim-only + // ex5_expo_p1(1 to 13) <= --sim-only + // (ex5_lzasub_p0(1 to 13) and (1 to 13 => f_nrm_ex5_extra_shift) ) or --sim-only + // (ex5_lzasub_p1(1 to 13) and (1 to 13 => not f_nrm_ex5_extra_shift) ) ; --sim-only + // ex5_ovf_calc <= --sim-only + // (ex5_ovf_m1 and f_nrm_ex5_extra_shift ) or --sim-only + // (ex5_ovf_p0 and not f_nrm_ex5_extra_shift ) ; --sim-only + // ex5_ovf_if_calc <= --sim-only + // (ex5_ovf_p0 and f_nrm_ex5_extra_shift ) or --sim-only + // (ex5_ovf_p1 and not f_nrm_ex5_extra_shift ) ; --sim-only + // ex5_unf_calc <= -- for recip sp : do not zero out exponent ... let it go neg_sp (norm in dp range) --sim-only + // (ex5_unf_m1 and f_nrm_ex5_extra_shift ) or --sim-only + // (ex5_unf_p0 and not f_nrm_ex5_extra_shift ); --sim-only + // + + assign ex5_expo_p0_0_b[1:13] = (~(ex5_lzasub_m1[1:13] & {13{f_nrm_ex5_extra_shift}})); + assign ex5_expo_p0_1_b[1:13] = (~(ex5_lzasub_p0[1:13] & {13{(~f_nrm_ex5_extra_shift)}})); + assign ex5_expo_p0[1:13] = (~(ex5_expo_p0_0_b[1:13] & ex5_expo_p0_1_b[1:13])); + + assign ex5_expo_p1_0_b[1:13] = (~(ex5_lzasub_p0[1:13] & {13{f_nrm_ex5_extra_shift}})); + assign ex5_expo_p1_1_b[1:13] = (~(ex5_lzasub_p1[1:13] & {13{(~f_nrm_ex5_extra_shift)}})); + assign ex5_expo_p1[1:13] = (~(ex5_expo_p1_0_b[1:13] & ex5_expo_p1_1_b[1:13])); + + assign ex5_ovf_calc_0_b = (~(ex5_ovf_m1 & f_nrm_ex5_extra_shift)); + assign ex5_ovf_calc_1_b = (~(ex5_ovf_p0 & (~f_nrm_ex5_extra_shift))); + assign ex5_ovf_calc = (~(ex5_ovf_calc_0_b & ex5_ovf_calc_1_b)); + + assign ex5_ovf_if_calc_0_b = (~(ex5_ovf_p0 & f_nrm_ex5_extra_shift)); + assign ex5_ovf_if_calc_1_b = (~(ex5_ovf_p1 & (~f_nrm_ex5_extra_shift))); + assign ex5_ovf_if_calc = (~(ex5_ovf_if_calc_0_b & ex5_ovf_if_calc_1_b)); + + // for recip sp : do not zero out exponent ... let it go neg_sp (norm in dp range) + assign ex5_unf_calc_0_b = (~(ex5_unf_m1 & f_nrm_ex5_extra_shift)); + assign ex5_unf_calc_1_b = (~(ex5_unf_p0 & (~f_nrm_ex5_extra_shift))); + assign ex5_unf_calc = (~(ex5_unf_calc_0_b & ex5_unf_calc_1_b)); + + assign ex5_est_sp = ex5_sel_est & ex5_sp; + + assign ex5_unf_tbl = f_pic_ex5_uf_en & f_tbl_ex5_unf_expo; + assign ex5_unf_tbl_spec_e = (ex5_unf_tbl & (~ex5_est_sp) & (~f_pic_ex5_ue)) | ex5_sel_k_part_e; + assign ex5_ov_en = f_pic_ex5_ov_en; + assign ex5_ov_en_oe0 = f_pic_ex5_ov_en & (~f_pic_ex5_oe); + assign ex5_sel_ov_spec = f_pic_ex5_sel_ov_spec; + assign ex5_unf_en_nedge = f_pic_ex5_uf_en & (~f_lza_ex5_no_lza_edge); + assign ex5_unf_ue0_nestsp = f_pic_ex5_uf_en & (~f_lza_ex5_no_lza_edge) & (~f_pic_ex5_ue) & (~(ex5_est_sp)); + assign ex5_sel_k_part_e = f_pic_ex5_spec_sel_k_e | f_pic_ex5_to_int_ov_all; + assign ex5_sel_k_part_f = f_pic_ex5_spec_sel_k_f | f_pic_ex5_to_int_ov_all; + + ////############################################## + ////# EX6 latches + ////############################################## + + tri_nand2_nlats #(.WIDTH(13), .NEEDS_SRESET(0)) ex6_urnd0_lat( + .vd(vdd), + .gd(gnd), + .lclk(ex6_lclk), // lclk.clk + .d1clk(ex6_d1clk), + .d2clk(ex6_d2clk), + .scanin(ex6_urnd0_si), + .scanout(ex6_urnd0_so), + .a1(ex5_expo_p0_0_b[1:13]), + .a2(ex5_expo_p0_1_b[1:13]), + .qb(ex6_expo_p0[1:13]) //LAT-- + ); + + tri_nand2_nlats #(.WIDTH(13), .NEEDS_SRESET(0)) ex6_urnd1_lat( + .vd(vdd), + .gd(gnd), + .lclk(ex6_lclk), //lclk.clk + .d1clk(ex6_d1clk), + .d2clk(ex6_d2clk), + .scanin(ex6_urnd1_si), + .scanout(ex6_urnd1_so), + .a1(ex5_expo_p1_0_b[1:13]), + .a2(ex5_expo_p1_1_b[1:13]), + .qb(ex6_expo_p1[1:13]) //LAT-- + ); + + tri_nand2_nlats #(.WIDTH(3), .NEEDS_SRESET(0)) ex6_ovctl_lat( + .vd(vdd), + .gd(gnd), + .lclk(ex6_lclk), //lclk.clk + .d1clk(ex6_d1clk), + .d2clk(ex6_d2clk), + .scanin(ex6_ovctl_si), + .scanout(ex6_ovctl_so), + //----------------- + .a1({ex5_ovf_calc_0_b, + ex5_ovf_if_calc_0_b, + ex5_unf_calc_0_b}), + //----------------- + .a2({ex5_ovf_calc_1_b, + ex5_ovf_if_calc_1_b, + ex5_unf_calc_1_b}), + //----------------- + .qb({ex6_ovf_calc, //LAT-- + ex6_ovf_if_calc, //LAT-- + ex6_unf_calc}) //LAT-- + ); + + + tri_rlmreg_p #(.WIDTH(13), .NEEDS_SRESET(0)) ex6_misc_lat( + .force_t(force_t), // tidn, + .d_mode(tiup), + .delay_lclkr(delay_lclkr[5]), // tidn, + .mpw1_b(mpw1_b[5]), // tidn, + .mpw2_b(mpw2_b[1]), // tidn, + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + .act(ex5_act), + .scout(ex6_misc_so), + .scin(ex6_misc_si), + //----------------- + .din({ ex5_unf_tbl, + ex5_unf_tbl_spec_e, + ex5_ov_en, + ex5_ov_en_oe0, + ex5_sel_ov_spec, + ex5_unf_en_nedge, + ex5_unf_ue0_nestsp, + ex5_sel_k_part_f, + ex5_ue1oe1_k[3:7]}), + //----------------- + .dout({ ex6_unf_tbl, //LAT-- + ex6_unf_tbl_spec_e, //LAT-- + ex6_ov_en, //LAT-- + ex6_ov_en_oe0, //LAT-- + ex6_sel_ov_spec, //LAT-- + ex6_unf_en_nedge, //LAT-- + ex6_unf_ue0_nestsp, //LAT-- + ex6_sel_k_part_f, //LAT-- + ex6_ue1oe1_k[3:7]}) //LAT-- + ); + + ////############################################## + ////# EX6 logic + ////############################################## + + assign f_eov_ex6_expo_p0[1:13] = ex6_expo_p0[1:13]; ////#rnd result exponent + assign f_eov_ex6_expo_p1[1:13] = ex6_expo_p1[1:13]; ////#rnd result exponent if rnd_up_all1 + + ////#----------------------------------------- + ////# moved from ex5 to ex6 for timing + ////#----------------------------------------- + + //------- LEVEL 1 ----------------------------------- + + assign ex6_sel_ov_spec_b = (~(ex6_sel_ov_spec)); + assign ex6_ovf_b = (~(ex6_ovf_calc & ex6_ov_en)); + assign ex6_ovf_if_b = (~(ex6_ovf_if_calc & ex6_ov_en)); + assign ex6_ovf_oe0_b = (~(ex6_ovf_calc & ex6_ov_en_oe0)); + assign ex6_ovf_if_oe0_b = (~(ex6_ovf_if_calc & ex6_ov_en_oe0)); + assign ex6_unf_b = (~(ex6_unf_calc & ex6_unf_en_nedge)); + assign ex6_unf_ue0_b = (~(ex6_unf_calc & ex6_unf_ue0_nestsp)); + assign ex6_sel_k_part_f_b = (~(ex6_sel_k_part_f)); + assign ex6_unf_tbl_spec_e_b = (~(ex6_unf_tbl_spec_e)); + assign ex6_unf_tbl_b = (~(ex6_unf_tbl)); + + //------- LEVEL 2 ----------------------------------- + + assign f_eov_ex6_ovf_expo = (~(ex6_ovf_b & ex6_sel_ov_spec_b)); + assign f_eov_ex6_ovf_if_expo = (~(ex6_ovf_if_b & ex6_sel_ov_spec_b)); + assign f_eov_ex6_sel_k_f = (~(ex6_ovf_oe0_b & ex6_sel_k_part_f_b)); + assign f_eov_ex6_sel_kif_f = (~(ex6_ovf_if_oe0_b & ex6_sel_k_part_f_b)); + assign f_eov_ex6_unf_expo = (~(ex6_unf_b & ex6_unf_tbl_b)); + assign f_eov_ex6_sel_k_e = (~(ex6_unf_ue0_b & ex6_unf_tbl_spec_e_b & ex6_ovf_oe0_b)); + assign f_eov_ex6_sel_kif_e = (~(ex6_unf_ue0_b & ex6_unf_tbl_spec_e_b & ex6_ovf_if_oe0_b)); + + ////#----------------------------- + ////# ue1 oe1 adders (does not need to be real fast) + ////#----------------------------- + + assign f_eov_ex6_expo_p0_ue1oe1[3:6] = ex6_ue1oe1_p0_p[3:6] ^ ex6_ue1oe1_p0_c[4:7]; //output- + assign f_eov_ex6_expo_p0_ue1oe1[7] = ex6_ue1oe1_p0_p[7]; + + assign ex6_ue1oe1_p0_p[3:7] = ex6_expo_p0[3:7] ^ ex6_ue1oe1_k[3:7]; + assign ex6_ue1oe1_p0_g[4:7] = ex6_expo_p0[4:7] & ex6_ue1oe1_k[4:7]; + assign ex6_ue1oe1_p0_t[4:6] = ex6_expo_p0[4:6] | ex6_ue1oe1_k[4:6]; + + assign ex6_ue1oe1_p0_g2_b[7] = (~(ex6_ue1oe1_p0_g[7])); + assign ex6_ue1oe1_p0_g2_b[6] = (~(ex6_ue1oe1_p0_g[6] | (ex6_ue1oe1_p0_t[6] & ex6_ue1oe1_p0_g[7]))); + assign ex6_ue1oe1_p0_g2_b[5] = (~(ex6_ue1oe1_p0_g[5])); + assign ex6_ue1oe1_p0_g2_b[4] = (~(ex6_ue1oe1_p0_g[4] | (ex6_ue1oe1_p0_t[4] & ex6_ue1oe1_p0_g[5]))); + + assign ex6_ue1oe1_p0_t2_b[5] = (~(ex6_ue1oe1_p0_t[5])); + assign ex6_ue1oe1_p0_t2_b[4] = (~((ex6_ue1oe1_p0_t[4] & ex6_ue1oe1_p0_t[5]))); + + assign ex6_ue1oe1_p0_c[7] = (~(ex6_ue1oe1_p0_g2_b[7])); + assign ex6_ue1oe1_p0_c[6] = (~(ex6_ue1oe1_p0_g2_b[6])); + assign ex6_ue1oe1_p0_c[5] = (~(ex6_ue1oe1_p0_g2_b[5] & (ex6_ue1oe1_p0_t2_b[5] | ex6_ue1oe1_p0_g2_b[6]))); + assign ex6_ue1oe1_p0_c[4] = (~(ex6_ue1oe1_p0_g2_b[4] & (ex6_ue1oe1_p0_t2_b[4] | ex6_ue1oe1_p0_g2_b[6]))); + + //------------------- + + assign f_eov_ex6_expo_p1_ue1oe1[3:6] = ex6_ue1oe1_p1_p[3:6] ^ ex6_ue1oe1_p1_c[4:7]; //output- + assign f_eov_ex6_expo_p1_ue1oe1[7] = ex6_ue1oe1_p1_p[7]; + + assign ex6_ue1oe1_p1_p[3:7] = ex6_expo_p1[3:7] ^ ex6_ue1oe1_k[3:7]; + assign ex6_ue1oe1_p1_g[4:7] = ex6_expo_p1[4:7] & ex6_ue1oe1_k[4:7]; + assign ex6_ue1oe1_p1_t[4:6] = ex6_expo_p1[4:6] | ex6_ue1oe1_k[4:6]; + + assign ex6_ue1oe1_p1_g2_b[7] = (~(ex6_ue1oe1_p1_g[7])); + assign ex6_ue1oe1_p1_g2_b[6] = (~(ex6_ue1oe1_p1_g[6] | (ex6_ue1oe1_p1_t[6] & ex6_ue1oe1_p1_g[7]))); + assign ex6_ue1oe1_p1_g2_b[5] = (~(ex6_ue1oe1_p1_g[5])); + assign ex6_ue1oe1_p1_g2_b[4] = (~(ex6_ue1oe1_p1_g[4] | (ex6_ue1oe1_p1_t[4] & ex6_ue1oe1_p1_g[5]))); + + assign ex6_ue1oe1_p1_t2_b[5] = (~(ex6_ue1oe1_p1_t[5])); + assign ex6_ue1oe1_p1_t2_b[4] = (~((ex6_ue1oe1_p1_t[4] & ex6_ue1oe1_p1_t[5]))); + + assign ex6_ue1oe1_p1_c[7] = (~(ex6_ue1oe1_p1_g2_b[7])); + assign ex6_ue1oe1_p1_c[6] = (~(ex6_ue1oe1_p1_g2_b[6])); + assign ex6_ue1oe1_p1_c[5] = (~(ex6_ue1oe1_p1_g2_b[5] & (ex6_ue1oe1_p1_t2_b[5] | ex6_ue1oe1_p1_g2_b[6]))); + assign ex6_ue1oe1_p1_c[4] = (~(ex6_ue1oe1_p1_g2_b[4] & (ex6_ue1oe1_p1_t2_b[4] | ex6_ue1oe1_p1_g2_b[6]))); + + ////############################################ + ////# scan + ////############################################ + + assign act_si[0:4] = {act_so[1:4], f_eov_si}; + assign ex5_iexp_si[0:15] = {ex5_iexp_so[1:15], act_so[0]}; + assign ex6_ovctl_si[0:2] = {ex6_ovctl_so[1:2], ex5_iexp_so[0]}; + assign ex6_misc_si[0:12] = {ex6_misc_so[1:12], ex6_ovctl_so[0]}; + assign ex6_urnd0_si[0:12] = {ex6_urnd0_so[1:12], ex6_misc_so[0]}; + assign ex6_urnd1_si[0:12] = {ex6_urnd1_so[1:12], ex6_urnd0_so[0]}; + assign f_eov_so = ex6_urnd1_so[0]; + +endmodule diff --git a/dev/verilog/work/fu_fmt.v b/dev/verilog/work/fu_fmt.v new file mode 100755 index 0000000..4696baa --- /dev/null +++ b/dev/verilog/work/fu_fmt.v @@ -0,0 +1,1469 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// bias 127 0_0000_0111_1111 +// bias 1023 0_0011_1111_1111 infinity=> 0_0111_1111_1111 2047 +// bias 2047 0_0111_1111_1111 infinity=> 0_1111_1111_1111 4095 +// bias 4095 0_1111_1111_1111 infinity=> 1_1111_1111_1111 8191 + + `include "tri_a2o.vh" + + +module fu_fmt( + vdd, + gnd, + clkoff_b, + act_dis, + flush, + delay_lclkr, + mpw1_b, + mpw2_b, + sg_1, + thold_1, + fpu_enable, + nclk, + f_fmt_si, + f_fmt_so, + ex1_act, + ex2_act, + f_dcd_ex2_perr_force_c, // :in std_ulogic; + f_dcd_ex2_perr_fsel_ovrd, // :in std_ulogic; + f_pic_ex2_ftdiv, // :in std_ulogic; + f_fmt_ex3_be_den, // :out std_ulogic + f_byp_fmt_ex2_a_sign, + f_byp_fmt_ex2_c_sign, + f_byp_fmt_ex2_b_sign, + f_byp_fmt_ex2_a_expo, + f_byp_fmt_ex2_c_expo, + f_byp_fmt_ex2_b_expo, + f_byp_fmt_ex2_a_frac, + f_byp_fmt_ex2_c_frac, + f_byp_fmt_ex2_b_frac, + f_dcd_ex1_aop_valid, + f_dcd_ex1_cop_valid, + f_dcd_ex1_bop_valid, + f_dcd_ex1_from_integer_b, + f_dcd_ex1_fsel_b, + f_dcd_ex1_force_pass_b, + f_dcd_ex1_sp, + f_pic_ex2_flush_en_sp, + f_pic_ex2_flush_en_dp, + f_pic_ex2_nj_deni, + f_dcd_ex1_uc_end, + f_dcd_ex1_uc_mid, + f_dcd_ex1_uc_special, + f_dcd_ex1_sgncpy_b, + f_dcd_ex2_divsqrt_v, + f_fmt_ex3_lu_den_recip, + f_fmt_ex3_lu_den_rsqrto, + f_fmt_ex2_bop_byt, + f_fmt_ex2_a_zero, + f_fmt_ex2_a_zero_dsq, + f_fmt_ex2_a_expo_max, + f_fmt_ex2_a_expo_max_dsq, + f_fmt_ex2_a_frac_zero, + f_fmt_ex2_a_frac_msb, + f_fmt_ex2_c_zero, + f_fmt_ex2_c_expo_max, + f_fmt_ex2_c_frac_zero, + f_fmt_ex2_c_frac_msb, + f_fmt_ex2_b_zero, + f_fmt_ex2_b_zero_dsq, + f_fmt_ex2_b_expo_max, + f_fmt_ex2_b_expo_max_dsq, + f_fmt_ex2_b_frac_zero, + f_fmt_ex2_b_frac_msb, + f_fmt_ex2_b_imp, + f_fmt_ex2_b_frac_z32, + f_fmt_ex2_prod_zero, + f_fmt_ex2_pass_sel, + f_fmt_ex2_sp_invalid, + f_fmt_ex2_bexpu_le126, + f_fmt_ex2_gt126, + f_fmt_ex2_ge128, + f_fmt_ex2_inf_and_beyond_sp, + f_mad_ex3_uc_a_expo_den, + f_mad_ex3_uc_a_expo_den_sp, + f_ex3_b_den_flush, + f_fmt_ex3_fsel_bsel, + f_fmt_ex3_pass_sign, + f_fmt_ex3_pass_msb, + f_fmt_ex2_b_frac, + f_fmt_ex2_b_sign_gst, + f_fmt_ex2_b_expo_gst_b, + f_fmt_ex2_a_sign_div, + f_fmt_ex2_a_expo_div_b, + f_fmt_ex2_a_frac_div, + f_fmt_ex2_b_sign_div, + f_fmt_ex2_b_expo_div_b, + f_fmt_ex2_b_frac_div, + f_fpr_ex2_a_par, + f_fpr_ex2_c_par, + f_fpr_ex2_b_par, + f_mad_ex3_a_parity_check, + f_mad_ex3_c_parity_check, + f_mad_ex3_b_parity_check, + f_fmt_ex3_ae_ge_54, + f_fmt_ex3_be_ge_54, + f_fmt_ex3_be_ge_2, + f_fmt_ex3_be_ge_2044, + f_fmt_ex3_tdiv_rng_chk, + f_fmt_ex3_pass_frac +); + inout vdd; + inout gnd; + input clkoff_b; // tiup + input act_dis; // ??tidn?? + input flush; // ??tidn?? + input [1:2] delay_lclkr; // tidn, + input [1:2] mpw1_b; // tidn, + input [0:0] mpw2_b; // tidn, + input sg_1; + input thold_1; + input fpu_enable; //dc_act + input [0:`NCLK_WIDTH-1] nclk; + + input f_fmt_si; //perv + output f_fmt_so; //perv + + input ex1_act; + input ex2_act; + input f_dcd_ex2_perr_force_c; // :in std_ulogic; + input f_dcd_ex2_perr_fsel_ovrd; // :in std_ulogic; + input f_pic_ex2_ftdiv; // :in std_ulogic; + output f_fmt_ex3_be_den; // :out std_ulogic + input f_byp_fmt_ex2_a_sign; + input f_byp_fmt_ex2_c_sign; + input f_byp_fmt_ex2_b_sign; + input [1:13] f_byp_fmt_ex2_a_expo; + input [1:13] f_byp_fmt_ex2_c_expo; + input [1:13] f_byp_fmt_ex2_b_expo; + input [0:52] f_byp_fmt_ex2_a_frac; + input [0:52] f_byp_fmt_ex2_c_frac; + input [0:52] f_byp_fmt_ex2_b_frac; + + input f_dcd_ex1_aop_valid; + input f_dcd_ex1_cop_valid; + input f_dcd_ex1_bop_valid; + input f_dcd_ex1_from_integer_b; //no NAN + input f_dcd_ex1_fsel_b; //modify nan mux + input f_dcd_ex1_force_pass_b; //force select of nan mux (fmr) + + input f_dcd_ex1_sp; + + input f_pic_ex2_flush_en_sp; + input f_pic_ex2_flush_en_dp; + + input f_pic_ex2_nj_deni; + input f_dcd_ex1_uc_end; + input f_dcd_ex1_uc_mid; + input f_dcd_ex1_uc_special; + input f_dcd_ex1_sgncpy_b; + input f_dcd_ex2_divsqrt_v; + output f_fmt_ex3_lu_den_recip; //pic + output f_fmt_ex3_lu_den_rsqrto; //pic + + output [45:52] f_fmt_ex2_bop_byt; // shadow reg + + output f_fmt_ex2_a_zero; //pic + output f_fmt_ex2_a_zero_dsq; //pic + + output f_fmt_ex2_a_expo_max; //pic + output f_fmt_ex2_a_expo_max_dsq; //pic + output f_fmt_ex2_a_frac_zero; //pic + output f_fmt_ex2_a_frac_msb; //pic + + output f_fmt_ex2_c_zero; //pic + output f_fmt_ex2_c_expo_max; //pic + output f_fmt_ex2_c_frac_zero; //pic + output f_fmt_ex2_c_frac_msb; //pic + + output f_fmt_ex2_b_zero; //pic + output f_fmt_ex2_b_zero_dsq; //pic + + output f_fmt_ex2_b_expo_max; //pic + output f_fmt_ex2_b_expo_max_dsq; //pic + + output f_fmt_ex2_b_frac_zero; //pic + output f_fmt_ex2_b_frac_msb; //pic + output f_fmt_ex2_b_imp; //pic-- + output f_fmt_ex2_b_frac_z32; //pic-- + + output f_fmt_ex2_prod_zero; //alg + output f_fmt_ex2_pass_sel; //alg + + output f_fmt_ex2_sp_invalid; //pic + output f_fmt_ex2_bexpu_le126; //pic + output f_fmt_ex2_gt126; //pic + output f_fmt_ex2_ge128; //pic + output f_fmt_ex2_inf_and_beyond_sp; //pic + + output f_mad_ex3_uc_a_expo_den; //dvSq input operand is already prenormed + output f_mad_ex3_uc_a_expo_den_sp; //dvSq input operand is already prenormed + //exponent negative or all zeroes + + output f_ex3_b_den_flush; //iu (does not include all gating) ??? + + output f_fmt_ex3_fsel_bsel; //pic--expo + output f_fmt_ex3_pass_sign; //alg + output f_fmt_ex3_pass_msb; //alg + output [1:19] f_fmt_ex2_b_frac; //clz (est) + output f_fmt_ex2_b_sign_gst; + output [1:13] f_fmt_ex2_b_expo_gst_b; + + output f_fmt_ex2_a_sign_div; + output [01:13] f_fmt_ex2_a_expo_div_b; + output [01:52] f_fmt_ex2_a_frac_div; + + output f_fmt_ex2_b_sign_div; + output [01:13] f_fmt_ex2_b_expo_div_b; + output [01:52] f_fmt_ex2_b_frac_div; + + input [0:7] f_fpr_ex2_a_par; + input [0:7] f_fpr_ex2_c_par; + input [0:7] f_fpr_ex2_b_par; + output f_mad_ex3_a_parity_check; // raw calculation + output f_mad_ex3_c_parity_check; // raw calculation + output f_mad_ex3_b_parity_check; // raw calculation + + output f_fmt_ex3_ae_ge_54; //unbiased exponent not LE -970 + output f_fmt_ex3_be_ge_54; //unbiased exponent not LE -970 + output f_fmt_ex3_be_ge_2; //unbiased exponent not le 1 + output f_fmt_ex3_be_ge_2044; //unbiased exponent ge 1023 + output f_fmt_ex3_tdiv_rng_chk; //unbiased exponent ae-be >= 1023, <= -1021 + output [0:52] f_fmt_ex3_pass_frac; //alg + + // ENTITY + + + parameter tiup = 1'b1; + parameter tidn = 1'b0; + + wire thold_0_b; + wire thold_0; + wire force_t; + wire sg_0; + + + (* analysis_not_referenced="TRUE" *) + wire [0:3] spare_unused; + //-------------------------------------- + wire [0:6] act_si; //SCAN + wire [0:6] act_so; //SCAN + + wire [0:8] ex2_ctl_si; //SCAN + wire [0:8] ex2_ctl_so; //SCAN + wire [0:79] ex3_pass_si; //SCAN + wire [0:79] ex3_pass_so; //SCAN + //-------------------------------------- + wire [0:52] ex3_pass_frac; + wire ex2_from_integer; + wire ex2_fsel; + wire ex2_force_pass; + wire ex2_a_sign; + wire ex2_c_sign; + wire ex2_b_sign; + wire ex3_fsel_bsel; + wire ex3_pass_sign; + //-------------------------------------- + wire [0:52] ex2_a_frac; + wire [0:52] ex2_c_frac; + wire [0:52] ex2_b_frac; + wire [0:52] ex2_pass_frac_ac; + wire [0:52] ex2_pass_frac; + wire ex2_a_frac_msb; + wire ex2_a_expo_min; + wire ex2_a_expo_max; + wire ex2_a_expo_max_dsq; + wire ex2_a_frac_zero; + wire ex2_c_frac_msb; + wire ex2_c_expo_min; + wire ex2_c_expo_max; + wire ex2_c_frac_zero; + wire ex2_b_frac_msb; + wire ex2_b_expo_min; + wire ex2_b_expo_max; + wire ex2_b_expo_max_dsq; + wire ex2_b_frac_zero; + wire ex2_b_frac_z32; + wire ex2_a_nan; + wire ex2_c_nan; + wire ex2_b_nan; + wire ex2_nan_pass; + wire ex2_pass_sel; + wire ex2_fsel_cif; + wire ex2_fsel_bsel; + wire ex2_mux_a_sel; + wire ex2_mux_c_sel; + wire ex2_pass_sign_ac; + wire ex2_pass_sign; + wire [1:13] ex2_a_expo; + wire [1:13] ex2_b_expo; + wire [1:13] ex2_c_expo; + wire [1:13] ex2_a_expo_b; + wire [1:13] ex2_c_expo_b; + wire [1:13] ex2_b_expo_b; + wire ex1_aop_valid_b; + wire ex1_cop_valid_b; + wire ex1_bop_valid_b; + wire ex2_aop_valid; + wire ex2_cop_valid; + wire ex2_bop_valid; + wire ex2_a_zero; + wire ex2_c_zero; + wire ex2_b_zero; + wire ex2_a_zero_x; + wire ex2_c_zero_x; + wire ex2_b_zero_x; + wire ex2_a_sp_expo_ok_1; + wire ex2_c_sp_expo_ok_1; + wire ex2_b_sp_expo_ok_1; + wire ex2_a_sp_expo_ok_2; + wire ex2_c_sp_expo_ok_2; + wire ex2_b_sp_expo_ok_2; + wire ex2_a_sp_expo_ok_3; + wire ex2_c_sp_expo_ok_3; + wire ex2_b_sp_expo_ok_3; + wire ex2_a_sp_expo_ok_4; + wire ex2_c_sp_expo_ok_4; + wire ex2_b_sp_expo_ok_4; + wire [0:52] ex3_pass_dp; + wire ex2_from_integer_b; + wire ex2_fsel_b; + wire ex2_aop_valid_b; + wire ex2_cop_valid_b; + wire ex2_bop_valid_b; + wire ex2_b_den_flush; + wire ex2_b_den_sp; + wire ex2_b_den_dp; + wire ex2_a_den_sp; + wire ex2_be_den; + wire ex3_be_den; + wire ex3_b_den_flush; + wire ex2_a_den_flush; + wire ex2_a_den_sp_ftdiv; + wire ex2_a_den_dp; + + wire ex2_lu_den_part; + wire ex2_lu_den_recip; + wire ex2_lu_den_rsqrto; + wire ex3_lu_den_recip; + wire ex3_lu_den_rsqrto; + wire ex2_recip_lo; + wire ex2_rsqrt_lo; + wire ex2_bfrac_eq_126; + wire ex2_bfrac_126_nz; + wire ex2_bexpo_ge897_hi; + wire ex2_bexpo_ge897_mid1; + wire ex2_bexpo_ge897_mid2; + wire ex2_bexpo_ge897_lo; + wire ex2_bexpo_ge897; + wire ex2_bexpu_eq6; + wire ex2_bexpu_ge7; + wire ex2_bexpu_ge7_lo; + wire ex2_bexpu_ge7_mid; + wire ex2_a_sp; + wire ex2_c_sp; + wire ex2_b_sp; + wire ex2_b_frac_zero_sp; + wire ex2_b_frac_zero_dp; + wire ex2_a_denz; + wire ex2_c_denz; + wire ex2_b_denz; + wire [0:52] ex2_a_frac_chop; + wire [0:52] ex2_c_frac_chop; + wire [0:52] ex2_b_frac_chop; + + wire ex1_sgncpy; + wire ex2_sgncpy; + wire ex2_uc_mid; + wire ex1_force_pass; + wire ex1_uc_end_nspec; + wire ex1_uc_end_spec; + wire ex2_uc_end_nspec; + wire ex2_uc_a_expo_den; + wire ex3_uc_a_expo_den; + wire ex2_uc_a_expo_den_sp; + wire ex3_uc_a_expo_den_sp; + + wire ex2_a_expo_ltx381_sp; + wire ex2_a_expo_ltx381; + wire ex2_a_expo_00xx_xxxx_xxxx; + wire ex2_a_expo_xx11_1xxx_xxxx; + wire ex2_a_expo_xxxx_x000_0000; + wire ex2_c_expo_ltx381_sp; + wire ex2_c_expo_ltx381; + wire ex2_c_expo_00xx_xxxx_xxxx; + wire ex2_c_expo_xx11_1xxx_xxxx; + wire ex2_c_expo_xxxx_x000_0000; + wire ex2_b_expo_ltx381_sp; + wire ex2_b_expo_ltx381; + wire ex2_b_expo_00xx_xxxx_xxxx; + wire ex2_b_expo_xx11_1xxx_xxxx; + wire ex2_b_expo_xxxx_x000_0000; + wire ex2_a_expo_ltx36A_sp; + wire ex2_b_expo_ltx36A_sp; + + wire ex2_a_sp_inf_alias_tail; + wire ex2_c_sp_inf_alias_tail; + wire ex2_b_sp_inf_alias_tail; + wire ex3_a_party_chick; + wire ex3_c_party_chick; + wire ex3_b_party_chick; + wire ex2_a_party_chick; + wire ex2_c_party_chick; + wire ex2_b_party_chick; + wire [0:7] ex2_a_party; + wire [0:7] ex2_c_party; + wire [0:7] ex2_b_party; + wire ex2_b_expo_ge1151; + wire ex2_ae_234567; + wire ex2_ae_89; + wire ex2_ae_abc; + wire ex2_ae_ge_54; + wire ex3_ae_ge_54; + wire ex2_be_234567; + wire ex2_be_89; + wire ex2_be_abc; + wire ex2_be_ge_54; + wire ex3_be_ge_54; + wire ex2_be_ge_2; + wire ex3_be_ge_2; + wire ex2_be_or_23456789abc; + wire ex2_be_ge_2044; + wire ex3_be_ge_2044; + wire ex2_be_and_3456789ab; + wire [0:12] ex2_aembex_car_b; + wire [0:12] ex2_aembey_car_b; + wire [1:13] ex2_aembex_sum_b; + wire [1:13] ex2_aembey_sum_b; + wire [2:12] ex2_aembex_g1; + wire [2:12] ex2_aembey_g1; + wire [2:12] ex2_aembex_t1; + wire [2:12] ex2_aembey_t1; + wire [0:5] ex2_aembex_g2; + wire [0:5] ex2_aembey_g2; + wire [0:4] ex2_aembex_t2; + wire [0:4] ex2_aembey_t2; + wire [0:2] ex2_aembex_g4; + wire [0:2] ex2_aembey_g4; + wire [0:1] ex2_aembex_t4; + wire [0:1] ex2_aembey_t4; + wire [0:2] ex3_aembex_g4; + wire [0:2] ex3_aembey_g4; + wire [0:1] ex3_aembex_t4; + wire [0:1] ex3_aembey_t4; + wire [0:1] ex3_aembex_g8; + wire [0:1] ex3_aembey_g8; + wire [0:0] ex3_aembex_t8; + wire [0:0] ex3_aembey_t8; + wire ex3_aembex_c2; + wire ex3_aembey_c2; + wire ex2_aembex_sgn; + wire ex2_aembey_sgn; + wire ex3_aembex_sgn; + wire ex3_aembey_sgn; + wire ex3_aembex_res_sgn; + wire ex3_aembey_res_sgn; + (* analysis_not_referenced="TRUE" *) // unused + wire unused; + wire ex2_divsqrt; + + //#=############################################################## + //# map block attributes + //#=############################################################## + + assign unused = ex2_aembex_car_b[0] | ex2_aembex_sum_b[13] | ex2_aembex_t1[12] | ex2_aembey_car_b[0] | ex2_aembey_sum_b[13] | ex2_aembey_t1[12]; + + //#=############################################################## + //# pervasive + //#=############################################################## + + + tri_plat thold_reg_0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(flush), + .din(thold_1), + .q(thold_0) + ); + + + tri_plat sg_reg_0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(flush), + .din(sg_1), + .q(sg_0) + ); + + + tri_lcbor lcbor_0( + .clkoff_b(clkoff_b), + .thold(thold_0), + .sg(sg_0), + .act_dis(act_dis), + .force_t(force_t), + .thold_b(thold_0_b) + ); + + //#=############################################################## + //# act + //#=############################################################## + + + + tri_rlmreg_p #(.WIDTH(7), .NEEDS_SRESET(0)) act_lat( + .force_t(force_t), //i-- tidn, + .d_mode(tiup), + .delay_lclkr(delay_lclkr[1]), //i-- tidn, + .mpw1_b(mpw1_b[1]), //i-- tidn, + .mpw2_b(mpw2_b[0]), //i-- tidn, + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(fpu_enable), + .thold_b(thold_0_b), + .sg(sg_0), + .scout(act_so), + .scin(act_si), + //----------------- + .din({ spare_unused[0], + spare_unused[1], + f_dcd_ex1_sp, + f_dcd_ex1_sp, + f_dcd_ex1_sp, + spare_unused[2], + spare_unused[3]}), + //----------------- + .dout({ spare_unused[0], + spare_unused[1], + ex2_a_sp, + ex2_c_sp, + ex2_b_sp, + spare_unused[2], + spare_unused[3]}) + ); + + //#=############################################################## + //# ex1 logic (after bypass) + //#=############################################################## + + assign ex1_aop_valid_b = (~f_dcd_ex1_aop_valid); + assign ex1_cop_valid_b = (~f_dcd_ex1_cop_valid); + assign ex1_bop_valid_b = (~f_dcd_ex1_bop_valid); + + //#=############################################################## + //# ex2 latches (from ex1 logic) + //#=############################################################## + + assign ex2_a_frac[0:52] = f_byp_fmt_ex2_a_frac[0:52]; + assign ex2_c_frac[0:52] = f_byp_fmt_ex2_c_frac[0:52]; + assign ex2_b_frac[0:52] = f_byp_fmt_ex2_b_frac[0:52]; + + assign ex2_a_sign = f_byp_fmt_ex2_a_sign; //rename-- + assign ex2_c_sign = f_byp_fmt_ex2_c_sign; //rename-- + assign ex2_b_sign = f_byp_fmt_ex2_b_sign; //rename-- + + assign ex2_a_expo[1:13] = f_byp_fmt_ex2_a_expo[1:13]; //rename-- + assign ex2_c_expo[1:13] = f_byp_fmt_ex2_c_expo[1:13]; //rename-- + assign ex2_b_expo[1:13] = f_byp_fmt_ex2_b_expo[1:13]; //rename-- + + assign ex2_a_expo_b[1:13] = (~ex2_a_expo[1:13]); + assign ex2_c_expo_b[1:13] = (~ex2_c_expo[1:13]); + assign ex2_b_expo_b[1:13] = (~ex2_b_expo[1:13]); + + assign f_fmt_ex2_b_sign_gst = ex2_b_sign; + + assign ex1_sgncpy = (~f_dcd_ex1_sgncpy_b); + assign ex1_uc_end_nspec = f_dcd_ex1_uc_end & (~f_dcd_ex1_uc_special); + assign ex1_uc_end_spec = f_dcd_ex1_uc_end & f_dcd_ex1_uc_special; + assign ex1_force_pass = ((~f_dcd_ex1_force_pass_b)) | ex1_uc_end_spec; + + + tri_rlmreg_p #(.WIDTH(9), .NEEDS_SRESET(0)) ex2_ctl_lat( + .force_t(force_t), //i-- tidn, + .d_mode(tiup), + .delay_lclkr(delay_lclkr[1]), //i-- tidn, + .mpw1_b(mpw1_b[1]), //i-- tidn, + .mpw2_b(mpw2_b[0]), //i-- tidn, + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_act), + .thold_b(thold_0_b), + .sg(sg_0), + .scout(ex2_ctl_so), + .scin(ex2_ctl_si), + //----------------- + .din({ f_dcd_ex1_from_integer_b, + f_dcd_ex1_fsel_b, + ex1_force_pass, + ex1_aop_valid_b, + ex1_cop_valid_b, + ex1_bop_valid_b, + ex1_sgncpy, + ex1_uc_end_nspec, + f_dcd_ex1_uc_mid}), + //----------------- + .dout({ ex2_from_integer_b, + ex2_fsel_b, + ex2_force_pass, + ex2_aop_valid_b, + ex2_cop_valid_b, + ex2_bop_valid_b, + ex2_sgncpy, + ex2_uc_end_nspec, + ex2_uc_mid}) + ); + + assign ex2_from_integer = (~ex2_from_integer_b); + assign ex2_fsel = (~ex2_fsel_b); + assign ex2_aop_valid = (~ex2_aop_valid_b); + assign ex2_cop_valid = (~ex2_cop_valid_b); + assign ex2_bop_valid = (~ex2_bop_valid_b); + + //#=############################################################## + //# ex2 logic + //#=############################################################## + assign f_fmt_ex2_bop_byt[45:52] = ex2_b_frac[45:52]; //output-- -- shadow reg + + //#=----------------------------------------------------------------- + //#= Boundary conditions for log2e/pow2e special cases + //#=----------------------------------------------------------------- + //#= exponent Lt 2**-126 ... -126 +1023 = 897 (sp denorms) x 0_0011_1000_0001 + //#= number less than -126 (2**6) <64>.<32><16>(8><4><2> + //#= x0_0011_1111_1111 bias = 1023 + //#= x0_0000_0000_0110 unbiased + //#= ----------------- + //#= x0_0100_0000_0101 biased 6 + + assign f_fmt_ex2_b_expo_gst_b[1:13] = (~ex2_b_expo[1:13]); + + // positive exponent + assign ex2_bexpo_ge897_hi = (~ex2_b_expo[1]) & ex2_b_frac[0]; // must be normalized (897 includes sp denorms) + assign ex2_bexpo_ge897_mid1 = ex2_b_expo[2] | ex2_b_expo[3]; + assign ex2_bexpo_ge897_mid2 = ex2_b_expo[4] & ex2_b_expo[5] & ex2_b_expo[6]; + assign ex2_bexpo_ge897_lo = ex2_b_expo[7] | ex2_b_expo[8] | ex2_b_expo[9] | ex2_b_expo[10] | ex2_b_expo[11] | ex2_b_expo[12] | ex2_b_expo[13]; + assign ex2_bexpo_ge897 = (ex2_bexpo_ge897_hi & ex2_bexpo_ge897_mid1) | (ex2_bexpo_ge897_hi & ex2_bexpo_ge897_mid2 & ex2_bexpo_ge897_lo); + + assign ex2_bexpu_ge7_mid = ex2_b_expo[4] | ex2_b_expo[5] | ex2_b_expo[6] | ex2_b_expo[7] | ex2_b_expo[8] | ex2_b_expo[9] | ex2_b_expo[10]; + assign ex2_bexpu_ge7_lo = ex2_b_expo[11] & ex2_b_expo[12]; + + assign ex2_bexpu_ge7 = ((~ex2_b_expo[1]) & ex2_b_expo[2]) | ((~ex2_b_expo[1]) & ex2_b_expo[3] & ex2_bexpu_ge7_mid) | ((~ex2_b_expo[1]) & ex2_b_expo[3] & ex2_bexpu_ge7_lo); + + // 0_0100_0000_0101 1023+6 - 1024+5 + // +expo + // 2048 + // 1024 + // 512 + // 256 + // 128 + // 64 + // 32 + // 16 + // 8 + // 4 + assign ex2_bexpu_eq6 = (~ex2_b_expo[1]) & (~ex2_b_expo[2]) & ex2_b_expo[3] & (~ex2_b_expo[4]) & (~ex2_b_expo[5]) & (~ex2_b_expo[6]) & (~ex2_b_expo[7]) & (~ex2_b_expo[8]) & (~ex2_b_expo[9]) & (~ex2_b_expo[10]) & ex2_b_expo[11] & (~ex2_b_expo[12]) & ex2_b_expo[13]; // 2 + // 1 + + assign f_fmt_ex2_bexpu_le126 = (~ex2_bexpo_ge897); //output-- + assign f_fmt_ex2_gt126 = ex2_bexpu_ge7 | (ex2_bexpu_eq6 & ex2_bfrac_eq_126 & ex2_bfrac_126_nz); //output-- + assign f_fmt_ex2_ge128 = ex2_bexpu_ge7; //output-- + + // exponent >= 1023 + 128 = 1151 (1024+127) + // 1 2345 6789 abcd + // 0_0100_0111 _1111 <-- 1151 aliases to sp infinity/nan range + // 0_1xxx_xxxx_xxxx + // 0_x11x_xxxx_xxxx + // 0_x1x1_xxxx_xxxx + // 0_x1xx_1xxx_xxxx + assign ex2_b_expo_ge1151 = (ex2_b_expo_b[1] & (~ex2_b_expo_b[2])) | (ex2_b_expo_b[1] & (~ex2_b_expo_b[3]) & (~ex2_b_expo_b[4])) | (ex2_b_expo_b[1] & (~ex2_b_expo_b[3]) & (~ex2_b_expo_b[5])) | (ex2_b_expo_b[1] & (~ex2_b_expo_b[3]) & (~ex2_b_expo_b[6])) | (ex2_b_expo_b[1] & (~ex2_b_expo_b[3]) & (~ex2_b_expo_b[7]) & (~ex2_b_expo_b[8]) & (~ex2_b_expo_b[9]) & (~ex2_b_expo_b[10]) & (~ex2_b_expo_b[11]) & (~ex2_b_expo_b[12]) & (~ex2_b_expo_b[13])); // 0_x1xx_x111_1111 + + assign f_fmt_ex2_inf_and_beyond_sp = ex2_b_expo_max | ex2_b_expo_ge1151; + + //64 + //32 + //16 + // 8 + assign ex2_bfrac_eq_126 = ex2_b_frac[0] & ex2_b_frac[1] & ex2_b_frac[2] & ex2_b_frac[3] & ex2_b_frac[4] & ex2_b_frac[5]; // 4 + // 2 + // ex2_b_frac(6) ; -- 1 + + assign ex2_bfrac_126_nz = ex2_b_frac[6] | ex2_b_frac[7] | ex2_b_frac[8] | ex2_b_frac[9] | ex2_b_frac[10] | ex2_b_frac[11] | ex2_b_frac[12] | ex2_b_frac[13] | ex2_b_frac[14] | ex2_b_frac[15] | ex2_b_frac[16] | ex2_b_frac[17] | ex2_b_frac[18] | ex2_b_frac[19] | ex2_b_frac[20] | ex2_b_frac[21] | ex2_b_frac[22] | ex2_b_frac[23]; + + //#=-------------------------------------------------- + //#= all1/all0 determination + //#=-------------------------------------------------- + + assign ex2_a_frac_msb = ex2_a_frac[1]; + assign ex2_c_frac_msb = ex2_c_frac[1]; + assign ex2_b_frac_msb = ex2_b_frac[1]; + + assign ex2_a_expo_min = (~ex2_a_frac[0]); // implicit bit off + assign ex2_c_expo_min = (~ex2_c_frac[0]); + assign ex2_b_expo_min = (~ex2_b_frac[0]); + + assign ex2_a_expo_max = ex2_a_expo_b[1] & ex2_a_expo_b[2] & (~ex2_a_expo_b[3]) & (~ex2_a_expo_b[4]) & (~ex2_a_expo_b[5]) & (~ex2_a_expo_b[6]) & (~ex2_a_expo_b[7]) & (~ex2_a_expo_b[8]) & (~ex2_a_expo_b[9]) & (~ex2_a_expo_b[10]) & (~ex2_a_expo_b[11]) & (~ex2_a_expo_b[12]) & (~ex2_a_expo_b[13]); + + assign ex2_c_expo_max = ex2_c_expo_b[1] & ex2_c_expo_b[2] & (~ex2_c_expo_b[3]) & (~ex2_c_expo_b[4]) & (~ex2_c_expo_b[5]) & (~ex2_c_expo_b[6]) & (~ex2_c_expo_b[7]) & (~ex2_c_expo_b[8]) & (~ex2_c_expo_b[9]) & (~ex2_c_expo_b[10]) & (~ex2_c_expo_b[11]) & (~ex2_c_expo_b[12]) & (~ex2_c_expo_b[13]); + + assign ex2_b_expo_max = ex2_b_expo_b[1] & ex2_b_expo_b[2] & (~ex2_b_expo_b[3]) & (~ex2_b_expo_b[4]) & (~ex2_b_expo_b[5]) & (~ex2_b_expo_b[6]) & (~ex2_b_expo_b[7]) & (~ex2_b_expo_b[8]) & (~ex2_b_expo_b[9]) & (~ex2_b_expo_b[10]) & (~ex2_b_expo_b[11]) & (~ex2_b_expo_b[12]) & (~ex2_b_expo_b[13]); + + // ex2_a_frac( 0) or + assign ex2_a_frac_zero = (~ex2_a_frac[1]) & (~ex2_a_frac[2]) & (~ex2_a_frac[3]) & (~ex2_a_frac[4]) & (~ex2_a_frac[5]) & (~ex2_a_frac[6]) & (~ex2_a_frac[7]) & (~ex2_a_frac[8]) & (~ex2_a_frac[9]) & (~ex2_a_frac[10]) & (~ex2_a_frac[11]) & (~ex2_a_frac[12]) & (~ex2_a_frac[13]) & (~ex2_a_frac[14]) & (~ex2_a_frac[15]) & (~ex2_a_frac[16]) & (~ex2_a_frac[17]) & (~ex2_a_frac[18]) & (~ex2_a_frac[19]) & (~ex2_a_frac[20]) & (~ex2_a_frac[21]) & (~ex2_a_frac[22]) & (~ex2_a_frac[23]) & (~ex2_a_frac[24]) & (~ex2_a_frac[25]) & (~ex2_a_frac[26]) & (~ex2_a_frac[27]) & (~ex2_a_frac[28]) & (~ex2_a_frac[29]) & (~ex2_a_frac[30]) & (~ex2_a_frac[31]) & (~ex2_a_frac[32]) & (~ex2_a_frac[33]) & (~ex2_a_frac[34]) & (~ex2_a_frac[35]) & (~ex2_a_frac[36]) & (~ex2_a_frac[37]) & (~ex2_a_frac[38]) & (~ex2_a_frac[39]) & (~ex2_a_frac[40]) & (~ex2_a_frac[41]) & (~ex2_a_frac[42]) & (~ex2_a_frac[43]) & (~ex2_a_frac[44]) & (~ex2_a_frac[45]) & (~ex2_a_frac[46]) & (~ex2_a_frac[47]) & (~ex2_a_frac[48]) & (~ex2_a_frac[49]) & (~ex2_a_frac[50]) & (~ex2_a_frac[51]) & (~ex2_a_frac[52]); // (ex2_a_frac_zero_dp or ex2_a_sp ); ex2_a_frac_zero_dp <= + + // ex2_c_frac( 0) and + assign ex2_c_frac_zero = (~ex2_c_frac[1]) & (~ex2_c_frac[2]) & (~ex2_c_frac[3]) & (~ex2_c_frac[4]) & (~ex2_c_frac[5]) & (~ex2_c_frac[6]) & (~ex2_c_frac[7]) & (~ex2_c_frac[8]) & (~ex2_c_frac[9]) & (~ex2_c_frac[10]) & (~ex2_c_frac[11]) & (~ex2_c_frac[12]) & (~ex2_c_frac[13]) & (~ex2_c_frac[14]) & (~ex2_c_frac[15]) & (~ex2_c_frac[16]) & (~ex2_c_frac[17]) & (~ex2_c_frac[18]) & (~ex2_c_frac[19]) & (~ex2_c_frac[20]) & (~ex2_c_frac[21]) & (~ex2_c_frac[22]) & (~ex2_c_frac[23]) & (~ex2_c_frac[24]) & (~ex2_c_frac[25]) & (~ex2_c_frac[26]) & (~ex2_c_frac[27]) & (~ex2_c_frac[28]) & (~ex2_c_frac[29]) & (~ex2_c_frac[30]) & (~ex2_c_frac[31]) & (~ex2_c_frac[32]) & (~ex2_c_frac[33]) & (~ex2_c_frac[34]) & (~ex2_c_frac[35]) & (~ex2_c_frac[36]) & (~ex2_c_frac[37]) & (~ex2_c_frac[38]) & (~ex2_c_frac[39]) & (~ex2_c_frac[40]) & (~ex2_c_frac[41]) & (~ex2_c_frac[42]) & (~ex2_c_frac[43]) & (~ex2_c_frac[44]) & (~ex2_c_frac[45]) & (~ex2_c_frac[46]) & (~ex2_c_frac[47]) & (~ex2_c_frac[48]) & (~ex2_c_frac[49]) & (~ex2_c_frac[50]) & (~ex2_c_frac[51]) & (~ex2_c_frac[52]); //( ex2_c_frac_zero_dp or ex2_c_sp ); ex2_c_frac_zero_dp <= + + assign ex2_b_frac_zero_sp = (~ex2_b_frac[1]) & (~ex2_b_frac[2]) & (~ex2_b_frac[3]) & (~ex2_b_frac[4]) & (~ex2_b_frac[5]) & (~ex2_b_frac[6]) & (~ex2_b_frac[7]) & (~ex2_b_frac[8]) & (~ex2_b_frac[9]) & (~ex2_b_frac[10]) & (~ex2_b_frac[11]) & (~ex2_b_frac[12]) & (~ex2_b_frac[13]) & (~ex2_b_frac[14]) & (~ex2_b_frac[15]) & (~ex2_b_frac[16]) & (~ex2_b_frac[17]) & (~ex2_b_frac[18]) & (~ex2_b_frac[19]) & (~ex2_b_frac[20]) & (~ex2_b_frac[21]) & (~ex2_b_frac[22]) & (~ex2_b_frac[23]); + + //SP/UNDEF ex2_b_frac_zero <= ex2_b_frac_zero_sp and ( ex2_b_sp or ex2_b_frac_zero_dp ); + assign ex2_b_frac_zero = ex2_b_frac_zero_sp & ex2_b_frac_zero_dp; + + assign ex2_b_frac_z32 = (~ex2_b_frac[24]) & (~ex2_b_frac[25]) & (~ex2_b_frac[26]) & (~ex2_b_frac[27]) & (~ex2_b_frac[28]) & (~ex2_b_frac[29]) & (~ex2_b_frac[30]) & (~ex2_b_frac[31]); // ex2_b_frac( 0) and + assign f_fmt_ex2_b_frac_z32 = ex2_b_frac_zero_sp & ex2_b_frac_z32; //output (for to_int_word special cases) + assign ex2_b_frac_zero_dp = ex2_b_frac_z32 & (~ex2_b_frac[32]) & (~ex2_b_frac[33]) & (~ex2_b_frac[34]) & (~ex2_b_frac[35]) & (~ex2_b_frac[36]) & (~ex2_b_frac[37]) & (~ex2_b_frac[38]) & (~ex2_b_frac[39]) & (~ex2_b_frac[40]) & (~ex2_b_frac[41]) & (~ex2_b_frac[42]) & (~ex2_b_frac[43]) & (~ex2_b_frac[44]) & (~ex2_b_frac[45]) & (~ex2_b_frac[46]) & (~ex2_b_frac[47]) & (~ex2_b_frac[48]) & (~ex2_b_frac[49]) & (~ex2_b_frac[50]) & (~ex2_b_frac[51]) & (~ex2_b_frac[52]); + + assign f_fmt_ex2_b_frac[1:19] = ex2_b_frac[1:19]; //output-- to tables + + assign f_fmt_ex2_a_sign_div = ex2_a_sign; + assign f_fmt_ex2_a_expo_div_b = (~ex2_a_expo[1:13]); + assign f_fmt_ex2_a_frac_div = ex2_a_frac[1:52]; + + assign f_fmt_ex2_b_sign_div = ex2_b_sign; + assign f_fmt_ex2_b_expo_div_b = (~ex2_b_expo[1:13]); + assign f_fmt_ex2_b_frac_div = ex2_b_frac[1:52]; + + assign ex2_a_denz = ((~ex2_a_frac[0]) | ex2_a_expo_ltx381_sp) & f_pic_ex2_nj_deni; // also true after prenorm + assign ex2_c_denz = ((~ex2_c_frac[0]) | ex2_c_expo_ltx381_sp) & f_pic_ex2_nj_deni; // also true after prenorm + assign ex2_b_denz = ((~ex2_b_frac[0]) | ex2_b_expo_ltx381_sp) & f_pic_ex2_nj_deni & (~ex2_from_integer); // also true after prenorm + + assign ex2_a_zero_x = (ex2_a_denz | (ex2_a_expo_min & ex2_a_frac_zero)); + assign ex2_c_zero_x = (ex2_c_denz | (ex2_c_expo_min & ex2_c_frac_zero)); + assign ex2_b_zero_x = (ex2_b_denz | (ex2_b_expo_min & ex2_b_frac_zero)) & ((~ex2_from_integer) | (~ex2_b_sign)); + + // from integer only does prenorm on SP denorm (exponent=x381) + assign ex2_divsqrt = f_dcd_ex2_divsqrt_v; + + assign ex2_b_den_flush = ex2_b_den_sp | ex2_b_den_dp | ex2_a_den_sp_ftdiv | (ex2_divsqrt & (ex2_a_den_dp | ex2_a_den_sp)); + + assign ex2_a_den_sp_ftdiv = f_pic_ex2_ftdiv & + ex2_aop_valid & + ex2_a_expo_min & //-- really just the implicit bit + (~ex2_a_frac_zero) & + (~f_pic_ex2_nj_deni) & //-- don't flush if converting inputs to zero + ex2_a_expo[5] ; //-- <== sp denorm !! + + // really just the implicit bit + assign ex2_b_den_dp = f_pic_ex2_flush_en_dp & ex2_bop_valid & ex2_b_expo_min & (~ex2_b_frac_zero) & (~f_pic_ex2_nj_deni) & (~ex2_b_expo[5]); // don't flush if converting inputs to zero + // <== dp denorm !! + + // from integer still needs to fix SP denorms + // really just the implicit bit + assign ex2_b_den_sp = f_pic_ex2_flush_en_sp & ex2_bop_valid & ex2_b_expo_min & (~ex2_b_frac_zero) & (~(f_pic_ex2_nj_deni & (~ex2_from_integer))) & ex2_b_expo[5]; // don't flush if converting inputs to zero + // <== sp denorm !! + + assign ex2_a_den_flush = ex2_a_den_sp | ex2_a_den_dp; + + // really just the implicit bit + assign ex2_a_den_dp = f_pic_ex2_flush_en_dp & ex2_aop_valid & ex2_a_expo_min & (~ex2_a_frac_zero) & (~f_pic_ex2_nj_deni) & (~ex2_a_expo[5]); // don't flush if converting inputs to zero + // <== dp denorm !! + + // from integer still needs to fix SP denorms + // really just the implicit bit + assign ex2_a_den_sp = f_pic_ex2_flush_en_sp & ex2_aop_valid & ex2_a_expo_min & (~ex2_a_frac_zero) & (~(f_pic_ex2_nj_deni & (~ex2_from_integer))) & ex2_a_expo[5]; // don't flush if converting inputs to zero + // <== sp denorm !! + + //lookup result will be denormal + assign ex2_lu_den_part = ex2_b_frac[1] & ex2_b_frac[2] & ex2_b_frac[3] & ex2_b_frac[4] & ex2_b_frac[5] & ex2_b_frac[6] & ex2_b_frac[7] & ex2_b_frac[8] & ex2_b_frac[9] & ex2_b_frac[10] & ex2_b_frac[11] & ex2_b_frac[12]; + + assign ex2_recip_lo = ex2_b_frac[14] | ex2_b_frac[15] | ex2_b_frac[16] | ex2_b_frac[17] | (ex2_b_frac[18] & ex2_b_frac[19]) | (ex2_b_frac[18] & ex2_b_frac[20]); + + // 0 1 2 + // 1234 56 78 9012 3456 7890 12 + // 1111 11 11 1111 1011 recip + // 1111 11 11 1111 1010 0001 01 recip + // + // 1111 11 11 1111 0001 rsqo + + // 366FFF0980000000 real boubdary for recip sqrt even + // FFF098 real boubdary for recip sqrt even + // + // 1111 1111 1111 0000 1001 1000 + // 1234 5678 9012 3456 7890 + // 0 1 2 + + // 3CFFFF8500000000 real boundary for reciprocal + // FFF85 + // 1111 1111 1111 1000 01010 + // 1234 5678 9012 3456 7890 + // 0 1 2 + + assign ex2_rsqrt_lo = ex2_b_frac[13] | ex2_b_frac[14] | ex2_b_frac[15] | ex2_b_frac[16] | (ex2_b_frac[17] & ex2_b_frac[18]) | (ex2_b_frac[17] & ex2_b_frac[19]) | (ex2_b_frac[17] & ex2_b_frac[20] & ex2_b_frac[21]); + + assign ex2_lu_den_recip = (ex2_lu_den_part & ex2_b_frac[13] & ex2_recip_lo); + + assign ex2_lu_den_rsqrto = (ex2_lu_den_part & ex2_rsqrt_lo); + + assign f_fmt_ex3_lu_den_recip = ex3_lu_den_recip; + assign f_fmt_ex3_lu_den_rsqrto = ex3_lu_den_rsqrto; // name is wrong (even biased, odd unbiased) + + // for from_integer if implicit bit is off result is "zero" plus rounding. + + assign ex2_a_zero = ex2_aop_valid & ex2_a_zero_x; + assign ex2_c_zero = ex2_cop_valid & ex2_c_zero_x; + assign ex2_b_zero = ex2_bop_valid & ex2_b_zero_x; + + assign ex2_a_expo_ltx36A_sp = (ex2_a_expo < 13'b0001101101010) ? 1'b1 : // exp < 0x36A 0d874 (-149 unbiased) + 1'b0; + assign ex2_b_expo_ltx36A_sp = (ex2_b_expo < 13'b0001101101010) ? 1'b1 : + 1'b0; + + assign ex2_a_expo_max_dsq = (ex2_a_expo > 13'b0010001111110) ? 1'b1 : + 1'b0; + assign ex2_b_expo_max_dsq = (ex2_b_expo > 13'b0010001111110) ? 1'b1 : + 1'b0; + + assign f_fmt_ex2_a_zero = ex2_a_zero; //output-- + assign f_fmt_ex2_a_zero_dsq = ((~ex2_a_frac[0]) | (ex2_a_expo_ltx36A_sp)) | (ex2_a_expo_min & ex2_a_frac_zero); + + assign f_fmt_ex2_a_expo_max = ex2_aop_valid & ex2_a_expo_max; //output-- + assign f_fmt_ex2_a_expo_max_dsq = ex2_a_expo_max_dsq; //output-- + + assign f_fmt_ex2_a_frac_zero = ex2_a_frac_zero; //output-- + assign f_fmt_ex2_a_frac_msb = ex2_a_frac_msb; //output-- + + assign f_fmt_ex2_c_zero = ex2_c_zero; //output-- + assign f_fmt_ex2_c_expo_max = ex2_cop_valid & ex2_c_expo_max; //output-- + assign f_fmt_ex2_c_frac_zero = ex2_c_frac_zero; //output-- + assign f_fmt_ex2_c_frac_msb = ex2_c_frac_msb; //output-- + + assign f_fmt_ex2_b_zero = ex2_b_zero; //output-- + assign f_fmt_ex2_b_zero_dsq = ((~ex2_b_frac[0]) | (ex2_b_expo_ltx36A_sp)) | (ex2_b_expo_min & ex2_b_frac_zero); + + assign f_fmt_ex2_b_expo_max = ex2_bop_valid & ex2_b_expo_max; //output-- + assign f_fmt_ex2_b_expo_max_dsq = ex2_b_expo_max_dsq; //output-- + + assign f_fmt_ex2_b_frac_zero = ex2_b_frac_zero; //output-- + assign f_fmt_ex2_b_frac_msb = ex2_b_frac_msb; //output-- + assign f_fmt_ex2_b_imp = ex2_b_frac[0]; //output-- + + assign f_fmt_ex2_prod_zero = ex2_a_zero | ex2_c_zero; //output--ex2_bop_valid and + + //#=-------------------------------------------------- + //#= NAN mux + //#=-------------------------------------------------- + // need to zero out sp bits that were left on so we could do a parity check. + + assign ex2_a_nan = ex2_a_expo_max & (~ex2_a_frac_zero) & (~ex2_from_integer) & (~ex2_sgncpy) & (~ex2_uc_end_nspec) & (~ex2_uc_mid) & (~f_dcd_ex2_perr_fsel_ovrd); + assign ex2_c_nan = ex2_c_expo_max & (~ex2_c_frac_zero) & (~ex2_from_integer) & (~ex2_fsel) & (~ex2_uc_end_nspec) & (~ex2_uc_mid); + assign ex2_b_nan = ex2_b_expo_max & (~ex2_b_frac_zero) & (~ex2_from_integer) & (~ex2_fsel) & (~ex2_uc_end_nspec) & (~ex2_uc_mid); + + assign ex2_nan_pass = ex2_a_nan | ex2_c_nan | ex2_b_nan; + assign ex2_pass_sel = ex2_nan_pass | ex2_fsel | ex2_force_pass; + + assign f_fmt_ex2_pass_sel = ex2_pass_sel; //output-- + + // a positive + assign ex2_fsel_cif = (ex2_fsel & (~ex2_a_sign) & (~f_dcd_ex2_perr_fsel_ovrd)) | + (ex2_fsel & ex2_a_zero & (~f_dcd_ex2_perr_fsel_ovrd)) | + ( f_dcd_ex2_perr_force_c & ( f_dcd_ex2_perr_fsel_ovrd)); + + assign ex2_be_den = + ( ex2_b_expo[1] ) | // it is negative + ( (~ex2_b_expo[2]) & // it is x000 ... as opposed to x001 + (~ex2_b_expo[3]) & // it is x000 ... as opposed to x001 + (~ex2_b_expo[4]) & // it is x000 ... as opposed to x001 + (~ex2_b_expo[5]) & // it is x000 ... as opposed to x001 + (~ex2_b_expo[6]) & // it is x000 ... as opposed to x001 + (~ex2_b_expo[7]) & // it is x000 ... as opposed to x001 + (~ex2_b_expo[8]) & // it is x000 ... as opposed to x001 + (~ex2_b_expo[9]) & // it is x000 ... as opposed to x001 + (~ex2_b_expo[10]) & // it is x000 ... as opposed to x001 + (~ex2_b_expo[11]) & // it is x000 ... as opposed to x001 + (~ex2_b_expo[12]) & // it is x000 ... as opposed to x001 + (~ex2_b_expo[13]) ); // it is x000 ... as opposed to x001 + + assign ex2_fsel_bsel = ex2_fsel & (ex2_a_nan | (~ex2_fsel_cif)); + + assign ex2_mux_a_sel = ex2_a_nan & (~ex2_fsel); + + assign ex2_mux_c_sel = ((~ex2_a_nan) & (~ex2_b_nan) & ex2_c_nan) | (ex2_a_nan & (~ex2_fsel)) | ((~ex2_a_nan) & ex2_fsel & ex2_fsel_cif); + + assign ex2_pass_sign_ac = (ex2_mux_a_sel & ex2_a_sign) | ((~ex2_mux_a_sel) & ex2_c_sign); + assign ex2_pass_sign = (ex2_mux_c_sel & ex2_pass_sign_ac) | ((~ex2_mux_c_sel) & ex2_b_sign); + + assign ex2_a_frac_chop[0:23] = ex2_a_frac[0:23]; + assign ex2_c_frac_chop[0:23] = ex2_c_frac[0:23]; + assign ex2_b_frac_chop[0:23] = ex2_b_frac[0:23]; + + assign ex2_a_frac_chop[24:52] = ex2_a_frac[24:52]; + assign ex2_c_frac_chop[24:52] = ex2_c_frac[24:52]; + assign ex2_b_frac_chop[24:52] = ex2_b_frac[24:52]; + assign ex2_a_expo_ltx381_sp = ex2_a_expo_ltx381 & ex2_a_sp; + assign ex2_c_expo_ltx381_sp = ex2_c_expo_ltx381 & ex2_c_sp; + assign ex2_b_expo_ltx381_sp = ex2_b_expo_ltx381 & ex2_b_sp; + + // negative + assign ex2_a_expo_ltx381 = ((~ex2_a_expo_b[1])) | (ex2_a_expo_00xx_xxxx_xxxx & (~ex2_a_expo_xx11_1xxx_xxxx)) | (ex2_a_expo_00xx_xxxx_xxxx & ex2_a_expo_xx11_1xxx_xxxx & ex2_a_expo_xxxx_x000_0000); // lt x380 + // eq x380 + + assign ex2_a_expo_00xx_xxxx_xxxx = ex2_a_expo_b[2] & ex2_a_expo_b[3]; + assign ex2_a_expo_xx11_1xxx_xxxx = (~ex2_a_expo_b[4]) & (~ex2_a_expo_b[5]) & (~ex2_a_expo_b[6]); + assign ex2_a_expo_xxxx_x000_0000 = ex2_a_expo_b[7] & ex2_a_expo_b[8] & ex2_a_expo_b[9] & ex2_a_expo_b[10] & ex2_a_expo_b[11] & ex2_a_expo_b[12] & ex2_a_expo_b[13]; + + // negative + assign ex2_c_expo_ltx381 = ((~ex2_c_expo_b[1])) | (ex2_c_expo_00xx_xxxx_xxxx & (~ex2_c_expo_xx11_1xxx_xxxx)) | (ex2_c_expo_00xx_xxxx_xxxx & ex2_c_expo_xx11_1xxx_xxxx & ex2_c_expo_xxxx_x000_0000); // lt x380 + // eq x380 + + assign ex2_c_expo_00xx_xxxx_xxxx = ex2_c_expo_b[2] & ex2_c_expo_b[3]; + assign ex2_c_expo_xx11_1xxx_xxxx = (~ex2_c_expo_b[4]) & (~ex2_c_expo_b[5]) & (~ex2_c_expo_b[6]); + assign ex2_c_expo_xxxx_x000_0000 = ex2_c_expo_b[7] & ex2_c_expo_b[8] & ex2_c_expo_b[9] & ex2_c_expo_b[10] & ex2_c_expo_b[11] & ex2_c_expo_b[12] & ex2_c_expo_b[13]; + + // negative + assign ex2_b_expo_ltx381 = ((~ex2_b_expo_b[1])) | (ex2_b_expo_00xx_xxxx_xxxx & (~ex2_b_expo_xx11_1xxx_xxxx)) | (ex2_b_expo_00xx_xxxx_xxxx & ex2_b_expo_xx11_1xxx_xxxx & ex2_b_expo_xxxx_x000_0000); // lt x380 + // eq x380 + + assign ex2_b_expo_00xx_xxxx_xxxx = ex2_b_expo_b[2] & ex2_b_expo_b[3]; + assign ex2_b_expo_xx11_1xxx_xxxx = (~ex2_b_expo_b[4]) & (~ex2_b_expo_b[5]) & (~ex2_b_expo_b[6]); + assign ex2_b_expo_xxxx_x000_0000 = ex2_b_expo_b[7] & ex2_b_expo_b[8] & ex2_b_expo_b[9] & ex2_b_expo_b[10] & ex2_b_expo_b[11] & ex2_b_expo_b[12] & ex2_b_expo_b[13]; + + assign ex2_pass_frac_ac[0:52] = ({53{ex2_mux_a_sel}} & ex2_a_frac_chop[0:52]) | + ({53{(~ex2_mux_a_sel)}} & ex2_c_frac_chop[0:52]); + + assign ex2_pass_frac[0:52] = ({53{ex2_mux_c_sel}} & ex2_pass_frac_ac[0:52]) | + ({53{(~ex2_mux_c_sel)}} & ex2_b_frac_chop[0:52]); + + // last iteration of divide = X * 1, check if x is a denorm + // expo is neg + assign ex2_uc_a_expo_den = ((~ex2_a_expo_b[1])) | (ex2_a_expo_b[2] & ex2_a_expo_b[3] & ex2_a_expo_b[4] & ex2_a_expo_b[5] & ex2_a_expo_b[6] & ex2_a_expo_b[7] & ex2_a_expo_b[8] & ex2_a_expo_b[9] & ex2_a_expo_b[10] & ex2_a_expo_b[11] & ex2_a_expo_b[12] & ex2_a_expo_b[13]); // expo is all zeroes + + // for SP we also need to add denorms <= x381 + assign ex2_uc_a_expo_den_sp = ex2_a_expo_ltx381; + + assign ex2_a_sp_inf_alias_tail = (~ex2_a_expo_b[7]) & (~ex2_a_expo_b[8]) & (~ex2_a_expo_b[9]) & (~ex2_a_expo_b[10]) & (~ex2_a_expo_b[11]) & (~ex2_a_expo_b[12]) & (~ex2_a_expo_b[13]); + assign ex2_c_sp_inf_alias_tail = (~ex2_c_expo_b[7]) & (~ex2_c_expo_b[8]) & (~ex2_c_expo_b[9]) & (~ex2_c_expo_b[10]) & (~ex2_c_expo_b[11]) & (~ex2_c_expo_b[12]) & (~ex2_c_expo_b[13]); + assign ex2_b_sp_inf_alias_tail = (~ex2_b_expo_b[7]) & (~ex2_b_expo_b[8]) & (~ex2_b_expo_b[9]) & (~ex2_b_expo_b[10]) & (~ex2_b_expo_b[11]) & (~ex2_b_expo_b[12]) & (~ex2_b_expo_b[13]); + + // 1024:1151 1151=1024+127 (exclude 1151) + // sign + // 2048 + // 1024 + // 512 + // 256 + assign ex2_a_sp_expo_ok_1 = ex2_a_expo_b[1] & ex2_a_expo_b[2] & (~ex2_a_expo_b[3]) & ex2_a_expo_b[4] & ex2_a_expo_b[5] & ex2_a_expo_b[6] & (~ex2_a_sp_inf_alias_tail); // 128; + + // 1024:1151 1151=1024+127 (exclude 1151) + // sign + // 2048 + // 1024 + // 512 + // 256 + assign ex2_c_sp_expo_ok_1 = ex2_c_expo_b[1] & ex2_c_expo_b[2] & (~ex2_c_expo_b[3]) & ex2_c_expo_b[4] & ex2_c_expo_b[5] & ex2_c_expo_b[6] & (~ex2_c_sp_inf_alias_tail); // 128; + + // 1024:1151 1151=1024+127 (exclude 1151) + // sign + // 2048 + // 1024 + // 512 + // 256 + assign ex2_b_sp_expo_ok_1 = ex2_b_expo_b[1] & ex2_b_expo_b[2] & (~ex2_b_expo_b[3]) & ex2_b_expo_b[4] & ex2_b_expo_b[5] & ex2_b_expo_b[6] & (~ex2_b_sp_inf_alias_tail); // 128; + + // 897:1023 + // 895 0_0011_0111_1111 00x00000_00000000_00000000 <2> + // 894 0_0011_0111_1110 000x0000_00000000_00000000 <3> + // 893 0_0011_0111_1101 0000x000_00000000_00000000 <4> + // 892 0_0011_0111_1100 00000x00_00000000_00000000 <5> + // 891 0_0011_0111_1011 000000x0_00000000_00000000 <6> + // 890 0_0011_0111_1010 0000000x_00000000_00000000 <7> + // 889 0_0011_0111_1001 00000000_x0000000_00000000 <8> + // 888 0_0011_0111_1000 00000000_0x000000_00000000 <9> + // 887 0_0011_0111_0111 00000000_00x00000_00000000 <10> + // 886 0_0011_0111_0110 00000000_000x0000_00000000 <11> + // 885 0_0011_0111_0101 00000000_0000x000_00000000 <12> + // 884 0_0011_0111_0100 00000000_00000x00_00000000 <13> + // 883 0_0011_0111_0011 00000000_000000x0_00000000 <14> + // 882 0_0011_0111_0010 00000000_0000000x_00000000 <15> + // 881 0_0011_0111_0001 00000000_00000000_x0000000 <16> + // 880 0_0011_0111_0000 00000000_00000000_0x000000 <17> + // 879 0_0011_0110_1111 00000000_00000000_00x00000 <18> + // 878 0_0011_0110_1110 00000000_00000000_000x0000 <19> + // 877 0_0011_0110_1101 00000000_00000000_0000x000 <20> + // 876 0_0011_0110_1100 00000000_00000000_00000x00 <21> + // 875 0_0011_0110_1011 00000000_00000000_000000x0 <22> + // x37A 874 0_0011_0110_1010 00000000_00000000_0000000x <23> + + assign f_fmt_ex2_sp_invalid = ((~ex2_a_sp_expo_ok_1) & (~ex2_a_sp_expo_ok_2) & (~ex2_a_sp_expo_ok_3) & (~ex2_a_sp_expo_ok_4) & (~ex2_a_expo_max) & (~ex2_a_zero_x)) | ((~ex2_c_sp_expo_ok_1) & (~ex2_c_sp_expo_ok_2) & (~ex2_c_sp_expo_ok_3) & (~ex2_c_sp_expo_ok_4) & (~ex2_c_expo_max) & (~ex2_c_zero_x)) | ((~ex2_b_sp_expo_ok_1) & (~ex2_b_sp_expo_ok_2) & (~ex2_b_sp_expo_ok_3) & (~ex2_b_sp_expo_ok_4) & (~ex2_b_expo_max) & (~ex2_b_zero_x)); + + //#=############################################################## + //# ex3 latches (from ex2 logic) + //#=############################################################## + + assign ex2_a_party[0] = ex2_a_sign ^ ex2_a_expo[1] ^ ex2_a_expo[2] ^ ex2_a_expo[3] ^ ex2_a_expo[4] ^ ex2_a_expo[5] ^ ex2_a_expo[6] ^ ex2_a_expo[7] ^ ex2_a_expo[8] ^ ex2_a_expo[9]; + assign ex2_a_party[1] = ex2_a_expo[10] ^ ex2_a_expo[11] ^ ex2_a_expo[12] ^ ex2_a_expo[13] ^ ex2_a_frac[0] ^ ex2_a_frac[1] ^ ex2_a_frac[2] ^ ex2_a_frac[3] ^ ex2_a_frac[4]; + assign ex2_a_party[2] = ex2_a_frac[5] ^ ex2_a_frac[6] ^ ex2_a_frac[7] ^ ex2_a_frac[8] ^ ex2_a_frac[9] ^ ex2_a_frac[10] ^ ex2_a_frac[11] ^ ex2_a_frac[12]; + assign ex2_a_party[3] = ex2_a_frac[13] ^ ex2_a_frac[14] ^ ex2_a_frac[15] ^ ex2_a_frac[16] ^ ex2_a_frac[17] ^ ex2_a_frac[18] ^ ex2_a_frac[19] ^ ex2_a_frac[20]; + assign ex2_a_party[4] = ex2_a_frac[21] ^ ex2_a_frac[22] ^ ex2_a_frac[23] ^ ex2_a_frac[24] ^ ex2_a_frac[25] ^ ex2_a_frac[26] ^ ex2_a_frac[27] ^ ex2_a_frac[28]; + assign ex2_a_party[5] = ex2_a_frac[29] ^ ex2_a_frac[30] ^ ex2_a_frac[31] ^ ex2_a_frac[32] ^ ex2_a_frac[33] ^ ex2_a_frac[34] ^ ex2_a_frac[35] ^ ex2_a_frac[36]; + assign ex2_a_party[6] = ex2_a_frac[37] ^ ex2_a_frac[38] ^ ex2_a_frac[39] ^ ex2_a_frac[40] ^ ex2_a_frac[41] ^ ex2_a_frac[42] ^ ex2_a_frac[43] ^ ex2_a_frac[44]; + assign ex2_a_party[7] = ex2_a_frac[45] ^ ex2_a_frac[46] ^ ex2_a_frac[47] ^ ex2_a_frac[48] ^ ex2_a_frac[49] ^ ex2_a_frac[50] ^ ex2_a_frac[51] ^ ex2_a_frac[52]; + + assign ex2_c_party[0] = ex2_c_sign ^ ex2_c_expo[1] ^ ex2_c_expo[2] ^ ex2_c_expo[3] ^ ex2_c_expo[4] ^ ex2_c_expo[5] ^ ex2_c_expo[6] ^ ex2_c_expo[7] ^ ex2_c_expo[8] ^ ex2_c_expo[9]; + assign ex2_c_party[1] = ex2_c_expo[10] ^ ex2_c_expo[11] ^ ex2_c_expo[12] ^ ex2_c_expo[13] ^ ex2_c_frac[0] ^ ex2_c_frac[1] ^ ex2_c_frac[2] ^ ex2_c_frac[3] ^ ex2_c_frac[4]; + assign ex2_c_party[2] = ex2_c_frac[5] ^ ex2_c_frac[6] ^ ex2_c_frac[7] ^ ex2_c_frac[8] ^ ex2_c_frac[9] ^ ex2_c_frac[10] ^ ex2_c_frac[11] ^ ex2_c_frac[12]; + assign ex2_c_party[3] = ex2_c_frac[13] ^ ex2_c_frac[14] ^ ex2_c_frac[15] ^ ex2_c_frac[16] ^ ex2_c_frac[17] ^ ex2_c_frac[18] ^ ex2_c_frac[19] ^ ex2_c_frac[20]; + assign ex2_c_party[4] = ex2_c_frac[21] ^ ex2_c_frac[22] ^ ex2_c_frac[23] ^ ex2_c_frac[24] ^ ex2_c_frac[25] ^ ex2_c_frac[26] ^ ex2_c_frac[27] ^ ex2_c_frac[28]; + assign ex2_c_party[5] = ex2_c_frac[29] ^ ex2_c_frac[30] ^ ex2_c_frac[31] ^ ex2_c_frac[32] ^ ex2_c_frac[33] ^ ex2_c_frac[34] ^ ex2_c_frac[35] ^ ex2_c_frac[36]; + assign ex2_c_party[6] = ex2_c_frac[37] ^ ex2_c_frac[38] ^ ex2_c_frac[39] ^ ex2_c_frac[40] ^ ex2_c_frac[41] ^ ex2_c_frac[42] ^ ex2_c_frac[43] ^ ex2_c_frac[44]; + assign ex2_c_party[7] = ex2_c_frac[45] ^ ex2_c_frac[46] ^ ex2_c_frac[47] ^ ex2_c_frac[48] ^ ex2_c_frac[49] ^ ex2_c_frac[50] ^ ex2_c_frac[51] ^ ex2_c_frac[52]; + + assign ex2_b_party[0] = ex2_b_sign ^ ex2_b_expo[1] ^ ex2_b_expo[2] ^ ex2_b_expo[3] ^ ex2_b_expo[4] ^ ex2_b_expo[5] ^ ex2_b_expo[6] ^ ex2_b_expo[7] ^ ex2_b_expo[8] ^ ex2_b_expo[9]; + assign ex2_b_party[1] = ex2_b_expo[10] ^ ex2_b_expo[11] ^ ex2_b_expo[12] ^ ex2_b_expo[13] ^ ex2_b_frac[0] ^ ex2_b_frac[1] ^ ex2_b_frac[2] ^ ex2_b_frac[3] ^ ex2_b_frac[4]; + assign ex2_b_party[2] = ex2_b_frac[5] ^ ex2_b_frac[6] ^ ex2_b_frac[7] ^ ex2_b_frac[8] ^ ex2_b_frac[9] ^ ex2_b_frac[10] ^ ex2_b_frac[11] ^ ex2_b_frac[12]; + assign ex2_b_party[3] = ex2_b_frac[13] ^ ex2_b_frac[14] ^ ex2_b_frac[15] ^ ex2_b_frac[16] ^ ex2_b_frac[17] ^ ex2_b_frac[18] ^ ex2_b_frac[19] ^ ex2_b_frac[20]; + assign ex2_b_party[4] = ex2_b_frac[21] ^ ex2_b_frac[22] ^ ex2_b_frac[23] ^ ex2_b_frac[24] ^ ex2_b_frac[25] ^ ex2_b_frac[26] ^ ex2_b_frac[27] ^ ex2_b_frac[28]; + assign ex2_b_party[5] = ex2_b_frac[29] ^ ex2_b_frac[30] ^ ex2_b_frac[31] ^ ex2_b_frac[32] ^ ex2_b_frac[33] ^ ex2_b_frac[34] ^ ex2_b_frac[35] ^ ex2_b_frac[36]; + assign ex2_b_party[6] = ex2_b_frac[37] ^ ex2_b_frac[38] ^ ex2_b_frac[39] ^ ex2_b_frac[40] ^ ex2_b_frac[41] ^ ex2_b_frac[42] ^ ex2_b_frac[43] ^ ex2_b_frac[44]; + assign ex2_b_party[7] = ex2_b_frac[45] ^ ex2_b_frac[46] ^ ex2_b_frac[47] ^ ex2_b_frac[48] ^ ex2_b_frac[49] ^ ex2_b_frac[50] ^ ex2_b_frac[51] ^ ex2_b_frac[52]; + + assign ex2_a_party_chick = (ex2_a_party[0] ^ f_fpr_ex2_a_par[0]) | (ex2_a_party[1] ^ f_fpr_ex2_a_par[1]) | (ex2_a_party[2] ^ f_fpr_ex2_a_par[2]) | (ex2_a_party[3] ^ f_fpr_ex2_a_par[3]) | (ex2_a_party[4] ^ f_fpr_ex2_a_par[4]) | (ex2_a_party[5] ^ f_fpr_ex2_a_par[5]) | (ex2_a_party[6] ^ f_fpr_ex2_a_par[6]) | (ex2_a_party[7] ^ f_fpr_ex2_a_par[7]); + + assign ex2_c_party_chick = (ex2_c_party[0] ^ f_fpr_ex2_c_par[0]) | (ex2_c_party[1] ^ f_fpr_ex2_c_par[1]) | (ex2_c_party[2] ^ f_fpr_ex2_c_par[2]) | (ex2_c_party[3] ^ f_fpr_ex2_c_par[3]) | (ex2_c_party[4] ^ f_fpr_ex2_c_par[4]) | (ex2_c_party[5] ^ f_fpr_ex2_c_par[5]) | (ex2_c_party[6] ^ f_fpr_ex2_c_par[6]) | (ex2_c_party[7] ^ f_fpr_ex2_c_par[7]); + + assign ex2_b_party_chick = (ex2_b_party[0] ^ f_fpr_ex2_b_par[0]) | (ex2_b_party[1] ^ f_fpr_ex2_b_par[1]) | (ex2_b_party[2] ^ f_fpr_ex2_b_par[2]) | (ex2_b_party[3] ^ f_fpr_ex2_b_par[3]) | (ex2_b_party[4] ^ f_fpr_ex2_b_par[4]) | (ex2_b_party[5] ^ f_fpr_ex2_b_par[5]) | (ex2_b_party[6] ^ f_fpr_ex2_b_par[6]) | (ex2_b_party[7] ^ f_fpr_ex2_b_par[7]); + + // --------------------------------------------------------------------- + // more logic for ftdiv ftsqrt + // --------------------------------------------------------------------- + + //---------------------------------------------------- + // x LE 53 == !(x ge 54) + // 1 - 2345 - 6789 - ABCD + // 54 0 0000 0011 0110 + // x_le_53 <= not x_ge_54 ; + // x_ge_54 =( ![1] * [2+3+4+5+6+7] ) + + // ( ![1] * [8][9][A] ) + + // ( ![1] * [8][9][B][C] ); + //---------------------------------------------------- + + assign ex2_ae_234567 = ex2_a_expo[2] | ex2_a_expo[3] | ex2_a_expo[4] | ex2_a_expo[5] | ex2_a_expo[6] | ex2_a_expo[7]; + assign ex2_ae_89 = ex2_a_expo[8] & ex2_a_expo[9]; + assign ex2_ae_abc = ex2_a_expo[10] | (ex2_a_expo[11] & ex2_a_expo[12]); + + assign ex2_ae_ge_54 = ((~ex2_a_expo[1]) & ex2_ae_234567) | ((~ex2_a_expo[1]) & ex2_ae_89 & ex2_ae_abc); + + assign ex2_be_234567 = ex2_b_expo[2] | ex2_b_expo[3] | ex2_b_expo[4] | ex2_b_expo[5] | ex2_b_expo[6] | ex2_b_expo[7]; + assign ex2_be_89 = ex2_b_expo[8] & ex2_b_expo[9]; + assign ex2_be_abc = ex2_b_expo[10] | (ex2_b_expo[11] & ex2_b_expo[12]); + + assign ex2_be_ge_54 = ((~ex2_b_expo[1]) & ex2_be_234567) | ((~ex2_b_expo[1]) & ex2_be_89 & ex2_be_abc); + + //---------------------------------------------------- + // x le 1 == !(x ge 2) -1022+1023 = 1 + // x ge 2044 1021+1023 = 2044 + // + // + // 1 - 2345 - 6789 - ABCD + // 2 0 0000 0000 0010 + // 2044 0 1111 1111 1100 + //---------------------------------------------------- + + assign ex2_be_or_23456789abc = ex2_b_expo[2] | ex2_b_expo[3] | ex2_b_expo[4] | ex2_b_expo[5] | ex2_b_expo[6] | ex2_b_expo[7] | ex2_b_expo[8] | ex2_b_expo[9] | ex2_b_expo[10] | ex2_b_expo[11] | ex2_b_expo[12]; + + assign ex2_be_and_3456789ab = ex2_b_expo[3] & ex2_b_expo[4] & ex2_b_expo[5] & ex2_b_expo[6] & ex2_b_expo[7] & ex2_b_expo[8] & ex2_b_expo[9] & ex2_b_expo[10] & ex2_b_expo[11]; + + assign ex2_be_ge_2 = (~ex2_b_expo[1]) & ex2_be_or_23456789abc; + assign ex2_be_ge_2044 = ((~ex2_b_expo[1]) & ex2_be_and_3456789ab) | ((~ex2_b_expo[1]) & ex2_b_expo[2]); + + //---------------------------------------------------- + // ae - be >= 1023 (same for biased, unbiased) !! + // ae - be <= -1021 ..... !(ae - be >= -1020) + // + // 1 - 2345 - 6789 - ABCD + // 1023 0 0011 1111 1111 + // 1022 0 0011 1111 1110 + // -1022 1 1100 0000 0010 + // (note ... a,b will always both be positive ) ... 1,2 ==0 + // + // ae - be - 1023 >= 0 , ae + !be + 1 - 1023 , (ae + !be -1022 >= 0) ... co = 1 <= x + // !(ae - be +1022 >= 0) , !(ae + !be + 1 + 1020) , !(ae + !be +1021 >= 0) ... co = 0 <= y + + assign ex2_aembex_car_b[0] = (~(ex2_a_expo[1] | ex2_b_expo_b[1])); //1 + assign ex2_aembex_car_b[1] = (~(ex2_a_expo[2] | ex2_b_expo_b[2])); //1 + assign ex2_aembex_car_b[2] = (~(ex2_a_expo[3] | ex2_b_expo_b[3])); //1 + assign ex2_aembex_car_b[3] = (~(ex2_a_expo[4] & ex2_b_expo_b[4])); //0 + assign ex2_aembex_car_b[4] = (~(ex2_a_expo[5] & ex2_b_expo_b[5])); //0 + assign ex2_aembex_car_b[5] = (~(ex2_a_expo[6] & ex2_b_expo_b[6])); //0 + assign ex2_aembex_car_b[6] = (~(ex2_a_expo[7] & ex2_b_expo_b[7])); //0 + assign ex2_aembex_car_b[7] = (~(ex2_a_expo[8] & ex2_b_expo_b[8])); //0 + assign ex2_aembex_car_b[8] = (~(ex2_a_expo[9] & ex2_b_expo_b[9])); //0 + assign ex2_aembex_car_b[9] = (~(ex2_a_expo[10] & ex2_b_expo_b[10])); //0 + assign ex2_aembex_car_b[10] = (~(ex2_a_expo[11] & ex2_b_expo_b[11])); //0 + assign ex2_aembex_car_b[11] = (~(ex2_a_expo[12] | ex2_b_expo_b[12])); //1 + assign ex2_aembex_car_b[12] = (~(ex2_a_expo[13] & ex2_b_expo_b[13])); //0 + + assign ex2_aembex_sum_b[1] = (ex2_a_expo[1] ^ ex2_b_expo_b[1]); //1 + assign ex2_aembex_sum_b[2] = (ex2_a_expo[2] ^ ex2_b_expo_b[2]); //1 + assign ex2_aembex_sum_b[3] = (ex2_a_expo[3] ^ ex2_b_expo_b[3]); //1 + assign ex2_aembex_sum_b[4] = (~(ex2_a_expo[4] ^ ex2_b_expo_b[4])); //0 + assign ex2_aembex_sum_b[5] = (~(ex2_a_expo[5] ^ ex2_b_expo_b[5])); //0 + assign ex2_aembex_sum_b[6] = (~(ex2_a_expo[6] ^ ex2_b_expo_b[6])); //0 + assign ex2_aembex_sum_b[7] = (~(ex2_a_expo[7] ^ ex2_b_expo_b[7])); //0 + assign ex2_aembex_sum_b[8] = (~(ex2_a_expo[8] ^ ex2_b_expo_b[8])); //0 + assign ex2_aembex_sum_b[9] = (~(ex2_a_expo[9] ^ ex2_b_expo_b[9])); //0 + assign ex2_aembex_sum_b[10] = (~(ex2_a_expo[10] ^ ex2_b_expo_b[10])); //0 + assign ex2_aembex_sum_b[11] = (~(ex2_a_expo[11] ^ ex2_b_expo_b[11])); //0 + assign ex2_aembex_sum_b[12] = (ex2_a_expo[12] ^ ex2_b_expo_b[12]); //1 + assign ex2_aembex_sum_b[13] = (~(ex2_a_expo[13] ^ ex2_b_expo_b[13])); //0 + + // want to know if the final sign is negative or positive + + assign ex2_aembex_sgn = ex2_aembex_sum_b[1] ^ ex2_aembex_car_b[1]; + + assign ex2_aembex_g1[2:12] = (~(ex2_aembex_sum_b[2:12] | ex2_aembex_car_b[2:12])); + assign ex2_aembex_t1[2:12] = (~(ex2_aembex_sum_b[2:12] & ex2_aembex_car_b[2:12])); + + assign ex2_aembex_g2[0] = ex2_aembex_g1[2] | (ex2_aembex_t1[2] & ex2_aembex_g1[3]); + assign ex2_aembex_g2[1] = ex2_aembex_g1[4] | (ex2_aembex_t1[4] & ex2_aembex_g1[5]); + assign ex2_aembex_g2[2] = ex2_aembex_g1[6] | (ex2_aembex_t1[6] & ex2_aembex_g1[7]); + assign ex2_aembex_g2[3] = ex2_aembex_g1[8] | (ex2_aembex_t1[8] & ex2_aembex_g1[9]); + assign ex2_aembex_g2[4] = ex2_aembex_g1[10] | (ex2_aembex_t1[10] & ex2_aembex_g1[11]); + assign ex2_aembex_g2[5] = ex2_aembex_g1[12]; + + assign ex2_aembex_t2[0] = (ex2_aembex_t1[2] & ex2_aembex_t1[3]); + assign ex2_aembex_t2[1] = (ex2_aembex_t1[4] & ex2_aembex_t1[5]); + assign ex2_aembex_t2[2] = (ex2_aembex_t1[6] & ex2_aembex_t1[7]); + assign ex2_aembex_t2[3] = (ex2_aembex_t1[8] & ex2_aembex_t1[9]); + assign ex2_aembex_t2[4] = (ex2_aembex_t1[10] & ex2_aembex_t1[11]); + + assign ex2_aembex_g4[0] = ex2_aembex_g2[0] | (ex2_aembex_t2[0] & ex2_aembex_g2[1]); + assign ex2_aembex_g4[1] = ex2_aembex_g2[2] | (ex2_aembex_t2[2] & ex2_aembex_g2[3]); + assign ex2_aembex_g4[2] = ex2_aembex_g2[4] | (ex2_aembex_t2[4] & ex2_aembex_g2[5]); + + assign ex2_aembex_t4[0] = (ex2_aembex_t2[0] & ex2_aembex_t2[1]); + assign ex2_aembex_t4[1] = (ex2_aembex_t2[2] & ex2_aembex_t2[3]); + + //-------------------------------------------- + + assign ex2_aembey_car_b[0] = (~(ex2_a_expo[1] & ex2_b_expo_b[1])); //0 + assign ex2_aembey_car_b[1] = (~(ex2_a_expo[2] & ex2_b_expo_b[2])); //0 + assign ex2_aembey_car_b[2] = (~(ex2_a_expo[3] & ex2_b_expo_b[3])); //0 + assign ex2_aembey_car_b[3] = (~(ex2_a_expo[4] | ex2_b_expo_b[4])); //1 + assign ex2_aembey_car_b[4] = (~(ex2_a_expo[5] | ex2_b_expo_b[5])); //1 + assign ex2_aembey_car_b[5] = (~(ex2_a_expo[6] | ex2_b_expo_b[6])); //1 + assign ex2_aembey_car_b[6] = (~(ex2_a_expo[7] | ex2_b_expo_b[7])); //1 + assign ex2_aembey_car_b[7] = (~(ex2_a_expo[8] | ex2_b_expo_b[8])); //1 + assign ex2_aembey_car_b[8] = (~(ex2_a_expo[9] | ex2_b_expo_b[9])); //1 + assign ex2_aembey_car_b[9] = (~(ex2_a_expo[10] | ex2_b_expo_b[10])); //1 + assign ex2_aembey_car_b[10] = (~(ex2_a_expo[11] | ex2_b_expo_b[11])); //1 + assign ex2_aembey_car_b[11] = (~(ex2_a_expo[12] & ex2_b_expo_b[12])); //0 + assign ex2_aembey_car_b[12] = (~(ex2_a_expo[13] | ex2_b_expo_b[13])); //1 + + assign ex2_aembey_sum_b[1] = (~(ex2_a_expo[1] ^ ex2_b_expo_b[1])); //0 + assign ex2_aembey_sum_b[2] = (~(ex2_a_expo[2] ^ ex2_b_expo_b[2])); //0 + assign ex2_aembey_sum_b[3] = (~(ex2_a_expo[3] ^ ex2_b_expo_b[3])); //0 + assign ex2_aembey_sum_b[4] = (ex2_a_expo[4] ^ ex2_b_expo_b[4]); //1 + assign ex2_aembey_sum_b[5] = (ex2_a_expo[5] ^ ex2_b_expo_b[5]); //1 + assign ex2_aembey_sum_b[6] = (ex2_a_expo[6] ^ ex2_b_expo_b[6]); //1 + assign ex2_aembey_sum_b[7] = (ex2_a_expo[7] ^ ex2_b_expo_b[7]); //1 + assign ex2_aembey_sum_b[8] = (ex2_a_expo[8] ^ ex2_b_expo_b[8]); //1 + assign ex2_aembey_sum_b[9] = (ex2_a_expo[9] ^ ex2_b_expo_b[9]); //1 + assign ex2_aembey_sum_b[10] = (ex2_a_expo[10] ^ ex2_b_expo_b[10]); //1 + assign ex2_aembey_sum_b[11] = (ex2_a_expo[11] ^ ex2_b_expo_b[11]); //1 + assign ex2_aembey_sum_b[12] = (~(ex2_a_expo[12] ^ ex2_b_expo_b[12])); //0 + assign ex2_aembey_sum_b[13] = (ex2_a_expo[13] ^ ex2_b_expo_b[13]); //1 + + // want to know if the final sign is negative or positive + + assign ex2_aembey_sgn = ex2_aembey_sum_b[1] ^ ex2_aembey_car_b[1]; + + assign ex2_aembey_g1[2:12] = (~(ex2_aembey_sum_b[2:12] | ex2_aembey_car_b[2:12])); + assign ex2_aembey_t1[2:12] = (~(ex2_aembey_sum_b[2:12] & ex2_aembey_car_b[2:12])); + + assign ex2_aembey_g2[0] = ex2_aembey_g1[2] | (ex2_aembey_t1[2] & ex2_aembey_g1[3]); + assign ex2_aembey_g2[1] = ex2_aembey_g1[4] | (ex2_aembey_t1[4] & ex2_aembey_g1[5]); + assign ex2_aembey_g2[2] = ex2_aembey_g1[6] | (ex2_aembey_t1[6] & ex2_aembey_g1[7]); + assign ex2_aembey_g2[3] = ex2_aembey_g1[8] | (ex2_aembey_t1[8] & ex2_aembey_g1[9]); + assign ex2_aembey_g2[4] = ex2_aembey_g1[10] | (ex2_aembey_t1[10] & ex2_aembey_g1[11]); + assign ex2_aembey_g2[5] = ex2_aembey_g1[12]; + + assign ex2_aembey_t2[0] = (ex2_aembey_t1[2] & ex2_aembey_t1[3]); + assign ex2_aembey_t2[1] = (ex2_aembey_t1[4] & ex2_aembey_t1[5]); + assign ex2_aembey_t2[2] = (ex2_aembey_t1[6] & ex2_aembey_t1[7]); + assign ex2_aembey_t2[3] = (ex2_aembey_t1[8] & ex2_aembey_t1[9]); + assign ex2_aembey_t2[4] = (ex2_aembey_t1[10] & ex2_aembey_t1[11]); + + assign ex2_aembey_g4[0] = ex2_aembey_g2[0] | (ex2_aembey_t2[0] & ex2_aembey_g2[1]); + assign ex2_aembey_g4[1] = ex2_aembey_g2[2] | (ex2_aembey_t2[2] & ex2_aembey_g2[3]); + assign ex2_aembey_g4[2] = ex2_aembey_g2[4] | (ex2_aembey_t2[4] & ex2_aembey_g2[5]); + + assign ex2_aembey_t4[0] = (ex2_aembey_t2[0] & ex2_aembey_t2[1]); + assign ex2_aembey_t4[1] = (ex2_aembey_t2[2] & ex2_aembey_t2[3]); + + //---------------------------------------------------- + + tri_rlmreg_p #(.WIDTH(80), .IBUF(1'B1), .NEEDS_SRESET(0)) ex3_pass_lat( + .force_t(force_t), //i-- tidn, + .d_mode(tiup), + .delay_lclkr(delay_lclkr[2]), //i-- tidn, + .mpw1_b(mpw1_b[2]), //i-- tidn, + .mpw2_b(mpw2_b[0]), //i-- tidn, + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_act), + .thold_b(thold_0_b), + .sg(sg_0), + .scout(ex3_pass_so), + .scin(ex3_pass_si), + //----------------- + .din({ ex2_fsel_bsel, + ex2_pass_sign, + ex2_pass_frac[0:52], + ex2_b_den_flush, + ex2_lu_den_recip, + ex2_lu_den_rsqrto, + ex2_uc_a_expo_den, + ex2_uc_a_expo_den_sp, + ex2_a_party_chick, + ex2_c_party_chick, + ex2_b_party_chick, + ex2_ae_ge_54, + ex2_be_ge_54, + ex2_be_ge_2, + ex2_be_ge_2044, + ex2_aembex_g4[0], + ex2_aembex_t4[0], + ex2_aembex_g4[1], + ex2_aembex_t4[1], + ex2_aembex_g4[2], + ex2_aembey_g4[0], + ex2_aembey_t4[0], + ex2_aembey_g4[1], + ex2_aembey_t4[1], + ex2_aembey_g4[2], + ex2_aembex_sgn, + ex2_aembey_sgn, + ex2_be_den}), + //----------------- + .dout({ ex3_fsel_bsel, + ex3_pass_sign, + ex3_pass_frac[0:52], + ex3_b_den_flush, + ex3_lu_den_recip, + ex3_lu_den_rsqrto, + ex3_uc_a_expo_den, + ex3_uc_a_expo_den_sp, + ex3_a_party_chick, + ex3_c_party_chick, + ex3_b_party_chick, + ex3_ae_ge_54, + ex3_be_ge_54, + ex3_be_ge_2, + ex3_be_ge_2044, + ex3_aembex_g4[0], + ex3_aembex_t4[0], + ex3_aembex_g4[1], + ex3_aembex_t4[1], + ex3_aembex_g4[2], + ex3_aembey_g4[0], + ex3_aembey_t4[0], + ex3_aembey_g4[1], + ex3_aembey_t4[1], + ex3_aembey_g4[2], + ex3_aembex_sgn, + ex3_aembey_sgn, + ex3_be_den}) + ); + assign f_fmt_ex3_be_den = ex3_be_den ; + assign f_mad_ex3_a_parity_check = ex3_a_party_chick; //output-- + assign f_mad_ex3_c_parity_check = ex3_c_party_chick; //output-- + assign f_mad_ex3_b_parity_check = ex3_b_party_chick; //output-- + + assign f_mad_ex3_uc_a_expo_den = ex3_uc_a_expo_den; + assign f_mad_ex3_uc_a_expo_den_sp = ex3_uc_a_expo_den_sp; + assign f_ex3_b_den_flush = ex3_b_den_flush; + + assign f_fmt_ex3_fsel_bsel = ex3_fsel_bsel; //output-- + assign f_fmt_ex3_pass_sign = ex3_pass_sign; //output-- + assign f_fmt_ex3_pass_msb = ex3_pass_frac[1]; //output-- + + assign ex3_pass_dp[0:52] = ex3_pass_frac[0:52]; + assign f_fmt_ex3_pass_frac[0:52] = ex3_pass_dp[0:52]; //output-- + + // -- shift 26 positions for SP + // -- if expo is very small in dp format, + // -- the lzo will shift 0 + // -- this leaves room so [0:23]G,X are all zero. + // -- could use shift 24 , if invalid sp op forces a NAN. + // + + assign ex3_aembex_g8[0] = ex3_aembex_g4[0] | (ex3_aembex_t4[0] & ex3_aembex_g4[1]); + assign ex3_aembex_g8[1] = ex3_aembex_g4[2]; + assign ex3_aembex_t8[0] = (ex3_aembex_t4[0] & ex3_aembex_t4[1]); + assign ex3_aembex_c2 = ex3_aembex_g8[0] | (ex3_aembex_t8[0] & ex3_aembex_g8[1]); + + assign ex3_aembey_g8[0] = ex3_aembey_g4[0] | (ex3_aembey_t4[0] & ex3_aembey_g4[1]); + assign ex3_aembey_g8[1] = ex3_aembey_g4[2]; + assign ex3_aembey_t8[0] = (ex3_aembey_t4[0] & ex3_aembey_t4[1]); + assign ex3_aembey_c2 = ex3_aembey_g8[0] | (ex3_aembey_t8[0] & ex3_aembey_g8[1]); + + assign ex3_aembex_res_sgn = ex3_aembex_c2 ^ ex3_aembex_sgn; + assign ex3_aembey_res_sgn = ex3_aembey_c2 ^ ex3_aembey_sgn; + + //output-- -- were the results positive or negative + // ae - be -1023 >= 0, ae + !be + 1 - 1023 set if positive + assign f_fmt_ex3_tdiv_rng_chk = ((~ex3_aembex_res_sgn)) | (ex3_aembey_res_sgn); // !(ae - be +1022 >= 0) , !(ae + !be + 1 + 1020) set if negtive + + assign f_fmt_ex3_ae_ge_54 = ex3_ae_ge_54; //output-- + assign f_fmt_ex3_be_ge_54 = ex3_be_ge_54; //output-- + assign f_fmt_ex3_be_ge_2 = ex3_be_ge_2; //output-- + assign f_fmt_ex3_be_ge_2044 = ex3_be_ge_2044; //output-- + + //#=############################################################## + //# ex3 logic + //#=############################################################## + + //#=############################################################## + //# scan string + //#=############################################################## + + assign ex2_ctl_si[0:8] = {ex2_ctl_so[1:8], f_fmt_si}; + assign ex3_pass_si[0:79] = {ex3_pass_so[1:79], ex2_ctl_so[0]}; + assign act_si[0:6] = {act_so[1:6], ex3_pass_so[0]}; + assign f_fmt_so = act_so[0]; + +endmodule diff --git a/dev/verilog/work/fu_fpr.v b/dev/verilog/work/fu_fpr.v new file mode 100755 index 0000000..f25d0f3 --- /dev/null +++ b/dev/verilog/work/fu_fpr.v @@ -0,0 +1,1693 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//***************************************************************************** +//* +//* TITLE: F_DP_FPR +//* +//* NAME: fu_fpr.vhdl +//* +//* DESC: This is the Floating Point Register file +//* +//***************************************************************************** + + `include "tri_a2o.vh" + +module fu_fpr( + nclk, + clkoff_b, + act_dis, + flush, + delay_lclkra, + delay_lclkrb, + mpw1_ba, + mpw1_bb, + mpw2_b, + abst_sl_thold_1, + time_sl_thold_1, + ary_nsl_thold_1, + gptr_sl_thold_0, + fce_1, + thold_1, + sg_1, + scan_dis_dc_b, + scan_diag_dc, + lbist_en_dc, + f_fpr_si, + f_fpr_so, + f_fpr_ab_si, + f_fpr_ab_so, + time_scan_in, + time_scan_out, + gptr_scan_in, + gptr_scan_out, + vdd, +// vcs, + gnd, + pc_fu_abist_di_0, + pc_fu_abist_di_1, + pc_fu_abist_ena_dc, + pc_fu_abist_grf_renb_0, + pc_fu_abist_grf_renb_1, + pc_fu_abist_grf_wenb_0, + pc_fu_abist_grf_wenb_1, + pc_fu_abist_raddr_0, + pc_fu_abist_raddr_1, + pc_fu_abist_raw_dc_b, + pc_fu_abist_waddr_0, + pc_fu_abist_waddr_1, + pc_fu_abist_wl144_comp_ena, + pc_fu_inj_regfile_parity, + f_dcd_msr_fp_act, + iu_fu_rf0_fra_v, + iu_fu_rf0_frb_v, + iu_fu_rf0_frc_v, + iu_fu_rf0_str_v, + iu_fu_rf0_tid, + f_dcd_rf0_fra, + f_dcd_rf0_frb, + f_dcd_rf0_frc, + f_dcd_rf0_tid, + iu_fu_rf0_ldst_tag, + f_dcd_ex6_frt_tid, + f_dcd_ex7_frt_addr, + f_dcd_ex7_frt_tid, + f_dcd_ex7_frt_wen, + f_rnd_ex7_res_expo, + f_rnd_ex7_res_frac, + f_rnd_ex7_res_sign, + xu_fu_ex5_load_val, + xu_fu_ex5_load_tag, + xu_fu_ex5_load_data, + lq_gpr_rel_we, + lq_gpr_rel_le, + lq_gpr_rel_wa, + lq_gpr_rel_wd, + f_fpr_ex6_load_addr, + f_fpr_ex6_load_v, + f_fpr_ex6_reload_addr, + f_fpr_ex6_reload_v, + + f_fpr_ex1_s_sign, + f_fpr_ex1_s_expo, + f_fpr_ex1_s_frac, + f_fpr_ex1_a_sign, + f_fpr_ex1_a_expo, + f_fpr_ex1_a_frac, + f_fpr_ex1_c_sign, + f_fpr_ex1_c_expo, + f_fpr_ex1_c_frac, + f_fpr_ex1_b_sign, + f_fpr_ex1_b_expo, + f_fpr_ex1_b_frac, + f_fpr_ex8_frt_sign, + f_fpr_ex8_frt_expo, + f_fpr_ex8_frt_frac, + f_fpr_ex9_frt_sign, + f_fpr_ex9_frt_expo, + f_fpr_ex9_frt_frac, + + f_fpr_ex6_load_sign, + f_fpr_ex6_load_expo, + f_fpr_ex6_load_frac, + f_fpr_ex7_load_sign, + f_fpr_ex7_load_expo, + f_fpr_ex7_load_frac, + f_fpr_ex8_load_sign, + f_fpr_ex8_load_expo, + f_fpr_ex8_load_frac, + + f_fpr_ex6_reload_sign, + f_fpr_ex6_reload_expo, + f_fpr_ex6_reload_frac, + f_fpr_ex7_reload_sign, + f_fpr_ex7_reload_expo, + f_fpr_ex7_reload_frac, + f_fpr_ex8_reload_sign, + f_fpr_ex8_reload_expo, + f_fpr_ex8_reload_frac, + + f_fpr_ex2_s_expo_extra, + f_fpr_ex2_a_par, + f_fpr_ex2_b_par, + f_fpr_ex2_c_par, + f_fpr_ex2_s_par +); + parameter fpr_pool = 64; + parameter fpr_pool_enc = 7; + parameter threads = 2; + parameter axu_spare_enc = 3; + + input [0:`NCLK_WIDTH-1] nclk; + input clkoff_b; // tiup + input act_dis; // ??tidn?? + input flush; // ??tidn?? + input [0:1] delay_lclkra; // tidn, + input [6:7] delay_lclkrb; + input [0:1] mpw1_ba; // tidn, + input [6:7] mpw1_bb; + input [0:1] mpw2_b; // tidn, + + input abst_sl_thold_1; + input time_sl_thold_1; + input ary_nsl_thold_1; + input gptr_sl_thold_0; + input fce_1; + input thold_1; + input sg_1; + input scan_dis_dc_b; + input scan_diag_dc; + input lbist_en_dc; + + input f_fpr_si; + output f_fpr_so; + input f_fpr_ab_si; + output f_fpr_ab_so; + input time_scan_in; + output time_scan_out; + input gptr_scan_in; + output gptr_scan_out; + inout vdd; + //inout vcs; + inout gnd; + // ABIST + input [0:3] pc_fu_abist_di_0; + input [0:3] pc_fu_abist_di_1; + input pc_fu_abist_ena_dc; + input pc_fu_abist_grf_renb_0; + input pc_fu_abist_grf_renb_1; + input pc_fu_abist_grf_wenb_0; + input pc_fu_abist_grf_wenb_1; + input [0:9] pc_fu_abist_raddr_0; + input [0:9] pc_fu_abist_raddr_1; + input pc_fu_abist_raw_dc_b; + input [0:9] pc_fu_abist_waddr_0; + input [0:9] pc_fu_abist_waddr_1; + input pc_fu_abist_wl144_comp_ena; + input [0:`THREADS-1] pc_fu_inj_regfile_parity; + input f_dcd_msr_fp_act; + input iu_fu_rf0_fra_v; + input iu_fu_rf0_frb_v; + input iu_fu_rf0_frc_v; + input iu_fu_rf0_str_v; + + // Interface to IU + input [0:threads-1] iu_fu_rf0_tid; // one hot + input [0:5] f_dcd_rf0_fra; + input [0:5] f_dcd_rf0_frb; + input [0:5] f_dcd_rf0_frc; + input [0:1] f_dcd_rf0_tid; + input [0:9] iu_fu_rf0_ldst_tag; + //---------------------------------------------- + input [0:1] f_dcd_ex6_frt_tid; // one hot + input [0:5] f_dcd_ex7_frt_addr; + input [0:1] f_dcd_ex7_frt_tid; + input f_dcd_ex7_frt_wen; + input [1:13] f_rnd_ex7_res_expo; + input [0:52] f_rnd_ex7_res_frac; + input f_rnd_ex7_res_sign; + //---------------------------------------------- + input xu_fu_ex5_load_val; + input [0:7+threads] xu_fu_ex5_load_tag; + input [192:255] xu_fu_ex5_load_data; + + input lq_gpr_rel_we; + input lq_gpr_rel_le; + input [0:7+threads] lq_gpr_rel_wa; + input [64:127] lq_gpr_rel_wd; // :out std_ulogic_vector((128-STQ_DATA_SIZE) to 127); + //---------------------------------------------- + output [0:7] f_fpr_ex6_load_addr; + output f_fpr_ex6_load_v; + output [0:7] f_fpr_ex6_reload_addr; + output f_fpr_ex6_reload_v; + + output f_fpr_ex1_s_sign; + output [1:11] f_fpr_ex1_s_expo; + output [0:52] f_fpr_ex1_s_frac; + output f_fpr_ex1_a_sign; + output [1:13] f_fpr_ex1_a_expo; + output [0:52] f_fpr_ex1_a_frac; + output f_fpr_ex1_c_sign; + output [1:13] f_fpr_ex1_c_expo; + output [0:52] f_fpr_ex1_c_frac; + output f_fpr_ex1_b_sign; + output [1:13] f_fpr_ex1_b_expo; + output [0:52] f_fpr_ex1_b_frac; + output f_fpr_ex8_frt_sign; + output [1:13] f_fpr_ex8_frt_expo; + output [0:52] f_fpr_ex8_frt_frac; + output f_fpr_ex9_frt_sign; + output [1:13] f_fpr_ex9_frt_expo; + output [0:52] f_fpr_ex9_frt_frac; + + output f_fpr_ex6_load_sign; + output [3:13] f_fpr_ex6_load_expo; + output [0:52] f_fpr_ex6_load_frac; + output f_fpr_ex7_load_sign; + output [3:13] f_fpr_ex7_load_expo; + output [0:52] f_fpr_ex7_load_frac; + output f_fpr_ex8_load_sign; + output [3:13] f_fpr_ex8_load_expo; + output [0:52] f_fpr_ex8_load_frac; + + output f_fpr_ex6_reload_sign; + output [3:13] f_fpr_ex6_reload_expo; + output [0:52] f_fpr_ex6_reload_frac; + output f_fpr_ex7_reload_sign; + output [3:13] f_fpr_ex7_reload_expo; + output [0:52] f_fpr_ex7_reload_frac; + output f_fpr_ex8_reload_sign; + output [3:13] f_fpr_ex8_reload_expo; + output [0:52] f_fpr_ex8_reload_frac; + + output [0:1] f_fpr_ex2_s_expo_extra; + output [0:7] f_fpr_ex2_a_par; + output [0:7] f_fpr_ex2_b_par; + output [0:7] f_fpr_ex2_c_par; + output [0:7] f_fpr_ex2_s_par; + // This entity contains macros + + + // ####################### SIGNALS ####################### -- + wire tilo; + wire tihi; + wire tiup; + wire tidn; + + wire [0:3] pc_fu_inj_regfile_parity_int; + + + wire thold_0; + wire thold_0_b; + wire sg_0; + wire force_t; + wire ab_thold_0; + wire ab_thold_0_b; + wire ab_force; + wire time_sl_thold_0; + + wire [0:1] load_tid_enc; + wire [0:7] load_addr; + wire load_wen; + + wire [0:63] ex6_load_data_raw; + wire [0:31] ex6_load_sp_data_raw; + wire [0:65] ex6_load_data; + wire [0:65] ex6_load_data_byp; + wire [0:65] ex7_load_data_byp; + wire [0:65] ex8_load_data_byp; + wire [0:65] ex6_reload_data_byp; + wire [0:65] ex7_reload_data_byp; + wire [0:65] ex8_reload_data_byp; + wire ex5_load_val; + wire ex5_load_v; + wire [0:9] ex5_load_tag; + wire ex6_load_val; + wire [0:9] ex6_load_tag; + + wire [0:1] reload_tid_enc; + wire [0:7] reload_addr; + wire reload_wen; + + wire ex5_reload_val; + wire ex5_reload_v; + wire [0:9] ex5_reload_tag; + wire [0:63] ex6_reload_data_raw; + wire [0:31] ex6_reload_sp_data_raw; + wire [0:65] ex6_reload_data; + wire ex6_reload_val; + wire [0:9] ex6_reload_tag; + + wire [0:3] perr_inject; + wire ex6_ld_perr_inj; + wire ex7_ld_perr_inj; + wire ex6_rld_perr_inj; + wire ex7_rld_perr_inj; + wire ex6_targ_perr_inj; + wire ex7_targ_perr_inj; + + wire r0e_en_func; + wire r1e_en_func; + + wire [0:73] load_data_f0; + wire [0:73] load_data_f1; + wire [0:7] load_data_parity; + wire [0:7] load_data_parity_inj; + wire load_sp; + wire load_int; + wire load_sign_ext; + wire load_int_1up; + wire load_dp_exp_zero; + wire load_sp_exp_zero; + wire load_sp_exp_ones; + wire [0:65] load_sp_data; + wire [0:65] load_dp_data; + + wire [0:73] reload_data_f0; + wire [0:73] reload_data_f1; + wire [0:7] reload_data_parity; + wire [0:7] reload_data_parity_inj; + wire reload_sp; + wire reload_int; + wire reload_sign_ext; + wire reload_int_1up; + wire reload_dp_exp_zero; + wire reload_sp_exp_zero; + wire reload_sp_exp_ones; + wire [0:65] reload_sp_data; + wire [0:65] reload_dp_data; + + wire [0:7] rf0_fra_addr; + wire [0:7] rf0_frb_addr; + wire [0:7] rf0_frc_addr; + wire [0:7] rf0_frs_addr; + + wire [0:7] frt_addr; + wire frt_wen; + wire [0:63] frt_data; + wire [0:7] frt_data_parity; + + wire [0:66] ex7_frt_data; + wire [0:66] ex8_frt_data; + wire [0:66] ex9_frt_data; + wire [0:131] ldwt_lat_si; + wire [0:131] ldwt_lat_so; + wire [0:131] reldwt_lat_si; + wire [0:131] reldwt_lat_so; + wire [0:133] tgwt_lat_si; + wire [0:133] tgwt_lat_so; + + wire [0:77] rf1_fra; + wire [0:77] rf1_frb; + wire [0:77] rf1_frc; + wire [0:77] rf1_frs; + + wire [0:9] abist_raddr_0; + wire [0:9] abist_raddr_1; + wire [0:9] abist_waddr_0; + wire [0:9] abist_waddr_1; + wire [0:52] ab_reg_si; + wire [0:52] ab_reg_so; + + wire abist_comp_en; // when abist tested + wire r0e_abist_comp_en; // when abist tested + wire r1e_abist_comp_en; // when abist tested + + wire lcb_act_dis_dc; + wire [0:1] lcb_clkoff_dc_b; + wire lcb_d_mode_dc; + wire [0:4] lcb_delay_lclkr_dc; // + wire fce_0; + wire [0:6] lcb_mpw1_dc_b; // + wire lcb_mpw2_dc_b; + wire lcb_sg_0; + wire lcb_abst_sl_thold_0; + wire ary_nsl_thold_0; + wire clkoff_dc_b; + wire d_mode_dc; + + wire scan_in_0; + wire scan_out_0; + + wire scan_in_1; + wire scan_out_1; + + wire r0e_en_abist; + wire [0:7] r0e_addr_abist; + + wire r1e_en_abist; + wire [0:7] r1e_addr_abist; + wire w0e_act; + wire w0e_en_func; + wire w0e_en_abist; + wire [0:7] w0e_addr_func; + wire [0:7] w0e_addr_abist; + wire [0:77] w0e_data_func_f0; + wire [0:77] w0e_data_func_f1; + + wire [0:77] rel_data_func_f0; + wire [0:77] rel_data_func_f1; + + wire [0:3] w0e_data_abist; + wire w0l_act; + wire w0l_en_func; + wire w0l_en_abist; + wire [0:7] w0l_addr_func; + wire [0:7] w0l_addr_abist; + wire [0:77] w0l_data_func_f0; + wire [0:77] w0l_data_func_f1; + wire [0:3] w0l_data_abist; + + wire [0:77] fra_data_out; + wire [0:77] frb_data_out; + wire [0:77] frc_data_out; + wire [0:77] frs_data_out; + wire [0:7] ex1_fra_par; + wire [0:7] ex1_frb_par; + wire [0:7] ex1_frc_par; + wire [0:7] ex1_frs_par; + wire [0:1] ex1_s_expo_extra; + + wire [0:63] ex7_ldat_si; + wire [0:63] ex7_ldat_so; + wire [0:63] ex7_rldat_si; + wire [0:63] ex7_rldat_so; + + wire [0:11] ex7_lctl_si; + wire [0:11] ex7_lctl_so; + wire [0:9] ex7_rlctl_si; + wire [0:9] ex7_rlctl_so; + + wire [0:1] ex7_ldv_si; + wire [0:1] ex7_ldv_so; + wire [0:4] ex6_lctl_si; + wire [0:4] ex6_lctl_so; + wire [0:33] ex1_par_si; + wire [0:33] ex1_par_so; + wire ld_par3239; + wire ld_par3239_inj; + wire ld_par4047; + wire ld_par4855; + wire ld_par5663; + wire ld_par6163; + wire ld_par6163_inj; + wire ld_par0007; + wire ld_par0815; + wire ld_par1623; + wire ld_par2431; + wire ld_par32_3436; + wire ld_par3744; + wire ld_par4552; + wire ld_par5360; + wire load_dp_nint; + wire load_dp_int; + wire load_sp_all1; + wire load_sp_nall1; + + wire rld_par3239; + wire rld_par3239_inj; + wire rld_par4047; + wire rld_par4855; + wire rld_par5663; + wire rld_par6163; + wire rld_par6163_inj; + wire rld_par0007; + wire rld_par0815; + wire rld_par1623; + wire rld_par2431; + wire rld_par32_3436; + wire rld_par3744; + wire rld_par4552; + wire rld_par5360; + wire reload_dp_nint; + wire reload_dp_int; + wire reload_sp_all1; + wire reload_sp_nall1; + + wire [0:77] zeros; + wire [1:25] spare_unused; + + //---------------------------------------------------------------------- + // Pervasive + + + tri_plat thold_reg_0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(flush), + .din(thold_1), + .q(thold_0) + ); + + + tri_plat sg_reg_0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(flush), + .din(sg_1), + .q(sg_0) + ); + + + tri_lcbor lcbor_0( + .clkoff_b(clkoff_b), + .thold(thold_0), + .sg(sg_0), + .act_dis(act_dis), + .force_t(force_t), + .thold_b(thold_0_b) + ); + + + tri_plat #(.WIDTH(4)) ab_thold_reg_0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(flush), + .din({abst_sl_thold_1, + time_sl_thold_1, + ary_nsl_thold_1, + fce_1}), + .q({ ab_thold_0, + time_sl_thold_0, + ary_nsl_thold_0, + fce_0}) + ); + + + tri_lcbor ab_lcbor_0( + .clkoff_b(clkoff_b), + .thold(ab_thold_0), + .sg(sg_0), + .act_dis(act_dis), + .force_t(ab_force), + .thold_b(ab_thold_0_b) + ); + + //---------------------------------------------------------------------- + // Act Latches + + assign tilo = 1'b0; + assign tihi = 1'b1; + assign zeros = {78{tilo}}; + assign tiup = 1'b1; + assign tidn = 1'b1; + + //---------------------------------------------------------------------- + // Load Data + + generate + if (threads == 1) + begin : fpr_inj_perr_thr1_1 + assign pc_fu_inj_regfile_parity_int[0:3] = {pc_fu_inj_regfile_parity[0], tidn, tidn, tidn}; + end + endgenerate + + generate + if (threads == 2) + begin : fpr_inj_perr_thr2_2 + assign pc_fu_inj_regfile_parity_int[0:3] = {pc_fu_inj_regfile_parity[0], pc_fu_inj_regfile_parity[1], tidn, tidn}; + end + endgenerate + + tri_rlmreg_p #(.INIT(0), .WIDTH(5)) ex6_lctl( + .nclk(nclk), + .act(tihi), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkrb[6]), + .mpw1_b(mpw1_bb[6]), + .mpw2_b(mpw2_b[1]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(ex6_lctl_si[0:4]), + .scout(ex6_lctl_so[0:4]), + + .din({ pc_fu_inj_regfile_parity_int[0:3], + ex6_targ_perr_inj}), + + .dout({ perr_inject[0:3], + ex7_targ_perr_inj}) + ); + + assign ex5_load_val = xu_fu_ex5_load_val; + assign ex5_load_v = ex5_load_val; + + generate + if (threads == 1) + begin : dcd_loadtag_thr1_1 + assign ex5_load_tag[0:9] = {xu_fu_ex5_load_tag[0:2], 1'b0, xu_fu_ex5_load_tag[3:8]}; + end + endgenerate + + generate + if (threads == 2) + begin : dcd_loadtag_thr2_1 + assign ex5_load_tag[0:9] = xu_fu_ex5_load_tag[0:9]; + end + endgenerate + + assign ex5_reload_val = lq_gpr_rel_we; + assign ex5_reload_v = ex5_reload_val; + + generate + if (threads == 1) + begin : dcd_reloadtag_thr1_1 + assign ex5_reload_tag[0:9] = {lq_gpr_rel_wa[0:2], 1'b0, lq_gpr_rel_wa[3:8]}; + end + endgenerate + + generate + if (threads == 2) + begin : dcd_reloadtag_thr2_1 + assign ex5_reload_tag[0:9] = lq_gpr_rel_wa[0:9]; + end + endgenerate + + assign ex6_ld_perr_inj = ((ex6_load_val) & (~ex6_load_tag[3]) & perr_inject[0]) | + ((ex6_load_val) & ( ex6_load_tag[3]) & perr_inject[1]); + + assign ex6_rld_perr_inj = ((ex6_reload_val) & (~ex6_reload_tag[3]) & perr_inject[0]) | + ((ex6_reload_val) & ( ex6_reload_tag[3]) & perr_inject[1]); + + + assign ex6_targ_perr_inj = (f_dcd_ex6_frt_tid[0] & perr_inject[0]) | + (f_dcd_ex6_frt_tid[1] & perr_inject[1]); + + + + + tri_rlmreg_p #(.INIT(0), .WIDTH(2)) ex6_ldv( + .nclk(nclk), + .act(tihi), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkrb[6]), + .mpw1_b(mpw1_bb[6]), + .mpw2_b(mpw2_b[1]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(ex7_ldv_si[0:1]), + .scout(ex7_ldv_so[0:1]), + .din({ex5_load_val, + ex5_reload_val}), + .dout({ex6_load_val, + ex6_reload_val}) + ); + + + tri_rlmreg_p #(.INIT(0), .WIDTH(12)) ex7_lctl( + .nclk(nclk), + .act(tihi), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkrb[6]), //todo separate these out into ex6 and ex7? + .mpw1_b(mpw1_bb[6]), + .mpw2_b(mpw2_b[1]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(ex7_lctl_si[0:11]), + .scout(ex7_lctl_so[0:11]), + .din({ex5_load_tag[0:9], + ex6_ld_perr_inj, + ex6_rld_perr_inj}), + .dout({ex6_load_tag[0:9], + ex7_ld_perr_inj, + ex7_rld_perr_inj}) + ); + + tri_rlmreg_p #(.INIT(0), .WIDTH(10)) ex7_rlctl( + .nclk(nclk), + .act(ex5_reload_v), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkrb[6]), + .mpw1_b(mpw1_bb[6]), + .mpw2_b(mpw2_b[1]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(ex7_rlctl_si[0:9]), + .scout(ex7_rlctl_so[0:9]), + .din(ex5_reload_tag[0:9]), + .dout(ex6_reload_tag[0:9]) + ); + + + tri_rlmreg_p #(.INIT(0), .WIDTH(64), .NEEDS_SRESET(0)) ex7_ldat( + .nclk(nclk), + .act(ex5_load_v), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkrb[7]), + .mpw1_b(mpw1_bb[7]), + .mpw2_b(mpw2_b[1]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(ex7_ldat_si[0:63]), + .scout(ex7_ldat_so[0:63]), + .din(xu_fu_ex5_load_data[192:255]), + .dout(ex6_load_data_raw[0:63]) + ); + + + tri_rlmreg_p #(.INIT(0), .WIDTH(64), .NEEDS_SRESET(0)) ex7_rldat( + .nclk(nclk), + .act(ex5_reload_v), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkrb[7]), + .mpw1_b(mpw1_bb[7]), + .mpw2_b(mpw2_b[1]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(ex7_rldat_si[0:63]), + .scout(ex7_rldat_so[0:63]), + .din(lq_gpr_rel_wd[64:127]), + .dout(ex6_reload_data_raw[0:63]) + ); + + assign load_tid_enc[0] = tilo; + assign load_tid_enc[1] = tilo; + + assign load_addr[1:7] = ex6_load_tag[3:9]; + + assign load_sp = ex6_load_tag[0]; // bit 0 of the tag indicates that the instr was an lfs* + assign load_int = ex6_load_tag[1]; // bit 1 is lfi* + assign load_sign_ext = ex6_load_tag[2]; // bit 1 is lfiwax + + assign load_wen = ex6_load_val; + + assign reload_tid_enc[0] = tilo; + assign reload_tid_enc[1] = tilo; + + assign reload_addr[0:7] = {1'b0, ex6_reload_tag[3:9]}; + + assign reload_sp = ex6_reload_tag[0]; // bit 0 of the tag indicates that the instr was an lfs* + assign reload_int = ex6_reload_tag[1]; // bit 1 is lfi* + assign reload_sign_ext = ex6_reload_tag[2]; // bit 1 is lfiwax + + assign reload_wen = ex6_reload_val; + + // FPU LOADS + // + // Double precision (DP) loads are straight forward. + // To get rid of the mathematical discontinuity in the ieee number system, + // We add the implicit bit and change the zero exponent from x000 to x001. + // This needs to be undone when data is stored. + // + // the spec says that Single Precision loads (SP) should be fully normalized + // and converted to double format before storing. + // there is not time to do that, so we take a short cut and deal with the problems + // when the operand is used. + // The Double precision exponent bias is 1023. + // The Single precision exponent bias is 127. + // The difference x380 is added to convert the exponent. + // (actually no adder is needed) + // x380 => "0_0011_1000_0000 + // SP Dddd_dddd + // if D=0 0_0011_1ddd_dddd --> {D, !D, !D, !D} + // if D=1 0_0100_0ddd_dddd --> {D, !D, !D, !D} + // + // also for SP -> SP_infinity is converted to DP infinity + // -> (0) is converted to x381 (instead of x380) and the implicit bit is added. + // so .... there are now 2 numbers that mean zero + // 1) (exp==x001) and (IMP_bit==0) and (FRAC==0) + // 2) (exp==x381) and (IMP_bit==0) and (FRAC==0) + // the only time the SP load needs correcting (prenormalization) is + // (exp==x381) and (IMP_bit==0) and (FRAC==0) <== SP denorm can be converted to DP norm. + // + //------------------------------------------------------------------------------------------------ + // INPUT LOAD DATA FORMAT LdDin[0:63] : + // + // lfd lfs + // [00:00] sign [00:00] sign + // [01:11] exponent [01:08] exponent + // [12:63] fraction [09:31] fraction + // ----------------------------------------------------------------------------------------------- + // OUTPUT LOAD DATA FORMAT ... add implicit bit + // + // DP | SP + // ---------------------------------------------|------------------------------------------------- + // [00:00] Din[00] | Din[00] <--- Sgn + // [01:01] Din[01] | Din[01] <--- exp[00] //03 + // [02:02] Din[02] | ~Din[01] | (Din[01:08]="11111111") <--- exp[01] //04 + // [03:03] Din[03] | ~Din[01] | (Din[01:08]="11111111") <--- exp[02] //05 + // [04:04] Din[04] | ~Din[01] | (Din[01:08]="11111111") <--- exp[03] //06 + // [05:10] Din[05:10] | Din[02:07] <--- exp[04:09] //07:12 + // [11:11] Din[11] | (Din[01:11]="00000000000") | Din[08] | (Din[01:08]="00000000") <--- exp[10] //13 + // [12:12] ~(Din[01:11]="00000000000") | ~(Din[01:08]="00000000") <--- frac[00] //imlicit bit + // [13:35] Din[12:34] | Din[09:31] <--- frac[01:23] + // [36:64] Din[35:63] | (0:28=>'0') <--- frac[24:52] + // ---------------------------------------------|------------------------------------------------- + //------------------------------------------------------------------------------ + // LOAD FPU/FPR data format + // + // Double-precision load: lfd* + // + // Value Loaded Internal Representation [sign exponent imp fraction] Format name + // ------------ ---------------------------------------------------- ----------- + // 0 x 00000000001 0 0000... Zero + // Denormal x 00000000001 0 xxxx... Denormal + // Normal x xxxxxxxxxxx 1 xxxx... Normal + // Inf x 11111111111 1 0000... Inf + // NaN x 11111111111 1 qxxx... NaN + // + // Single-precision denormal form (SP_DENORM) + // exp = 0x381, imp = 0, frac != 0 (frac == 0: SP_DENORM0) + // + // Single-precision load: lfs* + // + // Value Loaded Internal Representation [sign exponent imp fraction] Format name + // ------------ ---------------------------------------------------- ----------- + // 0 x 01110000001 0 000000000000000000000000000... SP_DENORM0 + // Denormal x 01110000001 0 xxxxxxxxxxxxxxxxxxxxxxx0000... SP_DENORM + // Normal x xXXXxxxxxxx 1 xxxxxxxxxxxxxxxxxxxxxxx0000... Normal + // Inf x 11111111111 1 000000000000000000000000000... Inf + // NaN x 11111111111 1 qxxxxxxxxxxxxxxxxxxxxxx0000... NaN + //------------------------------------------------------------------------------ + // Convert Incoming SP loads to DP format + // DP bias = 1023 + // SP bias = 127 + // diff = x380 => 0_0011_1000_0000 + // SP Dddd_dddd + // if D=0, 0_0011_1ddd_dddd -> {D,!D,!D,!D} + // if D=1, 0_0100_0ddd_dddd -> {D,!D,!D,!D} + + // For lfiwax and lfiwzx, either set upper (32) to zeros or ones + assign load_int_1up = load_int & load_sign_ext & load_sp_data[0]; + assign reload_int_1up = reload_int & reload_sign_ext & reload_sp_data[0]; + + // Due to the XU rotator, all SP loads (words) are aligned to the right + assign ex6_load_sp_data_raw[0:31] = ex6_load_data_raw[32:63]; + assign ex6_reload_sp_data_raw[0:31] = ex6_reload_data_raw[32:63]; + + assign load_dp_exp_zero = ex6_load_data_raw[1:11] == 11'b00000000000; + assign load_sp_exp_zero = ex6_load_sp_data_raw[1:8] == 8'b00000000; + assign load_sp_exp_ones = ex6_load_sp_data_raw[1:8] == 8'b11111111; + + assign load_sp_data[0] = ex6_load_sp_data_raw[0]; // sign + assign load_sp_data[1] = tilo; // exp02 + assign load_sp_data[2] = ex6_load_sp_data_raw[1]; // exp03 + assign load_sp_data[3] = (~ex6_load_sp_data_raw[1]) | load_sp_exp_ones; // exp04 + assign load_sp_data[4] = (~ex6_load_sp_data_raw[1]) | load_sp_exp_ones; // exp05 + assign load_sp_data[5] = (~ex6_load_sp_data_raw[1]) | load_sp_exp_ones; // exp06 + assign load_sp_data[6:11] = ex6_load_sp_data_raw[2:7]; // exp07-12 + assign load_sp_data[12] = ex6_load_sp_data_raw[8] | load_sp_exp_zero; // exp13 + assign load_sp_data[13] = (~load_sp_exp_zero); // implicit + assign load_sp_data[14:36] = ex6_load_sp_data_raw[9:31]; // frac01:23 + assign load_sp_data[37:65] = {29{tilo}}; // frac24:52 + + assign load_dp_data[0] = (ex6_load_data_raw[0] & (~load_int)) | load_int_1up; // sign + assign load_dp_data[1] = tilo; // exp02 + assign load_dp_data[2:11] = (ex6_load_data_raw[1:10] & {10{(~load_int)}}) | {10{load_int_1up}}; // exp03-12 + assign load_dp_data[12] = (ex6_load_data_raw[11] | load_dp_exp_zero) | load_int | load_int_1up; // exp13 + assign load_dp_data[13] = ((~load_dp_exp_zero) & (~load_int)) | load_int_1up; // implicit + assign load_dp_data[14:33] = (ex6_load_data_raw[12:31] & {20{(~load_int)}}) | {20{load_int_1up}}; // fraction + assign load_dp_data[34:65] = ex6_load_data_raw[32:63]; // fraction + + assign ex6_load_data[0:65] = (load_dp_data[0:65] & {66{(~load_sp)}}) | (load_sp_data[0:65] & {66{load_sp}}); + + assign load_data_f0[0:73] = {ex6_load_data[0:65], load_data_parity[0:7]}; + assign load_data_f1[0:73] = {ex6_load_data[0:65], load_data_parity_inj[0:7]}; + + assign reload_dp_exp_zero = ex6_reload_data_raw[1:11] == 11'b00000000000; + assign reload_sp_exp_zero = ex6_reload_sp_data_raw[1:8] == 8'b00000000; + assign reload_sp_exp_ones = ex6_reload_sp_data_raw[1:8] == 8'b11111111; + + assign reload_sp_data[0] = ex6_reload_sp_data_raw[0]; // sign + assign reload_sp_data[1] = tilo; // exp02 + assign reload_sp_data[2] = ex6_reload_sp_data_raw[1]; // exp03 + assign reload_sp_data[3] = (~ex6_reload_sp_data_raw[1]) | reload_sp_exp_ones; // exp04 + assign reload_sp_data[4] = (~ex6_reload_sp_data_raw[1]) | reload_sp_exp_ones; // exp05 + assign reload_sp_data[5] = (~ex6_reload_sp_data_raw[1]) | reload_sp_exp_ones; // exp06 + assign reload_sp_data[6:11] = ex6_reload_sp_data_raw[2:7]; // exp07-12 + assign reload_sp_data[12] = ex6_reload_sp_data_raw[8] | reload_sp_exp_zero; // exp13 + assign reload_sp_data[13] = (~reload_sp_exp_zero); // implicit + assign reload_sp_data[14:36] = ex6_reload_sp_data_raw[9:31]; // frac01:23 + assign reload_sp_data[37:65] = {29{tilo}}; // frac24:52 + + assign reload_dp_data[0] = (ex6_reload_data_raw[0] & (~reload_int)) | reload_int_1up; // sign + assign reload_dp_data[1] = tilo; // exp02 + assign reload_dp_data[2:11] = (ex6_reload_data_raw[1:10] & {10{(~reload_int)}}) | {10{reload_int_1up}}; // exp03-12 + assign reload_dp_data[12] = (ex6_reload_data_raw[11] | reload_dp_exp_zero) | reload_int | reload_int_1up; // exp13 + assign reload_dp_data[13] = ((~reload_dp_exp_zero) & (~reload_int)) | reload_int_1up; // implicit + assign reload_dp_data[14:33] = (ex6_reload_data_raw[12:31] & {20{(~reload_int)}}) | {20{reload_int_1up}}; // fraction + assign reload_dp_data[34:65] = ex6_reload_data_raw[32:63]; // fraction + + assign ex6_reload_data[0:65] = (reload_dp_data[0:65] & {66{(~reload_sp)}}) | (reload_sp_data[0:65] & {66{reload_sp}}); + + assign reload_data_f0[0:73] = {ex6_reload_data[0:65], reload_data_parity[0:7]}; + assign reload_data_f1[0:73] = {ex6_reload_data[0:65], reload_data_parity_inj[0:7]}; + + + + assign ld_par0007 = ex6_load_data_raw[0] ^ ex6_load_data_raw[1] ^ ex6_load_data_raw[2] ^ ex6_load_data_raw[3] ^ ex6_load_data_raw[4] ^ ex6_load_data_raw[5] ^ ex6_load_data_raw[6] ^ ex6_load_data_raw[7]; + assign ld_par32_3436 = ex6_load_data_raw[32] ^ ex6_load_data_raw[34] ^ ex6_load_data_raw[35] ^ ex6_load_data_raw[36]; + assign ld_par0815 = ex6_load_data_raw[8] ^ ex6_load_data_raw[9] ^ ex6_load_data_raw[10] ^ ex6_load_data_raw[11] ^ ex6_load_data_raw[12] ^ ex6_load_data_raw[13] ^ ex6_load_data_raw[14] ^ ex6_load_data_raw[15]; + assign ld_par3744 = ex6_load_data_raw[37] ^ ex6_load_data_raw[38] ^ ex6_load_data_raw[39] ^ ex6_load_data_raw[40] ^ ex6_load_data_raw[41] ^ ex6_load_data_raw[42] ^ ex6_load_data_raw[43] ^ ex6_load_data_raw[44]; + assign ld_par1623 = ex6_load_data_raw[16] ^ ex6_load_data_raw[17] ^ ex6_load_data_raw[18] ^ ex6_load_data_raw[19] ^ ex6_load_data_raw[20] ^ ex6_load_data_raw[21] ^ ex6_load_data_raw[22] ^ ex6_load_data_raw[23]; + assign ld_par4552 = ex6_load_data_raw[45] ^ ex6_load_data_raw[46] ^ ex6_load_data_raw[47] ^ ex6_load_data_raw[48] ^ ex6_load_data_raw[49] ^ ex6_load_data_raw[50] ^ ex6_load_data_raw[51] ^ ex6_load_data_raw[52]; + assign ld_par2431 = ex6_load_data_raw[24] ^ ex6_load_data_raw[25] ^ ex6_load_data_raw[26] ^ ex6_load_data_raw[27] ^ ex6_load_data_raw[28] ^ ex6_load_data_raw[29] ^ ex6_load_data_raw[30] ^ ex6_load_data_raw[31]; + assign ld_par5360 = ex6_load_data_raw[53] ^ ex6_load_data_raw[54] ^ ex6_load_data_raw[55] ^ ex6_load_data_raw[56] ^ ex6_load_data_raw[57] ^ ex6_load_data_raw[58] ^ ex6_load_data_raw[59] ^ ex6_load_data_raw[60]; + assign ld_par3239 = ex6_load_data_raw[32] ^ ex6_load_data_raw[33] ^ ex6_load_data_raw[34] ^ ex6_load_data_raw[35] ^ ex6_load_data_raw[36] ^ ex6_load_data_raw[37] ^ ex6_load_data_raw[38] ^ ex6_load_data_raw[39]; + assign ld_par4047 = ex6_load_data_raw[40] ^ ex6_load_data_raw[41] ^ ex6_load_data_raw[42] ^ ex6_load_data_raw[43] ^ ex6_load_data_raw[44] ^ ex6_load_data_raw[45] ^ ex6_load_data_raw[46] ^ ex6_load_data_raw[47]; + assign ld_par4855 = ex6_load_data_raw[48] ^ ex6_load_data_raw[49] ^ ex6_load_data_raw[50] ^ ex6_load_data_raw[51] ^ ex6_load_data_raw[52] ^ ex6_load_data_raw[53] ^ ex6_load_data_raw[54] ^ ex6_load_data_raw[55]; + assign ld_par5663 = ex6_load_data_raw[56] ^ ex6_load_data_raw[57] ^ ex6_load_data_raw[58] ^ ex6_load_data_raw[59] ^ ex6_load_data_raw[60] ^ ex6_load_data_raw[61] ^ ex6_load_data_raw[62] ^ ex6_load_data_raw[63]; + + assign ld_par3239_inj = ex6_load_data_raw[32] ^ ex6_load_data_raw[33] ^ ex6_load_data_raw[34] ^ ex6_load_data_raw[35] ^ ex6_load_data_raw[36] ^ ex6_load_data_raw[37] ^ ex6_load_data_raw[38] ^ ex6_load_data_raw[39] ^ ex7_ld_perr_inj; + + assign ld_par6163 = ex6_load_data_raw[61] ^ ex6_load_data_raw[62] ^ ex6_load_data_raw[63]; + assign ld_par6163_inj = ex6_load_data_raw[61] ^ ex6_load_data_raw[62] ^ ex6_load_data_raw[63] ^ ex7_ld_perr_inj; + + //ld_pgen_premux + + assign load_dp_nint = (~load_sp) & (~load_int); + assign load_dp_int = (~load_sp) & load_int; + assign load_sp_all1 = load_sp & load_sp_exp_ones; + assign load_sp_nall1 = load_sp & (~load_sp_exp_ones); + + assign load_data_parity[0] = (ld_par0007 & load_dp_nint) | (ld_par32_3436 & load_sp_all1) | ((~ld_par32_3436) & load_sp_nall1); + assign load_data_parity[1] = ((~ld_par0815) & load_dp_nint) | ((~ld_par3744) & load_sp) | load_dp_int; + assign load_data_parity[2] = (ld_par1623 & load_dp_nint) | (ld_par4552 & load_sp); + assign load_data_parity[3] = (ld_par2431 & load_dp_nint) | (ld_par5360 & load_sp); + assign load_data_parity[4] = (ld_par3239 & (~load_sp)) | (ld_par6163 & load_sp); + assign load_data_parity[5] = (ld_par4047 & (~load_sp)); + assign load_data_parity[6] = (ld_par4855 & (~load_sp)); + assign load_data_parity[7] = (ld_par5663 & (~load_sp)); + + + assign load_data_parity_inj[0] = (ld_par0007 & load_dp_nint) | (ld_par32_3436 & load_sp_all1) | ((~ld_par32_3436) & load_sp_nall1); + assign load_data_parity_inj[1] = ((~ld_par0815) & load_dp_nint) | ((~ld_par3744) & load_sp) | load_dp_int; + assign load_data_parity_inj[2] = (ld_par1623 & load_dp_nint) | (ld_par4552 & load_sp); + assign load_data_parity_inj[3] = (ld_par2431 & load_dp_nint) | (ld_par5360 & load_sp); + assign load_data_parity_inj[4] = (ld_par3239_inj & (~load_sp)) | (ld_par6163_inj & load_sp); + assign load_data_parity_inj[5] = (ld_par4047 & (~load_sp)); + assign load_data_parity_inj[6] = (ld_par4855 & (~load_sp)); + assign load_data_parity_inj[7] = (ld_par5663 & (~load_sp)); + + + + + assign rld_par0007 = ex6_reload_data_raw[0] ^ ex6_reload_data_raw[1] ^ ex6_reload_data_raw[2] ^ ex6_reload_data_raw[3] ^ ex6_reload_data_raw[4] ^ ex6_reload_data_raw[5] ^ ex6_reload_data_raw[6] ^ ex6_reload_data_raw[7]; //rld_pgen_premux-- + + assign rld_par32_3436 = ex6_reload_data_raw[32] ^ ex6_reload_data_raw[34] ^ ex6_reload_data_raw[35] ^ ex6_reload_data_raw[36]; //rld_pgen_premux-- + + assign rld_par0815 = ex6_reload_data_raw[8] ^ ex6_reload_data_raw[9] ^ ex6_reload_data_raw[10] ^ ex6_reload_data_raw[11] ^ ex6_reload_data_raw[12] ^ ex6_reload_data_raw[13] ^ ex6_reload_data_raw[14] ^ ex6_reload_data_raw[15]; //rld_pgen_premux-- + assign rld_par3744 = ex6_reload_data_raw[37] ^ ex6_reload_data_raw[38] ^ ex6_reload_data_raw[39] ^ ex6_reload_data_raw[40] ^ ex6_reload_data_raw[41] ^ ex6_reload_data_raw[42] ^ ex6_reload_data_raw[43] ^ ex6_reload_data_raw[44]; //rld_pgen_premux-- + assign rld_par1623 = ex6_reload_data_raw[16] ^ ex6_reload_data_raw[17] ^ ex6_reload_data_raw[18] ^ ex6_reload_data_raw[19] ^ ex6_reload_data_raw[20] ^ ex6_reload_data_raw[21] ^ ex6_reload_data_raw[22] ^ ex6_reload_data_raw[23]; //rld_pgen_premux-- + assign rld_par4552 = ex6_reload_data_raw[45] ^ ex6_reload_data_raw[46] ^ ex6_reload_data_raw[47] ^ ex6_reload_data_raw[48] ^ ex6_reload_data_raw[49] ^ ex6_reload_data_raw[50] ^ ex6_reload_data_raw[51] ^ ex6_reload_data_raw[52]; //rld_pgen_premux-- + assign rld_par2431 = ex6_reload_data_raw[24] ^ ex6_reload_data_raw[25] ^ ex6_reload_data_raw[26] ^ ex6_reload_data_raw[27] ^ ex6_reload_data_raw[28] ^ ex6_reload_data_raw[29] ^ ex6_reload_data_raw[30] ^ ex6_reload_data_raw[31]; //rld_pgen_premux-- + assign rld_par5360 = ex6_reload_data_raw[53] ^ ex6_reload_data_raw[54] ^ ex6_reload_data_raw[55] ^ ex6_reload_data_raw[56] ^ ex6_reload_data_raw[57] ^ ex6_reload_data_raw[58] ^ ex6_reload_data_raw[59] ^ ex6_reload_data_raw[60]; //rld_pgen_premux-- + assign rld_par3239 = ex6_reload_data_raw[32] ^ ex6_reload_data_raw[33] ^ ex6_reload_data_raw[34] ^ ex6_reload_data_raw[35] ^ ex6_reload_data_raw[36] ^ ex6_reload_data_raw[37] ^ ex6_reload_data_raw[38] ^ ex6_reload_data_raw[39]; //rld_pgen_premux-- + + assign rld_par4047 = ex6_reload_data_raw[40] ^ ex6_reload_data_raw[41] ^ ex6_reload_data_raw[42] ^ ex6_reload_data_raw[43] ^ ex6_reload_data_raw[44] ^ ex6_reload_data_raw[45] ^ ex6_reload_data_raw[46] ^ ex6_reload_data_raw[47]; //rld_pgen_premux-- + assign rld_par4855 = ex6_reload_data_raw[48] ^ ex6_reload_data_raw[49] ^ ex6_reload_data_raw[50] ^ ex6_reload_data_raw[51] ^ ex6_reload_data_raw[52] ^ ex6_reload_data_raw[53] ^ ex6_reload_data_raw[54] ^ ex6_reload_data_raw[55]; //rld_pgen_premux-- + assign rld_par5663 = ex6_reload_data_raw[56] ^ ex6_reload_data_raw[57] ^ ex6_reload_data_raw[58] ^ ex6_reload_data_raw[59] ^ ex6_reload_data_raw[60] ^ ex6_reload_data_raw[61] ^ ex6_reload_data_raw[62] ^ ex6_reload_data_raw[63]; //rld_pgen_premux-- + assign rld_par6163 = ex6_reload_data_raw[61] ^ ex6_reload_data_raw[62] ^ ex6_reload_data_raw[63]; //rld_pgen_premux-- + + assign rld_par3239_inj = ex6_reload_data_raw[32] ^ ex6_reload_data_raw[33] ^ ex6_reload_data_raw[34] ^ ex6_reload_data_raw[35] ^ ex6_reload_data_raw[36] ^ ex6_reload_data_raw[37] ^ ex6_reload_data_raw[38] ^ ex6_reload_data_raw[39] ^ ex7_rld_perr_inj; //rld_pgen_premux-- + assign rld_par6163_inj = ex6_reload_data_raw[61] ^ ex6_reload_data_raw[62] ^ ex6_reload_data_raw[63] ^ ex7_rld_perr_inj; //rld_pgen_premux-- + + + + + assign reload_dp_nint = (~reload_sp) & (~reload_int); //rld_pgen_premux-- + assign reload_dp_int = (~reload_sp) & reload_int; //rld_pgen_premux-- + assign reload_sp_all1 = reload_sp & reload_sp_exp_ones; //rld_pgen_premux-- + assign reload_sp_nall1 = reload_sp & (~reload_sp_exp_ones); //rld_pgen_premux-- + + assign reload_data_parity[0] = (rld_par0007 & reload_dp_nint) | (rld_par32_3436 & reload_sp_all1) | ((~rld_par32_3436) & reload_sp_nall1); //rld_pgen_premux-- + assign reload_data_parity[1] = ((~rld_par0815) & reload_dp_nint) | ((~rld_par3744) & reload_sp) | reload_dp_int; //rld_pgen_premux-- + assign reload_data_parity[2] = (rld_par1623 & reload_dp_nint) | (rld_par4552 & reload_sp); //rld_pgen_premux-- + assign reload_data_parity[3] = (rld_par2431 & reload_dp_nint) | (rld_par5360 & reload_sp); //rld_pgen_premux-- + assign reload_data_parity[4] = (rld_par3239 & (~reload_sp)) | (rld_par6163 & reload_sp); //rld_pgen_premux-- + assign reload_data_parity[5] = (rld_par4047 & (~reload_sp)); //rld_pgen_premux-- + assign reload_data_parity[6] = (rld_par4855 & (~reload_sp)); //rld_pgen_premux-- + assign reload_data_parity[7] = (rld_par5663 & (~reload_sp)); //rld_pgen_premux-- + + + assign reload_data_parity_inj[0] = (rld_par0007 & reload_dp_nint) | (rld_par32_3436 & reload_sp_all1) | ((~rld_par32_3436) & reload_sp_nall1); //rld_pgen_premux-- + assign reload_data_parity_inj[1] = ((~rld_par0815) & reload_dp_nint) | ((~rld_par3744) & reload_sp) | reload_dp_int; //rld_pgen_premux-- + assign reload_data_parity_inj[2] = (rld_par1623 & reload_dp_nint) | (rld_par4552 & reload_sp); //rld_pgen_premux-- + assign reload_data_parity_inj[3] = (rld_par2431 & reload_dp_nint) | (rld_par5360 & reload_sp); //rld_pgen_premux-- + assign reload_data_parity_inj[4] = (rld_par3239_inj & (~reload_sp)) | (rld_par6163_inj & reload_sp); //rld_pgen_premux-- + assign reload_data_parity_inj[5] = (rld_par4047 & (~reload_sp)); //rld_pgen_premux-- + assign reload_data_parity_inj[6] = (rld_par4855 & (~reload_sp)); //rld_pgen_premux-- + assign reload_data_parity_inj[7] = (rld_par5663 & (~reload_sp)); //rld_pgen_premux-- + + + + + //verity_out(0 to 73) <= load_data(0 to 73) ; --VERTIY-- + + //---------------------------------------------------------------------- + // Target Data + + generate + if (threads == 1) + begin : frt_addr_thr_1 + assign frt_addr[1:7] = {1'b0, f_dcd_ex7_frt_addr[0:5]}; + assign spare_unused[1] = f_dcd_ex7_frt_tid[1]; + end + endgenerate + + generate + if (threads == 2) + begin : frt_addr_thr_2 + assign frt_addr[1:7] = {f_dcd_ex7_frt_addr[0:5], f_dcd_ex7_frt_tid[1]}; + assign spare_unused[1] = tidn; + end + endgenerate + + assign frt_wen = f_dcd_ex7_frt_wen; + assign frt_data[0:63] = {f_rnd_ex7_res_sign, f_rnd_ex7_res_expo[3:13], f_rnd_ex7_res_frac[1:52]}; + + assign frt_data_parity[0] = f_rnd_ex7_res_sign ^ f_rnd_ex7_res_expo[1] ^ f_rnd_ex7_res_expo[2] ^ f_rnd_ex7_res_expo[3] ^ f_rnd_ex7_res_expo[4] ^ f_rnd_ex7_res_expo[5] ^ f_rnd_ex7_res_expo[6] ^ f_rnd_ex7_res_expo[7] ^ f_rnd_ex7_res_expo[8] ^ f_rnd_ex7_res_expo[9]; + assign frt_data_parity[1] = f_rnd_ex7_res_expo[10] ^ f_rnd_ex7_res_expo[11] ^ f_rnd_ex7_res_expo[12] ^ f_rnd_ex7_res_expo[13] ^ f_rnd_ex7_res_frac[0] ^ f_rnd_ex7_res_frac[1] ^ f_rnd_ex7_res_frac[2] ^ f_rnd_ex7_res_frac[3] ^ f_rnd_ex7_res_frac[4]; + assign frt_data_parity[2] = f_rnd_ex7_res_frac[5] ^ f_rnd_ex7_res_frac[6] ^ f_rnd_ex7_res_frac[7] ^ f_rnd_ex7_res_frac[8] ^ f_rnd_ex7_res_frac[9] ^ f_rnd_ex7_res_frac[10] ^ f_rnd_ex7_res_frac[11] ^ f_rnd_ex7_res_frac[12]; + assign frt_data_parity[3] = f_rnd_ex7_res_frac[13] ^ f_rnd_ex7_res_frac[14] ^ f_rnd_ex7_res_frac[15] ^ f_rnd_ex7_res_frac[16] ^ f_rnd_ex7_res_frac[17] ^ f_rnd_ex7_res_frac[18] ^ f_rnd_ex7_res_frac[19] ^ f_rnd_ex7_res_frac[20]; + assign frt_data_parity[4] = f_rnd_ex7_res_frac[21] ^ f_rnd_ex7_res_frac[22] ^ f_rnd_ex7_res_frac[23] ^ f_rnd_ex7_res_frac[24] ^ f_rnd_ex7_res_frac[25] ^ f_rnd_ex7_res_frac[26] ^ f_rnd_ex7_res_frac[27] ^ f_rnd_ex7_res_frac[28]; + assign frt_data_parity[5] = f_rnd_ex7_res_frac[29] ^ f_rnd_ex7_res_frac[30] ^ f_rnd_ex7_res_frac[31] ^ f_rnd_ex7_res_frac[32] ^ f_rnd_ex7_res_frac[33] ^ f_rnd_ex7_res_frac[34] ^ f_rnd_ex7_res_frac[35] ^ f_rnd_ex7_res_frac[36]; + assign frt_data_parity[6] = f_rnd_ex7_res_frac[37] ^ f_rnd_ex7_res_frac[38] ^ f_rnd_ex7_res_frac[39] ^ f_rnd_ex7_res_frac[40] ^ f_rnd_ex7_res_frac[41] ^ f_rnd_ex7_res_frac[42] ^ f_rnd_ex7_res_frac[43] ^ f_rnd_ex7_res_frac[44]; + assign frt_data_parity[7] = f_rnd_ex7_res_frac[45] ^ f_rnd_ex7_res_frac[46] ^ f_rnd_ex7_res_frac[47] ^ f_rnd_ex7_res_frac[48] ^ f_rnd_ex7_res_frac[49] ^ f_rnd_ex7_res_frac[50] ^ f_rnd_ex7_res_frac[51] ^ f_rnd_ex7_res_frac[52]; + + //---------------------------------------------------------------------- + // Source Address + + generate + if (threads == 1) + begin : addr_gen_1 + assign rf0_fra_addr[1:7] = {1'b0, f_dcd_rf0_fra[0:5]}; //uc_hook + assign rf0_frb_addr[1:7] = {1'b0, f_dcd_rf0_frb[0:5]}; + assign rf0_frc_addr[1:7] = {1'b0, f_dcd_rf0_frc[0:5]}; + end + endgenerate + + generate + if (threads == 2) + begin : addr_gen_2 + assign rf0_fra_addr[1:7] = {f_dcd_rf0_fra[0:5], f_dcd_rf0_tid[1]}; //uc_hook + assign rf0_frb_addr[1:7] = {f_dcd_rf0_frb[0:5], f_dcd_rf0_tid[1]}; + assign rf0_frc_addr[1:7] = {f_dcd_rf0_frc[0:5], f_dcd_rf0_tid[1]}; + end + endgenerate + + assign rf0_frs_addr[1:7] = iu_fu_rf0_ldst_tag[3:9]; + + // Microcode Scratch Registers + assign rf0_fra_addr[0] = tilo; // uc_hook + assign rf0_frb_addr[0] = tilo; + assign rf0_frc_addr[0] = tilo; + + assign frt_addr[0] = tilo; + assign rf0_frs_addr[0] = tilo; // Don't need to store from scratch regs + assign load_addr[0] = tilo; // Don't need to load into scratch regs + + // For bypass writethru compare + assign f_fpr_ex6_load_addr[0:7] = {1'b0, ex6_load_tag[3:9]}; // bit 9 is the tid + assign f_fpr_ex6_reload_addr[0:7] = {1'b0, ex6_reload_tag[3:9]}; // bit 9 is the tid + + assign f_fpr_ex6_load_v = load_wen; + assign f_fpr_ex6_reload_v = reload_wen; + + //---------------------------------------------------------------------- + // RF0 + + //---------------------------------------------------------------------- + // RF1 + + assign w0e_en_func = load_wen; + assign w0e_addr_func[0:7] = load_addr[0:7]; + assign w0l_en_func = frt_wen; + assign w0l_addr_func[0:7] = frt_addr[0:7]; + + //parity(0 to 7)<= data(66 to 73) 0:7 + //"000" 8:10 + //sign <= data(0); 11 + //expo(1) 12 + //expo(2 to 13) <= data(1 to 12); 13:24 + //frac(0 to 52) <= data(13 to 65); 25:77 + + assign w0e_data_func_f0[0:77] = {load_data_f0[66:73], 3'b000, load_data_f0[0], 1'b0, load_data_f0[1:65]}; + assign w0e_data_func_f1[0:77] = {load_data_f1[66:73], 3'b000, load_data_f1[0], 1'b0, load_data_f1[1:65]}; + + assign rel_data_func_f0[0:77] = {reload_data_f0[66:73], 3'b000, reload_data_f0[0], 1'b0, reload_data_f0[1:65]}; + assign rel_data_func_f1[0:77] = {reload_data_f1[66:73], 3'b000, reload_data_f1[0], 1'b0, reload_data_f1[1:65]}; + + + assign w0l_data_func_f0[0:77] = {frt_data_parity[0:7], 3'b000, f_rnd_ex7_res_sign, f_rnd_ex7_res_expo[1:13], f_rnd_ex7_res_frac[0:52]}; + assign w0l_data_func_f1[0:77] = {frt_data_parity[0:6], (frt_data_parity[7] ^ ex7_targ_perr_inj), 3'b000, f_rnd_ex7_res_sign, f_rnd_ex7_res_expo[1:13], f_rnd_ex7_res_frac[0:52]}; + + assign rf1_fra[0:77] = fra_data_out[0:77]; //frac + assign rf1_frb[0:77] = frb_data_out[0:77]; //frac + assign rf1_frc[0:77] = frc_data_out[0:77]; //frac + assign rf1_frs[0:77] = frs_data_out[0:77]; //frac + + // -- Array Instantiation + // f0 : entity tri.tri_144x78_2r2w + // generic map (expand_type => expand_type) + // port map( + // vdd => vdd , + // gnd => gnd , + // nclk => nclk , + // abist_en => pc_fu_abist_ena_dc , + // abist_raw_dc_b => pc_fu_abist_raw_dc_b , + // r0e_abist_comp_en => r0e_abist_comp_en , + // r1e_abist_comp_en => r1e_abist_comp_en , + //-- lbist_en => lbist_en_dc , + //-- tri_state_en => tri_state_en , + // lcb_act_dis_dc => lcb_act_dis_dc , + // lcb_clkoff_dc_b => lcb_clkoff_dc_b , + // lcb_d_mode_dc => lcb_d_mode_dc , + // lcb_delay_lclkr_dc => lcb_delay_lclkr_dc , + // lcb_fce_0 => fce_0 , + // lcb_mpw1_dc_b => lcb_mpw1_dc_b(1 to 6) , + // lcb_mpw2_dc_b => lcb_mpw2_dc_b , + // lcb_scan_diag_dc => scan_diag_dc , + // lcb_scan_dis_dc_b => scan_dis_dc_b , + // lcb_sg_0 => lcb_sg_0 , + // lcb_abst_sl_thold_0 => lcb_abst_sl_thold_0 , + // lcb_ary_nsl_thold_0 => ary_nsl_thold_0 , + // r_scan_in => r_scan_in_0 , + // r_scan_out => r_scan_out_0 , + // w_scan_in => w_scan_in_0 , + // w_scan_out => w_scan_out_0 , + // -- Read Port FRA + // r0e_act => r0e_act , + // r0e_en_func => r0e_en_func , + // r0e_en_abist => r0e_en_abist , + // r0e_addr_func => rf0_fra_addr , + // r0e_addr_abist => r0e_addr_abist , + // r0e_data_out => fra_data_out , + // r0e_byp_e => rf1_bypsel_a_load1 , + // r0e_byp_l => rf1_bypsel_a_res1 , + // r0e_byp_r => rf1_a_r0e_byp_r, + // -- Read Port FRC + // r1e_act => r1e_act , + // r1e_en_func => r1e_en_func , + // r1e_en_abist => r1e_en_abist , + // r1e_addr_func => rf0_frc_addr , + // r1e_addr_abist => r1e_addr_abist , + // r1e_data_out => frc_data_out , + // r1e_byp_e => rf1_bypsel_c_load1 , + // r1e_byp_l => rf1_bypsel_c_res1 , + // r1e_byp_r => rf1_c_r1e_byp_r, + // -- Write Ports + // w0e_act => w0e_act , + // w0e_en_func => w0e_en_func , + // w0e_en_abist => w0e_en_abist , + // w0e_addr_func => w0e_addr_func , + // w0e_addr_abist => w0e_addr_abist , + // w0e_data_func => w0e_data_func , + // w0e_data_abist => w0e_data_abist , + // w0e_pw_sel => "0000", -- TODO + // w0e_rsdly_sel => "00", -- TODO + // w0l_act => w0l_act , + // w0l_en_func => w0l_en_func , + // w0l_en_abist => w0l_en_abist , + // w0l_addr_func => w0l_addr_func , + // w0l_addr_abist => w0l_addr_abist , + // w0l_data_func => w0l_data_func , + // w0l_data_abist => w0l_data_abist , + // w0l_pw_sel => "0000", -- TODO + // w0l_rsdly_sel => "00" -- TODO + // ); + + // -- Array Instantiation + // f1 : entity tri.tri_144x78_2r2w + // generic map (expand_type => expand_type) + // port map( + // vdd => vdd , + // gnd => gnd , + // nclk => nclk , + // abist_en => pc_fu_abist_ena_dc , + // abist_raw_dc_b => pc_fu_abist_raw_dc_b , + // r0e_abist_comp_en => r0e_abist_comp_en , + // r1e_abist_comp_en => r1e_abist_comp_en , + //-- lbist_en => lbist_en_dc , + //-- tri_state_en => tri_state_en , + // lcb_act_dis_dc => lcb_act_dis_dc , + // lcb_clkoff_dc_b => lcb_clkoff_dc_b , + // lcb_d_mode_dc => lcb_d_mode_dc , + // lcb_delay_lclkr_dc => lcb_delay_lclkr_dc , + // lcb_fce_0 => fce_0 , + // lcb_mpw1_dc_b => lcb_mpw1_dc_b(1 to 6) , + // lcb_mpw2_dc_b => lcb_mpw2_dc_b , + // lcb_scan_diag_dc => scan_diag_dc , + // lcb_scan_dis_dc_b => scan_dis_dc_b , + // lcb_sg_0 => lcb_sg_0 , + // lcb_abst_sl_thold_0 => lcb_abst_sl_thold_0 , + // lcb_ary_nsl_thold_0 => ary_nsl_thold_0 , + // r_scan_in => r_scan_in_1 , + // r_scan_out => r_scan_out_1 , + // w_scan_in => w_scan_in_1 , + // w_scan_out => w_scan_out_1 , + // -- Read Port FRB + // r0e_act => r0e_act , + // r0e_en_func => r0e_en_func , + // r0e_en_abist => r0e_en_abist , + // r0e_addr_func => rf0_frb_addr , + // r0e_addr_abist => r0e_addr_abist , + // r0e_data_out => frb_data_out , + // r0e_byp_e => rf1_bypsel_b_load1 , + // r0e_byp_l => rf1_bypsel_b_res1 , + // r0e_byp_r => rf1_b_r0e_byp_r, + // -- Read Port FRS + // r1e_act => r1e_act , + // r1e_en_func => r1e_en_func , + // r1e_en_abist => r1e_en_abist , + // r1e_addr_func => rf0_frs_addr , + // r1e_addr_abist => r1e_addr_abist , + // r1e_data_out => frs_data_out , + // r1e_byp_e => rf1_bypsel_s_load1 , + // r1e_byp_l => rf1_bypsel_s_res1 , + // r1e_byp_r => rf1_s_r1e_byp_r, + // -- Write Ports + // w0e_act => w0e_act , + // w0e_en_func => w0e_en_func , + // w0e_en_abist => w0e_en_abist , + // w0e_addr_func => w0e_addr_func , + // w0e_addr_abist => w0e_addr_abist , + // w0e_data_func => w0e_data_func , + // w0e_data_abist => w0e_data_abist , + // w0e_pw_sel => "0000", -- TODO + // w0e_rsdly_sel => "00", -- TODO + // w0l_act => w0l_act , + // w0l_en_func => w0l_en_func , + // w0l_en_abist => w0l_en_abist , + // w0l_addr_func => w0l_addr_func , + // w0l_addr_abist => w0l_addr_abist , + // w0l_data_func => w0l_data_func , + // w0l_data_abist => w0l_data_abist , + // w0l_pw_sel => "0000", -- TODO + // w0l_rsdly_sel => "00" -- TODO + // ); + + // + + assign r0e_en_func = tiup; + assign r1e_en_func = tiup; + + + tri_144x78_2r4w fpr0( // .regsize(64), #( .gpr_pool(fpr_pool), .gpr_pool_enc(fpr_pool_enc)) + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .delay_lclkr_dc(delay_lclkra[0]), + .mpw1_dc_b(mpw1_ba[0]), + .mpw2_dc_b(mpw2_b[0]), + .func_sl_force(force_t), + .func_sl_thold_0_b(thold_0_b), + .func_slp_sl_force(force_t), + .func_slp_sl_thold_0_b(thold_0_b), + .sg_0(sg_0), + .scan_in(scan_in_0), + .scan_out(scan_out_0), + // Read Port FRA + .r_late_en_1(r0e_en_func), + .r_addr_in_1(rf0_fra_addr[(3 - threads):7]), // rf0_fra_addr(1 to 7), + .r_data_out_1(fra_data_out), + // Read Port FRC + .r_late_en_2(r1e_en_func), + .r_addr_in_2(rf0_frc_addr[(3 - threads):7]), //rf0_frc_addr(1 to 7), + .r_data_out_2(frc_data_out), + // Write Ports + .w_late_en_1(w0e_en_func), + .w_addr_in_1(w0e_addr_func[(3 - threads):7]), //w0e_addr_func(1 to 7), + .w_data_in_1(w0e_data_func_f0), + .w_late_en_2(w0l_en_func), + .w_addr_in_2(w0l_addr_func[(3 - threads):7]), //w0l_addr_func(1 to 7) + .w_data_in_2(w0l_data_func_f0), + .w_late_en_3(reload_wen), + .w_addr_in_3(reload_addr[(3 - threads):7]), //reload_addr(1 to 7), + .w_data_in_3(rel_data_func_f0), + .w_late_en_4(tilo), + .w_addr_in_4(zeros[(3 - threads):7]), + .w_data_in_4(zeros[0:77]) + ); + + + tri_144x78_2r4w fpr1(// .regsize(64),#( .gpr_pool(fpr_pool), .gpr_pool_enc(fpr_pool_enc)) + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .delay_lclkr_dc(delay_lclkra[0]), + .mpw1_dc_b(mpw1_ba[0]), + .mpw2_dc_b(mpw2_b[0]), + .func_sl_force(force_t), + .func_sl_thold_0_b(thold_0_b), + .func_slp_sl_force(force_t), + .func_slp_sl_thold_0_b(thold_0_b), + .sg_0(sg_0), + .scan_in(scan_in_1), + .scan_out(scan_out_1), + // Read Port FRB + .r_late_en_1(r0e_en_func), + .r_addr_in_1(rf0_frb_addr[(3 - threads):7]), //rf0_frb_addr(1 to 7), + .r_data_out_1(frb_data_out), + // Read Port FRS + .r_late_en_2(r1e_en_func), + .r_addr_in_2(rf0_frs_addr[(3 - threads):7]), //rf0_frs_addr(1 to 7), + .r_data_out_2(frs_data_out), + // Write Ports + .w_late_en_1(w0e_en_func), + .w_addr_in_1(w0e_addr_func[(3 - threads):7]), //w0e_addr_func(1 to 7), + .w_data_in_1(w0e_data_func_f1), + .w_late_en_2(w0l_en_func), + .w_addr_in_2(w0l_addr_func[(3 - threads):7]), //w0l_addr_func(1 to 7), + .w_data_in_2(w0l_data_func_f1), + .w_late_en_3(reload_wen), + .w_addr_in_3(reload_addr[(3 - threads):7]), //reload_addr(1 to 7), + .w_data_in_3(rel_data_func_f1), + .w_late_en_4(tilo), + .w_addr_in_4(zeros[(3 - threads):7]), + .w_data_in_4(zeros[0:77]) + ); + + // ABIST timing latches + + tri_rlmreg_p #(.INIT(0), .WIDTH(53), .NEEDS_SRESET(0)) ab_reg( + .nclk(nclk), + .act(tihi), + .force_t(ab_force), + .d_mode(tiup), + .delay_lclkr(delay_lclkra[0]), + .mpw1_b(mpw1_ba[0]), + .mpw2_b(mpw2_b[0]), + .thold_b(ab_thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(ab_reg_si[0:52]), + .scout(ab_reg_so[0:52]), + .din({ pc_fu_abist_di_0[0:3], + pc_fu_abist_di_1[0:3], + pc_fu_abist_grf_renb_0, + pc_fu_abist_grf_renb_1, + pc_fu_abist_grf_wenb_0, + pc_fu_abist_grf_wenb_1, + pc_fu_abist_raddr_0[0:9], + pc_fu_abist_raddr_1[0:9], + pc_fu_abist_waddr_0[0:9], + pc_fu_abist_waddr_1[0:9], + pc_fu_abist_wl144_comp_ena}), + .dout({ w0e_data_abist[0:3], + w0l_data_abist[0:3], + r0e_en_abist, + r1e_en_abist, + w0e_en_abist, + w0l_en_abist, + abist_raddr_0[0:9], + abist_raddr_1[0:9], + abist_waddr_0[0:9], + abist_waddr_1[0:9], + abist_comp_en }) + ); + + + tri_lcbcntl_array_mac lcbctrl( + .vdd(vdd), + .gnd(gnd), + .sg(sg_0), + .nclk(nclk), + .scan_in(time_scan_in), // Connects to time scan ring + .scan_diag_dc(scan_diag_dc), + .thold(time_sl_thold_0), //Connects to time thold + .clkoff_dc_b(clkoff_dc_b), + .delay_lclkr_dc(lcb_delay_lclkr_dc[0:4]), + .act_dis_dc(lcb_act_dis_dc), + .d_mode_dc(d_mode_dc), + .mpw1_dc_b(lcb_mpw1_dc_b[0:4]), + .mpw2_dc_b(lcb_mpw2_dc_b), + .scan_out(time_scan_out) // Connects to time scan ring + ); + + assign lcb_mpw1_dc_b[5:6] = 2'b00; // TODO: What is to be done with this? + + // Other inputs + assign r0e_abist_comp_en = abist_comp_en; + assign r1e_abist_comp_en = abist_comp_en; + + assign lcb_sg_0 = sg_0; + assign lcb_abst_sl_thold_0 = ab_thold_0; + + assign lcb_d_mode_dc = d_mode_dc; + assign lcb_clkoff_dc_b = {2{clkoff_dc_b}}; + + + assign r0e_addr_abist[0:7] = abist_raddr_0[2:9]; + + assign r1e_addr_abist[0:7] = abist_raddr_1[2:9]; + assign w0e_act = 1'b1; + assign w0e_addr_abist[0:7] = abist_waddr_1[2:9]; + assign w0l_act = 1'b1; + assign w0l_addr_abist[0:7] = abist_waddr_1[2:9]; + + //---------------------------------------------------------------------- + // Parity Checking + + + tri_rlmreg_p #(.INIT(0), .WIDTH(34), .NEEDS_SRESET(0)) ex1_par( + .nclk(nclk), + .act(tihi), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkra[1]), + .mpw1_b(mpw1_ba[1]), + .mpw2_b(mpw2_b[0]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(ex1_par_si[0:33]), + .scout(ex1_par_so[0:33]), + .din({ rf1_fra[0:7], + rf1_frb[0:7], + rf1_frc[0:7], + rf1_frs[0:7], + rf1_frs[12:13]}), + + .dout({ ex1_fra_par[0:7], + ex1_frb_par[0:7], + ex1_frc_par[0:7], + ex1_frs_par[0:7], + ex1_s_expo_extra[0:1]}) + ); + + assign f_fpr_ex2_a_par[0:7] = ex1_fra_par[0:7]; + assign f_fpr_ex2_b_par[0:7] = ex1_frb_par[0:7]; + assign f_fpr_ex2_c_par[0:7] = ex1_frc_par[0:7]; + assign f_fpr_ex2_s_par[0:7] = ex1_frs_par[0:7]; + + //---------------------------------------------------------------------- + // Read Port Outputs + + //parity(0 to 7)<= data(66 to 73) 0:7 + //"000" 8:10 + //sign <= data(0); 11 + //expo(1) 12 + //expo(2 to 13) <= data(1 to 12); 13:24 + //frac(0 to 52) <= data(13 to 65); 25:77 + + assign f_fpr_ex1_a_sign = rf1_fra[11]; + assign f_fpr_ex1_a_expo[1:13] = rf1_fra[12:24]; + assign f_fpr_ex1_a_frac[0:52] = rf1_fra[25:77]; + assign f_fpr_ex1_c_sign = rf1_frc[11]; + assign f_fpr_ex1_c_expo[1:13] = rf1_frc[12:24]; + assign f_fpr_ex1_c_frac[0:52] = rf1_frc[25:77]; + assign f_fpr_ex1_b_sign = rf1_frb[11]; + assign f_fpr_ex1_b_expo[1:13] = rf1_frb[12:24]; + assign f_fpr_ex1_b_frac[0:52] = rf1_frb[25:77]; + + assign f_fpr_ex1_s_sign = rf1_frs[11]; + assign f_fpr_ex1_s_expo[1:11] = rf1_frs[14:24]; + assign f_fpr_ex1_s_frac[0:52] = rf1_frs[25:77]; + // For Parity checking only, not used by store + assign f_fpr_ex2_s_expo_extra = ex1_s_expo_extra; + + //---------------------------------------------------------------------- + // Write-thru bypass + + // Load Bypass + + + tri_rlmreg_p #(.INIT(0), .WIDTH(132), .NEEDS_SRESET(0)) ldwt_lat( + .nclk(nclk), + .act(tihi), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkrb[7]), //todo, break out into ex7, ex8 + .mpw1_b(mpw1_bb[7]), + .mpw2_b(mpw2_b[1]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(ldwt_lat_si[0:131]), + .scout(ldwt_lat_so[0:131]), + //------------------------------------------- + .din({ ex6_load_data_byp[0:65], + ex7_load_data_byp[0:65] }), + //------------------------------------------- + .dout({ex7_load_data_byp[0:65], + ex8_load_data_byp[0:65] }) + ); + //------------------------------------------- + tri_rlmreg_p #(.INIT(0), .WIDTH(132), .NEEDS_SRESET(0)) reldwt_lat( + .nclk(nclk), + .act(tihi), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkrb[7]), + .mpw1_b(mpw1_bb[7]), + .mpw2_b(mpw2_b[1]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(reldwt_lat_si[0:131]), + .scout(reldwt_lat_so[0:131]), + //------------------------------------------- + .din({ ex6_reload_data_byp[0:65], + ex7_reload_data_byp[0:65] }), + //------------------------------------------- + .dout({ex7_reload_data_byp[0:65], + ex8_reload_data_byp[0:65] }) + ); + //------------------------------------------- + + assign ex6_reload_data_byp = ex6_reload_data[0:65]; + + assign ex6_load_data_byp = ex6_load_data[0:65]; + + + assign f_fpr_ex6_load_sign = ex6_load_data_byp[0]; + assign f_fpr_ex6_load_expo[3:13] = ex6_load_data_byp[2:12]; + assign f_fpr_ex6_load_frac[0:52] = ex6_load_data_byp[13:65]; + + // Latched Write Ports for bypass + assign f_fpr_ex7_load_sign = ex7_load_data_byp[0]; + assign f_fpr_ex7_load_expo[3:13] = ex7_load_data_byp[2:12]; + assign f_fpr_ex7_load_frac[0:52] = ex7_load_data_byp[13:65]; + + assign f_fpr_ex8_load_sign = ex8_load_data_byp[0]; + assign f_fpr_ex8_load_expo[3:13] = ex8_load_data_byp[2:12]; + assign f_fpr_ex8_load_frac[0:52] = ex8_load_data_byp[13:65]; + +// reload + + assign f_fpr_ex6_reload_sign = ex6_reload_data_byp[0]; + assign f_fpr_ex6_reload_expo[3:13] = ex6_reload_data_byp[2:12]; + assign f_fpr_ex6_reload_frac[0:52] = ex6_reload_data_byp[13:65]; + + // Latched Write Ports for bypass + assign f_fpr_ex7_reload_sign = ex7_reload_data_byp[0]; + assign f_fpr_ex7_reload_expo[3:13] = ex7_reload_data_byp[2:12]; + assign f_fpr_ex7_reload_frac[0:52] = ex7_reload_data_byp[13:65]; + + assign f_fpr_ex8_reload_sign = ex8_reload_data_byp[0]; + assign f_fpr_ex8_reload_expo[3:13] = ex8_reload_data_byp[2:12]; + assign f_fpr_ex8_reload_frac[0:52] = ex8_reload_data_byp[13:65]; + + + // Target Bypass + + tri_rlmreg_p #(.INIT(0), .WIDTH(134), .NEEDS_SRESET(0)) tgwt_lat( + .nclk(nclk), + .act(tihi), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkrb[7]),// todo, need 8,9? + .mpw1_b(mpw1_bb[7]), + .mpw2_b(mpw2_b[1]), + .thold_b(thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(tgwt_lat_si[0:133]), + .scout(tgwt_lat_so[0:133]), + //------------------------------------------- + .din({ex7_frt_data[0:66], + ex8_frt_data[0:66] }), + //------------------------------------------- + .dout({ex8_frt_data[0:66], + ex9_frt_data[0:66] }) + ); + //------------------------------------------- + + assign ex7_frt_data[0] = f_rnd_ex7_res_sign; + assign ex7_frt_data[1:13] = f_rnd_ex7_res_expo[1:13]; + assign ex7_frt_data[14:66] = f_rnd_ex7_res_frac[0:52]; + + assign f_fpr_ex8_frt_sign = ex8_frt_data[0]; + assign f_fpr_ex8_frt_expo[1:13] = ex8_frt_data[1:13]; + assign f_fpr_ex8_frt_frac[0:52] = ex8_frt_data[14:66]; + + assign f_fpr_ex9_frt_sign = ex9_frt_data[0]; + assign f_fpr_ex9_frt_expo[1:13] = ex9_frt_data[1:13]; + assign f_fpr_ex9_frt_frac[0:52] = ex9_frt_data[14:66]; + + //---------------------------------------------------------------------- + // Scan Chains + + assign ex7_ldat_si[0:63] = {ex7_ldat_so[1:63], f_fpr_si}; + assign ex7_rldat_si[0:63] = {ex7_rldat_so[1:63], ex7_ldat_so[0]}; + + assign ex7_ldv_si[0:1] = {ex7_ldv_so[1], ex7_rldat_so[0]}; + assign ex7_lctl_si[0:11] = {ex7_lctl_so[1:11], ex7_ldv_so[0]}; + assign ex7_rlctl_si[0:9] = {ex7_rlctl_so[1:9], ex7_lctl_so[0]}; + + assign ex6_lctl_si[0:4] = {ex6_lctl_so[1:4], ex7_rlctl_so[0]}; + assign ex1_par_si[0:33] = {ex1_par_so[1:33], ex6_lctl_so[0]}; + assign ldwt_lat_si[0:131] = {ldwt_lat_so[1:131], ex1_par_so[0]}; + assign reldwt_lat_si[0:131] = {reldwt_lat_so[1:131],ldwt_lat_so[0] }; + assign tgwt_lat_si[0:133] = {tgwt_lat_so[1:133], reldwt_lat_so[0]}; + + + + assign f_fpr_so = tgwt_lat_so[0]; + + + assign scan_in_0 = f_fpr_ab_si; + assign scan_in_1 = scan_out_0; + + assign ab_reg_si[0:52] = {ab_reg_so[1:52], scan_out_1}; + assign f_fpr_ab_so = ab_reg_so[0]; + + //---------------------------------------------------------------------- + // Unused + + assign spare_unused[2:4] = iu_fu_rf0_ldst_tag[0:2]; + assign spare_unused[5:7] = rf1_fra[8:10]; + assign spare_unused[8:10] = rf1_frb[8:10]; + assign spare_unused[11:13] = rf1_frc[8:10]; + assign spare_unused[14:16] = rf1_frs[8:10]; + + assign spare_unused[17:18] = abist_raddr_0[0:1]; + assign spare_unused[19:20] = abist_raddr_1[0:1]; + assign spare_unused[21:22] = abist_waddr_0[0:1]; + assign spare_unused[23:24] = abist_waddr_1[0:1]; + assign spare_unused[25] = lcb_mpw1_dc_b[0]; + +endmodule diff --git a/dev/verilog/work/fu_gst.v b/dev/verilog/work/fu_gst.v new file mode 100755 index 0000000..9a154b7 --- /dev/null +++ b/dev/verilog/work/fu_gst.v @@ -0,0 +1,1382 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//==########################################################################## +//==### FU_GST.VHDL ######### +//==### side pipe for graphics estimates ######### +//==### flogefp, fexptefp ######### +//==### ######### +//==########################################################################## + +module fu_gst( + vdd, + gnd, + clkoff_b, + act_dis, + flush, + delay_lclkr, + mpw1_b, + mpw2_b, + sg_1, + thold_1, + fpu_enable, + nclk, + f_gst_si, + f_gst_so, + ex1_act, + f_fmt_ex2_b_sign_gst, + f_fmt_ex2_b_expo_gst_b, + f_fmt_ex2_b_frac_gst, + f_pic_ex2_floges, + f_pic_ex2_fexptes, + f_gst_ex6_logexp_v, + f_gst_ex6_logexp_sign, + f_gst_ex6_logexp_exp, + f_gst_ex6_logexp_fract +); + `include "tri_a2o.vh" + + inout vdd; + inout gnd; + + input clkoff_b; // tiup + input act_dis; // ??tidn?? + input flush; // ??tidn?? + input [2:5] delay_lclkr; // tidn, + input [2:5] mpw1_b; // tidn, + input [0:1] mpw2_b; // tidn, + input sg_1; + input thold_1; + input fpu_enable; //dc_act + input [0:`NCLK_WIDTH-1] nclk; + //-------------------------------------------------------------------------- + // + input f_gst_si; //perv scan + output f_gst_so; //perv scan + + input ex1_act; + //-------------------------------------------------------------------------- + input f_fmt_ex2_b_sign_gst; + input [01:13] f_fmt_ex2_b_expo_gst_b; + input [01:19] f_fmt_ex2_b_frac_gst; + //-------------------------------------------------------------------------- + input f_pic_ex2_floges; + input f_pic_ex2_fexptes; + //-------------------------------------------------------------------------- + output f_gst_ex6_logexp_v; + output f_gst_ex6_logexp_sign; // needs to be right off of a latch + output [01:11] f_gst_ex6_logexp_exp; // needs to be right off of a latch + output [00:19] f_gst_ex6_logexp_fract; // needs to be right off of a latch + //-------------------------------------------------------------------------- + + //==################################################ + + parameter tiup = 1'b1; + parameter tidn = 1'b0; + + wire sg_0; + wire thold_0_b; + wire thold_0; + wire force_t; + + //---------------------------------------------------------------------- + + wire [0:1] ex3_gst_ctrl_lat_scout; + wire [0:1] ex3_gst_ctrl_lat_scin; + wire [0:1] ex4_gst_ctrl_lat_scout; + wire [0:1] ex4_gst_ctrl_lat_scin; + wire [0:3] ex5_gst_ctrl_lat_scout; + wire [0:3] ex5_gst_ctrl_lat_scin; + wire [0:1] ex6_gst_ctrl_lat_scout; + wire [0:1] ex6_gst_ctrl_lat_scin; + wire [0:32] ex3_gst_stage_lat_scout; + wire [0:32] ex3_gst_stage_lat_scin; + wire [0:19] ex4_gst_stage_lat_scout; + wire [0:19] ex4_gst_stage_lat_scin; + wire [0:23] ex5_gst_stage_lat_scout; + wire [0:23] ex5_gst_stage_lat_scin; + wire [0:31] ex6_gst_stage_lat_scout; + wire [0:31] ex6_gst_stage_lat_scin; + + wire [1:11] ex5_log_dp_bias; + wire ex5_logof1_specialcase; + wire ex4_logof1_specialcase; + + wire ex5_signbit_din; + wire ex6_signbit; + wire ex5_log_signbit; + + wire f1; + wire f2; + wire f3; + wire f4; + wire f5; + wire f6; + wire f7; + wire f8; + wire f9; + wire f10; + + wire s1; + wire s2; + wire s3; + wire c4; + wire c5; + wire c6; + wire c7; + wire a4; + wire a5; + wire a6; + wire a7; + wire a8; + wire a9; + wire a10; + wire a11; + + wire [1:11] ex3_f; + wire [4:11] ex3_a; + wire [4:11] ex3_c; + + wire [4:7] ex3_log_fsum; + wire [3:6] ex3_log_fcarryin; + + wire ex3_b_sign; + wire [1:13] ex3_b_biased_13exp; + wire [1:11] ex3_b_biased_11exp; + + wire [1:11] ex3_b_ubexp_sum; + wire [2:11] ex3_b_ubexp_cout; + wire [1:11] ex3_b_ubexp; + + wire [1:19] ex3_b_fract; + + wire [1:13] f_fmt_ex2_b_expo_gst; + + wire ex2_floges; + wire ex2_fexptes; + wire ex3_floges; + wire ex3_fexptes; + wire ex4_floges; + wire ex4_fexptes; + wire ex5_floges; + wire ex5_fexptes; + wire ex6_floges; + wire ex6_fexptes; + + wire [1:11] ex3_log_a_addend_b; + wire [1:11] ex3_log_b_addend_b; + + wire [1:19] ex4_mantissa; + wire [1:19] ex5_mantissa; + wire [1:19] ex4_mantissa_precomp; + wire [1:19] ex4_mantissa_precomp_b; + wire [1:19] ex3_log_mantissa_precomp; + wire [1:19] ex4_mantissa_neg; + wire [1:19] ex3_mantissa_din; + wire [0:4] ex3_shamt; + wire [0:4] ex4_shamt; + wire [0:4] ex5_shamt; + wire ex4_negate; + wire ex5_negate; + wire ex4_b_sign; + + wire [00:19] ex3_mantissa_shlev0; + wire [00:22] ex3_mantissa_shlev1; // 0 to 3 + wire [00:34] ex3_mantissa_shlev2; // 0 to 12 + wire [00:50] ex3_mantissa_shlev3; // 0 to 16 + + wire [1:8] ex3_pow_int; + wire [1:11] ex3_pow_frac; + + wire [01:19] ex5_mantissa_shlev0; + wire [01:22] ex5_mantissa_shlev1; // 0 to 3 + wire [01:34] ex5_mantissa_shlev2; // 0 to 12 + wire [01:50] ex5_mantissa_shlev3; // 0 to 16 + + wire [01:11] ex5_exponent_a_addend_b; + wire [01:11] ex5_exponent_b_addend_b; + + wire [01:11] ex5_log_a_addend_b; + wire [01:11] ex5_log_b_addend_b; + wire [01:11] ex5_pow_a_addend_b; + wire [01:11] ex5_pow_b_addend_b; + + wire [01:11] ex5_biased_exponent_result; + wire [01:11] ex6_biased_exponent_result; + + wire [01:19] ex5_log_mantissa_postsh; + wire [01:19] ex5_log_fract; + wire [01:11] ex5_pow_fract; + wire [01:11] ex5_pow_fract_b; + wire [00:19] ex5_fract_din; + wire [00:19] ex6_fract; + + wire l1_enc00; + wire l1_enc01; + wire l1_enc10; + wire l1_enc11; + wire l2_enc00; + wire l2_enc01; + wire l2_enc10; + wire l2_enc11; + wire l3_enc00; + wire l3_enc01; + wire l1_e00; + wire l1_e01; + wire l1_e10; + wire l1_e11; + wire l2_e00; + wire l2_e01; + wire l2_e10; + wire l2_e11; + wire l3_e00; + wire l3_e01; + + wire [01:11] ex5_f; + wire [01:11] ex5_f_b; + + //---------------------------------------------------------------------- + wire eb1; //, eb11 + wire eb2; + wire eb3; + wire eb4; + wire eb5; + wire eb6; + wire eb7; + wire eb8; + wire eb9; + wire eb10; + + wire ea4; + wire ea5; + wire ea6; + wire ea7; + wire ea8; + wire ea9; + wire ea10; + wire ea11; + wire ec4; + wire ec5; + wire ec6; + wire ec7; + wire es1; + wire es2; + wire es3; + wire [4:11] ex5_ea; + wire [4:11] ex5_ec; + + wire [1:11] ex5_addend1; + wire [1:11] ex5_addend2; + wire [1:11] ex5_addend3; + wire [1:11] ex5_fsum; + wire [1:11] ex5_fcarryin; + wire [1:11] ex5_powf_a_addend_b; + wire [1:11] ex5_powf_b_addend_b; + + wire [01:16] zeros; + wire ex3_powsh_no_sat_lft; + wire ex3_powsh_no_sat_rgt; + + + wire ex2_act; + wire ex3_act; + wire ex4_act; + wire ex5_act; + wire [0:7] act_so; + wire [0:7] act_si; + + (* analysis_not_referenced="TRUE" *) + wire [0:3] act_spare_unused; + + (* analysis_not_referenced="TRUE" *) + wire unused; + + wire [2:11] ex3_ube_g2_b; + wire [2:11] ex3_ube_g4; + wire [2:11] ex3_ube_g8_b; + wire s2_0; + wire s2_1; + wire s3_0; + wire s3_1; + wire sx; + + wire s7_if_s1; + wire s7_if_s20; + wire s7_if_s30; + wire s7_if_sx; + wire s7_if_s31; + wire s7_if_s21; + wire c6_if_s1; + wire c6_if_s20; + wire c6_if_s30; + wire c6_if_sx; + wire c6_if_s31; + wire c6_if_s21; + + wire s6_if_s1; + wire s6_if_s20; + wire s6_if_s30; + wire s6_if_sx; + wire s6_if_s31; + wire s6_if_s21; + wire c5_if_s1; + wire c5_if_s20; + wire c5_if_s30; + wire c5_if_sx; + wire c5_if_s31; + wire c5_if_s21; + + wire s5_if_s1; + wire s5_if_s20; + wire s5_if_s30; + wire s5_if_sx; + wire s5_if_s31; + wire s5_if_s21; + wire c4_if_s1; + wire c4_if_s20; + wire c4_if_s30; + wire c4_if_sx; + wire c4_if_s31; + wire c4_if_s21; + + wire s4_if_s1; + wire s4_if_s20; + wire s4_if_s30; + wire s4_if_sx; + wire s4_if_s31; + wire s4_if_s21; + wire c3_if_s1; + wire c3_if_s20; + wire c3_if_s30; + wire c3_if_sx; + wire c3_if_s31; + wire c3_if_s21; + + wire es4_if_s1; + wire es4_if_s20; + wire es4_if_s30; + wire es4_if_sx; + wire es4_if_s31; + wire es4_if_s21; + wire ec3_if_s1; + wire ec3_if_s20; + wire ec3_if_s30; + wire ec3_if_sx; + wire ec3_if_s31; + wire ec3_if_s21; + + wire es5_if_s1; + wire es5_if_s20; + wire es5_if_s30; + wire es5_if_sx; + wire es5_if_s31; + wire es5_if_s21; + wire ec4_if_s1; + wire ec4_if_s20; + wire ec4_if_s30; + wire ec4_if_sx; + wire ec4_if_s31; + wire ec4_if_s21; + + wire es6_if_s1; + wire es6_if_s20; + wire es6_if_s30; + wire es6_if_sx; + wire es6_if_s31; + wire es6_if_s21; + wire ec5_if_s1; + wire ec5_if_s20; + wire ec5_if_s30; + wire ec5_if_sx; + wire ec5_if_s31; + wire ec5_if_s21; + + wire es7_if_s1; + wire es7_if_s20; + wire es7_if_s30; + wire es7_if_sx; + wire es7_if_s31; + wire es7_if_s21; + wire ec6_if_s1; + wire ec6_if_s20; + wire ec6_if_s30; + wire ec6_if_sx; + wire ec6_if_s31; + wire ec6_if_s21; + wire es2_0; + wire es2_1; + wire esx; + wire es3_0; + wire es3_1; + + //==########################################## + //# pervasive + //==########################################## + + assign unused = ex3_b_biased_13exp[1] | ex3_b_biased_13exp[2] | ex3_b_ubexp[2] | ex3_b_ubexp[3] | +ex3_mantissa_shlev3[0] | ex3_mantissa_shlev3[1] | ex3_mantissa_shlev3[2] | ex3_mantissa_shlev3[3] | +ex3_mantissa_shlev3[4] | ex3_mantissa_shlev3[5] | ex3_mantissa_shlev3[6] | ex3_mantissa_shlev3[7] | +ex3_mantissa_shlev3[27] | ex3_mantissa_shlev3[28] | ex3_mantissa_shlev3[29] | ex3_mantissa_shlev3[30] | +ex3_mantissa_shlev3[31] | ex3_mantissa_shlev3[32] | ex3_mantissa_shlev3[33] | ex3_mantissa_shlev3[34] | +ex3_mantissa_shlev3[35] | ex3_mantissa_shlev3[36] | ex3_mantissa_shlev3[37] | ex3_mantissa_shlev3[38] | +ex3_mantissa_shlev3[39] | ex3_mantissa_shlev3[40] | ex3_mantissa_shlev3[41] | ex3_mantissa_shlev3[42] | +ex3_mantissa_shlev3[43] | ex3_mantissa_shlev3[44] | ex3_mantissa_shlev3[45] | ex3_mantissa_shlev3[46] | +ex3_mantissa_shlev3[47] | ex3_mantissa_shlev3[48] | ex3_mantissa_shlev3[49] | ex3_mantissa_shlev3[50] | +|(ex5_mantissa_shlev3[1:31]) | + |( ex3_a[4:7] ) | + |( ex3_c[4:11] ) | + |( ex5_addend1[1:11] ) | + |( ex5_addend2[1:11] ) | + |( ex5_addend3[1:11] ) | + s2 | + s3 | + es2 | + es3 ; + + + tri_plat thold_reg_0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(flush), + .din(thold_1), + .q(thold_0) + ); + + + tri_plat sg_reg_0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(flush), + .din(sg_1), + .q(sg_0) + ); + + + tri_lcbor lcbor_0( + .clkoff_b(clkoff_b), + .thold(thold_0), + .sg(sg_0), + .act_dis(act_dis), + .force_t(force_t), + .thold_b(thold_0_b) + ); + + //==########################################## + + + + tri_rlmreg_p #(.WIDTH(8), .NEEDS_SRESET(0)) act_lat( + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[4]), + .mpw1_b(mpw1_b[4]), + .mpw2_b(mpw2_b[0]), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(fpu_enable), + .thold_b(thold_0_b), + .sg(sg_0), + .scout(act_so), + .scin(act_si), + //----------------- + .din({act_spare_unused[0], + act_spare_unused[1], + ex1_act, + ex2_act, + ex3_act, + ex4_act, + act_spare_unused[2], + act_spare_unused[3]}), + //----------------- + .dout({act_spare_unused[0], + act_spare_unused[1], + ex2_act, + ex3_act, + ex4_act, + ex5_act, + act_spare_unused[2], + act_spare_unused[3]}) + ); + + //==########################################## + + assign zeros = {16{tidn}}; + + assign ex2_floges = f_pic_ex2_floges; + assign ex2_fexptes = f_pic_ex2_fexptes; + + //--------------------------------------------------------------------- + + tri_rlmreg_p #( .WIDTH(2), .NEEDS_SRESET(0)) ex3_gst_ctrl_lat( + .force_t(force_t), //d_mode => tiup, delay_lclkr => tidn, + .d_mode(tiup), + .delay_lclkr(delay_lclkr[2]), + .mpw1_b(mpw1_b[2]), + .mpw2_b(mpw2_b[0]), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + //----------------- + .act(ex2_act), + //----------------- + .scout(ex3_gst_ctrl_lat_scout), + .scin(ex3_gst_ctrl_lat_scin), + //----------------- + .din({ex2_floges, + ex2_fexptes}), + //----------------- + .dout({ex3_floges, + ex3_fexptes}) + ); + //--------------------------------------------------------------------- + + //---------------------------------------------------------------------- + //---------------------------------------------------------------------- + + assign f_fmt_ex2_b_expo_gst = (~f_fmt_ex2_b_expo_gst_b); + + //--------------------------------------------------------------------- + + tri_rlmreg_p #( .WIDTH(33), .NEEDS_SRESET(0)) ex3_gst_stage_lat( + .force_t(force_t), //d_mode => tiup, delay_lclkr => tidn, + .d_mode(tiup), + .delay_lclkr(delay_lclkr[2]), + .mpw1_b(mpw1_b[2]), + .mpw2_b(mpw2_b[0]), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + //----------------- + .act(ex2_act), + //----------------- + .scout(ex3_gst_stage_lat_scout), + .scin(ex3_gst_stage_lat_scin), + //----------------- + .din({f_fmt_ex2_b_sign_gst, + f_fmt_ex2_b_expo_gst, + f_fmt_ex2_b_frac_gst}), + + //----------------- + .dout({ex3_b_sign, + ex3_b_biased_13exp, + ex3_b_fract}) + ); + + //****************************************************************************** + //* LOG ESTIMATE CALCULATION, FRACTIONAL PORTION + //****************************************************************************** + + assign ex3_f[1:11] = ex3_b_fract[1:11]; + + assign f1 = ex3_f[1]; + assign f2 = ex3_f[2]; + assign f3 = ex3_f[3]; + assign f4 = ex3_f[4]; + assign f5 = ex3_f[5]; + assign f6 = ex3_f[6]; + assign f7 = ex3_f[7]; + assign f8 = ex3_f[8]; + assign f9 = ex3_f[9]; + assign f10 = ex3_f[10]; + + assign s1 = ((~f1) & (~f2) & (~f3) & (~f4)); //0 + //1 + assign s2_0 = ((~f1) & (~f2) & (~f3) & f4) | ((~f1) & (~f2) & f3 & (~f4)); //2 + //3 + assign s3_0 = ((~f1) & (~f2) & f3 & f4) | ((~f1) & f2 & (~f3)); //4,5 + //6,7 + assign sx = ((~f1) & f2 & f3) | (f1 & (~f2) & (~f3) & (~f4)); //8 + //9 + assign s3_1 = (f1 & (~f2) & (~f3) & f4) | (f1 & (~f2) & f3); //10,11 + assign s2_1 = (f1 & f2); //12,13,14,15 + + assign s2 = s2_0 | s2_1; + assign s3 = s3_0 | s3_1; + + //------------------------------------------------------------------------------ + + assign c4 = sx; + assign c5 = s3_0 | s3_1; + assign c6 = sx | s2_0; + assign c7 = sx | s3_0; + + assign a4 = (s1 & f3) | (s2_0 & f2) | (s2_1 & (~f2)); + + assign a5 = (s1 & f4) | (s2_0 & f3) | (s2_1 & (~f3)) | (s3_0 & f2) | (s3_1 & (~f2)); + + assign a6 = (s1 & f5) | (s2_0 & f4) | (s2_1 & (~f4)) | (s3_0 & f3) | (s3_1 & (~f3)); + + assign a7 = (s1 & f6) | (s2_0 & f5) | (s2_1 & (~f5)) | (s3_0 & f4) | (s3_1 & (~f4)); + + assign a8 = (s1 & f7) | (s2_0 & f6) | (s2_1 & (~f6)) | (s3_0 & f5) | (s3_1 & (~f5)); + + assign a9 = (s1 & f8) | (s2_0 & f7) | (s2_1 & (~f7)) | (s3_0 & f6) | (s3_1 & (~f6)); + + assign a10 = (s1 & f9) | (s2_0 & f8) | (s2_1 & (~f8)) | (s3_0 & f7) | (s3_1 & (~f7)); + + assign a11 = (s1 & f10) | (s2_0 & f9) | (s2_1 & (~f9)) | (s3_0 & f8) | (s3_1 & (~f8)); + + //------------------------------------------------------------------------------ + + assign ex3_a[4:11] = {a4, a5, a6, a7, a8, a9, a10, a11}; + assign ex3_c[4:11] = {c4, c5, c6, c7, tidn, tidn, tidn, tidn}; + + //------------------------------------------------------------------------------ + // 3 to 2 compressor + //------------------------------------------------------------------------------ + + assign c3_if_s1 = f4 & f3; + assign c3_if_s20 = f4 & f2; + assign c3_if_s30 = tidn; + assign c3_if_sx = f4; + assign c3_if_s31 = tidn; + assign c3_if_s21 = f4 & (~f2); + + assign s4_if_s1 = f4 ^ f3; + assign s4_if_s20 = f4 ^ f2; + assign s4_if_s30 = f4; + assign s4_if_sx = (~f4); + assign s4_if_s31 = f4; + assign s4_if_s21 = f4 ^ (~f2); + + assign c4_if_s1 = f5 & f4; + assign c4_if_s20 = f5 & f3; + assign c4_if_s30 = f5 | f2; + assign c4_if_sx = tidn; + assign c4_if_s31 = f5 | (~f2); + assign c4_if_s21 = f5 & (~f3); + + assign s5_if_s1 = f5 ^ f4; + assign s5_if_s20 = f5 ^ f3; + assign s5_if_s30 = f5 ^ (~f2); + assign s5_if_sx = f5; + assign s5_if_s31 = f5 ^ f2; + assign s5_if_s21 = f5 ^ (~f3); + + assign c5_if_s1 = f6 & f5; + assign c5_if_s20 = f6 | f4; + assign c5_if_s30 = f6 & f3; + assign c5_if_sx = f6; + assign c5_if_s31 = f6 & (~f3); + assign c5_if_s21 = f6 & (~f4); + + assign s6_if_s1 = f6 ^ f5; + assign s6_if_s20 = f6 ^ (~f4); + assign s6_if_s30 = f6 ^ f3; + assign s6_if_sx = (~f6); + assign s6_if_s31 = f6 ^ (~f3); + assign s6_if_s21 = f6 ^ (~f4); + + assign c6_if_s1 = f7 & f6; + assign c6_if_s20 = f7 & f5; + assign c6_if_s30 = f7 | f4; + assign c6_if_sx = f7; + assign c6_if_s31 = f7 & (~f4); + assign c6_if_s21 = f7 & (~f5); + + assign s7_if_s1 = f7 ^ f6; + assign s7_if_s20 = f7 ^ f5; + assign s7_if_s30 = f7 ^ (~f4); + assign s7_if_sx = (~f7); + assign s7_if_s31 = f7 ^ (~f4); + assign s7_if_s21 = f7 ^ (~f5); + + assign ex3_log_fsum[4] = (s1 & s4_if_s1) | (s2_0 & s4_if_s20) | (s3_0 & s4_if_s30) | (sx & s4_if_sx) | (s3_1 & s4_if_s31) | (s2_1 & s4_if_s21); + + assign ex3_log_fcarryin[3] = (s1 & c3_if_s1) | (s2_0 & c3_if_s20) | (s3_0 & c3_if_s30) | (sx & c3_if_sx) | (s3_1 & c3_if_s31) | (s2_1 & c3_if_s21); + + assign ex3_log_fsum[5] = (s1 & s5_if_s1) | (s2_0 & s5_if_s20) | (s3_0 & s5_if_s30) | (sx & s5_if_sx) | (s3_1 & s5_if_s31) | (s2_1 & s5_if_s21); + + assign ex3_log_fcarryin[4] = (s1 & c4_if_s1) | (s2_0 & c4_if_s20) | (s3_0 & c4_if_s30) | (sx & c4_if_sx) | (s3_1 & c4_if_s31) | (s2_1 & c4_if_s21); + + assign ex3_log_fsum[6] = (s1 & s6_if_s1) | (s2_0 & s6_if_s20) | (s3_0 & s6_if_s30) | (sx & s6_if_sx) | (s3_1 & s6_if_s31) | (s2_1 & s6_if_s21); + + assign ex3_log_fcarryin[5] = (s1 & c5_if_s1) | (s2_0 & c5_if_s20) | (s3_0 & c5_if_s30) | (sx & c5_if_sx) | (s3_1 & c5_if_s31) | (s2_1 & c5_if_s21); + + assign ex3_log_fsum[7] = (s1 & s7_if_s1) | (s2_0 & s7_if_s20) | (s3_0 & s7_if_s30) | (sx & s7_if_sx) | (s3_1 & s7_if_s31) | (s2_1 & s7_if_s21); + + assign ex3_log_fcarryin[6] = (s1 & c6_if_s1) | (s2_0 & c6_if_s20) | (s3_0 & c6_if_s30) | (sx & c6_if_sx) | (s3_1 & c6_if_s31) | (s2_1 & c6_if_s21); + + assign ex3_log_a_addend_b[1] = (~(ex3_f[1])); + assign ex3_log_a_addend_b[2] = (~(ex3_f[2])); + assign ex3_log_a_addend_b[3] = (~(ex3_f[3])); + assign ex3_log_a_addend_b[4] = (~(ex3_log_fsum[4])); + assign ex3_log_a_addend_b[5] = (~(ex3_log_fsum[5])); + assign ex3_log_a_addend_b[6] = (~(ex3_log_fsum[6])); + assign ex3_log_a_addend_b[7] = (~(ex3_log_fsum[7])); + assign ex3_log_a_addend_b[8] = (~(ex3_f[8])); + assign ex3_log_a_addend_b[9] = (~(ex3_f[9])); + assign ex3_log_a_addend_b[10] = (~(ex3_f[10])); + assign ex3_log_a_addend_b[11] = (~(ex3_f[11])); + + assign ex3_log_b_addend_b[1] = (~(tidn)); + assign ex3_log_b_addend_b[2] = (~(tidn)); + assign ex3_log_b_addend_b[3] = (~(ex3_log_fcarryin[3])); + assign ex3_log_b_addend_b[4] = (~(ex3_log_fcarryin[4])); + assign ex3_log_b_addend_b[5] = (~(ex3_log_fcarryin[5])); + assign ex3_log_b_addend_b[6] = (~(ex3_log_fcarryin[6])); + assign ex3_log_b_addend_b[7] = (~(tidn)); + assign ex3_log_b_addend_b[8] = (~(ex3_a[8])); + assign ex3_log_b_addend_b[9] = (~(ex3_a[9])); + assign ex3_log_b_addend_b[10] = (~(ex3_a[10])); + assign ex3_log_b_addend_b[11] = (~(ex3_a[11])); + + //------------------------------------------------------------------------------ + // unbias the exponent + //------------------------------------------------------------------------------ + // bias is DP, so subtract 1023 + + assign ex3_b_biased_11exp[1:11] = ex3_b_biased_13exp[3:13]; + + // add -1023 (10000000001) + + assign ex3_b_ubexp_sum[01] = (~ex3_b_biased_11exp[01]); + assign ex3_b_ubexp_sum[02:10] = ex3_b_biased_11exp[02:10]; + assign ex3_b_ubexp_sum[11] = (~ex3_b_biased_11exp[11]); + + assign ex3_ube_g2_b[11] = (~(ex3_b_biased_11exp[11])); + assign ex3_ube_g2_b[10] = (~(ex3_b_biased_11exp[10] & ex3_b_biased_11exp[11])); + assign ex3_ube_g2_b[9] = (~(ex3_b_biased_11exp[9] & ex3_b_biased_11exp[10])); + assign ex3_ube_g2_b[8] = (~(ex3_b_biased_11exp[8] & ex3_b_biased_11exp[9])); + assign ex3_ube_g2_b[7] = (~(ex3_b_biased_11exp[7] & ex3_b_biased_11exp[8])); + assign ex3_ube_g2_b[6] = (~(ex3_b_biased_11exp[6] & ex3_b_biased_11exp[7])); + assign ex3_ube_g2_b[5] = (~(ex3_b_biased_11exp[5] & ex3_b_biased_11exp[6])); + assign ex3_ube_g2_b[4] = (~(ex3_b_biased_11exp[4] & ex3_b_biased_11exp[5])); + assign ex3_ube_g2_b[3] = (~(ex3_b_biased_11exp[3] & ex3_b_biased_11exp[4])); + assign ex3_ube_g2_b[2] = (~(ex3_b_biased_11exp[2] & ex3_b_biased_11exp[3])); + + assign ex3_ube_g4[11] = (~(ex3_ube_g2_b[11])); + assign ex3_ube_g4[10] = (~(ex3_ube_g2_b[10])); + assign ex3_ube_g4[9] = (~(ex3_ube_g2_b[9] | ex3_ube_g2_b[11])); + assign ex3_ube_g4[8] = (~(ex3_ube_g2_b[8] | ex3_ube_g2_b[10])); + assign ex3_ube_g4[7] = (~(ex3_ube_g2_b[7] | ex3_ube_g2_b[9])); + assign ex3_ube_g4[6] = (~(ex3_ube_g2_b[6] | ex3_ube_g2_b[8])); + assign ex3_ube_g4[5] = (~(ex3_ube_g2_b[5] | ex3_ube_g2_b[7])); + assign ex3_ube_g4[4] = (~(ex3_ube_g2_b[4] | ex3_ube_g2_b[6])); + assign ex3_ube_g4[3] = (~(ex3_ube_g2_b[3] | ex3_ube_g2_b[5])); + assign ex3_ube_g4[2] = (~(ex3_ube_g2_b[2] | ex3_ube_g2_b[4])); + + assign ex3_ube_g8_b[11] = (~(ex3_ube_g4[11])); + assign ex3_ube_g8_b[10] = (~(ex3_ube_g4[10])); + assign ex3_ube_g8_b[9] = (~(ex3_ube_g4[9])); + assign ex3_ube_g8_b[8] = (~(ex3_ube_g4[8])); + assign ex3_ube_g8_b[7] = (~(ex3_ube_g4[7] & ex3_ube_g4[11])); + assign ex3_ube_g8_b[6] = (~(ex3_ube_g4[6] & ex3_ube_g4[10])); + assign ex3_ube_g8_b[5] = (~(ex3_ube_g4[5] & ex3_ube_g4[9])); + assign ex3_ube_g8_b[4] = (~(ex3_ube_g4[4] & ex3_ube_g4[8])); + assign ex3_ube_g8_b[3] = (~(ex3_ube_g4[3] & ex3_ube_g4[7])); + assign ex3_ube_g8_b[2] = (~(ex3_ube_g4[2] & ex3_ube_g4[6])); + + assign ex3_b_ubexp_cout[11] = (~(ex3_ube_g8_b[11])); + assign ex3_b_ubexp_cout[10] = (~(ex3_ube_g8_b[10])); + assign ex3_b_ubexp_cout[9] = (~(ex3_ube_g8_b[9])); + assign ex3_b_ubexp_cout[8] = (~(ex3_ube_g8_b[8])); + assign ex3_b_ubexp_cout[7] = (~(ex3_ube_g8_b[7])); + assign ex3_b_ubexp_cout[6] = (~(ex3_ube_g8_b[6])); + assign ex3_b_ubexp_cout[5] = (~(ex3_ube_g8_b[5])); + assign ex3_b_ubexp_cout[4] = (~(ex3_ube_g8_b[4])); + assign ex3_b_ubexp_cout[3] = (~(ex3_ube_g8_b[3] | ex3_ube_g8_b[11])); + assign ex3_b_ubexp_cout[2] = (~(ex3_ube_g8_b[2] | ex3_ube_g8_b[10])); + + assign ex3_b_ubexp[01:10] = ex3_b_ubexp_sum[01:10] ^ ex3_b_ubexp_cout[02:11]; + assign ex3_b_ubexp[11] = ex3_b_ubexp_sum[11]; + + //------------------------------------------------------------------------------ + + // not really an 11 bit adder + fu_gst_add11 ex3_logadd11( + .a_b(ex3_log_a_addend_b[1:11]), + .b_b(ex3_log_b_addend_b[1:11]), + //------------------------------------------------------ + .s0(ex3_log_mantissa_precomp[9:19]) + ); + //--------------------------------------------------------------------- + + assign ex3_log_mantissa_precomp[1:8] = ex3_b_ubexp[4:11]; + + //---------------------------------------------------------------------------------------------------------------------- + // for fexptes, shift mantissa based on the exponent (un-normalize) + + assign ex3_mantissa_shlev0[00:19] = {tiup, ex3_b_fract[01:19]}; + + assign ex3_shamt[0:4] = {ex3_b_ubexp[1], ex3_b_ubexp[08:11]}; + + //timing note: the shift amount comes after the adder to unbias the exponent. + // it would be faster to use the biased exponent but use the shift controls different. + // + // 1 2 3 4 5 6 7 8 9 A B + // 0 1 1 1 1 1 1 1 1 1 1 bias =1023 + // 1 0 0 0 0 0 0 0 0 0 1 add -1023 to unbias + // for small shifts unbiased 01 = biased 00 + // for small shifts unbiased 10 = biased 01 + // for small shifts unbiased 11 = biased 10 + // for small shifts unbiased 00 = biased 11 + + assign ex3_powsh_no_sat_lft = (~ex3_b_ubexp[2]) & (~ex3_b_ubexp[3]) & (~ex3_b_ubexp[4]) & (~ex3_b_ubexp[5]) & (~ex3_b_ubexp[6]) & (~ex3_b_ubexp[7]); + + assign ex3_powsh_no_sat_rgt = ex3_b_ubexp[2] & ex3_b_ubexp[3] & ex3_b_ubexp[4] & ex3_b_ubexp[5] & ex3_b_ubexp[6] & ex3_b_ubexp[7]; + + assign l1_e00 = (~ex3_shamt[3]) & (~ex3_shamt[4]); + assign l1_e01 = (~ex3_shamt[3]) & ex3_shamt[4]; + assign l1_e10 = ex3_shamt[3] & (~ex3_shamt[4]); + assign l1_e11 = ex3_shamt[3] & ex3_shamt[4]; + + assign l2_e00 = (~ex3_shamt[1]) & (~ex3_shamt[2]); + assign l2_e01 = (~ex3_shamt[1]) & ex3_shamt[2]; + assign l2_e10 = ex3_shamt[1] & (~ex3_shamt[2]); + assign l2_e11 = ex3_shamt[1] & ex3_shamt[2]; + + assign l3_e00 = (~ex3_shamt[0]) & ex3_powsh_no_sat_lft; + assign l3_e01 = ex3_shamt[0] & ex3_powsh_no_sat_rgt; // this means shift Right by 16 + + assign ex3_mantissa_shlev1[00:22] = ({zeros[01:03], (ex3_mantissa_shlev0[00:19])} & {23{l1_e00}}) | + ({zeros[01:02], ({ex3_mantissa_shlev0[00:19], zeros[01]})} & {23{l1_e01}}) | + ({zeros[01], ({ex3_mantissa_shlev0[00:19], zeros[01:02]})} & {23{l1_e10}}) | + (({ex3_mantissa_shlev0[00:19], zeros[01:03]}) & {23{l1_e11}}); + + assign ex3_mantissa_shlev2[00:34] = ({zeros[01:12], (ex3_mantissa_shlev1[00:22])} & {35{l2_e00}}) | + ({zeros[01:08], ({ex3_mantissa_shlev1[00:22], zeros[01:04]})} & {35{l2_e01}}) | + ({zeros[01:04], ({ex3_mantissa_shlev1[00:22], zeros[01:08]})} & {35{l2_e10}}) | + (({ex3_mantissa_shlev1[00:22], zeros[01:12]}) & {35{l2_e11}}); + + assign ex3_mantissa_shlev3[00:50] = (({ex3_mantissa_shlev2[00:34], zeros[01:16]}) & {51{l3_e00}}) | + ({zeros[01:16], (ex3_mantissa_shlev2[00:34])} & {51{l3_e01}}); + + assign ex3_pow_int[1:8] = ex3_mantissa_shlev3[08:15]; + assign ex3_pow_frac[1:11] = ex3_mantissa_shlev3[16:26]; + + assign ex3_mantissa_din[1:19] = (({ex3_pow_int[1:8], ex3_pow_frac[1:11]}) & {19{ex3_fexptes}}) | + (ex3_log_mantissa_precomp[1:19] & {19{ex3_floges}}); + + //--------------------------------------------------------------------- + //--------------------------------------------------------------------- + //--------------------------------------------------------------------- + //--------------------------------------------------------------------- + + tri_rlmreg_p #( .WIDTH(2), .NEEDS_SRESET(0)) ex4_gst_ctrl_lat( + .force_t(force_t), //d_mode => tiup, delay_lclkr => tidn, + .d_mode(tiup), + .delay_lclkr(delay_lclkr[3]), + .mpw1_b(mpw1_b[3]), + .mpw2_b(mpw2_b[0]), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + //----------------- + .act(ex3_act), + //----------------- + .scout(ex4_gst_ctrl_lat_scout), + .scin(ex4_gst_ctrl_lat_scin), + //----------------- + .din({ex3_floges, + ex3_fexptes}), + //----------------- + .dout({ex4_floges, + ex4_fexptes}) + ); + //--------------------------------------------------------------------- + + + tri_rlmreg_p #( .WIDTH(20), .NEEDS_SRESET(0)) ex4_gst_stage_lat( + .force_t(force_t), //d_mode => tiup, delay_lclkr => tidn, + .d_mode(tiup), + .delay_lclkr(delay_lclkr[3]), + .mpw1_b(mpw1_b[3]), + .mpw2_b(mpw2_b[0]), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + //----------------- + .act(ex3_act), + //----------------- + .scout(ex4_gst_stage_lat_scout), + .scin(ex4_gst_stage_lat_scin), + //----------------- + .din({ex3_mantissa_din, + ex3_b_sign}), + //----------------- + .dout({ex4_mantissa_precomp, + ex4_b_sign}) + ); + + //--------------------------------------------------------------------- + //--------------------------------------------------------------------- + //--------------------------------------------------------------------- + + assign ex4_mantissa_precomp_b = (~ex4_mantissa_precomp[1:19]); + + //--------------------------------------------------------------------- + + fu_gst_inc19 ex4_log_inc( + .a(ex4_mantissa_precomp_b[1:19]), + //------------------------------------------------------ + .o(ex4_mantissa_neg[1:19]) + ); + //--------------------------------------------------------------------- + + assign ex4_negate = (ex4_mantissa_precomp[1] & ex4_floges) | + (ex4_fexptes & ex4_b_sign); + + assign ex4_mantissa[1:19] = (ex4_mantissa_neg[1:19] & {19{ex4_negate}}) | + (ex4_mantissa_precomp[1:19] & {19{(~ex4_negate)}}); + + //--------------------------------------------------------------------- + + fu_gst_loa ex4_log_loa( + .a(ex4_mantissa), + //------------------------------------------------------ + .shamt(ex4_shamt[0:4]) + ); + //--------------------------------------------------------------------- + + assign ex4_logof1_specialcase = (~|(ex4_shamt[0:4])); + + //--------------------------------------------------------------------- + + tri_rlmreg_p #( .WIDTH(4), .NEEDS_SRESET(0)) ex5_gst_ctrl_lat( + .force_t(force_t), //d_mode => tiup, delay_lclkr => tidn, + .d_mode(tiup), + .delay_lclkr(delay_lclkr[4]), + .mpw1_b(mpw1_b[4]), + .mpw2_b(mpw2_b[0]), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + //----------------- + .act(ex4_act), + //----------------- + .scout(ex5_gst_ctrl_lat_scout), + .scin(ex5_gst_ctrl_lat_scin), + //----------------- + .din({ex4_floges, + ex4_fexptes, + ex4_negate, + ex4_logof1_specialcase}), + //----------------- + .dout({ex5_floges, + ex5_fexptes, + ex5_negate, + ex5_logof1_specialcase}) + ); + + + tri_rlmreg_p #( .WIDTH(24), .NEEDS_SRESET(0)) ex5_gst_stage_lat( + .force_t(force_t), //d_mode => tiup, delay_lclkr => tidn, + .d_mode(tiup), + .delay_lclkr(delay_lclkr[4]), + .mpw1_b(mpw1_b[4]), + .mpw2_b(mpw2_b[0]), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + //----------------- + .act(ex4_act), + //----------------- + .scout(ex5_gst_stage_lat_scout), + .scin(ex5_gst_stage_lat_scin), + //----------------- + .din({ex4_mantissa, + ex4_shamt}), + //----------------- + .dout({ex5_mantissa, + ex5_shamt}) + ); + //--------------------------------------------------------------------- + //--------------------------------------------------------------------- + //--------------------------------------------------------------------- + + // shift mantissa for log (shamt is set to zeros for exp) + // log mantissa gets normalized here + + assign ex5_mantissa_shlev0[01:19] = ex5_mantissa[01:19]; + + assign l1_enc00 = (~ex5_shamt[3]) & (~ex5_shamt[4]); + assign l1_enc01 = (~ex5_shamt[3]) & ex5_shamt[4]; + assign l1_enc10 = ex5_shamt[3] & (~ex5_shamt[4]); + assign l1_enc11 = ex5_shamt[3] & ex5_shamt[4]; + + assign l2_enc00 = (~ex5_shamt[1]) & (~ex5_shamt[2]); + assign l2_enc01 = (~ex5_shamt[1]) & ex5_shamt[2]; + assign l2_enc10 = ex5_shamt[1] & (~ex5_shamt[2]); + assign l2_enc11 = ex5_shamt[1] & ex5_shamt[2]; + + assign l3_enc00 = (~ex5_shamt[0]); + assign l3_enc01 = ex5_shamt[0]; + + assign ex5_mantissa_shlev1[01:22] = ({zeros[01:03], (ex5_mantissa_shlev0[01:19])} & {22{l1_enc00}}) | + ({zeros[01:02], ({ex5_mantissa_shlev0[01:19], zeros[01]})} & {22{l1_enc01}}) | + ({zeros[01], ({ex5_mantissa_shlev0[01:19], zeros[01:02]})} & {22{l1_enc10}}) | + (({ex5_mantissa_shlev0[01:19], zeros[01:03]}) & {22{l1_enc11}}); + + assign ex5_mantissa_shlev2[01:34] = ({zeros[01:12], (ex5_mantissa_shlev1[01:22])} & {34{l2_enc00}}) | + ({zeros[01:08], ({ex5_mantissa_shlev1[01:22], zeros[01:04]})} & {34{l2_enc01}}) | + ({zeros[01:04], ({ex5_mantissa_shlev1[01:22], zeros[01:08]})} & {34{l2_enc10}}) | + (({ex5_mantissa_shlev1[01:22], zeros[01:12]}) & {34{l2_enc11}}); + + assign ex5_mantissa_shlev3[01:50] = ({zeros[01:16], (ex5_mantissa_shlev2[01:34])} & {50{l3_enc00}}) | + (({ex5_mantissa_shlev2[01:34], zeros[01:16]}) & {50{l3_enc01}}); + + assign ex5_log_mantissa_postsh[01:19] = ex5_mantissa_shlev3[32:50]; + + //---------------------------------------------------------------------------------------------------------------------- + // pow fract logic + + assign ex5_f[1:11] = ex5_mantissa[9:19]; + // ************************************ + // ** vexptefp fract logic + // ************************************ + + assign eb1 = ex5_f[1]; + assign eb2 = ex5_f[2]; + assign eb3 = ex5_f[3]; + assign eb4 = ex5_f[4]; + assign eb5 = ex5_f[5]; + assign eb6 = ex5_f[6]; + assign eb7 = ex5_f[7]; + assign eb8 = ex5_f[8]; + assign eb9 = ex5_f[9]; + assign eb10 = ex5_f[10]; + + assign ex5_f_b[1:11] = (~ex5_f[1:11]); + + //0000 ^s2 + //0001 ^s2 + //0010 ^s2 + //0011 ^s2 + //0100 ^s3 + //0101 ^s3 + //0110 ^s3 + //0111 -- + //1000 -- + //1001 -- + //1010 s3 + //1011 s3 + //1100 s3 + //1101 s2 + //1110 s2 + //1111 s1 + + assign es2_0 = ((~eb1) & (~eb2)); //0,1,2,3 + //4,5 + assign es3_0 = ((~eb1) & eb2 & (~eb3)) | ((~eb1) & eb2 & eb3 & (~eb4)); //6 + //7 + assign esx = ((~eb1) & eb2 & eb3 & eb4) | (eb1 & (~eb2) & (~eb3)); //8,9 + //10,11 + assign es3_1 = (eb1 & (~eb2) & eb3) | (eb1 & eb2 & (~eb3) & (~eb4)); //12 + //13 + assign es2_1 = (eb1 & eb2 & (~eb3) & eb4) | (eb1 & eb2 & eb3 & (~eb4)); //14 + assign es1 = (eb1 & eb2 & eb3 & eb4); //15 + + assign es2 = es2_0 | es2_1; + assign es3 = es3_0 | es3_1; + + assign ec4 = esx; + assign ec5 = es3_0 | es3_1; + assign ec6 = esx | es2_1; + assign ec7 = esx | es3_1; + + //-------------------------------------------------------------------- + // mathematically eliminate the 3:2 compressor + //-------------------------------------------------------------------- + // + // f1234 | 3:2 inputs (f,c,a) | 3:2 carry : sum + // | | + // s2_0 0000 | f4 "0" f2 | !f4.f2 f4^f2 + // s2_0 0001 | f4 "0" f2 | !f4.f2 f4^f2 + // s2_0 0010 | f4 "0" f2 | !f4.f2 f4^f2 + // s2_0 0011 | f4 "0" f2 | !f4.f2 f4^f2 + // | | + // s3_0 0100 | f4 "0" "0" | "0" f4 + // s3_0 0101 | f4 "0" "0" | "0" f4 + // s3_0 0110 | f4 "0" "0" | "0" f4 + // | | + // sx 0111 | f4 "1" "0" | !f4 !f4 + // sx 1000 | f4 "1" "0" | !f4 !f4 + // sx 1001 | f4 "1" "0" | !f4 !f4 + // | | + // s3_1 1010 | f4 "0" "0" | "0" f4 + // s3_1 1011 | f4 "0" "0" | "0" f4 + // s3_1 1100 | f4 "0" "0" | "0" f4 + // | | + // s2_1 1101 | f4 "0" !f2 | !f4.!f2 f4^!f2 + // s2_1 1110 | f4 "0" !f2 | !f4.!f2 f4^!f2 + // | | + // s1 1111 | f4 "0" !f3 | !f4.!f3 f4^!f3 + //--------------------- + + assign ec3_if_s20 = (~eb4) & eb2; + assign ec3_if_s30 = tidn; + assign ec3_if_sx = (~eb4); + assign ec3_if_s31 = tidn; + assign ec3_if_s21 = (~eb4) & (~eb2); + assign ec3_if_s1 = (~eb4) & (~eb3); + + assign es4_if_s20 = (~eb4) ^ eb2; + assign es4_if_s30 = (~eb4); + assign es4_if_sx = eb4; + assign es4_if_s31 = (~eb4); + assign es4_if_s21 = (~eb4) ^ (~eb2); + assign es4_if_s1 = (~eb4) ^ (~eb3); + + assign ec4_if_s20 = (~eb5) & eb3; + assign ec4_if_s30 = (~eb5) | eb2; + assign ec4_if_sx = tidn; + assign ec4_if_s31 = (~eb5) | (~eb2); + assign ec4_if_s21 = (~eb5) & (~eb3); + assign ec4_if_s1 = (~eb5) & (~eb4); + + assign es5_if_s20 = (~eb5) ^ eb3; + assign es5_if_s30 = (~eb5) ^ (~eb2); + assign es5_if_sx = (~eb5); + assign es5_if_s31 = (~eb5) ^ eb2; + assign es5_if_s21 = (~eb5) ^ (~eb3); + assign es5_if_s1 = (~eb5) ^ (~eb4); + + assign ec5_if_s20 = (~eb6) & eb4; + assign ec5_if_s30 = (~eb6) & eb3; + assign ec5_if_sx = (~eb6); + assign ec5_if_s31 = (~eb6) & (~eb3); + assign ec5_if_s21 = (~eb6) | (~eb4); + assign ec5_if_s1 = (~eb6) & (~eb5); + + assign es6_if_s20 = (~eb6) ^ eb4; + assign es6_if_s30 = (~eb6) ^ eb3; + assign es6_if_sx = eb6; + assign es6_if_s31 = (~eb6) ^ (~eb3); + assign es6_if_s21 = (~eb6) ^ eb4; + assign es6_if_s1 = (~eb6) ^ (~eb5); + + assign ec6_if_s20 = (~eb7) & eb5; + assign ec6_if_s30 = (~eb7) & eb4; + assign ec6_if_sx = (~eb7); + assign ec6_if_s31 = (~eb7) | (~eb4); + assign ec6_if_s21 = (~eb7) & (~eb5); + assign ec6_if_s1 = (~eb7) & (~eb6); + + assign es7_if_s20 = (~eb7) ^ eb5; + assign es7_if_s30 = (~eb7) ^ eb4; + assign es7_if_sx = eb7; + assign es7_if_s31 = (~eb7) ^ eb4; + assign es7_if_s21 = (~eb7) ^ (~eb5); + assign es7_if_s1 = (~eb7) ^ (~eb6); + + assign ea4 = (es1 & (~eb3)) | (es2_0 & eb2) | (es2_1 & (~eb2)); + + assign ea5 = (es1 & (~eb4)) | (es2_0 & eb3) | (es2_1 & (~eb3)) | (es3_0 & eb2) | (es3_1 & (~eb2)); + + assign ea6 = (es1 & (~eb5)) | (es2_0 & eb4) | (es2_1 & (~eb4)) | (es3_0 & eb3) | (es3_1 & (~eb3)); + + assign ea7 = (es1 & (~eb6)) | (es2_0 & eb5) | (es2_1 & (~eb5)) | (es3_0 & eb4) | (es3_1 & (~eb4)); + + assign ea8 = (es1 & (~eb7)) | (es2_0 & eb6) | (es2_1 & (~eb6)) | (es3_0 & eb5) | (es3_1 & (~eb5)); + + assign ea9 = (es1 & (~eb8)) | (es2_0 & eb7) | (es2_1 & (~eb7)) | (es3_0 & eb6) | (es3_1 & (~eb6)); + + assign ea10 = (es1 & (~eb9)) | (es2_0 & eb8) | (es2_1 & (~eb8)) | (es3_0 & eb7) | (es3_1 & (~eb7)); + + assign ea11 = (es1 & (~eb10)) | (es2_0 & eb9) | (es2_1 & (~eb9)) | (es3_0 & eb8) | (es3_1 & (~eb8)); + + //------------------------------------------------------------------------------ + + assign ex5_ea[4:11] = {ea4, ea5, ea6, ea7, ea8, ea9, ea10, ea11}; + assign ex5_ec[4:11] = {ec4, ec5, ec6, ec7, zeros[1:4]}; + + assign ex5_addend1[1:11] = ex5_f_b[1:11]; + assign ex5_addend2[1:11] = {zeros[1:3], ex5_ea[4:11]}; + assign ex5_addend3[1:11] = {zeros[1:3], ex5_ec[4:11]}; + + assign ex5_fsum[1] = ex5_f_b[1]; + assign ex5_fsum[2] = ex5_f_b[2]; + assign ex5_fsum[3] = ex5_f_b[3]; + assign ex5_fsum[4] = (es1 & es4_if_s1) | (es2_0 & es4_if_s20) | (es3_0 & es4_if_s30) | (esx & es4_if_sx) | (es3_1 & es4_if_s31) | (es2_1 & es4_if_s21); + assign ex5_fsum[5] = (es1 & es5_if_s1) | (es2_0 & es5_if_s20) | (es3_0 & es5_if_s30) | (esx & es5_if_sx) | (es3_1 & es5_if_s31) | (es2_1 & es5_if_s21); + assign ex5_fsum[6] = (es1 & es6_if_s1) | (es2_0 & es6_if_s20) | (es3_0 & es6_if_s30) | (esx & es6_if_sx) | (es3_1 & es6_if_s31) | (es2_1 & es6_if_s21); + assign ex5_fsum[7] = (es1 & es7_if_s1) | (es2_0 & es7_if_s20) | (es3_0 & es7_if_s30) | (esx & es7_if_sx) | (es3_1 & es7_if_s31) | (es2_1 & es7_if_s21); + assign ex5_fsum[8] = ex5_f_b[8]; + assign ex5_fsum[9] = ex5_f_b[9]; + assign ex5_fsum[10] = ex5_f_b[10]; + assign ex5_fsum[11] = ex5_f_b[11]; + + assign ex5_fcarryin[1] = tidn; + assign ex5_fcarryin[2] = tidn; + assign ex5_fcarryin[3] = (es1 & ec3_if_s1) | (es2_0 & ec3_if_s20) | (es3_0 & ec3_if_s30) | (esx & ec3_if_sx) | (es3_1 & ec3_if_s31) | (es2_1 & ec3_if_s21); + assign ex5_fcarryin[4] = (es1 & ec4_if_s1) | (es2_0 & ec4_if_s20) | (es3_0 & ec4_if_s30) | (esx & ec4_if_sx) | (es3_1 & ec4_if_s31) | (es2_1 & ec4_if_s21); + assign ex5_fcarryin[5] = (es1 & ec5_if_s1) | (es2_0 & ec5_if_s20) | (es3_0 & ec5_if_s30) | (esx & ec5_if_sx) | (es3_1 & ec5_if_s31) | (es2_1 & ec5_if_s21); + assign ex5_fcarryin[6] = (es1 & ec6_if_s1) | (es2_0 & ec6_if_s20) | (es3_0 & ec6_if_s30) | (esx & ec6_if_sx) | (es3_1 & ec6_if_s31) | (es2_1 & ec6_if_s21); + assign ex5_fcarryin[7] = tidn; + assign ex5_fcarryin[8] = ea8; + assign ex5_fcarryin[9] = ea9; + assign ex5_fcarryin[10] = ea10; + assign ex5_fcarryin[11] = ea11; + + assign ex5_powf_a_addend_b = (~ex5_fsum[1:11]); + assign ex5_powf_b_addend_b = (~(ex5_fcarryin[1:11])); + + + fu_gst_add11 ex5_powfractadd11( + .a_b(ex5_powf_a_addend_b), + .b_b(ex5_powf_b_addend_b), + //------------------------------------------------------ + .s0(ex5_pow_fract_b) + ); + + assign ex5_pow_fract = (~ex5_pow_fract_b); + + //---------------------------------------------------------------------------------------------------------------------- + // not (dp bias +9) + assign ex5_log_dp_bias = (11'b01111110111 & {11{(~ex5_logof1_specialcase)}}) | + (11'b11111111101 & {11{ex5_logof1_specialcase}}); // results in exp of 000..1, which is zero + + assign ex5_log_a_addend_b[1:11] = {zeros[1:6], ex5_shamt[0:4]}; + assign ex5_log_b_addend_b[1:11] = ex5_log_dp_bias; + + assign ex5_pow_a_addend_b[1:11] = (~({ex5_mantissa[1], ex5_mantissa[1], ex5_mantissa[1], ex5_mantissa[1:8]})); + assign ex5_pow_b_addend_b[1:11] = 11'b10000000000; // dp bias + + assign ex5_exponent_a_addend_b = (ex5_log_a_addend_b & {11{ex5_floges}}) | + (ex5_pow_a_addend_b & {11{ex5_fexptes}}); + + assign ex5_exponent_b_addend_b = (ex5_log_b_addend_b & {11{ex5_floges}}) | + (ex5_pow_b_addend_b & {11{ex5_fexptes}}); + + //--------------------------------------------------------------------- + + + fu_gst_add11 ex5_explogadd11( + .a_b(ex5_exponent_a_addend_b), + .b_b(ex5_exponent_b_addend_b), + //------------------------------------------------------ + .s0(ex5_biased_exponent_result) + ); + //--------------------------------------------------------------------- + + assign ex5_log_fract = ex5_log_mantissa_postsh[01:19]; + assign ex5_log_signbit = ex5_negate; + + assign ex5_signbit_din = ex5_log_signbit & ex5_floges; + + assign ex5_fract_din = (({((~ex5_logof1_specialcase)), ex5_log_fract[1:19]}) & {20{ex5_floges}}) | + (({tiup, ex5_pow_fract[1:11], zeros[1:8]}) & {20{ex5_fexptes}}); + + //--------------------------------------------------------------------- + //--------------------------------------------------------------------- + //--------------------------------------------------------------------- + + tri_rlmreg_p #( .WIDTH(2), .NEEDS_SRESET(0)) ex6_gst_ctrl_lat( + .force_t(force_t), //d_mode => tiup, delay_lclkr => tidn, + .d_mode(tiup), + .delay_lclkr(delay_lclkr[5]), + .mpw1_b(mpw1_b[5]), + .mpw2_b(mpw2_b[1]), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + //----------------- + .act(ex5_act), + //----------------- + .scout(ex6_gst_ctrl_lat_scout), + .scin(ex6_gst_ctrl_lat_scin), + //----------------- + .din({ex5_floges, + ex5_fexptes}), + //----------------- + .dout({ex6_floges, + ex6_fexptes}) + ); + + + tri_rlmreg_p #( .WIDTH(32), .NEEDS_SRESET(0)) ex6_gst_stage_lat( + .force_t(force_t), //d_mode => tiup, delay_lclkr => tidn, + .d_mode(tiup), + .delay_lclkr(delay_lclkr[5]), + .mpw1_b(mpw1_b[5]), + .mpw2_b(mpw2_b[1]), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + //----------------- + .act(ex5_act), + //----------------- + .scout(ex6_gst_stage_lat_scout), + .scin(ex6_gst_stage_lat_scin), + //----------------- + .din({ex5_signbit_din, + ex5_biased_exponent_result, + ex5_fract_din}), + //----------------- + .dout({ex6_signbit, + ex6_biased_exponent_result, + ex6_fract}) + ); + + //--------------------------------------------------------------------- + //--------------------------------------------------------------------- + //--------------------------------------------------------------------- + + assign f_gst_ex6_logexp_sign = ex6_signbit; + assign f_gst_ex6_logexp_exp = ex6_biased_exponent_result; + assign f_gst_ex6_logexp_fract = ex6_fract; + assign f_gst_ex6_logexp_v = ex6_floges | ex6_fexptes; + + // todo: clk gating with acts, gate with log,exp instr decodes, fpu enable, etc + + assign ex3_gst_ctrl_lat_scin[0:1] = {f_gst_si, ex3_gst_ctrl_lat_scout[0]}; + assign ex4_gst_ctrl_lat_scin[0:1] = {ex3_gst_ctrl_lat_scout[1], ex4_gst_ctrl_lat_scout[0]}; + assign ex5_gst_ctrl_lat_scin[0:3] = {ex4_gst_ctrl_lat_scout[1], ex5_gst_ctrl_lat_scout[0:2]}; + assign ex6_gst_ctrl_lat_scin[0:1] = {ex5_gst_ctrl_lat_scout[3], ex6_gst_ctrl_lat_scout[0]}; + assign ex3_gst_stage_lat_scin[0:32] = {ex6_gst_ctrl_lat_scout[1], ex3_gst_stage_lat_scout[0:31]}; + assign ex4_gst_stage_lat_scin[0:19] = {ex3_gst_stage_lat_scout[32], ex4_gst_stage_lat_scout[0:18]}; + assign ex5_gst_stage_lat_scin[0:23] = {ex4_gst_stage_lat_scout[19], ex5_gst_stage_lat_scout[0:22]}; + assign ex6_gst_stage_lat_scin[0:31] = {ex5_gst_stage_lat_scout[23], ex6_gst_stage_lat_scout[0:30]}; + + assign act_si[0:7] = {act_so[1:7], ex6_gst_stage_lat_scout[31]}; + + assign f_gst_so = act_so[0]; + +endmodule diff --git a/dev/verilog/work/fu_gst_add11.v b/dev/verilog/work/fu_gst_add11.v new file mode 100755 index 0000000..5d55b53 --- /dev/null +++ b/dev/verilog/work/fu_gst_add11.v @@ -0,0 +1,151 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +////############################################################################ +////##### FUQ_GEST_add11.VHDL ######### +////##### side pipe for graphics estimates ######### +////##### flogefp, fexptefp ######### +////##### ######### +////############################################################################ + +module fu_gst_add11( + a_b, + b_b, + s0 +); + `include "tri_a2o.vh" + + + input [0:10] a_b; // inverted adder input + input [0:10] b_b; // inverted adder input + output [0:10] s0; + + (* NO_MODIFICATION="TRUE" *) + wire [0:10] p1; + (* NO_MODIFICATION="TRUE" *) + wire [1:10] g1; + (* NO_MODIFICATION="TRUE" *) + wire [1:9] t1; + (* NO_MODIFICATION="TRUE" *) + wire [1:10] g2_b; + (* NO_MODIFICATION="TRUE" *) + wire [1:10] g4; + (* NO_MODIFICATION="TRUE" *) + wire [1:10] g8_b; + (* NO_MODIFICATION="TRUE" *) + wire [1:10] c16; + (* NO_MODIFICATION="TRUE" *) + wire [1:8] t2_b; + (* NO_MODIFICATION="TRUE" *) + wire [1:6] t4; + (* NO_MODIFICATION="TRUE" *) + wire [1:2] t8_b; + + assign p1[0:10] = (a_b[0:10] ^ b_b[0:10]); + assign g1[1:10] = (~(a_b[1:10] | b_b[1:10])); + assign t1[1:9] = (~(a_b[1:9] & b_b[1:9])); + + //--------------------------------------------- + // carry chain --- + //--------------------------------------------- + + assign g2_b[1] = (~(g1[1] | (t1[1] & g1[2]))); + assign g2_b[2] = (~(g1[2] | (t1[2] & g1[3]))); + assign g2_b[3] = (~(g1[3] | (t1[3] & g1[4]))); + assign g2_b[4] = (~(g1[4] | (t1[4] & g1[5]))); + assign g2_b[5] = (~(g1[5] | (t1[5] & g1[6]))); + assign g2_b[6] = (~(g1[6] | (t1[6] & g1[7]))); + assign g2_b[7] = (~(g1[7] | (t1[7] & g1[8]))); + assign g2_b[8] = (~(g1[8] | (t1[8] & g1[9]))); + assign g2_b[9] = (~(g1[9] | (t1[9] & g1[10]))); //done + assign g2_b[10] = (~(g1[10])); + assign t2_b[1] = (~(t1[1] & t1[2])); + assign t2_b[2] = (~(t1[2] & t1[3])); + assign t2_b[3] = (~(t1[3] & t1[4])); + assign t2_b[4] = (~(t1[4] & t1[5])); + assign t2_b[5] = (~(t1[5] & t1[6])); + assign t2_b[6] = (~(t1[6] & t1[7])); + assign t2_b[7] = (~(t1[7] & t1[8])); + assign t2_b[8] = (~(t1[8] & t1[9])); + + assign g4[1] = (~(g2_b[1] & (t2_b[1] | g2_b[3]))); + assign g4[2] = (~(g2_b[2] & (t2_b[2] | g2_b[4]))); + assign g4[3] = (~(g2_b[3] & (t2_b[3] | g2_b[5]))); + assign g4[4] = (~(g2_b[4] & (t2_b[4] | g2_b[6]))); + assign g4[5] = (~(g2_b[5] & (t2_b[5] | g2_b[7]))); + assign g4[6] = (~(g2_b[6] & (t2_b[6] | g2_b[8]))); + assign g4[7] = (~(g2_b[7] & (t2_b[7] | g2_b[9]))); //done + assign g4[8] = (~(g2_b[8] & (t2_b[8] | g2_b[10]))); //done + assign g4[9] = (~(g2_b[9])); + assign g4[10] = (~(g2_b[10])); + assign t4[1] = (~(t2_b[1] | t2_b[3])); + assign t4[2] = (~(t2_b[2] | t2_b[4])); + assign t4[3] = (~(t2_b[3] | t2_b[5])); + assign t4[4] = (~(t2_b[4] | t2_b[6])); + assign t4[5] = (~(t2_b[5] | t2_b[7])); + assign t4[6] = (~(t2_b[6] | t2_b[8])); + + assign g8_b[1] = (~(g4[1] | (t4[1] & g4[5]))); + assign g8_b[2] = (~(g4[2] | (t4[2] & g4[6]))); + assign g8_b[3] = (~(g4[3] | (t4[3] & g4[7]))); //done + assign g8_b[4] = (~(g4[4] | (t4[4] & g4[8]))); //done + assign g8_b[5] = (~(g4[5] | (t4[5] & g4[9]))); //done + assign g8_b[6] = (~(g4[6] | (t4[6] & g4[10]))); //done + assign g8_b[7] = (~(g4[7])); + assign g8_b[8] = (~(g4[8])); + assign g8_b[9] = (~(g4[9])); + assign g8_b[10] = (~(g4[10])); + assign t8_b[1] = (~(t4[1] & t4[5])); + assign t8_b[2] = (~(t4[2] & t4[6])); + + assign c16[1] = (~(g8_b[1] & (t8_b[1] | g8_b[9]))); //done + assign c16[2] = (~(g8_b[2] & (t8_b[2] | g8_b[10]))); //done + assign c16[3] = (~(g8_b[3])); + assign c16[4] = (~(g8_b[4])); + assign c16[5] = (~(g8_b[5])); + assign c16[6] = (~(g8_b[6])); + assign c16[7] = (~(g8_b[7])); + assign c16[8] = (~(g8_b[8])); + assign c16[9] = (~(g8_b[9])); + assign c16[10] = (~(g8_b[10])); + + //--------------------------------------------- + // final result --- + //--------------------------------------------- + + assign s0[0:9] = p1[0:9] ^ c16[1:10]; + assign s0[10] = p1[10]; + + +endmodule + + + + diff --git a/dev/verilog/work/fu_gst_inc19.v b/dev/verilog/work/fu_gst_inc19.v new file mode 100755 index 0000000..8ca98ef --- /dev/null +++ b/dev/verilog/work/fu_gst_inc19.v @@ -0,0 +1,164 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +////############################################################################ +////##### FUQ_GEST_inc19.VHDL ######### +////##### side pipe for graphics estimates ######### +////##### flogefp, fexptefp ######### +////##### ######### +////############################################################################ + +module fu_gst_inc19( + a, + o +); + `include "tri_a2o.vh" + + + + input [1:19] a; + + output [1:19] o; // sum if ci=1 + + + wire [01:19] a_sum; + wire [02:19] a_cout_b; + (* NO_MODIFICATION="TRUE" *) + wire [02:19] g2_b; + (* NO_MODIFICATION="TRUE" *) + wire [02:19] g4; + (* NO_MODIFICATION="TRUE" *) + wire [02:19] g8_b; + (* NO_MODIFICATION="TRUE" *) + wire [02:19] g16; + + assign g2_b[19] = (~(a[19])); + assign g2_b[18] = (~(a[18] & a[19])); + assign g2_b[17] = (~(a[17] & a[18])); + assign g2_b[16] = (~(a[16] & a[17])); + assign g2_b[15] = (~(a[15] & a[16])); + assign g2_b[14] = (~(a[14] & a[15])); + assign g2_b[13] = (~(a[13] & a[14])); + assign g2_b[12] = (~(a[12] & a[13])); + assign g2_b[11] = (~(a[11] & a[12])); + assign g2_b[10] = (~(a[10] & a[11])); + assign g2_b[9] = (~(a[9] & a[10])); + assign g2_b[8] = (~(a[8] & a[9])); + assign g2_b[7] = (~(a[7] & a[8])); + assign g2_b[6] = (~(a[6] & a[7])); + assign g2_b[5] = (~(a[5] & a[6])); + assign g2_b[4] = (~(a[4] & a[5])); + assign g2_b[3] = (~(a[3] & a[4])); + assign g2_b[2] = (~(a[2] & a[3])); + + assign g4[19] = (~(g2_b[19])); + assign g4[18] = (~(g2_b[18])); + assign g4[17] = (~(g2_b[17] | g2_b[19])); + assign g4[16] = (~(g2_b[16] | g2_b[18])); + assign g4[15] = (~(g2_b[15] | g2_b[17])); + assign g4[14] = (~(g2_b[14] | g2_b[16])); + assign g4[13] = (~(g2_b[13] | g2_b[15])); + assign g4[12] = (~(g2_b[12] | g2_b[14])); + assign g4[11] = (~(g2_b[11] | g2_b[13])); + assign g4[10] = (~(g2_b[10] | g2_b[12])); + assign g4[9] = (~(g2_b[9] | g2_b[11])); + assign g4[8] = (~(g2_b[8] | g2_b[10])); + assign g4[7] = (~(g2_b[7] | g2_b[9])); + assign g4[6] = (~(g2_b[6] | g2_b[8])); + assign g4[5] = (~(g2_b[5] | g2_b[7])); + assign g4[4] = (~(g2_b[4] | g2_b[6])); + assign g4[3] = (~(g2_b[3] | g2_b[5])); + assign g4[2] = (~(g2_b[2] | g2_b[4])); + + assign g8_b[19] = (~(g4[19])); + assign g8_b[18] = (~(g4[18])); + assign g8_b[17] = (~(g4[17])); + assign g8_b[16] = (~(g4[16])); + assign g8_b[15] = (~(g4[15] & g4[19])); + assign g8_b[14] = (~(g4[14] & g4[18])); + assign g8_b[13] = (~(g4[13] & g4[17])); + assign g8_b[12] = (~(g4[12] & g4[16])); + assign g8_b[11] = (~(g4[11] & g4[15])); + assign g8_b[10] = (~(g4[10] & g4[14])); + assign g8_b[9] = (~(g4[9] & g4[13])); + assign g8_b[8] = (~(g4[8] & g4[12])); + assign g8_b[7] = (~(g4[7] & g4[11])); + assign g8_b[6] = (~(g4[6] & g4[10])); + assign g8_b[5] = (~(g4[5] & g4[9])); + assign g8_b[4] = (~(g4[4] & g4[8])); + assign g8_b[3] = (~(g4[3] & g4[7])); + assign g8_b[2] = (~(g4[2] & g4[6])); + + assign g16[19] = (~(g8_b[19])); + assign g16[18] = (~(g8_b[18])); + assign g16[17] = (~(g8_b[17])); + assign g16[16] = (~(g8_b[16])); + assign g16[15] = (~(g8_b[15])); + assign g16[14] = (~(g8_b[14])); + assign g16[13] = (~(g8_b[13])); + assign g16[12] = (~(g8_b[12])); + assign g16[11] = (~(g8_b[11] | g8_b[19])); + assign g16[10] = (~(g8_b[10] | g8_b[18])); + assign g16[9] = (~(g8_b[9] | g8_b[17])); + assign g16[8] = (~(g8_b[8] | g8_b[16])); + assign g16[7] = (~(g8_b[7] | g8_b[15])); + assign g16[6] = (~(g8_b[6] | g8_b[14])); + assign g16[5] = (~(g8_b[5] | g8_b[13])); + assign g16[4] = (~(g8_b[4] | g8_b[12])); + assign g16[3] = (~(g8_b[3] | g8_b[11])); + assign g16[2] = (~(g8_b[2] | g8_b[10])); + + assign a_cout_b[19] = (~(g16[19])); + assign a_cout_b[18] = (~(g16[18])); + assign a_cout_b[17] = (~(g16[17])); + assign a_cout_b[16] = (~(g16[16])); + assign a_cout_b[15] = (~(g16[15])); + assign a_cout_b[14] = (~(g16[14])); + assign a_cout_b[13] = (~(g16[13])); + assign a_cout_b[12] = (~(g16[12])); + assign a_cout_b[11] = (~(g16[11])); + assign a_cout_b[10] = (~(g16[10])); + assign a_cout_b[9] = (~(g16[9])); + assign a_cout_b[8] = (~(g16[8])); + assign a_cout_b[7] = (~(g16[7])); + assign a_cout_b[6] = (~(g16[6])); + assign a_cout_b[5] = (~(g16[5])); + assign a_cout_b[4] = (~(g16[4])); + assign a_cout_b[3] = (~(g16[3] & g16[19])); + assign a_cout_b[2] = (~(g16[2] & g16[18])); + + //--------------------------------------------------------- + assign a_sum[1:18] = a[1:18]; + assign a_sum[19] = (~a[19]); + + assign o[01:18] = (~(a_sum[01:18] ^ a_cout_b[02:19])); //output + assign o[19] = a_sum[19]; //output + +endmodule diff --git a/dev/verilog/work/fu_gst_loa.v b/dev/verilog/work/fu_gst_loa.v new file mode 100755 index 0000000..ed98846 --- /dev/null +++ b/dev/verilog/work/fu_gst_loa.v @@ -0,0 +1,103 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +////############################################################################ +////##### FU_GEST_loa.VHDL ######### +////##### side pipe for graphics estimates ######### +////##### flogefp, fexptefp ######### +////##### ######### +////############################################################################ + +module fu_gst_loa( + a, + shamt +); + `include "tri_a2o.vh" + + + input [1:19] a; + + output [0:4] shamt; + + + wire unused; + + assign unused = a[19]; + + //@@ ESPRESSO TABLE START @@ + // ################################################################################################## + + // ################################################################################################## + // .i 19 + // .o 5 + // .ilb a(01) a(02) a(03) a(04) a(05) a(06) a(07) a(08) a(09) a(10) a(11) a(12) a(13) a(14) a(15) a(16) a(17) a(18) a(19) + // .ob shamt(0) shamt(1) shamt(2) shamt(3) shamt(4) + + // .type fr + ////####################### + // + // 0000000000000000001 10011 + // 000000000000000001- 10010 + // 00000000000000001-- 10001 + // 0000000000000001--- 10000 + // 000000000000001---- 01111 + // 00000000000001----- 01110 + // 0000000000001------ 01101 + // 000000000001------- 01100 + // 00000000001-------- 01011 + // 0000000001--------- 01010 + // 000000001---------- 01001 + // 00000001----------- 01000 + // 0000001------------ 00111 + // 000001------------- 00110 + // 00001-------------- 00101 + // 0001--------------- 00100 + // 001---------------- 00011 + // 01----------------- 00010 + // 1------------------ 00001 + // 0000000000000000000 00000 + + // ############################################################################### + // .e + //@@ ESPRESSO TABLE END @@ + + //@@ ESPRESSO LOGIC START @@ + // logic generated on: Tue Dec 4 13:14:17 2007 + assign shamt[0] = ((~a[01]) & (~a[02]) & (~a[03]) & (~a[04]) & (~a[05]) & (~a[06]) & (~a[07]) & (~a[08]) & (~a[09]) & (~a[10]) & (~a[11]) & (~a[12]) & (~a[13]) & (~a[14]) & (~a[15]) & a[19]) | ((~a[01]) & (~a[02]) & (~a[03]) & (~a[04]) & (~a[05]) & (~a[06]) & (~a[07]) & (~a[08]) & (~a[09]) & (~a[10]) & (~a[11]) & (~a[12]) & (~a[13]) & (~a[14]) & (~a[15]) & a[18]) | ((~a[01]) & (~a[02]) & (~a[03]) & (~a[04]) & (~a[05]) & (~a[06]) & (~a[07]) & (~a[08]) & (~a[09]) & (~a[10]) & (~a[11]) & (~a[12]) & (~a[13]) & (~a[14]) & (~a[15]) & a[17]) | ((~a[01]) & (~a[02]) & (~a[03]) & (~a[04]) & (~a[05]) & (~a[06]) & (~a[07]) & (~a[08]) & (~a[09]) & (~a[10]) & (~a[11]) & (~a[12]) & (~a[13]) & (~a[14]) & (~a[15]) & a[16]); + + assign shamt[1] = ((~a[01]) & (~a[02]) & (~a[03]) & (~a[04]) & (~a[05]) & (~a[06]) & (~a[07]) & a[15]) | ((~a[01]) & (~a[02]) & (~a[03]) & (~a[04]) & (~a[05]) & (~a[06]) & (~a[07]) & a[14]) | ((~a[01]) & (~a[02]) & (~a[03]) & (~a[04]) & (~a[05]) & (~a[06]) & (~a[07]) & a[13]) | ((~a[01]) & (~a[02]) & (~a[03]) & (~a[04]) & (~a[05]) & (~a[06]) & (~a[07]) & a[12]) | ((~a[01]) & (~a[02]) & (~a[03]) & (~a[04]) & (~a[05]) & (~a[06]) & (~a[07]) & a[11]) | ((~a[01]) & (~a[02]) & (~a[03]) & (~a[04]) & (~a[05]) & (~a[06]) & (~a[07]) & a[10]) | ((~a[01]) & (~a[02]) & (~a[03]) & (~a[04]) & (~a[05]) & (~a[06]) & (~a[07]) & a[09]) | ((~a[01]) & (~a[02]) & (~a[03]) & (~a[04]) & (~a[05]) & (~a[06]) & (~a[07]) & a[08]); + + assign shamt[2] = ((~a[01]) & (~a[02]) & (~a[03]) & (~a[08]) & (~a[09]) & (~a[10]) & (~a[11]) & a[15]) | ((~a[01]) & (~a[02]) & (~a[03]) & (~a[08]) & (~a[09]) & (~a[10]) & (~a[11]) & a[14]) | ((~a[01]) & (~a[02]) & (~a[03]) & (~a[08]) & (~a[09]) & (~a[10]) & (~a[11]) & a[13]) | ((~a[01]) & (~a[02]) & (~a[03]) & (~a[08]) & (~a[09]) & (~a[10]) & (~a[11]) & a[12]) | ((~a[01]) & (~a[02]) & (~a[03]) & a[07]) | ((~a[01]) & (~a[02]) & (~a[03]) & a[06]) | ((~a[01]) & (~a[02]) & (~a[03]) & a[05]) | ((~a[01]) & (~a[02]) & (~a[03]) & a[04]); + + assign shamt[3] = ((~a[01]) & (~a[04]) & (~a[05]) & (~a[08]) & (~a[09]) & (~a[12]) & (~a[13]) & (~a[16]) & (~a[17]) & a[19]) | ((~a[01]) & (~a[04]) & (~a[05]) & (~a[08]) & (~a[09]) & (~a[12]) & (~a[13]) & (~a[16]) & (~a[17]) & a[18]) | ((~a[01]) & (~a[04]) & (~a[05]) & (~a[08]) & (~a[09]) & (~a[12]) & (~a[13]) & a[15]) | ((~a[01]) & (~a[04]) & (~a[05]) & (~a[08]) & (~a[09]) & (~a[12]) & (~a[13]) & a[14]) | ((~a[01]) & (~a[04]) & (~a[05]) & (~a[08]) & (~a[09]) & a[11]) | ((~a[01]) & (~a[04]) & (~a[05]) & (~a[08]) & (~a[09]) & a[10]) | ((~a[01]) & (~a[04]) & (~a[05]) & a[07]) | ((~a[01]) & (~a[04]) & (~a[05]) & a[06]) | ((~a[01]) & a[03]) | ((~a[01]) & a[02]); + + assign shamt[4] = ((~a[02]) & (~a[04]) & (~a[06]) & (~a[08]) & (~a[10]) & (~a[12]) & (~a[14]) & (~a[16]) & (~a[18]) & a[19]) | ((~a[02]) & (~a[04]) & (~a[06]) & (~a[08]) & (~a[10]) & (~a[12]) & (~a[14]) & (~a[16]) & a[17]) | ((~a[02]) & (~a[04]) & (~a[06]) & (~a[08]) & (~a[10]) & (~a[12]) & (~a[14]) & a[15]) | ((~a[02]) & (~a[04]) & (~a[06]) & (~a[08]) & (~a[10]) & (~a[12]) & a[13]) | ((~a[02]) & (~a[04]) & (~a[06]) & (~a[08]) & (~a[10]) & a[11]) | ((~a[02]) & (~a[04]) & (~a[06]) & (~a[08]) & a[09]) | ((~a[02]) & (~a[04]) & (~a[06]) & a[07]) | ((~a[02]) & (~a[04]) & a[05]) | ((~a[02]) & a[03]) | (a[01]); + +endmodule diff --git a/dev/verilog/work/fu_hc16pp.v b/dev/verilog/work/fu_hc16pp.v new file mode 100755 index 0000000..9a5344e --- /dev/null +++ b/dev/verilog/work/fu_hc16pp.v @@ -0,0 +1,507 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + + `include "tri_a2o.vh" + + + +module fu_hc16pp( + x, + y, + ci0, + ci0_b, + ci1, + ci1_b, + s0, + s1, + g16, + t16 +); + input [0:15] x; + input [0:15] y; + input ci0; + input ci0_b; + input ci1; + input ci1_b; + output [0:15] s0; + output [0:15] s1; + output g16; + output t16; + + wire [0:15] g01_b; + wire [0:15] t01_b; + wire [0:15] p01_b; + wire [0:15] p01; + wire [0:7] g01od; + wire [0:7] t01od; + wire [0:7] g02ev; + wire [0:7] t02ev; + wire [1:7] g02ev_b; + wire [1:7] t02ev_b; + wire [1:7] g04ev; + wire [1:7] t04ev; + wire [1:7] g08ev_b; + wire [1:7] t08ev_b; + wire [1:7] g16ev; + wire [1:7] t16ev; + wire [1:15] c0_b; + wire [1:15] c1_b; + wire [0:15] s0_raw; + wire [0:15] s1_raw; + wire [0:15] s0_x_b; + wire [0:15] s0_y_b; + wire [0:15] s1_x_b; + wire [0:15] s1_y_b; + + wire glb_g04_e01_b; //new // rep glb + wire glb_g04_e23_b; + wire glb_g04_e45_b; + wire glb_g04_e67_b; + wire glb_t04_e01_b; //new // rep glb + wire glb_t04_e23_b; + wire glb_t04_e45_b; + wire glb_t04_e67_b; + wire glb_g08_e03; //new // rep glb + wire glb_g08_e47; + wire glb_t08_e03; + wire glb_t08_e47; + wire glb_g16_e07_b; //new // rep glb + wire glb_t16_e07_b; + + + + ////##################################### + ////## group 1 + ////##################################### + // g01_b(0 to 15) <= not( x(0 to 15) and y(0 to 15) ); -- critical + // t01_b(0 to 15) <= not( x(0 to 15) or y(0 to 15) ); -- critical + // p01_b(0 to 15) <= not( x(0 to 15) xor y(0 to 15) ); -- not critical + + assign g01_b[0] = (~(x[0] & y[0])); //critical + assign g01_b[1] = (~(x[1] & y[1])); //critical + assign g01_b[2] = (~(x[2] & y[2])); //critical + assign g01_b[3] = (~(x[3] & y[3])); //critical + assign g01_b[4] = (~(x[4] & y[4])); //critical + assign g01_b[5] = (~(x[5] & y[5])); //critical + assign g01_b[6] = (~(x[6] & y[6])); //critical + assign g01_b[7] = (~(x[7] & y[7])); //critical + assign g01_b[8] = (~(x[8] & y[8])); //critical + assign g01_b[9] = (~(x[9] & y[9])); //critical + assign g01_b[10] = (~(x[10] & y[10])); //critical + assign g01_b[11] = (~(x[11] & y[11])); //critical + assign g01_b[12] = (~(x[12] & y[12])); //critical + assign g01_b[13] = (~(x[13] & y[13])); //critical + assign g01_b[14] = (~(x[14] & y[14])); //critical + assign g01_b[15] = (~(x[15] & y[15])); //critical + + assign t01_b[0] = (~(x[0] | y[0])); //critical + assign t01_b[1] = (~(x[1] | y[1])); //critical + assign t01_b[2] = (~(x[2] | y[2])); //critical + assign t01_b[3] = (~(x[3] | y[3])); //critical + assign t01_b[4] = (~(x[4] | y[4])); //critical + assign t01_b[5] = (~(x[5] | y[5])); //critical + assign t01_b[6] = (~(x[6] | y[6])); //critical + assign t01_b[7] = (~(x[7] | y[7])); //critical + assign t01_b[8] = (~(x[8] | y[8])); //critical + assign t01_b[9] = (~(x[9] | y[9])); //critical + assign t01_b[10] = (~(x[10] | y[10])); //critical + assign t01_b[11] = (~(x[11] | y[11])); //critical + assign t01_b[12] = (~(x[12] | y[12])); //critical + assign t01_b[13] = (~(x[13] | y[13])); //critical + assign t01_b[14] = (~(x[14] | y[14])); //critical + assign t01_b[15] = (~(x[15] | y[15])); //critical + + assign p01[0] = (x[0] ^ y[0]); //not critical + assign p01[1] = (x[1] ^ y[1]); //not critical + assign p01[2] = (x[2] ^ y[2]); //not critical + assign p01[3] = (x[3] ^ y[3]); //not critical + assign p01[4] = (x[4] ^ y[4]); //not critical + assign p01[5] = (x[5] ^ y[5]); //not critical + assign p01[6] = (x[6] ^ y[6]); //not critical + assign p01[7] = (x[7] ^ y[7]); //not critical + assign p01[8] = (x[8] ^ y[8]); //not critical + assign p01[9] = (x[9] ^ y[9]); //not critical + assign p01[10] = (x[10] ^ y[10]); //not critical + assign p01[11] = (x[11] ^ y[11]); //not critical + assign p01[12] = (x[12] ^ y[12]); //not critical + assign p01[13] = (x[13] ^ y[13]); //not critical + assign p01[14] = (x[14] ^ y[14]); //not critical + assign p01[15] = (x[15] ^ y[15]); //not critical + + assign p01_b[0] = (~(p01[0])); //not critical + assign p01_b[1] = (~(p01[1])); //not critical + assign p01_b[2] = (~(p01[2])); //not critical + assign p01_b[3] = (~(p01[3])); //not critical + assign p01_b[4] = (~(p01[4])); //not critical + assign p01_b[5] = (~(p01[5])); //not critical + assign p01_b[6] = (~(p01[6])); //not critical + assign p01_b[7] = (~(p01[7])); //not critical + assign p01_b[8] = (~(p01[8])); //not critical + assign p01_b[9] = (~(p01[9])); //not critical + assign p01_b[10] = (~(p01[10])); //not critical + assign p01_b[11] = (~(p01[11])); //not critical + assign p01_b[12] = (~(p01[12])); //not critical + assign p01_b[13] = (~(p01[13])); //not critical + assign p01_b[14] = (~(p01[14])); //not critical + assign p01_b[15] = (~(p01[15])); //not critical + + assign g01od[0] = (~g01_b[1]); + assign g01od[1] = (~g01_b[3]); + assign g01od[2] = (~g01_b[5]); + assign g01od[3] = (~g01_b[7]); + assign g01od[4] = (~g01_b[9]); + assign g01od[5] = (~g01_b[11]); + assign g01od[6] = (~g01_b[13]); + assign g01od[7] = (~g01_b[15]); + + assign t01od[0] = (~t01_b[1]); + assign t01od[1] = (~t01_b[3]); + assign t01od[2] = (~t01_b[5]); + assign t01od[3] = (~t01_b[7]); + assign t01od[4] = (~t01_b[9]); + assign t01od[5] = (~t01_b[11]); + assign t01od[6] = (~t01_b[13]); + assign t01od[7] = (~t01_b[15]); + + ////##################################### + ////## group 2 // local and global (shared) + ////##################################### + + assign g02ev[7] = (~((t01_b[14] | g01_b[15]) & g01_b[14])); //final + assign g02ev[6] = (~((t01_b[12] | g01_b[13]) & g01_b[12])); + assign g02ev[5] = (~((t01_b[10] | g01_b[11]) & g01_b[10])); + assign g02ev[4] = (~((t01_b[8] | g01_b[9]) & g01_b[8])); + assign g02ev[3] = (~((t01_b[6] | g01_b[7]) & g01_b[6])); + assign g02ev[2] = (~((t01_b[4] | g01_b[5]) & g01_b[4])); + assign g02ev[1] = (~((t01_b[2] | g01_b[3]) & g01_b[2])); + assign g02ev[0] = (~((t01_b[0] | g01_b[1]) & g01_b[0])); + + assign t02ev[7] = (~((t01_b[14] | t01_b[15]) & g01_b[14])); //final + assign t02ev[6] = (~(t01_b[12] | t01_b[13])); + assign t02ev[5] = (~(t01_b[10] | t01_b[11])); + assign t02ev[4] = (~(t01_b[8] | t01_b[9])); + assign t02ev[3] = (~(t01_b[6] | t01_b[7])); + assign t02ev[2] = (~(t01_b[4] | t01_b[5])); + assign t02ev[1] = (~(t01_b[2] | t01_b[3])); + assign t02ev[0] = (~(t01_b[0] | t01_b[1])); + + assign g02ev_b[7] = (~(g02ev[7])); //new + assign g02ev_b[6] = (~(g02ev[6])); //new + assign g02ev_b[5] = (~(g02ev[5])); //new + assign g02ev_b[4] = (~(g02ev[4])); //new + assign g02ev_b[3] = (~(g02ev[3])); //new + assign g02ev_b[2] = (~(g02ev[2])); //new + assign g02ev_b[1] = (~(g02ev[1])); //new + + assign t02ev_b[7] = (~(t02ev[7])); //new + assign t02ev_b[6] = (~(t02ev[6])); //new + assign t02ev_b[5] = (~(t02ev[5])); //new + assign t02ev_b[4] = (~(t02ev[4])); //new + assign t02ev_b[3] = (~(t02ev[3])); //new + assign t02ev_b[2] = (~(t02ev[2])); //new + assign t02ev_b[1] = (~(t02ev[1])); //new + + ////##################################### + ////## replicating for global chain + ////##################################### + + assign glb_g04_e01_b = (~(g02ev[0] | (t02ev[0] & g02ev[1]))); + assign glb_g04_e23_b = (~(g02ev[2] | (t02ev[2] & g02ev[3]))); + assign glb_g04_e45_b = (~(g02ev[4] | (t02ev[4] & g02ev[5]))); + assign glb_g04_e67_b = (~(g02ev[6] | (t02ev[6] & g02ev[7]))); + assign glb_t04_e01_b = (~(t02ev[0] & t02ev[1])); + assign glb_t04_e23_b = (~(t02ev[2] & t02ev[3])); + assign glb_t04_e45_b = (~(t02ev[4] & t02ev[5])); + assign glb_t04_e67_b = (~(g02ev[6] | (t02ev[6] & t02ev[7]))); + + assign glb_g08_e03 = (~(glb_g04_e01_b & (glb_t04_e01_b | glb_g04_e23_b))); + assign glb_g08_e47 = (~(glb_g04_e45_b & (glb_t04_e45_b | glb_g04_e67_b))); + assign glb_t08_e03 = (~(glb_t04_e01_b | glb_t04_e23_b)); + assign glb_t08_e47 = (~(glb_g04_e45_b & (glb_t04_e45_b | glb_t04_e67_b))); + + assign glb_g16_e07_b = (~(glb_g08_e03 | (glb_t08_e03 & glb_g08_e47))); + assign glb_t16_e07_b = (~(glb_g08_e03 | (glb_t08_e03 & glb_t08_e47))); + + assign g16 = (~(glb_g16_e07_b)); //output + assign t16 = (~(glb_t16_e07_b)); //output + + ////##################################### + ////## group 4 // delayed for local chain ... reverse phase + ////##################################### + + assign g04ev[7] = (~(g02ev_b[7])); + assign g04ev[6] = (~(g02ev_b[6] & (t02ev_b[6] | g02ev_b[7]))); //final + assign g04ev[5] = (~(g02ev_b[5] & (t02ev_b[5] | g02ev_b[6]))); + assign g04ev[4] = (~(g02ev_b[4] & (t02ev_b[4] | g02ev_b[5]))); + assign g04ev[3] = (~(g02ev_b[3] & (t02ev_b[3] | g02ev_b[4]))); + assign g04ev[2] = (~(g02ev_b[2] & (t02ev_b[2] | g02ev_b[3]))); + assign g04ev[1] = (~(g02ev_b[1] & (t02ev_b[1] | g02ev_b[2]))); + + assign t04ev[7] = (~(t02ev_b[7])); + assign t04ev[6] = (~(g02ev_b[6] & (t02ev_b[6] | t02ev_b[7]))); //final + assign t04ev[5] = (~(t02ev_b[5] | t02ev_b[6])); + assign t04ev[4] = (~(t02ev_b[4] | t02ev_b[5])); + assign t04ev[3] = (~(t02ev_b[3] | t02ev_b[4])); + assign t04ev[2] = (~(t02ev_b[2] | t02ev_b[3])); + assign t04ev[1] = (~(t02ev_b[1] | t02ev_b[2])); + + ////##################################### + ////## group 8 + ////##################################### + + assign g08ev_b[7] = (~(g04ev[7])); + assign g08ev_b[6] = (~(g04ev[6])); + assign g08ev_b[5] = (~(g04ev[5] | (t04ev[5] & g04ev[7]))); //final + assign g08ev_b[4] = (~(g04ev[4] | (t04ev[4] & g04ev[6]))); //final + assign g08ev_b[3] = (~(g04ev[3] | (t04ev[3] & g04ev[5]))); + assign g08ev_b[2] = (~(g04ev[2] | (t04ev[2] & g04ev[4]))); + assign g08ev_b[1] = (~(g04ev[1] | (t04ev[1] & g04ev[3]))); + + assign t08ev_b[7] = (~(t04ev[7])); + assign t08ev_b[6] = (~(t04ev[6])); + assign t08ev_b[5] = (~(g04ev[5] | (t04ev[5] & t04ev[7]))); //final + assign t08ev_b[4] = (~(g04ev[4] | (t04ev[4] & t04ev[6]))); //final + assign t08ev_b[3] = (~(t04ev[3] & t04ev[5])); + assign t08ev_b[2] = (~(t04ev[2] & t04ev[4])); + assign t08ev_b[1] = (~(t04ev[1] & t04ev[3])); + + ////##################################### + ////## group 16 + ////##################################### + + assign g16ev[7] = (~(g08ev_b[7])); + assign g16ev[6] = (~(g08ev_b[6])); + assign g16ev[5] = (~(g08ev_b[5])); + assign g16ev[4] = (~(g08ev_b[4])); + assign g16ev[3] = (~(g08ev_b[3] & (t08ev_b[3] | g08ev_b[7]))); //final + assign g16ev[2] = (~(g08ev_b[2] & (t08ev_b[2] | g08ev_b[6]))); //final + assign g16ev[1] = (~(g08ev_b[1] & (t08ev_b[1] | g08ev_b[5]))); //final + + assign t16ev[7] = (~(t08ev_b[7])); + assign t16ev[6] = (~(t08ev_b[6])); + assign t16ev[5] = (~(t08ev_b[5])); + assign t16ev[4] = (~(t08ev_b[4])); + assign t16ev[3] = (~(g08ev_b[3] & (t08ev_b[3] | t08ev_b[7]))); //final + assign t16ev[2] = (~(g08ev_b[2] & (t08ev_b[2] | t08ev_b[6]))); //final + assign t16ev[1] = (~(g08ev_b[1] & (t08ev_b[1] | t08ev_b[5]))); //final + + ////##################################### + ////## group 16 delayed + ////##################################### + + assign c0_b[14] = (~(g16ev[7])); + assign c0_b[12] = (~(g16ev[6])); + assign c0_b[10] = (~(g16ev[5])); + assign c0_b[8] = (~(g16ev[4])); + assign c0_b[6] = (~(g16ev[3])); + assign c0_b[4] = (~(g16ev[2])); + assign c0_b[2] = (~(g16ev[1])); + + assign c1_b[14] = (~(t16ev[7])); + assign c1_b[12] = (~(t16ev[6])); + assign c1_b[10] = (~(t16ev[5])); + assign c1_b[8] = (~(t16ev[4])); + assign c1_b[6] = (~(t16ev[3])); + assign c1_b[4] = (~(t16ev[2])); + assign c1_b[2] = (~(t16ev[1])); + + assign c0_b[15] = (~(g01od[7])); + assign c0_b[13] = (~((t01od[6] & g16ev[7]) | g01od[6])); + assign c0_b[11] = (~((t01od[5] & g16ev[6]) | g01od[5])); + assign c0_b[9] = (~((t01od[4] & g16ev[5]) | g01od[4])); + assign c0_b[7] = (~((t01od[3] & g16ev[4]) | g01od[3])); + assign c0_b[5] = (~((t01od[2] & g16ev[3]) | g01od[2])); + assign c0_b[3] = (~((t01od[1] & g16ev[2]) | g01od[1])); + assign c0_b[1] = (~((t01od[0] & g16ev[1]) | g01od[0])); + + assign c1_b[15] = (~(t01od[7])); + assign c1_b[13] = (~((t01od[6] & t16ev[7]) | g01od[6])); + assign c1_b[11] = (~((t01od[5] & t16ev[6]) | g01od[5])); + assign c1_b[9] = (~((t01od[4] & t16ev[5]) | g01od[4])); + assign c1_b[7] = (~((t01od[3] & t16ev[4]) | g01od[3])); + assign c1_b[5] = (~((t01od[2] & t16ev[3]) | g01od[2])); + assign c1_b[3] = (~((t01od[1] & t16ev[2]) | g01od[1])); + assign c1_b[1] = (~((t01od[0] & t16ev[1]) | g01od[0])); + + ////##################################### + ////## sum before select + ////##################################### + + assign s0_raw[0] = (p01_b[0] ^ c0_b[1]); + assign s0_raw[1] = (p01_b[1] ^ c0_b[2]); + assign s0_raw[2] = (p01_b[2] ^ c0_b[3]); + assign s0_raw[3] = (p01_b[3] ^ c0_b[4]); + assign s0_raw[4] = (p01_b[4] ^ c0_b[5]); + assign s0_raw[5] = (p01_b[5] ^ c0_b[6]); + assign s0_raw[6] = (p01_b[6] ^ c0_b[7]); + assign s0_raw[7] = (p01_b[7] ^ c0_b[8]); + assign s0_raw[8] = (p01_b[8] ^ c0_b[9]); + assign s0_raw[9] = (p01_b[9] ^ c0_b[10]); + assign s0_raw[10] = (p01_b[10] ^ c0_b[11]); + assign s0_raw[11] = (p01_b[11] ^ c0_b[12]); + assign s0_raw[12] = (p01_b[12] ^ c0_b[13]); + assign s0_raw[13] = (p01_b[13] ^ c0_b[14]); + assign s0_raw[14] = (p01_b[14] ^ c0_b[15]); + assign s0_raw[15] = (~p01_b[15]); + + assign s1_raw[0] = (p01_b[0] ^ c1_b[1]); + assign s1_raw[1] = (p01_b[1] ^ c1_b[2]); + assign s1_raw[2] = (p01_b[2] ^ c1_b[3]); + assign s1_raw[3] = (p01_b[3] ^ c1_b[4]); + assign s1_raw[4] = (p01_b[4] ^ c1_b[5]); + assign s1_raw[5] = (p01_b[5] ^ c1_b[6]); + assign s1_raw[6] = (p01_b[6] ^ c1_b[7]); + assign s1_raw[7] = (p01_b[7] ^ c1_b[8]); + assign s1_raw[8] = (p01_b[8] ^ c1_b[9]); + assign s1_raw[9] = (p01_b[9] ^ c1_b[10]); + assign s1_raw[10] = (p01_b[10] ^ c1_b[11]); + assign s1_raw[11] = (p01_b[11] ^ c1_b[12]); + assign s1_raw[12] = (p01_b[12] ^ c1_b[13]); + assign s1_raw[13] = (p01_b[13] ^ c1_b[14]); + assign s1_raw[14] = (p01_b[14] ^ c1_b[15]); + assign s1_raw[15] = (~s0_raw[15]); + + ////##################################### + ////## sum after select + ////##################################### + + assign s0_x_b[0] = (~(s0_raw[0] & ci0_b)); + assign s0_y_b[0] = (~(s1_raw[0] & ci0)); + assign s1_x_b[0] = (~(s0_raw[0] & ci1_b)); + assign s1_y_b[0] = (~(s1_raw[0] & ci1)); + assign s0[0] = (~(s0_x_b[0] & s0_y_b[0])); + assign s1[0] = (~(s1_x_b[0] & s1_y_b[0])); + + assign s0_x_b[1] = (~(s0_raw[1] & ci0_b)); + assign s0_y_b[1] = (~(s1_raw[1] & ci0)); + assign s1_x_b[1] = (~(s0_raw[1] & ci1_b)); + assign s1_y_b[1] = (~(s1_raw[1] & ci1)); + assign s0[1] = (~(s0_x_b[1] & s0_y_b[1])); + assign s1[1] = (~(s1_x_b[1] & s1_y_b[1])); + + assign s0_x_b[2] = (~(s0_raw[2] & ci0_b)); + assign s0_y_b[2] = (~(s1_raw[2] & ci0)); + assign s1_x_b[2] = (~(s0_raw[2] & ci1_b)); + assign s1_y_b[2] = (~(s1_raw[2] & ci1)); + assign s0[2] = (~(s0_x_b[2] & s0_y_b[2])); + assign s1[2] = (~(s1_x_b[2] & s1_y_b[2])); + + assign s0_x_b[3] = (~(s0_raw[3] & ci0_b)); + assign s0_y_b[3] = (~(s1_raw[3] & ci0)); + assign s1_x_b[3] = (~(s0_raw[3] & ci1_b)); + assign s1_y_b[3] = (~(s1_raw[3] & ci1)); + assign s0[3] = (~(s0_x_b[3] & s0_y_b[3])); + assign s1[3] = (~(s1_x_b[3] & s1_y_b[3])); + + assign s0_x_b[4] = (~(s0_raw[4] & ci0_b)); + assign s0_y_b[4] = (~(s1_raw[4] & ci0)); + assign s1_x_b[4] = (~(s0_raw[4] & ci1_b)); + assign s1_y_b[4] = (~(s1_raw[4] & ci1)); + assign s0[4] = (~(s0_x_b[4] & s0_y_b[4])); + assign s1[4] = (~(s1_x_b[4] & s1_y_b[4])); + + assign s0_x_b[5] = (~(s0_raw[5] & ci0_b)); + assign s0_y_b[5] = (~(s1_raw[5] & ci0)); + assign s1_x_b[5] = (~(s0_raw[5] & ci1_b)); + assign s1_y_b[5] = (~(s1_raw[5] & ci1)); + assign s0[5] = (~(s0_x_b[5] & s0_y_b[5])); + assign s1[5] = (~(s1_x_b[5] & s1_y_b[5])); + + assign s0_x_b[6] = (~(s0_raw[6] & ci0_b)); + assign s0_y_b[6] = (~(s1_raw[6] & ci0)); + assign s1_x_b[6] = (~(s0_raw[6] & ci1_b)); + assign s1_y_b[6] = (~(s1_raw[6] & ci1)); + assign s0[6] = (~(s0_x_b[6] & s0_y_b[6])); + assign s1[6] = (~(s1_x_b[6] & s1_y_b[6])); + + assign s0_x_b[7] = (~(s0_raw[7] & ci0_b)); + assign s0_y_b[7] = (~(s1_raw[7] & ci0)); + assign s1_x_b[7] = (~(s0_raw[7] & ci1_b)); + assign s1_y_b[7] = (~(s1_raw[7] & ci1)); + assign s0[7] = (~(s0_x_b[7] & s0_y_b[7])); + assign s1[7] = (~(s1_x_b[7] & s1_y_b[7])); + + assign s0_x_b[8] = (~(s0_raw[8] & ci0_b)); + assign s0_y_b[8] = (~(s1_raw[8] & ci0)); + assign s1_x_b[8] = (~(s0_raw[8] & ci1_b)); + assign s1_y_b[8] = (~(s1_raw[8] & ci1)); + assign s0[8] = (~(s0_x_b[8] & s0_y_b[8])); + assign s1[8] = (~(s1_x_b[8] & s1_y_b[8])); + + assign s0_x_b[9] = (~(s0_raw[9] & ci0_b)); + assign s0_y_b[9] = (~(s1_raw[9] & ci0)); + assign s1_x_b[9] = (~(s0_raw[9] & ci1_b)); + assign s1_y_b[9] = (~(s1_raw[9] & ci1)); + assign s0[9] = (~(s0_x_b[9] & s0_y_b[9])); + assign s1[9] = (~(s1_x_b[9] & s1_y_b[9])); + + assign s0_x_b[10] = (~(s0_raw[10] & ci0_b)); + assign s0_y_b[10] = (~(s1_raw[10] & ci0)); + assign s1_x_b[10] = (~(s0_raw[10] & ci1_b)); + assign s1_y_b[10] = (~(s1_raw[10] & ci1)); + assign s0[10] = (~(s0_x_b[10] & s0_y_b[10])); + assign s1[10] = (~(s1_x_b[10] & s1_y_b[10])); + + assign s0_x_b[11] = (~(s0_raw[11] & ci0_b)); + assign s0_y_b[11] = (~(s1_raw[11] & ci0)); + assign s1_x_b[11] = (~(s0_raw[11] & ci1_b)); + assign s1_y_b[11] = (~(s1_raw[11] & ci1)); + assign s0[11] = (~(s0_x_b[11] & s0_y_b[11])); + assign s1[11] = (~(s1_x_b[11] & s1_y_b[11])); + + assign s0_x_b[12] = (~(s0_raw[12] & ci0_b)); + assign s0_y_b[12] = (~(s1_raw[12] & ci0)); + assign s1_x_b[12] = (~(s0_raw[12] & ci1_b)); + assign s1_y_b[12] = (~(s1_raw[12] & ci1)); + assign s0[12] = (~(s0_x_b[12] & s0_y_b[12])); + assign s1[12] = (~(s1_x_b[12] & s1_y_b[12])); + + assign s0_x_b[13] = (~(s0_raw[13] & ci0_b)); + assign s0_y_b[13] = (~(s1_raw[13] & ci0)); + assign s1_x_b[13] = (~(s0_raw[13] & ci1_b)); + assign s1_y_b[13] = (~(s1_raw[13] & ci1)); + assign s0[13] = (~(s0_x_b[13] & s0_y_b[13])); + assign s1[13] = (~(s1_x_b[13] & s1_y_b[13])); + + assign s0_x_b[14] = (~(s0_raw[14] & ci0_b)); + assign s0_y_b[14] = (~(s1_raw[14] & ci0)); + assign s1_x_b[14] = (~(s0_raw[14] & ci1_b)); + assign s1_y_b[14] = (~(s1_raw[14] & ci1)); + assign s0[14] = (~(s0_x_b[14] & s0_y_b[14])); + assign s1[14] = (~(s1_x_b[14] & s1_y_b[14])); + + assign s0_x_b[15] = (~(s0_raw[15] & ci0_b)); + assign s0_y_b[15] = (~(s1_raw[15] & ci0)); + assign s1_x_b[15] = (~(s0_raw[15] & ci1_b)); + assign s1_y_b[15] = (~(s1_raw[15] & ci1)); + assign s0[15] = (~(s0_x_b[15] & s0_y_b[15])); + assign s1[15] = (~(s1_x_b[15] & s1_y_b[15])); + +endmodule diff --git a/dev/verilog/work/fu_hc16pp_lsb.v b/dev/verilog/work/fu_hc16pp_lsb.v new file mode 100755 index 0000000..a18266b --- /dev/null +++ b/dev/verilog/work/fu_hc16pp_lsb.v @@ -0,0 +1,347 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + + `include "tri_a2o.vh" + + +module fu_hc16pp_lsb( + x, + y, + s0, + s1, + g16, + t16 +); + input [0:13] x; + input [0:12] y; + output [0:13] s0; + output [0:13] s1; + output g16; + output t16; + + parameter tiup = 1'b1; + parameter tidn = 1'b0; + + wire [0:12] g01_b; + wire [0:13] t01_b; + wire [0:13] p01_b; + wire [0:13] p01; + + wire [0:5] g01od; + wire [0:6] t01od; + + wire [0:6] g02ev; + wire [0:6] t02ev; + wire [1:6] g02ev_b; + wire [1:6] t02ev_b; + wire [1:6] g04ev; + wire [1:6] t04ev; + wire [1:6] g08ev_b; + wire [1:6] t08ev_b; + wire [1:6] g16ev; + wire [1:6] t16ev; + wire [1:12] c0_b; + wire [1:13] c1_b; + + wire glb_g04_e01_b; //new // rep glb + wire glb_g04_e23_b; + wire glb_g04_e45_b; + wire glb_g04_e67_b; + wire glb_t04_e01_b; //new // rep glb + wire glb_t04_e23_b; + wire glb_t04_e45_b; + wire glb_t04_e67_b; + wire glb_g08_e03; //new // rep glb + wire glb_g08_e47; + wire glb_t08_e03; + wire glb_t08_e47; + wire glb_g16_e07_b; //new // rep glb + wire glb_t16_e07_b; + + + + ////##################################### + ////## group 1 + ////##################################### + + assign g01_b[0] = (~(x[0] & y[0])); //critical + assign g01_b[1] = (~(x[1] & y[1])); //critical + assign g01_b[2] = (~(x[2] & y[2])); //critical + assign g01_b[3] = (~(x[3] & y[3])); //critical + assign g01_b[4] = (~(x[4] & y[4])); //critical + assign g01_b[5] = (~(x[5] & y[5])); //critical + assign g01_b[6] = (~(x[6] & y[6])); //critical + assign g01_b[7] = (~(x[7] & y[7])); //critical + assign g01_b[8] = (~(x[8] & y[8])); //critical + assign g01_b[9] = (~(x[9] & y[9])); //critical + assign g01_b[10] = (~(x[10] & y[10])); //critical + assign g01_b[11] = (~(x[11] & y[11])); //critical + assign g01_b[12] = (~(x[12] & y[12])); //critical + + assign t01_b[0] = (~(x[0] | y[0])); //critical + assign t01_b[1] = (~(x[1] | y[1])); //critical + assign t01_b[2] = (~(x[2] | y[2])); //critical + assign t01_b[3] = (~(x[3] | y[3])); //critical + assign t01_b[4] = (~(x[4] | y[4])); //critical + assign t01_b[5] = (~(x[5] | y[5])); //critical + assign t01_b[6] = (~(x[6] | y[6])); //critical + assign t01_b[7] = (~(x[7] | y[7])); //critical + assign t01_b[8] = (~(x[8] | y[8])); //critical + assign t01_b[9] = (~(x[9] | y[9])); //critical + assign t01_b[10] = (~(x[10] | y[10])); //critical + assign t01_b[11] = (~(x[11] | y[11])); //critical + assign t01_b[12] = (~(x[12] | y[12])); //critical + assign t01_b[13] = (~(x[13])); //critical + + assign p01[0] = (x[0] ^ y[0]); //not critical + assign p01[1] = (x[1] ^ y[1]); //not critical + assign p01[2] = (x[2] ^ y[2]); //not critical + assign p01[3] = (x[3] ^ y[3]); //not critical + assign p01[4] = (x[4] ^ y[4]); //not critical + assign p01[5] = (x[5] ^ y[5]); //not critical + assign p01[6] = (x[6] ^ y[6]); //not critical + assign p01[7] = (x[7] ^ y[7]); //not critical + assign p01[8] = (x[8] ^ y[8]); //not critical + assign p01[9] = (x[9] ^ y[9]); //not critical + assign p01[10] = (x[10] ^ y[10]); //not critical + assign p01[11] = (x[11] ^ y[11]); //not critical + assign p01[12] = (x[12] ^ y[12]); //not critical + assign p01[13] = (~p01_b[13]); + + assign p01_b[0] = (~(p01[0])); //not critical + assign p01_b[1] = (~(p01[1])); //not critical + assign p01_b[2] = (~(p01[2])); //not critical + assign p01_b[3] = (~(p01[3])); //not critical + assign p01_b[4] = (~(p01[4])); //not critical + assign p01_b[5] = (~(p01[5])); //not critical + assign p01_b[6] = (~(p01[6])); //not critical + assign p01_b[7] = (~(p01[7])); //not critical + assign p01_b[8] = (~(p01[8])); //not critical + assign p01_b[9] = (~(p01[9])); //not critical + assign p01_b[10] = (~(p01[10])); //not critical + assign p01_b[11] = (~(p01[11])); //not critical + assign p01_b[12] = (~(p01[12])); //not critical + assign p01_b[13] = (~(x[13])); //not critical + + assign g01od[0] = (~g01_b[1]); + assign g01od[1] = (~g01_b[3]); + assign g01od[2] = (~g01_b[5]); + assign g01od[3] = (~g01_b[7]); + assign g01od[4] = (~g01_b[9]); + assign g01od[5] = (~g01_b[11]); + + assign t01od[0] = (~t01_b[1]); + assign t01od[1] = (~t01_b[3]); + assign t01od[2] = (~t01_b[5]); + assign t01od[3] = (~t01_b[7]); + assign t01od[4] = (~t01_b[9]); + assign t01od[5] = (~t01_b[11]); + assign t01od[6] = (~t01_b[13]); + + ////##################################### + ////## group 2 // local and global shared + ////##################################### + + assign g02ev[6] = (~(g01_b[12])); //final + assign g02ev[5] = (~((t01_b[10] | g01_b[11]) & g01_b[10])); + assign g02ev[4] = (~((t01_b[8] | g01_b[9]) & g01_b[8])); + assign g02ev[3] = (~((t01_b[6] | g01_b[7]) & g01_b[6])); + assign g02ev[2] = (~((t01_b[4] | g01_b[5]) & g01_b[4])); + assign g02ev[1] = (~((t01_b[2] | g01_b[3]) & g01_b[2])); + assign g02ev[0] = (~((t01_b[0] | g01_b[1]) & g01_b[0])); + + assign t02ev[6] = (~((t01_b[12] | t01_b[13]) & g01_b[12])); //final + assign t02ev[5] = (~((t01_b[10] | t01_b[11]))); + assign t02ev[4] = (~((t01_b[8] | t01_b[9]))); + assign t02ev[3] = (~((t01_b[6] | t01_b[7]))); + assign t02ev[2] = (~((t01_b[4] | t01_b[5]))); + assign t02ev[1] = (~((t01_b[2] | t01_b[3]))); + assign t02ev[0] = (~((t01_b[0] | t01_b[1]))); + + assign g02ev_b[6] = (~(g02ev[6])); //new + assign g02ev_b[5] = (~(g02ev[5])); //new + assign g02ev_b[4] = (~(g02ev[4])); //new + assign g02ev_b[3] = (~(g02ev[3])); //new + assign g02ev_b[2] = (~(g02ev[2])); //new + assign g02ev_b[1] = (~(g02ev[1])); //new + + assign t02ev_b[6] = (~(t02ev[6])); //new + assign t02ev_b[5] = (~(t02ev[5])); //new + assign t02ev_b[4] = (~(t02ev[4])); //new + assign t02ev_b[3] = (~(t02ev[3])); //new + assign t02ev_b[2] = (~(t02ev[2])); //new + assign t02ev_b[1] = (~(t02ev[1])); //new + + ////##################################### + ////## replicating for global chain + ////##################################### + + assign glb_g04_e01_b = (~(g02ev[0] | (t02ev[0] & g02ev[1]))); + assign glb_g04_e23_b = (~(g02ev[2] | (t02ev[2] & g02ev[3]))); + assign glb_g04_e45_b = (~(g02ev[4] | (t02ev[4] & g02ev[5]))); + assign glb_g04_e67_b = (~(g02ev[6])); + assign glb_t04_e01_b = (~(t02ev[0] & t02ev[1])); + assign glb_t04_e23_b = (~(t02ev[2] & t02ev[3])); + assign glb_t04_e45_b = (~(t02ev[4] & t02ev[5])); + assign glb_t04_e67_b = (~(t02ev[6])); + + assign glb_g08_e03 = (~(glb_g04_e01_b & (glb_t04_e01_b | glb_g04_e23_b))); + assign glb_g08_e47 = (~(glb_g04_e45_b & (glb_t04_e45_b | glb_g04_e67_b))); + assign glb_t08_e03 = (~(glb_t04_e01_b | glb_t04_e23_b)); + assign glb_t08_e47 = (~(glb_g04_e45_b & (glb_t04_e45_b | glb_t04_e67_b))); + + assign glb_g16_e07_b = (~(glb_g08_e03 | (glb_t08_e03 & glb_g08_e47))); + assign glb_t16_e07_b = (~(glb_g08_e03 | (glb_t08_e03 & glb_t08_e47))); + + assign g16 = (~(glb_g16_e07_b)); //output + assign t16 = (~(glb_t16_e07_b)); //output + + ////##################################### + ////## group 4 + ////##################################### + + assign g04ev[6] = (~(g02ev_b[6])); + assign g04ev[5] = (~((t02ev_b[5] | g02ev_b[6]) & g02ev_b[5])); //final + assign g04ev[4] = (~((t02ev_b[4] | g02ev_b[5]) & g02ev_b[4])); + assign g04ev[3] = (~((t02ev_b[3] | g02ev_b[4]) & g02ev_b[3])); + assign g04ev[2] = (~((t02ev_b[2] | g02ev_b[3]) & g02ev_b[2])); + assign g04ev[1] = (~((t02ev_b[1] | g02ev_b[2]) & g02ev_b[1])); + + assign t04ev[6] = (~(t02ev_b[6])); + assign t04ev[5] = (~((t02ev_b[5] | t02ev_b[6]) & g02ev_b[5])); //final + assign t04ev[4] = (~(t02ev_b[4] | t02ev_b[5])); + assign t04ev[3] = (~(t02ev_b[3] | t02ev_b[4])); + assign t04ev[2] = (~(t02ev_b[2] | t02ev_b[3])); + assign t04ev[1] = (~(t02ev_b[1] | t02ev_b[2])); + + ////##################################### + ////## group 8 + ////##################################### + + assign g08ev_b[6] = (~(g04ev[6])); + assign g08ev_b[5] = (~(g04ev[5])); + assign g08ev_b[4] = (~(g04ev[4] | (t04ev[4] & g04ev[6]))); //final + assign g08ev_b[3] = (~(g04ev[3] | (t04ev[3] & g04ev[5]))); //final + assign g08ev_b[2] = (~(g04ev[2] | (t04ev[2] & g04ev[4]))); + assign g08ev_b[1] = (~(g04ev[1] | (t04ev[1] & g04ev[3]))); + + assign t08ev_b[6] = (~(t04ev[6])); + assign t08ev_b[5] = (~(t04ev[5])); + assign t08ev_b[4] = (~(g04ev[4] | (t04ev[4] & t04ev[6]))); //final + assign t08ev_b[3] = (~(g04ev[3] | (t04ev[3] & t04ev[5]))); //final + assign t08ev_b[2] = (~(t04ev[2] & t04ev[4])); + assign t08ev_b[1] = (~(t04ev[1] & t04ev[3])); + + ////##################################### + ////## group 16 + ////##################################### + + assign g16ev[6] = (~(g08ev_b[6])); + assign g16ev[5] = (~(g08ev_b[5])); + assign g16ev[4] = (~(g08ev_b[4])); + assign g16ev[3] = (~(g08ev_b[3])); + assign g16ev[2] = (~((t08ev_b[2] | g08ev_b[6]) & g08ev_b[2])); //final + assign g16ev[1] = (~((t08ev_b[1] | g08ev_b[5]) & g08ev_b[1])); //final + + assign t16ev[6] = (~(t08ev_b[6])); + assign t16ev[5] = (~(t08ev_b[5])); + assign t16ev[4] = (~(t08ev_b[4])); + assign t16ev[3] = (~(t08ev_b[3])); + assign t16ev[2] = (~((t08ev_b[2] | t08ev_b[6]) & g08ev_b[2])); //final + assign t16ev[1] = (~((t08ev_b[1] | t08ev_b[5]) & g08ev_b[1])); //final + + ////##################################### + ////## group 16 delayed + ////##################################### + + assign c0_b[12] = (~(g16ev[6])); + assign c0_b[10] = (~(g16ev[5])); + assign c0_b[8] = (~(g16ev[4])); + assign c0_b[6] = (~(g16ev[3])); + assign c0_b[4] = (~(g16ev[2])); + assign c0_b[2] = (~(g16ev[1])); + + assign c1_b[12] = (~(t16ev[6])); + assign c1_b[10] = (~(t16ev[5])); + assign c1_b[8] = (~(t16ev[4])); + assign c1_b[6] = (~(t16ev[3])); + assign c1_b[4] = (~(t16ev[2])); + assign c1_b[2] = (~(t16ev[1])); + + assign c0_b[11] = (~((t01od[5] & g16ev[6]) | g01od[5])); + assign c0_b[9] = (~((t01od[4] & g16ev[5]) | g01od[4])); + assign c0_b[7] = (~((t01od[3] & g16ev[4]) | g01od[3])); + assign c0_b[5] = (~((t01od[2] & g16ev[3]) | g01od[2])); + assign c0_b[3] = (~((t01od[1] & g16ev[2]) | g01od[1])); + assign c0_b[1] = (~((t01od[0] & g16ev[1]) | g01od[0])); + + assign c1_b[13] = (~(t01od[6])); + assign c1_b[11] = (~((t01od[5] & t16ev[6]) | g01od[5])); + assign c1_b[9] = (~((t01od[4] & t16ev[5]) | g01od[4])); + assign c1_b[7] = (~((t01od[3] & t16ev[4]) | g01od[3])); + assign c1_b[5] = (~((t01od[2] & t16ev[3]) | g01od[2])); + assign c1_b[3] = (~((t01od[1] & t16ev[2]) | g01od[1])); + assign c1_b[1] = (~((t01od[0] & t16ev[1]) | g01od[0])); + + ////##################################### + ////## sum + ////##################################### + + assign s0[0] = (p01_b[0] ^ c0_b[1]); + assign s0[1] = (p01_b[1] ^ c0_b[2]); + assign s0[2] = (p01_b[2] ^ c0_b[3]); + assign s0[3] = (p01_b[3] ^ c0_b[4]); + assign s0[4] = (p01_b[4] ^ c0_b[5]); + assign s0[5] = (p01_b[5] ^ c0_b[6]); + assign s0[6] = (p01_b[6] ^ c0_b[7]); + assign s0[7] = (p01_b[7] ^ c0_b[8]); + assign s0[8] = (p01_b[8] ^ c0_b[9]); + assign s0[9] = (p01_b[9] ^ c0_b[10]); + assign s0[10] = (p01_b[10] ^ c0_b[11]); + assign s0[11] = (p01_b[11] ^ c0_b[12]); + assign s0[12] = (~(p01_b[12])); + assign s0[13] = (~(p01_b[13])); + + assign s1[0] = (p01_b[0] ^ c1_b[1]); + assign s1[1] = (p01_b[1] ^ c1_b[2]); + assign s1[2] = (p01_b[2] ^ c1_b[3]); + assign s1[3] = (p01_b[3] ^ c1_b[4]); + assign s1[4] = (p01_b[4] ^ c1_b[5]); + assign s1[5] = (p01_b[5] ^ c1_b[6]); + assign s1[6] = (p01_b[6] ^ c1_b[7]); + assign s1[7] = (p01_b[7] ^ c1_b[8]); + assign s1[8] = (p01_b[8] ^ c1_b[9]); + assign s1[9] = (p01_b[9] ^ c1_b[10]); + assign s1[10] = (p01_b[10] ^ c1_b[11]); + assign s1[11] = (p01_b[11] ^ c1_b[12]); + assign s1[12] = (p01_b[12] ^ c1_b[13]); + assign s1[13] = (~(p01[13])); + +endmodule diff --git a/dev/verilog/work/fu_hc16pp_msb.v b/dev/verilog/work/fu_hc16pp_msb.v new file mode 100755 index 0000000..9279168 --- /dev/null +++ b/dev/verilog/work/fu_hc16pp_msb.v @@ -0,0 +1,508 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// this version handles he psuedo bit + + `include "tri_a2o.vh" + + +module fu_hc16pp_msb( + x, + y, + ci0, + ci0_b, + ci1, + ci1_b, + s0, + s1, + g16, + t16 +); + input [0:15] x; + input [0:15] y; + input ci0; + input ci0_b; + input ci1; + input ci1_b; + output [0:15] s0; + output [0:15] s1; + output g16; + output t16; + + parameter tiup = 1'b1; + parameter tidn = 1'b0; + + wire [1:15] g01_b; + wire [0:15] t01_b; + wire [0:15] p01_b; + wire [0:15] p01; + wire [0:7] g01od; + wire [0:7] t01od; + wire [0:7] g02ev; + wire [0:7] t02ev; + wire [1:7] g02ev_b; + wire [1:7] t02ev_b; + wire [1:7] g04ev; + wire [1:7] t04ev; + wire [1:7] g08ev_b; + wire [1:7] t08ev_b; + wire [1:7] g16ev; + wire [1:7] t16ev; + wire [1:15] c0_b; + wire [1:15] c1_b; + wire [0:15] s0_raw; + wire [0:15] s1_raw; + wire [0:15] s0_x_b; + wire [0:15] s0_y_b; + wire [0:15] s1_x_b; + wire [0:15] s1_y_b; + + wire glb_g04_e01_b; //new // rep glb + wire glb_g04_e23_b; + wire glb_g04_e45_b; + wire glb_g04_e67_b; + wire glb_t04_e01_b; //new // rep glb + wire glb_t04_e23_b; + wire glb_t04_e45_b; + wire glb_t04_e67_b; + wire glb_g08_e03; //new // rep glb + wire glb_g08_e47; + wire glb_t08_e03; + wire glb_t08_e47; + wire glb_g16_e07_b; //new // rep glb + wire glb_t16_e07_b; + + + + ////##################################### + ////## group 1 + ////##################################### + + //hc00_g01: g01_b( 0) <= tiup ; --critical <=== different then MID + assign g01_b[1] = (~(x[1] & y[1])); //critical + assign g01_b[2] = (~(x[2] & y[2])); //critical + assign g01_b[3] = (~(x[3] & y[3])); //critical + assign g01_b[4] = (~(x[4] & y[4])); //critical + assign g01_b[5] = (~(x[5] & y[5])); //critical + assign g01_b[6] = (~(x[6] & y[6])); //critical + assign g01_b[7] = (~(x[7] & y[7])); //critical + assign g01_b[8] = (~(x[8] & y[8])); //critical + assign g01_b[9] = (~(x[9] & y[9])); //critical + assign g01_b[10] = (~(x[10] & y[10])); //critical + assign g01_b[11] = (~(x[11] & y[11])); //critical + assign g01_b[12] = (~(x[12] & y[12])); //critical + assign g01_b[13] = (~(x[13] & y[13])); //critical + assign g01_b[14] = (~(x[14] & y[14])); //critical + assign g01_b[15] = (~(x[15] & y[15])); //critical + + assign t01_b[0] = (~(x[0] & y[0])); //critical <==== different then MID + assign t01_b[1] = (~(x[1] | y[1])); //critical + assign t01_b[2] = (~(x[2] | y[2])); //critical + assign t01_b[3] = (~(x[3] | y[3])); //critical + assign t01_b[4] = (~(x[4] | y[4])); //critical + assign t01_b[5] = (~(x[5] | y[5])); //critical + assign t01_b[6] = (~(x[6] | y[6])); //critical + assign t01_b[7] = (~(x[7] | y[7])); //critical + assign t01_b[8] = (~(x[8] | y[8])); //critical + assign t01_b[9] = (~(x[9] | y[9])); //critical + assign t01_b[10] = (~(x[10] | y[10])); //critical + assign t01_b[11] = (~(x[11] | y[11])); //critical + assign t01_b[12] = (~(x[12] | y[12])); //critical + assign t01_b[13] = (~(x[13] | y[13])); //critical + assign t01_b[14] = (~(x[14] | y[14])); //critical + assign t01_b[15] = (~(x[15] | y[15])); //critical + + assign p01[0] = (~(x[0] ^ y[0])); //not critical <==== different than MID + assign p01[1] = (x[1] ^ y[1]); //not critical + assign p01[2] = (x[2] ^ y[2]); //not critical + assign p01[3] = (x[3] ^ y[3]); //not critical + assign p01[4] = (x[4] ^ y[4]); //not critical + assign p01[5] = (x[5] ^ y[5]); //not critical + assign p01[6] = (x[6] ^ y[6]); //not critical + assign p01[7] = (x[7] ^ y[7]); //not critical + assign p01[8] = (x[8] ^ y[8]); //not critical + assign p01[9] = (x[9] ^ y[9]); //not critical + assign p01[10] = (x[10] ^ y[10]); //not critical + assign p01[11] = (x[11] ^ y[11]); //not critical + assign p01[12] = (x[12] ^ y[12]); //not critical + assign p01[13] = (x[13] ^ y[13]); //not critical + assign p01[14] = (x[14] ^ y[14]); //not critical + assign p01[15] = (x[15] ^ y[15]); //not critical + + assign p01_b[0] = (~(p01[0])); //not critical + assign p01_b[1] = (~(p01[1])); //not critical + assign p01_b[2] = (~(p01[2])); //not critical + assign p01_b[3] = (~(p01[3])); //not critical + assign p01_b[4] = (~(p01[4])); //not critical + assign p01_b[5] = (~(p01[5])); //not critical + assign p01_b[6] = (~(p01[6])); //not critical + assign p01_b[7] = (~(p01[7])); //not critical + assign p01_b[8] = (~(p01[8])); //not critical + assign p01_b[9] = (~(p01[9])); //not critical + assign p01_b[10] = (~(p01[10])); //not critical + assign p01_b[11] = (~(p01[11])); //not critical + assign p01_b[12] = (~(p01[12])); //not critical + assign p01_b[13] = (~(p01[13])); //not critical + assign p01_b[14] = (~(p01[14])); //not critical + assign p01_b[15] = (~(p01[15])); //not critical + + assign g01od[0] = (~g01_b[1]); + assign g01od[1] = (~g01_b[3]); + assign g01od[2] = (~g01_b[5]); + assign g01od[3] = (~g01_b[7]); + assign g01od[4] = (~g01_b[9]); + assign g01od[5] = (~g01_b[11]); + assign g01od[6] = (~g01_b[13]); + assign g01od[7] = (~g01_b[15]); + + assign t01od[0] = (~t01_b[1]); + assign t01od[1] = (~t01_b[3]); + assign t01od[2] = (~t01_b[5]); + assign t01od[3] = (~t01_b[7]); + assign t01od[4] = (~t01_b[9]); + assign t01od[5] = (~t01_b[11]); + assign t01od[6] = (~t01_b[13]); + assign t01od[7] = (~t01_b[15]); + + ////##################################### + ////## group 2 + ////##################################### + + assign g02ev[7] = (~((t01_b[14] | g01_b[15]) & g01_b[14])); //final + assign g02ev[6] = (~((t01_b[12] | g01_b[13]) & g01_b[12])); + assign g02ev[5] = (~((t01_b[10] | g01_b[11]) & g01_b[10])); + assign g02ev[4] = (~((t01_b[8] | g01_b[9]) & g01_b[8])); + assign g02ev[3] = (~((t01_b[6] | g01_b[7]) & g01_b[6])); + assign g02ev[2] = (~((t01_b[4] | g01_b[5]) & g01_b[4])); + assign g02ev[1] = (~((t01_b[2] | g01_b[3]) & g01_b[2])); + assign g02ev[0] = (~(t01_b[0] | g01_b[1])); // <==== different than MID + + assign t02ev[7] = (~((t01_b[14] | t01_b[15]) & g01_b[14])); //final + assign t02ev[6] = (~(t01_b[12] | t01_b[13])); + assign t02ev[5] = (~(t01_b[10] | t01_b[11])); + assign t02ev[4] = (~(t01_b[8] | t01_b[9])); + assign t02ev[3] = (~(t01_b[6] | t01_b[7])); + assign t02ev[2] = (~(t01_b[4] | t01_b[5])); + assign t02ev[1] = (~(t01_b[2] | t01_b[3])); + assign t02ev[0] = (~(t01_b[0] | t01_b[1])); + + assign g02ev_b[7] = (~(g02ev[7])); //new + assign g02ev_b[6] = (~(g02ev[6])); //new + assign g02ev_b[5] = (~(g02ev[5])); //new + assign g02ev_b[4] = (~(g02ev[4])); //new + assign g02ev_b[3] = (~(g02ev[3])); //new + assign g02ev_b[2] = (~(g02ev[2])); //new + assign g02ev_b[1] = (~(g02ev[1])); //new + + assign t02ev_b[7] = (~(t02ev[7])); //new + assign t02ev_b[6] = (~(t02ev[6])); //new + assign t02ev_b[5] = (~(t02ev[5])); //new + assign t02ev_b[4] = (~(t02ev[4])); //new + assign t02ev_b[3] = (~(t02ev[3])); //new + assign t02ev_b[2] = (~(t02ev[2])); //new + assign t02ev_b[1] = (~(t02ev[1])); //new + + ////##################################### + ////## replicating for global chain + ////##################################### + + assign glb_g04_e01_b = (~(g02ev[0] | (t02ev[0] & g02ev[1]))); + assign glb_g04_e23_b = (~(g02ev[2] | (t02ev[2] & g02ev[3]))); + assign glb_g04_e45_b = (~(g02ev[4] | (t02ev[4] & g02ev[5]))); + assign glb_g04_e67_b = (~(g02ev[6] | (t02ev[6] & g02ev[7]))); + assign glb_t04_e01_b = (~(t02ev[0] & t02ev[1])); + assign glb_t04_e23_b = (~(t02ev[2] & t02ev[3])); + assign glb_t04_e45_b = (~(t02ev[4] & t02ev[5])); + assign glb_t04_e67_b = (~(g02ev[6] | (t02ev[6] & t02ev[7]))); + + assign glb_g08_e03 = (~(glb_g04_e01_b & (glb_t04_e01_b | glb_g04_e23_b))); + assign glb_g08_e47 = (~(glb_g04_e45_b & (glb_t04_e45_b | glb_g04_e67_b))); + assign glb_t08_e03 = (~(glb_t04_e01_b | glb_t04_e23_b)); + assign glb_t08_e47 = (~(glb_g04_e45_b & (glb_t04_e45_b | glb_t04_e67_b))); + + assign glb_g16_e07_b = (~(glb_g08_e03 | (glb_t08_e03 & glb_g08_e47))); + assign glb_t16_e07_b = (~(glb_g08_e03 | (glb_t08_e03 & glb_t08_e47))); + + assign g16 = (~(glb_g16_e07_b)); //output + assign t16 = (~(glb_t16_e07_b)); //output + + ////##################################### + ////## group 4 // delayed for local chain ... reverse phase + ////##################################### + + assign g04ev[7] = (~(g02ev_b[7])); + assign g04ev[6] = (~(g02ev_b[6] & (t02ev_b[6] | g02ev_b[7]))); //final + assign g04ev[5] = (~(g02ev_b[5] & (t02ev_b[5] | g02ev_b[6]))); + assign g04ev[4] = (~(g02ev_b[4] & (t02ev_b[4] | g02ev_b[5]))); + assign g04ev[3] = (~(g02ev_b[3] & (t02ev_b[3] | g02ev_b[4]))); + assign g04ev[2] = (~(g02ev_b[2] & (t02ev_b[2] | g02ev_b[3]))); + assign g04ev[1] = (~(g02ev_b[1] & (t02ev_b[1] | g02ev_b[2]))); + + assign t04ev[7] = (~(t02ev_b[7])); + assign t04ev[6] = (~(g02ev_b[6] & (t02ev_b[6] | t02ev_b[7]))); //final + assign t04ev[5] = (~(t02ev_b[5] | t02ev_b[6])); + assign t04ev[4] = (~(t02ev_b[4] | t02ev_b[5])); + assign t04ev[3] = (~(t02ev_b[3] | t02ev_b[4])); + assign t04ev[2] = (~(t02ev_b[2] | t02ev_b[3])); + assign t04ev[1] = (~(t02ev_b[1] | t02ev_b[2])); + + ////##################################### + ////## group 8 + ////##################################### + + assign g08ev_b[7] = (~(g04ev[7])); + assign g08ev_b[6] = (~(g04ev[6])); + assign g08ev_b[5] = (~(g04ev[5] | (t04ev[5] & g04ev[7]))); //final + assign g08ev_b[4] = (~(g04ev[4] | (t04ev[4] & g04ev[6]))); //final + assign g08ev_b[3] = (~(g04ev[3] | (t04ev[3] & g04ev[5]))); + assign g08ev_b[2] = (~(g04ev[2] | (t04ev[2] & g04ev[4]))); + assign g08ev_b[1] = (~(g04ev[1] | (t04ev[1] & g04ev[3]))); + + assign t08ev_b[7] = (~(t04ev[7])); + assign t08ev_b[6] = (~(t04ev[6])); + assign t08ev_b[5] = (~(g04ev[5] | (t04ev[5] & t04ev[7]))); //final + assign t08ev_b[4] = (~(g04ev[4] | (t04ev[4] & t04ev[6]))); //final + assign t08ev_b[3] = (~(t04ev[3] & t04ev[5])); + assign t08ev_b[2] = (~(t04ev[2] & t04ev[4])); + assign t08ev_b[1] = (~(t04ev[1] & t04ev[3])); + + ////##################################### + ////## group 16 + ////##################################### + + assign g16ev[7] = (~(g08ev_b[7])); + assign g16ev[6] = (~(g08ev_b[6])); + assign g16ev[5] = (~(g08ev_b[5])); + assign g16ev[4] = (~(g08ev_b[4])); + assign g16ev[3] = (~(g08ev_b[3] & (t08ev_b[3] | g08ev_b[7]))); //final + assign g16ev[2] = (~(g08ev_b[2] & (t08ev_b[2] | g08ev_b[6]))); //final + assign g16ev[1] = (~(g08ev_b[1] & (t08ev_b[1] | g08ev_b[5]))); //final + + assign t16ev[7] = (~(t08ev_b[7])); + assign t16ev[6] = (~(t08ev_b[6])); + assign t16ev[5] = (~(t08ev_b[5])); + assign t16ev[4] = (~(t08ev_b[4])); + assign t16ev[3] = (~(g08ev_b[3] & (t08ev_b[3] | t08ev_b[7]))); //final + assign t16ev[2] = (~(g08ev_b[2] & (t08ev_b[2] | t08ev_b[6]))); //final + assign t16ev[1] = (~(g08ev_b[1] & (t08ev_b[1] | t08ev_b[5]))); //final + + ////##################################### + ////## group 16 delayed + ////##################################### + + assign c0_b[14] = (~(g16ev[7])); + assign c0_b[12] = (~(g16ev[6])); + assign c0_b[10] = (~(g16ev[5])); + assign c0_b[8] = (~(g16ev[4])); + assign c0_b[6] = (~(g16ev[3])); + assign c0_b[4] = (~(g16ev[2])); + assign c0_b[2] = (~(g16ev[1])); + + assign c1_b[14] = (~(t16ev[7])); + assign c1_b[12] = (~(t16ev[6])); + assign c1_b[10] = (~(t16ev[5])); + assign c1_b[8] = (~(t16ev[4])); + assign c1_b[6] = (~(t16ev[3])); + assign c1_b[4] = (~(t16ev[2])); + assign c1_b[2] = (~(t16ev[1])); + + assign c0_b[15] = (~(g01od[7])); + assign c0_b[13] = (~((t01od[6] & g16ev[7]) | g01od[6])); + assign c0_b[11] = (~((t01od[5] & g16ev[6]) | g01od[5])); + assign c0_b[9] = (~((t01od[4] & g16ev[5]) | g01od[4])); + assign c0_b[7] = (~((t01od[3] & g16ev[4]) | g01od[3])); + assign c0_b[5] = (~((t01od[2] & g16ev[3]) | g01od[2])); + assign c0_b[3] = (~((t01od[1] & g16ev[2]) | g01od[1])); + assign c0_b[1] = (~((t01od[0] & g16ev[1]) | g01od[0])); + + assign c1_b[15] = (~(t01od[7])); + assign c1_b[13] = (~((t01od[6] & t16ev[7]) | g01od[6])); + assign c1_b[11] = (~((t01od[5] & t16ev[6]) | g01od[5])); + assign c1_b[9] = (~((t01od[4] & t16ev[5]) | g01od[4])); + assign c1_b[7] = (~((t01od[3] & t16ev[4]) | g01od[3])); + assign c1_b[5] = (~((t01od[2] & t16ev[3]) | g01od[2])); + assign c1_b[3] = (~((t01od[1] & t16ev[2]) | g01od[1])); + assign c1_b[1] = (~((t01od[0] & t16ev[1]) | g01od[0])); + + ////##################################### + ////## sum before select + ////##################################### + + assign s0_raw[0] = (p01_b[0] ^ c0_b[1]); + assign s0_raw[1] = (p01_b[1] ^ c0_b[2]); + assign s0_raw[2] = (p01_b[2] ^ c0_b[3]); + assign s0_raw[3] = (p01_b[3] ^ c0_b[4]); + assign s0_raw[4] = (p01_b[4] ^ c0_b[5]); + assign s0_raw[5] = (p01_b[5] ^ c0_b[6]); + assign s0_raw[6] = (p01_b[6] ^ c0_b[7]); + assign s0_raw[7] = (p01_b[7] ^ c0_b[8]); + assign s0_raw[8] = (p01_b[8] ^ c0_b[9]); + assign s0_raw[9] = (p01_b[9] ^ c0_b[10]); + assign s0_raw[10] = (p01_b[10] ^ c0_b[11]); + assign s0_raw[11] = (p01_b[11] ^ c0_b[12]); + assign s0_raw[12] = (p01_b[12] ^ c0_b[13]); + assign s0_raw[13] = (p01_b[13] ^ c0_b[14]); + assign s0_raw[14] = (p01_b[14] ^ c0_b[15]); + assign s0_raw[15] = (~p01_b[15]); + + assign s1_raw[0] = (p01_b[0] ^ c1_b[1]); + assign s1_raw[1] = (p01_b[1] ^ c1_b[2]); + assign s1_raw[2] = (p01_b[2] ^ c1_b[3]); + assign s1_raw[3] = (p01_b[3] ^ c1_b[4]); + assign s1_raw[4] = (p01_b[4] ^ c1_b[5]); + assign s1_raw[5] = (p01_b[5] ^ c1_b[6]); + assign s1_raw[6] = (p01_b[6] ^ c1_b[7]); + assign s1_raw[7] = (p01_b[7] ^ c1_b[8]); + assign s1_raw[8] = (p01_b[8] ^ c1_b[9]); + assign s1_raw[9] = (p01_b[9] ^ c1_b[10]); + assign s1_raw[10] = (p01_b[10] ^ c1_b[11]); + assign s1_raw[11] = (p01_b[11] ^ c1_b[12]); + assign s1_raw[12] = (p01_b[12] ^ c1_b[13]); + assign s1_raw[13] = (p01_b[13] ^ c1_b[14]); + assign s1_raw[14] = (p01_b[14] ^ c1_b[15]); + assign s1_raw[15] = (~s0_raw[15]); + + ////##################################### + ////## sum after select + ////##################################### + + assign s0_x_b[0] = (~(s0_raw[0] & ci0_b)); + assign s0_y_b[0] = (~(s1_raw[0] & ci0)); + assign s1_x_b[0] = (~(s0_raw[0] & ci1_b)); + assign s1_y_b[0] = (~(s1_raw[0] & ci1)); + assign s0[0] = (~(s0_x_b[0] & s0_y_b[0])); + assign s1[0] = (~(s1_x_b[0] & s1_y_b[0])); + + assign s0_x_b[1] = (~(s0_raw[1] & ci0_b)); + assign s0_y_b[1] = (~(s1_raw[1] & ci0)); + assign s1_x_b[1] = (~(s0_raw[1] & ci1_b)); + assign s1_y_b[1] = (~(s1_raw[1] & ci1)); + assign s0[1] = (~(s0_x_b[1] & s0_y_b[1])); + assign s1[1] = (~(s1_x_b[1] & s1_y_b[1])); + + assign s0_x_b[2] = (~(s0_raw[2] & ci0_b)); + assign s0_y_b[2] = (~(s1_raw[2] & ci0)); + assign s1_x_b[2] = (~(s0_raw[2] & ci1_b)); + assign s1_y_b[2] = (~(s1_raw[2] & ci1)); + assign s0[2] = (~(s0_x_b[2] & s0_y_b[2])); + assign s1[2] = (~(s1_x_b[2] & s1_y_b[2])); + + assign s0_x_b[3] = (~(s0_raw[3] & ci0_b)); + assign s0_y_b[3] = (~(s1_raw[3] & ci0)); + assign s1_x_b[3] = (~(s0_raw[3] & ci1_b)); + assign s1_y_b[3] = (~(s1_raw[3] & ci1)); + assign s0[3] = (~(s0_x_b[3] & s0_y_b[3])); + assign s1[3] = (~(s1_x_b[3] & s1_y_b[3])); + + assign s0_x_b[4] = (~(s0_raw[4] & ci0_b)); + assign s0_y_b[4] = (~(s1_raw[4] & ci0)); + assign s1_x_b[4] = (~(s0_raw[4] & ci1_b)); + assign s1_y_b[4] = (~(s1_raw[4] & ci1)); + assign s0[4] = (~(s0_x_b[4] & s0_y_b[4])); + assign s1[4] = (~(s1_x_b[4] & s1_y_b[4])); + + assign s0_x_b[5] = (~(s0_raw[5] & ci0_b)); + assign s0_y_b[5] = (~(s1_raw[5] & ci0)); + assign s1_x_b[5] = (~(s0_raw[5] & ci1_b)); + assign s1_y_b[5] = (~(s1_raw[5] & ci1)); + assign s0[5] = (~(s0_x_b[5] & s0_y_b[5])); + assign s1[5] = (~(s1_x_b[5] & s1_y_b[5])); + + assign s0_x_b[6] = (~(s0_raw[6] & ci0_b)); + assign s0_y_b[6] = (~(s1_raw[6] & ci0)); + assign s1_x_b[6] = (~(s0_raw[6] & ci1_b)); + assign s1_y_b[6] = (~(s1_raw[6] & ci1)); + assign s0[6] = (~(s0_x_b[6] & s0_y_b[6])); + assign s1[6] = (~(s1_x_b[6] & s1_y_b[6])); + + assign s0_x_b[7] = (~(s0_raw[7] & ci0_b)); + assign s0_y_b[7] = (~(s1_raw[7] & ci0)); + assign s1_x_b[7] = (~(s0_raw[7] & ci1_b)); + assign s1_y_b[7] = (~(s1_raw[7] & ci1)); + assign s0[7] = (~(s0_x_b[7] & s0_y_b[7])); + assign s1[7] = (~(s1_x_b[7] & s1_y_b[7])); + + assign s0_x_b[8] = (~(s0_raw[8] & ci0_b)); + assign s0_y_b[8] = (~(s1_raw[8] & ci0)); + assign s1_x_b[8] = (~(s0_raw[8] & ci1_b)); + assign s1_y_b[8] = (~(s1_raw[8] & ci1)); + assign s0[8] = (~(s0_x_b[8] & s0_y_b[8])); + assign s1[8] = (~(s1_x_b[8] & s1_y_b[8])); + + assign s0_x_b[9] = (~(s0_raw[9] & ci0_b)); + assign s0_y_b[9] = (~(s1_raw[9] & ci0)); + assign s1_x_b[9] = (~(s0_raw[9] & ci1_b)); + assign s1_y_b[9] = (~(s1_raw[9] & ci1)); + assign s0[9] = (~(s0_x_b[9] & s0_y_b[9])); + assign s1[9] = (~(s1_x_b[9] & s1_y_b[9])); + + assign s0_x_b[10] = (~(s0_raw[10] & ci0_b)); + assign s0_y_b[10] = (~(s1_raw[10] & ci0)); + assign s1_x_b[10] = (~(s0_raw[10] & ci1_b)); + assign s1_y_b[10] = (~(s1_raw[10] & ci1)); + assign s0[10] = (~(s0_x_b[10] & s0_y_b[10])); + assign s1[10] = (~(s1_x_b[10] & s1_y_b[10])); + + assign s0_x_b[11] = (~(s0_raw[11] & ci0_b)); + assign s0_y_b[11] = (~(s1_raw[11] & ci0)); + assign s1_x_b[11] = (~(s0_raw[11] & ci1_b)); + assign s1_y_b[11] = (~(s1_raw[11] & ci1)); + assign s0[11] = (~(s0_x_b[11] & s0_y_b[11])); + assign s1[11] = (~(s1_x_b[11] & s1_y_b[11])); + + assign s0_x_b[12] = (~(s0_raw[12] & ci0_b)); + assign s0_y_b[12] = (~(s1_raw[12] & ci0)); + assign s1_x_b[12] = (~(s0_raw[12] & ci1_b)); + assign s1_y_b[12] = (~(s1_raw[12] & ci1)); + assign s0[12] = (~(s0_x_b[12] & s0_y_b[12])); + assign s1[12] = (~(s1_x_b[12] & s1_y_b[12])); + + assign s0_x_b[13] = (~(s0_raw[13] & ci0_b)); + assign s0_y_b[13] = (~(s1_raw[13] & ci0)); + assign s1_x_b[13] = (~(s0_raw[13] & ci1_b)); + assign s1_y_b[13] = (~(s1_raw[13] & ci1)); + assign s0[13] = (~(s0_x_b[13] & s0_y_b[13])); + assign s1[13] = (~(s1_x_b[13] & s1_y_b[13])); + + assign s0_x_b[14] = (~(s0_raw[14] & ci0_b)); + assign s0_y_b[14] = (~(s1_raw[14] & ci0)); + assign s1_x_b[14] = (~(s0_raw[14] & ci1_b)); + assign s1_y_b[14] = (~(s1_raw[14] & ci1)); + assign s0[14] = (~(s0_x_b[14] & s0_y_b[14])); + assign s1[14] = (~(s1_x_b[14] & s1_y_b[14])); + + assign s0_x_b[15] = (~(s0_raw[15] & ci0_b)); + assign s0_y_b[15] = (~(s1_raw[15] & ci0)); + assign s1_x_b[15] = (~(s0_raw[15] & ci1_b)); + assign s1_y_b[15] = (~(s1_raw[15] & ci1)); + assign s0[15] = (~(s0_x_b[15] & s0_y_b[15])); + assign s1[15] = (~(s1_x_b[15] & s1_y_b[15])); + +endmodule diff --git a/dev/verilog/work/fu_loc8inc.v b/dev/verilog/work/fu_loc8inc.v new file mode 100755 index 0000000..418d565 --- /dev/null +++ b/dev/verilog/work/fu_loc8inc.v @@ -0,0 +1,224 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + + `include "tri_a2o.vh" + +module fu_loc8inc( + x, + ci, + ci_b, + co_b, + s0, + s1 +); + input [0:7] x; + input ci; + input ci_b; + output co_b; + output [0:7] s0; + output [0:7] s1; + + wire [0:7] x_if_ci; + wire [0:7] x_b; + wire [0:7] x_p; + wire g2_6t7_b; + wire g2_4t5_b; + wire g2_2t3_b; + wire g2_0t1_b; + wire g4_4t7; + wire g4_0t3; + wire t2_6t7; + wire t2_4t5; + wire t2_2t3; + wire t4_6t7_b; + wire t4_4t7_b; + wire t4_2t5_b; + wire t8_6t7; + wire t8_4t7; + wire t8_2t7; + wire t8_7t7_b; + wire t8_6t7_b; + wire t8_5t7_b; + wire t8_4t7_b; + wire t8_3t7_b; + wire t8_2t7_b; + wire t8_1t7_b; + wire [0:7] s1x_b; + wire [0:7] s1y_b; + wire [0:7] s0_b; + + // i0_b0 i1_b0 i2_b0 i3_b0 i4_b0 i5_b0 i6_b0 i7_b0 <=== buffer inputs + // i0_b1 i1_b1 i2_b1 i3_b1 i4_b1 i5_b1 i6_b1 i7_b1 <=== buffer inputs + // i0_g2 i0_g4 i2_g2 i0_g8 i4_g2 i4_g4 i6_g2 skip <=== global chain + // skip skip i2_t4 i2_t2 i4_t4 i4_t2 i6_t4 i6_t2 <=== local carry + // skip skip i2_t8x skip i4_t8x skip i6_t8x skip <=== local carry + // skip i1_t8 i2_t8 i3_t8 i4_t8 i5_t8 i6_t8 i7_t8 <=== local carry + // i0_if i1_if i2_if i3_if i4_if i5_if i6_if i7_if <=== local carry + // i0_s1x i1_s1x i2_s1x i3_s1x i4_s1x i5_s1x i6_s1x i7_s1x <=== carry select + // i0_s1y i1_s1y i2_s1y i3_s1y i4_s1y i5_s1y i6_s1y i7_s1y <=== carry select + // i0_s1 i1_s1 i2_s1 i3_s1 i4_s1 i5_s1 i6_s1 i7_s1 <=== carry select + // i0_s0b i1_s0b i2_s0b i3_s0b i4_s0b i5_s0b i6_s0b i7_s0b <=== carry select + // i0_s0 i1_s0 i2_s0 i3_s0 i4_s0 i5_s0 i6_s0 i7_s0 <=== carry select + + //FOLDED + + // i0_b0 i2_b0 i4_b0 i6_b0 skip skip skip skip <=== buffer inputs + // i1_b0 i3_b0 i5_b0 i7_b0 skip skip skip skip <=== buffer inputs + // i0_b1 i2_b1 i4_b1 i6_b1 skip skip skip skip <=== buffer inputs + // i1_b1 i3_b1 i5_b1 i7_b1 skip skip skip skip <=== buffer inputs + // i0_g2 i2_g2 i4_g2 i6_g2 skip skip skip skip <=== global chain + // i0_g4 i0_g8 i4_g4 skip skip skip skip skip <=== global chain + // skip i2_t2 i4_t2 i6_t2 skip skip skip skip <=== local carry + // skip i2_t4 i4_t4 i6_t4 skip skip skip skip <=== local carry + // skip i2_t8x i4_t8x i6_t8x skip skip skip skip <=== local carry + // skip i2_t8 i4_t8 i6_t8 skip skip skip skip <=== local carry + // i1_t8 i3_t8 i5_t8 i7_t8 skip skip skip skip <=== local carry + // i0_if i2_if i4_if i6_if skip skip skip skip <=== local carry + // i1_if i3_if i5_if i7_if skip skip skip skip <=== local carry + // i0_s1x i2_s1x i4_s1x i6_s1x skip skip skip skip <=== carry select + // i1_s1x i3_s1x i5_s1x i7_s1x skip skip skip skip <=== carry select + // i0_s1y i2_s1y i4_s1y i6_s1y skip skip skip skip <=== carry select + // i1_s1y i3_s1y i5_s1y i7_s1y skip skip skip skip <=== carry select + // i0_s1 i2_s1 i4_s1 i6_s1 skip skip skip skip <=== carry select + // i1_s1 i3_s1 i5_s1 i7_s1 skip skip skip skip <=== carry select + // i0_s0b i2_s0b i4_s0b i6_s0b skip skip skip skip <=== carry select + // i1_s0b i3_s0b i5_s0b i7_s0b skip skip skip skip <=== carry select + // i0_s0 i2_s0 i4_s0 i6_s0 skip skip skip skip <=== carry select + // i1_s0 i3_s0 i5_s0 i7_s0 skip skip skip skip <=== carry select + + assign x_b[0] = (~x[0]); + assign x_b[1] = (~x[1]); + assign x_b[2] = (~x[2]); + assign x_b[3] = (~x[3]); + assign x_b[4] = (~x[4]); + assign x_b[5] = (~x[5]); + assign x_b[6] = (~x[6]); + assign x_b[7] = (~x[7]); + + assign x_p[0] = (~x_b[0]); + assign x_p[1] = (~x_b[1]); + assign x_p[2] = (~x_b[2]); + assign x_p[3] = (~x_b[3]); + assign x_p[4] = (~x_b[4]); + assign x_p[5] = (~x_b[5]); + assign x_p[6] = (~x_b[6]); + assign x_p[7] = (~x_b[7]); + + //-------------------------------------------- + + assign g2_0t1_b = (~(x[0] & x[1])); //0-- + assign g2_2t3_b = (~(x[2] & x[3])); //2-- + assign g2_4t5_b = (~(x[4] & x[5])); //4-- + assign g2_6t7_b = (~(x[6] & x[7])); //6-- + + assign g4_0t3 = (~(g2_0t1_b | g2_2t3_b)); //1-- + assign g4_4t7 = (~(g2_4t5_b | g2_6t7_b)); //5-- + + assign co_b = (~(g4_0t3 & g4_4t7)); //3-- ; --output + + //------------------------------------------- + + assign t2_2t3 = (~(x_b[2] | x_b[3])); //2-- + assign t2_4t5 = (~(x_b[4] | x_b[5])); //4-- + assign t2_6t7 = (~(x_b[6] | x_b[7])); //6-- + + assign t4_2t5_b = (~(t2_2t3 & t2_4t5)); //3-- + assign t4_4t7_b = (~(t2_4t5 & t2_6t7)); //5-- + assign t4_6t7_b = (~(t2_6t7)); //7-- + + assign t8_2t7 = (~(t4_2t5_b | t4_6t7_b)); //3-- + assign t8_4t7 = (~(t4_4t7_b)); //5-- + assign t8_6t7 = (~(t4_6t7_b)); //7-- + + assign t8_1t7_b = (~(t8_2t7 & x_p[1])); //1-- + assign t8_2t7_b = (~(t8_2t7)); //2-- + assign t8_3t7_b = (~(t8_4t7 & x_p[3])); //3-- + assign t8_4t7_b = (~(t8_4t7)); //4-- + assign t8_5t7_b = (~(t8_6t7 & x_p[5])); //5-- + assign t8_6t7_b = (~(t8_6t7)); //6-- + assign t8_7t7_b = (~(x_p[7])); //7-- + + //------------------------------------ + + assign x_if_ci[0] = (~(x_p[0] ^ t8_1t7_b)); + assign x_if_ci[1] = (~(x_p[1] ^ t8_2t7_b)); + assign x_if_ci[2] = (~(x_p[2] ^ t8_3t7_b)); + assign x_if_ci[3] = (~(x_p[3] ^ t8_4t7_b)); + assign x_if_ci[4] = (~(x_p[4] ^ t8_5t7_b)); + assign x_if_ci[5] = (~(x_p[5] ^ t8_6t7_b)); + assign x_if_ci[6] = (~(x_p[6] ^ t8_7t7_b)); + assign x_if_ci[7] = (~(x_p[7])); + + assign s1x_b[0] = (~(x_p[0] & ci_b)); + assign s1x_b[1] = (~(x_p[1] & ci_b)); + assign s1x_b[2] = (~(x_p[2] & ci_b)); + assign s1x_b[3] = (~(x_p[3] & ci_b)); + assign s1x_b[4] = (~(x_p[4] & ci_b)); + assign s1x_b[5] = (~(x_p[5] & ci_b)); + assign s1x_b[6] = (~(x_p[6] & ci_b)); + assign s1x_b[7] = (~(x_p[7] & ci_b)); + + assign s1y_b[0] = (~(x_if_ci[0] & ci)); + assign s1y_b[1] = (~(x_if_ci[1] & ci)); + assign s1y_b[2] = (~(x_if_ci[2] & ci)); + assign s1y_b[3] = (~(x_if_ci[3] & ci)); + assign s1y_b[4] = (~(x_if_ci[4] & ci)); + assign s1y_b[5] = (~(x_if_ci[5] & ci)); + assign s1y_b[6] = (~(x_if_ci[6] & ci)); + assign s1y_b[7] = (~(x_if_ci[7] & ci)); + + assign s1[0] = (~(s1x_b[0] & s1y_b[0])); //output + assign s1[1] = (~(s1x_b[1] & s1y_b[1])); //output + assign s1[2] = (~(s1x_b[2] & s1y_b[2])); //output + assign s1[3] = (~(s1x_b[3] & s1y_b[3])); //output + assign s1[4] = (~(s1x_b[4] & s1y_b[4])); //output + assign s1[5] = (~(s1x_b[5] & s1y_b[5])); //output + assign s1[6] = (~(s1x_b[6] & s1y_b[6])); //output + assign s1[7] = (~(s1x_b[7] & s1y_b[7])); //output + + assign s0_b[0] = (~x_p[0]); + assign s0_b[1] = (~x_p[1]); + assign s0_b[2] = (~x_p[2]); + assign s0_b[3] = (~x_p[3]); + assign s0_b[4] = (~x_p[4]); + assign s0_b[5] = (~x_p[5]); + assign s0_b[6] = (~x_p[6]); + assign s0_b[7] = (~x_p[7]); + + assign s0[0] = (~s0_b[0]); // output + assign s0[1] = (~s0_b[1]); // output + assign s0[2] = (~s0_b[2]); // output + assign s0[3] = (~s0_b[3]); // output + assign s0[4] = (~s0_b[4]); // output + assign s0[5] = (~s0_b[5]); // output + assign s0[6] = (~s0_b[6]); // output + assign s0[7] = (~s0_b[7]); // output + +endmodule diff --git a/dev/verilog/work/fu_loc8inc_lsb.v b/dev/verilog/work/fu_loc8inc_lsb.v new file mode 100755 index 0000000..3c6a84d --- /dev/null +++ b/dev/verilog/work/fu_loc8inc_lsb.v @@ -0,0 +1,105 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + + `include "tri_a2o.vh" + + +module fu_loc8inc_lsb( + x, + co_b, + s0, + s1 +); + input [0:4] x; //48 to 52 + output co_b; + output [0:4] s0; + output [0:4] s1; + + wire [0:4] x_b; + wire [0:4] t2_b; + wire [0:4] t4; + + // FOLDED layout + // i0_xb i2_xb i4_xb skip skip skip skip + // i1_xb i3_xb skip skip skip skip skip + // i0_t2 i2_t2 i4_t2 skip skip skip skip + // skip i1_t2 i3_t2 skip skip skip skip + // i0_t2 i2_t2 i4_t2 skip skip skip skip + // i0_t8 i1_t2 i3_t2 skip skip skip skip + // i0_s0 i2_s0 i4_s0 skip skip skip skip + // i1_s0 i3_s0 skip skip skip skip skip + // i0_s1 i2_s1 i4_s1 skip skip skip skip + // i1_s1 i3_s1 skip skip skip skip skip + + //------------------------------- + // buffer off non critical path + //------------------------------- + + assign x_b[0] = (~x[0]); + assign x_b[1] = (~x[1]); + assign x_b[2] = (~x[2]); + assign x_b[3] = (~x[3]); + assign x_b[4] = (~x[4]); + + //-------------------------- + // local carry chain + //-------------------------- + + assign t2_b[0] = (~(x[0])); + assign t2_b[1] = (~(x[1] & x[2])); + assign t2_b[2] = (~(x[2] & x[3])); + assign t2_b[3] = (~(x[3] & x[4])); + assign t2_b[4] = (~(x[4])); + + assign t4[0] = (~(t2_b[0])); + assign t4[1] = (~(t2_b[1] | t2_b[3])); + assign t4[2] = (~(t2_b[2] | t2_b[4])); + assign t4[3] = (~(t2_b[3])); + assign t4[4] = (~(t2_b[4])); + + assign co_b = (~(t4[0] & t4[1])); + + //------------------------ + // sum generation + //------------------------ + + assign s0[0] = (~(x_b[0])); + assign s0[1] = (~(x_b[1])); + assign s0[2] = (~(x_b[2])); + assign s0[3] = (~(x_b[3])); + assign s0[4] = (~(x_b[4])); + + assign s1[0] = (~(x_b[0] ^ t4[1])); + assign s1[1] = (~(x_b[1] ^ t4[2])); + assign s1[2] = (~(x_b[2] ^ t4[3])); + assign s1[3] = (~(x_b[3] ^ t4[4])); + assign s1[4] = (~(t4[4])); + +endmodule diff --git a/dev/verilog/work/fu_lza.v b/dev/verilog/work/fu_lza.v new file mode 100755 index 0000000..d2e9fe3 --- /dev/null +++ b/dev/verilog/work/fu_lza.v @@ -0,0 +1,477 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + + `include "tri_a2o.vh" + +module fu_lza( + vdd, + gnd, + clkoff_b, + act_dis, + flush, + delay_lclkr, + mpw1_b, + mpw2_b, + sg_1, + thold_1, + fpu_enable, + nclk, + f_lza_si, + f_lza_so, + ex2_act_b, + f_sa3_ex4_s, + f_sa3_ex4_c, + f_alg_ex3_effsub_eac_b, + f_lze_ex3_lzo_din, + f_lze_ex4_sh_rgt_amt, + f_lze_ex4_sh_rgt_en, + f_lza_ex5_no_lza_edge, + f_lza_ex5_lza_amt, + f_lza_ex5_lza_dcd64_cp1, + f_lza_ex5_lza_dcd64_cp2, + f_lza_ex5_lza_dcd64_cp3, + f_lza_ex5_sh_rgt_en, + f_lza_ex5_sh_rgt_en_eov, + f_lza_ex5_lza_amt_eov +); + + inout vdd; + inout gnd; + input clkoff_b; // tiup + input act_dis; // ??tidn?? + input flush; // ??tidn?? + input [3:4] delay_lclkr; // tidn, + input [3:4] mpw1_b; // tidn, + input [0:0] mpw2_b; // tidn, + input sg_1; + input thold_1; + input fpu_enable; //dc_act + input [0:`NCLK_WIDTH-1] nclk; + + input f_lza_si; //perv + output f_lza_so; //perv + input ex2_act_b; //act + + input [0:162] f_sa3_ex4_s; // data + input [53:161] f_sa3_ex4_c; // data + input f_alg_ex3_effsub_eac_b; + + input [0:162] f_lze_ex3_lzo_din; + input [0:7] f_lze_ex4_sh_rgt_amt; + input f_lze_ex4_sh_rgt_en; + + output f_lza_ex5_no_lza_edge; //fpic + output [0:7] f_lza_ex5_lza_amt; //fnrm + output [0:2] f_lza_ex5_lza_dcd64_cp1; //fnrm + output [0:1] f_lza_ex5_lza_dcd64_cp2; //fnrm + output [0:0] f_lza_ex5_lza_dcd64_cp3; //fnrm + output f_lza_ex5_sh_rgt_en; + output f_lza_ex5_sh_rgt_en_eov; + output [0:7] f_lza_ex5_lza_amt_eov; //feov + + // ENTITY + + + parameter tiup = 1'b1; + parameter tidn = 1'b0; + + wire thold_0_b; + wire thold_0; + wire force_t; + wire sg_0; + wire ex3_act; + wire ex4_act; + wire ex2_act; + (* analysis_not_referenced="TRUE" *) + wire [0:3] act_spare_unused; + //-------------------------------------- + wire [0:5] act_so; //SCAN + wire [0:5] act_si; //SCAN + wire [0:162] ex4_lzo_so; //SCAN + wire [0:162] ex4_lzo_si; //SCAN + wire [0:0] ex4_sub_so; //SCAN + wire [0:0] ex4_sub_si; //SCAN + wire [0:15] ex5_amt_so; //SCAN + wire [0:15] ex5_amt_si; //SCAN + wire [0:8] ex5_dcd_so; //SCAN + wire [0:8] ex5_dcd_si; //SCAN + //-------------------------------------- + wire ex4_lza_any_b; + wire ex4_effsub; + wire ex5_no_edge; + wire ex4_no_edge_b; + wire [0:162] ex4_lzo; + wire [0:7] ex4_lza_amt_b; + wire [0:7] ex5_amt_eov; + wire [0:7] ex5_amt; + wire [0:162] ex4_sum; + wire [53:162] ex4_car; + wire [0:162] ex4_lv0_or; + wire ex4_sh_rgt_en_b; + wire ex4_lv6_or_0_b; + wire ex4_lv6_or_1_b; + wire ex4_lv6_or_0_t; + wire ex4_lv6_or_1_t; + wire ex4_lza_dcd64_0_b; + wire ex4_lza_dcd64_1_b; + wire ex4_lza_dcd64_2_b; + wire [0:2] ex5_lza_dcd64_cp1; + wire [0:1] ex5_lza_dcd64_cp2; + wire [0:0] ex5_lza_dcd64_cp3; + wire ex5_sh_rgt_en; + wire ex5_sh_rgt_en_eov; + wire ex3_effsub_eac; + wire ex3_effsub_eac_b; + wire [0:162] ex4_lzo_b; + wire [0:162] ex4_lzo_l2_b; + wire ex4_lv6_or_0; + wire ex4_lv6_or_1; + wire [0:7] ex4_rgt_amt_b; + wire lza_ex5_d1clk; + wire lza_ex5_d2clk; + wire lza_ex4_d1clk; + wire lza_ex4_d2clk; + wire [0:`NCLK_WIDTH-1] lza_ex5_lclk; + wire [0:`NCLK_WIDTH-1] lza_ex4_lclk; + + //=############################################################### + //= map block attributes + //=############################################################### + + //=############################################################### + //= pervasive + //=############################################################### + + + tri_plat thold_reg_0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(flush), + .din(thold_1), + .q(thold_0) + ); + + + tri_plat sg_reg_0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(flush), + .din(sg_1), + .q(sg_0) + ); + + + tri_lcbor lcbor_0( + .clkoff_b(clkoff_b), + .thold(thold_0), + .sg(sg_0), + .act_dis(act_dis), + .force_t(force_t), + .thold_b(thold_0_b) + ); + + //=############################################################### + //= act + //=############################################################### + + assign ex2_act = (~ex2_act_b); + + + tri_rlmreg_p #(.WIDTH(6), .NEEDS_SRESET(0)) act_lat( + .force_t(force_t), //i-- tidn, + .d_mode(tiup), + .delay_lclkr(delay_lclkr[3]), //i-- tidn, + .mpw1_b(mpw1_b[3]), //i-- tidn, + .mpw2_b(mpw2_b[0]), //i-- tidn, + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(fpu_enable), + .thold_b(thold_0_b), + .sg(sg_0), + .scout(act_so), + .scin(act_si), + //----------------- + .din({ act_spare_unused[0], + act_spare_unused[1], + ex2_act, + ex3_act, + act_spare_unused[2], + act_spare_unused[3]}), + //----------------- + .dout({ act_spare_unused[0], + act_spare_unused[1], + ex3_act, + ex4_act, + act_spare_unused[2], + act_spare_unused[3]}) + ); + + + tri_lcbnd lza_ex4_lcb( + .delay_lclkr(delay_lclkr[3]), // tidn ,--in + .mpw1_b(mpw1_b[3]), // tidn ,--in + .mpw2_b(mpw2_b[0]), // tidn ,--in + .force_t(force_t), // tidn ,--in + .nclk(nclk), //in + .vd(vdd), //inout + .gd(gnd), //inout + .act(ex3_act), //in + .sg(sg_0), //in + .thold_b(thold_0_b), //in + .d1clk(lza_ex4_d1clk), //out + .d2clk(lza_ex4_d2clk), //out + .lclk(lza_ex4_lclk) //out + ); + + + tri_lcbnd lza_ex5_lcb( + .delay_lclkr(delay_lclkr[4]), // tidn ,--in + .mpw1_b(mpw1_b[4]), // tidn ,--in + .mpw2_b(mpw2_b[0]), // tidn ,--in + .force_t(force_t), // tidn ,--in + .nclk(nclk), //in + .vd(vdd), //inout + .gd(gnd), //inout + .act(ex4_act), //in + .sg(sg_0), //in + .thold_b(thold_0_b), //in + .d1clk(lza_ex5_d1clk), //out + .d2clk(lza_ex5_d2clk), //out + .lclk(lza_ex5_lclk) //out + ); + + //=############################################################### + //= ex4 latches + //=############################################################### + + + tri_inv_nlats #(.WIDTH(163), .NEEDS_SRESET(0)) ex4_lzo_lat( + .vd(vdd), + .gd(gnd), + .lclk(lza_ex4_lclk), // lclk.clk + .d1clk(lza_ex4_d1clk), + .d2clk(lza_ex4_d2clk), + .scanin(ex4_lzo_si), + .scanout(ex4_lzo_so), + .d(f_lze_ex3_lzo_din[0:162]), + .qb(ex4_lzo_l2_b[0:162]) + ); + + assign ex4_lzo[0:162] = (~ex4_lzo_l2_b[0:162]); + assign ex4_lzo_b[0:162] = (~ex4_lzo[0:162]); + + assign ex3_effsub_eac = (~f_alg_ex3_effsub_eac_b); + assign ex3_effsub_eac_b = (~ex3_effsub_eac); + + + tri_inv_nlats #(.WIDTH(1), .NEEDS_SRESET(0)) ex4_sub_lat( + .vd(vdd), + .gd(gnd), + .lclk(lza_ex4_lclk), // lclk.clk + .d1clk(lza_ex4_d1clk), + .d2clk(lza_ex4_d2clk), + .scanin(ex4_sub_si[0]), + .scanout(ex4_sub_so[0]), + .d(ex3_effsub_eac_b), + .qb(ex4_effsub) + ); + + assign ex4_sum[0:52] = f_sa3_ex4_s[0:52]; + + //=############################################################### + //= ex4 logic + //=############################################################### + + assign ex4_sum[53:162] = f_sa3_ex4_s[53:162]; + assign ex4_car[53:162] = {f_sa3_ex4_c[53:161], tidn}; + + //=#------------------------------------------------ + //=#-- EDGE DETECTION + //=#------------------------------------------------ + + + fu_lza_ej lzaej( + .effsub(ex4_effsub), //i-- + .sum(ex4_sum[0:162]), //i-- + .car(ex4_car[53:162]), //i-- + .lzo_b(ex4_lzo_b[0:162]), //i-- + .edge_t(ex4_lv0_or[0:162]) //o-- + ); + + //=#------------------------------------------------ + //=#-- ENCODING TREE (CLZ) count leading zeroes + //=#------------------------------------------------ + + + fu_lza_clz lzaclz( + .lv0_or(ex4_lv0_or[0:162]), //i-- + .lv6_or_0(ex4_lv6_or_0), //o-- + .lv6_or_1(ex4_lv6_or_1), //o-- + .lza_any_b(ex4_lza_any_b), //i-- + .lza_amt_b(ex4_lza_amt_b[0:7]) //o-- + ); + + assign ex4_no_edge_b = (~ex4_lza_any_b); + + //=############################################################### + //= ex5 latches + //=############################################################### + + assign ex4_rgt_amt_b[0:7] = (~f_lze_ex4_sh_rgt_amt[0:7]); + + assign ex4_sh_rgt_en_b = (~f_lze_ex4_sh_rgt_en); + + assign ex4_lv6_or_0_b = (~ex4_lv6_or_0); + assign ex4_lv6_or_1_b = (~ex4_lv6_or_1); + assign ex4_lv6_or_0_t = (~ex4_lv6_or_0_b); + assign ex4_lv6_or_1_t = (~ex4_lv6_or_1_b); + + assign ex4_lza_dcd64_0_b = (~(ex4_lv6_or_0_t & ex4_sh_rgt_en_b)); + assign ex4_lza_dcd64_1_b = (~(ex4_lv6_or_0_b & ex4_lv6_or_1_t & ex4_sh_rgt_en_b)); + assign ex4_lza_dcd64_2_b = (~(ex4_lv6_or_0_b & ex4_lv6_or_1_b & ex4_sh_rgt_en_b)); + + tri_inv_nlats #(.WIDTH(9), .NEEDS_SRESET(0)) ex5_dcd_lat( + .vd(vdd), + .gd(gnd), + .lclk(lza_ex5_lclk), // lclk.clk + .d1clk(lza_ex5_d1clk), + .d2clk(lza_ex5_d2clk), + .scanin(ex5_dcd_si[0:8]), + .scanout(ex5_dcd_so[0:8]), + .d({ex4_lza_dcd64_0_b, //( 0) + ex4_lza_dcd64_0_b, //( 1) + ex4_lza_dcd64_0_b, //( 2) + ex4_lza_dcd64_1_b, //( 3) + ex4_lza_dcd64_1_b, //( 4) + ex4_lza_dcd64_2_b, //( 5) + ex4_sh_rgt_en_b, //( 6) + ex4_sh_rgt_en_b, //( 7) + ex4_no_edge_b}), //(24) + //----------------- + .qb({ex5_lza_dcd64_cp1[0], //( 6) + ex5_lza_dcd64_cp2[0], //( 9) + ex5_lza_dcd64_cp3[0], //( 1) + ex5_lza_dcd64_cp1[1], //( 7) + ex5_lza_dcd64_cp2[1], //( 0) + ex5_lza_dcd64_cp1[2], //( 8) + ex5_sh_rgt_en, //( 2) + ex5_sh_rgt_en_eov, //( 3) + ex5_no_edge}) //(24) + ); + + + tri_nand2_nlats #(.WIDTH(16), .NEEDS_SRESET(0)) ex5_amt_lat( + .vd(vdd), + .gd(gnd), + .lclk(lza_ex5_lclk), //in --lclk.clk + .d1clk(lza_ex5_d1clk), //in + .d2clk(lza_ex5_d2clk), //in + .scanin(ex5_amt_si[0:15]), + .scanout(ex5_amt_so[0:15]), + .a1({ ex4_lza_amt_b[0], //( 8) + ex4_lza_amt_b[0], //( 9) + ex4_lza_amt_b[1], //(10) + ex4_lza_amt_b[1], //(11) + ex4_lza_amt_b[2], //(12) + ex4_lza_amt_b[2], //(13) + ex4_lza_amt_b[3], //(14) + ex4_lza_amt_b[3], //(15) + ex4_lza_amt_b[4], //(16) + ex4_lza_amt_b[4], //(17) + ex4_lza_amt_b[5], //(18) + ex4_lza_amt_b[5], //(19) + ex4_lza_amt_b[6], //(20) + ex4_lza_amt_b[6], //(21) + ex4_lza_amt_b[7], //(22) + ex4_lza_amt_b[7]}), //(23) + + .a2({ ex4_rgt_amt_b[0], //( 8) + ex4_rgt_amt_b[0], //( 9) + ex4_rgt_amt_b[1], //(10) + ex4_rgt_amt_b[1], //(11) + ex4_rgt_amt_b[2], //(12) + ex4_rgt_amt_b[2], //(13) + ex4_rgt_amt_b[3], //(14) + ex4_rgt_amt_b[3], //(15) + ex4_rgt_amt_b[4], //(16) + ex4_rgt_amt_b[4], //(17) + ex4_rgt_amt_b[5], //(18) + ex4_rgt_amt_b[5], //(19) + ex4_rgt_amt_b[6], //(20) + ex4_rgt_amt_b[6], //(21) + ex4_rgt_amt_b[7], //(22) + ex4_rgt_amt_b[7] }), //(23) + + //----------------- + .qb({ ex5_amt[0], //( 0) + ex5_amt_eov[0], //( 8) + ex5_amt[1], //(11) + ex5_amt_eov[1], //(19) + ex5_amt[2], //(12) + ex5_amt_eov[2], //(10) + ex5_amt[3], //(13) + ex5_amt_eov[3], //(11) + ex5_amt[4], //(14) + ex5_amt_eov[4], //(12) + ex5_amt[5], //(15) + ex5_amt_eov[5], //(13) + ex5_amt[6], //(26) + ex5_amt_eov[6], //(24) + ex5_amt[7], //(27) + ex5_amt_eov[7]}) //(24) + ); + + assign f_lza_ex5_sh_rgt_en = ex5_sh_rgt_en; + assign f_lza_ex5_sh_rgt_en_eov = ex5_sh_rgt_en_eov; + + assign f_lza_ex5_lza_amt = ex5_amt[0:7]; //output-- --fnrm-- + + assign f_lza_ex5_lza_dcd64_cp1[0:2] = ex5_lza_dcd64_cp1[0:2]; //ouptut-- --fnrm + assign f_lza_ex5_lza_dcd64_cp2[0:1] = ex5_lza_dcd64_cp2[0:1]; //ouptut-- --fnrm + assign f_lza_ex5_lza_dcd64_cp3[0] = ex5_lza_dcd64_cp3[0]; //ouptut-- --fnrm + + assign f_lza_ex5_lza_amt_eov = ex5_amt_eov[0:7]; //output-- --feov-- + assign f_lza_ex5_no_lza_edge = ex5_no_edge; //output-- --fpic-- + + //=############################################################### + //= scan string + //=############################################################### + + assign ex4_lzo_si[0:162] = {ex4_lzo_so[1:162], f_lza_si}; + assign ex4_sub_si[0] = ex4_lzo_so[0]; + assign ex5_amt_si[0:15] = {ex5_amt_so[1:15], ex4_sub_so[0]}; + assign ex5_dcd_si[0:8] = {ex5_dcd_so[1:8], ex5_amt_so[0]}; + assign act_si[0:5] = {act_so[1:5], ex5_dcd_so[0]}; + assign f_lza_so = act_so[0]; + +endmodule diff --git a/dev/verilog/work/fu_lza_clz.v b/dev/verilog/work/fu_lza_clz.v new file mode 100755 index 0000000..f53cd70 --- /dev/null +++ b/dev/verilog/work/fu_lza_clz.v @@ -0,0 +1,947 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + + `include "tri_a2o.vh" + +module fu_lza_clz( + lv0_or, + lv6_or_0, + lv6_or_1, + lza_any_b, + lza_amt_b +); + input [0:162] lv0_or; + output lv6_or_0; + output lv6_or_1; + output lza_any_b; + output [0:7] lza_amt_b; + + parameter tiup = 1'b1; + parameter tidn = 1'b0; + + wire [0:81] lv1_or_b; // group_002 + wire [0:81] lv1_inv_b; + wire [0:81] lv1_enc7_b; + wire [0:40] lv2_or; // group_004 + wire [0:40] lv2_inv; + wire [0:40] lv2_enc6; + wire [0:40] lv2_enc7; + wire [0:20] lv3_or_b; // group_008 + + wire [0:20] lv3_inv_b; // group_008 + wire [0:20] lv3_enc5_b; + wire [0:20] lv3_enc6_b; + wire [0:20] lv3_enc7_b; + + wire [0:10] lv4_or; // group_016 + wire [0:10] lv4_inv; // group_016 + wire [0:10] lv4_enc4; + wire [0:10] lv4_enc5; + wire [0:10] lv4_enc6; + wire [0:10] lv4_enc7; + + wire [0:10] lv4_or_b; // group_016 + wire [0:10] lv4_enc4_b; + wire [0:10] lv4_enc5_b; + wire [0:10] lv4_enc6_b; + wire [0:10] lv4_enc7_b; + + //----------------------------------------------------------- + + wire [0:5] lv5_or; // group_032 + wire [0:5] lv5_inv; + wire [0:5] lv5_enc3; + wire [0:5] lv5_enc4; + wire [0:5] lv5_enc5; + wire [0:5] lv5_enc6; + wire [0:5] lv5_enc7; + + wire [0:2] lv6_or_b; // group_064 + wire [0:2] lv6_inv_b; + wire [0:2] lv6_enc2_b; + wire [0:2] lv6_enc3_b; + wire [0:2] lv6_enc4_b; + wire [0:2] lv6_enc5_b; + wire [0:2] lv6_enc6_b; + wire [0:2] lv6_enc7_b; + + wire [0:1] lv7_or; // group_128 + wire [0:1] lv7_inv; + wire [0:1] lv7_enc1; + wire [0:1] lv7_enc2; + wire [0:1] lv7_enc3; + wire [0:1] lv7_enc4; + wire [0:1] lv7_enc5; + wire [0:1] lv7_enc6; + wire [0:1] lv7_enc7; + + wire [0:0] lv8_or_b; // group_256 + wire [0:0] lv8_inv_b; + wire [0:0] lv8_enc0_b; + wire [0:0] lv8_enc1_b; + wire [0:0] lv8_enc2_b; + wire [0:0] lv8_enc3_b; + wire [0:0] lv8_enc4_b; + wire [0:0] lv8_enc5_b; + wire [0:0] lv8_enc6_b; + wire [0:0] lv8_enc7_b; + + //=#------------------------------------------------ + //=#-- ENCODING TREE (CLZ) count leading zeroes + //=#------------------------------------------------ + //-------------------------------------------------------------------------------- + // 002 bit group (phase_in=P, phase_out=N, level_in=lv0, level_out=lv1) + //-------------------------------------------------------------------------------- + + assign lv1_or_b[0] = (~(lv0_or[0] | lv0_or[1])); + assign lv1_or_b[1] = (~(lv0_or[2] | lv0_or[3])); + assign lv1_or_b[2] = (~(lv0_or[4] | lv0_or[5])); + assign lv1_or_b[3] = (~(lv0_or[6] | lv0_or[7])); + assign lv1_or_b[4] = (~(lv0_or[8] | lv0_or[9])); + assign lv1_or_b[5] = (~(lv0_or[10] | lv0_or[11])); + assign lv1_or_b[6] = (~(lv0_or[12] | lv0_or[13])); + assign lv1_or_b[7] = (~(lv0_or[14] | lv0_or[15])); + assign lv1_or_b[8] = (~(lv0_or[16] | lv0_or[17])); + assign lv1_or_b[9] = (~(lv0_or[18] | lv0_or[19])); + assign lv1_or_b[10] = (~(lv0_or[20] | lv0_or[21])); + assign lv1_or_b[11] = (~(lv0_or[22] | lv0_or[23])); + assign lv1_or_b[12] = (~(lv0_or[24] | lv0_or[25])); + assign lv1_or_b[13] = (~(lv0_or[26] | lv0_or[27])); + assign lv1_or_b[14] = (~(lv0_or[28] | lv0_or[29])); + assign lv1_or_b[15] = (~(lv0_or[30] | lv0_or[31])); + assign lv1_or_b[16] = (~(lv0_or[32] | lv0_or[33])); + assign lv1_or_b[17] = (~(lv0_or[34] | lv0_or[35])); + assign lv1_or_b[18] = (~(lv0_or[36] | lv0_or[37])); + assign lv1_or_b[19] = (~(lv0_or[38] | lv0_or[39])); + assign lv1_or_b[20] = (~(lv0_or[40] | lv0_or[41])); + assign lv1_or_b[21] = (~(lv0_or[42] | lv0_or[43])); + assign lv1_or_b[22] = (~(lv0_or[44] | lv0_or[45])); + assign lv1_or_b[23] = (~(lv0_or[46] | lv0_or[47])); + assign lv1_or_b[24] = (~(lv0_or[48] | lv0_or[49])); + assign lv1_or_b[25] = (~(lv0_or[50] | lv0_or[51])); + assign lv1_or_b[26] = (~(lv0_or[52] | lv0_or[53])); + assign lv1_or_b[27] = (~(lv0_or[54] | lv0_or[55])); + assign lv1_or_b[28] = (~(lv0_or[56] | lv0_or[57])); + assign lv1_or_b[29] = (~(lv0_or[58] | lv0_or[59])); + assign lv1_or_b[30] = (~(lv0_or[60] | lv0_or[61])); + assign lv1_or_b[31] = (~(lv0_or[62] | lv0_or[63])); + assign lv1_or_b[32] = (~(lv0_or[64] | lv0_or[65])); + assign lv1_or_b[33] = (~(lv0_or[66] | lv0_or[67])); + assign lv1_or_b[34] = (~(lv0_or[68] | lv0_or[69])); + assign lv1_or_b[35] = (~(lv0_or[70] | lv0_or[71])); + assign lv1_or_b[36] = (~(lv0_or[72] | lv0_or[73])); + assign lv1_or_b[37] = (~(lv0_or[74] | lv0_or[75])); + assign lv1_or_b[38] = (~(lv0_or[76] | lv0_or[77])); + assign lv1_or_b[39] = (~(lv0_or[78] | lv0_or[79])); + assign lv1_or_b[40] = (~(lv0_or[80] | lv0_or[81])); + assign lv1_or_b[41] = (~(lv0_or[82] | lv0_or[83])); + assign lv1_or_b[42] = (~(lv0_or[84] | lv0_or[85])); + assign lv1_or_b[43] = (~(lv0_or[86] | lv0_or[87])); + assign lv1_or_b[44] = (~(lv0_or[88] | lv0_or[89])); + assign lv1_or_b[45] = (~(lv0_or[90] | lv0_or[91])); + assign lv1_or_b[46] = (~(lv0_or[92] | lv0_or[93])); + assign lv1_or_b[47] = (~(lv0_or[94] | lv0_or[95])); + assign lv1_or_b[48] = (~(lv0_or[96] | lv0_or[97])); + assign lv1_or_b[49] = (~(lv0_or[98] | lv0_or[99])); + assign lv1_or_b[50] = (~(lv0_or[100] | lv0_or[101])); + assign lv1_or_b[51] = (~(lv0_or[102] | lv0_or[103])); + assign lv1_or_b[52] = (~(lv0_or[104] | lv0_or[105])); + assign lv1_or_b[53] = (~(lv0_or[106] | lv0_or[107])); + assign lv1_or_b[54] = (~(lv0_or[108] | lv0_or[109])); + assign lv1_or_b[55] = (~(lv0_or[110] | lv0_or[111])); + assign lv1_or_b[56] = (~(lv0_or[112] | lv0_or[113])); + assign lv1_or_b[57] = (~(lv0_or[114] | lv0_or[115])); + assign lv1_or_b[58] = (~(lv0_or[116] | lv0_or[117])); + assign lv1_or_b[59] = (~(lv0_or[118] | lv0_or[119])); + assign lv1_or_b[60] = (~(lv0_or[120] | lv0_or[121])); + assign lv1_or_b[61] = (~(lv0_or[122] | lv0_or[123])); + assign lv1_or_b[62] = (~(lv0_or[124] | lv0_or[125])); + assign lv1_or_b[63] = (~(lv0_or[126] | lv0_or[127])); + assign lv1_or_b[64] = (~(lv0_or[128] | lv0_or[129])); + assign lv1_or_b[65] = (~(lv0_or[130] | lv0_or[131])); + assign lv1_or_b[66] = (~(lv0_or[132] | lv0_or[133])); + assign lv1_or_b[67] = (~(lv0_or[134] | lv0_or[135])); + assign lv1_or_b[68] = (~(lv0_or[136] | lv0_or[137])); + assign lv1_or_b[69] = (~(lv0_or[138] | lv0_or[139])); + assign lv1_or_b[70] = (~(lv0_or[140] | lv0_or[141])); + assign lv1_or_b[71] = (~(lv0_or[142] | lv0_or[143])); + assign lv1_or_b[72] = (~(lv0_or[144] | lv0_or[145])); + assign lv1_or_b[73] = (~(lv0_or[146] | lv0_or[147])); + assign lv1_or_b[74] = (~(lv0_or[148] | lv0_or[149])); + assign lv1_or_b[75] = (~(lv0_or[150] | lv0_or[151])); + assign lv1_or_b[76] = (~(lv0_or[152] | lv0_or[153])); + assign lv1_or_b[77] = (~(lv0_or[154] | lv0_or[155])); + assign lv1_or_b[78] = (~(lv0_or[156] | lv0_or[157])); + assign lv1_or_b[79] = (~(lv0_or[158] | lv0_or[159])); + assign lv1_or_b[80] = (~(lv0_or[160] | lv0_or[161])); + assign lv1_or_b[81] = (~(lv0_or[162])); + + assign lv1_inv_b[0] = (~(lv0_or[0])); + assign lv1_inv_b[1] = (~(lv0_or[2])); + assign lv1_inv_b[2] = (~(lv0_or[4])); + assign lv1_inv_b[3] = (~(lv0_or[6])); + assign lv1_inv_b[4] = (~(lv0_or[8])); + assign lv1_inv_b[5] = (~(lv0_or[10])); + assign lv1_inv_b[6] = (~(lv0_or[12])); + assign lv1_inv_b[7] = (~(lv0_or[14])); + assign lv1_inv_b[8] = (~(lv0_or[16])); + assign lv1_inv_b[9] = (~(lv0_or[18])); + assign lv1_inv_b[10] = (~(lv0_or[20])); + assign lv1_inv_b[11] = (~(lv0_or[22])); + assign lv1_inv_b[12] = (~(lv0_or[24])); + assign lv1_inv_b[13] = (~(lv0_or[26])); + assign lv1_inv_b[14] = (~(lv0_or[28])); + assign lv1_inv_b[15] = (~(lv0_or[30])); + assign lv1_inv_b[16] = (~(lv0_or[32])); + assign lv1_inv_b[17] = (~(lv0_or[34])); + assign lv1_inv_b[18] = (~(lv0_or[36])); + assign lv1_inv_b[19] = (~(lv0_or[38])); + assign lv1_inv_b[20] = (~(lv0_or[40])); + assign lv1_inv_b[21] = (~(lv0_or[42])); + assign lv1_inv_b[22] = (~(lv0_or[44])); + assign lv1_inv_b[23] = (~(lv0_or[46])); + assign lv1_inv_b[24] = (~(lv0_or[48])); + assign lv1_inv_b[25] = (~(lv0_or[50])); + assign lv1_inv_b[26] = (~(lv0_or[52])); + assign lv1_inv_b[27] = (~(lv0_or[54])); + assign lv1_inv_b[28] = (~(lv0_or[56])); + assign lv1_inv_b[29] = (~(lv0_or[58])); + assign lv1_inv_b[30] = (~(lv0_or[60])); + assign lv1_inv_b[31] = (~(lv0_or[62])); + assign lv1_inv_b[32] = (~(lv0_or[64])); + assign lv1_inv_b[33] = (~(lv0_or[66])); + assign lv1_inv_b[34] = (~(lv0_or[68])); + assign lv1_inv_b[35] = (~(lv0_or[70])); + assign lv1_inv_b[36] = (~(lv0_or[72])); + assign lv1_inv_b[37] = (~(lv0_or[74])); + assign lv1_inv_b[38] = (~(lv0_or[76])); + assign lv1_inv_b[39] = (~(lv0_or[78])); + assign lv1_inv_b[40] = (~(lv0_or[80])); + assign lv1_inv_b[41] = (~(lv0_or[82])); + assign lv1_inv_b[42] = (~(lv0_or[84])); + assign lv1_inv_b[43] = (~(lv0_or[86])); + assign lv1_inv_b[44] = (~(lv0_or[88])); + assign lv1_inv_b[45] = (~(lv0_or[90])); + assign lv1_inv_b[46] = (~(lv0_or[92])); + assign lv1_inv_b[47] = (~(lv0_or[94])); + assign lv1_inv_b[48] = (~(lv0_or[96])); + assign lv1_inv_b[49] = (~(lv0_or[98])); + assign lv1_inv_b[50] = (~(lv0_or[100])); + assign lv1_inv_b[51] = (~(lv0_or[102])); + assign lv1_inv_b[52] = (~(lv0_or[104])); + assign lv1_inv_b[53] = (~(lv0_or[106])); + assign lv1_inv_b[54] = (~(lv0_or[108])); + assign lv1_inv_b[55] = (~(lv0_or[110])); + assign lv1_inv_b[56] = (~(lv0_or[112])); + assign lv1_inv_b[57] = (~(lv0_or[114])); + assign lv1_inv_b[58] = (~(lv0_or[116])); + assign lv1_inv_b[59] = (~(lv0_or[118])); + assign lv1_inv_b[60] = (~(lv0_or[120])); + assign lv1_inv_b[61] = (~(lv0_or[122])); + assign lv1_inv_b[62] = (~(lv0_or[124])); + assign lv1_inv_b[63] = (~(lv0_or[126])); + assign lv1_inv_b[64] = (~(lv0_or[128])); + assign lv1_inv_b[65] = (~(lv0_or[130])); + assign lv1_inv_b[66] = (~(lv0_or[132])); + assign lv1_inv_b[67] = (~(lv0_or[134])); + assign lv1_inv_b[68] = (~(lv0_or[136])); + assign lv1_inv_b[69] = (~(lv0_or[138])); + assign lv1_inv_b[70] = (~(lv0_or[140])); + assign lv1_inv_b[71] = (~(lv0_or[142])); + assign lv1_inv_b[72] = (~(lv0_or[144])); + assign lv1_inv_b[73] = (~(lv0_or[146])); + assign lv1_inv_b[74] = (~(lv0_or[148])); + assign lv1_inv_b[75] = (~(lv0_or[150])); + assign lv1_inv_b[76] = (~(lv0_or[152])); + assign lv1_inv_b[77] = (~(lv0_or[154])); + assign lv1_inv_b[78] = (~(lv0_or[156])); + assign lv1_inv_b[79] = (~(lv0_or[158])); + assign lv1_inv_b[80] = (~(lv0_or[160])); + assign lv1_inv_b[81] = (~(lv0_or[162])); + + assign lv1_enc7_b[0] = (~(lv1_inv_b[0] & lv0_or[1])); + assign lv1_enc7_b[1] = (~(lv1_inv_b[1] & lv0_or[3])); + assign lv1_enc7_b[2] = (~(lv1_inv_b[2] & lv0_or[5])); + assign lv1_enc7_b[3] = (~(lv1_inv_b[3] & lv0_or[7])); + assign lv1_enc7_b[4] = (~(lv1_inv_b[4] & lv0_or[9])); + assign lv1_enc7_b[5] = (~(lv1_inv_b[5] & lv0_or[11])); + assign lv1_enc7_b[6] = (~(lv1_inv_b[6] & lv0_or[13])); + assign lv1_enc7_b[7] = (~(lv1_inv_b[7] & lv0_or[15])); + assign lv1_enc7_b[8] = (~(lv1_inv_b[8] & lv0_or[17])); + assign lv1_enc7_b[9] = (~(lv1_inv_b[9] & lv0_or[19])); + assign lv1_enc7_b[10] = (~(lv1_inv_b[10] & lv0_or[21])); + assign lv1_enc7_b[11] = (~(lv1_inv_b[11] & lv0_or[23])); + assign lv1_enc7_b[12] = (~(lv1_inv_b[12] & lv0_or[25])); + assign lv1_enc7_b[13] = (~(lv1_inv_b[13] & lv0_or[27])); + assign lv1_enc7_b[14] = (~(lv1_inv_b[14] & lv0_or[29])); + assign lv1_enc7_b[15] = (~(lv1_inv_b[15] & lv0_or[31])); + assign lv1_enc7_b[16] = (~(lv1_inv_b[16] & lv0_or[33])); + assign lv1_enc7_b[17] = (~(lv1_inv_b[17] & lv0_or[35])); + assign lv1_enc7_b[18] = (~(lv1_inv_b[18] & lv0_or[37])); + assign lv1_enc7_b[19] = (~(lv1_inv_b[19] & lv0_or[39])); + assign lv1_enc7_b[20] = (~(lv1_inv_b[20] & lv0_or[41])); + assign lv1_enc7_b[21] = (~(lv1_inv_b[21] & lv0_or[43])); + assign lv1_enc7_b[22] = (~(lv1_inv_b[22] & lv0_or[45])); + assign lv1_enc7_b[23] = (~(lv1_inv_b[23] & lv0_or[47])); + assign lv1_enc7_b[24] = (~(lv1_inv_b[24] & lv0_or[49])); + assign lv1_enc7_b[25] = (~(lv1_inv_b[25] & lv0_or[51])); + assign lv1_enc7_b[26] = (~(lv1_inv_b[26] & lv0_or[53])); + assign lv1_enc7_b[27] = (~(lv1_inv_b[27] & lv0_or[55])); + assign lv1_enc7_b[28] = (~(lv1_inv_b[28] & lv0_or[57])); + assign lv1_enc7_b[29] = (~(lv1_inv_b[29] & lv0_or[59])); + assign lv1_enc7_b[30] = (~(lv1_inv_b[30] & lv0_or[61])); + assign lv1_enc7_b[31] = (~(lv1_inv_b[31] & lv0_or[63])); + assign lv1_enc7_b[32] = (~(lv1_inv_b[32] & lv0_or[65])); + assign lv1_enc7_b[33] = (~(lv1_inv_b[33] & lv0_or[67])); + assign lv1_enc7_b[34] = (~(lv1_inv_b[34] & lv0_or[69])); + assign lv1_enc7_b[35] = (~(lv1_inv_b[35] & lv0_or[71])); + assign lv1_enc7_b[36] = (~(lv1_inv_b[36] & lv0_or[73])); + assign lv1_enc7_b[37] = (~(lv1_inv_b[37] & lv0_or[75])); + assign lv1_enc7_b[38] = (~(lv1_inv_b[38] & lv0_or[77])); + assign lv1_enc7_b[39] = (~(lv1_inv_b[39] & lv0_or[79])); + assign lv1_enc7_b[40] = (~(lv1_inv_b[40] & lv0_or[81])); + assign lv1_enc7_b[41] = (~(lv1_inv_b[41] & lv0_or[83])); + assign lv1_enc7_b[42] = (~(lv1_inv_b[42] & lv0_or[85])); + assign lv1_enc7_b[43] = (~(lv1_inv_b[43] & lv0_or[87])); + assign lv1_enc7_b[44] = (~(lv1_inv_b[44] & lv0_or[89])); + assign lv1_enc7_b[45] = (~(lv1_inv_b[45] & lv0_or[91])); + assign lv1_enc7_b[46] = (~(lv1_inv_b[46] & lv0_or[93])); + assign lv1_enc7_b[47] = (~(lv1_inv_b[47] & lv0_or[95])); + assign lv1_enc7_b[48] = (~(lv1_inv_b[48] & lv0_or[97])); + assign lv1_enc7_b[49] = (~(lv1_inv_b[49] & lv0_or[99])); + assign lv1_enc7_b[50] = (~(lv1_inv_b[50] & lv0_or[101])); + assign lv1_enc7_b[51] = (~(lv1_inv_b[51] & lv0_or[103])); + assign lv1_enc7_b[52] = (~(lv1_inv_b[52] & lv0_or[105])); + assign lv1_enc7_b[53] = (~(lv1_inv_b[53] & lv0_or[107])); + assign lv1_enc7_b[54] = (~(lv1_inv_b[54] & lv0_or[109])); + assign lv1_enc7_b[55] = (~(lv1_inv_b[55] & lv0_or[111])); + assign lv1_enc7_b[56] = (~(lv1_inv_b[56] & lv0_or[113])); + assign lv1_enc7_b[57] = (~(lv1_inv_b[57] & lv0_or[115])); + assign lv1_enc7_b[58] = (~(lv1_inv_b[58] & lv0_or[117])); + assign lv1_enc7_b[59] = (~(lv1_inv_b[59] & lv0_or[119])); + assign lv1_enc7_b[60] = (~(lv1_inv_b[60] & lv0_or[121])); + assign lv1_enc7_b[61] = (~(lv1_inv_b[61] & lv0_or[123])); + assign lv1_enc7_b[62] = (~(lv1_inv_b[62] & lv0_or[125])); + assign lv1_enc7_b[63] = (~(lv1_inv_b[63] & lv0_or[127])); + assign lv1_enc7_b[64] = (~(lv1_inv_b[64] & lv0_or[129])); + assign lv1_enc7_b[65] = (~(lv1_inv_b[65] & lv0_or[131])); + assign lv1_enc7_b[66] = (~(lv1_inv_b[66] & lv0_or[133])); + assign lv1_enc7_b[67] = (~(lv1_inv_b[67] & lv0_or[135])); + assign lv1_enc7_b[68] = (~(lv1_inv_b[68] & lv0_or[137])); + assign lv1_enc7_b[69] = (~(lv1_inv_b[69] & lv0_or[139])); + assign lv1_enc7_b[70] = (~(lv1_inv_b[70] & lv0_or[141])); + assign lv1_enc7_b[71] = (~(lv1_inv_b[71] & lv0_or[143])); + assign lv1_enc7_b[72] = (~(lv1_inv_b[72] & lv0_or[145])); + assign lv1_enc7_b[73] = (~(lv1_inv_b[73] & lv0_or[147])); + assign lv1_enc7_b[74] = (~(lv1_inv_b[74] & lv0_or[149])); + assign lv1_enc7_b[75] = (~(lv1_inv_b[75] & lv0_or[151])); + assign lv1_enc7_b[76] = (~(lv1_inv_b[76] & lv0_or[153])); + assign lv1_enc7_b[77] = (~(lv1_inv_b[77] & lv0_or[155])); + assign lv1_enc7_b[78] = (~(lv1_inv_b[78] & lv0_or[157])); + assign lv1_enc7_b[79] = (~(lv1_inv_b[79] & lv0_or[159])); + assign lv1_enc7_b[80] = (~(lv1_inv_b[80] & lv0_or[161])); + assign lv1_enc7_b[81] = (~(lv1_inv_b[81])); //dflt1 + + //-------------------------------------------------------------------------------- + // 004 bit group (phase_in=N, phase_out=P, level_in=lv1, level_out=lv2) + //-------------------------------------------------------------------------------- + + assign lv2_or[0] = (~(lv1_or_b[0] & lv1_or_b[1])); + assign lv2_or[1] = (~(lv1_or_b[2] & lv1_or_b[3])); + assign lv2_or[2] = (~(lv1_or_b[4] & lv1_or_b[5])); + assign lv2_or[3] = (~(lv1_or_b[6] & lv1_or_b[7])); + assign lv2_or[4] = (~(lv1_or_b[8] & lv1_or_b[9])); + assign lv2_or[5] = (~(lv1_or_b[10] & lv1_or_b[11])); + assign lv2_or[6] = (~(lv1_or_b[12] & lv1_or_b[13])); + assign lv2_or[7] = (~(lv1_or_b[14] & lv1_or_b[15])); + assign lv2_or[8] = (~(lv1_or_b[16] & lv1_or_b[17])); + assign lv2_or[9] = (~(lv1_or_b[18] & lv1_or_b[19])); + assign lv2_or[10] = (~(lv1_or_b[20] & lv1_or_b[21])); + assign lv2_or[11] = (~(lv1_or_b[22] & lv1_or_b[23])); + assign lv2_or[12] = (~(lv1_or_b[24] & lv1_or_b[25])); + assign lv2_or[13] = (~(lv1_or_b[26] & lv1_or_b[27])); + assign lv2_or[14] = (~(lv1_or_b[28] & lv1_or_b[29])); + assign lv2_or[15] = (~(lv1_or_b[30] & lv1_or_b[31])); + assign lv2_or[16] = (~(lv1_or_b[32] & lv1_or_b[33])); + assign lv2_or[17] = (~(lv1_or_b[34] & lv1_or_b[35])); + assign lv2_or[18] = (~(lv1_or_b[36] & lv1_or_b[37])); + assign lv2_or[19] = (~(lv1_or_b[38] & lv1_or_b[39])); + assign lv2_or[20] = (~(lv1_or_b[40] & lv1_or_b[41])); + assign lv2_or[21] = (~(lv1_or_b[42] & lv1_or_b[43])); + assign lv2_or[22] = (~(lv1_or_b[44] & lv1_or_b[45])); + assign lv2_or[23] = (~(lv1_or_b[46] & lv1_or_b[47])); + assign lv2_or[24] = (~(lv1_or_b[48] & lv1_or_b[49])); + assign lv2_or[25] = (~(lv1_or_b[50] & lv1_or_b[51])); + assign lv2_or[26] = (~(lv1_or_b[52] & lv1_or_b[53])); + assign lv2_or[27] = (~(lv1_or_b[54] & lv1_or_b[55])); + assign lv2_or[28] = (~(lv1_or_b[56] & lv1_or_b[57])); + assign lv2_or[29] = (~(lv1_or_b[58] & lv1_or_b[59])); + assign lv2_or[30] = (~(lv1_or_b[60] & lv1_or_b[61])); + assign lv2_or[31] = (~(lv1_or_b[62] & lv1_or_b[63])); + assign lv2_or[32] = (~(lv1_or_b[64] & lv1_or_b[65])); + assign lv2_or[33] = (~(lv1_or_b[66] & lv1_or_b[67])); + assign lv2_or[34] = (~(lv1_or_b[68] & lv1_or_b[69])); + assign lv2_or[35] = (~(lv1_or_b[70] & lv1_or_b[71])); + assign lv2_or[36] = (~(lv1_or_b[72] & lv1_or_b[73])); + assign lv2_or[37] = (~(lv1_or_b[74] & lv1_or_b[75])); + assign lv2_or[38] = (~(lv1_or_b[76] & lv1_or_b[77])); + assign lv2_or[39] = (~(lv1_or_b[78] & lv1_or_b[79])); + assign lv2_or[40] = (~(lv1_or_b[80] & lv1_or_b[81])); + + assign lv2_inv[0] = (~(lv1_or_b[0])); + assign lv2_inv[1] = (~(lv1_or_b[2])); + assign lv2_inv[2] = (~(lv1_or_b[4])); + assign lv2_inv[3] = (~(lv1_or_b[6])); + assign lv2_inv[4] = (~(lv1_or_b[8])); + assign lv2_inv[5] = (~(lv1_or_b[10])); + assign lv2_inv[6] = (~(lv1_or_b[12])); + assign lv2_inv[7] = (~(lv1_or_b[14])); + assign lv2_inv[8] = (~(lv1_or_b[16])); + assign lv2_inv[9] = (~(lv1_or_b[18])); + assign lv2_inv[10] = (~(lv1_or_b[20])); + assign lv2_inv[11] = (~(lv1_or_b[22])); + assign lv2_inv[12] = (~(lv1_or_b[24])); + assign lv2_inv[13] = (~(lv1_or_b[26])); + assign lv2_inv[14] = (~(lv1_or_b[28])); + assign lv2_inv[15] = (~(lv1_or_b[30])); + assign lv2_inv[16] = (~(lv1_or_b[32])); + assign lv2_inv[17] = (~(lv1_or_b[34])); + assign lv2_inv[18] = (~(lv1_or_b[36])); + assign lv2_inv[19] = (~(lv1_or_b[38])); + assign lv2_inv[20] = (~(lv1_or_b[40])); + assign lv2_inv[21] = (~(lv1_or_b[42])); + assign lv2_inv[22] = (~(lv1_or_b[44])); + assign lv2_inv[23] = (~(lv1_or_b[46])); + assign lv2_inv[24] = (~(lv1_or_b[48])); + assign lv2_inv[25] = (~(lv1_or_b[50])); + assign lv2_inv[26] = (~(lv1_or_b[52])); + assign lv2_inv[27] = (~(lv1_or_b[54])); + assign lv2_inv[28] = (~(lv1_or_b[56])); + assign lv2_inv[29] = (~(lv1_or_b[58])); + assign lv2_inv[30] = (~(lv1_or_b[60])); + assign lv2_inv[31] = (~(lv1_or_b[62])); + assign lv2_inv[32] = (~(lv1_or_b[64])); + assign lv2_inv[33] = (~(lv1_or_b[66])); + assign lv2_inv[34] = (~(lv1_or_b[68])); + assign lv2_inv[35] = (~(lv1_or_b[70])); + assign lv2_inv[36] = (~(lv1_or_b[72])); + assign lv2_inv[37] = (~(lv1_or_b[74])); + assign lv2_inv[38] = (~(lv1_or_b[76])); + assign lv2_inv[39] = (~(lv1_or_b[78])); + assign lv2_inv[40] = (~(lv1_or_b[80])); + + assign lv2_enc6[0] = (~(lv2_inv[0] | lv1_or_b[1])); + assign lv2_enc6[1] = (~(lv2_inv[1] | lv1_or_b[3])); + assign lv2_enc6[2] = (~(lv2_inv[2] | lv1_or_b[5])); + assign lv2_enc6[3] = (~(lv2_inv[3] | lv1_or_b[7])); + assign lv2_enc6[4] = (~(lv2_inv[4] | lv1_or_b[9])); + assign lv2_enc6[5] = (~(lv2_inv[5] | lv1_or_b[11])); + assign lv2_enc6[6] = (~(lv2_inv[6] | lv1_or_b[13])); + assign lv2_enc6[7] = (~(lv2_inv[7] | lv1_or_b[15])); + assign lv2_enc6[8] = (~(lv2_inv[8] | lv1_or_b[17])); + assign lv2_enc6[9] = (~(lv2_inv[9] | lv1_or_b[19])); + assign lv2_enc6[10] = (~(lv2_inv[10] | lv1_or_b[21])); + assign lv2_enc6[11] = (~(lv2_inv[11] | lv1_or_b[23])); + assign lv2_enc6[12] = (~(lv2_inv[12] | lv1_or_b[25])); + assign lv2_enc6[13] = (~(lv2_inv[13] | lv1_or_b[27])); + assign lv2_enc6[14] = (~(lv2_inv[14] | lv1_or_b[29])); + assign lv2_enc6[15] = (~(lv2_inv[15] | lv1_or_b[31])); + assign lv2_enc6[16] = (~(lv2_inv[16] | lv1_or_b[33])); + assign lv2_enc6[17] = (~(lv2_inv[17] | lv1_or_b[35])); + assign lv2_enc6[18] = (~(lv2_inv[18] | lv1_or_b[37])); + assign lv2_enc6[19] = (~(lv2_inv[19] | lv1_or_b[39])); + assign lv2_enc6[20] = (~(lv2_inv[20] | lv1_or_b[41])); + assign lv2_enc6[21] = (~(lv2_inv[21] | lv1_or_b[43])); + assign lv2_enc6[22] = (~(lv2_inv[22] | lv1_or_b[45])); + assign lv2_enc6[23] = (~(lv2_inv[23] | lv1_or_b[47])); + assign lv2_enc6[24] = (~(lv2_inv[24] | lv1_or_b[49])); + assign lv2_enc6[25] = (~(lv2_inv[25] | lv1_or_b[51])); + assign lv2_enc6[26] = (~(lv2_inv[26] | lv1_or_b[53])); + assign lv2_enc6[27] = (~(lv2_inv[27] | lv1_or_b[55])); + assign lv2_enc6[28] = (~(lv2_inv[28] | lv1_or_b[57])); + assign lv2_enc6[29] = (~(lv2_inv[29] | lv1_or_b[59])); + assign lv2_enc6[30] = (~(lv2_inv[30] | lv1_or_b[61])); + assign lv2_enc6[31] = (~(lv2_inv[31] | lv1_or_b[63])); + assign lv2_enc6[32] = (~(lv2_inv[32] | lv1_or_b[65])); + assign lv2_enc6[33] = (~(lv2_inv[33] | lv1_or_b[67])); + assign lv2_enc6[34] = (~(lv2_inv[34] | lv1_or_b[69])); + assign lv2_enc6[35] = (~(lv2_inv[35] | lv1_or_b[71])); + assign lv2_enc6[36] = (~(lv2_inv[36] | lv1_or_b[73])); + assign lv2_enc6[37] = (~(lv2_inv[37] | lv1_or_b[75])); + assign lv2_enc6[38] = (~(lv2_inv[38] | lv1_or_b[77])); + assign lv2_enc6[39] = (~(lv2_inv[39] | lv1_or_b[79])); + assign lv2_enc6[40] = (~(lv2_inv[40])); //dflt1 + + assign lv2_enc7[0] = (~(lv1_enc7_b[0] & (lv1_enc7_b[1] | lv2_inv[0]))); + assign lv2_enc7[1] = (~(lv1_enc7_b[2] & (lv1_enc7_b[3] | lv2_inv[1]))); + assign lv2_enc7[2] = (~(lv1_enc7_b[4] & (lv1_enc7_b[5] | lv2_inv[2]))); + assign lv2_enc7[3] = (~(lv1_enc7_b[6] & (lv1_enc7_b[7] | lv2_inv[3]))); + assign lv2_enc7[4] = (~(lv1_enc7_b[8] & (lv1_enc7_b[9] | lv2_inv[4]))); + assign lv2_enc7[5] = (~(lv1_enc7_b[10] & (lv1_enc7_b[11] | lv2_inv[5]))); + assign lv2_enc7[6] = (~(lv1_enc7_b[12] & (lv1_enc7_b[13] | lv2_inv[6]))); + assign lv2_enc7[7] = (~(lv1_enc7_b[14] & (lv1_enc7_b[15] | lv2_inv[7]))); + assign lv2_enc7[8] = (~(lv1_enc7_b[16] & (lv1_enc7_b[17] | lv2_inv[8]))); + assign lv2_enc7[9] = (~(lv1_enc7_b[18] & (lv1_enc7_b[19] | lv2_inv[9]))); + assign lv2_enc7[10] = (~(lv1_enc7_b[20] & (lv1_enc7_b[21] | lv2_inv[10]))); + assign lv2_enc7[11] = (~(lv1_enc7_b[22] & (lv1_enc7_b[23] | lv2_inv[11]))); + assign lv2_enc7[12] = (~(lv1_enc7_b[24] & (lv1_enc7_b[25] | lv2_inv[12]))); + assign lv2_enc7[13] = (~(lv1_enc7_b[26] & (lv1_enc7_b[27] | lv2_inv[13]))); + assign lv2_enc7[14] = (~(lv1_enc7_b[28] & (lv1_enc7_b[29] | lv2_inv[14]))); + assign lv2_enc7[15] = (~(lv1_enc7_b[30] & (lv1_enc7_b[31] | lv2_inv[15]))); + assign lv2_enc7[16] = (~(lv1_enc7_b[32] & (lv1_enc7_b[33] | lv2_inv[16]))); + assign lv2_enc7[17] = (~(lv1_enc7_b[34] & (lv1_enc7_b[35] | lv2_inv[17]))); + assign lv2_enc7[18] = (~(lv1_enc7_b[36] & (lv1_enc7_b[37] | lv2_inv[18]))); + assign lv2_enc7[19] = (~(lv1_enc7_b[38] & (lv1_enc7_b[39] | lv2_inv[19]))); + assign lv2_enc7[20] = (~(lv1_enc7_b[40] & (lv1_enc7_b[41] | lv2_inv[20]))); + assign lv2_enc7[21] = (~(lv1_enc7_b[42] & (lv1_enc7_b[43] | lv2_inv[21]))); + assign lv2_enc7[22] = (~(lv1_enc7_b[44] & (lv1_enc7_b[45] | lv2_inv[22]))); + assign lv2_enc7[23] = (~(lv1_enc7_b[46] & (lv1_enc7_b[47] | lv2_inv[23]))); + assign lv2_enc7[24] = (~(lv1_enc7_b[48] & (lv1_enc7_b[49] | lv2_inv[24]))); + assign lv2_enc7[25] = (~(lv1_enc7_b[50] & (lv1_enc7_b[51] | lv2_inv[25]))); + assign lv2_enc7[26] = (~(lv1_enc7_b[52] & (lv1_enc7_b[53] | lv2_inv[26]))); + assign lv2_enc7[27] = (~(lv1_enc7_b[54] & (lv1_enc7_b[55] | lv2_inv[27]))); + assign lv2_enc7[28] = (~(lv1_enc7_b[56] & (lv1_enc7_b[57] | lv2_inv[28]))); + assign lv2_enc7[29] = (~(lv1_enc7_b[58] & (lv1_enc7_b[59] | lv2_inv[29]))); + assign lv2_enc7[30] = (~(lv1_enc7_b[60] & (lv1_enc7_b[61] | lv2_inv[30]))); + assign lv2_enc7[31] = (~(lv1_enc7_b[62] & (lv1_enc7_b[63] | lv2_inv[31]))); + assign lv2_enc7[32] = (~(lv1_enc7_b[64] & (lv1_enc7_b[65] | lv2_inv[32]))); + assign lv2_enc7[33] = (~(lv1_enc7_b[66] & (lv1_enc7_b[67] | lv2_inv[33]))); + assign lv2_enc7[34] = (~(lv1_enc7_b[68] & (lv1_enc7_b[69] | lv2_inv[34]))); + assign lv2_enc7[35] = (~(lv1_enc7_b[70] & (lv1_enc7_b[71] | lv2_inv[35]))); + assign lv2_enc7[36] = (~(lv1_enc7_b[72] & (lv1_enc7_b[73] | lv2_inv[36]))); + assign lv2_enc7[37] = (~(lv1_enc7_b[74] & (lv1_enc7_b[75] | lv2_inv[37]))); + assign lv2_enc7[38] = (~(lv1_enc7_b[76] & (lv1_enc7_b[77] | lv2_inv[38]))); + assign lv2_enc7[39] = (~(lv1_enc7_b[78] & (lv1_enc7_b[79] | lv2_inv[39]))); + assign lv2_enc7[40] = (~(lv1_enc7_b[80] & (lv1_enc7_b[81] | lv2_inv[40]))); + + //-------------------------------------------------------------------------------- + // 008 bit group (phase_in=P, phase_out=N, level_in=lv2, level_out=lv3) + //-------------------------------------------------------------------------------- + + assign lv3_or_b[0] = (~(lv2_or[0] | lv2_or[1])); + assign lv3_or_b[1] = (~(lv2_or[2] | lv2_or[3])); + assign lv3_or_b[2] = (~(lv2_or[4] | lv2_or[5])); + assign lv3_or_b[3] = (~(lv2_or[6] | lv2_or[7])); + assign lv3_or_b[4] = (~(lv2_or[8] | lv2_or[9])); + assign lv3_or_b[5] = (~(lv2_or[10] | lv2_or[11])); + assign lv3_or_b[6] = (~(lv2_or[12] | lv2_or[13])); + assign lv3_or_b[7] = (~(lv2_or[14] | lv2_or[15])); + assign lv3_or_b[8] = (~(lv2_or[16] | lv2_or[17])); + assign lv3_or_b[9] = (~(lv2_or[18] | lv2_or[19])); + assign lv3_or_b[10] = (~(lv2_or[20] | lv2_or[21])); + assign lv3_or_b[11] = (~(lv2_or[22] | lv2_or[23])); + assign lv3_or_b[12] = (~(lv2_or[24] | lv2_or[25])); + assign lv3_or_b[13] = (~(lv2_or[26] | lv2_or[27])); + assign lv3_or_b[14] = (~(lv2_or[28] | lv2_or[29])); + assign lv3_or_b[15] = (~(lv2_or[30] | lv2_or[31])); + assign lv3_or_b[16] = (~(lv2_or[32] | lv2_or[33])); + assign lv3_or_b[17] = (~(lv2_or[34] | lv2_or[35])); + assign lv3_or_b[18] = (~(lv2_or[36] | lv2_or[37])); + assign lv3_or_b[19] = (~(lv2_or[38] | lv2_or[39])); + assign lv3_or_b[20] = (~(lv2_or[40])); + + assign lv3_inv_b[0] = (~(lv2_or[0])); + assign lv3_inv_b[1] = (~(lv2_or[2])); + assign lv3_inv_b[2] = (~(lv2_or[4])); + assign lv3_inv_b[3] = (~(lv2_or[6])); + assign lv3_inv_b[4] = (~(lv2_or[8])); + assign lv3_inv_b[5] = (~(lv2_or[10])); + assign lv3_inv_b[6] = (~(lv2_or[12])); + assign lv3_inv_b[7] = (~(lv2_or[14])); + assign lv3_inv_b[8] = (~(lv2_or[16])); + assign lv3_inv_b[9] = (~(lv2_or[18])); + assign lv3_inv_b[10] = (~(lv2_or[20])); + assign lv3_inv_b[11] = (~(lv2_or[22])); + assign lv3_inv_b[12] = (~(lv2_or[24])); + assign lv3_inv_b[13] = (~(lv2_or[26])); + assign lv3_inv_b[14] = (~(lv2_or[28])); + assign lv3_inv_b[15] = (~(lv2_or[30])); + assign lv3_inv_b[16] = (~(lv2_or[32])); + assign lv3_inv_b[17] = (~(lv2_or[34])); + assign lv3_inv_b[18] = (~(lv2_or[36])); + assign lv3_inv_b[19] = (~(lv2_or[38])); + assign lv3_inv_b[20] = (~(lv2_or[40])); + + assign lv3_enc5_b[0] = (~(lv3_inv_b[0] & lv2_or[1])); + assign lv3_enc5_b[1] = (~(lv3_inv_b[1] & lv2_or[3])); + assign lv3_enc5_b[2] = (~(lv3_inv_b[2] & lv2_or[5])); + assign lv3_enc5_b[3] = (~(lv3_inv_b[3] & lv2_or[7])); + assign lv3_enc5_b[4] = (~(lv3_inv_b[4] & lv2_or[9])); + assign lv3_enc5_b[5] = (~(lv3_inv_b[5] & lv2_or[11])); + assign lv3_enc5_b[6] = (~(lv3_inv_b[6] & lv2_or[13])); + assign lv3_enc5_b[7] = (~(lv3_inv_b[7] & lv2_or[15])); + assign lv3_enc5_b[8] = (~(lv3_inv_b[8] & lv2_or[17])); + assign lv3_enc5_b[9] = (~(lv3_inv_b[9] & lv2_or[19])); + assign lv3_enc5_b[10] = (~(lv3_inv_b[10] & lv2_or[21])); + assign lv3_enc5_b[11] = (~(lv3_inv_b[11] & lv2_or[23])); + assign lv3_enc5_b[12] = (~(lv3_inv_b[12] & lv2_or[25])); + assign lv3_enc5_b[13] = (~(lv3_inv_b[13] & lv2_or[27])); + assign lv3_enc5_b[14] = (~(lv3_inv_b[14] & lv2_or[29])); + assign lv3_enc5_b[15] = (~(lv3_inv_b[15] & lv2_or[31])); + assign lv3_enc5_b[16] = (~(lv3_inv_b[16] & lv2_or[33])); + assign lv3_enc5_b[17] = (~(lv3_inv_b[17] & lv2_or[35])); + assign lv3_enc5_b[18] = (~(lv3_inv_b[18] & lv2_or[37])); + assign lv3_enc5_b[19] = (~(lv3_inv_b[19] & lv2_or[39])); + assign lv3_enc5_b[20] = tiup; //dflt0 + + assign lv3_enc6_b[0] = (~(lv2_enc6[0] | (lv2_enc6[1] & lv3_inv_b[0]))); + assign lv3_enc6_b[1] = (~(lv2_enc6[2] | (lv2_enc6[3] & lv3_inv_b[1]))); + assign lv3_enc6_b[2] = (~(lv2_enc6[4] | (lv2_enc6[5] & lv3_inv_b[2]))); + assign lv3_enc6_b[3] = (~(lv2_enc6[6] | (lv2_enc6[7] & lv3_inv_b[3]))); + assign lv3_enc6_b[4] = (~(lv2_enc6[8] | (lv2_enc6[9] & lv3_inv_b[4]))); + assign lv3_enc6_b[5] = (~(lv2_enc6[10] | (lv2_enc6[11] & lv3_inv_b[5]))); + assign lv3_enc6_b[6] = (~(lv2_enc6[12] | (lv2_enc6[13] & lv3_inv_b[6]))); + assign lv3_enc6_b[7] = (~(lv2_enc6[14] | (lv2_enc6[15] & lv3_inv_b[7]))); + assign lv3_enc6_b[8] = (~(lv2_enc6[16] | (lv2_enc6[17] & lv3_inv_b[8]))); + assign lv3_enc6_b[9] = (~(lv2_enc6[18] | (lv2_enc6[19] & lv3_inv_b[9]))); + assign lv3_enc6_b[10] = (~(lv2_enc6[20] | (lv2_enc6[21] & lv3_inv_b[10]))); + assign lv3_enc6_b[11] = (~(lv2_enc6[22] | (lv2_enc6[23] & lv3_inv_b[11]))); + assign lv3_enc6_b[12] = (~(lv2_enc6[24] | (lv2_enc6[25] & lv3_inv_b[12]))); + assign lv3_enc6_b[13] = (~(lv2_enc6[26] | (lv2_enc6[27] & lv3_inv_b[13]))); + assign lv3_enc6_b[14] = (~(lv2_enc6[28] | (lv2_enc6[29] & lv3_inv_b[14]))); + assign lv3_enc6_b[15] = (~(lv2_enc6[30] | (lv2_enc6[31] & lv3_inv_b[15]))); + assign lv3_enc6_b[16] = (~(lv2_enc6[32] | (lv2_enc6[33] & lv3_inv_b[16]))); + assign lv3_enc6_b[17] = (~(lv2_enc6[34] | (lv2_enc6[35] & lv3_inv_b[17]))); + assign lv3_enc6_b[18] = (~(lv2_enc6[36] | (lv2_enc6[37] & lv3_inv_b[18]))); + assign lv3_enc6_b[19] = (~(lv2_enc6[38] | (lv2_enc6[39] & lv3_inv_b[19]))); + assign lv3_enc6_b[20] = (~(lv2_enc6[40] | lv3_inv_b[20])); //dflt1 + + assign lv3_enc7_b[0] = (~(lv2_enc7[0] | (lv2_enc7[1] & lv3_inv_b[0]))); + assign lv3_enc7_b[1] = (~(lv2_enc7[2] | (lv2_enc7[3] & lv3_inv_b[1]))); + assign lv3_enc7_b[2] = (~(lv2_enc7[4] | (lv2_enc7[5] & lv3_inv_b[2]))); + assign lv3_enc7_b[3] = (~(lv2_enc7[6] | (lv2_enc7[7] & lv3_inv_b[3]))); + assign lv3_enc7_b[4] = (~(lv2_enc7[8] | (lv2_enc7[9] & lv3_inv_b[4]))); + assign lv3_enc7_b[5] = (~(lv2_enc7[10] | (lv2_enc7[11] & lv3_inv_b[5]))); + assign lv3_enc7_b[6] = (~(lv2_enc7[12] | (lv2_enc7[13] & lv3_inv_b[6]))); + assign lv3_enc7_b[7] = (~(lv2_enc7[14] | (lv2_enc7[15] & lv3_inv_b[7]))); + assign lv3_enc7_b[8] = (~(lv2_enc7[16] | (lv2_enc7[17] & lv3_inv_b[8]))); + assign lv3_enc7_b[9] = (~(lv2_enc7[18] | (lv2_enc7[19] & lv3_inv_b[9]))); + assign lv3_enc7_b[10] = (~(lv2_enc7[20] | (lv2_enc7[21] & lv3_inv_b[10]))); + assign lv3_enc7_b[11] = (~(lv2_enc7[22] | (lv2_enc7[23] & lv3_inv_b[11]))); + assign lv3_enc7_b[12] = (~(lv2_enc7[24] | (lv2_enc7[25] & lv3_inv_b[12]))); + assign lv3_enc7_b[13] = (~(lv2_enc7[26] | (lv2_enc7[27] & lv3_inv_b[13]))); + assign lv3_enc7_b[14] = (~(lv2_enc7[28] | (lv2_enc7[29] & lv3_inv_b[14]))); + assign lv3_enc7_b[15] = (~(lv2_enc7[30] | (lv2_enc7[31] & lv3_inv_b[15]))); + assign lv3_enc7_b[16] = (~(lv2_enc7[32] | (lv2_enc7[33] & lv3_inv_b[16]))); + assign lv3_enc7_b[17] = (~(lv2_enc7[34] | (lv2_enc7[35] & lv3_inv_b[17]))); + assign lv3_enc7_b[18] = (~(lv2_enc7[36] | (lv2_enc7[37] & lv3_inv_b[18]))); + assign lv3_enc7_b[19] = (~(lv2_enc7[38] | (lv2_enc7[39] & lv3_inv_b[19]))); + assign lv3_enc7_b[20] = (~(lv2_enc7[40] | lv3_inv_b[20])); //dflt1 + + //-------------------------------------------------------------------------------- + // 016 bit group (phase_in=N, phase_out=P, level_in=lv3, level_out=lv4) + //-------------------------------------------------------------------------------- + + assign lv4_or[0] = (~(lv3_or_b[0] & lv3_or_b[1])); + assign lv4_or[1] = (~(lv3_or_b[2] & lv3_or_b[3])); + assign lv4_or[2] = (~(lv3_or_b[4] & lv3_or_b[5])); + assign lv4_or[3] = (~(lv3_or_b[6] & lv3_or_b[7])); + assign lv4_or[4] = (~(lv3_or_b[8] & lv3_or_b[9])); + assign lv4_or[5] = (~(lv3_or_b[10] & lv3_or_b[11])); + assign lv4_or[6] = (~(lv3_or_b[12] & lv3_or_b[13])); + assign lv4_or[7] = (~(lv3_or_b[14] & lv3_or_b[15])); + assign lv4_or[8] = (~(lv3_or_b[16] & lv3_or_b[17])); + assign lv4_or[9] = (~(lv3_or_b[18] & lv3_or_b[19])); + assign lv4_or[10] = (~(lv3_or_b[20])); + + assign lv4_inv[0] = (~(lv3_or_b[0])); + assign lv4_inv[1] = (~(lv3_or_b[2])); + assign lv4_inv[2] = (~(lv3_or_b[4])); + assign lv4_inv[3] = (~(lv3_or_b[6])); + assign lv4_inv[4] = (~(lv3_or_b[8])); + assign lv4_inv[5] = (~(lv3_or_b[10])); + assign lv4_inv[6] = (~(lv3_or_b[12])); + assign lv4_inv[7] = (~(lv3_or_b[14])); + assign lv4_inv[8] = (~(lv3_or_b[16])); + assign lv4_inv[9] = (~(lv3_or_b[18])); + assign lv4_inv[10] = (~(lv3_or_b[20])); + + assign lv4_enc4[0] = (~(lv4_inv[0] | lv3_or_b[1])); + assign lv4_enc4[1] = (~(lv4_inv[1] | lv3_or_b[3])); + assign lv4_enc4[2] = (~(lv4_inv[2] | lv3_or_b[5])); + assign lv4_enc4[3] = (~(lv4_inv[3] | lv3_or_b[7])); + assign lv4_enc4[4] = (~(lv4_inv[4] | lv3_or_b[9])); + assign lv4_enc4[5] = (~(lv4_inv[5] | lv3_or_b[11])); + assign lv4_enc4[6] = (~(lv4_inv[6] | lv3_or_b[13])); + assign lv4_enc4[7] = (~(lv4_inv[7] | lv3_or_b[15])); + assign lv4_enc4[8] = (~(lv4_inv[8] | lv3_or_b[17])); + assign lv4_enc4[9] = (~(lv4_inv[9] | lv3_or_b[19])); + assign lv4_enc4[10] = tidn; //dflt0 + + assign lv4_enc5[0] = (~(lv3_enc5_b[0] & (lv3_enc5_b[1] | lv4_inv[0]))); + assign lv4_enc5[1] = (~(lv3_enc5_b[2] & (lv3_enc5_b[3] | lv4_inv[1]))); + assign lv4_enc5[2] = (~(lv3_enc5_b[4] & (lv3_enc5_b[5] | lv4_inv[2]))); + assign lv4_enc5[3] = (~(lv3_enc5_b[6] & (lv3_enc5_b[7] | lv4_inv[3]))); + assign lv4_enc5[4] = (~(lv3_enc5_b[8] & (lv3_enc5_b[9] | lv4_inv[4]))); + assign lv4_enc5[5] = (~(lv3_enc5_b[10] & (lv3_enc5_b[11] | lv4_inv[5]))); + assign lv4_enc5[6] = (~(lv3_enc5_b[12] & (lv3_enc5_b[13] | lv4_inv[6]))); + assign lv4_enc5[7] = (~(lv3_enc5_b[14] & (lv3_enc5_b[15] | lv4_inv[7]))); + assign lv4_enc5[8] = (~(lv3_enc5_b[16] & (lv3_enc5_b[17] | lv4_inv[8]))); + assign lv4_enc5[9] = (~(lv3_enc5_b[18] & (lv3_enc5_b[19] | lv4_inv[9]))); + assign lv4_enc5[10] = (~(lv3_enc5_b[20])); //dflt0 pass + + assign lv4_enc6[0] = (~(lv3_enc6_b[0] & (lv3_enc6_b[1] | lv4_inv[0]))); + assign lv4_enc6[1] = (~(lv3_enc6_b[2] & (lv3_enc6_b[3] | lv4_inv[1]))); + assign lv4_enc6[2] = (~(lv3_enc6_b[4] & (lv3_enc6_b[5] | lv4_inv[2]))); + assign lv4_enc6[3] = (~(lv3_enc6_b[6] & (lv3_enc6_b[7] | lv4_inv[3]))); + assign lv4_enc6[4] = (~(lv3_enc6_b[8] & (lv3_enc6_b[9] | lv4_inv[4]))); + assign lv4_enc6[5] = (~(lv3_enc6_b[10] & (lv3_enc6_b[11] | lv4_inv[5]))); + assign lv4_enc6[6] = (~(lv3_enc6_b[12] & (lv3_enc6_b[13] | lv4_inv[6]))); + assign lv4_enc6[7] = (~(lv3_enc6_b[14] & (lv3_enc6_b[15] | lv4_inv[7]))); + assign lv4_enc6[8] = (~(lv3_enc6_b[16] & (lv3_enc6_b[17] | lv4_inv[8]))); + assign lv4_enc6[9] = (~(lv3_enc6_b[18] & (lv3_enc6_b[19] | lv4_inv[9]))); + assign lv4_enc6[10] = (~(lv3_enc6_b[20] & lv4_inv[10])); //dflt1 + + assign lv4_enc7[0] = (~(lv3_enc7_b[0] & (lv3_enc7_b[1] | lv4_inv[0]))); + assign lv4_enc7[1] = (~(lv3_enc7_b[2] & (lv3_enc7_b[3] | lv4_inv[1]))); + assign lv4_enc7[2] = (~(lv3_enc7_b[4] & (lv3_enc7_b[5] | lv4_inv[2]))); + assign lv4_enc7[3] = (~(lv3_enc7_b[6] & (lv3_enc7_b[7] | lv4_inv[3]))); + assign lv4_enc7[4] = (~(lv3_enc7_b[8] & (lv3_enc7_b[9] | lv4_inv[4]))); + assign lv4_enc7[5] = (~(lv3_enc7_b[10] & (lv3_enc7_b[11] | lv4_inv[5]))); + assign lv4_enc7[6] = (~(lv3_enc7_b[12] & (lv3_enc7_b[13] | lv4_inv[6]))); + assign lv4_enc7[7] = (~(lv3_enc7_b[14] & (lv3_enc7_b[15] | lv4_inv[7]))); + assign lv4_enc7[8] = (~(lv3_enc7_b[16] & (lv3_enc7_b[17] | lv4_inv[8]))); + assign lv4_enc7[9] = (~(lv3_enc7_b[18] & (lv3_enc7_b[19] | lv4_inv[9]))); + assign lv4_enc7[10] = (~(lv3_enc7_b[20] & lv4_inv[10])); //dflt1 + + assign lv4_or_b[0] = (~(lv4_or[0])); //repower,long wire + assign lv4_or_b[1] = (~(lv4_or[1])); //repower,long wire + assign lv4_or_b[2] = (~(lv4_or[2])); //repower,long wire + assign lv4_or_b[3] = (~(lv4_or[3])); //repower,long wire + assign lv4_or_b[4] = (~(lv4_or[4])); //repower,long wire + assign lv4_or_b[5] = (~(lv4_or[5])); //repower,long wire + assign lv4_or_b[6] = (~(lv4_or[6])); //repower,long wire + assign lv4_or_b[7] = (~(lv4_or[7])); //repower,long wire + assign lv4_or_b[8] = (~(lv4_or[8])); //repower,long wire + assign lv4_or_b[9] = (~(lv4_or[9])); //repower,long wire + assign lv4_or_b[10] = (~(lv4_or[10])); //repower,long wire + assign lv4_enc4_b[0] = (~(lv4_enc4[0])); //repower,long wire + assign lv4_enc4_b[1] = (~(lv4_enc4[1])); //repower,long wire + assign lv4_enc4_b[2] = (~(lv4_enc4[2])); //repower,long wire + assign lv4_enc4_b[3] = (~(lv4_enc4[3])); //repower,long wire + assign lv4_enc4_b[4] = (~(lv4_enc4[4])); //repower,long wire + assign lv4_enc4_b[5] = (~(lv4_enc4[5])); //repower,long wire + assign lv4_enc4_b[6] = (~(lv4_enc4[6])); //repower,long wire + assign lv4_enc4_b[7] = (~(lv4_enc4[7])); //repower,long wire + assign lv4_enc4_b[8] = (~(lv4_enc4[8])); //repower,long wire + assign lv4_enc4_b[9] = (~(lv4_enc4[9])); //repower,long wire + assign lv4_enc4_b[10] = (~(lv4_enc4[10])); //repower,long wire + assign lv4_enc5_b[0] = (~(lv4_enc5[0])); //repower,long wire + assign lv4_enc5_b[1] = (~(lv4_enc5[1])); //repower,long wire + assign lv4_enc5_b[2] = (~(lv4_enc5[2])); //repower,long wire + assign lv4_enc5_b[3] = (~(lv4_enc5[3])); //repower,long wire + assign lv4_enc5_b[4] = (~(lv4_enc5[4])); //repower,long wire + assign lv4_enc5_b[5] = (~(lv4_enc5[5])); //repower,long wire + assign lv4_enc5_b[6] = (~(lv4_enc5[6])); //repower,long wire + assign lv4_enc5_b[7] = (~(lv4_enc5[7])); //repower,long wire + assign lv4_enc5_b[8] = (~(lv4_enc5[8])); //repower,long wire + assign lv4_enc5_b[9] = (~(lv4_enc5[9])); //repower,long wire + assign lv4_enc5_b[10] = (~(lv4_enc5[10])); //repower,long wire + assign lv4_enc6_b[0] = (~(lv4_enc6[0])); //repower,long wire + assign lv4_enc6_b[1] = (~(lv4_enc6[1])); //repower,long wire + assign lv4_enc6_b[2] = (~(lv4_enc6[2])); //repower,long wire + assign lv4_enc6_b[3] = (~(lv4_enc6[3])); //repower,long wire + assign lv4_enc6_b[4] = (~(lv4_enc6[4])); //repower,long wire + assign lv4_enc6_b[5] = (~(lv4_enc6[5])); //repower,long wire + assign lv4_enc6_b[6] = (~(lv4_enc6[6])); //repower,long wire + assign lv4_enc6_b[7] = (~(lv4_enc6[7])); //repower,long wire + assign lv4_enc6_b[8] = (~(lv4_enc6[8])); //repower,long wire + assign lv4_enc6_b[9] = (~(lv4_enc6[9])); //repower,long wire + assign lv4_enc6_b[10] = (~(lv4_enc6[10])); //repower,long wire + assign lv4_enc7_b[0] = (~(lv4_enc7[0])); //repower,long wire + assign lv4_enc7_b[1] = (~(lv4_enc7[1])); //repower,long wire + assign lv4_enc7_b[2] = (~(lv4_enc7[2])); //repower,long wire + assign lv4_enc7_b[3] = (~(lv4_enc7[3])); //repower,long wire + assign lv4_enc7_b[4] = (~(lv4_enc7[4])); //repower,long wire + assign lv4_enc7_b[5] = (~(lv4_enc7[5])); //repower,long wire + assign lv4_enc7_b[6] = (~(lv4_enc7[6])); //repower,long wire + assign lv4_enc7_b[7] = (~(lv4_enc7[7])); //repower,long wire + assign lv4_enc7_b[8] = (~(lv4_enc7[8])); //repower,long wire + assign lv4_enc7_b[9] = (~(lv4_enc7[9])); //repower,long wire + assign lv4_enc7_b[10] = (~(lv4_enc7[10])); //repower,long wire + + //-------------------------------------------------------------------------------- + // 032 bit group (phase_in=N, phase_out=P, level_in=lv4, level_out=lv5) + //-------------------------------------------------------------------------------- + + assign lv5_or[0] = (~(lv4_or_b[0] & lv4_or_b[1])); + assign lv5_or[1] = (~(lv4_or_b[2] & lv4_or_b[3])); + assign lv5_or[2] = (~(lv4_or_b[4] & lv4_or_b[5])); + assign lv5_or[3] = (~(lv4_or_b[6] & lv4_or_b[7])); + assign lv5_or[4] = (~(lv4_or_b[8] & lv4_or_b[9])); + assign lv5_or[5] = (~(lv4_or_b[10])); + + assign lv5_inv[0] = (~(lv4_or_b[0])); + assign lv5_inv[1] = (~(lv4_or_b[2])); + assign lv5_inv[2] = (~(lv4_or_b[4])); + assign lv5_inv[3] = (~(lv4_or_b[6])); + assign lv5_inv[4] = (~(lv4_or_b[8])); + assign lv5_inv[5] = (~(lv4_or_b[10])); + + assign lv5_enc3[0] = (~(lv5_inv[0] | lv4_or_b[1])); + assign lv5_enc3[1] = (~(lv5_inv[1] | lv4_or_b[3])); + assign lv5_enc3[2] = (~(lv5_inv[2] | lv4_or_b[5])); + assign lv5_enc3[3] = (~(lv5_inv[3] | lv4_or_b[7])); + assign lv5_enc3[4] = (~(lv5_inv[4] | lv4_or_b[9])); + assign lv5_enc3[5] = tidn; //dflt0 + + assign lv5_enc4[0] = (~(lv4_enc4_b[0] & (lv4_enc4_b[1] | lv5_inv[0]))); + assign lv5_enc4[1] = (~(lv4_enc4_b[2] & (lv4_enc4_b[3] | lv5_inv[1]))); + assign lv5_enc4[2] = (~(lv4_enc4_b[4] & (lv4_enc4_b[5] | lv5_inv[2]))); + assign lv5_enc4[3] = (~(lv4_enc4_b[6] & (lv4_enc4_b[7] | lv5_inv[3]))); + assign lv5_enc4[4] = (~(lv4_enc4_b[8] & (lv4_enc4_b[9] | lv5_inv[4]))); + assign lv5_enc4[5] = (~(lv4_enc4_b[10])); //dflt0 pass + + assign lv5_enc5[0] = (~(lv4_enc5_b[0] & (lv4_enc5_b[1] | lv5_inv[0]))); + assign lv5_enc5[1] = (~(lv4_enc5_b[2] & (lv4_enc5_b[3] | lv5_inv[1]))); + assign lv5_enc5[2] = (~(lv4_enc5_b[4] & (lv4_enc5_b[5] | lv5_inv[2]))); + assign lv5_enc5[3] = (~(lv4_enc5_b[6] & (lv4_enc5_b[7] | lv5_inv[3]))); + assign lv5_enc5[4] = (~(lv4_enc5_b[8] & (lv4_enc5_b[9] | lv5_inv[4]))); + assign lv5_enc5[5] = (~(lv4_enc5_b[10])); //dflt0 pass + + assign lv5_enc6[0] = (~(lv4_enc6_b[0] & (lv4_enc6_b[1] | lv5_inv[0]))); + assign lv5_enc6[1] = (~(lv4_enc6_b[2] & (lv4_enc6_b[3] | lv5_inv[1]))); + assign lv5_enc6[2] = (~(lv4_enc6_b[4] & (lv4_enc6_b[5] | lv5_inv[2]))); + assign lv5_enc6[3] = (~(lv4_enc6_b[6] & (lv4_enc6_b[7] | lv5_inv[3]))); + assign lv5_enc6[4] = (~(lv4_enc6_b[8] & (lv4_enc6_b[9] | lv5_inv[4]))); + assign lv5_enc6[5] = (~(lv4_enc6_b[10] & lv5_inv[5])); //dflt1 + + assign lv5_enc7[0] = (~(lv4_enc7_b[0] & (lv4_enc7_b[1] | lv5_inv[0]))); + assign lv5_enc7[1] = (~(lv4_enc7_b[2] & (lv4_enc7_b[3] | lv5_inv[1]))); + assign lv5_enc7[2] = (~(lv4_enc7_b[4] & (lv4_enc7_b[5] | lv5_inv[2]))); + assign lv5_enc7[3] = (~(lv4_enc7_b[6] & (lv4_enc7_b[7] | lv5_inv[3]))); + assign lv5_enc7[4] = (~(lv4_enc7_b[8] & (lv4_enc7_b[9] | lv5_inv[4]))); + assign lv5_enc7[5] = (~(lv4_enc7_b[10] & lv5_inv[5])); //dflt1 + + //-------------------------------------------------------------------------------- + // 064 bit group (phase_in=P, phase_out=N, level_in=lv5, level_out=lv6) + //-------------------------------------------------------------------------------- + + assign lv6_or_0 = (~lv6_or_b[0]); + assign lv6_or_1 = (~lv6_or_b[1]); + + assign lv6_or_b[0] = (~(lv5_or[0] | lv5_or[1])); + assign lv6_or_b[1] = (~(lv5_or[2] | lv5_or[3])); + assign lv6_or_b[2] = (~(lv5_or[4] | lv5_or[5])); + + assign lv6_inv_b[0] = (~(lv5_or[0])); + assign lv6_inv_b[1] = (~(lv5_or[2])); + assign lv6_inv_b[2] = (~(lv5_or[4])); + + assign lv6_enc2_b[0] = (~(lv6_inv_b[0] & lv5_or[1])); + assign lv6_enc2_b[1] = (~(lv6_inv_b[1] & lv5_or[3])); + assign lv6_enc2_b[2] = (~(lv6_inv_b[2])); //dflt1 + + assign lv6_enc3_b[0] = (~(lv5_enc3[0] | (lv5_enc3[1] & lv6_inv_b[0]))); + assign lv6_enc3_b[1] = (~(lv5_enc3[2] | (lv5_enc3[3] & lv6_inv_b[1]))); + assign lv6_enc3_b[2] = (~(lv5_enc3[4] | (lv5_enc3[5] & lv6_inv_b[2]))); + + assign lv6_enc4_b[0] = (~(lv5_enc4[0] | (lv5_enc4[1] & lv6_inv_b[0]))); + assign lv6_enc4_b[1] = (~(lv5_enc4[2] | (lv5_enc4[3] & lv6_inv_b[1]))); + assign lv6_enc4_b[2] = (~(lv5_enc4[4] | (lv5_enc4[5] & lv6_inv_b[2]))); + + assign lv6_enc5_b[0] = (~(lv5_enc5[0] | (lv5_enc5[1] & lv6_inv_b[0]))); + assign lv6_enc5_b[1] = (~(lv5_enc5[2] | (lv5_enc5[3] & lv6_inv_b[1]))); + assign lv6_enc5_b[2] = (~(lv5_enc5[4] | (lv5_enc5[5] & lv6_inv_b[2]))); + + assign lv6_enc6_b[0] = (~(lv5_enc6[0] | (lv5_enc6[1] & lv6_inv_b[0]))); + assign lv6_enc6_b[1] = (~(lv5_enc6[2] | (lv5_enc6[3] & lv6_inv_b[1]))); + assign lv6_enc6_b[2] = (~(lv5_enc6[4] | (lv5_enc6[5] & lv6_inv_b[2]))); + + assign lv6_enc7_b[0] = (~(lv5_enc7[0] | (lv5_enc7[1] & lv6_inv_b[0]))); + assign lv6_enc7_b[1] = (~(lv5_enc7[2] | (lv5_enc7[3] & lv6_inv_b[1]))); + assign lv6_enc7_b[2] = (~(lv5_enc7[4] | (lv5_enc7[5] & lv6_inv_b[2]))); + + //-------------------------------------------------------------------------------- + // 128 bit group (phase_in=N, phase_out=P, level_in=lv6, level_out=lv7) + //-------------------------------------------------------------------------------- + + assign lv7_or[0] = (~(lv6_or_b[0] & lv6_or_b[1])); + assign lv7_or[1] = (~(lv6_or_b[2])); + + assign lv7_inv[0] = (~(lv6_or_b[0])); + assign lv7_inv[1] = (~(lv6_or_b[2])); + + assign lv7_enc1[0] = (~(lv7_inv[0] | lv6_or_b[1])); + assign lv7_enc1[1] = tidn; //dflt0 + + assign lv7_enc2[0] = (~(lv6_enc2_b[0] & (lv6_enc2_b[1] | lv7_inv[0]))); + assign lv7_enc2[1] = (~(lv6_enc2_b[2] & lv7_inv[1])); //dflt1 + + assign lv7_enc3[0] = (~(lv6_enc3_b[0] & (lv6_enc3_b[1] | lv7_inv[0]))); + assign lv7_enc3[1] = (~(lv6_enc3_b[2])); //dflt0 pass + + assign lv7_enc4[0] = (~(lv6_enc4_b[0] & (lv6_enc4_b[1] | lv7_inv[0]))); + assign lv7_enc4[1] = (~(lv6_enc4_b[2])); //dflt0 pass + + assign lv7_enc5[0] = (~(lv6_enc5_b[0] & (lv6_enc5_b[1] | lv7_inv[0]))); + assign lv7_enc5[1] = (~(lv6_enc5_b[2])); //dflt0 pass + + assign lv7_enc6[0] = (~(lv6_enc6_b[0] & (lv6_enc6_b[1] | lv7_inv[0]))); + assign lv7_enc6[1] = (~(lv6_enc6_b[2] & lv7_inv[1])); //dflt1 + + assign lv7_enc7[0] = (~(lv6_enc7_b[0] & (lv6_enc7_b[1] | lv7_inv[0]))); + assign lv7_enc7[1] = (~(lv6_enc7_b[2] & lv7_inv[1])); //dflt1 + + //-------------------------------------------------------------------------------- + // 256 bit group (phase_in=P, phase_out=N, level_in=lv7, level_out=lv8) + //-------------------------------------------------------------------------------- + + assign lv8_or_b[0] = (~(lv7_or[0] | lv7_or[1])); + + assign lv8_inv_b[0] = (~(lv7_or[0])); + + assign lv8_enc0_b[0] = (~(lv8_inv_b[0])); //dflt1 + + assign lv8_enc1_b[0] = (~(lv7_enc1[0] | (lv7_enc1[1] & lv8_inv_b[0]))); + + assign lv8_enc2_b[0] = (~(lv7_enc2[0] | (lv7_enc2[1] & lv8_inv_b[0]))); + + assign lv8_enc3_b[0] = (~(lv7_enc3[0] | (lv7_enc3[1] & lv8_inv_b[0]))); + + assign lv8_enc4_b[0] = (~(lv7_enc4[0] | (lv7_enc4[1] & lv8_inv_b[0]))); + + assign lv8_enc5_b[0] = (~(lv7_enc5[0] | (lv7_enc5[1] & lv8_inv_b[0]))); + + assign lv8_enc6_b[0] = (~(lv7_enc6[0] | (lv7_enc6[1] & lv8_inv_b[0]))); + + assign lv8_enc7_b[0] = (~(lv7_enc7[0] | (lv7_enc7[1] & lv8_inv_b[0]))); + + assign lza_any_b = (lv8_or_b[0]); //repower,long wire + assign lza_amt_b[0] = (lv8_enc0_b[0]); //repower,long wire + assign lza_amt_b[1] = (lv8_enc1_b[0]); //repower,long wire + assign lza_amt_b[2] = (lv8_enc2_b[0]); //repower,long wire + assign lza_amt_b[3] = (lv8_enc3_b[0]); //repower,long wire + assign lza_amt_b[4] = (lv8_enc4_b[0]); //repower,long wire + assign lza_amt_b[5] = (lv8_enc5_b[0]); //repower,long wire + assign lza_amt_b[6] = (lv8_enc6_b[0]); //repower,long wire + assign lza_amt_b[7] = (lv8_enc7_b[0]); //repower,long wire + +endmodule diff --git a/dev/verilog/work/fu_lza_ej.v b/dev/verilog/work/fu_lza_ej.v new file mode 100755 index 0000000..e53820a --- /dev/null +++ b/dev/verilog/work/fu_lza_ej.v @@ -0,0 +1,178 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + + `include "tri_a2o.vh" + + +module fu_lza_ej( + effsub, + sum, + car, + lzo_b, + edge_t +); + input effsub; + input [0:162] sum; + input [53:162] car; + input [0:162] lzo_b; + output [0:162] edge_t; + + // generic 3 bit edge :: + // P G !Z + // P Z !G + // !P G !G + // !P Z !Z + + + parameter tiup = 1'b1; + parameter tidn = 1'b0; + + wire [0:52] x0; + wire [0:52] x1; + wire [0:52] x2; + wire [0:52] x1_b; + wire [0:52] ej_b; + wire [53:162] g_b; + wire [53:162] z; + wire [53:162] p; + wire [53:162] g; + wire [53:162] z_b; + wire [53:162] p_b; + wire sum_52_b; + wire lzo_54; + wire [55:162] gz; + wire [55:162] zg; + wire [55:162] gg; + wire [55:162] zz; + wire [53:162] e0_b; + wire [53:162] e1_b; + wire [54:54] e2_b; + wire unused; + + // these are different heights for different bits ... place them as seperate columns + // for 0 :52 + // for 53 + // for 54 + // for 55 + // for 56:162 + + assign unused = g[54] | z_b[53] | z_b[162] | p_b[161] | p_b[162]; + + //------------------------------------------- + // (0:52) only one data input + //------------------------------------------- + + assign x0[0:52] = {tidn, effsub, sum[0:50]}; // just a rename + assign x1[0:52] = {effsub, sum[0:51]}; // just a rename + assign x2[0:52] = sum[0:52]; // just a rename + + assign x1_b[0:52] = (~x1[0:52]); + assign ej_b[0:52] = (~(x1_b[0:52] & (x0[0:52] | x2[0:52]))); + assign edge_t[0:52] = (~(ej_b[0:52] & lzo_b[0:52])); + + //----------------------------------------------------------------- + // (53) psuedo bit + //----------------------------------------------------------------- + + assign g_b[53] = (~(sum[53] & car[53])); + assign z[53] = (~(sum[53] | car[53])); + assign p[53] = (sum[53] ^ car[53]); + + assign g[53] = (~(g_b[53])); + assign z_b[53] = (~(z[53])); //UNUSED + assign p_b[53] = (~(p[53])); + assign sum_52_b = (~(sum[52])); + + assign e0_b[53] = (~(sum[51] & sum_52_b)); + assign e1_b[53] = (~(sum_52_b & g[53])); + assign edge_t[53] = (~(lzo_b[53] & e0_b[53] & e1_b[53])); //output + + //----------------------------------------------------------------- + // (54) pseudo bit + 1 + //----------------------------------------------------------------- + + assign g_b[54] = (~(sum[54] & car[54])); + assign z[54] = (~(sum[54] | car[54])); + assign p[54] = (sum[54] ^ car[54]); + + assign g[54] = (~(g_b[54])); //UNUSED + assign z_b[54] = (~(z[54])); + assign p_b[54] = (~(p[54])); + + assign lzo_54 = (~lzo_b[54]); + + assign e0_b[54] = (~(sum_52_b & p[53] & z_b[54])); //really is p54 (demotes to z54) + assign e1_b[54] = (~(sum[52] & p[53] & g_b[54])); //really is p54 (demotes to z54) + assign e2_b[54] = (~((sum[52] & z[53]) | lzo_54)); + assign edge_t[54] = (~(e0_b[54] & e1_b[54] & e2_b[54])); //output + + //----------------------------------------------------------------- + // (55) pseudo bit + 2 + //----------------------------------------------------------------- + + assign g_b[55] = (~(sum[55] & car[55])); + assign z[55] = (~(sum[55] | car[55])); + assign p[55] = (sum[55] ^ car[55]); + + assign g[55] = (~(g_b[55])); + assign z_b[55] = (~(z[55])); + assign p_b[55] = (~(p[55])); + + assign gz[55] = (~(g_b[54] | z[55])); + assign zg[55] = (~(z_b[54] | g[55])); + assign gg[55] = (~(g_b[54] | g[55])); + assign zz[55] = (~(z_b[54] | z[55])); + + assign e1_b[55] = (~(p_b[53] & (gz[55] | zg[55]))); // P is flipped for psuedo bit + assign e0_b[55] = (~(p[53] & (gg[55] | zz[55]))); // P is flipped for psuedo bit + assign edge_t[55] = (~(e0_b[55] & e1_b[55] & lzo_b[55])); //output + + //----------------------------------------------------------------- + // (56:162) normal 2 input edge_t + //----------------------------------------------------------------- + + assign g_b[56:162] = (~(sum[56:162] & car[56:162])); + assign z[56:162] = (~(sum[56:162] | car[56:162])); + assign p[56:162] = (sum[56:162] ^ car[56:162]); + + assign g[56:162] = (~(g_b[56:162])); + assign z_b[56:162] = (~(z[56:162])); //162 unused + assign p_b[56:162] = (~(p[56:162])); //161,162 unused + + assign gz[56:162] = (~(g_b[55:161] | z[56:162])); + assign zg[56:162] = (~(z_b[55:161] | g[56:162])); + assign gg[56:162] = (~(g_b[55:161] | g[56:162])); + assign zz[56:162] = (~(z_b[55:161] | z[56:162])); + + assign e1_b[56:162] = (~(p[54:160] & (gz[56:162] | zg[56:162]))); + assign e0_b[56:162] = (~(p_b[54:160] & (gg[56:162] | zz[56:162]))); + assign edge_t[56:162] = (~(e0_b[56:162] & e1_b[56:162] & lzo_b[56:162])); //output + +endmodule diff --git a/dev/verilog/work/fu_lze.v b/dev/verilog/work/fu_lze.v new file mode 100755 index 0000000..9c92fcd --- /dev/null +++ b/dev/verilog/work/fu_lze.v @@ -0,0 +1,918 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + + `include "tri_a2o.vh" + + +module fu_lze( + vdd, + gnd, + clkoff_b, + act_dis, + flush, + delay_lclkr, + mpw1_b, + mpw2_b, + sg_1, + thold_1, + fpu_enable, + nclk, + f_lze_si, + f_lze_so, + ex2_act_b, + f_eie_ex3_lzo_expo, + f_eie_ex3_b_expo, + f_eie_ex3_use_bexp, + f_pic_ex3_lzo_dis_prod, + f_pic_ex3_sp_lzo, + f_pic_ex3_est_recip, + f_pic_ex3_est_rsqrt, + f_fmt_ex3_pass_msb_dp, + f_pic_ex3_frsp_ue1, + f_alg_ex3_byp_nonflip, + f_pic_ex3_b_valid, + f_alg_ex3_sel_byp, + f_pic_ex3_to_integer, + f_pic_ex3_prenorm, + f_lze_ex3_lzo_din, + f_lze_ex4_sh_rgt_amt, + f_lze_ex4_sh_rgt_en +); + inout vdd; + inout gnd; + input clkoff_b; // tiup + input act_dis; // ??tidn?? + input flush; // ??tidn?? + input [2:3] delay_lclkr; // tidn, + input [2:3] mpw1_b; // tidn, + input [0:0] mpw2_b; // tidn, + input sg_1; + input thold_1; + input fpu_enable; //dc_act + input [0:`NCLK_WIDTH-1] nclk; + + input f_lze_si; //perv + output f_lze_so; //perv + input ex2_act_b; //act + + input [1:13] f_eie_ex3_lzo_expo; + input [1:13] f_eie_ex3_b_expo; + input f_eie_ex3_use_bexp; + input f_pic_ex3_lzo_dis_prod; + input f_pic_ex3_sp_lzo; + input f_pic_ex3_est_recip; + input f_pic_ex3_est_rsqrt; + input f_fmt_ex3_pass_msb_dp; + input f_pic_ex3_frsp_ue1; + input f_alg_ex3_byp_nonflip; + input f_pic_ex3_b_valid; + input f_alg_ex3_sel_byp; + input f_pic_ex3_to_integer; + input f_pic_ex3_prenorm; + output [0:162] f_lze_ex3_lzo_din; + output [0:7] f_lze_ex4_sh_rgt_amt; + output f_lze_ex4_sh_rgt_en; + + // ENTITY + + + parameter tiup = 1'b1; + parameter tidn = 1'b0; + + wire thold_0_b; + wire thold_0; + wire force_t; + wire sg_0; + wire ex2_act; + wire ex3_act; + (* analysis_not_referenced="TRUE" *) // spare_unused + wire [0:3] spare_unused; + wire ex3_dp_001_by; + wire ex3_sp_001_by; + wire ex3_addr_dp_by; + wire ex3_addr_sp_by; + wire ex3_en_addr_dp_by; + wire ex3_en_addr_sp_by; + wire ex3_lzo_en; + wire ex3_lzo_en_rapsp; + wire ex3_lzo_en_by; + wire ex3_expo_neg_dp_by; + wire ex3_expo_neg_sp_by; + wire ex3_expo_6_adj_by; + wire ex3_addr_dp; + wire ex3_addr_sp; + wire ex3_addr_sp_rap; + wire ex3_en_addr_dp; + wire ex3_en_addr_sp; + wire ex3_en_addr_sp_rap; + wire ex3_lzo_cont; + wire ex3_lzo_cont_dp; + wire ex3_lzo_cont_sp; + wire ex3_expo_neg_dp; + wire ex3_expo_neg_sp; + wire ex3_expo_6_adj; + wire ex3_ins_est; + wire ex3_sh_rgt_en_by; + wire ex3_sh_rgt_en_p; + wire ex3_sh_rgt_en; + wire ex3_lzo_forbyp_0; + wire ex3_lzo_nonbyp_0; + wire ex4_sh_rgt_en; + wire [1:13] ex3_expo_by; + wire [0:0] ex3_lzo_dcd_hi_by; + wire [0:0] ex3_lzo_dcd_lo_by; + wire [1:13] ex3_expo; + wire [0:10] ex3_lzo_dcd_hi; + wire [0:15] ex3_lzo_dcd_lo; + wire [8:13] ex3_expo_p_sim_p; + wire [9:13] ex3_expo_p_sim_g; + wire [8:13] ex3_expo_p_sim; + wire [8:13] ex3_expo_sim_p; + wire [9:13] ex3_expo_sim_g; + wire [8:13] ex3_expo_sim; + wire [0:7] ex3_sh_rgt_amt; + wire [0:8] ex4_shr_so; + wire [0:8] ex4_shr_si; + wire [0:4] act_so; + wire [0:4] act_si; + wire [0:7] ex4_sh_rgt_amt; + wire ex3_lzo_dcd_0; + wire [0:162] ex3_lzo_dcd_b; + (* analysis_not_referenced="TRUE" *) // unused + wire unused; + wire f_alg_ex3_sel_byp_b; + wire ex3_lzo_nonbyp_0_b; + wire ex3_lzo_forbyp_0_b; + //-=############################################################### + //-= map block attributes + //-=############################################################### + + assign unused = ex3_lzo_dcd_b[0]; + + //-=############################################################### + //-= pervasive + //-=############################################################### + + + tri_plat thold_reg_0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(flush), + .din(thold_1), + .q(thold_0) + ); + + + tri_plat sg_reg_0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(flush), + .din(sg_1), + .q(sg_0) + ); + + + tri_lcbor lcbor_0( + .clkoff_b(clkoff_b), + .thold(thold_0), + .sg(sg_0), + .act_dis(act_dis), + .force_t(force_t), + .thold_b(thold_0_b) + ); + + //-=############################################################### + //-= act + //-=############################################################### + + assign ex2_act = (~ex2_act_b); + + + tri_rlmreg_p #(.WIDTH(5), .NEEDS_SRESET(0)) act_lat( + .force_t(force_t), // tidn, + .d_mode(tiup), + .delay_lclkr(delay_lclkr[2]), // tidn, + .mpw1_b(mpw1_b[2]), // tidn, + .mpw2_b(mpw2_b[0]), // tidn, + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(fpu_enable), + .thold_b(thold_0_b), + .sg(sg_0), + .scout(act_so), + .scin(act_si), + //----------------- + .din({ spare_unused[0], + spare_unused[1], + ex2_act, + spare_unused[2], + spare_unused[3]}), + //----------------- + .dout({ spare_unused[0], + spare_unused[1], + ex3_act, + spare_unused[2], + spare_unused[3]}) + ); + + //-=############################################################### + //-= ex3 logic + //-=############################################################### + + assign ex3_dp_001_by = (~ex3_expo_by[1]) & (~ex3_expo_by[2]) & (~ex3_expo_by[3]) & (~ex3_expo_by[4]) & (~ex3_expo_by[5]) & (~ex3_expo_by[6]) & (~ex3_expo_by[7]) & (~ex3_expo_by[8]) & (~ex3_expo_by[9]) & (~ex3_expo_by[10]) & (~ex3_expo_by[11]) & (~ex3_expo_by[12]) & ex3_expo_by[13]; //x001 + + assign ex3_sp_001_by = (~ex3_expo_by[1]) & (~ex3_expo_by[2]) & (~ex3_expo_by[3]) & ex3_expo_by[4] & ex3_expo_by[5] & ex3_expo_by[6] & (~ex3_expo_by[7]) & (~ex3_expo_by[8]) & (~ex3_expo_by[9]) & (~ex3_expo_by[10]) & (~ex3_expo_by[11]) & (~ex3_expo_by[12]) & ex3_expo_by[13]; //x381 + + //---------------------------------------------------------------- + // lzo dcd when B = denorm. + // sp denorm in dp_format may need to denormalize. + // sp is bypassed at [26] so there is room to do this on the left + //---------------------------------------------------------------- + // if B is normalized when bypassed, then no need for denorm because it will not shift left ? + // for EffSub, b MSB can move right 1 position ... only if BFrac = 0000111111,can't if bypass norm + // If B==0 then should NOT bypass ... except for Move instructions. + + assign ex3_expo_by[1:13] = f_eie_ex3_b_expo[1:13]; + + //=#------------------------------------------------ + //=#-- LZO Decode + //=#------------------------------------------------ + // the product exponent points at [0] in the dataflow. + // the lzo puts a marker (false edge) at the point where shifting must stop + // so the lza will not create a denormal exponent. (001/897) dp/sp. + // if p_expo==1 then maker @ 0 + // if p_expo==2 then maker @ 1 + // if p_expo==3 then maker @ 2 + // + // false edges are also used to control shifting for to-integer, aligner-bypass + + assign ex3_addr_dp_by = (~ex3_expo_by[1]) & (~ex3_expo_by[2]) & (~ex3_expo_by[3]) & (~ex3_expo_by[4]) & (~ex3_expo_by[5]); // x001 (1) in bits above decode 256 + + assign ex3_addr_sp_by = (~ex3_expo_by[1]) & (~ex3_expo_by[2]) & (~ex3_expo_by[3]) & ex3_expo_by[4] & ex3_expo_by[5]; // x381 (897) in bits above decode 256 + + assign ex3_en_addr_dp_by = ex3_addr_dp_by & ex3_lzo_cont_dp; + assign ex3_en_addr_sp_by = ex3_addr_sp_by & ex3_lzo_cont_sp; + + // want to avoid shift right for sp op with shOv of sp_den in dp format + // sp is bypassed 26 positions to the left , mark with LZO to create the denorm. + + assign ex3_lzo_en_by = (ex3_en_addr_dp_by | ex3_en_addr_sp_by) & ex3_lzo_cont; + + //decode 0 + assign ex3_expo_neg_dp_by = (ex3_lzo_en_by & ex3_lzo_dcd_hi_by[0] & ex3_lzo_dcd_lo_by[0]) | (ex3_expo_by[1]); //negative exponent + + // dp denorm starts at 0, but sp denorm starts at 896 (x380) + // sp addr 0_0011_xxxx_xxxx covers 0768-1023 + // 0_000x_xxxx_xxxx covers 0000,0001 + // 0_00x0_xxxx_xxxx covers 0000,0010 + + assign ex3_expo_neg_sp_by = (ex3_expo_by[1]) | ((~ex3_expo_by[2]) & (~ex3_expo_by[3]) & (~ex3_expo_by[4])) | ((~ex3_expo_by[2]) & (~ex3_expo_by[3]) & (~ex3_expo_by[5])) | ((~ex3_expo_by[2]) & (~ex3_expo_by[3]) & (~ex3_expo_by[6])) | ((~ex3_expo_by[2]) & (~ex3_expo_by[3]) & ex3_expo_by[4] & ex3_expo_by[5] & ex3_expo_by[6] & (~(ex3_expo_by[7] | ex3_expo_by[8] | ex3_expo_by[9] | ex3_expo_by[10] | ex3_expo_by[11] | ex3_expo_by[12] | ex3_expo_by[13]))); // negative + + assign ex3_expo_6_adj_by = ((~ex3_expo_by[6]) & f_pic_ex3_sp_lzo) | (ex3_expo_by[6] & (~f_pic_ex3_sp_lzo)); + + assign ex3_lzo_dcd_0 = ex3_lzo_dcd_hi[0] & ex3_lzo_dcd_lo[1]; + + assign ex3_lzo_dcd_hi_by[0] = (~ex3_expo_6_adj_by) & (~ex3_expo_by[7]) & (~ex3_expo_by[8]) & (~ex3_expo_by[9]) & ex3_lzo_en_by; + + assign ex3_lzo_dcd_lo_by[0] = (~ex3_expo_by[10]) & (~ex3_expo_by[11]) & (~ex3_expo_by[12]) & (~ex3_expo_by[13]); + + //=#------------------------------------------------ + //=#-- LZO Decode + //=#------------------------------------------------ + // the product exponent points at [0] in the dataflow. + // the lzo puts a marker (false edge) at the point where shifting must stop + // so the lza will not create a denormal exponent. (001/897) dp/sp. + // if p_expo==1 then maker @ 0 + // if p_expo==2 then maker @ 1 + // if p_expo==3 then maker @ 2 + // + // false edges are also used to control shifting for to-integer, aligner-bypass + + assign ex3_expo[1:13] = f_eie_ex3_lzo_expo[1:13]; + assign ex3_addr_dp = (~ex3_expo[1]) & (~ex3_expo[2]) & (~ex3_expo[3]) & (~ex3_expo[4]) & (~ex3_expo[5]); // x001 (1) in bits above decode 256 + + assign ex3_addr_sp = (~ex3_expo[1]) & (~ex3_expo[2]) & (~ex3_expo[3]) & ex3_expo[4] & ex3_expo[5]; // x381 (897) in bits above decode 256 + + assign ex3_addr_sp_rap = (~ex3_expo[1]) & (~ex3_expo[2]) & ex3_expo[3] & (~ex3_expo[4]) & (~ex3_expo[5]); // x381 (897) in bits above decode 256 + + assign ex3_en_addr_dp = ex3_addr_dp & ex3_lzo_cont_dp; + assign ex3_en_addr_sp = ex3_addr_sp & ex3_lzo_cont_sp; + assign ex3_en_addr_sp_rap = ex3_addr_sp_rap & ex3_lzo_cont_sp; + + assign ex3_lzo_cont = (~f_pic_ex3_lzo_dis_prod); + assign ex3_lzo_cont_dp = (~f_pic_ex3_lzo_dis_prod) & (~f_pic_ex3_sp_lzo); + assign ex3_lzo_cont_sp = (~f_pic_ex3_lzo_dis_prod) & f_pic_ex3_sp_lzo; + + // want to avoid shift right for sp op with shOv of sp_den in dp format + // sp is bypassed 26 positions to the left , mark with LZO to create the denorm. + + assign ex3_lzo_en = (ex3_en_addr_dp | ex3_en_addr_sp) & ex3_lzo_cont; + assign ex3_lzo_en_rapsp = (ex3_en_addr_dp | ex3_en_addr_sp_rap) & ex3_lzo_cont; + + //decode 0 + assign ex3_expo_neg_dp = (ex3_lzo_en & ex3_lzo_dcd_hi[0] & ex3_lzo_dcd_lo[0]) | (ex3_expo[1]); //negative exponent + + // dp denorm starts at 0, but sp denorm starts at 896 (x380) + // sp addr 0_0011_xxxx_xxxx covers 0768-1023 + // 0_000x_xxxx_xxxx covers 0000,0001 + // 0_00x0_xxxx_xxxx covers 0000,0010 + + assign ex3_expo_neg_sp = (ex3_expo[1]) | ((~ex3_expo[2]) & (~ex3_expo[3]) & (~ex3_expo[4])) | ((~ex3_expo[2]) & (~ex3_expo[3]) & (~ex3_expo[5])) | ((~ex3_expo[2]) & (~ex3_expo[3]) & (~ex3_expo[6])) | ((~ex3_expo[2]) & (~ex3_expo[3]) & ex3_expo[4] & ex3_expo[5] & ex3_expo[6] & (~(ex3_expo[7] | ex3_expo[8] | ex3_expo[9] | ex3_expo[10] | ex3_expo[11] | ex3_expo[12] | ex3_expo[13]))); // negative + + assign ex3_expo_6_adj = ((~ex3_expo[6]) & f_pic_ex3_sp_lzo) | (ex3_expo[6] & (~f_pic_ex3_sp_lzo)); + + assign ex3_lzo_dcd_hi[0] = (~ex3_expo_6_adj) & (~ex3_expo[7]) & (~ex3_expo[8]) & (~ex3_expo[9]) & ex3_lzo_en; + assign ex3_lzo_dcd_hi[1] = (~ex3_expo_6_adj) & (~ex3_expo[7]) & (~ex3_expo[8]) & ex3_expo[9] & ex3_lzo_en; + assign ex3_lzo_dcd_hi[2] = (~ex3_expo_6_adj) & (~ex3_expo[7]) & ex3_expo[8] & (~ex3_expo[9]) & ex3_lzo_en; + assign ex3_lzo_dcd_hi[3] = (~ex3_expo_6_adj) & (~ex3_expo[7]) & ex3_expo[8] & ex3_expo[9] & ex3_lzo_en; + assign ex3_lzo_dcd_hi[4] = (~ex3_expo_6_adj) & ex3_expo[7] & (~ex3_expo[8]) & (~ex3_expo[9]) & ex3_lzo_en; + assign ex3_lzo_dcd_hi[5] = (~ex3_expo_6_adj) & ex3_expo[7] & (~ex3_expo[8]) & ex3_expo[9] & ex3_lzo_en; + assign ex3_lzo_dcd_hi[6] = (~ex3_expo_6_adj) & ex3_expo[7] & ex3_expo[8] & (~ex3_expo[9]) & ex3_lzo_en; + assign ex3_lzo_dcd_hi[7] = (~ex3_expo_6_adj) & ex3_expo[7] & ex3_expo[8] & ex3_expo[9] & ex3_lzo_en; + assign ex3_lzo_dcd_hi[8] = ex3_expo_6_adj & (~ex3_expo[7]) & (~ex3_expo[8]) & (~ex3_expo[9]) & ex3_lzo_en_rapsp; + assign ex3_lzo_dcd_hi[9] = ex3_expo_6_adj & (~ex3_expo[7]) & (~ex3_expo[8]) & ex3_expo[9] & ex3_lzo_en_rapsp; + assign ex3_lzo_dcd_hi[10] = ex3_expo_6_adj & (~ex3_expo[7]) & ex3_expo[8] & (~ex3_expo[9]) & ex3_lzo_en_rapsp; + + assign ex3_lzo_dcd_lo[0] = (~ex3_expo[10]) & (~ex3_expo[11]) & (~ex3_expo[12]) & (~ex3_expo[13]); + assign ex3_lzo_dcd_lo[1] = (~ex3_expo[10]) & (~ex3_expo[11]) & (~ex3_expo[12]) & ex3_expo[13]; + assign ex3_lzo_dcd_lo[2] = (~ex3_expo[10]) & (~ex3_expo[11]) & ex3_expo[12] & (~ex3_expo[13]); + assign ex3_lzo_dcd_lo[3] = (~ex3_expo[10]) & (~ex3_expo[11]) & ex3_expo[12] & ex3_expo[13]; + assign ex3_lzo_dcd_lo[4] = (~ex3_expo[10]) & ex3_expo[11] & (~ex3_expo[12]) & (~ex3_expo[13]); + assign ex3_lzo_dcd_lo[5] = (~ex3_expo[10]) & ex3_expo[11] & (~ex3_expo[12]) & ex3_expo[13]; + assign ex3_lzo_dcd_lo[6] = (~ex3_expo[10]) & ex3_expo[11] & ex3_expo[12] & (~ex3_expo[13]); + assign ex3_lzo_dcd_lo[7] = (~ex3_expo[10]) & ex3_expo[11] & ex3_expo[12] & ex3_expo[13]; + assign ex3_lzo_dcd_lo[8] = ex3_expo[10] & (~ex3_expo[11]) & (~ex3_expo[12]) & (~ex3_expo[13]); + assign ex3_lzo_dcd_lo[9] = ex3_expo[10] & (~ex3_expo[11]) & (~ex3_expo[12]) & ex3_expo[13]; + assign ex3_lzo_dcd_lo[10] = ex3_expo[10] & (~ex3_expo[11]) & ex3_expo[12] & (~ex3_expo[13]); + assign ex3_lzo_dcd_lo[11] = ex3_expo[10] & (~ex3_expo[11]) & ex3_expo[12] & ex3_expo[13]; + assign ex3_lzo_dcd_lo[12] = ex3_expo[10] & ex3_expo[11] & (~ex3_expo[12]) & (~ex3_expo[13]); + assign ex3_lzo_dcd_lo[13] = ex3_expo[10] & ex3_expo[11] & (~ex3_expo[12]) & ex3_expo[13]; + assign ex3_lzo_dcd_lo[14] = ex3_expo[10] & ex3_expo[11] & ex3_expo[12] & (~ex3_expo[13]); + assign ex3_lzo_dcd_lo[15] = ex3_expo[10] & ex3_expo[11] & ex3_expo[12] & ex3_expo[13]; + + assign ex3_lzo_dcd_b[0] = (~(ex3_lzo_dcd_hi[0] & ex3_lzo_dcd_lo[1])); + assign ex3_lzo_dcd_b[1] = (~(ex3_lzo_dcd_hi[0] & ex3_lzo_dcd_lo[2])); + assign ex3_lzo_dcd_b[2] = (~(ex3_lzo_dcd_hi[0] & ex3_lzo_dcd_lo[3])); + assign ex3_lzo_dcd_b[3] = (~(ex3_lzo_dcd_hi[0] & ex3_lzo_dcd_lo[4])); + assign ex3_lzo_dcd_b[4] = (~(ex3_lzo_dcd_hi[0] & ex3_lzo_dcd_lo[5])); + assign ex3_lzo_dcd_b[5] = (~(ex3_lzo_dcd_hi[0] & ex3_lzo_dcd_lo[6])); + assign ex3_lzo_dcd_b[6] = (~(ex3_lzo_dcd_hi[0] & ex3_lzo_dcd_lo[7])); + assign ex3_lzo_dcd_b[7] = (~(ex3_lzo_dcd_hi[0] & ex3_lzo_dcd_lo[8])); + assign ex3_lzo_dcd_b[8] = (~(ex3_lzo_dcd_hi[0] & ex3_lzo_dcd_lo[9])); + assign ex3_lzo_dcd_b[9] = (~(ex3_lzo_dcd_hi[0] & ex3_lzo_dcd_lo[10])); + assign ex3_lzo_dcd_b[10] = (~(ex3_lzo_dcd_hi[0] & ex3_lzo_dcd_lo[11])); + assign ex3_lzo_dcd_b[11] = (~(ex3_lzo_dcd_hi[0] & ex3_lzo_dcd_lo[12])); + assign ex3_lzo_dcd_b[12] = (~(ex3_lzo_dcd_hi[0] & ex3_lzo_dcd_lo[13])); + assign ex3_lzo_dcd_b[13] = (~(ex3_lzo_dcd_hi[0] & ex3_lzo_dcd_lo[14])); + assign ex3_lzo_dcd_b[14] = (~(ex3_lzo_dcd_hi[0] & ex3_lzo_dcd_lo[15])); + + assign ex3_lzo_dcd_b[15] = (~(ex3_lzo_dcd_hi[1] & ex3_lzo_dcd_lo[0])); + assign ex3_lzo_dcd_b[16] = (~(ex3_lzo_dcd_hi[1] & ex3_lzo_dcd_lo[1])); + assign ex3_lzo_dcd_b[17] = (~(ex3_lzo_dcd_hi[1] & ex3_lzo_dcd_lo[2])); + assign ex3_lzo_dcd_b[18] = (~(ex3_lzo_dcd_hi[1] & ex3_lzo_dcd_lo[3])); + assign ex3_lzo_dcd_b[19] = (~(ex3_lzo_dcd_hi[1] & ex3_lzo_dcd_lo[4])); + assign ex3_lzo_dcd_b[20] = (~(ex3_lzo_dcd_hi[1] & ex3_lzo_dcd_lo[5])); + assign ex3_lzo_dcd_b[21] = (~(ex3_lzo_dcd_hi[1] & ex3_lzo_dcd_lo[6])); + assign ex3_lzo_dcd_b[22] = (~(ex3_lzo_dcd_hi[1] & ex3_lzo_dcd_lo[7])); + assign ex3_lzo_dcd_b[23] = (~(ex3_lzo_dcd_hi[1] & ex3_lzo_dcd_lo[8])); + assign ex3_lzo_dcd_b[24] = (~(ex3_lzo_dcd_hi[1] & ex3_lzo_dcd_lo[9])); + assign ex3_lzo_dcd_b[25] = (~(ex3_lzo_dcd_hi[1] & ex3_lzo_dcd_lo[10])); + assign ex3_lzo_dcd_b[26] = (~(ex3_lzo_dcd_hi[1] & ex3_lzo_dcd_lo[11])); + assign ex3_lzo_dcd_b[27] = (~(ex3_lzo_dcd_hi[1] & ex3_lzo_dcd_lo[12])); + assign ex3_lzo_dcd_b[28] = (~(ex3_lzo_dcd_hi[1] & ex3_lzo_dcd_lo[13])); + assign ex3_lzo_dcd_b[29] = (~(ex3_lzo_dcd_hi[1] & ex3_lzo_dcd_lo[14])); + assign ex3_lzo_dcd_b[30] = (~(ex3_lzo_dcd_hi[1] & ex3_lzo_dcd_lo[15])); + + assign ex3_lzo_dcd_b[31] = (~(ex3_lzo_dcd_hi[2] & ex3_lzo_dcd_lo[0])); + assign ex3_lzo_dcd_b[32] = (~(ex3_lzo_dcd_hi[2] & ex3_lzo_dcd_lo[1])); + assign ex3_lzo_dcd_b[33] = (~(ex3_lzo_dcd_hi[2] & ex3_lzo_dcd_lo[2])); + assign ex3_lzo_dcd_b[34] = (~(ex3_lzo_dcd_hi[2] & ex3_lzo_dcd_lo[3])); + assign ex3_lzo_dcd_b[35] = (~(ex3_lzo_dcd_hi[2] & ex3_lzo_dcd_lo[4])); + assign ex3_lzo_dcd_b[36] = (~(ex3_lzo_dcd_hi[2] & ex3_lzo_dcd_lo[5])); + assign ex3_lzo_dcd_b[37] = (~(ex3_lzo_dcd_hi[2] & ex3_lzo_dcd_lo[6])); + assign ex3_lzo_dcd_b[38] = (~(ex3_lzo_dcd_hi[2] & ex3_lzo_dcd_lo[7])); + assign ex3_lzo_dcd_b[39] = (~(ex3_lzo_dcd_hi[2] & ex3_lzo_dcd_lo[8])); + assign ex3_lzo_dcd_b[40] = (~(ex3_lzo_dcd_hi[2] & ex3_lzo_dcd_lo[9])); + assign ex3_lzo_dcd_b[41] = (~(ex3_lzo_dcd_hi[2] & ex3_lzo_dcd_lo[10])); + assign ex3_lzo_dcd_b[42] = (~(ex3_lzo_dcd_hi[2] & ex3_lzo_dcd_lo[11])); + assign ex3_lzo_dcd_b[43] = (~(ex3_lzo_dcd_hi[2] & ex3_lzo_dcd_lo[12])); + assign ex3_lzo_dcd_b[44] = (~(ex3_lzo_dcd_hi[2] & ex3_lzo_dcd_lo[13])); + assign ex3_lzo_dcd_b[45] = (~(ex3_lzo_dcd_hi[2] & ex3_lzo_dcd_lo[14])); + assign ex3_lzo_dcd_b[46] = (~(ex3_lzo_dcd_hi[2] & ex3_lzo_dcd_lo[15])); + + assign ex3_lzo_dcd_b[47] = (~(ex3_lzo_dcd_hi[3] & ex3_lzo_dcd_lo[0])); + assign ex3_lzo_dcd_b[48] = (~(ex3_lzo_dcd_hi[3] & ex3_lzo_dcd_lo[1])); + assign ex3_lzo_dcd_b[49] = (~(ex3_lzo_dcd_hi[3] & ex3_lzo_dcd_lo[2])); + assign ex3_lzo_dcd_b[50] = (~(ex3_lzo_dcd_hi[3] & ex3_lzo_dcd_lo[3])); + assign ex3_lzo_dcd_b[51] = (~(ex3_lzo_dcd_hi[3] & ex3_lzo_dcd_lo[4])); + assign ex3_lzo_dcd_b[52] = (~(ex3_lzo_dcd_hi[3] & ex3_lzo_dcd_lo[5])); + assign ex3_lzo_dcd_b[53] = (~(ex3_lzo_dcd_hi[3] & ex3_lzo_dcd_lo[6])); + assign ex3_lzo_dcd_b[54] = (~(ex3_lzo_dcd_hi[3] & ex3_lzo_dcd_lo[7])); + assign ex3_lzo_dcd_b[55] = (~(ex3_lzo_dcd_hi[3] & ex3_lzo_dcd_lo[8])); + assign ex3_lzo_dcd_b[56] = (~(ex3_lzo_dcd_hi[3] & ex3_lzo_dcd_lo[9])); + assign ex3_lzo_dcd_b[57] = (~(ex3_lzo_dcd_hi[3] & ex3_lzo_dcd_lo[10])); + assign ex3_lzo_dcd_b[58] = (~(ex3_lzo_dcd_hi[3] & ex3_lzo_dcd_lo[11])); + assign ex3_lzo_dcd_b[59] = (~(ex3_lzo_dcd_hi[3] & ex3_lzo_dcd_lo[12])); + assign ex3_lzo_dcd_b[60] = (~(ex3_lzo_dcd_hi[3] & ex3_lzo_dcd_lo[13])); + assign ex3_lzo_dcd_b[61] = (~(ex3_lzo_dcd_hi[3] & ex3_lzo_dcd_lo[14])); + assign ex3_lzo_dcd_b[62] = (~(ex3_lzo_dcd_hi[3] & ex3_lzo_dcd_lo[15])); + + assign ex3_lzo_dcd_b[63] = (~(ex3_lzo_dcd_hi[4] & ex3_lzo_dcd_lo[0])); + assign ex3_lzo_dcd_b[64] = (~(ex3_lzo_dcd_hi[4] & ex3_lzo_dcd_lo[1])); + assign ex3_lzo_dcd_b[65] = (~(ex3_lzo_dcd_hi[4] & ex3_lzo_dcd_lo[2])); + assign ex3_lzo_dcd_b[66] = (~(ex3_lzo_dcd_hi[4] & ex3_lzo_dcd_lo[3])); + assign ex3_lzo_dcd_b[67] = (~(ex3_lzo_dcd_hi[4] & ex3_lzo_dcd_lo[4])); + assign ex3_lzo_dcd_b[68] = (~(ex3_lzo_dcd_hi[4] & ex3_lzo_dcd_lo[5])); + assign ex3_lzo_dcd_b[69] = (~(ex3_lzo_dcd_hi[4] & ex3_lzo_dcd_lo[6])); + assign ex3_lzo_dcd_b[70] = (~(ex3_lzo_dcd_hi[4] & ex3_lzo_dcd_lo[7])); + assign ex3_lzo_dcd_b[71] = (~(ex3_lzo_dcd_hi[4] & ex3_lzo_dcd_lo[8])); + assign ex3_lzo_dcd_b[72] = (~(ex3_lzo_dcd_hi[4] & ex3_lzo_dcd_lo[9])); + assign ex3_lzo_dcd_b[73] = (~(ex3_lzo_dcd_hi[4] & ex3_lzo_dcd_lo[10])); + assign ex3_lzo_dcd_b[74] = (~(ex3_lzo_dcd_hi[4] & ex3_lzo_dcd_lo[11])); + assign ex3_lzo_dcd_b[75] = (~(ex3_lzo_dcd_hi[4] & ex3_lzo_dcd_lo[12])); + assign ex3_lzo_dcd_b[76] = (~(ex3_lzo_dcd_hi[4] & ex3_lzo_dcd_lo[13])); + assign ex3_lzo_dcd_b[77] = (~(ex3_lzo_dcd_hi[4] & ex3_lzo_dcd_lo[14])); + assign ex3_lzo_dcd_b[78] = (~(ex3_lzo_dcd_hi[4] & ex3_lzo_dcd_lo[15])); + + assign ex3_lzo_dcd_b[79] = (~(ex3_lzo_dcd_hi[5] & ex3_lzo_dcd_lo[0])); + assign ex3_lzo_dcd_b[80] = (~(ex3_lzo_dcd_hi[5] & ex3_lzo_dcd_lo[1])); + assign ex3_lzo_dcd_b[81] = (~(ex3_lzo_dcd_hi[5] & ex3_lzo_dcd_lo[2])); + assign ex3_lzo_dcd_b[82] = (~(ex3_lzo_dcd_hi[5] & ex3_lzo_dcd_lo[3])); + assign ex3_lzo_dcd_b[83] = (~(ex3_lzo_dcd_hi[5] & ex3_lzo_dcd_lo[4])); + assign ex3_lzo_dcd_b[84] = (~(ex3_lzo_dcd_hi[5] & ex3_lzo_dcd_lo[5])); + assign ex3_lzo_dcd_b[85] = (~(ex3_lzo_dcd_hi[5] & ex3_lzo_dcd_lo[6])); + assign ex3_lzo_dcd_b[86] = (~(ex3_lzo_dcd_hi[5] & ex3_lzo_dcd_lo[7])); + assign ex3_lzo_dcd_b[87] = (~(ex3_lzo_dcd_hi[5] & ex3_lzo_dcd_lo[8])); + assign ex3_lzo_dcd_b[88] = (~(ex3_lzo_dcd_hi[5] & ex3_lzo_dcd_lo[9])); + assign ex3_lzo_dcd_b[89] = (~(ex3_lzo_dcd_hi[5] & ex3_lzo_dcd_lo[10])); + assign ex3_lzo_dcd_b[90] = (~(ex3_lzo_dcd_hi[5] & ex3_lzo_dcd_lo[11])); + assign ex3_lzo_dcd_b[91] = (~(ex3_lzo_dcd_hi[5] & ex3_lzo_dcd_lo[12])); + assign ex3_lzo_dcd_b[92] = (~(ex3_lzo_dcd_hi[5] & ex3_lzo_dcd_lo[13])); + assign ex3_lzo_dcd_b[93] = (~(ex3_lzo_dcd_hi[5] & ex3_lzo_dcd_lo[14])); + assign ex3_lzo_dcd_b[94] = (~(ex3_lzo_dcd_hi[5] & ex3_lzo_dcd_lo[15])); + + assign ex3_lzo_dcd_b[95] = (~(ex3_lzo_dcd_hi[6] & ex3_lzo_dcd_lo[0])); + assign ex3_lzo_dcd_b[96] = (~(ex3_lzo_dcd_hi[6] & ex3_lzo_dcd_lo[1])); + assign ex3_lzo_dcd_b[97] = (~(ex3_lzo_dcd_hi[6] & ex3_lzo_dcd_lo[2])); + assign ex3_lzo_dcd_b[98] = (~(ex3_lzo_dcd_hi[6] & ex3_lzo_dcd_lo[3])); + assign ex3_lzo_dcd_b[99] = (~(ex3_lzo_dcd_hi[6] & ex3_lzo_dcd_lo[4])); + assign ex3_lzo_dcd_b[100] = (~(ex3_lzo_dcd_hi[6] & ex3_lzo_dcd_lo[5])); + assign ex3_lzo_dcd_b[101] = (~(ex3_lzo_dcd_hi[6] & ex3_lzo_dcd_lo[6])); + assign ex3_lzo_dcd_b[102] = (~(ex3_lzo_dcd_hi[6] & ex3_lzo_dcd_lo[7])); + assign ex3_lzo_dcd_b[103] = (~(ex3_lzo_dcd_hi[6] & ex3_lzo_dcd_lo[8])); + assign ex3_lzo_dcd_b[104] = (~(ex3_lzo_dcd_hi[6] & ex3_lzo_dcd_lo[9])); + assign ex3_lzo_dcd_b[105] = (~(ex3_lzo_dcd_hi[6] & ex3_lzo_dcd_lo[10])); + assign ex3_lzo_dcd_b[106] = (~(ex3_lzo_dcd_hi[6] & ex3_lzo_dcd_lo[11])); + assign ex3_lzo_dcd_b[107] = (~(ex3_lzo_dcd_hi[6] & ex3_lzo_dcd_lo[12])); + assign ex3_lzo_dcd_b[108] = (~(ex3_lzo_dcd_hi[6] & ex3_lzo_dcd_lo[13])); + assign ex3_lzo_dcd_b[109] = (~(ex3_lzo_dcd_hi[6] & ex3_lzo_dcd_lo[14])); + assign ex3_lzo_dcd_b[110] = (~(ex3_lzo_dcd_hi[6] & ex3_lzo_dcd_lo[15])); + + assign ex3_lzo_dcd_b[111] = (~(ex3_lzo_dcd_hi[7] & ex3_lzo_dcd_lo[0])); + assign ex3_lzo_dcd_b[112] = (~(ex3_lzo_dcd_hi[7] & ex3_lzo_dcd_lo[1])); + assign ex3_lzo_dcd_b[113] = (~(ex3_lzo_dcd_hi[7] & ex3_lzo_dcd_lo[2])); + assign ex3_lzo_dcd_b[114] = (~(ex3_lzo_dcd_hi[7] & ex3_lzo_dcd_lo[3])); + assign ex3_lzo_dcd_b[115] = (~(ex3_lzo_dcd_hi[7] & ex3_lzo_dcd_lo[4])); + assign ex3_lzo_dcd_b[116] = (~(ex3_lzo_dcd_hi[7] & ex3_lzo_dcd_lo[5])); + assign ex3_lzo_dcd_b[117] = (~(ex3_lzo_dcd_hi[7] & ex3_lzo_dcd_lo[6])); + assign ex3_lzo_dcd_b[118] = (~(ex3_lzo_dcd_hi[7] & ex3_lzo_dcd_lo[7])); + assign ex3_lzo_dcd_b[119] = (~(ex3_lzo_dcd_hi[7] & ex3_lzo_dcd_lo[8])); + assign ex3_lzo_dcd_b[120] = (~(ex3_lzo_dcd_hi[7] & ex3_lzo_dcd_lo[9])); + assign ex3_lzo_dcd_b[121] = (~(ex3_lzo_dcd_hi[7] & ex3_lzo_dcd_lo[10])); + assign ex3_lzo_dcd_b[122] = (~(ex3_lzo_dcd_hi[7] & ex3_lzo_dcd_lo[11])); + assign ex3_lzo_dcd_b[123] = (~(ex3_lzo_dcd_hi[7] & ex3_lzo_dcd_lo[12])); + assign ex3_lzo_dcd_b[124] = (~(ex3_lzo_dcd_hi[7] & ex3_lzo_dcd_lo[13])); + assign ex3_lzo_dcd_b[125] = (~(ex3_lzo_dcd_hi[7] & ex3_lzo_dcd_lo[14])); + assign ex3_lzo_dcd_b[126] = (~(ex3_lzo_dcd_hi[7] & ex3_lzo_dcd_lo[15])); + + assign ex3_lzo_dcd_b[127] = (~(ex3_lzo_dcd_hi[8] & ex3_lzo_dcd_lo[0])); + assign ex3_lzo_dcd_b[128] = (~(ex3_lzo_dcd_hi[8] & ex3_lzo_dcd_lo[1])); + assign ex3_lzo_dcd_b[129] = (~(ex3_lzo_dcd_hi[8] & ex3_lzo_dcd_lo[2])); + assign ex3_lzo_dcd_b[130] = (~(ex3_lzo_dcd_hi[8] & ex3_lzo_dcd_lo[3])); + assign ex3_lzo_dcd_b[131] = (~(ex3_lzo_dcd_hi[8] & ex3_lzo_dcd_lo[4])); + assign ex3_lzo_dcd_b[132] = (~(ex3_lzo_dcd_hi[8] & ex3_lzo_dcd_lo[5])); + assign ex3_lzo_dcd_b[133] = (~(ex3_lzo_dcd_hi[8] & ex3_lzo_dcd_lo[6])); + assign ex3_lzo_dcd_b[134] = (~(ex3_lzo_dcd_hi[8] & ex3_lzo_dcd_lo[7])); + assign ex3_lzo_dcd_b[135] = (~(ex3_lzo_dcd_hi[8] & ex3_lzo_dcd_lo[8])); + assign ex3_lzo_dcd_b[136] = (~(ex3_lzo_dcd_hi[8] & ex3_lzo_dcd_lo[9])); + assign ex3_lzo_dcd_b[137] = (~(ex3_lzo_dcd_hi[8] & ex3_lzo_dcd_lo[10])); + assign ex3_lzo_dcd_b[138] = (~(ex3_lzo_dcd_hi[8] & ex3_lzo_dcd_lo[11])); + assign ex3_lzo_dcd_b[139] = (~(ex3_lzo_dcd_hi[8] & ex3_lzo_dcd_lo[12])); + assign ex3_lzo_dcd_b[140] = (~(ex3_lzo_dcd_hi[8] & ex3_lzo_dcd_lo[13])); + assign ex3_lzo_dcd_b[141] = (~(ex3_lzo_dcd_hi[8] & ex3_lzo_dcd_lo[14])); + assign ex3_lzo_dcd_b[142] = (~(ex3_lzo_dcd_hi[8] & ex3_lzo_dcd_lo[15])); + + assign ex3_lzo_dcd_b[143] = (~(ex3_lzo_dcd_hi[9] & ex3_lzo_dcd_lo[0])); + assign ex3_lzo_dcd_b[144] = (~(ex3_lzo_dcd_hi[9] & ex3_lzo_dcd_lo[1])); + assign ex3_lzo_dcd_b[145] = (~(ex3_lzo_dcd_hi[9] & ex3_lzo_dcd_lo[2])); + assign ex3_lzo_dcd_b[146] = (~(ex3_lzo_dcd_hi[9] & ex3_lzo_dcd_lo[3])); + assign ex3_lzo_dcd_b[147] = (~(ex3_lzo_dcd_hi[9] & ex3_lzo_dcd_lo[4])); + assign ex3_lzo_dcd_b[148] = (~(ex3_lzo_dcd_hi[9] & ex3_lzo_dcd_lo[5])); + assign ex3_lzo_dcd_b[149] = (~(ex3_lzo_dcd_hi[9] & ex3_lzo_dcd_lo[6])); + assign ex3_lzo_dcd_b[150] = (~(ex3_lzo_dcd_hi[9] & ex3_lzo_dcd_lo[7])); + assign ex3_lzo_dcd_b[151] = (~(ex3_lzo_dcd_hi[9] & ex3_lzo_dcd_lo[8])); + assign ex3_lzo_dcd_b[152] = (~(ex3_lzo_dcd_hi[9] & ex3_lzo_dcd_lo[9])); + assign ex3_lzo_dcd_b[153] = (~(ex3_lzo_dcd_hi[9] & ex3_lzo_dcd_lo[10])); + assign ex3_lzo_dcd_b[154] = (~(ex3_lzo_dcd_hi[9] & ex3_lzo_dcd_lo[11])); + assign ex3_lzo_dcd_b[155] = (~(ex3_lzo_dcd_hi[9] & ex3_lzo_dcd_lo[12])); + assign ex3_lzo_dcd_b[156] = (~(ex3_lzo_dcd_hi[9] & ex3_lzo_dcd_lo[13])); + assign ex3_lzo_dcd_b[157] = (~(ex3_lzo_dcd_hi[9] & ex3_lzo_dcd_lo[14])); + assign ex3_lzo_dcd_b[158] = (~(ex3_lzo_dcd_hi[9] & ex3_lzo_dcd_lo[15])); + + assign ex3_lzo_dcd_b[159] = (~(ex3_lzo_dcd_hi[10] & ex3_lzo_dcd_lo[0])); + assign ex3_lzo_dcd_b[160] = (~(ex3_lzo_dcd_hi[10] & ex3_lzo_dcd_lo[1])); + assign ex3_lzo_dcd_b[161] = (~(ex3_lzo_dcd_hi[10] & ex3_lzo_dcd_lo[2])); + assign ex3_lzo_dcd_b[162] = (~(ex3_lzo_dcd_hi[10] & ex3_lzo_dcd_lo[3])); + + //----------------------------------------- + + assign f_alg_ex3_sel_byp_b = (~(f_alg_ex3_sel_byp)); + assign ex3_lzo_nonbyp_0_b = (~(ex3_lzo_nonbyp_0)); + assign ex3_lzo_forbyp_0_b = (~(ex3_lzo_forbyp_0)); + + assign f_lze_ex3_lzo_din[0] = (~((f_alg_ex3_sel_byp | ex3_lzo_nonbyp_0_b) & (f_alg_ex3_sel_byp_b | ex3_lzo_forbyp_0_b))); // neg input and/or + assign f_lze_ex3_lzo_din[1] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[1])); // neg input and -- + assign f_lze_ex3_lzo_din[2] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[2])); // neg input and -- + assign f_lze_ex3_lzo_din[3] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[3])); // neg input and -- + assign f_lze_ex3_lzo_din[4] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[4])); // neg input and -- + assign f_lze_ex3_lzo_din[5] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[5])); // neg input and -- + assign f_lze_ex3_lzo_din[6] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[6])); // neg input and -- + assign f_lze_ex3_lzo_din[7] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[7])); // neg input and -- + assign f_lze_ex3_lzo_din[8] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[8])); // neg input and -- + assign f_lze_ex3_lzo_din[9] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[9])); // neg input and -- + assign f_lze_ex3_lzo_din[10] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[10])); // neg input and -- + assign f_lze_ex3_lzo_din[11] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[11])); // neg input and -- + assign f_lze_ex3_lzo_din[12] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[12])); // neg input and -- + assign f_lze_ex3_lzo_din[13] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[13])); // neg input and -- + assign f_lze_ex3_lzo_din[14] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[14])); // neg input and -- + assign f_lze_ex3_lzo_din[15] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[15])); // neg input and -- + assign f_lze_ex3_lzo_din[16] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[16])); // neg input and -- + assign f_lze_ex3_lzo_din[17] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[17])); // neg input and -- + assign f_lze_ex3_lzo_din[18] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[18])); // neg input and -- + assign f_lze_ex3_lzo_din[19] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[19])); // neg input and -- + assign f_lze_ex3_lzo_din[20] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[20])); // neg input and -- + assign f_lze_ex3_lzo_din[21] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[21])); // neg input and -- + assign f_lze_ex3_lzo_din[22] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[22])); // neg input and -- + assign f_lze_ex3_lzo_din[23] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[23])); // neg input and -- + assign f_lze_ex3_lzo_din[24] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[24])); // neg input and -- + assign f_lze_ex3_lzo_din[25] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[25])); // neg input and -- + assign f_lze_ex3_lzo_din[26] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[26])); // neg input and -- + assign f_lze_ex3_lzo_din[27] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[27])); // neg input and -- + assign f_lze_ex3_lzo_din[28] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[28])); // neg input and -- + assign f_lze_ex3_lzo_din[29] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[29])); // neg input and -- + assign f_lze_ex3_lzo_din[30] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[30])); // neg input and -- + assign f_lze_ex3_lzo_din[31] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[31])); // neg input and -- + assign f_lze_ex3_lzo_din[32] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[32])); // neg input and -- + assign f_lze_ex3_lzo_din[33] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[33])); // neg input and -- + assign f_lze_ex3_lzo_din[34] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[34])); // neg input and -- + assign f_lze_ex3_lzo_din[35] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[35])); // neg input and -- + assign f_lze_ex3_lzo_din[36] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[36])); // neg input and -- + assign f_lze_ex3_lzo_din[37] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[37])); // neg input and -- + assign f_lze_ex3_lzo_din[38] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[38])); // neg input and -- + assign f_lze_ex3_lzo_din[39] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[39])); // neg input and -- + assign f_lze_ex3_lzo_din[40] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[40])); // neg input and -- + assign f_lze_ex3_lzo_din[41] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[41])); // neg input and -- + assign f_lze_ex3_lzo_din[42] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[42])); // neg input and -- + assign f_lze_ex3_lzo_din[43] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[43])); // neg input and -- + assign f_lze_ex3_lzo_din[44] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[44])); // neg input and -- + assign f_lze_ex3_lzo_din[45] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[45])); // neg input and -- + assign f_lze_ex3_lzo_din[46] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[46])); // neg input and -- + assign f_lze_ex3_lzo_din[47] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[47])); // neg input and -- + assign f_lze_ex3_lzo_din[48] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[48])); // neg input and -- + assign f_lze_ex3_lzo_din[49] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[49])); // neg input and -- + assign f_lze_ex3_lzo_din[50] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[50])); // neg input and -- + assign f_lze_ex3_lzo_din[51] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[51])); // neg input and -- + assign f_lze_ex3_lzo_din[52] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[52])); // neg input and -- + assign f_lze_ex3_lzo_din[53] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[53])); // neg input and -- + assign f_lze_ex3_lzo_din[54] = (~(f_alg_ex3_sel_byp | ex3_lzo_dcd_b[54])); // neg input and -- + assign f_lze_ex3_lzo_din[55] = (~ex3_lzo_dcd_b[55]); + assign f_lze_ex3_lzo_din[56] = (~ex3_lzo_dcd_b[56]); + assign f_lze_ex3_lzo_din[57] = (~ex3_lzo_dcd_b[57]); + assign f_lze_ex3_lzo_din[58] = (~ex3_lzo_dcd_b[58]); + assign f_lze_ex3_lzo_din[59] = (~ex3_lzo_dcd_b[59]); + assign f_lze_ex3_lzo_din[60] = (~ex3_lzo_dcd_b[60]); + assign f_lze_ex3_lzo_din[61] = (~ex3_lzo_dcd_b[61]); + assign f_lze_ex3_lzo_din[62] = (~ex3_lzo_dcd_b[62]); + assign f_lze_ex3_lzo_din[63] = (~ex3_lzo_dcd_b[63]); + assign f_lze_ex3_lzo_din[64] = (~ex3_lzo_dcd_b[64]); + assign f_lze_ex3_lzo_din[65] = (~ex3_lzo_dcd_b[65]); + assign f_lze_ex3_lzo_din[66] = (~ex3_lzo_dcd_b[66]); + assign f_lze_ex3_lzo_din[67] = (~ex3_lzo_dcd_b[67]); + assign f_lze_ex3_lzo_din[68] = (~ex3_lzo_dcd_b[68]); + assign f_lze_ex3_lzo_din[69] = (~ex3_lzo_dcd_b[69]); + assign f_lze_ex3_lzo_din[70] = (~ex3_lzo_dcd_b[70]); + assign f_lze_ex3_lzo_din[71] = (~ex3_lzo_dcd_b[71]); + assign f_lze_ex3_lzo_din[72] = (~ex3_lzo_dcd_b[72]); + assign f_lze_ex3_lzo_din[73] = (~ex3_lzo_dcd_b[73]); + assign f_lze_ex3_lzo_din[74] = (~ex3_lzo_dcd_b[74]); + assign f_lze_ex3_lzo_din[75] = (~ex3_lzo_dcd_b[75]); + assign f_lze_ex3_lzo_din[76] = (~ex3_lzo_dcd_b[76]); + assign f_lze_ex3_lzo_din[77] = (~ex3_lzo_dcd_b[77]); + assign f_lze_ex3_lzo_din[78] = (~ex3_lzo_dcd_b[78]); + assign f_lze_ex3_lzo_din[79] = (~ex3_lzo_dcd_b[79]); + assign f_lze_ex3_lzo_din[80] = (~ex3_lzo_dcd_b[80]); + assign f_lze_ex3_lzo_din[81] = (~ex3_lzo_dcd_b[81]); + assign f_lze_ex3_lzo_din[82] = (~ex3_lzo_dcd_b[82]); + assign f_lze_ex3_lzo_din[83] = (~ex3_lzo_dcd_b[83]); + assign f_lze_ex3_lzo_din[84] = (~ex3_lzo_dcd_b[84]); + assign f_lze_ex3_lzo_din[85] = (~ex3_lzo_dcd_b[85]); + assign f_lze_ex3_lzo_din[86] = (~ex3_lzo_dcd_b[86]); + assign f_lze_ex3_lzo_din[87] = (~ex3_lzo_dcd_b[87]); + assign f_lze_ex3_lzo_din[88] = (~ex3_lzo_dcd_b[88]); + assign f_lze_ex3_lzo_din[89] = (~ex3_lzo_dcd_b[89]); + assign f_lze_ex3_lzo_din[90] = (~ex3_lzo_dcd_b[90]); + assign f_lze_ex3_lzo_din[91] = (~ex3_lzo_dcd_b[91]); + assign f_lze_ex3_lzo_din[92] = (~ex3_lzo_dcd_b[92]); + assign f_lze_ex3_lzo_din[93] = (~ex3_lzo_dcd_b[93]); + assign f_lze_ex3_lzo_din[94] = (~ex3_lzo_dcd_b[94]); + assign f_lze_ex3_lzo_din[95] = (~ex3_lzo_dcd_b[95]); + assign f_lze_ex3_lzo_din[96] = (~ex3_lzo_dcd_b[96]); + assign f_lze_ex3_lzo_din[97] = (~ex3_lzo_dcd_b[97]); + assign f_lze_ex3_lzo_din[98] = (~ex3_lzo_dcd_b[98]); + assign f_lze_ex3_lzo_din[99] = (~(ex3_lzo_dcd_b[99] & (~f_pic_ex3_to_integer))); + assign f_lze_ex3_lzo_din[100] = (~ex3_lzo_dcd_b[100]); + assign f_lze_ex3_lzo_din[101] = (~ex3_lzo_dcd_b[101]); + assign f_lze_ex3_lzo_din[102] = (~ex3_lzo_dcd_b[102]); + assign f_lze_ex3_lzo_din[103] = (~ex3_lzo_dcd_b[103]); + assign f_lze_ex3_lzo_din[104] = (~ex3_lzo_dcd_b[104]); + assign f_lze_ex3_lzo_din[105] = (~ex3_lzo_dcd_b[105]); + assign f_lze_ex3_lzo_din[106] = (~ex3_lzo_dcd_b[106]); + assign f_lze_ex3_lzo_din[107] = (~ex3_lzo_dcd_b[107]); + assign f_lze_ex3_lzo_din[108] = (~ex3_lzo_dcd_b[108]); + assign f_lze_ex3_lzo_din[109] = (~ex3_lzo_dcd_b[109]); + assign f_lze_ex3_lzo_din[110] = (~ex3_lzo_dcd_b[110]); + assign f_lze_ex3_lzo_din[111] = (~ex3_lzo_dcd_b[111]); + assign f_lze_ex3_lzo_din[112] = (~ex3_lzo_dcd_b[112]); + assign f_lze_ex3_lzo_din[113] = (~ex3_lzo_dcd_b[113]); + assign f_lze_ex3_lzo_din[114] = (~ex3_lzo_dcd_b[114]); + assign f_lze_ex3_lzo_din[115] = (~ex3_lzo_dcd_b[115]); + assign f_lze_ex3_lzo_din[116] = (~ex3_lzo_dcd_b[116]); + assign f_lze_ex3_lzo_din[117] = (~ex3_lzo_dcd_b[117]); + assign f_lze_ex3_lzo_din[118] = (~ex3_lzo_dcd_b[118]); + assign f_lze_ex3_lzo_din[119] = (~ex3_lzo_dcd_b[119]); + assign f_lze_ex3_lzo_din[120] = (~ex3_lzo_dcd_b[120]); + assign f_lze_ex3_lzo_din[121] = (~ex3_lzo_dcd_b[121]); + assign f_lze_ex3_lzo_din[122] = (~ex3_lzo_dcd_b[122]); + assign f_lze_ex3_lzo_din[123] = (~ex3_lzo_dcd_b[123]); + assign f_lze_ex3_lzo_din[124] = (~ex3_lzo_dcd_b[124]); + assign f_lze_ex3_lzo_din[125] = (~ex3_lzo_dcd_b[125]); + assign f_lze_ex3_lzo_din[126] = (~ex3_lzo_dcd_b[126]); + assign f_lze_ex3_lzo_din[127] = (~ex3_lzo_dcd_b[127]); + assign f_lze_ex3_lzo_din[128] = (~ex3_lzo_dcd_b[128]); + assign f_lze_ex3_lzo_din[129] = (~ex3_lzo_dcd_b[129]); + assign f_lze_ex3_lzo_din[130] = (~ex3_lzo_dcd_b[130]); + assign f_lze_ex3_lzo_din[131] = (~ex3_lzo_dcd_b[131]); + assign f_lze_ex3_lzo_din[132] = (~ex3_lzo_dcd_b[132]); + assign f_lze_ex3_lzo_din[133] = (~ex3_lzo_dcd_b[133]); + assign f_lze_ex3_lzo_din[134] = (~ex3_lzo_dcd_b[134]); + assign f_lze_ex3_lzo_din[135] = (~ex3_lzo_dcd_b[135]); + assign f_lze_ex3_lzo_din[136] = (~ex3_lzo_dcd_b[136]); + assign f_lze_ex3_lzo_din[137] = (~ex3_lzo_dcd_b[137]); + assign f_lze_ex3_lzo_din[138] = (~ex3_lzo_dcd_b[138]); + assign f_lze_ex3_lzo_din[139] = (~ex3_lzo_dcd_b[139]); + assign f_lze_ex3_lzo_din[140] = (~ex3_lzo_dcd_b[140]); + assign f_lze_ex3_lzo_din[141] = (~ex3_lzo_dcd_b[141]); + assign f_lze_ex3_lzo_din[142] = (~ex3_lzo_dcd_b[142]); + assign f_lze_ex3_lzo_din[143] = (~ex3_lzo_dcd_b[143]); + assign f_lze_ex3_lzo_din[144] = (~ex3_lzo_dcd_b[144]); + assign f_lze_ex3_lzo_din[145] = (~ex3_lzo_dcd_b[145]); + assign f_lze_ex3_lzo_din[146] = (~ex3_lzo_dcd_b[146]); + assign f_lze_ex3_lzo_din[147] = (~ex3_lzo_dcd_b[147]); + assign f_lze_ex3_lzo_din[148] = (~ex3_lzo_dcd_b[148]); + assign f_lze_ex3_lzo_din[149] = (~ex3_lzo_dcd_b[149]); + assign f_lze_ex3_lzo_din[150] = (~ex3_lzo_dcd_b[150]); + assign f_lze_ex3_lzo_din[151] = (~ex3_lzo_dcd_b[151]); + assign f_lze_ex3_lzo_din[152] = (~ex3_lzo_dcd_b[152]); + assign f_lze_ex3_lzo_din[153] = (~ex3_lzo_dcd_b[153]); + assign f_lze_ex3_lzo_din[154] = (~ex3_lzo_dcd_b[154]); + assign f_lze_ex3_lzo_din[155] = (~ex3_lzo_dcd_b[155]); + assign f_lze_ex3_lzo_din[156] = (~ex3_lzo_dcd_b[156]); + assign f_lze_ex3_lzo_din[157] = (~ex3_lzo_dcd_b[157]); + assign f_lze_ex3_lzo_din[158] = (~ex3_lzo_dcd_b[158]); + assign f_lze_ex3_lzo_din[159] = (~ex3_lzo_dcd_b[159]); + assign f_lze_ex3_lzo_din[160] = (~ex3_lzo_dcd_b[160]); + assign f_lze_ex3_lzo_din[161] = (~ex3_lzo_dcd_b[161]); + assign f_lze_ex3_lzo_din[162] = (~ex3_lzo_dcd_b[162]); + + ////##------------------------------------------ + ////## shift right stuff ... some could be in cycle 3 + ////##------------------------------------------ + + // enable shift right when bypassing a denormal B operand (and NOT ue=1 or PRRENORM) + + assign ex3_ins_est = f_pic_ex3_est_recip | f_pic_ex3_est_rsqrt; + + assign ex3_sh_rgt_en_by = (f_eie_ex3_use_bexp & ex3_expo_neg_sp_by & ex3_lzo_cont_sp & (~f_alg_ex3_byp_nonflip) & (~ex3_ins_est)) | (f_eie_ex3_use_bexp & ex3_expo_neg_dp_by & ex3_lzo_cont_dp & (~f_alg_ex3_byp_nonflip) & (~ex3_ins_est)); // set LZO[0] so can just OR into result + assign ex3_sh_rgt_en_p = ((~f_eie_ex3_use_bexp) & ex3_expo_neg_sp & ex3_lzo_cont_sp & (~f_alg_ex3_byp_nonflip)) | ((~f_eie_ex3_use_bexp) & ex3_expo_neg_dp & ex3_lzo_cont_dp & (~f_alg_ex3_byp_nonflip)); // set LZO[0] so can just OR into result + + assign ex3_sh_rgt_en = ex3_sh_rgt_en_by | ex3_sh_rgt_en_p; + + ////---------------------------------------------------------------------------------------------- + //// you might be thinking that the shift right amount needs a limiter (so that amounts > 64 + //// do not wrap a round and leave bits in the result when the result should be zero). + //// (1) if the shift amount belongs to the "B" operand, (bypass) and since we only shift right + //// when B is a denorm (it has a bit on) then the maximum shift right is (52) because + //// the smallest b exponent (expo min) after prenorm is -52. + //// there is the possibility that a divide could create an artificially small Bexpo. + //// if that is true the shift right amount should be zero (right 64 followed by left 0). + //// (2) otherwise the right shift amount comes from the product exponent. + //// the product exponent could be very small, however for a multiply add if it becomes + //// too small then the exponent will come from the addend, so no problem. + //// a multiply instruction does not have an addend, and it could have a very small exponent. + //// BUT, the lead bit is at [55] and even if the shift right goes right 64 followed by left 64, + //// it will not but a bit into the result or guard fields. + ////----------------------------------------------------------------------------------------------- + + // calculate shift right amount (DP) ... expo must be correct value to subtract in expo logic + // decode = 0 shift right 1 -(-1) for expo 0_0000_0000_0000 -> 1_1111_1111_1111 -x = !x + 1, !x = -x - 1 + // decode = -1 shift right 2 -(-2) for expo 0_0000_0000_0001 -> 1_1111_1111_1110 + // decode = -2 shift right 3 -(-3) for expo 0_0000_0000_0010 -> 1_1111_1111_1101 + // + // max = -53 0_0000_0011_0101 -> 1_1111_1100_1010 + // * **** **dd_dddd + + // calculate shift right amount (SP) + // decode = x380 shift right 1 -(-1) for expo 0_0011_1000_0000 -> 1_1100_0111_1111 -x = !x + 1, !x = -x - 1 + // decode = x37F shift right 2 -(-2) for expo 0_0011_1000_0001 -> 1_1100_0111_1110 + // decode = x37E shift right 3 -(-3) for expo 0_0011_1000_0010 -> 1_1100_0111_1101 + // * **** **dd_dddd + + // expo = Bexpo - lza + // Bexpo + (!lza) ... lza is usually sign extended and inverted to make a negative number, + // Bexpo must be added to in denorm cases + // Make lza a negative number, so that when it is flipped it becomes a positive number. + // + // expo_adj + // expo = x380 896 0_0011_1000_0000 1 -( 1) 1111_1111 + // expo = x37f 895 0_0011_0111_1111 2 -( 2) 1111_1110 + // expo = x37e 894 0_0011_0111_1110 3 1111_1101 + // expo = x37d 893 0_0011_0111_1101 4 1111_1100 + // expo = x37c 892 0_0011_0111_1100 5 + // expo = x37b 891 0_0011_0111_1011 6 + // expo = x37a 890 0_0011_0111_1010 7 + // expo = x379 889 0_0011_0111_1001 8 + // expo = x378 888 0_0011_0111_1000 9 + // expo = x377 887 0_0011_0111_0111 10 + // expo = x376 886 0_0011_0111_0110 11 + // expo = x375 885 0_0011_0111_0101 12 + // expo = x374 884 0_0011_0111_0100 13 + // expo = x373 883 0_0011_0111_0011 14 + // expo = x372 882 0_0011_0111_0010 15 + // expo = x371 881 0_0011_0111_0001 16 + // expo = x370 880 0_0011_0111_0000 17 + // expo = x36f 879 0_0011_0110_1111 18 + // expo = x36e 878 0_0011_0110_1110 19 + // expo = x36d 877 0_0011_0110_1101 20 + // expo = x36c 876 0_0011_0110_1100 21 + // expo = x36b 875 0_0011_0110_1011 22 + // expo = x36a 874 0_0011_0110_1010 23 -(23) 1110_1001 + //----------------------------- + // expo = x369 873 0_0011_0110_1001 24 -(24) 1110_1000 + + // if p_exp an be more neg then -63 , then this needs to be detected and shAmt forced to a const. + + assign ex3_expo_p_sim_p[8:13] = (~ex3_expo[8:13]); + + assign ex3_expo_p_sim_g[13] = ex3_expo[13]; + assign ex3_expo_p_sim_g[12] = ex3_expo[13] | ex3_expo[12]; + assign ex3_expo_p_sim_g[11] = ex3_expo[13] | ex3_expo[12] | ex3_expo[11]; + assign ex3_expo_p_sim_g[10] = ex3_expo[13] | ex3_expo[12] | ex3_expo[11] | ex3_expo[10]; + assign ex3_expo_p_sim_g[9] = ex3_expo[13] | ex3_expo[12] | ex3_expo[11] | ex3_expo[10] | ex3_expo[9]; + + assign ex3_expo_p_sim[13] = ex3_expo_p_sim_p[13]; + assign ex3_expo_p_sim[12] = ex3_expo_p_sim_p[12] ^ (ex3_expo_p_sim_g[13]); + assign ex3_expo_p_sim[11] = ex3_expo_p_sim_p[11] ^ (ex3_expo_p_sim_g[12]); + assign ex3_expo_p_sim[10] = ex3_expo_p_sim_p[10] ^ (ex3_expo_p_sim_g[11]); + assign ex3_expo_p_sim[9] = ex3_expo_p_sim_p[9] ^ (ex3_expo_p_sim_g[10]); + assign ex3_expo_p_sim[8] = ex3_expo_p_sim_p[8] ^ (ex3_expo_p_sim_g[9]); + + assign ex3_expo_sim_p[8:13] = (~ex3_expo_by[8:13]); + + assign ex3_expo_sim_g[13] = ex3_expo_by[13]; + assign ex3_expo_sim_g[12] = ex3_expo_by[13] | ex3_expo_by[12]; + assign ex3_expo_sim_g[11] = ex3_expo_by[13] | ex3_expo_by[12] | ex3_expo_by[11]; + assign ex3_expo_sim_g[10] = ex3_expo_by[13] | ex3_expo_by[12] | ex3_expo_by[11] | ex3_expo_by[10]; + assign ex3_expo_sim_g[9] = ex3_expo_by[13] | ex3_expo_by[12] | ex3_expo_by[11] | ex3_expo_by[10] | ex3_expo_by[9]; + + assign ex3_expo_sim[13] = ex3_expo_sim_p[13]; + assign ex3_expo_sim[12] = ex3_expo_sim_p[12] ^ (ex3_expo_sim_g[13]); + assign ex3_expo_sim[11] = ex3_expo_sim_p[11] ^ (ex3_expo_sim_g[12]); + assign ex3_expo_sim[10] = ex3_expo_sim_p[10] ^ (ex3_expo_sim_g[11]); + assign ex3_expo_sim[9] = ex3_expo_sim_p[9] ^ (ex3_expo_sim_g[10]); + assign ex3_expo_sim[8] = ex3_expo_sim_p[8] ^ (ex3_expo_sim_g[9]); + + // testing a new (simpler) version ------------- + // could include these in lzo dis + // could include these in lzo_dis + assign ex3_lzo_forbyp_0 = (f_pic_ex3_est_recip) | (f_pic_ex3_est_rsqrt) | (f_alg_ex3_byp_nonflip & (~f_pic_ex3_prenorm)) | ((~f_fmt_ex3_pass_msb_dp) & (~f_pic_ex3_lzo_dis_prod)) | ((ex3_expo_neg_dp_by | ex3_dp_001_by) & ex3_lzo_cont_dp) | ((ex3_expo_neg_sp_by | ex3_sp_001_by) & ex3_lzo_cont_sp); // allow norm to decr MSB then renormalize + + assign ex3_lzo_nonbyp_0 = (ex3_lzo_dcd_0) | (ex3_expo_neg_dp & ex3_lzo_cont_dp) | (ex3_expo_neg_sp & ex3_lzo_cont_sp) | (f_pic_ex3_est_recip) | (f_pic_ex3_est_rsqrt); + + assign ex3_sh_rgt_amt[0] = ex3_sh_rgt_en; // huge shift right should give "0" + assign ex3_sh_rgt_amt[1] = ex3_sh_rgt_en; // huge shift right should give "0" + assign ex3_sh_rgt_amt[2] = (ex3_sh_rgt_en_p & ex3_expo_p_sim[8]) | (ex3_sh_rgt_en_by & ex3_expo_sim[8]); + assign ex3_sh_rgt_amt[3] = (ex3_sh_rgt_en_p & ex3_expo_p_sim[9]) | (ex3_sh_rgt_en_by & ex3_expo_sim[9]); + assign ex3_sh_rgt_amt[4] = (ex3_sh_rgt_en_p & ex3_expo_p_sim[10]) | (ex3_sh_rgt_en_by & ex3_expo_sim[10]); + assign ex3_sh_rgt_amt[5] = (ex3_sh_rgt_en_p & ex3_expo_p_sim[11]) | (ex3_sh_rgt_en_by & ex3_expo_sim[11]); + assign ex3_sh_rgt_amt[6] = (ex3_sh_rgt_en_p & ex3_expo_p_sim[12]) | (ex3_sh_rgt_en_by & ex3_expo_sim[12]); + assign ex3_sh_rgt_amt[7] = (ex3_sh_rgt_en_p & ex3_expo_p_sim[13]) | (ex3_sh_rgt_en_by & ex3_expo_sim[13]); + + // bit_to_set |------ b_expo ----------| + // 0 897 x381 0_0011_1000_0001 <== all normal SP numbers go here + // 1 896 x380 0_0011_1000_0000 + // 2 895 x37f 0_0011_0111_1111 + // 3 894 x37e 0_0011_0111_1110 + // 4 893 x37d 0_0011_0111_1101 + // 5 892 x37c 0_0011_0111_1100 + // 6 891 x37b 0_0011_0111_1011 + // 7 890 x37a 0_0011_0111_1010 + // 8 889 x379 0_0011_0111_1001 + // 9 888 x378 0_0011_0111_1000 + // 10 887 x377 0_0011_0111_0111 + // 11 886 x376 0_0011_0111_0110 + // 12 885 x375 0_0011_0111_0101 + // 13 884 x374 0_0011_0111_0100 expo = (884 +26 -13) = 884 + 13 = 897 + // 14 883 x373 0_0011_0111_0011 + // 15 882 x372 0_0011_0111_0010 + // 16 881 x371 0_0011_0111_0001 + // 17 880 x370 0_0011_0111_0000 + // 18 879 x36f 0_0011_0011_1111 + // 19 878 x36e 0_0011_0011_1110 + // 20 877 x36d 0_0011_0011_1101 + // 21 876 x36c 0_0011_0011_1100 + // 22 875 x36b 0_0011_0011_1011 + // 23 874 x36a 0_0011_0011_1010 + // ----------------------------------------- + // 24 873 x369 0_0011_0011_1001 <=== if this or smaller do nothing (special case sp invalid) + // + + //-=############################################################### + //-=## ex4 latches + //-=############################################################### + + + tri_rlmreg_p #(.WIDTH(9), .NEEDS_SRESET(0)) ex4_shr_lat( + .force_t(force_t), // tidn, + .d_mode(tiup), + .delay_lclkr(delay_lclkr[3]), // tidn, + .mpw1_b(mpw1_b[3]), // tidn, + .mpw2_b(mpw2_b[0]), // tidn, + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_act), + .thold_b(thold_0_b), + .sg(sg_0), + .scout(ex4_shr_so), + .scin(ex4_shr_si), + //----------------- + .din({ex3_sh_rgt_amt[0:7], + ex3_sh_rgt_en}), + //----------------- + .dout({ex4_sh_rgt_amt[0:7], + ex4_sh_rgt_en}) + ); + + assign f_lze_ex4_sh_rgt_amt[0:7] = ex4_sh_rgt_amt[0:7]; //OUTPUT-- + assign f_lze_ex4_sh_rgt_en = ex4_sh_rgt_en; //OUTPUT-- + + //-=############################################################### + //-= scan string + //-=############################################################### + + assign ex4_shr_si[0:8] = {ex4_shr_so[1:8], f_lze_si}; + assign act_si[0:4] = {act_so[1:4], ex4_shr_so[0]}; + + assign f_lze_so = act_so[0]; + +endmodule diff --git a/dev/verilog/work/fu_mad.v b/dev/verilog/work/fu_mad.v new file mode 100755 index 0000000..b88251a --- /dev/null +++ b/dev/verilog/work/fu_mad.v @@ -0,0 +1,2373 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + + `include "tri_a2o.vh" + +module fu_mad( + f_dcd_ex7_cancel, + f_dcd_ex1_bypsel_a_res0, + f_dcd_ex1_bypsel_a_res1, + f_dcd_ex1_bypsel_a_res2, + f_dcd_ex1_bypsel_a_load0, + f_dcd_ex1_bypsel_a_load1, + f_dcd_ex1_bypsel_a_load2, + f_dcd_ex1_bypsel_a_reload0, + f_dcd_ex1_bypsel_a_reload1, + f_dcd_ex1_bypsel_a_reload2, + + f_dcd_ex1_bypsel_b_res0, + f_dcd_ex1_bypsel_b_res1, + f_dcd_ex1_bypsel_b_res2, + f_dcd_ex1_bypsel_b_load0, + f_dcd_ex1_bypsel_b_load1, + f_dcd_ex1_bypsel_b_load2, + f_dcd_ex1_bypsel_b_reload0, + f_dcd_ex1_bypsel_b_reload1, + f_dcd_ex1_bypsel_b_reload2, + + f_dcd_ex1_bypsel_c_res0, + f_dcd_ex1_bypsel_c_res1, + f_dcd_ex1_bypsel_c_res2, + f_dcd_ex1_bypsel_c_load0, + f_dcd_ex1_bypsel_c_load1, + f_dcd_ex1_bypsel_c_load2, + f_dcd_ex1_bypsel_c_reload0, + f_dcd_ex1_bypsel_c_reload1, + f_dcd_ex1_bypsel_c_reload2, + + f_dcd_ex1_bypsel_s_res0, + f_dcd_ex1_bypsel_s_res1, + f_dcd_ex1_bypsel_s_res2, + f_dcd_ex1_bypsel_s_load0, + f_dcd_ex1_bypsel_s_load1, + f_dcd_ex1_bypsel_s_load2, + f_dcd_ex1_bypsel_s_reload0, + f_dcd_ex1_bypsel_s_reload1, + f_dcd_ex1_bypsel_s_reload2, + + f_dcd_ex2_perr_force_c, + f_dcd_ex2_perr_fsel_ovrd, + + f_fpr_ex8_frt_sign, + f_fpr_ex8_frt_expo, + f_fpr_ex8_frt_frac, + f_fpr_ex9_frt_sign, + f_fpr_ex9_frt_expo, + f_fpr_ex9_frt_frac, + + f_fpr_ex6_load_sign, + f_fpr_ex6_load_expo, + f_fpr_ex6_load_frac, + f_fpr_ex7_load_sign, + f_fpr_ex7_load_expo, + f_fpr_ex7_load_frac, + f_fpr_ex8_load_sign, + f_fpr_ex8_load_expo, + f_fpr_ex8_load_frac, + f_fpr_ex6_reload_sign, + f_fpr_ex6_reload_expo, + f_fpr_ex6_reload_frac, + f_fpr_ex7_reload_sign, + f_fpr_ex7_reload_expo, + f_fpr_ex7_reload_frac, + f_fpr_ex8_reload_sign, + f_fpr_ex8_reload_expo, + f_fpr_ex8_reload_frac, + + f_fpr_ex1_s_sign, + f_fpr_ex1_s_expo, + f_fpr_ex1_s_frac, + f_byp_ex1_s_sign, + f_byp_ex1_s_expo, + f_byp_ex1_s_frac, + f_pic_ex6_scr_upd_move_b, + f_dcd_ex7_fpscr_wr, + f_dcd_ex7_fpscr_addr, + f_dsq_debug, + cp_axu_i0_t1_v, + cp_axu_i0_t0_t1_t, + cp_axu_i0_t1_t1_t, + cp_axu_i0_t0_t1_p, + cp_axu_i0_t1_t1_p, + cp_axu_i1_t1_v, + cp_axu_i1_t0_t1_t, + cp_axu_i1_t1_t1_t, + cp_axu_i1_t0_t1_p, + cp_axu_i1_t1_t1_p, + + f_fpr_ex1_a_sign, + f_fpr_ex1_a_expo, + f_fpr_ex1_a_frac, + f_fpr_ex2_a_par, + f_fpr_ex1_c_sign, + f_fpr_ex1_c_expo, + f_fpr_ex1_c_frac, + f_fpr_ex2_c_par, + f_fpr_ex1_b_sign, + f_fpr_ex1_b_expo, + f_fpr_ex1_b_frac, + f_fpr_ex2_b_par, + f_dcd_ex1_aop_valid, + f_dcd_ex1_cop_valid, + f_dcd_ex1_bop_valid, + f_dcd_ex1_thread, + f_dcd_ex1_sp, + f_dcd_ex1_emin_dp, + f_dcd_ex1_emin_sp, + f_dcd_ex1_force_pass_b, + f_dcd_ex1_fsel_b, + f_dcd_ex1_from_integer_b, + f_dcd_ex1_to_integer_b, + f_dcd_ex1_rnd_to_int_b, + f_dcd_ex1_math_b, + f_dcd_ex1_est_recip_b, + f_dcd_ex1_est_rsqrt_b, + f_dcd_ex1_move_b, + f_dcd_ex1_prenorm_b, + f_dcd_ex1_frsp_b, + f_dcd_ex1_compare_b, + f_dcd_ex1_ordered_b, + f_dcd_ex1_pow2e_b, + f_dcd_ex1_log2e_b, + f_dcd_ex1_ftdiv, + f_dcd_ex1_ftsqrt, + f_dcd_ex1_nj_deno, + f_dcd_ex1_nj_deni, + f_dcd_ex1_sp_conv_b, + f_dcd_ex1_word_b, + f_dcd_ex1_uns_b, + f_dcd_ex1_sub_op_b, + f_dcd_ex1_force_excp_dis, + f_dcd_ex1_op_rnd_v_b, + f_dcd_ex1_op_rnd_b, + f_dcd_ex1_inv_sign_b, + f_dcd_ex1_sign_ctl_b, + f_dcd_ex1_sgncpy_b, + f_dcd_ex1_fpscr_bit_data_b, + f_dcd_ex1_fpscr_bit_mask_b, + f_dcd_ex1_fpscr_nib_mask_b, + f_dcd_ex1_mv_to_scr_b, + f_dcd_ex1_mv_from_scr_b, + f_dcd_ex1_mtfsbx_b, + f_dcd_ex1_mcrfs_b, + f_dcd_ex1_mtfsf_b, + f_dcd_ex1_mtfsfi_b, + f_dcd_ex1_uc_fc_hulp, + f_dcd_ex1_uc_fa_pos, + f_dcd_ex1_uc_fc_pos, + f_dcd_ex1_uc_fb_pos, + f_dcd_ex1_uc_fc_0_5, + f_dcd_ex1_uc_fc_1_0, + f_dcd_ex1_uc_fc_1_minus, + f_dcd_ex1_uc_fb_1_0, + f_dcd_ex1_uc_fb_0_75, + f_dcd_ex1_uc_fb_0_5, + f_dcd_ex1_uc_ft_pos, + f_dcd_ex1_uc_ft_neg, + + f_dcd_ex1_uc_mid, + f_dcd_ex1_uc_end, + f_dcd_ex1_uc_special, + f_dcd_ex3_uc_zx, + f_dcd_ex3_uc_vxidi, + f_dcd_ex3_uc_vxzdz, + f_dcd_ex3_uc_vxsqrt, + f_dcd_ex3_uc_vxsnan, + f_dcd_ex3_uc_inc_lsb, + f_dcd_ex3_uc_gs_v, + f_dcd_ex3_uc_gs, + f_mad_ex7_uc_sign, + f_mad_ex7_uc_zero, + f_mad_ex4_uc_special, + f_mad_ex4_uc_zx, + f_mad_ex4_uc_vxidi, + f_mad_ex4_uc_vxzdz, + f_mad_ex4_uc_vxsqrt, + f_mad_ex4_uc_vxsnan, + f_mad_ex4_uc_res_sign, + f_mad_ex4_uc_round_mode, + f_mad_ex3_a_parity_check, + f_mad_ex3_c_parity_check, + f_mad_ex3_b_parity_check, + f_dcd_ex0_div, + f_dcd_ex0_divs, + f_dcd_ex0_sqrt, + f_dcd_ex0_sqrts, + f_dcd_ex0_record_v, + f_dcd_ex2_divsqrt_v, + f_dcd_ex2_divsqrt_hole_v, + f_dcd_flush, + f_dcd_ex1_itag, + f_dcd_ex1_fpscr_addr, + f_dcd_ex1_instr_frt, + f_dcd_ex1_instr_tid, + f_dcd_ex1_divsqrt_cr_bf, + f_dcd_axucr0_deno, + f_dsq_ex5_divsqrt_v, + f_dsq_ex6_divsqrt_v, + f_dsq_ex6_divsqrt_record_v, + f_dsq_ex6_divsqrt_cr_bf, + f_dsq_ex6_divsqrt_v_suppress, + f_dsq_ex5_divsqrt_itag, + f_dsq_ex6_divsqrt_fpscr_addr, + f_dsq_ex6_divsqrt_instr_frt, + f_dsq_ex6_divsqrt_instr_tid, + f_dsq_ex3_hangcounter_trigger, + f_ex3_b_den_flush, + f_scr_ex8_cr_fld, + f_scr_ex6_fpscr_ni_thr0, + f_scr_ex6_fpscr_ni_thr1, + f_add_ex5_fpcc_iu, + f_pic_ex6_fpr_wr_dis_b, + f_rnd_ex7_res_expo, + f_rnd_ex7_res_frac, + f_rnd_ex7_res_sign, + f_scr_ex8_fx_thread0, + f_scr_ex8_fx_thread1, + f_scr_cpl_fx_thread0, + f_scr_cpl_fx_thread1, + ex1_thread_b, + f_dcd_ex1_act, + vdd, + gnd, + scan_in, + scan_out, + clkoff_b, + act_dis, + flush, + delay_lclkr, + mpw1_b, + mpw2_b, + thold_1, + sg_1, + fpu_enable, + nclk +); + parameter THREADS = 2; + input f_dcd_ex7_cancel; + input f_dcd_ex1_bypsel_a_res0; + input f_dcd_ex1_bypsel_a_res1; + input f_dcd_ex1_bypsel_a_res2; + input f_dcd_ex1_bypsel_a_load0; + input f_dcd_ex1_bypsel_a_load1; + input f_dcd_ex1_bypsel_a_load2; + input f_dcd_ex1_bypsel_a_reload0; + input f_dcd_ex1_bypsel_a_reload1; + input f_dcd_ex1_bypsel_a_reload2; + + input f_dcd_ex1_bypsel_b_res0; + input f_dcd_ex1_bypsel_b_res1; + input f_dcd_ex1_bypsel_b_res2; + input f_dcd_ex1_bypsel_b_load0; + input f_dcd_ex1_bypsel_b_load1; + input f_dcd_ex1_bypsel_b_load2; + input f_dcd_ex1_bypsel_b_reload0; + input f_dcd_ex1_bypsel_b_reload1; + input f_dcd_ex1_bypsel_b_reload2; + + input f_dcd_ex1_bypsel_c_res0; + input f_dcd_ex1_bypsel_c_res1; + input f_dcd_ex1_bypsel_c_res2; + input f_dcd_ex1_bypsel_c_load0; + input f_dcd_ex1_bypsel_c_load1; + input f_dcd_ex1_bypsel_c_load2; + input f_dcd_ex1_bypsel_c_reload0; + input f_dcd_ex1_bypsel_c_reload1; + input f_dcd_ex1_bypsel_c_reload2; + + input f_dcd_ex1_bypsel_s_res0; + input f_dcd_ex1_bypsel_s_res1; + input f_dcd_ex1_bypsel_s_res2; + input f_dcd_ex1_bypsel_s_load0; + input f_dcd_ex1_bypsel_s_load1; + input f_dcd_ex1_bypsel_s_load2; + input f_dcd_ex1_bypsel_s_reload0; + input f_dcd_ex1_bypsel_s_reload1; + input f_dcd_ex1_bypsel_s_reload2; + + input f_dcd_ex2_perr_force_c; + + input f_dcd_ex2_perr_fsel_ovrd; + + + input f_fpr_ex8_frt_sign; + input [1:13] f_fpr_ex8_frt_expo; + input [0:52] f_fpr_ex8_frt_frac; + input f_fpr_ex9_frt_sign; + input [1:13] f_fpr_ex9_frt_expo; + input [0:52] f_fpr_ex9_frt_frac; + input f_fpr_ex6_load_sign; + input [3:13] f_fpr_ex6_load_expo; + input [0:52] f_fpr_ex6_load_frac; + input f_fpr_ex7_load_sign; + input [3:13] f_fpr_ex7_load_expo; + input [0:52] f_fpr_ex7_load_frac; + input f_fpr_ex8_load_sign; + input [3:13] f_fpr_ex8_load_expo; + input [0:52] f_fpr_ex8_load_frac; + + input f_fpr_ex6_reload_sign; + input [3:13] f_fpr_ex6_reload_expo; + input [0:52] f_fpr_ex6_reload_frac; + input f_fpr_ex7_reload_sign; + input [3:13] f_fpr_ex7_reload_expo; + input [0:52] f_fpr_ex7_reload_frac; + input f_fpr_ex8_reload_sign; + input [3:13] f_fpr_ex8_reload_expo; + input [0:52] f_fpr_ex8_reload_frac; + + input f_fpr_ex1_s_sign; + input [3:13] f_fpr_ex1_s_expo; + input [0:52] f_fpr_ex1_s_frac; //[0] is implicit bit + + output f_byp_ex1_s_sign; + output [3:13] f_byp_ex1_s_expo; + output [0:52] f_byp_ex1_s_frac; + + output f_pic_ex6_scr_upd_move_b; + input f_dcd_ex7_fpscr_wr; + input [0:5] f_dcd_ex7_fpscr_addr; + output [0:63] f_dsq_debug; + + input [0:THREADS-1] cp_axu_i0_t1_v; + input [0:2] cp_axu_i0_t0_t1_t; + input [0:2] cp_axu_i0_t1_t1_t; + input [0:5] cp_axu_i0_t0_t1_p; + input [0:5] cp_axu_i0_t1_t1_p; + + input [0:THREADS-1] cp_axu_i1_t1_v; + input [0:2] cp_axu_i1_t0_t1_t; + input [0:2] cp_axu_i1_t1_t1_t; + input [0:5] cp_axu_i1_t0_t1_p; + input [0:5] cp_axu_i1_t1_t1_p; + + //-------------------------------------------------------------------------- + + input f_fpr_ex1_a_sign; + input [1:13] f_fpr_ex1_a_expo; + input [0:52] f_fpr_ex1_a_frac; + input [0:7] f_fpr_ex2_a_par; + input f_fpr_ex1_c_sign; + input [1:13] f_fpr_ex1_c_expo; + input [0:52] f_fpr_ex1_c_frac; + input [0:7] f_fpr_ex2_c_par; + input f_fpr_ex1_b_sign; + input [1:13] f_fpr_ex1_b_expo; + input [0:52] f_fpr_ex1_b_frac; + input [0:7] f_fpr_ex2_b_par; + //-------------------------------------------------------------------------- + input f_dcd_ex1_aop_valid; + input f_dcd_ex1_cop_valid; + input f_dcd_ex1_bop_valid; + input [0:1] f_dcd_ex1_thread; + input f_dcd_ex1_sp; // off for frsp + input f_dcd_ex1_emin_dp; // prenorm_dp + input f_dcd_ex1_emin_sp; // prenorm_sp, frsp + input f_dcd_ex1_force_pass_b; // fmr,fnabbs,fabs,fneg,mtfsf + + input f_dcd_ex1_fsel_b; // fsel + input f_dcd_ex1_from_integer_b; // fcfid (signed integer) + input f_dcd_ex1_to_integer_b; // fcti* (signed integer 32/64) + input f_dcd_ex1_rnd_to_int_b; // fri* + input f_dcd_ex1_math_b; // fmul,fmad,fmsub,fadd,fsub,fnmsub,fnmadd + input f_dcd_ex1_est_recip_b; // fres + input f_dcd_ex1_est_rsqrt_b; // frsqrte + input f_dcd_ex1_move_b; // fmr,fneg,fabs,fnabs + input f_dcd_ex1_prenorm_b; // prenorm ?? need + input f_dcd_ex1_frsp_b; // round-to-single-precision ?? need + input f_dcd_ex1_compare_b; // fcomp* + input f_dcd_ex1_ordered_b; // fcompo + + input f_dcd_ex1_pow2e_b; // pow2e sp, den==>0 + input f_dcd_ex1_log2e_b; // log2e sp, den==>0 + + input f_dcd_ex1_ftdiv; // ftdiv + input f_dcd_ex1_ftsqrt; // ftsqrt + + input f_dcd_ex1_nj_deno; // force output den to zero + input f_dcd_ex1_nj_deni; // force input den to zero + + input f_dcd_ex1_sp_conv_b; // for sp/dp convert + input f_dcd_ex1_word_b; // for converts word/dw + input f_dcd_ex1_uns_b; // for converts unsigned + input f_dcd_ex1_sub_op_b; // fsub, fnmsub, fmsub + + input f_dcd_ex1_force_excp_dis; + + input f_dcd_ex1_op_rnd_v_b; // rounding mode = nearest + input [0:1] f_dcd_ex1_op_rnd_b; // rounding mode = positive infinity + input f_dcd_ex1_inv_sign_b; // fnmsub fnmadd + input [0:1] f_dcd_ex1_sign_ctl_b; // 0:fmr/fneg 1:fneg/fnabs + input f_dcd_ex1_sgncpy_b; // for sgncpy instruction : + // BValid=1 Avalid=0 move=1 sgncpy=1 + // sgnctl=fabs=00 <11 for _b> + // force pass, rnd_v=0, ovf_unf_dis, + + input [0:3] f_dcd_ex1_fpscr_bit_data_b; //data to write to nibble (other than mtfsf) + input [0:3] f_dcd_ex1_fpscr_bit_mask_b; //enable update of bit within the nibble + input [0:8] f_dcd_ex1_fpscr_nib_mask_b; //enable update of this nibble + // [8] = 0 except + // if (mtfsi AND w=1 AND bf=000 ) <= 0000_0000_1 + // if (mtfsf AND L==1) <= 1111_1111_1 + // if (mtfsf AND L=0 and w=1 and flm=xxxx_xxxx_1) <= 0000_0000_1 + // if (mtfsf AND L=0 and w=1 and flm=xxxx_xxxx_0) <= 0000_0000_0 + // if (mtfsf AND L=0 and w=0 and flm=xxxx_xxxx_1) <= dddd_dddd_0 + + input f_dcd_ex1_mv_to_scr_b; //mcrfs,mtfsf,mtfsfi,mtfsb0,mtfsb1 + input f_dcd_ex1_mv_from_scr_b; //mffs + input f_dcd_ex1_mtfsbx_b; //fpscr set bit, reset bit + input f_dcd_ex1_mcrfs_b; //move fpscr field to cr and reset exceptions + input f_dcd_ex1_mtfsf_b; //move fpr data to fpscr + input f_dcd_ex1_mtfsfi_b; //move immediate data to fpscr + + input f_dcd_ex1_uc_fc_hulp; //byp : bit 53 of multiplier + input f_dcd_ex1_uc_fa_pos; //byp : immediate data + input f_dcd_ex1_uc_fc_pos; //byp : immediate data + input f_dcd_ex1_uc_fb_pos; //byp : immediate data + input f_dcd_ex1_uc_fc_0_5; //byp : immediate data + input f_dcd_ex1_uc_fc_1_0; //byp : immediate data + input f_dcd_ex1_uc_fc_1_minus; //byp : immediate data + input f_dcd_ex1_uc_fb_1_0; //byp : immediate data + input f_dcd_ex1_uc_fb_0_75; //byp : immediate data + input f_dcd_ex1_uc_fb_0_5; //byp : immediate data + input f_dcd_ex1_uc_ft_pos; //pic + input f_dcd_ex1_uc_ft_neg; //pic + + input f_dcd_ex1_uc_mid; + input f_dcd_ex1_uc_end; + input f_dcd_ex1_uc_special; + input f_dcd_ex3_uc_zx; + input f_dcd_ex3_uc_vxidi; + input f_dcd_ex3_uc_vxzdz; + input f_dcd_ex3_uc_vxsqrt; + input f_dcd_ex3_uc_vxsnan; + + input f_dcd_ex3_uc_inc_lsb; + input f_dcd_ex3_uc_gs_v; + input [0:1] f_dcd_ex3_uc_gs; + + output f_mad_ex7_uc_sign; + output f_mad_ex7_uc_zero; + output f_mad_ex4_uc_special; + output f_mad_ex4_uc_zx; + output f_mad_ex4_uc_vxidi; + output f_mad_ex4_uc_vxzdz; + output f_mad_ex4_uc_vxsqrt; + output f_mad_ex4_uc_vxsnan; + output f_mad_ex4_uc_res_sign; + output [0:1] f_mad_ex4_uc_round_mode; + + output f_mad_ex3_a_parity_check; + output f_mad_ex3_c_parity_check; + output f_mad_ex3_b_parity_check; + input f_dcd_ex0_div; + input f_dcd_ex0_divs; + input f_dcd_ex0_sqrt; + input f_dcd_ex0_sqrts; + input f_dcd_ex0_record_v; + input f_dcd_ex2_divsqrt_v; + + input f_dcd_ex2_divsqrt_hole_v; + input [0:1] f_dcd_flush; + input [0:6] f_dcd_ex1_itag; + input [0:5] f_dcd_ex1_fpscr_addr; + input [0:5] f_dcd_ex1_instr_frt; + input [0:3] f_dcd_ex1_instr_tid; + + input [0:4] f_dcd_ex1_divsqrt_cr_bf; + input f_dcd_axucr0_deno; + + output [0:1] f_dsq_ex5_divsqrt_v; + output [0:1] f_dsq_ex6_divsqrt_v; + output f_dsq_ex6_divsqrt_record_v; + output [0:4] f_dsq_ex6_divsqrt_cr_bf; + + output f_dsq_ex6_divsqrt_v_suppress; + output [0:6] f_dsq_ex5_divsqrt_itag; + output [0:5] f_dsq_ex6_divsqrt_fpscr_addr; + output [0:5] f_dsq_ex6_divsqrt_instr_frt; + output [0:3] f_dsq_ex6_divsqrt_instr_tid; + output f_dsq_ex3_hangcounter_trigger; + + output f_ex3_b_den_flush; //iu (does not include all gating) ??? + + output [0:3] f_scr_ex8_cr_fld; //o-- + output f_scr_ex6_fpscr_ni_thr0; + output f_scr_ex6_fpscr_ni_thr1; + output [0:3] f_add_ex5_fpcc_iu; //o-- + output f_pic_ex6_fpr_wr_dis_b; //o-- + output [1:13] f_rnd_ex7_res_expo; //o-- + output [0:52] f_rnd_ex7_res_frac; //o-- + output f_rnd_ex7_res_sign; //o-- + output [0:3] f_scr_ex8_fx_thread0; //o-- + output [0:3] f_scr_ex8_fx_thread1; //o-- + output [0:3] f_scr_cpl_fx_thread0; //o-- + output [0:3] f_scr_cpl_fx_thread1; //o-- + + //-------------------------------------------------------------------------- + input [0:3] ex1_thread_b; + input f_dcd_ex1_act; + //-------------------------------------------------------------------------- + inout vdd; + inout gnd; + input [0:18] scan_in; + output [0:18] scan_out; + input clkoff_b; // tiup + input act_dis; // ??tidn?? + input flush; // ??tidn?? + input [1:7] delay_lclkr; // tidn, + input [1:7] mpw1_b; // tidn, + input [0:1] mpw2_b; // tidn, + input thold_1; + input sg_1; + input fpu_enable; + input [0:`NCLK_WIDTH-1] nclk; + // This entity contains macros + + parameter tiup = 1'b1; + parameter tidn = 1'b0; + + wire f_fmt_ex2_inf_and_beyond_sp; + wire perv_eie_sg_1; //PERV-- + wire perv_eov_sg_1; //PERV-- + wire perv_fmt_sg_1; //PERV-- + wire perv_mul_sg_1; //PERV-- + wire perv_alg_sg_1; //PERV-- + wire perv_add_sg_1; //PERV-- + wire perv_lza_sg_1; //PERV-- + wire perv_nrm_sg_1; //PERV-- + wire perv_rnd_sg_1; //PERV-- + wire perv_scr_sg_1; //PERV-- + wire perv_pic_sg_1; //PERV-- + wire perv_cr2_sg_1; //PERV-- + wire perv_eie_thold_1; //PERV-- + wire perv_eov_thold_1; //PERV-- + wire perv_fmt_thold_1; //PERV-- + wire perv_mul_thold_1; //PERV-- + wire perv_alg_thold_1; //PERV-- + wire perv_add_thold_1; //PERV-- + wire perv_lza_thold_1; //PERV-- + wire perv_nrm_thold_1; //PERV-- + wire perv_rnd_thold_1; //PERV-- + wire perv_scr_thold_1; //PERV-- + wire perv_pic_thold_1; //PERV-- + wire perv_cr2_thold_1; //PERV-- + wire perv_eie_fpu_enable; //PERV-- + wire perv_eov_fpu_enable; //PERV-- + wire perv_fmt_fpu_enable; //PERV-- + wire perv_mul_fpu_enable; //PERV-- + wire perv_alg_fpu_enable; //PERV-- + wire perv_add_fpu_enable; //PERV-- + wire perv_lza_fpu_enable; //PERV-- + wire perv_nrm_fpu_enable; //PERV-- + wire perv_rnd_fpu_enable; //PERV-- + wire perv_scr_fpu_enable; //PERV-- + wire perv_pic_fpu_enable; //PERV-- + wire perv_cr2_fpu_enable; //PERV-- + + wire f_eov_ex5_may_ovf; + wire f_add_ex5_flag_eq; //o-- + wire f_add_ex5_flag_gt; //o-- + wire f_add_ex5_flag_lt; //o-- + wire f_add_ex5_flag_nan; //o-- + wire [0:162] f_add_ex5_res; //o-- + wire f_add_ex5_sign_carry; //o-- + wire f_add_ex5_sticky; //o-- + wire [0:1] f_add_ex5_to_int_ovf_dw; //o-- + wire [0:1] f_add_ex5_to_int_ovf_wd; //o-- + wire f_alg_ex3_effsub_eac_b; //o-- + wire f_alg_ex3_prod_z; //o-- + wire [0:162] f_alg_ex3_res; //o-- + wire f_alg_ex3_sel_byp; //o-- + wire f_alg_ex3_sh_ovf; //o-- + wire f_alg_ex3_sh_unf; //o-- + wire f_alg_ex4_frc_sel_p1; //o-- + wire f_alg_ex4_int_fi; //o-- + wire f_alg_ex4_int_fr; //o-- + wire f_alg_ex4_sticky; //o-- + + wire [0:7] f_scr_fpscr_ctrl_thr0; + wire [0:7] f_scr_fpscr_ctrl_thr1; + + wire [1:13] f_byp_fmt_ex2_a_expo; //o-- + wire [1:13] f_byp_eie_ex2_a_expo; //o-- + wire [1:13] f_byp_alg_ex2_a_expo; //o-- + wire [1:13] f_byp_fmt_ex2_b_expo; //o-- + wire [1:13] f_byp_eie_ex2_b_expo; //o-- + wire [1:13] f_byp_alg_ex2_b_expo; //o-- + wire [1:13] f_byp_fmt_ex2_c_expo; //o-- + wire [1:13] f_byp_eie_ex2_c_expo; //o-- + wire [1:13] f_byp_alg_ex2_c_expo; //o-- + wire [0:52] f_byp_fmt_ex2_a_frac; //o-- + wire [0:52] f_byp_fmt_ex2_c_frac; //o-- + wire [0:52] f_byp_fmt_ex2_b_frac; //o-- + wire [0:52] f_byp_mul_ex2_a_frac; //o-- + wire f_byp_mul_ex2_a_frac_17; //o-- + wire f_byp_mul_ex2_a_frac_35; //o-- + wire [0:53] f_byp_mul_ex2_c_frac; //o-- + wire [0:52] f_byp_alg_ex2_b_frac; //o-- + wire f_byp_fmt_ex2_a_sign; //o-- + wire f_byp_fmt_ex2_b_sign; //o-- + wire f_byp_fmt_ex2_c_sign; //o-- + wire f_byp_pic_ex2_a_sign; //o-- + wire f_byp_pic_ex2_b_sign; //o-- + wire f_byp_pic_ex2_c_sign; //o-- + wire f_byp_alg_ex2_b_sign; //o-- + + wire [0:7] f_cr2_ex2_fpscr_shadow; //o-- + wire f_pic_ex3_rnd_inf_ok; //o-- + wire f_pic_ex3_rnd_nr; //o-- + wire [0:3] f_cr2_ex4_fpscr_bit_data_b; + wire [0:3] f_cr2_ex4_fpscr_bit_mask_b; + wire [0:8] f_cr2_ex4_fpscr_nib_mask_b; + wire f_cr2_ex4_mcrfs_b; //o-- + wire f_cr2_ex4_mtfsbx_b; //o-- + wire f_cr2_ex4_mtfsf_b; //o-- + wire f_cr2_ex4_mtfsfi_b; //o-- + wire [0:3] f_cr2_ex4_thread_b; //o-- + wire f_pic_add_ex2_act_b; //o-- + wire f_pic_eov_ex3_act_b; //o-- + wire f_pic_ex2_effsub_raw; //o-- + wire f_pic_ex2_from_integer; //o-- + wire f_pic_ex2_fsel; //o-- + wire f_pic_ex2_sh_ovf_do; //o-- + wire f_pic_ex2_sh_ovf_ig_b; //o-- + wire f_pic_ex2_sh_unf_do; //o-- + wire f_pic_ex2_sh_unf_ig_b; //o-- + wire f_pic_ex3_force_sel_bexp; //o-- + wire f_pic_ex3_lzo_dis_prod; //o-- + wire f_pic_ex3_sp_b; //o-- + wire f_pic_ex3_sp_lzo; //o-- + wire f_pic_ex3_to_integer; //o-- + wire f_pic_ex3_prenorm; //o-- + wire f_pic_ex4_cmp_sgnneg; //o-- + wire f_pic_ex4_cmp_sgnpos; //o-- + wire f_pic_ex4_is_eq; //o-- + wire f_pic_ex4_is_gt; //o-- + wire f_pic_ex4_is_lt; //o-- + wire f_pic_ex4_is_nan; //o-- + wire f_pic_ex4_sel_est; //o-- + wire f_pic_ex4_sp_b; //o-- + wire f_pic_ex5_nj_deno; //o-- + wire f_pic_ex5_oe; //o-- + wire f_pic_ex5_ov_en; //o-- + wire f_pic_ex5_ovf_en_oe0_b; //o-- + wire f_pic_ex5_ovf_en_oe1_b; //o-- + wire f_pic_ex5_quiet_b; //o-- + wire f_pic_ex6_uc_inc_lsb; //o-- + wire f_pic_ex6_uc_guard; //o-- + wire f_pic_ex6_uc_sticky; //o-- + wire f_pic_ex6_uc_g_v; //o-- + wire f_pic_ex6_uc_s_v; //o-- + wire f_pic_ex5_rnd_inf_ok_b; //o-- + wire f_pic_ex5_rnd_ni_b; //o-- + wire f_pic_ex5_rnd_nr_b; //o-- + wire f_pic_ex5_sel_est_b; //o-- + wire f_pic_ex5_sel_fpscr_b; //o-- + wire f_pic_ex5_sp_b; //o-- + wire f_pic_ex5_spec_inf_b; //o-- + wire f_pic_ex5_spec_sel_k_e; //o-- + wire f_pic_ex5_spec_sel_k_f; //o-- + wire f_pic_ex5_to_int_ov_all; //o-- + wire f_pic_ex5_to_integer_b; //o-- + wire f_pic_ex5_word_b; //o-- + wire f_pic_ex5_uns_b; //o-- + wire f_pic_ex5_ue; //o-- + wire f_pic_ex5_uf_en; //o-- + wire f_pic_ex5_unf_en_ue0_b; //o-- + wire f_pic_ex5_unf_en_ue1_b; //o-- + wire f_pic_ex6_en_exact_zero; //o-- + wire f_pic_ex6_compare_b; //o-- + wire f_pic_ex3_ue1; //o-- + wire f_pic_ex3_frsp_ue1; //o-- + wire f_pic_ex2_frsp_ue1; //o-- + wire f_pic_ex6_frsp; //o-- + wire f_pic_ex6_fi_pipe_v_b; //o-- + wire f_pic_ex6_fi_spec_b; //o-- + wire f_pic_ex6_flag_vxcvi_b; //o-- + wire f_pic_ex6_flag_vxidi_b; //o-- + wire f_pic_ex6_flag_vximz_b; //o-- + wire f_pic_ex6_flag_vxisi_b; //o-- + wire f_pic_ex6_flag_vxsnan_b; //o-- + wire f_pic_ex6_flag_vxsqrt_b; //o-- + wire f_pic_ex6_flag_vxvc_b; //o-- + wire f_pic_ex6_flag_vxzdz_b; //o-- + wire f_pic_ex6_flag_zx_b; //o-- + wire f_pic_ex6_fprf_hold_b; //o-- + wire f_pic_ex6_fprf_pipe_v_b; //o-- + wire [0:4] f_pic_ex6_fprf_spec_b; //o-- + wire f_pic_ex6_fr_pipe_v_b; //o-- + wire f_pic_ex6_fr_spec_b; //o-- + wire f_pic_ex6_invert_sign; //o-- + wire f_pic_ex5_byp_prod_nz; //o-- + wire f_pic_ex6_k_nan; + wire f_pic_ex6_k_inf; + wire f_pic_ex6_k_max; + wire f_pic_ex6_k_zer; + wire f_pic_ex6_k_one; + wire f_pic_ex6_k_int_maxpos; + wire f_pic_ex6_k_int_maxneg; + wire f_pic_ex6_k_int_zer; + wire f_pic_ex6_ox_pipe_v_b; //o-- + wire f_pic_ex6_round_sign; //o-- + wire f_pic_ex6_scr_upd_move_b_int; //o-- + wire f_pic_ex6_scr_upd_pipe_b; //o-- + wire f_pic_ex6_ux_pipe_v_b; //o-- + wire f_pic_lza_ex2_act_b; //o-- + wire f_pic_mul_ex2_act; //o-- + wire f_pic_fmt_ex2_act; + wire f_pic_eie_ex2_act; + wire f_pic_alg_ex2_act; + wire f_pic_cr2_ex2_act; + wire f_fmt_ex3_be_den; + + wire f_pic_nrm_ex4_act_b; //o-- + wire f_pic_rnd_ex4_act_b; //o-- + wire f_pic_scr_ex3_act_b; //o-- + wire f_eie_ex3_dw_ov; //o-- + wire f_eie_ex3_dw_ov_if; //o-- + wire [1:13] f_eie_ex3_lzo_expo; //o-- + wire [1:13] f_eie_ex3_b_expo; //o-- + wire [1:13] f_eie_ex3_tbl_expo; //o-- + wire f_eie_ex3_wd_ov; //o-- + wire f_eie_ex3_wd_ov_if; //o-- + wire [1:13] f_eie_ex4_iexp; //o-- + wire [1:13] f_eov_ex6_expo_p0; //o-- + wire [3:7] f_eov_ex6_expo_p0_ue1oe1; //o-- + wire [1:13] f_eov_ex6_expo_p1; //o-- + wire [3:7] f_eov_ex6_expo_p1_ue1oe1; //o-- + wire f_eov_ex6_ovf_expo; //o-- + wire f_eov_ex6_ovf_if_expo; //o-- + wire f_eov_ex6_sel_k_e; //o-- + wire f_eov_ex6_sel_k_f; //o-- + wire f_eov_ex6_sel_kif_e; //o-- + wire f_eov_ex6_sel_kif_f; //o-- + wire f_eov_ex6_unf_expo; //o-- + wire f_fmt_ex2_a_expo_max; //o-- + wire f_fmt_ex2_a_expo_max_dsq; //o-- + wire f_fmt_ex2_a_zero; //o-- + wire f_fmt_ex2_a_zero_dsq; //o-- + wire f_fmt_ex2_a_frac_msb; //o-- + wire f_fmt_ex2_a_frac_zero; //o-- + wire f_fmt_ex2_b_expo_max; //o-- + wire f_fmt_ex2_b_expo_max_dsq; //o-- + wire f_fmt_ex2_b_zero; //o-- + wire f_fmt_ex2_b_zero_dsq; //o-- + wire f_fmt_ex2_b_frac_msb; //o-- + wire f_fmt_ex2_b_frac_z32; + wire f_fmt_ex2_b_frac_zero; //o-- + wire [45:52] f_fmt_ex2_bop_byt; //o-- + wire f_fmt_ex2_c_expo_max; //o-- + wire f_fmt_ex2_c_zero; //o-- + wire f_fmt_ex2_c_frac_msb; //o-- + wire f_fmt_ex2_c_frac_zero; //o-- + wire f_fmt_ex2_sp_invalid; //o-- + wire f_fmt_ex2_pass_sel; //o-- + wire f_fmt_ex2_prod_zero; //o-- + wire f_fmt_ex3_fsel_bsel; //o-- + wire [0:52] f_fmt_ex3_pass_frac; //o-- + wire f_fmt_ex3_pass_sign; //o-- + wire f_fmt_ex3_pass_msb; //o-- + wire f_fmt_ex2_b_imp; //o-- + wire [0:7] f_lza_ex5_lza_amt; //o-- + wire [0:2] f_lza_ex5_lza_dcd64_cp1; + wire [0:1] f_lza_ex5_lza_dcd64_cp2; + wire [0:0] f_lza_ex5_lza_dcd64_cp3; + wire f_lza_ex5_sh_rgt_en; + wire f_lza_ex5_sh_rgt_en_eov; + wire [0:7] f_lza_ex5_lza_amt_eov; //o-- + wire f_lza_ex5_no_lza_edge; //o-- + wire [1:108] f_mul_ex3_car; //o-- + wire [1:108] f_mul_ex3_sum; //o-- + wire f_nrm_ex5_extra_shift; //o-- + wire f_nrm_ex6_exact_zero; //o-- + wire [0:31] f_nrm_ex6_fpscr_wr_dat; //o-- + wire [0:3] f_nrm_ex6_fpscr_wr_dat_dfp; //o-- + wire [1:12] f_nrm_ex6_int_lsbs; //o-- + wire f_nrm_ex6_int_sign; + wire f_nrm_ex6_nrm_guard_dp; //o-- + wire f_nrm_ex6_nrm_guard_sp; //o-- + wire f_nrm_ex6_nrm_lsb_dp; //o-- + wire f_nrm_ex6_nrm_lsb_sp; //o-- + wire f_nrm_ex6_nrm_sticky_dp; //o-- + wire f_nrm_ex6_nrm_sticky_sp; //o-- + wire [0:52] f_nrm_ex6_res; //o-- + wire f_rnd_ex7_flag_den; //o-- + wire f_rnd_ex7_flag_fi; //o-- + wire f_rnd_ex7_flag_inf; //o-- + wire f_rnd_ex7_flag_ox; //o-- + wire f_rnd_ex7_flag_sgn; //o-- + wire f_rnd_ex7_flag_up; //o-- + wire f_rnd_ex7_flag_ux; //o-- + wire f_rnd_ex7_flag_zer; //o-- + wire [53:161] f_sa3_ex4_c_lza; //o-- + wire [0:162] f_sa3_ex4_s_lza; //o-- + wire [53:161] f_sa3_ex4_c_add; //o-- + wire [0:162] f_sa3_ex4_s_add; //o-- + wire [0:3] f_scr_ex6_fpscr_rd_dat_dfp; //o-- + wire [0:31] f_scr_ex6_fpscr_rd_dat; //o-- + wire [0:1] f_scr_ex6_fpscr_rm_thr0; //o-- + wire [0:4] f_scr_ex6_fpscr_ee_thr0; //o-- + wire f_scr_ex6_fpscr_ni_thr0_int; //o-- + + wire [0:1] f_scr_ex6_fpscr_rm_thr1; //o-- + wire [0:4] f_scr_ex6_fpscr_ee_thr1; //o-- + wire f_scr_ex6_fpscr_ni_thr1_int; //o-- + + wire [24:31] f_cr2_ex6_fpscr_rd_dat; //o-- + wire [24:31] f_cr2_ex7_fpscr_rd_dat; //o-- + wire f_pic_tbl_ex2_act; + wire f_pic_ex2_ftdiv; + + wire f_pic_ex3_math_bzer_b; + wire perv_sa3_thold_1; + wire perv_sa3_sg_1; + wire perv_sa3_fpu_enable; + wire f_pic_ex3_b_valid; + wire f_alg_ex3_byp_nonflip; + wire f_pic_ex2_rnd_to_int; + wire f_eie_ex3_lt_bias; + wire f_eie_ex3_eq_bias_m1; + wire f_pic_ex3_est_recip; + wire f_pic_ex3_est_rsqrt; + wire f_tbe_ex4_may_ov; + wire [1:13] f_tbe_ex4_res_expo; + wire perv_tbe_sg_1; + wire perv_tbe_thold_1; + wire perv_tbe_fpu_enable; + wire perv_tbl_sg_1; + wire perv_tbl_thold_1; + wire perv_tbl_fpu_enable; + wire f_tbe_ex4_recip_2046; + wire f_tbe_ex4_recip_2045; + wire [1:19] f_fmt_ex2_b_frac; + wire [0:26] f_tbl_ex6_est_frac; + wire f_tbl_ex6_recip_den; + wire f_eie_ex3_use_bexp; + wire rnd_ex7_res_sign; + wire [1:13] rnd_ex7_res_expo; + wire [0:52] rnd_ex7_res_frac; + wire f_pic_ex2_flush_en_dp; + wire f_pic_ex2_flush_en_sp; + wire f_fmt_ex3_lu_den_recip; + wire f_fmt_ex3_lu_den_rsqrto; + wire f_tbe_ex4_recip_2044; + wire f_tbe_ex4_lu_sh; + + wire [0:162] f_lze_ex3_lzo_din; + wire [0:7] f_lze_ex4_sh_rgt_amt; + wire f_lze_ex4_sh_rgt_en; + wire f_alg_ex2_sign_frmw; + wire f_tbe_ex4_match_en_sp; + wire f_tbe_ex4_match_en_dp; + wire f_tbl_ex5_unf_expo; + wire f_tbe_ex4_recip_ue1; + wire f_fmt_ex2_bexpu_le126; + wire f_fmt_ex2_gt126; + wire f_fmt_ex2_ge128; + wire f_gst_ex6_logexp_v; + wire f_gst_ex6_logexp_sign; + wire [1:11] f_gst_ex6_logexp_exp; + wire [0:19] f_gst_ex6_logexp_fract; + wire f_fmt_ex2_b_sign_gst; + wire [1:13] f_fmt_ex2_b_expo_gst_b; + wire f_pic_ex2_log2e; + wire f_pic_ex2_pow2e; + wire f_fmt_ex2_a_sign_div; + wire [01:13] f_fmt_ex2_a_expo_div_b; + wire [01:52] f_fmt_ex2_a_frac_div; + wire f_fmt_ex2_b_sign_div; + wire [01:13] f_fmt_ex2_b_expo_div_b; + wire [01:52] f_fmt_ex2_b_frac_div; + + wire f_dsq_ex6_divsqrt_v_int_suppress; + wire [0:1] f_dsq_ex6_divsqrt_v_int; + wire f_dsq_ex6_divsqrt_record_v_int; + wire [0:1] f_dsq_ex5_divsqrt_v_int; + wire [0:6] f_dsq_ex5_divsqrt_itag_int; + + wire [0:5] f_dsq_ex6_divsqrt_fpscr_addr_int; + wire [0:5] f_dsq_ex6_divsqrt_instr_frt_int; + wire [0:3] f_dsq_ex6_divsqrt_instr_tid_int; + wire f_dsq_ex3_hangcounter_trigger_int; + + + wire [0:4] f_dsq_ex6_divsqrt_cr_bf_int; + + wire f_dsq_ex6_divsqrt_sign; + wire [01:13] f_dsq_ex6_divsqrt_exp; + wire [00:52] f_dsq_ex6_divsqrt_fract; + + wire [00:15] f_dsq_ex6_divsqrt_flag_fpscr; + + wire f_mad_ex3_uc_a_expo_den; // a exponent <= 0 + wire f_mad_ex3_uc_a_expo_den_sp; + wire f_pic_ex2_nj_deni; + wire f_fmt_ex3_ae_ge_54; + wire f_fmt_ex3_be_ge_54; + wire f_fmt_ex3_be_ge_2; + wire f_fmt_ex3_be_ge_2044; + wire f_fmt_ex3_tdiv_rng_chk; + +// assign unused = tidn; // todo + + + // fuq_byp.vhdl + fu_byp fbyp( + //--------------------------------------------------------- -- fuq_byp.vhdl + .vdd(vdd), //i-- + .gnd(gnd), //i-- + .nclk(nclk), //i-- + .clkoff_b(clkoff_b), //i-- + .act_dis(act_dis), //i-- + .flush(flush), //i-- + .delay_lclkr(delay_lclkr[1]), //i-- + .mpw1_b(mpw1_b[1]), //i-- + .mpw2_b(mpw2_b[0]), //i-- + .thold_1(perv_fmt_thold_1), //i-- + .sg_1(perv_fmt_sg_1), //i-- + .fpu_enable(perv_fmt_fpu_enable), //i-- + + .f_byp_si(scan_in[0]), //i--fbyp + .f_byp_so(scan_out[0]), //o--fbyp + .ex1_act(f_dcd_ex1_act), //i--fbyp + + .f_fpr_ex8_frt_sign(f_fpr_ex8_frt_sign), //i--mad + .f_fpr_ex8_frt_expo(f_fpr_ex8_frt_expo[1:13]), //i--mad + .f_fpr_ex8_frt_frac(f_fpr_ex8_frt_frac[0:52]), //i--mad + .f_fpr_ex9_frt_sign(f_fpr_ex9_frt_sign), //i--mad + .f_fpr_ex9_frt_expo(f_fpr_ex9_frt_expo[1:13]), //i--mad + .f_fpr_ex9_frt_frac(f_fpr_ex9_frt_frac[0:52]), //i--mad + + .f_fpr_ex6_load_sign(f_fpr_ex6_load_sign), //i--fbyp + .f_fpr_ex6_load_expo(f_fpr_ex6_load_expo[3:13]), //i--fbyp + .f_fpr_ex6_load_frac(f_fpr_ex6_load_frac[0:52]), //i--fbyp + .f_fpr_ex7_load_sign(f_fpr_ex7_load_sign), //i--mad + .f_fpr_ex7_load_expo(f_fpr_ex7_load_expo[3:13]), //i--mad + .f_fpr_ex7_load_frac(f_fpr_ex7_load_frac[0:52]), //i--mad + .f_fpr_ex8_load_sign(f_fpr_ex8_load_sign), //i--mad + .f_fpr_ex8_load_expo(f_fpr_ex8_load_expo[3:13]), //i--mad + .f_fpr_ex8_load_frac(f_fpr_ex8_load_frac[0:52]), //i--mad + + .f_fpr_ex6_reload_sign(f_fpr_ex6_reload_sign), //i--fbyp + .f_fpr_ex6_reload_expo(f_fpr_ex6_reload_expo[3:13]), //i--fbyp + .f_fpr_ex6_reload_frac(f_fpr_ex6_reload_frac[0:52]), //i--fbyp + .f_fpr_ex7_reload_sign(f_fpr_ex7_reload_sign), //i--mad + .f_fpr_ex7_reload_expo(f_fpr_ex7_reload_expo[3:13]), //i--mad + .f_fpr_ex7_reload_frac(f_fpr_ex7_reload_frac[0:52]), //i--mad + .f_fpr_ex8_reload_sign(f_fpr_ex8_reload_sign), //i--mad + .f_fpr_ex8_reload_expo(f_fpr_ex8_reload_expo[3:13]), //i--mad + .f_fpr_ex8_reload_frac(f_fpr_ex8_reload_frac[0:52]), //i--mad + + + .f_fpr_ex1_s_sign(f_fpr_ex1_s_sign), + .f_fpr_ex1_s_expo(f_fpr_ex1_s_expo), + .f_fpr_ex1_s_frac(f_fpr_ex1_s_frac), + .f_byp_ex1_s_sign(f_byp_ex1_s_sign), + .f_byp_ex1_s_expo(f_byp_ex1_s_expo), + .f_byp_ex1_s_frac(f_byp_ex1_s_frac), + + .f_dcd_ex1_div_beg(tidn), //i--fbyp + + .f_dcd_ex1_uc_fa_pos(f_dcd_ex1_uc_fa_pos), //i--fbyp + .f_dcd_ex1_uc_fc_pos(f_dcd_ex1_uc_fc_pos), //i--fbyp + .f_dcd_ex1_uc_fb_pos(f_dcd_ex1_uc_fb_pos), //i--fbyp + .f_dcd_ex1_uc_fc_0_5(f_dcd_ex1_uc_fc_0_5), //i--fbyp + .f_dcd_ex1_uc_fc_1_0(f_dcd_ex1_uc_fc_1_0), //i--fbyp + .f_dcd_ex1_uc_fc_1_minus(f_dcd_ex1_uc_fc_1_minus), //i--fbyp + .f_dcd_ex1_uc_fb_1_0(f_dcd_ex1_uc_fb_1_0), //i--fbyp + .f_dcd_ex1_uc_fb_0_75(f_dcd_ex1_uc_fb_0_75), //i--fbyp + .f_dcd_ex1_uc_fb_0_5(f_dcd_ex1_uc_fb_0_5), //i--fbyp + + .f_dcd_ex1_uc_fc_hulp(f_dcd_ex1_uc_fc_hulp), //i--fbyp + .f_dcd_ex1_bypsel_a_res0(f_dcd_ex1_bypsel_a_res0), //i--fbyp + .f_dcd_ex1_bypsel_a_res1(f_dcd_ex1_bypsel_a_res1), //i--fbyp + .f_dcd_ex1_bypsel_a_load0(f_dcd_ex1_bypsel_a_load0), //i--fbyp + .f_dcd_ex1_bypsel_a_load1(f_dcd_ex1_bypsel_a_load1), //i--fbyp + .f_dcd_ex1_bypsel_a_load2(f_dcd_ex1_bypsel_a_load2), + .f_dcd_ex1_bypsel_a_reload0(f_dcd_ex1_bypsel_a_reload0), //i--fbyp + .f_dcd_ex1_bypsel_a_reload1(f_dcd_ex1_bypsel_a_reload1), //i--fbyp + .f_dcd_ex1_bypsel_a_reload2(f_dcd_ex1_bypsel_a_reload2), + + .f_dcd_ex1_bypsel_b_res0(f_dcd_ex1_bypsel_b_res0), //i--fbyp + .f_dcd_ex1_bypsel_b_res1(f_dcd_ex1_bypsel_b_res1), //i--fbyp + .f_dcd_ex1_bypsel_b_load0(f_dcd_ex1_bypsel_b_load0), //i--fbyp + .f_dcd_ex1_bypsel_b_load1(f_dcd_ex1_bypsel_b_load1), //i--fbyp + .f_dcd_ex1_bypsel_b_load2(f_dcd_ex1_bypsel_b_load2), + .f_dcd_ex1_bypsel_b_reload0(f_dcd_ex1_bypsel_b_reload0), //i--fbyp + .f_dcd_ex1_bypsel_b_reload1(f_dcd_ex1_bypsel_b_reload1), //i--fbyp + .f_dcd_ex1_bypsel_b_reload2(f_dcd_ex1_bypsel_b_reload2), + + .f_dcd_ex1_bypsel_c_res0(f_dcd_ex1_bypsel_c_res0), //i--fbyp + .f_dcd_ex1_bypsel_c_res1(f_dcd_ex1_bypsel_c_res1), //i--fbyp + .f_dcd_ex1_bypsel_c_load0(f_dcd_ex1_bypsel_c_load0), //i--fbyp + .f_dcd_ex1_bypsel_c_load1(f_dcd_ex1_bypsel_c_load1), //i--fbyp + .f_dcd_ex1_bypsel_c_load2(f_dcd_ex1_bypsel_c_load2), + .f_dcd_ex1_bypsel_c_reload0(f_dcd_ex1_bypsel_c_reload0), //i--fbyp + .f_dcd_ex1_bypsel_c_reload1(f_dcd_ex1_bypsel_c_reload1), //i--fbyp + .f_dcd_ex1_bypsel_c_reload2(f_dcd_ex1_bypsel_c_reload2), + + .f_dcd_ex1_bypsel_a_res2(f_dcd_ex1_bypsel_a_res2), + .f_dcd_ex1_bypsel_b_res2(f_dcd_ex1_bypsel_b_res2), + .f_dcd_ex1_bypsel_c_res2(f_dcd_ex1_bypsel_c_res2), + .f_dcd_ex1_bypsel_s_res0(f_dcd_ex1_bypsel_s_res0), + .f_dcd_ex1_bypsel_s_res1(f_dcd_ex1_bypsel_s_res1), + .f_dcd_ex1_bypsel_s_res2(f_dcd_ex1_bypsel_s_res2), + .f_dcd_ex1_bypsel_s_load0(f_dcd_ex1_bypsel_s_load0), + .f_dcd_ex1_bypsel_s_load1(f_dcd_ex1_bypsel_s_load1), + .f_dcd_ex1_bypsel_s_load2(f_dcd_ex1_bypsel_s_load2), + .f_dcd_ex1_bypsel_s_reload0(f_dcd_ex1_bypsel_s_reload0), + .f_dcd_ex1_bypsel_s_reload1(f_dcd_ex1_bypsel_s_reload1), + .f_dcd_ex1_bypsel_s_reload2(f_dcd_ex1_bypsel_s_reload2), + + .f_rnd_ex7_res_sign(rnd_ex7_res_sign), //i--fbyp + .f_rnd_ex7_res_expo(rnd_ex7_res_expo[1:13]), //i--fbyp + .f_rnd_ex7_res_frac(rnd_ex7_res_frac[0:52]), //i--fbyp + + .f_fpr_ex1_a_sign(f_fpr_ex1_a_sign), //i--fbyp + .f_fpr_ex1_a_expo(f_fpr_ex1_a_expo[1:13]), //i--fbyp + .f_fpr_ex1_a_frac(f_fpr_ex1_a_frac[0:52]), //i--fbyp + .f_fpr_ex1_c_sign(f_fpr_ex1_c_sign), //i--fbyp + .f_fpr_ex1_c_expo(f_fpr_ex1_c_expo[1:13]), //i--fbyp + .f_fpr_ex1_c_frac(f_fpr_ex1_c_frac[0:52]), //i--fbyp + .f_fpr_ex1_b_sign(f_fpr_ex1_b_sign), //i--fbyp + .f_fpr_ex1_b_expo(f_fpr_ex1_b_expo[1:13]), //i--fbyp + .f_fpr_ex1_b_frac(f_fpr_ex1_b_frac[0:52]), //i--fbyp + .f_dcd_ex1_aop_valid(f_dcd_ex1_aop_valid), //i--fbyp + .f_dcd_ex1_cop_valid(f_dcd_ex1_cop_valid), //i--fbyp + .f_dcd_ex1_bop_valid(f_dcd_ex1_bop_valid), //i--fbyp + .f_dcd_ex1_sp(f_dcd_ex1_sp), //i--fbyp + .f_dcd_ex1_to_integer_b(f_dcd_ex1_to_integer_b), //i--fbyp + .f_dcd_ex1_emin_dp(f_dcd_ex1_emin_dp), //i--fbyp + .f_dcd_ex1_emin_sp(f_dcd_ex1_emin_sp), //i--fbyp + + .f_byp_fmt_ex2_a_expo(f_byp_fmt_ex2_a_expo[1:13]), //o--fbyp + .f_byp_eie_ex2_a_expo(f_byp_eie_ex2_a_expo[1:13]), //o--fbyp + .f_byp_alg_ex2_a_expo(f_byp_alg_ex2_a_expo[1:13]), //o--fbyp + .f_byp_fmt_ex2_c_expo(f_byp_fmt_ex2_c_expo[1:13]), //o--fbyp + .f_byp_eie_ex2_c_expo(f_byp_eie_ex2_c_expo[1:13]), //o--fbyp + .f_byp_alg_ex2_c_expo(f_byp_alg_ex2_c_expo[1:13]), //o--fbyp + .f_byp_fmt_ex2_b_expo(f_byp_fmt_ex2_b_expo[1:13]), //o--fbyp + .f_byp_eie_ex2_b_expo(f_byp_eie_ex2_b_expo[1:13]), //o--fbyp + .f_byp_alg_ex2_b_expo(f_byp_alg_ex2_b_expo[1:13]), //o--fbyp + .f_byp_fmt_ex2_a_sign(f_byp_fmt_ex2_a_sign), //o--fbyp + .f_byp_fmt_ex2_c_sign(f_byp_fmt_ex2_c_sign), //o--fbyp + .f_byp_fmt_ex2_b_sign(f_byp_fmt_ex2_b_sign), //o--fbyp + .f_byp_pic_ex2_a_sign(f_byp_pic_ex2_a_sign), //o--fbyp + .f_byp_pic_ex2_c_sign(f_byp_pic_ex2_c_sign), //o--fbyp + .f_byp_pic_ex2_b_sign(f_byp_pic_ex2_b_sign), //o--fbyp + .f_byp_alg_ex2_b_sign(f_byp_alg_ex2_b_sign), //o--fbyp + .f_byp_mul_ex2_a_frac_17(f_byp_mul_ex2_a_frac_17), //o--fbyp + .f_byp_mul_ex2_a_frac_35(f_byp_mul_ex2_a_frac_35), //o--fbyp + .f_byp_mul_ex2_a_frac(f_byp_mul_ex2_a_frac[0:52]), //o--fbyp + .f_byp_fmt_ex2_a_frac(f_byp_fmt_ex2_a_frac[0:52]), //o--fbyp + .f_byp_mul_ex2_c_frac({f_byp_mul_ex2_c_frac[0:52], f_byp_mul_ex2_c_frac[53]}), //o--fbyp + .f_byp_fmt_ex2_c_frac(f_byp_fmt_ex2_c_frac[0:52]), //o--fbyp + .f_byp_alg_ex2_b_frac(f_byp_alg_ex2_b_frac[0:52]), //o--fbyp + .f_byp_fmt_ex2_b_frac(f_byp_fmt_ex2_b_frac[0:52]) //o--fbyp + ); + //--------------------------------------------------------- -- fuq_byp.vhdl + + + + // fu_fmt.vhdl + fu_fmt ffmt( + //----------------------------------------------------------- fu_fmt.vhdl + .vdd(vdd), //i-- + .gnd(gnd), //i-- + .nclk(nclk), //i-- + .clkoff_b(clkoff_b), //i-- + .act_dis(act_dis), //i-- + .flush(flush), //i-- + .delay_lclkr(delay_lclkr[1:2]), //i-- + .mpw1_b(mpw1_b[1:2]), //i-- + .mpw2_b(mpw2_b[0:0]), //i-- + .thold_1(perv_fmt_thold_1), //i-- + .sg_1(perv_fmt_sg_1), //i-- + .fpu_enable(perv_fmt_fpu_enable), //i-- + + .f_fmt_si(scan_in[1]), //i--ffmt + .f_fmt_so(scan_out[1]), //o--ffmt + .ex1_act(f_dcd_ex1_act), + .ex2_act(f_pic_fmt_ex2_act), + + .f_dcd_ex2_perr_force_c(f_dcd_ex2_perr_force_c), + .f_dcd_ex2_perr_fsel_ovrd(f_dcd_ex2_perr_fsel_ovrd), + .f_pic_ex2_ftdiv(f_pic_ex2_ftdiv), + .f_fmt_ex3_be_den(f_fmt_ex3_be_den), + .f_fpr_ex2_a_par(f_fpr_ex2_a_par[0:7]), //i--ffmt + .f_fpr_ex2_c_par(f_fpr_ex2_c_par[0:7]), //i--ffmt + .f_fpr_ex2_b_par(f_fpr_ex2_b_par[0:7]), //i--ffmt + + .f_mad_ex3_a_parity_check(f_mad_ex3_a_parity_check), //o--ffmt + .f_mad_ex3_c_parity_check(f_mad_ex3_c_parity_check), //o--ffmt + .f_mad_ex3_b_parity_check(f_mad_ex3_b_parity_check), //o--ffmt + .f_fmt_ex3_ae_ge_54(f_fmt_ex3_ae_ge_54), //o--ffmt + .f_fmt_ex3_be_ge_54(f_fmt_ex3_be_ge_54), //o--ffmt + .f_fmt_ex3_be_ge_2(f_fmt_ex3_be_ge_2), //o--ffmt + .f_fmt_ex3_be_ge_2044(f_fmt_ex3_be_ge_2044), //o--ffmt + .f_fmt_ex3_tdiv_rng_chk(f_fmt_ex3_tdiv_rng_chk), //o--ffmt + + .f_byp_fmt_ex2_a_sign(f_byp_fmt_ex2_a_sign), //i--ffmt + .f_byp_fmt_ex2_c_sign(f_byp_fmt_ex2_c_sign), //i--ffmt + .f_byp_fmt_ex2_b_sign(f_byp_fmt_ex2_b_sign), //i--ffmt + .f_byp_fmt_ex2_a_expo(f_byp_fmt_ex2_a_expo[1:13]), //i--ffmt + .f_byp_fmt_ex2_c_expo(f_byp_fmt_ex2_c_expo[1:13]), //i--ffmt + .f_byp_fmt_ex2_b_expo(f_byp_fmt_ex2_b_expo[1:13]), //i--ffmt + + .f_byp_fmt_ex2_a_frac(f_byp_fmt_ex2_a_frac[0:52]), //i--ffmt + .f_byp_fmt_ex2_c_frac(f_byp_fmt_ex2_c_frac[0:52]), //i--ffmt + .f_byp_fmt_ex2_b_frac(f_byp_fmt_ex2_b_frac[0:52]), //i--ffmt + + .f_dcd_ex1_sp(f_dcd_ex1_sp), //i--ffmt + .f_dcd_ex1_from_integer_b(f_dcd_ex1_from_integer_b), //i--ffmt + .f_dcd_ex1_sgncpy_b(f_dcd_ex1_sgncpy_b), //i--ffmt + .f_dcd_ex1_uc_mid(f_dcd_ex1_uc_mid), //i--ffmt + .f_dcd_ex1_uc_end(f_dcd_ex1_uc_end), //i--ffmt + .f_dcd_ex1_uc_special(f_dcd_ex1_uc_special), //i--ffmt + .f_dcd_ex1_aop_valid(f_dcd_ex1_aop_valid), //i--ffmt + .f_dcd_ex1_cop_valid(f_dcd_ex1_cop_valid), //i--ffmt + .f_dcd_ex1_bop_valid(f_dcd_ex1_bop_valid), //i--ffmt + .f_dcd_ex1_fsel_b(f_dcd_ex1_fsel_b), //i--ffmt + .f_dcd_ex1_force_pass_b(f_dcd_ex1_force_pass_b), //i--ffmt + .f_dcd_ex2_divsqrt_v(f_dcd_ex2_divsqrt_v), //i--ffmt + .f_pic_ex2_flush_en_sp(f_pic_ex2_flush_en_sp), //i--ffmt + .f_pic_ex2_flush_en_dp(f_pic_ex2_flush_en_dp), //i--ffmt + .f_pic_ex2_nj_deni(f_pic_ex2_nj_deni), //i--ffmt (connect) + .f_fmt_ex3_lu_den_recip(f_fmt_ex3_lu_den_recip), //o--ffmt + .f_fmt_ex3_lu_den_rsqrto(f_fmt_ex3_lu_den_rsqrto), //o--ffmt + .f_fmt_ex2_bop_byt(f_fmt_ex2_bop_byt[45:52]), //o--ffmt + .f_fmt_ex2_b_frac(f_fmt_ex2_b_frac[1:19]), //o--ffmt + + .f_fmt_ex2_a_sign_div(f_fmt_ex2_a_sign_div), //o--fdsq -- :in std_ulogic; + .f_fmt_ex2_a_expo_div_b(f_fmt_ex2_a_expo_div_b), //o--fdsq -- :in std_ulogic_vector(01 to 13); + .f_fmt_ex2_a_frac_div(f_fmt_ex2_a_frac_div), //o--fdsq -- :in std_ulogic_vector(01 to 52); + + .f_fmt_ex2_b_sign_div(f_fmt_ex2_b_sign_div), //o--fdsq -- :in std_ulogic; + .f_fmt_ex2_b_expo_div_b(f_fmt_ex2_b_expo_div_b), //o--fdsq -- :in std_ulogic_vector(01 to 13); + .f_fmt_ex2_b_frac_div(f_fmt_ex2_b_frac_div), //o--fdsq -- :in std_ulogic_vector(01 to 52); + + .f_fmt_ex2_bexpu_le126(f_fmt_ex2_bexpu_le126), //o--ffmt + .f_fmt_ex2_gt126(f_fmt_ex2_gt126), //o--ffmt + .f_fmt_ex2_ge128(f_fmt_ex2_ge128), //o--ffmt + .f_fmt_ex2_inf_and_beyond_sp(f_fmt_ex2_inf_and_beyond_sp), //o--ffmt + + .f_fmt_ex2_b_sign_gst(f_fmt_ex2_b_sign_gst), //o--ffmt + .f_fmt_ex2_b_expo_gst_b(f_fmt_ex2_b_expo_gst_b[1:13]), //o--ffmt + .f_mad_ex3_uc_a_expo_den(f_mad_ex3_uc_a_expo_den), //o--ffmt + .f_mad_ex3_uc_a_expo_den_sp(f_mad_ex3_uc_a_expo_den_sp), //o--ffmt + .f_fmt_ex2_a_zero(f_fmt_ex2_a_zero), //o--ffmt + .f_fmt_ex2_a_zero_dsq(f_fmt_ex2_a_zero_dsq), //o--ffmt + .f_fmt_ex2_a_expo_max(f_fmt_ex2_a_expo_max), //o--ffmt + .f_fmt_ex2_a_expo_max_dsq(f_fmt_ex2_a_expo_max_dsq), //o--ffmt + .f_fmt_ex2_a_frac_zero(f_fmt_ex2_a_frac_zero), //o--ffmt + .f_fmt_ex2_a_frac_msb(f_fmt_ex2_a_frac_msb), //o--ffmt + .f_fmt_ex2_c_zero(f_fmt_ex2_c_zero), //o--ffmt + .f_fmt_ex2_c_expo_max(f_fmt_ex2_c_expo_max), //o--ffmt + .f_fmt_ex2_c_frac_zero(f_fmt_ex2_c_frac_zero), //o--ffmt + .f_fmt_ex2_c_frac_msb(f_fmt_ex2_c_frac_msb), //o--ffmt + .f_fmt_ex2_b_zero(f_fmt_ex2_b_zero), //o--ffmt + .f_fmt_ex2_b_zero_dsq(f_fmt_ex2_b_zero_dsq), //o--ffmt + .f_fmt_ex2_b_expo_max(f_fmt_ex2_b_expo_max), //o--ffmt + .f_fmt_ex2_b_expo_max_dsq(f_fmt_ex2_b_expo_max_dsq), //o--ffmt + .f_fmt_ex2_b_frac_zero(f_fmt_ex2_b_frac_zero), //o--ffmt + .f_fmt_ex2_b_frac_msb(f_fmt_ex2_b_frac_msb), //o--ffmt + .f_fmt_ex2_b_frac_z32(f_fmt_ex2_b_frac_z32), //o--ffmt + .f_fmt_ex2_prod_zero(f_fmt_ex2_prod_zero), //o--ffmt + .f_fmt_ex2_pass_sel(f_fmt_ex2_pass_sel), //o--ffmt + .f_fmt_ex2_sp_invalid(f_fmt_ex2_sp_invalid), //o--ffmt + .f_ex3_b_den_flush(f_ex3_b_den_flush), //o--ffmt + .f_fmt_ex3_fsel_bsel(f_fmt_ex3_fsel_bsel), //o--ffmt + .f_fmt_ex3_pass_sign(f_fmt_ex3_pass_sign), //o--ffmt + .f_fmt_ex3_pass_msb(f_fmt_ex3_pass_msb), //o--ffmt + .f_fmt_ex2_b_imp(f_fmt_ex2_b_imp), //o--ffmt + .f_fmt_ex3_pass_frac(f_fmt_ex3_pass_frac[0:52]) //o--ffmt + ); + //----------------------------------------------------------- fu_fmt.vhdl + + // fu_eie.vhdl + fu_eie feie( + //----------------------------------------------------------- fu_eie.vhdl + .vdd(vdd), //i-- + .gnd(gnd), //i-- + .nclk(nclk), //i-- + .clkoff_b(clkoff_b), //i-- + .act_dis(act_dis), //i-- + .flush(flush), //i-- + .delay_lclkr(delay_lclkr[2:3]), //i-- + .mpw1_b(mpw1_b[2:3]), //i-- + .mpw2_b(mpw2_b[0:0]), //i-- + .thold_1(perv_eie_thold_1), //i-- + .sg_1(perv_eie_sg_1), //i-- + .fpu_enable(perv_eie_fpu_enable), //i-- + + .f_eie_si(scan_in[2]), //i--feie + .f_eie_so(scan_out[2]), //o--feie + .ex2_act(f_pic_eie_ex2_act), //i--feie + .f_byp_eie_ex2_a_expo(f_byp_eie_ex2_a_expo[1:13]), //i--feie + .f_byp_eie_ex2_c_expo(f_byp_eie_ex2_c_expo[1:13]), //i--feie + .f_byp_eie_ex2_b_expo(f_byp_eie_ex2_b_expo[1:13]), //i--feie + .f_pic_ex2_from_integer(f_pic_ex2_from_integer), //i--feie + .f_pic_ex2_fsel(f_pic_ex2_fsel), //i--feie + .f_pic_ex3_frsp_ue1(f_pic_ex3_frsp_ue1), //i--feie + .f_alg_ex3_sel_byp(f_alg_ex3_sel_byp), //i--feie + .f_fmt_ex3_fsel_bsel(f_fmt_ex3_fsel_bsel), //i--feie + .f_pic_ex3_force_sel_bexp(f_pic_ex3_force_sel_bexp), //i--feie + .f_pic_ex3_sp_b(f_pic_ex3_sp_b), //i--feie + .f_pic_ex3_math_bzer_b(f_pic_ex3_math_bzer_b), //i--feie + .f_eie_ex3_lt_bias(f_eie_ex3_lt_bias), //o--feie + .f_eie_ex3_eq_bias_m1(f_eie_ex3_eq_bias_m1), //o--feie + .f_eie_ex3_wd_ov(f_eie_ex3_wd_ov), //o--feie + .f_eie_ex3_dw_ov(f_eie_ex3_dw_ov), //o--feie + .f_eie_ex3_wd_ov_if(f_eie_ex3_wd_ov_if), //o--feie + .f_eie_ex3_dw_ov_if(f_eie_ex3_dw_ov_if), //o--feie + .f_eie_ex3_lzo_expo(f_eie_ex3_lzo_expo[1:13]), //o--feie + .f_eie_ex3_b_expo(f_eie_ex3_b_expo[1:13]), //o--feie + .f_eie_ex3_use_bexp(f_eie_ex3_use_bexp), //o--feie + .f_eie_ex3_tbl_expo(f_eie_ex3_tbl_expo[1:13]), //o--feie + .f_eie_ex4_iexp(f_eie_ex4_iexp[1:13]) //o--feie + ); + //----------------------------------------------------------- fu_eie.vhdl + + // fu_eov.vhdl + fu_eov feov( + //----------------------------------------------------------- fu_eov.vhdl + .vdd(vdd), //i-- + .gnd(gnd), //i-- + .nclk(nclk), //i-- + .clkoff_b(clkoff_b), //i-- + .act_dis(act_dis), //i-- + .flush(flush), //i-- + .delay_lclkr(delay_lclkr[4:5]), //i-- + .mpw1_b(mpw1_b[4:5]), //i-- + .mpw2_b(mpw2_b[0:1]), //i-- + .thold_1(perv_eov_thold_1), //i-- + .sg_1(perv_eov_sg_1), //i-- + .fpu_enable(perv_eov_fpu_enable), //i-- + + .f_eov_si(scan_in[3]), //i--feov + .f_eov_so(scan_out[3]), //o--feov + .ex3_act_b(f_pic_eov_ex3_act_b), //i--feov + .f_tbl_ex5_unf_expo(f_tbl_ex5_unf_expo), //i--feov + .f_tbe_ex4_may_ov(f_tbe_ex4_may_ov), //i--feov + .f_tbe_ex4_expo(f_tbe_ex4_res_expo[1:13]), //i--feov + .f_pic_ex4_sel_est(f_pic_ex4_sel_est), //i--feov + .f_eie_ex4_iexp(f_eie_ex4_iexp[1:13]), //i--feov + .f_pic_ex4_sp_b(f_pic_ex4_sp_b), //i--feov + .f_lza_ex5_sh_rgt_en_eov(f_lza_ex5_sh_rgt_en_eov), //i--feov + .f_pic_ex5_oe(f_pic_ex5_oe), //i--feov + .f_pic_ex5_ue(f_pic_ex5_ue), //i--feov + .f_pic_ex5_ov_en(f_pic_ex5_ov_en), //i--feov + .f_pic_ex5_uf_en(f_pic_ex5_uf_en), //i--feov + .f_pic_ex5_spec_sel_k_e(f_pic_ex5_spec_sel_k_e), //i--feov + .f_pic_ex5_spec_sel_k_f(f_pic_ex5_spec_sel_k_f), //i--feov + .f_pic_ex5_sel_ov_spec(tidn), //i--feov UNUSED DELETE + + .f_pic_ex5_to_int_ov_all(f_pic_ex5_to_int_ov_all), //i--feov + + .f_lza_ex5_no_lza_edge(f_lza_ex5_no_lza_edge), //i--feov + .f_lza_ex5_lza_amt_eov(f_lza_ex5_lza_amt_eov[0:7]), //i--feov + .f_nrm_ex5_extra_shift(f_nrm_ex5_extra_shift), //i--feov + .f_eov_ex5_may_ovf(f_eov_ex5_may_ovf), //o--feov + .f_eov_ex6_sel_k_f(f_eov_ex6_sel_k_f), //o--feov + .f_eov_ex6_sel_k_e(f_eov_ex6_sel_k_e), //o--feov + .f_eov_ex6_sel_kif_f(f_eov_ex6_sel_kif_f), //o--feov + .f_eov_ex6_sel_kif_e(f_eov_ex6_sel_kif_e), //o--feov + .f_eov_ex6_unf_expo(f_eov_ex6_unf_expo), //o--feov + .f_eov_ex6_ovf_expo(f_eov_ex6_ovf_expo), //o--feov + .f_eov_ex6_ovf_if_expo(f_eov_ex6_ovf_if_expo), //o--feov + .f_eov_ex6_expo_p0(f_eov_ex6_expo_p0[1:13]), //o--feov + .f_eov_ex6_expo_p1(f_eov_ex6_expo_p1[1:13]), //o--feov + .f_eov_ex6_expo_p0_ue1oe1(f_eov_ex6_expo_p0_ue1oe1[3:7]), //o--feov + .f_eov_ex6_expo_p1_ue1oe1(f_eov_ex6_expo_p1_ue1oe1[3:7]) //o--feov + ); + //----------------------------------------------------------- fu_eov.vhdl + + + + // fu_mul.vhdl + tri_fu_mul fmul( + //----------------------------------------------------------- fu_mul.vhdl + .vdd(vdd), //i-- + .gnd(gnd), //i-- + .nclk(nclk), //i-- + .clkoff_b(clkoff_b), //i-- + .act_dis(act_dis), //i-- + .flush(flush), //i-- + .delay_lclkr(delay_lclkr[2]), //i-- + .mpw1_b(mpw1_b[2]), //i-- + .mpw2_b(mpw2_b[0]), //i-- + .thold_1(perv_mul_thold_1), //i-- + .sg_1(perv_mul_sg_1), //i-- + .fpu_enable(perv_mul_fpu_enable), //i-- + + .f_mul_si(scan_in[4]), //i--fmul + .f_mul_so(scan_out[4]), //o--fmul + .ex2_act(f_pic_mul_ex2_act), //i--fmul + .f_fmt_ex2_a_frac(f_byp_mul_ex2_a_frac[0:52]), //i--fmul + .f_fmt_ex2_a_frac_17(f_byp_mul_ex2_a_frac_17), //i--fmul + .f_fmt_ex2_a_frac_35(f_byp_mul_ex2_a_frac_35), //i--fmul + .f_fmt_ex2_c_frac(f_byp_mul_ex2_c_frac[0:53]), //i--fmul + .f_mul_ex3_sum(f_mul_ex3_sum[1:108]), //o--fmul + .f_mul_ex3_car(f_mul_ex3_car[1:108]) //o--fmul + ); + //----------------------------------------------------------- fu_mul.vhdl + + // fu_alg.vhdl + fu_alg falg( + //----------------------------------------------------------- fu_alg.vhdl + .vdd(vdd), //i-- + .gnd(gnd), //i-- + .nclk(nclk), //i-- + .clkoff_b(clkoff_b), //i-- + .act_dis(act_dis), //i-- + .flush(flush), //i-- + .delay_lclkr(delay_lclkr[1:3]), //i-- + .mpw1_b(mpw1_b[1:3]), //i-- + .mpw2_b(mpw2_b[0:0]), //i-- + .thold_1(perv_alg_thold_1), //i-- + .sg_1(perv_alg_sg_1), //i-- + .fpu_enable(perv_alg_fpu_enable), //i-- + + .f_alg_si(scan_in[5]), //i--falg + .f_alg_so(scan_out[5]), //o--falg + .ex1_act(f_dcd_ex1_act), //i--falg + .ex2_act(f_pic_alg_ex2_act), //i--falg + .f_dcd_ex1_sp(f_dcd_ex1_sp), //i--falg + + .f_pic_ex2_frsp_ue1(f_pic_ex2_frsp_ue1), //i--feie WRONG cycle (move to ex2) + + .f_byp_alg_ex2_b_frac(f_byp_alg_ex2_b_frac[0:52]), //i--falg + .f_byp_alg_ex2_b_sign(f_byp_alg_ex2_b_sign), //i--falg + .f_byp_alg_ex2_b_expo(f_byp_alg_ex2_b_expo[1:13]), //i--falg + .f_byp_alg_ex2_a_expo(f_byp_alg_ex2_a_expo[1:13]), //i--falg + .f_byp_alg_ex2_c_expo(f_byp_alg_ex2_c_expo[1:13]), //i--falg + + .f_fmt_ex2_prod_zero(f_fmt_ex2_prod_zero), //i--falg + .f_fmt_ex2_b_zero(f_fmt_ex2_b_zero), //i--falg + .f_fmt_ex2_pass_sel(f_fmt_ex2_pass_sel), //i--falg + .f_fmt_ex3_pass_frac(f_fmt_ex3_pass_frac[0:52]), //i--falg + .f_dcd_ex1_word_b(f_dcd_ex1_word_b), //i--falg + .f_dcd_ex1_uns_b(f_dcd_ex1_uns_b), //i--falg + .f_dcd_ex1_from_integer_b(f_dcd_ex1_from_integer_b), //i--falg + .f_dcd_ex1_to_integer_b(f_dcd_ex1_to_integer_b), //i--falg + .f_pic_ex2_rnd_to_int(f_pic_ex2_rnd_to_int), //i--falg + .f_pic_ex2_effsub_raw(f_pic_ex2_effsub_raw), //i--falg + .f_pic_ex2_sh_unf_ig_b(f_pic_ex2_sh_unf_ig_b), //i--falg + .f_pic_ex2_sh_unf_do(f_pic_ex2_sh_unf_do), //i--falg + .f_pic_ex2_sh_ovf_ig_b(f_pic_ex2_sh_ovf_ig_b), //i--falg + .f_pic_ex2_sh_ovf_do(f_pic_ex2_sh_ovf_do), //i--falg + .f_pic_ex3_rnd_nr(f_pic_ex3_rnd_nr), //i--falg + .f_pic_ex3_rnd_inf_ok(f_pic_ex3_rnd_inf_ok), //i--falg + .f_alg_ex2_sign_frmw(f_alg_ex2_sign_frmw), //o--falg + .f_alg_ex3_res(f_alg_ex3_res[0:162]), //o--falg + .f_alg_ex3_sel_byp(f_alg_ex3_sel_byp), //o--falg + .f_alg_ex3_effsub_eac_b(f_alg_ex3_effsub_eac_b), //o--falg + .f_alg_ex3_prod_z(f_alg_ex3_prod_z), //o--falg + .f_alg_ex3_sh_unf(f_alg_ex3_sh_unf), //o--falg + .f_alg_ex3_sh_ovf(f_alg_ex3_sh_ovf), //o--falg + .f_alg_ex3_byp_nonflip(f_alg_ex3_byp_nonflip), //o--falg + .f_alg_ex4_frc_sel_p1(f_alg_ex4_frc_sel_p1), //o--falg + .f_alg_ex4_sticky(f_alg_ex4_sticky), //o--falg + .f_alg_ex4_int_fr(f_alg_ex4_int_fr), //o--falg + .f_alg_ex4_int_fi(f_alg_ex4_int_fi) //o--falg + ); + //----------------------------------------------------------- fu_alg.vhdl + + // fuq_sa3.vhdl + fu_sa3 fsa3( + //----------------------------------------------------------- fuq_sa3.vhdl + .vdd(vdd), //i-- + .gnd(gnd), //i-- + .nclk(nclk), //i-- + .clkoff_b(clkoff_b), //i-- + .act_dis(act_dis), //i-- + .flush(flush), //i-- + .delay_lclkr(delay_lclkr[2:3]), //i-- + .mpw1_b(mpw1_b[2:3]), //i-- + .mpw2_b(mpw2_b[0:0]), //i-- + .thold_1(perv_sa3_thold_1), //i-- + .sg_1(perv_sa3_sg_1), //i-- + .fpu_enable(perv_sa3_fpu_enable), //i-- + + .f_sa3_si(scan_in[6]), //i--fsa3 + .f_sa3_so(scan_out[6]), //o--fsa3 + .ex2_act_b(f_pic_add_ex2_act_b), //i--fsa3 + .f_mul_ex3_sum(f_mul_ex3_sum[1:108]), //i--fsa3 + .f_mul_ex3_car(f_mul_ex3_car[1:108]), //i--fsa3 + .f_alg_ex3_res(f_alg_ex3_res[0:162]), //i--fsa3 + .f_sa3_ex4_s_lza(f_sa3_ex4_s_lza[0:162]), //o--fsa3 + .f_sa3_ex4_c_lza(f_sa3_ex4_c_lza[53:161]), //o--fsa3 + .f_sa3_ex4_s_add(f_sa3_ex4_s_add[0:162]), //o--fsa3 + .f_sa3_ex4_c_add(f_sa3_ex4_c_add[53:161]) //o--fsa3 + ); + //----------------------------------------------------------- fuq_sa3.vhdl + + // fu_add.vhdl + fu_add fadd( + //----------------------------------------------------------- fu_add.vhdl + .vdd(vdd), //i-- + .gnd(gnd), //i-- + .nclk(nclk), //i-- + .clkoff_b(clkoff_b), //i-- + .act_dis(act_dis), //i-- + .flush(flush), //i-- + .delay_lclkr(delay_lclkr[3:4]), //i-- + .mpw1_b(mpw1_b[3:4]), //i-- + .mpw2_b(mpw2_b[0:0]), //i-- + .thold_1(perv_add_thold_1), //i-- + .sg_1(perv_add_sg_1), //i-- + .fpu_enable(perv_add_fpu_enable), //i-- + + .f_add_si(scan_in[7]), //i--fadd + .f_add_so(scan_out[7]), //o--fadd + .ex2_act_b(f_pic_add_ex2_act_b), //i--fadd + .f_sa3_ex4_s(f_sa3_ex4_s_add[0:162]), //i--fadd + .f_sa3_ex4_c(f_sa3_ex4_c_add[53:161]), //i--fadd + .f_alg_ex4_frc_sel_p1(f_alg_ex4_frc_sel_p1), //i--fadd + .f_alg_ex4_sticky(f_alg_ex4_sticky), //i--fadd + .f_alg_ex3_effsub_eac_b(f_alg_ex3_effsub_eac_b), //i--fadd + .f_alg_ex3_prod_z(f_alg_ex3_prod_z), //i--fadd + .f_pic_ex4_is_gt(f_pic_ex4_is_gt), //i--fadd + .f_pic_ex4_is_lt(f_pic_ex4_is_lt), //i--fadd + .f_pic_ex4_is_eq(f_pic_ex4_is_eq), //i--fadd + .f_pic_ex4_is_nan(f_pic_ex4_is_nan), //i--fadd + .f_pic_ex4_cmp_sgnpos(f_pic_ex4_cmp_sgnpos), //i--fadd + .f_pic_ex4_cmp_sgnneg(f_pic_ex4_cmp_sgnneg), //i--fadd + .f_add_ex5_res(f_add_ex5_res[0:162]), //o--fadd + .f_add_ex5_flag_nan(f_add_ex5_flag_nan), //o--fadd + .f_add_ex5_flag_gt(f_add_ex5_flag_gt), //o--fadd + .f_add_ex5_flag_lt(f_add_ex5_flag_lt), //o--fadd + .f_add_ex5_flag_eq(f_add_ex5_flag_eq), //o--fadd + .f_add_ex5_fpcc_iu(f_add_ex5_fpcc_iu[0:3]), //o--fadd + .f_add_ex5_sign_carry(f_add_ex5_sign_carry), //o--fadd + .f_add_ex5_to_int_ovf_wd(f_add_ex5_to_int_ovf_wd[0:1]), //o--fadd + .f_add_ex5_to_int_ovf_dw(f_add_ex5_to_int_ovf_dw[0:1]), //o--fadd + .f_add_ex5_sticky(f_add_ex5_sticky) //o--fadd + ); + //----------------------------------------------------------- fu_add.vhdl + + // fu_lze.vhdl + fu_lze flze( + //----------------------------------------------------------- fu_lze.vhdl + .vdd(vdd), //i-- + .gnd(gnd), //i-- + .nclk(nclk), //i-- + .clkoff_b(clkoff_b), //i-- + .act_dis(act_dis), //i-- + .flush(flush), //i-- + .delay_lclkr(delay_lclkr[2:3]), //i-- + .mpw1_b(mpw1_b[2:3]), //i-- + .mpw2_b(mpw2_b[0:0]), //i-- + .thold_1(perv_lza_thold_1), //i-- + .sg_1(perv_lza_sg_1), //i-- + .fpu_enable(perv_lza_fpu_enable), //i-- + + .f_lze_si(scan_in[8]), //i--flze + .f_lze_so(scan_out[8]), //o--flze + .ex2_act_b(f_pic_lza_ex2_act_b), //i--flze + .f_eie_ex3_lzo_expo(f_eie_ex3_lzo_expo[1:13]), //i--flze + .f_eie_ex3_b_expo(f_eie_ex3_b_expo[1:13]), //i--flze + .f_pic_ex3_est_recip(f_pic_ex3_est_recip), //i--flze + .f_pic_ex3_est_rsqrt(f_pic_ex3_est_rsqrt), //i--flze + .f_alg_ex3_byp_nonflip(f_alg_ex3_byp_nonflip), //i--flze + .f_eie_ex3_use_bexp(f_eie_ex3_use_bexp), //i--flze + .f_pic_ex3_b_valid(f_pic_ex3_b_valid), //i--flze + .f_pic_ex3_lzo_dis_prod(f_pic_ex3_lzo_dis_prod), //i--flze + .f_pic_ex3_sp_lzo(f_pic_ex3_sp_lzo), //i--flze + .f_pic_ex3_frsp_ue1(f_pic_ex3_frsp_ue1), //i--flze + .f_fmt_ex3_pass_msb_dp(f_fmt_ex3_pass_frac[0]), //i--flze + .f_alg_ex3_sel_byp(f_alg_ex3_sel_byp), //i--flze + .f_pic_ex3_to_integer(f_pic_ex3_to_integer), //i--flze + .f_pic_ex3_prenorm(f_pic_ex3_prenorm), //i--flze + + .f_lze_ex3_lzo_din(f_lze_ex3_lzo_din[0:162]), //o--flze + .f_lze_ex4_sh_rgt_amt(f_lze_ex4_sh_rgt_amt[0:7]), //o--flze + .f_lze_ex4_sh_rgt_en(f_lze_ex4_sh_rgt_en) //o--flze + ); + + //----------------------------------------------------------- fu_lze vhdl + + // fu_lza.vhdl + fu_lza flza( + //----------------------------------------------------------- fu_lza.vhdl + .vdd(vdd), //i-- + .gnd(gnd), //i-- + .nclk(nclk), //i-- + .clkoff_b(clkoff_b), //i-- + .act_dis(act_dis), //i-- + .flush(flush), //i-- + .delay_lclkr(delay_lclkr[3:4]), //i-- + .mpw1_b(mpw1_b[3:4]), //i-- + .mpw2_b(mpw2_b[0:0]), //i-- + .thold_1(perv_lza_thold_1), //i-- + .sg_1(perv_lza_sg_1), //i-- + .fpu_enable(perv_lza_fpu_enable), //i-- + + .f_lza_si(scan_in[9]), //i--flza + .f_lza_so(scan_out[9]), //o--flza + .ex2_act_b(f_pic_lza_ex2_act_b), //i--flza + .f_sa3_ex4_s(f_sa3_ex4_s_lza[0:162]), //i--flza + .f_sa3_ex4_c(f_sa3_ex4_c_lza[53:161]), //i--flza + .f_alg_ex3_effsub_eac_b(f_alg_ex3_effsub_eac_b), //i--flza + + .f_lze_ex3_lzo_din(f_lze_ex3_lzo_din[0:162]), //i--flza + .f_lze_ex4_sh_rgt_amt(f_lze_ex4_sh_rgt_amt[0:7]), //i--flza + .f_lze_ex4_sh_rgt_en(f_lze_ex4_sh_rgt_en), //i--flza + + .f_lza_ex5_no_lza_edge(f_lza_ex5_no_lza_edge), //o--flza + .f_lza_ex5_lza_amt(f_lza_ex5_lza_amt[0:7]), //o--flza + .f_lza_ex5_sh_rgt_en(f_lza_ex5_sh_rgt_en), //o--flza + .f_lza_ex5_sh_rgt_en_eov(f_lza_ex5_sh_rgt_en_eov), //o--flza + .f_lza_ex5_lza_dcd64_cp1(f_lza_ex5_lza_dcd64_cp1[0:2]), //o--flza + .f_lza_ex5_lza_dcd64_cp2(f_lza_ex5_lza_dcd64_cp2[0:1]), //o--flza + .f_lza_ex5_lza_dcd64_cp3(f_lza_ex5_lza_dcd64_cp3[0]), //o--flza + + .f_lza_ex5_lza_amt_eov(f_lza_ex5_lza_amt_eov[0:7]) //o--flza + ); + //----------------------------------------------------------- fu_lza vhdl + + // fu_nrm.vhdl + fu_nrm fnrm( + //----------------------------------------------------------- fu_nrm.vhdl + .vdd(vdd), //i-- + .gnd(gnd), //i-- + .nclk(nclk), //i-- + .clkoff_b(clkoff_b), //i-- + .act_dis(act_dis), //i-- + .flush(flush), //i-- + .delay_lclkr(delay_lclkr[4:5]), //i-- + .mpw1_b(mpw1_b[4:5]), //i-- + .mpw2_b(mpw2_b[0:1]), //i-- + .thold_1(perv_nrm_thold_1), //i-- + .sg_1(perv_nrm_sg_1), //i-- + .fpu_enable(perv_nrm_fpu_enable), //i-- + + .f_nrm_si(scan_in[10]), //i--fnrm + .f_nrm_so(scan_out[10]), //o--fnrm + .ex4_act_b(f_pic_nrm_ex4_act_b), //i--fnrm + + .f_lza_ex5_sh_rgt_en(f_lza_ex5_sh_rgt_en), //i--fnrm + .f_lza_ex5_lza_amt_cp1(f_lza_ex5_lza_amt[0:7]), //i--fnrm + .f_lza_ex5_lza_dcd64_cp1(f_lza_ex5_lza_dcd64_cp1[0:2]), //o--fnrm + .f_lza_ex5_lza_dcd64_cp2(f_lza_ex5_lza_dcd64_cp2[0:1]), //o--fnrm + .f_lza_ex5_lza_dcd64_cp3(f_lza_ex5_lza_dcd64_cp3[0]), //o--fnrm + + .f_add_ex5_res(f_add_ex5_res[0:162]), //i--fnrm + .f_add_ex5_sticky(f_add_ex5_sticky), //i--fnrm + .f_pic_ex5_byp_prod_nz(f_pic_ex5_byp_prod_nz), //i--fnrm + .f_nrm_ex6_res(f_nrm_ex6_res[0:52]), //o--fnrm + .f_nrm_ex6_int_lsbs(f_nrm_ex6_int_lsbs[1:12]), //o--fnrm + .f_nrm_ex6_int_sign(f_nrm_ex6_int_sign), //o--fnrm + .f_nrm_ex6_nrm_sticky_dp(f_nrm_ex6_nrm_sticky_dp), //o--fnrm + .f_nrm_ex6_nrm_guard_dp(f_nrm_ex6_nrm_guard_dp), //o--fnrm + .f_nrm_ex6_nrm_lsb_dp(f_nrm_ex6_nrm_lsb_dp), //o--fnrm + .f_nrm_ex6_nrm_sticky_sp(f_nrm_ex6_nrm_sticky_sp), //o--fnrm + .f_nrm_ex6_nrm_guard_sp(f_nrm_ex6_nrm_guard_sp), //o--fnrm + .f_nrm_ex6_nrm_lsb_sp(f_nrm_ex6_nrm_lsb_sp), //o--fnrm + .f_nrm_ex6_exact_zero(f_nrm_ex6_exact_zero), //o--fnrm + .f_nrm_ex5_extra_shift(f_nrm_ex5_extra_shift), //o--fnrm + .f_nrm_ex6_fpscr_wr_dat_dfp(f_nrm_ex6_fpscr_wr_dat_dfp[0:3]), //o--fnrm + .f_nrm_ex6_fpscr_wr_dat(f_nrm_ex6_fpscr_wr_dat[0:31]) //o--fnrm + ); + //----------------------------------------------------------- fu_nrm.vhdl + + // fu_rnd.vhdl + fu_rnd frnd( + //----------------------------------------------------------- fu_rnd.vhdl + .vdd(vdd), //i-- + .gnd(gnd), //i-- + .nclk(nclk), //i-- + .clkoff_b(clkoff_b), //i-- + .act_dis(act_dis), //i-- + .flush(flush), //i-- + .delay_lclkr(delay_lclkr[5:6]), //i-- + .mpw1_b(mpw1_b[5:6]), //i-- + .mpw2_b(mpw2_b[1:1]), //i-- + .thold_1(perv_rnd_thold_1), //i-- + .sg_1(perv_rnd_sg_1), //i-- + .fpu_enable(perv_rnd_fpu_enable), //i-- + + .f_rnd_si(scan_in[11]), //i--frnd + .f_rnd_so(scan_out[11]), //o--frnd + .ex4_act_b(f_pic_rnd_ex4_act_b), //i--frnd + .f_pic_ex5_sel_est_b(f_pic_ex5_sel_est_b), //i--frnd + .f_tbl_ex6_est_frac(f_tbl_ex6_est_frac[0:26]), //i--frnd + .f_nrm_ex6_res(f_nrm_ex6_res[0:52]), //i--frnd + .f_nrm_ex6_int_lsbs(f_nrm_ex6_int_lsbs[1:12]), //i--frnd + .f_nrm_ex6_int_sign(f_nrm_ex6_int_sign), //i--frnd + .f_nrm_ex6_nrm_sticky_dp(f_nrm_ex6_nrm_sticky_dp), //i--frnd + .f_nrm_ex6_nrm_guard_dp(f_nrm_ex6_nrm_guard_dp), //i--frnd + .f_nrm_ex6_nrm_lsb_dp(f_nrm_ex6_nrm_lsb_dp), //i--frnd + .f_nrm_ex6_nrm_sticky_sp(f_nrm_ex6_nrm_sticky_sp), //i--frnd + .f_nrm_ex6_nrm_guard_sp(f_nrm_ex6_nrm_guard_sp), //i--frnd + .f_nrm_ex6_nrm_lsb_sp(f_nrm_ex6_nrm_lsb_sp), //i--frnd + .f_nrm_ex6_exact_zero(f_nrm_ex6_exact_zero), //i--frnd + .f_pic_ex6_invert_sign(f_pic_ex6_invert_sign), //i--frnd + .f_pic_ex6_en_exact_zero(f_pic_ex6_en_exact_zero), //i--frnd + .f_pic_ex6_k_nan(f_pic_ex6_k_nan), //i--frnd + .f_pic_ex6_k_inf(f_pic_ex6_k_inf), //i--frnd + .f_pic_ex6_k_max(f_pic_ex6_k_max), //i--frnd + .f_pic_ex6_k_zer(f_pic_ex6_k_zer), //i--frnd + .f_pic_ex6_k_one(f_pic_ex6_k_one), //i--frnd + .f_pic_ex6_k_int_maxpos(f_pic_ex6_k_int_maxpos), //i--frnd + .f_pic_ex6_k_int_maxneg(f_pic_ex6_k_int_maxneg), //i--frnd + .f_pic_ex6_k_int_zer(f_pic_ex6_k_int_zer), //i--frnd + .f_tbl_ex6_recip_den(f_tbl_ex6_recip_den), //i--frnd + .f_pic_ex5_rnd_ni_b(f_pic_ex5_rnd_ni_b), //i--frnd + .f_pic_ex5_rnd_nr_b(f_pic_ex5_rnd_nr_b), //i--frnd + .f_pic_ex5_rnd_inf_ok_b(f_pic_ex5_rnd_inf_ok_b), //i--frnd + .f_pic_ex6_uc_inc_lsb(f_pic_ex6_uc_inc_lsb), //i--frnd + .f_pic_ex6_uc_guard(f_pic_ex6_uc_guard), //i--frnd + .f_pic_ex6_uc_sticky(f_pic_ex6_uc_sticky), //i--frnd + .f_pic_ex6_uc_g_v(f_pic_ex6_uc_g_v), //i--frnd + .f_pic_ex6_uc_s_v(f_pic_ex6_uc_s_v), //i--frnd + .f_pic_ex5_sel_fpscr_b(f_pic_ex5_sel_fpscr_b), //i--frnd + .f_pic_ex5_to_integer_b(f_pic_ex5_to_integer_b), //i--frnd + .f_pic_ex5_word_b(f_pic_ex5_word_b), //i--frnd + .f_pic_ex5_uns_b(f_pic_ex5_uns_b), //i--frnd + .f_pic_ex5_sp_b(f_pic_ex5_sp_b), //i--frnd + .f_pic_ex5_spec_inf_b(f_pic_ex5_spec_inf_b), //i--frnd + .f_pic_ex5_quiet_b(f_pic_ex5_quiet_b), //i--frnd + .f_pic_ex5_nj_deno(f_pic_ex5_nj_deno), //i--frnd + .f_pic_ex5_unf_en_ue0_b(f_pic_ex5_unf_en_ue0_b), //i--frnd + .f_pic_ex5_unf_en_ue1_b(f_pic_ex5_unf_en_ue1_b), //i--frnd + .f_pic_ex5_ovf_en_oe0_b(f_pic_ex5_ovf_en_oe0_b), //i--frnd + .f_pic_ex5_ovf_en_oe1_b(f_pic_ex5_ovf_en_oe1_b), //i--frnd + .f_pic_ex6_round_sign(f_pic_ex6_round_sign), //i--frnd + .f_scr_ex6_fpscr_rd_dat_dfp(f_scr_ex6_fpscr_rd_dat_dfp[0:3]), //i--frnd + .f_scr_ex6_fpscr_rd_dat(f_scr_ex6_fpscr_rd_dat[0:31]), //i--frnd + .f_eov_ex6_sel_k_f(f_eov_ex6_sel_k_f), //i--frnd + .f_eov_ex6_sel_k_e(f_eov_ex6_sel_k_e), //i--frnd + .f_eov_ex6_sel_kif_f(f_eov_ex6_sel_kif_f), //i--frnd + .f_eov_ex6_sel_kif_e(f_eov_ex6_sel_kif_e), //i--frnd + .f_eov_ex6_ovf_expo(f_eov_ex6_ovf_expo), //i--frnd + .f_eov_ex6_ovf_if_expo(f_eov_ex6_ovf_if_expo), //i--frnd + .f_eov_ex6_unf_expo(f_eov_ex6_unf_expo), //i--frnd + .f_pic_ex6_frsp(f_pic_ex6_frsp), //i--frnd + .f_eov_ex6_expo_p0(f_eov_ex6_expo_p0[1:13]), //i--frnd + .f_eov_ex6_expo_p1(f_eov_ex6_expo_p1[1:13]), //i--frnd + .f_eov_ex6_expo_p0_ue1oe1(f_eov_ex6_expo_p0_ue1oe1[3:7]), //i--frnd + .f_eov_ex6_expo_p1_ue1oe1(f_eov_ex6_expo_p1_ue1oe1[3:7]), //i--frnd + .f_gst_ex6_logexp_v(f_gst_ex6_logexp_v), //i--frnd + .f_gst_ex6_logexp_sign(f_gst_ex6_logexp_sign), //i--frnd + .f_gst_ex6_logexp_exp(f_gst_ex6_logexp_exp[1:11]), //i--frnd + .f_gst_ex6_logexp_fract(f_gst_ex6_logexp_fract[0:19]), //i--frnd + .f_dsq_ex6_divsqrt_v(f_dsq_ex6_divsqrt_v_int), //i--fdsq -- :out std_ulogic; + + .f_dsq_ex6_divsqrt_sign(f_dsq_ex6_divsqrt_sign), //i--fdsq -- :out std_ulogic; + .f_dsq_ex6_divsqrt_exp(f_dsq_ex6_divsqrt_exp), //i--fdsq -- :out std_ulogic_vector(01 to 13); + .f_dsq_ex6_divsqrt_fract(f_dsq_ex6_divsqrt_fract), //i--fdsq -- :out std_ulogic_vector(00 to 52) + .f_dsq_ex6_divsqrt_flag_fpscr(f_dsq_ex6_divsqrt_flag_fpscr[0:10]), //i--fdsq -- :out std_ulogic_vector(00 to 09) + + .f_mad_ex7_uc_sign(f_mad_ex7_uc_sign), //o--frnd + .f_mad_ex7_uc_zero(f_mad_ex7_uc_zero), //o--frnd + .f_rnd_ex7_res_sign(rnd_ex7_res_sign), //o--frnd + .f_rnd_ex7_res_expo(rnd_ex7_res_expo[1:13]), //o--frnd + .f_rnd_ex7_res_frac(rnd_ex7_res_frac[0:52]), //o--frnd + .f_rnd_ex7_flag_up(f_rnd_ex7_flag_up), //o--frnd + .f_rnd_ex7_flag_fi(f_rnd_ex7_flag_fi), //o--frnd + .f_rnd_ex7_flag_ox(f_rnd_ex7_flag_ox), //o--frnd + .f_rnd_ex7_flag_den(f_rnd_ex7_flag_den), //o--frnd + .f_rnd_ex7_flag_sgn(f_rnd_ex7_flag_sgn), //o--frnd + .f_rnd_ex7_flag_inf(f_rnd_ex7_flag_inf), //o--frnd + .f_rnd_ex7_flag_zer(f_rnd_ex7_flag_zer), //o--frnd + .f_rnd_ex7_flag_ux(f_rnd_ex7_flag_ux) //o--frnd + ); + //----------------------------------------------------------- fu_rnd.vhdl + + assign f_rnd_ex7_res_sign = rnd_ex7_res_sign; + assign f_rnd_ex7_res_expo[1:13] = rnd_ex7_res_expo[1:13]; + assign f_rnd_ex7_res_frac[0:52] = rnd_ex7_res_frac[0:52]; + + // fu_gst.vhdl + fu_gst fgst( + //----------------------------------------------------------- fu_gst.vhdl + .vdd(vdd), //i-- + .gnd(gnd), //i-- + .nclk(nclk), //i-- + .clkoff_b(clkoff_b), //i-- + .act_dis(act_dis), //i-- + .flush(flush), //i-- + .delay_lclkr(delay_lclkr[2:5]), //i-- + .mpw1_b(mpw1_b[2:5]), //i-- + .mpw2_b(mpw2_b[0:1]), //i-- + .thold_1(perv_rnd_thold_1), //i-- + .sg_1(perv_rnd_sg_1), //i-- + .fpu_enable(perv_rnd_fpu_enable), //i-- + + .f_gst_si(scan_in[12]), //i--fgst + .f_gst_so(scan_out[12]), //o--fgst + .ex1_act(f_dcd_ex1_act), //i--fgst (connect) + .f_fmt_ex2_b_sign_gst(f_fmt_ex2_b_sign_gst), //i--fgst + .f_fmt_ex2_b_expo_gst_b(f_fmt_ex2_b_expo_gst_b[1:13]), //i--fgst + .f_fmt_ex2_b_frac_gst(f_fmt_ex2_b_frac[1:19]), //i--fgst + .f_pic_ex2_floges(f_pic_ex2_log2e), //i--fgst + .f_pic_ex2_fexptes(f_pic_ex2_pow2e), //i--fgst + .f_gst_ex6_logexp_v(f_gst_ex6_logexp_v), //o--fgst + .f_gst_ex6_logexp_sign(f_gst_ex6_logexp_sign), //o--fgst + .f_gst_ex6_logexp_exp(f_gst_ex6_logexp_exp[1:11]), //o--fgst + .f_gst_ex6_logexp_fract(f_gst_ex6_logexp_fract[0:19]) //o--fgst + ); + //----------------------------------------------------------- fuq_gst.vhdl + + // fu_divsqrt.vhdl + fu_divsqrt fdsq( + //----------------------------------------------------------- fu_divsqrt.vhdl + .vdd(vdd), //i-- + .gnd(gnd), //i-- + .nclk(nclk), //i-- + .clkoff_b(clkoff_b), //i-- + .act_dis(act_dis), //i-- + .flush(flush), //i-- + .delay_lclkr(delay_lclkr[1]), //i-- + .mpw1_b(mpw1_b[1]), //i-- + .mpw2_b(mpw2_b[0]), //i-- + .thold_1(perv_rnd_thold_1), //i-- + .sg_1(perv_rnd_sg_1), //i-- + .fpu_enable(perv_rnd_fpu_enable), //i-- + + .f_dsq_si(scan_in[13]), //i--fdsq + .f_dsq_so(scan_out[13]), //o--fdsq + .ex0_act_b(tidn), //i--fdsq (connect) + + .f_dcd_ex0_div(f_dcd_ex0_div), //i--fdsq -- :in std_ulogic; + .f_dcd_ex0_divs(f_dcd_ex0_divs), //i--fdsq -- :in std_ulogic; + .f_dcd_ex0_sqrt(f_dcd_ex0_sqrt), //i--fdsq -- :in std_ulogic; + .f_dcd_ex0_sqrts(f_dcd_ex0_sqrts), //i--fdsq -- :in std_ulogic; + .f_dcd_ex0_record_v(f_dcd_ex0_record_v), //i--fdsq -- :in std_ulogic; + + .f_dcd_ex2_divsqrt_hole_v(f_dcd_ex2_divsqrt_hole_v), //i--fdsq + .f_dcd_flush(f_dcd_flush), //i--fdsq -- :in std_ulogic; + .f_dcd_ex1_itag(f_dcd_ex1_itag), //i--fdsq -- :in std_ulogic_vector(0 to 6); + .f_dcd_ex1_fpscr_addr(f_dcd_ex1_fpscr_addr), //i--fdsq -- :in std_ulogic_vector(0 to 5); + .f_dcd_ex1_instr_frt(f_dcd_ex1_instr_frt), //i--fdsq -- :in std_ulogic_vector(0 to 5); + .f_dcd_ex1_instr_tid(f_dcd_ex1_instr_tid), //i--fdsq -- :in std_ulogic_vector(0 to 5); + + .f_dcd_ex1_divsqrt_cr_bf(f_dcd_ex1_divsqrt_cr_bf), //i--fdsq -- :in std_ulogic_vector(0 to 5); + .f_dcd_axucr0_deno(f_dcd_axucr0_deno), + .f_fmt_ex2_a_sign_div(f_fmt_ex2_a_sign_div), //i--fdsq -- :in std_ulogic; + .f_fmt_ex2_a_expo_div_b(f_fmt_ex2_a_expo_div_b), //i--fdsq -- :in std_ulogic_vector(01 to 13); + .f_fmt_ex2_a_frac_div(f_fmt_ex2_a_frac_div), //i--fdsq -- :in std_ulogic_vector(01 to 52); + + .f_fmt_ex2_b_sign_div(f_fmt_ex2_b_sign_div), //i--fdsq -- :in std_ulogic; + .f_fmt_ex2_b_expo_div_b(f_fmt_ex2_b_expo_div_b), //i--fdsq -- :in std_ulogic_vector(01 to 13); + .f_fmt_ex2_b_frac_div(f_fmt_ex2_b_frac_div), //i--fdsq -- :in std_ulogic_vector(01 to 52); + .f_fmt_ex2_a_zero_dsq(f_fmt_ex2_a_zero_dsq), //i--fdsq + .f_fmt_ex2_a_zero(f_fmt_ex2_a_zero), //i--fdsq + + .f_fmt_ex2_a_expo_max(f_fmt_ex2_a_expo_max), //i--fdsq + .f_fmt_ex2_a_expo_max_dsq(f_fmt_ex2_a_expo_max_dsq), //i--fdsq + .f_fmt_ex2_a_frac_zero(f_fmt_ex2_a_frac_zero), //i--fdsq + .f_fmt_ex2_b_zero_dsq(f_fmt_ex2_b_zero_dsq), //i--fdsq + .f_fmt_ex2_b_zero(f_fmt_ex2_b_zero), //i--fdsq + + .f_fmt_ex2_b_expo_max(f_fmt_ex2_b_expo_max), //i--fdsq + .f_fmt_ex2_b_expo_max_dsq(f_fmt_ex2_b_expo_max_dsq), //i--fdsq + .f_fmt_ex2_b_frac_zero(f_fmt_ex2_b_frac_zero), //i--fdsq + .f_dsq_ex3_hangcounter_trigger(f_dsq_ex3_hangcounter_trigger_int), + .f_dsq_ex5_divsqrt_v(f_dsq_ex5_divsqrt_v_int), //o--fdsq -- :out std_ulogic; + .f_dsq_ex6_divsqrt_v(f_dsq_ex6_divsqrt_v_int), //o--fdsq -- :out std_ulogic; + .f_dsq_ex6_divsqrt_record_v(f_dsq_ex6_divsqrt_record_v_int), //o--fdsq -- :out std_ulogic; + + .f_dsq_ex6_divsqrt_v_suppress(f_dsq_ex6_divsqrt_v_int_suppress), //o--fdsq -- :out std_ulogic; + + .f_dsq_ex5_divsqrt_itag(f_dsq_ex5_divsqrt_itag_int), //i--fdsq -- :out std_ulogic; + .f_dsq_ex6_divsqrt_fpscr_addr(f_dsq_ex6_divsqrt_fpscr_addr_int), //i--fdsq -- :out std_ulogic; + .f_dsq_ex6_divsqrt_instr_frt(f_dsq_ex6_divsqrt_instr_frt_int), //i--fdsq -- :out std_ulogic; + .f_dsq_ex6_divsqrt_instr_tid(f_dsq_ex6_divsqrt_instr_tid_int), //i--fdsq -- :out std_ulogic; + + .f_dsq_ex6_divsqrt_cr_bf(f_dsq_ex6_divsqrt_cr_bf_int), //i--fdsq -- :out std_ulogic; + + .f_scr_ex6_fpscr_rm_thr0(f_scr_ex6_fpscr_rm_thr0), //i--fdsq + .f_scr_ex6_fpscr_ee_thr0(f_scr_ex6_fpscr_ee_thr0), //i--fdsq + .f_scr_ex6_fpscr_rm_thr1(f_scr_ex6_fpscr_rm_thr1), //i--fdsq + .f_scr_ex6_fpscr_ee_thr1(f_scr_ex6_fpscr_ee_thr1), //i--fdsq + + .f_dsq_ex6_divsqrt_sign(f_dsq_ex6_divsqrt_sign), //o--fdsq -- :out std_ulogic; + .f_dsq_ex6_divsqrt_exp(f_dsq_ex6_divsqrt_exp), //o--fdsq -- :out std_ulogic_vector(01 to 13); + .f_dsq_ex6_divsqrt_fract(f_dsq_ex6_divsqrt_fract), //o--fdsq -- :out std_ulogic_vector(00 to 52) + .f_dsq_ex6_divsqrt_flag_fpscr(f_dsq_ex6_divsqrt_flag_fpscr),//o--fdsq -- :out std_ulogic_vector(00 to 09) + .f_dsq_debug(f_dsq_debug) + ); + + //----------------------------------------------------------- fu_divsqrt.vhdl + assign f_dsq_ex5_divsqrt_v = f_dsq_ex5_divsqrt_v_int; + assign f_dsq_ex6_divsqrt_v = f_dsq_ex6_divsqrt_v_int; + assign f_dsq_ex6_divsqrt_record_v = f_dsq_ex6_divsqrt_record_v_int; + assign f_dsq_ex6_divsqrt_v_suppress = f_dsq_ex6_divsqrt_v_int_suppress; + assign f_dsq_ex5_divsqrt_itag = f_dsq_ex5_divsqrt_itag_int; + assign f_dsq_ex6_divsqrt_fpscr_addr = f_dsq_ex6_divsqrt_fpscr_addr_int; + assign f_dsq_ex6_divsqrt_instr_frt = f_dsq_ex6_divsqrt_instr_frt_int; + assign f_dsq_ex6_divsqrt_instr_tid = f_dsq_ex6_divsqrt_instr_tid_int; + assign f_dsq_ex3_hangcounter_trigger = f_dsq_ex3_hangcounter_trigger_int; + + assign f_dsq_ex6_divsqrt_cr_bf = f_dsq_ex6_divsqrt_cr_bf_int; + + // fu_pic.vhdl + fu_pic fpic( + //----------------------------------------------------------- fu_pic.vhdl + .vdd(vdd), //i-- + .gnd(gnd), //i-- + .nclk(nclk), //i-- + .clkoff_b(clkoff_b), //i-- + .act_dis(act_dis), //i-- + .flush(flush), //i-- + .delay_lclkr(delay_lclkr[1:5]), //i-- + .mpw1_b(mpw1_b[1:5]), //i-- + .mpw2_b(mpw2_b[0:1]), //i-- + .thold_1(perv_pic_thold_1), //i-- + .sg_1(perv_pic_sg_1), //i-- + .fpu_enable(perv_pic_fpu_enable), //i-- + + .f_pic_si(scan_in[14]), //i--fpic + .f_pic_so(scan_out[14]), //o--fpic + .f_dcd_ex1_act(f_dcd_ex1_act), //i--fpic + .f_cr2_ex2_fpscr_shadow_thr0(f_scr_fpscr_ctrl_thr0), //i--fpic + .f_cr2_ex2_fpscr_shadow_thr1(f_scr_fpscr_ctrl_thr1), //i--fpic + .f_dcd_ex1_pow2e_b(f_dcd_ex1_pow2e_b), //i--fpic + .f_dcd_ex1_log2e_b(f_dcd_ex1_log2e_b), //i--fpic + .f_byp_pic_ex2_a_sign(f_byp_pic_ex2_a_sign), //i--fpic + .f_byp_pic_ex2_c_sign(f_byp_pic_ex2_c_sign), //i--fpic + .f_byp_pic_ex2_b_sign(f_byp_pic_ex2_b_sign), //i--fpic + .f_dcd_ex1_aop_valid(f_dcd_ex1_aop_valid), //i--fpic + .f_dcd_ex1_cop_valid(f_dcd_ex1_cop_valid), //i--fpic + .f_dcd_ex1_bop_valid(f_dcd_ex1_bop_valid), //i--fpic + .f_dcd_ex1_thread(f_dcd_ex1_thread), //i--fpic + + .f_dcd_ex1_uc_ft_neg(f_dcd_ex1_uc_ft_neg), //i--fpic + .f_dcd_ex1_uc_ft_pos(f_dcd_ex1_uc_ft_pos), //i--fpic + .f_dcd_ex1_fsel_b(f_dcd_ex1_fsel_b), //i--fpic + .f_dcd_ex1_from_integer_b(f_dcd_ex1_from_integer_b), //i--fpic + .f_dcd_ex1_to_integer_b(f_dcd_ex1_to_integer_b), //i--fpic + .f_dcd_ex1_rnd_to_int_b(f_dcd_ex1_rnd_to_int_b), //i--fpic + .f_dcd_ex1_math_b(f_dcd_ex1_math_b), //i--fpic + .f_dcd_ex1_est_recip_b(f_dcd_ex1_est_recip_b), //i--fpic + .f_dcd_ex1_ftdiv(f_dcd_ex1_ftdiv), //i--fpic + .f_dcd_ex1_ftsqrt(f_dcd_ex1_ftsqrt), //i--fpic + .f_fmt_ex3_ae_ge_54(f_fmt_ex3_ae_ge_54), //i--fpic + .f_fmt_ex3_be_ge_54(f_fmt_ex3_be_ge_54), //i--fpic + .f_fmt_ex3_be_ge_2(f_fmt_ex3_be_ge_2), //i--fpic + .f_fmt_ex3_be_ge_2044(f_fmt_ex3_be_ge_2044), //i--fpic + .f_fmt_ex3_tdiv_rng_chk(f_fmt_ex3_tdiv_rng_chk), //i--fpic + + .f_dcd_ex1_est_rsqrt_b(f_dcd_ex1_est_rsqrt_b), //i--fpic + .f_dcd_ex1_move_b(f_dcd_ex1_move_b), //i--fpic + .f_dcd_ex1_prenorm_b(f_dcd_ex1_prenorm_b), //i--fpic + .f_dcd_ex1_frsp_b(f_dcd_ex1_frsp_b), //i--fpic + .f_dcd_ex1_sp(f_dcd_ex1_sp), //i--fpic + .f_dcd_ex1_sp_conv_b(f_dcd_ex1_sp_conv_b), //i--fpic + .f_dcd_ex1_word_b(f_dcd_ex1_word_b), //i--fpic + .f_dcd_ex1_uns_b(f_dcd_ex1_uns_b), //i--fpic + .f_dcd_ex1_sub_op_b(f_dcd_ex1_sub_op_b), //i--fpic + .f_dcd_ex1_op_rnd_v_b(f_dcd_ex1_op_rnd_v_b), //i--fpic + .f_dcd_ex1_op_rnd_b(f_dcd_ex1_op_rnd_b[0:1]), //i--fpic + .f_dcd_ex1_inv_sign_b(f_dcd_ex1_inv_sign_b), //i--fpic + .f_dcd_ex1_sign_ctl_b(f_dcd_ex1_sign_ctl_b[0:1]), //i--fpic + .f_dcd_ex1_sgncpy_b(f_dcd_ex1_sgncpy_b), //i--fpic + .f_dcd_ex1_nj_deno(f_dcd_ex1_nj_deno), //i--fpic + .f_dcd_ex1_mv_to_scr_b(f_dcd_ex1_mv_to_scr_b), //i--fpic + .f_dcd_ex1_mv_from_scr_b(f_dcd_ex1_mv_from_scr_b), //i--fpic + .f_dcd_ex1_compare_b(f_dcd_ex1_compare_b), //i--fpic + .f_dcd_ex1_ordered_b(f_dcd_ex1_ordered_b), //i--fpic + .f_alg_ex2_sign_frmw(f_alg_ex2_sign_frmw), //i--fpic + .f_dcd_ex1_force_excp_dis(f_dcd_ex1_force_excp_dis), //i--fpic + .f_pic_ex2_log2e(f_pic_ex2_log2e), //i--fpic + .f_pic_ex2_pow2e(f_pic_ex2_pow2e), //i--fpic + .f_fmt_ex2_bexpu_le126(f_fmt_ex2_bexpu_le126), //i--fpic + .f_fmt_ex2_gt126(f_fmt_ex2_gt126), //i--fpic + .f_fmt_ex2_ge128(f_fmt_ex2_ge128), //i--fpic + .f_fmt_ex2_inf_and_beyond_sp(f_fmt_ex2_inf_and_beyond_sp), //i--fpic + .f_fmt_ex2_sp_invalid(f_fmt_ex2_sp_invalid), //i--fpic + .f_fmt_ex2_a_zero(f_fmt_ex2_a_zero), //i--fpic + .f_fmt_ex2_a_expo_max(f_fmt_ex2_a_expo_max), //i--fpic + .f_fmt_ex2_a_frac_zero(f_fmt_ex2_a_frac_zero), //i--fpic + .f_fmt_ex2_a_frac_msb(f_fmt_ex2_a_frac_msb), //i--fpic + .f_fmt_ex2_c_zero(f_fmt_ex2_c_zero), //i--fpic + .f_fmt_ex2_c_expo_max(f_fmt_ex2_c_expo_max), //i--fpic + .f_fmt_ex2_c_frac_zero(f_fmt_ex2_c_frac_zero), //i--fpic + .f_fmt_ex2_c_frac_msb(f_fmt_ex2_c_frac_msb), //i--fpic + .f_fmt_ex2_b_zero(f_fmt_ex2_b_zero), //i--fpic + .f_fmt_ex2_b_expo_max(f_fmt_ex2_b_expo_max), //i--fpic + .f_fmt_ex2_b_frac_zero(f_fmt_ex2_b_frac_zero), //i--fpic + .f_fmt_ex2_b_frac_msb(f_fmt_ex2_b_frac_msb), //i--fpic + .f_fmt_ex2_prod_zero(f_fmt_ex2_prod_zero), //i--fpic + .f_fmt_ex3_pass_sign(f_fmt_ex3_pass_sign), //i--fpic + .f_fmt_ex3_pass_msb(f_fmt_ex3_pass_msb), //i--fpic + .f_fmt_ex2_b_frac_z32(f_fmt_ex2_b_frac_z32), //i--fpic + .f_fmt_ex2_b_imp(f_fmt_ex2_b_imp), //i--fpic + .f_eie_ex3_wd_ov(f_eie_ex3_wd_ov), //i--fpic + .f_eie_ex3_dw_ov(f_eie_ex3_dw_ov), //i--fpic + .f_eie_ex3_wd_ov_if(f_eie_ex3_wd_ov_if), //i--fpic + .f_eie_ex3_dw_ov_if(f_eie_ex3_dw_ov_if), //i--fpic + .f_eie_ex3_lt_bias(f_eie_ex3_lt_bias), //i--fpic + .f_eie_ex3_eq_bias_m1(f_eie_ex3_eq_bias_m1), //i--fpic + .f_alg_ex3_sel_byp(f_alg_ex3_sel_byp), //i--fpic + .f_alg_ex3_effsub_eac_b(f_alg_ex3_effsub_eac_b), //i--fpic + .f_alg_ex3_sh_unf(f_alg_ex3_sh_unf), //i--fpic + .f_alg_ex3_sh_ovf(f_alg_ex3_sh_ovf), //i--fpic + .f_alg_ex4_int_fr(f_alg_ex4_int_fr), //i--fpic + .f_alg_ex4_int_fi(f_alg_ex4_int_fi), //i--fpic + .f_eov_ex5_may_ovf(f_eov_ex5_may_ovf), //i--fpic + .f_add_ex5_fpcc_iu({f_add_ex5_flag_lt, f_add_ex5_flag_gt, f_add_ex5_flag_eq, f_add_ex5_flag_nan}), //o--fadd + .f_add_ex5_sign_carry(f_add_ex5_sign_carry), //i--fpic + .f_dcd_ex1_div_beg(tidn), //i--fpic + .f_dcd_ex1_sqrt_beg(tidn), //i--fpic + .f_pic_ex6_fpr_wr_dis_b(f_pic_ex6_fpr_wr_dis_b), //o--fpic + .f_add_ex5_to_int_ovf_wd(f_add_ex5_to_int_ovf_wd[0:1]), //i--fpic + .f_add_ex5_to_int_ovf_dw(f_add_ex5_to_int_ovf_dw[0:1]), //i--fpic + .f_pic_ex2_flush_en_sp(f_pic_ex2_flush_en_sp), //o--fpic + .f_pic_ex2_flush_en_dp(f_pic_ex2_flush_en_dp), //o--fpic + .f_pic_ex2_rnd_to_int(f_pic_ex2_rnd_to_int), //o--fpic + + + .f_fmt_ex3_be_den (f_fmt_ex3_be_den) , //i--ffmt + .f_pic_fmt_ex2_act(f_pic_fmt_ex2_act), //o--fpic + .f_pic_eie_ex2_act(f_pic_eie_ex2_act), //o--fpic + .f_pic_mul_ex2_act(f_pic_mul_ex2_act), //o--fpic + .f_pic_alg_ex2_act(f_pic_alg_ex2_act), //o--fpic + .f_pic_cr2_ex2_act(f_pic_cr2_ex2_act), //o--fpic + .f_pic_tbl_ex2_act(f_pic_tbl_ex2_act), //o--fpic + .f_pic_ex2_ftdiv (f_pic_ex2_ftdiv ), //o--fpic to fmt + + + .f_pic_add_ex2_act_b(f_pic_add_ex2_act_b), //o--fpic + .f_pic_lza_ex2_act_b(f_pic_lza_ex2_act_b), //o--fpic + .f_pic_eov_ex3_act_b(f_pic_eov_ex3_act_b), //o--fpic + .f_pic_nrm_ex4_act_b(f_pic_nrm_ex4_act_b), //o--fpic + .f_pic_rnd_ex4_act_b(f_pic_rnd_ex4_act_b), //o--fpic + .f_pic_scr_ex3_act_b(f_pic_scr_ex3_act_b), //o--fpic + .f_pic_ex2_effsub_raw(f_pic_ex2_effsub_raw), //o--fpic + .f_pic_ex4_sel_est(f_pic_ex4_sel_est), //o--fpic + .f_pic_ex2_from_integer(f_pic_ex2_from_integer), //o--fpic + .f_pic_ex3_ue1(f_pic_ex3_ue1), //o--fpic + .f_pic_ex3_frsp_ue1(f_pic_ex3_frsp_ue1), //o--fpic + .f_pic_ex2_frsp_ue1(f_pic_ex2_frsp_ue1), //o--fpic --wrong cycle (temporary) + .f_pic_ex2_fsel(f_pic_ex2_fsel), //o--fpic + .f_pic_ex2_sh_ovf_do(f_pic_ex2_sh_ovf_do), //o--fpic + .f_pic_ex2_sh_ovf_ig_b(f_pic_ex2_sh_ovf_ig_b), //o--fpic + .f_pic_ex2_sh_unf_do(f_pic_ex2_sh_unf_do), //o--fpic + .f_pic_ex2_sh_unf_ig_b(f_pic_ex2_sh_unf_ig_b), //o--fpic + .f_pic_ex3_est_recip(f_pic_ex3_est_recip), //o--fpic + .f_pic_ex3_est_rsqrt(f_pic_ex3_est_rsqrt), //o--fpic + .f_pic_ex3_force_sel_bexp(f_pic_ex3_force_sel_bexp), //o--fpic + .f_pic_ex3_lzo_dis_prod(f_pic_ex3_lzo_dis_prod), //o--fpic + .f_pic_ex3_sp_b(f_pic_ex3_sp_b), //o--fpic + .f_pic_ex3_sp_lzo(f_pic_ex3_sp_lzo), //o--fpic + .f_pic_ex3_to_integer(f_pic_ex3_to_integer), //o--fpic + .f_pic_ex3_prenorm(f_pic_ex3_prenorm), //o--fpic + .f_pic_ex3_b_valid(f_pic_ex3_b_valid), //i--fpic + .f_pic_ex3_rnd_nr(f_pic_ex3_rnd_nr), //i--falg + .f_pic_ex3_rnd_inf_ok(f_pic_ex3_rnd_inf_ok), //i--falg + .f_pic_ex3_math_bzer_b(f_pic_ex3_math_bzer_b), //o--fpic + .f_pic_ex4_cmp_sgnneg(f_pic_ex4_cmp_sgnneg), //o--fpic + .f_pic_ex4_cmp_sgnpos(f_pic_ex4_cmp_sgnpos), //o--fpic + .f_pic_ex4_is_eq(f_pic_ex4_is_eq), //o--fpic + .f_pic_ex4_is_gt(f_pic_ex4_is_gt), //o--fpic + .f_pic_ex4_is_lt(f_pic_ex4_is_lt), //o--fpic + .f_pic_ex4_is_nan(f_pic_ex4_is_nan), //o--fpic + .f_pic_ex4_sp_b(f_pic_ex4_sp_b), //o--fpic + .f_dcd_ex1_uc_mid(f_dcd_ex1_uc_mid), //i--fpic + .f_dcd_ex1_uc_end(f_dcd_ex1_uc_end), //i--fpic + .f_dcd_ex1_uc_special(f_dcd_ex1_uc_special), //i--fpic + .f_mad_ex3_uc_a_expo_den_sp(f_mad_ex3_uc_a_expo_den_sp), //i--fpic + .f_mad_ex3_uc_a_expo_den(f_mad_ex3_uc_a_expo_den), //i--fpic + .f_dcd_ex3_uc_zx(f_dcd_ex3_uc_zx), //i--fpic + .f_dcd_ex3_uc_vxidi(f_dcd_ex3_uc_vxidi), //i--fpic + .f_dcd_ex3_uc_vxzdz(f_dcd_ex3_uc_vxzdz), //i--fpic + .f_dcd_ex3_uc_vxsqrt(f_dcd_ex3_uc_vxsqrt), //i--fpic + .f_dcd_ex3_uc_vxsnan(f_dcd_ex3_uc_vxsnan), //i--fpic + .f_mad_ex4_uc_special(f_mad_ex4_uc_special), //o--fpic + .f_mad_ex4_uc_zx(f_mad_ex4_uc_zx), //o--fpic + .f_mad_ex4_uc_vxidi(f_mad_ex4_uc_vxidi), //o--fpic + .f_mad_ex4_uc_vxzdz(f_mad_ex4_uc_vxzdz), //o--fpic + .f_mad_ex4_uc_vxsqrt(f_mad_ex4_uc_vxsqrt), //o--fpic + .f_mad_ex4_uc_vxsnan(f_mad_ex4_uc_vxsnan), //o--fpic + .f_mad_ex4_uc_res_sign(f_mad_ex4_uc_res_sign), //o--fpic + .f_mad_ex4_uc_round_mode(f_mad_ex4_uc_round_mode[0:1]), //o--fpic + .f_pic_ex5_byp_prod_nz(f_pic_ex5_byp_prod_nz), //o--fpic + .f_pic_ex5_sel_est_b(f_pic_ex5_sel_est_b), //o--fpic + .f_pic_ex5_nj_deno(f_pic_ex5_nj_deno), //o--fpic + .f_pic_ex5_oe(f_pic_ex5_oe), //o--fpic + .f_pic_ex5_ov_en(f_pic_ex5_ov_en), //o--fpic + .f_pic_ex5_ovf_en_oe0_b(f_pic_ex5_ovf_en_oe0_b), //o--fpic + .f_pic_ex5_ovf_en_oe1_b(f_pic_ex5_ovf_en_oe1_b), //o--fpic + .f_pic_ex5_quiet_b(f_pic_ex5_quiet_b), //o--fpic + .f_pic_ex5_rnd_inf_ok_b(f_pic_ex5_rnd_inf_ok_b), //o--fpic + .f_pic_ex5_rnd_ni_b(f_pic_ex5_rnd_ni_b), //o--fpic + .f_pic_ex5_rnd_nr_b(f_pic_ex5_rnd_nr_b), //o--fpic + .f_pic_ex5_sel_fpscr_b(f_pic_ex5_sel_fpscr_b), //o--fpic + .f_pic_ex5_sp_b(f_pic_ex5_sp_b), //o--fpic + .f_pic_ex5_spec_inf_b(f_pic_ex5_spec_inf_b), //o--fpic + .f_pic_ex5_spec_sel_k_e(f_pic_ex5_spec_sel_k_e), //o--fpic + .f_pic_ex5_spec_sel_k_f(f_pic_ex5_spec_sel_k_f), //o--fpic + .f_dcd_ex3_uc_inc_lsb(f_dcd_ex3_uc_inc_lsb), //i--fpic + .f_dcd_ex3_uc_guard(f_dcd_ex3_uc_gs[0]), //i--fpic + .f_dcd_ex3_uc_sticky(f_dcd_ex3_uc_gs[1]), //i--fpic + .f_dcd_ex3_uc_gs_v(f_dcd_ex3_uc_gs_v), //i--fpic + .f_pic_ex6_uc_inc_lsb(f_pic_ex6_uc_inc_lsb), //o--fpic + .f_pic_ex6_uc_guard(f_pic_ex6_uc_guard), //o--fpic + .f_pic_ex6_uc_sticky(f_pic_ex6_uc_sticky), //o--fpic + .f_pic_ex6_uc_g_v(f_pic_ex6_uc_g_v), //o--fpic + .f_pic_ex6_uc_s_v(f_pic_ex6_uc_s_v), //o--fpic + .f_pic_ex5_to_int_ov_all(f_pic_ex5_to_int_ov_all), //o--fpic + .f_pic_ex5_to_integer_b(f_pic_ex5_to_integer_b), //o--fpic + .f_pic_ex5_word_b(f_pic_ex5_word_b), //o--fpic + .f_pic_ex5_uns_b(f_pic_ex5_uns_b), //o--fpic + .f_pic_ex5_ue(f_pic_ex5_ue), //o--fpic + .f_pic_ex5_uf_en(f_pic_ex5_uf_en), //o--fpic + .f_pic_ex5_unf_en_ue0_b(f_pic_ex5_unf_en_ue0_b), //o--fpic + .f_pic_ex5_unf_en_ue1_b(f_pic_ex5_unf_en_ue1_b), //o--fpic + .f_pic_ex6_en_exact_zero(f_pic_ex6_en_exact_zero), //o--fpic + .f_pic_ex6_compare_b(f_pic_ex6_compare_b), //o--fpic + .f_pic_ex6_frsp(f_pic_ex6_frsp), //o--fpic + .f_pic_ex6_fi_pipe_v_b(f_pic_ex6_fi_pipe_v_b), //o--fpic + .f_pic_ex6_fi_spec_b(f_pic_ex6_fi_spec_b), //o--fpic + .f_pic_ex6_flag_vxcvi_b(f_pic_ex6_flag_vxcvi_b), //o--fpic + .f_pic_ex6_flag_vxidi_b(f_pic_ex6_flag_vxidi_b), //o--fpic + .f_pic_ex6_flag_vximz_b(f_pic_ex6_flag_vximz_b), //o--fpic + .f_pic_ex6_flag_vxisi_b(f_pic_ex6_flag_vxisi_b), //o--fpic + .f_pic_ex6_flag_vxsnan_b(f_pic_ex6_flag_vxsnan_b), //o--fpic + .f_pic_ex6_flag_vxsqrt_b(f_pic_ex6_flag_vxsqrt_b), //o--fpic + .f_pic_ex6_flag_vxvc_b(f_pic_ex6_flag_vxvc_b), //o--fpic + .f_pic_ex6_flag_vxzdz_b(f_pic_ex6_flag_vxzdz_b), //o--fpic + .f_pic_ex6_flag_zx_b(f_pic_ex6_flag_zx_b), //o--fpic + .f_pic_ex6_fprf_hold_b(f_pic_ex6_fprf_hold_b), //o--fpic + .f_pic_ex6_fprf_pipe_v_b(f_pic_ex6_fprf_pipe_v_b), //o--fpic + .f_pic_ex6_fprf_spec_b(f_pic_ex6_fprf_spec_b[0:4]), //o--fpic + .f_pic_ex6_fr_pipe_v_b(f_pic_ex6_fr_pipe_v_b), //o--fpic + .f_pic_ex6_fr_spec_b(f_pic_ex6_fr_spec_b), //o--fpic + .f_pic_ex6_invert_sign(f_pic_ex6_invert_sign), //o--fpic + .f_pic_ex6_k_nan(f_pic_ex6_k_nan), //o--fpic + .f_pic_ex6_k_inf(f_pic_ex6_k_inf), //o--fpic + .f_pic_ex6_k_max(f_pic_ex6_k_max), //o--fpic + .f_pic_ex6_k_zer(f_pic_ex6_k_zer), //o--fpic + .f_pic_ex6_k_one(f_pic_ex6_k_one), //o--fpic + .f_pic_ex6_k_int_maxpos(f_pic_ex6_k_int_maxpos), //o--fpic + .f_pic_ex6_k_int_maxneg(f_pic_ex6_k_int_maxneg), //o--fpic + .f_pic_ex6_k_int_zer(f_pic_ex6_k_int_zer), //o--fpic + .f_pic_ex6_ox_pipe_v_b(f_pic_ex6_ox_pipe_v_b), //o--fpic + .f_pic_ex6_round_sign(f_pic_ex6_round_sign), //o--fpic + .f_pic_ex6_scr_upd_move_b(f_pic_ex6_scr_upd_move_b_int), //o--fpic + .f_pic_ex6_scr_upd_pipe_b(f_pic_ex6_scr_upd_pipe_b), //o--fpic + .f_pic_ex2_nj_deni(f_pic_ex2_nj_deni), //o--fpic + .f_dcd_ex1_nj_deni(f_dcd_ex1_nj_deni), //i--fpic + .f_pic_ex6_ux_pipe_v_b(f_pic_ex6_ux_pipe_v_b) //o--fpic + ); + //----------------------------------------------------------- fu_pic.vhdl + + assign f_pic_ex6_scr_upd_move_b = f_pic_ex6_scr_upd_move_b_int; + + // fu_cr2.vhdl + fu_cr2 fcr2( + //----------------------------------------------------------- fu_cr2.vhdl + .vdd(vdd), //i-- + .gnd(gnd), //i-- + .nclk(nclk), //i-- + .clkoff_b(clkoff_b), //i-- + .act_dis(act_dis), //i-- + .flush(flush), //i-- + .delay_lclkr(delay_lclkr[1:7]), //i-- + .mpw1_b(mpw1_b[1:7]), //i-- + .mpw2_b(mpw2_b[0:1]), //i-- + .thold_1(perv_cr2_thold_1), //i-- + .sg_1(perv_cr2_sg_1), //i-- + .fpu_enable(perv_cr2_fpu_enable), //i-- + + .f_cr2_si(scan_in[15]), //i--fcr2 + .f_cr2_so(scan_out[15]), //o--fcr2 + .ex1_act(f_dcd_ex1_act), //i--fcr2 + .ex2_act(f_pic_cr2_ex2_act), //i--fcr2 + .ex1_thread_b(ex1_thread_b[0:3]), //i--fcr2 + .f_dcd_ex7_cancel(f_dcd_ex7_cancel), //i--fcr2 + .f_fmt_ex2_bop_byt(f_fmt_ex2_bop_byt[45:52]), //i--fcr2 for mtfsf to shadow reg + .f_dcd_ex1_fpscr_bit_data_b(f_dcd_ex1_fpscr_bit_data_b[0:3]), //i--fcr2 data to write to nibble (other than mtfsf) + .f_dcd_ex1_fpscr_bit_mask_b(f_dcd_ex1_fpscr_bit_mask_b[0:3]), //i--fcr2 enable update of bit within the nibble + .f_dcd_ex1_fpscr_nib_mask_b(f_dcd_ex1_fpscr_nib_mask_b[0:8]), //i--fcr2 enable update of this nibble + .f_dcd_ex1_mtfsbx_b(f_dcd_ex1_mtfsbx_b), //i--fcr2 fpscr set bit, reset bit + .f_dcd_ex1_mcrfs_b(f_dcd_ex1_mcrfs_b), //i--fcr2 move fpscr field to cr and reset exceptions + .f_dcd_ex1_mtfsf_b(f_dcd_ex1_mtfsf_b), //i--fcr2 move fpr data to fpscr + .f_dcd_ex1_mtfsfi_b(f_dcd_ex1_mtfsfi_b), //i--fcr2 move immediate data to fpscr + .f_cr2_ex4_thread_b(f_cr2_ex4_thread_b[0:3]), //o--fcr2 + .f_cr2_ex4_fpscr_bit_data_b(f_cr2_ex4_fpscr_bit_data_b[0:3]), //o--fcr2 data to write to nibble (other than mtfsf) + .f_cr2_ex4_fpscr_bit_mask_b(f_cr2_ex4_fpscr_bit_mask_b[0:3]), //o--fcr2 enable update of bit within the nibble + .f_cr2_ex4_fpscr_nib_mask_b(f_cr2_ex4_fpscr_nib_mask_b[0:8]), //o--fcr2 enable update of this nibble + .f_cr2_ex4_mtfsbx_b(f_cr2_ex4_mtfsbx_b), //o--fcr2 fpscr set bit, reset bit + .f_cr2_ex4_mcrfs_b(f_cr2_ex4_mcrfs_b), //o--fcr2 move fpscr field to cr and reset exceptions + .f_cr2_ex4_mtfsf_b(f_cr2_ex4_mtfsf_b), //o--fcr2 move fpr data to fpscr + .f_cr2_ex4_mtfsfi_b(f_cr2_ex4_mtfsfi_b), //o--fcr2 move immediate data to fpscr + .f_cr2_ex6_fpscr_rd_dat(f_cr2_ex6_fpscr_rd_dat[24:31]), //o--fcr2 + .f_cr2_ex7_fpscr_rd_dat(f_cr2_ex7_fpscr_rd_dat[24:31]) //o--fcr2 + ); + //f_cr2_ex1_fpscr_shadow(0 to 7) => f_cr2_ex1_fpscr_shadow(0 to 7) );--o--fcr2 + //----------------------------------------------------------- fu_cr2.vhdl + + assign f_cr2_ex2_fpscr_shadow[0:7] = f_scr_ex6_fpscr_rd_dat[24:31]; // no forwarding + + + fu_oscr #( .THREADS(THREADS)) fscr( + //----------------------------------------------------------- fuq_scr.vhdl + .vdd(vdd), //i-- + .gnd(gnd), //i-- + .nclk(nclk), //i-- + .clkoff_b(clkoff_b), //i-- + .act_dis(act_dis), //i-- + .flush(flush), //i-- + .delay_lclkr(delay_lclkr[4:7]), //i-- + .mpw1_b(mpw1_b[4:7]), //i-- + .mpw2_b(mpw2_b[0:1]), //i-- + .thold_1(perv_scr_thold_1), //i-- + .sg_1(perv_scr_sg_1), //i-- + .fpu_enable(perv_scr_fpu_enable), //i-- + + .f_scr_si(scan_in[16]), //i--fscr + .f_scr_so(scan_out[16]), //o--fscr + .ex3_act_b(f_pic_scr_ex3_act_b), //i--fscr + .f_cr2_ex4_thread_b(f_cr2_ex4_thread_b[0:3]), //i--fscr + + .f_dcd_ex7_cancel(f_dcd_ex7_cancel), //i--fcr2 + + .f_pic_ex6_scr_upd_move_b(f_pic_ex6_scr_upd_move_b_int), //i--fscr + .f_pic_ex6_scr_upd_pipe_b(f_pic_ex6_scr_upd_pipe_b), //i--fscr + .f_pic_ex6_fprf_spec_b(f_pic_ex6_fprf_spec_b[0:4]), //i--fscr + .f_pic_ex6_compare_b(f_pic_ex6_compare_b), //i--fscr + .f_pic_ex6_fprf_pipe_v_b(f_pic_ex6_fprf_pipe_v_b), //i--fscr + .f_pic_ex6_fprf_hold_b(f_pic_ex6_fprf_hold_b), //i--fscr + .f_pic_ex6_fi_spec_b(f_pic_ex6_fi_spec_b), //i--fscr + .f_pic_ex6_fi_pipe_v_b(f_pic_ex6_fi_pipe_v_b), //i--fscr + .f_pic_ex6_fr_spec_b(f_pic_ex6_fr_spec_b), //i--fscr + .f_pic_ex6_fr_pipe_v_b(f_pic_ex6_fr_pipe_v_b), //i--fscr + .f_pic_ex6_ox_spec_b(tiup), //i--fscr + .f_pic_ex6_ox_pipe_v_b(f_pic_ex6_ox_pipe_v_b), //i--fscr + .f_pic_ex6_ux_spec_b(tiup), //i--fscr + .f_pic_ex6_ux_pipe_v_b(f_pic_ex6_ux_pipe_v_b), //i--fscr + .f_pic_ex6_flag_vxsnan_b(f_pic_ex6_flag_vxsnan_b), //i--fscr + .f_pic_ex6_flag_vxisi_b(f_pic_ex6_flag_vxisi_b), //i--fscr + .f_pic_ex6_flag_vxidi_b(f_pic_ex6_flag_vxidi_b), //i--fscr + .f_pic_ex6_flag_vxzdz_b(f_pic_ex6_flag_vxzdz_b), //i--fscr + .f_pic_ex6_flag_vximz_b(f_pic_ex6_flag_vximz_b), //i--fscr + .f_pic_ex6_flag_vxvc_b(f_pic_ex6_flag_vxvc_b), //i--fscr + .f_pic_ex6_flag_vxsqrt_b(f_pic_ex6_flag_vxsqrt_b), //i--fscr + .f_pic_ex6_flag_vxcvi_b(f_pic_ex6_flag_vxcvi_b), //i--fscr + .f_pic_ex6_flag_zx_b(f_pic_ex6_flag_zx_b), //i--fscr + .f_nrm_ex6_fpscr_wr_dat_dfp(f_nrm_ex6_fpscr_wr_dat_dfp[0:3]), //i--fscr + .f_nrm_ex6_fpscr_wr_dat(f_nrm_ex6_fpscr_wr_dat[0:31]), //i--fscr + .f_cr2_ex4_fpscr_bit_data_b(f_cr2_ex4_fpscr_bit_data_b[0:3]), //o--fscr data to write to nibble (other than mtfsf) + .f_cr2_ex4_fpscr_bit_mask_b(f_cr2_ex4_fpscr_bit_mask_b[0:3]), //o--fscr enable update of bit within the nibble + .f_cr2_ex4_fpscr_nib_mask_b(f_cr2_ex4_fpscr_nib_mask_b[0:8]), //o--fscr enable update of this nibble + .f_cr2_ex4_mtfsbx_b(f_cr2_ex4_mtfsbx_b), //o--fscr fpscr set bit, reset bit + .f_cr2_ex4_mcrfs_b(f_cr2_ex4_mcrfs_b), //o--fscr move fpscr field to cr and reset exceptions + .f_cr2_ex4_mtfsf_b(f_cr2_ex4_mtfsf_b), //o--fscr move fpr data to fpscr + .f_cr2_ex4_mtfsfi_b(f_cr2_ex4_mtfsfi_b), //o--fscr move immediate data to fpscr + .f_dsq_ex6_divsqrt_v(f_dsq_ex6_divsqrt_v_int), //i--fdsq -- :in std_ulogic; + .f_dsq_ex6_divsqrt_v_suppress(f_dsq_ex6_divsqrt_v_int_suppress), //i--fdsq -- :in std_ulogic; + + .f_dsq_ex6_divsqrt_flag_fpscr_zx(f_dsq_ex6_divsqrt_flag_fpscr[2]), //i--fdsq + .f_dsq_ex6_divsqrt_flag_fpscr_idi(f_dsq_ex6_divsqrt_flag_fpscr[11]), //i--fdsq + .f_dsq_ex6_divsqrt_flag_fpscr_zdz(f_dsq_ex6_divsqrt_flag_fpscr[12]), //i--fdsq + .f_dsq_ex6_divsqrt_flag_fpscr_sqrt(f_dsq_ex6_divsqrt_flag_fpscr[13]), //i--fdsq + .f_dsq_ex6_divsqrt_flag_fpscr_nan(f_dsq_ex6_divsqrt_flag_fpscr[14]), //i--fdsq + .f_dsq_ex6_divsqrt_flag_fpscr_snan(f_dsq_ex6_divsqrt_flag_fpscr[15]), //i--fdsq + + .f_rnd_ex7_flag_up(f_rnd_ex7_flag_up), //i--fscr + .f_rnd_ex7_flag_fi(f_rnd_ex7_flag_fi), //i--fscr + .f_rnd_ex7_flag_ox(f_rnd_ex7_flag_ox), //i--fscr + .f_rnd_ex7_flag_den(f_rnd_ex7_flag_den), //i--fscr + .f_rnd_ex7_flag_sgn(f_rnd_ex7_flag_sgn), //i--fscr + .f_rnd_ex7_flag_inf(f_rnd_ex7_flag_inf), //i--fscr + .f_rnd_ex7_flag_zer(f_rnd_ex7_flag_zer), //i--fscr + .f_rnd_ex7_flag_ux(f_rnd_ex7_flag_ux), //i--fscr + .f_cr2_ex7_fpscr_rd_dat(f_cr2_ex7_fpscr_rd_dat[24:31]), //i--fscr + .f_cr2_ex6_fpscr_rd_dat(f_cr2_ex6_fpscr_rd_dat[24:31]), //i--fscr + .f_dcd_ex7_fpscr_wr(f_dcd_ex7_fpscr_wr), //i--fscr + .f_dcd_ex7_fpscr_addr(f_dcd_ex7_fpscr_addr), //i--fscr + .cp_axu_i0_t1_v(cp_axu_i0_t1_v), + .cp_axu_i0_t0_t1_t(cp_axu_i0_t0_t1_t), + .cp_axu_i0_t1_t1_t(cp_axu_i0_t1_t1_t), + .cp_axu_i0_t0_t1_p(cp_axu_i0_t0_t1_p), + .cp_axu_i0_t1_t1_p(cp_axu_i0_t1_t1_p), + // + .cp_axu_i1_t1_v(cp_axu_i1_t1_v), + .cp_axu_i1_t0_t1_t(cp_axu_i1_t0_t1_t), + .cp_axu_i1_t1_t1_t(cp_axu_i1_t1_t1_t), + .cp_axu_i1_t0_t1_p(cp_axu_i1_t0_t1_p), + .cp_axu_i1_t1_t1_p(cp_axu_i1_t1_t1_p), + + .f_scr_ex6_fpscr_rd_dat(f_scr_ex6_fpscr_rd_dat[0:31]), //o--fscr + .f_scr_fpscr_ctrl_thr0(f_scr_fpscr_ctrl_thr0), + .f_scr_fpscr_ctrl_thr1(f_scr_fpscr_ctrl_thr1), + .f_scr_ex6_fpscr_rd_dat_dfp(f_scr_ex6_fpscr_rd_dat_dfp[0:3]), //o--fscr + .f_scr_ex6_fpscr_rm_thr0(f_scr_ex6_fpscr_rm_thr0), //o--fscr + .f_scr_ex6_fpscr_ee_thr0(f_scr_ex6_fpscr_ee_thr0), //o--fscr + .f_scr_ex6_fpscr_ni_thr0(f_scr_ex6_fpscr_ni_thr0_int), //o--fscr + + .f_scr_ex6_fpscr_rm_thr1(f_scr_ex6_fpscr_rm_thr1), //o--fscr + .f_scr_ex6_fpscr_ee_thr1(f_scr_ex6_fpscr_ee_thr1), //o--fscr + .f_scr_ex6_fpscr_ni_thr1(f_scr_ex6_fpscr_ni_thr1_int), //o--fscr + + .f_scr_ex8_cr_fld(f_scr_ex8_cr_fld[0:3]), //o--fscr + .f_scr_ex8_fx_thread0(f_scr_ex8_fx_thread0[0:3]), //o--fscr --UNUSED ?? + .f_scr_ex8_fx_thread1(f_scr_ex8_fx_thread1[0:3]), //o--fscr --UNUSED ?? + .f_scr_cpl_fx_thread0(f_scr_cpl_fx_thread0[0:3]), //o--fscr --UNUSED ?? + .f_scr_cpl_fx_thread1(f_scr_cpl_fx_thread1[0:3]) //o--fscr --UNUSED ?? + ); + //----------------------------------------------------------- fuq_scr.vhdl + + assign f_scr_ex6_fpscr_ni_thr0 = f_scr_ex6_fpscr_ni_thr0_int; + assign f_scr_ex6_fpscr_ni_thr1 = f_scr_ex6_fpscr_ni_thr1_int; + + + // exponent for table lookups + fu_tblexp ftbe( + //----------------------------------------------------------- fuq_tblexp.vhdl + .vdd(vdd), //i-- + .gnd(gnd), //i-- + .nclk(nclk), //i-- + .clkoff_b(clkoff_b), //i-- + .act_dis(act_dis), //i-- + .flush(flush), //i-- + .delay_lclkr(delay_lclkr[2:3]), //i-- + .mpw1_b(mpw1_b[2:3]), //i-- + .mpw2_b(mpw2_b[0:0]), //i-- + .thold_1(perv_tbe_thold_1), //i-- + .sg_1(perv_tbe_sg_1), //i-- + .fpu_enable(perv_tbe_fpu_enable), //i-- + + .si(scan_in[17]), //i--ftbe + .so(scan_out[17]), //o--ftbe + .ex2_act_b(f_pic_lza_ex2_act_b), //i--ftbe + .f_pic_ex3_ue1(f_pic_ex3_ue1), //i--ftbe + .f_pic_ex3_sp_b(f_pic_ex3_sp_b), //i--ftbe + .f_pic_ex3_est_recip(f_pic_ex3_est_recip), //i--ftbe + .f_pic_ex3_est_rsqrt(f_pic_ex3_est_rsqrt), //i--ftbe + .f_eie_ex3_tbl_expo(f_eie_ex3_tbl_expo[1:13]), //i--ftbe + .f_fmt_ex3_lu_den_recip(f_fmt_ex3_lu_den_recip), //i--ftbe + .f_fmt_ex3_lu_den_rsqrto(f_fmt_ex3_lu_den_rsqrto), //i--ftbe + .f_tbe_ex4_match_en_sp(f_tbe_ex4_match_en_sp), //o--ftbe + .f_tbe_ex4_match_en_dp(f_tbe_ex4_match_en_dp), //o--ftbe + .f_tbe_ex4_recip_2046(f_tbe_ex4_recip_2046), //o--ftbe + .f_tbe_ex4_recip_2045(f_tbe_ex4_recip_2045), //o--ftbe + .f_tbe_ex4_recip_2044(f_tbe_ex4_recip_2044), //o--ftbe + .f_tbe_ex4_lu_sh(f_tbe_ex4_lu_sh), //o--ftbe + .f_tbe_ex4_recip_ue1(f_tbe_ex4_recip_ue1), //o--ftbe + .f_tbe_ex4_may_ov(f_tbe_ex4_may_ov), //o--ftbe + .f_tbe_ex4_res_expo(f_tbe_ex4_res_expo[1:13]) //o--ftbe + ); + + + fu_tbllut ftbl( + //----------------------------------------------------------- fuq_tbllut.vhdl + .vdd(vdd), //i-- + .gnd(gnd), //i-- + .nclk(nclk), //i-- + .clkoff_b(clkoff_b), //i-- + .act_dis(act_dis), //i-- + .flush(flush), //i-- + .delay_lclkr(delay_lclkr[2:5]), //i-- + .mpw1_b(mpw1_b[2:5]), //i-- + .mpw2_b(mpw2_b[0:1]), //i-- + .thold_1(perv_tbl_thold_1), //i-- + .sg_1(perv_tbl_sg_1), //i-- + .fpu_enable(perv_tbl_fpu_enable), //i-- + + .si(scan_in[18]), //i--ftbl + .so(scan_out[18]), //o--ftbl + .ex2_act(f_pic_tbl_ex2_act), //i--ftbl + .f_fmt_ex2_b_frac(f_fmt_ex2_b_frac[1:6]), //i--ftbl + .f_fmt_ex3_b_frac(f_fmt_ex3_pass_frac[7:22]), //i--ftbl + .f_tbe_ex3_expo_lsb(f_eie_ex3_tbl_expo[13]), //i--ftbl + .f_tbe_ex3_est_recip(f_pic_ex3_est_recip), //i--ftbl + .f_tbe_ex3_est_rsqrt(f_pic_ex3_est_rsqrt), //i--ftbl + .f_tbe_ex4_recip_ue1(f_tbe_ex4_recip_ue1), //i--ftbl + .f_tbe_ex4_lu_sh(f_tbe_ex4_lu_sh), //i--ftbl + .f_tbe_ex4_match_en_sp(f_tbe_ex4_match_en_sp), //i--ftbl + .f_tbe_ex4_match_en_dp(f_tbe_ex4_match_en_dp), //i--ftbl + .f_tbe_ex4_recip_2046(f_tbe_ex4_recip_2046), //i--ftbl + .f_tbe_ex4_recip_2045(f_tbe_ex4_recip_2045), //i--ftbl + .f_tbe_ex4_recip_2044(f_tbe_ex4_recip_2044), //i--ftbl + .f_tbl_ex6_est_frac(f_tbl_ex6_est_frac[0:26]), //o--ftbl + .f_tbl_ex5_unf_expo(f_tbl_ex5_unf_expo), //o--ftbl + .f_tbl_ex6_recip_den(f_tbl_ex6_recip_den) //o--ftbl + ); + //----------------------------------------------------------- fuq_tbllut.vhdl + + //------------------------------------------- + // pervasive + //------------------------------------------- + + assign perv_tbl_sg_1 = sg_1; + assign perv_tbe_sg_1 = sg_1; + assign perv_eie_sg_1 = sg_1; + assign perv_eov_sg_1 = sg_1; + assign perv_fmt_sg_1 = sg_1; + assign perv_mul_sg_1 = sg_1; + assign perv_alg_sg_1 = sg_1; + assign perv_sa3_sg_1 = sg_1; + assign perv_add_sg_1 = sg_1; + assign perv_lza_sg_1 = sg_1; + assign perv_nrm_sg_1 = sg_1; + assign perv_rnd_sg_1 = sg_1; + assign perv_scr_sg_1 = sg_1; + assign perv_pic_sg_1 = sg_1; + assign perv_cr2_sg_1 = sg_1; + + assign perv_tbl_thold_1 = thold_1; + assign perv_tbe_thold_1 = thold_1; + assign perv_eie_thold_1 = thold_1; + assign perv_eov_thold_1 = thold_1; + assign perv_fmt_thold_1 = thold_1; + assign perv_mul_thold_1 = thold_1; + assign perv_alg_thold_1 = thold_1; + assign perv_sa3_thold_1 = thold_1; + assign perv_add_thold_1 = thold_1; + assign perv_lza_thold_1 = thold_1; + assign perv_nrm_thold_1 = thold_1; + assign perv_rnd_thold_1 = thold_1; + assign perv_scr_thold_1 = thold_1; + assign perv_pic_thold_1 = thold_1; + assign perv_cr2_thold_1 = thold_1; + + assign perv_tbl_fpu_enable = fpu_enable; + assign perv_tbe_fpu_enable = fpu_enable; + assign perv_eie_fpu_enable = fpu_enable; + assign perv_eov_fpu_enable = fpu_enable; + assign perv_fmt_fpu_enable = fpu_enable; + assign perv_mul_fpu_enable = fpu_enable; + assign perv_alg_fpu_enable = fpu_enable; + assign perv_sa3_fpu_enable = fpu_enable; + assign perv_add_fpu_enable = fpu_enable; + assign perv_lza_fpu_enable = fpu_enable; + assign perv_nrm_fpu_enable = fpu_enable; + assign perv_rnd_fpu_enable = fpu_enable; + assign perv_scr_fpu_enable = fpu_enable; + assign perv_pic_fpu_enable = fpu_enable; + assign perv_cr2_fpu_enable = fpu_enable; + +endmodule diff --git a/dev/verilog/work/fu_nrm.v b/dev/verilog/work/fu_nrm.v new file mode 100755 index 0000000..7758205 --- /dev/null +++ b/dev/verilog/work/fu_nrm.v @@ -0,0 +1,609 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + + `include "tri_a2o.vh" + + +module fu_nrm( + vdd, + gnd, + clkoff_b, + act_dis, + flush, + delay_lclkr, + mpw1_b, + mpw2_b, + sg_1, + thold_1, + fpu_enable, + nclk, + f_nrm_si, + f_nrm_so, + ex4_act_b, + f_lza_ex5_lza_amt_cp1, + f_lza_ex5_lza_dcd64_cp1, + f_lza_ex5_lza_dcd64_cp2, + f_lza_ex5_lza_dcd64_cp3, + f_lza_ex5_sh_rgt_en, + f_add_ex5_res, + f_add_ex5_sticky, + f_pic_ex5_byp_prod_nz, + f_nrm_ex6_res, + f_nrm_ex6_int_sign, + f_nrm_ex6_int_lsbs, + f_nrm_ex6_nrm_sticky_dp, + f_nrm_ex6_nrm_guard_dp, + f_nrm_ex6_nrm_lsb_dp, + f_nrm_ex6_nrm_sticky_sp, + f_nrm_ex6_nrm_guard_sp, + f_nrm_ex6_nrm_lsb_sp, + f_nrm_ex6_exact_zero, + f_nrm_ex5_extra_shift, + f_nrm_ex6_fpscr_wr_dat_dfp, + f_nrm_ex6_fpscr_wr_dat +); + + inout vdd; + inout gnd; + input clkoff_b; // tiup + input act_dis; // ??tidn?? + input flush; // ??tidn?? + input [4:5] delay_lclkr; // tidn, + input [4:5] mpw1_b; // tidn, + input [0:1] mpw2_b; // tidn, + input sg_1; + input thold_1; + input fpu_enable; //dc_act + input [0:`NCLK_WIDTH-1] nclk; + + input f_nrm_si; // perv + output f_nrm_so; // perv + input ex4_act_b; // act + + input [0:7] f_lza_ex5_lza_amt_cp1; // shift amount + + input [0:2] f_lza_ex5_lza_dcd64_cp1; //fnrm + input [0:1] f_lza_ex5_lza_dcd64_cp2; //fnrm + input [0:0] f_lza_ex5_lza_dcd64_cp3; //fnrm + input f_lza_ex5_sh_rgt_en; + + input [0:162] f_add_ex5_res; // data to shift + input f_add_ex5_sticky; // or into sticky + input f_pic_ex5_byp_prod_nz; + output [0:52] f_nrm_ex6_res; //rnd, + output f_nrm_ex6_int_sign; //rnd, (151:162) + output [1:12] f_nrm_ex6_int_lsbs; //rnd, (151:162) + output f_nrm_ex6_nrm_sticky_dp; //rnd, + output f_nrm_ex6_nrm_guard_dp; //rnd, + output f_nrm_ex6_nrm_lsb_dp; //rnd, + output f_nrm_ex6_nrm_sticky_sp; //rnd, + output f_nrm_ex6_nrm_guard_sp; //rnd, + output f_nrm_ex6_nrm_lsb_sp; //rnd, + output f_nrm_ex6_exact_zero; //rnd, + output f_nrm_ex5_extra_shift; //expo_ov, + output [0:3] f_nrm_ex6_fpscr_wr_dat_dfp; //fpscr, (17:20) + output [0:31] f_nrm_ex6_fpscr_wr_dat; //fpscr, (21:52) + + // end ports + + // ENTITY + + + parameter tiup = 1'b1; + parameter tidn = 1'b0; + + wire sg_0; + wire thold_0_b; + wire thold_0; + wire force_t; + wire ex4_act; + wire ex5_act; + wire [0:2] act_spare_unused; + //----------------- + wire [0:3] act_so; //SCAN + wire [0:3] act_si; //SCAN + wire [0:52] ex6_res_so; //SCAN + wire [0:52] ex6_res_si; //SCAN + wire [0:3] ex6_nrm_lg_so; //SCAN + wire [0:3] ex6_nrm_lg_si; //SCAN + wire [0:2] ex6_nrm_x_so; //SCAN + wire [0:2] ex6_nrm_x_si; //SCAN + wire [0:12] ex6_nrm_pass_so; //SCAN + wire [0:12] ex6_nrm_pass_si; //SCAN + wire [0:35] ex6_fmv_so; //SCAN + wire [0:35] ex6_fmv_si; //SCAN + //----------------- + wire [26:72] ex5_sh2; + wire ex5_sh4_25; //shifting + wire ex5_sh4_54; //shifting + wire [0:53] ex5_nrm_res; //shifting + wire [0:53] ex5_sh5_x_b; + wire [0:53] ex5_sh5_y_b; + wire ex5_lt064_x; //sticky + wire ex5_lt128_x; //sticky + wire ex5_lt016_x; //sticky + wire ex5_lt032_x; //sticky + wire ex5_lt048_x; //sticky + wire ex5_lt016; //sticky + wire ex5_lt032; //sticky + wire ex5_lt048; //sticky + wire ex5_lt064; //sticky + wire ex5_lt080; //sticky + wire ex5_lt096; //sticky + wire ex5_lt112; //sticky + wire ex5_lt128; //sticky + wire ex5_lt04_x; //sticky + wire ex5_lt08_x; //sticky + wire ex5_lt12_x; //sticky + wire ex5_lt01_x; //sticky + wire ex5_lt02_x; //sticky + wire ex5_lt03_x; //sticky + wire ex5_sticky_sp; //sticky + wire ex5_sticky_dp; //sticky + wire ex5_sticky16_dp; //sticky + wire ex5_sticky16_sp; //sticky + wire [0:10] ex5_or_grp16; //sticky + wire [0:14] ex5_lt; //sticky + wire ex5_exact_zero; //sticky + wire ex5_exact_zero_b; //sticky + //------------------ + wire [0:52] ex6_res; // LATCH OUTPUTS + wire ex6_nrm_sticky_dp; + wire ex6_nrm_guard_dp; + wire ex6_nrm_lsb_dp; + wire ex6_nrm_sticky_sp; + wire ex6_nrm_guard_sp; + wire ex6_nrm_lsb_sp; + wire ex6_exact_zero; + wire ex6_int_sign; + wire [1:12] ex6_int_lsbs; + wire [0:31] ex6_fpscr_wr_dat; + wire [0:3] ex6_fpscr_wr_dat_dfp; + wire ex5_rgt_4more; + wire ex5_rgt_3more; + wire ex5_rgt_2more; + wire ex5_shift_extra_cp2; + wire unused; + + wire ex5_sticky_dp_x2_b; + wire ex5_sticky_dp_x1_b; + wire ex5_sticky_dp_x1; + wire ex5_sticky_sp_x2_b; + wire ex5_sticky_sp_x1_b; + wire ex5_sticky_sp_x1; + wire ex6_d1clk; + wire ex6_d2clk; + wire [0:`NCLK_WIDTH-1] ex6_lclk; + wire ex5_sticky_stuff; + + // sticky bit sp/dp does not look at all the bits + assign unused = |(ex5_sh2[41:54]) | |(ex5_nrm_res[0:53]) | ex5_sticky_sp | ex5_sticky_dp | ex5_exact_zero; + + ////############################################ + //# pervasive + ////############################################ + + + tri_plat thold_reg_0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(flush), + .din(thold_1), + .q(thold_0) + ); + + + tri_plat sg_reg_0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(flush), + .din(sg_1), + .q(sg_0) + ); + + + tri_lcbor lcbor_0( + .clkoff_b(clkoff_b), + .thold(thold_0), + .sg(sg_0), + .act_dis(act_dis), + .force_t(force_t), + .thold_b(thold_0_b) + ); + + tri_lcbnd ex6_lcb( + .delay_lclkr(delay_lclkr[5]), // tidn + .mpw1_b(mpw1_b[5]), // tidn + .mpw2_b(mpw2_b[1]), // tidn + .force_t(force_t), // tidn + .nclk(nclk), //in + .vd(vdd), //inout + .gd(gnd), //inout + .act(ex5_act), //in + .sg(sg_0), //in + .thold_b(thold_0_b), //in + .d1clk(ex6_d1clk), //out + .d2clk(ex6_d2clk), //out + .lclk(ex6_lclk) //out + ); + + ////############################################ + //# ACT LATCHES + ////############################################ + + assign ex4_act = (~ex4_act_b); + + + tri_rlmreg_p #(.WIDTH(4), .NEEDS_SRESET(0)) act_lat( + .force_t(force_t), //i-- tidn, + .d_mode(tiup), + .delay_lclkr(delay_lclkr[4]), //i-- tidn, + .mpw1_b(mpw1_b[4]), //i-- tidn, + .mpw2_b(mpw2_b[0]), //i-- tidn, + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + .act(fpu_enable), + .scout(act_so[0:3]), + .scin(act_si[0:3]), + //----------------- + .din({ act_spare_unused[0], + act_spare_unused[1], + ex4_act, + act_spare_unused[2]}), + //----------------- + .dout({ act_spare_unused[0], + act_spare_unused[1], + ex5_act, + act_spare_unused[2]}) + ); + + ////############################################## + //# EX5 logic: shifting + ////############################################## + + + fu_nrm_sh sh( + .f_lza_ex5_sh_rgt_en(f_lza_ex5_sh_rgt_en), //i-- + .f_lza_ex5_lza_amt_cp1(f_lza_ex5_lza_amt_cp1[2:7]), //i-- + .f_lza_ex5_lza_dcd64_cp1(f_lza_ex5_lza_dcd64_cp1[0:2]), //i-- + .f_lza_ex5_lza_dcd64_cp2(f_lza_ex5_lza_dcd64_cp2[0:1]), //i-- + .f_lza_ex5_lza_dcd64_cp3(f_lza_ex5_lza_dcd64_cp3[0:0]), //i-- + .f_add_ex5_res(f_add_ex5_res[0:162]), //i-- + .ex5_shift_extra_cp1(f_nrm_ex5_extra_shift), //o-- <30ish> loads feov + .ex5_shift_extra_cp2(ex5_shift_extra_cp2), //o-- <2> loads sticky sp/dp + .ex5_sh4_25(ex5_sh4_25), //o-- + .ex5_sh4_54(ex5_sh4_54), //o-- + .ex5_sh2_o(ex5_sh2[26:72]), //o-- + .ex5_sh5_x_b(ex5_sh5_x_b[0:53]), //o-- + .ex5_sh5_y_b(ex5_sh5_y_b[0:53]) //o-- + ); + + assign ex5_nrm_res[0:53] = (~(ex5_sh5_x_b[0:53] & ex5_sh5_y_b[0:53])); + ////############################################## + //# EX5 logic: stciky bit + ////############################################## + + //# thermometer decode 1 --------------- + //# + //# the smaller the shift the more sticky bits. + //# the multiple of 16 shifter is 0:68 ... bits after 68 are known sticky DP. + //# 53-24=29 extra sp bits 68-29 = 39 + //# bits after 39 are known sticky SP. + + assign ex5_lt064_x = (~(f_lza_ex5_lza_amt_cp1[0] | f_lza_ex5_lza_amt_cp1[1])); // 00 + assign ex5_lt128_x = (~(f_lza_ex5_lza_amt_cp1[0])); // 00 01 + + assign ex5_lt016_x = (~(f_lza_ex5_lza_amt_cp1[2] | f_lza_ex5_lza_amt_cp1[3])); // 00 + assign ex5_lt032_x = (~(f_lza_ex5_lza_amt_cp1[2])); // 00 01 + assign ex5_lt048_x = (~(f_lza_ex5_lza_amt_cp1[2] & f_lza_ex5_lza_amt_cp1[3])); // 00 01 10 + + assign ex5_lt016 = ex5_lt064_x & ex5_lt016_x; //tail=067 sticky_dp=069:162 sticky_sp=039:162 + assign ex5_lt032 = ex5_lt064_x & ex5_lt032_x; //tail=083 sticky_dp=085:162 sticky_sp=055:162 + assign ex5_lt048 = ex5_lt064_x & ex5_lt048_x; //tail=099 sticky_dp=101:162 sticky_sp=071:162 + assign ex5_lt064 = ex5_lt064_x; //tail=115 sticky_dp=117:162 sticky_sp=087:162 + assign ex5_lt080 = ex5_lt064_x | (ex5_lt128_x & ex5_lt016_x); //tail=131 sticky_dp=133:162 sticky_sp=103:162 + assign ex5_lt096 = ex5_lt064_x | (ex5_lt128_x & ex5_lt032_x); //tail=147 sticky_dp=149:162 sticky_sp=119:162 + assign ex5_lt112 = ex5_lt064_x | (ex5_lt128_x & ex5_lt048_x); //tail=163 sticky_dp=xxxxxxx sticky_sp=135:162 + assign ex5_lt128 = ex5_lt128_x; //tail=179 sticky_dp=xxxxxxx sticky_sp=151:162 + + // 1111xxxx shift right 1 -> 16 (shift right sticky groups of 16 may be off by one from shift left sticky groups) + // 1110xxxx shift right 17 -> 32 + // 1101xxxx shift right 33 -> 48 + // 1100xxxx shift right 49 -> 64 + // x0xxxxxx shift > 64 + // 0xxxxxxx shift > 64 + + // for shift right Amt[0]==Amt[1]==shRgtEn + // xx00_dddd Right64, then Left00 4 more sticky16 group than 0000_dddd + // xx01_dddd Right64, then Left16 3 more sticky16 group than 0000_dddd + // xx10_dddd Right64, then Left32 2 more sticky16 group than 0000_dddd + // xx11_dddd Right64, then Left48 1 more sticky16 group than 0000_dddd + + assign ex5_rgt_2more = f_lza_ex5_sh_rgt_en & ((~f_lza_ex5_lza_amt_cp1[2]) | (~f_lza_ex5_lza_amt_cp1[3])); // 234 + assign ex5_rgt_3more = f_lza_ex5_sh_rgt_en & ((~f_lza_ex5_lza_amt_cp1[2])); // 23 + assign ex5_rgt_4more = f_lza_ex5_sh_rgt_en & ((~f_lza_ex5_lza_amt_cp1[2]) & (~f_lza_ex5_lza_amt_cp1[3])); // 2 + + //#------------------------ + //# sticky group 16 ors + //#------------------------ + + + fu_nrm_or16 or16( + .f_add_ex5_res(f_add_ex5_res[0:162]), //i-- + .ex5_or_grp16(ex5_or_grp16[0:10]) //o-- + ); + + //#------------------------ + //# enable the 16 bit ors + //#------------------------ + + assign ex5_sticky_stuff = (f_pic_ex5_byp_prod_nz) | (f_add_ex5_sticky); + + // 71: 86 + // 87:102 + //103:118 + //119:134 + //135:150 + //151:162 + // so group16s match for sp/dp + assign ex5_sticky16_dp = (ex5_or_grp16[1] & ex5_rgt_4more) | (ex5_or_grp16[2] & ex5_rgt_3more) | (ex5_or_grp16[3] & ex5_rgt_2more) | (ex5_or_grp16[4] & f_lza_ex5_sh_rgt_en) | (ex5_or_grp16[5] & (ex5_lt016 | f_lza_ex5_sh_rgt_en)) | (ex5_or_grp16[6] & (ex5_lt032 | f_lza_ex5_sh_rgt_en)) | (ex5_or_grp16[7] & (ex5_lt048 | f_lza_ex5_sh_rgt_en)) | (ex5_or_grp16[8] & (ex5_lt064 | f_lza_ex5_sh_rgt_en)) | (ex5_or_grp16[9] & (ex5_lt080 | f_lza_ex5_sh_rgt_en)) | (ex5_or_grp16[10] & (ex5_lt096 | f_lza_ex5_sh_rgt_en)) | (ex5_sh2[70]) | (ex5_sh2[71]) | (ex5_sh2[72]) | (ex5_sticky_stuff); // so group16s match for sp/dp + + // 39: 54 + // 55: 70 + // 71: 86 + // 87:102 + //103:118 + //119:134 + //135:150 + assign ex5_sticky16_sp = (ex5_or_grp16[0] & ex5_rgt_3more) | (ex5_or_grp16[1] & ex5_rgt_2more) | (ex5_or_grp16[2] & f_lza_ex5_sh_rgt_en) | (ex5_or_grp16[3] & (ex5_lt016 | f_lza_ex5_sh_rgt_en)) | (ex5_or_grp16[4] & (ex5_lt032 | f_lza_ex5_sh_rgt_en)) | (ex5_or_grp16[5] & (ex5_lt048 | f_lza_ex5_sh_rgt_en)) | (ex5_or_grp16[6] & (ex5_lt064 | f_lza_ex5_sh_rgt_en)) | (ex5_or_grp16[7] & (ex5_lt080 | f_lza_ex5_sh_rgt_en)) | (ex5_or_grp16[8] & (ex5_lt096 | f_lza_ex5_sh_rgt_en)) | (ex5_or_grp16[9] & (ex5_lt112 | f_lza_ex5_sh_rgt_en)) | (ex5_or_grp16[10] & (ex5_lt128 | f_lza_ex5_sh_rgt_en)) | (ex5_sticky_stuff); //151:162 + + assign ex5_exact_zero_b = ex5_or_grp16[0] | ex5_or_grp16[1] | ex5_or_grp16[2] | ex5_or_grp16[3] | ex5_or_grp16[4] | ex5_or_grp16[5] | ex5_or_grp16[6] | ex5_or_grp16[7] | ex5_or_grp16[8] | ex5_or_grp16[9] | ex5_or_grp16[10] | (ex5_sticky_stuff); + + assign ex5_exact_zero = (~ex5_exact_zero_b); + + //#------------------------ + //# thermometer decode 2 + //#------------------------ + + assign ex5_lt04_x = (~(f_lza_ex5_lza_amt_cp1[4] | f_lza_ex5_lza_amt_cp1[5])); // 00 + assign ex5_lt08_x = (~(f_lza_ex5_lza_amt_cp1[4])); // 00 01 + assign ex5_lt12_x = (~(f_lza_ex5_lza_amt_cp1[4] & f_lza_ex5_lza_amt_cp1[5])); // 00 01 10 + + assign ex5_lt01_x = (~(f_lza_ex5_lza_amt_cp1[6] | f_lza_ex5_lza_amt_cp1[7])); // 00 + assign ex5_lt02_x = (~(f_lza_ex5_lza_amt_cp1[6])); // 00 01 + assign ex5_lt03_x = (~(f_lza_ex5_lza_amt_cp1[6] & f_lza_ex5_lza_amt_cp1[7])); // 00 01 10 + + assign ex5_lt[0] = ex5_lt04_x & ex5_lt01_x; // 1 + assign ex5_lt[1] = ex5_lt04_x & ex5_lt02_x; // 2 + assign ex5_lt[2] = ex5_lt04_x & ex5_lt03_x; // 3 + assign ex5_lt[3] = ex5_lt04_x; // 4 + + assign ex5_lt[4] = ex5_lt04_x | (ex5_lt08_x & ex5_lt01_x); // 5 + assign ex5_lt[5] = ex5_lt04_x | (ex5_lt08_x & ex5_lt02_x); // 6 + assign ex5_lt[6] = ex5_lt04_x | (ex5_lt08_x & ex5_lt03_x); // 7 + assign ex5_lt[7] = (ex5_lt08_x); // 8 + + assign ex5_lt[8] = ex5_lt08_x | (ex5_lt12_x & ex5_lt01_x); // 9 + assign ex5_lt[9] = ex5_lt08_x | (ex5_lt12_x & ex5_lt02_x); //10 + assign ex5_lt[10] = ex5_lt08_x | (ex5_lt12_x & ex5_lt03_x); //11 + assign ex5_lt[11] = (ex5_lt12_x); //12 + + assign ex5_lt[12] = ex5_lt12_x | ex5_lt01_x; //13 + assign ex5_lt[13] = ex5_lt12_x | ex5_lt02_x; //14 + assign ex5_lt[14] = ex5_lt12_x | ex5_lt03_x; //15 + + //#------------------------ + //# final sticky bits + //#------------------------ + + // lt 01 + // lt 02 + // lt 03 + // lt 04 + // lt 05 + // lt 06 + // lt 07 + // lt 08 + // lt 09 + // lt 10 + // lt 11 + // lt 12 + // lt 13 + // lt 14 + assign ex5_sticky_sp_x1 = (ex5_lt[14] & ex5_sh2[40]) | (ex5_lt[13] & ex5_sh2[39]) | (ex5_lt[12] & ex5_sh2[38]) | (ex5_lt[11] & ex5_sh2[37]) | (ex5_lt[10] & ex5_sh2[36]) | (ex5_lt[9] & ex5_sh2[35]) | (ex5_lt[8] & ex5_sh2[34]) | (ex5_lt[7] & ex5_sh2[33]) | (ex5_lt[6] & ex5_sh2[32]) | (ex5_lt[5] & ex5_sh2[31]) | (ex5_lt[4] & ex5_sh2[30]) | (ex5_lt[3] & ex5_sh2[29]) | (ex5_lt[2] & ex5_sh2[28]) | (ex5_lt[1] & ex5_sh2[27]) | (ex5_lt[0] & ex5_sh2[26]) | (ex5_sticky16_sp); // lt 15 + + assign ex5_sticky_sp_x2_b = (~((~ex5_shift_extra_cp2) & ex5_sh4_25)); + assign ex5_sticky_sp_x1_b = (~ex5_sticky_sp_x1); + assign ex5_sticky_sp = (~(ex5_sticky_sp_x1_b & ex5_sticky_sp_x2_b)); + + // lt 01 + // lt 02 + // lt 03 + // lt 04 + // lt 05 + // lt 06 + // lt 07 + // lt 08 + // lt 09 + // lt 10 + // lt 11 + // lt 12 + // lt 13 + // lt 14 + assign ex5_sticky_dp_x1 = (ex5_lt[14] & ex5_sh2[69]) | (ex5_lt[13] & ex5_sh2[68]) | (ex5_lt[12] & ex5_sh2[67]) | (ex5_lt[11] & ex5_sh2[66]) | (ex5_lt[10] & ex5_sh2[65]) | (ex5_lt[9] & ex5_sh2[64]) | (ex5_lt[8] & ex5_sh2[63]) | (ex5_lt[7] & ex5_sh2[62]) | (ex5_lt[6] & ex5_sh2[61]) | (ex5_lt[5] & ex5_sh2[60]) | (ex5_lt[4] & ex5_sh2[59]) | (ex5_lt[3] & ex5_sh2[58]) | (ex5_lt[2] & ex5_sh2[57]) | (ex5_lt[1] & ex5_sh2[56]) | (ex5_lt[0] & ex5_sh2[55]) | (ex5_sticky16_dp); // lt 15 + + assign ex5_sticky_dp_x2_b = (~((~ex5_shift_extra_cp2) & ex5_sh4_54)); + assign ex5_sticky_dp_x1_b = (~ex5_sticky_dp_x1); + assign ex5_sticky_dp = (~(ex5_sticky_dp_x1_b & ex5_sticky_dp_x2_b)); + + ////############################################## + //# EX6 latches + ////############################################## + + + // , ibuf => true, + tri_nand2_nlats #(.WIDTH(53), .NEEDS_SRESET(0)) ex6_res_lat( + .vd(vdd), + .gd(gnd), + .lclk(ex6_lclk), //lclk.clk + .d1clk(ex6_d1clk), + .d2clk(ex6_d2clk), + .scanin(ex6_res_si), + .scanout(ex6_res_so), + .a1(ex5_sh5_x_b[0:52]), + .a2(ex5_sh5_y_b[0:52]), + .qb(ex6_res[0:52]) //LAT-- + ); + + // , ibuf => true, + tri_nand2_nlats #(.WIDTH(4), .NEEDS_SRESET(0)) ex6_nrm_lg_lat( + .vd(vdd), + .gd(gnd), + .lclk(ex6_lclk), //lclk.clk + .d1clk(ex6_d1clk), + .d2clk(ex6_d2clk), + .scanin(ex6_nrm_lg_si), + .scanout(ex6_nrm_lg_so), + //----------------- + .a1({ex5_sh5_x_b[23], + ex5_sh5_x_b[24], + ex5_sh5_x_b[52], + ex5_sh5_x_b[53]}), + //----------------- + .a2({ex5_sh5_y_b[23], + ex5_sh5_y_b[24], + ex5_sh5_y_b[52], + ex5_sh5_y_b[53]}), + //----------------- + .qb({ex6_nrm_lsb_sp, //LAT-- --sp lsb + ex6_nrm_guard_sp, //LAT-- --sp guard + ex6_nrm_lsb_dp, //LAT-- --dp lsb + ex6_nrm_guard_dp}) //LAT-- --dp guard + ); + + // , ibuf => true, + tri_nand2_nlats #(.WIDTH(3), .NEEDS_SRESET(0)) ex6_nrm_x_lat( + .vd(vdd), + .gd(gnd), + .lclk(ex6_lclk), //lclk.clk + .d1clk(ex6_d1clk), + .d2clk(ex6_d2clk), + .scanin(ex6_nrm_x_si), + .scanout(ex6_nrm_x_so), + //----------------- + .a1({ ex5_sticky_sp_x2_b, + ex5_sticky_dp_x2_b, + ex5_exact_zero_b}), + //----------------- + .a2({ ex5_sticky_sp_x1_b, + ex5_sticky_dp_x1_b, + tiup}), + //----------------- + .qb({ ex6_nrm_sticky_sp, //LAT-- + ex6_nrm_sticky_dp, //LAT-- + ex6_exact_zero}) //LAT-- + ); + + + tri_rlmreg_p #(.WIDTH(13), .IBUF(1'B1), .NEEDS_SRESET(0)) ex6_nrm_pass_lat( + .force_t(force_t), //i-- tidn, + .d_mode(tiup), + .delay_lclkr(delay_lclkr[5]), //i-- tidn, + .mpw1_b(mpw1_b[5]), //i-- tidn, + .mpw2_b(mpw2_b[1]), //i-- tidn, + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + .act(ex5_act), + .scout(ex6_nrm_pass_so), + .scin(ex6_nrm_pass_si), + //----------------- + .din({f_add_ex5_res[99], + f_add_ex5_res[151:162]}), // (151:162) + //----------------- + .dout({ex6_int_sign, //LAT-- + ex6_int_lsbs[1:12]}) //LAT-- --(151:162) + ); + + + tri_rlmreg_p #(.WIDTH(36), .IBUF(1'B1), .NEEDS_SRESET(1)) ex6_fmv_lat( + .force_t(force_t), //i-- tidn, + .d_mode(tiup), + .delay_lclkr(delay_lclkr[5]), //i-- tidn, + .mpw1_b(mpw1_b[5]), //i-- tidn, + .mpw2_b(mpw2_b[1]), //i-- tidn, + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + .act(ex5_act), + .scout(ex6_fmv_so), + .scin(ex6_fmv_si), + //----------------- + .din(f_add_ex5_res[17:52]), //LAT + //----------------- + .dout({ex6_fpscr_wr_dat_dfp[0:3], + ex6_fpscr_wr_dat[0:31]}) //LAT + ); + + assign f_nrm_ex6_res = ex6_res[0:52]; //output--rnd + assign f_nrm_ex6_nrm_lsb_sp = ex6_nrm_lsb_sp; //output--rnd + assign f_nrm_ex6_nrm_guard_sp = ex6_nrm_guard_sp; //output--rnd + assign f_nrm_ex6_nrm_sticky_sp = ex6_nrm_sticky_sp; //output--rnd + assign f_nrm_ex6_nrm_lsb_dp = ex6_nrm_lsb_dp; //output--rnd + assign f_nrm_ex6_nrm_guard_dp = ex6_nrm_guard_dp; //output--rnd + assign f_nrm_ex6_nrm_sticky_dp = ex6_nrm_sticky_dp; //output--rnd + assign f_nrm_ex6_exact_zero = ex6_exact_zero; //output--rnd + assign f_nrm_ex6_int_lsbs = ex6_int_lsbs[1:12]; //output--rnd (151:162) + assign f_nrm_ex6_fpscr_wr_dat = ex6_fpscr_wr_dat[0:31]; //output--fpscr, (21:52) + assign f_nrm_ex6_fpscr_wr_dat_dfp = ex6_fpscr_wr_dat_dfp[0:3]; //output--fpscr (17:20) + assign f_nrm_ex6_int_sign = ex6_int_sign; //output--rnd (151:162) + + ////############################################ + //# scan + ////############################################ + + assign act_si[0:3] = {act_so[1:3], f_nrm_si}; + assign ex6_res_si[0:52] = {ex6_res_so[1:52], act_so[0]}; + assign ex6_nrm_lg_si[0:3] = {ex6_nrm_lg_so[1:3], ex6_res_so[0]}; + assign ex6_nrm_x_si[0:2] = {ex6_nrm_x_so[1:2], ex6_nrm_lg_so[0]}; + assign ex6_nrm_pass_si[0:12] = {ex6_nrm_pass_so[1:12], ex6_nrm_x_so[0]}; + assign ex6_fmv_si[0:35] = {ex6_fmv_so[1:35], ex6_nrm_pass_so[0]}; + assign f_nrm_so = ex6_fmv_so[0]; + +endmodule diff --git a/dev/verilog/work/fu_nrm_or16.v b/dev/verilog/work/fu_nrm_or16.v new file mode 100755 index 0000000..3ae79a7 --- /dev/null +++ b/dev/verilog/work/fu_nrm_or16.v @@ -0,0 +1,325 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + + `include "tri_a2o.vh" + + +module fu_nrm_or16( + f_add_ex5_res, + ex5_or_grp16 +); + input [0:162] f_add_ex5_res; + output [0:10] ex5_or_grp16; + + // ENTITY + + + parameter tiup = 1'b1; + parameter tidn = 1'b0; + + wire [0:162] ex5_res_b; + wire [0:3] g00_or02; + wire [0:7] g01_or02; + wire [0:7] g02_or02; + wire [0:7] g03_or02; + wire [0:7] g04_or02; + wire [0:7] g05_or02; + wire [0:7] g06_or02; + wire [0:7] g07_or02; + wire [0:7] g08_or02; + wire [0:7] g09_or02; + wire [0:5] g10_or02; + + wire [0:1] g00_or04_b; + wire [0:3] g01_or04_b; + wire [0:3] g02_or04_b; + wire [0:3] g03_or04_b; + wire [0:3] g04_or04_b; + wire [0:3] g05_or04_b; + wire [0:3] g06_or04_b; + wire [0:3] g07_or04_b; + wire [0:3] g08_or04_b; + wire [0:3] g09_or04_b; + wire [0:2] g10_or04_b; + + wire [0:0] g00_or08; + wire [0:1] g01_or08; + wire [0:1] g02_or08; + wire [0:1] g03_or08; + wire [0:1] g04_or08; + wire [0:1] g05_or08; + wire [0:1] g06_or08; + wire [0:1] g07_or08; + wire [0:1] g08_or08; + wire [0:1] g09_or08; + wire [0:1] g10_or08; + + wire g00_or16_b; + wire g01_or16_b; + wire g02_or16_b; + wire g03_or16_b; + wire g04_or16_b; + wire g05_or16_b; + wire g06_or16_b; + wire g07_or16_b; + wire g08_or16_b; + wire g09_or16_b; + wire g10_or16_b; + + // ex5_or_grp16(0) <= 0: 7 + // ex5_or_grp16(1) <= 8: 23 + // ex5_or_grp16(2) <= 24: 39 + // ex5_or_grp16(3) <= 40: 55 + // ex5_or_grp16(4) <= 56: 71 + // ex5_or_grp16(5) <= 72: 87 + // ex5_or_grp16(6) <= 88:103 + // ex5_or_grp16(7) <= 104:119 + // ex5_or_grp16(8) <= 120:135 + // ex5_or_grp16(9) <= 136:151 + // ex5_or_grp16(10) <= 152:162 + + //===============================================================-- + + assign ex5_res_b[0:162] = (~f_add_ex5_res[0:162]); // small + + //===============================================================-- + + assign g00_or02[0] = (~(ex5_res_b[0] & ex5_res_b[1])); + assign g00_or02[1] = (~(ex5_res_b[2] & ex5_res_b[3])); + assign g00_or02[2] = (~(ex5_res_b[4] & ex5_res_b[5])); + assign g00_or02[3] = (~(ex5_res_b[6] & ex5_res_b[7])); + + assign g01_or02[0] = (~(ex5_res_b[8] & ex5_res_b[9])); + assign g01_or02[1] = (~(ex5_res_b[10] & ex5_res_b[11])); + assign g01_or02[2] = (~(ex5_res_b[12] & ex5_res_b[13])); + assign g01_or02[3] = (~(ex5_res_b[14] & ex5_res_b[15])); + assign g01_or02[4] = (~(ex5_res_b[16] & ex5_res_b[17])); + assign g01_or02[5] = (~(ex5_res_b[18] & ex5_res_b[19])); + assign g01_or02[6] = (~(ex5_res_b[20] & ex5_res_b[21])); + assign g01_or02[7] = (~(ex5_res_b[22] & ex5_res_b[23])); + + assign g02_or02[0] = (~(ex5_res_b[24] & ex5_res_b[25])); + assign g02_or02[1] = (~(ex5_res_b[26] & ex5_res_b[27])); + assign g02_or02[2] = (~(ex5_res_b[28] & ex5_res_b[29])); + assign g02_or02[3] = (~(ex5_res_b[30] & ex5_res_b[31])); + assign g02_or02[4] = (~(ex5_res_b[32] & ex5_res_b[33])); + assign g02_or02[5] = (~(ex5_res_b[34] & ex5_res_b[35])); + assign g02_or02[6] = (~(ex5_res_b[36] & ex5_res_b[37])); + assign g02_or02[7] = (~(ex5_res_b[38] & ex5_res_b[39])); + + assign g03_or02[0] = (~(ex5_res_b[40] & ex5_res_b[41])); + assign g03_or02[1] = (~(ex5_res_b[42] & ex5_res_b[43])); + assign g03_or02[2] = (~(ex5_res_b[44] & ex5_res_b[45])); + assign g03_or02[3] = (~(ex5_res_b[46] & ex5_res_b[47])); + assign g03_or02[4] = (~(ex5_res_b[48] & ex5_res_b[49])); + assign g03_or02[5] = (~(ex5_res_b[50] & ex5_res_b[51])); + assign g03_or02[6] = (~(ex5_res_b[52] & ex5_res_b[53])); + assign g03_or02[7] = (~(ex5_res_b[54] & ex5_res_b[55])); + + assign g04_or02[0] = (~(ex5_res_b[56] & ex5_res_b[57])); + assign g04_or02[1] = (~(ex5_res_b[58] & ex5_res_b[59])); + assign g04_or02[2] = (~(ex5_res_b[60] & ex5_res_b[61])); + assign g04_or02[3] = (~(ex5_res_b[62] & ex5_res_b[63])); + assign g04_or02[4] = (~(ex5_res_b[64] & ex5_res_b[65])); + assign g04_or02[5] = (~(ex5_res_b[66] & ex5_res_b[67])); + assign g04_or02[6] = (~(ex5_res_b[68] & ex5_res_b[69])); + assign g04_or02[7] = (~(ex5_res_b[70] & ex5_res_b[71])); + + assign g05_or02[0] = (~(ex5_res_b[72] & ex5_res_b[73])); + assign g05_or02[1] = (~(ex5_res_b[74] & ex5_res_b[75])); + assign g05_or02[2] = (~(ex5_res_b[76] & ex5_res_b[77])); + assign g05_or02[3] = (~(ex5_res_b[78] & ex5_res_b[79])); + assign g05_or02[4] = (~(ex5_res_b[80] & ex5_res_b[81])); + assign g05_or02[5] = (~(ex5_res_b[82] & ex5_res_b[83])); + assign g05_or02[6] = (~(ex5_res_b[84] & ex5_res_b[85])); + assign g05_or02[7] = (~(ex5_res_b[86] & ex5_res_b[87])); + + assign g06_or02[0] = (~(ex5_res_b[88] & ex5_res_b[89])); + assign g06_or02[1] = (~(ex5_res_b[90] & ex5_res_b[91])); + assign g06_or02[2] = (~(ex5_res_b[92] & ex5_res_b[93])); + assign g06_or02[3] = (~(ex5_res_b[94] & ex5_res_b[95])); + assign g06_or02[4] = (~(ex5_res_b[96] & ex5_res_b[97])); + assign g06_or02[5] = (~(ex5_res_b[98] & ex5_res_b[99])); + assign g06_or02[6] = (~(ex5_res_b[100] & ex5_res_b[101])); + assign g06_or02[7] = (~(ex5_res_b[102] & ex5_res_b[103])); + + assign g07_or02[0] = (~(ex5_res_b[104] & ex5_res_b[105])); + assign g07_or02[1] = (~(ex5_res_b[106] & ex5_res_b[107])); + assign g07_or02[2] = (~(ex5_res_b[108] & ex5_res_b[109])); + assign g07_or02[3] = (~(ex5_res_b[110] & ex5_res_b[111])); + assign g07_or02[4] = (~(ex5_res_b[112] & ex5_res_b[113])); + assign g07_or02[5] = (~(ex5_res_b[114] & ex5_res_b[115])); + assign g07_or02[6] = (~(ex5_res_b[116] & ex5_res_b[117])); + assign g07_or02[7] = (~(ex5_res_b[118] & ex5_res_b[119])); + + assign g08_or02[0] = (~(ex5_res_b[120] & ex5_res_b[121])); + assign g08_or02[1] = (~(ex5_res_b[122] & ex5_res_b[123])); + assign g08_or02[2] = (~(ex5_res_b[124] & ex5_res_b[125])); + assign g08_or02[3] = (~(ex5_res_b[126] & ex5_res_b[127])); + assign g08_or02[4] = (~(ex5_res_b[128] & ex5_res_b[129])); + assign g08_or02[5] = (~(ex5_res_b[130] & ex5_res_b[131])); + assign g08_or02[6] = (~(ex5_res_b[132] & ex5_res_b[133])); + assign g08_or02[7] = (~(ex5_res_b[134] & ex5_res_b[135])); + + assign g09_or02[0] = (~(ex5_res_b[136] & ex5_res_b[137])); + assign g09_or02[1] = (~(ex5_res_b[138] & ex5_res_b[139])); + assign g09_or02[2] = (~(ex5_res_b[140] & ex5_res_b[141])); + assign g09_or02[3] = (~(ex5_res_b[142] & ex5_res_b[143])); + assign g09_or02[4] = (~(ex5_res_b[144] & ex5_res_b[145])); + assign g09_or02[5] = (~(ex5_res_b[146] & ex5_res_b[147])); + assign g09_or02[6] = (~(ex5_res_b[148] & ex5_res_b[149])); + assign g09_or02[7] = (~(ex5_res_b[150] & ex5_res_b[151])); + + assign g10_or02[0] = (~(ex5_res_b[152] & ex5_res_b[153])); + assign g10_or02[1] = (~(ex5_res_b[154] & ex5_res_b[155])); + assign g10_or02[2] = (~(ex5_res_b[156] & ex5_res_b[157])); + assign g10_or02[3] = (~(ex5_res_b[158] & ex5_res_b[159])); + assign g10_or02[4] = (~(ex5_res_b[160] & ex5_res_b[161])); + assign g10_or02[5] = (~(ex5_res_b[162])); + + //===============================================================-- + + assign g00_or04_b[0] = (~(g00_or02[0] | g00_or02[1])); + assign g00_or04_b[1] = (~(g00_or02[2] | g00_or02[3])); + + assign g01_or04_b[0] = (~(g01_or02[0] | g01_or02[1])); + assign g01_or04_b[1] = (~(g01_or02[2] | g01_or02[3])); + assign g01_or04_b[2] = (~(g01_or02[4] | g01_or02[5])); + assign g01_or04_b[3] = (~(g01_or02[6] | g01_or02[7])); + + assign g02_or04_b[0] = (~(g02_or02[0] | g02_or02[1])); + assign g02_or04_b[1] = (~(g02_or02[2] | g02_or02[3])); + assign g02_or04_b[2] = (~(g02_or02[4] | g02_or02[5])); + assign g02_or04_b[3] = (~(g02_or02[6] | g02_or02[7])); + + assign g03_or04_b[0] = (~(g03_or02[0] | g03_or02[1])); + assign g03_or04_b[1] = (~(g03_or02[2] | g03_or02[3])); + assign g03_or04_b[2] = (~(g03_or02[4] | g03_or02[5])); + assign g03_or04_b[3] = (~(g03_or02[6] | g03_or02[7])); + + assign g04_or04_b[0] = (~(g04_or02[0] | g04_or02[1])); + assign g04_or04_b[1] = (~(g04_or02[2] | g04_or02[3])); + assign g04_or04_b[2] = (~(g04_or02[4] | g04_or02[5])); + assign g04_or04_b[3] = (~(g04_or02[6] | g04_or02[7])); + + assign g05_or04_b[0] = (~(g05_or02[0] | g05_or02[1])); + assign g05_or04_b[1] = (~(g05_or02[2] | g05_or02[3])); + assign g05_or04_b[2] = (~(g05_or02[4] | g05_or02[5])); + assign g05_or04_b[3] = (~(g05_or02[6] | g05_or02[7])); + + assign g06_or04_b[0] = (~(g06_or02[0] | g06_or02[1])); + assign g06_or04_b[1] = (~(g06_or02[2] | g06_or02[3])); + assign g06_or04_b[2] = (~(g06_or02[4] | g06_or02[5])); + assign g06_or04_b[3] = (~(g06_or02[6] | g06_or02[7])); + + assign g07_or04_b[0] = (~(g07_or02[0] | g07_or02[1])); + assign g07_or04_b[1] = (~(g07_or02[2] | g07_or02[3])); + assign g07_or04_b[2] = (~(g07_or02[4] | g07_or02[5])); + assign g07_or04_b[3] = (~(g07_or02[6] | g07_or02[7])); + + assign g08_or04_b[0] = (~(g08_or02[0] | g08_or02[1])); + assign g08_or04_b[1] = (~(g08_or02[2] | g08_or02[3])); + assign g08_or04_b[2] = (~(g08_or02[4] | g08_or02[5])); + assign g08_or04_b[3] = (~(g08_or02[6] | g08_or02[7])); + + assign g09_or04_b[0] = (~(g09_or02[0] | g09_or02[1])); + assign g09_or04_b[1] = (~(g09_or02[2] | g09_or02[3])); + assign g09_or04_b[2] = (~(g09_or02[4] | g09_or02[5])); + assign g09_or04_b[3] = (~(g09_or02[6] | g09_or02[7])); + + assign g10_or04_b[0] = (~(g10_or02[0] | g10_or02[1])); + assign g10_or04_b[1] = (~(g10_or02[2] | g10_or02[3])); + assign g10_or04_b[2] = (~(g10_or02[4] | g10_or02[5])); + + //===============================================================-- + + assign g00_or08[0] = (~(g00_or04_b[0] & g00_or04_b[1])); + + assign g01_or08[0] = (~(g01_or04_b[0] & g01_or04_b[1])); + assign g01_or08[1] = (~(g01_or04_b[2] & g01_or04_b[3])); + + assign g02_or08[0] = (~(g02_or04_b[0] & g02_or04_b[1])); + assign g02_or08[1] = (~(g02_or04_b[2] & g02_or04_b[3])); + + assign g03_or08[0] = (~(g03_or04_b[0] & g03_or04_b[1])); + assign g03_or08[1] = (~(g03_or04_b[2] & g03_or04_b[3])); + + assign g04_or08[0] = (~(g04_or04_b[0] & g04_or04_b[1])); + assign g04_or08[1] = (~(g04_or04_b[2] & g04_or04_b[3])); + + assign g05_or08[0] = (~(g05_or04_b[0] & g05_or04_b[1])); + assign g05_or08[1] = (~(g05_or04_b[2] & g05_or04_b[3])); + + assign g06_or08[0] = (~(g06_or04_b[0] & g06_or04_b[1])); + assign g06_or08[1] = (~(g06_or04_b[2] & g06_or04_b[3])); + + assign g07_or08[0] = (~(g07_or04_b[0] & g07_or04_b[1])); + assign g07_or08[1] = (~(g07_or04_b[2] & g07_or04_b[3])); + + assign g08_or08[0] = (~(g08_or04_b[0] & g08_or04_b[1])); + assign g08_or08[1] = (~(g08_or04_b[2] & g08_or04_b[3])); + + assign g09_or08[0] = (~(g09_or04_b[0] & g09_or04_b[1])); + assign g09_or08[1] = (~(g09_or04_b[2] & g09_or04_b[3])); + + assign g10_or08[0] = (~(g10_or04_b[0] & g10_or04_b[1])); + assign g10_or08[1] = (~(g10_or04_b[2])); + + //===============================================================-- + + assign g00_or16_b = (~(g00_or08[0])); + assign g01_or16_b = (~(g01_or08[0] | g01_or08[1])); + assign g02_or16_b = (~(g02_or08[0] | g02_or08[1])); + assign g03_or16_b = (~(g03_or08[0] | g03_or08[1])); + assign g04_or16_b = (~(g04_or08[0] | g04_or08[1])); + assign g05_or16_b = (~(g05_or08[0] | g05_or08[1])); + assign g06_or16_b = (~(g06_or08[0] | g06_or08[1])); + assign g07_or16_b = (~(g07_or08[0] | g07_or08[1])); + assign g08_or16_b = (~(g08_or08[0] | g08_or08[1])); + assign g09_or16_b = (~(g09_or08[0] | g09_or08[1])); + assign g10_or16_b = (~(g10_or08[0] | g10_or08[1])); + + //===============================================================-- + + ///////////////////////////////////////////////////////////-- + + assign ex5_or_grp16[0] = (~(g00_or16_b)); //output-- + assign ex5_or_grp16[1] = (~(g01_or16_b)); //output-- + assign ex5_or_grp16[2] = (~(g02_or16_b)); //output-- + assign ex5_or_grp16[3] = (~(g03_or16_b)); //output-- + assign ex5_or_grp16[4] = (~(g04_or16_b)); //output-- + assign ex5_or_grp16[5] = (~(g05_or16_b)); //output-- + assign ex5_or_grp16[6] = (~(g06_or16_b)); //output-- + assign ex5_or_grp16[7] = (~(g07_or16_b)); //output-- + assign ex5_or_grp16[8] = (~(g08_or16_b)); //output-- + assign ex5_or_grp16[9] = (~(g09_or16_b)); //output-- + assign ex5_or_grp16[10] = (~(g10_or16_b)); //output-- + +endmodule diff --git a/dev/verilog/work/fu_nrm_sh.v b/dev/verilog/work/fu_nrm_sh.v new file mode 100755 index 0000000..a1e3218 --- /dev/null +++ b/dev/verilog/work/fu_nrm_sh.v @@ -0,0 +1,1351 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + + `include "tri_a2o.vh" + + +module fu_nrm_sh( + f_lza_ex5_sh_rgt_en, + f_lza_ex5_lza_amt_cp1, + f_lza_ex5_lza_dcd64_cp1, + f_lza_ex5_lza_dcd64_cp2, + f_lza_ex5_lza_dcd64_cp3, + f_add_ex5_res, + ex5_sh2_o, + ex5_sh4_25, + ex5_sh4_54, + ex5_shift_extra_cp1, + ex5_shift_extra_cp2, + ex5_sh5_x_b, + ex5_sh5_y_b +); + //--------- SHIFT CONTROLS ----------------- + input f_lza_ex5_sh_rgt_en; + input [2:7] f_lza_ex5_lza_amt_cp1; + input [0:2] f_lza_ex5_lza_dcd64_cp1; + input [0:1] f_lza_ex5_lza_dcd64_cp2; + input [0:0] f_lza_ex5_lza_dcd64_cp3; + + //--------- SHIFT DATA ----------------- + input [0:162] f_add_ex5_res; + + //-------- SHIFT OUTPUT --------------- + output [26:72] ex5_sh2_o; + output ex5_sh4_25; + output ex5_sh4_54; + output ex5_shift_extra_cp1; + output ex5_shift_extra_cp2; + + output [0:53] ex5_sh5_x_b; + output [0:53] ex5_sh5_y_b; + + // ENTITY + + + parameter tiup = 1'b1; + parameter tidn = 1'b0; + + wire [0:120] ex5_sh1_x_b; + wire [0:99] ex5_sh1_y_b; + wire [0:35] ex5_sh1_u_b; + wire [65:118] ex5_sh1_z_b; + wire [0:72] ex5_sh2_x_b; + wire [0:72] ex5_sh2_y_b; + wire [0:57] ex5_sh3_x_b; + wire [0:57] ex5_sh3_y_b; + wire [0:54] ex5_sh4_x_b; + wire [0:54] ex5_sh4_y_b; + wire ex5_sh4_x_00_b; + wire ex5_sh4_y_00_b; + + wire ex5_shift_extra_cp1_b; + + wire ex5_shift_extra_cp2_b; + wire ex5_shift_extra_cp3_b; + wire ex5_shift_extra_cp4_b; + wire ex5_shift_extra_cp3; + wire ex5_shift_extra_cp4; + wire [0:54] ex5_sh4; + wire [0:57] ex5_sh3; + wire [0:72] ex5_sh2; + wire [0:120] ex5_sh1; + wire [0:2] ex5_shctl_64; + wire [0:1] ex5_shctl_64_cp2; + wire [0:0] ex5_shctl_64_cp3; + wire [0:3] ex5_shctl_16; + wire [0:3] ex5_shctl_04; + wire [0:3] ex5_shctl_01; + wire ex5_shift_extra_10_cp3; + wire ex5_shift_extra_20_cp3_b; + wire ex5_shift_extra_11_cp3; + wire ex5_shift_extra_21_cp3_b; + wire ex5_shift_extra_31_cp3; + wire ex5_shift_extra_10_cp4; + wire ex5_shift_extra_20_cp4_b; + wire ex5_shift_extra_11_cp4; + wire ex5_shift_extra_21_cp4_b; + wire ex5_shift_extra_31_cp4; + wire ex5_shift_extra_00_cp3_b; + wire ex5_shift_extra_00_cp4_b; + + + ////############################################## + //# EX5 logic: shift decode + ////############################################## + + assign ex5_shctl_64[0:2] = f_lza_ex5_lza_dcd64_cp1[0:2]; + assign ex5_shctl_64_cp2[0:1] = f_lza_ex5_lza_dcd64_cp2[0:1]; + assign ex5_shctl_64_cp3[0] = f_lza_ex5_lza_dcd64_cp3[0]; + + assign ex5_shctl_16[0] = (~f_lza_ex5_lza_amt_cp1[2]) & (~f_lza_ex5_lza_amt_cp1[3]); //SH000 + assign ex5_shctl_16[1] = (~f_lza_ex5_lza_amt_cp1[2]) & f_lza_ex5_lza_amt_cp1[3]; //SH016 + assign ex5_shctl_16[2] = f_lza_ex5_lza_amt_cp1[2] & (~f_lza_ex5_lza_amt_cp1[3]); //SH032 + assign ex5_shctl_16[3] = f_lza_ex5_lza_amt_cp1[2] & f_lza_ex5_lza_amt_cp1[3]; //SH048 + + assign ex5_shctl_04[0] = (~f_lza_ex5_lza_amt_cp1[4]) & (~f_lza_ex5_lza_amt_cp1[5]); //SH000 + assign ex5_shctl_04[1] = (~f_lza_ex5_lza_amt_cp1[4]) & f_lza_ex5_lza_amt_cp1[5]; //SH004 + assign ex5_shctl_04[2] = f_lza_ex5_lza_amt_cp1[4] & (~f_lza_ex5_lza_amt_cp1[5]); //SH008 + assign ex5_shctl_04[3] = f_lza_ex5_lza_amt_cp1[4] & f_lza_ex5_lza_amt_cp1[5]; //SH012 + + assign ex5_shctl_01[0] = (~f_lza_ex5_lza_amt_cp1[6]) & (~f_lza_ex5_lza_amt_cp1[7]); //SH000 + assign ex5_shctl_01[1] = (~f_lza_ex5_lza_amt_cp1[6]) & f_lza_ex5_lza_amt_cp1[7]; //SH001 + assign ex5_shctl_01[2] = f_lza_ex5_lza_amt_cp1[6] & (~f_lza_ex5_lza_amt_cp1[7]); //SH002 + assign ex5_shctl_01[3] = f_lza_ex5_lza_amt_cp1[6] & f_lza_ex5_lza_amt_cp1[7]; //SH003 + + ////############################################## + //# EX5 logic: shifting + ////############################################## + ////## big shifts first (come sooner from LZA, + ////## when shift amount is [0] we need to start out with a "dummy" leading bit to sacrifice for shift_extra + //// ex5_sh1(0 to 54) <= + //// ( ( tidn & f_add_ex5_res( 0 to 53) ) and (0 to 54 => ex5_shctl_64(0)) ) or --SH000 + //// ( ( f_add_ex5_res( 63 to 117) ) and (0 to 54 => ex5_shctl_64(1)) ) or --SH064 + //// ( ( f_add_ex5_res(127 to 162) & (36 to 54 => tidn) ) and (0 to 54 => ex5_shctl_64(2)) ) ; --SH128 + //// + //// ex5_sh1(55 to 64) <= + //// ( ( f_add_ex5_res( 54 to 63 ) ) and (55 to 64 => ex5_shctl_64_cp2(0)) ) or --SH000 + //// ( ( f_add_ex5_res(118 to 127) ) and (55 to 64 => ex5_shctl_64_cp2(1)) ) ; --SH064 + //// + //// ex5_sh1(65 to 108) <= + //// ( ( f_add_ex5_res( 64 to 107) ) and (65 to 108 => ex5_shctl_64_cp2(0)) ) or --SH000 + //// ( ( f_add_ex5_res(128 to 162) & (100 to 108=> tidn) ) and (65 to 108 => ex5_shctl_64_cp2(1)) ) or --SH064 + //// ( ( f_add_ex5_res(0 to 43) ) and (65 to 108 => f_lza_ex5_sh_rgt_en) ) ; --SHR64 + //// + //// ex5_sh1(109 to 118) <= + //// ( ( f_add_ex5_res(108 to 117) ) and (109 to 118 => ex5_shctl_64_cp3(0)) ) or --SH000 + //// ( ( f_add_ex5_res(44 to 53) ) and (109 to 118 => f_lza_ex5_sh_rgt_en) ) ; --SHR64 + //// + //// ex5_sh1(119 to 120) <= + //// ( ( f_add_ex5_res(118 to 119) ) and (119 to 120 => ex5_shctl_64_cp3(0)) ); --SH000 + //// + //// -- sh2 ony needs to be 0:69 , however since sp & dp group16s would be off by 2 + //// -- it saves logic in sticky calc to keep 2 more bits + //// -- and use the same sticky or group 16s for sp/dp. + //// -- 70:71 are always part of dp sticky + //// + //// ex5_sh2(0 to 72) <= -- (0 to 69) -- shift by multiples of 16 + //// ( ex5_sh1( 0 to 72) and (0 to 72 => ex5_shctl_16(0) ) ) or --SH00 + //// ( ex5_sh1(16 to 88) and (0 to 72 => ex5_shctl_16(1) ) ) or --SH16 + //// ( ex5_sh1(32 to 104) and (0 to 72 => ex5_shctl_16(2) ) ) or --SH32 + //// ( ex5_sh1(48 to 120) and (0 to 72 => ex5_shctl_16(3) ) ) ; --SH48 + + assign ex5_sh2_o[26:72] = ex5_sh2[26:72]; // for sticky bit + + //// ex5_sh3(0 to 57) <= -- shift by multiples of 4 + //// ( ex5_sh2( 0 to 57) and (0 to 57 => ex5_shctl_04(0) ) ) or --SH00 + //// ( ex5_sh2( 4 to 61) and (0 to 57 => ex5_shctl_04(1) ) ) or --SH04 + //// ( ex5_sh2( 8 to 65) and (0 to 57 => ex5_shctl_04(2) ) ) or --SH08 + //// ( ex5_sh2(12 to 69) and (0 to 57 => ex5_shctl_04(3) ) ) ; --SH12 + //// + //// ex5_sh4(0 to 54) <= -- shift by multiples of 1 + //// ( ex5_sh3(0 to 54) and (0 to 54 => ex5_shctl_01(0) ) ) or --SH00 + //// ( ex5_sh3(1 to 55) and (0 to 54 => ex5_shctl_01(1) ) ) or --SH01 + //// ( ex5_sh3(2 to 56) and (0 to 54 => ex5_shctl_01(2) ) ) or --SH02 + //// ( ex5_sh3(3 to 57) and (0 to 54 => ex5_shctl_01(3) ) ) ; --SH03 + + assign ex5_sh4_25 = ex5_sh4[25]; // for sticky bit + assign ex5_sh4_54 = ex5_sh4[54]; // for sticky bit + + //// ex5_nrm_res(0 to 53) <= -- [53] is for the DP guard bit + //// ( ex5_sh4(0 to 53) and (0 to 53 => not ex5_shift_extra) ) or + //// ( ex5_sh4(1 to 54) and (0 to 53 => ex5_shift_extra) ) ; + + //------------------------------------------------------- + assign ex5_sh1_x_b[0] = (~(tidn & ex5_shctl_64[0])); + assign ex5_sh1_x_b[1] = (~(f_add_ex5_res[0] & ex5_shctl_64[0])); + assign ex5_sh1_x_b[2] = (~(f_add_ex5_res[1] & ex5_shctl_64[0])); + assign ex5_sh1_x_b[3] = (~(f_add_ex5_res[2] & ex5_shctl_64[0])); + assign ex5_sh1_x_b[4] = (~(f_add_ex5_res[3] & ex5_shctl_64[0])); + assign ex5_sh1_x_b[5] = (~(f_add_ex5_res[4] & ex5_shctl_64[0])); + assign ex5_sh1_x_b[6] = (~(f_add_ex5_res[5] & ex5_shctl_64[0])); + assign ex5_sh1_x_b[7] = (~(f_add_ex5_res[6] & ex5_shctl_64[0])); + assign ex5_sh1_x_b[8] = (~(f_add_ex5_res[7] & ex5_shctl_64[0])); + assign ex5_sh1_x_b[9] = (~(f_add_ex5_res[8] & ex5_shctl_64[0])); + assign ex5_sh1_x_b[10] = (~(f_add_ex5_res[9] & ex5_shctl_64[0])); + assign ex5_sh1_x_b[11] = (~(f_add_ex5_res[10] & ex5_shctl_64[0])); + assign ex5_sh1_x_b[12] = (~(f_add_ex5_res[11] & ex5_shctl_64[0])); + assign ex5_sh1_x_b[13] = (~(f_add_ex5_res[12] & ex5_shctl_64[0])); + assign ex5_sh1_x_b[14] = (~(f_add_ex5_res[13] & ex5_shctl_64[0])); + assign ex5_sh1_x_b[15] = (~(f_add_ex5_res[14] & ex5_shctl_64[0])); + assign ex5_sh1_x_b[16] = (~(f_add_ex5_res[15] & ex5_shctl_64[0])); + assign ex5_sh1_x_b[17] = (~(f_add_ex5_res[16] & ex5_shctl_64[0])); + assign ex5_sh1_x_b[18] = (~(f_add_ex5_res[17] & ex5_shctl_64[0])); + assign ex5_sh1_x_b[19] = (~(f_add_ex5_res[18] & ex5_shctl_64[0])); + assign ex5_sh1_x_b[20] = (~(f_add_ex5_res[19] & ex5_shctl_64[0])); + assign ex5_sh1_x_b[21] = (~(f_add_ex5_res[20] & ex5_shctl_64[0])); + assign ex5_sh1_x_b[22] = (~(f_add_ex5_res[21] & ex5_shctl_64[0])); + assign ex5_sh1_x_b[23] = (~(f_add_ex5_res[22] & ex5_shctl_64[0])); + assign ex5_sh1_x_b[24] = (~(f_add_ex5_res[23] & ex5_shctl_64[0])); + assign ex5_sh1_x_b[25] = (~(f_add_ex5_res[24] & ex5_shctl_64[0])); + assign ex5_sh1_x_b[26] = (~(f_add_ex5_res[25] & ex5_shctl_64[0])); + assign ex5_sh1_x_b[27] = (~(f_add_ex5_res[26] & ex5_shctl_64[0])); + assign ex5_sh1_x_b[28] = (~(f_add_ex5_res[27] & ex5_shctl_64[0])); + assign ex5_sh1_x_b[29] = (~(f_add_ex5_res[28] & ex5_shctl_64[0])); + assign ex5_sh1_x_b[30] = (~(f_add_ex5_res[29] & ex5_shctl_64[0])); + assign ex5_sh1_x_b[31] = (~(f_add_ex5_res[30] & ex5_shctl_64[0])); + assign ex5_sh1_x_b[32] = (~(f_add_ex5_res[31] & ex5_shctl_64[0])); + assign ex5_sh1_x_b[33] = (~(f_add_ex5_res[32] & ex5_shctl_64[0])); + assign ex5_sh1_x_b[34] = (~(f_add_ex5_res[33] & ex5_shctl_64[0])); + assign ex5_sh1_x_b[35] = (~(f_add_ex5_res[34] & ex5_shctl_64[0])); + assign ex5_sh1_x_b[36] = (~(f_add_ex5_res[35] & ex5_shctl_64[0])); + assign ex5_sh1_x_b[37] = (~(f_add_ex5_res[36] & ex5_shctl_64[0])); + assign ex5_sh1_x_b[38] = (~(f_add_ex5_res[37] & ex5_shctl_64[0])); + assign ex5_sh1_x_b[39] = (~(f_add_ex5_res[38] & ex5_shctl_64[0])); + assign ex5_sh1_x_b[40] = (~(f_add_ex5_res[39] & ex5_shctl_64_cp2[0])); //-------- + assign ex5_sh1_x_b[41] = (~(f_add_ex5_res[40] & ex5_shctl_64_cp2[0])); + assign ex5_sh1_x_b[42] = (~(f_add_ex5_res[41] & ex5_shctl_64_cp2[0])); + assign ex5_sh1_x_b[43] = (~(f_add_ex5_res[42] & ex5_shctl_64_cp2[0])); + assign ex5_sh1_x_b[44] = (~(f_add_ex5_res[43] & ex5_shctl_64_cp2[0])); + assign ex5_sh1_x_b[45] = (~(f_add_ex5_res[44] & ex5_shctl_64_cp2[0])); + assign ex5_sh1_x_b[46] = (~(f_add_ex5_res[45] & ex5_shctl_64_cp2[0])); + assign ex5_sh1_x_b[47] = (~(f_add_ex5_res[46] & ex5_shctl_64_cp2[0])); + assign ex5_sh1_x_b[48] = (~(f_add_ex5_res[47] & ex5_shctl_64_cp2[0])); + assign ex5_sh1_x_b[49] = (~(f_add_ex5_res[48] & ex5_shctl_64_cp2[0])); + assign ex5_sh1_x_b[50] = (~(f_add_ex5_res[49] & ex5_shctl_64_cp2[0])); + assign ex5_sh1_x_b[51] = (~(f_add_ex5_res[50] & ex5_shctl_64_cp2[0])); + assign ex5_sh1_x_b[52] = (~(f_add_ex5_res[51] & ex5_shctl_64_cp2[0])); + assign ex5_sh1_x_b[53] = (~(f_add_ex5_res[52] & ex5_shctl_64_cp2[0])); + assign ex5_sh1_x_b[54] = (~(f_add_ex5_res[53] & ex5_shctl_64_cp2[0])); + assign ex5_sh1_x_b[55] = (~(f_add_ex5_res[54] & ex5_shctl_64_cp2[0])); + assign ex5_sh1_x_b[56] = (~(f_add_ex5_res[55] & ex5_shctl_64_cp2[0])); + assign ex5_sh1_x_b[57] = (~(f_add_ex5_res[56] & ex5_shctl_64_cp2[0])); + assign ex5_sh1_x_b[58] = (~(f_add_ex5_res[57] & ex5_shctl_64_cp2[0])); + assign ex5_sh1_x_b[59] = (~(f_add_ex5_res[58] & ex5_shctl_64_cp2[0])); + assign ex5_sh1_x_b[60] = (~(f_add_ex5_res[59] & ex5_shctl_64_cp2[0])); + assign ex5_sh1_x_b[61] = (~(f_add_ex5_res[60] & ex5_shctl_64_cp2[0])); + assign ex5_sh1_x_b[62] = (~(f_add_ex5_res[61] & ex5_shctl_64_cp2[0])); + assign ex5_sh1_x_b[63] = (~(f_add_ex5_res[62] & ex5_shctl_64_cp2[0])); + assign ex5_sh1_x_b[64] = (~(f_add_ex5_res[63] & ex5_shctl_64_cp2[0])); + assign ex5_sh1_x_b[65] = (~(f_add_ex5_res[64] & ex5_shctl_64_cp2[0])); + assign ex5_sh1_x_b[66] = (~(f_add_ex5_res[65] & ex5_shctl_64_cp2[0])); + assign ex5_sh1_x_b[67] = (~(f_add_ex5_res[66] & ex5_shctl_64_cp2[0])); + assign ex5_sh1_x_b[68] = (~(f_add_ex5_res[67] & ex5_shctl_64_cp2[0])); + assign ex5_sh1_x_b[69] = (~(f_add_ex5_res[68] & ex5_shctl_64_cp2[0])); + assign ex5_sh1_x_b[70] = (~(f_add_ex5_res[69] & ex5_shctl_64_cp2[0])); + assign ex5_sh1_x_b[71] = (~(f_add_ex5_res[70] & ex5_shctl_64_cp2[0])); + assign ex5_sh1_x_b[72] = (~(f_add_ex5_res[71] & ex5_shctl_64_cp2[0])); + assign ex5_sh1_x_b[73] = (~(f_add_ex5_res[72] & ex5_shctl_64_cp2[0])); + assign ex5_sh1_x_b[74] = (~(f_add_ex5_res[73] & ex5_shctl_64_cp2[0])); + assign ex5_sh1_x_b[75] = (~(f_add_ex5_res[74] & ex5_shctl_64_cp2[0])); + assign ex5_sh1_x_b[76] = (~(f_add_ex5_res[75] & ex5_shctl_64_cp2[0])); + assign ex5_sh1_x_b[77] = (~(f_add_ex5_res[76] & ex5_shctl_64_cp2[0])); + assign ex5_sh1_x_b[78] = (~(f_add_ex5_res[77] & ex5_shctl_64_cp2[0])); + assign ex5_sh1_x_b[79] = (~(f_add_ex5_res[78] & ex5_shctl_64_cp2[0])); + assign ex5_sh1_x_b[80] = (~(f_add_ex5_res[79] & ex5_shctl_64_cp2[0])); + assign ex5_sh1_x_b[81] = (~(f_add_ex5_res[80] & ex5_shctl_64_cp3[0])); //---- + assign ex5_sh1_x_b[82] = (~(f_add_ex5_res[81] & ex5_shctl_64_cp3[0])); + assign ex5_sh1_x_b[83] = (~(f_add_ex5_res[82] & ex5_shctl_64_cp3[0])); + assign ex5_sh1_x_b[84] = (~(f_add_ex5_res[83] & ex5_shctl_64_cp3[0])); + assign ex5_sh1_x_b[85] = (~(f_add_ex5_res[84] & ex5_shctl_64_cp3[0])); + assign ex5_sh1_x_b[86] = (~(f_add_ex5_res[85] & ex5_shctl_64_cp3[0])); + assign ex5_sh1_x_b[87] = (~(f_add_ex5_res[86] & ex5_shctl_64_cp3[0])); + assign ex5_sh1_x_b[88] = (~(f_add_ex5_res[87] & ex5_shctl_64_cp3[0])); + assign ex5_sh1_x_b[89] = (~(f_add_ex5_res[88] & ex5_shctl_64_cp3[0])); + assign ex5_sh1_x_b[90] = (~(f_add_ex5_res[89] & ex5_shctl_64_cp3[0])); + assign ex5_sh1_x_b[91] = (~(f_add_ex5_res[90] & ex5_shctl_64_cp3[0])); + assign ex5_sh1_x_b[92] = (~(f_add_ex5_res[91] & ex5_shctl_64_cp3[0])); + assign ex5_sh1_x_b[93] = (~(f_add_ex5_res[92] & ex5_shctl_64_cp3[0])); + assign ex5_sh1_x_b[94] = (~(f_add_ex5_res[93] & ex5_shctl_64_cp3[0])); + assign ex5_sh1_x_b[95] = (~(f_add_ex5_res[94] & ex5_shctl_64_cp3[0])); + assign ex5_sh1_x_b[96] = (~(f_add_ex5_res[95] & ex5_shctl_64_cp3[0])); + assign ex5_sh1_x_b[97] = (~(f_add_ex5_res[96] & ex5_shctl_64_cp3[0])); + assign ex5_sh1_x_b[98] = (~(f_add_ex5_res[97] & ex5_shctl_64_cp3[0])); + assign ex5_sh1_x_b[99] = (~(f_add_ex5_res[98] & ex5_shctl_64_cp3[0])); + assign ex5_sh1_x_b[100] = (~(f_add_ex5_res[99] & ex5_shctl_64_cp3[0])); + assign ex5_sh1_x_b[101] = (~(f_add_ex5_res[100] & ex5_shctl_64_cp3[0])); + assign ex5_sh1_x_b[102] = (~(f_add_ex5_res[101] & ex5_shctl_64_cp3[0])); + assign ex5_sh1_x_b[103] = (~(f_add_ex5_res[102] & ex5_shctl_64_cp3[0])); + assign ex5_sh1_x_b[104] = (~(f_add_ex5_res[103] & ex5_shctl_64_cp3[0])); + assign ex5_sh1_x_b[105] = (~(f_add_ex5_res[104] & ex5_shctl_64_cp3[0])); + assign ex5_sh1_x_b[106] = (~(f_add_ex5_res[105] & ex5_shctl_64_cp3[0])); + assign ex5_sh1_x_b[107] = (~(f_add_ex5_res[106] & ex5_shctl_64_cp3[0])); + assign ex5_sh1_x_b[108] = (~(f_add_ex5_res[107] & ex5_shctl_64_cp3[0])); + assign ex5_sh1_x_b[109] = (~(f_add_ex5_res[108] & ex5_shctl_64_cp3[0])); + assign ex5_sh1_x_b[110] = (~(f_add_ex5_res[109] & ex5_shctl_64_cp3[0])); + assign ex5_sh1_x_b[111] = (~(f_add_ex5_res[110] & ex5_shctl_64_cp3[0])); + assign ex5_sh1_x_b[112] = (~(f_add_ex5_res[111] & ex5_shctl_64_cp3[0])); + assign ex5_sh1_x_b[113] = (~(f_add_ex5_res[112] & ex5_shctl_64_cp3[0])); + assign ex5_sh1_x_b[114] = (~(f_add_ex5_res[113] & ex5_shctl_64_cp3[0])); + assign ex5_sh1_x_b[115] = (~(f_add_ex5_res[114] & ex5_shctl_64_cp3[0])); + assign ex5_sh1_x_b[116] = (~(f_add_ex5_res[115] & ex5_shctl_64_cp3[0])); + assign ex5_sh1_x_b[117] = (~(f_add_ex5_res[116] & ex5_shctl_64_cp3[0])); + assign ex5_sh1_x_b[118] = (~(f_add_ex5_res[117] & ex5_shctl_64_cp3[0])); + assign ex5_sh1_x_b[119] = (~(f_add_ex5_res[118] & ex5_shctl_64_cp3[0])); + assign ex5_sh1_x_b[120] = (~(f_add_ex5_res[119] & ex5_shctl_64_cp3[0])); + + assign ex5_sh1_y_b[0] = (~(f_add_ex5_res[63] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[1] = (~(f_add_ex5_res[64] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[2] = (~(f_add_ex5_res[65] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[3] = (~(f_add_ex5_res[66] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[4] = (~(f_add_ex5_res[67] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[5] = (~(f_add_ex5_res[68] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[6] = (~(f_add_ex5_res[69] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[7] = (~(f_add_ex5_res[70] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[8] = (~(f_add_ex5_res[71] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[9] = (~(f_add_ex5_res[72] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[10] = (~(f_add_ex5_res[73] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[11] = (~(f_add_ex5_res[74] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[12] = (~(f_add_ex5_res[75] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[13] = (~(f_add_ex5_res[76] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[14] = (~(f_add_ex5_res[77] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[15] = (~(f_add_ex5_res[78] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[16] = (~(f_add_ex5_res[79] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[17] = (~(f_add_ex5_res[80] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[18] = (~(f_add_ex5_res[81] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[19] = (~(f_add_ex5_res[82] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[20] = (~(f_add_ex5_res[83] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[21] = (~(f_add_ex5_res[84] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[22] = (~(f_add_ex5_res[85] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[23] = (~(f_add_ex5_res[86] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[24] = (~(f_add_ex5_res[87] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[25] = (~(f_add_ex5_res[88] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[26] = (~(f_add_ex5_res[89] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[27] = (~(f_add_ex5_res[90] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[28] = (~(f_add_ex5_res[91] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[29] = (~(f_add_ex5_res[92] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[30] = (~(f_add_ex5_res[93] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[31] = (~(f_add_ex5_res[94] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[32] = (~(f_add_ex5_res[95] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[33] = (~(f_add_ex5_res[96] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[34] = (~(f_add_ex5_res[97] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[35] = (~(f_add_ex5_res[98] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[36] = (~(f_add_ex5_res[99] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[37] = (~(f_add_ex5_res[100] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[38] = (~(f_add_ex5_res[101] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[39] = (~(f_add_ex5_res[102] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[40] = (~(f_add_ex5_res[103] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[41] = (~(f_add_ex5_res[104] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[42] = (~(f_add_ex5_res[105] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[43] = (~(f_add_ex5_res[106] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[44] = (~(f_add_ex5_res[107] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[45] = (~(f_add_ex5_res[108] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[46] = (~(f_add_ex5_res[109] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[47] = (~(f_add_ex5_res[110] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[48] = (~(f_add_ex5_res[111] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[49] = (~(f_add_ex5_res[112] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[50] = (~(f_add_ex5_res[113] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[51] = (~(f_add_ex5_res[114] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[52] = (~(f_add_ex5_res[115] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[53] = (~(f_add_ex5_res[116] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[54] = (~(f_add_ex5_res[117] & ex5_shctl_64[1])); + assign ex5_sh1_y_b[55] = (~(f_add_ex5_res[118] & ex5_shctl_64_cp2[1])); + assign ex5_sh1_y_b[56] = (~(f_add_ex5_res[119] & ex5_shctl_64_cp2[1])); + assign ex5_sh1_y_b[57] = (~(f_add_ex5_res[120] & ex5_shctl_64_cp2[1])); + assign ex5_sh1_y_b[58] = (~(f_add_ex5_res[121] & ex5_shctl_64_cp2[1])); + assign ex5_sh1_y_b[59] = (~(f_add_ex5_res[122] & ex5_shctl_64_cp2[1])); + assign ex5_sh1_y_b[60] = (~(f_add_ex5_res[123] & ex5_shctl_64_cp2[1])); + assign ex5_sh1_y_b[61] = (~(f_add_ex5_res[124] & ex5_shctl_64_cp2[1])); + assign ex5_sh1_y_b[62] = (~(f_add_ex5_res[125] & ex5_shctl_64_cp2[1])); + assign ex5_sh1_y_b[63] = (~(f_add_ex5_res[126] & ex5_shctl_64_cp2[1])); + assign ex5_sh1_y_b[64] = (~(f_add_ex5_res[127] & ex5_shctl_64_cp2[1])); + assign ex5_sh1_y_b[65] = (~(f_add_ex5_res[128] & ex5_shctl_64_cp2[1])); + assign ex5_sh1_y_b[66] = (~(f_add_ex5_res[129] & ex5_shctl_64_cp2[1])); + assign ex5_sh1_y_b[67] = (~(f_add_ex5_res[130] & ex5_shctl_64_cp2[1])); + assign ex5_sh1_y_b[68] = (~(f_add_ex5_res[131] & ex5_shctl_64_cp2[1])); + assign ex5_sh1_y_b[69] = (~(f_add_ex5_res[132] & ex5_shctl_64_cp2[1])); + assign ex5_sh1_y_b[70] = (~(f_add_ex5_res[133] & ex5_shctl_64_cp2[1])); + assign ex5_sh1_y_b[71] = (~(f_add_ex5_res[134] & ex5_shctl_64_cp2[1])); + assign ex5_sh1_y_b[72] = (~(f_add_ex5_res[135] & ex5_shctl_64_cp2[1])); + assign ex5_sh1_y_b[73] = (~(f_add_ex5_res[136] & ex5_shctl_64_cp2[1])); + assign ex5_sh1_y_b[74] = (~(f_add_ex5_res[137] & ex5_shctl_64_cp2[1])); + assign ex5_sh1_y_b[75] = (~(f_add_ex5_res[138] & ex5_shctl_64_cp2[1])); + assign ex5_sh1_y_b[76] = (~(f_add_ex5_res[139] & ex5_shctl_64_cp2[1])); + assign ex5_sh1_y_b[77] = (~(f_add_ex5_res[140] & ex5_shctl_64_cp2[1])); + assign ex5_sh1_y_b[78] = (~(f_add_ex5_res[141] & ex5_shctl_64_cp2[1])); + assign ex5_sh1_y_b[79] = (~(f_add_ex5_res[142] & ex5_shctl_64_cp2[1])); + assign ex5_sh1_y_b[80] = (~(f_add_ex5_res[143] & ex5_shctl_64_cp2[1])); + assign ex5_sh1_y_b[81] = (~(f_add_ex5_res[144] & ex5_shctl_64_cp2[1])); + assign ex5_sh1_y_b[82] = (~(f_add_ex5_res[145] & ex5_shctl_64_cp2[1])); + assign ex5_sh1_y_b[83] = (~(f_add_ex5_res[146] & ex5_shctl_64_cp2[1])); + assign ex5_sh1_y_b[84] = (~(f_add_ex5_res[147] & ex5_shctl_64_cp2[1])); + assign ex5_sh1_y_b[85] = (~(f_add_ex5_res[148] & ex5_shctl_64_cp2[1])); + assign ex5_sh1_y_b[86] = (~(f_add_ex5_res[149] & ex5_shctl_64_cp2[1])); + assign ex5_sh1_y_b[87] = (~(f_add_ex5_res[150] & ex5_shctl_64_cp2[1])); + assign ex5_sh1_y_b[88] = (~(f_add_ex5_res[151] & ex5_shctl_64_cp2[1])); + assign ex5_sh1_y_b[89] = (~(f_add_ex5_res[152] & ex5_shctl_64_cp2[1])); + assign ex5_sh1_y_b[90] = (~(f_add_ex5_res[153] & ex5_shctl_64_cp2[1])); + assign ex5_sh1_y_b[91] = (~(f_add_ex5_res[154] & ex5_shctl_64_cp2[1])); + assign ex5_sh1_y_b[92] = (~(f_add_ex5_res[155] & ex5_shctl_64_cp2[1])); + assign ex5_sh1_y_b[93] = (~(f_add_ex5_res[156] & ex5_shctl_64_cp2[1])); + assign ex5_sh1_y_b[94] = (~(f_add_ex5_res[157] & ex5_shctl_64_cp2[1])); + assign ex5_sh1_y_b[95] = (~(f_add_ex5_res[158] & ex5_shctl_64_cp2[1])); + assign ex5_sh1_y_b[96] = (~(f_add_ex5_res[159] & ex5_shctl_64_cp2[1])); + assign ex5_sh1_y_b[97] = (~(f_add_ex5_res[160] & ex5_shctl_64_cp2[1])); + assign ex5_sh1_y_b[98] = (~(f_add_ex5_res[161] & ex5_shctl_64_cp2[1])); + assign ex5_sh1_y_b[99] = (~(f_add_ex5_res[162] & ex5_shctl_64_cp2[1])); + + assign ex5_sh1_u_b[0] = (~(f_add_ex5_res[127] & ex5_shctl_64[2])); + assign ex5_sh1_u_b[1] = (~(f_add_ex5_res[128] & ex5_shctl_64[2])); + assign ex5_sh1_u_b[2] = (~(f_add_ex5_res[129] & ex5_shctl_64[2])); + assign ex5_sh1_u_b[3] = (~(f_add_ex5_res[130] & ex5_shctl_64[2])); + assign ex5_sh1_u_b[4] = (~(f_add_ex5_res[131] & ex5_shctl_64[2])); + assign ex5_sh1_u_b[5] = (~(f_add_ex5_res[132] & ex5_shctl_64[2])); + assign ex5_sh1_u_b[6] = (~(f_add_ex5_res[133] & ex5_shctl_64[2])); + assign ex5_sh1_u_b[7] = (~(f_add_ex5_res[134] & ex5_shctl_64[2])); + assign ex5_sh1_u_b[8] = (~(f_add_ex5_res[135] & ex5_shctl_64[2])); + assign ex5_sh1_u_b[9] = (~(f_add_ex5_res[136] & ex5_shctl_64[2])); + assign ex5_sh1_u_b[10] = (~(f_add_ex5_res[137] & ex5_shctl_64[2])); + assign ex5_sh1_u_b[11] = (~(f_add_ex5_res[138] & ex5_shctl_64[2])); + assign ex5_sh1_u_b[12] = (~(f_add_ex5_res[139] & ex5_shctl_64[2])); + assign ex5_sh1_u_b[13] = (~(f_add_ex5_res[140] & ex5_shctl_64[2])); + assign ex5_sh1_u_b[14] = (~(f_add_ex5_res[141] & ex5_shctl_64[2])); + assign ex5_sh1_u_b[15] = (~(f_add_ex5_res[142] & ex5_shctl_64[2])); + assign ex5_sh1_u_b[16] = (~(f_add_ex5_res[143] & ex5_shctl_64[2])); + assign ex5_sh1_u_b[17] = (~(f_add_ex5_res[144] & ex5_shctl_64[2])); + assign ex5_sh1_u_b[18] = (~(f_add_ex5_res[145] & ex5_shctl_64[2])); + assign ex5_sh1_u_b[19] = (~(f_add_ex5_res[146] & ex5_shctl_64[2])); + assign ex5_sh1_u_b[20] = (~(f_add_ex5_res[147] & ex5_shctl_64[2])); + assign ex5_sh1_u_b[21] = (~(f_add_ex5_res[148] & ex5_shctl_64[2])); + assign ex5_sh1_u_b[22] = (~(f_add_ex5_res[149] & ex5_shctl_64[2])); + assign ex5_sh1_u_b[23] = (~(f_add_ex5_res[150] & ex5_shctl_64[2])); + assign ex5_sh1_u_b[24] = (~(f_add_ex5_res[151] & ex5_shctl_64[2])); + assign ex5_sh1_u_b[25] = (~(f_add_ex5_res[152] & ex5_shctl_64[2])); + assign ex5_sh1_u_b[26] = (~(f_add_ex5_res[153] & ex5_shctl_64[2])); + assign ex5_sh1_u_b[27] = (~(f_add_ex5_res[154] & ex5_shctl_64[2])); + assign ex5_sh1_u_b[28] = (~(f_add_ex5_res[155] & ex5_shctl_64[2])); + assign ex5_sh1_u_b[29] = (~(f_add_ex5_res[156] & ex5_shctl_64[2])); + assign ex5_sh1_u_b[30] = (~(f_add_ex5_res[157] & ex5_shctl_64[2])); + assign ex5_sh1_u_b[31] = (~(f_add_ex5_res[158] & ex5_shctl_64[2])); + assign ex5_sh1_u_b[32] = (~(f_add_ex5_res[159] & ex5_shctl_64[2])); + assign ex5_sh1_u_b[33] = (~(f_add_ex5_res[160] & ex5_shctl_64[2])); + assign ex5_sh1_u_b[34] = (~(f_add_ex5_res[161] & ex5_shctl_64[2])); + assign ex5_sh1_u_b[35] = (~(f_add_ex5_res[162] & ex5_shctl_64[2])); + + assign ex5_sh1_z_b[65] = (~(f_add_ex5_res[0] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[66] = (~(f_add_ex5_res[1] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[67] = (~(f_add_ex5_res[2] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[68] = (~(f_add_ex5_res[3] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[69] = (~(f_add_ex5_res[4] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[70] = (~(f_add_ex5_res[5] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[71] = (~(f_add_ex5_res[6] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[72] = (~(f_add_ex5_res[7] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[73] = (~(f_add_ex5_res[8] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[74] = (~(f_add_ex5_res[9] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[75] = (~(f_add_ex5_res[10] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[76] = (~(f_add_ex5_res[11] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[77] = (~(f_add_ex5_res[12] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[78] = (~(f_add_ex5_res[13] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[79] = (~(f_add_ex5_res[14] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[80] = (~(f_add_ex5_res[15] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[81] = (~(f_add_ex5_res[16] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[82] = (~(f_add_ex5_res[17] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[83] = (~(f_add_ex5_res[18] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[84] = (~(f_add_ex5_res[19] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[85] = (~(f_add_ex5_res[20] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[86] = (~(f_add_ex5_res[21] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[87] = (~(f_add_ex5_res[22] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[88] = (~(f_add_ex5_res[23] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[89] = (~(f_add_ex5_res[24] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[90] = (~(f_add_ex5_res[25] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[91] = (~(f_add_ex5_res[26] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[92] = (~(f_add_ex5_res[27] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[93] = (~(f_add_ex5_res[28] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[94] = (~(f_add_ex5_res[29] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[95] = (~(f_add_ex5_res[30] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[96] = (~(f_add_ex5_res[31] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[97] = (~(f_add_ex5_res[32] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[98] = (~(f_add_ex5_res[33] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[99] = (~(f_add_ex5_res[34] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[100] = (~(f_add_ex5_res[35] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[101] = (~(f_add_ex5_res[36] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[102] = (~(f_add_ex5_res[37] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[103] = (~(f_add_ex5_res[38] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[104] = (~(f_add_ex5_res[39] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[105] = (~(f_add_ex5_res[40] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[106] = (~(f_add_ex5_res[41] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[107] = (~(f_add_ex5_res[42] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[108] = (~(f_add_ex5_res[43] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[109] = (~(f_add_ex5_res[44] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[110] = (~(f_add_ex5_res[45] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[111] = (~(f_add_ex5_res[46] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[112] = (~(f_add_ex5_res[47] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[113] = (~(f_add_ex5_res[48] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[114] = (~(f_add_ex5_res[49] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[115] = (~(f_add_ex5_res[50] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[116] = (~(f_add_ex5_res[51] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[117] = (~(f_add_ex5_res[52] & f_lza_ex5_sh_rgt_en)); + assign ex5_sh1_z_b[118] = (~(f_add_ex5_res[53] & f_lza_ex5_sh_rgt_en)); + + assign ex5_sh1[0] = (~(ex5_sh1_x_b[0] & ex5_sh1_y_b[0] & ex5_sh1_u_b[0])); + assign ex5_sh1[1] = (~(ex5_sh1_x_b[1] & ex5_sh1_y_b[1] & ex5_sh1_u_b[1])); + assign ex5_sh1[2] = (~(ex5_sh1_x_b[2] & ex5_sh1_y_b[2] & ex5_sh1_u_b[2])); + assign ex5_sh1[3] = (~(ex5_sh1_x_b[3] & ex5_sh1_y_b[3] & ex5_sh1_u_b[3])); + assign ex5_sh1[4] = (~(ex5_sh1_x_b[4] & ex5_sh1_y_b[4] & ex5_sh1_u_b[4])); + assign ex5_sh1[5] = (~(ex5_sh1_x_b[5] & ex5_sh1_y_b[5] & ex5_sh1_u_b[5])); + assign ex5_sh1[6] = (~(ex5_sh1_x_b[6] & ex5_sh1_y_b[6] & ex5_sh1_u_b[6])); + assign ex5_sh1[7] = (~(ex5_sh1_x_b[7] & ex5_sh1_y_b[7] & ex5_sh1_u_b[7])); + assign ex5_sh1[8] = (~(ex5_sh1_x_b[8] & ex5_sh1_y_b[8] & ex5_sh1_u_b[8])); + assign ex5_sh1[9] = (~(ex5_sh1_x_b[9] & ex5_sh1_y_b[9] & ex5_sh1_u_b[9])); + assign ex5_sh1[10] = (~(ex5_sh1_x_b[10] & ex5_sh1_y_b[10] & ex5_sh1_u_b[10])); + assign ex5_sh1[11] = (~(ex5_sh1_x_b[11] & ex5_sh1_y_b[11] & ex5_sh1_u_b[11])); + assign ex5_sh1[12] = (~(ex5_sh1_x_b[12] & ex5_sh1_y_b[12] & ex5_sh1_u_b[12])); + assign ex5_sh1[13] = (~(ex5_sh1_x_b[13] & ex5_sh1_y_b[13] & ex5_sh1_u_b[13])); + assign ex5_sh1[14] = (~(ex5_sh1_x_b[14] & ex5_sh1_y_b[14] & ex5_sh1_u_b[14])); + assign ex5_sh1[15] = (~(ex5_sh1_x_b[15] & ex5_sh1_y_b[15] & ex5_sh1_u_b[15])); + assign ex5_sh1[16] = (~(ex5_sh1_x_b[16] & ex5_sh1_y_b[16] & ex5_sh1_u_b[16])); + assign ex5_sh1[17] = (~(ex5_sh1_x_b[17] & ex5_sh1_y_b[17] & ex5_sh1_u_b[17])); + assign ex5_sh1[18] = (~(ex5_sh1_x_b[18] & ex5_sh1_y_b[18] & ex5_sh1_u_b[18])); + assign ex5_sh1[19] = (~(ex5_sh1_x_b[19] & ex5_sh1_y_b[19] & ex5_sh1_u_b[19])); + assign ex5_sh1[20] = (~(ex5_sh1_x_b[20] & ex5_sh1_y_b[20] & ex5_sh1_u_b[20])); + assign ex5_sh1[21] = (~(ex5_sh1_x_b[21] & ex5_sh1_y_b[21] & ex5_sh1_u_b[21])); + assign ex5_sh1[22] = (~(ex5_sh1_x_b[22] & ex5_sh1_y_b[22] & ex5_sh1_u_b[22])); + assign ex5_sh1[23] = (~(ex5_sh1_x_b[23] & ex5_sh1_y_b[23] & ex5_sh1_u_b[23])); + assign ex5_sh1[24] = (~(ex5_sh1_x_b[24] & ex5_sh1_y_b[24] & ex5_sh1_u_b[24])); + assign ex5_sh1[25] = (~(ex5_sh1_x_b[25] & ex5_sh1_y_b[25] & ex5_sh1_u_b[25])); + assign ex5_sh1[26] = (~(ex5_sh1_x_b[26] & ex5_sh1_y_b[26] & ex5_sh1_u_b[26])); + assign ex5_sh1[27] = (~(ex5_sh1_x_b[27] & ex5_sh1_y_b[27] & ex5_sh1_u_b[27])); + assign ex5_sh1[28] = (~(ex5_sh1_x_b[28] & ex5_sh1_y_b[28] & ex5_sh1_u_b[28])); + assign ex5_sh1[29] = (~(ex5_sh1_x_b[29] & ex5_sh1_y_b[29] & ex5_sh1_u_b[29])); + assign ex5_sh1[30] = (~(ex5_sh1_x_b[30] & ex5_sh1_y_b[30] & ex5_sh1_u_b[30])); + assign ex5_sh1[31] = (~(ex5_sh1_x_b[31] & ex5_sh1_y_b[31] & ex5_sh1_u_b[31])); + assign ex5_sh1[32] = (~(ex5_sh1_x_b[32] & ex5_sh1_y_b[32] & ex5_sh1_u_b[32])); + assign ex5_sh1[33] = (~(ex5_sh1_x_b[33] & ex5_sh1_y_b[33] & ex5_sh1_u_b[33])); + assign ex5_sh1[34] = (~(ex5_sh1_x_b[34] & ex5_sh1_y_b[34] & ex5_sh1_u_b[34])); + assign ex5_sh1[35] = (~(ex5_sh1_x_b[35] & ex5_sh1_y_b[35] & ex5_sh1_u_b[35])); + assign ex5_sh1[36] = (~(ex5_sh1_x_b[36] & ex5_sh1_y_b[36])); + assign ex5_sh1[37] = (~(ex5_sh1_x_b[37] & ex5_sh1_y_b[37])); + assign ex5_sh1[38] = (~(ex5_sh1_x_b[38] & ex5_sh1_y_b[38])); + assign ex5_sh1[39] = (~(ex5_sh1_x_b[39] & ex5_sh1_y_b[39])); + assign ex5_sh1[40] = (~(ex5_sh1_x_b[40] & ex5_sh1_y_b[40])); + assign ex5_sh1[41] = (~(ex5_sh1_x_b[41] & ex5_sh1_y_b[41])); + assign ex5_sh1[42] = (~(ex5_sh1_x_b[42] & ex5_sh1_y_b[42])); + assign ex5_sh1[43] = (~(ex5_sh1_x_b[43] & ex5_sh1_y_b[43])); + assign ex5_sh1[44] = (~(ex5_sh1_x_b[44] & ex5_sh1_y_b[44])); + assign ex5_sh1[45] = (~(ex5_sh1_x_b[45] & ex5_sh1_y_b[45])); + assign ex5_sh1[46] = (~(ex5_sh1_x_b[46] & ex5_sh1_y_b[46])); + assign ex5_sh1[47] = (~(ex5_sh1_x_b[47] & ex5_sh1_y_b[47])); + assign ex5_sh1[48] = (~(ex5_sh1_x_b[48] & ex5_sh1_y_b[48])); + assign ex5_sh1[49] = (~(ex5_sh1_x_b[49] & ex5_sh1_y_b[49])); + assign ex5_sh1[50] = (~(ex5_sh1_x_b[50] & ex5_sh1_y_b[50])); + assign ex5_sh1[51] = (~(ex5_sh1_x_b[51] & ex5_sh1_y_b[51])); + assign ex5_sh1[52] = (~(ex5_sh1_x_b[52] & ex5_sh1_y_b[52])); + assign ex5_sh1[53] = (~(ex5_sh1_x_b[53] & ex5_sh1_y_b[53])); + assign ex5_sh1[54] = (~(ex5_sh1_x_b[54] & ex5_sh1_y_b[54])); + assign ex5_sh1[55] = (~(ex5_sh1_x_b[55] & ex5_sh1_y_b[55])); + assign ex5_sh1[56] = (~(ex5_sh1_x_b[56] & ex5_sh1_y_b[56])); + assign ex5_sh1[57] = (~(ex5_sh1_x_b[57] & ex5_sh1_y_b[57])); + assign ex5_sh1[58] = (~(ex5_sh1_x_b[58] & ex5_sh1_y_b[58])); + assign ex5_sh1[59] = (~(ex5_sh1_x_b[59] & ex5_sh1_y_b[59])); + assign ex5_sh1[60] = (~(ex5_sh1_x_b[60] & ex5_sh1_y_b[60])); + assign ex5_sh1[61] = (~(ex5_sh1_x_b[61] & ex5_sh1_y_b[61])); + assign ex5_sh1[62] = (~(ex5_sh1_x_b[62] & ex5_sh1_y_b[62])); + assign ex5_sh1[63] = (~(ex5_sh1_x_b[63] & ex5_sh1_y_b[63])); + assign ex5_sh1[64] = (~(ex5_sh1_x_b[64] & ex5_sh1_y_b[64])); + assign ex5_sh1[65] = (~(ex5_sh1_x_b[65] & ex5_sh1_y_b[65] & ex5_sh1_z_b[65])); + assign ex5_sh1[66] = (~(ex5_sh1_x_b[66] & ex5_sh1_y_b[66] & ex5_sh1_z_b[66])); + assign ex5_sh1[67] = (~(ex5_sh1_x_b[67] & ex5_sh1_y_b[67] & ex5_sh1_z_b[67])); + assign ex5_sh1[68] = (~(ex5_sh1_x_b[68] & ex5_sh1_y_b[68] & ex5_sh1_z_b[68])); + assign ex5_sh1[69] = (~(ex5_sh1_x_b[69] & ex5_sh1_y_b[69] & ex5_sh1_z_b[69])); + assign ex5_sh1[70] = (~(ex5_sh1_x_b[70] & ex5_sh1_y_b[70] & ex5_sh1_z_b[70])); + assign ex5_sh1[71] = (~(ex5_sh1_x_b[71] & ex5_sh1_y_b[71] & ex5_sh1_z_b[71])); + assign ex5_sh1[72] = (~(ex5_sh1_x_b[72] & ex5_sh1_y_b[72] & ex5_sh1_z_b[72])); + assign ex5_sh1[73] = (~(ex5_sh1_x_b[73] & ex5_sh1_y_b[73] & ex5_sh1_z_b[73])); + assign ex5_sh1[74] = (~(ex5_sh1_x_b[74] & ex5_sh1_y_b[74] & ex5_sh1_z_b[74])); + assign ex5_sh1[75] = (~(ex5_sh1_x_b[75] & ex5_sh1_y_b[75] & ex5_sh1_z_b[75])); + assign ex5_sh1[76] = (~(ex5_sh1_x_b[76] & ex5_sh1_y_b[76] & ex5_sh1_z_b[76])); + assign ex5_sh1[77] = (~(ex5_sh1_x_b[77] & ex5_sh1_y_b[77] & ex5_sh1_z_b[77])); + assign ex5_sh1[78] = (~(ex5_sh1_x_b[78] & ex5_sh1_y_b[78] & ex5_sh1_z_b[78])); + assign ex5_sh1[79] = (~(ex5_sh1_x_b[79] & ex5_sh1_y_b[79] & ex5_sh1_z_b[79])); + assign ex5_sh1[80] = (~(ex5_sh1_x_b[80] & ex5_sh1_y_b[80] & ex5_sh1_z_b[80])); + assign ex5_sh1[81] = (~(ex5_sh1_x_b[81] & ex5_sh1_y_b[81] & ex5_sh1_z_b[81])); + assign ex5_sh1[82] = (~(ex5_sh1_x_b[82] & ex5_sh1_y_b[82] & ex5_sh1_z_b[82])); + assign ex5_sh1[83] = (~(ex5_sh1_x_b[83] & ex5_sh1_y_b[83] & ex5_sh1_z_b[83])); + assign ex5_sh1[84] = (~(ex5_sh1_x_b[84] & ex5_sh1_y_b[84] & ex5_sh1_z_b[84])); + assign ex5_sh1[85] = (~(ex5_sh1_x_b[85] & ex5_sh1_y_b[85] & ex5_sh1_z_b[85])); + assign ex5_sh1[86] = (~(ex5_sh1_x_b[86] & ex5_sh1_y_b[86] & ex5_sh1_z_b[86])); + assign ex5_sh1[87] = (~(ex5_sh1_x_b[87] & ex5_sh1_y_b[87] & ex5_sh1_z_b[87])); + assign ex5_sh1[88] = (~(ex5_sh1_x_b[88] & ex5_sh1_y_b[88] & ex5_sh1_z_b[88])); + assign ex5_sh1[89] = (~(ex5_sh1_x_b[89] & ex5_sh1_y_b[89] & ex5_sh1_z_b[89])); + assign ex5_sh1[90] = (~(ex5_sh1_x_b[90] & ex5_sh1_y_b[90] & ex5_sh1_z_b[90])); + assign ex5_sh1[91] = (~(ex5_sh1_x_b[91] & ex5_sh1_y_b[91] & ex5_sh1_z_b[91])); + assign ex5_sh1[92] = (~(ex5_sh1_x_b[92] & ex5_sh1_y_b[92] & ex5_sh1_z_b[92])); + assign ex5_sh1[93] = (~(ex5_sh1_x_b[93] & ex5_sh1_y_b[93] & ex5_sh1_z_b[93])); + assign ex5_sh1[94] = (~(ex5_sh1_x_b[94] & ex5_sh1_y_b[94] & ex5_sh1_z_b[94])); + assign ex5_sh1[95] = (~(ex5_sh1_x_b[95] & ex5_sh1_y_b[95] & ex5_sh1_z_b[95])); + assign ex5_sh1[96] = (~(ex5_sh1_x_b[96] & ex5_sh1_y_b[96] & ex5_sh1_z_b[96])); + assign ex5_sh1[97] = (~(ex5_sh1_x_b[97] & ex5_sh1_y_b[97] & ex5_sh1_z_b[97])); + assign ex5_sh1[98] = (~(ex5_sh1_x_b[98] & ex5_sh1_y_b[98] & ex5_sh1_z_b[98])); + assign ex5_sh1[99] = (~(ex5_sh1_x_b[99] & ex5_sh1_y_b[99] & ex5_sh1_z_b[99])); + assign ex5_sh1[100] = (~(ex5_sh1_x_b[100] & ex5_sh1_z_b[100])); + assign ex5_sh1[101] = (~(ex5_sh1_x_b[101] & ex5_sh1_z_b[101])); + assign ex5_sh1[102] = (~(ex5_sh1_x_b[102] & ex5_sh1_z_b[102])); + assign ex5_sh1[103] = (~(ex5_sh1_x_b[103] & ex5_sh1_z_b[103])); + assign ex5_sh1[104] = (~(ex5_sh1_x_b[104] & ex5_sh1_z_b[104])); + assign ex5_sh1[105] = (~(ex5_sh1_x_b[105] & ex5_sh1_z_b[105])); + assign ex5_sh1[106] = (~(ex5_sh1_x_b[106] & ex5_sh1_z_b[106])); + assign ex5_sh1[107] = (~(ex5_sh1_x_b[107] & ex5_sh1_z_b[107])); + assign ex5_sh1[108] = (~(ex5_sh1_x_b[108] & ex5_sh1_z_b[108])); + assign ex5_sh1[109] = (~(ex5_sh1_x_b[109] & ex5_sh1_z_b[109])); + assign ex5_sh1[110] = (~(ex5_sh1_x_b[110] & ex5_sh1_z_b[110])); + assign ex5_sh1[111] = (~(ex5_sh1_x_b[111] & ex5_sh1_z_b[111])); + assign ex5_sh1[112] = (~(ex5_sh1_x_b[112] & ex5_sh1_z_b[112])); + assign ex5_sh1[113] = (~(ex5_sh1_x_b[113] & ex5_sh1_z_b[113])); + assign ex5_sh1[114] = (~(ex5_sh1_x_b[114] & ex5_sh1_z_b[114])); + assign ex5_sh1[115] = (~(ex5_sh1_x_b[115] & ex5_sh1_z_b[115])); + assign ex5_sh1[116] = (~(ex5_sh1_x_b[116] & ex5_sh1_z_b[116])); + assign ex5_sh1[117] = (~(ex5_sh1_x_b[117] & ex5_sh1_z_b[117])); + assign ex5_sh1[118] = (~(ex5_sh1_x_b[118] & ex5_sh1_z_b[118])); + assign ex5_sh1[119] = (~(ex5_sh1_x_b[119])); + assign ex5_sh1[120] = (~(ex5_sh1_x_b[120])); + + //---------------------------------------------------------------------------------- + + assign ex5_sh2_x_b[0] = (~((ex5_sh1[0] & ex5_shctl_16[0]) | (ex5_sh1[16] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[1] = (~((ex5_sh1[1] & ex5_shctl_16[0]) | (ex5_sh1[17] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[2] = (~((ex5_sh1[2] & ex5_shctl_16[0]) | (ex5_sh1[18] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[3] = (~((ex5_sh1[3] & ex5_shctl_16[0]) | (ex5_sh1[19] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[4] = (~((ex5_sh1[4] & ex5_shctl_16[0]) | (ex5_sh1[20] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[5] = (~((ex5_sh1[5] & ex5_shctl_16[0]) | (ex5_sh1[21] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[6] = (~((ex5_sh1[6] & ex5_shctl_16[0]) | (ex5_sh1[22] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[7] = (~((ex5_sh1[7] & ex5_shctl_16[0]) | (ex5_sh1[23] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[8] = (~((ex5_sh1[8] & ex5_shctl_16[0]) | (ex5_sh1[24] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[9] = (~((ex5_sh1[9] & ex5_shctl_16[0]) | (ex5_sh1[25] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[10] = (~((ex5_sh1[10] & ex5_shctl_16[0]) | (ex5_sh1[26] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[11] = (~((ex5_sh1[11] & ex5_shctl_16[0]) | (ex5_sh1[27] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[12] = (~((ex5_sh1[12] & ex5_shctl_16[0]) | (ex5_sh1[28] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[13] = (~((ex5_sh1[13] & ex5_shctl_16[0]) | (ex5_sh1[29] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[14] = (~((ex5_sh1[14] & ex5_shctl_16[0]) | (ex5_sh1[30] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[15] = (~((ex5_sh1[15] & ex5_shctl_16[0]) | (ex5_sh1[31] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[16] = (~((ex5_sh1[16] & ex5_shctl_16[0]) | (ex5_sh1[32] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[17] = (~((ex5_sh1[17] & ex5_shctl_16[0]) | (ex5_sh1[33] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[18] = (~((ex5_sh1[18] & ex5_shctl_16[0]) | (ex5_sh1[34] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[19] = (~((ex5_sh1[19] & ex5_shctl_16[0]) | (ex5_sh1[35] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[20] = (~((ex5_sh1[20] & ex5_shctl_16[0]) | (ex5_sh1[36] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[21] = (~((ex5_sh1[21] & ex5_shctl_16[0]) | (ex5_sh1[37] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[22] = (~((ex5_sh1[22] & ex5_shctl_16[0]) | (ex5_sh1[38] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[23] = (~((ex5_sh1[23] & ex5_shctl_16[0]) | (ex5_sh1[39] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[24] = (~((ex5_sh1[24] & ex5_shctl_16[0]) | (ex5_sh1[40] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[25] = (~((ex5_sh1[25] & ex5_shctl_16[0]) | (ex5_sh1[41] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[26] = (~((ex5_sh1[26] & ex5_shctl_16[0]) | (ex5_sh1[42] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[27] = (~((ex5_sh1[27] & ex5_shctl_16[0]) | (ex5_sh1[43] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[28] = (~((ex5_sh1[28] & ex5_shctl_16[0]) | (ex5_sh1[44] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[29] = (~((ex5_sh1[29] & ex5_shctl_16[0]) | (ex5_sh1[45] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[30] = (~((ex5_sh1[30] & ex5_shctl_16[0]) | (ex5_sh1[46] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[31] = (~((ex5_sh1[31] & ex5_shctl_16[0]) | (ex5_sh1[47] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[32] = (~((ex5_sh1[32] & ex5_shctl_16[0]) | (ex5_sh1[48] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[33] = (~((ex5_sh1[33] & ex5_shctl_16[0]) | (ex5_sh1[49] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[34] = (~((ex5_sh1[34] & ex5_shctl_16[0]) | (ex5_sh1[50] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[35] = (~((ex5_sh1[35] & ex5_shctl_16[0]) | (ex5_sh1[51] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[36] = (~((ex5_sh1[36] & ex5_shctl_16[0]) | (ex5_sh1[52] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[37] = (~((ex5_sh1[37] & ex5_shctl_16[0]) | (ex5_sh1[53] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[38] = (~((ex5_sh1[38] & ex5_shctl_16[0]) | (ex5_sh1[54] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[39] = (~((ex5_sh1[39] & ex5_shctl_16[0]) | (ex5_sh1[55] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[40] = (~((ex5_sh1[40] & ex5_shctl_16[0]) | (ex5_sh1[56] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[41] = (~((ex5_sh1[41] & ex5_shctl_16[0]) | (ex5_sh1[57] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[42] = (~((ex5_sh1[42] & ex5_shctl_16[0]) | (ex5_sh1[58] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[43] = (~((ex5_sh1[43] & ex5_shctl_16[0]) | (ex5_sh1[59] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[44] = (~((ex5_sh1[44] & ex5_shctl_16[0]) | (ex5_sh1[60] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[45] = (~((ex5_sh1[45] & ex5_shctl_16[0]) | (ex5_sh1[61] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[46] = (~((ex5_sh1[46] & ex5_shctl_16[0]) | (ex5_sh1[62] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[47] = (~((ex5_sh1[47] & ex5_shctl_16[0]) | (ex5_sh1[63] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[48] = (~((ex5_sh1[48] & ex5_shctl_16[0]) | (ex5_sh1[64] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[49] = (~((ex5_sh1[49] & ex5_shctl_16[0]) | (ex5_sh1[65] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[50] = (~((ex5_sh1[50] & ex5_shctl_16[0]) | (ex5_sh1[66] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[51] = (~((ex5_sh1[51] & ex5_shctl_16[0]) | (ex5_sh1[67] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[52] = (~((ex5_sh1[52] & ex5_shctl_16[0]) | (ex5_sh1[68] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[53] = (~((ex5_sh1[53] & ex5_shctl_16[0]) | (ex5_sh1[69] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[54] = (~((ex5_sh1[54] & ex5_shctl_16[0]) | (ex5_sh1[70] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[55] = (~((ex5_sh1[55] & ex5_shctl_16[0]) | (ex5_sh1[71] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[56] = (~((ex5_sh1[56] & ex5_shctl_16[0]) | (ex5_sh1[72] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[57] = (~((ex5_sh1[57] & ex5_shctl_16[0]) | (ex5_sh1[73] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[58] = (~((ex5_sh1[58] & ex5_shctl_16[0]) | (ex5_sh1[74] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[59] = (~((ex5_sh1[59] & ex5_shctl_16[0]) | (ex5_sh1[75] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[60] = (~((ex5_sh1[60] & ex5_shctl_16[0]) | (ex5_sh1[76] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[61] = (~((ex5_sh1[61] & ex5_shctl_16[0]) | (ex5_sh1[77] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[62] = (~((ex5_sh1[62] & ex5_shctl_16[0]) | (ex5_sh1[78] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[63] = (~((ex5_sh1[63] & ex5_shctl_16[0]) | (ex5_sh1[79] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[64] = (~((ex5_sh1[64] & ex5_shctl_16[0]) | (ex5_sh1[80] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[65] = (~((ex5_sh1[65] & ex5_shctl_16[0]) | (ex5_sh1[81] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[66] = (~((ex5_sh1[66] & ex5_shctl_16[0]) | (ex5_sh1[82] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[67] = (~((ex5_sh1[67] & ex5_shctl_16[0]) | (ex5_sh1[83] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[68] = (~((ex5_sh1[68] & ex5_shctl_16[0]) | (ex5_sh1[84] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[69] = (~((ex5_sh1[69] & ex5_shctl_16[0]) | (ex5_sh1[85] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[70] = (~((ex5_sh1[70] & ex5_shctl_16[0]) | (ex5_sh1[86] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[71] = (~((ex5_sh1[71] & ex5_shctl_16[0]) | (ex5_sh1[87] & ex5_shctl_16[1]))); + assign ex5_sh2_x_b[72] = (~((ex5_sh1[72] & ex5_shctl_16[0]) | (ex5_sh1[88] & ex5_shctl_16[1]))); + + assign ex5_sh2_y_b[0] = (~((ex5_sh1[32] & ex5_shctl_16[2]) | (ex5_sh1[48] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[1] = (~((ex5_sh1[33] & ex5_shctl_16[2]) | (ex5_sh1[49] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[2] = (~((ex5_sh1[34] & ex5_shctl_16[2]) | (ex5_sh1[50] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[3] = (~((ex5_sh1[35] & ex5_shctl_16[2]) | (ex5_sh1[51] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[4] = (~((ex5_sh1[36] & ex5_shctl_16[2]) | (ex5_sh1[52] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[5] = (~((ex5_sh1[37] & ex5_shctl_16[2]) | (ex5_sh1[53] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[6] = (~((ex5_sh1[38] & ex5_shctl_16[2]) | (ex5_sh1[54] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[7] = (~((ex5_sh1[39] & ex5_shctl_16[2]) | (ex5_sh1[55] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[8] = (~((ex5_sh1[40] & ex5_shctl_16[2]) | (ex5_sh1[56] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[9] = (~((ex5_sh1[41] & ex5_shctl_16[2]) | (ex5_sh1[57] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[10] = (~((ex5_sh1[42] & ex5_shctl_16[2]) | (ex5_sh1[58] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[11] = (~((ex5_sh1[43] & ex5_shctl_16[2]) | (ex5_sh1[59] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[12] = (~((ex5_sh1[44] & ex5_shctl_16[2]) | (ex5_sh1[60] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[13] = (~((ex5_sh1[45] & ex5_shctl_16[2]) | (ex5_sh1[61] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[14] = (~((ex5_sh1[46] & ex5_shctl_16[2]) | (ex5_sh1[62] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[15] = (~((ex5_sh1[47] & ex5_shctl_16[2]) | (ex5_sh1[63] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[16] = (~((ex5_sh1[48] & ex5_shctl_16[2]) | (ex5_sh1[64] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[17] = (~((ex5_sh1[49] & ex5_shctl_16[2]) | (ex5_sh1[65] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[18] = (~((ex5_sh1[50] & ex5_shctl_16[2]) | (ex5_sh1[66] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[19] = (~((ex5_sh1[51] & ex5_shctl_16[2]) | (ex5_sh1[67] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[20] = (~((ex5_sh1[52] & ex5_shctl_16[2]) | (ex5_sh1[68] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[21] = (~((ex5_sh1[53] & ex5_shctl_16[2]) | (ex5_sh1[69] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[22] = (~((ex5_sh1[54] & ex5_shctl_16[2]) | (ex5_sh1[70] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[23] = (~((ex5_sh1[55] & ex5_shctl_16[2]) | (ex5_sh1[71] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[24] = (~((ex5_sh1[56] & ex5_shctl_16[2]) | (ex5_sh1[72] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[25] = (~((ex5_sh1[57] & ex5_shctl_16[2]) | (ex5_sh1[73] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[26] = (~((ex5_sh1[58] & ex5_shctl_16[2]) | (ex5_sh1[74] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[27] = (~((ex5_sh1[59] & ex5_shctl_16[2]) | (ex5_sh1[75] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[28] = (~((ex5_sh1[60] & ex5_shctl_16[2]) | (ex5_sh1[76] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[29] = (~((ex5_sh1[61] & ex5_shctl_16[2]) | (ex5_sh1[77] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[30] = (~((ex5_sh1[62] & ex5_shctl_16[2]) | (ex5_sh1[78] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[31] = (~((ex5_sh1[63] & ex5_shctl_16[2]) | (ex5_sh1[79] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[32] = (~((ex5_sh1[64] & ex5_shctl_16[2]) | (ex5_sh1[80] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[33] = (~((ex5_sh1[65] & ex5_shctl_16[2]) | (ex5_sh1[81] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[34] = (~((ex5_sh1[66] & ex5_shctl_16[2]) | (ex5_sh1[82] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[35] = (~((ex5_sh1[67] & ex5_shctl_16[2]) | (ex5_sh1[83] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[36] = (~((ex5_sh1[68] & ex5_shctl_16[2]) | (ex5_sh1[84] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[37] = (~((ex5_sh1[69] & ex5_shctl_16[2]) | (ex5_sh1[85] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[38] = (~((ex5_sh1[70] & ex5_shctl_16[2]) | (ex5_sh1[86] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[39] = (~((ex5_sh1[71] & ex5_shctl_16[2]) | (ex5_sh1[87] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[40] = (~((ex5_sh1[72] & ex5_shctl_16[2]) | (ex5_sh1[88] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[41] = (~((ex5_sh1[73] & ex5_shctl_16[2]) | (ex5_sh1[89] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[42] = (~((ex5_sh1[74] & ex5_shctl_16[2]) | (ex5_sh1[90] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[43] = (~((ex5_sh1[75] & ex5_shctl_16[2]) | (ex5_sh1[91] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[44] = (~((ex5_sh1[76] & ex5_shctl_16[2]) | (ex5_sh1[92] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[45] = (~((ex5_sh1[77] & ex5_shctl_16[2]) | (ex5_sh1[93] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[46] = (~((ex5_sh1[78] & ex5_shctl_16[2]) | (ex5_sh1[94] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[47] = (~((ex5_sh1[79] & ex5_shctl_16[2]) | (ex5_sh1[95] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[48] = (~((ex5_sh1[80] & ex5_shctl_16[2]) | (ex5_sh1[96] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[49] = (~((ex5_sh1[81] & ex5_shctl_16[2]) | (ex5_sh1[97] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[50] = (~((ex5_sh1[82] & ex5_shctl_16[2]) | (ex5_sh1[98] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[51] = (~((ex5_sh1[83] & ex5_shctl_16[2]) | (ex5_sh1[99] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[52] = (~((ex5_sh1[84] & ex5_shctl_16[2]) | (ex5_sh1[100] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[53] = (~((ex5_sh1[85] & ex5_shctl_16[2]) | (ex5_sh1[101] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[54] = (~((ex5_sh1[86] & ex5_shctl_16[2]) | (ex5_sh1[102] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[55] = (~((ex5_sh1[87] & ex5_shctl_16[2]) | (ex5_sh1[103] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[56] = (~((ex5_sh1[88] & ex5_shctl_16[2]) | (ex5_sh1[104] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[57] = (~((ex5_sh1[89] & ex5_shctl_16[2]) | (ex5_sh1[105] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[58] = (~((ex5_sh1[90] & ex5_shctl_16[2]) | (ex5_sh1[106] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[59] = (~((ex5_sh1[91] & ex5_shctl_16[2]) | (ex5_sh1[107] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[60] = (~((ex5_sh1[92] & ex5_shctl_16[2]) | (ex5_sh1[108] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[61] = (~((ex5_sh1[93] & ex5_shctl_16[2]) | (ex5_sh1[109] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[62] = (~((ex5_sh1[94] & ex5_shctl_16[2]) | (ex5_sh1[110] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[63] = (~((ex5_sh1[95] & ex5_shctl_16[2]) | (ex5_sh1[111] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[64] = (~((ex5_sh1[96] & ex5_shctl_16[2]) | (ex5_sh1[112] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[65] = (~((ex5_sh1[97] & ex5_shctl_16[2]) | (ex5_sh1[113] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[66] = (~((ex5_sh1[98] & ex5_shctl_16[2]) | (ex5_sh1[114] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[67] = (~((ex5_sh1[99] & ex5_shctl_16[2]) | (ex5_sh1[115] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[68] = (~((ex5_sh1[100] & ex5_shctl_16[2]) | (ex5_sh1[116] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[69] = (~((ex5_sh1[101] & ex5_shctl_16[2]) | (ex5_sh1[117] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[70] = (~((ex5_sh1[102] & ex5_shctl_16[2]) | (ex5_sh1[118] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[71] = (~((ex5_sh1[103] & ex5_shctl_16[2]) | (ex5_sh1[119] & ex5_shctl_16[3]))); + assign ex5_sh2_y_b[72] = (~((ex5_sh1[104] & ex5_shctl_16[2]) | (ex5_sh1[120] & ex5_shctl_16[3]))); + + assign ex5_sh2[0] = (~(ex5_sh2_x_b[0] & ex5_sh2_y_b[0])); + assign ex5_sh2[1] = (~(ex5_sh2_x_b[1] & ex5_sh2_y_b[1])); + assign ex5_sh2[2] = (~(ex5_sh2_x_b[2] & ex5_sh2_y_b[2])); + assign ex5_sh2[3] = (~(ex5_sh2_x_b[3] & ex5_sh2_y_b[3])); + assign ex5_sh2[4] = (~(ex5_sh2_x_b[4] & ex5_sh2_y_b[4])); + assign ex5_sh2[5] = (~(ex5_sh2_x_b[5] & ex5_sh2_y_b[5])); + assign ex5_sh2[6] = (~(ex5_sh2_x_b[6] & ex5_sh2_y_b[6])); + assign ex5_sh2[7] = (~(ex5_sh2_x_b[7] & ex5_sh2_y_b[7])); + assign ex5_sh2[8] = (~(ex5_sh2_x_b[8] & ex5_sh2_y_b[8])); + assign ex5_sh2[9] = (~(ex5_sh2_x_b[9] & ex5_sh2_y_b[9])); + assign ex5_sh2[10] = (~(ex5_sh2_x_b[10] & ex5_sh2_y_b[10])); + assign ex5_sh2[11] = (~(ex5_sh2_x_b[11] & ex5_sh2_y_b[11])); + assign ex5_sh2[12] = (~(ex5_sh2_x_b[12] & ex5_sh2_y_b[12])); + assign ex5_sh2[13] = (~(ex5_sh2_x_b[13] & ex5_sh2_y_b[13])); + assign ex5_sh2[14] = (~(ex5_sh2_x_b[14] & ex5_sh2_y_b[14])); + assign ex5_sh2[15] = (~(ex5_sh2_x_b[15] & ex5_sh2_y_b[15])); + assign ex5_sh2[16] = (~(ex5_sh2_x_b[16] & ex5_sh2_y_b[16])); + assign ex5_sh2[17] = (~(ex5_sh2_x_b[17] & ex5_sh2_y_b[17])); + assign ex5_sh2[18] = (~(ex5_sh2_x_b[18] & ex5_sh2_y_b[18])); + assign ex5_sh2[19] = (~(ex5_sh2_x_b[19] & ex5_sh2_y_b[19])); + assign ex5_sh2[20] = (~(ex5_sh2_x_b[20] & ex5_sh2_y_b[20])); + assign ex5_sh2[21] = (~(ex5_sh2_x_b[21] & ex5_sh2_y_b[21])); + assign ex5_sh2[22] = (~(ex5_sh2_x_b[22] & ex5_sh2_y_b[22])); + assign ex5_sh2[23] = (~(ex5_sh2_x_b[23] & ex5_sh2_y_b[23])); + assign ex5_sh2[24] = (~(ex5_sh2_x_b[24] & ex5_sh2_y_b[24])); + assign ex5_sh2[25] = (~(ex5_sh2_x_b[25] & ex5_sh2_y_b[25])); + assign ex5_sh2[26] = (~(ex5_sh2_x_b[26] & ex5_sh2_y_b[26])); + assign ex5_sh2[27] = (~(ex5_sh2_x_b[27] & ex5_sh2_y_b[27])); + assign ex5_sh2[28] = (~(ex5_sh2_x_b[28] & ex5_sh2_y_b[28])); + assign ex5_sh2[29] = (~(ex5_sh2_x_b[29] & ex5_sh2_y_b[29])); + assign ex5_sh2[30] = (~(ex5_sh2_x_b[30] & ex5_sh2_y_b[30])); + assign ex5_sh2[31] = (~(ex5_sh2_x_b[31] & ex5_sh2_y_b[31])); + assign ex5_sh2[32] = (~(ex5_sh2_x_b[32] & ex5_sh2_y_b[32])); + assign ex5_sh2[33] = (~(ex5_sh2_x_b[33] & ex5_sh2_y_b[33])); + assign ex5_sh2[34] = (~(ex5_sh2_x_b[34] & ex5_sh2_y_b[34])); + assign ex5_sh2[35] = (~(ex5_sh2_x_b[35] & ex5_sh2_y_b[35])); + assign ex5_sh2[36] = (~(ex5_sh2_x_b[36] & ex5_sh2_y_b[36])); + assign ex5_sh2[37] = (~(ex5_sh2_x_b[37] & ex5_sh2_y_b[37])); + assign ex5_sh2[38] = (~(ex5_sh2_x_b[38] & ex5_sh2_y_b[38])); + assign ex5_sh2[39] = (~(ex5_sh2_x_b[39] & ex5_sh2_y_b[39])); + assign ex5_sh2[40] = (~(ex5_sh2_x_b[40] & ex5_sh2_y_b[40])); + assign ex5_sh2[41] = (~(ex5_sh2_x_b[41] & ex5_sh2_y_b[41])); + assign ex5_sh2[42] = (~(ex5_sh2_x_b[42] & ex5_sh2_y_b[42])); + assign ex5_sh2[43] = (~(ex5_sh2_x_b[43] & ex5_sh2_y_b[43])); + assign ex5_sh2[44] = (~(ex5_sh2_x_b[44] & ex5_sh2_y_b[44])); + assign ex5_sh2[45] = (~(ex5_sh2_x_b[45] & ex5_sh2_y_b[45])); + assign ex5_sh2[46] = (~(ex5_sh2_x_b[46] & ex5_sh2_y_b[46])); + assign ex5_sh2[47] = (~(ex5_sh2_x_b[47] & ex5_sh2_y_b[47])); + assign ex5_sh2[48] = (~(ex5_sh2_x_b[48] & ex5_sh2_y_b[48])); + assign ex5_sh2[49] = (~(ex5_sh2_x_b[49] & ex5_sh2_y_b[49])); + assign ex5_sh2[50] = (~(ex5_sh2_x_b[50] & ex5_sh2_y_b[50])); + assign ex5_sh2[51] = (~(ex5_sh2_x_b[51] & ex5_sh2_y_b[51])); + assign ex5_sh2[52] = (~(ex5_sh2_x_b[52] & ex5_sh2_y_b[52])); + assign ex5_sh2[53] = (~(ex5_sh2_x_b[53] & ex5_sh2_y_b[53])); + assign ex5_sh2[54] = (~(ex5_sh2_x_b[54] & ex5_sh2_y_b[54])); + assign ex5_sh2[55] = (~(ex5_sh2_x_b[55] & ex5_sh2_y_b[55])); + assign ex5_sh2[56] = (~(ex5_sh2_x_b[56] & ex5_sh2_y_b[56])); + assign ex5_sh2[57] = (~(ex5_sh2_x_b[57] & ex5_sh2_y_b[57])); + assign ex5_sh2[58] = (~(ex5_sh2_x_b[58] & ex5_sh2_y_b[58])); + assign ex5_sh2[59] = (~(ex5_sh2_x_b[59] & ex5_sh2_y_b[59])); + assign ex5_sh2[60] = (~(ex5_sh2_x_b[60] & ex5_sh2_y_b[60])); + assign ex5_sh2[61] = (~(ex5_sh2_x_b[61] & ex5_sh2_y_b[61])); + assign ex5_sh2[62] = (~(ex5_sh2_x_b[62] & ex5_sh2_y_b[62])); + assign ex5_sh2[63] = (~(ex5_sh2_x_b[63] & ex5_sh2_y_b[63])); + assign ex5_sh2[64] = (~(ex5_sh2_x_b[64] & ex5_sh2_y_b[64])); + assign ex5_sh2[65] = (~(ex5_sh2_x_b[65] & ex5_sh2_y_b[65])); + assign ex5_sh2[66] = (~(ex5_sh2_x_b[66] & ex5_sh2_y_b[66])); + assign ex5_sh2[67] = (~(ex5_sh2_x_b[67] & ex5_sh2_y_b[67])); + assign ex5_sh2[68] = (~(ex5_sh2_x_b[68] & ex5_sh2_y_b[68])); + assign ex5_sh2[69] = (~(ex5_sh2_x_b[69] & ex5_sh2_y_b[69])); + assign ex5_sh2[70] = (~(ex5_sh2_x_b[70] & ex5_sh2_y_b[70])); + assign ex5_sh2[71] = (~(ex5_sh2_x_b[71] & ex5_sh2_y_b[71])); + assign ex5_sh2[72] = (~(ex5_sh2_x_b[72] & ex5_sh2_y_b[72])); + + //--------------------------------------------- + + assign ex5_sh3_x_b[0] = (~((ex5_sh2[0] & ex5_shctl_04[0]) | (ex5_sh2[4] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[1] = (~((ex5_sh2[1] & ex5_shctl_04[0]) | (ex5_sh2[5] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[2] = (~((ex5_sh2[2] & ex5_shctl_04[0]) | (ex5_sh2[6] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[3] = (~((ex5_sh2[3] & ex5_shctl_04[0]) | (ex5_sh2[7] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[4] = (~((ex5_sh2[4] & ex5_shctl_04[0]) | (ex5_sh2[8] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[5] = (~((ex5_sh2[5] & ex5_shctl_04[0]) | (ex5_sh2[9] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[6] = (~((ex5_sh2[6] & ex5_shctl_04[0]) | (ex5_sh2[10] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[7] = (~((ex5_sh2[7] & ex5_shctl_04[0]) | (ex5_sh2[11] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[8] = (~((ex5_sh2[8] & ex5_shctl_04[0]) | (ex5_sh2[12] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[9] = (~((ex5_sh2[9] & ex5_shctl_04[0]) | (ex5_sh2[13] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[10] = (~((ex5_sh2[10] & ex5_shctl_04[0]) | (ex5_sh2[14] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[11] = (~((ex5_sh2[11] & ex5_shctl_04[0]) | (ex5_sh2[15] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[12] = (~((ex5_sh2[12] & ex5_shctl_04[0]) | (ex5_sh2[16] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[13] = (~((ex5_sh2[13] & ex5_shctl_04[0]) | (ex5_sh2[17] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[14] = (~((ex5_sh2[14] & ex5_shctl_04[0]) | (ex5_sh2[18] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[15] = (~((ex5_sh2[15] & ex5_shctl_04[0]) | (ex5_sh2[19] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[16] = (~((ex5_sh2[16] & ex5_shctl_04[0]) | (ex5_sh2[20] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[17] = (~((ex5_sh2[17] & ex5_shctl_04[0]) | (ex5_sh2[21] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[18] = (~((ex5_sh2[18] & ex5_shctl_04[0]) | (ex5_sh2[22] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[19] = (~((ex5_sh2[19] & ex5_shctl_04[0]) | (ex5_sh2[23] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[20] = (~((ex5_sh2[20] & ex5_shctl_04[0]) | (ex5_sh2[24] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[21] = (~((ex5_sh2[21] & ex5_shctl_04[0]) | (ex5_sh2[25] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[22] = (~((ex5_sh2[22] & ex5_shctl_04[0]) | (ex5_sh2[26] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[23] = (~((ex5_sh2[23] & ex5_shctl_04[0]) | (ex5_sh2[27] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[24] = (~((ex5_sh2[24] & ex5_shctl_04[0]) | (ex5_sh2[28] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[25] = (~((ex5_sh2[25] & ex5_shctl_04[0]) | (ex5_sh2[29] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[26] = (~((ex5_sh2[26] & ex5_shctl_04[0]) | (ex5_sh2[30] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[27] = (~((ex5_sh2[27] & ex5_shctl_04[0]) | (ex5_sh2[31] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[28] = (~((ex5_sh2[28] & ex5_shctl_04[0]) | (ex5_sh2[32] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[29] = (~((ex5_sh2[29] & ex5_shctl_04[0]) | (ex5_sh2[33] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[30] = (~((ex5_sh2[30] & ex5_shctl_04[0]) | (ex5_sh2[34] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[31] = (~((ex5_sh2[31] & ex5_shctl_04[0]) | (ex5_sh2[35] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[32] = (~((ex5_sh2[32] & ex5_shctl_04[0]) | (ex5_sh2[36] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[33] = (~((ex5_sh2[33] & ex5_shctl_04[0]) | (ex5_sh2[37] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[34] = (~((ex5_sh2[34] & ex5_shctl_04[0]) | (ex5_sh2[38] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[35] = (~((ex5_sh2[35] & ex5_shctl_04[0]) | (ex5_sh2[39] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[36] = (~((ex5_sh2[36] & ex5_shctl_04[0]) | (ex5_sh2[40] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[37] = (~((ex5_sh2[37] & ex5_shctl_04[0]) | (ex5_sh2[41] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[38] = (~((ex5_sh2[38] & ex5_shctl_04[0]) | (ex5_sh2[42] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[39] = (~((ex5_sh2[39] & ex5_shctl_04[0]) | (ex5_sh2[43] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[40] = (~((ex5_sh2[40] & ex5_shctl_04[0]) | (ex5_sh2[44] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[41] = (~((ex5_sh2[41] & ex5_shctl_04[0]) | (ex5_sh2[45] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[42] = (~((ex5_sh2[42] & ex5_shctl_04[0]) | (ex5_sh2[46] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[43] = (~((ex5_sh2[43] & ex5_shctl_04[0]) | (ex5_sh2[47] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[44] = (~((ex5_sh2[44] & ex5_shctl_04[0]) | (ex5_sh2[48] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[45] = (~((ex5_sh2[45] & ex5_shctl_04[0]) | (ex5_sh2[49] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[46] = (~((ex5_sh2[46] & ex5_shctl_04[0]) | (ex5_sh2[50] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[47] = (~((ex5_sh2[47] & ex5_shctl_04[0]) | (ex5_sh2[51] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[48] = (~((ex5_sh2[48] & ex5_shctl_04[0]) | (ex5_sh2[52] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[49] = (~((ex5_sh2[49] & ex5_shctl_04[0]) | (ex5_sh2[53] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[50] = (~((ex5_sh2[50] & ex5_shctl_04[0]) | (ex5_sh2[54] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[51] = (~((ex5_sh2[51] & ex5_shctl_04[0]) | (ex5_sh2[55] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[52] = (~((ex5_sh2[52] & ex5_shctl_04[0]) | (ex5_sh2[56] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[53] = (~((ex5_sh2[53] & ex5_shctl_04[0]) | (ex5_sh2[57] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[54] = (~((ex5_sh2[54] & ex5_shctl_04[0]) | (ex5_sh2[58] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[55] = (~((ex5_sh2[55] & ex5_shctl_04[0]) | (ex5_sh2[59] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[56] = (~((ex5_sh2[56] & ex5_shctl_04[0]) | (ex5_sh2[60] & ex5_shctl_04[1]))); + assign ex5_sh3_x_b[57] = (~((ex5_sh2[57] & ex5_shctl_04[0]) | (ex5_sh2[61] & ex5_shctl_04[1]))); + + assign ex5_sh3_y_b[0] = (~((ex5_sh2[8] & ex5_shctl_04[2]) | (ex5_sh2[12] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[1] = (~((ex5_sh2[9] & ex5_shctl_04[2]) | (ex5_sh2[13] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[2] = (~((ex5_sh2[10] & ex5_shctl_04[2]) | (ex5_sh2[14] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[3] = (~((ex5_sh2[11] & ex5_shctl_04[2]) | (ex5_sh2[15] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[4] = (~((ex5_sh2[12] & ex5_shctl_04[2]) | (ex5_sh2[16] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[5] = (~((ex5_sh2[13] & ex5_shctl_04[2]) | (ex5_sh2[17] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[6] = (~((ex5_sh2[14] & ex5_shctl_04[2]) | (ex5_sh2[18] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[7] = (~((ex5_sh2[15] & ex5_shctl_04[2]) | (ex5_sh2[19] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[8] = (~((ex5_sh2[16] & ex5_shctl_04[2]) | (ex5_sh2[20] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[9] = (~((ex5_sh2[17] & ex5_shctl_04[2]) | (ex5_sh2[21] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[10] = (~((ex5_sh2[18] & ex5_shctl_04[2]) | (ex5_sh2[22] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[11] = (~((ex5_sh2[19] & ex5_shctl_04[2]) | (ex5_sh2[23] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[12] = (~((ex5_sh2[20] & ex5_shctl_04[2]) | (ex5_sh2[24] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[13] = (~((ex5_sh2[21] & ex5_shctl_04[2]) | (ex5_sh2[25] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[14] = (~((ex5_sh2[22] & ex5_shctl_04[2]) | (ex5_sh2[26] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[15] = (~((ex5_sh2[23] & ex5_shctl_04[2]) | (ex5_sh2[27] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[16] = (~((ex5_sh2[24] & ex5_shctl_04[2]) | (ex5_sh2[28] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[17] = (~((ex5_sh2[25] & ex5_shctl_04[2]) | (ex5_sh2[29] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[18] = (~((ex5_sh2[26] & ex5_shctl_04[2]) | (ex5_sh2[30] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[19] = (~((ex5_sh2[27] & ex5_shctl_04[2]) | (ex5_sh2[31] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[20] = (~((ex5_sh2[28] & ex5_shctl_04[2]) | (ex5_sh2[32] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[21] = (~((ex5_sh2[29] & ex5_shctl_04[2]) | (ex5_sh2[33] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[22] = (~((ex5_sh2[30] & ex5_shctl_04[2]) | (ex5_sh2[34] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[23] = (~((ex5_sh2[31] & ex5_shctl_04[2]) | (ex5_sh2[35] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[24] = (~((ex5_sh2[32] & ex5_shctl_04[2]) | (ex5_sh2[36] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[25] = (~((ex5_sh2[33] & ex5_shctl_04[2]) | (ex5_sh2[37] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[26] = (~((ex5_sh2[34] & ex5_shctl_04[2]) | (ex5_sh2[38] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[27] = (~((ex5_sh2[35] & ex5_shctl_04[2]) | (ex5_sh2[39] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[28] = (~((ex5_sh2[36] & ex5_shctl_04[2]) | (ex5_sh2[40] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[29] = (~((ex5_sh2[37] & ex5_shctl_04[2]) | (ex5_sh2[41] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[30] = (~((ex5_sh2[38] & ex5_shctl_04[2]) | (ex5_sh2[42] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[31] = (~((ex5_sh2[39] & ex5_shctl_04[2]) | (ex5_sh2[43] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[32] = (~((ex5_sh2[40] & ex5_shctl_04[2]) | (ex5_sh2[44] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[33] = (~((ex5_sh2[41] & ex5_shctl_04[2]) | (ex5_sh2[45] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[34] = (~((ex5_sh2[42] & ex5_shctl_04[2]) | (ex5_sh2[46] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[35] = (~((ex5_sh2[43] & ex5_shctl_04[2]) | (ex5_sh2[47] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[36] = (~((ex5_sh2[44] & ex5_shctl_04[2]) | (ex5_sh2[48] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[37] = (~((ex5_sh2[45] & ex5_shctl_04[2]) | (ex5_sh2[49] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[38] = (~((ex5_sh2[46] & ex5_shctl_04[2]) | (ex5_sh2[50] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[39] = (~((ex5_sh2[47] & ex5_shctl_04[2]) | (ex5_sh2[51] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[40] = (~((ex5_sh2[48] & ex5_shctl_04[2]) | (ex5_sh2[52] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[41] = (~((ex5_sh2[49] & ex5_shctl_04[2]) | (ex5_sh2[53] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[42] = (~((ex5_sh2[50] & ex5_shctl_04[2]) | (ex5_sh2[54] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[43] = (~((ex5_sh2[51] & ex5_shctl_04[2]) | (ex5_sh2[55] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[44] = (~((ex5_sh2[52] & ex5_shctl_04[2]) | (ex5_sh2[56] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[45] = (~((ex5_sh2[53] & ex5_shctl_04[2]) | (ex5_sh2[57] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[46] = (~((ex5_sh2[54] & ex5_shctl_04[2]) | (ex5_sh2[58] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[47] = (~((ex5_sh2[55] & ex5_shctl_04[2]) | (ex5_sh2[59] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[48] = (~((ex5_sh2[56] & ex5_shctl_04[2]) | (ex5_sh2[60] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[49] = (~((ex5_sh2[57] & ex5_shctl_04[2]) | (ex5_sh2[61] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[50] = (~((ex5_sh2[58] & ex5_shctl_04[2]) | (ex5_sh2[62] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[51] = (~((ex5_sh2[59] & ex5_shctl_04[2]) | (ex5_sh2[63] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[52] = (~((ex5_sh2[60] & ex5_shctl_04[2]) | (ex5_sh2[64] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[53] = (~((ex5_sh2[61] & ex5_shctl_04[2]) | (ex5_sh2[65] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[54] = (~((ex5_sh2[62] & ex5_shctl_04[2]) | (ex5_sh2[66] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[55] = (~((ex5_sh2[63] & ex5_shctl_04[2]) | (ex5_sh2[67] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[56] = (~((ex5_sh2[64] & ex5_shctl_04[2]) | (ex5_sh2[68] & ex5_shctl_04[3]))); + assign ex5_sh3_y_b[57] = (~((ex5_sh2[65] & ex5_shctl_04[2]) | (ex5_sh2[69] & ex5_shctl_04[3]))); + + assign ex5_sh3[0] = (~(ex5_sh3_x_b[0] & ex5_sh3_y_b[0])); + assign ex5_sh3[1] = (~(ex5_sh3_x_b[1] & ex5_sh3_y_b[1])); + assign ex5_sh3[2] = (~(ex5_sh3_x_b[2] & ex5_sh3_y_b[2])); + assign ex5_sh3[3] = (~(ex5_sh3_x_b[3] & ex5_sh3_y_b[3])); + assign ex5_sh3[4] = (~(ex5_sh3_x_b[4] & ex5_sh3_y_b[4])); + assign ex5_sh3[5] = (~(ex5_sh3_x_b[5] & ex5_sh3_y_b[5])); + assign ex5_sh3[6] = (~(ex5_sh3_x_b[6] & ex5_sh3_y_b[6])); + assign ex5_sh3[7] = (~(ex5_sh3_x_b[7] & ex5_sh3_y_b[7])); + assign ex5_sh3[8] = (~(ex5_sh3_x_b[8] & ex5_sh3_y_b[8])); + assign ex5_sh3[9] = (~(ex5_sh3_x_b[9] & ex5_sh3_y_b[9])); + assign ex5_sh3[10] = (~(ex5_sh3_x_b[10] & ex5_sh3_y_b[10])); + assign ex5_sh3[11] = (~(ex5_sh3_x_b[11] & ex5_sh3_y_b[11])); + assign ex5_sh3[12] = (~(ex5_sh3_x_b[12] & ex5_sh3_y_b[12])); + assign ex5_sh3[13] = (~(ex5_sh3_x_b[13] & ex5_sh3_y_b[13])); + assign ex5_sh3[14] = (~(ex5_sh3_x_b[14] & ex5_sh3_y_b[14])); + assign ex5_sh3[15] = (~(ex5_sh3_x_b[15] & ex5_sh3_y_b[15])); + assign ex5_sh3[16] = (~(ex5_sh3_x_b[16] & ex5_sh3_y_b[16])); + assign ex5_sh3[17] = (~(ex5_sh3_x_b[17] & ex5_sh3_y_b[17])); + assign ex5_sh3[18] = (~(ex5_sh3_x_b[18] & ex5_sh3_y_b[18])); + assign ex5_sh3[19] = (~(ex5_sh3_x_b[19] & ex5_sh3_y_b[19])); + assign ex5_sh3[20] = (~(ex5_sh3_x_b[20] & ex5_sh3_y_b[20])); + assign ex5_sh3[21] = (~(ex5_sh3_x_b[21] & ex5_sh3_y_b[21])); + assign ex5_sh3[22] = (~(ex5_sh3_x_b[22] & ex5_sh3_y_b[22])); + assign ex5_sh3[23] = (~(ex5_sh3_x_b[23] & ex5_sh3_y_b[23])); + assign ex5_sh3[24] = (~(ex5_sh3_x_b[24] & ex5_sh3_y_b[24])); + assign ex5_sh3[25] = (~(ex5_sh3_x_b[25] & ex5_sh3_y_b[25])); + assign ex5_sh3[26] = (~(ex5_sh3_x_b[26] & ex5_sh3_y_b[26])); + assign ex5_sh3[27] = (~(ex5_sh3_x_b[27] & ex5_sh3_y_b[27])); + assign ex5_sh3[28] = (~(ex5_sh3_x_b[28] & ex5_sh3_y_b[28])); + assign ex5_sh3[29] = (~(ex5_sh3_x_b[29] & ex5_sh3_y_b[29])); + assign ex5_sh3[30] = (~(ex5_sh3_x_b[30] & ex5_sh3_y_b[30])); + assign ex5_sh3[31] = (~(ex5_sh3_x_b[31] & ex5_sh3_y_b[31])); + assign ex5_sh3[32] = (~(ex5_sh3_x_b[32] & ex5_sh3_y_b[32])); + assign ex5_sh3[33] = (~(ex5_sh3_x_b[33] & ex5_sh3_y_b[33])); + assign ex5_sh3[34] = (~(ex5_sh3_x_b[34] & ex5_sh3_y_b[34])); + assign ex5_sh3[35] = (~(ex5_sh3_x_b[35] & ex5_sh3_y_b[35])); + assign ex5_sh3[36] = (~(ex5_sh3_x_b[36] & ex5_sh3_y_b[36])); + assign ex5_sh3[37] = (~(ex5_sh3_x_b[37] & ex5_sh3_y_b[37])); + assign ex5_sh3[38] = (~(ex5_sh3_x_b[38] & ex5_sh3_y_b[38])); + assign ex5_sh3[39] = (~(ex5_sh3_x_b[39] & ex5_sh3_y_b[39])); + assign ex5_sh3[40] = (~(ex5_sh3_x_b[40] & ex5_sh3_y_b[40])); + assign ex5_sh3[41] = (~(ex5_sh3_x_b[41] & ex5_sh3_y_b[41])); + assign ex5_sh3[42] = (~(ex5_sh3_x_b[42] & ex5_sh3_y_b[42])); + assign ex5_sh3[43] = (~(ex5_sh3_x_b[43] & ex5_sh3_y_b[43])); + assign ex5_sh3[44] = (~(ex5_sh3_x_b[44] & ex5_sh3_y_b[44])); + assign ex5_sh3[45] = (~(ex5_sh3_x_b[45] & ex5_sh3_y_b[45])); + assign ex5_sh3[46] = (~(ex5_sh3_x_b[46] & ex5_sh3_y_b[46])); + assign ex5_sh3[47] = (~(ex5_sh3_x_b[47] & ex5_sh3_y_b[47])); + assign ex5_sh3[48] = (~(ex5_sh3_x_b[48] & ex5_sh3_y_b[48])); + assign ex5_sh3[49] = (~(ex5_sh3_x_b[49] & ex5_sh3_y_b[49])); + assign ex5_sh3[50] = (~(ex5_sh3_x_b[50] & ex5_sh3_y_b[50])); + assign ex5_sh3[51] = (~(ex5_sh3_x_b[51] & ex5_sh3_y_b[51])); + assign ex5_sh3[52] = (~(ex5_sh3_x_b[52] & ex5_sh3_y_b[52])); + assign ex5_sh3[53] = (~(ex5_sh3_x_b[53] & ex5_sh3_y_b[53])); + assign ex5_sh3[54] = (~(ex5_sh3_x_b[54] & ex5_sh3_y_b[54])); + assign ex5_sh3[55] = (~(ex5_sh3_x_b[55] & ex5_sh3_y_b[55])); + assign ex5_sh3[56] = (~(ex5_sh3_x_b[56] & ex5_sh3_y_b[56])); + assign ex5_sh3[57] = (~(ex5_sh3_x_b[57] & ex5_sh3_y_b[57])); + + //--------------------------------------------- + + assign ex5_sh4_x_00_b = (~((ex5_sh3[0] & ex5_shctl_01[0]) | (ex5_sh3[1] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[0] = (~((ex5_sh3[0] & ex5_shctl_01[0]) | (ex5_sh3[1] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[1] = (~((ex5_sh3[1] & ex5_shctl_01[0]) | (ex5_sh3[2] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[2] = (~((ex5_sh3[2] & ex5_shctl_01[0]) | (ex5_sh3[3] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[3] = (~((ex5_sh3[3] & ex5_shctl_01[0]) | (ex5_sh3[4] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[4] = (~((ex5_sh3[4] & ex5_shctl_01[0]) | (ex5_sh3[5] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[5] = (~((ex5_sh3[5] & ex5_shctl_01[0]) | (ex5_sh3[6] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[6] = (~((ex5_sh3[6] & ex5_shctl_01[0]) | (ex5_sh3[7] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[7] = (~((ex5_sh3[7] & ex5_shctl_01[0]) | (ex5_sh3[8] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[8] = (~((ex5_sh3[8] & ex5_shctl_01[0]) | (ex5_sh3[9] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[9] = (~((ex5_sh3[9] & ex5_shctl_01[0]) | (ex5_sh3[10] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[10] = (~((ex5_sh3[10] & ex5_shctl_01[0]) | (ex5_sh3[11] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[11] = (~((ex5_sh3[11] & ex5_shctl_01[0]) | (ex5_sh3[12] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[12] = (~((ex5_sh3[12] & ex5_shctl_01[0]) | (ex5_sh3[13] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[13] = (~((ex5_sh3[13] & ex5_shctl_01[0]) | (ex5_sh3[14] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[14] = (~((ex5_sh3[14] & ex5_shctl_01[0]) | (ex5_sh3[15] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[15] = (~((ex5_sh3[15] & ex5_shctl_01[0]) | (ex5_sh3[16] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[16] = (~((ex5_sh3[16] & ex5_shctl_01[0]) | (ex5_sh3[17] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[17] = (~((ex5_sh3[17] & ex5_shctl_01[0]) | (ex5_sh3[18] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[18] = (~((ex5_sh3[18] & ex5_shctl_01[0]) | (ex5_sh3[19] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[19] = (~((ex5_sh3[19] & ex5_shctl_01[0]) | (ex5_sh3[20] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[20] = (~((ex5_sh3[20] & ex5_shctl_01[0]) | (ex5_sh3[21] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[21] = (~((ex5_sh3[21] & ex5_shctl_01[0]) | (ex5_sh3[22] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[22] = (~((ex5_sh3[22] & ex5_shctl_01[0]) | (ex5_sh3[23] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[23] = (~((ex5_sh3[23] & ex5_shctl_01[0]) | (ex5_sh3[24] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[24] = (~((ex5_sh3[24] & ex5_shctl_01[0]) | (ex5_sh3[25] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[25] = (~((ex5_sh3[25] & ex5_shctl_01[0]) | (ex5_sh3[26] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[26] = (~((ex5_sh3[26] & ex5_shctl_01[0]) | (ex5_sh3[27] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[27] = (~((ex5_sh3[27] & ex5_shctl_01[0]) | (ex5_sh3[28] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[28] = (~((ex5_sh3[28] & ex5_shctl_01[0]) | (ex5_sh3[29] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[29] = (~((ex5_sh3[29] & ex5_shctl_01[0]) | (ex5_sh3[30] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[30] = (~((ex5_sh3[30] & ex5_shctl_01[0]) | (ex5_sh3[31] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[31] = (~((ex5_sh3[31] & ex5_shctl_01[0]) | (ex5_sh3[32] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[32] = (~((ex5_sh3[32] & ex5_shctl_01[0]) | (ex5_sh3[33] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[33] = (~((ex5_sh3[33] & ex5_shctl_01[0]) | (ex5_sh3[34] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[34] = (~((ex5_sh3[34] & ex5_shctl_01[0]) | (ex5_sh3[35] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[35] = (~((ex5_sh3[35] & ex5_shctl_01[0]) | (ex5_sh3[36] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[36] = (~((ex5_sh3[36] & ex5_shctl_01[0]) | (ex5_sh3[37] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[37] = (~((ex5_sh3[37] & ex5_shctl_01[0]) | (ex5_sh3[38] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[38] = (~((ex5_sh3[38] & ex5_shctl_01[0]) | (ex5_sh3[39] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[39] = (~((ex5_sh3[39] & ex5_shctl_01[0]) | (ex5_sh3[40] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[40] = (~((ex5_sh3[40] & ex5_shctl_01[0]) | (ex5_sh3[41] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[41] = (~((ex5_sh3[41] & ex5_shctl_01[0]) | (ex5_sh3[42] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[42] = (~((ex5_sh3[42] & ex5_shctl_01[0]) | (ex5_sh3[43] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[43] = (~((ex5_sh3[43] & ex5_shctl_01[0]) | (ex5_sh3[44] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[44] = (~((ex5_sh3[44] & ex5_shctl_01[0]) | (ex5_sh3[45] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[45] = (~((ex5_sh3[45] & ex5_shctl_01[0]) | (ex5_sh3[46] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[46] = (~((ex5_sh3[46] & ex5_shctl_01[0]) | (ex5_sh3[47] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[47] = (~((ex5_sh3[47] & ex5_shctl_01[0]) | (ex5_sh3[48] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[48] = (~((ex5_sh3[48] & ex5_shctl_01[0]) | (ex5_sh3[49] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[49] = (~((ex5_sh3[49] & ex5_shctl_01[0]) | (ex5_sh3[50] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[50] = (~((ex5_sh3[50] & ex5_shctl_01[0]) | (ex5_sh3[51] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[51] = (~((ex5_sh3[51] & ex5_shctl_01[0]) | (ex5_sh3[52] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[52] = (~((ex5_sh3[52] & ex5_shctl_01[0]) | (ex5_sh3[53] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[53] = (~((ex5_sh3[53] & ex5_shctl_01[0]) | (ex5_sh3[54] & ex5_shctl_01[1]))); + assign ex5_sh4_x_b[54] = (~((ex5_sh3[54] & ex5_shctl_01[0]) | (ex5_sh3[55] & ex5_shctl_01[1]))); + + assign ex5_sh4_y_00_b = (~((ex5_sh3[2] & ex5_shctl_01[2]) | (ex5_sh3[3] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[0] = (~((ex5_sh3[2] & ex5_shctl_01[2]) | (ex5_sh3[3] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[1] = (~((ex5_sh3[3] & ex5_shctl_01[2]) | (ex5_sh3[4] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[2] = (~((ex5_sh3[4] & ex5_shctl_01[2]) | (ex5_sh3[5] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[3] = (~((ex5_sh3[5] & ex5_shctl_01[2]) | (ex5_sh3[6] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[4] = (~((ex5_sh3[6] & ex5_shctl_01[2]) | (ex5_sh3[7] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[5] = (~((ex5_sh3[7] & ex5_shctl_01[2]) | (ex5_sh3[8] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[6] = (~((ex5_sh3[8] & ex5_shctl_01[2]) | (ex5_sh3[9] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[7] = (~((ex5_sh3[9] & ex5_shctl_01[2]) | (ex5_sh3[10] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[8] = (~((ex5_sh3[10] & ex5_shctl_01[2]) | (ex5_sh3[11] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[9] = (~((ex5_sh3[11] & ex5_shctl_01[2]) | (ex5_sh3[12] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[10] = (~((ex5_sh3[12] & ex5_shctl_01[2]) | (ex5_sh3[13] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[11] = (~((ex5_sh3[13] & ex5_shctl_01[2]) | (ex5_sh3[14] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[12] = (~((ex5_sh3[14] & ex5_shctl_01[2]) | (ex5_sh3[15] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[13] = (~((ex5_sh3[15] & ex5_shctl_01[2]) | (ex5_sh3[16] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[14] = (~((ex5_sh3[16] & ex5_shctl_01[2]) | (ex5_sh3[17] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[15] = (~((ex5_sh3[17] & ex5_shctl_01[2]) | (ex5_sh3[18] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[16] = (~((ex5_sh3[18] & ex5_shctl_01[2]) | (ex5_sh3[19] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[17] = (~((ex5_sh3[19] & ex5_shctl_01[2]) | (ex5_sh3[20] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[18] = (~((ex5_sh3[20] & ex5_shctl_01[2]) | (ex5_sh3[21] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[19] = (~((ex5_sh3[21] & ex5_shctl_01[2]) | (ex5_sh3[22] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[20] = (~((ex5_sh3[22] & ex5_shctl_01[2]) | (ex5_sh3[23] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[21] = (~((ex5_sh3[23] & ex5_shctl_01[2]) | (ex5_sh3[24] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[22] = (~((ex5_sh3[24] & ex5_shctl_01[2]) | (ex5_sh3[25] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[23] = (~((ex5_sh3[25] & ex5_shctl_01[2]) | (ex5_sh3[26] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[24] = (~((ex5_sh3[26] & ex5_shctl_01[2]) | (ex5_sh3[27] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[25] = (~((ex5_sh3[27] & ex5_shctl_01[2]) | (ex5_sh3[28] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[26] = (~((ex5_sh3[28] & ex5_shctl_01[2]) | (ex5_sh3[29] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[27] = (~((ex5_sh3[29] & ex5_shctl_01[2]) | (ex5_sh3[30] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[28] = (~((ex5_sh3[30] & ex5_shctl_01[2]) | (ex5_sh3[31] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[29] = (~((ex5_sh3[31] & ex5_shctl_01[2]) | (ex5_sh3[32] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[30] = (~((ex5_sh3[32] & ex5_shctl_01[2]) | (ex5_sh3[33] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[31] = (~((ex5_sh3[33] & ex5_shctl_01[2]) | (ex5_sh3[34] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[32] = (~((ex5_sh3[34] & ex5_shctl_01[2]) | (ex5_sh3[35] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[33] = (~((ex5_sh3[35] & ex5_shctl_01[2]) | (ex5_sh3[36] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[34] = (~((ex5_sh3[36] & ex5_shctl_01[2]) | (ex5_sh3[37] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[35] = (~((ex5_sh3[37] & ex5_shctl_01[2]) | (ex5_sh3[38] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[36] = (~((ex5_sh3[38] & ex5_shctl_01[2]) | (ex5_sh3[39] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[37] = (~((ex5_sh3[39] & ex5_shctl_01[2]) | (ex5_sh3[40] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[38] = (~((ex5_sh3[40] & ex5_shctl_01[2]) | (ex5_sh3[41] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[39] = (~((ex5_sh3[41] & ex5_shctl_01[2]) | (ex5_sh3[42] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[40] = (~((ex5_sh3[42] & ex5_shctl_01[2]) | (ex5_sh3[43] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[41] = (~((ex5_sh3[43] & ex5_shctl_01[2]) | (ex5_sh3[44] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[42] = (~((ex5_sh3[44] & ex5_shctl_01[2]) | (ex5_sh3[45] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[43] = (~((ex5_sh3[45] & ex5_shctl_01[2]) | (ex5_sh3[46] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[44] = (~((ex5_sh3[46] & ex5_shctl_01[2]) | (ex5_sh3[47] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[45] = (~((ex5_sh3[47] & ex5_shctl_01[2]) | (ex5_sh3[48] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[46] = (~((ex5_sh3[48] & ex5_shctl_01[2]) | (ex5_sh3[49] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[47] = (~((ex5_sh3[49] & ex5_shctl_01[2]) | (ex5_sh3[50] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[48] = (~((ex5_sh3[50] & ex5_shctl_01[2]) | (ex5_sh3[51] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[49] = (~((ex5_sh3[51] & ex5_shctl_01[2]) | (ex5_sh3[52] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[50] = (~((ex5_sh3[52] & ex5_shctl_01[2]) | (ex5_sh3[53] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[51] = (~((ex5_sh3[53] & ex5_shctl_01[2]) | (ex5_sh3[54] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[52] = (~((ex5_sh3[54] & ex5_shctl_01[2]) | (ex5_sh3[55] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[53] = (~((ex5_sh3[55] & ex5_shctl_01[2]) | (ex5_sh3[56] & ex5_shctl_01[3]))); + assign ex5_sh4_y_b[54] = (~((ex5_sh3[56] & ex5_shctl_01[2]) | (ex5_sh3[57] & ex5_shctl_01[3]))); + + assign ex5_shift_extra_cp1_b = (~(ex5_sh4_x_00_b & ex5_sh4_y_00_b)); // shift extra when implicit bit is not 1 + assign ex5_shift_extra_cp2_b = (~(ex5_sh4_x_00_b & ex5_sh4_y_00_b)); // shift extra when implicit bit is not 1 + assign ex5_shift_extra_00_cp3_b = (~(ex5_sh4_x_b[0] & ex5_sh4_y_b[0])); // shift extra when implicit bit is not 1 + assign ex5_shift_extra_00_cp4_b = (~(ex5_sh4_x_b[0] & ex5_sh4_y_b[0])); // shift extra when implicit bit is not 1 + + assign ex5_shift_extra_cp1 = (~ex5_shift_extra_cp1_b); //output-- + assign ex5_shift_extra_cp2 = (~ex5_shift_extra_cp2_b); //output-- + + assign ex5_shift_extra_10_cp3 = (~ex5_shift_extra_00_cp3_b); // x4 + assign ex5_shift_extra_20_cp3_b = (~ex5_shift_extra_10_cp3); // x6 + assign ex5_shift_extra_cp3 = (~ex5_shift_extra_20_cp3_b); // x9 + + assign ex5_shift_extra_11_cp3 = (~ex5_shift_extra_00_cp3_b); // x2 + assign ex5_shift_extra_21_cp3_b = (~ex5_shift_extra_11_cp3); // x4 + assign ex5_shift_extra_31_cp3 = (~ex5_shift_extra_21_cp3_b); // x6 + assign ex5_shift_extra_cp3_b = (~ex5_shift_extra_31_cp3); // x9 + + assign ex5_shift_extra_10_cp4 = (~ex5_shift_extra_00_cp4_b); // x4 + assign ex5_shift_extra_20_cp4_b = (~ex5_shift_extra_10_cp4); // x6 + assign ex5_shift_extra_cp4 = (~ex5_shift_extra_20_cp4_b); // x9 + + assign ex5_shift_extra_11_cp4 = (~ex5_shift_extra_00_cp4_b); // x2 + assign ex5_shift_extra_21_cp4_b = (~ex5_shift_extra_11_cp4); // x4 + assign ex5_shift_extra_31_cp4 = (~ex5_shift_extra_21_cp4_b); // x6 + assign ex5_shift_extra_cp4_b = (~ex5_shift_extra_31_cp4); // x9 + + assign ex5_sh4[0] = (~(ex5_sh4_x_b[0] & ex5_sh4_y_b[0])); + assign ex5_sh4[1] = (~(ex5_sh4_x_b[1] & ex5_sh4_y_b[1])); + assign ex5_sh4[2] = (~(ex5_sh4_x_b[2] & ex5_sh4_y_b[2])); + assign ex5_sh4[3] = (~(ex5_sh4_x_b[3] & ex5_sh4_y_b[3])); + assign ex5_sh4[4] = (~(ex5_sh4_x_b[4] & ex5_sh4_y_b[4])); + assign ex5_sh4[5] = (~(ex5_sh4_x_b[5] & ex5_sh4_y_b[5])); + assign ex5_sh4[6] = (~(ex5_sh4_x_b[6] & ex5_sh4_y_b[6])); + assign ex5_sh4[7] = (~(ex5_sh4_x_b[7] & ex5_sh4_y_b[7])); + assign ex5_sh4[8] = (~(ex5_sh4_x_b[8] & ex5_sh4_y_b[8])); + assign ex5_sh4[9] = (~(ex5_sh4_x_b[9] & ex5_sh4_y_b[9])); + assign ex5_sh4[10] = (~(ex5_sh4_x_b[10] & ex5_sh4_y_b[10])); + assign ex5_sh4[11] = (~(ex5_sh4_x_b[11] & ex5_sh4_y_b[11])); + assign ex5_sh4[12] = (~(ex5_sh4_x_b[12] & ex5_sh4_y_b[12])); + assign ex5_sh4[13] = (~(ex5_sh4_x_b[13] & ex5_sh4_y_b[13])); + assign ex5_sh4[14] = (~(ex5_sh4_x_b[14] & ex5_sh4_y_b[14])); + assign ex5_sh4[15] = (~(ex5_sh4_x_b[15] & ex5_sh4_y_b[15])); + assign ex5_sh4[16] = (~(ex5_sh4_x_b[16] & ex5_sh4_y_b[16])); + assign ex5_sh4[17] = (~(ex5_sh4_x_b[17] & ex5_sh4_y_b[17])); + assign ex5_sh4[18] = (~(ex5_sh4_x_b[18] & ex5_sh4_y_b[18])); + assign ex5_sh4[19] = (~(ex5_sh4_x_b[19] & ex5_sh4_y_b[19])); + assign ex5_sh4[20] = (~(ex5_sh4_x_b[20] & ex5_sh4_y_b[20])); + assign ex5_sh4[21] = (~(ex5_sh4_x_b[21] & ex5_sh4_y_b[21])); + assign ex5_sh4[22] = (~(ex5_sh4_x_b[22] & ex5_sh4_y_b[22])); + assign ex5_sh4[23] = (~(ex5_sh4_x_b[23] & ex5_sh4_y_b[23])); + assign ex5_sh4[24] = (~(ex5_sh4_x_b[24] & ex5_sh4_y_b[24])); + assign ex5_sh4[25] = (~(ex5_sh4_x_b[25] & ex5_sh4_y_b[25])); + assign ex5_sh4[26] = (~(ex5_sh4_x_b[26] & ex5_sh4_y_b[26])); + assign ex5_sh4[27] = (~(ex5_sh4_x_b[27] & ex5_sh4_y_b[27])); + assign ex5_sh4[28] = (~(ex5_sh4_x_b[28] & ex5_sh4_y_b[28])); + assign ex5_sh4[29] = (~(ex5_sh4_x_b[29] & ex5_sh4_y_b[29])); + assign ex5_sh4[30] = (~(ex5_sh4_x_b[30] & ex5_sh4_y_b[30])); + assign ex5_sh4[31] = (~(ex5_sh4_x_b[31] & ex5_sh4_y_b[31])); + assign ex5_sh4[32] = (~(ex5_sh4_x_b[32] & ex5_sh4_y_b[32])); + assign ex5_sh4[33] = (~(ex5_sh4_x_b[33] & ex5_sh4_y_b[33])); + assign ex5_sh4[34] = (~(ex5_sh4_x_b[34] & ex5_sh4_y_b[34])); + assign ex5_sh4[35] = (~(ex5_sh4_x_b[35] & ex5_sh4_y_b[35])); + assign ex5_sh4[36] = (~(ex5_sh4_x_b[36] & ex5_sh4_y_b[36])); + assign ex5_sh4[37] = (~(ex5_sh4_x_b[37] & ex5_sh4_y_b[37])); + assign ex5_sh4[38] = (~(ex5_sh4_x_b[38] & ex5_sh4_y_b[38])); + assign ex5_sh4[39] = (~(ex5_sh4_x_b[39] & ex5_sh4_y_b[39])); + assign ex5_sh4[40] = (~(ex5_sh4_x_b[40] & ex5_sh4_y_b[40])); + assign ex5_sh4[41] = (~(ex5_sh4_x_b[41] & ex5_sh4_y_b[41])); + assign ex5_sh4[42] = (~(ex5_sh4_x_b[42] & ex5_sh4_y_b[42])); + assign ex5_sh4[43] = (~(ex5_sh4_x_b[43] & ex5_sh4_y_b[43])); + assign ex5_sh4[44] = (~(ex5_sh4_x_b[44] & ex5_sh4_y_b[44])); + assign ex5_sh4[45] = (~(ex5_sh4_x_b[45] & ex5_sh4_y_b[45])); + assign ex5_sh4[46] = (~(ex5_sh4_x_b[46] & ex5_sh4_y_b[46])); + assign ex5_sh4[47] = (~(ex5_sh4_x_b[47] & ex5_sh4_y_b[47])); + assign ex5_sh4[48] = (~(ex5_sh4_x_b[48] & ex5_sh4_y_b[48])); + assign ex5_sh4[49] = (~(ex5_sh4_x_b[49] & ex5_sh4_y_b[49])); + assign ex5_sh4[50] = (~(ex5_sh4_x_b[50] & ex5_sh4_y_b[50])); + assign ex5_sh4[51] = (~(ex5_sh4_x_b[51] & ex5_sh4_y_b[51])); + assign ex5_sh4[52] = (~(ex5_sh4_x_b[52] & ex5_sh4_y_b[52])); + assign ex5_sh4[53] = (~(ex5_sh4_x_b[53] & ex5_sh4_y_b[53])); + assign ex5_sh4[54] = (~(ex5_sh4_x_b[54] & ex5_sh4_y_b[54])); + + //--------------------------------------------- + + assign ex5_sh5_x_b[0] = (~(ex5_sh4[0] & ex5_shift_extra_cp3_b)); + assign ex5_sh5_x_b[1] = (~(ex5_sh4[1] & ex5_shift_extra_cp3_b)); + assign ex5_sh5_x_b[2] = (~(ex5_sh4[2] & ex5_shift_extra_cp3_b)); + assign ex5_sh5_x_b[3] = (~(ex5_sh4[3] & ex5_shift_extra_cp3_b)); + assign ex5_sh5_x_b[4] = (~(ex5_sh4[4] & ex5_shift_extra_cp3_b)); + assign ex5_sh5_x_b[5] = (~(ex5_sh4[5] & ex5_shift_extra_cp3_b)); + assign ex5_sh5_x_b[6] = (~(ex5_sh4[6] & ex5_shift_extra_cp3_b)); + assign ex5_sh5_x_b[7] = (~(ex5_sh4[7] & ex5_shift_extra_cp3_b)); + assign ex5_sh5_x_b[8] = (~(ex5_sh4[8] & ex5_shift_extra_cp3_b)); + assign ex5_sh5_x_b[9] = (~(ex5_sh4[9] & ex5_shift_extra_cp3_b)); + assign ex5_sh5_x_b[10] = (~(ex5_sh4[10] & ex5_shift_extra_cp3_b)); + assign ex5_sh5_x_b[11] = (~(ex5_sh4[11] & ex5_shift_extra_cp3_b)); + assign ex5_sh5_x_b[12] = (~(ex5_sh4[12] & ex5_shift_extra_cp3_b)); + assign ex5_sh5_x_b[13] = (~(ex5_sh4[13] & ex5_shift_extra_cp3_b)); + assign ex5_sh5_x_b[14] = (~(ex5_sh4[14] & ex5_shift_extra_cp3_b)); + assign ex5_sh5_x_b[15] = (~(ex5_sh4[15] & ex5_shift_extra_cp3_b)); + assign ex5_sh5_x_b[16] = (~(ex5_sh4[16] & ex5_shift_extra_cp3_b)); + assign ex5_sh5_x_b[17] = (~(ex5_sh4[17] & ex5_shift_extra_cp3_b)); + assign ex5_sh5_x_b[18] = (~(ex5_sh4[18] & ex5_shift_extra_cp3_b)); + assign ex5_sh5_x_b[19] = (~(ex5_sh4[19] & ex5_shift_extra_cp3_b)); + assign ex5_sh5_x_b[20] = (~(ex5_sh4[20] & ex5_shift_extra_cp3_b)); + assign ex5_sh5_x_b[21] = (~(ex5_sh4[21] & ex5_shift_extra_cp3_b)); + assign ex5_sh5_x_b[22] = (~(ex5_sh4[22] & ex5_shift_extra_cp3_b)); + assign ex5_sh5_x_b[23] = (~(ex5_sh4[23] & ex5_shift_extra_cp3_b)); + assign ex5_sh5_x_b[24] = (~(ex5_sh4[24] & ex5_shift_extra_cp3_b)); + assign ex5_sh5_x_b[25] = (~(ex5_sh4[25] & ex5_shift_extra_cp3_b)); + assign ex5_sh5_x_b[26] = (~(ex5_sh4[26] & ex5_shift_extra_cp4_b)); + assign ex5_sh5_x_b[27] = (~(ex5_sh4[27] & ex5_shift_extra_cp4_b)); + assign ex5_sh5_x_b[28] = (~(ex5_sh4[28] & ex5_shift_extra_cp4_b)); + assign ex5_sh5_x_b[29] = (~(ex5_sh4[29] & ex5_shift_extra_cp4_b)); + assign ex5_sh5_x_b[30] = (~(ex5_sh4[30] & ex5_shift_extra_cp4_b)); + assign ex5_sh5_x_b[31] = (~(ex5_sh4[31] & ex5_shift_extra_cp4_b)); + assign ex5_sh5_x_b[32] = (~(ex5_sh4[32] & ex5_shift_extra_cp4_b)); + assign ex5_sh5_x_b[33] = (~(ex5_sh4[33] & ex5_shift_extra_cp4_b)); + assign ex5_sh5_x_b[34] = (~(ex5_sh4[34] & ex5_shift_extra_cp4_b)); + assign ex5_sh5_x_b[35] = (~(ex5_sh4[35] & ex5_shift_extra_cp4_b)); + assign ex5_sh5_x_b[36] = (~(ex5_sh4[36] & ex5_shift_extra_cp4_b)); + assign ex5_sh5_x_b[37] = (~(ex5_sh4[37] & ex5_shift_extra_cp4_b)); + assign ex5_sh5_x_b[38] = (~(ex5_sh4[38] & ex5_shift_extra_cp4_b)); + assign ex5_sh5_x_b[39] = (~(ex5_sh4[39] & ex5_shift_extra_cp4_b)); + assign ex5_sh5_x_b[40] = (~(ex5_sh4[40] & ex5_shift_extra_cp4_b)); + assign ex5_sh5_x_b[41] = (~(ex5_sh4[41] & ex5_shift_extra_cp4_b)); + assign ex5_sh5_x_b[42] = (~(ex5_sh4[42] & ex5_shift_extra_cp4_b)); + assign ex5_sh5_x_b[43] = (~(ex5_sh4[43] & ex5_shift_extra_cp4_b)); + assign ex5_sh5_x_b[44] = (~(ex5_sh4[44] & ex5_shift_extra_cp4_b)); + assign ex5_sh5_x_b[45] = (~(ex5_sh4[45] & ex5_shift_extra_cp4_b)); + assign ex5_sh5_x_b[46] = (~(ex5_sh4[46] & ex5_shift_extra_cp4_b)); + assign ex5_sh5_x_b[47] = (~(ex5_sh4[47] & ex5_shift_extra_cp4_b)); + assign ex5_sh5_x_b[48] = (~(ex5_sh4[48] & ex5_shift_extra_cp4_b)); + assign ex5_sh5_x_b[49] = (~(ex5_sh4[49] & ex5_shift_extra_cp4_b)); + assign ex5_sh5_x_b[50] = (~(ex5_sh4[50] & ex5_shift_extra_cp4_b)); + assign ex5_sh5_x_b[51] = (~(ex5_sh4[51] & ex5_shift_extra_cp4_b)); + assign ex5_sh5_x_b[52] = (~(ex5_sh4[52] & ex5_shift_extra_cp4_b)); + assign ex5_sh5_x_b[53] = (~(ex5_sh4[53] & ex5_shift_extra_cp4_b)); + + assign ex5_sh5_y_b[0] = (~(ex5_sh4[1] & ex5_shift_extra_cp3)); + assign ex5_sh5_y_b[1] = (~(ex5_sh4[2] & ex5_shift_extra_cp3)); + assign ex5_sh5_y_b[2] = (~(ex5_sh4[3] & ex5_shift_extra_cp3)); + assign ex5_sh5_y_b[3] = (~(ex5_sh4[4] & ex5_shift_extra_cp3)); + assign ex5_sh5_y_b[4] = (~(ex5_sh4[5] & ex5_shift_extra_cp3)); + assign ex5_sh5_y_b[5] = (~(ex5_sh4[6] & ex5_shift_extra_cp3)); + assign ex5_sh5_y_b[6] = (~(ex5_sh4[7] & ex5_shift_extra_cp3)); + assign ex5_sh5_y_b[7] = (~(ex5_sh4[8] & ex5_shift_extra_cp3)); + assign ex5_sh5_y_b[8] = (~(ex5_sh4[9] & ex5_shift_extra_cp3)); + assign ex5_sh5_y_b[9] = (~(ex5_sh4[10] & ex5_shift_extra_cp3)); + assign ex5_sh5_y_b[10] = (~(ex5_sh4[11] & ex5_shift_extra_cp3)); + assign ex5_sh5_y_b[11] = (~(ex5_sh4[12] & ex5_shift_extra_cp3)); + assign ex5_sh5_y_b[12] = (~(ex5_sh4[13] & ex5_shift_extra_cp3)); + assign ex5_sh5_y_b[13] = (~(ex5_sh4[14] & ex5_shift_extra_cp3)); + assign ex5_sh5_y_b[14] = (~(ex5_sh4[15] & ex5_shift_extra_cp3)); + assign ex5_sh5_y_b[15] = (~(ex5_sh4[16] & ex5_shift_extra_cp3)); + assign ex5_sh5_y_b[16] = (~(ex5_sh4[17] & ex5_shift_extra_cp3)); + assign ex5_sh5_y_b[17] = (~(ex5_sh4[18] & ex5_shift_extra_cp3)); + assign ex5_sh5_y_b[18] = (~(ex5_sh4[19] & ex5_shift_extra_cp3)); + assign ex5_sh5_y_b[19] = (~(ex5_sh4[20] & ex5_shift_extra_cp3)); + assign ex5_sh5_y_b[20] = (~(ex5_sh4[21] & ex5_shift_extra_cp3)); + assign ex5_sh5_y_b[21] = (~(ex5_sh4[22] & ex5_shift_extra_cp3)); + assign ex5_sh5_y_b[22] = (~(ex5_sh4[23] & ex5_shift_extra_cp3)); + assign ex5_sh5_y_b[23] = (~(ex5_sh4[24] & ex5_shift_extra_cp3)); + assign ex5_sh5_y_b[24] = (~(ex5_sh4[25] & ex5_shift_extra_cp3)); + assign ex5_sh5_y_b[25] = (~(ex5_sh4[26] & ex5_shift_extra_cp3)); + assign ex5_sh5_y_b[26] = (~(ex5_sh4[27] & ex5_shift_extra_cp4)); + assign ex5_sh5_y_b[27] = (~(ex5_sh4[28] & ex5_shift_extra_cp4)); + assign ex5_sh5_y_b[28] = (~(ex5_sh4[29] & ex5_shift_extra_cp4)); + assign ex5_sh5_y_b[29] = (~(ex5_sh4[30] & ex5_shift_extra_cp4)); + assign ex5_sh5_y_b[30] = (~(ex5_sh4[31] & ex5_shift_extra_cp4)); + assign ex5_sh5_y_b[31] = (~(ex5_sh4[32] & ex5_shift_extra_cp4)); + assign ex5_sh5_y_b[32] = (~(ex5_sh4[33] & ex5_shift_extra_cp4)); + assign ex5_sh5_y_b[33] = (~(ex5_sh4[34] & ex5_shift_extra_cp4)); + assign ex5_sh5_y_b[34] = (~(ex5_sh4[35] & ex5_shift_extra_cp4)); + assign ex5_sh5_y_b[35] = (~(ex5_sh4[36] & ex5_shift_extra_cp4)); + assign ex5_sh5_y_b[36] = (~(ex5_sh4[37] & ex5_shift_extra_cp4)); + assign ex5_sh5_y_b[37] = (~(ex5_sh4[38] & ex5_shift_extra_cp4)); + assign ex5_sh5_y_b[38] = (~(ex5_sh4[39] & ex5_shift_extra_cp4)); + assign ex5_sh5_y_b[39] = (~(ex5_sh4[40] & ex5_shift_extra_cp4)); + assign ex5_sh5_y_b[40] = (~(ex5_sh4[41] & ex5_shift_extra_cp4)); + assign ex5_sh5_y_b[41] = (~(ex5_sh4[42] & ex5_shift_extra_cp4)); + assign ex5_sh5_y_b[42] = (~(ex5_sh4[43] & ex5_shift_extra_cp4)); + assign ex5_sh5_y_b[43] = (~(ex5_sh4[44] & ex5_shift_extra_cp4)); + assign ex5_sh5_y_b[44] = (~(ex5_sh4[45] & ex5_shift_extra_cp4)); + assign ex5_sh5_y_b[45] = (~(ex5_sh4[46] & ex5_shift_extra_cp4)); + assign ex5_sh5_y_b[46] = (~(ex5_sh4[47] & ex5_shift_extra_cp4)); + assign ex5_sh5_y_b[47] = (~(ex5_sh4[48] & ex5_shift_extra_cp4)); + assign ex5_sh5_y_b[48] = (~(ex5_sh4[49] & ex5_shift_extra_cp4)); + assign ex5_sh5_y_b[49] = (~(ex5_sh4[50] & ex5_shift_extra_cp4)); + assign ex5_sh5_y_b[50] = (~(ex5_sh4[51] & ex5_shift_extra_cp4)); + assign ex5_sh5_y_b[51] = (~(ex5_sh4[52] & ex5_shift_extra_cp4)); + assign ex5_sh5_y_b[52] = (~(ex5_sh4[53] & ex5_shift_extra_cp4)); + assign ex5_sh5_y_b[53] = (~(ex5_sh4[54] & ex5_shift_extra_cp4)); + +endmodule diff --git a/dev/verilog/work/fu_oscr.v b/dev/verilog/work/fu_oscr.v new file mode 100755 index 0000000..3232de2 --- /dev/null +++ b/dev/verilog/work/fu_oscr.v @@ -0,0 +1,2718 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +////## some inputs and their latches can be droped (fr/fi always enabled together) +////## (ox/ux always enabled together) +////## spec always sets fr=fi=ox=ux=0 +////############################################################################## + +// cyc ex5 NORM : fpscr_rd +// cyc ex6 RND : +// cyc ex7 FPSCR : fpscr_wr +// +// +// FPSCR BIT DEFINITIONS +// ---------------- status 3:12,21:23 resetable +// [ 0] fx exception transition 0->1 (except mtfs,mtfsi) +// [ 1] fex "or" of enabled exceptions +// [ 2] vex "or" of invalid exceptions +// [ 3] ox +// [ 4] ux +// [ 5] zx +// [ 6] xx +// [ 7] vxsnan +// [ 8] vxisi (inf-sub-inf) +// [ 9] vxidi +// [10] vxzdz +// [11] vximz +// [12] vxvc +// [13] fr +// [14] fi +// [15] FPRF C +// [16] FPRF fpcc(lt) +// [17] FPRF fpcc(gt) +// [18] FPRF fpcc(eq) +// [19] FPRF fpcc(nan) +// [20] RESERVED +// [21] vx-soft +// [22] vx-sqrt +// [23] vx-vci +// -------------- control +// [24] ve +// [25] oe +// [26] ue +// [27] ze +// [28] xe +// [29] non-ieee +// [30:31] rnd_mode 00:nr 01:zr 02:pi 03:ni +//--------------- +// FPRF +// 10001 QNAN [0] qnan | den | (sign*zero) +// 01001 -INF [1] sign * !zero +// 01000 -norm [2] !sign * !zero * !qnan +// 11000 -den [3] zero +// 10010 -zero [4] inf | qnan +// 00010 +zero +// 10100 +den +// 00100 +norm +// 00101 +inf + +// tvc -F -B -T -O joboutput -c "tri=head" -src fu_divsqrt.vhdl + + `include "tri_a2o.vh" + + +module fu_oscr( + vdd, + gnd, + clkoff_b, + act_dis, + flush, + delay_lclkr, + mpw1_b, + mpw2_b, + sg_1, + thold_1, + fpu_enable, + nclk, + f_scr_si, + f_scr_so, + ex3_act_b, + f_cr2_ex4_thread_b, + f_pic_ex6_scr_upd_move_b, + f_pic_ex6_scr_upd_pipe_b, + f_dcd_ex7_cancel, + f_pic_ex6_fprf_spec_b, + f_pic_ex6_compare_b, + f_pic_ex6_fprf_pipe_v_b, + f_pic_ex6_fprf_hold_b, + f_pic_ex6_fi_spec_b, + f_pic_ex6_fi_pipe_v_b, + f_pic_ex6_fr_spec_b, + f_pic_ex6_fr_pipe_v_b, + f_pic_ex6_ox_spec_b, + f_pic_ex6_ox_pipe_v_b, + f_pic_ex6_ux_spec_b, + f_pic_ex6_ux_pipe_v_b, + f_pic_ex6_flag_vxsnan_b, + f_pic_ex6_flag_vxisi_b, + f_pic_ex6_flag_vxidi_b, + f_pic_ex6_flag_vxzdz_b, + f_pic_ex6_flag_vximz_b, + f_pic_ex6_flag_vxvc_b, + f_pic_ex6_flag_vxsqrt_b, + f_pic_ex6_flag_vxcvi_b, + f_pic_ex6_flag_zx_b, + f_cr2_ex4_fpscr_bit_data_b, + f_cr2_ex4_fpscr_bit_mask_b, + f_cr2_ex4_fpscr_nib_mask_b, + f_cr2_ex4_mcrfs_b, + f_cr2_ex4_mtfsf_b, + f_cr2_ex4_mtfsfi_b, + f_cr2_ex4_mtfsbx_b, + f_nrm_ex6_fpscr_wr_dat_dfp, + f_scr_ex6_fpscr_rd_dat_dfp, + f_nrm_ex6_fpscr_wr_dat, + f_cr2_ex7_fpscr_rd_dat, + f_cr2_ex6_fpscr_rd_dat, + f_scr_ex6_fpscr_rd_dat, + f_scr_fpscr_ctrl_thr0, + f_scr_fpscr_ctrl_thr1, + f_scr_ex6_fpscr_rm_thr0, + f_scr_ex6_fpscr_ee_thr0, + f_scr_ex6_fpscr_ni_thr0, + f_scr_ex6_fpscr_rm_thr1, + f_scr_ex6_fpscr_ee_thr1, + f_scr_ex6_fpscr_ni_thr1, + f_dsq_ex6_divsqrt_v, + f_dsq_ex6_divsqrt_v_suppress, + f_dsq_ex6_divsqrt_flag_fpscr_zx, + f_dsq_ex6_divsqrt_flag_fpscr_idi, + f_dsq_ex6_divsqrt_flag_fpscr_zdz, + f_dsq_ex6_divsqrt_flag_fpscr_sqrt, + f_dsq_ex6_divsqrt_flag_fpscr_nan, + f_dsq_ex6_divsqrt_flag_fpscr_snan, + f_rnd_ex7_flag_up, + f_rnd_ex7_flag_fi, + f_rnd_ex7_flag_ox, + f_rnd_ex7_flag_den, + f_rnd_ex7_flag_sgn, + f_rnd_ex7_flag_inf, + f_rnd_ex7_flag_zer, + f_rnd_ex7_flag_ux, + f_dcd_ex7_fpscr_wr, + f_dcd_ex7_fpscr_addr, + cp_axu_i0_t1_v, + cp_axu_i0_t0_t1_t, + cp_axu_i0_t1_t1_t, + cp_axu_i0_t0_t1_p, + cp_axu_i0_t1_t1_p, + cp_axu_i1_t1_v, + cp_axu_i1_t0_t1_t, + cp_axu_i1_t1_t1_t, + cp_axu_i1_t0_t1_p, + cp_axu_i1_t1_t1_p, + f_scr_ex8_cr_fld, + f_scr_ex8_fx_thread0, + f_scr_ex8_fx_thread1, + f_scr_cpl_fx_thread0, + f_scr_cpl_fx_thread1 +); + parameter THREADS = 2; + + inout vdd; + inout gnd; + input clkoff_b; // tiup + input act_dis; // ??tidn?? + input flush; // ??tidn?? + input [4:7] delay_lclkr; // tidn, + input [4:7] mpw1_b; // tidn, + input [0:1] mpw2_b; // tidn, + input sg_1; + input thold_1; + input fpu_enable; //dc_act + input [0:`NCLK_WIDTH-1] nclk; + + input f_scr_si; // perv + output f_scr_so; // perv + input ex3_act_b; // act writes + input [0:3] f_cr2_ex4_thread_b; // thread write + input f_pic_ex6_scr_upd_move_b; + input f_pic_ex6_scr_upd_pipe_b; + input f_dcd_ex7_cancel; + input [0:4] f_pic_ex6_fprf_spec_b; //FPRF for special cases + input f_pic_ex6_compare_b; + input f_pic_ex6_fprf_pipe_v_b; + input f_pic_ex6_fprf_hold_b; //compare + input f_pic_ex6_fi_spec_b; + input f_pic_ex6_fi_pipe_v_b; + input f_pic_ex6_fr_spec_b; + input f_pic_ex6_fr_pipe_v_b; + input f_pic_ex6_ox_spec_b; + input f_pic_ex6_ox_pipe_v_b; + input f_pic_ex6_ux_spec_b; + input f_pic_ex6_ux_pipe_v_b; + input f_pic_ex6_flag_vxsnan_b; ////# sig_nan + input f_pic_ex6_flag_vxisi_b; ////# inf_sub_inf + input f_pic_ex6_flag_vxidi_b; ////# inf_div_inf + input f_pic_ex6_flag_vxzdz_b; ////# zer_div_zer + input f_pic_ex6_flag_vximz_b; ////# inf_mul_zer + input f_pic_ex6_flag_vxvc_b; ////# inval_cmp + input f_pic_ex6_flag_vxsqrt_b; ////# inval_sqrt + input f_pic_ex6_flag_vxcvi_b; ////# inval_convert + input f_pic_ex6_flag_zx_b; ////# div_zer + + input [0:3] f_cr2_ex4_fpscr_bit_data_b; + input [0:3] f_cr2_ex4_fpscr_bit_mask_b; + input [0:8] f_cr2_ex4_fpscr_nib_mask_b; + input f_cr2_ex4_mcrfs_b; + input f_cr2_ex4_mtfsf_b; + input f_cr2_ex4_mtfsfi_b; + input f_cr2_ex4_mtfsbx_b; + + input [0:3] f_nrm_ex6_fpscr_wr_dat_dfp; + output [0:3] f_scr_ex6_fpscr_rd_dat_dfp; + + input [0:31] f_nrm_ex6_fpscr_wr_dat; + + input [24:31] f_cr2_ex7_fpscr_rd_dat; ////# for update + input [24:31] f_cr2_ex6_fpscr_rd_dat; ////# for mffs + output [0:31] f_scr_ex6_fpscr_rd_dat; ////# f_rnd + output [0:7] f_scr_fpscr_ctrl_thr0; + output [0:7] f_scr_fpscr_ctrl_thr1; + output [0:1] f_scr_ex6_fpscr_rm_thr0; ////# to fu_divsqrt + output [0:4] f_scr_ex6_fpscr_ee_thr0; ////# to fu_divsqrt + output f_scr_ex6_fpscr_ni_thr0; + + output [0:1] f_scr_ex6_fpscr_rm_thr1; ////# to fu_divsqrt + output [0:4] f_scr_ex6_fpscr_ee_thr1; ////# to fu_divsqrt + output f_scr_ex6_fpscr_ni_thr1; + + input [0:1] f_dsq_ex6_divsqrt_v; + input f_dsq_ex6_divsqrt_v_suppress; + + input f_dsq_ex6_divsqrt_flag_fpscr_zx; + input f_dsq_ex6_divsqrt_flag_fpscr_idi; + input f_dsq_ex6_divsqrt_flag_fpscr_zdz; + input f_dsq_ex6_divsqrt_flag_fpscr_sqrt; + input f_dsq_ex6_divsqrt_flag_fpscr_nan; + input f_dsq_ex6_divsqrt_flag_fpscr_snan; + + input f_rnd_ex7_flag_up; + input f_rnd_ex7_flag_fi; + input f_rnd_ex7_flag_ox; + input f_rnd_ex7_flag_den; + input f_rnd_ex7_flag_sgn; + input f_rnd_ex7_flag_inf; + input f_rnd_ex7_flag_zer; + input f_rnd_ex7_flag_ux; + + input f_dcd_ex7_fpscr_wr; + input [0:5] f_dcd_ex7_fpscr_addr; + + input [0:THREADS-1] cp_axu_i0_t1_v; + input [0:2] cp_axu_i0_t0_t1_t; + input [0:2] cp_axu_i0_t1_t1_t; + input [0:5] cp_axu_i0_t0_t1_p; + input [0:5] cp_axu_i0_t1_t1_p; + + input [0:THREADS-1] cp_axu_i1_t1_v; + input [0:2] cp_axu_i1_t0_t1_t; + input [0:2] cp_axu_i1_t1_t1_t; + input [0:5] cp_axu_i1_t0_t1_p; + input [0:5] cp_axu_i1_t1_t1_p; + + + + output [0:3] f_scr_ex8_cr_fld; ////#iu + output [0:3] f_scr_ex8_fx_thread0; ////#iu + output [0:3] f_scr_ex8_fx_thread1; ////#iu + output [0:3] f_scr_cpl_fx_thread0; ////#iu + output [0:3] f_scr_cpl_fx_thread1; ////#iu + + // end ports + + // ENTITY + + + parameter tiup = 1'b1; + parameter tidn = 1'b0; + + wire sg_0; + wire thold_0_b; + wire thold_0; + wire force_t; + wire ex4_act; + wire ex3_act; + wire ex5_act; + wire ex6_act; + wire ex6_act_din; + wire ex6_act_q; + wire ex7_act; + wire ex7_th0_act; + wire ex7_th1_act; + wire ex7_th2_act; + wire ex7_th3_act; + wire ex7_th0_act_wocan; + wire ex7_th1_act_wocan; + wire ex7_th2_act_wocan; + wire ex7_th3_act_wocan; + + (* analysis_not_referenced="TRUE" *) + wire [0:3] act_spare_unused; + (* analysis_not_referenced="TRUE" *) + wire [0:67] spare_unused; + //----------------- + wire [0:13] act_so; //SCAN + wire [0:13] act_si; //SCAN + + wire [0:24] ex5_ctl_so; //SCAN + wire [0:24] ex5_ctl_si; //SCAN + wire [0:24] ex6_ctl_so; //SCAN + wire [0:24] ex6_ctl_si; //SCAN + wire [0:24] ex7_ctl_so; //SCAN + wire [0:24] ex7_ctl_si; //SCAN + wire [0:3] ex8_ctl_so; //SCAN + wire [0:3] ex8_ctl_si; //SCAN + + wire [0:26] ex7_flag_so; //SCAN + wire [0:26] ex7_flag_si; //SCAN + wire [0:35] ex7_mvdat_so; //SCAN + wire [0:35] ex7_mvdat_si; //SCAN + + wire [0:27] fpscr_th0_so; //SCAN + wire [0:27] fpscr_th0_si; //SCAN + wire [0:27] fpscr_th1_so; //SCAN + wire [0:27] fpscr_th1_si; //SCAN + wire [0:27] fpscr_th2_so; //SCAN + wire [0:27] fpscr_th2_si; //SCAN + wire [0:27] fpscr_th3_so; //SCAN + wire [0:27] fpscr_th3_si; //SCAN + + wire [0:3] ex8_crf_so; //SCAN + wire [0:3] ex8_crf_si; //SCAN + //----------------- + wire [0:23] ex7_mrg; + wire [0:3] ex7_mrg_dfp; + wire [0:3] ex7_fpscr_dfp_din; + wire [0:23] ex7_fpscr_din; + wire ex7_fpscr_din1_thr0; + wire ex7_fpscr_din1_thr1; + wire [0:3] ex7_cr_fld; + wire [0:3] ex7_cr_fld_x; + wire [0:31] ex7_fpscr_move; + wire [0:23] ex7_fpscr_pipe; + wire [0:3] ex7_fpscr_move_dfp; + wire [0:3] ex7_fpscr_pipe_dfp; + + wire [0:3] fpscr_dfp_th0; + wire [0:3] fpscr_dfp_th1; + wire [0:3] fpscr_dfp_th2; + wire [0:3] fpscr_dfp_th3; + + wire [0:23] fpscr_th0; + wire [0:23] fpscr_th1; + wire [0:23] fpscr_th2; + wire [0:23] fpscr_th3; + + wire [0:31] fpscr_rd_dat; + wire [0:3] fpscr_rd_dat_dfp; + wire [0:3] ex8_cr_fld; + wire [0:4] ex7_fprf_pipe; + + wire [0:3] ex5_thread; + wire [0:3] ex6_thread; + wire [0:3] ex6_thread_q; + wire [0:3] ex7_thread; + wire [0:3] ex8_thread; + + wire ex6_th0_act; + wire ex6_th1_act; + wire ex6_th2_act; + wire ex6_th3_act; + wire ex7_upd_move; + wire ex7_scr_upd_move; + wire ex7_upd_pipe; + + wire [0:4] ex7_fprf_spec; + wire ex7_compare; + wire ex7_fprf_pipe_v; + wire ex7_fprf_hold; + wire ex7_fi_spec; + wire ex7_fi_pipe_v; + wire ex7_fr_spec; + wire ex7_fr_pipe_v; + wire ex7_ox_spec; + wire ex7_ox_pipe_v; + wire ex7_ux_spec; + wire ex7_ux_pipe_v; + wire [0:31] ex7_mv_data; + wire [0:3] ex7_mv_data_dfp; + wire [0:31] ex7_mv_sel; + wire [0:3] ex7_mv_sel_dfp; + + wire ex7_flag_vxsnan; + wire ex7_flag_vxisi; + wire ex7_flag_vxidi; + wire ex7_flag_vxzdz; + wire ex7_flag_vximz; + wire ex7_flag_vxvc; + wire ex7_flag_vxsqrt; + wire ex7_flag_vxcvi; + wire ex7_flag_zx; + wire [0:31] ex7_fpscr_wr_dat; + wire [0:3] ex7_fpscr_wr_dat_dfp; + wire ex7_new_excp; + wire [0:3] ex5_bit_data; + wire [0:3] ex5_bit_mask; + wire [0:8] ex5_nib_mask; + wire ex5_mcrfs; + wire ex5_mtfsf; + wire ex5_mtfsfi; + wire ex5_mtfsbx; + wire [0:3] ex6_bit_data; + wire [0:3] ex6_bit_mask; + wire [0:8] ex6_nib_mask; + wire ex6_mcrfs; + wire ex6_mtfsf; + wire ex6_mtfsfi; + wire ex6_mtfsbx; + wire [0:3] ex7_bit_data; + wire [0:3] ex7_bit_mask; + wire [0:8] ex7_nib_mask; + wire ex7_mcrfs; + wire ex7_mtfsf; + wire ex7_mtfsfi; + wire ex7_mtfsbx; + wire unused_stuff; + wire ex6_scr_upd_move; + wire ex6_scr_upd_pipe; + wire [0:3] ex4_thread; + wire [0:3] ex4_fpscr_bit_data; + wire [0:3] ex4_fpscr_bit_mask; + wire [0:8] ex4_fpscr_nib_mask; + wire ex4_mcrfs; + wire ex4_mtfsf; + wire ex4_mtfsfi; + wire ex4_mtfsbx; + wire ex6_flag_vxsnan; + wire ex6_flag_vxisi; + wire ex6_flag_vxidi; + wire ex6_flag_vxzdz; + wire ex6_flag_vximz; + wire ex6_flag_vxvc; + wire ex6_flag_vxsqrt; + wire ex6_flag_vxcvi; + wire ex6_flag_zx; + wire [0:4] ex6_fprf_spec; + wire ex6_compare; + wire ex6_fprf_pipe_v; + wire ex6_fprf_hold; + wire ex6_fi_spec; + wire ex6_fi_pipe_v; + wire ex6_fr_spec; + wire ex6_fr_pipe_v; + wire ex6_ox_spec; + wire ex6_ox_pipe_v; + wire ex6_ux_spec; + wire ex6_ux_pipe_v; + wire ex7_upd_move_nmcrfs; + wire ex7_upd_move_thr0; + wire ex7_upd_move_thr1; + wire ex6_divsqrt_v; + wire ex7_divsqrt_v; + wire ex6_divsqrt_v_s; + wire ex6_divsqrt_v_suppress; + wire [0:1] ex6_divsqrt_v_tid; + wire [0:63] zeros; + wire re0_thr0; + + wire [0:23] do0_thr0; + wire [0:23] do0_thr1; + wire re1_thr0; + + wire [0:5] ra0_thr0; + wire [0:5] ra0_thr1; + wire [0:5] ra1_thr0; + wire [0:5] ra1_thr1; + + wire [0:23] do1_thr0; + wire [0:23] do1_thr1; + + wire we0_thr0; + wire we0_thr1; + wire [0:5] wa0; + wire [0:23] di0; + wire we1; + wire [0:5] wa1; + wire [0:23] di1; + wire re0_2_thr0; + wire re1_2_thr0; + + wire re0_thr1; + wire re1_thr1; + wire re0_2_thr1; + wire re1_2_thr1; + + wire [28:63] cfpscr_thr0_din; + wire [28:63] cfpscr_thr1_din; + wire [28:63] cfpscr_thr0_din_i0; + wire [28:63] cfpscr_thr1_din_i0; + + wire [28:63] cfpscr_thr0_l2; + wire [28:63] cfpscr_thr1_l2; + + wire [32:63] cfpscr_pipe_thr1_i0; + wire cfpscr_new_excp_thr1_i0; + + wire [32:63] cfpscr_pipe_thr0_i0; + wire cfpscr_new_excp_thr0_i0; + + wire cfpscr_i0_wr_thr0; + wire cfpscr_i1_wr_thr0; + wire cfpscr_i0i1_wr_thr0; + + wire cfpscr_i0_wr_thr1; + wire cfpscr_i1_wr_thr1; + wire cfpscr_i0i1_wr_thr1; + + wire [28:63] cfpscr_thrx_cr; + wire [28:63] ex6_cfpscr_thrx_cr; + + wire [0:35] cfpscr_thr0_si; + wire [0:35] cfpscr_thr0_so; + wire [0:35] cfpscr_thr1_si; + wire [0:35] cfpscr_thr1_so; + + wire [0:3] cadd_si; + wire [0:3] cadd_so; + wire [0:3] cadd_thr1_si; + wire [0:3] cadd_thr1_so; + wire [0:23] ex7_hfpscr_pipe; + wire [28:63] cfpscr_pipe_thr0; + wire [28:63] cfpscr_pipe_thr1; + + wire [28:63] cfpscr_move; + + wire [35:55] upd_i0_fpscr_thr0; + wire [35:55] upd_i1_fpscr_thr0; + wire [35:55] upd_i0_fpscr_thr1; + wire [35:55] upd_i1_fpscr_thr1; + + wire cfpscr_upd_i0_thr0; + wire cfpscr_upd_i1_thr0; + wire cfpscr_upd_i0_thr1; + wire cfpscr_upd_i1_thr1; + + wire ex6_divsqrt_flag_fpscr_nan; + wire ex7_divsqrt_flag_fpscr_nan; + + wire cfpscr_mtfsf; + wire cfpscr_mtfsfi; + wire cfpscr_new_excp_thr0; + wire cfpscr_new_excp_thr1; + + wire cfpscr_upd_move; + wire cfpscr_upd_pipe_thr0; + wire cfpscr_upd_pipe_thr1; + + wire upd_i0_thr0; + wire upd_i0_thr1; + + wire upd_i0_fprf_hold_thr0; + wire upd_i0_fprf_hold_thr1; + + wire upd_i0_compare_thr0; + wire upd_i0_compare_thr1; + + wire upd_i1_thr0; + wire upd_i1_thr1; + wire upd_i1_fprf_hold_thr0; + wire upd_i1_fprf_hold_thr1; + + wire upd_i1_compare_thr0; + wire upd_i1_compare_thr1; + wire ex7_inv_fpscr_bit; + + wire upd_i0_fprf_hold_47_thr0; + wire upd_i1_fprf_hold_47_thr0; + wire upd_i0_fprf_hold_47_thr1; + wire upd_i1_fprf_hold_47_thr1; + + wire [0:31] fwrite_thr0; + wire [0:31] fwrite_thr1; + wire [0:31] fwrite_thr0_b; + wire [0:31] fwrite_thr1_b; + wire [0:31] fread0_thr0; + wire [0:31] fread0_thr1; + wire [0:31] fread1_thr0; + wire [0:31] fread1_thr1; + + wire [0:767] hfpscr_thr0_q; + wire [0:767] hfpscr_thr0_din; + wire [0:575] hfpscr_thr1_q; + wire [0:575] hfpscr_thr1_din; + + wire [0:31] fread0_thr0_q; + wire [0:31] fread1_thr0_q; + wire [0:31] fread0_thr1_q; + wire [0:31] fread1_thr1_q; + + wire [0:831] hfpscr_thr0_so; + wire [0:831] hfpscr_thr0_si; + wire [0:639] hfpscr_thr1_so; + wire [0:639] hfpscr_thr1_si; + + genvar i; + + ////############################################ + ////# pervasive + ////############################################ + + + tri_plat thold_reg_0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(flush), + .din(thold_1), + .q(thold_0) + ); + + + tri_plat sg_reg_0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(flush), + .din(sg_1), + .q(sg_0) + ); + + + tri_lcbor lcbor_0( + .clkoff_b(clkoff_b), + .thold(thold_0), + .sg(sg_0), + .act_dis(act_dis), + .force_t(force_t), + .thold_b(thold_0_b) + ); + + ////############################################ + ////# ACT LATCHES + ////############################################ + + assign ex3_act = (~ex3_act_b); + assign ex6_scr_upd_move = (~f_pic_ex6_scr_upd_move_b); + assign ex6_divsqrt_v = |(f_dsq_ex6_divsqrt_v); + assign ex6_divsqrt_v_tid = f_dsq_ex6_divsqrt_v; + assign ex6_divsqrt_v_s = ex6_divsqrt_v & (~f_dsq_ex6_divsqrt_v_suppress); + assign ex6_divsqrt_v_suppress = f_dsq_ex6_divsqrt_v_suppress; + + assign ex6_scr_upd_pipe = ((~f_pic_ex6_scr_upd_pipe_b)) | ex6_divsqrt_v; + + assign ex6_act_din = ex6_act | ex6_divsqrt_v; + + + tri_rlmreg_p #(.WIDTH(14)) act_lat( + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[6]), + .mpw1_b(mpw1_b[6]), + .mpw2_b(mpw2_b[1]), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(thold_0_b), + .sg(sg_0), + .scout(act_so), + .scin(act_si), + //----------------- + .din({ act_spare_unused[0], + act_spare_unused[1], + ex3_act, + ex4_act, + ex5_act, + ex6_act_din, + ex6_th0_act, + ex6_th1_act, + ex6_th2_act, + ex6_th3_act, + ex6_scr_upd_move, + ex6_scr_upd_pipe, + act_spare_unused[2], + act_spare_unused[3]}), + //----------------- + .dout({ act_spare_unused[0], + act_spare_unused[1], + ex4_act, + ex5_act, + ex6_act_q, + ex7_act, + ex7_th0_act_wocan, + ex7_th1_act_wocan, + ex7_th2_act_wocan, + ex7_th3_act_wocan, + ex7_scr_upd_move, + ex7_upd_pipe, + act_spare_unused[2], + act_spare_unused[3]}) + ); + + assign ex6_act = ex6_act_q | ex6_divsqrt_v; + + assign ex7_upd_move = ex7_scr_upd_move & (~f_dcd_ex7_cancel) & (~ex7_divsqrt_v); + assign ex7_upd_move_thr0 = ex7_upd_move & ex7_thread[0]; + assign ex7_upd_move_thr1 = ex7_upd_move & ex7_thread[1]; + + assign ex6_th0_act = (ex6_thread[0] & ex6_act & (ex6_scr_upd_move | ex6_scr_upd_pipe)); + assign ex6_th1_act = (ex6_thread[1] & ex6_act & (ex6_scr_upd_move | ex6_scr_upd_pipe)); + assign ex6_th2_act = (ex6_thread[2] & ex6_act & (ex6_scr_upd_move | ex6_scr_upd_pipe)); + assign ex6_th3_act = (ex6_thread[3] & ex6_act & (ex6_scr_upd_move | ex6_scr_upd_pipe)); + + assign ex7_th0_act = ex7_th0_act_wocan & (~f_dcd_ex7_cancel); + assign ex7_th1_act = ex7_th1_act_wocan & (~f_dcd_ex7_cancel); + assign ex7_th2_act = ex7_th2_act_wocan & (~f_dcd_ex7_cancel); + assign ex7_th3_act = ex7_th3_act_wocan & (~f_dcd_ex7_cancel); + + ////############################################## + ////# EX5 latches + ////############################################## + + assign ex4_thread[0:3] = (~f_cr2_ex4_thread_b[0:3]); + assign ex4_fpscr_bit_data[0:3] = (~f_cr2_ex4_fpscr_bit_data_b[0:3]); + assign ex4_fpscr_bit_mask[0:3] = (~f_cr2_ex4_fpscr_bit_mask_b[0:3]); + assign ex4_fpscr_nib_mask[0:8] = (~f_cr2_ex4_fpscr_nib_mask_b[0:8]); + assign ex4_mcrfs = (~f_cr2_ex4_mcrfs_b); + assign ex4_mtfsf = (~f_cr2_ex4_mtfsf_b); + assign ex4_mtfsfi = (~f_cr2_ex4_mtfsfi_b); + assign ex4_mtfsbx = (~f_cr2_ex4_mtfsbx_b); + + + tri_rlmreg_p #(.WIDTH(25)) ex5_ctl_lat( + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[4]), + .mpw1_b(mpw1_b[4]), + .mpw2_b(mpw2_b[0]), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(thold_0_b), + .sg(sg_0), + .scout(ex5_ctl_so), + .scin(ex5_ctl_si), + //----------------- + .din({ ex4_thread[0:3], + ex4_fpscr_bit_data[0:3], + ex4_fpscr_bit_mask[0:3], + ex4_fpscr_nib_mask[0:8], + ex4_mcrfs, + ex4_mtfsf, + ex4_mtfsfi, + ex4_mtfsbx}), + //----------------- + .dout({ ex5_thread[0:3], + ex5_bit_data[0:3], + ex5_bit_mask[0:3], + ex5_nib_mask[0:8], + ex5_mcrfs, + ex5_mtfsf, + ex5_mtfsfi, + ex5_mtfsbx}) + ); + + ////############################################## + ////# EX6 latches + ////############################################## + + + tri_rlmreg_p #(.WIDTH(25)) ex6_ctl_lat( + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[5]), + .mpw1_b(mpw1_b[5]), + .mpw2_b(mpw2_b[1]), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(thold_0_b), + .sg(sg_0), + .scout(ex6_ctl_so), + .scin(ex6_ctl_si), + //----------------- + .din({ ex5_thread[0:3], + ex5_bit_data[0:3], + ex5_bit_mask[0:3], + ex5_nib_mask[0:8], + ex5_mcrfs, + ex5_mtfsf, + ex5_mtfsfi, + ex5_mtfsbx}), + //----------------- + .dout({ ex6_thread_q[0:3], + ex6_bit_data[0:3], + ex6_bit_mask[0:3], + ex6_nib_mask[0:8], + ex6_mcrfs, + ex6_mtfsf, + ex6_mtfsfi, + ex6_mtfsbx}) + ); + + assign ex6_thread[0] = (ex6_thread_q[0] & (~ex6_divsqrt_v)) | ex6_divsqrt_v_tid[0]; + assign ex6_thread[1] = (ex6_thread_q[1] & (~ex6_divsqrt_v)) | ex6_divsqrt_v_tid[1]; + assign ex6_thread[2] = ex6_thread_q[2] & (~ex6_divsqrt_v); + assign ex6_thread[3] = ex6_thread_q[3] & (~ex6_divsqrt_v); + + ////############################################## + ////# EX7 latches + ////############################################## + + + tri_rlmreg_p #(.WIDTH(25)) ex7_ctl_lat( + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[6]), + .mpw1_b(mpw1_b[6]), + .mpw2_b(mpw2_b[1]), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(thold_0_b), + .sg(sg_0), + .scout(ex7_ctl_so), + .scin(ex7_ctl_si), + //----------------- + .din({ ex6_thread[0:3], + ex6_bit_data[0:3], + ex6_bit_mask[0:3], + ex6_nib_mask[0:8], + ex6_mcrfs, + ex6_mtfsf, + ex6_mtfsfi, + ex6_mtfsbx}), + //----------------- + .dout({ ex7_thread[0:3], + ex7_bit_data[0:3], + ex7_bit_mask[0:3], + ex7_nib_mask[0:8], + ex7_mcrfs, + ex7_mtfsf, + ex7_mtfsfi, + ex7_mtfsbx}) + ); + + + tri_rlmreg_p #(.WIDTH(4)) ex8_ctl_lat( + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[7]), + .mpw1_b(mpw1_b[7]), + .mpw2_b(mpw2_b[1]), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(thold_0_b), + .sg(sg_0), + .scout(ex8_ctl_so), + .scin(ex8_ctl_si), + //----------------- + .din(ex7_thread[0:3]), + //----------------- + .dout(ex8_thread[0:3]) + ); + + assign ex6_flag_vxsnan = (((~f_pic_ex6_flag_vxsnan_b)) & (~ex6_divsqrt_v)) | ((f_dsq_ex6_divsqrt_flag_fpscr_snan) & ex6_divsqrt_v); + + assign ex6_flag_vxisi = ((~f_pic_ex6_flag_vxisi_b)) & (~ex6_divsqrt_v); + + assign ex6_flag_vxidi = (((~f_pic_ex6_flag_vxidi_b)) & (~ex6_divsqrt_v)) | ((f_dsq_ex6_divsqrt_flag_fpscr_idi) & ex6_divsqrt_v); + + assign ex6_flag_vxzdz = (((~f_pic_ex6_flag_vxzdz_b)) & (~ex6_divsqrt_v)) | ((f_dsq_ex6_divsqrt_flag_fpscr_zdz) & ex6_divsqrt_v); + + assign ex6_flag_vximz = ((~f_pic_ex6_flag_vximz_b)) & (~ex6_divsqrt_v); + assign ex6_flag_vxvc = ((~f_pic_ex6_flag_vxvc_b)) & (~ex6_divsqrt_v); + + assign ex6_flag_vxsqrt = (((~f_pic_ex6_flag_vxsqrt_b)) & (~ex6_divsqrt_v)) | ((f_dsq_ex6_divsqrt_flag_fpscr_sqrt) & ex6_divsqrt_v); + + assign ex6_flag_vxcvi = ((~f_pic_ex6_flag_vxcvi_b)) & (~ex6_divsqrt_v); + + assign ex6_flag_zx = (((~f_pic_ex6_flag_zx_b)) & (~ex6_divsqrt_v)) | ((f_dsq_ex6_divsqrt_flag_fpscr_zx) & ex6_divsqrt_v); + + assign ex6_fprf_spec[0] = (((~f_pic_ex6_fprf_spec_b[0])) & (~ex6_divsqrt_v)); + assign ex6_fprf_spec[1] = (((~f_pic_ex6_fprf_spec_b[1])) & (~ex6_divsqrt_v)); + assign ex6_fprf_spec[2] = (((~f_pic_ex6_fprf_spec_b[2])) & (~ex6_divsqrt_v)); + assign ex6_fprf_spec[3] = (((~f_pic_ex6_fprf_spec_b[3])) & (~ex6_divsqrt_v)); + assign ex6_fprf_spec[4] = (((~f_pic_ex6_fprf_spec_b[4])) & (~ex6_divsqrt_v)); + + assign ex6_compare = ((~f_pic_ex6_compare_b)) & (~ex6_divsqrt_v); + assign ex6_fprf_pipe_v = (((~f_pic_ex6_fprf_pipe_v_b)) | ex6_divsqrt_v) & (~(f_dsq_ex6_divsqrt_v_suppress & ex6_divsqrt_v)); + + assign ex6_fprf_hold = (((~f_pic_ex6_fprf_hold_b)) | (ex6_divsqrt_v & ex6_divsqrt_v_suppress)) & (~ex6_divsqrt_v_s); + assign ex6_fi_spec = ((~f_pic_ex6_fi_spec_b)) & (~ex6_divsqrt_v); + assign ex6_fi_pipe_v = ((~f_pic_ex6_fi_pipe_v_b)) | ex6_divsqrt_v; + assign ex6_fr_spec = ((~f_pic_ex6_fr_spec_b)) & (~ex6_divsqrt_v); + assign ex6_fr_pipe_v = ((~f_pic_ex6_fr_pipe_v_b)) | ex6_divsqrt_v; + assign ex6_ox_spec = ((~f_pic_ex6_ox_spec_b)) & (~ex6_divsqrt_v); + assign ex6_ox_pipe_v = ((~f_pic_ex6_ox_pipe_v_b)) | ex6_divsqrt_v; + assign ex6_ux_spec = ((~f_pic_ex6_ux_spec_b)) & (~ex6_divsqrt_v); + assign ex6_ux_pipe_v = ((~f_pic_ex6_ux_pipe_v_b)) | ex6_divsqrt_v; + + assign ex6_divsqrt_flag_fpscr_nan = f_dsq_ex6_divsqrt_flag_fpscr_nan & ex6_divsqrt_v; + + + tri_rlmreg_p #(.WIDTH(27)) ex7_flag_lat( + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[6]), + .mpw1_b(mpw1_b[6]), + .mpw2_b(mpw2_b[1]), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), // ex6_act, -- todo: act pin + .thold_b(thold_0_b), + .sg(sg_0), + .scout(ex7_flag_so), + .scin(ex7_flag_si), + //----------------- + .din({ ex6_flag_vxsnan, ////# sig_nan + ex6_flag_vxisi, ////# inf_sub_inf + ex6_flag_vxidi, ////# inf_div_inf + ex6_flag_vxzdz, ////# zer_div_zer + ex6_flag_vximz, ////# inf_mul_zer + ex6_flag_vxvc, ////# inval_cmp + ex6_flag_vxsqrt, ////# inval_sqrt + ex6_flag_vxcvi, ////# inval_convert + ex6_flag_zx, ////# div_zer + ex6_fprf_spec[0:4], //FPRF/'0'FPCC for special cases + ex6_compare, + ex6_fprf_pipe_v, //fprf update exluding compare + ex6_fprf_hold, //fprf update including compare + ex6_fi_spec, + ex6_fi_pipe_v, + ex6_fr_spec, + ex6_fr_pipe_v, + ex6_ox_spec, + ex6_ox_pipe_v, + ex6_ux_spec, + ex6_ux_pipe_v, + ex6_divsqrt_flag_fpscr_nan, + ex6_divsqrt_v}), + //----------------- + .dout({ ex7_flag_vxsnan, //LAT-- + ex7_flag_vxisi, //LAT-- + ex7_flag_vxidi, //LAT-- + ex7_flag_vxzdz, //LAT-- + ex7_flag_vximz, //LAT-- + ex7_flag_vxvc, //LAT-- + ex7_flag_vxsqrt, //LAT-- + ex7_flag_vxcvi, //LAT-- + ex7_flag_zx, //LAT-- + ex7_fprf_spec[0:4], //LAT-- + ex7_compare, //LAT-- + ex7_fprf_pipe_v, //LAT-- + ex7_fprf_hold, //LAT-- + ex7_fi_spec, //LAT-- + ex7_fi_pipe_v, //LAT-- + ex7_fr_spec, //LAT-- + ex7_fr_pipe_v, //LAT-- + ex7_ox_spec, //LAT-- + ex7_ox_pipe_v, //LAT-- + ex7_ux_spec, //LAT-- + ex7_ux_pipe_v, //LAT-- + ex7_divsqrt_flag_fpscr_nan, //LAT-- + ex7_divsqrt_v}) + ); + + + tri_rlmreg_p #(.WIDTH(36)) ex7_mvdat_lat( + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[6]), + .mpw1_b(mpw1_b[6]), + .mpw2_b(mpw2_b[1]), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex6_act), + .thold_b(thold_0_b), + .sg(sg_0), + .scout(ex7_mvdat_so), + .scin(ex7_mvdat_si), + //----------------- + .din({ f_nrm_ex6_fpscr_wr_dat_dfp[0:3], + f_nrm_ex6_fpscr_wr_dat[0:31]}), + .dout({ ex7_fpscr_wr_dat_dfp[0:3], //LAT-- + ex7_fpscr_wr_dat[0:31]}) //LAT-- + ); + + ////############################################## + ////# EX7 logic + ////############################################## + + ////#----------------------------------------- + ////# select field for mcrfs + ////#----------------------------------------- + + assign cfpscr_thrx_cr[28:63] = (cfpscr_thr0_l2[28:63] & {36{ex7_thread[0]}}) | + (cfpscr_thr1_l2[28:63] & {36{ex7_thread[1]}}); + + assign ex6_cfpscr_thrx_cr[28:63] = (cfpscr_thr0_l2[28:63] & {36{ex6_thread[0]}}) | + (cfpscr_thr1_l2[28:63] & {36{ex6_thread[1]}}); + + assign ex7_cr_fld_x[0:3] = (ex7_mrg[0:3] & {4{ex7_nib_mask[0]}}) | + (ex7_mrg[4:7] & {4{ex7_nib_mask[1]}}) | + (ex7_mrg[8:11] & {4{ex7_nib_mask[2]}}) | + (ex7_mrg[12:15] & {4{ex7_nib_mask[3]}}) | + (ex7_mrg[16:19] & {4{ex7_nib_mask[4]}}) | + (({tidn, ex7_mrg[21:23]}) & {4{ex7_nib_mask[5]}}) | + (cfpscr_thrx_cr[56:59] & {4{ex7_nib_mask[6]}}) | + (cfpscr_thrx_cr[60:63] & {4{ex7_nib_mask[7]}}); //[20] is a reserved bit + + assign ex7_upd_move_nmcrfs = ex7_upd_move & (~ex7_mcrfs); + + // fmr + // the old value + //( cfpscr_thr0_l2(32 to 35) and (0 to 3 => ex7_upd_pipe ) ) or -- what the math update will be + //( cfpscr_thr0_l2(32 to 35) and (0 to 3 => ex7_upd_move_nmcrfs ) ) ; -- what the math update will be + assign ex7_cr_fld[0:3] = (ex7_mrg[0:3] & {4{(~ex7_upd_move) & (~ex7_upd_pipe)}}) | + (ex7_cr_fld_x[0:3] & {4{ex7_mcrfs}}) | + (ex7_fpscr_din[0:3] & {4{ex7_upd_pipe}}) | + (ex7_fpscr_din[0:3] & {4{ex7_upd_move_nmcrfs}}); // what the math update will be + + + // what the math update will be + + ////#----------------------------------------------------------------------- + ////# move to logic mtfsf mtfsfi mcrf mtfsb0 mtfsb1 + ////#----------------------------------------------------------------------- + // if mcrfs : if nib_mask selects -> reset if (0,3:12,21:23) (bit mask=1111) + // if mtfsfi : if nib_mask selects -> load with bit data (bit mask=1111) + // if mtfsf : if nib_mask selects -> load with wr_data (bit mask=1111) + // if mtfsb0 : if nib_mask selects -> load with bit data (if bit mask) + // if mtfsb1 : if nib_mask selects -> load with bit_data (if bit mask) + + assign ex7_mv_data_dfp[0:3] = (ex7_bit_data[0:3] & {4{(~ex7_mtfsf)}}) | + (ex7_fpscr_wr_dat_dfp[0:3] & {4{ex7_mtfsf}}); + + assign ex7_mv_data[0:3] = (ex7_bit_data[0:3] & {4{(~ex7_mtfsf)}}) | (ex7_fpscr_wr_dat[0:3] & {4{ex7_mtfsf}}); + assign ex7_mv_data[4:7] = (ex7_bit_data[0:3] & {4{(~ex7_mtfsf)}}) | (ex7_fpscr_wr_dat[4:7] & {4{ex7_mtfsf}}); + assign ex7_mv_data[8:11] = (ex7_bit_data[0:3] & {4{(~ex7_mtfsf)}}) | (ex7_fpscr_wr_dat[8:11] & {4{ex7_mtfsf}}); + assign ex7_mv_data[12:15] = (ex7_bit_data[0:3] & {4{(~ex7_mtfsf)}}) | (ex7_fpscr_wr_dat[12:15] & {4{ex7_mtfsf}}); + assign ex7_mv_data[16:19] = (ex7_bit_data[0:3] & {4{(~ex7_mtfsf)}}) | (ex7_fpscr_wr_dat[16:19] & {4{ex7_mtfsf}}); + assign ex7_mv_data[20:23] = (ex7_bit_data[0:3] & {4{(~ex7_mtfsf)}}) | (ex7_fpscr_wr_dat[20:23] & {4{ex7_mtfsf}}); + assign ex7_mv_data[24:27] = (ex7_bit_data[0:3] & {4{(~ex7_mtfsf)}}) | (ex7_fpscr_wr_dat[24:27] & {4{ex7_mtfsf}}); + assign ex7_mv_data[28:31] = (ex7_bit_data[0:3] & {4{(~ex7_mtfsf)}}) | (ex7_fpscr_wr_dat[28:31] & {4{ex7_mtfsf}}); + + assign ex7_mv_sel_dfp[0] = ex7_bit_mask[0] & ex7_nib_mask[8]; + assign ex7_mv_sel_dfp[1] = ex7_bit_mask[1] & ex7_nib_mask[8]; + assign ex7_mv_sel_dfp[2] = ex7_bit_mask[2] & ex7_nib_mask[8]; + assign ex7_mv_sel_dfp[3] = ex7_bit_mask[3] & ex7_nib_mask[8]; + + assign ex7_mv_sel[0] = ex7_bit_mask[0] & ex7_nib_mask[0]; // fx + assign ex7_mv_sel[1] = tidn; //UNUSED -- fex + assign ex7_mv_sel[2] = tidn; //UNUSED -- vx + assign ex7_mv_sel[3] = ex7_bit_mask[3] & ex7_nib_mask[0]; // ox + assign ex7_mv_sel[4] = ex7_bit_mask[0] & ex7_nib_mask[1]; // ux + assign ex7_mv_sel[5] = ex7_bit_mask[1] & ex7_nib_mask[1]; // zx + assign ex7_mv_sel[6] = ex7_bit_mask[2] & ex7_nib_mask[1]; // xx + assign ex7_mv_sel[7] = ex7_bit_mask[3] & ex7_nib_mask[1]; // vxsnan + assign ex7_mv_sel[8] = ex7_bit_mask[0] & ex7_nib_mask[2]; // vxisi + assign ex7_mv_sel[9] = ex7_bit_mask[1] & ex7_nib_mask[2]; // vxidi + assign ex7_mv_sel[10] = ex7_bit_mask[2] & ex7_nib_mask[2]; // vxzdz + assign ex7_mv_sel[11] = ex7_bit_mask[3] & ex7_nib_mask[2]; // vximz + assign ex7_mv_sel[12] = ex7_bit_mask[0] & ex7_nib_mask[3]; // vxvc + assign ex7_mv_sel[13] = ex7_bit_mask[1] & ex7_nib_mask[3] & (~ex7_mcrfs); // fr + assign ex7_mv_sel[14] = ex7_bit_mask[2] & ex7_nib_mask[3] & (~ex7_mcrfs); // fi + assign ex7_mv_sel[15] = ex7_bit_mask[3] & ex7_nib_mask[3] & (~ex7_mcrfs); // FPRF C + assign ex7_mv_sel[16] = ex7_bit_mask[0] & ex7_nib_mask[4] & (~ex7_mcrfs); // FPRF fpcc(lt) + assign ex7_mv_sel[17] = ex7_bit_mask[1] & ex7_nib_mask[4] & (~ex7_mcrfs); // FPRF fpcc(gt) + assign ex7_mv_sel[18] = ex7_bit_mask[2] & ex7_nib_mask[4] & (~ex7_mcrfs); // FPRF fpcc(eq) + assign ex7_mv_sel[19] = ex7_bit_mask[3] & ex7_nib_mask[4] & (~ex7_mcrfs); // FPRF fpcc(nan) + assign ex7_mv_sel[20] = ex7_bit_mask[0] & ex7_nib_mask[5] & (~ex7_mcrfs); // RESERVED + assign ex7_mv_sel[21] = ex7_bit_mask[1] & ex7_nib_mask[5]; // vx-soft + assign ex7_mv_sel[22] = ex7_bit_mask[2] & ex7_nib_mask[5]; // vx-sqrt + assign ex7_mv_sel[23] = ex7_bit_mask[3] & ex7_nib_mask[5]; // vx-vci + assign ex7_mv_sel[24] = ex7_bit_mask[0] & ex7_nib_mask[6] & (~ex7_mcrfs); // ve + assign ex7_mv_sel[25] = ex7_bit_mask[1] & ex7_nib_mask[6] & (~ex7_mcrfs); // oe + assign ex7_mv_sel[26] = ex7_bit_mask[2] & ex7_nib_mask[6] & (~ex7_mcrfs); // ue + assign ex7_mv_sel[27] = ex7_bit_mask[3] & ex7_nib_mask[6] & (~ex7_mcrfs); // ze + assign ex7_mv_sel[28] = ex7_bit_mask[0] & ex7_nib_mask[7] & (~ex7_mcrfs); // xe + assign ex7_mv_sel[29] = ex7_bit_mask[1] & ex7_nib_mask[7] & (~ex7_mcrfs); // non-ieee + assign ex7_mv_sel[30] = ex7_bit_mask[2] & ex7_nib_mask[7] & (~ex7_mcrfs); // rnd-mode + assign ex7_mv_sel[31] = ex7_bit_mask[3] & ex7_nib_mask[7] & (~ex7_mcrfs); // rnd-mode + + assign ex7_fpscr_move[0] = (ex7_mrg[0] & (~ex7_mv_sel[0])) | (ex7_mv_data[0] & ex7_mv_sel[0]); + assign ex7_fpscr_move[1] = tidn; ////unused (from other bits after move/pipe selection) + assign ex7_fpscr_move[2] = tidn; ////unused (from other bits after move/pipe selection) + assign ex7_fpscr_move[3:23] = (ex7_mrg[3:23] & (~ex7_mv_sel[3:23])) | (ex7_mv_data[3:23] & ex7_mv_sel[3:23]); + assign ex7_fpscr_move[24:31] = (cfpscr_thrx_cr[56:63] & (~ex7_mv_sel[24:31])) | (ex7_mv_data[24:31] & ex7_mv_sel[24:31]); + + assign ex7_fpscr_move_dfp[0:3] = (ex7_mrg_dfp[0:3] & (~ex7_mv_sel_dfp[0:3])) | (ex7_mv_data_dfp[0:3] & ex7_mv_sel_dfp[0:3]); + + ////#------------------------------------------------------------------------ + ////# decode fprf field for pipe settings + ////#------------------------------------------------------------------------ + // FPRF + // 10001 QNAN [0] qnan | den | (sign*zero) + // 01001 -INF [1] sign * !zero + // 01000 -norm [2] !sign * !zero * !qnan + // 11000 -den [3] zero + // 10010 -zero [4] inf | qnan + // 00010 +zero + // 10100 +den + // 00100 +norm + // 00101 +inf + + assign ex7_fprf_pipe[0] = (f_rnd_ex7_flag_sgn & f_rnd_ex7_flag_zer) | (f_rnd_ex7_flag_den & (~f_rnd_ex7_flag_zer)) | ex7_divsqrt_flag_fpscr_nan; + + assign ex7_fprf_pipe[1] = (f_rnd_ex7_flag_sgn & (~f_rnd_ex7_flag_zer)) & (~ex7_divsqrt_flag_fpscr_nan); + assign ex7_fprf_pipe[2] = ((~f_rnd_ex7_flag_sgn) & (~f_rnd_ex7_flag_zer)) & (~ex7_divsqrt_flag_fpscr_nan); + assign ex7_fprf_pipe[3] = f_rnd_ex7_flag_zer & (~ex7_divsqrt_flag_fpscr_nan); + assign ex7_fprf_pipe[4] = f_rnd_ex7_flag_inf | ex7_divsqrt_flag_fpscr_nan; + + ////#------------------------------------------------------------------------ + ////# functional updates (excp enable cases, special setting vs pipe setting) + ////#------------------------------------------------------------------------ + + assign ex7_fpscr_pipe[0] = ex7_mrg[0]; // check 0->1 excp after selection for move/pipe + assign ex7_fpscr_pipe[1] = tidn; //// unused (from other bits after move/pipe selection) + assign ex7_fpscr_pipe[2] = tidn; //// unused (from other bits after move/pipe selection) + assign ex7_fpscr_pipe[3] = ex7_mrg[3] | ex7_ox_spec | (ex7_ox_pipe_v & f_rnd_ex7_flag_ox); //ox STICKY + assign ex7_fpscr_pipe[4] = ex7_mrg[4] | ex7_ux_spec | (ex7_ux_pipe_v & f_rnd_ex7_flag_ux); //ux STICKY + assign ex7_fpscr_pipe[5] = ex7_mrg[5] | ex7_flag_zx; //sticky + + assign ex7_fpscr_pipe[6] = (ex7_mrg[6]) | (ex7_fi_spec) | (ex7_fi_pipe_v & f_rnd_ex7_flag_fi); // ex7_fpscr_pipe(14); --sticky version of fi + + assign ex7_fpscr_pipe[7] = ex7_mrg[7] | ex7_flag_vxsnan; //sticky + assign ex7_fpscr_pipe[8] = ex7_mrg[8] | ex7_flag_vxisi; //sticky + assign ex7_fpscr_pipe[9] = ex7_mrg[9] | ex7_flag_vxidi; //sticky + assign ex7_fpscr_pipe[10] = ex7_mrg[10] | ex7_flag_vxzdz; //sticky + assign ex7_fpscr_pipe[11] = ex7_mrg[11] | ex7_flag_vximz; //sticky + assign ex7_fpscr_pipe[12] = ex7_mrg[12] | ex7_flag_vxvc; //sticky + + assign ex7_fpscr_pipe[13] = (ex7_mrg[13] & ex7_compare) | (ex7_fr_spec) | (ex7_fr_pipe_v & f_rnd_ex7_flag_up); //fr NOT sticky + assign ex7_fpscr_pipe[14] = (ex7_mrg[14] & ex7_compare) | (ex7_fi_spec) | (ex7_fi_pipe_v & f_rnd_ex7_flag_fi); //fi NOT sticky + + assign ex7_fpscr_pipe[15] = (ex7_mrg[15] & (ex7_fprf_hold)) | (ex7_mrg[15] & (ex7_compare & (~ex7_divsqrt_v))) | (ex7_fprf_spec[0]) | (ex7_fprf_pipe_v & ex7_fprf_pipe[0]); //FPRF C NOT sticky + + assign ex7_fpscr_pipe[16] = (ex7_mrg[16] & (ex7_fprf_hold)) | (ex7_fprf_spec[1]) | (ex7_fprf_pipe_v & ex7_fprf_pipe[1]); //FPRF fpdd(lt) + assign ex7_fpscr_pipe[17] = (ex7_mrg[17] & (ex7_fprf_hold)) | (ex7_fprf_spec[2]) | (ex7_fprf_pipe_v & ex7_fprf_pipe[2]); //FPRF fpcc(gt) + assign ex7_fpscr_pipe[18] = (ex7_mrg[18] & (ex7_fprf_hold)) | (ex7_fprf_spec[3]) | (ex7_fprf_pipe_v & ex7_fprf_pipe[3]); //FPRF fpcc(eq) + assign ex7_fpscr_pipe[19] = (ex7_mrg[19] & (ex7_fprf_hold)) | (ex7_fprf_spec[4]) | (ex7_fprf_pipe_v & ex7_fprf_pipe[4]); //FPRF fpcc(nan) + + assign ex7_fpscr_pipe[20] = tidn; // reseved bit + assign ex7_fpscr_pipe[21] = ex7_mrg[21]; // VXSOFT + assign ex7_fpscr_pipe[22] = ex7_mrg[22] | ex7_flag_vxsqrt; //sticky + assign ex7_fpscr_pipe[23] = ex7_mrg[23] | ex7_flag_vxcvi; //sticky + + assign ex7_fpscr_pipe_dfp[0:3] = ex7_mrg_dfp[0:3]; + + ////#------------------------------------------------------------------------ + ////# creating the funny or bits afer the selection + ////#------------------------------------------------------------------------ + + assign ex7_fpscr_dfp_din[0] = (ex7_fpscr_move_dfp[0] & ex7_upd_move) | (ex7_fpscr_pipe_dfp[0] & ex7_upd_pipe); + assign ex7_fpscr_dfp_din[1] = (ex7_fpscr_move_dfp[1] & ex7_upd_move) | (ex7_fpscr_pipe_dfp[1] & ex7_upd_pipe); + assign ex7_fpscr_dfp_din[2] = (ex7_fpscr_move_dfp[2] & ex7_upd_move) | (ex7_fpscr_pipe_dfp[2] & ex7_upd_pipe); + assign ex7_fpscr_dfp_din[3] = (ex7_fpscr_move_dfp[3] & ex7_upd_move) | (ex7_fpscr_pipe_dfp[3] & ex7_upd_pipe); + + assign ex7_fpscr_din[23] = (ex7_fpscr_move[23] & ex7_upd_move) | (ex7_fpscr_pipe[23] & ex7_upd_pipe); + assign ex7_fpscr_din[22] = (ex7_fpscr_move[22] & ex7_upd_move) | (ex7_fpscr_pipe[22] & ex7_upd_pipe); + assign ex7_fpscr_din[21] = (ex7_fpscr_move[21] & ex7_upd_move) | (ex7_fpscr_pipe[21] & ex7_upd_pipe); + assign ex7_fpscr_din[20] = tidn; // reserved + assign ex7_fpscr_din[19] = (ex7_fpscr_move[19] & ex7_upd_move) | (ex7_fpscr_pipe[19] & ex7_upd_pipe); + assign ex7_fpscr_din[18] = (ex7_fpscr_move[18] & ex7_upd_move) | (ex7_fpscr_pipe[18] & ex7_upd_pipe); + assign ex7_fpscr_din[17] = (ex7_fpscr_move[17] & ex7_upd_move) | (ex7_fpscr_pipe[17] & ex7_upd_pipe); + assign ex7_fpscr_din[16] = (ex7_fpscr_move[16] & ex7_upd_move) | (ex7_fpscr_pipe[16] & ex7_upd_pipe); + assign ex7_fpscr_din[15] = (ex7_fpscr_move[15] & ex7_upd_move) | (ex7_fpscr_pipe[15] & ex7_upd_pipe); + assign ex7_fpscr_din[14] = (ex7_fpscr_move[14] & ex7_upd_move) | (ex7_fpscr_pipe[14] & ex7_upd_pipe); + assign ex7_fpscr_din[13] = (ex7_fpscr_move[13] & ex7_upd_move) | (ex7_fpscr_pipe[13] & ex7_upd_pipe); + assign ex7_fpscr_din[12] = (ex7_fpscr_move[12] & ex7_upd_move) | (ex7_fpscr_pipe[12] & ex7_upd_pipe); + assign ex7_fpscr_din[11] = (ex7_fpscr_move[11] & ex7_upd_move) | (ex7_fpscr_pipe[11] & ex7_upd_pipe); + assign ex7_fpscr_din[10] = (ex7_fpscr_move[10] & ex7_upd_move) | (ex7_fpscr_pipe[10] & ex7_upd_pipe); + assign ex7_fpscr_din[9] = (ex7_fpscr_move[9] & ex7_upd_move) | (ex7_fpscr_pipe[9] & ex7_upd_pipe); + assign ex7_fpscr_din[8] = (ex7_fpscr_move[8] & ex7_upd_move) | (ex7_fpscr_pipe[8] & ex7_upd_pipe); + assign ex7_fpscr_din[7] = (ex7_fpscr_move[7] & ex7_upd_move) | (ex7_fpscr_pipe[7] & ex7_upd_pipe); + assign ex7_fpscr_din[6] = (ex7_fpscr_move[6] & ex7_upd_move) | (ex7_fpscr_pipe[6] & ex7_upd_pipe); + assign ex7_fpscr_din[5] = (ex7_fpscr_move[5] & ex7_upd_move) | (ex7_fpscr_pipe[5] & ex7_upd_pipe); + assign ex7_fpscr_din[4] = (ex7_fpscr_move[4] & ex7_upd_move) | (ex7_fpscr_pipe[4] & ex7_upd_pipe); + assign ex7_fpscr_din[3] = (ex7_fpscr_move[3] & ex7_upd_move) | (ex7_fpscr_pipe[3] & ex7_upd_pipe); + + // or all invalid operation exceptions + // vxsnan + // vxisi + // vxidi + // vxzdz + // vximx + // vxvc + // vxzdz + assign ex7_fpscr_din[2] = ex7_fpscr_din[7] | ex7_fpscr_din[8] | ex7_fpscr_din[9] | ex7_fpscr_din[10] | ex7_fpscr_din[11] | ex7_fpscr_din[12] | ex7_fpscr_din[21] | ex7_fpscr_din[22] | ex7_fpscr_din[23]; // vximx + // vxvc + + // masked or of all exception bits + // vx* / ve + // ox / oe + // ux / ue + assign ex7_fpscr_din1_thr0 = (ex7_fpscr_din[2] & cfpscr_thr0_din[56]) | (ex7_fpscr_din[3] & cfpscr_thr0_din[57]) | (ex7_fpscr_din[4] & cfpscr_thr0_din[58]) | (ex7_fpscr_din[5] & cfpscr_thr0_din[59]) | (ex7_fpscr_din[6] & cfpscr_thr0_din[60]); // zx / ze + // xx / xe + // masked or of all exception bits + // vx* / ve + // ox / oe + // ux / ue + assign ex7_fpscr_din1_thr1 = (ex7_fpscr_din[2] & cfpscr_thr1_din[56]) | (ex7_fpscr_din[3] & cfpscr_thr1_din[57]) | (ex7_fpscr_din[4] & cfpscr_thr1_din[58]) | (ex7_fpscr_din[5] & cfpscr_thr1_din[59]) | (ex7_fpscr_din[6] & cfpscr_thr1_din[60]); // zx / ze + // xx / xe + assign ex7_fpscr_din[1] = (ex7_fpscr_din1_thr0 & ex7_thread[0]) | (ex7_fpscr_din1_thr1 & ex7_thread[1]); + + assign ex7_fpscr_din[0] = (ex7_fpscr_move[0] & ex7_upd_move) | (ex7_fpscr_pipe[0] & ex7_upd_pipe) | (ex7_new_excp & (~ex7_mtfsf) & (~ex7_mtfsfi)); + + // only check the exception bits + // ox + // ux + // zx + // xx + // vxsnan + // vxisi + // vxidi + // vxzdz + // vximx + // vxvc + // vxzdz + assign ex7_new_excp = ((~ex7_mrg[3]) & ex7_fpscr_din[3]) | ((~ex7_mrg[4]) & ex7_fpscr_din[4]) | ((~ex7_mrg[5]) & ex7_fpscr_din[5]) | ((~ex7_mrg[6]) & ex7_fpscr_din[6]) | ((~ex7_mrg[7]) & ex7_fpscr_din[7]) | ((~ex7_mrg[8]) & ex7_fpscr_din[8]) | ((~ex7_mrg[9]) & ex7_fpscr_din[9]) | ((~ex7_mrg[10]) & ex7_fpscr_din[10]) | ((~ex7_mrg[11]) & ex7_fpscr_din[11]) | ((~ex7_mrg[12]) & ex7_fpscr_din[12]) | ((~ex7_mrg[21]) & ex7_fpscr_din[21]) | ((~ex7_mrg[22]) & ex7_fpscr_din[22]) | ((~ex7_mrg[23]) & ex7_fpscr_din[23]); // vximx + // vxvc + + ////############################################## + ////# EX8 latches + ////############################################## + + + tri_rlmreg_p #(.WIDTH(28)) fpscr_th0_lat( + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[7]), + .mpw1_b(mpw1_b[7]), + .mpw2_b(mpw2_b[1]), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + .act(ex7_act), + .scout(fpscr_th0_so), + .scin(fpscr_th0_si), + //----------------- + .din({ ex7_fpscr_dfp_din[0:3], + ex7_fpscr_din[0:23]}), + .dout({fpscr_dfp_th0[0:3], //LAT-- + fpscr_th0[0:23]}) //LAT-- + ); + + + tri_rlmreg_p #(.WIDTH(28)) fpscr_th1_lat( + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[7]), + .mpw1_b(mpw1_b[7]), + .mpw2_b(mpw2_b[1]), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + .act(ex7_act), //ex7_th1_act, todo: act pin + .scout(fpscr_th1_so), + .scin(fpscr_th1_si), + //----------------- + .din({ ex7_fpscr_dfp_din[0:3], + ex7_fpscr_din[0:23]}), + .dout({ fpscr_dfp_th1[0:3], //LAT-- + fpscr_th1[0:23]}) //LAT-- + ); + + tri_rlmreg_p #(.WIDTH(4)) ex8_crf_lat( + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[7]), + .mpw1_b(mpw1_b[7]), + .mpw2_b(mpw2_b[1]), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex7_act), + .thold_b(thold_0_b), + .sg(sg_0), + .scout(ex8_crf_so), + .scin(ex8_crf_si), + //----------------- + .din( ex7_cr_fld[0:3]), + .dout( ex8_cr_fld[0:3]) //LAT-- + ); + + assign f_scr_ex8_cr_fld[0:3] = ex8_cr_fld[0:3]; //output-- This is the first 4 bits of the fpscr used for speculative exceptions/cr val + assign f_scr_ex8_fx_thread0[0:3] = fpscr_th0[0:3]; //output-- + assign f_scr_cpl_fx_thread0[0:3] = cfpscr_thr0_l2[32:35]; //output-- This is the completed version, used for async fp enabled + + assign f_scr_ex8_fx_thread1[0:3] = fpscr_th1[0:3]; //output-- + assign f_scr_cpl_fx_thread1[0:3] = cfpscr_thr1_l2[32:35]; //output-- This is the completed version, used for async fp enabled + + ////############################################## + ////# read fpscr (mixed cycles) + ////############################################## + + assign fpscr_rd_dat_dfp[0:3] = (ex6_cfpscr_thrx_cr[28:31]); // write data to bit 20 is "0" + + assign fpscr_rd_dat[0:23] = (ex6_cfpscr_thrx_cr[32:55]); // write data to bit 20 is "0" + + assign ex7_mrg_dfp[0:3] = (cfpscr_thrx_cr[28:31]); // write data to bit 20 is "0" + + assign ex7_mrg[0:23] = (cfpscr_thrx_cr[32:55]); // write data to bit 20 is "0" + + assign fpscr_rd_dat[24:31] = ex6_cfpscr_thrx_cr[56:63]; + + assign f_scr_ex6_fpscr_rm_thr0[0:1] = cfpscr_thr0_l2[62:63]; + assign f_scr_ex6_fpscr_ee_thr0[0:4] = cfpscr_thr0_l2[56:60]; + assign f_scr_ex6_fpscr_ni_thr0 = cfpscr_thr0_l2[61]; + assign f_scr_ex6_fpscr_rm_thr1[0:1] = cfpscr_thr1_l2[62:63]; + assign f_scr_ex6_fpscr_ee_thr1[0:4] = cfpscr_thr1_l2[56:60]; + assign f_scr_ex6_fpscr_ni_thr1 = cfpscr_thr1_l2[61]; + + assign f_scr_ex6_fpscr_rd_dat[0:31] = fpscr_rd_dat[0:31]; + assign f_scr_ex6_fpscr_rd_dat_dfp[0:3] = fpscr_rd_dat_dfp[0:3]; + + assign f_scr_fpscr_ctrl_thr0 = cfpscr_thr0_l2[56:63]; + assign f_scr_fpscr_ctrl_thr1 = cfpscr_thr1_l2[56:63]; + + ////############################################## + ////# FPSCR History Array + ////############################################## + + assign ex7_hfpscr_pipe[3] = ex7_ox_spec | (ex7_ox_pipe_v & f_rnd_ex7_flag_ox); //ex7_mrg( 3) or --ox STICKY + assign ex7_hfpscr_pipe[4] = ex7_ux_spec | (ex7_ux_pipe_v & f_rnd_ex7_flag_ux); //ex7_mrg( 4) or --ux STICKY + assign ex7_hfpscr_pipe[5] = ex7_flag_zx; //ex7_mrg( 5) or --sticky + + assign ex7_hfpscr_pipe[6] = (ex7_fi_spec) | (ex7_fi_pipe_v & f_rnd_ex7_flag_fi); //(ex7_mrg( 6) ) or -- ex7_hfpscr_pipe(14); --sticky version of fi (XX) + + assign ex7_hfpscr_pipe[7] = ex7_flag_vxsnan; //sticky + assign ex7_hfpscr_pipe[8] = ex7_flag_vxisi; //sticky + assign ex7_hfpscr_pipe[9] = ex7_flag_vxidi; //sticky + assign ex7_hfpscr_pipe[10] = ex7_flag_vxzdz; //sticky + assign ex7_hfpscr_pipe[11] = ex7_flag_vximz; //sticky + assign ex7_hfpscr_pipe[12] = ex7_flag_vxvc; //sticky + + //(ex7_mrg(13) and ex7_compare ) or + assign ex7_hfpscr_pipe[13] = (ex7_fr_spec) | (ex7_fr_pipe_v & f_rnd_ex7_flag_up); //fr NOT sticky + //(ex7_mrg(14) and ex7_compare ) or + assign ex7_hfpscr_pipe[14] = (ex7_fi_spec) | (ex7_fi_pipe_v & f_rnd_ex7_flag_fi); //fi NOT sticky + + //(ex7_mrg(15) and ex7_fprf_hold ) or + //(ex7_mrg(15) and ex7_compare ) or + assign ex7_hfpscr_pipe[15] = (ex7_fprf_spec[0]) | (ex7_fprf_pipe_v & ex7_fprf_pipe[0]); //FPRF C NOT sticky + + //(ex7_mrg(16) and ex7_fprf_hold ) or + assign ex7_hfpscr_pipe[16] = (ex7_fprf_spec[1]) | (ex7_fprf_pipe_v & ex7_fprf_pipe[1]); //FPRF fpdd(lt) + //(ex7_mrg(17) and ex7_fprf_hold ) or + assign ex7_hfpscr_pipe[17] = (ex7_fprf_spec[2]) | (ex7_fprf_pipe_v & ex7_fprf_pipe[2]); //FPRF fpcc(gt) + //(ex7_mrg(18) and ex7_fprf_hold ) or + assign ex7_hfpscr_pipe[18] = (ex7_fprf_spec[3]) | (ex7_fprf_pipe_v & ex7_fprf_pipe[3]); //FPRF fpcc(eq) + //(ex7_mrg(19) and ex7_fprf_hold ) or + assign ex7_hfpscr_pipe[19] = (ex7_fprf_spec[4]) | (ex7_fprf_pipe_v & ex7_fprf_pipe[4]); //FPRF fpcc(nan) + + assign ex7_hfpscr_pipe[20] = tidn; // reseved bit + assign ex7_hfpscr_pipe[21] = tidn; //ex7_mrg(21); -- VXSOFT --sticky + assign ex7_hfpscr_pipe[22] = ex7_flag_vxsqrt; //ex7_mrg(22) or ex7_flag_vxsqrt ;--sticky + assign ex7_hfpscr_pipe[23] = ex7_flag_vxcvi; //ex7_mrg(23) or ex7_flag_vxcvi ;--sticky + + //generic (addressable_ports : positive $ 64; -- number of addressable register in this array + // addressbus_WIDTH : positive $ 6; -- WIDTH of the bus to address all ports (2^addressbus_WIDTH >= addressable_ports) + // port_bitwidth : positive $ 64; -- bitwidth of ports + + assign zeros[0:63] = {64{tidn}}; + + //Write + + assign we0_thr0 = f_dcd_ex7_fpscr_wr & ex7_thread[0]; + assign we0_thr1 = f_dcd_ex7_fpscr_wr & ex7_thread[1]; + assign wa0[0:5] = f_dcd_ex7_fpscr_addr[0:5]; + assign di0[0:23] = {ex7_compare, ex7_fprf_hold, ex7_upd_pipe, ex7_hfpscr_pipe[3:23]}; + + assign we1 = tidn; + assign wa1 = {6{tidn}}; + assign di1 = {24{tidn}}; + + //Read + + generate + if (THREADS == 1) + begin : oscr_val_thr1_1 + assign re0_thr0 = cp_axu_i0_t1_v[0] & (cp_axu_i0_t0_t1_t == 3'b111); + assign re0_thr1 = tidn; + assign ra0_thr0[0:5] = cp_axu_i0_t0_t1_p; + assign ra0_thr1[0:5] = 6'b000000; + end + endgenerate + + generate + if (THREADS == 2) + begin : oscr_val_thr2_1 + assign re0_thr0 = cp_axu_i0_t1_v[0] & (cp_axu_i0_t0_t1_t == 3'b111); + assign re0_thr1 = cp_axu_i0_t1_v[1] & (cp_axu_i0_t1_t1_t == 3'b111); + assign ra0_thr0[0:5] = cp_axu_i0_t0_t1_p; + assign ra0_thr1[0:5] = cp_axu_i0_t1_t1_p; + end + endgenerate + + generate + if (THREADS == 1) + begin : oscr_val_thr1_2 + assign re1_thr0 = cp_axu_i1_t1_v[0] & (cp_axu_i1_t0_t1_t == 3'b111); + assign re1_thr1 = tidn; + assign ra1_thr0[0:5] = cp_axu_i1_t0_t1_p; + assign ra1_thr1[0:5] = 6'b000000; + end + endgenerate + + generate + if (THREADS == 2) + begin : oscr_val_thr2_2 + assign re1_thr0 = cp_axu_i1_t1_v[0] & (cp_axu_i1_t0_t1_t == 3'b111); + assign re1_thr1 = cp_axu_i1_t1_v[1] & (cp_axu_i1_t1_t1_t == 3'b111); + assign ra1_thr0[0:5] = cp_axu_i1_t0_t1_p; + assign ra1_thr1[0:5] = cp_axu_i1_t1_t1_p; + end + endgenerate + + generate + if (THREADS == 1) + begin : oscr_hscr_arr_thr1 + + assign fwrite_thr0[00] = (wa0[1:5] == 5'b00000) & we0_thr0; + assign fwrite_thr0[01] = (wa0[1:5] == 5'b00001) & we0_thr0; + assign fwrite_thr0[02] = (wa0[1:5] == 5'b00010) & we0_thr0; + assign fwrite_thr0[03] = (wa0[1:5] == 5'b00011) & we0_thr0; + assign fwrite_thr0[04] = (wa0[1:5] == 5'b00100) & we0_thr0; + assign fwrite_thr0[05] = (wa0[1:5] == 5'b00101) & we0_thr0; + assign fwrite_thr0[06] = (wa0[1:5] == 5'b00110) & we0_thr0; + assign fwrite_thr0[07] = (wa0[1:5] == 5'b00111) & we0_thr0; + assign fwrite_thr0[08] = (wa0[1:5] == 5'b01000) & we0_thr0; + assign fwrite_thr0[09] = (wa0[1:5] == 5'b01001) & we0_thr0; + assign fwrite_thr0[10] = (wa0[1:5] == 5'b01010) & we0_thr0; + assign fwrite_thr0[11] = (wa0[1:5] == 5'b01011) & we0_thr0; + assign fwrite_thr0[12] = (wa0[1:5] == 5'b01100) & we0_thr0; + assign fwrite_thr0[13] = (wa0[1:5] == 5'b01101) & we0_thr0; + assign fwrite_thr0[14] = (wa0[1:5] == 5'b01110) & we0_thr0; + assign fwrite_thr0[15] = (wa0[1:5] == 5'b01111) & we0_thr0; + assign fwrite_thr0[16] = (wa0[1:5] == 5'b10000) & we0_thr0; + assign fwrite_thr0[17] = (wa0[1:5] == 5'b10001) & we0_thr0; + assign fwrite_thr0[18] = (wa0[1:5] == 5'b10010) & we0_thr0; + assign fwrite_thr0[19] = (wa0[1:5] == 5'b10011) & we0_thr0; + assign fwrite_thr0[20] = (wa0[1:5] == 5'b10100) & we0_thr0; + assign fwrite_thr0[21] = (wa0[1:5] == 5'b10101) & we0_thr0; + assign fwrite_thr0[22] = (wa0[1:5] == 5'b10110) & we0_thr0; + assign fwrite_thr0[23] = (wa0[1:5] == 5'b10111) & we0_thr0; + assign fwrite_thr0[24] = (wa0[1:5] == 5'b11000) & we0_thr0; + assign fwrite_thr0[25] = (wa0[1:5] == 5'b11001) & we0_thr0; + assign fwrite_thr0[26] = (wa0[1:5] == 5'b11010) & we0_thr0; + assign fwrite_thr0[27] = (wa0[1:5] == 5'b11011) & we0_thr0; + assign fwrite_thr0[28] = (wa0[1:5] == 5'b11100) & we0_thr0; + assign fwrite_thr0[29] = (wa0[1:5] == 5'b11101) & we0_thr0; + assign fwrite_thr0[30] = (wa0[1:5] == 5'b11110) & we0_thr0; + assign fwrite_thr0[31] = (wa0[1:5] == 5'b11111) & we0_thr0; + + + + + assign fwrite_thr0_b = (~fwrite_thr0); + + assign fread0_thr0[00] = (ra0_thr0[1:5] == 5'b00000) & re0_thr0; + assign fread0_thr0[01] = (ra0_thr0[1:5] == 5'b00001) & re0_thr0; + assign fread0_thr0[02] = (ra0_thr0[1:5] == 5'b00010) & re0_thr0; + assign fread0_thr0[03] = (ra0_thr0[1:5] == 5'b00011) & re0_thr0; + assign fread0_thr0[04] = (ra0_thr0[1:5] == 5'b00100) & re0_thr0; + assign fread0_thr0[05] = (ra0_thr0[1:5] == 5'b00101) & re0_thr0; + assign fread0_thr0[06] = (ra0_thr0[1:5] == 5'b00110) & re0_thr0; + assign fread0_thr0[07] = (ra0_thr0[1:5] == 5'b00111) & re0_thr0; + assign fread0_thr0[08] = (ra0_thr0[1:5] == 5'b01000) & re0_thr0; + assign fread0_thr0[09] = (ra0_thr0[1:5] == 5'b01001) & re0_thr0; + assign fread0_thr0[10] = (ra0_thr0[1:5] == 5'b01010) & re0_thr0; + assign fread0_thr0[11] = (ra0_thr0[1:5] == 5'b01011) & re0_thr0; + assign fread0_thr0[12] = (ra0_thr0[1:5] == 5'b01100) & re0_thr0; + assign fread0_thr0[13] = (ra0_thr0[1:5] == 5'b01101) & re0_thr0; + assign fread0_thr0[14] = (ra0_thr0[1:5] == 5'b01110) & re0_thr0; + assign fread0_thr0[15] = (ra0_thr0[1:5] == 5'b01111) & re0_thr0; + assign fread0_thr0[16] = (ra0_thr0[1:5] == 5'b10000) & re0_thr0; + assign fread0_thr0[17] = (ra0_thr0[1:5] == 5'b10001) & re0_thr0; + assign fread0_thr0[18] = (ra0_thr0[1:5] == 5'b10010) & re0_thr0; + assign fread0_thr0[19] = (ra0_thr0[1:5] == 5'b10011) & re0_thr0; + assign fread0_thr0[20] = (ra0_thr0[1:5] == 5'b10100) & re0_thr0; + assign fread0_thr0[21] = (ra0_thr0[1:5] == 5'b10101) & re0_thr0; + assign fread0_thr0[22] = (ra0_thr0[1:5] == 5'b10110) & re0_thr0; + assign fread0_thr0[23] = (ra0_thr0[1:5] == 5'b10111) & re0_thr0; + assign fread0_thr0[24] = (ra0_thr0[1:5] == 5'b11000) & re0_thr0; + assign fread0_thr0[25] = (ra0_thr0[1:5] == 5'b11001) & re0_thr0; + assign fread0_thr0[26] = (ra0_thr0[1:5] == 5'b11010) & re0_thr0; + assign fread0_thr0[27] = (ra0_thr0[1:5] == 5'b11011) & re0_thr0; + assign fread0_thr0[28] = (ra0_thr0[1:5] == 5'b11100) & re0_thr0; + assign fread0_thr0[29] = (ra0_thr0[1:5] == 5'b11101) & re0_thr0; + assign fread0_thr0[30] = (ra0_thr0[1:5] == 5'b11110) & re0_thr0; + assign fread0_thr0[31] = (ra0_thr0[1:5] == 5'b11111) & re0_thr0; + + + + assign fread1_thr0[00] = (ra1_thr0[1:5] == 5'b00000) & re1_thr0; + assign fread1_thr0[01] = (ra1_thr0[1:5] == 5'b00001) & re1_thr0; + assign fread1_thr0[02] = (ra1_thr0[1:5] == 5'b00010) & re1_thr0; + assign fread1_thr0[03] = (ra1_thr0[1:5] == 5'b00011) & re1_thr0; + assign fread1_thr0[04] = (ra1_thr0[1:5] == 5'b00100) & re1_thr0; + assign fread1_thr0[05] = (ra1_thr0[1:5] == 5'b00101) & re1_thr0; + assign fread1_thr0[06] = (ra1_thr0[1:5] == 5'b00110) & re1_thr0; + assign fread1_thr0[07] = (ra1_thr0[1:5] == 5'b00111) & re1_thr0; + assign fread1_thr0[08] = (ra1_thr0[1:5] == 5'b01000) & re1_thr0; + assign fread1_thr0[09] = (ra1_thr0[1:5] == 5'b01001) & re1_thr0; + assign fread1_thr0[10] = (ra1_thr0[1:5] == 5'b01010) & re1_thr0; + assign fread1_thr0[11] = (ra1_thr0[1:5] == 5'b01011) & re1_thr0; + assign fread1_thr0[12] = (ra1_thr0[1:5] == 5'b01100) & re1_thr0; + assign fread1_thr0[13] = (ra1_thr0[1:5] == 5'b01101) & re1_thr0; + assign fread1_thr0[14] = (ra1_thr0[1:5] == 5'b01110) & re1_thr0; + assign fread1_thr0[15] = (ra1_thr0[1:5] == 5'b01111) & re1_thr0; + assign fread1_thr0[16] = (ra1_thr0[1:5] == 5'b10000) & re1_thr0; + assign fread1_thr0[17] = (ra1_thr0[1:5] == 5'b10001) & re1_thr0; + assign fread1_thr0[18] = (ra1_thr0[1:5] == 5'b10010) & re1_thr0; + assign fread1_thr0[19] = (ra1_thr0[1:5] == 5'b10011) & re1_thr0; + assign fread1_thr0[20] = (ra1_thr0[1:5] == 5'b10100) & re1_thr0; + assign fread1_thr0[21] = (ra1_thr0[1:5] == 5'b10101) & re1_thr0; + assign fread1_thr0[22] = (ra1_thr0[1:5] == 5'b10110) & re1_thr0; + assign fread1_thr0[23] = (ra1_thr0[1:5] == 5'b10111) & re1_thr0; + assign fread1_thr0[24] = (ra1_thr0[1:5] == 5'b11000) & re1_thr0; + assign fread1_thr0[25] = (ra1_thr0[1:5] == 5'b11001) & re1_thr0; + assign fread1_thr0[26] = (ra1_thr0[1:5] == 5'b11010) & re1_thr0; + assign fread1_thr0[27] = (ra1_thr0[1:5] == 5'b11011) & re1_thr0; + assign fread1_thr0[28] = (ra1_thr0[1:5] == 5'b11100) & re1_thr0; + assign fread1_thr0[29] = (ra1_thr0[1:5] == 5'b11101) & re1_thr0; + assign fread1_thr0[30] = (ra1_thr0[1:5] == 5'b11110) & re1_thr0; + assign fread1_thr0[31] = (ra1_thr0[1:5] == 5'b11111) & re1_thr0; + + + + + begin : xhdl1 + // genvar i; + for (i = 0; i <= 31; i = i + 1) + begin : writeport_hfpscr_thr0 + assign hfpscr_thr0_din[24 * i:(24 * i) + 23] = ((hfpscr_thr0_q[24 * i:(24 * i) + 23] & {24{fwrite_thr0_b[i]}}) | + (di0 & {24{fwrite_thr0[i]}})); + end + end + + + tri_rlmreg_p #(.WIDTH(768 + 64)) hfpscr_thr0_lat( + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[7]), + .mpw1_b(mpw1_b[7]), + .mpw2_b(mpw2_b[1]), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(thold_0_b), + .sg(sg_0), + .scout(hfpscr_thr0_so), + .scin(hfpscr_thr0_si), + //----------------- + .din({ hfpscr_thr0_din, + fread0_thr0, + fread1_thr0 }), + + //----------------- + .dout({ hfpscr_thr0_q, + fread0_thr0_q, + fread1_thr0_q }) + ); + + assign hfpscr_thr0_si[0:831] = {hfpscr_thr0_so[1:831], hfpscr_thr0_so[0]};// todo + + + assign do0_thr0 = ((hfpscr_thr0_q[24 * 00:(24 * 00) + 23] & {24{fread0_thr0_q[00]}}) | + (hfpscr_thr0_q[24 * 01:(24 * 01) + 23] & {24{fread0_thr0_q[01]}}) | + (hfpscr_thr0_q[24 * 02:(24 * 02) + 23] & {24{fread0_thr0_q[02]}}) | + (hfpscr_thr0_q[24 * 03:(24 * 03) + 23] & {24{fread0_thr0_q[03]}}) | + (hfpscr_thr0_q[24 * 04:(24 * 04) + 23] & {24{fread0_thr0_q[04]}}) | + (hfpscr_thr0_q[24 * 05:(24 * 05) + 23] & {24{fread0_thr0_q[05]}}) | + (hfpscr_thr0_q[24 * 06:(24 * 06) + 23] & {24{fread0_thr0_q[06]}}) | + (hfpscr_thr0_q[24 * 07:(24 * 07) + 23] & {24{fread0_thr0_q[07]}}) | + (hfpscr_thr0_q[24 * 08:(24 * 08) + 23] & {24{fread0_thr0_q[08]}}) | + (hfpscr_thr0_q[24 * 09:(24 * 09) + 23] & {24{fread0_thr0_q[09]}}) | + (hfpscr_thr0_q[24 * 10:(24 * 10) + 23] & {24{fread0_thr0_q[10]}}) | + (hfpscr_thr0_q[24 * 11:(24 * 11) + 23] & {24{fread0_thr0_q[11]}}) | + (hfpscr_thr0_q[24 * 12:(24 * 12) + 23] & {24{fread0_thr0_q[12]}}) | + (hfpscr_thr0_q[24 * 13:(24 * 13) + 23] & {24{fread0_thr0_q[13]}}) | + (hfpscr_thr0_q[24 * 14:(24 * 14) + 23] & {24{fread0_thr0_q[14]}}) | + (hfpscr_thr0_q[24 * 15:(24 * 15) + 23] & {24{fread0_thr0_q[15]}}) | + (hfpscr_thr0_q[24 * 16:(24 * 16) + 23] & {24{fread0_thr0_q[16]}}) | + (hfpscr_thr0_q[24 * 17:(24 * 17) + 23] & {24{fread0_thr0_q[17]}}) | + (hfpscr_thr0_q[24 * 18:(24 * 18) + 23] & {24{fread0_thr0_q[18]}}) | + (hfpscr_thr0_q[24 * 19:(24 * 19) + 23] & {24{fread0_thr0_q[19]}}) | + (hfpscr_thr0_q[24 * 20:(24 * 20) + 23] & {24{fread0_thr0_q[20]}}) | + (hfpscr_thr0_q[24 * 21:(24 * 21) + 23] & {24{fread0_thr0_q[21]}}) | + (hfpscr_thr0_q[24 * 22:(24 * 22) + 23] & {24{fread0_thr0_q[22]}}) | + (hfpscr_thr0_q[24 * 23:(24 * 23) + 23] & {24{fread0_thr0_q[23]}}) | + (hfpscr_thr0_q[24 * 24:(24 * 24) + 23] & {24{fread0_thr0_q[24]}}) | + (hfpscr_thr0_q[24 * 25:(24 * 25) + 23] & {24{fread0_thr0_q[25]}}) | + (hfpscr_thr0_q[24 * 26:(24 * 26) + 23] & {24{fread0_thr0_q[26]}}) | + (hfpscr_thr0_q[24 * 27:(24 * 27) + 23] & {24{fread0_thr0_q[27]}}) | + (hfpscr_thr0_q[24 * 28:(24 * 28) + 23] & {24{fread0_thr0_q[28]}}) | + (hfpscr_thr0_q[24 * 29:(24 * 29) + 23] & {24{fread0_thr0_q[29]}}) | + (hfpscr_thr0_q[24 * 30:(24 * 30) + 23] & {24{fread0_thr0_q[30]}}) | + (hfpscr_thr0_q[24 * 31:(24 * 31) + 23] & {24{fread0_thr0_q[31]}})); + + + + + assign do1_thr0 = ((hfpscr_thr0_q[24 * 00:(24 * 00) + 23] & {24{fread1_thr0_q[00]}}) | + (hfpscr_thr0_q[24 * 01:(24 * 01) + 23] & {24{fread1_thr0_q[01]}}) | + (hfpscr_thr0_q[24 * 02:(24 * 02) + 23] & {24{fread1_thr0_q[02]}}) | + (hfpscr_thr0_q[24 * 03:(24 * 03) + 23] & {24{fread1_thr0_q[03]}}) | + (hfpscr_thr0_q[24 * 04:(24 * 04) + 23] & {24{fread1_thr0_q[04]}}) | + (hfpscr_thr0_q[24 * 05:(24 * 05) + 23] & {24{fread1_thr0_q[05]}}) | + (hfpscr_thr0_q[24 * 06:(24 * 06) + 23] & {24{fread1_thr0_q[06]}}) | + (hfpscr_thr0_q[24 * 07:(24 * 07) + 23] & {24{fread1_thr0_q[07]}}) | + (hfpscr_thr0_q[24 * 08:(24 * 08) + 23] & {24{fread1_thr0_q[08]}}) | + (hfpscr_thr0_q[24 * 09:(24 * 09) + 23] & {24{fread1_thr0_q[09]}}) | + (hfpscr_thr0_q[24 * 10:(24 * 10) + 23] & {24{fread1_thr0_q[10]}}) | + (hfpscr_thr0_q[24 * 11:(24 * 11) + 23] & {24{fread1_thr0_q[11]}}) | + (hfpscr_thr0_q[24 * 12:(24 * 12) + 23] & {24{fread1_thr0_q[12]}}) | + (hfpscr_thr0_q[24 * 13:(24 * 13) + 23] & {24{fread1_thr0_q[13]}}) | + (hfpscr_thr0_q[24 * 14:(24 * 14) + 23] & {24{fread1_thr0_q[14]}}) | + (hfpscr_thr0_q[24 * 15:(24 * 15) + 23] & {24{fread1_thr0_q[15]}}) | + (hfpscr_thr0_q[24 * 16:(24 * 16) + 23] & {24{fread1_thr0_q[16]}}) | + (hfpscr_thr0_q[24 * 17:(24 * 17) + 23] & {24{fread1_thr0_q[17]}}) | + (hfpscr_thr0_q[24 * 18:(24 * 18) + 23] & {24{fread1_thr0_q[18]}}) | + (hfpscr_thr0_q[24 * 19:(24 * 19) + 23] & {24{fread1_thr0_q[19]}}) | + (hfpscr_thr0_q[24 * 20:(24 * 20) + 23] & {24{fread1_thr0_q[20]}}) | + (hfpscr_thr0_q[24 * 21:(24 * 21) + 23] & {24{fread1_thr0_q[21]}}) | + (hfpscr_thr0_q[24 * 22:(24 * 22) + 23] & {24{fread1_thr0_q[22]}}) | + (hfpscr_thr0_q[24 * 23:(24 * 23) + 23] & {24{fread1_thr0_q[23]}}) | + (hfpscr_thr0_q[24 * 24:(24 * 24) + 23] & {24{fread1_thr0_q[24]}}) | + (hfpscr_thr0_q[24 * 25:(24 * 25) + 23] & {24{fread1_thr0_q[25]}}) | + (hfpscr_thr0_q[24 * 26:(24 * 26) + 23] & {24{fread1_thr0_q[26]}}) | + (hfpscr_thr0_q[24 * 27:(24 * 27) + 23] & {24{fread1_thr0_q[27]}}) | + (hfpscr_thr0_q[24 * 28:(24 * 28) + 23] & {24{fread1_thr0_q[28]}}) | + (hfpscr_thr0_q[24 * 29:(24 * 29) + 23] & {24{fread1_thr0_q[29]}}) | + (hfpscr_thr0_q[24 * 30:(24 * 30) + 23] & {24{fread1_thr0_q[30]}}) | + (hfpscr_thr0_q[24 * 31:(24 * 31) + 23] & {24{fread1_thr0_q[31]}})); + + + + // thread 1: + + assign fwrite_thr1 = {32{1'b0}}; + + assign fwrite_thr1_b = (~fwrite_thr1); + + assign fread0_thr1 = {32{1'b0}}; + + assign fread1_thr1 = {32{1'b0}}; + + assign hfpscr_thr1_din = {576{1'b0}}; + + assign do0_thr1 = {24{1'b0}}; + assign do1_thr1 = {24{1'b0}}; + end + endgenerate + + generate + if (THREADS == 2) + begin : oscr_hscr_arr_thr2 + // FPSCR History Array + // hscr_arr_thr0: entity tri.tri_64xxx_2r2w generic map ( expand_type => expand_type) + // port map ( + // clk => nclk , + // re0 => re0_thr0 , + // ra0 => ra0_thr0 , + // do0 => do0_thr0 , + + // re1 => re1_thr0 , + // ra1 => ra1_thr0 , + // do1 => do1_thr0 , + + // we0 => we0_thr0 , + // wa0 => wa0(0 to 5) , + // di0 => di0(0 to 63) , + // we1 => we1 , + // wa1 => wa1(0 to 5) , + // di1 => di1(0 to 63) ); + + // hscr_arr_thr1: entity tri.tri_64xxx_2r2w generic map ( expand_type => expand_type) + // port map ( + // clk => nclk , + // re0 => re0_thr1 , + // ra0 => ra0_thr1 , + // do0 => do0_thr1 , + + // re1 => re1_thr1 , + // ra1 => ra1_thr1 , + // do1 => do1_thr1 , + + // we0 => we0_thr1 , + // wa0 => wa0(0 to 5) , + // di0 => di0(0 to 63) , + // we1 => we1 , + // wa1 => wa1(0 to 5) , + // di1 => di1(0 to 63) ); + + assign fwrite_thr0[00] = (wa0[1:5] == 5'b00000) & we0_thr0; + assign fwrite_thr0[01] = (wa0[1:5] == 5'b00001) & we0_thr0; + assign fwrite_thr0[02] = (wa0[1:5] == 5'b00010) & we0_thr0; + assign fwrite_thr0[03] = (wa0[1:5] == 5'b00011) & we0_thr0; + assign fwrite_thr0[04] = (wa0[1:5] == 5'b00100) & we0_thr0; + assign fwrite_thr0[05] = (wa0[1:5] == 5'b00101) & we0_thr0; + assign fwrite_thr0[06] = (wa0[1:5] == 5'b00110) & we0_thr0; + assign fwrite_thr0[07] = (wa0[1:5] == 5'b00111) & we0_thr0; + assign fwrite_thr0[08] = (wa0[1:5] == 5'b01000) & we0_thr0; + assign fwrite_thr0[09] = (wa0[1:5] == 5'b01001) & we0_thr0; + assign fwrite_thr0[10] = (wa0[1:5] == 5'b01010) & we0_thr0; + assign fwrite_thr0[11] = (wa0[1:5] == 5'b01011) & we0_thr0; + assign fwrite_thr0[12] = (wa0[1:5] == 5'b01100) & we0_thr0; + assign fwrite_thr0[13] = (wa0[1:5] == 5'b01101) & we0_thr0; + assign fwrite_thr0[14] = (wa0[1:5] == 5'b01110) & we0_thr0; + assign fwrite_thr0[15] = (wa0[1:5] == 5'b01111) & we0_thr0; + assign fwrite_thr0[16] = (wa0[1:5] == 5'b10000) & we0_thr0; + assign fwrite_thr0[17] = (wa0[1:5] == 5'b10001) & we0_thr0; + assign fwrite_thr0[18] = (wa0[1:5] == 5'b10010) & we0_thr0; + assign fwrite_thr0[19] = (wa0[1:5] == 5'b10011) & we0_thr0; + assign fwrite_thr0[20] = (wa0[1:5] == 5'b10100) & we0_thr0; + assign fwrite_thr0[21] = (wa0[1:5] == 5'b10101) & we0_thr0; + assign fwrite_thr0[22] = (wa0[1:5] == 5'b10110) & we0_thr0; + assign fwrite_thr0[23] = (wa0[1:5] == 5'b10111) & we0_thr0; + + assign fwrite_thr0_b = (~fwrite_thr0); + assign fread0_thr0[00] = (ra0_thr0[1:5] == 5'b00000) & re0_thr0; + assign fread0_thr0[01] = (ra0_thr0[1:5] == 5'b00001) & re0_thr0; + assign fread0_thr0[02] = (ra0_thr0[1:5] == 5'b00010) & re0_thr0; + assign fread0_thr0[03] = (ra0_thr0[1:5] == 5'b00011) & re0_thr0; + assign fread0_thr0[04] = (ra0_thr0[1:5] == 5'b00100) & re0_thr0; + assign fread0_thr0[05] = (ra0_thr0[1:5] == 5'b00101) & re0_thr0; + assign fread0_thr0[06] = (ra0_thr0[1:5] == 5'b00110) & re0_thr0; + assign fread0_thr0[07] = (ra0_thr0[1:5] == 5'b00111) & re0_thr0; + assign fread0_thr0[08] = (ra0_thr0[1:5] == 5'b01000) & re0_thr0; + assign fread0_thr0[09] = (ra0_thr0[1:5] == 5'b01001) & re0_thr0; + assign fread0_thr0[10] = (ra0_thr0[1:5] == 5'b01010) & re0_thr0; + assign fread0_thr0[11] = (ra0_thr0[1:5] == 5'b01011) & re0_thr0; + assign fread0_thr0[12] = (ra0_thr0[1:5] == 5'b01100) & re0_thr0; + assign fread0_thr0[13] = (ra0_thr0[1:5] == 5'b01101) & re0_thr0; + assign fread0_thr0[14] = (ra0_thr0[1:5] == 5'b01110) & re0_thr0; + assign fread0_thr0[15] = (ra0_thr0[1:5] == 5'b01111) & re0_thr0; + assign fread0_thr0[16] = (ra0_thr0[1:5] == 5'b10000) & re0_thr0; + assign fread0_thr0[17] = (ra0_thr0[1:5] == 5'b10001) & re0_thr0; + assign fread0_thr0[18] = (ra0_thr0[1:5] == 5'b10010) & re0_thr0; + assign fread0_thr0[19] = (ra0_thr0[1:5] == 5'b10011) & re0_thr0; + assign fread0_thr0[20] = (ra0_thr0[1:5] == 5'b10100) & re0_thr0; + assign fread0_thr0[21] = (ra0_thr0[1:5] == 5'b10101) & re0_thr0; + assign fread0_thr0[22] = (ra0_thr0[1:5] == 5'b10110) & re0_thr0; + assign fread0_thr0[23] = (ra0_thr0[1:5] == 5'b10111) & re0_thr0; + + assign fread0_thr0[24:31] = {8{tidn}}; + + + + assign fread1_thr0[00] = (ra1_thr0[1:5] == 5'b00000) & re1_thr0; + assign fread1_thr0[01] = (ra1_thr0[1:5] == 5'b00001) & re1_thr0; + assign fread1_thr0[02] = (ra1_thr0[1:5] == 5'b00010) & re1_thr0; + assign fread1_thr0[03] = (ra1_thr0[1:5] == 5'b00011) & re1_thr0; + assign fread1_thr0[04] = (ra1_thr0[1:5] == 5'b00100) & re1_thr0; + assign fread1_thr0[05] = (ra1_thr0[1:5] == 5'b00101) & re1_thr0; + assign fread1_thr0[06] = (ra1_thr0[1:5] == 5'b00110) & re1_thr0; + assign fread1_thr0[07] = (ra1_thr0[1:5] == 5'b00111) & re1_thr0; + assign fread1_thr0[08] = (ra1_thr0[1:5] == 5'b01000) & re1_thr0; + assign fread1_thr0[09] = (ra1_thr0[1:5] == 5'b01001) & re1_thr0; + assign fread1_thr0[10] = (ra1_thr0[1:5] == 5'b01010) & re1_thr0; + assign fread1_thr0[11] = (ra1_thr0[1:5] == 5'b01011) & re1_thr0; + assign fread1_thr0[12] = (ra1_thr0[1:5] == 5'b01100) & re1_thr0; + assign fread1_thr0[13] = (ra1_thr0[1:5] == 5'b01101) & re1_thr0; + assign fread1_thr0[14] = (ra1_thr0[1:5] == 5'b01110) & re1_thr0; + assign fread1_thr0[15] = (ra1_thr0[1:5] == 5'b01111) & re1_thr0; + assign fread1_thr0[16] = (ra1_thr0[1:5] == 5'b10000) & re1_thr0; + assign fread1_thr0[17] = (ra1_thr0[1:5] == 5'b10001) & re1_thr0; + assign fread1_thr0[18] = (ra1_thr0[1:5] == 5'b10010) & re1_thr0; + assign fread1_thr0[19] = (ra1_thr0[1:5] == 5'b10011) & re1_thr0; + assign fread1_thr0[20] = (ra1_thr0[1:5] == 5'b10100) & re1_thr0; + assign fread1_thr0[21] = (ra1_thr0[1:5] == 5'b10101) & re1_thr0; + assign fread1_thr0[22] = (ra1_thr0[1:5] == 5'b10110) & re1_thr0; + assign fread1_thr0[23] = (ra1_thr0[1:5] == 5'b10111) & re1_thr0; + + assign fread1_thr0[24:31] = {8{tidn}}; + + + + + begin : xhdl2 + // genvar i; + for (i = 0; i <= 23; i = i + 1) + begin : writeport_hfpscr_thr0 + assign hfpscr_thr0_din[24 * i:(24 * i) + 23] = ((hfpscr_thr0_q[24 * i:(24 * i) + 23] & {24{fwrite_thr0_b[i]}}) | + (di0 & {24{fwrite_thr0[i]}})); + end + end + + + tri_rlmreg_p #(.WIDTH(576 + 64)) hfpscr_thr0_lat( + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[7]), + .mpw1_b(mpw1_b[7]), + .mpw2_b(mpw2_b[1]), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(thold_0_b), + .sg(sg_0), + .scout(hfpscr_thr0_so[0:639]), + .scin(hfpscr_thr0_si[0:639]), + //----------------- + .din({ hfpscr_thr0_din[0:575], + fread0_thr0, + fread1_thr0 }), + + //----------------- + .dout({ hfpscr_thr0_q[0:575], + fread0_thr0_q, + fread1_thr0_q }) + ); + + assign hfpscr_thr0_din[576:767] = {192{tidn}}; + assign hfpscr_thr0_q[576:767] = {192{tidn}}; + + assign hfpscr_thr0_si[0:831] = {hfpscr_thr0_so[1:831], hfpscr_thr0_so[0]};// todo + + assign do0_thr0 = ((hfpscr_thr0_q[24 * 00:(24 * 00) + 23] & {24{fread0_thr0_q[00]}}) | + (hfpscr_thr0_q[24 * 01:(24 * 01) + 23] & {24{fread0_thr0_q[01]}}) | + (hfpscr_thr0_q[24 * 02:(24 * 02) + 23] & {24{fread0_thr0_q[02]}}) | + (hfpscr_thr0_q[24 * 03:(24 * 03) + 23] & {24{fread0_thr0_q[03]}}) | + (hfpscr_thr0_q[24 * 04:(24 * 04) + 23] & {24{fread0_thr0_q[04]}}) | + (hfpscr_thr0_q[24 * 05:(24 * 05) + 23] & {24{fread0_thr0_q[05]}}) | + (hfpscr_thr0_q[24 * 06:(24 * 06) + 23] & {24{fread0_thr0_q[06]}}) | + (hfpscr_thr0_q[24 * 07:(24 * 07) + 23] & {24{fread0_thr0_q[07]}}) | + (hfpscr_thr0_q[24 * 08:(24 * 08) + 23] & {24{fread0_thr0_q[08]}}) | + (hfpscr_thr0_q[24 * 09:(24 * 09) + 23] & {24{fread0_thr0_q[09]}}) | + (hfpscr_thr0_q[24 * 10:(24 * 10) + 23] & {24{fread0_thr0_q[10]}}) | + (hfpscr_thr0_q[24 * 11:(24 * 11) + 23] & {24{fread0_thr0_q[11]}}) | + (hfpscr_thr0_q[24 * 12:(24 * 12) + 23] & {24{fread0_thr0_q[12]}}) | + (hfpscr_thr0_q[24 * 13:(24 * 13) + 23] & {24{fread0_thr0_q[13]}}) | + (hfpscr_thr0_q[24 * 14:(24 * 14) + 23] & {24{fread0_thr0_q[14]}}) | + (hfpscr_thr0_q[24 * 15:(24 * 15) + 23] & {24{fread0_thr0_q[15]}}) | + (hfpscr_thr0_q[24 * 16:(24 * 16) + 23] & {24{fread0_thr0_q[16]}}) | + (hfpscr_thr0_q[24 * 17:(24 * 17) + 23] & {24{fread0_thr0_q[17]}}) | + (hfpscr_thr0_q[24 * 18:(24 * 18) + 23] & {24{fread0_thr0_q[18]}}) | + (hfpscr_thr0_q[24 * 19:(24 * 19) + 23] & {24{fread0_thr0_q[19]}}) | + (hfpscr_thr0_q[24 * 20:(24 * 20) + 23] & {24{fread0_thr0_q[20]}}) | + (hfpscr_thr0_q[24 * 21:(24 * 21) + 23] & {24{fread0_thr0_q[21]}}) | + (hfpscr_thr0_q[24 * 22:(24 * 22) + 23] & {24{fread0_thr0_q[22]}}) | + (hfpscr_thr0_q[24 * 23:(24 * 23) + 23] & {24{fread0_thr0_q[23]}})); + + + + + assign do1_thr0 = ((hfpscr_thr0_q[24 * 00:(24 * 00) + 23] & {24{fread1_thr0_q[00]}}) | + (hfpscr_thr0_q[24 * 01:(24 * 01) + 23] & {24{fread1_thr0_q[01]}}) | + (hfpscr_thr0_q[24 * 02:(24 * 02) + 23] & {24{fread1_thr0_q[02]}}) | + (hfpscr_thr0_q[24 * 03:(24 * 03) + 23] & {24{fread1_thr0_q[03]}}) | + (hfpscr_thr0_q[24 * 04:(24 * 04) + 23] & {24{fread1_thr0_q[04]}}) | + (hfpscr_thr0_q[24 * 05:(24 * 05) + 23] & {24{fread1_thr0_q[05]}}) | + (hfpscr_thr0_q[24 * 06:(24 * 06) + 23] & {24{fread1_thr0_q[06]}}) | + (hfpscr_thr0_q[24 * 07:(24 * 07) + 23] & {24{fread1_thr0_q[07]}}) | + (hfpscr_thr0_q[24 * 08:(24 * 08) + 23] & {24{fread1_thr0_q[08]}}) | + (hfpscr_thr0_q[24 * 09:(24 * 09) + 23] & {24{fread1_thr0_q[09]}}) | + (hfpscr_thr0_q[24 * 10:(24 * 10) + 23] & {24{fread1_thr0_q[10]}}) | + (hfpscr_thr0_q[24 * 11:(24 * 11) + 23] & {24{fread1_thr0_q[11]}}) | + (hfpscr_thr0_q[24 * 12:(24 * 12) + 23] & {24{fread1_thr0_q[12]}}) | + (hfpscr_thr0_q[24 * 13:(24 * 13) + 23] & {24{fread1_thr0_q[13]}}) | + (hfpscr_thr0_q[24 * 14:(24 * 14) + 23] & {24{fread1_thr0_q[14]}}) | + (hfpscr_thr0_q[24 * 15:(24 * 15) + 23] & {24{fread1_thr0_q[15]}}) | + (hfpscr_thr0_q[24 * 16:(24 * 16) + 23] & {24{fread1_thr0_q[16]}}) | + (hfpscr_thr0_q[24 * 17:(24 * 17) + 23] & {24{fread1_thr0_q[17]}}) | + (hfpscr_thr0_q[24 * 18:(24 * 18) + 23] & {24{fread1_thr0_q[18]}}) | + (hfpscr_thr0_q[24 * 19:(24 * 19) + 23] & {24{fread1_thr0_q[19]}}) | + (hfpscr_thr0_q[24 * 20:(24 * 20) + 23] & {24{fread1_thr0_q[20]}}) | + (hfpscr_thr0_q[24 * 21:(24 * 21) + 23] & {24{fread1_thr0_q[21]}}) | + (hfpscr_thr0_q[24 * 22:(24 * 22) + 23] & {24{fread1_thr0_q[22]}}) | + (hfpscr_thr0_q[24 * 23:(24 * 23) + 23] & {24{fread1_thr0_q[23]}})); + + + + // thread 1: + assign fwrite_thr1[00] = (wa0[1:5] == 5'b00000) & we0_thr1; + assign fwrite_thr1[01] = (wa0[1:5] == 5'b00001) & we0_thr1; + assign fwrite_thr1[02] = (wa0[1:5] == 5'b00010) & we0_thr1; + assign fwrite_thr1[03] = (wa0[1:5] == 5'b00011) & we0_thr1; + assign fwrite_thr1[04] = (wa0[1:5] == 5'b00100) & we0_thr1; + assign fwrite_thr1[05] = (wa0[1:5] == 5'b00101) & we0_thr1; + assign fwrite_thr1[06] = (wa0[1:5] == 5'b00110) & we0_thr1; + assign fwrite_thr1[07] = (wa0[1:5] == 5'b00111) & we0_thr1; + assign fwrite_thr1[08] = (wa0[1:5] == 5'b01000) & we0_thr1; + assign fwrite_thr1[09] = (wa0[1:5] == 5'b01001) & we0_thr1; + assign fwrite_thr1[10] = (wa0[1:5] == 5'b01010) & we0_thr1; + assign fwrite_thr1[11] = (wa0[1:5] == 5'b01011) & we0_thr1; + assign fwrite_thr1[12] = (wa0[1:5] == 5'b01100) & we0_thr1; + assign fwrite_thr1[13] = (wa0[1:5] == 5'b01101) & we0_thr1; + assign fwrite_thr1[14] = (wa0[1:5] == 5'b01110) & we0_thr1; + assign fwrite_thr1[15] = (wa0[1:5] == 5'b01111) & we0_thr1; + assign fwrite_thr1[16] = (wa0[1:5] == 5'b10000) & we0_thr1; + assign fwrite_thr1[17] = (wa0[1:5] == 5'b10001) & we0_thr1; + assign fwrite_thr1[18] = (wa0[1:5] == 5'b10010) & we0_thr1; + assign fwrite_thr1[19] = (wa0[1:5] == 5'b10011) & we0_thr1; + assign fwrite_thr1[20] = (wa0[1:5] == 5'b10100) & we0_thr1; + assign fwrite_thr1[21] = (wa0[1:5] == 5'b10101) & we0_thr1; + assign fwrite_thr1[22] = (wa0[1:5] == 5'b10110) & we0_thr1; + assign fwrite_thr1[23] = (wa0[1:5] == 5'b10111) & we0_thr1; + + assign fwrite_thr1_b = (~fwrite_thr1); + + assign fread0_thr1[00] = (ra0_thr1[1:5] == 5'b00000) & re0_thr1; + assign fread0_thr1[01] = (ra0_thr1[1:5] == 5'b00001) & re0_thr1; + assign fread0_thr1[02] = (ra0_thr1[1:5] == 5'b00010) & re0_thr1; + assign fread0_thr1[03] = (ra0_thr1[1:5] == 5'b00011) & re0_thr1; + assign fread0_thr1[04] = (ra0_thr1[1:5] == 5'b00100) & re0_thr1; + assign fread0_thr1[05] = (ra0_thr1[1:5] == 5'b00101) & re0_thr1; + assign fread0_thr1[06] = (ra0_thr1[1:5] == 5'b00110) & re0_thr1; + assign fread0_thr1[07] = (ra0_thr1[1:5] == 5'b00111) & re0_thr1; + assign fread0_thr1[08] = (ra0_thr1[1:5] == 5'b01000) & re0_thr1; + assign fread0_thr1[09] = (ra0_thr1[1:5] == 5'b01001) & re0_thr1; + assign fread0_thr1[10] = (ra0_thr1[1:5] == 5'b01010) & re0_thr1; + assign fread0_thr1[11] = (ra0_thr1[1:5] == 5'b01011) & re0_thr1; + assign fread0_thr1[12] = (ra0_thr1[1:5] == 5'b01100) & re0_thr1; + assign fread0_thr1[13] = (ra0_thr1[1:5] == 5'b01101) & re0_thr1; + assign fread0_thr1[14] = (ra0_thr1[1:5] == 5'b01110) & re0_thr1; + assign fread0_thr1[15] = (ra0_thr1[1:5] == 5'b01111) & re0_thr1; + assign fread0_thr1[16] = (ra0_thr1[1:5] == 5'b10000) & re0_thr1; + assign fread0_thr1[17] = (ra0_thr1[1:5] == 5'b10001) & re0_thr1; + assign fread0_thr1[18] = (ra0_thr1[1:5] == 5'b10010) & re0_thr1; + assign fread0_thr1[19] = (ra0_thr1[1:5] == 5'b10011) & re0_thr1; + assign fread0_thr1[20] = (ra0_thr1[1:5] == 5'b10100) & re0_thr1; + assign fread0_thr1[21] = (ra0_thr1[1:5] == 5'b10101) & re0_thr1; + assign fread0_thr1[22] = (ra0_thr1[1:5] == 5'b10110) & re0_thr1; + assign fread0_thr1[23] = (ra0_thr1[1:5] == 5'b10111) & re0_thr1; + + + + assign fread1_thr1[00] = (ra1_thr1[1:5] == 5'b00000) & re1_thr1; + assign fread1_thr1[01] = (ra1_thr1[1:5] == 5'b00001) & re1_thr1; + assign fread1_thr1[02] = (ra1_thr1[1:5] == 5'b00010) & re1_thr1; + assign fread1_thr1[03] = (ra1_thr1[1:5] == 5'b00011) & re1_thr1; + assign fread1_thr1[04] = (ra1_thr1[1:5] == 5'b00100) & re1_thr1; + assign fread1_thr1[05] = (ra1_thr1[1:5] == 5'b00101) & re1_thr1; + assign fread1_thr1[06] = (ra1_thr1[1:5] == 5'b00110) & re1_thr1; + assign fread1_thr1[07] = (ra1_thr1[1:5] == 5'b00111) & re1_thr1; + assign fread1_thr1[08] = (ra1_thr1[1:5] == 5'b01000) & re1_thr1; + assign fread1_thr1[09] = (ra1_thr1[1:5] == 5'b01001) & re1_thr1; + assign fread1_thr1[10] = (ra1_thr1[1:5] == 5'b01010) & re1_thr1; + assign fread1_thr1[11] = (ra1_thr1[1:5] == 5'b01011) & re1_thr1; + assign fread1_thr1[12] = (ra1_thr1[1:5] == 5'b01100) & re1_thr1; + assign fread1_thr1[13] = (ra1_thr1[1:5] == 5'b01101) & re1_thr1; + assign fread1_thr1[14] = (ra1_thr1[1:5] == 5'b01110) & re1_thr1; + assign fread1_thr1[15] = (ra1_thr1[1:5] == 5'b01111) & re1_thr1; + assign fread1_thr1[16] = (ra1_thr1[1:5] == 5'b10000) & re1_thr1; + assign fread1_thr1[17] = (ra1_thr1[1:5] == 5'b10001) & re1_thr1; + assign fread1_thr1[18] = (ra1_thr1[1:5] == 5'b10010) & re1_thr1; + assign fread1_thr1[19] = (ra1_thr1[1:5] == 5'b10011) & re1_thr1; + assign fread1_thr1[20] = (ra1_thr1[1:5] == 5'b10100) & re1_thr1; + assign fread1_thr1[21] = (ra1_thr1[1:5] == 5'b10101) & re1_thr1; + assign fread1_thr1[22] = (ra1_thr1[1:5] == 5'b10110) & re1_thr1; + assign fread1_thr1[23] = (ra1_thr1[1:5] == 5'b10111) & re1_thr1; + + + begin : xhdl3 + // genvar i; + for (i = 0; i <= 23; i = i + 1) + begin : writeport_hfpscr_thr1 + assign hfpscr_thr1_din[24 * i:(24 * i) + 23] = ((hfpscr_thr1_q[24 * i:(24 * i) + 23] & {24{fwrite_thr1_b[i]}}) | + (di0 & {24{fwrite_thr1[i]}})); + end + end + + + tri_rlmreg_p #(.WIDTH(576 + 64)) hfpscr_thr1_lat( + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[7]), + .mpw1_b(mpw1_b[7]), + .mpw2_b(mpw2_b[1]), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(thold_0_b), + .sg(sg_0), + .scout(hfpscr_thr1_so), + .scin(hfpscr_thr1_si), + //----------------- + .din({ hfpscr_thr1_din, + fread0_thr1, + fread1_thr1 + }), + + //----------------- + .dout({ hfpscr_thr1_q, + fread0_thr1_q, + fread1_thr1_q }) + ); + + assign hfpscr_thr1_si[0:639] = {hfpscr_thr1_so[1:639], hfpscr_thr1_so[0]};// todo + + + + + + assign do0_thr1 = ((hfpscr_thr1_q[24 * 00:(24 * 00) + 23] & {24{fread0_thr1_q[00]}}) | + (hfpscr_thr1_q[24 * 01:(24 * 01) + 23] & {24{fread0_thr1_q[01]}}) | + (hfpscr_thr1_q[24 * 02:(24 * 02) + 23] & {24{fread0_thr1_q[02]}}) | + (hfpscr_thr1_q[24 * 03:(24 * 03) + 23] & {24{fread0_thr1_q[03]}}) | + (hfpscr_thr1_q[24 * 04:(24 * 04) + 23] & {24{fread0_thr1_q[04]}}) | + (hfpscr_thr1_q[24 * 05:(24 * 05) + 23] & {24{fread0_thr1_q[05]}}) | + (hfpscr_thr1_q[24 * 06:(24 * 06) + 23] & {24{fread0_thr1_q[06]}}) | + (hfpscr_thr1_q[24 * 07:(24 * 07) + 23] & {24{fread0_thr1_q[07]}}) | + (hfpscr_thr1_q[24 * 08:(24 * 08) + 23] & {24{fread0_thr1_q[08]}}) | + (hfpscr_thr1_q[24 * 09:(24 * 09) + 23] & {24{fread0_thr1_q[09]}}) | + (hfpscr_thr1_q[24 * 10:(24 * 10) + 23] & {24{fread0_thr1_q[10]}}) | + (hfpscr_thr1_q[24 * 11:(24 * 11) + 23] & {24{fread0_thr1_q[11]}}) | + (hfpscr_thr1_q[24 * 12:(24 * 12) + 23] & {24{fread0_thr1_q[12]}}) | + (hfpscr_thr1_q[24 * 13:(24 * 13) + 23] & {24{fread0_thr1_q[13]}}) | + (hfpscr_thr1_q[24 * 14:(24 * 14) + 23] & {24{fread0_thr1_q[14]}}) | + (hfpscr_thr1_q[24 * 15:(24 * 15) + 23] & {24{fread0_thr1_q[15]}}) | + (hfpscr_thr1_q[24 * 16:(24 * 16) + 23] & {24{fread0_thr1_q[16]}}) | + (hfpscr_thr1_q[24 * 17:(24 * 17) + 23] & {24{fread0_thr1_q[17]}}) | + (hfpscr_thr1_q[24 * 18:(24 * 18) + 23] & {24{fread0_thr1_q[18]}}) | + (hfpscr_thr1_q[24 * 19:(24 * 19) + 23] & {24{fread0_thr1_q[19]}}) | + (hfpscr_thr1_q[24 * 20:(24 * 20) + 23] & {24{fread0_thr1_q[20]}}) | + (hfpscr_thr1_q[24 * 21:(24 * 21) + 23] & {24{fread0_thr1_q[21]}}) | + (hfpscr_thr1_q[24 * 22:(24 * 22) + 23] & {24{fread0_thr1_q[22]}}) | + (hfpscr_thr1_q[24 * 23:(24 * 23) + 23] & {24{fread0_thr1_q[23]}})); + + + + + assign do1_thr1 = ((hfpscr_thr1_q[24 * 00:(24 * 00) + 23] & {24{fread1_thr1_q[00]}}) | + (hfpscr_thr1_q[24 * 01:(24 * 01) + 23] & {24{fread1_thr1_q[01]}}) | + (hfpscr_thr1_q[24 * 02:(24 * 02) + 23] & {24{fread1_thr1_q[02]}}) | + (hfpscr_thr1_q[24 * 03:(24 * 03) + 23] & {24{fread1_thr1_q[03]}}) | + (hfpscr_thr1_q[24 * 04:(24 * 04) + 23] & {24{fread1_thr1_q[04]}}) | + (hfpscr_thr1_q[24 * 05:(24 * 05) + 23] & {24{fread1_thr1_q[05]}}) | + (hfpscr_thr1_q[24 * 06:(24 * 06) + 23] & {24{fread1_thr1_q[06]}}) | + (hfpscr_thr1_q[24 * 07:(24 * 07) + 23] & {24{fread1_thr1_q[07]}}) | + (hfpscr_thr1_q[24 * 08:(24 * 08) + 23] & {24{fread1_thr1_q[08]}}) | + (hfpscr_thr1_q[24 * 09:(24 * 09) + 23] & {24{fread1_thr1_q[09]}}) | + (hfpscr_thr1_q[24 * 10:(24 * 10) + 23] & {24{fread1_thr1_q[10]}}) | + (hfpscr_thr1_q[24 * 11:(24 * 11) + 23] & {24{fread1_thr1_q[11]}}) | + (hfpscr_thr1_q[24 * 12:(24 * 12) + 23] & {24{fread1_thr1_q[12]}}) | + (hfpscr_thr1_q[24 * 13:(24 * 13) + 23] & {24{fread1_thr1_q[13]}}) | + (hfpscr_thr1_q[24 * 14:(24 * 14) + 23] & {24{fread1_thr1_q[14]}}) | + (hfpscr_thr1_q[24 * 15:(24 * 15) + 23] & {24{fread1_thr1_q[15]}}) | + (hfpscr_thr1_q[24 * 16:(24 * 16) + 23] & {24{fread1_thr1_q[16]}}) | + (hfpscr_thr1_q[24 * 17:(24 * 17) + 23] & {24{fread1_thr1_q[17]}}) | + (hfpscr_thr1_q[24 * 18:(24 * 18) + 23] & {24{fread1_thr1_q[18]}}) | + (hfpscr_thr1_q[24 * 19:(24 * 19) + 23] & {24{fread1_thr1_q[19]}}) | + (hfpscr_thr1_q[24 * 20:(24 * 20) + 23] & {24{fread1_thr1_q[20]}}) | + (hfpscr_thr1_q[24 * 21:(24 * 21) + 23] & {24{fread1_thr1_q[21]}}) | + (hfpscr_thr1_q[24 * 22:(24 * 22) + 23] & {24{fread1_thr1_q[22]}}) | + (hfpscr_thr1_q[24 * 23:(24 * 23) + 23] & {24{fread1_thr1_q[23]}})); + + + end + endgenerate + + assign cfpscr_upd_i0_thr0 = do0_thr0[2] & upd_i0_thr0; + assign upd_i0_fprf_hold_thr0 = do0_thr0[1] & upd_i0_thr0; + assign upd_i0_compare_thr0 = do0_thr0[0] & upd_i0_thr0; + + assign cfpscr_upd_i1_thr0 = do1_thr0[2] & upd_i1_thr0; + assign upd_i1_fprf_hold_thr0 = do1_thr0[1] & upd_i1_thr0; + assign upd_i1_compare_thr0 = do1_thr0[0] & upd_i1_thr0; + + assign cfpscr_upd_i0_thr1 = do0_thr1[2] & upd_i0_thr1; + assign upd_i0_fprf_hold_thr1 = do0_thr1[1] & upd_i0_thr1; + assign upd_i0_compare_thr1 = do0_thr1[0] & upd_i0_thr1; + + assign cfpscr_upd_i1_thr1 = do1_thr1[2] & upd_i1_thr1; + assign upd_i1_fprf_hold_thr1 = do1_thr1[1] & upd_i1_thr1; + assign upd_i1_compare_thr1 = do1_thr1[0] & upd_i1_thr1; + + assign cfpscr_upd_pipe_thr0 = cfpscr_upd_i0_thr0 | cfpscr_upd_i1_thr0; + assign cfpscr_upd_pipe_thr1 = cfpscr_upd_i0_thr1 | cfpscr_upd_i1_thr1; + + assign upd_i0_fpscr_thr0[35:55] = do0_thr0[3:23] & {21{cfpscr_upd_i0_thr0}}; + assign upd_i1_fpscr_thr0[35:55] = do1_thr0[3:23] & {21{cfpscr_upd_i1_thr0}}; + assign upd_i0_fpscr_thr1[35:55] = do0_thr1[3:23] & {21{cfpscr_upd_i0_thr1}}; + assign upd_i1_fpscr_thr1[35:55] = do1_thr1[3:23] & {21{cfpscr_upd_i1_thr1}}; + + // Move Operations + assign cfpscr_upd_move = 1'b0; + assign cfpscr_move[28:63] = {36{1'b0}}; + assign cfpscr_mtfsf = 1'b0; + assign cfpscr_mtfsfi = 1'b0; + //------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + // Pipe Operations + assign cfpscr_pipe_thr0[32] = cfpscr_thr0_l2[32]; // check 0->1 excp after selection for move/pipe + assign cfpscr_pipe_thr0[33] = tidn; //// unused (from other bits after move/pipe selection) + assign cfpscr_pipe_thr0[34] = tidn; //// unused (from other bits after move/pipe selection) + assign cfpscr_pipe_thr0[35] = cfpscr_thr0_l2[35] | upd_i0_fpscr_thr0[35] | upd_i1_fpscr_thr0[35]; //ox STICKY + assign cfpscr_pipe_thr0[36] = cfpscr_thr0_l2[36] | upd_i0_fpscr_thr0[36] | upd_i1_fpscr_thr0[36]; //ux STICKY + assign cfpscr_pipe_thr0[37] = cfpscr_thr0_l2[37] | upd_i0_fpscr_thr0[37] | upd_i1_fpscr_thr0[37]; //zx sticky + assign cfpscr_pipe_thr0[38] = cfpscr_thr0_l2[38] | upd_i0_fpscr_thr0[38] | upd_i1_fpscr_thr0[38]; //xx sticky version of fi + + assign cfpscr_pipe_thr0[39] = cfpscr_thr0_l2[39] | upd_i0_fpscr_thr0[39] | upd_i1_fpscr_thr0[39]; //ex7_flag_vxsnan ; --sticky + assign cfpscr_pipe_thr0[40] = cfpscr_thr0_l2[40] | upd_i0_fpscr_thr0[40] | upd_i1_fpscr_thr0[40]; //ex7_flag_vxisi ; --sticky + assign cfpscr_pipe_thr0[41] = cfpscr_thr0_l2[41] | upd_i0_fpscr_thr0[41] | upd_i1_fpscr_thr0[41]; //ex7_flag_vxidi ; --sticky + assign cfpscr_pipe_thr0[42] = cfpscr_thr0_l2[42] | upd_i0_fpscr_thr0[42] | upd_i1_fpscr_thr0[42]; //ex7_flag_vxzdz ; --sticky + assign cfpscr_pipe_thr0[43] = cfpscr_thr0_l2[43] | upd_i0_fpscr_thr0[43] | upd_i1_fpscr_thr0[43]; //ex7_flag_vximz ; --sticky + assign cfpscr_pipe_thr0[44] = cfpscr_thr0_l2[44] | upd_i0_fpscr_thr0[44] | upd_i1_fpscr_thr0[44]; //ex7_flag_vxvc ; --sticky + + //fr NOT sticky + //no update if 1 compare + //no update if 1 compare + assign cfpscr_pipe_thr0[45] = (upd_i0_fpscr_thr0[45] & (~cfpscr_upd_i1_thr0)) | upd_i1_fpscr_thr0[45] | (cfpscr_thr0_l2[45] & (upd_i0_compare_thr0 & (~upd_i1_thr0))) | (cfpscr_thr0_l2[45] & (upd_i1_compare_thr0 & (~upd_i0_thr0))) | (cfpscr_thr0_l2[45] & (upd_i0_compare_thr0 & upd_i1_compare_thr0)) | (upd_i0_fpscr_thr0[45] & ((~upd_i0_compare_thr0) & upd_i0_thr0 & upd_i1_compare_thr0)); //no update if both compares + //i0 if i1 compare + + assign cfpscr_pipe_thr0[46] = (upd_i0_fpscr_thr0[46] & (~cfpscr_upd_i1_thr0)) | upd_i1_fpscr_thr0[46] | (cfpscr_thr0_l2[46] & (upd_i0_compare_thr0 & (~upd_i1_thr0))) | (cfpscr_thr0_l2[46] & (upd_i1_compare_thr0 & (~upd_i0_thr0))) | (cfpscr_thr0_l2[46] & (upd_i0_compare_thr0 & upd_i1_compare_thr0)) | (upd_i0_fpscr_thr0[46] & ((~upd_i0_compare_thr0) & upd_i0_thr0 & upd_i1_compare_thr0)); //fi NOT sticky + + assign upd_i0_fprf_hold_47_thr0 = upd_i0_compare_thr0 | upd_i0_fprf_hold_thr0; + assign upd_i1_fprf_hold_47_thr0 = upd_i1_compare_thr0 | upd_i1_fprf_hold_thr0; + + assign cfpscr_pipe_thr0[47] = (upd_i0_fpscr_thr0[47] & (~cfpscr_upd_i1_thr0)) | upd_i1_fpscr_thr0[47] | (cfpscr_thr0_l2[47] & (upd_i0_fprf_hold_47_thr0 & (~upd_i1_thr0))) | (cfpscr_thr0_l2[47] & (upd_i1_fprf_hold_47_thr0 & (~upd_i0_thr0))) | (cfpscr_thr0_l2[47] & (upd_i0_fprf_hold_47_thr0 & upd_i1_fprf_hold_47_thr0)) | (upd_i0_fpscr_thr0[47] & ((~upd_i0_fprf_hold_47_thr0) & upd_i0_thr0 & upd_i1_fprf_hold_47_thr0)); //FPRF C NOT sticky + + assign cfpscr_pipe_thr0[48] = (upd_i0_fpscr_thr0[48] & (~cfpscr_upd_i1_thr0)) | upd_i1_fpscr_thr0[48] | (cfpscr_thr0_l2[48] & (upd_i0_fprf_hold_thr0 & (~upd_i1_thr0))) | (cfpscr_thr0_l2[48] & (upd_i1_fprf_hold_thr0 & (~upd_i0_thr0))) | (cfpscr_thr0_l2[48] & (upd_i0_fprf_hold_thr0 & upd_i1_fprf_hold_thr0)) | (upd_i0_fpscr_thr0[48] & ((~upd_i0_fprf_hold_thr0) & upd_i0_thr0 & upd_i1_fprf_hold_thr0)); //FPRF fpdd(lt) + + assign cfpscr_pipe_thr0[49] = (upd_i0_fpscr_thr0[49] & (~cfpscr_upd_i1_thr0)) | upd_i1_fpscr_thr0[49] | (cfpscr_thr0_l2[49] & (upd_i0_fprf_hold_thr0 & (~upd_i1_thr0))) | (cfpscr_thr0_l2[49] & (upd_i1_fprf_hold_thr0 & (~upd_i0_thr0))) | (cfpscr_thr0_l2[49] & (upd_i0_fprf_hold_thr0 & upd_i1_fprf_hold_thr0)) | (upd_i0_fpscr_thr0[49] & ((~upd_i0_fprf_hold_thr0) & upd_i0_thr0 & upd_i1_fprf_hold_thr0)); //FPRF fpdd(gt) + + assign cfpscr_pipe_thr0[50] = (upd_i0_fpscr_thr0[50] & (~cfpscr_upd_i1_thr0)) | upd_i1_fpscr_thr0[50] | (cfpscr_thr0_l2[50] & (upd_i0_fprf_hold_thr0 & (~upd_i1_thr0))) | (cfpscr_thr0_l2[50] & (upd_i1_fprf_hold_thr0 & (~upd_i0_thr0))) | (cfpscr_thr0_l2[50] & (upd_i0_fprf_hold_thr0 & upd_i1_fprf_hold_thr0)) | (upd_i0_fpscr_thr0[50] & ((~upd_i0_fprf_hold_thr0) & upd_i0_thr0 & upd_i1_fprf_hold_thr0)); //FPRF fpdd(eq) + + assign cfpscr_pipe_thr0[51] = (upd_i0_fpscr_thr0[51] & (~cfpscr_upd_i1_thr0)) | upd_i1_fpscr_thr0[51] | (cfpscr_thr0_l2[51] & (upd_i0_fprf_hold_thr0 & (~upd_i1_thr0))) | (cfpscr_thr0_l2[51] & (upd_i1_fprf_hold_thr0 & (~upd_i0_thr0))) | (cfpscr_thr0_l2[51] & (upd_i0_fprf_hold_thr0 & upd_i1_fprf_hold_thr0)) | (upd_i0_fpscr_thr0[51] & ((~upd_i0_fprf_hold_thr0) & upd_i0_thr0 & upd_i1_fprf_hold_thr0)); //FPRF fpdd(nan) + + assign cfpscr_pipe_thr0[52] = tidn; //reserved + assign cfpscr_pipe_thr0[53] = cfpscr_thr0_l2[53]; //VXSOFT sticky + assign cfpscr_pipe_thr0[54] = cfpscr_thr0_l2[54] | upd_i0_fpscr_thr0[54] | upd_i1_fpscr_thr0[54]; //VXSQRT sticky + assign cfpscr_pipe_thr0[55] = cfpscr_thr0_l2[55] | upd_i0_fpscr_thr0[55] | upd_i1_fpscr_thr0[55]; //VXCVI sticky + + //cfpscr_din(28 to 31) <= cfpscr_pipe_thr0(28 to 31) ; + assign cfpscr_thr0_din[28] = (ex7_fpscr_move_dfp[0] & ex7_upd_move_thr0) | (cfpscr_thr0_l2[28] & (~ex7_upd_move_thr0)); + assign cfpscr_thr0_din[29] = (ex7_fpscr_move_dfp[1] & ex7_upd_move_thr0) | (cfpscr_thr0_l2[29] & (~ex7_upd_move_thr0)); + assign cfpscr_thr0_din[30] = (ex7_fpscr_move_dfp[2] & ex7_upd_move_thr0) | (cfpscr_thr0_l2[30] & (~ex7_upd_move_thr0)); + assign cfpscr_thr0_din[31] = (ex7_fpscr_move_dfp[3] & ex7_upd_move_thr0) | (cfpscr_thr0_l2[31] & (~ex7_upd_move_thr0)); + + // Control Bits + assign cfpscr_pipe_thr0[56:63] = cfpscr_thr0_l2[56:63]; + + assign cfpscr_thr0_din[63] = (ex7_fpscr_move[31] & ex7_upd_move_thr0) | (cfpscr_thr0_l2[63] & (~ex7_upd_move_thr0)); + assign cfpscr_thr0_din[62] = (ex7_fpscr_move[30] & ex7_upd_move_thr0) | (cfpscr_thr0_l2[62] & (~ex7_upd_move_thr0)); + assign cfpscr_thr0_din[61] = (ex7_fpscr_move[29] & ex7_upd_move_thr0) | (cfpscr_thr0_l2[61] & (~ex7_upd_move_thr0)); + assign cfpscr_thr0_din[60] = (ex7_fpscr_move[28] & ex7_upd_move_thr0) | (cfpscr_thr0_l2[60] & (~ex7_upd_move_thr0)); + assign cfpscr_thr0_din[59] = (ex7_fpscr_move[27] & ex7_upd_move_thr0) | (cfpscr_thr0_l2[59] & (~ex7_upd_move_thr0)); + assign cfpscr_thr0_din[58] = (ex7_fpscr_move[26] & ex7_upd_move_thr0) | (cfpscr_thr0_l2[58] & (~ex7_upd_move_thr0)); + assign cfpscr_thr0_din[57] = (ex7_fpscr_move[25] & ex7_upd_move_thr0) | (cfpscr_thr0_l2[57] & (~ex7_upd_move_thr0)); + assign cfpscr_thr0_din[56] = (ex7_fpscr_move[24] & ex7_upd_move_thr0) | (cfpscr_thr0_l2[56] & (~ex7_upd_move_thr0)); + + assign cfpscr_thr0_din[55] = (ex7_fpscr_move[23] & ex7_upd_move_thr0) | (cfpscr_pipe_thr0[55] & cfpscr_upd_pipe_thr0) | (cfpscr_thr0_l2[55] & (~(ex7_upd_move_thr0 | cfpscr_upd_pipe_thr0))); + assign cfpscr_thr0_din[54] = (ex7_fpscr_move[22] & ex7_upd_move_thr0) | (cfpscr_pipe_thr0[54] & cfpscr_upd_pipe_thr0) | (cfpscr_thr0_l2[54] & (~(ex7_upd_move_thr0 | cfpscr_upd_pipe_thr0))); + assign cfpscr_thr0_din[53] = (ex7_fpscr_move[21] & ex7_upd_move_thr0) | (cfpscr_pipe_thr0[53] & cfpscr_upd_pipe_thr0) | (cfpscr_thr0_l2[53] & (~(ex7_upd_move_thr0 | cfpscr_upd_pipe_thr0))); + assign cfpscr_thr0_din[52] = tidn; // reserved + assign cfpscr_thr0_din[51] = (ex7_fpscr_move[19] & ex7_upd_move_thr0) | (cfpscr_pipe_thr0[51] & cfpscr_upd_pipe_thr0) | (cfpscr_thr0_l2[51] & (~(ex7_upd_move_thr0 | cfpscr_upd_pipe_thr0))); + assign cfpscr_thr0_din[50] = (ex7_fpscr_move[18] & ex7_upd_move_thr0) | (cfpscr_pipe_thr0[50] & cfpscr_upd_pipe_thr0) | (cfpscr_thr0_l2[50] & (~(ex7_upd_move_thr0 | cfpscr_upd_pipe_thr0))); + assign cfpscr_thr0_din[49] = (ex7_fpscr_move[17] & ex7_upd_move_thr0) | (cfpscr_pipe_thr0[49] & cfpscr_upd_pipe_thr0) | (cfpscr_thr0_l2[49] & (~(ex7_upd_move_thr0 | cfpscr_upd_pipe_thr0))); + assign cfpscr_thr0_din[48] = (ex7_fpscr_move[16] & ex7_upd_move_thr0) | (cfpscr_pipe_thr0[48] & cfpscr_upd_pipe_thr0) | (cfpscr_thr0_l2[48] & (~(ex7_upd_move_thr0 | cfpscr_upd_pipe_thr0))); + assign cfpscr_thr0_din[47] = (ex7_fpscr_move[15] & ex7_upd_move_thr0) | (cfpscr_pipe_thr0[47] & cfpscr_upd_pipe_thr0) | (cfpscr_thr0_l2[47] & (~(ex7_upd_move_thr0 | cfpscr_upd_pipe_thr0))); + assign cfpscr_thr0_din[46] = (ex7_fpscr_move[14] & ex7_upd_move_thr0) | (cfpscr_pipe_thr0[46] & cfpscr_upd_pipe_thr0) | (cfpscr_thr0_l2[46] & (~(ex7_upd_move_thr0 | cfpscr_upd_pipe_thr0))); + assign cfpscr_thr0_din[45] = (ex7_fpscr_move[13] & ex7_upd_move_thr0) | (cfpscr_pipe_thr0[45] & cfpscr_upd_pipe_thr0) | (cfpscr_thr0_l2[45] & (~(ex7_upd_move_thr0 | cfpscr_upd_pipe_thr0))); + assign cfpscr_thr0_din[44] = (ex7_fpscr_move[12] & ex7_upd_move_thr0) | (cfpscr_pipe_thr0[44] & cfpscr_upd_pipe_thr0) | (cfpscr_thr0_l2[44] & (~(ex7_upd_move_thr0 | cfpscr_upd_pipe_thr0))); + assign cfpscr_thr0_din[43] = (ex7_fpscr_move[11] & ex7_upd_move_thr0) | (cfpscr_pipe_thr0[43] & cfpscr_upd_pipe_thr0) | (cfpscr_thr0_l2[43] & (~(ex7_upd_move_thr0 | cfpscr_upd_pipe_thr0))); + assign cfpscr_thr0_din[42] = (ex7_fpscr_move[10] & ex7_upd_move_thr0) | (cfpscr_pipe_thr0[42] & cfpscr_upd_pipe_thr0) | (cfpscr_thr0_l2[42] & (~(ex7_upd_move_thr0 | cfpscr_upd_pipe_thr0))); + assign cfpscr_thr0_din[41] = (ex7_fpscr_move[9] & ex7_upd_move_thr0) | (cfpscr_pipe_thr0[41] & cfpscr_upd_pipe_thr0) | (cfpscr_thr0_l2[41] & (~(ex7_upd_move_thr0 | cfpscr_upd_pipe_thr0))); + assign cfpscr_thr0_din[40] = (ex7_fpscr_move[8] & ex7_upd_move_thr0) | (cfpscr_pipe_thr0[40] & cfpscr_upd_pipe_thr0) | (cfpscr_thr0_l2[40] & (~(ex7_upd_move_thr0 | cfpscr_upd_pipe_thr0))); + assign cfpscr_thr0_din[39] = (ex7_fpscr_move[7] & ex7_upd_move_thr0) | (cfpscr_pipe_thr0[39] & cfpscr_upd_pipe_thr0) | (cfpscr_thr0_l2[39] & (~(ex7_upd_move_thr0 | cfpscr_upd_pipe_thr0))); + assign cfpscr_thr0_din[38] = (ex7_fpscr_move[6] & ex7_upd_move_thr0) | (cfpscr_pipe_thr0[38] & cfpscr_upd_pipe_thr0) | (cfpscr_thr0_l2[38] & (~(ex7_upd_move_thr0 | cfpscr_upd_pipe_thr0))); + assign cfpscr_thr0_din[37] = (ex7_fpscr_move[5] & ex7_upd_move_thr0) | (cfpscr_pipe_thr0[37] & cfpscr_upd_pipe_thr0) | (cfpscr_thr0_l2[37] & (~(ex7_upd_move_thr0 | cfpscr_upd_pipe_thr0))); + assign cfpscr_thr0_din[36] = (ex7_fpscr_move[4] & ex7_upd_move_thr0) | (cfpscr_pipe_thr0[36] & cfpscr_upd_pipe_thr0) | (cfpscr_thr0_l2[36] & (~(ex7_upd_move_thr0 | cfpscr_upd_pipe_thr0))); + assign cfpscr_thr0_din[35] = (ex7_fpscr_move[3] & ex7_upd_move_thr0) | (cfpscr_pipe_thr0[35] & cfpscr_upd_pipe_thr0) | (cfpscr_thr0_l2[35] & (~(ex7_upd_move_thr0 | cfpscr_upd_pipe_thr0))); + + // or all invalid operation exceptions + // vxsnan + // vxisi + // vxidi + // vxzdz + // vximx + // vxvc + // vxzdz + assign cfpscr_thr0_din[34] = cfpscr_thr0_din[39] | cfpscr_thr0_din[40] | cfpscr_thr0_din[41] | cfpscr_thr0_din[42] | cfpscr_thr0_din[43] | cfpscr_thr0_din[44] | cfpscr_thr0_din[53] | cfpscr_thr0_din[54] | cfpscr_thr0_din[55]; // vximx + // vxvc + + // masked or of all exception bits + // vx* / ve + // ox / oe + // ux / ue + assign cfpscr_thr0_din[33] = (cfpscr_thr0_din[34] & cfpscr_thr0_din[56]) | (cfpscr_thr0_din[35] & cfpscr_thr0_din[57]) | (cfpscr_thr0_din[36] & cfpscr_thr0_din[58]) | (cfpscr_thr0_din[37] & cfpscr_thr0_din[59]) | (cfpscr_thr0_din[38] & cfpscr_thr0_din[60]); // zx / ze + // xx / xe + + assign cfpscr_thr0_din[32] = (ex7_fpscr_move[0] & ex7_upd_move_thr0) | (cfpscr_pipe_thr0[32] & (~ex7_upd_move_thr0)) | (cfpscr_new_excp_thr0 & (~(((ex7_mtfsf | ex7_mtfsfi) & ex7_thread[0]) & (~f_dcd_ex7_cancel)))); //upd_pipe and hold sticky + + // only check the exception bits + // ox + // ux + // zx + // xx + // vxsnan + // vxisi + // vxidi + // vxzdz + // vximx + // vxvc + // vxzdz + assign cfpscr_new_excp_thr0 = ((~cfpscr_thr0_l2[35]) & cfpscr_thr0_din[35]) | ((~cfpscr_thr0_l2[36]) & cfpscr_thr0_din[36]) | ((~cfpscr_thr0_l2[37]) & cfpscr_thr0_din[37]) | ((~cfpscr_thr0_l2[38]) & cfpscr_thr0_din[38]) | ((~cfpscr_thr0_l2[39]) & cfpscr_thr0_din[39]) | ((~cfpscr_thr0_l2[40]) & cfpscr_thr0_din[40]) | ((~cfpscr_thr0_l2[41]) & cfpscr_thr0_din[41]) | ((~cfpscr_thr0_l2[42]) & cfpscr_thr0_din[42]) | ((~cfpscr_thr0_l2[43]) & cfpscr_thr0_din[43]) | ((~cfpscr_thr0_l2[44]) & cfpscr_thr0_din[44]) | ((~cfpscr_thr0_l2[53]) & cfpscr_thr0_din[53]) | ((~cfpscr_thr0_l2[54]) & cfpscr_thr0_din[54]) | ((~cfpscr_thr0_l2[55]) & cfpscr_thr0_din[55]); // vximx + // vxvc + + //--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + //-FOR RTX only: ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + + assign ex7_inv_fpscr_bit = (ex7_nib_mask[0] & ~( |(ex7_nib_mask[1:3]))) & + ((~(ex7_bit_mask[0]) & ex7_bit_mask[1] & ~(ex7_bit_mask[2]) & ~(ex7_bit_mask[3])) | + (~(ex7_bit_mask[0]) & ~(ex7_bit_mask[1]) & ex7_bit_mask[2] & ~(ex7_bit_mask[3]))); + + + assign cfpscr_i0_wr_thr0 = cfpscr_upd_i0_thr0 | (ex7_upd_move_thr0 & ~(ex7_inv_fpscr_bit)); // don't do the write if BT is 1 or 2 (FPSCR 33 or 34) + assign cfpscr_i1_wr_thr0 = cfpscr_upd_i1_thr0; + assign cfpscr_i0i1_wr_thr0 = cfpscr_i0_wr_thr0 & cfpscr_i1_wr_thr0; + + assign cfpscr_i0_wr_thr1 = cfpscr_upd_i0_thr1 | (ex7_upd_move_thr1 & ~(ex7_inv_fpscr_bit)); + assign cfpscr_i1_wr_thr1 = cfpscr_upd_i1_thr1; + assign cfpscr_i0i1_wr_thr1 = cfpscr_i0_wr_thr1 & cfpscr_i1_wr_thr1; + + + //--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + //-FOR RTX only: Thread 0 i0 completion only ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + assign cfpscr_pipe_thr0_i0[32] = cfpscr_thr0_l2[32]; // check 0->1 excp after selection for move/pipe + assign cfpscr_pipe_thr0_i0[33] = tidn; //// unused (from other bits after move/pipe selection) + assign cfpscr_pipe_thr0_i0[34] = tidn; //// unused (from other bits after move/pipe selection) + assign cfpscr_pipe_thr0_i0[35] = cfpscr_thr0_l2[35] | upd_i0_fpscr_thr0[35] ; //ox STICKY + assign cfpscr_pipe_thr0_i0[36] = cfpscr_thr0_l2[36] | upd_i0_fpscr_thr0[36] ; //ux STICKY + assign cfpscr_pipe_thr0_i0[37] = cfpscr_thr0_l2[37] | upd_i0_fpscr_thr0[37] ; //zx sticky + assign cfpscr_pipe_thr0_i0[38] = cfpscr_thr0_l2[38] | upd_i0_fpscr_thr0[38] ; //xx sticky version of fi + + assign cfpscr_pipe_thr0_i0[39] = cfpscr_thr0_l2[39] | upd_i0_fpscr_thr0[39] ; //ex7_flag_vxsnan ; --sticky + assign cfpscr_pipe_thr0_i0[40] = cfpscr_thr0_l2[40] | upd_i0_fpscr_thr0[40] ; //ex7_flag_vxisi ; --sticky + assign cfpscr_pipe_thr0_i0[41] = cfpscr_thr0_l2[41] | upd_i0_fpscr_thr0[41] ; //ex7_flag_vxidi ; --sticky + assign cfpscr_pipe_thr0_i0[42] = cfpscr_thr0_l2[42] | upd_i0_fpscr_thr0[42] ; //ex7_flag_vxzdz ; --sticky + assign cfpscr_pipe_thr0_i0[43] = cfpscr_thr0_l2[43] | upd_i0_fpscr_thr0[43] ; //ex7_flag_vximz ; --sticky + assign cfpscr_pipe_thr0_i0[44] = cfpscr_thr0_l2[44] | upd_i0_fpscr_thr0[44] ; //ex7_flag_vxvc ; --sticky + + //fr NOT sticky + //no update if 1 compare + //no update if 1 compare + assign cfpscr_pipe_thr0_i0[45] = (upd_i0_fpscr_thr0[45]) | (cfpscr_thr0_l2[45] & (upd_i0_compare_thr0)) | (upd_i0_fpscr_thr0[45] & ((~upd_i0_compare_thr0) & upd_i0_thr0)); //no update if both compares + //i0 if i1 compare + + assign cfpscr_pipe_thr0_i0[46] = (upd_i0_fpscr_thr0[46]) | (cfpscr_thr0_l2[46] & (upd_i0_compare_thr0)) | (upd_i0_fpscr_thr0[46] & ((~upd_i0_compare_thr0) & upd_i0_thr0)); //fi NOT sticky + + assign cfpscr_pipe_thr0_i0[47] = (upd_i0_fpscr_thr0[47]) | (cfpscr_thr0_l2[47] & (upd_i0_fprf_hold_47_thr0 )) | (upd_i0_fpscr_thr0[47] & ((~upd_i0_fprf_hold_47_thr0) & upd_i0_thr0)); //FPRF C NOT sticky + + assign cfpscr_pipe_thr0_i0[48] = (upd_i0_fpscr_thr0[48]) | (cfpscr_thr0_l2[48] & (upd_i0_fprf_hold_thr0 )) | (upd_i0_fpscr_thr0[48] & ((~upd_i0_fprf_hold_thr0) & upd_i0_thr0)); //FPRF fpdd(lt) + + assign cfpscr_pipe_thr0_i0[49] = (upd_i0_fpscr_thr0[49]) | (cfpscr_thr0_l2[49] & (upd_i0_fprf_hold_thr0 )) | (upd_i0_fpscr_thr0[49] & ((~upd_i0_fprf_hold_thr0) & upd_i0_thr0)); //FPRF fpdd(gt) + + assign cfpscr_pipe_thr0_i0[50] = (upd_i0_fpscr_thr0[50]) | (cfpscr_thr0_l2[50] & (upd_i0_fprf_hold_thr0 )) | (upd_i0_fpscr_thr0[50] & ((~upd_i0_fprf_hold_thr0) & upd_i0_thr0)); //FPRF fpdd(eq) + + assign cfpscr_pipe_thr0_i0[51] = (upd_i0_fpscr_thr0[51]) | (cfpscr_thr0_l2[51] & (upd_i0_fprf_hold_thr0 )) | (upd_i0_fpscr_thr0[51] & ((~upd_i0_fprf_hold_thr0) & upd_i0_thr0)); //FPRF fpdd(nan) + + assign cfpscr_pipe_thr0_i0[52] = tidn; //reserved + assign cfpscr_pipe_thr0_i0[53] = cfpscr_thr0_l2[53]; //VXSOFT sticky + assign cfpscr_pipe_thr0_i0[54] = cfpscr_thr0_l2[54] | upd_i0_fpscr_thr0[54] ; //VXSQRT sticky + assign cfpscr_pipe_thr0_i0[55] = cfpscr_thr0_l2[55] | upd_i0_fpscr_thr0[55] ; //VXCVI sticky + + //cfpscr_din(28 to 31) <= cfpscr_pipe_thr0_i0(28 to 31) ; + assign cfpscr_thr0_din_i0[28] = (ex7_fpscr_move_dfp[0] & ex7_upd_move_thr0) | (cfpscr_thr0_l2[28] & (~ex7_upd_move_thr0)); + assign cfpscr_thr0_din_i0[29] = (ex7_fpscr_move_dfp[1] & ex7_upd_move_thr0) | (cfpscr_thr0_l2[29] & (~ex7_upd_move_thr0)); + assign cfpscr_thr0_din_i0[30] = (ex7_fpscr_move_dfp[2] & ex7_upd_move_thr0) | (cfpscr_thr0_l2[30] & (~ex7_upd_move_thr0)); + assign cfpscr_thr0_din_i0[31] = (ex7_fpscr_move_dfp[3] & ex7_upd_move_thr0) | (cfpscr_thr0_l2[31] & (~ex7_upd_move_thr0)); + + // Control Bits + assign cfpscr_pipe_thr0_i0[56:63] = cfpscr_thr0_l2[56:63]; + + assign cfpscr_thr0_din_i0[63] = (ex7_fpscr_move[31] & ex7_upd_move_thr0) | (cfpscr_thr0_l2[63] & (~ex7_upd_move_thr0)); + assign cfpscr_thr0_din_i0[62] = (ex7_fpscr_move[30] & ex7_upd_move_thr0) | (cfpscr_thr0_l2[62] & (~ex7_upd_move_thr0)); + assign cfpscr_thr0_din_i0[61] = (ex7_fpscr_move[29] & ex7_upd_move_thr0) | (cfpscr_thr0_l2[61] & (~ex7_upd_move_thr0)); + assign cfpscr_thr0_din_i0[60] = (ex7_fpscr_move[28] & ex7_upd_move_thr0) | (cfpscr_thr0_l2[60] & (~ex7_upd_move_thr0)); + assign cfpscr_thr0_din_i0[59] = (ex7_fpscr_move[27] & ex7_upd_move_thr0) | (cfpscr_thr0_l2[59] & (~ex7_upd_move_thr0)); + assign cfpscr_thr0_din_i0[58] = (ex7_fpscr_move[26] & ex7_upd_move_thr0) | (cfpscr_thr0_l2[58] & (~ex7_upd_move_thr0)); + assign cfpscr_thr0_din_i0[57] = (ex7_fpscr_move[25] & ex7_upd_move_thr0) | (cfpscr_thr0_l2[57] & (~ex7_upd_move_thr0)); + assign cfpscr_thr0_din_i0[56] = (ex7_fpscr_move[24] & ex7_upd_move_thr0) | (cfpscr_thr0_l2[56] & (~ex7_upd_move_thr0)); + + assign cfpscr_thr0_din_i0[55] = (ex7_fpscr_move[23] & ex7_upd_move_thr0) | (cfpscr_pipe_thr0_i0[55] & cfpscr_upd_i0_thr0) | (cfpscr_thr0_l2[55] & (~(ex7_upd_move_thr0 | cfpscr_upd_i0_thr0))); + assign cfpscr_thr0_din_i0[54] = (ex7_fpscr_move[22] & ex7_upd_move_thr0) | (cfpscr_pipe_thr0_i0[54] & cfpscr_upd_i0_thr0) | (cfpscr_thr0_l2[54] & (~(ex7_upd_move_thr0 | cfpscr_upd_i0_thr0))); + assign cfpscr_thr0_din_i0[53] = (ex7_fpscr_move[21] & ex7_upd_move_thr0) | (cfpscr_pipe_thr0_i0[53] & cfpscr_upd_i0_thr0) | (cfpscr_thr0_l2[53] & (~(ex7_upd_move_thr0 | cfpscr_upd_i0_thr0))); + assign cfpscr_thr0_din_i0[52] = tidn; // reserved + assign cfpscr_thr0_din_i0[51] = (ex7_fpscr_move[19] & ex7_upd_move_thr0) | (cfpscr_pipe_thr0_i0[51] & cfpscr_upd_i0_thr0) | (cfpscr_thr0_l2[51] & (~(ex7_upd_move_thr0 | cfpscr_upd_i0_thr0))); + assign cfpscr_thr0_din_i0[50] = (ex7_fpscr_move[18] & ex7_upd_move_thr0) | (cfpscr_pipe_thr0_i0[50] & cfpscr_upd_i0_thr0) | (cfpscr_thr0_l2[50] & (~(ex7_upd_move_thr0 | cfpscr_upd_i0_thr0))); + assign cfpscr_thr0_din_i0[49] = (ex7_fpscr_move[17] & ex7_upd_move_thr0) | (cfpscr_pipe_thr0_i0[49] & cfpscr_upd_i0_thr0) | (cfpscr_thr0_l2[49] & (~(ex7_upd_move_thr0 | cfpscr_upd_i0_thr0))); + assign cfpscr_thr0_din_i0[48] = (ex7_fpscr_move[16] & ex7_upd_move_thr0) | (cfpscr_pipe_thr0_i0[48] & cfpscr_upd_i0_thr0) | (cfpscr_thr0_l2[48] & (~(ex7_upd_move_thr0 | cfpscr_upd_i0_thr0))); + assign cfpscr_thr0_din_i0[47] = (ex7_fpscr_move[15] & ex7_upd_move_thr0) | (cfpscr_pipe_thr0_i0[47] & cfpscr_upd_i0_thr0) | (cfpscr_thr0_l2[47] & (~(ex7_upd_move_thr0 | cfpscr_upd_i0_thr0))); + assign cfpscr_thr0_din_i0[46] = (ex7_fpscr_move[14] & ex7_upd_move_thr0) | (cfpscr_pipe_thr0_i0[46] & cfpscr_upd_i0_thr0) | (cfpscr_thr0_l2[46] & (~(ex7_upd_move_thr0 | cfpscr_upd_i0_thr0))); + assign cfpscr_thr0_din_i0[45] = (ex7_fpscr_move[13] & ex7_upd_move_thr0) | (cfpscr_pipe_thr0_i0[45] & cfpscr_upd_i0_thr0) | (cfpscr_thr0_l2[45] & (~(ex7_upd_move_thr0 | cfpscr_upd_i0_thr0))); + assign cfpscr_thr0_din_i0[44] = (ex7_fpscr_move[12] & ex7_upd_move_thr0) | (cfpscr_pipe_thr0_i0[44] & cfpscr_upd_i0_thr0) | (cfpscr_thr0_l2[44] & (~(ex7_upd_move_thr0 | cfpscr_upd_i0_thr0))); + assign cfpscr_thr0_din_i0[43] = (ex7_fpscr_move[11] & ex7_upd_move_thr0) | (cfpscr_pipe_thr0_i0[43] & cfpscr_upd_i0_thr0) | (cfpscr_thr0_l2[43] & (~(ex7_upd_move_thr0 | cfpscr_upd_i0_thr0))); + assign cfpscr_thr0_din_i0[42] = (ex7_fpscr_move[10] & ex7_upd_move_thr0) | (cfpscr_pipe_thr0_i0[42] & cfpscr_upd_i0_thr0) | (cfpscr_thr0_l2[42] & (~(ex7_upd_move_thr0 | cfpscr_upd_i0_thr0))); + assign cfpscr_thr0_din_i0[41] = (ex7_fpscr_move[9] & ex7_upd_move_thr0) | (cfpscr_pipe_thr0_i0[41] & cfpscr_upd_i0_thr0) | (cfpscr_thr0_l2[41] & (~(ex7_upd_move_thr0 | cfpscr_upd_i0_thr0))); + assign cfpscr_thr0_din_i0[40] = (ex7_fpscr_move[8] & ex7_upd_move_thr0) | (cfpscr_pipe_thr0_i0[40] & cfpscr_upd_i0_thr0) | (cfpscr_thr0_l2[40] & (~(ex7_upd_move_thr0 | cfpscr_upd_i0_thr0))); + assign cfpscr_thr0_din_i0[39] = (ex7_fpscr_move[7] & ex7_upd_move_thr0) | (cfpscr_pipe_thr0_i0[39] & cfpscr_upd_i0_thr0) | (cfpscr_thr0_l2[39] & (~(ex7_upd_move_thr0 | cfpscr_upd_i0_thr0))); + assign cfpscr_thr0_din_i0[38] = (ex7_fpscr_move[6] & ex7_upd_move_thr0) | (cfpscr_pipe_thr0_i0[38] & cfpscr_upd_i0_thr0) | (cfpscr_thr0_l2[38] & (~(ex7_upd_move_thr0 | cfpscr_upd_i0_thr0))); + assign cfpscr_thr0_din_i0[37] = (ex7_fpscr_move[5] & ex7_upd_move_thr0) | (cfpscr_pipe_thr0_i0[37] & cfpscr_upd_i0_thr0) | (cfpscr_thr0_l2[37] & (~(ex7_upd_move_thr0 | cfpscr_upd_i0_thr0))); + assign cfpscr_thr0_din_i0[36] = (ex7_fpscr_move[4] & ex7_upd_move_thr0) | (cfpscr_pipe_thr0_i0[36] & cfpscr_upd_i0_thr0) | (cfpscr_thr0_l2[36] & (~(ex7_upd_move_thr0 | cfpscr_upd_i0_thr0))); + assign cfpscr_thr0_din_i0[35] = (ex7_fpscr_move[3] & ex7_upd_move_thr0) | (cfpscr_pipe_thr0_i0[35] & cfpscr_upd_i0_thr0) | (cfpscr_thr0_l2[35] & (~(ex7_upd_move_thr0 | cfpscr_upd_i0_thr0))); + + assign cfpscr_thr0_din_i0[34] = cfpscr_thr0_din_i0[39] | cfpscr_thr0_din_i0[40] | cfpscr_thr0_din_i0[41] | cfpscr_thr0_din_i0[42] | cfpscr_thr0_din_i0[43] | cfpscr_thr0_din_i0[44] | cfpscr_thr0_din_i0[53] | cfpscr_thr0_din_i0[54] | cfpscr_thr0_din_i0[55]; // vximx + + assign cfpscr_thr0_din_i0[33] = (cfpscr_thr0_din_i0[34] & cfpscr_thr0_din_i0[56]) | (cfpscr_thr0_din_i0[35] & cfpscr_thr0_din_i0[57]) | (cfpscr_thr0_din_i0[36] & cfpscr_thr0_din_i0[58]) | (cfpscr_thr0_din_i0[37] & cfpscr_thr0_din_i0[59]) | (cfpscr_thr0_din_i0[38] & cfpscr_thr0_din_i0[60]); // zx / ze + + assign cfpscr_thr0_din_i0[32] = (ex7_fpscr_move[0] & ex7_upd_move_thr0) | (cfpscr_pipe_thr0_i0[32] & (~ex7_upd_move_thr0)) | (cfpscr_new_excp_thr0_i0 & (~(((ex7_mtfsf | ex7_mtfsfi) & ex7_thread[0]) & (~f_dcd_ex7_cancel)))); //upd_pipe and hold sticky + + assign cfpscr_new_excp_thr0_i0 = ((~cfpscr_thr0_l2[35]) & cfpscr_thr0_din_i0[35]) | ((~cfpscr_thr0_l2[36]) & cfpscr_thr0_din_i0[36]) | ((~cfpscr_thr0_l2[37]) & cfpscr_thr0_din_i0[37]) | ((~cfpscr_thr0_l2[38]) & cfpscr_thr0_din_i0[38]) | ((~cfpscr_thr0_l2[39]) & cfpscr_thr0_din_i0[39]) | ((~cfpscr_thr0_l2[40]) & cfpscr_thr0_din_i0[40]) | ((~cfpscr_thr0_l2[41]) & cfpscr_thr0_din_i0[41]) | ((~cfpscr_thr0_l2[42]) & cfpscr_thr0_din_i0[42]) | ((~cfpscr_thr0_l2[43]) & cfpscr_thr0_din_i0[43]) | ((~cfpscr_thr0_l2[44]) & cfpscr_thr0_din_i0[44]) | ((~cfpscr_thr0_l2[53]) & cfpscr_thr0_din_i0[53]) | ((~cfpscr_thr0_l2[54]) & cfpscr_thr0_din_i0[54]) | ((~cfpscr_thr0_l2[55]) & cfpscr_thr0_din_i0[55]); // vximx + + assign spare_unused[36:67] = cfpscr_thr0_din_i0[32:63]; + + //--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + + + //--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + //------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ + // Pipe Operations + assign cfpscr_pipe_thr1[32] = cfpscr_thr1_l2[32]; // check 0->1 excp after selection for move/pipe + assign cfpscr_pipe_thr1[33] = tidn; //// unused (from other bits after move/pipe selection) + assign cfpscr_pipe_thr1[34] = tidn; //// unused (from other bits after move/pipe selection) + assign cfpscr_pipe_thr1[35] = cfpscr_thr1_l2[35] | upd_i0_fpscr_thr1[35] | upd_i1_fpscr_thr1[35]; //ox STICKY + assign cfpscr_pipe_thr1[36] = cfpscr_thr1_l2[36] | upd_i0_fpscr_thr1[36] | upd_i1_fpscr_thr1[36]; //ux STICKY + assign cfpscr_pipe_thr1[37] = cfpscr_thr1_l2[37] | upd_i0_fpscr_thr1[37] | upd_i1_fpscr_thr1[37]; //zx sticky + assign cfpscr_pipe_thr1[38] = cfpscr_thr1_l2[38] | upd_i0_fpscr_thr1[38] | upd_i1_fpscr_thr1[38]; //xx sticky version of fi + + assign cfpscr_pipe_thr1[39] = cfpscr_thr1_l2[39] | upd_i0_fpscr_thr1[39] | upd_i1_fpscr_thr1[39]; //ex7_flag_vxsnan ; --sticky + assign cfpscr_pipe_thr1[40] = cfpscr_thr1_l2[40] | upd_i0_fpscr_thr1[40] | upd_i1_fpscr_thr1[40]; //ex7_flag_vxisi ; --sticky + assign cfpscr_pipe_thr1[41] = cfpscr_thr1_l2[41] | upd_i0_fpscr_thr1[41] | upd_i1_fpscr_thr1[41]; //ex7_flag_vxidi ; --sticky + assign cfpscr_pipe_thr1[42] = cfpscr_thr1_l2[42] | upd_i0_fpscr_thr1[42] | upd_i1_fpscr_thr1[42]; //ex7_flag_vxzdz ; --sticky + assign cfpscr_pipe_thr1[43] = cfpscr_thr1_l2[43] | upd_i0_fpscr_thr1[43] | upd_i1_fpscr_thr1[43]; //ex7_flag_vximz ; --sticky + assign cfpscr_pipe_thr1[44] = cfpscr_thr1_l2[44] | upd_i0_fpscr_thr1[44] | upd_i1_fpscr_thr1[44]; //ex7_flag_vxvc ; --sticky + + //fr NOT sticky + //no update if 1 compare + //no update if 1 compare + assign cfpscr_pipe_thr1[45] = (upd_i0_fpscr_thr1[45] & (~cfpscr_upd_i1_thr1)) | upd_i1_fpscr_thr1[45] | (cfpscr_thr1_l2[45] & (upd_i0_compare_thr1 & (~upd_i1_thr1))) | (cfpscr_thr1_l2[45] & (upd_i1_compare_thr1 & (~upd_i0_thr1))) | (cfpscr_thr1_l2[45] & (upd_i0_compare_thr1 & upd_i1_compare_thr1)) | (upd_i0_fpscr_thr1[45] & ((~upd_i0_compare_thr1) & upd_i0_thr1 & upd_i1_compare_thr1)); //no update if both compares + //i0 if i1 compare + + assign cfpscr_pipe_thr1[46] = (upd_i0_fpscr_thr1[46] & (~cfpscr_upd_i1_thr1)) | upd_i1_fpscr_thr1[46] | (cfpscr_thr1_l2[46] & (upd_i0_compare_thr1 & (~upd_i1_thr1))) | (cfpscr_thr1_l2[46] & (upd_i1_compare_thr1 & (~upd_i0_thr1))) | (cfpscr_thr1_l2[46] & (upd_i0_compare_thr1 & upd_i1_compare_thr1)) | (upd_i0_fpscr_thr1[46] & ((~upd_i0_compare_thr1) & upd_i0_thr1 & upd_i1_compare_thr1)); //fi NOT sticky + + assign upd_i0_fprf_hold_47_thr1 = upd_i0_compare_thr1 | upd_i0_fprf_hold_thr1; + assign upd_i1_fprf_hold_47_thr1 = upd_i1_compare_thr1 | upd_i1_fprf_hold_thr1; + + assign cfpscr_pipe_thr1[47] = (upd_i0_fpscr_thr1[47] & (~cfpscr_upd_i1_thr1)) | upd_i1_fpscr_thr1[47] | (cfpscr_thr1_l2[47] & (upd_i0_fprf_hold_47_thr1 & (~upd_i1_thr1))) | (cfpscr_thr1_l2[47] & (upd_i1_fprf_hold_47_thr1 & (~upd_i0_thr1))) | (cfpscr_thr1_l2[47] & (upd_i0_fprf_hold_47_thr1 & upd_i1_fprf_hold_47_thr1)) | (upd_i0_fpscr_thr1[47] & ((~upd_i0_fprf_hold_47_thr1) & upd_i0_thr1 & upd_i1_fprf_hold_47_thr1)); //FPRF C NOT sticky + + assign cfpscr_pipe_thr1[48] = (upd_i0_fpscr_thr1[48] & (~cfpscr_upd_i1_thr1)) | upd_i1_fpscr_thr1[48] | (cfpscr_thr1_l2[48] & (upd_i0_fprf_hold_thr1 & (~upd_i1_thr1))) | (cfpscr_thr1_l2[48] & (upd_i1_fprf_hold_thr1 & (~upd_i0_thr1))) | (cfpscr_thr1_l2[48] & (upd_i0_fprf_hold_thr1 & upd_i1_fprf_hold_thr1)) | (upd_i0_fpscr_thr1[48] & ((~upd_i0_fprf_hold_thr1) & upd_i0_thr1 & upd_i1_fprf_hold_thr1)); //FPRF fpdd(lt) + + assign cfpscr_pipe_thr1[49] = (upd_i0_fpscr_thr1[49] & (~cfpscr_upd_i1_thr1)) | upd_i1_fpscr_thr1[49] | (cfpscr_thr1_l2[49] & (upd_i0_fprf_hold_thr1 & (~upd_i1_thr1))) | (cfpscr_thr1_l2[49] & (upd_i1_fprf_hold_thr1 & (~upd_i0_thr1))) | (cfpscr_thr1_l2[49] & (upd_i0_fprf_hold_thr1 & upd_i1_fprf_hold_thr1)) | (upd_i0_fpscr_thr1[49] & ((~upd_i0_fprf_hold_thr1) & upd_i0_thr1 & upd_i1_fprf_hold_thr1)); //FPRF fpdd(gt) + + assign cfpscr_pipe_thr1[50] = (upd_i0_fpscr_thr1[50] & (~cfpscr_upd_i1_thr1)) | upd_i1_fpscr_thr1[50] | (cfpscr_thr1_l2[50] & (upd_i0_fprf_hold_thr1 & (~upd_i1_thr1))) | (cfpscr_thr1_l2[50] & (upd_i1_fprf_hold_thr1 & (~upd_i0_thr1))) | (cfpscr_thr1_l2[50] & (upd_i0_fprf_hold_thr1 & upd_i1_fprf_hold_thr1)) | (upd_i0_fpscr_thr1[50] & ((~upd_i0_fprf_hold_thr1) & upd_i0_thr1 & upd_i1_fprf_hold_thr1)); //FPRF fpdd(eq) + + assign cfpscr_pipe_thr1[51] = (upd_i0_fpscr_thr1[51] & (~cfpscr_upd_i1_thr1)) | upd_i1_fpscr_thr1[51] | (cfpscr_thr1_l2[51] & (upd_i0_fprf_hold_thr1 & (~upd_i1_thr1))) | (cfpscr_thr1_l2[51] & (upd_i1_fprf_hold_thr1 & (~upd_i0_thr1))) | (cfpscr_thr1_l2[51] & (upd_i0_fprf_hold_thr1 & upd_i1_fprf_hold_thr1)) | (upd_i0_fpscr_thr1[51] & ((~upd_i0_fprf_hold_thr1) & upd_i0_thr1 & upd_i1_fprf_hold_thr1)); //FPRF fpdd(nan) + + assign cfpscr_pipe_thr1[52] = tidn; //reserved + assign cfpscr_pipe_thr1[53] = cfpscr_thr1_l2[53]; //VXSOFT sticky + assign cfpscr_pipe_thr1[54] = cfpscr_thr1_l2[54] | upd_i0_fpscr_thr1[54] | upd_i1_fpscr_thr1[54]; //VXSQRT sticky + assign cfpscr_pipe_thr1[55] = cfpscr_thr1_l2[55] | upd_i0_fpscr_thr1[55] | upd_i1_fpscr_thr1[55]; //VXCVI sticky + + //cfpscr_din(28 to 31) <= cfpscr_pipe_thr1(28 to 31) ; + assign cfpscr_thr1_din[28] = (ex7_fpscr_move_dfp[0] & ex7_upd_move_thr1) | (cfpscr_thr1_l2[28] & (~ex7_upd_move_thr1)); + assign cfpscr_thr1_din[29] = (ex7_fpscr_move_dfp[1] & ex7_upd_move_thr1) | (cfpscr_thr1_l2[29] & (~ex7_upd_move_thr1)); + assign cfpscr_thr1_din[30] = (ex7_fpscr_move_dfp[2] & ex7_upd_move_thr1) | (cfpscr_thr1_l2[30] & (~ex7_upd_move_thr1)); + assign cfpscr_thr1_din[31] = (ex7_fpscr_move_dfp[3] & ex7_upd_move_thr1) | (cfpscr_thr1_l2[31] & (~ex7_upd_move_thr1)); + + // Control Bits + assign cfpscr_pipe_thr1[56:63] = cfpscr_thr1_l2[56:63]; + + assign cfpscr_thr1_din[63] = (ex7_fpscr_move[31] & ex7_upd_move_thr1) | (cfpscr_thr1_l2[63] & (~ex7_upd_move_thr1)); + assign cfpscr_thr1_din[62] = (ex7_fpscr_move[30] & ex7_upd_move_thr1) | (cfpscr_thr1_l2[62] & (~ex7_upd_move_thr1)); + assign cfpscr_thr1_din[61] = (ex7_fpscr_move[29] & ex7_upd_move_thr1) | (cfpscr_thr1_l2[61] & (~ex7_upd_move_thr1)); + assign cfpscr_thr1_din[60] = (ex7_fpscr_move[28] & ex7_upd_move_thr1) | (cfpscr_thr1_l2[60] & (~ex7_upd_move_thr1)); + assign cfpscr_thr1_din[59] = (ex7_fpscr_move[27] & ex7_upd_move_thr1) | (cfpscr_thr1_l2[59] & (~ex7_upd_move_thr1)); + assign cfpscr_thr1_din[58] = (ex7_fpscr_move[26] & ex7_upd_move_thr1) | (cfpscr_thr1_l2[58] & (~ex7_upd_move_thr1)); + assign cfpscr_thr1_din[57] = (ex7_fpscr_move[25] & ex7_upd_move_thr1) | (cfpscr_thr1_l2[57] & (~ex7_upd_move_thr1)); + assign cfpscr_thr1_din[56] = (ex7_fpscr_move[24] & ex7_upd_move_thr1) | (cfpscr_thr1_l2[56] & (~ex7_upd_move_thr1)); + + assign cfpscr_thr1_din[55] = (ex7_fpscr_move[23] & ex7_upd_move_thr1) | (cfpscr_pipe_thr1[55] & cfpscr_upd_pipe_thr1) | (cfpscr_thr1_l2[55] & (~(ex7_upd_move_thr1 | cfpscr_upd_pipe_thr1))); + assign cfpscr_thr1_din[54] = (ex7_fpscr_move[22] & ex7_upd_move_thr1) | (cfpscr_pipe_thr1[54] & cfpscr_upd_pipe_thr1) | (cfpscr_thr1_l2[54] & (~(ex7_upd_move_thr1 | cfpscr_upd_pipe_thr1))); + assign cfpscr_thr1_din[53] = (ex7_fpscr_move[21] & ex7_upd_move_thr1) | (cfpscr_pipe_thr1[53] & cfpscr_upd_pipe_thr1) | (cfpscr_thr1_l2[53] & (~(ex7_upd_move_thr1 | cfpscr_upd_pipe_thr1))); + assign cfpscr_thr1_din[52] = tidn; // reserved + assign cfpscr_thr1_din[51] = (ex7_fpscr_move[19] & ex7_upd_move_thr1) | (cfpscr_pipe_thr1[51] & cfpscr_upd_pipe_thr1) | (cfpscr_thr1_l2[51] & (~(ex7_upd_move_thr1 | cfpscr_upd_pipe_thr1))); + assign cfpscr_thr1_din[50] = (ex7_fpscr_move[18] & ex7_upd_move_thr1) | (cfpscr_pipe_thr1[50] & cfpscr_upd_pipe_thr1) | (cfpscr_thr1_l2[50] & (~(ex7_upd_move_thr1 | cfpscr_upd_pipe_thr1))); + assign cfpscr_thr1_din[49] = (ex7_fpscr_move[17] & ex7_upd_move_thr1) | (cfpscr_pipe_thr1[49] & cfpscr_upd_pipe_thr1) | (cfpscr_thr1_l2[49] & (~(ex7_upd_move_thr1 | cfpscr_upd_pipe_thr1))); + assign cfpscr_thr1_din[48] = (ex7_fpscr_move[16] & ex7_upd_move_thr1) | (cfpscr_pipe_thr1[48] & cfpscr_upd_pipe_thr1) | (cfpscr_thr1_l2[48] & (~(ex7_upd_move_thr1 | cfpscr_upd_pipe_thr1))); + assign cfpscr_thr1_din[47] = (ex7_fpscr_move[15] & ex7_upd_move_thr1) | (cfpscr_pipe_thr1[47] & cfpscr_upd_pipe_thr1) | (cfpscr_thr1_l2[47] & (~(ex7_upd_move_thr1 | cfpscr_upd_pipe_thr1))); + assign cfpscr_thr1_din[46] = (ex7_fpscr_move[14] & ex7_upd_move_thr1) | (cfpscr_pipe_thr1[46] & cfpscr_upd_pipe_thr1) | (cfpscr_thr1_l2[46] & (~(ex7_upd_move_thr1 | cfpscr_upd_pipe_thr1))); + assign cfpscr_thr1_din[45] = (ex7_fpscr_move[13] & ex7_upd_move_thr1) | (cfpscr_pipe_thr1[45] & cfpscr_upd_pipe_thr1) | (cfpscr_thr1_l2[45] & (~(ex7_upd_move_thr1 | cfpscr_upd_pipe_thr1))); + assign cfpscr_thr1_din[44] = (ex7_fpscr_move[12] & ex7_upd_move_thr1) | (cfpscr_pipe_thr1[44] & cfpscr_upd_pipe_thr1) | (cfpscr_thr1_l2[44] & (~(ex7_upd_move_thr1 | cfpscr_upd_pipe_thr1))); + assign cfpscr_thr1_din[43] = (ex7_fpscr_move[11] & ex7_upd_move_thr1) | (cfpscr_pipe_thr1[43] & cfpscr_upd_pipe_thr1) | (cfpscr_thr1_l2[43] & (~(ex7_upd_move_thr1 | cfpscr_upd_pipe_thr1))); + assign cfpscr_thr1_din[42] = (ex7_fpscr_move[10] & ex7_upd_move_thr1) | (cfpscr_pipe_thr1[42] & cfpscr_upd_pipe_thr1) | (cfpscr_thr1_l2[42] & (~(ex7_upd_move_thr1 | cfpscr_upd_pipe_thr1))); + assign cfpscr_thr1_din[41] = (ex7_fpscr_move[9] & ex7_upd_move_thr1) | (cfpscr_pipe_thr1[41] & cfpscr_upd_pipe_thr1) | (cfpscr_thr1_l2[41] & (~(ex7_upd_move_thr1 | cfpscr_upd_pipe_thr1))); + assign cfpscr_thr1_din[40] = (ex7_fpscr_move[8] & ex7_upd_move_thr1) | (cfpscr_pipe_thr1[40] & cfpscr_upd_pipe_thr1) | (cfpscr_thr1_l2[40] & (~(ex7_upd_move_thr1 | cfpscr_upd_pipe_thr1))); + assign cfpscr_thr1_din[39] = (ex7_fpscr_move[7] & ex7_upd_move_thr1) | (cfpscr_pipe_thr1[39] & cfpscr_upd_pipe_thr1) | (cfpscr_thr1_l2[39] & (~(ex7_upd_move_thr1 | cfpscr_upd_pipe_thr1))); + assign cfpscr_thr1_din[38] = (ex7_fpscr_move[6] & ex7_upd_move_thr1) | (cfpscr_pipe_thr1[38] & cfpscr_upd_pipe_thr1) | (cfpscr_thr1_l2[38] & (~(ex7_upd_move_thr1 | cfpscr_upd_pipe_thr1))); + assign cfpscr_thr1_din[37] = (ex7_fpscr_move[5] & ex7_upd_move_thr1) | (cfpscr_pipe_thr1[37] & cfpscr_upd_pipe_thr1) | (cfpscr_thr1_l2[37] & (~(ex7_upd_move_thr1 | cfpscr_upd_pipe_thr1))); + assign cfpscr_thr1_din[36] = (ex7_fpscr_move[4] & ex7_upd_move_thr1) | (cfpscr_pipe_thr1[36] & cfpscr_upd_pipe_thr1) | (cfpscr_thr1_l2[36] & (~(ex7_upd_move_thr1 | cfpscr_upd_pipe_thr1))); + assign cfpscr_thr1_din[35] = (ex7_fpscr_move[3] & ex7_upd_move_thr1) | (cfpscr_pipe_thr1[35] & cfpscr_upd_pipe_thr1) | (cfpscr_thr1_l2[35] & (~(ex7_upd_move_thr1 | cfpscr_upd_pipe_thr1))); + + // or all invalid operation exceptions + // vxsnan + // vxisi + // vxidi + // vxzdz + // vximx + // vxvc + // vxzdz + assign cfpscr_thr1_din[34] = cfpscr_thr1_din[39] | cfpscr_thr1_din[40] | cfpscr_thr1_din[41] | cfpscr_thr1_din[42] | cfpscr_thr1_din[43] | cfpscr_thr1_din[44] | cfpscr_thr1_din[53] | cfpscr_thr1_din[54] | cfpscr_thr1_din[55]; // vximx + // vxvc + + // masked or of all exception bits + // vx* / ve + // ox / oe + // ux / ue + assign cfpscr_thr1_din[33] = (cfpscr_thr1_din[34] & cfpscr_thr1_din[56]) | (cfpscr_thr1_din[35] & cfpscr_thr1_din[57]) | (cfpscr_thr1_din[36] & cfpscr_thr1_din[58]) | (cfpscr_thr1_din[37] & cfpscr_thr1_din[59]) | (cfpscr_thr1_din[38] & cfpscr_thr1_din[60]); // zx / ze + // xx / xe + + assign cfpscr_thr1_din[32] = (ex7_fpscr_move[0] & ex7_upd_move_thr1) | (cfpscr_pipe_thr1[32] & (~ex7_upd_move_thr1)) | (cfpscr_new_excp_thr1 & (~(((ex7_mtfsf | ex7_mtfsfi) & ex7_thread[1]) & (~f_dcd_ex7_cancel)))); //upd_pipe and hold sticky + + // only check the exception bits + // ox + // ux + // zx + // xx + // vxsnan + // vxisi + // vxidi + // vxzdz + // vximx + // vxvc + // vxzdz + assign cfpscr_new_excp_thr1 = ((~cfpscr_thr1_l2[35]) & cfpscr_thr1_din[35]) | ((~cfpscr_thr1_l2[36]) & cfpscr_thr1_din[36]) | ((~cfpscr_thr1_l2[37]) & cfpscr_thr1_din[37]) | ((~cfpscr_thr1_l2[38]) & cfpscr_thr1_din[38]) | ((~cfpscr_thr1_l2[39]) & cfpscr_thr1_din[39]) | ((~cfpscr_thr1_l2[40]) & cfpscr_thr1_din[40]) | ((~cfpscr_thr1_l2[41]) & cfpscr_thr1_din[41]) | ((~cfpscr_thr1_l2[42]) & cfpscr_thr1_din[42]) | ((~cfpscr_thr1_l2[43]) & cfpscr_thr1_din[43]) | ((~cfpscr_thr1_l2[44]) & cfpscr_thr1_din[44]) | ((~cfpscr_thr1_l2[53]) & cfpscr_thr1_din[53]) | ((~cfpscr_thr1_l2[54]) & cfpscr_thr1_din[54]) | ((~cfpscr_thr1_l2[55]) & cfpscr_thr1_din[55]); // vximx + // vxvc + //---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + //--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + //-FOR RTX only: Thread 1 i0 completion only ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + assign cfpscr_pipe_thr1_i0[32] = cfpscr_thr1_l2[32]; // check 0->1 excp after selection for move/pipe + assign cfpscr_pipe_thr1_i0[33] = tidn; //// unused (from other bits after move/pipe selection) + assign cfpscr_pipe_thr1_i0[34] = tidn; //// unused (from other bits after move/pipe selection) + assign cfpscr_pipe_thr1_i0[35] = cfpscr_thr1_l2[35] | upd_i0_fpscr_thr1[35] ; //ox STICKY + assign cfpscr_pipe_thr1_i0[36] = cfpscr_thr1_l2[36] | upd_i0_fpscr_thr1[36] ; //ux STICKY + assign cfpscr_pipe_thr1_i0[37] = cfpscr_thr1_l2[37] | upd_i0_fpscr_thr1[37] ; //zx sticky + assign cfpscr_pipe_thr1_i0[38] = cfpscr_thr1_l2[38] | upd_i0_fpscr_thr1[38] ; //xx sticky version of fi + + assign cfpscr_pipe_thr1_i0[39] = cfpscr_thr1_l2[39] | upd_i0_fpscr_thr1[39] ; //ex7_flag_vxsnan ; --sticky + assign cfpscr_pipe_thr1_i0[40] = cfpscr_thr1_l2[40] | upd_i0_fpscr_thr1[40] ; //ex7_flag_vxisi ; --sticky + assign cfpscr_pipe_thr1_i0[41] = cfpscr_thr1_l2[41] | upd_i0_fpscr_thr1[41] ; //ex7_flag_vxidi ; --sticky + assign cfpscr_pipe_thr1_i0[42] = cfpscr_thr1_l2[42] | upd_i0_fpscr_thr1[42] ; //ex7_flag_vxzdz ; --sticky + assign cfpscr_pipe_thr1_i0[43] = cfpscr_thr1_l2[43] | upd_i0_fpscr_thr1[43] ; //ex7_flag_vximz ; --sticky + assign cfpscr_pipe_thr1_i0[44] = cfpscr_thr1_l2[44] | upd_i0_fpscr_thr1[44] ; //ex7_flag_vxvc ; --sticky + + //fr NOT sticky + //no update if 1 compare + //no update if 1 compare + assign cfpscr_pipe_thr1_i0[45] = (upd_i0_fpscr_thr1[45]) | (cfpscr_thr1_l2[45] & (upd_i0_compare_thr1)) | (upd_i0_fpscr_thr1[45] & ((~upd_i0_compare_thr1) & upd_i0_thr1)); //no update if both compares + //i0 if i1 compare + + assign cfpscr_pipe_thr1_i0[46] = (upd_i0_fpscr_thr1[46]) | (cfpscr_thr1_l2[46] & (upd_i0_compare_thr1)) | (upd_i0_fpscr_thr1[46] & ((~upd_i0_compare_thr1) & upd_i0_thr1)); //fi NOT sticky + + assign cfpscr_pipe_thr1_i0[47] = (upd_i0_fpscr_thr1[47]) | (cfpscr_thr1_l2[47] & (upd_i0_fprf_hold_47_thr1 )) | (upd_i0_fpscr_thr1[47] & ((~upd_i0_fprf_hold_47_thr1) & upd_i0_thr1)); //FPRF C NOT sticky + + assign cfpscr_pipe_thr1_i0[48] = (upd_i0_fpscr_thr1[48]) | (cfpscr_thr1_l2[48] & (upd_i0_fprf_hold_thr1 )) | (upd_i0_fpscr_thr1[48] & ((~upd_i0_fprf_hold_thr1) & upd_i0_thr1)); //FPRF fpdd(lt) + + assign cfpscr_pipe_thr1_i0[49] = (upd_i0_fpscr_thr1[49]) | (cfpscr_thr1_l2[49] & (upd_i0_fprf_hold_thr1 )) | (upd_i0_fpscr_thr1[49] & ((~upd_i0_fprf_hold_thr1) & upd_i0_thr1)); //FPRF fpdd(gt) + + assign cfpscr_pipe_thr1_i0[50] = (upd_i0_fpscr_thr1[50]) | (cfpscr_thr1_l2[50] & (upd_i0_fprf_hold_thr1 )) | (upd_i0_fpscr_thr1[50] & ((~upd_i0_fprf_hold_thr1) & upd_i0_thr1)); //FPRF fpdd(eq) + + assign cfpscr_pipe_thr1_i0[51] = (upd_i0_fpscr_thr1[51]) | (cfpscr_thr1_l2[51] & (upd_i0_fprf_hold_thr1 )) | (upd_i0_fpscr_thr1[51] & ((~upd_i0_fprf_hold_thr1) & upd_i0_thr1)); //FPRF fpdd(nan) + + assign cfpscr_pipe_thr1_i0[52] = tidn; //reserved + assign cfpscr_pipe_thr1_i0[53] = cfpscr_thr1_l2[53]; //VXSOFT sticky + assign cfpscr_pipe_thr1_i0[54] = cfpscr_thr1_l2[54] | upd_i0_fpscr_thr1[54] ; //VXSQRT sticky + assign cfpscr_pipe_thr1_i0[55] = cfpscr_thr1_l2[55] | upd_i0_fpscr_thr1[55] ; //VXCVI sticky + + assign cfpscr_thr1_din_i0[28] = (ex7_fpscr_move_dfp[0] & ex7_upd_move_thr1) | (cfpscr_thr1_l2[28] & (~ex7_upd_move_thr1)); + assign cfpscr_thr1_din_i0[29] = (ex7_fpscr_move_dfp[1] & ex7_upd_move_thr1) | (cfpscr_thr1_l2[29] & (~ex7_upd_move_thr1)); + assign cfpscr_thr1_din_i0[30] = (ex7_fpscr_move_dfp[2] & ex7_upd_move_thr1) | (cfpscr_thr1_l2[30] & (~ex7_upd_move_thr1)); + assign cfpscr_thr1_din_i0[31] = (ex7_fpscr_move_dfp[3] & ex7_upd_move_thr1) | (cfpscr_thr1_l2[31] & (~ex7_upd_move_thr1)); + + // Control Bits + assign cfpscr_pipe_thr1_i0[56:63] = cfpscr_thr1_l2[56:63]; + + assign cfpscr_thr1_din_i0[63] = (ex7_fpscr_move[31] & ex7_upd_move_thr1) | (cfpscr_thr1_l2[63] & (~ex7_upd_move_thr1)); + assign cfpscr_thr1_din_i0[62] = (ex7_fpscr_move[30] & ex7_upd_move_thr1) | (cfpscr_thr1_l2[62] & (~ex7_upd_move_thr1)); + assign cfpscr_thr1_din_i0[61] = (ex7_fpscr_move[29] & ex7_upd_move_thr1) | (cfpscr_thr1_l2[61] & (~ex7_upd_move_thr1)); + assign cfpscr_thr1_din_i0[60] = (ex7_fpscr_move[28] & ex7_upd_move_thr1) | (cfpscr_thr1_l2[60] & (~ex7_upd_move_thr1)); + assign cfpscr_thr1_din_i0[59] = (ex7_fpscr_move[27] & ex7_upd_move_thr1) | (cfpscr_thr1_l2[59] & (~ex7_upd_move_thr1)); + assign cfpscr_thr1_din_i0[58] = (ex7_fpscr_move[26] & ex7_upd_move_thr1) | (cfpscr_thr1_l2[58] & (~ex7_upd_move_thr1)); + assign cfpscr_thr1_din_i0[57] = (ex7_fpscr_move[25] & ex7_upd_move_thr1) | (cfpscr_thr1_l2[57] & (~ex7_upd_move_thr1)); + assign cfpscr_thr1_din_i0[56] = (ex7_fpscr_move[24] & ex7_upd_move_thr1) | (cfpscr_thr1_l2[56] & (~ex7_upd_move_thr1)); + + assign cfpscr_thr1_din_i0[55] = (ex7_fpscr_move[23] & ex7_upd_move_thr1) | (cfpscr_pipe_thr1_i0[55] & cfpscr_upd_i0_thr1) | (cfpscr_thr1_l2[55] & (~(ex7_upd_move_thr1 | cfpscr_upd_i0_thr1))); + assign cfpscr_thr1_din_i0[54] = (ex7_fpscr_move[22] & ex7_upd_move_thr1) | (cfpscr_pipe_thr1_i0[54] & cfpscr_upd_i0_thr1) | (cfpscr_thr1_l2[54] & (~(ex7_upd_move_thr1 | cfpscr_upd_i0_thr1))); + assign cfpscr_thr1_din_i0[53] = (ex7_fpscr_move[21] & ex7_upd_move_thr1) | (cfpscr_pipe_thr1_i0[53] & cfpscr_upd_i0_thr1) | (cfpscr_thr1_l2[53] & (~(ex7_upd_move_thr1 | cfpscr_upd_i0_thr1))); + assign cfpscr_thr1_din_i0[52] = tidn; // reserved + assign cfpscr_thr1_din_i0[51] = (ex7_fpscr_move[19] & ex7_upd_move_thr1) | (cfpscr_pipe_thr1_i0[51] & cfpscr_upd_i0_thr1) | (cfpscr_thr1_l2[51] & (~(ex7_upd_move_thr1 | cfpscr_upd_i0_thr1))); + assign cfpscr_thr1_din_i0[50] = (ex7_fpscr_move[18] & ex7_upd_move_thr1) | (cfpscr_pipe_thr1_i0[50] & cfpscr_upd_i0_thr1) | (cfpscr_thr1_l2[50] & (~(ex7_upd_move_thr1 | cfpscr_upd_i0_thr1))); + assign cfpscr_thr1_din_i0[49] = (ex7_fpscr_move[17] & ex7_upd_move_thr1) | (cfpscr_pipe_thr1_i0[49] & cfpscr_upd_i0_thr1) | (cfpscr_thr1_l2[49] & (~(ex7_upd_move_thr1 | cfpscr_upd_i0_thr1))); + assign cfpscr_thr1_din_i0[48] = (ex7_fpscr_move[16] & ex7_upd_move_thr1) | (cfpscr_pipe_thr1_i0[48] & cfpscr_upd_i0_thr1) | (cfpscr_thr1_l2[48] & (~(ex7_upd_move_thr1 | cfpscr_upd_i0_thr1))); + assign cfpscr_thr1_din_i0[47] = (ex7_fpscr_move[15] & ex7_upd_move_thr1) | (cfpscr_pipe_thr1_i0[47] & cfpscr_upd_i0_thr1) | (cfpscr_thr1_l2[47] & (~(ex7_upd_move_thr1 | cfpscr_upd_i0_thr1))); + assign cfpscr_thr1_din_i0[46] = (ex7_fpscr_move[14] & ex7_upd_move_thr1) | (cfpscr_pipe_thr1_i0[46] & cfpscr_upd_i0_thr1) | (cfpscr_thr1_l2[46] & (~(ex7_upd_move_thr1 | cfpscr_upd_i0_thr1))); + assign cfpscr_thr1_din_i0[45] = (ex7_fpscr_move[13] & ex7_upd_move_thr1) | (cfpscr_pipe_thr1_i0[45] & cfpscr_upd_i0_thr1) | (cfpscr_thr1_l2[45] & (~(ex7_upd_move_thr1 | cfpscr_upd_i0_thr1))); + assign cfpscr_thr1_din_i0[44] = (ex7_fpscr_move[12] & ex7_upd_move_thr1) | (cfpscr_pipe_thr1_i0[44] & cfpscr_upd_i0_thr1) | (cfpscr_thr1_l2[44] & (~(ex7_upd_move_thr1 | cfpscr_upd_i0_thr1))); + assign cfpscr_thr1_din_i0[43] = (ex7_fpscr_move[11] & ex7_upd_move_thr1) | (cfpscr_pipe_thr1_i0[43] & cfpscr_upd_i0_thr1) | (cfpscr_thr1_l2[43] & (~(ex7_upd_move_thr1 | cfpscr_upd_i0_thr1))); + assign cfpscr_thr1_din_i0[42] = (ex7_fpscr_move[10] & ex7_upd_move_thr1) | (cfpscr_pipe_thr1_i0[42] & cfpscr_upd_i0_thr1) | (cfpscr_thr1_l2[42] & (~(ex7_upd_move_thr1 | cfpscr_upd_i0_thr1))); + assign cfpscr_thr1_din_i0[41] = (ex7_fpscr_move[9] & ex7_upd_move_thr1) | (cfpscr_pipe_thr1_i0[41] & cfpscr_upd_i0_thr1) | (cfpscr_thr1_l2[41] & (~(ex7_upd_move_thr1 | cfpscr_upd_i0_thr1))); + assign cfpscr_thr1_din_i0[40] = (ex7_fpscr_move[8] & ex7_upd_move_thr1) | (cfpscr_pipe_thr1_i0[40] & cfpscr_upd_i0_thr1) | (cfpscr_thr1_l2[40] & (~(ex7_upd_move_thr1 | cfpscr_upd_i0_thr1))); + assign cfpscr_thr1_din_i0[39] = (ex7_fpscr_move[7] & ex7_upd_move_thr1) | (cfpscr_pipe_thr1_i0[39] & cfpscr_upd_i0_thr1) | (cfpscr_thr1_l2[39] & (~(ex7_upd_move_thr1 | cfpscr_upd_i0_thr1))); + assign cfpscr_thr1_din_i0[38] = (ex7_fpscr_move[6] & ex7_upd_move_thr1) | (cfpscr_pipe_thr1_i0[38] & cfpscr_upd_i0_thr1) | (cfpscr_thr1_l2[38] & (~(ex7_upd_move_thr1 | cfpscr_upd_i0_thr1))); + assign cfpscr_thr1_din_i0[37] = (ex7_fpscr_move[5] & ex7_upd_move_thr1) | (cfpscr_pipe_thr1_i0[37] & cfpscr_upd_i0_thr1) | (cfpscr_thr1_l2[37] & (~(ex7_upd_move_thr1 | cfpscr_upd_i0_thr1))); + assign cfpscr_thr1_din_i0[36] = (ex7_fpscr_move[4] & ex7_upd_move_thr1) | (cfpscr_pipe_thr1_i0[36] & cfpscr_upd_i0_thr1) | (cfpscr_thr1_l2[36] & (~(ex7_upd_move_thr1 | cfpscr_upd_i0_thr1))); + assign cfpscr_thr1_din_i0[35] = (ex7_fpscr_move[3] & ex7_upd_move_thr1) | (cfpscr_pipe_thr1_i0[35] & cfpscr_upd_i0_thr1) | (cfpscr_thr1_l2[35] & (~(ex7_upd_move_thr1 | cfpscr_upd_i0_thr1))); + + assign cfpscr_thr1_din_i0[34] = cfpscr_thr1_din_i0[39] | cfpscr_thr1_din_i0[40] | cfpscr_thr1_din_i0[41] | cfpscr_thr1_din_i0[42] | cfpscr_thr1_din_i0[43] | cfpscr_thr1_din_i0[44] | cfpscr_thr1_din_i0[53] | cfpscr_thr1_din_i0[54] | cfpscr_thr1_din_i0[55]; // vximx + + assign cfpscr_thr1_din_i0[33] = (cfpscr_thr1_din_i0[34] & cfpscr_thr1_din_i0[56]) | (cfpscr_thr1_din_i0[35] & cfpscr_thr1_din_i0[57]) | (cfpscr_thr1_din_i0[36] & cfpscr_thr1_din_i0[58]) | (cfpscr_thr1_din_i0[37] & cfpscr_thr1_din_i0[59]) | (cfpscr_thr1_din_i0[38] & cfpscr_thr1_din_i0[60]); // zx / ze + + assign cfpscr_thr1_din_i0[32] = (ex7_fpscr_move[0] & ex7_upd_move_thr1) | (cfpscr_pipe_thr1_i0[32] & (~ex7_upd_move_thr1)) | (cfpscr_new_excp_thr1_i0 & (~(((ex7_mtfsf | ex7_mtfsfi) & ex7_thread[1]) & (~f_dcd_ex7_cancel)))); //upd_pipe and hold sticky + + assign cfpscr_new_excp_thr1_i0 = ((~cfpscr_thr1_l2[35]) & cfpscr_thr1_din_i0[35]) | ((~cfpscr_thr1_l2[36]) & cfpscr_thr1_din_i0[36]) | ((~cfpscr_thr1_l2[37]) & cfpscr_thr1_din_i0[37]) | ((~cfpscr_thr1_l2[38]) & cfpscr_thr1_din_i0[38]) | ((~cfpscr_thr1_l2[39]) & cfpscr_thr1_din_i0[39]) | ((~cfpscr_thr1_l2[40]) & cfpscr_thr1_din_i0[40]) | ((~cfpscr_thr1_l2[41]) & cfpscr_thr1_din_i0[41]) | ((~cfpscr_thr1_l2[42]) & cfpscr_thr1_din_i0[42]) | ((~cfpscr_thr1_l2[43]) & cfpscr_thr1_din_i0[43]) | ((~cfpscr_thr1_l2[44]) & cfpscr_thr1_din_i0[44]) | ((~cfpscr_thr1_l2[53]) & cfpscr_thr1_din_i0[53]) | ((~cfpscr_thr1_l2[54]) & cfpscr_thr1_din_i0[54]) | ((~cfpscr_thr1_l2[55]) & cfpscr_thr1_din_i0[55]); // vximx + + assign spare_unused[4:35] = cfpscr_thr1_din_i0[32:63]; + + //--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- + + // Completed FPSCR + + tri_rlmreg_p #(.WIDTH(36)) cfpscr_thr0_lat( + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[7]), + .mpw1_b(mpw1_b[7]), + .mpw2_b(mpw2_b[1]), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(thold_0_b), + .sg(sg_0), + .scout(cfpscr_thr0_so), + .scin(cfpscr_thr0_si), + //----------------- + .din({ cfpscr_thr0_din[28:63]}), + .dout({ cfpscr_thr0_l2[28:63]}) //LAT-- + ); + + + tri_rlmreg_p #(.WIDTH(4)) cadd_lat_thr0( + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[7]), + .mpw1_b(mpw1_b[7]), + .mpw2_b(mpw2_b[1]), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(thold_0_b), + .sg(sg_0), + .scout(cadd_so), + .scin(cadd_si), + //----------------- + .din({ re0_thr0, + re1_thr0, + re0_2_thr0, + re1_2_thr0}), + //----------------- + .dout({ re0_2_thr0, + re1_2_thr0, + spare_unused[0], //upd_i0_thr0, + spare_unused[1]}) //upd_i1_thr0 ); + ); + + assign upd_i0_thr0 = re0_2_thr0; + assign upd_i1_thr0 = re1_2_thr0; + + generate + if (THREADS == 2) + begin : oscr_cadd_lat_thr1 + + + tri_rlmreg_p #(.WIDTH(36)) cfpscr_thr1_lat( + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[7]), + .mpw1_b(mpw1_b[7]), + .mpw2_b(mpw2_b[1]), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(thold_0_b), + .sg(sg_0), + .scout(cfpscr_thr1_so), + .scin(cfpscr_thr1_si), + //----------------- + .din( cfpscr_thr1_din[28:63]), + .dout( cfpscr_thr1_l2[28:63]) //LAT-- + ); + + + tri_rlmreg_p #(.WIDTH(4)) cadd_lat_thr1( + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[7]), + .mpw1_b(mpw1_b[7]), + .mpw2_b(mpw2_b[1]), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(thold_0_b), + .sg(sg_0), + .scout(cadd_thr1_so), + .scin(cadd_thr1_si), + //----------------- + .din({ re0_thr1, + re1_thr1, + re0_2_thr1, + re1_2_thr1}), + //----------------- + .dout({ re0_2_thr1, + re1_2_thr1, + spare_unused[2], //upd_i0_thr1, + spare_unused[3]}) //upd_i1_thr1 ); + ); + + assign upd_i0_thr1 = re0_2_thr1; + assign upd_i1_thr1 = re1_2_thr1; + end + endgenerate + + ////############################################ + ////# scan + ////############################################ + + assign ex5_ctl_si[0:24] = {ex5_ctl_so[1:24], f_scr_si}; + assign ex6_ctl_si[0:24] = {ex6_ctl_so[1:24], ex5_ctl_so[0]}; + assign ex7_ctl_si[0:24] = {ex7_ctl_so[1:24], ex6_ctl_so[0]}; + assign ex8_ctl_si[0:3] = {ex8_ctl_so[1:3], ex7_ctl_so[0]}; + assign ex7_flag_si[0:26] = {ex7_flag_so[1:26], ex8_ctl_so[0]}; + assign ex7_mvdat_si[0:35] = {ex7_mvdat_so[1:35], ex7_flag_so[0]}; + assign fpscr_th0_si[0:27] = {fpscr_th0_so[1:27], ex7_mvdat_so[0]}; + assign fpscr_th1_si[0:27] = {fpscr_th1_so[1:27], fpscr_th0_so[0]}; + assign fpscr_th2_si[0:27] = {fpscr_th2_so[1:27], fpscr_th1_so[0]}; + assign fpscr_th3_si[0:27] = {fpscr_th3_so[1:27], fpscr_th2_so[0]}; + assign ex8_crf_si[0:3] = {ex8_crf_so[1:3], fpscr_th3_so[0]}; + + + + assign act_si[0:13] = {act_so[1:13], ex8_crf_so[0]}; + assign f_scr_so = act_so[0]; + + //TODO fix me + assign ex7_hfpscr_pipe[0:2] = {tidn, tidn, tidn}; + assign cfpscr_pipe_thr0[28:31] = {4{tidn}}; + + assign cfpscr_pipe_thr1[28:31] = {4{tidn}}; + assign fpscr_th2_so = {28{tidn}}; + assign fpscr_th3_so = {28{tidn}}; + + + assign cfpscr_thr1_si = {36{tidn}}; + assign cfpscr_thr0_si = {36{tidn}}; + + assign cadd_thr1_si = {4{tidn}}; + assign cadd_si = {4{tidn}}; + + assign fpscr_dfp_th2 = {4{tidn}}; + assign fpscr_dfp_th3 = {4{tidn}}; + assign fpscr_th2 = {24{tidn}}; + assign fpscr_th3 = {24{tidn}}; + + assign unused_stuff = |(f_nrm_ex6_fpscr_wr_dat[24:31]) | ex7_mtfsbx | ex7_fpscr_move[1] | + ex7_fpscr_move[2] | ex7_fpscr_move[20] | ex7_fpscr_pipe[1] | + ex7_fpscr_pipe[2] | ex7_fpscr_pipe[20] | ex7_mv_data[1] | ex7_mv_data[2] | + ex7_mv_sel[1] | ex7_mv_sel[2]; + +endmodule diff --git a/dev/verilog/work/fu_perv.v b/dev/verilog/work/fu_perv.v new file mode 100755 index 0000000..4a21030 --- /dev/null +++ b/dev/verilog/work/fu_perv.v @@ -0,0 +1,332 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// ********************************************************************* +// +// This is the ENTITY for fu_perv +// +// ********************************************************************* + +`include "tri_a2o.vh" + +module fu_perv( + vdd, + gnd, + nclk, + pc_fu_sg_3, + pc_fu_abst_sl_thold_3, + pc_fu_func_sl_thold_3, + pc_fu_func_slp_sl_thold_3, + pc_fu_gptr_sl_thold_3, + pc_fu_time_sl_thold_3, + pc_fu_ary_nsl_thold_3, + pc_fu_cfg_sl_thold_3, + pc_fu_repr_sl_thold_3, + pc_fu_fce_3, + tc_ac_ccflush_dc, + tc_ac_scan_diag_dc, + abst_sl_thold_1, + func_sl_thold_1, + time_sl_thold_1, + ary_nsl_thold_1, + cfg_sl_thold_1, + gptr_sl_thold_0, + func_slp_sl_thold_1, + fce_1, + sg_1, + clkoff_dc_b, + act_dis, + delay_lclkr_dc, + mpw1_dc_b, + mpw2_dc_b, + repr_scan_in, + repr_scan_out, + gptr_scan_in, + gptr_scan_out +); + inout vdd; + inout gnd; + + input [0:`NCLK_WIDTH-1] nclk; + input [0:1] pc_fu_sg_3; + input pc_fu_abst_sl_thold_3; + input [0:1] pc_fu_func_sl_thold_3; + input [0:1] pc_fu_func_slp_sl_thold_3; + input pc_fu_gptr_sl_thold_3; + input pc_fu_time_sl_thold_3; + input pc_fu_ary_nsl_thold_3; + input pc_fu_cfg_sl_thold_3; + input pc_fu_repr_sl_thold_3; + input pc_fu_fce_3; + input tc_ac_ccflush_dc; + input tc_ac_scan_diag_dc; + output abst_sl_thold_1; + output [0:1] func_sl_thold_1; + output time_sl_thold_1; + output ary_nsl_thold_1; + output cfg_sl_thold_1; + output gptr_sl_thold_0; + output func_slp_sl_thold_1; + + output fce_1; + output [0:1] sg_1; + output clkoff_dc_b; + output act_dis; + output [0:9] delay_lclkr_dc; + output [0:9] mpw1_dc_b; + output [0:1] mpw2_dc_b; + input repr_scan_in; //tc_ac_repr_scan_in(2) + output repr_scan_out; //tc_ac_repr_scan_in(2) + input gptr_scan_in; + output gptr_scan_out; + + //-- + + wire abst_sl_thold_2; + wire time_sl_thold_2; + wire [0:1] func_sl_thold_2; + wire func_slp_sl_thold_2; + + wire gptr_sl_thold_0_int; + + + + wire gptr_sl_thold_2; + wire ary_nsl_thold_2; + wire cfg_sl_thold_2; + wire repr_sl_thold_2; + + wire [0:1] sg_2; + wire fce_2; + + wire gptr_sl_thold_1; + wire repr_sl_thold_1; + wire [0:1] sg_1_int; + + + wire repr_sl_thold_0; + wire repr_sl_force; + wire repr_sl_thold_0_b; + wire repr_in; + wire repr_UNUSED; + + (* analysis_not_assigned="true" *) + (* analysis_not_referenced="true" *) + wire spare_unused; + + wire sg_0; + wire gptr_sio; + wire [0:9] prv_delay_lclkr_dc; + wire [0:9] prv_mpw1_dc_b; + wire [0:1] prv_mpw2_dc_b; + wire prv_act_dis; + wire prv_clkoff_dc_b; + wire tihi; + wire tiup; + + assign tihi = 1'b1; + assign tiup = 1'b1; + + + tri_plat #(.WIDTH(12)) perv_3to2_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + + .din({ + pc_fu_func_sl_thold_3[0:1], + pc_fu_gptr_sl_thold_3, + pc_fu_abst_sl_thold_3, + pc_fu_sg_3[0:1], + pc_fu_time_sl_thold_3, + pc_fu_fce_3, + pc_fu_ary_nsl_thold_3, + pc_fu_cfg_sl_thold_3, + pc_fu_repr_sl_thold_3, + pc_fu_func_slp_sl_thold_3[0]}), + + .q({ + func_sl_thold_2[0:1], + gptr_sl_thold_2, + abst_sl_thold_2, + sg_2[0:1], + time_sl_thold_2, + fce_2, + ary_nsl_thold_2, + cfg_sl_thold_2, + repr_sl_thold_2, + func_slp_sl_thold_2}) + ); + + + tri_plat #(.WIDTH(12)) perv_2to1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + + .din({ + func_sl_thold_2[0:1], + gptr_sl_thold_2, + abst_sl_thold_2, + sg_2[0:1], + time_sl_thold_2, + fce_2, + ary_nsl_thold_2, + cfg_sl_thold_2, + repr_sl_thold_2, + func_slp_sl_thold_2}), + + .q({ + func_sl_thold_1[0:1], + gptr_sl_thold_1, + abst_sl_thold_1, + sg_1_int[0:1], + time_sl_thold_1, + fce_1, + ary_nsl_thold_1, + cfg_sl_thold_1, + repr_sl_thold_1, + func_slp_sl_thold_1}) + ); + + assign sg_1[0:1] = sg_1_int[0:1]; + + + tri_plat #(.WIDTH(3)) perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + .din({ gptr_sl_thold_1, + sg_1_int[0], + repr_sl_thold_1}), + + .q({ gptr_sl_thold_0_int, + sg_0, + repr_sl_thold_0}) + ); + + assign gptr_sl_thold_0 = gptr_sl_thold_0_int; + +// Pipeline mapping of mpw1_b and delay_lclkr, mpw2_b +// RF0 8 1 +// RF1 0 0 +// EX1 1 0 +// EX2 2 0 +// EX3 3 0 +// EX4 4 0 +// EX5 5 1 +// EX6 6 1 +// EX7 7 1 +// Ctrl 9 1 + + tri_lcbcntl_mac perv_lcbctrl0( + .vdd(vdd), + .gnd(gnd), + .sg(sg_0), + .nclk(nclk), + .scan_in(gptr_scan_in), + .scan_diag_dc(tc_ac_scan_diag_dc), + .thold(gptr_sl_thold_0_int), + .clkoff_dc_b(prv_clkoff_dc_b), + .delay_lclkr_dc(prv_delay_lclkr_dc[0:4]), + .act_dis_dc(), + .mpw1_dc_b(prv_mpw1_dc_b[0:4]), + .mpw2_dc_b(prv_mpw2_dc_b[0]), + .scan_out(gptr_sio) + ); + + + tri_lcbcntl_mac perv_lcbctrl1( + .vdd(vdd), + .gnd(gnd), + .sg(sg_0), + .nclk(nclk), + .scan_in(gptr_sio), + .scan_diag_dc(tc_ac_scan_diag_dc), + .thold(gptr_sl_thold_0_int), + .clkoff_dc_b(), + .delay_lclkr_dc(prv_delay_lclkr_dc[5:9]), + .act_dis_dc(), + .mpw1_dc_b(prv_mpw1_dc_b[5:9]), + .mpw2_dc_b(prv_mpw2_dc_b[1]), + .scan_out(gptr_scan_out) + ); + + //Outputs + assign delay_lclkr_dc[0:9] = prv_delay_lclkr_dc[0:9]; + assign mpw1_dc_b[0:9] = prv_mpw1_dc_b[0:9]; + assign mpw2_dc_b[0:1] = prv_mpw2_dc_b[0:1]; + + //never disable act pins, they are used functionally + assign prv_act_dis = 1'b0; + assign act_dis = prv_act_dis; + assign clkoff_dc_b = prv_clkoff_dc_b; + + // Repower latch for repr scan ins/outs + + tri_lcbor repr_sl_lcbor_0( + .clkoff_b(prv_clkoff_dc_b), + .thold(repr_sl_thold_0), + .sg(sg_0), + .act_dis(prv_act_dis), + .force_t(repr_sl_force), + .thold_b(repr_sl_thold_0_b) + ); + + assign repr_in = 1'b0; + + tri_rlmreg_p #(.INIT(0), .WIDTH(1)) repr_rpwr_lat( + .nclk(nclk), + .act(tihi), + .force_t(repr_sl_force), + .d_mode(tiup), + .delay_lclkr(prv_delay_lclkr_dc[9]), + .mpw1_b(prv_mpw1_dc_b[9]), + .mpw2_b(prv_mpw2_dc_b[1]), + .thold_b(repr_sl_thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(repr_scan_in), + .scout(repr_scan_out), + //------------------------------------------- + .din(repr_in), + //------------------------------------------- + .dout(repr_UNUSED) + ); + +// Unused logic + assign spare_unused = pc_fu_func_slp_sl_thold_3[1]; + + +endmodule diff --git a/dev/verilog/work/fu_pic.v b/dev/verilog/work/fu_pic.v new file mode 100755 index 0000000..24b1d48 --- /dev/null +++ b/dev/verilog/work/fu_pic.v @@ -0,0 +1,2928 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" + +module fu_pic( + vdd, + gnd, + clkoff_b, + act_dis, + flush, + delay_lclkr, + mpw1_b, + mpw2_b, + sg_1, + thold_1, + fpu_enable, + nclk, + f_pic_si, + f_pic_so, + f_dcd_ex1_act, + f_dcd_ex1_aop_valid, + f_dcd_ex1_cop_valid, + f_dcd_ex1_bop_valid, + f_dcd_ex1_fsel_b, + f_dcd_ex1_from_integer_b, + f_dcd_ex1_to_integer_b, + f_dcd_ex1_rnd_to_int_b, + f_dcd_ex1_math_b, + f_dcd_ex1_est_recip_b, + f_dcd_ex1_est_rsqrt_b, + f_dcd_ex1_move_b, + f_dcd_ex1_compare_b, + f_dcd_ex1_prenorm_b, + f_dcd_ex1_frsp_b, + f_dcd_ex1_mv_to_scr_b, + f_dcd_ex1_mv_from_scr_b, + f_dcd_ex1_div_beg, + f_dcd_ex1_sqrt_beg, + f_dcd_ex1_force_excp_dis, + f_dcd_ex1_ftdiv, + f_dcd_ex1_ftsqrt, + f_fmt_ex3_ae_ge_54, + f_fmt_ex3_be_ge_54, + f_fmt_ex3_be_ge_2, + f_fmt_ex3_be_ge_2044, + f_fmt_ex3_tdiv_rng_chk, + f_dcd_ex1_sp, + f_dcd_ex1_uns_b, + f_dcd_ex1_word_b, + f_dcd_ex1_sp_conv_b, + f_dcd_ex1_pow2e_b, + f_dcd_ex1_log2e_b, + f_dcd_ex1_ordered_b, + f_dcd_ex1_sub_op_b, + f_dcd_ex1_op_rnd_v_b, + f_dcd_ex1_op_rnd_b, + f_dcd_ex1_inv_sign_b, + f_dcd_ex1_sign_ctl_b, + f_dcd_ex1_sgncpy_b, + f_byp_pic_ex2_a_sign, + f_byp_pic_ex2_c_sign, + f_byp_pic_ex2_b_sign, + f_dcd_ex1_thread, + f_dcd_ex1_nj_deno, + f_dcd_ex1_nj_deni, + f_cr2_ex2_fpscr_shadow_thr0, + f_cr2_ex2_fpscr_shadow_thr1, + f_fmt_ex2_sp_invalid, + f_fmt_ex2_a_zero, + f_fmt_ex2_a_expo_max, + f_fmt_ex2_a_frac_zero, + f_fmt_ex2_a_frac_msb, + f_fmt_ex2_c_zero, + f_fmt_ex2_c_expo_max, + f_fmt_ex2_c_frac_zero, + f_fmt_ex2_c_frac_msb, + f_fmt_ex2_b_zero, + f_fmt_ex2_b_expo_max, + f_fmt_ex2_b_frac_zero, + f_fmt_ex2_b_frac_msb, + f_fmt_ex2_prod_zero, + f_fmt_ex2_bexpu_le126, + f_fmt_ex2_gt126, + f_fmt_ex2_ge128, + f_fmt_ex2_inf_and_beyond_sp, + f_alg_ex2_sign_frmw, + f_fmt_ex3_pass_sign, + f_fmt_ex3_pass_msb, + f_fmt_ex2_b_imp, + f_fmt_ex2_b_frac_z32, + f_eie_ex3_wd_ov, + f_eie_ex3_dw_ov, + f_eie_ex3_wd_ov_if, + f_eie_ex3_dw_ov_if, + f_eie_ex3_lt_bias, + f_eie_ex3_eq_bias_m1, + f_alg_ex3_sel_byp, + f_alg_ex3_effsub_eac_b, + f_alg_ex3_sh_unf, + f_alg_ex3_sh_ovf, + f_mad_ex3_uc_a_expo_den, + f_mad_ex3_uc_a_expo_den_sp, + f_alg_ex4_int_fr, + f_alg_ex4_int_fi, + f_eov_ex5_may_ovf, + f_add_ex5_fpcc_iu, + f_add_ex5_sign_carry, + f_add_ex5_to_int_ovf_wd, + f_add_ex5_to_int_ovf_dw, + + f_fmt_ex3_be_den, + + f_pic_fmt_ex2_act, + f_pic_eie_ex2_act, + f_pic_mul_ex2_act, + f_pic_alg_ex2_act, + f_pic_cr2_ex2_act, + f_pic_tbl_ex2_act, + f_pic_ex2_ftdiv, + + f_pic_add_ex2_act_b, + f_pic_lza_ex2_act_b, + f_pic_eov_ex3_act_b, + f_pic_nrm_ex4_act_b, + f_pic_rnd_ex4_act_b, + f_pic_scr_ex3_act_b, + f_pic_ex2_rnd_to_int, + f_pic_ex2_fsel, + f_pic_ex2_frsp_ue1, + f_pic_ex3_frsp_ue1, + f_pic_ex3_ue1, + f_pic_ex2_effsub_raw, + f_pic_ex2_from_integer, + f_pic_ex2_sh_ovf_do, + f_pic_ex2_sh_ovf_ig_b, + f_pic_ex2_sh_unf_do, + f_pic_ex2_sh_unf_ig_b, + f_pic_ex2_log2e, + f_pic_ex2_pow2e, + f_pic_ex2_flush_en_sp, + f_pic_ex2_flush_en_dp, + f_pic_ex3_est_recip, + f_pic_ex3_est_rsqrt, + f_pic_ex3_force_sel_bexp, + f_pic_ex3_lzo_dis_prod, + f_pic_ex3_sp_b, + f_pic_ex3_sp_lzo, + f_pic_ex3_to_integer, + f_pic_ex3_prenorm, + f_pic_ex3_math_bzer_b, + f_pic_ex3_b_valid, + f_pic_ex3_rnd_nr, + f_pic_ex3_rnd_inf_ok, + f_pic_ex4_cmp_sgnneg, + f_pic_ex4_cmp_sgnpos, + f_pic_ex4_is_eq, + f_pic_ex4_is_gt, + f_pic_ex4_is_lt, + f_pic_ex4_is_nan, + f_pic_ex4_sp_b, + f_pic_ex4_sel_est, + f_dcd_ex1_uc_ft_pos, + f_dcd_ex1_uc_ft_neg, + f_dcd_ex1_uc_mid, + f_dcd_ex1_uc_end, + f_dcd_ex1_uc_special, + f_dcd_ex3_uc_zx, + f_dcd_ex3_uc_vxidi, + f_dcd_ex3_uc_vxzdz, + f_dcd_ex3_uc_vxsqrt, + f_dcd_ex3_uc_vxsnan, + f_mad_ex4_uc_special, + f_mad_ex4_uc_zx, + f_mad_ex4_uc_vxidi, + f_mad_ex4_uc_vxzdz, + f_mad_ex4_uc_vxsqrt, + f_mad_ex4_uc_vxsnan, + f_mad_ex4_uc_res_sign, + f_mad_ex4_uc_round_mode, + f_pic_ex5_byp_prod_nz, + f_pic_ex5_sel_est_b, + f_pic_ex2_nj_deni, + f_pic_ex5_nj_deno, + f_pic_ex5_oe, + f_pic_ex5_ov_en, + f_pic_ex5_ovf_en_oe0_b, + f_pic_ex5_ovf_en_oe1_b, + f_pic_ex5_quiet_b, + f_dcd_ex3_uc_inc_lsb, + f_dcd_ex3_uc_guard, + f_dcd_ex3_uc_sticky, + f_dcd_ex3_uc_gs_v, + f_pic_ex6_uc_inc_lsb, + f_pic_ex6_uc_guard, + f_pic_ex6_uc_sticky, + f_pic_ex6_uc_g_v, + f_pic_ex6_uc_s_v, + f_pic_ex5_rnd_inf_ok_b, + f_pic_ex5_rnd_ni_b, + f_pic_ex5_rnd_nr_b, + f_pic_ex5_sel_fpscr_b, + f_pic_ex5_sp_b, + f_pic_ex5_spec_inf_b, + f_pic_ex5_spec_sel_k_e, + f_pic_ex5_spec_sel_k_f, + f_pic_ex5_to_int_ov_all, + f_pic_ex5_to_integer_b, + f_pic_ex5_word_b, + f_pic_ex5_uns_b, + f_pic_ex5_ue, + f_pic_ex5_uf_en, + f_pic_ex5_unf_en_ue0_b, + f_pic_ex5_unf_en_ue1_b, + f_pic_ex6_en_exact_zero, + f_pic_ex6_frsp, + f_pic_ex6_compare_b, + f_pic_ex6_fi_pipe_v_b, + f_pic_ex6_fi_spec_b, + f_pic_ex6_flag_vxcvi_b, + f_pic_ex6_flag_vxidi_b, + f_pic_ex6_flag_vximz_b, + f_pic_ex6_flag_vxisi_b, + f_pic_ex6_flag_vxsnan_b, + f_pic_ex6_flag_vxsqrt_b, + f_pic_ex6_flag_vxvc_b, + f_pic_ex6_flag_vxzdz_b, + f_pic_ex6_flag_zx_b, + f_pic_ex6_fprf_hold_b, + f_pic_ex6_fprf_pipe_v_b, + f_pic_ex6_fprf_spec_b, + f_pic_ex6_fr_pipe_v_b, + f_pic_ex6_fr_spec_b, + f_pic_ex6_invert_sign, + f_pic_ex6_k_nan, + f_pic_ex6_k_inf, + f_pic_ex6_k_max, + f_pic_ex6_k_zer, + f_pic_ex6_k_one, + f_pic_ex6_k_int_maxpos, + f_pic_ex6_k_int_maxneg, + f_pic_ex6_k_int_zer, + f_pic_ex6_ox_pipe_v_b, + f_pic_ex6_round_sign, + f_pic_ex6_ux_pipe_v_b, + f_pic_ex6_scr_upd_move_b, + f_pic_ex6_scr_upd_pipe_b, + f_pic_ex6_fpr_wr_dis_b +); + inout vdd; + inout gnd; + input clkoff_b; // tiup + input act_dis; // ??tidn?? + input flush; // ??tidn?? + input [1:5] delay_lclkr; // tidn, + input [1:5] mpw1_b; // tidn, + input [0:1] mpw2_b; // tidn, + input sg_1; + input thold_1; + input fpu_enable; //dc_act + input [0:`NCLK_WIDTH-1] nclk; + + input f_pic_si; //perv + output f_pic_so; //perv + input f_dcd_ex1_act; //act + + input f_dcd_ex1_aop_valid; + input f_dcd_ex1_cop_valid; + input f_dcd_ex1_bop_valid; + + input f_dcd_ex1_fsel_b; // fsel + input f_dcd_ex1_from_integer_b; // fcfid (signed integer) + input f_dcd_ex1_to_integer_b; // fcti* (signed integer 32/64) + input f_dcd_ex1_rnd_to_int_b; // fcti* (signed integer 32/64) + input f_dcd_ex1_math_b; // fmul,fmad,fmsub,fadd,fsub,fnmsub,fnmadd + input f_dcd_ex1_est_recip_b; // fres + input f_dcd_ex1_est_rsqrt_b; // frsqrte + input f_dcd_ex1_move_b; // fmr,fneg,fabs,fnabs + input f_dcd_ex1_compare_b; // fcomp* + input f_dcd_ex1_prenorm_b; // prenorm ?? need + input f_dcd_ex1_frsp_b; // round-to-single-precision ?? need + input f_dcd_ex1_mv_to_scr_b; //mcrfs,mtfsf,mtfsfi,mtfsb0,mtfsb1 + input f_dcd_ex1_mv_from_scr_b; //mffs + input f_dcd_ex1_div_beg; + input f_dcd_ex1_sqrt_beg; + input f_dcd_ex1_force_excp_dis; // ve=ue=xe=ze=oe= 0 + input f_dcd_ex1_ftdiv; + input f_dcd_ex1_ftsqrt; + input f_fmt_ex3_ae_ge_54; + input f_fmt_ex3_be_ge_54; + input f_fmt_ex3_be_ge_2; + input f_fmt_ex3_be_ge_2044; + input f_fmt_ex3_tdiv_rng_chk; + + input f_dcd_ex1_sp; // single precision output + input f_dcd_ex1_uns_b; // convert unsigned + input f_dcd_ex1_word_b; // convert word/dw + input f_dcd_ex1_sp_conv_b; // convert sp/d + input f_dcd_ex1_pow2e_b; + input f_dcd_ex1_log2e_b; + input f_dcd_ex1_ordered_b; // fcompo + input f_dcd_ex1_sub_op_b; // fsub, fnmsub, fmsub (fcomp) + input f_dcd_ex1_op_rnd_v_b; // fctidz, fctiwz, prenorm, fri* + input [0:1] f_dcd_ex1_op_rnd_b; // + input f_dcd_ex1_inv_sign_b; // fnmsub fnmadd + input [0:1] f_dcd_ex1_sign_ctl_b; // 0:fmr/fneg 1:fneg/fnabs + input f_dcd_ex1_sgncpy_b; + + input f_byp_pic_ex2_a_sign; + input f_byp_pic_ex2_c_sign; + input f_byp_pic_ex2_b_sign; + + input [0:1] f_dcd_ex1_thread; + input f_dcd_ex1_nj_deno; // force output den to zero + input f_dcd_ex1_nj_deni; // force output den to zero + + input [0:7] f_cr2_ex2_fpscr_shadow_thr0; + input [0:7] f_cr2_ex2_fpscr_shadow_thr1; + + input f_fmt_ex2_sp_invalid; + input f_fmt_ex2_a_zero; + input f_fmt_ex2_a_expo_max; + input f_fmt_ex2_a_frac_zero; + input f_fmt_ex2_a_frac_msb; + input f_fmt_ex2_c_zero; + input f_fmt_ex2_c_expo_max; + input f_fmt_ex2_c_frac_zero; + input f_fmt_ex2_c_frac_msb; + input f_fmt_ex2_b_zero; + input f_fmt_ex2_b_expo_max; + input f_fmt_ex2_b_frac_zero; + input f_fmt_ex2_b_frac_msb; + input f_fmt_ex2_prod_zero; + input f_fmt_ex2_bexpu_le126; // log2e/pow2e special cases + input f_fmt_ex2_gt126; // log2e/pow2e special cases + input f_fmt_ex2_ge128; // log2e/pow2e special cases + input f_fmt_ex2_inf_and_beyond_sp; + input f_alg_ex2_sign_frmw; //?? from_int word is always unsigned (do not need this signal) + + input f_fmt_ex3_pass_sign; + input f_fmt_ex3_pass_msb; + input f_fmt_ex2_b_imp; + input f_fmt_ex2_b_frac_z32; + + input f_eie_ex3_wd_ov; + input f_eie_ex3_dw_ov; + input f_eie_ex3_wd_ov_if; + input f_eie_ex3_dw_ov_if; + input f_eie_ex3_lt_bias; + input f_eie_ex3_eq_bias_m1; + + input f_alg_ex3_sel_byp; + input f_alg_ex3_effsub_eac_b; + input f_alg_ex3_sh_unf; + input f_alg_ex3_sh_ovf; + + input f_mad_ex3_uc_a_expo_den; + input f_mad_ex3_uc_a_expo_den_sp; + + input f_alg_ex4_int_fr; + input f_alg_ex4_int_fi; + + input f_eov_ex5_may_ovf; + input [0:3] f_add_ex5_fpcc_iu; + input f_add_ex5_sign_carry; + input [0:1] f_add_ex5_to_int_ovf_wd; + input [0:1] f_add_ex5_to_int_ovf_dw; + + + + input f_fmt_ex3_be_den; + output f_pic_fmt_ex2_act; + output f_pic_eie_ex2_act; + output f_pic_mul_ex2_act; + output f_pic_alg_ex2_act; + output f_pic_cr2_ex2_act; + output f_pic_tbl_ex2_act; + output f_pic_ex2_ftdiv; + + + + + output f_pic_add_ex2_act_b; //set + output f_pic_lza_ex2_act_b; //set + output f_pic_eov_ex3_act_b; //set + output f_pic_nrm_ex4_act_b; //set + output f_pic_rnd_ex4_act_b; //set + output f_pic_scr_ex3_act_b; //set + + output f_pic_ex2_rnd_to_int; + output f_pic_ex2_fsel; + output f_pic_ex2_frsp_ue1; + output f_pic_ex3_frsp_ue1; + output f_pic_ex3_ue1; + output f_pic_ex2_effsub_raw; + output f_pic_ex2_from_integer; + output f_pic_ex2_sh_ovf_do; + output f_pic_ex2_sh_ovf_ig_b; + output f_pic_ex2_sh_unf_do; + output f_pic_ex2_sh_unf_ig_b; + + output f_pic_ex2_log2e; + output f_pic_ex2_pow2e; + + output f_pic_ex2_flush_en_sp; + output f_pic_ex2_flush_en_dp; + + output f_pic_ex3_est_recip; + output f_pic_ex3_est_rsqrt; + + output f_pic_ex3_force_sel_bexp; + output f_pic_ex3_lzo_dis_prod; + output f_pic_ex3_sp_b; + output f_pic_ex3_sp_lzo; + output f_pic_ex3_to_integer; + output f_pic_ex3_prenorm; + output f_pic_ex3_math_bzer_b; + output f_pic_ex3_b_valid; + output f_pic_ex3_rnd_nr; + output f_pic_ex3_rnd_inf_ok; + + output f_pic_ex4_cmp_sgnneg; + output f_pic_ex4_cmp_sgnpos; + output f_pic_ex4_is_eq; + output f_pic_ex4_is_gt; + output f_pic_ex4_is_lt; + output f_pic_ex4_is_nan; + output f_pic_ex4_sp_b; + output f_pic_ex4_sel_est; + + input f_dcd_ex1_uc_ft_pos; // force div/sqrt result poitive + input f_dcd_ex1_uc_ft_neg; // force div/sqrt result poitive + input f_dcd_ex1_uc_mid; + input f_dcd_ex1_uc_end; + input f_dcd_ex1_uc_special; + input f_dcd_ex3_uc_zx; + input f_dcd_ex3_uc_vxidi; + input f_dcd_ex3_uc_vxzdz; + input f_dcd_ex3_uc_vxsqrt; + input f_dcd_ex3_uc_vxsnan; + + output f_mad_ex4_uc_special; + output f_mad_ex4_uc_zx; + output f_mad_ex4_uc_vxidi; + output f_mad_ex4_uc_vxzdz; + output f_mad_ex4_uc_vxsqrt; + output f_mad_ex4_uc_vxsnan; + output f_mad_ex4_uc_res_sign; + output [0:1] f_mad_ex4_uc_round_mode; + + output f_pic_ex5_byp_prod_nz; + output f_pic_ex5_sel_est_b; + output f_pic_ex2_nj_deni; + output f_pic_ex5_nj_deno; + output f_pic_ex5_oe; + output f_pic_ex5_ov_en; + output f_pic_ex5_ovf_en_oe0_b; + output f_pic_ex5_ovf_en_oe1_b; + output f_pic_ex5_quiet_b; + + input f_dcd_ex3_uc_inc_lsb; + input f_dcd_ex3_uc_guard; + input f_dcd_ex3_uc_sticky; + input f_dcd_ex3_uc_gs_v; + + output f_pic_ex6_uc_inc_lsb; + output f_pic_ex6_uc_guard; + output f_pic_ex6_uc_sticky; + output f_pic_ex6_uc_g_v; + output f_pic_ex6_uc_s_v; + + output f_pic_ex5_rnd_inf_ok_b; + output f_pic_ex5_rnd_ni_b; + output f_pic_ex5_rnd_nr_b; + output f_pic_ex5_sel_fpscr_b; + output f_pic_ex5_sp_b; + output f_pic_ex5_spec_inf_b; + output f_pic_ex5_spec_sel_k_e; + output f_pic_ex5_spec_sel_k_f; + + output f_pic_ex5_to_int_ov_all; + + output f_pic_ex5_to_integer_b; + output f_pic_ex5_word_b; + output f_pic_ex5_uns_b; + output f_pic_ex5_ue; + output f_pic_ex5_uf_en; + output f_pic_ex5_unf_en_ue0_b; + output f_pic_ex5_unf_en_ue1_b; + + output f_pic_ex6_en_exact_zero; + output f_pic_ex6_frsp; + output f_pic_ex6_compare_b; + output f_pic_ex6_fi_pipe_v_b; + output f_pic_ex6_fi_spec_b; + output f_pic_ex6_flag_vxcvi_b; + output f_pic_ex6_flag_vxidi_b; + output f_pic_ex6_flag_vximz_b; + output f_pic_ex6_flag_vxisi_b; + output f_pic_ex6_flag_vxsnan_b; + output f_pic_ex6_flag_vxsqrt_b; + output f_pic_ex6_flag_vxvc_b; + output f_pic_ex6_flag_vxzdz_b; + output f_pic_ex6_flag_zx_b; + output f_pic_ex6_fprf_hold_b; + output f_pic_ex6_fprf_pipe_v_b; + output [0:4] f_pic_ex6_fprf_spec_b; + output f_pic_ex6_fr_pipe_v_b; + output f_pic_ex6_fr_spec_b; + output f_pic_ex6_invert_sign; + + output f_pic_ex6_k_nan; + output f_pic_ex6_k_inf; + output f_pic_ex6_k_max; + output f_pic_ex6_k_zer; + output f_pic_ex6_k_one; + output f_pic_ex6_k_int_maxpos; + output f_pic_ex6_k_int_maxneg; + output f_pic_ex6_k_int_zer; + output f_pic_ex6_ox_pipe_v_b; + output f_pic_ex6_round_sign; + output f_pic_ex6_ux_pipe_v_b; + output f_pic_ex6_scr_upd_move_b; + output f_pic_ex6_scr_upd_pipe_b; + output f_pic_ex6_fpr_wr_dis_b; + + // ENTITY + + + parameter tiup = 1'b1; + parameter tidn = 1'b0; + + wire thold_0_b; + wire thold_0; + wire force_t; + wire sg_0; + + wire ex1_act; + wire ex2_act; + wire ex3_act; + wire ex4_act; + wire ex5_act; + + wire ex2_act_add; + wire ex2_act_lza; + wire ex3_act_eov; + wire ex3_act_scr; + wire ex4_act_nrm; + wire ex4_act_rnd; + (* analysis_not_referenced="TRUE" *) // spare_unused + wire [0:3] spare_unused; + wire [0:20] act_so; + wire [0:20] act_si; + + wire [0:44] ex2_ctl_so; + wire [0:44] ex2_ctl_si; + wire [0:56] ex3_ctl_so; + wire [0:56] ex3_ctl_si; + wire [0:33] ex4_ctl_so; + wire [0:33] ex4_ctl_si; + wire [0:28] ex5_ctl_so; + wire [0:28] ex5_ctl_si; + wire [0:17] ex3_flg_so; + wire [0:17] ex3_flg_si; + wire [0:7] ex4_scr_so; + wire [0:7] ex4_scr_si; + wire [0:46] ex4_flg_so; + wire [0:46] ex4_flg_si; + wire [0:7] ex5_scr_so; + wire [0:7] ex5_scr_si; + wire [0:37] ex5_flg_so; + wire [0:37] ex5_flg_si; + wire [0:41] ex6_flg_so; + wire [0:41] ex6_flg_si; + + wire ex5_may_ovf; + wire ex6_unused; + wire ex3_a_sign; + wire ex4_pass_nan; + wire ex3_pass_x; + + wire [0:1] ex2_rnd_fpscr; + wire [0:1] ex3_rnd_fpscr; + wire [0:1] ex4_rnd_fpscr; + wire ex2_div_sign; + wire ex3_div_sign; + wire ex4_div_sign; + wire [0:1] ex1_thread; + wire ex4_ve; + wire ex4_oe; + wire ex4_ue; + wire ex4_ze; + wire ex4_xe; + wire ex4_nonieee; + wire ex4_rnd0; + wire ex4_rnd1; + wire ex5_ve; + wire ex5_oe; + wire ex5_ue; + wire ex5_ze; + wire ex5_xe; + wire ex5_nonieee; + wire ex5_rnd0; + wire ex5_rnd1; + wire ex3_toint_nan_sign; + + wire ex2_uc_ft_neg; + wire ex3_uc_ft_neg; + wire ex4_uc_ft_neg; + wire ex2_uc_ft_pos; + wire ex3_uc_ft_pos; + wire ex4_uc_ft_pos; + wire ex2_a_inf; + wire ex2_a_nan; + wire ex2_a_sign; + wire ex2_b_inf; + wire ex2_b_nan; + wire ex2_b_sign; + wire ex2_b_sign_adj; + wire ex2_b_sign_adj_x; + wire ex2_b_sign_alt; + wire ex2_a_valid; + wire ex2_c_valid; + wire ex2_b_valid; + wire ex2_c_inf; + wire ex2_sp_invalid; + wire ex3_sp_invalid; + wire ex2_c_nan; + wire ex2_c_sign; + wire ex2_compare; + wire ex2_div_beg; + wire ex2_est_recip; + wire ex2_est_rsqrt; + wire ex2_op_rnd_v; + wire [0:1] ex2_op_rnd; + wire ex2_from_integer; + wire ex2_frsp; + wire ex2_fsel; + wire ex2_inv_sign; + wire ex2_lzo_dis; + wire ex2_uc_mid; + wire ex3_uc_mid; + wire ex4_uc_mid; + wire ex5_uc_mid; + wire ex2_math; + wire ex2_move; + wire ex2_mv_from_scr; + wire ex2_mv_to_scr; + wire ex2_p_sign; + wire ex2_prenorm; + wire [0:1] ex2_sign_ctl; + wire ex2_sp; + wire ex2_sp_b; + wire ex2_sqrt_beg; + wire ex2_sub_op; + wire ex2_to_integer; + wire ex2_ordered; + wire ex2_word; + wire ex1_uns; + wire ex1_sp_conv; + wire ex2_uns; + wire ex3_uns; + wire ex4_uns; + wire ex5_uns; + wire ex2_sp_conv; + wire ex3_a_frac_msb; + wire ex3_a_inf; + wire ex3_a_nan; + wire ex3_a_zero; + wire ex3_any_inf; + wire ex3_b_frac_msb; + wire ex3_b_inf; + wire ex3_b_nan; + wire ex3_b_sign_adj; + wire ex3_to_int_uns_neg; + wire ex4_to_int_uns_neg; + wire ex5_to_int_uns_neg; + wire ex3_wd_ov_x; + wire ex3_dw_ov_x; + wire ex3_b_sign_alt; + wire ex3_b_zero; + wire ex4_b_zero; + wire ex3_c_frac_msb; + wire ex3_c_inf; + wire ex3_c_nan; + wire ex3_c_zero; + wire ex3_cmp_sgnneg; + wire ex3_cmp_sgnpos; + wire ex3_cmp_zero; + wire ex3_compare; + wire ex3_div_beg; + wire ex4_div_beg; + wire ex5_div_beg; + wire ex3_est_recip; + wire ex3_est_rsqrt; + wire ex3_rnd_dis; + wire [0:1] ex3_op_rnd; + wire ex3_from_integer; + wire ex3_frsp; + wire ex3_fsel; + wire ex3_gen_inf; + wire ex3_gen_max; + wire ex3_gen_nan; + wire ex3_gen_zero; + wire ex3_inf_sign; + wire ex3_inv_sign; + wire ex3_is_eq; + wire ex3_is_gt; + wire ex3_is_lt; + wire ex3_is_nan; + wire ex3_lzo_dis; + wire ex3_math; + wire ex3_move; + wire ex3_mv_from_scr; + wire ex3_mv_to_scr; + wire ex3_neg_sqrt_nz; + wire ex3_p_inf; + wire ex3_p_sign; + wire ex3_p_zero; + wire ex3_pass_en; + wire ex3_pass_nan; + wire ex3_prenorm; + wire ex3_quiet; + wire ex3_rnd0; + wire ex3_rnd1; + wire ex3_rnd_inf_ok; + wire ex3_rnd_nr; + wire ex3_sp; + wire ex3_sp_notrunc; + wire ex3_sp_o_frsp; + wire ex3_spec_sign; + wire ex3_sqrt_beg; + wire ex4_sqrt_beg; + wire ex5_sqrt_beg; + wire ex3_sub_op; + wire ex3_to_integer; + wire ex3_ue; + wire ex3_ordered; + wire ex3_nonieee; + wire ex3_ze; + wire ex3_ve; + wire ex3_oe; + wire ex3_xe; + wire ex3_vxcvi; + wire ex3_vxidi; + wire ex3_vximz; + wire ex3_vxisi; + wire ex3_vxsnan; + wire ex3_vxsqrt; + wire ex3_vxvc; + wire ex3_vxzdz; + wire ex3_word; + wire ex3_zx; + wire ex4_b_sign_adj; + wire ex4_b_sign_alt; + wire ex4_cmp_sgnneg; + wire ex4_cmp_sgnpos; + wire ex4_compare; + wire ex4_dw_ov; + wire ex4_dw_ov_if; + wire ex4_effsub_eac; + wire ex5_effsub_eac; + wire ex4_est_recip; + wire ex4_est_rsqrt; + wire ex4_rnd_dis; + wire ex4_from_integer; + wire ex4_frsp; + wire ex4_fsel; + wire ex4_gen_inf; + wire ex4_gen_inf_mutex; + wire ex4_gen_max_mutex; + wire ex4_gen_max; + wire ex4_gen_nan; + wire ex4_gen_nan_mutex; + wire ex4_gen_zer_mutex; + wire ex4_gen_zero; + wire ex4_inv_sign; + wire ex4_is_eq; + wire ex4_is_gt; + wire ex4_is_lt; + wire ex4_is_nan; + wire ex4_math; + wire ex4_move; + wire ex4_mv_from_scr; + wire ex4_mv_to_scr; + wire ex4_oe_x; + wire ex4_ov_en; + wire ex4_ovf_en_oe0; + wire ex4_ovf_en_oe1; + wire ex4_p_sign; + wire ex4_p_sign_may; + wire ex4_prenorm; + wire ex4_quiet; + wire ex4_sel_byp; + wire ex4_sh_ovf; + wire ex4_sh_unf; + wire ex4_sign_nco; + wire ex4_sign_pco; + wire ex4_sp; + wire ex4_sp_x; + wire ex4_sp_conv; + wire ex3_sp_conv; + wire ex4_spec_sel_e; + wire ex4_spec_sel_f; + wire ex4_spec_sign; + wire ex4_spec_sign_x; + wire ex4_spec_sign_sel; + wire ex4_sub_op; + wire ex4_to_int_dw; + wire ex4_to_int_ov; + wire ex4_to_int_ov_if; + wire ex4_to_int_wd; + wire ex4_to_integer; + wire ex4_ue_x; + wire ex4_uf_en; + wire ex4_unf_en_oe0; + wire ex4_unf_en_oe1; + wire ex4_vxcvi; + wire ex4_vxidi; + wire ex4_vximz; + wire ex4_vxisi; + wire ex4_vxsnan; + wire ex4_vxsqrt; + wire ex4_vxvc; + wire ex4_vxzdz; + wire ex4_wd_ov; + wire ex4_wd_ov_if; + wire ex4_word; + wire ex4_word_to; + wire ex4_zx; + wire ex5_compare; + wire ex6_compare; + wire ex5_en_exact_zero; + wire ex5_est_recip; + wire ex5_est_rsqrt; + wire ex5_rnd_dis; + wire ex5_fpr_wr_dis; + wire ex5_fprf_pipe_v; + wire [0:4] ex5_fprf_spec; + wire [0:4] ex5_fprf_spec_x; + wire ex5_fr_pipe_v; + wire ex5_from_integer; + wire ex5_frsp; + wire ex6_frsp; + wire ex5_fsel; + wire ex5_gen_inf; + wire ex5_gen_inf_sign; + wire ex5_gen_max; + wire ex5_gen_nan; + wire ex5_pass_nan; + wire ex5_gen_zero; + wire ex5_inv_sign; + wire ex5_invert_sign; + wire ex5_k_max_fp; + wire ex5_math; + wire ex5_move; + wire ex5_mv_from_scr; + wire ex5_mv_to_scr; + wire ex5_ov_en; + wire ex5_ovf_en_oe0; + wire ex5_ovf_en_oe1; + wire ex5_ox_pipe_v; + wire ex5_prenorm; + wire ex5_quiet; + wire ex5_rnd_en; + wire ex5_rnd_inf_ok; + wire ex5_rnd_pi; + wire ex5_rnd_ni; + wire ex5_rnd_nr; + wire ex5_rnd_zr; + wire ex5_rnd_nr_ok; + wire ex5_round_sign; + wire ex5_round_sign_x; + wire ex5_scr_upd_move; + wire ex5_scr_upd_pipe; + wire ex5_sel_spec_e; + wire ex5_sel_spec_f; + wire ex5_sel_spec_fr; + wire ex5_sign_nco; + wire ex5_sign_pco; + wire ex5_sign_nco_x; + wire ex5_sign_pco_x; + wire ex5_sign_nco_xx; + wire ex5_sign_pco_xx; + wire ex5_sp; + wire ex5_spec_sel_e; + wire ex5_spec_sel_f; + wire ex5_sub_op; + wire ex5_to_int_dw; + wire ex5_to_int_ov; + wire ex5_to_int_ov_if; + wire ex5_to_int_wd; + wire ex5_to_integer; + wire ex5_uf_en; + wire ex5_unf_en_oe0; + wire ex5_unf_en_oe1; + wire ex5_upd_fpscr_ops; + wire ex5_vx; + wire ex5_vxidi; + wire ex5_vximz; + wire ex5_vxisi; + wire ex5_vxsnan; + wire ex5_vxsqrt; + wire ex5_vxvc; + wire ex5_vxcvi; + wire ex5_vxcvi_ov; + wire ex5_to_int_ov_all_x; + wire ex5_to_int_ov_all; + wire ex5_to_int_ov_all_gt; + wire ex5_to_int_k_sign; + wire ex5_vxzdz; + wire ex5_word; + wire ex5_zx; + wire ex6_en_exact_zero; + wire ex6_fpr_wr_dis; + wire ex6_fprf_pipe_v; + wire [0:4] ex6_fprf_spec; + wire ex6_fr_pipe_v; + wire ex6_invert_sign; + wire ex6_ox_pipe_v; + wire ex6_round_sign; + wire ex6_scr_upd_move; + wire ex6_scr_upd_pipe; + wire ex6_vxcvi; + wire ex6_vxidi; + wire ex6_vximz; + wire ex6_vxisi; + wire ex6_vxsnan; + wire ex6_vxsqrt; + wire ex6_vxvc; + wire ex6_vxzdz; + wire ex6_zx; + wire ex6_k_nan; + wire ex6_k_inf; + wire ex6_k_max; + wire ex6_k_zer; + wire ex6_k_int_maxpos; + wire ex6_k_int_maxneg; + wire ex6_k_int_zer; + wire ex5_gen_any; + wire ex5_k_nan; + wire ex5_k_inf; + wire ex5_k_max; + wire ex5_k_zer; + wire ex5_k_int_maxpos; + wire ex5_k_int_maxneg; + wire ex5_k_int_zer; + wire ex5_k_nan_x; + wire ex5_k_inf_x; + wire ex5_k_max_x; + wire ex5_k_zer_x; + wire ex3_a_valid; + wire ex3_c_valid; + wire ex3_b_valid; + wire ex3_prod_zero; + wire ex5_byp_prod_nz; + wire ex4_byp_prod_nz; + wire ex4_byp_prod_nz_sub; + wire ex4_a_valid; + wire ex4_c_valid; + wire ex4_b_valid; + wire ex4_prod_zero; + wire ex5_int_fr; + wire ex5_int_fi; + wire ex5_fi_spec; + wire ex5_fr_spec; + wire ex6_fi_spec; + wire ex6_fr_spec; + wire ex3_toint_genz; + wire ex3_a_snan; + wire ex3_b_snan; + wire ex3_c_snan; + wire ex3_a_qnan; + wire ex3_b_qnan; + wire ex3_nan_op_grp1; + wire ex3_nan_op_grp2; + wire ex3_compo; + wire ex6_fprf_hold; + wire ex5_fprf_hold; + wire ex5_fprf_hold_ops; + wire ex2_bf_10000; + wire ex3_bf_10000; + wire ex4_bf_10000; + + wire ex2_rnd_to_int; + wire ex3_rnd_to_int; + wire ex4_rnd_to_int; + wire ex5_rnd_to_int; + wire ex4_lt_bias; + wire ex4_eq_bias_m1; + wire ex4_gen_rnd2int; + wire ex4_gen_one_rnd2int; + wire ex4_gen_zer_rnd2int; + wire ex3_gen_one; + wire ex4_gen_one; + wire ex4_gen_one_mutex; + wire ex5_gen_one; + wire ex5_k_one; + wire ex6_k_one; + wire ex5_k_one_x; + wire ex4_rnd2int_up; + wire ex5_sel_est; + wire ex2_ve; + wire ex2_oe; + wire ex2_ue; + wire ex2_ze; + wire ex2_xe; + wire ex2_nonieee; + wire ex2_rnd0; + wire ex2_rnd1; + wire ex2_rnd_dis; + wire ex1_fsel; + wire ex1_from_integer; + wire ex1_to_integer; + wire ex1_math; + wire ex1_est_recip; + wire ex1_est_rsqrt; + wire ex1_move; + wire ex1_compare; + wire ex1_prenorm; + wire ex1_frsp; + wire ex1_mv_to_scr; + wire ex1_mv_from_scr; + wire ex1_div_beg; + wire ex1_sqrt_beg; + wire ex1_sp; + wire ex1_word; + wire ex1_ordered; + wire ex1_sub_op; + wire ex1_op_rnd_v; + wire ex1_inv_sign; + wire [0:1] ex1_sign_ctl; + wire ex1_sgncpy; + wire ex2_sgncpy; + wire [0:1] ex1_op_rnd; + wire ex1_rnd_to_int; + wire ex3_effsub_eac; + wire ex2_flush_dis_dp; + wire ex2_flush_dis_sp; + wire ex5_to_integer_ken; + wire ex1_log2e; + wire ex1_pow2e; + wire ex2_log2e; + wire ex2_pow2e; + wire ex3_log2e; + wire ex3_pow2e; + wire ex4_log2e; + wire ex4_pow2e; + wire ex5_log2e; + wire ex5_pow2e; + wire ex3_log_ofzero; + wire ex3_bexpu_le126; + wire ex3_gt126; + wire ex3_ge128; + wire ex3_gen_nan_log; + wire ex3_gen_inf_log; + wire ex3_gen_inf_pow; + wire ex3_gen_zero_pow; + wire ex2_ovf_unf_dis; + wire ex3_ovf_unf_dis; + wire ex4_ovf_unf_dis; + wire ex5_ovf_unf_dis; + wire ex3_exact_zero_sign; + wire ex3_rnd_ni; + wire ex3_gen_inf_sq; + wire ex3_gen_inf_dv; + wire ex3_gen_zer_sq; + wire ex3_gen_zer_dv; + wire ex3_gen_nan_sq; + wire ex3_gen_nan_dv; + wire ex3_prenorm_special; + wire ex3_prenorm_sign; + + wire ex4_uc_inc_lsb; + wire ex5_uc_inc_lsb; + wire ex6_uc_inc_lsb; + wire ex4_uc_guard; + wire ex5_uc_guard; + wire ex6_uc_guard; + wire ex4_uc_sticky; + wire ex5_uc_sticky; + wire ex6_uc_sticky; + wire ex4_uc_gs_v; + wire ex5_uc_gs_v; + wire ex5_uc_s_v; + wire ex5_uc_g_v; + wire ex6_uc_s_v; + wire ex6_uc_g_v; + wire ex3_uc_g_ig; + wire ex4_uc_g_ig; + wire ex5_uc_g_ig; + wire ex2_force_excp_dis; + wire ex1_uc_end_nspec; + wire ex2_uc_end_nspec; + wire ex1_uc_end_spec; + wire ex2_uc_end_spec; + wire ex3_uc_end_spec; + wire ex4_uc_end_spec; + wire ex5_uc_end_spec; + (* analysis_not_referenced="TRUE" *) // unused + wire unused; + wire ex1_nj_deno_x; + wire ex2_nj_deno; + wire ex3_nj_deno; + wire ex4_nj_deno; + wire ex4_nj_deno_x; + wire ex5_nj_deno; + wire ex1_nj_deni_x; + wire ex2_nj_deni; + wire ex1_den_ok; + wire ex3_gen_nan_pow; + wire ex3_inf_and_beyond_sp; + wire ex2_ftdiv; + wire ex2_ftsqrt; + wire ex3_ftdiv; + wire ex3_ftsqrt; + wire ex3_accuracy; + wire ex3_b_imp; + + wire [0:7] ex2_fpscr_shadow; + wire [0:1] ex2_thread; + + ////################################################################ + ////# map block attributes + ////################################################################ + + + assign unused = ex4_byp_prod_nz_sub | ex5_sel_spec_f | + ex1_act | + ex3_op_rnd[0] | ex3_op_rnd[1] | ex4_b_sign_adj | ex4_b_valid | + ex4_gen_max | ex4_sh_unf | ex4_sh_ovf | ex5_nonieee | ex5_xe | ex5_fsel | ex5_move | + ex5_prenorm | ex5_div_beg | ex5_sqrt_beg | ex5_sub_op | ex5_log2e | ex5_pow2e | ex6_unused; //lat-- + + ////################################################################ + ////# pervasive + ////################################################################ + + + tri_plat thold_reg_0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(flush), + .din(thold_1), + .q(thold_0) + ); + + + tri_plat sg_reg_0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(flush), + .din(sg_1), + .q(sg_0) + ); + + + tri_lcbor lcbor_0( + .clkoff_b(clkoff_b), + .thold(thold_0), + .sg(sg_0), + .act_dis(act_dis), + .force_t(force_t), + .thold_b(thold_0_b) + ); + + ////################################################################ + ////# act + ////################################################################ + + // act_lat: entity WORK.tri_rlmreg_p generic map (width=> 22, expand_type => expand_type) port map ( + + tri_rlmreg_p #(.WIDTH(21)) act_lat( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[4]), + .mpw1_b(mpw1_b[4]), + .mpw2_b(mpw2_b[0]), + .act(fpu_enable), //tiup + .thold_b(thold_0_b), //tiup, + .sg(sg_0), //tidn, + .scout(act_so), + .scin(act_si), + //----------------- + .din({spare_unused[0], + spare_unused[1], + tiup, //is2_act, + f_dcd_ex1_act, //is2_act, + f_dcd_ex1_act, //is2_act, + f_dcd_ex1_act, //is2_act, + f_dcd_ex1_act, //is2_act, + tiup, //is2_act, + f_dcd_ex1_act, //rf0_act, + f_dcd_ex1_act, //rf0_act, + f_dcd_ex1_act, //ex1_act, + f_dcd_ex1_act, //ex1_act, + ex2_act, //ex1_act, + ex2_act, + ex2_act, + ex3_act, + ex3_act, + ex3_act, + ex4_act, + spare_unused[2], + spare_unused[3]}), + //----------------- + .dout({spare_unused[0], + spare_unused[1], + f_pic_fmt_ex2_act , + f_pic_eie_ex2_act , + f_pic_mul_ex2_act , + f_pic_alg_ex2_act , + f_pic_cr2_ex2_act , + ex1_act, + f_pic_tbl_ex2_act , + ex2_act, + ex2_act_add, + ex2_act_lza, + ex3_act, + ex3_act_eov, + ex3_act_scr, + ex4_act, + ex4_act_nrm, + ex4_act_rnd, + ex5_act, + spare_unused[2], + spare_unused[3]}) + ); + + + assign f_pic_add_ex2_act_b = (~ex2_act_add); + assign f_pic_lza_ex2_act_b = (~ex2_act_lza); + assign f_pic_eov_ex3_act_b = (~ex3_act_eov); + assign f_pic_scr_ex3_act_b = (~ex3_act_scr); + assign f_pic_nrm_ex4_act_b = (~ex4_act_nrm); + assign f_pic_rnd_ex4_act_b = (~ex4_act_rnd); + + ////################################################################ + ////# ex1 logic + ////################################################################ + + ////################################################################ + ////# ex2 latches + ////################################################################ + + assign ex1_fsel = (~f_dcd_ex1_fsel_b); + assign ex1_from_integer = (~f_dcd_ex1_from_integer_b); + assign ex1_to_integer = (~f_dcd_ex1_to_integer_b); + assign ex1_math = (~f_dcd_ex1_math_b); + assign ex1_est_recip = (~f_dcd_ex1_est_recip_b); + assign ex1_est_rsqrt = (~f_dcd_ex1_est_rsqrt_b); + assign ex1_move = (~f_dcd_ex1_move_b); + assign ex1_compare = (~f_dcd_ex1_compare_b); + assign ex1_prenorm = (~(f_dcd_ex1_prenorm_b)) | f_dcd_ex1_div_beg | f_dcd_ex1_sqrt_beg; + assign ex1_frsp = (~f_dcd_ex1_frsp_b); + assign ex1_mv_to_scr = (~f_dcd_ex1_mv_to_scr_b); + assign ex1_mv_from_scr = (~f_dcd_ex1_mv_from_scr_b); + assign ex1_div_beg = f_dcd_ex1_div_beg; + assign ex1_sqrt_beg = f_dcd_ex1_sqrt_beg; + assign ex1_sp = (~f_dcd_ex1_sp); + assign ex1_word = (~f_dcd_ex1_word_b); + assign ex1_uns = (~f_dcd_ex1_uns_b); + assign ex1_sp_conv = (~f_dcd_ex1_sp_conv_b); + assign ex1_ordered = (~f_dcd_ex1_ordered_b); + assign ex1_sub_op = (~f_dcd_ex1_sub_op_b); + assign ex1_op_rnd_v = (~f_dcd_ex1_op_rnd_v_b); + assign ex1_inv_sign = (~f_dcd_ex1_inv_sign_b); + assign ex1_sign_ctl[0] = (~f_dcd_ex1_sign_ctl_b[0]); + assign ex1_sign_ctl[1] = (~f_dcd_ex1_sign_ctl_b[1]); + assign ex1_sgncpy = (~f_dcd_ex1_sgncpy_b); + assign ex1_op_rnd[0] = (~f_dcd_ex1_op_rnd_b[0]); + assign ex1_op_rnd[1] = (~f_dcd_ex1_op_rnd_b[1]); + assign ex1_rnd_to_int = (~f_dcd_ex1_rnd_to_int_b); + assign ex1_log2e = (~f_dcd_ex1_log2e_b); + assign ex1_pow2e = (~f_dcd_ex1_pow2e_b); + assign ex1_uc_end_nspec = f_dcd_ex1_uc_end & (~f_dcd_ex1_uc_special); + assign ex1_uc_end_spec = f_dcd_ex1_uc_end & f_dcd_ex1_uc_special; + + assign ex1_den_ok = ex1_move | ex1_mv_to_scr | ex1_mv_from_scr | ex1_fsel | f_dcd_ex1_uc_mid; + + assign ex1_nj_deno_x = f_dcd_ex1_nj_deno & (~f_dcd_ex1_div_beg) & (~f_dcd_ex1_sqrt_beg) & (~ex1_to_integer) & (~ex1_den_ok); // do not want denorm outputs in the middle of a divide + + assign ex1_nj_deni_x = f_dcd_ex1_nj_deni & (~ex1_den_ok); // do not want denorm outputs in the middle of a divide + + assign ex1_thread = f_dcd_ex1_thread; + + + tri_rlmreg_p #(.WIDTH(45)) ex2_ctl_lat( + .vd(vdd), + .gd(gnd), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[1]), + .mpw1_b(mpw1_b[1]), + .mpw2_b(mpw2_b[0]), + .nclk(nclk), + .act(f_dcd_ex1_act), + .thold_b(thold_0_b), + .sg(sg_0), + .scout(ex2_ctl_so), + .scin(ex2_ctl_si), + //----------------- + .din({ ex1_fsel, + ex1_from_integer, + ex1_to_integer, + ex1_math, + ex1_est_recip, + ex1_est_rsqrt, + ex1_move, + ex1_compare, + ex1_prenorm, + ex1_frsp, + ex1_mv_to_scr, + ex1_mv_from_scr, + ex1_div_beg, + ex1_sqrt_beg, + ex1_sp, + ex1_word, + ex1_ordered, + ex1_sub_op, + f_dcd_ex1_uc_mid, + ex1_op_rnd_v, + ex1_inv_sign, + ex1_sign_ctl[0], + ex1_sign_ctl[1], + f_dcd_ex1_aop_valid, + f_dcd_ex1_cop_valid, + f_dcd_ex1_bop_valid, + ex1_op_rnd[0], + ex1_op_rnd[1], + ex1_rnd_to_int, + ex1_uns, + ex1_sp_conv, + ex1_sgncpy, + ex1_log2e, + ex1_pow2e, + f_dcd_ex1_uc_ft_pos, + f_dcd_ex1_uc_ft_neg, + f_dcd_ex1_force_excp_dis, + ex1_uc_end_nspec, + ex1_uc_end_spec, + ex1_nj_deno_x, + ex1_nj_deni_x, + f_dcd_ex1_ftdiv, + f_dcd_ex1_ftsqrt, + ex1_thread}), + //----------------- + .dout({ ex2_fsel, + ex2_from_integer, + ex2_to_integer, + ex2_math, + ex2_est_recip, + ex2_est_rsqrt, + ex2_move, + ex2_compare, + ex2_prenorm, + ex2_frsp, + ex2_mv_to_scr, + ex2_mv_from_scr, + ex2_div_beg, + ex2_sqrt_beg, + ex2_sp_b, + ex2_word, + ex2_ordered, + ex2_sub_op, + ex2_uc_mid, + ex2_op_rnd_v, + ex2_inv_sign, + ex2_sign_ctl[0], + ex2_sign_ctl[1], + ex2_a_valid, + ex2_c_valid, + ex2_b_valid, + ex2_op_rnd[0], + ex2_op_rnd[1], + ex2_rnd_to_int, + ex2_uns, + ex2_sp_conv, + ex2_sgncpy, + ex2_log2e, + ex2_pow2e, + ex2_uc_ft_pos, + ex2_uc_ft_neg, + ex2_force_excp_dis, + ex2_uc_end_nspec, + ex2_uc_end_spec, + ex2_nj_deno, + ex2_nj_deni, + ex2_ftdiv, + ex2_ftsqrt, + ex2_thread}) + ); + + assign f_pic_ex2_nj_deni = ex2_nj_deni; + + assign ex2_ovf_unf_dis = ex2_uc_mid | ex2_prenorm | ex2_move | ex2_fsel | ex2_mv_to_scr | ex2_mv_from_scr; + + assign ex2_fpscr_shadow = (f_cr2_ex2_fpscr_shadow_thr0 & {8{ex2_thread[0]}}) | + (f_cr2_ex2_fpscr_shadow_thr1 & {8{ex2_thread[1]}}); + + assign ex2_ve = ex2_fpscr_shadow[0] & (~ex2_force_excp_dis); // 24 + assign ex2_oe = ex2_fpscr_shadow[1] & (~ex2_force_excp_dis); // 25 + assign ex2_ue = ex2_fpscr_shadow[2] & (~ex2_force_excp_dis); // 26 + assign ex2_ze = ex2_fpscr_shadow[3] & (~ex2_force_excp_dis); // 27 + assign ex2_xe = ex2_fpscr_shadow[4] & (~ex2_force_excp_dis); // 28 + assign ex2_nonieee = ex2_fpscr_shadow[5]; // 29 + + assign ex2_rnd_fpscr[0:1] = ex2_fpscr_shadow[6:7]; + + assign ex2_rnd0 = (ex2_fpscr_shadow[6] & (~ex2_op_rnd_v)) | (ex2_op_rnd[0] & ex2_op_rnd_v); // 30 + assign ex2_rnd1 = (ex2_fpscr_shadow[7] & (~ex2_op_rnd_v)) | (ex2_op_rnd[1] & ex2_op_rnd_v); // 31 + assign ex2_rnd_dis = tidn & f_fmt_ex2_prod_zero & ex2_nj_deni; // force truncate "01" + + assign f_pic_ex2_rnd_to_int = ex2_rnd_to_int; //output-- + + // denorm input forced to zero + assign ex2_flush_dis_sp = ex2_uc_mid | ex2_fsel | ex2_log2e | ex2_pow2e | ex2_prenorm | ex2_move | ex2_to_integer | ex2_frsp; + + assign ex2_flush_dis_dp = ex2_flush_dis_sp | ex2_from_integer | ex2_ftdiv | ex2_ftsqrt | ex2_mv_to_scr; + + assign f_pic_ex2_flush_en_sp = (~ex2_flush_dis_sp); + assign f_pic_ex2_flush_en_dp = (~ex2_flush_dis_dp); + + assign f_pic_ex2_log2e = ex2_log2e; //output-- + assign f_pic_ex2_pow2e = ex2_pow2e; //output-- + + ////################################################################ + ////# ex2 logic + ////################################################################ + // fmr/fneg/fabs/fnabs + // fsel + // mffs + // mcrfs, mtcrf, mtfs* + // prenorm_sp prenorm_dp + // fcomp + // fmul fadd fsub fmadd fmsub fnmsub fnmadd + // fres,frsqrte + // frsp + //------------------------------------------- + // + + assign f_pic_ex2_from_integer = ex2_from_integer; //output-- + assign f_pic_ex2_fsel = ex2_fsel; //output-- + + assign f_pic_ex2_sh_ovf_do = ex2_fsel | ex2_move | ex2_prenorm | ex2_mv_to_scr | ex2_mv_from_scr; + + assign f_pic_ex2_sh_ovf_ig_b = (~(ex2_from_integer | (~ex2_b_valid))); //output-- + + assign f_pic_ex2_sh_unf_do = (~ex2_b_valid) | ex2_est_recip | ex2_est_rsqrt; //output-- + + assign f_pic_ex2_sh_unf_ig_b = (~ex2_from_integer); //output-- --UNSET-- + + assign ex2_a_sign = f_byp_pic_ex2_a_sign; + assign ex2_c_sign = f_byp_pic_ex2_c_sign; + assign ex2_b_sign = f_byp_pic_ex2_b_sign; + + assign ex2_b_sign_adj_x = ex2_b_sign ^ ex2_sub_op; //addend sign adjusted + assign ex2_p_sign = ex2_a_sign ^ ex2_c_sign; //product sign + + assign ex2_b_sign_adj = (ex2_b_sign_adj_x & ex2_b_valid) | (ex2_p_sign & (~ex2_b_valid)); // multiply/divide always use p-sign + + assign ex2_div_sign = (ex2_a_sign ^ ex2_b_sign) & ex2_div_beg; + + ////#------------------------------------------ + ////# effective subtract + ////#------------------------------------------ + + assign f_pic_ex2_effsub_raw = (ex2_math | ex2_compare) & (ex2_b_sign_adj ^ ex2_p_sign); //output-- + + ////#--------------------------------------------- + ////# sign logic alter b-sign for funny moves + ////#--------------------------------------------- + // sign is 0 when not valid + + assign ex2_b_sign_alt = (ex2_a_sign & ex2_move & ex2_sgncpy & ex2_b_valid) | (ex2_b_sign & ex2_move & ex2_sign_ctl[0] & ex2_b_valid & (~ex2_sgncpy)) | ((~ex2_b_sign) & ex2_move & ex2_sign_ctl[1] & ex2_b_valid & (~ex2_sgncpy)) | (f_alg_ex2_sign_frmw & ex2_from_integer & (~ex2_uns) & ex2_word) | (ex2_b_sign & ex2_from_integer & (~ex2_uns) & (~ex2_word)) | (ex2_b_sign_adj & (ex2_math | ex2_compare)) | (ex2_b_sign & (~ex2_move) & (~(ex2_math | ex2_compare)) & ex2_b_valid & (~ex2_from_integer)); // when ! b_valid (mul) use p_sign + + ////################################################################ + ////# ex3 latches + ////################################################################ + + assign ex2_lzo_dis = (ex2_uc_mid) | (ex2_prenorm) | (ex2_fsel) | (ex2_move) | (ex2_from_integer) | (ex2_est_recip) | (ex2_est_rsqrt) | (ex2_to_integer & (~ex2_rnd_to_int)); //f_pic_ex3_to_integer + + assign ex2_a_nan = f_fmt_ex2_a_expo_max & (~f_fmt_ex2_a_frac_zero) & (~ex2_uc_end_nspec) & (~ex2_uc_mid); + assign ex2_c_nan = f_fmt_ex2_c_expo_max & (~f_fmt_ex2_c_frac_zero) & (~ex2_uc_end_nspec) & (~ex2_uc_mid); + assign ex2_b_nan = f_fmt_ex2_b_expo_max & (~f_fmt_ex2_b_frac_zero) & (~ex2_uc_end_nspec) & (~ex2_uc_mid); + + assign ex2_a_inf = f_fmt_ex2_a_expo_max & f_fmt_ex2_a_frac_zero & (~ex2_uc_end_nspec) & (~ex2_uc_mid); + assign ex2_c_inf = f_fmt_ex2_c_expo_max & f_fmt_ex2_c_frac_zero & (~ex2_uc_end_nspec) & (~ex2_uc_mid); + assign ex2_b_inf = f_fmt_ex2_b_expo_max & f_fmt_ex2_b_frac_zero & (~ex2_uc_end_nspec) & (~ex2_uc_mid); + + assign ex2_bf_10000 = (f_fmt_ex2_b_imp & f_fmt_ex2_b_frac_zero) | (f_fmt_ex2_b_imp & f_fmt_ex2_b_frac_z32 & ex2_word); // imp=1, frac=0 + + assign f_pic_ex2_frsp_ue1 = ex2_frsp & ex2_ue; //output + + assign ex2_sp = (~ex2_sp_b); + assign f_pic_ex2_ftdiv = ex2_ftdiv ; + + tri_rlmreg_p #(.WIDTH(57) ) ex3_ctl_lat( + .vd(vdd), + .gd(gnd), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[2]), + .mpw1_b(mpw1_b[2]), + .mpw2_b(mpw2_b[0]), + .nclk(nclk), + .act(ex2_act), + .thold_b(thold_0_b), + .sg(sg_0), + .scout(ex3_ctl_so), + .scin(ex3_ctl_si), + //----------------- + .din({ ex2_fsel, + ex2_from_integer, + ex2_to_integer, + ex2_math, + ex2_est_recip, + ex2_est_rsqrt, + ex2_move, + ex2_compare, + ex2_prenorm, + ex2_frsp, + ex2_mv_to_scr, + ex2_mv_from_scr, + ex2_div_beg, + ex2_sqrt_beg, + ex2_sp, + ex2_word, + ex2_ordered, + ex2_sub_op, + ex2_lzo_dis, + ex2_rnd_dis, + ex2_inv_sign, + ex2_p_sign, + ex2_b_sign_adj, + ex2_b_sign_alt, + ex2_a_sign, + ex2_a_valid, + ex2_c_valid, + ex2_b_valid, + f_fmt_ex2_prod_zero, + ex2_rnd0, + ex2_rnd1, + ex2_rnd_to_int, + ex2_ve, + ex2_oe, + ex2_ue, + ex2_ze, + ex2_xe, + ex2_nonieee, + ex2_rnd0, + ex2_rnd1, + ex2_sp_conv, + ex2_uns, + ex2_log2e, + ex2_pow2e, + ex2_ovf_unf_dis, + ex2_rnd_fpscr[0], + ex2_rnd_fpscr[1], + ex2_div_sign, + ex2_uc_ft_pos, + ex2_uc_ft_neg, + ex2_uc_mid, + ex2_uc_end_spec, + ex2_nj_deno, + ex2_ftdiv, + ex2_ftsqrt, + tiup, + f_fmt_ex2_b_imp}), + //----------------- + .dout({ ex3_fsel, + ex3_from_integer, + ex3_to_integer, + ex3_math, + ex3_est_recip, + ex3_est_rsqrt, + ex3_move, + ex3_compare, + ex3_prenorm, + ex3_frsp, + ex3_mv_to_scr, + ex3_mv_from_scr, + ex3_div_beg, + ex3_sqrt_beg, + ex3_sp, + ex3_word, + ex3_ordered, + ex3_sub_op, + ex3_lzo_dis, + ex3_rnd_dis, + ex3_inv_sign, + ex3_p_sign, + ex3_b_sign_adj, + ex3_b_sign_alt, + ex3_a_sign, + ex3_a_valid, + ex3_c_valid, + ex3_b_valid, + ex3_prod_zero, + ex3_op_rnd[0], + ex3_op_rnd[1], + ex3_rnd_to_int, + ex3_ve, + ex3_oe, + ex3_ue, + ex3_ze, + ex3_xe, + ex3_nonieee, + ex3_rnd0, + ex3_rnd1, + ex3_sp_conv, + ex3_uns, + ex3_log2e, + ex3_pow2e, + ex3_ovf_unf_dis, + ex3_rnd_fpscr[0], + ex3_rnd_fpscr[1], + ex3_div_sign, + ex3_uc_ft_pos, + ex3_uc_ft_neg, + ex3_uc_mid, + ex3_uc_end_spec, + ex3_nj_deno, + ex3_ftdiv, + ex3_ftsqrt, + ex3_accuracy, + ex3_b_imp}) + ); + + assign ex3_to_int_uns_neg = ex3_to_integer & (~ex3_rnd_to_int) & ex3_uns & ex3_b_sign_alt; + assign ex3_wd_ov_x = f_eie_ex3_wd_ov; + assign ex3_dw_ov_x = f_eie_ex3_dw_ov; + + assign f_pic_ex3_frsp_ue1 = ex3_frsp & ex3_ue; //output + assign f_pic_ex3_b_valid = ex3_b_valid; //output + assign f_pic_ex3_ue1 = ex3_ue | ex3_ovf_unf_dis; //output + + assign ex2_sp_invalid = (f_fmt_ex2_sp_invalid & ex2_sp & (~ex2_from_integer) & (~ex2_uc_mid) & (~ex2_uc_end_nspec)); + + + tri_rlmreg_p #(.WIDTH(18)) ex3_flg_lat( + .vd(vdd), + .gd(gnd), + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(tidn), + .mpw1_b(tidn), + .mpw2_b(tidn), + .nclk(nclk), + .act(ex2_act), + .thold_b(thold_0_b), + .sg(sg_0), + .scout(ex3_flg_so), + .scin(ex3_flg_si), + //----------------- + .din({ f_fmt_ex2_a_frac_msb, + f_fmt_ex2_c_frac_msb, + f_fmt_ex2_b_frac_msb, + f_fmt_ex2_a_zero, + f_fmt_ex2_c_zero, + f_fmt_ex2_b_zero, + ex2_a_nan, + ex2_c_nan, + ex2_b_nan, + ex2_a_inf, + ex2_b_inf, + ex2_c_inf, + ex2_sp_invalid, + ex2_bf_10000, + f_fmt_ex2_bexpu_le126, + f_fmt_ex2_gt126, + f_fmt_ex2_ge128, + f_fmt_ex2_inf_and_beyond_sp}), + //----------------- + .dout({ ex3_a_frac_msb, + ex3_c_frac_msb, + ex3_b_frac_msb, + ex3_a_zero, + ex3_c_zero, + ex3_b_zero, + ex3_a_nan, + ex3_c_nan, + ex3_b_nan, + ex3_a_inf, + ex3_b_inf, + ex3_c_inf, + ex3_sp_invalid, + ex3_bf_10000, + ex3_bexpu_le126, + ex3_gt126, + ex3_ge128, + ex3_inf_and_beyond_sp}) + ); + + ////################################################################ + ////# ex3 logic + ////################################################################ + + assign f_pic_ex3_sp_b = (~ex3_sp); //output-- + assign f_pic_ex3_to_integer = ex3_to_integer & (~ex3_rnd_to_int); //output-- --lza only + assign f_pic_ex3_prenorm = ex3_prenorm; + + //output-- + assign f_pic_ex3_force_sel_bexp = (ex3_from_integer) | (ex3_move) | (ex3_mv_to_scr) | (ex3_mv_from_scr) | (ex3_prenorm) | (ex3_est_recip) | (ex3_est_rsqrt); + + assign f_pic_ex3_est_recip = ex3_est_recip; //output--feie + assign f_pic_ex3_est_rsqrt = ex3_est_rsqrt; //output--feie + + assign f_pic_ex3_sp_lzo = (ex3_frsp) | (ex3_math & ex3_sp); //output-- + + //output-- + assign f_pic_ex3_lzo_dis_prod = (ex3_math & ex3_ue) | (ex3_frsp & ex3_ue) | (ex3_lzo_dis); // intermediate steps div/sqrt + + assign f_pic_ex3_math_bzer_b = (~(ex3_math & ex3_b_zero)); + + assign ex3_rnd_nr = (~ex3_rnd_dis) & (~ex3_rnd0) & (~ex3_rnd1); + assign ex3_rnd_inf_ok = (~ex3_rnd_dis) & ex3_rnd0 & (~(ex3_rnd1 ^ ex3_b_sign_alt)); + + assign f_pic_ex3_rnd_nr = ex3_rnd_nr; + assign f_pic_ex3_rnd_inf_ok = ex3_rnd_inf_ok; + + ////#------------------------------------------------------ + ////# special cases from inputs + ////#------------------------------------------------------ + ////# special cases can force 4 different results: PassNan genNan Inf Zero + ////# (the value of inf can be modified based on round-mode) + ////# + ////# ................................................................... + ////# @@ Specail Cases From inputs (other than NAN) + ////# COMPARE : no special cases other than NAN which sets NAN compare + ////# + ////# FROMINT : BZero T=+Zero FI=0 FR=0 UX=0 OX=0 FPRF=+Zero // all others are +/- NORM + ////# + ////# TOINT : BZero+ T=+Zero FI=0 FR=0 UX=0 OX=0 FPRF=00000 (ALL TOINTEGER UX=0 OX=0 FPRF=00000) + ////# TOINT : BZero- T=+Zero FI=0 FR=0 UX=0 OX=0 FPRF=00000 (ALL TOINTEGER UX=0 OX=0 FPRF=00000) + ////# TOINT : BNan T=80000 Fi=0 Fr=0 Ux=0 Ox=0 FPRF=00000 (ALL TOINTEGER UX=0 OX=0 FPRF=00000) + ////# TOINT : BInf+ T=PIPE Fi=0 Fr=0 Ux=0 Ox=0 FPRF=00000 (ALL TOINTEGER UX=0 OX=0 FPRF=00000) + ////# TOINT : BInf- T=PIPE Fi=0 Fr=0 Ux=0 Ox=0 FPRF=00000 (ALL TOINTEGER UX=0 OX=0 FPRF=00000) + ////# + ////# FRES : BZer+ T=+INF Fi=0 Fr=0 Ux=0 Ox=0 FPRF=+INF // ZX (Ve=1: hold FPRF) + ////# FRES : BZer- T=-INF Fi=0 Fr=0 Ux=0 Ox=0 FPRF=-INF // ZX (Ve=1: hold FPRF) + ////# FRES : BInf+ T=+Zer Fi=0 Fr=0 Ux=0 Ox=0 FPRF=+Zer + ////# FRES : BInf- T=-Zer Fi=0 Fr=0 Ux=0 Ox=0 FPRF=-Zer + ////# FRES : BNAN T=PASS Fi=0 Fr=0 Ux=0 Ox=0 FPRF=qNAN + ////# + ////# FRSQRTE : BZer+ T=Inf+ Fi=0 Fr=0 Ux=0 Ox=0 FPRF=Inf+ // ZX (Ve=1: hold FPRF) + ////# FRSQRTE : BZer- T=Inf- Fi=0 Fr=0 Ux=0 Ox=0 FPRF=Inf- // ZX (Ve=1: hold FPRF) + ////# FRSQRTE : BInf- T=NAN Fi=0 Fr=0 Ux=0 Ox=0 FPRF=nan // vxsqrt + ////# FRSQRTE : B- T=NAN Fi=0 Fr=0 Ux=0 Ox=0 FPRF=nan // vxsqrt + ////# FRSQRTE : BInf+ T=Zer+ Fi=0 Fr=0 Ux=0 Ox=0 FPRF=Zer+ + ////# FRSQRTE : BNan T=PASS Fi=0 Fr=0 Ux=0 Ox=0 FPRF=nan // vxsnan[?12] + ////# + ////# SQRT_END : BZer+ T=Zer+ Fi=0 Fr=0 Ux=0 Ox=0 FPRF=Zer+ + ////# SQRT_END : BZer- T=Zer- Fi=0 Fr=0 Ux=0 Ox=0 FPRF=Zer- + ////# SQRT_END : BINF- T=NAN Fi=0 Fr=0 Ux=0 Ox=0 FPRF=NAN // vxsqrt + ////# SQRT_END : B- T=NAN Fi=0 Fr=0 Ux=0 Ox=0 FPRF=NAN // vxsqrt + ////# SQRT_END : BINF+ T=Inf+ Fi=0 Fr=0 Ux=0 Ox=0 FPRF=Inf+ + ////# SQRT_END : BNan T=PASS Fi=0 Fr=0 Ux=0 Ox=0 FPRF=nan // vxsnan[?12] + ////# + ////# DIV_BEG : BZer+ T=Inf? Fi=0 Fr=0 Ux=0 Ox=0 FPRF=Inf? // ZX (Ve=1: hold FPRF) (vxZDZ if A=Zer) + ////# DIV_BEG : BZer- T=Inf? Fi=0 Fr=0 Ux=0 Ox=0 FPRF=Inf? // ZX (Ve=1: hold FPRF) (vxZDZ if A=Zer) + ////# DIV_BEG : BNAN T=Pass Fi=0 Fr=0 Ux=0 Ox=0 FPRF=nan // vxsnan[?12] + ////# DIV_BEG : BInf+ T=Zer? Fi=0 Fr=0 Ux=0 Ox=0 FPRF=Zer? // (vxIDI if A=Inf) + ////# DIV_BEG : BInf- T=Zer? Fi=0 Fr=0 Ux=0 Ox=0 FPRF=Zer? // (vxIDI if A=Inf) + ////# DIV_BEG : Both,AInf T=Inf? Fi=0 Fr=0 Ux=0 Ox=0 FPRF=Inf? // + ////# DIV_BEG : Both,AZer T=Zer? Fi=0 Fr=0 Ux=0 Ox=0 FPRF=Zer? // + ////# + ////# FRSP : BZer+ T=Zer+ Fi=0 Fr=0 Ux=0 Ox=0 Fprf=Zer+ + ////# FRSP : BZer- T=Zer- Fi=0 Fr=0 Ux=0 Ox=0 Fprf=Zer- + ////# FRSP : BInf+ T=Inf+ Fi=0 Fr=0 Ux=0 Ox=0 Fprf=Inf+ + ////# FRSP : BInf- T=Inf- Fi=0 Fr=0 Ux=0 Ox=0 Fprf=Inf- + ////# FRSP : BNan T=Pass Fi=0 Fr=0 Ux=0 Ox=0 Fprf=Nan? + ////# + ////# MATH : ANAN T=Pass Fi=0 Fr=0 Ux=0 Ox=0 Fprf=Nan? + ////# MATH : BNAN T=Pass Fi=0 Fr=0 Ux=0 Ox=0 Fprf=Nan? + ////# MATH : CNAN T=Pass Fi=0 Fr=0 Ux=0 Ox=0 Fprf=Nan? + ////# MATH : BZer*AZer T=Zer@@ Fi-0 Fr=0 Ux=0 Ox=0 Fprf=Zer@@ @@:ExactZero Rounding Rule + ////# MATH : BZer*CZer T=Zer@@ Fi-0 Fr=0 Ux=0 Ox=0 Fprf=Zer@@ @@:ExactZero Rounding Rule + ////# + ////# MATH : AINF|CINF|BINF T=??? Fi=0 Fr=0 Ux=0 Ox=0 Fprf=??? + ////# + ////# A C B + ////# Z I x => GenNan : vxIMZ + ////# I Z x => GenNan : vxIMZ + ////# I !Z I => GenNan : vxISI if effsub + ////# !Z I I => GenNan : vxISI if effsub + ////# I !Z I => INF : if effadd // sign = psign + ////# !Z I I => INF : if effadd // sign = psign + ////# I !Z !I => INF : psign + ////# !Z I !I => INF : psign + ////# !ZI !ZI I => INF : bsign xor sub_op + ////# + + ////#---------------------------------------------------- + ////# pass NAN (math,est,frsp) + ////#---------------------------------------------------- + + assign ex3_a_snan = ex3_a_nan & (~ex3_a_frac_msb); + assign ex3_b_snan = ex3_b_nan & (~ex3_b_frac_msb); + assign ex3_c_snan = ex3_c_nan & (~ex3_c_frac_msb); + assign ex3_a_qnan = ex3_a_nan & ex3_a_frac_msb; + assign ex3_b_qnan = ex3_b_nan & ex3_b_frac_msb; + assign ex3_nan_op_grp1 = ex3_math | ex3_est_recip | ex3_est_rsqrt | ex3_frsp | ex3_compare | ex3_rnd_to_int | ex3_div_beg | ex3_sqrt_beg; + assign ex3_nan_op_grp2 = ex3_nan_op_grp1 | ex3_to_integer | ex3_div_beg; + assign ex3_compo = ex3_compare & ex3_ordered; + + assign ex3_pass_en = (ex3_a_nan | ex3_c_nan | ex3_b_nan); + assign ex3_pass_nan = ex3_nan_op_grp1 & ex3_pass_en; + + //(1) + assign ex3_vxsnan = (ex3_a_snan & ex3_nan_op_grp1) | (ex3_c_snan & ex3_nan_op_grp1) | (ex3_b_snan & ex3_nan_op_grp2) | (f_dcd_ex3_uc_vxsnan); + + //(2) + assign ex3_vxvc = (ex3_compo & ex3_a_qnan & (~ex3_b_snan)) | (ex3_compo & ex3_b_qnan & (~ex3_a_snan)) | (ex3_compo & ex3_a_snan & (~ex3_ve)) | (ex3_compo & ex3_b_snan & (~ex3_ve)); + + assign ex3_vxcvi = (ex3_to_integer & ex3_b_nan & (~ex3_rnd_to_int)) & (~ex3_sp_invalid); //(3) + + assign ex3_vxzdz = f_dcd_ex3_uc_vxzdz | (ex3_a_zero & ex3_b_zero & ex3_div_beg & (~ex3_sp_invalid)); //(4) FDIV only + + assign ex3_vxidi = f_dcd_ex3_uc_vxidi | (ex3_a_inf & ex3_b_inf & ex3_div_beg & (~ex3_sp_invalid)); //(5) FDIV only + + ////#---------------------------------------------------- + ////# special case genNAN + ////#---------------------------------------------------- + + assign ex3_p_inf = ex3_a_inf | ex3_c_inf; + assign ex3_p_zero = ex3_a_zero | ex3_c_zero; + + assign ex3_vximz = (ex3_math & ex3_p_inf & ex3_p_zero) & (~ex3_sp_invalid); //(6) + + assign ex3_vxisi = (ex3_math & ex3_b_inf & ex3_p_inf & (~ex3_p_zero) & (~f_alg_ex3_effsub_eac_b)) & (~ex3_sp_invalid); //(7) + + assign ex3_vxsqrt = f_dcd_ex3_uc_vxsqrt | ((ex3_est_rsqrt | ex3_sqrt_beg) & ex3_b_sign_alt & (~ex3_b_zero) & (~ex3_b_nan) & (~ex3_sp_invalid)); //(8) + + assign ex3_gen_nan_dv = (ex3_a_zero & ex3_b_zero & ex3_div_beg) | ((ex3_vxidi | ex3_sp_invalid) & ex3_div_beg); + + assign ex3_gen_nan_sq = (ex3_vxsqrt | ex3_sp_invalid) & ex3_sqrt_beg; + + assign ex3_gen_nan = (ex3_b_nan & ex3_to_integer & (~ex3_rnd_to_int)) | ex3_gen_nan_log | ex3_gen_nan_pow | ex3_vxisi | ex3_vximz | (ex3_a_zero & ex3_b_zero & ex3_div_beg) | ex3_vxsqrt | ex3_vxidi | (ex3_sp_invalid & (~ex3_pow2e) & (~ex3_log2e)); + // sp op requires exponent in sp range (except frsp) + + // NAN *log:QNAN_PASS *pow: QNAN_PASS + // -INF *log:QNAN_dflt pow: +0 + // +INF *log:+INF *pow: +INF + // -0 *log:-INF *pow: +1 + // +0 *log:-INF *pow: +1 + // NEG *log:QNAN_dflt *pow: xxxxx + // -0 for to_ineger should now set fr_pipe_v fr=00 + //$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$ + + assign ex5_ox_pipe_v = (~ex5_sel_spec_e) & (~ex5_compare) & (~ex5_to_integer) & (~ex5_from_integer) & (~ex5_rnd_to_int) & (~ex5_uc_end_spec); + assign ex5_fr_pipe_v = (~ex5_sel_spec_fr) & (~ex5_compare) & (~ex5_to_integer) & (~ex5_rnd_to_int) & (~ex5_uc_end_spec); + + assign ex5_fprf_pipe_v = (~ex5_sel_spec_e) & (~ex5_compare) & (~(ex5_to_integer & (~ex5_rnd_to_int))) & (~ex5_fprf_hold); + + assign ex5_fprf_hold_ops = ex5_to_integer | ex5_frsp | ex5_rnd_to_int | (ex5_math & (~ex5_uc_mid)) | (ex5_est_recip & (~ex5_uc_mid)) | (ex5_est_rsqrt & (~ex5_uc_mid)); + + assign ex5_fprf_hold = (ex5_ve & ex5_vx & ex5_fprf_hold_ops) | (ex5_ze & ex5_zx & ex5_fprf_hold_ops); + + // FPRF + // 1 0 0 0 1 QNAN [0] qnan | den | (sign*zero) + // 0 1 0 0 1 -INF [1] sign * !zero + // 0 1 0 0 0 -norm [2] !sign * !zero * !qnan + // 1 1 0 0 0 -den [3] zero + // 1 0 0 1 0 -zero [4] inf | qnan + // 0 0 0 1 0 +zero + // 1 0 1 0 0 +den + // 0 0 1 0 0 +norm + // 0 0 1 0 1 +inf + // + // ex5_pass_nan 10001 @ + // ex5_gen_nan 10001 @ + // ex5_gen_inf (-) 01001 + // ex5_gen_inf (+) 00101 + // ex5_gen_zero (-) 10010 @ + // ex5_gen_zero (+) 00010 @ + // ex5_gen_one (+) 00100 +norm + // ex5_gen_one (-) 01000 -norm + + assign ex5_gen_inf_sign = ex5_round_sign ^ (ex5_inv_sign & (~ex5_pass_nan) & (~ex5_gen_nan)); + + //[0] nan, -zer, -den, +den ... (spec does not create den) + assign ex5_fprf_spec_x[0] = ex5_pass_nan | ex5_gen_nan | (ex5_gen_zero & (ex5_math & ex5_effsub_eac) & (ex5_rnd_ni ^ ex5_inv_sign)) | (ex5_gen_zero & (~(ex5_math & ex5_effsub_eac)) & (ex5_round_sign ^ ex5_inv_sign)); + + assign ex5_fprf_spec_x[1] = (ex5_gen_inf & ex5_gen_inf_sign) | (ex5_gen_one & ex5_round_sign); + assign ex5_fprf_spec_x[2] = (ex5_gen_inf & (~ex5_gen_inf_sign)) | (ex5_gen_one & (~ex5_round_sign)); + assign ex5_fprf_spec_x[3] = ex5_gen_zero; + assign ex5_fprf_spec_x[4] = ex5_pass_nan | ex5_gen_nan | ex5_gen_inf; + + assign ex5_fprf_spec[0:4] = (({tidn, f_add_ex5_fpcc_iu[0:3]}) & {5{ex5_compare}}) | + (ex5_fprf_spec_x[0:4] & {5{(~ex5_to_integer_ken)}} & ~{5{(ex5_compare | ex5_fprf_hold)}}); + + // selects for constant (pipe and spec) ??? need mayOvf + + // k depends on the rounding mode (also diff for to intetger) + // NAN : pipe does not create nan + // +/- INF frac=0 + // MAX FP frac=1 + // MAX +int frac=1 + // MAX -INT frac=0 + + assign ex5_may_ovf = f_eov_ex5_may_ovf; + + assign ex5_k_max_fp = (ex5_may_ovf & ex5_rnd_zr) | (ex5_may_ovf & ex5_rnd_pi & ex5_round_sign) | (ex5_may_ovf & ex5_rnd_ni & (~ex5_round_sign)); + + //exponent 1 <= tidn (sign) + //exponent 2 <= tidn (2048) + //exponent 3 <= msb (1024) for inf/nan + //exponent 4 <= sp (512) + //exponent 5 <= sp (256) + //exponent 6 <= sp (128) + //exponent 7 <= mid (64) + //exponent 8 <= mid (64) + //exponent 9 <= mid (32) + //exponent 10 <= mid (16) + //exponent 11 <= mid (8) + //exponent 12 <= mid (4) + //exponent 13 <= lsb (1) + + assign ex5_gen_any = ex5_gen_nan | ex5_gen_inf | ex5_gen_zero | ex5_gen_one; + + assign ex5_k_nan = (ex5_gen_nan | ex5_pass_nan) & (~ex5_to_integer_ken); + + assign ex5_k_inf = (ex5_gen_inf & (~ex5_to_integer_ken)) | ((~ex5_gen_any) & (~ex5_to_integer_ken) & ex5_may_ovf & (~ex5_k_max_fp)); + + assign ex5_k_max = (ex5_gen_max & (~ex5_to_integer_ken)) | ((~ex5_gen_any) & (~ex5_to_integer_ken) & ex5_may_ovf & ex5_k_max_fp); + + assign ex5_k_zer = (ex5_gen_zero & (~ex5_to_integer_ken)) | ((~ex5_gen_any) & (~ex5_to_integer_ken) & (~ex5_may_ovf)); + + assign ex5_k_one = ex5_gen_one; + + assign ex5_to_integer_ken = ex5_to_integer & (~ex5_rnd_to_int); + + //uns + assign ex5_k_int_zer = (ex5_to_integer_ken & ex5_uns & ex5_gen_zero) | (ex5_to_integer_ken & ex5_uns & ex5_gen_nan) | (ex5_to_integer_ken & ex5_uns & ex5_sign_nco) | (ex5_to_integer_ken & (~ex5_uns) & ex5_gen_zero); //uns + //sgn + + //uns + assign ex5_k_int_maxpos = (ex5_to_integer_ken & ex5_uns & (~ex5_gen_zero) & (~ex5_gen_nan) & (~ex5_sign_nco)) | (ex5_to_integer_ken & (~ex5_uns) & (~ex5_gen_zero) & (~ex5_gen_nan) & (~ex5_sign_nco)); //sgn + + //sgn + assign ex5_k_int_maxneg = (ex5_to_integer_ken & (~ex5_uns) & (~ex5_gen_zero) & ex5_gen_nan) | (ex5_to_integer_ken & (~ex5_uns) & (~ex5_gen_zero) & ex5_sign_nco); //sgn + + assign ex5_en_exact_zero = ex5_math & ex5_effsub_eac & (~ex5_sel_spec_e); // nan_pass, gen_nan, gen_inf, gen_zero + + assign ex5_invert_sign = ex5_inv_sign & (~ex5_pass_nan) & (~ex5_gen_nan) & (~(ex5_gen_zero & ex5_effsub_eac)); + + assign ex5_sign_pco_x = ((~(ex5_gen_zero & ex5_math & ex5_effsub_eac)) & ex5_sign_pco) | ((ex5_gen_zero & ex5_math & ex5_effsub_eac) & (ex5_rnd_ni ^ ex5_inv_sign)); + assign ex5_sign_nco_x = ((~(ex5_gen_zero & ex5_math & ex5_effsub_eac)) & ex5_sign_nco) | ((ex5_gen_zero & ex5_math & ex5_effsub_eac) & (ex5_rnd_ni ^ ex5_inv_sign)); + + assign ex5_round_sign = (f_add_ex5_sign_carry & ex5_sign_pco) | ((~f_add_ex5_sign_carry) & ex5_sign_nco); // co means a frac 21:52 [21] is the integer sign bit + + assign ex6_frac_k[0] = ex6_k_notzer | ex6_word; // implicit bit + assign ex6_frac_k[1] = ex6_k_max_intmax_nan | ex6_word; + assign ex6_frac_k[2:20] = {19{(ex6_k_max_intmax & (~ex6_word))}}; + assign ex6_frac_k[21] = ex6_k_max_intsgn; // sign of int word + assign ex6_frac_k[22] = ex6_k_max_intmax; + assign ex6_frac_k[23] = ex6_k_max_intmax; + assign ex6_frac_k[24:52] = {29{ex6_k_max_intmax_nsp}}; + + assign ex6_k_notzer = (~(f_pic_ex6_k_zer | f_pic_ex6_k_int_zer | f_pic_ex6_k_int_maxneg)); //or f_pic_ex6_k_one + assign ex6_k_max_intmax_nan = f_pic_ex6_k_max | f_pic_ex6_k_int_maxpos | f_pic_ex6_k_nan; + assign ex6_k_max_intmax = f_pic_ex6_k_max | f_pic_ex6_k_int_maxpos; + assign ex6_k_max_intmax_nsp = (f_pic_ex6_k_max | f_pic_ex6_k_int_maxpos) & (~ex6_sp); + + // not to-integer + // dw-to_integer + assign ex6_k_max_intsgn = (f_pic_ex6_k_max) | (f_pic_ex6_k_int_maxpos & (~ex6_word)) | (f_pic_ex6_k_int_maxneg & ex6_word & (~ex6_uns)) | (f_pic_ex6_k_int_maxpos & ex6_word & ex6_uns); // wd-to-integer signed + // wd-to-integer unsigned + + assign ex6_res_frac[0] = (ex6_frac_k[0] & ex6_res_sel_k_f) | (ex6_frac_px[0] & (~ex6_res_sel_k_f)); // for to integer (impl needs extra logic) + + assign ex6_res_frac[1:52] = (ex6_frac_k[1:52] & {52{ex6_res_sel_k_f}}) | + (ex6_frac_px[1:52] & {52{(~ex6_res_sel_k_f)}}); + + ////##------------------------------------------- + ////## final selection muxing exponent + ////##------------------------------------------- + + // max sp expo 1151 is wrong 1151 =127+1024 0_0100_0111_1111 + // 1150 0_0100_0111_1110 + + assign ex6_k_inf_nan_max = f_pic_ex6_k_nan | f_pic_ex6_k_inf | f_pic_ex6_k_max; + + assign ex6_k_inf_nan_maxdp = f_pic_ex6_k_nan | f_pic_ex6_k_inf | (f_pic_ex6_k_max & (~ex6_sp)); + + assign ex6_k_inf_nan_zer = f_pic_ex6_k_nan | f_pic_ex6_k_inf | f_pic_ex6_k_zer; + + assign ex6_k_zer_sp = f_pic_ex6_k_zer & ex6_sp; + + assign ex6_expo_k[1] = tidn; // 4096 sign + assign ex6_expo_k[2] = tidn; // 2048 + assign ex6_expo_k[3] = ex6_k_inf_nan_max | f_pic_ex6_k_int_maxpos | ex6_word; // 1024 + assign ex6_expo_k[4] = ex6_k_inf_nan_maxdp | f_pic_ex6_k_int_maxpos | ex6_k_zer_sp | ex6_word | f_pic_ex6_k_one; // 0512 + assign ex6_expo_k[5] = ex6_k_inf_nan_maxdp | f_pic_ex6_k_int_maxpos | ex6_k_zer_sp | ex6_word | f_pic_ex6_k_one; // 0256 + assign ex6_expo_k[6] = ex6_k_inf_nan_maxdp | f_pic_ex6_k_int_maxpos | ex6_k_zer_sp | ex6_word | f_pic_ex6_k_one; // 0128 + assign ex6_expo_k[7] = ex6_k_inf_nan_max | f_pic_ex6_k_int_maxpos | ex6_word | f_pic_ex6_k_one; // 0064 + assign ex6_expo_k[8] = ex6_k_inf_nan_max | f_pic_ex6_k_int_maxpos | ex6_word | f_pic_ex6_k_one; // 0032 + assign ex6_expo_k[9] = ex6_k_inf_nan_max | f_pic_ex6_k_int_maxpos | ex6_word | f_pic_ex6_k_one; // 0016 + assign ex6_expo_k[10] = ex6_k_inf_nan_max | f_pic_ex6_k_int_maxpos | ex6_word | f_pic_ex6_k_one; // 0008 + assign ex6_expo_k[11] = ex6_k_inf_nan_max | f_pic_ex6_k_int_maxpos | ex6_word | f_pic_ex6_k_one; // 0004 + assign ex6_expo_k[12] = ex6_k_inf_nan_max | f_pic_ex6_k_int_maxpos | ex6_word | f_pic_ex6_k_one; // 0002 + assign ex6_expo_k[13] = ex6_k_inf_nan_zer | f_pic_ex6_k_int_maxpos | ex6_k_zero | f_pic_ex6_k_int_maxneg | ex6_word | f_pic_ex6_k_one; // 0001 + + //--------- + + assign ex6_expo_p0k[1:13] = (ex6_expo_k[1:13] & {13{ex6_expo_p0_sel_k}}) | + (({tidn, tidn, ex6_to_int_data[1:11]}) & {13{ex6_expo_p0_sel_int}}) | + (({tidn, tidn, f_gst_ex6_logexp_exp[1:11]}) & {13{ex6_expo_p0_sel_gst}}) | + ((f_dsq_ex6_divsqrt_exp[1:13]) & {13{ex6_expo_p0_sel_divsqrt}}) | + (({{12{tidn}}, tiup}) & {13{ex6_sel_fpscr_v}}) | + (f_eov_ex6_expo_p0[1:13] & {13{ex6_expo_p0_sel_dflt}}); + + assign ex6_expo_p1k[1:13] = (ex6_expo_k[1:13] & {13{ex6_expo_p1_sel_k}}) | + (f_eov_ex6_expo_p1[1:13] & {13{ex6_expo_p1_sel_dflt}}); + + //----------- + assign ex6_expo_p0kx[1:7] = (ex6_expo_p0k[1:7] & {7{(~ex6_sel_p0_joke)}}) | + (({tidn, tidn, f_eov_ex6_expo_p0_ue1oe1[3:7]}) & {7{ex6_sel_p0_joke}}); + + assign ex6_expo_p1kx[1:7] = (ex6_expo_p1k[1:7] & {7{(~ex6_sel_p1_joke)}}) | + (({tidn, tidn, f_eov_ex6_expo_p1_ue1oe1[3:7]}) & {7{ex6_sel_p1_joke}}); + + assign ex6_expo_p0kx[8:12] = ex6_expo_p0k[8:12]; // joke does not effect these bits + assign ex6_expo_p1kx[8:12] = ex6_expo_p1k[8:12]; // joke does not effect these bits + + // the silly exceptions enabled logic could wrap around and hit the exponent Zero + // if it is nonZero: it will normalize + // overflow + // DP constant = 1536 overflow = 2047 = 2047 Expo>=2047, subtracting 1536 cannot hit zero + // SP constant = 192 overflow = 255 + 896 = 1151 Expo>=1151, subtracting 192 cannot hit zero + // underflow + // DP constant = 1536 underflow at zero ... worst expo = -53??? + // SP constant = 192 underflow at 896 ... worst expo = + + assign ex6_expo_p0kx[13] = ex6_expo_p0k[13]; //or not ex6_res_frac(0) ; -- joke does not effect these bits + assign ex6_expo_p1kx[13] = ex6_expo_p1k[13]; //or not ex6_res_frac(0) ; -- joke does not effect these bits + //----------- + + assign ex6_res_expo[1] = (ex6_expo_p0kx[1] & (~ex6_res_sel_p1_e) & (~ex6_res_clip_e)) | (ex6_expo_p1kx[1] & ex6_res_sel_p1_e); // 4096 /sign + assign ex6_res_expo[2] = (ex6_expo_p0kx[2] & (~ex6_res_sel_p1_e) & (~ex6_res_clip_e)) | (ex6_expo_p1kx[2] & ex6_res_sel_p1_e); // 2048 + assign ex6_res_expo[3] = (ex6_expo_p0kx[3] & (~ex6_res_sel_p1_e) & (~ex6_res_clip_e)) | (ex6_expo_p1kx[3] & ex6_res_sel_p1_e); // 1024 + + assign ex6_res_expo[4] = (ex6_expo_p0kx[4] & (~ex6_res_sel_p1_e) & (~ex6_res_clip_e)) | (ex6_sp & (~ex6_res_sel_p1_e) & ex6_res_clip_e) | (ex6_expo_p1kx[4] & ex6_res_sel_p1_e); // 512 + assign ex6_res_expo[5] = (ex6_expo_p0kx[5] & (~ex6_res_sel_p1_e) & (~ex6_res_clip_e)) | (ex6_sp & (~ex6_res_sel_p1_e) & ex6_res_clip_e) | (ex6_expo_p1kx[5] & ex6_res_sel_p1_e); // 256 + assign ex6_res_expo[6] = (ex6_expo_p0kx[6] & (~ex6_res_sel_p1_e) & (~ex6_res_clip_e)) | (ex6_sp & (~ex6_res_sel_p1_e) & ex6_res_clip_e) | (ex6_expo_p1kx[6] & ex6_res_sel_p1_e); // 128 + + assign ex6_res_expo[7] = (ex6_expo_p0kx[7] & (~ex6_res_sel_p1_e) & (~ex6_res_clip_e)) | (ex6_expo_p1kx[7] & ex6_res_sel_p1_e); // 64 + assign ex6_res_expo[8] = (ex6_expo_p0kx[8] & (~ex6_res_sel_p1_e) & (~ex6_res_clip_e)) | (ex6_expo_p1kx[8] & ex6_res_sel_p1_e); // 32 + assign ex6_res_expo[9] = (ex6_expo_p0kx[9] & (~ex6_res_sel_p1_e) & (~ex6_res_clip_e)) | (ex6_expo_p1kx[9] & ex6_res_sel_p1_e); // 16 + assign ex6_res_expo[10] = (ex6_expo_p0kx[10] & (~ex6_res_sel_p1_e) & (~ex6_res_clip_e)) | (ex6_expo_p1kx[10] & ex6_res_sel_p1_e); // 8 + assign ex6_res_expo[11] = (ex6_expo_p0kx[11] & (~ex6_res_sel_p1_e) & (~ex6_res_clip_e)) | (ex6_expo_p1kx[11] & ex6_res_sel_p1_e); // 4 + assign ex6_res_expo[12] = (ex6_expo_p0kx[12] & (~ex6_res_sel_p1_e) & (~ex6_res_clip_e)) | (ex6_expo_p1kx[12] & ex6_res_sel_p1_e); // 2 + assign ex6_res_expo[13] = (ex6_expo_p0kx[13] & (~ex6_res_sel_p1_e)) | ((~ex6_res_sel_p1_e) & ex6_res_clip_e) | (ex6_expo_p1kx[13] & ex6_res_sel_p1_e); // 1 + + ////##------------------------------------------- + ////## final selection muxing sign + ////##------------------------------------------- + // actually know to_integer sign for signed convert ahead of time. + // may be unsigned converts in the future + + assign ex6_sgn_result_fp = f_pic_ex6_round_sign ^ f_pic_ex6_invert_sign; + + assign ex6_res_sign_prez = (ex6_sgn_result_fp & (~((ex6_to_integer | f_gst_ex6_logexp_v | ex6_divsqrt_v) & (~ex6_expo_sel_k)))) | (ex6_to_int_data[0] & (ex6_to_integer & (~ex6_expo_sel_k)) & (~ex6_word)) | (f_gst_ex6_logexp_sign & (f_gst_ex6_logexp_v & (~ex6_expo_sel_k))) | (f_dsq_ex6_divsqrt_sign & (ex6_divsqrt_v & (~ex6_expo_sel_k))); + + assign ex6_exact_zero_rnd = f_nrm_ex6_exact_zero & (~f_nrm_ex6_nrm_sticky_dp); // really just after aligner sicky from shift underflow + + assign ex6_rnd_ni_adj = ex6_rnd_ni ^ f_pic_ex6_invert_sign; + + assign ex6_exact_sgn_rst = f_pic_ex6_en_exact_zero & ex6_exact_zero_rnd & (~ex6_rnd_ni_adj); + assign ex6_exact_sgn_set = f_pic_ex6_en_exact_zero & ex6_exact_zero_rnd & ex6_rnd_ni_adj; + + assign ex6_res_sign = (((ex6_res_sign_prez & (~ex6_exact_sgn_rst)) | ex6_exact_sgn_set) & (~ex6_divsqrt_v)) | (f_dsq_ex6_divsqrt_flag_fpscr[6] & ex6_divsqrt_v); + + ////##------------------------------------------- + ////## selects for final selection muxing + ////##------------------------------------------- + + assign ex6_res_sel_k_f = ((f_eov_ex6_sel_kif_f & ex6_all1 & ex6_up) | (f_eov_ex6_sel_k_f) | (ex6_clip_deno) | (ex6_sel_est_v & f_tbl_ex6_recip_den & ex6_nj_deno)) & (~ex6_divsqrt_v); + + //------------------- + + assign ex6_res_sel_p1_e = ex6_all1 & ex6_up & (~ex6_divsqrt_v); + + assign ex6_est_log_pow_divsqrt = f_gst_ex6_logexp_v | ex6_sel_est | ex6_divsqrt_v; + + // ??? should al he sel_k override massive cancellation ??? + // i.e : unf_expo + // might NOT need this term since implicit catches it above + assign ex6_res_clip_e = (ex6_unf_en_ue0 & (~f_nrm_ex6_res[0]) & (~ex6_expo_sel_k) & (~ex6_est_log_pow_divsqrt)) | (ex6_unf_en_ue0 & f_eov_ex6_unf_expo & (~ex6_expo_sel_k) & (~ex6_est_log_pow_divsqrt)) | (ex6_all0 & (~ex6_to_integer) & (~ex6_expo_sel_k) & (~ex6_est_log_pow_divsqrt)) | (ex6_nj_deno & (~f_nrm_ex6_res[0]) & (~ex6_expo_sel_k) & (~ex6_est_log_pow_divsqrt)); // massive cancel (surprise) + + assign ex6_clip_deno = (ex6_nj_deno & (~f_nrm_ex6_res[0]) & (~ex6_expo_sel_k) & (~ex6_est_log_pow_divsqrt)); + + assign ex6_expo_sel_k = f_eov_ex6_sel_k_e; + assign ex6_expo_sel_k_both = f_eov_ex6_sel_k_e | f_eov_ex6_sel_kif_e; + + assign ex6_expo_p0_sel_k = ex6_expo_sel_k & (~ex6_divsqrt_v); + assign ex6_expo_p0_sel_gst = (~ex6_expo_sel_k) & f_gst_ex6_logexp_v & (~ex6_divsqrt_v); + assign ex6_expo_p0_sel_int = (~ex6_expo_sel_k) & ex6_to_integer & (~ex6_divsqrt_v); + assign ex6_expo_p0_sel_dflt = (~ex6_expo_sel_k) & (~ex6_to_integer) & (~f_gst_ex6_logexp_v) & (~ex6_divsqrt_v); + assign ex6_expo_p0_sel_divsqrt = ex6_divsqrt_v; + + assign ex6_expo_p1_sel_k = ex6_expo_sel_k_both; + assign ex6_expo_p1_sel_dflt = (~ex6_expo_sel_k_both); + + // ue1/oe1 exponent wrapping + assign ex6_sel_p0_joke = ((ex6_unf_en_ue1 & f_eov_ex6_unf_expo) | (ex6_ovf_en_oe1 & f_eov_ex6_ovf_expo)) & (~ex6_divsqrt_v); // for UX + + // ue1/oe1/exponent wrapping + assign ex6_sel_p1_joke = (ex6_unf_en_ue1 & f_eov_ex6_unf_expo) | (ex6_ovf_en_oe1 & f_eov_ex6_ovf_expo) | (ex6_ovf_en_oe1 & f_eov_ex6_ovf_if_expo); // for UX + + ////##------------------------------------------- + ////## flags for fspscr + ////##------------------------------------------- + + assign ex6_pwr4_spec_frsp = ex6_unf_en_ue1 & (~f_nrm_ex6_res[0]) & f_pic_ex6_frsp; + // frsp : + // For ue=1 with sp output , normalize then add 192 to exponent. + // the 192 thing works for madd when both operands are in sp range, + // however it does not work with frsp and a small dp number, smaller than an sp madd can create. + // also frsp needs to know ue=1 to set up a dummy pExpo in rf2 (early). + // this is hard since we are not suppose to stall/flush for mvto_fpscr ops. + // if we set up the constant like ue=0 for both modes, then + // we math the spec up to emin - 160, then give zero as a result. + // this is simillar to (but not exactly inclusive of all) the range where the +192 works. + // power4 seems to do it the ignore ue=1 way. + // + // power 4 sets the exact denorms to : fprf=+/-norm fi/fr=00 + // i like fprf=+/-zero fi/fr=10 fprf=+/-norm fi/fr=11 + // although that allows round up out of zero ???? + + assign ex6_flag_ox = (f_eov_ex6_ovf_expo & (~ex6_divsqrt_v)) | (f_eov_ex6_ovf_if_expo & ex6_all1 & ex6_up & (~ex6_divsqrt_v)) | (f_dsq_ex6_divsqrt_flag_fpscr[0] & ex6_divsqrt_v); + + assign ex6_ov_oe0 = ex6_flag_ox & ex6_ovf_en_oe0; + + assign ex6_flag_inf = (((ex6_spec_inf) | (ex6_ov_oe0 & (~f_pic_ex6_k_max))) & (~ex6_divsqrt_v)) | (f_dsq_ex6_divsqrt_flag_fpscr[9] & ex6_divsqrt_v); // rnd mode decides if to use infinity + + //fr is undefined for the ovf case (usin Loki reference model that sets it to 1). + + assign ex6_flag_up = ((ex6_ov_oe0 | ex6_up) & (~ex6_divsqrt_v)) | (f_dsq_ex6_divsqrt_flag_fpscr[4] & ex6_divsqrt_v); // (ex6_up and not ex6_pwr4_spec_frsp) ; + + assign ex6_flag_fi = ((ex6_ov_oe0 | ex6_gox) & (~ex6_divsqrt_v)) | (f_dsq_ex6_divsqrt_flag_fpscr[5] & ex6_divsqrt_v); // (ex6_gox and not ex6_pwr4_spec_frsp) ; + + // ue=0: lzo limits exponent to 381 ... look at pre-round implicit bit + // tiny with precision loss + // tiny + assign ex6_flag_ux = (((ex6_unf_en_ue0 & (~f_nrm_ex6_res[0]) & (~ex6_exact_zero_rnd) & ex6_gox & (~ex6_sel_est)) | (ex6_unf_en_ue0 & f_eov_ex6_unf_expo & (~ex6_exact_zero_rnd) & ex6_gox) | (ex6_unf_en_ue1 & f_eov_ex6_unf_expo & (~ex6_exact_zero_rnd)) | (ex6_unf_en_ue1 & f_eov_ex6_unf_expo & ex6_sel_est) | (ex6_unf_en_ue0 & f_eov_ex6_unf_expo & ex6_sel_est) | (ex6_pwr4_spec_frsp)) & (~ex6_divsqrt_v)) | (f_dsq_ex6_divsqrt_flag_fpscr[1] & ex6_divsqrt_v); // (power4 mode) + + assign ex6_k_zero = f_pic_ex6_k_zer | f_pic_ex6_k_int_zer; + + // start with zero + assign ex6_flag_zer = ((((~ex6_sel_est) & (~ex6_res_sel_k_f) & ex6_all0 & (~ex6_up)) | (ex6_res_sel_k_f & ex6_k_zero)) & (~ex6_divsqrt_v)) | (f_dsq_ex6_divsqrt_flag_fpscr[8] & ex6_divsqrt_v); // forcing zero + + // !implicit_bit :: denorm + assign ex6_flag_den = ((((~ex6_sel_est) & (~ex6_res_frac[0])) | (ex6_sel_est & f_tbl_ex6_recip_den) | (ex6_sel_est & ex6_unf_en_ue0 & f_eov_ex6_unf_expo)) & (~ex6_divsqrt_v)) | (f_dsq_ex6_divsqrt_flag_fpscr[10] & ex6_divsqrt_v); + + ////############################################## + ////# EX7 latches + ////############################################## + + + tri_rlmreg_p #(.WIDTH(53), .NEEDS_SRESET(0)) ex7_frac_lat( + .force_t(force_t), //i-- tidn, + .d_mode(tiup), + .delay_lclkr(delay_lclkr[6]), //i-- tidn, + .mpw1_b(mpw1_b[6]), //i-- tidn, + .mpw2_b(mpw2_b[1]), //i-- tidn, + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + .act(ex6_act), + .scout(ex7_frac_so), + .scin(ex7_frac_si), + //----------------- + .din(ex6_res_frac[0:52]), + //----------------- + .dout(ex7_res_frac[0:52]) //LAT-- + ); + + + tri_rlmreg_p #(.WIDTH(14), .NEEDS_SRESET(0)) ex7_expo_lat( + .force_t(force_t), //i-- tidn, + .d_mode(tiup), + .delay_lclkr(delay_lclkr[6]), //i-- tidn, + .mpw1_b(mpw1_b[6]), //i-- tidn, + .mpw2_b(mpw2_b[1]), //i-- tidn, + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + .act(ex6_act), + .scout(ex7_expo_so), + .scin(ex7_expo_si), + //----------------- + .din({ex6_res_sign, + ex6_res_expo[1:13]}), + //----------------- + .dout({ex7_res_sign, //LAT-- + ex7_res_expo[1:13]}) //LAT-- + ); + + + tri_rlmreg_p #(.WIDTH(10), .NEEDS_SRESET(1)) ex7_flag_lat( + .force_t(force_t), //i-- tidn, + .d_mode(tiup), + .delay_lclkr(delay_lclkr[6]), //i-- tidn, + .mpw1_b(mpw1_b[6]), //i-- tidn, + .mpw2_b(mpw2_b[1]), //i-- tidn, + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + .act(ex6_act), + .scout(ex7_flag_so), + .scin(ex7_flag_si), + //----------------- + .din({ flag_spare_unused, + ex6_res_sign, + ex6_flag_den, + ex6_flag_inf, + ex6_flag_zer, + ex6_flag_ux, + ex6_flag_up, + ex6_flag_fi, + ex6_flag_ox, + ex6_nj_deno}), + //----------------- + .dout({ flag_spare_unused, //LAT-- + ex7_flag_sgn, //LAT-- + ex7_flag_den, //LAT-- + ex7_flag_inf, //LAT-- + ex7_flag_zer, //LAT-- + ex7_flag_ux, //LAT-- + ex7_flag_up, //LAT-- + ex7_flag_fi, //LAT-- + ex7_flag_ox, //LAT-- + ex7_nj_deno}) //LAT-- + ); + + assign f_rnd_ex7_res_sign = ex7_res_sign; //output-- + assign f_rnd_ex7_res_expo[1:13] = ex7_res_expo[1:13]; //output-- + assign f_rnd_ex7_res_frac[0:52] = ex7_res_frac[0:52]; //output-- + + assign f_rnd_ex7_flag_sgn = ex7_flag_sgn; //output-- + assign f_rnd_ex7_flag_den = ex7_flag_den & (~ex7_nj_deno); //output-- + assign f_rnd_ex7_flag_inf = ex7_flag_inf; //output-- + assign f_rnd_ex7_flag_zer = ex7_flag_zer | (ex7_flag_den & ex7_nj_deno); //output-- + assign f_rnd_ex7_flag_ux = ex7_flag_ux & (~(ex7_flag_den & ex7_nj_deno)); //output-- + assign f_rnd_ex7_flag_up = ex7_flag_up & (~(ex7_flag_den & ex7_nj_deno)); //output-- + assign f_rnd_ex7_flag_fi = ex7_flag_fi & (~(ex7_flag_den & ex7_nj_deno)); //output-- + assign f_rnd_ex7_flag_ox = ex7_flag_ox; //output-- + + assign f_mad_ex7_uc_sign = ex7_res_sign; //output-- + assign f_mad_ex7_uc_zero = ex7_flag_zer & (~ex7_flag_fi); //output-- ??exact zero?? + + ////############################################ + ////# scan + ////############################################ + + assign act_si[0:4] = {act_so[1:4], f_rnd_si}; + assign ex6_ctl_si[0:15] = {ex6_ctl_so[1:15], act_so[0]}; + assign ex7_frac_si[0:52] = {ex7_frac_so[1:52], ex6_ctl_so[0]}; + assign ex7_expo_si[0:13] = {ex7_expo_so[1:13], ex7_frac_so[0]}; + assign ex7_flag_si[0:9] = {ex7_flag_so[1:9], ex7_expo_so[0]}; + assign f_rnd_so = ex7_flag_so[0]; + +endmodule diff --git a/dev/verilog/work/fu_sa3.v b/dev/verilog/work/fu_sa3.v new file mode 100755 index 0000000..f56e225 --- /dev/null +++ b/dev/verilog/work/fu_sa3.v @@ -0,0 +1,1397 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + + `include "tri_a2o.vh" + + +module fu_sa3( + vdd, + gnd, + clkoff_b, + act_dis, + flush, + delay_lclkr, + mpw1_b, + mpw2_b, + sg_1, + thold_1, + fpu_enable, + nclk, + f_sa3_si, + f_sa3_so, + ex2_act_b, + f_mul_ex3_sum, + f_mul_ex3_car, + f_alg_ex3_res, + f_sa3_ex4_s_lza, + f_sa3_ex4_c_lza, + f_sa3_ex4_s_add, + f_sa3_ex4_c_add +); + inout vdd; + inout gnd; + input clkoff_b; // tiup + input act_dis; // ??tidn?? + input flush; // ??tidn?? + input [2:3] delay_lclkr; // tidn, + input [2:3] mpw1_b; // tidn, + input [0:0] mpw2_b; // tidn, + input sg_1; + input thold_1; + input fpu_enable; //dc_act + input [0:`NCLK_WIDTH-1] nclk; + + input f_sa3_si; //perv + output f_sa3_so; //perv + input ex2_act_b; //act + + input [54:161] f_mul_ex3_sum; + input [54:161] f_mul_ex3_car; + input [0:162] f_alg_ex3_res; + + output [0:162] f_sa3_ex4_s_lza; // data + output [53:161] f_sa3_ex4_c_lza; // data + + output [0:162] f_sa3_ex4_s_add; // data + output [53:161] f_sa3_ex4_c_add; // data + + // ENTITY + + + parameter tiup = 1'b1; + parameter tidn = 1'b0; + + ////################################# + ////# sigdef : functional + ////################################# + wire thold_0_b; + wire thold_0; + wire force_t; + wire sg_0; + + (* analysis_not_referenced="TRUE" *) + wire [0:3] act_spare_unused; + + wire ex3_act; + wire [0:4] act_so; + wire [0:4] act_si; + wire [0:162] ex4_sum; + wire [53:161] ex4_car; + wire ex2_act; + wire [0:109] ex4_053_sum_si; + wire [0:109] ex4_053_sum_so; + wire [0:108] ex4_053_car_si; + wire [0:108] ex4_053_car_so; + wire [0:52] ex4_000_si; + wire [0:52] ex4_000_so; + wire [0:162] ex4_sum_lza_b; + wire [0:162] ex4_sum_add_b; + wire [53:161] ex4_car_lza_b; + wire [53:161] ex4_car_add_b; + wire sa3_ex4_d2clk; + wire sa3_ex4_d1clk; + wire [0:`NCLK_WIDTH-1] sa3_ex4_lclk; + + + wire [0:52] ex3_alg_b; + wire [53:162] ex3_sum_b; + wire [53:161] ex3_car_b; + + wire [55:161] f_alg_ex3_res_b; + wire [55:161] f_mul_ex3_sum_b; + wire [55:161] f_mul_ex3_car_b; + + ////################################################################ + ////# ex3 logic + ////################################################################ + + // just a 3:2 compressor + // + // ex3_sum(54 to 159) <= f_mul_ex3_sum(54 to 159) xor f_mul_ex3_car(54 to 159) xor f_alg_ex3_res(54 to 159) ; + // ex3_sum(160) <= f_mul_ex3_sum(160) xor f_alg_ex3_res(160) ; + // + // ex3_car(53 to 158) <= ( f_mul_ex3_sum(54 to 159) and f_mul_ex3_car(54 to 159) ) or + // ( f_mul_ex3_sum(54 to 159) and f_alg_ex3_res(54 to 159) ) or + // ( f_alg_ex3_res(54 to 159) and f_mul_ex3_car(54 to 159) ) ; + // ex3_car(159) <= ( f_mul_ex3_sum(160) and f_alg_ex3_res(160) ) ; + //--------------------------------------------------------------- + + // this model @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ + // + // aligner 000 001 002 ....... 052 053 054 055 056 .... 158 159 160 161 162 + // mul sum xxx xxx xxx ....... xxx xxx 054* 055 056 .... 158 159 160 xxx xxx + // mul car xxx xxx xxx ....... xxx xxx 054* 055 056 .... 158 159 xxx xxx xxx + // rid PB "1" "1" "1" ....... "1" "1" "1" "0" "0" .... "0" "0" "0" "0" "0" + // + // 54* is the pseudo bit ... at most 1 is on + + assign ex3_sum_b[54] = (~((~(f_mul_ex3_sum[54] | f_mul_ex3_car[54])) ^ f_alg_ex3_res[54])); + assign ex3_car_b[53] = (~((f_mul_ex3_sum[54] | f_mul_ex3_car[54]) | f_alg_ex3_res[54])); + + // rest of bits are normal as expected + + // with 3:2 is it equivalent to invert all the inputs, or invert all the outputs + + assign ex3_alg_b[0:52] = (~f_alg_ex3_res[0:52]); + + assign f_alg_ex3_res_b[55:161] = (~(f_alg_ex3_res[55:161])); + assign f_mul_ex3_sum_b[55:161] = (~(f_mul_ex3_sum[55:161])); + assign f_mul_ex3_car_b[55:161] = (~(f_mul_ex3_car[55:161])); + + //MLT32_X1_A12TH + tri_csa32 res_csa_55( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[55]), //i-- + .b(f_mul_ex3_sum_b[55]), //i-- + .c(f_mul_ex3_car_b[55]), //i-- + .sum(ex3_sum_b[55]), //o-- + .car(ex3_car_b[54]) //o-- + ); + + tri_csa32 res_csa_56( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[56]), //i-- + .b(f_mul_ex3_sum_b[56]), //i-- + .c(f_mul_ex3_car_b[56]), //i-- + .sum(ex3_sum_b[56]), //o-- + .car(ex3_car_b[55]) //o-- + ); + + tri_csa32 res_csa_57( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[57]), //i-- + .b(f_mul_ex3_sum_b[57]), //i-- + .c(f_mul_ex3_car_b[57]), //i-- + .sum(ex3_sum_b[57]), //o-- + .car(ex3_car_b[56]) //o-- + ); + + tri_csa32 res_csa_58( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[58]), //i-- + .b(f_mul_ex3_sum_b[58]), //i-- + .c(f_mul_ex3_car_b[58]), //i-- + .sum(ex3_sum_b[58]), //o-- + .car(ex3_car_b[57]) //o-- + ); + + tri_csa32 res_csa_59( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[59]), //i-- + .b(f_mul_ex3_sum_b[59]), //i-- + .c(f_mul_ex3_car_b[59]), //i-- + .sum(ex3_sum_b[59]), //o-- + .car(ex3_car_b[58]) //o-- + ); + + tri_csa32 res_csa_60( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[60]), //i-- + .b(f_mul_ex3_sum_b[60]), //i-- + .c(f_mul_ex3_car_b[60]), //i-- + .sum(ex3_sum_b[60]), //o-- + .car(ex3_car_b[59]) //o-- + ); + + tri_csa32 res_csa_61( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[61]), //i-- + .b(f_mul_ex3_sum_b[61]), //i-- + .c(f_mul_ex3_car_b[61]), //i-- + .sum(ex3_sum_b[61]), //o-- + .car(ex3_car_b[60]) //o-- + ); + + tri_csa32 res_csa_62( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[62]), //i-- + .b(f_mul_ex3_sum_b[62]), //i-- + .c(f_mul_ex3_car_b[62]), //i-- + .sum(ex3_sum_b[62]), //o-- + .car(ex3_car_b[61]) //o-- + ); + + tri_csa32 res_csa_63( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[63]), //i-- + .b(f_mul_ex3_sum_b[63]), //i-- + .c(f_mul_ex3_car_b[63]), //i-- + .sum(ex3_sum_b[63]), //o-- + .car(ex3_car_b[62]) //o-- + ); + + tri_csa32 res_csa_64( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[64]), //i-- + .b(f_mul_ex3_sum_b[64]), //i-- + .c(f_mul_ex3_car_b[64]), //i-- + .sum(ex3_sum_b[64]), //o-- + .car(ex3_car_b[63]) //o-- + ); + + tri_csa32 res_csa_65( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[65]), //i-- + .b(f_mul_ex3_sum_b[65]), //i-- + .c(f_mul_ex3_car_b[65]), //i-- + .sum(ex3_sum_b[65]), //o-- + .car(ex3_car_b[64]) //o-- + ); + + tri_csa32 res_csa_66( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[66]), //i-- + .b(f_mul_ex3_sum_b[66]), //i-- + .c(f_mul_ex3_car_b[66]), //i-- + .sum(ex3_sum_b[66]), //o-- + .car(ex3_car_b[65]) //o-- + ); + + tri_csa32 res_csa_67( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[67]), //i-- + .b(f_mul_ex3_sum_b[67]), //i-- + .c(f_mul_ex3_car_b[67]), //i-- + .sum(ex3_sum_b[67]), //o-- + .car(ex3_car_b[66]) //o-- + ); + + tri_csa32 res_csa_68( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[68]), //i-- + .b(f_mul_ex3_sum_b[68]), //i-- + .c(f_mul_ex3_car_b[68]), //i-- + .sum(ex3_sum_b[68]), //o-- + .car(ex3_car_b[67]) //o-- + ); + + tri_csa32 res_csa_69( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[69]), //i-- + .b(f_mul_ex3_sum_b[69]), //i-- + .c(f_mul_ex3_car_b[69]), //i-- + .sum(ex3_sum_b[69]), //o-- + .car(ex3_car_b[68]) //o-- + ); + + tri_csa32 res_csa_70( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[70]), //i-- + .b(f_mul_ex3_sum_b[70]), //i-- + .c(f_mul_ex3_car_b[70]), //i-- + .sum(ex3_sum_b[70]), //o-- + .car(ex3_car_b[69]) //o-- + ); + + tri_csa32 res_csa_71( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[71]), //i-- + .b(f_mul_ex3_sum_b[71]), //i-- + .c(f_mul_ex3_car_b[71]), //i-- + .sum(ex3_sum_b[71]), //o-- + .car(ex3_car_b[70]) //o-- + ); + + tri_csa32 res_csa_72( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[72]), //i-- + .b(f_mul_ex3_sum_b[72]), //i-- + .c(f_mul_ex3_car_b[72]), //i-- + .sum(ex3_sum_b[72]), //o-- + .car(ex3_car_b[71]) //o-- + ); + + tri_csa32 res_csa_73( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[73]), //i-- + .b(f_mul_ex3_sum_b[73]), //i-- + .c(f_mul_ex3_car_b[73]), //i-- + .sum(ex3_sum_b[73]), //o-- + .car(ex3_car_b[72]) //o-- + ); + + tri_csa32 res_csa_74( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[74]), //i-- + .b(f_mul_ex3_sum_b[74]), //i-- + .c(f_mul_ex3_car_b[74]), //i-- + .sum(ex3_sum_b[74]), //o-- + .car(ex3_car_b[73]) //o-- + ); + + tri_csa32 res_csa_75( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[75]), //i-- + .b(f_mul_ex3_sum_b[75]), //i-- + .c(f_mul_ex3_car_b[75]), //i-- + .sum(ex3_sum_b[75]), //o-- + .car(ex3_car_b[74]) //o-- + ); + + tri_csa32 res_csa_76( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[76]), //i-- + .b(f_mul_ex3_sum_b[76]), //i-- + .c(f_mul_ex3_car_b[76]), //i-- + .sum(ex3_sum_b[76]), //o-- + .car(ex3_car_b[75]) //o-- + ); + + tri_csa32 res_csa_77( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[77]), //i-- + .b(f_mul_ex3_sum_b[77]), //i-- + .c(f_mul_ex3_car_b[77]), //i-- + .sum(ex3_sum_b[77]), //o-- + .car(ex3_car_b[76]) //o-- + ); + + tri_csa32 res_csa_78( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[78]), //i-- + .b(f_mul_ex3_sum_b[78]), //i-- + .c(f_mul_ex3_car_b[78]), //i-- + .sum(ex3_sum_b[78]), //o-- + .car(ex3_car_b[77]) //o-- + ); + + tri_csa32 res_csa_79( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[79]), //i-- + .b(f_mul_ex3_sum_b[79]), //i-- + .c(f_mul_ex3_car_b[79]), //i-- + .sum(ex3_sum_b[79]), //o-- + .car(ex3_car_b[78]) //o-- + ); + + tri_csa32 res_csa_80( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[80]), //i-- + .b(f_mul_ex3_sum_b[80]), //i-- + .c(f_mul_ex3_car_b[80]), //i-- + .sum(ex3_sum_b[80]), //o-- + .car(ex3_car_b[79]) //o-- + ); + + tri_csa32 res_csa_81( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[81]), //i-- + .b(f_mul_ex3_sum_b[81]), //i-- + .c(f_mul_ex3_car_b[81]), //i-- + .sum(ex3_sum_b[81]), //o-- + .car(ex3_car_b[80]) //o-- + ); + + tri_csa32 res_csa_82( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[82]), //i-- + .b(f_mul_ex3_sum_b[82]), //i-- + .c(f_mul_ex3_car_b[82]), //i-- + .sum(ex3_sum_b[82]), //o-- + .car(ex3_car_b[81]) //o-- + ); + + tri_csa32 res_csa_83( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[83]), //i-- + .b(f_mul_ex3_sum_b[83]), //i-- + .c(f_mul_ex3_car_b[83]), //i-- + .sum(ex3_sum_b[83]), //o-- + .car(ex3_car_b[82]) //o-- + ); + + tri_csa32 res_csa_84( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[84]), //i-- + .b(f_mul_ex3_sum_b[84]), //i-- + .c(f_mul_ex3_car_b[84]), //i-- + .sum(ex3_sum_b[84]), //o-- + .car(ex3_car_b[83]) //o-- + ); + + tri_csa32 res_csa_85( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[85]), //i-- + .b(f_mul_ex3_sum_b[85]), //i-- + .c(f_mul_ex3_car_b[85]), //i-- + .sum(ex3_sum_b[85]), //o-- + .car(ex3_car_b[84]) //o-- + ); + + tri_csa32 res_csa_86( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[86]), //i-- + .b(f_mul_ex3_sum_b[86]), //i-- + .c(f_mul_ex3_car_b[86]), //i-- + .sum(ex3_sum_b[86]), //o-- + .car(ex3_car_b[85]) //o-- + ); + + tri_csa32 res_csa_87( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[87]), //i-- + .b(f_mul_ex3_sum_b[87]), //i-- + .c(f_mul_ex3_car_b[87]), //i-- + .sum(ex3_sum_b[87]), //o-- + .car(ex3_car_b[86]) //o-- + ); + + tri_csa32 res_csa_88( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[88]), //i-- + .b(f_mul_ex3_sum_b[88]), //i-- + .c(f_mul_ex3_car_b[88]), //i-- + .sum(ex3_sum_b[88]), //o-- + .car(ex3_car_b[87]) //o-- + ); + + tri_csa32 res_csa_89( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[89]), //i-- + .b(f_mul_ex3_sum_b[89]), //i-- + .c(f_mul_ex3_car_b[89]), //i-- + .sum(ex3_sum_b[89]), //o-- + .car(ex3_car_b[88]) //o-- + ); + + tri_csa32 res_csa_90( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[90]), //i-- + .b(f_mul_ex3_sum_b[90]), //i-- + .c(f_mul_ex3_car_b[90]), //i-- + .sum(ex3_sum_b[90]), //o-- + .car(ex3_car_b[89]) //o-- + ); + + tri_csa32 res_csa_91( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[91]), //i-- + .b(f_mul_ex3_sum_b[91]), //i-- + .c(f_mul_ex3_car_b[91]), //i-- + .sum(ex3_sum_b[91]), //o-- + .car(ex3_car_b[90]) //o-- + ); + + tri_csa32 res_csa_92( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[92]), //i-- + .b(f_mul_ex3_sum_b[92]), //i-- + .c(f_mul_ex3_car_b[92]), //i-- + .sum(ex3_sum_b[92]), //o-- + .car(ex3_car_b[91]) //o-- + ); + + tri_csa32 res_csa_93( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[93]), //i-- + .b(f_mul_ex3_sum_b[93]), //i-- + .c(f_mul_ex3_car_b[93]), //i-- + .sum(ex3_sum_b[93]), //o-- + .car(ex3_car_b[92]) //o-- + ); + + tri_csa32 res_csa_94( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[94]), //i-- + .b(f_mul_ex3_sum_b[94]), //i-- + .c(f_mul_ex3_car_b[94]), //i-- + .sum(ex3_sum_b[94]), //o-- + .car(ex3_car_b[93]) //o-- + ); + + tri_csa32 res_csa_95( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[95]), //i-- + .b(f_mul_ex3_sum_b[95]), //i-- + .c(f_mul_ex3_car_b[95]), //i-- + .sum(ex3_sum_b[95]), //o-- + .car(ex3_car_b[94]) //o-- + ); + + tri_csa32 res_csa_96( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[96]), //i-- + .b(f_mul_ex3_sum_b[96]), //i-- + .c(f_mul_ex3_car_b[96]), //i-- + .sum(ex3_sum_b[96]), //o-- + .car(ex3_car_b[95]) //o-- + ); + + tri_csa32 res_csa_97( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[97]), //i-- + .b(f_mul_ex3_sum_b[97]), //i-- + .c(f_mul_ex3_car_b[97]), //i-- + .sum(ex3_sum_b[97]), //o-- + .car(ex3_car_b[96]) //o-- + ); + + tri_csa32 res_csa_98( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[98]), //i-- + .b(f_mul_ex3_sum_b[98]), //i-- + .c(f_mul_ex3_car_b[98]), //i-- + .sum(ex3_sum_b[98]), //o-- + .car(ex3_car_b[97]) //o-- + ); + + tri_csa32 res_csa_99( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[99]), //i-- + .b(f_mul_ex3_sum_b[99]), //i-- + .c(f_mul_ex3_car_b[99]), //i-- + .sum(ex3_sum_b[99]), //o-- + .car(ex3_car_b[98]) //o-- + ); + + tri_csa32 res_csa_100( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[100]), //i-- + .b(f_mul_ex3_sum_b[100]), //i-- + .c(f_mul_ex3_car_b[100]), //i-- + .sum(ex3_sum_b[100]), //o-- + .car(ex3_car_b[99]) //o-- + ); + + tri_csa32 res_csa_101( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[101]), //i-- + .b(f_mul_ex3_sum_b[101]), //i-- + .c(f_mul_ex3_car_b[101]), //i-- + .sum(ex3_sum_b[101]), //o-- + .car(ex3_car_b[100]) //o-- + ); + + tri_csa32 res_csa_102( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[102]), //i-- + .b(f_mul_ex3_sum_b[102]), //i-- + .c(f_mul_ex3_car_b[102]), //i-- + .sum(ex3_sum_b[102]), //o-- + .car(ex3_car_b[101]) //o-- + ); + + tri_csa32 res_csa_103( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[103]), //i-- + .b(f_mul_ex3_sum_b[103]), //i-- + .c(f_mul_ex3_car_b[103]), //i-- + .sum(ex3_sum_b[103]), //o-- + .car(ex3_car_b[102]) //o-- + ); + + tri_csa32 res_csa_104( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[104]), //i-- + .b(f_mul_ex3_sum_b[104]), //i-- + .c(f_mul_ex3_car_b[104]), //i-- + .sum(ex3_sum_b[104]), //o-- + .car(ex3_car_b[103]) //o-- + ); + + tri_csa32 res_csa_105( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[105]), //i-- + .b(f_mul_ex3_sum_b[105]), //i-- + .c(f_mul_ex3_car_b[105]), //i-- + .sum(ex3_sum_b[105]), //o-- + .car(ex3_car_b[104]) //o-- + ); + + tri_csa32 res_csa_106( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[106]), //i-- + .b(f_mul_ex3_sum_b[106]), //i-- + .c(f_mul_ex3_car_b[106]), //i-- + .sum(ex3_sum_b[106]), //o-- + .car(ex3_car_b[105]) //o-- + ); + + tri_csa32 res_csa_107( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[107]), //i-- + .b(f_mul_ex3_sum_b[107]), //i-- + .c(f_mul_ex3_car_b[107]), //i-- + .sum(ex3_sum_b[107]), //o-- + .car(ex3_car_b[106]) //o-- + ); + + tri_csa32 res_csa_108( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[108]), //i-- + .b(f_mul_ex3_sum_b[108]), //i-- + .c(f_mul_ex3_car_b[108]), //i-- + .sum(ex3_sum_b[108]), //o-- + .car(ex3_car_b[107]) //o-- + ); + + tri_csa32 res_csa_109( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[109]), //i-- + .b(f_mul_ex3_sum_b[109]), //i-- + .c(f_mul_ex3_car_b[109]), //i-- + .sum(ex3_sum_b[109]), //o-- + .car(ex3_car_b[108]) //o-- + ); + + tri_csa32 res_csa_110( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[110]), //i-- + .b(f_mul_ex3_sum_b[110]), //i-- + .c(f_mul_ex3_car_b[110]), //i-- + .sum(ex3_sum_b[110]), //o-- + .car(ex3_car_b[109]) //o-- + ); + + tri_csa32 res_csa_111( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[111]), //i-- + .b(f_mul_ex3_sum_b[111]), //i-- + .c(f_mul_ex3_car_b[111]), //i-- + .sum(ex3_sum_b[111]), //o-- + .car(ex3_car_b[110]) //o-- + ); + + tri_csa32 res_csa_112( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[112]), //i-- + .b(f_mul_ex3_sum_b[112]), //i-- + .c(f_mul_ex3_car_b[112]), //i-- + .sum(ex3_sum_b[112]), //o-- + .car(ex3_car_b[111]) //o-- + ); + + tri_csa32 res_csa_113( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[113]), //i-- + .b(f_mul_ex3_sum_b[113]), //i-- + .c(f_mul_ex3_car_b[113]), //i-- + .sum(ex3_sum_b[113]), //o-- + .car(ex3_car_b[112]) //o-- + ); + + tri_csa32 res_csa_114( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[114]), //i-- + .b(f_mul_ex3_sum_b[114]), //i-- + .c(f_mul_ex3_car_b[114]), //i-- + .sum(ex3_sum_b[114]), //o-- + .car(ex3_car_b[113]) //o-- + ); + + tri_csa32 res_csa_115( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[115]), //i-- + .b(f_mul_ex3_sum_b[115]), //i-- + .c(f_mul_ex3_car_b[115]), //i-- + .sum(ex3_sum_b[115]), //o-- + .car(ex3_car_b[114]) //o-- + ); + + tri_csa32 res_csa_116( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[116]), //i-- + .b(f_mul_ex3_sum_b[116]), //i-- + .c(f_mul_ex3_car_b[116]), //i-- + .sum(ex3_sum_b[116]), //o-- + .car(ex3_car_b[115]) //o-- + ); + + tri_csa32 res_csa_117( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[117]), //i-- + .b(f_mul_ex3_sum_b[117]), //i-- + .c(f_mul_ex3_car_b[117]), //i-- + .sum(ex3_sum_b[117]), //o-- + .car(ex3_car_b[116]) //o-- + ); + + tri_csa32 res_csa_118( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[118]), //i-- + .b(f_mul_ex3_sum_b[118]), //i-- + .c(f_mul_ex3_car_b[118]), //i-- + .sum(ex3_sum_b[118]), //o-- + .car(ex3_car_b[117]) //o-- + ); + + tri_csa32 res_csa_119( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[119]), //i-- + .b(f_mul_ex3_sum_b[119]), //i-- + .c(f_mul_ex3_car_b[119]), //i-- + .sum(ex3_sum_b[119]), //o-- + .car(ex3_car_b[118]) //o-- + ); + + tri_csa32 res_csa_120( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[120]), //i-- + .b(f_mul_ex3_sum_b[120]), //i-- + .c(f_mul_ex3_car_b[120]), //i-- + .sum(ex3_sum_b[120]), //o-- + .car(ex3_car_b[119]) //o-- + ); + + tri_csa32 res_csa_121( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[121]), //i-- + .b(f_mul_ex3_sum_b[121]), //i-- + .c(f_mul_ex3_car_b[121]), //i-- + .sum(ex3_sum_b[121]), //o-- + .car(ex3_car_b[120]) //o-- + ); + + tri_csa32 res_csa_122( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[122]), //i-- + .b(f_mul_ex3_sum_b[122]), //i-- + .c(f_mul_ex3_car_b[122]), //i-- + .sum(ex3_sum_b[122]), //o-- + .car(ex3_car_b[121]) //o-- + ); + + tri_csa32 res_csa_123( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[123]), //i-- + .b(f_mul_ex3_sum_b[123]), //i-- + .c(f_mul_ex3_car_b[123]), //i-- + .sum(ex3_sum_b[123]), //o-- + .car(ex3_car_b[122]) //o-- + ); + + tri_csa32 res_csa_124( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[124]), //i-- + .b(f_mul_ex3_sum_b[124]), //i-- + .c(f_mul_ex3_car_b[124]), //i-- + .sum(ex3_sum_b[124]), //o-- + .car(ex3_car_b[123]) //o-- + ); + + tri_csa32 res_csa_125( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[125]), //i-- + .b(f_mul_ex3_sum_b[125]), //i-- + .c(f_mul_ex3_car_b[125]), //i-- + .sum(ex3_sum_b[125]), //o-- + .car(ex3_car_b[124]) //o-- + ); + + tri_csa32 res_csa_126( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[126]), //i-- + .b(f_mul_ex3_sum_b[126]), //i-- + .c(f_mul_ex3_car_b[126]), //i-- + .sum(ex3_sum_b[126]), //o-- + .car(ex3_car_b[125]) //o-- + ); + + tri_csa32 res_csa_127( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[127]), //i-- + .b(f_mul_ex3_sum_b[127]), //i-- + .c(f_mul_ex3_car_b[127]), //i-- + .sum(ex3_sum_b[127]), //o-- + .car(ex3_car_b[126]) //o-- + ); + + tri_csa32 res_csa_128( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[128]), //i-- + .b(f_mul_ex3_sum_b[128]), //i-- + .c(f_mul_ex3_car_b[128]), //i-- + .sum(ex3_sum_b[128]), //o-- + .car(ex3_car_b[127]) //o-- + ); + + tri_csa32 res_csa_129( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[129]), //i-- + .b(f_mul_ex3_sum_b[129]), //i-- + .c(f_mul_ex3_car_b[129]), //i-- + .sum(ex3_sum_b[129]), //o-- + .car(ex3_car_b[128]) //o-- + ); + + tri_csa32 res_csa_130( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[130]), //i-- + .b(f_mul_ex3_sum_b[130]), //i-- + .c(f_mul_ex3_car_b[130]), //i-- + .sum(ex3_sum_b[130]), //o-- + .car(ex3_car_b[129]) //o-- + ); + + tri_csa32 res_csa_131( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[131]), //i-- + .b(f_mul_ex3_sum_b[131]), //i-- + .c(f_mul_ex3_car_b[131]), //i-- + .sum(ex3_sum_b[131]), //o-- + .car(ex3_car_b[130]) //o-- + ); + + tri_csa32 res_csa_132( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[132]), //i-- + .b(f_mul_ex3_sum_b[132]), //i-- + .c(f_mul_ex3_car_b[132]), //i-- + .sum(ex3_sum_b[132]), //o-- + .car(ex3_car_b[131]) //o-- + ); + + tri_csa32 res_csa_133( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[133]), //i-- + .b(f_mul_ex3_sum_b[133]), //i-- + .c(f_mul_ex3_car_b[133]), //i-- + .sum(ex3_sum_b[133]), //o-- + .car(ex3_car_b[132]) //o-- + ); + + tri_csa32 res_csa_134( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[134]), //i-- + .b(f_mul_ex3_sum_b[134]), //i-- + .c(f_mul_ex3_car_b[134]), //i-- + .sum(ex3_sum_b[134]), //o-- + .car(ex3_car_b[133]) //o-- + ); + + tri_csa32 res_csa_135( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[135]), //i-- + .b(f_mul_ex3_sum_b[135]), //i-- + .c(f_mul_ex3_car_b[135]), //i-- + .sum(ex3_sum_b[135]), //o-- + .car(ex3_car_b[134]) //o-- + ); + + tri_csa32 res_csa_136( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[136]), //i-- + .b(f_mul_ex3_sum_b[136]), //i-- + .c(f_mul_ex3_car_b[136]), //i-- + .sum(ex3_sum_b[136]), //o-- + .car(ex3_car_b[135]) //o-- + ); + + tri_csa32 res_csa_137( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[137]), //i-- + .b(f_mul_ex3_sum_b[137]), //i-- + .c(f_mul_ex3_car_b[137]), //i-- + .sum(ex3_sum_b[137]), //o-- + .car(ex3_car_b[136]) //o-- + ); + + tri_csa32 res_csa_138( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[138]), //i-- + .b(f_mul_ex3_sum_b[138]), //i-- + .c(f_mul_ex3_car_b[138]), //i-- + .sum(ex3_sum_b[138]), //o-- + .car(ex3_car_b[137]) //o-- + ); + + tri_csa32 res_csa_139( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[139]), //i-- + .b(f_mul_ex3_sum_b[139]), //i-- + .c(f_mul_ex3_car_b[139]), //i-- + .sum(ex3_sum_b[139]), //o-- + .car(ex3_car_b[138]) //o-- + ); + + tri_csa32 res_csa_140( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[140]), //i-- + .b(f_mul_ex3_sum_b[140]), //i-- + .c(f_mul_ex3_car_b[140]), //i-- + .sum(ex3_sum_b[140]), //o-- + .car(ex3_car_b[139]) //o-- + ); + + tri_csa32 res_csa_141( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[141]), //i-- + .b(f_mul_ex3_sum_b[141]), //i-- + .c(f_mul_ex3_car_b[141]), //i-- + .sum(ex3_sum_b[141]), //o-- + .car(ex3_car_b[140]) //o-- + ); + + tri_csa32 res_csa_142( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[142]), //i-- + .b(f_mul_ex3_sum_b[142]), //i-- + .c(f_mul_ex3_car_b[142]), //i-- + .sum(ex3_sum_b[142]), //o-- + .car(ex3_car_b[141]) //o-- + ); + + tri_csa32 res_csa_143( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[143]), //i-- + .b(f_mul_ex3_sum_b[143]), //i-- + .c(f_mul_ex3_car_b[143]), //i-- + .sum(ex3_sum_b[143]), //o-- + .car(ex3_car_b[142]) //o-- + ); + + tri_csa32 res_csa_144( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[144]), //i-- + .b(f_mul_ex3_sum_b[144]), //i-- + .c(f_mul_ex3_car_b[144]), //i-- + .sum(ex3_sum_b[144]), //o-- + .car(ex3_car_b[143]) //o-- + ); + + tri_csa32 res_csa_145( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[145]), //i-- + .b(f_mul_ex3_sum_b[145]), //i-- + .c(f_mul_ex3_car_b[145]), //i-- + .sum(ex3_sum_b[145]), //o-- + .car(ex3_car_b[144]) //o-- + ); + + tri_csa32 res_csa_146( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[146]), //i-- + .b(f_mul_ex3_sum_b[146]), //i-- + .c(f_mul_ex3_car_b[146]), //i-- + .sum(ex3_sum_b[146]), //o-- + .car(ex3_car_b[145]) //o-- + ); + + tri_csa32 res_csa_147( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[147]), //i-- + .b(f_mul_ex3_sum_b[147]), //i-- + .c(f_mul_ex3_car_b[147]), //i-- + .sum(ex3_sum_b[147]), //o-- + .car(ex3_car_b[146]) //o-- + ); + + tri_csa32 res_csa_148( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[148]), //i-- + .b(f_mul_ex3_sum_b[148]), //i-- + .c(f_mul_ex3_car_b[148]), //i-- + .sum(ex3_sum_b[148]), //o-- + .car(ex3_car_b[147]) //o-- + ); + + tri_csa32 res_csa_149( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[149]), //i-- + .b(f_mul_ex3_sum_b[149]), //i-- + .c(f_mul_ex3_car_b[149]), //i-- + .sum(ex3_sum_b[149]), //o-- + .car(ex3_car_b[148]) //o-- + ); + + tri_csa32 res_csa_150( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[150]), //i-- + .b(f_mul_ex3_sum_b[150]), //i-- + .c(f_mul_ex3_car_b[150]), //i-- + .sum(ex3_sum_b[150]), //o-- + .car(ex3_car_b[149]) //o-- + ); + + tri_csa32 res_csa_151( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[151]), //i-- + .b(f_mul_ex3_sum_b[151]), //i-- + .c(f_mul_ex3_car_b[151]), //i-- + .sum(ex3_sum_b[151]), //o-- + .car(ex3_car_b[150]) //o-- + ); + + tri_csa32 res_csa_152( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[152]), //i-- + .b(f_mul_ex3_sum_b[152]), //i-- + .c(f_mul_ex3_car_b[152]), //i-- + .sum(ex3_sum_b[152]), //o-- + .car(ex3_car_b[151]) //o-- + ); + + tri_csa32 res_csa_153( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[153]), //i-- + .b(f_mul_ex3_sum_b[153]), //i-- + .c(f_mul_ex3_car_b[153]), //i-- + .sum(ex3_sum_b[153]), //o-- + .car(ex3_car_b[152]) //o-- + ); + + tri_csa32 res_csa_154( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[154]), //i-- + .b(f_mul_ex3_sum_b[154]), //i-- + .c(f_mul_ex3_car_b[154]), //i-- + .sum(ex3_sum_b[154]), //o-- + .car(ex3_car_b[153]) //o-- + ); + + tri_csa32 res_csa_155( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[155]), //i-- + .b(f_mul_ex3_sum_b[155]), //i-- + .c(f_mul_ex3_car_b[155]), //i-- + .sum(ex3_sum_b[155]), //o-- + .car(ex3_car_b[154]) //o-- + ); + + tri_csa32 res_csa_156( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[156]), //i-- + .b(f_mul_ex3_sum_b[156]), //i-- + .c(f_mul_ex3_car_b[156]), //i-- + .sum(ex3_sum_b[156]), //o-- + .car(ex3_car_b[155]) //o-- + ); + + tri_csa32 res_csa_157( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[157]), //i-- + .b(f_mul_ex3_sum_b[157]), //i-- + .c(f_mul_ex3_car_b[157]), //i-- + .sum(ex3_sum_b[157]), //o-- + .car(ex3_car_b[156]) //o-- + ); + + tri_csa32 res_csa_158( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[158]), //i-- + .b(f_mul_ex3_sum_b[158]), //i-- + .c(f_mul_ex3_car_b[158]), //i-- + .sum(ex3_sum_b[158]), //o-- + .car(ex3_car_b[157]) //o-- + ); + + tri_csa32 res_csa_159( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[159]), //i-- + .b(f_mul_ex3_sum_b[159]), //i-- + .c(f_mul_ex3_car_b[159]), //i-- + .sum(ex3_sum_b[159]), //o-- + .car(ex3_car_b[158]) //o-- + ); + + tri_csa32 res_csa_160( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[160]), //i-- + .b(f_mul_ex3_sum_b[160]), //i-- + .c(f_mul_ex3_car_b[160]), //i-- + .sum(ex3_sum_b[160]), //o-- + .car(ex3_car_b[159]) //o-- + ); + + tri_csa32 res_csa_161( + .vd(vdd), + .gd(gnd), + .a(f_alg_ex3_res_b[161]), //i-- + .b(f_mul_ex3_sum_b[161]), //i-- + .c(f_mul_ex3_car_b[161]), //i-- + .sum(ex3_sum_b[161]), //o-- + .car(ex3_car_b[160]) //o-- + ); + + assign ex3_sum_b[53] = (~f_alg_ex3_res[53]); + assign ex3_sum_b[162] = (~f_alg_ex3_res[162]); + assign ex3_car_b[161] = tiup; + + ////################################################################ + ////# functional latches + ////################################################################ + + // 053:068 : 16sum, 16 carry + // 069:084 + // 085:100 + // 101:116 + // 117:132 + // 133:148 + // 149:164 + + tri_inv_nlats #(.WIDTH(53), .NEEDS_SRESET(0)) ex4_000_lat( + .vd(vdd), + .gd(gnd), + .lclk(sa3_ex4_lclk), //lclk.clk + .d1clk(sa3_ex4_d1clk), + .d2clk(sa3_ex4_d2clk), + .scanin(ex4_000_si), + .scanout(ex4_000_so), + .d(ex3_alg_b[0:52]), + .qb(ex4_sum[0:52]) + ); + + tri_inv_nlats #(.WIDTH(110), .NEEDS_SRESET(0)) ex4_053_sum_lat( + .vd(vdd), + .gd(gnd), + .lclk(sa3_ex4_lclk), //lclk.clk + .d1clk(sa3_ex4_d1clk), + .d2clk(sa3_ex4_d2clk), + .scanin(ex4_053_sum_si), + .scanout(ex4_053_sum_so), + .d(ex3_sum_b[53:162]), + .qb(ex4_sum[53:162]) + ); + + tri_inv_nlats #(.WIDTH(109), .NEEDS_SRESET(0)) ex4_053_car_lat( + .vd(vdd), + .gd(gnd), + .lclk(sa3_ex4_lclk), //lclk.clk + .d1clk(sa3_ex4_d1clk), + .d2clk(sa3_ex4_d2clk), + .scanin(ex4_053_car_si), + .scanout(ex4_053_car_so), + .d(ex3_car_b[53:161]), + .qb(ex4_car[53:161]) + ); + + assign ex4_sum_lza_b[0:162] = (~ex4_sum[0:162]); + assign ex4_car_lza_b[53:161] = (~ex4_car[53:161]); + assign ex4_sum_add_b[0:162] = (~ex4_sum[0:162]); + assign ex4_car_add_b[53:161] = (~ex4_car[53:161]); + + assign f_sa3_ex4_s_lza[0:162] = (~ex4_sum_lza_b[0:162]); + assign f_sa3_ex4_c_lza[53:161] = (~ex4_car_lza_b[53:161]); + assign f_sa3_ex4_s_add[0:162] = (~ex4_sum_add_b[0:162]); + assign f_sa3_ex4_c_add[53:161] = (~ex4_car_add_b[53:161]); + + ////################################################################ + ////# pervasive + ////################################################################ + + + tri_plat thold_reg_0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(flush), + .din(thold_1), + .q(thold_0) + ); + + + tri_plat sg_reg_0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(flush), + .din(sg_1), + .q(sg_0) + ); + + + tri_lcbor lcbor_0( + .clkoff_b(clkoff_b), + .thold(thold_0), + .sg(sg_0), + .act_dis(act_dis), + .force_t(force_t), + .thold_b(thold_0_b) + ); + + ////################################################################ + ////# act + ////################################################################ + + assign ex2_act = (~ex2_act_b); + + + tri_rlmreg_p #(.WIDTH(5), .NEEDS_SRESET(0)) act_lat( + .force_t(force_t), // tidn, + .d_mode(tiup), + .delay_lclkr(delay_lclkr[2]), // tidn, + .mpw1_b(mpw1_b[2]), // tidn, + .mpw2_b(mpw2_b[0]), // tidn, + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(fpu_enable), + .thold_b(thold_0_b), + .sg(sg_0), + .scout(act_so), + .scin(act_si), + //----------------- + .din({ act_spare_unused[0], + act_spare_unused[1], + ex2_act, + act_spare_unused[2], + act_spare_unused[3]}), + //----------------- + .dout({act_spare_unused[0], + act_spare_unused[1], + ex3_act, + act_spare_unused[2], + act_spare_unused[3]}) + ); + + + tri_lcbnd sa3_ex4_lcb( + .delay_lclkr(delay_lclkr[3]), // tidn ,--in + .mpw1_b(mpw1_b[3]), // tidn ,--in + .mpw2_b(mpw2_b[0]), // tidn ,--in + .force_t(force_t), // tidn ,--in + .nclk(nclk), //in + .vd(vdd), //inout + .gd(gnd), //inout + .act(ex3_act), //in + .sg(sg_0), //in + .thold_b(thold_0_b), //in + .d1clk(sa3_ex4_d1clk), //out + .d2clk(sa3_ex4_d2clk), //out + .lclk(sa3_ex4_lclk) //out + ); + + ////################################################################ + ////# scan string + ////################################################################ + + assign ex4_053_car_si[0:108] = {ex4_053_car_so[1:108], f_sa3_si}; + assign ex4_053_sum_si[0:109] = {ex4_053_sum_so[1:109], ex4_053_car_so[0]}; + assign ex4_000_si[0:52] = {ex4_000_so[1:52], ex4_053_sum_so[0]}; + assign act_si[0:4] = {act_so[1:4], ex4_000_so[0]}; + assign f_sa3_so = act_so[0]; + +endmodule diff --git a/dev/verilog/work/fu_sto.v b/dev/verilog/work/fu_sto.v new file mode 100755 index 0000000..10ca111 --- /dev/null +++ b/dev/verilog/work/fu_sto.v @@ -0,0 +1,882 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ +//@@ replicate critical select latch to PO +//@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ + +//xxx_lcbor: tri_lcbor generic map (expand_type => expand_type ) port map ( +// clkoff_b => clkoff_b, +// thold => pc_func_sl_thold_0(0), +// sg => pc_sg_0(0), +// act_dis => act_dis, +// force => force, +// thold_b => pc_func_sl_thold_0_b ); +// +// print "alter --d_mode 0 b\n"; +// print "alter delay_lclkr 0 b\n"; +// print "alter mpw1_b 1 b\n"; +// print "alter mpw2_b 1 b\n"; +// print "alter clkoff_b 1 b\n"; +// print "alter dis_act 0 b\n"; +// print "alter scan_diag 0 b\n"; + +// PPC FP STORE reformating +// (1) DP STORE : sp_denorm needs to normalize +// (2) SP STORE : dp_norm may need to denormalize +// (3) stfwix : pass througn + + `include "tri_a2o.vh" + + +module fu_sto( + vdd, + gnd, + clkoff_b, + act_dis, + flush, + delay_lclkr, + mpw1_b, + mpw2_b, + sg_1, + thold_1, + fpu_enable, + nclk, + f_sto_si, + f_sto_so, + f_dcd_ex1_sto_act, + f_dcd_ex1_sto_v, + f_fpr_ex2_s_expo_extra, + f_fpr_ex2_s_par, + f_sto_ex3_s_parity_check, + f_dcd_ex1_sto_dp, + f_dcd_ex1_sto_sp, + f_dcd_ex1_sto_wd, + f_byp_ex1_s_sign, + f_byp_ex1_s_expo, + f_byp_ex1_s_frac, + f_sto_ex3_sto_data +); + inout vdd; + inout gnd; + input clkoff_b; // tiup + input act_dis; // ??tidn?? + input flush; // ??tidn?? + input [1:2] delay_lclkr; // tidn, + input [1:2] mpw1_b; // tidn, + input [0:0] mpw2_b; // tidn, + input sg_1; + input thold_1; + input fpu_enable; //dc_act + input [0:`NCLK_WIDTH-1] nclk; + + input f_sto_si; + output f_sto_so; + input f_dcd_ex1_sto_act; + input f_dcd_ex1_sto_v; + + input [0:1] f_fpr_ex2_s_expo_extra; + input [0:7] f_fpr_ex2_s_par; + output f_sto_ex3_s_parity_check; // raw calculation + + input f_dcd_ex1_sto_dp; + input f_dcd_ex1_sto_sp; + input f_dcd_ex1_sto_wd; + + input f_byp_ex1_s_sign; + input [1:11] f_byp_ex1_s_expo; + input [0:52] f_byp_ex1_s_frac; + + output [0:63] f_sto_ex3_sto_data; + + // end ports + + // ENTITY + + + parameter tiup = 1'b1; + parameter tidn = 1'b0; + + wire sg_0; + wire thold_0_b; + wire thold_0; + + wire ex1_act; + + wire ex2_act; + + (* analysis_not_referenced="TRUE" *) + wire [0:1] spare_unused; + + //----------------- + wire [0:3] act_so; //SCAN + wire [0:3] act_si; //SCAN + wire [0:2] ex2_sins_so; + wire [0:2] ex2_sins_si; + wire [0:64] ex2_sop_so; + wire [0:64] ex2_sop_si; + wire [0:72] ex3_sto_so; + wire [0:72] ex3_sto_si; + //----------------- + wire ex2_s_sign; + wire [1:11] ex2_s_expo; + wire [0:52] ex2_s_frac; + wire [0:63] ex2_sto_data; + wire [0:63] ex3_sto_data; + wire ex2_sto_dp; + wire ex2_sto_sp; + wire ex2_sto_wd; + wire ex2_den_ramt8_02; + wire ex2_den_ramt8_18; + wire ex2_den_ramt4_12; + wire ex2_den_ramt4_08; + wire ex2_den_ramt4_04; + wire ex2_den_ramt4_00; + wire ex2_den_ramt1_03; + wire ex2_den_ramt1_02; + wire ex2_den_ramt1_01; + wire ex2_den_ramt1_00; + wire ex2_expo_eq896; + wire ex2_expo_ge896; + wire ex2_expo_lt896; + wire ex2_sts_lt896; + wire ex2_sts_ge896; + wire ex2_sts_expo_nz; + wire ex2_fixden; + wire ex2_fixden_small; + wire ex2_fixden_big; + wire ex2_std_nonden; + wire ex2_std_fixden_big; + wire ex2_std_fixden_small; + wire ex2_std_nonbig; + wire ex2_std_nonden_wd; + wire ex2_std_lamt8_02; + wire ex2_std_lamt8_10; + wire ex2_std_lamt8_18; + wire ex2_std_lamt2_0; + wire ex2_std_lamt2_2; + wire ex2_std_lamt2_4; + wire ex2_std_lamt2_6; + wire ex2_std_lamt1_0; + wire ex2_std_lamt1_1; + wire [0:23] ex2_sts_sh8; + wire [0:23] ex2_sts_sh4; + wire [0:23] ex2_sts_sh1; + wire [0:23] ex2_sts_nrm; + wire [1:23] ex2_sts_frac; + wire [1:8] ex2_sts_expo; + wire [0:10] ex2_clz02_or; + wire [0:10] ex2_clz02_enc4; + wire [0:5] ex2_clz04_or; + wire [0:5] ex2_clz04_enc3; + wire [0:5] ex2_clz04_enc4; + wire [0:2] ex2_clz08_or; + wire [0:2] ex2_clz08_enc2; + wire [0:2] ex2_clz08_enc3; + wire [0:2] ex2_clz08_enc4; + wire [0:1] ex2_clz16_or; + wire [0:1] ex2_clz16_enc1; + wire [0:1] ex2_clz16_enc2; + wire [0:1] ex2_clz16_enc3; + wire [0:1] ex2_clz16_enc4; + wire [0:4] ex2_sto_clz; + wire [1:11] ex2_expo_nonden; + wire [1:11] ex2_expo_fixden; + wire [1:11] ex2_std_expo; + wire [1:52] ex2_std_frac_nrm; + wire [0:23] ex2_std_sh8; + wire [0:23] ex2_std_sh2; + wire [1:23] ex2_std_frac_den; + wire ex2_ge874; + wire ex2_any_edge; + wire [0:63] ex3_sto_data_rot0_b; + wire [0:63] ex3_sto_data_rot1_b; + + wire [0:3] ex3_sto_wd; + wire [0:3] ex3_sto_sp; + wire force_t; + + wire ex2_s_party_chick; + wire ex3_s_party_chick; + wire [0:7] ex2_s_party; + + wire ex2_sto_v; + + + (* analysis_not_referenced="TRUE" *) // unused + wire [0:1] unused; + + ////############################################ + ////# pervasive + ////############################################ + + assign unused[0] = ex2_sts_sh1[0] | ex2_sts_nrm[0] | ex2_std_sh2[0]; + + + tri_plat thold_reg_0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(flush), + .din(thold_1), + .q(thold_0) + ); + + + tri_plat sg_reg_0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(flush), + .din(sg_1), + .q(sg_0) + ); + + + tri_lcbor lcbor_0( + .clkoff_b(clkoff_b), + .thold(thold_0), + .sg(sg_0), + .act_dis(act_dis), + .force_t(force_t), + .thold_b(thold_0_b) + ); + + ////############################################ + ////# ACT LATCHES + ////############################################ + + assign ex1_act = f_dcd_ex1_sto_act; + + tri_rlmreg_p #(.WIDTH(4)) act_lat( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .force_t(force_t), // tidn + .d_mode(tiup), + .delay_lclkr(delay_lclkr[1]), // tidn, + .mpw1_b(mpw1_b[1]), // tidn, + .mpw2_b(mpw2_b[0]), // tidn, + .act(tiup), + .thold_b(thold_0_b), + .sg(sg_0), + .scout(act_so), + .scin(act_si), + //----------------- + .din({ ex1_act, + spare_unused[0], + spare_unused[1], + f_dcd_ex1_sto_v}), + //----------------- + .dout({ ex2_act, + spare_unused[0], + spare_unused[1], + ex2_sto_v}) + ); + assign unused[1] = ex2_sto_v; + + + ////############################################## + ////# EX2 latch inputs from ex1 + ////############################################## + + + tri_rlmreg_p #(.WIDTH(3), .IBUF(1'B1)) ex2_sins_lat( + .force_t(force_t), //tidn, + .d_mode(tiup), + .delay_lclkr(delay_lclkr[1]), //tidn, + .mpw1_b(mpw1_b[1]), //tidn, + .mpw2_b(mpw2_b[0]), //tidn, + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + .act(ex1_act), + .vd(vdd), + .gd(gnd), + .scout(ex2_sins_so), + .scin(ex2_sins_si), + //----------------- + .din({ f_dcd_ex1_sto_dp, + f_dcd_ex1_sto_sp, + f_dcd_ex1_sto_wd}), + //----------------- + .dout({ ex2_sto_dp, + ex2_sto_sp, + ex2_sto_wd}) + ); + + + tri_rlmreg_p #(.WIDTH(65), .NEEDS_SRESET(0), .IBUF(1'B1)) ex2_sop_lat( + .force_t(force_t), //tidn, + .d_mode(tiup), + .delay_lclkr(delay_lclkr[1]), //tidn, + .mpw1_b(mpw1_b[1]), //tidn, + .mpw2_b(mpw2_b[0]), //tidn, + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + .act(ex1_act), + .vd(vdd), + .gd(gnd), + .scout(ex2_sop_so), + .scin(ex2_sop_si), + //----------------- + .din({ f_byp_ex1_s_sign, + f_byp_ex1_s_expo[1:11], + f_byp_ex1_s_frac[0:52]}), + //----------------- + .dout({ ex2_s_sign, + ex2_s_expo[1:11], + ex2_s_frac[0:52]}) + ); + + ////############################################## + ////# EX2 logic + ////############################################## + + ////################################################### + ////# shifting for store sp + ////################################################### + // output of dp instr with expo below x381 needs to denormalize to sp format. + // x380 d896 011_1000_0000 => right 1 11 11 11 <== treat as special case + // x37F d895 011_0111_1111 => right 2 00 00 00 + // x37E d894 011_0111_1110 => right 3 00 00 01 + // x37D d893 011_0111_1101 => right 4 00 00 10 + // x37C d892 011_0111_1100 => right 5 00 00 11 + // x37B d891 011_0111_1011 => right 6 00 01 00 + // x37A d890 011_0111_1010 => right 7 00 01 01 + // x379 d889 011_0111_1001 => right 8 00 01 10 + // x378 d888 011_0111_1000 => right 9 00 01 11 + // x377 d887 011_0111_0111 => right 10 00 10 00 + // x376 d886 011_0111_0110 => right 11 00 10 01 + // x375 d885 011_0111_0101 => right 12 00 10 10 + // x374 d884 011_0111_0100 => right 13 00 10 11 + // x373 d883 011_0111_0011 => right 14 00 11 00 + // x372 d882 011_0111_0010 => right 15 00 11 01 + // x371 d881 011_0111_0001 => right 16 00 11 10 + // x370 d880 011_0111_0000 => right 17 00 11 11 + // x36F d879 011_0110_1111 => right 18 01 00 00 + // x36E d878 011_0110_1110 => right 19 01 00 01 + // x36B d877 011_0110_1101 => right 20 01 00 10 + // x36C d876 011_0110_1100 => right 21 01 00 11 + // x36B d875 011_0110_1011 => right 22 01 01 00 + // x36A d874 011_0110_1010 => right 23 01 01 01 + // x369 d873 011_0110_1001 => right 24 01 01 10 ===> result is zero after here + //------------------------ + // 000 0000 0011 + // 123 4567 8901 + + assign ex2_den_ramt8_02 = ex2_s_expo[6] & ex2_s_expo[7]; + assign ex2_den_ramt8_18 = ex2_s_expo[6] & (~ex2_s_expo[7]); + + assign ex2_den_ramt4_12 = (~ex2_s_expo[8]) & (~ex2_s_expo[9]); + assign ex2_den_ramt4_08 = (~ex2_s_expo[8]) & ex2_s_expo[9]; + assign ex2_den_ramt4_04 = ex2_s_expo[8] & (~ex2_s_expo[9]); + assign ex2_den_ramt4_00 = ex2_s_expo[8] & ex2_s_expo[9]; + + assign ex2_den_ramt1_03 = (~ex2_s_expo[10]) & (~ex2_s_expo[11]); + assign ex2_den_ramt1_02 = (~ex2_s_expo[10]) & ex2_s_expo[11]; + assign ex2_den_ramt1_01 = ex2_s_expo[10] & (~ex2_s_expo[11]); + assign ex2_den_ramt1_00 = ex2_s_expo[10] & ex2_s_expo[11]; + + assign ex2_expo_eq896 = (~ex2_s_expo[1]) & ex2_s_expo[2] & ex2_s_expo[3] & ex2_s_expo[4] & (~ex2_s_expo[5]) & (~ex2_s_expo[6]) & (~ex2_s_expo[7]) & (~ex2_s_expo[8]) & (~ex2_s_expo[9]) & (~ex2_s_expo[10]) & (~ex2_s_expo[11]); // 011_1000_0000 + + assign ex2_expo_ge896 = (ex2_s_expo[1]) | (ex2_s_expo[2] & ex2_s_expo[3] & ex2_s_expo[4]); + + assign ex2_ge874 = (ex2_s_expo[1]) | (ex2_s_expo[2] & ex2_s_expo[3] & ex2_s_expo[4]) | (ex2_s_expo[2] & ex2_s_expo[3] & ex2_s_expo[5] & ex2_s_expo[6]); // 011_0110_1010 -- enough so shifter does not wrap 011_0110_xxxx + + assign ex2_expo_lt896 = (~ex2_expo_ge896); + assign ex2_sts_lt896 = ex2_sto_sp & ex2_expo_lt896 & ex2_ge874; // result = zero when lt 874 + assign ex2_sts_ge896 = ex2_sto_sp & ex2_expo_ge896; + + assign ex2_sts_sh8[0:23] = ({24{ex2_den_ramt8_02}} & ({{2{tidn}}, ex2_s_frac[0:21]})) | + ({24{ex2_den_ramt8_18}} & ({{18{tidn}}, ex2_s_frac[0:5]})); + + assign ex2_sts_sh4[0:23] = ({24{ex2_den_ramt4_12}} & ({{12{tidn}}, ex2_sts_sh8[0:11]})) | + ({24{ex2_den_ramt4_08}} & ({{8{tidn}}, ex2_sts_sh8[0:15]})) | + ({24{ex2_den_ramt4_04}} & ({{4{tidn}}, ex2_sts_sh8[0:19]})) | + ({24{ex2_den_ramt4_00}} & (ex2_sts_sh8[0:23])); + + assign ex2_sts_sh1[0:23] = ({24{ex2_den_ramt1_03}} & ({{3{tidn}}, ex2_sts_sh4[0:20]})) | + ({24{ex2_den_ramt1_02}} & ({{2{tidn}}, ex2_sts_sh4[0:21]})) | + ({24{ex2_den_ramt1_01}} & ({tidn, ex2_sts_sh4[0:22]})) | + ({24{ex2_den_ramt1_00}} & (ex2_sts_sh4[0:23])); + + assign ex2_sts_nrm[0:23] = ({24{ex2_expo_eq896}} & ({tidn, ex2_s_frac[0:22]})) | + ({24{(~ex2_expo_eq896)}} & (ex2_s_frac[0:23])); + + assign ex2_sts_frac[1:23] = ({23{ex2_sts_lt896}} & ex2_sts_sh1[1:23]) | + ({23{ex2_sts_ge896}} & ex2_sts_nrm[1:23]); + + ////################################################### + ////# store_sp : calc shift amount : + ////################################################### + + assign ex2_sts_expo_nz = ex2_sto_sp & ex2_expo_ge896; + assign ex2_sts_expo[1] = ex2_s_expo[1] & ex2_sts_expo_nz; + assign ex2_sts_expo[2:7] = ex2_s_expo[5:10] & {6{ex2_sts_expo_nz}}; + assign ex2_sts_expo[8] = ex2_s_expo[11] & ex2_s_frac[0] & ex2_sts_expo_nz; + + ////################################################### + ////# normalization shift left amount for store_dp + ////################################################### + // count leading zeroes to get the shift amount + //bit pos dp_expo bin_expo inv clz lsb shift left to norm + // + // 00 x381 011_1000_0001 1_1110 00 0_0000 <== normal + // 01 x380 011_1000_0000 1_1111 01 0_0001 + // 02 x37F 011_0111_1111 0_0000 02 0_0010 <=== start clz on bit 2; + // 03 x37E 011_0111_1110 0_0001 03 0_0010 + // 04 x37D 011_0111_1101 0_0010 04 0_0010 + // 05 x37C 011_0111_1100 0_0011 05 0_0010 + // 06 x37B 011_0111_1011 0_0100 06 0_0010 + // 07 x37A 011_0111_1010 0_0101 07 0_0010 + // 08 x379 011_0111_1001 0_0110 08 0_0010 + // 09 x378 011_0111_1000 0_0111 09 0_0010 + // 10 x377 011_0111_0111 0_1000 10 0_0010 + // 11 x376 011_0111_0110 0_1001 11 0_0010 + // 12 x375 011_0111_0101 0_1010 12 0_0010 + // 13 x374 011_0111_0100 0_1011 13 0_0010 + // 14 x373 011_0111_0011 0_1100 14 0_0010 + // 15 x372 011_0111_0010 0_1101 15 0_0010 + // 16 x371 011_0111_0001 0_1110 16 0_0010 + // 17 x370 011_0111_0000 0_1111 17 0_0010 + // 18 x36F 011_0110_1111 1_0000 18 0_0010 + // 19 x36E 011_0110_1110 1_0001 19 0_0010 + // 20 x36D 011_0110_1101 1_0010 20 0_0010 + // 21 x36C 011_0110_1100 1_0011 21 0_0010 + // 22 x36B 011_0110_1011 1_0100 22 0_0010 + // 23 x36A 011_0110_1010 1_0101 23 0_0010 + + // if clz does not find leading bit (shift of 0 is ok) + + assign ex2_clz02_or[0] = ex2_s_frac[2] | ex2_s_frac[3]; + assign ex2_clz02_enc4[0] = (~ex2_s_frac[2]) & ex2_s_frac[3]; + + assign ex2_clz02_or[1] = ex2_s_frac[4] | ex2_s_frac[5]; + assign ex2_clz02_enc4[1] = (~ex2_s_frac[4]) & ex2_s_frac[5]; + + assign ex2_clz02_or[2] = ex2_s_frac[6] | ex2_s_frac[7]; + assign ex2_clz02_enc4[2] = (~ex2_s_frac[6]) & ex2_s_frac[7]; + + assign ex2_clz02_or[3] = ex2_s_frac[8] | ex2_s_frac[9]; + assign ex2_clz02_enc4[3] = (~ex2_s_frac[8]) & ex2_s_frac[9]; + + assign ex2_clz02_or[4] = ex2_s_frac[10] | ex2_s_frac[11]; + assign ex2_clz02_enc4[4] = (~ex2_s_frac[10]) & ex2_s_frac[11]; + + assign ex2_clz02_or[5] = ex2_s_frac[12] | ex2_s_frac[13]; + assign ex2_clz02_enc4[5] = (~ex2_s_frac[12]) & ex2_s_frac[13]; + + assign ex2_clz02_or[6] = ex2_s_frac[14] | ex2_s_frac[15]; + assign ex2_clz02_enc4[6] = (~ex2_s_frac[14]) & ex2_s_frac[15]; + + assign ex2_clz02_or[7] = ex2_s_frac[16] | ex2_s_frac[17]; + assign ex2_clz02_enc4[7] = (~ex2_s_frac[16]) & ex2_s_frac[17]; + + assign ex2_clz02_or[8] = ex2_s_frac[18] | ex2_s_frac[19]; + assign ex2_clz02_enc4[8] = (~ex2_s_frac[18]) & ex2_s_frac[19]; + + assign ex2_clz02_or[9] = ex2_s_frac[20] | ex2_s_frac[21]; + assign ex2_clz02_enc4[9] = (~ex2_s_frac[20]) & ex2_s_frac[21]; + + assign ex2_clz02_or[10] = ex2_s_frac[22] | ex2_s_frac[23]; + assign ex2_clz02_enc4[10] = (~ex2_s_frac[22]) & ex2_s_frac[23]; + + assign ex2_clz04_or[0] = ex2_clz02_or[0] | ex2_clz02_or[1]; + assign ex2_clz04_enc3[0] = (~ex2_clz02_or[0]) & ex2_clz02_or[1]; + assign ex2_clz04_enc4[0] = ex2_clz02_enc4[0] | ((~ex2_clz02_or[0]) & ex2_clz02_enc4[1]); + + assign ex2_clz04_or[1] = ex2_clz02_or[2] | ex2_clz02_or[3]; + assign ex2_clz04_enc3[1] = (~ex2_clz02_or[2]) & ex2_clz02_or[3]; + assign ex2_clz04_enc4[1] = ex2_clz02_enc4[2] | ((~ex2_clz02_or[2]) & ex2_clz02_enc4[3]); + + assign ex2_clz04_or[2] = ex2_clz02_or[4] | ex2_clz02_or[5]; + assign ex2_clz04_enc3[2] = (~ex2_clz02_or[4]) & ex2_clz02_or[5]; + assign ex2_clz04_enc4[2] = ex2_clz02_enc4[4] | ((~ex2_clz02_or[4]) & ex2_clz02_enc4[5]); + + assign ex2_clz04_or[3] = ex2_clz02_or[6] | ex2_clz02_or[7]; + assign ex2_clz04_enc3[3] = (~ex2_clz02_or[6]) & ex2_clz02_or[7]; + assign ex2_clz04_enc4[3] = ex2_clz02_enc4[6] | ((~ex2_clz02_or[6]) & ex2_clz02_enc4[7]); + + assign ex2_clz04_or[4] = ex2_clz02_or[8] | ex2_clz02_or[9]; + assign ex2_clz04_enc3[4] = (~ex2_clz02_or[8]) & ex2_clz02_or[9]; + assign ex2_clz04_enc4[4] = ex2_clz02_enc4[8] | ((~ex2_clz02_or[8]) & ex2_clz02_enc4[9]); + + assign ex2_clz04_or[5] = ex2_clz02_or[10]; + assign ex2_clz04_enc3[5] = tidn; + assign ex2_clz04_enc4[5] = ex2_clz02_enc4[10]; + + assign ex2_clz08_or[0] = ex2_clz04_or[0] | ex2_clz04_or[1]; + assign ex2_clz08_enc2[0] = (~ex2_clz04_or[0]) & ex2_clz04_or[1]; + assign ex2_clz08_enc3[0] = ex2_clz04_enc3[0] | ((~ex2_clz04_or[0]) & ex2_clz04_enc3[1]); + assign ex2_clz08_enc4[0] = ex2_clz04_enc4[0] | ((~ex2_clz04_or[0]) & ex2_clz04_enc4[1]); + + assign ex2_clz08_or[1] = ex2_clz04_or[2] | ex2_clz04_or[3]; + assign ex2_clz08_enc2[1] = (~ex2_clz04_or[2]) & ex2_clz04_or[3]; + assign ex2_clz08_enc3[1] = ex2_clz04_enc3[2] | ((~ex2_clz04_or[2]) & ex2_clz04_enc3[3]); + assign ex2_clz08_enc4[1] = ex2_clz04_enc4[2] | ((~ex2_clz04_or[2]) & ex2_clz04_enc4[3]); + + assign ex2_clz08_or[2] = ex2_clz04_or[4] | ex2_clz04_or[5]; + assign ex2_clz08_enc2[2] = (~ex2_clz04_or[4]) & ex2_clz04_or[5]; + assign ex2_clz08_enc3[2] = ex2_clz04_enc3[4] | ((~ex2_clz04_or[4]) & ex2_clz04_enc3[5]); + assign ex2_clz08_enc4[2] = ex2_clz04_enc4[4] | ((~ex2_clz04_or[4]) & ex2_clz04_enc4[5]); + + assign ex2_clz16_or[0] = ex2_clz08_or[0] | ex2_clz08_or[1]; + assign ex2_clz16_enc1[0] = (~ex2_clz08_or[0]) & ex2_clz08_or[1]; + assign ex2_clz16_enc2[0] = ex2_clz08_enc2[0] | ((~ex2_clz08_or[0]) & ex2_clz08_enc2[1]); + assign ex2_clz16_enc3[0] = ex2_clz08_enc3[0] | ((~ex2_clz08_or[0]) & ex2_clz08_enc3[1]); + assign ex2_clz16_enc4[0] = ex2_clz08_enc4[0] | ((~ex2_clz08_or[0]) & ex2_clz08_enc4[1]); + + assign ex2_clz16_or[1] = ex2_clz08_or[2]; + assign ex2_clz16_enc1[1] = tidn; + assign ex2_clz16_enc2[1] = ex2_clz08_enc2[2]; + assign ex2_clz16_enc3[1] = ex2_clz08_enc3[2]; + assign ex2_clz16_enc4[1] = ex2_clz08_enc4[2]; + + assign ex2_sto_clz[0] = (~ex2_clz16_or[0]) & ex2_clz16_or[1]; + assign ex2_sto_clz[1] = ex2_clz16_enc1[0] | ((~ex2_clz16_or[0]) & ex2_clz16_enc1[1]); + assign ex2_sto_clz[2] = ex2_clz16_enc2[0] | ((~ex2_clz16_or[0]) & ex2_clz16_enc2[1]); + assign ex2_sto_clz[3] = ex2_clz16_enc3[0] | ((~ex2_clz16_or[0]) & ex2_clz16_enc3[1]); + assign ex2_sto_clz[4] = ex2_clz16_enc4[0] | ((~ex2_clz16_or[0]) & ex2_clz16_enc4[1]); + + assign ex2_any_edge = (ex2_clz16_or[0] | ex2_clz16_or[1]); + + ////################################################### + ////# exponent for store dp + ////################################################### + // exponent must be zero when input is zero x001 * !imp + + assign ex2_fixden = ex2_s_expo[2] & (~ex2_s_frac[0]); // sp denorm or zero + assign ex2_fixden_small = ex2_s_expo[2] & (~ex2_s_frac[0]) & ex2_s_frac[1]; + assign ex2_fixden_big = ex2_s_expo[2] & (~ex2_s_frac[0]) & (~ex2_s_frac[1]); + + assign ex2_std_nonden = ex2_sto_dp & (~ex2_fixden); + assign ex2_std_fixden_big = ex2_sto_dp & ex2_fixden_big; // denorm more than 1 + assign ex2_std_fixden_small = ex2_sto_dp & ex2_fixden_small; // denorm by 1 + assign ex2_std_nonbig = ex2_sto_dp & (~ex2_fixden_big); + + // dp denorm/zero turn of expo lsb + // sp denorm(1) goes to x380 (turn off lsb) + assign ex2_expo_nonden[1:10] = ex2_s_expo[1:10] & {10{ex2_std_nonbig}}; + assign ex2_expo_nonden[11] = ex2_s_expo[11] & ex2_s_frac[0] & ex2_std_nonden; + + assign ex2_expo_fixden[1] = tidn; // 011_011x_xxx + assign ex2_expo_fixden[2] = ex2_any_edge; // 011_011x_xxx + assign ex2_expo_fixden[3] = ex2_any_edge; // 011_011x_xxx + assign ex2_expo_fixden[4] = tidn; // 011_011x_xxx + assign ex2_expo_fixden[5] = ex2_any_edge; // 011_011x_xxx + assign ex2_expo_fixden[6] = ex2_any_edge; // 011_011x_xxx + assign ex2_expo_fixden[7:11] = (~ex2_sto_clz[0:4]) & {5{ex2_any_edge}}; + + assign ex2_std_expo[1:11] = (ex2_expo_nonden[1:11]) | + (ex2_expo_fixden[1:11] & {11{ex2_std_fixden_big}}); + + ////######################################################################### + ////# shifting for store dp + ////######################################################################### + + assign ex2_std_nonden_wd = ex2_std_nonden | ex2_sto_wd; + + assign ex2_std_frac_nrm[1:20] = (ex2_s_frac[2:21] & {20{ex2_std_fixden_small}}) | + (ex2_s_frac[1:20] & {20{ex2_std_nonden}}); + assign ex2_std_frac_nrm[21:52] = (({ex2_s_frac[22:52], tidn}) & {32{ex2_std_fixden_small}}) | + (ex2_s_frac[21:52] & {32{ex2_std_nonden_wd}}); // stfiwx has a 32 bit result f[21:52] + + assign ex2_std_lamt8_02 = (~ex2_sto_clz[0]) & (~ex2_sto_clz[1]); // 0 + 2 + assign ex2_std_lamt8_10 = (~ex2_sto_clz[0]) & ex2_sto_clz[1]; // 8 + 2 + assign ex2_std_lamt8_18 = ex2_sto_clz[0] & (~ex2_sto_clz[1]); //16 + 2 + + assign ex2_std_lamt2_0 = (~ex2_sto_clz[2]) & (~ex2_sto_clz[3]); + assign ex2_std_lamt2_2 = (~ex2_sto_clz[2]) & ex2_sto_clz[3]; + assign ex2_std_lamt2_4 = ex2_sto_clz[2] & (~ex2_sto_clz[3]); + assign ex2_std_lamt2_6 = ex2_sto_clz[2] & ex2_sto_clz[3]; + + assign ex2_std_lamt1_0 = ex2_std_fixden_big & (~ex2_sto_clz[4]); + assign ex2_std_lamt1_1 = ex2_std_fixden_big & ex2_sto_clz[4]; + + //@-- -- if the input was an sp denorm (sp format) then there are only 24 input bits [0:23] + + assign ex2_std_sh8[0:23] = (({ex2_s_frac[2:23], {2{tidn}}}) & {24{ex2_std_lamt8_02}}) | + (({ex2_s_frac[10:23], {10{tidn}}}) & {24{ex2_std_lamt8_10}}) | + (({ex2_s_frac[18:23], {18{tidn}}}) & {24{ex2_std_lamt8_18}}); + + assign ex2_std_sh2[0:23] = (ex2_std_sh8[0:23] & {24{ex2_std_lamt2_0}}) | + (({ex2_std_sh8[2:23], {2{tidn}}}) & {24{ex2_std_lamt2_2}}) | + (({ex2_std_sh8[4:23], {4{tidn}}}) & {24{ex2_std_lamt2_4}}) | + (({ex2_std_sh8[6:23], {6{tidn}}}) & {24{ex2_std_lamt2_6}}); + + assign ex2_std_frac_den[1:23] = (ex2_std_sh2[1:23] & {23{ex2_std_lamt1_0}}) | + (({ex2_std_sh2[2:23], tidn}) & {23{ex2_std_lamt1_1}}); + + ////################################################### + ////# final combinations + ////################################################### + + assign ex2_sto_data[0] = ex2_s_sign & (~ex2_sto_wd); // sign bit + + assign ex2_sto_data[1:8] = ex2_sts_expo[1:8] | ex2_std_expo[1:8]; + + assign ex2_sto_data[9:11] = ex2_sts_frac[1:3] | ex2_std_expo[9:11]; + + assign ex2_sto_data[12:31] = ex2_sts_frac[4:23] | ex2_std_frac_nrm[1:20] | ex2_std_frac_den[1:20]; + + assign ex2_sto_data[32:34] = ex2_std_frac_nrm[21:23] | ex2_std_frac_den[21:23]; //03 bits (includes stfwix) + + assign ex2_sto_data[35:63] = ex2_std_frac_nrm[24:52]; //29 bits (includes stfwix) + + ////############################################## + ////# EX3 latches + ////############################################## + + + tri_rlmreg_p #(.WIDTH(73), .NEEDS_SRESET(0), .IBUF(1'B1)) ex3_sto_lat( + .force_t(force_t), //tidn, + .d_mode(tiup), + .delay_lclkr(delay_lclkr[2]), //tidn, + .mpw1_b(mpw1_b[2]), //tidn, + .mpw2_b(mpw2_b[0]), //tidn, + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + .act(ex2_act), + .vd(vdd), + .gd(gnd), + .scout(ex3_sto_so), + .scin(ex3_sto_si), + //----------------- + .din({ ex2_sto_data[0:63], + ex2_sto_sp, + ex2_sto_sp, + ex2_sto_sp, + ex2_sto_sp, + ex2_sto_wd, + ex2_sto_wd, + ex2_sto_wd, + ex2_sto_wd, + ex2_s_party_chick}), + + .dout({ ex3_sto_data[0:63], //LAT-- + ex3_sto_sp[0], //LAT-- + ex3_sto_sp[1], //LAT-- + ex3_sto_sp[2], //LAT-- + ex3_sto_sp[3], //LAT-- + ex3_sto_wd[0], //LAT-- + ex3_sto_wd[1], //LAT-- + ex3_sto_wd[2], //LAT-- + ex3_sto_wd[3], //LAT-- + ex3_s_party_chick}) //LAT-- + ); + + assign f_sto_ex3_s_parity_check = ex3_s_party_chick; + + // 1 unused + // 2 xx + // 3 1 + // 4 2 + // 5 3 + // 6 4 + // 7 5 + // 8 6 + // 9 7 + // 10 8 + // 11 9 + // 12 10 + // 13 11 + + assign ex2_s_party[0] = ex2_s_sign ^ f_fpr_ex2_s_expo_extra[0] ^ f_fpr_ex2_s_expo_extra[1] ^ ex2_s_expo[1] ^ ex2_s_expo[2] ^ ex2_s_expo[3] ^ ex2_s_expo[4] ^ ex2_s_expo[5] ^ ex2_s_expo[6] ^ ex2_s_expo[7]; + assign ex2_s_party[1] = ex2_s_expo[8] ^ ex2_s_expo[9] ^ ex2_s_expo[10] ^ ex2_s_expo[11] ^ ex2_s_frac[0] ^ ex2_s_frac[1] ^ ex2_s_frac[2] ^ ex2_s_frac[3] ^ ex2_s_frac[4]; + assign ex2_s_party[2] = ex2_s_frac[5] ^ ex2_s_frac[6] ^ ex2_s_frac[7] ^ ex2_s_frac[8] ^ ex2_s_frac[9] ^ ex2_s_frac[10] ^ ex2_s_frac[11] ^ ex2_s_frac[12]; + assign ex2_s_party[3] = ex2_s_frac[13] ^ ex2_s_frac[14] ^ ex2_s_frac[15] ^ ex2_s_frac[16] ^ ex2_s_frac[17] ^ ex2_s_frac[18] ^ ex2_s_frac[19] ^ ex2_s_frac[20]; + assign ex2_s_party[4] = ex2_s_frac[21] ^ ex2_s_frac[22] ^ ex2_s_frac[23] ^ ex2_s_frac[24] ^ ex2_s_frac[25] ^ ex2_s_frac[26] ^ ex2_s_frac[27] ^ ex2_s_frac[28]; + assign ex2_s_party[5] = ex2_s_frac[29] ^ ex2_s_frac[30] ^ ex2_s_frac[31] ^ ex2_s_frac[32] ^ ex2_s_frac[33] ^ ex2_s_frac[34] ^ ex2_s_frac[35] ^ ex2_s_frac[36]; + assign ex2_s_party[6] = ex2_s_frac[37] ^ ex2_s_frac[38] ^ ex2_s_frac[39] ^ ex2_s_frac[40] ^ ex2_s_frac[41] ^ ex2_s_frac[42] ^ ex2_s_frac[43] ^ ex2_s_frac[44]; + assign ex2_s_party[7] = ex2_s_frac[45] ^ ex2_s_frac[46] ^ ex2_s_frac[47] ^ ex2_s_frac[48] ^ ex2_s_frac[49] ^ ex2_s_frac[50] ^ ex2_s_frac[51] ^ ex2_s_frac[52]; + + assign ex2_s_party_chick = (ex2_s_party[0] ^ f_fpr_ex2_s_par[0]) | (ex2_s_party[1] ^ f_fpr_ex2_s_par[1]) | (ex2_s_party[2] ^ f_fpr_ex2_s_par[2]) | (ex2_s_party[3] ^ f_fpr_ex2_s_par[3]) | (ex2_s_party[4] ^ f_fpr_ex2_s_par[4]) | (ex2_s_party[5] ^ f_fpr_ex2_s_par[5]) | (ex2_s_party[6] ^ f_fpr_ex2_s_par[6]) | (ex2_s_party[7] ^ f_fpr_ex2_s_par[7]); + + ////############################################## + ////# EX3 logic + ////############################################## + //@@ ex3_sto_data_rot(0 to 31) <= + //@@ ( ex3_sto_data( 0 to 31) and ( 0 to 31=> not ex3_sto_wd) ) or + //@@ ( ex3_sto_data(32 to 63) and ( 0 to 31=> ex3_sto_wd) ); + //@@ + //@@ ex3_sto_data_rot(32 to 63) <= + //@@ ( ex3_sto_data( 0 to 31) and (32 to 63=> ex3_sto_sp) ) or + //@@ ( ex3_sto_data(32 to 63) and (32 to 63=> not ex3_sto_sp) ); + //@@ + //@@ + //@@ f_sto_ex3_sto_data( 0 to 63) <= ex3_sto_data_rot(0 to 63); + //@@ + + assign ex3_sto_data_rot0_b[0] = (~(ex3_sto_data[0] & (~ex3_sto_wd[0]))); + assign ex3_sto_data_rot0_b[1] = (~(ex3_sto_data[1] & (~ex3_sto_wd[0]))); + assign ex3_sto_data_rot0_b[2] = (~(ex3_sto_data[2] & (~ex3_sto_wd[0]))); + assign ex3_sto_data_rot0_b[3] = (~(ex3_sto_data[3] & (~ex3_sto_wd[0]))); + assign ex3_sto_data_rot0_b[4] = (~(ex3_sto_data[4] & (~ex3_sto_wd[0]))); + assign ex3_sto_data_rot0_b[5] = (~(ex3_sto_data[5] & (~ex3_sto_wd[0]))); + assign ex3_sto_data_rot0_b[6] = (~(ex3_sto_data[6] & (~ex3_sto_wd[0]))); + assign ex3_sto_data_rot0_b[7] = (~(ex3_sto_data[7] & (~ex3_sto_wd[0]))); + assign ex3_sto_data_rot0_b[8] = (~(ex3_sto_data[8] & (~ex3_sto_wd[1]))); + assign ex3_sto_data_rot0_b[9] = (~(ex3_sto_data[9] & (~ex3_sto_wd[1]))); + assign ex3_sto_data_rot0_b[10] = (~(ex3_sto_data[10] & (~ex3_sto_wd[1]))); + assign ex3_sto_data_rot0_b[11] = (~(ex3_sto_data[11] & (~ex3_sto_wd[1]))); + assign ex3_sto_data_rot0_b[12] = (~(ex3_sto_data[12] & (~ex3_sto_wd[1]))); + assign ex3_sto_data_rot0_b[13] = (~(ex3_sto_data[13] & (~ex3_sto_wd[1]))); + assign ex3_sto_data_rot0_b[14] = (~(ex3_sto_data[14] & (~ex3_sto_wd[1]))); + assign ex3_sto_data_rot0_b[15] = (~(ex3_sto_data[15] & (~ex3_sto_wd[1]))); + assign ex3_sto_data_rot0_b[16] = (~(ex3_sto_data[16] & (~ex3_sto_wd[2]))); + assign ex3_sto_data_rot0_b[17] = (~(ex3_sto_data[17] & (~ex3_sto_wd[2]))); + assign ex3_sto_data_rot0_b[18] = (~(ex3_sto_data[18] & (~ex3_sto_wd[2]))); + assign ex3_sto_data_rot0_b[19] = (~(ex3_sto_data[19] & (~ex3_sto_wd[2]))); + assign ex3_sto_data_rot0_b[20] = (~(ex3_sto_data[20] & (~ex3_sto_wd[2]))); + assign ex3_sto_data_rot0_b[21] = (~(ex3_sto_data[21] & (~ex3_sto_wd[2]))); + assign ex3_sto_data_rot0_b[22] = (~(ex3_sto_data[22] & (~ex3_sto_wd[2]))); + assign ex3_sto_data_rot0_b[23] = (~(ex3_sto_data[23] & (~ex3_sto_wd[2]))); + assign ex3_sto_data_rot0_b[24] = (~(ex3_sto_data[24] & (~ex3_sto_wd[3]))); + assign ex3_sto_data_rot0_b[25] = (~(ex3_sto_data[25] & (~ex3_sto_wd[3]))); + assign ex3_sto_data_rot0_b[26] = (~(ex3_sto_data[26] & (~ex3_sto_wd[3]))); + assign ex3_sto_data_rot0_b[27] = (~(ex3_sto_data[27] & (~ex3_sto_wd[3]))); + assign ex3_sto_data_rot0_b[28] = (~(ex3_sto_data[28] & (~ex3_sto_wd[3]))); + assign ex3_sto_data_rot0_b[29] = (~(ex3_sto_data[29] & (~ex3_sto_wd[3]))); + assign ex3_sto_data_rot0_b[30] = (~(ex3_sto_data[30] & (~ex3_sto_wd[3]))); + assign ex3_sto_data_rot0_b[31] = (~(ex3_sto_data[31] & (~ex3_sto_wd[3]))); + assign ex3_sto_data_rot0_b[32] = (~(ex3_sto_data[0] & ex3_sto_sp[0])); + assign ex3_sto_data_rot0_b[33] = (~(ex3_sto_data[1] & ex3_sto_sp[0])); + assign ex3_sto_data_rot0_b[34] = (~(ex3_sto_data[2] & ex3_sto_sp[0])); + assign ex3_sto_data_rot0_b[35] = (~(ex3_sto_data[3] & ex3_sto_sp[0])); + assign ex3_sto_data_rot0_b[36] = (~(ex3_sto_data[4] & ex3_sto_sp[0])); + assign ex3_sto_data_rot0_b[37] = (~(ex3_sto_data[5] & ex3_sto_sp[0])); + assign ex3_sto_data_rot0_b[38] = (~(ex3_sto_data[6] & ex3_sto_sp[0])); + assign ex3_sto_data_rot0_b[39] = (~(ex3_sto_data[7] & ex3_sto_sp[0])); + assign ex3_sto_data_rot0_b[40] = (~(ex3_sto_data[8] & ex3_sto_sp[1])); + assign ex3_sto_data_rot0_b[41] = (~(ex3_sto_data[9] & ex3_sto_sp[1])); + assign ex3_sto_data_rot0_b[42] = (~(ex3_sto_data[10] & ex3_sto_sp[1])); + assign ex3_sto_data_rot0_b[43] = (~(ex3_sto_data[11] & ex3_sto_sp[1])); + assign ex3_sto_data_rot0_b[44] = (~(ex3_sto_data[12] & ex3_sto_sp[1])); + assign ex3_sto_data_rot0_b[45] = (~(ex3_sto_data[13] & ex3_sto_sp[1])); + assign ex3_sto_data_rot0_b[46] = (~(ex3_sto_data[14] & ex3_sto_sp[1])); + assign ex3_sto_data_rot0_b[47] = (~(ex3_sto_data[15] & ex3_sto_sp[1])); + assign ex3_sto_data_rot0_b[48] = (~(ex3_sto_data[16] & ex3_sto_sp[2])); + assign ex3_sto_data_rot0_b[49] = (~(ex3_sto_data[17] & ex3_sto_sp[2])); + assign ex3_sto_data_rot0_b[50] = (~(ex3_sto_data[18] & ex3_sto_sp[2])); + assign ex3_sto_data_rot0_b[51] = (~(ex3_sto_data[19] & ex3_sto_sp[2])); + assign ex3_sto_data_rot0_b[52] = (~(ex3_sto_data[20] & ex3_sto_sp[2])); + assign ex3_sto_data_rot0_b[53] = (~(ex3_sto_data[21] & ex3_sto_sp[2])); + assign ex3_sto_data_rot0_b[54] = (~(ex3_sto_data[22] & ex3_sto_sp[2])); + assign ex3_sto_data_rot0_b[55] = (~(ex3_sto_data[23] & ex3_sto_sp[2])); + assign ex3_sto_data_rot0_b[56] = (~(ex3_sto_data[24] & ex3_sto_sp[3])); + assign ex3_sto_data_rot0_b[57] = (~(ex3_sto_data[25] & ex3_sto_sp[3])); + assign ex3_sto_data_rot0_b[58] = (~(ex3_sto_data[26] & ex3_sto_sp[3])); + assign ex3_sto_data_rot0_b[59] = (~(ex3_sto_data[27] & ex3_sto_sp[3])); + assign ex3_sto_data_rot0_b[60] = (~(ex3_sto_data[28] & ex3_sto_sp[3])); + assign ex3_sto_data_rot0_b[61] = (~(ex3_sto_data[29] & ex3_sto_sp[3])); + assign ex3_sto_data_rot0_b[62] = (~(ex3_sto_data[30] & ex3_sto_sp[3])); + assign ex3_sto_data_rot0_b[63] = (~(ex3_sto_data[31] & ex3_sto_sp[3])); + + assign ex3_sto_data_rot1_b[0] = (~(ex3_sto_data[32] & ex3_sto_wd[0])); + assign ex3_sto_data_rot1_b[1] = (~(ex3_sto_data[33] & ex3_sto_wd[0])); + assign ex3_sto_data_rot1_b[2] = (~(ex3_sto_data[34] & ex3_sto_wd[0])); + assign ex3_sto_data_rot1_b[3] = (~(ex3_sto_data[35] & ex3_sto_wd[0])); + assign ex3_sto_data_rot1_b[4] = (~(ex3_sto_data[36] & ex3_sto_wd[0])); + assign ex3_sto_data_rot1_b[5] = (~(ex3_sto_data[37] & ex3_sto_wd[0])); + assign ex3_sto_data_rot1_b[6] = (~(ex3_sto_data[38] & ex3_sto_wd[0])); + assign ex3_sto_data_rot1_b[7] = (~(ex3_sto_data[39] & ex3_sto_wd[0])); + assign ex3_sto_data_rot1_b[8] = (~(ex3_sto_data[40] & ex3_sto_wd[1])); + assign ex3_sto_data_rot1_b[9] = (~(ex3_sto_data[41] & ex3_sto_wd[1])); + assign ex3_sto_data_rot1_b[10] = (~(ex3_sto_data[42] & ex3_sto_wd[1])); + assign ex3_sto_data_rot1_b[11] = (~(ex3_sto_data[43] & ex3_sto_wd[1])); + assign ex3_sto_data_rot1_b[12] = (~(ex3_sto_data[44] & ex3_sto_wd[1])); + assign ex3_sto_data_rot1_b[13] = (~(ex3_sto_data[45] & ex3_sto_wd[1])); + assign ex3_sto_data_rot1_b[14] = (~(ex3_sto_data[46] & ex3_sto_wd[1])); + assign ex3_sto_data_rot1_b[15] = (~(ex3_sto_data[47] & ex3_sto_wd[1])); + assign ex3_sto_data_rot1_b[16] = (~(ex3_sto_data[48] & ex3_sto_wd[2])); + assign ex3_sto_data_rot1_b[17] = (~(ex3_sto_data[49] & ex3_sto_wd[2])); + assign ex3_sto_data_rot1_b[18] = (~(ex3_sto_data[50] & ex3_sto_wd[2])); + assign ex3_sto_data_rot1_b[19] = (~(ex3_sto_data[51] & ex3_sto_wd[2])); + assign ex3_sto_data_rot1_b[20] = (~(ex3_sto_data[52] & ex3_sto_wd[2])); + assign ex3_sto_data_rot1_b[21] = (~(ex3_sto_data[53] & ex3_sto_wd[2])); + assign ex3_sto_data_rot1_b[22] = (~(ex3_sto_data[54] & ex3_sto_wd[2])); + assign ex3_sto_data_rot1_b[23] = (~(ex3_sto_data[55] & ex3_sto_wd[2])); + assign ex3_sto_data_rot1_b[24] = (~(ex3_sto_data[56] & ex3_sto_wd[3])); + assign ex3_sto_data_rot1_b[25] = (~(ex3_sto_data[57] & ex3_sto_wd[3])); + assign ex3_sto_data_rot1_b[26] = (~(ex3_sto_data[58] & ex3_sto_wd[3])); + assign ex3_sto_data_rot1_b[27] = (~(ex3_sto_data[59] & ex3_sto_wd[3])); + assign ex3_sto_data_rot1_b[28] = (~(ex3_sto_data[60] & ex3_sto_wd[3])); + assign ex3_sto_data_rot1_b[29] = (~(ex3_sto_data[61] & ex3_sto_wd[3])); + assign ex3_sto_data_rot1_b[30] = (~(ex3_sto_data[62] & ex3_sto_wd[3])); + assign ex3_sto_data_rot1_b[31] = (~(ex3_sto_data[63] & ex3_sto_wd[3])); + assign ex3_sto_data_rot1_b[32] = (~(ex3_sto_data[32] & (~ex3_sto_sp[0]))); + assign ex3_sto_data_rot1_b[33] = (~(ex3_sto_data[33] & (~ex3_sto_sp[0]))); + assign ex3_sto_data_rot1_b[34] = (~(ex3_sto_data[34] & (~ex3_sto_sp[0]))); + assign ex3_sto_data_rot1_b[35] = (~(ex3_sto_data[35] & (~ex3_sto_sp[0]))); + assign ex3_sto_data_rot1_b[36] = (~(ex3_sto_data[36] & (~ex3_sto_sp[0]))); + assign ex3_sto_data_rot1_b[37] = (~(ex3_sto_data[37] & (~ex3_sto_sp[0]))); + assign ex3_sto_data_rot1_b[38] = (~(ex3_sto_data[38] & (~ex3_sto_sp[0]))); + assign ex3_sto_data_rot1_b[39] = (~(ex3_sto_data[39] & (~ex3_sto_sp[0]))); + assign ex3_sto_data_rot1_b[40] = (~(ex3_sto_data[40] & (~ex3_sto_sp[1]))); + assign ex3_sto_data_rot1_b[41] = (~(ex3_sto_data[41] & (~ex3_sto_sp[1]))); + assign ex3_sto_data_rot1_b[42] = (~(ex3_sto_data[42] & (~ex3_sto_sp[1]))); + assign ex3_sto_data_rot1_b[43] = (~(ex3_sto_data[43] & (~ex3_sto_sp[1]))); + assign ex3_sto_data_rot1_b[44] = (~(ex3_sto_data[44] & (~ex3_sto_sp[1]))); + assign ex3_sto_data_rot1_b[45] = (~(ex3_sto_data[45] & (~ex3_sto_sp[1]))); + assign ex3_sto_data_rot1_b[46] = (~(ex3_sto_data[46] & (~ex3_sto_sp[1]))); + assign ex3_sto_data_rot1_b[47] = (~(ex3_sto_data[47] & (~ex3_sto_sp[1]))); + assign ex3_sto_data_rot1_b[48] = (~(ex3_sto_data[48] & (~ex3_sto_sp[2]))); + assign ex3_sto_data_rot1_b[49] = (~(ex3_sto_data[49] & (~ex3_sto_sp[2]))); + assign ex3_sto_data_rot1_b[50] = (~(ex3_sto_data[50] & (~ex3_sto_sp[2]))); + assign ex3_sto_data_rot1_b[51] = (~(ex3_sto_data[51] & (~ex3_sto_sp[2]))); + assign ex3_sto_data_rot1_b[52] = (~(ex3_sto_data[52] & (~ex3_sto_sp[2]))); + assign ex3_sto_data_rot1_b[53] = (~(ex3_sto_data[53] & (~ex3_sto_sp[2]))); + assign ex3_sto_data_rot1_b[54] = (~(ex3_sto_data[54] & (~ex3_sto_sp[2]))); + assign ex3_sto_data_rot1_b[55] = (~(ex3_sto_data[55] & (~ex3_sto_sp[2]))); + assign ex3_sto_data_rot1_b[56] = (~(ex3_sto_data[56] & (~ex3_sto_sp[3]))); + assign ex3_sto_data_rot1_b[57] = (~(ex3_sto_data[57] & (~ex3_sto_sp[3]))); + assign ex3_sto_data_rot1_b[58] = (~(ex3_sto_data[58] & (~ex3_sto_sp[3]))); + assign ex3_sto_data_rot1_b[59] = (~(ex3_sto_data[59] & (~ex3_sto_sp[3]))); + assign ex3_sto_data_rot1_b[60] = (~(ex3_sto_data[60] & (~ex3_sto_sp[3]))); + assign ex3_sto_data_rot1_b[61] = (~(ex3_sto_data[61] & (~ex3_sto_sp[3]))); + assign ex3_sto_data_rot1_b[62] = (~(ex3_sto_data[62] & (~ex3_sto_sp[3]))); + assign ex3_sto_data_rot1_b[63] = (~(ex3_sto_data[63] & (~ex3_sto_sp[3]))); + + assign f_sto_ex3_sto_data[0:63] = (~(ex3_sto_data_rot0_b[0:63] & ex3_sto_data_rot1_b[0:63])); + + ////############################################ + ////# scan + ////############################################ + + assign ex2_sins_si[0:2] = {ex2_sins_so[1:2], f_sto_si}; + assign ex2_sop_si[0:64] = {ex2_sop_so[1:64], ex2_sins_so[0]}; + assign ex3_sto_si[0:72] = {ex3_sto_so[1:72], ex2_sop_so[0]}; + assign act_si[0:3] = {act_so[1:3], ex3_sto_so[0]}; + assign f_sto_so = act_so[0]; + +endmodule diff --git a/dev/verilog/work/fu_tblexp.v b/dev/verilog/work/fu_tblexp.v new file mode 100755 index 0000000..62c7832 --- /dev/null +++ b/dev/verilog/work/fu_tblexp.v @@ -0,0 +1,694 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +module fu_tblexp( + vdd, + gnd, + clkoff_b, + act_dis, + flush, + delay_lclkr, + mpw1_b, + mpw2_b, + sg_1, + thold_1, + fpu_enable, + nclk, + si, + so, + ex2_act_b, + f_pic_ex3_ue1, + f_pic_ex3_sp_b, + f_pic_ex3_est_recip, + f_pic_ex3_est_rsqrt, + f_eie_ex3_tbl_expo, + f_fmt_ex3_lu_den_recip, + f_fmt_ex3_lu_den_rsqrto, + f_tbe_ex4_recip_ue1, + f_tbe_ex4_lu_sh, + f_tbe_ex4_match_en_sp, + f_tbe_ex4_match_en_dp, + f_tbe_ex4_recip_2046, + f_tbe_ex4_recip_2045, + f_tbe_ex4_recip_2044, + f_tbe_ex4_may_ov, + f_tbe_ex4_res_expo +); + `include "tri_a2o.vh" + + inout vdd; + inout gnd; + input clkoff_b; // tiup + input act_dis; // ??tidn?? + input flush; // ??tidn?? + input [2:3] delay_lclkr; // tidn, + input [2:3] mpw1_b; // tidn, + input [0:0] mpw2_b; // tidn, + input sg_1; + input thold_1; + input fpu_enable; //dc_act + input [0:`NCLK_WIDTH-1] nclk; + + input si; // perv + output so; // perv + input ex2_act_b; // act + + input f_pic_ex3_ue1; + input f_pic_ex3_sp_b; + input f_pic_ex3_est_recip; + input f_pic_ex3_est_rsqrt; + input [1:13] f_eie_ex3_tbl_expo; + input f_fmt_ex3_lu_den_recip; + input f_fmt_ex3_lu_den_rsqrto; + + output f_tbe_ex4_recip_ue1; + output f_tbe_ex4_lu_sh; + output f_tbe_ex4_match_en_sp; + output f_tbe_ex4_match_en_dp; + output f_tbe_ex4_recip_2046; + output f_tbe_ex4_recip_2045; + output f_tbe_ex4_recip_2044; + output f_tbe_ex4_may_ov; + output [1:13] f_tbe_ex4_res_expo; // to rounder + + // end ports + + // ENTITY + + + parameter tiup = 1'b1; + parameter tidn = 1'b0; + + wire thold_0_b; + wire thold_0; + wire force_t; + wire sg_0; + wire [0:3] act_spare_unused; + wire ex3_act; + wire [0:4] act_so; + wire [0:4] act_si; + wire [0:19] ex4_expo_so; + wire [0:19] ex4_expo_si; + wire [1:13] ex3_res_expo; + wire [1:13] ex4_res_expo; + wire ex4_recip_2044; + wire ex3_recip_2044; + wire ex3_recip_ue1; + wire ex4_recip_2045; + wire ex3_recip_2045; + wire ex4_recip_ue1; + wire ex4_recip_2046; + wire ex3_recip_2046; + wire ex4_force_expo_den; + + wire [1:13] ex3_b_expo_adj_b; + wire [1:13] ex3_b_expo_adj; + wire [1:13] ex3_recip_k; + wire [1:13] ex3_recip_p; + wire [2:13] ex3_recip_g; + wire [2:12] ex3_recip_t; + wire [2:13] ex3_recip_c; + wire [1:13] ex3_recip_expo; + wire [1:13] ex3_rsqrt_k; + wire [1:13] ex3_rsqrt_p; + wire [2:13] ex3_rsqrt_g; + wire [2:12] ex3_rsqrt_t; + wire [2:13] ex3_rsqrt_c; + wire [1:13] ex3_rsqrt_expo; + wire [1:13] ex3_rsqrt_bsh_b; + + wire [2:13] ex3_recip_g2; + wire [2:11] ex3_recip_t2; + wire [2:13] ex3_recip_g4; + wire [2:9] ex3_recip_t4; + wire [2:13] ex3_recip_g8; + wire [2:5] ex3_recip_t8; + + wire [2:13] ex3_rsqrt_g2; + wire [2:11] ex3_rsqrt_t2; + wire [2:13] ex3_rsqrt_g4; + wire [2:9] ex3_rsqrt_t4; + wire [2:13] ex3_rsqrt_g8; + wire [2:5] ex3_rsqrt_t8; + wire ex2_act; + + wire ex3_lu_sh; + wire ex4_lu_sh; + wire [2:13] ex4_res_expo_c; + wire [2:13] ex4_res_expo_g8_b; + wire [2:13] ex4_res_expo_g4; + wire [2:13] ex4_res_expo_g2_b; + wire [1:13] ex4_res_decr; + wire [1:13] ex4_res_expo_b; + wire ex4_decr_expo; + + wire ex3_mid_match_ifsp; + wire ex3_mid_match_ifdp; + wire ex3_match_en_dp; + wire ex3_match_en_sp; + wire ex4_match_en_dp; + wire ex4_match_en_sp; + wire ex3_com_match; + wire ex4_recip_2044_dp; + wire ex4_recip_2045_dp; + wire ex4_recip_2046_dp; + + ////############################################ + ////# pervasive + ////############################################ + + + tri_plat thold_reg_0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(flush), + .din(thold_1), + .q(thold_0) + ); + + + tri_plat sg_reg_0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(flush), + .din(sg_1), + .q(sg_0) + ); + + + tri_lcbor lcbor_0( + .clkoff_b(clkoff_b), + .thold(thold_0), + .sg(sg_0), + .act_dis(act_dis), + .force_t(force_t), + .thold_b(thold_0_b) + ); + + ////############################################ + ////# ACT LATCHES + ////############################################ + + assign ex2_act = (~ex2_act_b); + + + tri_rlmreg_p #(.WIDTH(5)) act_lat( + .force_t(force_t), //tidn, + .d_mode(tiup), // => d_mode ,--tiup, + .delay_lclkr(delay_lclkr[2]), //tidn, + .mpw1_b(mpw1_b[2]), //tidn, + .mpw2_b(mpw2_b[0]), //tidn, + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + .act(fpu_enable), + .scout(act_so), + .scin(act_si), + //----------------- + .din({ act_spare_unused[0], + act_spare_unused[1], + ex2_act, + act_spare_unused[2], + act_spare_unused[3]}), + //----------------- + .dout({ act_spare_unused[0], + act_spare_unused[1], + ex3_act, + act_spare_unused[2], + act_spare_unused[3]}) + ); + + ////############################################## + ////# EX3 logic + ////############################################## + // 1* 2 3 4 5* 6 7 8 9* 10 11 12 13* + // * * * * + // 0 B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 sqrt_q0 + // 0 0 1 1 1 1 1 1 1 1 1 1 0 + // * * * * + // !B01 !B02 !B03 !B04 !B05 !B06 !B07 !B08 !B09 !B10 !B11 !B12 !B13 fres + // 0 0 1 1 1 1 1 1 1 1 1 1 0 + // * * * * + // 1 !B01 !B02 !B03 !B04 !B05 !B06 !B07 !B08 !B09 !B10 !B11 !B12 rsqrte + // 0 0 1 0 1 1 1 1 1 1 1 1 !B13 + // * * * * + //----------------------------------------------------------------------------- + // 1 !B01 !B02 !B03 !B04 !B05 !B06 !B07 !B08 !B09 !B10 !B11 !B12 rsqrte + // 0 0 1 0 1 1 1 1 1 1 1 1 (!c5 +!B13 +<1>) + // 1 1 1 1 1 1 1 1 !c0 !c1 !c2 !c3 !c4 + // + + // !c5 + !b13 + <1> | or xnor | or+xnor => put into LSB position + //------------------+-----------+-------- + // 0 0 | 0 1 | 1+0 + // 0 1 | 1 0 | 1+0 + // 1 0 | 1 0 | 1+0 + // 1 1 | 1 1 | 1+1 + + ////#-------------------------------------------- + ////# first generate B - clz (upper half should be carry select) + ////#---------------------------------------------- + ////# upper half should be carry select decrementer + + assign ex3_b_expo_adj[1:13] = f_eie_ex3_tbl_expo[1:13]; + assign ex3_b_expo_adj_b[1:13] = (~ex3_b_expo_adj[1:13]); + + ////#-------------------------------------------- + ////# adder for !(B-clz) + K_res + ////#-------------------------------------------- + // 1 2 3 4 5 6 7 8 9 10 11 12 13 + // !B01 !B02 !B03 !B04 !B05 !B06 !B07 !B08 !B09 !B10 !B11 !B12 !B13 fres + // 0 0 1 1 1 1 1 1 1 1 1 1 0 + + assign ex3_recip_k[1:13] = {{2{tidn}}, {10{tiup}}, tidn}; + + assign ex3_recip_p[1:13] = ex3_recip_k[1:13] ^ ex3_b_expo_adj_b[1:13]; + assign ex3_recip_g[2:13] = ex3_recip_k[2:13] & ex3_b_expo_adj_b[2:13]; + assign ex3_recip_t[2:12] = ex3_recip_k[2:12] | ex3_b_expo_adj_b[2:12]; + + assign ex3_recip_g2[13] = ex3_recip_g[13]; + assign ex3_recip_g2[12] = ex3_recip_g[12] | (ex3_recip_t[12] & ex3_recip_g[13]); + assign ex3_recip_g2[11] = ex3_recip_g[11] | (ex3_recip_t[11] & ex3_recip_g[12]); + assign ex3_recip_g2[10] = ex3_recip_g[10] | (ex3_recip_t[10] & ex3_recip_g[11]); + assign ex3_recip_g2[9] = ex3_recip_g[9] | (ex3_recip_t[9] & ex3_recip_g[10]); + assign ex3_recip_g2[8] = ex3_recip_g[8] | (ex3_recip_t[8] & ex3_recip_g[9]); + assign ex3_recip_g2[7] = ex3_recip_g[7] | (ex3_recip_t[7] & ex3_recip_g[8]); + assign ex3_recip_g2[6] = ex3_recip_g[6] | (ex3_recip_t[6] & ex3_recip_g[7]); + assign ex3_recip_g2[5] = ex3_recip_g[5] | (ex3_recip_t[5] & ex3_recip_g[6]); + assign ex3_recip_g2[4] = ex3_recip_g[4] | (ex3_recip_t[4] & ex3_recip_g[5]); + assign ex3_recip_g2[3] = ex3_recip_g[3] | (ex3_recip_t[3] & ex3_recip_g[4]); + assign ex3_recip_g2[2] = ex3_recip_g[2] | (ex3_recip_t[2] & ex3_recip_g[3]); + + assign ex3_recip_t2[11] = (ex3_recip_t[11] & ex3_recip_t[12]); + assign ex3_recip_t2[10] = (ex3_recip_t[10] & ex3_recip_t[11]); + assign ex3_recip_t2[9] = (ex3_recip_t[9] & ex3_recip_t[10]); + assign ex3_recip_t2[8] = (ex3_recip_t[8] & ex3_recip_t[9]); + assign ex3_recip_t2[7] = (ex3_recip_t[7] & ex3_recip_t[8]); + assign ex3_recip_t2[6] = (ex3_recip_t[6] & ex3_recip_t[7]); + assign ex3_recip_t2[5] = (ex3_recip_t[5] & ex3_recip_t[6]); + assign ex3_recip_t2[4] = (ex3_recip_t[4] & ex3_recip_t[5]); + assign ex3_recip_t2[3] = (ex3_recip_t[3] & ex3_recip_t[4]); + assign ex3_recip_t2[2] = (ex3_recip_t[2] & ex3_recip_t[3]); + + assign ex3_recip_g4[13] = ex3_recip_g2[13]; + assign ex3_recip_g4[12] = ex3_recip_g2[12]; + assign ex3_recip_g4[11] = ex3_recip_g2[11] | (ex3_recip_t2[11] & ex3_recip_g2[13]); + assign ex3_recip_g4[10] = ex3_recip_g2[10] | (ex3_recip_t2[10] & ex3_recip_g2[12]); + assign ex3_recip_g4[9] = ex3_recip_g2[9] | (ex3_recip_t2[9] & ex3_recip_g2[11]); + assign ex3_recip_g4[8] = ex3_recip_g2[8] | (ex3_recip_t2[8] & ex3_recip_g2[10]); + assign ex3_recip_g4[7] = ex3_recip_g2[7] | (ex3_recip_t2[7] & ex3_recip_g2[9]); + assign ex3_recip_g4[6] = ex3_recip_g2[6] | (ex3_recip_t2[6] & ex3_recip_g2[8]); + assign ex3_recip_g4[5] = ex3_recip_g2[5] | (ex3_recip_t2[5] & ex3_recip_g2[7]); + assign ex3_recip_g4[4] = ex3_recip_g2[4] | (ex3_recip_t2[4] & ex3_recip_g2[6]); + assign ex3_recip_g4[3] = ex3_recip_g2[3] | (ex3_recip_t2[3] & ex3_recip_g2[5]); + assign ex3_recip_g4[2] = ex3_recip_g2[2] | (ex3_recip_t2[2] & ex3_recip_g2[4]); + + assign ex3_recip_t4[9] = (ex3_recip_t2[9] & ex3_recip_t2[11]); + assign ex3_recip_t4[8] = (ex3_recip_t2[8] & ex3_recip_t2[10]); + assign ex3_recip_t4[7] = (ex3_recip_t2[7] & ex3_recip_t2[9]); + assign ex3_recip_t4[6] = (ex3_recip_t2[6] & ex3_recip_t2[8]); + assign ex3_recip_t4[5] = (ex3_recip_t2[5] & ex3_recip_t2[7]); + assign ex3_recip_t4[4] = (ex3_recip_t2[4] & ex3_recip_t2[6]); + assign ex3_recip_t4[3] = (ex3_recip_t2[3] & ex3_recip_t2[5]); + assign ex3_recip_t4[2] = (ex3_recip_t2[2] & ex3_recip_t2[4]); + + assign ex3_recip_g8[13] = ex3_recip_g4[13]; + assign ex3_recip_g8[12] = ex3_recip_g4[12]; + assign ex3_recip_g8[11] = ex3_recip_g4[11]; + assign ex3_recip_g8[10] = ex3_recip_g4[10]; + assign ex3_recip_g8[9] = ex3_recip_g4[9] | (ex3_recip_t4[9] & ex3_recip_g4[13]); + assign ex3_recip_g8[8] = ex3_recip_g4[8] | (ex3_recip_t4[8] & ex3_recip_g4[12]); + assign ex3_recip_g8[7] = ex3_recip_g4[7] | (ex3_recip_t4[7] & ex3_recip_g4[11]); + assign ex3_recip_g8[6] = ex3_recip_g4[6] | (ex3_recip_t4[6] & ex3_recip_g4[10]); + assign ex3_recip_g8[5] = ex3_recip_g4[5] | (ex3_recip_t4[5] & ex3_recip_g4[9]); + assign ex3_recip_g8[4] = ex3_recip_g4[4] | (ex3_recip_t4[4] & ex3_recip_g4[8]); + assign ex3_recip_g8[3] = ex3_recip_g4[3] | (ex3_recip_t4[3] & ex3_recip_g4[7]); + assign ex3_recip_g8[2] = ex3_recip_g4[2] | (ex3_recip_t4[2] & ex3_recip_g4[6]); + + assign ex3_recip_t8[5] = (ex3_recip_t4[5] & ex3_recip_t4[9]); + assign ex3_recip_t8[4] = (ex3_recip_t4[4] & ex3_recip_t4[8]); + assign ex3_recip_t8[3] = (ex3_recip_t4[3] & ex3_recip_t4[7]); + assign ex3_recip_t8[2] = (ex3_recip_t4[2] & ex3_recip_t4[6]); + + assign ex3_recip_c[13] = ex3_recip_g8[13]; + assign ex3_recip_c[12] = ex3_recip_g8[12]; + assign ex3_recip_c[11] = ex3_recip_g8[11]; + assign ex3_recip_c[10] = ex3_recip_g8[10]; + assign ex3_recip_c[9] = ex3_recip_g8[9]; + assign ex3_recip_c[8] = ex3_recip_g8[8]; + assign ex3_recip_c[7] = ex3_recip_g8[7]; + assign ex3_recip_c[6] = ex3_recip_g8[6]; + assign ex3_recip_c[5] = ex3_recip_g8[5] | (ex3_recip_t8[5] & ex3_recip_g8[13]); + assign ex3_recip_c[4] = ex3_recip_g8[4] | (ex3_recip_t8[4] & ex3_recip_g8[12]); + assign ex3_recip_c[3] = ex3_recip_g8[3] | (ex3_recip_t8[3] & ex3_recip_g8[11]); + assign ex3_recip_c[2] = ex3_recip_g8[2] | (ex3_recip_t8[2] & ex3_recip_g8[10]); + + assign ex3_recip_expo[1:12] = ex3_recip_p[1:12] ^ ex3_recip_c[2:13]; + assign ex3_recip_expo[13] = ex3_recip_p[13]; + + ////#-------------------------------------------- + ////# adder for !(B-clz) + K_rsqrt + ////#-------------------------------------------- + // 1 2 3 4 5 6 7 8 9 10 11 12 13 + // 1 !B01 !B02 !B03 !B04 !B05 !B06 !B07 !B08 !B09 !B10 !B11 !B12 rsqrte + // 0 0 1 0 1 1 1 1 1 1 1 1 !B13 + + assign ex3_rsqrt_k[1:13] = {tidn, tidn, tiup, tidn, {8{tiup}}, ex3_b_expo_adj_b[13]}; + assign ex3_rsqrt_bsh_b[1:13] = {ex3_b_expo_adj_b[1], ex3_b_expo_adj_b[1:12]}; //negative expo in -> positive + + assign ex3_rsqrt_p[1:13] = ex3_rsqrt_k[1:13] ^ ex3_rsqrt_bsh_b[1:13]; + assign ex3_rsqrt_g[2:13] = ex3_rsqrt_k[2:13] & ex3_rsqrt_bsh_b[2:13]; + assign ex3_rsqrt_t[2:12] = ex3_rsqrt_k[2:12] | ex3_rsqrt_bsh_b[2:12]; + + assign ex3_rsqrt_g2[13] = ex3_rsqrt_g[13]; + assign ex3_rsqrt_g2[12] = ex3_rsqrt_g[12] | (ex3_rsqrt_t[12] & ex3_rsqrt_g[13]); + assign ex3_rsqrt_g2[11] = ex3_rsqrt_g[11] | (ex3_rsqrt_t[11] & ex3_rsqrt_g[12]); + assign ex3_rsqrt_g2[10] = ex3_rsqrt_g[10] | (ex3_rsqrt_t[10] & ex3_rsqrt_g[11]); + assign ex3_rsqrt_g2[9] = ex3_rsqrt_g[9] | (ex3_rsqrt_t[9] & ex3_rsqrt_g[10]); + assign ex3_rsqrt_g2[8] = ex3_rsqrt_g[8] | (ex3_rsqrt_t[8] & ex3_rsqrt_g[9]); + assign ex3_rsqrt_g2[7] = ex3_rsqrt_g[7] | (ex3_rsqrt_t[7] & ex3_rsqrt_g[8]); + assign ex3_rsqrt_g2[6] = ex3_rsqrt_g[6] | (ex3_rsqrt_t[6] & ex3_rsqrt_g[7]); + assign ex3_rsqrt_g2[5] = ex3_rsqrt_g[5] | (ex3_rsqrt_t[5] & ex3_rsqrt_g[6]); + assign ex3_rsqrt_g2[4] = ex3_rsqrt_g[4] | (ex3_rsqrt_t[4] & ex3_rsqrt_g[5]); + assign ex3_rsqrt_g2[3] = ex3_rsqrt_g[3] | (ex3_rsqrt_t[3] & ex3_rsqrt_g[4]); + assign ex3_rsqrt_g2[2] = ex3_rsqrt_g[2] | (ex3_rsqrt_t[2] & ex3_rsqrt_g[3]); + + assign ex3_rsqrt_t2[11] = (ex3_rsqrt_t[11] & ex3_rsqrt_t[12]); + assign ex3_rsqrt_t2[10] = (ex3_rsqrt_t[10] & ex3_rsqrt_t[11]); + assign ex3_rsqrt_t2[9] = (ex3_rsqrt_t[9] & ex3_rsqrt_t[10]); + assign ex3_rsqrt_t2[8] = (ex3_rsqrt_t[8] & ex3_rsqrt_t[9]); + assign ex3_rsqrt_t2[7] = (ex3_rsqrt_t[7] & ex3_rsqrt_t[8]); + assign ex3_rsqrt_t2[6] = (ex3_rsqrt_t[6] & ex3_rsqrt_t[7]); + assign ex3_rsqrt_t2[5] = (ex3_rsqrt_t[5] & ex3_rsqrt_t[6]); + assign ex3_rsqrt_t2[4] = (ex3_rsqrt_t[4] & ex3_rsqrt_t[5]); + assign ex3_rsqrt_t2[3] = (ex3_rsqrt_t[3] & ex3_rsqrt_t[4]); + assign ex3_rsqrt_t2[2] = (ex3_rsqrt_t[2] & ex3_rsqrt_t[3]); + + assign ex3_rsqrt_g4[13] = ex3_rsqrt_g2[13]; + assign ex3_rsqrt_g4[12] = ex3_rsqrt_g2[12]; + assign ex3_rsqrt_g4[11] = ex3_rsqrt_g2[11] | (ex3_rsqrt_t2[11] & ex3_rsqrt_g2[13]); + assign ex3_rsqrt_g4[10] = ex3_rsqrt_g2[10] | (ex3_rsqrt_t2[10] & ex3_rsqrt_g2[12]); + assign ex3_rsqrt_g4[9] = ex3_rsqrt_g2[9] | (ex3_rsqrt_t2[9] & ex3_rsqrt_g2[11]); + assign ex3_rsqrt_g4[8] = ex3_rsqrt_g2[8] | (ex3_rsqrt_t2[8] & ex3_rsqrt_g2[10]); + assign ex3_rsqrt_g4[7] = ex3_rsqrt_g2[7] | (ex3_rsqrt_t2[7] & ex3_rsqrt_g2[9]); + assign ex3_rsqrt_g4[6] = ex3_rsqrt_g2[6] | (ex3_rsqrt_t2[6] & ex3_rsqrt_g2[8]); + assign ex3_rsqrt_g4[5] = ex3_rsqrt_g2[5] | (ex3_rsqrt_t2[5] & ex3_rsqrt_g2[7]); + assign ex3_rsqrt_g4[4] = ex3_rsqrt_g2[4] | (ex3_rsqrt_t2[4] & ex3_rsqrt_g2[6]); + assign ex3_rsqrt_g4[3] = ex3_rsqrt_g2[3] | (ex3_rsqrt_t2[3] & ex3_rsqrt_g2[5]); + assign ex3_rsqrt_g4[2] = ex3_rsqrt_g2[2] | (ex3_rsqrt_t2[2] & ex3_rsqrt_g2[4]); + + assign ex3_rsqrt_t4[9] = (ex3_rsqrt_t2[9] & ex3_rsqrt_t2[11]); + assign ex3_rsqrt_t4[8] = (ex3_rsqrt_t2[8] & ex3_rsqrt_t2[10]); + assign ex3_rsqrt_t4[7] = (ex3_rsqrt_t2[7] & ex3_rsqrt_t2[9]); + assign ex3_rsqrt_t4[6] = (ex3_rsqrt_t2[6] & ex3_rsqrt_t2[8]); + assign ex3_rsqrt_t4[5] = (ex3_rsqrt_t2[5] & ex3_rsqrt_t2[7]); + assign ex3_rsqrt_t4[4] = (ex3_rsqrt_t2[4] & ex3_rsqrt_t2[6]); + assign ex3_rsqrt_t4[3] = (ex3_rsqrt_t2[3] & ex3_rsqrt_t2[5]); + assign ex3_rsqrt_t4[2] = (ex3_rsqrt_t2[2] & ex3_rsqrt_t2[4]); + + assign ex3_rsqrt_g8[13] = ex3_rsqrt_g4[13]; + assign ex3_rsqrt_g8[12] = ex3_rsqrt_g4[12]; + assign ex3_rsqrt_g8[11] = ex3_rsqrt_g4[11]; + assign ex3_rsqrt_g8[10] = ex3_rsqrt_g4[10]; + assign ex3_rsqrt_g8[9] = ex3_rsqrt_g4[9] | (ex3_rsqrt_t4[9] & ex3_rsqrt_g4[13]); + assign ex3_rsqrt_g8[8] = ex3_rsqrt_g4[8] | (ex3_rsqrt_t4[8] & ex3_rsqrt_g4[12]); + assign ex3_rsqrt_g8[7] = ex3_rsqrt_g4[7] | (ex3_rsqrt_t4[7] & ex3_rsqrt_g4[11]); + assign ex3_rsqrt_g8[6] = ex3_rsqrt_g4[6] | (ex3_rsqrt_t4[6] & ex3_rsqrt_g4[10]); + assign ex3_rsqrt_g8[5] = ex3_rsqrt_g4[5] | (ex3_rsqrt_t4[5] & ex3_rsqrt_g4[9]); + assign ex3_rsqrt_g8[4] = ex3_rsqrt_g4[4] | (ex3_rsqrt_t4[4] & ex3_rsqrt_g4[8]); + assign ex3_rsqrt_g8[3] = ex3_rsqrt_g4[3] | (ex3_rsqrt_t4[3] & ex3_rsqrt_g4[7]); + assign ex3_rsqrt_g8[2] = ex3_rsqrt_g4[2] | (ex3_rsqrt_t4[2] & ex3_rsqrt_g4[6]); + + assign ex3_rsqrt_t8[5] = (ex3_rsqrt_t4[5] & ex3_rsqrt_t4[9]); + assign ex3_rsqrt_t8[4] = (ex3_rsqrt_t4[4] & ex3_rsqrt_t4[8]); + assign ex3_rsqrt_t8[3] = (ex3_rsqrt_t4[3] & ex3_rsqrt_t4[7]); + assign ex3_rsqrt_t8[2] = (ex3_rsqrt_t4[2] & ex3_rsqrt_t4[6]); + + assign ex3_rsqrt_c[13] = ex3_rsqrt_g8[13]; + assign ex3_rsqrt_c[12] = ex3_rsqrt_g8[12]; + assign ex3_rsqrt_c[11] = ex3_rsqrt_g8[11]; + assign ex3_rsqrt_c[10] = ex3_rsqrt_g8[10]; + assign ex3_rsqrt_c[9] = ex3_rsqrt_g8[9]; + assign ex3_rsqrt_c[8] = ex3_rsqrt_g8[8]; + assign ex3_rsqrt_c[7] = ex3_rsqrt_g8[7]; + assign ex3_rsqrt_c[6] = ex3_rsqrt_g8[6]; + assign ex3_rsqrt_c[5] = ex3_rsqrt_g8[5] | (ex3_rsqrt_t8[5] & ex3_rsqrt_g8[13]); + assign ex3_rsqrt_c[4] = ex3_rsqrt_g8[4] | (ex3_rsqrt_t8[4] & ex3_rsqrt_g8[12]); + assign ex3_rsqrt_c[3] = ex3_rsqrt_g8[3] | (ex3_rsqrt_t8[3] & ex3_rsqrt_g8[11]); + assign ex3_rsqrt_c[2] = ex3_rsqrt_g8[2] | (ex3_rsqrt_t8[2] & ex3_rsqrt_g8[10]); + + assign ex3_rsqrt_expo[1:12] = ex3_rsqrt_p[1:12] ^ ex3_rsqrt_c[2:13]; + assign ex3_rsqrt_expo[13] = ex3_rsqrt_p[13]; + + ////#-------------------------------------------- + ////# select the result + ////#-------------------------------------------- + + assign ex3_res_expo[1:13] = ({13{f_pic_ex3_est_rsqrt}} & ex3_rsqrt_expo[1:13]) | + ({13{f_pic_ex3_est_recip}} & ex3_recip_expo[1:13]); + + ////#-------------------------------------------- + + ////## -------------------------------------------------- + ////## DETECT: exponents that require denormalization + // + // rsqrte: -( (e - bias)/2 ) + bias = -e/2 + 3/2 bias + // expo = 7ff inf/nan (2047) <=== special case logic gives result + // expo = 7fe (2046) -(2046 - 1023)/2 + 1023 = -1023/2 + 1023 = -512 + 1023 = 611 : norm + // + // + // recip : 2bias -expo = -(e - bias) + bias + // expo = 7ff inf/nan (2047) <=== special case logic gives result + // expo = 7fe (2046) 2bias -expo = 2046 - 2046 = x000 denorm + // expo = 7fd (2045) 2046 - 2045 = x001 denorm ? + // expo = 7fc (2044) 2046 - 2044 = x002 norm (denorm if adjust) + ////## -------------------------------------------------- + // for sp underflow, no need to denormalize, but must set the UX flag + // 2046 -1151 = 895 - 1 = 894 <=== INF/NAN in sp range + // 2046 -1150 = 896 - 1 = 895 x380 + // 2046 -1149 = 897 - 1 = 896 x380 + // 2046 -1148 = 898 - 1 = 897 (denorm if adjust) + // + // 2046 111_1111_11110 + // 2045 111_1111_11101 + // 2044 111_1111_11100 + // + // 1150 100_0111_11110 + // 1149 100_0111_11101 + // 1148 100_0111_11100 + // + + // 0512 + assign ex3_mid_match_ifsp = (~f_eie_ex3_tbl_expo[4]) & (~f_eie_ex3_tbl_expo[5]) & (~f_eie_ex3_tbl_expo[6]); // 0256 + // 0128 + + // 0512 total = 896 + assign ex3_mid_match_ifdp = f_eie_ex3_tbl_expo[4] & f_eie_ex3_tbl_expo[5] & f_eie_ex3_tbl_expo[6]; // 0256 + // 0128 + + // sign + // 2048 + // 1024 + // 0064 + // 0032 + // 0016 + assign ex3_com_match = (~f_eie_ex3_tbl_expo[1]) & (~f_eie_ex3_tbl_expo[2]) & f_eie_ex3_tbl_expo[3] & f_eie_ex3_tbl_expo[7] & f_eie_ex3_tbl_expo[8] & f_eie_ex3_tbl_expo[9] & f_eie_ex3_tbl_expo[10] & f_eie_ex3_tbl_expo[11]; // 0008 + // 0004 + + assign ex3_match_en_dp = ex3_com_match & f_pic_ex3_sp_b & ex3_mid_match_ifdp; + assign ex3_match_en_sp = ex3_com_match & (~f_pic_ex3_sp_b) & ex3_mid_match_ifsp; + + // not f_pic_ex3_ue1 and + assign ex3_recip_2046 = f_pic_ex3_est_recip & f_eie_ex3_tbl_expo[12] & (~f_eie_ex3_tbl_expo[13]); // 0002 + // 0001 + + // not f_pic_ex3_ue1 and + assign ex3_recip_2045 = f_pic_ex3_est_recip & (~f_eie_ex3_tbl_expo[12]) & f_eie_ex3_tbl_expo[13]; // 0002 + // 0001 + + // not f_pic_ex3_ue1 and + assign ex3_recip_2044 = f_pic_ex3_est_recip & (~f_eie_ex3_tbl_expo[12]) & (~f_eie_ex3_tbl_expo[13]); // 0002 + // 0001 + + assign ex3_recip_ue1 = f_pic_ex3_est_recip & f_pic_ex3_ue1; + + ////############################################## + ////# EX4 latches + ////############################################## + + // name says odd(unbiased) but it is really for even biased. + assign ex3_lu_sh = (f_fmt_ex3_lu_den_recip & f_pic_ex3_est_recip) | (f_fmt_ex3_lu_den_rsqrto & f_pic_ex3_est_rsqrt & (~f_eie_ex3_tbl_expo[13])); + + + tri_rlmreg_p #(.WIDTH(20)) ex4_expo_lat( + .force_t(force_t), //tidn, + .d_mode(tiup), //d_mode => d_mode ,--tiup, + .delay_lclkr(delay_lclkr[3]), //tidn, + .mpw1_b(mpw1_b[3]), //tidn, + .mpw2_b(mpw2_b[0]), //tidn, + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .thold_b(thold_0_b), + .sg(sg_0), + .act(ex3_act), + .scout(ex4_expo_so), + .scin(ex4_expo_si), + + .din({ ex3_res_expo[1:13], + ex3_match_en_dp, + ex3_match_en_sp, + ex3_recip_2046, + ex3_recip_2045, + ex3_recip_2044, + ex3_lu_sh, + ex3_recip_ue1}), + //----------------- + .dout({ ex4_res_expo[1:13], //LAT-- + ex4_match_en_dp, //LAT-- + ex4_match_en_sp, //LAT-- + ex4_recip_2046, //LAT-- + ex4_recip_2045, //LAT-- + ex4_recip_2044, //LAT-- + ex4_lu_sh, //LAT-- + ex4_recip_ue1}) //LAT-- + ); + + ////############################################## + ////# EX4 logic + ////############################################## + + assign f_tbe_ex4_match_en_sp = ex4_match_en_sp; //output + assign f_tbe_ex4_match_en_dp = ex4_match_en_dp; //output + assign f_tbe_ex4_recip_2046 = ex4_recip_2046; //output + assign f_tbe_ex4_recip_2045 = ex4_recip_2045; //output + assign f_tbe_ex4_recip_2044 = ex4_recip_2044; //output + assign f_tbe_ex4_lu_sh = ex4_lu_sh; //output-- + assign f_tbe_ex4_recip_ue1 = ex4_recip_ue1; //output-- + + assign ex4_recip_2046_dp = ex4_recip_2046 & ex4_match_en_dp & (~ex4_recip_ue1); // for shifting + assign ex4_recip_2045_dp = ex4_recip_2045 & ex4_match_en_dp & (~ex4_recip_ue1); // for shifting + assign ex4_recip_2044_dp = ex4_recip_2044 & ex4_match_en_dp & (~ex4_recip_ue1); // for shifting + assign ex4_force_expo_den = ex4_recip_2046_dp | ex4_recip_2045_dp; // do not force DEN for ue1 mode + // 2044 conditionally backs into denorm depending on lu_sh ... decrement + + assign ex4_decr_expo = (ex4_lu_sh & ex4_recip_ue1) | (ex4_lu_sh & (~ex4_recip_ue1) & (~ex4_recip_2046_dp) & (~ex4_recip_2045_dp) & (~ex4_recip_2044_dp)); // for denormalization / normalization + + // decrement is like add 11111....11111 (lsb does not change + // t = 1 + // g = d + + assign ex4_res_expo_b[1:13] = (~ex4_res_expo[1:13]); + + assign ex4_res_expo_g2_b[13] = (~(ex4_res_expo[13])); + assign ex4_res_expo_g2_b[12] = (~(ex4_res_expo[12] | ex4_res_expo[13])); + assign ex4_res_expo_g2_b[11] = (~(ex4_res_expo[11] | ex4_res_expo[12])); + assign ex4_res_expo_g2_b[10] = (~(ex4_res_expo[10] | ex4_res_expo[11])); + assign ex4_res_expo_g2_b[9] = (~(ex4_res_expo[9] | ex4_res_expo[10])); + assign ex4_res_expo_g2_b[8] = (~(ex4_res_expo[8] | ex4_res_expo[9])); + assign ex4_res_expo_g2_b[7] = (~(ex4_res_expo[7] | ex4_res_expo[8])); + assign ex4_res_expo_g2_b[6] = (~(ex4_res_expo[6] | ex4_res_expo[7])); + assign ex4_res_expo_g2_b[5] = (~(ex4_res_expo[5] | ex4_res_expo[6])); + assign ex4_res_expo_g2_b[4] = (~(ex4_res_expo[4] | ex4_res_expo[5])); + assign ex4_res_expo_g2_b[3] = (~(ex4_res_expo[3] | ex4_res_expo[4])); + assign ex4_res_expo_g2_b[2] = (~(ex4_res_expo[2] | ex4_res_expo[3])); + + assign ex4_res_expo_g4[13] = (~(ex4_res_expo_g2_b[13])); + assign ex4_res_expo_g4[12] = (~(ex4_res_expo_g2_b[12])); + assign ex4_res_expo_g4[11] = (~(ex4_res_expo_g2_b[11] & ex4_res_expo_g2_b[13])); + assign ex4_res_expo_g4[10] = (~(ex4_res_expo_g2_b[10] & ex4_res_expo_g2_b[12])); + assign ex4_res_expo_g4[9] = (~(ex4_res_expo_g2_b[9] & ex4_res_expo_g2_b[11])); + assign ex4_res_expo_g4[8] = (~(ex4_res_expo_g2_b[8] & ex4_res_expo_g2_b[10])); + assign ex4_res_expo_g4[7] = (~(ex4_res_expo_g2_b[7] & ex4_res_expo_g2_b[9])); + assign ex4_res_expo_g4[6] = (~(ex4_res_expo_g2_b[6] & ex4_res_expo_g2_b[8])); + assign ex4_res_expo_g4[5] = (~(ex4_res_expo_g2_b[5] & ex4_res_expo_g2_b[7])); + assign ex4_res_expo_g4[4] = (~(ex4_res_expo_g2_b[4] & ex4_res_expo_g2_b[6])); + assign ex4_res_expo_g4[3] = (~(ex4_res_expo_g2_b[3] & ex4_res_expo_g2_b[5])); + assign ex4_res_expo_g4[2] = (~(ex4_res_expo_g2_b[2] & ex4_res_expo_g2_b[4])); + + assign ex4_res_expo_g8_b[13] = (~(ex4_res_expo_g4[13])); + assign ex4_res_expo_g8_b[12] = (~(ex4_res_expo_g4[12])); + assign ex4_res_expo_g8_b[11] = (~(ex4_res_expo_g4[11])); + assign ex4_res_expo_g8_b[10] = (~(ex4_res_expo_g4[10])); + assign ex4_res_expo_g8_b[9] = (~(ex4_res_expo_g4[9] | ex4_res_expo_g4[13])); + assign ex4_res_expo_g8_b[8] = (~(ex4_res_expo_g4[8] | ex4_res_expo_g4[12])); + assign ex4_res_expo_g8_b[7] = (~(ex4_res_expo_g4[7] | ex4_res_expo_g4[11])); + assign ex4_res_expo_g8_b[6] = (~(ex4_res_expo_g4[6] | ex4_res_expo_g4[10])); + assign ex4_res_expo_g8_b[5] = (~(ex4_res_expo_g4[5] | ex4_res_expo_g4[9])); + assign ex4_res_expo_g8_b[4] = (~(ex4_res_expo_g4[4] | ex4_res_expo_g4[8])); + assign ex4_res_expo_g8_b[3] = (~(ex4_res_expo_g4[3] | ex4_res_expo_g4[7])); + assign ex4_res_expo_g8_b[2] = (~(ex4_res_expo_g4[2] | ex4_res_expo_g4[6])); + + assign ex4_res_expo_c[13] = (~(ex4_res_expo_g8_b[13])); + assign ex4_res_expo_c[12] = (~(ex4_res_expo_g8_b[12])); + assign ex4_res_expo_c[11] = (~(ex4_res_expo_g8_b[11])); + assign ex4_res_expo_c[10] = (~(ex4_res_expo_g8_b[10])); + assign ex4_res_expo_c[9] = (~(ex4_res_expo_g8_b[9])); + assign ex4_res_expo_c[8] = (~(ex4_res_expo_g8_b[8])); + assign ex4_res_expo_c[7] = (~(ex4_res_expo_g8_b[7])); + assign ex4_res_expo_c[6] = (~(ex4_res_expo_g8_b[6])); + assign ex4_res_expo_c[5] = (~(ex4_res_expo_g8_b[5] & ex4_res_expo_g8_b[13])); + assign ex4_res_expo_c[4] = (~(ex4_res_expo_g8_b[4] & ex4_res_expo_g8_b[12])); + assign ex4_res_expo_c[3] = (~(ex4_res_expo_g8_b[3] & ex4_res_expo_g8_b[11])); + assign ex4_res_expo_c[2] = (~(ex4_res_expo_g8_b[2] & ex4_res_expo_g8_b[10])); + + assign ex4_res_decr[1:12] = ex4_res_expo_b[1:12] ^ ex4_res_expo_c[2:13]; + assign ex4_res_decr[13] = ex4_res_expo_b[13]; + + assign f_tbe_ex4_res_expo[1] = (ex4_res_expo[1] & (~ex4_decr_expo) & (~ex4_force_expo_den)) | (ex4_res_decr[1] & ex4_decr_expo); //output + assign f_tbe_ex4_res_expo[2] = (ex4_res_expo[2] & (~ex4_decr_expo) & (~ex4_force_expo_den)) | (ex4_res_decr[2] & ex4_decr_expo); //output + assign f_tbe_ex4_res_expo[3] = (ex4_res_expo[3] & (~ex4_decr_expo) & (~ex4_force_expo_den)) | (ex4_res_decr[3] & ex4_decr_expo); //output + assign f_tbe_ex4_res_expo[4] = (ex4_res_expo[4] & (~ex4_decr_expo) & (~ex4_force_expo_den)) | (ex4_res_decr[4] & ex4_decr_expo); //output + assign f_tbe_ex4_res_expo[5] = (ex4_res_expo[5] & (~ex4_decr_expo) & (~ex4_force_expo_den)) | (ex4_res_decr[5] & ex4_decr_expo); //output + assign f_tbe_ex4_res_expo[6] = (ex4_res_expo[6] & (~ex4_decr_expo) & (~ex4_force_expo_den)) | (ex4_res_decr[6] & ex4_decr_expo); //output + assign f_tbe_ex4_res_expo[7] = (ex4_res_expo[7] & (~ex4_decr_expo) & (~ex4_force_expo_den)) | (ex4_res_decr[7] & ex4_decr_expo); //output + assign f_tbe_ex4_res_expo[8] = (ex4_res_expo[8] & (~ex4_decr_expo) & (~ex4_force_expo_den)) | (ex4_res_decr[8] & ex4_decr_expo); //output + assign f_tbe_ex4_res_expo[9] = (ex4_res_expo[9] & (~ex4_decr_expo) & (~ex4_force_expo_den)) | (ex4_res_decr[9] & ex4_decr_expo); //output + assign f_tbe_ex4_res_expo[10] = (ex4_res_expo[10] & (~ex4_decr_expo) & (~ex4_force_expo_den)) | (ex4_res_decr[10] & ex4_decr_expo); //output + assign f_tbe_ex4_res_expo[11] = (ex4_res_expo[11] & (~ex4_decr_expo) & (~ex4_force_expo_den)) | (ex4_res_decr[11] & ex4_decr_expo); //output + assign f_tbe_ex4_res_expo[12] = (ex4_res_expo[12] & (~ex4_decr_expo) & (~ex4_force_expo_den)) | (ex4_res_decr[12] & ex4_decr_expo); //output + assign f_tbe_ex4_res_expo[13] = (ex4_res_expo[13] & (~ex4_decr_expo)) | (ex4_res_decr[13] & ex4_decr_expo) | (ex4_force_expo_den); //output + + // (not ex4_res_expo(1) and ex4_res_expo(3) ) or + assign f_tbe_ex4_may_ov = ((~ex4_res_expo[1]) & ex4_res_expo[2]) | ((~ex4_res_expo[1]) & ex4_res_expo[3] & ex4_res_expo[4]) | ((~ex4_res_expo[1]) & ex4_res_expo[3] & ex4_res_expo[5]) | ((~ex4_res_expo[1]) & ex4_res_expo[3] & ex4_res_expo[6]) | ((~ex4_res_expo[1]) & ex4_res_expo[3] & ex4_res_expo[7]) | ((~ex4_res_expo[1]) & ex4_res_expo[3] & ex4_res_expo[8] & ex4_res_expo[9]); // before the den adjustments on purpose + + ////############################################ + ////# scan + ////############################################ + + assign ex4_expo_si[0:19] = {ex4_expo_so[1:19], si}; + assign act_si[0:4] = {act_so[1:4], ex4_expo_so[0]}; + assign so = act_so[0]; + +endmodule diff --git a/dev/verilog/work/fu_tbllut.v b/dev/verilog/work/fu_tbllut.v new file mode 100755 index 0000000..c7572f9 --- /dev/null +++ b/dev/verilog/work/fu_tbllut.v @@ -0,0 +1,929 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + + `include "tri_a2o.vh" + +module fu_tbllut( + vdd, + gnd, + clkoff_b, + act_dis, + flush, + delay_lclkr, + mpw1_b, + mpw2_b, + sg_1, + thold_1, + fpu_enable, + nclk, + si, + so, + ex2_act, + f_fmt_ex2_b_frac, + f_fmt_ex3_b_frac, + f_tbe_ex3_expo_lsb, + f_tbe_ex3_est_recip, + f_tbe_ex3_est_rsqrt, + f_tbe_ex4_recip_ue1, + f_tbe_ex4_lu_sh, + f_tbe_ex4_match_en_sp, + f_tbe_ex4_match_en_dp, + f_tbe_ex4_recip_2046, + f_tbe_ex4_recip_2045, + f_tbe_ex4_recip_2044, + f_tbl_ex6_est_frac, + f_tbl_ex5_unf_expo, + f_tbl_ex6_recip_den +); + inout vdd; + inout gnd; + input clkoff_b; // tiup + input act_dis; // ??tidn?? + input flush; // ??tidn?? + input [2:5] delay_lclkr; // tidn, + input [2:5] mpw1_b; // tidn, + input [0:1] mpw2_b; // tidn, + input sg_1; + input thold_1; + input fpu_enable; //dc_act + input [0:`NCLK_WIDTH-1] nclk; + + input si; //perv + output so; //perv + input ex2_act; //act + //---------------------------- + input [1:6] f_fmt_ex2_b_frac; + input [7:22] f_fmt_ex3_b_frac; + input f_tbe_ex3_expo_lsb; + input f_tbe_ex3_est_recip; + input f_tbe_ex3_est_rsqrt; + input f_tbe_ex4_recip_ue1; + input f_tbe_ex4_lu_sh; + input f_tbe_ex4_match_en_sp; + input f_tbe_ex4_match_en_dp; + input f_tbe_ex4_recip_2046; + input f_tbe_ex4_recip_2045; + input f_tbe_ex4_recip_2044; + //---------------------------- + output [0:26] f_tbl_ex6_est_frac; + output f_tbl_ex5_unf_expo; + output f_tbl_ex6_recip_den; //generates den flag + + // ENTITY + + + parameter tiup = 1'b1; + parameter tidn = 1'b0; + + wire ex5_unf_expo; + wire [1:6] ex3_f; + wire ex3_sel_recip; + wire ex3_sel_rsqte; + wire ex3_sel_rsqto; + wire [1:20] ex3_est; + wire [1:20] ex3_est_recip; + wire [1:20] ex3_est_rsqte; + wire [1:20] ex3_est_rsqto; + wire [6:20] ex3_rng; + wire [6:20] ex3_rng_recip; + wire [6:20] ex3_rng_rsqte; + wire [6:20] ex3_rng_rsqto; + + wire thold_0_b; + wire thold_0; + wire force_t; + wire sg_0; + wire ex3_act; + wire ex4_act; + wire ex5_act; + wire [0:3] spare_unused; + + wire [0:5] ex3_lut_so; + wire [0:5] ex3_lut_si; + wire [0:6] act_so; + wire [0:6] act_si; + wire [0:19] ex4_lut_e_so; + wire [0:19] ex4_lut_e_si; + wire [0:14] ex4_lut_r_so; + wire [0:14] ex4_lut_r_si; + wire [0:15] ex4_lut_b_so; + wire [0:15] ex4_lut_b_si; + + wire [6:20] ex4_rng; + wire [6:20] ex4_rng_b; + wire [1:20] ex4_est; + wire [1:20] ex4_est_b; + wire [7:22] ex4_bop; + wire [7:22] ex4_bop_b; + wire [0:36] ex4_tbl_sum; + wire [0:35] ex4_tbl_car; + wire [0:38] ex5_tbl_sum; + wire [0:38] ex5_tbl_car; + + wire [0:79] ex5_lut_so; + wire [0:79] ex5_lut_si; + + wire [0:27] ex6_lut_so; + wire [0:27] ex6_lut_si; + wire [0:27] ex5_lu; + wire [0:27] ex5_lux; + wire [0:26] ex5_lu_nrm; + wire [0:26] ex6_lu; + + wire [0:27] lua_p; + wire [1:37] lua_t; + wire [1:38] lua_g; + wire [1:38] lua_g2; + wire [1:36] lua_g4; + wire [1:32] lua_g8; + wire [1:36] lua_t2; + wire [1:32] lua_t4; + wire [1:28] lua_t8; + wire [1:28] lua_gt8; + wire [0:27] lua_s0_b; + wire [0:27] lua_s1_b; + wire [0:3] lua_g16; + wire [0:1] lua_t16; + wire lua_c32; + wire lua_c24; + wire lua_c16; + wire lua_c08; + wire ex5_recip_den; + wire ex6_recip_den; + wire ex5_lu_sh; + wire ex5_recip_ue1; + wire ex5_recip_2044; + wire ex5_recip_2046; + wire ex5_recip_2045; + wire ex5_recip_2044_dp; + wire ex5_recip_2046_dp; + wire ex5_recip_2045_dp; + wire ex5_recip_2044_sp; + wire ex5_recip_2046_sp; + wire ex5_recip_2045_sp; + + wire ex5_shlft_1; + wire ex5_shlft_0; + wire ex5_shrgt_1; + wire ex5_shrgt_2; + wire ex5_match_en_sp; + wire ex5_match_en_dp; + wire tbl_ex4_d1clk; + wire tbl_ex4_d2clk; + wire tbl_ex5_d1clk; + wire tbl_ex5_d2clk; + wire [0:`NCLK_WIDTH-1] tbl_ex4_lclk; + wire [0:`NCLK_WIDTH-1] tbl_ex5_lclk; + wire unused; + wire [0:36] ex5_tbl_sum_b; + wire [0:35] ex5_tbl_car_b; + wire ex5_match_en_sp_b; + wire ex5_match_en_dp_b; + wire ex5_recip_2046_b; + wire ex5_recip_2045_b; + wire ex5_recip_2044_b; + wire ex5_lu_sh_b; + wire ex5_recip_ue1_b; + + wire ex5_sp_chop_24; + wire ex5_sp_chop_23; + wire ex5_sp_chop_22; + wire ex5_sp_chop_21; + + //==############################################################## + //= map block attributes + //==############################################################## + + assign unused = |(lua_g8[29:31]) | |(lua_g4[33:35]); + + //==############################################################## + //= ex3 logic + //==############################################################## + + + tri_rlmreg_p #(.WIDTH(6)) ex3_lut_lat( + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[2]), + .mpw1_b(mpw1_b[2]), + .mpw2_b(mpw2_b[0]), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_act), + .thold_b(thold_0_b), + .sg(sg_0), + .scout(ex3_lut_so), + .scin(ex3_lut_si), + //----------------- + .din(f_fmt_ex2_b_frac[1:6]), + .dout(ex3_f[1:6]) + ); + + //==############################################################## + //= ex3 logic + //==############################################################## + + //==########################################### + //= rsqrt ev lookup table + //==########################################### + + + fu_tblsqe ftbe( + .f(ex3_f[1:6]), //i-- + .est(ex3_est_rsqte[1:20]), //o-- + .rng(ex3_rng_rsqte[6:20]) //o-- + ); + + //==########################################### + //= rsqrt od lookup table + //==########################################### + + + fu_tblsqo ftbo( + .f(ex3_f[1:6]), //i-- + .est(ex3_est_rsqto[1:20]), //o-- + .rng(ex3_rng_rsqto[6:20]) //o-- + ); + + //==########################################### + //= recip lookup table + //==########################################### + + + fu_tblres ftbr( + .f(ex3_f[1:6]), //i-- + .est(ex3_est_recip[1:20]), //o-- + .rng(ex3_rng_recip[6:20]) //o-- + ); + + //==########################################### + //= muxing + //==########################################### + + assign ex3_sel_recip = f_tbe_ex3_est_recip; + assign ex3_sel_rsqte = f_tbe_ex3_est_rsqrt & (~f_tbe_ex3_expo_lsb); + assign ex3_sel_rsqto = f_tbe_ex3_est_rsqrt & f_tbe_ex3_expo_lsb; + + assign ex3_est[1:20] = ({20{ex3_sel_recip}} & ex3_est_recip[1:20]) | + ({20{ex3_sel_rsqte}} & ex3_est_rsqte[1:20]) | + ({20{ex3_sel_rsqto}} & ex3_est_rsqto[1:20]); // nand2 / nand3 + + assign ex3_rng[6:20] = ({15{ex3_sel_recip}} & (ex3_rng_recip[6:20])) | + ({15{ex3_sel_rsqte}} & (ex3_rng_rsqte[6:20])) | + ({15{ex3_sel_rsqto}} & (ex3_rng_rsqto[6:20])); // nand2 / nand3 + + //==############################################################## + //= ex4 latches + //==############################################################## + + + tri_inv_nlats #(.WIDTH(20), .NEEDS_SRESET(0)) ex4_lut_e_lat( + .vd(vdd), + .gd(gnd), + .lclk(tbl_ex4_lclk), // lclk.clk + .d1clk(tbl_ex4_d1clk), + .d2clk(tbl_ex4_d2clk), + .scanin(ex4_lut_e_si), + .scanout(ex4_lut_e_so), + .d(ex3_est[1:20]), //0:19 + .qb(ex4_est_b[1:20]) //0:19 + ); + + + tri_inv_nlats #(.WIDTH(15), .NEEDS_SRESET(0)) ex4_lut_r_lat( + .vd(vdd), + .gd(gnd), + .lclk(tbl_ex4_lclk), // lclk.clk + .d1clk(tbl_ex4_d1clk), + .d2clk(tbl_ex4_d2clk), + .scanin(ex4_lut_r_si), + .scanout(ex4_lut_r_so), + .d(ex3_rng[6:20]), //20:34 + .qb(ex4_rng_b[6:20]) //20:34 + ); + + + tri_inv_nlats #(.WIDTH(16), .NEEDS_SRESET(0)) ex4_lut_b_lat( + .vd(vdd), + .gd(gnd), + .lclk(tbl_ex4_lclk), // lclk.clk + .d1clk(tbl_ex4_d1clk), + .d2clk(tbl_ex4_d2clk), + .scanin(ex4_lut_b_si), + .scanout(ex4_lut_b_so), + .d(f_fmt_ex3_b_frac[7:22]), //35:50 + .qb(ex4_bop_b[7:22]) //35:50 + ); + + assign ex4_est[1:20] = (~ex4_est_b[1:20]); + assign ex4_rng[6:20] = (~ex4_rng_b[6:20]); + assign ex4_bop[7:22] = (~ex4_bop_b[7:22]); + + //==############################################################## + //= ex4 logic : multiply + //==############################################################## + + + tri_fu_tblmul ftbm( + .vdd(vdd), + .gnd(gnd), + .x(ex4_rng[6:20]), //i-- RECODED + .y(ex4_bop[7:22]), //i-- SHIFTED + .z({tiup,ex4_est[1:20]}), //i-- + .tbl_sum(ex4_tbl_sum[0:36]), //o-- + .tbl_car(ex4_tbl_car[0:35]) //o-- + ); + + //==############################################################## + //= ex5 latches + //==############################################################## + + + tri_inv_nlats #(.WIDTH(80), .NEEDS_SRESET(0)) ex5_lut_lat( + .vd(vdd), + .gd(gnd), + .lclk(tbl_ex5_lclk), // lclk.clk + .d1clk(tbl_ex5_d1clk), + .d2clk(tbl_ex5_d2clk), + .scanin(ex5_lut_si), + .scanout(ex5_lut_so), + .d({ex4_tbl_sum[0:36], + ex4_tbl_car[0:35], + f_tbe_ex4_match_en_sp, + f_tbe_ex4_match_en_dp, + f_tbe_ex4_recip_2046, + f_tbe_ex4_recip_2045, + f_tbe_ex4_recip_2044, + f_tbe_ex4_lu_sh, + f_tbe_ex4_recip_ue1}), + //---- + .qb({ + ex5_tbl_sum_b[0:36], + ex5_tbl_car_b[0:35], + ex5_match_en_sp_b, + ex5_match_en_dp_b, + ex5_recip_2046_b, + ex5_recip_2045_b, + ex5_recip_2044_b, + ex5_lu_sh_b, + ex5_recip_ue1_b}) + ); + + assign ex5_tbl_sum[0:36] = (~ex5_tbl_sum_b[0:36]); + assign ex5_tbl_car[0:35] = (~ex5_tbl_car_b[0:35]); + assign ex5_match_en_sp = (~ex5_match_en_sp_b); + assign ex5_match_en_dp = (~ex5_match_en_dp_b); + assign ex5_recip_2046 = (~ex5_recip_2046_b); + assign ex5_recip_2045 = (~ex5_recip_2045_b); + assign ex5_recip_2044 = (~ex5_recip_2044_b); + assign ex5_lu_sh = (~ex5_lu_sh_b); + assign ex5_recip_ue1 = (~ex5_recip_ue1_b); + + assign ex5_tbl_sum[37] = tidn; + assign ex5_tbl_sum[38] = tidn; + + assign ex5_tbl_car[36] = tidn; //tiup; -- the +1 in -mul = !mul + 1 + assign ex5_tbl_car[37] = tidn; //tiup; -- the +1 in -mul = !mul + 1 + assign ex5_tbl_car[38] = tidn; //tiup; -- the +1 in -mul = !mul + 1 + + //==############################################################## + //= ex5 logic : add + //==############################################################## + // all bits paricipate in the carry, but only upper bits of sum are returned + + // P/G/T ------------------------------------------------------ + assign lua_p[0:27] = ex5_tbl_sum[0:27] ^ ex5_tbl_car[0:27]; + assign lua_t[1:37] = ex5_tbl_sum[1:37] | ex5_tbl_car[1:37]; + assign lua_g[1:38] = ex5_tbl_sum[1:38] & ex5_tbl_car[1:38]; + + // LOCAL BYTE CARRY -------------------------------------------------- + + assign lua_g2[38] = lua_g[38]; + assign lua_g2[37] = lua_g[37] | (lua_t[37] & lua_g[38]); + assign lua_g2[36] = lua_g[36] | (lua_t[36] & lua_g[37]); + assign lua_g2[35] = lua_g[35] | (lua_t[35] & lua_g[36]); + assign lua_g2[34] = lua_g[34] | (lua_t[34] & lua_g[35]); + assign lua_g2[33] = lua_g[33] | (lua_t[33] & lua_g[34]); + assign lua_g2[32] = lua_g[32] | (lua_t[32] & lua_g[33]); + // lua_t2(38) <= lua_t(38) ; + // lua_t2(37) <= lua_t(37) and lua_t(38) ; + assign lua_t2[36] = lua_t[36] & lua_t[37]; + assign lua_t2[35] = lua_t[35] & lua_t[36]; + assign lua_t2[34] = lua_t[34] & lua_t[35]; + assign lua_t2[33] = lua_t[33] & lua_t[34]; + assign lua_t2[32] = lua_t[32] & lua_t[33]; + // lua_g4(38) <= lua_g2(38) ; + // lua_g4(37) <= lua_g2(37) ; + assign lua_g4[36] = lua_g2[36] | (lua_t2[36] & lua_g2[38]); + assign lua_g4[35] = lua_g2[35] | (lua_t2[35] & lua_g2[37]); + assign lua_g4[34] = lua_g2[34] | (lua_t2[34] & lua_g2[36]); + assign lua_g4[33] = lua_g2[33] | (lua_t2[33] & lua_g2[35]); + assign lua_g4[32] = lua_g2[32] | (lua_t2[32] & lua_g2[34]); + // lua_t4(38) <= lua_t2(38) ; + // lua_t4(37) <= lua_t2(37) ; + // lua_t4(36) <= lua_t2(36) and lua_t2(38) ; + // lua_t4(35) <= lua_t2(35) and lua_t2(37) ; + // lua_t4(34) <= lua_t2(34) and lua_t2(36) ; + // lua_t4(33) <= lua_t2(33) and lua_t2(35) ; + assign lua_t4[32] = lua_t2[32] & lua_t2[34]; + //lua_g8(38) <= lua_g4(38) ; + //lua_g8(37) <= lua_g4(37) ; + //lua_g8(36) <= lua_g4(36) ; + //lua_g8(35) <= lua_g4(35) ; + //lua_g8(34) <= lua_g4(34) or (lua_t4(34) and lua_g4(38) ); + //lua_g8(33) <= lua_g4(33) or (lua_t4(33) and lua_g4(37) ); + assign lua_g8[32] = lua_g4[32] | (lua_t4[32] & lua_g4[36]); + //lua_t8(38) <= lua_t4(38) ; + //lua_t8(37) <= lua_t4(37) ; + //lua_t8(36) <= lua_t4(36) ; + //lua_t8(35) <= lua_t4(35) ; + //lua_t8(34) <= lua_t4(34) and lua_t4(38) ; + //lua_t8(33) <= lua_t4(33) and lua_t4(37) ; + //lua_t8(32) <= lua_t4(32) and lua_t4(36) ; + + assign lua_g2[31] = lua_g[31]; + assign lua_g2[30] = lua_g[30] | (lua_t[30] & lua_g[31]); + assign lua_g2[29] = lua_g[29] | (lua_t[29] & lua_g[30]); + assign lua_g2[28] = lua_g[28] | (lua_t[28] & lua_g[29]); + assign lua_g2[27] = lua_g[27] | (lua_t[27] & lua_g[28]); + assign lua_g2[26] = lua_g[26] | (lua_t[26] & lua_g[27]); + assign lua_g2[25] = lua_g[25] | (lua_t[25] & lua_g[26]); + assign lua_g2[24] = lua_g[24] | (lua_t[24] & lua_g[25]); + assign lua_t2[31] = lua_t[31]; + assign lua_t2[30] = lua_t[30] & lua_t[31]; + assign lua_t2[29] = lua_t[29] & lua_t[30]; + assign lua_t2[28] = lua_t[28] & lua_t[29]; + assign lua_t2[27] = lua_t[27] & lua_t[28]; + assign lua_t2[26] = lua_t[26] & lua_t[27]; + assign lua_t2[25] = lua_t[25] & lua_t[26]; + assign lua_t2[24] = lua_t[24] & lua_t[25]; + assign lua_g4[31] = lua_g2[31]; + assign lua_g4[30] = lua_g2[30]; + assign lua_g4[29] = lua_g2[29] | (lua_t2[29] & lua_g2[31]); + assign lua_g4[28] = lua_g2[28] | (lua_t2[28] & lua_g2[30]); + assign lua_g4[27] = lua_g2[27] | (lua_t2[27] & lua_g2[29]); + assign lua_g4[26] = lua_g2[26] | (lua_t2[26] & lua_g2[28]); + assign lua_g4[25] = lua_g2[25] | (lua_t2[25] & lua_g2[27]); + assign lua_g4[24] = lua_g2[24] | (lua_t2[24] & lua_g2[26]); + assign lua_t4[31] = lua_t2[31]; + assign lua_t4[30] = lua_t2[30]; + assign lua_t4[29] = lua_t2[29] & lua_t2[31]; + assign lua_t4[28] = lua_t2[28] & lua_t2[30]; + assign lua_t4[27] = lua_t2[27] & lua_t2[29]; + assign lua_t4[26] = lua_t2[26] & lua_t2[28]; + assign lua_t4[25] = lua_t2[25] & lua_t2[27]; + assign lua_t4[24] = lua_t2[24] & lua_t2[26]; + assign lua_g8[31] = lua_g4[31]; + assign lua_g8[30] = lua_g4[30]; + assign lua_g8[29] = lua_g4[29]; + assign lua_g8[28] = lua_g4[28]; + assign lua_g8[27] = lua_g4[27] | (lua_t4[27] & lua_g4[31]); + assign lua_g8[26] = lua_g4[26] | (lua_t4[26] & lua_g4[30]); + assign lua_g8[25] = lua_g4[25] | (lua_t4[25] & lua_g4[29]); + assign lua_g8[24] = lua_g4[24] | (lua_t4[24] & lua_g4[28]); + // lua_t8(31) <= lua_t4(31) ; + // lua_t8(30) <= lua_t4(30) ; + // lua_t8(29) <= lua_t4(29) ; + assign lua_t8[28] = lua_t4[28]; + assign lua_t8[27] = lua_t4[27] & lua_t4[31]; + assign lua_t8[26] = lua_t4[26] & lua_t4[30]; + assign lua_t8[25] = lua_t4[25] & lua_t4[29]; + assign lua_t8[24] = lua_t4[24] & lua_t4[28]; + + assign lua_g2[23] = lua_g[23]; + assign lua_g2[22] = lua_g[22] | (lua_t[22] & lua_g[23]); + assign lua_g2[21] = lua_g[21] | (lua_t[21] & lua_g[22]); + assign lua_g2[20] = lua_g[20] | (lua_t[20] & lua_g[21]); + assign lua_g2[19] = lua_g[19] | (lua_t[19] & lua_g[20]); + assign lua_g2[18] = lua_g[18] | (lua_t[18] & lua_g[19]); + assign lua_g2[17] = lua_g[17] | (lua_t[17] & lua_g[18]); + assign lua_g2[16] = lua_g[16] | (lua_t[16] & lua_g[17]); + assign lua_t2[23] = lua_t[23]; + assign lua_t2[22] = lua_t[22] & lua_t[23]; + assign lua_t2[21] = lua_t[21] & lua_t[22]; + assign lua_t2[20] = lua_t[20] & lua_t[21]; + assign lua_t2[19] = lua_t[19] & lua_t[20]; + assign lua_t2[18] = lua_t[18] & lua_t[19]; + assign lua_t2[17] = lua_t[17] & lua_t[18]; + assign lua_t2[16] = lua_t[16] & lua_t[17]; + assign lua_g4[23] = lua_g2[23]; + assign lua_g4[22] = lua_g2[22]; + assign lua_g4[21] = lua_g2[21] | (lua_t2[21] & lua_g2[23]); + assign lua_g4[20] = lua_g2[20] | (lua_t2[20] & lua_g2[22]); + assign lua_g4[19] = lua_g2[19] | (lua_t2[19] & lua_g2[21]); + assign lua_g4[18] = lua_g2[18] | (lua_t2[18] & lua_g2[20]); + assign lua_g4[17] = lua_g2[17] | (lua_t2[17] & lua_g2[19]); + assign lua_g4[16] = lua_g2[16] | (lua_t2[16] & lua_g2[18]); + assign lua_t4[23] = lua_t2[23]; + assign lua_t4[22] = lua_t2[22]; + assign lua_t4[21] = lua_t2[21] & lua_t2[23]; + assign lua_t4[20] = lua_t2[20] & lua_t2[22]; + assign lua_t4[19] = lua_t2[19] & lua_t2[21]; + assign lua_t4[18] = lua_t2[18] & lua_t2[20]; + assign lua_t4[17] = lua_t2[17] & lua_t2[19]; + assign lua_t4[16] = lua_t2[16] & lua_t2[18]; + assign lua_g8[23] = lua_g4[23]; + assign lua_g8[22] = lua_g4[22]; + assign lua_g8[21] = lua_g4[21]; + assign lua_g8[20] = lua_g4[20]; + assign lua_g8[19] = lua_g4[19] | (lua_t4[19] & lua_g4[23]); + assign lua_g8[18] = lua_g4[18] | (lua_t4[18] & lua_g4[22]); + assign lua_g8[17] = lua_g4[17] | (lua_t4[17] & lua_g4[21]); + assign lua_g8[16] = lua_g4[16] | (lua_t4[16] & lua_g4[20]); + assign lua_t8[23] = lua_t4[23]; + assign lua_t8[22] = lua_t4[22]; + assign lua_t8[21] = lua_t4[21]; + assign lua_t8[20] = lua_t4[20]; + assign lua_t8[19] = lua_t4[19] & lua_t4[23]; + assign lua_t8[18] = lua_t4[18] & lua_t4[22]; + assign lua_t8[17] = lua_t4[17] & lua_t4[21]; + assign lua_t8[16] = lua_t4[16] & lua_t4[20]; + + assign lua_g2[15] = lua_g[15]; + assign lua_g2[14] = lua_g[14] | (lua_t[14] & lua_g[15]); + assign lua_g2[13] = lua_g[13] | (lua_t[13] & lua_g[14]); + assign lua_g2[12] = lua_g[12] | (lua_t[12] & lua_g[13]); + assign lua_g2[11] = lua_g[11] | (lua_t[11] & lua_g[12]); + assign lua_g2[10] = lua_g[10] | (lua_t[10] & lua_g[11]); + assign lua_g2[9] = lua_g[9] | (lua_t[9] & lua_g[10]); + assign lua_g2[8] = lua_g[8] | (lua_t[8] & lua_g[9]); + assign lua_t2[15] = lua_t[15]; + assign lua_t2[14] = lua_t[14] & lua_t[15]; + assign lua_t2[13] = lua_t[13] & lua_t[14]; + assign lua_t2[12] = lua_t[12] & lua_t[13]; + assign lua_t2[11] = lua_t[11] & lua_t[12]; + assign lua_t2[10] = lua_t[10] & lua_t[11]; + assign lua_t2[9] = lua_t[9] & lua_t[10]; + assign lua_t2[8] = lua_t[8] & lua_t[9]; + assign lua_g4[15] = lua_g2[15]; + assign lua_g4[14] = lua_g2[14]; + assign lua_g4[13] = lua_g2[13] | (lua_t2[13] & lua_g2[15]); + assign lua_g4[12] = lua_g2[12] | (lua_t2[12] & lua_g2[14]); + assign lua_g4[11] = lua_g2[11] | (lua_t2[11] & lua_g2[13]); + assign lua_g4[10] = lua_g2[10] | (lua_t2[10] & lua_g2[12]); + assign lua_g4[9] = lua_g2[9] | (lua_t2[9] & lua_g2[11]); + assign lua_g4[8] = lua_g2[8] | (lua_t2[8] & lua_g2[10]); + assign lua_t4[15] = lua_t2[15]; + assign lua_t4[14] = lua_t2[14]; + assign lua_t4[13] = lua_t2[13] & lua_t2[15]; + assign lua_t4[12] = lua_t2[12] & lua_t2[14]; + assign lua_t4[11] = lua_t2[11] & lua_t2[13]; + assign lua_t4[10] = lua_t2[10] & lua_t2[12]; + assign lua_t4[9] = lua_t2[9] & lua_t2[11]; + assign lua_t4[8] = lua_t2[8] & lua_t2[10]; + assign lua_g8[15] = lua_g4[15]; + assign lua_g8[14] = lua_g4[14]; + assign lua_g8[13] = lua_g4[13]; + assign lua_g8[12] = lua_g4[12]; + assign lua_g8[11] = lua_g4[11] | (lua_t4[11] & lua_g4[15]); + assign lua_g8[10] = lua_g4[10] | (lua_t4[10] & lua_g4[14]); + assign lua_g8[9] = lua_g4[9] | (lua_t4[9] & lua_g4[13]); + assign lua_g8[8] = lua_g4[8] | (lua_t4[8] & lua_g4[12]); + assign lua_t8[15] = lua_t4[15]; + assign lua_t8[14] = lua_t4[14]; + assign lua_t8[13] = lua_t4[13]; + assign lua_t8[12] = lua_t4[12]; + assign lua_t8[11] = lua_t4[11] & lua_t4[15]; + assign lua_t8[10] = lua_t4[10] & lua_t4[14]; + assign lua_t8[9] = lua_t4[9] & lua_t4[13]; + assign lua_t8[8] = lua_t4[8] & lua_t4[12]; + + assign lua_g2[7] = lua_g[7]; + assign lua_g2[6] = lua_g[6] | (lua_t[6] & lua_g[7]); + assign lua_g2[5] = lua_g[5] | (lua_t[5] & lua_g[6]); + assign lua_g2[4] = lua_g[4] | (lua_t[4] & lua_g[5]); + assign lua_g2[3] = lua_g[3] | (lua_t[3] & lua_g[4]); + assign lua_g2[2] = lua_g[2] | (lua_t[2] & lua_g[3]); + assign lua_g2[1] = lua_g[1] | (lua_t[1] & lua_g[2]); + // lua_g2(0) <= lua_g(0) or (lua_t(0) and lua_g(1) ); + assign lua_t2[7] = lua_t[7]; + assign lua_t2[6] = lua_t[6] & lua_t[7]; + assign lua_t2[5] = lua_t[5] & lua_t[6]; + assign lua_t2[4] = lua_t[4] & lua_t[5]; + assign lua_t2[3] = lua_t[3] & lua_t[4]; + assign lua_t2[2] = lua_t[2] & lua_t[3]; + assign lua_t2[1] = lua_t[1] & lua_t[2]; + // lua_t2(0) <= lua_t(0) and lua_t(1) ; + assign lua_g4[7] = lua_g2[7]; + assign lua_g4[6] = lua_g2[6]; + assign lua_g4[5] = lua_g2[5] | (lua_t2[5] & lua_g2[7]); + assign lua_g4[4] = lua_g2[4] | (lua_t2[4] & lua_g2[6]); + assign lua_g4[3] = lua_g2[3] | (lua_t2[3] & lua_g2[5]); + assign lua_g4[2] = lua_g2[2] | (lua_t2[2] & lua_g2[4]); + assign lua_g4[1] = lua_g2[1] | (lua_t2[1] & lua_g2[3]); + // lua_g4(0) <= lua_g2(0) or (lua_t2(0) and lua_g2(2) ); + assign lua_t4[7] = lua_t2[7]; + assign lua_t4[6] = lua_t2[6]; + assign lua_t4[5] = lua_t2[5] & lua_t2[7]; + assign lua_t4[4] = lua_t2[4] & lua_t2[6]; + assign lua_t4[3] = lua_t2[3] & lua_t2[5]; + assign lua_t4[2] = lua_t2[2] & lua_t2[4]; + assign lua_t4[1] = lua_t2[1] & lua_t2[3]; + // lua_t4(0) <= lua_t2(0) and lua_t2(2) ; + assign lua_g8[7] = lua_g4[7]; + assign lua_g8[6] = lua_g4[6]; + assign lua_g8[5] = lua_g4[5]; + assign lua_g8[4] = lua_g4[4]; + assign lua_g8[3] = lua_g4[3] | (lua_t4[3] & lua_g4[7]); + assign lua_g8[2] = lua_g4[2] | (lua_t4[2] & lua_g4[6]); + assign lua_g8[1] = lua_g4[1] | (lua_t4[1] & lua_g4[5]); + //lua_g8(0) <= lua_g4(0) or (lua_t4(0) and lua_g4(4) ); + assign lua_t8[7] = lua_t4[7]; + assign lua_t8[6] = lua_t4[6]; + assign lua_t8[5] = lua_t4[5]; + assign lua_t8[4] = lua_t4[4]; + assign lua_t8[3] = lua_t4[3] & lua_t4[7]; + assign lua_t8[2] = lua_t4[2] & lua_t4[6]; + assign lua_t8[1] = lua_t4[1] & lua_t4[5]; + //lua_t8(0) <= lua_t4(0) and lua_t4(4) ; + + // CONDITIONL SUM --------------------------------------------- + + assign lua_gt8[1:28] = lua_g8[1:28] | lua_t8[1:28]; + + assign lua_s1_b[0:27] = (~(lua_p[0:27] ^ lua_gt8[1:28])); + assign lua_s0_b[0:27] = (~(lua_p[0:27] ^ lua_g8[1:28])); + + // BYTE SELECT ------------------------------ + // ex5_lu(0 to 27) <= not( ex5_lu_p(0 to 27) xor ex5_lu_c(1 to 28) ); -- invert + + assign ex5_lu[0] = (lua_s0_b[0] & (~lua_c08)) | (lua_s1_b[0] & lua_c08); + assign ex5_lu[1] = (lua_s0_b[1] & (~lua_c08)) | (lua_s1_b[1] & lua_c08); + assign ex5_lu[2] = (lua_s0_b[2] & (~lua_c08)) | (lua_s1_b[2] & lua_c08); + assign ex5_lu[3] = (lua_s0_b[3] & (~lua_c08)) | (lua_s1_b[3] & lua_c08); + assign ex5_lu[4] = (lua_s0_b[4] & (~lua_c08)) | (lua_s1_b[4] & lua_c08); + assign ex5_lu[5] = (lua_s0_b[5] & (~lua_c08)) | (lua_s1_b[5] & lua_c08); + assign ex5_lu[6] = (lua_s0_b[6] & (~lua_c08)) | (lua_s1_b[6] & lua_c08); + assign ex5_lu[7] = (lua_s0_b[7] & (~lua_c08)) | (lua_s1_b[7] & lua_c08); + + assign ex5_lu[8] = (lua_s0_b[8] & (~lua_c16)) | (lua_s1_b[8] & lua_c16); + assign ex5_lu[9] = (lua_s0_b[9] & (~lua_c16)) | (lua_s1_b[9] & lua_c16); + assign ex5_lu[10] = (lua_s0_b[10] & (~lua_c16)) | (lua_s1_b[10] & lua_c16); + assign ex5_lu[11] = (lua_s0_b[11] & (~lua_c16)) | (lua_s1_b[11] & lua_c16); + assign ex5_lu[12] = (lua_s0_b[12] & (~lua_c16)) | (lua_s1_b[12] & lua_c16); + assign ex5_lu[13] = (lua_s0_b[13] & (~lua_c16)) | (lua_s1_b[13] & lua_c16); + assign ex5_lu[14] = (lua_s0_b[14] & (~lua_c16)) | (lua_s1_b[14] & lua_c16); + assign ex5_lu[15] = (lua_s0_b[15] & (~lua_c16)) | (lua_s1_b[15] & lua_c16); + + assign ex5_lu[16] = (lua_s0_b[16] & (~lua_c24)) | (lua_s1_b[16] & lua_c24); + assign ex5_lu[17] = (lua_s0_b[17] & (~lua_c24)) | (lua_s1_b[17] & lua_c24); + assign ex5_lu[18] = (lua_s0_b[18] & (~lua_c24)) | (lua_s1_b[18] & lua_c24); + assign ex5_lu[19] = (lua_s0_b[19] & (~lua_c24)) | (lua_s1_b[19] & lua_c24); + assign ex5_lu[20] = (lua_s0_b[20] & (~lua_c24)) | (lua_s1_b[20] & lua_c24); + assign ex5_lu[21] = (lua_s0_b[21] & (~lua_c24)) | (lua_s1_b[21] & lua_c24); + assign ex5_lu[22] = (lua_s0_b[22] & (~lua_c24)) | (lua_s1_b[22] & lua_c24); + assign ex5_lu[23] = (lua_s0_b[23] & (~lua_c24)) | (lua_s1_b[23] & lua_c24); + + assign ex5_lu[24] = (lua_s0_b[24] & (~lua_c32)) | (lua_s1_b[24] & lua_c32); + assign ex5_lu[25] = (lua_s0_b[25] & (~lua_c32)) | (lua_s1_b[25] & lua_c32); + assign ex5_lu[26] = (lua_s0_b[26] & (~lua_c32)) | (lua_s1_b[26] & lua_c32); + assign ex5_lu[27] = (lua_s0_b[27] & (~lua_c32)) | (lua_s1_b[27] & lua_c32); + + // GLOBAL BYTE CARRY ------------------------------ + + assign lua_g16[3] = lua_g8[32]; + assign lua_g16[2] = lua_g8[24] | (lua_t8[24] & lua_g8[32]); + assign lua_g16[1] = lua_g8[16] | (lua_t8[16] & lua_g8[24]); + assign lua_g16[0] = lua_g8[8] | (lua_t8[8] & lua_g8[16]); + + //lua_t16(3) <= lua_t8(32); + //lua_t16(2) <= lua_t8(24) and lua_t8(32) ; + assign lua_t16[1] = lua_t8[16] & lua_t8[24]; + assign lua_t16[0] = lua_t8[8] & lua_t8[16]; + + assign lua_c32 = lua_g16[3]; + assign lua_c24 = lua_g16[2]; + assign lua_c16 = lua_g16[1] | (lua_t16[1] & lua_g16[3]); + assign lua_c08 = lua_g16[0] | (lua_t16[0] & lua_g16[2]); + + //--------------------------------------------------------------- + // normalize + //--------------------------------------------------------------- + // expo=2046 ==> imp=0 shift right 1 + // expo=2045 ==> imp=0 shift right 0 + // expo=other => imp=1 shift right 0 + assign ex5_recip_2044_dp = ex5_recip_2044 & ex5_match_en_dp & (~ex5_recip_ue1); + assign ex5_recip_2045_dp = ex5_recip_2045 & ex5_match_en_dp & (~ex5_recip_ue1); + assign ex5_recip_2046_dp = ex5_recip_2046 & ex5_match_en_dp & (~ex5_recip_ue1); + + assign ex5_recip_2044_sp = ex5_recip_2044 & ex5_match_en_sp & (~ex5_recip_ue1); + assign ex5_recip_2045_sp = ex5_recip_2045 & ex5_match_en_sp & (~ex5_recip_ue1); + assign ex5_recip_2046_sp = ex5_recip_2046 & ex5_match_en_sp & (~ex5_recip_ue1); + + // lu_sh means : shift left one, and decr exponent (unless it will create a denorm exponent) + + // result in norm dp fmt, but set fpscr flag for sp unf + // result in norm dp fmt, but set fpscr flag for sp unf + // result in norm dp fmt, but set fpscr flag for sp unf + assign ex5_recip_den = ex5_recip_2046_sp | ex5_recip_2045_sp | (ex5_lu_sh & ex5_recip_2044_sp) | ex5_recip_2046_dp | ex5_recip_2045_dp | (ex5_lu_sh & ex5_recip_2044_dp); // use in round to set implicit bit + // cannot shift left , denorm result + + // by not denormalizing sp the fpscr(ux) is set even though the implicit bit is set + // divide does not want the denormed result + // for setting UX (same for ue=0, ue=1 + // ( ex5_match_en_dp) and -- leave SP normalized + assign ex5_unf_expo = (ex5_match_en_sp | ex5_match_en_dp) & (ex5_recip_2046 | ex5_recip_2045 | (ex5_recip_2044 & ex5_lu_sh)); // leave SP normalized + + assign f_tbl_ex5_unf_expo = ex5_unf_expo; //output-- + + assign ex5_shlft_1 = (~ex5_recip_2046_dp) & (~ex5_recip_2045_dp) & (ex5_lu_sh & (~ex5_recip_2044_dp)); + assign ex5_shlft_0 = (~ex5_recip_2046_dp) & (~ex5_recip_2045_dp) & (~(ex5_lu_sh & (~ex5_recip_2044_dp))); + assign ex5_shrgt_1 = ex5_recip_2045_dp; + assign ex5_shrgt_2 = ex5_recip_2046_dp; + + // the final sp result will be in dp_norm format for an sp_denorm. + // emulate the dropping of bits when an sp is shifted right then fitted into 23 frac bits. + + assign ex5_sp_chop_24 = ex5_recip_2046_sp | ex5_recip_2045_sp | ex5_recip_2044_sp; + assign ex5_sp_chop_23 = ex5_recip_2046_sp | ex5_recip_2045_sp; + assign ex5_sp_chop_22 = ex5_recip_2046_sp; + assign ex5_sp_chop_21 = tidn; + + assign ex5_lux[0:20] = ex5_lu[0:20]; + assign ex5_lux[21] = ex5_lu[21] & (~ex5_sp_chop_21); + assign ex5_lux[22] = ex5_lu[22] & (~ex5_sp_chop_22); + assign ex5_lux[23] = ex5_lu[23] & (~ex5_sp_chop_23); + assign ex5_lux[24] = ex5_lu[24] & (~ex5_sp_chop_24); + assign ex5_lux[25:27] = ex5_lu[25:27]; + + assign ex5_lu_nrm[0:26] = ({27{ex5_shlft_1}} & (ex5_lux[1:27])) | + ({27{ex5_shlft_0}} & (ex5_lux[0:26])) | + ({27{ex5_shrgt_1}} & ({tidn, ex5_lux[0:25]})) | + ({27{ex5_shrgt_2}} & ({tidn, tidn, ex5_lux[0:24]})); + + //==############################################################## + //= ex6 latches + //==############################################################## + + + tri_rlmreg_p #(.WIDTH(28)) ex6_lut_lat( + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[5]), + .mpw1_b(mpw1_b[5]), + .mpw2_b(mpw2_b[1]), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_act), + .thold_b(thold_0_b), + .sg(sg_0), + .scout(ex6_lut_so), + .scin(ex6_lut_si), + //----------------- + .din({ex5_lu_nrm[0:26], + ex5_recip_den}), + .dout({ex6_lu[0:26], + ex6_recip_den}) + ); + + assign f_tbl_ex6_est_frac[0:26] = ex6_lu[0:26]; + assign f_tbl_ex6_recip_den = ex6_recip_den; + + //==############################################################## + //= pervasive + //==############################################################## + + + tri_plat thold_reg_0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(flush), + .din(thold_1), + .q(thold_0) + ); + + + tri_plat sg_reg_0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(flush), + .din(sg_1), + .q(sg_0) + ); + + + tri_lcbor lcbor_0( + .clkoff_b(clkoff_b), + .thold(thold_0), + .sg(sg_0), + .act_dis(act_dis), + .force_t(force_t), + .thold_b(thold_0_b) + ); + + //==############################################################## + //= act + //==############################################################## + + + tri_rlmreg_p #(.WIDTH(7)) act_lat( + .force_t(force_t), + .d_mode(tiup), + .delay_lclkr(delay_lclkr[4]), + .mpw1_b(mpw1_b[4]), + .mpw2_b(mpw2_b[0]), + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(fpu_enable), + .thold_b(thold_0_b), + .sg(sg_0), + .scout(act_so), + .scin(act_si), + //----------------- + .din({spare_unused[0], + spare_unused[1], + ex2_act, + ex3_act, + ex4_act, + spare_unused[2], + spare_unused[3]}), + //----------------- + .dout({ spare_unused[0], + spare_unused[1], + ex3_act, + ex4_act, + ex5_act, + spare_unused[2], + spare_unused[3]}) + ); + + + tri_lcbnd tbl_ex4_lcb( + .delay_lclkr(delay_lclkr[3]), // tidn ,--in + .mpw1_b(mpw1_b[3]), // tidn ,--in + .mpw2_b(mpw2_b[0]), // tidn ,--in + .force_t(force_t), // tidn ,--in + .nclk(nclk), //in + .vd(vdd), //inout + .gd(gnd), //inout + .act(ex3_act), //in + .sg(sg_0), //in + .thold_b(thold_0_b), //in + .d1clk(tbl_ex4_d1clk), //out + .d2clk(tbl_ex4_d2clk), //out + .lclk(tbl_ex4_lclk) //out + ); + + + tri_lcbnd tbl_ex5_lcb( + .delay_lclkr(delay_lclkr[4]), // tidn ,--in + .mpw1_b(mpw1_b[4]), // tidn ,--in + .mpw2_b(mpw2_b[0]), // tidn ,--in + .force_t(force_t), // tidn ,--in + .nclk(nclk), //in + .vd(vdd), //inout + .gd(gnd), //inout + .act(ex4_act), //in + .sg(sg_0), //in + .thold_b(thold_0_b), //in + .d1clk(tbl_ex5_d1clk), //out + .d2clk(tbl_ex5_d2clk), //out + .lclk(tbl_ex5_lclk) //out + ); + + //==############################################################## + //= scan string + //==############################################################## + + assign ex3_lut_si[0:5] = {ex3_lut_so[1:5], si}; + assign ex4_lut_e_si[0:19] = {ex4_lut_e_so[1:19], ex3_lut_so[0]}; + assign ex4_lut_r_si[0:14] = {ex4_lut_r_so[1:14], ex4_lut_e_so[0]}; + assign ex4_lut_b_si[0:15] = {ex4_lut_b_so[1:15], ex4_lut_r_so[0]}; + assign ex5_lut_si[0:79] = {ex5_lut_so[1:79], ex4_lut_b_so[0]}; + assign ex6_lut_si[0:27] = {ex6_lut_so[1:27], ex5_lut_so[0]}; + assign act_si[0:6] = {act_so[1:6], ex6_lut_so[0]}; + assign so = act_so[0]; //SCAN + +endmodule diff --git a/dev/verilog/work/fu_tblres.v b/dev/verilog/work/fu_tblres.v new file mode 100755 index 0000000..5ce1729 --- /dev/null +++ b/dev/verilog/work/fu_tblres.v @@ -0,0 +1,972 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + + + `include "tri_a2o.vh" + +// 11111111111111000000 111111000000101 0 +// 11111000000110111001 111101000110110 1 +// 11110000011110000001 111011010010000 2 +// 11101001000011110001 111001100010010 3 +// 11100001110111011111 110111110111100 4 +// 11011010111000100001 110110010001100 5 +// 11010100000110010101 110100101111100 6 +// 11001101100000010111 110011010001110 7 +// 11000111000110000111 110001111000000 8 +// 11000000110111000111 110000100001100 9 +// 10111010110010111001 101111001110110 10 +// 10110100111001000001 101101111111010 11 +// 10101111001001000111 101100110010110 12 +// 10101001100010101111 101011101001010 13 +// 10100100000101100101 101010100010100 14 +// 10011110110001001111 101001011110100 15 +// 10011001100101011001 101000011101000 16 +// 10010100100001110001 100111011101110 17 +// 10001111100110000001 100110100001000 18 +// 10001010110001111001 100101100110010 19 +// 10000110000101000111 100100101101110 20 +// 10000001011111011001 100011110111000 21 +// 01111101000000011111 100011000010010 22 +// 01111000101000001101 100010001111010 23 +// 01110100010110010001 100001011110000 24 +// 01110000001010100001 100000101110100 25 +// 01101100000100101101 100000000000100 26 +// 01101000000100101001 011111010011110 27 +// 01100100001010001001 011110101000110 28 +// 01100000010101000001 011101111111000 29 +// 01011100100101001001 011101010110100 30 +// 01011000111010010011 011100101111100 31 +// 01010101010100010101 011100001001100 32 +// 01010001110011000111 011011100100110 33 +// 01001110010110100001 011011000001010 34 +// 01001010111110010111 011010011110100 35 +// 01000111101010100001 011001111101000 36 +// 01000100011010111001 011001011100100 37 +// 01000001001111010101 011000111100110 38 +// 00111110000111101101 011000011110000 39 +// 00111011000011111011 011000000000010 40 +// 00111000000011111001 010111100011010 41 +// 00110101000111011101 010111000111000 42 +// 00110010001110100011 010110101011110 43 +// 00101111011001000101 010110010001000 44 +// 00101100100110111011 010101110111010 45 +// 00101001111000000001 010101011110000 46 +// 00100111001100010001 010101000101100 47 +// 00100100100011100101 010100101101100 48 +// 00100001111101110111 010100010110010 49 +// 00011111011011000101 010011111111100 50 +// 00011100111011000111 010011101001100 51 +// 00011010011101111001 010011010100000 52 +// 00011000000011011001 010010111111000 53 +// 00010101101011011111 010010101010110 54 +// 00010011010110001001 010010010110110 55 +// 00010001000011010001 010010000011010 56 +// 00001110110010110101 010001110000100 57 +// 00001100100100110001 010001011110000 58 +// 00001010011001000001 010001001100000 59 +// 00001000001111100001 010000111010010 60 +// 00000110001000001101 010000101001000 61 +// 00000100000011000101 010000011000010 62 +// 00000010000000000001 010000001000000 63 + +module fu_tblres( + f, + est, + rng +); + input [1:6] f; + output [1:20] est; + output [6:20] rng; + + // end ports + + // ENTITY + + + parameter tiup = 1'b1; + parameter tidn = 1'b0; + + wire dcd_00x; + wire dcd_01x; + wire dcd_10x; + wire dcd_11x; + wire dcd_000; + wire dcd_001; + wire dcd_010; + wire dcd_011; + wire dcd_100; + wire dcd_101; + wire dcd_110; + wire dcd_111; + wire combo2_1000; + wire combo2_0100; + wire combo2_1100; + wire combo2_0010; + wire combo2_1010; + wire combo2_0110; + wire combo2_1110; + wire combo2_0001; + wire combo2_1001; + wire combo2_0101; + wire combo2_1101; + wire combo2_0011; + wire combo2_1011; + wire combo2_0111; + wire combo2_1000_xxxx_b; + wire combo2_0100_xxxx_b; + wire combo2_1100_xxxx_b; + wire combo2_0010_xxxx_b; + wire combo2_1010_xxxx_b; + wire combo2_0110_xxxx_b; + wire combo2_1110_xxxx_b; + wire combo2_0001_xxxx_b; + wire combo2_1001_xxxx_b; + wire combo2_0101_xxxx_b; + wire combo2_1101_xxxx_b; + wire combo2_0011_xxxx_b; + wire combo2_1011_xxxx_b; + wire combo2_0111_xxxx_b; + wire combo2_xxxx_1000_b; + wire combo2_xxxx_0100_b; + wire combo2_xxxx_1100_b; + wire combo2_xxxx_0010_b; + wire combo2_xxxx_1010_b; + wire combo2_xxxx_0110_b; + wire combo2_xxxx_1110_b; + wire combo2_xxxx_0001_b; + wire combo2_xxxx_1001_b; + wire combo2_xxxx_0101_b; + wire combo2_xxxx_1101_b; + wire combo2_xxxx_0011_b; + wire combo2_xxxx_1011_b; + wire combo2_xxxx_0111_b; + wire combo3_0000_0001; + wire combo3_0000_0010; + wire combo3_0000_0011; + wire combo3_0000_0100; + wire combo3_0000_0101; + wire combo3_0000_0110; + wire combo3_0000_1001; + wire combo3_0000_1010; + wire combo3_0000_1011; + wire combo3_0000_1110; + wire combo3_0000_1111; + wire combo3_0001_0001; + wire combo3_0001_0010; + wire combo3_0001_0100; + wire combo3_0001_0101; + wire combo3_0001_0111; + wire combo3_0001_1000; + wire combo3_0001_1010; + wire combo3_0001_1011; + wire combo3_0001_1100; + wire combo3_0001_1110; + wire combo3_0001_1111; + wire combo3_0010_0000; + wire combo3_0010_0100; + wire combo3_0010_0101; + wire combo3_0010_0110; + wire combo3_0010_0111; + wire combo3_0010_1000; + wire combo3_0010_1001; + wire combo3_0010_1101; + wire combo3_0011_0000; + wire combo3_0011_0001; + wire combo3_0011_0011; + wire combo3_0011_0101; + wire combo3_0011_1000; + wire combo3_0011_1001; + wire combo3_0011_1010; + wire combo3_0011_1011; + wire combo3_0011_1100; + wire combo3_0011_1110; + wire combo3_0011_1111; + wire combo3_0100_0000; + wire combo3_0100_0011; + wire combo3_0100_0110; + wire combo3_0100_1000; + wire combo3_0100_1001; + wire combo3_0100_1010; + wire combo3_0100_1100; + wire combo3_0100_1101; + wire combo3_0100_1110; + wire combo3_0101_0000; + wire combo3_0101_0001; + wire combo3_0101_0010; + wire combo3_0101_0100; + wire combo3_0101_0101; + wire combo3_0101_0110; + wire combo3_0101_1000; + wire combo3_0101_1011; + wire combo3_0101_1111; + wire combo3_0110_0000; + wire combo3_0110_0010; + wire combo3_0110_0011; + wire combo3_0110_0110; + wire combo3_0110_0111; + wire combo3_0110_1000; + wire combo3_0110_1010; + wire combo3_0110_1011; + wire combo3_0110_1100; + wire combo3_0110_1101; + wire combo3_0111_0000; + wire combo3_0111_0001; + wire combo3_0111_0101; + wire combo3_0111_0110; + wire combo3_0111_1000; + wire combo3_0111_1001; + wire combo3_0111_1010; + wire combo3_0111_1011; + wire combo3_0111_1101; + wire combo3_0111_1111; + wire combo3_1000_0000; + wire combo3_1000_0001; + wire combo3_1000_0011; + wire combo3_1000_0100; + wire combo3_1000_0101; + wire combo3_1000_1010; + wire combo3_1000_1100; + wire combo3_1000_1101; + wire combo3_1001_0100; + wire combo3_1001_0110; + wire combo3_1001_0111; + wire combo3_1001_1000; + wire combo3_1001_1001; + wire combo3_1001_1010; + wire combo3_1001_1011; + wire combo3_1001_1111; + wire combo3_1010_0100; + wire combo3_1010_0110; + wire combo3_1010_1000; + wire combo3_1010_1001; + wire combo3_1010_1010; + wire combo3_1010_1011; + wire combo3_1010_1100; + wire combo3_1010_1101; + wire combo3_1011_0010; + wire combo3_1011_0011; + wire combo3_1011_0100; + wire combo3_1011_0101; + wire combo3_1011_0110; + wire combo3_1011_0111; + wire combo3_1100_0000; + wire combo3_1100_0001; + wire combo3_1100_0010; + wire combo3_1100_0011; + wire combo3_1100_0100; + wire combo3_1100_0111; + wire combo3_1100_1000; + wire combo3_1100_1001; + wire combo3_1100_1010; + wire combo3_1100_1101; + wire combo3_1100_1110; + wire combo3_1100_1111; + wire combo3_1101_0010; + wire combo3_1101_0011; + wire combo3_1101_0100; + wire combo3_1101_0101; + wire combo3_1101_0110; + wire combo3_1101_0111; + wire combo3_1101_1100; + wire combo3_1101_1101; + wire combo3_1101_1110; + wire combo3_1110_0000; + wire combo3_1110_0100; + wire combo3_1110_0101; + wire combo3_1110_0110; + wire combo3_1110_1000; + wire combo3_1110_1010; + wire combo3_1110_1101; + wire combo3_1111_0000; + wire combo3_1111_0001; + wire combo3_1111_0010; + wire combo3_1111_0100; + wire combo3_1111_1000; + wire combo3_1111_1001; + wire combo3_1111_1010; + wire combo3_1111_1100; + wire combo3_1111_1110; + wire [0:7] e_00_b; + wire [0:7] e_01_b; + wire [0:7] e_02_b; + wire [0:7] e_03_b; + wire [0:7] e_04_b; + wire [0:7] e_05_b; + wire [0:7] e_06_b; + wire [0:7] e_07_b; + wire [0:7] e_08_b; + wire [0:7] e_09_b; + wire [0:7] e_10_b; + wire [0:7] e_11_b; + wire [0:7] e_12_b; + wire [0:7] e_13_b; + wire [0:7] e_14_b; + wire [0:7] e_15_b; + wire [0:7] e_16_b; + wire [0:7] e_17_b; + wire [0:7] e_18_b; + wire [0:7] e_19_b; + wire [0:19] e; + wire [0:7] r_00_b; + wire [0:7] r_01_b; + wire [0:7] r_02_b; + wire [0:7] r_03_b; + wire [0:7] r_04_b; + wire [0:7] r_05_b; + wire [0:7] r_06_b; + wire [0:7] r_07_b; + wire [0:7] r_08_b; + wire [0:7] r_09_b; + wire [0:7] r_10_b; + wire [0:7] r_11_b; + wire [0:7] r_12_b; + wire [0:7] r_13_b; + wire [0:7] r_14_b; + wire [0:14] r; + + ////####################################### + ////## decode the upper 3 index bits + ////####################################### + + assign dcd_00x = (~f[1]) & (~f[2]); + assign dcd_01x = (~f[1]) & f[2]; + assign dcd_10x = f[1] & (~f[2]); + assign dcd_11x = f[1] & f[2]; + + assign dcd_000 = (~f[3]) & dcd_00x; + assign dcd_001 = f[3] & dcd_00x; + assign dcd_010 = (~f[3]) & dcd_01x; + assign dcd_011 = f[3] & dcd_01x; + assign dcd_100 = (~f[3]) & dcd_10x; + assign dcd_101 = f[3] & dcd_10x; + assign dcd_110 = (~f[3]) & dcd_11x; + assign dcd_111 = f[3] & dcd_11x; + + ////####################################### + ////## combos based on lower 2 index bits + ////####################################### + + assign combo2_1000 = (~f[5]) & (~f[6]); // [0] + assign combo2_0100 = (~f[5]) & f[6]; // [1] + assign combo2_1100 = (~f[5]); // [0,1] + assign combo2_0010 = f[5] & (~f[6]); // [2] + assign combo2_1010 = (~f[6]); // [0,2] + assign combo2_0110 = f[5] ^ f[6]; // [1,2] + assign combo2_1110 = (~(f[5] & f[6])); // [0,1,2] + assign combo2_0001 = f[5] & f[6]; // [3] + assign combo2_1001 = (~(f[5] ^ f[6])); // [0,3] + assign combo2_0101 = f[6]; // [1,3] + assign combo2_1101 = (~(f[5] & (~f[6]))); // [1,2,3] + assign combo2_0011 = f[5]; // [2,3] + assign combo2_1011 = (~((~f[5]) & f[6])); // [0,2,3] + assign combo2_0111 = (~((~f[5]) & (~f[6]))); // [1,2,3] + + ////####################################### + ////## combos based on lower 3 index bits + ////####################################### + + assign combo2_1000_xxxx_b = (~((~f[4]) & combo2_1000)); + assign combo2_0100_xxxx_b = (~((~f[4]) & combo2_0100)); + assign combo2_1100_xxxx_b = (~((~f[4]) & combo2_1100)); + assign combo2_0010_xxxx_b = (~((~f[4]) & combo2_0010)); + assign combo2_1010_xxxx_b = (~((~f[4]) & combo2_1010)); + assign combo2_0110_xxxx_b = (~((~f[4]) & combo2_0110)); + assign combo2_1110_xxxx_b = (~((~f[4]) & combo2_1110)); + assign combo2_0001_xxxx_b = (~((~f[4]) & combo2_0001)); + assign combo2_1001_xxxx_b = (~((~f[4]) & combo2_1001)); + assign combo2_0101_xxxx_b = (~((~f[4]) & combo2_0101)); + assign combo2_1101_xxxx_b = (~((~f[4]) & combo2_1101)); + assign combo2_0011_xxxx_b = (~((~f[4]) & combo2_0011)); + assign combo2_1011_xxxx_b = (~((~f[4]) & combo2_1011)); + assign combo2_0111_xxxx_b = (~((~f[4]) & combo2_0111)); + + assign combo2_xxxx_1000_b = (~(f[4] & combo2_1000)); + assign combo2_xxxx_0100_b = (~(f[4] & combo2_0100)); + assign combo2_xxxx_1100_b = (~(f[4] & combo2_1100)); + assign combo2_xxxx_0010_b = (~(f[4] & combo2_0010)); + assign combo2_xxxx_1010_b = (~(f[4] & combo2_1010)); + assign combo2_xxxx_0110_b = (~(f[4] & combo2_0110)); + assign combo2_xxxx_1110_b = (~(f[4] & combo2_1110)); + assign combo2_xxxx_0001_b = (~(f[4] & combo2_0001)); + assign combo2_xxxx_1001_b = (~(f[4] & combo2_1001)); + assign combo2_xxxx_0101_b = (~(f[4] & combo2_0101)); + assign combo2_xxxx_1101_b = (~(f[4] & combo2_1101)); + assign combo2_xxxx_0011_b = (~(f[4] & combo2_0011)); + assign combo2_xxxx_1011_b = (~(f[4] & combo2_1011)); + assign combo2_xxxx_0111_b = (~(f[4] & combo2_0111)); + + assign combo3_0000_0001 = (~(combo2_xxxx_0001_b)); //i=1, 2 1 + assign combo3_0000_0010 = (~(combo2_xxxx_0010_b)); //i=2, 1 2 + assign combo3_0000_0011 = (~(combo2_xxxx_0011_b)); //i=3, 3 3 + assign combo3_0000_0100 = (~(combo2_xxxx_0100_b)); //i=4, 1 4 + assign combo3_0000_0101 = (~(combo2_xxxx_0101_b)); //i=5, 2 5 + assign combo3_0000_0110 = (~(combo2_xxxx_0110_b)); //i=6, 2 6 + assign combo3_0000_1001 = (~(combo2_xxxx_1001_b)); //i=9, 1 7 + assign combo3_0000_1010 = (~(combo2_xxxx_1010_b)); //i=10, 2 8 + assign combo3_0000_1011 = (~(combo2_xxxx_1011_b)); //i=11, 2 9 + assign combo3_0000_1110 = (~(combo2_xxxx_1110_b)); //i=14, 1 10 + assign combo3_0000_1111 = (~((~f[4]))); //i=15, 2 11 + assign combo3_0001_0001 = (~((~combo2_0001))); //i=17, 2 12* + assign combo3_0001_0010 = (~(combo2_0001_xxxx_b & combo2_xxxx_0010_b)); //i=18, 1 13 + assign combo3_0001_0100 = (~(combo2_0001_xxxx_b & combo2_xxxx_0100_b)); //i=20, 1 14 + assign combo3_0001_0101 = (~(combo2_0001_xxxx_b & combo2_xxxx_0101_b)); //i=21, 1 15 + assign combo3_0001_0111 = (~(combo2_0001_xxxx_b & combo2_xxxx_0111_b)); //i=23, 1 16 + assign combo3_0001_1000 = (~(combo2_0001_xxxx_b & combo2_xxxx_1000_b)); //i=24, 3 17 + assign combo3_0001_1010 = (~(combo2_0001_xxxx_b & combo2_xxxx_1010_b)); //i=26, 1 18 + assign combo3_0001_1011 = (~(combo2_0001_xxxx_b & combo2_xxxx_1011_b)); //i=27, 1 19 + assign combo3_0001_1100 = (~(combo2_0001_xxxx_b & combo2_xxxx_1100_b)); //i=28, 1 20 + assign combo3_0001_1110 = (~(combo2_0001_xxxx_b & combo2_xxxx_1110_b)); //i=30, 1 21 + assign combo3_0001_1111 = (~(combo2_0001_xxxx_b & (~f[4]))); //i=31, 4 22 + assign combo3_0010_0000 = (~(combo2_0010_xxxx_b)); //i=32, 2 23 + assign combo3_0010_0100 = (~(combo2_0010_xxxx_b & combo2_xxxx_0100_b)); //i=36, 1 24 + assign combo3_0010_0101 = (~(combo2_0010_xxxx_b & combo2_xxxx_0101_b)); //i=37, 1 25 + assign combo3_0010_0110 = (~(combo2_0010_xxxx_b & combo2_xxxx_0110_b)); //i=38, 2 26 + assign combo3_0010_0111 = (~(combo2_0010_xxxx_b & combo2_xxxx_0111_b)); //i=39, 1 27 + assign combo3_0010_1000 = (~(combo2_0010_xxxx_b & combo2_xxxx_1000_b)); //i=40, 2 28 + assign combo3_0010_1001 = (~(combo2_0010_xxxx_b & combo2_xxxx_1001_b)); //i=41, 1 29 + assign combo3_0010_1101 = (~(combo2_0010_xxxx_b & combo2_xxxx_1101_b)); //i=45, 4 30 + assign combo3_0011_0000 = (~(combo2_0011_xxxx_b)); //i=48, 1 31 + assign combo3_0011_0001 = (~(combo2_0011_xxxx_b & combo2_xxxx_0001_b)); //i=49, 3 32 + assign combo3_0011_0011 = (~((~combo2_0011))); //i=51, 1 33* + assign combo3_0011_0101 = (~(combo2_0011_xxxx_b & combo2_xxxx_0101_b)); //i=53, 1 34 + assign combo3_0011_1000 = (~(combo2_0011_xxxx_b & combo2_xxxx_1000_b)); //i=56, 3 35 + assign combo3_0011_1001 = (~(combo2_0011_xxxx_b & combo2_xxxx_1001_b)); //i=57, 1 36 + assign combo3_0011_1010 = (~(combo2_0011_xxxx_b & combo2_xxxx_1010_b)); //i=58, 1 37 + assign combo3_0011_1011 = (~(combo2_0011_xxxx_b & combo2_xxxx_1011_b)); //i=59, 1 38 + assign combo3_0011_1100 = (~(combo2_0011_xxxx_b & combo2_xxxx_1100_b)); //i=60, 3 39 + assign combo3_0011_1110 = (~(combo2_0011_xxxx_b & combo2_xxxx_1110_b)); //i=62, 1 40 + assign combo3_0011_1111 = (~(combo2_0011_xxxx_b & (~f[4]))); //i=63, 4 41 + assign combo3_0100_0000 = (~(combo2_0100_xxxx_b)); //i=64, 1 42 + assign combo3_0100_0011 = (~(combo2_0100_xxxx_b & combo2_xxxx_0011_b)); //i=67, 2 43 + assign combo3_0100_0110 = (~(combo2_0100_xxxx_b & combo2_xxxx_0110_b)); //i=70, 1 44 + assign combo3_0100_1000 = (~(combo2_0100_xxxx_b & combo2_xxxx_1000_b)); //i=72, 2 45 + assign combo3_0100_1001 = (~(combo2_0100_xxxx_b & combo2_xxxx_1001_b)); //i=73, 2 46 + assign combo3_0100_1010 = (~(combo2_0100_xxxx_b & combo2_xxxx_1010_b)); //i=74, 2 47 + assign combo3_0100_1100 = (~(combo2_0100_xxxx_b & combo2_xxxx_1100_b)); //i=76, 1 48 + assign combo3_0100_1101 = (~(combo2_0100_xxxx_b & combo2_xxxx_1101_b)); //i=77, 1 49 + assign combo3_0100_1110 = (~(combo2_0100_xxxx_b & combo2_xxxx_1110_b)); //i=78, 1 50 + assign combo3_0101_0000 = (~(combo2_0101_xxxx_b)); //i=80, 3 51 + assign combo3_0101_0001 = (~(combo2_0101_xxxx_b & combo2_xxxx_0001_b)); //i=81, 1 52 + assign combo3_0101_0010 = (~(combo2_0101_xxxx_b & combo2_xxxx_0010_b)); //i=82, 1 53 + assign combo3_0101_0100 = (~(combo2_0101_xxxx_b & combo2_xxxx_0100_b)); //i=84, 3 54 + assign combo3_0101_0101 = (~((~combo2_0101))); //i=85, 1 55* + assign combo3_0101_0110 = (~(combo2_0101_xxxx_b & combo2_xxxx_0110_b)); //i=86, 1 56 + assign combo3_0101_1000 = (~(combo2_0101_xxxx_b & combo2_xxxx_1000_b)); //i=88, 1 57 + assign combo3_0101_1011 = (~(combo2_0101_xxxx_b & combo2_xxxx_1011_b)); //i=91, 3 58 + assign combo3_0101_1111 = (~(combo2_0101_xxxx_b & (~f[4]))); //i=95, 1 59 + assign combo3_0110_0000 = (~(combo2_0110_xxxx_b)); //i=96, 1 60 + assign combo3_0110_0010 = (~(combo2_0110_xxxx_b & combo2_xxxx_0010_b)); //i=98, 1 61 + assign combo3_0110_0011 = (~(combo2_0110_xxxx_b & combo2_xxxx_0011_b)); //i=99, 1 62 + assign combo3_0110_0110 = (~((~combo2_0110))); //i=102, 1 63* + assign combo3_0110_0111 = (~(combo2_0110_xxxx_b & combo2_xxxx_0111_b)); //i=103, 3 64 + assign combo3_0110_1000 = (~(combo2_0110_xxxx_b & combo2_xxxx_1000_b)); //i=104, 1 65 + assign combo3_0110_1010 = (~(combo2_0110_xxxx_b & combo2_xxxx_1010_b)); //i=106, 2 66 + assign combo3_0110_1011 = (~(combo2_0110_xxxx_b & combo2_xxxx_1011_b)); //i=107, 1 67 + assign combo3_0110_1100 = (~(combo2_0110_xxxx_b & combo2_xxxx_1100_b)); //i=108, 1 68 + assign combo3_0110_1101 = (~(combo2_0110_xxxx_b & combo2_xxxx_1101_b)); //i=109, 1 69 + assign combo3_0111_0000 = (~(combo2_0111_xxxx_b)); //i=112, 3 70 + assign combo3_0111_0001 = (~(combo2_0111_xxxx_b & combo2_xxxx_0001_b)); //i=113, 1 71 + assign combo3_0111_0101 = (~(combo2_0111_xxxx_b & combo2_xxxx_0101_b)); //i=117, 1 72 + assign combo3_0111_0110 = (~(combo2_0111_xxxx_b & combo2_xxxx_0110_b)); //i=118, 1 73 + assign combo3_0111_1000 = (~(combo2_0111_xxxx_b & combo2_xxxx_1000_b)); //i=120, 3 74 + assign combo3_0111_1001 = (~(combo2_0111_xxxx_b & combo2_xxxx_1001_b)); //i=121, 1 75 + assign combo3_0111_1010 = (~(combo2_0111_xxxx_b & combo2_xxxx_1010_b)); //i=122, 2 76 + assign combo3_0111_1011 = (~(combo2_0111_xxxx_b & combo2_xxxx_1011_b)); //i=123, 1 77 + assign combo3_0111_1101 = (~(combo2_0111_xxxx_b & combo2_xxxx_1101_b)); //i=125, 1 78 + assign combo3_0111_1111 = (~(combo2_0111_xxxx_b & (~f[4]))); //i=127, 3 79 + assign combo3_1000_0000 = (~(combo2_1000_xxxx_b)); //i=128, 7 80 + assign combo3_1000_0001 = (~(combo2_1000_xxxx_b & combo2_xxxx_0001_b)); //i=129, 1 81 + assign combo3_1000_0011 = (~(combo2_1000_xxxx_b & combo2_xxxx_0011_b)); //i=131, 1 82 + assign combo3_1000_0100 = (~(combo2_1000_xxxx_b & combo2_xxxx_0100_b)); //i=132, 2 83 + assign combo3_1000_0101 = (~(combo2_1000_xxxx_b & combo2_xxxx_0101_b)); //i=133, 1 84 + assign combo3_1000_1010 = (~(combo2_1000_xxxx_b & combo2_xxxx_1010_b)); //i=138, 1 85 + assign combo3_1000_1100 = (~(combo2_1000_xxxx_b & combo2_xxxx_1100_b)); //i=140, 1 86 + assign combo3_1000_1101 = (~(combo2_1000_xxxx_b & combo2_xxxx_1101_b)); //i=141, 1 87 + assign combo3_1001_0100 = (~(combo2_1001_xxxx_b & combo2_xxxx_0100_b)); //i=148, 1 88 + assign combo3_1001_0110 = (~(combo2_1001_xxxx_b & combo2_xxxx_0110_b)); //i=150, 3 89 + assign combo3_1001_0111 = (~(combo2_1001_xxxx_b & combo2_xxxx_0111_b)); //i=151, 1 90 + assign combo3_1001_1000 = (~(combo2_1001_xxxx_b & combo2_xxxx_1000_b)); //i=152, 1 91 + assign combo3_1001_1001 = (~((~combo2_1001))); //i=153, 3 92* + assign combo3_1001_1010 = (~(combo2_1001_xxxx_b & combo2_xxxx_1010_b)); //i=154, 1 93 + assign combo3_1001_1011 = (~(combo2_1001_xxxx_b & combo2_xxxx_1011_b)); //i=155, 1 94 + assign combo3_1001_1111 = (~(combo2_1001_xxxx_b & (~f[4]))); //i=159, 1 95 + assign combo3_1010_0100 = (~(combo2_1010_xxxx_b & combo2_xxxx_0100_b)); //i=164, 1 96 + assign combo3_1010_0110 = (~(combo2_1010_xxxx_b & combo2_xxxx_0110_b)); //i=166, 1 97 + assign combo3_1010_1000 = (~(combo2_1010_xxxx_b & combo2_xxxx_1000_b)); //i=168, 2 98 + assign combo3_1010_1001 = (~(combo2_1010_xxxx_b & combo2_xxxx_1001_b)); //i=169, 1 99 + assign combo3_1010_1010 = (~((~combo2_1010))); //i=170, 1 100* + assign combo3_1010_1011 = (~(combo2_1010_xxxx_b & combo2_xxxx_1011_b)); //i=171, 1 101 + assign combo3_1010_1100 = (~(combo2_1010_xxxx_b & combo2_xxxx_1100_b)); //i=172, 2 102 + assign combo3_1010_1101 = (~(combo2_1010_xxxx_b & combo2_xxxx_1101_b)); //i=173, 2 103 + assign combo3_1011_0010 = (~(combo2_1011_xxxx_b & combo2_xxxx_0010_b)); //i=178, 1 104 + assign combo3_1011_0011 = (~(combo2_1011_xxxx_b & combo2_xxxx_0011_b)); //i=179, 3 105 + assign combo3_1011_0100 = (~(combo2_1011_xxxx_b & combo2_xxxx_0100_b)); //i=180, 1 106 + assign combo3_1011_0101 = (~(combo2_1011_xxxx_b & combo2_xxxx_0101_b)); //i=181, 2 107 + assign combo3_1011_0110 = (~(combo2_1011_xxxx_b & combo2_xxxx_0110_b)); //i=182, 3 108 + assign combo3_1011_0111 = (~(combo2_1011_xxxx_b & combo2_xxxx_0111_b)); //i=183, 1 109 + assign combo3_1100_0000 = (~(combo2_1100_xxxx_b)); //i=192, 4 110 + assign combo3_1100_0001 = (~(combo2_1100_xxxx_b & combo2_xxxx_0001_b)); //i=193, 1 111 + assign combo3_1100_0010 = (~(combo2_1100_xxxx_b & combo2_xxxx_0010_b)); //i=194, 1 112 + assign combo3_1100_0011 = (~(combo2_1100_xxxx_b & combo2_xxxx_0011_b)); //i=195, 2 113 + assign combo3_1100_0100 = (~(combo2_1100_xxxx_b & combo2_xxxx_0100_b)); //i=196, 1 114 + assign combo3_1100_0111 = (~(combo2_1100_xxxx_b & combo2_xxxx_0111_b)); //i=199, 1 115 + assign combo3_1100_1000 = (~(combo2_1100_xxxx_b & combo2_xxxx_1000_b)); //i=200, 1 116 + assign combo3_1100_1001 = (~(combo2_1100_xxxx_b & combo2_xxxx_1001_b)); //i=201, 2 117 + assign combo3_1100_1010 = (~(combo2_1100_xxxx_b & combo2_xxxx_1010_b)); //i=202, 2 118 + assign combo3_1100_1101 = (~(combo2_1100_xxxx_b & combo2_xxxx_1101_b)); //i=205, 2 119 + assign combo3_1100_1110 = (~(combo2_1100_xxxx_b & combo2_xxxx_1110_b)); //i=206, 2 120 + assign combo3_1100_1111 = (~(combo2_1100_xxxx_b & (~f[4]))); //i=207, 2 121 + assign combo3_1101_0010 = (~(combo2_1101_xxxx_b & combo2_xxxx_0010_b)); //i=210, 1 122 + assign combo3_1101_0011 = (~(combo2_1101_xxxx_b & combo2_xxxx_0011_b)); //i=211, 1 123 + assign combo3_1101_0100 = (~(combo2_1101_xxxx_b & combo2_xxxx_0100_b)); //i=212, 2 124 + assign combo3_1101_0101 = (~(combo2_1101_xxxx_b & combo2_xxxx_0101_b)); //i=213, 1 125 + assign combo3_1101_0110 = (~(combo2_1101_xxxx_b & combo2_xxxx_0110_b)); //i=214, 2 126 + assign combo3_1101_0111 = (~(combo2_1101_xxxx_b & combo2_xxxx_0111_b)); //i=215, 1 127 + assign combo3_1101_1100 = (~(combo2_1101_xxxx_b & combo2_xxxx_1100_b)); //i=220, 1 128 + assign combo3_1101_1101 = (~((~combo2_1101))); //i=221, 1 129* + assign combo3_1101_1110 = (~(combo2_1101_xxxx_b & combo2_xxxx_1110_b)); //i=222, 1 130 + assign combo3_1110_0000 = (~(combo2_1110_xxxx_b)); //i=224, 2 131 + assign combo3_1110_0100 = (~(combo2_1110_xxxx_b & combo2_xxxx_0100_b)); //i=228, 2 132 + assign combo3_1110_0101 = (~(combo2_1110_xxxx_b & combo2_xxxx_0101_b)); //i=229, 1 133 + assign combo3_1110_0110 = (~(combo2_1110_xxxx_b & combo2_xxxx_0110_b)); //i=230, 1 134 + assign combo3_1110_1000 = (~(combo2_1110_xxxx_b & combo2_xxxx_1000_b)); //i=232, 1 135 + assign combo3_1110_1010 = (~(combo2_1110_xxxx_b & combo2_xxxx_1010_b)); //i=234, 1 136 + assign combo3_1110_1101 = (~(combo2_1110_xxxx_b & combo2_xxxx_1101_b)); //i=237, 2 137 + assign combo3_1111_0000 = (~(f[4])); //i=240, 2 138 + assign combo3_1111_0001 = (~(f[4] & combo2_xxxx_0001_b)); //i=241, 1 139 + assign combo3_1111_0010 = (~(f[4] & combo2_xxxx_0010_b)); //i=242, 1 140 + assign combo3_1111_0100 = (~(f[4] & combo2_xxxx_0100_b)); //i=244, 2 141 + assign combo3_1111_1000 = (~(f[4] & combo2_xxxx_1000_b)); //i=248, 1 142 + assign combo3_1111_1001 = (~(f[4] & combo2_xxxx_1001_b)); //i=249, 1 143 + assign combo3_1111_1010 = (~(f[4] & combo2_xxxx_1010_b)); //i=250, 1 144 + assign combo3_1111_1100 = (~(f[4] & combo2_xxxx_1100_b)); //i=252, 2 145 + assign combo3_1111_1110 = (~(f[4] & combo2_xxxx_1110_b)); //i=254, 2 146 + + ////####################################### + ////## ESTIMATE VECTORs + ////####################################### + + assign e_00_b[0] = (~(dcd_000 & tiup)); + assign e_00_b[1] = (~(dcd_001 & tiup)); + assign e_00_b[2] = (~(dcd_010 & combo3_1111_1100)); + assign e_00_b[3] = (~(dcd_011 & tidn)); + assign e_00_b[4] = (~(dcd_100 & tidn)); + assign e_00_b[5] = (~(dcd_101 & tidn)); + assign e_00_b[6] = (~(dcd_110 & tidn)); + assign e_00_b[7] = (~(dcd_111 & tidn)); + + assign e[0] = (~(e_00_b[0] & e_00_b[1] & e_00_b[2] & e_00_b[3] & e_00_b[4] & e_00_b[5] & e_00_b[6] & e_00_b[7])); + + assign e_01_b[0] = (~(dcd_000 & tiup)); + assign e_01_b[1] = (~(dcd_001 & combo3_1100_0000)); + assign e_01_b[2] = (~(dcd_010 & combo3_0000_0011)); + assign e_01_b[3] = (~(dcd_011 & tiup)); + assign e_01_b[4] = (~(dcd_100 & combo3_1111_1110)); + assign e_01_b[5] = (~(dcd_101 & tidn)); + assign e_01_b[6] = (~(dcd_110 & tidn)); + assign e_01_b[7] = (~(dcd_111 & tidn)); + + assign e[1] = (~(e_01_b[0] & e_01_b[1] & e_01_b[2] & e_01_b[3] & e_01_b[4] & e_01_b[5] & e_01_b[6] & e_01_b[7])); + + assign e_02_b[0] = (~(dcd_000 & combo3_1111_1000)); + assign e_02_b[1] = (~(dcd_001 & combo3_0011_1110)); + assign e_02_b[2] = (~(dcd_010 & combo3_0000_0011)); + assign e_02_b[3] = (~(dcd_011 & combo3_1111_1100)); + assign e_02_b[4] = (~(dcd_100 & combo3_0000_0001)); + assign e_02_b[5] = (~(dcd_101 & tiup)); + assign e_02_b[6] = (~(dcd_110 & combo3_1100_0000)); + assign e_02_b[7] = (~(dcd_111 & tidn)); + + assign e[2] = (~(e_02_b[0] & e_02_b[1] & e_02_b[2] & e_02_b[3] & e_02_b[4] & e_02_b[5] & e_02_b[6] & e_02_b[7])); + + assign e_03_b[0] = (~(dcd_000 & combo3_1110_0110)); + assign e_03_b[1] = (~(dcd_001 & combo3_0011_0001)); + assign e_03_b[2] = (~(dcd_010 & combo3_1100_0011)); + assign e_03_b[3] = (~(dcd_011 & combo3_1100_0011)); + assign e_03_b[4] = (~(dcd_100 & combo3_1100_0001)); + assign e_03_b[5] = (~(dcd_101 & combo3_1111_0000)); + assign e_03_b[6] = (~(dcd_110 & combo3_0011_1111)); + assign e_03_b[7] = (~(dcd_111 & combo3_1000_0000)); + + assign e[3] = (~(e_03_b[0] & e_03_b[1] & e_03_b[2] & e_03_b[3] & e_03_b[4] & e_03_b[5] & e_03_b[6] & e_03_b[7])); + + assign e_04_b[0] = (~(dcd_000 & combo3_1101_0101)); + assign e_04_b[1] = (~(dcd_001 & combo3_0010_1101)); + assign e_04_b[2] = (~(dcd_010 & combo3_1011_0011)); + assign e_04_b[3] = (~(dcd_011 & combo3_0011_0011)); + assign e_04_b[4] = (~(dcd_100 & combo3_0011_0001)); + assign e_04_b[5] = (~(dcd_101 & combo3_1100_1110)); + assign e_04_b[6] = (~(dcd_110 & combo3_0011_1100)); + assign e_04_b[7] = (~(dcd_111 & combo3_0111_1000)); + + assign e[4] = (~(e_04_b[0] & e_04_b[1] & e_04_b[2] & e_04_b[3] & e_04_b[4] & e_04_b[5] & e_04_b[6] & e_04_b[7])); + + assign e_05_b[0] = (~(dcd_000 & combo3_1000_0011)); + assign e_05_b[1] = (~(dcd_001 & combo3_1001_1011)); + assign e_05_b[2] = (~(dcd_010 & combo3_0110_1010)); + assign e_05_b[3] = (~(dcd_011 & combo3_1010_1010)); + assign e_05_b[4] = (~(dcd_100 & combo3_1010_1101)); + assign e_05_b[5] = (~(dcd_101 & combo3_0010_1101)); + assign e_05_b[6] = (~(dcd_110 & combo3_1011_0010)); + assign e_05_b[7] = (~(dcd_111 & combo3_0110_0110)); + + assign e[5] = (~(e_05_b[0] & e_05_b[1] & e_05_b[2] & e_05_b[3] & e_05_b[4] & e_05_b[5] & e_05_b[6] & e_05_b[7])); + + assign e_06_b[0] = (~(dcd_000 & combo3_1000_0100)); + assign e_06_b[1] = (~(dcd_001 & combo3_1010_1001)); + assign e_06_b[2] = (~(dcd_010 & combo3_0011_1000)); + assign e_06_b[3] = (~(dcd_011 & tidn)); + assign e_06_b[4] = (~(dcd_100 & combo3_0011_1001)); + assign e_06_b[5] = (~(dcd_101 & combo3_1001_1001)); + assign e_06_b[6] = (~(dcd_110 & combo3_0010_1001)); + assign e_06_b[7] = (~(dcd_111 & combo3_0101_0101)); + + assign e[6] = (~(e_06_b[0] & e_06_b[1] & e_06_b[2] & e_06_b[3] & e_06_b[4] & e_06_b[5] & e_06_b[6] & e_06_b[7])); + + assign e_07_b[0] = (~(dcd_000 & combo3_1001_1001)); + assign e_07_b[1] = (~(dcd_001 & combo3_1000_1100)); + assign e_07_b[2] = (~(dcd_010 & combo3_1010_0110)); + assign e_07_b[3] = (~(dcd_011 & tidn)); + assign e_07_b[4] = (~(dcd_100 & combo3_1100_1010)); + assign e_07_b[5] = (~(dcd_101 & combo3_1010_1011)); + assign e_07_b[6] = (~(dcd_110 & combo3_0110_0011)); + assign e_07_b[7] = (~(dcd_111 & combo3_1000_0000)); + + assign e[7] = (~(e_07_b[0] & e_07_b[1] & e_07_b[2] & e_07_b[3] & e_07_b[4] & e_07_b[5] & e_07_b[6] & e_07_b[7])); + + assign e_08_b[0] = (~(dcd_000 & combo3_1000_1101)); + assign e_08_b[1] = (~(dcd_001 & combo3_0111_0101)); + assign e_08_b[2] = (~(dcd_010 & combo3_1111_0001)); + assign e_08_b[3] = (~(dcd_011 & combo3_0000_0011)); + assign e_08_b[4] = (~(dcd_100 & combo3_0101_1000)); + assign e_08_b[5] = (~(dcd_101 & combo3_0000_0110)); + assign e_08_b[6] = (~(dcd_110 & combo3_1101_0010)); + assign e_08_b[7] = (~(dcd_111 & combo3_0110_0000)); + + assign e[8] = (~(e_08_b[0] & e_08_b[1] & e_08_b[2] & e_08_b[3] & e_08_b[4] & e_08_b[5] & e_08_b[6] & e_08_b[7])); + + assign e_09_b[0] = (~(dcd_000 & combo3_1010_1100)); + assign e_09_b[1] = (~(dcd_001 & combo3_0111_0001)); + assign e_09_b[2] = (~(dcd_010 & combo3_0001_0100)); + assign e_09_b[3] = (~(dcd_011 & combo3_1000_0101)); + assign e_09_b[4] = (~(dcd_100 & combo3_1111_0100)); + assign e_09_b[5] = (~(dcd_101 & combo3_0000_1010)); + assign e_09_b[6] = (~(dcd_110 & combo3_0111_1001)); + assign e_09_b[7] = (~(dcd_111 & combo3_0101_0000)); + + assign e[9] = (~(e_09_b[0] & e_09_b[1] & e_09_b[2] & e_09_b[3] & e_09_b[4] & e_09_b[5] & e_09_b[6] & e_09_b[7])); + + assign e_10_b[0] = (~(dcd_000 & combo3_1010_0100)); + assign e_10_b[1] = (~(dcd_001 & combo3_0001_1000)); + assign e_10_b[2] = (~(dcd_010 & combo3_0000_0101)); + assign e_10_b[3] = (~(dcd_011 & combo3_0100_1001)); + assign e_10_b[4] = (~(dcd_100 & combo3_0001_1110)); + assign e_10_b[5] = (~(dcd_101 & combo3_0001_1011)); + assign e_10_b[6] = (~(dcd_110 & combo3_0111_1010)); + assign e_10_b[7] = (~(dcd_111 & combo3_0001_1100)); + + assign e[10] = (~(e_10_b[0] & e_10_b[1] & e_10_b[2] & e_10_b[3] & e_10_b[4] & e_10_b[5] & e_10_b[6] & e_10_b[7])); + + assign e_11_b[0] = (~(dcd_000 & combo3_1110_1010)); + assign e_11_b[1] = (~(dcd_001 & combo3_1100_0010)); + assign e_11_b[2] = (~(dcd_010 & combo3_1010_1100)); + assign e_11_b[3] = (~(dcd_011 & combo3_1011_0110)); + assign e_11_b[4] = (~(dcd_100 & combo3_1011_0011)); + assign e_11_b[5] = (~(dcd_101 & combo3_0011_0101)); + assign e_11_b[6] = (~(dcd_110 & combo3_0100_1001)); + assign e_11_b[7] = (~(dcd_111 & combo3_0010_1000)); + + assign e[11] = (~(e_11_b[0] & e_11_b[1] & e_11_b[2] & e_11_b[3] & e_11_b[4] & e_11_b[5] & e_11_b[6] & e_11_b[7])); + + assign e_12_b[0] = (~(dcd_000 & combo3_1111_1010)); + assign e_12_b[1] = (~(dcd_001 & combo3_1110_0100)); + assign e_12_b[2] = (~(dcd_010 & combo3_0010_0100)); + assign e_12_b[3] = (~(dcd_011 & combo3_1100_1001)); + assign e_12_b[4] = (~(dcd_100 & combo3_0111_1111)); + assign e_12_b[5] = (~(dcd_101 & combo3_1111_0100)); + assign e_12_b[6] = (~(dcd_110 & combo3_1011_0111)); + assign e_12_b[7] = (~(dcd_111 & combo3_1100_1010)); + + assign e[12] = (~(e_12_b[0] & e_12_b[1] & e_12_b[2] & e_12_b[3] & e_12_b[4] & e_12_b[5] & e_12_b[6] & e_12_b[7])); + + assign e_13_b[0] = (~(dcd_000 & combo3_1001_1000)); + assign e_13_b[1] = (~(dcd_001 & combo3_0101_1011)); + assign e_13_b[2] = (~(dcd_010 & combo3_1101_1100)); + assign e_13_b[3] = (~(dcd_011 & combo3_0000_0110)); + assign e_13_b[4] = (~(dcd_100 & combo3_0100_0011)); + assign e_13_b[5] = (~(dcd_101 & combo3_1110_1000)); + assign e_13_b[6] = (~(dcd_110 & combo3_1111_1110)); + assign e_13_b[7] = (~(dcd_111 & combo3_1001_1010)); + + assign e[13] = (~(e_13_b[0] & e_13_b[1] & e_13_b[2] & e_13_b[3] & e_13_b[4] & e_13_b[5] & e_13_b[6] & e_13_b[7])); + + assign e_14_b[0] = (~(dcd_000 & combo3_0101_0100)); + assign e_14_b[1] = (~(dcd_001 & combo3_0010_0110)); + assign e_14_b[2] = (~(dcd_010 & combo3_0101_0000)); + assign e_14_b[3] = (~(dcd_011 & combo3_0111_0000)); + assign e_14_b[4] = (~(dcd_100 & combo3_0010_1101)); + assign e_14_b[5] = (~(dcd_101 & combo3_1101_0100)); + assign e_14_b[6] = (~(dcd_110 & combo3_1100_1000)); + assign e_14_b[7] = (~(dcd_111 & combo3_0110_1000)); + + assign e[14] = (~(e_14_b[0] & e_14_b[1] & e_14_b[2] & e_14_b[3] & e_14_b[4] & e_14_b[5] & e_14_b[6] & e_14_b[7])); + + assign e_15_b[0] = (~(dcd_000 & combo3_0101_1011)); + assign e_15_b[1] = (~(dcd_001 & combo3_0010_0000)); + assign e_15_b[2] = (~(dcd_010 & combo3_1101_0110)); + assign e_15_b[3] = (~(dcd_011 & combo3_1000_0001)); + assign e_15_b[4] = (~(dcd_100 & combo3_1001_0110)); + assign e_15_b[5] = (~(dcd_101 & combo3_1110_0101)); + assign e_15_b[6] = (~(dcd_110 & combo3_0100_1110)); + assign e_15_b[7] = (~(dcd_111 & combo3_1110_0000)); + + assign e[15] = (~(e_15_b[0] & e_15_b[1] & e_15_b[2] & e_15_b[3] & e_15_b[4] & e_15_b[5] & e_15_b[6] & e_15_b[7])); + + assign e_16_b[0] = (~(dcd_000 & combo3_0100_1000)); + assign e_16_b[1] = (~(dcd_001 & combo3_0010_0101)); + assign e_16_b[2] = (~(dcd_010 & combo3_1001_0111)); + assign e_16_b[3] = (~(dcd_011 & combo3_0011_1010)); + assign e_16_b[4] = (~(dcd_100 & combo3_0000_0101)); + assign e_16_b[5] = (~(dcd_101 & combo3_1110_0100)); + assign e_16_b[6] = (~(dcd_110 & combo3_0000_1111)); + assign e_16_b[7] = (~(dcd_111 & combo3_0000_0100)); + + assign e[16] = (~(e_16_b[0] & e_16_b[1] & e_16_b[2] & e_16_b[3] & e_16_b[4] & e_16_b[5] & e_16_b[6] & e_16_b[7])); + + assign e_17_b[0] = (~(dcd_000 & combo3_0000_1011)); + assign e_17_b[1] = (~(dcd_001 & combo3_1100_1111)); + assign e_17_b[2] = (~(dcd_010 & combo3_0000_1011)); + assign e_17_b[3] = (~(dcd_011 & combo3_0010_0000)); + assign e_17_b[4] = (~(dcd_100 & combo3_1101_0011)); + assign e_17_b[5] = (~(dcd_101 & combo3_0010_1000)); + assign e_17_b[6] = (~(dcd_110 & combo3_1111_0010)); + assign e_17_b[7] = (~(dcd_111 & combo3_0100_0110)); + + assign e[17] = (~(e_17_b[0] & e_17_b[1] & e_17_b[2] & e_17_b[3] & e_17_b[4] & e_17_b[5] & e_17_b[6] & e_17_b[7])); + + assign e_18_b[0] = (~(dcd_000 & combo3_0000_1001)); + assign e_18_b[1] = (~(dcd_001 & combo3_1100_1101)); + assign e_18_b[2] = (~(dcd_010 & combo3_0000_1010)); + assign e_18_b[3] = (~(dcd_011 & combo3_0000_0001)); + assign e_18_b[4] = (~(dcd_100 & combo3_0101_0000)); + assign e_18_b[5] = (~(dcd_101 & combo3_1001_0100)); + assign e_18_b[6] = (~(dcd_110 & combo3_0101_0010)); + assign e_18_b[7] = (~(dcd_111 & tidn)); + + assign e[18] = (~(e_18_b[0] & e_18_b[1] & e_18_b[2] & e_18_b[3] & e_18_b[4] & e_18_b[5] & e_18_b[6] & e_18_b[7])); + + assign e_19_b[0] = (~(dcd_000 & combo3_0111_1111)); + assign e_19_b[1] = (~(dcd_001 & tiup)); + assign e_19_b[2] = (~(dcd_010 & tiup)); + assign e_19_b[3] = (~(dcd_011 & tiup)); + assign e_19_b[4] = (~(dcd_100 & tiup)); + assign e_19_b[5] = (~(dcd_101 & tiup)); + assign e_19_b[6] = (~(dcd_110 & tiup)); + assign e_19_b[7] = (~(dcd_111 & tiup)); + + assign e[19] = (~(e_19_b[0] & e_19_b[1] & e_19_b[2] & e_19_b[3] & e_19_b[4] & e_19_b[5] & e_19_b[6] & e_19_b[7])); + + ////####################################### + ////## RANGE VECTORs + ////####################################### + + assign r_00_b[0] = (~(dcd_000 & tiup)); + assign r_00_b[1] = (~(dcd_001 & tiup)); + assign r_00_b[2] = (~(dcd_010 & tiup)); + assign r_00_b[3] = (~(dcd_011 & combo3_1110_0000)); + assign r_00_b[4] = (~(dcd_100 & tidn)); + assign r_00_b[5] = (~(dcd_101 & tidn)); + assign r_00_b[6] = (~(dcd_110 & tidn)); + assign r_00_b[7] = (~(dcd_111 & tidn)); + + assign r[0] = (~(r_00_b[0] & r_00_b[1] & r_00_b[2] & r_00_b[3] & r_00_b[4] & r_00_b[5] & r_00_b[6] & r_00_b[7])); + + assign r_01_b[0] = (~(dcd_000 & tiup)); + assign r_01_b[1] = (~(dcd_001 & combo3_1100_0000)); + assign r_01_b[2] = (~(dcd_010 & tidn)); + assign r_01_b[3] = (~(dcd_011 & combo3_0001_1111)); + assign r_01_b[4] = (~(dcd_100 & tiup)); + assign r_01_b[5] = (~(dcd_101 & tiup)); + assign r_01_b[6] = (~(dcd_110 & tiup)); + assign r_01_b[7] = (~(dcd_111 & tiup)); + + assign r[1] = (~(r_01_b[0] & r_01_b[1] & r_01_b[2] & r_01_b[3] & r_01_b[4] & r_01_b[5] & r_01_b[6] & r_01_b[7])); + + assign r_02_b[0] = (~(dcd_000 & combo3_1111_0000)); + assign r_02_b[1] = (~(dcd_001 & combo3_0011_1111)); + assign r_02_b[2] = (~(dcd_010 & combo3_1000_0000)); + assign r_02_b[3] = (~(dcd_011 & combo3_0001_1111)); + assign r_02_b[4] = (~(dcd_100 & tiup)); + assign r_02_b[5] = (~(dcd_101 & combo3_1000_0000)); + assign r_02_b[6] = (~(dcd_110 & tidn)); + assign r_02_b[7] = (~(dcd_111 & tidn)); + + assign r[2] = (~(r_02_b[0] & r_02_b[1] & r_02_b[2] & r_02_b[3] & r_02_b[4] & r_02_b[5] & r_02_b[6] & r_02_b[7])); + + assign r_03_b[0] = (~(dcd_000 & combo3_1100_1110)); + assign r_03_b[1] = (~(dcd_001 & combo3_0011_1000)); + assign r_03_b[2] = (~(dcd_010 & combo3_0111_1000)); + assign r_03_b[3] = (~(dcd_011 & combo3_0001_1111)); + assign r_03_b[4] = (~(dcd_100 & combo3_1000_0000)); + assign r_03_b[5] = (~(dcd_101 & combo3_0111_1111)); + assign r_03_b[6] = (~(dcd_110 & combo3_1100_0000)); + assign r_03_b[7] = (~(dcd_111 & tidn)); + + assign r[3] = (~(r_03_b[0] & r_03_b[1] & r_03_b[2] & r_03_b[3] & r_03_b[4] & r_03_b[5] & r_03_b[6] & r_03_b[7])); + + assign r_04_b[0] = (~(dcd_000 & combo3_1010_1101)); + assign r_04_b[1] = (~(dcd_001 & combo3_0010_0110)); + assign r_04_b[2] = (~(dcd_010 & combo3_0110_0111)); + assign r_04_b[3] = (~(dcd_011 & combo3_0001_1000)); + assign r_04_b[4] = (~(dcd_100 & combo3_0111_0000)); + assign r_04_b[5] = (~(dcd_101 & combo3_0111_1000)); + assign r_04_b[6] = (~(dcd_110 & combo3_0011_1111)); + assign r_04_b[7] = (~(dcd_111 & combo3_1000_0000)); + + assign r[4] = (~(r_04_b[0] & r_04_b[1] & r_04_b[2] & r_04_b[3] & r_04_b[4] & r_04_b[5] & r_04_b[6] & r_04_b[7])); + + assign r_05_b[0] = (~(dcd_000 & combo3_1111_1001)); + assign r_05_b[1] = (~(dcd_001 & combo3_1011_0101)); + assign r_05_b[2] = (~(dcd_010 & combo3_0101_0110)); + assign r_05_b[3] = (~(dcd_011 & combo3_1001_0110)); + assign r_05_b[4] = (~(dcd_100 & combo3_0110_1100)); + assign r_05_b[5] = (~(dcd_101 & combo3_0110_0111)); + assign r_05_b[6] = (~(dcd_110 & combo3_0011_1000)); + assign r_05_b[7] = (~(dcd_111 & combo3_0111_0000)); + + assign r[5] = (~(r_05_b[0] & r_05_b[1] & r_05_b[2] & r_05_b[3] & r_05_b[4] & r_05_b[5] & r_05_b[6] & r_05_b[7])); + + assign r_06_b[0] = (~(dcd_000 & combo3_0001_1010)); + assign r_06_b[1] = (~(dcd_001 & combo3_1101_1110)); + assign r_06_b[2] = (~(dcd_010 & combo3_0011_1100)); + assign r_06_b[3] = (~(dcd_011 & combo3_0100_1101)); + assign r_06_b[4] = (~(dcd_100 & combo3_0100_1010)); + assign r_06_b[5] = (~(dcd_101 & combo3_0101_0100)); + assign r_06_b[6] = (~(dcd_110 & combo3_1011_0110)); + assign r_06_b[7] = (~(dcd_111 & combo3_0100_1100)); + + assign r[6] = (~(r_06_b[0] & r_06_b[1] & r_06_b[2] & r_06_b[3] & r_06_b[4] & r_06_b[5] & r_06_b[6] & r_06_b[7])); + + assign r_07_b[0] = (~(dcd_000 & combo3_0010_1101)); + assign r_07_b[1] = (~(dcd_001 & combo3_1001_1001)); + assign r_07_b[2] = (~(dcd_010 & combo3_1100_0100)); + assign r_07_b[3] = (~(dcd_011 & combo3_1001_0110)); + assign r_07_b[4] = (~(dcd_100 & combo3_0001_1111)); + assign r_07_b[5] = (~(dcd_101 & combo3_0000_1110)); + assign r_07_b[6] = (~(dcd_110 & combo3_0110_1101)); + assign r_07_b[7] = (~(dcd_111 & combo3_0110_1010)); + + assign r[7] = (~(r_07_b[0] & r_07_b[1] & r_07_b[2] & r_07_b[3] & r_07_b[4] & r_07_b[5] & r_07_b[6] & r_07_b[7])); + + assign r_08_b[0] = (~(dcd_000 & combo3_0000_0010)); + assign r_08_b[1] = (~(dcd_001 & combo3_1011_0101)); + assign r_08_b[2] = (~(dcd_010 & combo3_1100_1001)); + assign r_08_b[3] = (~(dcd_011 & combo3_1100_1101)); + assign r_08_b[4] = (~(dcd_100 & combo3_1001_1111)); + assign r_08_b[5] = (~(dcd_101 & combo3_0001_0010)); + assign r_08_b[6] = (~(dcd_110 & combo3_1011_0110)); + assign r_08_b[7] = (~(dcd_111 & combo3_0011_1111)); + + assign r[8] = (~(r_08_b[0] & r_08_b[1] & r_08_b[2] & r_08_b[3] & r_08_b[4] & r_08_b[5] & r_08_b[6] & r_08_b[7])); + + assign r_09_b[0] = (~(dcd_000 & combo3_0100_1010)); + assign r_09_b[1] = (~(dcd_001 & combo3_0011_0001)); + assign r_09_b[2] = (~(dcd_010 & combo3_1101_1101)); + assign r_09_b[3] = (~(dcd_011 & combo3_1100_0111)); + assign r_09_b[4] = (~(dcd_100 & combo3_0101_1111)); + assign r_09_b[5] = (~(dcd_101 & combo3_0010_0111)); + assign r_09_b[6] = (~(dcd_110 & combo3_1110_1101)); + assign r_09_b[7] = (~(dcd_111 & combo3_0011_0000)); + + assign r[9] = (~(r_09_b[0] & r_09_b[1] & r_09_b[2] & r_09_b[3] & r_09_b[4] & r_09_b[5] & r_09_b[6] & r_09_b[7])); + + assign r_10_b[0] = (~(dcd_000 & combo3_0111_1010)); + assign r_10_b[1] = (~(dcd_001 & combo3_0011_1011)); + assign r_10_b[2] = (~(dcd_010 & combo3_0001_0111)); + assign r_10_b[3] = (~(dcd_011 & combo3_1101_0111)); + assign r_10_b[4] = (~(dcd_100 & combo3_0001_0001)); + assign r_10_b[5] = (~(dcd_101 & combo3_0111_0110)); + assign r_10_b[6] = (~(dcd_110 & combo3_0110_0111)); + assign r_10_b[7] = (~(dcd_111 & combo3_1010_1000)); + + assign r[10] = (~(r_10_b[0] & r_10_b[1] & r_10_b[2] & r_10_b[3] & r_10_b[4] & r_10_b[5] & r_10_b[6] & r_10_b[7])); + + assign r_11_b[0] = (~(dcd_000 & combo3_0000_1111)); + assign r_11_b[1] = (~(dcd_001 & combo3_0101_0100)); + assign r_11_b[2] = (~(dcd_010 & combo3_1110_1101)); + assign r_11_b[3] = (~(dcd_011 & combo3_0001_0101)); + assign r_11_b[4] = (~(dcd_100 & combo3_1010_1000)); + assign r_11_b[5] = (~(dcd_101 & combo3_0111_1101)); + assign r_11_b[6] = (~(dcd_110 & combo3_1011_0100)); + assign r_11_b[7] = (~(dcd_111 & combo3_1000_0100)); + + assign r[11] = (~(r_11_b[0] & r_11_b[1] & r_11_b[2] & r_11_b[3] & r_11_b[4] & r_11_b[5] & r_11_b[6] & r_11_b[7])); + + assign r_12_b[0] = (~(dcd_000 & combo3_1100_1111)); + assign r_12_b[1] = (~(dcd_001 & combo3_0110_1011)); + assign r_12_b[2] = (~(dcd_010 & combo3_0100_1000)); + assign r_12_b[3] = (~(dcd_011 & combo3_0111_1011)); + assign r_12_b[4] = (~(dcd_100 & combo3_1101_0110)); + assign r_12_b[5] = (~(dcd_101 & combo3_0001_0001)); + assign r_12_b[6] = (~(dcd_110 & combo3_1011_0011)); + assign r_12_b[7] = (~(dcd_111 & combo3_0100_0000)); + + assign r[12] = (~(r_12_b[0] & r_12_b[1] & r_12_b[2] & r_12_b[3] & r_12_b[4] & r_12_b[5] & r_12_b[6] & r_12_b[7])); + + assign r_13_b[0] = (~(dcd_000 & combo3_0101_0001)); + assign r_13_b[1] = (~(dcd_001 & combo3_0011_1100)); + assign r_13_b[2] = (~(dcd_010 & combo3_0101_1011)); + assign r_13_b[3] = (~(dcd_011 & combo3_0001_1000)); + assign r_13_b[4] = (~(dcd_100 & combo3_0110_0010)); + assign r_13_b[5] = (~(dcd_101 & combo3_1101_0100)); + assign r_13_b[6] = (~(dcd_110 & combo3_0100_0011)); + assign r_13_b[7] = (~(dcd_111 & combo3_1000_1010)); + + assign r[13] = (~(r_13_b[0] & r_13_b[1] & r_13_b[2] & r_13_b[3] & r_13_b[4] & r_13_b[5] & r_13_b[6] & r_13_b[7])); + + assign r_14_b[0] = (~(dcd_000 & combo3_1000_0000)); + assign r_14_b[1] = (~(dcd_001 & tidn)); + assign r_14_b[2] = (~(dcd_010 & tidn)); + assign r_14_b[3] = (~(dcd_011 & tidn)); + assign r_14_b[4] = (~(dcd_100 & tidn)); + assign r_14_b[5] = (~(dcd_101 & tidn)); + assign r_14_b[6] = (~(dcd_110 & tidn)); + assign r_14_b[7] = (~(dcd_111 & tidn)); + + assign r[14] = (~(r_14_b[0] & r_14_b[1] & r_14_b[2] & r_14_b[3] & r_14_b[4] & r_14_b[5] & r_14_b[6] & r_14_b[7])); + + ////####################################### + ////## RENUMBERING OUTPUTS + ////####################################### + + assign est[1:20] = e[0:19]; // renumbering + assign rng[6:20] = r[0:14]; // renumbering + +endmodule diff --git a/dev/verilog/work/fu_tblsqe.v b/dev/verilog/work/fu_tblsqe.v new file mode 100755 index 0000000..788cd3a --- /dev/null +++ b/dev/verilog/work/fu_tblsqe.v @@ -0,0 +1,952 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + + +// 01101010000001011111 010110010111010 0 +// 01100111001110100011 010101110110100 1 +// 01100100011111101101 010101010111010 2 +// 01100001110100110011 010100111001000 3 +// 01011111001101101011 010100011011110 4 +// 01011100101010001011 010011111111100 5 +// 01011010001010001101 010011100100100 6 +// 01010111101101101001 010011001010010 7 +// 01010101010100010101 010010110001000 8 +// 01010010111110001101 010010011000100 9 +// 01010000101011000111 010010000001000 10 +// 01001110011010111101 010001101010010 11 +// 01001100001101101011 010001010100000 12 +// 01001010000011001011 010000111110110 13 +// 01000111111011010101 010000101010000 14 +// 01000101110110000011 010000010110000 15 +// 01000011110011010011 010000000010100 16 +// 01000001110010111111 001111101111110 17 +// 00111111110101000001 001111011101010 18 +// 00111101111001010101 001111001011110 19 +// 00111011111111110111 001110111010100 20 +// 00111010001000100001 001110101001110 21 +// 00111000010011010011 001110011001100 22 +// 00110110100000000101 001110001001110 23 +// 00110100101110110111 001101111010100 24 +// 00110010111111100001 001101101011100 25 +// 00110001010010000011 001101011101000 26 +// 00101111100110011001 001101001111000 27 +// 00101101111100100001 001101000001010 28 +// 00101100010100010101 001100110100000 29 +// 00101010101101110101 001100100111000 30 +// 00101001001000111011 001100011010010 31 +// 00100111100101100111 001100001110000 32 +// 00100110000011110101 001100000010000 33 +// 00100100100011100101 001011110110010 34 +// 00100011000100110001 001011101011000 35 +// 00100001100111011001 001011011111110 36 +// 00100000001011011001 001011010101000 37 +// 00011110110000110001 001011001010100 38 +// 00011101010111011101 001011000000000 39 +// 00011011111111011011 001010110110000 40 +// 00011010101000101001 001010101100000 41 +// 00011001010011000111 001010100010100 42 +// 00010111111110110011 001010011001000 43 +// 00010110101011101001 001010010000000 44 +// 00010101011001101001 001010000111000 45 +// 00010100001000101111 001001111110010 46 +// 00010010111000111101 001001110101110 47 +// 00010001101010001111 001001101101010 48 +// 00010000011100100011 001001100101000 49 +// 00001111001111111011 001001011101000 50 +// 00001110000100010001 001001010101010 51 +// 00001100111001100111 001001001101100 52 +// 00001011101111111001 001001000110000 53 +// 00001010100111000111 001000111110110 54 +// 00001001011111010001 001000110111100 55 +// 00001000011000010101 001000110000100 56 +// 00000111010010010001 001000101001100 57 +// 00000110001101000011 001000100010110 58 +// 00000101001000101101 001000011100000 59 +// 00000100000101001011 001000010101100 60 +// 00000011000010011101 001000001111010 61 +// 00000010000000100001 001000001001000 62 +// 00000000111111011001 001000000011000 63 + + `include "tri_a2o.vh" + +module fu_tblsqe( + f, + est, + rng +); + input [1:6] f; + output [1:20] est; + output [6:20] rng; + + // end ports + + // ENTITY + + + parameter tiup = 1'b1; + parameter tidn = 1'b0; + + wire dcd_00x; + wire dcd_01x; + wire dcd_10x; + wire dcd_11x; + wire dcd_000; + wire dcd_001; + wire dcd_010; + wire dcd_011; + wire dcd_100; + wire dcd_101; + wire dcd_110; + wire dcd_111; + wire combo2_1000; + wire combo2_0100; + wire combo2_1100; + wire combo2_0010; + wire combo2_1010; + wire combo2_0110; + wire combo2_1110; + wire combo2_0001; + wire combo2_1001; + wire combo2_0101; + wire combo2_1101; + wire combo2_0011; + wire combo2_1011; + wire combo2_0111; + wire combo2_1000_xxxx_b; + wire combo2_0100_xxxx_b; + wire combo2_1100_xxxx_b; + wire combo2_0010_xxxx_b; + wire combo2_1010_xxxx_b; + wire combo2_0110_xxxx_b; + wire combo2_1110_xxxx_b; + wire combo2_0001_xxxx_b; + wire combo2_1001_xxxx_b; + wire combo2_0101_xxxx_b; + wire combo2_1101_xxxx_b; + wire combo2_0011_xxxx_b; + wire combo2_1011_xxxx_b; + wire combo2_0111_xxxx_b; + wire combo2_xxxx_1000_b; + wire combo2_xxxx_0100_b; + wire combo2_xxxx_1100_b; + wire combo2_xxxx_0010_b; + wire combo2_xxxx_1010_b; + wire combo2_xxxx_0110_b; + wire combo2_xxxx_1110_b; + wire combo2_xxxx_0001_b; + wire combo2_xxxx_1001_b; + wire combo2_xxxx_0101_b; + wire combo2_xxxx_1101_b; + wire combo2_xxxx_0011_b; + wire combo2_xxxx_1011_b; + wire combo2_xxxx_0111_b; + wire combo3_0000_0001; + wire combo3_0000_0011; + wire combo3_0000_0100; + wire combo3_0000_0111; + wire combo3_0000_1001; + wire combo3_0000_1010; + wire combo3_0000_1011; + wire combo3_0000_1101; + wire combo3_0000_1111; + wire combo3_0001_0001; + wire combo3_0001_0010; + wire combo3_0001_0100; + wire combo3_0001_0101; + wire combo3_0001_0111; + wire combo3_0001_1000; + wire combo3_0001_1100; + wire combo3_0001_1101; + wire combo3_0001_1110; + wire combo3_0001_1111; + wire combo3_0010_0001; + wire combo3_0010_0011; + wire combo3_0010_0100; + wire combo3_0010_0101; + wire combo3_0010_1000; + wire combo3_0010_1001; + wire combo3_0010_1010; + wire combo3_0010_1100; + wire combo3_0010_1101; + wire combo3_0010_1110; + wire combo3_0010_1111; + wire combo3_0011_0000; + wire combo3_0011_0001; + wire combo3_0011_0011; + wire combo3_0011_0101; + wire combo3_0011_0110; + wire combo3_0011_1000; + wire combo3_0011_1001; + wire combo3_0011_1110; + wire combo3_0011_1111; + wire combo3_0100_0000; + wire combo3_0100_0010; + wire combo3_0100_0100; + wire combo3_0100_0101; + wire combo3_0100_1001; + wire combo3_0100_1100; + wire combo3_0100_1110; + wire combo3_0100_1111; + wire combo3_0101_0010; + wire combo3_0101_0100; + wire combo3_0101_0110; + wire combo3_0101_1001; + wire combo3_0101_1100; + wire combo3_0101_1111; + wire combo3_0110_0000; + wire combo3_0110_0011; + wire combo3_0110_0110; + wire combo3_0110_0111; + wire combo3_0110_1100; + wire combo3_0110_1101; + wire combo3_0110_1111; + wire combo3_0111_0000; + wire combo3_0111_0101; + wire combo3_0111_0111; + wire combo3_0111_1000; + wire combo3_0111_1001; + wire combo3_0111_1010; + wire combo3_0111_1111; + wire combo3_1000_0000; + wire combo3_1000_0011; + wire combo3_1000_0110; + wire combo3_1000_0111; + wire combo3_1000_1010; + wire combo3_1000_1110; + wire combo3_1001_0000; + wire combo3_1001_0001; + wire combo3_1001_0010; + wire combo3_1001_0100; + wire combo3_1001_0110; + wire combo3_1001_0111; + wire combo3_1001_1000; + wire combo3_1001_1001; + wire combo3_1001_1010; + wire combo3_1001_1011; + wire combo3_1001_1100; + wire combo3_1010_0000; + wire combo3_1010_0001; + wire combo3_1010_0010; + wire combo3_1010_0100; + wire combo3_1010_0101; + wire combo3_1010_0110; + wire combo3_1010_0111; + wire combo3_1010_1001; + wire combo3_1010_1010; + wire combo3_1010_1100; + wire combo3_1010_1101; + wire combo3_1010_1111; + wire combo3_1011_0001; + wire combo3_1011_0010; + wire combo3_1011_0100; + wire combo3_1011_0101; + wire combo3_1011_1000; + wire combo3_1011_1010; + wire combo3_1011_1100; + wire combo3_1100_0000; + wire combo3_1100_0001; + wire combo3_1100_0011; + wire combo3_1100_0101; + wire combo3_1100_0110; + wire combo3_1100_0111; + wire combo3_1100_1001; + wire combo3_1100_1010; + wire combo3_1100_1011; + wire combo3_1100_1101; + wire combo3_1100_1111; + wire combo3_1101_0010; + wire combo3_1101_0011; + wire combo3_1101_1000; + wire combo3_1101_1001; + wire combo3_1101_1010; + wire combo3_1101_1100; + wire combo3_1101_1110; + wire combo3_1101_1111; + wire combo3_1110_0000; + wire combo3_1110_0001; + wire combo3_1110_0011; + wire combo3_1110_0110; + wire combo3_1110_1000; + wire combo3_1110_1010; + wire combo3_1110_1101; + wire combo3_1111_0000; + wire combo3_1111_0001; + wire combo3_1111_0010; + wire combo3_1111_1000; + wire combo3_1111_1001; + wire combo3_1111_1010; + wire combo3_1111_1100; + wire [0:7] e_00_b; + wire [0:7] e_01_b; + wire [0:7] e_02_b; + wire [0:7] e_03_b; + wire [0:7] e_04_b; + wire [0:7] e_05_b; + wire [0:7] e_06_b; + wire [0:7] e_07_b; + wire [0:7] e_08_b; + wire [0:7] e_09_b; + wire [0:7] e_10_b; + wire [0:7] e_11_b; + wire [0:7] e_12_b; + wire [0:7] e_13_b; + wire [0:7] e_14_b; + wire [0:7] e_15_b; + wire [0:7] e_16_b; + wire [0:7] e_17_b; + wire [0:7] e_18_b; + wire [0:7] e_19_b; + wire [0:19] e; + wire [0:7] r_00_b; + wire [0:7] r_01_b; + wire [0:7] r_02_b; + wire [0:7] r_03_b; + wire [0:7] r_04_b; + wire [0:7] r_05_b; + wire [0:7] r_06_b; + wire [0:7] r_07_b; + wire [0:7] r_08_b; + wire [0:7] r_09_b; + wire [0:7] r_10_b; + wire [0:7] r_11_b; + wire [0:7] r_12_b; + wire [0:7] r_13_b; + wire [0:7] r_14_b; + wire [0:14] r; + + ////####################################### + ////## decode the upper 3 index bits + ////####################################### + + assign dcd_00x = (~f[1]) & (~f[2]); + assign dcd_01x = (~f[1]) & f[2]; + assign dcd_10x = f[1] & (~f[2]); + assign dcd_11x = f[1] & f[2]; + + assign dcd_000 = (~f[3]) & dcd_00x; + assign dcd_001 = f[3] & dcd_00x; + assign dcd_010 = (~f[3]) & dcd_01x; + assign dcd_011 = f[3] & dcd_01x; + assign dcd_100 = (~f[3]) & dcd_10x; + assign dcd_101 = f[3] & dcd_10x; + assign dcd_110 = (~f[3]) & dcd_11x; + assign dcd_111 = f[3] & dcd_11x; + + ////####################################### + ////## combos based on lower 2 index bits + ////####################################### + + assign combo2_1000 = (~f[5]) & (~f[6]); // [0] + assign combo2_0100 = (~f[5]) & f[6]; // [1] + assign combo2_1100 = (~f[5]); // [0,1] + assign combo2_0010 = f[5] & (~f[6]); // [2] + assign combo2_1010 = (~f[6]); // [0,2] + assign combo2_0110 = f[5] ^ f[6]; // [1,2] + assign combo2_1110 = (~(f[5] & f[6])); // [0,1,2] + assign combo2_0001 = f[5] & f[6]; // [3] + assign combo2_1001 = (~(f[5] ^ f[6])); // [0,3] + assign combo2_0101 = f[6]; // [1,3] + assign combo2_1101 = (~(f[5] & (~f[6]))); // [1,2,3] + assign combo2_0011 = f[5]; // [2,3] + assign combo2_1011 = (~((~f[5]) & f[6])); // [0,2,3] + assign combo2_0111 = (~((~f[5]) & (~f[6]))); // [1,2,3] + + ////####################################### + ////## combos based on lower 3 index bits + ////####################################### + + assign combo2_1000_xxxx_b = (~((~f[4]) & combo2_1000)); + assign combo2_0100_xxxx_b = (~((~f[4]) & combo2_0100)); + assign combo2_1100_xxxx_b = (~((~f[4]) & combo2_1100)); + assign combo2_0010_xxxx_b = (~((~f[4]) & combo2_0010)); + assign combo2_1010_xxxx_b = (~((~f[4]) & combo2_1010)); + assign combo2_0110_xxxx_b = (~((~f[4]) & combo2_0110)); + assign combo2_1110_xxxx_b = (~((~f[4]) & combo2_1110)); + assign combo2_0001_xxxx_b = (~((~f[4]) & combo2_0001)); + assign combo2_1001_xxxx_b = (~((~f[4]) & combo2_1001)); + assign combo2_0101_xxxx_b = (~((~f[4]) & combo2_0101)); + assign combo2_1101_xxxx_b = (~((~f[4]) & combo2_1101)); + assign combo2_0011_xxxx_b = (~((~f[4]) & combo2_0011)); + assign combo2_1011_xxxx_b = (~((~f[4]) & combo2_1011)); + assign combo2_0111_xxxx_b = (~((~f[4]) & combo2_0111)); + + assign combo2_xxxx_1000_b = (~(f[4] & combo2_1000)); + assign combo2_xxxx_0100_b = (~(f[4] & combo2_0100)); + assign combo2_xxxx_1100_b = (~(f[4] & combo2_1100)); + assign combo2_xxxx_0010_b = (~(f[4] & combo2_0010)); + assign combo2_xxxx_1010_b = (~(f[4] & combo2_1010)); + assign combo2_xxxx_0110_b = (~(f[4] & combo2_0110)); + assign combo2_xxxx_1110_b = (~(f[4] & combo2_1110)); + assign combo2_xxxx_0001_b = (~(f[4] & combo2_0001)); + assign combo2_xxxx_1001_b = (~(f[4] & combo2_1001)); + assign combo2_xxxx_0101_b = (~(f[4] & combo2_0101)); + assign combo2_xxxx_1101_b = (~(f[4] & combo2_1101)); + assign combo2_xxxx_0011_b = (~(f[4] & combo2_0011)); + assign combo2_xxxx_1011_b = (~(f[4] & combo2_1011)); + assign combo2_xxxx_0111_b = (~(f[4] & combo2_0111)); + + assign combo3_0000_0001 = (~(combo2_xxxx_0001_b)); //i=1, 1 1 + assign combo3_0000_0011 = (~(combo2_xxxx_0011_b)); //i=3, 5 2 + assign combo3_0000_0100 = (~(combo2_xxxx_0100_b)); //i=4, 1 3 + assign combo3_0000_0111 = (~(combo2_xxxx_0111_b)); //i=7, 1 4 + assign combo3_0000_1001 = (~(combo2_xxxx_1001_b)); //i=9, 1 5 + assign combo3_0000_1010 = (~(combo2_xxxx_1010_b)); //i=10, 1 6 + assign combo3_0000_1011 = (~(combo2_xxxx_1011_b)); //i=11, 1 7 + assign combo3_0000_1101 = (~(combo2_xxxx_1101_b)); //i=13, 2 8 + assign combo3_0000_1111 = (~((~f[4]))); //i=15, 1 9 + assign combo3_0001_0001 = (~((~combo2_0001))); //i=17, 1 10* + assign combo3_0001_0010 = (~(combo2_0001_xxxx_b & combo2_xxxx_0010_b)); //i=18, 1 11 + assign combo3_0001_0100 = (~(combo2_0001_xxxx_b & combo2_xxxx_0100_b)); //i=20, 1 12 + assign combo3_0001_0101 = (~(combo2_0001_xxxx_b & combo2_xxxx_0101_b)); //i=21, 2 13 + assign combo3_0001_0111 = (~(combo2_0001_xxxx_b & combo2_xxxx_0111_b)); //i=23, 1 14 + assign combo3_0001_1000 = (~(combo2_0001_xxxx_b & combo2_xxxx_1000_b)); //i=24, 2 15 + assign combo3_0001_1100 = (~(combo2_0001_xxxx_b & combo2_xxxx_1100_b)); //i=28, 4 16 + assign combo3_0001_1101 = (~(combo2_0001_xxxx_b & combo2_xxxx_1101_b)); //i=29, 2 17 + assign combo3_0001_1110 = (~(combo2_0001_xxxx_b & combo2_xxxx_1110_b)); //i=30, 1 18 + assign combo3_0001_1111 = (~(combo2_0001_xxxx_b & (~f[4]))); //i=31, 1 19 + assign combo3_0010_0001 = (~(combo2_0010_xxxx_b & combo2_xxxx_0001_b)); //i=33, 1 20 + assign combo3_0010_0011 = (~(combo2_0010_xxxx_b & combo2_xxxx_0011_b)); //i=35, 1 21 + assign combo3_0010_0100 = (~(combo2_0010_xxxx_b & combo2_xxxx_0100_b)); //i=36, 1 22 + assign combo3_0010_0101 = (~(combo2_0010_xxxx_b & combo2_xxxx_0101_b)); //i=37, 1 23 + assign combo3_0010_1000 = (~(combo2_0010_xxxx_b & combo2_xxxx_1000_b)); //i=40, 3 24 + assign combo3_0010_1001 = (~(combo2_0010_xxxx_b & combo2_xxxx_1001_b)); //i=41, 2 25 + assign combo3_0010_1010 = (~(combo2_0010_xxxx_b & combo2_xxxx_1010_b)); //i=42, 1 26 + assign combo3_0010_1100 = (~(combo2_0010_xxxx_b & combo2_xxxx_1100_b)); //i=44, 1 27 + assign combo3_0010_1101 = (~(combo2_0010_xxxx_b & combo2_xxxx_1101_b)); //i=45, 1 28 + assign combo3_0010_1110 = (~(combo2_0010_xxxx_b & combo2_xxxx_1110_b)); //i=46, 1 29 + assign combo3_0010_1111 = (~(combo2_0010_xxxx_b & (~f[4]))); //i=47, 1 30 + assign combo3_0011_0000 = (~(combo2_0011_xxxx_b)); //i=48, 2 31 + assign combo3_0011_0001 = (~(combo2_0011_xxxx_b & combo2_xxxx_0001_b)); //i=49, 1 32 + assign combo3_0011_0011 = (~((~combo2_0011))); //i=51, 1 33* + assign combo3_0011_0101 = (~(combo2_0011_xxxx_b & combo2_xxxx_0101_b)); //i=53, 1 34 + assign combo3_0011_0110 = (~(combo2_0011_xxxx_b & combo2_xxxx_0110_b)); //i=54, 2 35 + assign combo3_0011_1000 = (~(combo2_0011_xxxx_b & combo2_xxxx_1000_b)); //i=56, 1 36 + assign combo3_0011_1001 = (~(combo2_0011_xxxx_b & combo2_xxxx_1001_b)); //i=57, 1 37 + assign combo3_0011_1110 = (~(combo2_0011_xxxx_b & combo2_xxxx_1110_b)); //i=62, 1 38 + assign combo3_0011_1111 = (~(combo2_0011_xxxx_b & (~f[4]))); //i=63, 5 39 + assign combo3_0100_0000 = (~(combo2_0100_xxxx_b)); //i=64, 1 40 + assign combo3_0100_0010 = (~(combo2_0100_xxxx_b & combo2_xxxx_0010_b)); //i=66, 1 41 + assign combo3_0100_0100 = (~((~combo2_0100))); //i=68, 1 42* + assign combo3_0100_0101 = (~(combo2_0100_xxxx_b & combo2_xxxx_0101_b)); //i=69, 1 43 + assign combo3_0100_1001 = (~(combo2_0100_xxxx_b & combo2_xxxx_1001_b)); //i=73, 1 44 + assign combo3_0100_1100 = (~(combo2_0100_xxxx_b & combo2_xxxx_1100_b)); //i=76, 2 45 + assign combo3_0100_1110 = (~(combo2_0100_xxxx_b & combo2_xxxx_1110_b)); //i=78, 1 46 + assign combo3_0100_1111 = (~(combo2_0100_xxxx_b & (~f[4]))); //i=79, 1 47 + assign combo3_0101_0010 = (~(combo2_0101_xxxx_b & combo2_xxxx_0010_b)); //i=82, 2 48 + assign combo3_0101_0100 = (~(combo2_0101_xxxx_b & combo2_xxxx_0100_b)); //i=84, 1 49 + assign combo3_0101_0110 = (~(combo2_0101_xxxx_b & combo2_xxxx_0110_b)); //i=86, 4 50 + assign combo3_0101_1001 = (~(combo2_0101_xxxx_b & combo2_xxxx_1001_b)); //i=89, 2 51 + assign combo3_0101_1100 = (~(combo2_0101_xxxx_b & combo2_xxxx_1100_b)); //i=92, 1 52 + assign combo3_0101_1111 = (~(combo2_0101_xxxx_b & (~f[4]))); //i=95, 2 53 + assign combo3_0110_0000 = (~(combo2_0110_xxxx_b)); //i=96, 1 54 + assign combo3_0110_0011 = (~(combo2_0110_xxxx_b & combo2_xxxx_0011_b)); //i=99, 1 55 + assign combo3_0110_0110 = (~((~combo2_0110))); //i=102, 2 56* + assign combo3_0110_0111 = (~(combo2_0110_xxxx_b & combo2_xxxx_0111_b)); //i=103, 1 57 + assign combo3_0110_1100 = (~(combo2_0110_xxxx_b & combo2_xxxx_1100_b)); //i=108, 2 58 + assign combo3_0110_1101 = (~(combo2_0110_xxxx_b & combo2_xxxx_1101_b)); //i=109, 2 59 + assign combo3_0110_1111 = (~(combo2_0110_xxxx_b & (~f[4]))); //i=111, 1 60 + assign combo3_0111_0000 = (~(combo2_0111_xxxx_b)); //i=112, 1 61 + assign combo3_0111_0101 = (~(combo2_0111_xxxx_b & combo2_xxxx_0101_b)); //i=117, 1 62 + assign combo3_0111_0111 = (~((~combo2_0111))); //i=119, 3 63* + assign combo3_0111_1000 = (~(combo2_0111_xxxx_b & combo2_xxxx_1000_b)); //i=120, 1 64 + assign combo3_0111_1001 = (~(combo2_0111_xxxx_b & combo2_xxxx_1001_b)); //i=121, 2 65 + assign combo3_0111_1010 = (~(combo2_0111_xxxx_b & combo2_xxxx_1010_b)); //i=122, 2 66 + assign combo3_0111_1111 = (~(combo2_0111_xxxx_b & (~f[4]))); //i=127, 4 67 + assign combo3_1000_0000 = (~(combo2_1000_xxxx_b)); //i=128, 3 68 + assign combo3_1000_0011 = (~(combo2_1000_xxxx_b & combo2_xxxx_0011_b)); //i=131, 1 69 + assign combo3_1000_0110 = (~(combo2_1000_xxxx_b & combo2_xxxx_0110_b)); //i=134, 1 70 + assign combo3_1000_0111 = (~(combo2_1000_xxxx_b & combo2_xxxx_0111_b)); //i=135, 1 71 + assign combo3_1000_1010 = (~(combo2_1000_xxxx_b & combo2_xxxx_1010_b)); //i=138, 1 72 + assign combo3_1000_1110 = (~(combo2_1000_xxxx_b & combo2_xxxx_1110_b)); //i=142, 2 73 + assign combo3_1001_0000 = (~(combo2_1001_xxxx_b)); //i=144, 2 74 + assign combo3_1001_0001 = (~(combo2_1001_xxxx_b & combo2_xxxx_0001_b)); //i=145, 1 75 + assign combo3_1001_0010 = (~(combo2_1001_xxxx_b & combo2_xxxx_0010_b)); //i=146, 2 76 + assign combo3_1001_0100 = (~(combo2_1001_xxxx_b & combo2_xxxx_0100_b)); //i=148, 1 77 + assign combo3_1001_0110 = (~(combo2_1001_xxxx_b & combo2_xxxx_0110_b)); //i=150, 1 78 + assign combo3_1001_0111 = (~(combo2_1001_xxxx_b & combo2_xxxx_0111_b)); //i=151, 1 79 + assign combo3_1001_1000 = (~(combo2_1001_xxxx_b & combo2_xxxx_1000_b)); //i=152, 1 80 + assign combo3_1001_1001 = (~((~combo2_1001))); //i=153, 2 81* + assign combo3_1001_1010 = (~(combo2_1001_xxxx_b & combo2_xxxx_1010_b)); //i=154, 1 82 + assign combo3_1001_1011 = (~(combo2_1001_xxxx_b & combo2_xxxx_1011_b)); //i=155, 2 83 + assign combo3_1001_1100 = (~(combo2_1001_xxxx_b & combo2_xxxx_1100_b)); //i=156, 1 84 + assign combo3_1010_0000 = (~(combo2_1010_xxxx_b)); //i=160, 1 85 + assign combo3_1010_0001 = (~(combo2_1010_xxxx_b & combo2_xxxx_0001_b)); //i=161, 1 86 + assign combo3_1010_0010 = (~(combo2_1010_xxxx_b & combo2_xxxx_0010_b)); //i=162, 1 87 + assign combo3_1010_0100 = (~(combo2_1010_xxxx_b & combo2_xxxx_0100_b)); //i=164, 1 88 + assign combo3_1010_0101 = (~(combo2_1010_xxxx_b & combo2_xxxx_0101_b)); //i=165, 2 89 + assign combo3_1010_0110 = (~(combo2_1010_xxxx_b & combo2_xxxx_0110_b)); //i=166, 1 90 + assign combo3_1010_0111 = (~(combo2_1010_xxxx_b & combo2_xxxx_0111_b)); //i=167, 1 91 + assign combo3_1010_1001 = (~(combo2_1010_xxxx_b & combo2_xxxx_1001_b)); //i=169, 2 92 + assign combo3_1010_1010 = (~((~combo2_1010))); //i=170, 2 93* + assign combo3_1010_1100 = (~(combo2_1010_xxxx_b & combo2_xxxx_1100_b)); //i=172, 2 94 + assign combo3_1010_1101 = (~(combo2_1010_xxxx_b & combo2_xxxx_1101_b)); //i=173, 1 95 + assign combo3_1010_1111 = (~(combo2_1010_xxxx_b & (~f[4]))); //i=175, 1 96 + assign combo3_1011_0001 = (~(combo2_1011_xxxx_b & combo2_xxxx_0001_b)); //i=177, 1 97 + assign combo3_1011_0010 = (~(combo2_1011_xxxx_b & combo2_xxxx_0010_b)); //i=178, 1 98 + assign combo3_1011_0100 = (~(combo2_1011_xxxx_b & combo2_xxxx_0100_b)); //i=180, 1 99 + assign combo3_1011_0101 = (~(combo2_1011_xxxx_b & combo2_xxxx_0101_b)); //i=181, 1 100 + assign combo3_1011_1000 = (~(combo2_1011_xxxx_b & combo2_xxxx_1000_b)); //i=184, 1 101 + assign combo3_1011_1010 = (~(combo2_1011_xxxx_b & combo2_xxxx_1010_b)); //i=186, 1 102 + assign combo3_1011_1100 = (~(combo2_1011_xxxx_b & combo2_xxxx_1100_b)); //i=188, 1 103 + assign combo3_1100_0000 = (~(combo2_1100_xxxx_b)); //i=192, 4 104 + assign combo3_1100_0001 = (~(combo2_1100_xxxx_b & combo2_xxxx_0001_b)); //i=193, 1 105 + assign combo3_1100_0011 = (~(combo2_1100_xxxx_b & combo2_xxxx_0011_b)); //i=195, 1 106 + assign combo3_1100_0101 = (~(combo2_1100_xxxx_b & combo2_xxxx_0101_b)); //i=197, 1 107 + assign combo3_1100_0110 = (~(combo2_1100_xxxx_b & combo2_xxxx_0110_b)); //i=198, 1 108 + assign combo3_1100_0111 = (~(combo2_1100_xxxx_b & combo2_xxxx_0111_b)); //i=199, 1 109 + assign combo3_1100_1001 = (~(combo2_1100_xxxx_b & combo2_xxxx_1001_b)); //i=201, 1 110 + assign combo3_1100_1010 = (~(combo2_1100_xxxx_b & combo2_xxxx_1010_b)); //i=202, 2 111 + assign combo3_1100_1011 = (~(combo2_1100_xxxx_b & combo2_xxxx_1011_b)); //i=203, 3 112 + assign combo3_1100_1101 = (~(combo2_1100_xxxx_b & combo2_xxxx_1101_b)); //i=205, 1 113 + assign combo3_1100_1111 = (~(combo2_1100_xxxx_b & (~f[4]))); //i=207, 1 114 + assign combo3_1101_0010 = (~(combo2_1101_xxxx_b & combo2_xxxx_0010_b)); //i=210, 1 115 + assign combo3_1101_0011 = (~(combo2_1101_xxxx_b & combo2_xxxx_0011_b)); //i=211, 2 116 + assign combo3_1101_1000 = (~(combo2_1101_xxxx_b & combo2_xxxx_1000_b)); //i=216, 1 117 + assign combo3_1101_1001 = (~(combo2_1101_xxxx_b & combo2_xxxx_1001_b)); //i=217, 2 118 + assign combo3_1101_1010 = (~(combo2_1101_xxxx_b & combo2_xxxx_1010_b)); //i=218, 2 119 + assign combo3_1101_1100 = (~(combo2_1101_xxxx_b & combo2_xxxx_1100_b)); //i=220, 1 120 + assign combo3_1101_1110 = (~(combo2_1101_xxxx_b & combo2_xxxx_1110_b)); //i=222, 1 121 + assign combo3_1101_1111 = (~(combo2_1101_xxxx_b & (~f[4]))); //i=223, 2 122 + assign combo3_1110_0000 = (~(combo2_1110_xxxx_b)); //i=224, 5 123 + assign combo3_1110_0001 = (~(combo2_1110_xxxx_b & combo2_xxxx_0001_b)); //i=225, 1 124 + assign combo3_1110_0011 = (~(combo2_1110_xxxx_b & combo2_xxxx_0011_b)); //i=227, 2 125 + assign combo3_1110_0110 = (~(combo2_1110_xxxx_b & combo2_xxxx_0110_b)); //i=230, 1 126 + assign combo3_1110_1000 = (~(combo2_1110_xxxx_b & combo2_xxxx_1000_b)); //i=232, 1 127 + assign combo3_1110_1010 = (~(combo2_1110_xxxx_b & combo2_xxxx_1010_b)); //i=234, 1 128 + assign combo3_1110_1101 = (~(combo2_1110_xxxx_b & combo2_xxxx_1101_b)); //i=237, 3 129 + assign combo3_1111_0000 = (~(f[4])); //i=240, 2 130 + assign combo3_1111_0001 = (~(f[4] & combo2_xxxx_0001_b)); //i=241, 1 131 + assign combo3_1111_0010 = (~(f[4] & combo2_xxxx_0010_b)); //i=242, 2 132 + assign combo3_1111_1000 = (~(f[4] & combo2_xxxx_1000_b)); //i=248, 3 133 + assign combo3_1111_1001 = (~(f[4] & combo2_xxxx_1001_b)); //i=249, 2 134 + assign combo3_1111_1010 = (~(f[4] & combo2_xxxx_1010_b)); //i=250, 2 135 + assign combo3_1111_1100 = (~(f[4] & combo2_xxxx_1100_b)); //i=252, 4 136 + + ////####################################### + ////## ESTIMATE VECTORs + ////####################################### + + assign e_00_b[0] = (~(dcd_000 & tidn)); + assign e_00_b[1] = (~(dcd_001 & tidn)); + assign e_00_b[2] = (~(dcd_010 & tidn)); + assign e_00_b[3] = (~(dcd_011 & tidn)); + assign e_00_b[4] = (~(dcd_100 & tidn)); + assign e_00_b[5] = (~(dcd_101 & tidn)); + assign e_00_b[6] = (~(dcd_110 & tidn)); + assign e_00_b[7] = (~(dcd_111 & tidn)); + + assign e[0] = (~(e_00_b[0] & e_00_b[1] & e_00_b[2] & e_00_b[3] & e_00_b[4] & e_00_b[5] & e_00_b[6] & e_00_b[7])); + + assign e_01_b[0] = (~(dcd_000 & tiup)); + assign e_01_b[1] = (~(dcd_001 & tiup)); + assign e_01_b[2] = (~(dcd_010 & combo3_1100_0000)); + assign e_01_b[3] = (~(dcd_011 & tidn)); + assign e_01_b[4] = (~(dcd_100 & tidn)); + assign e_01_b[5] = (~(dcd_101 & tidn)); + assign e_01_b[6] = (~(dcd_110 & tidn)); + assign e_01_b[7] = (~(dcd_111 & tidn)); + + assign e[1] = (~(e_01_b[0] & e_01_b[1] & e_01_b[2] & e_01_b[3] & e_01_b[4] & e_01_b[5] & e_01_b[6] & e_01_b[7])); + + assign e_02_b[0] = (~(dcd_000 & combo3_1111_0000)); + assign e_02_b[1] = (~(dcd_001 & tidn)); + assign e_02_b[2] = (~(dcd_010 & combo3_0011_1111)); + assign e_02_b[3] = (~(dcd_011 & tiup)); + assign e_02_b[4] = (~(dcd_100 & combo3_1111_1100)); + assign e_02_b[5] = (~(dcd_101 & tidn)); + assign e_02_b[6] = (~(dcd_110 & tidn)); + assign e_02_b[7] = (~(dcd_111 & tidn)); + + assign e[2] = (~(e_02_b[0] & e_02_b[1] & e_02_b[2] & e_02_b[3] & e_02_b[4] & e_02_b[5] & e_02_b[6] & e_02_b[7])); + + assign e_03_b[0] = (~(dcd_000 & combo3_0000_1111)); + assign e_03_b[1] = (~(dcd_001 & combo3_1110_0000)); + assign e_03_b[2] = (~(dcd_010 & combo3_0011_1111)); + assign e_03_b[3] = (~(dcd_011 & combo3_1110_0000)); + assign e_03_b[4] = (~(dcd_100 & combo3_0000_0011)); + assign e_03_b[5] = (~(dcd_101 & tiup)); + assign e_03_b[6] = (~(dcd_110 & combo3_1100_0000)); + assign e_03_b[7] = (~(dcd_111 & tidn)); + + assign e[3] = (~(e_03_b[0] & e_03_b[1] & e_03_b[2] & e_03_b[3] & e_03_b[4] & e_03_b[5] & e_03_b[6] & e_03_b[7])); + + assign e_04_b[0] = (~(dcd_000 & combo3_1000_1110)); + assign e_04_b[1] = (~(dcd_001 & combo3_0001_1100)); + assign e_04_b[2] = (~(dcd_010 & combo3_0011_1110)); + assign e_04_b[3] = (~(dcd_011 & combo3_0001_1111)); + assign e_04_b[4] = (~(dcd_100 & combo3_0000_0011)); + assign e_04_b[5] = (~(dcd_101 & combo3_1110_0000)); + assign e_04_b[6] = (~(dcd_110 & combo3_0011_1111)); + assign e_04_b[7] = (~(dcd_111 & combo3_1000_0000)); + + assign e[4] = (~(e_04_b[0] & e_04_b[1] & e_04_b[2] & e_04_b[3] & e_04_b[4] & e_04_b[5] & e_04_b[6] & e_04_b[7])); + + assign e_05_b[0] = (~(dcd_000 & combo3_0110_1101)); + assign e_05_b[1] = (~(dcd_001 & combo3_1001_1011)); + assign e_05_b[2] = (~(dcd_010 & combo3_0011_0001)); + assign e_05_b[3] = (~(dcd_011 & combo3_1001_1100)); + assign e_05_b[4] = (~(dcd_100 & combo3_1110_0011)); + assign e_05_b[5] = (~(dcd_101 & combo3_0001_1110)); + assign e_05_b[6] = (~(dcd_110 & combo3_0011_1000)); + assign e_05_b[7] = (~(dcd_111 & combo3_0111_1000)); + + assign e[5] = (~(e_05_b[0] & e_05_b[1] & e_05_b[2] & e_05_b[3] & e_05_b[4] & e_05_b[5] & e_05_b[6] & e_05_b[7])); + + assign e_06_b[0] = (~(dcd_000 & combo3_1100_1011)); + assign e_06_b[1] = (~(dcd_001 & combo3_0101_0110)); + assign e_06_b[2] = (~(dcd_010 & combo3_1010_1101)); + assign e_06_b[3] = (~(dcd_011 & combo3_0101_0010)); + assign e_06_b[4] = (~(dcd_100 & combo3_1101_0010)); + assign e_06_b[5] = (~(dcd_101 & combo3_1101_1001)); + assign e_06_b[6] = (~(dcd_110 & combo3_0011_0110)); + assign e_06_b[7] = (~(dcd_111 & combo3_0110_0110)); + + assign e[6] = (~(e_06_b[0] & e_06_b[1] & e_06_b[2] & e_06_b[3] & e_06_b[4] & e_06_b[5] & e_06_b[6] & e_06_b[7])); + + assign e_07_b[0] = (~(dcd_000 & combo3_0101_1001)); + assign e_07_b[1] = (~(dcd_001 & combo3_1000_0011)); + assign e_07_b[2] = (~(dcd_010 & combo3_1111_1000)); + assign e_07_b[3] = (~(dcd_011 & combo3_0011_1001)); + assign e_07_b[4] = (~(dcd_100 & combo3_1001_1001)); + assign e_07_b[5] = (~(dcd_101 & combo3_1011_0100)); + assign e_07_b[6] = (~(dcd_110 & combo3_1010_0101)); + assign e_07_b[7] = (~(dcd_111 & combo3_0101_0100)); + + assign e[7] = (~(e_07_b[0] & e_07_b[1] & e_07_b[2] & e_07_b[3] & e_07_b[4] & e_07_b[5] & e_07_b[6] & e_07_b[7])); + + assign e_08_b[0] = (~(dcd_000 & combo3_0001_0101)); + assign e_08_b[1] = (~(dcd_001 & combo3_0110_0011)); + assign e_08_b[2] = (~(dcd_010 & combo3_1111_1001)); + assign e_08_b[3] = (~(dcd_011 & combo3_1101_1010)); + assign e_08_b[4] = (~(dcd_100 & combo3_1010_1010)); + assign e_08_b[5] = (~(dcd_101 & combo3_1101_1001)); + assign e_08_b[6] = (~(dcd_110 & combo3_1000_1110)); + assign e_08_b[7] = (~(dcd_111 & combo3_0000_0001)); + + assign e[8] = (~(e_08_b[0] & e_08_b[1] & e_08_b[2] & e_08_b[3] & e_08_b[4] & e_08_b[5] & e_08_b[6] & e_08_b[7])); + + assign e_09_b[0] = (~(dcd_000 & combo3_0011_0000)); + assign e_09_b[1] = (~(dcd_001 & combo3_1101_0011)); + assign e_09_b[2] = (~(dcd_010 & combo3_1111_1010)); + assign e_09_b[3] = (~(dcd_011 & combo3_0110_1100)); + assign e_09_b[4] = (~(dcd_100 & combo3_0000_0011)); + assign e_09_b[5] = (~(dcd_101 & combo3_1011_0101)); + assign e_09_b[6] = (~(dcd_110 & combo3_0100_1001)); + assign e_09_b[7] = (~(dcd_111 & combo3_1100_0001)); + + assign e[9] = (~(e_09_b[0] & e_09_b[1] & e_09_b[2] & e_09_b[3] & e_09_b[4] & e_09_b[5] & e_09_b[6] & e_09_b[7])); + + assign e_10_b[0] = (~(dcd_000 & combo3_0110_1111)); + assign e_10_b[1] = (~(dcd_001 & combo3_0111_1010)); + assign e_10_b[2] = (~(dcd_010 & combo3_0001_1100)); + assign e_10_b[3] = (~(dcd_011 & combo3_1100_1011)); + assign e_10_b[4] = (~(dcd_100 & combo3_0000_0100)); + assign e_10_b[5] = (~(dcd_101 & combo3_1101_1111)); + assign e_10_b[6] = (~(dcd_110 & combo3_1110_1101)); + assign e_10_b[7] = (~(dcd_111 & combo3_1011_0001)); + + assign e[10] = (~(e_10_b[0] & e_10_b[1] & e_10_b[2] & e_10_b[3] & e_10_b[4] & e_10_b[5] & e_10_b[6] & e_10_b[7])); + + assign e_11_b[0] = (~(dcd_000 & combo3_0111_1001)); + assign e_11_b[1] = (~(dcd_001 & combo3_1100_1001)); + assign e_11_b[2] = (~(dcd_010 & combo3_0010_1000)); + assign e_11_b[3] = (~(dcd_011 & combo3_1101_1110)); + assign e_11_b[4] = (~(dcd_100 & combo3_1001_1001)); + assign e_11_b[5] = (~(dcd_101 & combo3_1001_0000)); + assign e_11_b[6] = (~(dcd_110 & combo3_0111_0111)); + assign e_11_b[7] = (~(dcd_111 & combo3_0010_1001)); + + assign e[11] = (~(e_11_b[0] & e_11_b[1] & e_11_b[2] & e_11_b[3] & e_11_b[4] & e_11_b[5] & e_11_b[6] & e_11_b[7])); + + assign e_12_b[0] = (~(dcd_000 & combo3_0110_0110)); + assign e_12_b[1] = (~(dcd_001 & combo3_0111_0111)); + assign e_12_b[2] = (~(dcd_010 & combo3_1100_1010)); + assign e_12_b[3] = (~(dcd_011 & combo3_1111_0000)); + assign e_12_b[4] = (~(dcd_100 & combo3_0110_1101)); + assign e_12_b[5] = (~(dcd_101 & combo3_1011_1000)); + assign e_12_b[6] = (~(dcd_110 & combo3_1010_0111)); + assign e_12_b[7] = (~(dcd_111 & combo3_0100_0101)); + + assign e[12] = (~(e_12_b[0] & e_12_b[1] & e_12_b[2] & e_12_b[3] & e_12_b[4] & e_12_b[5] & e_12_b[6] & e_12_b[7])); + + assign e_13_b[0] = (~(dcd_000 & combo3_1010_1001)); + assign e_13_b[1] = (~(dcd_001 & combo3_0010_1110)); + assign e_13_b[2] = (~(dcd_010 & combo3_1011_1010)); + assign e_13_b[3] = (~(dcd_011 & combo3_0100_0010)); + assign e_13_b[4] = (~(dcd_100 & combo3_1110_1101)); + assign e_13_b[5] = (~(dcd_101 & combo3_1010_1100)); + assign e_13_b[6] = (~(dcd_110 & combo3_0010_1111)); + assign e_13_b[7] = (~(dcd_111 & combo3_0010_1001)); + + assign e[13] = (~(e_13_b[0] & e_13_b[1] & e_13_b[2] & e_13_b[3] & e_13_b[4] & e_13_b[5] & e_13_b[6] & e_13_b[7])); + + assign e_14_b[0] = (~(dcd_000 & combo3_0111_1001)); + assign e_14_b[1] = (~(dcd_001 & combo3_0001_1000)); + assign e_14_b[2] = (~(dcd_010 & combo3_0100_1100)); + assign e_14_b[3] = (~(dcd_011 & combo3_1100_1011)); + assign e_14_b[4] = (~(dcd_100 & combo3_1111_0010)); + assign e_14_b[5] = (~(dcd_101 & combo3_0101_1111)); + assign e_14_b[6] = (~(dcd_110 & combo3_0110_1100)); + assign e_14_b[7] = (~(dcd_111 & combo3_0001_0010)); + + assign e[14] = (~(e_14_b[0] & e_14_b[1] & e_14_b[2] & e_14_b[3] & e_14_b[4] & e_14_b[5] & e_14_b[6] & e_14_b[7])); + + assign e_15_b[0] = (~(dcd_000 & combo3_1001_0000)); + assign e_15_b[1] = (~(dcd_001 & combo3_1001_0010)); + assign e_15_b[2] = (~(dcd_010 & combo3_1101_1010)); + assign e_15_b[3] = (~(dcd_011 & combo3_1001_0111)); + assign e_15_b[4] = (~(dcd_100 & combo3_0101_1111)); + assign e_15_b[5] = (~(dcd_101 & combo3_1001_0001)); + assign e_15_b[6] = (~(dcd_110 & combo3_0011_0101)); + assign e_15_b[7] = (~(dcd_111 & combo3_1100_0101)); + + assign e[15] = (~(e_15_b[0] & e_15_b[1] & e_15_b[2] & e_15_b[3] & e_15_b[4] & e_15_b[5] & e_15_b[6] & e_15_b[7])); + + assign e_16_b[0] = (~(dcd_000 & combo3_1010_1111)); + assign e_16_b[1] = (~(dcd_001 & combo3_0101_1100)); + assign e_16_b[2] = (~(dcd_010 & combo3_0100_0000)); + assign e_16_b[3] = (~(dcd_011 & combo3_0001_0001)); + assign e_16_b[4] = (~(dcd_100 & combo3_0000_1101)); + assign e_16_b[5] = (~(dcd_101 & combo3_1100_1111)); + assign e_16_b[6] = (~(dcd_110 & combo3_1010_0100)); + assign e_16_b[7] = (~(dcd_111 & combo3_0001_1101)); + + assign e[16] = (~(e_16_b[0] & e_16_b[1] & e_16_b[2] & e_16_b[3] & e_16_b[4] & e_16_b[5] & e_16_b[6] & e_16_b[7])); + + assign e_17_b[0] = (~(dcd_000 & combo3_1010_0010)); + assign e_17_b[1] = (~(dcd_001 & combo3_1111_0010)); + assign e_17_b[2] = (~(dcd_010 & combo3_0101_1001)); + assign e_17_b[3] = (~(dcd_011 & combo3_1000_0110)); + assign e_17_b[4] = (~(dcd_100 & combo3_1110_0001)); + assign e_17_b[5] = (~(dcd_101 & combo3_0010_0011)); + assign e_17_b[6] = (~(dcd_110 & combo3_1000_1010)); + assign e_17_b[7] = (~(dcd_111 & combo3_1001_0100)); + + assign e[17] = (~(e_17_b[0] & e_17_b[1] & e_17_b[2] & e_17_b[3] & e_17_b[4] & e_17_b[5] & e_17_b[6] & e_17_b[7])); + + assign e_18_b[0] = (~(dcd_000 & combo3_1101_1100)); + assign e_18_b[1] = (~(dcd_001 & combo3_0010_1101)); + assign e_18_b[2] = (~(dcd_010 & combo3_1100_1010)); + assign e_18_b[3] = (~(dcd_011 & combo3_1010_0001)); + assign e_18_b[4] = (~(dcd_100 & combo3_1000_0000)); + assign e_18_b[5] = (~(dcd_101 & combo3_1011_0010)); + assign e_18_b[6] = (~(dcd_110 & combo3_1110_1010)); + assign e_18_b[7] = (~(dcd_111 & combo3_0010_1000)); + + assign e[18] = (~(e_18_b[0] & e_18_b[1] & e_18_b[2] & e_18_b[3] & e_18_b[4] & e_18_b[5] & e_18_b[6] & e_18_b[7])); + + assign e_19_b[0] = (~(dcd_000 & tiup)); + assign e_19_b[1] = (~(dcd_001 & tiup)); + assign e_19_b[2] = (~(dcd_010 & tiup)); + assign e_19_b[3] = (~(dcd_011 & tiup)); + assign e_19_b[4] = (~(dcd_100 & tiup)); + assign e_19_b[5] = (~(dcd_101 & tiup)); + assign e_19_b[6] = (~(dcd_110 & tiup)); + assign e_19_b[7] = (~(dcd_111 & tiup)); + + assign e[19] = (~(e_19_b[0] & e_19_b[1] & e_19_b[2] & e_19_b[3] & e_19_b[4] & e_19_b[5] & e_19_b[6] & e_19_b[7])); + + ////####################################### + ////## RANGE VECTORs + ////####################################### + + assign r_00_b[0] = (~(dcd_000 & tidn)); + assign r_00_b[1] = (~(dcd_001 & tidn)); + assign r_00_b[2] = (~(dcd_010 & tidn)); + assign r_00_b[3] = (~(dcd_011 & tidn)); + assign r_00_b[4] = (~(dcd_100 & tidn)); + assign r_00_b[5] = (~(dcd_101 & tidn)); + assign r_00_b[6] = (~(dcd_110 & tidn)); + assign r_00_b[7] = (~(dcd_111 & tidn)); + + assign r[0] = (~(r_00_b[0] & r_00_b[1] & r_00_b[2] & r_00_b[3] & r_00_b[4] & r_00_b[5] & r_00_b[6] & r_00_b[7])); + + assign r_01_b[0] = (~(dcd_000 & tiup)); + assign r_01_b[1] = (~(dcd_001 & tiup)); + assign r_01_b[2] = (~(dcd_010 & combo3_1000_0000)); + assign r_01_b[3] = (~(dcd_011 & tidn)); + assign r_01_b[4] = (~(dcd_100 & tidn)); + assign r_01_b[5] = (~(dcd_101 & tidn)); + assign r_01_b[6] = (~(dcd_110 & tidn)); + assign r_01_b[7] = (~(dcd_111 & tidn)); + + assign r[1] = (~(r_01_b[0] & r_01_b[1] & r_01_b[2] & r_01_b[3] & r_01_b[4] & r_01_b[5] & r_01_b[6] & r_01_b[7])); + + assign r_02_b[0] = (~(dcd_000 & tidn)); + assign r_02_b[1] = (~(dcd_001 & tidn)); + assign r_02_b[2] = (~(dcd_010 & combo3_0111_1111)); + assign r_02_b[3] = (~(dcd_011 & tiup)); + assign r_02_b[4] = (~(dcd_100 & tiup)); + assign r_02_b[5] = (~(dcd_101 & tiup)); + assign r_02_b[6] = (~(dcd_110 & tiup)); + assign r_02_b[7] = (~(dcd_111 & tiup)); + + assign r[2] = (~(r_02_b[0] & r_02_b[1] & r_02_b[2] & r_02_b[3] & r_02_b[4] & r_02_b[5] & r_02_b[6] & r_02_b[7])); + + assign r_03_b[0] = (~(dcd_000 & combo3_1111_1000)); + assign r_03_b[1] = (~(dcd_001 & tidn)); + assign r_03_b[2] = (~(dcd_010 & combo3_0111_1111)); + assign r_03_b[3] = (~(dcd_011 & tiup)); + assign r_03_b[4] = (~(dcd_100 & combo3_1100_0000)); + assign r_03_b[5] = (~(dcd_101 & tidn)); + assign r_03_b[6] = (~(dcd_110 & tidn)); + assign r_03_b[7] = (~(dcd_111 & tidn)); + + assign r[3] = (~(r_03_b[0] & r_03_b[1] & r_03_b[2] & r_03_b[3] & r_03_b[4] & r_03_b[5] & r_03_b[6] & r_03_b[7])); + + assign r_04_b[0] = (~(dcd_000 & combo3_1000_0111)); + assign r_04_b[1] = (~(dcd_001 & combo3_1110_0000)); + assign r_04_b[2] = (~(dcd_010 & combo3_0111_1111)); + assign r_04_b[3] = (~(dcd_011 & tidn)); + assign r_04_b[4] = (~(dcd_100 & combo3_0011_1111)); + assign r_04_b[5] = (~(dcd_101 & combo3_1111_1100)); + assign r_04_b[6] = (~(dcd_110 & tidn)); + assign r_04_b[7] = (~(dcd_111 & tidn)); + + assign r[4] = (~(r_04_b[0] & r_04_b[1] & r_04_b[2] & r_04_b[3] & r_04_b[4] & r_04_b[5] & r_04_b[6] & r_04_b[7])); + + assign r_05_b[0] = (~(dcd_000 & combo3_0110_0111)); + assign r_05_b[1] = (~(dcd_001 & combo3_0001_1000)); + assign r_05_b[2] = (~(dcd_010 & combo3_0111_0000)); + assign r_05_b[3] = (~(dcd_011 & combo3_1111_1000)); + assign r_05_b[4] = (~(dcd_100 & combo3_0011_1111)); + assign r_05_b[5] = (~(dcd_101 & combo3_0000_0011)); + assign r_05_b[6] = (~(dcd_110 & combo3_1111_1100)); + assign r_05_b[7] = (~(dcd_111 & tidn)); + + assign r[5] = (~(r_05_b[0] & r_05_b[1] & r_05_b[2] & r_05_b[3] & r_05_b[4] & r_05_b[5] & r_05_b[6] & r_05_b[7])); + + assign r_06_b[0] = (~(dcd_000 & combo3_0101_0110)); + assign r_06_b[1] = (~(dcd_001 & combo3_1001_0110)); + assign r_06_b[2] = (~(dcd_010 & combo3_0100_1100)); + assign r_06_b[3] = (~(dcd_011 & combo3_1100_0110)); + assign r_06_b[4] = (~(dcd_100 & combo3_0011_0000)); + assign r_06_b[5] = (~(dcd_101 & combo3_1110_0011)); + assign r_06_b[6] = (~(dcd_110 & combo3_1100_0011)); + assign r_06_b[7] = (~(dcd_111 & combo3_1110_0000)); + + assign r[6] = (~(r_06_b[0] & r_06_b[1] & r_06_b[2] & r_06_b[3] & r_06_b[4] & r_06_b[5] & r_06_b[6] & r_06_b[7])); + + assign r_07_b[0] = (~(dcd_000 & combo3_1111_1100)); + assign r_07_b[1] = (~(dcd_001 & combo3_1100_1101)); + assign r_07_b[2] = (~(dcd_010 & combo3_0010_1010)); + assign r_07_b[3] = (~(dcd_011 & combo3_1010_0101)); + assign r_07_b[4] = (~(dcd_100 & combo3_0010_1100)); + assign r_07_b[5] = (~(dcd_101 & combo3_1001_1011)); + assign r_07_b[6] = (~(dcd_110 & combo3_0011_0011)); + assign r_07_b[7] = (~(dcd_111 & combo3_1001_1000)); + + assign r[7] = (~(r_07_b[0] & r_07_b[1] & r_07_b[2] & r_07_b[3] & r_07_b[4] & r_07_b[5] & r_07_b[6] & r_07_b[7])); + + assign r_08_b[0] = (~(dcd_000 & combo3_0001_1101)); + assign r_08_b[1] = (~(dcd_001 & combo3_0101_0110)); + assign r_08_b[2] = (~(dcd_010 & combo3_0111_1111)); + assign r_08_b[3] = (~(dcd_011 & combo3_1111_0001)); + assign r_08_b[4] = (~(dcd_100 & combo3_1001_1010)); + assign r_08_b[5] = (~(dcd_101 & combo3_0101_0010)); + assign r_08_b[6] = (~(dcd_110 & combo3_1010_1010)); + assign r_08_b[7] = (~(dcd_111 & combo3_0101_0110)); + + assign r[8] = (~(r_08_b[0] & r_08_b[1] & r_08_b[2] & r_08_b[3] & r_08_b[4] & r_08_b[5] & r_08_b[6] & r_08_b[7])); + + assign r_09_b[0] = (~(dcd_000 & combo3_1110_0110)); + assign r_09_b[1] = (~(dcd_001 & combo3_0000_1101)); + assign r_09_b[2] = (~(dcd_010 & combo3_0110_0000)); + assign r_09_b[3] = (~(dcd_011 & combo3_0011_0110)); + assign r_09_b[4] = (~(dcd_100 & combo3_1010_1100)); + assign r_09_b[5] = (~(dcd_101 & combo3_1100_0111)); + assign r_09_b[6] = (~(dcd_110 & tiup)); + assign r_09_b[7] = (~(dcd_111 & combo3_0001_1100)); + + assign r[9] = (~(r_09_b[0] & r_09_b[1] & r_09_b[2] & r_09_b[3] & r_09_b[4] & r_09_b[5] & r_09_b[6] & r_09_b[7])); + + assign r_10_b[0] = (~(dcd_000 & combo3_1110_1101)); + assign r_10_b[1] = (~(dcd_001 & combo3_0001_0111)); + assign r_10_b[2] = (~(dcd_010 & combo3_1101_1000)); + assign r_10_b[3] = (~(dcd_011 & combo3_1101_0011)); + assign r_10_b[4] = (~(dcd_100 & combo3_1111_1010)); + assign r_10_b[5] = (~(dcd_101 & combo3_1010_0110)); + assign r_10_b[6] = (~(dcd_110 & combo3_0000_0111)); + assign r_10_b[7] = (~(dcd_111 & combo3_0010_0101)); + + assign r[10] = (~(r_10_b[0] & r_10_b[1] & r_10_b[2] & r_10_b[3] & r_10_b[4] & r_10_b[5] & r_10_b[6] & r_10_b[7])); + + assign r_11_b[0] = (~(dcd_000 & combo3_1011_1100)); + assign r_11_b[1] = (~(dcd_001 & combo3_1010_0000)); + assign r_11_b[2] = (~(dcd_010 & combo3_0111_0111)); + assign r_11_b[3] = (~(dcd_011 & combo3_0111_1010)); + assign r_11_b[4] = (~(dcd_100 & combo3_0001_1100)); + assign r_11_b[5] = (~(dcd_101 & combo3_0001_0101)); + assign r_11_b[6] = (~(dcd_110 & combo3_1111_1001)); + assign r_11_b[7] = (~(dcd_111 & combo3_0100_1111)); + + assign r[11] = (~(r_11_b[0] & r_11_b[1] & r_11_b[2] & r_11_b[3] & r_11_b[4] & r_11_b[5] & r_11_b[6] & r_11_b[7])); + + assign r_12_b[0] = (~(dcd_000 & combo3_0100_1110)); + assign r_12_b[1] = (~(dcd_001 & combo3_0100_0100)); + assign r_12_b[2] = (~(dcd_010 & combo3_1101_1111)); + assign r_12_b[3] = (~(dcd_011 & combo3_1100_0000)); + assign r_12_b[4] = (~(dcd_100 & combo3_0000_1010)); + assign r_12_b[5] = (~(dcd_101 & combo3_0010_0001)); + assign r_12_b[6] = (~(dcd_110 & combo3_0000_1011)); + assign r_12_b[7] = (~(dcd_111 & combo3_1110_1000)); + + assign r[12] = (~(r_12_b[0] & r_12_b[1] & r_12_b[2] & r_12_b[3] & r_12_b[4] & r_12_b[5] & r_12_b[6] & r_12_b[7])); + + assign r_13_b[0] = (~(dcd_000 & combo3_1010_1001)); + assign r_13_b[1] = (~(dcd_001 & combo3_0001_0100)); + assign r_13_b[2] = (~(dcd_010 & combo3_0111_0101)); + assign r_13_b[3] = (~(dcd_011 & combo3_0000_1001)); + assign r_13_b[4] = (~(dcd_100 & combo3_0010_1000)); + assign r_13_b[5] = (~(dcd_101 & combo3_0000_0011)); + assign r_13_b[6] = (~(dcd_110 & combo3_1001_0010)); + assign r_13_b[7] = (~(dcd_111 & combo3_0010_0100)); + + assign r[13] = (~(r_13_b[0] & r_13_b[1] & r_13_b[2] & r_13_b[3] & r_13_b[4] & r_13_b[5] & r_13_b[6] & r_13_b[7])); + + assign r_14_b[0] = (~(dcd_000 & tidn)); + assign r_14_b[1] = (~(dcd_001 & tidn)); + assign r_14_b[2] = (~(dcd_010 & tidn)); + assign r_14_b[3] = (~(dcd_011 & tidn)); + assign r_14_b[4] = (~(dcd_100 & tidn)); + assign r_14_b[5] = (~(dcd_101 & tidn)); + assign r_14_b[6] = (~(dcd_110 & tidn)); + assign r_14_b[7] = (~(dcd_111 & tidn)); + + assign r[14] = (~(r_14_b[0] & r_14_b[1] & r_14_b[2] & r_14_b[3] & r_14_b[4] & r_14_b[5] & r_14_b[6] & r_14_b[7])); + + ////####################################### + ////## RENUMBERING OUTPUTS + ////####################################### + + assign est[1:20] = e[0:19]; // renumbering + assign rng[6:20] = r[0:14]; // renumbering + +endmodule diff --git a/dev/verilog/work/fu_tblsqo.v b/dev/verilog/work/fu_tblsqo.v new file mode 100755 index 0000000..fed8280 --- /dev/null +++ b/dev/verilog/work/fu_tblsqo.v @@ -0,0 +1,959 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + + `include "tri_a2o.vh" + +// 11111111111111000001 011111101000010 0 +// 11111100000001111101 011110111010000 1 +// 11111000001010101101 011110001101100 2 +// 11110100011000111111 011101100010110 3 +// 11110000101100101001 011100111001100 4 +// 11101101000101011011 011100010001110 5 +// 11101001100011001101 011011101011010 6 +// 11100110000101110001 011011000110010 7 +// 11100010101100111101 011010100010100 8 +// 11011111011000101001 011010000000000 9 +// 11011100001000100111 011001011110100 10 +// 11011000111100110011 011000111110010 11 +// 11010101110100111111 011000011111000 12 +// 11010010110001000101 011000000000110 13 +// 11001111110000111101 010111100011100 14 +// 11001100110100100001 010111000111010 15 +// 11001001111011100101 010110101011110 16 +// 11000111000110000111 010110010001000 17 +// 11000100010011111101 010101110111010 18 +// 11000001100101000011 010101011110010 19 +// 10111110111001010001 010101000101110 20 +// 10111100010000100001 010100101110010 21 +// 10111001101010101101 010100010111010 22 +// 10110111000111110011 010100000001000 23 +// 10110100100111101001 010011101011010 24 +// 10110010001010001101 010011010110010 25 +// 10101111101111011001 010011000001110 26 +// 10101101010111001011 010010101110000 27 +// 10101011000001011001 010010011010100 28 +// 10101000101110000101 010010000111110 29 +// 10100110011101000101 010001110101010 30 +// 10100100001110011011 010001100011100 31 +// 10100010000001111101 010001010010000 32 +// 10011111110111101101 010001000001000 33 +// 10011101101111100011 010000110000100 34 +// 10011011101001011101 010000100000100 35 +// 10011001100101011001 010000010000110 36 +// 10010111100011010011 010000000001010 37 +// 10010101100011000111 001111110010010 38 +// 10010011100100110101 001111100011110 39 +// 10010001101000010101 001111010101100 40 +// 10001111101101101001 001111000111100 41 +// 10001101110100101011 001110111010000 42 +// 10001011111101011011 001110101100110 43 +// 10001010000111110101 001110011111110 44 +// 10001000010011110101 001110010011000 45 +// 10000110100001011101 001110000110100 46 +// 10000100110000100111 001101111010100 47 +// 10000011000001010001 001101101110110 48 +// 10000001010011011011 001101100011000 49 +// 01111111100111000011 001101010111110 50 +// 01111101111100000011 001101001100110 51 +// 01111100010010011101 001101000001110 52 +// 01111010101010001111 001100110111010 53 +// 01111001000011010011 001100101100110 54 +// 01110111011101101101 001100100010100 55 +// 01110101111001010111 001100011000100 56 +// 01110100010110010001 001100001110110 57 +// 01110010110100011001 001100000101010 58 +// 01110001010011101111 001011111100000 59 +// 01101111110100001111 001011110010110 60 +// 01101110010101110111 001011101001110 61 +// 01101100111000101001 001011100001000 62 +// 01101011011100100001 001011011000010 63 + +module fu_tblsqo( + f, + est, + rng +); + input [1:6] f; + output [1:20] est; + output [6:20] rng; + + // end ports + + // ENTITY + + + parameter tiup = 1'b1; + parameter tidn = 1'b0; + + wire dcd_00x; + wire dcd_01x; + wire dcd_10x; + wire dcd_11x; + wire dcd_000; + wire dcd_001; + wire dcd_010; + wire dcd_011; + wire dcd_100; + wire dcd_101; + wire dcd_110; + wire dcd_111; + wire combo2_1000; + wire combo2_0100; + wire combo2_1100; + wire combo2_0010; + wire combo2_1010; + wire combo2_0110; + wire combo2_1110; + wire combo2_0001; + wire combo2_1001; + wire combo2_0101; + wire combo2_1101; + wire combo2_0011; + wire combo2_1011; + wire combo2_0111; + wire combo2_1000_xxxx_b; + wire combo2_0100_xxxx_b; + wire combo2_1100_xxxx_b; + wire combo2_0010_xxxx_b; + wire combo2_1010_xxxx_b; + wire combo2_0110_xxxx_b; + wire combo2_1110_xxxx_b; + wire combo2_0001_xxxx_b; + wire combo2_1001_xxxx_b; + wire combo2_0101_xxxx_b; + wire combo2_1101_xxxx_b; + wire combo2_0011_xxxx_b; + wire combo2_1011_xxxx_b; + wire combo2_0111_xxxx_b; + wire combo2_xxxx_1000_b; + wire combo2_xxxx_0100_b; + wire combo2_xxxx_1100_b; + wire combo2_xxxx_0010_b; + wire combo2_xxxx_1010_b; + wire combo2_xxxx_0110_b; + wire combo2_xxxx_1110_b; + wire combo2_xxxx_0001_b; + wire combo2_xxxx_1001_b; + wire combo2_xxxx_0101_b; + wire combo2_xxxx_1101_b; + wire combo2_xxxx_0011_b; + wire combo2_xxxx_1011_b; + wire combo2_xxxx_0111_b; + wire combo3_0000_0001; + wire combo3_0000_0011; + wire combo3_0000_0100; + wire combo3_0000_1011; + wire combo3_0000_1100; + wire combo3_0000_1101; + wire combo3_0000_1111; + wire combo3_0001_0001; + wire combo3_0001_0010; + wire combo3_0001_0100; + wire combo3_0001_0101; + wire combo3_0001_0111; + wire combo3_0001_1000; + wire combo3_0001_1110; + wire combo3_0001_1111; + wire combo3_0010_0001; + wire combo3_0010_0010; + wire combo3_0010_0011; + wire combo3_0010_0100; + wire combo3_0010_0110; + wire combo3_0010_1001; + wire combo3_0010_1101; + wire combo3_0010_1110; + wire combo3_0011_0000; + wire combo3_0011_0001; + wire combo3_0011_0011; + wire combo3_0011_0100; + wire combo3_0011_0101; + wire combo3_0011_1000; + wire combo3_0011_1001; + wire combo3_0011_1010; + wire combo3_0011_1100; + wire combo3_0011_1110; + wire combo3_0011_1111; + wire combo3_0100_0000; + wire combo3_0100_0101; + wire combo3_0100_0110; + wire combo3_0100_1000; + wire combo3_0100_1001; + wire combo3_0100_1010; + wire combo3_0100_1100; + wire combo3_0100_1101; + wire combo3_0101_0000; + wire combo3_0101_0001; + wire combo3_0101_0011; + wire combo3_0101_0101; + wire combo3_0101_0110; + wire combo3_0101_1001; + wire combo3_0101_1010; + wire combo3_0101_1110; + wire combo3_0101_1111; + wire combo3_0110_0011; + wire combo3_0110_0110; + wire combo3_0110_0111; + wire combo3_0110_1001; + wire combo3_0110_1010; + wire combo3_0110_1011; + wire combo3_0110_1100; + wire combo3_0110_1101; + wire combo3_0110_1110; + wire combo3_0110_1111; + wire combo3_0111_0000; + wire combo3_0111_0010; + wire combo3_0111_0011; + wire combo3_0111_0110; + wire combo3_0111_1000; + wire combo3_0111_1001; + wire combo3_0111_1100; + wire combo3_0111_1110; + wire combo3_0111_1111; + wire combo3_1000_0000; + wire combo3_1000_0001; + wire combo3_1000_0011; + wire combo3_1000_0110; + wire combo3_1000_1000; + wire combo3_1000_1010; + wire combo3_1000_1101; + wire combo3_1000_1110; + wire combo3_1000_1111; + wire combo3_1001_0000; + wire combo3_1001_0010; + wire combo3_1001_0011; + wire combo3_1001_0100; + wire combo3_1001_0111; + wire combo3_1001_1000; + wire combo3_1001_1001; + wire combo3_1001_1010; + wire combo3_1001_1100; + wire combo3_1001_1101; + wire combo3_1001_1110; + wire combo3_1001_1111; + wire combo3_1010_0010; + wire combo3_1010_0100; + wire combo3_1010_0101; + wire combo3_1010_0110; + wire combo3_1010_0111; + wire combo3_1010_1010; + wire combo3_1010_1100; + wire combo3_1010_1101; + wire combo3_1010_1110; + wire combo3_1011_0011; + wire combo3_1011_0110; + wire combo3_1011_0111; + wire combo3_1011_1000; + wire combo3_1011_1001; + wire combo3_1011_1010; + wire combo3_1011_1011; + wire combo3_1011_1110; + wire combo3_1100_0000; + wire combo3_1100_0001; + wire combo3_1100_0011; + wire combo3_1100_0110; + wire combo3_1100_0111; + wire combo3_1100_1010; + wire combo3_1100_1100; + wire combo3_1100_1110; + wire combo3_1101_0000; + wire combo3_1101_0011; + wire combo3_1101_0101; + wire combo3_1101_1000; + wire combo3_1101_1010; + wire combo3_1101_1011; + wire combo3_1101_1101; + wire combo3_1110_0000; + wire combo3_1110_0001; + wire combo3_1110_0010; + wire combo3_1110_0011; + wire combo3_1110_0100; + wire combo3_1110_0101; + wire combo3_1110_0110; + wire combo3_1110_1010; + wire combo3_1110_1011; + wire combo3_1111_0000; + wire combo3_1111_0011; + wire combo3_1111_0101; + wire combo3_1111_1000; + wire combo3_1111_1001; + wire combo3_1111_1011; + wire combo3_1111_1100; + wire combo3_1111_1110; + wire [0:7] e_00_b; + wire [0:7] e_01_b; + wire [0:7] e_02_b; + wire [0:7] e_03_b; + wire [0:7] e_04_b; + wire [0:7] e_05_b; + wire [0:7] e_06_b; + wire [0:7] e_07_b; + wire [0:7] e_08_b; + wire [0:7] e_09_b; + wire [0:7] e_10_b; + wire [0:7] e_11_b; + wire [0:7] e_12_b; + wire [0:7] e_13_b; + wire [0:7] e_14_b; + wire [0:7] e_15_b; + wire [0:7] e_16_b; + wire [0:7] e_17_b; + wire [0:7] e_18_b; + wire [0:7] e_19_b; + wire [0:19] e; + wire [0:7] r_00_b; + wire [0:7] r_01_b; + wire [0:7] r_02_b; + wire [0:7] r_03_b; + wire [0:7] r_04_b; + wire [0:7] r_05_b; + wire [0:7] r_06_b; + wire [0:7] r_07_b; + wire [0:7] r_08_b; + wire [0:7] r_09_b; + wire [0:7] r_10_b; + wire [0:7] r_11_b; + wire [0:7] r_12_b; + wire [0:7] r_13_b; + wire [0:7] r_14_b; + wire [0:14] r; + + ////####################################### + ////## decode the upper 3 index bits + ////####################################### + + assign dcd_00x = (~f[1]) & (~f[2]); + assign dcd_01x = (~f[1]) & f[2]; + assign dcd_10x = f[1] & (~f[2]); + assign dcd_11x = f[1] & f[2]; + + assign dcd_000 = (~f[3]) & dcd_00x; + assign dcd_001 = f[3] & dcd_00x; + assign dcd_010 = (~f[3]) & dcd_01x; + assign dcd_011 = f[3] & dcd_01x; + assign dcd_100 = (~f[3]) & dcd_10x; + assign dcd_101 = f[3] & dcd_10x; + assign dcd_110 = (~f[3]) & dcd_11x; + assign dcd_111 = f[3] & dcd_11x; + + ////####################################### + ////## combos based on lower 2 index bits + ////####################################### + + assign combo2_1000 = (~f[5]) & (~f[6]); // [0] + assign combo2_0100 = (~f[5]) & f[6]; // [1] + assign combo2_1100 = (~f[5]); // [0,1] + assign combo2_0010 = f[5] & (~f[6]); // [2] + assign combo2_1010 = (~f[6]); // [0,2] + assign combo2_0110 = f[5] ^ f[6]; // [1,2] + assign combo2_1110 = (~(f[5] & f[6])); // [0,1,2] + assign combo2_0001 = f[5] & f[6]; // [3] + assign combo2_1001 = (~(f[5] ^ f[6])); // [0,3] + assign combo2_0101 = f[6]; // [1,3] + assign combo2_1101 = (~(f[5] & (~f[6]))); // [1,2,3] + assign combo2_0011 = f[5]; // [2,3] + assign combo2_1011 = (~((~f[5]) & f[6])); // [0,2,3] + assign combo2_0111 = (~((~f[5]) & (~f[6]))); // [1,2,3] + + ////####################################### + ////## combos based on lower 3 index bits + ////####################################### + + assign combo2_1000_xxxx_b = (~((~f[4]) & combo2_1000)); + assign combo2_0100_xxxx_b = (~((~f[4]) & combo2_0100)); + assign combo2_1100_xxxx_b = (~((~f[4]) & combo2_1100)); + assign combo2_0010_xxxx_b = (~((~f[4]) & combo2_0010)); + assign combo2_1010_xxxx_b = (~((~f[4]) & combo2_1010)); + assign combo2_0110_xxxx_b = (~((~f[4]) & combo2_0110)); + assign combo2_1110_xxxx_b = (~((~f[4]) & combo2_1110)); + assign combo2_0001_xxxx_b = (~((~f[4]) & combo2_0001)); + assign combo2_1001_xxxx_b = (~((~f[4]) & combo2_1001)); + assign combo2_0101_xxxx_b = (~((~f[4]) & combo2_0101)); + assign combo2_1101_xxxx_b = (~((~f[4]) & combo2_1101)); + assign combo2_0011_xxxx_b = (~((~f[4]) & combo2_0011)); + assign combo2_1011_xxxx_b = (~((~f[4]) & combo2_1011)); + assign combo2_0111_xxxx_b = (~((~f[4]) & combo2_0111)); + + assign combo2_xxxx_1000_b = (~(f[4] & combo2_1000)); + assign combo2_xxxx_0100_b = (~(f[4] & combo2_0100)); + assign combo2_xxxx_1100_b = (~(f[4] & combo2_1100)); + assign combo2_xxxx_0010_b = (~(f[4] & combo2_0010)); + assign combo2_xxxx_1010_b = (~(f[4] & combo2_1010)); + assign combo2_xxxx_0110_b = (~(f[4] & combo2_0110)); + assign combo2_xxxx_1110_b = (~(f[4] & combo2_1110)); + assign combo2_xxxx_0001_b = (~(f[4] & combo2_0001)); + assign combo2_xxxx_1001_b = (~(f[4] & combo2_1001)); + assign combo2_xxxx_0101_b = (~(f[4] & combo2_0101)); + assign combo2_xxxx_1101_b = (~(f[4] & combo2_1101)); + assign combo2_xxxx_0011_b = (~(f[4] & combo2_0011)); + assign combo2_xxxx_1011_b = (~(f[4] & combo2_1011)); + assign combo2_xxxx_0111_b = (~(f[4] & combo2_0111)); + + assign combo3_0000_0001 = (~(combo2_xxxx_0001_b)); //i=1, 1 1 + assign combo3_0000_0011 = (~(combo2_xxxx_0011_b)); //i=3, 4 2 + assign combo3_0000_0100 = (~(combo2_xxxx_0100_b)); //i=4, 1 3 + assign combo3_0000_1011 = (~(combo2_xxxx_1011_b)); //i=11, 1 4 + assign combo3_0000_1100 = (~(combo2_xxxx_1100_b)); //i=12, 1 5 + assign combo3_0000_1101 = (~(combo2_xxxx_1101_b)); //i=13, 1 6 + assign combo3_0000_1111 = (~((~f[4]))); //i=15, 4 7 + assign combo3_0001_0001 = (~((~combo2_0001))); //i=17, 1 8* + assign combo3_0001_0010 = (~(combo2_0001_xxxx_b & combo2_xxxx_0010_b)); //i=18, 1 9 + assign combo3_0001_0100 = (~(combo2_0001_xxxx_b & combo2_xxxx_0100_b)); //i=20, 1 10 + assign combo3_0001_0101 = (~(combo2_0001_xxxx_b & combo2_xxxx_0101_b)); //i=21, 2 11 + assign combo3_0001_0111 = (~(combo2_0001_xxxx_b & combo2_xxxx_0111_b)); //i=23, 1 12 + assign combo3_0001_1000 = (~(combo2_0001_xxxx_b & combo2_xxxx_1000_b)); //i=24, 1 13 + assign combo3_0001_1110 = (~(combo2_0001_xxxx_b & combo2_xxxx_1110_b)); //i=30, 1 14 + assign combo3_0001_1111 = (~(combo2_0001_xxxx_b & (~f[4]))); //i=31, 2 15 + assign combo3_0010_0001 = (~(combo2_0010_xxxx_b & combo2_xxxx_0001_b)); //i=33, 1 16 + assign combo3_0010_0010 = (~((~combo2_0010))); //i=34, 1 17* + assign combo3_0010_0011 = (~(combo2_0010_xxxx_b & combo2_xxxx_0011_b)); //i=35, 1 18 + assign combo3_0010_0100 = (~(combo2_0010_xxxx_b & combo2_xxxx_0100_b)); //i=36, 1 19 + assign combo3_0010_0110 = (~(combo2_0010_xxxx_b & combo2_xxxx_0110_b)); //i=38, 2 20 + assign combo3_0010_1001 = (~(combo2_0010_xxxx_b & combo2_xxxx_1001_b)); //i=41, 2 21 + assign combo3_0010_1101 = (~(combo2_0010_xxxx_b & combo2_xxxx_1101_b)); //i=45, 2 22 + assign combo3_0010_1110 = (~(combo2_0010_xxxx_b & combo2_xxxx_1110_b)); //i=46, 1 23 + assign combo3_0011_0000 = (~(combo2_0011_xxxx_b)); //i=48, 1 24 + assign combo3_0011_0001 = (~(combo2_0011_xxxx_b & combo2_xxxx_0001_b)); //i=49, 3 25 + assign combo3_0011_0011 = (~((~combo2_0011))); //i=51, 1 26* + assign combo3_0011_0100 = (~(combo2_0011_xxxx_b & combo2_xxxx_0100_b)); //i=52, 1 27 + assign combo3_0011_0101 = (~(combo2_0011_xxxx_b & combo2_xxxx_0101_b)); //i=53, 1 28 + assign combo3_0011_1000 = (~(combo2_0011_xxxx_b & combo2_xxxx_1000_b)); //i=56, 5 29 + assign combo3_0011_1001 = (~(combo2_0011_xxxx_b & combo2_xxxx_1001_b)); //i=57, 4 30 + assign combo3_0011_1010 = (~(combo2_0011_xxxx_b & combo2_xxxx_1010_b)); //i=58, 1 31 + assign combo3_0011_1100 = (~(combo2_0011_xxxx_b & combo2_xxxx_1100_b)); //i=60, 2 32 + assign combo3_0011_1110 = (~(combo2_0011_xxxx_b & combo2_xxxx_1110_b)); //i=62, 2 33 + assign combo3_0011_1111 = (~(combo2_0011_xxxx_b & (~f[4]))); //i=63, 3 34 + assign combo3_0100_0000 = (~(combo2_0100_xxxx_b)); //i=64, 1 35 + assign combo3_0100_0101 = (~(combo2_0100_xxxx_b & combo2_xxxx_0101_b)); //i=69, 1 36 + assign combo3_0100_0110 = (~(combo2_0100_xxxx_b & combo2_xxxx_0110_b)); //i=70, 1 37 + assign combo3_0100_1000 = (~(combo2_0100_xxxx_b & combo2_xxxx_1000_b)); //i=72, 1 38 + assign combo3_0100_1001 = (~(combo2_0100_xxxx_b & combo2_xxxx_1001_b)); //i=73, 1 39 + assign combo3_0100_1010 = (~(combo2_0100_xxxx_b & combo2_xxxx_1010_b)); //i=74, 2 40 + assign combo3_0100_1100 = (~(combo2_0100_xxxx_b & combo2_xxxx_1100_b)); //i=76, 1 41 + assign combo3_0100_1101 = (~(combo2_0100_xxxx_b & combo2_xxxx_1101_b)); //i=77, 1 42 + assign combo3_0101_0000 = (~(combo2_0101_xxxx_b)); //i=80, 1 43 + assign combo3_0101_0001 = (~(combo2_0101_xxxx_b & combo2_xxxx_0001_b)); //i=81, 2 44 + assign combo3_0101_0011 = (~(combo2_0101_xxxx_b & combo2_xxxx_0011_b)); //i=83, 1 45 + assign combo3_0101_0101 = (~((~combo2_0101))); //i=85, 1 46* + assign combo3_0101_0110 = (~(combo2_0101_xxxx_b & combo2_xxxx_0110_b)); //i=86, 1 47 + assign combo3_0101_1001 = (~(combo2_0101_xxxx_b & combo2_xxxx_1001_b)); //i=89, 1 48 + assign combo3_0101_1010 = (~(combo2_0101_xxxx_b & combo2_xxxx_1010_b)); //i=90, 1 49 + assign combo3_0101_1110 = (~(combo2_0101_xxxx_b & combo2_xxxx_1110_b)); //i=94, 1 50 + assign combo3_0101_1111 = (~(combo2_0101_xxxx_b & (~f[4]))); //i=95, 1 51 + assign combo3_0110_0011 = (~(combo2_0110_xxxx_b & combo2_xxxx_0011_b)); //i=99, 1 52 + assign combo3_0110_0110 = (~((~combo2_0110))); //i=102, 2 53* + assign combo3_0110_0111 = (~(combo2_0110_xxxx_b & combo2_xxxx_0111_b)); //i=103, 1 54 + assign combo3_0110_1001 = (~(combo2_0110_xxxx_b & combo2_xxxx_1001_b)); //i=105, 1 55 + assign combo3_0110_1010 = (~(combo2_0110_xxxx_b & combo2_xxxx_1010_b)); //i=106, 1 56 + assign combo3_0110_1011 = (~(combo2_0110_xxxx_b & combo2_xxxx_1011_b)); //i=107, 1 57 + assign combo3_0110_1100 = (~(combo2_0110_xxxx_b & combo2_xxxx_1100_b)); //i=108, 1 58 + assign combo3_0110_1101 = (~(combo2_0110_xxxx_b & combo2_xxxx_1101_b)); //i=109, 4 59 + assign combo3_0110_1110 = (~(combo2_0110_xxxx_b & combo2_xxxx_1110_b)); //i=110, 1 60 + assign combo3_0110_1111 = (~(combo2_0110_xxxx_b & (~f[4]))); //i=111, 1 61 + assign combo3_0111_0000 = (~(combo2_0111_xxxx_b)); //i=112, 1 62 + assign combo3_0111_0010 = (~(combo2_0111_xxxx_b & combo2_xxxx_0010_b)); //i=114, 3 63 + assign combo3_0111_0011 = (~(combo2_0111_xxxx_b & combo2_xxxx_0011_b)); //i=115, 1 64 + assign combo3_0111_0110 = (~(combo2_0111_xxxx_b & combo2_xxxx_0110_b)); //i=118, 1 65 + assign combo3_0111_1000 = (~(combo2_0111_xxxx_b & combo2_xxxx_1000_b)); //i=120, 2 66 + assign combo3_0111_1001 = (~(combo2_0111_xxxx_b & combo2_xxxx_1001_b)); //i=121, 1 67 + assign combo3_0111_1100 = (~(combo2_0111_xxxx_b & combo2_xxxx_1100_b)); //i=124, 2 68 + assign combo3_0111_1110 = (~(combo2_0111_xxxx_b & combo2_xxxx_1110_b)); //i=126, 1 69 + assign combo3_0111_1111 = (~(combo2_0111_xxxx_b & (~f[4]))); //i=127, 3 70 + assign combo3_1000_0000 = (~(combo2_1000_xxxx_b)); //i=128, 4 71 + assign combo3_1000_0001 = (~(combo2_1000_xxxx_b & combo2_xxxx_0001_b)); //i=129, 1 72 + assign combo3_1000_0011 = (~(combo2_1000_xxxx_b & combo2_xxxx_0011_b)); //i=131, 2 73 + assign combo3_1000_0110 = (~(combo2_1000_xxxx_b & combo2_xxxx_0110_b)); //i=134, 1 74 + assign combo3_1000_1000 = (~((~combo2_1000))); //i=136, 1 75* + assign combo3_1000_1010 = (~(combo2_1000_xxxx_b & combo2_xxxx_1010_b)); //i=138, 2 76 + assign combo3_1000_1101 = (~(combo2_1000_xxxx_b & combo2_xxxx_1101_b)); //i=141, 1 77 + assign combo3_1000_1110 = (~(combo2_1000_xxxx_b & combo2_xxxx_1110_b)); //i=142, 1 78 + assign combo3_1000_1111 = (~(combo2_1000_xxxx_b & (~f[4]))); //i=143, 1 79 + assign combo3_1001_0000 = (~(combo2_1001_xxxx_b)); //i=144, 1 80 + assign combo3_1001_0010 = (~(combo2_1001_xxxx_b & combo2_xxxx_0010_b)); //i=146, 2 81 + assign combo3_1001_0011 = (~(combo2_1001_xxxx_b & combo2_xxxx_0011_b)); //i=147, 2 82 + assign combo3_1001_0100 = (~(combo2_1001_xxxx_b & combo2_xxxx_0100_b)); //i=148, 2 83 + assign combo3_1001_0111 = (~(combo2_1001_xxxx_b & combo2_xxxx_0111_b)); //i=151, 1 84 + assign combo3_1001_1000 = (~(combo2_1001_xxxx_b & combo2_xxxx_1000_b)); //i=152, 1 85 + assign combo3_1001_1001 = (~((~combo2_1001))); //i=153, 3 86* + assign combo3_1001_1010 = (~(combo2_1001_xxxx_b & combo2_xxxx_1010_b)); //i=154, 2 87 + assign combo3_1001_1100 = (~(combo2_1001_xxxx_b & combo2_xxxx_1100_b)); //i=156, 2 88 + assign combo3_1001_1101 = (~(combo2_1001_xxxx_b & combo2_xxxx_1101_b)); //i=157, 1 89 + assign combo3_1001_1110 = (~(combo2_1001_xxxx_b & combo2_xxxx_1110_b)); //i=158, 1 90 + assign combo3_1001_1111 = (~(combo2_1001_xxxx_b & (~f[4]))); //i=159, 1 91 + assign combo3_1010_0010 = (~(combo2_1010_xxxx_b & combo2_xxxx_0010_b)); //i=162, 1 92 + assign combo3_1010_0100 = (~(combo2_1010_xxxx_b & combo2_xxxx_0100_b)); //i=164, 2 93 + assign combo3_1010_0101 = (~(combo2_1010_xxxx_b & combo2_xxxx_0101_b)); //i=165, 1 94 + assign combo3_1010_0110 = (~(combo2_1010_xxxx_b & combo2_xxxx_0110_b)); //i=166, 1 95 + assign combo3_1010_0111 = (~(combo2_1010_xxxx_b & combo2_xxxx_0111_b)); //i=167, 2 96 + assign combo3_1010_1010 = (~((~combo2_1010))); //i=170, 2 97* + assign combo3_1010_1100 = (~(combo2_1010_xxxx_b & combo2_xxxx_1100_b)); //i=172, 1 98 + assign combo3_1010_1101 = (~(combo2_1010_xxxx_b & combo2_xxxx_1101_b)); //i=173, 1 99 + assign combo3_1010_1110 = (~(combo2_1010_xxxx_b & combo2_xxxx_1110_b)); //i=174, 1 100 + assign combo3_1011_0011 = (~(combo2_1011_xxxx_b & combo2_xxxx_0011_b)); //i=179, 1 101 + assign combo3_1011_0110 = (~(combo2_1011_xxxx_b & combo2_xxxx_0110_b)); //i=182, 2 102 + assign combo3_1011_0111 = (~(combo2_1011_xxxx_b & combo2_xxxx_0111_b)); //i=183, 1 103 + assign combo3_1011_1000 = (~(combo2_1011_xxxx_b & combo2_xxxx_1000_b)); //i=184, 1 104 + assign combo3_1011_1001 = (~(combo2_1011_xxxx_b & combo2_xxxx_1001_b)); //i=185, 1 105 + assign combo3_1011_1010 = (~(combo2_1011_xxxx_b & combo2_xxxx_1010_b)); //i=186, 1 106 + assign combo3_1011_1011 = (~((~combo2_1011))); //i=187, 2 107* + assign combo3_1011_1110 = (~(combo2_1011_xxxx_b & combo2_xxxx_1110_b)); //i=190, 2 108 + assign combo3_1100_0000 = (~(combo2_1100_xxxx_b)); //i=192, 3 109 + assign combo3_1100_0001 = (~(combo2_1100_xxxx_b & combo2_xxxx_0001_b)); //i=193, 1 110 + assign combo3_1100_0011 = (~(combo2_1100_xxxx_b & combo2_xxxx_0011_b)); //i=195, 2 111 + assign combo3_1100_0110 = (~(combo2_1100_xxxx_b & combo2_xxxx_0110_b)); //i=198, 1 112 + assign combo3_1100_0111 = (~(combo2_1100_xxxx_b & combo2_xxxx_0111_b)); //i=199, 2 113 + assign combo3_1100_1010 = (~(combo2_1100_xxxx_b & combo2_xxxx_1010_b)); //i=202, 2 114 + assign combo3_1100_1100 = (~((~combo2_1100))); //i=204, 2 115* + assign combo3_1100_1110 = (~(combo2_1100_xxxx_b & combo2_xxxx_1110_b)); //i=206, 1 116 + assign combo3_1101_0000 = (~(combo2_1101_xxxx_b)); //i=208, 1 117 + assign combo3_1101_0011 = (~(combo2_1101_xxxx_b & combo2_xxxx_0011_b)); //i=211, 2 118 + assign combo3_1101_0101 = (~(combo2_1101_xxxx_b & combo2_xxxx_0101_b)); //i=213, 3 119 + assign combo3_1101_1000 = (~(combo2_1101_xxxx_b & combo2_xxxx_1000_b)); //i=216, 1 120 + assign combo3_1101_1010 = (~(combo2_1101_xxxx_b & combo2_xxxx_1010_b)); //i=218, 2 121 + assign combo3_1101_1011 = (~(combo2_1101_xxxx_b & combo2_xxxx_1011_b)); //i=219, 1 122 + assign combo3_1101_1101 = (~((~combo2_1101))); //i=221, 1 123* + assign combo3_1110_0000 = (~(combo2_1110_xxxx_b)); //i=224, 1 124 + assign combo3_1110_0001 = (~(combo2_1110_xxxx_b & combo2_xxxx_0001_b)); //i=225, 1 125 + assign combo3_1110_0010 = (~(combo2_1110_xxxx_b & combo2_xxxx_0010_b)); //i=226, 1 126 + assign combo3_1110_0011 = (~(combo2_1110_xxxx_b & combo2_xxxx_0011_b)); //i=227, 4 127 + assign combo3_1110_0100 = (~(combo2_1110_xxxx_b & combo2_xxxx_0100_b)); //i=228, 1 128 + assign combo3_1110_0101 = (~(combo2_1110_xxxx_b & combo2_xxxx_0101_b)); //i=229, 1 129 + assign combo3_1110_0110 = (~(combo2_1110_xxxx_b & combo2_xxxx_0110_b)); //i=230, 2 130 + assign combo3_1110_1010 = (~(combo2_1110_xxxx_b & combo2_xxxx_1010_b)); //i=234, 1 131 + assign combo3_1110_1011 = (~(combo2_1110_xxxx_b & combo2_xxxx_1011_b)); //i=235, 1 132 + assign combo3_1111_0000 = (~(f[4])); //i=240, 4 133 + assign combo3_1111_0011 = (~(f[4] & combo2_xxxx_0011_b)); //i=243, 2 134 + assign combo3_1111_0101 = (~(f[4] & combo2_xxxx_0101_b)); //i=245, 1 135 + assign combo3_1111_1000 = (~(f[4] & combo2_xxxx_1000_b)); //i=248, 2 136 + assign combo3_1111_1001 = (~(f[4] & combo2_xxxx_1001_b)); //i=249, 1 137 + assign combo3_1111_1011 = (~(f[4] & combo2_xxxx_1011_b)); //i=251, 1 138 + assign combo3_1111_1100 = (~(f[4] & combo2_xxxx_1100_b)); //i=252, 4 139 + assign combo3_1111_1110 = (~(f[4] & combo2_xxxx_1110_b)); //i=254, 2 140 + + ////####################################### + ////## ESTIMATE VECTORs + ////####################################### + + assign e_00_b[0] = (~(dcd_000 & tiup)); + assign e_00_b[1] = (~(dcd_001 & tiup)); + assign e_00_b[2] = (~(dcd_010 & tiup)); + assign e_00_b[3] = (~(dcd_011 & tiup)); + assign e_00_b[4] = (~(dcd_100 & tiup)); + assign e_00_b[5] = (~(dcd_101 & tiup)); + assign e_00_b[6] = (~(dcd_110 & combo3_1100_0000)); + assign e_00_b[7] = (~(dcd_111 & tidn)); + + assign e[0] = (~(e_00_b[0] & e_00_b[1] & e_00_b[2] & e_00_b[3] & e_00_b[4] & e_00_b[5] & e_00_b[6] & e_00_b[7])); + + assign e_01_b[0] = (~(dcd_000 & tiup)); + assign e_01_b[1] = (~(dcd_001 & tiup)); + assign e_01_b[2] = (~(dcd_010 & combo3_1111_0000)); + assign e_01_b[3] = (~(dcd_011 & tidn)); + assign e_01_b[4] = (~(dcd_100 & tidn)); + assign e_01_b[5] = (~(dcd_101 & tidn)); + assign e_01_b[6] = (~(dcd_110 & combo3_0011_1111)); + assign e_01_b[7] = (~(dcd_111 & tiup)); + + assign e[1] = (~(e_01_b[0] & e_01_b[1] & e_01_b[2] & e_01_b[3] & e_01_b[4] & e_01_b[5] & e_01_b[6] & e_01_b[7])); + + assign e_02_b[0] = (~(dcd_000 & tiup)); + assign e_02_b[1] = (~(dcd_001 & combo3_1000_0000)); + assign e_02_b[2] = (~(dcd_010 & combo3_0000_1111)); + assign e_02_b[3] = (~(dcd_011 & tiup)); + assign e_02_b[4] = (~(dcd_100 & combo3_1000_0000)); + assign e_02_b[5] = (~(dcd_101 & tidn)); + assign e_02_b[6] = (~(dcd_110 & combo3_0011_1111)); + assign e_02_b[7] = (~(dcd_111 & tiup)); + + assign e[2] = (~(e_02_b[0] & e_02_b[1] & e_02_b[2] & e_02_b[3] & e_02_b[4] & e_02_b[5] & e_02_b[6] & e_02_b[7])); + + assign e_03_b[0] = (~(dcd_000 & combo3_1111_1000)); + assign e_03_b[1] = (~(dcd_001 & combo3_0111_1100)); + assign e_03_b[2] = (~(dcd_010 & combo3_0000_1111)); + assign e_03_b[3] = (~(dcd_011 & combo3_1100_0000)); + assign e_03_b[4] = (~(dcd_100 & combo3_0111_1111)); + assign e_03_b[5] = (~(dcd_101 & combo3_1000_0000)); + assign e_03_b[6] = (~(dcd_110 & combo3_0011_1111)); + assign e_03_b[7] = (~(dcd_111 & combo3_1111_0000)); + + assign e[3] = (~(e_03_b[0] & e_03_b[1] & e_03_b[2] & e_03_b[3] & e_03_b[4] & e_03_b[5] & e_03_b[6] & e_03_b[7])); + + assign e_04_b[0] = (~(dcd_000 & combo3_1110_0110)); + assign e_04_b[1] = (~(dcd_001 & combo3_0111_0011)); + assign e_04_b[2] = (~(dcd_010 & combo3_1000_1110)); + assign e_04_b[3] = (~(dcd_011 & combo3_0011_1100)); + assign e_04_b[4] = (~(dcd_100 & combo3_0111_1000)); + assign e_04_b[5] = (~(dcd_101 & combo3_0111_1100)); + assign e_04_b[6] = (~(dcd_110 & combo3_0011_1110)); + assign e_04_b[7] = (~(dcd_111 & combo3_0000_1111)); + + assign e[4] = (~(e_04_b[0] & e_04_b[1] & e_04_b[2] & e_04_b[3] & e_04_b[4] & e_04_b[5] & e_04_b[6] & e_04_b[7])); + + assign e_05_b[0] = (~(dcd_000 & combo3_1101_0101)); + assign e_05_b[1] = (~(dcd_001 & combo3_0110_1011)); + assign e_05_b[2] = (~(dcd_010 & combo3_0110_1101)); + assign e_05_b[3] = (~(dcd_011 & combo3_1011_0011)); + assign e_05_b[4] = (~(dcd_100 & combo3_0110_0110)); + assign e_05_b[5] = (~(dcd_101 & combo3_0110_0011)); + assign e_05_b[6] = (~(dcd_110 & combo3_0011_1001)); + assign e_05_b[7] = (~(dcd_111 & combo3_1100_1110)); + + assign e[5] = (~(e_05_b[0] & e_05_b[1] & e_05_b[2] & e_05_b[3] & e_05_b[4] & e_05_b[5] & e_05_b[6] & e_05_b[7])); + + assign e_06_b[0] = (~(dcd_000 & combo3_1000_0001)); + assign e_06_b[1] = (~(dcd_001 & combo3_1100_0110)); + assign e_06_b[2] = (~(dcd_010 & combo3_0100_1001)); + assign e_06_b[3] = (~(dcd_011 & combo3_0110_1010)); + assign e_06_b[4] = (~(dcd_100 & combo3_1101_0101)); + assign e_06_b[5] = (~(dcd_101 & combo3_0101_1010)); + assign e_06_b[6] = (~(dcd_110 & combo3_1010_0101)); + assign e_06_b[7] = (~(dcd_111 & combo3_0010_1101)); + + assign e[6] = (~(e_06_b[0] & e_06_b[1] & e_06_b[2] & e_06_b[3] & e_06_b[4] & e_06_b[5] & e_06_b[6] & e_06_b[7])); + + assign e_07_b[0] = (~(dcd_000 & combo3_1000_0110)); + assign e_07_b[1] = (~(dcd_001 & combo3_0100_1010)); + assign e_07_b[2] = (~(dcd_010 & combo3_1101_0011)); + assign e_07_b[3] = (~(dcd_011 & combo3_0011_1000)); + assign e_07_b[4] = (~(dcd_100 & combo3_0111_1111)); + assign e_07_b[5] = (~(dcd_101 & combo3_1111_0000)); + assign e_07_b[6] = (~(dcd_110 & combo3_1111_0011)); + assign e_07_b[7] = (~(dcd_111 & combo3_1001_1001)); + + assign e[7] = (~(e_07_b[0] & e_07_b[1] & e_07_b[2] & e_07_b[3] & e_07_b[4] & e_07_b[5] & e_07_b[6] & e_07_b[7])); + + assign e_08_b[0] = (~(dcd_000 & combo3_1000_1010)); + assign e_08_b[1] = (~(dcd_001 & combo3_1001_1111)); + assign e_08_b[2] = (~(dcd_010 & combo3_1001_1010)); + assign e_08_b[3] = (~(dcd_011 & combo3_1010_0100)); + assign e_08_b[4] = (~(dcd_100 & combo3_0111_1111)); + assign e_08_b[5] = (~(dcd_101 & combo3_1111_0011)); + assign e_08_b[6] = (~(dcd_110 & combo3_0011_0100)); + assign e_08_b[7] = (~(dcd_111 & combo3_1010_1010)); + + assign e[8] = (~(e_08_b[0] & e_08_b[1] & e_08_b[2] & e_08_b[3] & e_08_b[4] & e_08_b[5] & e_08_b[6] & e_08_b[7])); + + assign e_09_b[0] = (~(dcd_000 & combo3_1001_0000)); + assign e_09_b[1] = (~(dcd_001 & combo3_0101_1111)); + assign e_09_b[2] = (~(dcd_010 & combo3_1010_1100)); + assign e_09_b[3] = (~(dcd_011 & combo3_0001_0010)); + assign e_09_b[4] = (~(dcd_100 & combo3_0100_0000)); + assign e_09_b[5] = (~(dcd_101 & combo3_0011_0101)); + assign e_09_b[6] = (~(dcd_110 & combo3_0101_1001)); + assign e_09_b[7] = (~(dcd_111 & tiup)); + + assign e[9] = (~(e_09_b[0] & e_09_b[1] & e_09_b[2] & e_09_b[3] & e_09_b[4] & e_09_b[5] & e_09_b[6] & e_09_b[7])); + + assign e_10_b[0] = (~(dcd_000 & combo3_1011_1000)); + assign e_10_b[1] = (~(dcd_001 & combo3_1111_0000)); + assign e_10_b[2] = (~(dcd_010 & combo3_1000_1010)); + assign e_10_b[3] = (~(dcd_011 & combo3_0110_0111)); + assign e_10_b[4] = (~(dcd_100 & combo3_0011_0000)); + assign e_10_b[5] = (~(dcd_101 & combo3_1101_0000)); + assign e_10_b[6] = (~(dcd_110 & combo3_0001_0101)); + assign e_10_b[7] = (~(dcd_111 & combo3_1000_0011)); + + assign e[10] = (~(e_10_b[0] & e_10_b[1] & e_10_b[2] & e_10_b[3] & e_10_b[4] & e_10_b[5] & e_10_b[6] & e_10_b[7])); + + assign e_11_b[0] = (~(dcd_000 & combo3_1000_1101)); + assign e_11_b[1] = (~(dcd_001 & combo3_1001_1001)); + assign e_11_b[2] = (~(dcd_010 & combo3_0101_0001)); + assign e_11_b[3] = (~(dcd_011 & combo3_1011_0111)); + assign e_11_b[4] = (~(dcd_100 & combo3_0110_1001)); + assign e_11_b[5] = (~(dcd_101 & combo3_0111_1000)); + assign e_11_b[6] = (~(dcd_110 & combo3_0011_0001)); + assign e_11_b[7] = (~(dcd_111 & combo3_0110_1101)); + + assign e[11] = (~(e_11_b[0] & e_11_b[1] & e_11_b[2] & e_11_b[3] & e_11_b[4] & e_11_b[5] & e_11_b[6] & e_11_b[7])); + + assign e_12_b[0] = (~(dcd_000 & combo3_1010_0010)); + assign e_12_b[1] = (~(dcd_001 & tidn)); + assign e_12_b[2] = (~(dcd_010 & combo3_1110_0011)); + assign e_12_b[3] = (~(dcd_011 & combo3_1111_0101)); + assign e_12_b[4] = (~(dcd_100 & combo3_0110_0110)); + assign e_12_b[5] = (~(dcd_101 & combo3_0000_1100)); + assign e_12_b[6] = (~(dcd_110 & combo3_0110_1110)); + assign e_12_b[7] = (~(dcd_111 & combo3_0101_0000)); + + assign e[12] = (~(e_12_b[0] & e_12_b[1] & e_12_b[2] & e_12_b[3] & e_12_b[4] & e_12_b[5] & e_12_b[6] & e_12_b[7])); + + assign e_13_b[0] = (~(dcd_000 & combo3_1100_0111)); + assign e_13_b[1] = (~(dcd_001 & combo3_0000_0100)); + assign e_13_b[2] = (~(dcd_010 & combo3_1011_1001)); + assign e_13_b[3] = (~(dcd_011 & combo3_1011_1010)); + assign e_13_b[4] = (~(dcd_100 & combo3_1111_1110)); + assign e_13_b[5] = (~(dcd_101 & combo3_0101_1110)); + assign e_13_b[6] = (~(dcd_110 & combo3_1110_0011)); + assign e_13_b[7] = (~(dcd_111 & combo3_1001_0100)); + + assign e[13] = (~(e_13_b[0] & e_13_b[1] & e_13_b[2] & e_13_b[3] & e_13_b[4] & e_13_b[5] & e_13_b[6] & e_13_b[7])); + + assign e_14_b[0] = (~(dcd_000 & combo3_0111_1001)); + assign e_14_b[1] = (~(dcd_001 & combo3_1111_1011)); + assign e_14_b[2] = (~(dcd_010 & combo3_1010_0111)); + assign e_14_b[3] = (~(dcd_011 & combo3_1000_0000)); + assign e_14_b[4] = (~(dcd_100 & combo3_1110_0001)); + assign e_14_b[5] = (~(dcd_101 & combo3_0110_1101)); + assign e_14_b[6] = (~(dcd_110 & combo3_0000_0001)); + assign e_14_b[7] = (~(dcd_111 & combo3_0001_0111)); + + assign e[14] = (~(e_14_b[0] & e_14_b[1] & e_14_b[2] & e_14_b[3] & e_14_b[4] & e_14_b[5] & e_14_b[6] & e_14_b[7])); + + assign e_15_b[0] = (~(dcd_000 & combo3_0101_0101)); + assign e_15_b[1] = (~(dcd_001 & combo3_1001_1010)); + assign e_15_b[2] = (~(dcd_010 & combo3_0010_1001)); + assign e_15_b[3] = (~(dcd_011 & combo3_0010_1001)); + assign e_15_b[4] = (~(dcd_100 & combo3_1001_1101)); + assign e_15_b[5] = (~(dcd_101 & combo3_1001_1110)); + assign e_15_b[6] = (~(dcd_110 & combo3_1100_1010)); + assign e_15_b[7] = (~(dcd_111 & combo3_1110_0100)); + + assign e[15] = (~(e_15_b[0] & e_15_b[1] & e_15_b[2] & e_15_b[3] & e_15_b[4] & e_15_b[5] & e_15_b[6] & e_15_b[7])); + + assign e_16_b[0] = (~(dcd_000 & combo3_0111_1110)); + assign e_16_b[1] = (~(dcd_001 & combo3_1100_1010)); + assign e_16_b[2] = (~(dcd_010 & combo3_0010_0010)); + assign e_16_b[3] = (~(dcd_011 & combo3_1111_1001)); + assign e_16_b[4] = (~(dcd_100 & combo3_1101_1000)); + assign e_16_b[5] = (~(dcd_101 & combo3_0111_0010)); + assign e_16_b[6] = (~(dcd_110 & combo3_0100_1101)); + assign e_16_b[7] = (~(dcd_111 & combo3_0011_1010)); + + assign e[16] = (~(e_16_b[0] & e_16_b[1] & e_16_b[2] & e_16_b[3] & e_16_b[4] & e_16_b[5] & e_16_b[6] & e_16_b[7])); + + assign e_17_b[0] = (~(dcd_000 & combo3_0111_0010)); + assign e_17_b[1] = (~(dcd_001 & combo3_1010_1110)); + assign e_17_b[2] = (~(dcd_010 & combo3_1110_0010)); + assign e_17_b[3] = (~(dcd_011 & combo3_0100_0110)); + assign e_17_b[4] = (~(dcd_100 & combo3_1101_0011)); + assign e_17_b[5] = (~(dcd_101 & combo3_1000_1111)); + assign e_17_b[6] = (~(dcd_110 & combo3_0000_1101)); + assign e_17_b[7] = (~(dcd_111 & combo3_1001_1100)); + + assign e[17] = (~(e_17_b[0] & e_17_b[1] & e_17_b[2] & e_17_b[3] & e_17_b[4] & e_17_b[5] & e_17_b[6] & e_17_b[7])); + + assign e_18_b[0] = (~(dcd_000 & combo3_0001_0100)); + assign e_18_b[1] = (~(dcd_001 & combo3_0011_1000)); + assign e_18_b[2] = (~(dcd_010 & combo3_0101_0001)); + assign e_18_b[3] = (~(dcd_011 & combo3_0001_0001)); + assign e_18_b[4] = (~(dcd_100 & combo3_0010_0110)); + assign e_18_b[5] = (~(dcd_101 & combo3_0011_0001)); + assign e_18_b[6] = (~(dcd_110 & combo3_0111_0110)); + assign e_18_b[7] = (~(dcd_111 & combo3_1001_1100)); + + assign e[18] = (~(e_18_b[0] & e_18_b[1] & e_18_b[2] & e_18_b[3] & e_18_b[4] & e_18_b[5] & e_18_b[6] & e_18_b[7])); + + assign e_19_b[0] = (~(dcd_000 & tiup)); + assign e_19_b[1] = (~(dcd_001 & tiup)); + assign e_19_b[2] = (~(dcd_010 & tiup)); + assign e_19_b[3] = (~(dcd_011 & tiup)); + assign e_19_b[4] = (~(dcd_100 & tiup)); + assign e_19_b[5] = (~(dcd_101 & tiup)); + assign e_19_b[6] = (~(dcd_110 & tiup)); + assign e_19_b[7] = (~(dcd_111 & tiup)); + + assign e[19] = (~(e_19_b[0] & e_19_b[1] & e_19_b[2] & e_19_b[3] & e_19_b[4] & e_19_b[5] & e_19_b[6] & e_19_b[7])); + + ////####################################### + ////## RANGE VECTORs + ////####################################### + + assign r_00_b[0] = (~(dcd_000 & tidn)); + assign r_00_b[1] = (~(dcd_001 & tidn)); + assign r_00_b[2] = (~(dcd_010 & tidn)); + assign r_00_b[3] = (~(dcd_011 & tidn)); + assign r_00_b[4] = (~(dcd_100 & tidn)); + assign r_00_b[5] = (~(dcd_101 & tidn)); + assign r_00_b[6] = (~(dcd_110 & tidn)); + assign r_00_b[7] = (~(dcd_111 & tidn)); + + assign r[0] = (~(r_00_b[0] & r_00_b[1] & r_00_b[2] & r_00_b[3] & r_00_b[4] & r_00_b[5] & r_00_b[6] & r_00_b[7])); + + assign r_01_b[0] = (~(dcd_000 & tiup)); + assign r_01_b[1] = (~(dcd_001 & tiup)); + assign r_01_b[2] = (~(dcd_010 & tiup)); + assign r_01_b[3] = (~(dcd_011 & tiup)); + assign r_01_b[4] = (~(dcd_100 & combo3_1111_1100)); + assign r_01_b[5] = (~(dcd_101 & tidn)); + assign r_01_b[6] = (~(dcd_110 & tidn)); + assign r_01_b[7] = (~(dcd_111 & tidn)); + + assign r[1] = (~(r_01_b[0] & r_01_b[1] & r_01_b[2] & r_01_b[3] & r_01_b[4] & r_01_b[5] & r_01_b[6] & r_01_b[7])); + + assign r_02_b[0] = (~(dcd_000 & tiup)); + assign r_02_b[1] = (~(dcd_001 & combo3_1111_1100)); + assign r_02_b[2] = (~(dcd_010 & tidn)); + assign r_02_b[3] = (~(dcd_011 & tidn)); + assign r_02_b[4] = (~(dcd_100 & combo3_0000_0011)); + assign r_02_b[5] = (~(dcd_101 & tiup)); + assign r_02_b[6] = (~(dcd_110 & tiup)); + assign r_02_b[7] = (~(dcd_111 & tiup)); + + assign r[2] = (~(r_02_b[0] & r_02_b[1] & r_02_b[2] & r_02_b[3] & r_02_b[4] & r_02_b[5] & r_02_b[6] & r_02_b[7])); + + assign r_03_b[0] = (~(dcd_000 & combo3_1111_1100)); + assign r_03_b[1] = (~(dcd_001 & combo3_0000_0011)); + assign r_03_b[2] = (~(dcd_010 & tiup)); + assign r_03_b[3] = (~(dcd_011 & tidn)); + assign r_03_b[4] = (~(dcd_100 & combo3_0000_0011)); + assign r_03_b[5] = (~(dcd_101 & tiup)); + assign r_03_b[6] = (~(dcd_110 & tiup)); + assign r_03_b[7] = (~(dcd_111 & combo3_1110_0000)); + + assign r[3] = (~(r_03_b[0] & r_03_b[1] & r_03_b[2] & r_03_b[3] & r_03_b[4] & r_03_b[5] & r_03_b[6] & r_03_b[7])); + + assign r_04_b[0] = (~(dcd_000 & combo3_1110_0011)); + assign r_04_b[1] = (~(dcd_001 & combo3_1100_0011)); + assign r_04_b[2] = (~(dcd_010 & combo3_1100_0000)); + assign r_04_b[3] = (~(dcd_011 & combo3_1111_1100)); + assign r_04_b[4] = (~(dcd_100 & combo3_0000_0011)); + assign r_04_b[5] = (~(dcd_101 & combo3_1111_1110)); + assign r_04_b[6] = (~(dcd_110 & tidn)); + assign r_04_b[7] = (~(dcd_111 & combo3_0001_1111)); + + assign r[4] = (~(r_04_b[0] & r_04_b[1] & r_04_b[2] & r_04_b[3] & r_04_b[4] & r_04_b[5] & r_04_b[6] & r_04_b[7])); + + assign r_05_b[0] = (~(dcd_000 & combo3_1001_0011)); + assign r_05_b[1] = (~(dcd_001 & combo3_0010_0011)); + assign r_05_b[2] = (~(dcd_010 & combo3_0011_1000)); + assign r_05_b[3] = (~(dcd_011 & combo3_1110_0011)); + assign r_05_b[4] = (~(dcd_100 & combo3_1100_0011)); + assign r_05_b[5] = (~(dcd_101 & combo3_1100_0001)); + assign r_05_b[6] = (~(dcd_110 & combo3_1111_1000)); + assign r_05_b[7] = (~(dcd_111 & combo3_0001_1111)); + + assign r[5] = (~(r_05_b[0] & r_05_b[1] & r_05_b[2] & r_05_b[3] & r_05_b[4] & r_05_b[5] & r_05_b[6] & r_05_b[7])); + + assign r_06_b[0] = (~(dcd_000 & combo3_1101_1010)); + assign r_06_b[1] = (~(dcd_001 & combo3_1001_0010)); + assign r_06_b[2] = (~(dcd_010 & combo3_1010_0100)); + assign r_06_b[3] = (~(dcd_011 & combo3_1001_0011)); + assign r_06_b[4] = (~(dcd_100 & combo3_0011_0011)); + assign r_06_b[5] = (~(dcd_101 & combo3_0011_0001)); + assign r_06_b[6] = (~(dcd_110 & combo3_1100_0111)); + assign r_06_b[7] = (~(dcd_111 & combo3_0001_1110)); + + assign r[6] = (~(r_06_b[0] & r_06_b[1] & r_06_b[2] & r_06_b[3] & r_06_b[4] & r_06_b[5] & r_06_b[6] & r_06_b[7])); + + assign r_07_b[0] = (~(dcd_000 & combo3_0100_1100)); + assign r_07_b[1] = (~(dcd_001 & combo3_0011_1000)); + assign r_07_b[2] = (~(dcd_010 & combo3_0111_0010)); + assign r_07_b[3] = (~(dcd_011 & combo3_0100_1010)); + assign r_07_b[4] = (~(dcd_100 & combo3_1010_1010)); + assign r_07_b[5] = (~(dcd_101 & combo3_1010_1101)); + assign r_07_b[6] = (~(dcd_110 & combo3_0010_0100)); + assign r_07_b[7] = (~(dcd_111 & combo3_1001_1001)); + + assign r[7] = (~(r_07_b[0] & r_07_b[1] & r_07_b[2] & r_07_b[3] & r_07_b[4] & r_07_b[5] & r_07_b[6] & r_07_b[7])); + + assign r_08_b[0] = (~(dcd_000 & combo3_1110_1010)); + assign r_08_b[1] = (~(dcd_001 & combo3_0011_1000)); + assign r_08_b[2] = (~(dcd_010 & combo3_1001_0100)); + assign r_08_b[3] = (~(dcd_011 & combo3_1001_1000)); + assign r_08_b[4] = (~(dcd_100 & tidn)); + assign r_08_b[5] = (~(dcd_101 & combo3_0011_1001)); + assign r_08_b[6] = (~(dcd_110 & combo3_1001_0010)); + assign r_08_b[7] = (~(dcd_111 & combo3_1101_0101)); + + assign r[8] = (~(r_08_b[0] & r_08_b[1] & r_08_b[2] & r_08_b[3] & r_08_b[4] & r_08_b[5] & r_08_b[6] & r_08_b[7])); + + assign r_09_b[0] = (~(dcd_000 & combo3_0010_0001)); + assign r_09_b[1] = (~(dcd_001 & combo3_0011_1001)); + assign r_09_b[2] = (~(dcd_010 & combo3_0011_1110)); + assign r_09_b[3] = (~(dcd_011 & combo3_0101_0110)); + assign r_09_b[4] = (~(dcd_100 & tidn)); + assign r_09_b[5] = (~(dcd_101 & combo3_1101_1010)); + assign r_09_b[6] = (~(dcd_110 & combo3_1011_0110)); + assign r_09_b[7] = (~(dcd_111 & combo3_0111_0000)); + + assign r[9] = (~(r_09_b[0] & r_09_b[1] & r_09_b[2] & r_09_b[3] & r_09_b[4] & r_09_b[5] & r_09_b[6] & r_09_b[7])); + + assign r_10_b[0] = (~(dcd_000 & combo3_0101_0011)); + assign r_10_b[1] = (~(dcd_001 & combo3_1011_1011)); + assign r_10_b[2] = (~(dcd_010 & combo3_1011_0110)); + assign r_10_b[3] = (~(dcd_011 & combo3_1101_1101)); + assign r_10_b[4] = (~(dcd_100 & combo3_1000_0011)); + assign r_10_b[5] = (~(dcd_101 & combo3_0110_1111)); + assign r_10_b[6] = (~(dcd_110 & combo3_1110_0101)); + assign r_10_b[7] = (~(dcd_111 & combo3_0100_1000)); + + assign r[10] = (~(r_10_b[0] & r_10_b[1] & r_10_b[2] & r_10_b[3] & r_10_b[4] & r_10_b[5] & r_10_b[6] & r_10_b[7])); + + assign r_11_b[0] = (~(dcd_000 & combo3_0010_1110)); + assign r_11_b[1] = (~(dcd_001 & combo3_0000_1011)); + assign r_11_b[2] = (~(dcd_010 & combo3_1110_1011)); + assign r_11_b[3] = (~(dcd_011 & combo3_1010_0111)); + assign r_11_b[4] = (~(dcd_100 & combo3_0100_0101)); + assign r_11_b[5] = (~(dcd_101 & combo3_1100_1100)); + assign r_11_b[6] = (~(dcd_110 & combo3_0110_1100)); + assign r_11_b[7] = (~(dcd_111 & combo3_0010_0110)); + + assign r[11] = (~(r_11_b[0] & r_11_b[1] & r_11_b[2] & r_11_b[3] & r_11_b[4] & r_11_b[5] & r_11_b[6] & r_11_b[7])); + + assign r_12_b[0] = (~(dcd_000 & combo3_0011_1100)); + assign r_12_b[1] = (~(dcd_001 & combo3_1010_0110)); + assign r_12_b[2] = (~(dcd_010 & combo3_1000_1000)); + assign r_12_b[3] = (~(dcd_011 & combo3_0010_1101)); + assign r_12_b[4] = (~(dcd_100 & combo3_0011_1001)); + assign r_12_b[5] = (~(dcd_101 & combo3_1101_1011)); + assign r_12_b[6] = (~(dcd_110 & combo3_1011_1011)); + assign r_12_b[7] = (~(dcd_111 & combo3_1100_1100)); + + assign r[12] = (~(r_12_b[0] & r_12_b[1] & r_12_b[2] & r_12_b[3] & r_12_b[4] & r_12_b[5] & r_12_b[6] & r_12_b[7])); + + assign r_13_b[0] = (~(dcd_000 & combo3_1001_0111)); + assign r_13_b[1] = (~(dcd_001 & combo3_0001_0101)); + assign r_13_b[2] = (~(dcd_010 & combo3_1011_1110)); + assign r_13_b[3] = (~(dcd_011 & combo3_1110_0110)); + assign r_13_b[4] = (~(dcd_100 & combo3_0000_1111)); + assign r_13_b[5] = (~(dcd_101 & combo3_0001_1000)); + assign r_13_b[6] = (~(dcd_110 & combo3_1011_1110)); + assign r_13_b[7] = (~(dcd_111 & combo3_0110_1101)); + + assign r[13] = (~(r_13_b[0] & r_13_b[1] & r_13_b[2] & r_13_b[3] & r_13_b[4] & r_13_b[5] & r_13_b[6] & r_13_b[7])); + + assign r_14_b[0] = (~(dcd_000 & tidn)); + assign r_14_b[1] = (~(dcd_001 & tidn)); + assign r_14_b[2] = (~(dcd_010 & tidn)); + assign r_14_b[3] = (~(dcd_011 & tidn)); + assign r_14_b[4] = (~(dcd_100 & tidn)); + assign r_14_b[5] = (~(dcd_101 & tidn)); + assign r_14_b[6] = (~(dcd_110 & tidn)); + assign r_14_b[7] = (~(dcd_111 & tidn)); + + assign r[14] = (~(r_14_b[0] & r_14_b[1] & r_14_b[2] & r_14_b[3] & r_14_b[4] & r_14_b[5] & r_14_b[6] & r_14_b[7])); + + ////####################################### + ////## RENUMBERING OUTPUTS + ////####################################### + + assign est[1:20] = e[0:19]; // renumbering + assign rng[6:20] = r[0:14]; // renumbering + +endmodule diff --git a/dev/verilog/work/iuq.v b/dev/verilog/work/iuq.v new file mode 100755 index 0000000..bb91e02 --- /dev/null +++ b/dev/verilog/work/iuq.v @@ -0,0 +1,3357 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//******************************************************************** +//* +//* TITLE: Instruction Buffer +//* +//* NAME: iuq.v +//* +//********************************************************************* + +(* recursive_synthesis="0" *) +`include "tri_a2o.vh" + +module iuq( + (* pin_data="PIN_FUNCTION=/G_CLK/" *) + input [0:`NCLK_WIDTH-1] nclk, + input pc_iu_sg_3, + input pc_iu_fce_3, + input pc_iu_func_slp_sl_thold_3, // was: chip_b_sl_2_thold_3_b + input pc_iu_func_nsl_thold_3, // added for custom cam + input pc_iu_cfg_slp_sl_thold_3, // for boot config slats + input pc_iu_regf_slp_sl_thold_3, + input pc_iu_func_sl_thold_3, + input pc_iu_time_sl_thold_3, + input pc_iu_abst_sl_thold_3, + input pc_iu_abst_slp_sl_thold_3, + input pc_iu_repr_sl_thold_3, + input pc_iu_ary_nsl_thold_3, + input pc_iu_ary_slp_nsl_thold_3, + input pc_iu_func_slp_nsl_thold_3, + input pc_iu_bolt_sl_thold_3, + input clkoff_b, + input act_dis, + input tc_ac_ccflush_dc, + input tc_ac_scan_dis_dc_b, + input tc_ac_scan_diag_dc, + input d_mode, + input delay_lclkr, + input mpw1_b, + input mpw2_b, + input scan_in, + output scan_out, + + input [0:3] pc_iu_abist_dcomp_g6t_2r, + input [0:3] pc_iu_abist_di_0, + input [0:3] pc_iu_abist_di_g6t_2r, + input pc_iu_abist_ena_dc, + input [0:1] pc_iu_abist_g6t_bw, + input pc_iu_abist_g6t_r_wb, + input pc_iu_abist_g8t1p_renb_0, + input pc_iu_abist_g8t_bw_0, + input pc_iu_abist_g8t_bw_1, + input [0:3] pc_iu_abist_g8t_dcomp, + input pc_iu_abist_g8t_wenb, + input [1:9] pc_iu_abist_raddr_0, + input pc_iu_abist_raw_dc_b, + input [3:9] pc_iu_abist_waddr_0, + input pc_iu_abist_wl512_comp_ena, + input pc_iu_abist_wl128_comp_ena, + input an_ac_lbist_ary_wrt_thru_dc, + input an_ac_lbist_en_dc, + input an_ac_atpg_en_dc, + input an_ac_grffence_en_dc, + + input pc_iu_bo_enable_3, // bolt-on ABIST + input pc_iu_bo_reset, + input pc_iu_bo_unload, + input pc_iu_bo_repair, + input pc_iu_bo_shdata, + input [0:4] pc_iu_bo_select, + output [0:4] iu_pc_bo_fail, + output [0:4] iu_pc_bo_diagout, + + output [0:`THREADS-1] iu_pc_err_ucode_illegal, + + // Cache inject + output iu_pc_err_icache_parity, + output iu_pc_err_icachedir_parity, + output iu_pc_err_icachedir_multihit, + output iu_pc_err_ierat_multihit, + output iu_pc_err_ierat_parity, + input pc_iu_inj_icache_parity, + input pc_iu_inj_icachedir_parity, + input pc_iu_inj_icachedir_multihit, + input pc_iu_init_reset, + + // spr ring + input iu_slowspr_val_in, + input iu_slowspr_rw_in, + input [0:1] iu_slowspr_etid_in, + input [0:9] iu_slowspr_addr_in, + input [64-`GPR_WIDTH:63] iu_slowspr_data_in, + input iu_slowspr_done_in, + output iu_slowspr_val_out, + output iu_slowspr_rw_out, + output [0:1] iu_slowspr_etid_out, + output [0:9] iu_slowspr_addr_out, + output [64-`GPR_WIDTH:63] iu_slowspr_data_out, + output iu_slowspr_done_out, + + input [0:`THREADS-1] xu_iu_msr_ucle, + input [0:`THREADS-1] xu_iu_msr_de, + input [0:`THREADS-1] xu_iu_msr_pr, + input [0:`THREADS-1] xu_iu_msr_is, + input [0:`THREADS-1] xu_iu_msr_cm, + input [0:`THREADS-1] xu_iu_msr_gs, + input [0:`THREADS-1] xu_iu_msr_me, + input [0:`THREADS-1] xu_iu_dbcr0_edm, + input [0:`THREADS-1] xu_iu_dbcr0_idm, + input [0:`THREADS-1] xu_iu_dbcr0_icmp, + input [0:`THREADS-1] xu_iu_dbcr0_brt, + input [0:`THREADS-1] xu_iu_dbcr0_irpt, + input [0:`THREADS-1] xu_iu_dbcr0_trap, + input [0:`THREADS-1] xu_iu_iac1_en, + input [0:`THREADS-1] xu_iu_iac2_en, + input [0:`THREADS-1] xu_iu_iac3_en, + input [0:`THREADS-1] xu_iu_iac4_en, + input [0:1] xu_iu_t0_dbcr0_dac1, + input [0:1] xu_iu_t0_dbcr0_dac2, + input [0:1] xu_iu_t0_dbcr0_dac3, + input [0:1] xu_iu_t0_dbcr0_dac4, +`ifndef THREADS1 + input [0:1] xu_iu_t1_dbcr0_dac1, + input [0:1] xu_iu_t1_dbcr0_dac2, + input [0:1] xu_iu_t1_dbcr0_dac3, + input [0:1] xu_iu_t1_dbcr0_dac4, +`endif + input [0:`THREADS-1] xu_iu_dbcr0_ret, + input [0:`THREADS-1] xu_iu_dbcr1_iac12m, + input [0:`THREADS-1] xu_iu_dbcr1_iac34m, + input [0:`THREADS-1] lq_iu_spr_dbcr3_ivc, + input [0:`THREADS-1] xu_iu_epcr_extgs, + input [0:`THREADS-1] xu_iu_epcr_dtlbgs, + input [0:`THREADS-1] xu_iu_epcr_itlbgs, + input [0:`THREADS-1] xu_iu_epcr_dsigs, + input [0:`THREADS-1] xu_iu_epcr_isigs, + input [0:`THREADS-1] xu_iu_epcr_duvd, + input [0:`THREADS-1] xu_iu_epcr_dgtmi, + input [0:`THREADS-1] xu_iu_epcr_icm, + input [0:`THREADS-1] xu_iu_epcr_gicm, + input [0:`THREADS-1] xu_iu_msrp_uclep, + input xu_iu_hid_mmu_mode, + input xu_iu_spr_ccr2_en_dcr, + input xu_iu_spr_ccr2_ifrat, + input [0:8] xu_iu_spr_ccr2_ifratsc, // 0:4: wimge, 5:8: u0:3 + input xu_iu_spr_ccr2_ucode_dis, + input xu_iu_xucr4_mmu_mchk, + + output iu_mm_ierat_req, + output iu_mm_ierat_req_nonspec, + output [0:51] iu_mm_ierat_epn, + output [0:`THREADS-1] iu_mm_ierat_thdid, + output [0:3] iu_mm_ierat_state, + output [0:13] iu_mm_ierat_tid, + output [0:`THREADS-1] iu_mm_ierat_flush, + output [0:`THREADS-1] iu_mm_perf_itlb, + + input [0:4] mm_iu_ierat_rel_val, + input [0:131] mm_iu_ierat_rel_data, + input [0:`THREADS-1] mm_iu_ierat_pt_fault, + input [0:`THREADS-1] mm_iu_ierat_lrat_miss, + input [0:`THREADS-1] mm_iu_ierat_tlb_inelig, + input [0:`THREADS-1] mm_iu_tlb_multihit_err, + input [0:`THREADS-1] mm_iu_tlb_par_err, + input [0:`THREADS-1] mm_iu_lru_par_err, + input [0:`THREADS-1] mm_iu_tlb_miss, + + input [0:13] mm_iu_t0_ierat_pid, + input [0:19] mm_iu_t0_ierat_mmucr0, +`ifndef THREADS1 + input [0:13] mm_iu_t1_ierat_pid, + input [0:19] mm_iu_t1_ierat_mmucr0, +`endif + output [0:17] iu_mm_ierat_mmucr0, + output [0:`THREADS-1] iu_mm_ierat_mmucr0_we, + input [0:8] mm_iu_ierat_mmucr1, + output [0:3] iu_mm_ierat_mmucr1, + output iu_mm_ierat_mmucr1_we, + + input mm_iu_ierat_snoop_coming, + input mm_iu_ierat_snoop_val, + input [0:25] mm_iu_ierat_snoop_attr, + input [(62-`EFF_IFAR_ARCH):51] mm_iu_ierat_snoop_vpn, + output iu_mm_ierat_snoop_ack, + + output [0:`THREADS-1] iu_mm_hold_ack, + input [0:`THREADS-1] mm_iu_hold_req, + input [0:`THREADS-1] mm_iu_flush_req, + input [0:`THREADS-1] mm_iu_hold_done, + + output [0:`THREADS-1] iu_mm_bus_snoop_hold_ack, + input [0:`THREADS-1] mm_iu_bus_snoop_hold_req, + input [0:`THREADS-1] mm_iu_bus_snoop_hold_done, + + input [0:`THREADS-1] mm_iu_tlbi_complete, + + input mm_iu_tlbwe_binv, + + output [0:5] cp_mm_except_taken_t0, +`ifndef THREADS1 + output [0:5] cp_mm_except_taken_t1, +`endif + + input an_ac_back_inv, + input [64-`REAL_IFAR_WIDTH:57] an_ac_back_inv_addr, + input an_ac_back_inv_target, // connect to bit(0) + + output [0:`THREADS-1] iu_lq_request, + output [0:1] iu_lq_ctag, + output [64-`REAL_IFAR_WIDTH:59] iu_lq_ra, + output [0:4] iu_lq_wimge, + output [0:3] iu_lq_userdef, + + input an_ac_reld_data_vld, + input [0:4] an_ac_reld_core_tag, + input [58:59] an_ac_reld_qw, + input [0:127] an_ac_reld_data, + input an_ac_reld_ecc_err, + input an_ac_reld_ecc_err_ue, + + output iu_mm_lmq_empty, + output [0:`THREADS-1] iu_xu_icache_quiesce, + output [0:`THREADS-1] iu_pc_icache_quiesce, + + output iu_pc_err_btb_parity, + + + //---------------------------------------------------------------- + // Interface to reservation station - Completion is snooping also + //---------------------------------------------------------------- + output iu_rv_iu6_t0_i0_vld, + output iu_rv_iu6_t0_i0_act, + output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i0_itag, + output [0:2] iu_rv_iu6_t0_i0_ucode, + output [0:`UCODE_ENTRIES_ENC-1] iu_rv_iu6_t0_i0_ucode_cnt, + output iu_rv_iu6_t0_i0_2ucode, + output iu_rv_iu6_t0_i0_rte_lq, + output iu_rv_iu6_t0_i0_rte_sq, + output iu_rv_iu6_t0_i0_rte_fx0, + output iu_rv_iu6_t0_i0_rte_fx1, + output iu_rv_iu6_t0_i0_rte_axu0, + output iu_rv_iu6_t0_i0_rte_axu1, + output iu_rv_iu6_t0_i0_ord, + output iu_rv_iu6_t0_i0_cord, + output iu_rv_iu6_t0_i0_bta_val, + output [0:19] iu_rv_iu6_t0_i0_fusion, + output iu_rv_iu6_t0_i0_spec, + output iu_rv_iu6_t0_i0_isload, + output iu_rv_iu6_t0_i0_isstore, + output [0:31] iu_rv_iu6_t0_i0_instr, + output [62-`EFF_IFAR_WIDTH:61] iu_rv_iu6_t0_i0_ifar, + output [62-`EFF_IFAR_WIDTH:61] iu_rv_iu6_t0_i0_bta, + output iu_rv_iu6_t0_i0_br_pred, + output iu_rv_iu6_t0_i0_bh_update, + output [0:17] iu_rv_iu6_t0_i0_gshare, + output [0:2] iu_rv_iu6_t0_i0_ls_ptr, + output [0:3] iu_rv_iu6_t0_i0_ilat, + output iu_rv_iu6_t0_i0_t1_v, + output [0:2] iu_rv_iu6_t0_i0_t1_t, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_t1_p, + output iu_rv_iu6_t0_i0_t2_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_t2_p, + output [0:2] iu_rv_iu6_t0_i0_t2_t, + output iu_rv_iu6_t0_i0_t3_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_t3_p, + output [0:2] iu_rv_iu6_t0_i0_t3_t, + output iu_rv_iu6_t0_i0_s1_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_s1_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_s1_p, + output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i0_s1_itag, + output [0:2] iu_rv_iu6_t0_i0_s1_t, + output iu_rv_iu6_t0_i0_s2_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_s2_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_s2_p, + output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i0_s2_itag, + output [0:2] iu_rv_iu6_t0_i0_s2_t, + output iu_rv_iu6_t0_i0_s3_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_s3_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_s3_p, + output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i0_s3_itag, + output [0:2] iu_rv_iu6_t0_i0_s3_t, + + output iu_rv_iu6_t0_i1_vld, + output iu_rv_iu6_t0_i1_act, + output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i1_itag, + output [0:2] iu_rv_iu6_t0_i1_ucode, + output [0:`UCODE_ENTRIES_ENC-1] iu_rv_iu6_t0_i1_ucode_cnt, + output iu_rv_iu6_t0_i1_rte_lq, + output iu_rv_iu6_t0_i1_rte_sq, + output iu_rv_iu6_t0_i1_rte_fx0, + output iu_rv_iu6_t0_i1_rte_fx1, + output iu_rv_iu6_t0_i1_rte_axu0, + output iu_rv_iu6_t0_i1_rte_axu1, + output iu_rv_iu6_t0_i1_ord, + output iu_rv_iu6_t0_i1_cord, + output iu_rv_iu6_t0_i1_bta_val, + output [0:19] iu_rv_iu6_t0_i1_fusion, + output iu_rv_iu6_t0_i1_spec, + output iu_rv_iu6_t0_i1_isload, + output iu_rv_iu6_t0_i1_isstore, + output [0:31] iu_rv_iu6_t0_i1_instr, + output [62-`EFF_IFAR_WIDTH:61] iu_rv_iu6_t0_i1_ifar, + output [62-`EFF_IFAR_WIDTH:61] iu_rv_iu6_t0_i1_bta, + output iu_rv_iu6_t0_i1_br_pred, + output iu_rv_iu6_t0_i1_bh_update, + output [0:17] iu_rv_iu6_t0_i1_gshare, + output [0:2] iu_rv_iu6_t0_i1_ls_ptr, + output [0:3] iu_rv_iu6_t0_i1_ilat, + output iu_rv_iu6_t0_i1_t1_v, + output [0:2] iu_rv_iu6_t0_i1_t1_t, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_t1_p, + output iu_rv_iu6_t0_i1_t2_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_t2_p, + output [0:2] iu_rv_iu6_t0_i1_t2_t, + output iu_rv_iu6_t0_i1_t3_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_t3_p, + output [0:2] iu_rv_iu6_t0_i1_t3_t, + output iu_rv_iu6_t0_i1_s1_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_s1_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_s1_p, + output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i1_s1_itag, + output [0:2] iu_rv_iu6_t0_i1_s1_t, + output iu_rv_iu6_t0_i1_s1_dep_hit, + output iu_rv_iu6_t0_i1_s2_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_s2_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_s2_p, + output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i1_s2_itag, + output [0:2] iu_rv_iu6_t0_i1_s2_t, + output iu_rv_iu6_t0_i1_s2_dep_hit, + output iu_rv_iu6_t0_i1_s3_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_s3_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_s3_p, + output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i1_s3_itag, + output [0:2] iu_rv_iu6_t0_i1_s3_t, + output iu_rv_iu6_t0_i1_s3_dep_hit, + +`ifndef THREADS1 + //---------------------------------------------------------------- + // Interface to reservation station - Completion is snooping also + //---------------------------------------------------------------- + output iu_rv_iu6_t1_i0_vld, + output iu_rv_iu6_t1_i0_act, + output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i0_itag, + output [0:2] iu_rv_iu6_t1_i0_ucode, + output [0:`UCODE_ENTRIES_ENC-1] iu_rv_iu6_t1_i0_ucode_cnt, + output iu_rv_iu6_t1_i0_2ucode, + output iu_rv_iu6_t1_i0_rte_lq, + output iu_rv_iu6_t1_i0_rte_sq, + output iu_rv_iu6_t1_i0_rte_fx0, + output iu_rv_iu6_t1_i0_rte_fx1, + output iu_rv_iu6_t1_i0_rte_axu0, + output iu_rv_iu6_t1_i0_rte_axu1, + output iu_rv_iu6_t1_i0_ord, + output iu_rv_iu6_t1_i0_cord, + output iu_rv_iu6_t1_i0_bta_val, + output [0:19] iu_rv_iu6_t1_i0_fusion, + output iu_rv_iu6_t1_i0_spec, + output iu_rv_iu6_t1_i0_isload, + output iu_rv_iu6_t1_i0_isstore, + output [0:31] iu_rv_iu6_t1_i0_instr, + output [62-`EFF_IFAR_WIDTH:61] iu_rv_iu6_t1_i0_ifar, + output [62-`EFF_IFAR_WIDTH:61] iu_rv_iu6_t1_i0_bta, + output iu_rv_iu6_t1_i0_br_pred, + output iu_rv_iu6_t1_i0_bh_update, + output [0:17] iu_rv_iu6_t1_i0_gshare, + output [0:2] iu_rv_iu6_t1_i0_ls_ptr, + output [0:3] iu_rv_iu6_t1_i0_ilat, + output iu_rv_iu6_t1_i0_t1_v, + output [0:2] iu_rv_iu6_t1_i0_t1_t, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_t1_p, + output iu_rv_iu6_t1_i0_t2_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_t2_p, + output [0:2] iu_rv_iu6_t1_i0_t2_t, + output iu_rv_iu6_t1_i0_t3_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_t3_p, + output [0:2] iu_rv_iu6_t1_i0_t3_t, + output iu_rv_iu6_t1_i0_s1_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_s1_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_s1_p, + output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i0_s1_itag, + output [0:2] iu_rv_iu6_t1_i0_s1_t, + output iu_rv_iu6_t1_i0_s2_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_s2_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_s2_p, + output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i0_s2_itag, + output [0:2] iu_rv_iu6_t1_i0_s2_t, + output iu_rv_iu6_t1_i0_s3_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_s3_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_s3_p, + output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i0_s3_itag, + output [0:2] iu_rv_iu6_t1_i0_s3_t, + + output iu_rv_iu6_t1_i1_vld, + output iu_rv_iu6_t1_i1_act, + output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i1_itag, + output [0:2] iu_rv_iu6_t1_i1_ucode, + output [0:`UCODE_ENTRIES_ENC-1] iu_rv_iu6_t1_i1_ucode_cnt, + output iu_rv_iu6_t1_i1_rte_lq, + output iu_rv_iu6_t1_i1_rte_sq, + output iu_rv_iu6_t1_i1_rte_fx0, + output iu_rv_iu6_t1_i1_rte_fx1, + output iu_rv_iu6_t1_i1_rte_axu0, + output iu_rv_iu6_t1_i1_rte_axu1, + output iu_rv_iu6_t1_i1_ord, + output iu_rv_iu6_t1_i1_cord, + output iu_rv_iu6_t1_i1_bta_val, + output [0:19] iu_rv_iu6_t1_i1_fusion, + output iu_rv_iu6_t1_i1_spec, + output iu_rv_iu6_t1_i1_isload, + output iu_rv_iu6_t1_i1_isstore, + output [0:31] iu_rv_iu6_t1_i1_instr, + output [62-`EFF_IFAR_WIDTH:61] iu_rv_iu6_t1_i1_ifar, + output [62-`EFF_IFAR_WIDTH:61] iu_rv_iu6_t1_i1_bta, + output iu_rv_iu6_t1_i1_br_pred, + output iu_rv_iu6_t1_i1_bh_update, + output [0:17] iu_rv_iu6_t1_i1_gshare, + output [0:2] iu_rv_iu6_t1_i1_ls_ptr, + output [0:3] iu_rv_iu6_t1_i1_ilat, + output iu_rv_iu6_t1_i1_t1_v, + output [0:2] iu_rv_iu6_t1_i1_t1_t, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_t1_p, + output iu_rv_iu6_t1_i1_t2_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_t2_p, + output [0:2] iu_rv_iu6_t1_i1_t2_t, + output iu_rv_iu6_t1_i1_t3_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_t3_p, + output [0:2] iu_rv_iu6_t1_i1_t3_t, + output iu_rv_iu6_t1_i1_s1_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_s1_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_s1_p, + output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i1_s1_itag, + output [0:2] iu_rv_iu6_t1_i1_s1_t, + output iu_rv_iu6_t1_i1_s1_dep_hit, + output iu_rv_iu6_t1_i1_s2_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_s2_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_s2_p, + output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i1_s2_itag, + output [0:2] iu_rv_iu6_t1_i1_s2_t, + output iu_rv_iu6_t1_i1_s2_dep_hit, + output iu_rv_iu6_t1_i1_s3_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_s3_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_s3_p, + output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i1_s3_itag, + output [0:2] iu_rv_iu6_t1_i1_s3_t, + output iu_rv_iu6_t1_i1_s3_dep_hit, +`endif + + // XER read bus to RF for store conditionals + output [0:`XER_POOL_ENC-1] iu_rf_t0_xer_p, +`ifndef THREADS1 + output [0:`XER_POOL_ENC-1] iu_rf_t1_xer_p, +`endif + + // Credit Interface with IU + input [0:`THREADS-1] rv_iu_fx0_credit_free, + input [0:`THREADS-1] rv_iu_fx1_credit_free, + input [0:`THREADS-1] axu0_iu_credit_free, + input [0:`THREADS-1] axu1_iu_credit_free, + + // LQ Instruction Executed + input [0:`THREADS-1] lq0_iu_execute_vld, + input [0:`ITAG_SIZE_ENC-1] lq0_iu_itag, + input lq0_iu_n_flush, + input lq0_iu_np1_flush, + input lq0_iu_dacr_type, + input [0:3] lq0_iu_dacrw, + input [0:31] lq0_iu_instr, + input [64-`GPR_WIDTH:63] lq0_iu_eff_addr, + input lq0_iu_exception_val, + input [0:5] lq0_iu_exception, + input lq0_iu_flush2ucode, + input lq0_iu_flush2ucode_type, + input [0:`THREADS-1] lq0_iu_recirc_val, + input [0:`THREADS-1] lq0_iu_dear_val, + + input [0:`THREADS-1] lq1_iu_execute_vld, + input [0:`ITAG_SIZE_ENC-1] lq1_iu_itag, + input lq1_iu_n_flush, + input lq1_iu_np1_flush, + input lq1_iu_exception_val, + input [0:5] lq1_iu_exception, + input lq1_iu_dacr_type, + input [0:3] lq1_iu_dacrw, + input [0:3] lq1_iu_perf_events, + + input [0:`THREADS-1] lq_iu_credit_free, + input [0:`THREADS-1] sq_iu_credit_free, + + // Interface IU ucode + input [0:`THREADS-1] xu_iu_ucode_xer_val, + input [57:63] xu_iu_ucode_xer, + + // Complete iTag + output [0:`THREADS-1] iu_lq_i0_completed, + output [0:`THREADS-1] iu_lq_i1_completed, + output [0:`ITAG_SIZE_ENC-1] iu_lq_t0_i0_completed_itag, + output [0:`ITAG_SIZE_ENC-1] iu_lq_t0_i1_completed_itag, +`ifndef THREADS1 + output [0:`ITAG_SIZE_ENC-1] iu_lq_t1_i0_completed_itag, + output [0:`ITAG_SIZE_ENC-1] iu_lq_t1_i1_completed_itag, +`endif + output [0:`THREADS-1] iu_lq_recirc_val, + + // ICBI Interface to IU + input [0:`THREADS-1] lq_iu_icbi_val, + input [64-`REAL_IFAR_WIDTH:57] lq_iu_icbi_addr, + output [0:`THREADS-1] iu_lq_icbi_complete, + input lq_iu_ici_val, + output iu_lq_spr_iucr0_icbi_ack, + + // BR Instruction Executed + input [0:`THREADS-1] br_iu_execute_vld, + input [0:`ITAG_SIZE_ENC-1] br_iu_itag, + input [62-`EFF_IFAR_ARCH:61] br_iu_bta, + input br_iu_taken, + input [0:`THREADS-1] br_iu_redirect, + input [0:3] br_iu_perf_events, + + //br unit repairs + input [0:17] br_iu_gshare, + input [0:2] br_iu_ls_ptr, + input [62-`EFF_IFAR_WIDTH:61] br_iu_ls_data, + input br_iu_ls_update, + + // XU0 Instruction Executed + input [0:`THREADS-1] xu_iu_execute_vld, + input [0:`ITAG_SIZE_ENC-1] xu_iu_itag, + input xu_iu_n_flush, + input xu_iu_np1_flush, + input xu_iu_flush2ucode, + input xu_iu_exception_val, + input [0:4] xu_iu_exception, + input [0:`THREADS-1] xu_iu_mtiar, + input [62-`EFF_IFAR_ARCH:61] xu_iu_bta, + input [0:3] xu_iu_perf_events, + + // XU1 Instruction Executed + input [0:`THREADS-1] xu1_iu_execute_vld, + input [0:`ITAG_SIZE_ENC-1] xu1_iu_itag, + + // XU IERAT interface + input [0:`THREADS-1] xu_iu_val, + input [0:`THREADS-1] xu_iu_pri_val, + input [0:2] xu_iu_pri, + input xu_iu_is_eratre, + input xu_iu_is_eratwe, + input xu_iu_is_eratsx, + input xu_iu_is_eratilx, + input [0:1] xu_iu_ws, + input [0:3] xu_iu_ra_entry, + input [64-`GPR_WIDTH:51] xu_iu_rb, + input [64-`GPR_WIDTH:63] xu_iu_rs_data, + output iu_xu_ord_read_done, + output iu_xu_ord_write_done, + output iu_xu_ord_par_err, + output iu_xu_ord_n_flush_req, + output [64-`GPR_WIDTH:63] iu_xu_ex5_data, + + // AXU0 Instruction Executed + input [0:`THREADS-1] axu0_iu_execute_vld, + input [0:`ITAG_SIZE_ENC-1] axu0_iu_itag, + input axu0_iu_n_flush, + input axu0_iu_np1_flush, + input axu0_iu_n_np1_flush, + input [0:3] axu0_iu_exception, + input axu0_iu_flush2ucode, + input axu0_iu_flush2ucode_type, + input axu0_iu_exception_val, + input [0:`THREADS-1] axu0_iu_async_fex, + input [0:3] axu0_iu_perf_events, + + // AXU1 Instruction Executed + input [0:`THREADS-1] axu1_iu_execute_vld, + input [0:`ITAG_SIZE_ENC-1] axu1_iu_itag, + input axu1_iu_n_flush, + input axu1_iu_np1_flush, + input [0:3] axu1_iu_exception, + input axu1_iu_flush2ucode, + input axu1_iu_flush2ucode_type, + input axu1_iu_exception_val, + input [0:3] axu1_iu_perf_events, + + // Completion and XU + // Run State + output [0:`THREADS-1] iu_xu_stop, + input [0:`THREADS-1] xu_iu_run_thread, + output iu_xu_credits_returned, + input [0:`THREADS-1] xu_iu_single_instr_mode, + input [0:`THREADS-1] xu_iu_raise_iss_pri, + output [0:`THREADS-1] iu_xu_quiesce, + output [0:`THREADS-1] iu_pc_quiesce, + // Interrupt Interface + output [0:`THREADS-1] iu_xu_rfi, + output [0:`THREADS-1] iu_xu_rfgi, + output [0:`THREADS-1] iu_xu_rfci, + output [0:`THREADS-1] iu_xu_rfmci, + output [0:`THREADS-1] iu_xu_int, + output [0:`THREADS-1] iu_xu_gint, + output [0:`THREADS-1] iu_xu_cint, + output [0:`THREADS-1] iu_xu_mcint, + output [0:`THREADS-1] iu_xu_dear_update, + output [62-`EFF_IFAR_ARCH:61] iu_xu_t0_nia, + output [0:16] iu_xu_t0_esr, + output [0:14] iu_xu_t0_mcsr, + output [0:18] iu_xu_t0_dbsr, + output [64-`GPR_WIDTH:63] iu_xu_t0_dear, +`ifndef THREADS1 + output [62-`EFF_IFAR_ARCH:61] iu_xu_t1_nia, + output [0:16] iu_xu_t1_esr, + output [0:14] iu_xu_t1_mcsr, + output [0:18] iu_xu_t1_dbsr, + output [64-`GPR_WIDTH:63] iu_xu_t1_dear, +`endif + output [0:`THREADS-1] iu_xu_dbsr_update, + output [0:`THREADS-1] iu_xu_dbsr_ude, + output [0:`THREADS-1] iu_xu_dbsr_ide, + output [0:`THREADS-1] iu_xu_esr_update, + output [0:`THREADS-1] iu_xu_act, + output [0:`THREADS-1] iu_xu_dbell_taken, + output [0:`THREADS-1] iu_xu_cdbell_taken, + output [0:`THREADS-1] iu_xu_gdbell_taken, + output [0:`THREADS-1] iu_xu_gcdbell_taken, + output [0:`THREADS-1] iu_xu_gmcdbell_taken, + output [0:`THREADS-1] iu_xu_instr_cpl, + input [0:`THREADS-1] xu_iu_np1_async_flush, + output [0:`THREADS-1] iu_xu_async_complete, + + // Interrupts + input [0:`THREADS-1] an_ac_uncond_dbg_event, + input [0:`THREADS-1] xu_iu_external_mchk, + input [0:`THREADS-1] xu_iu_ext_interrupt, + input [0:`THREADS-1] xu_iu_dec_interrupt, + input [0:`THREADS-1] xu_iu_udec_interrupt, + input [0:`THREADS-1] xu_iu_perf_interrupt, + input [0:`THREADS-1] xu_iu_fit_interrupt, + input [0:`THREADS-1] xu_iu_crit_interrupt, + input [0:`THREADS-1] xu_iu_wdog_interrupt, + input [0:`THREADS-1] xu_iu_gwdog_interrupt, + input [0:`THREADS-1] xu_iu_gfit_interrupt, + input [0:`THREADS-1] xu_iu_gdec_interrupt, + input [0:`THREADS-1] xu_iu_dbell_interrupt, + input [0:`THREADS-1] xu_iu_cdbell_interrupt, + input [0:`THREADS-1] xu_iu_gdbell_interrupt, + input [0:`THREADS-1] xu_iu_gcdbell_interrupt, + input [0:`THREADS-1] xu_iu_gmcdbell_interrupt, + input [0:`THREADS-1] xu_iu_dbsr_ide, + input [62-`EFF_IFAR_ARCH:61] xu_iu_t0_rest_ifar, +`ifndef THREADS1 + input [62-`EFF_IFAR_ARCH:61] xu_iu_t1_rest_ifar, +`endif + + + input [0:`THREADS-1] pc_iu_pm_fetch_halt, + //Ram interface + input [0:31] pc_iu_ram_instr, + input [0:3] pc_iu_ram_instr_ext, + input pc_iu_ram_issue, + output iu_pc_ram_done, + output iu_pc_ram_interrupt, + output iu_pc_ram_unsupported, + input [0:`THREADS-1] pc_iu_ram_active, + input [0:`THREADS-1] pc_iu_ram_flush_thread, + input [0:`THREADS-1] xu_iu_msrovride_enab, + input [0:`THREADS-1] pc_iu_stop, + input [0:`THREADS-1] pc_iu_step, + input [0:2] pc_iu_t0_dbg_action, +`ifndef THREADS1 + input [0:2] pc_iu_t1_dbg_action, +`endif + output [0:`THREADS-1] iu_pc_step_done, + output [0:`THREADS-1] iu_pc_stop_dbg_event, + output [0:`THREADS-1] iu_pc_err_debug_event, + output [0:`THREADS-1] iu_pc_attention_instr, + output [0:`THREADS-1] iu_pc_err_mchk_disabled, + output [0:`THREADS-1] ac_an_debug_trigger, + + output [0:`THREADS-1] cp_axu_i0_t1_v, + output [0:`THREADS-1] cp_axu_i1_t1_v, + output [0:`TYPE_WIDTH-1] cp_axu_t0_i0_t1_t, + output [0:`GPR_POOL_ENC-1] cp_axu_t0_i0_t1_p, + output [0:`TYPE_WIDTH-1] cp_axu_t0_i1_t1_t, + output [0:`GPR_POOL_ENC-1] cp_axu_t0_i1_t1_p, +`ifndef THREADS1 + output [0:`TYPE_WIDTH-1] cp_axu_t1_i0_t1_t, + output [0:`GPR_POOL_ENC-1] cp_axu_t1_i0_t1_p, + output [0:`TYPE_WIDTH-1] cp_axu_t1_i1_t1_t, + output [0:`GPR_POOL_ENC-1] cp_axu_t1_i1_t1_p, +`endif + + output cp_is_isync, + output cp_is_csync, + + // Completion flush + output [0:`THREADS-1] cp_flush, +`ifndef THREADS1 + output [0:`ITAG_SIZE_ENC-1] cp_t1_next_itag, + output [0:`ITAG_SIZE_ENC-1] cp_t1_flush_itag, + output [62-`EFF_IFAR_ARCH:61] cp_t1_flush_ifar, +`endif + output [0:`ITAG_SIZE_ENC-1] cp_t0_next_itag, + output [0:`ITAG_SIZE_ENC-1] cp_t0_flush_itag, + output [62-`EFF_IFAR_ARCH:61] cp_t0_flush_ifar, + + // Performance + input pc_iu_event_bus_enable, + input [0:2] pc_iu_event_count_mode, + input [0:4*`THREADS-1] iu_event_bus_in, + output [0:4*`THREADS-1] iu_event_bus_out, + + output [0:`THREADS-1] iu_pc_fx0_credit_ok, + output [0:`THREADS-1] iu_pc_fx1_credit_ok, + output [0:`THREADS-1] iu_pc_axu0_credit_ok, + output [0:`THREADS-1] iu_pc_axu1_credit_ok, + output [0:`THREADS-1] iu_pc_lq_credit_ok, + output [0:`THREADS-1] iu_pc_sq_credit_ok, + + + // Debug Trace + input pc_iu_trace_bus_enable, + input [0:10] pc_iu_debug_mux1_ctrls, + input [0:10] pc_iu_debug_mux2_ctrls, + + input [0:31] debug_bus_in, + output [0:31] debug_bus_out, + input [0:3] coretrace_ctrls_in, + output [0:3] coretrace_ctrls_out + ); + + // scan + wire btb_scan_in; + wire btb_scan_out; + wire bh0_scan_in; + wire bh0_scan_out; + wire bh1_scan_in; + wire bh1_scan_out; + wire bh2_scan_in; + wire bh2_scan_out; + wire [0:2*`THREADS-1] bp_scan_in; + wire [0:2*`THREADS-1] bp_scan_out; + wire [0:`THREADS*7] slice_scan_in; + wire [0:`THREADS*7] slice_scan_out; + wire [0:`THREADS] cp_scan_in; + wire [0:`THREADS] cp_scan_out; + wire func_scan_in; + wire func_scan_out; + wire ac_ccfg_scan_in; + wire ac_ccfg_scan_out; + wire time_scan_in; + wire time_scan_out; + wire repr_scan_in; + wire repr_scan_out; + wire [0:2] abst_scan_in; + wire [0:2] abst_scan_out; + wire [0:4] regf_scan_in; + wire [0:4] regf_scan_out; + wire [0:`THREADS-1] uc_scan_in; + wire [0:`THREADS-1] uc_scan_out; + wire ram_scan_in; + wire ram_scan_out; + wire dbg1_scan_in; + wire dbg1_scan_out; + + wire [0:`THREADS-1] cp_async_block; + + // ERAT connections to these need to be cleaned up for A2O + wire cp_ic_is_isync; + wire cp_ic_is_csync; + // bp + wire [0:1] iu2_0_bh0_rd_data; + wire [0:1] iu2_1_bh0_rd_data; + wire [0:1] iu2_2_bh0_rd_data; + wire [0:1] iu2_3_bh0_rd_data; + wire [0:1] iu2_0_bh1_rd_data; + wire [0:1] iu2_1_bh1_rd_data; + wire [0:1] iu2_2_bh1_rd_data; + wire [0:1] iu2_3_bh1_rd_data; + wire iu2_0_bh2_rd_data; + wire iu2_1_bh2_rd_data; + wire iu2_2_bh2_rd_data; + wire iu2_3_bh2_rd_data; + wire [0:9] iu0_bh0_rd_addr; + wire [0:9] iu0_bh1_rd_addr; + wire [0:8] iu0_bh2_rd_addr; + wire iu0_bh0_rd_act; + wire iu0_bh1_rd_act; + wire iu0_bh2_rd_act; + wire [0:1] ex5_bh0_wr_data; + wire [0:1] ex5_bh1_wr_data; + wire ex5_bh2_wr_data; + wire [0:9] ex5_bh0_wr_addr; + wire [0:9] ex5_bh1_wr_addr; + wire [0:8] ex5_bh2_wr_addr; + wire [0:3] ex5_bh0_wr_act; + wire [0:3] ex5_bh1_wr_act; + wire [0:3] ex5_bh2_wr_act; + wire [0:5] iu0_btb_rd_addr; + wire iu0_btb_rd_act; + wire [0:63] iu2_btb_rd_data; + wire [0:5] ex5_btb_wr_addr; + wire ex5_btb_wr_act; + wire [0:63] ex5_btb_wr_data; + wire [0:`THREADS-1] cp_bp_val; + wire [62-`EFF_IFAR_WIDTH:61] cp_bp_t0_ifar; + wire [0:1] cp_bp_t0_bh0_hist; + wire [0:1] cp_bp_t0_bh1_hist; + wire [0:1] cp_bp_t0_bh2_hist; + wire [0:`THREADS-1] cp_bp_br_pred; + wire [0:`THREADS-1] cp_bp_br_taken; + wire [0:`THREADS-1] cp_bp_bh_update; + wire [0:`THREADS-1] cp_bp_bcctr; + wire [0:`THREADS-1] cp_bp_bclr; + wire [0:`THREADS-1] cp_bp_getNIA; + wire [0:`THREADS-1] cp_bp_group; + wire [0:`THREADS-1] cp_bp_lk; + wire [0:1] cp_bp_t0_bh; + wire [62-`EFF_IFAR_WIDTH:61] cp_bp_t0_ctr; + wire [0:9] cp_bp_t0_gshare; + wire [0:2] cp_bp_t0_ls_ptr; + wire [0:`THREADS-1] cp_bp_btb_entry; + wire [0:1] cp_bp_t0_btb_hist; +`ifndef THREADS1 + wire [62-`EFF_IFAR_WIDTH:61] cp_bp_t1_ifar; + wire [0:1] cp_bp_t1_bh0_hist; + wire [0:1] cp_bp_t1_bh1_hist; + wire [0:1] cp_bp_t1_bh2_hist; + wire [0:1] cp_bp_t1_bh; + wire [62-`EFF_IFAR_WIDTH:61] cp_bp_t1_ctr; + wire [0:9] cp_bp_t1_gshare; + wire [0:2] cp_bp_t1_ls_ptr; + wire [0:1] cp_bp_t1_btb_hist; +`endif + // ibuf + wire [0:`IBUFF_DEPTH/4-1] ib_ic_t0_need_fetch; + wire [0:3] bp_ib_iu3_t0_val; + wire [62-`EFF_IFAR_WIDTH:61] bp_ib_iu3_t0_ifar; + wire [62-`EFF_IFAR_WIDTH:61] bp_ib_iu3_t0_bta; + wire [0:`IBUFF_INSTR_WIDTH-1] bp_ib_iu3_t0_0_instr; + wire [0:`IBUFF_INSTR_WIDTH-1] bp_ib_iu3_t0_1_instr; + wire [0:`IBUFF_INSTR_WIDTH-1] bp_ib_iu3_t0_2_instr; + wire [0:`IBUFF_INSTR_WIDTH-1] bp_ib_iu3_t0_3_instr; +`ifndef THREADS1 + wire [0:`IBUFF_DEPTH/4-1] ib_ic_t1_need_fetch; + wire [0:3] bp_ib_iu3_t1_val; + wire [62-`EFF_IFAR_WIDTH:61] bp_ib_iu3_t1_ifar; + wire [62-`EFF_IFAR_WIDTH:61] bp_ib_iu3_t1_bta; + wire [0:`IBUFF_INSTR_WIDTH-1] bp_ib_iu3_t1_0_instr; + wire [0:`IBUFF_INSTR_WIDTH-1] bp_ib_iu3_t1_1_instr; + wire [0:`IBUFF_INSTR_WIDTH-1] bp_ib_iu3_t1_2_instr; + wire [0:`IBUFF_INSTR_WIDTH-1] bp_ib_iu3_t1_3_instr; +`endif + + // idec + wire [0:31] spr_dec_mask; + wire [0:31] spr_dec_match; + + // rn + wire [0:`THREADS-1] spr_single_issue; + wire [0:`THREADS-1] cp_rn_empty; + wire [0:`THREADS-1] iu_flush; + wire [0:`THREADS-1] cp_iu0_flush_2ucode; + wire [0:`THREADS-1] cp_iu0_flush_2ucode_type; + wire [0:`THREADS-1] cp_iu0_flush_nonspec; + wire [0:`THREADS-1] ic_cp_nonspec_hit; + + // Output to dispatch to block due to ivax + wire [0:`THREADS-1] cp_dis_ivax; + + // Instruction 0 Complete + wire cp_rn_t0_i0_v; + wire cp_rn_t0_i0_axu_exception_val; + wire [0:3] cp_rn_t0_i0_axu_exception; + wire cp_rn_t0_i0_t1_v; + wire [0:2] cp_rn_t0_i0_t1_t; + wire [0:`GPR_POOL_ENC-1] cp_rn_t0_i0_t1_p; + wire [0:`GPR_POOL_ENC-1] cp_rn_t0_i0_t1_a; + + wire cp_rn_t0_i0_t2_v; + wire [0:2] cp_rn_t0_i0_t2_t; + wire [0:`GPR_POOL_ENC-1] cp_rn_t0_i0_t2_p; + wire [0:`GPR_POOL_ENC-1] cp_rn_t0_i0_t2_a; + + wire cp_rn_t0_i0_t3_v; + wire [0:2] cp_rn_t0_i0_t3_t; + wire [0:`GPR_POOL_ENC-1] cp_rn_t0_i0_t3_p; + wire [0:`GPR_POOL_ENC-1] cp_rn_t0_i0_t3_a; + + // Instruction 1 Complete + wire cp_rn_t0_i1_v; + wire cp_rn_t0_i1_axu_exception_val; + wire [0:3] cp_rn_t0_i1_axu_exception; + wire cp_rn_t0_i1_t1_v; + wire [0:2] cp_rn_t0_i1_t1_t; + wire [0:`GPR_POOL_ENC-1] cp_rn_t0_i1_t1_p; + wire [0:`GPR_POOL_ENC-1] cp_rn_t0_i1_t1_a; + + wire cp_rn_t0_i1_t2_v; + wire [0:2] cp_rn_t0_i1_t2_t; + wire [0:`GPR_POOL_ENC-1] cp_rn_t0_i1_t2_p; + wire [0:`GPR_POOL_ENC-1] cp_rn_t0_i1_t2_a; + + wire cp_rn_t0_i1_t3_v; + wire [0:2] cp_rn_t0_i1_t3_t; + wire [0:`GPR_POOL_ENC-1] cp_rn_t0_i1_t3_p; + wire [0:`GPR_POOL_ENC-1] cp_rn_t0_i1_t3_a; +`ifndef THREADS1 + // Instruction 0 Complete + wire cp_rn_t1_i0_v; + wire cp_rn_t1_i0_axu_exception_val; + wire [0:3] cp_rn_t1_i0_axu_exception; + wire cp_rn_t1_i0_t1_v; + wire [0:2] cp_rn_t1_i0_t1_t; + wire [0:`GPR_POOL_ENC-1] cp_rn_t1_i0_t1_p; + wire [0:`GPR_POOL_ENC-1] cp_rn_t1_i0_t1_a; + + wire cp_rn_t1_i0_t2_v; + wire [0:2] cp_rn_t1_i0_t2_t; + wire [0:`GPR_POOL_ENC-1] cp_rn_t1_i0_t2_p; + wire [0:`GPR_POOL_ENC-1] cp_rn_t1_i0_t2_a; + + wire cp_rn_t1_i0_t3_v; + wire [0:2] cp_rn_t1_i0_t3_t; + wire [0:`GPR_POOL_ENC-1] cp_rn_t1_i0_t3_p; + wire [0:`GPR_POOL_ENC-1] cp_rn_t1_i0_t3_a; + + // Instruction 1 Complete + wire cp_rn_t1_i1_v; + wire cp_rn_t1_i1_axu_exception_val; + wire [0:3] cp_rn_t1_i1_axu_exception; + wire cp_rn_t1_i1_t1_v; + wire [0:2] cp_rn_t1_i1_t1_t; + wire [0:`GPR_POOL_ENC-1] cp_rn_t1_i1_t1_p; + wire [0:`GPR_POOL_ENC-1] cp_rn_t1_i1_t1_a; + + wire cp_rn_t1_i1_t2_v; + wire [0:2] cp_rn_t1_i1_t2_t; + wire [0:`GPR_POOL_ENC-1] cp_rn_t1_i1_t2_p; + wire [0:`GPR_POOL_ENC-1] cp_rn_t1_i1_t2_a; + + wire cp_rn_t1_i1_t3_v; + wire [0:2] cp_rn_t1_i1_t3_t; + wire [0:`GPR_POOL_ENC-1] cp_rn_t1_i1_t3_p; + wire [0:`GPR_POOL_ENC-1] cp_rn_t1_i1_t3_a; +`endif + // Instruction 0 Issue + wire rn_cp_iu6_t0_i0_vld; + wire [0:`ITAG_SIZE_ENC-1] rn_cp_iu6_t0_i0_itag; + wire [0:2] rn_cp_iu6_t0_i0_ucode; + wire rn_cp_iu6_t0_i0_fuse_nop; + wire rn_cp_iu6_t0_i0_rte_lq; + wire rn_cp_iu6_t0_i0_rte_sq; + wire rn_cp_iu6_t0_i0_rte_fx0; + wire rn_cp_iu6_t0_i0_rte_fx1; + wire rn_cp_iu6_t0_i0_rte_axu0; + wire rn_cp_iu6_t0_i0_rte_axu1; + wire [62-`EFF_IFAR_WIDTH:61] rn_cp_iu6_t0_i0_ifar; + wire [62-`EFF_IFAR_WIDTH:61] rn_cp_iu6_t0_i0_bta; + wire rn_cp_iu6_t0_i0_isram; + wire [0:31] rn_cp_iu6_t0_i0_instr; + wire rn_cp_iu6_t0_i0_valop; + wire [0:2] rn_cp_iu6_t0_i0_error; + wire rn_cp_iu6_t0_i0_br_pred; + wire rn_cp_iu6_t0_i0_bh_update; + wire [0:1] rn_cp_iu6_t0_i0_bh0_hist; + wire [0:1] rn_cp_iu6_t0_i0_bh1_hist; + wire [0:1] rn_cp_iu6_t0_i0_bh2_hist; + wire [0:17] rn_cp_iu6_t0_i0_gshare; + wire [0:2] rn_cp_iu6_t0_i0_ls_ptr; + wire rn_cp_iu6_t0_i0_match; + wire rn_cp_iu6_t0_i0_type_fp; + wire rn_cp_iu6_t0_i0_type_ap; + wire rn_cp_iu6_t0_i0_type_spv; + wire rn_cp_iu6_t0_i0_type_st; + wire rn_cp_iu6_t0_i0_async_block; + wire rn_cp_iu6_t0_i0_np1_flush; + wire rn_cp_iu6_t0_i0_t1_v; + wire [0:2] rn_cp_iu6_t0_i0_t1_t; + wire [0:`GPR_POOL_ENC-1] rn_cp_iu6_t0_i0_t1_p; + wire [0:`GPR_POOL_ENC-1] rn_cp_iu6_t0_i0_t1_a; + wire rn_cp_iu6_t0_i0_t2_v; + wire [0:2] rn_cp_iu6_t0_i0_t2_t; + wire [0:`GPR_POOL_ENC-1] rn_cp_iu6_t0_i0_t2_p; + wire [0:`GPR_POOL_ENC-1] rn_cp_iu6_t0_i0_t2_a; + wire rn_cp_iu6_t0_i0_t3_v; + wire [0:2] rn_cp_iu6_t0_i0_t3_t; + wire [0:`GPR_POOL_ENC-1] rn_cp_iu6_t0_i0_t3_p; + wire [0:`GPR_POOL_ENC-1] rn_cp_iu6_t0_i0_t3_a; + wire rn_cp_iu6_t0_i0_btb_entry; + wire [0:1] rn_cp_iu6_t0_i0_btb_hist; + wire rn_cp_iu6_t0_i0_bta_val; + // Instruction 1 Issue + wire rn_cp_iu6_t0_i1_vld; + wire [0:`ITAG_SIZE_ENC-1] rn_cp_iu6_t0_i1_itag; + wire [0:2] rn_cp_iu6_t0_i1_ucode; + wire rn_cp_iu6_t0_i1_fuse_nop; + wire rn_cp_iu6_t0_i1_rte_lq; + wire rn_cp_iu6_t0_i1_rte_sq; + wire rn_cp_iu6_t0_i1_rte_fx0; + wire rn_cp_iu6_t0_i1_rte_fx1; + wire rn_cp_iu6_t0_i1_rte_axu0; + wire rn_cp_iu6_t0_i1_rte_axu1; + wire [62-`EFF_IFAR_WIDTH:61] rn_cp_iu6_t0_i1_ifar; + wire [62-`EFF_IFAR_WIDTH:61] rn_cp_iu6_t0_i1_bta; + wire rn_cp_iu6_t0_i1_isram; + wire [0:31] rn_cp_iu6_t0_i1_instr; + wire rn_cp_iu6_t0_i1_valop; + wire [0:2] rn_cp_iu6_t0_i1_error; + wire rn_cp_iu6_t0_i1_br_pred; + wire rn_cp_iu6_t0_i1_bh_update; + wire [0:1] rn_cp_iu6_t0_i1_bh0_hist; + wire [0:1] rn_cp_iu6_t0_i1_bh1_hist; + wire [0:1] rn_cp_iu6_t0_i1_bh2_hist; + wire [0:17] rn_cp_iu6_t0_i1_gshare; + wire [0:2] rn_cp_iu6_t0_i1_ls_ptr; + wire rn_cp_iu6_t0_i1_match; + wire rn_cp_iu6_t0_i1_type_fp; + wire rn_cp_iu6_t0_i1_type_ap; + wire rn_cp_iu6_t0_i1_type_spv; + wire rn_cp_iu6_t0_i1_type_st; + wire rn_cp_iu6_t0_i1_async_block; + wire rn_cp_iu6_t0_i1_np1_flush; + wire rn_cp_iu6_t0_i1_t1_v; + wire [0:2] rn_cp_iu6_t0_i1_t1_t; + wire [0:`GPR_POOL_ENC-1] rn_cp_iu6_t0_i1_t1_p; + wire [0:`GPR_POOL_ENC-1] rn_cp_iu6_t0_i1_t1_a; + wire rn_cp_iu6_t0_i1_t2_v; + wire [0:2] rn_cp_iu6_t0_i1_t2_t; + wire [0:`GPR_POOL_ENC-1] rn_cp_iu6_t0_i1_t2_p; + wire [0:`GPR_POOL_ENC-1] rn_cp_iu6_t0_i1_t2_a; + wire rn_cp_iu6_t0_i1_t3_v; + wire [0:2] rn_cp_iu6_t0_i1_t3_t; + wire [0:`GPR_POOL_ENC-1] rn_cp_iu6_t0_i1_t3_p; + wire [0:`GPR_POOL_ENC-1] rn_cp_iu6_t0_i1_t3_a; + wire rn_cp_iu6_t0_i1_btb_entry; + wire [0:1] rn_cp_iu6_t0_i1_btb_hist; + wire rn_cp_iu6_t0_i1_bta_val; +`ifndef THREADS1 + // Instruction 0 Issue + wire rn_cp_iu6_t1_i0_vld; + wire [0:`ITAG_SIZE_ENC-1] rn_cp_iu6_t1_i0_itag; + wire [0:2] rn_cp_iu6_t1_i0_ucode; + wire rn_cp_iu6_t1_i0_fuse_nop; + wire rn_cp_iu6_t1_i0_rte_lq; + wire rn_cp_iu6_t1_i0_rte_sq; + wire rn_cp_iu6_t1_i0_rte_fx0; + wire rn_cp_iu6_t1_i0_rte_fx1; + wire rn_cp_iu6_t1_i0_rte_axu0; + wire rn_cp_iu6_t1_i0_rte_axu1; + wire [62-`EFF_IFAR_WIDTH:61] rn_cp_iu6_t1_i0_ifar; + wire [62-`EFF_IFAR_WIDTH:61] rn_cp_iu6_t1_i0_bta; + wire rn_cp_iu6_t1_i0_isram; + wire [0:31] rn_cp_iu6_t1_i0_instr; + wire rn_cp_iu6_t1_i0_valop; + wire [0:2] rn_cp_iu6_t1_i0_error; + wire rn_cp_iu6_t1_i0_br_pred; + wire rn_cp_iu6_t1_i0_bh_update; + wire [0:1] rn_cp_iu6_t1_i0_bh0_hist; + wire [0:1] rn_cp_iu6_t1_i0_bh1_hist; + wire [0:1] rn_cp_iu6_t1_i0_bh2_hist; + wire [0:17] rn_cp_iu6_t1_i0_gshare; + wire [0:2] rn_cp_iu6_t1_i0_ls_ptr; + wire rn_cp_iu6_t1_i0_match; + wire rn_cp_iu6_t1_i0_type_fp; + wire rn_cp_iu6_t1_i0_type_ap; + wire rn_cp_iu6_t1_i0_type_spv; + wire rn_cp_iu6_t1_i0_type_st; + wire rn_cp_iu6_t1_i0_async_block; + wire rn_cp_iu6_t1_i0_np1_flush; + wire rn_cp_iu6_t1_i0_t1_v; + wire [0:2] rn_cp_iu6_t1_i0_t1_t; + wire [0:`GPR_POOL_ENC-1] rn_cp_iu6_t1_i0_t1_p; + wire [0:`GPR_POOL_ENC-1] rn_cp_iu6_t1_i0_t1_a; + wire rn_cp_iu6_t1_i0_t2_v; + wire [0:2] rn_cp_iu6_t1_i0_t2_t; + wire [0:`GPR_POOL_ENC-1] rn_cp_iu6_t1_i0_t2_p; + wire [0:`GPR_POOL_ENC-1] rn_cp_iu6_t1_i0_t2_a; + wire rn_cp_iu6_t1_i0_t3_v; + wire [0:2] rn_cp_iu6_t1_i0_t3_t; + wire [0:`GPR_POOL_ENC-1] rn_cp_iu6_t1_i0_t3_p; + wire [0:`GPR_POOL_ENC-1] rn_cp_iu6_t1_i0_t3_a; + wire rn_cp_iu6_t1_i0_btb_entry; + wire [0:1] rn_cp_iu6_t1_i0_btb_hist; + wire rn_cp_iu6_t1_i0_bta_val; + // Instruction 1 Issue + wire rn_cp_iu6_t1_i1_vld; + wire [0:`ITAG_SIZE_ENC-1] rn_cp_iu6_t1_i1_itag; + wire [0:2] rn_cp_iu6_t1_i1_ucode; + wire rn_cp_iu6_t1_i1_fuse_nop; + wire rn_cp_iu6_t1_i1_rte_lq; + wire rn_cp_iu6_t1_i1_rte_sq; + wire rn_cp_iu6_t1_i1_rte_fx0; + wire rn_cp_iu6_t1_i1_rte_fx1; + wire rn_cp_iu6_t1_i1_rte_axu0; + wire rn_cp_iu6_t1_i1_rte_axu1; + wire [62-`EFF_IFAR_WIDTH:61] rn_cp_iu6_t1_i1_ifar; + wire [62-`EFF_IFAR_WIDTH:61] rn_cp_iu6_t1_i1_bta; + wire rn_cp_iu6_t1_i1_isram; + wire [0:31] rn_cp_iu6_t1_i1_instr; + wire rn_cp_iu6_t1_i1_valop; + wire [0:2] rn_cp_iu6_t1_i1_error; + wire rn_cp_iu6_t1_i1_br_pred; + wire rn_cp_iu6_t1_i1_bh_update; + wire [0:1] rn_cp_iu6_t1_i1_bh0_hist; + wire [0:1] rn_cp_iu6_t1_i1_bh1_hist; + wire [0:1] rn_cp_iu6_t1_i1_bh2_hist; + wire [0:17] rn_cp_iu6_t1_i1_gshare; + wire [0:2] rn_cp_iu6_t1_i1_ls_ptr; + wire rn_cp_iu6_t1_i1_match; + wire rn_cp_iu6_t1_i1_type_fp; + wire rn_cp_iu6_t1_i1_type_ap; + wire rn_cp_iu6_t1_i1_type_spv; + wire rn_cp_iu6_t1_i1_type_st; + wire rn_cp_iu6_t1_i1_async_block; + wire rn_cp_iu6_t1_i1_np1_flush; + wire rn_cp_iu6_t1_i1_t1_v; + wire [0:2] rn_cp_iu6_t1_i1_t1_t; + wire [0:`GPR_POOL_ENC-1] rn_cp_iu6_t1_i1_t1_p; + wire [0:`GPR_POOL_ENC-1] rn_cp_iu6_t1_i1_t1_a; + wire rn_cp_iu6_t1_i1_t2_v; + wire [0:2] rn_cp_iu6_t1_i1_t2_t; + wire [0:`GPR_POOL_ENC-1] rn_cp_iu6_t1_i1_t2_p; + wire [0:`GPR_POOL_ENC-1] rn_cp_iu6_t1_i1_t2_a; + wire rn_cp_iu6_t1_i1_t3_v; + wire [0:2] rn_cp_iu6_t1_i1_t3_t; + wire [0:`GPR_POOL_ENC-1] rn_cp_iu6_t1_i1_t3_p; + wire [0:`GPR_POOL_ENC-1] rn_cp_iu6_t1_i1_t3_a; + wire rn_cp_iu6_t1_i1_btb_entry; + wire [0:1] rn_cp_iu6_t1_i1_btb_hist; + wire rn_cp_iu6_t1_i1_bta_val; +`endif + wire [64-`GPR_WIDTH:51] spr_ivpr; + wire [64-`GPR_WIDTH:51] spr_givpr; + wire [62-`EFF_IFAR_ARCH:61] spr_iac1; + wire [62-`EFF_IFAR_ARCH:61] spr_iac2; + wire [62-`EFF_IFAR_ARCH:61] spr_iac3; + wire [62-`EFF_IFAR_ARCH:61] spr_iac4; + + wire [0:`THREADS-1] spr_cpcr_we; + + wire [0:4] spr_t0_cpcr2_fx0_cnt; + wire [0:4] spr_t0_cpcr2_fx1_cnt; + wire [0:4] spr_t0_cpcr2_lq_cnt; + wire [0:4] spr_t0_cpcr2_sq_cnt; + wire [0:4] spr_t0_cpcr3_fu0_cnt; + wire [0:4] spr_t0_cpcr3_fu1_cnt; + wire [0:6] spr_t0_cpcr3_cp_cnt; + wire [0:4] spr_t0_cpcr4_fx0_cnt; + wire [0:4] spr_t0_cpcr4_fx1_cnt; + wire [0:4] spr_t0_cpcr4_lq_cnt; + wire [0:4] spr_t0_cpcr4_sq_cnt; + wire [0:4] spr_t0_cpcr5_fu0_cnt; + wire [0:4] spr_t0_cpcr5_fu1_cnt; + wire [0:6] spr_t0_cpcr5_cp_cnt; +`ifndef THREADS1 + wire [0:4] spr_t1_cpcr2_fx0_cnt; + wire [0:4] spr_t1_cpcr2_fx1_cnt; + wire [0:4] spr_t1_cpcr2_lq_cnt; + wire [0:4] spr_t1_cpcr2_sq_cnt; + wire [0:4] spr_t1_cpcr3_fu0_cnt; + wire [0:4] spr_t1_cpcr3_fu1_cnt; + wire [0:6] spr_t1_cpcr3_cp_cnt; + wire [0:4] spr_t1_cpcr4_fx0_cnt; + wire [0:4] spr_t1_cpcr4_fx1_cnt; + wire [0:4] spr_t1_cpcr4_lq_cnt; + wire [0:4] spr_t1_cpcr4_sq_cnt; + wire [0:4] spr_t1_cpcr5_fu0_cnt; + wire [0:4] spr_t1_cpcr5_fu1_cnt; + wire [0:6] spr_t1_cpcr5_cp_cnt; +`endif + wire [0:4] spr_cpcr0_fx0_cnt; + wire [0:4] spr_cpcr0_fx1_cnt; + wire [0:4] spr_cpcr0_lq_cnt; + wire [0:4] spr_cpcr0_sq_cnt; + wire [0:4] spr_cpcr1_fu0_cnt; + wire [0:4] spr_cpcr1_fu1_cnt; + + wire [0:`THREADS-1] spr_high_pri_mask; + wire [0:`THREADS-1] spr_med_pri_mask; + wire [0:5] spr_t0_low_pri_count; +`ifndef THREADS1 + wire [0:5] spr_t1_low_pri_count; +`endif + + wire [0:`THREADS-1] cp_rn_uc_credit_free; + wire [0:`THREADS-1] dp_cp_hold_req; + wire [0:`THREADS-1] dp_cp_bus_snoop_hold_req; + + wire [0:`THREADS-1] iu_spr_eheir_update; + wire [0:31] iu_spr_t0_eheir; +`ifndef THREADS1 + wire [0:31] iu_spr_t1_eheir; +`endif + + // axu + wire [0:7] iu_au_t0_config_iucr; +`ifndef THREADS1 + wire [0:7] iu_au_t1_config_iucr; +`endif + + wire [0:`THREADS-1] ib_uc_rdy; + wire [0:3] uc_ib_iu3_t0_invalid; + wire [0:1] uc_ib_t0_val; + wire [0:`THREADS-1] uc_ib_done; + wire [0:`THREADS-1] uc_ib_iu3_flush_all; + wire [0:31] uc_ib_t0_instr0; + wire [0:31] uc_ib_t0_instr1; + wire [62-`EFF_IFAR_WIDTH:61] uc_ib_t0_ifar0; + wire [62-`EFF_IFAR_WIDTH:61] uc_ib_t0_ifar1; + wire [0:3] uc_ib_t0_ext0; //RT, S1, S2, S3 + wire [0:3] uc_ib_t0_ext1; //RT, S1, S2, S3 +`ifndef THREADS1 + wire [0:3] uc_ib_iu3_t1_invalid; + wire [0:1] uc_ib_t1_val; + wire [0:31] uc_ib_t1_instr0; + wire [0:31] uc_ib_t1_instr1; + wire [62-`EFF_IFAR_WIDTH:61] uc_ib_t1_ifar0; + wire [62-`EFF_IFAR_WIDTH:61] uc_ib_t1_ifar1; + wire [0:3] uc_ib_t1_ext0; //RT, S1, S2, S3 + wire [0:3] uc_ib_t1_ext1; //RT, S1, S2, S3 +`endif + + wire iu_pc_ram_done_int; + wire [0:`THREADS-1] ib_rm_rdy; + wire [0:`THREADS-1] rm_ib_iu3_val; + wire [0:35] rm_ib_iu3_instr; + + wire [0:`THREADS-1] cp_flush_internal; + wire [0:`THREADS-1] iu_xu_stop_internal; + wire [62-`EFF_IFAR_ARCH:61] cp_t0_flush_ifar_internal; +`ifndef THREADS1 + wire [62-`EFF_IFAR_ARCH:61] cp_t1_flush_ifar_internal; +`endif + wire [0:`THREADS-1] iu_mm_bus_snoop_hold_ack_int; + + wire [0:`THREADS-1] cp_flush_into_uc; + wire [43:61] cp_uc_t0_flush_ifar; +`ifndef THREADS1 + wire [43:61] cp_uc_t1_flush_ifar; +`endif + wire [0:`THREADS-1] cp_uc_np1_flush; + + wire g8t_clkoff_b; + wire g8t_d_mode; + wire [0:4] g8t_delay_lclkr; + wire [0:4] g8t_mpw1_b; + wire g8t_mpw2_b; + wire g6t_clkoff_b; + wire g6t_act_dis; + wire g6t_d_mode; + wire [0:3] g6t_delay_lclkr; + wire [0:4] g6t_mpw1_b; + wire g6t_mpw2_b; + wire cam_clkoff_b; + wire cam_act_dis; + wire cam_d_mode; + wire [0:4] cam_delay_lclkr; + wire [0:4] cam_mpw1_b; + wire cam_mpw2_b; + wire [0:`THREADS-1] mm_iu_reload_hit; + + wire [0:31] ifetch_debug_bus_out; + wire [0:3] ifetch_coretrace_ctrls_out; + + //------------------------------- + // Slice performance interface with I$ + //------------------------------- + wire [0:20] slice_ic_t0_perf_events; +`ifndef THREADS1 + wire [0:20] slice_ic_t1_perf_events; +`endif + + wire [0:31] spr_cp_perf_event_mux_ctrls; + + wire tidn; + wire tiup; + + //need to remove only here for the facs + wire [0:`THREADS-1] cp_ib_iu4_hold; + + wire [0:`ITAG_SIZE_ENC-1] iu_lq_t0_i0_completed_itag_int; + wire [0:`ITAG_SIZE_ENC-1] iu_lq_t0_i1_completed_itag_int; +`ifndef THREADS1 + wire [0:`ITAG_SIZE_ENC-1] iu_lq_t1_i0_completed_itag_int; + wire [0:`ITAG_SIZE_ENC-1] iu_lq_t1_i1_completed_itag_int; +`endif + + wire pc_iu_func_slp_sl_thold_2; + wire pc_iu_func_nsl_thold_2; + wire pc_iu_cfg_slp_sl_thold_2; + wire pc_iu_regf_slp_sl_thold_2; + wire pc_iu_func_sl_thold_2; + wire pc_iu_time_sl_thold_2; + wire pc_iu_abst_sl_thold_2; + wire pc_iu_abst_slp_sl_thold_2; + wire pc_iu_repr_sl_thold_2; + wire pc_iu_ary_nsl_thold_2; + wire pc_iu_ary_slp_nsl_thold_2; + wire pc_iu_func_slp_nsl_thold_2; + wire pc_iu_bolt_sl_thold_2; + wire pc_iu_sg_2; + wire pc_iu_fce_2; + + wire [0:4*`THREADS-1] event_bus_in[0:1]; + wire [0:4*`THREADS-1] event_bus_out[0:1]; + + wire vdd; + wire gnd; + + assign vdd = 1'b1; + assign gnd = 1'b0; + + // Temp should be driven by external mode debug compare decodes + assign mm_iu_reload_hit[0] = mm_iu_ierat_rel_val[0] & mm_iu_ierat_rel_val[4]; +`ifndef THREADS1 + assign mm_iu_reload_hit[1] = mm_iu_ierat_rel_val[1] & mm_iu_ierat_rel_val[4]; +`endif + + assign cp_flush = cp_flush_internal; + assign iu_xu_stop = iu_xu_stop_internal; + assign cp_t0_flush_ifar = cp_t0_flush_ifar_internal; +`ifndef THREADS1 + assign cp_t1_flush_ifar = cp_t1_flush_ifar_internal; +`endif + assign iu_mm_bus_snoop_hold_ack = iu_mm_bus_snoop_hold_ack_int; + + assign tidn = 1'b0; + assign tiup = 1'b1; + + assign cp_ib_iu4_hold = {`THREADS{1'b0}}; + + assign cp_is_isync = cp_ic_is_isync; + assign cp_is_csync = cp_ic_is_csync; + + assign iu_lq_t0_i0_completed_itag = iu_lq_t0_i0_completed_itag_int; + assign iu_lq_t0_i1_completed_itag = iu_lq_t0_i1_completed_itag_int; +`ifndef THREADS1 + assign iu_lq_t1_i0_completed_itag = iu_lq_t1_i0_completed_itag_int; + assign iu_lq_t1_i1_completed_itag = iu_lq_t1_i1_completed_itag_int; +`endif + + assign event_bus_in[0] = iu_event_bus_in; + assign iu_event_bus_out = event_bus_out[1]; + assign event_bus_in[1] = event_bus_out[0]; + + + iuq_btb iuq_btb0( +// tri_btb_64x64_1r1w iuq_btb0( + .gnd(gnd), + .vdd(vdd), + .vcs(vdd), + .nclk(nclk), + .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), + .pc_iu_sg_2(pc_iu_sg_2), + .pc_iu_fce_2(pc_iu_fce_2), + .tc_ac_ccflush_dc(tc_ac_ccflush_dc), + .clkoff_b(clkoff_b), + .act_dis(act_dis), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scan_in(btb_scan_in), + .scan_out(btb_scan_out), + .r_act(iu0_btb_rd_act), + .w_act(ex5_btb_wr_act), + .r_addr(iu0_btb_rd_addr), + .w_addr(ex5_btb_wr_addr), + .data_in(ex5_btb_wr_data[0:42]), + .data_out(iu2_btb_rd_data[0:42]), + .pc_iu_init_reset(pc_iu_init_reset) + ); + + + iuq_ifetch iuq_ifetch0( + //.vcs(vdd), + //.vdd(vdd), + //.gnd(gnd), + .nclk(nclk), + .tc_ac_ccflush_dc(tc_ac_ccflush_dc), + .tc_ac_scan_dis_dc_b(tc_ac_scan_dis_dc_b), + .tc_ac_scan_diag_dc(tc_ac_scan_diag_dc), + .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), + .pc_iu_func_slp_sl_thold_2(pc_iu_func_slp_sl_thold_2), + .pc_iu_func_nsl_thold_2(pc_iu_func_nsl_thold_2), + .pc_iu_cfg_slp_sl_thold_2(pc_iu_cfg_slp_sl_thold_2), + .pc_iu_regf_slp_sl_thold_2(pc_iu_regf_slp_sl_thold_2), + .pc_iu_time_sl_thold_2(pc_iu_time_sl_thold_2), + .pc_iu_abst_sl_thold_2(pc_iu_abst_sl_thold_2), + .pc_iu_abst_slp_sl_thold_2(pc_iu_abst_slp_sl_thold_2), + .pc_iu_repr_sl_thold_2(pc_iu_repr_sl_thold_2), + .pc_iu_ary_nsl_thold_2(pc_iu_ary_nsl_thold_2), + .pc_iu_ary_slp_nsl_thold_2(pc_iu_ary_slp_nsl_thold_2), + .pc_iu_func_slp_nsl_thold_2(pc_iu_func_slp_nsl_thold_2), + .pc_iu_bolt_sl_thold_2(pc_iu_bolt_sl_thold_2), + .pc_iu_sg_2(pc_iu_sg_2), + .pc_iu_fce_2(pc_iu_fce_2), + .clkoff_b(clkoff_b), + .act_dis(act_dis), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .g8t_clkoff_b(g8t_clkoff_b), + .g8t_d_mode(g8t_d_mode), + .g8t_delay_lclkr(g8t_delay_lclkr), + .g8t_mpw1_b(g8t_mpw1_b), + .g8t_mpw2_b(g8t_mpw2_b), + .g6t_clkoff_b(g6t_clkoff_b), + .g6t_act_dis(g6t_act_dis), + .g6t_d_mode(g6t_d_mode), + .g6t_delay_lclkr(g6t_delay_lclkr), + .g6t_mpw1_b(g6t_mpw1_b), + .g6t_mpw2_b(g6t_mpw2_b), + .cam_clkoff_b(cam_clkoff_b), + .cam_act_dis(cam_act_dis), + .cam_d_mode(cam_d_mode), + .cam_delay_lclkr(cam_delay_lclkr), + .cam_mpw1_b(cam_mpw1_b), + .cam_mpw2_b(cam_mpw2_b), + .func_scan_in(func_scan_in), + .func_scan_out(func_scan_out), + .ac_ccfg_scan_in(ac_ccfg_scan_in), + .ac_ccfg_scan_out(ac_ccfg_scan_out), + .time_scan_in(time_scan_in), + .time_scan_out(time_scan_out), + .repr_scan_in(repr_scan_in), + .repr_scan_out(repr_scan_out), + .abst_scan_in(abst_scan_in), + .abst_scan_out(abst_scan_out), + .regf_scan_in(regf_scan_in), + .regf_scan_out(regf_scan_out), + .iu_pc_err_icache_parity(iu_pc_err_icache_parity), + .iu_pc_err_icachedir_parity(iu_pc_err_icachedir_parity), + .iu_pc_err_icachedir_multihit(iu_pc_err_icachedir_multihit), + .iu_pc_err_ierat_multihit(iu_pc_err_ierat_multihit), + .iu_pc_err_ierat_parity(iu_pc_err_ierat_parity), + .pc_iu_inj_icache_parity(pc_iu_inj_icache_parity), + .pc_iu_inj_icachedir_parity(pc_iu_inj_icachedir_parity), + .pc_iu_inj_icachedir_multihit(pc_iu_inj_icachedir_multihit), + .pc_iu_abist_g8t_wenb(pc_iu_abist_g8t_wenb), + .pc_iu_abist_g8t1p_renb_0(pc_iu_abist_g8t1p_renb_0), + .pc_iu_abist_di_0(pc_iu_abist_di_0), + .pc_iu_abist_g8t_bw_1(pc_iu_abist_g8t_bw_1), + .pc_iu_abist_g8t_bw_0(pc_iu_abist_g8t_bw_0), + .pc_iu_abist_waddr_0(pc_iu_abist_waddr_0), + .pc_iu_abist_raddr_0(pc_iu_abist_raddr_0), + .pc_iu_abist_ena_dc(pc_iu_abist_ena_dc), + .pc_iu_abist_wl128_comp_ena(pc_iu_abist_wl128_comp_ena), + .pc_iu_abist_raw_dc_b(pc_iu_abist_raw_dc_b), + .pc_iu_abist_g8t_dcomp(pc_iu_abist_g8t_dcomp), + .pc_iu_abist_g6t_bw(pc_iu_abist_g6t_bw), + .pc_iu_abist_di_g6t_2r(pc_iu_abist_di_g6t_2r), + .pc_iu_abist_wl512_comp_ena(pc_iu_abist_wl512_comp_ena), + .pc_iu_abist_dcomp_g6t_2r(pc_iu_abist_dcomp_g6t_2r), + .pc_iu_abist_g6t_r_wb(pc_iu_abist_g6t_r_wb), + .an_ac_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc), + .an_ac_lbist_en_dc(an_ac_lbist_en_dc), + .an_ac_atpg_en_dc(an_ac_atpg_en_dc), + .an_ac_grffence_en_dc(an_ac_grffence_en_dc), + .pc_iu_bo_enable_3(pc_iu_bo_enable_3), + .pc_iu_bo_reset(pc_iu_bo_reset), + .pc_iu_bo_unload(pc_iu_bo_unload), + .pc_iu_bo_repair(pc_iu_bo_repair), + .pc_iu_bo_shdata(pc_iu_bo_shdata), + .pc_iu_bo_select(pc_iu_bo_select[0:3]), + .iu_pc_bo_fail(iu_pc_bo_fail[0:3]), + .iu_pc_bo_diagout(iu_pc_bo_diagout[0:3]), + .lq_iu_icbi_val(lq_iu_icbi_val), + .lq_iu_icbi_addr(lq_iu_icbi_addr), + .iu_lq_icbi_complete(iu_lq_icbi_complete), + .lq_iu_ici_val(lq_iu_ici_val), + .iu_lq_spr_iucr0_icbi_ack(iu_lq_spr_iucr0_icbi_ack), + .pc_iu_init_reset(pc_iu_init_reset), + .xu_iu_val(xu_iu_val), + .xu_iu_is_eratre(xu_iu_is_eratre), + .xu_iu_is_eratwe(xu_iu_is_eratwe), + .xu_iu_is_eratsx(xu_iu_is_eratsx), + .xu_iu_is_eratilx(xu_iu_is_eratilx), + .cp_is_isync(cp_ic_is_isync), + .cp_is_csync(cp_ic_is_csync), + .xu_iu_ws(xu_iu_ws), + .xu_iu_ra_entry(xu_iu_ra_entry), + .xu_iu_rb(xu_iu_rb), + .xu_iu_rs_data(xu_iu_rs_data), + .iu_xu_ord_read_done(iu_xu_ord_read_done), + .iu_xu_ord_write_done(iu_xu_ord_write_done), + .iu_xu_ord_par_err(iu_xu_ord_par_err), + .iu_xu_ord_n_flush_req(iu_xu_ord_n_flush_req), + .xu_iu_msr_gs(xu_iu_msr_gs), + .xu_iu_msr_pr(xu_iu_msr_pr), + .xu_iu_msr_is(xu_iu_msr_is), + .xu_iu_hid_mmu_mode(xu_iu_hid_mmu_mode), + .xu_iu_spr_ccr2_ifrat(xu_iu_spr_ccr2_ifrat), + .xu_iu_spr_ccr2_ifratsc(xu_iu_spr_ccr2_ifratsc), + .xu_iu_xucr4_mmu_mchk(xu_iu_xucr4_mmu_mchk), + .iu_xu_ex5_data(iu_xu_ex5_data), + .iu_mm_ierat_req(iu_mm_ierat_req), + .iu_mm_ierat_req_nonspec(iu_mm_ierat_req_nonspec), + .iu_mm_ierat_epn(iu_mm_ierat_epn), + .iu_mm_ierat_thdid(iu_mm_ierat_thdid), + .iu_mm_ierat_state(iu_mm_ierat_state), + .iu_mm_ierat_tid(iu_mm_ierat_tid), + .iu_mm_ierat_flush(iu_mm_ierat_flush), + .iu_mm_perf_itlb(iu_mm_perf_itlb), + .mm_iu_ierat_rel_val(mm_iu_ierat_rel_val), + .mm_iu_ierat_rel_data(mm_iu_ierat_rel_data), + .mm_iu_t0_ierat_pid(mm_iu_t0_ierat_pid), + .mm_iu_t0_ierat_mmucr0(mm_iu_t0_ierat_mmucr0), +`ifndef THREADS1 + .mm_iu_t1_ierat_pid(mm_iu_t1_ierat_pid), + .mm_iu_t1_ierat_mmucr0(mm_iu_t1_ierat_mmucr0), +`endif + .iu_mm_ierat_mmucr0(iu_mm_ierat_mmucr0), + .iu_mm_ierat_mmucr0_we(iu_mm_ierat_mmucr0_we), + .mm_iu_ierat_mmucr1(mm_iu_ierat_mmucr1), + .iu_mm_ierat_mmucr1(iu_mm_ierat_mmucr1), + .iu_mm_ierat_mmucr1_we(iu_mm_ierat_mmucr1_we), + .mm_iu_ierat_snoop_coming(mm_iu_ierat_snoop_coming), + .mm_iu_ierat_snoop_val(mm_iu_ierat_snoop_val), + .mm_iu_ierat_snoop_attr(mm_iu_ierat_snoop_attr), + .mm_iu_ierat_snoop_vpn(mm_iu_ierat_snoop_vpn), + .iu_mm_ierat_snoop_ack(iu_mm_ierat_snoop_ack), + .mm_iu_hold_req(mm_iu_hold_req), + .mm_iu_hold_done(mm_iu_hold_done), + .mm_iu_bus_snoop_hold_req(iu_mm_bus_snoop_hold_ack_int), + .mm_iu_bus_snoop_hold_done(mm_iu_bus_snoop_hold_done), + .pc_iu_pm_fetch_halt(pc_iu_pm_fetch_halt), + .xu_iu_run_thread(xu_iu_run_thread), + .cp_ic_stop(iu_xu_stop_internal), + .xu_iu_msr_cm(xu_iu_msr_cm), + .iu_flush(iu_flush), + .br_iu_redirect(br_iu_redirect), + .br_iu_bta(br_iu_bta), + .cp_flush_into_uc(cp_flush_into_uc), + .cp_uc_t0_flush_ifar(cp_uc_t0_flush_ifar), +`ifndef THREADS1 + .cp_uc_t1_flush_ifar(cp_uc_t1_flush_ifar), +`endif + .cp_uc_np1_flush(cp_uc_np1_flush), + .cp_uc_credit_free(cp_rn_uc_credit_free), + .cp_flush(cp_flush_internal), + .cp_iu0_t0_flush_ifar(cp_t0_flush_ifar_internal), +`ifndef THREADS1 + .cp_iu0_t1_flush_ifar(cp_t1_flush_ifar_internal), +`endif + .cp_iu0_flush_2ucode(cp_iu0_flush_2ucode), + .cp_iu0_flush_2ucode_type(cp_iu0_flush_2ucode_type), + .cp_iu0_flush_nonspec(cp_iu0_flush_nonspec), + .ic_cp_nonspec_hit(ic_cp_nonspec_hit), + .an_ac_back_inv(an_ac_back_inv), + .an_ac_back_inv_addr(an_ac_back_inv_addr), + .an_ac_back_inv_target(an_ac_back_inv_target), + .iu_lq_request(iu_lq_request), + .iu_lq_ctag(iu_lq_ctag), + .iu_lq_ra(iu_lq_ra), + .iu_lq_wimge(iu_lq_wimge), + .iu_lq_userdef(iu_lq_userdef), + .an_ac_reld_data_vld(an_ac_reld_data_vld), + .an_ac_reld_core_tag(an_ac_reld_core_tag), + .an_ac_reld_qw(an_ac_reld_qw), + .an_ac_reld_data(an_ac_reld_data), + .an_ac_reld_ecc_err(an_ac_reld_ecc_err), + .an_ac_reld_ecc_err_ue(an_ac_reld_ecc_err_ue), + .ib_ic_t0_need_fetch(ib_ic_t0_need_fetch), +`ifndef THREADS1 + .ib_ic_t1_need_fetch(ib_ic_t1_need_fetch), +`endif + .cp_async_block(cp_async_block), + .iu_mm_lmq_empty(iu_mm_lmq_empty), + .iu_xu_icache_quiesce(iu_xu_icache_quiesce), + .iu_pc_icache_quiesce(iu_pc_icache_quiesce), + .iu2_0_bh0_rd_data(iu2_0_bh0_rd_data), + .iu2_1_bh0_rd_data(iu2_1_bh0_rd_data), + .iu2_2_bh0_rd_data(iu2_2_bh0_rd_data), + .iu2_3_bh0_rd_data(iu2_3_bh0_rd_data), + .iu2_0_bh1_rd_data(iu2_0_bh1_rd_data), + .iu2_1_bh1_rd_data(iu2_1_bh1_rd_data), + .iu2_2_bh1_rd_data(iu2_2_bh1_rd_data), + .iu2_3_bh1_rd_data(iu2_3_bh1_rd_data), + .iu2_0_bh2_rd_data(iu2_0_bh2_rd_data), + .iu2_1_bh2_rd_data(iu2_1_bh2_rd_data), + .iu2_2_bh2_rd_data(iu2_2_bh2_rd_data), + .iu2_3_bh2_rd_data(iu2_3_bh2_rd_data), + .iu0_bh0_rd_addr(iu0_bh0_rd_addr), + .iu0_bh1_rd_addr(iu0_bh1_rd_addr), + .iu0_bh2_rd_addr(iu0_bh2_rd_addr), + .iu0_bh0_rd_act(iu0_bh0_rd_act), + .iu0_bh1_rd_act(iu0_bh1_rd_act), + .iu0_bh2_rd_act(iu0_bh2_rd_act), + .ex5_bh0_wr_data(ex5_bh0_wr_data), + .ex5_bh1_wr_data(ex5_bh1_wr_data), + .ex5_bh2_wr_data(ex5_bh2_wr_data), + .ex5_bh0_wr_addr(ex5_bh0_wr_addr), + .ex5_bh1_wr_addr(ex5_bh1_wr_addr), + .ex5_bh2_wr_addr(ex5_bh2_wr_addr), + .ex5_bh0_wr_act(ex5_bh0_wr_act), + .ex5_bh1_wr_act(ex5_bh1_wr_act), + .ex5_bh2_wr_act(ex5_bh2_wr_act), + .iu0_btb_rd_addr(iu0_btb_rd_addr), + .iu0_btb_rd_act(iu0_btb_rd_act), + .iu2_btb_rd_data(iu2_btb_rd_data), + .ex5_btb_wr_addr(ex5_btb_wr_addr), + .ex5_btb_wr_act(ex5_btb_wr_act), + .ex5_btb_wr_data(ex5_btb_wr_data), + .bp_ib_iu3_t0_val(bp_ib_iu3_t0_val), + .bp_ib_iu3_t0_ifar(bp_ib_iu3_t0_ifar), + .bp_ib_iu3_t0_bta(bp_ib_iu3_t0_bta), + .bp_ib_iu3_t0_0_instr(bp_ib_iu3_t0_0_instr), + .bp_ib_iu3_t0_1_instr(bp_ib_iu3_t0_1_instr), + .bp_ib_iu3_t0_2_instr(bp_ib_iu3_t0_2_instr), + .bp_ib_iu3_t0_3_instr(bp_ib_iu3_t0_3_instr), +`ifndef THREADS1 + .bp_ib_iu3_t1_val(bp_ib_iu3_t1_val), + .bp_ib_iu3_t1_ifar(bp_ib_iu3_t1_ifar), + .bp_ib_iu3_t1_bta(bp_ib_iu3_t1_bta), + .bp_ib_iu3_t1_0_instr(bp_ib_iu3_t1_0_instr), + .bp_ib_iu3_t1_1_instr(bp_ib_iu3_t1_1_instr), + .bp_ib_iu3_t1_2_instr(bp_ib_iu3_t1_2_instr), + .bp_ib_iu3_t1_3_instr(bp_ib_iu3_t1_3_instr), +`endif + .cp_bp_val(cp_bp_val), + .cp_bp_t0_ifar(cp_bp_t0_ifar), + .cp_bp_t0_bh0_hist(cp_bp_t0_bh0_hist), + .cp_bp_t0_bh1_hist(cp_bp_t0_bh1_hist), + .cp_bp_t0_bh2_hist(cp_bp_t0_bh2_hist), +`ifndef THREADS1 + .cp_bp_t1_ifar(cp_bp_t1_ifar), + .cp_bp_t1_bh0_hist(cp_bp_t1_bh0_hist), + .cp_bp_t1_bh1_hist(cp_bp_t1_bh1_hist), + .cp_bp_t1_bh2_hist(cp_bp_t1_bh2_hist), +`endif + .cp_bp_br_pred(cp_bp_br_pred), + .cp_bp_br_taken(cp_bp_br_taken), + .cp_bp_bh_update(cp_bp_bh_update), + .cp_bp_bcctr(cp_bp_bcctr), + .cp_bp_bclr(cp_bp_bclr), + .cp_bp_getNIA(cp_bp_getNIA), + .cp_bp_group(cp_bp_group), + .cp_bp_lk(cp_bp_lk), + .cp_bp_t0_bh(cp_bp_t0_bh), + .cp_bp_t0_bta(cp_bp_t0_ctr), + .cp_bp_t0_gshare(cp_bp_t0_gshare), + .cp_bp_t0_ls_ptr(cp_bp_t0_ls_ptr), + .cp_bp_t0_btb_hist(cp_bp_t0_btb_hist), +`ifndef THREADS1 + .cp_bp_t1_bh(cp_bp_t1_bh), + .cp_bp_t1_bta(cp_bp_t1_ctr), + .cp_bp_t1_gshare(cp_bp_t1_gshare), + .cp_bp_t1_ls_ptr(cp_bp_t1_ls_ptr), + .cp_bp_t1_btb_hist(cp_bp_t1_btb_hist), +`endif + .cp_bp_btb_entry(cp_bp_btb_entry), + .br_iu_gshare(br_iu_gshare), + .br_iu_ls_ptr(br_iu_ls_ptr), + .br_iu_ls_data(br_iu_ls_data), + .br_iu_ls_update(br_iu_ls_update), + .xu_iu_msr_de(xu_iu_msr_de), + .xu_iu_dbcr0_icmp(xu_iu_dbcr0_icmp), + .xu_iu_dbcr0_brt(xu_iu_dbcr0_brt), + .xu_iu_iac1_en(xu_iu_iac1_en), + .xu_iu_iac2_en(xu_iu_iac2_en), + .xu_iu_iac3_en(xu_iu_iac3_en), + .xu_iu_iac4_en(xu_iu_iac4_en), + .lq_iu_spr_dbcr3_ivc(lq_iu_spr_dbcr3_ivc), + .xu_iu_single_instr_mode(xu_iu_single_instr_mode), + .xu_iu_raise_iss_pri(xu_iu_raise_iss_pri), + .bp_scan_in(bp_scan_in), + .bp_scan_out(bp_scan_out), + .pc_iu_ram_instr(pc_iu_ram_instr), + .pc_iu_ram_instr_ext(pc_iu_ram_instr_ext), + .pc_iu_ram_issue(pc_iu_ram_issue), + .pc_iu_ram_active(pc_iu_ram_active), + .iu_pc_ram_done(iu_pc_ram_done_int), + .ib_rm_rdy(ib_rm_rdy), + .rm_ib_iu3_val(rm_ib_iu3_val), + .rm_ib_iu3_instr(rm_ib_iu3_instr), + .ram_scan_in(ram_scan_in), + .ram_scan_out(ram_scan_out), + .uc_scan_in(uc_scan_in), + .uc_scan_out(uc_scan_out), + .iu_pc_err_ucode_illegal(iu_pc_err_ucode_illegal), + .xu_iu_ucode_xer_val(xu_iu_ucode_xer_val), + .xu_iu_ucode_xer(xu_iu_ucode_xer), + .ib_uc_rdy(ib_uc_rdy), + .uc_ib_iu3_t0_invalid(uc_ib_iu3_t0_invalid), + .uc_ib_t0_val(uc_ib_t0_val), +`ifndef THREADS1 + .uc_ib_iu3_t1_invalid(uc_ib_iu3_t1_invalid), + .uc_ib_t1_val(uc_ib_t1_val), +`endif + .uc_ib_done(uc_ib_done), + .uc_ib_iu3_flush_all(uc_ib_iu3_flush_all), + .uc_ib_t0_instr0(uc_ib_t0_instr0), + .uc_ib_t0_instr1(uc_ib_t0_instr1), + .uc_ib_t0_ifar0(uc_ib_t0_ifar0), + .uc_ib_t0_ifar1(uc_ib_t0_ifar1), + .uc_ib_t0_ext0(uc_ib_t0_ext0), + .uc_ib_t0_ext1(uc_ib_t0_ext1), +`ifndef THREADS1 + .uc_ib_t1_instr0(uc_ib_t1_instr0), + .uc_ib_t1_instr1(uc_ib_t1_instr1), + .uc_ib_t1_ifar0(uc_ib_t1_ifar0), + .uc_ib_t1_ifar1(uc_ib_t1_ifar1), + .uc_ib_t1_ext0(uc_ib_t1_ext0), + .uc_ib_t1_ext1(uc_ib_t1_ext1), +`endif + .iu_slowspr_val_in(iu_slowspr_val_in), + .iu_slowspr_rw_in(iu_slowspr_rw_in), + .iu_slowspr_etid_in(iu_slowspr_etid_in), + .iu_slowspr_addr_in(iu_slowspr_addr_in), + .iu_slowspr_data_in(iu_slowspr_data_in), + .iu_slowspr_done_in(iu_slowspr_done_in), + .iu_slowspr_val_out(iu_slowspr_val_out), + .iu_slowspr_rw_out(iu_slowspr_rw_out), + .iu_slowspr_etid_out(iu_slowspr_etid_out), + .iu_slowspr_addr_out(iu_slowspr_addr_out), + .iu_slowspr_data_out(iu_slowspr_data_out), + .iu_slowspr_done_out(iu_slowspr_done_out), + .spr_dec_mask(spr_dec_mask), + .spr_dec_match(spr_dec_match), + .spr_single_issue(spr_single_issue), + .iu_au_t0_config_iucr(iu_au_t0_config_iucr), +`ifndef THREADS1 + .iu_au_t1_config_iucr(iu_au_t1_config_iucr), +`endif + .xu_iu_pri_val(xu_iu_pri_val), + .xu_iu_pri(xu_iu_pri), + .spr_cp_perf_event_mux_ctrls(spr_cp_perf_event_mux_ctrls), + .slice_ic_t0_perf_events(slice_ic_t0_perf_events), +`ifndef THREADS1 + .slice_ic_t1_perf_events(slice_ic_t1_perf_events), +`endif + .spr_ivpr(spr_ivpr), + .spr_givpr(spr_givpr), + .spr_iac1(spr_iac1), + .spr_iac2(spr_iac2), + .spr_iac3(spr_iac3), + .spr_iac4(spr_iac4), + .spr_cpcr_we(spr_cpcr_we), + .spr_t0_cpcr2_fx0_cnt(spr_t0_cpcr2_fx0_cnt), + .spr_t0_cpcr2_fx1_cnt(spr_t0_cpcr2_fx1_cnt), + .spr_t0_cpcr2_lq_cnt(spr_t0_cpcr2_lq_cnt), + .spr_t0_cpcr2_sq_cnt(spr_t0_cpcr2_sq_cnt), + .spr_t0_cpcr3_fu0_cnt(spr_t0_cpcr3_fu0_cnt), + .spr_t0_cpcr3_fu1_cnt(spr_t0_cpcr3_fu1_cnt), + .spr_t0_cpcr3_cp_cnt(spr_t0_cpcr3_cp_cnt), + .spr_t0_cpcr4_fx0_cnt(spr_t0_cpcr4_fx0_cnt), + .spr_t0_cpcr4_fx1_cnt(spr_t0_cpcr4_fx1_cnt), + .spr_t0_cpcr4_lq_cnt(spr_t0_cpcr4_lq_cnt), + .spr_t0_cpcr4_sq_cnt(spr_t0_cpcr4_sq_cnt), + .spr_t0_cpcr5_fu0_cnt(spr_t0_cpcr5_fu0_cnt), + .spr_t0_cpcr5_fu1_cnt(spr_t0_cpcr5_fu1_cnt), + .spr_t0_cpcr5_cp_cnt(spr_t0_cpcr5_cp_cnt), +`ifndef THREADS1 + .spr_t1_cpcr2_fx0_cnt(spr_t1_cpcr2_fx0_cnt), + .spr_t1_cpcr2_fx1_cnt(spr_t1_cpcr2_fx1_cnt), + .spr_t1_cpcr2_lq_cnt(spr_t1_cpcr2_lq_cnt), + .spr_t1_cpcr2_sq_cnt(spr_t1_cpcr2_sq_cnt), + .spr_t1_cpcr3_fu0_cnt(spr_t1_cpcr3_fu0_cnt), + .spr_t1_cpcr3_fu1_cnt(spr_t1_cpcr3_fu1_cnt), + .spr_t1_cpcr3_cp_cnt(spr_t1_cpcr3_cp_cnt), + .spr_t1_cpcr4_fx0_cnt(spr_t1_cpcr4_fx0_cnt), + .spr_t1_cpcr4_fx1_cnt(spr_t1_cpcr4_fx1_cnt), + .spr_t1_cpcr4_lq_cnt(spr_t1_cpcr4_lq_cnt), + .spr_t1_cpcr4_sq_cnt(spr_t1_cpcr4_sq_cnt), + .spr_t1_cpcr5_fu0_cnt(spr_t1_cpcr5_fu0_cnt), + .spr_t1_cpcr5_fu1_cnt(spr_t1_cpcr5_fu1_cnt), + .spr_t1_cpcr5_cp_cnt(spr_t1_cpcr5_cp_cnt), +`endif + .spr_cpcr0_fx0_cnt(spr_cpcr0_fx0_cnt), + .spr_cpcr0_fx1_cnt(spr_cpcr0_fx1_cnt), + .spr_cpcr0_lq_cnt(spr_cpcr0_lq_cnt), + .spr_cpcr0_sq_cnt(spr_cpcr0_sq_cnt), + .spr_cpcr1_fu0_cnt(spr_cpcr1_fu0_cnt), + .spr_cpcr1_fu1_cnt(spr_cpcr1_fu1_cnt), + .spr_high_pri_mask(spr_high_pri_mask), + .spr_med_pri_mask(spr_med_pri_mask), + .spr_t0_low_pri_count(spr_t0_low_pri_count), +`ifndef THREADS1 + .spr_t1_low_pri_count(spr_t1_low_pri_count), +`endif + .iu_spr_eheir_update(iu_spr_eheir_update), + .iu_spr_t0_eheir(iu_spr_t0_eheir), +`ifndef THREADS1 + .iu_spr_t1_eheir(iu_spr_t1_eheir), +`endif + .spr_scan_in(scan_in), + .spr_scan_out(scan_out), + .pc_iu_event_bus_enable(pc_iu_event_bus_enable), + .pc_iu_event_count_mode(pc_iu_event_count_mode), + .event_bus_in(event_bus_in[0]), + .event_bus_out(event_bus_out[0]), + .dbg1_scan_in(dbg1_scan_in), + .dbg1_scan_out(dbg1_scan_out), + .pc_iu_trace_bus_enable(pc_iu_trace_bus_enable), + .pc_iu_debug_mux1_ctrls(pc_iu_debug_mux1_ctrls), + .debug_bus_in(debug_bus_in), + .debug_bus_out(ifetch_debug_bus_out), + .coretrace_ctrls_in(coretrace_ctrls_in), + .coretrace_ctrls_out(ifetch_coretrace_ctrls_out) + ); + +// iuq_bht bht0( + tri_bht_1024x8_1r1w bht0( + .gnd(gnd), + .vdd(vdd), + .vcs(vdd), + .nclk(nclk), + .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), + .pc_iu_sg_2(pc_iu_sg_2), + .pc_iu_time_sl_thold_2(pc_iu_time_sl_thold_2), + .pc_iu_abst_sl_thold_2(pc_iu_abst_sl_thold_2), + .pc_iu_ary_nsl_thold_2(pc_iu_ary_nsl_thold_2), + .pc_iu_repr_sl_thold_2(pc_iu_repr_sl_thold_2), + .pc_iu_bolt_sl_thold_2(pc_iu_bolt_sl_thold_2), + .tc_ac_ccflush_dc(tc_ac_ccflush_dc), + .tc_ac_scan_dis_dc_b(tc_ac_scan_dis_dc_b), + .clkoff_b(clkoff_b), + .scan_diag_dc(tc_ac_scan_diag_dc), + .act_dis(act_dis), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .g8t_clkoff_b(g8t_clkoff_b), + .g8t_d_mode(g8t_d_mode), + .g8t_delay_lclkr(g8t_delay_lclkr), + .g8t_mpw1_b(g8t_mpw1_b), + .g8t_mpw2_b(g8t_mpw2_b), + .func_scan_in(bh0_scan_in), + .time_scan_in(1'b0), + .abst_scan_in(1'b0), + .repr_scan_in(1'b0), + .func_scan_out(bh0_scan_out), + .time_scan_out(), + .abst_scan_out(), + .repr_scan_out(), + .pc_iu_abist_di_0(pc_iu_abist_di_0), + .pc_iu_abist_g8t_bw_1(pc_iu_abist_g8t_bw_1), + .pc_iu_abist_g8t_bw_0(pc_iu_abist_g8t_bw_0), + .pc_iu_abist_waddr_0(pc_iu_abist_waddr_0), + .pc_iu_abist_g8t_wenb(pc_iu_abist_g8t_wenb), + .pc_iu_abist_raddr_0(pc_iu_abist_raddr_0[3:9]), + .pc_iu_abist_g8t1p_renb_0(pc_iu_abist_g8t1p_renb_0), + .an_ac_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc), + .pc_iu_abist_ena_dc(pc_iu_abist_ena_dc), + .pc_iu_abist_wl128_comp_ena(pc_iu_abist_wl128_comp_ena), + .pc_iu_abist_raw_dc_b(pc_iu_abist_raw_dc_b), + .pc_iu_abist_g8t_dcomp(pc_iu_abist_g8t_dcomp), + .pc_iu_bo_enable_2(pc_iu_bo_enable_3), + .pc_iu_bo_reset(pc_iu_bo_reset), + .pc_iu_bo_unload(pc_iu_bo_unload), + .pc_iu_bo_repair(pc_iu_bo_repair), + .pc_iu_bo_shdata(pc_iu_bo_shdata), + .pc_iu_bo_select(pc_iu_bo_select[0]), + .iu_pc_bo_fail(), + .iu_pc_bo_diagout(), + .r_act(iu0_bh0_rd_act), + .w_act(ex5_bh0_wr_act), + .r_addr(iu0_bh0_rd_addr[0:9]), + .w_addr(ex5_bh0_wr_addr[0:9]), + .data_in(ex5_bh0_wr_data), + .data_out0(iu2_0_bh0_rd_data), + .data_out1(iu2_1_bh0_rd_data), + .data_out2(iu2_2_bh0_rd_data), + .data_out3(iu2_3_bh0_rd_data), + .pc_iu_init_reset(pc_iu_init_reset) + ); + + +// iuq_bht bht1( + tri_bht_1024x8_1r1w bht1( + .gnd(gnd), + .vdd(vdd), + .vcs(vdd), + .nclk(nclk), + .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), + .pc_iu_sg_2(pc_iu_sg_2), + .pc_iu_time_sl_thold_2(pc_iu_time_sl_thold_2), + .pc_iu_abst_sl_thold_2(pc_iu_abst_sl_thold_2), + .pc_iu_ary_nsl_thold_2(pc_iu_ary_nsl_thold_2), + .pc_iu_repr_sl_thold_2(pc_iu_repr_sl_thold_2), + .pc_iu_bolt_sl_thold_2(pc_iu_bolt_sl_thold_2), + .tc_ac_ccflush_dc(tc_ac_ccflush_dc), + .tc_ac_scan_dis_dc_b(tc_ac_scan_dis_dc_b), + .clkoff_b(clkoff_b), + .scan_diag_dc(tc_ac_scan_diag_dc), + .act_dis(act_dis), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .g8t_clkoff_b(g8t_clkoff_b), + .g8t_d_mode(g8t_d_mode), + .g8t_delay_lclkr(g8t_delay_lclkr), + .g8t_mpw1_b(g8t_mpw1_b), + .g8t_mpw2_b(g8t_mpw2_b), + .func_scan_in(bh1_scan_in), + .time_scan_in(1'b0), + .abst_scan_in(1'b0), + .repr_scan_in(1'b0), + .func_scan_out(bh1_scan_out), + .time_scan_out(), + .abst_scan_out(), + .repr_scan_out(), + .pc_iu_abist_di_0(pc_iu_abist_di_0), + .pc_iu_abist_g8t_bw_1(pc_iu_abist_g8t_bw_1), + .pc_iu_abist_g8t_bw_0(pc_iu_abist_g8t_bw_0), + .pc_iu_abist_waddr_0(pc_iu_abist_waddr_0), + .pc_iu_abist_g8t_wenb(pc_iu_abist_g8t_wenb), + .pc_iu_abist_raddr_0(pc_iu_abist_raddr_0[3:9]), + .pc_iu_abist_g8t1p_renb_0(pc_iu_abist_g8t1p_renb_0), + .an_ac_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc), + .pc_iu_abist_ena_dc(pc_iu_abist_ena_dc), + .pc_iu_abist_wl128_comp_ena(pc_iu_abist_wl128_comp_ena), + .pc_iu_abist_raw_dc_b(pc_iu_abist_raw_dc_b), + .pc_iu_abist_g8t_dcomp(pc_iu_abist_g8t_dcomp), + .pc_iu_bo_enable_2(pc_iu_bo_enable_3), + .pc_iu_bo_reset(pc_iu_bo_reset), + .pc_iu_bo_unload(pc_iu_bo_unload), + .pc_iu_bo_repair(pc_iu_bo_repair), + .pc_iu_bo_shdata(pc_iu_bo_shdata), + .pc_iu_bo_select(pc_iu_bo_select[0]), + .iu_pc_bo_fail(), + .iu_pc_bo_diagout(), + .r_act(iu0_bh1_rd_act), + .w_act(ex5_bh1_wr_act), + .r_addr(iu0_bh1_rd_addr[0:9]), + .w_addr(ex5_bh1_wr_addr[0:9]), + .data_in(ex5_bh1_wr_data), + .data_out0(iu2_0_bh1_rd_data), + .data_out1(iu2_1_bh1_rd_data), + .data_out2(iu2_2_bh1_rd_data), + .data_out3(iu2_3_bh1_rd_data), + .pc_iu_init_reset(pc_iu_init_reset) + ); + +// iuq_bht bht2( + tri_bht_512x4_1r1w bht2( + .gnd(gnd), + .vdd(vdd), + .vcs(vdd), + .nclk(nclk), + .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), + .pc_iu_sg_2(pc_iu_sg_2), + .pc_iu_time_sl_thold_2(pc_iu_time_sl_thold_2), + .pc_iu_abst_sl_thold_2(pc_iu_abst_sl_thold_2), + .pc_iu_ary_nsl_thold_2(pc_iu_ary_nsl_thold_2), + .pc_iu_repr_sl_thold_2(pc_iu_repr_sl_thold_2), + .pc_iu_bolt_sl_thold_2(pc_iu_bolt_sl_thold_2), + .tc_ac_ccflush_dc(tc_ac_ccflush_dc), + .tc_ac_scan_dis_dc_b(tc_ac_scan_dis_dc_b), + .clkoff_b(clkoff_b), + .scan_diag_dc(tc_ac_scan_diag_dc), + .act_dis(act_dis), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .g8t_clkoff_b(g8t_clkoff_b), + .g8t_d_mode(g8t_d_mode), + .g8t_delay_lclkr(g8t_delay_lclkr), + .g8t_mpw1_b(g8t_mpw1_b), + .g8t_mpw2_b(g8t_mpw2_b), + .func_scan_in(bh2_scan_in), + .time_scan_in(1'b0), + .abst_scan_in(1'b0), + .repr_scan_in(1'b0), + .func_scan_out(bh2_scan_out), + .time_scan_out(), + .abst_scan_out(), + .repr_scan_out(), + .pc_iu_abist_di_0(pc_iu_abist_di_0), + .pc_iu_abist_g8t_bw_1(pc_iu_abist_g8t_bw_1), + .pc_iu_abist_g8t_bw_0(pc_iu_abist_g8t_bw_0), + .pc_iu_abist_waddr_0(pc_iu_abist_waddr_0), + .pc_iu_abist_g8t_wenb(pc_iu_abist_g8t_wenb), + .pc_iu_abist_raddr_0(pc_iu_abist_raddr_0[3:9]), + .pc_iu_abist_g8t1p_renb_0(pc_iu_abist_g8t1p_renb_0), + .an_ac_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc), + .pc_iu_abist_ena_dc(pc_iu_abist_ena_dc), + .pc_iu_abist_wl128_comp_ena(pc_iu_abist_wl128_comp_ena), + .pc_iu_abist_raw_dc_b(pc_iu_abist_raw_dc_b), + .pc_iu_abist_g8t_dcomp(pc_iu_abist_g8t_dcomp), + .pc_iu_bo_enable_2(pc_iu_bo_enable_3), + .pc_iu_bo_reset(pc_iu_bo_reset), + .pc_iu_bo_unload(pc_iu_bo_unload), + .pc_iu_bo_repair(pc_iu_bo_repair), + .pc_iu_bo_shdata(pc_iu_bo_shdata), + .pc_iu_bo_select(pc_iu_bo_select[0]), + .iu_pc_bo_fail(), + .iu_pc_bo_diagout(), + .r_act(iu0_bh2_rd_act), + .w_act(ex5_bh2_wr_act), + .r_addr(iu0_bh2_rd_addr[0:8]), + .w_addr(ex5_bh2_wr_addr[0:8]), + .data_in(ex5_bh2_wr_data), + .data_out0(iu2_0_bh2_rd_data), + .data_out1(iu2_1_bh2_rd_data), + .data_out2(iu2_2_bh2_rd_data), + .data_out3(iu2_3_bh2_rd_data), + .pc_iu_init_reset(pc_iu_init_reset) + ); + + //`IBUFF_IFAR_WIDTH => `IBUFF_IFAR_WIDTH, + iuq_slice_top iuq_slice_top0( + //.vdd(vdd), + //.gnd(gnd), + .nclk(nclk), + .pc_iu_sg_2(pc_iu_sg_2), + .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), + .pc_iu_func_slp_sl_thold_2(pc_iu_func_slp_sl_thold_2), + .clkoff_b(clkoff_b), + .act_dis(act_dis), + .tc_ac_ccflush_dc(tc_ac_ccflush_dc), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scan_in(slice_scan_in), + .scan_out(slice_scan_out), + + + .iu_pc_fx0_credit_ok(iu_pc_fx0_credit_ok), + .iu_pc_fx1_credit_ok(iu_pc_fx1_credit_ok), + .iu_pc_lq_credit_ok(iu_pc_lq_credit_ok), + .iu_pc_sq_credit_ok(iu_pc_sq_credit_ok), + .iu_pc_axu0_credit_ok(iu_pc_axu0_credit_ok), + .iu_pc_axu1_credit_ok(iu_pc_axu1_credit_ok), + + //------------------------------- + // Performance interface with I$ + //------------------------------- + .pc_iu_event_bus_enable(pc_iu_event_bus_enable), + .slice_ic_t0_perf_events(slice_ic_t0_perf_events), +`ifndef THREADS1 + .slice_ic_t1_perf_events(slice_ic_t1_perf_events), +`endif + + .spr_dec_mask(spr_dec_mask), + .spr_dec_match(spr_dec_match), + + .xu_iu_ccr2_ucode_dis(xu_iu_spr_ccr2_ucode_dis), + .mm_iu_tlbwe_binv(mm_iu_tlbwe_binv), + .rm_ib_iu3_instr(rm_ib_iu3_instr), + + .cp_iu_iu4_flush(iu_flush), + .cp_flush_into_uc(cp_flush_into_uc), + + .xu_iu_epcr_dgtmi(xu_iu_epcr_dgtmi), + .xu_iu_msrp_uclep(xu_iu_msrp_uclep), + .xu_iu_msr_pr(xu_iu_msr_pr), + .xu_iu_msr_gs(xu_iu_msr_gs), + .xu_iu_msr_ucle(xu_iu_msr_ucle), + .spr_single_issue(spr_single_issue), + + // Input to dispatch to block due to ivax + .cp_dis_ivax(cp_dis_ivax), + + //----------------------------- + // MMU Connections + //----------------------------- + .mm_iu_flush_req(mm_iu_flush_req), + .dp_cp_hold_req(dp_cp_hold_req), + .mm_iu_hold_done(mm_iu_hold_done), + .mm_iu_bus_snoop_hold_req(mm_iu_bus_snoop_hold_req), + .dp_cp_bus_snoop_hold_req(dp_cp_bus_snoop_hold_req), + .mm_iu_bus_snoop_hold_done(mm_iu_bus_snoop_hold_done), + .mm_iu_tlbi_complete(mm_iu_tlbi_complete), + + //---------------------------- + // Credit Interface with IU + //---------------------------- + .rv_iu_fx0_credit_free(rv_iu_fx0_credit_free), + .rv_iu_fx1_credit_free(rv_iu_fx1_credit_free), // Need to add 2nd unit someday + .lq_iu_credit_free(lq_iu_credit_free), + .sq_iu_credit_free(sq_iu_credit_free), + .axu0_iu_credit_free(axu0_iu_credit_free), // credit free from axu reservation station + .axu1_iu_credit_free(axu1_iu_credit_free), // credit free from axu reservation station + + .ib_rm_rdy(ib_rm_rdy), + .rm_ib_iu3_val(rm_ib_iu3_val), + .ib_uc_rdy(ib_uc_rdy), + .uc_ib_done(uc_ib_done), + + .iu_flush(iu_flush), + .cp_flush(cp_flush_internal), + .br_iu_redirect(br_iu_redirect), + .uc_ib_iu3_flush_all(uc_ib_iu3_flush_all), + .cp_rn_uc_credit_free(cp_rn_uc_credit_free), + .xu_iu_run_thread(xu_iu_run_thread), + .iu_xu_credits_returned(iu_xu_credits_returned), + + //----------------------------- + // SPR connections + //----------------------------- + .spr_cpcr_we(spr_cpcr_we), + .spr_t0_cpcr2_fx0_cnt(spr_t0_cpcr2_fx0_cnt), + .spr_t0_cpcr2_fx1_cnt(spr_t0_cpcr2_fx1_cnt), + .spr_t0_cpcr2_lq_cnt(spr_t0_cpcr2_lq_cnt), + .spr_t0_cpcr2_sq_cnt(spr_t0_cpcr2_sq_cnt), + .spr_t0_cpcr3_fu0_cnt(spr_t0_cpcr3_fu0_cnt), + .spr_t0_cpcr3_fu1_cnt(spr_t0_cpcr3_fu1_cnt), + .spr_t0_cpcr3_cp_cnt(spr_t0_cpcr3_cp_cnt), + .spr_t0_cpcr4_fx0_cnt(spr_t0_cpcr4_fx0_cnt), + .spr_t0_cpcr4_fx1_cnt(spr_t0_cpcr4_fx1_cnt), + .spr_t0_cpcr4_lq_cnt(spr_t0_cpcr4_lq_cnt), + .spr_t0_cpcr4_sq_cnt(spr_t0_cpcr4_sq_cnt), + .spr_t0_cpcr5_fu0_cnt(spr_t0_cpcr5_fu0_cnt), + .spr_t0_cpcr5_fu1_cnt(spr_t0_cpcr5_fu1_cnt), + .spr_t0_cpcr5_cp_cnt(spr_t0_cpcr5_cp_cnt), +`ifndef THREADS1 + .spr_t1_cpcr2_fx0_cnt(spr_t1_cpcr2_fx0_cnt), + .spr_t1_cpcr2_fx1_cnt(spr_t1_cpcr2_fx1_cnt), + .spr_t1_cpcr2_lq_cnt(spr_t1_cpcr2_lq_cnt), + .spr_t1_cpcr2_sq_cnt(spr_t1_cpcr2_sq_cnt), + .spr_t1_cpcr3_fu0_cnt(spr_t1_cpcr3_fu0_cnt), + .spr_t1_cpcr3_fu1_cnt(spr_t1_cpcr3_fu1_cnt), + .spr_t1_cpcr3_cp_cnt(spr_t1_cpcr3_cp_cnt), + .spr_t1_cpcr4_fx0_cnt(spr_t1_cpcr4_fx0_cnt), + .spr_t1_cpcr4_fx1_cnt(spr_t1_cpcr4_fx1_cnt), + .spr_t1_cpcr4_lq_cnt(spr_t1_cpcr4_lq_cnt), + .spr_t1_cpcr4_sq_cnt(spr_t1_cpcr4_sq_cnt), + .spr_t1_cpcr5_fu0_cnt(spr_t1_cpcr5_fu0_cnt), + .spr_t1_cpcr5_fu1_cnt(spr_t1_cpcr5_fu1_cnt), + .spr_t1_cpcr5_cp_cnt(spr_t1_cpcr5_cp_cnt), +`endif + .spr_cpcr0_fx0_cnt(spr_cpcr0_fx0_cnt), + .spr_cpcr0_fx1_cnt(spr_cpcr0_fx1_cnt), + .spr_cpcr0_lq_cnt(spr_cpcr0_lq_cnt), + .spr_cpcr0_sq_cnt(spr_cpcr0_sq_cnt), + .spr_cpcr1_fu0_cnt(spr_cpcr1_fu0_cnt), + .spr_cpcr1_fu1_cnt(spr_cpcr1_fu1_cnt), + .spr_high_pri_mask(spr_high_pri_mask), + .spr_med_pri_mask(spr_med_pri_mask), + .spr_t0_low_pri_count(spr_t0_low_pri_count), +`ifndef THREADS1 + .spr_t1_low_pri_count(spr_t1_low_pri_count), +`endif + + //----------------------------- + // SPR values + //----------------------------- + .iu_au_t0_config_iucr(iu_au_t0_config_iucr), + + //---------------------------- + // Ucode interface with IB + //---------------------------- + .uc_ib_iu3_t0_invalid(uc_ib_iu3_t0_invalid), + .uc_ib_t0_val(uc_ib_t0_val), + .uc_ib_t0_instr0(uc_ib_t0_instr0), + .uc_ib_t0_instr1(uc_ib_t0_instr1), + .uc_ib_t0_ifar0(uc_ib_t0_ifar0), + .uc_ib_t0_ifar1(uc_ib_t0_ifar1), + .uc_ib_t0_ext0(uc_ib_t0_ext0), + .uc_ib_t0_ext1(uc_ib_t0_ext1), + + //---------------------------- + // Completion Interface + //---------------------------- + .cp_rn_empty(cp_rn_empty), + .cp_rn_t0_i0_axu_exception_val(cp_rn_t0_i0_axu_exception_val), + .cp_rn_t0_i0_axu_exception(cp_rn_t0_i0_axu_exception), + .cp_rn_t0_i1_axu_exception_val(cp_rn_t0_i1_axu_exception_val), + .cp_rn_t0_i1_axu_exception(cp_rn_t0_i1_axu_exception), + .cp_rn_t0_i0_v(cp_rn_t0_i0_v), + .cp_rn_t0_i0_itag(iu_lq_t0_i0_completed_itag_int), + .cp_rn_t0_i0_t1_v(cp_rn_t0_i0_t1_v), + .cp_rn_t0_i0_t1_t(cp_rn_t0_i0_t1_t), + .cp_rn_t0_i0_t1_p(cp_rn_t0_i0_t1_p), + .cp_rn_t0_i0_t1_a(cp_rn_t0_i0_t1_a), + .cp_rn_t0_i0_t2_v(cp_rn_t0_i0_t2_v), + .cp_rn_t0_i0_t2_t(cp_rn_t0_i0_t2_t), + .cp_rn_t0_i0_t2_p(cp_rn_t0_i0_t2_p), + .cp_rn_t0_i0_t2_a(cp_rn_t0_i0_t2_a), + .cp_rn_t0_i0_t3_v(cp_rn_t0_i0_t3_v), + .cp_rn_t0_i0_t3_t(cp_rn_t0_i0_t3_t), + .cp_rn_t0_i0_t3_p(cp_rn_t0_i0_t3_p), + .cp_rn_t0_i0_t3_a(cp_rn_t0_i0_t3_a), + + .cp_rn_t0_i1_v(cp_rn_t0_i1_v), + .cp_rn_t0_i1_itag(iu_lq_t0_i1_completed_itag_int), + .cp_rn_t0_i1_t1_v(cp_rn_t0_i1_t1_v), + .cp_rn_t0_i1_t1_t(cp_rn_t0_i1_t1_t), + .cp_rn_t0_i1_t1_p(cp_rn_t0_i1_t1_p), + .cp_rn_t0_i1_t1_a(cp_rn_t0_i1_t1_a), + .cp_rn_t0_i1_t2_v(cp_rn_t0_i1_t2_v), + .cp_rn_t0_i1_t2_t(cp_rn_t0_i1_t2_t), + .cp_rn_t0_i1_t2_p(cp_rn_t0_i1_t2_p), + .cp_rn_t0_i1_t2_a(cp_rn_t0_i1_t2_a), + .cp_rn_t0_i1_t3_v(cp_rn_t0_i1_t3_v), + .cp_rn_t0_i1_t3_t(cp_rn_t0_i1_t3_t), + .cp_rn_t0_i1_t3_p(cp_rn_t0_i1_t3_p), + .cp_rn_t0_i1_t3_a(cp_rn_t0_i1_t3_a), + + //---------------------------------------------------------------- + // Interface to reservation station - Completion is snooping also + //---------------------------------------------------------------- + .iu_rv_iu6_t0_i0_vld(rn_cp_iu6_t0_i0_vld), + .iu_rv_iu6_t0_i0_act(iu_rv_iu6_t0_i0_act), + .iu_rv_iu6_t0_i0_itag(rn_cp_iu6_t0_i0_itag), + .iu_rv_iu6_t0_i0_ucode(rn_cp_iu6_t0_i0_ucode), + .iu_rv_iu6_t0_i0_ucode_cnt(iu_rv_iu6_t0_i0_ucode_cnt), + .iu_rv_iu6_t0_i0_2ucode(iu_rv_iu6_t0_i0_2ucode), + .iu_rv_iu6_t0_i0_fuse_nop(rn_cp_iu6_t0_i0_fuse_nop), + .iu_rv_iu6_t0_i0_rte_lq(rn_cp_iu6_t0_i0_rte_lq), + .iu_rv_iu6_t0_i0_rte_sq(rn_cp_iu6_t0_i0_rte_sq), + .iu_rv_iu6_t0_i0_rte_fx0(rn_cp_iu6_t0_i0_rte_fx0), + .iu_rv_iu6_t0_i0_rte_fx1(rn_cp_iu6_t0_i0_rte_fx1), + .iu_rv_iu6_t0_i0_rte_axu0(rn_cp_iu6_t0_i0_rte_axu0), + .iu_rv_iu6_t0_i0_rte_axu1(rn_cp_iu6_t0_i0_rte_axu1), + .iu_rv_iu6_t0_i0_valop(rn_cp_iu6_t0_i0_valop), + .iu_rv_iu6_t0_i0_ord(iu_rv_iu6_t0_i0_ord), + .iu_rv_iu6_t0_i0_cord(iu_rv_iu6_t0_i0_cord), + .iu_rv_iu6_t0_i0_error(rn_cp_iu6_t0_i0_error), + .iu_rv_iu6_t0_i0_btb_entry(rn_cp_iu6_t0_i0_btb_entry), + .iu_rv_iu6_t0_i0_btb_hist(rn_cp_iu6_t0_i0_btb_hist), + .iu_rv_iu6_t0_i0_bta_val(rn_cp_iu6_t0_i0_bta_val), + .iu_rv_iu6_t0_i0_fusion(iu_rv_iu6_t0_i0_fusion), + .iu_rv_iu6_t0_i0_spec(iu_rv_iu6_t0_i0_spec), + .iu_rv_iu6_t0_i0_type_fp(rn_cp_iu6_t0_i0_type_fp), + .iu_rv_iu6_t0_i0_type_ap(rn_cp_iu6_t0_i0_type_ap), + .iu_rv_iu6_t0_i0_type_spv(rn_cp_iu6_t0_i0_type_spv), + .iu_rv_iu6_t0_i0_type_st(rn_cp_iu6_t0_i0_type_st), + .iu_rv_iu6_t0_i0_async_block(rn_cp_iu6_t0_i0_async_block), + .iu_rv_iu6_t0_i0_np1_flush(rn_cp_iu6_t0_i0_np1_flush), + .iu_rv_iu6_t0_i0_isram(rn_cp_iu6_t0_i0_isram), + .iu_rv_iu6_t0_i0_isload(iu_rv_iu6_t0_i0_isload), + .iu_rv_iu6_t0_i0_isstore(iu_rv_iu6_t0_i0_isstore), + .iu_rv_iu6_t0_i0_instr(rn_cp_iu6_t0_i0_instr), + .iu_rv_iu6_t0_i0_ifar(rn_cp_iu6_t0_i0_ifar), + .iu_rv_iu6_t0_i0_bta(rn_cp_iu6_t0_i0_bta), + .iu_rv_iu6_t0_i0_br_pred(rn_cp_iu6_t0_i0_br_pred), + .iu_rv_iu6_t0_i0_bh_update(rn_cp_iu6_t0_i0_bh_update), + .iu_rv_iu6_t0_i0_bh0_hist(rn_cp_iu6_t0_i0_bh0_hist), + .iu_rv_iu6_t0_i0_bh1_hist(rn_cp_iu6_t0_i0_bh1_hist), + .iu_rv_iu6_t0_i0_bh2_hist(rn_cp_iu6_t0_i0_bh2_hist), + .iu_rv_iu6_t0_i0_gshare(rn_cp_iu6_t0_i0_gshare), + .iu_rv_iu6_t0_i0_ls_ptr(rn_cp_iu6_t0_i0_ls_ptr), + .iu_rv_iu6_t0_i0_match(rn_cp_iu6_t0_i0_match), + .iu_rv_iu6_t0_i0_ilat(iu_rv_iu6_t0_i0_ilat), + .iu_rv_iu6_t0_i0_t1_v(rn_cp_iu6_t0_i0_t1_v), + .iu_rv_iu6_t0_i0_t1_t(rn_cp_iu6_t0_i0_t1_t), + .iu_rv_iu6_t0_i0_t1_a(rn_cp_iu6_t0_i0_t1_a), + .iu_rv_iu6_t0_i0_t1_p(rn_cp_iu6_t0_i0_t1_p), + .iu_rv_iu6_t0_i0_t2_v(rn_cp_iu6_t0_i0_t2_v), + .iu_rv_iu6_t0_i0_t2_a(rn_cp_iu6_t0_i0_t2_a), + .iu_rv_iu6_t0_i0_t2_p(rn_cp_iu6_t0_i0_t2_p), + .iu_rv_iu6_t0_i0_t2_t(rn_cp_iu6_t0_i0_t2_t), + .iu_rv_iu6_t0_i0_t3_v(rn_cp_iu6_t0_i0_t3_v), + .iu_rv_iu6_t0_i0_t3_a(rn_cp_iu6_t0_i0_t3_a), + .iu_rv_iu6_t0_i0_t3_p(rn_cp_iu6_t0_i0_t3_p), + .iu_rv_iu6_t0_i0_t3_t(rn_cp_iu6_t0_i0_t3_t), + .iu_rv_iu6_t0_i0_s1_v(iu_rv_iu6_t0_i0_s1_v), + .iu_rv_iu6_t0_i0_s1_a(iu_rv_iu6_t0_i0_s1_a), + .iu_rv_iu6_t0_i0_s1_p(iu_rv_iu6_t0_i0_s1_p), + .iu_rv_iu6_t0_i0_s1_itag(iu_rv_iu6_t0_i0_s1_itag), + .iu_rv_iu6_t0_i0_s1_t(iu_rv_iu6_t0_i0_s1_t), + .iu_rv_iu6_t0_i0_s2_v(iu_rv_iu6_t0_i0_s2_v), + .iu_rv_iu6_t0_i0_s2_a(iu_rv_iu6_t0_i0_s2_a), + .iu_rv_iu6_t0_i0_s2_p(iu_rv_iu6_t0_i0_s2_p), + .iu_rv_iu6_t0_i0_s2_itag(iu_rv_iu6_t0_i0_s2_itag), + .iu_rv_iu6_t0_i0_s2_t(iu_rv_iu6_t0_i0_s2_t), + .iu_rv_iu6_t0_i0_s3_v(iu_rv_iu6_t0_i0_s3_v), + .iu_rv_iu6_t0_i0_s3_a(iu_rv_iu6_t0_i0_s3_a), + .iu_rv_iu6_t0_i0_s3_p(iu_rv_iu6_t0_i0_s3_p), + .iu_rv_iu6_t0_i0_s3_itag(iu_rv_iu6_t0_i0_s3_itag), + .iu_rv_iu6_t0_i0_s3_t(iu_rv_iu6_t0_i0_s3_t), + + .iu_rv_iu6_t0_i1_vld(rn_cp_iu6_t0_i1_vld), + .iu_rv_iu6_t0_i1_act(iu_rv_iu6_t0_i1_act), + .iu_rv_iu6_t0_i1_itag(rn_cp_iu6_t0_i1_itag), + .iu_rv_iu6_t0_i1_ucode(rn_cp_iu6_t0_i1_ucode), + .iu_rv_iu6_t0_i1_ucode_cnt(iu_rv_iu6_t0_i1_ucode_cnt), + .iu_rv_iu6_t0_i1_fuse_nop(rn_cp_iu6_t0_i1_fuse_nop), + .iu_rv_iu6_t0_i1_rte_lq(rn_cp_iu6_t0_i1_rte_lq), + .iu_rv_iu6_t0_i1_rte_sq(rn_cp_iu6_t0_i1_rte_sq), + .iu_rv_iu6_t0_i1_rte_fx0(rn_cp_iu6_t0_i1_rte_fx0), + .iu_rv_iu6_t0_i1_rte_fx1(rn_cp_iu6_t0_i1_rte_fx1), + .iu_rv_iu6_t0_i1_rte_axu0(rn_cp_iu6_t0_i1_rte_axu0), + .iu_rv_iu6_t0_i1_rte_axu1(rn_cp_iu6_t0_i1_rte_axu1), + .iu_rv_iu6_t0_i1_valop(rn_cp_iu6_t0_i1_valop), + .iu_rv_iu6_t0_i1_ord(iu_rv_iu6_t0_i1_ord), + .iu_rv_iu6_t0_i1_cord(iu_rv_iu6_t0_i1_cord), + .iu_rv_iu6_t0_i1_error(rn_cp_iu6_t0_i1_error), + .iu_rv_iu6_t0_i1_btb_entry(rn_cp_iu6_t0_i1_btb_entry), + .iu_rv_iu6_t0_i1_btb_hist(rn_cp_iu6_t0_i1_btb_hist), + .iu_rv_iu6_t0_i1_bta_val(rn_cp_iu6_t0_i1_bta_val), + .iu_rv_iu6_t0_i1_fusion(iu_rv_iu6_t0_i1_fusion), + .iu_rv_iu6_t0_i1_spec(iu_rv_iu6_t0_i1_spec), + .iu_rv_iu6_t0_i1_type_fp(rn_cp_iu6_t0_i1_type_fp), + .iu_rv_iu6_t0_i1_type_ap(rn_cp_iu6_t0_i1_type_ap), + .iu_rv_iu6_t0_i1_type_spv(rn_cp_iu6_t0_i1_type_spv), + .iu_rv_iu6_t0_i1_type_st(rn_cp_iu6_t0_i1_type_st), + .iu_rv_iu6_t0_i1_async_block(rn_cp_iu6_t0_i1_async_block), + .iu_rv_iu6_t0_i1_np1_flush(rn_cp_iu6_t0_i1_np1_flush), + .iu_rv_iu6_t0_i1_isram(rn_cp_iu6_t0_i1_isram), + .iu_rv_iu6_t0_i1_isload(iu_rv_iu6_t0_i1_isload), + .iu_rv_iu6_t0_i1_isstore(iu_rv_iu6_t0_i1_isstore), + .iu_rv_iu6_t0_i1_instr(rn_cp_iu6_t0_i1_instr), + .iu_rv_iu6_t0_i1_ifar(rn_cp_iu6_t0_i1_ifar), + .iu_rv_iu6_t0_i1_bta(rn_cp_iu6_t0_i1_bta), + .iu_rv_iu6_t0_i1_br_pred(rn_cp_iu6_t0_i1_br_pred), + .iu_rv_iu6_t0_i1_bh_update(rn_cp_iu6_t0_i1_bh_update), + .iu_rv_iu6_t0_i1_bh0_hist(rn_cp_iu6_t0_i1_bh0_hist), + .iu_rv_iu6_t0_i1_bh1_hist(rn_cp_iu6_t0_i1_bh1_hist), + .iu_rv_iu6_t0_i1_bh2_hist(rn_cp_iu6_t0_i1_bh2_hist), + .iu_rv_iu6_t0_i1_gshare(rn_cp_iu6_t0_i1_gshare), + .iu_rv_iu6_t0_i1_ls_ptr(rn_cp_iu6_t0_i1_ls_ptr), + .iu_rv_iu6_t0_i1_match(rn_cp_iu6_t0_i1_match), + .iu_rv_iu6_t0_i1_ilat(iu_rv_iu6_t0_i1_ilat), + .iu_rv_iu6_t0_i1_t1_v(rn_cp_iu6_t0_i1_t1_v), + .iu_rv_iu6_t0_i1_t1_t(rn_cp_iu6_t0_i1_t1_t), + .iu_rv_iu6_t0_i1_t1_a(rn_cp_iu6_t0_i1_t1_a), + .iu_rv_iu6_t0_i1_t1_p(rn_cp_iu6_t0_i1_t1_p), + .iu_rv_iu6_t0_i1_t2_v(rn_cp_iu6_t0_i1_t2_v), + .iu_rv_iu6_t0_i1_t2_a(rn_cp_iu6_t0_i1_t2_a), + .iu_rv_iu6_t0_i1_t2_p(rn_cp_iu6_t0_i1_t2_p), + .iu_rv_iu6_t0_i1_t2_t(rn_cp_iu6_t0_i1_t2_t), + .iu_rv_iu6_t0_i1_t3_v(rn_cp_iu6_t0_i1_t3_v), + .iu_rv_iu6_t0_i1_t3_a(rn_cp_iu6_t0_i1_t3_a), + .iu_rv_iu6_t0_i1_t3_p(rn_cp_iu6_t0_i1_t3_p), + .iu_rv_iu6_t0_i1_t3_t(rn_cp_iu6_t0_i1_t3_t), + .iu_rv_iu6_t0_i1_s1_v(iu_rv_iu6_t0_i1_s1_v), + .iu_rv_iu6_t0_i1_s1_a(iu_rv_iu6_t0_i1_s1_a), + .iu_rv_iu6_t0_i1_s1_p(iu_rv_iu6_t0_i1_s1_p), + .iu_rv_iu6_t0_i1_s1_itag(iu_rv_iu6_t0_i1_s1_itag), + .iu_rv_iu6_t0_i1_s1_t(iu_rv_iu6_t0_i1_s1_t), + .iu_rv_iu6_t0_i1_s1_dep_hit(iu_rv_iu6_t0_i1_s1_dep_hit), + .iu_rv_iu6_t0_i1_s2_v(iu_rv_iu6_t0_i1_s2_v), + .iu_rv_iu6_t0_i1_s2_a(iu_rv_iu6_t0_i1_s2_a), + .iu_rv_iu6_t0_i1_s2_p(iu_rv_iu6_t0_i1_s2_p), + .iu_rv_iu6_t0_i1_s2_itag(iu_rv_iu6_t0_i1_s2_itag), + .iu_rv_iu6_t0_i1_s2_t(iu_rv_iu6_t0_i1_s2_t), + .iu_rv_iu6_t0_i1_s2_dep_hit(iu_rv_iu6_t0_i1_s2_dep_hit), + .iu_rv_iu6_t0_i1_s3_v(iu_rv_iu6_t0_i1_s3_v), + .iu_rv_iu6_t0_i1_s3_a(iu_rv_iu6_t0_i1_s3_a), + .iu_rv_iu6_t0_i1_s3_p(iu_rv_iu6_t0_i1_s3_p), + .iu_rv_iu6_t0_i1_s3_itag(iu_rv_iu6_t0_i1_s3_itag), + .iu_rv_iu6_t0_i1_s3_t(iu_rv_iu6_t0_i1_s3_t), + .iu_rv_iu6_t0_i1_s3_dep_hit(iu_rv_iu6_t0_i1_s3_dep_hit), +`ifndef THREADS1 + //----------------------------- + // SPR values + //----------------------------- + .iu_au_t1_config_iucr(iu_au_t1_config_iucr), + + //---------------------------- + // Ucode interface with IB + //---------------------------- + .uc_ib_iu3_t1_invalid(uc_ib_iu3_t1_invalid), + .uc_ib_t1_val(uc_ib_t1_val), + .uc_ib_t1_instr0(uc_ib_t1_instr0), + .uc_ib_t1_instr1(uc_ib_t1_instr1), + .uc_ib_t1_ifar0(uc_ib_t1_ifar0), + .uc_ib_t1_ifar1(uc_ib_t1_ifar1), + .uc_ib_t1_ext0(uc_ib_t1_ext0), + .uc_ib_t1_ext1(uc_ib_t1_ext1), + + //---------------------------- + // Completion Interface + //---------------------------- + .cp_rn_t1_i0_axu_exception_val(cp_rn_t1_i0_axu_exception_val), + .cp_rn_t1_i0_axu_exception(cp_rn_t1_i0_axu_exception), + .cp_rn_t1_i1_axu_exception_val(cp_rn_t1_i1_axu_exception_val), + .cp_rn_t1_i1_axu_exception(cp_rn_t1_i1_axu_exception), + .cp_rn_t1_i0_v(cp_rn_t1_i0_v), + .cp_rn_t1_i0_itag(iu_lq_t1_i0_completed_itag_int), + .cp_rn_t1_i0_t1_v(cp_rn_t1_i0_t1_v), + .cp_rn_t1_i0_t1_t(cp_rn_t1_i0_t1_t), + .cp_rn_t1_i0_t1_p(cp_rn_t1_i0_t1_p), + .cp_rn_t1_i0_t1_a(cp_rn_t1_i0_t1_a), + .cp_rn_t1_i0_t2_v(cp_rn_t1_i0_t2_v), + .cp_rn_t1_i0_t2_t(cp_rn_t1_i0_t2_t), + .cp_rn_t1_i0_t2_p(cp_rn_t1_i0_t2_p), + .cp_rn_t1_i0_t2_a(cp_rn_t1_i0_t2_a), + .cp_rn_t1_i0_t3_v(cp_rn_t1_i0_t3_v), + .cp_rn_t1_i0_t3_t(cp_rn_t1_i0_t3_t), + .cp_rn_t1_i0_t3_p(cp_rn_t1_i0_t3_p), + .cp_rn_t1_i0_t3_a(cp_rn_t1_i0_t3_a), + + .cp_rn_t1_i1_v(cp_rn_t1_i1_v), + .cp_rn_t1_i1_itag(iu_lq_t1_i1_completed_itag_int), + .cp_rn_t1_i1_t1_v(cp_rn_t1_i1_t1_v), + .cp_rn_t1_i1_t1_t(cp_rn_t1_i1_t1_t), + .cp_rn_t1_i1_t1_p(cp_rn_t1_i1_t1_p), + .cp_rn_t1_i1_t1_a(cp_rn_t1_i1_t1_a), + .cp_rn_t1_i1_t2_v(cp_rn_t1_i1_t2_v), + .cp_rn_t1_i1_t2_t(cp_rn_t1_i1_t2_t), + .cp_rn_t1_i1_t2_p(cp_rn_t1_i1_t2_p), + .cp_rn_t1_i1_t2_a(cp_rn_t1_i1_t2_a), + .cp_rn_t1_i1_t3_v(cp_rn_t1_i1_t3_v), + .cp_rn_t1_i1_t3_t(cp_rn_t1_i1_t3_t), + .cp_rn_t1_i1_t3_p(cp_rn_t1_i1_t3_p), + .cp_rn_t1_i1_t3_a(cp_rn_t1_i1_t3_a), + + .iu_rv_iu6_t1_i0_vld(rn_cp_iu6_t1_i0_vld), + .iu_rv_iu6_t1_i0_act(iu_rv_iu6_t1_i0_act), + .iu_rv_iu6_t1_i0_itag(rn_cp_iu6_t1_i0_itag), + .iu_rv_iu6_t1_i0_ucode(rn_cp_iu6_t1_i0_ucode), + .iu_rv_iu6_t1_i0_ucode_cnt(iu_rv_iu6_t1_i0_ucode_cnt), + .iu_rv_iu6_t1_i0_2ucode(iu_rv_iu6_t1_i0_2ucode), + .iu_rv_iu6_t1_i0_fuse_nop(rn_cp_iu6_t1_i0_fuse_nop), + .iu_rv_iu6_t1_i0_rte_lq(rn_cp_iu6_t1_i0_rte_lq), + .iu_rv_iu6_t1_i0_rte_sq(rn_cp_iu6_t1_i0_rte_sq), + .iu_rv_iu6_t1_i0_rte_fx0(rn_cp_iu6_t1_i0_rte_fx0), + .iu_rv_iu6_t1_i0_rte_fx1(rn_cp_iu6_t1_i0_rte_fx1), + .iu_rv_iu6_t1_i0_rte_axu0(rn_cp_iu6_t1_i0_rte_axu0), + .iu_rv_iu6_t1_i0_rte_axu1(rn_cp_iu6_t1_i0_rte_axu1), + .iu_rv_iu6_t1_i0_valop(rn_cp_iu6_t1_i0_valop), + .iu_rv_iu6_t1_i0_ord(iu_rv_iu6_t1_i0_ord), + .iu_rv_iu6_t1_i0_cord(iu_rv_iu6_t1_i0_cord), + .iu_rv_iu6_t1_i0_error(rn_cp_iu6_t1_i0_error), + .iu_rv_iu6_t1_i0_btb_entry(rn_cp_iu6_t1_i0_btb_entry), + .iu_rv_iu6_t1_i0_btb_hist(rn_cp_iu6_t1_i0_btb_hist), + .iu_rv_iu6_t1_i0_bta_val(rn_cp_iu6_t1_i0_bta_val), + .iu_rv_iu6_t1_i0_fusion(iu_rv_iu6_t1_i0_fusion), + .iu_rv_iu6_t1_i0_spec(iu_rv_iu6_t1_i0_spec), + .iu_rv_iu6_t1_i0_type_fp(rn_cp_iu6_t1_i0_type_fp), + .iu_rv_iu6_t1_i0_type_ap(rn_cp_iu6_t1_i0_type_ap), + .iu_rv_iu6_t1_i0_type_spv(rn_cp_iu6_t1_i0_type_spv), + .iu_rv_iu6_t1_i0_type_st(rn_cp_iu6_t1_i0_type_st), + .iu_rv_iu6_t1_i0_async_block(rn_cp_iu6_t1_i0_async_block), + .iu_rv_iu6_t1_i0_np1_flush(rn_cp_iu6_t1_i0_np1_flush), + .iu_rv_iu6_t1_i0_isram(rn_cp_iu6_t1_i0_isram), + .iu_rv_iu6_t1_i0_isload(iu_rv_iu6_t1_i0_isload), + .iu_rv_iu6_t1_i0_isstore(iu_rv_iu6_t1_i0_isstore), + .iu_rv_iu6_t1_i0_instr(rn_cp_iu6_t1_i0_instr), + .iu_rv_iu6_t1_i0_ifar(rn_cp_iu6_t1_i0_ifar), + .iu_rv_iu6_t1_i0_bta(rn_cp_iu6_t1_i0_bta), + .iu_rv_iu6_t1_i0_br_pred(rn_cp_iu6_t1_i0_br_pred), + .iu_rv_iu6_t1_i0_bh_update(rn_cp_iu6_t1_i0_bh_update), + .iu_rv_iu6_t1_i0_bh0_hist(rn_cp_iu6_t1_i0_bh0_hist), + .iu_rv_iu6_t1_i0_bh1_hist(rn_cp_iu6_t1_i0_bh1_hist), + .iu_rv_iu6_t1_i0_bh2_hist(rn_cp_iu6_t1_i0_bh2_hist), + .iu_rv_iu6_t1_i0_gshare(rn_cp_iu6_t1_i0_gshare), + .iu_rv_iu6_t1_i0_ls_ptr(rn_cp_iu6_t1_i0_ls_ptr), + .iu_rv_iu6_t1_i0_match(rn_cp_iu6_t1_i0_match), + .iu_rv_iu6_t1_i0_ilat(iu_rv_iu6_t1_i0_ilat), + .iu_rv_iu6_t1_i0_t1_v(rn_cp_iu6_t1_i0_t1_v), + .iu_rv_iu6_t1_i0_t1_t(rn_cp_iu6_t1_i0_t1_t), + .iu_rv_iu6_t1_i0_t1_a(rn_cp_iu6_t1_i0_t1_a), + .iu_rv_iu6_t1_i0_t1_p(rn_cp_iu6_t1_i0_t1_p), + .iu_rv_iu6_t1_i0_t2_v(rn_cp_iu6_t1_i0_t2_v), + .iu_rv_iu6_t1_i0_t2_a(rn_cp_iu6_t1_i0_t2_a), + .iu_rv_iu6_t1_i0_t2_p(rn_cp_iu6_t1_i0_t2_p), + .iu_rv_iu6_t1_i0_t2_t(rn_cp_iu6_t1_i0_t2_t), + .iu_rv_iu6_t1_i0_t3_v(rn_cp_iu6_t1_i0_t3_v), + .iu_rv_iu6_t1_i0_t3_a(rn_cp_iu6_t1_i0_t3_a), + .iu_rv_iu6_t1_i0_t3_p(rn_cp_iu6_t1_i0_t3_p), + .iu_rv_iu6_t1_i0_t3_t(rn_cp_iu6_t1_i0_t3_t), + .iu_rv_iu6_t1_i0_s1_v(iu_rv_iu6_t1_i0_s1_v), + .iu_rv_iu6_t1_i0_s1_a(iu_rv_iu6_t1_i0_s1_a), + .iu_rv_iu6_t1_i0_s1_p(iu_rv_iu6_t1_i0_s1_p), + .iu_rv_iu6_t1_i0_s1_itag(iu_rv_iu6_t1_i0_s1_itag), + .iu_rv_iu6_t1_i0_s1_t(iu_rv_iu6_t1_i0_s1_t), + .iu_rv_iu6_t1_i0_s2_v(iu_rv_iu6_t1_i0_s2_v), + .iu_rv_iu6_t1_i0_s2_a(iu_rv_iu6_t1_i0_s2_a), + .iu_rv_iu6_t1_i0_s2_p(iu_rv_iu6_t1_i0_s2_p), + .iu_rv_iu6_t1_i0_s2_itag(iu_rv_iu6_t1_i0_s2_itag), + .iu_rv_iu6_t1_i0_s2_t(iu_rv_iu6_t1_i0_s2_t), + .iu_rv_iu6_t1_i0_s3_v(iu_rv_iu6_t1_i0_s3_v), + .iu_rv_iu6_t1_i0_s3_a(iu_rv_iu6_t1_i0_s3_a), + .iu_rv_iu6_t1_i0_s3_p(iu_rv_iu6_t1_i0_s3_p), + .iu_rv_iu6_t1_i0_s3_itag(iu_rv_iu6_t1_i0_s3_itag), + .iu_rv_iu6_t1_i0_s3_t(iu_rv_iu6_t1_i0_s3_t), + + .iu_rv_iu6_t1_i1_vld(rn_cp_iu6_t1_i1_vld), + .iu_rv_iu6_t1_i1_act(iu_rv_iu6_t1_i1_act), + .iu_rv_iu6_t1_i1_itag(rn_cp_iu6_t1_i1_itag), + .iu_rv_iu6_t1_i1_ucode(rn_cp_iu6_t1_i1_ucode), + .iu_rv_iu6_t1_i1_ucode_cnt(iu_rv_iu6_t1_i1_ucode_cnt), + .iu_rv_iu6_t1_i1_fuse_nop(rn_cp_iu6_t1_i1_fuse_nop), + .iu_rv_iu6_t1_i1_rte_lq(rn_cp_iu6_t1_i1_rte_lq), + .iu_rv_iu6_t1_i1_rte_sq(rn_cp_iu6_t1_i1_rte_sq), + .iu_rv_iu6_t1_i1_rte_fx0(rn_cp_iu6_t1_i1_rte_fx0), + .iu_rv_iu6_t1_i1_rte_fx1(rn_cp_iu6_t1_i1_rte_fx1), + .iu_rv_iu6_t1_i1_rte_axu0(rn_cp_iu6_t1_i1_rte_axu0), + .iu_rv_iu6_t1_i1_rte_axu1(rn_cp_iu6_t1_i1_rte_axu1), + .iu_rv_iu6_t1_i1_valop(rn_cp_iu6_t1_i1_valop), + .iu_rv_iu6_t1_i1_ord(iu_rv_iu6_t1_i1_ord), + .iu_rv_iu6_t1_i1_cord(iu_rv_iu6_t1_i1_cord), + .iu_rv_iu6_t1_i1_error(rn_cp_iu6_t1_i1_error), + .iu_rv_iu6_t1_i1_btb_entry(rn_cp_iu6_t1_i1_btb_entry), + .iu_rv_iu6_t1_i1_btb_hist(rn_cp_iu6_t1_i1_btb_hist), + .iu_rv_iu6_t1_i1_bta_val(rn_cp_iu6_t1_i1_bta_val), + .iu_rv_iu6_t1_i1_fusion(iu_rv_iu6_t1_i1_fusion), + .iu_rv_iu6_t1_i1_spec(iu_rv_iu6_t1_i1_spec), + .iu_rv_iu6_t1_i1_type_fp(rn_cp_iu6_t1_i1_type_fp), + .iu_rv_iu6_t1_i1_type_ap(rn_cp_iu6_t1_i1_type_ap), + .iu_rv_iu6_t1_i1_type_spv(rn_cp_iu6_t1_i1_type_spv), + .iu_rv_iu6_t1_i1_type_st(rn_cp_iu6_t1_i1_type_st), + .iu_rv_iu6_t1_i1_async_block(rn_cp_iu6_t1_i1_async_block), + .iu_rv_iu6_t1_i1_np1_flush(rn_cp_iu6_t1_i1_np1_flush), + .iu_rv_iu6_t1_i1_isram(rn_cp_iu6_t1_i1_isram), + .iu_rv_iu6_t1_i1_isload(iu_rv_iu6_t1_i1_isload), + .iu_rv_iu6_t1_i1_isstore(iu_rv_iu6_t1_i1_isstore), + .iu_rv_iu6_t1_i1_instr(rn_cp_iu6_t1_i1_instr), + .iu_rv_iu6_t1_i1_ifar(rn_cp_iu6_t1_i1_ifar), + .iu_rv_iu6_t1_i1_bta(rn_cp_iu6_t1_i1_bta), + .iu_rv_iu6_t1_i1_br_pred(rn_cp_iu6_t1_i1_br_pred), + .iu_rv_iu6_t1_i1_bh_update(rn_cp_iu6_t1_i1_bh_update), + .iu_rv_iu6_t1_i1_bh0_hist(rn_cp_iu6_t1_i1_bh0_hist), + .iu_rv_iu6_t1_i1_bh1_hist(rn_cp_iu6_t1_i1_bh1_hist), + .iu_rv_iu6_t1_i1_bh2_hist(rn_cp_iu6_t1_i1_bh2_hist), + .iu_rv_iu6_t1_i1_gshare(rn_cp_iu6_t1_i1_gshare), + .iu_rv_iu6_t1_i1_ls_ptr(rn_cp_iu6_t1_i1_ls_ptr), + .iu_rv_iu6_t1_i1_match(rn_cp_iu6_t1_i1_match), + .iu_rv_iu6_t1_i1_ilat(iu_rv_iu6_t1_i1_ilat), + .iu_rv_iu6_t1_i1_t1_v(rn_cp_iu6_t1_i1_t1_v), + .iu_rv_iu6_t1_i1_t1_t(rn_cp_iu6_t1_i1_t1_t), + .iu_rv_iu6_t1_i1_t1_a(rn_cp_iu6_t1_i1_t1_a), + .iu_rv_iu6_t1_i1_t1_p(rn_cp_iu6_t1_i1_t1_p), + .iu_rv_iu6_t1_i1_t2_v(rn_cp_iu6_t1_i1_t2_v), + .iu_rv_iu6_t1_i1_t2_a(rn_cp_iu6_t1_i1_t2_a), + .iu_rv_iu6_t1_i1_t2_p(rn_cp_iu6_t1_i1_t2_p), + .iu_rv_iu6_t1_i1_t2_t(rn_cp_iu6_t1_i1_t2_t), + .iu_rv_iu6_t1_i1_t3_v(rn_cp_iu6_t1_i1_t3_v), + .iu_rv_iu6_t1_i1_t3_a(rn_cp_iu6_t1_i1_t3_a), + .iu_rv_iu6_t1_i1_t3_p(rn_cp_iu6_t1_i1_t3_p), + .iu_rv_iu6_t1_i1_t3_t(rn_cp_iu6_t1_i1_t3_t), + .iu_rv_iu6_t1_i1_s1_v(iu_rv_iu6_t1_i1_s1_v), + .iu_rv_iu6_t1_i1_s1_a(iu_rv_iu6_t1_i1_s1_a), + .iu_rv_iu6_t1_i1_s1_p(iu_rv_iu6_t1_i1_s1_p), + .iu_rv_iu6_t1_i1_s1_itag(iu_rv_iu6_t1_i1_s1_itag), + .iu_rv_iu6_t1_i1_s1_t(iu_rv_iu6_t1_i1_s1_t), + .iu_rv_iu6_t1_i1_s1_dep_hit(iu_rv_iu6_t1_i1_s1_dep_hit), + .iu_rv_iu6_t1_i1_s2_v(iu_rv_iu6_t1_i1_s2_v), + .iu_rv_iu6_t1_i1_s2_a(iu_rv_iu6_t1_i1_s2_a), + .iu_rv_iu6_t1_i1_s2_p(iu_rv_iu6_t1_i1_s2_p), + .iu_rv_iu6_t1_i1_s2_itag(iu_rv_iu6_t1_i1_s2_itag), + .iu_rv_iu6_t1_i1_s2_t(iu_rv_iu6_t1_i1_s2_t), + .iu_rv_iu6_t1_i1_s2_dep_hit(iu_rv_iu6_t1_i1_s2_dep_hit), + .iu_rv_iu6_t1_i1_s3_v(iu_rv_iu6_t1_i1_s3_v), + .iu_rv_iu6_t1_i1_s3_a(iu_rv_iu6_t1_i1_s3_a), + .iu_rv_iu6_t1_i1_s3_p(iu_rv_iu6_t1_i1_s3_p), + .iu_rv_iu6_t1_i1_s3_itag(iu_rv_iu6_t1_i1_s3_itag), + .iu_rv_iu6_t1_i1_s3_t(iu_rv_iu6_t1_i1_s3_t), + .iu_rv_iu6_t1_i1_s3_dep_hit(iu_rv_iu6_t1_i1_s3_dep_hit), +`endif + //---------------------------- + // Ifetch with slice + //---------------------------- +`ifndef THREADS1 + .ib_ic_t1_need_fetch(ib_ic_t1_need_fetch), + .bp_ib_iu3_t1_val(bp_ib_iu3_t1_val), + .bp_ib_iu3_t1_ifar(bp_ib_iu3_t1_ifar), + .bp_ib_iu3_t1_bta(bp_ib_iu3_t1_bta), + .bp_ib_iu3_t1_0_instr(bp_ib_iu3_t1_0_instr), + .bp_ib_iu3_t1_1_instr(bp_ib_iu3_t1_1_instr), + .bp_ib_iu3_t1_2_instr(bp_ib_iu3_t1_2_instr), + .bp_ib_iu3_t1_3_instr(bp_ib_iu3_t1_3_instr), +`endif + .ib_ic_t0_need_fetch(ib_ic_t0_need_fetch), + .bp_ib_iu3_t0_ifar(bp_ib_iu3_t0_ifar), + .bp_ib_iu3_t0_bta(bp_ib_iu3_t0_bta), + .bp_ib_iu3_t0_0_instr(bp_ib_iu3_t0_0_instr), + .bp_ib_iu3_t0_1_instr(bp_ib_iu3_t0_1_instr), + .bp_ib_iu3_t0_2_instr(bp_ib_iu3_t0_2_instr), + .bp_ib_iu3_t0_3_instr(bp_ib_iu3_t0_3_instr), + .bp_ib_iu3_t0_val(bp_ib_iu3_t0_val) + + ); + + assign iu_rv_iu6_t0_i0_vld = rn_cp_iu6_t0_i0_vld; + assign iu_rv_iu6_t0_i0_itag = rn_cp_iu6_t0_i0_itag; + assign iu_rv_iu6_t0_i0_ucode = rn_cp_iu6_t0_i0_ucode; + assign iu_rv_iu6_t0_i0_rte_lq = rn_cp_iu6_t0_i0_rte_lq; + assign iu_rv_iu6_t0_i0_rte_sq = rn_cp_iu6_t0_i0_rte_sq; + assign iu_rv_iu6_t0_i0_rte_fx0 = rn_cp_iu6_t0_i0_rte_fx0; + assign iu_rv_iu6_t0_i0_rte_fx1 = rn_cp_iu6_t0_i0_rte_fx1; + assign iu_rv_iu6_t0_i0_rte_axu0 = rn_cp_iu6_t0_i0_rte_axu0; + assign iu_rv_iu6_t0_i0_rte_axu1 = rn_cp_iu6_t0_i0_rte_axu1; + assign iu_rv_iu6_t0_i0_instr = rn_cp_iu6_t0_i0_instr; + assign iu_rv_iu6_t0_i0_ifar = rn_cp_iu6_t0_i0_ifar; + assign iu_rv_iu6_t0_i0_bta = rn_cp_iu6_t0_i0_bta; + assign iu_rv_iu6_t0_i0_br_pred = rn_cp_iu6_t0_i0_br_pred; + assign iu_rv_iu6_t0_i0_bh_update = rn_cp_iu6_t0_i0_bh_update; + assign iu_rv_iu6_t0_i0_gshare = rn_cp_iu6_t0_i0_gshare; + assign iu_rv_iu6_t0_i0_ls_ptr = rn_cp_iu6_t0_i0_ls_ptr; + assign iu_rv_iu6_t0_i0_t1_v = rn_cp_iu6_t0_i0_t1_v; + assign iu_rv_iu6_t0_i0_t1_t = rn_cp_iu6_t0_i0_t1_t; + assign iu_rv_iu6_t0_i0_t1_p = rn_cp_iu6_t0_i0_t1_p; + assign iu_rv_iu6_t0_i0_t2_v = rn_cp_iu6_t0_i0_t2_v; + assign iu_rv_iu6_t0_i0_t2_p = rn_cp_iu6_t0_i0_t2_p; + assign iu_rv_iu6_t0_i0_t2_t = rn_cp_iu6_t0_i0_t2_t; + assign iu_rv_iu6_t0_i0_t3_v = rn_cp_iu6_t0_i0_t3_v; + assign iu_rv_iu6_t0_i0_t3_p = rn_cp_iu6_t0_i0_t3_p; + assign iu_rv_iu6_t0_i0_t3_t = rn_cp_iu6_t0_i0_t3_t; + assign iu_rv_iu6_t0_i0_bta_val = rn_cp_iu6_t0_i0_bta_val; + assign iu_rv_iu6_t0_i1_vld = rn_cp_iu6_t0_i1_vld; + assign iu_rv_iu6_t0_i1_itag = rn_cp_iu6_t0_i1_itag; + assign iu_rv_iu6_t0_i1_ucode = rn_cp_iu6_t0_i1_ucode; + assign iu_rv_iu6_t0_i1_rte_lq = rn_cp_iu6_t0_i1_rte_lq; + assign iu_rv_iu6_t0_i1_rte_sq = rn_cp_iu6_t0_i1_rte_sq; + assign iu_rv_iu6_t0_i1_rte_fx0 = rn_cp_iu6_t0_i1_rte_fx0; + assign iu_rv_iu6_t0_i1_rte_fx1 = rn_cp_iu6_t0_i1_rte_fx1; + assign iu_rv_iu6_t0_i1_rte_axu0 = rn_cp_iu6_t0_i1_rte_axu0; + assign iu_rv_iu6_t0_i1_rte_axu1 = rn_cp_iu6_t0_i1_rte_axu1; + assign iu_rv_iu6_t0_i1_instr = rn_cp_iu6_t0_i1_instr; + assign iu_rv_iu6_t0_i1_ifar = rn_cp_iu6_t0_i1_ifar; + assign iu_rv_iu6_t0_i1_bta = rn_cp_iu6_t0_i1_bta; + assign iu_rv_iu6_t0_i1_br_pred = rn_cp_iu6_t0_i1_br_pred; + assign iu_rv_iu6_t0_i1_bh_update = rn_cp_iu6_t0_i1_bh_update; + assign iu_rv_iu6_t0_i1_gshare = rn_cp_iu6_t0_i1_gshare; + assign iu_rv_iu6_t0_i1_ls_ptr = rn_cp_iu6_t0_i1_ls_ptr; + assign iu_rv_iu6_t0_i1_t1_v = rn_cp_iu6_t0_i1_t1_v; + assign iu_rv_iu6_t0_i1_t1_t = rn_cp_iu6_t0_i1_t1_t; + assign iu_rv_iu6_t0_i1_t1_p = rn_cp_iu6_t0_i1_t1_p; + assign iu_rv_iu6_t0_i1_t2_v = rn_cp_iu6_t0_i1_t2_v; + assign iu_rv_iu6_t0_i1_t2_p = rn_cp_iu6_t0_i1_t2_p; + assign iu_rv_iu6_t0_i1_t2_t = rn_cp_iu6_t0_i1_t2_t; + assign iu_rv_iu6_t0_i1_t3_v = rn_cp_iu6_t0_i1_t3_v; + assign iu_rv_iu6_t0_i1_t3_p = rn_cp_iu6_t0_i1_t3_p; + assign iu_rv_iu6_t0_i1_t3_t = rn_cp_iu6_t0_i1_t3_t; + assign iu_rv_iu6_t0_i1_bta_val = rn_cp_iu6_t0_i1_bta_val; +`ifndef THREADS1 + assign iu_rv_iu6_t1_i0_vld = rn_cp_iu6_t1_i0_vld; + assign iu_rv_iu6_t1_i0_itag = rn_cp_iu6_t1_i0_itag; + assign iu_rv_iu6_t1_i0_ucode = rn_cp_iu6_t1_i0_ucode; + assign iu_rv_iu6_t1_i0_rte_lq = rn_cp_iu6_t1_i0_rte_lq; + assign iu_rv_iu6_t1_i0_rte_sq = rn_cp_iu6_t1_i0_rte_sq; + assign iu_rv_iu6_t1_i0_rte_fx0 = rn_cp_iu6_t1_i0_rte_fx0; + assign iu_rv_iu6_t1_i0_rte_fx1 = rn_cp_iu6_t1_i0_rte_fx1; + assign iu_rv_iu6_t1_i0_rte_axu0 = rn_cp_iu6_t1_i0_rte_axu0; + assign iu_rv_iu6_t1_i0_rte_axu1 = rn_cp_iu6_t1_i0_rte_axu1; + assign iu_rv_iu6_t1_i0_instr = rn_cp_iu6_t1_i0_instr; + assign iu_rv_iu6_t1_i0_ifar = rn_cp_iu6_t1_i0_ifar; + assign iu_rv_iu6_t1_i0_bta = rn_cp_iu6_t1_i0_bta; + assign iu_rv_iu6_t1_i0_br_pred = rn_cp_iu6_t1_i0_br_pred; + assign iu_rv_iu6_t1_i0_bh_update = rn_cp_iu6_t1_i0_bh_update; + assign iu_rv_iu6_t1_i0_gshare = rn_cp_iu6_t1_i0_gshare; + assign iu_rv_iu6_t1_i0_ls_ptr = rn_cp_iu6_t1_i0_ls_ptr; + assign iu_rv_iu6_t1_i0_t1_v = rn_cp_iu6_t1_i0_t1_v; + assign iu_rv_iu6_t1_i0_t1_t = rn_cp_iu6_t1_i0_t1_t; + assign iu_rv_iu6_t1_i0_t1_p = rn_cp_iu6_t1_i0_t1_p; + assign iu_rv_iu6_t1_i0_t2_v = rn_cp_iu6_t1_i0_t2_v; + assign iu_rv_iu6_t1_i0_t2_p = rn_cp_iu6_t1_i0_t2_p; + assign iu_rv_iu6_t1_i0_t2_t = rn_cp_iu6_t1_i0_t2_t; + assign iu_rv_iu6_t1_i0_t3_v = rn_cp_iu6_t1_i0_t3_v; + assign iu_rv_iu6_t1_i0_t3_p = rn_cp_iu6_t1_i0_t3_p; + assign iu_rv_iu6_t1_i0_t3_t = rn_cp_iu6_t1_i0_t3_t; + assign iu_rv_iu6_t1_i0_bta_val = rn_cp_iu6_t1_i0_bta_val; + assign iu_rv_iu6_t1_i1_vld = rn_cp_iu6_t1_i1_vld; + assign iu_rv_iu6_t1_i1_itag = rn_cp_iu6_t1_i1_itag; + assign iu_rv_iu6_t1_i1_ucode = rn_cp_iu6_t1_i1_ucode; + assign iu_rv_iu6_t1_i1_rte_lq = rn_cp_iu6_t1_i1_rte_lq; + assign iu_rv_iu6_t1_i1_rte_sq = rn_cp_iu6_t1_i1_rte_sq; + assign iu_rv_iu6_t1_i1_rte_fx0 = rn_cp_iu6_t1_i1_rte_fx0; + assign iu_rv_iu6_t1_i1_rte_fx1 = rn_cp_iu6_t1_i1_rte_fx1; + assign iu_rv_iu6_t1_i1_rte_axu0 = rn_cp_iu6_t1_i1_rte_axu0; + assign iu_rv_iu6_t1_i1_rte_axu1 = rn_cp_iu6_t1_i1_rte_axu1; + assign iu_rv_iu6_t1_i1_instr = rn_cp_iu6_t1_i1_instr; + assign iu_rv_iu6_t1_i1_ifar = rn_cp_iu6_t1_i1_ifar; + assign iu_rv_iu6_t1_i1_bta = rn_cp_iu6_t1_i1_bta; + assign iu_rv_iu6_t1_i1_br_pred = rn_cp_iu6_t1_i1_br_pred; + assign iu_rv_iu6_t1_i1_bh_update = rn_cp_iu6_t1_i1_bh_update; + assign iu_rv_iu6_t1_i1_gshare = rn_cp_iu6_t1_i1_gshare; + assign iu_rv_iu6_t1_i1_ls_ptr = rn_cp_iu6_t1_i1_ls_ptr; + assign iu_rv_iu6_t1_i1_t1_v = rn_cp_iu6_t1_i1_t1_v; + assign iu_rv_iu6_t1_i1_t1_t = rn_cp_iu6_t1_i1_t1_t; + assign iu_rv_iu6_t1_i1_t1_p = rn_cp_iu6_t1_i1_t1_p; + assign iu_rv_iu6_t1_i1_t2_v = rn_cp_iu6_t1_i1_t2_v; + assign iu_rv_iu6_t1_i1_t2_p = rn_cp_iu6_t1_i1_t2_p; + assign iu_rv_iu6_t1_i1_t2_t = rn_cp_iu6_t1_i1_t2_t; + assign iu_rv_iu6_t1_i1_t3_v = rn_cp_iu6_t1_i1_t3_v; + assign iu_rv_iu6_t1_i1_t3_p = rn_cp_iu6_t1_i1_t3_p; + assign iu_rv_iu6_t1_i1_t3_t = rn_cp_iu6_t1_i1_t3_t; + assign iu_rv_iu6_t1_i1_bta_val = rn_cp_iu6_t1_i1_bta_val; +`endif + + // FPSCR, update on completion. Use t1 type, but no dependency +`ifdef THREADS1 + assign cp_axu_i1_t1_v = cp_rn_t0_i1_t1_v; + assign cp_axu_i0_t1_v = cp_rn_t0_i0_t1_v; +`endif +`ifndef THREADS1 + assign cp_axu_i1_t1_v = {cp_rn_t0_i1_t1_v, cp_rn_t1_i1_t1_v}; + assign cp_axu_i0_t1_v = {cp_rn_t0_i0_t1_v, cp_rn_t1_i0_t1_v}; +`endif + assign cp_axu_t0_i0_t1_t = cp_rn_t0_i0_t1_t; + assign cp_axu_t0_i0_t1_p = cp_rn_t0_i0_t1_p; + assign cp_axu_t0_i1_t1_t = cp_rn_t0_i1_t1_t; + assign cp_axu_t0_i1_t1_p = cp_rn_t0_i1_t1_p; +`ifndef THREADS1 + assign cp_axu_t1_i0_t1_t = cp_rn_t1_i0_t1_t; + assign cp_axu_t1_i0_t1_p = cp_rn_t1_i0_t1_p; + assign cp_axu_t1_i1_t1_t = cp_rn_t1_i1_t1_t; + assign cp_axu_t1_i1_t1_p = cp_rn_t1_i1_t1_p; +`endif + + iuq_cpl_top iuq_cpl_top0( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .tc_ac_ccflush_dc(tc_ac_ccflush_dc), + .clkoff_dc_b(clkoff_b), + .d_mode_dc(d_mode), + .delay_lclkr_dc(delay_lclkr), + .mpw1_dc_b(mpw1_b), + .mpw2_dc_b(mpw2_b), + .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), + .pc_iu_func_slp_sl_thold_2(pc_iu_func_slp_sl_thold_2), + .pc_iu_sg_2(pc_iu_sg_2), + .cp_scan_in(cp_scan_in), + .cp_scan_out(cp_scan_out), + .pc_iu_event_bus_enable(pc_iu_event_bus_enable), + .pc_iu_event_count_mode(pc_iu_event_count_mode), + .spr_cp_perf_event_mux_ctrls(spr_cp_perf_event_mux_ctrls), + .event_bus_in(event_bus_in[1]), + .event_bus_out(event_bus_out[1]), + .rn_cp_iu6_t0_i0_vld(rn_cp_iu6_t0_i0_vld), + .rn_cp_iu6_t0_i0_itag(rn_cp_iu6_t0_i0_itag[1:`ITAG_SIZE_ENC-1]), + .rn_cp_iu6_t0_i0_ucode(rn_cp_iu6_t0_i0_ucode), + .rn_cp_iu6_t0_i0_fuse_nop(rn_cp_iu6_t0_i0_fuse_nop), + .rn_cp_iu6_t0_i0_rte_lq(rn_cp_iu6_t0_i0_rte_lq), + .rn_cp_iu6_t0_i0_rte_sq(rn_cp_iu6_t0_i0_rte_sq), + .rn_cp_iu6_t0_i0_rte_fx0(rn_cp_iu6_t0_i0_rte_fx0), + .rn_cp_iu6_t0_i0_rte_fx1(rn_cp_iu6_t0_i0_rte_fx1), + .rn_cp_iu6_t0_i0_rte_axu0(rn_cp_iu6_t0_i0_rte_axu0), + .rn_cp_iu6_t0_i0_rte_axu1(rn_cp_iu6_t0_i0_rte_axu1), + .rn_cp_iu6_t0_i0_ifar(rn_cp_iu6_t0_i0_ifar), + .rn_cp_iu6_t0_i0_bta(rn_cp_iu6_t0_i0_bta), + .rn_cp_iu6_t0_i0_isram(rn_cp_iu6_t0_i0_isram), + .rn_cp_iu6_t0_i0_instr(rn_cp_iu6_t0_i0_instr), + .rn_cp_iu6_t0_i0_valop(rn_cp_iu6_t0_i0_valop), + .rn_cp_iu6_t0_i0_error(rn_cp_iu6_t0_i0_error), + .rn_cp_iu6_t0_i0_br_pred(rn_cp_iu6_t0_i0_br_pred), + .rn_cp_iu6_t0_i0_bh_update(rn_cp_iu6_t0_i0_bh_update), + .rn_cp_iu6_t0_i0_bh0_hist(rn_cp_iu6_t0_i0_bh0_hist), + .rn_cp_iu6_t0_i0_bh1_hist(rn_cp_iu6_t0_i0_bh1_hist), + .rn_cp_iu6_t0_i0_bh2_hist(rn_cp_iu6_t0_i0_bh2_hist), + .rn_cp_iu6_t0_i0_gshare(rn_cp_iu6_t0_i0_gshare[0:9]), + .rn_cp_iu6_t0_i0_ls_ptr(rn_cp_iu6_t0_i0_ls_ptr), + .rn_cp_iu6_t0_i0_match(rn_cp_iu6_t0_i0_match), + .rn_cp_iu6_t0_i0_type_fp(rn_cp_iu6_t0_i0_type_fp), + .rn_cp_iu6_t0_i0_type_ap(rn_cp_iu6_t0_i0_type_ap), + .rn_cp_iu6_t0_i0_type_spv(rn_cp_iu6_t0_i0_type_spv), + .rn_cp_iu6_t0_i0_type_st(rn_cp_iu6_t0_i0_type_st), + .rn_cp_iu6_t0_i0_async_block(rn_cp_iu6_t0_i0_async_block), + .rn_cp_iu6_t0_i0_np1_flush(rn_cp_iu6_t0_i0_np1_flush), + .rn_cp_iu6_t0_i0_t1_v(rn_cp_iu6_t0_i0_t1_v), + .rn_cp_iu6_t0_i0_t1_t(rn_cp_iu6_t0_i0_t1_t), + .rn_cp_iu6_t0_i0_t1_p(rn_cp_iu6_t0_i0_t1_p), + .rn_cp_iu6_t0_i0_t1_a(rn_cp_iu6_t0_i0_t1_a), + .rn_cp_iu6_t0_i0_t2_v(rn_cp_iu6_t0_i0_t2_v), + .rn_cp_iu6_t0_i0_t2_t(rn_cp_iu6_t0_i0_t2_t), + .rn_cp_iu6_t0_i0_t2_p(rn_cp_iu6_t0_i0_t2_p), + .rn_cp_iu6_t0_i0_t2_a(rn_cp_iu6_t0_i0_t2_a), + .rn_cp_iu6_t0_i0_t3_v(rn_cp_iu6_t0_i0_t3_v), + .rn_cp_iu6_t0_i0_t3_t(rn_cp_iu6_t0_i0_t3_t), + .rn_cp_iu6_t0_i0_t3_p(rn_cp_iu6_t0_i0_t3_p), + .rn_cp_iu6_t0_i0_t3_a(rn_cp_iu6_t0_i0_t3_a), + .rn_cp_iu6_t0_i0_btb_entry(rn_cp_iu6_t0_i0_btb_entry), + .rn_cp_iu6_t0_i0_btb_hist(rn_cp_iu6_t0_i0_btb_hist), + .rn_cp_iu6_t0_i0_bta_val(rn_cp_iu6_t0_i0_bta_val), + .rn_cp_iu6_t0_i1_vld(rn_cp_iu6_t0_i1_vld), + .rn_cp_iu6_t0_i1_itag(rn_cp_iu6_t0_i1_itag[1:`ITAG_SIZE_ENC-1]), + .rn_cp_iu6_t0_i1_ucode(rn_cp_iu6_t0_i1_ucode), + .rn_cp_iu6_t0_i1_fuse_nop(rn_cp_iu6_t0_i1_fuse_nop), + .rn_cp_iu6_t0_i1_rte_lq(rn_cp_iu6_t0_i1_rte_lq), + .rn_cp_iu6_t0_i1_rte_sq(rn_cp_iu6_t0_i1_rte_sq), + .rn_cp_iu6_t0_i1_rte_fx0(rn_cp_iu6_t0_i1_rte_fx0), + .rn_cp_iu6_t0_i1_rte_fx1(rn_cp_iu6_t0_i1_rte_fx1), + .rn_cp_iu6_t0_i1_rte_axu0(rn_cp_iu6_t0_i1_rte_axu0), + .rn_cp_iu6_t0_i1_rte_axu1(rn_cp_iu6_t0_i1_rte_axu1), + .rn_cp_iu6_t0_i1_ifar(rn_cp_iu6_t0_i1_ifar), + .rn_cp_iu6_t0_i1_bta(rn_cp_iu6_t0_i1_bta), + .rn_cp_iu6_t0_i1_isram(rn_cp_iu6_t0_i1_isram), + .rn_cp_iu6_t0_i1_instr(rn_cp_iu6_t0_i1_instr), + .rn_cp_iu6_t0_i1_valop(rn_cp_iu6_t0_i1_valop), + .rn_cp_iu6_t0_i1_error(rn_cp_iu6_t0_i1_error), + .rn_cp_iu6_t0_i1_br_pred(rn_cp_iu6_t0_i1_br_pred), + .rn_cp_iu6_t0_i1_bh_update(rn_cp_iu6_t0_i1_bh_update), + .rn_cp_iu6_t0_i1_bh0_hist(rn_cp_iu6_t0_i1_bh0_hist), + .rn_cp_iu6_t0_i1_bh1_hist(rn_cp_iu6_t0_i1_bh1_hist), + .rn_cp_iu6_t0_i1_bh2_hist(rn_cp_iu6_t0_i1_bh2_hist), + .rn_cp_iu6_t0_i1_gshare(rn_cp_iu6_t0_i1_gshare[0:9]), + .rn_cp_iu6_t0_i1_ls_ptr(rn_cp_iu6_t0_i1_ls_ptr), + .rn_cp_iu6_t0_i1_match(rn_cp_iu6_t0_i1_match), + .rn_cp_iu6_t0_i1_type_fp(rn_cp_iu6_t0_i1_type_fp), + .rn_cp_iu6_t0_i1_type_ap(rn_cp_iu6_t0_i1_type_ap), + .rn_cp_iu6_t0_i1_type_spv(rn_cp_iu6_t0_i1_type_spv), + .rn_cp_iu6_t0_i1_type_st(rn_cp_iu6_t0_i1_type_st), + .rn_cp_iu6_t0_i1_async_block(rn_cp_iu6_t0_i1_async_block), + .rn_cp_iu6_t0_i1_np1_flush(rn_cp_iu6_t0_i1_np1_flush), + .rn_cp_iu6_t0_i1_t1_v(rn_cp_iu6_t0_i1_t1_v), + .rn_cp_iu6_t0_i1_t1_t(rn_cp_iu6_t0_i1_t1_t), + .rn_cp_iu6_t0_i1_t1_p(rn_cp_iu6_t0_i1_t1_p), + .rn_cp_iu6_t0_i1_t1_a(rn_cp_iu6_t0_i1_t1_a), + .rn_cp_iu6_t0_i1_t2_v(rn_cp_iu6_t0_i1_t2_v), + .rn_cp_iu6_t0_i1_t2_t(rn_cp_iu6_t0_i1_t2_t), + .rn_cp_iu6_t0_i1_t2_p(rn_cp_iu6_t0_i1_t2_p), + .rn_cp_iu6_t0_i1_t2_a(rn_cp_iu6_t0_i1_t2_a), + .rn_cp_iu6_t0_i1_t3_v(rn_cp_iu6_t0_i1_t3_v), + .rn_cp_iu6_t0_i1_t3_t(rn_cp_iu6_t0_i1_t3_t), + .rn_cp_iu6_t0_i1_t3_p(rn_cp_iu6_t0_i1_t3_p), + .rn_cp_iu6_t0_i1_t3_a(rn_cp_iu6_t0_i1_t3_a), + .rn_cp_iu6_t0_i1_btb_entry(rn_cp_iu6_t0_i1_btb_entry), + .rn_cp_iu6_t0_i1_btb_hist(rn_cp_iu6_t0_i1_btb_hist), + .rn_cp_iu6_t0_i1_bta_val(rn_cp_iu6_t0_i1_bta_val), +`ifndef THREADS1 + .rn_cp_iu6_t1_i0_vld(rn_cp_iu6_t1_i0_vld), + .rn_cp_iu6_t1_i0_itag(rn_cp_iu6_t1_i0_itag[1:`ITAG_SIZE_ENC-1]), + .rn_cp_iu6_t1_i0_ucode(rn_cp_iu6_t1_i0_ucode), + .rn_cp_iu6_t1_i0_fuse_nop(rn_cp_iu6_t1_i0_fuse_nop), + .rn_cp_iu6_t1_i0_rte_lq(rn_cp_iu6_t1_i0_rte_lq), + .rn_cp_iu6_t1_i0_rte_sq(rn_cp_iu6_t1_i0_rte_sq), + .rn_cp_iu6_t1_i0_rte_fx0(rn_cp_iu6_t1_i0_rte_fx0), + .rn_cp_iu6_t1_i0_rte_fx1(rn_cp_iu6_t1_i0_rte_fx1), + .rn_cp_iu6_t1_i0_rte_axu0(rn_cp_iu6_t1_i0_rte_axu0), + .rn_cp_iu6_t1_i0_rte_axu1(rn_cp_iu6_t1_i0_rte_axu1), + .rn_cp_iu6_t1_i0_ifar(rn_cp_iu6_t1_i0_ifar), + .rn_cp_iu6_t1_i0_bta(rn_cp_iu6_t1_i0_bta), + .rn_cp_iu6_t1_i0_isram(rn_cp_iu6_t1_i0_isram), + .rn_cp_iu6_t1_i0_instr(rn_cp_iu6_t1_i0_instr), + .rn_cp_iu6_t1_i0_valop(rn_cp_iu6_t1_i0_valop), + .rn_cp_iu6_t1_i0_error(rn_cp_iu6_t1_i0_error), + .rn_cp_iu6_t1_i0_br_pred(rn_cp_iu6_t1_i0_br_pred), + .rn_cp_iu6_t1_i0_bh_update(rn_cp_iu6_t1_i0_bh_update), + .rn_cp_iu6_t1_i0_bh0_hist(rn_cp_iu6_t1_i0_bh0_hist), + .rn_cp_iu6_t1_i0_bh1_hist(rn_cp_iu6_t1_i0_bh1_hist), + .rn_cp_iu6_t1_i0_bh2_hist(rn_cp_iu6_t1_i0_bh2_hist), + .rn_cp_iu6_t1_i0_gshare(rn_cp_iu6_t1_i0_gshare[0:9]), + .rn_cp_iu6_t1_i0_ls_ptr(rn_cp_iu6_t1_i0_ls_ptr), + .rn_cp_iu6_t1_i0_match(rn_cp_iu6_t1_i0_match), + .rn_cp_iu6_t1_i0_type_fp(rn_cp_iu6_t1_i0_type_fp), + .rn_cp_iu6_t1_i0_type_ap(rn_cp_iu6_t1_i0_type_ap), + .rn_cp_iu6_t1_i0_type_spv(rn_cp_iu6_t1_i0_type_spv), + .rn_cp_iu6_t1_i0_type_st(rn_cp_iu6_t1_i0_type_st), + .rn_cp_iu6_t1_i0_async_block(rn_cp_iu6_t1_i0_async_block), + .rn_cp_iu6_t1_i0_np1_flush(rn_cp_iu6_t1_i0_np1_flush), + .rn_cp_iu6_t1_i0_t1_v(rn_cp_iu6_t1_i0_t1_v), + .rn_cp_iu6_t1_i0_t1_t(rn_cp_iu6_t1_i0_t1_t), + .rn_cp_iu6_t1_i0_t1_p(rn_cp_iu6_t1_i0_t1_p), + .rn_cp_iu6_t1_i0_t1_a(rn_cp_iu6_t1_i0_t1_a), + .rn_cp_iu6_t1_i0_t2_v(rn_cp_iu6_t1_i0_t2_v), + .rn_cp_iu6_t1_i0_t2_t(rn_cp_iu6_t1_i0_t2_t), + .rn_cp_iu6_t1_i0_t2_p(rn_cp_iu6_t1_i0_t2_p), + .rn_cp_iu6_t1_i0_t2_a(rn_cp_iu6_t1_i0_t2_a), + .rn_cp_iu6_t1_i0_t3_v(rn_cp_iu6_t1_i0_t3_v), + .rn_cp_iu6_t1_i0_t3_t(rn_cp_iu6_t1_i0_t3_t), + .rn_cp_iu6_t1_i0_t3_p(rn_cp_iu6_t1_i0_t3_p), + .rn_cp_iu6_t1_i0_t3_a(rn_cp_iu6_t1_i0_t3_a), + .rn_cp_iu6_t1_i0_btb_entry(rn_cp_iu6_t1_i0_btb_entry), + .rn_cp_iu6_t1_i0_btb_hist(rn_cp_iu6_t1_i0_btb_hist), + .rn_cp_iu6_t1_i0_bta_val(rn_cp_iu6_t1_i0_bta_val), + .rn_cp_iu6_t1_i1_vld(rn_cp_iu6_t1_i1_vld), + .rn_cp_iu6_t1_i1_itag(rn_cp_iu6_t1_i1_itag[1:`ITAG_SIZE_ENC-1]), + .rn_cp_iu6_t1_i1_ucode(rn_cp_iu6_t1_i1_ucode), + .rn_cp_iu6_t1_i1_fuse_nop(rn_cp_iu6_t1_i1_fuse_nop), + .rn_cp_iu6_t1_i1_rte_lq(rn_cp_iu6_t1_i1_rte_lq), + .rn_cp_iu6_t1_i1_rte_sq(rn_cp_iu6_t1_i1_rte_sq), + .rn_cp_iu6_t1_i1_rte_fx0(rn_cp_iu6_t1_i1_rte_fx0), + .rn_cp_iu6_t1_i1_rte_fx1(rn_cp_iu6_t1_i1_rte_fx1), + .rn_cp_iu6_t1_i1_rte_axu0(rn_cp_iu6_t1_i1_rte_axu0), + .rn_cp_iu6_t1_i1_rte_axu1(rn_cp_iu6_t1_i1_rte_axu1), + .rn_cp_iu6_t1_i1_ifar(rn_cp_iu6_t1_i1_ifar), + .rn_cp_iu6_t1_i1_bta(rn_cp_iu6_t1_i1_bta), + .rn_cp_iu6_t1_i1_isram(rn_cp_iu6_t1_i1_isram), + .rn_cp_iu6_t1_i1_instr(rn_cp_iu6_t1_i1_instr), + .rn_cp_iu6_t1_i1_valop(rn_cp_iu6_t1_i1_valop), + .rn_cp_iu6_t1_i1_error(rn_cp_iu6_t1_i1_error), + .rn_cp_iu6_t1_i1_br_pred(rn_cp_iu6_t1_i1_br_pred), + .rn_cp_iu6_t1_i1_bh_update(rn_cp_iu6_t1_i1_bh_update), + .rn_cp_iu6_t1_i1_bh0_hist(rn_cp_iu6_t1_i1_bh0_hist), + .rn_cp_iu6_t1_i1_bh1_hist(rn_cp_iu6_t1_i1_bh1_hist), + .rn_cp_iu6_t1_i1_bh2_hist(rn_cp_iu6_t1_i1_bh2_hist), + .rn_cp_iu6_t1_i1_gshare(rn_cp_iu6_t1_i1_gshare[0:9]), + .rn_cp_iu6_t1_i1_ls_ptr(rn_cp_iu6_t1_i1_ls_ptr), + .rn_cp_iu6_t1_i1_match(rn_cp_iu6_t1_i1_match), + .rn_cp_iu6_t1_i1_type_fp(rn_cp_iu6_t1_i1_type_fp), + .rn_cp_iu6_t1_i1_type_ap(rn_cp_iu6_t1_i1_type_ap), + .rn_cp_iu6_t1_i1_type_spv(rn_cp_iu6_t1_i1_type_spv), + .rn_cp_iu6_t1_i1_type_st(rn_cp_iu6_t1_i1_type_st), + .rn_cp_iu6_t1_i1_async_block(rn_cp_iu6_t1_i1_async_block), + .rn_cp_iu6_t1_i1_np1_flush(rn_cp_iu6_t1_i1_np1_flush), + .rn_cp_iu6_t1_i1_t1_v(rn_cp_iu6_t1_i1_t1_v), + .rn_cp_iu6_t1_i1_t1_t(rn_cp_iu6_t1_i1_t1_t), + .rn_cp_iu6_t1_i1_t1_p(rn_cp_iu6_t1_i1_t1_p), + .rn_cp_iu6_t1_i1_t1_a(rn_cp_iu6_t1_i1_t1_a), + .rn_cp_iu6_t1_i1_t2_v(rn_cp_iu6_t1_i1_t2_v), + .rn_cp_iu6_t1_i1_t2_t(rn_cp_iu6_t1_i1_t2_t), + .rn_cp_iu6_t1_i1_t2_p(rn_cp_iu6_t1_i1_t2_p), + .rn_cp_iu6_t1_i1_t2_a(rn_cp_iu6_t1_i1_t2_a), + .rn_cp_iu6_t1_i1_t3_v(rn_cp_iu6_t1_i1_t3_v), + .rn_cp_iu6_t1_i1_t3_t(rn_cp_iu6_t1_i1_t3_t), + .rn_cp_iu6_t1_i1_t3_p(rn_cp_iu6_t1_i1_t3_p), + .rn_cp_iu6_t1_i1_t3_a(rn_cp_iu6_t1_i1_t3_a), + .rn_cp_iu6_t1_i1_btb_entry(rn_cp_iu6_t1_i1_btb_entry), + .rn_cp_iu6_t1_i1_btb_hist(rn_cp_iu6_t1_i1_btb_hist), + .rn_cp_iu6_t1_i1_bta_val(rn_cp_iu6_t1_i1_bta_val), +`endif + .cp_rn_empty(cp_rn_empty), + .cp_async_block(cp_async_block), + .cp_rn_t0_i0_v(cp_rn_t0_i0_v), + .cp_rn_t0_i0_axu_exception_val(cp_rn_t0_i0_axu_exception_val), + .cp_rn_t0_i0_axu_exception(cp_rn_t0_i0_axu_exception), + .cp_rn_t0_i0_t1_v(cp_rn_t0_i0_t1_v), + .cp_rn_t0_i0_t1_t(cp_rn_t0_i0_t1_t), + .cp_rn_t0_i0_t1_p(cp_rn_t0_i0_t1_p), + .cp_rn_t0_i0_t1_a(cp_rn_t0_i0_t1_a), + .cp_rn_t0_i0_t2_v(cp_rn_t0_i0_t2_v), + .cp_rn_t0_i0_t2_t(cp_rn_t0_i0_t2_t), + .cp_rn_t0_i0_t2_p(cp_rn_t0_i0_t2_p), + .cp_rn_t0_i0_t2_a(cp_rn_t0_i0_t2_a), + .cp_rn_t0_i0_t3_v(cp_rn_t0_i0_t3_v), + .cp_rn_t0_i0_t3_t(cp_rn_t0_i0_t3_t), + .cp_rn_t0_i0_t3_p(cp_rn_t0_i0_t3_p), + .cp_rn_t0_i0_t3_a(cp_rn_t0_i0_t3_a), + .cp_rn_t0_i1_v(cp_rn_t0_i1_v), + .cp_rn_t0_i1_axu_exception_val(cp_rn_t0_i1_axu_exception_val), + .cp_rn_t0_i1_axu_exception(cp_rn_t0_i1_axu_exception), + .cp_rn_t0_i1_t1_v(cp_rn_t0_i1_t1_v), + .cp_rn_t0_i1_t1_t(cp_rn_t0_i1_t1_t), + .cp_rn_t0_i1_t1_p(cp_rn_t0_i1_t1_p), + .cp_rn_t0_i1_t1_a(cp_rn_t0_i1_t1_a), + .cp_rn_t0_i1_t2_v(cp_rn_t0_i1_t2_v), + .cp_rn_t0_i1_t2_t(cp_rn_t0_i1_t2_t), + .cp_rn_t0_i1_t2_p(cp_rn_t0_i1_t2_p), + .cp_rn_t0_i1_t2_a(cp_rn_t0_i1_t2_a), + .cp_rn_t0_i1_t3_v(cp_rn_t0_i1_t3_v), + .cp_rn_t0_i1_t3_t(cp_rn_t0_i1_t3_t), + .cp_rn_t0_i1_t3_p(cp_rn_t0_i1_t3_p), + .cp_rn_t0_i1_t3_a(cp_rn_t0_i1_t3_a), +`ifndef THREADS1 + .cp_rn_t1_i0_v(cp_rn_t1_i0_v), + .cp_rn_t1_i0_axu_exception_val(cp_rn_t1_i0_axu_exception_val), + .cp_rn_t1_i0_axu_exception(cp_rn_t1_i0_axu_exception), + .cp_rn_t1_i0_t1_v(cp_rn_t1_i0_t1_v), + .cp_rn_t1_i0_t1_t(cp_rn_t1_i0_t1_t), + .cp_rn_t1_i0_t1_p(cp_rn_t1_i0_t1_p), + .cp_rn_t1_i0_t1_a(cp_rn_t1_i0_t1_a), + .cp_rn_t1_i0_t2_v(cp_rn_t1_i0_t2_v), + .cp_rn_t1_i0_t2_t(cp_rn_t1_i0_t2_t), + .cp_rn_t1_i0_t2_p(cp_rn_t1_i0_t2_p), + .cp_rn_t1_i0_t2_a(cp_rn_t1_i0_t2_a), + .cp_rn_t1_i0_t3_v(cp_rn_t1_i0_t3_v), + .cp_rn_t1_i0_t3_t(cp_rn_t1_i0_t3_t), + .cp_rn_t1_i0_t3_p(cp_rn_t1_i0_t3_p), + .cp_rn_t1_i0_t3_a(cp_rn_t1_i0_t3_a), + .cp_rn_t1_i1_v(cp_rn_t1_i1_v), + .cp_rn_t1_i1_axu_exception_val(cp_rn_t1_i1_axu_exception_val), + .cp_rn_t1_i1_axu_exception(cp_rn_t1_i1_axu_exception), + .cp_rn_t1_i1_t1_v(cp_rn_t1_i1_t1_v), + .cp_rn_t1_i1_t1_t(cp_rn_t1_i1_t1_t), + .cp_rn_t1_i1_t1_p(cp_rn_t1_i1_t1_p), + .cp_rn_t1_i1_t1_a(cp_rn_t1_i1_t1_a), + .cp_rn_t1_i1_t2_v(cp_rn_t1_i1_t2_v), + .cp_rn_t1_i1_t2_t(cp_rn_t1_i1_t2_t), + .cp_rn_t1_i1_t2_p(cp_rn_t1_i1_t2_p), + .cp_rn_t1_i1_t2_a(cp_rn_t1_i1_t2_a), + .cp_rn_t1_i1_t3_v(cp_rn_t1_i1_t3_v), + .cp_rn_t1_i1_t3_t(cp_rn_t1_i1_t3_t), + .cp_rn_t1_i1_t3_p(cp_rn_t1_i1_t3_p), + .cp_rn_t1_i1_t3_a(cp_rn_t1_i1_t3_a), +`endif + .cp_bp_t0_val(cp_bp_val[0]), + .cp_bp_t0_ifar(cp_bp_t0_ifar), + .cp_bp_t0_bh0_hist(cp_bp_t0_bh0_hist), + .cp_bp_t0_bh1_hist(cp_bp_t0_bh1_hist), + .cp_bp_t0_bh2_hist(cp_bp_t0_bh2_hist), + .cp_bp_t0_br_pred(cp_bp_br_pred[0]), + .cp_bp_t0_br_taken(cp_bp_br_taken[0]), + .cp_bp_t0_bh_update(cp_bp_bh_update[0]), + .cp_bp_t0_bcctr(cp_bp_bcctr[0]), + .cp_bp_t0_bclr(cp_bp_bclr[0]), + .cp_bp_t0_getnia(cp_bp_getNIA[0]), + .cp_bp_t0_group(cp_bp_group[0]), + .cp_bp_t0_lk(cp_bp_lk[0]), + .cp_bp_t0_bh(cp_bp_t0_bh), + .cp_bp_t0_gshare(cp_bp_t0_gshare), + .cp_bp_t0_ls_ptr(cp_bp_t0_ls_ptr), + .cp_bp_t0_ctr(cp_bp_t0_ctr), + .cp_bp_t0_btb_entry(cp_bp_btb_entry[0]), + .cp_bp_t0_btb_hist(cp_bp_t0_btb_hist), +`ifndef THREADS1 + .cp_bp_t1_val(cp_bp_val[1]), + .cp_bp_t1_ifar(cp_bp_t1_ifar), + .cp_bp_t1_bh0_hist(cp_bp_t1_bh0_hist), + .cp_bp_t1_bh1_hist(cp_bp_t1_bh1_hist), + .cp_bp_t1_bh2_hist(cp_bp_t1_bh2_hist), + .cp_bp_t1_br_pred(cp_bp_br_pred[1]), + .cp_bp_t1_br_taken(cp_bp_br_taken[1]), + .cp_bp_t1_bh_update(cp_bp_bh_update[1]), + .cp_bp_t1_bcctr(cp_bp_bcctr[1]), + .cp_bp_t1_bclr(cp_bp_bclr[1]), + .cp_bp_t1_getnia(cp_bp_getNIA[1]), + .cp_bp_t1_group(cp_bp_group[1]), + .cp_bp_t1_lk(cp_bp_lk[1]), + .cp_bp_t1_bh(cp_bp_t1_bh), + .cp_bp_t1_gshare(cp_bp_t1_gshare), + .cp_bp_t1_ls_ptr(cp_bp_t1_ls_ptr), + .cp_bp_t1_ctr(cp_bp_t1_ctr), + .cp_bp_t1_btb_entry(cp_bp_btb_entry[1]), + .cp_bp_t1_btb_hist(cp_bp_t1_btb_hist), +`endif + .cp_dis_ivax(cp_dis_ivax), + .lq0_iu_execute_vld(lq0_iu_execute_vld), + .lq0_iu_itag(lq0_iu_itag), + .lq0_iu_n_flush(lq0_iu_n_flush), + .lq0_iu_np1_flush(lq0_iu_np1_flush), + .lq0_iu_dacr_type(lq0_iu_dacr_type), + .lq0_iu_dacrw(lq0_iu_dacrw), + .lq0_iu_instr(lq0_iu_instr), + .lq0_iu_eff_addr(lq0_iu_eff_addr), + .lq0_iu_exception_val(lq0_iu_exception_val), + .lq0_iu_exception(lq0_iu_exception), + .lq0_iu_flush2ucode(lq0_iu_flush2ucode), + .lq0_iu_flush2ucode_type(lq0_iu_flush2ucode_type), + .lq0_iu_recirc_val(lq0_iu_recirc_val), + .lq0_iu_dear_val(lq0_iu_dear_val), + .lq1_iu_execute_vld(lq1_iu_execute_vld), + .lq1_iu_itag(lq1_iu_itag), + .lq1_iu_n_flush(lq1_iu_n_flush), + .lq1_iu_np1_flush(lq1_iu_np1_flush), + .lq1_iu_exception_val(lq1_iu_exception_val), + .lq1_iu_exception(lq1_iu_exception), + .lq1_iu_dacr_type(lq1_iu_dacr_type), + .lq1_iu_dacrw(lq1_iu_dacrw), + .lq1_iu_perf_events(lq1_iu_perf_events), + .iu_lq_i0_completed(iu_lq_i0_completed), + .iu_lq_i1_completed(iu_lq_i1_completed), + .iu_lq_t0_i0_completed_itag(iu_lq_t0_i0_completed_itag_int), + .iu_lq_t0_i1_completed_itag(iu_lq_t0_i1_completed_itag_int), +`ifndef THREADS1 + .iu_lq_t1_i0_completed_itag(iu_lq_t1_i0_completed_itag_int), + .iu_lq_t1_i1_completed_itag(iu_lq_t1_i1_completed_itag_int), +`endif + .iu_lq_recirc_val(iu_lq_recirc_val), + .br_iu_execute_vld(br_iu_execute_vld), + .br_iu_itag(br_iu_itag), + .br_iu_bta(br_iu_bta), + .br_iu_redirect(br_iu_redirect), + .br_iu_taken(br_iu_taken), + .br_iu_perf_events(br_iu_perf_events), + .xu_iu_execute_vld(xu_iu_execute_vld), + .xu_iu_itag(xu_iu_itag), + .xu_iu_exception_val(xu_iu_exception_val), + .xu_iu_exception(xu_iu_exception), + .xu_iu_mtiar(xu_iu_mtiar), + .xu_iu_bta(xu_iu_bta), + .xu_iu_perf_events(xu_iu_perf_events), + .xu_iu_n_flush(xu_iu_n_flush), + .xu_iu_np1_flush(xu_iu_np1_flush), + .xu_iu_flush2ucode(xu_iu_flush2ucode), + .xu1_iu_execute_vld(xu1_iu_execute_vld), + .xu1_iu_itag(xu1_iu_itag), + .axu0_iu_execute_vld(axu0_iu_execute_vld), + .axu0_iu_itag(axu0_iu_itag), + .axu0_iu_n_flush(axu0_iu_n_flush), + .axu0_iu_np1_flush(axu0_iu_np1_flush), + .axu0_iu_n_np1_flush(axu0_iu_n_np1_flush), + .axu0_iu_exception(axu0_iu_exception), + .axu0_iu_exception_val(axu0_iu_exception_val), + .axu0_iu_flush2ucode(axu0_iu_flush2ucode), + .axu0_iu_flush2ucode_type(axu0_iu_flush2ucode_type), + .axu0_iu_async_fex(axu0_iu_async_fex), + .axu0_iu_perf_events(axu0_iu_perf_events), + .axu1_iu_execute_vld(axu1_iu_execute_vld), + .axu1_iu_itag(axu1_iu_itag), + .axu1_iu_n_flush(axu1_iu_n_flush), + .axu1_iu_np1_flush(axu1_iu_np1_flush), + .axu1_iu_exception(axu1_iu_exception), + .axu1_iu_exception_val(axu1_iu_exception_val), + .axu1_iu_flush2ucode(axu1_iu_flush2ucode), + .axu1_iu_flush2ucode_type(axu1_iu_flush2ucode_type), + .axu1_iu_perf_events(axu1_iu_perf_events), + .an_ac_uncond_dbg_event(an_ac_uncond_dbg_event), + .xu_iu_external_mchk(xu_iu_external_mchk), + .xu_iu_ext_interrupt(xu_iu_ext_interrupt), + .xu_iu_dec_interrupt(xu_iu_dec_interrupt), + .xu_iu_udec_interrupt(xu_iu_udec_interrupt), + .xu_iu_perf_interrupt(xu_iu_perf_interrupt), + .xu_iu_fit_interrupt(xu_iu_fit_interrupt), + .xu_iu_crit_interrupt(xu_iu_crit_interrupt), + .xu_iu_wdog_interrupt(xu_iu_wdog_interrupt), + .xu_iu_gwdog_interrupt(xu_iu_gwdog_interrupt), + .xu_iu_gfit_interrupt(xu_iu_gfit_interrupt), + .xu_iu_gdec_interrupt(xu_iu_gdec_interrupt), + .xu_iu_dbell_interrupt(xu_iu_dbell_interrupt), + .xu_iu_cdbell_interrupt(xu_iu_cdbell_interrupt), + .xu_iu_gdbell_interrupt(xu_iu_gdbell_interrupt), + .xu_iu_gcdbell_interrupt(xu_iu_gcdbell_interrupt), + .xu_iu_gmcdbell_interrupt(xu_iu_gmcdbell_interrupt), + .xu_iu_dbsr_ide(xu_iu_dbsr_ide), + .xu_iu_t0_rest_ifar(xu_iu_t0_rest_ifar), +`ifndef THREADS1 + .xu_iu_t1_rest_ifar(xu_iu_t1_rest_ifar), +`endif + .cp_is_isync(cp_ic_is_isync), + .cp_is_csync(cp_ic_is_csync), + .iu_flush(iu_flush), + .cp_flush_into_uc(cp_flush_into_uc), + .cp_uc_t0_flush_ifar(cp_uc_t0_flush_ifar), +`ifndef THREADS1 + .cp_uc_t1_flush_ifar(cp_uc_t1_flush_ifar), +`endif + .cp_uc_np1_flush(cp_uc_np1_flush), + .cp_flush(cp_flush_internal), + .cp_t0_next_itag(cp_t0_next_itag), + .cp_t0_flush_itag(cp_t0_flush_itag), + .cp_t0_flush_ifar(cp_t0_flush_ifar_internal), +`ifndef THREADS1 + .cp_t1_next_itag(cp_t1_next_itag), + .cp_t1_flush_itag(cp_t1_flush_itag), + .cp_t1_flush_ifar(cp_t1_flush_ifar_internal), +`endif + .cp_iu0_flush_2ucode(cp_iu0_flush_2ucode), + .cp_iu0_flush_2ucode_type(cp_iu0_flush_2ucode_type), + .cp_iu0_flush_nonspec(cp_iu0_flush_nonspec), + .pc_iu_init_reset(pc_iu_init_reset), + .cp_rn_uc_credit_free(cp_rn_uc_credit_free), + .iu_xu_rfi(iu_xu_rfi), + .iu_xu_rfgi(iu_xu_rfgi), + .iu_xu_rfci(iu_xu_rfci), + .iu_xu_rfmci(iu_xu_rfmci), + .iu_xu_int(iu_xu_int), + .iu_xu_gint(iu_xu_gint), + .iu_xu_cint(iu_xu_cint), + .iu_xu_mcint(iu_xu_mcint), + .iu_xu_dear_update(iu_xu_dear_update), + .iu_spr_eheir_update(iu_spr_eheir_update), + .iu_xu_t0_nia(iu_xu_t0_nia), + .iu_xu_t0_esr(iu_xu_t0_esr), + .iu_xu_t0_mcsr(iu_xu_t0_mcsr), + .iu_xu_t0_dbsr(iu_xu_t0_dbsr), + .iu_xu_t0_dear(iu_xu_t0_dear), + .iu_spr_t0_eheir(iu_spr_t0_eheir), + .xu_iu_t0_dbcr0_dac1(xu_iu_t0_dbcr0_dac1), + .xu_iu_t0_dbcr0_dac2(xu_iu_t0_dbcr0_dac2), + .xu_iu_t0_dbcr0_dac3(xu_iu_t0_dbcr0_dac3), + .xu_iu_t0_dbcr0_dac4(xu_iu_t0_dbcr0_dac4), +`ifndef THREADS1 + .iu_xu_t1_nia(iu_xu_t1_nia), + .iu_xu_t1_esr(iu_xu_t1_esr), + .iu_xu_t1_mcsr(iu_xu_t1_mcsr), + .iu_xu_t1_dbsr(iu_xu_t1_dbsr), + .iu_xu_t1_dear(iu_xu_t1_dear), + .iu_spr_t1_eheir(iu_spr_t1_eheir), + .xu_iu_t1_dbcr0_dac1(xu_iu_t1_dbcr0_dac1), + .xu_iu_t1_dbcr0_dac2(xu_iu_t1_dbcr0_dac2), + .xu_iu_t1_dbcr0_dac3(xu_iu_t1_dbcr0_dac3), + .xu_iu_t1_dbcr0_dac4(xu_iu_t1_dbcr0_dac4), +`endif + .iu_xu_dbsr_update(iu_xu_dbsr_update), + .iu_xu_dbsr_ude(iu_xu_dbsr_ude), + .iu_xu_dbsr_ide(iu_xu_dbsr_ide), + .iu_xu_esr_update(iu_xu_esr_update), + .iu_xu_act(iu_xu_act), + .iu_xu_dbell_taken(iu_xu_dbell_taken), + .iu_xu_cdbell_taken(iu_xu_cdbell_taken), + .iu_xu_gdbell_taken(iu_xu_gdbell_taken), + .iu_xu_gcdbell_taken(iu_xu_gcdbell_taken), + .iu_xu_gmcdbell_taken(iu_xu_gmcdbell_taken), + .iu_xu_instr_cpl(iu_xu_instr_cpl), + .xu_iu_np1_async_flush(xu_iu_np1_async_flush), + .iu_xu_async_complete(iu_xu_async_complete), + .dp_cp_hold_req(dp_cp_hold_req), + .iu_mm_hold_ack(iu_mm_hold_ack), + .dp_cp_bus_snoop_hold_req(dp_cp_bus_snoop_hold_req), + .iu_mm_bus_snoop_hold_ack(iu_mm_bus_snoop_hold_ack_int), + .xu_iu_msr_de(xu_iu_msr_de), + .xu_iu_msr_pr(xu_iu_msr_pr), + .xu_iu_msr_cm(xu_iu_msr_cm), + .xu_iu_msr_gs(xu_iu_msr_gs), + .xu_iu_msr_me(xu_iu_msr_me), + .xu_iu_dbcr0_edm(xu_iu_dbcr0_edm), + .xu_iu_dbcr0_idm(xu_iu_dbcr0_idm), + .xu_iu_dbcr0_icmp(xu_iu_dbcr0_icmp), + .xu_iu_dbcr0_brt(xu_iu_dbcr0_brt), + .xu_iu_dbcr0_irpt(xu_iu_dbcr0_irpt), + .xu_iu_dbcr0_trap(xu_iu_dbcr0_trap), + .xu_iu_iac1_en(xu_iu_iac1_en), + .xu_iu_iac2_en(xu_iu_iac2_en), + .xu_iu_iac3_en(xu_iu_iac3_en), + .xu_iu_iac4_en(xu_iu_iac4_en), + .xu_iu_dbcr0_ret(xu_iu_dbcr0_ret), + .xu_iu_dbcr1_iac12m(xu_iu_dbcr1_iac12m), + .xu_iu_dbcr1_iac34m(xu_iu_dbcr1_iac34m), + .lq_iu_spr_dbcr3_ivc(lq_iu_spr_dbcr3_ivc), + .xu_iu_epcr_extgs(xu_iu_epcr_extgs), + .xu_iu_epcr_dtlbgs(xu_iu_epcr_dtlbgs), + .xu_iu_epcr_itlbgs(xu_iu_epcr_itlbgs), + .xu_iu_epcr_dsigs(xu_iu_epcr_dsigs), + .xu_iu_epcr_isigs(xu_iu_epcr_isigs), + .xu_iu_epcr_duvd(xu_iu_epcr_duvd), + .xu_iu_epcr_icm(xu_iu_epcr_icm), + .xu_iu_epcr_gicm(xu_iu_epcr_gicm), + .xu_iu_spr_ccr2_en_dcr(xu_iu_spr_ccr2_en_dcr), + .xu_iu_spr_ccr2_ucode_dis(xu_iu_spr_ccr2_ucode_dis), + .xu_iu_hid_mmu_mode(xu_iu_hid_mmu_mode), + .xu_iu_xucr4_mmu_mchk(xu_iu_xucr4_mmu_mchk), + .iu_xu_quiesce(iu_xu_quiesce), + .iu_pc_quiesce(iu_pc_quiesce), + .mm_iu_ierat_rel_val(mm_iu_ierat_rel_val[0:`THREADS - 1]), + .mm_iu_ierat_pt_fault(mm_iu_ierat_pt_fault), + .mm_iu_ierat_lrat_miss(mm_iu_ierat_lrat_miss), + .mm_iu_ierat_tlb_inelig(mm_iu_ierat_tlb_inelig), + .mm_iu_tlb_multihit_err(mm_iu_tlb_multihit_err), + .mm_iu_tlb_par_err(mm_iu_tlb_par_err), + .mm_iu_lru_par_err(mm_iu_lru_par_err), + .mm_iu_tlb_miss(mm_iu_tlb_miss), + .mm_iu_reload_hit(mm_iu_reload_hit), + .mm_iu_ierat_mmucr1(mm_iu_ierat_mmucr1[3:4]), + .ic_cp_nonspec_hit(ic_cp_nonspec_hit), + .cp_mm_except_taken_t0(cp_mm_except_taken_t0), + `ifndef THREADS1 + .cp_mm_except_taken_t1(cp_mm_except_taken_t1), + `endif + .xu_iu_single_instr_mode(xu_iu_single_instr_mode), + .spr_single_issue(spr_single_issue), + .spr_ivpr(spr_ivpr), + .spr_givpr(spr_givpr), + .spr_iac1(spr_iac1), + .spr_iac2(spr_iac2), + .spr_iac3(spr_iac3), + .spr_iac4(spr_iac4), + .iu_rf_t0_xer_p(iu_rf_t0_xer_p), +`ifndef THREADS1 + .iu_rf_t1_xer_p(iu_rf_t1_xer_p), +`endif + .pc_iu_ram_active(pc_iu_ram_active), + .pc_iu_ram_flush_thread(pc_iu_ram_flush_thread), + .xu_iu_msrovride_enab(xu_iu_msrovride_enab), + .iu_pc_ram_done(iu_pc_ram_done_int), + .iu_pc_ram_interrupt(iu_pc_ram_interrupt), + .iu_pc_ram_unsupported(iu_pc_ram_unsupported), + .pc_iu_stop(pc_iu_stop), + .pc_iu_step(pc_iu_step), + .pc_iu_t0_dbg_action(pc_iu_t0_dbg_action), +`ifndef THREADS1 + .pc_iu_t1_dbg_action(pc_iu_t1_dbg_action), +`endif + .iu_pc_step_done(iu_pc_step_done), + .iu_pc_stop_dbg_event(iu_pc_stop_dbg_event), + .iu_pc_err_debug_event(iu_pc_err_debug_event), + .iu_pc_attention_instr(iu_pc_attention_instr), + .iu_pc_err_mchk_disabled(iu_pc_err_mchk_disabled), + .ac_an_debug_trigger(ac_an_debug_trigger), + .iu_xu_stop(iu_xu_stop_internal), + .pc_iu_trace_bus_enable(pc_iu_trace_bus_enable), + .pc_iu_debug_mux_ctrls(pc_iu_debug_mux2_ctrls), + .debug_bus_in(ifetch_debug_bus_out), + .debug_bus_out(debug_bus_out), + .coretrace_ctrls_in(ifetch_coretrace_ctrls_out), + .coretrace_ctrls_out(coretrace_ctrls_out) + + ); + + assign iu_pc_ram_done = iu_pc_ram_done_int; + + // Need to fix these + + assign g8t_clkoff_b = 1'b1; + assign g8t_d_mode = 1'b0; + assign g8t_delay_lclkr = {5{1'b0}}; + assign g8t_mpw1_b = {5{1'b1}}; + assign g8t_mpw2_b = 1'b1; + assign g6t_clkoff_b = 1'b1; + assign g6t_act_dis = 1'b0; + assign g6t_d_mode = 1'b0; + assign g6t_delay_lclkr = {4{1'b0}}; + assign g6t_mpw1_b = {5{1'b1}}; + assign g6t_mpw2_b = 1'b1; + assign cam_clkoff_b = 1'b1; + assign cam_act_dis = 1'b0; + assign cam_d_mode = 1'b0; + assign cam_delay_lclkr = {5{1'b0}}; + assign cam_mpw1_b = {5{1'b1}}; + assign cam_mpw2_b = 1'b1; + + assign btb_scan_in = 1'b0; + assign func_scan_in = 1'b0; + assign ac_ccfg_scan_in = 1'b0; + assign time_scan_in = 1'b0; + assign repr_scan_in = 1'b0; + assign abst_scan_in = 3'b000; + assign regf_scan_in = {5{1'b0}}; + assign bp_scan_in = {2*`THREADS{1'b0}}; + assign ram_scan_in = 1'b0; + assign uc_scan_in = {`THREADS{1'b0}}; + assign dbg1_scan_in = 1'b0; + assign bh0_scan_in = 1'b0; + assign bh1_scan_in = 1'b0; + assign bh2_scan_in = 1'b0; + assign slice_scan_in = {(`THREADS*7+1){1'b0}}; + assign cp_scan_in = {(`THREADS+1){1'b0}}; + + assign iu_pc_bo_fail[4] = 1'b0; + assign iu_pc_bo_diagout[4] = 1'b0; + + // This needs to get moved into an RLM + tri_plat #(.WIDTH(15)) perv_3to2_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + .din({pc_iu_func_slp_sl_thold_3, + pc_iu_func_nsl_thold_3, + pc_iu_func_slp_nsl_thold_3, + pc_iu_func_sl_thold_3, + pc_iu_cfg_slp_sl_thold_3, + pc_iu_regf_slp_sl_thold_3, + pc_iu_time_sl_thold_3, + pc_iu_abst_sl_thold_3, + pc_iu_abst_slp_sl_thold_3, + pc_iu_repr_sl_thold_3, + pc_iu_ary_nsl_thold_3, + pc_iu_ary_slp_nsl_thold_3, + pc_iu_bolt_sl_thold_3, + pc_iu_sg_3, + pc_iu_fce_3}), + .q( {pc_iu_func_slp_sl_thold_2, + pc_iu_func_nsl_thold_2, + pc_iu_func_slp_nsl_thold_2, + pc_iu_func_sl_thold_2, + pc_iu_cfg_slp_sl_thold_2, + pc_iu_regf_slp_sl_thold_2, + pc_iu_time_sl_thold_2, + pc_iu_abst_sl_thold_2, + pc_iu_abst_slp_sl_thold_2, + pc_iu_repr_sl_thold_2, + pc_iu_ary_nsl_thold_2, + pc_iu_ary_slp_nsl_thold_2, + pc_iu_bolt_sl_thold_2, + pc_iu_sg_2, + pc_iu_fce_2}) + ); + + +endmodule diff --git a/dev/verilog/work/iuq_axu_fu_dec.v b/dev/verilog/work/iuq_axu_fu_dec.v new file mode 100755 index 0000000..dd24614 --- /dev/null +++ b/dev/verilog/work/iuq_axu_fu_dec.v @@ -0,0 +1,1403 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//------------------------------------------------------------------- + +//------------------------------------------------------------------- + +`include "tri_a2o.vh" + +module iuq_axu_fu_dec( + input [0:`NCLK_WIDTH-1] nclk, + //------------------------------------------------------------------- + inout vdd, + inout gnd, + //------------------------------------------------------------------- + + input i_dec_si, + output i_dec_so, + + input pc_iu_sg_2, + input pc_iu_func_sl_thold_2, + input clkoff_b, + input act_dis, + input tc_ac_ccflush_dc, + input d_mode, + input delay_lclkr, + input mpw1_b, + input mpw2_b, + + input iu_au_iu4_isram, + + // AXU interface signals--------------------------------------------- + input iu_au_iu4_instr_v, + input [0:31] iu_au_iu4_instr, + input [0:3] iu_au_iu4_ucode_ext, // TABC + input [0:2] iu_au_iu4_ucode, + input iu_au_iu4_2ucode, + input iu_au_ucode_restart, + + input [0:7] iu_au_config_iucr, // 0: graphics mode, 1: disable axu bypass + + // out to AXU + output au_iu_iu4_i_dec_b, // decoded a valid FU instruction (inverted) 0509 + output [0:2] au_iu_iu4_ucode, + + output au_iu_iu4_t1_v, + output [0:2] au_iu_iu4_t1_t, + output [0:`GPR_POOL_ENC-1] au_iu_iu4_t1_a, + + output au_iu_iu4_t2_v, + output [0:`GPR_POOL_ENC-1] au_iu_iu4_t2_a, + output [0:2] au_iu_iu4_t2_t, + + output au_iu_iu4_t3_v, + output [0:`GPR_POOL_ENC-1] au_iu_iu4_t3_a, + output [0:2] au_iu_iu4_t3_t, + + output au_iu_iu4_s1_v, + output [0:`GPR_POOL_ENC-1] au_iu_iu4_s1_a, + output [0:2] au_iu_iu4_s1_t, + + output au_iu_iu4_s2_v, + output [0:`GPR_POOL_ENC-1] au_iu_iu4_s2_a, + output [0:2] au_iu_iu4_s2_t, + + output au_iu_iu4_s3_v, + output [0:`GPR_POOL_ENC-1] au_iu_iu4_s3_a, + output [0:2] au_iu_iu4_s3_t, + + output [0:2] au_iu_iu4_ilat, + output au_iu_iu4_ord, + output au_iu_iu4_cord, + output au_iu_iu4_spec, + output au_iu_iu4_type_fp, + output au_iu_iu4_type_ap, + output au_iu_iu4_type_spv, + output au_iu_iu4_type_st, + output au_iu_iu4_async_block, + + output au_iu_iu4_isload, + output au_iu_iu4_isstore, + + output au_iu_iu4_rte_lq, + output au_iu_iu4_rte_sq, + output au_iu_iu4_rte_axu0, + output au_iu_iu4_rte_axu1, + + output au_iu_iu4_no_ram, + + //------------------------------------------------------------------- + + output [0:31] fu_dec_debug + ); + + //------------------------------------------------------------------------------------------------------------------------------------------------------ + + wire tidn; + wire tiup; + + wire [0:5] is0_ldst_ra; + + wire [0:7] iu_au_config_iucr_int; + wire [0:7] iu_au_config_iucr_l2; + wire [0:7] iu_au_config_iucr_din; + wire [00:31] is0_instr; + wire [0:5] pri_is0; // primary opcode + wire [20:31] sec_is0; // secondary opcode + wire av; // source/target valids + wire bv; + wire cv; + wire tv; + wire isfu_dec_is0; + wire ld_st_is0; + wire isLoad; + wire isStore; + + wire st_is0; + wire indexed; + wire fdiv_is0; + wire fsqrt_is0; + wire update_form; + wire forcealign; + wire cr_writer; + wire is0_instr_v; + wire ucode_restart; + wire mffgpr; + wire mftgpr; + wire record_form; + wire fpscr_wr; + wire fpscr_mv; + wire [0:8] ldst_tag; + wire [0:4] ldst_tag_addr; + wire is0_to_ucode; + wire cordered; + wire ordered; + wire is0_zero_r0; + + wire [0:7] config_reg_scin; + wire [0:7] config_reg_scout; + + wire [0:5] size; + wire [3:7] spare_unused; + + wire is0_is_ucode; + wire in_ucode_mode; + wire only_from_ucode; + wire only_graphics_mode; + wire graphics_mode; + wire is0_invalid_kill; + wire is0_invalid_kill_uc; + + wire ldst_extpid; + wire single_precision_ldst; + wire int_word_ldst; + wire sign_ext_ldst; + wire io_port; + wire io_port_ext; + + wire ignore_flush_is0; + + wire is0_kill_or_divsqrt_b; + wire au_iu_is0_i_dec; + wire is0_i_dec_b; + wire no_ram; + + wire ram_mode_v; + + wire [0:5] au_iu_iu4_t1_a6; + wire [0:5] au_iu_iu4_t2_a6; + wire [0:5] au_iu_iu4_t3_a6; + wire [0:5] au_iu_iu4_s1_a6; + wire [0:5] au_iu_iu4_s2_a6; + wire [0:5] au_iu_iu4_s3_a6; + + // Pervasive + wire pc_iu_func_sl_thold_1; + wire pc_iu_func_sl_thold_0; + wire pc_iu_func_sl_thold_0_b; + wire pc_iu_sg_1; + wire pc_iu_sg_0; + wire force_t; + //-------------------------------------------------------------- + + //----------------------------------------------- + // pervasive + //----------------------------------------------- + + + tri_plat #(.WIDTH(2)) perv_2to1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + .din({pc_iu_func_sl_thold_2,pc_iu_sg_2}), + .q({pc_iu_func_sl_thold_1,pc_iu_sg_1}) + ); + + + tri_plat #(.WIDTH(2)) perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + .din({pc_iu_func_sl_thold_1,pc_iu_sg_1}), + .q({pc_iu_func_sl_thold_0,pc_iu_sg_0}) + ); + + + tri_lcbor perv_lcbor( + .clkoff_b(clkoff_b), + .thold(pc_iu_func_sl_thold_0), + .sg(pc_iu_sg_0), + .act_dis(act_dis), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b) + ); + + assign tidn = 1'b0; + assign tiup = 1'b1; + + assign is0_instr = iu_au_iu4_instr; + assign is0_instr_v = iu_au_iu4_instr_v; + assign ucode_restart = iu_au_ucode_restart; + + assign pri_is0[0:5] = is0_instr[0:5]; + assign sec_is0[20:31] = is0_instr[20:31]; + + // update # of inputs and outputs .i xx .o xx + // run "espvhdlexpand iuq_axu_fu_dec.vhdl > iuq_axu_fu_dec_new.vhdl" to regenerate logic below table + // + + //@@ ESPRESSO TABLE START @@ + // ################################################################################################## + // .i 18 + // .o 35 + // .ilb pri_is0[0] pri_is0[1] pri_is0[2] pri_is0[3] pri_is0[4] pri_is0[5] + // sec_is0[20] sec_is0[21] sec_is0[22] sec_is0[23] sec_is0[24] sec_is0[25] sec_is0[26] sec_is0[27] sec_is0[28] sec_is0[29] sec_is0[30] sec_is0[31] + // .ob isfu_dec_is0 tv av bv cv + // record_form fpscr_wr cordered ordered fpscr_mv + // ld_st_is0 st_is0 indexed update_form forcealign single_precision_ldst int_word_ldst sign_ext_ldst ldst_extpid io_port io_port_ext + // size[0] size[1] size[2] size[3] size[4] size[5] + // cr_writer mffgpr mftgpr fdiv_is0 + // fsqrt_is0 only_from_ucode no_ram only_graphics_mode + // .type fd + //# + //# + // ##################################################################################################################### + //# s + //# i + //# n + //# g o + //# l n + //# e l + //# | o y + //# p n | + //# r i s l g + //# e n i y r + //# u c t g l i | a + //# p f i | n d o f p + //# d o s w | s | c r h + //# f c f l a r i o e t p LD/ST r o i + //# p o o p d i t c o r x | io size m c + //# r s r r s n e e n d t e or in w mm | n s + //# e c d d c o s d a | | | x |t bytes r ff f u o | + //#pri_is0 sec_is0 i c r e e r r t e f l l l l t p| 1to16 i ft fs c | m + //# s o _ r r _ o x o i d d d p oe pwrs t gg dq o r o + //#000000 2 2222222223 3 F T A B C r w e e m s r e r g s s s i rx oftwo e pp ir d a d + //#012345 0 1234567890 1 U V V V V d r d d v t e d m n t t t d tt 012345 r rr vt e m e + // ##################################################################################################################### + + // 000000 - ---------- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 110011 - 00 00 0 0 0 # reserved + // 000001 - ---------- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 # open for vxu new instructions + // 000010 - ---------- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 000011 - ---------- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 000100 - 000------- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 000100 - 0010------ - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 000100 - 00110000-- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 000100 - 0011000100 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 000100 - 0011000101 1 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 000100 - 001100011- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 000100 - 0011001--- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 000100 - 001101---- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 000100 - 00111000-- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 000100 - 0011100100 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 000100 - 0011100101 1 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 000100 - 001110011- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 000100 - 0011101--- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 000100 - 001111---- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 000100 - 01-------- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 000100 - 1--------- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 000101 - ---------- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 000110 - ---------- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 000111 - ---------- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 001--- - ---------- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 010--- - ---------- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 01-0-- - ---------- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 01--0- - ---------- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 01---0 - ---------- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 0000000000 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 1 0000000011 0 0 1 0 0 0 0 0 0 0 - 1 0 1 0 0 0 1 0 0 11 000000 0 10 00 0 0 0 # mfdpx (DITC to FPR) + // 011111 1 0000000011 1 0 1 0 0 0 0 0 0 0 - 1 0 1 0 0 0 1 0 0 11 000000 1 10 00 0 0 0 # mfdpx. (DITC to FPR) + // 011111 1 0000100011 0 0 1 0 0 0 0 0 0 0 - 1 0 0 0 0 0 1 0 0 10 000000 0 10 00 0 0 0 # mfdp (DITC to FPR) + // 011111 1 0000100011 1 0 1 0 0 0 0 0 0 0 - 1 0 0 0 0 0 1 0 0 10 000000 1 10 00 0 0 0 # mfdp. (DITC to FPR) + // 011111 1 0001000011 0 0 0 1 0 0 0 0 0 0 - 1 1 1 0 0 0 1 0 0 11 000000 0 01 00 0 0 0 # mtdpx (DITC from FPR) + // 011111 1 0001000011 1 0 0 1 0 0 0 0 0 0 - 1 1 1 0 0 0 1 0 0 11 000000 1 01 00 0 0 0 # mtdpx. (DITC from FPR) + // 011111 1 0001100011 0 0 0 1 0 0 0 0 0 0 - 1 1 0 0 0 0 1 0 0 10 000000 0 01 00 0 0 0 # mtdp (DITC from FPR) + // 011111 1 0001100011 1 0 0 1 0 0 0 0 0 0 - 1 1 0 0 0 0 1 0 0 10 000000 1 01 00 0 0 0 # mtdp. (DITC from FPR) + // 011111 - 01-------- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 100000---- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 10000100-- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 100001010- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 1000010110 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 1000010111 - 1 1 0 0 0 0 0 0 0 - 1 0 1 0 0 1 0 0 0 00 000100 0 00 00 0 0 0 # lfsx + // 011111 - 1000011--- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 100010---- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 10001100-- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 100011010- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 1000110110 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 1000110111 - 1 1 0 0 0 0 0 0 0 - 1 0 1 1 0 1 0 0 0 00 000100 0 00 00 0 1 0 # lfsux + // 011111 - 1000111--- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 100100---- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 10010100-- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 100101010- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 1001010110 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 1001010111 - 1 1 0 0 0 0 0 0 0 - 1 0 1 0 0 0 0 0 0 00 001000 0 00 00 0 0 0 # lfdx + // 011111 - 10010110-- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 100101110- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 1001011110 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 1001011111 - 1 1 0 0 0 0 0 0 0 - 1 0 1 0 0 0 0 0 1 00 001000 0 00 00 0 0 0 # lfdepx + // 011111 - 100110---- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 10011100-- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 100111010- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 1001110110 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 1001110111 - 1 1 0 0 0 0 0 0 0 - 1 0 1 1 0 0 0 0 0 00 001000 0 00 00 0 1 0 # lfdux + // 011111 - 1001111100 - 1 1 0 0 0 0 0 0 0 - 1 0 0 0 0 0 1 1 0 00 000000 0 10 00 1 0 1 # mfifgpr (mffgpr for lfiwax) + // 011111 - 1001111101 - 1 1 0 0 0 0 0 0 0 - 1 0 0 0 0 0 1 0 0 00 000000 0 10 00 1 0 1 # mfixfgpr (mffgpr for lfiwzx) + // 011111 - 1001111110 - 1 1 0 0 0 0 0 0 0 - 1 0 0 0 0 1 0 0 0 00 000000 0 10 00 1 0 1 # mfsfgpr (mffgpr for lfs, lfsu single) + // 011111 - 1001111111 - 1 1 0 0 0 0 0 0 0 - 1 0 0 0 0 0 0 0 0 00 000000 0 10 00 1 0 1 # mffgpr (mffgpr for lfd, lfdu double) + // 011111 - 101000---- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 10100100-- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 101001010- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 1010010110 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 1010010111 - 1 0 1 0 0 0 0 0 0 - 1 1 1 0 0 1 0 0 0 00 000100 0 00 00 0 0 0 # stfsx + // 011111 - 1010011--- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 101010---- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 10101100-- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 101011010- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 1010110110 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 1010110111 - 1 0 1 0 0 0 0 0 0 - 1 1 1 1 0 1 0 0 0 00 000100 0 00 00 0 0 0 # stfsux + // 011111 - 1010111--- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 101100---- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 10110100-- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 101101010- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 1011010110 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 1011010111 - 1 0 1 0 0 0 0 0 0 - 1 1 1 0 0 0 0 0 0 00 001000 0 00 00 0 0 0 # stfdx + // 011111 - 10110110-- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 1011011100 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 1011011101 - 1 0 0 1 0 0 0 0 0 - 1 1 0 0 0 0 1 0 0 00 000000 0 01 00 1 0 1 # mfitgpr (mftgpr for stfiwx integer word) + // 011111 - 1011011110 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 1011011111 - 1 0 1 0 0 0 0 0 0 - 1 1 1 0 0 0 0 0 1 00 001000 0 00 00 0 0 0 # stfdepx + // 011111 - 101110---- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 10111100-- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 101111010- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 1011110110 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 1011110111 - 1 0 1 0 0 0 0 0 0 - 1 1 1 1 0 0 0 0 0 00 001000 0 00 00 0 0 0 # stfdux + // 011111 - 1011111110 - 1 0 0 1 0 0 0 0 0 - 1 1 0 0 0 1 0 0 0 00 000000 0 01 00 1 0 1 # mfstgpr (mftgpr single) + // 011111 - 1011111111 - 1 0 0 1 0 0 0 0 0 - 1 1 0 0 0 0 0 0 0 00 000000 0 01 00 1 0 1 # mftgpr (mftgpr double) + // 011111 - 110000---- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 11000100-- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 110001010- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 1100010110 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + //#011111 - 1100010111 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 # lfdpx (ucoded) + // 011111 - 1100011--- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 11001----- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 110100---- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 11010100-- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 110101010- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 1101010110 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 1101010111 - 1 1 0 0 0 0 0 0 0 - 1 0 1 0 0 0 1 1 0 00 000100 0 00 00 0 0 0 # lfiwax + // 011111 - 1101011--- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 1101110111 - 1 1 0 0 0 0 0 0 0 - 1 0 1 0 0 0 1 0 0 00 000100 0 00 00 0 0 0 # lfiwzx + // 011111 - 111000---- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 11100100-- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 111001010- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 1110010110 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + //#011111 - 1110010111 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 # stfdpx (ucoded) + // 011111 - 1110011--- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 11101----- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 111100---- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 11110100-- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 111101010- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 1111010110 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 1111010111 - 1 0 1 0 0 0 0 0 0 - 1 1 1 0 0 0 1 0 0 00 000100 0 00 00 0 0 0 # stfiwx + // 011111 - 1111011--- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 011111 - 11111----- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 10---- - ---------- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 110000 - ---------- - 1 1 0 0 0 0 0 0 0 - 1 0 0 0 0 1 0 0 0 00 000100 0 00 00 0 0 0 # lfs + // 110001 - ---------- - 1 1 0 0 0 0 0 0 0 - 1 0 0 1 0 1 0 0 0 00 000100 0 00 00 0 1 0 # lfsu + // 110010 - ---------- - 1 1 0 0 0 0 0 0 0 - 1 0 0 0 0 0 0 0 0 00 001000 0 00 00 0 0 0 # lfd + // 110011 - ---------- - 1 1 0 0 0 0 0 0 0 - 1 0 0 1 0 0 0 0 0 00 001000 0 00 00 0 1 0 # lfdu + // 110100 - ---------- - 1 0 1 0 0 0 0 0 0 - 1 1 0 0 0 1 0 0 0 00 000100 0 00 00 0 0 0 # stfs + // 110101 - ---------- - 1 0 1 0 0 0 0 0 0 - 1 1 0 1 0 1 0 0 0 00 000100 0 00 00 0 0 0 # stfsu + // 110110 - ---------- - 1 0 1 0 0 0 0 0 0 - 1 1 0 0 0 0 0 0 0 00 001000 0 00 00 0 0 0 # stfd + // 110111 - ---------- - 1 0 1 0 0 0 0 0 0 - 1 1 0 1 0 0 0 0 0 00 001000 0 00 00 0 0 0 # stfdu + // 111000 - ---------- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + //#111001 - ---------0 0 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 # lfdp (ucoded) + // 111001 - ---------0 1 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111001 - ---------1 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111010 - ---------- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111011 - 000--0---- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111011 - 0010-0---- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111011 - 00110000-- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111011 - 0011000100 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111011 - 0011000101 0 1 1 0 1 0 0 0 0 0 - 0 0 0 0 0 - - - 0 00 ------ 0 00 00 0 0 1 # fexptes + // 111011 - 001100011- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111011 - 00110010-- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111011 - 001100110- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111011 - 0011001110 0 0 1 0 1 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # fcfiwus (removed) + // 111011 - 0011001110 1 0 1 0 1 0 1 1 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # fcfiwus. (removed) + // 111011 - 0011001111 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111011 - 00111000-- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111011 - 0011100100 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111011 - 0011100101 0 1 1 0 1 0 0 0 0 0 - 0 0 0 0 0 - - - 0 00 ------ 0 00 00 0 0 1 # floges + // 111011 - 001110011- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111011 - 0011101--- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111011 - 01---0---- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111011 - 10---0---- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111011 - 1100-0---- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111011 - 1101000--- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111011 - 11010010-- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111011 - 110100110- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111011 - 1101001110 0 1 1 0 1 0 0 1 0 0 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # fcfids + // 111011 - 1101001110 1 1 1 0 1 0 1 1 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # fcfids. + // 111011 - 1101001111 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111011 - 110110---- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111011 - 1110-0---- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111011 - 1111000--- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111011 - 11110010-- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111011 - 111100110- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111011 - 1111001110 0 1 1 0 1 0 0 1 0 0 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # fcfidus + // 111011 - 1111001110 1 1 1 0 1 0 1 1 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # fcfidus. + // 111011 - 1111001111 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111011 - 111110---- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111011 - -----10000 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111011 - -----10001 0 0 1 1 0 1 0 1 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 1 0 0 # fmuls_uc + // 111011 - -----10001 1 0 1 1 0 1 1 1 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 1 0 0 # fmuls_uc. + // 111011 - -----10010 0 1 1 1 1 0 0 1 0 1 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 10 0 0 0 # fdivs + // 111011 - -----10010 1 1 1 1 1 0 1 1 1 1 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 10 0 0 0 # fdivs. + // 111011 - -----10011 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111011 - -----10100 0 1 1 1 1 0 0 1 0 0 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # fsubs + // 111011 - -----10100 1 1 1 1 1 0 1 1 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # fsubs. + // 111011 - -----10101 0 1 1 1 1 0 0 1 0 0 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # fadds + // 111011 - -----10101 1 1 1 1 1 0 1 1 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # fadds. + // 111011 - -----10110 0 1 1 0 1 0 0 1 0 1 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 01 0 0 0 # fsqrts + // 111011 - -----10110 1 1 1 0 1 0 1 1 1 1 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 01 0 0 0 # fsqrts. + // 111011 - -----10111 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111011 - -----11000 0 1 1 0 1 0 0 1 0 0 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # fres + // 111011 - -----11000 1 1 1 0 1 0 1 1 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # fres. + // 111011 - -----11001 0 1 1 1 0 1 0 1 0 0 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # fmuls + // 111011 - -----11001 1 1 1 1 0 1 1 1 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # fmuls. + // 111011 - -----11010 0 1 1 0 1 0 0 1 0 0 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # frsqrtes + // 111011 - -----11010 1 1 1 0 1 0 1 1 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # frsqrtes. + // 111011 - -----11011 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111011 - -----11100 0 1 1 1 1 1 0 1 0 0 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # fmsubs + // 111011 - -----11100 1 1 1 1 1 1 1 1 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # fmsubs. + // 111011 - -----11101 0 1 1 1 1 1 0 1 0 0 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # fmadds + // 111011 - -----11101 1 1 1 1 1 1 1 1 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # fmadds. + // 111011 - -----11110 0 1 1 1 1 1 0 1 0 0 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # fnmsubs + // 111011 - -----11110 1 1 1 1 1 1 1 1 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # fnmsubs. + // 111011 - -----11111 0 1 1 1 1 1 0 1 0 0 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # fnmadds + // 111011 - -----11111 1 1 1 1 1 1 1 1 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # fnmadds. + // 111100 - ---------- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + //#111101 - ---------0 0 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 # stfdp (ucoded) + // 111101 - ---------0 1 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111101 - ---------1 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111110 - ---------- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + //#111111 - -----1---- - 0 - - - 0 0 0 00 0 0 0 + // 111111 - 0000000000 - 1 0 1 1 0 0 1 0 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # fcmpu + // 111111 - 0000000001 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 000000001- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 00000001-- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 0000001000 0 1 1 1 1 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # fcpsgn + // 111111 - 0000001000 1 1 1 1 1 0 1 0 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # fcpsgn. + // 111111 - 0000001001 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 000000101- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 0000001100 0 1 1 0 1 0 0 1 0 0 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # frsp + // 111111 - 0000001100 1 1 1 0 1 0 1 1 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # frsp. + // 111111 - 0000001101 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 0000001110 0 1 1 0 1 0 0 1 0 0 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # fctiw + // 111111 - 0000001110 1 1 1 0 1 0 1 1 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # fctiw. + // 111111 - 0000001111 0 1 1 0 1 0 0 1 0 0 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # fctiwz + // 111111 - 0000001111 1 1 1 0 1 0 1 1 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # fctiwz. + // 111111 - -----10000 - 1 1 0 1 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 1 0 0 # prenormalization + // 111111 - -----10001 0 0 1 1 0 1 0 1 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 1 0 0 # fmul_uc + // 111111 - -----10001 1 0 1 1 0 1 1 1 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 1 0 0 # fmul_uc. + // 111111 - -----10010 0 1 1 1 1 0 0 1 0 1 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 10 0 0 0 # fdiv + // 111111 - -----10010 1 1 1 1 1 0 1 1 1 1 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 10 0 0 0 # fdiv. + // 111111 - -----10011 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - -----10100 0 1 1 1 1 0 0 1 0 0 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # fsub + // 111111 - -----10100 1 1 1 1 1 0 1 1 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # fsub. + // 111111 - -----10101 0 1 1 1 1 0 0 1 0 0 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # fadd + // 111111 - -----10101 1 1 1 1 1 0 1 1 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # fadd. + // 111111 - -----10110 0 1 1 0 1 0 0 1 0 1 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 01 0 0 0 # fsqrt + // 111111 - -----10110 1 1 1 0 1 0 1 1 1 1 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 01 0 0 0 # fsqrt. + // 111111 - -----10111 0 1 1 1 1 1 0 0 0 0 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # fsel + // 111111 - -----10111 1 1 1 1 1 1 1 0 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # fsel. + // 111111 - -----11000 0 1 1 0 1 0 0 1 0 0 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # fre + // 111111 - -----11000 1 1 1 0 1 0 1 1 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # fre. + // 111111 - -----11001 0 1 1 1 0 1 0 1 0 0 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # fmul + // 111111 - -----11001 1 1 1 1 0 1 1 1 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # fmul. + // 111111 - -----11010 0 1 1 0 1 0 0 1 0 0 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # frsqrte + // 111111 - -----11010 1 1 1 0 1 0 1 1 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # frsqrte. + // 111111 - -----11011 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - -----11100 0 1 1 1 1 1 0 1 0 0 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # fmsub + // 111111 - -----11100 1 1 1 1 1 1 1 1 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # fmsub. + // 111111 - -----11101 0 1 1 1 1 1 0 1 0 0 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # fmadd + // 111111 - -----11101 1 1 1 1 1 1 1 1 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # fmadd. + // 111111 - -----11110 0 1 1 1 1 1 0 1 0 0 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # fnmsub + // 111111 - -----11110 1 1 1 1 1 1 1 1 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # fnmsub. + // 111111 - -----11111 0 1 1 1 1 1 0 1 0 0 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # fnmadd + // 111111 - -----11111 1 1 1 1 1 1 1 1 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # fnmadd. + // 111111 - 0000100000 - 1 0 1 1 0 0 1 0 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # fcmpo + // 111111 - 0000100001 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 000010001- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 000010010- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 0000100110 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # mtfsb1 + // 111111 - 0000100110 1 1 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # mtfsb1. + // 111111 - 0000100111 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 0000101000 0 1 1 0 1 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # fneg + // 111111 - 0000101000 1 1 1 0 1 0 1 0 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # fneg. + // 111111 - 0000101001 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 000010101- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 00001011-- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + //#111111 - 000011---- - 0 - - - 0 0 0 00 0 0 0 + // 111111 - 0001000000 - 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # mcrfs + // 111111 - 0001000001 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 000100001- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 000100010- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 0001000110 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # mtfsb0 + // 111111 - 0001000110 1 1 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # mtfsb0. + // 111111 - 0001000111 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 0001001000 0 1 1 0 1 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # fmr + // 111111 - 0001001000 1 1 1 0 1 0 1 0 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # fmr. + // 111111 - 0001001001 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 000100101- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 00010011-- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + //#111111 - 000101---- - 0 - - - 0 0 0 00 0 0 0 + // 111111 - 000110---- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + //#111111 - 000111---- - 0 - - - 0 0 0 00 0 0 0 + // 111111 - 0010000000 - 1 0 1 1 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # ftdiv + // 111111 - 001000010- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 0010000110 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # mtfsfi + // 111111 - 0010000110 1 1 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # mtfsfi. + // 111111 - 0010000111 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 0010001000 0 1 1 0 1 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # fnabs + // 111111 - 0010001000 1 1 1 0 1 0 1 0 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # fnabs. + // 111111 - 0010001001 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 001000101- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 001000110- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 0010001110 0 1 1 0 1 0 0 1 0 0 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # fctiwu + // 111111 - 0010001110 1 1 1 0 1 0 1 1 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # fctiwu. + // 111111 - 0010001111 0 1 1 0 1 0 0 1 0 0 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # fctiduz + // 111111 - 0010001111 1 1 1 0 1 0 1 1 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # fctiduz. + //#111111 - 001001---- - 0 - - - 0 0 0 00 0 0 0 + // 111111 - 0010100000 - 1 0 0 1 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # ftsqrt + //#111111 - 001011---- - 0 - - - 0 0 0 00 0 0 0 + // 111111 - 0011000--- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 00110010-- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 001100110- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 0011001110 0 0 1 0 1 0 0 1 0 0 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # fcfiwu (removed) + // 111111 - 0011001110 1 0 1 0 1 0 1 1 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # fcfiwu. (removed) + // 111111 - 0011001111 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + //#111111 - 001101---- - 0 - - - 0 0 0 00 0 0 0 + // 111111 - 001110---- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + //#111111 - 001111---- - 0 - - - 0 0 0 00 0 0 0 + // 111111 - 0100000--- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 0100001000 0 1 1 0 1 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # fabs + // 111111 - 0100001000 1 1 1 0 1 0 1 0 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # fabs. + // 111111 - 0100001001 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 010000101- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 01000011-- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + //#111111 - 010001---- - 0 - - - 0 0 0 00 0 0 0 + // 111111 - 010010---- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + //#111111 - 010011---- - 0 - - - 0 0 0 00 0 0 0 + // 111111 - 010100---- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + //#111111 - 010101---- - 0 - - - 0 0 0 00 0 0 0 + // 111111 - 010110---- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + //#111111 - 010111---- - 0 - - - 0 0 0 00 0 0 0 + // 111111 - 0110000--- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 0110001000 0 1 1 0 1 0 0 1 0 0 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # frin + // 111111 - 0110001000 1 1 1 0 1 0 1 1 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # frin. + // 111111 - 0110001001 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 011000101- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 01100011-- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + //#111111 - 011001---- - 0 - - - 0 0 0 0 00 0 0 0 + // 111111 - 0110100--- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 0110101000 0 1 1 0 1 0 0 1 0 0 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # friz + // 111111 - 0110101000 1 1 1 0 1 0 1 1 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # friz. + // 111111 - 0110101001 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 011010101- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 01101011-- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + //#111111 - 011011---- - 0 - - - 0 0 0 0 00 0 0 0 + // 111111 - 0111000--- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 0111001000 0 1 1 0 1 0 0 1 0 0 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # frip + // 111111 - 0111001000 1 1 1 0 1 0 1 1 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # frip. + // 111111 - 0111001001 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 011100101- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 01110011-- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + //#111111 - 011101---- - 0 - - - 0 0 0 0 00 0 0 0 + // 111111 - 0111100--- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 0111101000 0 1 1 0 1 0 0 1 0 0 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # frim + // 111111 - 0111101000 1 1 1 0 1 0 1 1 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # frim. + // 111111 - 0111101001 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 011110101- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 01111011-- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + //#111111 - 011111---- - 0 - - - 0 0 0 00 0 0 0 + // 111111 - 100000---- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + //#111111 - 100001---- - 0 - - - 0 0 0 00 0 0 0 + // 111111 - 100010---- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + //#111111 - 100011---- - 0 - - - 0 0 0 00 0 0 0 + // 111111 - 10010000-- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 100100010- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 1001000110 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 1001000111 0 1 1 0 0 0 0 0 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # mffs + // 111111 - 1001000111 1 1 1 0 0 0 1 0 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # mffs. + // 111111 - 1001001--- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + //#111111 - 100101---- - 0 - - - 0 0 0 00 0 0 0 + // 111111 - 100110---- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + //#111111 - 100111---- - 0 - - - 0 0 0 00 0 0 0 + // 111111 - 101000---- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + //#111111 - 101001---- - 0 - - - 0 0 0 00 0 0 0 + // 111111 - 101010---- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + //#111111 - 101011---- - 0 - - - 0 0 0 00 0 0 0 + // 111111 - 10110000-- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 101100010- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 1011000110 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 1011000111 0 1 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # mtfsf + // 111111 - 1011000111 1 1 0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # mtfsf. + // 111111 - 1011001--- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + //#111111 - 101101---- - 0 - - - 0 0 0 00 0 0 0 + // 111111 - 101110---- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + //#111111 - 101111---- - 0 - - - 0 0 0 00 0 0 0 + // 111111 - 110000---- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + //#111111 - 110001---- - 0 - - - 0 0 0 00 0 0 0 + // 111111 - 1100100--- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 11001010-- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 110010110- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 1100101110 0 1 1 0 1 0 0 1 0 0 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # fctid + // 111111 - 1100101110 1 1 1 0 1 0 1 1 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # fctid. + // 111111 - 1100101111 0 1 1 0 1 0 0 1 0 0 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # fctidz + // 111111 - 1100101111 1 1 1 0 1 0 1 1 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # fctidz. + + //#111111 - 110011---- - 0 - - - 0 0 0 00 0 0 0 + // 111111 - 1101000--- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 11010010-- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 110100110- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 1101001110 0 1 1 0 1 0 0 1 0 0 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # fcfid + // 111111 - 1101001110 1 1 1 0 1 0 1 1 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # fcfid. + // 111111 - 1101001111 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + //#111111 - 110101---- - 0 - - - 0 0 0 00 0 0 0 + // 111111 - 110110---- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + //#111111 - 110111---- - 0 - - - 0 0 0 00 0 0 0 + // 111111 - 111000---- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + //#111111 - 111001---- - 0 - - - 0 0 0 00 0 0 0 + // 111111 - 1110100--- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 11101010-- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 111010110- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + // 111111 - 1110101110 0 1 1 0 1 0 0 1 0 0 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # fctidu + // 111111 - 1110101110 1 1 1 0 1 0 1 1 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # fctidu. + // 111111 - 1110101111 0 1 1 0 1 0 0 1 0 0 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # fctiwuz + // 111111 - 1110101111 1 1 1 0 1 0 1 1 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # fctiwuz. + //#111111 - 111011---- - 0 - - - 0 0 0 00 0 0 0 + // 111111 - 1111000--- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 000000 - 00 00 0 0 0 + // 111111 - 11110010-- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 000000 - 00 00 0 0 0 + // 111111 - 111100110- - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 000000 - 00 00 0 0 0 + // 111111 - 1111001110 0 1 1 0 1 0 0 1 0 0 - 0 0 0 0 0 0 0 0 0 00 ------ 0 00 00 0 0 0 # fcfidu + // 111111 - 1111001110 1 1 1 0 1 0 1 1 1 0 - 0 0 0 0 0 0 0 0 0 00 ------ 1 00 00 0 0 0 # fcfidu. + // 111111 - 1111001111 - 0 - - - - - - - - - 0 0 - 0 - - - - 0 00 000000 - 00 00 0 0 0 + //#111111 - 111101---- - 0 - - - 0 0 0 00 0 0 0 + //#111111 - 111110---- - 0 - - - - - - - - - 0 0 - 0 1 0 0 0 0 00 ------ - 00 00 1 0 0 # reserve for + // 111111 - 111111---- - 0 - - - - - - - - - - - - - 1 - - - - -- 110011 - -- -- - - - # no more <=0 + + // ######################################################################### + // .e + //@@ ESPRESSO TABLE END @@ + +//@@ ESPRESSO LOGIC START @@ +// logic generated on: Tue May 3 12:09:00 2011 +assign isfu_dec_is0 = ( pri_is0[0] & pri_is0[1] & pri_is0[3] & pri_is0[4] + & pri_is0[5] & ~sec_is0[21] & ~sec_is0[22] + & ~sec_is0[23] & ~sec_is0[24] & ~sec_is0[25] + & sec_is0[27] & ~sec_is0[29] & ~sec_is0[30]) | + ( pri_is0[0] & pri_is0[1] & ~pri_is0[3] & pri_is0[4] + & pri_is0[5] & ~sec_is0[21] & ~sec_is0[22] + & sec_is0[23] & sec_is0[24] & ~sec_is0[27] + & sec_is0[28] & ~sec_is0[29] & sec_is0[30] + & ~sec_is0[31]) | + ( pri_is0[0] & pri_is0[1] & pri_is0[3] & pri_is0[4] + & pri_is0[5] & ~sec_is0[21] & sec_is0[22] + & sec_is0[23] & sec_is0[27] & ~sec_is0[28] + & ~sec_is0[29] & ~sec_is0[30]) | + ( pri_is0[1] & pri_is0[2] & pri_is0[3] & pri_is0[4] + & pri_is0[5] & sec_is0[21] & ~sec_is0[23] + & sec_is0[24] & sec_is0[26] & ~sec_is0[27] + & sec_is0[28] & sec_is0[29] & sec_is0[30]) | + ( pri_is0[0] & pri_is0[1] & pri_is0[4] & pri_is0[5] + & sec_is0[21] & sec_is0[22] & sec_is0[24] + & ~sec_is0[25] & sec_is0[27] & sec_is0[28] + & sec_is0[29] & ~sec_is0[30]) | + ( pri_is0[1] & pri_is0[2] & pri_is0[3] & pri_is0[4] + & pri_is0[5] & sec_is0[21] & sec_is0[24] + & ~sec_is0[25] & sec_is0[26] & ~sec_is0[27] + & sec_is0[28] & sec_is0[29] & sec_is0[30]) | + ( pri_is0[1] & pri_is0[2] & pri_is0[3] & pri_is0[4] + & pri_is0[5] & sec_is0[21] & ~sec_is0[22] + & sec_is0[26] & ~sec_is0[27] & sec_is0[28] + & sec_is0[29] & sec_is0[30]) | + ( pri_is0[0] & pri_is0[1] & pri_is0[3] & pri_is0[4] + & pri_is0[5] & ~sec_is0[21] & ~sec_is0[24] + & ~sec_is0[25] & sec_is0[27] & ~sec_is0[28] + & ~sec_is0[29] & ~sec_is0[30]) | + ( pri_is0[0] & pri_is0[1] & pri_is0[3] & pri_is0[4] + & pri_is0[5] & ~sec_is0[21] & ~sec_is0[22] + & ~sec_is0[23] & ~sec_is0[24] & ~sec_is0[28] + & ~sec_is0[29] & ~sec_is0[30]) | + ( pri_is0[0] & pri_is0[1] & pri_is0[3] & pri_is0[4] + & pri_is0[5] & sec_is0[21] & sec_is0[22] + & ~sec_is0[24] & sec_is0[25] & sec_is0[27] + & sec_is0[28] & sec_is0[29]) | + ( pri_is0[1] & pri_is0[2] & pri_is0[3] & pri_is0[4] + & pri_is0[5] & sec_is0[21] & ~sec_is0[22] + & ~sec_is0[23] & sec_is0[24] & sec_is0[25] + & sec_is0[26] & sec_is0[27] & sec_is0[28]) | + ( pri_is0[0] & pri_is0[1] & pri_is0[3] & pri_is0[4] + & pri_is0[5] & sec_is0[21] & ~sec_is0[22] + & sec_is0[24] & ~sec_is0[25] & ~sec_is0[27] + & sec_is0[28] & sec_is0[29] & sec_is0[30]) | + ( pri_is0[0] & pri_is0[1] & pri_is0[3] & pri_is0[4] + & pri_is0[5] & ~sec_is0[21] & ~sec_is0[22] + & ~sec_is0[23] & ~sec_is0[25] & ~sec_is0[28] + & ~sec_is0[29] & ~sec_is0[30]) | + ( pri_is0[1] & pri_is0[2] & pri_is0[3] & pri_is0[4] + & pri_is0[5] & sec_is0[21] & ~sec_is0[22] + & sec_is0[24] & sec_is0[26] & sec_is0[28] + & sec_is0[29] & sec_is0[30]) | + ( pri_is0[1] & pri_is0[2] & pri_is0[3] & pri_is0[4] + & pri_is0[5] & sec_is0[21] & ~sec_is0[22] + & sec_is0[23] & sec_is0[24] & ~sec_is0[25] + & sec_is0[26] & sec_is0[27] & sec_is0[28] + & sec_is0[30]) | + ( pri_is0[0] & pri_is0[1] & pri_is0[3] & pri_is0[4] + & pri_is0[5] & ~sec_is0[21] & ~sec_is0[22] + & ~sec_is0[23] & ~sec_is0[24] & sec_is0[25] + & ~sec_is0[27] & sec_is0[28] & sec_is0[29] + & ~sec_is0[30]) | + ( pri_is0[0] & pri_is0[1] & pri_is0[3] & pri_is0[4] + & pri_is0[5] & ~sec_is0[21] & ~sec_is0[22] + & ~sec_is0[24] & ~sec_is0[27] & ~sec_is0[28] + & ~sec_is0[29] & ~sec_is0[30]) | + ( pri_is0[0] & pri_is0[1] & pri_is0[3] & pri_is0[4] + & pri_is0[5] & ~sec_is0[21] & ~sec_is0[22] + & sec_is0[23] & ~sec_is0[24] & ~sec_is0[25] + & sec_is0[28] & sec_is0[29] & ~sec_is0[30]) | + ( pri_is0[0] & pri_is0[1] & pri_is0[3] & pri_is0[4] + & pri_is0[5] & ~sec_is0[21] & ~sec_is0[22] + & ~sec_is0[23] & sec_is0[24] & ~sec_is0[25] + & ~sec_is0[27] & sec_is0[28] & sec_is0[29] + & ~sec_is0[30]) | + ( pri_is0[0] & pri_is0[1] & pri_is0[3] & pri_is0[4] + & pri_is0[5] & ~sec_is0[21] & ~sec_is0[22] + & ~sec_is0[24] & ~sec_is0[25] & sec_is0[27] + & sec_is0[28] & sec_is0[29]) | + ( pri_is0[1] & pri_is0[2] & pri_is0[3] & pri_is0[4] + & pri_is0[5] & sec_is0[21] & ~sec_is0[22] + & sec_is0[24] & sec_is0[25] & sec_is0[26] + & sec_is0[27] & sec_is0[28] & sec_is0[29]) | + ( pri_is0[0] & pri_is0[1] & pri_is0[4] & pri_is0[5] + & sec_is0[26] & sec_is0[27] & ~sec_is0[29]) | + ( pri_is0[0] & pri_is0[1] & pri_is0[4] & pri_is0[5] + & sec_is0[26] & sec_is0[29] & ~sec_is0[30]) | + ( pri_is0[0] & pri_is0[1] & pri_is0[4] & pri_is0[5] + & sec_is0[26] & sec_is0[28] & ~sec_is0[29]) | + ( pri_is0[0] & pri_is0[1] & pri_is0[4] & pri_is0[5] + & sec_is0[26] & sec_is0[27] & sec_is0[28]) | + ( pri_is0[0] & pri_is0[1] & ~pri_is0[2]) | + ( pri_is0[0] & pri_is0[1] & pri_is0[3] & pri_is0[4] + & pri_is0[5] & sec_is0[26] & sec_is0[28]) | + ( pri_is0[0] & pri_is0[1] & pri_is0[3] & pri_is0[4] + & pri_is0[5] & sec_is0[26] & ~sec_is0[30]); + +assign tv = (~pri_is0[3] & sec_is0[30] & ~sec_is0[31]) | + ( pri_is0[2] & pri_is0[4] & ~sec_is0[21] & sec_is0[22]) | + ( pri_is0[2] & sec_is0[20] & ~sec_is0[23] & ~sec_is0[24] + & ~sec_is0[26] & ~sec_is0[27] & ~sec_is0[28] & sec_is0[29] + & sec_is0[30]) | + ( pri_is0[2] & sec_is0[22] & ~sec_is0[23] & sec_is0[24] + & sec_is0[26] & ~sec_is0[27] & sec_is0[28] & sec_is0[29] + & sec_is0[30]) | + ( pri_is0[2] & pri_is0[4] & sec_is0[22] & ~sec_is0[24] + & sec_is0[27]) | + ( pri_is0[2] & pri_is0[4] & sec_is0[21] & ~sec_is0[22] + & ~sec_is0[23] & sec_is0[28]) | + ( pri_is0[0] & pri_is0[2] & pri_is0[4] & ~sec_is0[25] + & sec_is0[27]) | + ( pri_is0[0] & pri_is0[2] & pri_is0[4] & ~sec_is0[23] + & sec_is0[27]) | + ( pri_is0[0] & pri_is0[2] & pri_is0[4] & sec_is0[26]) | + (~pri_is0[2] & ~pri_is0[3]); + +assign av = ( pri_is0[3] & sec_is0[20] & ~sec_is0[22] & ~sec_is0[23] + & sec_is0[24] & ~sec_is0[26] & ~sec_is0[27] & ~sec_is0[28] + & sec_is0[29] & sec_is0[30]) | + ( pri_is0[0] & pri_is0[3] & pri_is0[4] & ~sec_is0[22] + & ~sec_is0[23] & ~sec_is0[24] & ~sec_is0[25] & ~sec_is0[26] + & ~sec_is0[28]) | + ( pri_is0[0] & pri_is0[3] & pri_is0[4] & ~sec_is0[23] + & sec_is0[25] & ~sec_is0[26] & ~sec_is0[27] & ~sec_is0[29]) | + (~pri_is0[0] & sec_is0[21] & sec_is0[23] & sec_is0[24] + & ~sec_is0[25] & sec_is0[29]) | + ( pri_is0[0] & pri_is0[3] & pri_is0[4] & ~sec_is0[24] + & ~sec_is0[25] & ~sec_is0[26] & ~sec_is0[27] & ~sec_is0[29] + & ~sec_is0[30]) | + (~pri_is0[0] & sec_is0[21] & ~sec_is0[22] & sec_is0[23] + & ~sec_is0[27]) | + ( pri_is0[0] & pri_is0[2] & pri_is0[4] & sec_is0[26] + & sec_is0[27] & sec_is0[28]) | + ( pri_is0[0] & pri_is0[2] & pri_is0[4] & sec_is0[26] + & ~sec_is0[27] & ~sec_is0[28] & sec_is0[29]) | + ( pri_is0[0] & pri_is0[2] & pri_is0[4] & sec_is0[26] + & sec_is0[28] & ~sec_is0[29]) | + ( pri_is0[0] & pri_is0[2] & sec_is0[26] & sec_is0[30]) | + ( pri_is0[1] & ~pri_is0[2] & pri_is0[3]); + +assign bv = (~pri_is0[0] & sec_is0[21] & ~sec_is0[25] & ~sec_is0[29]) | + ( pri_is0[2] & ~pri_is0[3] & sec_is0[28] & sec_is0[30] + & ~sec_is0[31]) | + (~pri_is0[0] & sec_is0[21] & sec_is0[23] & sec_is0[25] + & sec_is0[27] & sec_is0[28] & sec_is0[29]) | + ( pri_is0[0] & pri_is0[2] & pri_is0[4] & ~sec_is0[24] + & ~sec_is0[27] & ~sec_is0[28] & ~sec_is0[29] & ~sec_is0[30]) | + ( pri_is0[2] & pri_is0[4] & sec_is0[22] & ~sec_is0[24] + & ~sec_is0[26]) | + ( pri_is0[0] & pri_is0[2] & pri_is0[4] & sec_is0[23] + & sec_is0[24] & ~sec_is0[25] & sec_is0[29]) | + ( pri_is0[0] & pri_is0[2] & pri_is0[4] & ~sec_is0[25] + & ~sec_is0[26] & sec_is0[27]) | + ( pri_is0[0] & pri_is0[2] & pri_is0[4] & ~sec_is0[21] + & sec_is0[24] & sec_is0[27] & ~sec_is0[30]) | + ( pri_is0[0] & pri_is0[2] & sec_is0[26] & sec_is0[28] + & sec_is0[30]) | + ( pri_is0[0] & pri_is0[2] & pri_is0[4] & ~sec_is0[23] + & ~sec_is0[26] & sec_is0[27]) | + ( pri_is0[0] & pri_is0[2] & pri_is0[4] & sec_is0[26] + & ~sec_is0[30]); + +assign cv = ( pri_is0[0] & pri_is0[2] & sec_is0[26] & ~sec_is0[28] + & sec_is0[30]) | + ( pri_is0[0] & pri_is0[2] & sec_is0[26] & sec_is0[29] + & sec_is0[30]) | + ( pri_is0[0] & pri_is0[2] & pri_is0[4] & sec_is0[26] + & sec_is0[27] & sec_is0[28]); + +assign record_form = ( pri_is0[0] & pri_is0[2] & ~sec_is0[21] & sec_is0[24] + & sec_is0[27] & sec_is0[31]) | + ( pri_is0[0] & pri_is0[2] & ~sec_is0[23] & sec_is0[29] + & sec_is0[31]) | + ( pri_is0[0] & pri_is0[2] & ~sec_is0[25] & sec_is0[28] + & sec_is0[29] & sec_is0[31]) | + ( pri_is0[2] & sec_is0[22] & ~sec_is0[24] + & sec_is0[27] & sec_is0[31]) | + ( pri_is0[0] & pri_is0[2] & ~sec_is0[23] & sec_is0[27] + & sec_is0[31]) | + ( pri_is0[0] & pri_is0[2] & ~sec_is0[25] & sec_is0[27] + & sec_is0[31]) | + ( pri_is0[0] & pri_is0[2] & sec_is0[26] & sec_is0[30] + & sec_is0[31]) | + ( pri_is0[0] & pri_is0[2] & sec_is0[26] & sec_is0[29] + & sec_is0[31]) | + ( pri_is0[0] & pri_is0[2] & sec_is0[26] & sec_is0[28] + & sec_is0[31]) | + ( pri_is0[0] & pri_is0[2] & sec_is0[26] & sec_is0[27] + & sec_is0[31]); + +assign fpscr_wr = ( pri_is0[2] & ~pri_is0[3] & ~sec_is0[30] & sec_is0[31]) | + ( pri_is0[0] & pri_is0[2] & pri_is0[4] & ~sec_is0[23] + & ~sec_is0[24] & ~sec_is0[26] & ~sec_is0[27] & ~sec_is0[29]) | + ( pri_is0[2] & pri_is0[4] & sec_is0[22] & ~sec_is0[25] + & sec_is0[27] & sec_is0[29]) | + ( pri_is0[2] & pri_is0[4] & sec_is0[21] & ~sec_is0[24] + & sec_is0[27]) | + ( pri_is0[2] & pri_is0[4] & ~sec_is0[21] & sec_is0[22] + & sec_is0[23] & sec_is0[27]) | + ( pri_is0[0] & pri_is0[2] & sec_is0[26] & ~sec_is0[29] + & sec_is0[30]) | + ( pri_is0[0] & pri_is0[2] & pri_is0[4] & sec_is0[26] + & sec_is0[28] & ~sec_is0[30]) | + ( pri_is0[0] & pri_is0[2] & pri_is0[3] & pri_is0[4] + & ~sec_is0[25] & sec_is0[27] & sec_is0[28]) | + ( pri_is0[0] & pri_is0[2] & pri_is0[4] & sec_is0[26] + & sec_is0[29] & ~sec_is0[30]) | + ( pri_is0[0] & pri_is0[2] & pri_is0[4] & sec_is0[26] + & sec_is0[27]); + +assign cordered = ( pri_is0[2] & ~sec_is0[21] & sec_is0[22] & sec_is0[27] + & sec_is0[31]) | + ( pri_is0[0] & pri_is0[2] & pri_is0[4] & ~sec_is0[23] + & sec_is0[24] & ~sec_is0[26] & ~sec_is0[27]) | + ( pri_is0[0] & pri_is0[2] & pri_is0[4] & ~sec_is0[23] + & ~sec_is0[26] & ~sec_is0[27] & sec_is0[29]) | + ( pri_is0[2] & sec_is0[22] & ~sec_is0[24] & sec_is0[27] + & sec_is0[31]) | + ( pri_is0[0] & pri_is0[2] & pri_is0[4] & ~sec_is0[25] + & ~sec_is0[26] & ~sec_is0[27] & sec_is0[28] & sec_is0[29]) | + ( pri_is0[0] & pri_is0[2] & ~sec_is0[23] & sec_is0[27] + & sec_is0[31]) | + ( pri_is0[0] & pri_is0[2] & ~sec_is0[25] & sec_is0[27] + & sec_is0[31]) | + ( pri_is0[0] & pri_is0[2] & sec_is0[26] & ~sec_is0[27] + & ~sec_is0[28] & sec_is0[30]) | + ( pri_is0[0] & pri_is0[2] & sec_is0[26] & sec_is0[29] + & sec_is0[31]) | + ( pri_is0[0] & pri_is0[2] & sec_is0[26] & sec_is0[27] + & sec_is0[31]) | + ( pri_is0[0] & pri_is0[2] & sec_is0[26] & sec_is0[28] + & sec_is0[31]); + +assign ordered = ( pri_is0[0] & pri_is0[2] & pri_is0[4] & sec_is0[26] + & ~sec_is0[27] & sec_is0[29] & ~sec_is0[30]); + +assign fpscr_mv = ( pri_is0[0] & pri_is0[4] & ~sec_is0[25] & sec_is0[28] + & sec_is0[29]) | + ( pri_is0[0] & pri_is0[4] & ~sec_is0[23]); + +assign ld_st_is0 = (~pri_is0[0] & pri_is0[1] & pri_is0[2] & pri_is0[3] + & pri_is0[4] & pri_is0[5] & sec_is0[20] & ~sec_is0[21] + & ~sec_is0[22] & ~sec_is0[23] & ~sec_is0[26] & ~sec_is0[27] + & ~sec_is0[28] & sec_is0[29] & sec_is0[30]) | + (~pri_is0[0] & pri_is0[1] & pri_is0[2] & pri_is0[3] + & pri_is0[4] & pri_is0[5] & sec_is0[21] + & ~sec_is0[22] & ~sec_is0[23] & sec_is0[24] + & sec_is0[25] & sec_is0[26] & sec_is0[27] + & sec_is0[28]) | + (~pri_is0[0] & pri_is0[1] & pri_is0[2] & pri_is0[3] + & pri_is0[4] & pri_is0[5] & sec_is0[21] + & ~sec_is0[22] & sec_is0[23] & sec_is0[24] + & ~sec_is0[25] & sec_is0[26] & sec_is0[27] + & sec_is0[28] & sec_is0[30]) | + (~pri_is0[0] & pri_is0[1] & pri_is0[2] & pri_is0[3] + & pri_is0[4] & pri_is0[5] & sec_is0[21] + & ~sec_is0[22] & sec_is0[24] & sec_is0[25] + & sec_is0[26] & sec_is0[27] & sec_is0[28] + & sec_is0[29]) | + (~pri_is0[0] & pri_is0[1] & pri_is0[2] & pri_is0[3] + & pri_is0[4] & pri_is0[5] & sec_is0[21] + & sec_is0[24] & ~sec_is0[25] & sec_is0[26] + & ~sec_is0[27] & sec_is0[28] & sec_is0[29] + & sec_is0[30]) | + (~pri_is0[0] & pri_is0[1] & pri_is0[2] & pri_is0[3] + & pri_is0[4] & pri_is0[5] & sec_is0[21] + & ~sec_is0[22] & sec_is0[26] & ~sec_is0[27] + & sec_is0[28] & sec_is0[29] & sec_is0[30]) | + (~pri_is0[0] & pri_is0[1] & pri_is0[2] & pri_is0[3] + & pri_is0[4] & pri_is0[5] & sec_is0[21] + & ~sec_is0[23] & sec_is0[24] & sec_is0[26] + & ~sec_is0[27] & sec_is0[28] & sec_is0[29] + & sec_is0[30]) | + (~pri_is0[0] & pri_is0[1] & pri_is0[2] & pri_is0[3] + & pri_is0[4] & pri_is0[5] & sec_is0[21] + & ~sec_is0[22] & sec_is0[24] & sec_is0[26] + & sec_is0[28] & sec_is0[29] & sec_is0[30]) | + ( pri_is0[0] & pri_is0[1] & ~pri_is0[2]); + +assign st_is0 = (~pri_is0[0] & pri_is0[1] & pri_is0[2] & pri_is0[3] + & pri_is0[4] & pri_is0[5] & sec_is0[20] + & ~sec_is0[21] & ~sec_is0[22] & ~sec_is0[23] + & sec_is0[24] & ~sec_is0[26] & ~sec_is0[27] + & ~sec_is0[28] & sec_is0[29] & sec_is0[30]) | + (~pri_is0[0] & pri_is0[1] & pri_is0[2] & pri_is0[3] + & pri_is0[4] & pri_is0[5] & sec_is0[21] & ~sec_is0[22] + & sec_is0[23] & sec_is0[24] & sec_is0[25] & sec_is0[26] + & sec_is0[27] & sec_is0[28] & sec_is0[29]) | + (~pri_is0[0] & pri_is0[1] & pri_is0[2] & pri_is0[3] + & pri_is0[4] & pri_is0[5] & sec_is0[21] & ~sec_is0[22] + & sec_is0[23] & sec_is0[24] & ~sec_is0[25] & sec_is0[26] + & sec_is0[27] & sec_is0[28] & sec_is0[30]) | + (~pri_is0[0] & pri_is0[1] & pri_is0[2] & pri_is0[3] + & pri_is0[4] & pri_is0[5] & sec_is0[21] & sec_is0[23] + & sec_is0[24] & ~sec_is0[25] & sec_is0[26] & ~sec_is0[27] + & sec_is0[28] & sec_is0[29] & sec_is0[30]) | + (~pri_is0[0] & pri_is0[1] & pri_is0[2] & pri_is0[3] + & pri_is0[4] & pri_is0[5] & sec_is0[21] & ~sec_is0[22] + & sec_is0[23] & sec_is0[26] & ~sec_is0[27] & sec_is0[28] + & sec_is0[29] & sec_is0[30]) | + ( pri_is0[0] & pri_is0[1] & ~pri_is0[2] & pri_is0[3]); + +assign indexed = ( pri_is0[2] & sec_is0[20] & ~sec_is0[23] & ~sec_is0[25] + & ~sec_is0[26] & ~sec_is0[27] & ~sec_is0[28] & sec_is0[29] + & sec_is0[30]) | + (~pri_is0[0] & sec_is0[21] & sec_is0[25] & sec_is0[26] + & ~sec_is0[27] & sec_is0[28] & sec_is0[29] & sec_is0[30]) | + (~pri_is0[0] & sec_is0[21] & sec_is0[24] & sec_is0[26] + & ~sec_is0[27] & sec_is0[28] & sec_is0[29] & sec_is0[30]) | + (~pri_is0[0] & sec_is0[21] & ~sec_is0[22] & ~sec_is0[25] + & sec_is0[29]); + +assign update_form = (~pri_is0[0] & pri_is0[1] & pri_is0[2] & pri_is0[3] + & pri_is0[4] & pri_is0[5] & sec_is0[21] & ~sec_is0[22] + & sec_is0[25] & sec_is0[26] & ~sec_is0[27] & sec_is0[28] + & sec_is0[29] & sec_is0[30]) | + ( pri_is0[0] & pri_is0[1] & ~pri_is0[2] & pri_is0[5]); + +assign forcealign = ( pri_is0[2] & pri_is0[3] & pri_is0[4] & sec_is0[21] + & sec_is0[22] & sec_is0[23] & sec_is0[24] + & sec_is0[25] & sec_is0[26]); + +assign single_precision_ldst = ( pri_is0[1] & ~pri_is0[2] & ~pri_is0[4]) | + (~pri_is0[0] & sec_is0[21] & ~sec_is0[22] + & sec_is0[28] & sec_is0[29] & ~sec_is0[30]) | + (~pri_is0[0] & sec_is0[21] & ~sec_is0[22] + & ~sec_is0[24]); + +assign int_word_ldst = ( pri_is0[2] & sec_is0[20] & ~sec_is0[22] + & ~sec_is0[23] & ~sec_is0[26] & ~sec_is0[27] + & ~sec_is0[28] & sec_is0[29] & sec_is0[30]) | + (~pri_is0[0] & sec_is0[22] & sec_is0[24] + & sec_is0[26] & ~sec_is0[27] & sec_is0[28] + & sec_is0[29] & sec_is0[30]) | + (~pri_is0[0] & sec_is0[21] & ~sec_is0[22] + & ~sec_is0[23] & sec_is0[28] & ~sec_is0[29]) | + (~pri_is0[0] & sec_is0[21] & ~sec_is0[25] + & ~sec_is0[29]); + +assign sign_ext_ldst = (~pri_is0[0] & sec_is0[21] & ~sec_is0[22] + & ~sec_is0[23] & sec_is0[28] & ~sec_is0[29] + & ~sec_is0[30]) | + (~pri_is0[0] & sec_is0[22] & ~sec_is0[23] + & sec_is0[24] & ~sec_is0[25]); + +assign ldst_extpid = (~pri_is0[0] & pri_is0[1] & pri_is0[2] & pri_is0[3] + & pri_is0[4] & pri_is0[5] & sec_is0[21] + & ~sec_is0[22] & sec_is0[24] & ~sec_is0[25] + & sec_is0[26] & sec_is0[27] & sec_is0[28] + & sec_is0[29] & sec_is0[30]); + +assign io_port = (~pri_is0[0] & pri_is0[1] & pri_is0[2] & pri_is0[3] + & pri_is0[4] & pri_is0[5] & sec_is0[20] + & ~sec_is0[21] & ~sec_is0[22] & ~sec_is0[23] + & ~sec_is0[26] & ~sec_is0[27] & ~sec_is0[28] + & sec_is0[29] & sec_is0[30]); + +assign io_port_ext = (~pri_is0[0] & pri_is0[1] & pri_is0[2] & pri_is0[3] + & pri_is0[4] & pri_is0[5] & sec_is0[20] + & ~sec_is0[21] & ~sec_is0[22] & ~sec_is0[23] + & ~sec_is0[25] & ~sec_is0[26] & ~sec_is0[27] + & ~sec_is0[28] & sec_is0[29] & sec_is0[30]); + +assign size[0] = (~pri_is0[1] & ~pri_is0[3]); + +assign size[1] = (~pri_is0[1] & ~pri_is0[3]); + +assign size[2] = ( pri_is0[4] & sec_is0[21] & ~sec_is0[22] & ~sec_is0[25] + & sec_is0[27] & sec_is0[29]) | + ( pri_is0[4] & sec_is0[21] & ~sec_is0[22] & sec_is0[24] + & ~sec_is0[27]) | + (~pri_is0[2] & pri_is0[4]); + +assign size[3] = ( pri_is0[2] & pri_is0[4] & sec_is0[21] & ~sec_is0[22] + & ~sec_is0[24]) | + ( pri_is0[2] & sec_is0[22] & sec_is0[24] & sec_is0[26] + & ~sec_is0[27] & sec_is0[28] & sec_is0[29] & sec_is0[30]) | + ( pri_is0[1] & ~pri_is0[2] & ~pri_is0[4]); + +assign size[4] = (~pri_is0[1] & ~pri_is0[3]); + +assign size[5] = (~pri_is0[1] & ~pri_is0[3]); + +assign cr_writer = ( pri_is0[2] & sec_is0[20] & ~sec_is0[22] & ~sec_is0[23] + & ~sec_is0[26] & ~sec_is0[27] & ~sec_is0[28] & sec_is0[29] + & sec_is0[30] & sec_is0[31]) | + ( pri_is0[0] & pri_is0[2] & ~sec_is0[25] & ~sec_is0[26] + & ~sec_is0[29] & ~sec_is0[30] & sec_is0[31]) | + ( pri_is0[0] & pri_is0[2] & ~sec_is0[21] & sec_is0[24] + & sec_is0[27] & sec_is0[31]) | + ( pri_is0[0] & pri_is0[2] & ~sec_is0[23] & ~sec_is0[26] + & sec_is0[31]) | + ( pri_is0[0] & pri_is0[2] & pri_is0[4] & ~sec_is0[22] + & ~sec_is0[26] & ~sec_is0[27] & ~sec_is0[28] + & ~sec_is0[29] & ~sec_is0[30]) | + ( pri_is0[0] & pri_is0[2] & ~sec_is0[25] & sec_is0[28] + & sec_is0[29] & sec_is0[31]) | + ( pri_is0[2] & sec_is0[22] & ~sec_is0[24] + & sec_is0[27] & sec_is0[31]) | + ( pri_is0[0] & pri_is0[2] & sec_is0[26] & sec_is0[30] + & sec_is0[31]) | + ( pri_is0[0] & pri_is0[2] & sec_is0[26] & sec_is0[29] + & sec_is0[31]) | + ( pri_is0[0] & pri_is0[2] & sec_is0[26] & sec_is0[28] + & sec_is0[31]) | + ( pri_is0[0] & pri_is0[2] & sec_is0[26] & sec_is0[27] + & sec_is0[31]); + +assign mffgpr = (~pri_is0[0] & pri_is0[1] & pri_is0[2] & pri_is0[3] + & pri_is0[4] & pri_is0[5] & sec_is0[20] + & ~sec_is0[21] & ~sec_is0[22] & ~sec_is0[23] + & ~sec_is0[24] & ~sec_is0[26] & ~sec_is0[27] + & ~sec_is0[28] & sec_is0[29] & sec_is0[30]) | + (~pri_is0[0] & pri_is0[1] & pri_is0[2] & pri_is0[3] + & pri_is0[4] & pri_is0[5] & sec_is0[21] & ~sec_is0[22] + & ~sec_is0[23] & sec_is0[24] & sec_is0[25] & sec_is0[26] + & sec_is0[27] & sec_is0[28]); + +assign mftgpr = (~pri_is0[0] & pri_is0[1] & pri_is0[2] & pri_is0[3] + & pri_is0[4] & pri_is0[5] & sec_is0[21] & ~sec_is0[22] + & sec_is0[23] & sec_is0[24] & ~sec_is0[25] & sec_is0[26] + & sec_is0[27] & sec_is0[28] & ~sec_is0[29] & sec_is0[30]) | + (~pri_is0[0] & pri_is0[1] & pri_is0[2] & pri_is0[3] + & pri_is0[4] & pri_is0[5] & sec_is0[21] & ~sec_is0[22] + & sec_is0[23] & sec_is0[24] & sec_is0[25] & sec_is0[26] + & sec_is0[27] & sec_is0[28] & sec_is0[29]) | + (~pri_is0[0] & pri_is0[1] & pri_is0[2] & pri_is0[3] + & pri_is0[4] & pri_is0[5] & sec_is0[20] & ~sec_is0[21] + & ~sec_is0[22] & ~sec_is0[23] & sec_is0[24] & ~sec_is0[26] + & ~sec_is0[27] & ~sec_is0[28] & sec_is0[29] & sec_is0[30]); + +assign fdiv_is0 = ( pri_is0[0] & pri_is0[1] & pri_is0[2] & pri_is0[4] + & pri_is0[5] & sec_is0[26] & ~sec_is0[27] & ~sec_is0[28] + & sec_is0[29] & ~sec_is0[30]); + +assign fsqrt_is0 = ( pri_is0[0] & pri_is0[1] & pri_is0[2] & pri_is0[4] + & pri_is0[5] & sec_is0[26] & ~sec_is0[27] & sec_is0[28] + & sec_is0[29] & ~sec_is0[30]); + +assign only_from_ucode = (~pri_is0[0] & pri_is0[1] & pri_is0[2] & pri_is0[3] + & pri_is0[4] & pri_is0[5] & sec_is0[21] & ~sec_is0[22] + & sec_is0[24] & sec_is0[25] & sec_is0[26] & sec_is0[27] + & sec_is0[28] & sec_is0[29]) | + (~pri_is0[0] & pri_is0[1] & pri_is0[2] & pri_is0[3] + & pri_is0[4] & pri_is0[5] & sec_is0[21] + & ~sec_is0[22] & sec_is0[23] & sec_is0[24] + & ~sec_is0[25] & sec_is0[26] & sec_is0[27] + & sec_is0[28] & ~sec_is0[29] & sec_is0[30]) | + (~pri_is0[0] & pri_is0[1] & pri_is0[2] & pri_is0[3] + & pri_is0[4] & pri_is0[5] & sec_is0[21] + & ~sec_is0[22] & ~sec_is0[23] & sec_is0[24] + & sec_is0[25] & sec_is0[26] & sec_is0[27] + & sec_is0[28]) | + ( pri_is0[0] & pri_is0[1] & pri_is0[2] & pri_is0[4] + & pri_is0[5] & sec_is0[26] & ~sec_is0[27] + & ~sec_is0[28] & ~sec_is0[29] & sec_is0[30]) | + ( pri_is0[0] & pri_is0[1] & pri_is0[2] & pri_is0[3] + & pri_is0[4] & pri_is0[5] & sec_is0[26] + & ~sec_is0[27] & ~sec_is0[28] & ~sec_is0[29]); + +assign no_ram = (~pri_is0[0] & pri_is0[1] & pri_is0[2] & pri_is0[3] + & pri_is0[4] & pri_is0[5] & sec_is0[21] + & ~sec_is0[22] & ~sec_is0[23] & sec_is0[25] + & sec_is0[26] & ~sec_is0[27] & sec_is0[28] + & sec_is0[29] & sec_is0[30]) | + ( pri_is0[0] & pri_is0[1] & ~pri_is0[2] & ~pri_is0[3] + & pri_is0[5]); + +assign only_graphics_mode = ( pri_is0[0] & pri_is0[1] & pri_is0[2] + & ~pri_is0[3] & pri_is0[4] & pri_is0[5] & ~sec_is0[21] + & ~sec_is0[22] & sec_is0[23] & sec_is0[24] & ~sec_is0[26] + & ~sec_is0[27] & sec_is0[28] & ~sec_is0[29] & sec_is0[30] + & ~sec_is0[31]) | + (~pri_is0[0] & pri_is0[1] & pri_is0[2] & pri_is0[3] + & pri_is0[4] & pri_is0[5] & sec_is0[21] + & ~sec_is0[22] & ~sec_is0[23] & sec_is0[24] + & sec_is0[25] & sec_is0[26] & sec_is0[27] + & sec_is0[28]) | + (~pri_is0[0] & pri_is0[1] & pri_is0[2] & pri_is0[3] + & pri_is0[4] & pri_is0[5] & sec_is0[21] + & ~sec_is0[22] & sec_is0[23] & sec_is0[24] + & ~sec_is0[25] & sec_is0[26] & sec_is0[27] + & sec_is0[28] & ~sec_is0[29] & sec_is0[30]) | + (~pri_is0[0] & pri_is0[1] & pri_is0[2] & pri_is0[3] + & pri_is0[4] & pri_is0[5] & sec_is0[21] + & ~sec_is0[22] & sec_is0[24] & sec_is0[25] + & sec_is0[26] & sec_is0[27] & sec_is0[28] + & sec_is0[29]); + +//@@ ESPRESSO LOGIC END @@ + + + + assign ldst_tag = {single_precision_ldst, int_word_ldst, sign_ext_ldst, iu_au_iu4_ucode_ext[0], ldst_tag_addr[0:4]}; // for lfiwax + + assign ldst_tag_addr = (mftgpr == 1'b0) ? is0_instr[06:10] : + is0_instr[16:20]; + + assign ram_mode_v = iu_au_iu4_isram; + + //---------------------------------------------------------------------------------------------------------------------- + // config bits + assign iu_au_config_iucr_din = iu_au_config_iucr; + + assign config_reg_scin = 0; + + + tri_rlmreg_p #(.INIT(0), .WIDTH(8)) config_reg( + .vd(vdd), + .gd(gnd), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .nclk(nclk), + .mpw1_b(mpw1_b), + .act(tiup), + .mpw2_b(mpw2_b), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .d_mode(tiup), + .scin(config_reg_scin[0:7]), + .scout(config_reg_scout[0:7]), + .din(iu_au_config_iucr_din), + .dout(iu_au_config_iucr_l2) + ); + + assign iu_au_config_iucr_int[0:7] = iu_au_config_iucr_l2[0:7]; + + assign graphics_mode = iu_au_config_iucr_int[0]; + + assign spare_unused[4:7] = iu_au_config_iucr_int[4:7]; + + assign is0_is_ucode = iu_au_iu4_ucode[0]; + + assign in_ucode_mode = iu_au_iu4_ucode[0] & is0_instr_v; + + // special ucode instructions getting issued when not doing ucode is bad + assign is0_invalid_kill_uc = ((~(in_ucode_mode | ram_mode_v)) & only_from_ucode) | ((~(graphics_mode | in_ucode_mode | ram_mode_v)) & only_graphics_mode); // can use any graphics mode insr in ucode + + // the XU must now do something like: + + //au_iu_is0_i_dec_internal <= (not au_iu_is0_i_dec_b) and not (not in_ucode_mode and au_iu_is0_ucode_only); + + assign is0_invalid_kill = ((~(graphics_mode | in_ucode_mode)) & only_graphics_mode) | is0_invalid_kill_uc; // can use any graphics mode insr in ucode + //is0_invalid_kill <= '0'; + + assign au_iu_iu4_no_ram = no_ram; + + assign is0_kill_or_divsqrt_b = (~(is0_invalid_kill)); + + assign is0_i_dec_b = (~(isfu_dec_is0 & is0_kill_or_divsqrt_b)); // inverted for timing + assign au_iu_iu4_i_dec_b = is0_i_dec_b; + + assign au_iu_is0_i_dec = (~is0_i_dec_b); + assign spare_unused[3] = au_iu_is0_i_dec; + + // fdiv and fsqrt will be handled by ucode. The fu may issue them lateer + // This signal is passed down the pipe to rf1, because + // these opcodes are used to initiate some operand checking so they should continue down the pipe and not be flushed because of ucode. + + // During fdiv/fsqrt the axu may select this thread before or after the "real" fxu selection. + // If the axu selects this thread earlier than the fxu, s1 is simply updated early. + // If the axu selects this thread later than the fxu, ucode instructions would get wiped out by the flush + // This signal protects the instruction from being flushed + //ignore_flush_is0 <= (fdiv_is0 or fsqrt_is0) and isfu_dec_is0; -- these opcodes will not change the FpScr or any Fpr. Only scratch reg s0 will be changed + assign ignore_flush_is0 = 1'b0; // disabled for a2o + + //---------------------------------------------------------------------------------------------------------------------- + + assign is0_to_ucode = (iu_au_iu4_2ucode) & isfu_dec_is0; //uCode from either a denorm or fdiv(s)(.) or fsqrt(s)(.) + assign au_iu_iu4_ucode[0:2] = iu_au_iu4_ucode[0:2]; + + assign is0_ldst_ra = (mftgpr == 1'b0) ? {iu_au_iu4_ucode_ext[1], is0_instr[11:15]} : + {iu_au_iu4_ucode_ext[0], is0_instr[6:10]}; // for mftgpr, make RA the target, same as updates + + assign is0_zero_r0 = ld_st_is0 & (is0_ldst_ra == 6'b000000); + + //---------------------------------------------------------------------------------------------------------------------- + // Interface to Core Decode + + // mftgpr RT, FRB + // 6:10, 16:20 + // mffgpr FRT, RB + // 6:10, 16:20 + // mfdp FRT t2 (mffgpr and io_port) + // 6:10 + // mtdp FRS s3 (mftgpr and io_port) + // 6:10 + // lfdx FRT, RA,RB + // 6:10,11:15,16:20 + // stfdx FRS, RA,RB + // 6:10,11:15,16:20 + + assign au_iu_iu4_t1_v = (update_form | mftgpr | fpscr_wr) & (~iu_au_iu4_ucode[1]); + assign au_iu_iu4_t1_t[0:2] = (fpscr_wr == 1'b1) ? 3'b111 : //fpscr or gpr + 3'b000; + assign au_iu_iu4_t1_a6[0:5] = (({iu_au_iu4_ucode_ext[1], is0_instr[11:15]}) & ({6{(~mftgpr) & (~fpscr_wr)}})) | + (({iu_au_iu4_ucode_ext[0], is0_instr[6:10]}) & ({6{ mftgpr & (~fpscr_wr)}})) | + ((6'b000000) & ({6{fpscr_wr}})); + + //---------------------------------------------------------------------------------------------------------------------- + assign au_iu_iu4_t2_v = tv & (~iu_au_iu4_ucode[1]); + assign au_iu_iu4_t2_a6[0:5] = (tv == 1'b0 & fpscr_wr == 1'b1) ? 6'b110000 : //for compares, need fpscr rename, big targ + {iu_au_iu4_ucode_ext[0], is0_instr[06:10]}; + assign au_iu_iu4_t2_t[0:2] = 3'b110; //fpr + + //---------------------------------------------------------------------------------------------------------------------- + assign au_iu_iu4_t3_v = cr_writer & (~iu_au_iu4_ucode[1]); + assign au_iu_iu4_t3_a6[0:5] = ({3'b000, is0_instr[06:08]} & {6{(~record_form)}}) | ((6'b000001) & {6{record_form}}); + assign au_iu_iu4_t3_t[0:2] = 3'b001; //cr + + //---------------------------------------------------------------------------------------------------------------------- + assign au_iu_iu4_s1_v = ((ld_st_is0 & (~is0_zero_r0) & (~mftgpr) & (~mffgpr)) & ld_st_is0) | (av & (~ld_st_is0)); + assign au_iu_iu4_s1_a6[0:5] = ((is0_ldst_ra[0:5]) & {6{ld_st_is0}}) | (({iu_au_iu4_ucode_ext[1], is0_instr[11:15]}) & {6{(~ld_st_is0)}}); + + //gpr + assign au_iu_iu4_s1_t[0:2] = (3'b000 & {3{ld_st_is0}}) | (3'b110 & {3{(~ld_st_is0)}}); //fpr + + //---------------------------------------------------------------------------------------------------------------------- + assign au_iu_iu4_s2_v = ((indexed | mffgpr) & ld_st_is0) | (bv & (~ld_st_is0)); + assign au_iu_iu4_s2_a6[0:5] = {iu_au_iu4_ucode_ext[2], is0_instr[16:20]}; + //gpr + assign au_iu_iu4_s2_t[0:2] = (3'b000 & {3{ld_st_is0}}) | (3'b110 & {3{(~ld_st_is0)}}); //fpr + + //---------------------------------------------------------------------------------------------------------------------- + assign au_iu_iu4_s3_v = (st_is0 & (~mftgpr) & ld_st_is0) | (cv & (~ld_st_is0)); + assign au_iu_iu4_s3_a6[0:5] = (({iu_au_iu4_ucode_ext[0], is0_instr[06:10]}) & {6{ld_st_is0 & (~(mffgpr | mftgpr))}}) | + (({iu_au_iu4_ucode_ext[2], is0_instr[16:20]}) & {6{ld_st_is0 & ( mffgpr | mftgpr) }}) | + (({iu_au_iu4_ucode_ext[3], is0_instr[21:25]}) & {6{(~ld_st_is0)}}); + //gpr + assign au_iu_iu4_s3_t[0:2] = (3'b000 & {3{mffgpr}}) | (3'b110 & {3{(~mffgpr)}}); //fpr + + //---------------------------------------------------------------------------------------------------------------------- + generate + if (`GPR_POOL_ENC > 6) + begin : gpr_pool + assign au_iu_iu4_t1_a[0:`GPR_POOL_ENC - 7] = 0; + assign au_iu_iu4_t2_a[0:`GPR_POOL_ENC - 7] = 0; + assign au_iu_iu4_t3_a[0:`GPR_POOL_ENC - 7] = 0; + assign au_iu_iu4_s1_a[0:`GPR_POOL_ENC - 7] = 0; + assign au_iu_iu4_s2_a[0:`GPR_POOL_ENC - 7] = 0; + assign au_iu_iu4_s3_a[0:`GPR_POOL_ENC - 7] = 0; + end + endgenerate + assign au_iu_iu4_t1_a[`GPR_POOL_ENC - 6:`GPR_POOL_ENC - 1] = au_iu_iu4_t1_a6[0:5]; + assign au_iu_iu4_t2_a[`GPR_POOL_ENC - 6:`GPR_POOL_ENC - 1] = au_iu_iu4_t2_a6[0:5]; + assign au_iu_iu4_t3_a[`GPR_POOL_ENC - 6:`GPR_POOL_ENC - 1] = au_iu_iu4_t3_a6[0:5]; + assign au_iu_iu4_s1_a[`GPR_POOL_ENC - 6:`GPR_POOL_ENC - 1] = au_iu_iu4_s1_a6[0:5]; + assign au_iu_iu4_s2_a[`GPR_POOL_ENC - 6:`GPR_POOL_ENC - 1] = au_iu_iu4_s2_a6[0:5]; + assign au_iu_iu4_s3_a[`GPR_POOL_ENC - 6:`GPR_POOL_ENC - 1] = au_iu_iu4_s3_a6[0:5]; + + //---------------------------------------------------------------------------------------------------------------------- + assign isLoad = ld_st_is0 & (~st_is0) & (~(mffgpr | mftgpr)); + assign isStore = ld_st_is0 & (st_is0 | mftgpr) & (~mffgpr); + + assign au_iu_iu4_isload = isLoad; + assign au_iu_iu4_isstore = isStore; + + assign au_iu_iu4_ilat[0:2] = (3'b100 & {3{ld_st_is0 & (~st_is0)}}) | (3'b011 & {3{ld_st_is0 & st_is0 & (~mftgpr)}}) | (3'b110 & {3{ld_st_is0 & st_is0 & mftgpr}}) | (3'b110 & {3{(~ld_st_is0)}}); + assign au_iu_iu4_ord = ordered & (~iu_au_iu4_ucode[1]); + assign au_iu_iu4_cord = cordered & (~iu_au_iu4_ucode[1]); + + assign au_iu_iu4_spec = ld_st_is0; + + // To set the ESR bits + assign au_iu_iu4_type_fp = isfu_dec_is0; + assign au_iu_iu4_type_ap = 1'b0; + assign au_iu_iu4_type_spv = 1'b0; + assign au_iu_iu4_type_st = st_is0; + + assign au_iu_iu4_rte_lq = ld_st_is0; + assign au_iu_iu4_rte_sq = isStore; + assign au_iu_iu4_rte_axu0 = isfu_dec_is0 & (~(ld_st_is0 & (~st_is0))) & ~(isStore & iu_au_iu4_ucode[1]); //don't route to axu on a store pressissue + assign au_iu_iu4_rte_axu1 = 1'b0; + + assign au_iu_iu4_async_block = fpscr_mv; + + //---------------------------------------------------------------------------------------------------------------------- + + assign i_dec_so = 1'b0; + assign fu_dec_debug = 0; + + +endmodule diff --git a/dev/verilog/work/iuq_axu_fu_rn.v b/dev/verilog/work/iuq_axu_fu_rn.v new file mode 100755 index 0000000..a52d175 --- /dev/null +++ b/dev/verilog/work/iuq_axu_fu_rn.v @@ -0,0 +1,730 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//* ******************************************************************* +//* +//* TITLE: +//* +//* NAME: iuq_axu_fu_rn.vhdl +//* +//********************************************************************* + +(* block_type="leaf" *) +(* recursive_synthesis="2" *) + +`include "tri_a2o.vh" + +module iuq_axu_fu_rn #( + parameter FPR_POOL = 64, + parameter FPR_UCODE_POOL = 4, + parameter FPSCR_POOL_ENC = 5) + ( + inout vdd, + inout gnd, + input [0:`NCLK_WIDTH-1] nclk, + input pc_iu_func_sl_thold_2, // acts as reset for non-ibm types + input pc_iu_sg_2, + input clkoff_b, + input act_dis, + input tc_ac_ccflush_dc, + input d_mode, + input delay_lclkr, + input mpw1_b, + input mpw2_b, + input func_scan_in, + output func_scan_out, + + //----------------------------- + // Inputs to rename from decode + //----------------------------- + input iu_au_iu5_i0_vld, + input [0:2] iu_au_iu5_i0_ucode, + input iu_au_iu5_i0_rte_lq, + input iu_au_iu5_i0_rte_sq, + input iu_au_iu5_i0_rte_fx0, + input iu_au_iu5_i0_rte_fx1, + input iu_au_iu5_i0_rte_axu0, + input iu_au_iu5_i0_rte_axu1, + input iu_au_iu5_i0_ord, + input iu_au_iu5_i0_cord, + input [0:31] iu_au_iu5_i0_instr, + input [62-`EFF_IFAR_WIDTH:61] iu_au_iu5_i0_ifar, + input [0:9] iu_au_iu5_i0_gshare, + input [0:3] iu_au_iu5_i0_ilat, + input iu_au_iu5_i0_isload, + input iu_au_iu5_i0_t1_v, + input [0:2] iu_au_iu5_i0_t1_t, + input [0:`GPR_POOL_ENC-1] iu_au_iu5_i0_t1_a, + input iu_au_iu5_i0_t2_v, + input [0:2] iu_au_iu5_i0_t2_t, + input [0:`GPR_POOL_ENC-1] iu_au_iu5_i0_t2_a, + input iu_au_iu5_i0_t3_v, + input [0:2] iu_au_iu5_i0_t3_t, + input [0:`GPR_POOL_ENC-1] iu_au_iu5_i0_t3_a, + input iu_au_iu5_i0_s1_v, + input [0:2] iu_au_iu5_i0_s1_t, + input [0:`GPR_POOL_ENC-1] iu_au_iu5_i0_s1_a, + input iu_au_iu5_i0_s2_v, + input [0:2] iu_au_iu5_i0_s2_t, + input [0:`GPR_POOL_ENC-1] iu_au_iu5_i0_s2_a, + input iu_au_iu5_i0_s3_v, + input [0:2] iu_au_iu5_i0_s3_t, + input [0:`GPR_POOL_ENC-1] iu_au_iu5_i0_s3_a, + + input iu_au_iu5_i1_vld, + input [0:2] iu_au_iu5_i1_ucode, + input iu_au_iu5_i1_rte_lq, + input iu_au_iu5_i1_rte_sq, + input iu_au_iu5_i1_rte_fx0, + input iu_au_iu5_i1_rte_fx1, + input iu_au_iu5_i1_rte_axu0, + input iu_au_iu5_i1_rte_axu1, + input iu_au_iu5_i1_ord, + input iu_au_iu5_i1_cord, + input [0:31] iu_au_iu5_i1_instr, + input [62-`EFF_IFAR_WIDTH:61] iu_au_iu5_i1_ifar, + input [0:9] iu_au_iu5_i1_gshare, + input [0:3] iu_au_iu5_i1_ilat, + input iu_au_iu5_i1_isload, + input iu_au_iu5_i1_t1_v, + input [0:2] iu_au_iu5_i1_t1_t, + input [0:`GPR_POOL_ENC-1] iu_au_iu5_i1_t1_a, + input iu_au_iu5_i1_t2_v, + input [0:2] iu_au_iu5_i1_t2_t, + input [0:`GPR_POOL_ENC-1] iu_au_iu5_i1_t2_a, + input iu_au_iu5_i1_t3_v, + input [0:2] iu_au_iu5_i1_t3_t, + input [0:`GPR_POOL_ENC-1] iu_au_iu5_i1_t3_a, + input iu_au_iu5_i1_s1_v, + input [0:2] iu_au_iu5_i1_s1_t, + input [0:`GPR_POOL_ENC-1] iu_au_iu5_i1_s1_a, + input iu_au_iu5_i1_s2_v, + input [0:2] iu_au_iu5_i1_s2_t, + input [0:`GPR_POOL_ENC-1] iu_au_iu5_i1_s2_a, + input iu_au_iu5_i1_s3_v, + input [0:2] iu_au_iu5_i1_s3_t, + input [0:`GPR_POOL_ENC-1] iu_au_iu5_i1_s3_a, + + //----------------------------- + // SPR values + //----------------------------- + input spr_single_issue, + + //----------------------------- + // Stall to decode + //----------------------------- + output au_iu_iu5_stall, + + //---------------------------- + // Completion Interface + //---------------------------- + input cp_rn_i0_axu_exception_val, + input [0:3] cp_rn_i0_axu_exception, + input [0:`ITAG_SIZE_ENC-1] cp_rn_i0_itag, + input cp_rn_i0_t1_v, + input [0:2] cp_rn_i0_t1_t, + input [0:`GPR_POOL_ENC-1] cp_rn_i0_t1_p, + input [0:`GPR_POOL_ENC-1] cp_rn_i0_t1_a, + input cp_rn_i0_t2_v, + input [0:2] cp_rn_i0_t2_t, + input [0:`GPR_POOL_ENC-1] cp_rn_i0_t2_p, + input [0:`GPR_POOL_ENC-1] cp_rn_i0_t2_a, + input cp_rn_i0_t3_v, + input [0:2] cp_rn_i0_t3_t, + input [0:`GPR_POOL_ENC-1] cp_rn_i0_t3_p, + input [0:`GPR_POOL_ENC-1] cp_rn_i0_t3_a, + + input cp_rn_i1_axu_exception_val, + input [0:3] cp_rn_i1_axu_exception, + input [0:`ITAG_SIZE_ENC-1] cp_rn_i1_itag, + input cp_rn_i1_t1_v, + input [0:2] cp_rn_i1_t1_t, + input [0:`GPR_POOL_ENC-1] cp_rn_i1_t1_p, + input [0:`GPR_POOL_ENC-1] cp_rn_i1_t1_a, + input cp_rn_i1_t2_v, + input [0:2] cp_rn_i1_t2_t, + input [0:`GPR_POOL_ENC-1] cp_rn_i1_t2_p, + input [0:`GPR_POOL_ENC-1] cp_rn_i1_t2_a, + input cp_rn_i1_t3_v, + input [0:2] cp_rn_i1_t3_t, + input [0:`GPR_POOL_ENC-1] cp_rn_i1_t3_p, + input [0:`GPR_POOL_ENC-1] cp_rn_i1_t3_a, + + input cp_flush, + input br_iu_redirect, + + //---------------------------------------------------------------- + // Interface to Rename + //---------------------------------------------------------------- + input iu_au_iu5_send_ok, + input [0:`ITAG_SIZE_ENC-1] iu_au_iu5_next_itag_i0, + input [0:`ITAG_SIZE_ENC-1] iu_au_iu5_next_itag_i1, + output au_iu_iu5_axu0_send_ok, + output au_iu_iu5_axu1_send_ok, + + output [0:`GPR_POOL_ENC-1] au_iu_iu5_i0_t1_p, + output [0:`GPR_POOL_ENC-1] au_iu_iu5_i0_t2_p, + output [0:`GPR_POOL_ENC-1] au_iu_iu5_i0_t3_p, + output [0:`GPR_POOL_ENC-1] au_iu_iu5_i0_s1_p, + output [0:`GPR_POOL_ENC-1] au_iu_iu5_i0_s2_p, + output [0:`GPR_POOL_ENC-1] au_iu_iu5_i0_s3_p, + + output [0:`ITAG_SIZE_ENC-1] au_iu_iu5_i0_s1_itag, + output [0:`ITAG_SIZE_ENC-1] au_iu_iu5_i0_s2_itag, + output [0:`ITAG_SIZE_ENC-1] au_iu_iu5_i0_s3_itag, + + output [0:`GPR_POOL_ENC-1] au_iu_iu5_i1_t1_p, + output [0:`GPR_POOL_ENC-1] au_iu_iu5_i1_t2_p, + output [0:`GPR_POOL_ENC-1] au_iu_iu5_i1_t3_p, + output [0:`GPR_POOL_ENC-1] au_iu_iu5_i1_s1_p, + output [0:`GPR_POOL_ENC-1] au_iu_iu5_i1_s2_p, + output [0:`GPR_POOL_ENC-1] au_iu_iu5_i1_s3_p, + output au_iu_iu5_i1_s1_dep_hit, + output au_iu_iu5_i1_s2_dep_hit, + output au_iu_iu5_i1_s3_dep_hit, + + output [0:`ITAG_SIZE_ENC-1] au_iu_iu5_i1_s1_itag, + output [0:`ITAG_SIZE_ENC-1] au_iu_iu5_i1_s2_itag, + + output [0:`ITAG_SIZE_ENC-1] au_iu_iu5_i1_s3_itag + ); + + parameter cp_flush_offset = 0; + parameter br_iu_hold_offset = cp_flush_offset + 1; + parameter scan_right = br_iu_hold_offset + 1 - 1; + + // scan + wire [0:scan_right] siv; + wire [0:scan_right] sov; + wire [0:1] map_siv; + wire [0:1] map_sov; + + wire tidn; + wire tiup; + + // Latch to delay the flush signal + wire cp_flush_d; + wire cp_flush_l2; + wire br_iu_hold_d; + wire br_iu_hold_l2; + + // Source lookups from pools note may not be valid if source if type not of the right type + wire [0:`GPR_POOL_ENC-1] fpr_iu5_i0_src1_p; + wire [0:`GPR_POOL_ENC-1] fpr_iu5_i0_src2_p; + wire [0:`GPR_POOL_ENC-1] fpr_iu5_i0_src3_p; + wire [0:`GPR_POOL_ENC-1] fpr_iu5_i1_src1_p; + wire [0:`GPR_POOL_ENC-1] fpr_iu5_i1_src2_p; + wire [0:`GPR_POOL_ENC-1] fpr_iu5_i1_src3_p; + + // Source lookups from pools note may not be valid if source if type not of the right type + wire [0:`ITAG_SIZE_ENC-1] fpr_iu5_i0_src1_itag; + wire [0:`ITAG_SIZE_ENC-1] fpr_iu5_i0_src2_itag; + wire [0:`ITAG_SIZE_ENC-1] fpr_iu5_i0_src3_itag; + wire [0:`ITAG_SIZE_ENC-1] fpr_iu5_i1_src1_itag; + wire [0:`ITAG_SIZE_ENC-1] fpr_iu5_i1_src2_itag; + wire [0:`ITAG_SIZE_ENC-1] fpr_iu5_i1_src3_itag; + + // I1 dependency hit vs I0 for each source this is used by RV + wire fpr_s1_dep_hit; + wire fpr_s2_dep_hit; + wire fpr_s3_dep_hit; + + // Free from completion to the fpr pool + wire fpr_cp_i0_wr_v; + wire [0:`GPR_POOL_ENC-1] fpr_cp_i0_wr_a; + wire [0:`GPR_POOL_ENC-1] fpr_cp_i0_wr_p; + wire [0:`ITAG_SIZE_ENC-1] fpr_cp_i0_wr_itag; + wire fpr_cp_i1_wr_v; + wire [0:`GPR_POOL_ENC-1] fpr_cp_i1_wr_a; + wire [0:`GPR_POOL_ENC-1] fpr_cp_i1_wr_p; + wire [0:`ITAG_SIZE_ENC-1] fpr_cp_i1_wr_itag; + + wire fpr_spec_i0_wr_v; + wire fpr_spec_i0_wr_v_fast; + wire [0:`GPR_POOL_ENC-1] fpr_spec_i0_wr_a; + wire [0:`GPR_POOL_ENC-1] fpr_spec_i0_wr_p; + wire [0:`ITAG_SIZE_ENC-1] fpr_spec_i0_wr_itag; + wire fpr_spec_i1_wr_v; + wire fpr_spec_i1_wr_v_fast; + wire [0:`GPR_POOL_ENC-1] fpr_spec_i1_wr_a; + wire [0:`GPR_POOL_ENC-1] fpr_spec_i1_wr_p; + wire [0:`ITAG_SIZE_ENC-1] fpr_spec_i1_wr_itag; + + wire next_fpr_0_v; + wire [0:`GPR_POOL_ENC-1] next_fpr_0; + wire next_fpr_1_v; + wire [0:`GPR_POOL_ENC-1] next_fpr_1; + + wire fpscr_cp_i0_wr_v; + wire [0:FPSCR_POOL_ENC-1] fpscr_cp_i0_wr_a; + wire [0:FPSCR_POOL_ENC-1] fpscr_cp_i0_wr_p; + wire [0:`ITAG_SIZE_ENC-1] fpscr_cp_i0_wr_itag; + wire fpscr_cp_i1_wr_v; + wire [0:FPSCR_POOL_ENC-1] fpscr_cp_i1_wr_a; + wire [0:FPSCR_POOL_ENC-1] fpscr_cp_i1_wr_p; + wire [0:`ITAG_SIZE_ENC-1] fpscr_cp_i1_wr_itag; + + wire fpscr_spec_i0_wr_v; + wire fpscr_spec_i0_wr_v_fast; + wire [0:FPSCR_POOL_ENC-1] fpscr_spec_i0_wr_a; + wire [0:FPSCR_POOL_ENC-1] fpscr_spec_i0_wr_p; + wire [0:`ITAG_SIZE_ENC-1] fpscr_spec_i0_wr_itag; + wire fpscr_spec_i1_wr_v; + wire fpscr_spec_i1_wr_v_fast; + wire [0:FPSCR_POOL_ENC-1] fpscr_spec_i1_wr_a; + wire [0:FPSCR_POOL_ENC-1] fpscr_spec_i1_wr_p; + wire [0:`ITAG_SIZE_ENC-1] fpscr_spec_i1_wr_itag; + + wire next_fpscr_0_v; + wire [0:FPSCR_POOL_ENC-1] next_fpscr_0; + wire next_fpscr_1_v; + wire [0:FPSCR_POOL_ENC-1] next_fpscr_1; + + wire [0:1] fpr_send_cnt; + wire [0:1] fpscr_send_cnt; + + wire fpr_send_ok; + wire fpscr_send_ok; + + wire send_instructions; + + // Pervasive + wire pc_iu_func_sl_thold_1; + wire pc_iu_func_sl_thold_0; + wire pc_iu_func_sl_thold_0_b; + wire pc_iu_sg_1; + wire pc_iu_sg_0; + wire force_t; + + // This signal compares credits left and issues LQ/FX instructions to FX when set + wire dual_issue_use_fx; + //-------------------------------------------------------------- + + assign tidn = 1'b0; + assign tiup = 1'b1; + + assign cp_flush_d = cp_flush; + assign br_iu_hold_d = (br_iu_redirect | br_iu_hold_l2) & (~(cp_flush_l2)); + + assign fpr_send_cnt = ({(iu_au_iu5_i0_t2_v & (iu_au_iu5_i0_t2_t == `axu0_t)), (iu_au_iu5_i1_t2_v & (iu_au_iu5_i1_t2_t == `axu0_t))}); + + assign fpscr_send_cnt = ({(iu_au_iu5_i0_t1_v & (iu_au_iu5_i0_t1_t == `axu1_t)), (iu_au_iu5_i1_t1_v & (iu_au_iu5_i1_t1_t == `axu1_t))}); + + assign fpr_send_ok = (fpr_send_cnt == 2'b00) | ((fpr_send_cnt[0] ^ fpr_send_cnt[1]) & next_fpr_0_v) | (next_fpr_0_v & next_fpr_1_v); + + assign fpscr_send_ok = (fpscr_send_cnt == 2'b00) | ((fpscr_send_cnt[0] ^ fpscr_send_cnt[1]) & next_fpscr_0_v) | (next_fpscr_0_v & next_fpscr_1_v); + + + assign au_iu_iu5_axu0_send_ok = fpr_send_ok & fpscr_send_ok; + assign au_iu_iu5_axu1_send_ok = 1'b1; + + //todo... frn may not send instr due to other credits... + assign send_instructions = (fpr_send_ok & fpscr_send_ok & iu_au_iu5_send_ok & iu_au_iu5_i0_vld) & (~(br_iu_hold_l2)); + + assign dual_issue_use_fx = 1'b0; + + //----------------------------------------------------------------------- + //-- Outputs + //----------------------------------------------------------------------- + + assign au_iu_iu5_stall = (~(fpr_send_ok & fpscr_send_ok)); + + assign au_iu_iu5_i0_t1_p[0:`GPR_POOL_ENC - 1] = {1'b0,next_fpscr_0}; + assign au_iu_iu5_i0_t2_p = next_fpr_0; + assign au_iu_iu5_i0_t3_p = 0; + + assign au_iu_iu5_i0_s1_p = fpr_iu5_i0_src1_p; + assign au_iu_iu5_i0_s2_p = fpr_iu5_i0_src2_p; + assign au_iu_iu5_i0_s3_p = fpr_iu5_i0_src3_p; + + assign au_iu_iu5_i0_s1_itag = fpr_iu5_i0_src1_itag; + assign au_iu_iu5_i0_s2_itag = fpr_iu5_i0_src2_itag; + assign au_iu_iu5_i0_s3_itag = fpr_iu5_i0_src3_itag; + + assign au_iu_iu5_i1_t1_p[0:`GPR_POOL_ENC - 1] = {1'b0,next_fpscr_1}; + assign au_iu_iu5_i1_t2_p = next_fpr_1; + assign au_iu_iu5_i1_t3_p = 0; + + assign au_iu_iu5_i1_s1_p = fpr_iu5_i1_src1_p; + assign au_iu_iu5_i1_s2_p = fpr_iu5_i1_src2_p; + assign au_iu_iu5_i1_s3_p = fpr_iu5_i1_src3_p; + + assign au_iu_iu5_i1_s1_itag = fpr_iu5_i1_src1_itag; + assign au_iu_iu5_i1_s2_itag = fpr_iu5_i1_src2_itag; + assign au_iu_iu5_i1_s3_itag = fpr_iu5_i1_src3_itag; + + assign au_iu_iu5_i1_s1_dep_hit = fpr_s1_dep_hit & (iu_au_iu5_i1_s1_t == `axu0_t); + assign au_iu_iu5_i1_s2_dep_hit = fpr_s2_dep_hit & (iu_au_iu5_i1_s2_t == `axu0_t); + assign au_iu_iu5_i1_s3_dep_hit = fpr_s3_dep_hit & (iu_au_iu5_i1_s3_t == `axu0_t); + + //----------------------------------------------------------------------- + //-- FPR Renamer + //----------------------------------------------------------------------- + // Gate the FPR write enable by killing its completion report to the rn mapper + + assign fpr_cp_i0_wr_v = cp_rn_i0_t2_v & (cp_rn_i0_t2_t == `axu0_t) & (~(cp_rn_i0_axu_exception[0:3] == 4'b0101)); + assign fpr_cp_i0_wr_a = cp_rn_i0_t2_a; + assign fpr_cp_i0_wr_p = cp_rn_i0_t2_p; + assign fpr_cp_i0_wr_itag = cp_rn_i0_itag; + assign fpr_cp_i1_wr_v = cp_rn_i1_t2_v & (cp_rn_i1_t2_t == `axu0_t) & (~(cp_rn_i1_axu_exception[0:3] == 4'b0101)); + assign fpr_cp_i1_wr_a = cp_rn_i1_t2_a; + assign fpr_cp_i1_wr_p = cp_rn_i1_t2_p; + assign fpr_cp_i1_wr_itag = cp_rn_i1_itag; + + assign fpr_spec_i0_wr_v = send_instructions & (~(fpr_send_cnt[0:1] == 2'b00)); + assign fpr_spec_i0_wr_v_fast = (~(fpr_send_cnt[0:1] == 2'b00)); + assign fpr_spec_i0_wr_a = (fpr_send_cnt[0] ? iu_au_iu5_i0_t2_a : 0) | (((~(fpr_send_cnt[0])) & fpr_send_cnt[1]) ? iu_au_iu5_i1_t2_a : 0); + assign fpr_spec_i0_wr_p = next_fpr_0; + assign fpr_spec_i0_wr_itag = (fpr_send_cnt[0] ? iu_au_iu5_next_itag_i0 : 0) | (((~(fpr_send_cnt[0])) & fpr_send_cnt[1]) ? iu_au_iu5_next_itag_i1 : 0); + assign fpr_spec_i1_wr_v = send_instructions & (fpr_send_cnt[0:1] == 2'b11); + assign fpr_spec_i1_wr_v_fast = (fpr_send_cnt[0:1] == 2'b11); + assign fpr_spec_i1_wr_a = iu_au_iu5_i1_t2_a; + assign fpr_spec_i1_wr_p = next_fpr_1; + assign fpr_spec_i1_wr_itag = iu_au_iu5_next_itag_i1; + + assign fpr_s1_dep_hit = fpr_spec_i0_wr_v_fast & fpr_send_cnt[0] & (fpr_spec_i0_wr_a == iu_au_iu5_i1_s1_a); + assign fpr_s2_dep_hit = fpr_spec_i0_wr_v_fast & fpr_send_cnt[0] & (fpr_spec_i0_wr_a == iu_au_iu5_i1_s2_a); + assign fpr_s3_dep_hit = fpr_spec_i0_wr_v_fast & fpr_send_cnt[0] & (fpr_spec_i0_wr_a == iu_au_iu5_i1_s3_a); + + iuq_rn_map #(.ARCHITECTED_REGISTER_DEPTH((32 + FPR_UCODE_POOL)), .REGISTER_RENAME_DEPTH(FPR_POOL), .STORAGE_WIDTH(`GPR_POOL_ENC)) fpr_rn_map( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .pc_iu_func_sl_thold_0_b(pc_iu_func_sl_thold_0_b), + .pc_iu_sg_0(pc_iu_sg_0), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .func_scan_in(map_siv[0]), + .func_scan_out(map_sov[0]), + + .take_a(fpr_spec_i0_wr_v), + .take_b(fpr_spec_i1_wr_v), + .next_reg_a_val(next_fpr_0_v), + .next_reg_a(next_fpr_0), + .next_reg_b_val(next_fpr_1_v), + .next_reg_b(next_fpr_1), + + .src1_a(iu_au_iu5_i0_s1_a), //fdec_frn_iu5_i0_s1_a, + .src1_p(fpr_iu5_i0_src1_p), + .src1_itag(fpr_iu5_i0_src1_itag), + .src2_a(iu_au_iu5_i0_s2_a), //fdec_frn_iu5_i0_s2_a, + .src2_p(fpr_iu5_i0_src2_p), + .src2_itag(fpr_iu5_i0_src2_itag), + .src3_a(iu_au_iu5_i0_s3_a), //fdec_frn_iu5_i0_s3_a, + .src3_p(fpr_iu5_i0_src3_p), + .src3_itag(fpr_iu5_i0_src3_itag), + .src4_a(iu_au_iu5_i1_s1_a), //fdec_frn_iu5_i1_s1_a, + .src4_p(fpr_iu5_i1_src1_p), + .src4_itag(fpr_iu5_i1_src1_itag), + .src5_a(iu_au_iu5_i1_s2_a), //fdec_frn_iu5_i1_s2_a, + .src5_p(fpr_iu5_i1_src2_p), + .src5_itag(fpr_iu5_i1_src2_itag), + .src6_a(iu_au_iu5_i1_s3_a), //fdec_frn_iu5_i1_s3_a, + .src6_p(fpr_iu5_i1_src3_p), + .src6_itag(fpr_iu5_i1_src3_itag), + + .comp_0_wr_val(fpr_cp_i0_wr_v), + .comp_0_wr_arc(fpr_cp_i0_wr_a), + .comp_0_wr_rename(fpr_cp_i0_wr_p), + .comp_0_wr_itag(fpr_cp_i0_wr_itag), + + .comp_1_wr_val(fpr_cp_i1_wr_v), + .comp_1_wr_arc(fpr_cp_i1_wr_a), + .comp_1_wr_rename(fpr_cp_i1_wr_p), + .comp_1_wr_itag(fpr_cp_i1_wr_itag), + + .spec_0_wr_val(fpr_spec_i0_wr_v), + .spec_0_wr_val_fast(fpr_spec_i0_wr_v_fast), + .spec_0_wr_arc(fpr_spec_i0_wr_a), + .spec_0_wr_rename(fpr_spec_i0_wr_p), + .spec_0_wr_itag(fpr_spec_i0_wr_itag), + + .spec_1_dep_hit_s1(fpr_s1_dep_hit), + .spec_1_dep_hit_s2(fpr_s2_dep_hit), + .spec_1_dep_hit_s3(fpr_s3_dep_hit), + .spec_1_wr_val(fpr_spec_i1_wr_v), + .spec_1_wr_val_fast(fpr_spec_i1_wr_v_fast), + .spec_1_wr_arc(fpr_spec_i1_wr_a), + .spec_1_wr_rename(fpr_spec_i1_wr_p), + .spec_1_wr_itag(fpr_spec_i1_wr_itag), + + .flush_map(cp_flush_l2) + ); + + //----------------------------------------------------------------------- + //-- FPSCR Renamer + //----------------------------------------------------------------------- + assign fpscr_cp_i0_wr_v = cp_rn_i0_t1_v & (cp_rn_i0_t1_t == `axu1_t); + assign fpscr_cp_i0_wr_a = cp_rn_i0_t1_a[1:`GPR_POOL_ENC - 1]; + assign fpscr_cp_i0_wr_p = cp_rn_i0_t1_p[1:`GPR_POOL_ENC - 1]; + assign fpscr_cp_i0_wr_itag = cp_rn_i0_itag; + assign fpscr_cp_i1_wr_v = cp_rn_i1_t1_v & (cp_rn_i1_t1_t == `axu1_t); + assign fpscr_cp_i1_wr_a = cp_rn_i1_t1_a[1:`GPR_POOL_ENC - 1]; + assign fpscr_cp_i1_wr_p = cp_rn_i1_t1_p[1:`GPR_POOL_ENC - 1]; + assign fpscr_cp_i1_wr_itag = cp_rn_i1_itag; + + assign fpscr_spec_i0_wr_v = send_instructions & (~(fpscr_send_cnt[0:1] == 2'b00)); + assign fpscr_spec_i0_wr_v_fast = (~(fpscr_send_cnt[0:1] == 2'b00)); + assign fpscr_spec_i0_wr_a = (fpscr_send_cnt[0] ? iu_au_iu5_i0_t1_a[1:`GPR_POOL_ENC - 1] : 0) | (((~(fpscr_send_cnt[0])) & fpscr_send_cnt[1]) ? iu_au_iu5_i1_t1_a[1:`GPR_POOL_ENC - 1] : 0); + assign fpscr_spec_i0_wr_p = next_fpscr_0; + assign fpscr_spec_i0_wr_itag = (fpscr_send_cnt[0] ? iu_au_iu5_next_itag_i0 : 0) | (((~(fpscr_send_cnt[0])) & fpscr_send_cnt[1]) ? iu_au_iu5_next_itag_i1 : 0); + assign fpscr_spec_i1_wr_v = send_instructions & (fpscr_send_cnt[0:1] == 2'b11); + assign fpscr_spec_i1_wr_v_fast = (fpscr_send_cnt[0:1] == 2'b11); + assign fpscr_spec_i1_wr_a = iu_au_iu5_i1_t1_a[1:`GPR_POOL_ENC - 1]; + assign fpscr_spec_i1_wr_p = next_fpscr_1; + assign fpscr_spec_i1_wr_itag = iu_au_iu5_next_itag_i1; + + +`ifndef THREADS1 + + // 24 entries per thread for dual thread + iuq_rn_map #(.ARCHITECTED_REGISTER_DEPTH(1), .REGISTER_RENAME_DEPTH(24), .STORAGE_WIDTH(5)) fpscr_rn_map( //`GPR_POOL_ENC) + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .pc_iu_func_sl_thold_0_b(pc_iu_func_sl_thold_0_b), + .pc_iu_sg_0(pc_iu_sg_0), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .func_scan_in(map_siv[1]), + .func_scan_out(map_sov[1]), + + .take_a(fpscr_spec_i0_wr_v), + .take_b(fpscr_spec_i1_wr_v), + .next_reg_a_val(next_fpscr_0_v), + .next_reg_a(next_fpscr_0), + .next_reg_b_val(next_fpscr_1_v), + .next_reg_b(next_fpscr_1), + + .src1_a(iu_au_iu5_i0_s1_a[1:`GPR_POOL_ENC - 1]), + .src1_p(), + .src1_itag(), + .src2_a(iu_au_iu5_i0_s2_a[1:`GPR_POOL_ENC - 1]), + .src2_p(), + .src2_itag(), + .src3_a(iu_au_iu5_i0_s3_a[1:`GPR_POOL_ENC - 1]), + .src3_p(), + .src3_itag(), + .src4_a(iu_au_iu5_i1_s1_a[1:`GPR_POOL_ENC - 1]), + .src4_p(), + .src4_itag(), + .src5_a(iu_au_iu5_i1_s2_a[1:`GPR_POOL_ENC - 1]), + .src5_p(), + .src5_itag(), + .src6_a(iu_au_iu5_i1_s3_a[1:`GPR_POOL_ENC - 1]), + .src6_p(), + .src6_itag(), + + .comp_0_wr_val(fpscr_cp_i0_wr_v), + .comp_0_wr_arc(fpscr_cp_i0_wr_a), + .comp_0_wr_rename(fpscr_cp_i0_wr_p), + .comp_0_wr_itag(fpscr_cp_i0_wr_itag), + + .comp_1_wr_val(fpscr_cp_i1_wr_v), + .comp_1_wr_arc(fpscr_cp_i1_wr_a), + .comp_1_wr_rename(fpscr_cp_i1_wr_p), + .comp_1_wr_itag(fpscr_cp_i1_wr_itag), + + .spec_0_wr_val(fpscr_spec_i0_wr_v), + .spec_0_wr_val_fast(fpscr_spec_i0_wr_v_fast), + .spec_0_wr_arc(fpscr_spec_i0_wr_a), + .spec_0_wr_rename(fpscr_spec_i0_wr_p), + .spec_0_wr_itag(fpscr_spec_i0_wr_itag), + + .spec_1_dep_hit_s1(gnd), + .spec_1_dep_hit_s2(gnd), + .spec_1_dep_hit_s3(gnd), + .spec_1_wr_val(fpscr_spec_i1_wr_v), + .spec_1_wr_val_fast(fpscr_spec_i1_wr_v_fast), + .spec_1_wr_arc(fpscr_spec_i1_wr_a), + .spec_1_wr_rename(fpscr_spec_i1_wr_p), + .spec_1_wr_itag(fpscr_spec_i1_wr_itag), + + .flush_map(cp_flush_l2) + ); + + + `else + // 32 if single thread + iuq_rn_map #(.ARCHITECTED_REGISTER_DEPTH(1), .REGISTER_RENAME_DEPTH(32), .STORAGE_WIDTH(5)) fpscr_rn_map( //`GPR_POOL_ENC) + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .pc_iu_func_sl_thold_0_b(pc_iu_func_sl_thold_0_b), + .pc_iu_sg_0(pc_iu_sg_0), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .func_scan_in(map_siv[1]), + .func_scan_out(map_sov[1]), + + .take_a(fpscr_spec_i0_wr_v), + .take_b(fpscr_spec_i1_wr_v), + .next_reg_a_val(next_fpscr_0_v), + .next_reg_a(next_fpscr_0), + .next_reg_b_val(next_fpscr_1_v), + .next_reg_b(next_fpscr_1), + + .src1_a(iu_au_iu5_i0_s1_a[1:`GPR_POOL_ENC - 1]), + .src1_p(), + .src1_itag(), + .src2_a(iu_au_iu5_i0_s2_a[1:`GPR_POOL_ENC - 1]), + .src2_p(), + .src2_itag(), + .src3_a(iu_au_iu5_i0_s3_a[1:`GPR_POOL_ENC - 1]), + .src3_p(), + .src3_itag(), + .src4_a(iu_au_iu5_i1_s1_a[1:`GPR_POOL_ENC - 1]), + .src4_p(), + .src4_itag(), + .src5_a(iu_au_iu5_i1_s2_a[1:`GPR_POOL_ENC - 1]), + .src5_p(), + .src5_itag(), + .src6_a(iu_au_iu5_i1_s3_a[1:`GPR_POOL_ENC - 1]), + .src6_p(), + .src6_itag(), + + .comp_0_wr_val(fpscr_cp_i0_wr_v), + .comp_0_wr_arc(fpscr_cp_i0_wr_a), + .comp_0_wr_rename(fpscr_cp_i0_wr_p), + .comp_0_wr_itag(fpscr_cp_i0_wr_itag), + + .comp_1_wr_val(fpscr_cp_i1_wr_v), + .comp_1_wr_arc(fpscr_cp_i1_wr_a), + .comp_1_wr_rename(fpscr_cp_i1_wr_p), + .comp_1_wr_itag(fpscr_cp_i1_wr_itag), + + .spec_0_wr_val(fpscr_spec_i0_wr_v), + .spec_0_wr_val_fast(fpscr_spec_i0_wr_v_fast), + .spec_0_wr_arc(fpscr_spec_i0_wr_a), + .spec_0_wr_rename(fpscr_spec_i0_wr_p), + .spec_0_wr_itag(fpscr_spec_i0_wr_itag), + + .spec_1_dep_hit_s1(gnd), + .spec_1_dep_hit_s2(gnd), + .spec_1_dep_hit_s3(gnd), + .spec_1_wr_val(fpscr_spec_i1_wr_v), + .spec_1_wr_val_fast(fpscr_spec_i1_wr_v_fast), + .spec_1_wr_arc(fpscr_spec_i1_wr_a), + .spec_1_wr_rename(fpscr_spec_i1_wr_p), + .spec_1_wr_itag(fpscr_spec_i1_wr_itag), + + .flush_map(cp_flush_l2) + ); + + `endif + + + + tri_rlmlatch_p #(.INIT(0)) cp_flush_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[cp_flush_offset]), + .scout(sov[cp_flush_offset]), + .din(cp_flush_d), + .dout(cp_flush_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) br_iu_hold_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[br_iu_hold_offset]), + .scout(sov[br_iu_hold_offset]), + .din(br_iu_hold_d), + .dout(br_iu_hold_l2) + ); + + //----------------------------------------------- + // pervasive + //----------------------------------------------- + + + tri_plat #(.WIDTH(2)) perv_2to1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + .din({pc_iu_func_sl_thold_2,pc_iu_sg_2}), + .q({pc_iu_func_sl_thold_1,pc_iu_sg_1}) + ); + + + tri_plat #(.WIDTH(2)) perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + .din({pc_iu_func_sl_thold_1,pc_iu_sg_1}), + .q({pc_iu_func_sl_thold_0,pc_iu_sg_0}) + ); + + + tri_lcbor perv_lcbor( + .clkoff_b(clkoff_b), + .thold(pc_iu_func_sl_thold_0), + .sg(pc_iu_sg_0), + .act_dis(act_dis), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b) + ); + + assign map_siv = {func_scan_in, map_sov[0]}; + assign siv = {sov[1:scan_right], map_sov[1]}; + assign func_scan_out = sov[0]; + +endmodule + diff --git a/dev/verilog/work/iuq_bd.v b/dev/verilog/work/iuq_bd.v new file mode 100755 index 0000000..767d373 --- /dev/null +++ b/dev/verilog/work/iuq_bd.v @@ -0,0 +1,232 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// VHDL 1076 Macro Expander C version 07/11/00 +// job was run on Fri Mar 25 11:38:23 2011 + +//******************************************************************** +//* +//* TITLE: IU Branch Decode +//* +//* NAME: iuq_bd.vhdl +//* +//********************************************************************* + + +module iuq_bd( + instruction, + instruction_next, + branch_decode, + bp_bc_en, + bp_bclr_en, + bp_bcctr_en, + bp_sw_en +); + //parameter `GPR_WIDTH = 64; +`include "tri_a2o.vh" + + (* analysis_not_referenced="<12:20>true" *) + input [0:31] instruction; + (* analysis_not_referenced="<6:7>,<9:10>,<14:20>,<31>true" *) + input [0:31] instruction_next; + output [0:3] branch_decode; + + input bp_bc_en; + input bp_bclr_en; + input bp_bcctr_en; + input bp_sw_en; + + wire [1:12] MICROCODE_PT; + wire core64; + wire to_uc; + //architecture iuq_bd of iuq_bd is + wire b; + wire bc; + wire bclr; + wire bcctr; + wire bctar; + wire br_val; + wire [0:4] bo; + wire hint; + wire hint_val; + wire cmpi; + wire cmpli; + wire cmp; + wire cmpl; + wire [0:2] bf; + wire next_bc; + wire next_bclr; + wire next_bcctr; + wire next_bctar; + wire [0:2] next_bi; + wire next_ctr; + wire fuse_val; + //@@ START OF EXECUTABLE CODE FOR IUQ_BD + + //begin + assign b = instruction[0:5] == 6'b010010; + assign bc = bp_bc_en & instruction[0:5] == 6'b010000; + assign bclr = bp_bclr_en & instruction[0:5] == 6'b010011 & instruction[21:30] == 10'b0000010000; + assign bcctr = bp_bcctr_en & instruction[0:5] == 6'b010011 & instruction[21:30] == 10'b1000010000; + assign bctar = bp_bcctr_en & instruction[0:5] == 6'b010011 & instruction[21:30] == 10'b1000110000; + assign br_val = b | bc | bclr | bcctr | bctar; + assign bo[0:4] = instruction[6:10]; + assign hint_val = (bo[0] & bo[2]) | (bp_sw_en & ((bo[0] == 1'b0 & bo[2] == 1'b1 & bo[3] == 1'b1) | (bo[0] == 1'b1 & bo[2] == 1'b0 & bo[1] == 1'b1))); + assign hint = (bo[0] & bo[2]) | bo[4]; + assign branch_decode[0:3] = {br_val, (b | to_uc), ((br_val & hint_val) | fuse_val), hint}; + //------------------ + // fusion predecode + //------------------ + assign cmpi = instruction[0:5] == 6'b001011; + assign cmpli = instruction[0:5] == 6'b001010; + assign cmp = instruction[0:5] == 6'b011111 & instruction[21:30] == 10'b0000000000; + assign cmpl = instruction[0:5] == 6'b011111 & instruction[21:30] == 10'b0000100000; + assign bf[0:2] = instruction[6:8]; + assign next_bc = instruction_next[0:5] == 6'b010000; + assign next_bclr = instruction_next[0:5] == 6'b010011 & instruction_next[21:30] == 10'b0000010000; + assign next_bcctr = instruction_next[0:5] == 6'b010011 & instruction_next[21:30] == 10'b1000010000; + assign next_bctar = instruction_next[0:5] == 6'b010011 & instruction_next[21:30] == 10'b1000110000; + assign next_bi[0:2] = instruction_next[11:13]; + assign next_ctr = instruction_next[8] == 1'b0; + //remove update LR cases for now + assign fuse_val = (bf[0:2] == next_bi[0:2]) & (((cmpi | cmpli) & (next_bc | next_bcctr | ((next_bclr | next_bctar) & (~next_ctr)))) | ((cmp | cmpl) & (((next_bc) & (~next_ctr))))); + //------------------ + // ucode predecode + //------------------ + //64-bit core + generate + if (`GPR_WIDTH == 64) + begin : c64 + assign core64 = 1'b1; + end + endgenerate + //32-bit core + generate + if (`GPR_WIDTH == 32) + begin : c32 + assign core64 = 1'b0; + end + endgenerate + +/* +//table_start +?TABLE microcode LISTING(final) OPTIMIZE PARMS(ON-SET,DC-SET); +*INPUTS*=====================*OUTPUTS*==* +| | | +| core64 | | +| | | | +| | instruction | to_uc | +| | | instruction | | | +| | | | instruction | | | +| | | | | | | | +| | | 1 22222222233 | | | +| | 012345 1 12345678901 | | | +*TYPE*=======================+==========+ +| S PPPPPP P PPPPPPPPPPP | S | +*TERMS*======================+==========+ +| . 100011 . ........... | 1 | lbzu +| . 011111 . 0001110111. | 1 | lbzux +| 1 111010 . .........01 | 1 | ldu +| 1 011111 . 0000110101. | 1 | ldux +| . 101011 . ........... | 1 | lhau +| . 011111 . 0101110111. | 1 | lhaux +| . 101001 . ........... | 1 | lhzu +| . 011111 . 0100110111. | 1 | lhzux +| . 101110 . ........... | 1 | lmw +| . 011111 . 1001010101. | 1 | lswi +| . 011111 . 1000010101. | 1 | lswx +| 1 011111 . 0101110101. | 1 | lwaux +| . 100001 . ........... | 1 | lwzu +| . 011111 . 0000110111. | 1 | lwzux +| . 110001 . ........... | 1 | lfsu +| . 011111 . 1000110111. | 1 | lfsux +| . 110011 . ........... | 1 | lfdu +| . 011111 . 1001110111. | 1 | lfdux +| . 011111 . 1000000000. | 1 | mcrxr +| . 011111 0 0000010011. | 1 | mfcr +| . 011111 0 0010010000. | 1 | mtcrf +| . 101111 . ........... | 1 | stmw +| . 011111 . 1011010101. | 1 | stswi +| . 011111 . 1010010101. | 1 | stswx +*END*========================+==========+ +?TABLE END microcode ; +//table_end +*/ + +//assign_start + // + // Final Table Listing + // *INPUTS*=====================*OUTPUTS*==* + // | | | + // | core64 | | + // | | | | + // | | instruction | to_uc | + // | | | instruction | | | + // | | | | instruction | | | + // | | | | | | | | + // | | | 1 22222222233 | | | + // | | 012345 1 12345678901 | | | + // *TYPE*=======================+==========+ + // | S PPPPPP P PPPPPPPPPPP | S | + // *POLARITY*------------------>| + | + // *PHASE*--------------------->| T | + // *TERMS*======================+==========+ + // 1 | - 011111 0 0010010000- | 1 | + // 2 | - 011111 - 1000000000- | 1 | + // 3 | 1 011111 - 01011101-1- | 1 | + // 4 | - 011111 0 0000010011- | 1 | + // 5 | 1 011111 - 00001101-1- | 1 | + // 6 | - 011111 - 10--010101- | 1 | + // 7 | - 011111 - 0-0-110111- | 1 | + // 8 | - 011111 - -00-110111- | 1 | + // 9 | 1 111010 - ---------01 | 1 | + // 10 | - 1-00-1 - ----------- | 1 | + // 11 | - 10-0-1 - ----------- | 1 | + // 12 | - 10111- - ----------- | 1 | + // *=======================================* + // + // Table MICROCODE Signal Assignments for Product Terms + assign MICROCODE_PT[1] = (({instruction[0], instruction[1], instruction[2], instruction[3], instruction[4], instruction[5], instruction[11], instruction[21], instruction[22], instruction[23], instruction[24], instruction[25], instruction[26], instruction[27], instruction[28], instruction[29], instruction[30]}) === 17'b01111100010010000); + assign MICROCODE_PT[2] = (({instruction[0], instruction[1], instruction[2], instruction[3], instruction[4], instruction[5], instruction[21], instruction[22], instruction[23], instruction[24], instruction[25], instruction[26], instruction[27], instruction[28], instruction[29], instruction[30]}) === 16'b0111111000000000); + assign MICROCODE_PT[3] = (({core64, instruction[0], instruction[1], instruction[2], instruction[3], instruction[4], instruction[5], instruction[21], instruction[22], instruction[23], instruction[24], instruction[25], instruction[26], instruction[27], instruction[28], instruction[30]}) === 16'b1011111010111011); + assign MICROCODE_PT[4] = (({instruction[0], instruction[1], instruction[2], instruction[3], instruction[4], instruction[5], instruction[11], instruction[21], instruction[22], instruction[23], instruction[24], instruction[25], instruction[26], instruction[27], instruction[28], instruction[29], instruction[30]}) === 17'b01111100000010011); + assign MICROCODE_PT[5] = (({core64, instruction[0], instruction[1], instruction[2], instruction[3], instruction[4], instruction[5], instruction[21], instruction[22], instruction[23], instruction[24], instruction[25], instruction[26], instruction[27], instruction[28], instruction[30]}) === 16'b1011111000011011); + assign MICROCODE_PT[6] = (({instruction[0], instruction[1], instruction[2], instruction[3], instruction[4], instruction[5], instruction[21], instruction[22], instruction[25], instruction[26], instruction[27], instruction[28], instruction[29], instruction[30]}) === 14'b01111110010101); + assign MICROCODE_PT[7] = (({instruction[0], instruction[1], instruction[2], instruction[3], instruction[4], instruction[5], instruction[21], instruction[23], instruction[25], instruction[26], instruction[27], instruction[28], instruction[29], instruction[30]}) === 14'b01111100110111); + assign MICROCODE_PT[8] = (({instruction[0], instruction[1], instruction[2], instruction[3], instruction[4], instruction[5], instruction[22], instruction[23], instruction[25], instruction[26], instruction[27], instruction[28], instruction[29], instruction[30]}) === 14'b01111100110111); + assign MICROCODE_PT[9] = (({core64, instruction[0], instruction[1], instruction[2], instruction[3], instruction[4], instruction[5], instruction[30], instruction[31]}) === 9'b111101001); + assign MICROCODE_PT[10] = (({instruction[0], instruction[2], instruction[3], instruction[5]}) === 4'b1001); + assign MICROCODE_PT[11] = (({instruction[0], instruction[1], instruction[3], instruction[5]}) === 4'b1001); + assign MICROCODE_PT[12] = (({instruction[0], instruction[1], instruction[2], instruction[3], instruction[4]}) === 5'b10111); + // Table MICROCODE Signal Assignments for Outputs + assign to_uc = (MICROCODE_PT[1] | MICROCODE_PT[2] | MICROCODE_PT[3] | MICROCODE_PT[4] | MICROCODE_PT[5] | MICROCODE_PT[6] | MICROCODE_PT[7] | MICROCODE_PT[8] | MICROCODE_PT[9] | MICROCODE_PT[10] | MICROCODE_PT[11] | MICROCODE_PT[12]); +//assign_end + +endmodule diff --git a/dev/verilog/work/iuq_bp.v b/dev/verilog/work/iuq_bp.v new file mode 100755 index 0000000..d3d3bb4 --- /dev/null +++ b/dev/verilog/work/iuq_bp.v @@ -0,0 +1,3714 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +module iuq_bp( + iu2_0_bh0_rd_data, + iu2_1_bh0_rd_data, + iu2_2_bh0_rd_data, + iu2_3_bh0_rd_data, + iu2_0_bh1_rd_data, + iu2_1_bh1_rd_data, + iu2_2_bh1_rd_data, + iu2_3_bh1_rd_data, + iu2_0_bh2_rd_data, + iu2_1_bh2_rd_data, + iu2_2_bh2_rd_data, + iu2_3_bh2_rd_data, + iu0_bh0_rd_addr, + iu0_bh1_rd_addr, + iu0_bh2_rd_addr, + iu0_bh0_rd_act, + iu0_bh1_rd_act, + iu0_bh2_rd_act, + ex5_bh0_wr_data, + ex5_bh1_wr_data, + ex5_bh2_wr_data, + ex5_bh0_wr_addr, + ex5_bh1_wr_addr, + ex5_bh2_wr_addr, + ex5_bh0_wr_act, + ex5_bh1_wr_act, + ex5_bh2_wr_act, + iu0_btb_rd_addr, + iu0_btb_rd_act, + iu2_btb_rd_data, + ex5_btb_wr_addr, + ex5_btb_wr_act, + ex5_btb_wr_data, + ic_bp_iu0_val, + ic_bp_iu0_ifar, + ic_bp_iu2_val, + ic_bp_iu2_ifar, + ic_bp_iu2_error, + ic_bp_iu2_2ucode, + ic_bp_iu2_flush, + ic_bp_iu3_flush, + ic_bp_iu3_ecc_err, + ic_bp_iu2_0_instr, + ic_bp_iu2_1_instr, + ic_bp_iu2_2_instr, + ic_bp_iu2_3_instr, + bp_ib_iu3_val, + bp_ib_iu3_ifar, + bp_ib_iu3_bta, + bp_ib_iu3_0_instr, + bp_ib_iu3_1_instr, + bp_ib_iu3_2_instr, + bp_ib_iu3_3_instr, + bp_ic_iu3_hold, + bp_ic_iu2_redirect, + bp_ic_iu3_redirect, + bp_ic_iu4_redirect, + bp_ic_redirect_ifar, + cp_bp_ifar, + cp_bp_val, + cp_bp_bh0_hist, + cp_bp_bh1_hist, + cp_bp_bh2_hist, + cp_bp_br_pred, + cp_bp_br_taken, + cp_bp_bh_update, + cp_bp_bcctr, + cp_bp_bclr, + cp_bp_getNIA, + cp_bp_group, + cp_bp_lk, + cp_bp_bh, + cp_bp_bta, + cp_bp_gshare, + cp_bp_ls_ptr, + cp_bp_btb_hist, + cp_bp_btb_entry, + br_iu_gshare, + br_iu_ls_ptr, + br_iu_ls_data, + br_iu_ls_update, + iu_flush, + br_iu_redirect, + cp_flush, + ib_ic_iu4_redirect, + uc_iu4_flush, + spr_bp_config, + spr_bp_size, + xu_iu_msr_de, + xu_iu_dbcr0_icmp, + xu_iu_dbcr0_brt, + xu_iu_iac1_en, + xu_iu_iac2_en, + xu_iu_iac3_en, + xu_iu_iac4_en, + lq_iu_spr_dbcr3_ivc, + xu_iu_single_instr_mode, + spr_single_issue, + vdd, + gnd, + nclk, + pc_iu_sg_2, + pc_iu_func_sl_thold_2, + clkoff_b, + act_dis, + tc_ac_ccflush_dc, + d_mode, + delay_lclkr, + mpw1_b, + mpw2_b, + scan_in, + scan_out +); +// parameter `EFF_IFAR_ARCH = 62; +// parameter `EFF_IFAR_WIDTH = 20; +// parameter PRED_TYPE = 0; // 0 = hybrid, 1 = gskew + +`include "tri_a2o.vh" + + //in from bht + input [0:1] iu2_0_bh0_rd_data; + input [0:1] iu2_1_bh0_rd_data; + input [0:1] iu2_2_bh0_rd_data; + input [0:1] iu2_3_bh0_rd_data; + + input [0:1] iu2_0_bh1_rd_data; + input [0:1] iu2_1_bh1_rd_data; + input [0:1] iu2_2_bh1_rd_data; + input [0:1] iu2_3_bh1_rd_data; + + input iu2_0_bh2_rd_data; + input iu2_1_bh2_rd_data; + input iu2_2_bh2_rd_data; + input iu2_3_bh2_rd_data; + + //out to bht + output [0:9] iu0_bh0_rd_addr; + output [0:9] iu0_bh1_rd_addr; + output [0:8] iu0_bh2_rd_addr; + output iu0_bh0_rd_act; + output iu0_bh1_rd_act; + output iu0_bh2_rd_act; + output [0:1] ex5_bh0_wr_data; + output [0:1] ex5_bh1_wr_data; + output ex5_bh2_wr_data; + output [0:9] ex5_bh0_wr_addr; + output [0:9] ex5_bh1_wr_addr; + output [0:8] ex5_bh2_wr_addr; + output [0:3] ex5_bh0_wr_act; + output [0:3] ex5_bh1_wr_act; + output [0:3] ex5_bh2_wr_act; + + //in/out to btb + output [0:5] iu0_btb_rd_addr; + output iu0_btb_rd_act; + input [0:63] iu2_btb_rd_data; + output [0:5] ex5_btb_wr_addr; + output ex5_btb_wr_act; + output [0:63] ex5_btb_wr_data; + + //iu0 + input ic_bp_iu0_val; + input [50:59] ic_bp_iu0_ifar; + + //iu2 + input [0:3] ic_bp_iu2_val; + input [62-`EFF_IFAR_WIDTH:61] ic_bp_iu2_ifar; + input [0:2] ic_bp_iu2_error; + input ic_bp_iu2_2ucode; + input ic_bp_iu2_flush; + input ic_bp_iu3_flush; + input ic_bp_iu3_ecc_err; + + //iu2 instruction(0:31) + predecode(32:35) + input [0:35] ic_bp_iu2_0_instr; + input [0:35] ic_bp_iu2_1_instr; + input [0:35] ic_bp_iu2_2_instr; + input [0:35] ic_bp_iu2_3_instr; + + //iu3 + output [0:3] bp_ib_iu3_val; + output [62-`EFF_IFAR_WIDTH:61] bp_ib_iu3_ifar; + output [62-`EFF_IFAR_WIDTH:61] bp_ib_iu3_bta; + + //iu3 instruction(0:31) + + output [0:69] bp_ib_iu3_0_instr; + output [0:69] bp_ib_iu3_1_instr; + output [0:69] bp_ib_iu3_2_instr; + output [0:69] bp_ib_iu3_3_instr; + + //iu4 hold/redirect + output bp_ic_iu3_hold; + output bp_ic_iu2_redirect; + output bp_ic_iu3_redirect; + output bp_ic_iu4_redirect; + output [62-`EFF_IFAR_WIDTH:61] bp_ic_redirect_ifar; + + //ex4 update + input [62-`EFF_IFAR_WIDTH:61] cp_bp_ifar; + input cp_bp_val; + input [0:1] cp_bp_bh0_hist; + input [0:1] cp_bp_bh1_hist; + input [0:1] cp_bp_bh2_hist; + input cp_bp_br_pred; + input cp_bp_br_taken; + input cp_bp_bh_update; + input cp_bp_bcctr; + input cp_bp_bclr; + input cp_bp_getNIA; + input cp_bp_group; + input cp_bp_lk; + input [0:1] cp_bp_bh; + input [62-`EFF_IFAR_WIDTH:61] cp_bp_bta; + input [0:9] cp_bp_gshare; + input [0:2] cp_bp_ls_ptr; + input [0:1] cp_bp_btb_hist; + input cp_bp_btb_entry; + + //br unit repairs + input [0:17] br_iu_gshare; + input [0:2] br_iu_ls_ptr; + input [62-`EFF_IFAR_WIDTH:61] br_iu_ls_data; + input br_iu_ls_update; + + //flush conditions + input iu_flush; + input br_iu_redirect; + input cp_flush; + input ib_ic_iu4_redirect; + input uc_iu4_flush; + + //config bits + input [0:5] spr_bp_config; + input [0:1] spr_bp_size; + input xu_iu_msr_de; + input xu_iu_dbcr0_icmp; + input xu_iu_dbcr0_brt; + input xu_iu_iac1_en; + input xu_iu_iac2_en; + input xu_iu_iac3_en; + input xu_iu_iac4_en; + input lq_iu_spr_dbcr3_ivc; + input xu_iu_single_instr_mode; + input spr_single_issue; + + //pervasive + inout vdd; + inout gnd; + (* pin_data="PIN_FUNCTION=/G_CLK/" *) + input [0:`NCLK_WIDTH-1] nclk; + input pc_iu_sg_2; + input pc_iu_func_sl_thold_2; + input clkoff_b; + input act_dis; + input tc_ac_ccflush_dc; + input d_mode; + input delay_lclkr; + input mpw1_b; + input mpw2_b; + input [0:1] scan_in; + + output [0:1] scan_out; + + localparam [0:31] value_1 = 32'h00000001; + localparam [0:31] value_2 = 32'h00000002; + + //-------------------------- + // components + //-------------------------- + + //-------------------------- + // constants + //-------------------------- + + //scan chain 0 + + parameter iu0_btb_hist_offset = 0; + parameter iu1_btb_hist_offset = iu0_btb_hist_offset + 128; + parameter iu2_btb_hist_offset = iu1_btb_hist_offset + 2; + parameter gshare_offset = iu2_btb_hist_offset + 2; + parameter gshare_shift0_offset = gshare_offset + 16; + parameter cp_gshare_offset = gshare_shift0_offset + 5; + parameter cp_gs_count_offset = cp_gshare_offset + 16; + parameter cp_gs_taken_offset = cp_gs_count_offset + 2; + parameter iu1_gs_pos_offset = cp_gs_taken_offset + 1; + parameter iu2_gs_pos_offset = iu1_gs_pos_offset + 3; + parameter iu3_gs_pos_offset = iu2_gs_pos_offset + 3; + parameter iu1_gshare_offset = iu3_gs_pos_offset + 3; + parameter iu2_gshare_offset = iu1_gshare_offset + 10; + parameter iu3_bh_offset = iu2_gshare_offset + 10; + parameter iu3_lk_offset = iu3_bh_offset + 2; + parameter iu3_aa_offset = iu3_lk_offset + 1; + parameter iu3_b_offset = iu3_aa_offset + 1; + parameter iu3_bclr_offset = iu3_b_offset + 1; + parameter iu3_bcctr_offset = iu3_bclr_offset + 1; + parameter iu3_opcode_offset = iu3_bcctr_offset + 1; + parameter iu3_bo_offset = iu3_opcode_offset + 6; + parameter iu3_bi_offset = iu3_bo_offset + 5; + parameter iu3_tar_offset = iu3_bi_offset + 5; + parameter iu3_ifar_offset = iu3_tar_offset + 24; + parameter iu3_ifar_pri_offset = iu3_ifar_offset + `EFF_IFAR_WIDTH; + parameter iu3_pr_val_offset = iu3_ifar_pri_offset + 2; + parameter iu3_lnk_offset = iu3_pr_val_offset + 1; + parameter iu3_btb_offset = iu3_lnk_offset + `EFF_IFAR_WIDTH; + parameter iu3_nfg_offset = iu3_btb_offset + `EFF_IFAR_WIDTH; + parameter iu3_val_offset = iu3_nfg_offset + `EFF_IFAR_WIDTH; + parameter iu3_0_instr_offset = iu3_val_offset + 4; + parameter iu3_1_instr_offset = iu3_0_instr_offset + 61; + parameter iu3_2_instr_offset = iu3_1_instr_offset + 61; + parameter iu3_3_instr_offset = iu3_2_instr_offset + 61; + parameter iu3_btb_redirect_offset = iu3_3_instr_offset + 61; + parameter iu3_btb_misdirect_offset = iu3_btb_redirect_offset + 1; + parameter iu3_btb_link_offset = iu3_btb_misdirect_offset + 1; + parameter iu4_redirect_ifar_offset = iu3_btb_link_offset + 1; + parameter iu4_redirect_offset = iu4_redirect_ifar_offset + `EFF_IFAR_WIDTH; + parameter iu4_ls_push_offset = iu4_redirect_offset + 1; + parameter iu4_ls_pop_offset = iu4_ls_push_offset + 1; + parameter iu4_ifar_offset = iu4_ls_pop_offset + 1; + parameter scan_right0 = iu4_ifar_offset + `EFF_IFAR_WIDTH - 1; + + //scan chain 1 + parameter iu5_ls_t0_ptr_offset = 0; + parameter iu5_ls_t00_offset = iu5_ls_t0_ptr_offset + 8; + parameter iu5_ls_t01_offset = iu5_ls_t00_offset + `EFF_IFAR_WIDTH; + parameter iu5_ls_t02_offset = iu5_ls_t01_offset + `EFF_IFAR_WIDTH; + parameter iu5_ls_t03_offset = iu5_ls_t02_offset + `EFF_IFAR_WIDTH; + parameter iu5_ls_t04_offset = iu5_ls_t03_offset + `EFF_IFAR_WIDTH; + parameter iu5_ls_t05_offset = iu5_ls_t04_offset + `EFF_IFAR_WIDTH; + parameter iu5_ls_t06_offset = iu5_ls_t05_offset + `EFF_IFAR_WIDTH; + parameter iu5_ls_t07_offset = iu5_ls_t06_offset + `EFF_IFAR_WIDTH; + parameter ex6_ls_t00_offset = iu5_ls_t07_offset + `EFF_IFAR_WIDTH; + parameter ex6_ls_t01_offset = ex6_ls_t00_offset + `EFF_IFAR_WIDTH; + parameter ex6_ls_t02_offset = ex6_ls_t01_offset + `EFF_IFAR_WIDTH; + parameter ex6_ls_t03_offset = ex6_ls_t02_offset + `EFF_IFAR_WIDTH; + parameter ex6_ls_t04_offset = ex6_ls_t03_offset + `EFF_IFAR_WIDTH; + parameter ex6_ls_t05_offset = ex6_ls_t04_offset + `EFF_IFAR_WIDTH; + parameter ex6_ls_t06_offset = ex6_ls_t05_offset + `EFF_IFAR_WIDTH; + parameter ex6_ls_t07_offset = ex6_ls_t06_offset + `EFF_IFAR_WIDTH; + parameter ex5_val_offset = ex6_ls_t07_offset + `EFF_IFAR_WIDTH; + parameter ex5_ifar_offset = ex5_val_offset + 1; + parameter ex5_bh_update_offset = ex5_ifar_offset + `EFF_IFAR_WIDTH; + parameter ex5_gshare_offset = ex5_bh_update_offset + 1; + parameter ex5_bh0_hist_offset = ex5_gshare_offset + 10; + parameter ex5_bh1_hist_offset = ex5_bh0_hist_offset + 2; + parameter ex5_bh2_hist_offset = ex5_bh1_hist_offset + 2; + parameter ex5_br_pred_offset = ex5_bh2_hist_offset + 2; + parameter ex5_bcctr_offset = ex5_br_pred_offset + 1; + parameter ex5_bta_offset = ex5_bcctr_offset + 1; + parameter ex5_br_taken_offset = ex5_bta_offset + `EFF_IFAR_WIDTH; + parameter ex5_ls_ptr_offset = ex5_br_taken_offset + 1; + parameter ex5_bclr_offset = ex5_ls_ptr_offset + 8; + parameter ex5_getNIA_offset = ex5_bclr_offset + 1; + parameter ex5_group_offset = ex5_getNIA_offset + 1; + parameter ex5_lk_offset = ex5_group_offset + 1; + parameter ex5_bh_offset = ex5_lk_offset + 1; + parameter ex5_ls_push_offset = ex5_bh_offset + 2; + parameter ex5_ls_pop_offset = ex5_ls_push_offset + 1; + parameter ex5_flush_offset = ex5_ls_pop_offset + 1; + parameter ex5_btb_hist_offset = ex5_flush_offset + 1; + parameter ex5_btb_entry_offset = ex5_btb_hist_offset + 2; + parameter ex5_btb_repl_offset = ex5_btb_entry_offset + 1; + parameter ex6_ls_t0_ptr_offset = ex5_btb_repl_offset + 128; + parameter bp_config_offset = ex6_ls_t0_ptr_offset + 8; + parameter br_iu_gshare_offset = bp_config_offset + 7; + parameter br_iu_ls_ptr_offset = br_iu_gshare_offset + 18; + parameter br_iu_ls_data_offset = br_iu_ls_ptr_offset + 8; + parameter br_iu_ls_update_offset = br_iu_ls_data_offset + `EFF_IFAR_WIDTH; + parameter br_iu_redirect_offset = br_iu_ls_update_offset + 1; + parameter cp_flush_offset = br_iu_redirect_offset + 1; + parameter iu_flush_offset = cp_flush_offset + 1; + parameter bcache_data0_offset = iu_flush_offset + 1; + parameter bcache_data1_offset = bcache_data0_offset + 16; + parameter bcache_data2_offset = bcache_data1_offset + 16; + parameter bcache_data3_offset = bcache_data2_offset + 16; + parameter bcache_data4_offset = bcache_data3_offset + 16; + parameter bcache_data5_offset = bcache_data4_offset + 16; + parameter bcache_data6_offset = bcache_data5_offset + 16; + parameter bcache_data7_offset = bcache_data6_offset + 16; + parameter scan_right1 = bcache_data7_offset + 16 - 1; + + //-------------------------- + // signals + //-------------------------- + + wire fuse_en; + + wire bp_dy_en; + wire bp_st_en; + wire bp_bt_en; + wire [0:1] bp_gs_mode; + + wire [0:6] bp_config_d; + wire [0:6] bp_config_q; + + wire [0:9] iu0_bh_ti0gs0_rd_addr; + wire [0:9] iu0_bh_ti0gs1_rd_addr; + wire [0:8] iu0_bh_ti0gs2_rd_addr; + wire [0:9] iu0_gshare0; + wire [0:9] iu0_gshare1; + wire [0:8] iu0_gshare2; + + wire [0:9] ex5_bh_ti0gs0_wr_addr; + wire [0:9] ex5_bh_ti0gs1_wr_addr; + wire [0:8] ex5_bh_ti0gs2_wr_addr; + wire [0:9] ex5_gshare0; + wire [0:9] ex5_gshare1; + wire [0:8] ex5_gshare2; + wire [0:3] ex5_bh_wr_act; + + wire [0:0] gshare_act; + wire gshare_taken; + + wire [0:4] gshare_shift; + wire [0:4] gshare_shift1; + wire [0:4] gshare_shift2; + wire [0:4] gshare_shift3; + wire [0:4] gshare_shift4; + wire [0:4] gshare_shift0_d; + wire [0:4] gshare_shift0_q; + + wire cp_gshare_shift; + wire cp_gshare_taken; + wire [0:15] cp_gshare_d; + wire [0:15] cp_gshare_q; + + wire [0:15] gshare_d; + wire [0:15] gshare_q; + + wire [0:9] iu1_gshare_d; + wire [0:9] iu1_gshare_q; + wire [0:9] iu2_gshare_d; + wire [0:9] iu2_gshare_q; + + wire iu2_0_bh_pred; + wire iu2_1_bh_pred; + wire iu2_2_bh_pred; + wire iu2_3_bh_pred; + + wire [0:1] iu2_0_bh0_hist; + wire [0:1] iu2_1_bh0_hist; + wire [0:1] iu2_2_bh0_hist; + wire [0:1] iu2_3_bh0_hist; + + wire [0:1] iu2_0_bh1_hist; + wire [0:1] iu2_1_bh1_hist; + wire [0:1] iu2_2_bh1_hist; + wire [0:1] iu2_3_bh1_hist; + + wire iu2_0_bh2_hist; + wire iu2_1_bh2_hist; + wire iu2_2_bh2_hist; + wire iu2_3_bh2_hist; + + wire [0:3] iu2_fuse; + wire [0:3] iu2_uc; + wire [0:3] iu2_br_val; + wire [0:3] iu2_br_hard; + wire [0:3] iu2_hint_val; + wire [0:3] iu2_hint; + wire [0:3] iu2_bh_pred; + + wire [0:3] iu2_bh_update; + wire [0:3] iu2_br_dynamic; + wire [0:3] iu2_br_static; + wire [0:3] iu2_br_pred; + + wire [0:33] iu2_instr_pri; + + wire [62-`EFF_IFAR_WIDTH:61] iu2_lnk; + wire [62-`EFF_IFAR_WIDTH:61] iu2_btb; + wire [0:2] iu2_ls_ptr; + + wire [62-`EFF_IFAR_WIDTH:61] iu2_btb_tag; + wire iu2_btb_link; + wire [0:1] iu2_btb_hist; + wire [0:3] iu2_btb_entry; + + wire iu1_flush; + wire iu2_flush; + + wire iu2_redirect; + wire iu3_btb_redirect_d; + wire iu3_btb_redirect_q; + wire iu3_btb_misdirect_d; + wire iu3_btb_misdirect_q; + wire iu3_btb_link_d; + wire iu3_btb_link_q; + + wire [0:1] iu0_btb_hist_new; + wire [0:127] iu0_btb_hist_out; + wire iu0_btb_hist_act; + wire [0:127] iu0_btb_hist_d; + wire [0:127] iu0_btb_hist_q; + wire [0:1] iu1_btb_hist_d; + wire [0:1] iu1_btb_hist_q; + wire [0:1] iu2_btb_hist_d; + wire [0:1] iu2_btb_hist_q; + + wire [0:127] ex5_btb_hist_out; + wire [0:1] ex5_btb_hist; + wire [0:1] ex5_btb_repl_cnt; + wire [0:1] ex5_btb_repl_new; + wire [0:127] ex5_btb_repl_out; + wire [0:127] ex5_btb_repl_d; + wire [0:127] ex5_btb_repl_q; + + wire iu3_b_d; + wire iu3_b_q; + wire [62-`EFF_IFAR_WIDTH:61] iu3_bd; + wire [62-`EFF_IFAR_WIDTH:61] iu3_li; + + wire iu3_act; + wire [0:3] iu3_instr_act; + + wire [0:3] iu3_bh_update; + wire [0:3] iu3_br_pred; + + wire [0:1] iu3_bh_d; + wire [0:1] iu3_bh_q; + wire iu3_lk_d; + wire iu3_lk_q; + wire iu3_aa_d; + wire iu3_aa_q; + + wire iu3_bclr_d; + wire iu3_bclr_q; + wire iu3_bcctr_d; + wire iu3_bcctr_q; + + wire [0:5] iu3_opcode_d; + wire [0:5] iu3_opcode_q; + wire [6:10] iu3_bo_d; + wire [6:10] iu3_bo_q; + wire [11:15] iu3_bi_d; + wire [11:15] iu3_bi_q; + wire iu3_getNIA; + + wire [6:29] iu3_tar_d; + wire [6:29] iu3_tar_q; + wire [62-`EFF_IFAR_WIDTH:61] iu3_abs; + + wire [62-`EFF_IFAR_WIDTH:61] iu3_ifar_d; + wire [62-`EFF_IFAR_WIDTH:61] iu3_ifar_q; + wire [60:61] iu3_ifar_pri_d; + wire [60:61] iu3_ifar_pri_q; + + wire [62-`EFF_IFAR_WIDTH:61] iu3_off; + wire [62-`EFF_IFAR_WIDTH:61] iu3_bta; + + wire [62-`EFF_IFAR_WIDTH:61] iu3_lnk_d; + wire [62-`EFF_IFAR_WIDTH:61] iu3_lnk_q; + wire [62-`EFF_IFAR_WIDTH:61] iu3_btb_d; + wire [62-`EFF_IFAR_WIDTH:61] iu3_btb_q; + wire [62-`EFF_IFAR_WIDTH:61] iu3_nfg_d; + wire [62-`EFF_IFAR_WIDTH:61] iu3_nfg_q; + + wire iu3_pr_val_d; + wire iu3_pr_val_q; + + wire [0:3] iu3_val_d; + wire [0:3] iu3_val_q; + + wire [0:60] iu3_0_instr_d; + wire [0:60] iu3_0_instr_q; + wire [0:60] iu3_1_instr_d; + wire [0:60] iu3_1_instr_q; + wire [0:60] iu3_2_instr_d; + wire [0:60] iu3_2_instr_q; + wire [0:60] iu3_3_instr_d; + wire [0:60] iu3_3_instr_q; + + wire bp_ib_iu3_bta_val; + + wire iu3_flush; + wire iu3_redirect; + wire iu3_redirect_early; + + wire iu4_flush; + + wire [62-`EFF_IFAR_WIDTH:61] iu4_redirect_ifar_d; + wire [62-`EFF_IFAR_WIDTH:61] iu4_redirect_ifar_q; + wire iu4_redirect_d; + wire iu4_redirect_q; + wire iu4_redirect_act; + + wire iu4_act; + + wire iu4_ls_push_d; + wire iu4_ls_push_q; + wire iu4_ls_pop_d; + wire iu4_ls_pop_q; + + wire [62-`EFF_IFAR_WIDTH:61] iu4_ifar_d; + wire [62-`EFF_IFAR_WIDTH:61] iu4_ifar_q; + + wire [62-`EFF_IFAR_WIDTH:61] ex5_ifar_d; + wire [62-`EFF_IFAR_WIDTH:61] ex5_ifar_q; + wire ex5_val_d; + wire ex5_val_q; + wire ex5_bh_update_d; + wire ex5_bh_update_q; + wire [0:9] ex5_gshare_d; + wire [0:9] ex5_gshare_q; + wire [0:1] ex5_bh0_hist_d; + wire [0:1] ex5_bh0_hist_q; + wire [0:1] ex5_bh1_hist_d; + wire [0:1] ex5_bh1_hist_q; + wire [0:1] ex5_bh2_hist_d; + wire [0:1] ex5_bh2_hist_q; + wire ex5_br_pred_d; + wire ex5_br_pred_q; + wire ex5_br_taken_d; + wire ex5_br_taken_q; + wire ex5_bcctr_d; + wire ex5_bcctr_q; + wire ex5_bclr_d; + wire ex5_bclr_q; + wire ex5_getNIA_d; + wire ex5_getNIA_q; + wire ex5_group_d; + wire ex5_group_q; + wire ex5_lk_d; + wire ex5_lk_q; + wire [0:1] ex5_bh_d; + wire [0:1] ex5_bh_q; + wire [62-`EFF_IFAR_WIDTH:61] ex5_bta_d; + wire [62-`EFF_IFAR_WIDTH:61] ex5_bta_q; + wire [0:7] ex5_ls_ptr_d; + wire [0:7] ex5_ls_ptr_q; + wire [0:1] ex5_btb_hist_d; + wire [0:1] ex5_btb_hist_q; + wire ex5_btb_entry_d; + wire ex5_btb_entry_q; + + wire ex5_ls_push_d; + wire ex5_ls_push_q; + wire ex5_ls_pop_d; + wire ex5_ls_pop_q; + + wire ex6_ls_ptr_act; + wire [0:7] ex6_ls_t0_ptr_d; + wire [0:7] ex6_ls_t0_ptr_q; + + wire ex5_flush_d; + wire ex5_flush_q; + + wire ex5_bh0_dec; + wire ex5_bh0_inc; + wire ex5_bh1_dec; + wire ex5_bh1_inc; + wire ex5_bh2_dec; + wire ex5_bh2_inc; + + wire ex5_bh0_wr_en; + wire ex5_bh1_wr_en; + wire ex5_bh2_wr_en; + + wire [0:7] iu5_ls_t0_ptr_d; + wire [0:7] iu5_ls_t0_ptr_q; + wire [0:0] iu5_ls_ptr_act; + + wire iu4_ls_update; + wire ex5_ls_update; + wire ex5_repair; + + wire [62-`EFF_IFAR_WIDTH:61] iu4_nia; + wire [62-`EFF_IFAR_WIDTH:61] ex5_nia; + + wire [62-`EFF_IFAR_WIDTH:61] iu5_ls_t00_d; + wire [62-`EFF_IFAR_WIDTH:61] iu5_ls_t00_q; + wire [62-`EFF_IFAR_WIDTH:61] iu5_ls_t01_d; + wire [62-`EFF_IFAR_WIDTH:61] iu5_ls_t01_q; + wire [62-`EFF_IFAR_WIDTH:61] iu5_ls_t02_d; + wire [62-`EFF_IFAR_WIDTH:61] iu5_ls_t02_q; + wire [62-`EFF_IFAR_WIDTH:61] iu5_ls_t03_d; + wire [62-`EFF_IFAR_WIDTH:61] iu5_ls_t03_q; + wire [62-`EFF_IFAR_WIDTH:61] iu5_ls_t04_d; + wire [62-`EFF_IFAR_WIDTH:61] iu5_ls_t04_q; + wire [62-`EFF_IFAR_WIDTH:61] iu5_ls_t05_d; + wire [62-`EFF_IFAR_WIDTH:61] iu5_ls_t05_q; + wire [62-`EFF_IFAR_WIDTH:61] iu5_ls_t06_d; + wire [62-`EFF_IFAR_WIDTH:61] iu5_ls_t06_q; + wire [62-`EFF_IFAR_WIDTH:61] iu5_ls_t07_d; + wire [62-`EFF_IFAR_WIDTH:61] iu5_ls_t07_q; + wire [0:7] iu5_ls_t0_act; + + wire [62-`EFF_IFAR_WIDTH:61] ex6_ls_t00_d; + wire [62-`EFF_IFAR_WIDTH:61] ex6_ls_t00_q; + wire [62-`EFF_IFAR_WIDTH:61] ex6_ls_t01_d; + wire [62-`EFF_IFAR_WIDTH:61] ex6_ls_t01_q; + wire [62-`EFF_IFAR_WIDTH:61] ex6_ls_t02_d; + wire [62-`EFF_IFAR_WIDTH:61] ex6_ls_t02_q; + wire [62-`EFF_IFAR_WIDTH:61] ex6_ls_t03_d; + wire [62-`EFF_IFAR_WIDTH:61] ex6_ls_t03_q; + wire [62-`EFF_IFAR_WIDTH:61] ex6_ls_t04_d; + wire [62-`EFF_IFAR_WIDTH:61] ex6_ls_t04_q; + wire [62-`EFF_IFAR_WIDTH:61] ex6_ls_t05_d; + wire [62-`EFF_IFAR_WIDTH:61] ex6_ls_t05_q; + wire [62-`EFF_IFAR_WIDTH:61] ex6_ls_t06_d; + wire [62-`EFF_IFAR_WIDTH:61] ex6_ls_t06_q; + wire [62-`EFF_IFAR_WIDTH:61] ex6_ls_t07_d; + wire [62-`EFF_IFAR_WIDTH:61] ex6_ls_t07_q; + wire [0:7] ex6_ls_t0_act; + + wire br_iu_redirect_q; + wire cp_flush_q; + wire iu_flush_q; + + wire [0:17] br_iu_gshare_d; + wire [0:17] br_iu_gshare_q; + wire [0:7] br_iu_ls_ptr_d; + wire [0:7] br_iu_ls_ptr_q; + wire [62-`EFF_IFAR_WIDTH:61] br_iu_ls_data_d; + wire [62-`EFF_IFAR_WIDTH:61] br_iu_ls_data_q; + wire br_iu_ls_update_d; + wire br_iu_ls_update_q; + + wire [0:31] xnop; + + wire tiup; + wire tidn; + + wire pc_iu_func_sl_thold_1; + wire pc_iu_func_sl_thold_0; + wire pc_iu_func_sl_thold_0_b; + wire pc_iu_sg_1; + wire pc_iu_sg_0; + wire force_t; + + wire [0:scan_right0] siv0; + wire [0:scan_right0] sov0; + + wire [0:scan_right1] siv1; + wire [0:scan_right1] sov1; + +wire iu0_val; +wire [0:1] iu3_gs_count_next; +wire [0:1] iu3_gs_count; +wire [0:5] iu3_gs_counts; +wire [0:1] iu3_gs_count0; +wire [0:1] iu3_gs_count1; +wire [0:1] iu3_gs_count2; +wire [0:1] iu3_gs_count3; +wire [0:2] iu3_gs_pos; +wire [0:1] cp_gs_count; +wire [0:1] cp_gs_count_d; +wire [0:1] cp_gs_count_q; +wire cp_gs_taken; +wire cp_gs_taken_d; +wire cp_gs_taken_q; +wire cp_gs_group; +wire [0:2] iu3_gs_pos_d; +wire [0:2] iu3_gs_pos_q; +wire [0:2] iu2_gs_pos_d; +wire [0:2] iu2_gs_pos_q; +wire [0:2] iu1_gs_pos_d; +wire [0:2] iu1_gs_pos_q; + + +wire [0:1] ex5_bh0_hist; +wire [0:1] ex5_bh1_hist; +wire [0:1] bcache_bh0_hist; +wire [0:1] bcache_bh1_hist; +wire [0:1] bcache_bh0_wr_data; +wire [0:1] bcache_bh1_wr_data; +wire [0:11] bcache_wr_addr; +wire [0:15] bcache_data_new; +wire [0:15] bcache_data0_d; +wire [0:15] bcache_data0_q; +wire [0:15] bcache_data1_d; +wire [0:15] bcache_data1_q; +wire [0:15] bcache_data2_d; +wire [0:15] bcache_data2_q; +wire [0:15] bcache_data3_d; +wire [0:15] bcache_data3_q; +wire [0:15] bcache_data4_d; +wire [0:15] bcache_data4_q; +wire [0:15] bcache_data5_d; +wire [0:15] bcache_data5_q; +wire [0:15] bcache_data6_d; +wire [0:15] bcache_data6_q; +wire [0:15] bcache_data7_d; +wire [0:15] bcache_data7_q; +wire [0:7] bcache_hit; +wire [0:7] bcache_shift; + + assign tiup = 1'b1; + assign tidn = 1'b0; + + //------------------------------------------------- + //-- config bits + //------------------------------------------------- + + assign bp_config_d[0:5] = spr_bp_config[0:5]; + + assign bp_config_d[6] = xu_iu_msr_de | + xu_iu_dbcr0_icmp | + xu_iu_dbcr0_brt | + xu_iu_iac1_en | + xu_iu_iac2_en | + xu_iu_iac3_en | + xu_iu_iac4_en | + lq_iu_spr_dbcr3_ivc | + xu_iu_single_instr_mode | + spr_single_issue; + + + assign bp_dy_en = bp_config_q[0]; //dynamic prediction enable default = 1 + assign bp_st_en = bp_config_q[1]; //static prediction enable default = 0 + assign bp_bt_en = bp_config_q[2]; //btb enable default = 1 + + //fused branches enable default = 1 + assign fuse_en = bp_config_q[3] & (~bp_config_q[6]); //disable compare/branch fusion when debug enable or single instruction mode + + assign bp_gs_mode[0:1] = bp_config_q[4:5]; //length of BHT2 gshare hash 00 = 0 bits (default), 01 = 2 bits, 10 = 6 bits + + + //----------------------------------------------- + // latched xu interface + //----------------------------------------------- + + assign ex5_flush_d = cp_flush_q & iu_flush_q; + + assign ex5_ifar_d = cp_bp_ifar; + assign ex5_val_d = cp_bp_val & (~cp_flush_q); + assign ex5_bh0_hist_d = cp_bp_bh0_hist; + assign ex5_bh1_hist_d = cp_bp_bh1_hist; + assign ex5_bh2_hist_d = cp_bp_bh2_hist; + assign ex5_br_pred_d = cp_bp_br_pred; + assign ex5_br_taken_d = cp_bp_br_taken; + assign ex5_bh_update_d = cp_bp_bh_update; + assign ex5_gshare_d = cp_bp_gshare; + assign ex5_bcctr_d = cp_bp_bcctr; + assign ex5_bclr_d = cp_bp_bclr; + assign ex5_getNIA_d = cp_bp_getNIA; + assign ex5_group_d = cp_bp_group; + assign ex5_lk_d = cp_bp_lk; + assign ex5_bh_d = cp_bp_bh; + assign ex5_bta_d = cp_bp_bta; + assign ex5_btb_hist_d = cp_bp_btb_hist; + assign ex5_btb_entry_d = cp_bp_btb_entry; + + assign ex5_ls_ptr_d[0] = cp_bp_ls_ptr[0:2] == 3'b000; + assign ex5_ls_ptr_d[1] = cp_bp_ls_ptr[0:2] == 3'b001; + assign ex5_ls_ptr_d[2] = cp_bp_ls_ptr[0:2] == 3'b010; + assign ex5_ls_ptr_d[3] = cp_bp_ls_ptr[0:2] == 3'b011; + assign ex5_ls_ptr_d[4] = cp_bp_ls_ptr[0:2] == 3'b100; + assign ex5_ls_ptr_d[5] = cp_bp_ls_ptr[0:2] == 3'b101; + assign ex5_ls_ptr_d[6] = cp_bp_ls_ptr[0:2] == 3'b110; + assign ex5_ls_ptr_d[7] = cp_bp_ls_ptr[0:2] == 3'b111; + + //----------------------------------------------- + // latched br interface + //----------------------------------------------- + + assign br_iu_gshare_d = br_iu_gshare; + assign br_iu_ls_data_d = br_iu_ls_data; + assign br_iu_ls_update_d = br_iu_ls_update; + + assign br_iu_ls_ptr_d[0] = br_iu_ls_ptr[0:2] == 3'b000; + assign br_iu_ls_ptr_d[1] = br_iu_ls_ptr[0:2] == 3'b001; + assign br_iu_ls_ptr_d[2] = br_iu_ls_ptr[0:2] == 3'b010; + assign br_iu_ls_ptr_d[3] = br_iu_ls_ptr[0:2] == 3'b011; + assign br_iu_ls_ptr_d[4] = br_iu_ls_ptr[0:2] == 3'b100; + assign br_iu_ls_ptr_d[5] = br_iu_ls_ptr[0:2] == 3'b101; + assign br_iu_ls_ptr_d[6] = br_iu_ls_ptr[0:2] == 3'b110; + assign br_iu_ls_ptr_d[7] = br_iu_ls_ptr[0:2] == 3'b111; + + //----------------------------------------------- + // read branch history table + //----------------------------------------------- + + assign iu0_bh0_rd_act = iu0_val; + assign iu0_bh1_rd_act = iu0_val; + assign iu0_bh2_rd_act = iu0_val; + + assign iu0_val = ic_bp_iu0_val & ~iu1_flush; + + assign iu0_bh_ti0gs0_rd_addr[0:9] = (ic_bp_iu0_ifar[50:59] ^ iu0_gshare0[0:9]); + assign iu0_bh_ti0gs1_rd_addr[0:9] = (ic_bp_iu0_ifar[50:59] ^ iu0_gshare1[0:9]); + assign iu0_bh_ti0gs2_rd_addr[0:8] = (ic_bp_iu0_ifar[51:59] ^ iu0_gshare2[0:8]); + + assign iu0_bh0_rd_addr[0:9] = iu0_bh_ti0gs0_rd_addr[0:9]; + assign iu0_bh1_rd_addr[0:9] = iu0_bh_ti0gs1_rd_addr[0:9]; + assign iu0_bh2_rd_addr[0:8] = iu0_bh_ti0gs2_rd_addr[0:8]; + + assign iu0_gshare0[0:9] = gshare_q[0:9]; + assign iu0_gshare1[0:9] = gshare_q[0:9]; + + assign iu0_gshare2[0:8] = bp_gs_mode[0:1] == 2'b10 ? {gshare_q[0:5], 3'b000 } : + bp_gs_mode[0:1] == 2'b01 ? {gshare_q[0:1], 7'b0000000} : + 9'b000000000; + + assign iu1_gshare_d[0:9] = gshare_q[0:9]; + assign iu2_gshare_d[0:9] = iu1_gshare_q[0:9]; + + //----------------------------------------------- + // write branch history table + //----------------------------------------------- + + assign ex5_bh0_wr_act = ({4{ex5_bh0_wr_en}} & ex5_bh_wr_act); + assign ex5_bh1_wr_act = ({4{ex5_bh1_wr_en}} & ex5_bh_wr_act); + assign ex5_bh2_wr_act = ({4{ex5_bh2_wr_en}} & ex5_bh_wr_act); + + assign ex5_bh_ti0gs0_wr_addr[0:9] = (ex5_ifar_q[50:59] ^ ex5_gshare0[0:9]); + assign ex5_bh_ti0gs1_wr_addr[0:9] = (ex5_ifar_q[50:59] ^ ex5_gshare1[0:9]); + assign ex5_bh_ti0gs2_wr_addr[0:8] = (ex5_ifar_q[51:59] ^ ex5_gshare2[0:8]); + + assign ex5_bh0_wr_addr[0:9] = ex5_bh_ti0gs0_wr_addr[0:9]; + assign ex5_bh1_wr_addr[0:9] = ex5_bh_ti0gs1_wr_addr[0:9]; + assign ex5_bh2_wr_addr[0:8] = ex5_bh_ti0gs2_wr_addr[0:8]; + + assign ex5_gshare0[0:9] = ex5_gshare_q[0:9]; + assign ex5_gshare1[0:9] = ex5_gshare_q[0:9]; + + assign ex5_gshare2[0:8] = bp_gs_mode[0:1] == 2'b10 ? {ex5_gshare_q[0:5], 3'b000 } : + bp_gs_mode[0:1] == 2'b01 ? {ex5_gshare_q[0:1], 7'b0000000} : + 9'b000000000; + + + //----------------------------------------------- + // update branch hitstory + //----------------------------------------------- + +/* + assign ex5_bh_wr_act[0] = ex5_ifar_q[60:61] == 2'b00; + assign ex5_bh_wr_act[1] = ex5_ifar_q[60:61] == 2'b01; + assign ex5_bh_wr_act[2] = ex5_ifar_q[60:61] == 2'b10; + assign ex5_bh_wr_act[3] = ex5_ifar_q[60:61] == 2'b11; + + assign ex5_bh0_dec = ex5_br_taken_q == 1'b0 & ex5_bh0_hist_q[0:1] != 2'b00; + assign ex5_bh1_dec = ex5_br_taken_q == 1'b0 & ex5_bh1_hist_q[0:1] != 2'b00; + assign ex5_bh2_dec = ex5_br_taken_q == 1'b0 & ex5_bh2_hist_q[0] != 1'b0; + + assign ex5_bh0_inc = ex5_br_taken_q == 1'b1 & ex5_bh0_hist_q[0:1] != 2'b11; + assign ex5_bh1_inc = ex5_br_taken_q == 1'b1 & ex5_bh1_hist_q[0:1] != 2'b11; + assign ex5_bh2_inc = ex5_br_taken_q == 1'b1 & ex5_bh2_hist_q[0] != 1'b1; + + assign ex5_bh0_wr_data[0:1] = (ex5_bh0_inc == 1'b1) ? ex5_bh0_hist_q[0:1] + 2'b01 : + (ex5_bh0_dec == 1'b1) ? ex5_bh0_hist_q[0:1] - 2'b01 : + ex5_bh0_hist_q[0:1]; + assign ex5_bh1_wr_data[0:1] = (ex5_bh1_inc == 1'b1) ? ex5_bh1_hist_q[0:1] + 2'b01 : + (ex5_bh1_dec == 1'b1) ? ex5_bh1_hist_q[0:1] - 2'b01 : + ex5_bh1_hist_q[0:1]; + assign ex5_bh2_wr_data = ex5_br_taken_q; + + assign ex5_bh0_wr_en = ex5_val_q == 1'b1 & ex5_bh_update_q == 1'b1 & ex5_bh2_hist_q[0] == 1'b0; + assign ex5_bh1_wr_en = ex5_val_q == 1'b1 & ex5_bh_update_q == 1'b1 & ex5_bh2_hist_q[0] == 1'b1; + assign ex5_bh2_wr_en = ex5_val_q == 1'b1 & ex5_bh_update_q == 1'b1; +*/ + + assign ex5_bh_wr_act[0] = ex5_ifar_q[60:61] == 2'b00; + assign ex5_bh_wr_act[1] = ex5_ifar_q[60:61] == 2'b01; + assign ex5_bh_wr_act[2] = ex5_ifar_q[60:61] == 2'b10; + assign ex5_bh_wr_act[3] = ex5_ifar_q[60:61] == 2'b11; + + assign ex5_bh0_dec = ex5_br_taken_q == 1'b0 & ex5_bh0_hist[0:1] != 2'b00 & ex5_bh2_hist_q[0] == 1'b0; + assign ex5_bh1_dec = ex5_br_taken_q == 1'b0 & ex5_bh1_hist[0:1] != 2'b00 & ex5_bh2_hist_q[0] == 1'b1; + assign ex5_bh2_dec = ex5_br_taken_q == 1'b0 & ex5_bh2_hist_q[0] != 1'b0; + + assign ex5_bh0_inc = ex5_br_taken_q == 1'b1 & ex5_bh0_hist[0:1] != 2'b11 & ex5_bh2_hist_q[0] == 1'b0; + assign ex5_bh1_inc = ex5_br_taken_q == 1'b1 & ex5_bh1_hist[0:1] != 2'b11 & ex5_bh2_hist_q[0] == 1'b1; + assign ex5_bh2_inc = ex5_br_taken_q == 1'b1 & ex5_bh2_hist_q[0] != 1'b1; + + assign bcache_bh0_wr_data[0:1] = (ex5_bh0_inc == 1'b1) ? ex5_bh0_hist[0:1] + 2'b01 : + (ex5_bh0_dec == 1'b1) ? ex5_bh0_hist[0:1] - 2'b01 : + ex5_bh0_hist[0:1]; + assign bcache_bh1_wr_data[0:1] = (ex5_bh1_inc == 1'b1) ? ex5_bh1_hist[0:1] + 2'b01 : + (ex5_bh1_dec == 1'b1) ? ex5_bh1_hist[0:1] - 2'b01 : + ex5_bh1_hist[0:1]; + assign ex5_bh2_wr_data = ex5_br_taken_q; + + assign ex5_bh0_wr_en = ex5_val_q == 1'b1 & ex5_bh_update_q == 1'b1 & ex5_bh2_hist_q[0] == 1'b0; + assign ex5_bh1_wr_en = ex5_val_q == 1'b1 & ex5_bh_update_q == 1'b1 & ex5_bh2_hist_q[0] == 1'b1; + assign ex5_bh2_wr_en = ex5_val_q == 1'b1 & ex5_bh_update_q == 1'b1; + + + //----------------------------------------------- + // recent branch history cache + //---------------------------------------------- + + assign ex5_bh0_hist = |(bcache_hit[0:7]) ? bcache_bh0_hist : ex5_bh0_hist_q; + assign ex5_bh1_hist = |(bcache_hit[0:7]) ? bcache_bh1_hist : ex5_bh1_hist_q; + + assign ex5_bh0_wr_data = bcache_bh0_wr_data; + assign ex5_bh1_wr_data = bcache_bh1_wr_data; + + assign bcache_wr_addr = {ex5_bh_ti0gs0_wr_addr, ex5_ifar_q[60:61]}; + + //branch cache: bht_index[0:9], bht0_hist[0:1], bht1_hist[0:1] + assign bcache_data_new[0:15] = {bcache_wr_addr[0:11], bcache_bh0_wr_data[0:1], bcache_bh1_wr_data[0:1]}; + + assign bcache_data0_d = bcache_shift[0] ? bcache_data1_q : + bcache_data0_q ; + + assign bcache_data1_d = bcache_shift[1] ? bcache_data2_q : + bcache_data1_q ; + + assign bcache_data2_d = bcache_shift[2] ? bcache_data3_q : + bcache_data2_q ; + + assign bcache_data3_d = bcache_shift[3] ? bcache_data4_q : + bcache_data3_q ; + + assign bcache_data4_d = bcache_shift[4] ? bcache_data5_q : + bcache_data4_q ; + + assign bcache_data5_d = bcache_shift[5] ? bcache_data6_q : + bcache_data5_q ; + + assign bcache_data6_d = bcache_shift[6] ? bcache_data7_q : + bcache_data6_q ; + + assign bcache_data7_d = bcache_shift[7] ? bcache_data_new : + bcache_data7_q ; + + + assign bcache_hit[0] = ex5_val_q & ex5_bh_update_q & (bcache_data0_q[0:11] == bcache_data_new[0:11]); + assign bcache_hit[1] = ex5_val_q & ex5_bh_update_q & (bcache_data1_q[0:11] == bcache_data_new[0:11]); + assign bcache_hit[2] = ex5_val_q & ex5_bh_update_q & (bcache_data2_q[0:11] == bcache_data_new[0:11]); + assign bcache_hit[3] = ex5_val_q & ex5_bh_update_q & (bcache_data3_q[0:11] == bcache_data_new[0:11]); + assign bcache_hit[4] = ex5_val_q & ex5_bh_update_q & (bcache_data4_q[0:11] == bcache_data_new[0:11]); + assign bcache_hit[5] = ex5_val_q & ex5_bh_update_q & (bcache_data5_q[0:11] == bcache_data_new[0:11]); + assign bcache_hit[6] = ex5_val_q & ex5_bh_update_q & (bcache_data6_q[0:11] == bcache_data_new[0:11]); + assign bcache_hit[7] = ex5_val_q & ex5_bh_update_q & (bcache_data7_q[0:11] == bcache_data_new[0:11]); + + assign bcache_shift[0] = ex5_val_q & ex5_bh_update_q & ~(|(bcache_hit[1:7])); + assign bcache_shift[1] = ex5_val_q & ex5_bh_update_q & ~(|(bcache_hit[2:7])); + assign bcache_shift[2] = ex5_val_q & ex5_bh_update_q & ~(|(bcache_hit[3:7])); + assign bcache_shift[3] = ex5_val_q & ex5_bh_update_q & ~(|(bcache_hit[4:7])); + assign bcache_shift[4] = ex5_val_q & ex5_bh_update_q & ~(|(bcache_hit[5:7])); + assign bcache_shift[5] = ex5_val_q & ex5_bh_update_q & ~(|(bcache_hit[6:7])); + assign bcache_shift[6] = ex5_val_q & ex5_bh_update_q & ~( bcache_hit[7] ); + assign bcache_shift[7] = ex5_val_q & ex5_bh_update_q; + + assign bcache_bh0_hist = bcache_hit[0] ? bcache_data0_q[12:13] : + bcache_hit[1] ? bcache_data1_q[12:13] : + bcache_hit[2] ? bcache_data2_q[12:13] : + bcache_hit[3] ? bcache_data3_q[12:13] : + bcache_hit[4] ? bcache_data4_q[12:13] : + bcache_hit[5] ? bcache_data5_q[12:13] : + bcache_hit[6] ? bcache_data6_q[12:13] : + bcache_hit[7] ? bcache_data7_q[12:13] : + 2'b00 ; + + assign bcache_bh1_hist = bcache_hit[0] ? bcache_data0_q[14:15] : + bcache_hit[1] ? bcache_data1_q[14:15] : + bcache_hit[2] ? bcache_data2_q[14:15] : + bcache_hit[3] ? bcache_data3_q[14:15] : + bcache_hit[4] ? bcache_data4_q[14:15] : + bcache_hit[5] ? bcache_data5_q[14:15] : + bcache_hit[6] ? bcache_data6_q[14:15] : + bcache_hit[7] ? bcache_data7_q[14:15] : + 2'b00 ; + + + //----------------------------------------------- + // update global history + //----------------------------------------------- + + assign gshare_shift0_d[0:4] = (ex5_repair & cp_gs_count_d[0:1] == 2'b00) ? 5'b10000 : + (ex5_repair & cp_gs_count_d[0:1] == 2'b01) ? 5'b01000 : + (ex5_repair & cp_gs_count_d[0:1] == 2'b10) ? 5'b00100 : + (ex5_repair & cp_gs_count_d[0:1] == 2'b11) ? 5'b00010 : + (br_iu_redirect_q & br_iu_gshare_q[16:17] == 2'b00) ? 5'b10000 : + (br_iu_redirect_q & br_iu_gshare_q[16:17] == 2'b01) ? 5'b01000 : + (br_iu_redirect_q & br_iu_gshare_q[16:17] == 2'b10) ? 5'b00100 : + (br_iu_redirect_q & br_iu_gshare_q[16:17] == 2'b11) ? 5'b00010 : + (iu3_val_q[0]) ? 5'b10000 : + gshare_shift0_q[0:4]; + + assign gshare_shift1[0:4] = ((iu3_val_q[0] & iu3_bh_update[0]) == 1'b1) ? {1'b0, gshare_shift0_q[0:3]} : + gshare_shift0_q[0:4]; + assign gshare_shift2[0:4] = ((iu3_val_q[1] & iu3_bh_update[1]) == 1'b1) ? {1'b0, gshare_shift1[0:3]} : + gshare_shift1[0:4]; + assign gshare_shift3[0:4] = ((iu3_val_q[2] & iu3_bh_update[2]) == 1'b1) ? {1'b0, gshare_shift2[0:3]} : + gshare_shift2[0:4]; + assign gshare_shift4[0:4] = ((iu3_val_q[3] & iu3_bh_update[3]) == 1'b1) ? {1'b0, gshare_shift3[0:3]} : + gshare_shift3[0:4]; + + assign gshare_shift = ({5{~iu3_flush}} & gshare_shift4); + assign gshare_taken = |(iu3_val_q[0:3] & iu3_bh_update[0:3] & iu3_br_pred[0:3]); + + + //need to make pipeline gshares the NEXT CYCLE value to give me a pre-shifted restore point (iu3 uses iu2 to assume shift) + //taken branches per fetch group + assign gshare_d[0:2] = (ex5_repair) ? cp_gshare_d[0:2] : + (br_iu_redirect_q) ? br_iu_gshare_q[0:2] : + (iu3_redirect) ? ({iu3_pr_val_q, iu2_gshare_q[1:2]}) : + (iu2_redirect) ? ({1'b1, iu1_gshare_q[1:2]}) : + (iu0_val) ? ({1'b0, gshare_q[0:1]}) : + gshare_q[0:2]; + + //taken branches + assign gshare_d[3:9] = (ex5_repair == 1'b1) ? cp_gshare_d[3:9] : + (br_iu_redirect_q == 1'b1) ? br_iu_gshare_q[3:9] : + (iu3_redirect) ? ({iu2_gshare_q[3:9]}) : + (iu2_redirect) ? ({iu1_gshare_q[3:9]}) : + ((iu0_val) & (iu3_gs_count_next[0:1] == 2'b11)) ? ({gshare_q[2], 2'b00, gshare_q[3:6]}) : + ((iu0_val) & (iu3_gs_count_next[0:1] == 2'b10)) ? ({gshare_q[2], 1'b0, gshare_q[3:7]}) : + ((iu0_val) & (iu3_gs_count_next[0:1] == 2'b01)) ? ({gshare_q[2], gshare_q[3:8]}) : + ((iu0_val) & (iu3_gs_count_next[0:1] == 2'b00)) ? ({ gshare_q[3:9]}) : + gshare_q[3:9]; + + + + + //branches per fetch group + assign iu3_gs_count_next[0:1] = (iu3_gs_pos[2]) ? iu3_gs_count[0:1] : gshare_q[14:15]; + + assign iu3_gs_count[0:1] = (gshare_shift[4] == 1'b1) ? 2'b11 : + (gshare_shift[3] == 1'b1) ? 2'b11 : + (gshare_shift[2] == 1'b1) ? 2'b10 : + (gshare_shift[1] == 1'b1) ? 2'b01 : + 2'b00 ; + +//if a CURRENT instruction is in a given position, the OLD/RECOVERY point is pushed forward by that amount + assign iu3_gs_counts[0:1] = (iu3_gs_pos[0]) ? (gshare_q[12:13]) : + (iu3_gs_pos[1]) ? (gshare_q[14:15]) : + (iu3_gs_pos[2]) ? (gshare_q[10:11]) : + 2'b00 ; + + assign iu3_gs_counts[2:3] = (iu3_gs_pos[0]) ? (gshare_q[14:15]) : + (iu3_gs_pos[1]) ? (gshare_q[10:11]) : + (iu3_gs_pos[2]) ? (gshare_q[12:13]) : + 2'b00 ; + + assign iu3_gs_counts[4:5] = (iu3_gs_pos[0]) ? (gshare_q[10:11]) : + (iu3_gs_pos[1]) ? (gshare_q[12:13]) : + (iu3_gs_pos[2]) ? (gshare_q[14:15]) : + 2'b00 ; + + + //track position of current instruction in gshare history + assign iu1_gs_pos_d[0:2] = (iu0_val) ? 3'b100 : + 3'b000 ; + assign iu2_gs_pos_d[0:2] = (iu0_val) ? ({1'b0, iu1_gs_pos_q[0:1]}) : + iu1_gs_pos_q[0:2]; + assign iu3_gs_pos_d[0:2] = (iu2_redirect) ? 3'b100 : + (iu0_val) ? ({1'b0, iu2_gs_pos_q[0:1]}) : + iu2_gs_pos_q[0:2]; + + assign iu3_gs_pos[0:2] = iu3_gs_pos_q[0:2] & {3{iu3_val_q[0] & ~iu3_flush}}; + + assign gshare_d[10:15] = (ex5_repair) ? cp_gshare_d[10:15] : + (br_iu_redirect_q) ? br_iu_gshare_q[10:15] : + (iu3_redirect & iu3_gs_pos[0]) ? ({iu3_gs_count[0:1], gshare_q[12:15]}) : + (iu3_redirect & iu3_gs_pos[1]) ? ({iu3_gs_count[0:1], gshare_q[14:15], gshare_q[10:11]}) : + (iu3_redirect & iu3_gs_pos[2]) ? ({iu3_gs_count[0:1], gshare_q[10:13]}) : + (iu2_redirect & iu3_gs_pos[1]) ? ({gshare_q[10:11], iu3_gs_count[0:1], gshare_q[14:15]}) : + (iu2_redirect & iu3_gs_pos[2]) ? ({gshare_q[12:13], iu3_gs_count[0:1], gshare_q[10:11]}) : + (iu2_redirect & iu2_gs_pos_q[0]) ? ({gshare_q[10:15]}) : + (iu2_redirect & iu2_gs_pos_q[1]) ? ({gshare_q[12:15], gshare_q[10:11]}) : + (iu0_val & iu3_gs_pos[0]) ? ({gshare_q[14:15], iu3_gs_count[0:1], gshare_q[12:13]}) : + (iu0_val & iu3_gs_pos[1]) ? ({gshare_q[14:15], gshare_q[10:11], iu3_gs_count[0:1]}) : + (iu0_val & iu3_gs_pos[2]) ? ({iu3_gs_count[0:1], gshare_q[10:13]}) : + (iu3_gs_pos[0]) ? ({iu3_gs_count[0:1], gshare_q[12:15]}) : + (iu3_gs_pos[1]) ? ({gshare_q[10:11], iu3_gs_count[0:1], gshare_q[14:15]}) : + (iu3_gs_pos[2]) ? ({gshare_q[10:13], iu3_gs_count[0:1]}) : + (iu0_val) ? ({gshare_q[14:15], gshare_q[10:13]}) : + gshare_q[10:15]; + + + + //replace iu3_gshare[10:11] per instruction with the following counts for outgoing instructions. + assign iu3_gs_count0[0:1] = (gshare_shift1[1] == 1'b1) ? 2'b01 : + 2'b00 ; + + assign iu3_gs_count1[0:1] = (gshare_shift2[2] == 1'b1) ? 2'b10 : + (gshare_shift2[1] == 1'b1) ? 2'b01 : + 2'b00 ; + + assign iu3_gs_count2[0:1] = (gshare_shift3[3] == 1'b1) ? 2'b11 : + (gshare_shift3[2] == 1'b1) ? 2'b10 : + (gshare_shift3[1] == 1'b1) ? 2'b01 : + 2'b00 ; + + assign iu3_gs_count3[0:1] = (gshare_shift4[4] == 1'b1) ? 2'b11 : + (gshare_shift4[3] == 1'b1) ? 2'b11 : + (gshare_shift4[2] == 1'b1) ? 2'b10 : + (gshare_shift4[1] == 1'b1) ? 2'b01 : + 2'b00 ; + + + + + assign gshare_act[0] = tiup; + + + //completion time repair + assign cp_gshare_shift = ex5_val_q & ex5_bh_update_q; + assign cp_gshare_taken = ex5_val_q & ex5_br_taken_q; + + assign cp_gshare_d[0:2] = (cp_gs_group) ? ({cp_gs_taken, cp_gshare_q[0:1]}) : + cp_gshare_q[0:2]; + + assign cp_gshare_d[3:9] = (cp_gs_group & cp_gshare_q[14:15] == 2'b11) ? ({cp_gshare_q[2], 2'b00, cp_gshare_q[6:9]}) : + (cp_gs_group & cp_gshare_q[14:15] == 2'b10) ? ({cp_gshare_q[2], 1'b0 , cp_gshare_q[5:9]}) : + (cp_gs_group & cp_gshare_q[14:15] == 2'b01) ? ({cp_gshare_q[2] , cp_gshare_q[4:9]}) : + (cp_gs_group & cp_gshare_q[14:15] == 2'b00) ? ({ cp_gshare_q[3:9]}) : + cp_gshare_q[3:9] ; + + assign cp_gshare_d[10:15] = (cp_gs_group) ? ({cp_gs_count[0:1], cp_gshare_q[10:13]}) : + cp_gshare_q[10:15]; + + assign cp_gs_group = cp_gshare_taken | ex5_group_q; + + assign cp_gs_count[0:1] = (cp_gs_count_q[0:1] == 2'b11) ? 2'b11 : + (cp_gshare_shift) ? cp_gs_count_q[0:1] + 2'b01 : + cp_gs_count_q[0:1]; + + assign cp_gs_count_d[0:1] = (cp_gs_group) ? 2'b00 : + cp_gs_count[0:1]; + + assign cp_gs_taken = cp_gshare_taken | cp_gs_taken_q; + + assign cp_gs_taken_d = (cp_gs_group) ? 1'b0 : + cp_gs_taken; + + + + //----------------------------------------------- + // rotate branch history to match instructions + //----------------------------------------------- + + assign iu2_0_bh0_hist = (ic_bp_iu2_ifar[60:61] == 2'b11) ? iu2_3_bh0_rd_data[0:1] : + (ic_bp_iu2_ifar[60:61] == 2'b10) ? iu2_2_bh0_rd_data[0:1] : + (ic_bp_iu2_ifar[60:61] == 2'b01) ? iu2_1_bh0_rd_data[0:1] : + iu2_0_bh0_rd_data[0:1]; + assign iu2_1_bh0_hist = (ic_bp_iu2_ifar[60:61] == 2'b10) ? iu2_3_bh0_rd_data[0:1] : + (ic_bp_iu2_ifar[60:61] == 2'b01) ? iu2_2_bh0_rd_data[0:1] : + iu2_1_bh0_rd_data[0:1]; + assign iu2_2_bh0_hist = (ic_bp_iu2_ifar[60:61] == 2'b01) ? iu2_3_bh0_rd_data[0:1] : + iu2_2_bh0_rd_data[0:1]; + assign iu2_3_bh0_hist = iu2_3_bh0_rd_data[0:1]; + + assign iu2_0_bh1_hist = (ic_bp_iu2_ifar[60:61] == 2'b11) ? iu2_3_bh1_rd_data[0:1] : + (ic_bp_iu2_ifar[60:61] == 2'b10) ? iu2_2_bh1_rd_data[0:1] : + (ic_bp_iu2_ifar[60:61] == 2'b01) ? iu2_1_bh1_rd_data[0:1] : + iu2_0_bh1_rd_data[0:1]; + assign iu2_1_bh1_hist = (ic_bp_iu2_ifar[60:61] == 2'b10) ? iu2_3_bh1_rd_data[0:1] : + (ic_bp_iu2_ifar[60:61] == 2'b01) ? iu2_2_bh1_rd_data[0:1] : + iu2_1_bh1_rd_data[0:1]; + assign iu2_2_bh1_hist = (ic_bp_iu2_ifar[60:61] == 2'b01) ? iu2_3_bh1_rd_data[0:1] : + iu2_2_bh1_rd_data[0:1]; + assign iu2_3_bh1_hist = iu2_3_bh1_rd_data[0:1]; + + assign iu2_0_bh2_hist = (ic_bp_iu2_ifar[60:61] == 2'b11) ? iu2_3_bh2_rd_data : + (ic_bp_iu2_ifar[60:61] == 2'b10) ? iu2_2_bh2_rd_data : + (ic_bp_iu2_ifar[60:61] == 2'b01) ? iu2_1_bh2_rd_data : + iu2_0_bh2_rd_data; + assign iu2_1_bh2_hist = (ic_bp_iu2_ifar[60:61] == 2'b10) ? iu2_3_bh2_rd_data : + (ic_bp_iu2_ifar[60:61] == 2'b01) ? iu2_2_bh2_rd_data : + iu2_1_bh2_rd_data; + assign iu2_2_bh2_hist = (ic_bp_iu2_ifar[60:61] == 2'b01) ? iu2_3_bh2_rd_data : + iu2_2_bh2_rd_data; + assign iu2_3_bh2_hist = iu2_3_bh2_rd_data; + + //----------------------------------------------- + // bht selection + //----------------------------------------------- + + assign iu2_0_bh_pred = (iu2_0_bh0_hist[0] & iu2_0_bh2_hist == 1'b0) | (iu2_0_bh1_hist[0] & iu2_0_bh2_hist == 1'b1); + + assign iu2_1_bh_pred = (iu2_1_bh0_hist[0] & iu2_1_bh2_hist == 1'b0) | (iu2_1_bh1_hist[0] & iu2_1_bh2_hist == 1'b1); + + assign iu2_2_bh_pred = (iu2_2_bh0_hist[0] & iu2_2_bh2_hist == 1'b0) | (iu2_2_bh1_hist[0] & iu2_2_bh2_hist == 1'b1); + + assign iu2_3_bh_pred = (iu2_3_bh0_hist[0] & iu2_3_bh2_hist == 1'b0) | (iu2_3_bh1_hist[0] & iu2_3_bh2_hist == 1'b1); + + //----------------------------------------------- + // predict branches + //----------------------------------------------- + + assign iu2_uc[0:3] = ({ic_bp_iu2_0_instr[33], ic_bp_iu2_1_instr[33], ic_bp_iu2_2_instr[33], ic_bp_iu2_3_instr[33]}) & (~({ic_bp_iu2_0_instr[32], ic_bp_iu2_1_instr[32], ic_bp_iu2_2_instr[32], ic_bp_iu2_3_instr[32]})); + + assign iu2_fuse[0:3] = ({4{fuse_en}} & ({ic_bp_iu2_0_instr[34], ic_bp_iu2_1_instr[34], ic_bp_iu2_2_instr[34], ic_bp_iu2_3_instr[34]}) & + (~{ic_bp_iu2_0_instr[32], ic_bp_iu2_1_instr[32], ic_bp_iu2_2_instr[32], ic_bp_iu2_3_instr[32]})); + + assign iu2_br_val[0:3] = {ic_bp_iu2_0_instr[32], ic_bp_iu2_1_instr[32], ic_bp_iu2_2_instr[32], ic_bp_iu2_3_instr[32]}; + assign iu2_br_hard[0:3] = {ic_bp_iu2_0_instr[33], ic_bp_iu2_1_instr[33], ic_bp_iu2_2_instr[33], ic_bp_iu2_3_instr[33]}; + assign iu2_hint_val[0:3] = {ic_bp_iu2_0_instr[34], ic_bp_iu2_1_instr[34], ic_bp_iu2_2_instr[34], ic_bp_iu2_3_instr[34]}; + assign iu2_hint[0:3] = {ic_bp_iu2_0_instr[35], ic_bp_iu2_1_instr[35], ic_bp_iu2_2_instr[35], ic_bp_iu2_3_instr[35]}; + + assign iu2_bh_pred[0:3] = {iu2_0_bh_pred, iu2_1_bh_pred, iu2_2_bh_pred, iu2_3_bh_pred}; + + assign iu2_br_dynamic[0:3] = ({4{bp_dy_en}} & ~(iu2_br_hard[0:3] | iu2_hint_val[0:3])); + assign iu2_br_static[0:3] = ({4{bp_st_en & ~bp_dy_en}} & ~(iu2_br_hard[0:3] | iu2_hint_val[0:3])); + + assign iu2_br_pred[0:3] = ic_bp_iu2_val[0:3] & iu2_br_val[0:3] & (iu2_br_hard[0:3] | (iu2_hint_val[0:3] & iu2_hint[0:3]) | (iu2_br_dynamic[0:3] & iu2_bh_pred[0:3]) | (iu2_br_static[0:3])); + + assign iu2_bh_update[0:3] = iu2_br_val[0:3] & iu2_br_dynamic[0:3]; + + //----------------------------------------------- + // prioritize branch instructions + //----------------------------------------------- + + assign iu2_instr_pri[0:33] = (iu2_br_pred[0] == 1'b1) ? ic_bp_iu2_0_instr[0:33] : + (iu2_br_pred[1] == 1'b1) ? ic_bp_iu2_1_instr[0:33] : + (iu2_br_pred[2] == 1'b1) ? ic_bp_iu2_2_instr[0:33] : + ic_bp_iu2_3_instr[0:33]; + + assign iu3_ifar_pri_d[60:61] = (iu2_br_pred[0] == 1'b1) ? ic_bp_iu2_ifar[60:61] : + (iu2_br_pred[1] == 1'b1) ? ic_bp_iu2_ifar[60:61] + 2'b01 : + (iu2_br_pred[2] == 1'b1) ? ic_bp_iu2_ifar[60:61] + 2'b10 : + ic_bp_iu2_ifar[60:61] + 2'b11; + + assign iu3_bclr_d = (iu2_br_pred[0] == 1'b1) ? ic_bp_iu2_0_instr[0:5] == 6'b010011 & ic_bp_iu2_0_instr[21:30] == 10'b0000010000 : + (iu2_br_pred[1] == 1'b1) ? ic_bp_iu2_1_instr[0:5] == 6'b010011 & ic_bp_iu2_1_instr[21:30] == 10'b0000010000 : + (iu2_br_pred[2] == 1'b1) ? ic_bp_iu2_2_instr[0:5] == 6'b010011 & ic_bp_iu2_2_instr[21:30] == 10'b0000010000 : + ic_bp_iu2_3_instr[0:5] == 6'b010011 & ic_bp_iu2_3_instr[21:30] == 10'b0000010000; + + assign iu3_bcctr_d = (iu2_br_pred[0] == 1'b1) ? (ic_bp_iu2_0_instr[0:5] == 6'b010011 & ic_bp_iu2_0_instr[21:30] == 10'b1000110000) | (ic_bp_iu2_0_instr[0:5] == 6'b010011 & ic_bp_iu2_0_instr[21:30] == 10'b1000010000) : //bctar + (iu2_br_pred[1] == 1'b1) ? (ic_bp_iu2_1_instr[0:5] == 6'b010011 & ic_bp_iu2_1_instr[21:30] == 10'b1000110000) | (ic_bp_iu2_1_instr[0:5] == 6'b010011 & ic_bp_iu2_1_instr[21:30] == 10'b1000010000) : //bctar + (iu2_br_pred[2] == 1'b1) ? (ic_bp_iu2_2_instr[0:5] == 6'b010011 & ic_bp_iu2_2_instr[21:30] == 10'b1000110000) | (ic_bp_iu2_2_instr[0:5] == 6'b010011 & ic_bp_iu2_2_instr[21:30] == 10'b1000010000) : //bctar + (ic_bp_iu2_3_instr[0:5] == 6'b010011 & ic_bp_iu2_3_instr[21:30] == 10'b1000110000) | (ic_bp_iu2_3_instr[0:5] == 6'b010011 & ic_bp_iu2_3_instr[21:30] == 10'b1000010000); //bctar + + //----------------------------------------------- + // decode priority branch instruction + //----------------------------------------------- + + assign iu3_b_d = iu2_instr_pri[33]; + assign iu3_tar_d[6:29] = iu2_instr_pri[6:29]; + + generate + begin : xhdl1 + genvar i; + for (i = 62 - `EFF_IFAR_WIDTH; i <= 61; i = i + 1) + begin : sign_extend + if (i < 48) + begin : bd0 + assign iu3_bd[i] = iu3_tar_q[16]; + end + if (i > 47) + begin : bd1 + assign iu3_bd[i] = iu3_tar_q[i - 32]; + end + if (i < 38) + begin : li0 + assign iu3_li[i] = iu3_tar_q[6]; + end + if (i > 37) + begin : li1 + assign iu3_li[i] = iu3_tar_q[i - 32]; + end +end +end +endgenerate + +assign iu3_bh_d[0:1] = iu2_instr_pri[19:20]; +assign iu3_lk_d = iu2_instr_pri[31]; +assign iu3_aa_d = iu2_instr_pri[30]; + +assign iu3_pr_val_d = |(iu2_br_pred[0:3]) & (~iu2_flush) & (~ic_bp_iu2_error[0]); + +// bcl 20,31,$+4 is special case. not a subroutine call, used to get next instruction address, should not be placed on link stack. +assign iu3_opcode_d[0:5] = iu2_instr_pri[0:5]; +assign iu3_bo_d[6:10] = iu2_instr_pri[6:10]; +assign iu3_bi_d[11:15] = iu2_instr_pri[11:15]; + +assign iu3_getNIA = iu3_opcode_q[0:5] == 6'b010000 & iu3_bo_q[6:10] == 5'b10100 & iu3_bi_q[11:15] == 5'b11111 & iu3_bd[62-`EFF_IFAR_WIDTH:61] == value_1[32-`EFF_IFAR_WIDTH:31] & iu3_aa_q == 1'b0 & iu3_lk_q == 1'b1; + +//----------------------------------------------- +// calculate branch target address +//----------------------------------------------- + +assign iu3_abs[62 - `EFF_IFAR_WIDTH:61] = (iu3_b_q == 1'b1) ? iu3_li[62 - `EFF_IFAR_WIDTH:61] : + iu3_bd[62 - `EFF_IFAR_WIDTH:61]; + +assign iu3_off[62 - `EFF_IFAR_WIDTH:61] = iu3_abs[62 - `EFF_IFAR_WIDTH:61] + ({iu3_ifar_q[62 - `EFF_IFAR_WIDTH:59], iu3_ifar_pri_q[60:61]}); + +assign iu3_bta[62 - `EFF_IFAR_WIDTH:61] = (iu3_aa_q == 1'b1) ? iu3_abs[62 - `EFF_IFAR_WIDTH:61] : + iu3_off[62 - `EFF_IFAR_WIDTH:61]; + +//----------------------------------------------- +// forward validated instructions +//----------------------------------------------- + +// Using xori 0,0,0 (xnop) when erat error +assign xnop[0:31] = {6'b011010, 26'b0}; + +assign iu3_act = ic_bp_iu2_val[0]; +assign iu3_instr_act[0:3] = ic_bp_iu2_val[0:3]; + +assign iu3_ifar_d[62 - `EFF_IFAR_WIDTH:61] = ic_bp_iu2_ifar[62 - `EFF_IFAR_WIDTH:61]; + +assign iu3_val_d[0] = (~iu2_flush) & ic_bp_iu2_val[0]; +assign iu3_val_d[1] = (~iu2_flush) & ic_bp_iu2_val[1] & (ic_bp_iu2_error[0] | ((~iu2_br_pred[0]))); +assign iu3_val_d[2] = (~iu2_flush) & ic_bp_iu2_val[2] & (ic_bp_iu2_error[0] | ((~iu2_br_pred[0]) & (~iu2_br_pred[1]))); +assign iu3_val_d[3] = (~iu2_flush) & ic_bp_iu2_val[3] & (ic_bp_iu2_error[0] | ((~iu2_br_pred[0]) & (~iu2_br_pred[1]) & (~iu2_br_pred[2]))); + +assign iu3_0_instr_d[0:31] = (ic_bp_iu2_error[0] == 1'b0) ? ic_bp_iu2_0_instr[0:31] : + xnop[0:31]; +assign iu3_1_instr_d[0:31] = (ic_bp_iu2_error[0] == 1'b0) ? ic_bp_iu2_1_instr[0:31] : + xnop[0:31]; +assign iu3_2_instr_d[0:31] = (ic_bp_iu2_error[0] == 1'b0) ? ic_bp_iu2_2_instr[0:31] : + xnop[0:31]; +assign iu3_3_instr_d[0:31] = (ic_bp_iu2_error[0] == 1'b0) ? ic_bp_iu2_3_instr[0:31] : + xnop[0:31]; + +assign iu3_0_instr_d[32] = iu2_br_pred[0] & (~ic_bp_iu2_error[0]); +assign iu3_1_instr_d[32] = iu2_br_pred[1] & (~ic_bp_iu2_error[0]); +assign iu3_2_instr_d[32] = iu2_br_pred[2] & (~ic_bp_iu2_error[0]); +assign iu3_3_instr_d[32] = iu2_br_pred[3] & (~ic_bp_iu2_error[0]); + +assign iu3_0_instr_d[33] = iu2_bh_update[0] & (~ic_bp_iu2_error[0]); +assign iu3_1_instr_d[33] = iu2_bh_update[1] & (~ic_bp_iu2_error[0]); +assign iu3_2_instr_d[33] = iu2_bh_update[2] & (~ic_bp_iu2_error[0]); +assign iu3_3_instr_d[33] = iu2_bh_update[3] & (~ic_bp_iu2_error[0]); + +assign iu3_0_instr_d[34:35] = iu2_0_bh0_hist; +assign iu3_1_instr_d[34:35] = iu2_1_bh0_hist; +assign iu3_2_instr_d[34:35] = iu2_2_bh0_hist; +assign iu3_3_instr_d[34:35] = iu2_3_bh0_hist; + +assign iu3_0_instr_d[36:37] = iu2_0_bh1_hist; +assign iu3_1_instr_d[36:37] = iu2_1_bh1_hist; +assign iu3_2_instr_d[36:37] = iu2_2_bh1_hist; +assign iu3_3_instr_d[36:37] = iu2_3_bh1_hist; + +assign iu3_0_instr_d[38] = iu2_0_bh2_hist; +assign iu3_1_instr_d[38] = iu2_1_bh2_hist; +assign iu3_2_instr_d[38] = iu2_2_bh2_hist; +assign iu3_3_instr_d[38] = iu2_3_bh2_hist; + +assign iu3_0_instr_d[39] = 1'b0; +assign iu3_1_instr_d[39] = 1'b0; +assign iu3_2_instr_d[39] = 1'b0; +assign iu3_3_instr_d[39] = 1'b0; + +assign iu3_0_instr_d[40:49] = iu2_gshare_q[0:9]; +assign iu3_1_instr_d[40:49] = iu2_gshare_q[0:9]; +assign iu3_2_instr_d[40:49] = iu2_gshare_q[0:9]; +assign iu3_3_instr_d[40:49] = iu2_gshare_q[0:9]; + +assign iu3_0_instr_d[50:52] = iu2_ls_ptr[0:2]; +assign iu3_1_instr_d[50:52] = iu2_ls_ptr[0:2]; +assign iu3_2_instr_d[50:52] = iu2_ls_ptr[0:2]; +assign iu3_3_instr_d[50:52] = iu2_ls_ptr[0:2]; + +assign iu3_0_instr_d[53:55] = ic_bp_iu2_error[0:2]; +assign iu3_1_instr_d[53:55] = ic_bp_iu2_error[0:2]; +assign iu3_2_instr_d[53:55] = ic_bp_iu2_error[0:2]; +assign iu3_3_instr_d[53:55] = ic_bp_iu2_error[0:2]; + +assign iu3_0_instr_d[56] = (iu2_uc[0] | ic_bp_iu2_2ucode) & (~ic_bp_iu2_error[0]); +assign iu3_1_instr_d[56] = iu2_uc[1] & (~ic_bp_iu2_error[0]); +assign iu3_2_instr_d[56] = iu2_uc[2] & (~ic_bp_iu2_error[0]); +assign iu3_3_instr_d[56] = iu2_uc[3] & (~ic_bp_iu2_error[0]); + +assign iu3_0_instr_d[57] = iu2_fuse[0] & (~ic_bp_iu2_error[0]); +assign iu3_1_instr_d[57] = iu2_fuse[1] & (~ic_bp_iu2_error[0]); +assign iu3_2_instr_d[57] = iu2_fuse[2] & (~ic_bp_iu2_error[0]); +assign iu3_3_instr_d[57] = iu2_fuse[3] & (~ic_bp_iu2_error[0]); + +assign iu3_0_instr_d[58] = iu2_btb_entry[0]; +assign iu3_1_instr_d[58] = iu2_btb_entry[1]; +assign iu3_2_instr_d[58] = iu2_btb_entry[2]; +assign iu3_3_instr_d[58] = iu2_btb_entry[3]; + +assign iu3_0_instr_d[59] = ic_bp_iu2_2ucode; +assign iu3_1_instr_d[59] = ic_bp_iu2_2ucode; +assign iu3_2_instr_d[59] = ic_bp_iu2_2ucode; +assign iu3_3_instr_d[59] = ic_bp_iu2_2ucode; + +assign iu3_0_instr_d[60] = 1'b0; +assign iu3_1_instr_d[60] = 1'b0; +assign iu3_2_instr_d[60] = 1'b0; +assign iu3_3_instr_d[60] = 1'b0; + +assign iu3_br_pred[0:3] = {iu3_0_instr_q[32], iu3_1_instr_q[32], iu3_2_instr_q[32], iu3_3_instr_q[32]}; +assign iu3_bh_update[0:3] = {iu3_0_instr_q[33], iu3_1_instr_q[33], iu3_2_instr_q[33], iu3_3_instr_q[33]}; + +//----------------------------------------------- +// detect incoming flushes +//----------------------------------------------- + +assign iu1_flush = iu2_flush | iu2_redirect; + +assign iu2_flush = iu_flush_q | br_iu_redirect_q | ic_bp_iu2_flush | ic_bp_iu3_flush | iu3_redirect | iu4_redirect_q | ib_ic_iu4_redirect | uc_iu4_flush; + +assign iu3_flush = iu_flush_q | br_iu_redirect_q | ic_bp_iu3_flush | iu4_redirect_q | ib_ic_iu4_redirect | uc_iu4_flush; + +assign iu4_flush = iu_flush_q | br_iu_redirect_q | ib_ic_iu4_redirect | uc_iu4_flush; //it is possible to remove iu_flush from iu4_flush for timing but will have performance impact + +//----------------------------------------------- +// ex link stack pointers +//----------------------------------------------- + +//valid can be concurrent with flush +assign ex5_ls_push_d = ex5_val_d & ex5_br_taken_d & (~ex5_bclr_d) & ex5_lk_d & (~ex5_getNIA_d); +assign ex5_ls_pop_d = ex5_val_d & ex5_br_taken_d & ex5_bclr_d & ex5_bh_d[0:1] == 2'b00; + +assign ex6_ls_t0_ptr_d[0:7] = (ex5_ls_push_q == 1'b1 & ex5_ls_pop_q == 1'b0) ? {ex5_ls_ptr_q[7], ex5_ls_ptr_q[0:6]} : + (ex5_ls_push_q == 1'b0 & ex5_ls_pop_q == 1'b1) ? {ex5_ls_ptr_q[1:7], ex5_ls_ptr_q[0]} : + ex6_ls_t0_ptr_q[0:7]; + +assign ex6_ls_ptr_act = ex5_ls_push_q ^ ex5_ls_pop_q; +//----------------------------------------------- +// maintain link stack contents +//----------------------------------------------- + +assign ex5_ls_update = ex5_ls_push_q; + +assign ex5_nia[62 - `EFF_IFAR_WIDTH:61] = ex5_ifar_q[62-`EFF_IFAR_WIDTH:61] + value_1[32-`EFF_IFAR_WIDTH:31]; + +assign ex6_ls_t00_d[62 - `EFF_IFAR_WIDTH:61] = (ex5_ls_update == 1'b1) ? ex5_nia[62 - `EFF_IFAR_WIDTH:61] : + ex6_ls_t00_q[62 - `EFF_IFAR_WIDTH:61]; +assign ex6_ls_t01_d[62 - `EFF_IFAR_WIDTH:61] = (ex5_ls_update == 1'b1) ? ex5_nia[62 - `EFF_IFAR_WIDTH:61] : + ex6_ls_t01_q[62 - `EFF_IFAR_WIDTH:61]; +assign ex6_ls_t02_d[62 - `EFF_IFAR_WIDTH:61] = (ex5_ls_update == 1'b1) ? ex5_nia[62 - `EFF_IFAR_WIDTH:61] : + ex6_ls_t02_q[62 - `EFF_IFAR_WIDTH:61]; +assign ex6_ls_t03_d[62 - `EFF_IFAR_WIDTH:61] = (ex5_ls_update == 1'b1) ? ex5_nia[62 - `EFF_IFAR_WIDTH:61] : + ex6_ls_t03_q[62 - `EFF_IFAR_WIDTH:61]; +assign ex6_ls_t04_d[62 - `EFF_IFAR_WIDTH:61] = (ex5_ls_update == 1'b1) ? ex5_nia[62 - `EFF_IFAR_WIDTH:61] : + ex6_ls_t04_q[62 - `EFF_IFAR_WIDTH:61]; +assign ex6_ls_t05_d[62 - `EFF_IFAR_WIDTH:61] = (ex5_ls_update == 1'b1) ? ex5_nia[62 - `EFF_IFAR_WIDTH:61] : + ex6_ls_t05_q[62 - `EFF_IFAR_WIDTH:61]; +assign ex6_ls_t06_d[62 - `EFF_IFAR_WIDTH:61] = (ex5_ls_update == 1'b1) ? ex5_nia[62 - `EFF_IFAR_WIDTH:61] : + ex6_ls_t06_q[62 - `EFF_IFAR_WIDTH:61]; +assign ex6_ls_t07_d[62 - `EFF_IFAR_WIDTH:61] = (ex5_ls_update == 1'b1) ? ex5_nia[62 - `EFF_IFAR_WIDTH:61] : + ex6_ls_t07_q[62 - `EFF_IFAR_WIDTH:61]; + +assign ex6_ls_t0_act[0:7] = (ex5_ls_update == 1'b1) ? ex6_ls_t0_ptr_d[0:7] : + 8'b00000000; + +//----------------------------------------------- +// iu link stack pointers +//----------------------------------------------- + +assign iu4_ls_push_d = iu3_pr_val_q & (~iu3_flush) & (~iu3_bclr_q) & iu3_lk_q & (~iu3_getNIA); +assign iu4_ls_pop_d = iu3_pr_val_q & (~iu3_flush) & iu3_bclr_q & iu3_bh_q[0:1] == 2'b00; + +assign ex5_repair = ex5_flush_q; + +assign iu5_ls_t0_ptr_d[0:7] = (ex5_repair == 1'b1) ? ex6_ls_t0_ptr_d[0:7] : + (br_iu_redirect_q == 1'b1) ? br_iu_ls_ptr_q[0:7] : + (iu4_ls_push_q == 1'b1 & iu4_ls_pop_q == 1'b0) ? {iu5_ls_t0_ptr_q[7], iu5_ls_t0_ptr_q[0:6]} : + (iu4_ls_push_q == 1'b0 & iu4_ls_pop_q == 1'b1) ? {iu5_ls_t0_ptr_q[1:7], iu5_ls_t0_ptr_q[0]} : + iu5_ls_t0_ptr_q[0:7]; + +assign iu5_ls_ptr_act[0] = br_iu_redirect_q | ex5_repair | (~iu4_flush); + +//----------------------------------------------- +// maintain link stack contents +//----------------------------------------------- + +assign iu4_ls_update = iu4_ls_push_q & (~iu4_flush); + +assign iu4_ifar_d[62 - `EFF_IFAR_WIDTH:61] = ({iu3_ifar_q[62 - `EFF_IFAR_WIDTH:59], iu3_ifar_pri_q[60:61]}); +assign iu4_act = iu3_pr_val_q & iu3_lk_q; + +assign iu4_nia[62 - `EFF_IFAR_WIDTH:61] = iu4_ifar_q[62 - `EFF_IFAR_WIDTH:61] + value_1[32-`EFF_IFAR_WIDTH:31]; + +assign iu5_ls_t00_d[62 - `EFF_IFAR_WIDTH:61] = (ex5_repair == 1'b1) ? ex6_ls_t00_d[62 - `EFF_IFAR_WIDTH:61] : + (br_iu_redirect_q == 1'b1 & br_iu_ls_update_q == 1'b1) ? br_iu_ls_data_q[62 - `EFF_IFAR_WIDTH:61] : + (iu4_ls_update == 1'b1) ? iu4_nia[62 - `EFF_IFAR_WIDTH:61] : + iu5_ls_t00_q[62 - `EFF_IFAR_WIDTH:61]; +assign iu5_ls_t01_d[62 - `EFF_IFAR_WIDTH:61] = (ex5_repair == 1'b1) ? ex6_ls_t01_d[62 - `EFF_IFAR_WIDTH:61] : + (br_iu_redirect_q == 1'b1 & br_iu_ls_update_q == 1'b1) ? br_iu_ls_data_q[62 - `EFF_IFAR_WIDTH:61] : + (iu4_ls_update == 1'b1) ? iu4_nia[62 - `EFF_IFAR_WIDTH:61] : + iu5_ls_t01_q[62 - `EFF_IFAR_WIDTH:61]; +assign iu5_ls_t02_d[62 - `EFF_IFAR_WIDTH:61] = (ex5_repair == 1'b1) ? ex6_ls_t02_d[62 - `EFF_IFAR_WIDTH:61] : + (br_iu_redirect_q == 1'b1 & br_iu_ls_update_q == 1'b1) ? br_iu_ls_data_q[62 - `EFF_IFAR_WIDTH:61] : + (iu4_ls_update == 1'b1) ? iu4_nia[62 - `EFF_IFAR_WIDTH:61] : + iu5_ls_t02_q[62 - `EFF_IFAR_WIDTH:61]; +assign iu5_ls_t03_d[62 - `EFF_IFAR_WIDTH:61] = (ex5_repair == 1'b1) ? ex6_ls_t03_d[62 - `EFF_IFAR_WIDTH:61] : + (br_iu_redirect_q == 1'b1 & br_iu_ls_update_q == 1'b1) ? br_iu_ls_data_q[62 - `EFF_IFAR_WIDTH:61] : + (iu4_ls_update == 1'b1) ? iu4_nia[62 - `EFF_IFAR_WIDTH:61] : + iu5_ls_t03_q[62 - `EFF_IFAR_WIDTH:61]; +assign iu5_ls_t04_d[62 - `EFF_IFAR_WIDTH:61] = (ex5_repair == 1'b1) ? ex6_ls_t04_d[62 - `EFF_IFAR_WIDTH:61] : + (br_iu_redirect_q == 1'b1 & br_iu_ls_update_q == 1'b1) ? br_iu_ls_data_q[62 - `EFF_IFAR_WIDTH:61] : + (iu4_ls_update == 1'b1) ? iu4_nia[62 - `EFF_IFAR_WIDTH:61] : + iu5_ls_t04_q[62 - `EFF_IFAR_WIDTH:61]; +assign iu5_ls_t05_d[62 - `EFF_IFAR_WIDTH:61] = (ex5_repair == 1'b1) ? ex6_ls_t05_d[62 - `EFF_IFAR_WIDTH:61] : + (br_iu_redirect_q == 1'b1 & br_iu_ls_update_q == 1'b1) ? br_iu_ls_data_q[62 - `EFF_IFAR_WIDTH:61] : + (iu4_ls_update == 1'b1) ? iu4_nia[62 - `EFF_IFAR_WIDTH:61] : + iu5_ls_t05_q[62 - `EFF_IFAR_WIDTH:61]; +assign iu5_ls_t06_d[62 - `EFF_IFAR_WIDTH:61] = (ex5_repair == 1'b1) ? ex6_ls_t06_d[62 - `EFF_IFAR_WIDTH:61] : + (br_iu_redirect_q == 1'b1 & br_iu_ls_update_q == 1'b1) ? br_iu_ls_data_q[62 - `EFF_IFAR_WIDTH:61] : + (iu4_ls_update == 1'b1) ? iu4_nia[62 - `EFF_IFAR_WIDTH:61] : + iu5_ls_t06_q[62 - `EFF_IFAR_WIDTH:61]; +assign iu5_ls_t07_d[62 - `EFF_IFAR_WIDTH:61] = (ex5_repair == 1'b1) ? ex6_ls_t07_d[62 - `EFF_IFAR_WIDTH:61] : + (br_iu_redirect_q == 1'b1 & br_iu_ls_update_q == 1'b1) ? br_iu_ls_data_q[62 - `EFF_IFAR_WIDTH:61] : + (iu4_ls_update == 1'b1) ? iu4_nia[62 - `EFF_IFAR_WIDTH:61] : + iu5_ls_t07_q[62 - `EFF_IFAR_WIDTH:61]; + +assign iu5_ls_t0_act[0:7] = (ex5_repair == 1'b1) ? 8'b11111111 : + (iu4_ls_push_q == 1'b1 | (br_iu_redirect_q == 1'b1 & br_iu_ls_update_q == 1'b1)) ? iu5_ls_t0_ptr_d[0:7] : + 8'b00000000; + +//----------------------------------------------- +// mux out link address +//----------------------------------------------- + +assign iu2_lnk[62-`EFF_IFAR_WIDTH:61] = ({`EFF_IFAR_WIDTH{iu5_ls_t0_ptr_q[0]}} & iu5_ls_t00_q[62 - `EFF_IFAR_WIDTH:61]) | + ({`EFF_IFAR_WIDTH{iu5_ls_t0_ptr_q[1]}} & iu5_ls_t01_q[62 - `EFF_IFAR_WIDTH:61]) | + ({`EFF_IFAR_WIDTH{iu5_ls_t0_ptr_q[2]}} & iu5_ls_t02_q[62 - `EFF_IFAR_WIDTH:61]) | + ({`EFF_IFAR_WIDTH{iu5_ls_t0_ptr_q[3]}} & iu5_ls_t03_q[62 - `EFF_IFAR_WIDTH:61]) | + ({`EFF_IFAR_WIDTH{iu5_ls_t0_ptr_q[4]}} & iu5_ls_t04_q[62 - `EFF_IFAR_WIDTH:61]) | + ({`EFF_IFAR_WIDTH{iu5_ls_t0_ptr_q[5]}} & iu5_ls_t05_q[62 - `EFF_IFAR_WIDTH:61]) | + ({`EFF_IFAR_WIDTH{iu5_ls_t0_ptr_q[6]}} & iu5_ls_t06_q[62 - `EFF_IFAR_WIDTH:61]) | + ({`EFF_IFAR_WIDTH{iu5_ls_t0_ptr_q[7]}} & iu5_ls_t07_q[62 - `EFF_IFAR_WIDTH:61]); + +assign iu2_ls_ptr[0:2] = ({3{iu5_ls_t0_ptr_q[0]}} & 3'b000) | + ({3{iu5_ls_t0_ptr_q[1]}} & 3'b001) | + ({3{iu5_ls_t0_ptr_q[2]}} & 3'b010) | + ({3{iu5_ls_t0_ptr_q[3]}} & 3'b011) | + ({3{iu5_ls_t0_ptr_q[4]}} & 3'b100) | + ({3{iu5_ls_t0_ptr_q[5]}} & 3'b101) | + ({3{iu5_ls_t0_ptr_q[6]}} & 3'b110) | + ({3{iu5_ls_t0_ptr_q[7]}} & 3'b111) ; + + + +//----------------------------------------------- +// read btb for bcctr +//----------------------------------------------- + +//btb has READ gating to prevent r/w collisions, with external write thru. writes are never blocked, so its okay to read as often as we like +assign iu0_btb_rd_act = ic_bp_iu0_val; +assign iu0_btb_rd_addr[0:5] = ic_bp_iu0_ifar[54:59]; + +assign iu2_btb[62 - `EFF_IFAR_WIDTH:61] = iu2_btb_rd_data[0:`EFF_IFAR_WIDTH - 1]; +assign iu2_btb_tag[62 - `EFF_IFAR_WIDTH:61] = iu2_btb_rd_data[`EFF_IFAR_WIDTH:2 * `EFF_IFAR_WIDTH - 1]; +assign iu2_btb_link = iu2_btb_rd_data[2 * `EFF_IFAR_WIDTH]; +assign iu2_btb_hist[0:1] = iu2_btb_hist_q[0:1]; + +assign iu2_btb_entry[0] = ic_bp_iu2_ifar[62 - `EFF_IFAR_WIDTH:59] == iu2_btb_tag[62 - `EFF_IFAR_WIDTH:59] & iu2_btb_tag[60:61] == ic_bp_iu2_ifar[60:61]; +assign iu2_btb_entry[1] = ic_bp_iu2_ifar[62 - `EFF_IFAR_WIDTH:59] == iu2_btb_tag[62 - `EFF_IFAR_WIDTH:59] & iu2_btb_tag[60:61] == ic_bp_iu2_ifar[60:61] + 2'b01; +assign iu2_btb_entry[2] = ic_bp_iu2_ifar[62 - `EFF_IFAR_WIDTH:59] == iu2_btb_tag[62 - `EFF_IFAR_WIDTH:59] & iu2_btb_tag[60:61] == ic_bp_iu2_ifar[60:61] + 2'b10; +assign iu2_btb_entry[3] = ic_bp_iu2_ifar[62 - `EFF_IFAR_WIDTH:59] == iu2_btb_tag[62 - `EFF_IFAR_WIDTH:59] & iu2_btb_tag[60:61] == ic_bp_iu2_ifar[60:61] + 2'b11; + +//----------------------------------------------- +// read/write btb replacement counter +//----------------------------------------------- + +assign ex5_btb_repl_new[0:1] = ((ex5_btb_entry_q == 1'b0 & ex5_br_taken_q == 1'b1 & (ex5_btb_repl_cnt[0:1] == 2'b00 | ex5_bcctr_q == 1'b1 | (ex5_bclr_q == 1'b1 & ex5_bh_q[0:1] != 2'b00)))) ? 2'b01 : + (ex5_btb_entry_q == 1'b0 & ex5_br_taken_q == 1'b1 & ex5_btb_repl_cnt[0:1] != 2'b00) ? ex5_btb_repl_cnt[0:1] - 2'b01 : + (ex5_br_taken_q == 1'b1 & ex5_btb_hist[0] == 1'b1 & (ex5_bcctr_q == 1'b1 | (ex5_bclr_q == 1'b1 & ex5_bh_q[0:1] != 2'b00))) ? 2'b11 : + (ex5_br_taken_q == 1'b1 & ex5_btb_hist[0] == 1'b1 & ex5_btb_repl_cnt[0:1] != 2'b11) ? ex5_btb_repl_cnt[0:1] + 2'b01 : + ex5_btb_repl_cnt[0:1]; + +generate +begin : xhdl2 + genvar i; + for (i = 0; i <= 63; i = i + 1) + begin : repl_cnt + wire [54:59] id = i; + assign ex5_btb_repl_d[2 * i:2 * i + 1] = (ex5_ifar_q[54:59] == id) ? ex5_btb_repl_new[0:1] : + ex5_btb_repl_q[2 * i:2 * i + 1]; + assign ex5_btb_repl_out[i] = ex5_btb_repl_q[2 * i] & ex5_ifar_q[54:59] == id; + assign ex5_btb_repl_out[i + 64] = ex5_btb_repl_q[2 * i + 1] & ex5_ifar_q[54:59] == id; + end +end +endgenerate + +assign ex5_btb_repl_cnt[0:1] = {|(ex5_btb_repl_out[0:63]), |(ex5_btb_repl_out[64:127])}; + +//----------------------------------------------- +// read/write btb history +//----------------------------------------------- + +assign iu0_btb_hist_new[0:1] = (ex5_val_q == 1'b0 & ex5_btb_entry_q == 1'b1 & ex5_btb_hist[0:1] != 2'b00) ? ex5_btb_hist[0:1] - 2'b01 : + ((ex5_btb_entry_q == 1'b0 & ex5_br_taken_q == 1'b1 & (ex5_btb_repl_cnt[0:1] == 2'b00 | ex5_bcctr_q == 1'b1 | (ex5_bclr_q == 1'b1 & ex5_bh_q[0:1] != 2'b00)))) ? 2'b10 : + (ex5_br_taken_q == 1'b1 & ex5_btb_hist[0:1] != 2'b11) ? ex5_btb_hist[0:1] + 2'b01 : + (ex5_br_taken_q == 1'b0 & ex5_btb_hist[0:1] != 2'b00) ? ex5_btb_hist[0:1] - 2'b01 : + ex5_btb_hist[0:1]; + +generate + begin : xhdl3 + genvar i; + for (i = 0; i <= 63; i = i + 1) + begin : btb_hist + wire [54:59] id = i; + assign iu0_btb_hist_d[2 * i:2 * i + 1] = (ex5_ifar_q[54:59] == id) ? iu0_btb_hist_new[0:1] : + iu0_btb_hist_q[2 * i:2 * i + 1]; + assign iu0_btb_hist_out[i] = iu0_btb_hist_q[2 * i] & ic_bp_iu0_ifar[54:59] == id; + assign iu0_btb_hist_out[i + 64] = iu0_btb_hist_q[2 * i + 1] & ic_bp_iu0_ifar[54:59] == id; + assign ex5_btb_hist_out[i] = iu0_btb_hist_q[2 * i] & ex5_ifar_q[54:59] == id; + assign ex5_btb_hist_out[i + 64] = iu0_btb_hist_q[2 * i + 1] & ex5_ifar_q[54:59] == id; + end + end + endgenerate + + assign iu1_btb_hist_d[0:1] = {|(iu0_btb_hist_out[0:63]), |(iu0_btb_hist_out[64:127])}; + assign iu2_btb_hist_d[0:1] = iu1_btb_hist_q[0:1]; + + assign ex5_btb_hist[0:1] = {|(ex5_btb_hist_out[0:63]), |(ex5_btb_hist_out[64:127])}; + + assign iu0_btb_hist_act = (ex5_val_q == 1'b0 & ex5_btb_entry_q == 1'b1) | (ex5_val_q == 1'b1 & ((ex5_btb_entry_q == 1'b1) | (ex5_btb_entry_q == 1'b0 & ex5_br_taken_q & (ex5_btb_repl_cnt[0:1] == 2'b00 | ex5_bcctr_q == 1'b1 | (ex5_bclr_q == 1'b1 & ex5_bh_q[0:1] != 2'b00))))); + + //----------------------------------------------- + // write btb + //----------------------------------------------- + + //target + //branch to link + assign ex5_btb_wr_data[0:63] = {ex5_bta_q[62 - `EFF_IFAR_WIDTH:61], ex5_ifar_q[62 - `EFF_IFAR_WIDTH:61], (ex5_bclr_q & ex5_bh_q[0:1] == 2'b00), {(64-(2*`EFF_IFAR_WIDTH + 1)){1'b0}}}; //tag + + assign ex5_btb_wr_addr[0:5] = ex5_ifar_q[54:59]; + + assign ex5_btb_wr_act = (ex5_val_q == 1'b1 & ((ex5_btb_entry_q == 1'b1 & ex5_br_taken_q) | (ex5_btb_entry_q == 1'b0 & ex5_br_taken_q & (ex5_btb_repl_cnt[0:1] == 2'b00 | ex5_bcctr_q == 1'b1 | (ex5_bclr_q == 1'b1 & ex5_bh_q[0:1] != 2'b00))))); + + //----------------------------------------------- + // select indirect ifar + //----------------------------------------------- + + assign iu3_lnk_d[62 - `EFF_IFAR_WIDTH:61] = iu2_lnk[62 - `EFF_IFAR_WIDTH:61]; + assign iu3_btb_d[62 - `EFF_IFAR_WIDTH:61] = iu2_btb[62 - `EFF_IFAR_WIDTH:61]; + + //next fetch group address + assign iu3_nfg_d[62-`EFF_IFAR_WIDTH:59] = ic_bp_iu2_ifar[62 - `EFF_IFAR_WIDTH:59] + value_1[34-`EFF_IFAR_WIDTH:31]; + assign iu3_nfg_d[60:61] = 2'b00; + + //----------------------------------------------- + // redirect instruction pointer + //----------------------------------------------- + + assign iu2_redirect = bp_bt_en & ic_bp_iu2_val[0] & ic_bp_iu2_error[0:2] == 3'b000 & iu2_btb_hist[0] & ic_bp_iu2_ifar[62 - `EFF_IFAR_WIDTH:53] == iu2_btb_tag[62 - `EFF_IFAR_WIDTH:53] & ic_bp_iu2_ifar[60:61] <= iu2_btb_tag[60:61]; + + assign iu3_btb_redirect_d = iu2_redirect & (~iu2_flush); + assign iu3_btb_misdirect_d = iu2_redirect & (~iu2_flush) & iu2_btb_tag[60:61] != iu3_ifar_pri_d[60:61]; + assign iu3_btb_link_d = iu2_btb_link; + + assign iu4_redirect_act = iu3_redirect; + + assign iu4_redirect_ifar_d[62 - `EFF_IFAR_WIDTH:61] = iu3_bta[62 - `EFF_IFAR_WIDTH:61]; + + assign iu3_redirect = (iu3_pr_val_q ^ iu3_btb_redirect_q) | (iu3_btb_redirect_q & ((iu3_bclr_q == 1'b1 & iu3_bh_q[0:1] == 2'b00) ^ iu3_btb_link_q == 1'b1)) | (iu3_btb_misdirect_q & (~(((iu3_bcctr_q == 1'b1 | (iu3_bclr_q == 1'b1 & iu3_bh_q[0:1] != 2'b00)) & iu3_btb_link_q == 1'b0) | (iu3_bclr_q == 1'b1 & iu3_bh_q[0:1] == 2'b00 & iu3_btb_link_q == 1'b1)))); + + assign iu3_redirect_early = iu3_bclr_q | iu3_bcctr_q | (~iu3_pr_val_q); + assign iu4_redirect_d = iu3_redirect & (~iu3_redirect_early) & (~iu3_flush); + + assign bp_ic_redirect_ifar[62 - `EFF_IFAR_WIDTH:61] = (iu4_redirect_q == 1'b1) ? iu4_redirect_ifar_q[62 - `EFF_IFAR_WIDTH:61] : + ((iu3_redirect == 1'b1 & iu3_pr_val_q == 1'b0)) ? iu3_nfg_q[62 - `EFF_IFAR_WIDTH:61] : + ((iu3_redirect == 1'b1 & iu3_bclr_q == 1'b1 & iu3_bh_q[0:1] == 2'b00)) ? iu3_lnk_q[62 - `EFF_IFAR_WIDTH:61] : + ((iu3_redirect == 1'b1)) ? iu3_btb_q[62 - `EFF_IFAR_WIDTH:61] : + ((iu2_btb_link == 1'b1)) ? iu3_lnk_d[62 - `EFF_IFAR_WIDTH:61] : + iu3_btb_d[62 - `EFF_IFAR_WIDTH:61]; + + assign bp_ic_iu4_redirect = iu4_redirect_q; + assign bp_ic_iu3_redirect = iu3_redirect; + assign bp_ic_iu2_redirect = iu2_redirect; + + //----------------------------------------------- + // out of sync hold of link stack instructions + //----------------------------------------------- + + assign bp_ic_iu3_hold = 1'b0; + + //----------------------------------------------- + // output validated instructions + //----------------------------------------------- + + assign bp_ib_iu3_ifar[62 - `EFF_IFAR_WIDTH:61] = iu3_ifar_q[62 - `EFF_IFAR_WIDTH:61]; + + assign bp_ib_iu3_val[0:3] = ({4{~ic_bp_iu3_flush}} & iu3_val_q[0:3]); + + assign bp_ib_iu3_0_instr[0:69] = {iu3_0_instr_q[0:53], (iu3_0_instr_q[54] | ic_bp_iu3_ecc_err), iu3_0_instr_q[55:60], bp_ib_iu3_bta_val, iu3_gs_counts[0:5], iu3_gs_count0[0:1]}; + assign bp_ib_iu3_1_instr[0:69] = {iu3_1_instr_q[0:53], (iu3_1_instr_q[54] | ic_bp_iu3_ecc_err), iu3_1_instr_q[55:60], bp_ib_iu3_bta_val, iu3_gs_counts[0:5], iu3_gs_count1[0:1]}; + assign bp_ib_iu3_2_instr[0:69] = {iu3_2_instr_q[0:53], (iu3_2_instr_q[54] | ic_bp_iu3_ecc_err), iu3_2_instr_q[55:60], bp_ib_iu3_bta_val, iu3_gs_counts[0:5], iu3_gs_count2[0:1]}; + assign bp_ib_iu3_3_instr[0:69] = {iu3_3_instr_q[0:53], (iu3_3_instr_q[54] | ic_bp_iu3_ecc_err), iu3_3_instr_q[55:60], bp_ib_iu3_bta_val, iu3_gs_counts[0:5], iu3_gs_count3[0:1]}; + + assign bp_ib_iu3_bta[62 - `EFF_IFAR_WIDTH:61] = ((iu3_bclr_q == 1'b1 & iu3_bh_q[0:1] == 2'b00)) ? iu3_lnk_q[62 - `EFF_IFAR_WIDTH:61] : + iu3_btb_q[62 - `EFF_IFAR_WIDTH:61]; + + assign bp_ib_iu3_bta_val = (~iu4_redirect_d); + + //----------------------------------------------- + // latches + //----------------------------------------------- + + //scan chain 0 + + tri_rlmreg_p #(.WIDTH(128), .INIT(0)) iu0_btb_hist_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu0_btb_hist_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv0[iu0_btb_hist_offset:iu0_btb_hist_offset + 127]), + .scout(sov0[iu0_btb_hist_offset:iu0_btb_hist_offset + 127]), + .din(iu0_btb_hist_d[0:127]), + .dout(iu0_btb_hist_q[0:127]) + ); + + + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) iu1_btb_hist_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv0[iu1_btb_hist_offset:iu1_btb_hist_offset + 1]), + .scout(sov0[iu1_btb_hist_offset:iu1_btb_hist_offset + 1]), + .din(iu1_btb_hist_d[0:1]), + .dout(iu1_btb_hist_q[0:1]) + ); + + + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) iu2_btb_hist_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv0[iu2_btb_hist_offset:iu2_btb_hist_offset + 1]), + .scout(sov0[iu2_btb_hist_offset:iu2_btb_hist_offset + 1]), + .din(iu2_btb_hist_d[0:1]), + .dout(iu2_btb_hist_q[0:1]) + ); + + + tri_rlmreg_p #(.WIDTH(16), .INIT(0)) gshare_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(gshare_act[0]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv0[gshare_offset:gshare_offset + 15]), + .scout(sov0[gshare_offset:gshare_offset + 15]), + .din(gshare_d[0:15]), + .dout(gshare_q[0:15]) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(0)) gshare_shift0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv0[gshare_shift0_offset:gshare_shift0_offset + 4]), + .scout(sov0[gshare_shift0_offset:gshare_shift0_offset + 4]), + .din(gshare_shift0_d[0:4]), + .dout(gshare_shift0_q[0:4]) + ); + + tri_rlmreg_p #(.WIDTH(16), .INIT(0)) cp_gshare_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv0[cp_gshare_offset:cp_gshare_offset + 15]), + .scout(sov0[cp_gshare_offset:cp_gshare_offset + 15]), + .din(cp_gshare_d[0:15]), + .dout(cp_gshare_q[0:15]) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) cp_gs_count_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv0[cp_gs_count_offset:cp_gs_count_offset + 1]), + .scout(sov0[cp_gs_count_offset:cp_gs_count_offset + 1]), + .din(cp_gs_count_d[0:1]), + .dout(cp_gs_count_q[0:1]) + ); + + tri_rlmlatch_p #(.INIT(0)) cp_gs_taken_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu3_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv0[cp_gs_taken_offset]), + .scout(sov0[cp_gs_taken_offset]), + .din(cp_gs_taken_d), + .dout(cp_gs_taken_q) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu1_gs_pos_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv0[iu1_gs_pos_offset:iu1_gs_pos_offset + 2]), + .scout(sov0[iu1_gs_pos_offset:iu1_gs_pos_offset + 2]), + .din(iu1_gs_pos_d[0:2]), + .dout(iu1_gs_pos_q[0:2]) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu2_gs_pos_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv0[iu2_gs_pos_offset:iu2_gs_pos_offset + 2]), + .scout(sov0[iu2_gs_pos_offset:iu2_gs_pos_offset + 2]), + .din(iu2_gs_pos_d[0:2]), + .dout(iu2_gs_pos_q[0:2]) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu3_gs_pos_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv0[iu3_gs_pos_offset:iu3_gs_pos_offset + 2]), + .scout(sov0[iu3_gs_pos_offset:iu3_gs_pos_offset + 2]), + .din(iu3_gs_pos_d[0:2]), + .dout(iu3_gs_pos_q[0:2]) + ); + + tri_rlmreg_p #(.WIDTH(10), .INIT(0)) iu1_gshare_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv0[iu1_gshare_offset:iu1_gshare_offset + 9]), + .scout(sov0[iu1_gshare_offset:iu1_gshare_offset + 9]), + .din(iu1_gshare_d[0:9]), + .dout(iu1_gshare_q[0:9]) + ); + + + tri_rlmreg_p #(.WIDTH(10), .INIT(0)) iu2_gshare_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv0[iu2_gshare_offset:iu2_gshare_offset + 9]), + .scout(sov0[iu2_gshare_offset:iu2_gshare_offset + 9]), + .din(iu2_gshare_d[0:9]), + .dout(iu2_gshare_q[0:9]) + ); + + + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) iu3_bh_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu3_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv0[iu3_bh_offset:iu3_bh_offset + 1]), + .scout(sov0[iu3_bh_offset:iu3_bh_offset + 1]), + .din(iu3_bh_d[0:1]), + .dout(iu3_bh_q[0:1]) + ); + + + tri_rlmlatch_p #(.INIT(0)) iu3_lk_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu3_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv0[iu3_lk_offset]), + .scout(sov0[iu3_lk_offset]), + .din(iu3_lk_d), + .dout(iu3_lk_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) iu3_aa_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu3_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv0[iu3_aa_offset]), + .scout(sov0[iu3_aa_offset]), + .din(iu3_aa_d), + .dout(iu3_aa_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) iu3_b_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu3_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv0[iu3_b_offset]), + .scout(sov0[iu3_b_offset]), + .din(iu3_b_d), + .dout(iu3_b_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) iu3_bclr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu3_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv0[iu3_bclr_offset]), + .scout(sov0[iu3_bclr_offset]), + .din(iu3_bclr_d), + .dout(iu3_bclr_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) iu3_bcctr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu3_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv0[iu3_bcctr_offset]), + .scout(sov0[iu3_bcctr_offset]), + .din(iu3_bcctr_d), + .dout(iu3_bcctr_q) + ); + + + tri_rlmreg_p #(.WIDTH(6), .INIT(0)) iu3_opcode_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu3_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv0[iu3_opcode_offset:iu3_opcode_offset + 5]), + .scout(sov0[iu3_opcode_offset:iu3_opcode_offset + 5]), + .din(iu3_opcode_d[0:5]), + .dout(iu3_opcode_q[0:5]) + ); + + + tri_rlmreg_p #(.WIDTH(5), .INIT(0)) iu3_bo_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu3_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv0[iu3_bo_offset:iu3_bo_offset + 4]), + .scout(sov0[iu3_bo_offset:iu3_bo_offset + 4]), + .din(iu3_bo_d[6:10]), + .dout(iu3_bo_q[6:10]) + ); + + + tri_rlmreg_p #(.WIDTH(5), .INIT(0)) iu3_bi_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu3_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv0[iu3_bi_offset:iu3_bi_offset + 4]), + .scout(sov0[iu3_bi_offset:iu3_bi_offset + 4]), + .din(iu3_bi_d[11:15]), + .dout(iu3_bi_q[11:15]) + ); + + + tri_rlmreg_p #(.WIDTH(24), .INIT(0)) iu3_tar_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu3_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv0[iu3_tar_offset:iu3_tar_offset + 23]), + .scout(sov0[iu3_tar_offset:iu3_tar_offset + 23]), + .din(iu3_tar_d[6:29]), + .dout(iu3_tar_q[6:29]) + ); + + + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) iu3_ifar_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu3_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv0[iu3_ifar_offset:iu3_ifar_offset + `EFF_IFAR_WIDTH - 1]), + .scout(sov0[iu3_ifar_offset:iu3_ifar_offset + `EFF_IFAR_WIDTH - 1]), + .din(iu3_ifar_d[62 - `EFF_IFAR_WIDTH:61]), + .dout(iu3_ifar_q[62 - `EFF_IFAR_WIDTH:61]) + ); + + + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) iu3_ifar_pri_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu3_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv0[iu3_ifar_pri_offset:iu3_ifar_pri_offset + 1]), + .scout(sov0[iu3_ifar_pri_offset:iu3_ifar_pri_offset + 1]), + .din(iu3_ifar_pri_d[60:61]), + .dout(iu3_ifar_pri_q[60:61]) + ); + + + tri_rlmlatch_p #(.INIT(0)) iu3_pr_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv0[iu3_pr_val_offset]), + .scout(sov0[iu3_pr_val_offset]), + .din(iu3_pr_val_d), + .dout(iu3_pr_val_q) + ); + + tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) iu3_lnk_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu3_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv0[iu3_lnk_offset:iu3_lnk_offset + (`EFF_IFAR_WIDTH) - 1]), + .scout(sov0[iu3_lnk_offset:iu3_lnk_offset + (`EFF_IFAR_WIDTH) - 1]), + .din(iu3_lnk_d), + .dout(iu3_lnk_q) + ); + + + tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) iu3_btb_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu3_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv0[iu3_btb_offset:iu3_btb_offset + (`EFF_IFAR_WIDTH) - 1]), + .scout(sov0[iu3_btb_offset:iu3_btb_offset + (`EFF_IFAR_WIDTH) - 1]), + .din(iu3_btb_d), + .dout(iu3_btb_q) + ); + + + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) iu3_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv0[iu3_val_offset:iu3_val_offset + 3]), + .scout(sov0[iu3_val_offset:iu3_val_offset + 3]), + .din(iu3_val_d[0:3]), + .dout(iu3_val_q[0:3]) + ); + + + tri_rlmreg_p #(.WIDTH(61), .INIT(0)) iu3_0_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu3_instr_act[0]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv0[iu3_0_instr_offset:iu3_0_instr_offset + 61 - 1]), + .scout(sov0[iu3_0_instr_offset:iu3_0_instr_offset + 61 - 1]), + .din(iu3_0_instr_d), + .dout(iu3_0_instr_q) + ); + + + tri_rlmreg_p #(.WIDTH(61), .INIT(0)) iu3_1_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu3_instr_act[1]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv0[iu3_1_instr_offset:iu3_1_instr_offset + 61 - 1]), + .scout(sov0[iu3_1_instr_offset:iu3_1_instr_offset + 61 - 1]), + .din(iu3_1_instr_d), + .dout(iu3_1_instr_q) + ); + + + tri_rlmreg_p #(.WIDTH(61), .INIT(0)) iu3_2_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu3_instr_act[2]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv0[iu3_2_instr_offset:iu3_2_instr_offset + 61 - 1]), + .scout(sov0[iu3_2_instr_offset:iu3_2_instr_offset + 61 - 1]), + .din(iu3_2_instr_d), + .dout(iu3_2_instr_q) + ); + + + tri_rlmreg_p #(.WIDTH(61), .INIT(0)) iu3_3_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu3_instr_act[3]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv0[iu3_3_instr_offset:iu3_3_instr_offset + 61 - 1]), + .scout(sov0[iu3_3_instr_offset:iu3_3_instr_offset + 61 - 1]), + .din(iu3_3_instr_d), + .dout(iu3_3_instr_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) iu3_btb_redirect_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv0[iu3_btb_redirect_offset]), + .scout(sov0[iu3_btb_redirect_offset]), + .din(iu3_btb_redirect_d), + .dout(iu3_btb_redirect_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) iu3_btb_misdirect_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv0[iu3_btb_misdirect_offset]), + .scout(sov0[iu3_btb_misdirect_offset]), + .din(iu3_btb_misdirect_d), + .dout(iu3_btb_misdirect_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) iu3_btb_link_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu3_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv0[iu3_btb_link_offset]), + .scout(sov0[iu3_btb_link_offset]), + .din(iu3_btb_link_d), + .dout(iu3_btb_link_q) + ); + + + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) iu3_nfg_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu3_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv0[iu3_nfg_offset:iu3_nfg_offset + `EFF_IFAR_WIDTH - 1]), + .scout(sov0[iu3_nfg_offset:iu3_nfg_offset + `EFF_IFAR_WIDTH - 1]), + .din(iu3_nfg_d[62 - `EFF_IFAR_WIDTH:61]), + .dout(iu3_nfg_q[62 - `EFF_IFAR_WIDTH:61]) + ); + + + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) iu4_redirect_ifar_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu4_redirect_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv0[iu4_redirect_ifar_offset:iu4_redirect_ifar_offset + `EFF_IFAR_WIDTH - 1]), + .scout(sov0[iu4_redirect_ifar_offset:iu4_redirect_ifar_offset + `EFF_IFAR_WIDTH - 1]), + .din(iu4_redirect_ifar_d[62 - `EFF_IFAR_WIDTH:61]), + .dout(iu4_redirect_ifar_q[62 - `EFF_IFAR_WIDTH:61]) + ); + + + tri_rlmlatch_p #(.INIT(0)) iu4_redirect_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv0[iu4_redirect_offset]), + .scout(sov0[iu4_redirect_offset]), + .din(iu4_redirect_d), + .dout(iu4_redirect_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) iu4_ls_push_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv0[iu4_ls_push_offset]), + .scout(sov0[iu4_ls_push_offset]), + .din(iu4_ls_push_d), + .dout(iu4_ls_push_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) iu4_ls_pop_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv0[iu4_ls_pop_offset]), + .scout(sov0[iu4_ls_pop_offset]), + .din(iu4_ls_pop_d), + .dout(iu4_ls_pop_q) + ); + + + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) iu4_ifar_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu4_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv0[iu4_ifar_offset:iu4_ifar_offset + `EFF_IFAR_WIDTH - 1]), + .scout(sov0[iu4_ifar_offset:iu4_ifar_offset + `EFF_IFAR_WIDTH - 1]), + .din(iu4_ifar_d[62 - `EFF_IFAR_WIDTH:61]), + .dout(iu4_ifar_q[62 - `EFF_IFAR_WIDTH:61]) + ); + + //scan chain 1 + + tri_rlmreg_p #(.WIDTH(8), .INIT(128)) iu5_ls_t0_ptr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_ls_ptr_act[0]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[iu5_ls_t0_ptr_offset:iu5_ls_t0_ptr_offset + 7]), + .scout(sov1[iu5_ls_t0_ptr_offset:iu5_ls_t0_ptr_offset + 7]), + .din(iu5_ls_t0_ptr_d[0:7]), + .dout(iu5_ls_t0_ptr_q[0:7]) + ); + + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) iu5_ls_t00_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_ls_t0_act[0]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[iu5_ls_t00_offset:iu5_ls_t00_offset + `EFF_IFAR_WIDTH - 1]), + .scout(sov1[iu5_ls_t00_offset:iu5_ls_t00_offset + `EFF_IFAR_WIDTH - 1]), + .din(iu5_ls_t00_d[62 - `EFF_IFAR_WIDTH:61]), + .dout(iu5_ls_t00_q[62 - `EFF_IFAR_WIDTH:61]) + ); + + + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) iu5_ls_t01_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_ls_t0_act[1]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[iu5_ls_t01_offset:iu5_ls_t01_offset + `EFF_IFAR_WIDTH - 1]), + .scout(sov1[iu5_ls_t01_offset:iu5_ls_t01_offset + `EFF_IFAR_WIDTH - 1]), + .din(iu5_ls_t01_d[62 - `EFF_IFAR_WIDTH:61]), + .dout(iu5_ls_t01_q[62 - `EFF_IFAR_WIDTH:61]) + ); + + + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) iu5_ls_t02_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_ls_t0_act[2]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[iu5_ls_t02_offset:iu5_ls_t02_offset + `EFF_IFAR_WIDTH - 1]), + .scout(sov1[iu5_ls_t02_offset:iu5_ls_t02_offset + `EFF_IFAR_WIDTH - 1]), + .din(iu5_ls_t02_d[62 - `EFF_IFAR_WIDTH:61]), + .dout(iu5_ls_t02_q[62 - `EFF_IFAR_WIDTH:61]) + ); + + + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) iu5_ls_t03_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_ls_t0_act[3]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[iu5_ls_t03_offset:iu5_ls_t03_offset + `EFF_IFAR_WIDTH - 1]), + .scout(sov1[iu5_ls_t03_offset:iu5_ls_t03_offset + `EFF_IFAR_WIDTH - 1]), + .din(iu5_ls_t03_d[62 - `EFF_IFAR_WIDTH:61]), + .dout(iu5_ls_t03_q[62 - `EFF_IFAR_WIDTH:61]) + ); + + + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) iu5_ls_t04_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_ls_t0_act[4]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[iu5_ls_t04_offset:iu5_ls_t04_offset + `EFF_IFAR_WIDTH - 1]), + .scout(sov1[iu5_ls_t04_offset:iu5_ls_t04_offset + `EFF_IFAR_WIDTH - 1]), + .din(iu5_ls_t04_d[62 - `EFF_IFAR_WIDTH:61]), + .dout(iu5_ls_t04_q[62 - `EFF_IFAR_WIDTH:61]) + ); + + + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) iu5_ls_t05_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_ls_t0_act[5]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[iu5_ls_t05_offset:iu5_ls_t05_offset + `EFF_IFAR_WIDTH - 1]), + .scout(sov1[iu5_ls_t05_offset:iu5_ls_t05_offset + `EFF_IFAR_WIDTH - 1]), + .din(iu5_ls_t05_d[62 - `EFF_IFAR_WIDTH:61]), + .dout(iu5_ls_t05_q[62 - `EFF_IFAR_WIDTH:61]) + ); + + + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) iu5_ls_t06_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_ls_t0_act[6]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[iu5_ls_t06_offset:iu5_ls_t06_offset + `EFF_IFAR_WIDTH - 1]), + .scout(sov1[iu5_ls_t06_offset:iu5_ls_t06_offset + `EFF_IFAR_WIDTH - 1]), + .din(iu5_ls_t06_d[62 - `EFF_IFAR_WIDTH:61]), + .dout(iu5_ls_t06_q[62 - `EFF_IFAR_WIDTH:61]) + ); + + + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) iu5_ls_t07_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_ls_t0_act[7]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[iu5_ls_t07_offset:iu5_ls_t07_offset + `EFF_IFAR_WIDTH - 1]), + .scout(sov1[iu5_ls_t07_offset:iu5_ls_t07_offset + `EFF_IFAR_WIDTH - 1]), + .din(iu5_ls_t07_d[62 - `EFF_IFAR_WIDTH:61]), + .dout(iu5_ls_t07_q[62 - `EFF_IFAR_WIDTH:61]) + ); + + + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) ex6_ls_t00_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex6_ls_t0_act[0]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[ex6_ls_t00_offset:ex6_ls_t00_offset + `EFF_IFAR_WIDTH - 1]), + .scout(sov1[ex6_ls_t00_offset:ex6_ls_t00_offset + `EFF_IFAR_WIDTH - 1]), + .din(ex6_ls_t00_d[62 - `EFF_IFAR_WIDTH:61]), + .dout(ex6_ls_t00_q[62 - `EFF_IFAR_WIDTH:61]) + ); + + + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) ex6_ls_t01_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex6_ls_t0_act[1]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[ex6_ls_t01_offset:ex6_ls_t01_offset + `EFF_IFAR_WIDTH - 1]), + .scout(sov1[ex6_ls_t01_offset:ex6_ls_t01_offset + `EFF_IFAR_WIDTH - 1]), + .din(ex6_ls_t01_d[62 - `EFF_IFAR_WIDTH:61]), + .dout(ex6_ls_t01_q[62 - `EFF_IFAR_WIDTH:61]) + ); + + + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) ex6_ls_t02_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex6_ls_t0_act[2]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[ex6_ls_t02_offset:ex6_ls_t02_offset + `EFF_IFAR_WIDTH - 1]), + .scout(sov1[ex6_ls_t02_offset:ex6_ls_t02_offset + `EFF_IFAR_WIDTH - 1]), + .din(ex6_ls_t02_d[62 - `EFF_IFAR_WIDTH:61]), + .dout(ex6_ls_t02_q[62 - `EFF_IFAR_WIDTH:61]) + ); + + + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) ex6_ls_t03_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex6_ls_t0_act[3]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[ex6_ls_t03_offset:ex6_ls_t03_offset + `EFF_IFAR_WIDTH - 1]), + .scout(sov1[ex6_ls_t03_offset:ex6_ls_t03_offset + `EFF_IFAR_WIDTH - 1]), + .din(ex6_ls_t03_d[62 - `EFF_IFAR_WIDTH:61]), + .dout(ex6_ls_t03_q[62 - `EFF_IFAR_WIDTH:61]) + ); + + + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) ex6_ls_t04_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex6_ls_t0_act[4]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[ex6_ls_t04_offset:ex6_ls_t04_offset + `EFF_IFAR_WIDTH - 1]), + .scout(sov1[ex6_ls_t04_offset:ex6_ls_t04_offset + `EFF_IFAR_WIDTH - 1]), + .din(ex6_ls_t04_d[62 - `EFF_IFAR_WIDTH:61]), + .dout(ex6_ls_t04_q[62 - `EFF_IFAR_WIDTH:61]) + ); + + + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) ex6_ls_t05_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex6_ls_t0_act[5]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[ex6_ls_t05_offset:ex6_ls_t05_offset + `EFF_IFAR_WIDTH - 1]), + .scout(sov1[ex6_ls_t05_offset:ex6_ls_t05_offset + `EFF_IFAR_WIDTH - 1]), + .din(ex6_ls_t05_d[62 - `EFF_IFAR_WIDTH:61]), + .dout(ex6_ls_t05_q[62 - `EFF_IFAR_WIDTH:61]) + ); + + + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) ex6_ls_t06_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex6_ls_t0_act[6]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[ex6_ls_t06_offset:ex6_ls_t06_offset + `EFF_IFAR_WIDTH - 1]), + .scout(sov1[ex6_ls_t06_offset:ex6_ls_t06_offset + `EFF_IFAR_WIDTH - 1]), + .din(ex6_ls_t06_d[62 - `EFF_IFAR_WIDTH:61]), + .dout(ex6_ls_t06_q[62 - `EFF_IFAR_WIDTH:61]) + ); + + + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) ex6_ls_t07_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex6_ls_t0_act[7]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[ex6_ls_t07_offset:ex6_ls_t07_offset + `EFF_IFAR_WIDTH - 1]), + .scout(sov1[ex6_ls_t07_offset:ex6_ls_t07_offset + `EFF_IFAR_WIDTH - 1]), + .din(ex6_ls_t07_d[62 - `EFF_IFAR_WIDTH:61]), + .dout(ex6_ls_t07_q[62 - `EFF_IFAR_WIDTH:61]) + ); + + tri_rlmlatch_p #(.INIT(0)) ex5_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[ex5_val_offset]), + .scout(sov1[ex5_val_offset]), + .din(ex5_val_d), + .dout(ex5_val_q) + ); + + + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) ex5_ifar_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_val_d), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[ex5_ifar_offset:ex5_ifar_offset + `EFF_IFAR_WIDTH - 1]), + .scout(sov1[ex5_ifar_offset:ex5_ifar_offset + `EFF_IFAR_WIDTH - 1]), + .din(ex5_ifar_d[62 - `EFF_IFAR_WIDTH:61]), + .dout(ex5_ifar_q[62 - `EFF_IFAR_WIDTH:61]) + ); + + + tri_rlmlatch_p #(.INIT(0)) ex5_bh_update_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_val_d), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[ex5_bh_update_offset]), + .scout(sov1[ex5_bh_update_offset]), + .din(ex5_bh_update_d), + .dout(ex5_bh_update_q) + ); + + + tri_rlmreg_p #(.WIDTH(10), .INIT(0)) ex5_gshare_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_val_d), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[ex5_gshare_offset:ex5_gshare_offset + 9]), + .scout(sov1[ex5_gshare_offset:ex5_gshare_offset + 9]), + .din(ex5_gshare_d[0:9]), + .dout(ex5_gshare_q[0:9]) + ); + + + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) ex5_bh0_hist_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_val_d), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[ex5_bh0_hist_offset:ex5_bh0_hist_offset + 1]), + .scout(sov1[ex5_bh0_hist_offset:ex5_bh0_hist_offset + 1]), + .din(ex5_bh0_hist_d[0:1]), + .dout(ex5_bh0_hist_q[0:1]) + ); + + + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) ex5_bh1_hist_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_val_d), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[ex5_bh1_hist_offset:ex5_bh1_hist_offset + 1]), + .scout(sov1[ex5_bh1_hist_offset:ex5_bh1_hist_offset + 1]), + .din(ex5_bh1_hist_d[0:1]), + .dout(ex5_bh1_hist_q[0:1]) + ); + + + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) ex5_bh2_hist_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_val_d), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[ex5_bh2_hist_offset:ex5_bh2_hist_offset + 1]), + .scout(sov1[ex5_bh2_hist_offset:ex5_bh2_hist_offset + 1]), + .din(ex5_bh2_hist_d[0:1]), + .dout(ex5_bh2_hist_q[0:1]) + ); + + + tri_rlmlatch_p #(.INIT(0)) ex5_br_pred_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_val_d), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[ex5_br_pred_offset]), + .scout(sov1[ex5_br_pred_offset]), + .din(ex5_br_pred_d), + .dout(ex5_br_pred_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) ex5_br_taken_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_val_d), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[ex5_br_taken_offset]), + .scout(sov1[ex5_br_taken_offset]), + .din(ex5_br_taken_d), + .dout(ex5_br_taken_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) ex5_bcctr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_val_d), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[ex5_bcctr_offset]), + .scout(sov1[ex5_bcctr_offset]), + .din(ex5_bcctr_d), + .dout(ex5_bcctr_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) ex5_bclr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_val_d), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[ex5_bclr_offset]), + .scout(sov1[ex5_bclr_offset]), + .din(ex5_bclr_d), + .dout(ex5_bclr_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) ex5_getNIA_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_val_d), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[ex5_getNIA_offset]), + .scout(sov1[ex5_getNIA_offset]), + .din(ex5_getNIA_d), + .dout(ex5_getNIA_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) ex5_lk_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_val_d), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[ex5_lk_offset]), + .scout(sov1[ex5_lk_offset]), + .din(ex5_lk_d), + .dout(ex5_lk_q) + ); + + + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) ex5_bh_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_val_d), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[ex5_bh_offset:ex5_bh_offset + 1]), + .scout(sov1[ex5_bh_offset:ex5_bh_offset + 1]), + .din(ex5_bh_d[0:1]), + .dout(ex5_bh_q[0:1]) + ); + + + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) ex5_bta_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_val_d), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[ex5_bta_offset:ex5_bta_offset + `EFF_IFAR_WIDTH - 1]), + .scout(sov1[ex5_bta_offset:ex5_bta_offset + `EFF_IFAR_WIDTH - 1]), + .din(ex5_bta_d[62 - `EFF_IFAR_WIDTH:61]), + .dout(ex5_bta_q[62 - `EFF_IFAR_WIDTH:61]) + ); + + + tri_rlmreg_p #(.WIDTH(8), .INIT(0)) ex5_ls_ptr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_val_d), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[ex5_ls_ptr_offset:ex5_ls_ptr_offset + 7]), + .scout(sov1[ex5_ls_ptr_offset:ex5_ls_ptr_offset + 7]), + .din(ex5_ls_ptr_d[0:7]), + .dout(ex5_ls_ptr_q[0:7]) + ); + + + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) ex5_btb_hist_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_val_d), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[ex5_btb_hist_offset:ex5_btb_hist_offset + 1]), + .scout(sov1[ex5_btb_hist_offset:ex5_btb_hist_offset + 1]), + .din(ex5_btb_hist_d[0:1]), + .dout(ex5_btb_hist_q[0:1]) + ); + + + tri_rlmlatch_p #(.INIT(0)) ex5_btb_entry_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[ex5_btb_entry_offset]), + .scout(sov1[ex5_btb_entry_offset]), + .din(ex5_btb_entry_d), + .dout(ex5_btb_entry_q) + ); + + + tri_rlmreg_p #(.WIDTH(128), .INIT(0)) ex5_btb_repl_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_val_q), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[ex5_btb_repl_offset:ex5_btb_repl_offset + 127]), + .scout(sov1[ex5_btb_repl_offset:ex5_btb_repl_offset + 127]), + .din(ex5_btb_repl_d[0:127]), + .dout(ex5_btb_repl_q[0:127]) + ); + + + tri_rlmlatch_p #(.INIT(0)) ex5_ls_push_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[ex5_ls_push_offset]), + .scout(sov1[ex5_ls_push_offset]), + .din(ex5_ls_push_d), + .dout(ex5_ls_push_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) ex5_ls_pop_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[ex5_ls_pop_offset]), + .scout(sov1[ex5_ls_pop_offset]), + .din(ex5_ls_pop_d), + .dout(ex5_ls_pop_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) ex5_group_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[ex5_group_offset]), + .scout(sov1[ex5_group_offset]), + .din(ex5_group_d), + .dout(ex5_group_q) + ); + + tri_rlmlatch_p #(.INIT(0)) ex5_flush_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[ex5_flush_offset]), + .scout(sov1[ex5_flush_offset]), + .din(ex5_flush_d), + .dout(ex5_flush_q) + ); + + + tri_rlmreg_p #(.WIDTH(8), .INIT(128)) ex6_ls_t0_ptr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex6_ls_ptr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[ex6_ls_t0_ptr_offset:ex6_ls_t0_ptr_offset + 7]), + .scout(sov1[ex6_ls_t0_ptr_offset:ex6_ls_t0_ptr_offset + 7]), + .din(ex6_ls_t0_ptr_d[0:7]), + .dout(ex6_ls_t0_ptr_q[0:7]) + ); + + + tri_rlmreg_p #(.WIDTH(7), .INIT(0)) bp_config_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[bp_config_offset:bp_config_offset + 6]), + .scout(sov1[bp_config_offset:bp_config_offset + 6]), + .din(bp_config_d[0:6]), + .dout(bp_config_q[0:6]) + ); + + + tri_rlmreg_p #(.WIDTH(18), .INIT(0)) br_iu_gshare_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[br_iu_gshare_offset:br_iu_gshare_offset + 17]), + .scout(sov1[br_iu_gshare_offset:br_iu_gshare_offset + 17]), + .din(br_iu_gshare_d[0:17]), + .dout(br_iu_gshare_q[0:17]) + ); + + + tri_rlmreg_p #(.WIDTH(8), .INIT(0)) br_iu_ls_ptr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[br_iu_ls_ptr_offset:br_iu_ls_ptr_offset + 7]), + .scout(sov1[br_iu_ls_ptr_offset:br_iu_ls_ptr_offset + 7]), + .din(br_iu_ls_ptr_d[0:7]), + .dout(br_iu_ls_ptr_q[0:7]) + ); + + + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) br_iu_ls_data_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[br_iu_ls_data_offset:br_iu_ls_data_offset + `EFF_IFAR_WIDTH - 1]), + .scout(sov1[br_iu_ls_data_offset:br_iu_ls_data_offset + `EFF_IFAR_WIDTH - 1]), + .din(br_iu_ls_data_d[62 - `EFF_IFAR_WIDTH:61]), + .dout(br_iu_ls_data_q[62 - `EFF_IFAR_WIDTH:61]) + ); + + + tri_rlmlatch_p #(.INIT(0)) br_iu_ls_update_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[br_iu_ls_update_offset]), + .scout(sov1[br_iu_ls_update_offset]), + .din(br_iu_ls_update_d), + .dout(br_iu_ls_update_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) br_iu_redirect_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[br_iu_redirect_offset]), + .scout(sov1[br_iu_redirect_offset]), + .din(br_iu_redirect), + .dout(br_iu_redirect_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) cp_flush_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[cp_flush_offset]), + .scout(sov1[cp_flush_offset]), + .din(cp_flush), + .dout(cp_flush_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) iu_flush_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[iu_flush_offset]), + .scout(sov1[iu_flush_offset]), + .din(iu_flush), + .dout(iu_flush_q) + ); + + tri_rlmreg_p #(.WIDTH(16), .INIT(0)) bcache_data0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(bcache_shift[0]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[bcache_data0_offset:bcache_data0_offset + 15]), + .scout(sov1[bcache_data0_offset:bcache_data0_offset + 15]), + .din(bcache_data0_d[0:15]), + .dout(bcache_data0_q[0:15]) + ); + + tri_rlmreg_p #(.WIDTH(16), .INIT(0)) bcache_data1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(bcache_shift[1]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[bcache_data1_offset:bcache_data1_offset + 15]), + .scout(sov1[bcache_data1_offset:bcache_data1_offset + 15]), + .din(bcache_data1_d[0:15]), + .dout(bcache_data1_q[0:15]) + ); + + tri_rlmreg_p #(.WIDTH(16), .INIT(0)) bcache_data2_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(bcache_shift[2]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[bcache_data2_offset:bcache_data2_offset + 15]), + .scout(sov1[bcache_data2_offset:bcache_data2_offset + 15]), + .din(bcache_data2_d[0:15]), + .dout(bcache_data2_q[0:15]) + ); + + tri_rlmreg_p #(.WIDTH(16), .INIT(0)) bcache_data3_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(bcache_shift[3]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[bcache_data3_offset:bcache_data3_offset + 15]), + .scout(sov1[bcache_data3_offset:bcache_data3_offset + 15]), + .din(bcache_data3_d[0:15]), + .dout(bcache_data3_q[0:15]) + ); + + tri_rlmreg_p #(.WIDTH(16), .INIT(0)) bcache_data4_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(bcache_shift[4]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[bcache_data4_offset:bcache_data4_offset + 15]), + .scout(sov1[bcache_data4_offset:bcache_data4_offset + 15]), + .din(bcache_data4_d[0:15]), + .dout(bcache_data4_q[0:15]) + ); + + tri_rlmreg_p #(.WIDTH(16), .INIT(0)) bcache_data5_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(bcache_shift[5]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[bcache_data5_offset:bcache_data5_offset + 15]), + .scout(sov1[bcache_data5_offset:bcache_data5_offset + 15]), + .din(bcache_data5_d[0:15]), + .dout(bcache_data5_q[0:15]) + ); + + + tri_rlmreg_p #(.WIDTH(16), .INIT(0)) bcache_data6_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(bcache_shift[6]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[bcache_data6_offset:bcache_data6_offset + 15]), + .scout(sov1[bcache_data6_offset:bcache_data6_offset + 15]), + .din(bcache_data6_d[0:15]), + .dout(bcache_data6_q[0:15]) + ); + + tri_rlmreg_p #(.WIDTH(16), .INIT(0)) bcache_data7_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(bcache_shift[7]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv1[bcache_data7_offset:bcache_data7_offset + 15]), + .scout(sov1[bcache_data7_offset:bcache_data7_offset + 15]), + .din(bcache_data7_d[0:15]), + .dout(bcache_data7_q[0:15]) + ); + + + //----------------------------------------------- + // pervasive + //----------------------------------------------- + + + tri_plat #(.WIDTH(2)) perv_2to1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + .din({pc_iu_func_sl_thold_2,pc_iu_sg_2}), + .q({pc_iu_func_sl_thold_1,pc_iu_sg_1}) + ); + + + tri_plat #(.WIDTH(2)) perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + .din({pc_iu_func_sl_thold_1,pc_iu_sg_1}), + .q({pc_iu_func_sl_thold_0,pc_iu_sg_0}) + ); + + + tri_lcbor perv_lcbor( + .clkoff_b(clkoff_b), + .thold(pc_iu_func_sl_thold_0), + .sg(pc_iu_sg_0), + .act_dis(act_dis), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b) + ); + + //----------------------------------------------- + // scan + //----------------------------------------------- + + assign siv0[0:scan_right0] = {scan_in[0], sov0[0:scan_right0 - 1]}; + assign scan_out[0] = sov0[scan_right0]; + + assign siv1[0:scan_right1] = {scan_in[1], sov1[0:scan_right1 - 1]}; + assign scan_out[1] = sov1[scan_right1]; + +endmodule diff --git a/dev/verilog/work/iuq_btb.v b/dev/verilog/work/iuq_btb.v new file mode 100755 index 0000000..713cbf9 --- /dev/null +++ b/dev/verilog/work/iuq_btb.v @@ -0,0 +1,430 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// ********************************************************************* +// +// This is the ENTITY for iuq_btb +// +// ********************************************************************* + +`include "tri_a2o.vh" + +module iuq_btb( + // power pins + inout gnd, + inout vdd, + inout vcs, + + // clock and clockcontrol ports + input [0:`NCLK_WIDTH-1] nclk, + input pc_iu_func_sl_thold_2, + input pc_iu_sg_2, + input pc_iu_fce_2, + input tc_ac_ccflush_dc, + input clkoff_b, + input act_dis, + input d_mode, + input delay_lclkr, + input mpw1_b, + input mpw2_b, + input scan_in, + output scan_out, + + // ports + input r_act, + input w_act, + input [0:5] r_addr, + input [0:5] w_addr, + input [0:2*`EFF_IFAR_WIDTH+2] data_in, + output [0:2*`EFF_IFAR_WIDTH+2] data_out, + input pc_iu_init_reset + ); + + + //-------------------------- + // constants + //-------------------------- + + parameter data_in_offset = 0; + parameter w_act_offset = data_in_offset + 2 * `EFF_IFAR_WIDTH + 3; + parameter r_act_offset = w_act_offset + 1; + parameter w_addr_offset = r_act_offset + 1; + parameter r_addr_offset = w_addr_offset + 6; + parameter reset_w_addr_offset = r_addr_offset + 6; + parameter data_out_offset = reset_w_addr_offset + 6; + parameter scan_right = data_out_offset + 2 * `EFF_IFAR_WIDTH + 3 - 1; + + //-------------------------- + // signals + //-------------------------- + + wire [0:71] w_data_in; + wire [0:71] r_data_out; + + wire [0:5] zeros; + + wire pc_iu_func_sl_thold_1; + wire pc_iu_func_sl_thold_0; + wire pc_iu_func_sl_thold_0_b; + wire pc_iu_sg_1; + wire pc_iu_sg_0; + wire pc_iu_fce_1; + (* analysis_not_referenced="true" *) + wire pc_iu_fce_0; + wire force_t; + + wire [0:scan_right] siv; + wire [0:scan_right] sov; + + wire tiup; + wire tidn; + + wire write_thru; + + wire [0:2*`EFF_IFAR_WIDTH+2] data_in_d; + wire [0:2*`EFF_IFAR_WIDTH+2] data_in_q; + wire w_act_d; + wire w_act_q; + wire r_act_d; + wire r_act_q; + wire [0:5] w_addr_d; + wire [0:5] w_addr_q; + wire [0:5] r_addr_d; + wire [0:5] r_addr_q; + wire [0:2*`EFF_IFAR_WIDTH+2] data_out_d; + wire [0:2*`EFF_IFAR_WIDTH+2] data_out_q; + + wire lat_wi_act; + wire lat_ri_act; + wire lat_ro_act; + + wire reset_act; + wire [0:5] reset_w_addr_d; + wire [0:5] reset_w_addr_q; + wire w_act_in; + wire [0:5] w_addr_in; + + //unused +(* analysis_not_referenced="true" *) + wire abst_scan_out; +(* analysis_not_referenced="true" *) + wire time_scan_out; +(* analysis_not_referenced="true" *) + wire repr_scan_out; +(* analysis_not_referenced="true" *) + wire bo_pc_failout; +(* analysis_not_referenced="true" *) + wire bo_pc_diagloop; + + + assign tiup = 1'b1; + assign tidn = 1'b0; + + assign reset_act = pc_iu_init_reset; + assign reset_w_addr_d[0:5] = reset_w_addr_q[0:5] + 6'b000001; + + + //-- data in + // + assign zeros[0:5] = {6{1'b0}}; + // + //-- arrays + // + + // tri array + + assign w_act_in = reset_act | w_act; + assign w_addr_in[0:5] = reset_act ? reset_w_addr_q[0:5] : w_addr[0:5]; + assign w_data_in[0:71] = reset_act ? 0 : {data_in[0:2 * `EFF_IFAR_WIDTH + 2], {(71 - (2 * `EFF_IFAR_WIDTH + 2)){1'b0}} }; + + + tri_64x72_1r1w btb0( + .vdd(vdd), + .vcs(vcs), + .gnd(gnd), + .nclk(nclk), + .sg_0(pc_iu_sg_0), + .abst_sl_thold_0(tidn), + .ary_nsl_thold_0(tidn), + .time_sl_thold_0(tiup), + .repr_sl_thold_0(tiup), + // Reads + .rd0_act(r_act), + .rd0_adr(r_addr), + .do0(r_data_out), + // Writes + .wr_act(w_act_in), + .wr_adr(w_addr_in), + .di(w_data_in), + // Scan + .abst_scan_in(tidn), + .abst_scan_out(abst_scan_out), + .time_scan_in(tidn), + .time_scan_out(time_scan_out), + .repr_scan_in(tidn), + .repr_scan_out(repr_scan_out), + // Misc Pervasive + .scan_dis_dc_b(tidn), //an_ac_scan_dis_dc_b, + .scan_diag_dc(tidn), //an_ac_scan_diag_dc, + .ccflush_dc(tc_ac_ccflush_dc), + .clkoff_dc_b(clkoff_b), //g8t_clkoff_dc_b, + .d_mode_dc(d_mode), //g8t_d_mode_dc, + .mpw1_dc_b({5{mpw1_b}}), //g8t_mpw1_dc_b, + .mpw2_dc_b(mpw2_b), //g8t_mpw2_dc_b, + .delay_lclkr_dc({5{delay_lclkr}}), //g8t_delay_lclkr_dc, + // BOLT-ON + .lcb_bolt_sl_thold_0(tidn), //bolt_sl_thold_0, + .pc_bo_enable_2(tidn), //bo_enable_2, -- general bolt-on enable + .pc_bo_reset(tidn), //pc_xu_bo_reset, -- reset + .pc_bo_unload(tidn), //pc_xu_bo_unload, -- unload sticky bits + .pc_bo_repair(tidn), //pc_xu_bo_repair, -- execute sticky bit decode + .pc_bo_shdata(tidn), //pc_xu_bo_shdata, -- shift data for timing write and diag loop + .pc_bo_select(tidn), //pc_xu_bo_select, -- select for mask and hier writes + .bo_pc_failout(bo_pc_failout), + .bo_pc_diagloop(bo_pc_diagloop), + .tri_lcb_mpw1_dc_b(mpw1_b), //mpw1_dc_b, + .tri_lcb_mpw2_dc_b(mpw2_b), //mpw2_dc_b, + .tri_lcb_delay_lclkr_dc(delay_lclkr), //delay_lclkr_dc, + .tri_lcb_clkoff_dc_b(clkoff_b), //clkoff_dc_b, + .tri_lcb_act_dis_dc(act_dis), + // ABIST + .abist_bw_odd(tidn), //abist_g8t_bw_1_q, + .abist_bw_even(tidn), //abist_g8t_bw_0_q, + .tc_lbist_ary_wrt_thru_dc(tidn), //an_ac_lbist_ary_wrt_thru_dc, + .abist_ena_1(tidn), //pc_xu_abist_ena_dc, + .wr_abst_act(tidn), //abist_g8t_wenb_q, + .abist_wr_adr(zeros[0:5]), //abist_waddr_0_q, + .abist_di(zeros[0:3]), //abist_di_0_q, + .rd0_abst_act(tidn), //abist_g8t1p_renb_0_q, + .abist_rd0_adr(zeros[0:5]), //abist_raddr_0_q, + .abist_g8t_rd0_comp_ena(tidn), //abist_wl32_comp_ena_q, + .abist_raw_dc_b(tidn), //pc_xu_abist_raw_dc_b, + .obs0_abist_cmp(zeros[0:3]) //abist_g8t_dcomp_q + ); + + // write through support + + assign data_in_d[0:2 * `EFF_IFAR_WIDTH + 2] = data_in[0:2 * `EFF_IFAR_WIDTH + 2]; + assign w_act_d = w_act; + assign r_act_d = r_act; + assign w_addr_d[0:5] = w_addr[0:5]; + assign r_addr_d[0:5] = r_addr[0:5]; + + assign write_thru = w_act_q & (w_addr_q[0:5] == r_addr_q[0:5]) & r_act_q; + + // data out + + assign data_out_d[0:2 * `EFF_IFAR_WIDTH + 2] = (write_thru == 1'b1) ? data_in_q[0:2 * `EFF_IFAR_WIDTH + 2] : + r_data_out[0:2 * `EFF_IFAR_WIDTH + 2]; + + assign data_out[0:2 * `EFF_IFAR_WIDTH + 2] = data_out_q[0:2 * `EFF_IFAR_WIDTH + 2]; + + //latch acts + assign lat_wi_act = w_act; + assign lat_ri_act = r_act; + assign lat_ro_act = r_act_q; + + // latches + + + tri_rlmreg_p #(.WIDTH((2*`EFF_IFAR_WIDTH+2+1)), .INIT(0)) data_in_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lat_wi_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[data_in_offset:data_in_offset + (2*`EFF_IFAR_WIDTH+2+1) - 1]), + .scout(sov[data_in_offset:data_in_offset + (2*`EFF_IFAR_WIDTH+2+1) - 1]), + .din(data_in_d), + .dout(data_in_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) w_act_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[w_act_offset]), + .scout(sov[w_act_offset]), + .din(w_act_d), + .dout(w_act_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) r_act_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[r_act_offset]), + .scout(sov[r_act_offset]), + .din(r_act_d), + .dout(r_act_q) + ); + + + tri_rlmreg_p #(.WIDTH(6), .INIT(0)) w_addr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lat_wi_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[w_addr_offset:w_addr_offset + 6 - 1]), + .scout(sov[w_addr_offset:w_addr_offset + 6 - 1]), + .din(w_addr_d), + .dout(w_addr_q) + ); + + + tri_rlmreg_p #(.WIDTH(6), .INIT(0)) r_addr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lat_ri_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[r_addr_offset:r_addr_offset + 6 - 1]), + .scout(sov[r_addr_offset:r_addr_offset + 6 - 1]), + .din(r_addr_d), + .dout(r_addr_q) + ); + + + tri_rlmreg_p #(.WIDTH((2*`EFF_IFAR_WIDTH+2+1)), .INIT(0)) data_out_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lat_ro_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[data_out_offset:data_out_offset + (2*`EFF_IFAR_WIDTH+2+1) - 1]), + .scout(sov[data_out_offset:data_out_offset + (2*`EFF_IFAR_WIDTH+2+1) - 1]), + .din(data_out_d), + .dout(data_out_q) + ); + + tri_rlmreg_p #(.WIDTH(6), .INIT(0)) reset_w_addr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(reset_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[reset_w_addr_offset:reset_w_addr_offset + 6 - 1]), + .scout(sov[reset_w_addr_offset:reset_w_addr_offset + 6 - 1]), + .din(reset_w_addr_d), + .dout(reset_w_addr_q) + ); + + //----------------------------------------------- + // pervasive + //----------------------------------------------- + + + tri_plat #(.WIDTH(3)) perv_2to1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + .din({pc_iu_func_sl_thold_2, pc_iu_sg_2, pc_iu_fce_2}), + .q({pc_iu_func_sl_thold_1, pc_iu_sg_1, pc_iu_fce_1}) + ); + + + tri_plat #(.WIDTH(3)) perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + .din({pc_iu_func_sl_thold_1, pc_iu_sg_1, pc_iu_fce_1}), + .q({pc_iu_func_sl_thold_0, pc_iu_sg_0, pc_iu_fce_0}) + ); + + + tri_lcbor perv_lcbor( + .clkoff_b(clkoff_b), + .thold(pc_iu_func_sl_thold_0), + .sg(pc_iu_sg_0), + .act_dis(act_dis), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b) + ); + + //----------------------------------------------- + // scan + //----------------------------------------------- + + assign siv[0:scan_right] = {scan_in, sov[0:scan_right - 1]}; + assign scan_out = sov[scan_right]; + + +endmodule diff --git a/dev/verilog/work/iuq_cpl.v b/dev/verilog/work/iuq_cpl.v new file mode 100755 index 0000000..02f288e --- /dev/null +++ b/dev/verilog/work/iuq_cpl.v @@ -0,0 +1,1614 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: Completion Unit +// +//***************************************************************************** + +`include "tri_a2o.vh" + +module iuq_cpl( + // Clocks + input [0:`NCLK_WIDTH-1] nclk, + + // Pervasive + input tc_ac_ccflush_dc, + input clkoff_dc_b, + input d_mode_dc, + input delay_lclkr_dc, + input mpw1_dc_b, + input mpw2_dc_b, + input func_sl_thold_2, + input func_slp_sl_thold_2, + input sg_2, + input scan_in, + output scan_out, + + // Perfomance selectors + input pc_iu_event_bus_enable, + input [0:2] pc_iu_event_count_mode, + input [0:15] spr_cp_perf_event_mux_ctrls, + input [0:3] event_bus_in, + output [0:3] event_bus_out, + + // Instruction 0 Issue + input rn_cp_iu6_i0_vld, + input [1:`ITAG_SIZE_ENC-1] rn_cp_iu6_i0_itag, + input [0:2] rn_cp_iu6_i0_ucode, + input rn_cp_iu6_i0_fuse_nop, + input rn_cp_iu6_i0_rte_lq, + input rn_cp_iu6_i0_rte_sq, + input rn_cp_iu6_i0_rte_fx0, + input rn_cp_iu6_i0_rte_fx1, + input rn_cp_iu6_i0_rte_axu0, + input rn_cp_iu6_i0_rte_axu1, + + input [62-`EFF_IFAR_WIDTH:61] rn_cp_iu6_i0_ifar, + input [62-`EFF_IFAR_WIDTH:61] rn_cp_iu6_i0_bta, + input rn_cp_iu6_i0_isram, + input [0:31] rn_cp_iu6_i0_instr, + + input rn_cp_iu6_i0_valop, + input [0:2] rn_cp_iu6_i0_error, + input rn_cp_iu6_i0_br_pred, + input rn_cp_iu6_i0_bh_update, + input [0:1] rn_cp_iu6_i0_bh0_hist, + input [0:1] rn_cp_iu6_i0_bh1_hist, + input [0:1] rn_cp_iu6_i0_bh2_hist, + input [0:9] rn_cp_iu6_i0_gshare, + input [0:2] rn_cp_iu6_i0_ls_ptr, + input rn_cp_iu6_i0_match, + + input rn_cp_iu6_i0_type_fp, + input rn_cp_iu6_i0_type_ap, + input rn_cp_iu6_i0_type_spv, + input rn_cp_iu6_i0_type_st, + input rn_cp_iu6_i0_async_block, + input rn_cp_iu6_i0_np1_flush, + + input rn_cp_iu6_i0_t1_v, + input [0:`TYPE_WIDTH-1] rn_cp_iu6_i0_t1_t, + input [0:`GPR_POOL_ENC-1] rn_cp_iu6_i0_t1_p, + input [0:`GPR_POOL_ENC-1] rn_cp_iu6_i0_t1_a, + + input rn_cp_iu6_i0_t2_v, + input [0:`TYPE_WIDTH-1] rn_cp_iu6_i0_t2_t, + input [0:`GPR_POOL_ENC-1] rn_cp_iu6_i0_t2_p, + input [0:`GPR_POOL_ENC-1] rn_cp_iu6_i0_t2_a, + + input rn_cp_iu6_i0_t3_v, + input [0:`TYPE_WIDTH-1] rn_cp_iu6_i0_t3_t, + input [0:`GPR_POOL_ENC-1] rn_cp_iu6_i0_t3_p, + input [0:`GPR_POOL_ENC-1] rn_cp_iu6_i0_t3_a, + + input rn_cp_iu6_i0_btb_entry, + input [0:1] rn_cp_iu6_i0_btb_hist, + input rn_cp_iu6_i0_bta_val, + + // Instruction 1 Issue + input rn_cp_iu6_i1_vld, + input [1:`ITAG_SIZE_ENC-1] rn_cp_iu6_i1_itag, + input [0:2] rn_cp_iu6_i1_ucode, + input rn_cp_iu6_i1_fuse_nop, + input rn_cp_iu6_i1_rte_lq, + input rn_cp_iu6_i1_rte_sq, + input rn_cp_iu6_i1_rte_fx0, + input rn_cp_iu6_i1_rte_fx1, + input rn_cp_iu6_i1_rte_axu0, + input rn_cp_iu6_i1_rte_axu1, + + input [62-`EFF_IFAR_WIDTH:61] rn_cp_iu6_i1_ifar, + input [62-`EFF_IFAR_WIDTH:61] rn_cp_iu6_i1_bta, + input rn_cp_iu6_i1_isram, + input [0:31] rn_cp_iu6_i1_instr, + + input rn_cp_iu6_i1_valop, + input [0:2] rn_cp_iu6_i1_error, + input rn_cp_iu6_i1_br_pred, + input rn_cp_iu6_i1_bh_update, + input [0:1] rn_cp_iu6_i1_bh0_hist, + input [0:1] rn_cp_iu6_i1_bh1_hist, + input [0:1] rn_cp_iu6_i1_bh2_hist, + input [0:9] rn_cp_iu6_i1_gshare, + input [0:2] rn_cp_iu6_i1_ls_ptr, + input rn_cp_iu6_i1_match, + + input rn_cp_iu6_i1_type_fp, + input rn_cp_iu6_i1_type_ap, + input rn_cp_iu6_i1_type_spv, + input rn_cp_iu6_i1_type_st, + input rn_cp_iu6_i1_async_block, + input rn_cp_iu6_i1_np1_flush, + + input rn_cp_iu6_i1_t1_v, + input [0:`TYPE_WIDTH-1] rn_cp_iu6_i1_t1_t, + input [0:`GPR_POOL_ENC-1] rn_cp_iu6_i1_t1_p, + input [0:`GPR_POOL_ENC-1] rn_cp_iu6_i1_t1_a, + + input rn_cp_iu6_i1_t2_v, + input [0:`TYPE_WIDTH-1] rn_cp_iu6_i1_t2_t, + input [0:`GPR_POOL_ENC-1] rn_cp_iu6_i1_t2_p, + input [0:`GPR_POOL_ENC-1] rn_cp_iu6_i1_t2_a, + + input rn_cp_iu6_i1_t3_v, + input [0:`TYPE_WIDTH-1] rn_cp_iu6_i1_t3_t, + input [0:`GPR_POOL_ENC-1] rn_cp_iu6_i1_t3_p, + input [0:`GPR_POOL_ENC-1] rn_cp_iu6_i1_t3_a, + + input rn_cp_iu6_i1_btb_entry, + input [0:1] rn_cp_iu6_i1_btb_hist, + input rn_cp_iu6_i1_bta_val, + + // completion empty + output cp_rn_empty, + output cp_async_block, + + // Instruction 0 Complete + output cp_rn_i0_v, + output cp_rn_i0_axu_exception_val, + output [0:3] cp_rn_i0_axu_exception, + output cp_rn_i0_t1_v, + output [0:`TYPE_WIDTH-1] cp_rn_i0_t1_t, + output [0:`GPR_POOL_ENC-1] cp_rn_i0_t1_p, + output [0:`GPR_POOL_ENC-1] cp_rn_i0_t1_a, + + output cp_rn_i0_t2_v, + output [0:`TYPE_WIDTH-1] cp_rn_i0_t2_t, + output [0:`GPR_POOL_ENC-1] cp_rn_i0_t2_p, + output [0:`GPR_POOL_ENC-1] cp_rn_i0_t2_a, + + output cp_rn_i0_t3_v, + output [0:`TYPE_WIDTH-1] cp_rn_i0_t3_t, + output [0:`GPR_POOL_ENC-1] cp_rn_i0_t3_p, + output [0:`GPR_POOL_ENC-1] cp_rn_i0_t3_a, + + // Instruction 1 Complete + output cp_rn_i1_v, + output cp_rn_i1_axu_exception_val, + output [0:3] cp_rn_i1_axu_exception, + output cp_rn_i1_t1_v, + output [0:`TYPE_WIDTH-1] cp_rn_i1_t1_t, + output [0:`GPR_POOL_ENC-1] cp_rn_i1_t1_p, + output [0:`GPR_POOL_ENC-1] cp_rn_i1_t1_a, + + output cp_rn_i1_t2_v, + output [0:`TYPE_WIDTH-1] cp_rn_i1_t2_t, + output [0:`GPR_POOL_ENC-1] cp_rn_i1_t2_p, + output [0:`GPR_POOL_ENC-1] cp_rn_i1_t2_a, + + output cp_rn_i1_t3_v, + output [0:`TYPE_WIDTH-1] cp_rn_i1_t3_t, + output [0:`GPR_POOL_ENC-1] cp_rn_i1_t3_p, + output [0:`GPR_POOL_ENC-1] cp_rn_i1_t3_a, + + // Branch Prediction Complete + output cp_bp_val, + output [62-`EFF_IFAR_WIDTH:61] cp_bp_ifar, + output [0:1] cp_bp_bh0_hist, + output [0:1] cp_bp_bh1_hist, + output [0:1] cp_bp_bh2_hist, + output cp_bp_br_pred, + output cp_bp_br_taken, + output cp_bp_bh_update, + output cp_bp_bcctr, + output cp_bp_bclr, + output cp_bp_lk, + output [0:1] cp_bp_bh, + output [0:9] cp_bp_gshare, + output [0:2] cp_bp_ls_ptr, + output [62-`EFF_IFAR_WIDTH:61] cp_bp_ctr, + output cp_bp_btb_entry, + output [0:1] cp_bp_btb_hist, + output cp_bp_getnia, + output cp_bp_group, + + // Output to dispatch to block due to ivax + output cp_dis_ivax, + + // LQ Instruction Executed + input lq0_iu_execute_vld, + input [0:`ITAG_SIZE_ENC-1] lq0_iu_itag, + input lq0_iu_n_flush, + input lq0_iu_np1_flush, + input lq0_iu_dacr_type, + input [0:3] lq0_iu_dacrw, + input [0:31] lq0_iu_instr, + input [64-`GPR_WIDTH:63] lq0_iu_eff_addr, + input lq0_iu_exception_val, + input [0:5] lq0_iu_exception, + input lq0_iu_flush2ucode, + input lq0_iu_flush2ucode_type, + input lq0_iu_recirc_val, + input lq0_iu_dear_val, + + input lq1_iu_execute_vld, + input [0:`ITAG_SIZE_ENC-1] lq1_iu_itag, + input lq1_iu_n_flush, + input lq1_iu_np1_flush, + input lq1_iu_exception_val, + input [0:5] lq1_iu_exception, + input lq1_iu_dacr_type, + input [0:3] lq1_iu_dacrw, + input [0:3] lq1_iu_perf_events, + + output iu_lq_i0_completed, + output [0:`ITAG_SIZE_ENC-1] iu_lq_i0_completed_itag, + output iu_lq_i1_completed, + output [0:`ITAG_SIZE_ENC-1] iu_lq_i1_completed_itag, + + output iu_lq_recirc_val, + + // BR Instruction Executed + input br_iu_execute_vld, + input [0:`ITAG_SIZE_ENC-1] br_iu_itag, + input br_iu_redirect, + input [62-`EFF_IFAR_ARCH:61] br_iu_bta, + input br_iu_taken, + input [0:3] br_iu_perf_events, + + // XU0 Instruction Executed + input xu_iu_execute_vld, + input [0:`ITAG_SIZE_ENC-1] xu_iu_itag, + input xu_iu_n_flush, + input xu_iu_np1_flush, + input xu_iu_flush2ucode, + input xu_iu_exception_val, + input [0:4] xu_iu_exception, + input xu_iu_mtiar, + input [62-`EFF_IFAR_ARCH:61] xu_iu_bta, + input [0:3] xu_iu_perf_events, + + // XU0 Instruction Executed + input xu1_iu_execute_vld, + input [0:`ITAG_SIZE_ENC-1] xu1_iu_itag, + + // AXU0 Instruction Executed + input axu0_iu_execute_vld, + input [0:`ITAG_SIZE_ENC-1] axu0_iu_itag, + input axu0_iu_n_flush, + input axu0_iu_np1_flush, + input axu0_iu_n_np1_flush, + input axu0_iu_flush2ucode, + input axu0_iu_flush2ucode_type, + input axu0_iu_exception_val, + input [0:3] axu0_iu_exception, + input [0:3] axu0_iu_perf_events, + + // AXU1 Instruction Executed + input axu1_iu_execute_vld, + input [0:`ITAG_SIZE_ENC-1] axu1_iu_itag, + input axu1_iu_n_flush, + input axu1_iu_np1_flush, + input axu1_iu_flush2ucode, + input axu1_iu_flush2ucode_type, + input axu1_iu_exception_val, + input [0:3] axu1_iu_exception, + input [0:3] axu1_iu_perf_events, + + // Interrupts + input an_ac_uncond_dbg_event, + input xu_iu_external_mchk, + input xu_iu_ext_interrupt, + input xu_iu_dec_interrupt, + input xu_iu_udec_interrupt, + input xu_iu_perf_interrupt, + input xu_iu_fit_interrupt, + input xu_iu_crit_interrupt, + input xu_iu_wdog_interrupt, + input xu_iu_gwdog_interrupt, + input xu_iu_gfit_interrupt, + input xu_iu_gdec_interrupt, + input xu_iu_dbell_interrupt, + input xu_iu_cdbell_interrupt, + input xu_iu_gdbell_interrupt, + input xu_iu_gcdbell_interrupt, + input xu_iu_gmcdbell_interrupt, + input xu_iu_dbsr_ide, + + input [62-`EFF_IFAR_ARCH:61] xu_iu_rest_ifar, + input axu0_iu_async_fex, + + // To Ierats + output cp_is_isync, + output cp_is_csync, + + // Flushes + output iu_flush, + output cp_flush_into_uc, + output [43:61] cp_uc_flush_ifar, + output cp_uc_np1_flush, + output cp_flush, + output [0:`ITAG_SIZE_ENC-1] cp_next_itag, + output [0:`ITAG_SIZE_ENC-1] cp_flush_itag, + output [62-`EFF_IFAR_ARCH:61] cp_flush_ifar, + output cp_iu0_flush_2ucode, + output cp_iu0_flush_2ucode_type, + output cp_iu0_flush_nonspec, + input pc_iu_init_reset, + output cp_rn_uc_credit_free, + + // Signals to SPR partition + output iu_xu_rfi, + output iu_xu_rfgi, + output iu_xu_rfci, + output iu_xu_rfmci, + output iu_xu_int, + output iu_xu_gint, + output iu_xu_cint, + output iu_xu_mcint, + output [62-`EFF_IFAR_ARCH:61] iu_xu_nia, + output [0:16] iu_xu_esr, + output [0:14] iu_xu_mcsr, + output [0:18] iu_xu_dbsr, + output iu_xu_dear_update, + output [64-`GPR_WIDTH:63] iu_xu_dear, + output iu_xu_dbsr_update, + output iu_xu_dbsr_ude, + output iu_xu_dbsr_ide, + output iu_xu_esr_update, + output iu_xu_act, + output iu_xu_dbell_taken, + output iu_xu_cdbell_taken, + output iu_xu_gdbell_taken, + output iu_xu_gcdbell_taken, + output iu_xu_gmcdbell_taken, + output iu_xu_instr_cpl, + input xu_iu_np1_async_flush, + output iu_xu_async_complete, + input dp_cp_hold_req, + output iu_mm_hold_ack, + input dp_cp_bus_snoop_hold_req, + output iu_mm_bus_snoop_hold_ack, + output iu_spr_eheir_update, + output [0:31] iu_spr_eheir, + input xu_iu_msr_de, + input xu_iu_msr_pr, + input xu_iu_msr_cm, + input xu_iu_msr_gs, + input xu_iu_msr_me, + input xu_iu_dbcr0_edm, + input xu_iu_dbcr0_idm, + input xu_iu_dbcr0_icmp, + input xu_iu_dbcr0_brt, + input xu_iu_dbcr0_irpt, + input xu_iu_dbcr0_trap, + input xu_iu_iac1_en, + input xu_iu_iac2_en, + input xu_iu_iac3_en, + input xu_iu_iac4_en, + input [0:1] xu_iu_dbcr0_dac1, + input [0:1] xu_iu_dbcr0_dac2, + input [0:1] xu_iu_dbcr0_dac3, + input [0:1] xu_iu_dbcr0_dac4, + input xu_iu_dbcr0_ret, + input xu_iu_dbcr1_iac12m, + input xu_iu_dbcr1_iac34m, + input lq_iu_spr_dbcr3_ivc, + input xu_iu_epcr_extgs, + input xu_iu_epcr_dtlbgs, + input xu_iu_epcr_itlbgs, + input xu_iu_epcr_dsigs, + input xu_iu_epcr_isigs, + input xu_iu_epcr_duvd, + input xu_iu_epcr_icm, + input xu_iu_epcr_gicm, + input xu_iu_ccr2_en_dcr, + input xu_iu_ccr2_ucode_dis, + input xu_iu_hid_mmu_mode, + input xu_iu_xucr4_mmu_mchk, + + output iu_xu_quiesce, + output iu_pc_quiesce, + + // MMU Errors + input mm_iu_ierat_rel_val, + input mm_iu_ierat_pt_fault, + input mm_iu_ierat_lrat_miss, + input mm_iu_ierat_tlb_inelig, + input mm_iu_tlb_multihit_err, + input mm_iu_tlb_par_err, + input mm_iu_lru_par_err, + input mm_iu_tlb_miss, + input mm_iu_reload_hit, + input [3:4] mm_iu_ierat_mmucr1, + input ic_cp_nonspec_hit, + + output [0:5] cp_mm_except_taken, + + // SPRs + input xu_iu_single_instr_mode, + input spr_single_issue, + input [64-`GPR_WIDTH:51] spr_ivpr, + input [64-`GPR_WIDTH:51] spr_givpr, + input [62-`EFF_IFAR_ARCH:61] spr_iac1, + input [62-`EFF_IFAR_ARCH:61] spr_iac2, + input [62-`EFF_IFAR_ARCH:61] spr_iac3, + input [62-`EFF_IFAR_ARCH:61] spr_iac4, + + // XER read bus to RF for store conditionals + output [0:`XER_POOL_ENC-1] iu_rf_xer_p, + + // Signals from pervasive + input pc_iu_ram_active, + input pc_iu_ram_flush_thread, + input xu_iu_msrovride_enab, + output iu_pc_ram_done, + output iu_pc_ram_interrupt, + output iu_pc_ram_unsupported, + input pc_iu_stop, + input pc_iu_step, + input [0:2] pc_iu_dbg_action, + output iu_pc_step_done, + output [0:`THREADS-1] iu_pc_stop_dbg_event, + output iu_pc_err_debug_event, + output iu_pc_attention_instr, + output iu_pc_err_mchk_disabled, + output ac_an_debug_trigger, + output iu_xu_stop, + + // Power + inout vdd, + inout gnd); + + + + + // Define Offsets for the Queue Entry + parameter entry_ifar_offset = 0; + parameter entry_bp_val_offset = entry_ifar_offset + `EFF_IFAR_WIDTH; + parameter entry_bp_bcctr_offset = entry_bp_val_offset + 1; + parameter entry_bp_bclr_offset = entry_bp_bcctr_offset + 1; + parameter entry_bp_bta_offset = entry_bp_bclr_offset + 1; + parameter entry_rfi_offset = entry_bp_bta_offset + `EFF_IFAR_WIDTH; + parameter entry_rfgi_offset = entry_rfi_offset + 1; + parameter entry_rfci_offset = entry_rfgi_offset + 1; + parameter entry_rfmci_offset = entry_rfci_offset + 1; + parameter entry_ivax_offset = entry_rfmci_offset + 1; + parameter entry_sc_offset = entry_ivax_offset + 1; + parameter entry_mtiar_offset = entry_sc_offset + 1; + parameter entry_rollover_offset = entry_mtiar_offset + 1; + parameter entry_is_csync_offset = entry_rollover_offset + 1; + parameter entry_is_isync_offset = entry_is_csync_offset + 1; + parameter entry_bh_update_offset = entry_is_isync_offset + 1; + parameter entry_bh0_hist_offset = entry_bh_update_offset + 1; + parameter entry_bh1_hist_offset = entry_bh0_hist_offset + 2; + parameter entry_bh2_hist_offset = entry_bh1_hist_offset + 2; + parameter entry_gshare_offset = entry_bh2_hist_offset + 2; + parameter entry_ls_ptr_offset = entry_gshare_offset + 10; + parameter entry_isram_offset = entry_ls_ptr_offset + 3; + parameter entry_lk_offset = entry_isram_offset + 1; + parameter entry_bh_offset = entry_lk_offset + 1; + parameter entry_getnia_offset = entry_bh_offset + 2; + parameter entry_ld_offset = entry_getnia_offset + 1; + parameter entry_st_offset = entry_ld_offset + 1; + parameter entry_epid_offset = entry_st_offset + 1; + parameter entry_ucode_offset = entry_epid_offset + 1; + parameter entry_type_fp_offset = entry_ucode_offset + 3; + parameter entry_type_ap_offset = entry_type_fp_offset + 1; + parameter entry_type_spv_offset = entry_type_ap_offset + 1; + parameter entry_type_st_offset = entry_type_spv_offset + 1; + parameter entry_attn_offset = entry_type_st_offset + 1; + parameter entry_fuse_nop_offset = entry_attn_offset + 1; + parameter entry_icmp_block_offset = entry_fuse_nop_offset + 1; + parameter entry_nonspec_offset = entry_icmp_block_offset + 1; + parameter entry_t1_v_offset = entry_nonspec_offset + 1; + parameter entry_t1_t_offset = entry_t1_v_offset + 1; + parameter entry_t1_p_offset = entry_t1_t_offset + `TYPE_WIDTH; + parameter entry_t1_a_offset = entry_t1_p_offset + `GPR_POOL_ENC; + parameter entry_t2_v_offset = entry_t1_a_offset + `GPR_POOL_ENC; + parameter entry_t2_t_offset = entry_t2_v_offset + 1; + parameter entry_t2_p_offset = entry_t2_t_offset + `TYPE_WIDTH; + parameter entry_t2_a_offset = entry_t2_p_offset + `GPR_POOL_ENC; + parameter entry_t3_v_offset = entry_t2_a_offset + `GPR_POOL_ENC; + parameter entry_t3_t_offset = entry_t3_v_offset + 1; + parameter entry_t3_p_offset = entry_t3_t_offset + `TYPE_WIDTH; + parameter entry_t3_a_offset = entry_t3_p_offset + `GPR_POOL_ENC; + parameter entry_btb_entry_offset = entry_t3_a_offset + `GPR_POOL_ENC; + parameter entry_btb_hist_offset = entry_btb_entry_offset + 1; + parameter entry_length = entry_btb_hist_offset + 2; + // Signals + wire tidn; + wire tiup; + wire func_sl_thold_1; + wire func_slp_sl_thold_1; + wire sg_1; + wire func_sl_force; + wire func_sl_thold_0; + wire func_sl_thold_0_b; + wire func_slp_sl_force; + wire func_slp_sl_thold_0; + wire func_slp_sl_thold_0_b; + wire sg_0; + wire we0; + wire we1; + wire re0; + wire re1; + wire [0:`ITAG_SIZE_ENC-2] wa0; + wire [0:`ITAG_SIZE_ENC-2] wa1; + wire [0:`ITAG_SIZE_ENC-2] ra0; + wire [0:`ITAG_SIZE_ENC-2] ra1; + wire [0:entry_length-1] di0; + wire [0:entry_length-1] di1; + wire [0:entry_length-1] do0; + wire [0:entry_length-1] do1; + wire [62-`EFF_IFAR_WIDTH:61] cp2_i0_ifar; + wire [62-`EFF_IFAR_WIDTH:61] cp2_i1_ifar; + wire cp2_i0_bp_pred; + wire cp2_i1_bp_pred; + wire cp2_i0_br_pred; + wire cp2_i1_br_pred; + wire cp2_i0_bp_val; + wire cp2_i1_bp_val; + wire cp2_i0_bp_bcctr; + wire cp2_i1_bp_bcctr; + wire cp2_i0_bp_bclr; + wire cp2_i1_bp_bclr; + wire [62-`EFF_IFAR_WIDTH:61] cp2_i0_bp_bta; + wire [62-`EFF_IFAR_WIDTH:61] cp2_i1_bp_bta; + wire cp2_i0_rfi; + wire cp2_i1_rfi; + wire cp2_i0_rfgi; + wire cp2_i1_rfgi; + wire cp2_i0_rfci; + wire cp2_i1_rfci; + wire cp2_i0_rfmci; + wire cp2_i1_rfmci; + wire cp2_i0_ivax; + wire cp2_i1_ivax; + wire cp2_i0_sc; + wire cp2_i1_sc; + wire cp2_i0_mtiar; + wire cp2_i1_mtiar; + wire cp2_i0_rollover; + wire cp2_i1_rollover; + wire cp2_i0_is_csync; + wire cp2_i1_is_csync; + wire cp2_i0_is_isync; + wire cp2_i1_is_isync; + wire cp2_i0_bh_update; + wire cp2_i1_bh_update; + wire [0:1] cp2_i0_bh0_hist; + wire [0:1] cp2_i1_bh0_hist; + wire [0:1] cp2_i0_bh1_hist; + wire [0:1] cp2_i1_bh1_hist; + wire [0:1] cp2_i0_bh2_hist; + wire [0:1] cp2_i1_bh2_hist; + wire [0:9] cp2_i0_gshare; + wire [0:9] cp2_i1_gshare; + wire [0:2] cp2_i0_ls_ptr; + wire [0:2] cp2_i1_ls_ptr; + wire [62-`EFF_IFAR_WIDTH:61] cp2_i0_bta; + wire [62-`EFF_IFAR_WIDTH:61] cp2_i1_bta; + wire cp2_i0_isram; + wire cp2_i1_isram; + wire cp2_i0_lk; + wire cp2_i1_lk; + wire [0:1] cp2_i0_bh; + wire [0:1] cp2_i1_bh; + wire cp2_i0_getnia; + wire cp2_i1_getnia; + wire cp2_i0_ld; + wire cp2_i1_ld; + wire cp2_i0_st; + wire cp2_i1_st; + wire cp2_i0_epid; + wire cp2_i1_epid; + wire [0:2] cp2_i0_ucode; + wire [0:2] cp2_i1_ucode; + wire cp2_i0_type_fp; + wire cp2_i1_type_fp; + wire cp2_i0_type_ap; + wire cp2_i1_type_ap; + wire cp2_i0_type_spv; + wire cp2_i1_type_spv; + wire cp2_i0_type_st; + wire cp2_i1_type_st; + wire cp2_i0_attn; + wire cp2_i1_attn; + wire cp2_i0_fuse_nop; + wire cp2_i1_fuse_nop; + wire cp2_i0_icmp_block; + wire cp2_i1_icmp_block; + wire cp2_i0_nonspec; + wire cp2_i1_nonspec; + wire cp2_i0_t1_v; + wire cp2_i1_t1_v; + wire [0:`TYPE_WIDTH-1] cp2_i0_t1_t; + wire [0:`TYPE_WIDTH-1] cp2_i1_t1_t; + wire [0:`GPR_POOL_ENC-1] cp2_i0_t1_p; + wire [0:`GPR_POOL_ENC-1] cp2_i1_t1_p; + wire [0:`GPR_POOL_ENC-1] cp2_i0_t1_a; + wire [0:`GPR_POOL_ENC-1] cp2_i1_t1_a; + wire cp2_i0_t2_v; + wire cp2_i1_t2_v; + wire [0:`TYPE_WIDTH-1] cp2_i0_t2_t; + wire [0:`TYPE_WIDTH-1] cp2_i1_t2_t; + wire [0:`GPR_POOL_ENC-1] cp2_i0_t2_p; + wire [0:`GPR_POOL_ENC-1] cp2_i1_t2_p; + wire [0:`GPR_POOL_ENC-1] cp2_i0_t2_a; + wire [0:`GPR_POOL_ENC-1] cp2_i1_t2_a; + wire cp2_i0_t3_v; + wire cp2_i1_t3_v; + wire [0:`TYPE_WIDTH-1] cp2_i0_t3_t; + wire [0:`TYPE_WIDTH-1] cp2_i1_t3_t; + wire [0:`GPR_POOL_ENC-1] cp2_i0_t3_p; + wire [0:`GPR_POOL_ENC-1] cp2_i1_t3_p; + wire [0:`GPR_POOL_ENC-1] cp2_i0_t3_a; + wire [0:`GPR_POOL_ENC-1] cp2_i1_t3_a; + wire cp2_i0_btb_entry; + wire cp2_i1_btb_entry; + wire [0:1] cp2_i0_btb_hist; + wire [0:1] cp2_i1_btb_hist; + wire cp2_i0_completed; + wire cp2_i1_completed; + wire [1:`ITAG_SIZE_ENC-1] cp0_i0_completed_itag; + wire [1:`ITAG_SIZE_ENC-1] cp0_i1_completed_itag; + wire cp2_i0_axu_exception_val; + wire [0:3] cp2_i0_axu_exception; + wire cp2_i1_axu_exception_val; + wire [0:3] cp2_i1_axu_exception; + + wire b_i0; + wire bc_i0; + wire bclr_i0; + wire bcctr_i0; + wire br_val_i0; + wire br_add_chk_i0; + wire rfi_i0; + wire rfgi_i0; + wire rfci_i0; + wire rfmci_i0; + wire mtiar_i0; + wire isync_i0; + wire sc_i0; + wire sc_hyp_i0; + wire sc_illegal_i0; + wire dcr_illegal_i0; + wire attn_i0; + wire icmp_block_i0; + wire nonspec_i0; + wire ehpriv_i0; + wire mtmsr_i0; + wire ivax_i0; + wire mtpid_i0; + wire mtlpidr_i0; + wire async_block_i0; + wire i0_np1_flush; + wire is_csync_i0; + wire is_isync_i0; + wire b_i1; + wire bc_i1; + wire bclr_i1; + wire bcctr_i1; + wire br_val_i1; + wire br_add_chk_i1; + wire rfi_i1; + wire rfgi_i1; + wire rfci_i1; + wire rfmci_i1; + wire mtiar_i1; + wire isync_i1; + wire sc_i1; + wire sc_hyp_i1; + wire sc_illegal_i1; + wire dcr_illegal_i1; + wire attn_i1; + wire icmp_block_i1; + wire nonspec_i1; + wire ehpriv_i1; + wire mtmsr_i1; + wire ivax_i1; + wire mtpid_i1; + wire mtlpidr_i1; + wire async_block_i1; + wire i1_np1_flush; + wire is_csync_i1; + wire is_isync_i1; + wire folded_op_i0; + wire folded_op_i1; + wire rollover_i0; + wire rollover_i1; + + wire [0:`XER_POOL_ENC-1] xer_cp_p_q; + wire [0:`XER_POOL_ENC-1] xer_cp_p_d; + + // Branch predict calcs + wire [62-`EFF_IFAR_WIDTH:61] bta_bd_i0; + wire [62-`EFF_IFAR_WIDTH:61] bta_bd_i1; + wire [62-`EFF_IFAR_WIDTH:61] bta_li_i0; + wire [62-`EFF_IFAR_WIDTH:61] bta_li_i1; + wire [62-`EFF_IFAR_WIDTH:61] bta_abs_i0; + wire [62-`EFF_IFAR_WIDTH:61] bta_abs_i1; + wire [62-`EFF_IFAR_WIDTH:61] bta_off_i0; + wire [62-`EFF_IFAR_WIDTH:61] bta_off_i1; + wire [62-`EFF_IFAR_WIDTH:61] bta_i0; + wire [62-`EFF_IFAR_WIDTH:61] bta_i1; + + wire cp_i0_lk; + wire [0:1] cp_i0_bh; + wire cp_i0_getnia; + wire cp_i0_ld; + wire cp_i0_st; + wire cp_i0_epid; + + wire cp_i1_lk; + wire [0:1] cp_i1_bh; + wire cp_i1_getnia; + wire cp_i1_ld; + wire cp_i1_st; + wire cp_i1_epid; + + wire iu_xu_quiesce_int; + wire cpl_perr; + + // Scanchains + parameter xer_cp_p_offset = 0; + parameter scan_right = xer_cp_p_offset + `XER_POOL_ENC; + wire [0:scan_right-1] siv; + wire [0:scan_right-1] sov; + wire scan_con_a; + + wire force_t, thold_0_b, funcslp_force; + + assign tidn = 1'b0; + assign tiup = 1'b1; + + assign siv = {scan_right{1'b0}}; + + assign iu_xu_quiesce = iu_xu_quiesce_int; + assign iu_pc_quiesce = iu_xu_quiesce_int; + + assign xer_cp_p_d = (cp2_i1_t2_v == 1'b1 & cp2_i1_completed == 1'b1 & cp2_i1_t2_t == 3'b100) ? cp2_i1_t2_p[`GPR_POOL_ENC - `XER_POOL_ENC:`GPR_POOL_ENC - 1] : + (cp2_i0_t2_v == 1'b1 & cp2_i0_completed == 1'b1 & cp2_i0_t2_t == 3'b100) ? cp2_i0_t2_p[`GPR_POOL_ENC - `XER_POOL_ENC:`GPR_POOL_ENC - 1] : + xer_cp_p_q; + assign iu_rf_xer_p = xer_cp_p_q; + + assign is_csync_i0 = (~mm_iu_ierat_mmucr1[3] & ~xu_iu_hid_mmu_mode) & + (sc_i0 | ehpriv_i0 | mtmsr_i0 | mtpid_i0 | mtlpidr_i0 | rfi_i0 | rfgi_i0 | rfci_i0 | rfmci_i0); + assign is_csync_i1 = (~mm_iu_ierat_mmucr1[3] & ~xu_iu_hid_mmu_mode) & + (sc_i1 | ehpriv_i1 | mtmsr_i1 | mtpid_i1 | mtlpidr_i1 | rfi_i1 | rfgi_i1 | rfci_i1 | rfmci_i1); + + assign is_isync_i0 = (~mm_iu_ierat_mmucr1[4] & ~xu_iu_hid_mmu_mode) & isync_i0; + assign is_isync_i1 = (~mm_iu_ierat_mmucr1[4] & ~xu_iu_hid_mmu_mode) & isync_i1; + + assign b_i0 = rn_cp_iu6_i0_instr[0:5] == 6'b010010; + assign bc_i0 = rn_cp_iu6_i0_instr[0:5] == 6'b010000; + assign bclr_i0 = rn_cp_iu6_i0_instr[0:5] == 6'b010011 & rn_cp_iu6_i0_instr[21:30] == 10'b0000010000; + assign bcctr_i0 = (rn_cp_iu6_i0_instr[0:5] == 6'b010011 & rn_cp_iu6_i0_instr[21:30] == 10'b1000010000) | + (rn_cp_iu6_i0_instr[0:5] == 6'b010011 & rn_cp_iu6_i0_instr[21:30] == 10'b1000110000); //bctar + assign br_val_i0 = b_i0 | bc_i0 | bclr_i0 | bcctr_i0; + assign br_add_chk_i0 = rn_cp_iu6_i0_bta_val; + assign rfi_i0 = rn_cp_iu6_i0_instr[0:5] == 6'b010011 & rn_cp_iu6_i0_instr[21:30] == 10'b0000110010 & (~(xu_iu_msr_gs == 1'b1 & xu_iu_msr_pr == 1'b0)); + assign rfgi_i0 = (rn_cp_iu6_i0_instr[0:5] == 6'b010011 & rn_cp_iu6_i0_instr[21:30] == 10'b0001100110) | + (rn_cp_iu6_i0_instr[0:5] == 6'b010011 & rn_cp_iu6_i0_instr[21:30] == 10'b0000110010 & xu_iu_msr_gs == 1'b1 & xu_iu_msr_pr == 1'b0); + assign rfci_i0 = rn_cp_iu6_i0_instr[0:5] == 6'b010011 & rn_cp_iu6_i0_instr[21:30] == 10'b0000110011; + assign rfmci_i0 = rn_cp_iu6_i0_instr[0:5] == 6'b010011 & rn_cp_iu6_i0_instr[21:30] == 10'b0000100110; + assign mtiar_i0 = rn_cp_iu6_i0_instr[0:5] == 6'b011111 & rn_cp_iu6_i0_instr[11:20] == 10'b1001011011 & rn_cp_iu6_i0_instr[21:30] == 10'b0111010011; + assign isync_i0 = rn_cp_iu6_i0_instr[0:5] == 6'b010011 & rn_cp_iu6_i0_instr[21:30] == 10'b0010010110; + assign sc_i0 = rn_cp_iu6_i0_instr[0:5] == 6'b010001 & rn_cp_iu6_i0_instr[20:26] == 7'b0000000 & rn_cp_iu6_i0_instr[30] == 1'b1; + assign sc_hyp_i0 = rn_cp_iu6_i0_instr[0:5] == 6'b010001 & rn_cp_iu6_i0_instr[20:26] == 7'b0000001 & rn_cp_iu6_i0_instr[30] == 1'b1; + assign sc_illegal_i0 = rn_cp_iu6_i0_instr[0:5] == 6'b010001 & |(rn_cp_iu6_i0_instr[20:25]) & rn_cp_iu6_i0_instr[30] == 1'b1; + assign dcr_illegal_i0 = rn_cp_iu6_i0_instr[0:5] == 6'b011111 & xu_iu_ccr2_en_dcr == 1'b1 & + (rn_cp_iu6_i0_instr[21:30] == 10'b0101000011 | rn_cp_iu6_i0_instr[21:30] == 10'b0111000011 | + rn_cp_iu6_i0_instr[21:30] == 10'b0100100011 | rn_cp_iu6_i0_instr[21:30] == 10'b0110100011 | + rn_cp_iu6_i0_instr[21:30] == 10'b0100000011 | rn_cp_iu6_i0_instr[21:30] == 10'b0110000011); + assign attn_i0 = rn_cp_iu6_i0_instr[0:5] == 6'b000000 & rn_cp_iu6_i0_instr[21:30] == 10'b0100000000; + assign icmp_block_i0 = sc_i0 | sc_hyp_i0 | ehpriv_i0 | attn_i0; + assign nonspec_i0 = rn_cp_iu6_i0_error == 3'b111 & ~rn_cp_iu6_i0_isram; + assign ehpriv_i0 = rn_cp_iu6_i0_instr[0:5] == 6'b011111 & rn_cp_iu6_i0_instr[21:30] == 10'b0100001110; + assign mtmsr_i0 = rn_cp_iu6_i0_instr[0:5] == 6'b011111 & rn_cp_iu6_i0_instr[21:30] == 10'b0010010010; // mtmsr + + assign ivax_i0 = (rn_cp_iu6_i0_instr[0:5] == 6'b011111 & rn_cp_iu6_i0_instr[21:30] == 10'b1100110011) | + (rn_cp_iu6_i0_instr[0:5] == 6'b011111 & rn_cp_iu6_i0_instr[21:30] == 10'b1100010010); + assign mtpid_i0 = rn_cp_iu6_i0_instr[0:5] == 6'b011111 & rn_cp_iu6_i0_instr[21:30] == 10'b0111010011 & rn_cp_iu6_i0_instr[11:20] == 10'b1000000001; + assign mtlpidr_i0 = rn_cp_iu6_i0_instr[0:5] == 6'b011111 & rn_cp_iu6_i0_instr[21:30] == 10'b0111010011 & rn_cp_iu6_i0_instr[11:20] == 10'b1001001010; + + assign cp_i0_lk = rn_cp_iu6_i0_instr[31]; + assign cp_i0_bh = rn_cp_iu6_i0_instr[19:20]; + assign cp_i0_getnia = rn_cp_iu6_i0_instr[0:31] == 32'b01000010100111110000000000000101; + + iuq_cpl_dec iuq_cpl_dec0( + // Exception Decode input + .cp2_instr(rn_cp_iu6_i0_instr), + // Exception Decode output + .cp2_ld(cp_i0_ld), + .cp2_st(cp_i0_st), + .cp2_epid(cp_i0_epid) + ); + + assign async_block_i0 = rn_cp_iu6_i0_async_block; + assign i0_np1_flush = rn_cp_iu6_i0_np1_flush; + + // Folded ops complete on issue + assign folded_op_i0 = (~rn_cp_iu6_i0_rte_lq & ~rn_cp_iu6_i0_rte_sq & ~rn_cp_iu6_i0_rte_fx0 & + ~rn_cp_iu6_i0_rte_fx1 & ~rn_cp_iu6_i0_rte_axu0 & ~rn_cp_iu6_i0_rte_axu1) | ~rn_cp_iu6_i0_valop | (rn_cp_iu6_i0_error != 3'b000); + + assign b_i1 = rn_cp_iu6_i1_instr[0:5] == 6'b010010; + assign bc_i1 = rn_cp_iu6_i1_instr[0:5] == 6'b010000; + assign bclr_i1 = rn_cp_iu6_i1_instr[0:5] == 6'b010011 & rn_cp_iu6_i1_instr[21:30] == 10'b0000010000; + assign bcctr_i1 = (rn_cp_iu6_i1_instr[0:5] == 6'b010011 & rn_cp_iu6_i1_instr[21:30] == 10'b1000010000) | + (rn_cp_iu6_i1_instr[0:5] == 6'b010011 & rn_cp_iu6_i1_instr[21:30] == 10'b1000110000); //bctar + assign br_val_i1 = b_i1 | bc_i1 | bclr_i1 | bcctr_i1; + assign br_add_chk_i1 = rn_cp_iu6_i1_bta_val; + assign rfi_i1 = rn_cp_iu6_i1_instr[0:5] == 6'b010011 & rn_cp_iu6_i1_instr[21:30] == 10'b0000110010 & (~(xu_iu_msr_gs == 1'b1 & xu_iu_msr_pr == 1'b0)); + assign rfgi_i1 = (rn_cp_iu6_i1_instr[0:5] == 6'b010011 & rn_cp_iu6_i1_instr[21:30] == 10'b0001100110) | + (rn_cp_iu6_i1_instr[0:5] == 6'b010011 & rn_cp_iu6_i1_instr[21:30] == 10'b0000110010 & xu_iu_msr_gs == 1'b1 & xu_iu_msr_pr == 1'b0); + assign rfci_i1 = rn_cp_iu6_i1_instr[0:5] == 6'b010011 & rn_cp_iu6_i1_instr[21:30] == 10'b0000110011; + assign rfmci_i1 = rn_cp_iu6_i1_instr[0:5] == 6'b010011 & rn_cp_iu6_i1_instr[21:30] == 10'b0000100110; + assign mtiar_i1 = rn_cp_iu6_i1_instr[0:5] == 6'b011111 & rn_cp_iu6_i1_instr[11:20] == 10'b1001011011 & rn_cp_iu6_i1_instr[21:30] == 10'b0111010011; + assign isync_i1 = rn_cp_iu6_i1_instr[0:5] == 6'b010011 & rn_cp_iu6_i1_instr[21:30] == 10'b0010010110; + assign sc_i1 = rn_cp_iu6_i1_instr[0:5] == 6'b010001 & rn_cp_iu6_i1_instr[20:26] == 7'b0000000 & rn_cp_iu6_i1_instr[30] == 1'b1; + assign sc_hyp_i1 = rn_cp_iu6_i1_instr[0:5] == 6'b010001 & rn_cp_iu6_i1_instr[20:26] == 7'b0000001 & rn_cp_iu6_i1_instr[30] == 1'b1; + assign sc_illegal_i1 = rn_cp_iu6_i1_instr[0:5] == 6'b010001 & |rn_cp_iu6_i1_instr[20:25] & rn_cp_iu6_i1_instr[30] == 1'b1; + assign dcr_illegal_i1 = rn_cp_iu6_i1_instr[0:5] == 6'b011111 & xu_iu_ccr2_en_dcr == 1'b1 & + (rn_cp_iu6_i1_instr[21:30] == 10'b0101000011 | rn_cp_iu6_i1_instr[21:30] == 10'b0111000011 | + rn_cp_iu6_i1_instr[21:30] == 10'b0100100011 | rn_cp_iu6_i1_instr[21:30] == 10'b0110100011 | + rn_cp_iu6_i1_instr[21:30] == 10'b0100000011 | rn_cp_iu6_i1_instr[21:30] == 10'b0110000011); + assign attn_i1 = rn_cp_iu6_i1_instr[0:5] == 6'b000000 & rn_cp_iu6_i1_instr[21:30] == 10'b0100000000; + assign icmp_block_i1 = sc_i1 | sc_hyp_i1 | ehpriv_i1 | attn_i1; + assign nonspec_i1 = rn_cp_iu6_i1_error == 3'b111 & ~rn_cp_iu6_i1_isram; + assign ehpriv_i1 = rn_cp_iu6_i1_instr[0:5] == 6'b011111 & rn_cp_iu6_i1_instr[21:30] == 10'b0100001110; + assign mtmsr_i1 = rn_cp_iu6_i1_instr[0:5] == 6'b011111 & rn_cp_iu6_i1_instr[21:30] == 10'b0010010010; // mtmsr + assign ivax_i1 = (rn_cp_iu6_i1_instr[0:5] == 6'b011111 & rn_cp_iu6_i1_instr[21:30] == 10'b1100110011) | + (rn_cp_iu6_i1_instr[0:5] == 6'b011111 & rn_cp_iu6_i1_instr[21:30] == 10'b1100010010); + assign mtpid_i1 = rn_cp_iu6_i1_instr[0:5] == 6'b011111 & rn_cp_iu6_i1_instr[21:30] == 10'b0111010011 & rn_cp_iu6_i1_instr[11:20] == 10'b1000000001; + assign mtlpidr_i1 = rn_cp_iu6_i1_instr[0:5] == 6'b011111 & rn_cp_iu6_i1_instr[21:30] == 10'b0111010011 & rn_cp_iu6_i1_instr[11:20] == 10'b1001001010; + + assign cp_i1_lk = rn_cp_iu6_i1_instr[31]; + assign cp_i1_bh = rn_cp_iu6_i1_instr[19:20]; + assign cp_i1_getnia = rn_cp_iu6_i1_instr[0:31] == 32'b01000010100111110000000000000101; + + iuq_cpl_dec iuq_cpl_dec1( + // Exception Decode input + .cp2_instr(rn_cp_iu6_i1_instr), + // Exception Decode output + .cp2_ld(cp_i1_ld), + .cp2_st(cp_i1_st), + .cp2_epid(cp_i1_epid) + ); + + assign async_block_i1 = rn_cp_iu6_i1_async_block; + assign i1_np1_flush = rn_cp_iu6_i1_np1_flush; + + // Folded ops complete on issue + assign folded_op_i1 = (~rn_cp_iu6_i1_rte_lq & ~rn_cp_iu6_i1_rte_sq & ~rn_cp_iu6_i1_rte_fx0 & ~rn_cp_iu6_i1_rte_fx1 & + ~rn_cp_iu6_i1_rte_axu0 & ~rn_cp_iu6_i1_rte_axu1) | ~rn_cp_iu6_i1_valop | (rn_cp_iu6_i1_error != 3'b000); + + assign rollover_i0 = (rn_cp_iu6_i0_ifar == {`EFF_IFAR_WIDTH{1'b1}}); + assign rollover_i1 = (rn_cp_iu6_i1_ifar == {`EFF_IFAR_WIDTH{1'b1}}); + + //----------------------------------------------- + // calculate branch target address + //----------------------------------------------- + generate + begin : xhdl0 + genvar i; + for (i = 62 - `EFF_IFAR_WIDTH; i <= 61; i = i + 1) + begin : sign_extend_i0 + if (i < 48) + begin : bd_i0_0 + assign bta_bd_i0[i] = rn_cp_iu6_i0_instr[16]; + end + if (i > 47) + begin : bd_i0_1 + assign bta_bd_i0[i] = rn_cp_iu6_i0_instr[i - 32]; + end + if (i < 38) + begin : li_i0_0 + assign bta_li_i0[i] = rn_cp_iu6_i0_instr[6]; + end + if (i > 37) + begin : li_i0_1 + assign bta_li_i0[i] = rn_cp_iu6_i0_instr[i - 32]; + end + end + end + endgenerate + + assign bta_abs_i0[62 - `EFF_IFAR_WIDTH:61] = (b_i0 == 1'b1) ? bta_li_i0[62 - `EFF_IFAR_WIDTH:61] : + bta_bd_i0[62 - `EFF_IFAR_WIDTH:61]; + + assign bta_off_i0[62 - `EFF_IFAR_WIDTH:61] = bta_abs_i0[62 - `EFF_IFAR_WIDTH:61] + rn_cp_iu6_i0_ifar[62 - `EFF_IFAR_WIDTH:61]; + + assign bta_i0[62 - `EFF_IFAR_WIDTH:61] = (rn_cp_iu6_i0_bta_val == 1'b1) ? rn_cp_iu6_i0_bta : + (rn_cp_iu6_i0_instr[30] == 1'b1) ? bta_abs_i0[62 - `EFF_IFAR_WIDTH:61] : + bta_off_i0[62 - `EFF_IFAR_WIDTH:61]; + + generate + begin : xhdl1 + genvar i; + for (i = 62 - `EFF_IFAR_WIDTH; i <= 61; i = i + 1) + begin : sign_extend_i1 + if (i < 48) + begin : bd_i1_0 + assign bta_bd_i1[i] = rn_cp_iu6_i1_instr[16]; + end + if (i > 47) + begin : bd_i1_1 + assign bta_bd_i1[i] = rn_cp_iu6_i1_instr[i - 32]; + end + if (i < 38) + begin : li_i1_0 + assign bta_li_i1[i] = rn_cp_iu6_i1_instr[6]; + end + if (i > 37) + begin : li_i1_1 + assign bta_li_i1[i] = rn_cp_iu6_i1_instr[i - 32]; + end + end + end + endgenerate + + assign bta_abs_i1[62 - `EFF_IFAR_WIDTH:61] = (b_i1 == 1'b1) ? bta_li_i1[62 - `EFF_IFAR_WIDTH:61] : + bta_bd_i1[62 - `EFF_IFAR_WIDTH:61]; + + assign bta_off_i1[62 - `EFF_IFAR_WIDTH:61] = bta_abs_i1[62 - `EFF_IFAR_WIDTH:61] + rn_cp_iu6_i1_ifar[62 - `EFF_IFAR_WIDTH:61]; + + assign bta_i1[62 - `EFF_IFAR_WIDTH:61] = (rn_cp_iu6_i1_bta_val == 1'b1) ? rn_cp_iu6_i1_bta : + (rn_cp_iu6_i1_instr[30] == 1'b1) ? bta_abs_i1[62 - `EFF_IFAR_WIDTH:61] : + bta_off_i1[62 - `EFF_IFAR_WIDTH:61]; + + + iuq_cpl_ctrl iuq_cpl_ctrl( + .nclk(nclk), + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .func_sl_force(func_sl_force), + .func_sl_thold_0_b(func_sl_thold_0_b), + .func_slp_sl_force(func_slp_sl_force), + .func_slp_sl_thold_0_b(func_slp_sl_thold_0_b), + .sg_0(sg_0), + .scan_in(scan_in), + .scan_out(scan_con_a), + .pc_iu_event_bus_enable(pc_iu_event_bus_enable), + .pc_iu_event_count_mode(pc_iu_event_count_mode), + .spr_cp_perf_event_mux_ctrls(spr_cp_perf_event_mux_ctrls), + .event_bus_in(event_bus_in), + .event_bus_out(event_bus_out), + .rn_cp_iu6_i0_vld(rn_cp_iu6_i0_vld), + .rn_cp_iu6_i0_itag(rn_cp_iu6_i0_itag), + .rn_cp_iu6_i0_ifar(rn_cp_iu6_i0_ifar), + .rn_cp_iu6_i0_instr(rn_cp_iu6_i0_instr), + .rn_cp_iu6_i0_ucode(rn_cp_iu6_i0_ucode), + .rn_cp_iu6_i0_fuse_nop(rn_cp_iu6_i0_fuse_nop), + .rn_cp_iu6_i0_error(rn_cp_iu6_i0_error), + .rn_cp_iu6_i0_valop(rn_cp_iu6_i0_valop), + .rn_cp_iu6_i0_is_rfi(rfi_i0), + .rn_cp_iu6_i0_is_rfgi(rfgi_i0), + .rn_cp_iu6_i0_is_rfci(rfci_i0), + .rn_cp_iu6_i0_is_rfmci(rfmci_i0), + .rn_cp_iu6_i0_is_isync(isync_i0), + .rn_cp_iu6_i0_is_sc(sc_i0), + .rn_cp_iu6_i0_is_np1_flush(i0_np1_flush), + .rn_cp_iu6_i0_is_sc_hyp(sc_hyp_i0), + .rn_cp_iu6_i0_is_sc_ill(sc_illegal_i0), + .rn_cp_iu6_i0_is_dcr_ill(dcr_illegal_i0), + .rn_cp_iu6_i0_is_attn(attn_i0), + .rn_cp_iu6_i0_is_ehpriv(ehpriv_i0), + .rn_cp_iu6_i0_is_folded(folded_op_i0), + .rn_cp_iu6_i0_async_block(async_block_i0), + .rn_cp_iu6_i0_is_br(br_val_i0), + .rn_cp_iu6_i0_br_add_chk(br_add_chk_i0), + .rn_cp_iu6_i0_pred(rn_cp_iu6_i0_br_pred), + .rn_cp_iu6_i0_rollover(rollover_i0), + .rn_cp_iu6_i0_isram(rn_cp_iu6_i0_isram), + .rn_cp_iu6_i0_match(rn_cp_iu6_i0_match), + .rn_cp_iu6_i1_vld(rn_cp_iu6_i1_vld), + .rn_cp_iu6_i1_itag(rn_cp_iu6_i1_itag), + .rn_cp_iu6_i1_ifar(rn_cp_iu6_i1_ifar), + .rn_cp_iu6_i1_instr(rn_cp_iu6_i1_instr), + .rn_cp_iu6_i1_ucode(rn_cp_iu6_i1_ucode), + .rn_cp_iu6_i1_fuse_nop(rn_cp_iu6_i1_fuse_nop), + .rn_cp_iu6_i1_error(rn_cp_iu6_i1_error), + .rn_cp_iu6_i1_valop(rn_cp_iu6_i1_valop), + .rn_cp_iu6_i1_is_rfi(rfi_i1), + .rn_cp_iu6_i1_is_rfgi(rfgi_i1), + .rn_cp_iu6_i1_is_rfci(rfci_i1), + .rn_cp_iu6_i1_is_rfmci(rfmci_i1), + .rn_cp_iu6_i1_is_isync(isync_i1), + .rn_cp_iu6_i1_is_sc(sc_i1), + .rn_cp_iu6_i1_is_np1_flush(i1_np1_flush), + .rn_cp_iu6_i1_is_sc_hyp(sc_hyp_i1), + .rn_cp_iu6_i1_is_sc_ill(sc_illegal_i1), + .rn_cp_iu6_i1_is_dcr_ill(dcr_illegal_i1), + .rn_cp_iu6_i1_is_attn(attn_i1), + .rn_cp_iu6_i1_is_ehpriv(ehpriv_i1), + .rn_cp_iu6_i1_is_folded(folded_op_i1), + .rn_cp_iu6_i1_async_block(async_block_i1), + .rn_cp_iu6_i1_is_br(br_val_i1), + .rn_cp_iu6_i1_br_add_chk(br_add_chk_i1), + .rn_cp_iu6_i1_pred(rn_cp_iu6_i1_br_pred), + .rn_cp_iu6_i1_rollover(rollover_i1), + .rn_cp_iu6_i1_isram(rn_cp_iu6_i1_isram), + .rn_cp_iu6_i1_match(rn_cp_iu6_i1_match), + .cp2_i0_completed(cp2_i0_completed), + .cp2_i1_completed(cp2_i1_completed), + .cp0_i0_completed_itag(cp0_i0_completed_itag), + .cp0_i1_completed_itag(cp0_i1_completed_itag), + .cp2_i0_ifar(cp2_i0_ifar), + .cp2_i1_ifar(cp2_i1_ifar), + .cp2_i0_bp_bta(cp2_i0_bp_bta), + .cp2_i1_bp_bta(cp2_i1_bp_bta), + .cp2_i0_rfi(cp2_i0_rfi), + .cp2_i0_rfgi(cp2_i0_rfgi), + .cp2_i0_rfci(cp2_i0_rfci), + .cp2_i0_rfmci(cp2_i0_rfmci), + .cp2_i0_sc(cp2_i0_sc), + .cp2_i0_mtiar(cp2_i0_mtiar), + .cp2_i0_rollover(cp2_i0_rollover), + .cp2_i1_rfi(cp2_i1_rfi), + .cp2_i1_rfgi(cp2_i1_rfgi), + .cp2_i1_rfci(cp2_i1_rfci), + .cp2_i1_rfmci(cp2_i1_rfmci), + .cp2_i1_sc(cp2_i1_sc), + .cp2_i1_mtiar(cp2_i1_mtiar), + .cp2_i1_rollover(cp2_i1_rollover), + .cp2_i0_bp_pred(cp2_i0_bp_pred), + .cp2_i1_bp_pred(cp2_i1_bp_pred), + .cp2_i0_br_pred(cp2_i0_br_pred), + .cp2_i1_br_pred(cp2_i1_br_pred), + .cp2_i0_bta(cp2_i0_bta), + .cp2_i1_bta(cp2_i1_bta), + .cp2_i0_isram(cp2_i0_isram), + .cp2_i1_isram(cp2_i1_isram), + .cp2_i0_ld(cp2_i0_ld), + .cp2_i1_ld(cp2_i1_ld), + .cp2_i0_st(cp2_i0_st), + .cp2_i1_st(cp2_i1_st), + .cp2_i0_epid(cp2_i0_epid), + .cp2_i1_epid(cp2_i1_epid), + .cp2_i0_ucode(cp2_i0_ucode), + .cp2_i1_ucode(cp2_i1_ucode), + .cp2_i0_type_fp(cp2_i0_type_fp), + .cp2_i1_type_fp(cp2_i1_type_fp), + .cp2_i0_type_ap(cp2_i0_type_ap), + .cp2_i1_type_ap(cp2_i1_type_ap), + .cp2_i0_type_spv(cp2_i0_type_spv), + .cp2_i1_type_spv(cp2_i1_type_spv), + .cp2_i0_type_st(cp2_i0_type_st), + .cp2_i1_type_st(cp2_i1_type_st), + .cp2_i0_attn(cp2_i0_attn), + .cp2_i1_attn(cp2_i1_attn), + .cp2_i0_fuse_nop(cp2_i0_fuse_nop), + .cp2_i1_fuse_nop(cp2_i1_fuse_nop), + .cp2_i0_icmp_block(cp2_i0_icmp_block), + .cp2_i1_icmp_block(cp2_i1_icmp_block), + .cp2_i0_axu_exception_val(cp2_i0_axu_exception_val), + .cp2_i0_axu_exception(cp2_i0_axu_exception), + .cp2_i1_axu_exception_val(cp2_i1_axu_exception_val), + .cp2_i1_axu_exception(cp2_i1_axu_exception), + .cp2_i0_nonspec(cp2_i0_nonspec), + .cp2_i1_nonspec(cp2_i1_nonspec), + .lq0_iu_execute_vld(lq0_iu_execute_vld), + .lq0_iu_itag(lq0_iu_itag), + .lq0_iu_n_flush(lq0_iu_n_flush), + .lq0_iu_np1_flush(lq0_iu_np1_flush), + .lq0_iu_dacr_type(lq0_iu_dacr_type), + .lq0_iu_dacrw(lq0_iu_dacrw), + .lq0_iu_instr(lq0_iu_instr), + .lq0_iu_eff_addr(lq0_iu_eff_addr), + .lq0_iu_exception_val(lq0_iu_exception_val), + .lq0_iu_exception(lq0_iu_exception), + .lq0_iu_flush2ucode(lq0_iu_flush2ucode), + .lq0_iu_flush2ucode_type(lq0_iu_flush2ucode_type), + .lq0_iu_recirc_val(lq0_iu_recirc_val), + .lq0_iu_dear_val(lq0_iu_dear_val), + .lq1_iu_execute_vld(lq1_iu_execute_vld), + .lq1_iu_itag(lq1_iu_itag), + .lq1_iu_n_flush(lq1_iu_n_flush), + .lq1_iu_np1_flush(lq1_iu_np1_flush), + .lq1_iu_exception_val(lq1_iu_exception_val), + .lq1_iu_exception(lq1_iu_exception), + .lq1_iu_dacr_type(lq1_iu_dacr_type), + .lq1_iu_dacrw(lq1_iu_dacrw), + .lq1_iu_perf_events(lq1_iu_perf_events), + .iu_lq_i0_completed(iu_lq_i0_completed), + .iu_lq_i0_completed_itag(iu_lq_i0_completed_itag), + .iu_lq_i1_completed(iu_lq_i1_completed), + .iu_lq_i1_completed_itag(iu_lq_i1_completed_itag), + .iu_lq_recirc_val(iu_lq_recirc_val), + .br_iu_execute_vld(br_iu_execute_vld), + .br_iu_itag(br_iu_itag), + .br_iu_redirect(br_iu_redirect), + .br_iu_bta(br_iu_bta), + .br_iu_taken(br_iu_taken), + .br_iu_perf_events(br_iu_perf_events), + .xu_iu_execute_vld(xu_iu_execute_vld), + .xu_iu_itag(xu_iu_itag), + .xu_iu_n_flush(xu_iu_n_flush), + .xu_iu_np1_flush(xu_iu_np1_flush), + .xu_iu_flush2ucode(xu_iu_flush2ucode), + .xu_iu_exception_val(xu_iu_exception_val), + .xu_iu_exception(xu_iu_exception), + .xu_iu_mtiar(xu_iu_mtiar), + .xu_iu_bta(xu_iu_bta), + .xu1_iu_execute_vld(xu1_iu_execute_vld), + .xu1_iu_itag(xu1_iu_itag), + .xu_iu_rest_ifar(xu_iu_rest_ifar), + .xu_iu_perf_events(xu_iu_perf_events), + .axu0_iu_async_fex(axu0_iu_async_fex), + .axu0_iu_execute_vld(axu0_iu_execute_vld), + .axu0_iu_itag(axu0_iu_itag), + .axu0_iu_n_flush(axu0_iu_n_flush), + .axu0_iu_np1_flush(axu0_iu_np1_flush), + .axu0_iu_n_np1_flush(axu0_iu_n_np1_flush), + .axu0_iu_flush2ucode(axu0_iu_flush2ucode), + .axu0_iu_flush2ucode_type(axu0_iu_flush2ucode_type), + .axu0_iu_exception_val(axu0_iu_exception_val), + .axu0_iu_exception(axu0_iu_exception), + .axu0_iu_perf_events(axu0_iu_perf_events), + .axu1_iu_execute_vld(axu1_iu_execute_vld), + .axu1_iu_itag(axu1_iu_itag), + .axu1_iu_n_flush(axu1_iu_n_flush), + .axu1_iu_np1_flush(axu1_iu_np1_flush), + .axu1_iu_n_np1_flush(1'b0), + .axu1_iu_flush2ucode(axu1_iu_flush2ucode), + .axu1_iu_flush2ucode_type(axu1_iu_flush2ucode_type), + .axu1_iu_exception_val(axu1_iu_exception_val), + .axu1_iu_exception(axu1_iu_exception), + .axu1_iu_perf_events(axu1_iu_perf_events), + .iu_xu_rfi(iu_xu_rfi), + .iu_xu_rfgi(iu_xu_rfgi), + .iu_xu_rfci(iu_xu_rfci), + .iu_xu_rfmci(iu_xu_rfmci), + .iu_xu_int(iu_xu_int), + .iu_xu_gint(iu_xu_gint), + .iu_xu_cint(iu_xu_cint), + .iu_xu_mcint(iu_xu_mcint), + .iu_xu_nia(iu_xu_nia), + .iu_xu_esr(iu_xu_esr), + .iu_xu_mcsr(iu_xu_mcsr), + .iu_xu_dbsr(iu_xu_dbsr), + .iu_xu_dear_update(iu_xu_dear_update), + .iu_xu_dear(iu_xu_dear), + .iu_xu_dbsr_update(iu_xu_dbsr_update), + .iu_xu_dbsr_ude(iu_xu_dbsr_ude), + .iu_xu_dbsr_ide(iu_xu_dbsr_ide), + .iu_xu_esr_update(iu_xu_esr_update), + .iu_xu_act(iu_xu_act), + .iu_xu_dbell_taken(iu_xu_dbell_taken), + .iu_xu_cdbell_taken(iu_xu_cdbell_taken), + .iu_xu_gdbell_taken(iu_xu_gdbell_taken), + .iu_xu_gcdbell_taken(iu_xu_gcdbell_taken), + .iu_xu_gmcdbell_taken(iu_xu_gmcdbell_taken), + .iu_xu_instr_cpl(iu_xu_instr_cpl), + .xu_iu_np1_async_flush(xu_iu_np1_async_flush), + .iu_xu_async_complete(iu_xu_async_complete), + .dp_cp_hold_req(dp_cp_hold_req), + .iu_mm_hold_ack(iu_mm_hold_ack), + .dp_cp_bus_snoop_hold_req(dp_cp_bus_snoop_hold_req), + .iu_mm_bus_snoop_hold_ack(iu_mm_bus_snoop_hold_ack), + .iu_spr_eheir_update(iu_spr_eheir_update), + .iu_spr_eheir(iu_spr_eheir), + .xu_iu_msr_de(xu_iu_msr_de), + .xu_iu_msr_pr(xu_iu_msr_pr), + .xu_iu_msr_cm(xu_iu_msr_cm), + .xu_iu_msr_gs(xu_iu_msr_gs), + .xu_iu_msr_me(xu_iu_msr_me), + .xu_iu_dbcr0_edm(xu_iu_dbcr0_edm), + .xu_iu_dbcr0_idm(xu_iu_dbcr0_idm), + .xu_iu_dbcr0_icmp(xu_iu_dbcr0_icmp), + .xu_iu_dbcr0_brt(xu_iu_dbcr0_brt), + .xu_iu_dbcr0_irpt(xu_iu_dbcr0_irpt), + .xu_iu_dbcr0_trap(xu_iu_dbcr0_trap), + .xu_iu_iac1_en(xu_iu_iac1_en), + .xu_iu_iac2_en(xu_iu_iac2_en), + .xu_iu_iac3_en(xu_iu_iac3_en), + .xu_iu_iac4_en(xu_iu_iac4_en), + .xu_iu_dbcr0_dac1(xu_iu_dbcr0_dac1), + .xu_iu_dbcr0_dac2(xu_iu_dbcr0_dac2), + .xu_iu_dbcr0_dac3(xu_iu_dbcr0_dac3), + .xu_iu_dbcr0_dac4(xu_iu_dbcr0_dac4), + .xu_iu_dbcr0_ret(xu_iu_dbcr0_ret), + .xu_iu_dbcr1_iac12m(xu_iu_dbcr1_iac12m), + .xu_iu_dbcr1_iac34m(xu_iu_dbcr1_iac34m), + .lq_iu_spr_dbcr3_ivc(lq_iu_spr_dbcr3_ivc), + .xu_iu_epcr_extgs(xu_iu_epcr_extgs), + .xu_iu_epcr_dtlbgs(xu_iu_epcr_dtlbgs), + .xu_iu_epcr_itlbgs(xu_iu_epcr_itlbgs), + .xu_iu_epcr_dsigs(xu_iu_epcr_dsigs), + .xu_iu_epcr_isigs(xu_iu_epcr_isigs), + .xu_iu_epcr_duvd(xu_iu_epcr_duvd), + .xu_iu_epcr_icm(xu_iu_epcr_icm), + .xu_iu_epcr_gicm(xu_iu_epcr_gicm), + .xu_iu_ccr2_ucode_dis(xu_iu_ccr2_ucode_dis), + .xu_iu_hid_mmu_mode(xu_iu_hid_mmu_mode), + .xu_iu_xucr4_mmu_mchk(xu_iu_xucr4_mmu_mchk), + .an_ac_uncond_dbg_event(an_ac_uncond_dbg_event), + .xu_iu_external_mchk(xu_iu_external_mchk), + .xu_iu_ext_interrupt(xu_iu_ext_interrupt), + .xu_iu_dec_interrupt(xu_iu_dec_interrupt), + .xu_iu_udec_interrupt(xu_iu_udec_interrupt), + .xu_iu_perf_interrupt(xu_iu_perf_interrupt), + .xu_iu_fit_interrupt(xu_iu_fit_interrupt), + .xu_iu_crit_interrupt(xu_iu_crit_interrupt), + .xu_iu_wdog_interrupt(xu_iu_wdog_interrupt), + .xu_iu_gwdog_interrupt(xu_iu_gwdog_interrupt), + .xu_iu_gfit_interrupt(xu_iu_gfit_interrupt), + .xu_iu_gdec_interrupt(xu_iu_gdec_interrupt), + .xu_iu_dbell_interrupt(xu_iu_dbell_interrupt), + .xu_iu_cdbell_interrupt(xu_iu_cdbell_interrupt), + .xu_iu_gdbell_interrupt(xu_iu_gdbell_interrupt), + .xu_iu_gcdbell_interrupt(xu_iu_gcdbell_interrupt), + .xu_iu_gmcdbell_interrupt(xu_iu_gmcdbell_interrupt), + .xu_iu_dbsr_ide(xu_iu_dbsr_ide), + .iu_flush(iu_flush), + .cp_flush_into_uc(cp_flush_into_uc), + .cp_uc_flush_ifar(cp_uc_flush_ifar), + .cp_uc_np1_flush(cp_uc_np1_flush), + .cp_flush(cp_flush), + .cp_next_itag(cp_next_itag), + .cp_flush_itag(cp_flush_itag), + .cp_flush_ifar(cp_flush_ifar), + .cp_iu0_flush_2ucode(cp_iu0_flush_2ucode), + .cp_iu0_flush_2ucode_type(cp_iu0_flush_2ucode_type), + .cp_iu0_flush_nonspec(cp_iu0_flush_nonspec), + .pc_iu_init_reset(pc_iu_init_reset), + .xu_iu_single_instr_mode(xu_iu_single_instr_mode), + .spr_single_issue(spr_single_issue), + .spr_ivpr(spr_ivpr), + .spr_givpr(spr_givpr), + .spr_iac1(spr_iac1), + .spr_iac2(spr_iac2), + .spr_iac3(spr_iac3), + .spr_iac4(spr_iac4), + .pc_iu_ram_active(pc_iu_ram_active), + .pc_iu_ram_flush_thread(pc_iu_ram_flush_thread), + .xu_iu_msrovride_enab(xu_iu_msrovride_enab), + .iu_pc_ram_done(iu_pc_ram_done), + .iu_pc_ram_interrupt(iu_pc_ram_interrupt), + .iu_pc_ram_unsupported(iu_pc_ram_unsupported), + .pc_iu_stop(pc_iu_stop), + .pc_iu_step(pc_iu_step), + .pc_iu_dbg_action(pc_iu_dbg_action), + .iu_pc_step_done(iu_pc_step_done), + .iu_pc_stop_dbg_event(iu_pc_stop_dbg_event), + .iu_pc_err_debug_event(iu_pc_err_debug_event), + .iu_pc_attention_instr(iu_pc_attention_instr), + .iu_pc_err_mchk_disabled(iu_pc_err_mchk_disabled), + .ac_an_debug_trigger(ac_an_debug_trigger), + .iu_xu_stop(iu_xu_stop), + .iu_xu_quiesce(iu_xu_quiesce_int), + .mm_iu_ierat_rel_val(mm_iu_ierat_rel_val), + .mm_iu_ierat_pt_fault(mm_iu_ierat_pt_fault), + .mm_iu_ierat_lrat_miss(mm_iu_ierat_lrat_miss), + .mm_iu_ierat_tlb_inelig(mm_iu_ierat_tlb_inelig), + .mm_iu_tlb_multihit_err(mm_iu_tlb_multihit_err), + .mm_iu_tlb_par_err(mm_iu_tlb_par_err), + .mm_iu_lru_par_err(mm_iu_lru_par_err), + .mm_iu_tlb_miss(mm_iu_tlb_miss), + .mm_iu_reload_hit(mm_iu_reload_hit), + .ic_cp_nonspec_hit(ic_cp_nonspec_hit), + .cp_mm_except_taken(cp_mm_except_taken), + // completion empty + .cp_rn_empty(cp_rn_empty), + .cp_async_block(cp_async_block), + + .vdd(vdd), + .gnd(gnd) + ); + + assign re0 = 1'b1; + assign ra0 = cp0_i0_completed_itag; + + assign re1 = 1'b1; + assign ra1 = cp0_i1_completed_itag; + + assign we0 = rn_cp_iu6_i0_vld; + assign wa0 = rn_cp_iu6_i0_itag[1:`ITAG_SIZE_ENC - 1]; + assign di0 = {rn_cp_iu6_i0_ifar, br_val_i0, bcctr_i0, bclr_i0, bta_i0, rfi_i0, rfgi_i0, rfci_i0, rfmci_i0, ivax_i0, (sc_i0 | sc_hyp_i0), mtiar_i0, rollover_i0, is_csync_i0, is_isync_i0, rn_cp_iu6_i0_bh_update, rn_cp_iu6_i0_bh0_hist, rn_cp_iu6_i0_bh1_hist, rn_cp_iu6_i0_bh2_hist, rn_cp_iu6_i0_gshare, rn_cp_iu6_i0_ls_ptr, rn_cp_iu6_i0_isram, cp_i0_lk, cp_i0_bh, cp_i0_getnia, cp_i0_ld, cp_i0_st, cp_i0_epid, rn_cp_iu6_i0_ucode, rn_cp_iu6_i0_type_fp, rn_cp_iu6_i0_type_ap, rn_cp_iu6_i0_type_spv, rn_cp_iu6_i0_type_st, attn_i0, rn_cp_iu6_i0_fuse_nop, icmp_block_i0, nonspec_i0, rn_cp_iu6_i0_t1_v, rn_cp_iu6_i0_t1_t, rn_cp_iu6_i0_t1_p, rn_cp_iu6_i0_t1_a, rn_cp_iu6_i0_t2_v, rn_cp_iu6_i0_t2_t, rn_cp_iu6_i0_t2_p, rn_cp_iu6_i0_t2_a, rn_cp_iu6_i0_t3_v, rn_cp_iu6_i0_t3_t, rn_cp_iu6_i0_t3_p, rn_cp_iu6_i0_t3_a, rn_cp_iu6_i0_btb_entry, rn_cp_iu6_i0_btb_hist}; + + + assign we1 = rn_cp_iu6_i1_vld; + assign wa1 = rn_cp_iu6_i1_itag[1:`ITAG_SIZE_ENC - 1]; + assign di1 = {rn_cp_iu6_i1_ifar, br_val_i1, bcctr_i1, bclr_i1, bta_i1, rfi_i1, rfgi_i1, rfci_i1, rfmci_i1, ivax_i1, (sc_i1 | sc_hyp_i1), mtiar_i1, rollover_i1, is_csync_i1, is_isync_i1, rn_cp_iu6_i1_bh_update, rn_cp_iu6_i1_bh0_hist, rn_cp_iu6_i1_bh1_hist, rn_cp_iu6_i1_bh2_hist, rn_cp_iu6_i1_gshare, rn_cp_iu6_i1_ls_ptr, rn_cp_iu6_i1_isram, cp_i1_lk, cp_i1_bh, cp_i1_getnia, cp_i1_ld, cp_i1_st, cp_i1_epid, rn_cp_iu6_i1_ucode, rn_cp_iu6_i1_type_fp, rn_cp_iu6_i1_type_ap, rn_cp_iu6_i1_type_spv, rn_cp_iu6_i1_type_st, attn_i1, rn_cp_iu6_i1_fuse_nop, icmp_block_i1, nonspec_i1, rn_cp_iu6_i1_t1_v, rn_cp_iu6_i1_t1_t, rn_cp_iu6_i1_t1_p, rn_cp_iu6_i1_t1_a, rn_cp_iu6_i1_t2_v, rn_cp_iu6_i1_t2_t, rn_cp_iu6_i1_t2_p, rn_cp_iu6_i1_t2_a, rn_cp_iu6_i1_t3_v, rn_cp_iu6_i1_t3_t, rn_cp_iu6_i1_t3_p, rn_cp_iu6_i1_t3_a, rn_cp_iu6_i1_btb_entry, rn_cp_iu6_i1_btb_hist}; + + assign cp2_i0_ifar = do0[entry_ifar_offset:entry_ifar_offset + `EFF_IFAR_WIDTH-1]; + assign cp2_i0_bp_val = do0[entry_bp_val_offset]; + assign cp2_i0_bp_bcctr = do0[entry_bp_bcctr_offset]; + assign cp2_i0_bp_bclr = do0[entry_bp_bclr_offset]; + assign cp2_i0_bp_bta = do0[entry_bp_bta_offset:entry_bp_bta_offset + `EFF_IFAR_WIDTH-1]; + assign cp2_i0_rfi = do0[entry_rfi_offset]; + assign cp2_i0_rfgi = do0[entry_rfgi_offset]; + assign cp2_i0_rfci = do0[entry_rfci_offset]; + assign cp2_i0_rfmci = do0[entry_rfmci_offset]; + assign cp2_i0_ivax = do0[entry_ivax_offset]; + assign cp2_i0_sc = do0[entry_sc_offset]; + assign cp2_i0_mtiar = do0[entry_mtiar_offset]; + assign cp2_i0_rollover = do0[entry_rollover_offset]; + assign cp2_i0_is_csync = do0[entry_is_csync_offset]; + assign cp2_i0_is_isync = do0[entry_is_isync_offset]; + assign cp2_i0_bh_update = do0[entry_bh_update_offset]; + assign cp2_i0_bh0_hist = do0[entry_bh0_hist_offset:entry_bh0_hist_offset + 2 - 1]; + assign cp2_i0_bh1_hist = do0[entry_bh1_hist_offset:entry_bh1_hist_offset + 2 - 1]; + assign cp2_i0_bh2_hist = do0[entry_bh2_hist_offset:entry_bh2_hist_offset + 2 - 1]; + assign cp2_i0_gshare = do0[entry_gshare_offset:entry_gshare_offset + 10 - 1]; + assign cp2_i0_ls_ptr = do0[entry_ls_ptr_offset:entry_ls_ptr_offset + 3 - 1]; + assign cp2_i0_isram = do0[entry_isram_offset]; + assign cp2_i0_lk = do0[entry_lk_offset]; + assign cp2_i0_bh = do0[entry_bh_offset:entry_bh_offset + 2 - 1]; + assign cp2_i0_getnia = do0[entry_getnia_offset]; + assign cp2_i0_ld = do0[entry_ld_offset]; + assign cp2_i0_st = do0[entry_st_offset]; + assign cp2_i0_epid = do0[entry_epid_offset]; + assign cp2_i0_ucode = do0[entry_ucode_offset:entry_ucode_offset + 3 - 1]; + assign cp2_i0_type_fp = do0[entry_type_fp_offset]; + assign cp2_i0_type_ap = do0[entry_type_ap_offset]; + assign cp2_i0_type_spv = do0[entry_type_spv_offset]; + assign cp2_i0_type_st = do0[entry_type_st_offset]; + assign cp2_i0_attn = do0[entry_attn_offset]; + assign cp2_i0_fuse_nop = do0[entry_fuse_nop_offset]; + assign cp2_i0_icmp_block = do0[entry_icmp_block_offset]; + assign cp2_i0_nonspec = do0[entry_nonspec_offset]; + assign cp2_i0_t1_v = do0[entry_t1_v_offset]; + assign cp2_i0_t1_t = do0[entry_t1_t_offset:entry_t1_t_offset + `TYPE_WIDTH - 1]; + assign cp2_i0_t1_p = do0[entry_t1_p_offset:entry_t1_p_offset + `GPR_POOL_ENC - 1]; + assign cp2_i0_t1_a = do0[entry_t1_a_offset:entry_t1_a_offset + `GPR_POOL_ENC - 1]; + assign cp2_i0_t2_v = do0[entry_t2_v_offset]; + assign cp2_i0_t2_t = do0[entry_t2_t_offset:entry_t2_t_offset + `TYPE_WIDTH - 1]; + assign cp2_i0_t2_p = do0[entry_t2_p_offset:entry_t2_p_offset + `GPR_POOL_ENC - 1]; + assign cp2_i0_t2_a = do0[entry_t2_a_offset:entry_t2_a_offset + `GPR_POOL_ENC - 1]; + assign cp2_i0_t3_v = do0[entry_t3_v_offset]; + assign cp2_i0_t3_t = do0[entry_t3_t_offset:entry_t3_t_offset + `TYPE_WIDTH - 1]; + assign cp2_i0_t3_p = do0[entry_t3_p_offset:entry_t3_p_offset + `GPR_POOL_ENC - 1]; + assign cp2_i0_t3_a = do0[entry_t3_a_offset:entry_t3_a_offset + `GPR_POOL_ENC - 1]; + assign cp2_i0_btb_entry = do0[entry_btb_entry_offset]; + assign cp2_i0_btb_hist = do0[entry_btb_hist_offset:entry_btb_hist_offset + 2 - 1]; + + assign cp2_i1_ifar = do1[entry_ifar_offset:entry_ifar_offset + `EFF_IFAR_WIDTH - 1]; + assign cp2_i1_bp_val = do1[entry_bp_val_offset]; + assign cp2_i1_bp_bcctr = do1[entry_bp_bcctr_offset]; + assign cp2_i1_bp_bclr = do1[entry_bp_bclr_offset]; + assign cp2_i1_bp_bta = do1[entry_bp_bta_offset:entry_bp_bta_offset + `EFF_IFAR_WIDTH - 1]; + assign cp2_i1_rfi = do1[entry_rfi_offset]; + assign cp2_i1_rfgi = do1[entry_rfgi_offset]; + assign cp2_i1_rfci = do1[entry_rfci_offset]; + assign cp2_i1_rfmci = do1[entry_rfmci_offset]; + assign cp2_i1_ivax = do1[entry_ivax_offset]; + assign cp2_i1_sc = do1[entry_sc_offset]; + assign cp2_i1_mtiar = do1[entry_mtiar_offset]; + assign cp2_i1_rollover = do1[entry_rollover_offset]; + assign cp2_i1_is_csync = do1[entry_is_csync_offset]; + assign cp2_i1_is_isync = do1[entry_is_isync_offset]; + assign cp2_i1_bh_update = do1[entry_bh_update_offset]; + assign cp2_i1_bh0_hist = do1[entry_bh0_hist_offset:entry_bh0_hist_offset + 2 - 1]; + assign cp2_i1_bh1_hist = do1[entry_bh1_hist_offset:entry_bh1_hist_offset + 2 - 1]; + assign cp2_i1_bh2_hist = do1[entry_bh2_hist_offset:entry_bh2_hist_offset + 2 - 1]; + assign cp2_i1_gshare = do1[entry_gshare_offset:entry_gshare_offset + 10 - 1]; + assign cp2_i1_ls_ptr = do1[entry_ls_ptr_offset:entry_ls_ptr_offset + 3 - 1]; + assign cp2_i1_isram = do1[entry_isram_offset]; + assign cp2_i1_lk = do1[entry_lk_offset]; + assign cp2_i1_bh = do1[entry_bh_offset:entry_bh_offset + 2 - 1]; + assign cp2_i1_getnia = do1[entry_getnia_offset]; + assign cp2_i1_ld = do1[entry_ld_offset]; + assign cp2_i1_st = do1[entry_st_offset]; + assign cp2_i1_epid = do1[entry_epid_offset]; + assign cp2_i1_ucode = do1[entry_ucode_offset:entry_ucode_offset + 3 - 1]; + assign cp2_i1_type_fp = do1[entry_type_fp_offset]; + assign cp2_i1_type_ap = do1[entry_type_ap_offset]; + assign cp2_i1_type_spv = do1[entry_type_spv_offset]; + assign cp2_i1_type_st = do1[entry_type_st_offset]; + assign cp2_i1_attn = do1[entry_attn_offset]; + assign cp2_i1_fuse_nop = do1[entry_fuse_nop_offset]; + assign cp2_i1_icmp_block = do1[entry_icmp_block_offset]; + assign cp2_i1_nonspec = do1[entry_nonspec_offset]; + assign cp2_i1_t1_v = do1[entry_t1_v_offset]; + assign cp2_i1_t1_t = do1[entry_t1_t_offset:entry_t1_t_offset + `TYPE_WIDTH - 1]; + assign cp2_i1_t1_p = do1[entry_t1_p_offset:entry_t1_p_offset + `GPR_POOL_ENC - 1]; + assign cp2_i1_t1_a = do1[entry_t1_a_offset:entry_t1_a_offset + `GPR_POOL_ENC - 1]; + assign cp2_i1_t2_v = do1[entry_t2_v_offset]; + assign cp2_i1_t2_t = do1[entry_t2_t_offset:entry_t2_t_offset + `TYPE_WIDTH - 1]; + assign cp2_i1_t2_p = do1[entry_t2_p_offset:entry_t2_p_offset + `GPR_POOL_ENC - 1]; + assign cp2_i1_t2_a = do1[entry_t2_a_offset:entry_t2_a_offset + `GPR_POOL_ENC - 1]; + assign cp2_i1_t3_v = do1[entry_t3_v_offset]; + assign cp2_i1_t3_t = do1[entry_t3_t_offset:entry_t3_t_offset + `TYPE_WIDTH - 1]; + assign cp2_i1_t3_p = do1[entry_t3_p_offset:entry_t3_p_offset + `GPR_POOL_ENC - 1]; + assign cp2_i1_t3_a = do1[entry_t3_a_offset:entry_t3_a_offset + `GPR_POOL_ENC - 1]; + assign cp2_i1_btb_entry = do1[entry_btb_entry_offset]; + assign cp2_i1_btb_hist = do1[entry_btb_hist_offset:entry_btb_hist_offset + 2 - 1]; + + assign cp_rn_i0_v = cp2_i0_completed; + assign cp_rn_i0_axu_exception_val = cp2_i0_axu_exception_val; + assign cp_rn_i0_axu_exception = cp2_i0_axu_exception; + assign cp_rn_i0_t1_v = cp2_i0_t1_v & cp2_i0_completed; + assign cp_rn_i0_t1_t = cp2_i0_t1_t; + assign cp_rn_i0_t1_p = cp2_i0_t1_p; + assign cp_rn_i0_t1_a = cp2_i0_t1_a; + + assign cp_rn_i0_t2_v = cp2_i0_t2_v & cp2_i0_completed; + assign cp_rn_i0_t2_t = cp2_i0_t2_t; + assign cp_rn_i0_t2_p = cp2_i0_t2_p; + assign cp_rn_i0_t2_a = cp2_i0_t2_a; + + assign cp_rn_i0_t3_v = cp2_i0_t3_v & cp2_i0_completed; + assign cp_rn_i0_t3_t = cp2_i0_t3_t; + assign cp_rn_i0_t3_p = cp2_i0_t3_p; + assign cp_rn_i0_t3_a = cp2_i0_t3_a; + + assign cp_rn_i1_v = cp2_i1_completed; + assign cp_rn_i1_axu_exception_val = cp2_i1_axu_exception_val; + assign cp_rn_i1_axu_exception = cp2_i1_axu_exception; + assign cp_rn_i1_t1_v = cp2_i1_t1_v & cp2_i1_completed; + assign cp_rn_i1_t1_t = cp2_i1_t1_t; + assign cp_rn_i1_t1_p = cp2_i1_t1_p; + assign cp_rn_i1_t1_a = cp2_i1_t1_a; + + assign cp_rn_i1_t2_v = cp2_i1_t2_v & cp2_i1_completed; + assign cp_rn_i1_t2_t = cp2_i1_t2_t; + assign cp_rn_i1_t2_p = cp2_i1_t2_p; + assign cp_rn_i1_t2_a = cp2_i1_t2_a; + + assign cp_rn_i1_t3_v = cp2_i1_t3_v & cp2_i1_completed; + assign cp_rn_i1_t3_t = cp2_i1_t3_t; + assign cp_rn_i1_t3_p = cp2_i1_t3_p; + assign cp_rn_i1_t3_a = cp2_i1_t3_a; + + assign cp_rn_uc_credit_free = (cp2_i0_completed & (cp2_i0_ucode == 3'b101)) | + (cp2_i1_completed & (cp2_i1_ucode == 3'b101)); + assign cp_bp_val = (cp2_i0_bp_val & cp2_i0_completed) | + (cp2_i1_bp_val & cp2_i1_completed); + assign cp_bp_bcctr = (cp2_i0_bp_val & cp2_i0_bp_bcctr & cp2_i0_completed) | + (cp2_i1_bp_val & cp2_i1_bp_bcctr & cp2_i1_completed); + assign cp_bp_bclr = (cp2_i0_bp_val & cp2_i0_bp_bclr & cp2_i0_completed) | + (cp2_i1_bp_val & cp2_i1_bp_bclr & cp2_i1_completed); + assign cp_bp_br_pred = (cp2_i0_bp_val & cp2_i0_bp_pred & cp2_i0_completed) | + (cp2_i1_bp_val & cp2_i1_bp_pred & cp2_i1_completed); + assign cp_bp_br_taken = (cp2_i0_bp_val & cp2_i0_br_pred & cp2_i0_completed) | + (cp2_i1_bp_val & cp2_i1_br_pred & cp2_i1_completed); + assign cp_bp_ifar = ({`EFF_IFAR_WIDTH{cp2_i0_bp_val & cp2_i0_completed}} & cp2_i0_ifar) | + ({`EFF_IFAR_WIDTH{cp2_i1_bp_val & cp2_i1_completed}} & cp2_i1_ifar); + assign cp_bp_bh0_hist = ({2{cp2_i0_bp_val & cp2_i0_completed}} & cp2_i0_bh0_hist) | + ({2{cp2_i1_bp_val & cp2_i1_completed}} & cp2_i1_bh0_hist); + assign cp_bp_bh1_hist = ({2{cp2_i0_bp_val & cp2_i0_completed}} & cp2_i0_bh1_hist) | + ({2{cp2_i1_bp_val & cp2_i1_completed}} & cp2_i1_bh1_hist); + assign cp_bp_bh2_hist = ({2{cp2_i0_bp_val & cp2_i0_completed}} & cp2_i0_bh2_hist) | + ({2{cp2_i1_bp_val & cp2_i1_completed}} & cp2_i1_bh2_hist); + assign cp_bp_bh_update = (cp2_i0_bp_val & cp2_i0_bh_update & cp2_i0_completed) | + (cp2_i1_bp_val & cp2_i1_bh_update & cp2_i1_completed); + assign cp_bp_lk = (cp2_i0_bp_val & cp2_i0_lk & cp2_i0_completed) | + (cp2_i1_bp_val & cp2_i1_lk & cp2_i1_completed); + assign cp_bp_bh = ({2{cp2_i0_bp_val & cp2_i0_completed}} & cp2_i0_bh) | + ({2{cp2_i1_bp_val & cp2_i1_completed}} & cp2_i1_bh); + assign cp_bp_gshare = ({10{cp2_i0_bp_val & cp2_i0_completed}} & cp2_i0_gshare) | + ({10{cp2_i1_bp_val & cp2_i1_completed}} & cp2_i1_gshare); + assign cp_bp_ls_ptr = ({3{cp2_i0_bp_val & cp2_i0_completed}} & cp2_i0_ls_ptr) | + ({3{cp2_i1_bp_val & cp2_i1_completed}} & cp2_i1_ls_ptr); + assign cp_bp_ctr = ({`EFF_IFAR_WIDTH{cp2_i0_bp_val & cp2_i0_completed}} & cp2_i0_bta) | + ({`EFF_IFAR_WIDTH{cp2_i1_bp_val & cp2_i1_completed}} & cp2_i1_bta); + assign cp_bp_btb_entry = (cp2_i0_bp_val & cp2_i0_btb_entry & cp2_i0_completed) | + (cp2_i1_bp_val & cp2_i1_btb_entry & cp2_i1_completed); + assign cp_bp_btb_hist = ({2{cp2_i0_bp_val & cp2_i0_completed}} & cp2_i0_btb_hist) | + ({2{cp2_i1_bp_val & cp2_i1_completed}} & cp2_i1_btb_hist); + assign cp_is_csync = (cp2_i0_completed & cp2_i0_is_csync) | + (cp2_i1_completed & cp2_i1_is_csync); + assign cp_is_isync = (cp2_i0_completed & cp2_i0_is_isync) | + (cp2_i1_completed & cp2_i1_is_isync); + assign cp_bp_getnia = (cp2_i0_bp_val & cp2_i0_getnia & cp2_i0_completed) | + (cp2_i1_bp_val & cp2_i1_getnia & cp2_i1_completed); + assign cp_dis_ivax = (cp2_i0_completed & cp2_i0_ivax) | + (cp2_i1_completed & cp2_i0_ivax); + + //end of fetch group completion + assign cp_bp_group = (cp2_i0_completed & cp2_i0_ifar[60:61]==2'b11) | + (cp2_i1_completed & cp2_i1_ifar[60:61]==2'b11); + + // number of addressable register in this array + // width of the bus to address all ports (2^addressbus_width >= addressable_ports) + tri_iuq_cpl_arr #(.ADDRESSABLE_PORTS(64), .ADDRESSBUS_WIDTH(6), .PORT_BITWIDTH(entry_length), .LATCHED_READ(1'b1), .LATCHED_READ_DATA(1'b1), .LATCHED_WRITE(1'b1)) + iuq_cpl_arr( // bitwidth of ports + .gnd(gnd), + .vdd(vdd), + .nclk(nclk), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .force_t(force_t), + .thold_0_b(thold_0_b), + .sg_0(sg_0), + .scan_in(scan_con_a), + .scan_out(scan_out), + .re0(re0), + .ra0(ra0), + .do0(do0), + .re1(re1), + .ra1(ra1), + .do1(do1), + .we0(we0), + .wa0(wa0), + .di0(di0), + .we1(we1), + .wa1(wa1), + .di1(di1), + .perr(cpl_perr) + ); + + // Latch Instances + + tri_rlmreg_p #(.WIDTH(`XER_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) xer_cp_p_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[xer_cp_p_offset:xer_cp_p_offset + `XER_POOL_ENC - 1]), + .scout(sov[xer_cp_p_offset:xer_cp_p_offset + `XER_POOL_ENC - 1]), + .din(xer_cp_p_d), + .dout(xer_cp_p_q) + ); + + //----------------------------------------------- + // Pervasive + //----------------------------------------------- + + tri_plat #(.WIDTH(3)) perv_2to1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + .din({func_sl_thold_2, func_slp_sl_thold_2, sg_2}), + .q({func_sl_thold_1, func_slp_sl_thold_1, sg_1}) + ); + + tri_plat #(.WIDTH(3)) perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + .din({func_sl_thold_1, func_slp_sl_thold_1, sg_1}), + .q({func_sl_thold_0, func_slp_sl_thold_0, sg_0}) + ); + + tri_lcbor perv_lcbor_func_sl( + .clkoff_b(clkoff_dc_b), + .thold(func_sl_thold_0), + .sg(sg_0), + .act_dis(tidn), + .force_t(func_sl_force), + .thold_b(func_sl_thold_0_b) + ); + + tri_lcbor perv_lcbor_func_slp_sl( + .clkoff_b(clkoff_dc_b), + .thold(func_slp_sl_thold_0), + .sg(sg_0), + .act_dis(tidn), + .force_t(func_slp_sl_force), + .thold_b(func_slp_sl_thold_0_b) + ); + +endmodule diff --git a/dev/verilog/work/iuq_cpl_ctrl.v b/dev/verilog/work/iuq_cpl_ctrl.v new file mode 100755 index 0000000..a36266a --- /dev/null +++ b/dev/verilog/work/iuq_cpl_ctrl.v @@ -0,0 +1,10077 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: Completion Unit +// +//***************************************************************************** + +`include "tri_a2o.vh" + +module iuq_cpl_ctrl( + // Clocks + input [0:`NCLK_WIDTH-1] nclk, + + // Pervasive + input d_mode_dc, + input delay_lclkr_dc, + input mpw1_dc_b, + input mpw2_dc_b, + input func_sl_force, + input func_sl_thold_0_b, + input func_slp_sl_force, + input func_slp_sl_thold_0_b, + input sg_0, + input scan_in, + output scan_out, + + // Perfomance selectors + input pc_iu_event_bus_enable, + input [0:2] pc_iu_event_count_mode, + input [0:15] spr_cp_perf_event_mux_ctrls, + input [0:3] event_bus_in, + output [0:3] event_bus_out, + + // Instruction Dispatch + input rn_cp_iu6_i0_vld, + input [1:`ITAG_SIZE_ENC-1] rn_cp_iu6_i0_itag, + input [62-`EFF_IFAR_WIDTH:61] rn_cp_iu6_i0_ifar, + input [0:31] rn_cp_iu6_i0_instr, + input [0:2] rn_cp_iu6_i0_ucode, + input rn_cp_iu6_i0_fuse_nop, + input [0:2] rn_cp_iu6_i0_error, + input rn_cp_iu6_i0_valop, + input rn_cp_iu6_i0_is_rfi, + input rn_cp_iu6_i0_is_rfgi, + input rn_cp_iu6_i0_is_rfci, + input rn_cp_iu6_i0_is_rfmci, + input rn_cp_iu6_i0_is_isync, + input rn_cp_iu6_i0_is_sc, + input rn_cp_iu6_i0_is_np1_flush, + input rn_cp_iu6_i0_is_sc_hyp, + input rn_cp_iu6_i0_is_sc_ill, + input rn_cp_iu6_i0_is_dcr_ill, + input rn_cp_iu6_i0_is_attn, + input rn_cp_iu6_i0_is_ehpriv, + input rn_cp_iu6_i0_is_folded, + input rn_cp_iu6_i0_async_block, + input rn_cp_iu6_i0_is_br, + input rn_cp_iu6_i0_br_add_chk, + input rn_cp_iu6_i0_pred, + input rn_cp_iu6_i0_rollover, + input rn_cp_iu6_i0_isram, + input rn_cp_iu6_i0_match, + input rn_cp_iu6_i1_vld, + input [1:`ITAG_SIZE_ENC-1] rn_cp_iu6_i1_itag, + input [62-`EFF_IFAR_WIDTH:61] rn_cp_iu6_i1_ifar, + input [0:31] rn_cp_iu6_i1_instr, + input [0:2] rn_cp_iu6_i1_ucode, + input rn_cp_iu6_i1_fuse_nop, + input [0:2] rn_cp_iu6_i1_error, + input rn_cp_iu6_i1_valop, + input rn_cp_iu6_i1_is_rfi, + input rn_cp_iu6_i1_is_rfgi, + input rn_cp_iu6_i1_is_rfci, + input rn_cp_iu6_i1_is_rfmci, + input rn_cp_iu6_i1_is_isync, + input rn_cp_iu6_i1_is_sc, + input rn_cp_iu6_i1_is_np1_flush, + input rn_cp_iu6_i1_is_sc_hyp, + input rn_cp_iu6_i1_is_sc_ill, + input rn_cp_iu6_i1_is_dcr_ill, + input rn_cp_iu6_i1_is_attn, + input rn_cp_iu6_i1_is_ehpriv, + input rn_cp_iu6_i1_is_folded, + input rn_cp_iu6_i1_async_block, + input rn_cp_iu6_i1_is_br, + input rn_cp_iu6_i1_br_add_chk, + input rn_cp_iu6_i1_pred, + input rn_cp_iu6_i1_rollover, + input rn_cp_iu6_i1_isram, + input rn_cp_iu6_i1_match, + + // Instruction Completed + output cp2_i0_completed, + output cp2_i1_completed, + output [1:`ITAG_SIZE_ENC-1] cp0_i0_completed_itag, + output [1:`ITAG_SIZE_ENC-1] cp0_i1_completed_itag, + input [62-`EFF_IFAR_WIDTH:61] cp2_i0_ifar, + input [62-`EFF_IFAR_WIDTH:61] cp2_i1_ifar, + input [62-`EFF_IFAR_WIDTH:61] cp2_i0_bp_bta, + input [62-`EFF_IFAR_WIDTH:61] cp2_i1_bp_bta, + input cp2_i0_rfi, + input cp2_i0_rfgi, + input cp2_i0_rfci, + input cp2_i0_rfmci, + input cp2_i0_sc, + input cp2_i0_mtiar, + input cp2_i0_rollover, + input cp2_i1_rfi, + input cp2_i1_rfgi, + input cp2_i1_rfci, + input cp2_i1_rfmci, + input cp2_i1_sc, + input cp2_i1_mtiar, + input cp2_i1_rollover, + output cp2_i0_bp_pred, + output cp2_i1_bp_pred, + output cp2_i0_br_pred, + output cp2_i1_br_pred, + output [62-`EFF_IFAR_WIDTH:61] cp2_i0_bta, + output [62-`EFF_IFAR_WIDTH:61] cp2_i1_bta, + input cp2_i0_isram, + input cp2_i1_isram, + input cp2_i0_ld, + input cp2_i1_ld, + input cp2_i0_st, + input cp2_i1_st, + input cp2_i0_epid, + input cp2_i1_epid, + input [0:2] cp2_i0_ucode, + input [0:2] cp2_i1_ucode, + input cp2_i0_type_fp, + input cp2_i1_type_fp, + input cp2_i0_type_ap, + input cp2_i1_type_ap, + input cp2_i0_type_spv, + input cp2_i1_type_spv, + input cp2_i0_type_st, + input cp2_i1_type_st, + input cp2_i0_attn, + input cp2_i1_attn, + input cp2_i0_fuse_nop, + input cp2_i1_fuse_nop, + input cp2_i0_icmp_block, + input cp2_i1_icmp_block, + output cp2_i0_axu_exception_val, + output [0:3] cp2_i0_axu_exception, + output cp2_i1_axu_exception_val, + output [0:3] cp2_i1_axu_exception, + input cp2_i0_nonspec, + input cp2_i1_nonspec, + + // LQ Instruction Executed + input lq0_iu_execute_vld, + input [0:`ITAG_SIZE_ENC-1] lq0_iu_itag, + input lq0_iu_n_flush, + input lq0_iu_np1_flush, + input lq0_iu_dacr_type, + input [0:3] lq0_iu_dacrw, + input [0:31] lq0_iu_instr, + input [64-`GPR_WIDTH:63] lq0_iu_eff_addr, + input lq0_iu_exception_val, + input [0:5] lq0_iu_exception, + input lq0_iu_flush2ucode, + input lq0_iu_flush2ucode_type, + input lq0_iu_recirc_val, + input lq0_iu_dear_val, + + input lq1_iu_execute_vld, + input [0:`ITAG_SIZE_ENC-1] lq1_iu_itag, + input lq1_iu_n_flush, + input lq1_iu_np1_flush, + input lq1_iu_exception_val, + input [0:5] lq1_iu_exception, + input lq1_iu_dacr_type, + input [0:3] lq1_iu_dacrw, + input [0:3] lq1_iu_perf_events, + + output iu_lq_i0_completed, + output [0:`ITAG_SIZE_ENC-1] iu_lq_i0_completed_itag, + output iu_lq_i1_completed, + output [0:`ITAG_SIZE_ENC-1] iu_lq_i1_completed_itag, + + output iu_lq_recirc_val, + + // BR Instruction Executed + input br_iu_execute_vld, + input [0:`ITAG_SIZE_ENC-1] br_iu_itag, + input br_iu_redirect, + input [62-`EFF_IFAR_ARCH:61] br_iu_bta, + input br_iu_taken, + input [0:3] br_iu_perf_events, + + // XU0 Instruction Executed + input xu_iu_execute_vld, + input [0:`ITAG_SIZE_ENC-1] xu_iu_itag, + input xu_iu_n_flush, + input xu_iu_np1_flush, + input xu_iu_flush2ucode, + input xu_iu_exception_val, + input [0:4] xu_iu_exception, + input xu_iu_mtiar, + input [62-`EFF_IFAR_ARCH:61] xu_iu_bta, + input [62-`EFF_IFAR_ARCH:61] xu_iu_rest_ifar, + input [0:3] xu_iu_perf_events, + + // XU1 Instruction Executed + input xu1_iu_execute_vld, + input [0:`ITAG_SIZE_ENC-1] xu1_iu_itag, + + // AXU0 Instruction Executed + input axu0_iu_execute_vld, + input [0:`ITAG_SIZE_ENC-1] axu0_iu_itag, + input axu0_iu_n_flush, + input axu0_iu_np1_flush, + input axu0_iu_n_np1_flush, + input axu0_iu_flush2ucode, + input axu0_iu_flush2ucode_type, + input axu0_iu_exception_val, + input [0:3] axu0_iu_exception, + input [0:3] axu0_iu_perf_events, + + // AXU0 Instruction Executed + input axu1_iu_execute_vld, + input [0:`ITAG_SIZE_ENC-1] axu1_iu_itag, + input axu1_iu_n_flush, + input axu1_iu_np1_flush, + input axu1_iu_n_np1_flush, + input axu1_iu_flush2ucode, + input axu1_iu_flush2ucode_type, + input axu1_iu_exception_val, + input [0:3] axu1_iu_exception, + input [0:3] axu1_iu_perf_events, + + // Signals to SPR partition + output iu_xu_rfi, + output iu_xu_rfgi, + output iu_xu_rfci, + output iu_xu_rfmci, + output iu_xu_int, + output iu_xu_gint, + output iu_xu_cint, + output iu_xu_mcint, + output [62-`EFF_IFAR_ARCH:61] iu_xu_nia, + output [0:16] iu_xu_esr, + output [0:14] iu_xu_mcsr, + output [0:18] iu_xu_dbsr, + output iu_xu_dear_update, + output [64-`GPR_WIDTH:63] iu_xu_dear, + output iu_xu_dbsr_update, + output iu_xu_dbsr_ude, + output iu_xu_dbsr_ide, + output iu_xu_esr_update, + output iu_xu_act, + output iu_xu_dbell_taken, + output iu_xu_cdbell_taken, + output iu_xu_gdbell_taken, + output iu_xu_gcdbell_taken, + output iu_xu_gmcdbell_taken, + output iu_xu_instr_cpl, + input xu_iu_np1_async_flush, + output iu_xu_async_complete, + input dp_cp_hold_req, + output iu_mm_hold_ack, + input dp_cp_bus_snoop_hold_req, + output iu_mm_bus_snoop_hold_ack, + output iu_spr_eheir_update, + output [0:31] iu_spr_eheir, + input xu_iu_msr_de, + input xu_iu_msr_pr, + input xu_iu_msr_cm, + input xu_iu_msr_gs, + input xu_iu_msr_me, + input xu_iu_dbcr0_edm, + input xu_iu_dbcr0_idm, + input xu_iu_dbcr0_icmp, + input xu_iu_dbcr0_brt, + input xu_iu_dbcr0_irpt, + input xu_iu_dbcr0_trap, + input xu_iu_iac1_en, + input xu_iu_iac2_en, + input xu_iu_iac3_en, + input xu_iu_iac4_en, + input [0:1] xu_iu_dbcr0_dac1, + input [0:1] xu_iu_dbcr0_dac2, + input [0:1] xu_iu_dbcr0_dac3, + input [0:1] xu_iu_dbcr0_dac4, + input xu_iu_dbcr0_ret, + input xu_iu_dbcr1_iac12m, + input xu_iu_dbcr1_iac34m, + input lq_iu_spr_dbcr3_ivc, + input xu_iu_epcr_extgs, + input xu_iu_epcr_dtlbgs, + input xu_iu_epcr_itlbgs, + input xu_iu_epcr_dsigs, + input xu_iu_epcr_isigs, + input xu_iu_epcr_duvd, + input xu_iu_epcr_icm, + input xu_iu_epcr_gicm, + input xu_iu_ccr2_ucode_dis, + input xu_iu_hid_mmu_mode, + input xu_iu_xucr4_mmu_mchk, + + // Interrupts + input an_ac_uncond_dbg_event, + input xu_iu_external_mchk, + input xu_iu_ext_interrupt, + input xu_iu_dec_interrupt, + input xu_iu_udec_interrupt, + input xu_iu_perf_interrupt, + input xu_iu_fit_interrupt, + input xu_iu_crit_interrupt, + input xu_iu_wdog_interrupt, + input xu_iu_gwdog_interrupt, + input xu_iu_gfit_interrupt, + input xu_iu_gdec_interrupt, + input xu_iu_dbell_interrupt, + input xu_iu_cdbell_interrupt, + input xu_iu_gdbell_interrupt, + input xu_iu_gcdbell_interrupt, + input xu_iu_gmcdbell_interrupt, + input xu_iu_dbsr_ide, + input axu0_iu_async_fex, + + // Flushes + output iu_flush, + output cp_flush_into_uc, + output [43:61] cp_uc_flush_ifar, + output cp_uc_np1_flush, + output cp_flush, + output [0:`ITAG_SIZE_ENC-1] cp_next_itag, + output [0:`ITAG_SIZE_ENC-1] cp_flush_itag, + output [62-`EFF_IFAR_ARCH:61] cp_flush_ifar, + output cp_iu0_flush_2ucode, + output cp_iu0_flush_2ucode_type, + output cp_iu0_flush_nonspec, + input pc_iu_init_reset, + + // SPRs + input xu_iu_single_instr_mode, + input spr_single_issue, + input [64-`GPR_WIDTH:51] spr_ivpr, + input [64-`GPR_WIDTH:51] spr_givpr, + input [62-`EFF_IFAR_ARCH:61] spr_iac1, + input [62-`EFF_IFAR_ARCH:61] spr_iac2, + input [62-`EFF_IFAR_ARCH:61] spr_iac3, + input [62-`EFF_IFAR_ARCH:61] spr_iac4, + + // Signals from pervasive + input pc_iu_ram_active, + input pc_iu_ram_flush_thread, + input xu_iu_msrovride_enab, + output iu_pc_ram_done, + output iu_pc_ram_interrupt, + output iu_pc_ram_unsupported, + input pc_iu_stop, + input pc_iu_step, + input [0:2] pc_iu_dbg_action, + output iu_pc_step_done, + output [0:`THREADS-1] iu_pc_stop_dbg_event, + output iu_pc_err_debug_event, + output iu_pc_attention_instr, + output iu_pc_err_mchk_disabled, + output ac_an_debug_trigger, + output iu_xu_stop, + output iu_xu_quiesce, + + // MMU Errors + input mm_iu_ierat_rel_val, + input mm_iu_ierat_pt_fault, + input mm_iu_ierat_lrat_miss, + input mm_iu_ierat_tlb_inelig, + input mm_iu_tlb_multihit_err, + input mm_iu_tlb_par_err, + input mm_iu_lru_par_err, + input mm_iu_tlb_miss, + input mm_iu_reload_hit, + input ic_cp_nonspec_hit, + + output [0:5] cp_mm_except_taken, + + // completion empty + output cp_rn_empty, + output cp_async_block, + + // Power + inout vdd, + inout gnd); + + // Latches + wire [1:`ITAG_SIZE_ENC-1] iu6_i0_itag_q; + wire [1:`ITAG_SIZE_ENC-1] iu6_i1_itag_q; + wire [0:`ITAG_SIZE_ENC-1] cp1_i0_itag_q; + wire [0:`ITAG_SIZE_ENC-1] cp0_i0_itag; + wire [0:`CPL_Q_DEPTH-1] cp1_i0_ptr_q; + wire [0:`CPL_Q_DEPTH-1] cp0_i0_ptr; + wire [0:`ITAG_SIZE_ENC-1] cp1_i1_itag_q; + wire [0:`ITAG_SIZE_ENC-1] cp0_i1_itag; + wire [0:`CPL_Q_DEPTH-1] cp1_i1_ptr_q; + wire [0:`CPL_Q_DEPTH-1] cp0_i1_ptr; + wire [0:`ITAG_SIZE_ENC-1] cp2_i0_itag_q; + wire [0:`ITAG_SIZE_ENC-1] cp2_i1_itag_q; + wire cp2_async_int_val_q; + wire cp1_async_int_val; + wire [0:31] cp2_async_int_q; + wire [0:31] cp1_async_int; + wire cp2_i0_complete_q; + wire cp1_i0_complete; + wire cp2_i1_complete_q; + wire cp1_i1_complete; + wire cp2_i0_np1_flush_q; + wire cp1_i0_np1_flush; + wire cp2_i1_np1_flush_q; + wire cp1_i1_np1_flush; + wire cp2_i0_n_np1_flush_q; + wire cp1_i0_n_np1_flush; + wire cp2_i1_n_np1_flush_q; + wire cp1_i1_n_np1_flush; + wire cp2_i0_bp_pred_q; + wire cp1_i0_bp_pred; + wire cp2_i1_bp_pred_q; + wire cp1_i1_bp_pred; + wire cp2_i0_br_pred_q; + wire cp1_i0_br_pred; + wire cp2_i1_br_pred_q; + wire cp1_i1_br_pred; + wire cp2_i0_br_miss_q; + wire cp1_i0_br_miss; + wire cp2_i1_br_miss_q; + wire cp1_i1_br_miss; + wire cp2_i0_flush2ucode_q; + wire cp1_i0_flush2ucode; + wire cp2_i0_flush2ucode_type_q; + wire cp1_i0_flush2ucode_type; + wire cp2_i1_flush2ucode_q; + wire cp1_i1_flush2ucode; + wire cp2_i1_flush2ucode_type_q; + wire cp1_i1_flush2ucode_type; + wire [62-`EFF_IFAR_ARCH:61] cp2_i_bta_q; + wire [62-`EFF_IFAR_ARCH:61] cp1_i_bta; + wire cp2_i0_iu_excvec_val_q; + wire cp1_i0_iu_excvec_val; + wire [0:3] cp2_i0_iu_excvec_q; + reg [0:3] cp1_i0_iu_excvec; + wire cp2_i1_iu_excvec_val_q; + wire cp1_i1_iu_excvec_val; + wire [0:3] cp2_i1_iu_excvec_q; + reg [0:3] cp1_i1_iu_excvec; + wire cp2_i0_lq_excvec_val_q; + wire cp1_i0_lq_excvec_val; + wire [0:5] cp2_i0_lq_excvec_q; + reg [0:5] cp1_i0_lq_excvec; + wire cp2_i1_lq_excvec_val_q; + wire cp1_i1_lq_excvec_val; + wire [0:5] cp2_i1_lq_excvec_q; + reg [0:5] cp1_i1_lq_excvec; + wire cp2_i0_xu_excvec_val_q; + wire cp1_i0_xu_excvec_val; + wire [0:4] cp2_i0_xu_excvec_q; + reg [0:4] cp1_i0_xu_excvec; + wire cp2_i1_xu_excvec_val_q; + wire cp1_i1_xu_excvec_val; + wire [0:4] cp2_i1_xu_excvec_q; + reg [0:4] cp1_i1_xu_excvec; + wire cp2_i0_axu_excvec_val_q; + wire cp1_i0_axu_excvec_val; + wire [0:3] cp2_i0_axu_excvec_q; + reg [0:3] cp1_i0_axu_excvec; + wire cp2_i1_axu_excvec_val_q; + wire cp1_i1_axu_excvec_val; + wire [0:3] cp2_i1_axu_excvec_q; + reg [0:3] cp1_i1_axu_excvec; + wire cp2_i0_db_val_q; + wire cp1_i0_db_val; + wire [0:18] cp2_i0_db_events_q; + reg [0:18] cp1_i0_db_events; + wire cp2_i1_db_val_q; + wire cp1_i1_db_val; + wire [0:18] cp2_i1_db_events_q; + reg [0:18] cp1_i1_db_events; + wire [0:3] cp2_i0_perf_events_q; + reg [0:3] cp1_i0_perf_events; + wire [0:3] cp2_i1_perf_events_q; + reg [0:3] cp1_i1_perf_events; + wire [0:`CPL_Q_DEPTH-1] cp1_executed_q; + wire [0:`CPL_Q_DEPTH-1] cp0_executed; + wire [0:`CPL_Q_DEPTH-1] cp1_dispatched_q; + wire [0:`CPL_Q_DEPTH-1] cp0_dispatched; + wire [0:`CPL_Q_DEPTH-1] cp1_n_flush_q; + wire [0:`CPL_Q_DEPTH-1] cp0_n_flush; + wire [0:`CPL_Q_DEPTH-1] cp1_np1_flush_q; + wire [0:`CPL_Q_DEPTH-1] cp0_np1_flush; + wire [0:`CPL_Q_DEPTH-1] cp1_n_np1_flush_q; + wire [0:`CPL_Q_DEPTH-1] cp0_n_np1_flush; + wire [0:`CPL_Q_DEPTH-1] cp1_flush2ucode_q; + wire [0:`CPL_Q_DEPTH-1] cp0_flush2ucode; + wire [0:`CPL_Q_DEPTH-1] cp1_flush2ucode_type_q; + wire [0:`CPL_Q_DEPTH-1] cp0_flush2ucode_type; + wire [0:`CPL_Q_DEPTH-1] cp1_recirc_vld_q; + wire [0:`CPL_Q_DEPTH-1] cp0_recirc_vld; + wire [0:3] cp1_perf_events_q[0:`CPL_Q_DEPTH-1]; + wire [0:3] cp0_perf_events[0:`CPL_Q_DEPTH-1]; + wire [0:`CPL_Q_DEPTH-1] cp1_iu_excvec_val_q; + wire [0:`CPL_Q_DEPTH-1] cp0_iu_excvec_val; + wire [0:3] cp1_iu_excvec_q[0:`CPL_Q_DEPTH-1]; + wire [0:3] cp0_iu_excvec[0:`CPL_Q_DEPTH-1]; + wire [0:`CPL_Q_DEPTH-1] cp1_lq_excvec_val_q; + wire [0:`CPL_Q_DEPTH-1] cp0_lq_excvec_val; + wire [0:5] cp1_lq_excvec_q[0:`CPL_Q_DEPTH-1]; + wire [0:5] cp0_lq_excvec[0:`CPL_Q_DEPTH-1]; + wire [0:`CPL_Q_DEPTH-1] cp1_xu_excvec_val_q; + wire [0:`CPL_Q_DEPTH-1] cp0_xu_excvec_val; + wire [0:4] cp1_xu_excvec_q[0:`CPL_Q_DEPTH-1]; + wire [0:4] cp0_xu_excvec[0:`CPL_Q_DEPTH-1]; + wire [0:`CPL_Q_DEPTH-1] cp1_axu_excvec_val_q; + wire [0:`CPL_Q_DEPTH-1] cp0_axu_excvec_val; + wire [0:3] cp1_axu_excvec_q[0:`CPL_Q_DEPTH-1]; + wire [0:3] cp0_axu_excvec[0:`CPL_Q_DEPTH-1]; + wire [0:18] cp1_db_events_q[0:`CPL_Q_DEPTH-1]; + wire [0:18] cp0_db_events[0:`CPL_Q_DEPTH-1]; + wire [0:`CPL_Q_DEPTH-1] cp1_db_IAC_IVC_event; + wire [0:`CPL_Q_DEPTH-1] cp1_async_block_q; + wire [0:`CPL_Q_DEPTH-1] cp0_async_block; + wire [0:`CPL_Q_DEPTH-1] cp1_is_br_q; + wire [0:`CPL_Q_DEPTH-1] cp0_is_br; + wire [0:`CPL_Q_DEPTH-1] cp1_br_add_chk_q; + wire [0:`CPL_Q_DEPTH-1] cp0_br_add_chk; + wire [0:`CPL_Q_DEPTH-1] cp1_bp_pred_q; + wire [0:`CPL_Q_DEPTH-1] cp0_bp_pred; + wire [0:`CPL_Q_DEPTH-1] cp1_br_pred_q; + wire [0:`CPL_Q_DEPTH-1] cp0_br_pred; + wire [0:`CPL_Q_DEPTH-1] cp1_br_miss_q; + wire [0:`CPL_Q_DEPTH-1] cp0_br_miss; + wire cp0_br_bta_act; + wire [62-`EFF_IFAR_ARCH:61] cp1_br_bta_q; + wire [62-`EFF_IFAR_ARCH:61] cp0_br_bta; + reg [62-`EFF_IFAR_ARCH:61] cp0_br_bta_tmp; + wire cp1_br_bta_v_q; + reg cp0_br_bta_v; + wire [0:`ITAG_SIZE_ENC-1] cp1_br_bta_itag_q; + wire [0:`ITAG_SIZE_ENC-1] cp0_br_bta_itag; + reg [0:`ITAG_SIZE_ENC-1] cp0_br_bta_itag_tmp; + wire iu6_i0_dispatched_d; // rn_cp_iu6_i0_vld + wire iu6_i1_dispatched_d; // rn_cp_iu6_i1_vld + wire iu6_i0_dispatched_q; // rn_cp_iu6_i0_vld + wire iu6_i1_dispatched_q; // rn_cp_iu6_i1_vld + wire [62-`EFF_IFAR_WIDTH:61] iu6_i0_ifar_q; // rn_cp_iu6_i0_ifar + wire [0:2] iu6_i0_ucode_q; // rn_cp_iu6_i0_ucode + wire iu6_i0_fuse_nop_q; // rn_cp_iu6_i0_fuse_nop + wire [0:2] iu6_i0_error_q; // rn_cp_iu6_i0_error + wire iu6_i0_valop_q; // rn_cp_iu6_i0_valop + wire iu6_i0_is_rfi_q; // rn_cp_iu6_i0_is_rfi + wire iu6_i0_is_rfgi_q; // rn_cp_iu6_i0_is_rfgi + wire iu6_i0_is_rfci_q; // rn_cp_iu6_i0_is_rfci + wire iu6_i0_is_rfmci_q; // rn_cp_iu6_i0_is_rfmci + wire iu6_i0_is_isync_q; // rn_cp_iu6_i0_is_isync + wire iu6_i0_is_sc_q; // rn_cp_iu6_i0_is_sc + wire iu6_i0_is_np1_flush_q; // rn_cp_iu6_i0_is_np1_flush + wire iu6_i0_is_sc_hyp_q; // rn_cp_iu6_i0_is_sc_hyp + wire iu6_i0_is_sc_ill_q; // rn_cp_iu6_i0_is_sc_ill + wire iu6_i0_is_dcr_ill_q; // rn_cp_iu6_i0_is_dcr_ill + wire iu6_i0_is_attn_q; // rn_cp_iu6_i0_is_attn + wire iu6_i0_is_ehpriv_q; // rn_cp_iu6_i0_is_ehpriv + wire iu6_i0_is_folded_q; // rn_cp_iu6_i0_is_folded + wire iu6_i0_async_block_q; // rn_cp_iu6_i0_async_block + wire iu6_i0_is_br_q; // rn_cp_iu6_i0_is_br + wire iu6_i0_br_add_chk_q; // rn_cp_iu6_i0_br_add_chk + wire iu6_i0_bp_pred_q; // rn_cp_iu6_i0_pred + wire iu6_i0_rollover_q; // rn_cp_iu6_i0_rollover + wire iu6_i0_isram_q; // rn_cp_iu6_i0_isram + wire iu6_i0_match_q; // rn_cp_iu6_i0_match + wire [62-`EFF_IFAR_WIDTH:61] iu6_i1_ifar_q; // rn_cp_iu6_i1_ifar + wire [0:2] iu6_i1_ucode_q; // rn_cp_iu6_i1_ucode + wire iu6_i1_fuse_nop_q; // rn_cp_iu6_i1_fuse_nop + wire [0:2] iu6_i1_error_q; // rn_cp_iu6_i1_error + wire iu6_i1_valop_q; // rn_cp_iu6_i1_valop + wire iu6_i1_is_rfi_q; // rn_cp_iu6_i1_is_rfi + wire iu6_i1_is_rfgi_q; // rn_cp_iu6_i1_is_rfgi + wire iu6_i1_is_rfci_q; // rn_cp_iu6_i1_is_rfci + wire iu6_i1_is_rfmci_q; // rn_cp_iu6_i1_is_rfmci + wire iu6_i1_is_isync_q; // rn_cp_iu6_i1_is_isync + wire iu6_i1_is_sc_q; // rn_cp_iu6_i1_is_sc + wire iu6_i1_is_np1_flush_q; // rn_cp_iu6_i1_is_np1_flush + wire iu6_i1_is_sc_hyp_q; // rn_cp_iu6_i1_is_sc_hyp + wire iu6_i1_is_sc_ill_q; // rn_cp_iu6_i1_is_sc_ill + wire iu6_i1_is_dcr_ill_q; // rn_cp_iu6_i1_is_dcr_ill + wire iu6_i1_is_attn_q; // rn_cp_iu6_i1_is_attn + wire iu6_i1_is_ehpriv_q; // rn_cp_iu6_i1_is_ehpriv + wire iu6_i1_is_folded_q; // rn_cp_iu6_i1_is_folded + wire iu6_i1_async_block_q; // rn_cp_iu6_i1_async_block + wire iu6_i1_is_br_q; // rn_cp_iu6_i1_is_br + wire iu6_i1_br_add_chk_q; // rn_cp_iu6_i1_br_add_chk + wire iu6_i1_bp_pred_q; // rn_cp_iu6_i1_pred + wire iu6_i1_rollover_q; // rn_cp_iu6_i1_rollover + wire iu6_i1_isram_q; // rn_cp_iu6_i1_isram + wire iu6_i1_match_q; // rn_cp_iu6_i1_match + wire iu6_uc_hold_rollover_q; + wire iu6_uc_hold_rollover_d; + wire [0:`CPL_Q_DEPTH-1] cp1_i0_dispatched_delay_q; // Added these to delay checking for completion due to completion array write for I1 + wire [0:`CPL_Q_DEPTH-1] cp1_i0_dispatched_delay_d; + wire [0:`CPL_Q_DEPTH-1] cp1_i1_dispatched_delay_q; // Added these to delay checking for completion due to completion array write for I1 + wire [0:`CPL_Q_DEPTH-1] cp1_i1_dispatched_delay_d; + wire iu7_i0_is_folded_q; // Added these to delay checking for completion due to completion array write for I1 + wire iu7_i0_is_folded_d; + wire iu7_i1_is_folded_q; // Added these to delay checking for completion due to completion array write for I1 + wire iu7_i1_is_folded_d; + wire lq0_execute_vld_d; // lq0_iu_execute_vld + wire lq0_execute_vld_q; // lq0_iu_execute_vld + wire [0:`ITAG_SIZE_ENC-1] lq0_itag_q; // lq0_iu_itag + wire lq0_n_flush_q; // lq0_iu_n_flush + wire lq0_np1_flush_q; // lq0_iu_np1_flush + wire lq0_dacr_type_q; // lq0_iu_dacr_type + wire [0:3] lq0_dacrw_q; // lq0_iu_dacrw + wire [0:31] lq0_instr_q; // lq0_iu_instr + wire [64-`GPR_WIDTH:63] lq0_eff_addr_q; // lq0_iu_eff_addr + wire lq0_exception_val_d; + wire lq0_exception_val_q; // lq0_iu_exception_val + wire [0:5] lq0_exception_q; // lq0_iu_exception + wire lq0_flush2ucode_q; // lq0_iu_flush2ucode + wire lq0_flush2ucode_type_q; // lq0_iu_flush2ucode_type + wire lq0_recirc_val_q; // lq0_iu_recirc_val + wire lq1_execute_vld_d; // lq1_iu_execute_vld + wire lq1_execute_vld_q; // lq1_iu_execute_vld + wire [0:`ITAG_SIZE_ENC-1] lq1_itag_q; // lq1_iu_itag + wire lq1_n_flush_q; // lq1_iu_n_flush + wire lq1_np1_flush_q; // lq1_iu_np1_flush + wire lq1_exception_val_q; // lq1_iu_exception_val + wire [0:5] lq1_exception_q; // lq1_iu_exception + wire lq1_dacr_type_q; + wire [0:3] lq1_dacrw_q; + wire [0:3] lq1_perf_events_q; + wire br_execute_vld_d; // br_iu_execute_vld + wire br_execute_vld_q; // br_iu_execute_vld + wire [0:`ITAG_SIZE_ENC-1] br_itag_q; // br_iu_itag + wire br_taken_q; // br_iu_taken + wire br_redirect_q; // br_iu_redirect + wire [62-`EFF_IFAR_ARCH:61] br_bta_q; // br_iu_bta + wire [62-`EFF_IFAR_ARCH:61] br_bta_d; + wire [0:3] br_perf_events_q; + wire xu_execute_vld_d; // xu_iu_execute_vld + wire xu_execute_vld_q; // xu_iu_execute_vld + wire [0:`ITAG_SIZE_ENC-1] xu_itag_q; // xu_iu_itag + wire xu_n_flush_q; // xu_iu_n_flush + wire xu_np1_flush_q; // xu_iu_np1_flush + wire xu_flush2ucode_q; // xu_iu_flush2ucode + wire xu_exception_val_q; // xu_iu_exception_val + wire xu_exception_val_d; + wire [0:4] xu_exception_q; // xu_iu_exception + wire xu_mtiar_q; // xu_iu_mtiar + wire [62-`EFF_IFAR_ARCH:61] xu_bta_q; // xu_iu_bta + wire [0:3] xu_perf_events_q; + wire xu1_execute_vld_d; // xu1_iu_execute_vld + wire xu1_execute_vld_q; // xu1_iu_execute_vld + wire [0:`ITAG_SIZE_ENC-1] xu1_itag_q; // xu1_iu_itag + wire axu0_execute_vld_d; // axu0_iu_execute_vld + wire axu0_execute_vld_q; // axu0_iu_execute_vld + wire [0:`ITAG_SIZE_ENC-1] axu0_itag_q; // axu0_iu_itag + wire axu0_n_flush_q; // axu0_iu_n_flush + wire axu0_np1_flush_q; // axu0_iu_np1_flush + wire axu0_n_np1_flush_q; // axu0_iu_n_np1_flush + wire axu0_flush2ucode_q; // axu0_iu_flush2ucode + wire axu0_flush2ucode_type_q; // axu0_iu_flush2ucode_type + wire axu0_exception_val_q; // axu0_iu_exception_val + wire [0:3] axu0_exception_q; // axu0_iu_exception + wire [0:3] axu0_perf_events_q; + wire axu1_execute_vld_d; // axu1_iu_execute_vld + wire axu1_execute_vld_q; // axu1_iu_execute_vld + wire [0:`ITAG_SIZE_ENC-1] axu1_itag_q; // axu1_iu_itag + wire axu1_n_flush_q; // axu1_iu_n_flush + wire axu1_np1_flush_q; // axu1_iu_np1_flush + wire axu1_n_np1_flush_q; // axu1_iu_n_np1_flush + wire axu1_flush2ucode_q; // axu1_iu_flush2ucode + wire axu1_flush2ucode_type_q; // axu1_iu_flush2ucode_type + wire axu1_exception_val_q; // axu1_iu_exception_val + wire [0:3] axu1_exception_q; // axu1_iu_exception + wire [0:3] axu1_perf_events_q; + wire iu_xu_cp3_rfi_q; + wire iu_xu_cp2_rfi_d; + wire iu_xu_cp3_rfgi_q; + wire iu_xu_cp2_rfgi_d; + wire iu_xu_cp3_rfci_q; + wire iu_xu_cp2_rfci_d; + wire iu_xu_cp3_rfmci_q; + wire iu_xu_cp2_rfmci_d; + wire iu_xu_cp4_rfi_q; + wire iu_xu_cp4_rfgi_q; + wire iu_xu_cp4_rfci_q; + wire iu_xu_cp4_rfmci_q; + wire cp3_ld_save_q; + wire cp3_ld_save_d; + wire cp3_st_save_q; + wire cp3_st_save_d; + wire cp3_fp_save_q; + wire cp3_fp_save_d; + wire cp3_ap_save_q; + wire cp3_ap_save_d; + wire cp3_spv_save_q; + wire cp3_spv_save_d; + wire cp3_epid_save_q; + wire cp3_epid_save_d; + wire cp3_async_hold_q; + wire cp3_async_hold_d; + wire cp2_async_hold; + wire cp2_flush_q; + wire cp1_flush; + wire cp3_flush_q; // cp3_flush_q + wire cp3_flush_d; + wire cp4_flush_q; // cp4_flush_q used to gate off incoming executes + wire cp3_rfi_q; // cp3_rfi_q + wire cp2_rfi; + wire cp3_attn_q; // cp3_attn_q + wire cp2_attn; + wire cp3_sc_q; // cp3_sc_q + wire cp2_sc; + wire cp3_icmp_block_q; // cp2_icmp_block + wire cp2_icmp_block; + wire cp3_async_int_val_q; + wire [0:31] cp3_async_int_q; + wire cp3_iu_excvec_val_q; + wire cp2_iu_excvec_val; + wire [0:3] cp3_iu_excvec_q; + wire [0:3] cp2_iu_excvec; + wire cp3_lq_excvec_val_q; + wire cp2_lq_excvec_val; + wire [0:5] cp3_lq_excvec_q; + wire [0:5] cp2_lq_excvec; + wire cp3_xu_excvec_val_q; + wire cp2_xu_excvec_val; + wire [0:4] cp3_xu_excvec_q; + wire [0:4] cp2_xu_excvec; + wire cp3_axu_excvec_val_q; + wire cp2_axu_excvec_val; + wire [0:3] cp3_axu_excvec_q; + wire [0:3] cp2_axu_excvec; + wire cp3_db_val_q; + wire cp2_db_val; + wire [0:18] cp3_db_events_q; + wire [0:18] cp2_db_events; + wire cp3_ld_q; + wire cp2_ld; + wire cp3_st_q; + wire cp2_st; + wire cp3_fp_q; + wire cp2_fp; + wire cp3_ap_q; + wire cp2_ap; + wire cp3_spv_q; + wire cp2_spv; + wire cp3_epid_q; + wire cp2_epid; + wire [43:61] cp3_ifar_q; + wire [43:61] cp2_ifar; + wire cp3_np1_flush_q; + wire cp2_np1_flush; + wire cp3_ucode_q; + wire cp3_preissue_q; + wire cp2_ucode; + wire cp2_preissue; + wire cp3_nia_act; + wire [62-`EFF_IFAR_ARCH:61] cp3_nia_q; + wire [62-`EFF_IFAR_ARCH:61] cp2_nia; + wire [62-`EFF_IFAR_ARCH:61] nia_mask; + wire cp3_flush2ucode_q; + wire cp2_flush2ucode; + wire cp3_flush2ucode_type_q; + wire cp2_flush2ucode_type; + wire cp3_flush_nonspec_q; + wire cp2_flush_nonspec; + wire cp3_mispredict_q; + wire cp2_mispredict; + wire cp4_rfi_q; + wire cp3_rfi; + wire cp5_rfi_q; + wire cp6_rfi_q; + wire cp7_rfi_q; + wire cp8_rfi_q; + wire cp4_excvec_val_q; + wire cp4_excvec_val; + wire cp3_excvec_val; + wire cp4_dp_cp_async_flush_q; + wire cp3_dp_cp_async_flush; + wire cp4_dp_cp_async_bus_snoop_flush_q; + wire cp3_dp_cp_async_bus_snoop_flush; + wire cp4_async_np1_q; + wire cp3_async_np1; + wire cp3_async_n; + wire cp4_async_n_q; + wire cp3_mm_iu_exception; + wire cp4_pc_stop_q; + wire cp3_pc_stop; + wire pc_stop_hold_q; + wire pc_stop_hold_d; + wire cp4_mc_int_q; + wire cp3_mc_int; + wire cp4_g_int_q; + wire cp3_g_int; + wire cp4_c_int_q; + wire cp3_c_int; + wire cp4_dbell_int_q; + wire cp3_dbell_int; + wire cp4_cdbell_int_q; + wire cp3_cdbell_int; + wire cp4_gdbell_int_q; + wire cp3_gdbell_int; + wire cp4_gcdbell_int_q; + wire cp3_gcdbell_int; + wire cp4_gmcdbell_int_q; + wire cp3_gmcdbell_int; + wire cp4_dbsr_update_q; + wire cp3_dbsr_update; + wire cp4_eheir_update_q; + wire cp3_eheir_update; + wire [0:18] cp4_dbsr_q; + wire [0:18] cp3_dbsr; + wire cp4_esr_update_q; + wire cp3_esr_update; + wire [0:16] cp4_exc_esr_q; + wire [0:16] cp3_exc_esr; + wire [0:14] cp4_exc_mcsr_q; + wire [0:14] cp3_exc_mcsr; + wire cp4_asyn_irpt_needed_q; + wire cp4_asyn_irpt_needed_d; + wire cp4_asyn_icmp_needed_q; + wire cp4_asyn_icmp_needed_d; + wire [62-`EFF_IFAR_ARCH:61] cp4_exc_nia_q; + wire [62-`EFF_IFAR_ARCH:61] cp3_exc_nia; + wire cp4_mchk_disabled_q; + wire cp3_mchk_disabled; + wire cp4_dear_update_q; + wire cp3_dear_update; + wire [0:1] flush_hold_q; + wire [0:1] flush_hold_d; + wire flush_hold; + wire pc_iu_init_reset_q; + wire dp_cp_async_flush_q; + wire dp_cp_async_flush_d; + wire dp_cp_async_bus_snoop_flush_q; + wire dp_cp_async_bus_snoop_flush_d; + wire np1_async_flush_q; + wire np1_async_flush_d; + wire msr_de_q; + wire msr_pr_q; + wire msr_cm_q; + wire msr_cm_noact_q; + wire msr_gs_q; + wire msr_me_q; + wire dbcr0_edm_q; + wire dbcr0_idm_q; + wire dbcr0_icmp_q; + wire dbcr0_brt_q; + wire dbcr0_irpt_q; + wire dbcr0_trap_q; + wire iac1_en_q; + wire iac2_en_q; + wire iac3_en_q; + wire iac4_en_q; + wire [0:1] dbcr0_dac1_q; + wire [0:1] dbcr0_dac2_q; + wire [0:1] dbcr0_dac3_q; + wire [0:1] dbcr0_dac4_q; + wire dbcr0_ret_q; + wire dbcr1_iac12m_q; + wire dbcr1_iac34m_q; + wire dbcr3_ivc_q; + wire epcr_extgs_q; + wire epcr_dtlbgs_q; + wire epcr_itlbgs_q; + wire epcr_dsigs_q; + wire epcr_isigs_q; + wire epcr_duvd_q; + wire epcr_icm_q; + wire epcr_gicm_q; + wire ccr2_ucode_dis_q; + wire ccr2_mmu_mode_q; + wire xu_iu_xucr4_mmu_mchk_q; + wire pc_iu_ram_active_q; + wire pc_iu_ram_flush_thread_q; + wire xu_iu_msrovride_enab_q; + wire pc_iu_stop_q; + wire pc_iu_step_q; + wire [0:15] spr_perf_mux_ctrls_q; + wire [0:2] pc_iu_dbg_action_q; + wire xu_iu_single_instr_q; + wire spr_single_issue_q; + wire [64-`GPR_WIDTH:51] spr_ivpr_q; + wire [64-`GPR_WIDTH:51] spr_givpr_q; + wire [62-`EFF_IFAR_ARCH:61] spr_iac1_q; + wire [62-`EFF_IFAR_ARCH:61] spr_iac2_q; + wire [62-`EFF_IFAR_ARCH:61] spr_iac3_q; + wire [62-`EFF_IFAR_ARCH:61] spr_iac4_q; + wire iu_pc_step_done_q; + wire iu_pc_step_done_d; + wire uncond_dbg_event_q; + wire external_mchk_q; + wire ext_interrupt_q; + wire dec_interrupt_q; + wire udec_interrupt_q; + wire perf_interrupt_q; + wire fit_interrupt_q; + wire crit_interrupt_q; + wire wdog_interrupt_q; + wire gwdog_interrupt_q; + wire gfit_interrupt_q; + wire gdec_interrupt_q; + wire dbell_interrupt_q; + wire cdbell_interrupt_q; + wire gdbell_interrupt_q; + wire gcdbell_interrupt_q; + wire gmcdbell_interrupt_q; + wire dbsr_interrupt_q; + wire fex_interrupt_q; + wire [0:2] async_delay_cnt_q; + wire [0:2] async_delay_cnt_d; + wire iu_lq_recirc_val_q; + wire iu_lq_recirc_val_d; + wire [0:`ITAG_SIZE_ENC-1] cp_next_itag_q; + wire [0:`ITAG_SIZE_ENC-1] cp_next_itag_d; + wire [62-`EFF_IFAR_ARCH:61] xu_iu_rest_ifar_q; + wire attn_hold_q; + wire attn_hold_d; + wire [0:1] flush_delay_q; + wire [0:1] flush_delay_d; + wire iu_nonspec_q; + wire iu_nonspec_d; + wire nonspec_release; + wire ierat_pt_fault_q; + wire ierat_pt_fault_d; + wire ierat_lrat_miss_q; + wire ierat_lrat_miss_d; + wire ierat_tlb_inelig_q; + wire ierat_tlb_inelig_d; + wire tlb_multihit_err_q; + wire tlb_multihit_err_d; + wire tlb_par_err_q; + wire tlb_par_err_d; + wire lru_par_err_q; + wire lru_par_err_d; + wire tlb_miss_q; + wire tlb_miss_d; + wire reload_hit_d; + wire reload_hit_q; + wire nonspec_hit_d; + wire nonspec_hit_q; + + wire [0:5] cp_mm_except_taken_d; + wire [0:5] cp_mm_except_taken_q; + + wire eheir_val_d; + wire eheir_val_q; + + wire [0:3] event_bus_out_d; + wire [0:3] event_bus_out_q; + + // External Debug + wire ext_dbg_stop_d; + wire ext_dbg_stop_q; + wire ext_dbg_stop_other_d; + wire ext_dbg_stop_other_q; + wire ext_dbg_act_err_d; + wire ext_dbg_act_err_q; + wire ext_dbg_act_ext_d; + wire ext_dbg_act_ext_q; + wire dbg_int_en_d; + wire dbg_int_en_q; + wire dbg_flush_en; + wire dbg_event_en_d; + wire dbg_event_en_q; + + // Scanchains + parameter iu6_i0_itag_offset = 0; + parameter iu6_i1_itag_offset = iu6_i0_itag_offset + `ITAG_SIZE_ENC-1; + parameter cp1_i0_itag_offset = iu6_i1_itag_offset + `ITAG_SIZE_ENC-1; + parameter cp1_i0_ptr_offset = cp1_i0_itag_offset + `ITAG_SIZE_ENC; + parameter cp1_i1_itag_offset = cp1_i0_ptr_offset + `CPL_Q_DEPTH; + parameter cp1_i1_ptr_offset = cp1_i1_itag_offset + `ITAG_SIZE_ENC; + parameter cp2_i0_itag_offset = cp1_i1_ptr_offset + `CPL_Q_DEPTH; + parameter cp2_i1_itag_offset = cp2_i0_itag_offset + `ITAG_SIZE_ENC; + parameter cp2_async_int_val_offset = cp2_i1_itag_offset + `ITAG_SIZE_ENC; + parameter cp2_async_int_offset = cp2_async_int_val_offset + 1; + parameter cp2_i0_completed_offset = cp2_async_int_offset + 32; + parameter cp2_i1_completed_offset = cp2_i0_completed_offset + 1; + parameter cp2_i0_np1_flush_offset = cp2_i1_completed_offset + 1; + parameter cp2_i1_np1_flush_offset = cp2_i0_np1_flush_offset + 1; + parameter cp2_i0_n_np1_flush_offset = cp2_i1_np1_flush_offset + 1; + parameter cp2_i1_n_np1_flush_offset = cp2_i0_n_np1_flush_offset + 1; + parameter cp2_i0_bp_pred_offset = cp2_i1_n_np1_flush_offset + 1; + parameter cp2_i1_bp_pred_offset = cp2_i0_bp_pred_offset + 1; + parameter cp2_i0_br_pred_offset = cp2_i1_bp_pred_offset + 1; + parameter cp2_i1_br_pred_offset = cp2_i0_br_pred_offset + 1; + parameter cp2_i0_br_miss_offset = cp2_i1_br_pred_offset + 1; + parameter cp2_i1_br_miss_offset = cp2_i0_br_miss_offset + 1; + parameter cp2_i0_db_val_offset = cp2_i1_br_miss_offset + 1; + parameter cp2_i0_db_events_offset = cp2_i0_db_val_offset + 1; + parameter cp2_i1_db_val_offset = cp2_i0_db_events_offset + 19; + parameter cp2_i1_db_events_offset = cp2_i1_db_val_offset + 1; + parameter cp2_i0_perf_events_offset = cp2_i1_db_events_offset + 19; + parameter cp2_i1_perf_events_offset = cp2_i0_perf_events_offset + 4; + parameter cp2_i0_flush2ucode_offset = cp2_i1_perf_events_offset + 4; + parameter cp2_i0_flush2ucode_type_offset = cp2_i0_flush2ucode_offset + 1; + parameter cp2_i1_flush2ucode_offset = cp2_i0_flush2ucode_type_offset + 1; + parameter cp2_i1_flush2ucode_type_offset = cp2_i1_flush2ucode_offset + 1; + parameter cp2_i_bta_offset = cp2_i1_flush2ucode_type_offset + 1; + parameter cp2_i0_iu_excvec_val_offset = cp2_i_bta_offset + `EFF_IFAR_ARCH; + parameter cp2_i0_iu_excvec_offset = cp2_i0_iu_excvec_val_offset + 1; + parameter cp2_i1_iu_excvec_val_offset = cp2_i0_iu_excvec_offset + 4; + parameter cp2_i1_iu_excvec_offset = cp2_i1_iu_excvec_val_offset + 1; + parameter cp2_i0_lq_excvec_val_offset = cp2_i1_iu_excvec_offset + 4; + parameter cp2_i0_lq_excvec_offset = cp2_i0_lq_excvec_val_offset + 1; + parameter cp2_i1_lq_excvec_val_offset = cp2_i0_lq_excvec_offset + 6; + parameter cp2_i1_lq_excvec_offset = cp2_i1_lq_excvec_val_offset + 1; + parameter cp2_i0_xu_excvec_val_offset = cp2_i1_lq_excvec_offset + 6; + parameter cp2_i0_xu_excvec_offset = cp2_i0_xu_excvec_val_offset + 1; + parameter cp2_i1_xu_excvec_val_offset = cp2_i0_xu_excvec_offset + 5; + parameter cp2_i1_xu_excvec_offset = cp2_i1_xu_excvec_val_offset + 1; + parameter cp2_i0_axu_excvec_val_offset = cp2_i1_xu_excvec_offset + 5; + parameter cp2_i0_axu_excvec_offset = cp2_i0_axu_excvec_val_offset + 1; + parameter cp2_i1_axu_excvec_val_offset = cp2_i0_axu_excvec_offset + 4; + parameter cp2_i1_axu_excvec_offset = cp2_i1_axu_excvec_val_offset + 1; + parameter cp1_executed_offset = cp2_i1_axu_excvec_offset + 4; + parameter cp1_dispatched_offset = cp1_executed_offset + `CPL_Q_DEPTH; + parameter cp1_n_flush_offset = cp1_dispatched_offset + `CPL_Q_DEPTH; + parameter cp1_np1_flush_offset = cp1_n_flush_offset + `CPL_Q_DEPTH; + parameter cp1_n_np1_flush_offset = cp1_np1_flush_offset + `CPL_Q_DEPTH; + parameter cp1_flush2ucode_offset = cp1_n_np1_flush_offset + `CPL_Q_DEPTH; + parameter cp1_flush2ucode_type_offset = cp1_flush2ucode_offset + `CPL_Q_DEPTH; + parameter cp1_perf_events_offset = cp1_flush2ucode_type_offset + `CPL_Q_DEPTH; + parameter cp1_iu_excvec_val_offset = cp1_perf_events_offset + 4 * `CPL_Q_DEPTH; + parameter cp1_iu_excvec_offset = cp1_iu_excvec_val_offset + 1 * `CPL_Q_DEPTH; + parameter cp1_lq_excvec_val_offset = cp1_iu_excvec_offset + 4 * `CPL_Q_DEPTH; + parameter cp1_lq_excvec_offset = cp1_lq_excvec_val_offset + 1 * `CPL_Q_DEPTH; + parameter cp1_xu_excvec_val_offset = cp1_lq_excvec_offset + 6 * `CPL_Q_DEPTH; + parameter cp1_xu_excvec_offset = cp1_xu_excvec_val_offset + 1 * `CPL_Q_DEPTH; + parameter cp1_axu_excvec_val_offset = cp1_xu_excvec_offset + 5 * `CPL_Q_DEPTH; + parameter cp1_axu_excvec_offset = cp1_axu_excvec_val_offset + 1 * `CPL_Q_DEPTH; + parameter cp1_db_events_offset = cp1_axu_excvec_offset + 4 * `CPL_Q_DEPTH; + parameter cp1_recirc_vld_offset = cp1_db_events_offset + 19 * `CPL_Q_DEPTH; + parameter cp1_async_block_offset = cp1_recirc_vld_offset + 1 * `CPL_Q_DEPTH; + parameter cp1_is_br_offset = cp1_async_block_offset + 1 * `CPL_Q_DEPTH; + parameter cp1_br_add_chk_offset = cp1_is_br_offset + 1 * `CPL_Q_DEPTH; + parameter cp1_bp_pred_offset = cp1_br_add_chk_offset + 1 * `CPL_Q_DEPTH; + parameter cp1_br_pred_offset = cp1_bp_pred_offset + 1 * `CPL_Q_DEPTH; + parameter cp1_br_miss_offset = cp1_br_pred_offset + 1 * `CPL_Q_DEPTH; + parameter cp1_br_bta_offset = cp1_br_miss_offset + 1 * `CPL_Q_DEPTH; + parameter cp1_br_bta_v_offset = cp1_br_bta_offset + `EFF_IFAR_ARCH; + parameter cp1_br_bta_itag_offset = cp1_br_bta_v_offset + 1; + parameter cp0_i0_dispatched_offset = cp1_br_bta_itag_offset + `ITAG_SIZE_ENC; + parameter cp0_i1_dispatched_offset = cp0_i0_dispatched_offset + 1; + parameter cp0_i0_ifar_offset = cp0_i1_dispatched_offset + 1; + parameter cp0_i0_ucode_offset = cp0_i0_ifar_offset + `EFF_IFAR_WIDTH; + parameter cp0_i0_fuse_nop_offset = cp0_i0_ucode_offset + 3; + parameter cp0_i0_error_offset = cp0_i0_fuse_nop_offset + 1; + parameter cp0_i0_valop_offset = cp0_i0_error_offset + 3; + parameter cp0_i0_is_rfi_offset = cp0_i0_valop_offset + 1; + parameter cp0_i0_is_rfgi_offset = cp0_i0_is_rfi_offset + 1; + parameter cp0_i0_is_rfci_offset = cp0_i0_is_rfgi_offset + 1; + parameter cp0_i0_is_rfmci_offset = cp0_i0_is_rfci_offset + 1; + parameter cp0_i0_is_isync_offset = cp0_i0_is_rfmci_offset + 1; + parameter cp0_i0_is_sc_offset = cp0_i0_is_isync_offset + 1; + parameter cp0_i0_is_np1_flush_offset = cp0_i0_is_sc_offset + 1; + parameter cp0_i0_is_sc_hyp_offset = cp0_i0_is_np1_flush_offset + 1; + parameter cp0_i0_is_sc_ill_offset = cp0_i0_is_sc_hyp_offset + 1; + parameter cp0_i0_is_dcr_ill_offset = cp0_i0_is_sc_ill_offset + 1; + parameter cp0_i0_is_attn_offset = cp0_i0_is_dcr_ill_offset + 1; + parameter cp0_i0_is_ehpriv_offset = cp0_i0_is_attn_offset + 1; + parameter cp0_i0_is_folded_offset = cp0_i0_is_ehpriv_offset + 1; + parameter cp0_i0_async_block_offset = cp0_i0_is_folded_offset + 1; + parameter cp0_i0_is_br_offset = cp0_i0_async_block_offset + 1; + parameter cp0_i0_br_add_chk_offset = cp0_i0_is_br_offset + 1; + parameter cp0_i0_bp_pred_offset = cp0_i0_br_add_chk_offset + 1; + parameter cp0_i0_rollover_offset = cp0_i0_bp_pred_offset + 1; + parameter cp0_i0_isram_offset = cp0_i0_rollover_offset + 1; + parameter cp0_i0_match_offset = cp0_i0_isram_offset + 1; + parameter cp0_i1_ifar_offset = cp0_i0_match_offset + 1; + parameter cp0_i1_ucode_offset = cp0_i1_ifar_offset + `EFF_IFAR_WIDTH; + parameter cp0_i1_fuse_nop_offset = cp0_i1_ucode_offset + 3; + parameter cp0_i1_error_offset = cp0_i1_fuse_nop_offset + 1; + parameter cp0_i1_valop_offset = cp0_i1_error_offset + 3; + parameter cp0_i1_is_rfi_offset = cp0_i1_valop_offset + 1; + parameter cp0_i1_is_rfgi_offset = cp0_i1_is_rfi_offset + 1; + parameter cp0_i1_is_rfci_offset = cp0_i1_is_rfgi_offset + 1; + parameter cp0_i1_is_rfmci_offset = cp0_i1_is_rfci_offset + 1; + parameter cp0_i1_is_isync_offset = cp0_i1_is_rfmci_offset + 1; + parameter cp0_i1_is_sc_offset = cp0_i1_is_isync_offset + 1; + parameter cp0_i1_is_np1_flush_offset = cp0_i1_is_sc_offset + 1; + parameter cp0_i1_is_sc_hyp_offset = cp0_i1_is_np1_flush_offset + 1; + parameter cp0_i1_is_sc_ill_offset = cp0_i1_is_sc_hyp_offset + 1; + parameter cp0_i1_is_dcr_ill_offset = cp0_i1_is_sc_ill_offset + 1; + parameter cp0_i1_is_attn_offset = cp0_i1_is_dcr_ill_offset + 1; + parameter cp0_i1_is_ehpriv_offset = cp0_i1_is_attn_offset + 1; + parameter cp0_i1_is_folded_offset = cp0_i1_is_ehpriv_offset + 1; + parameter cp0_i1_async_block_offset = cp0_i1_is_folded_offset + 1; + parameter cp0_i1_is_br_offset = cp0_i1_async_block_offset + 1; + parameter cp0_i1_br_add_chk_offset = cp0_i1_is_br_offset + 1; + parameter cp0_i1_bp_pred_offset = cp0_i1_br_add_chk_offset + 1; + parameter cp0_i1_rollover_offset = cp0_i1_bp_pred_offset + 1; + parameter cp0_i1_isram_offset = cp0_i1_rollover_offset + 1; + parameter cp0_i1_match_offset = cp0_i1_isram_offset + 1; + parameter cp0_uc_hold_rollover_offset = cp0_i1_match_offset + 1; + parameter lq0_execute_vld_offset = cp0_uc_hold_rollover_offset + 1; + parameter lq0_itag_offset = lq0_execute_vld_offset + 1; + parameter lq0_n_flush_offset = lq0_itag_offset + `ITAG_SIZE_ENC; + parameter lq0_np1_flush_offset = lq0_n_flush_offset + 1; + parameter lq0_dacr_type_offset = lq0_np1_flush_offset + 1; + parameter lq0_dacrw_offset = lq0_dacr_type_offset + 1; + parameter lq0_instr_offset = lq0_dacrw_offset + 4; + parameter lq0_eff_addr_offset = lq0_instr_offset + 32; + parameter lq0_exception_val_offset = lq0_eff_addr_offset + `GPR_WIDTH; + parameter lq0_exception_offset = lq0_exception_val_offset + 1; + parameter lq0_flush2ucode_offset = lq0_exception_offset + 6; + parameter lq0_flush2ucode_type_offset = lq0_flush2ucode_offset + 1; + parameter lq0_recirc_val_offset = lq0_flush2ucode_type_offset + 1; + parameter lq1_execute_vld_offset = lq0_recirc_val_offset + 1; + parameter lq1_itag_offset = lq1_execute_vld_offset + 1; + parameter lq1_n_flush_offset = lq1_itag_offset + `ITAG_SIZE_ENC; + parameter lq1_np1_flush_offset = lq1_n_flush_offset + 1; + parameter lq1_exception_val_offset = lq1_np1_flush_offset + 1; + parameter lq1_exception_offset = lq1_exception_val_offset + 1; + parameter lq1_dacr_type_offset = lq1_exception_offset + 6; + parameter lq1_dacrw_offset = lq1_dacr_type_offset + 1; + parameter lq1_perf_events_offset = lq1_dacrw_offset + 4; + parameter br_perf_events_offset = lq1_perf_events_offset + 4; + parameter axu0_perf_events_offset = br_perf_events_offset + 4; + parameter axu1_perf_events_offset = axu0_perf_events_offset + 4; + parameter br_execute_vld_offset = axu1_perf_events_offset + 4; + parameter br_itag_offset = br_execute_vld_offset + 1; + parameter br_taken_offset = br_itag_offset + `ITAG_SIZE_ENC; + parameter br_redirect_offset = br_taken_offset + 1; + parameter br_bta_offset = br_redirect_offset + 1; + parameter xu_execute_vld_offset = br_bta_offset + `EFF_IFAR_ARCH; + parameter xu_itag_offset = xu_execute_vld_offset + 1; + parameter xu_n_flush_offset = xu_itag_offset + `ITAG_SIZE_ENC; + parameter xu_np1_flush_offset = xu_n_flush_offset + 1; + parameter xu_flush2ucode_offset = xu_np1_flush_offset + 1; + parameter xu_exception_val_offset = xu_flush2ucode_offset + 1; + parameter xu_exception_offset = xu_exception_val_offset + 1; + parameter xu_mtiar_offset = xu_exception_offset + 5; + parameter xu_bta_offset = xu_mtiar_offset + 1; + parameter xu_perf_events_offset = xu_bta_offset + `EFF_IFAR_ARCH; + parameter xu1_execute_vld_offset = xu_perf_events_offset + 4; + parameter xu1_itag_offset = xu1_execute_vld_offset + 1; + parameter axu0_execute_vld_offset = xu1_itag_offset + `ITAG_SIZE_ENC; + parameter axu0_itag_offset = axu0_execute_vld_offset + 1; + parameter axu0_n_flush_offset = axu0_itag_offset + `ITAG_SIZE_ENC; + parameter axu0_np1_flush_offset = axu0_n_flush_offset + 1; + parameter axu0_n_np1_flush_offset = axu0_np1_flush_offset + 1; + parameter axu0_flush2ucode_offset = axu0_n_np1_flush_offset + 1; + parameter axu0_flush2ucode_type_offset = axu0_flush2ucode_offset + 1; + parameter axu0_exception_val_offset = axu0_flush2ucode_type_offset + 1; + parameter axu0_exception_offset = axu0_exception_val_offset + 1; + parameter axu1_execute_vld_offset = axu0_exception_offset + 4; + parameter axu1_itag_offset = axu1_execute_vld_offset + 1; + parameter axu1_n_flush_offset = axu1_itag_offset + `ITAG_SIZE_ENC; + parameter axu1_np1_flush_offset = axu1_n_flush_offset + 1; + parameter axu1_n_np1_flush_offset = axu1_np1_flush_offset + 1; + parameter axu1_flush2ucode_offset = axu1_n_np1_flush_offset + 1; + parameter axu1_flush2ucode_type_offset = axu1_flush2ucode_offset + 1; + parameter axu1_exception_val_offset = axu1_flush2ucode_type_offset + 1; + parameter axu1_exception_offset = axu1_exception_val_offset + 1; + parameter iu_xu_cp3_rfi_offset = axu1_exception_offset + 4; + parameter iu_xu_cp3_rfgi_offset = iu_xu_cp3_rfi_offset + 1; + parameter iu_xu_cp3_rfci_offset = iu_xu_cp3_rfgi_offset + 1; + parameter iu_xu_cp3_rfmci_offset = iu_xu_cp3_rfci_offset + 1; + parameter iu_xu_cp4_rfi_offset = iu_xu_cp3_rfmci_offset + 1; + parameter iu_xu_cp4_rfgi_offset = iu_xu_cp4_rfi_offset + 1; + parameter iu_xu_cp4_rfci_offset = iu_xu_cp4_rfgi_offset + 1; + parameter iu_xu_cp4_rfmci_offset = iu_xu_cp4_rfci_offset + 1; + parameter cp3_ld_save_offset = iu_xu_cp4_rfmci_offset + 1; + parameter cp3_st_save_offset = cp3_ld_save_offset + 1; + parameter cp3_fp_save_offset = cp3_st_save_offset + 1; + parameter cp3_ap_save_offset = cp3_fp_save_offset + 1; + parameter cp3_spv_save_offset = cp3_ap_save_offset + 1; + parameter cp3_epid_save_offset = cp3_spv_save_offset + 1; + parameter cp3_async_hold_offset = cp3_epid_save_offset + 1; + parameter cp2_flush_offset = cp3_async_hold_offset + 1; + parameter cp3_flush_offset = cp2_flush_offset + 1; + parameter cp4_flush_offset = cp3_flush_offset + 1; + parameter cp3_rfi_offset = cp4_flush_offset + 1; + parameter cp3_attn_offset = cp3_rfi_offset + 1; + parameter cp3_sc_offset = cp3_attn_offset + 1; + parameter cp3_icmp_block_offset = cp3_sc_offset + 1; + parameter cp3_flush2ucode_offset = cp3_icmp_block_offset + 1; + parameter cp3_flush2ucode_type_offset = cp3_flush2ucode_offset + 1; + parameter cp3_flush_nonspec_offset = cp3_flush2ucode_type_offset + 1; + parameter cp3_mispredict_offset = cp3_flush_nonspec_offset + 1; + parameter cp3_async_int_val_offset = cp3_mispredict_offset + 1; + parameter cp3_async_int_offset = cp3_async_int_val_offset + 1; + parameter cp3_iu_excvec_val_offset = cp3_async_int_offset + 32; + parameter cp3_iu_excvec_offset = cp3_iu_excvec_val_offset + 1; + parameter cp3_lq_excvec_val_offset = cp3_iu_excvec_offset + 4; + parameter cp3_lq_excvec_offset = cp3_lq_excvec_val_offset + 1; + parameter cp3_xu_excvec_val_offset = cp3_lq_excvec_offset + 6; + parameter cp3_xu_excvec_offset = cp3_xu_excvec_val_offset + 1; + parameter cp3_axu_excvec_val_offset = cp3_xu_excvec_offset + 5; + parameter cp3_axu_excvec_offset = cp3_axu_excvec_val_offset + 1; + parameter cp3_db_val_offset = cp3_axu_excvec_offset + 4; + parameter cp3_db_events_offset = cp3_db_val_offset + 1; + parameter cp3_ld_offset = cp3_db_events_offset + 19; + parameter cp3_st_offset = cp3_ld_offset + 1; + parameter cp3_fp_offset = cp3_st_offset + 1; + parameter cp3_ap_offset = cp3_fp_offset + 1; + parameter cp3_spv_offset = cp3_ap_offset + 1; + parameter cp3_epid_offset = cp3_spv_offset + 1; + parameter cp3_ifar_offset = cp3_epid_offset + 1; + parameter cp3_np1_flush_offset = cp3_ifar_offset + 19; + parameter cp3_ucode_offset = cp3_np1_flush_offset + 1; + parameter cp3_preissue_offset = cp3_ucode_offset + 1; + parameter cp3_nia_offset = cp3_preissue_offset + 1; + parameter cp4_rfi_offset = cp3_nia_offset + `EFF_IFAR_ARCH; + parameter cp5_rfi_offset = cp4_rfi_offset + 1; + parameter cp6_rfi_offset = cp5_rfi_offset + 1; + parameter cp7_rfi_offset = cp6_rfi_offset + 1; + parameter cp8_rfi_offset = cp7_rfi_offset + 1; + parameter cp4_exc_val_offset = cp8_rfi_offset + 1; + parameter flush_hold_offset = cp4_exc_val_offset + 1; + parameter cp4_dp_cp_async_flush_offset = flush_hold_offset + 2; + parameter cp4_dp_cp_async_bus_snoop_flush_offset = cp4_dp_cp_async_flush_offset + 1; + parameter cp4_async_np1_offset = cp4_dp_cp_async_bus_snoop_flush_offset + 1; + parameter cp4_async_n_offset = cp4_async_np1_offset + 1; + parameter cp4_pc_stop_offset = cp4_async_n_offset + 1; + parameter pc_stop_hold_offset = cp4_pc_stop_offset + 1; + parameter cp4_mc_int_offset = pc_stop_hold_offset + 1; + parameter cp4_mchk_disabled_offset = cp4_mc_int_offset + 1; + parameter cp4_g_int_offset = cp4_mchk_disabled_offset + 1; + parameter cp4_c_int_offset = cp4_g_int_offset + 1; + parameter cp4_dbell_int_offset = cp4_c_int_offset + 1; + parameter cp4_cdbell_int_offset = cp4_dbell_int_offset + 1; + parameter cp4_gdbell_int_offset = cp4_cdbell_int_offset + 1; + parameter cp4_gcdbell_int_offset = cp4_gdbell_int_offset + 1; + parameter cp4_gmcdbell_int_offset = cp4_gcdbell_int_offset + 1; + parameter cp4_dbsr_update_offset = cp4_gmcdbell_int_offset + 1; + parameter cp4_dbsr_offset = cp4_dbsr_update_offset + 1; + parameter cp4_eheir_update_offset = cp4_dbsr_offset + 19; + parameter cp4_esr_update_offset = cp4_eheir_update_offset + 1; + parameter cp4_exc_esr_offset = cp4_esr_update_offset + 1; + parameter cp4_exc_mcsr_offset = cp4_exc_esr_offset + 17; + parameter cp4_asyn_irpt_needed_offset = cp4_exc_mcsr_offset + 15; + parameter cp4_asyn_icmp_needed_offset = cp4_asyn_irpt_needed_offset + 1; + parameter cp4_exc_nia_offset = cp4_asyn_icmp_needed_offset + 1; + parameter cp4_dear_update_offset = cp4_exc_nia_offset + `EFF_IFAR_ARCH; + parameter cp_next_itag_offset = cp4_dear_update_offset + 1; + parameter pc_iu_init_reset_offset = cp_next_itag_offset + `ITAG_SIZE_ENC; + parameter np1_async_flush_offset = pc_iu_init_reset_offset + 1; + parameter dp_cp_async_flush_offset = np1_async_flush_offset + 1; + parameter dp_cp_async_bus_snoop_flush_offset = dp_cp_async_flush_offset + 1; + parameter msr_de_offset = dp_cp_async_bus_snoop_flush_offset + 1; + parameter msr_pr_offset = msr_de_offset + 1; + parameter msr_cm_offset = msr_pr_offset + 1; + parameter msr_cm_noact_offset = msr_cm_offset + 1; + parameter msr_gs_offset = msr_cm_noact_offset + 1; + parameter msr_me_offset = msr_gs_offset + 1; + parameter dbcr0_edm_offset = msr_me_offset + 1; + parameter dbcr0_idm_offset = dbcr0_edm_offset + 1; + parameter dbcr0_icmp_offset = dbcr0_idm_offset + 1; + parameter dbcr0_brt_offset = dbcr0_icmp_offset + 1; + parameter dbcr0_irpt_offset = dbcr0_brt_offset + 1; + parameter dbcr0_trap_offset = dbcr0_irpt_offset + 1; + parameter iac1_en_offset = dbcr0_trap_offset + 1; + parameter iac2_en_offset = iac1_en_offset + 1; + parameter iac3_en_offset = iac2_en_offset + 1; + parameter iac4_en_offset = iac3_en_offset + 1; + parameter dbcr0_dac1_offset = iac4_en_offset + 1; + parameter dbcr0_dac2_offset = dbcr0_dac1_offset + 2; + parameter dbcr0_dac3_offset = dbcr0_dac2_offset + 2; + parameter dbcr0_dac4_offset = dbcr0_dac3_offset + 2; + parameter dbcr0_ret_offset = dbcr0_dac4_offset + 2; + parameter dbcr1_iac12m_offset = dbcr0_ret_offset + 1; + parameter dbcr1_iac34m_offset = dbcr1_iac12m_offset + 1; + parameter dbcr3_ivc_offset = dbcr1_iac34m_offset + 1; + parameter epcr_extgs_offset = dbcr3_ivc_offset + 1; + parameter epcr_dtlbgs_offset = epcr_extgs_offset + 1; + parameter epcr_itlbgs_offset = epcr_dtlbgs_offset + 1; + parameter epcr_dsigs_offset = epcr_itlbgs_offset + 1; + parameter epcr_isigs_offset = epcr_dsigs_offset + 1; + parameter epcr_duvd_offset = epcr_isigs_offset + 1; + parameter epcr_icm_offset = epcr_duvd_offset + 1; + parameter epcr_gicm_offset = epcr_icm_offset + 1; + parameter ccr2_ucode_dis_offset = epcr_gicm_offset + 1; + parameter ccr2_mmu_mode_offset = ccr2_ucode_dis_offset + 1; + parameter pc_iu_ram_active_offset = ccr2_mmu_mode_offset + 1; + parameter xu_iu_xucr4_mmu_mchk_offset = pc_iu_ram_active_offset + 1; + parameter pc_iu_ram_flush_thread_offset = xu_iu_xucr4_mmu_mchk_offset + 1; + parameter xu_iu_msrovride_enab_offset = pc_iu_ram_flush_thread_offset + 1; + parameter pc_iu_stop_offset = xu_iu_msrovride_enab_offset + 1; + parameter pc_iu_step_offset = pc_iu_stop_offset + 1; + parameter xu_iu_single_instr_offset = pc_iu_step_offset + 1; + parameter spr_single_issue_offset = xu_iu_single_instr_offset + 1; + parameter spr_ivpr_offset = spr_single_issue_offset + 1; + parameter spr_givpr_offset = spr_ivpr_offset + `GPR_WIDTH-12; + parameter spr_iac1_offset = spr_givpr_offset + `GPR_WIDTH-12; + parameter spr_iac2_offset = spr_iac1_offset + `EFF_IFAR_ARCH; + parameter spr_iac3_offset = spr_iac2_offset + `EFF_IFAR_ARCH; + parameter spr_iac4_offset = spr_iac3_offset + `EFF_IFAR_ARCH; + parameter spr_perf_mux_ctrls_offset = spr_iac4_offset + `EFF_IFAR_ARCH; + parameter pc_iu_dbg_action_offset = spr_perf_mux_ctrls_offset + 16; + parameter iu_pc_step_done_offset = pc_iu_dbg_action_offset + 3; + parameter uncond_dbg_event_offset = iu_pc_step_done_offset + 1; + parameter external_mchk_offset = uncond_dbg_event_offset + 1; + parameter ext_interrupt_offset = external_mchk_offset + 1; + parameter dec_interrupt_offset = ext_interrupt_offset + 1; + parameter udec_interrupt_offset = dec_interrupt_offset + 1; + parameter perf_interrupt_offset = udec_interrupt_offset + 1; + parameter fit_interrupt_offset = perf_interrupt_offset + 1; + parameter crit_interrupt_offset = fit_interrupt_offset + 1; + parameter wdog_interrupt_offset = crit_interrupt_offset + 1; + parameter gwdog_interrupt_offset = wdog_interrupt_offset + 1; + parameter gfit_interrupt_offset = gwdog_interrupt_offset + 1; + parameter gdec_interrupt_offset = gfit_interrupt_offset + 1; + parameter dbell_interrupt_offset = gdec_interrupt_offset + 1; + parameter cdbell_interrupt_offset = dbell_interrupt_offset + 1; + parameter gdbell_interrupt_offset = cdbell_interrupt_offset + 1; + parameter gcdbell_interrupt_offset = gdbell_interrupt_offset + 1; + parameter gmcdbell_interrupt_offset = gcdbell_interrupt_offset + 1; + parameter dbsr_interrupt_offset = gmcdbell_interrupt_offset + 1; + parameter fex_interrupt_offset = dbsr_interrupt_offset + 1; + parameter async_delay_cnt_offset = fex_interrupt_offset + 1; + parameter iu_lq_recirc_val_offset = async_delay_cnt_offset + 3; + parameter ext_dbg_stop_offset = iu_lq_recirc_val_offset + 1; + parameter ext_dbg_stop_other_offset = ext_dbg_stop_offset + 1; + parameter ext_dbg_act_err_offset = ext_dbg_stop_other_offset + 1; + parameter ext_dbg_act_ext_offset = ext_dbg_act_err_offset + 1; + parameter dbg_int_en_offset = ext_dbg_act_ext_offset + 1; + parameter dbg_event_en_offset = dbg_int_en_offset + 1; + parameter cp1_i0_dispatched_offset = dbg_event_en_offset + 1; + parameter cp1_i1_dispatched_offset = cp1_i0_dispatched_offset + `CPL_Q_DEPTH; + parameter iu7_i0_is_folded_offset = cp1_i1_dispatched_offset + `CPL_Q_DEPTH; + parameter iu7_i1_is_folded_offset = iu7_i0_is_folded_offset + 1; + parameter select_reset_offset = iu7_i1_is_folded_offset + 1; + parameter xu_iu_rest_ifar_offset = select_reset_offset + 1; + parameter attn_hold_offset = xu_iu_rest_ifar_offset + `EFF_IFAR_ARCH; + parameter flush_delay_offset = attn_hold_offset + 1; + parameter iu_nonspec_offset = flush_delay_offset + 2; + parameter ierat_pt_fault_offset = iu_nonspec_offset + 1; + parameter ierat_lrat_miss_offset = ierat_pt_fault_offset + 1; + parameter ierat_tlb_inelig_offset = ierat_lrat_miss_offset + 1; + parameter tlb_multihit_err_offset = ierat_tlb_inelig_offset + 1; + parameter tlb_par_err_offset = tlb_multihit_err_offset + 1; + parameter lru_par_err_offset = tlb_par_err_offset + 1; + parameter tlb_miss_offset = lru_par_err_offset + 1; + parameter reload_hit_offset = tlb_miss_offset + 1; + parameter nonspec_hit_offset = reload_hit_offset + 1; + parameter cp_mm_except_taken_offset = nonspec_hit_offset + 1; + parameter eheir_val_offset = cp_mm_except_taken_offset + 6; + parameter perf_bus_offset = eheir_val_offset + 1; + parameter scan_right = perf_bus_offset + 4; + wire [0:scan_right-1] siv; + wire [0:scan_right-1] sov; + // Signals + wire tidn; + wire tiup; + wire [0:`CPL_Q_DEPTH-1] lq0_execute_vld; + wire [0:`CPL_Q_DEPTH-1] lq0_recirc_vld; + wire [0:`CPL_Q_DEPTH-1] lq1_execute_vld; + wire [0:`CPL_Q_DEPTH-1] br_execute_vld; + wire [0:`CPL_Q_DEPTH-1] fold_i0_execute_vld; + wire [0:`CPL_Q_DEPTH-1] fold_i1_execute_vld; + wire [0:`CPL_Q_DEPTH-1] xu_execute_vld; + wire [0:`CPL_Q_DEPTH-1] xu1_execute_vld; + wire [0:`CPL_Q_DEPTH-1] axu0_execute_vld; + wire [0:`CPL_Q_DEPTH-1] axu1_execute_vld; + wire excvec_act; + wire [0:`CPL_Q_DEPTH-1] excvec_act_v; + wire [0:`CPL_Q_DEPTH-1] cp1_compl_ready; + wire [0:`CPL_Q_DEPTH-1] iu6_i0_ptr; + wire [0:`CPL_Q_DEPTH-1] iu6_i1_ptr; + wire [0:`CPL_Q_DEPTH-1] cp1_i0_dispatched; + wire [0:`CPL_Q_DEPTH-1] cp1_i1_dispatched; + wire [0:`CPL_Q_DEPTH-1] cp1_i0_completed; + wire [0:`CPL_Q_DEPTH-1] cp1_i1_completed; + wire [0:`CPL_Q_DEPTH-1] cp1_i0_completed_ror; + wire [0:`CPL_Q_DEPTH-1] exx_executed; + wire [0:`CPL_Q_DEPTH-1] cp1_completed; + wire [0:`CPL_Q_DEPTH-1] cp1_flushed; + wire [62-`EFF_IFAR_ARCH:61-`EFF_IFAR_WIDTH] cp3_ifor; + + // Reasons to not complete I1 + wire cp1_i01_comp_is_br; // Can't complete 2 branches in a cycle due to BHT writes + wire cp1_i0_comp_is_flush; // If you flush I0 don't complete I1 + + // Signal for NIA selection + wire select_i0_p1; + wire select_i1_p1; + wire select_i0_bta; + wire select_i1_bta; + wire select_i0_bp_bta; + wire select_i1_bp_bta; + wire select_ucode_p1; + wire select_reset; + wire select_reset_q; + wire select_mtiar; + + // IU exception calculations + reg iu6_i0_exception_val; + reg iu6_i1_exception_val; + reg [0:3] iu6_i0_exception; + reg [0:3] iu6_i1_exception; + reg iu6_i0_n_flush; + reg iu6_i1_n_flush; + reg iu6_i0_np1_flush; + reg iu6_i1_np1_flush; + + // Exception decode outputs + wire cp2_i0_iu_excvec_val; + wire cp2_i1_iu_excvec_val; + wire cp2_i0_lq_excvec_val; + wire cp2_i1_lq_excvec_val; + wire cp2_i0_xu_excvec_val; + wire cp2_i1_xu_excvec_val; + wire cp2_i0_axu_excvec_val; + wire cp2_i1_axu_excvec_val; + wire cp2_i0_db_events_val; + wire cp2_i1_db_events_val; + wire cp2_i0_exc_val; + wire cp2_i1_exc_val; + wire cp2_i0_ram_excvec_val; + wire cp1_async_block; + wire cp2_open_async; + wire iu_flush_cond; + wire flush_cond; + + // Instruction Address Compares + wire [62-`EFF_IFAR_ARCH:61] iac2_mask; + wire [62-`EFF_IFAR_ARCH:61] iac4_mask; + wire [0:1] iac1_cmprh; + wire [0:1] iac2_cmprh; + wire [0:1] iac3_cmprh; + wire [0:1] iac4_cmprh; + wire [0:1] iac1_cmprl; + wire [0:1] iac2_cmprl; + wire [0:1] iac3_cmprl; + wire [0:1] iac4_cmprl; + wire [0:1] iac1_cmpr; + wire [0:1] iac2_cmpr; + wire [0:1] iac3_cmpr; + wire [0:1] iac4_cmpr; + wire [0:1] iac1_cmpr_sel; + wire [0:1] iac2_cmpr_sel; + wire [0:1] iac3_cmpr_sel; + wire [0:1] iac4_cmpr_sel; + wire [0:1] ivc_cmpr_sel; + wire ude_dbg_event; + wire [0:1] icmp_dbg_event; + wire [0:1] iac1_dbg_event; + wire [0:1] iac2_dbg_event; + wire [0:1] iac3_dbg_event; + wire [0:1] iac4_dbg_event; + wire [0:1] ret_sel; + wire [0:1] rfi_dbg_event; + wire [0:1] ivc_dbg_event; + wire trap_dbg_event; + wire brt_dbg_event; + wire [0:1] iu_irpt_dbg_event; + wire xu_irpt_dbg_event; + wire axu0_irpt_dbg_event; + wire axu1_irpt_dbg_event; + wire lq0_irpt_dbg_event; + wire lq1_irpt_dbg_event; + wire iac_i0_n_flush; + wire iac_i1_n_flush; + wire dac_lq0_n_flush; + wire dac_lq1_n_flush; + wire [0:1] dac1r_dbg_event; + wire [0:1] dac1w_dbg_event; + wire [0:1] dac2r_dbg_event; + wire [0:1] dac2w_dbg_event; + wire [0:1] dac3r_dbg_event; + wire [0:1] dac3w_dbg_event; + wire [0:1] dac4r_dbg_event; + wire [0:1] dac4w_dbg_event; + wire [0:1] dacr_dbg_event; + wire icmp_enable; + wire irpt_enable; + wire cp3_asyn_irpt_taken; + wire cp3_asyn_irpt_needed; + wire cp3_asyn_icmp_taken; + wire cp3_asyn_icmp_needed; + wire cp3_db_events_masked_reduced; + wire [0:1] iu6_dbg_flush_en; + wire cp2_complete_act; + wire cp2_msr_act; + + wire iu6_i0_db_IAC_IVC_event; + wire iu6_i1_db_IAC_IVC_event; + wire [62-`EFF_IFAR_ARCH:61] iu6_ifar[0:1]; + wire cp_iu0_flush_2ucode_int; + wire cp_flush_into_uc_int; + wire iu_xu_dbsr_ude_int; + + // act signals + wire rn_cp_iu6_i0_act; + wire rn_cp_iu6_i1_act; + + // Signals for itag comparison + wire br_older_xu; + wire br_older_lq; + wire br_older_save; + wire xu_older_lq; + wire xu_older_save; + wire lq_older_save; + wire select_br; + wire select_xu; + wire select_lq; + wire [1:32] save_table_pt; + + // temp signals + wire iu_pc_i0_comp_temp; + wire iu_pc_i1_comp_temp; + + wire cp_mm_itlb_miss; + wire cp_mm_dtlb_miss; + wire cp_mm_isi; + wire cp_mm_dsi; + wire cp_mm_ilrat_miss; + wire cp_mm_dlrat_miss; + wire cp_mm_imchk; + wire cp_mm_dmchk; + + wire dis_mm_mchk; + + wire eheir_val; + wire [1:`ITAG_SIZE_ENC-1] eheir_itag; + wire [0:31] eheir_instr; + + wire cp_events_en; + wire [0:15] cp_events_in; + + wire iu_pc_i0_comp, iu_pc_i1_comp, iu_pc_i0_br_miss, iu_pc_i1_br_miss, iu_pc_i0_br_pred, iu_pc_i1_br_pred, pc_iu_stop_d, iu_pc_flush_cnt; + + assign tidn = 1'b0; + assign tiup = 1'b1; + + function [0:`CPL_Q_DEPTH-1] decode_a; + input [1:`ITAG_SIZE_ENC-1] decode_input; + + //(* analysis_not_referenced="true" *) + + integer i; + for(i = 0; i < `CPL_Q_DEPTH; i = i + 1) + begin + if({{32-`ITAG_SIZE_ENC+1{1'b0}},decode_input} == i) + decode_a[i] = 1'b1; + else + decode_a[i] = 1'b0; + end + endfunction + + //----------------------------------------------------------------------------- + // Temporary + //----------------------------------------------------------------------------- + assign iu_pc_i0_comp = iu_pc_i0_comp_temp; + assign iu_pc_i1_comp = iu_pc_i1_comp_temp; + assign iu_pc_i0_br_miss = iu_pc_i0_comp_temp & cp2_i0_br_miss_q; + assign iu_pc_i1_br_miss = iu_pc_i1_comp_temp & cp2_i1_br_miss_q; + assign iu_pc_i0_br_pred = iu_pc_i0_comp_temp & cp2_i0_bp_pred_q; + assign iu_pc_i1_br_pred = iu_pc_i1_comp_temp & cp2_i1_bp_pred_q; + assign iu_pc_flush_cnt = flush_cond; + + //----------------------------------------------------------------------------- + // Status Control + //----------------------------------------------------------------------------- + assign iu6_i0_ptr = decode_a(iu6_i0_itag_q[1:`ITAG_SIZE_ENC - 1]); + assign iu6_i1_ptr = decode_a(iu6_i1_itag_q[1:`ITAG_SIZE_ENC - 1]); + + assign cp1_i0_dispatched = iu6_i0_dispatched_q ? iu6_i0_ptr : 0; + assign cp1_i1_dispatched = iu6_i1_dispatched_q ? iu6_i1_ptr : 0; + assign cp1_i0_dispatched_delay_d = {`CPL_Q_DEPTH{~(cp3_flush_q | cp2_flush_q)}} & cp1_i0_dispatched; + assign cp1_i1_dispatched_delay_d = {`CPL_Q_DEPTH{~(cp3_flush_q | cp2_flush_q)}} & cp1_i1_dispatched; + + assign cp0_dispatched = ({`CPL_Q_DEPTH{~cp3_flush_q}} & ((cp1_dispatched_q & (~cp1_completed)) | (cp1_i0_dispatched_delay_q | cp1_i1_dispatched_delay_q))); + + assign exx_executed = lq0_execute_vld | lq1_execute_vld | br_execute_vld | xu_execute_vld | xu1_execute_vld | + axu0_execute_vld | axu1_execute_vld | fold_i0_execute_vld | fold_i1_execute_vld; + + assign cp0_executed = (({`CPL_Q_DEPTH{~cp3_flush_q}}) & ((cp1_executed_q & (~cp1_completed)) | exx_executed)); + + assign cp1_compl_ready = cp1_dispatched_q & cp1_executed_q; + + assign cp1_i0_completed = ({`CPL_Q_DEPTH{~cp2_flush_q & ~cp3_flush_q}} & (cp1_i0_ptr_q & cp1_compl_ready & ~cp1_n_flush_q)); + assign cp1_i0_completed_ror = {cp1_i0_completed[`CPL_Q_DEPTH - 1], cp1_i0_completed[0:`CPL_Q_DEPTH - 2]}; + assign cp1_i01_comp_is_br = (|(cp1_i0_ptr_q & cp1_is_br_q) & |(cp1_i1_ptr_q & cp1_is_br_q)); + assign cp1_i0_comp_is_flush = |(cp1_i0_ptr_q & (cp1_n_flush_q | cp1_np1_flush_q)); + assign cp1_i1_completed = ({`CPL_Q_DEPTH{~cp2_flush_q & ~cp3_flush_q & ~cp1_i01_comp_is_br & ~cp1_i0_comp_is_flush}} & + (cp1_i1_ptr_q & cp1_compl_ready & (~cp1_n_flush_q) & cp1_i0_completed_ror)); + + assign cp1_completed = cp1_i0_completed | cp1_i1_completed | cp1_flushed; + + assign cp1_i0_complete = |(cp1_i0_completed) & ~cp1_async_int_val; + assign cp1_i1_complete = |(cp1_i1_completed) & ~cp1_async_int_val; + + assign cp1_flushed = (cp1_i0_ptr_q | cp1_i0_completed_ror) & cp1_compl_ready & (cp1_n_flush_q | cp1_np1_flush_q); + assign cp1_flush = (|(cp1_flushed) | cp1_async_int_val) & ~cp2_flush_q & ~cp3_flush_q; + + assign cp1_i0_np1_flush = |(cp1_i0_ptr_q & cp1_np1_flush_q) & ~cp1_async_int_val; + assign cp1_i1_np1_flush = |(cp1_i1_ptr_q & cp1_np1_flush_q) & ~cp1_i0_comp_is_flush & ~cp1_async_int_val; + assign cp1_i0_n_np1_flush = |(cp1_i0_ptr_q & cp1_n_np1_flush_q) & ~cp1_async_int_val; + assign cp1_i1_n_np1_flush = |(cp1_i1_ptr_q & cp1_n_np1_flush_q) & ~cp1_i0_comp_is_flush & ~cp1_async_int_val; + assign cp1_i0_bp_pred = |(cp1_i0_ptr_q & cp1_bp_pred_q) & ~cp1_async_int_val; + assign cp1_i1_bp_pred = |(cp1_i1_ptr_q & cp1_bp_pred_q) & ~cp1_i0_comp_is_flush & ~cp1_async_int_val; + assign cp1_i0_br_pred = |(cp1_i0_ptr_q & cp1_br_pred_q) & ~cp1_async_int_val; + assign cp1_i1_br_pred = |(cp1_i1_ptr_q & cp1_br_pred_q) & ~cp1_i0_comp_is_flush & ~cp1_async_int_val; + assign cp1_i0_br_miss = |(cp1_i0_ptr_q & cp1_br_miss_q) & ~cp1_async_int_val; + assign cp1_i1_br_miss = |(cp1_i1_ptr_q & cp1_br_miss_q) & ~cp1_i0_comp_is_flush & ~cp1_async_int_val; + assign cp1_i0_flush2ucode = |(cp1_i0_ptr_q & cp1_flush2ucode_q) & ~cp1_async_int_val; + assign cp1_i0_flush2ucode_type = |(cp1_i0_ptr_q & cp1_flush2ucode_type_q) & ~cp1_async_int_val; + assign cp1_i1_flush2ucode = |(cp1_i1_ptr_q & cp1_flush2ucode_q) & ~cp1_i0_comp_is_flush & ~cp1_async_int_val; + assign cp1_i1_flush2ucode_type = |(cp1_i1_ptr_q & cp1_flush2ucode_type_q) & ~cp1_i0_comp_is_flush & ~cp1_async_int_val; + assign cp1_i0_iu_excvec_val = |(cp1_i0_ptr_q & cp1_dispatched_q & cp1_iu_excvec_val_q) & ~cp2_flush_q & ~cp3_flush_q & ~cp1_async_int_val; + assign cp1_i1_iu_excvec_val = |(cp1_i1_ptr_q & cp1_dispatched_q & cp1_iu_excvec_val_q) & ~cp1_i0_comp_is_flush & ~cp2_flush_q & ~cp3_flush_q & ~cp1_async_int_val; + assign cp1_i0_lq_excvec_val = |(cp1_i0_ptr_q & cp1_dispatched_q & cp1_lq_excvec_val_q) & ~cp2_flush_q & ~cp3_flush_q & ~cp1_async_int_val; + assign cp1_i1_lq_excvec_val = |(cp1_i1_ptr_q & cp1_dispatched_q & cp1_lq_excvec_val_q) & ~cp1_i0_comp_is_flush & ~cp2_flush_q & ~cp3_flush_q & ~cp1_async_int_val; + assign cp1_i0_xu_excvec_val = |(cp1_i0_ptr_q & cp1_dispatched_q & cp1_xu_excvec_val_q) & ~cp2_flush_q & ~cp3_flush_q & ~cp1_async_int_val; + assign cp1_i1_xu_excvec_val = |(cp1_i1_ptr_q & cp1_dispatched_q & cp1_xu_excvec_val_q) & ~cp1_i0_comp_is_flush & ~cp2_flush_q & ~cp3_flush_q & ~cp1_async_int_val; + assign cp1_i0_axu_excvec_val = |(cp1_i0_ptr_q & cp1_dispatched_q & cp1_axu_excvec_val_q) & ~cp2_flush_q & ~cp3_flush_q & ~cp1_async_int_val; + assign cp1_i1_axu_excvec_val = |(cp1_i1_ptr_q & cp1_dispatched_q & cp1_axu_excvec_val_q) & ~cp1_i0_comp_is_flush & ~cp2_flush_q & ~cp3_flush_q & ~cp1_async_int_val; + assign cp1_i0_db_val = |(cp1_i0_ptr_q & cp1_compl_ready) & ~cp2_flush_q & ~cp3_flush_q & ~cp1_async_int_val; + assign cp1_i1_db_val = |(cp1_i1_ptr_q & cp1_compl_ready & cp1_i0_completed_ror) & ~cp1_i0_comp_is_flush & ~cp2_flush_q & ~cp3_flush_q & ~cp1_async_int_val; + assign cp1_i_bta = cp1_br_bta_q; + + +// always @(cp1_i0_ptr_q or cp1_i1_ptr_q or cp1_iu_excvec_q or cp1_lq_excvec_q or cp1_xu_excvec_q or cp1_axu_excvec_q or cp1_db_events_q) + always @(*) + begin: cp1_excvec_proc + + //(* analysis_not_referenced="true" *) + + integer e; + cp1_i0_iu_excvec = 0; + cp1_i1_iu_excvec = 0; + cp1_i0_lq_excvec = 0; + cp1_i1_lq_excvec = 0; + cp1_i0_xu_excvec = 0; + cp1_i1_xu_excvec = 0; + cp1_i0_axu_excvec = 0; + cp1_i1_axu_excvec = 0; + cp1_i0_db_events = 0; + cp1_i1_db_events = 0; + cp1_i0_perf_events = 0; + cp1_i1_perf_events = 0; + + for (e = 0; e < `CPL_Q_DEPTH; e = e + 1) + begin + if (cp1_i0_ptr_q[e] == 1'b1) + begin + cp1_i0_iu_excvec = cp1_iu_excvec_q[e]; + cp1_i0_lq_excvec = cp1_lq_excvec_q[e]; + cp1_i0_xu_excvec = cp1_xu_excvec_q[e]; + cp1_i0_axu_excvec = cp1_axu_excvec_q[e]; + cp1_i0_db_events = cp1_db_events_q[e]; + cp1_i0_perf_events = cp1_perf_events_q[e]; + end + if (cp1_i1_ptr_q[e] == 1'b1) + begin + cp1_i1_iu_excvec = cp1_iu_excvec_q[e]; + cp1_i1_lq_excvec = cp1_lq_excvec_q[e]; + cp1_i1_xu_excvec = cp1_xu_excvec_q[e]; + cp1_i1_axu_excvec = cp1_axu_excvec_q[e]; + cp1_i1_db_events = cp1_db_events_q[e]; + cp1_i1_perf_events = cp1_perf_events_q[e]; + end + end + end + +// The following table is for the cp2_async_hold and cp2_async_open logic +// cp2_i0_complete_q | +// | cp2_i1_complete_q | +// | | in_ucode_i0 | +// | | | ucode_end_i0 | +// | | | | nop_i0 | +// | | | | | in_ucode_i1 | open +// | | | | | | ucode_end_i1 | | hold +// | | | | | | | nop_i1 | | | +// | | | | | | | | | | | +// ------------------------------------------- +// 0 0 - - - - - - | 0 0 +// 1 0 0 - 0 - - - | 1 0 -- new +// 1 0 1 0 - - - - | 0 1 +// 1 0 1 1 - - - - | 1 0 +// 1 0 - - 1 - - - | 0 1 +// 1 1 1 0 - 1 0 - | 0 1 +// 1 1 1 0 - 1 1 - | 1 0 +// 1 1 - - - 0 - 0 | 1 0 -- changed +// 1 1 - - - 0 - 1 | 0 1 -- changed +// 1 1 1 1 - 1 - - | 1 1 + assign cp3_async_hold_d = (cp2_async_hold | (cp3_async_hold_q & ~cp2_open_async)) & ~(iu_flush_cond & ~cp_flush_into_uc_int); + assign cp2_async_hold = (cp2_i0_complete_q & ~cp2_i1_complete_q & (cp2_i0_ucode[0] | cp2_i0_ucode[1]) & ~cp2_i0_ucode[2]) | + (cp2_i0_complete_q & ~cp2_i1_complete_q & cp2_i0_fuse_nop) | + (cp2_i0_complete_q & cp2_i1_complete_q & (cp2_i0_ucode[0] | cp2_i0_ucode[1]) & ~cp2_i0_ucode[2] & (cp2_i1_ucode[0] | cp2_i1_ucode[1]) & ~cp2_i1_ucode[2]) | + (cp2_i0_complete_q & cp2_i1_complete_q & ~(cp2_i1_ucode[0] | cp2_i1_ucode[1]) & cp2_i1_fuse_nop) | + (cp2_i0_complete_q & cp2_i1_complete_q & (cp2_i0_ucode[0] | cp2_i0_ucode[1]) & cp2_i0_ucode[2] & (cp2_i1_ucode[0] | cp2_i1_ucode[1])); + assign cp2_open_async = (cp2_i0_complete_q & ~cp2_i1_complete_q & ~(cp2_i0_ucode[0] | cp2_i0_ucode[1]) & ~cp2_i0_fuse_nop) | + (cp2_i0_complete_q & ~cp2_i1_complete_q & (cp2_i0_ucode[0] | cp2_i0_ucode[1]) & cp2_i0_ucode[2]) | + (cp2_i0_complete_q & cp2_i1_complete_q & (cp2_i0_ucode[0] | cp2_i0_ucode[1]) & ~cp2_i0_ucode[2] & (cp2_i1_ucode[0] | cp2_i1_ucode[1]) & cp2_i1_ucode[2]) | + (cp2_i0_complete_q & cp2_i1_complete_q & ~(cp2_i1_ucode[0] | cp2_i1_ucode[1]) & ~cp2_i1_fuse_nop) | + (cp2_i0_complete_q & cp2_i1_complete_q & (cp2_i0_ucode[0] | cp2_i0_ucode[1]) & cp2_i0_ucode[2] & (cp2_i1_ucode[0] | cp2_i1_ucode[1])); + assign cp1_async_block = (((|(cp1_i0_ptr_q & cp1_dispatched_q & (cp1_async_block_q | cp1_recirc_vld_q))) | (cp2_async_hold | cp3_async_hold_q)) & ~cp2_open_async) | iu_nonspec_q; + assign cp1_async_int = {( {tlb_miss_q, lru_par_err_q, tlb_par_err_q, tlb_multihit_err_q, ierat_pt_fault_q, + ierat_tlb_inelig_q, ierat_lrat_miss_q}), + ({25{~cp1_async_block}} & {cp4_asyn_icmp_needed_q, cp4_asyn_irpt_needed_q, dp_cp_async_flush_q, dp_cp_async_bus_snoop_flush_q, + np1_async_flush_q, pc_iu_stop_q, dbsr_interrupt_q, fex_interrupt_q, external_mchk_q, gmcdbell_interrupt_q, + ude_dbg_event, crit_interrupt_q, wdog_interrupt_q, gwdog_interrupt_q, cdbell_interrupt_q, + gcdbell_interrupt_q, ext_interrupt_q, fit_interrupt_q, gfit_interrupt_q, dec_interrupt_q, + gdec_interrupt_q, dbell_interrupt_q, gdbell_interrupt_q, udec_interrupt_q, perf_interrupt_q})}; + assign cp1_async_int_val = |(cp1_async_int) & ~cp2_flush_q & ~cp3_flush_q & (async_delay_cnt_q == 3'b0) & ~flush_hold; + + assign iu_lq_recirc_val_d = |(cp1_i0_ptr_q & cp1_dispatched_q & cp1_recirc_vld_q); + + //----------------------------------------------------------------------------- + // IFAR/ITAG Tracking + //----------------------------------------------------------------------------- + assign iu_xu_cp2_rfi_d = (cp2_i0_complete_q & cp2_i0_rfi & ~(cp2_db_val & |({cp2_i0_db_events_q[0], cp2_i0_db_events_q[2:18]}))) | + (cp2_i1_complete_q & cp2_i1_rfi & ~(cp2_db_val & |({cp2_i1_db_events_q[0], cp2_i1_db_events_q[2:18]}))); + assign iu_xu_cp2_rfgi_d = (cp2_i0_complete_q & cp2_i0_rfgi & ~(cp2_db_val & |({cp2_i0_db_events_q[0], cp2_i0_db_events_q[2:18]}))) | + (cp2_i1_complete_q & cp2_i1_rfgi & ~(cp2_db_val & |({cp2_i1_db_events_q[0], cp2_i1_db_events_q[2:18]}))); + assign iu_xu_cp2_rfci_d = (cp2_i0_complete_q & cp2_i0_rfci & ~(cp2_db_val & |({cp2_i0_db_events_q[0], cp2_i0_db_events_q[2:18]}))) | + (cp2_i1_complete_q & cp2_i1_rfci & ~(cp2_db_val & |({cp2_i1_db_events_q[0], cp2_i1_db_events_q[2:18]}))); + assign iu_xu_cp2_rfmci_d = (cp2_i0_complete_q & cp2_i0_rfmci & ~(cp2_db_val & |({cp2_i0_db_events_q[0], cp2_i0_db_events_q[2:18]}))) | + (cp2_i1_complete_q & cp2_i1_rfmci & ~(cp2_db_val & |({cp2_i1_db_events_q[0], cp2_i1_db_events_q[2:18]}))); + + assign iu_xu_rfi = iu_xu_cp4_rfi_q; + assign iu_xu_rfgi = iu_xu_cp4_rfgi_q; + assign iu_xu_rfci = iu_xu_cp4_rfci_q; + assign iu_xu_rfmci = iu_xu_cp4_rfmci_q; + + assign cp2_rfi = (cp2_i0_complete_q & cp2_i0_rfi & ~(cp2_db_val & |({cp2_i0_db_events_q[0], cp2_i0_db_events_q[2:18]}))) | + (cp2_i1_complete_q & cp2_i1_rfi & ~(cp2_db_val & |({cp2_i1_db_events_q[0], cp2_i1_db_events_q[2:18]}))) | + (cp2_i0_complete_q & cp2_i0_rfgi & ~(cp2_db_val & |({cp2_i0_db_events_q[0], cp2_i0_db_events_q[2:18]}))) | + (cp2_i1_complete_q & cp2_i1_rfgi & ~(cp2_db_val & |({cp2_i1_db_events_q[0], cp2_i1_db_events_q[2:18]}))) | + (cp2_i0_complete_q & cp2_i0_rfci & ~(cp2_db_val & |({cp2_i0_db_events_q[0], cp2_i0_db_events_q[2:18]}))) | + (cp2_i1_complete_q & cp2_i1_rfci & ~(cp2_db_val & |({cp2_i1_db_events_q[0], cp2_i1_db_events_q[2:18]}))) | + (cp2_i0_complete_q & cp2_i0_rfmci & ~(cp2_db_val & |({cp2_i0_db_events_q[0], cp2_i0_db_events_q[2:18]}))) | + (cp2_i1_complete_q & cp2_i1_rfmci & ~(cp2_db_val & |({cp2_i1_db_events_q[0], cp2_i1_db_events_q[2:18]}))); + + assign cp2_attn = (cp2_i0_complete_q & cp2_i0_attn & ~(cp2_db_val & |({cp2_i0_db_events_q[0], cp2_i0_db_events_q[2:18]}))) | + (cp2_i1_complete_q & cp2_i1_attn & ~(cp2_db_val & |({cp2_i1_db_events_q[0], cp2_i1_db_events_q[2:18]}))); + + assign cp2_sc = (cp2_i0_complete_q & cp2_i0_sc) | + (cp2_i1_complete_q & cp2_i1_sc); + + + + iuq_cpl_table iuq_cpl_table( + // NIA table inputs + .i0_complete(cp2_i0_complete_q), + .i0_bp_pred(cp2_i0_bp_pred_q), + .i0_br_miss(cp2_i0_br_miss_q), + .i0_ucode(cp2_i0_ucode), + .i0_isram(cp2_i0_isram), + .i0_mtiar(cp2_i0_mtiar), + .i0_rollover(cp2_i0_rollover), + .i0_rfi(cp6_rfi_q), + .i0_n_np1_flush(cp2_i0_n_np1_flush_q), + .i1_complete(cp2_i1_complete_q), + .i1_bp_pred(cp2_i1_bp_pred_q), + .i1_br_miss(cp2_i1_br_miss_q), + .i1_ucode(cp2_i1_ucode), + .i1_isram(cp2_i1_isram), + .i1_mtiar(cp2_i1_mtiar), + .i1_rollover(cp2_i1_rollover), + .i1_rfi(tidn), + .i1_n_np1_flush(cp2_i1_n_np1_flush_q), + + // Temp perf + .iu_pc_i0_comp(iu_pc_i0_comp_temp), + .iu_pc_i1_comp(iu_pc_i1_comp_temp), + + .icmp_enable(icmp_enable), + .irpt_enable(irpt_enable), + + // NIA output selectors + .select_i0_p1(select_i0_p1), + .select_i1_p1(select_i1_p1), + .select_i0_bta(select_i0_bta), + .select_i1_bta(select_i1_bta), + .select_i0_bp_bta(select_i0_bp_bta), + .select_i1_bp_bta(select_i1_bp_bta), + .select_ucode_p1(select_ucode_p1), + .select_reset(select_reset), + .select_mtiar(select_mtiar), // only used to gate off the branch mispredict + + // Async list + .cp3_async_int_val(cp3_async_int_val_q), + .cp3_async_int(cp3_async_int_q), + // IU execption list + .cp3_iu_excvec_val(cp3_iu_excvec_val_q), + .cp3_iu_excvec(cp3_iu_excvec_q), + // LQ execption list + .cp3_lq_excvec_val(cp3_lq_excvec_val_q), + .cp3_lq_excvec(cp3_lq_excvec_q), + // XU execption list + .cp3_xu_excvec_val(cp3_xu_excvec_val_q), + .cp3_xu_excvec(cp3_xu_excvec_q), + // AXU execption list + .cp3_axu_excvec_val(cp3_axu_excvec_val_q), + .cp3_axu_excvec(cp3_axu_excvec_q), + // Debug events + .cp3_db_val(cp3_db_val_q), + .cp3_db_events(cp3_db_events_q), + // Instruction info + .cp3_ld(cp3_ld_q), + .cp3_st(cp3_st_q), + .cp3_fp(cp3_fp_q), + .cp3_ap(cp3_ap_q), + .cp3_spv(cp3_spv_q), + .cp3_epid(cp3_epid_q), + .cp3_rfi(cp3_rfi_q), + .cp3_attn(cp3_attn_q), + .cp3_sc(cp3_sc_q), + .cp3_icmp_block(cp3_icmp_block_q), + // Debug interrupt taken + .cp3_asyn_irpt_taken(cp3_asyn_irpt_taken), + .cp3_asyn_irpt_needed(cp3_asyn_irpt_needed), + .cp3_asyn_icmp_taken(cp3_asyn_icmp_taken), + .cp3_asyn_icmp_needed(cp3_asyn_icmp_needed), + .cp3_db_events_masked_reduced(cp3_db_events_masked_reduced), + // Execption output + .cp3_exc_nia(cp3_exc_nia), + .cp3_mchk_disabled(cp3_mchk_disabled), + // SPR bits + .spr_ivpr(spr_ivpr), + .spr_givpr(spr_givpr), + .msr_gs(msr_gs_q), + .msr_me(msr_me_q), + .dbg_int_en(dbg_int_en_q), + .dbcr0_irpt(dbcr0_irpt_q), + .epcr_duvd(epcr_duvd_q), + .epcr_extgs(epcr_extgs_q), + .epcr_dtlbgs(epcr_dtlbgs_q), + .epcr_itlbgs(epcr_itlbgs_q), + .epcr_dsigs(epcr_dsigs_q), + .epcr_isigs(epcr_isigs_q), + .epcr_icm(epcr_icm_q), + .epcr_gicm(epcr_gicm_q), + // Type of exception + .dp_cp_async_flush(cp3_dp_cp_async_flush), + .dp_cp_async_bus_snoop_flush(cp3_dp_cp_async_bus_snoop_flush), + .async_np1_flush(cp3_async_np1), + .async_n_flush(cp3_async_n), + .mm_iu_exception(cp3_mm_iu_exception), + .pc_iu_stop(cp3_pc_stop), + .mc_int(cp3_mc_int), + .g_int(cp3_g_int), + .c_int(cp3_c_int), + .dbell_taken(cp3_dbell_int), + .cdbell_taken(cp3_cdbell_int), + .gdbell_taken(cp3_gdbell_int), + .gcdbell_taken(cp3_gcdbell_int), + .gmcdbell_taken(cp3_gmcdbell_int), + // Update bits to SPR parititon + .dear_update(cp3_dear_update), + .dbsr_update(cp3_dbsr_update), + .eheir_update(cp3_eheir_update), + .cp3_dbsr(cp3_dbsr), + // ESR bits + .esr_update(cp3_esr_update), + .cp3_exc_esr(cp3_exc_esr), + + .cp3_exc_mcsr(cp3_exc_mcsr), + + .cp_mm_itlb_miss(cp_mm_itlb_miss), + .cp_mm_dtlb_miss(cp_mm_dtlb_miss), + .cp_mm_isi(cp_mm_isi), + .cp_mm_dsi(cp_mm_dsi), + .cp_mm_ilrat_miss(cp_mm_ilrat_miss), + .cp_mm_dlrat_miss(cp_mm_dlrat_miss), + .cp_mm_imchk(cp_mm_imchk), + .cp_mm_dmchk(cp_mm_dmchk), + .dis_mm_mchk(dis_mm_mchk) + + ); + + assign cp2_ifar = ({19{~cp2_i0_complete_q | cp2_i0_np1_flush_q}} & cp2_i0_ifar[43:61]) | + ({19{cp2_i0_complete_q & ~cp2_i0_np1_flush_q}} & cp2_i1_ifar[43:61]); + assign cp2_np1_flush = (cp2_i0_complete_q & cp2_i0_np1_flush_q) | + (~cp2_i0_np1_flush_q & cp2_i1_complete_q & cp2_i1_np1_flush_q); + assign cp2_ucode = (~cp2_i0_complete_q & (cp2_i0_ucode[0] | cp2_i0_ucode[1] | cp2_i0_ucode[2])) | + (cp2_i0_complete_q & ~cp2_i1_complete_q & (cp2_i0_ucode[0] | cp2_i0_ucode[1]) & ~cp2_i0_ucode[2]); + + assign cp2_preissue = (cp2_i0_ucode == 3'b010); + + + assign iu_pc_step_done_d = (pc_iu_step_q & cp2_flush_q & ~(cp2_flush2ucode | cp2_ucode | cp2_flush_nonspec)) | + (iu_pc_step_done_q & pc_iu_step_q); + assign cp3_flush_d = cp2_flush_q; + + assign nia_mask = ~msr_cm_noact_q ? {{`EFF_IFAR_ARCH-30{1'b0}}, {30{1'b1}}} : {`EFF_IFAR_ARCH{1'b1}}; + + assign cp4_excvec_val = ((~(cp4_async_np1_q | cp4_async_n_q | cp4_pc_stop_q | cp4_dp_cp_async_flush_q | cp4_dp_cp_async_bus_snoop_flush_q)) & cp4_excvec_val_q); + + assign cp2_nia = ({`EFF_IFAR_ARCH{select_i0_p1}} & (nia_mask & ({cp3_ifor, cp2_i0_ifar} + 1))) | + ({`EFF_IFAR_ARCH{select_i1_p1}} & (nia_mask & ({cp3_ifor, cp2_i1_ifar} + 1))) | + ({`EFF_IFAR_ARCH{select_i0_bta}} & (nia_mask & cp2_i_bta_q)) | + ({`EFF_IFAR_ARCH{select_i1_bta}} & (nia_mask & cp2_i_bta_q)) | + ({`EFF_IFAR_ARCH{select_i0_bp_bta}} & (nia_mask & {cp3_ifor, cp2_i0_bp_bta})) | + ({`EFF_IFAR_ARCH{select_i1_bp_bta}} & (nia_mask & {cp3_ifor, cp2_i1_bp_bta})) | + ({`EFF_IFAR_ARCH{select_ucode_p1}} & (nia_mask & (cp3_nia_q + 1))) | + ({`EFF_IFAR_ARCH{select_reset_q}} & xu_iu_rest_ifar_q) | + ({`EFF_IFAR_ARCH{cp4_excvec_val}} & cp4_exc_nia_q); + + assign cp3_nia_act = (select_i0_p1 | select_i1_p1 | select_i0_bta | select_i1_bta | select_i0_bp_bta | select_i1_bp_bta | select_ucode_p1 | select_reset_q | cp4_excvec_val); + + assign cp3_ifor = cp3_nia_q[62-`EFF_IFAR_ARCH:61-`EFF_IFAR_WIDTH]; + + //----------------------------------------------------------------------------- + // Exception Handler (Work in progress) + //----------------------------------------------------------------------------- + assign cp2_i0_iu_excvec_val = cp2_i0_iu_excvec_val_q & (~(cp2_i0_isram)); + assign cp2_i1_iu_excvec_val = cp2_i1_iu_excvec_val_q & (~(cp2_i1_isram)); + assign cp2_i0_lq_excvec_val = cp2_i0_lq_excvec_val_q & (~(cp2_i0_isram)); + assign cp2_i1_lq_excvec_val = cp2_i1_lq_excvec_val_q & (~(cp2_i1_isram)); + assign cp2_i0_xu_excvec_val = cp2_i0_xu_excvec_val_q & (~(cp2_i0_isram)); + assign cp2_i1_xu_excvec_val = cp2_i1_xu_excvec_val_q & (~(cp2_i1_isram)); + assign cp2_i0_axu_excvec_val = cp2_i0_axu_excvec_val_q & (~(cp2_i0_isram)); + assign cp2_i1_axu_excvec_val = cp2_i1_axu_excvec_val_q & (~(cp2_i1_isram)); + assign cp2_i0_db_events_val = cp2_i0_db_val_q & (~(cp2_i0_isram)); + assign cp2_i1_db_events_val = cp2_i1_db_val_q & (~(cp2_i1_isram)); + assign cp2_i0_exc_val = cp2_i0_iu_excvec_val | cp2_i0_lq_excvec_val | cp2_i0_xu_excvec_val | cp2_i0_axu_excvec_val; + assign cp2_i1_exc_val = cp2_i1_iu_excvec_val | cp2_i1_lq_excvec_val | cp2_i1_xu_excvec_val | cp2_i1_axu_excvec_val; + assign cp2_i0_ram_excvec_val = cp2_i0_iu_excvec_val_q | cp2_i0_lq_excvec_val_q | cp2_i0_xu_excvec_val_q | cp2_i0_axu_excvec_val_q; + + assign cp2_iu_excvec_val = ((cp2_i0_complete_q | (~cp2_i0_complete_q & cp3_flush_d)) & cp2_i0_iu_excvec_val) | + ((cp2_i1_complete_q | (cp2_i0_complete_q & ~select_i0_bta & cp3_flush_d)) & cp2_i1_iu_excvec_val); + assign cp2_iu_excvec = ({4{cp2_i0_iu_excvec_val_q}} & cp2_i0_iu_excvec_q) | + ({4{~cp2_i0_iu_excvec_val_q & cp2_i1_iu_excvec_val_q}} & cp2_i1_iu_excvec_q); + + assign cp2_lq_excvec_val = ((cp2_i0_complete_q | (~cp2_i0_complete_q & cp3_flush_d)) & cp2_i0_lq_excvec_val) | + ((cp2_i1_complete_q | (cp2_i0_complete_q & ~select_i0_bta & cp3_flush_d)) & cp2_i1_lq_excvec_val); + assign cp2_lq_excvec = ({6{cp2_i0_lq_excvec_val_q}} & cp2_i0_lq_excvec_q) | + ({6{~cp2_i0_lq_excvec_val_q & cp2_i1_lq_excvec_val_q}} & cp2_i1_lq_excvec_q); + + assign cp2_xu_excvec_val = ((cp2_i0_complete_q | (~cp2_i0_complete_q & cp3_flush_d)) & cp2_i0_xu_excvec_val) | + ((cp2_i1_complete_q | (cp2_i0_complete_q & ~select_i0_bta & cp3_flush_d)) & cp2_i1_xu_excvec_val); + assign cp2_xu_excvec = ({5{cp2_i0_xu_excvec_val_q}} & cp2_i0_xu_excvec_q) | + ({5{~cp2_i0_xu_excvec_val_q & cp2_i1_xu_excvec_val_q}} & cp2_i1_xu_excvec_q); + + assign cp2_axu_excvec_val = ((cp2_i0_complete_q | (~cp2_i0_complete_q & cp3_flush_d)) & cp2_i0_axu_excvec_val) | + ((cp2_i1_complete_q | (cp2_i0_complete_q & ~select_i0_bta & cp3_flush_d)) & cp2_i1_axu_excvec_val); + assign cp2_axu_excvec = ({4{cp2_i0_axu_excvec_val_q}} & cp2_i0_axu_excvec_q) | + ({4{~cp2_i0_axu_excvec_val_q & cp2_i1_axu_excvec_val_q}} & cp2_i1_axu_excvec_q); + + assign cp2_i0_axu_exception_val = cp2_i0_axu_excvec_val & cp2_i0_complete_q; + assign cp2_i0_axu_exception = cp2_i0_axu_excvec_q; + assign cp2_i1_axu_exception_val = cp2_i1_axu_excvec_val & cp2_i1_complete_q; + assign cp2_i1_axu_exception = cp2_i1_axu_excvec_q; + + assign cp2_db_val = (((cp2_i0_complete_q | (~cp2_i0_complete_q & cp3_flush_d)) & cp2_i0_db_events_val) | + ((cp2_i1_complete_q | (cp2_i0_complete_q & ~select_i0_bta & cp3_flush_d)) & cp2_i1_db_events_val)) & msr_de_q; + assign cp2_db_events = ({19{cp2_i0_db_events_val}} & cp2_i0_db_events_q) | + ({19{cp2_i1_db_events_val}} & cp2_i1_db_events_q); + + // Hold ucode values + assign cp3_ld_save_d = ((cp2_i0_complete_q == 1'b1 & cp2_i1_complete_q == 1'b1 & cp2_i1_ucode[0] == 1'b1 & cp2_i1_ucode[2] == 1'b1)) ? 1'b0 : + ((cp2_i0_complete_q == 1'b1 & cp2_i1_complete_q == 1'b1 & cp2_i1_ucode[1] == 1'b1)) ? cp2_i1_ld : + ((cp2_i0_complete_q == 1'b1 & cp2_i0_ucode[1] == 1'b1)) ? cp2_i0_ld : + ((cp2_i0_complete_q == 1'b1 & cp2_i0_ucode[0] == 1'b1 & cp2_i0_ucode[2] == 1'b1)) ? 1'b0 : + ((cp3_flush_q == 1'b1 & cp_flush_into_uc_int == 1'b0)) ? 1'b0 : + cp3_ld_save_q; + + assign cp3_st_save_d = ((cp2_i0_complete_q == 1'b1 & cp2_i1_complete_q == 1'b1 & cp2_i1_ucode[0] == 1'b1 & cp2_i1_ucode[2] == 1'b1)) ? 1'b0 : + ((cp2_i0_complete_q == 1'b1 & cp2_i1_complete_q == 1'b1 & cp2_i1_ucode[1] == 1'b1)) ? (cp2_i1_st | cp2_i1_type_st) : + ((cp2_i0_complete_q == 1'b1 & cp2_i0_ucode[1] == 1'b1)) ? (cp2_i0_st | cp2_i0_type_st) : + ((cp2_i0_complete_q == 1'b1 & cp2_i0_ucode[0] == 1'b1 & cp2_i0_ucode[2] == 1'b1)) ? 1'b0 : + ((cp3_flush_q == 1'b1 & cp_flush_into_uc_int == 1'b0)) ? 1'b0 : + cp3_st_save_q; + + assign cp3_fp_save_d = ((cp2_i0_complete_q == 1'b1 & cp2_i1_complete_q == 1'b1 & cp2_i1_ucode[0] == 1'b1 & cp2_i1_ucode[2] == 1'b1)) ? 1'b0 : + ((cp2_i0_complete_q == 1'b1 & cp2_i1_complete_q == 1'b1 & cp2_i1_ucode[1] == 1'b1)) ? cp2_i1_type_fp : + ((cp2_i0_complete_q == 1'b1 & cp2_i0_ucode[1] == 1'b1)) ? cp2_i0_type_fp : + ((cp2_i0_complete_q == 1'b1 & cp2_i0_ucode[0] == 1'b1 & cp2_i0_ucode[2] == 1'b1)) ? 1'b0 : + ((cp3_flush_q == 1'b1 & cp_flush_into_uc_int == 1'b0)) ? 1'b0 : + cp3_fp_save_q; + + assign cp3_ap_save_d = ((cp2_i0_complete_q == 1'b1 & cp2_i1_complete_q == 1'b1 & cp2_i1_ucode[0] == 1'b1 & cp2_i1_ucode[2] == 1'b1)) ? 1'b0 : + ((cp2_i0_complete_q == 1'b1 & cp2_i1_complete_q == 1'b1 & cp2_i1_ucode[1] == 1'b1)) ? cp2_i1_type_ap : + ((cp2_i0_complete_q == 1'b1 & cp2_i0_ucode[1] == 1'b1)) ? cp2_i0_type_ap : + ((cp2_i0_complete_q == 1'b1 & cp2_i0_ucode[0] == 1'b1 & cp2_i0_ucode[2] == 1'b1)) ? 1'b0 : + ((cp3_flush_q == 1'b1 & cp_flush_into_uc_int == 1'b0)) ? 1'b0 : + cp3_ap_save_q; + + assign cp3_spv_save_d = ((cp2_i0_complete_q == 1'b1 & cp2_i1_complete_q == 1'b1 & cp2_i1_ucode[0] == 1'b1 & cp2_i1_ucode[2] == 1'b1)) ? 1'b0 : + ((cp2_i0_complete_q == 1'b1 & cp2_i1_complete_q == 1'b1 & cp2_i1_ucode[1] == 1'b1)) ? cp2_i1_type_spv : + ((cp2_i0_complete_q == 1'b1 & cp2_i0_ucode[1] == 1'b1)) ? cp2_i0_type_spv : + ((cp2_i0_complete_q == 1'b1 & cp2_i0_ucode[0] == 1'b1 & cp2_i0_ucode[2] == 1'b1)) ? 1'b0 : + ((cp3_flush_q == 1'b1 & cp_flush_into_uc_int == 1'b0)) ? 1'b0 : + cp3_spv_save_q; + + assign cp3_epid_save_d = ((cp2_i0_complete_q == 1'b1 & cp2_i1_complete_q == 1'b1 & cp2_i1_ucode[0] == 1'b1 & cp2_i1_ucode[2] == 1'b1)) ? 1'b0 : + ((cp2_i0_complete_q == 1'b1 & cp2_i1_complete_q == 1'b1 & cp2_i1_ucode[1] == 1'b1)) ? cp2_i1_epid : + ((cp2_i0_complete_q == 1'b1 & cp2_i0_ucode[1] == 1'b1)) ? cp2_i0_epid : + ((cp2_i0_complete_q == 1'b1 & cp2_i0_ucode[0] == 1'b1 & cp2_i0_ucode[2] == 1'b1)) ? 1'b0 : + ((cp3_flush_q == 1'b1 & cp_flush_into_uc_int == 1'b0)) ? 1'b0 : + cp3_epid_save_q; + + assign cp2_ld = (cp2_i0_exc_val & (cp3_ld_save_q | cp2_i0_ld)) | + ((~cp2_i0_exc_val & cp2_i1_exc_val & cp2_i1_ucode[0]) & cp3_ld_save_q) | + ((~cp2_i0_exc_val & cp2_i1_exc_val & ~cp2_i1_ucode[0]) & cp2_i1_ld); + + assign cp2_st = (cp2_i0_exc_val & (cp3_st_save_q | cp2_i0_st | cp2_i0_type_st)) | + ((~cp2_i0_exc_val & cp2_i1_exc_val & cp2_i1_ucode[0]) & cp3_st_save_q) | + ((~cp2_i0_exc_val & cp2_i1_exc_val & ~cp2_i1_ucode[0]) & (cp2_i1_st | cp2_i1_type_st)); + + assign cp2_fp = (cp2_i0_exc_val & (cp3_fp_save_q | cp2_i0_type_fp)) | + ((~cp2_i0_exc_val & cp2_i1_exc_val & cp2_i1_ucode[0]) & cp3_fp_save_q) | + ((~cp2_i0_exc_val & cp2_i1_exc_val & ~cp2_i1_ucode[0]) & cp2_i1_type_fp); + + assign cp2_ap = (cp2_i0_exc_val & (cp3_ap_save_q | cp2_i0_type_ap)) | + ((~cp2_i0_exc_val & cp2_i1_exc_val & cp2_i1_ucode[0]) & cp3_ap_save_q) | + ((~cp2_i0_exc_val & cp2_i1_exc_val & ~cp2_i1_ucode[0]) & cp2_i1_type_ap); + + assign cp2_spv = (cp2_i0_exc_val & (cp3_spv_save_q | cp2_i0_type_spv)) | + ((~cp2_i0_exc_val & cp2_i1_exc_val & cp2_i1_ucode[0]) & cp3_spv_save_q) | + ((~cp2_i0_exc_val & cp2_i1_exc_val & ~cp2_i1_ucode[0]) & cp2_i1_type_spv); + + assign cp2_epid = (cp2_i0_exc_val & (cp3_epid_save_q | cp2_i0_epid)) | + ((~cp2_i0_exc_val & cp2_i1_exc_val & cp2_i1_ucode[0]) & cp3_epid_save_q) | + ((~cp2_i0_exc_val & cp2_i1_exc_val & ~cp2_i1_ucode[0]) & cp2_i1_epid); + + assign cp2_icmp_block = (cp2_i0_db_events_val & cp2_i0_icmp_block) | (cp2_i1_db_events_val & cp2_i1_icmp_block); + + assign cp2_flush2ucode = ((cp2_i0_flush2ucode_q) | (cp2_i0_complete_q & ~cp2_i0_np1_flush_q & cp2_i1_flush2ucode_q)) & cp2_flush_q; + assign cp2_flush2ucode_type = ((cp2_i0_flush2ucode_type_q) | (cp2_i0_complete_q & ~cp2_i0_np1_flush_q & cp2_i1_flush2ucode_type_q)) & cp2_flush_q; + assign cp2_flush_nonspec = ((cp2_i0_nonspec) | (cp2_i0_complete_q & ~cp2_i0_np1_flush_q & cp2_i1_nonspec)) & cp2_flush_q; + assign cp2_mispredict = (select_i0_bta | select_i1_bta) & (~(select_mtiar)); + + // Async debug interrupt + assign cp4_asyn_irpt_needed_d = (cp4_asyn_irpt_needed_q & dbg_event_en_q & (~(cp3_asyn_irpt_taken))) | cp3_asyn_irpt_needed; + assign cp4_asyn_icmp_needed_d = (cp4_asyn_icmp_needed_q & (~(cp3_asyn_icmp_taken))) | cp3_asyn_icmp_needed; + + // Delayed for table lookups + assign cp3_excvec_val = (cp3_iu_excvec_val_q | cp3_lq_excvec_val_q | cp3_xu_excvec_val_q | + cp3_axu_excvec_val_q | (cp3_db_val_q & cp3_db_events_masked_reduced) | cp3_async_int_val_q) & ~cp3_mchk_disabled; + + // Just or all exceptions here + assign cp3_rfi = cp3_rfi_q; // need to check if we are in the right state someday + + assign flush_hold_d[0] = cp4_excvec_val_q | attn_hold_q; // Need to hold exceptions longer to make sure updates have occured. + assign flush_hold_d[1] = flush_hold_q[0]; // Need to hold exceptions longer to make sure updates have occured. + assign flush_hold = |flush_hold_q; + + assign np1_async_flush_d = (np1_async_flush_q & (~(cp4_async_np1_q))) | xu_iu_np1_async_flush; + + assign pc_iu_stop_d = (pc_iu_stop_q & (~(cp4_pc_stop_q | pc_stop_hold_q))) | (pc_iu_stop & ~pc_stop_hold_q); + assign pc_stop_hold_d = (pc_stop_hold_q & pc_iu_stop) | cp4_pc_stop_q; + + assign dp_cp_async_flush_d = (dp_cp_async_flush_q & (~(cp4_dp_cp_async_flush_q))) | dp_cp_hold_req; + assign dp_cp_async_bus_snoop_flush_d = (dp_cp_async_bus_snoop_flush_q & (~(cp4_dp_cp_async_bus_snoop_flush_q))) | dp_cp_bus_snoop_hold_req; + + assign iu_xu_int = cp4_excvec_val_q & (~(cp4_g_int_q | cp4_c_int_q | cp4_mc_int_q | cp4_async_np1_q | cp4_async_n_q | cp4_pc_stop_q | cp4_dp_cp_async_flush_q | cp4_dp_cp_async_bus_snoop_flush_q)); + assign iu_xu_async_complete = cp4_async_np1_q; + assign iu_mm_hold_ack = cp4_dp_cp_async_flush_q; + assign iu_mm_bus_snoop_hold_ack = cp4_dp_cp_async_bus_snoop_flush_q; + assign iu_xu_gint = cp4_g_int_q; + assign iu_xu_cint = cp4_c_int_q; + assign iu_xu_mcint = cp4_mc_int_q; + assign iu_xu_nia = cp3_nia_q; + assign iu_xu_esr_update = cp4_esr_update_q; + assign iu_xu_esr = cp4_exc_esr_q; + assign iu_xu_mcsr = cp4_exc_mcsr_q; + assign iu_xu_dbsr_update = cp4_dbsr_update_q; + assign iu_xu_dbsr = cp4_dbsr_q; + assign iu_xu_dear_update = cp4_dear_update_q; + assign iu_xu_dear = lq0_eff_addr_q; + assign iu_xu_stop = cp4_pc_stop_q | pc_stop_hold_q; + assign iu_xu_quiesce = ~|cp1_dispatched_q; + assign iu_xu_act = cp4_excvec_val_q | cp4_dbsr_update_q; + assign iu_xu_dbell_taken = cp4_dbell_int_q; + assign iu_xu_cdbell_taken = cp4_cdbell_int_q; + assign iu_xu_gdbell_taken = cp4_gdbell_int_q; + assign iu_xu_gcdbell_taken = cp4_gcdbell_int_q; + assign iu_xu_gmcdbell_taken = cp4_gmcdbell_int_q; + assign iu_xu_instr_cpl = iu_pc_i0_comp_temp | iu_pc_i1_comp_temp; + assign iu_spr_eheir_update = cp4_eheir_update_q; + assign iu_spr_eheir = cp1_br_bta_q[30:61]; + assign iu_pc_step_done = iu_pc_step_done_q; + assign iu_pc_attention_instr = (cp2_i0_complete_q & cp2_i0_attn) | (cp2_i1_complete_q & cp2_i1_attn); + assign iu_pc_err_mchk_disabled = cp4_mchk_disabled_q; + assign attn_hold_d = (cp2_i0_complete_q & cp2_i0_attn) | (cp2_i1_complete_q & cp2_i1_attn) | (attn_hold_q & (~(pc_iu_stop_q))); + + assign async_delay_cnt_d = (cp3_excvec_val == 1'b1 | cp3_rfi_q == 1'b1 | async_delay_cnt_q != 3'b0) ? async_delay_cnt_q + 3'b001 : async_delay_cnt_q; + + `ifdef THREADS1 + assign iu_pc_stop_dbg_event = ext_dbg_stop_q & (cp4_dbsr_update_q | iu_xu_dbsr_ude_int); + `endif + `ifndef THREADS1 + assign iu_pc_stop_dbg_event = {(ext_dbg_stop_q & (cp4_dbsr_update_q | iu_xu_dbsr_ude_int)), + (ext_dbg_stop_other_q & (cp4_dbsr_update_q | iu_xu_dbsr_ude_int))}; + `endif + assign iu_pc_err_debug_event = ext_dbg_act_err_q & (cp4_dbsr_update_q | iu_xu_dbsr_ude_int); + assign ac_an_debug_trigger = ext_dbg_act_ext_q & (cp4_dbsr_update_q | iu_xu_dbsr_ude_int); + assign iu_pc_ram_done = (cp2_i0_complete_q | cp2_i0_ram_excvec_val | (cp2_flush_q & cp2_flush2ucode)) & cp2_i0_isram; + assign iu_pc_ram_interrupt = cp2_i0_ram_excvec_val & ~&cp2_iu_excvec & cp2_i0_isram; + assign iu_pc_ram_unsupported = ((cp2_i0_ram_excvec_val & (&cp2_iu_excvec)) | (cp2_flush_q & cp2_flush2ucode)) & cp2_i0_isram; + + assign cp_async_block = cp3_async_hold_q; + + //----------------------------------------------------------------------------- + // ACT + //----------------------------------------------------------------------------- + assign cp2_complete_act = cp2_i0_complete_q | cp2_i1_complete_q | flush_cond | flush_delay_q[0]; + assign cp2_msr_act = xu_iu_msrovride_enab_q | cp2_complete_act; + + //----------------------------------------------------------------------------- + // Next ITAG to complete + //----------------------------------------------------------------------------- + assign cp_next_itag_d = ~(cp2_flush_q | cp3_flush_q) ? cp2_i0_itag_q : {`ITAG_SIZE_ENC{1'b1}}; // Had to match this time with the flush time for mispredict to a cp_next + assign cp_next_itag = cp_next_itag_q; + + assign iu_lq_i0_completed = cp2_i0_complete_q; + assign iu_lq_i0_completed_itag = cp2_i0_itag_q; + assign iu_lq_i1_completed = cp2_i1_complete_q; + assign iu_lq_i1_completed_itag = cp2_i1_itag_q; + + //----------------------------------------------------------------------------- + // Flush + //----------------------------------------------------------------------------- + assign flush_cond = cp3_flush_q | pc_iu_init_reset_q | cp4_excvec_val_q | cp4_rfi_q | cp5_rfi_q | cp6_rfi_q | cp7_rfi_q | cp8_rfi_q | iu_pc_step_done_q | pc_iu_ram_flush_thread_q | flush_hold; + assign iu_flush_cond = (cp3_flush_q & ~cp3_mispredict_q) | pc_iu_init_reset_q | cp4_excvec_val_q | cp4_rfi_q | cp5_rfi_q | cp6_rfi_q | cp7_rfi_q | cp8_rfi_q | iu_pc_step_done_q | pc_iu_ram_flush_thread_q | flush_hold; + assign iu_flush = iu_flush_cond; + assign cp_flush_into_uc_int = cp3_flush_q & (~(cp3_flush2ucode_q)) & cp3_ucode_q & (~(cp3_preissue_q)); + assign cp_flush_into_uc = cp_flush_into_uc_int; + assign cp_uc_flush_ifar = cp3_ifar_q[43:61]; + assign cp_uc_np1_flush = cp3_np1_flush_q; + assign cp_flush = flush_cond; + assign cp_flush_itag = cp1_i0_itag_q; + assign cp_flush_ifar = ({cp8_rfi_q, cp4_excvec_val_q} == 2'b10) ? cp3_nia_q : + ({cp8_rfi_q, cp4_excvec_val_q} == 2'b00) ? cp3_nia_q : + cp4_exc_nia_q; + assign cp_iu0_flush_2ucode = cp_iu0_flush_2ucode_int; + assign cp_iu0_flush_2ucode_int = cp3_flush2ucode_q & ~(pc_iu_init_reset_q | cp4_excvec_val_q | cp4_rfi_q | cp5_rfi_q | cp6_rfi_q | cp7_rfi_q | cp8_rfi_q | pc_iu_ram_flush_thread_q); + assign cp_iu0_flush_2ucode_type = cp3_flush2ucode_type_q & ~(pc_iu_init_reset_q | cp4_excvec_val_q | cp4_rfi_q | cp5_rfi_q | cp6_rfi_q | cp7_rfi_q | cp8_rfi_q | pc_iu_ram_flush_thread_q); + assign cp_iu0_flush_nonspec = iu_flush_cond & cp3_flush_nonspec_q & ~(pc_iu_init_reset_q | cp4_excvec_val_q | cp4_rfi_q | cp5_rfi_q | cp6_rfi_q | cp7_rfi_q | cp8_rfi_q | pc_iu_ram_flush_thread_q); + + // Have a hole today for a few cycles from rename till when dispatched is set + assign cp_rn_empty = ~|cp1_dispatched_q; + + assign nonspec_release = (nonspec_hit_d | reload_hit_q | ierat_pt_fault_q | ierat_lrat_miss_q | ierat_tlb_inelig_q | + tlb_multihit_err_q | tlb_par_err_q | lru_par_err_q | tlb_miss_q); + + assign iu_nonspec_d = ((iu_flush_cond & cp3_flush_nonspec_q) | (~iu_flush_cond & iu_nonspec_q)) & ~nonspec_release; + assign ierat_pt_fault_d = (mm_iu_ierat_rel_val & mm_iu_ierat_pt_fault) | (ierat_pt_fault_q & ~cp3_mm_iu_exception) ; + assign ierat_lrat_miss_d = (mm_iu_ierat_rel_val & mm_iu_ierat_lrat_miss) | (ierat_lrat_miss_q & ~cp3_mm_iu_exception); + assign ierat_tlb_inelig_d = (mm_iu_ierat_rel_val & mm_iu_ierat_tlb_inelig) | (ierat_tlb_inelig_q & ~cp3_mm_iu_exception); + assign tlb_multihit_err_d = (mm_iu_ierat_rel_val & mm_iu_tlb_multihit_err) | (tlb_multihit_err_q & ~cp3_mm_iu_exception); + assign tlb_par_err_d = (mm_iu_ierat_rel_val & mm_iu_tlb_par_err) | (tlb_par_err_q & ~cp3_mm_iu_exception); + assign lru_par_err_d = (mm_iu_ierat_rel_val & mm_iu_lru_par_err) | (lru_par_err_q & ~cp3_mm_iu_exception); + assign tlb_miss_d = (mm_iu_ierat_rel_val & mm_iu_tlb_miss) | (tlb_miss_q & ~cp3_mm_iu_exception); + assign reload_hit_d = mm_iu_reload_hit; + assign nonspec_hit_d = ic_cp_nonspec_hit; + + assign lq0_execute_vld_d = lq0_iu_execute_vld & ~(cp3_flush_q | cp4_flush_q); + assign lq1_execute_vld_d = lq1_iu_execute_vld & ~(cp3_flush_q | cp4_flush_q); + assign br_execute_vld_d = br_iu_execute_vld & ~(cp3_flush_q | cp4_flush_q); + assign xu_execute_vld_d = xu_iu_execute_vld & ~(cp3_flush_q | cp4_flush_q); + assign xu1_execute_vld_d = xu1_iu_execute_vld & ~(cp3_flush_q | cp4_flush_q); + assign axu0_execute_vld_d = axu0_iu_execute_vld & ~(cp3_flush_q | cp4_flush_q); + assign axu1_execute_vld_d = axu1_iu_execute_vld & ~(cp3_flush_q | cp4_flush_q); + + //----------------------------------------------------------------------------- + // ITAG Decode + //----------------------------------------------------------------------------- + assign lq0_execute_vld = {`CPL_Q_DEPTH{lq0_execute_vld_q}} & decode_a(lq0_itag_q[1:`ITAG_SIZE_ENC - 1]); + assign lq0_recirc_vld = {`CPL_Q_DEPTH{lq0_recirc_val_q}} & decode_a(lq0_itag_q[1:`ITAG_SIZE_ENC - 1]); + assign lq1_execute_vld = {`CPL_Q_DEPTH{lq1_execute_vld_q}} & decode_a(lq1_itag_q[1:`ITAG_SIZE_ENC - 1]); + assign br_execute_vld = {`CPL_Q_DEPTH{br_execute_vld_q}} & decode_a(br_itag_q[1:`ITAG_SIZE_ENC - 1]); + assign xu_execute_vld = {`CPL_Q_DEPTH{xu_execute_vld_q}} & decode_a(xu_itag_q[1:`ITAG_SIZE_ENC - 1]); + assign xu1_execute_vld = {`CPL_Q_DEPTH{xu1_execute_vld_q}} & decode_a(xu1_itag_q[1:`ITAG_SIZE_ENC - 1]); + assign axu0_execute_vld = {`CPL_Q_DEPTH{axu0_execute_vld_q}} & decode_a(axu0_itag_q[1:`ITAG_SIZE_ENC - 1]); + assign axu1_execute_vld = {`CPL_Q_DEPTH{axu1_execute_vld_q}} & decode_a(axu1_itag_q[1:`ITAG_SIZE_ENC - 1]); + assign fold_i0_execute_vld = {`CPL_Q_DEPTH{iu7_i0_is_folded_q}} & cp1_i0_dispatched_delay_q; + assign fold_i1_execute_vld = {`CPL_Q_DEPTH{iu7_i1_is_folded_q}} & cp1_i1_dispatched_delay_q; + + assign excvec_act = lq0_execute_vld_q | lq0_recirc_val_q | lq1_execute_vld_q | br_execute_vld_q | xu_execute_vld_q | + xu1_execute_vld_q | axu0_execute_vld_q | axu1_execute_vld_q | iu6_i0_dispatched_q | iu6_i1_dispatched_q; + + //----------------------------------------------------------------------------- + // Update Fields on Dispatch + //----------------------------------------------------------------------------- + generate + begin : xhdl0 + genvar e; + for (e = 0; e < `CPL_Q_DEPTH ; e = e + 1) + begin : dispatch_update_gen + assign cp0_iu_excvec_val[e] = ({cp1_i0_dispatched[e], cp1_i1_dispatched[e]} == 2'b10) ? iu6_i0_exception_val : + ({cp1_i0_dispatched[e], cp1_i1_dispatched[e]} == 2'b01) ? iu6_i1_exception_val : + cp1_iu_excvec_val_q[e]; + + assign cp0_iu_excvec[e] = ({cp1_i0_dispatched[e], cp1_i1_dispatched[e]} == 2'b10) ? iu6_i0_exception : + ({cp1_i0_dispatched[e], cp1_i1_dispatched[e]} == 2'b01) ? iu6_i1_exception : + cp1_iu_excvec_q[e]; + + assign cp0_async_block[e] = ({cp1_i0_dispatched[e], cp1_i1_dispatched[e]} == 2'b10) ? iu6_i0_async_block_q : + ({cp1_i0_dispatched[e], cp1_i1_dispatched[e]} == 2'b01) ? iu6_i1_async_block_q : + cp1_async_block_q[e]; + + assign cp0_is_br[e] = ({cp1_i0_dispatched[e], cp1_i1_dispatched[e]} == 2'b10) ? iu6_i0_is_br_q : + ({cp1_i0_dispatched[e], cp1_i1_dispatched[e]} == 2'b01) ? iu6_i1_is_br_q : + cp1_is_br_q[e]; + + assign cp0_br_add_chk[e] = ({cp1_i0_dispatched[e], cp1_i1_dispatched[e]} == 2'b10) ? iu6_i0_br_add_chk_q : + ({cp1_i0_dispatched[e], cp1_i1_dispatched[e]} == 2'b01) ? iu6_i1_br_add_chk_q : + cp1_br_add_chk_q[e]; + + assign cp0_bp_pred[e] = ({cp1_i0_dispatched[e], cp1_i1_dispatched[e]} == 2'b10) ? iu6_i0_bp_pred_q : + ({cp1_i0_dispatched[e], cp1_i1_dispatched[e]} == 2'b01) ? iu6_i1_bp_pred_q : + cp1_bp_pred_q[e]; + end + end + endgenerate + + // Debug is special because it is updates on dispatch and completion + // 0 - Unconditional implemented + // 1 - Instruction Complete RTX + // 2 - Branch Taken implemented + // 3 - Interrupt Taken RTX + // 4 - Trap Instruction implemented + // 5:8 - IAC1-4 implemented + // 9:10 - DAC1R, DAC1W implemented + // 11:12- DAC2R, DAC2W implemented + // 13 - Return implemented + // 14:15 - DAC3R, DAC3W implemented + // 16:17- DAC4R, DAC4W implemented + // 18 - Instr Value Comp implemented + assign iu6_i0_db_IAC_IVC_event = iac1_dbg_event[0] | iac2_dbg_event[0] | iac3_dbg_event[0] | iac4_dbg_event[0] | ivc_dbg_event[0]; + assign iu6_i1_db_IAC_IVC_event = iac1_dbg_event[1] | iac2_dbg_event[1] | iac3_dbg_event[1] | iac4_dbg_event[1] | ivc_dbg_event[1]; + + generate + begin : xhdl1 + genvar e; + for (e = 0; e < `CPL_Q_DEPTH; e = e + 1) + begin : db_event_cp_gen + assign cp1_db_IAC_IVC_event[e] = cp1_db_events_q[e][5] | cp1_db_events_q[e][6] | cp1_db_events_q[e][7] | cp1_db_events_q[e][8] | cp1_db_events_q[e][18]; + + assign cp0_db_events[e][0] = 1'b0; + + assign cp0_db_events[e][1] = cp1_i0_dispatched[e] ? (icmp_dbg_event[0] & ~iu6_i0_n_flush & ~iu6_i0_db_IAC_IVC_event) : + cp1_i1_dispatched[e] ? (icmp_dbg_event[1] & ~iu6_i1_n_flush & ~iu6_i1_db_IAC_IVC_event) : + lq0_execute_vld[e] ? (cp1_db_events_q[e][1] & ~lq0_n_flush_q & ~cp1_db_IAC_IVC_event[e]) : + lq1_execute_vld[e] ? (cp1_db_events_q[e][1] & ~lq1_n_flush_q & ~cp1_db_IAC_IVC_event[e]) : + xu_execute_vld[e] ? (cp1_db_events_q[e][1] & ~xu_n_flush_q & ~cp1_db_IAC_IVC_event[e]) : + xu1_execute_vld[e] ? (cp1_db_events_q[e][1] & ~cp1_db_IAC_IVC_event[e]) : + axu0_execute_vld[e] ? (cp1_db_events_q[e][1] & ~axu0_n_flush_q & ~cp1_db_IAC_IVC_event[e]) : + axu1_execute_vld[e] ? (cp1_db_events_q[e][1] & ~axu1_n_flush_q & ~cp1_db_IAC_IVC_event[e]) : + br_execute_vld[e] ? (cp1_db_events_q[e][1] & ~cp1_db_IAC_IVC_event[e] & ~brt_dbg_event) : + cp1_db_events_q[e][1]; + + assign cp0_db_events[e][2] = cp1_i0_dispatched[e] ? 1'b0 : + cp1_i1_dispatched[e] ? 1'b0 : + br_execute_vld[e] ? (brt_dbg_event & ~cp1_db_IAC_IVC_event[e]) : + cp1_db_events_q[e][2]; + + assign cp0_db_events[e][3] = cp1_i0_dispatched[e] ? (iu_irpt_dbg_event[0] & ~iu6_i0_db_IAC_IVC_event) : + cp1_i1_dispatched[e] ? (iu_irpt_dbg_event[1] & ~iu6_i1_db_IAC_IVC_event) : + lq0_execute_vld[e] ? (lq0_irpt_dbg_event & ~cp1_db_IAC_IVC_event[e]) : + lq1_execute_vld[e] ? (lq1_irpt_dbg_event & ~cp1_db_IAC_IVC_event[e]) : + xu_execute_vld[e] ? (xu_irpt_dbg_event & ~cp1_db_IAC_IVC_event[e]) : + axu0_execute_vld[e] ? (axu0_irpt_dbg_event & ~cp1_db_IAC_IVC_event[e]) : + axu1_execute_vld[e] ? (axu1_irpt_dbg_event & ~cp1_db_IAC_IVC_event[e]) : + cp1_db_events_q[e][3]; + + assign cp0_db_events[e][4] = cp1_i0_dispatched[e] ? 1'b0 : + cp1_i1_dispatched[e] ? 1'b0 : + xu_execute_vld[e] ? (trap_dbg_event & ~cp1_db_IAC_IVC_event[e]) : + cp1_db_events_q[e][4]; + + assign cp0_db_events[e][5] = cp1_i0_dispatched[e] ? iac1_dbg_event[0] : + cp1_i1_dispatched[e] ? iac1_dbg_event[1] : + cp1_db_events_q[e][5]; + + assign cp0_db_events[e][6] = cp1_i0_dispatched[e] ? iac2_dbg_event[0] : + cp1_i1_dispatched[e] ? iac2_dbg_event[1] : + cp1_db_events_q[e][6]; + + assign cp0_db_events[e][7] = cp1_i0_dispatched[e] ? iac3_dbg_event[0] : + cp1_i1_dispatched[e] ? iac3_dbg_event[1] : + cp1_db_events_q[e][7]; + + assign cp0_db_events[e][8] = cp1_i0_dispatched[e] ? iac4_dbg_event[0] : + cp1_i1_dispatched[e] ? iac4_dbg_event[1] : + cp1_db_events_q[e][8]; + + assign cp0_db_events[e][9] = cp1_i0_dispatched[e] ? 1'b0 : + cp1_i1_dispatched[e] ? 1'b0 : + lq0_execute_vld[e] ? (dac1r_dbg_event[0] & ~cp1_db_IAC_IVC_event[e]) : + lq1_execute_vld[e] ? (dac1r_dbg_event[1] & ~cp1_db_IAC_IVC_event[e]) : + cp1_db_events_q[e][9]; + + assign cp0_db_events[e][10] = cp1_i0_dispatched[e] ? 1'b0 : + cp1_i1_dispatched[e] ? 1'b0 : + lq0_execute_vld[e] ? (dac1w_dbg_event[0] & ~cp1_db_IAC_IVC_event[e]) : + lq1_execute_vld[e] ? (dac1w_dbg_event[1] & ~cp1_db_IAC_IVC_event[e]) : + cp1_db_events_q[e][10]; + + assign cp0_db_events[e][11] = cp1_i0_dispatched[e] ? 1'b0 : + cp1_i1_dispatched[e] ? 1'b0 : + lq0_execute_vld[e] ? (dac2r_dbg_event[0] & ~cp1_db_IAC_IVC_event[e]) : + lq1_execute_vld[e] ? (dac2r_dbg_event[1] & ~cp1_db_IAC_IVC_event[e]) : + cp1_db_events_q[e][11]; + + assign cp0_db_events[e][12] = cp1_i0_dispatched[e] ? 1'b0 : + cp1_i1_dispatched[e] ? 1'b0 : + lq0_execute_vld[e] ? (dac2w_dbg_event[0] & ~cp1_db_IAC_IVC_event[e]) : + lq1_execute_vld[e] ? (dac2w_dbg_event[1] & ~cp1_db_IAC_IVC_event[e]) : + cp1_db_events_q[e][12]; + + assign cp0_db_events[e][13] = cp1_i0_dispatched[e] ? (rfi_dbg_event[0] & ~iu6_i0_db_IAC_IVC_event) : + cp1_i1_dispatched[e] ? (rfi_dbg_event[1] & ~iu6_i1_db_IAC_IVC_event) : + cp1_db_events_q[e][13]; + + assign cp0_db_events[e][14] = cp1_i0_dispatched[e] ? 1'b0 : + cp1_i1_dispatched[e] ? 1'b0 : + lq0_execute_vld[e] ? (dac3r_dbg_event[0] & ~cp1_db_IAC_IVC_event[e]) : + lq1_execute_vld[e] ? (dac3r_dbg_event[1] & ~cp1_db_IAC_IVC_event[e]) : + cp1_db_events_q[e][14]; + + assign cp0_db_events[e][15] = cp1_i0_dispatched[e] ? 1'b0 : + cp1_i1_dispatched[e] ? 1'b0 : + lq0_execute_vld[e] ? (dac3w_dbg_event[0] & ~cp1_db_IAC_IVC_event[e]) : + lq1_execute_vld[e] ? (dac3w_dbg_event[1] & ~cp1_db_IAC_IVC_event[e]) : + cp1_db_events_q[e][15]; + + assign cp0_db_events[e][16] = cp1_i0_dispatched[e] ? 1'b0 : + cp1_i1_dispatched[e] ? 1'b0 : + lq0_execute_vld[e] ? (dac4r_dbg_event[0] & ~cp1_db_IAC_IVC_event[e]) : + lq1_execute_vld[e] ? (dac4r_dbg_event[1] & ~cp1_db_IAC_IVC_event[e]) : + cp1_db_events_q[e][16]; + + assign cp0_db_events[e][17] = cp1_i0_dispatched[e] ? 1'b0 : + cp1_i1_dispatched[e] ? 1'b0 : + lq0_execute_vld[e] ? (dac4w_dbg_event[0] & ~cp1_db_IAC_IVC_event[e]) : + lq1_execute_vld[e] ? (dac4w_dbg_event[1] & ~cp1_db_IAC_IVC_event[e]) : + cp1_db_events_q[e][17]; + + assign cp0_db_events[e][18] = cp1_i0_dispatched[e] ? ivc_dbg_event[0] : + cp1_i1_dispatched[e] ? ivc_dbg_event[1] : + cp1_db_events_q[e][18]; + end + end + endgenerate + + assign rn_cp_iu6_i0_act = rn_cp_iu6_i0_vld; + assign rn_cp_iu6_i1_act = rn_cp_iu6_i0_vld; + assign iu6_i0_dispatched_d = rn_cp_iu6_i0_vld & ~(cp3_flush_d | cp3_flush_q | cp4_flush_q); + assign iu6_i1_dispatched_d = rn_cp_iu6_i1_vld & ~(cp3_flush_d | cp3_flush_q | cp4_flush_q); + + //----------------------------------------------------------------------------- + // Update Fields on Execution + //----------------------------------------------------------------------------- + generate + begin : xhdl2 + genvar e; + for (e = 0; e < `CPL_Q_DEPTH; e = e + 1) + begin : cp1_executed_update_gen + + assign excvec_act_v[e] = lq0_execute_vld[e] | lq0_recirc_vld[e] | lq1_execute_vld[e] | br_execute_vld[e] | xu_execute_vld[e] | xu1_execute_vld[e] | axu0_execute_vld[e] | axu1_execute_vld[e] | cp1_i0_dispatched[e] | cp1_i1_dispatched[e]; + + assign cp0_lq_excvec_val[e] = lq0_execute_vld[e] ? lq0_exception_val_q : + lq1_execute_vld[e] ? lq1_exception_val_q : + cp1_i0_dispatched[e] ? 1'b0 : + cp1_i1_dispatched[e] ? 1'b0 : + cp1_lq_excvec_val_q[e]; + + assign cp0_lq_excvec[e] = lq0_execute_vld[e] ? lq0_exception_q : + lq1_execute_vld[e] ? lq1_exception_q : + cp1_i0_dispatched[e] ? 6'b0 : + cp1_i1_dispatched[e] ? 6'b0 : + cp1_lq_excvec_q[e]; + + assign cp0_xu_excvec_val[e] = xu_execute_vld[e] ? xu_exception_val_q : + cp1_i0_dispatched[e] ? 1'b0 : + cp1_i1_dispatched[e] ? 1'b0 : + cp1_xu_excvec_val_q[e]; + + assign cp0_xu_excvec[e] = xu_execute_vld[e] ? xu_exception_q : + cp1_i0_dispatched[e] ? 5'b0 : + cp1_i1_dispatched[e] ? 5'b0 : + cp1_xu_excvec_q[e]; + + assign cp0_axu_excvec_val[e] = axu0_execute_vld[e] ? axu0_exception_val_q : + axu1_execute_vld[e] ? axu1_exception_val_q : + cp1_i0_dispatched[e] ? 1'b0 : + cp1_i1_dispatched[e] ? 1'b0 : + cp1_axu_excvec_val_q[e]; + + assign cp0_axu_excvec[e] = axu0_execute_vld[e] ? axu0_exception_q : + axu1_execute_vld[e] ? axu1_exception_q : + cp1_i0_dispatched[e] ? 4'b0 : + cp1_i1_dispatched[e] ? 4'b0 : + cp1_axu_excvec_q[e]; + + assign cp0_n_flush[e] = lq0_execute_vld[e] ? (cp1_n_flush_q[e] | lq0_n_flush_q | (dac_lq0_n_flush & dbg_flush_en)) : + lq1_execute_vld[e] ? (cp1_n_flush_q[e] | lq1_n_flush_q | (dac_lq1_n_flush & dbg_flush_en)) : + br_execute_vld[e] ? (cp1_n_flush_q[e] | (brt_dbg_event & dbg_flush_en)) : + xu_execute_vld[e] ? (cp1_n_flush_q[e] | xu_n_flush_q | (trap_dbg_event & dbg_flush_en)) : + axu0_execute_vld[e] ? (cp1_n_flush_q[e] | axu0_n_flush_q) : + axu1_execute_vld[e] ? (cp1_n_flush_q[e] | axu1_n_flush_q) : + cp1_i0_dispatched[e] ? (iu6_i0_n_flush | iac_i0_n_flush) : + cp1_i1_dispatched[e] ? (iu6_i1_n_flush | iac_i1_n_flush) : + cp1_n_flush_q[e]; + + assign cp0_np1_flush[e] = lq0_execute_vld[e] ? (cp1_np1_flush_q[e] | lq0_np1_flush_q) : + lq1_execute_vld[e] ? (cp1_np1_flush_q[e] | lq1_np1_flush_q) : + br_execute_vld[e] ? (cp1_np1_flush_q[e] | br_redirect_q) : + xu_execute_vld[e] ? (cp1_np1_flush_q[e] | xu_np1_flush_q | xu_mtiar_q) : + axu0_execute_vld[e] ? (cp1_np1_flush_q[e] | axu0_np1_flush_q) : + axu1_execute_vld[e] ? (cp1_np1_flush_q[e] | axu1_np1_flush_q) : + cp1_i0_dispatched[e] ? (iu6_i0_np1_flush | spr_single_issue_q): + cp1_i1_dispatched[e] ? (iu6_i1_np1_flush | spr_single_issue_q): + cp1_np1_flush_q[e]; + + assign cp0_perf_events[e] = lq0_execute_vld[e] ? (cp1_perf_events_q[e] | {(spr_cp_perf_event_mux_ctrls[0:3]===4'b1100), + (spr_cp_perf_event_mux_ctrls[4:7]===4'b1100), + (spr_cp_perf_event_mux_ctrls[8:11]===4'b1100), + (spr_cp_perf_event_mux_ctrls[12:15]===4'b1100)}) : + lq1_execute_vld[e] ? (cp1_perf_events_q[e] | lq1_perf_events_q) : + br_execute_vld[e] ? (cp1_perf_events_q[e] | br_perf_events_q) : + xu_execute_vld[e] ? (cp1_perf_events_q[e] | xu_perf_events_q) : + xu1_execute_vld[e] ? (cp1_perf_events_q[e] | {(spr_cp_perf_event_mux_ctrls[0:3]===4'b1011), + (spr_cp_perf_event_mux_ctrls[4:7]===4'b1011), + (spr_cp_perf_event_mux_ctrls[8:11]===4'b1011), + (spr_cp_perf_event_mux_ctrls[12:15]===4'b1011)}) : + axu0_execute_vld[e] ? (cp1_perf_events_q[e] | axu0_perf_events_q) : + axu1_execute_vld[e] ? (cp1_perf_events_q[e] | axu1_perf_events_q) : + cp1_i0_dispatched[e] ? 4'b0 : + cp1_i1_dispatched[e] ? 4'b0 : + cp1_perf_events_q[e]; + + // This should probably be cleared on a flush so async aren't blocked as long. + assign cp0_n_np1_flush[e] = axu0_execute_vld[e] ? (cp1_n_np1_flush_q[e] | axu0_n_np1_flush_q) : // clear on dispatch + axu1_execute_vld[e] ? (cp1_n_np1_flush_q[e] | axu1_n_np1_flush_q) : + cp1_i0_dispatched[e] ? 1'b0 : + cp1_i1_dispatched[e] ? 1'b0 : + cp1_n_np1_flush_q[e]; + + assign cp0_recirc_vld[e] = cp1_i0_dispatched[e] ? 1'b0 : // clear on dispatch + cp1_i1_dispatched[e] ? 1'b0 : + lq0_recirc_vld[e] ? 1'b1 : + cp1_recirc_vld_q[e]; + + assign cp0_flush2ucode[e] = cp1_i0_dispatched[e] ? 1'b0 : // clear on dispatch + cp1_i1_dispatched[e] ? 1'b0 : + lq0_execute_vld[e] ? lq0_flush2ucode_q : + xu_execute_vld[e] ? xu_flush2ucode_q : + axu0_execute_vld[e] ? axu0_flush2ucode_q : + axu1_execute_vld[e] ? axu1_flush2ucode_q : + cp1_flush2ucode_q[e]; + + assign cp0_flush2ucode_type[e] = cp1_i0_dispatched[e] ? 1'b0 : + cp1_i1_dispatched[e] ? 1'b0 : + lq0_execute_vld[e] ? (lq0_flush2ucode_q & lq0_flush2ucode_type_q) : + axu0_execute_vld[e] ? (axu0_flush2ucode_q & axu0_flush2ucode_type_q) : + axu1_execute_vld[e] ? (axu1_flush2ucode_q & axu1_flush2ucode_type_q) : + cp1_flush2ucode_type_q[e]; + + assign cp0_br_pred[e] = br_execute_vld[e] ? br_taken_q : cp1_br_pred_q[e]; + + assign cp0_br_miss[e] = cp1_i0_dispatched[e] ? 1'b0 : + cp1_i1_dispatched[e] ? 1'b0 : + br_execute_vld[e] ? br_redirect_q : + xu_execute_vld[e] ? xu_mtiar_q : + cp1_br_miss_q[e]; + end + end + endgenerate + + + //----------------------------------------------------------------------------- + // BTA calculations + //----------------------------------------------------------------------------- + tri_agecmp #(.SIZE(`ITAG_SIZE_ENC)) br_xu_cmp( + .a(xu_itag_q), + .b(br_itag_q), + .a_newer_b(br_older_xu) + ); + + tri_agecmp #(.SIZE(`ITAG_SIZE_ENC)) br_lq_cmp( + .a(lq0_itag_q), + .b(br_itag_q), + .a_newer_b(br_older_lq) + ); + + tri_agecmp #(.SIZE(`ITAG_SIZE_ENC)) br_save_cmp( + .a(cp1_br_bta_itag_q), + .b(br_itag_q), + .a_newer_b(br_older_save) + ); + + tri_agecmp #(.SIZE(`ITAG_SIZE_ENC)) xu_lq_cmp( + .a(lq0_itag_q), + .b(xu_itag_q), + .a_newer_b(xu_older_lq) + ); + + tri_agecmp #(.SIZE(`ITAG_SIZE_ENC)) xu_save_cmp( + .a(cp1_br_bta_itag_q), + .b(xu_itag_q), + .a_newer_b(xu_older_save) + ); + + tri_agecmp #(.SIZE(`ITAG_SIZE_ENC)) lq_save_cmp( + .a(cp1_br_bta_itag_q), + .b(lq0_itag_q), + .a_newer_b(lq_older_save) + ); + + + + assign cp0_br_bta_act = br_redirect_q | xu_mtiar_q | xu_exception_val_q | lq0_exception_val_q | eheir_val | cp1_br_bta_v_q; + +//table_start +// +//?TABLE SAVE_TABLE LISTING(final) OPTIMIZE PARMS(ON-SET,DC-SET); +//*INPUTS*=================================*OUTPUTS*=============* +//| | | +//| br_redirect_q | | +//| | xu_mtiar_q | | +//| | | xu_exception_val_q | | +//| | | | lq0_exception_val_q | | +//| | | | | cp1_br_bta_v_q | | +//| | | | | | | | +//| | | | | | br_older_xu | | +//| | | | | | | br_older_lq | select_br | +//| | | | | | | | br_older_save | | select_xu | +//| | | | | | | | | xu_older_lq | | | select_lq | +//| | | | | | | | | | xu_older_save | | | | | +//| | | | | | | | | | | lq_older_save | | | | | +//| | | | | | | | | | | | | | | | | +//| | | | | | | | | | | | | | | | | +//| | | | | | | | | | | | | | | | | +//| | | | | | | | | | | | | | | | | +//| | | | | | | | | | | | | | | | | +//*TYPE*===================================+=====================+ +//| P P P P P P P P P P P | S S S | +//*TERMS*==================================+=====================+ +//| 0 0 0 0 0 - - - - - - | 0 0 0 | # No Valid +//| 1 0 0 0 0 - - - - - - | 1 0 0 | # Single Valid - BR +//| 0 P P 0 0 - - - - - - | 0 1 0 | # Single Valid - XU +//| 0 0 0 1 0 - - - - - - | 0 0 1 | # Single Valid - LQ +//| 0 0 0 0 1 - - - - - - | 0 0 0 | # Single Valid - SAVE +//| 1 P P 0 0 1 - - - - - | 1 0 0 | # Double Valid - BR,XU +//| 1 P P 0 0 0 - - - - - | 0 1 0 | # Double Valid - BR,XU +//| 1 0 0 1 0 - 1 - - - - | 1 0 0 | # Double Valid - BR,LQ +//| 1 0 0 1 0 - 0 - - - - | 0 0 1 | # Double Valid - BR,LQ +//| 1 0 0 0 1 - - 1 - - - | 1 0 0 | # Double Valid - BR,SAVE +//| 1 0 0 0 1 - - 0 - - - | 0 0 0 | # Double Valid - BR,SAVE +//| 0 P P 1 0 - - - 1 - - | 1 0 0 | # Double Valid - XU,LQ +//| 0 P P 1 0 - - - 0 - - | 0 0 1 | # Double Valid - XU,LQ +//| 0 P P 0 1 - - - - 1 - | 0 1 0 | # Double Valid - XU,SAVE +//| 0 P P 0 1 - - - - 0 - | 0 0 0 | # Double Valid - XU,SAVE +//| 0 0 0 1 1 - - - - - 1 | 0 0 1 | # Double Valid - LQ,SAVE +//| 0 0 0 1 1 - - - - - 0 | 0 0 0 | # Double Valid - LQ,SAVE +//| 1 P P 1 0 - 0 - 0 - - | 0 0 1 | # Triple Valid - BR,XU,LQ - LQ +//| 1 P P 1 0 0 - - 1 - - | 0 1 0 | # Triple Valid - BR,XU,LQ - XU +//| 1 P P 1 0 1 1 - - - - | 1 0 0 | # Triple Valid - BR,XU,LQ - BR +//| 1 P P 0 1 - - 0 - 0 - | 0 0 0 | # Triple Valid - BR,XU,SAVE - SAVE +//| 1 P P 0 1 0 - - - 1 - | 0 1 0 | # Triple Valid - BR,XU,SAVE - XU +//| 1 P P 0 1 1 - 1 - - - | 1 0 0 | # Triple Valid - BR,XU,SAVE - BR +//| 1 0 0 1 1 - - 0 - - 0 | 0 0 0 | # Triple Valid - BR,LQ,SAVE - SAVE +//| 1 0 0 1 1 - 0 - - - 1 | 0 0 1 | # Triple Valid - BR,LQ,SAVE - LQ +//| 1 0 0 1 1 - 1 1 - - - | 1 0 0 | # Triple Valid - BR,LQ,SAVE - BR +//| 0 P P 1 1 - - - - 0 0 | 0 0 0 | # Triple Valid - XU,LQ,SAVE - SAVE +//| 0 P P 1 1 - - - 0 - 1 | 0 0 1 | # Triple Valid - XU,LQ,SAVE - LQ +//| 0 P P 1 1 - - - 1 1 - | 0 1 0 | # Triple Valid - XU,LQ,SAVE - XU +//| 1 P P 1 1 1 1 1 - - - | 1 0 0 | # Quad Valid - BR +//| 1 P P 1 1 0 - - 1 1 - | 0 1 0 | # Quad Valid - XU +//| 1 P P 1 1 - 0 - 0 - 1 | 0 0 1 | # Quad Valid - LQ +//| 1 P P 1 1 - - 0 - 0 0 | 0 0 0 | # Quad Valid - SAVE +//*END*====================================+=====================+ +//?TABLE END SAVE_TABLE ; +//table_end + +//assign_start + +assign save_table_pt[1] = + (({ br_redirect_q , xu_mtiar_q , + br_older_xu , xu_older_lq , + xu_older_save }) === 5'b11011); +assign save_table_pt[2] = + (({ br_redirect_q , xu_exception_val_q , + br_older_xu , xu_older_lq , + xu_older_save }) === 5'b11011); +assign save_table_pt[3] = + (({ xu_mtiar_q , xu_exception_val_q , + lq0_exception_val_q , br_older_lq , + lq_older_save }) === 5'b00101); +assign save_table_pt[4] = + (({ br_redirect_q , xu_mtiar_q , + xu_exception_val_q , br_older_lq , + br_older_save }) === 5'b10011); +assign save_table_pt[5] = + (({ lq0_exception_val_q , br_older_lq , + xu_older_lq , lq_older_save + }) === 4'b1001); +assign save_table_pt[6] = + (({ br_redirect_q , br_older_xu , + br_older_lq , br_older_save + }) === 4'b1111); +assign save_table_pt[7] = + (({ br_redirect_q , xu_mtiar_q , + xu_exception_val_q , lq0_exception_val_q , + lq_older_save }) === 5'b00011); +assign save_table_pt[8] = + (({ br_redirect_q , xu_mtiar_q , + xu_exception_val_q , lq0_exception_val_q , + br_older_save }) === 5'b10001); +assign save_table_pt[9] = + (({ br_redirect_q , lq0_exception_val_q , + xu_older_lq , lq_older_save + }) === 4'b0101); +assign save_table_pt[10] = + (({ br_redirect_q , lq0_exception_val_q , + br_older_xu , br_older_save + }) === 4'b1011); +assign save_table_pt[11] = + (({ br_redirect_q , xu_exception_val_q , + cp1_br_bta_v_q , xu_older_lq , + xu_older_save }) === 5'b01111); +assign save_table_pt[12] = + (({ br_redirect_q , xu_mtiar_q , + cp1_br_bta_v_q , xu_older_lq , + xu_older_save }) === 5'b01111); +assign save_table_pt[13] = + (({ xu_exception_val_q , lq0_exception_val_q , + br_older_xu , xu_older_save + }) === 4'b1001); +assign save_table_pt[14] = + (({ xu_mtiar_q , lq0_exception_val_q , + br_older_xu , xu_older_save + }) === 4'b1001); +assign save_table_pt[15] = + (({ xu_mtiar_q , xu_exception_val_q , + lq0_exception_val_q , cp1_br_bta_v_q , + br_older_lq }) === 5'b00100); +assign save_table_pt[16] = + (({ br_redirect_q , xu_mtiar_q , + xu_exception_val_q , cp1_br_bta_v_q , + br_older_lq }) === 5'b10001); +assign save_table_pt[17] = + (({ lq0_exception_val_q , cp1_br_bta_v_q , + br_older_lq , xu_older_lq + }) === 4'b1000); +assign save_table_pt[18] = + (({ br_redirect_q , cp1_br_bta_v_q , + br_older_xu , br_older_lq + }) === 4'b1011); +assign save_table_pt[19] = + (({ br_redirect_q , xu_exception_val_q , + cp1_br_bta_v_q , br_older_xu , + xu_older_lq }) === 5'b11001); +assign save_table_pt[20] = + (({ br_redirect_q , xu_mtiar_q , + cp1_br_bta_v_q , br_older_xu , + xu_older_lq }) === 5'b11001); +assign save_table_pt[21] = + (({ br_redirect_q , xu_exception_val_q , + lq0_exception_val_q , xu_older_save + }) === 4'b0101); +assign save_table_pt[22] = + (({ br_redirect_q , xu_mtiar_q , + lq0_exception_val_q , xu_older_save + }) === 4'b0101); +assign save_table_pt[23] = + (({ br_redirect_q , xu_mtiar_q , + xu_exception_val_q , lq0_exception_val_q , + cp1_br_bta_v_q }) === 5'b00010); +assign save_table_pt[24] = + (({ br_redirect_q , xu_mtiar_q , + xu_exception_val_q , lq0_exception_val_q , + cp1_br_bta_v_q }) === 5'b10000); +assign save_table_pt[25] = + (({ br_redirect_q , lq0_exception_val_q , + cp1_br_bta_v_q , xu_older_lq + }) === 4'b0100); +assign save_table_pt[26] = + (({ br_redirect_q , xu_exception_val_q , + lq0_exception_val_q , cp1_br_bta_v_q , + xu_older_lq }) === 5'b01101); +assign save_table_pt[27] = + (({ br_redirect_q , xu_mtiar_q , + lq0_exception_val_q , cp1_br_bta_v_q , + xu_older_lq }) === 5'b01101); +assign save_table_pt[28] = + (({ br_redirect_q , lq0_exception_val_q , + cp1_br_bta_v_q , br_older_xu + }) === 4'b1001); +assign save_table_pt[29] = + (({ xu_exception_val_q , lq0_exception_val_q , + cp1_br_bta_v_q , br_older_xu + }) === 4'b1000); +assign save_table_pt[30] = + (({ xu_mtiar_q , lq0_exception_val_q , + cp1_br_bta_v_q , br_older_xu + }) === 4'b1000); +assign save_table_pt[31] = + (({ br_redirect_q , xu_exception_val_q , + lq0_exception_val_q , cp1_br_bta_v_q + }) === 4'b0100); +assign save_table_pt[32] = + (({ br_redirect_q , xu_mtiar_q , + lq0_exception_val_q , cp1_br_bta_v_q + }) === 4'b0100); +assign select_br = + (save_table_pt[4] | save_table_pt[6] + | save_table_pt[8] | save_table_pt[10] + | save_table_pt[16] | save_table_pt[18] + | save_table_pt[24] | save_table_pt[26] + | save_table_pt[27] | save_table_pt[28] + ); +assign select_xu = + (save_table_pt[1] | save_table_pt[2] + | save_table_pt[11] | save_table_pt[12] + | save_table_pt[13] | save_table_pt[14] + | save_table_pt[19] | save_table_pt[20] + | save_table_pt[21] | save_table_pt[22] + | save_table_pt[29] | save_table_pt[30] + | save_table_pt[31] | save_table_pt[32] + ); +assign select_lq = + (save_table_pt[3] | save_table_pt[5] + | save_table_pt[7] | save_table_pt[9] + | save_table_pt[15] | save_table_pt[17] + | save_table_pt[23] | save_table_pt[25] + ); + +//assign_end + + // EHEIR instruction value is passed in the bta field to conserve resources + always @(*) + begin: bta_proc + cp0_br_bta_v = cp1_br_bta_v_q; + cp0_br_bta_itag_tmp = cp1_br_bta_itag_q; + cp0_br_bta_tmp = cp1_br_bta_q; + + if (flush_delay_q[1] == 1'b1) // This flush must match the flush the units see + cp0_br_bta_v = 1'b0; + else + begin + if(select_br == 1'b1) + begin + cp0_br_bta_v = 1'b1; + cp0_br_bta_itag_tmp = br_itag_q; + cp0_br_bta_tmp = br_bta_q; + end + if(select_xu == 1'b1) + begin + cp0_br_bta_v = 1'b1; + cp0_br_bta_itag_tmp = xu_itag_q; + cp0_br_bta_tmp = xu_bta_q; + end + if(select_lq == 1'b1) + begin + cp0_br_bta_v = 1'b1; + cp0_br_bta_itag_tmp = lq0_itag_q; + cp0_br_bta_tmp[30:61] = lq0_instr_q; + end + end + end + + assign eheir_val_d = (( ( (rn_cp_iu6_i0_is_rfci | rn_cp_iu6_i0_is_rfmci ) | + (rn_cp_iu6_i1_is_rfci | rn_cp_iu6_i1_is_rfmci ) ) & + xu_iu_msr_gs ) | (eheir_val_q & ~flush_delay_q[1])); + + // this will come on once for a single cycle and not come on again until the flush occurs. + // since this is looking at dispatch, the first one is the oldest one. + assign eheir_val = eheir_val_d & ~ eheir_val_q; + + + assign eheir_instr = ((rn_cp_iu6_i0_is_rfci | rn_cp_iu6_i0_is_rfmci ) & xu_iu_msr_gs ) ? rn_cp_iu6_i0_instr : rn_cp_iu6_i1_instr; + assign eheir_itag = ((rn_cp_iu6_i0_is_rfci | rn_cp_iu6_i0_is_rfmci ) & xu_iu_msr_gs ) ? rn_cp_iu6_i0_itag : rn_cp_iu6_i1_itag; + + // this logic works on the notion that instuctions seen at dispatch will always + // be older than ones which update on a completion report. Therefore I will only + // update the bta from iu if it has not already been updated from the other sources, + // br, xu, lq. + assign cp0_br_bta[62-`EFF_IFAR_ARCH:29] = cp0_br_bta_tmp[62-`EFF_IFAR_ARCH:29]; + assign cp0_br_bta[30:61] = (cp0_br_bta_v == 1'b0) ? eheir_instr : cp0_br_bta_tmp[30:61]; + assign cp0_br_bta_itag = (cp0_br_bta_v == 1'b0) ? { 1'b0, eheir_itag } : cp0_br_bta_itag_tmp; + + + + //----------------------------------------------------------------------------- + // ITAG Incrementers + //----------------------------------------------------------------------------- + iuq_cpl_itag #(.SIZE(`ITAG_SIZE_ENC), .WRAP(`CPL_Q_DEPTH - 1)) cp1_i0_itag_inc( + .inc({cp1_i0_complete, cp1_i1_complete}), + .i(cp1_i0_itag_q), + .o(cp0_i0_itag) + ); + + iuq_cpl_itag #(.SIZE(`ITAG_SIZE_ENC), .WRAP(`CPL_Q_DEPTH - 1)) cp1_i1_itag_inc( + .inc({cp1_i0_complete, cp1_i1_complete}), + .i(cp1_i1_itag_q), + .o(cp0_i1_itag) + ); + + // Added for timing + + assign cp0_i0_ptr = ({cp1_i0_complete, cp1_i1_complete} == 2'b10) ? {cp1_i0_ptr_q[`CPL_Q_DEPTH - 1], cp1_i0_ptr_q[0:`CPL_Q_DEPTH - 2]} : + ({cp1_i0_complete, cp1_i1_complete} == 2'b11) ? {cp1_i0_ptr_q[`CPL_Q_DEPTH - 2:`CPL_Q_DEPTH - 1], cp1_i0_ptr_q[0:`CPL_Q_DEPTH - 3]} : + cp1_i0_ptr_q; + + assign cp0_i1_ptr = ({cp1_i0_complete, cp1_i1_complete} == 2'b10) ? {cp1_i1_ptr_q[`CPL_Q_DEPTH - 1], cp1_i1_ptr_q[0:`CPL_Q_DEPTH - 2]} : + ({cp1_i0_complete, cp1_i1_complete} == 2'b11) ? {cp1_i1_ptr_q[`CPL_Q_DEPTH - 2:`CPL_Q_DEPTH - 1], cp1_i1_ptr_q[0:`CPL_Q_DEPTH - 3]} : + cp1_i1_ptr_q; + + //----------------------------------------------------------------------------- + // IAC Compare + //----------------------------------------------------------------------------- + // Debug Enables + assign iu6_ifar[0] = {cp3_nia_q[62 - `EFF_IFAR_ARCH:61 - `EFF_IFAR_WIDTH], iu6_i0_ifar_q}; + assign iu6_ifar[1] = {cp3_nia_q[62 - `EFF_IFAR_ARCH:61 - `EFF_IFAR_WIDTH], iu6_i1_ifar_q}; + + generate + begin : xhdl3 + genvar e; + for (e = 0; e < `EFF_IFAR_ARCH; e = e + 1) + begin : iac_mask_gen + assign iac2_mask[e] = spr_iac2_q[e] | (~(dbcr1_iac12m_q)); + assign iac4_mask[e] = spr_iac4_q[e] | (~(dbcr1_iac34m_q)); + end + end + endgenerate + + generate + begin : xhdl4 + genvar t; + for (t = 0; t <= 1; t = t + 1) + begin : ifar_cmp + if (`EFF_IFAR_ARCH > 32) // ui=62-eff_ifar + begin : iac_cmprh_gen0 + assign iac1_cmprh[t] = &((iu6_ifar[t][62-`EFF_IFAR_ARCH:31] ~^ spr_iac1_q[62-`EFF_IFAR_ARCH:31]) | (~iac2_mask[62-`EFF_IFAR_ARCH:31])); + assign iac2_cmprh[t] = &(iu6_ifar[t][62-`EFF_IFAR_ARCH:31] ~^ spr_iac2_q[62-`EFF_IFAR_ARCH:31]); + assign iac3_cmprh[t] = &((iu6_ifar[t][62-`EFF_IFAR_ARCH:31] ~^ spr_iac3_q[62-`EFF_IFAR_ARCH:31]) | (~iac4_mask[62-`EFF_IFAR_ARCH:31])); + assign iac4_cmprh[t] = &(iu6_ifar[t][62-`EFF_IFAR_ARCH:31] ~^ spr_iac4_q[62-`EFF_IFAR_ARCH:31]); + assign iac1_cmprl[t] = &((iu6_ifar[t][32:61] ~^ spr_iac1_q[32:61]) | (~iac2_mask[32:61])); + assign iac2_cmprl[t] = &(iu6_ifar[t][32:61] ~^ spr_iac2_q[32:61]); + assign iac3_cmprl[t] = &((iu6_ifar[t][32:61] ~^ spr_iac3_q[32:61]) | (~iac4_mask[32:61])); + assign iac4_cmprl[t] = &(iu6_ifar[t][32:61] ~^ spr_iac4_q[32:61]); + assign iac1_cmpr[t] = iac1_cmprl[t] & (iac1_cmprh[t] | ~msr_cm_q); + assign iac2_cmpr[t] = iac2_cmprl[t] & (iac2_cmprh[t] | ~msr_cm_q); + assign iac3_cmpr[t] = iac3_cmprl[t] & (iac3_cmprh[t] | ~msr_cm_q); + assign iac4_cmpr[t] = iac4_cmprl[t] & (iac4_cmprh[t] | ~msr_cm_q); + end + + if (`EFF_IFAR_ARCH <= 32) // ui=62-eff_ifar + begin : iac_cmprh_gen1 + assign iac1_cmprl[t] = &((iu6_ifar[t][62-`EFF_IFAR_ARCH:61] ~^ spr_iac1_q[62-`EFF_IFAR_ARCH:61]) | (~iac2_mask[62-`EFF_IFAR_ARCH:61])); + assign iac2_cmprl[t] = &(iu6_ifar[t][62-`EFF_IFAR_ARCH:61] ~^ spr_iac2_q[62-`EFF_IFAR_ARCH:61]); + assign iac3_cmprl[t] = &((iu6_ifar[t][62-`EFF_IFAR_ARCH:61] ~^ spr_iac3_q[62-`EFF_IFAR_ARCH:61]) | (~iac4_mask[62-`EFF_IFAR_ARCH:61])); + assign iac4_cmprl[t] = &(iu6_ifar[t][62-`EFF_IFAR_ARCH:61] ~^ spr_iac4_q[62-`EFF_IFAR_ARCH:61]); + assign iac1_cmpr[t] = iac1_cmprl[t]; + assign iac2_cmpr[t] = iac2_cmprl[t]; + assign iac3_cmpr[t] = iac3_cmprl[t]; + assign iac4_cmpr[t] = iac4_cmprl[t]; + end + + assign iac1_cmpr_sel[t] = (iac1_cmpr[t] & iac1_en_q); + assign iac2_cmpr_sel[t] = (dbcr1_iac12m_q == 1'b0) ? (iac2_cmpr[t] & iac2_en_q) : + (iac1_cmpr[t] & iac2_en_q); + assign iac3_cmpr_sel[t] = (iac3_cmpr[t] & iac3_en_q); + assign iac4_cmpr_sel[t] = (dbcr1_iac34m_q == 1'b0) ? (iac4_cmpr[t] & iac4_en_q) : + (iac3_cmpr[t] & iac4_en_q); + end + end + endgenerate + + assign ivc_cmpr_sel[0] = iu6_i0_match_q & dbcr3_ivc_q; + assign ivc_cmpr_sel[1] = iu6_i1_match_q & dbcr3_ivc_q; + + assign ext_dbg_stop_d = dbcr0_edm_q & ((pc_iu_dbg_action_q == 3'b010) | (pc_iu_dbg_action_q == 3'b011) | (pc_iu_dbg_action_q == 3'b110) | (pc_iu_dbg_action_q == 3'b111)); + assign ext_dbg_stop_other_d = dbcr0_edm_q & ((pc_iu_dbg_action_q == 3'b011) | (pc_iu_dbg_action_q == 3'b111)); + assign ext_dbg_act_err_d = dbcr0_edm_q & (pc_iu_dbg_action_q == 3'b100); + assign ext_dbg_act_ext_d = dbcr0_edm_q & ((pc_iu_dbg_action_q == 3'b101) | (pc_iu_dbg_action_q == 3'b110) | (pc_iu_dbg_action_q == 3'b111)); + assign iu6_dbg_flush_en[0] = dbg_flush_en & (~(iu6_i0_is_sc_q | iu6_i0_is_sc_hyp_q | iu6_i0_is_ehpriv_q | iu6_i0_is_attn_q)); + assign iu6_dbg_flush_en[1] = dbg_flush_en & (~(iu6_i1_is_sc_q | iu6_i1_is_sc_hyp_q | iu6_i1_is_ehpriv_q | iu6_i1_is_attn_q)); + assign dbg_event_en_d = (~(epcr_duvd_q & (~msr_gs_q) & (~msr_pr_q))); + assign dbg_int_en_d = msr_de_q & dbcr0_idm_q & (~ext_dbg_stop_q); // shouldn't stop be replaced with edm + assign dbg_flush_en = (msr_de_q & dbcr0_idm_q) | ext_dbg_stop_q; + + assign iu6_uc_hold_rollover_d = (iu6_uc_hold_rollover_q | (iu6_i0_rollover_q & iu6_i0_ucode_q == 3'b010) | (iu6_i1_rollover_q & iu6_i1_ucode_q == 3'b010)) & + (~(cp3_flush_q & (~(cp_flush_into_uc_int)))); + + assign ret_sel[0] = (iu6_i0_is_rfi_q | iu6_i0_is_rfgi_q) & dbcr0_ret_q; + assign ret_sel[1] = (iu6_i1_is_rfi_q | iu6_i1_is_rfgi_q) & dbcr0_ret_q; + + assign ude_dbg_event = (msr_de_q & dbcr0_idm_q & dbg_event_en_q & uncond_dbg_event_q); + assign iu_xu_dbsr_ude_int = ((~msr_de_q | ~dbcr0_idm_q) & dbg_event_en_q & uncond_dbg_event_q); + assign iu_xu_dbsr_ude = iu_xu_dbsr_ude_int; + assign iu_xu_dbsr_ide = (~msr_de_q & dbg_event_en_q & uncond_dbg_event_q); + assign icmp_dbg_event[0] = (msr_de_q & dbg_event_en_q & dbcr0_icmp_q & (iu6_i0_ucode_q == 3'b000 | iu6_i0_ucode_q == 3'b101)); + assign icmp_dbg_event[1] = (msr_de_q & dbg_event_en_q & dbcr0_icmp_q & (iu6_i1_ucode_q == 3'b000 | iu6_i1_ucode_q == 3'b101)); + assign iac1_dbg_event[0] = (dbg_event_en_q & iac1_cmpr_sel[0] & (iu6_i0_ucode_q == 3'b000 | iu6_i0_ucode_q == 3'b010)); + assign iac1_dbg_event[1] = (dbg_event_en_q & iac1_cmpr_sel[1] & (iu6_i1_ucode_q == 3'b000 | iu6_i1_ucode_q == 3'b010)); + assign iac2_dbg_event[0] = (dbg_event_en_q & iac2_cmpr_sel[0] & (iu6_i0_ucode_q == 3'b000 | iu6_i0_ucode_q == 3'b010)); + assign iac2_dbg_event[1] = (dbg_event_en_q & iac2_cmpr_sel[1] & (iu6_i1_ucode_q == 3'b000 | iu6_i1_ucode_q == 3'b010)); + assign iac3_dbg_event[0] = (dbg_event_en_q & iac3_cmpr_sel[0] & (iu6_i0_ucode_q == 3'b000 | iu6_i0_ucode_q == 3'b010)); + assign iac3_dbg_event[1] = (dbg_event_en_q & iac3_cmpr_sel[1] & (iu6_i1_ucode_q == 3'b000 | iu6_i1_ucode_q == 3'b010)); + assign iac4_dbg_event[0] = (dbg_event_en_q & iac4_cmpr_sel[0] & (iu6_i0_ucode_q == 3'b000 | iu6_i0_ucode_q == 3'b010)); + assign iac4_dbg_event[1] = (dbg_event_en_q & iac4_cmpr_sel[1] & (iu6_i1_ucode_q == 3'b000 | iu6_i1_ucode_q == 3'b010)); + assign dac1r_dbg_event[0] = (dbg_event_en_q & lq0_dacrw_q[0] & dacr_dbg_event[0]); + assign dac1r_dbg_event[1] = (dbg_event_en_q & lq1_dacrw_q[0] & dacr_dbg_event[1]); + assign dac1w_dbg_event[0] = (dbg_event_en_q & lq0_dacrw_q[0] & ~dacr_dbg_event[0]); + assign dac1w_dbg_event[1] = (dbg_event_en_q & lq1_dacrw_q[0] & ~dacr_dbg_event[1]); + assign dac2r_dbg_event[0] = (dbg_event_en_q & lq0_dacrw_q[1] & dacr_dbg_event[0]); + assign dac2r_dbg_event[1] = (dbg_event_en_q & lq1_dacrw_q[1] & dacr_dbg_event[1]); + assign dac2w_dbg_event[0] = (dbg_event_en_q & lq0_dacrw_q[1] & ~dacr_dbg_event[0]); + assign dac2w_dbg_event[1] = (dbg_event_en_q & lq1_dacrw_q[1] & ~dacr_dbg_event[1]); + assign dac3r_dbg_event[0] = (dbg_event_en_q & lq0_dacrw_q[2] & dacr_dbg_event[0]); + assign dac3r_dbg_event[1] = (dbg_event_en_q & lq1_dacrw_q[2] & dacr_dbg_event[1]); + assign dac3w_dbg_event[0] = (dbg_event_en_q & lq0_dacrw_q[2] & ~dacr_dbg_event[0]); + assign dac3w_dbg_event[1] = (dbg_event_en_q & lq1_dacrw_q[2] & ~dacr_dbg_event[1]); + assign dac4r_dbg_event[0] = (dbg_event_en_q & lq0_dacrw_q[3] & dacr_dbg_event[0]); + assign dac4r_dbg_event[1] = (dbg_event_en_q & lq1_dacrw_q[3] & dacr_dbg_event[1]); + assign dac4w_dbg_event[0] = (dbg_event_en_q & lq0_dacrw_q[3] & ~dacr_dbg_event[0]); + assign dac4w_dbg_event[1] = (dbg_event_en_q & lq1_dacrw_q[3] & ~dacr_dbg_event[1]); + assign dacr_dbg_event[0] = (dbg_event_en_q & lq0_dacr_type_q); + assign dacr_dbg_event[1] = (dbg_event_en_q & lq1_dacr_type_q); + assign rfi_dbg_event[0] = (dbg_event_en_q & ret_sel[0] & (iu6_i0_ucode_q == 3'b000 | iu6_i0_ucode_q == 3'b010)); + assign rfi_dbg_event[1] = (dbg_event_en_q & ret_sel[1] & (iu6_i1_ucode_q == 3'b000 | iu6_i1_ucode_q == 3'b010)); + assign ivc_dbg_event[0] = (dbg_event_en_q & ivc_cmpr_sel[0] & (iu6_i0_ucode_q == 3'b000 | iu6_i0_ucode_q == 3'b010)); + assign ivc_dbg_event[1] = (dbg_event_en_q & ivc_cmpr_sel[1] & (iu6_i1_ucode_q == 3'b000 | iu6_i1_ucode_q == 3'b010)); + assign trap_dbg_event = dbg_event_en_q & (xu_exception_val_q & xu_exception_q == 5'b01110) & dbcr0_trap_q; + assign iu_irpt_dbg_event[0] = (dbg_event_en_q & iu6_i0_exception_val & dbcr0_irpt_q); + assign iu_irpt_dbg_event[1] = (dbg_event_en_q & iu6_i1_exception_val & dbcr0_irpt_q); + assign xu_irpt_dbg_event = (dbg_event_en_q & xu_exception_val_q & dbcr0_irpt_q); + assign axu0_irpt_dbg_event = (dbg_event_en_q & axu0_exception_val_q & dbcr0_irpt_q); + assign axu1_irpt_dbg_event = (dbg_event_en_q & axu1_exception_val_q & dbcr0_irpt_q); + assign lq0_irpt_dbg_event = (dbg_event_en_q & lq0_exception_val_q & dbcr0_irpt_q); + assign lq1_irpt_dbg_event = (dbg_event_en_q & lq1_exception_val_q & dbcr0_irpt_q); + assign brt_dbg_event = msr_de_q & dbg_event_en_q & (br_execute_vld_q & br_taken_q) & dbcr0_brt_q; + assign iac_i0_n_flush = (iac1_dbg_event[0] | iac2_dbg_event[0] | iac3_dbg_event[0] | iac4_dbg_event[0] | ivc_dbg_event[0]) & dbg_flush_en; + assign iac_i1_n_flush = (iac1_dbg_event[1] | iac2_dbg_event[1] | iac3_dbg_event[1] | iac4_dbg_event[1] | ivc_dbg_event[1]) & dbg_flush_en; + assign dac_lq0_n_flush = dac1r_dbg_event[0] | dac1w_dbg_event[0] | dac2r_dbg_event[0] | dac2w_dbg_event[0] | + dac3r_dbg_event[0] | dac3w_dbg_event[0] | dac4r_dbg_event[0] | dac4w_dbg_event[0]; + assign dac_lq1_n_flush = dac1r_dbg_event[1] | dac1w_dbg_event[1] | dac2r_dbg_event[1] | dac2w_dbg_event[1] | + dac3r_dbg_event[1] | dac3w_dbg_event[1] | dac4r_dbg_event[1] | dac4w_dbg_event[1]; + assign icmp_enable = dbg_event_en_q & dbcr0_icmp_q; + assign irpt_enable = dbg_event_en_q & dbcr0_irpt_q; + + assign iu7_i0_is_folded_d = iu6_i0_is_folded_q | iac_i0_n_flush; + assign iu7_i1_is_folded_d = iu6_i1_is_folded_q | iac_i1_n_flush; + + //----------------------------------------------------------------------------- + // IU ERROR Calculations and Folded ops + //----------------------------------------------------------------------------- + //Machine Check I-ERAT Parity Error N iu_err = "101" 0 + //Machine Check I-Side L2 ECC error N iu_err = "010" 1 + //Machine Check IERAT Multi-hit Error N iu_err = "110" 2 + //Debug Instruction Address Compare Event N iu_cp_eff_match 3 + //Debug Instruction Value Compare Event Yes N iu_cp_value_match 4 + //Instruction TLB ERAT Miss N iu_err = "111" 5 + //Instruction Storage Execution Access Violation N iu_err = "100" 6 + //Priviledge N 7 removed + //Hyper Priviledge N 8 removed + //System Call System Call NP1 sc 9 + //System Call System Call Hypervisor NP1 sc_hyp 10 + //Program Unimplemented Op N valop = '0' 11 + //Program Unimplemented SC N sc_ill 12 + + + always @(*) + begin: iu6_i0_exec_proc + iu6_i0_exception_val = 1'b0; + iu6_i0_exception = 4'b0000; + iu6_i0_n_flush = (iu6_dbg_flush_en[0] & (iac1_dbg_event[0] | iac2_dbg_event[0] | iac3_dbg_event[0] | iac4_dbg_event[0] | ivc_dbg_event[0] | rfi_dbg_event[0])) & (~(iu6_i0_isram_q)); + iu6_i0_np1_flush = (((iu6_dbg_flush_en[0] & dbcr0_icmp_q) | ((xu_iu_single_instr_q | pc_iu_step_q) & ~iu6_i0_fuse_nop_q)) & (iu6_i0_ucode_q == 3'b000 | iu6_i0_ucode_q == 3'b101)) | + (iu6_i0_rollover_q & (~(iu6_i0_ucode_q == 3'b010 | iu6_i0_ucode_q == 3'b100))) | + (iu6_uc_hold_rollover_q & iu6_i0_ucode_q == 3'b101) | + iu6_i0_is_np1_flush_q; + + if (iu6_i0_error_q == 3'b101) + begin + iu6_i0_exception_val = 1'b1; + iu6_i0_exception = 4'b0000; + iu6_i0_n_flush = 1'b1; + end + else if (iu6_i0_error_q == 3'b010) + begin + iu6_i0_exception_val = 1'b1; + iu6_i0_exception = 4'b0001; + iu6_i0_n_flush = 1'b1; + end + else if (iu6_i0_error_q == 3'b110) + begin + iu6_i0_exception_val = 1'b1; + iu6_i0_exception = 4'b0010; + iu6_i0_n_flush = 1'b1; + end + else if (iu6_i0_error_q == 3'b111 & ccr2_mmu_mode_q == 1'b1 & iu6_i0_isram_q == 1'b0) + begin + iu6_i0_exception_val = 1'b1; + iu6_i0_exception = 4'b0101; + iu6_i0_n_flush = 1'b1; + end + else if (iu6_i0_error_q == 3'b111 & ccr2_mmu_mode_q == 1'b0 & iu_nonspec_q == 1'b1 & iu6_i0_isram_q == 1'b0) + begin + iu6_i0_exception_val = 1'b1; + iu6_i0_exception = 4'b0101; + iu6_i0_n_flush = 1'b1; + end + else if (iu6_i0_error_q == 3'b111 & ccr2_mmu_mode_q == 1'b0 & iu_nonspec_q == 1'b0 & iu6_i0_isram_q == 1'b0) + begin + iu6_i0_exception_val = 1'b0; + iu6_i0_exception = 4'b0000; + iu6_i0_n_flush = 1'b1; + end + else if (iu6_i0_error_q == 3'b111 & iu6_i0_isram_q == 1'b1) + begin + iu6_i0_exception_val = 1'b1; + iu6_i0_exception = 4'b1111; + iu6_i0_n_flush = 1'b1; + end + else if (iu6_i0_error_q == 3'b100) + begin + iu6_i0_exception_val = 1'b1; + iu6_i0_exception = 4'b0110; + iu6_i0_n_flush = 1'b1; + end + else if ((iu6_i0_is_rfi_q == 1'b1 | iu6_i0_is_rfci_q == 1'b1 | iu6_i0_is_rfmci_q == 1'b1 | iu6_i0_is_rfgi_q == 1'b1) & msr_pr_q == 1'b1) + begin + iu6_i0_exception_val = 1'b1; + iu6_i0_exception = 4'b0111; + iu6_i0_n_flush = 1'b1; + end + else if ((iu6_i0_is_rfci_q == 1'b1 | iu6_i0_is_rfmci_q == 1'b1) & msr_gs_q == 1'b1) + begin + iu6_i0_exception_val = 1'b1; + iu6_i0_exception = 4'b1000; + iu6_i0_n_flush = 1'b1; + end + else + if (iu6_i0_is_sc_q == 1'b1) + begin + iu6_i0_exception_val = 1'b1; + iu6_i0_exception = 4'b1001; + iu6_i0_np1_flush = 1'b1; + end + else if (iu6_i0_is_sc_hyp_q == 1'b1) + begin + iu6_i0_exception_val = 1'b1; + iu6_i0_exception = 4'b1010; + iu6_i0_np1_flush = 1'b1; + end + else if (iu6_i0_ucode_q[1] == 1'b1 & ccr2_ucode_dis_q == 1'b1) + begin + iu6_i0_exception_val = 1'b1; + iu6_i0_exception = 4'b1011; + iu6_i0_n_flush = 1'b1; + end + else if (iu6_i0_is_sc_ill_q == 1'b1 | iu6_i0_is_dcr_ill_q == 1'b1) + begin + iu6_i0_exception_val = 1'b1; + iu6_i0_exception = 4'b1100; + iu6_i0_n_flush = 1'b1; + end + else if (iu6_i0_is_isync_q == 1'b1) + iu6_i0_np1_flush = 1'b1; + else if (iu6_i0_is_rfi_q == 1'b1 | iu6_i0_is_rfci_q == 1'b1 | iu6_i0_is_rfmci_q == 1'b1 | iu6_i0_is_rfgi_q == 1'b1) + iu6_i0_np1_flush = 1'b1; + else if (iu6_i0_valop_q == 1'b0) + begin + iu6_i0_exception_val = 1'b1; + iu6_i0_exception = 4'b1100; + iu6_i0_n_flush = 1'b1; + end + end + + always @(*) + begin: iu6_i1_exec_proc + iu6_i1_exception_val = 1'b0; + iu6_i1_exception = 4'b0000; + iu6_i1_n_flush = (iu6_dbg_flush_en[1] & (iac1_dbg_event[1] | iac2_dbg_event[1] | iac3_dbg_event[1] | iac4_dbg_event[1] | ivc_dbg_event[1] | rfi_dbg_event[1])) & (~(iu6_i1_isram_q)); + iu6_i1_np1_flush = (((iu6_dbg_flush_en[1] & dbcr0_icmp_q) | ((xu_iu_single_instr_q | pc_iu_step_q) & ~iu6_i1_fuse_nop_q)) & (iu6_i1_ucode_q == 3'b000 | iu6_i1_ucode_q == 3'b101)) | + (iu6_i1_rollover_q & (~(iu6_i1_ucode_q == 3'b010 | iu6_i1_ucode_q == 3'b100))) | + (iu6_uc_hold_rollover_q & iu6_i1_ucode_q == 3'b101) | + iu6_i1_is_np1_flush_q; + + if (iu6_i1_error_q == 3'b101) + begin + iu6_i1_exception_val = 1'b1; + iu6_i1_exception = 4'b0000; + iu6_i1_n_flush = 1'b1; + end + else if (iu6_i1_error_q == 3'b010) + begin + iu6_i1_exception_val = 1'b1; + iu6_i1_exception = 4'b0001; + iu6_i1_n_flush = 1'b1; + end + else if (iu6_i1_error_q == 3'b110) + begin + iu6_i1_exception_val = 1'b1; + iu6_i1_exception = 4'b0010; + iu6_i1_n_flush = 1'b1; + end + else if (iu6_i1_error_q == 3'b111 & ccr2_mmu_mode_q == 1'b1 & iu6_i1_isram_q == 1'b0) + begin + iu6_i1_exception_val = 1'b1; + iu6_i1_exception = 4'b0101; + iu6_i1_n_flush = 1'b1; + end + else if (iu6_i1_error_q == 3'b111 & ccr2_mmu_mode_q == 1'b0 & iu6_i1_isram_q == 1'b0) + begin + iu6_i1_exception_val = 1'b0; + iu6_i1_exception = 4'b0000; + iu6_i1_n_flush = 1'b1; + end + else if (iu6_i1_error_q == 3'b111 & iu6_i1_isram_q == 1'b1) + begin + iu6_i1_exception_val = 1'b1; + iu6_i1_exception = 4'b1111; + iu6_i1_n_flush = 1'b1; + end + else if (iu6_i1_error_q == 3'b100) + begin + iu6_i1_exception_val = 1'b1; + iu6_i1_exception = 4'b0110; + iu6_i1_n_flush = 1'b1; + end + else if ((iu6_i1_is_rfi_q == 1'b1 | iu6_i1_is_rfci_q == 1'b1 | iu6_i1_is_rfmci_q == 1'b1 | iu6_i1_is_rfgi_q == 1'b1) & msr_pr_q == 1'b1) + begin + iu6_i1_exception_val = 1'b1; + iu6_i1_exception = 4'b0111; + iu6_i1_n_flush = 1'b1; + end + else if ((iu6_i1_is_rfci_q == 1'b1 | iu6_i1_is_rfmci_q == 1'b1) & msr_gs_q == 1'b1) + begin + iu6_i1_exception_val = 1'b1; + iu6_i1_exception = 4'b1000; + iu6_i1_n_flush = 1'b1; + end + else + if (iu6_i1_is_sc_q == 1'b1) + begin + iu6_i1_exception_val = 1'b1; + iu6_i1_exception = 4'b1001; + iu6_i1_np1_flush = 1'b1; + end + else if (iu6_i1_is_sc_hyp_q == 1'b1) + begin + iu6_i1_exception_val = 1'b1; + iu6_i1_exception = 4'b1010; + iu6_i1_np1_flush = 1'b1; + end + else if (iu6_i1_ucode_q[1] == 1'b1 & ccr2_ucode_dis_q == 1'b1) + begin + iu6_i1_exception_val = 1'b1; + iu6_i1_exception = 4'b1011; + iu6_i1_n_flush = 1'b1; + end + else if (iu6_i1_is_sc_ill_q == 1'b1 | iu6_i1_is_dcr_ill_q == 1'b1) + begin + iu6_i1_exception_val = 1'b1; + iu6_i1_exception = 4'b1100; + iu6_i1_n_flush = 1'b1; + end + else if (iu6_i1_is_isync_q == 1'b1) + iu6_i1_np1_flush = 1'b1; + else if (iu6_i1_is_rfi_q == 1'b1 | iu6_i1_is_rfci_q == 1'b1 | iu6_i1_is_rfmci_q == 1'b1 | iu6_i1_is_rfgi_q == 1'b1) + iu6_i1_np1_flush = 1'b1; + else if (iu6_i1_valop_q == 1'b0) + begin + iu6_i1_exception_val = 1'b1; + iu6_i1_exception = 4'b1100; + iu6_i1_n_flush = 1'b1; + end + end + + // Create the cp_mm_exept_taken bus which tells mmu info on the exception taken + assign cp_mm_except_taken_d[0] = (cp_mm_dtlb_miss | cp_mm_dsi | cp_mm_dlrat_miss | cp_mm_dmchk | cp_mm_itlb_miss | cp_mm_isi | cp_mm_ilrat_miss | cp_mm_imchk); + assign cp_mm_except_taken_d[1] = (cp_mm_dtlb_miss | cp_mm_dsi | cp_mm_dlrat_miss | cp_mm_dmchk); + assign cp_mm_except_taken_d[2] = (cp_mm_itlb_miss | cp_mm_dtlb_miss); + assign cp_mm_except_taken_d[3] = (cp_mm_isi | cp_mm_dsi); + assign cp_mm_except_taken_d[4] = (cp_mm_ilrat_miss | cp_mm_dlrat_miss); + assign cp_mm_except_taken_d[5] = (cp_mm_imchk | cp_mm_dmchk); + + + assign cp_mm_except_taken = cp_mm_except_taken_q; + + //----------------------------------------------------------------------------- + // I0 Assignments + //----------------------------------------------------------------------------- + assign iu_lq_recirc_val = iu_lq_recirc_val_q; + assign cp2_i0_completed = cp2_i0_complete_q; + assign cp2_i1_completed = cp2_i1_complete_q; + assign cp2_i0_bp_pred = cp2_i0_bp_pred_q; + assign cp2_i1_bp_pred = cp2_i1_bp_pred_q; + assign cp2_i0_br_pred = cp2_i0_br_pred_q; + assign cp2_i1_br_pred = cp2_i1_br_pred_q; + assign cp2_i0_bta = ({`EFF_IFAR_WIDTH{~select_i0_bta}} & cp2_i0_bp_bta) | + ({`EFF_IFAR_WIDTH{select_i0_bta}} & cp2_i_bta_q[62 - `EFF_IFAR_WIDTH:61]); + assign cp2_i1_bta = ({`EFF_IFAR_WIDTH{~select_i1_bta}} & cp2_i1_bp_bta) | + ({`EFF_IFAR_WIDTH{select_i1_bta}} & cp2_i_bta_q[62 - `EFF_IFAR_WIDTH:61]); + assign cp0_i0_completed_itag = cp0_i0_itag[1:`ITAG_SIZE_ENC - 1]; + assign cp0_i1_completed_itag = cp0_i1_itag[1:`ITAG_SIZE_ENC - 1]; + + assign dis_mm_mchk = ((~xu_iu_xucr4_mmu_mchk_q) & (~ccr2_mmu_mode_q)); + + + //----------------------------------------------- + // performance events + //----------------------------------------------- + assign cp_events_en = (pc_iu_event_count_mode[0] & xu_iu_msr_pr ) | //problem state + (pc_iu_event_count_mode[1] & ~xu_iu_msr_pr & xu_iu_msr_gs) | //guest supervisor state + (pc_iu_event_count_mode[2] & ~xu_iu_msr_pr & ~xu_iu_msr_gs) ; //hypervisor state + + // events are set here + // Question: Should I be gating the speculative events based on pc_iu_event_count_mode? If they are already being + // gated in the units, then it should not be needed. + assign cp_events_in = ({1'b0, cp2_i0_perf_events_q, 11'b00000000000} & {16{cp_events_en}}); + + // we are discussing how to handle the i1 events. Right now I think we are going to have + // a second 4 bits per thread which will be added to the corresponding bit of the main event bus + // to count events which can happen two per cycle. + + + + + tri_event_mux1t #(.EVENTS_IN(16), .EVENTS_OUT(4)) iuq_cp_perf( + .vd(vdd), + .gd(gnd), + .select_bits(spr_cp_perf_event_mux_ctrls), + .unit_events_in(cp_events_in[1:15]), + .event_bus_in(event_bus_in), + .event_bus_out(event_bus_out_d) + ); + + assign event_bus_out = event_bus_out_q; + + + //----------------------------------------------- + // Latch Instances + //----------------------------------------------- + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC-1), .INIT(0), .NEEDS_SRESET(1)) iu6_i0_itag_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[iu6_i0_itag_offset:iu6_i0_itag_offset + `ITAG_SIZE_ENC - 2]), + .scout(sov[iu6_i0_itag_offset:iu6_i0_itag_offset + `ITAG_SIZE_ENC - 2]), + .din(rn_cp_iu6_i0_itag), + .dout(iu6_i0_itag_q) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC-1), .INIT(1), .NEEDS_SRESET(1)) iu6_i1_itag_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[iu6_i1_itag_offset:iu6_i1_itag_offset + `ITAG_SIZE_ENC - 2]), + .scout(sov[iu6_i1_itag_offset:iu6_i1_itag_offset + `ITAG_SIZE_ENC - 2]), + .din(rn_cp_iu6_i1_itag), + .dout(iu6_i1_itag_q) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) cp1_i0_itag_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp1_i0_complete), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp1_i0_itag_offset:cp1_i0_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[cp1_i0_itag_offset:cp1_i0_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(cp0_i0_itag), + .dout(cp1_i0_itag_q) + ); + + tri_rlmreg_p #(.WIDTH(1), .INIT(1), .NEEDS_SRESET(1)) cp1_i0_ptr0_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp1_i0_complete), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp1_i0_ptr_offset:cp1_i0_ptr_offset]), + .scout(sov[cp1_i0_ptr_offset:cp1_i0_ptr_offset]), + .din(cp0_i0_ptr[0:0]), + .dout(cp1_i0_ptr_q[0:0]) + ); + + tri_rlmreg_p #(.WIDTH((`CPL_Q_DEPTH - 1)), .INIT(0), .NEEDS_SRESET(1)) cp1_i0_ptr1_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp1_i0_complete), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp1_i0_ptr_offset + 1:cp1_i0_ptr_offset + `CPL_Q_DEPTH - 1]), + .scout(sov[cp1_i0_ptr_offset + 1:cp1_i0_ptr_offset + `CPL_Q_DEPTH - 1]), + .din(cp0_i0_ptr[1:`CPL_Q_DEPTH - 1]), + .dout(cp1_i0_ptr_q[1:`CPL_Q_DEPTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) cp2_i0_itag_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp2_i0_complete_q), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp2_i0_itag_offset:cp2_i0_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[cp2_i0_itag_offset:cp2_i0_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(cp1_i0_itag_q), + .dout(cp2_i0_itag_q) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(1), .NEEDS_SRESET(1)) cp1_i1_itag_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp1_i0_complete), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp1_i1_itag_offset:cp1_i1_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[cp1_i1_itag_offset:cp1_i1_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(cp0_i1_itag), + .dout(cp1_i1_itag_q) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(1), .NEEDS_SRESET(1)) cp1_i1_ptr0_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp1_i0_complete), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp1_i1_ptr_offset:cp1_i1_ptr_offset + 1]), + .scout(sov[cp1_i1_ptr_offset:cp1_i1_ptr_offset + 1]), + .din(cp0_i1_ptr[0:1]), + .dout(cp1_i1_ptr_q[0:1]) + ); + + tri_rlmreg_p #(.WIDTH((`CPL_Q_DEPTH - 2)), .INIT(0), .NEEDS_SRESET(1)) cp1_i1_ptr1_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp1_i0_complete), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp1_i1_ptr_offset + 2:cp1_i1_ptr_offset + `CPL_Q_DEPTH - 1]), + .scout(sov[cp1_i1_ptr_offset + 2:cp1_i1_ptr_offset + `CPL_Q_DEPTH - 1]), + .din(cp0_i1_ptr[2:`CPL_Q_DEPTH - 1]), + .dout(cp1_i1_ptr_q[2:`CPL_Q_DEPTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(1), .NEEDS_SRESET(1)) cp2_i1_itag_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp2_i0_complete_q), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp2_i1_itag_offset:cp2_i1_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[cp2_i1_itag_offset:cp2_i1_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(cp1_i1_itag_q), + .dout(cp2_i1_itag_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_async_int_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .force_t(func_slp_sl_force), + .scin(siv[cp2_async_int_val_offset]), + .scout(sov[cp2_async_int_val_offset]), + .din(cp1_async_int_val), + .dout(cp2_async_int_val_q) + ); + + tri_rlmreg_p #(.WIDTH(32), .INIT(1), .NEEDS_SRESET(1)) cp2_async_int_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp1_async_int_val), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .force_t(func_slp_sl_force), + .scin(siv[cp2_async_int_offset:cp2_async_int_offset + 32 - 1]), + .scout(sov[cp2_async_int_offset:cp2_async_int_offset + 32 - 1]), + .din(cp1_async_int), + .dout(cp2_async_int_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i0_completed_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp2_i0_completed_offset]), + .scout(sov[cp2_i0_completed_offset]), + .din(cp1_i0_complete), + .dout(cp2_i0_complete_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i1_completed_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp2_i1_completed_offset]), + .scout(sov[cp2_i1_completed_offset]), + .din(cp1_i1_complete), + .dout(cp2_i1_complete_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i0_np1_flush_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp2_i0_np1_flush_offset]), + .scout(sov[cp2_i0_np1_flush_offset]), + .din(cp1_i0_np1_flush), + .dout(cp2_i0_np1_flush_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i1_np1_flush_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp2_i1_np1_flush_offset]), + .scout(sov[cp2_i1_np1_flush_offset]), + .din(cp1_i1_np1_flush), + .dout(cp2_i1_np1_flush_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i0_n_np1_flush_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp2_i0_n_np1_flush_offset]), + .scout(sov[cp2_i0_n_np1_flush_offset]), + .din(cp1_i0_n_np1_flush), + .dout(cp2_i0_n_np1_flush_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i1_n_np1_flush_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp2_i1_n_np1_flush_offset]), + .scout(sov[cp2_i1_n_np1_flush_offset]), + .din(cp1_i1_n_np1_flush), + .dout(cp2_i1_n_np1_flush_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i0_bp_pred_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp2_i0_bp_pred_offset]), + .scout(sov[cp2_i0_bp_pred_offset]), + .din(cp1_i0_bp_pred), + .dout(cp2_i0_bp_pred_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i1_bp_pred_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp2_i1_bp_pred_offset]), + .scout(sov[cp2_i1_bp_pred_offset]), + .din(cp1_i1_bp_pred), + .dout(cp2_i1_bp_pred_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i0_br_pred_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp2_i0_br_pred_offset]), + .scout(sov[cp2_i0_br_pred_offset]), + .din(cp1_i0_br_pred), + .dout(cp2_i0_br_pred_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i1_br_pred_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp2_i1_br_pred_offset]), + .scout(sov[cp2_i1_br_pred_offset]), + .din(cp1_i1_br_pred), + .dout(cp2_i1_br_pred_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i0_br_miss_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp2_i0_br_miss_offset]), + .scout(sov[cp2_i0_br_miss_offset]), + .din(cp1_i0_br_miss), + .dout(cp2_i0_br_miss_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i1_br_miss_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp2_i1_br_miss_offset]), + .scout(sov[cp2_i1_br_miss_offset]), + .din(cp1_i1_br_miss), + .dout(cp2_i1_br_miss_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i0_db_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp2_i0_db_val_offset]), + .scout(sov[cp2_i0_db_val_offset]), + .din(cp1_i0_db_val), + .dout(cp2_i0_db_val_q) + ); + + tri_rlmreg_p #(.WIDTH(19), .INIT(0), .NEEDS_SRESET(1)) cp2_i0_db_events_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp1_i0_db_val), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp2_i0_db_events_offset:cp2_i0_db_events_offset + 19 - 1]), + .scout(sov[cp2_i0_db_events_offset:cp2_i0_db_events_offset + 19 - 1]), + .din(cp1_i0_db_events), + .dout(cp2_i0_db_events_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i1_db_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp2_i1_db_val_offset]), + .scout(sov[cp2_i1_db_val_offset]), + .din(cp1_i1_db_val), + .dout(cp2_i1_db_val_q) + ); + + tri_rlmreg_p #(.WIDTH(19), .INIT(0), .NEEDS_SRESET(1)) cp2_i1_db_events_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp1_i1_db_val), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp2_i1_db_events_offset:cp2_i1_db_events_offset + 19 - 1]), + .scout(sov[cp2_i1_db_events_offset:cp2_i1_db_events_offset + 19 - 1]), + .din(cp1_i1_db_events), + .dout(cp2_i1_db_events_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) cp2_i0_perf_events_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp2_i0_perf_events_offset:cp2_i0_perf_events_offset + 4 - 1]), + .scout(sov[cp2_i0_perf_events_offset:cp2_i0_perf_events_offset + 4 - 1]), + .din(cp1_i0_perf_events), + .dout(cp2_i0_perf_events_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) cp2_i1_perf_events_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp2_i1_perf_events_offset:cp2_i1_perf_events_offset + 4 - 1]), + .scout(sov[cp2_i1_perf_events_offset:cp2_i1_perf_events_offset + 4 - 1]), + .din(cp1_i1_perf_events), + .dout(cp2_i1_perf_events_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i0_flush2ucode_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp2_i0_flush2ucode_offset]), + .scout(sov[cp2_i0_flush2ucode_offset]), + .din(cp1_i0_flush2ucode), + .dout(cp2_i0_flush2ucode_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i0_flush2ucode_type_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp2_i0_flush2ucode_type_offset]), + .scout(sov[cp2_i0_flush2ucode_type_offset]), + .din(cp1_i0_flush2ucode_type), + .dout(cp2_i0_flush2ucode_type_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i1_flush2ucode_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp2_i1_flush2ucode_offset]), + .scout(sov[cp2_i1_flush2ucode_offset]), + .din(cp1_i1_flush2ucode), + .dout(cp2_i1_flush2ucode_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i1_flush2ucode_type_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp2_i1_flush2ucode_type_offset]), + .scout(sov[cp2_i1_flush2ucode_type_offset]), + .din(cp1_i1_flush2ucode_type), + .dout(cp2_i1_flush2ucode_type_q) + ); + + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0), .NEEDS_SRESET(1)) cp2_i_bta_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp2_i_bta_offset:cp2_i_bta_offset + `EFF_IFAR_ARCH - 1]), + .scout(sov[cp2_i_bta_offset:cp2_i_bta_offset + `EFF_IFAR_ARCH - 1]), + .din(cp1_i_bta), + .dout(cp2_i_bta_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i0_iu_excvec_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp2_i0_iu_excvec_val_offset]), + .scout(sov[cp2_i0_iu_excvec_val_offset]), + .din(cp1_i0_iu_excvec_val), + .dout(cp2_i0_iu_excvec_val_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) cp2_i0_iu_excvec_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp1_i0_iu_excvec_val), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp2_i0_iu_excvec_offset:cp2_i0_iu_excvec_offset + 4 - 1]), + .scout(sov[cp2_i0_iu_excvec_offset:cp2_i0_iu_excvec_offset + 4 - 1]), + .din(cp1_i0_iu_excvec), + .dout(cp2_i0_iu_excvec_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i1_iu_excvec_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp2_i1_iu_excvec_val_offset]), + .scout(sov[cp2_i1_iu_excvec_val_offset]), + .din(cp1_i1_iu_excvec_val), + .dout(cp2_i1_iu_excvec_val_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) cp2_i1_iu_excvec_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp1_i1_iu_excvec_val), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp2_i1_iu_excvec_offset:cp2_i1_iu_excvec_offset + 4 - 1]), + .scout(sov[cp2_i1_iu_excvec_offset:cp2_i1_iu_excvec_offset + 4 - 1]), + .din(cp1_i1_iu_excvec), + .dout(cp2_i1_iu_excvec_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i0_lq_excvec_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp2_i0_lq_excvec_val_offset]), + .scout(sov[cp2_i0_lq_excvec_val_offset]), + .din(cp1_i0_lq_excvec_val), + .dout(cp2_i0_lq_excvec_val_q) + ); + + tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) cp2_i0_lq_excvec_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp1_i0_lq_excvec_val), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp2_i0_lq_excvec_offset:cp2_i0_lq_excvec_offset + 6 - 1]), + .scout(sov[cp2_i0_lq_excvec_offset:cp2_i0_lq_excvec_offset + 6 - 1]), + .din(cp1_i0_lq_excvec), + .dout(cp2_i0_lq_excvec_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i1_lq_excvec_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp2_i1_lq_excvec_val_offset]), + .scout(sov[cp2_i1_lq_excvec_val_offset]), + .din(cp1_i1_lq_excvec_val), + .dout(cp2_i1_lq_excvec_val_q) + ); + + tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) cp2_i1_lq_excvec_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp1_i1_lq_excvec_val), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp2_i1_lq_excvec_offset:cp2_i1_lq_excvec_offset + 6 - 1]), + .scout(sov[cp2_i1_lq_excvec_offset:cp2_i1_lq_excvec_offset + 6 - 1]), + .din(cp1_i1_lq_excvec), + .dout(cp2_i1_lq_excvec_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i0_xu_excvec_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp2_i0_xu_excvec_val_offset]), + .scout(sov[cp2_i0_xu_excvec_val_offset]), + .din(cp1_i0_xu_excvec_val), + .dout(cp2_i0_xu_excvec_val_q) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) cp2_i0_xu_excvec_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp1_i0_xu_excvec_val), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp2_i0_xu_excvec_offset:cp2_i0_xu_excvec_offset + 5 - 1]), + .scout(sov[cp2_i0_xu_excvec_offset:cp2_i0_xu_excvec_offset + 5 - 1]), + .din(cp1_i0_xu_excvec), + .dout(cp2_i0_xu_excvec_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i1_xu_excvec_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp2_i1_xu_excvec_val_offset]), + .scout(sov[cp2_i1_xu_excvec_val_offset]), + .din(cp1_i1_xu_excvec_val), + .dout(cp2_i1_xu_excvec_val_q) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) cp2_i1_xu_excvec_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp1_i1_xu_excvec_val), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp2_i1_xu_excvec_offset:cp2_i1_xu_excvec_offset + 5 - 1]), + .scout(sov[cp2_i1_xu_excvec_offset:cp2_i1_xu_excvec_offset + 5 - 1]), + .din(cp1_i1_xu_excvec), + .dout(cp2_i1_xu_excvec_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i0_axu_excvec_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp2_i0_axu_excvec_val_offset]), + .scout(sov[cp2_i0_axu_excvec_val_offset]), + .din(cp1_i0_axu_excvec_val), + .dout(cp2_i0_axu_excvec_val_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) cp2_i0_axu_excvec_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), // Has to be tiup because axu doesn't need a valid to have a exception + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp2_i0_axu_excvec_offset:cp2_i0_axu_excvec_offset + 4 - 1]), + .scout(sov[cp2_i0_axu_excvec_offset:cp2_i0_axu_excvec_offset + 4 - 1]), + .din(cp1_i0_axu_excvec), + .dout(cp2_i0_axu_excvec_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i1_axu_excvec_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp2_i1_axu_excvec_val_offset]), + .scout(sov[cp2_i1_axu_excvec_val_offset]), + .din(cp1_i1_axu_excvec_val), + .dout(cp2_i1_axu_excvec_val_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) cp2_i1_axu_excvec_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), // Has to be tiup because axu doesn't need a valid to have a exception + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp2_i1_axu_excvec_offset:cp2_i1_axu_excvec_offset + 4 - 1]), + .scout(sov[cp2_i1_axu_excvec_offset:cp2_i1_axu_excvec_offset + 4 - 1]), + .din(cp1_i1_axu_excvec), + .dout(cp2_i1_axu_excvec_q) + ); + + tri_rlmreg_p #(.WIDTH(`CPL_Q_DEPTH), .INIT(0), .NEEDS_SRESET(1)) cp1_executed_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp1_executed_offset:cp1_executed_offset + `CPL_Q_DEPTH - 1]), + .scout(sov[cp1_executed_offset:cp1_executed_offset + `CPL_Q_DEPTH - 1]), + .din(cp0_executed), + .dout(cp1_executed_q) + ); + + tri_rlmreg_p #(.WIDTH(`CPL_Q_DEPTH), .INIT(0), .NEEDS_SRESET(1)) cp1_dispatched_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp1_dispatched_offset:cp1_dispatched_offset + `CPL_Q_DEPTH - 1]), + .scout(sov[cp1_dispatched_offset:cp1_dispatched_offset + `CPL_Q_DEPTH - 1]), + .din(cp0_dispatched), + .dout(cp1_dispatched_q) + ); + + tri_rlmreg_p #(.WIDTH(`CPL_Q_DEPTH), .INIT(0), .NEEDS_SRESET(1)) cp1_n_flush_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(excvec_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp1_n_flush_offset:cp1_n_flush_offset + `CPL_Q_DEPTH - 1]), + .scout(sov[cp1_n_flush_offset:cp1_n_flush_offset + `CPL_Q_DEPTH - 1]), + .din(cp0_n_flush), + .dout(cp1_n_flush_q) + ); + + tri_rlmreg_p #(.WIDTH(`CPL_Q_DEPTH), .INIT(0), .NEEDS_SRESET(1)) cp1_np1_flush_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(excvec_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp1_np1_flush_offset:cp1_np1_flush_offset + `CPL_Q_DEPTH - 1]), + .scout(sov[cp1_np1_flush_offset:cp1_np1_flush_offset + `CPL_Q_DEPTH - 1]), + .din(cp0_np1_flush), + .dout(cp1_np1_flush_q) + ); + + tri_rlmreg_p #(.WIDTH(`CPL_Q_DEPTH), .INIT(0), .NEEDS_SRESET(1)) cp1_n_np1_flush_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(excvec_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp1_n_np1_flush_offset:cp1_n_np1_flush_offset + `CPL_Q_DEPTH - 1]), + .scout(sov[cp1_n_np1_flush_offset:cp1_n_np1_flush_offset + `CPL_Q_DEPTH - 1]), + .din(cp0_n_np1_flush), + .dout(cp1_n_np1_flush_q) + ); + + tri_rlmreg_p #(.WIDTH(`CPL_Q_DEPTH), .INIT(0), .NEEDS_SRESET(1)) cp1_flush2ucode_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(excvec_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp1_flush2ucode_offset:cp1_flush2ucode_offset + `CPL_Q_DEPTH - 1]), + .scout(sov[cp1_flush2ucode_offset:cp1_flush2ucode_offset + `CPL_Q_DEPTH - 1]), + .din(cp0_flush2ucode), + .dout(cp1_flush2ucode_q) + ); + + tri_rlmreg_p #(.WIDTH(`CPL_Q_DEPTH), .INIT(0), .NEEDS_SRESET(1)) cp1_flush2ucode_type_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(excvec_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp1_flush2ucode_type_offset:cp1_flush2ucode_type_offset + `CPL_Q_DEPTH - 1]), + .scout(sov[cp1_flush2ucode_type_offset:cp1_flush2ucode_type_offset + `CPL_Q_DEPTH - 1]), + .din(cp0_flush2ucode_type), + .dout(cp1_flush2ucode_type_q) + ); + + generate + begin : xhdl5 + genvar i; + for (i = 0; i <= `CPL_Q_DEPTH - 1; i = i + 1) + begin : q_depth_gen + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) cp1_perf_events_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(excvec_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp1_perf_events_offset + 4 * i:cp1_perf_events_offset + 4 * (i + 1) - 1]), + .scout(sov[cp1_perf_events_offset + 4 * i:cp1_perf_events_offset + 4 * (i + 1) - 1]), + .din(cp0_perf_events[i]), + .dout(cp1_perf_events_q[i]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp1_iu_excvec_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(excvec_act_v[i]), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp1_iu_excvec_val_offset + i]), + .scout(sov[cp1_iu_excvec_val_offset + i]), + .din(cp0_iu_excvec_val[i]), + .dout(cp1_iu_excvec_val_q[i]) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) cp1_iu_excvec_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(excvec_act_v[i]), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp1_iu_excvec_offset + 4 * i:cp1_iu_excvec_offset + 4 * (i + 1) - 1]), + .scout(sov[cp1_iu_excvec_offset + 4 * i:cp1_iu_excvec_offset + 4 * (i + 1) - 1]), + .din(cp0_iu_excvec[i]), + .dout(cp1_iu_excvec_q[i]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp1_lq_excvec_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(excvec_act_v[i]), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp1_lq_excvec_val_offset + i]), + .scout(sov[cp1_lq_excvec_val_offset + i]), + .din(cp0_lq_excvec_val[i]), + .dout(cp1_lq_excvec_val_q[i]) + ); + + tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) cp1_lq_excvec_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(excvec_act_v[i]), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp1_lq_excvec_offset + 6 * i:cp1_lq_excvec_offset + 6 * (i + 1) - 1]), + .scout(sov[cp1_lq_excvec_offset + 6 * i:cp1_lq_excvec_offset + 6 * (i + 1) - 1]), + .din(cp0_lq_excvec[i]), + .dout(cp1_lq_excvec_q[i]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp1_xu_excvec_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(excvec_act_v[i]), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp1_xu_excvec_val_offset + i]), + .scout(sov[cp1_xu_excvec_val_offset + i]), + .din(cp0_xu_excvec_val[i]), + .dout(cp1_xu_excvec_val_q[i]) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) cp1_xu_excvec_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(excvec_act_v[i]), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp1_xu_excvec_offset + 5 * i:cp1_xu_excvec_offset + 5 * (i + 1) - 1]), + .scout(sov[cp1_xu_excvec_offset + 5 * i:cp1_xu_excvec_offset + 5 * (i + 1) - 1]), + .din(cp0_xu_excvec[i]), + .dout(cp1_xu_excvec_q[i]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp1_axu_excvec_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(excvec_act_v[i]), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp1_axu_excvec_val_offset + i]), + .scout(sov[cp1_axu_excvec_val_offset + i]), + .din(cp0_axu_excvec_val[i]), + .dout(cp1_axu_excvec_val_q[i]) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) cp1_axu_excvec_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(excvec_act_v[i]), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp1_axu_excvec_offset + 4 * i:cp1_axu_excvec_offset + 4 * (i + 1) - 1]), + .scout(sov[cp1_axu_excvec_offset + 4 * i:cp1_axu_excvec_offset + 4 * (i + 1) - 1]), + .din(cp0_axu_excvec[i]), + .dout(cp1_axu_excvec_q[i]) + ); + + tri_rlmreg_p #(.WIDTH(19), .INIT(0), .NEEDS_SRESET(1)) cp1_db_events_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(excvec_act_v[i]), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp1_db_events_offset + 19 * i:cp1_db_events_offset + 19 * (i + 1) - 1]), + .scout(sov[cp1_db_events_offset + 19 * i:cp1_db_events_offset + 19 * (i + 1) - 1]), + .din(cp0_db_events[i]), + .dout(cp1_db_events_q[i]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp1_recirc_vld_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(excvec_act_v[i]), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp1_recirc_vld_offset + i]), + .scout(sov[cp1_recirc_vld_offset + i]), + .din(cp0_recirc_vld[i]), + .dout(cp1_recirc_vld_q[i]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp1_async_block_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(excvec_act_v[i]), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp1_async_block_offset + i]), + .scout(sov[cp1_async_block_offset + i]), + .din(cp0_async_block[i]), + .dout(cp1_async_block_q[i]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp1_is_br_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(excvec_act_v[i]), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp1_is_br_offset + i]), + .scout(sov[cp1_is_br_offset + i]), + .din(cp0_is_br[i]), + .dout(cp1_is_br_q[i]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp1_br_add_chk_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(excvec_act_v[i]), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp1_br_add_chk_offset + i]), + .scout(sov[cp1_br_add_chk_offset + i]), + .din(cp0_br_add_chk[i]), + .dout(cp1_br_add_chk_q[i]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp1_bp_pred_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(excvec_act_v[i]), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp1_bp_pred_offset + i]), + .scout(sov[cp1_bp_pred_offset + i]), + .din(cp0_bp_pred[i]), + .dout(cp1_bp_pred_q[i]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp1_br_pred_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(excvec_act_v[i]), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp1_br_pred_offset + i]), + .scout(sov[cp1_br_pred_offset + i]), + .din(cp0_br_pred[i]), + .dout(cp1_br_pred_q[i]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp1_br_miss_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(excvec_act_v[i]), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp1_br_miss_offset + i]), + .scout(sov[cp1_br_miss_offset + i]), + .din(cp0_br_miss[i]), + .dout(cp1_br_miss_q[i]) + ); + end + end + endgenerate + + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0), .NEEDS_SRESET(1)) cp1_br_bta_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp0_br_bta_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp1_br_bta_offset:cp1_br_bta_offset + `EFF_IFAR_ARCH - 1]), + .scout(sov[cp1_br_bta_offset:cp1_br_bta_offset + `EFF_IFAR_ARCH - 1]), + .din(cp0_br_bta), + .dout(cp1_br_bta_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp1_br_bta_v_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp1_br_bta_v_offset]), + .scout(sov[cp1_br_bta_v_offset]), + .din(cp0_br_bta_v), + .dout(cp1_br_bta_v_q) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) cp1_br_bta_itag_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp0_br_bta_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp1_br_bta_itag_offset:cp1_br_bta_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[cp1_br_bta_itag_offset:cp1_br_bta_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(cp0_br_bta_itag), + .dout(cp1_br_bta_itag_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i0_dispatched_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i0_dispatched_offset]), + .scout(sov[cp0_i0_dispatched_offset]), + .din(iu6_i0_dispatched_d), + .dout(iu6_i0_dispatched_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i1_dispatched_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i1_dispatched_offset]), + .scout(sov[cp0_i1_dispatched_offset]), + .din(iu6_i1_dispatched_d), + .dout(iu6_i1_dispatched_q) + ); + + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) iu6_i0_ifar_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i0_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i0_ifar_offset:cp0_i0_ifar_offset + `EFF_IFAR_WIDTH - 1]), + .scout(sov[cp0_i0_ifar_offset:cp0_i0_ifar_offset + `EFF_IFAR_WIDTH - 1]), + .din(rn_cp_iu6_i0_ifar), + .dout(iu6_i0_ifar_q) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) iu6_i0_ucode_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i0_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i0_ucode_offset:cp0_i0_ucode_offset + 3 - 1]), + .scout(sov[cp0_i0_ucode_offset:cp0_i0_ucode_offset + 3 - 1]), + .din(rn_cp_iu6_i0_ucode), + .dout(iu6_i0_ucode_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i0_fuse_nop_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i0_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i0_fuse_nop_offset]), + .scout(sov[cp0_i0_fuse_nop_offset]), + .din(rn_cp_iu6_i0_fuse_nop), + .dout(iu6_i0_fuse_nop_q) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) iu6_i0_error_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i0_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i0_error_offset:cp0_i0_error_offset + 3 - 1]), + .scout(sov[cp0_i0_error_offset:cp0_i0_error_offset + 3 - 1]), + .din(rn_cp_iu6_i0_error), + .dout(iu6_i0_error_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i0_valop_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i0_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i0_valop_offset]), + .scout(sov[cp0_i0_valop_offset]), + .din(rn_cp_iu6_i0_valop), + .dout(iu6_i0_valop_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i0_is_rfi_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i0_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i0_is_rfi_offset]), + .scout(sov[cp0_i0_is_rfi_offset]), + .din(rn_cp_iu6_i0_is_rfi), + .dout(iu6_i0_is_rfi_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i0_is_rfgi_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i0_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i0_is_rfgi_offset]), + .scout(sov[cp0_i0_is_rfgi_offset]), + .din(rn_cp_iu6_i0_is_rfgi), + .dout(iu6_i0_is_rfgi_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i0_is_rfci_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i0_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i0_is_rfci_offset]), + .scout(sov[cp0_i0_is_rfci_offset]), + .din(rn_cp_iu6_i0_is_rfci), + .dout(iu6_i0_is_rfci_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i0_is_rfmci_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i0_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i0_is_rfmci_offset]), + .scout(sov[cp0_i0_is_rfmci_offset]), + .din(rn_cp_iu6_i0_is_rfmci), + .dout(iu6_i0_is_rfmci_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i0_is_isync_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i0_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i0_is_isync_offset]), + .scout(sov[cp0_i0_is_isync_offset]), + .din(rn_cp_iu6_i0_is_isync), + .dout(iu6_i0_is_isync_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i0_is_sc_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i0_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i0_is_sc_offset]), + .scout(sov[cp0_i0_is_sc_offset]), + .din(rn_cp_iu6_i0_is_sc), + .dout(iu6_i0_is_sc_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i0_is_np1_flush_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i0_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i0_is_np1_flush_offset]), + .scout(sov[cp0_i0_is_np1_flush_offset]), + .din(rn_cp_iu6_i0_is_np1_flush), + .dout(iu6_i0_is_np1_flush_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i0_is_sc_hyp_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i0_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i0_is_sc_hyp_offset]), + .scout(sov[cp0_i0_is_sc_hyp_offset]), + .din(rn_cp_iu6_i0_is_sc_hyp), + .dout(iu6_i0_is_sc_hyp_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i0_is_sc_ill_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i0_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i0_is_sc_ill_offset]), + .scout(sov[cp0_i0_is_sc_ill_offset]), + .din(rn_cp_iu6_i0_is_sc_ill), + .dout(iu6_i0_is_sc_ill_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i0_is_dcr_ill_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i0_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i0_is_dcr_ill_offset]), + .scout(sov[cp0_i0_is_dcr_ill_offset]), + .din(rn_cp_iu6_i0_is_dcr_ill), + .dout(iu6_i0_is_dcr_ill_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i0_is_attn_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i0_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i0_is_attn_offset]), + .scout(sov[cp0_i0_is_attn_offset]), + .din(rn_cp_iu6_i0_is_attn), + .dout(iu6_i0_is_attn_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i0_is_ehpriv_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i0_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i0_is_ehpriv_offset]), + .scout(sov[cp0_i0_is_ehpriv_offset]), + .din(rn_cp_iu6_i0_is_ehpriv), + .dout(iu6_i0_is_ehpriv_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i0_is_folded_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i0_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i0_is_folded_offset]), + .scout(sov[cp0_i0_is_folded_offset]), + .din(rn_cp_iu6_i0_is_folded), + .dout(iu6_i0_is_folded_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i0_async_block_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i0_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i0_async_block_offset]), + .scout(sov[cp0_i0_async_block_offset]), + .din(rn_cp_iu6_i0_async_block), + .dout(iu6_i0_async_block_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i0_is_br_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i0_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i0_is_br_offset]), + .scout(sov[cp0_i0_is_br_offset]), + .din(rn_cp_iu6_i0_is_br), + .dout(iu6_i0_is_br_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i0_br_add_chk_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i0_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i0_br_add_chk_offset]), + .scout(sov[cp0_i0_br_add_chk_offset]), + .din(rn_cp_iu6_i0_br_add_chk), + .dout(iu6_i0_br_add_chk_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i0_bp_pred_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i0_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i0_bp_pred_offset]), + .scout(sov[cp0_i0_bp_pred_offset]), + .din(rn_cp_iu6_i0_pred), + .dout(iu6_i0_bp_pred_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i0_rollover_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i0_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i0_rollover_offset]), + .scout(sov[cp0_i0_rollover_offset]), + .din(rn_cp_iu6_i0_rollover), + .dout(iu6_i0_rollover_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i0_isram_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i0_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i0_isram_offset]), + .scout(sov[cp0_i0_isram_offset]), + .din(rn_cp_iu6_i0_isram), + .dout(iu6_i0_isram_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i0_match_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i0_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i0_match_offset]), + .scout(sov[cp0_i0_match_offset]), + .din(rn_cp_iu6_i0_match), + .dout(iu6_i0_match_q) + ); + + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) iu6_i1_ifar_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i1_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i1_ifar_offset:cp0_i1_ifar_offset + `EFF_IFAR_WIDTH - 1]), + .scout(sov[cp0_i1_ifar_offset:cp0_i1_ifar_offset + `EFF_IFAR_WIDTH - 1]), + .din(rn_cp_iu6_i1_ifar), + .dout(iu6_i1_ifar_q) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) iu6_i1_ucode_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i1_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i1_ucode_offset:cp0_i1_ucode_offset + 3 - 1]), + .scout(sov[cp0_i1_ucode_offset:cp0_i1_ucode_offset + 3 - 1]), + .din(rn_cp_iu6_i1_ucode), + .dout(iu6_i1_ucode_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i1_fuse_nop_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i1_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i1_fuse_nop_offset]), + .scout(sov[cp0_i1_fuse_nop_offset]), + .din(rn_cp_iu6_i1_fuse_nop), + .dout(iu6_i1_fuse_nop_q) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) iu6_i1_error_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i1_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i1_error_offset:cp0_i1_error_offset + 3 - 1]), + .scout(sov[cp0_i1_error_offset:cp0_i1_error_offset + 3 - 1]), + .din(rn_cp_iu6_i1_error), + .dout(iu6_i1_error_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i1_valop_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i1_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i1_valop_offset]), + .scout(sov[cp0_i1_valop_offset]), + .din(rn_cp_iu6_i1_valop), + .dout(iu6_i1_valop_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i1_is_rfi_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i1_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i1_is_rfi_offset]), + .scout(sov[cp0_i1_is_rfi_offset]), + .din(rn_cp_iu6_i1_is_rfi), + .dout(iu6_i1_is_rfi_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i1_is_rfgi_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i1_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i1_is_rfgi_offset]), + .scout(sov[cp0_i1_is_rfgi_offset]), + .din(rn_cp_iu6_i1_is_rfgi), + .dout(iu6_i1_is_rfgi_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i1_is_rfci_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i1_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i1_is_rfci_offset]), + .scout(sov[cp0_i1_is_rfci_offset]), + .din(rn_cp_iu6_i1_is_rfci), + .dout(iu6_i1_is_rfci_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i1_is_rfmci_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i1_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i1_is_rfmci_offset]), + .scout(sov[cp0_i1_is_rfmci_offset]), + .din(rn_cp_iu6_i1_is_rfmci), + .dout(iu6_i1_is_rfmci_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i1_is_isync_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i1_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i1_is_isync_offset]), + .scout(sov[cp0_i1_is_isync_offset]), + .din(rn_cp_iu6_i1_is_isync), + .dout(iu6_i1_is_isync_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i1_is_sc_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i1_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i1_is_sc_offset]), + .scout(sov[cp0_i1_is_sc_offset]), + .din(rn_cp_iu6_i1_is_sc), + .dout(iu6_i1_is_sc_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i1_is_np1_flush_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i1_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i1_is_np1_flush_offset]), + .scout(sov[cp0_i1_is_np1_flush_offset]), + .din(rn_cp_iu6_i1_is_np1_flush), + .dout(iu6_i1_is_np1_flush_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i1_is_sc_hyp_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i1_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i1_is_sc_hyp_offset]), + .scout(sov[cp0_i1_is_sc_hyp_offset]), + .din(rn_cp_iu6_i1_is_sc_hyp), + .dout(iu6_i1_is_sc_hyp_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i1_is_sc_ill_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i1_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i1_is_sc_ill_offset]), + .scout(sov[cp0_i1_is_sc_ill_offset]), + .din(rn_cp_iu6_i1_is_sc_ill), + .dout(iu6_i1_is_sc_ill_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i1_is_dcr_ill_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i1_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i1_is_dcr_ill_offset]), + .scout(sov[cp0_i1_is_dcr_ill_offset]), + .din(rn_cp_iu6_i1_is_dcr_ill), + .dout(iu6_i1_is_dcr_ill_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i1_is_attn_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i1_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i1_is_attn_offset]), + .scout(sov[cp0_i1_is_attn_offset]), + .din(rn_cp_iu6_i1_is_attn), + .dout(iu6_i1_is_attn_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i1_is_ehpriv_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i1_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i1_is_ehpriv_offset]), + .scout(sov[cp0_i1_is_ehpriv_offset]), + .din(rn_cp_iu6_i1_is_ehpriv), + .dout(iu6_i1_is_ehpriv_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i1_is_folded_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i1_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i1_is_folded_offset]), + .scout(sov[cp0_i1_is_folded_offset]), + .din(rn_cp_iu6_i1_is_folded), + .dout(iu6_i1_is_folded_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i1_async_block_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i1_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i1_async_block_offset]), + .scout(sov[cp0_i1_async_block_offset]), + .din(rn_cp_iu6_i1_async_block), + .dout(iu6_i1_async_block_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i1_is_br_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i1_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i1_is_br_offset]), + .scout(sov[cp0_i1_is_br_offset]), + .din(rn_cp_iu6_i1_is_br), + .dout(iu6_i1_is_br_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i1_br_add_chk_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i1_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i1_br_add_chk_offset]), + .scout(sov[cp0_i1_br_add_chk_offset]), + .din(rn_cp_iu6_i1_br_add_chk), + .dout(iu6_i1_br_add_chk_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i1_bp_pred_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i1_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i1_bp_pred_offset]), + .scout(sov[cp0_i1_bp_pred_offset]), + .din(rn_cp_iu6_i1_pred), + .dout(iu6_i1_bp_pred_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i1_rollover_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i1_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i1_rollover_offset]), + .scout(sov[cp0_i1_rollover_offset]), + .din(rn_cp_iu6_i1_rollover), + .dout(iu6_i1_rollover_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i1_isram_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i1_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i1_isram_offset]), + .scout(sov[cp0_i1_isram_offset]), + .din(rn_cp_iu6_i1_isram), + .dout(iu6_i1_isram_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i1_match_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rn_cp_iu6_i1_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_i1_match_offset]), + .scout(sov[cp0_i1_match_offset]), + .din(rn_cp_iu6_i1_match), + .dout(iu6_i1_match_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_uc_hold_rollover_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp0_uc_hold_rollover_offset]), + .scout(sov[cp0_uc_hold_rollover_offset]), + .din(iu6_uc_hold_rollover_d), + .dout(iu6_uc_hold_rollover_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq0_execute_vld_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[lq0_execute_vld_offset]), + .scout(sov[lq0_execute_vld_offset]), + .din(lq0_execute_vld_d), + .dout(lq0_execute_vld_q) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) lq0_itag_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), // can gate if I use lq0_iu_execute_vld or lq0_iu_recirc_val + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[lq0_itag_offset:lq0_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[lq0_itag_offset:lq0_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(lq0_iu_itag), + .dout(lq0_itag_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq0_n_flush_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(lq0_iu_execute_vld), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[lq0_n_flush_offset]), + .scout(sov[lq0_n_flush_offset]), + .din(lq0_iu_n_flush), + .dout(lq0_n_flush_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq0_np1_flush_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(lq0_iu_execute_vld), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[lq0_np1_flush_offset]), + .scout(sov[lq0_np1_flush_offset]), + .din(lq0_iu_np1_flush), + .dout(lq0_np1_flush_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq0_dacr_type_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(lq0_iu_execute_vld), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[lq0_dacr_type_offset]), + .scout(sov[lq0_dacr_type_offset]), + .din(lq0_iu_dacr_type), + .dout(lq0_dacr_type_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lq0_dacrw_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(lq0_iu_execute_vld), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[lq0_dacrw_offset:lq0_dacrw_offset + 4 - 1]), + .scout(sov[lq0_dacrw_offset:lq0_dacrw_offset + 4 - 1]), + .din(lq0_iu_dacrw), + .dout(lq0_dacrw_q) + ); + + tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) lq0_instr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(lq0_iu_execute_vld), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[lq0_instr_offset:lq0_instr_offset + 32 - 1]), + .scout(sov[lq0_instr_offset:lq0_instr_offset + 32 - 1]), + .din(lq0_iu_instr), + .dout(lq0_instr_q) + ); + + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lq0_eff_addr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(lq0_iu_dear_val), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[lq0_eff_addr_offset:lq0_eff_addr_offset + `GPR_WIDTH - 1]), + .scout(sov[lq0_eff_addr_offset:lq0_eff_addr_offset + `GPR_WIDTH - 1]), + .din(lq0_iu_eff_addr), + .dout(lq0_eff_addr_q) + ); + + assign lq0_exception_val_d = lq0_iu_execute_vld & lq0_iu_exception_val; + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq0_exception_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[lq0_exception_val_offset]), + .scout(sov[lq0_exception_val_offset]), + .din(lq0_exception_val_d), + .dout(lq0_exception_val_q) + ); + + tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) lq0_exception_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(lq0_iu_execute_vld), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[lq0_exception_offset:lq0_exception_offset + 6 - 1]), + .scout(sov[lq0_exception_offset:lq0_exception_offset + 6 - 1]), + .din(lq0_iu_exception), + .dout(lq0_exception_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq0_flush2ucode_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(lq0_iu_execute_vld), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[lq0_flush2ucode_offset]), + .scout(sov[lq0_flush2ucode_offset]), + .din(lq0_iu_flush2ucode), + .dout(lq0_flush2ucode_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq0_flush2ucode_type_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(lq0_iu_execute_vld), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[lq0_flush2ucode_type_offset]), + .scout(sov[lq0_flush2ucode_type_offset]), + .din(lq0_iu_flush2ucode_type), + .dout(lq0_flush2ucode_type_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq0_recirc_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[lq0_recirc_val_offset]), + .scout(sov[lq0_recirc_val_offset]), + .din(lq0_iu_recirc_val), + .dout(lq0_recirc_val_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq1_execute_vld_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[lq1_execute_vld_offset]), + .scout(sov[lq1_execute_vld_offset]), + .din(lq1_execute_vld_d), + .dout(lq1_execute_vld_q) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) lq1_itag_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(lq1_iu_execute_vld), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[lq1_itag_offset:lq1_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[lq1_itag_offset:lq1_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(lq1_iu_itag), + .dout(lq1_itag_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq1_n_flush_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(lq1_iu_execute_vld), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[lq1_n_flush_offset]), + .scout(sov[lq1_n_flush_offset]), + .din(lq1_iu_n_flush), + .dout(lq1_n_flush_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq1_np1_flush_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(lq1_iu_execute_vld), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[lq1_np1_flush_offset]), + .scout(sov[lq1_np1_flush_offset]), + .din(lq1_iu_np1_flush), + .dout(lq1_np1_flush_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq1_exception_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(lq1_iu_execute_vld), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[lq1_exception_val_offset]), + .scout(sov[lq1_exception_val_offset]), + .din(lq1_iu_exception_val), + .dout(lq1_exception_val_q) + ); + + tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) lq1_exception_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(lq1_iu_execute_vld), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[lq1_exception_offset:lq1_exception_offset + 6 - 1]), + .scout(sov[lq1_exception_offset:lq1_exception_offset + 6 - 1]), + .din(lq1_iu_exception), + .dout(lq1_exception_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq1_dacr_type_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(lq1_iu_execute_vld), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[lq1_dacr_type_offset]), + .scout(sov[lq1_dacr_type_offset]), + .din(lq1_iu_dacr_type), + .dout(lq1_dacr_type_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lq1_dacrw_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(lq1_iu_execute_vld), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[lq1_dacrw_offset:lq1_dacrw_offset + 4 - 1]), + .scout(sov[lq1_dacrw_offset:lq1_dacrw_offset + 4 - 1]), + .din(lq1_iu_dacrw), + .dout(lq1_dacrw_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lq1_perf_events_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(lq1_iu_execute_vld), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[lq1_perf_events_offset:lq1_perf_events_offset + 4 - 1]), + .scout(sov[lq1_perf_events_offset:lq1_perf_events_offset + 4 - 1]), + .din(lq1_iu_perf_events), + .dout(lq1_perf_events_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) br_perf_events_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(br_iu_execute_vld), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[br_perf_events_offset:br_perf_events_offset + 4 - 1]), + .scout(sov[br_perf_events_offset:br_perf_events_offset + 4 - 1]), + .din(br_iu_perf_events), + .dout(br_perf_events_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) axu0_perf_events_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(axu0_iu_execute_vld), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[axu0_perf_events_offset:axu0_perf_events_offset + 4 - 1]), + .scout(sov[axu0_perf_events_offset:axu0_perf_events_offset + 4 - 1]), + .din(axu0_iu_perf_events), + .dout(axu0_perf_events_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) axu1_perf_events_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(axu1_iu_execute_vld), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[axu1_perf_events_offset:axu1_perf_events_offset + 4 - 1]), + .scout(sov[axu1_perf_events_offset:axu1_perf_events_offset + 4 - 1]), + .din(axu1_iu_perf_events), + .dout(axu1_perf_events_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) br_execute_vld_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[br_execute_vld_offset]), + .scout(sov[br_execute_vld_offset]), + .din(br_execute_vld_d), + .dout(br_execute_vld_q) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) br_itag_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(br_iu_execute_vld), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[br_itag_offset:br_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[br_itag_offset:br_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(br_iu_itag), + .dout(br_itag_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) br_taken_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(br_iu_execute_vld), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[br_taken_offset]), + .scout(sov[br_taken_offset]), + .din(br_iu_taken), + .dout(br_taken_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) br_redirect_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), // removed br_iu_execute_vld + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[br_redirect_offset]), + .scout(sov[br_redirect_offset]), + .din(br_iu_redirect), + .dout(br_redirect_q) + ); + + assign br_bta_d = {({`EFF_IFAR_ARCH-30{msr_cm_q}} & br_iu_bta[62 - `EFF_IFAR_ARCH:31]), br_iu_bta[32:61]}; + + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0), .NEEDS_SRESET(1)) br_bta_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(br_iu_execute_vld), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[br_bta_offset:br_bta_offset + `EFF_IFAR_ARCH - 1]), + .scout(sov[br_bta_offset:br_bta_offset + `EFF_IFAR_ARCH - 1]), + .din(br_bta_d), + .dout(br_bta_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_execute_vld_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[xu_execute_vld_offset]), + .scout(sov[xu_execute_vld_offset]), + .din(xu_execute_vld_d), + .dout(xu_execute_vld_q) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) xu_itag_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(xu_iu_execute_vld), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[xu_itag_offset:xu_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[xu_itag_offset:xu_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(xu_iu_itag), + .dout(xu_itag_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_n_flush_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(xu_iu_execute_vld), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[xu_n_flush_offset]), + .scout(sov[xu_n_flush_offset]), + .din(xu_iu_n_flush), + .dout(xu_n_flush_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_np1_flush_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(xu_iu_execute_vld), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[xu_np1_flush_offset]), + .scout(sov[xu_np1_flush_offset]), + .din(xu_iu_np1_flush), + .dout(xu_np1_flush_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_flush2ucode_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(xu_iu_execute_vld), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[xu_flush2ucode_offset]), + .scout(sov[xu_flush2ucode_offset]), + .din(xu_iu_flush2ucode), + .dout(xu_flush2ucode_q) + ); + + assign xu_exception_val_d = xu_iu_execute_vld & xu_iu_exception_val; + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_exception_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[xu_exception_val_offset]), + .scout(sov[xu_exception_val_offset]), + .din(xu_exception_val_d), + .dout(xu_exception_val_q) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) xu_exception_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(xu_iu_execute_vld), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[xu_exception_offset:xu_exception_offset + 5 - 1]), + .scout(sov[xu_exception_offset:xu_exception_offset + 5 - 1]), + .din(xu_iu_exception), + .dout(xu_exception_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_mtiar_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), // removed xu_iu_execute_vld because used in branches + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[xu_mtiar_offset]), + .scout(sov[xu_mtiar_offset]), + .din(xu_iu_mtiar), + .dout(xu_mtiar_q) + ); + + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0), .NEEDS_SRESET(1)) xu_bta_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(xu_iu_execute_vld), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[xu_bta_offset:xu_bta_offset + `EFF_IFAR_ARCH - 1]), + .scout(sov[xu_bta_offset:xu_bta_offset + `EFF_IFAR_ARCH - 1]), + .din(xu_iu_bta), + .dout(xu_bta_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) xu_perf_events_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(xu_iu_execute_vld), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[xu_perf_events_offset:xu_perf_events_offset + 4 - 1]), + .scout(sov[xu_perf_events_offset:xu_perf_events_offset + 4 - 1]), + .din(xu_iu_perf_events), + .dout(xu_perf_events_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu1_execute_vld_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[xu1_execute_vld_offset]), + .scout(sov[xu1_execute_vld_offset]), + .din(xu1_execute_vld_d), + .dout(xu1_execute_vld_q) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) xu1_itag_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(xu1_iu_execute_vld), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[xu1_itag_offset:xu1_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[xu1_itag_offset:xu1_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(xu1_iu_itag), + .dout(xu1_itag_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) axu0_execute_vld_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[axu0_execute_vld_offset]), + .scout(sov[axu0_execute_vld_offset]), + .din(axu0_execute_vld_d), + .dout(axu0_execute_vld_q) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) axu0_itag_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(axu0_iu_execute_vld), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[axu0_itag_offset:axu0_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[axu0_itag_offset:axu0_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(axu0_iu_itag), + .dout(axu0_itag_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) axu0_n_flush_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(axu0_iu_execute_vld), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[axu0_n_flush_offset]), + .scout(sov[axu0_n_flush_offset]), + .din(axu0_iu_n_flush), + .dout(axu0_n_flush_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) axu0_np1_flush_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(axu0_iu_execute_vld), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[axu0_np1_flush_offset]), + .scout(sov[axu0_np1_flush_offset]), + .din(axu0_iu_np1_flush), + .dout(axu0_np1_flush_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) axu0_n_np1_flush_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(axu0_iu_execute_vld), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[axu0_n_np1_flush_offset]), + .scout(sov[axu0_n_np1_flush_offset]), + .din(axu0_iu_n_np1_flush), + .dout(axu0_n_np1_flush_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) axu0_flush2ucode_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(axu0_iu_execute_vld), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[axu0_flush2ucode_offset]), + .scout(sov[axu0_flush2ucode_offset]), + .din(axu0_iu_flush2ucode), + .dout(axu0_flush2ucode_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) axu0_flush2ucode_type_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(axu0_iu_execute_vld), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[axu0_flush2ucode_type_offset]), + .scout(sov[axu0_flush2ucode_type_offset]), + .din(axu0_iu_flush2ucode_type), + .dout(axu0_flush2ucode_type_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) axu0_exception_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(axu0_iu_execute_vld), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[axu0_exception_val_offset]), + .scout(sov[axu0_exception_val_offset]), + .din(axu0_iu_exception_val), + .dout(axu0_exception_val_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) axu0_exception_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(axu0_iu_execute_vld), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[axu0_exception_offset:axu0_exception_offset + 4 - 1]), + .scout(sov[axu0_exception_offset:axu0_exception_offset + 4 - 1]), + .din(axu0_iu_exception), + .dout(axu0_exception_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) axu1_execute_vld_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[axu1_execute_vld_offset]), + .scout(sov[axu1_execute_vld_offset]), + .din(axu1_execute_vld_d), + .dout(axu1_execute_vld_q) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) axu1_itag_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(axu1_iu_execute_vld), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[axu1_itag_offset:axu1_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[axu1_itag_offset:axu1_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(axu1_iu_itag), + .dout(axu1_itag_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) axu1_n_flush_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(axu1_iu_execute_vld), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[axu1_n_flush_offset]), + .scout(sov[axu1_n_flush_offset]), + .din(axu1_iu_n_flush), + .dout(axu1_n_flush_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) axu1_np1_flush_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(axu1_iu_execute_vld), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[axu1_np1_flush_offset]), + .scout(sov[axu1_np1_flush_offset]), + .din(axu1_iu_np1_flush), + .dout(axu1_np1_flush_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) axu1_n_np1_flush_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(axu1_iu_execute_vld), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[axu1_n_np1_flush_offset]), + .scout(sov[axu1_n_np1_flush_offset]), + .din(axu1_iu_n_np1_flush), + .dout(axu1_n_np1_flush_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) axu1_flush2ucode_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(axu1_iu_execute_vld), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[axu1_flush2ucode_offset]), + .scout(sov[axu1_flush2ucode_offset]), + .din(axu1_iu_flush2ucode), + .dout(axu1_flush2ucode_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) axu1_flush2ucode_type_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(axu1_iu_execute_vld), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[axu1_flush2ucode_type_offset]), + .scout(sov[axu1_flush2ucode_type_offset]), + .din(axu1_iu_flush2ucode_type), + .dout(axu1_flush2ucode_type_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) axu1_exception_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(axu1_iu_execute_vld), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[axu1_exception_val_offset]), + .scout(sov[axu1_exception_val_offset]), + .din(axu1_iu_exception_val), + .dout(axu1_exception_val_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) axu1_exception_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(axu1_iu_execute_vld), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[axu1_exception_offset:axu1_exception_offset + 4 - 1]), + .scout(sov[axu1_exception_offset:axu1_exception_offset + 4 - 1]), + .din(axu1_iu_exception), + .dout(axu1_exception_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_xu_cp3_rfi_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[iu_xu_cp3_rfi_offset]), + .scout(sov[iu_xu_cp3_rfi_offset]), + .din(iu_xu_cp2_rfi_d), + .dout(iu_xu_cp3_rfi_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_xu_cp3_rfgi_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[iu_xu_cp3_rfgi_offset]), + .scout(sov[iu_xu_cp3_rfgi_offset]), + .din(iu_xu_cp2_rfgi_d), + .dout(iu_xu_cp3_rfgi_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_xu_cp3_rfci_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[iu_xu_cp3_rfci_offset]), + .scout(sov[iu_xu_cp3_rfci_offset]), + .din(iu_xu_cp2_rfci_d), + .dout(iu_xu_cp3_rfci_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_xu_cp3_rfmci_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[iu_xu_cp3_rfmci_offset]), + .scout(sov[iu_xu_cp3_rfmci_offset]), + .din(iu_xu_cp2_rfmci_d), + .dout(iu_xu_cp3_rfmci_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_xu_cp4_rfi_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[iu_xu_cp4_rfi_offset]), + .scout(sov[iu_xu_cp4_rfi_offset]), + .din(iu_xu_cp3_rfi_q), + .dout(iu_xu_cp4_rfi_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_xu_cp4_rfgi_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[iu_xu_cp4_rfgi_offset]), + .scout(sov[iu_xu_cp4_rfgi_offset]), + .din(iu_xu_cp3_rfgi_q), + .dout(iu_xu_cp4_rfgi_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_xu_cp4_rfci_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[iu_xu_cp4_rfci_offset]), + .scout(sov[iu_xu_cp4_rfci_offset]), + .din(iu_xu_cp3_rfci_q), + .dout(iu_xu_cp4_rfci_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_xu_cp4_rfmci_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[iu_xu_cp4_rfmci_offset]), + .scout(sov[iu_xu_cp4_rfmci_offset]), + .din(iu_xu_cp3_rfmci_q), + .dout(iu_xu_cp4_rfmci_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_ld_save_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp3_ld_save_offset]), + .scout(sov[cp3_ld_save_offset]), + .din(cp3_ld_save_d), + .dout(cp3_ld_save_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_st_save_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp3_st_save_offset]), + .scout(sov[cp3_st_save_offset]), + .din(cp3_st_save_d), + .dout(cp3_st_save_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_fp_save_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp3_fp_save_offset]), + .scout(sov[cp3_fp_save_offset]), + .din(cp3_fp_save_d), + .dout(cp3_fp_save_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_ap_save_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp3_ap_save_offset]), + .scout(sov[cp3_ap_save_offset]), + .din(cp3_ap_save_d), + .dout(cp3_ap_save_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_spv_save_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp3_spv_save_offset]), + .scout(sov[cp3_spv_save_offset]), + .din(cp3_spv_save_d), + .dout(cp3_spv_save_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_epid_save_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp3_epid_save_offset]), + .scout(sov[cp3_epid_save_offset]), + .din(cp3_epid_save_d), + .dout(cp3_epid_save_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_async_hold_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .force_t(func_slp_sl_force), + .scin(siv[cp3_async_hold_offset]), + .scout(sov[cp3_async_hold_offset]), + .din(cp3_async_hold_d), + .dout(cp3_async_hold_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_flush_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .force_t(func_slp_sl_force), + .scin(siv[cp2_flush_offset]), + .scout(sov[cp2_flush_offset]), + .din(cp1_flush), + .dout(cp2_flush_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_flush_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .force_t(func_slp_sl_force), + .scin(siv[cp3_flush_offset]), + .scout(sov[cp3_flush_offset]), + .din(cp3_flush_d), + .dout(cp3_flush_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp4_flush_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .force_t(func_slp_sl_force), + .scin(siv[cp4_flush_offset]), + .scout(sov[cp4_flush_offset]), + .din(cp3_flush_q), + .dout(cp4_flush_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_rfi_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp3_rfi_offset]), + .scout(sov[cp3_rfi_offset]), + .din(cp2_rfi), + .dout(cp3_rfi_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_attn_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp3_attn_offset]), + .scout(sov[cp3_attn_offset]), + .din(cp2_attn), + .dout(cp3_attn_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_sc_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp3_sc_offset]), + .scout(sov[cp3_sc_offset]), + .din(cp2_sc), + .dout(cp3_sc_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_icmp_block_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp3_icmp_block_offset]), + .scout(sov[cp3_icmp_block_offset]), + .din(cp2_icmp_block), + .dout(cp3_icmp_block_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_flush2ucode_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp3_flush2ucode_offset]), + .scout(sov[cp3_flush2ucode_offset]), + .din(cp2_flush2ucode), + .dout(cp3_flush2ucode_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_flush2ucode_type_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp3_flush2ucode_type_offset]), + .scout(sov[cp3_flush2ucode_type_offset]), + .din(cp2_flush2ucode_type), + .dout(cp3_flush2ucode_type_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_flush_nonspec_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp3_flush_nonspec_offset]), + .scout(sov[cp3_flush_nonspec_offset]), + .din(cp2_flush_nonspec), + .dout(cp3_flush_nonspec_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_mispredict_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp3_mispredict_offset]), + .scout(sov[cp3_mispredict_offset]), + .din(cp2_mispredict), + .dout(cp3_mispredict_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_async_int_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .force_t(func_slp_sl_force), + .scin(siv[cp3_async_int_val_offset]), + .scout(sov[cp3_async_int_val_offset]), + .din(cp2_async_int_val_q), + .dout(cp3_async_int_val_q) + ); + + tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) cp3_async_int_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .force_t(func_slp_sl_force), + .scin(siv[cp3_async_int_offset:cp3_async_int_offset + 32 - 1]), + .scout(sov[cp3_async_int_offset:cp3_async_int_offset + 32 - 1]), + .din(cp2_async_int_q), + .dout(cp3_async_int_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_iu_excvec_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp3_iu_excvec_val_offset]), + .scout(sov[cp3_iu_excvec_val_offset]), + .din(cp2_iu_excvec_val), + .dout(cp3_iu_excvec_val_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) cp3_iu_excvec_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp3_iu_excvec_offset:cp3_iu_excvec_offset + 4 - 1]), + .scout(sov[cp3_iu_excvec_offset:cp3_iu_excvec_offset + 4 - 1]), + .din(cp2_iu_excvec), + .dout(cp3_iu_excvec_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_lq_excvec_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp3_lq_excvec_val_offset]), + .scout(sov[cp3_lq_excvec_val_offset]), + .din(cp2_lq_excvec_val), + .dout(cp3_lq_excvec_val_q) + ); + + tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) cp3_lq_excvec_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp3_lq_excvec_offset:cp3_lq_excvec_offset + 6 - 1]), + .scout(sov[cp3_lq_excvec_offset:cp3_lq_excvec_offset + 6 - 1]), + .din(cp2_lq_excvec), + .dout(cp3_lq_excvec_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_xu_excvec_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp3_xu_excvec_val_offset]), + .scout(sov[cp3_xu_excvec_val_offset]), + .din(cp2_xu_excvec_val), + .dout(cp3_xu_excvec_val_q) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) cp3_xu_excvec_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp3_xu_excvec_offset:cp3_xu_excvec_offset + 5 - 1]), + .scout(sov[cp3_xu_excvec_offset:cp3_xu_excvec_offset + 5 - 1]), + .din(cp2_xu_excvec), + .dout(cp3_xu_excvec_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_axu_excvec_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp3_axu_excvec_val_offset]), + .scout(sov[cp3_axu_excvec_val_offset]), + .din(cp2_axu_excvec_val), + .dout(cp3_axu_excvec_val_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) cp3_axu_excvec_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp3_axu_excvec_offset:cp3_axu_excvec_offset + 4 - 1]), + .scout(sov[cp3_axu_excvec_offset:cp3_axu_excvec_offset + 4 - 1]), + .din(cp2_axu_excvec), + .dout(cp3_axu_excvec_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_db_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp3_db_val_offset]), + .scout(sov[cp3_db_val_offset]), + .din(cp2_db_val), + .dout(cp3_db_val_q) + ); + + tri_rlmreg_p #(.WIDTH(19), .INIT(0), .NEEDS_SRESET(1)) cp3_db_events_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp3_db_events_offset:cp3_db_events_offset + 19 - 1]), + .scout(sov[cp3_db_events_offset:cp3_db_events_offset + 19 - 1]), + .din(cp2_db_events), + .dout(cp3_db_events_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_ld_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp3_ld_offset]), + .scout(sov[cp3_ld_offset]), + .din(cp2_ld), + .dout(cp3_ld_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_st_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp3_st_offset]), + .scout(sov[cp3_st_offset]), + .din(cp2_st), + .dout(cp3_st_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_fp_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp3_fp_offset]), + .scout(sov[cp3_fp_offset]), + .din(cp2_fp), + .dout(cp3_fp_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_ap_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp3_ap_offset]), + .scout(sov[cp3_ap_offset]), + .din(cp2_ap), + .dout(cp3_ap_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_spv_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp3_spv_offset]), + .scout(sov[cp3_spv_offset]), + .din(cp2_spv), + .dout(cp3_spv_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_epid_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp3_epid_offset]), + .scout(sov[cp3_epid_offset]), + .din(cp2_epid), + .dout(cp3_epid_q) + ); + + tri_rlmreg_p #(.WIDTH(19), .INIT(0), .NEEDS_SRESET(1)) cp3_ifar_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp3_ifar_offset:cp3_ifar_offset + 18]), + .scout(sov[cp3_ifar_offset:cp3_ifar_offset + 18]), + .din(cp2_ifar), + .dout(cp3_ifar_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_np1_flush_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp3_np1_flush_offset]), + .scout(sov[cp3_np1_flush_offset]), + .din(cp2_np1_flush), + .dout(cp3_np1_flush_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_ucode_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp3_ucode_offset]), + .scout(sov[cp3_ucode_offset]), + .din(cp2_ucode), + .dout(cp3_ucode_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_preissue_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp3_preissue_offset]), + .scout(sov[cp3_preissue_offset]), + .din(cp2_preissue), + .dout(cp3_preissue_q) + ); + + + generate + begin : xhdl6 + genvar i; + for (i = 0; i < `EFF_IFAR_ARCH; i = i + 1) + begin : q_depth_gen + if((62-`EFF_IFAR_ARCH+i) > 31) + tri_rlmlatch_p #(.INIT(1), .NEEDS_SRESET(1)) cp3_nia_a_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp3_nia_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp3_nia_offset + i]), + .scout(sov[cp3_nia_offset + i]), + .din(cp2_nia[(62-`EFF_IFAR_ARCH+i)]), + .dout(cp3_nia_q[(62-`EFF_IFAR_ARCH+i)]) + ); + else + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_nia_a_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp3_nia_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp3_nia_offset + i]), + .scout(sov[cp3_nia_offset + i]), + .din(cp2_nia[(62-`EFF_IFAR_ARCH+i)]), + .dout(cp3_nia_q[(62-`EFF_IFAR_ARCH+i)]) + ); + end + end + endgenerate + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp4_rfi_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp4_rfi_offset]), + .scout(sov[cp4_rfi_offset]), + .din(cp3_rfi), + .dout(cp4_rfi_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp5_rfi_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp5_rfi_offset]), + .scout(sov[cp5_rfi_offset]), + .din(cp4_rfi_q), + .dout(cp5_rfi_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp6_rfi_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp6_rfi_offset]), + .scout(sov[cp6_rfi_offset]), + .din(cp5_rfi_q), + .dout(cp6_rfi_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp7_rfi_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp7_rfi_offset]), + .scout(sov[cp7_rfi_offset]), + .din(cp6_rfi_q), + .dout(cp7_rfi_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp8_rfi_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp8_rfi_offset]), + .scout(sov[cp8_rfi_offset]), + .din(cp7_rfi_q), + .dout(cp8_rfi_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp4_exc_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .force_t(func_slp_sl_force), + .scin(siv[cp4_exc_val_offset]), + .scout(sov[cp4_exc_val_offset]), + .din(cp3_excvec_val), + .dout(cp4_excvec_val_q) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) flush_hold_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .force_t(func_slp_sl_force), + .scin(siv[flush_hold_offset:flush_hold_offset + 1]), + .scout(sov[flush_hold_offset:flush_hold_offset + 1]), + .din(flush_hold_d), + .dout(flush_hold_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp4_dp_cp_async_flush_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .force_t(func_slp_sl_force), + .scin(siv[cp4_dp_cp_async_flush_offset]), + .scout(sov[cp4_dp_cp_async_flush_offset]), + .din(cp3_dp_cp_async_flush), + .dout(cp4_dp_cp_async_flush_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp4_dp_cp_async_bus_snoop_flush_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .force_t(func_slp_sl_force), + .scin(siv[cp4_dp_cp_async_bus_snoop_flush_offset]), + .scout(sov[cp4_dp_cp_async_bus_snoop_flush_offset]), + .din(cp3_dp_cp_async_bus_snoop_flush), + .dout(cp4_dp_cp_async_bus_snoop_flush_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp4_async_np1_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .force_t(func_slp_sl_force), + .scin(siv[cp4_async_np1_offset]), + .scout(sov[cp4_async_np1_offset]), + .din(cp3_async_np1), + .dout(cp4_async_np1_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp4_async_n_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .force_t(func_slp_sl_force), + .scin(siv[cp4_async_n_offset]), + .scout(sov[cp4_async_n_offset]), + .din(cp3_async_n), + .dout(cp4_async_n_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp4_pc_stop_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp4_pc_stop_offset]), + .scout(sov[cp4_pc_stop_offset]), + .din(cp3_pc_stop), + .dout(cp4_pc_stop_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pc_stop_hold_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[pc_stop_hold_offset]), + .scout(sov[pc_stop_hold_offset]), + .din(pc_stop_hold_d), + .dout(pc_stop_hold_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp4_mchk_disabled_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp4_mchk_disabled_offset]), + .scout(sov[cp4_mchk_disabled_offset]), + .din(cp3_mchk_disabled), + .dout(cp4_mchk_disabled_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp4_mc_int_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp4_mc_int_offset]), + .scout(sov[cp4_mc_int_offset]), + .din(cp3_mc_int), + .dout(cp4_mc_int_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp4_g_int_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp4_g_int_offset]), + .scout(sov[cp4_g_int_offset]), + .din(cp3_g_int), + .dout(cp4_g_int_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp4_c_int_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp4_c_int_offset]), + .scout(sov[cp4_c_int_offset]), + .din(cp3_c_int), + .dout(cp4_c_int_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp4_dbell_int_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp4_dbell_int_offset]), + .scout(sov[cp4_dbell_int_offset]), + .din(cp3_dbell_int), + .dout(cp4_dbell_int_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp4_cdbell_int_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp4_cdbell_int_offset]), + .scout(sov[cp4_cdbell_int_offset]), + .din(cp3_cdbell_int), + .dout(cp4_cdbell_int_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp4_gdbell_int_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp4_gdbell_int_offset]), + .scout(sov[cp4_gdbell_int_offset]), + .din(cp3_gdbell_int), + .dout(cp4_gdbell_int_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp4_gcdbell_int_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp4_gcdbell_int_offset]), + .scout(sov[cp4_gcdbell_int_offset]), + .din(cp3_gcdbell_int), + .dout(cp4_gcdbell_int_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp4_gmcdbell_int_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp4_gmcdbell_int_offset]), + .scout(sov[cp4_gmcdbell_int_offset]), + .din(cp3_gmcdbell_int), + .dout(cp4_gmcdbell_int_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp4_dbsr_update_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp4_dbsr_update_offset]), + .scout(sov[cp4_dbsr_update_offset]), + .din(cp3_dbsr_update), + .dout(cp4_dbsr_update_q) + ); + + tri_rlmreg_p #(.WIDTH(19), .INIT(0), .NEEDS_SRESET(1)) cp4_dbsr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp4_dbsr_offset:cp4_dbsr_offset + 19 - 1]), + .scout(sov[cp4_dbsr_offset:cp4_dbsr_offset + 19 - 1]), + .din(cp3_dbsr), + .dout(cp4_dbsr_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp4_eheir_update_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp4_eheir_update_offset]), + .scout(sov[cp4_eheir_update_offset]), + .din(cp3_eheir_update), + .dout(cp4_eheir_update_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp4_esr_update_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp4_esr_update_offset]), + .scout(sov[cp4_esr_update_offset]), + .din(cp3_esr_update), + .dout(cp4_esr_update_q) + ); + + tri_rlmreg_p #(.WIDTH(17), .INIT(0), .NEEDS_SRESET(1)) cp4_exc_esr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp4_exc_esr_offset:cp4_exc_esr_offset + 17 - 1]), + .scout(sov[cp4_exc_esr_offset:cp4_exc_esr_offset + 17 - 1]), + .din(cp3_exc_esr), + .dout(cp4_exc_esr_q) + ); + + tri_rlmreg_p #(.WIDTH(15), .INIT(0), .NEEDS_SRESET(1)) cp4_exc_mcsr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp4_exc_mcsr_offset:cp4_exc_mcsr_offset + 15 - 1]), + .scout(sov[cp4_exc_mcsr_offset:cp4_exc_mcsr_offset + 15 - 1]), + .din(cp3_exc_mcsr), + .dout(cp4_exc_mcsr_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp4_asyn_irpt_needed_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp4_asyn_irpt_needed_offset]), + .scout(sov[cp4_asyn_irpt_needed_offset]), + .din(cp4_asyn_irpt_needed_d), + .dout(cp4_asyn_irpt_needed_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp4_asyn_icmp_needed_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp4_asyn_icmp_needed_offset]), + .scout(sov[cp4_asyn_icmp_needed_offset]), + .din(cp4_asyn_icmp_needed_d), + .dout(cp4_asyn_icmp_needed_q) + ); + + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0), .NEEDS_SRESET(1)) cp4_exc_nia_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp3_excvec_val), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp4_exc_nia_offset:cp4_exc_nia_offset + `EFF_IFAR_ARCH - 1]), + .scout(sov[cp4_exc_nia_offset:cp4_exc_nia_offset + `EFF_IFAR_ARCH - 1]), + .din(cp3_exc_nia), + .dout(cp4_exc_nia_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp4_dear_update_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp4_dear_update_offset]), + .scout(sov[cp4_dear_update_offset]), + .din(cp3_dear_update), + .dout(cp4_dear_update_q) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) cp_next_itag_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp_next_itag_offset:cp_next_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[cp_next_itag_offset:cp_next_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(cp_next_itag_d), + .dout(cp_next_itag_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pc_iu_init_reset_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[pc_iu_init_reset_offset]), + .scout(sov[pc_iu_init_reset_offset]), + .din(pc_iu_init_reset), + .dout(pc_iu_init_reset_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_iu_np1_async_flush_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[np1_async_flush_offset]), + .scout(sov[np1_async_flush_offset]), + .din(np1_async_flush_d), + .dout(np1_async_flush_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dp_cp_hold_req_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .force_t(func_slp_sl_force), + .scin(siv[dp_cp_async_flush_offset]), + .scout(sov[dp_cp_async_flush_offset]), + .din(dp_cp_async_flush_d), + .dout(dp_cp_async_flush_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dp_cp_bus_snoop_hold_req_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .force_t(func_slp_sl_force), + .scin(siv[dp_cp_async_bus_snoop_flush_offset]), + .scout(sov[dp_cp_async_bus_snoop_flush_offset]), + .din(dp_cp_async_bus_snoop_flush_d), + .dout(dp_cp_async_bus_snoop_flush_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) msr_de_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp2_msr_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[msr_de_offset]), + .scout(sov[msr_de_offset]), + .din(xu_iu_msr_de), + .dout(msr_de_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) msr_pr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp2_msr_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[msr_pr_offset]), + .scout(sov[msr_pr_offset]), + .din(xu_iu_msr_pr), + .dout(msr_pr_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) msr_cm_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp2_msr_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[msr_cm_offset]), + .scout(sov[msr_cm_offset]), + .din(xu_iu_msr_cm), + .dout(msr_cm_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) msr_cm_noact_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[msr_cm_noact_offset]), + .scout(sov[msr_cm_noact_offset]), + .din(xu_iu_msr_cm), + .dout(msr_cm_noact_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) msr_gs_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp2_msr_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[msr_gs_offset]), + .scout(sov[msr_gs_offset]), + .din(xu_iu_msr_gs), + .dout(msr_gs_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) msr_me_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp2_msr_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[msr_me_offset]), + .scout(sov[msr_me_offset]), + .din(xu_iu_msr_me), + .dout(msr_me_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dbcr0_edm_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[dbcr0_edm_offset]), + .scout(sov[dbcr0_edm_offset]), + .din(xu_iu_dbcr0_edm), + .dout(dbcr0_edm_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dbcr0_idm_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp2_complete_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[dbcr0_idm_offset]), + .scout(sov[dbcr0_idm_offset]), + .din(xu_iu_dbcr0_idm), + .dout(dbcr0_idm_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dbcr0_icmp_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp2_complete_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[dbcr0_icmp_offset]), + .scout(sov[dbcr0_icmp_offset]), + .din(xu_iu_dbcr0_icmp), + .dout(dbcr0_icmp_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dbcr0_brt_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp2_complete_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[dbcr0_brt_offset]), + .scout(sov[dbcr0_brt_offset]), + .din(xu_iu_dbcr0_brt), + .dout(dbcr0_brt_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dbcr0_irpt_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp2_complete_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[dbcr0_irpt_offset]), + .scout(sov[dbcr0_irpt_offset]), + .din(xu_iu_dbcr0_irpt), + .dout(dbcr0_irpt_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dbcr0_trap_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp2_complete_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[dbcr0_trap_offset]), + .scout(sov[dbcr0_trap_offset]), + .din(xu_iu_dbcr0_trap), + .dout(dbcr0_trap_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iac1_en_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp2_complete_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[iac1_en_offset]), + .scout(sov[iac1_en_offset]), + .din(xu_iu_iac1_en), + .dout(iac1_en_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iac2_en_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp2_complete_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[iac2_en_offset]), + .scout(sov[iac2_en_offset]), + .din(xu_iu_iac2_en), + .dout(iac2_en_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iac3_en_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp2_complete_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[iac3_en_offset]), + .scout(sov[iac3_en_offset]), + .din(xu_iu_iac3_en), + .dout(iac3_en_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iac4_en_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp2_complete_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[iac4_en_offset]), + .scout(sov[iac4_en_offset]), + .din(xu_iu_iac4_en), + .dout(iac4_en_q) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) dbcr0_dac1_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp2_complete_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[dbcr0_dac1_offset:dbcr0_dac1_offset + 2 - 1]), + .scout(sov[dbcr0_dac1_offset:dbcr0_dac1_offset + 2 - 1]), + .din(xu_iu_dbcr0_dac1), + .dout(dbcr0_dac1_q) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) dbcr0_dac2_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp2_complete_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[dbcr0_dac2_offset:dbcr0_dac2_offset + 2 - 1]), + .scout(sov[dbcr0_dac2_offset:dbcr0_dac2_offset + 2 - 1]), + .din(xu_iu_dbcr0_dac2), + .dout(dbcr0_dac2_q) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) dbcr0_dac3_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp2_complete_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[dbcr0_dac3_offset:dbcr0_dac3_offset + 2 - 1]), + .scout(sov[dbcr0_dac3_offset:dbcr0_dac3_offset + 2 - 1]), + .din(xu_iu_dbcr0_dac3), + .dout(dbcr0_dac3_q) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) dbcr0_dac4_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp2_complete_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[dbcr0_dac4_offset:dbcr0_dac4_offset + 2 - 1]), + .scout(sov[dbcr0_dac4_offset:dbcr0_dac4_offset + 2 - 1]), + .din(xu_iu_dbcr0_dac4), + .dout(dbcr0_dac4_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dbcr0_ret_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp2_complete_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[dbcr0_ret_offset]), + .scout(sov[dbcr0_ret_offset]), + .din(xu_iu_dbcr0_ret), + .dout(dbcr0_ret_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dbcr1_iac12m_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp2_complete_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[dbcr1_iac12m_offset]), + .scout(sov[dbcr1_iac12m_offset]), + .din(xu_iu_dbcr1_iac12m), + .dout(dbcr1_iac12m_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dbcr1_iac34m_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp2_complete_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[dbcr1_iac34m_offset]), + .scout(sov[dbcr1_iac34m_offset]), + .din(xu_iu_dbcr1_iac34m), + .dout(dbcr1_iac34m_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dbcr3_ivc_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp2_complete_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[dbcr3_ivc_offset]), + .scout(sov[dbcr3_ivc_offset]), + .din(lq_iu_spr_dbcr3_ivc), + .dout(dbcr3_ivc_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) epcr_extgs_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp2_complete_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[epcr_extgs_offset]), + .scout(sov[epcr_extgs_offset]), + .din(xu_iu_epcr_extgs), + .dout(epcr_extgs_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) epcr_dtlbgs_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp2_complete_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[epcr_dtlbgs_offset]), + .scout(sov[epcr_dtlbgs_offset]), + .din(xu_iu_epcr_dtlbgs), + .dout(epcr_dtlbgs_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) epcr_itlbgs_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp2_complete_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[epcr_itlbgs_offset]), + .scout(sov[epcr_itlbgs_offset]), + .din(xu_iu_epcr_itlbgs), + .dout(epcr_itlbgs_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) epcr_dsigs_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp2_complete_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[epcr_dsigs_offset]), + .scout(sov[epcr_dsigs_offset]), + .din(xu_iu_epcr_dsigs), + .dout(epcr_dsigs_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) epcr_isigs_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp2_complete_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[epcr_isigs_offset]), + .scout(sov[epcr_isigs_offset]), + .din(xu_iu_epcr_isigs), + .dout(epcr_isigs_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) epcr_duvd_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp2_complete_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[epcr_duvd_offset]), + .scout(sov[epcr_duvd_offset]), + .din(xu_iu_epcr_duvd), + .dout(epcr_duvd_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) epcr_icm_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp2_complete_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[epcr_icm_offset]), + .scout(sov[epcr_icm_offset]), + .din(xu_iu_epcr_icm), + .dout(epcr_icm_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) epcr_gicm_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp2_complete_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[epcr_gicm_offset]), + .scout(sov[epcr_gicm_offset]), + .din(xu_iu_epcr_gicm), + .dout(epcr_gicm_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ccr2_ucode_dis_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp2_complete_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[ccr2_ucode_dis_offset]), + .scout(sov[ccr2_ucode_dis_offset]), + .din(xu_iu_ccr2_ucode_dis), + .dout(ccr2_ucode_dis_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mmu_mode_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp2_complete_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[ccr2_mmu_mode_offset]), + .scout(sov[ccr2_mmu_mode_offset]), + .din(xu_iu_hid_mmu_mode), + .dout(ccr2_mmu_mode_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_iu_xucr4_mmu_mchk_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp2_complete_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[xu_iu_xucr4_mmu_mchk_offset]), + .scout(sov[xu_iu_xucr4_mmu_mchk_offset]), + .din(xu_iu_xucr4_mmu_mchk), + .dout(xu_iu_xucr4_mmu_mchk_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pc_iu_ram_active_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[pc_iu_ram_active_offset]), + .scout(sov[pc_iu_ram_active_offset]), + .din(pc_iu_ram_active), + .dout(pc_iu_ram_active_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pc_iu_ram_flush_thread_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[pc_iu_ram_flush_thread_offset]), + .scout(sov[pc_iu_ram_flush_thread_offset]), + .din(pc_iu_ram_flush_thread), + .dout(pc_iu_ram_flush_thread_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_iu_msrovride_enab_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[xu_iu_msrovride_enab_offset]), + .scout(sov[xu_iu_msrovride_enab_offset]), + .din(xu_iu_msrovride_enab), + .dout(xu_iu_msrovride_enab_q) + ); + + tri_rlmlatch_p #(.INIT(1), .NEEDS_SRESET(1)) pc_iu_stop_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[pc_iu_stop_offset]), + .scout(sov[pc_iu_stop_offset]), + .din(pc_iu_stop_d), + .dout(pc_iu_stop_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pc_iu_step_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[pc_iu_step_offset]), + .scout(sov[pc_iu_step_offset]), + .din(pc_iu_step), + .dout(pc_iu_step_q) + ); + + tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) spr_perf_mux_ctrls_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[spr_perf_mux_ctrls_offset:spr_perf_mux_ctrls_offset + 16 - 1]), + .scout(sov[spr_perf_mux_ctrls_offset:spr_perf_mux_ctrls_offset + 16 - 1]), + .din(spr_cp_perf_event_mux_ctrls), + .dout(spr_perf_mux_ctrls_q) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) pc_iu_dbg_action_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[pc_iu_dbg_action_offset:pc_iu_dbg_action_offset + 3 - 1]), + .scout(sov[pc_iu_dbg_action_offset:pc_iu_dbg_action_offset + 3 - 1]), + .din(pc_iu_dbg_action), + .dout(pc_iu_dbg_action_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_iu_single_instr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp2_complete_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[xu_iu_single_instr_offset]), + .scout(sov[xu_iu_single_instr_offset]), + .din(xu_iu_single_instr_mode), + .dout(xu_iu_single_instr_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_single_issue_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp2_complete_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[spr_single_issue_offset]), + .scout(sov[spr_single_issue_offset]), + .din(spr_single_issue), + .dout(spr_single_issue_q) + ); + + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH-12), .INIT(0), .NEEDS_SRESET(1)) spr_ivpr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp2_complete_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[spr_ivpr_offset:spr_ivpr_offset + (`GPR_WIDTH-12) - 1]), + .scout(sov[spr_ivpr_offset:spr_ivpr_offset + (`GPR_WIDTH-12) - 1]), + .din(spr_ivpr), + .dout(spr_ivpr_q) + ); + + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH-12), .INIT(0), .NEEDS_SRESET(1)) spr_givpr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp2_complete_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[spr_givpr_offset:spr_givpr_offset + (`GPR_WIDTH-12) - 1]), + .scout(sov[spr_givpr_offset:spr_givpr_offset + (`GPR_WIDTH-12) - 1]), + .din(spr_givpr), + .dout(spr_givpr_q) + ); + + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0), .NEEDS_SRESET(1)) spr_iac1_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp2_complete_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[spr_iac1_offset:spr_iac1_offset + `EFF_IFAR_ARCH - 1]), + .scout(sov[spr_iac1_offset:spr_iac1_offset + `EFF_IFAR_ARCH - 1]), + .din(spr_iac1), + .dout(spr_iac1_q) + ); + + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0), .NEEDS_SRESET(1)) spr_iac2_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp2_complete_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[spr_iac2_offset:spr_iac2_offset + `EFF_IFAR_ARCH - 1]), + .scout(sov[spr_iac2_offset:spr_iac2_offset + `EFF_IFAR_ARCH - 1]), + .din(spr_iac2), + .dout(spr_iac2_q) + ); + + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0), .NEEDS_SRESET(1)) spr_iac3_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp2_complete_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[spr_iac3_offset:spr_iac3_offset + `EFF_IFAR_ARCH - 1]), + .scout(sov[spr_iac3_offset:spr_iac3_offset + `EFF_IFAR_ARCH - 1]), + .din(spr_iac3), + .dout(spr_iac3_q) + ); + + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0), .NEEDS_SRESET(1)) spr_iac4_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cp2_complete_act), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[spr_iac4_offset:spr_iac4_offset + `EFF_IFAR_ARCH - 1]), + .scout(sov[spr_iac4_offset:spr_iac4_offset + `EFF_IFAR_ARCH - 1]), + .din(spr_iac4), + .dout(spr_iac4_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_pc_step_done_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[iu_pc_step_done_offset]), + .scout(sov[iu_pc_step_done_offset]), + .din(iu_pc_step_done_d), + .dout(iu_pc_step_done_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) uncond_dbg_event_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[uncond_dbg_event_offset]), + .scout(sov[uncond_dbg_event_offset]), + .din(an_ac_uncond_dbg_event), + .dout(uncond_dbg_event_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) external_mchk_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[external_mchk_offset]), + .scout(sov[external_mchk_offset]), + .din(xu_iu_external_mchk), + .dout(external_mchk_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ext_int_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[ext_interrupt_offset]), + .scout(sov[ext_interrupt_offset]), + .din(xu_iu_ext_interrupt), + .dout(ext_interrupt_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dec_int_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[dec_interrupt_offset]), + .scout(sov[dec_interrupt_offset]), + .din(xu_iu_dec_interrupt), + .dout(dec_interrupt_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) udec_int_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[udec_interrupt_offset]), + .scout(sov[udec_interrupt_offset]), + .din(xu_iu_udec_interrupt), + .dout(udec_interrupt_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) perf_int_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[perf_interrupt_offset]), + .scout(sov[perf_interrupt_offset]), + .din(xu_iu_perf_interrupt), + .dout(perf_interrupt_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) fit_int_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[fit_interrupt_offset]), + .scout(sov[fit_interrupt_offset]), + .din(xu_iu_fit_interrupt), + .dout(fit_interrupt_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) crit_int_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[crit_interrupt_offset]), + .scout(sov[crit_interrupt_offset]), + .din(xu_iu_crit_interrupt), + .dout(crit_interrupt_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) wdog_int_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[wdog_interrupt_offset]), + .scout(sov[wdog_interrupt_offset]), + .din(xu_iu_wdog_interrupt), + .dout(wdog_interrupt_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) gwdog_int_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[gwdog_interrupt_offset]), + .scout(sov[gwdog_interrupt_offset]), + .din(xu_iu_gwdog_interrupt), + .dout(gwdog_interrupt_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) gfit_int_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[gfit_interrupt_offset]), + .scout(sov[gfit_interrupt_offset]), + .din(xu_iu_gfit_interrupt), + .dout(gfit_interrupt_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) gdec_int_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[gdec_interrupt_offset]), + .scout(sov[gdec_interrupt_offset]), + .din(xu_iu_gdec_interrupt), + .dout(gdec_interrupt_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dbell_int_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[dbell_interrupt_offset]), + .scout(sov[dbell_interrupt_offset]), + .din(xu_iu_dbell_interrupt), + .dout(dbell_interrupt_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cdbell_int_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cdbell_interrupt_offset]), + .scout(sov[cdbell_interrupt_offset]), + .din(xu_iu_cdbell_interrupt), + .dout(cdbell_interrupt_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) gdbell_int_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[gdbell_interrupt_offset]), + .scout(sov[gdbell_interrupt_offset]), + .din(xu_iu_gdbell_interrupt), + .dout(gdbell_interrupt_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) gcdbell_int_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[gcdbell_interrupt_offset]), + .scout(sov[gcdbell_interrupt_offset]), + .din(xu_iu_gcdbell_interrupt), + .dout(gcdbell_interrupt_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) gmcdbell_int_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[gmcdbell_interrupt_offset]), + .scout(sov[gmcdbell_interrupt_offset]), + .din(xu_iu_gmcdbell_interrupt), + .dout(gmcdbell_interrupt_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dbsr_int_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[dbsr_interrupt_offset]), + .scout(sov[dbsr_interrupt_offset]), + .din(xu_iu_dbsr_ide), + .dout(dbsr_interrupt_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) fex_int_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[fex_interrupt_offset]), + .scout(sov[fex_interrupt_offset]), + .din(axu0_iu_async_fex), + .dout(fex_interrupt_q) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) async_delay_cnt_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .force_t(func_slp_sl_force), + .scin(siv[async_delay_cnt_offset:async_delay_cnt_offset + 3 - 1]), + .scout(sov[async_delay_cnt_offset:async_delay_cnt_offset + 3 - 1]), + .din(async_delay_cnt_d), + .dout(async_delay_cnt_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_lq_recirc_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[iu_lq_recirc_val_offset]), + .scout(sov[iu_lq_recirc_val_offset]), + .din(iu_lq_recirc_val_d), + .dout(iu_lq_recirc_val_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ext_dbg_stop_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[ext_dbg_stop_offset]), + .scout(sov[ext_dbg_stop_offset]), + .din(ext_dbg_stop_d), + .dout(ext_dbg_stop_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ext_dbg_stop_other_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[ext_dbg_stop_other_offset]), + .scout(sov[ext_dbg_stop_other_offset]), + .din(ext_dbg_stop_other_d), + .dout(ext_dbg_stop_other_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ext_dbg_act_err_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[ext_dbg_act_err_offset]), + .scout(sov[ext_dbg_act_err_offset]), + .din(ext_dbg_act_err_d), + .dout(ext_dbg_act_err_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ext_dbg_act_ext_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[ext_dbg_act_ext_offset]), + .scout(sov[ext_dbg_act_ext_offset]), + .din(ext_dbg_act_ext_d), + .dout(ext_dbg_act_ext_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dbg_int_en_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[dbg_int_en_offset]), + .scout(sov[dbg_int_en_offset]), + .din(dbg_int_en_d), + .dout(dbg_int_en_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dbg_event_en_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[dbg_event_en_offset]), + .scout(sov[dbg_event_en_offset]), + .din(dbg_event_en_d), + .dout(dbg_event_en_q) + ); + + tri_rlmreg_p #(.WIDTH(`CPL_Q_DEPTH), .INIT(0), .NEEDS_SRESET(1)) cp1_i0_dispatched_delay_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp1_i0_dispatched_offset:cp1_i0_dispatched_offset + `CPL_Q_DEPTH - 1]), + .scout(sov[cp1_i0_dispatched_offset:cp1_i0_dispatched_offset + `CPL_Q_DEPTH - 1]), + .din(cp1_i0_dispatched_delay_d), + .dout(cp1_i0_dispatched_delay_q) + ); + + tri_rlmreg_p #(.WIDTH(`CPL_Q_DEPTH), .INIT(0), .NEEDS_SRESET(1)) cp1_i1_dispatched_delay_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp1_i1_dispatched_offset:cp1_i1_dispatched_offset + `CPL_Q_DEPTH - 1]), + .scout(sov[cp1_i1_dispatched_offset:cp1_i1_dispatched_offset + `CPL_Q_DEPTH - 1]), + .din(cp1_i1_dispatched_delay_d), + .dout(cp1_i1_dispatched_delay_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu7_i0_is_folded_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[iu7_i0_is_folded_offset]), + .scout(sov[iu7_i0_is_folded_offset]), + .din(iu7_i0_is_folded_d), + .dout(iu7_i0_is_folded_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu7_i1_is_folded_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[iu7_i1_is_folded_offset]), + .scout(sov[iu7_i1_is_folded_offset]), + .din(iu7_i1_is_folded_d), + .dout(iu7_i1_is_folded_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) select_reset_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[select_reset_offset]), + .scout(sov[select_reset_offset]), + .din(select_reset), + .dout(select_reset_q) + ); + + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0), .NEEDS_SRESET(1)) xu_iu_rest_ifar_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(select_reset), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[xu_iu_rest_ifar_offset:xu_iu_rest_ifar_offset + `EFF_IFAR_ARCH - 1]), + .scout(sov[xu_iu_rest_ifar_offset:xu_iu_rest_ifar_offset + `EFF_IFAR_ARCH - 1]), + .din(xu_iu_rest_ifar), + .dout(xu_iu_rest_ifar_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) attn_hold_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[attn_hold_offset]), + .scout(sov[attn_hold_offset]), + .din(attn_hold_d), + .dout(attn_hold_q) + ); + assign flush_delay_d = {flush_cond, flush_delay_q[0]}; + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) flush_delay_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .force_t(func_slp_sl_force), + .scin(siv[flush_delay_offset:flush_delay_offset + 2 - 1]), + .scout(sov[flush_delay_offset:flush_delay_offset + 2 - 1]), + .din(flush_delay_d), + .dout(flush_delay_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_nonspec_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[iu_nonspec_offset]), + .scout(sov[iu_nonspec_offset]), + .din(iu_nonspec_d), + .dout(iu_nonspec_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ierat_pt_fault_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[ierat_pt_fault_offset]), + .scout(sov[ierat_pt_fault_offset]), + .din(ierat_pt_fault_d), + .dout(ierat_pt_fault_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ierat_lrat_miss_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[ierat_lrat_miss_offset]), + .scout(sov[ierat_lrat_miss_offset]), + .din(ierat_lrat_miss_d), + .dout(ierat_lrat_miss_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ierat_tlb_inelig_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[ierat_tlb_inelig_offset]), + .scout(sov[ierat_tlb_inelig_offset]), + .din(ierat_tlb_inelig_d), + .dout(ierat_tlb_inelig_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_multihit_err_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[tlb_multihit_err_offset]), + .scout(sov[tlb_multihit_err_offset]), + .din(tlb_multihit_err_d), + .dout(tlb_multihit_err_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_par_err_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[tlb_par_err_offset]), + .scout(sov[tlb_par_err_offset]), + .din(tlb_par_err_d), + .dout(tlb_par_err_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lru_par_err_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[lru_par_err_offset]), + .scout(sov[lru_par_err_offset]), + .din(lru_par_err_d), + .dout(lru_par_err_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_miss_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[tlb_miss_offset]), + .scout(sov[tlb_miss_offset]), + .din(tlb_miss_d), + .dout(tlb_miss_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) reload_hit_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[reload_hit_offset]), + .scout(sov[reload_hit_offset]), + .din(reload_hit_d), + .dout(reload_hit_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) nonspec_hit_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[nonspec_hit_offset]), + .scout(sov[nonspec_hit_offset]), + .din(nonspec_hit_d), + .dout(nonspec_hit_q) + ); + + + tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) cp_mm_except_taken_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[cp_mm_except_taken_offset:cp_mm_except_taken_offset + 5]), + .scout(sov[cp_mm_except_taken_offset:cp_mm_except_taken_offset + 5]), + .din(cp_mm_except_taken_d), + .dout(cp_mm_except_taken_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) eheir_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .scin(siv[eheir_val_offset]), + .scout(sov[eheir_val_offset]), + .din(eheir_val_d), + .dout(eheir_val_q) + ); + + + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) perf_bus_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pc_iu_event_bus_enable), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(func_sl_force), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw1_dc_b), + .d_mode(d_mode_dc), + .scin(siv[perf_bus_offset:perf_bus_offset + 3]), + .scout(sov[perf_bus_offset:perf_bus_offset + 3]), + .din(event_bus_out_d), + .dout(event_bus_out_q) + ); + + + assign siv[0:scan_right - 1] = {sov[1:scan_right - 1], scan_in}; + assign scan_out = sov[0]; + +endmodule diff --git a/dev/verilog/work/iuq_cpl_ctrl_inc.v b/dev/verilog/work/iuq_cpl_ctrl_inc.v new file mode 100755 index 0000000..35db1e8 --- /dev/null +++ b/dev/verilog/work/iuq_cpl_ctrl_inc.v @@ -0,0 +1,81 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: Saturating Incrementer +// +//***************************************************************************** + +module iuq_cpl_ctrl_inc( + inc, + i, + o +); +`include "tri_a2o.vh" + parameter SIZE = 7; + parameter WRAP = 40; + input [0:1] inc; + input [0:SIZE-1] i; + + output [0:SIZE-1] o; + + wire [1:SIZE] a; + wire [1:SIZE] b; + wire [1:SIZE] rslt; + wire rollover; + wire rollover_m1; + wire inc_1; + wire inc_2; + wire [0:1] wrap_sel; + + // Increment by 1 or 2. + // Go back to zero at WRAP + // Flip bit zero when a rollover occurs + // eg 0...39, 64..103 + + assign a = {i[1:SIZE - 1], inc[1]}; + assign b = {1'b0, inc[0], inc[1]}; + assign rslt = a + b; + + assign rollover = i[1:SIZE - 1] == WRAP; + assign rollover_m1 = i[1:SIZE - 1] == WRAP - 1; + + assign inc_1 = inc[0] ^ inc[1]; + assign inc_2 = inc[0] & inc[1]; + + assign wrap_sel[0] = (rollover & inc_1) | (rollover_m1 & inc_2); + assign wrap_sel[1] = rollover & inc_2; + + assign o[0] = i[0] ^ |(wrap_sel); + + assign o[1:SIZE - 1] = (wrap_sel[0:1] == 2'b10) ? 0 : + (wrap_sel[0:1] == 2'b01) ? 1 : + rslt[1:SIZE - 1]; + +endmodule diff --git a/dev/verilog/work/iuq_cpl_dec.v b/dev/verilog/work/iuq_cpl_dec.v new file mode 100755 index 0000000..fee1c77 --- /dev/null +++ b/dev/verilog/work/iuq_cpl_dec.v @@ -0,0 +1,190 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// VHDL 1076 Macro Expander C version 07/11/00 +// job was run on Tue Feb 1 10:11:27 2011 + +//******************************************************************** +//* +//* TITLE: +//* +//* NAME: iuq_cpl_dec.v +//* +//********************************************************************* +module iuq_cpl_dec( + input [0:31] cp2_instr, + output cp2_ld, + output cp2_st, + output cp2_epid); + + wire [1:7] TBL_EPID_DEC_PT; + wire [1:41] TBL_LD_ST_PT; + //@@ START OF EXECUTABLE CODE FOR IUQ_CPL_DEC + // + // Final Table Listing + // *INPUTS*=============*OUTPUTS*=====* + // | | | + // | cp2_instr | cp2_epid | + // | | cp2_instr | | | + // | | | | | | + // | 000000 2222222223 | | | + // | 012345 1234567890 | | | + // *TYPE*===============+=============+ + // | PPPPPP PPPPPPPPPP | P | + // *POLARITY*---------->| + | + // *PHASE*------------->| T | + // *TERMS*==============+=============+ + // 1 | 011111 1110110110 | 1 | + // 2 | 011111 1111-11111 | 1 | + // 3 | 011111 00-00111-1 | 1 | + // 4 | 011111 0-00-11111 | 1 | + // 5 | 011111 -0-1011111 | 1 | + // 6 | 011111 00-1-11111 | 1 | + // 7 | 011111 0--0011111 | 1 | + // *==================================* + // + // Table TBL_EPID_DEC Signal Assignments for Product Terms + assign TBL_EPID_DEC_PT[1] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[23], cp2_instr[24], cp2_instr[25], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 16'b0111111110110110); + assign TBL_EPID_DEC_PT[2] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[23], cp2_instr[24], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 15'b011111111111111); + assign TBL_EPID_DEC_PT[3] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[24], cp2_instr[25], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[30]}) === 14'b01111100001111); + assign TBL_EPID_DEC_PT[4] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[23], cp2_instr[24], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 14'b01111100011111); + assign TBL_EPID_DEC_PT[5] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[22], cp2_instr[24], cp2_instr[25], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 14'b01111101011111); + assign TBL_EPID_DEC_PT[6] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[24], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 14'b01111100111111); + assign TBL_EPID_DEC_PT[7] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[24], cp2_instr[25], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 14'b01111100011111); + + // Table TBL_EPID_DEC Signal Assignments for Outputs + assign cp2_epid = (TBL_EPID_DEC_PT[1] | TBL_EPID_DEC_PT[2] | TBL_EPID_DEC_PT[3] | TBL_EPID_DEC_PT[4] | TBL_EPID_DEC_PT[5] | TBL_EPID_DEC_PT[6] | TBL_EPID_DEC_PT[7]); + // + // Final Table Listing + // *INPUTS*===========================*OUTPUTS*============* + // | | | + // | cp2_instr | | + // | | cp2_instr | | + // | | | cp2_instr | | + // | | | | cp2_instr | | + // | | | | | | cp2_ld | + // | | | | | | | cp2_st | + // | 000000 0 2222222223 33 | | | | + // | 012345 9 1234567890 01 | | | | + // *TYPE*=============================+====================+ + // | PPPPPP P PPPPPPPPPP PP | P P | + // *POLARITY*------------------------>| + + | + // *PHASE*--------------------------->| T T | + // *TERMS*============================+====================+ + // 1 | 011111 - 1-10-10110 0- | . 1 | + // 2 | 011111 - 000-01011- -- | 1 . | + // 3 | 011111 - 0-1001011- 0- | . 1 | + // 4 | 011111 - 101001010- -- | . 1 | + // 5 | 011111 - -00001010- -- | 1 . | + // 6 | 011111 - 1111111111 -- | . 1 | + // 7 | 011111 - 0-11100110 -- | 1 . | + // 8 | 011111 - 1111110110 -- | . 1 | + // 9 | 011111 - 1111011111 -- | 1 . | + // 10 | 011111 - 0101-101-1 -- | 1 . | + // 11 | 011111 - 101-010101 -- | . 1 | + // 12 | 011111 - 0110000110 -- | 1 . | + // 13 | 011111 - 001-100110 -- | 1 . | + // 14 | 011111 - 0-00-1-111 -- | 1 . | + // 15 | 011111 - 001001-1-1 -- | . 1 | + // 16 | 011111 - 0011-1-111 -- | . 1 | + // 17 | 011111 - 100-010101 -- | 1 . | + // 18 | 011111 - 00100-0110 -- | . 1 | + // 19 | 011111 - 000001-1-1 -- | 1 . | + // 20 | 011111 - 000--1-111 -- | 1 . | + // 21 | 011111 - 1-10010110 -- | . 1 | + // 22 | 011111 - 1010-10110 -- | . 1 | + // 23 | 011111 - 1111010110 -- | 1 . | + // 24 | 011111 - 0-1001-111 -- | . 1 | + // 25 | 011111 - --00010110 -- | 1 . | + // 26 | 011111 - -01-010110 -- | . 1 | + // 27 | 011111 - 0010-101-1 -- | . 1 | + // 28 | 011111 - 00-1010100 -- | 1 . | + // 29 | 011111 - 0000-101-1 -- | 1 . | + // 30 | 011111 - 0-11010110 -- | . 1 | + // 31 | 011111 - 0-10-10111 -- | . 1 | + // 32 | 011111 - 00111-0110 -- | 1 . | + // 33 | 011111 - 0000-1011- -- | 1 . | + // 34 | 10-0-- - ---------- -- | 1 . | + // 35 | 1-1010 - ---------- -0 | 1 . | + // 36 | 1-1010 - ---------- 0- | 1 . | + // 37 | 10-10- - ---------- -- | . 1 | + // 38 | 111110 - ---------- 0- | . 1 | + // 39 | 1001-- - ---------- -- | . 1 | + // 40 | 101-10 - ---------- -- | 1 . | + // 41 | 10-1-1 - ---------- -- | . 1 | + // *=======================================================* + // + // Table TBL_LD_ST Signal Assignments for Product Terms + assign TBL_LD_ST_PT[1] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[23], cp2_instr[24], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30], cp2_instr[30]}) === 15'b011111110101100); + assign TBL_LD_ST_PT[2] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[23], cp2_instr[25], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29]}) === 14'b01111100001011); + assign TBL_LD_ST_PT[3] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[23], cp2_instr[24], cp2_instr[25], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 15'b011111010010110); + assign TBL_LD_ST_PT[4] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[23], cp2_instr[24], cp2_instr[25], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29]}) === 15'b011111101001010); + assign TBL_LD_ST_PT[5] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[22], cp2_instr[23], cp2_instr[24], cp2_instr[25], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29]}) === 14'b01111100001010); + assign TBL_LD_ST_PT[6] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[23], cp2_instr[24], cp2_instr[25], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 16'b0111111111111111); + assign TBL_LD_ST_PT[7] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[23], cp2_instr[24], cp2_instr[25], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 15'b011111011100110); + assign TBL_LD_ST_PT[8] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[23], cp2_instr[24], cp2_instr[25], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 16'b0111111111110110); + assign TBL_LD_ST_PT[9] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[23], cp2_instr[24], cp2_instr[25], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 16'b0111111111011111); + assign TBL_LD_ST_PT[10] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[23], cp2_instr[24], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[30]}) === 14'b01111101011011); + assign TBL_LD_ST_PT[11] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[23], cp2_instr[25], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 15'b011111101010101); + assign TBL_LD_ST_PT[12] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[23], cp2_instr[24], cp2_instr[25], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 16'b0111110110000110); + assign TBL_LD_ST_PT[13] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[23], cp2_instr[25], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 15'b011111001100110); + assign TBL_LD_ST_PT[14] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[23], cp2_instr[24], cp2_instr[26], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 13'b0111110001111); + assign TBL_LD_ST_PT[15] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[23], cp2_instr[24], cp2_instr[25], cp2_instr[26], cp2_instr[28], cp2_instr[30]}) === 14'b01111100100111); + assign TBL_LD_ST_PT[16] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[23], cp2_instr[24], cp2_instr[26], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 14'b01111100111111); + assign TBL_LD_ST_PT[17] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[23], cp2_instr[25], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 15'b011111100010101); + assign TBL_LD_ST_PT[18] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[23], cp2_instr[24], cp2_instr[25], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 15'b011111001000110); + assign TBL_LD_ST_PT[19] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[23], cp2_instr[24], cp2_instr[25], cp2_instr[26], cp2_instr[28], cp2_instr[30]}) === 14'b01111100000111); + assign TBL_LD_ST_PT[20] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[23], cp2_instr[26], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 13'b0111110001111); + assign TBL_LD_ST_PT[21] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[23], cp2_instr[24], cp2_instr[25], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 15'b011111110010110); + assign TBL_LD_ST_PT[22] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[23], cp2_instr[24], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 15'b011111101010110); + assign TBL_LD_ST_PT[23] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[23], cp2_instr[24], cp2_instr[25], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 16'b0111111111010110); + assign TBL_LD_ST_PT[24] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[23], cp2_instr[24], cp2_instr[25], cp2_instr[26], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 14'b01111101001111); + assign TBL_LD_ST_PT[25] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[23], cp2_instr[24], cp2_instr[25], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 14'b01111100010110); + assign TBL_LD_ST_PT[26] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[22], cp2_instr[23], cp2_instr[25], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 14'b01111101010110); + assign TBL_LD_ST_PT[27] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[23], cp2_instr[24], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[30]}) === 14'b01111100101011); + assign TBL_LD_ST_PT[28] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[24], cp2_instr[25], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 15'b011111001010100); + assign TBL_LD_ST_PT[29] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[23], cp2_instr[24], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[30]}) === 14'b01111100001011); + assign TBL_LD_ST_PT[30] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[23], cp2_instr[24], cp2_instr[25], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 15'b011111011010110); + assign TBL_LD_ST_PT[31] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[23], cp2_instr[24], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 14'b01111101010111); + assign TBL_LD_ST_PT[32] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[23], cp2_instr[24], cp2_instr[25], cp2_instr[27], cp2_instr[28], cp2_instr[29], cp2_instr[30]}) === 15'b011111001110110); + assign TBL_LD_ST_PT[33] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[21], cp2_instr[22], cp2_instr[23], cp2_instr[24], cp2_instr[26], cp2_instr[27], cp2_instr[28], cp2_instr[29]}) === 14'b01111100001011); + assign TBL_LD_ST_PT[34] = (({cp2_instr[00], cp2_instr[01], cp2_instr[03]}) === 3'b100); + assign TBL_LD_ST_PT[35] = (({cp2_instr[00], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[31]}) === 6'b110100); + assign TBL_LD_ST_PT[36] = (({cp2_instr[00], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[30]}) === 6'b110100); + assign TBL_LD_ST_PT[37] = (({cp2_instr[00], cp2_instr[01], cp2_instr[03], cp2_instr[04]}) === 4'b1010); + assign TBL_LD_ST_PT[38] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03], cp2_instr[04], cp2_instr[05], cp2_instr[30]}) === 7'b1111100); + assign TBL_LD_ST_PT[39] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[03]}) === 4'b1001); + assign TBL_LD_ST_PT[40] = (({cp2_instr[00], cp2_instr[01], cp2_instr[02], cp2_instr[04], cp2_instr[05]}) === 5'b10110); + assign TBL_LD_ST_PT[41] = (({cp2_instr[00], cp2_instr[01], cp2_instr[03], cp2_instr[05]}) === 4'b1011); + // Table TBL_LD_ST Signal Assignments for Outputs + assign cp2_ld = (TBL_LD_ST_PT[2] | TBL_LD_ST_PT[5] | TBL_LD_ST_PT[7] | TBL_LD_ST_PT[9] | TBL_LD_ST_PT[10] | TBL_LD_ST_PT[12] | TBL_LD_ST_PT[13] | TBL_LD_ST_PT[14] | TBL_LD_ST_PT[17] | TBL_LD_ST_PT[19] | TBL_LD_ST_PT[20] | TBL_LD_ST_PT[23] | TBL_LD_ST_PT[25] | TBL_LD_ST_PT[28] | TBL_LD_ST_PT[29] | TBL_LD_ST_PT[32] | TBL_LD_ST_PT[33] | TBL_LD_ST_PT[34] | TBL_LD_ST_PT[35] | TBL_LD_ST_PT[36] | TBL_LD_ST_PT[40]); + assign cp2_st = (TBL_LD_ST_PT[1] | TBL_LD_ST_PT[3] | TBL_LD_ST_PT[4] | TBL_LD_ST_PT[6] | TBL_LD_ST_PT[8] | TBL_LD_ST_PT[11] | TBL_LD_ST_PT[15] | TBL_LD_ST_PT[16] | TBL_LD_ST_PT[18] | TBL_LD_ST_PT[21] | TBL_LD_ST_PT[22] | TBL_LD_ST_PT[24] | TBL_LD_ST_PT[26] | TBL_LD_ST_PT[27] | TBL_LD_ST_PT[30] | TBL_LD_ST_PT[31] | TBL_LD_ST_PT[37] | TBL_LD_ST_PT[38] | TBL_LD_ST_PT[39] | TBL_LD_ST_PT[41]); + +endmodule diff --git a/dev/verilog/work/iuq_cpl_itag.v b/dev/verilog/work/iuq_cpl_itag.v new file mode 100755 index 0000000..6193820 --- /dev/null +++ b/dev/verilog/work/iuq_cpl_itag.v @@ -0,0 +1,83 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: Saturating Incrementer +// +// Change log at bottom of this file +//***************************************************************************** + +module iuq_cpl_itag( inc, i, o); + parameter SIZE = 7; + parameter WRAP = 40; + + input [0:1] inc; + input [0:SIZE-1] i; + + output [0:SIZE-1] o; + + wire [1:SIZE] a; + wire [1:SIZE] b; + wire [1:SIZE] rslt; + wire rollover; + wire rollover_m1; + wire inc_1; + wire inc_2; + wire [0:1] wrap_sel; + + + (* analysis_not_referenced="true" *) + + wire unused; + // Increment by 1 or 2. + // Go back to zero at WRAP + // Flip bit zero when a rollover occurs + // eg 0...39, 64..103 + assign unused = rslt[SIZE]; + + assign a = {i[1:SIZE - 1], inc[1]}; + assign b = {{SIZE-2{1'b0}},{inc[0], inc[1]}}; + assign rslt = a + b; + + assign rollover = {{32-SIZE+1{1'b0}},i[1:SIZE - 1]} == WRAP; + assign rollover_m1 = {{32-SIZE+1{1'b0}},i[1:SIZE - 1]} == WRAP - 1; + + assign inc_1 = inc[0] ^ inc[1]; + assign inc_2 = inc[0] & inc[1]; + + assign wrap_sel[0] = (rollover & inc_1) | (rollover_m1 & inc_2); + assign wrap_sel[1] = rollover & inc_2; + + assign o[0] = i[0] ^ |(wrap_sel); + + assign o[1:SIZE-1] = (wrap_sel[0:1] == 2'b10) ? {SIZE-1{1'b0}} : + (wrap_sel[0:1] == 2'b01) ? {{SIZE-2{1'b0}},{1'b1}} : + rslt[1:SIZE-1]; + +endmodule diff --git a/dev/verilog/work/iuq_cpl_table.v b/dev/verilog/work/iuq_cpl_table.v new file mode 100755 index 0000000..fa28c7a --- /dev/null +++ b/dev/verilog/work/iuq_cpl_table.v @@ -0,0 +1,2522 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// VHDL 1076 Macro Expander C version 07/11/00 +// job was run on Fri Apr 15 16:09:08 2011 + +//******************************************************************** +//* +//* TITLE: +//* +//* NAME: iuq_cpl_table.v +//* +//********************************************************************* + +`include "tri_a2o.vh" + +module iuq_cpl_table( + input i0_complete, + input i0_bp_pred, + input i0_br_miss, + input [0:2] i0_ucode, + input i0_isram, + input i0_mtiar, + input i0_rollover, + input i0_rfi, + input i0_n_np1_flush, + input i1_complete, + input i1_bp_pred, + input i1_br_miss, + input [0:2] i1_ucode, + input i1_isram, + input i1_mtiar, + input i1_rollover, + input i1_rfi, + input i1_n_np1_flush, + + output iu_pc_i0_comp, + output iu_pc_i1_comp, + + input icmp_enable, + input irpt_enable, + + output select_i0_p1, + output select_i1_p1, + output select_i0_bta, + output select_i1_bta, + output select_i0_bp_bta, + output select_i1_bp_bta, + output select_ucode_p1, + output select_reset, + output select_mtiar, + + input cp3_async_int_val, + input [0:31] cp3_async_int, + input cp3_iu_excvec_val, + input [0:3] cp3_iu_excvec, + input cp3_lq_excvec_val, + input [0:5] cp3_lq_excvec, + input cp3_xu_excvec_val, + input [0:4] cp3_xu_excvec, + input cp3_axu_excvec_val, + input [0:3] cp3_axu_excvec, + input cp3_db_val, + input [0:18] cp3_db_events, + input cp3_ld, + input cp3_st, + input cp3_fp, + input cp3_ap, + input cp3_spv, + input cp3_epid, + input cp3_rfi, + input cp3_attn, + input cp3_sc, + input cp3_icmp_block, + output cp3_asyn_irpt_taken, + output cp3_asyn_irpt_needed, + output cp3_asyn_icmp_taken, + output cp3_asyn_icmp_needed, + output cp3_db_events_masked_reduced, + output [62-`EFF_IFAR_ARCH:61] cp3_exc_nia, + output cp3_mchk_disabled, + input [64-`GPR_WIDTH:51] spr_ivpr, + input [64-`GPR_WIDTH:51] spr_givpr, + input msr_gs, + input msr_me, + input dbg_int_en, + input dbcr0_irpt, + input epcr_duvd, + input epcr_extgs, + input epcr_dtlbgs, + input epcr_itlbgs, + input epcr_dsigs, + input epcr_isigs, + input epcr_icm, + input epcr_gicm, + output dp_cp_async_flush, + output dp_cp_async_bus_snoop_flush, + output async_np1_flush, + output async_n_flush, + output mm_iu_exception, + output pc_iu_stop, + output mc_int, + output g_int, + output c_int, + output dear_update, + output dbsr_update, + output eheir_update, + output [0:18] cp3_dbsr, + output dbell_taken, + output cdbell_taken, + output gdbell_taken, + output gcdbell_taken, + output gmcdbell_taken, + + output esr_update, + output [0:16] cp3_exc_esr, + output [0:14] cp3_exc_mcsr, + + output cp_mm_itlb_miss, + output cp_mm_dtlb_miss, + output cp_mm_isi, + output cp_mm_dsi, + output cp_mm_ilrat_miss, + output cp_mm_dlrat_miss, + output cp_mm_imchk, + output cp_mm_dmchk, + + input dis_mm_mchk + +); + + wire ap_async; + wire ap_axu; + wire ap_iu; + wire ap_lq; + wire ap_xu; + wire bo_async; + wire bo_axu; + wire bo_iu; + wire bo_lq; + wire bo_xu; + wire data_async; + wire data_axu; + wire data_iu; + wire data_lq; + wire data_xu; + wire dcache_dir_multi_lq; + wire dcache_dir_par_lq; + wire dcache_l2_ecc_lq; + wire dcache_par_lq; + wire derat_multi_lq; + wire derat_par_lq; + wire derat_par_xu; + wire [0:1] dlk_async; + wire [0:1] dlk_axu; + wire [0:1] dlk_iu; + wire [0:1] dlk_lq; + wire [0:1] dlk_xu; + wire epid_async; + wire epid_axu; + wire epid_iu; + wire epid_lq; + wire epid_xu; + wire esr_async; + wire esr_axu; + wire esr_iu; + wire esr_lq; + wire esr_xu; + wire fp_async; + wire fp_axu; + wire fp_iu; + wire fp_lq; + wire fp_xu; + wire icache_l2_ecc_iu; + wire ierat_multi_iu; + wire ierat_par_iu; + wire ierat_par_xu; + wire [1:10] nia0_pt; + wire [1:10] nia1_pt; + wire pie_async; + wire pie_axu; + wire pie_iu; + wire pie_lq; + wire pie_xu; + wire pil_async; + wire pil_axu; + wire pil_iu; + wire pil_lq; + wire pil_xu; + wire ppr_async; + wire ppr_axu; + wire ppr_iu; + wire ppr_lq; + wire ppr_xu; + wire ptr_async; + wire ptr_axu; + wire ptr_iu; + wire ptr_lq; + wire ptr_xu; + wire pt_async; + wire pt_axu; + wire pt_iu; + wire pt_lq; + wire pt_xu; + wire puo_async; + wire puo_axu; + wire puo_iu; + wire puo_lq; + wire puo_xu; + wire spv_async; + wire spv_axu; + wire spv_iu; + wire spv_lq; + wire spv_xu; + wire st_async; + wire st_axu; + wire st_iu; + wire st_lq; + wire st_xu; + wire [1:35] tbl_async_exection_list_pt; + wire [1:6] tbl_axu_exection_list_pt; + wire [1:14] tbl_iu_exection_list_pt; + wire [1:28] tbl_lq_exection_list_pt; + wire [1:18] tbl_xu_exection_list_pt; + wire tlbi_async; + wire tlbi_axu; + wire tlbi_iu; + wire tlbi_lq; + wire tlbi_xu; + wire tlb_lru_par_async; + wire tlb_lru_par_lq; + wire tlb_lru_par_xu; + wire tlb_multi_async; + wire tlb_multi_lq; + wire tlb_multi_xu; + wire tlb_par_async; + wire tlb_par_lq; + wire tlb_par_xu; + wire tlb_snoop_rej_async; + wire uct_async; + wire uct_axu; + wire uct_iu; + wire uct_lq; + wire uct_xu; + wire ude_input_async; + wire alignment_lq; + wire ap_unavailable_axu; + wire ap_unavailable_lq; + wire async_np1; + wire async_n; + wire [0:18] axu_db_mask; + wire cp3_icmp_excep; + wire crit_async; + wire crit_input_async; + wire data_storage_hv_lq; + wire data_storage_lq; + wire data_storage_xu; + wire data_tlb_lq; + wire dbell_async; + wire dbell_crit_async; + wire debug_async; + wire debug_icmp; + wire debug_irpt; + wire dec_async; + wire dp_cp_async; + wire dp_cp_async_bus_snoop; + wire external_async; + wire fit_async; + wire fp_unavailable_axu; + wire fp_unavailable_lq; + wire guest_async; + wire guest_dbell_async; + wire guest_dbell_crit_async; + wire guest_dbell_mchk_async; + wire guest_dec_async; + wire guest_fit_async; + wire guest_wdog_async; + wire hyp_priv_iu; + wire n_flush_iu; + wire hyp_priv_lq; + wire hyp_priv_xu; + wire i0_bp_bta; + wire i0_bta; + wire i0_check_next; + wire i0_comp; + wire i0_p1; + wire i0_reset; + wire i0_ucode_p1; + wire i1_bp_bta; + wire i1_bta; + wire i1_check_next; + wire i1_comp; + wire i1_p1; + wire i1_reset; + wire i1_ucode_p1; + wire instruction_storage_hv_iu; + wire instruction_storage_iu; + wire instruction_tlb_iu; + wire instr_tlb_async; + wire irpt_taken_async; + wire [0:18] iu_db_mask; + wire [0:18] lq_db_mask; + wire lrat_lq; + wire lrat_miss_async; + wire lrat_xu; + wire mcheck_async; + wire mcheck_iu; + wire mcheck_lq; + wire mcheck_xu; + wire mchk_ext_async; + wire perf_async; + wire program_ap_axu; + wire program_fp_axu; + wire program_fp_en_async; + wire program_iu; + wire program_lq; + wire program_xu; + wire pt_fault_async; + wire system_call_hyp_iu; + wire system_call_iu; + wire tlb_inelig_async; + wire tlb_xu; + wire user_dec_async; + wire vec_unavailable_axu; + wire vec_unavailable_lq; + wire wdog_async; + wire [0:18] xu_db_mask; + wire guest_int; + wire [0:18] cp3_db_events_masked; + wire cp3_db_int_events_val; + wire [0:18] db_mask; + wire debug_irpt_int_dis; + wire debug_icmp_excep; + wire pc_stop; + +//table_start +// +//?generate begin a(0 to 1); +//?TABLE NIA LISTING(final) OPTIMIZE PARMS(ON-SET,DC-SET); +//*INPUTS*============================*OUTPUTS*=======================* +//| | | +//| i_complete | | +//| | i_bp_pred | | +//| | | i_br_miss | | +//| | | | i_ucode | | +//| | | | | i_isram | | +//| | | | | | i_mtiar | | +//| | | | | | | i_rfi | | +//| | | | | | | | i_n_np1_flush | i_p1 | +//| | | | | | | | | | | i_bta | +//| | | | | | | | | | | | i_bp_bta | +//| | | | | | | | | | | | | i_ucode_p1 | +//| | | | | | | | | | | | | | i_reset | +//| | | | | | | | | | | | | | | i_check_next | +//| | | | | | | | | | | | | | | | i_comp | +//| | | | | | | | | | | | | | | | | | +//| | | | | | | | | | | | | | | | | | +//| | | | 012 | | | | | | | | | | | | | +//*TYPE*==============================+===============================+ +//| P P P PPP P P P P | S S S S S S S | +//*TERMS*=============================+===============================+ +//| 1 0 0 000 0 0 0 0 | 1 0 0 0 0 1 1 | # Completing +//| 1 0 0 000 0 0 0 1 | 0 0 0 0 0 0 0 | # Completing without updating ifar stupid FU exceptions +//| 1 0 0 101 0 0 0 1 | 0 0 0 0 0 0 0 | # Completing without updating ifar stupid FU exceptions +//| 1 0 1 --- 0 - 0 . | 0 1 0 0 0 0 1 | # Miss predict +//| 1 1 1 --- 0 0 0 . | 0 1 0 0 0 0 1 | # Miss predict +//| 1 1 0 --- 0 0 0 . | 0 0 1 0 0 1 1 | # Correct predict +//| 1 - - 010 0 0 0 . | 0 0 0 0 0 1 0 | # Ucode Start Complete +//| 1 - - 100 0 0 0 . | 0 0 0 0 0 1 0 | # Ucode Middle Complete +//| 1 - - 101 0 0 0 0 | 0 0 0 1 0 1 1 | # Ucode End Complete +//| 1 - - --- 1 0 - . | 0 0 0 0 0 1 0 | # Completing RAM +//| 1 - - --- - 1 - . | 0 1 0 0 0 0 0 | # Completing MTIAR in RAM +//| 0 - - --- - - 1 . | 0 0 0 0 1 0 0 | # Completing RFI Used to only update IAR +//*END*===============================+===============================+ +//?TABLE END NIA ; +//?generate end; +// +// +//?TABLE tbl_iu_exection_list LISTING(final) OPTIMIZE PARMS(ON-SET,DC-SET); +//*INPUTS*====================*OUTPUTS*===========================================================================* +//| | | +//| cp3_iu_excvec_val | | +//| | cp3_iu_excvec | mcheck_iu | +//| | | dis_mm_mchk | | instruction_tlb_iu | +//| | | | | | | instruction_storage_iu | +//| | | | | | | | instruction_storage_hv_iu | +//| | | | | | | | | system_call_iu | +//| | | | | | | | | | system_call_hyp_iu | +//| | | | | | | | | | | program_iu | +//| | | | | | | | | | | | hyp_priv_iu | +//| | | | | | | | | | | | | n_flush_iu | +//| | | | | | | | | | | | | | FP_iu | +//| | | | | | | | | | | | | | | ST_iu | +//| | | | | | | | | | | | | | | | DLK_iu | +//| | | | | | | | | | | | | | | | | AP_iu | +//| | | | | | | | | | | | | | | | | | BO_iu | +//| | | | | | | | | | | | | | | | | | | TLBI_iu | +//| | | | | | | | | | | | | | | | | | | | PT_iu | +//| | | | | | | | | | | | | | | | | | | | | SPV_iu | +//| | | | | | | | | | | | | | | | | | | | | | EPID_iu | +//| | | | | | | | | | | | | | | | | | | | | | | PIL_iu | +//| | | | | | | | | | | | | | | | | | | | | | | | PPR_iu | +//| | | | | | | | | | | | | | | | | | | | | | | | | PTR_iu | +//| | | | | | | | | | | | | | | | | | | | | | | | | | PUO_iu | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | PIE_iu | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | UCT_iu | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | DATA_iu | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ESR_iu | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ICache_l2_ecc_iu | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IErat_multi_iu | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IErat_par_iu | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | iu_db_mask | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 111111111 | +//| | 0123 | | | | | | | | | | | | | 01 | | | | | | | | | | | | | | | | | 0123456789012345678 | +//*TYPE*======================+===================================================================================+ +//| P PPPP P | S S S S S S S S S S S SS S S S S S S S S S S S S S S S S S SSSSSSSSSSSSSSSSSSS | +//*TERMS*=====================+===================================================================================+ +//| 0 ---- - | 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1111111111111111111 | +//| 1 0000 0 | 1 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0000000000000000000 | Machine Check I-ERAT Parity Error IEPE 0x000 0 +//| 1 0000 1 | 0 0 0 0 0 0 0 0 1 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0000000000000000000 | I-ERAT Parity Error NFLUSH(NO_MCHK, XUCR4[MMU_MCHK]=0 and CCR2[NOTLB]=0) +//| 1 0001 - | 1 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0000000000000000000 | Machine Check L2 ECC 0x000 1 +//| 1 0010 0 | 1 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0000000000000000000 | Machine Check IERAT Multi-hit Error IEMH 0x000 2 +//| 1 0010 1 | 0 0 0 0 0 0 0 0 1 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0000000000000000000 | IERAT Multi-hit Error NFLUSH(NO_MCHK, XUCR4[MMU_MCHK]=0 and CCR2[NOTLB]=0) +//| 1 0101 - | 0 1 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0001011110000000001 | Instruction TLB ERAT Miss 0x1E0 5 +//| 1 0110 - | 0 0 1 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0001011110000000001 | Instruction Storage Execution Access Violation 0x080 6 +//| 1 0111 - | 0 0 0 0 0 0 1 0 0 0 0 00 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0001011110000000001 | Program IU sourced priviledged instruction PPR 0x0E0 7 +//| 1 1000 - | 0 0 0 0 0 0 0 1 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0001011110000000001 | Hypervisor Priv IU source Hypervisor priviledged instruction 0x320 8 +//| 1 1001 - | 0 0 0 0 1 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0101011110000000001 | System Call System Call 0x120 9 +//| 1 1010 - | 0 0 0 0 0 1 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0101011110000000001 | System Call System Call Hypervisor 0x300 10 +//| 1 1011 - | 0 0 0 0 0 0 1 0 0 1 0 00 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0001011110000000001 | Program Unimplemented Op PUO,[FP,AP,SPV] 0x0E0 11 +//| 1 1100 - | 0 0 0 0 0 0 1 0 0 0 0 00 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0001011110000000001 | Program Illegal SC/DCR PIL 0x0E0 12 +//*END*=======================+===================================================================================+ +//?TABLE END tbl_iu_exection_list; +// +// +//?TABLE tbl_lq_exection_list LISTING(final) OPTIMIZE PARMS(ON-SET,DC-SET); +//*INPUTS*===========================*OUTPUTS*==========================================================================================* +//| | | +//| cp3_lq_excvec_val | lrat_lq | +//| | cp3_lq_excvec | | fp_unavailable_lq | +//| | | | | | ap_unavailable_lq | +//| | | | | | | vec_unavailable_lq | +//| | | | | | | | program_lq | +//| | | | | | | | | mcheck_lq | +//| | | | | | | | | | data_tlb_lq | +//| | | | | | | | | | | data_storage_lq | +//| | | | | | | | | | | | data_storage_hv_lq | +//| | | | | | | | | | | | | alignment_lq | +//| | | | | | | | | | | | | | hyp_priv_lq | +//| | | | | | | | | | | | | | | | +//| | | | | | | | | | | | | | | FP_lq | +//| | | | | | | | | | | | | | | | ST_lq | +//| | | | | | | | | | | | | | | | | DLK_lq | +//| | | | | | | | | | | | | | | | | | AP_lq | +//| | | | | | | | | | | | | | | | | | | BO_lq | +//| | | | | | | | | | | | | | | | | | | | TLBI_lq | +//| | | | | | | | | | | | | | | | | | | | | PT_lq | +//| | | | | | | | | | | | | | | | | | | | | | SPV_lq | +//| | | | | | | | | | | | | | | | | | | | | | | EPID_lq | +//| | | | | | | | | | | | | | | | | | | | | | | | PIL_lq | +//| | | | | | | | | | | | | | | | | | | | | | | | | PPR_lq | +//| | | | | | | | | | | | | | | | | | | | | | | | | | PTR_lq | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | PUO_lq | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | PIE_lq | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | UCT_lq | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DATA_lq | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ESR_lq | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DCache_dir_multi_lq | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TLB_LRU_par_lq | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DCache_l2_ecc_lq | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DCache_dir_par_lq | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DCache_par_lq | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DErat_multi_lq | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TLB_multi_lq | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DErat_par_lq | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TLB_par_lq | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | lq_db_mask | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 111111111 | +//| | 012345 | | | | | | | | | | | | | | 01 | | | | | | | | | | | | | | | | | | | | | | | 0123456789012345678 | +//*TYPE*=============================+==================================================================================================+ +//| P PPPPPP | S S S S S S S S S S S S S SS S S S S S S S S S S S S S S S S S S S S S S S SSSSSSSSSSSSSSSSSSS | +//*TERMS*============================+==================================================================================================+ +//| 0 ------ | 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1111111111111111111 | +//| 1 000000 | 0 0 0 0 1 0 0 0 0 0 0 1 0 00 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0001011110000000001 | Illegal instr type LQ Sourced PIL 0x0E0 0 +//| 1 000001 | 0 0 0 0 1 0 0 0 0 0 0 1 0 00 1 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0001011110000000001 | Program LQ Priviledged Program Interrupt PPR 0x0E0 1 +//| 1 000010 | 0 1 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0001011110000000001 | FP Unavailable XU Sourced 0x100 2 +//| 1 000011 | 0 0 1 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0001011110000000001 | AP Unavailable XU Sourced 0x140 3 +//| 1 000100 | 0 0 0 1 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0001011110000000001 | Vector Unavailable XU Sourced 0x200 4 +//| 1 000101 | 0 0 0 0 1 0 0 0 0 0 0 1 0 00 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0001011110000000001 | Program Unimplemented Op PUO,[FP,AP,SPV] 0x0E0 5 +//| 1 000110 | 0 0 0 0 0 0 0 0 0 0 1 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0001011110000000001 | Hypervisor Priv LQ sourced priviledged instruction 0x320 6 +//| 1 000111 | 0 0 0 0 0 1 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0000011110000000001 | Machine Check D-ERAT Parity Error DEPE 0x000 7 +//| 1 001000 | 0 0 0 0 0 1 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0000011110000000001 | Machine Check Data Cache Directory Parity Error DDPE 0x000 8 +//| 1 001001 | 0 0 0 0 0 1 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0000011110000000001 | Machine Check Data Cache Parity Error DCPE 0x000 9 +//| 1 001010 | 0 0 0 0 0 1 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0000011110000000001 | Machine Check DERAT Multi-hit Error DEMH 0x000 10 +//| 1 001011 | 0 0 0 0 0 1 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0000011110000000001 | Machine Check Data Cache Multi-hit Error DEMH 0x000 11 +//| 1 001100 | 0 0 0 0 0 1 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0000011110000000001 | Machine Check TLB Parity Error TLBPE 0x000 12 +//| 1 001101 | 0 0 0 0 0 1 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0000011110000000001 | Machine Check TLB LRU Parity Error TLBLRUPE 0x000 13 +//| 1 001110 | 0 0 0 0 0 1 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0000011110000000001 | Machine Check TLB MultiHit Error TLBMH 0x000 14 +//| 1 001111 | 0 0 0 0 0 0 1 0 0 0 0 1 1 00 1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0001011110000000001 | Data TLB TLB/ERAT Miss [ST],[FP,AP,SPV],[EPID] 0x1C0 15 +//| 1 010000 | 0 0 0 0 0 0 0 1 0 0 0 1 1 00 1 0 0 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0001011110000000001 | Data Storage Page Table Fault [ST],PT,[FP,AP,SPV],[EPID] 0x060 16 +//| 1 010001 | 0 0 0 0 0 0 0 0 1 0 0 1 1 00 1 0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0001011110000000001 | Data Storage TLB Ineligible [ST],TLBI,[FP,AP,SPV],[EPID] 0x060 17 +//| 1 010010 | 0 0 0 0 0 0 0 1 0 0 0 0 1 10 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0001011110000000001 | Data Storage D$ Lock Instruction [ST],DLK0 0x060 19 +//| 1 010011 | 0 0 0 0 0 0 0 1 0 0 0 0 1 01 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0001011110000000001 | Data Storage I$ Lock Instruction [ST],DLK1 0x060 20 +//| 1 010100 | 0 0 0 0 0 0 0 0 1 0 0 1 1 00 1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0001011110000000001 | Data Storage Virtualization Fault bit set [ST],[FP,AP,SPV],[EPID] 0x060 21 +//| 1 010101 | 0 0 0 0 0 0 0 1 0 0 0 1 1 00 1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0001011110000000001 | Data Storage R/W Access violation [ST],[FP,AP,SPV] 0x060 22 +//| 1 010110 | 0 0 0 0 0 0 0 1 0 0 0 0 1 00 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0001011110000000001 | Data Storage LWARX/STWCX Instruction with I=1 or W=1 [ST] 0x060 23 +//| 1 010111 | 0 0 0 0 0 0 0 1 0 0 0 0 0 00 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0001011110000000001 | Data Storage Unavaible Coprocessor Type UCT,[EPID] 0x060 24 +//| 1 011000 | 0 0 0 0 0 0 0 0 0 1 0 1 1 00 1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0001011110000000001 | Alignment Load or Store alignment [ST],[FP,AP,SPV],[EPID] 0x0C0 25 +//| 1 011001 | 1 0 0 0 0 0 0 0 0 0 0 1 1 00 1 0 0 1 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0001011110000000001 | LRAT Data side LRAT Miss [ST],DATA,PT,[FP,AP,SPV],[EPID] 0x340 18 +//| 1 011010 | 0 0 0 0 0 1 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0000011110000000001 | Machine Check Dcache L2 Reload UE DL2ECC 0x000 26 +//*END*==============================+==================================================================================================+ +//?TABLE END tbl_lq_exection_list; +// +// +//?TABLE tbl_xu_exection_list LISTING(final) OPTIMIZE PARMS(ON-SET,DC-SET); +//*INPUTS*==================*OUTPUTS*==============================================================================* +//| | | +//| cp3_xu_excvec_val | mcheck_xu | +//| | cp3_xu_excvec | | program_xu | +//| | | | | | cp3_icmp_excep | +//| | | | | | | hyp_priv_xu | +//| | | | | | | | data_storage_xu | +//| | | | | | | | | tlb_xu | +//| | | | | | | | | | lrat_xu | +//| | | | | | | | | | | | +//| | | | | | | | | | | FP_xu | +//| | | | | | | | | | | | ST_xu | +//| | | | | | | | | | | | | DLK_xu | +//| | | | | | | | | | | | | | AP_xu | +//| | | | | | | | | | | | | | | BO_xu | +//| | | | | | | | | | | | | | | | TLBI_xu | +//| | | | | | | | | | | | | | | | | PT_xu | +//| | | | | | | | | | | | | | | | | | SPV_xu | +//| | | | | | | | | | | | | | | | | | | EPID_xu | +//| | | | | | | | | | | | | | | | | | | | PIL_xu | +//| | | | | | | | | | | | | | | | | | | | | PPR_xu | +//| | | | | | | | | | | | | | | | | | | | | | PTR_xu | +//| | | | | | | | | | | | | | | | | | | | | | | PUO_xu | +//| | | | | | | | | | | | | | | | | | | | | | | | PIE_xu | +//| | | | | | | | | | | | | | | | | | | | | | | | | UCT_xu | +//| | | | | | | | | | | | | | | | | | | | | | | | | | DATA_xu | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | ESR_xu | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | TLB_LRU_par_xu | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | TLB_multi_xu | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IErat_par_xu | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DErat_par_xu | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TLB_par_xu | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TLB_snoop_rej_async | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | xu_db_mask | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 111111111 | +//| | 01234 | | | | | | | | | | 01 | | | | | | | | | | | | | | | | | | | | 0123456789012345678 | +//*TYPE*====================+======================================================================================+ +//| P PPPPP | S S S S S S S S S SS S S S S S S S S S S S S S S S S S S S S SSSSSSSSSSSSSSSSSSS | +//*TERMS*===================+======================================================================================+ +//| 0 ----- | 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1111111111111111111 | +//| 1 00000 | 1 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0000011110000000001 | # Machine Check TLB Parity Error TLBPE 0 +//| 1 00001 | 1 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0000011110000000001 | # Machine Check TLB LRU Parity Error TLBRUPE 1 +//| 1 00010 | 1 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0000011110000000001 | # Machine Check TLB Multi-Hit Error TLBMH 2 +//| 1 00011 | 1 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0000011110000000001 | # Machine Check IERAT search parity error IEPE 3 +//| 1 00100 | 1 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0000011110000000001 | # Machine Check DERAT search parity error DEPE 4 +//| 1 00101 | 0 1 0 0 0 0 0 0 0 00 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0001011110000000001 | # Program XU sourced illegal instruction type PIL 5 +//| 1 00110 | 0 1 0 0 0 0 0 0 0 00 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0001011110000000001 | # Program SPR sourced illegal SPR PIL 6 +//| 1 00111 | 0 1 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0001011110000000001 | # Program SPR sourced priviledged SPR PPR 7 +//| 1 01000 | 0 1 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0001011110000000001 | # Program XU sourced priviledged instruction PPR 8 +//| 1 01001 | 0 0 0 1 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0001011110000000001 | # Hypervisor Priviledge Priviledged SPR 9 +//| 1 01010 | 0 0 1 1 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0001011111000000001 | # Hypervisor Priviledge ehpriv instruction 10 +//| 1 01011 | 0 0 0 1 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0001011110000000001 | # Hypervisor Priviledge XU sourced priviledged instruction 11 +//| 1 01100 | 0 0 0 0 0 1 0 1 1 00 1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0001011110000000001 | # Data Storage TLB Ineligible [ST],[FP,AP,SPV],[EPID] 0x060 12 +//| 1 01101 | 0 1 0 0 0 0 0 0 0 00 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0001011110000000001 | # Program MMU Illegal Mas PIL 13 +//| 1 01110 | 0 1 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0001111110000000001 | # Program Trap Instruction PTR 14 +//| 1 01111 | 0 0 0 0 0 0 1 1 1 00 1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0001011110000000001 | # LRAT Data side LRAT Miss [ST],[FP,AP,SPV],[EPID] 0x340 15 +//| 1 10000 | 1 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0001011110000000001 | # Machine Check TLBIVAX reject 16 +//*END*=====================+======================================================================================+ +//?TABLE END tbl_xu_exection_list; +// +//?TABLE tbl_axu_exection_list LISTING(final) OPTIMIZE PARMS(ON-SET,DC-SET); +//*INPUTS*================*OUTPUTS*============================================================* +//| | | +//| cp3_axu_excvec_val | ap_unavailable_axu | +//| | cp3_axu_excvec | | fp_unavailable_axu | +//| | | | | | vec_unavailable_axu | +//| | | | | | | program_fp_axu | +//| | | | | | | | program_ap_axu | +//| | | | | | | | | | +//| | | | | | | | | FP_axu | +//| | | | | | | | | | ST_axu | +//| | | | | | | | | | | DLK_axu | +//| | | | | | | | | | | | AP_axu | +//| | | | | | | | | | | | | BO_axu | +//| | | | | | | | | | | | | | TLBI_axu | +//| | | | | | | | | | | | | | | PT_axu | +//| | | | | | | | | | | | | | | | SPV_axu | +//| | | | | | | | | | | | | | | | | EPID_axu | +//| | | | | | | | | | | | | | | | | | PIL_axu | +//| | | | | | | | | | | | | | | | | | | PPR_axu | +//| | | | | | | | | | | | | | | | | | | | PTR_axu | +//| | | | | | | | | | | | | | | | | | | | | PUO_axu | +//| | | | | | | | | | | | | | | | | | | | | | PIE_axu | +//| | | | | | | | | | | | | | | | | | | | | | | UCT_axu | +//| | | | | | | | | | | | | | | | | | | | | | | | DATA_axu | +//| | | | | | | | | | | | | | | | | | | | | | | | | ESR_axu | +//| | | | | | | | | | | | | | | | | | | | | | | | | | axu_db_mask | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | 111111111 | +//| | 0123 | | | | | | | | 01 | | | | | | | | | | | | | | 0123456789012345678 | +//*TYPE*==================+====================================================================+ +//| P PPPP | S S S S S S S SS S S S S S S S S S S S S S S SSSSSSSSSSSSSSSSSSS | +//*TERMS*=================+====================================================================+ +//| 0 ---- | 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1111111111111111111 | +//| 1 0000 | 1 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0001011110000000001 | AP Unavailable 0x140 7 +//| 1 0001 | 0 1 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0001011110000000001 | FP Unavailable 0x100 7 +//| 1 0010 | 0 0 1 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0001011110000000001 | Vector Unavailable 0x200 7 +//| 1 0011 | 0 0 0 0 1 0 0 00 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0001011110000000001 | Progam AP Enabled AP 0x0E0 100 +//| 1 0100 | 0 0 0 1 0 1 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0001011110000000001 | Progam FP Enabled FP 0x0E0 10 +//| 1 0101 | 0 0 0 1 0 1 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0001011110000000001 | Progam FP Enabled FP 0x0E0 10 +//*END*===================+====================================================================+ +//?TABLE END tbl_axu_exection_list; +// +// +//?TABLE tbl_async_exection_list LISTING(final) OPTIMIZE PARMS(ON-SET,DC-SET); +//*INPUTS*===========================================*OUTPUTS*=========================================================================================================================* +//| | instr_tlb_async | +//| | | pt_fault_async | +//| | | | lrat_miss_async | +//| | | | | tlb_inelig_async | +//| | | | | | TLB_multi_async | +//| | | | | | | TLB_par_async | +//| | | | | | | | TLB_LRU_par_async | +//| | | | | | | | | debug_icmp | +//| | | | | | | | | | debug_irpt | +//| | | | | | | | | | | debug_async | +//| | | | | | | | | | | | mchk_ext_async | +//| cp3_async_int_val | | | | | | | | | | | | program_fp_en_async | +//| | cp3_async_int | | | | | | | | | | | | | guest_dbell_mchk_async | +//| | | dis_mm_mchk | | | | | | | | | | | | | | perf_async | +//| | | | | | | | | | | | | | | | | | | UDE_input_async | +//| | | | | | | | | | | | | | | | | | | | crit_input_async | +//| | | | | | | | | | | | | | | | | | | | | wdog_async | +//| | | | | | | | | | | | | | | | | | | | | | guest_wdog_async | +//| | | | | | | | | | | | | | | | | | | | | | | dbell_crit_async | +//| | | | | | | | | | | | | | | | | | | | | | | | guest_dbell_crit_async | +//| | | | | | | | | | | | | | | | | | | | | | | | | external_async | +//| | | | | | | | | | | | | | | | | | | | | | | | | | fit_async | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | guest_fit_async | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | dec_async | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | guest_dec_async | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dbell_async | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | guest_dbell_async | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | user_dec_async | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dp_cp_async | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dp_cp_async_bus_snoop | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | async_np1 | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pc_stop | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | async_n | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FP_async | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ST_async | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DLK_async | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AP_async | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BO_async | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TLBI_async | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PT_async | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SPV_async | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | EPID_async | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PIL_async | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PPR_async | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PTR_async | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PUO_async | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PIE_async | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | UCT_async | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DATA_async | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ESR_async | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | crit_async | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mcheck_async | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | guest_async | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | irpt_taken_async | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | +//| | | 1111111111222222222233 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | +//| | 01234567890123456789012345678901 | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 01 | | | | | | | | | | | | | | | | | | | +//*TYPE*=============================================+=================================================================================================================================+ +//| P PPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPP P | S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S S SS S S S S S S S S S S S S S S S S S S | +//*TERMS*============================================+=================================================================================================================================+ +//| 0 -------------------------------- - | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | +//| 1 1------------------------------- - | 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 | Instruction TLB miss TLBLRUPER 0x000 10 + +//| 1 01------------------------------ 0 | 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 | TLB_LRU_parity error TLBLRUPER 0x000 10 +//| 1 001----------------------------- 0 | 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 | TLB parity error TLBPER 0x000 10 +//| 1 0001---------------------------- 0 | 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 | TLB multihit TLBMHIT 0x000 10 +//| 1 01------------------------------ 1 | 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | TLB_LRU_parity error NFLUSH(NO_MCHK, XUCR4[MMU_MCHK]=0 and CCR2[NOTLB]=0) +//| 1 001----------------------------- 1 | 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | TLB parity error NFLUSH(NO_MCHK, XUCR4[MMU_MCHK]=0 and CCR2[NOTLB]=0) +//| 1 0001---------------------------- 1 | 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | TLB multihit NFLUSH(NO_MCHK, XUCR4[MMU_MCHK]=0 and CCR2[NOTLB]=0) + +//| 1 00001--------------------------- - | 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 | IU PT Fault 0x080 10 +//| 1 000001-------------------------- - | 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 | IU TLB InElig TLBI 0x080 10 +//| 1 0000001------------------------- - | 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 | IU LRAT Miss 0x340 10 +//| 1 00000001------------------------ - | 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 | Debug icmp Crit DBSR update 0x040 10 +//| 1 000000001----------------------- - | 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 | Debug irpt Crit DBSR update 0x040 10 +//| 1 0000000001---------------------- - | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | mm hold req +//| 1 00000000001--------------------- - | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | mm bus snoop hold req +//| 1 000000000001-------------------- - | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | async np1 +//| 1 0000000000001------------------- - | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 | pc_iu_stop +//| 1 00000000000001------------------ - | 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 | Debug async Crit DBSR update 0x040 10 +//| 1 000000000000001----------------- - | 0 0 0 0 0 0 0 0 0 - 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 00 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 | Progam FP Enabled FP, PIE 0x0E0 10 +//| 1 0000000000000001---------------- - | 0 0 0 0 0 0 0 0 0 - 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 | Mchk external MCHK 0x000 10 +//| 1 00000000000000001--------------- - | 0 0 0 0 0 0 0 0 0 - 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 | Guest DBell Mach Check Crit 0x2E0 19 +//| 1 000000000000000001-------------- - | 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 | UDE debug event Crit DBSR update 0x040 10 +//| 1 0000000000000000001------------- - | 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 | Critical Input Crit 0x020 21 +//| 1 00000000000000000001------------ - | 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 | Watchdog Crit 0x1A0 22 +//| 1 000000000000000000001----------- - | 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 | Guest Watchdog Crit 0x1A0 22.1 +//| 1 0000000000000000000001---------- - | 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 | Doorbell Critical Crit 0x2A0 23 +//| 1 00000000000000000000001--------- - | 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 | Guest Doorbell Critical Crit 0x2E0 24 +//| 1 000000000000000000000001-------- - | 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 | External 0x0A0 25 +//| 1 0000000000000000000000001------- - | 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 | Fixed Interval Timer Crit 0x180 26 +//| 1 00000000000000000000000001------ - | 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 | Guest Fixed Int Timer Crit 0x180 26.1 +//| 1 000000000000000000000000001----- - | 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 | Decrement 0x160 27 +//| 1 0000000000000000000000000001---- - | 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 | Guest Decrement 0x160 27.1 +//| 1 00000000000000000000000000001--- - | 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 | Doorbell 0x280 28 +//| 1 000000000000000000000000000001-- - | 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 | Guest Doorbell 0x2C0 29 +//| 1 0000000000000000000000000000001- - | 0 0 0 0 0 0 0 0 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 | User Decrementer 0x800 30 +//| 1 00000000000000000000000000000001 - | 0 0 0 0 0 0 0 0 0 - 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 | Perf 0x820 31 +//*END*==============================================+=================================================================================================================================+ +//?TABLE END tbl_async_exection_list; +// +//table_end +// +//assign_start + +assign nia0_pt[1] = + (({ i0_complete , i0_bp_pred , + i0_br_miss , i0_ucode[0] , + i0_ucode[1] , i0_ucode[2] , + i0_isram , i0_mtiar , + i0_rfi , i0_n_np1_flush + }) === 10'b1000000000); +assign nia0_pt[2] = + (({ i0_complete , i0_ucode[0] , + i0_ucode[1] , i0_ucode[2] , + i0_isram , i0_mtiar , + i0_rfi , i0_n_np1_flush + }) === 8'b11010000); +assign nia0_pt[3] = + (({ i0_complete , i0_ucode[0] , + i0_ucode[1] , i0_ucode[2] , + i0_mtiar , i0_rfi + }) === 6'b101000); +assign nia0_pt[4] = + (({ i0_complete , i0_ucode[0] , + i0_ucode[1] , i0_ucode[2] , + i0_mtiar , i0_rfi + }) === 6'b110000); +assign nia0_pt[5] = + (({ i0_complete , i0_bp_pred , + i0_br_miss , i0_isram , + i0_rfi }) === 5'b10100); +assign nia0_pt[6] = + (({ i0_complete , i0_rfi + }) === 2'b01); +assign nia0_pt[7] = + (({ i0_complete , i0_bp_pred , + i0_br_miss , i0_isram , + i0_mtiar , i0_rfi + }) === 6'b110000); +assign nia0_pt[8] = + (({ i0_complete , i0_br_miss , + i0_isram , i0_mtiar , + i0_rfi }) === 5'b11000); +assign nia0_pt[9] = + (({ i0_complete , i0_mtiar + }) === 2'b11); +assign nia0_pt[10] = + (({ i0_complete , i0_isram , + i0_mtiar }) === 3'b110); +assign i0_p1 = + (nia0_pt[1]); +assign i0_bta = + (nia0_pt[8] | nia0_pt[9] + ); +assign i0_bp_bta = + (nia0_pt[7]); +assign i0_ucode_p1 = + (nia0_pt[2]); +assign i0_reset = + (nia0_pt[6]); +assign i0_check_next = + (nia0_pt[1] | nia0_pt[2] + | nia0_pt[3] | nia0_pt[4] + | nia0_pt[7] | nia0_pt[10] + ); +assign i0_comp = + (nia0_pt[1] | nia0_pt[2] + | nia0_pt[5] | nia0_pt[7] + | nia0_pt[8]); + +assign nia1_pt[1] = + (({ i1_complete , i1_bp_pred , + i1_br_miss , i1_ucode[0] , + i1_ucode[1] , i1_ucode[2] , + i1_isram , i1_mtiar , + i1_rfi , i1_n_np1_flush + }) === 10'b1000000000); +assign nia1_pt[2] = + (({ i1_complete , i1_ucode[0] , + i1_ucode[1] , i1_ucode[2] , + i1_isram , i1_mtiar , + i1_rfi , i1_n_np1_flush + }) === 8'b11010000); +assign nia1_pt[3] = + (({ i1_complete , i1_ucode[0] , + i1_ucode[1] , i1_ucode[2] , + i1_mtiar , i1_rfi + }) === 6'b101000); +assign nia1_pt[4] = + (({ i1_complete , i1_ucode[0] , + i1_ucode[1] , i1_ucode[2] , + i1_mtiar , i1_rfi + }) === 6'b110000); +assign nia1_pt[5] = + (({ i1_complete , i1_bp_pred , + i1_br_miss , i1_isram , + i1_rfi }) === 5'b10100); +assign nia1_pt[6] = + (({ i1_complete , i1_rfi + }) === 2'b01); +assign nia1_pt[7] = + (({ i1_complete , i1_bp_pred , + i1_br_miss , i1_isram , + i1_mtiar , i1_rfi + }) === 6'b110000); +assign nia1_pt[8] = + (({ i1_complete , i1_br_miss , + i1_isram , i1_mtiar , + i1_rfi }) === 5'b11000); +assign nia1_pt[9] = + (({ i1_complete , i1_mtiar + }) === 2'b11); +assign nia1_pt[10] = + (({ i1_complete , i1_isram , + i1_mtiar }) === 3'b110); +assign i1_p1 = + (nia1_pt[1]); +assign i1_bta = + (nia1_pt[8] | nia1_pt[9] + ); +assign i1_bp_bta = + (nia1_pt[7]); +assign i1_ucode_p1 = + (nia1_pt[2]); +assign i1_reset = + (nia1_pt[6]); +assign i1_check_next = + (nia1_pt[1] | nia1_pt[2] + | nia1_pt[3] | nia1_pt[4] + | nia1_pt[7] | nia1_pt[10] + ); +assign i1_comp = + (nia1_pt[1] | nia1_pt[2] + | nia1_pt[5] | nia1_pt[7] + | nia1_pt[8]); + +assign tbl_iu_exection_list_pt[1] = + (({ cp3_iu_excvec_val , cp3_iu_excvec[0] , + cp3_iu_excvec[1] , cp3_iu_excvec[2] , + cp3_iu_excvec[3] , dis_mm_mchk + }) === 6'b100100); +assign tbl_iu_exection_list_pt[2] = + (({ cp3_iu_excvec_val , cp3_iu_excvec[0] , + cp3_iu_excvec[1] , cp3_iu_excvec[2] , + cp3_iu_excvec[3] , dis_mm_mchk + }) === 6'b100101); +assign tbl_iu_exection_list_pt[3] = + (({ cp3_iu_excvec_val , cp3_iu_excvec[0] , + cp3_iu_excvec[1] , cp3_iu_excvec[2] , + cp3_iu_excvec[3] , dis_mm_mchk + }) === 6'b100000); +assign tbl_iu_exection_list_pt[4] = + (({ cp3_iu_excvec_val , cp3_iu_excvec[0] , + cp3_iu_excvec[1] , cp3_iu_excvec[2] , + cp3_iu_excvec[3] , dis_mm_mchk + }) === 6'b100001); +assign tbl_iu_exection_list_pt[5] = + (({ cp3_iu_excvec_val , cp3_iu_excvec[0] , + cp3_iu_excvec[1] , cp3_iu_excvec[2] , + cp3_iu_excvec[3] }) === 5'b10101); +assign tbl_iu_exection_list_pt[6] = + (({ cp3_iu_excvec_val , cp3_iu_excvec[0] , + cp3_iu_excvec[1] , cp3_iu_excvec[2] , + cp3_iu_excvec[3] }) === 5'b10111); +assign tbl_iu_exection_list_pt[7] = + (({ cp3_iu_excvec_val , cp3_iu_excvec[0] , + cp3_iu_excvec[1] , cp3_iu_excvec[2] , + cp3_iu_excvec[3] }) === 5'b10110); +assign tbl_iu_exection_list_pt[8] = + (({ cp3_iu_excvec_val , cp3_iu_excvec[0] , + cp3_iu_excvec[1] , cp3_iu_excvec[2] , + cp3_iu_excvec[3] }) === 5'b11100); +assign tbl_iu_exection_list_pt[9] = + (({ cp3_iu_excvec_val , cp3_iu_excvec[0] , + cp3_iu_excvec[1] , cp3_iu_excvec[2] , + cp3_iu_excvec[3] }) === 5'b10001); +assign tbl_iu_exection_list_pt[10] = + (({ cp3_iu_excvec_val , cp3_iu_excvec[0] , + cp3_iu_excvec[1] , cp3_iu_excvec[2] , + cp3_iu_excvec[3] }) === 5'b11001); +assign tbl_iu_exection_list_pt[11] = + (({ cp3_iu_excvec_val , cp3_iu_excvec[0] , + cp3_iu_excvec[1] , cp3_iu_excvec[2] , + cp3_iu_excvec[3] }) === 5'b11000); +assign tbl_iu_exection_list_pt[12] = + (({ cp3_iu_excvec_val , cp3_iu_excvec[0] , + cp3_iu_excvec[1] , cp3_iu_excvec[2] , + cp3_iu_excvec[3] }) === 5'b11011); +assign tbl_iu_exection_list_pt[13] = + (({ cp3_iu_excvec_val , cp3_iu_excvec[0] , + cp3_iu_excvec[1] , cp3_iu_excvec[2] , + cp3_iu_excvec[3] }) === 5'b11010); +assign tbl_iu_exection_list_pt[14] = + (({ cp3_iu_excvec_val }) === 1'b0); +assign mcheck_iu = + (tbl_iu_exection_list_pt[1] | tbl_iu_exection_list_pt[3] + | tbl_iu_exection_list_pt[9]); +assign instruction_tlb_iu = + (tbl_iu_exection_list_pt[5]); +assign instruction_storage_iu = + (tbl_iu_exection_list_pt[7]); +assign instruction_storage_hv_iu = + 1'b0; +assign system_call_iu = + (tbl_iu_exection_list_pt[10]); +assign system_call_hyp_iu = + (tbl_iu_exection_list_pt[13]); +assign program_iu = + (tbl_iu_exection_list_pt[6] | tbl_iu_exection_list_pt[8] + | tbl_iu_exection_list_pt[12]); +assign hyp_priv_iu = + (tbl_iu_exection_list_pt[11]); +assign n_flush_iu = + (tbl_iu_exection_list_pt[2] | tbl_iu_exection_list_pt[4] + ); +assign fp_iu = + (tbl_iu_exection_list_pt[12]); +assign st_iu = + 1'b0; +assign dlk_iu[0] = + 1'b0; +assign dlk_iu[1] = + 1'b0; +assign ap_iu = + (tbl_iu_exection_list_pt[12]); +assign bo_iu = + 1'b0; +assign tlbi_iu = + 1'b0; +assign pt_iu = + 1'b0; +assign spv_iu = + (tbl_iu_exection_list_pt[12]); +assign epid_iu = + 1'b0; +assign pil_iu = + (tbl_iu_exection_list_pt[8]); +assign ppr_iu = + (tbl_iu_exection_list_pt[6]); +assign ptr_iu = + 1'b0; +assign puo_iu = + (tbl_iu_exection_list_pt[12]); +assign pie_iu = + 1'b0; +assign uct_iu = + 1'b0; +assign data_iu = + 1'b0; +assign esr_iu = + (tbl_iu_exection_list_pt[6] | tbl_iu_exection_list_pt[7] + | tbl_iu_exection_list_pt[8] | tbl_iu_exection_list_pt[12] + ); +assign icache_l2_ecc_iu = + (tbl_iu_exection_list_pt[9]); +assign ierat_multi_iu = + (tbl_iu_exection_list_pt[1] | tbl_iu_exection_list_pt[2] + ); +assign ierat_par_iu = + (tbl_iu_exection_list_pt[3] | tbl_iu_exection_list_pt[4] + ); +assign iu_db_mask[0] = + (tbl_iu_exection_list_pt[14]); +assign iu_db_mask[1] = + (tbl_iu_exection_list_pt[10] | tbl_iu_exection_list_pt[13] + | tbl_iu_exection_list_pt[14]); +assign iu_db_mask[2] = + (tbl_iu_exection_list_pt[14]); +assign iu_db_mask[3] = + (tbl_iu_exection_list_pt[5] | tbl_iu_exection_list_pt[6] + | tbl_iu_exection_list_pt[7] | tbl_iu_exection_list_pt[8] + | tbl_iu_exection_list_pt[10] | tbl_iu_exection_list_pt[11] + | tbl_iu_exection_list_pt[12] | tbl_iu_exection_list_pt[13] + | tbl_iu_exection_list_pt[14]); +assign iu_db_mask[4] = + (tbl_iu_exection_list_pt[14]); +assign iu_db_mask[5] = + (tbl_iu_exection_list_pt[5] | tbl_iu_exection_list_pt[6] + | tbl_iu_exection_list_pt[7] | tbl_iu_exection_list_pt[8] + | tbl_iu_exection_list_pt[10] | tbl_iu_exection_list_pt[11] + | tbl_iu_exection_list_pt[12] | tbl_iu_exection_list_pt[13] + | tbl_iu_exection_list_pt[14]); +assign iu_db_mask[6] = + (tbl_iu_exection_list_pt[5] | tbl_iu_exection_list_pt[6] + | tbl_iu_exection_list_pt[7] | tbl_iu_exection_list_pt[8] + | tbl_iu_exection_list_pt[10] | tbl_iu_exection_list_pt[11] + | tbl_iu_exection_list_pt[12] | tbl_iu_exection_list_pt[13] + | tbl_iu_exection_list_pt[14]); +assign iu_db_mask[7] = + (tbl_iu_exection_list_pt[5] | tbl_iu_exection_list_pt[6] + | tbl_iu_exection_list_pt[7] | tbl_iu_exection_list_pt[8] + | tbl_iu_exection_list_pt[10] | tbl_iu_exection_list_pt[11] + | tbl_iu_exection_list_pt[12] | tbl_iu_exection_list_pt[13] + | tbl_iu_exection_list_pt[14]); +assign iu_db_mask[8] = + (tbl_iu_exection_list_pt[5] | tbl_iu_exection_list_pt[6] + | tbl_iu_exection_list_pt[7] | tbl_iu_exection_list_pt[8] + | tbl_iu_exection_list_pt[10] | tbl_iu_exection_list_pt[11] + | tbl_iu_exection_list_pt[12] | tbl_iu_exection_list_pt[13] + | tbl_iu_exection_list_pt[14]); +assign iu_db_mask[9] = + (tbl_iu_exection_list_pt[14]); +assign iu_db_mask[10] = + (tbl_iu_exection_list_pt[14]); +assign iu_db_mask[11] = + (tbl_iu_exection_list_pt[14]); +assign iu_db_mask[12] = + (tbl_iu_exection_list_pt[14]); +assign iu_db_mask[13] = + (tbl_iu_exection_list_pt[14]); +assign iu_db_mask[14] = + (tbl_iu_exection_list_pt[14]); +assign iu_db_mask[15] = + (tbl_iu_exection_list_pt[14]); +assign iu_db_mask[16] = + (tbl_iu_exection_list_pt[14]); +assign iu_db_mask[17] = + (tbl_iu_exection_list_pt[14]); +assign iu_db_mask[18] = + (tbl_iu_exection_list_pt[5] | tbl_iu_exection_list_pt[6] + | tbl_iu_exection_list_pt[7] | tbl_iu_exection_list_pt[8] + | tbl_iu_exection_list_pt[10] | tbl_iu_exection_list_pt[11] + | tbl_iu_exection_list_pt[12] | tbl_iu_exection_list_pt[13] + | tbl_iu_exection_list_pt[14]); + +assign tbl_lq_exection_list_pt[1] = + (({ cp3_lq_excvec_val , cp3_lq_excvec[0] , + cp3_lq_excvec[1] , cp3_lq_excvec[2] , + cp3_lq_excvec[3] , cp3_lq_excvec[4] , + cp3_lq_excvec[5] }) === 7'b1010010); +assign tbl_lq_exection_list_pt[2] = + (({ cp3_lq_excvec_val , cp3_lq_excvec[0] , + cp3_lq_excvec[1] , cp3_lq_excvec[2] , + cp3_lq_excvec[3] , cp3_lq_excvec[4] , + cp3_lq_excvec[5] }) === 7'b1011010); +assign tbl_lq_exection_list_pt[3] = + (({ cp3_lq_excvec_val , cp3_lq_excvec[0] , + cp3_lq_excvec[1] , cp3_lq_excvec[2] , + cp3_lq_excvec[3] , cp3_lq_excvec[4] , + cp3_lq_excvec[5] }) === 7'b1001101); +assign tbl_lq_exection_list_pt[4] = + (({ cp3_lq_excvec_val , cp3_lq_excvec[0] , + cp3_lq_excvec[1] , cp3_lq_excvec[2] , + cp3_lq_excvec[3] , cp3_lq_excvec[4] , + cp3_lq_excvec[5] }) === 7'b1001110); +assign tbl_lq_exection_list_pt[5] = + (({ cp3_lq_excvec_val , cp3_lq_excvec[0] , + cp3_lq_excvec[1] , cp3_lq_excvec[2] , + cp3_lq_excvec[3] , cp3_lq_excvec[4] , + cp3_lq_excvec[5] }) === 7'b1001100); +assign tbl_lq_exection_list_pt[6] = + (({ cp3_lq_excvec_val , cp3_lq_excvec[0] , + cp3_lq_excvec[1] , cp3_lq_excvec[2] , + cp3_lq_excvec[3] , cp3_lq_excvec[4] , + cp3_lq_excvec[5] }) === 7'b1001011); +assign tbl_lq_exection_list_pt[7] = + (({ cp3_lq_excvec_val , cp3_lq_excvec[0] , + cp3_lq_excvec[1] , cp3_lq_excvec[2] , + cp3_lq_excvec[3] , cp3_lq_excvec[4] , + cp3_lq_excvec[5] }) === 7'b1001001); +assign tbl_lq_exection_list_pt[8] = + (({ cp3_lq_excvec_val , cp3_lq_excvec[0] , + cp3_lq_excvec[1] , cp3_lq_excvec[2] , + cp3_lq_excvec[3] , cp3_lq_excvec[4] , + cp3_lq_excvec[5] }) === 7'b1001010); +assign tbl_lq_exection_list_pt[9] = + (({ cp3_lq_excvec_val , cp3_lq_excvec[0] , + cp3_lq_excvec[1] , cp3_lq_excvec[2] , + cp3_lq_excvec[3] , cp3_lq_excvec[4] , + cp3_lq_excvec[5] }) === 7'b1000111); +assign tbl_lq_exection_list_pt[10] = + (({ cp3_lq_excvec_val , cp3_lq_excvec[0] , + cp3_lq_excvec[1] , cp3_lq_excvec[2] , + cp3_lq_excvec[3] , cp3_lq_excvec[4] , + cp3_lq_excvec[5] }) === 7'b1001000); +assign tbl_lq_exection_list_pt[11] = + (({ cp3_lq_excvec_val , cp3_lq_excvec[0] , + cp3_lq_excvec[1] , cp3_lq_excvec[2] , + cp3_lq_excvec[3] , cp3_lq_excvec[4] , + cp3_lq_excvec[5] }) === 7'b1000110); +assign tbl_lq_exection_list_pt[12] = + (({ cp3_lq_excvec_val , cp3_lq_excvec[0] , + cp3_lq_excvec[1] , cp3_lq_excvec[2] , + cp3_lq_excvec[3] , cp3_lq_excvec[4] , + cp3_lq_excvec[5] }) === 7'b1000100); +assign tbl_lq_exection_list_pt[13] = + (({ cp3_lq_excvec_val , cp3_lq_excvec[0] , + cp3_lq_excvec[1] , cp3_lq_excvec[2] , + cp3_lq_excvec[3] , cp3_lq_excvec[4] , + cp3_lq_excvec[5] }) === 7'b1000011); +assign tbl_lq_exection_list_pt[14] = + (({ cp3_lq_excvec_val , cp3_lq_excvec[0] , + cp3_lq_excvec[1] , cp3_lq_excvec[2] , + cp3_lq_excvec[3] , cp3_lq_excvec[4] , + cp3_lq_excvec[5] }) === 7'b1000010); +assign tbl_lq_exection_list_pt[15] = + (({ cp3_lq_excvec_val , cp3_lq_excvec[0] , + cp3_lq_excvec[1] , cp3_lq_excvec[2] , + cp3_lq_excvec[3] , cp3_lq_excvec[4] , + cp3_lq_excvec[5] }) === 7'b1010111); +assign tbl_lq_exection_list_pt[16] = + (({ cp3_lq_excvec_val , cp3_lq_excvec[0] , + cp3_lq_excvec[1] , cp3_lq_excvec[2] , + cp3_lq_excvec[3] , cp3_lq_excvec[4] , + cp3_lq_excvec[5] }) === 7'b1010011); +assign tbl_lq_exection_list_pt[17] = + (({ cp3_lq_excvec_val , cp3_lq_excvec[0] , + cp3_lq_excvec[1] , cp3_lq_excvec[2] , + cp3_lq_excvec[3] , cp3_lq_excvec[4] , + cp3_lq_excvec[5] }) === 7'b1000000); +assign tbl_lq_exection_list_pt[18] = + (({ cp3_lq_excvec_val , cp3_lq_excvec[0] , + cp3_lq_excvec[1] , cp3_lq_excvec[2] , + cp3_lq_excvec[4] , cp3_lq_excvec[5] + }) === 6'b101010); +assign tbl_lq_exection_list_pt[19] = + (({ cp3_lq_excvec_val , cp3_lq_excvec[0] , + cp3_lq_excvec[1] , cp3_lq_excvec[2] , + cp3_lq_excvec[3] , cp3_lq_excvec[4] , + cp3_lq_excvec[5] }) === 7'b1000101); +assign tbl_lq_exection_list_pt[20] = + (({ cp3_lq_excvec_val , cp3_lq_excvec[0] , + cp3_lq_excvec[1] , cp3_lq_excvec[2] , + cp3_lq_excvec[3] , cp3_lq_excvec[4] , + cp3_lq_excvec[5] }) === 7'b1000001); +assign tbl_lq_exection_list_pt[21] = + (({ cp3_lq_excvec_val , cp3_lq_excvec[0] , + cp3_lq_excvec[1] , cp3_lq_excvec[2] , + cp3_lq_excvec[3] , cp3_lq_excvec[4] , + cp3_lq_excvec[5] }) === 7'b1001111); +assign tbl_lq_exection_list_pt[22] = + (({ cp3_lq_excvec_val , cp3_lq_excvec[0] , + cp3_lq_excvec[1] , cp3_lq_excvec[2] , + cp3_lq_excvec[3] , cp3_lq_excvec[4] , + cp3_lq_excvec[5] }) === 7'b1011000); +assign tbl_lq_exection_list_pt[23] = + (({ cp3_lq_excvec_val , cp3_lq_excvec[0] , + cp3_lq_excvec[1] , cp3_lq_excvec[2] , + cp3_lq_excvec[3] , cp3_lq_excvec[4] , + cp3_lq_excvec[5] }) === 7'b1010100); +assign tbl_lq_exection_list_pt[24] = + (({ cp3_lq_excvec_val , cp3_lq_excvec[0] , + cp3_lq_excvec[1] , cp3_lq_excvec[2] , + cp3_lq_excvec[3] , cp3_lq_excvec[4] , + cp3_lq_excvec[5] }) === 7'b1011001); +assign tbl_lq_exection_list_pt[25] = + (({ cp3_lq_excvec_val , cp3_lq_excvec[0] , + cp3_lq_excvec[1] , cp3_lq_excvec[2] , + cp3_lq_excvec[3] , cp3_lq_excvec[4] , + cp3_lq_excvec[5] }) === 7'b1010101); +assign tbl_lq_exection_list_pt[26] = + (({ cp3_lq_excvec_val }) === 1'b0); +assign tbl_lq_exection_list_pt[27] = + (({ cp3_lq_excvec_val , cp3_lq_excvec[0] , + cp3_lq_excvec[1] , cp3_lq_excvec[2] , + cp3_lq_excvec[3] , cp3_lq_excvec[4] , + cp3_lq_excvec[5] }) === 7'b1010001); +assign tbl_lq_exection_list_pt[28] = + (({ cp3_lq_excvec_val , cp3_lq_excvec[0] , + cp3_lq_excvec[1] , cp3_lq_excvec[2] , + cp3_lq_excvec[3] , cp3_lq_excvec[4] , + cp3_lq_excvec[5] }) === 7'b1010000); +assign lrat_lq = + (tbl_lq_exection_list_pt[24]); +assign fp_unavailable_lq = + (tbl_lq_exection_list_pt[14]); +assign ap_unavailable_lq = + (tbl_lq_exection_list_pt[13]); +assign vec_unavailable_lq = + (tbl_lq_exection_list_pt[12]); +assign program_lq = + (tbl_lq_exection_list_pt[17] | tbl_lq_exection_list_pt[19] + | tbl_lq_exection_list_pt[20]); +assign mcheck_lq = + (tbl_lq_exection_list_pt[2] | tbl_lq_exection_list_pt[3] + | tbl_lq_exection_list_pt[4] | tbl_lq_exection_list_pt[5] + | tbl_lq_exection_list_pt[6] | tbl_lq_exection_list_pt[7] + | tbl_lq_exection_list_pt[8] | tbl_lq_exection_list_pt[9] + | tbl_lq_exection_list_pt[10]); +assign data_tlb_lq = + (tbl_lq_exection_list_pt[21]); +assign data_storage_lq = + (tbl_lq_exection_list_pt[15] | tbl_lq_exection_list_pt[16] + | tbl_lq_exection_list_pt[18] | tbl_lq_exection_list_pt[25] + | tbl_lq_exection_list_pt[28]); +assign data_storage_hv_lq = + (tbl_lq_exection_list_pt[23] | tbl_lq_exection_list_pt[27] + ); +assign alignment_lq = + (tbl_lq_exection_list_pt[22]); +assign hyp_priv_lq = + (tbl_lq_exection_list_pt[11]); +assign fp_lq = + (tbl_lq_exection_list_pt[17] | tbl_lq_exection_list_pt[19] + | tbl_lq_exection_list_pt[20] | tbl_lq_exection_list_pt[21] + | tbl_lq_exection_list_pt[22] | tbl_lq_exection_list_pt[23] + | tbl_lq_exection_list_pt[24] | tbl_lq_exection_list_pt[25] + | tbl_lq_exection_list_pt[27] | tbl_lq_exection_list_pt[28] + ); +assign st_lq = + (tbl_lq_exection_list_pt[16] | tbl_lq_exection_list_pt[18] + | tbl_lq_exection_list_pt[21] | tbl_lq_exection_list_pt[22] + | tbl_lq_exection_list_pt[23] | tbl_lq_exection_list_pt[24] + | tbl_lq_exection_list_pt[25] | tbl_lq_exection_list_pt[27] + | tbl_lq_exection_list_pt[28]); +assign dlk_lq[0] = + (tbl_lq_exection_list_pt[1]); +assign dlk_lq[1] = + (tbl_lq_exection_list_pt[16]); +assign ap_lq = + (tbl_lq_exection_list_pt[19] | tbl_lq_exection_list_pt[20] + | tbl_lq_exection_list_pt[21] | tbl_lq_exection_list_pt[22] + | tbl_lq_exection_list_pt[23] | tbl_lq_exection_list_pt[24] + | tbl_lq_exection_list_pt[25] | tbl_lq_exection_list_pt[27] + | tbl_lq_exection_list_pt[28]); +assign bo_lq = + 1'b0; +assign tlbi_lq = + (tbl_lq_exection_list_pt[27]); +assign pt_lq = + (tbl_lq_exection_list_pt[24] | tbl_lq_exection_list_pt[28] + ); +assign spv_lq = + (tbl_lq_exection_list_pt[19] | tbl_lq_exection_list_pt[20] + | tbl_lq_exection_list_pt[21] | tbl_lq_exection_list_pt[22] + | tbl_lq_exection_list_pt[23] | tbl_lq_exection_list_pt[24] + | tbl_lq_exection_list_pt[25] | tbl_lq_exection_list_pt[27] + | tbl_lq_exection_list_pt[28]); +assign epid_lq = + (tbl_lq_exection_list_pt[15] | tbl_lq_exection_list_pt[21] + | tbl_lq_exection_list_pt[22] | tbl_lq_exection_list_pt[23] + | tbl_lq_exection_list_pt[24] | tbl_lq_exection_list_pt[25] + | tbl_lq_exection_list_pt[27] | tbl_lq_exection_list_pt[28] + ); +assign pil_lq = + (tbl_lq_exection_list_pt[17]); +assign ppr_lq = + (tbl_lq_exection_list_pt[20]); +assign ptr_lq = + 1'b0; +assign puo_lq = + (tbl_lq_exection_list_pt[19]); +assign pie_lq = + 1'b0; +assign uct_lq = + (tbl_lq_exection_list_pt[15]); +assign data_lq = + (tbl_lq_exection_list_pt[24]); +assign esr_lq = + (tbl_lq_exection_list_pt[15] | tbl_lq_exection_list_pt[16] + | tbl_lq_exection_list_pt[17] | tbl_lq_exection_list_pt[18] + | tbl_lq_exection_list_pt[19] | tbl_lq_exection_list_pt[20] + | tbl_lq_exection_list_pt[21] | tbl_lq_exection_list_pt[22] + | tbl_lq_exection_list_pt[23] | tbl_lq_exection_list_pt[24] + | tbl_lq_exection_list_pt[25] | tbl_lq_exection_list_pt[27] + | tbl_lq_exection_list_pt[28]); +assign dcache_dir_multi_lq = + (tbl_lq_exection_list_pt[6]); +assign tlb_lru_par_lq = + (tbl_lq_exection_list_pt[3]); +assign dcache_l2_ecc_lq = + (tbl_lq_exection_list_pt[2]); +assign dcache_dir_par_lq = + (tbl_lq_exection_list_pt[10]); +assign dcache_par_lq = + (tbl_lq_exection_list_pt[7]); +assign derat_multi_lq = + (tbl_lq_exection_list_pt[8]); +assign tlb_multi_lq = + (tbl_lq_exection_list_pt[4]); +assign derat_par_lq = + (tbl_lq_exection_list_pt[9]); +assign tlb_par_lq = + (tbl_lq_exection_list_pt[5]); +assign lq_db_mask[0] = + (tbl_lq_exection_list_pt[26]); +assign lq_db_mask[1] = + (tbl_lq_exection_list_pt[26]); +assign lq_db_mask[2] = + (tbl_lq_exection_list_pt[26]); +assign lq_db_mask[3] = + (tbl_lq_exection_list_pt[11] | tbl_lq_exection_list_pt[12] + | tbl_lq_exection_list_pt[13] | tbl_lq_exection_list_pt[14] + | tbl_lq_exection_list_pt[15] | tbl_lq_exection_list_pt[16] + | tbl_lq_exection_list_pt[17] | tbl_lq_exection_list_pt[18] + | tbl_lq_exection_list_pt[19] | tbl_lq_exection_list_pt[20] + | tbl_lq_exection_list_pt[21] | tbl_lq_exection_list_pt[22] + | tbl_lq_exection_list_pt[23] | tbl_lq_exection_list_pt[24] + | tbl_lq_exection_list_pt[25] | tbl_lq_exection_list_pt[26] + | tbl_lq_exection_list_pt[27] | tbl_lq_exection_list_pt[28] + ); +assign lq_db_mask[4] = + (tbl_lq_exection_list_pt[26]); +assign lq_db_mask[5] = + (tbl_lq_exection_list_pt[2] | tbl_lq_exection_list_pt[3] + | tbl_lq_exection_list_pt[4] | tbl_lq_exection_list_pt[5] + | tbl_lq_exection_list_pt[6] | tbl_lq_exection_list_pt[7] + | tbl_lq_exection_list_pt[8] | tbl_lq_exection_list_pt[9] + | tbl_lq_exection_list_pt[10] | tbl_lq_exection_list_pt[11] + | tbl_lq_exection_list_pt[12] | tbl_lq_exection_list_pt[13] + | tbl_lq_exection_list_pt[14] | tbl_lq_exection_list_pt[15] + | tbl_lq_exection_list_pt[16] | tbl_lq_exection_list_pt[17] + | tbl_lq_exection_list_pt[18] | tbl_lq_exection_list_pt[19] + | tbl_lq_exection_list_pt[20] | tbl_lq_exection_list_pt[21] + | tbl_lq_exection_list_pt[22] | tbl_lq_exection_list_pt[23] + | tbl_lq_exection_list_pt[24] | tbl_lq_exection_list_pt[25] + | tbl_lq_exection_list_pt[26] | tbl_lq_exection_list_pt[27] + | tbl_lq_exection_list_pt[28]); +assign lq_db_mask[6] = + (tbl_lq_exection_list_pt[2] | tbl_lq_exection_list_pt[3] + | tbl_lq_exection_list_pt[4] | tbl_lq_exection_list_pt[5] + | tbl_lq_exection_list_pt[6] | tbl_lq_exection_list_pt[7] + | tbl_lq_exection_list_pt[8] | tbl_lq_exection_list_pt[9] + | tbl_lq_exection_list_pt[10] | tbl_lq_exection_list_pt[11] + | tbl_lq_exection_list_pt[12] | tbl_lq_exection_list_pt[13] + | tbl_lq_exection_list_pt[14] | tbl_lq_exection_list_pt[15] + | tbl_lq_exection_list_pt[16] | tbl_lq_exection_list_pt[17] + | tbl_lq_exection_list_pt[18] | tbl_lq_exection_list_pt[19] + | tbl_lq_exection_list_pt[20] | tbl_lq_exection_list_pt[21] + | tbl_lq_exection_list_pt[22] | tbl_lq_exection_list_pt[23] + | tbl_lq_exection_list_pt[24] | tbl_lq_exection_list_pt[25] + | tbl_lq_exection_list_pt[26] | tbl_lq_exection_list_pt[27] + | tbl_lq_exection_list_pt[28]); +assign lq_db_mask[7] = + (tbl_lq_exection_list_pt[2] | tbl_lq_exection_list_pt[3] + | tbl_lq_exection_list_pt[4] | tbl_lq_exection_list_pt[5] + | tbl_lq_exection_list_pt[6] | tbl_lq_exection_list_pt[7] + | tbl_lq_exection_list_pt[8] | tbl_lq_exection_list_pt[9] + | tbl_lq_exection_list_pt[10] | tbl_lq_exection_list_pt[11] + | tbl_lq_exection_list_pt[12] | tbl_lq_exection_list_pt[13] + | tbl_lq_exection_list_pt[14] | tbl_lq_exection_list_pt[15] + | tbl_lq_exection_list_pt[16] | tbl_lq_exection_list_pt[17] + | tbl_lq_exection_list_pt[18] | tbl_lq_exection_list_pt[19] + | tbl_lq_exection_list_pt[20] | tbl_lq_exection_list_pt[21] + | tbl_lq_exection_list_pt[22] | tbl_lq_exection_list_pt[23] + | tbl_lq_exection_list_pt[24] | tbl_lq_exection_list_pt[25] + | tbl_lq_exection_list_pt[26] | tbl_lq_exection_list_pt[27] + | tbl_lq_exection_list_pt[28]); +assign lq_db_mask[8] = + (tbl_lq_exection_list_pt[2] | tbl_lq_exection_list_pt[3] + | tbl_lq_exection_list_pt[4] | tbl_lq_exection_list_pt[5] + | tbl_lq_exection_list_pt[6] | tbl_lq_exection_list_pt[7] + | tbl_lq_exection_list_pt[8] | tbl_lq_exection_list_pt[9] + | tbl_lq_exection_list_pt[10] | tbl_lq_exection_list_pt[11] + | tbl_lq_exection_list_pt[12] | tbl_lq_exection_list_pt[13] + | tbl_lq_exection_list_pt[14] | tbl_lq_exection_list_pt[15] + | tbl_lq_exection_list_pt[16] | tbl_lq_exection_list_pt[17] + | tbl_lq_exection_list_pt[18] | tbl_lq_exection_list_pt[19] + | tbl_lq_exection_list_pt[20] | tbl_lq_exection_list_pt[21] + | tbl_lq_exection_list_pt[22] | tbl_lq_exection_list_pt[23] + | tbl_lq_exection_list_pt[24] | tbl_lq_exection_list_pt[25] + | tbl_lq_exection_list_pt[26] | tbl_lq_exection_list_pt[27] + | tbl_lq_exection_list_pt[28]); +assign lq_db_mask[9] = + (tbl_lq_exection_list_pt[26]); +assign lq_db_mask[10] = + (tbl_lq_exection_list_pt[26]); +assign lq_db_mask[11] = + (tbl_lq_exection_list_pt[26]); +assign lq_db_mask[12] = + (tbl_lq_exection_list_pt[26]); +assign lq_db_mask[13] = + (tbl_lq_exection_list_pt[26]); +assign lq_db_mask[14] = + (tbl_lq_exection_list_pt[26]); +assign lq_db_mask[15] = + (tbl_lq_exection_list_pt[26]); +assign lq_db_mask[16] = + (tbl_lq_exection_list_pt[26]); +assign lq_db_mask[17] = + (tbl_lq_exection_list_pt[26]); +assign lq_db_mask[18] = + (tbl_lq_exection_list_pt[2] | tbl_lq_exection_list_pt[3] + | tbl_lq_exection_list_pt[4] | tbl_lq_exection_list_pt[5] + | tbl_lq_exection_list_pt[6] | tbl_lq_exection_list_pt[7] + | tbl_lq_exection_list_pt[8] | tbl_lq_exection_list_pt[9] + | tbl_lq_exection_list_pt[10] | tbl_lq_exection_list_pt[11] + | tbl_lq_exection_list_pt[12] | tbl_lq_exection_list_pt[13] + | tbl_lq_exection_list_pt[14] | tbl_lq_exection_list_pt[15] + | tbl_lq_exection_list_pt[16] | tbl_lq_exection_list_pt[17] + | tbl_lq_exection_list_pt[18] | tbl_lq_exection_list_pt[19] + | tbl_lq_exection_list_pt[20] | tbl_lq_exection_list_pt[21] + | tbl_lq_exection_list_pt[22] | tbl_lq_exection_list_pt[23] + | tbl_lq_exection_list_pt[24] | tbl_lq_exection_list_pt[25] + | tbl_lq_exection_list_pt[26] | tbl_lq_exection_list_pt[27] + | tbl_lq_exection_list_pt[28]); + +assign tbl_xu_exection_list_pt[1] = + (({ cp3_xu_excvec_val , cp3_xu_excvec[0] , + cp3_xu_excvec[1] , cp3_xu_excvec[2] , + cp3_xu_excvec[3] , cp3_xu_excvec[4] + }) === 6'b110000); +assign tbl_xu_exection_list_pt[2] = + (({ cp3_xu_excvec_val , cp3_xu_excvec[0] , + cp3_xu_excvec[1] , cp3_xu_excvec[2] , + cp3_xu_excvec[3] , cp3_xu_excvec[4] + }) === 6'b100011); +assign tbl_xu_exection_list_pt[3] = + (({ cp3_xu_excvec_val , cp3_xu_excvec[0] , + cp3_xu_excvec[1] , cp3_xu_excvec[2] , + cp3_xu_excvec[3] , cp3_xu_excvec[4] + }) === 6'b100001); +assign tbl_xu_exection_list_pt[4] = + (({ cp3_xu_excvec_val , cp3_xu_excvec[0] , + cp3_xu_excvec[1] , cp3_xu_excvec[2] , + cp3_xu_excvec[4] }) === 5'b10101); +assign tbl_xu_exection_list_pt[5] = + (({ cp3_xu_excvec_val , cp3_xu_excvec[0] , + cp3_xu_excvec[1] , cp3_xu_excvec[2] , + cp3_xu_excvec[3] , cp3_xu_excvec[4] + }) === 6'b100010); +assign tbl_xu_exection_list_pt[6] = + (({ cp3_xu_excvec_val , cp3_xu_excvec[0] , + cp3_xu_excvec[1] , cp3_xu_excvec[2] , + cp3_xu_excvec[3] , cp3_xu_excvec[4] + }) === 6'b100111); +assign tbl_xu_exection_list_pt[7] = + (({ cp3_xu_excvec_val , cp3_xu_excvec[0] , + cp3_xu_excvec[1] , cp3_xu_excvec[2] , + cp3_xu_excvec[3] , cp3_xu_excvec[4] + }) === 6'b100000); +assign tbl_xu_exection_list_pt[8] = + (({ cp3_xu_excvec_val , cp3_xu_excvec[0] , + cp3_xu_excvec[1] , cp3_xu_excvec[2] , + cp3_xu_excvec[3] , cp3_xu_excvec[4] + }) === 6'b101010); +assign tbl_xu_exection_list_pt[9] = + (({ cp3_xu_excvec_val , cp3_xu_excvec[0] , + cp3_xu_excvec[1] , cp3_xu_excvec[2] , + cp3_xu_excvec[3] , cp3_xu_excvec[4] + }) === 6'b101111); +assign tbl_xu_exection_list_pt[10] = + (({ cp3_xu_excvec_val , cp3_xu_excvec[0] , + cp3_xu_excvec[2] , cp3_xu_excvec[3] , + cp3_xu_excvec[4] }) === 5'b10101); +assign tbl_xu_exection_list_pt[11] = + (({ cp3_xu_excvec_val , cp3_xu_excvec[0] , + cp3_xu_excvec[1] , cp3_xu_excvec[2] , + cp3_xu_excvec[3] , cp3_xu_excvec[4] + }) === 6'b100110); +assign tbl_xu_exection_list_pt[12] = + (({ cp3_xu_excvec_val , cp3_xu_excvec[0] , + cp3_xu_excvec[1] , cp3_xu_excvec[2] , + cp3_xu_excvec[3] , cp3_xu_excvec[4] + }) === 6'b101000); +assign tbl_xu_exection_list_pt[13] = + (({ cp3_xu_excvec_val , cp3_xu_excvec[0] , + cp3_xu_excvec[1] , cp3_xu_excvec[2] , + cp3_xu_excvec[3] , cp3_xu_excvec[4] + }) === 6'b100100); +assign tbl_xu_exection_list_pt[14] = + (({ cp3_xu_excvec_val , cp3_xu_excvec[0] , + cp3_xu_excvec[1] , cp3_xu_excvec[2] , + cp3_xu_excvec[3] , cp3_xu_excvec[4] + }) === 6'b101110); +assign tbl_xu_exection_list_pt[15] = + (({ cp3_xu_excvec_val , cp3_xu_excvec[0] , + cp3_xu_excvec[1] , cp3_xu_excvec[2] , + cp3_xu_excvec[3] , cp3_xu_excvec[4] + }) === 6'b101100); +assign tbl_xu_exection_list_pt[16] = + (({ cp3_xu_excvec_val }) === 1'b0); +assign mcheck_xu = + (tbl_xu_exection_list_pt[1] | tbl_xu_exection_list_pt[2] + | tbl_xu_exection_list_pt[3] | tbl_xu_exection_list_pt[5] + | tbl_xu_exection_list_pt[7] | tbl_xu_exection_list_pt[13] + ); +assign program_xu = + (tbl_xu_exection_list_pt[6] | tbl_xu_exection_list_pt[10] + | tbl_xu_exection_list_pt[11] | tbl_xu_exection_list_pt[12] + | tbl_xu_exection_list_pt[14]); +assign cp3_icmp_excep = + (tbl_xu_exection_list_pt[8]); +assign hyp_priv_xu = + (tbl_xu_exection_list_pt[4] | tbl_xu_exection_list_pt[8] + ); +assign data_storage_xu = + 1'b0; +assign tlb_xu = + (tbl_xu_exection_list_pt[15]); +assign lrat_xu = + (tbl_xu_exection_list_pt[9]); +assign fp_xu = + (tbl_xu_exection_list_pt[9] | tbl_xu_exection_list_pt[15] + ); +assign st_xu = + (tbl_xu_exection_list_pt[9] | tbl_xu_exection_list_pt[15] + ); +assign dlk_xu[0] = + 1'b0; +assign dlk_xu[1] = + 1'b0; +assign ap_xu = + (tbl_xu_exection_list_pt[9] | tbl_xu_exection_list_pt[15] + ); +assign bo_xu = + 1'b0; +assign tlbi_xu = + 1'b0; +assign pt_xu = + 1'b0; +assign spv_xu = + (tbl_xu_exection_list_pt[9] | tbl_xu_exection_list_pt[15] + ); +assign epid_xu = + (tbl_xu_exection_list_pt[9] | tbl_xu_exection_list_pt[15] + ); +assign pil_xu = + (tbl_xu_exection_list_pt[10] | tbl_xu_exection_list_pt[11] + ); +assign ppr_xu = + (tbl_xu_exection_list_pt[6] | tbl_xu_exection_list_pt[12] + ); +assign ptr_xu = + (tbl_xu_exection_list_pt[14]); +assign puo_xu = + 1'b0; +assign pie_xu = + 1'b0; +assign uct_xu = + 1'b0; +assign data_xu = + 1'b0; +assign esr_xu = + (tbl_xu_exection_list_pt[6] | tbl_xu_exection_list_pt[9] + | tbl_xu_exection_list_pt[10] | tbl_xu_exection_list_pt[11] + | tbl_xu_exection_list_pt[12] | tbl_xu_exection_list_pt[14] + | tbl_xu_exection_list_pt[15]); +assign tlb_lru_par_xu = + (tbl_xu_exection_list_pt[3]); +assign tlb_multi_xu = + (tbl_xu_exection_list_pt[5]); +assign ierat_par_xu = + (tbl_xu_exection_list_pt[2]); +assign derat_par_xu = + (tbl_xu_exection_list_pt[13]); +assign tlb_par_xu = + (tbl_xu_exection_list_pt[7]); +assign tlb_snoop_rej_async = + (tbl_xu_exection_list_pt[1]); +assign xu_db_mask[0] = + (tbl_xu_exection_list_pt[16]); +assign xu_db_mask[1] = + (tbl_xu_exection_list_pt[16]); +assign xu_db_mask[2] = + (tbl_xu_exection_list_pt[16]); +assign xu_db_mask[3] = + (tbl_xu_exection_list_pt[1] | tbl_xu_exection_list_pt[4] + | tbl_xu_exection_list_pt[6] | tbl_xu_exection_list_pt[8] + | tbl_xu_exection_list_pt[9] | tbl_xu_exection_list_pt[10] + | tbl_xu_exection_list_pt[11] | tbl_xu_exection_list_pt[12] + | tbl_xu_exection_list_pt[14] | tbl_xu_exection_list_pt[15] + | tbl_xu_exection_list_pt[16]); +assign xu_db_mask[4] = + (tbl_xu_exection_list_pt[14] | tbl_xu_exection_list_pt[16] + ); +assign xu_db_mask[5] = + (tbl_xu_exection_list_pt[1] | tbl_xu_exection_list_pt[2] + | tbl_xu_exection_list_pt[3] | tbl_xu_exection_list_pt[4] + | tbl_xu_exection_list_pt[5] | tbl_xu_exection_list_pt[6] + | tbl_xu_exection_list_pt[7] | tbl_xu_exection_list_pt[8] + | tbl_xu_exection_list_pt[9] | tbl_xu_exection_list_pt[10] + | tbl_xu_exection_list_pt[11] | tbl_xu_exection_list_pt[12] + | tbl_xu_exection_list_pt[13] | tbl_xu_exection_list_pt[14] + | tbl_xu_exection_list_pt[15] | tbl_xu_exection_list_pt[16] + ); +assign xu_db_mask[6] = + (tbl_xu_exection_list_pt[1] | tbl_xu_exection_list_pt[2] + | tbl_xu_exection_list_pt[3] | tbl_xu_exection_list_pt[4] + | tbl_xu_exection_list_pt[5] | tbl_xu_exection_list_pt[6] + | tbl_xu_exection_list_pt[7] | tbl_xu_exection_list_pt[8] + | tbl_xu_exection_list_pt[9] | tbl_xu_exection_list_pt[10] + | tbl_xu_exection_list_pt[11] | tbl_xu_exection_list_pt[12] + | tbl_xu_exection_list_pt[13] | tbl_xu_exection_list_pt[14] + | tbl_xu_exection_list_pt[15] | tbl_xu_exection_list_pt[16] + ); +assign xu_db_mask[7] = + (tbl_xu_exection_list_pt[1] | tbl_xu_exection_list_pt[2] + | tbl_xu_exection_list_pt[3] | tbl_xu_exection_list_pt[4] + | tbl_xu_exection_list_pt[5] | tbl_xu_exection_list_pt[6] + | tbl_xu_exection_list_pt[7] | tbl_xu_exection_list_pt[8] + | tbl_xu_exection_list_pt[9] | tbl_xu_exection_list_pt[10] + | tbl_xu_exection_list_pt[11] | tbl_xu_exection_list_pt[12] + | tbl_xu_exection_list_pt[13] | tbl_xu_exection_list_pt[14] + | tbl_xu_exection_list_pt[15] | tbl_xu_exection_list_pt[16] + ); +assign xu_db_mask[8] = + (tbl_xu_exection_list_pt[1] | tbl_xu_exection_list_pt[2] + | tbl_xu_exection_list_pt[3] | tbl_xu_exection_list_pt[4] + | tbl_xu_exection_list_pt[5] | tbl_xu_exection_list_pt[6] + | tbl_xu_exection_list_pt[7] | tbl_xu_exection_list_pt[8] + | tbl_xu_exection_list_pt[9] | tbl_xu_exection_list_pt[10] + | tbl_xu_exection_list_pt[11] | tbl_xu_exection_list_pt[12] + | tbl_xu_exection_list_pt[13] | tbl_xu_exection_list_pt[14] + | tbl_xu_exection_list_pt[15] | tbl_xu_exection_list_pt[16] + ); +assign xu_db_mask[9] = + (tbl_xu_exection_list_pt[8] | tbl_xu_exection_list_pt[16] + ); +assign xu_db_mask[10] = + (tbl_xu_exection_list_pt[16]); +assign xu_db_mask[11] = + (tbl_xu_exection_list_pt[16]); +assign xu_db_mask[12] = + (tbl_xu_exection_list_pt[16]); +assign xu_db_mask[13] = + (tbl_xu_exection_list_pt[16]); +assign xu_db_mask[14] = + (tbl_xu_exection_list_pt[16]); +assign xu_db_mask[15] = + (tbl_xu_exection_list_pt[16]); +assign xu_db_mask[16] = + (tbl_xu_exection_list_pt[16]); +assign xu_db_mask[17] = + (tbl_xu_exection_list_pt[16]); +assign xu_db_mask[18] = + (tbl_xu_exection_list_pt[1] | tbl_xu_exection_list_pt[2] + | tbl_xu_exection_list_pt[3] | tbl_xu_exection_list_pt[4] + | tbl_xu_exection_list_pt[5] | tbl_xu_exection_list_pt[6] + | tbl_xu_exection_list_pt[7] | tbl_xu_exection_list_pt[8] + | tbl_xu_exection_list_pt[9] | tbl_xu_exection_list_pt[10] + | tbl_xu_exection_list_pt[11] | tbl_xu_exection_list_pt[12] + | tbl_xu_exection_list_pt[13] | tbl_xu_exection_list_pt[14] + | tbl_xu_exection_list_pt[15] | tbl_xu_exection_list_pt[16] + ); + +assign tbl_axu_exection_list_pt[1] = + (({ cp3_axu_excvec_val , cp3_axu_excvec[0] , + cp3_axu_excvec[1] , cp3_axu_excvec[2] , + cp3_axu_excvec[3] }) === 5'b10010); +assign tbl_axu_exection_list_pt[2] = + (({ cp3_axu_excvec_val , cp3_axu_excvec[0] , + cp3_axu_excvec[1] , cp3_axu_excvec[2] , + cp3_axu_excvec[3] }) === 5'b10011); +assign tbl_axu_exection_list_pt[3] = + (({ cp3_axu_excvec_val , cp3_axu_excvec[0] , + cp3_axu_excvec[1] , cp3_axu_excvec[2] + }) === 4'b1010); +assign tbl_axu_exection_list_pt[4] = + (({ cp3_axu_excvec_val , cp3_axu_excvec[0] , + cp3_axu_excvec[1] , cp3_axu_excvec[2] , + cp3_axu_excvec[3] }) === 5'b10000); +assign tbl_axu_exection_list_pt[5] = + (({ cp3_axu_excvec_val , cp3_axu_excvec[0] , + cp3_axu_excvec[1] , cp3_axu_excvec[2] , + cp3_axu_excvec[3] }) === 5'b10001); +assign tbl_axu_exection_list_pt[6] = + (({ cp3_axu_excvec_val }) === 1'b0); +assign ap_unavailable_axu = + (tbl_axu_exection_list_pt[4]); +assign fp_unavailable_axu = + (tbl_axu_exection_list_pt[5]); +assign vec_unavailable_axu = + (tbl_axu_exection_list_pt[1]); +assign program_fp_axu = + (tbl_axu_exection_list_pt[3]); +assign program_ap_axu = + (tbl_axu_exection_list_pt[2]); +assign fp_axu = + (tbl_axu_exection_list_pt[3]); +assign st_axu = + 1'b0; +assign dlk_axu[0] = + 1'b0; +assign dlk_axu[1] = + 1'b0; +assign ap_axu = + (tbl_axu_exection_list_pt[2]); +assign bo_axu = + 1'b0; +assign tlbi_axu = + 1'b0; +assign pt_axu = + 1'b0; +assign spv_axu = + 1'b0; +assign epid_axu = + 1'b0; +assign pil_axu = + 1'b0; +assign ppr_axu = + 1'b0; +assign ptr_axu = + 1'b0; +assign puo_axu = + 1'b0; +assign pie_axu = + 1'b0; +assign uct_axu = + 1'b0; +assign data_axu = + 1'b0; +assign esr_axu = + (tbl_axu_exection_list_pt[3]); +assign axu_db_mask[0] = + (tbl_axu_exection_list_pt[6]); +assign axu_db_mask[1] = + (tbl_axu_exection_list_pt[6]); +assign axu_db_mask[2] = + (tbl_axu_exection_list_pt[6]); +assign axu_db_mask[3] = + (tbl_axu_exection_list_pt[1] | tbl_axu_exection_list_pt[2] + | tbl_axu_exection_list_pt[3] | tbl_axu_exection_list_pt[4] + | tbl_axu_exection_list_pt[5] | tbl_axu_exection_list_pt[6] + ); +assign axu_db_mask[4] = + (tbl_axu_exection_list_pt[6]); +assign axu_db_mask[5] = + (tbl_axu_exection_list_pt[1] | tbl_axu_exection_list_pt[2] + | tbl_axu_exection_list_pt[3] | tbl_axu_exection_list_pt[4] + | tbl_axu_exection_list_pt[5] | tbl_axu_exection_list_pt[6] + ); +assign axu_db_mask[6] = + (tbl_axu_exection_list_pt[1] | tbl_axu_exection_list_pt[2] + | tbl_axu_exection_list_pt[3] | tbl_axu_exection_list_pt[4] + | tbl_axu_exection_list_pt[5] | tbl_axu_exection_list_pt[6] + ); +assign axu_db_mask[7] = + (tbl_axu_exection_list_pt[1] | tbl_axu_exection_list_pt[2] + | tbl_axu_exection_list_pt[3] | tbl_axu_exection_list_pt[4] + | tbl_axu_exection_list_pt[5] | tbl_axu_exection_list_pt[6] + ); +assign axu_db_mask[8] = + (tbl_axu_exection_list_pt[1] | tbl_axu_exection_list_pt[2] + | tbl_axu_exection_list_pt[3] | tbl_axu_exection_list_pt[4] + | tbl_axu_exection_list_pt[5] | tbl_axu_exection_list_pt[6] + ); +assign axu_db_mask[9] = + (tbl_axu_exection_list_pt[6]); +assign axu_db_mask[10] = + (tbl_axu_exection_list_pt[6]); +assign axu_db_mask[11] = + (tbl_axu_exection_list_pt[6]); +assign axu_db_mask[12] = + (tbl_axu_exection_list_pt[6]); +assign axu_db_mask[13] = + (tbl_axu_exection_list_pt[6]); +assign axu_db_mask[14] = + (tbl_axu_exection_list_pt[6]); +assign axu_db_mask[15] = + (tbl_axu_exection_list_pt[6]); +assign axu_db_mask[16] = + (tbl_axu_exection_list_pt[6]); +assign axu_db_mask[17] = + (tbl_axu_exection_list_pt[6]); +assign axu_db_mask[18] = + (tbl_axu_exection_list_pt[1] | tbl_axu_exection_list_pt[2] + | tbl_axu_exection_list_pt[3] | tbl_axu_exection_list_pt[4] + | tbl_axu_exection_list_pt[5] | tbl_axu_exection_list_pt[6] + ); + +assign tbl_async_exection_list_pt[1] = + (({ cp3_async_int_val , cp3_async_int[0] , + cp3_async_int[1] , cp3_async_int[2] , + cp3_async_int[3] , cp3_async_int[4] , + cp3_async_int[5] , cp3_async_int[6] , + cp3_async_int[7] , cp3_async_int[8] , + cp3_async_int[9] , cp3_async_int[10] , + cp3_async_int[11] , cp3_async_int[12] , + cp3_async_int[13] , cp3_async_int[14] , + cp3_async_int[15] , cp3_async_int[16] , + cp3_async_int[17] , cp3_async_int[18] , + cp3_async_int[19] , cp3_async_int[20] , + cp3_async_int[21] , cp3_async_int[22] , + cp3_async_int[23] , cp3_async_int[24] , + cp3_async_int[25] , cp3_async_int[26] , + cp3_async_int[27] , cp3_async_int[28] , + cp3_async_int[29] , cp3_async_int[30] , + cp3_async_int[31] }) === 33'b100000000000000000000000000000001); +assign tbl_async_exection_list_pt[2] = + (({ cp3_async_int_val , cp3_async_int[0] , + cp3_async_int[1] , cp3_async_int[2] , + cp3_async_int[3] , cp3_async_int[4] , + cp3_async_int[5] , cp3_async_int[6] , + cp3_async_int[7] , cp3_async_int[8] , + cp3_async_int[9] , cp3_async_int[10] , + cp3_async_int[11] , cp3_async_int[12] , + cp3_async_int[13] , cp3_async_int[14] , + cp3_async_int[15] , cp3_async_int[16] , + cp3_async_int[17] , cp3_async_int[18] , + cp3_async_int[19] , cp3_async_int[20] , + cp3_async_int[21] , cp3_async_int[22] , + cp3_async_int[23] , cp3_async_int[24] , + cp3_async_int[25] , cp3_async_int[26] , + cp3_async_int[27] , cp3_async_int[28] , + cp3_async_int[29] , cp3_async_int[30] + }) === 32'b10000000000000000000000000000001); +assign tbl_async_exection_list_pt[3] = + (({ cp3_async_int_val , cp3_async_int[0] , + cp3_async_int[1] , cp3_async_int[2] , + cp3_async_int[3] , cp3_async_int[4] , + cp3_async_int[5] , cp3_async_int[6] , + cp3_async_int[7] , cp3_async_int[8] , + cp3_async_int[9] , cp3_async_int[10] , + cp3_async_int[11] , cp3_async_int[12] , + cp3_async_int[13] , cp3_async_int[14] , + cp3_async_int[15] , cp3_async_int[16] , + cp3_async_int[17] , cp3_async_int[18] , + cp3_async_int[19] , cp3_async_int[20] , + cp3_async_int[21] , cp3_async_int[22] , + cp3_async_int[23] , cp3_async_int[24] , + cp3_async_int[25] , cp3_async_int[26] , + cp3_async_int[27] , cp3_async_int[28] , + cp3_async_int[29] }) === 31'b1000000000000000000000000000001); +assign tbl_async_exection_list_pt[4] = + (({ cp3_async_int_val , cp3_async_int[0] , + cp3_async_int[1] , cp3_async_int[2] , + cp3_async_int[3] , cp3_async_int[4] , + cp3_async_int[5] , cp3_async_int[6] , + cp3_async_int[7] , cp3_async_int[8] , + cp3_async_int[9] , cp3_async_int[10] , + cp3_async_int[11] , cp3_async_int[12] , + cp3_async_int[13] , cp3_async_int[14] , + cp3_async_int[15] , cp3_async_int[16] , + cp3_async_int[17] , cp3_async_int[18] , + cp3_async_int[19] , cp3_async_int[20] , + cp3_async_int[21] , cp3_async_int[22] , + cp3_async_int[23] , cp3_async_int[24] , + cp3_async_int[25] , cp3_async_int[26] , + cp3_async_int[27] , cp3_async_int[28] + }) === 30'b100000000000000000000000000001); +assign tbl_async_exection_list_pt[5] = + (({ cp3_async_int_val , cp3_async_int[0] , + cp3_async_int[1] , cp3_async_int[2] , + cp3_async_int[3] , cp3_async_int[4] , + cp3_async_int[5] , cp3_async_int[6] , + cp3_async_int[7] , cp3_async_int[8] , + cp3_async_int[9] , cp3_async_int[10] , + cp3_async_int[11] , cp3_async_int[12] , + cp3_async_int[13] , cp3_async_int[14] , + cp3_async_int[15] , cp3_async_int[16] , + cp3_async_int[17] , cp3_async_int[18] , + cp3_async_int[19] , cp3_async_int[20] , + cp3_async_int[21] , cp3_async_int[22] , + cp3_async_int[23] , cp3_async_int[24] , + cp3_async_int[25] , cp3_async_int[26] , + cp3_async_int[27] }) === 29'b10000000000000000000000000001); +assign tbl_async_exection_list_pt[6] = + (({ cp3_async_int_val , cp3_async_int[0] , + cp3_async_int[1] , cp3_async_int[2] , + cp3_async_int[3] , cp3_async_int[4] , + cp3_async_int[5] , cp3_async_int[6] , + cp3_async_int[7] , cp3_async_int[8] , + cp3_async_int[9] , cp3_async_int[10] , + cp3_async_int[11] , cp3_async_int[12] , + cp3_async_int[13] , cp3_async_int[14] , + cp3_async_int[15] , cp3_async_int[16] , + cp3_async_int[17] , cp3_async_int[18] , + cp3_async_int[19] , cp3_async_int[20] , + cp3_async_int[21] , cp3_async_int[22] , + cp3_async_int[23] , cp3_async_int[24] , + cp3_async_int[25] , cp3_async_int[26] + }) === 28'b1000000000000000000000000001); +assign tbl_async_exection_list_pt[7] = + (({ cp3_async_int_val , cp3_async_int[0] , + cp3_async_int[1] , cp3_async_int[2] , + cp3_async_int[3] , cp3_async_int[4] , + cp3_async_int[5] , cp3_async_int[6] , + cp3_async_int[7] , cp3_async_int[8] , + cp3_async_int[9] , cp3_async_int[10] , + cp3_async_int[11] , cp3_async_int[12] , + cp3_async_int[13] , cp3_async_int[14] , + cp3_async_int[15] , cp3_async_int[16] , + cp3_async_int[17] , cp3_async_int[18] , + cp3_async_int[19] , cp3_async_int[20] , + cp3_async_int[21] , cp3_async_int[22] , + cp3_async_int[23] , cp3_async_int[24] , + cp3_async_int[25] }) === 27'b100000000000000000000000001); +assign tbl_async_exection_list_pt[8] = + (({ cp3_async_int_val , cp3_async_int[0] , + cp3_async_int[1] , cp3_async_int[2] , + cp3_async_int[3] , cp3_async_int[4] , + cp3_async_int[5] , cp3_async_int[6] , + cp3_async_int[7] , cp3_async_int[8] , + cp3_async_int[9] , cp3_async_int[10] , + cp3_async_int[11] , cp3_async_int[12] , + cp3_async_int[13] , cp3_async_int[14] , + cp3_async_int[15] , cp3_async_int[16] , + cp3_async_int[17] , cp3_async_int[18] , + cp3_async_int[19] , cp3_async_int[20] , + cp3_async_int[21] , cp3_async_int[22] , + cp3_async_int[23] , cp3_async_int[24] + }) === 26'b10000000000000000000000001); +assign tbl_async_exection_list_pt[9] = + (({ cp3_async_int_val , cp3_async_int[0] , + cp3_async_int[1] , cp3_async_int[2] , + cp3_async_int[3] , cp3_async_int[4] , + cp3_async_int[5] , cp3_async_int[6] , + cp3_async_int[7] , cp3_async_int[8] , + cp3_async_int[9] , cp3_async_int[10] , + cp3_async_int[11] , cp3_async_int[12] , + cp3_async_int[13] , cp3_async_int[14] , + cp3_async_int[15] , cp3_async_int[16] , + cp3_async_int[17] , cp3_async_int[18] , + cp3_async_int[19] , cp3_async_int[20] , + cp3_async_int[21] , cp3_async_int[22] , + cp3_async_int[23] }) === 25'b1000000000000000000000001); +assign tbl_async_exection_list_pt[10] = + (({ cp3_async_int_val , cp3_async_int[0] , + cp3_async_int[1] , cp3_async_int[2] , + cp3_async_int[3] , cp3_async_int[4] , + cp3_async_int[5] , cp3_async_int[6] , + cp3_async_int[7] , cp3_async_int[8] , + cp3_async_int[9] , cp3_async_int[10] , + cp3_async_int[11] , cp3_async_int[12] , + cp3_async_int[13] , cp3_async_int[14] , + cp3_async_int[15] , cp3_async_int[16] , + cp3_async_int[17] , cp3_async_int[18] , + cp3_async_int[19] , cp3_async_int[20] , + cp3_async_int[21] , cp3_async_int[22] + }) === 24'b100000000000000000000001); +assign tbl_async_exection_list_pt[11] = + (({ cp3_async_int_val , cp3_async_int[0] , + cp3_async_int[1] , cp3_async_int[2] , + cp3_async_int[3] , cp3_async_int[4] , + cp3_async_int[5] , cp3_async_int[6] , + cp3_async_int[7] , cp3_async_int[8] , + cp3_async_int[9] , cp3_async_int[10] , + cp3_async_int[11] , cp3_async_int[12] , + cp3_async_int[13] , cp3_async_int[14] , + cp3_async_int[15] , cp3_async_int[16] , + cp3_async_int[17] , cp3_async_int[18] , + cp3_async_int[19] , cp3_async_int[20] , + cp3_async_int[21] }) === 23'b10000000000000000000001); +assign tbl_async_exection_list_pt[12] = + (({ cp3_async_int_val , cp3_async_int[0] , + cp3_async_int[1] , cp3_async_int[2] , + cp3_async_int[3] , cp3_async_int[4] , + cp3_async_int[5] , cp3_async_int[6] , + cp3_async_int[7] , cp3_async_int[8] , + cp3_async_int[9] , cp3_async_int[10] , + cp3_async_int[11] , cp3_async_int[12] , + cp3_async_int[13] , cp3_async_int[14] , + cp3_async_int[15] , cp3_async_int[16] , + cp3_async_int[17] , cp3_async_int[18] , + cp3_async_int[19] , cp3_async_int[20] + }) === 22'b1000000000000000000001); +assign tbl_async_exection_list_pt[13] = + (({ cp3_async_int_val , cp3_async_int[0] , + cp3_async_int[1] , cp3_async_int[2] , + cp3_async_int[3] , cp3_async_int[4] , + cp3_async_int[5] , cp3_async_int[6] , + cp3_async_int[7] , cp3_async_int[8] , + cp3_async_int[9] , cp3_async_int[10] , + cp3_async_int[11] , cp3_async_int[12] , + cp3_async_int[13] , cp3_async_int[14] , + cp3_async_int[15] , cp3_async_int[16] , + cp3_async_int[17] , cp3_async_int[18] , + cp3_async_int[19] }) === 21'b100000000000000000001); +assign tbl_async_exection_list_pt[14] = + (({ cp3_async_int_val , cp3_async_int[0] , + cp3_async_int[1] , cp3_async_int[2] , + cp3_async_int[3] , cp3_async_int[4] , + cp3_async_int[5] , cp3_async_int[6] , + cp3_async_int[7] , cp3_async_int[8] , + cp3_async_int[9] , cp3_async_int[10] , + cp3_async_int[11] , cp3_async_int[12] , + cp3_async_int[13] , cp3_async_int[14] , + cp3_async_int[15] , cp3_async_int[16] , + cp3_async_int[17] , cp3_async_int[18] + }) === 20'b10000000000000000001); +assign tbl_async_exection_list_pt[15] = + (({ cp3_async_int_val , cp3_async_int[0] , + cp3_async_int[1] , cp3_async_int[2] , + cp3_async_int[3] , cp3_async_int[4] , + cp3_async_int[5] , cp3_async_int[6] , + cp3_async_int[7] , cp3_async_int[8] , + cp3_async_int[9] , cp3_async_int[10] , + cp3_async_int[11] , cp3_async_int[12] , + cp3_async_int[13] , cp3_async_int[14] , + cp3_async_int[15] , cp3_async_int[16] , + cp3_async_int[17] }) === 19'b1000000000000000001); +assign tbl_async_exection_list_pt[16] = + (({ cp3_async_int_val , cp3_async_int[0] , + cp3_async_int[1] , cp3_async_int[2] , + cp3_async_int[3] , cp3_async_int[4] , + cp3_async_int[5] , cp3_async_int[6] , + cp3_async_int[7] , cp3_async_int[8] , + cp3_async_int[9] , cp3_async_int[10] , + cp3_async_int[11] , cp3_async_int[12] , + cp3_async_int[13] , cp3_async_int[14] , + cp3_async_int[15] , cp3_async_int[16] + }) === 18'b100000000000000001); +assign tbl_async_exection_list_pt[17] = + (({ cp3_async_int_val , cp3_async_int[0] , + cp3_async_int[1] , cp3_async_int[2] , + cp3_async_int[3] , cp3_async_int[4] , + cp3_async_int[5] , cp3_async_int[6] , + cp3_async_int[7] , cp3_async_int[8] , + cp3_async_int[9] , cp3_async_int[10] , + cp3_async_int[11] , cp3_async_int[12] , + cp3_async_int[13] , cp3_async_int[14] , + cp3_async_int[15] }) === 17'b10000000000000001); +assign tbl_async_exection_list_pt[18] = + (({ cp3_async_int_val , cp3_async_int[0] , + cp3_async_int[1] , cp3_async_int[2] , + cp3_async_int[3] , cp3_async_int[4] , + cp3_async_int[5] , cp3_async_int[6] , + cp3_async_int[7] , cp3_async_int[8] , + cp3_async_int[9] , cp3_async_int[10] , + cp3_async_int[11] , cp3_async_int[12] , + cp3_async_int[13] , cp3_async_int[14] + }) === 16'b1000000000000001); +assign tbl_async_exection_list_pt[19] = + (({ cp3_async_int_val , cp3_async_int[0] , + cp3_async_int[1] , cp3_async_int[2] , + cp3_async_int[3] , cp3_async_int[4] , + cp3_async_int[5] , cp3_async_int[6] , + cp3_async_int[7] , cp3_async_int[8] , + cp3_async_int[9] , cp3_async_int[10] , + cp3_async_int[11] , cp3_async_int[12] + }) === 14'b10000000000001); +assign tbl_async_exection_list_pt[20] = + (({ cp3_async_int_val , cp3_async_int[0] , + cp3_async_int[1] , cp3_async_int[2] , + cp3_async_int[3] , cp3_async_int[4] , + cp3_async_int[5] , cp3_async_int[6] , + cp3_async_int[7] , cp3_async_int[8] , + cp3_async_int[9] , cp3_async_int[10] , + cp3_async_int[11] }) === 13'b1000000000001); +assign tbl_async_exection_list_pt[21] = + (({ cp3_async_int_val , cp3_async_int[0] , + cp3_async_int[1] , cp3_async_int[2] , + cp3_async_int[3] , cp3_async_int[4] , + cp3_async_int[5] , cp3_async_int[6] , + cp3_async_int[9] , cp3_async_int[10] , + cp3_async_int[11] , cp3_async_int[12] , + cp3_async_int[13] }) === 13'b1000000000001); +assign tbl_async_exection_list_pt[22] = + (({ cp3_async_int_val , cp3_async_int[0] , + cp3_async_int[1] , cp3_async_int[2] , + cp3_async_int[3] , cp3_async_int[4] , + cp3_async_int[5] , cp3_async_int[6] , + cp3_async_int[7] , cp3_async_int[8] , + cp3_async_int[9] , cp3_async_int[10] + }) === 12'b100000000001); +assign tbl_async_exection_list_pt[23] = + (({ cp3_async_int_val , cp3_async_int[0] , + cp3_async_int[1] , cp3_async_int[2] , + cp3_async_int[3] , cp3_async_int[4] , + cp3_async_int[5] , cp3_async_int[6] , + cp3_async_int[7] , cp3_async_int[8] , + cp3_async_int[9] }) === 11'b10000000001); +assign tbl_async_exection_list_pt[24] = + (({ cp3_async_int_val , cp3_async_int[0] , + cp3_async_int[1] , cp3_async_int[2] , + cp3_async_int[3] , cp3_async_int[4] , + cp3_async_int[5] , cp3_async_int[6] , + cp3_async_int[7] , cp3_async_int[8] + }) === 10'b1000000001); +assign tbl_async_exection_list_pt[25] = + (({ cp3_async_int_val , cp3_async_int[0] , + cp3_async_int[1] , cp3_async_int[2] , + cp3_async_int[3] , dis_mm_mchk + }) === 6'b100011); +assign tbl_async_exection_list_pt[26] = + (({ cp3_async_int_val , cp3_async_int[0] , + cp3_async_int[1] , cp3_async_int[2] , + cp3_async_int[3] , dis_mm_mchk + }) === 6'b100010); +assign tbl_async_exection_list_pt[27] = + (({ cp3_async_int_val , cp3_async_int[0] , + cp3_async_int[1] , cp3_async_int[2] , + dis_mm_mchk }) === 5'b10011); +assign tbl_async_exection_list_pt[28] = + (({ cp3_async_int_val , cp3_async_int[0] , + cp3_async_int[1] , cp3_async_int[2] , + dis_mm_mchk }) === 5'b10010); +assign tbl_async_exection_list_pt[29] = + (({ cp3_async_int_val , cp3_async_int[0] , + cp3_async_int[1] , cp3_async_int[2] , + cp3_async_int[3] , cp3_async_int[4] , + cp3_async_int[5] , cp3_async_int[6] , + cp3_async_int[7] }) === 9'b100000001); +assign tbl_async_exection_list_pt[30] = + (({ cp3_async_int_val , cp3_async_int[0] , + cp3_async_int[1] , dis_mm_mchk + }) === 4'b1011); +assign tbl_async_exection_list_pt[31] = + (({ cp3_async_int_val , cp3_async_int[0] , + cp3_async_int[1] , dis_mm_mchk + }) === 4'b1010); +assign tbl_async_exection_list_pt[32] = + (({ cp3_async_int_val , cp3_async_int[0] , + cp3_async_int[1] , cp3_async_int[2] , + cp3_async_int[3] , cp3_async_int[4] , + cp3_async_int[5] , cp3_async_int[6] + }) === 8'b10000001); +assign tbl_async_exection_list_pt[33] = + (({ cp3_async_int_val , cp3_async_int[0] , + cp3_async_int[1] , cp3_async_int[2] , + cp3_async_int[3] , cp3_async_int[4] , + cp3_async_int[5] }) === 7'b1000001); +assign tbl_async_exection_list_pt[34] = + (({ cp3_async_int_val , cp3_async_int[0] , + cp3_async_int[1] , cp3_async_int[2] , + cp3_async_int[3] , cp3_async_int[4] + }) === 6'b100001); +assign tbl_async_exection_list_pt[35] = + (({ cp3_async_int_val , cp3_async_int[0] + }) === 2'b11); +assign instr_tlb_async = + (tbl_async_exection_list_pt[35]); +assign pt_fault_async = + (tbl_async_exection_list_pt[34]); +assign lrat_miss_async = + (tbl_async_exection_list_pt[32]); +assign tlb_inelig_async = + (tbl_async_exection_list_pt[33]); +assign tlb_multi_async = + (tbl_async_exection_list_pt[25] | tbl_async_exection_list_pt[26] + ); +assign tlb_par_async = + (tbl_async_exection_list_pt[27] | tbl_async_exection_list_pt[28] + ); +assign tlb_lru_par_async = + (tbl_async_exection_list_pt[30] | tbl_async_exection_list_pt[31] + ); +assign debug_icmp = + (tbl_async_exection_list_pt[29]); +assign debug_irpt = + (tbl_async_exection_list_pt[24]); +assign debug_async = + (tbl_async_exection_list_pt[15] | tbl_async_exection_list_pt[21] + | tbl_async_exection_list_pt[24] | tbl_async_exection_list_pt[29] + ); +assign mchk_ext_async = + (tbl_async_exection_list_pt[17]); +assign program_fp_en_async = + (tbl_async_exection_list_pt[18]); +assign guest_dbell_mchk_async = + (tbl_async_exection_list_pt[16]); +assign perf_async = + (tbl_async_exection_list_pt[1]); +assign ude_input_async = + (tbl_async_exection_list_pt[15]); +assign crit_input_async = + (tbl_async_exection_list_pt[14]); +assign wdog_async = + (tbl_async_exection_list_pt[13]); +assign guest_wdog_async = + (tbl_async_exection_list_pt[12]); +assign dbell_crit_async = + (tbl_async_exection_list_pt[11]); +assign guest_dbell_crit_async = + (tbl_async_exection_list_pt[10]); +assign external_async = + (tbl_async_exection_list_pt[9]); +assign fit_async = + (tbl_async_exection_list_pt[8]); +assign guest_fit_async = + (tbl_async_exection_list_pt[7]); +assign dec_async = + (tbl_async_exection_list_pt[6]); +assign guest_dec_async = + (tbl_async_exection_list_pt[5]); +assign dbell_async = + (tbl_async_exection_list_pt[4]); +assign guest_dbell_async = + (tbl_async_exection_list_pt[3]); +assign user_dec_async = + (tbl_async_exection_list_pt[2]); +assign dp_cp_async = + (tbl_async_exection_list_pt[23]); +assign dp_cp_async_bus_snoop = + (tbl_async_exection_list_pt[22]); +assign async_np1 = + (tbl_async_exection_list_pt[20]); +assign pc_stop = + (tbl_async_exection_list_pt[19]); +assign async_n = + (tbl_async_exection_list_pt[19] | tbl_async_exection_list_pt[25] + | tbl_async_exection_list_pt[27] | tbl_async_exection_list_pt[30] + ); +assign fp_async = + (tbl_async_exection_list_pt[18]); +assign st_async = + 1'b0; +assign dlk_async[0] = + 1'b0; +assign dlk_async[1] = + 1'b0; +assign ap_async = + 1'b0; +assign bo_async = + 1'b0; +assign tlbi_async = + (tbl_async_exection_list_pt[33]); +assign pt_async = + (tbl_async_exection_list_pt[32] | tbl_async_exection_list_pt[34] + ); +assign spv_async = + 1'b0; +assign epid_async = + 1'b0; +assign pil_async = + 1'b0; +assign ppr_async = + 1'b0; +assign ptr_async = + 1'b0; +assign puo_async = + 1'b0; +assign pie_async = + (tbl_async_exection_list_pt[18]); +assign uct_async = + 1'b0; +assign data_async = + 1'b0; +assign esr_async = + (tbl_async_exection_list_pt[18] | tbl_async_exection_list_pt[32] + | tbl_async_exection_list_pt[33] | tbl_async_exection_list_pt[34] + ); +assign crit_async = + (tbl_async_exection_list_pt[10] | tbl_async_exection_list_pt[11] + | tbl_async_exection_list_pt[12] | tbl_async_exection_list_pt[13] + | tbl_async_exection_list_pt[14] | tbl_async_exection_list_pt[15] + | tbl_async_exection_list_pt[16] | tbl_async_exection_list_pt[21] + | tbl_async_exection_list_pt[24] | tbl_async_exection_list_pt[29] + ); +assign mcheck_async = + (tbl_async_exection_list_pt[17] | tbl_async_exection_list_pt[26] + | tbl_async_exection_list_pt[28] | tbl_async_exection_list_pt[31] + ); +assign guest_async = + (tbl_async_exection_list_pt[5] | tbl_async_exection_list_pt[7] + ); +assign irpt_taken_async = + (tbl_async_exection_list_pt[1] | tbl_async_exection_list_pt[2] + | tbl_async_exection_list_pt[3] | tbl_async_exection_list_pt[4] + | tbl_async_exection_list_pt[5] | tbl_async_exection_list_pt[6] + | tbl_async_exection_list_pt[7] | tbl_async_exection_list_pt[8] + | tbl_async_exection_list_pt[9] | tbl_async_exection_list_pt[18] + | tbl_async_exection_list_pt[32] | tbl_async_exection_list_pt[33] + | tbl_async_exection_list_pt[34] | tbl_async_exection_list_pt[35] + ); + +//assign_end + + + assign select_i0_p1 = i0_p1 & ((~(i0_check_next)) | (~(i1_comp))); + assign select_i1_p1 = i1_p1 & i0_check_next; + assign select_i0_bta = i0_bta & ((~(i0_check_next)) | (~(i1_comp))); + assign select_i1_bta = i1_bta & i0_check_next; + assign select_i0_bp_bta = i0_bp_bta & ((~(i0_check_next)) | (~(i1_comp))); + assign select_i1_bp_bta = i1_bp_bta & i0_check_next; + assign select_ucode_p1 = (i0_ucode_p1 & ((~(i0_check_next)) | (~(i1_comp)))) | (i1_ucode_p1 & i0_check_next); + assign select_reset = (i0_reset & ((~(i0_check_next)) | (~(i1_comp)))) | (i1_reset & i0_check_next); + assign select_mtiar = (i0_complete & i0_mtiar) | (i1_complete & i1_mtiar & i0_check_next); + // Temp + assign iu_pc_i0_comp = i0_comp; + assign iu_pc_i1_comp = i1_comp & i0_check_next; + + assign db_mask = ({19{~(cp3_async_int_val | cp3_iu_excvec_val | cp3_lq_excvec_val | cp3_xu_excvec_val | cp3_axu_excvec_val)}} & {19{1'b1}}) | + ({19{cp3_iu_excvec_val}} & iu_db_mask) | + ({19{cp3_lq_excvec_val}} & lq_db_mask) | + ({19{cp3_xu_excvec_val}} & xu_db_mask) | + ({19{cp3_axu_excvec_val}} & axu_db_mask); + + generate + begin : xhdl0 + genvar i; + for (i = 0; i <= (19 - 1); i = i + 1) + begin : cp3_db_mask + if (i == 1) + begin : R0 + assign cp3_db_events_masked[i] = db_mask[i] & cp3_db_events[i] & ~(cp3_rfi | cp3_attn); + end + if (i == 3) + begin : R1 + assign cp3_db_events_masked[i] = 1'b0; + end + if ((i != 1) & (i != 3)) + begin : R2 + assign cp3_db_events_masked[i] = db_mask[i] & cp3_db_events[i]; + end + end + end + endgenerate + + assign cp3_db_int_events_val = dbg_int_en & cp3_db_val & |{cp3_db_events_masked[0],(cp3_db_events_masked[1] & ~cp3_icmp_block),cp3_db_events_masked[2:18]}; + assign cp3_db_events_masked_reduced = cp3_db_int_events_val; + assign cp3_asyn_irpt_needed = (dbg_int_en & cp3_db_val & cp3_db_events[3] & db_mask[3] & ~cp3_db_events_masked[4]) | (dbg_int_en & irpt_enable & irpt_taken_async); + assign cp3_asyn_irpt_taken = debug_irpt; + assign cp3_asyn_icmp_needed = dbg_int_en & cp3_db_val & cp3_db_events[1] & (cp3_rfi | cp3_attn); + assign cp3_asyn_icmp_taken = debug_icmp; + assign debug_irpt_int_dis = (((db_mask[3] & cp3_db_events[3] & (~(dbg_int_en))) | (~dbg_int_en & irpt_enable & irpt_taken_async)) & (~(epcr_duvd & ~guest_int)) ); + assign debug_icmp_excep = dbg_int_en & icmp_enable & cp3_db_val & cp3_icmp_excep & (~(cp3_db_int_events_val)); + assign dbsr_update = |(cp3_db_events_masked) | + debug_icmp | + debug_irpt | + debug_irpt_int_dis | + debug_icmp_excep | + ude_input_async; + + assign cp3_dbsr = ({19{~(debug_icmp | debug_irpt)}} & cp3_db_events_masked) | + ({19{debug_icmp}} & 19'b0100000000000000000) | + ({19{debug_irpt | debug_irpt_int_dis}} & 19'b0001000000000000000) | + ({19{debug_icmp_excep}} & 19'b0100000000000000000) | + ({19{ude_input_async}} & 19'b1000000000000000000); + + assign dear_update = (~(cp3_db_int_events_val)) & (lrat_lq | data_tlb_lq | data_storage_lq | data_storage_hv_lq | data_storage_xu | alignment_lq); + assign esr_update = (~(cp3_db_int_events_val)) & (esr_iu | esr_lq | esr_xu | esr_axu | esr_async); + assign cp3_exc_nia[62 - `EFF_IFAR_ARCH:51] = ((~guest_int) ? ({({32{epcr_icm}} & spr_ivpr[0:31]), spr_ivpr[32:51]}) : 0) | + ((guest_int | guest_wdog_async) ? ({({32{epcr_gicm}} & spr_givpr[0:31]), spr_givpr[32:51]}) : 0); + + assign cp3_exc_nia[52:61] = ((~(cp3_db_int_events_val) & (mcheck_iu | mcheck_lq | mcheck_xu | mcheck_async)) ? 10'b0000000000 : 10'b0000000000) | + (cp3_db_int_events_val ? 10'b0000010000 : 10'b0000000000) | + ((~(cp3_db_int_events_val) & (instr_tlb_async | instruction_tlb_iu)) ? 10'b0001111000 : 10'b0000000000) | + ((~(cp3_db_int_events_val) & (instruction_storage_iu | pt_fault_async | tlb_inelig_async)) ? 10'b0000100000 : 10'b0000000000) | + ((~(cp3_db_int_events_val) & instruction_storage_hv_iu) ? 10'b0000100000 : 10'b0000000000) | + ((~(cp3_db_int_events_val) & system_call_iu) ? 10'b0001001000 : 10'b0000000000) | + ((~(cp3_db_int_events_val) & system_call_hyp_iu) ? 10'b0011000000 : 10'b0000000000) | + ((~(cp3_db_int_events_val) & (lrat_lq | lrat_xu | lrat_miss_async)) ? 10'b0011010000 : 10'b0000000000) | + ((~(cp3_db_int_events_val) & (fp_unavailable_lq | fp_unavailable_axu)) ? 10'b0001000000 : 10'b0000000000) | + ((~(cp3_db_int_events_val) & (ap_unavailable_lq | ap_unavailable_axu)) ? 10'b0001010000 : 10'b0000000000) | + ((~(cp3_db_int_events_val) & (vec_unavailable_lq | vec_unavailable_axu)) ? 10'b0010000000 : 10'b0000000000) | + ((~(cp3_db_int_events_val) & (program_iu | program_lq | program_xu | program_fp_axu | program_ap_axu)) ? 10'b0000111000 : 10'b0000000000) | + ((~(cp3_db_int_events_val) & (data_tlb_lq | tlb_xu)) ? 10'b0001110000 : 10'b0000000000) | + ((~(cp3_db_int_events_val) & (data_storage_lq | data_storage_xu)) ? 10'b0000011000 : 10'b0000000000) | + ((~(cp3_db_int_events_val) & data_storage_hv_lq) ? 10'b0000011000 : 10'b0000000000) | + ((~(cp3_db_int_events_val) & alignment_lq) ? 10'b0000110000 : 10'b0000000000) | + ((~(cp3_db_int_events_val) & (hyp_priv_iu | hyp_priv_lq | hyp_priv_xu)) ? 10'b0011001000 : 10'b0000000000) | + ((~(cp3_db_int_events_val) & program_fp_en_async) ? 10'b0000111000 : 10'b0000000000) | + ((~(cp3_db_int_events_val) & guest_dbell_mchk_async) ? 10'b0010111000 : 10'b0000000000) | + ((~(cp3_db_int_events_val) & debug_async) ? 10'b0000010000 : 10'b0000000000) | + ((~(cp3_db_int_events_val) & perf_async) ? 10'b1000001000 : 10'b0000000000) | + ((~(cp3_db_int_events_val) & crit_input_async) ? 10'b0000001000 : 10'b0000000000) | + ((~(cp3_db_int_events_val) & (wdog_async | guest_wdog_async)) ? 10'b0001101000 : 10'b0000000000) | + ((~(cp3_db_int_events_val) & dbell_crit_async) ? 10'b0010101000 : 10'b0000000000) | + ((~(cp3_db_int_events_val) & guest_dbell_crit_async) ? 10'b0010111000 : 10'b0000000000) | + ((~(cp3_db_int_events_val) & external_async) ? 10'b0000101000 : 10'b0000000000) | + ((~(cp3_db_int_events_val) & (fit_async | guest_fit_async)) ? 10'b0001100000 : 10'b0000000000) | + ((~(cp3_db_int_events_val) & (dec_async | guest_dec_async)) ? 10'b0001011000 : 10'b0000000000) | + ((~(cp3_db_int_events_val) & dbell_async) ? 10'b0010100000 : 10'b0000000000) | + ((~(cp3_db_int_events_val) & guest_dbell_async) ? 10'b0010110000 : 10'b0000000000) | + ((~(cp3_db_int_events_val) & user_dec_async) ? 10'b1000000000 : 10'b0000000000); + + assign cp3_exc_esr[0] = (~(cp3_db_int_events_val)) & (pil_iu | pil_lq | pil_xu | pil_axu | pil_async); + assign cp3_exc_esr[1] = (~(cp3_db_int_events_val)) & (ppr_iu | ppr_lq | ppr_xu | ppr_axu | ppr_async); + assign cp3_exc_esr[2] = (~(cp3_db_int_events_val)) & (ptr_iu | ptr_lq | ptr_xu | ptr_axu | ptr_async); + assign cp3_exc_esr[3] = (~(cp3_db_int_events_val)) & (((fp_iu | fp_lq | fp_xu | fp_axu) & cp3_fp) | fp_async); + assign cp3_exc_esr[4] = (~(cp3_db_int_events_val)) & ((st_iu | st_lq | st_xu | st_axu | st_async) & cp3_st); + assign cp3_exc_esr[5:6] = ({2{~cp3_db_int_events_val}} & (dlk_iu | dlk_lq | dlk_xu | dlk_axu | dlk_async)); + assign cp3_exc_esr[7] = (~(cp3_db_int_events_val)) & ((ap_iu | ap_lq | ap_xu | ap_axu | ap_async) & cp3_ap); + assign cp3_exc_esr[8] = (~(cp3_db_int_events_val)) & (puo_iu | puo_lq | puo_xu | puo_axu | puo_async); + assign cp3_exc_esr[9] = (~(cp3_db_int_events_val)) & (bo_iu | bo_lq | bo_xu | bo_axu | bo_async); + assign cp3_exc_esr[10] = (~(cp3_db_int_events_val)) & (pie_iu | pie_lq | pie_xu | pie_axu | pie_async); + assign cp3_exc_esr[11] = (~(cp3_db_int_events_val)) & (uct_iu | uct_lq | uct_xu | uct_axu | uct_async); + assign cp3_exc_esr[12] = (~(cp3_db_int_events_val)) & (data_iu | data_lq | data_xu | data_axu | data_async); + assign cp3_exc_esr[13] = (~(cp3_db_int_events_val)) & (tlbi_iu | tlbi_lq | tlbi_xu | tlbi_axu | tlbi_async); + assign cp3_exc_esr[14] = (~(cp3_db_int_events_val)) & (pt_iu | pt_lq | pt_xu | pt_axu | pt_async); + assign cp3_exc_esr[15] = (~(cp3_db_int_events_val)) & ((spv_iu | spv_lq | spv_xu | spv_axu | spv_async) & cp3_spv); + assign cp3_exc_esr[16] = (~(cp3_db_int_events_val)) & ((epid_iu | epid_lq | epid_xu | epid_axu | epid_async) & cp3_epid); + + assign cp3_exc_mcsr[0] = (~(cp3_db_int_events_val)) & 1'b0; + assign cp3_exc_mcsr[1] = (~(cp3_db_int_events_val)) & dcache_dir_multi_lq; + assign cp3_exc_mcsr[2] = (~(cp3_db_int_events_val)) & tlb_snoop_rej_async; + assign cp3_exc_mcsr[3] = (~(cp3_db_int_events_val)) & (tlb_lru_par_async | tlb_lru_par_lq | tlb_lru_par_xu); + assign cp3_exc_mcsr[4] = (~(cp3_db_int_events_val)) & icache_l2_ecc_iu; + assign cp3_exc_mcsr[5] = (~(cp3_db_int_events_val)) & dcache_l2_ecc_lq; + assign cp3_exc_mcsr[6] = (~(cp3_db_int_events_val)) & dcache_dir_par_lq; + assign cp3_exc_mcsr[7] = (~(cp3_db_int_events_val)) & mchk_ext_async; + assign cp3_exc_mcsr[8] = (~(cp3_db_int_events_val)) & dcache_par_lq; + assign cp3_exc_mcsr[9] = (~(cp3_db_int_events_val)) & ierat_multi_iu; + assign cp3_exc_mcsr[10] = (~(cp3_db_int_events_val)) & derat_multi_lq; + assign cp3_exc_mcsr[11] = (~(cp3_db_int_events_val)) & (tlb_multi_async | tlb_multi_lq | tlb_multi_xu); + assign cp3_exc_mcsr[12] = (~(cp3_db_int_events_val)) & (ierat_par_iu | ierat_par_xu); + assign cp3_exc_mcsr[13] = (~(cp3_db_int_events_val)) & (derat_par_lq | derat_par_xu); + assign cp3_exc_mcsr[14] = (~(cp3_db_int_events_val)) & (tlb_par_async | tlb_par_lq | tlb_par_xu); + + assign eheir_update = hyp_priv_iu | hyp_priv_lq | hyp_priv_xu; + assign dp_cp_async_flush = dp_cp_async; + assign dp_cp_async_bus_snoop_flush = dp_cp_async_bus_snoop; + assign async_np1_flush = async_np1; + assign async_n_flush = (async_n | n_flush_iu); + assign mm_iu_exception = (instr_tlb_async | instr_tlb_async | pt_fault_async | lrat_miss_async | tlb_inelig_async | + tlb_multi_async | tlb_par_async | tlb_lru_par_async); + assign pc_iu_stop = pc_stop; + assign mc_int = ~cp3_db_int_events_val & (mcheck_iu | mcheck_lq | mcheck_xu | mcheck_async) & (msr_me | msr_gs); + assign cp3_mchk_disabled = ~cp3_db_int_events_val & (mcheck_iu | mcheck_lq | mcheck_xu | mcheck_async) & ~(msr_me | msr_gs); + assign g_int = guest_int; + assign guest_int = (~(cp3_db_int_events_val)) & + (((instr_tlb_async | instruction_tlb_iu) & msr_gs & epcr_itlbgs) | + ((instruction_storage_iu | pt_fault_async | tlb_inelig_async) & msr_gs & epcr_isigs) | + ((data_tlb_lq | tlb_xu) & msr_gs & epcr_dtlbgs) | + ((data_storage_lq | data_storage_xu) & msr_gs & epcr_dsigs) | + (external_async & epcr_extgs) | + (system_call_iu & msr_gs) | + guest_async); + + assign c_int = cp3_db_int_events_val | crit_async; + assign dbell_taken = dbell_async; + assign cdbell_taken = dbell_crit_async; + assign gdbell_taken = guest_dbell_async; + assign gcdbell_taken = guest_dbell_crit_async; + assign gmcdbell_taken = guest_dbell_mchk_async; + + //------------------------------------------------------------------------------------------------------------------ + // cp_mm except bus + //------------------------------------------------------------------------------------------------------------------ + // I-Side D-Side + // 0 Valid + // 1 I=0/D=1 + // + // 2 TLB Miss instruction_tlb_iu | data_tlb_lq | + // instr_tlb_async tlb_xu + // + // 3 Storage instruction_storage_iu | data_storage_lq | + // pt_fault_async | data_storage_xu + // tlb_inelig_async + // + // 4 LRAT Miss lrat_miss_async lrat_lq | lrat_xu | lrat_miss_async + // + // 5 Machine Check ierat_multi_iu | derat_par_lq | + // ierat_par_iu derat_multi_lq | + // ierat_par_xu derat_par_xu | + // tlb_multi_async | tlb_lru_par_lq | + // tlb_par_async | tlb_multi_lq | + // tlb_lru_par_async tlb_par_lq + // tlb_lru_par_xu + // tlb_multi_xu + // tlb_par_xu + // tlb_snoop_rej_async + + + + // Bit 2 + //ITLB Miss + assign cp_mm_itlb_miss = instruction_tlb_iu | instr_tlb_async; + // DTLB Miss + assign cp_mm_dtlb_miss = data_tlb_lq | tlb_xu; + + // Bit 3 + // ISI + assign cp_mm_isi = instruction_storage_iu | pt_fault_async | tlb_inelig_async; + // DSI + assign cp_mm_dsi = ( data_storage_xu | // TLBI + (cp3_lq_excvec_val & + ((cp3_lq_excvec == 6'b010000) | // PT Fault + (cp3_lq_excvec == 6'b010001) | // TLBI + (cp3_lq_excvec == 6'b010101) | // Virtualization Fault bit set + (cp3_lq_excvec == 6'b010110)))); // R/W/E Access violation + + // Bit 4 + // ILRAT Miss + assign cp_mm_ilrat_miss = lrat_miss_async; + // DLRAT Miss + assign cp_mm_dlrat_miss = lrat_lq | lrat_xu; + + // Bit 5 + // I-Side Machine Checks + assign cp_mm_imchk = ierat_multi_iu | ierat_par_iu | ierat_par_xu | tlb_multi_async | tlb_par_async | tlb_lru_par_async; + // D-Side Machine Checks + assign cp_mm_dmchk = (derat_par_lq | derat_multi_lq | derat_par_xu | + tlb_lru_par_lq | tlb_multi_lq | tlb_par_lq | + tlb_lru_par_xu | tlb_multi_xu | tlb_par_xu | + tlb_snoop_rej_async); + + +endmodule diff --git a/dev/verilog/work/iuq_cpl_top.v b/dev/verilog/work/iuq_cpl_top.v new file mode 100755 index 0000000..421a209 --- /dev/null +++ b/dev/verilog/work/iuq_cpl_top.v @@ -0,0 +1,1539 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: Completion Unit +// +//***************************************************************************** + +`include "tri_a2o.vh" + +module iuq_cpl_top( + // Clocks + (* pin_data="PIN_FUNCTION=/G_CLK/" *) + input [0:`NCLK_WIDTH-1] nclk, + + // Pervasive + input tc_ac_ccflush_dc, + input clkoff_dc_b, + input d_mode_dc, + input delay_lclkr_dc, + input mpw1_dc_b, + input mpw2_dc_b, + input pc_iu_func_sl_thold_2, + input pc_iu_func_slp_sl_thold_2, + input pc_iu_sg_2, + input [0:`THREADS] cp_scan_in, + output [0:`THREADS] cp_scan_out, + + // Perfomance selectors + input pc_iu_event_bus_enable, + input [0:2] pc_iu_event_count_mode, + + input [0:31] spr_cp_perf_event_mux_ctrls, + input [0:4*`THREADS-1] event_bus_in, + output [0:4*`THREADS-1] event_bus_out, + + // Instruction 0 Issue + input rn_cp_iu6_t0_i0_vld, + input [1:`ITAG_SIZE_ENC-1] rn_cp_iu6_t0_i0_itag, + input [0:2] rn_cp_iu6_t0_i0_ucode, + input rn_cp_iu6_t0_i0_fuse_nop, + input rn_cp_iu6_t0_i0_rte_lq, + input rn_cp_iu6_t0_i0_rte_sq, + input rn_cp_iu6_t0_i0_rte_fx0, + input rn_cp_iu6_t0_i0_rte_fx1, + input rn_cp_iu6_t0_i0_rte_axu0, + input rn_cp_iu6_t0_i0_rte_axu1, + + input [62-`EFF_IFAR_WIDTH:61] rn_cp_iu6_t0_i0_ifar, + input [62-`EFF_IFAR_WIDTH:61] rn_cp_iu6_t0_i0_bta, + input rn_cp_iu6_t0_i0_isram, + input [0:31] rn_cp_iu6_t0_i0_instr, + + input rn_cp_iu6_t0_i0_valop, + input [0:2] rn_cp_iu6_t0_i0_error, + input rn_cp_iu6_t0_i0_br_pred, + input rn_cp_iu6_t0_i0_bh_update, + input [0:1] rn_cp_iu6_t0_i0_bh0_hist, + input [0:1] rn_cp_iu6_t0_i0_bh1_hist, + input [0:1] rn_cp_iu6_t0_i0_bh2_hist, + input [0:9] rn_cp_iu6_t0_i0_gshare, + input [0:2] rn_cp_iu6_t0_i0_ls_ptr, + input rn_cp_iu6_t0_i0_match, + + input rn_cp_iu6_t0_i0_type_fp, + input rn_cp_iu6_t0_i0_type_ap, + input rn_cp_iu6_t0_i0_type_spv, + input rn_cp_iu6_t0_i0_type_st, + input rn_cp_iu6_t0_i0_async_block, + input rn_cp_iu6_t0_i0_np1_flush, + + input rn_cp_iu6_t0_i0_t1_v, + input [0:2] rn_cp_iu6_t0_i0_t1_t, + input [0:`GPR_POOL_ENC-1] rn_cp_iu6_t0_i0_t1_p, + input [0:`GPR_POOL_ENC-1] rn_cp_iu6_t0_i0_t1_a, + + input rn_cp_iu6_t0_i0_t2_v, + input [0:2] rn_cp_iu6_t0_i0_t2_t, + input [0:`GPR_POOL_ENC-1] rn_cp_iu6_t0_i0_t2_p, + input [0:`GPR_POOL_ENC-1] rn_cp_iu6_t0_i0_t2_a, + + input rn_cp_iu6_t0_i0_t3_v, + input [0:2] rn_cp_iu6_t0_i0_t3_t, + input [0:`GPR_POOL_ENC-1] rn_cp_iu6_t0_i0_t3_p, + input [0:`GPR_POOL_ENC-1] rn_cp_iu6_t0_i0_t3_a, + + input rn_cp_iu6_t0_i0_btb_entry, + input [0:1] rn_cp_iu6_t0_i0_btb_hist, + input rn_cp_iu6_t0_i0_bta_val, + + // Instruction 1 Issue + input rn_cp_iu6_t0_i1_vld, + input [1:`ITAG_SIZE_ENC-1] rn_cp_iu6_t0_i1_itag, + input [0:2] rn_cp_iu6_t0_i1_ucode, + input rn_cp_iu6_t0_i1_fuse_nop, + input rn_cp_iu6_t0_i1_rte_lq, + input rn_cp_iu6_t0_i1_rte_sq, + input rn_cp_iu6_t0_i1_rte_fx0, + input rn_cp_iu6_t0_i1_rte_fx1, + input rn_cp_iu6_t0_i1_rte_axu0, + input rn_cp_iu6_t0_i1_rte_axu1, + + input [62-`EFF_IFAR_WIDTH:61] rn_cp_iu6_t0_i1_ifar, + input [62-`EFF_IFAR_WIDTH:61] rn_cp_iu6_t0_i1_bta, + input rn_cp_iu6_t0_i1_isram, + input [0:31] rn_cp_iu6_t0_i1_instr, + + input rn_cp_iu6_t0_i1_valop, + input [0:2] rn_cp_iu6_t0_i1_error, + input rn_cp_iu6_t0_i1_br_pred, + input rn_cp_iu6_t0_i1_bh_update, + input [0:1] rn_cp_iu6_t0_i1_bh0_hist, + input [0:1] rn_cp_iu6_t0_i1_bh1_hist, + input [0:1] rn_cp_iu6_t0_i1_bh2_hist, + input [0:9] rn_cp_iu6_t0_i1_gshare, + input [0:2] rn_cp_iu6_t0_i1_ls_ptr, + input rn_cp_iu6_t0_i1_match, + + input rn_cp_iu6_t0_i1_type_fp, + input rn_cp_iu6_t0_i1_type_ap, + input rn_cp_iu6_t0_i1_type_spv, + input rn_cp_iu6_t0_i1_type_st, + input rn_cp_iu6_t0_i1_async_block, + input rn_cp_iu6_t0_i1_np1_flush, + + input rn_cp_iu6_t0_i1_t1_v, + input [0:2] rn_cp_iu6_t0_i1_t1_t, + input [0:`GPR_POOL_ENC-1] rn_cp_iu6_t0_i1_t1_p, + input [0:`GPR_POOL_ENC-1] rn_cp_iu6_t0_i1_t1_a, + + input rn_cp_iu6_t0_i1_t2_v, + input [0:2] rn_cp_iu6_t0_i1_t2_t, + input [0:`GPR_POOL_ENC-1] rn_cp_iu6_t0_i1_t2_p, + input [0:`GPR_POOL_ENC-1] rn_cp_iu6_t0_i1_t2_a, + + input rn_cp_iu6_t0_i1_t3_v, + input [0:2] rn_cp_iu6_t0_i1_t3_t, + input [0:`GPR_POOL_ENC-1] rn_cp_iu6_t0_i1_t3_p, + input [0:`GPR_POOL_ENC-1] rn_cp_iu6_t0_i1_t3_a, + + input rn_cp_iu6_t0_i1_btb_entry, + input [0:1] rn_cp_iu6_t0_i1_btb_hist, + input rn_cp_iu6_t0_i1_bta_val, + +`ifndef THREADS1 + // Instruction 0 Issue + input rn_cp_iu6_t1_i0_vld, + input [1:`ITAG_SIZE_ENC-1] rn_cp_iu6_t1_i0_itag, + input [0:2] rn_cp_iu6_t1_i0_ucode, + input rn_cp_iu6_t1_i0_fuse_nop, + input rn_cp_iu6_t1_i0_rte_lq, + input rn_cp_iu6_t1_i0_rte_sq, + input rn_cp_iu6_t1_i0_rte_fx0, + input rn_cp_iu6_t1_i0_rte_fx1, + input rn_cp_iu6_t1_i0_rte_axu0, + input rn_cp_iu6_t1_i0_rte_axu1, + + input [62-`EFF_IFAR_WIDTH:61] rn_cp_iu6_t1_i0_ifar, + input [62-`EFF_IFAR_WIDTH:61] rn_cp_iu6_t1_i0_bta, + input rn_cp_iu6_t1_i0_isram, + input [0:31] rn_cp_iu6_t1_i0_instr, + + input rn_cp_iu6_t1_i0_valop, + input [0:2] rn_cp_iu6_t1_i0_error, + input rn_cp_iu6_t1_i0_br_pred, + input rn_cp_iu6_t1_i0_bh_update, + input [0:1] rn_cp_iu6_t1_i0_bh0_hist, + input [0:1] rn_cp_iu6_t1_i0_bh1_hist, + input [0:1] rn_cp_iu6_t1_i0_bh2_hist, + input [0:9] rn_cp_iu6_t1_i0_gshare, + input [0:2] rn_cp_iu6_t1_i0_ls_ptr, + input rn_cp_iu6_t1_i0_match, + + input rn_cp_iu6_t1_i0_type_fp, + input rn_cp_iu6_t1_i0_type_ap, + input rn_cp_iu6_t1_i0_type_spv, + input rn_cp_iu6_t1_i0_type_st, + input rn_cp_iu6_t1_i0_async_block, + input rn_cp_iu6_t1_i0_np1_flush, + + input rn_cp_iu6_t1_i0_t1_v, + input [0:2] rn_cp_iu6_t1_i0_t1_t, + input [0:`GPR_POOL_ENC-1] rn_cp_iu6_t1_i0_t1_p, + input [0:`GPR_POOL_ENC-1] rn_cp_iu6_t1_i0_t1_a, + + input rn_cp_iu6_t1_i0_t2_v, + input [0:2] rn_cp_iu6_t1_i0_t2_t, + input [0:`GPR_POOL_ENC-1] rn_cp_iu6_t1_i0_t2_p, + input [0:`GPR_POOL_ENC-1] rn_cp_iu6_t1_i0_t2_a, + + input rn_cp_iu6_t1_i0_t3_v, + input [0:2] rn_cp_iu6_t1_i0_t3_t, + input [0:`GPR_POOL_ENC-1] rn_cp_iu6_t1_i0_t3_p, + input [0:`GPR_POOL_ENC-1] rn_cp_iu6_t1_i0_t3_a, + + input rn_cp_iu6_t1_i0_btb_entry, + input [0:1] rn_cp_iu6_t1_i0_btb_hist, + input rn_cp_iu6_t1_i0_bta_val, + + // Instruction 1 Issue + input rn_cp_iu6_t1_i1_vld, + input [1:`ITAG_SIZE_ENC-1] rn_cp_iu6_t1_i1_itag, + input [0:2] rn_cp_iu6_t1_i1_ucode, + input rn_cp_iu6_t1_i1_fuse_nop, + input rn_cp_iu6_t1_i1_rte_lq, + input rn_cp_iu6_t1_i1_rte_sq, + input rn_cp_iu6_t1_i1_rte_fx0, + input rn_cp_iu6_t1_i1_rte_fx1, + input rn_cp_iu6_t1_i1_rte_axu0, + input rn_cp_iu6_t1_i1_rte_axu1, + + input [62-`EFF_IFAR_WIDTH:61] rn_cp_iu6_t1_i1_ifar, + input [62-`EFF_IFAR_WIDTH:61] rn_cp_iu6_t1_i1_bta, + input rn_cp_iu6_t1_i1_isram, + input [0:31] rn_cp_iu6_t1_i1_instr, + + input rn_cp_iu6_t1_i1_valop, + input [0:2] rn_cp_iu6_t1_i1_error, + input rn_cp_iu6_t1_i1_br_pred, + input rn_cp_iu6_t1_i1_bh_update, + input [0:1] rn_cp_iu6_t1_i1_bh0_hist, + input [0:1] rn_cp_iu6_t1_i1_bh1_hist, + input [0:1] rn_cp_iu6_t1_i1_bh2_hist, + input [0:9] rn_cp_iu6_t1_i1_gshare, + input [0:2] rn_cp_iu6_t1_i1_ls_ptr, + input rn_cp_iu6_t1_i1_match, + + input rn_cp_iu6_t1_i1_type_fp, + input rn_cp_iu6_t1_i1_type_ap, + input rn_cp_iu6_t1_i1_type_spv, + input rn_cp_iu6_t1_i1_type_st, + input rn_cp_iu6_t1_i1_async_block, + input rn_cp_iu6_t1_i1_np1_flush, + + input rn_cp_iu6_t1_i1_t1_v, + input [0:2] rn_cp_iu6_t1_i1_t1_t, + input [0:`GPR_POOL_ENC-1] rn_cp_iu6_t1_i1_t1_p, + input [0:`GPR_POOL_ENC-1] rn_cp_iu6_t1_i1_t1_a, + + input rn_cp_iu6_t1_i1_t2_v, + input [0:2] rn_cp_iu6_t1_i1_t2_t, + input [0:`GPR_POOL_ENC-1] rn_cp_iu6_t1_i1_t2_p, + input [0:`GPR_POOL_ENC-1] rn_cp_iu6_t1_i1_t2_a, + + input rn_cp_iu6_t1_i1_t3_v, + input [0:2] rn_cp_iu6_t1_i1_t3_t, + input [0:`GPR_POOL_ENC-1] rn_cp_iu6_t1_i1_t3_p, + input [0:`GPR_POOL_ENC-1] rn_cp_iu6_t1_i1_t3_a, + + input rn_cp_iu6_t1_i1_btb_entry, + input [0:1] rn_cp_iu6_t1_i1_btb_hist, + input rn_cp_iu6_t1_i1_bta_val, + `endif + + // completion empty + output [0:`THREADS-1] cp_rn_empty, + output [0:`THREADS-1] cp_async_block, + + // Instruction 0 Complete + output cp_rn_t0_i0_v, + output cp_rn_t0_i0_axu_exception_val, + output [0:3] cp_rn_t0_i0_axu_exception, + output cp_rn_t0_i0_t1_v, + output [0:2] cp_rn_t0_i0_t1_t, + output [0:`GPR_POOL_ENC-1] cp_rn_t0_i0_t1_p, + output [0:`GPR_POOL_ENC-1] cp_rn_t0_i0_t1_a, + + output cp_rn_t0_i0_t2_v, + output [0:2] cp_rn_t0_i0_t2_t, + output [0:`GPR_POOL_ENC-1] cp_rn_t0_i0_t2_p, + output [0:`GPR_POOL_ENC-1] cp_rn_t0_i0_t2_a, + + output cp_rn_t0_i0_t3_v, + output [0:2] cp_rn_t0_i0_t3_t, + output [0:`GPR_POOL_ENC-1] cp_rn_t0_i0_t3_p, + output [0:`GPR_POOL_ENC-1] cp_rn_t0_i0_t3_a, + + // Instruction 1 Complete + output cp_rn_t0_i1_v, + output cp_rn_t0_i1_axu_exception_val, + output [0:3] cp_rn_t0_i1_axu_exception, + output cp_rn_t0_i1_t1_v, + output [0:2] cp_rn_t0_i1_t1_t, + output [0:`GPR_POOL_ENC-1] cp_rn_t0_i1_t1_p, + output [0:`GPR_POOL_ENC-1] cp_rn_t0_i1_t1_a, + + output cp_rn_t0_i1_t2_v, + output [0:2] cp_rn_t0_i1_t2_t, + output [0:`GPR_POOL_ENC-1] cp_rn_t0_i1_t2_p, + output [0:`GPR_POOL_ENC-1] cp_rn_t0_i1_t2_a, + + output cp_rn_t0_i1_t3_v, + output [0:2] cp_rn_t0_i1_t3_t, + output [0:`GPR_POOL_ENC-1] cp_rn_t0_i1_t3_p, + output [0:`GPR_POOL_ENC-1] cp_rn_t0_i1_t3_a, + +`ifndef THREADS1 + // Instruction 0 Complete + output cp_rn_t1_i0_v, + output cp_rn_t1_i0_axu_exception_val, + output [0:3] cp_rn_t1_i0_axu_exception, + output cp_rn_t1_i0_t1_v, + output [0:2] cp_rn_t1_i0_t1_t, + output [0:`GPR_POOL_ENC-1] cp_rn_t1_i0_t1_p, + output [0:`GPR_POOL_ENC-1] cp_rn_t1_i0_t1_a, + + output cp_rn_t1_i0_t2_v, + output [0:2] cp_rn_t1_i0_t2_t, + output [0:`GPR_POOL_ENC-1] cp_rn_t1_i0_t2_p, + output [0:`GPR_POOL_ENC-1] cp_rn_t1_i0_t2_a, + + output cp_rn_t1_i0_t3_v, + output [0:2] cp_rn_t1_i0_t3_t, + output [0:`GPR_POOL_ENC-1] cp_rn_t1_i0_t3_p, + output [0:`GPR_POOL_ENC-1] cp_rn_t1_i0_t3_a, + + // Instruction 1 Complete + output cp_rn_t1_i1_v, + output cp_rn_t1_i1_axu_exception_val, + output [0:3] cp_rn_t1_i1_axu_exception, + output cp_rn_t1_i1_t1_v, + output [0:2] cp_rn_t1_i1_t1_t, + output [0:`GPR_POOL_ENC-1] cp_rn_t1_i1_t1_p, + output [0:`GPR_POOL_ENC-1] cp_rn_t1_i1_t1_a, + + output cp_rn_t1_i1_t2_v, + output [0:2] cp_rn_t1_i1_t2_t, + output [0:`GPR_POOL_ENC-1] cp_rn_t1_i1_t2_p, + output [0:`GPR_POOL_ENC-1] cp_rn_t1_i1_t2_a, + + output cp_rn_t1_i1_t3_v, + output [0:2] cp_rn_t1_i1_t3_t, + output [0:`GPR_POOL_ENC-1] cp_rn_t1_i1_t3_p, + output [0:`GPR_POOL_ENC-1] cp_rn_t1_i1_t3_a, +`endif + + // Branch Prediction Complete + output cp_bp_t0_val, + output [62-`EFF_IFAR_WIDTH:61] cp_bp_t0_ifar, + output [0:1] cp_bp_t0_bh0_hist, + output [0:1] cp_bp_t0_bh1_hist, + output [0:1] cp_bp_t0_bh2_hist, + output cp_bp_t0_br_pred, + output cp_bp_t0_br_taken, + output cp_bp_t0_bh_update, + output cp_bp_t0_bcctr, + output cp_bp_t0_bclr, + output cp_bp_t0_getnia, + output cp_bp_t0_group, + output cp_bp_t0_lk, + output [0:1] cp_bp_t0_bh, + output [0:9] cp_bp_t0_gshare, + output [0:2] cp_bp_t0_ls_ptr, + output [62-`EFF_IFAR_WIDTH:61] cp_bp_t0_ctr, + output cp_bp_t0_btb_entry, + output [0:1] cp_bp_t0_btb_hist, + +`ifndef THREADS1 + // Branch Prediction Complete + output cp_bp_t1_val, + output [62-`EFF_IFAR_WIDTH:61] cp_bp_t1_ifar, + output [0:1] cp_bp_t1_bh0_hist, + output [0:1] cp_bp_t1_bh1_hist, + output [0:1] cp_bp_t1_bh2_hist, + output cp_bp_t1_br_pred, + output cp_bp_t1_br_taken, + output cp_bp_t1_bh_update, + output cp_bp_t1_bcctr, + output cp_bp_t1_bclr, + output cp_bp_t1_getnia, + output cp_bp_t1_group, + output cp_bp_t1_lk, + output [0:1] cp_bp_t1_bh, + output [0:9] cp_bp_t1_gshare, + output [0:2] cp_bp_t1_ls_ptr, + output [62-`EFF_IFAR_WIDTH:61] cp_bp_t1_ctr, + output cp_bp_t1_btb_entry, + output [0:1] cp_bp_t1_btb_hist, +`endif + + // Output to dispatch to block due to ivax + output [0:`THREADS-1] cp_dis_ivax, + + // LQ Instruction Executed + input [0:`THREADS-1] lq0_iu_execute_vld, + input [0:`ITAG_SIZE_ENC-1] lq0_iu_itag, + input lq0_iu_n_flush, + input lq0_iu_np1_flush, + input lq0_iu_dacr_type, + input [0:3] lq0_iu_dacrw, + input [0:31] lq0_iu_instr, + input [64-`GPR_WIDTH:63] lq0_iu_eff_addr, + input lq0_iu_exception_val, + input [0:5] lq0_iu_exception, + input lq0_iu_flush2ucode, + input lq0_iu_flush2ucode_type, + input [0:`THREADS-1] lq0_iu_recirc_val, + input [0:`THREADS-1] lq0_iu_dear_val, + + input [0:`THREADS-1] lq1_iu_execute_vld, + input [0:`ITAG_SIZE_ENC-1] lq1_iu_itag, + input lq1_iu_n_flush, + input lq1_iu_np1_flush, + input lq1_iu_exception_val, + input [0:5] lq1_iu_exception, + input lq1_iu_dacr_type, + input [0:3] lq1_iu_dacrw, + input [0:3] lq1_iu_perf_events, + + output [0:`THREADS-1] iu_lq_i0_completed, + output [0:`THREADS-1] iu_lq_i1_completed, + output [0:`ITAG_SIZE_ENC-1] iu_lq_t0_i0_completed_itag, + output [0:`ITAG_SIZE_ENC-1] iu_lq_t0_i1_completed_itag, +`ifndef THREADS1 + output [0:`ITAG_SIZE_ENC-1] iu_lq_t1_i0_completed_itag, + output [0:`ITAG_SIZE_ENC-1] iu_lq_t1_i1_completed_itag, +`endif + + output [0:`THREADS-1] iu_lq_recirc_val, + + // BR Instruction Executed + input [0:`THREADS-1] br_iu_execute_vld, + input [0:`ITAG_SIZE_ENC-1] br_iu_itag, + input [0:`THREADS-1] br_iu_redirect, + input [62-`EFF_IFAR_ARCH:61] br_iu_bta, + input br_iu_taken, + input [0:3] br_iu_perf_events, + + // XU0 Instruction Executed + input [0:`THREADS-1] xu_iu_execute_vld, + input [0:`ITAG_SIZE_ENC-1] xu_iu_itag, + input xu_iu_n_flush, + input xu_iu_np1_flush, + input xu_iu_flush2ucode, + input xu_iu_exception_val, + input [0:4] xu_iu_exception, + input [0:`THREADS-1] xu_iu_mtiar, + input [62-`EFF_IFAR_ARCH:61] xu_iu_bta, + input [0:3] xu_iu_perf_events, + + // XU0 Instruction Executed + input [0:`THREADS-1] xu1_iu_execute_vld, + input [0:`ITAG_SIZE_ENC-1] xu1_iu_itag, + + // AXU0 Instruction Executed + input [0:`THREADS-1] axu0_iu_execute_vld, + input [0:`ITAG_SIZE_ENC-1] axu0_iu_itag, + input axu0_iu_n_flush, + input axu0_iu_np1_flush, + input axu0_iu_n_np1_flush, + input axu0_iu_flush2ucode, + input axu0_iu_flush2ucode_type, + input axu0_iu_exception_val, + input [0:3] axu0_iu_exception, + input [0:3] axu0_iu_perf_events, + + // AXU1 Instruction Executed + input [0:`THREADS-1] axu1_iu_execute_vld, + input [0:`ITAG_SIZE_ENC-1] axu1_iu_itag, + input axu1_iu_n_flush, + input axu1_iu_np1_flush, + input axu1_iu_flush2ucode, + input axu1_iu_flush2ucode_type, + input axu1_iu_exception_val, + input [0:3] axu1_iu_exception, + input [0:3] axu1_iu_perf_events, + + // Interrupts + input [0:`THREADS-1] an_ac_uncond_dbg_event, + input [0:`THREADS-1] xu_iu_external_mchk, + input [0:`THREADS-1] xu_iu_ext_interrupt, + input [0:`THREADS-1] xu_iu_dec_interrupt, + input [0:`THREADS-1] xu_iu_udec_interrupt, + input [0:`THREADS-1] xu_iu_perf_interrupt, + input [0:`THREADS-1] xu_iu_fit_interrupt, + input [0:`THREADS-1] xu_iu_crit_interrupt, + input [0:`THREADS-1] xu_iu_wdog_interrupt, + input [0:`THREADS-1] xu_iu_gwdog_interrupt, + input [0:`THREADS-1] xu_iu_gfit_interrupt, + input [0:`THREADS-1] xu_iu_gdec_interrupt, + input [0:`THREADS-1] xu_iu_dbell_interrupt, + input [0:`THREADS-1] xu_iu_cdbell_interrupt, + input [0:`THREADS-1] xu_iu_gdbell_interrupt, + input [0:`THREADS-1] xu_iu_gcdbell_interrupt, + input [0:`THREADS-1] xu_iu_gmcdbell_interrupt, + input [0:`THREADS-1] xu_iu_dbsr_ide, + input [62-`EFF_IFAR_ARCH:61] xu_iu_t0_rest_ifar, +`ifndef THREADS1 + input [62-`EFF_IFAR_ARCH:61] xu_iu_t1_rest_ifar, +`endif + input [0:`THREADS-1] axu0_iu_async_fex, + + // To Ierats + output cp_is_isync, // Or together from each completion unit + output cp_is_csync, // Or together from each completion unit + + // Flushes + output [0:`THREADS-1] iu_flush, + output [0:`THREADS-1] cp_flush_into_uc, + output [43:61] cp_uc_t0_flush_ifar, +`ifndef THREADS1 + output [43:61] cp_uc_t1_flush_ifar, +`endif + output [0:`THREADS-1] cp_uc_np1_flush, + output [0:`THREADS-1] cp_flush, + output [0:`ITAG_SIZE_ENC-1] cp_t0_next_itag, + output [0:`ITAG_SIZE_ENC-1] cp_t0_flush_itag, + output [62-`EFF_IFAR_ARCH:61] cp_t0_flush_ifar, +`ifndef THREADS1 + output [0:`ITAG_SIZE_ENC-1] cp_t1_next_itag, + output [0:`ITAG_SIZE_ENC-1] cp_t1_flush_itag, + output [62-`EFF_IFAR_ARCH:61] cp_t1_flush_ifar, +`endif + output [0:`THREADS-1] cp_iu0_flush_2ucode, + output [0:`THREADS-1] cp_iu0_flush_2ucode_type, + output [0:`THREADS-1] cp_iu0_flush_nonspec, + input pc_iu_init_reset, + output [0:`THREADS-1] cp_rn_uc_credit_free, + + // Signals to SPR partition + output [0:`THREADS-1] iu_xu_rfi, + output [0:`THREADS-1] iu_xu_rfgi, + output [0:`THREADS-1] iu_xu_rfci, + output [0:`THREADS-1] iu_xu_rfmci, + output [0:`THREADS-1] iu_xu_int, + output [0:`THREADS-1] iu_xu_gint, + output [0:`THREADS-1] iu_xu_cint, + output [0:`THREADS-1] iu_xu_mcint, + output [0:`THREADS-1] iu_xu_dear_update, + output [0:`THREADS-1] iu_spr_eheir_update, + output [62-`EFF_IFAR_ARCH:61] iu_xu_t0_nia, + output [0:16] iu_xu_t0_esr, + output [0:14] iu_xu_t0_mcsr, + output [0:18] iu_xu_t0_dbsr, + output [64-`GPR_WIDTH:63] iu_xu_t0_dear, + output [0:31] iu_spr_t0_eheir, + input [0:1] xu_iu_t0_dbcr0_dac1, + input [0:1] xu_iu_t0_dbcr0_dac2, + input [0:1] xu_iu_t0_dbcr0_dac3, + input [0:1] xu_iu_t0_dbcr0_dac4, +`ifndef THREADS1 + output [62-`EFF_IFAR_ARCH:61] iu_xu_t1_nia, + output [0:16] iu_xu_t1_esr, + output [0:14] iu_xu_t1_mcsr, + output [0:18] iu_xu_t1_dbsr, + output [64-`GPR_WIDTH:63] iu_xu_t1_dear, + output [0:31] iu_spr_t1_eheir, + input [0:1] xu_iu_t1_dbcr0_dac1, + input [0:1] xu_iu_t1_dbcr0_dac2, + input [0:1] xu_iu_t1_dbcr0_dac3, + input [0:1] xu_iu_t1_dbcr0_dac4, +`endif + output [0:`THREADS-1] iu_xu_dbsr_update, + output [0:`THREADS-1] iu_xu_dbsr_ude, + output [0:`THREADS-1] iu_xu_dbsr_ide, + output [0:`THREADS-1] iu_xu_esr_update, + output [0:`THREADS-1] iu_xu_act, + output [0:`THREADS-1] iu_xu_dbell_taken, + output [0:`THREADS-1] iu_xu_cdbell_taken, + output [0:`THREADS-1] iu_xu_gdbell_taken, + output [0:`THREADS-1] iu_xu_gcdbell_taken, + output [0:`THREADS-1] iu_xu_gmcdbell_taken, + output [0:`THREADS-1] iu_xu_instr_cpl, + input [0:`THREADS-1] xu_iu_np1_async_flush, + output [0:`THREADS-1] iu_xu_async_complete, + input [0:`THREADS-1] dp_cp_hold_req, + output [0:`THREADS-1] iu_mm_hold_ack, + input [0:`THREADS-1] dp_cp_bus_snoop_hold_req, + output [0:`THREADS-1] iu_mm_bus_snoop_hold_ack, + input [0:`THREADS-1] xu_iu_msr_de, + input [0:`THREADS-1] xu_iu_msr_pr, + input [0:`THREADS-1] xu_iu_msr_cm, + input [0:`THREADS-1] xu_iu_msr_gs, + input [0:`THREADS-1] xu_iu_msr_me, + input [0:`THREADS-1] xu_iu_dbcr0_edm, + input [0:`THREADS-1] xu_iu_dbcr0_idm, + input [0:`THREADS-1] xu_iu_dbcr0_icmp, + input [0:`THREADS-1] xu_iu_dbcr0_brt, + input [0:`THREADS-1] xu_iu_dbcr0_irpt, + input [0:`THREADS-1] xu_iu_dbcr0_trap, + input [0:`THREADS-1] xu_iu_iac1_en, + input [0:`THREADS-1] xu_iu_iac2_en, + input [0:`THREADS-1] xu_iu_iac3_en, + input [0:`THREADS-1] xu_iu_iac4_en, + input [0:`THREADS-1] xu_iu_dbcr0_ret, + input [0:`THREADS-1] xu_iu_dbcr1_iac12m, + input [0:`THREADS-1] xu_iu_dbcr1_iac34m, + input [0:`THREADS-1] lq_iu_spr_dbcr3_ivc, + input [0:`THREADS-1] xu_iu_epcr_extgs, + input [0:`THREADS-1] xu_iu_epcr_dtlbgs, + input [0:`THREADS-1] xu_iu_epcr_itlbgs, + input [0:`THREADS-1] xu_iu_epcr_dsigs, + input [0:`THREADS-1] xu_iu_epcr_isigs, + input [0:`THREADS-1] xu_iu_epcr_duvd, + input [0:`THREADS-1] xu_iu_epcr_icm, + input [0:`THREADS-1] xu_iu_epcr_gicm, + input xu_iu_spr_ccr2_en_dcr, + input xu_iu_spr_ccr2_ucode_dis, + input xu_iu_hid_mmu_mode, + input xu_iu_xucr4_mmu_mchk, + output [0:`THREADS-1] iu_xu_quiesce, + output [0:`THREADS-1] iu_pc_quiesce, + + // MMU Errors + input [0:`THREADS-1] mm_iu_ierat_rel_val, + input [0:`THREADS-1] mm_iu_ierat_pt_fault, + input [0:`THREADS-1] mm_iu_ierat_lrat_miss, + input [0:`THREADS-1] mm_iu_ierat_tlb_inelig, + input [0:`THREADS-1] mm_iu_tlb_multihit_err, + input [0:`THREADS-1] mm_iu_tlb_par_err, + input [0:`THREADS-1] mm_iu_lru_par_err, + input [0:`THREADS-1] mm_iu_tlb_miss, + input [0:`THREADS-1] mm_iu_reload_hit, + input [3:4] mm_iu_ierat_mmucr1, + input [0:`THREADS-1] ic_cp_nonspec_hit, + + + output [0:5] cp_mm_except_taken_t0, +`ifndef THREADS1 + output [0:5] cp_mm_except_taken_t1, +`endif + + // SPRs + input [0:`THREADS-1] xu_iu_single_instr_mode, + input [0:`THREADS-1] spr_single_issue, + input [64-`GPR_WIDTH:51] spr_ivpr, + input [64-`GPR_WIDTH:51] spr_givpr, + input [62-`EFF_IFAR_ARCH:61] spr_iac1, + input [62-`EFF_IFAR_ARCH:61] spr_iac2, + input [62-`EFF_IFAR_ARCH:61] spr_iac3, + input [62-`EFF_IFAR_ARCH:61] spr_iac4, + + // XER read bus to RF for store conditionals + output [0:`XER_POOL_ENC-1] iu_rf_t0_xer_p, +`ifndef THREADS1 + output [0:`XER_POOL_ENC-1] iu_rf_t1_xer_p, +`endif + + // Signals from pervasive + input [0:`THREADS-1] pc_iu_ram_active, + input [0:`THREADS-1] pc_iu_ram_flush_thread, + input [0:`THREADS-1] xu_iu_msrovride_enab, + output iu_pc_ram_done, // Need to Or these togther to create + output iu_pc_ram_interrupt, // Need to Or these togther to create + output iu_pc_ram_unsupported, + input [0:`THREADS-1] pc_iu_stop, + input [0:`THREADS-1] pc_iu_step, + input [0:2] pc_iu_t0_dbg_action, +`ifndef THREADS1 + input [0:2] pc_iu_t1_dbg_action, +`endif + output [0:`THREADS-1] iu_pc_step_done, + output [0:`THREADS-1] iu_pc_stop_dbg_event, + output [0:`THREADS-1] iu_pc_err_debug_event, + output [0:`THREADS-1] iu_pc_attention_instr, + output [0:`THREADS-1] iu_pc_err_mchk_disabled, + output [0:`THREADS-1] ac_an_debug_trigger, + output [0:`THREADS-1] iu_xu_stop, + + input pc_iu_trace_bus_enable, + input [0:10] pc_iu_debug_mux_ctrls, + input [0:31] debug_bus_in, + output [0:31] debug_bus_out, + input [0:3] coretrace_ctrls_in, + output [0:3] coretrace_ctrls_out, + + + // Power + inout vdd, + inout gnd); + + wire [0:`THREADS-1] cp_is_isync_int; + wire [0:`THREADS-1] cp_is_csync_int; + wire [0:`THREADS-1] iu_pc_ram_done_int; + wire [0:`THREADS-1] iu_pc_ram_interrupt_int; + wire [0:`THREADS-1] iu_pc_ram_unsupported_int; + + wire [0:`THREADS-1] iu_pc_stop_dbg_event_int[0:`THREADS-1]; + + wire [0:31] unit_dbg_data0; + wire [0:31] unit_dbg_data1; + wire [0:31] unit_dbg_data2; + wire [0:31] unit_dbg_data3; + wire [0:31] unit_dbg_data4; + wire [0:31] unit_dbg_data5; + wire [0:31] unit_dbg_data6; + wire [0:31] unit_dbg_data7; + wire [0:31] unit_dbg_data8; + wire [0:31] unit_dbg_data9; + wire [0:31] unit_dbg_data10; + wire [0:31] unit_dbg_data11; + wire [0:31] unit_dbg_data12; + wire [0:31] unit_dbg_data13; + wire [0:31] unit_dbg_data14; + wire [0:31] unit_dbg_data15; + + wire clkoff_b, act_dis, d_mode, delay_lclkr, mpw1_b, mpw2_b; + + // for now assigning the debug to 0 + assign unit_dbg_data0 = 32'h00000000; + assign unit_dbg_data1 = 32'h00000000; + assign unit_dbg_data2 = 32'h00000000; + assign unit_dbg_data3 = 32'h00000000; + assign unit_dbg_data4 = 32'h00000000; + assign unit_dbg_data5 = 32'h00000000; + assign unit_dbg_data6 = 32'h00000000; + assign unit_dbg_data7 = 32'h00000000; + assign unit_dbg_data8 = 32'h00000000; + assign unit_dbg_data9 = 32'h00000000; + assign unit_dbg_data10 = 32'h00000000; + assign unit_dbg_data11 = 32'h00000000; + assign unit_dbg_data12 = 32'h00000000; + assign unit_dbg_data13 = 32'h00000000; + assign unit_dbg_data14 = 32'h00000000; + assign unit_dbg_data15 = 32'h00000000; + + + + assign cp_is_isync = |cp_is_isync_int; + assign cp_is_csync = |cp_is_csync_int; + assign iu_pc_ram_done = |iu_pc_ram_done_int; + assign iu_pc_ram_interrupt = |iu_pc_ram_interrupt_int; + assign iu_pc_ram_unsupported = |iu_pc_ram_unsupported_int; + `ifdef THREADS1 + assign iu_pc_stop_dbg_event = iu_pc_stop_dbg_event_int[0][0]; + `endif + `ifndef THREADS1 + assign iu_pc_stop_dbg_event = {(iu_pc_stop_dbg_event_int[0][0] | iu_pc_stop_dbg_event_int[1][1]), (iu_pc_stop_dbg_event_int[0][1] | iu_pc_stop_dbg_event_int[1][0])}; + `endif + + iuq_cpl iuq_cpl0( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .tc_ac_ccflush_dc(tc_ac_ccflush_dc), + .clkoff_dc_b(clkoff_dc_b), + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .func_sl_thold_2(pc_iu_func_sl_thold_2), + .func_slp_sl_thold_2(pc_iu_func_slp_sl_thold_2), + .sg_2(pc_iu_sg_2), + .scan_in(cp_scan_in[0]), + .scan_out(cp_scan_out[0]), + .pc_iu_event_bus_enable(pc_iu_event_bus_enable), + .pc_iu_event_count_mode(pc_iu_event_count_mode), + .spr_cp_perf_event_mux_ctrls(spr_cp_perf_event_mux_ctrls[0:15]), + .event_bus_in(event_bus_in[0:3]), + .event_bus_out(event_bus_out[0:3]), + .rn_cp_iu6_i0_vld(rn_cp_iu6_t0_i0_vld), + .rn_cp_iu6_i0_itag(rn_cp_iu6_t0_i0_itag), + .rn_cp_iu6_i0_ucode(rn_cp_iu6_t0_i0_ucode), + .rn_cp_iu6_i0_fuse_nop(rn_cp_iu6_t0_i0_fuse_nop), + .rn_cp_iu6_i0_rte_lq(rn_cp_iu6_t0_i0_rte_lq), + .rn_cp_iu6_i0_rte_sq(rn_cp_iu6_t0_i0_rte_sq), + .rn_cp_iu6_i0_rte_fx0(rn_cp_iu6_t0_i0_rte_fx0), + .rn_cp_iu6_i0_rte_fx1(rn_cp_iu6_t0_i0_rte_fx1), + .rn_cp_iu6_i0_rte_axu0(rn_cp_iu6_t0_i0_rte_axu0), + .rn_cp_iu6_i0_rte_axu1(rn_cp_iu6_t0_i0_rte_axu1), + .rn_cp_iu6_i0_ifar(rn_cp_iu6_t0_i0_ifar), + .rn_cp_iu6_i0_bta(rn_cp_iu6_t0_i0_bta), + .rn_cp_iu6_i0_isram(rn_cp_iu6_t0_i0_isram), + .rn_cp_iu6_i0_instr(rn_cp_iu6_t0_i0_instr), + .rn_cp_iu6_i0_valop(rn_cp_iu6_t0_i0_valop), + .rn_cp_iu6_i0_error(rn_cp_iu6_t0_i0_error), + .rn_cp_iu6_i0_br_pred(rn_cp_iu6_t0_i0_br_pred), + .rn_cp_iu6_i0_bh_update(rn_cp_iu6_t0_i0_bh_update), + .rn_cp_iu6_i0_bh0_hist(rn_cp_iu6_t0_i0_bh0_hist), + .rn_cp_iu6_i0_bh1_hist(rn_cp_iu6_t0_i0_bh1_hist), + .rn_cp_iu6_i0_bh2_hist(rn_cp_iu6_t0_i0_bh2_hist), + .rn_cp_iu6_i0_gshare(rn_cp_iu6_t0_i0_gshare), + .rn_cp_iu6_i0_ls_ptr(rn_cp_iu6_t0_i0_ls_ptr), + .rn_cp_iu6_i0_match(rn_cp_iu6_t0_i0_match), + .rn_cp_iu6_i0_type_fp(rn_cp_iu6_t0_i0_type_fp), + .rn_cp_iu6_i0_type_ap(rn_cp_iu6_t0_i0_type_ap), + .rn_cp_iu6_i0_type_spv(rn_cp_iu6_t0_i0_type_spv), + .rn_cp_iu6_i0_type_st(rn_cp_iu6_t0_i0_type_st), + .rn_cp_iu6_i0_async_block(rn_cp_iu6_t0_i0_async_block), + .rn_cp_iu6_i0_np1_flush(rn_cp_iu6_t0_i0_np1_flush), + .rn_cp_iu6_i0_t1_v(rn_cp_iu6_t0_i0_t1_v), + .rn_cp_iu6_i0_t1_t(rn_cp_iu6_t0_i0_t1_t), + .rn_cp_iu6_i0_t1_p(rn_cp_iu6_t0_i0_t1_p), + .rn_cp_iu6_i0_t1_a(rn_cp_iu6_t0_i0_t1_a), + .rn_cp_iu6_i0_t2_v(rn_cp_iu6_t0_i0_t2_v), + .rn_cp_iu6_i0_t2_t(rn_cp_iu6_t0_i0_t2_t), + .rn_cp_iu6_i0_t2_p(rn_cp_iu6_t0_i0_t2_p), + .rn_cp_iu6_i0_t2_a(rn_cp_iu6_t0_i0_t2_a), + .rn_cp_iu6_i0_t3_v(rn_cp_iu6_t0_i0_t3_v), + .rn_cp_iu6_i0_t3_t(rn_cp_iu6_t0_i0_t3_t), + .rn_cp_iu6_i0_t3_p(rn_cp_iu6_t0_i0_t3_p), + .rn_cp_iu6_i0_t3_a(rn_cp_iu6_t0_i0_t3_a), + .rn_cp_iu6_i0_btb_entry(rn_cp_iu6_t0_i0_btb_entry), + .rn_cp_iu6_i0_btb_hist(rn_cp_iu6_t0_i0_btb_hist), + .rn_cp_iu6_i0_bta_val(rn_cp_iu6_t0_i0_bta_val), + .rn_cp_iu6_i1_vld(rn_cp_iu6_t0_i1_vld), + .rn_cp_iu6_i1_itag(rn_cp_iu6_t0_i1_itag), + .rn_cp_iu6_i1_ucode(rn_cp_iu6_t0_i1_ucode), + .rn_cp_iu6_i1_fuse_nop(rn_cp_iu6_t0_i1_fuse_nop), + .rn_cp_iu6_i1_rte_lq(rn_cp_iu6_t0_i1_rte_lq), + .rn_cp_iu6_i1_rte_sq(rn_cp_iu6_t0_i1_rte_sq), + .rn_cp_iu6_i1_rte_fx0(rn_cp_iu6_t0_i1_rte_fx0), + .rn_cp_iu6_i1_rte_fx1(rn_cp_iu6_t0_i1_rte_fx1), + .rn_cp_iu6_i1_rte_axu0(rn_cp_iu6_t0_i1_rte_axu0), + .rn_cp_iu6_i1_rte_axu1(rn_cp_iu6_t0_i1_rte_axu1), + .rn_cp_iu6_i1_ifar(rn_cp_iu6_t0_i1_ifar), + .rn_cp_iu6_i1_bta(rn_cp_iu6_t0_i1_bta), + .rn_cp_iu6_i1_isram(rn_cp_iu6_t0_i1_isram), + .rn_cp_iu6_i1_instr(rn_cp_iu6_t0_i1_instr), + .rn_cp_iu6_i1_valop(rn_cp_iu6_t0_i1_valop), + .rn_cp_iu6_i1_error(rn_cp_iu6_t0_i1_error), + .rn_cp_iu6_i1_br_pred(rn_cp_iu6_t0_i1_br_pred), + .rn_cp_iu6_i1_bh_update(rn_cp_iu6_t0_i1_bh_update), + .rn_cp_iu6_i1_bh0_hist(rn_cp_iu6_t0_i1_bh0_hist), + .rn_cp_iu6_i1_bh1_hist(rn_cp_iu6_t0_i1_bh1_hist), + .rn_cp_iu6_i1_bh2_hist(rn_cp_iu6_t0_i1_bh2_hist), + .rn_cp_iu6_i1_gshare(rn_cp_iu6_t0_i1_gshare), + .rn_cp_iu6_i1_ls_ptr(rn_cp_iu6_t0_i1_ls_ptr), + .rn_cp_iu6_i1_match(rn_cp_iu6_t0_i1_match), + .rn_cp_iu6_i1_type_fp(rn_cp_iu6_t0_i1_type_fp), + .rn_cp_iu6_i1_type_ap(rn_cp_iu6_t0_i1_type_ap), + .rn_cp_iu6_i1_type_spv(rn_cp_iu6_t0_i1_type_spv), + .rn_cp_iu6_i1_type_st(rn_cp_iu6_t0_i1_type_st), + .rn_cp_iu6_i1_async_block(rn_cp_iu6_t0_i1_async_block), + .rn_cp_iu6_i1_np1_flush(rn_cp_iu6_t0_i1_np1_flush), + .rn_cp_iu6_i1_t1_v(rn_cp_iu6_t0_i1_t1_v), + .rn_cp_iu6_i1_t1_t(rn_cp_iu6_t0_i1_t1_t), + .rn_cp_iu6_i1_t1_p(rn_cp_iu6_t0_i1_t1_p), + .rn_cp_iu6_i1_t1_a(rn_cp_iu6_t0_i1_t1_a), + .rn_cp_iu6_i1_t2_v(rn_cp_iu6_t0_i1_t2_v), + .rn_cp_iu6_i1_t2_t(rn_cp_iu6_t0_i1_t2_t), + .rn_cp_iu6_i1_t2_p(rn_cp_iu6_t0_i1_t2_p), + .rn_cp_iu6_i1_t2_a(rn_cp_iu6_t0_i1_t2_a), + .rn_cp_iu6_i1_t3_v(rn_cp_iu6_t0_i1_t3_v), + .rn_cp_iu6_i1_t3_t(rn_cp_iu6_t0_i1_t3_t), + .rn_cp_iu6_i1_t3_p(rn_cp_iu6_t0_i1_t3_p), + .rn_cp_iu6_i1_t3_a(rn_cp_iu6_t0_i1_t3_a), + .rn_cp_iu6_i1_btb_entry(rn_cp_iu6_t0_i1_btb_entry), + .rn_cp_iu6_i1_btb_hist(rn_cp_iu6_t0_i1_btb_hist), + .rn_cp_iu6_i1_bta_val(rn_cp_iu6_t0_i1_bta_val), + .cp_rn_empty(cp_rn_empty[0]), + .cp_async_block(cp_async_block[0]), + .cp_rn_i0_v(cp_rn_t0_i0_v), + .cp_rn_i0_axu_exception_val(cp_rn_t0_i0_axu_exception_val), + .cp_rn_i0_axu_exception(cp_rn_t0_i0_axu_exception), + .cp_rn_i0_t1_v(cp_rn_t0_i0_t1_v), + .cp_rn_i0_t1_t(cp_rn_t0_i0_t1_t), + .cp_rn_i0_t1_p(cp_rn_t0_i0_t1_p), + .cp_rn_i0_t1_a(cp_rn_t0_i0_t1_a), + .cp_rn_i0_t2_v(cp_rn_t0_i0_t2_v), + .cp_rn_i0_t2_t(cp_rn_t0_i0_t2_t), + .cp_rn_i0_t2_p(cp_rn_t0_i0_t2_p), + .cp_rn_i0_t2_a(cp_rn_t0_i0_t2_a), + .cp_rn_i0_t3_v(cp_rn_t0_i0_t3_v), + .cp_rn_i0_t3_t(cp_rn_t0_i0_t3_t), + .cp_rn_i0_t3_p(cp_rn_t0_i0_t3_p), + .cp_rn_i0_t3_a(cp_rn_t0_i0_t3_a), + .cp_rn_i1_v(cp_rn_t0_i1_v), + .cp_rn_i1_axu_exception_val(cp_rn_t0_i1_axu_exception_val), + .cp_rn_i1_axu_exception(cp_rn_t0_i1_axu_exception), + .cp_rn_i1_t1_v(cp_rn_t0_i1_t1_v), + .cp_rn_i1_t1_t(cp_rn_t0_i1_t1_t), + .cp_rn_i1_t1_p(cp_rn_t0_i1_t1_p), + .cp_rn_i1_t1_a(cp_rn_t0_i1_t1_a), + .cp_rn_i1_t2_v(cp_rn_t0_i1_t2_v), + .cp_rn_i1_t2_t(cp_rn_t0_i1_t2_t), + .cp_rn_i1_t2_p(cp_rn_t0_i1_t2_p), + .cp_rn_i1_t2_a(cp_rn_t0_i1_t2_a), + .cp_rn_i1_t3_v(cp_rn_t0_i1_t3_v), + .cp_rn_i1_t3_t(cp_rn_t0_i1_t3_t), + .cp_rn_i1_t3_p(cp_rn_t0_i1_t3_p), + .cp_rn_i1_t3_a(cp_rn_t0_i1_t3_a), + .cp_bp_val(cp_bp_t0_val), + .cp_bp_ifar(cp_bp_t0_ifar), + .cp_bp_bh0_hist(cp_bp_t0_bh0_hist), + .cp_bp_bh1_hist(cp_bp_t0_bh1_hist), + .cp_bp_bh2_hist(cp_bp_t0_bh2_hist), + .cp_bp_br_pred(cp_bp_t0_br_pred), + .cp_bp_br_taken(cp_bp_t0_br_taken), + .cp_bp_bh_update(cp_bp_t0_bh_update), + .cp_bp_bcctr(cp_bp_t0_bcctr), + .cp_bp_bclr(cp_bp_t0_bclr), + .cp_bp_getnia(cp_bp_t0_getnia), + .cp_bp_group(cp_bp_t0_group), + .cp_dis_ivax(cp_dis_ivax[0]), + .cp_bp_lk(cp_bp_t0_lk), + .cp_bp_bh(cp_bp_t0_bh), + .cp_bp_gshare(cp_bp_t0_gshare), + .cp_bp_ls_ptr(cp_bp_t0_ls_ptr), + .cp_bp_ctr(cp_bp_t0_ctr), + .cp_bp_btb_entry(cp_bp_t0_btb_entry), + .cp_bp_btb_hist(cp_bp_t0_btb_hist), + .lq0_iu_execute_vld(lq0_iu_execute_vld[0]), + .lq0_iu_itag(lq0_iu_itag), + .lq0_iu_n_flush(lq0_iu_n_flush), + .lq0_iu_np1_flush(lq0_iu_np1_flush), + .lq0_iu_dacr_type(lq0_iu_dacr_type), + .lq0_iu_dacrw(lq0_iu_dacrw), + .lq0_iu_instr(lq0_iu_instr), + .lq0_iu_eff_addr(lq0_iu_eff_addr), + .lq0_iu_exception_val(lq0_iu_exception_val), + .lq0_iu_exception(lq0_iu_exception), + .lq0_iu_flush2ucode(lq0_iu_flush2ucode), + .lq0_iu_flush2ucode_type(lq0_iu_flush2ucode_type), + .lq0_iu_recirc_val(lq0_iu_recirc_val[0]), + .lq0_iu_dear_val(lq0_iu_dear_val[0]), + .lq1_iu_execute_vld(lq1_iu_execute_vld[0]), + .lq1_iu_itag(lq1_iu_itag), + .lq1_iu_n_flush(lq1_iu_n_flush), + .lq1_iu_np1_flush(lq1_iu_np1_flush), + .lq1_iu_exception_val(lq1_iu_exception_val), + .lq1_iu_exception(lq1_iu_exception), + .lq1_iu_dacr_type(lq1_iu_dacr_type), + .lq1_iu_dacrw(lq1_iu_dacrw), + .lq1_iu_perf_events(lq1_iu_perf_events), + .iu_lq_i0_completed(iu_lq_i0_completed[0]), + .iu_lq_i1_completed(iu_lq_i1_completed[0]), + .iu_lq_i0_completed_itag(iu_lq_t0_i0_completed_itag), + .iu_lq_i1_completed_itag(iu_lq_t0_i1_completed_itag), + .iu_lq_recirc_val(iu_lq_recirc_val[0]), + .br_iu_execute_vld(br_iu_execute_vld[0]), + .br_iu_itag(br_iu_itag), + .br_iu_bta(br_iu_bta), + .br_iu_redirect(br_iu_redirect[0]), + .br_iu_taken(br_iu_taken), + .br_iu_perf_events(br_iu_perf_events), + .xu_iu_execute_vld(xu_iu_execute_vld[0]), + .xu_iu_itag(xu_iu_itag), + .xu_iu_exception_val(xu_iu_exception_val), + .xu_iu_exception(xu_iu_exception), + .xu_iu_mtiar(xu_iu_mtiar[0]), + .xu_iu_bta(xu_iu_bta), + .xu_iu_perf_events(xu_iu_perf_events), + .xu_iu_n_flush(xu_iu_n_flush), + .xu_iu_np1_flush(xu_iu_np1_flush), + .xu_iu_flush2ucode(xu_iu_flush2ucode), + .xu1_iu_execute_vld(xu1_iu_execute_vld[0]), + .xu1_iu_itag(xu1_iu_itag), + .axu0_iu_execute_vld(axu0_iu_execute_vld[0]), + .axu0_iu_itag(axu0_iu_itag), + .axu0_iu_n_flush(axu0_iu_n_flush), + .axu0_iu_np1_flush(axu0_iu_np1_flush), + .axu0_iu_n_np1_flush(axu0_iu_n_np1_flush), + .axu0_iu_exception(axu0_iu_exception), + .axu0_iu_exception_val(axu0_iu_exception_val), + .axu0_iu_flush2ucode(axu0_iu_flush2ucode), + .axu0_iu_flush2ucode_type(axu0_iu_flush2ucode_type), + .axu0_iu_async_fex(axu0_iu_async_fex[0]), + .axu0_iu_perf_events(axu0_iu_perf_events), + .axu1_iu_execute_vld(axu1_iu_execute_vld[0]), + .axu1_iu_itag(axu1_iu_itag), + .axu1_iu_n_flush(axu1_iu_n_flush), + .axu1_iu_np1_flush(axu1_iu_np1_flush), + .axu1_iu_exception(axu1_iu_exception), + .axu1_iu_exception_val(axu1_iu_exception_val), + .axu1_iu_flush2ucode(axu1_iu_flush2ucode), + .axu1_iu_flush2ucode_type(axu1_iu_flush2ucode_type), + .axu1_iu_perf_events(axu1_iu_perf_events), + .an_ac_uncond_dbg_event(an_ac_uncond_dbg_event[0]), + .xu_iu_external_mchk(xu_iu_external_mchk[0]), + .xu_iu_ext_interrupt(xu_iu_ext_interrupt[0]), + .xu_iu_dec_interrupt(xu_iu_dec_interrupt[0]), + .xu_iu_udec_interrupt(xu_iu_udec_interrupt[0]), + .xu_iu_perf_interrupt(xu_iu_perf_interrupt[0]), + .xu_iu_fit_interrupt(xu_iu_fit_interrupt[0]), + .xu_iu_crit_interrupt(xu_iu_crit_interrupt[0]), + .xu_iu_wdog_interrupt(xu_iu_wdog_interrupt[0]), + .xu_iu_gwdog_interrupt(xu_iu_gwdog_interrupt[0]), + .xu_iu_gfit_interrupt(xu_iu_gfit_interrupt[0]), + .xu_iu_gdec_interrupt(xu_iu_gdec_interrupt[0]), + .xu_iu_dbell_interrupt(xu_iu_dbell_interrupt[0]), + .xu_iu_cdbell_interrupt(xu_iu_cdbell_interrupt[0]), + .xu_iu_gdbell_interrupt(xu_iu_gdbell_interrupt[0]), + .xu_iu_gcdbell_interrupt(xu_iu_gcdbell_interrupt[0]), + .xu_iu_gmcdbell_interrupt(xu_iu_gmcdbell_interrupt[0]), + .xu_iu_dbsr_ide(xu_iu_dbsr_ide[0]), + .xu_iu_rest_ifar(xu_iu_t0_rest_ifar), + .cp_is_isync(cp_is_isync_int[0]), + .cp_is_csync(cp_is_csync_int[0]), + .iu_flush(iu_flush[0]), + .cp_flush_into_uc(cp_flush_into_uc[0]), + .cp_uc_flush_ifar(cp_uc_t0_flush_ifar), + .cp_uc_np1_flush(cp_uc_np1_flush[0]), + .cp_flush(cp_flush[0]), + .cp_next_itag(cp_t0_next_itag), + .cp_flush_itag(cp_t0_flush_itag), + .cp_flush_ifar(cp_t0_flush_ifar), + .cp_iu0_flush_2ucode(cp_iu0_flush_2ucode[0]), + .cp_iu0_flush_2ucode_type(cp_iu0_flush_2ucode_type[0]), + .cp_iu0_flush_nonspec(cp_iu0_flush_nonspec[0]), + .pc_iu_init_reset(pc_iu_init_reset), + .cp_rn_uc_credit_free(cp_rn_uc_credit_free[0]), + .iu_xu_rfi(iu_xu_rfi[0]), + .iu_xu_rfgi(iu_xu_rfgi[0]), + .iu_xu_rfci(iu_xu_rfci[0]), + .iu_xu_rfmci(iu_xu_rfmci[0]), + .iu_xu_int(iu_xu_int[0]), + .iu_xu_gint(iu_xu_gint[0]), + .iu_xu_cint(iu_xu_cint[0]), + .iu_xu_mcint(iu_xu_mcint[0]), + .iu_xu_nia(iu_xu_t0_nia), + .iu_xu_esr(iu_xu_t0_esr), + .iu_xu_mcsr(iu_xu_t0_mcsr), + .iu_xu_dbsr(iu_xu_t0_dbsr), + .iu_xu_dear_update(iu_xu_dear_update[0]), + .iu_xu_dear(iu_xu_t0_dear), + .iu_xu_dbsr_update(iu_xu_dbsr_update[0]), + .iu_xu_dbsr_ude(iu_xu_dbsr_ude[0]), + .iu_xu_dbsr_ide(iu_xu_dbsr_ide[0]), + .iu_xu_esr_update(iu_xu_esr_update[0]), + .iu_xu_act(iu_xu_act[0]), + .iu_xu_dbell_taken(iu_xu_dbell_taken[0]), + .iu_xu_cdbell_taken(iu_xu_cdbell_taken[0]), + .iu_xu_gdbell_taken(iu_xu_gdbell_taken[0]), + .iu_xu_gcdbell_taken(iu_xu_gcdbell_taken[0]), + .iu_xu_gmcdbell_taken(iu_xu_gmcdbell_taken[0]), + .iu_xu_instr_cpl(iu_xu_instr_cpl[0]), + .xu_iu_np1_async_flush(xu_iu_np1_async_flush[0]), + .iu_xu_async_complete(iu_xu_async_complete[0]), + .dp_cp_hold_req(dp_cp_hold_req[0]), + .iu_mm_hold_ack(iu_mm_hold_ack[0]), + .dp_cp_bus_snoop_hold_req(dp_cp_bus_snoop_hold_req[0]), + .iu_mm_bus_snoop_hold_ack(iu_mm_bus_snoop_hold_ack[0]), + .iu_spr_eheir_update(iu_spr_eheir_update[0]), + .iu_spr_eheir(iu_spr_t0_eheir), + .xu_iu_msr_de(xu_iu_msr_de[0]), + .xu_iu_msr_pr(xu_iu_msr_pr[0]), + .xu_iu_msr_cm(xu_iu_msr_cm[0]), + .xu_iu_msr_gs(xu_iu_msr_gs[0]), + .xu_iu_msr_me(xu_iu_msr_me[0]), + .xu_iu_dbcr0_edm(xu_iu_dbcr0_edm[0]), + .xu_iu_dbcr0_idm(xu_iu_dbcr0_idm[0]), + .xu_iu_dbcr0_icmp(xu_iu_dbcr0_icmp[0]), + .xu_iu_dbcr0_brt(xu_iu_dbcr0_brt[0]), + .xu_iu_dbcr0_irpt(xu_iu_dbcr0_irpt[0]), + .xu_iu_dbcr0_trap(xu_iu_dbcr0_trap[0]), + .xu_iu_iac1_en(xu_iu_iac1_en[0]), + .xu_iu_iac2_en(xu_iu_iac2_en[0]), + .xu_iu_iac3_en(xu_iu_iac3_en[0]), + .xu_iu_iac4_en(xu_iu_iac4_en[0]), + .xu_iu_dbcr0_dac1(xu_iu_t0_dbcr0_dac1), + .xu_iu_dbcr0_dac2(xu_iu_t0_dbcr0_dac2), + .xu_iu_dbcr0_dac3(xu_iu_t0_dbcr0_dac3), + .xu_iu_dbcr0_dac4(xu_iu_t0_dbcr0_dac4), + .xu_iu_dbcr0_ret(xu_iu_dbcr0_ret[0]), + .xu_iu_dbcr1_iac12m(xu_iu_dbcr1_iac12m[0]), + .xu_iu_dbcr1_iac34m(xu_iu_dbcr1_iac34m[0]), + .lq_iu_spr_dbcr3_ivc(lq_iu_spr_dbcr3_ivc[0]), + .xu_iu_epcr_extgs(xu_iu_epcr_extgs[0]), + .xu_iu_epcr_dtlbgs(xu_iu_epcr_dtlbgs[0]), + .xu_iu_epcr_itlbgs(xu_iu_epcr_itlbgs[0]), + .xu_iu_epcr_dsigs(xu_iu_epcr_dsigs[0]), + .xu_iu_epcr_isigs(xu_iu_epcr_isigs[0]), + .xu_iu_epcr_duvd(xu_iu_epcr_duvd[0]), + .xu_iu_epcr_icm(xu_iu_epcr_icm[0]), + .xu_iu_epcr_gicm(xu_iu_epcr_gicm[0]), + .xu_iu_ccr2_en_dcr(xu_iu_spr_ccr2_en_dcr), + .xu_iu_ccr2_ucode_dis(xu_iu_spr_ccr2_ucode_dis), + .xu_iu_hid_mmu_mode(xu_iu_hid_mmu_mode), + .xu_iu_xucr4_mmu_mchk(xu_iu_xucr4_mmu_mchk), + .iu_xu_quiesce(iu_xu_quiesce[0]), + .iu_pc_quiesce(iu_pc_quiesce[0]), + .mm_iu_ierat_rel_val(mm_iu_ierat_rel_val[0]), + .mm_iu_ierat_pt_fault(mm_iu_ierat_pt_fault[0]), + .mm_iu_ierat_lrat_miss(mm_iu_ierat_lrat_miss[0]), + .mm_iu_ierat_tlb_inelig(mm_iu_ierat_tlb_inelig[0]), + .mm_iu_tlb_multihit_err(mm_iu_tlb_multihit_err[0]), + .mm_iu_tlb_par_err(mm_iu_tlb_par_err[0]), + .mm_iu_lru_par_err(mm_iu_lru_par_err[0]), + .mm_iu_tlb_miss(mm_iu_tlb_miss[0]), + .mm_iu_reload_hit(mm_iu_reload_hit[0]), + .mm_iu_ierat_mmucr1(mm_iu_ierat_mmucr1[3:4]), + .ic_cp_nonspec_hit(ic_cp_nonspec_hit[0]), + .cp_mm_except_taken(cp_mm_except_taken_t0), + .xu_iu_single_instr_mode(xu_iu_single_instr_mode[0]), + .spr_single_issue(spr_single_issue[0]), + .spr_ivpr(spr_ivpr), + .spr_givpr(spr_givpr), + .spr_iac1(spr_iac1), + .spr_iac2(spr_iac2), + .spr_iac3(spr_iac3), + .spr_iac4(spr_iac4), + .iu_rf_xer_p(iu_rf_t0_xer_p), + .pc_iu_ram_active(pc_iu_ram_active[0]), + .pc_iu_ram_flush_thread(pc_iu_ram_flush_thread[0]), + .xu_iu_msrovride_enab(xu_iu_msrovride_enab[0]), + .iu_pc_ram_done(iu_pc_ram_done_int[0]), + .iu_pc_ram_interrupt(iu_pc_ram_interrupt_int[0]), + .iu_pc_ram_unsupported(iu_pc_ram_unsupported_int[0]), + .pc_iu_stop(pc_iu_stop[0]), + .pc_iu_step(pc_iu_step[0]), + .pc_iu_dbg_action(pc_iu_t0_dbg_action), + .iu_pc_step_done(iu_pc_step_done[0]), + .iu_pc_stop_dbg_event(iu_pc_stop_dbg_event_int[0]), + .iu_pc_err_debug_event(iu_pc_err_debug_event[0]), + .iu_pc_attention_instr(iu_pc_attention_instr[0]), + .iu_pc_err_mchk_disabled(iu_pc_err_mchk_disabled[0]), + .ac_an_debug_trigger(ac_an_debug_trigger[0]), + .iu_xu_stop(iu_xu_stop[0]) + ); + +`ifndef THREADS1 + iuq_cpl iuq_cpl1( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .tc_ac_ccflush_dc(tc_ac_ccflush_dc), + .clkoff_dc_b(clkoff_dc_b), + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .func_sl_thold_2(pc_iu_func_sl_thold_2), + .func_slp_sl_thold_2(pc_iu_func_slp_sl_thold_2), + .sg_2(pc_iu_sg_2), + .scan_in(cp_scan_in[1]), + .scan_out(cp_scan_out[1]), + .pc_iu_event_bus_enable(pc_iu_event_bus_enable), + .pc_iu_event_count_mode(pc_iu_event_count_mode), + .spr_cp_perf_event_mux_ctrls(spr_cp_perf_event_mux_ctrls[16:31]), + .event_bus_in(event_bus_in[4:7]), + .event_bus_out(event_bus_out[4:7]), + .rn_cp_iu6_i0_vld(rn_cp_iu6_t1_i0_vld), + .rn_cp_iu6_i0_itag(rn_cp_iu6_t1_i0_itag), + .rn_cp_iu6_i0_ucode(rn_cp_iu6_t1_i0_ucode), + .rn_cp_iu6_i0_fuse_nop(rn_cp_iu6_t1_i0_fuse_nop), + .rn_cp_iu6_i0_rte_lq(rn_cp_iu6_t1_i0_rte_lq), + .rn_cp_iu6_i0_rte_sq(rn_cp_iu6_t1_i0_rte_sq), + .rn_cp_iu6_i0_rte_fx0(rn_cp_iu6_t1_i0_rte_fx0), + .rn_cp_iu6_i0_rte_fx1(rn_cp_iu6_t1_i0_rte_fx1), + .rn_cp_iu6_i0_rte_axu0(rn_cp_iu6_t1_i0_rte_axu0), + .rn_cp_iu6_i0_rte_axu1(rn_cp_iu6_t1_i0_rte_axu1), + .rn_cp_iu6_i0_ifar(rn_cp_iu6_t1_i0_ifar), + .rn_cp_iu6_i0_bta(rn_cp_iu6_t1_i0_bta), + .rn_cp_iu6_i0_isram(rn_cp_iu6_t1_i0_isram), + .rn_cp_iu6_i0_instr(rn_cp_iu6_t1_i0_instr), + .rn_cp_iu6_i0_valop(rn_cp_iu6_t1_i0_valop), + .rn_cp_iu6_i0_error(rn_cp_iu6_t1_i0_error), + .rn_cp_iu6_i0_br_pred(rn_cp_iu6_t1_i0_br_pred), + .rn_cp_iu6_i0_bh_update(rn_cp_iu6_t1_i0_bh_update), + .rn_cp_iu6_i0_bh0_hist(rn_cp_iu6_t1_i0_bh0_hist), + .rn_cp_iu6_i0_bh1_hist(rn_cp_iu6_t1_i0_bh1_hist), + .rn_cp_iu6_i0_bh2_hist(rn_cp_iu6_t1_i0_bh2_hist), + .rn_cp_iu6_i0_gshare(rn_cp_iu6_t1_i0_gshare), + .rn_cp_iu6_i0_ls_ptr(rn_cp_iu6_t1_i0_ls_ptr), + .rn_cp_iu6_i0_match(rn_cp_iu6_t1_i0_match), + .rn_cp_iu6_i0_type_fp(rn_cp_iu6_t1_i0_type_fp), + .rn_cp_iu6_i0_type_ap(rn_cp_iu6_t1_i0_type_ap), + .rn_cp_iu6_i0_type_spv(rn_cp_iu6_t1_i0_type_spv), + .rn_cp_iu6_i0_type_st(rn_cp_iu6_t1_i0_type_st), + .rn_cp_iu6_i0_async_block(rn_cp_iu6_t1_i0_async_block), + .rn_cp_iu6_i0_np1_flush(rn_cp_iu6_t1_i0_np1_flush), + .rn_cp_iu6_i0_t1_v(rn_cp_iu6_t1_i0_t1_v), + .rn_cp_iu6_i0_t1_t(rn_cp_iu6_t1_i0_t1_t), + .rn_cp_iu6_i0_t1_p(rn_cp_iu6_t1_i0_t1_p), + .rn_cp_iu6_i0_t1_a(rn_cp_iu6_t1_i0_t1_a), + .rn_cp_iu6_i0_t2_v(rn_cp_iu6_t1_i0_t2_v), + .rn_cp_iu6_i0_t2_t(rn_cp_iu6_t1_i0_t2_t), + .rn_cp_iu6_i0_t2_p(rn_cp_iu6_t1_i0_t2_p), + .rn_cp_iu6_i0_t2_a(rn_cp_iu6_t1_i0_t2_a), + .rn_cp_iu6_i0_t3_v(rn_cp_iu6_t1_i0_t3_v), + .rn_cp_iu6_i0_t3_t(rn_cp_iu6_t1_i0_t3_t), + .rn_cp_iu6_i0_t3_p(rn_cp_iu6_t1_i0_t3_p), + .rn_cp_iu6_i0_t3_a(rn_cp_iu6_t1_i0_t3_a), + .rn_cp_iu6_i0_btb_entry(rn_cp_iu6_t1_i0_btb_entry), + .rn_cp_iu6_i0_btb_hist(rn_cp_iu6_t1_i0_btb_hist), + .rn_cp_iu6_i0_bta_val(rn_cp_iu6_t1_i0_bta_val), + .rn_cp_iu6_i1_vld(rn_cp_iu6_t1_i1_vld), + .rn_cp_iu6_i1_itag(rn_cp_iu6_t1_i1_itag), + .rn_cp_iu6_i1_ucode(rn_cp_iu6_t1_i1_ucode), + .rn_cp_iu6_i1_fuse_nop(rn_cp_iu6_t1_i1_fuse_nop), + .rn_cp_iu6_i1_rte_lq(rn_cp_iu6_t1_i1_rte_lq), + .rn_cp_iu6_i1_rte_sq(rn_cp_iu6_t1_i1_rte_sq), + .rn_cp_iu6_i1_rte_fx0(rn_cp_iu6_t1_i1_rte_fx0), + .rn_cp_iu6_i1_rte_fx1(rn_cp_iu6_t1_i1_rte_fx1), + .rn_cp_iu6_i1_rte_axu0(rn_cp_iu6_t1_i1_rte_axu0), + .rn_cp_iu6_i1_rte_axu1(rn_cp_iu6_t1_i1_rte_axu1), + .rn_cp_iu6_i1_ifar(rn_cp_iu6_t1_i1_ifar), + .rn_cp_iu6_i1_bta(rn_cp_iu6_t1_i1_bta), + .rn_cp_iu6_i1_isram(rn_cp_iu6_t1_i1_isram), + .rn_cp_iu6_i1_instr(rn_cp_iu6_t1_i1_instr), + .rn_cp_iu6_i1_valop(rn_cp_iu6_t1_i1_valop), + .rn_cp_iu6_i1_error(rn_cp_iu6_t1_i1_error), + .rn_cp_iu6_i1_br_pred(rn_cp_iu6_t1_i1_br_pred), + .rn_cp_iu6_i1_bh_update(rn_cp_iu6_t1_i1_bh_update), + .rn_cp_iu6_i1_bh0_hist(rn_cp_iu6_t1_i1_bh0_hist), + .rn_cp_iu6_i1_bh1_hist(rn_cp_iu6_t1_i1_bh1_hist), + .rn_cp_iu6_i1_bh2_hist(rn_cp_iu6_t1_i1_bh2_hist), + .rn_cp_iu6_i1_gshare(rn_cp_iu6_t1_i1_gshare), + .rn_cp_iu6_i1_ls_ptr(rn_cp_iu6_t1_i1_ls_ptr), + .rn_cp_iu6_i1_match(rn_cp_iu6_t1_i1_match), + .rn_cp_iu6_i1_type_fp(rn_cp_iu6_t1_i1_type_fp), + .rn_cp_iu6_i1_type_ap(rn_cp_iu6_t1_i1_type_ap), + .rn_cp_iu6_i1_type_spv(rn_cp_iu6_t1_i1_type_spv), + .rn_cp_iu6_i1_type_st(rn_cp_iu6_t1_i1_type_st), + .rn_cp_iu6_i1_async_block(rn_cp_iu6_t1_i1_async_block), + .rn_cp_iu6_i1_np1_flush(rn_cp_iu6_t1_i1_np1_flush), + .rn_cp_iu6_i1_t1_v(rn_cp_iu6_t1_i1_t1_v), + .rn_cp_iu6_i1_t1_t(rn_cp_iu6_t1_i1_t1_t), + .rn_cp_iu6_i1_t1_p(rn_cp_iu6_t1_i1_t1_p), + .rn_cp_iu6_i1_t1_a(rn_cp_iu6_t1_i1_t1_a), + .rn_cp_iu6_i1_t2_v(rn_cp_iu6_t1_i1_t2_v), + .rn_cp_iu6_i1_t2_t(rn_cp_iu6_t1_i1_t2_t), + .rn_cp_iu6_i1_t2_p(rn_cp_iu6_t1_i1_t2_p), + .rn_cp_iu6_i1_t2_a(rn_cp_iu6_t1_i1_t2_a), + .rn_cp_iu6_i1_t3_v(rn_cp_iu6_t1_i1_t3_v), + .rn_cp_iu6_i1_t3_t(rn_cp_iu6_t1_i1_t3_t), + .rn_cp_iu6_i1_t3_p(rn_cp_iu6_t1_i1_t3_p), + .rn_cp_iu6_i1_t3_a(rn_cp_iu6_t1_i1_t3_a), + .rn_cp_iu6_i1_btb_entry(rn_cp_iu6_t1_i1_btb_entry), + .rn_cp_iu6_i1_btb_hist(rn_cp_iu6_t1_i1_btb_hist), + .rn_cp_iu6_i1_bta_val(rn_cp_iu6_t1_i1_bta_val), + .cp_rn_empty(cp_rn_empty[1]), + .cp_async_block(cp_async_block[1]), + .cp_rn_i0_v(cp_rn_t1_i0_v), + .cp_rn_i0_axu_exception_val(cp_rn_t1_i0_axu_exception_val), + .cp_rn_i0_axu_exception(cp_rn_t1_i0_axu_exception), + .cp_rn_i0_t1_v(cp_rn_t1_i0_t1_v), + .cp_rn_i0_t1_t(cp_rn_t1_i0_t1_t), + .cp_rn_i0_t1_p(cp_rn_t1_i0_t1_p), + .cp_rn_i0_t1_a(cp_rn_t1_i0_t1_a), + .cp_rn_i0_t2_v(cp_rn_t1_i0_t2_v), + .cp_rn_i0_t2_t(cp_rn_t1_i0_t2_t), + .cp_rn_i0_t2_p(cp_rn_t1_i0_t2_p), + .cp_rn_i0_t2_a(cp_rn_t1_i0_t2_a), + .cp_rn_i0_t3_v(cp_rn_t1_i0_t3_v), + .cp_rn_i0_t3_t(cp_rn_t1_i0_t3_t), + .cp_rn_i0_t3_p(cp_rn_t1_i0_t3_p), + .cp_rn_i0_t3_a(cp_rn_t1_i0_t3_a), + .cp_rn_i1_v(cp_rn_t1_i1_v), + .cp_rn_i1_axu_exception_val(cp_rn_t1_i1_axu_exception_val), + .cp_rn_i1_axu_exception(cp_rn_t1_i1_axu_exception), + .cp_rn_i1_t1_v(cp_rn_t1_i1_t1_v), + .cp_rn_i1_t1_t(cp_rn_t1_i1_t1_t), + .cp_rn_i1_t1_p(cp_rn_t1_i1_t1_p), + .cp_rn_i1_t1_a(cp_rn_t1_i1_t1_a), + .cp_rn_i1_t2_v(cp_rn_t1_i1_t2_v), + .cp_rn_i1_t2_t(cp_rn_t1_i1_t2_t), + .cp_rn_i1_t2_p(cp_rn_t1_i1_t2_p), + .cp_rn_i1_t2_a(cp_rn_t1_i1_t2_a), + .cp_rn_i1_t3_v(cp_rn_t1_i1_t3_v), + .cp_rn_i1_t3_t(cp_rn_t1_i1_t3_t), + .cp_rn_i1_t3_p(cp_rn_t1_i1_t3_p), + .cp_rn_i1_t3_a(cp_rn_t1_i1_t3_a), + .cp_bp_val(cp_bp_t1_val), + .cp_bp_ifar(cp_bp_t1_ifar), + .cp_bp_bh0_hist(cp_bp_t1_bh0_hist), + .cp_bp_bh1_hist(cp_bp_t1_bh1_hist), + .cp_bp_bh2_hist(cp_bp_t1_bh2_hist), + .cp_bp_br_pred(cp_bp_t1_br_pred), + .cp_bp_br_taken(cp_bp_t1_br_taken), + .cp_bp_bh_update(cp_bp_t1_bh_update), + .cp_bp_bcctr(cp_bp_t1_bcctr), + .cp_bp_bclr(cp_bp_t1_bclr), + .cp_bp_getnia(cp_bp_t1_getnia), + .cp_bp_group(cp_bp_t1_group), + .cp_dis_ivax(cp_dis_ivax[1]), + .cp_bp_lk(cp_bp_t1_lk), + .cp_bp_bh(cp_bp_t1_bh), + .cp_bp_gshare(cp_bp_t1_gshare), + .cp_bp_ls_ptr(cp_bp_t1_ls_ptr), + .cp_bp_ctr(cp_bp_t1_ctr), + .cp_bp_btb_entry(cp_bp_t1_btb_entry), + .cp_bp_btb_hist(cp_bp_t1_btb_hist), + .lq0_iu_execute_vld(lq0_iu_execute_vld[1]), + .lq0_iu_itag(lq0_iu_itag), + .lq0_iu_n_flush(lq0_iu_n_flush), + .lq0_iu_np1_flush(lq0_iu_np1_flush), + .lq0_iu_dacr_type(lq0_iu_dacr_type), + .lq0_iu_dacrw(lq0_iu_dacrw), + .lq0_iu_instr(lq0_iu_instr), + .lq0_iu_eff_addr(lq0_iu_eff_addr), + .lq0_iu_exception_val(lq0_iu_exception_val), + .lq0_iu_exception(lq0_iu_exception), + .lq0_iu_flush2ucode(lq0_iu_flush2ucode), + .lq0_iu_flush2ucode_type(lq0_iu_flush2ucode_type), + .lq0_iu_recirc_val(lq0_iu_recirc_val[1]), + .lq0_iu_dear_val(lq0_iu_dear_val[1]), + .lq1_iu_execute_vld(lq1_iu_execute_vld[1]), + .lq1_iu_itag(lq1_iu_itag), + .lq1_iu_n_flush(lq1_iu_n_flush), + .lq1_iu_np1_flush(lq1_iu_np1_flush), + .lq1_iu_exception_val(lq1_iu_exception_val), + .lq1_iu_exception(lq1_iu_exception), + .lq1_iu_dacr_type(lq1_iu_dacr_type), + .lq1_iu_dacrw(lq1_iu_dacrw), + .lq1_iu_perf_events(lq1_iu_perf_events), + .iu_lq_i0_completed(iu_lq_i0_completed[1]), + .iu_lq_i1_completed(iu_lq_i1_completed[1]), + .iu_lq_i0_completed_itag(iu_lq_t1_i0_completed_itag), + .iu_lq_i1_completed_itag(iu_lq_t1_i1_completed_itag), + .iu_lq_recirc_val(iu_lq_recirc_val[1]), + .br_iu_execute_vld(br_iu_execute_vld[1]), + .br_iu_itag(br_iu_itag), + .br_iu_bta(br_iu_bta), + .br_iu_redirect(br_iu_redirect[1]), + .br_iu_taken(br_iu_taken), + .xu_iu_execute_vld(xu_iu_execute_vld[1]), + .xu_iu_itag(xu_iu_itag), + .xu_iu_exception_val(xu_iu_exception_val), + .xu_iu_exception(xu_iu_exception), + .xu_iu_mtiar(xu_iu_mtiar[1]), + .xu_iu_bta(xu_iu_bta), + .xu_iu_perf_events(xu_iu_perf_events), + .xu_iu_n_flush(xu_iu_n_flush), + .xu_iu_np1_flush(xu_iu_np1_flush), + .xu_iu_flush2ucode(xu_iu_flush2ucode), + .xu1_iu_execute_vld(xu1_iu_execute_vld[1]), + .xu1_iu_itag(xu1_iu_itag), + .axu0_iu_execute_vld(axu0_iu_execute_vld[1]), + .axu0_iu_itag(axu0_iu_itag), + .axu0_iu_n_flush(axu0_iu_n_flush), + .axu0_iu_np1_flush(axu0_iu_np1_flush), + .axu0_iu_n_np1_flush(axu0_iu_n_np1_flush), + .axu0_iu_exception(axu0_iu_exception), + .axu0_iu_exception_val(axu0_iu_exception_val), + .axu0_iu_flush2ucode(axu0_iu_flush2ucode), + .axu0_iu_flush2ucode_type(axu0_iu_flush2ucode_type), + .axu0_iu_async_fex(axu0_iu_async_fex[1]), + .axu1_iu_execute_vld(axu1_iu_execute_vld[1]), + .axu1_iu_itag(axu1_iu_itag), + .axu1_iu_n_flush(axu1_iu_n_flush), + .axu1_iu_np1_flush(axu1_iu_np1_flush), + .axu1_iu_exception(axu1_iu_exception), + .axu1_iu_exception_val(axu1_iu_exception_val), + .axu1_iu_flush2ucode(axu1_iu_flush2ucode), + .axu1_iu_flush2ucode_type(axu1_iu_flush2ucode_type), + .an_ac_uncond_dbg_event(an_ac_uncond_dbg_event[1]), + .xu_iu_external_mchk(xu_iu_external_mchk[1]), + .xu_iu_ext_interrupt(xu_iu_ext_interrupt[1]), + .xu_iu_dec_interrupt(xu_iu_dec_interrupt[1]), + .xu_iu_udec_interrupt(xu_iu_udec_interrupt[1]), + .xu_iu_perf_interrupt(xu_iu_perf_interrupt[1]), + .xu_iu_fit_interrupt(xu_iu_fit_interrupt[1]), + .xu_iu_crit_interrupt(xu_iu_crit_interrupt[1]), + .xu_iu_wdog_interrupt(xu_iu_wdog_interrupt[1]), + .xu_iu_gwdog_interrupt(xu_iu_gwdog_interrupt[1]), + .xu_iu_gfit_interrupt(xu_iu_gfit_interrupt[1]), + .xu_iu_gdec_interrupt(xu_iu_gdec_interrupt[1]), + .xu_iu_dbell_interrupt(xu_iu_dbell_interrupt[1]), + .xu_iu_cdbell_interrupt(xu_iu_cdbell_interrupt[1]), + .xu_iu_gdbell_interrupt(xu_iu_gdbell_interrupt[1]), + .xu_iu_gcdbell_interrupt(xu_iu_gcdbell_interrupt[1]), + .xu_iu_gmcdbell_interrupt(xu_iu_gmcdbell_interrupt[1]), + .xu_iu_dbsr_ide(xu_iu_dbsr_ide[1]), + .xu_iu_rest_ifar(xu_iu_t1_rest_ifar), + .cp_is_isync(cp_is_isync_int[1]), + .cp_is_csync(cp_is_csync_int[1]), + .iu_flush(iu_flush[1]), + .cp_flush_into_uc(cp_flush_into_uc[1]), + .cp_uc_flush_ifar(cp_uc_t1_flush_ifar), + .cp_uc_np1_flush(cp_uc_np1_flush[1]), + .cp_flush(cp_flush[1]), + .cp_next_itag(cp_t1_next_itag), + .cp_flush_itag(cp_t1_flush_itag), + .cp_flush_ifar(cp_t1_flush_ifar), + .cp_iu0_flush_2ucode(cp_iu0_flush_2ucode[1]), + .cp_iu0_flush_2ucode_type(cp_iu0_flush_2ucode_type[1]), + .cp_iu0_flush_nonspec(cp_iu0_flush_nonspec[1]), + .pc_iu_init_reset(pc_iu_init_reset), + .cp_rn_uc_credit_free(cp_rn_uc_credit_free[1]), + .iu_xu_rfi(iu_xu_rfi[1]), + .iu_xu_rfgi(iu_xu_rfgi[1]), + .iu_xu_rfci(iu_xu_rfci[1]), + .iu_xu_rfmci(iu_xu_rfmci[1]), + .iu_xu_int(iu_xu_int[1]), + .iu_xu_gint(iu_xu_gint[1]), + .iu_xu_cint(iu_xu_cint[1]), + .iu_xu_mcint(iu_xu_mcint[1]), + .iu_xu_nia(iu_xu_t1_nia), + .iu_xu_esr(iu_xu_t1_esr), + .iu_xu_mcsr(iu_xu_t1_mcsr), + .iu_xu_dbsr(iu_xu_t1_dbsr), + .iu_xu_dear_update(iu_xu_dear_update[1]), + .iu_xu_dear(iu_xu_t1_dear), + .iu_xu_dbsr_update(iu_xu_dbsr_update[1]), + .iu_xu_dbsr_ude(iu_xu_dbsr_ude[1]), + .iu_xu_dbsr_ide(iu_xu_dbsr_ide[1]), + .iu_xu_esr_update(iu_xu_esr_update[1]), + .iu_xu_act(iu_xu_act[1]), + .iu_xu_dbell_taken(iu_xu_dbell_taken[1]), + .iu_xu_cdbell_taken(iu_xu_cdbell_taken[1]), + .iu_xu_gdbell_taken(iu_xu_gdbell_taken[1]), + .iu_xu_gcdbell_taken(iu_xu_gcdbell_taken[1]), + .iu_xu_gmcdbell_taken(iu_xu_gmcdbell_taken[1]), + .iu_xu_instr_cpl(iu_xu_instr_cpl[1]), + .xu_iu_np1_async_flush(xu_iu_np1_async_flush[1]), + .iu_xu_async_complete(iu_xu_async_complete[1]), + .dp_cp_hold_req(dp_cp_hold_req[1]), + .iu_mm_hold_ack(iu_mm_hold_ack[1]), + .dp_cp_bus_snoop_hold_req(dp_cp_bus_snoop_hold_req[1]), + .iu_mm_bus_snoop_hold_ack(iu_mm_bus_snoop_hold_ack[1]), + .iu_spr_eheir_update(iu_spr_eheir_update[1]), + .iu_spr_eheir(iu_spr_t1_eheir), + .xu_iu_msr_de(xu_iu_msr_de[1]), + .xu_iu_msr_pr(xu_iu_msr_pr[1]), + .xu_iu_msr_cm(xu_iu_msr_cm[1]), + .xu_iu_msr_gs(xu_iu_msr_gs[1]), + .xu_iu_msr_me(xu_iu_msr_me[1]), + .xu_iu_dbcr0_edm(xu_iu_dbcr0_edm[1]), + .xu_iu_dbcr0_idm(xu_iu_dbcr0_idm[1]), + .xu_iu_dbcr0_icmp(xu_iu_dbcr0_icmp[1]), + .xu_iu_dbcr0_brt(xu_iu_dbcr0_brt[1]), + .xu_iu_dbcr0_irpt(xu_iu_dbcr0_irpt[1]), + .xu_iu_dbcr0_trap(xu_iu_dbcr0_trap[1]), + .xu_iu_iac1_en(xu_iu_iac1_en[1]), + .xu_iu_iac2_en(xu_iu_iac2_en[1]), + .xu_iu_iac3_en(xu_iu_iac3_en[1]), + .xu_iu_iac4_en(xu_iu_iac4_en[1]), + .xu_iu_dbcr0_dac1(xu_iu_t1_dbcr0_dac1), + .xu_iu_dbcr0_dac2(xu_iu_t1_dbcr0_dac2), + .xu_iu_dbcr0_dac3(xu_iu_t1_dbcr0_dac3), + .xu_iu_dbcr0_dac4(xu_iu_t1_dbcr0_dac4), + .xu_iu_dbcr0_ret(xu_iu_dbcr0_ret[1]), + .xu_iu_dbcr1_iac12m(xu_iu_dbcr1_iac12m[1]), + .xu_iu_dbcr1_iac34m(xu_iu_dbcr1_iac34m[1]), + .lq_iu_spr_dbcr3_ivc(lq_iu_spr_dbcr3_ivc[1]), + .xu_iu_epcr_extgs(xu_iu_epcr_extgs[1]), + .xu_iu_epcr_dtlbgs(xu_iu_epcr_dtlbgs[1]), + .xu_iu_epcr_itlbgs(xu_iu_epcr_itlbgs[1]), + .xu_iu_epcr_dsigs(xu_iu_epcr_dsigs[1]), + .xu_iu_epcr_isigs(xu_iu_epcr_isigs[1]), + .xu_iu_epcr_duvd(xu_iu_epcr_duvd[1]), + .xu_iu_epcr_icm(xu_iu_epcr_icm[1]), + .xu_iu_epcr_gicm(xu_iu_epcr_gicm[1]), + .xu_iu_ccr2_en_dcr(xu_iu_spr_ccr2_en_dcr), + .xu_iu_ccr2_ucode_dis(xu_iu_spr_ccr2_ucode_dis), + .xu_iu_hid_mmu_mode(xu_iu_hid_mmu_mode), + .xu_iu_xucr4_mmu_mchk(xu_iu_xucr4_mmu_mchk), + .iu_xu_quiesce(iu_xu_quiesce[1]), + .iu_pc_quiesce(iu_pc_quiesce[1]), + .mm_iu_ierat_rel_val(mm_iu_ierat_rel_val[1]), + .mm_iu_ierat_pt_fault(mm_iu_ierat_pt_fault[1]), + .mm_iu_ierat_lrat_miss(mm_iu_ierat_lrat_miss[1]), + .mm_iu_ierat_tlb_inelig(mm_iu_ierat_tlb_inelig[1]), + .mm_iu_tlb_multihit_err(mm_iu_tlb_multihit_err[1]), + .mm_iu_tlb_par_err(mm_iu_tlb_par_err[1]), + .mm_iu_lru_par_err(mm_iu_lru_par_err[1]), + .mm_iu_tlb_miss(mm_iu_tlb_miss[1]), + .mm_iu_reload_hit(mm_iu_reload_hit[1]), + .mm_iu_ierat_mmucr1(mm_iu_ierat_mmucr1[3:4]), + .ic_cp_nonspec_hit(ic_cp_nonspec_hit[1]), + .cp_mm_except_taken(cp_mm_except_taken_t1), + .xu_iu_single_instr_mode(xu_iu_single_instr_mode[1]), + .spr_single_issue(spr_single_issue[1]), + .spr_ivpr(spr_ivpr), + .spr_givpr(spr_givpr), + .spr_iac1(spr_iac1), + .spr_iac2(spr_iac2), + .spr_iac3(spr_iac3), + .spr_iac4(spr_iac4), + .iu_rf_xer_p(iu_rf_t1_xer_p), + .pc_iu_ram_active(pc_iu_ram_active[1]), + .pc_iu_ram_flush_thread(pc_iu_ram_flush_thread[1]), + .xu_iu_msrovride_enab(xu_iu_msrovride_enab[1]), + .iu_pc_ram_done(iu_pc_ram_done_int[1]), + .iu_pc_ram_interrupt(iu_pc_ram_interrupt_int[1]), + .iu_pc_ram_unsupported(iu_pc_ram_unsupported_int[1]), + .pc_iu_stop(pc_iu_stop[1]), + .pc_iu_step(pc_iu_step[1]), + .pc_iu_dbg_action(pc_iu_t1_dbg_action), + .iu_pc_step_done(iu_pc_step_done[1]), + .iu_pc_stop_dbg_event(iu_pc_stop_dbg_event_int[1]), + .iu_pc_err_debug_event(iu_pc_err_debug_event[1]), + .iu_pc_attention_instr(iu_pc_attention_instr[1]), + .iu_pc_err_mchk_disabled(iu_pc_err_mchk_disabled[1]), + .ac_an_debug_trigger(ac_an_debug_trigger[1]), + .iu_xu_stop(iu_xu_stop[1]) + ); +`endif + + +iuq_dbg iuq_cpl_dbg( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .thold_2(pc_iu_func_sl_thold_2), + .pc_iu_sg_2(pc_iu_sg_2), + .clkoff_b(clkoff_b), + .act_dis(act_dis), + .tc_ac_ccflush_dc(tc_ac_ccflush_dc), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .func_scan_in(cp_scan_in[`THREADS]), + .func_scan_out(cp_scan_out[`THREADS]), + .unit_dbg_data0(unit_dbg_data0), + .unit_dbg_data1(unit_dbg_data1), + .unit_dbg_data2(unit_dbg_data2), + .unit_dbg_data3(unit_dbg_data3), + .unit_dbg_data4(unit_dbg_data4), + .unit_dbg_data5(unit_dbg_data5), + .unit_dbg_data6(unit_dbg_data6), + .unit_dbg_data7(unit_dbg_data7), + .unit_dbg_data8(unit_dbg_data8), + .unit_dbg_data9(unit_dbg_data9), + .unit_dbg_data10(unit_dbg_data10), + .unit_dbg_data11(unit_dbg_data11), + .unit_dbg_data12(unit_dbg_data12), + .unit_dbg_data13(unit_dbg_data13), + .unit_dbg_data14(unit_dbg_data14), + .unit_dbg_data15(unit_dbg_data15), + .pc_iu_trace_bus_enable(pc_iu_trace_bus_enable), + .pc_iu_debug_mux_ctrls(pc_iu_debug_mux_ctrls), + .debug_bus_in(debug_bus_in), + .debug_bus_out(debug_bus_out), + .coretrace_ctrls_in(coretrace_ctrls_in), + .coretrace_ctrls_out(coretrace_ctrls_out) +); + + +endmodule diff --git a/dev/verilog/work/iuq_dbg.v b/dev/verilog/work/iuq_dbg.v new file mode 100755 index 0000000..3abd9a0 --- /dev/null +++ b/dev/verilog/work/iuq_dbg.v @@ -0,0 +1,264 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//******************************************************************** +//* +//* TITLE: Instruction Unit Debug +//* +//* NAME: iuq_dbg.v +//* +//********************************************************************* + +`include "tri_a2o.vh" + +module iuq_dbg( + inout vdd, + inout gnd, + + (* pin_data ="PIN_FUNCTION=/G_CLK/" *) + input [0:`NCLK_WIDTH-1] nclk, + input thold_2, // Connect to slp if unit uses slp + input pc_iu_sg_2, + input clkoff_b, + input act_dis, + input tc_ac_ccflush_dc, + input d_mode, + input delay_lclkr, + input mpw1_b, + input mpw2_b, + (* pin_data ="PIN_FUNCTION=/SCAN_IN/" *) + input func_scan_in, + (* pin_data ="PIN_FUNCTION=/SCAN_OUT/" *) + output func_scan_out, + + input [0:31] unit_dbg_data0, + input [0:31] unit_dbg_data1, + input [0:31] unit_dbg_data2, + input [0:31] unit_dbg_data3, + input [0:31] unit_dbg_data4, + input [0:31] unit_dbg_data5, + input [0:31] unit_dbg_data6, + input [0:31] unit_dbg_data7, + input [0:31] unit_dbg_data8, + input [0:31] unit_dbg_data9, + input [0:31] unit_dbg_data10, + input [0:31] unit_dbg_data11, + input [0:31] unit_dbg_data12, + input [0:31] unit_dbg_data13, + input [0:31] unit_dbg_data14, + input [0:31] unit_dbg_data15, + + input pc_iu_trace_bus_enable, + input [0:10] pc_iu_debug_mux_ctrls, + + input [0:31] debug_bus_in, + output [0:31] debug_bus_out, + input [0:3] coretrace_ctrls_in, + output [0:3] coretrace_ctrls_out +); + + localparam trace_bus_enable_offset = 0; + localparam debug_mux_ctrls_offset = trace_bus_enable_offset + 1; + localparam trace_data_out_offset = debug_mux_ctrls_offset + 11; + localparam coretrace_ctrls_out_offset = trace_data_out_offset + 32; + localparam scan_right = coretrace_ctrls_out_offset + 4 - 1; + + wire trace_bus_enable_d; + wire trace_bus_enable_q; + + wire [0:10] debug_mux_ctrls_d; + wire [0:10] debug_mux_ctrls_q; + + wire [0:31] trace_data_out_d; + wire [0:31] trace_data_out_q; + + wire [0:3] coretrace_ctrls_out_d; + wire [0:3] coretrace_ctrls_out_q; + + wire [0:scan_right] siv; + wire [0:scan_right] sov; + + wire thold_1; + wire thold_0; + wire thold_0_b; + wire pc_iu_sg_1; + wire pc_iu_sg_0; + wire force_t; + + wire tiup; + + //BEGIN + + assign tiup = 1'b1; + + tri_debug_mux16 dbg_mux0( + //.vd(vdd), + //.gd(gnd), + .select_bits(debug_mux_ctrls_q), + .trace_data_in(debug_bus_in), + .dbg_group0(unit_dbg_data0), + .dbg_group1(unit_dbg_data1), + .dbg_group2(unit_dbg_data2), + .dbg_group3(unit_dbg_data3), + .dbg_group4(unit_dbg_data4), + .dbg_group5(unit_dbg_data5), + .dbg_group6(unit_dbg_data6), + .dbg_group7(unit_dbg_data7), + .dbg_group8(unit_dbg_data8), + .dbg_group9(unit_dbg_data9), + .dbg_group10(unit_dbg_data10), + .dbg_group11(unit_dbg_data11), + .dbg_group12(unit_dbg_data12), + .dbg_group13(unit_dbg_data13), + .dbg_group14(unit_dbg_data14), + .dbg_group15(unit_dbg_data15), + .trace_data_out(trace_data_out_d), + .coretrace_ctrls_in(coretrace_ctrls_in), + .coretrace_ctrls_out(coretrace_ctrls_out_d) + ); + + assign debug_bus_out = trace_data_out_q; + assign coretrace_ctrls_out = coretrace_ctrls_out_q; + + //--------------------------------------------------------------------- + // Latches + //--------------------------------------------------------------------- + assign trace_bus_enable_d = pc_iu_trace_bus_enable; + assign debug_mux_ctrls_d = pc_iu_debug_mux_ctrls; + + tri_rlmlatch_p #(.INIT(0)) trace_bus_enable_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[trace_bus_enable_offset]), + .scout(sov[trace_bus_enable_offset]), + .din(trace_bus_enable_d), + .dout(trace_bus_enable_q) + ); + + tri_rlmreg_p #(.WIDTH(11), .INIT(0)) debug_mux_ctrls_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(trace_bus_enable_q), + .thold_b(thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[debug_mux_ctrls_offset:debug_mux_ctrls_offset + 10]), + .scout(sov[debug_mux_ctrls_offset:debug_mux_ctrls_offset + 10]), + .din(debug_mux_ctrls_d), + .dout(debug_mux_ctrls_q) + ); + + tri_rlmreg_p #(.WIDTH(32), .INIT(0)) trace_data_out_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(trace_bus_enable_q), + .thold_b(thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[trace_data_out_offset:trace_data_out_offset + 31]), + .scout(sov[trace_data_out_offset:trace_data_out_offset + 31]), + .din(trace_data_out_d), + .dout(trace_data_out_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) coretrace_ctrls_out_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(trace_bus_enable_q), + .thold_b(thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[coretrace_ctrls_out_offset:coretrace_ctrls_out_offset + 3]), + .scout(sov[coretrace_ctrls_out_offset:coretrace_ctrls_out_offset + 3]), + .din(coretrace_ctrls_out_d), + .dout(coretrace_ctrls_out_q) + ); + + //--------------------------------------------------------------------- + // pervasive thold/sg latches + //--------------------------------------------------------------------- + tri_plat #(.WIDTH(2)) perv_2to1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + .din({thold_2, pc_iu_sg_2}), + .q( {thold_1, pc_iu_sg_1}) + ); + + tri_plat #(.WIDTH(2)) perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + .din({thold_1, pc_iu_sg_1}), + .q( {thold_0, pc_iu_sg_0}) + ); + + tri_lcbor perv_lcbor( + .clkoff_b(clkoff_b), + .thold(thold_0), + .sg(pc_iu_sg_0), + .act_dis(act_dis), + .force_t(force_t), + .thold_b(thold_0_b) + ); + + //--------------------------------------------------------------------- + // Scan + //--------------------------------------------------------------------- + assign siv[0:scan_right] = {sov[1:scan_right], func_scan_in}; + assign func_scan_out = sov[0]; + +endmodule diff --git a/dev/verilog/work/iuq_dec_top.v b/dev/verilog/work/iuq_dec_top.v new file mode 100755 index 0000000..d130a9e --- /dev/null +++ b/dev/verilog/work/iuq_dec_top.v @@ -0,0 +1,711 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//******************************************************************** +//* +//* TITLE: +//* +//* NAME: iuq_dec_top.vhdl +//* +//********************************************************************* + + +`include "tri_a2o.vh" + +module iuq_dec_top( + inout vdd, + inout gnd, + input [0:`NCLK_WIDTH-1] nclk, + input pc_iu_sg_2, + input pc_iu_func_sl_thold_2, + input clkoff_b, + input act_dis, + input tc_ac_ccflush_dc, + input d_mode, + input delay_lclkr, + input mpw1_b, + input mpw2_b, + input [0:3] scan_in, + output [0:3] scan_out, + + input xu_iu_epcr_dgtmi, + input xu_iu_msrp_uclep, + input xu_iu_msr_pr, + input xu_iu_msr_gs, + input xu_iu_msr_ucle, + input xu_iu_ccr2_ucode_dis, + + input [0:31] spr_dec_mask, + input [0:31] spr_dec_match, + input [0:7] iu_au_config_iucr, + input mm_iu_tlbwe_binv, + + input cp_iu_iu4_flush, + input uc_ib_iu3_flush_all, + input br_iu_redirect, + + input ib_id_iu4_0_valid, + input [62-`EFF_IFAR_WIDTH:61] ib_id_iu4_0_ifar, + input [62-`EFF_IFAR_WIDTH:61] ib_id_iu4_0_bta, + input [0:69] ib_id_iu4_0_instr, + input [0:2] ib_id_iu4_0_ucode, + input [0:3] ib_id_iu4_0_ucode_ext, + input ib_id_iu4_0_isram, + input [0:31] ib_id_iu4_0_fuse_data, + input ib_id_iu4_0_fuse_val, + + input ib_id_iu4_1_valid, + input [62-`EFF_IFAR_WIDTH:61] ib_id_iu4_1_ifar, + input [62-`EFF_IFAR_WIDTH:61] ib_id_iu4_1_bta, + input [0:69] ib_id_iu4_1_instr, + input [0:2] ib_id_iu4_1_ucode, + input [0:3] ib_id_iu4_1_ucode_ext, + input ib_id_iu4_1_isram, + input [0:31] ib_id_iu4_1_fuse_data, + input ib_id_iu4_1_fuse_val, + + output id_ib_iu4_stall, + + // Decoded instruction to send to rename + output fdec_frn_iu5_i0_vld, + output [0:2] fdec_frn_iu5_i0_ucode, + output fdec_frn_iu5_i0_2ucode, + output fdec_frn_iu5_i0_fuse_nop, + output fdec_frn_iu5_i0_rte_lq, + output fdec_frn_iu5_i0_rte_sq, + output fdec_frn_iu5_i0_rte_fx0, + output fdec_frn_iu5_i0_rte_fx1, + output fdec_frn_iu5_i0_rte_axu0, + output fdec_frn_iu5_i0_rte_axu1, + output fdec_frn_iu5_i0_valop, + output fdec_frn_iu5_i0_ord, + output fdec_frn_iu5_i0_cord, + output [0:2] fdec_frn_iu5_i0_error, + output [0:19] fdec_frn_iu5_i0_fusion, + output fdec_frn_iu5_i0_spec, + output fdec_frn_iu5_i0_type_fp, + output fdec_frn_iu5_i0_type_ap, + output fdec_frn_iu5_i0_type_spv, + output fdec_frn_iu5_i0_type_st, + output fdec_frn_iu5_i0_async_block, + output fdec_frn_iu5_i0_np1_flush, + output fdec_frn_iu5_i0_core_block, + output fdec_frn_iu5_i0_isram, + output fdec_frn_iu5_i0_isload, + output fdec_frn_iu5_i0_isstore, + output [0:31] fdec_frn_iu5_i0_instr, + output [62-`EFF_IFAR_WIDTH:61] fdec_frn_iu5_i0_ifar, + output [62-`EFF_IFAR_WIDTH:61] fdec_frn_iu5_i0_bta, + output [0:3] fdec_frn_iu5_i0_ilat, + output fdec_frn_iu5_i0_t1_v, + output [0:2] fdec_frn_iu5_i0_t1_t, + output [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i0_t1_a, + output fdec_frn_iu5_i0_t2_v, + output [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i0_t2_a, + output [0:2] fdec_frn_iu5_i0_t2_t, + output fdec_frn_iu5_i0_t3_v, + output [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i0_t3_a, + output [0:2] fdec_frn_iu5_i0_t3_t, + output fdec_frn_iu5_i0_s1_v, + output [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i0_s1_a, + output [0:2] fdec_frn_iu5_i0_s1_t, + output fdec_frn_iu5_i0_s2_v, + output [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i0_s2_a, + output [0:2] fdec_frn_iu5_i0_s2_t, + output fdec_frn_iu5_i0_s3_v, + output [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i0_s3_a, + output [0:2] fdec_frn_iu5_i0_s3_t, + output fdec_frn_iu5_i0_br_pred, + output fdec_frn_iu5_i0_bh_update, + output [0:1] fdec_frn_iu5_i0_bh0_hist, + output [0:1] fdec_frn_iu5_i0_bh1_hist, + output [0:1] fdec_frn_iu5_i0_bh2_hist, + output [0:17] fdec_frn_iu5_i0_gshare, + output [0:2] fdec_frn_iu5_i0_ls_ptr, + output fdec_frn_iu5_i0_match, + output fdec_frn_iu5_i0_btb_entry, + output [0:1] fdec_frn_iu5_i0_btb_hist, + output fdec_frn_iu5_i0_bta_val, + + output fdec_frn_iu5_i1_vld, + output [0:2] fdec_frn_iu5_i1_ucode, + output fdec_frn_iu5_i1_fuse_nop, + output fdec_frn_iu5_i1_rte_lq, + output fdec_frn_iu5_i1_rte_sq, + output fdec_frn_iu5_i1_rte_fx0, + output fdec_frn_iu5_i1_rte_fx1, + output fdec_frn_iu5_i1_rte_axu0, + output fdec_frn_iu5_i1_rte_axu1, + output fdec_frn_iu5_i1_valop, + output fdec_frn_iu5_i1_ord, + output fdec_frn_iu5_i1_cord, + output [0:2] fdec_frn_iu5_i1_error, + output [0:19] fdec_frn_iu5_i1_fusion, + output fdec_frn_iu5_i1_spec, + output fdec_frn_iu5_i1_type_fp, + output fdec_frn_iu5_i1_type_ap, + output fdec_frn_iu5_i1_type_spv, + output fdec_frn_iu5_i1_type_st, + output fdec_frn_iu5_i1_async_block, + output fdec_frn_iu5_i1_np1_flush, + output fdec_frn_iu5_i1_core_block, + output fdec_frn_iu5_i1_isram, + output fdec_frn_iu5_i1_isload, + output fdec_frn_iu5_i1_isstore, + output [0:31] fdec_frn_iu5_i1_instr, + output [62-`EFF_IFAR_WIDTH:61] fdec_frn_iu5_i1_ifar, + output [62-`EFF_IFAR_WIDTH:61] fdec_frn_iu5_i1_bta, + output [0:3] fdec_frn_iu5_i1_ilat, + output fdec_frn_iu5_i1_t1_v, + output [0:2] fdec_frn_iu5_i1_t1_t, + output [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i1_t1_a, + output fdec_frn_iu5_i1_t2_v, + output [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i1_t2_a, + output [0:2] fdec_frn_iu5_i1_t2_t, + output fdec_frn_iu5_i1_t3_v, + output [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i1_t3_a, + output [0:2] fdec_frn_iu5_i1_t3_t, + output fdec_frn_iu5_i1_s1_v, + output [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i1_s1_a, + output [0:2] fdec_frn_iu5_i1_s1_t, + output fdec_frn_iu5_i1_s2_v, + output [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i1_s2_a, + output [0:2] fdec_frn_iu5_i1_s2_t, + output fdec_frn_iu5_i1_s3_v, + output [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i1_s3_a, + output [0:2] fdec_frn_iu5_i1_s3_t, + output fdec_frn_iu5_i1_br_pred, + output fdec_frn_iu5_i1_bh_update, + output [0:1] fdec_frn_iu5_i1_bh0_hist, + output [0:1] fdec_frn_iu5_i1_bh1_hist, + output [0:1] fdec_frn_iu5_i1_bh2_hist, + output [0:17] fdec_frn_iu5_i1_gshare, + output [0:2] fdec_frn_iu5_i1_ls_ptr, + output fdec_frn_iu5_i1_match, + output fdec_frn_iu5_i1_btb_entry, + output [0:1] fdec_frn_iu5_i1_btb_hist, + output fdec_frn_iu5_i1_bta_val, + + input frn_fdec_iu5_stall + ); + + //AXU Interface + wire au_iu_iu4_i0_i_dec_b; + wire [0:2] au_iu_iu4_i0_ucode; + wire au_iu_iu4_i0_t1_v; + wire [0:2] au_iu_iu4_i0_t1_t; + wire [0:`GPR_POOL_ENC-1] au_iu_iu4_i0_t1_a; + wire au_iu_iu4_i0_t2_v; + wire [0:`GPR_POOL_ENC-1] au_iu_iu4_i0_t2_a; + wire [0:2] au_iu_iu4_i0_t2_t; + wire au_iu_iu4_i0_t3_v; + wire [0:`GPR_POOL_ENC-1] au_iu_iu4_i0_t3_a; + wire [0:2] au_iu_iu4_i0_t3_t; + wire au_iu_iu4_i0_s1_v; + wire [0:`GPR_POOL_ENC-1] au_iu_iu4_i0_s1_a; + wire [0:2] au_iu_iu4_i0_s1_t; + wire au_iu_iu4_i0_s2_v; + wire [0:`GPR_POOL_ENC-1] au_iu_iu4_i0_s2_a; + wire [0:2] au_iu_iu4_i0_s2_t; + wire au_iu_iu4_i0_s3_v; + wire [0:`GPR_POOL_ENC-1] au_iu_iu4_i0_s3_a; + wire [0:2] au_iu_iu4_i0_s3_t; + wire [0:2] au_iu_iu4_i0_ilat; + wire au_iu_iu4_i0_ord; + wire au_iu_iu4_i0_cord; + wire au_iu_iu4_i0_spec; + wire au_iu_iu4_i0_type_fp; + wire au_iu_iu4_i0_type_ap; + wire au_iu_iu4_i0_type_spv; + wire au_iu_iu4_i0_type_st; + wire au_iu_iu4_i0_async_block; + wire au_iu_iu4_i0_isload; + wire au_iu_iu4_i0_isstore; + wire au_iu_iu4_i0_rte_lq; + wire au_iu_iu4_i0_rte_sq; + wire au_iu_iu4_i0_rte_axu0; + wire au_iu_iu4_i0_rte_axu1; + wire au_iu_iu4_i0_no_ram; + + wire au_iu_iu4_i1_i_dec_b; // decoded a valid FU instruction (inverted) 0509 + wire [0:2] au_iu_iu4_i1_ucode; + wire au_iu_iu4_i1_t1_v; + wire [0:2] au_iu_iu4_i1_t1_t; + wire [0:`GPR_POOL_ENC-1] au_iu_iu4_i1_t1_a; + wire au_iu_iu4_i1_t2_v; + wire [0:`GPR_POOL_ENC-1] au_iu_iu4_i1_t2_a; + wire [0:2] au_iu_iu4_i1_t2_t; + wire au_iu_iu4_i1_t3_v; + wire [0:`GPR_POOL_ENC-1] au_iu_iu4_i1_t3_a; + wire [0:2] au_iu_iu4_i1_t3_t; + wire au_iu_iu4_i1_s1_v; + wire [0:`GPR_POOL_ENC-1] au_iu_iu4_i1_s1_a; + wire [0:2] au_iu_iu4_i1_s1_t; + wire au_iu_iu4_i1_s2_v; + wire [0:`GPR_POOL_ENC-1] au_iu_iu4_i1_s2_a; + wire [0:2] au_iu_iu4_i1_s2_t; + wire au_iu_iu4_i1_s3_v; + wire [0:`GPR_POOL_ENC-1] au_iu_iu4_i1_s3_a; + wire [0:2] au_iu_iu4_i1_s3_t; + wire [0:2] au_iu_iu4_i1_ilat; + wire au_iu_iu4_i1_ord; + wire au_iu_iu4_i1_cord; + wire au_iu_iu4_i1_spec; + wire au_iu_iu4_i1_type_fp; + wire au_iu_iu4_i1_type_ap; + wire au_iu_iu4_i1_type_spv; + wire au_iu_iu4_i1_type_st; + wire au_iu_iu4_i1_async_block; + wire au_iu_iu4_i1_isload; + wire au_iu_iu4_i1_isstore; + wire au_iu_iu4_i1_rte_lq; + wire au_iu_iu4_i1_rte_sq; + wire au_iu_iu4_i1_rte_axu0; + wire au_iu_iu4_i1_rte_axu1; + wire au_iu_iu4_i1_no_ram; + + wire fdec_frn_iu5_i0_vld_int; + wire iu5_stall; + + assign iu5_stall = frn_fdec_iu5_stall & fdec_frn_iu5_i0_vld_int; + assign id_ib_iu4_stall = iu5_stall; + assign fdec_frn_iu5_i0_vld = fdec_frn_iu5_i0_vld_int; + + iuq_idec fx_dec0( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .pc_iu_sg_2(pc_iu_sg_2), + .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), + .clkoff_b(clkoff_b), + .act_dis(act_dis), + .tc_ac_ccflush_dc(tc_ac_ccflush_dc), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scan_in(scan_in[0]), + .scan_out(scan_out[0]), + + .xu_iu_epcr_dgtmi(xu_iu_epcr_dgtmi), + .xu_iu_msrp_uclep(xu_iu_msrp_uclep), + .xu_iu_msr_pr(xu_iu_msr_pr), + .xu_iu_msr_gs(xu_iu_msr_gs), + .xu_iu_msr_ucle(xu_iu_msr_ucle), + .xu_iu_ccr2_ucode_dis(xu_iu_ccr2_ucode_dis), + .mm_iu_tlbwe_binv(mm_iu_tlbwe_binv), + + .spr_dec_mask(spr_dec_mask), + .spr_dec_match(spr_dec_match), + + .cp_iu_iu4_flush(cp_iu_iu4_flush), + .uc_ib_iu3_flush_all(uc_ib_iu3_flush_all), + .br_iu_redirect(br_iu_redirect), + + .ib_id_iu4_valid(ib_id_iu4_0_valid), + .ib_id_iu4_ifar(ib_id_iu4_0_ifar), + .ib_id_iu4_bta(ib_id_iu4_0_bta), + .ib_id_iu4_instr(ib_id_iu4_0_instr), + .ib_id_iu4_ucode(ib_id_iu4_0_ucode), + .ib_id_iu4_ucode_ext(ib_id_iu4_0_ucode_ext), + .ib_id_iu4_isram(ib_id_iu4_0_isram), + .ib_id_iu4_fuse_data(ib_id_iu4_0_fuse_data), + .ib_id_iu4_fuse_val(ib_id_iu4_0_fuse_val), + + //AXU Interface + .au_iu_iu4_i_dec_b(au_iu_iu4_i0_i_dec_b), + .au_iu_iu4_ucode(au_iu_iu4_i0_ucode), + .au_iu_iu4_t1_v(au_iu_iu4_i0_t1_v), + .au_iu_iu4_t1_t(au_iu_iu4_i0_t1_t), + .au_iu_iu4_t1_a(au_iu_iu4_i0_t1_a), + .au_iu_iu4_t2_v(au_iu_iu4_i0_t2_v), + .au_iu_iu4_t2_a(au_iu_iu4_i0_t2_a), + .au_iu_iu4_t2_t(au_iu_iu4_i0_t2_t), + .au_iu_iu4_t3_v(au_iu_iu4_i0_t3_v), + .au_iu_iu4_t3_a(au_iu_iu4_i0_t3_a), + .au_iu_iu4_t3_t(au_iu_iu4_i0_t3_t), + .au_iu_iu4_s1_v(au_iu_iu4_i0_s1_v), + .au_iu_iu4_s1_a(au_iu_iu4_i0_s1_a), + .au_iu_iu4_s1_t(au_iu_iu4_i0_s1_t), + .au_iu_iu4_s2_v(au_iu_iu4_i0_s2_v), + .au_iu_iu4_s2_a(au_iu_iu4_i0_s2_a), + .au_iu_iu4_s2_t(au_iu_iu4_i0_s2_t), + .au_iu_iu4_s3_v(au_iu_iu4_i0_s3_v), + .au_iu_iu4_s3_a(au_iu_iu4_i0_s3_a), + .au_iu_iu4_s3_t(au_iu_iu4_i0_s3_t), + .au_iu_iu4_ilat(au_iu_iu4_i0_ilat), + .au_iu_iu4_ord(au_iu_iu4_i0_ord), + .au_iu_iu4_cord(au_iu_iu4_i0_cord), + .au_iu_iu4_spec(au_iu_iu4_i0_spec), + .au_iu_iu4_type_fp(au_iu_iu4_i0_type_fp), + .au_iu_iu4_type_ap(au_iu_iu4_i0_type_ap), + .au_iu_iu4_type_spv(au_iu_iu4_i0_type_spv), + .au_iu_iu4_type_st(au_iu_iu4_i0_type_st), + .au_iu_iu4_async_block(au_iu_iu4_i0_async_block), + .au_iu_iu4_isload(au_iu_iu4_i0_isload), + .au_iu_iu4_isstore(au_iu_iu4_i0_isstore), + .au_iu_iu4_rte_lq(au_iu_iu4_i0_rte_lq), + .au_iu_iu4_rte_sq(au_iu_iu4_i0_rte_sq), + .au_iu_iu4_rte_axu0(au_iu_iu4_i0_rte_axu0), + .au_iu_iu4_rte_axu1(au_iu_iu4_i0_rte_axu1), + .au_iu_iu4_no_ram(au_iu_iu4_i0_no_ram), + + // Decoded instruction to send to rename + .fdec_frn_iu5_ix_vld(fdec_frn_iu5_i0_vld_int), + .fdec_frn_iu5_ix_ucode(fdec_frn_iu5_i0_ucode), + .fdec_frn_iu5_ix_2ucode(fdec_frn_iu5_i0_2ucode), + .fdec_frn_iu5_ix_fuse_nop(fdec_frn_iu5_i0_fuse_nop), + .fdec_frn_iu5_ix_rte_lq(fdec_frn_iu5_i0_rte_lq), + .fdec_frn_iu5_ix_rte_sq(fdec_frn_iu5_i0_rte_sq), + .fdec_frn_iu5_ix_rte_fx0(fdec_frn_iu5_i0_rte_fx0), + .fdec_frn_iu5_ix_rte_fx1(fdec_frn_iu5_i0_rte_fx1), + .fdec_frn_iu5_ix_rte_axu0(fdec_frn_iu5_i0_rte_axu0), + .fdec_frn_iu5_ix_rte_axu1(fdec_frn_iu5_i0_rte_axu1), + .fdec_frn_iu5_ix_valop(fdec_frn_iu5_i0_valop), + .fdec_frn_iu5_ix_ord(fdec_frn_iu5_i0_ord), + .fdec_frn_iu5_ix_cord(fdec_frn_iu5_i0_cord), + .fdec_frn_iu5_ix_error(fdec_frn_iu5_i0_error), + .fdec_frn_iu5_ix_fusion(fdec_frn_iu5_i0_fusion), + .fdec_frn_iu5_ix_spec(fdec_frn_iu5_i0_spec), + .fdec_frn_iu5_ix_type_fp(fdec_frn_iu5_i0_type_fp), + .fdec_frn_iu5_ix_type_ap(fdec_frn_iu5_i0_type_ap), + .fdec_frn_iu5_ix_type_spv(fdec_frn_iu5_i0_type_spv), + .fdec_frn_iu5_ix_type_st(fdec_frn_iu5_i0_type_st), + .fdec_frn_iu5_ix_async_block(fdec_frn_iu5_i0_async_block), + .fdec_frn_iu5_ix_np1_flush(fdec_frn_iu5_i0_np1_flush), + .fdec_frn_iu5_ix_core_block(fdec_frn_iu5_i0_core_block), + .fdec_frn_iu5_ix_isram(fdec_frn_iu5_i0_isram), + .fdec_frn_iu5_ix_isload(fdec_frn_iu5_i0_isload), + .fdec_frn_iu5_ix_isstore(fdec_frn_iu5_i0_isstore), + .fdec_frn_iu5_ix_instr(fdec_frn_iu5_i0_instr), + .fdec_frn_iu5_ix_ifar(fdec_frn_iu5_i0_ifar), + .fdec_frn_iu5_ix_bta(fdec_frn_iu5_i0_bta), + .fdec_frn_iu5_ix_ilat(fdec_frn_iu5_i0_ilat), + .fdec_frn_iu5_ix_t1_v(fdec_frn_iu5_i0_t1_v), + .fdec_frn_iu5_ix_t1_t(fdec_frn_iu5_i0_t1_t), + .fdec_frn_iu5_ix_t1_a(fdec_frn_iu5_i0_t1_a), + .fdec_frn_iu5_ix_t2_v(fdec_frn_iu5_i0_t2_v), + .fdec_frn_iu5_ix_t2_a(fdec_frn_iu5_i0_t2_a), + .fdec_frn_iu5_ix_t2_t(fdec_frn_iu5_i0_t2_t), + .fdec_frn_iu5_ix_t3_v(fdec_frn_iu5_i0_t3_v), + .fdec_frn_iu5_ix_t3_a(fdec_frn_iu5_i0_t3_a), + .fdec_frn_iu5_ix_t3_t(fdec_frn_iu5_i0_t3_t), + .fdec_frn_iu5_ix_s1_v(fdec_frn_iu5_i0_s1_v), + .fdec_frn_iu5_ix_s1_a(fdec_frn_iu5_i0_s1_a), + .fdec_frn_iu5_ix_s1_t(fdec_frn_iu5_i0_s1_t), + .fdec_frn_iu5_ix_s2_v(fdec_frn_iu5_i0_s2_v), + .fdec_frn_iu5_ix_s2_a(fdec_frn_iu5_i0_s2_a), + .fdec_frn_iu5_ix_s2_t(fdec_frn_iu5_i0_s2_t), + .fdec_frn_iu5_ix_s3_v(fdec_frn_iu5_i0_s3_v), + .fdec_frn_iu5_ix_s3_a(fdec_frn_iu5_i0_s3_a), + .fdec_frn_iu5_ix_s3_t(fdec_frn_iu5_i0_s3_t), + .fdec_frn_iu5_ix_br_pred(fdec_frn_iu5_i0_br_pred), + .fdec_frn_iu5_ix_bh_update(fdec_frn_iu5_i0_bh_update), + .fdec_frn_iu5_ix_bh0_hist(fdec_frn_iu5_i0_bh0_hist), + .fdec_frn_iu5_ix_bh1_hist(fdec_frn_iu5_i0_bh1_hist), + .fdec_frn_iu5_ix_bh2_hist(fdec_frn_iu5_i0_bh2_hist), + .fdec_frn_iu5_ix_gshare(fdec_frn_iu5_i0_gshare), + .fdec_frn_iu5_ix_ls_ptr(fdec_frn_iu5_i0_ls_ptr), + .fdec_frn_iu5_ix_match(fdec_frn_iu5_i0_match), + .fdec_frn_iu5_ix_btb_entry(fdec_frn_iu5_i0_btb_entry), + .fdec_frn_iu5_ix_btb_hist(fdec_frn_iu5_i0_btb_hist), + .fdec_frn_iu5_ix_bta_val(fdec_frn_iu5_i0_bta_val), + + .frn_fdec_iu5_stall(iu5_stall) + ); + + iuq_idec fx_dec1( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .pc_iu_sg_2(pc_iu_sg_2), + .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), + .clkoff_b(clkoff_b), + .act_dis(act_dis), + .tc_ac_ccflush_dc(tc_ac_ccflush_dc), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scan_in(scan_in[1]), + .scan_out(scan_out[1]), + + .xu_iu_epcr_dgtmi(xu_iu_epcr_dgtmi), + .xu_iu_msrp_uclep(xu_iu_msrp_uclep), + .xu_iu_msr_pr(xu_iu_msr_pr), + .xu_iu_msr_gs(xu_iu_msr_gs), + .xu_iu_msr_ucle(xu_iu_msr_ucle), + .xu_iu_ccr2_ucode_dis(xu_iu_ccr2_ucode_dis), + .mm_iu_tlbwe_binv(mm_iu_tlbwe_binv), + + .spr_dec_mask(spr_dec_mask), + .spr_dec_match(spr_dec_match), + + .cp_iu_iu4_flush(cp_iu_iu4_flush), + .uc_ib_iu3_flush_all(uc_ib_iu3_flush_all), + .br_iu_redirect(br_iu_redirect), + + .ib_id_iu4_valid(ib_id_iu4_1_valid), + .ib_id_iu4_ifar(ib_id_iu4_1_ifar), + .ib_id_iu4_bta(ib_id_iu4_1_bta), + .ib_id_iu4_instr(ib_id_iu4_1_instr), + .ib_id_iu4_ucode(ib_id_iu4_1_ucode), + .ib_id_iu4_ucode_ext(ib_id_iu4_1_ucode_ext), + .ib_id_iu4_isram(ib_id_iu4_1_isram), + .ib_id_iu4_fuse_data(ib_id_iu4_1_fuse_data), + .ib_id_iu4_fuse_val(ib_id_iu4_1_fuse_val), + + //AXU Interface + .au_iu_iu4_i_dec_b(au_iu_iu4_i1_i_dec_b), + .au_iu_iu4_ucode(au_iu_iu4_i1_ucode), + .au_iu_iu4_t1_v(au_iu_iu4_i1_t1_v), + .au_iu_iu4_t1_t(au_iu_iu4_i1_t1_t), + .au_iu_iu4_t1_a(au_iu_iu4_i1_t1_a), + .au_iu_iu4_t2_v(au_iu_iu4_i1_t2_v), + .au_iu_iu4_t2_a(au_iu_iu4_i1_t2_a), + .au_iu_iu4_t2_t(au_iu_iu4_i1_t2_t), + .au_iu_iu4_t3_v(au_iu_iu4_i1_t3_v), + .au_iu_iu4_t3_a(au_iu_iu4_i1_t3_a), + .au_iu_iu4_t3_t(au_iu_iu4_i1_t3_t), + .au_iu_iu4_s1_v(au_iu_iu4_i1_s1_v), + .au_iu_iu4_s1_a(au_iu_iu4_i1_s1_a), + .au_iu_iu4_s1_t(au_iu_iu4_i1_s1_t), + .au_iu_iu4_s2_v(au_iu_iu4_i1_s2_v), + .au_iu_iu4_s2_a(au_iu_iu4_i1_s2_a), + .au_iu_iu4_s2_t(au_iu_iu4_i1_s2_t), + .au_iu_iu4_s3_v(au_iu_iu4_i1_s3_v), + .au_iu_iu4_s3_a(au_iu_iu4_i1_s3_a), + .au_iu_iu4_s3_t(au_iu_iu4_i1_s3_t), + .au_iu_iu4_ilat(au_iu_iu4_i1_ilat), + .au_iu_iu4_ord(au_iu_iu4_i1_ord), + .au_iu_iu4_cord(au_iu_iu4_i1_cord), + .au_iu_iu4_spec(au_iu_iu4_i1_spec), + .au_iu_iu4_type_fp(au_iu_iu4_i1_type_fp), + .au_iu_iu4_type_ap(au_iu_iu4_i1_type_ap), + .au_iu_iu4_type_spv(au_iu_iu4_i1_type_spv), + .au_iu_iu4_type_st(au_iu_iu4_i1_type_st), + .au_iu_iu4_async_block(au_iu_iu4_i1_async_block), + .au_iu_iu4_isload(au_iu_iu4_i1_isload), + .au_iu_iu4_isstore(au_iu_iu4_i1_isstore), + .au_iu_iu4_rte_lq(au_iu_iu4_i1_rte_lq), + .au_iu_iu4_rte_sq(au_iu_iu4_i1_rte_sq), + .au_iu_iu4_rte_axu0(au_iu_iu4_i1_rte_axu0), + .au_iu_iu4_rte_axu1(au_iu_iu4_i1_rte_axu1), + .au_iu_iu4_no_ram(au_iu_iu4_i1_no_ram), + + // Decoded instruction to send to rename + .fdec_frn_iu5_ix_vld(fdec_frn_iu5_i1_vld), + .fdec_frn_iu5_ix_ucode(fdec_frn_iu5_i1_ucode), + .fdec_frn_iu5_ix_2ucode(), + .fdec_frn_iu5_ix_fuse_nop(fdec_frn_iu5_i1_fuse_nop), + .fdec_frn_iu5_ix_rte_lq(fdec_frn_iu5_i1_rte_lq), + .fdec_frn_iu5_ix_rte_sq(fdec_frn_iu5_i1_rte_sq), + .fdec_frn_iu5_ix_rte_fx0(fdec_frn_iu5_i1_rte_fx0), + .fdec_frn_iu5_ix_rte_fx1(fdec_frn_iu5_i1_rte_fx1), + .fdec_frn_iu5_ix_rte_axu0(fdec_frn_iu5_i1_rte_axu0), + .fdec_frn_iu5_ix_rte_axu1(fdec_frn_iu5_i1_rte_axu1), + .fdec_frn_iu5_ix_valop(fdec_frn_iu5_i1_valop), + .fdec_frn_iu5_ix_ord(fdec_frn_iu5_i1_ord), + .fdec_frn_iu5_ix_cord(fdec_frn_iu5_i1_cord), + .fdec_frn_iu5_ix_error(fdec_frn_iu5_i1_error), + .fdec_frn_iu5_ix_fusion(fdec_frn_iu5_i1_fusion), + .fdec_frn_iu5_ix_spec(fdec_frn_iu5_i1_spec), + .fdec_frn_iu5_ix_type_fp(fdec_frn_iu5_i1_type_fp), + .fdec_frn_iu5_ix_type_ap(fdec_frn_iu5_i1_type_ap), + .fdec_frn_iu5_ix_type_spv(fdec_frn_iu5_i1_type_spv), + .fdec_frn_iu5_ix_type_st(fdec_frn_iu5_i1_type_st), + .fdec_frn_iu5_ix_async_block(fdec_frn_iu5_i1_async_block), + .fdec_frn_iu5_ix_np1_flush(fdec_frn_iu5_i1_np1_flush), + .fdec_frn_iu5_ix_core_block(fdec_frn_iu5_i1_core_block), + .fdec_frn_iu5_ix_isram(fdec_frn_iu5_i1_isram), + .fdec_frn_iu5_ix_isload(fdec_frn_iu5_i1_isload), + .fdec_frn_iu5_ix_isstore(fdec_frn_iu5_i1_isstore), + .fdec_frn_iu5_ix_instr(fdec_frn_iu5_i1_instr), + .fdec_frn_iu5_ix_ifar(fdec_frn_iu5_i1_ifar), + .fdec_frn_iu5_ix_bta(fdec_frn_iu5_i1_bta), + .fdec_frn_iu5_ix_ilat(fdec_frn_iu5_i1_ilat), + .fdec_frn_iu5_ix_t1_v(fdec_frn_iu5_i1_t1_v), + .fdec_frn_iu5_ix_t1_t(fdec_frn_iu5_i1_t1_t), + .fdec_frn_iu5_ix_t1_a(fdec_frn_iu5_i1_t1_a), + .fdec_frn_iu5_ix_t2_v(fdec_frn_iu5_i1_t2_v), + .fdec_frn_iu5_ix_t2_a(fdec_frn_iu5_i1_t2_a), + .fdec_frn_iu5_ix_t2_t(fdec_frn_iu5_i1_t2_t), + .fdec_frn_iu5_ix_t3_v(fdec_frn_iu5_i1_t3_v), + .fdec_frn_iu5_ix_t3_a(fdec_frn_iu5_i1_t3_a), + .fdec_frn_iu5_ix_t3_t(fdec_frn_iu5_i1_t3_t), + .fdec_frn_iu5_ix_s1_v(fdec_frn_iu5_i1_s1_v), + .fdec_frn_iu5_ix_s1_a(fdec_frn_iu5_i1_s1_a), + .fdec_frn_iu5_ix_s1_t(fdec_frn_iu5_i1_s1_t), + .fdec_frn_iu5_ix_s2_v(fdec_frn_iu5_i1_s2_v), + .fdec_frn_iu5_ix_s2_a(fdec_frn_iu5_i1_s2_a), + .fdec_frn_iu5_ix_s2_t(fdec_frn_iu5_i1_s2_t), + .fdec_frn_iu5_ix_s3_v(fdec_frn_iu5_i1_s3_v), + .fdec_frn_iu5_ix_s3_a(fdec_frn_iu5_i1_s3_a), + .fdec_frn_iu5_ix_s3_t(fdec_frn_iu5_i1_s3_t), + .fdec_frn_iu5_ix_br_pred(fdec_frn_iu5_i1_br_pred), + .fdec_frn_iu5_ix_bh_update(fdec_frn_iu5_i1_bh_update), + .fdec_frn_iu5_ix_bh0_hist(fdec_frn_iu5_i1_bh0_hist), + .fdec_frn_iu5_ix_bh1_hist(fdec_frn_iu5_i1_bh1_hist), + .fdec_frn_iu5_ix_bh2_hist(fdec_frn_iu5_i1_bh2_hist), + .fdec_frn_iu5_ix_gshare(fdec_frn_iu5_i1_gshare), + .fdec_frn_iu5_ix_ls_ptr(fdec_frn_iu5_i1_ls_ptr), + .fdec_frn_iu5_ix_match(fdec_frn_iu5_i1_match), + .fdec_frn_iu5_ix_btb_entry(fdec_frn_iu5_i1_btb_entry), + .fdec_frn_iu5_ix_btb_hist(fdec_frn_iu5_i1_btb_hist), + .fdec_frn_iu5_ix_bta_val(fdec_frn_iu5_i1_bta_val), + + .frn_fdec_iu5_stall(iu5_stall) + ); + + iuq_axu_fu_dec axu_dec0( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .i_dec_si(scan_in[2]), + .i_dec_so(scan_out[2]), + .pc_iu_sg_2(pc_iu_sg_2), + .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), + .clkoff_b(clkoff_b), + .act_dis(act_dis), + .tc_ac_ccflush_dc(tc_ac_ccflush_dc), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + + .iu_au_iu4_isram(ib_id_iu4_0_isram), + .iu_au_ucode_restart(1'b0), + .iu_au_config_iucr(iu_au_config_iucr), + .iu_au_iu4_instr_v(ib_id_iu4_0_valid), + .iu_au_iu4_instr(ib_id_iu4_0_instr[0:31]), + .iu_au_iu4_ucode_ext(ib_id_iu4_0_ucode_ext), + .iu_au_iu4_ucode(ib_id_iu4_0_ucode), + .iu_au_iu4_2ucode(1'b0), + .au_iu_iu4_i_dec_b(au_iu_iu4_i0_i_dec_b), + .au_iu_iu4_ucode(au_iu_iu4_i0_ucode), + .au_iu_iu4_t1_v(au_iu_iu4_i0_t1_v), + .au_iu_iu4_t1_t(au_iu_iu4_i0_t1_t), + .au_iu_iu4_t1_a(au_iu_iu4_i0_t1_a), + .au_iu_iu4_t2_v(au_iu_iu4_i0_t2_v), + .au_iu_iu4_t2_a(au_iu_iu4_i0_t2_a), + .au_iu_iu4_t2_t(au_iu_iu4_i0_t2_t), + .au_iu_iu4_t3_v(au_iu_iu4_i0_t3_v), + .au_iu_iu4_t3_a(au_iu_iu4_i0_t3_a), + .au_iu_iu4_t3_t(au_iu_iu4_i0_t3_t), + .au_iu_iu4_s1_v(au_iu_iu4_i0_s1_v), + .au_iu_iu4_s1_a(au_iu_iu4_i0_s1_a), + .au_iu_iu4_s1_t(au_iu_iu4_i0_s1_t), + .au_iu_iu4_s2_v(au_iu_iu4_i0_s2_v), + .au_iu_iu4_s2_a(au_iu_iu4_i0_s2_a), + .au_iu_iu4_s2_t(au_iu_iu4_i0_s2_t), + .au_iu_iu4_s3_v(au_iu_iu4_i0_s3_v), + .au_iu_iu4_s3_a(au_iu_iu4_i0_s3_a), + .au_iu_iu4_s3_t(au_iu_iu4_i0_s3_t), + .au_iu_iu4_ilat(au_iu_iu4_i0_ilat), + .au_iu_iu4_ord(au_iu_iu4_i0_ord), + .au_iu_iu4_cord(au_iu_iu4_i0_cord), + .au_iu_iu4_spec(au_iu_iu4_i0_spec), + .au_iu_iu4_type_fp(au_iu_iu4_i0_type_fp), + .au_iu_iu4_type_ap(au_iu_iu4_i0_type_ap), + .au_iu_iu4_type_spv(au_iu_iu4_i0_type_spv), + .au_iu_iu4_type_st(au_iu_iu4_i0_type_st), + .au_iu_iu4_async_block(au_iu_iu4_i0_async_block), + .au_iu_iu4_isload(au_iu_iu4_i0_isload), + .au_iu_iu4_isstore(au_iu_iu4_i0_isstore), + .au_iu_iu4_rte_lq(au_iu_iu4_i0_rte_lq), + .au_iu_iu4_rte_sq(au_iu_iu4_i0_rte_sq), + .au_iu_iu4_rte_axu0(au_iu_iu4_i0_rte_axu0), + .au_iu_iu4_rte_axu1(au_iu_iu4_i0_rte_axu1), + .au_iu_iu4_no_ram(au_iu_iu4_i0_no_ram) + ); + + iuq_axu_fu_dec axu_dec1( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .i_dec_si(scan_in[3]), + .i_dec_so(scan_out[3]), + .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), + .pc_iu_sg_2(pc_iu_sg_2), + .clkoff_b(clkoff_b), + .act_dis(act_dis), + .tc_ac_ccflush_dc(tc_ac_ccflush_dc), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + + .iu_au_iu4_isram(ib_id_iu4_1_isram), + .iu_au_ucode_restart(1'b0), + .iu_au_config_iucr(iu_au_config_iucr), + .iu_au_iu4_instr_v(ib_id_iu4_1_valid), + .iu_au_iu4_instr(ib_id_iu4_1_instr[0:31]), + .iu_au_iu4_ucode_ext(ib_id_iu4_1_ucode_ext), + .iu_au_iu4_ucode(ib_id_iu4_1_ucode), + .iu_au_iu4_2ucode(1'b0), + .au_iu_iu4_i_dec_b(au_iu_iu4_i1_i_dec_b), + .au_iu_iu4_ucode(au_iu_iu4_i1_ucode), + .au_iu_iu4_t1_v(au_iu_iu4_i1_t1_v), + .au_iu_iu4_t1_t(au_iu_iu4_i1_t1_t), + .au_iu_iu4_t1_a(au_iu_iu4_i1_t1_a), + .au_iu_iu4_t2_v(au_iu_iu4_i1_t2_v), + .au_iu_iu4_t2_a(au_iu_iu4_i1_t2_a), + .au_iu_iu4_t2_t(au_iu_iu4_i1_t2_t), + .au_iu_iu4_t3_v(au_iu_iu4_i1_t3_v), + .au_iu_iu4_t3_a(au_iu_iu4_i1_t3_a), + .au_iu_iu4_t3_t(au_iu_iu4_i1_t3_t), + .au_iu_iu4_s1_v(au_iu_iu4_i1_s1_v), + .au_iu_iu4_s1_a(au_iu_iu4_i1_s1_a), + .au_iu_iu4_s1_t(au_iu_iu4_i1_s1_t), + .au_iu_iu4_s2_v(au_iu_iu4_i1_s2_v), + .au_iu_iu4_s2_a(au_iu_iu4_i1_s2_a), + .au_iu_iu4_s2_t(au_iu_iu4_i1_s2_t), + .au_iu_iu4_s3_v(au_iu_iu4_i1_s3_v), + .au_iu_iu4_s3_a(au_iu_iu4_i1_s3_a), + .au_iu_iu4_s3_t(au_iu_iu4_i1_s3_t), + .au_iu_iu4_ilat(au_iu_iu4_i1_ilat), + .au_iu_iu4_ord(au_iu_iu4_i1_ord), + .au_iu_iu4_cord(au_iu_iu4_i1_cord), + .au_iu_iu4_spec(au_iu_iu4_i1_spec), + .au_iu_iu4_type_fp(au_iu_iu4_i1_type_fp), + .au_iu_iu4_type_ap(au_iu_iu4_i1_type_ap), + .au_iu_iu4_type_spv(au_iu_iu4_i1_type_spv), + .au_iu_iu4_type_st(au_iu_iu4_i1_type_st), + .au_iu_iu4_async_block(au_iu_iu4_i1_async_block), + .au_iu_iu4_isload(au_iu_iu4_i1_isload), + .au_iu_iu4_isstore(au_iu_iu4_i1_isstore), + .au_iu_iu4_rte_lq(au_iu_iu4_i1_rte_lq), + .au_iu_iu4_rte_sq(au_iu_iu4_i1_rte_sq), + .au_iu_iu4_rte_axu0(au_iu_iu4_i1_rte_axu0), + .au_iu_iu4_rte_axu1(au_iu_iu4_i1_rte_axu1), + .au_iu_iu4_no_ram(au_iu_iu4_i1_no_ram) + ); + +endmodule diff --git a/dev/verilog/work/iuq_dispatch.v b/dev/verilog/work/iuq_dispatch.v new file mode 100755 index 0000000..acbc45b --- /dev/null +++ b/dev/verilog/work/iuq_dispatch.v @@ -0,0 +1,4120 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//******************************************************************** +//* +//* TITLE: +//* +//* NAME: iuq_dispatch.vhdl +//* + +`include "tri_a2o.vh" + +module iuq_dispatch( + inout vdd, + inout gnd, + input [0:`NCLK_WIDTH-1] nclk, + input pc_iu_sg_2, + input pc_iu_func_sl_thold_2, + input pc_iu_func_slp_sl_thold_2, + input clkoff_b, + input act_dis, + input tc_ac_ccflush_dc, + input d_mode, + input delay_lclkr, + input mpw1_b, + input mpw2_b, + input scan_in, + output scan_out, + + //----------------------------- + // SPR connections + //----------------------------- + input [0:`THREADS-1] spr_cpcr_we, + input [0:4] spr_t0_cpcr2_fx0_cnt, + input [0:4] spr_t0_cpcr2_fx1_cnt, + input [0:4] spr_t0_cpcr2_lq_cnt, + input [0:4] spr_t0_cpcr2_sq_cnt, + input [0:4] spr_t0_cpcr3_fu0_cnt, + input [0:4] spr_t0_cpcr3_fu1_cnt, + input [0:4] spr_t0_cpcr4_fx0_cnt, + input [0:4] spr_t0_cpcr4_fx1_cnt, + input [0:4] spr_t0_cpcr4_lq_cnt, + input [0:4] spr_t0_cpcr4_sq_cnt, + input [0:4] spr_t0_cpcr5_fu0_cnt, + input [0:4] spr_t0_cpcr5_fu1_cnt, +`ifndef THREADS1 + input [0:4] spr_t1_cpcr2_fx0_cnt, + input [0:4] spr_t1_cpcr2_fx1_cnt, + input [0:4] spr_t1_cpcr2_lq_cnt, + input [0:4] spr_t1_cpcr2_sq_cnt, + input [0:4] spr_t1_cpcr3_fu0_cnt, + input [0:4] spr_t1_cpcr3_fu1_cnt, + input [0:4] spr_t1_cpcr4_fx0_cnt, + input [0:4] spr_t1_cpcr4_fx1_cnt, + input [0:4] spr_t1_cpcr4_lq_cnt, + input [0:4] spr_t1_cpcr4_sq_cnt, + input [0:4] spr_t1_cpcr5_fu0_cnt, + input [0:4] spr_t1_cpcr5_fu1_cnt, +`endif + input [0:4] spr_cpcr0_fx0_cnt, + input [0:4] spr_cpcr0_fx1_cnt, + input [0:4] spr_cpcr0_lq_cnt, + input [0:4] spr_cpcr0_sq_cnt, + input [0:4] spr_cpcr1_fu0_cnt, + input [0:4] spr_cpcr1_fu1_cnt, + + input [0:`THREADS-1] spr_high_pri_mask, + input [0:`THREADS-1] spr_med_pri_mask, + input [0:5] spr_t0_low_pri_count, +`ifndef THREADS1 + input [0:5] spr_t1_low_pri_count, +`endif + + //------------------------------- + // Performance interface with I$ + //------------------------------- + input pc_iu_event_bus_enable, + output [0:`THREADS-1] perf_iu6_stall, + output [0:`THREADS-1] perf_iu6_dispatch_fx0, + output [0:`THREADS-1] perf_iu6_dispatch_fx1, + output [0:`THREADS-1] perf_iu6_dispatch_lq, + output [0:`THREADS-1] perf_iu6_dispatch_axu0, + output [0:`THREADS-1] perf_iu6_dispatch_axu1, + output [0:`THREADS-1] perf_iu6_fx0_credit_stall, + output [0:`THREADS-1] perf_iu6_fx1_credit_stall, + output [0:`THREADS-1] perf_iu6_lq_credit_stall, + output [0:`THREADS-1] perf_iu6_sq_credit_stall, + output [0:`THREADS-1] perf_iu6_axu0_credit_stall, + output [0:`THREADS-1] perf_iu6_axu1_credit_stall, + + + //---------------------------- + // SCOM signals + //---------------------------- + output [0:`THREADS-1] iu_pc_fx0_credit_ok, + output [0:`THREADS-1] iu_pc_fx1_credit_ok, + output [0:`THREADS-1] iu_pc_axu0_credit_ok, + output [0:`THREADS-1] iu_pc_axu1_credit_ok, + output [0:`THREADS-1] iu_pc_lq_credit_ok, + output [0:`THREADS-1] iu_pc_sq_credit_ok, + + + //---------------------------- + // Credit Interface with IU + //---------------------------- + input [0:`THREADS-1] rv_iu_fx0_credit_free, + input [0:`THREADS-1] rv_iu_fx1_credit_free, // Need to add 2nd unit someday + input [0:`THREADS-1] lq_iu_credit_free, + input [0:`THREADS-1] sq_iu_credit_free, + input [0:`THREADS-1] axu0_iu_credit_free, // credit free from axu reservation station + input [0:`THREADS-1] axu1_iu_credit_free, // credit free from axu reservation station + + input [0:`THREADS-1] cp_flush, + input [0:`THREADS-1] xu_iu_run_thread, + output iu_xu_credits_returned, + + //---------------------------------------------------------------- + // Interface with rename + //---------------------------------------------------------------- + input frn_fdis_iu6_t0_i0_vld, + input [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_t0_i0_itag, + input [0:2] frn_fdis_iu6_t0_i0_ucode, + input [0:`UCODE_ENTRIES_ENC-1] frn_fdis_iu6_t0_i0_ucode_cnt, + input frn_fdis_iu6_t0_i0_2ucode, + input frn_fdis_iu6_t0_i0_fuse_nop, + input frn_fdis_iu6_t0_i0_rte_lq, + input frn_fdis_iu6_t0_i0_rte_sq, + input frn_fdis_iu6_t0_i0_rte_fx0, + input frn_fdis_iu6_t0_i0_rte_fx1, + input frn_fdis_iu6_t0_i0_rte_axu0, + input frn_fdis_iu6_t0_i0_rte_axu1, + input frn_fdis_iu6_t0_i0_valop, + input frn_fdis_iu6_t0_i0_ord, + input frn_fdis_iu6_t0_i0_cord, + input [0:2] frn_fdis_iu6_t0_i0_error, + input frn_fdis_iu6_t0_i0_btb_entry, + input [0:1] frn_fdis_iu6_t0_i0_btb_hist, + input frn_fdis_iu6_t0_i0_bta_val, + input [0:19] frn_fdis_iu6_t0_i0_fusion, + input frn_fdis_iu6_t0_i0_spec, + input frn_fdis_iu6_t0_i0_type_fp, + input frn_fdis_iu6_t0_i0_type_ap, + input frn_fdis_iu6_t0_i0_type_spv, + input frn_fdis_iu6_t0_i0_type_st, + input frn_fdis_iu6_t0_i0_async_block, + input frn_fdis_iu6_t0_i0_np1_flush, + input frn_fdis_iu6_t0_i0_core_block, + input frn_fdis_iu6_t0_i0_isram, + input frn_fdis_iu6_t0_i0_isload, + input frn_fdis_iu6_t0_i0_isstore, + input [0:31] frn_fdis_iu6_t0_i0_instr, + input [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_t0_i0_ifar, + input [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_t0_i0_bta, + input frn_fdis_iu6_t0_i0_br_pred, + input frn_fdis_iu6_t0_i0_bh_update, + input [0:1] frn_fdis_iu6_t0_i0_bh0_hist, + input [0:1] frn_fdis_iu6_t0_i0_bh1_hist, + input [0:1] frn_fdis_iu6_t0_i0_bh2_hist, + input [0:17] frn_fdis_iu6_t0_i0_gshare, + input [0:2] frn_fdis_iu6_t0_i0_ls_ptr, + input frn_fdis_iu6_t0_i0_match, + input [0:3] frn_fdis_iu6_t0_i0_ilat, + input frn_fdis_iu6_t0_i0_t1_v, + input [0:2] frn_fdis_iu6_t0_i0_t1_t, + input [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t0_i0_t1_a, + input [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t0_i0_t1_p, + input frn_fdis_iu6_t0_i0_t2_v, + input [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t0_i0_t2_a, + input [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t0_i0_t2_p, + input [0:2] frn_fdis_iu6_t0_i0_t2_t, + input frn_fdis_iu6_t0_i0_t3_v, + input [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t0_i0_t3_a, + input [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t0_i0_t3_p, + input [0:2] frn_fdis_iu6_t0_i0_t3_t, + input frn_fdis_iu6_t0_i0_s1_v, + input [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t0_i0_s1_a, + input [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t0_i0_s1_p, + input [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_t0_i0_s1_itag, + input [0:2] frn_fdis_iu6_t0_i0_s1_t, + input frn_fdis_iu6_t0_i0_s2_v, + input [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t0_i0_s2_a, + input [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t0_i0_s2_p, + input [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_t0_i0_s2_itag, + input [0:2] frn_fdis_iu6_t0_i0_s2_t, + input frn_fdis_iu6_t0_i0_s3_v, + input [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t0_i0_s3_a, + input [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t0_i0_s3_p, + input [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_t0_i0_s3_itag, + input [0:2] frn_fdis_iu6_t0_i0_s3_t, + + input frn_fdis_iu6_t0_i1_vld, + input [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_t0_i1_itag, + input [0:2] frn_fdis_iu6_t0_i1_ucode, + input [0:`UCODE_ENTRIES_ENC-1] frn_fdis_iu6_t0_i1_ucode_cnt, + input frn_fdis_iu6_t0_i1_fuse_nop, + input frn_fdis_iu6_t0_i1_rte_lq, + input frn_fdis_iu6_t0_i1_rte_sq, + input frn_fdis_iu6_t0_i1_rte_fx0, + input frn_fdis_iu6_t0_i1_rte_fx1, + input frn_fdis_iu6_t0_i1_rte_axu0, + input frn_fdis_iu6_t0_i1_rte_axu1, + input frn_fdis_iu6_t0_i1_valop, + input frn_fdis_iu6_t0_i1_ord, + input frn_fdis_iu6_t0_i1_cord, + input [0:2] frn_fdis_iu6_t0_i1_error, + input frn_fdis_iu6_t0_i1_btb_entry, + input [0:1] frn_fdis_iu6_t0_i1_btb_hist, + input frn_fdis_iu6_t0_i1_bta_val, + input [0:19] frn_fdis_iu6_t0_i1_fusion, + input frn_fdis_iu6_t0_i1_spec, + input frn_fdis_iu6_t0_i1_type_fp, + input frn_fdis_iu6_t0_i1_type_ap, + input frn_fdis_iu6_t0_i1_type_spv, + input frn_fdis_iu6_t0_i1_type_st, + input frn_fdis_iu6_t0_i1_async_block, + input frn_fdis_iu6_t0_i1_np1_flush, + input frn_fdis_iu6_t0_i1_core_block, + input frn_fdis_iu6_t0_i1_isram, + input frn_fdis_iu6_t0_i1_isload, + input frn_fdis_iu6_t0_i1_isstore, + input [0:31] frn_fdis_iu6_t0_i1_instr, + input [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_t0_i1_ifar, + input [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_t0_i1_bta, + input frn_fdis_iu6_t0_i1_br_pred, + input frn_fdis_iu6_t0_i1_bh_update, + input [0:1] frn_fdis_iu6_t0_i1_bh0_hist, + input [0:1] frn_fdis_iu6_t0_i1_bh1_hist, + input [0:1] frn_fdis_iu6_t0_i1_bh2_hist, + input [0:17] frn_fdis_iu6_t0_i1_gshare, + input [0:2] frn_fdis_iu6_t0_i1_ls_ptr, + input frn_fdis_iu6_t0_i1_match, + input [0:3] frn_fdis_iu6_t0_i1_ilat, + input frn_fdis_iu6_t0_i1_t1_v, + input [0:2] frn_fdis_iu6_t0_i1_t1_t, + input [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t0_i1_t1_a, + input [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t0_i1_t1_p, + input frn_fdis_iu6_t0_i1_t2_v, + input [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t0_i1_t2_a, + input [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t0_i1_t2_p, + input [0:2] frn_fdis_iu6_t0_i1_t2_t, + input frn_fdis_iu6_t0_i1_t3_v, + input [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t0_i1_t3_a, + input [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t0_i1_t3_p, + input [0:2] frn_fdis_iu6_t0_i1_t3_t, + input frn_fdis_iu6_t0_i1_s1_v, + input [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t0_i1_s1_a, + input [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t0_i1_s1_p, + input [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_t0_i1_s1_itag, + input [0:2] frn_fdis_iu6_t0_i1_s1_t, + input frn_fdis_iu6_t0_i1_s1_dep_hit, + input frn_fdis_iu6_t0_i1_s2_v, + input [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t0_i1_s2_a, + input [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t0_i1_s2_p, + input [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_t0_i1_s2_itag, + input [0:2] frn_fdis_iu6_t0_i1_s2_t, + input frn_fdis_iu6_t0_i1_s2_dep_hit, + input frn_fdis_iu6_t0_i1_s3_v, + input [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t0_i1_s3_a, + input [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t0_i1_s3_p, + input [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_t0_i1_s3_itag, + input [0:2] frn_fdis_iu6_t0_i1_s3_t, + input frn_fdis_iu6_t0_i1_s3_dep_hit, + +`ifndef THREADS1 + //---------------------------------------------------------------- + // Interface with rename + //---------------------------------------------------------------- + input frn_fdis_iu6_t1_i0_vld, + input [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_t1_i0_itag, + input [0:2] frn_fdis_iu6_t1_i0_ucode, + input [0:`UCODE_ENTRIES_ENC-1] frn_fdis_iu6_t1_i0_ucode_cnt, + input frn_fdis_iu6_t1_i0_2ucode, + input frn_fdis_iu6_t1_i0_fuse_nop, + input frn_fdis_iu6_t1_i0_rte_lq, + input frn_fdis_iu6_t1_i0_rte_sq, + input frn_fdis_iu6_t1_i0_rte_fx0, + input frn_fdis_iu6_t1_i0_rte_fx1, + input frn_fdis_iu6_t1_i0_rte_axu0, + input frn_fdis_iu6_t1_i0_rte_axu1, + input frn_fdis_iu6_t1_i0_valop, + input frn_fdis_iu6_t1_i0_ord, + input frn_fdis_iu6_t1_i0_cord, + input [0:2] frn_fdis_iu6_t1_i0_error, + input frn_fdis_iu6_t1_i0_btb_entry, + input [0:1] frn_fdis_iu6_t1_i0_btb_hist, + input frn_fdis_iu6_t1_i0_bta_val, + input [0:19] frn_fdis_iu6_t1_i0_fusion, + input frn_fdis_iu6_t1_i0_spec, + input frn_fdis_iu6_t1_i0_type_fp, + input frn_fdis_iu6_t1_i0_type_ap, + input frn_fdis_iu6_t1_i0_type_spv, + input frn_fdis_iu6_t1_i0_type_st, + input frn_fdis_iu6_t1_i0_async_block, + input frn_fdis_iu6_t1_i0_np1_flush, + input frn_fdis_iu6_t1_i0_core_block, + input frn_fdis_iu6_t1_i0_isram, + input frn_fdis_iu6_t1_i0_isload, + input frn_fdis_iu6_t1_i0_isstore, + input [0:31] frn_fdis_iu6_t1_i0_instr, + input [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_t1_i0_ifar, + input [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_t1_i0_bta, + input frn_fdis_iu6_t1_i0_br_pred, + input frn_fdis_iu6_t1_i0_bh_update, + input [0:1] frn_fdis_iu6_t1_i0_bh0_hist, + input [0:1] frn_fdis_iu6_t1_i0_bh1_hist, + input [0:1] frn_fdis_iu6_t1_i0_bh2_hist, + input [0:17] frn_fdis_iu6_t1_i0_gshare, + input [0:2] frn_fdis_iu6_t1_i0_ls_ptr, + input frn_fdis_iu6_t1_i0_match, + input [0:3] frn_fdis_iu6_t1_i0_ilat, + input frn_fdis_iu6_t1_i0_t1_v, + input [0:2] frn_fdis_iu6_t1_i0_t1_t, + input [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t1_i0_t1_a, + input [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t1_i0_t1_p, + input frn_fdis_iu6_t1_i0_t2_v, + input [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t1_i0_t2_a, + input [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t1_i0_t2_p, + input [0:2] frn_fdis_iu6_t1_i0_t2_t, + input frn_fdis_iu6_t1_i0_t3_v, + input [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t1_i0_t3_a, + input [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t1_i0_t3_p, + input [0:2] frn_fdis_iu6_t1_i0_t3_t, + input frn_fdis_iu6_t1_i0_s1_v, + input [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t1_i0_s1_a, + input [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t1_i0_s1_p, + input [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_t1_i0_s1_itag, + input [0:2] frn_fdis_iu6_t1_i0_s1_t, + input frn_fdis_iu6_t1_i0_s2_v, + input [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t1_i0_s2_a, + input [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t1_i0_s2_p, + input [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_t1_i0_s2_itag, + input [0:2] frn_fdis_iu6_t1_i0_s2_t, + input frn_fdis_iu6_t1_i0_s3_v, + input [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t1_i0_s3_a, + input [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t1_i0_s3_p, + input [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_t1_i0_s3_itag, + input [0:2] frn_fdis_iu6_t1_i0_s3_t, + + input frn_fdis_iu6_t1_i1_vld, + input [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_t1_i1_itag, + input [0:2] frn_fdis_iu6_t1_i1_ucode, + input [0:`UCODE_ENTRIES_ENC-1] frn_fdis_iu6_t1_i1_ucode_cnt, + input frn_fdis_iu6_t1_i1_fuse_nop, + input frn_fdis_iu6_t1_i1_rte_lq, + input frn_fdis_iu6_t1_i1_rte_sq, + input frn_fdis_iu6_t1_i1_rte_fx0, + input frn_fdis_iu6_t1_i1_rte_fx1, + input frn_fdis_iu6_t1_i1_rte_axu0, + input frn_fdis_iu6_t1_i1_rte_axu1, + input frn_fdis_iu6_t1_i1_valop, + input frn_fdis_iu6_t1_i1_ord, + input frn_fdis_iu6_t1_i1_cord, + input [0:2] frn_fdis_iu6_t1_i1_error, + input frn_fdis_iu6_t1_i1_btb_entry, + input [0:1] frn_fdis_iu6_t1_i1_btb_hist, + input frn_fdis_iu6_t1_i1_bta_val, + input [0:19] frn_fdis_iu6_t1_i1_fusion, + input frn_fdis_iu6_t1_i1_spec, + input frn_fdis_iu6_t1_i1_type_fp, + input frn_fdis_iu6_t1_i1_type_ap, + input frn_fdis_iu6_t1_i1_type_spv, + input frn_fdis_iu6_t1_i1_type_st, + input frn_fdis_iu6_t1_i1_async_block, + input frn_fdis_iu6_t1_i1_np1_flush, + input frn_fdis_iu6_t1_i1_core_block, + input frn_fdis_iu6_t1_i1_isram, + input frn_fdis_iu6_t1_i1_isload, + input frn_fdis_iu6_t1_i1_isstore, + input [0:31] frn_fdis_iu6_t1_i1_instr, + input [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_t1_i1_ifar, + input [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_t1_i1_bta, + input frn_fdis_iu6_t1_i1_br_pred, + input frn_fdis_iu6_t1_i1_bh_update, + input [0:1] frn_fdis_iu6_t1_i1_bh0_hist, + input [0:1] frn_fdis_iu6_t1_i1_bh1_hist, + input [0:1] frn_fdis_iu6_t1_i1_bh2_hist, + input [0:17] frn_fdis_iu6_t1_i1_gshare, + input [0:2] frn_fdis_iu6_t1_i1_ls_ptr, + input frn_fdis_iu6_t1_i1_match, + input [0:3] frn_fdis_iu6_t1_i1_ilat, + input frn_fdis_iu6_t1_i1_t1_v, + input [0:2] frn_fdis_iu6_t1_i1_t1_t, + input [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t1_i1_t1_a, + input [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t1_i1_t1_p, + input frn_fdis_iu6_t1_i1_t2_v, + input [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t1_i1_t2_a, + input [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t1_i1_t2_p, + input [0:2] frn_fdis_iu6_t1_i1_t2_t, + input frn_fdis_iu6_t1_i1_t3_v, + input [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t1_i1_t3_a, + input [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t1_i1_t3_p, + input [0:2] frn_fdis_iu6_t1_i1_t3_t, + input frn_fdis_iu6_t1_i1_s1_v, + input [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t1_i1_s1_a, + input [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t1_i1_s1_p, + input [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_t1_i1_s1_itag, + input [0:2] frn_fdis_iu6_t1_i1_s1_t, + input frn_fdis_iu6_t1_i1_s1_dep_hit, + input frn_fdis_iu6_t1_i1_s2_v, + input [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t1_i1_s2_a, + input [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t1_i1_s2_p, + input [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_t1_i1_s2_itag, + input [0:2] frn_fdis_iu6_t1_i1_s2_t, + input frn_fdis_iu6_t1_i1_s2_dep_hit, + input frn_fdis_iu6_t1_i1_s3_v, + input [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t1_i1_s3_a, + input [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t1_i1_s3_p, + input [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_t1_i1_s3_itag, + input [0:2] frn_fdis_iu6_t1_i1_s3_t, + input frn_fdis_iu6_t1_i1_s3_dep_hit, +`endif + + // Input to dispatch to block due to ivax + input [0:`THREADS-1] cp_dis_ivax, + + //----------------------------- + // Stall from MMU + //----------------------------- + input [0:`THREADS-1] mm_iu_flush_req, + output [0:`THREADS-1] dp_cp_hold_req, + input [0:`THREADS-1] mm_iu_hold_done, + input [0:`THREADS-1] mm_iu_bus_snoop_hold_req, + output [0:`THREADS-1] dp_cp_bus_snoop_hold_req, + input [0:`THREADS-1] mm_iu_bus_snoop_hold_done, + input [0:`THREADS-1] mm_iu_tlbi_complete, + + //----------------------------- + // Stall from dispatch + //----------------------------- + output [0:`THREADS-1] fdis_frn_iu6_stall, + + //---------------------------------------------------------------- + // Interface to reservation station - Completion is snooping also + //---------------------------------------------------------------- + output iu_rv_iu6_t0_i0_vld, + output iu_rv_iu6_t0_i0_act, + output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i0_itag, + output [0:2] iu_rv_iu6_t0_i0_ucode, + output [0:`UCODE_ENTRIES_ENC-1] iu_rv_iu6_t0_i0_ucode_cnt, + output iu_rv_iu6_t0_i0_2ucode, + output iu_rv_iu6_t0_i0_fuse_nop, + output iu_rv_iu6_t0_i0_rte_lq, + output iu_rv_iu6_t0_i0_rte_sq, + output iu_rv_iu6_t0_i0_rte_fx0, + output iu_rv_iu6_t0_i0_rte_fx1, + output iu_rv_iu6_t0_i0_rte_axu0, + output iu_rv_iu6_t0_i0_rte_axu1, + output iu_rv_iu6_t0_i0_valop, + output iu_rv_iu6_t0_i0_ord, + output iu_rv_iu6_t0_i0_cord, + output [0:2] iu_rv_iu6_t0_i0_error, + output iu_rv_iu6_t0_i0_btb_entry, + output [0:1] iu_rv_iu6_t0_i0_btb_hist, + output iu_rv_iu6_t0_i0_bta_val, + output [0:19] iu_rv_iu6_t0_i0_fusion, + output iu_rv_iu6_t0_i0_spec, + output iu_rv_iu6_t0_i0_type_fp, + output iu_rv_iu6_t0_i0_type_ap, + output iu_rv_iu6_t0_i0_type_spv, + output iu_rv_iu6_t0_i0_type_st, + output iu_rv_iu6_t0_i0_async_block, + output iu_rv_iu6_t0_i0_np1_flush, + output iu_rv_iu6_t0_i0_isram, + output iu_rv_iu6_t0_i0_isload, + output iu_rv_iu6_t0_i0_isstore, + output [0:31] iu_rv_iu6_t0_i0_instr, + output [62-`EFF_IFAR_WIDTH:61] iu_rv_iu6_t0_i0_ifar, + output [62-`EFF_IFAR_WIDTH:61] iu_rv_iu6_t0_i0_bta, + output iu_rv_iu6_t0_i0_br_pred, + output iu_rv_iu6_t0_i0_bh_update, + output [0:1] iu_rv_iu6_t0_i0_bh0_hist, + output [0:1] iu_rv_iu6_t0_i0_bh1_hist, + output [0:1] iu_rv_iu6_t0_i0_bh2_hist, + output [0:17] iu_rv_iu6_t0_i0_gshare, + output [0:2] iu_rv_iu6_t0_i0_ls_ptr, + output iu_rv_iu6_t0_i0_match, + output [0:3] iu_rv_iu6_t0_i0_ilat, + output iu_rv_iu6_t0_i0_t1_v, + output [0:2] iu_rv_iu6_t0_i0_t1_t, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_t1_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_t1_p, + output iu_rv_iu6_t0_i0_t2_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_t2_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_t2_p, + output [0:2] iu_rv_iu6_t0_i0_t2_t, + output iu_rv_iu6_t0_i0_t3_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_t3_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_t3_p, + output [0:2] iu_rv_iu6_t0_i0_t3_t, + output iu_rv_iu6_t0_i0_s1_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_s1_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_s1_p, + output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i0_s1_itag, + output [0:2] iu_rv_iu6_t0_i0_s1_t, + output iu_rv_iu6_t0_i0_s2_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_s2_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_s2_p, + output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i0_s2_itag, + output [0:2] iu_rv_iu6_t0_i0_s2_t, + output iu_rv_iu6_t0_i0_s3_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_s3_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_s3_p, + output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i0_s3_itag, + output [0:2] iu_rv_iu6_t0_i0_s3_t, + + output iu_rv_iu6_t0_i1_vld, + output iu_rv_iu6_t0_i1_act, + output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i1_itag, + output [0:2] iu_rv_iu6_t0_i1_ucode, + output [0:`UCODE_ENTRIES_ENC-1] iu_rv_iu6_t0_i1_ucode_cnt, + output iu_rv_iu6_t0_i1_fuse_nop, + output iu_rv_iu6_t0_i1_rte_lq, + output iu_rv_iu6_t0_i1_rte_sq, + output iu_rv_iu6_t0_i1_rte_fx0, + output iu_rv_iu6_t0_i1_rte_fx1, + output iu_rv_iu6_t0_i1_rte_axu0, + output iu_rv_iu6_t0_i1_rte_axu1, + output iu_rv_iu6_t0_i1_valop, + output iu_rv_iu6_t0_i1_ord, + output iu_rv_iu6_t0_i1_cord, + output [0:2] iu_rv_iu6_t0_i1_error, + output iu_rv_iu6_t0_i1_btb_entry, + output [0:1] iu_rv_iu6_t0_i1_btb_hist, + output iu_rv_iu6_t0_i1_bta_val, + output [0:19] iu_rv_iu6_t0_i1_fusion, + output iu_rv_iu6_t0_i1_spec, + output iu_rv_iu6_t0_i1_type_fp, + output iu_rv_iu6_t0_i1_type_ap, + output iu_rv_iu6_t0_i1_type_spv, + output iu_rv_iu6_t0_i1_type_st, + output iu_rv_iu6_t0_i1_async_block, + output iu_rv_iu6_t0_i1_np1_flush, + output iu_rv_iu6_t0_i1_isram, + output iu_rv_iu6_t0_i1_isload, + output iu_rv_iu6_t0_i1_isstore, + output [0:31] iu_rv_iu6_t0_i1_instr, + output [62-`EFF_IFAR_WIDTH:61] iu_rv_iu6_t0_i1_ifar, + output [62-`EFF_IFAR_WIDTH:61] iu_rv_iu6_t0_i1_bta, + output iu_rv_iu6_t0_i1_br_pred, + output iu_rv_iu6_t0_i1_bh_update, + output [0:1] iu_rv_iu6_t0_i1_bh0_hist, + output [0:1] iu_rv_iu6_t0_i1_bh1_hist, + output [0:1] iu_rv_iu6_t0_i1_bh2_hist, + output [0:17] iu_rv_iu6_t0_i1_gshare, + output [0:2] iu_rv_iu6_t0_i1_ls_ptr, + output iu_rv_iu6_t0_i1_match, + output [0:3] iu_rv_iu6_t0_i1_ilat, + output iu_rv_iu6_t0_i1_t1_v, + output [0:2] iu_rv_iu6_t0_i1_t1_t, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_t1_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_t1_p, + output iu_rv_iu6_t0_i1_t2_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_t2_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_t2_p, + output [0:2] iu_rv_iu6_t0_i1_t2_t, + output iu_rv_iu6_t0_i1_t3_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_t3_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_t3_p, + output [0:2] iu_rv_iu6_t0_i1_t3_t, + output iu_rv_iu6_t0_i1_s1_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_s1_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_s1_p, + output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i1_s1_itag, + output [0:2] iu_rv_iu6_t0_i1_s1_t, + output iu_rv_iu6_t0_i1_s1_dep_hit, + output iu_rv_iu6_t0_i1_s2_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_s2_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_s2_p, + output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i1_s2_itag, + output [0:2] iu_rv_iu6_t0_i1_s2_t, + output iu_rv_iu6_t0_i1_s2_dep_hit, + output iu_rv_iu6_t0_i1_s3_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_s3_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_s3_p, + output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i1_s3_itag, + output [0:2] iu_rv_iu6_t0_i1_s3_t, + output iu_rv_iu6_t0_i1_s3_dep_hit, + +`ifndef THREADS1 + //---------------------------------------------------------------- + // Interface with rename + //---------------------------------------------------------------- + output iu_rv_iu6_t1_i0_vld, + output iu_rv_iu6_t1_i0_act, + output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i0_itag, + output [0:2] iu_rv_iu6_t1_i0_ucode, + output [0:`UCODE_ENTRIES_ENC-1] iu_rv_iu6_t1_i0_ucode_cnt, + output iu_rv_iu6_t1_i0_2ucode, + output iu_rv_iu6_t1_i0_fuse_nop, + output iu_rv_iu6_t1_i0_rte_lq, + output iu_rv_iu6_t1_i0_rte_sq, + output iu_rv_iu6_t1_i0_rte_fx0, + output iu_rv_iu6_t1_i0_rte_fx1, + output iu_rv_iu6_t1_i0_rte_axu0, + output iu_rv_iu6_t1_i0_rte_axu1, + output iu_rv_iu6_t1_i0_valop, + output iu_rv_iu6_t1_i0_ord, + output iu_rv_iu6_t1_i0_cord, + output [0:2] iu_rv_iu6_t1_i0_error, + output iu_rv_iu6_t1_i0_btb_entry, + output [0:1] iu_rv_iu6_t1_i0_btb_hist, + output iu_rv_iu6_t1_i0_bta_val, + output [0:19] iu_rv_iu6_t1_i0_fusion, + output iu_rv_iu6_t1_i0_spec, + output iu_rv_iu6_t1_i0_type_fp, + output iu_rv_iu6_t1_i0_type_ap, + output iu_rv_iu6_t1_i0_type_spv, + output iu_rv_iu6_t1_i0_type_st, + output iu_rv_iu6_t1_i0_async_block, + output iu_rv_iu6_t1_i0_np1_flush, + output iu_rv_iu6_t1_i0_isram, + output iu_rv_iu6_t1_i0_isload, + output iu_rv_iu6_t1_i0_isstore, + output [0:31] iu_rv_iu6_t1_i0_instr, + output [62-`EFF_IFAR_WIDTH:61] iu_rv_iu6_t1_i0_ifar, + output [62-`EFF_IFAR_WIDTH:61] iu_rv_iu6_t1_i0_bta, + output iu_rv_iu6_t1_i0_br_pred, + output iu_rv_iu6_t1_i0_bh_update, + output [0:1] iu_rv_iu6_t1_i0_bh0_hist, + output [0:1] iu_rv_iu6_t1_i0_bh1_hist, + output [0:1] iu_rv_iu6_t1_i0_bh2_hist, + output [0:17] iu_rv_iu6_t1_i0_gshare, + output [0:2] iu_rv_iu6_t1_i0_ls_ptr, + output iu_rv_iu6_t1_i0_match, + output [0:3] iu_rv_iu6_t1_i0_ilat, + output iu_rv_iu6_t1_i0_t1_v, + output [0:2] iu_rv_iu6_t1_i0_t1_t, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_t1_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_t1_p, + output iu_rv_iu6_t1_i0_t2_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_t2_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_t2_p, + output [0:2] iu_rv_iu6_t1_i0_t2_t, + output iu_rv_iu6_t1_i0_t3_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_t3_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_t3_p, + output [0:2] iu_rv_iu6_t1_i0_t3_t, + output iu_rv_iu6_t1_i0_s1_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_s1_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_s1_p, + output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i0_s1_itag, + output [0:2] iu_rv_iu6_t1_i0_s1_t, + output iu_rv_iu6_t1_i0_s2_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_s2_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_s2_p, + output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i0_s2_itag, + output [0:2] iu_rv_iu6_t1_i0_s2_t, + output iu_rv_iu6_t1_i0_s3_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_s3_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_s3_p, + output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i0_s3_itag, + output [0:2] iu_rv_iu6_t1_i0_s3_t, + + output iu_rv_iu6_t1_i1_vld, + output iu_rv_iu6_t1_i1_act, + output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i1_itag, + output [0:2] iu_rv_iu6_t1_i1_ucode, + output [0:`UCODE_ENTRIES_ENC-1] iu_rv_iu6_t1_i1_ucode_cnt, + output iu_rv_iu6_t1_i1_fuse_nop, + output iu_rv_iu6_t1_i1_rte_lq, + output iu_rv_iu6_t1_i1_rte_sq, + output iu_rv_iu6_t1_i1_rte_fx0, + output iu_rv_iu6_t1_i1_rte_fx1, + output iu_rv_iu6_t1_i1_rte_axu0, + output iu_rv_iu6_t1_i1_rte_axu1, + output iu_rv_iu6_t1_i1_valop, + output iu_rv_iu6_t1_i1_ord, + output iu_rv_iu6_t1_i1_cord, + output [0:2] iu_rv_iu6_t1_i1_error, + output iu_rv_iu6_t1_i1_btb_entry, + output [0:1] iu_rv_iu6_t1_i1_btb_hist, + output iu_rv_iu6_t1_i1_bta_val, + output [0:19] iu_rv_iu6_t1_i1_fusion, + output iu_rv_iu6_t1_i1_spec, + output iu_rv_iu6_t1_i1_type_fp, + output iu_rv_iu6_t1_i1_type_ap, + output iu_rv_iu6_t1_i1_type_spv, + output iu_rv_iu6_t1_i1_type_st, + output iu_rv_iu6_t1_i1_async_block, + output iu_rv_iu6_t1_i1_np1_flush, + output iu_rv_iu6_t1_i1_isram, + output iu_rv_iu6_t1_i1_isload, + output iu_rv_iu6_t1_i1_isstore, + output [0:31] iu_rv_iu6_t1_i1_instr, + output [62-`EFF_IFAR_WIDTH:61] iu_rv_iu6_t1_i1_ifar, + output [62-`EFF_IFAR_WIDTH:61] iu_rv_iu6_t1_i1_bta, + output iu_rv_iu6_t1_i1_br_pred, + output iu_rv_iu6_t1_i1_bh_update, + output [0:1] iu_rv_iu6_t1_i1_bh0_hist, + output [0:1] iu_rv_iu6_t1_i1_bh1_hist, + output [0:1] iu_rv_iu6_t1_i1_bh2_hist, + output [0:17] iu_rv_iu6_t1_i1_gshare, + output [0:2] iu_rv_iu6_t1_i1_ls_ptr, + output iu_rv_iu6_t1_i1_match, + output [0:3] iu_rv_iu6_t1_i1_ilat, + output iu_rv_iu6_t1_i1_t1_v, + output [0:2] iu_rv_iu6_t1_i1_t1_t, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_t1_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_t1_p, + output iu_rv_iu6_t1_i1_t2_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_t2_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_t2_p, + output [0:2] iu_rv_iu6_t1_i1_t2_t, + output iu_rv_iu6_t1_i1_t3_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_t3_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_t3_p, + output [0:2] iu_rv_iu6_t1_i1_t3_t, + output iu_rv_iu6_t1_i1_s1_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_s1_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_s1_p, + output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i1_s1_itag, + output [0:2] iu_rv_iu6_t1_i1_s1_t, + output iu_rv_iu6_t1_i1_s1_dep_hit, + output iu_rv_iu6_t1_i1_s2_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_s2_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_s2_p, + output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i1_s2_itag, + output [0:2] iu_rv_iu6_t1_i1_s2_t, + output iu_rv_iu6_t1_i1_s2_dep_hit, + output iu_rv_iu6_t1_i1_s3_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_s3_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_s3_p, + output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i1_s3_itag, + output [0:2] iu_rv_iu6_t1_i1_s3_t, + output iu_rv_iu6_t1_i1_s3_dep_hit, +`endif + input [0:`THREADS-1] spr_cpcr2_we + ); + + localparam [0:31] value_1 = 32'h00000001; + localparam [0:31] value_2 = 32'h00000002; + localparam [0:31] value_3 = 32'h00000003; + localparam [0:31] value_4 = 32'h00000004; + parameter fx0_high_credit_cnt_offset = 0; + parameter fx1_high_credit_cnt_offset = fx0_high_credit_cnt_offset + 5 * `THREADS; + parameter lq_cmdq_high_credit_cnt_offset = fx1_high_credit_cnt_offset + 5 * `THREADS; + parameter sq_cmdq_high_credit_cnt_offset = lq_cmdq_high_credit_cnt_offset + 5 * `THREADS; + parameter fu0_high_credit_cnt_offset = sq_cmdq_high_credit_cnt_offset + 5 * `THREADS; + parameter fu1_high_credit_cnt_offset = fu0_high_credit_cnt_offset + 5 * `THREADS; + parameter fx0_med_credit_cnt_offset = fu1_high_credit_cnt_offset + 5 * `THREADS; + parameter fx1_med_credit_cnt_offset = fx0_med_credit_cnt_offset + 5 * `THREADS; + parameter lq_cmdq_med_credit_cnt_offset = fx1_med_credit_cnt_offset + 5 * `THREADS; + parameter sq_cmdq_med_credit_cnt_offset = lq_cmdq_med_credit_cnt_offset + 5 * `THREADS; + parameter fu0_med_credit_cnt_offset = sq_cmdq_med_credit_cnt_offset + 5 * `THREADS; + parameter fu1_med_credit_cnt_offset = fu0_med_credit_cnt_offset + 5 * `THREADS; + parameter fx0_total_credit_cnt_offset = fu1_med_credit_cnt_offset + 5 * `THREADS; + parameter fx1_total_credit_cnt_offset = fx0_total_credit_cnt_offset + 5; + parameter lq_cmdq_total_credit_cnt_offset = fx1_total_credit_cnt_offset + 5; + parameter sq_cmdq_total_credit_cnt_offset = lq_cmdq_total_credit_cnt_offset + 5; + parameter fu0_total_credit_cnt_offset = sq_cmdq_total_credit_cnt_offset + 5; + parameter fu1_total_credit_cnt_offset = fu0_total_credit_cnt_offset + 5; + parameter cp_flush_offset = fu1_total_credit_cnt_offset + 5; + parameter xu_iu_run_thread_offset = cp_flush_offset + `THREADS; + parameter iu_xu_credits_returned_offset = xu_iu_run_thread_offset + `THREADS; + parameter dual_issue_use_fx0_offset = iu_xu_credits_returned_offset + 1; + parameter last_thread_offset = dual_issue_use_fx0_offset + 2; + parameter mm_hold_req_offset = last_thread_offset + `THREADS; + parameter mm_hold_done_offset = mm_hold_req_offset + `THREADS; + parameter mm_bus_snoop_hold_req_offset = mm_hold_done_offset + `THREADS; + parameter mm_bus_snoop_hold_done_offset = mm_bus_snoop_hold_req_offset + `THREADS; + parameter hold_instructions_offset = mm_bus_snoop_hold_done_offset + `THREADS; + parameter hold_req_offset = hold_instructions_offset + 1; + parameter hold_done_offset = hold_req_offset + `THREADS; + parameter ivax_hold_req_offset = hold_done_offset + `THREADS; + parameter mm_iu_flush_req_offset = ivax_hold_req_offset + `THREADS; + parameter mm_iu_hold_done_offset = mm_iu_flush_req_offset + `THREADS; + parameter mm_iu_bus_snoop_hold_req_offset = mm_iu_hold_done_offset + `THREADS; + parameter mm_iu_bus_snoop_hold_done_offset = mm_iu_bus_snoop_hold_req_offset + `THREADS; + parameter in_ucode_offset = mm_iu_bus_snoop_hold_done_offset + `THREADS; + parameter in_fusion_offset = in_ucode_offset + `THREADS; + parameter total_pri_mask_offset = in_fusion_offset + `THREADS; + parameter high_pri_mask_offset = total_pri_mask_offset + `THREADS; + parameter med_pri_mask_offset = high_pri_mask_offset + `THREADS; + parameter low_pri_mask_offset = med_pri_mask_offset + `THREADS; + parameter low_pri_cnt_offset = low_pri_mask_offset + `THREADS; + parameter low_pri_max_offset = low_pri_cnt_offset + 8 * `THREADS; + parameter perf_iu6_stall_offset = low_pri_max_offset + (6 * `THREADS); + parameter perf_iu6_dispatch_fx0_offset = perf_iu6_stall_offset + `THREADS; + parameter perf_iu6_dispatch_fx1_offset = perf_iu6_dispatch_fx0_offset + 2*`THREADS; + parameter perf_iu6_dispatch_lq_offset = perf_iu6_dispatch_fx1_offset + 2*`THREADS; + parameter perf_iu6_dispatch_axu0_offset = perf_iu6_dispatch_lq_offset + 2*`THREADS; + parameter perf_iu6_dispatch_axu1_offset = perf_iu6_dispatch_axu0_offset + 2*`THREADS; + parameter perf_iu6_fx0_credit_stall_offset = perf_iu6_dispatch_axu1_offset + 2*`THREADS; + parameter perf_iu6_fx1_credit_stall_offset = perf_iu6_fx0_credit_stall_offset + `THREADS; + parameter perf_iu6_lq_credit_stall_offset = perf_iu6_fx1_credit_stall_offset + `THREADS; + parameter perf_iu6_sq_credit_stall_offset = perf_iu6_lq_credit_stall_offset + `THREADS; + parameter perf_iu6_axu0_credit_stall_offset = perf_iu6_sq_credit_stall_offset + `THREADS; + parameter perf_iu6_axu1_credit_stall_offset = perf_iu6_axu0_credit_stall_offset + `THREADS; + parameter iu_pc_fx0_credit_ok_offset = perf_iu6_axu1_credit_stall_offset + `THREADS; + parameter iu_pc_fx1_credit_ok_offset = iu_pc_fx0_credit_ok_offset + `THREADS; + parameter iu_pc_lq_credit_ok_offset = iu_pc_fx1_credit_ok_offset + `THREADS; + parameter iu_pc_sq_credit_ok_offset = iu_pc_lq_credit_ok_offset + `THREADS; + parameter iu_pc_axu0_credit_ok_offset = iu_pc_sq_credit_ok_offset + `THREADS; + parameter iu_pc_axu1_credit_ok_offset = iu_pc_axu0_credit_ok_offset + `THREADS; + parameter scan_right = iu_pc_axu1_credit_ok_offset + `THREADS - 1; + + // scan + wire [0:scan_right] siv; + wire [0:scan_right] sov; + + wire tiup; + + // MMU hold request + wire [0:`THREADS-1] mm_hold_req_d; + wire [0:`THREADS-1] mm_hold_req_l2; + wire [0:`THREADS-1] mm_hold_done_d; + wire [0:`THREADS-1] mm_hold_done_l2; + wire [0:`THREADS-1] hold_req_d; + wire [0:`THREADS-1] hold_req_l2; + wire [0:`THREADS-1] hold_done_d; + wire [0:`THREADS-1] hold_done_l2; + wire [0:`THREADS-1] mm_bus_snoop_hold_req_d; + wire [0:`THREADS-1] mm_bus_snoop_hold_req_l2; + wire [0:`THREADS-1] mm_bus_snoop_hold_done_d; + wire [0:`THREADS-1] mm_bus_snoop_hold_done_l2; + wire [0:`THREADS-1] ivax_hold_req_d; + wire [0:`THREADS-1] ivax_hold_req_l2; + + wire [0:`THREADS-1] mm_iu_flush_req_d; + wire [0:`THREADS-1] mm_iu_flush_req_l2; + wire [0:`THREADS-1] mm_iu_hold_done_l2; + wire [0:`THREADS-1] mm_iu_bus_snoop_hold_req_d; + wire [0:`THREADS-1] mm_iu_bus_snoop_hold_req_l2; + wire [0:`THREADS-1] mm_iu_bus_snoop_hold_done_l2; + wire [0:`THREADS-1] in_ucode_d; + wire [0:`THREADS-1] in_ucode_l2; + wire [0:`THREADS-1] in_fusion_d; + wire [0:`THREADS-1] in_fusion_l2; + + wire hold_instructions_d; + wire hold_instructions_l2; + + + // Credit counters + wire [0:4] fx0_high_credit_cnt_plus1_temp[0:`THREADS-1]; + wire [0:4] fx0_high_credit_cnt_plus1[0:`THREADS-1]; + wire [0:4] fx0_high_credit_cnt_minus1_temp[0:`THREADS-1]; + wire [0:4] fx0_high_credit_cnt_minus1[0:`THREADS-1]; + wire [0:4] fx0_high_credit_cnt_minus2_temp[0:`THREADS-1]; + wire [0:4] fx0_high_credit_cnt_minus2[0:`THREADS-1]; + reg [0:4] fx0_high_credit_cnt_d[0:`THREADS-1]; + wire [0:4] fx0_high_credit_cnt_l2[0:`THREADS-1]; + wire [0:4] fx1_high_credit_cnt_plus1_temp[0:`THREADS-1]; + wire [0:4] fx1_high_credit_cnt_plus1[0:`THREADS-1]; + wire [0:4] fx1_high_credit_cnt_minus1_temp[0:`THREADS-1]; + wire [0:4] fx1_high_credit_cnt_minus1[0:`THREADS-1]; + wire [0:4] fx1_high_credit_cnt_minus2_temp[0:`THREADS-1]; + wire [0:4] fx1_high_credit_cnt_minus2[0:`THREADS-1]; + reg [0:4] fx1_high_credit_cnt_d[0:`THREADS-1]; + wire [0:4] fx1_high_credit_cnt_l2[0:`THREADS-1]; + wire [0:4] lq_cmdq_high_credit_cnt_plus1_temp[0:`THREADS-1]; + wire [0:4] lq_cmdq_high_credit_cnt_plus1[0:`THREADS-1]; + wire [0:4] lq_cmdq_high_credit_cnt_minus1_temp[0:`THREADS-1]; + wire [0:4] lq_cmdq_high_credit_cnt_minus1[0:`THREADS-1]; + wire [0:4] lq_cmdq_high_credit_cnt_minus2_temp[0:`THREADS-1]; + wire [0:4] lq_cmdq_high_credit_cnt_minus2[0:`THREADS-1]; + reg [0:4] lq_cmdq_high_credit_cnt_d[0:`THREADS-1]; + wire [0:4] lq_cmdq_high_credit_cnt_l2[0:`THREADS-1]; + wire [0:4] sq_cmdq_high_credit_cnt_plus1_temp[0:`THREADS-1]; + wire [0:4] sq_cmdq_high_credit_cnt_plus1[0:`THREADS-1]; + wire [0:4] sq_cmdq_high_credit_cnt_minus1_temp[0:`THREADS-1]; + wire [0:4] sq_cmdq_high_credit_cnt_minus1[0:`THREADS-1]; + wire [0:4] sq_cmdq_high_credit_cnt_minus2_temp[0:`THREADS-1]; + wire [0:4] sq_cmdq_high_credit_cnt_minus2[0:`THREADS-1]; + reg [0:4] sq_cmdq_high_credit_cnt_d[0:`THREADS-1]; + wire [0:4] sq_cmdq_high_credit_cnt_l2[0:`THREADS-1]; + wire [0:4] fu0_high_credit_cnt_plus1_temp[0:`THREADS-1]; + wire [0:4] fu0_high_credit_cnt_plus1[0:`THREADS-1]; + wire [0:4] fu0_high_credit_cnt_minus1_temp[0:`THREADS-1]; + wire [0:4] fu0_high_credit_cnt_minus1[0:`THREADS-1]; + wire [0:4] fu0_high_credit_cnt_minus2_temp[0:`THREADS-1]; + wire [0:4] fu0_high_credit_cnt_minus2[0:`THREADS-1]; + reg [0:4] fu0_high_credit_cnt_d[0:`THREADS-1]; + wire [0:4] fu0_high_credit_cnt_l2[0:`THREADS-1]; + wire [0:4] fu1_high_credit_cnt_plus1_temp[0:`THREADS-1]; + wire [0:4] fu1_high_credit_cnt_plus1[0:`THREADS-1]; + wire [0:4] fu1_high_credit_cnt_minus1_temp[0:`THREADS-1]; + wire [0:4] fu1_high_credit_cnt_minus1[0:`THREADS-1]; + wire [0:4] fu1_high_credit_cnt_minus2_temp[0:`THREADS-1]; + wire [0:4] fu1_high_credit_cnt_minus2[0:`THREADS-1]; + reg [0:4] fu1_high_credit_cnt_d[0:`THREADS-1]; + wire [0:4] fu1_high_credit_cnt_l2[0:`THREADS-1]; + + wire [0:4] fx0_med_credit_cnt_plus1_temp[0:`THREADS-1]; + wire [0:4] fx0_med_credit_cnt_plus1[0:`THREADS-1]; + wire [0:4] fx0_med_credit_cnt_minus1_temp[0:`THREADS-1]; + wire [0:4] fx0_med_credit_cnt_minus1[0:`THREADS-1]; + wire [0:4] fx0_med_credit_cnt_minus2_temp[0:`THREADS-1]; + wire [0:4] fx0_med_credit_cnt_minus2[0:`THREADS-1]; + reg [0:4] fx0_med_credit_cnt_d[0:`THREADS-1]; + wire [0:4] fx0_med_credit_cnt_l2[0:`THREADS-1]; + wire [0:4] fx1_med_credit_cnt_plus1_temp[0:`THREADS-1]; + wire [0:4] fx1_med_credit_cnt_plus1[0:`THREADS-1]; + wire [0:4] fx1_med_credit_cnt_minus1_temp[0:`THREADS-1]; + wire [0:4] fx1_med_credit_cnt_minus1[0:`THREADS-1]; + wire [0:4] fx1_med_credit_cnt_minus2_temp[0:`THREADS-1]; + wire [0:4] fx1_med_credit_cnt_minus2[0:`THREADS-1]; + reg [0:4] fx1_med_credit_cnt_d[0:`THREADS-1]; + wire [0:4] fx1_med_credit_cnt_l2[0:`THREADS-1]; + wire [0:4] lq_cmdq_med_credit_cnt_plus1_temp[0:`THREADS-1]; + wire [0:4] lq_cmdq_med_credit_cnt_plus1[0:`THREADS-1]; + wire [0:4] lq_cmdq_med_credit_cnt_minus1_temp[0:`THREADS-1]; + wire [0:4] lq_cmdq_med_credit_cnt_minus1[0:`THREADS-1]; + wire [0:4] lq_cmdq_med_credit_cnt_minus2_temp[0:`THREADS-1]; + wire [0:4] lq_cmdq_med_credit_cnt_minus2[0:`THREADS-1]; + reg [0:4] lq_cmdq_med_credit_cnt_d[0:`THREADS-1]; + wire [0:4] lq_cmdq_med_credit_cnt_l2[0:`THREADS-1]; + wire [0:4] sq_cmdq_med_credit_cnt_plus1_temp[0:`THREADS-1]; + wire [0:4] sq_cmdq_med_credit_cnt_plus1[0:`THREADS-1]; + wire [0:4] sq_cmdq_med_credit_cnt_minus1_temp[0:`THREADS-1]; + wire [0:4] sq_cmdq_med_credit_cnt_minus1[0:`THREADS-1]; + wire [0:4] sq_cmdq_med_credit_cnt_minus2_temp[0:`THREADS-1]; + wire [0:4] sq_cmdq_med_credit_cnt_minus2[0:`THREADS-1]; + reg [0:4] sq_cmdq_med_credit_cnt_d[0:`THREADS-1]; + wire [0:4] sq_cmdq_med_credit_cnt_l2[0:`THREADS-1]; + wire [0:4] fu0_med_credit_cnt_plus1_temp[0:`THREADS-1]; + wire [0:4] fu0_med_credit_cnt_plus1[0:`THREADS-1]; + wire [0:4] fu0_med_credit_cnt_minus1_temp[0:`THREADS-1]; + wire [0:4] fu0_med_credit_cnt_minus1[0:`THREADS-1]; + wire [0:4] fu0_med_credit_cnt_minus2_temp[0:`THREADS-1]; + wire [0:4] fu0_med_credit_cnt_minus2[0:`THREADS-1]; + reg [0:4] fu0_med_credit_cnt_d[0:`THREADS-1]; + wire [0:4] fu0_med_credit_cnt_l2[0:`THREADS-1]; + wire [0:4] fu1_med_credit_cnt_plus1_temp[0:`THREADS-1]; + wire [0:4] fu1_med_credit_cnt_plus1[0:`THREADS-1]; + wire [0:4] fu1_med_credit_cnt_minus1_temp[0:`THREADS-1]; + wire [0:4] fu1_med_credit_cnt_minus1[0:`THREADS-1]; + wire [0:4] fu1_med_credit_cnt_minus2_temp[0:`THREADS-1]; + wire [0:4] fu1_med_credit_cnt_minus2[0:`THREADS-1]; + reg [0:4] fu1_med_credit_cnt_d[0:`THREADS-1]; + wire [0:4] fu1_med_credit_cnt_l2[0:`THREADS-1]; + + wire [0:4] fx0_credit_cnt_mux[0:`THREADS-1]; + wire [0:4] fx1_credit_cnt_mux[0:`THREADS-1]; + wire [0:4] lq_cmdq_credit_cnt_mux[0:`THREADS-1]; + wire [0:4] sq_cmdq_credit_cnt_mux[0:`THREADS-1]; + wire [0:4] fu0_credit_cnt_mux[0:`THREADS-1]; + wire [0:4] fu1_credit_cnt_mux[0:`THREADS-1]; + + reg [0:4] fx0_total_credit_cnt_d; + wire [0:4] fx0_total_credit_cnt_l2; + reg [0:4] fx1_total_credit_cnt_d; + wire [0:4] fx1_total_credit_cnt_l2; + reg [0:4] lq_cmdq_total_credit_cnt_d; + wire [0:4] lq_cmdq_total_credit_cnt_l2; + reg [0:4] sq_cmdq_total_credit_cnt_d; + wire [0:4] sq_cmdq_total_credit_cnt_l2; + reg [0:4] fu0_total_credit_cnt_d; + wire [0:4] fu0_total_credit_cnt_l2; + reg [0:4] fu1_total_credit_cnt_d; + wire [0:4] fu1_total_credit_cnt_l2; + + wire [0:`THREADS-1] total_pri_mask_d; + wire [0:`THREADS-1] total_pri_mask_l2; + wire [0:`THREADS-1] high_pri_mask_d; + wire [0:`THREADS-1] high_pri_mask_l2; + wire [0:`THREADS-1] med_pri_mask_d; + wire [0:`THREADS-1] med_pri_mask_l2; + wire [0:`THREADS-1] low_pri_mask_d; + wire [0:`THREADS-1] low_pri_mask_l2; + wire [0:7] low_pri_cnt_d[0:`THREADS-1]; + wire [0:7] low_pri_cnt_l2[0:`THREADS-1]; + wire [0:5] low_pri_max_d[0:`THREADS-1]; + wire [0:5] low_pri_max_l2[0:`THREADS-1]; + wire [0:`THREADS-1] low_pri_cnt_act; + wire [0:`THREADS-1] low_pri_en; + + // Perf count latches + wire [0:`THREADS-1] perf_iu6_stall_d; + wire [0:`THREADS-1] perf_iu6_stall_l2; + wire [0:1] perf_iu6_dispatch_fx0_d[0:`THREADS-1]; + wire [0:1] perf_iu6_dispatch_fx0_l2[0:`THREADS-1]; + wire [0:1] perf_iu6_dispatch_fx1_d[0:`THREADS-1]; + wire [0:1] perf_iu6_dispatch_fx1_l2[0:`THREADS-1]; + wire [0:1] perf_iu6_dispatch_lq_d[0:`THREADS-1]; + wire [0:1] perf_iu6_dispatch_lq_l2[0:`THREADS-1]; + wire [0:1] perf_iu6_dispatch_axu0_d[0:`THREADS-1]; + wire [0:1] perf_iu6_dispatch_axu0_l2[0:`THREADS-1]; + wire [0:1] perf_iu6_dispatch_axu1_d[0:`THREADS-1]; + wire [0:1] perf_iu6_dispatch_axu1_l2[0:`THREADS-1]; + wire [0:`THREADS-1] perf_iu6_fx0_credit_stall_d; + wire [0:`THREADS-1] perf_iu6_fx0_credit_stall_l2; + wire [0:`THREADS-1] perf_iu6_fx1_credit_stall_d; + wire [0:`THREADS-1] perf_iu6_fx1_credit_stall_l2; + wire [0:`THREADS-1] perf_iu6_lq_credit_stall_d; + wire [0:`THREADS-1] perf_iu6_lq_credit_stall_l2; + wire [0:`THREADS-1] perf_iu6_sq_credit_stall_d; + wire [0:`THREADS-1] perf_iu6_sq_credit_stall_l2; + wire [0:`THREADS-1] perf_iu6_axu0_credit_stall_d; + wire [0:`THREADS-1] perf_iu6_axu0_credit_stall_l2; + wire [0:`THREADS-1] perf_iu6_axu1_credit_stall_d; + wire [0:`THREADS-1] perf_iu6_axu1_credit_stall_l2; + + wire [0:`THREADS-1] iu_pc_fx0_credit_ok_d; + wire [0:`THREADS-1] iu_pc_fx0_credit_ok_l2; + wire [0:`THREADS-1] iu_pc_fx1_credit_ok_d; + wire [0:`THREADS-1] iu_pc_fx1_credit_ok_l2; + wire [0:`THREADS-1] iu_pc_lq_credit_ok_d; + wire [0:`THREADS-1] iu_pc_lq_credit_ok_l2; + wire [0:`THREADS-1] iu_pc_sq_credit_ok_d; + wire [0:`THREADS-1] iu_pc_sq_credit_ok_l2; + wire [0:`THREADS-1] iu_pc_axu0_credit_ok_d; + wire [0:`THREADS-1] iu_pc_axu0_credit_ok_l2; + wire [0:`THREADS-1] iu_pc_axu1_credit_ok_d; + wire [0:`THREADS-1] iu_pc_axu1_credit_ok_l2; + + // Counts used for total counts + reg [0:1] fx0_credit_cnt_minus_1; + reg [0:1] fx0_credit_cnt_minus_2; + reg [0:1] fx0_credit_cnt_plus_1; + reg [0:1] fx0_credit_cnt_zero; + reg [0:1] fx1_credit_cnt_minus_1; + reg [0:1] fx1_credit_cnt_minus_2; + reg [0:1] fx1_credit_cnt_plus_1; + reg [0:1] fx1_credit_cnt_zero; + reg [0:1] lq_cmdq_credit_cnt_minus_1; + reg [0:1] lq_cmdq_credit_cnt_minus_2; + reg [0:1] lq_cmdq_credit_cnt_plus_1; + reg [0:1] lq_cmdq_credit_cnt_zero; + reg [0:1] sq_cmdq_credit_cnt_minus_1; + reg [0:1] sq_cmdq_credit_cnt_minus_2; + reg [0:1] sq_cmdq_credit_cnt_plus_1; + reg [0:1] sq_cmdq_credit_cnt_zero; + reg [0:1] fu0_credit_cnt_minus_1; + reg [0:1] fu0_credit_cnt_minus_2; + reg [0:1] fu0_credit_cnt_plus_1; + reg [0:1] fu0_credit_cnt_zero; + reg [0:1] fu1_credit_cnt_minus_1; + reg [0:1] fu1_credit_cnt_minus_2; + reg [0:1] fu1_credit_cnt_plus_1; + reg [0:1] fu1_credit_cnt_zero; + + // Latch to delay the flush signal + wire [0:`THREADS-1] cp_flush_l2; + wire [0:`THREADS-1] xu_iu_run_thread_l2; + + wire iu_xu_credits_returned_d; + wire iu_xu_credits_returned_l2; + + // Rotating bit to determine in a tie which thread will issue + wire [0:`THREADS-1] last_thread_d; + wire [0:`THREADS-1] last_thread_l2; + wire last_thread_act; + + // This signal compares credits left and issues FX0 and FX1 instructions to FX0 when set + reg [0:1] dual_issue_use_fx0_d; + wire [0:1] dual_issue_use_fx0_l2; + + wire [0:1] fx0_send_cnt[0:`THREADS-1]; + wire [0:1] fx1_send_cnt[0:`THREADS-1]; + wire [0:1] lq_cmdq_send_cnt[0:`THREADS-1]; + wire [0:1] sq_cmdq_send_cnt[0:`THREADS-1]; + wire [0:1] fu0_send_cnt[0:`THREADS-1]; + wire [0:1] fu1_send_cnt[0:`THREADS-1]; + + wire [0:`THREADS-1] core_block_ok; + // Check credits if only issue individual thread + wire [0:`THREADS-1] fx0_local_credit_ok; + wire [0:`THREADS-1] fx1_local_credit_ok; + wire [0:`THREADS-1] lq_cmdq_local_credit_ok; + wire [0:`THREADS-1] sq_cmdq_local_credit_ok; + wire [0:`THREADS-1] fu0_local_credit_ok; + wire [0:`THREADS-1] fu1_local_credit_ok; + // Check total credits if only issue individual thread + wire [0:`THREADS-1] fx0_credit_ok; + wire [0:`THREADS-1] fx1_credit_ok; + wire [0:`THREADS-1] lq_cmdq_credit_ok; + wire [0:`THREADS-1] sq_cmdq_credit_ok; + wire [0:`THREADS-1] fu0_credit_ok; + wire [0:`THREADS-1] fu1_credit_ok; + // Check total credits if issue all `THREADS + wire fx0_both_credit_ok; + wire fx1_both_credit_ok; + wire lq_cmdq_both_credit_ok; + wire sq_cmdq_both_credit_ok; + wire fu0_both_credit_ok; + wire fu1_both_credit_ok; + + wire [0:`THREADS-1] core_block; + + wire [0:`THREADS-1] send_instructions_all; + wire [0:`THREADS-1] send_instructions_local; + wire [0:`THREADS-1] send_instructions; + + // signals to be used internal to vhdl + wire [0:`THREADS-1] iu_rv_iu6_i0_vld_int; + wire [0:`THREADS-1] iu_rv_iu6_i1_vld_int; + + // Pervasive + wire pc_iu_func_sl_thold_1; + wire pc_iu_func_sl_thold_0; + wire pc_iu_func_sl_thold_0_b; + wire pc_iu_func_slp_sl_thold_1; + wire pc_iu_func_slp_sl_thold_0; + wire pc_iu_func_slp_sl_thold_0_b; + wire pc_iu_sg_1; + wire pc_iu_sg_0; + wire force_t; + + wire [0:4] spr_high_fx0_cnt[0:`THREADS-1]; + wire [0:4] spr_high_fx1_cnt[0:`THREADS-1]; + wire [0:4] spr_high_lq_cnt[0:`THREADS-1]; + wire [0:4] spr_high_sq_cnt[0:`THREADS-1]; + wire [0:4] spr_high_fu0_cnt[0:`THREADS-1]; + wire [0:4] spr_high_fu1_cnt[0:`THREADS-1]; + + wire [0:4] spr_med_fx0_cnt[0:`THREADS-1]; + wire [0:4] spr_med_fx1_cnt[0:`THREADS-1]; + wire [0:4] spr_med_lq_cnt[0:`THREADS-1]; + wire [0:4] spr_med_sq_cnt[0:`THREADS-1]; + wire [0:4] spr_med_fu0_cnt[0:`THREADS-1]; + wire [0:4] spr_med_fu1_cnt[0:`THREADS-1]; + + wire [0:5] spr_low_pri_count[0:`THREADS-1]; + + // Wires to more to 2D arrays + wire [0:`THREADS-1] frn_fdis_iu6_i0_vld; + wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i0_itag[0:`THREADS-1]; + wire [0:2] frn_fdis_iu6_i0_ucode[0:`THREADS-1]; + wire [0:`UCODE_ENTRIES_ENC-1] frn_fdis_iu6_i0_ucode_cnt[0:`THREADS-1]; + wire [0:`THREADS-1] frn_fdis_iu6_i0_2ucode; + wire [0:`THREADS-1] frn_fdis_iu6_i0_fuse_nop; + wire [0:`THREADS-1] frn_fdis_iu6_i0_rte_lq; + wire [0:`THREADS-1] frn_fdis_iu6_i0_rte_sq; + wire [0:`THREADS-1] frn_fdis_iu6_i0_rte_fx0; + wire [0:`THREADS-1] frn_fdis_iu6_i0_rte_fx1; + wire [0:`THREADS-1] frn_fdis_iu6_i0_rte_axu0; + wire [0:`THREADS-1] frn_fdis_iu6_i0_rte_axu1; + wire [0:`THREADS-1] frn_fdis_iu6_i0_valop; + wire [0:`THREADS-1] frn_fdis_iu6_i0_ord; + wire [0:`THREADS-1] frn_fdis_iu6_i0_cord; + wire [0:2] frn_fdis_iu6_i0_error[0:`THREADS-1]; + wire [0:`THREADS-1] frn_fdis_iu6_i0_btb_entry; + wire [0:1] frn_fdis_iu6_i0_btb_hist[0:`THREADS-1]; + wire [0:`THREADS-1] frn_fdis_iu6_i0_bta_val; + wire [0:19] frn_fdis_iu6_i0_fusion[0:`THREADS-1]; + wire [0:`THREADS-1] frn_fdis_iu6_i0_spec; + wire [0:`THREADS-1] frn_fdis_iu6_i0_type_fp; + wire [0:`THREADS-1] frn_fdis_iu6_i0_type_ap; + wire [0:`THREADS-1] frn_fdis_iu6_i0_type_spv; + wire [0:`THREADS-1] frn_fdis_iu6_i0_type_st; + wire [0:`THREADS-1] frn_fdis_iu6_i0_async_block; + wire [0:`THREADS-1] frn_fdis_iu6_i0_np1_flush; + wire [0:`THREADS-1] frn_fdis_iu6_i0_core_block; + wire [0:`THREADS-1] frn_fdis_iu6_i0_isram; + wire [0:`THREADS-1] frn_fdis_iu6_i0_isload; + wire [0:`THREADS-1] frn_fdis_iu6_i0_isstore; + wire [0:31] frn_fdis_iu6_i0_instr[0:`THREADS-1]; + wire [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_i0_ifar[0:`THREADS-1]; + wire [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_i0_bta[0:`THREADS-1]; + wire [0:`THREADS-1] frn_fdis_iu6_i0_br_pred; + wire [0:`THREADS-1] frn_fdis_iu6_i0_bh_update; + wire [0:1] frn_fdis_iu6_i0_bh0_hist[0:`THREADS-1]; + wire [0:1] frn_fdis_iu6_i0_bh1_hist[0:`THREADS-1]; + wire [0:1] frn_fdis_iu6_i0_bh2_hist[0:`THREADS-1]; + wire [0:17] frn_fdis_iu6_i0_gshare[0:`THREADS-1]; + wire [0:2] frn_fdis_iu6_i0_ls_ptr[0:`THREADS-1]; + wire [0:`THREADS-1] frn_fdis_iu6_i0_match; + wire [0:3] frn_fdis_iu6_i0_ilat[0:`THREADS-1]; + wire [0:`THREADS-1] frn_fdis_iu6_i0_t1_v; + wire [0:2] frn_fdis_iu6_i0_t1_t[0:`THREADS-1]; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t1_a[0:`THREADS-1]; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t1_p[0:`THREADS-1]; + wire [0:`THREADS-1] frn_fdis_iu6_i0_t2_v; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t2_a[0:`THREADS-1]; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t2_p[0:`THREADS-1]; + wire [0:2] frn_fdis_iu6_i0_t2_t[0:`THREADS-1]; + wire [0:`THREADS-1] frn_fdis_iu6_i0_t3_v; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t3_a[0:`THREADS-1]; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t3_p[0:`THREADS-1]; + wire [0:2] frn_fdis_iu6_i0_t3_t[0:`THREADS-1]; + wire [0:`THREADS-1] frn_fdis_iu6_i0_s1_v; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s1_a[0:`THREADS-1]; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s1_p[0:`THREADS-1]; + wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i0_s1_itag[0:`THREADS-1]; + wire [0:2] frn_fdis_iu6_i0_s1_t[0:`THREADS-1]; + wire [0:`THREADS-1] frn_fdis_iu6_i0_s1_dep_hit; + wire [0:`THREADS-1] frn_fdis_iu6_i0_s2_v; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s2_a[0:`THREADS-1]; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s2_p[0:`THREADS-1]; + wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i0_s2_itag[0:`THREADS-1]; + wire [0:2] frn_fdis_iu6_i0_s2_t[0:`THREADS-1]; + wire [0:`THREADS-1] frn_fdis_iu6_i0_s2_dep_hit; + wire [0:`THREADS-1] frn_fdis_iu6_i0_s3_v; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s3_a[0:`THREADS-1]; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s3_p[0:`THREADS-1]; + wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i0_s3_itag[0:`THREADS-1]; + wire [0:2] frn_fdis_iu6_i0_s3_t[0:`THREADS-1]; + wire [0:`THREADS-1] frn_fdis_iu6_i0_s3_dep_hit; + + wire [0:`THREADS-1] frn_fdis_iu6_i1_vld; + wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i1_itag[0:`THREADS-1]; + wire [0:2] frn_fdis_iu6_i1_ucode[0:`THREADS-1]; + wire [0:`UCODE_ENTRIES_ENC-1] frn_fdis_iu6_i1_ucode_cnt[0:`THREADS-1]; + wire [0:`THREADS-1] frn_fdis_iu6_i1_fuse_nop; + wire [0:`THREADS-1] frn_fdis_iu6_i1_rte_lq; + wire [0:`THREADS-1] frn_fdis_iu6_i1_rte_sq; + wire [0:`THREADS-1] frn_fdis_iu6_i1_rte_fx0; + wire [0:`THREADS-1] frn_fdis_iu6_i1_rte_fx1; + wire [0:`THREADS-1] frn_fdis_iu6_i1_rte_axu0; + wire [0:`THREADS-1] frn_fdis_iu6_i1_rte_axu1; + wire [0:`THREADS-1] frn_fdis_iu6_i1_valop; + wire [0:`THREADS-1] frn_fdis_iu6_i1_ord; + wire [0:`THREADS-1] frn_fdis_iu6_i1_cord; + wire [0:2] frn_fdis_iu6_i1_error[0:`THREADS-1]; + wire [0:`THREADS-1] frn_fdis_iu6_i1_btb_entry; + wire [0:1] frn_fdis_iu6_i1_btb_hist[0:`THREADS-1]; + wire [0:`THREADS-1] frn_fdis_iu6_i1_bta_val; + wire [0:19] frn_fdis_iu6_i1_fusion[0:`THREADS-1]; + wire [0:`THREADS-1] frn_fdis_iu6_i1_spec; + wire [0:`THREADS-1] frn_fdis_iu6_i1_type_fp; + wire [0:`THREADS-1] frn_fdis_iu6_i1_type_ap; + wire [0:`THREADS-1] frn_fdis_iu6_i1_type_spv; + wire [0:`THREADS-1] frn_fdis_iu6_i1_type_st; + wire [0:`THREADS-1] frn_fdis_iu6_i1_async_block; + wire [0:`THREADS-1] frn_fdis_iu6_i1_np1_flush; + wire [0:`THREADS-1] frn_fdis_iu6_i1_core_block; + wire [0:`THREADS-1] frn_fdis_iu6_i1_isram; + wire [0:`THREADS-1] frn_fdis_iu6_i1_isload; + wire [0:`THREADS-1] frn_fdis_iu6_i1_isstore; + wire [0:31] frn_fdis_iu6_i1_instr[0:`THREADS-1]; + wire [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_i1_ifar[0:`THREADS-1]; + wire [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_i1_bta[0:`THREADS-1]; + wire [0:`THREADS-1] frn_fdis_iu6_i1_br_pred; + wire [0:`THREADS-1] frn_fdis_iu6_i1_bh_update; + wire [0:1] frn_fdis_iu6_i1_bh0_hist[0:`THREADS-1]; + wire [0:1] frn_fdis_iu6_i1_bh1_hist[0:`THREADS-1]; + wire [0:1] frn_fdis_iu6_i1_bh2_hist[0:`THREADS-1]; + wire [0:17] frn_fdis_iu6_i1_gshare[0:`THREADS-1]; + wire [0:2] frn_fdis_iu6_i1_ls_ptr[0:`THREADS-1]; + wire [0:`THREADS-1] frn_fdis_iu6_i1_match; + wire [0:3] frn_fdis_iu6_i1_ilat[0:`THREADS-1]; + wire [0:`THREADS-1] frn_fdis_iu6_i1_t1_v; + wire [0:2] frn_fdis_iu6_i1_t1_t[0:`THREADS-1]; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t1_a[0:`THREADS-1]; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t1_p[0:`THREADS-1]; + wire [0:`THREADS-1] frn_fdis_iu6_i1_t2_v; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t2_a[0:`THREADS-1]; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t2_p[0:`THREADS-1]; + wire [0:2] frn_fdis_iu6_i1_t2_t[0:`THREADS-1]; + wire [0:`THREADS-1] frn_fdis_iu6_i1_t3_v; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t3_a[0:`THREADS-1]; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t3_p[0:`THREADS-1]; + wire [0:2] frn_fdis_iu6_i1_t3_t[0:`THREADS-1]; + wire [0:`THREADS-1] frn_fdis_iu6_i1_s1_v; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s1_a[0:`THREADS-1]; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s1_p[0:`THREADS-1]; + wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i1_s1_itag[0:`THREADS-1]; + wire [0:2] frn_fdis_iu6_i1_s1_t[0:`THREADS-1]; + wire [0:`THREADS-1] frn_fdis_iu6_i1_s1_dep_hit; + wire [0:`THREADS-1] frn_fdis_iu6_i1_s2_v; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s2_a[0:`THREADS-1]; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s2_p[0:`THREADS-1]; + wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i1_s2_itag[0:`THREADS-1]; + wire [0:2] frn_fdis_iu6_i1_s2_t[0:`THREADS-1]; + wire [0:`THREADS-1] frn_fdis_iu6_i1_s2_dep_hit; + wire [0:`THREADS-1] frn_fdis_iu6_i1_s3_v; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s3_a[0:`THREADS-1]; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s3_p[0:`THREADS-1]; + wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i1_s3_itag[0:`THREADS-1]; + wire [0:2] frn_fdis_iu6_i1_s3_t[0:`THREADS-1]; + wire [0:`THREADS-1] frn_fdis_iu6_i1_s3_dep_hit; + + wire [0:`THREADS-1] fx0_send_cnt_zero; + wire [0:`THREADS-1] fx0_send_cnt_one; + wire [0:`THREADS-1] fx1_send_cnt_zero; + wire [0:`THREADS-1] fx1_send_cnt_one; + wire [0:`THREADS-1] fu0_send_cnt_zero; + wire [0:`THREADS-1] fu0_send_cnt_one; + wire [0:`THREADS-1] fu1_send_cnt_zero; + wire [0:`THREADS-1] fu1_send_cnt_one; + wire [0:`THREADS-1] lq_cmdq_send_cnt_zero; + wire [0:`THREADS-1] lq_cmdq_send_cnt_one; + wire [0:`THREADS-1] sq_cmdq_send_cnt_zero; + wire [0:`THREADS-1] sq_cmdq_send_cnt_one; + + wire funcslp_force; + + //!! Bugspray Include: iuq_dispatch + + assign spr_high_fx0_cnt[0] = spr_t0_cpcr2_fx0_cnt; + assign spr_high_fx1_cnt[0] = spr_t0_cpcr2_fx1_cnt; + assign spr_high_lq_cnt[0] = spr_t0_cpcr2_lq_cnt; + assign spr_high_sq_cnt[0] = spr_t0_cpcr2_sq_cnt; + assign spr_high_fu0_cnt[0] = spr_t0_cpcr3_fu0_cnt; + assign spr_high_fu1_cnt[0] = spr_t0_cpcr3_fu1_cnt; + assign spr_med_fx0_cnt[0] = spr_t0_cpcr4_fx0_cnt; + assign spr_med_fx1_cnt[0] = spr_t0_cpcr4_fx1_cnt; + assign spr_med_lq_cnt[0] = spr_t0_cpcr4_lq_cnt; + assign spr_med_sq_cnt[0] = spr_t0_cpcr4_sq_cnt; + assign spr_med_fu0_cnt[0] = spr_t0_cpcr5_fu0_cnt; + assign spr_med_fu1_cnt[0] = spr_t0_cpcr5_fu1_cnt; + assign spr_low_pri_count[0] = spr_t0_low_pri_count; +`ifndef THREADS1 + assign spr_high_fx0_cnt[1] = spr_t1_cpcr2_fx0_cnt; + assign spr_high_fx1_cnt[1] = spr_t1_cpcr2_fx1_cnt; + assign spr_high_lq_cnt[1] = spr_t1_cpcr2_lq_cnt; + assign spr_high_sq_cnt[1] = spr_t1_cpcr2_sq_cnt; + assign spr_high_fu0_cnt[1] = spr_t1_cpcr3_fu0_cnt; + assign spr_high_fu1_cnt[1] = spr_t1_cpcr3_fu1_cnt; + assign spr_med_fx0_cnt[1] = spr_t1_cpcr4_fx0_cnt; + assign spr_med_fx1_cnt[1] = spr_t1_cpcr4_fx1_cnt; + assign spr_med_lq_cnt[1] = spr_t1_cpcr4_lq_cnt; + assign spr_med_sq_cnt[1] = spr_t1_cpcr4_sq_cnt; + assign spr_med_fu0_cnt[1] = spr_t1_cpcr5_fu0_cnt; + assign spr_med_fu1_cnt[1] = spr_t1_cpcr5_fu1_cnt; + assign spr_low_pri_count[1] = spr_t1_low_pri_count; +`endif + + assign frn_fdis_iu6_i0_vld[0] = frn_fdis_iu6_t0_i0_vld; + assign frn_fdis_iu6_i0_itag[0] = frn_fdis_iu6_t0_i0_itag; + assign frn_fdis_iu6_i0_ucode[0] = frn_fdis_iu6_t0_i0_ucode; + assign frn_fdis_iu6_i0_ucode_cnt[0] = frn_fdis_iu6_t0_i0_ucode_cnt; + assign frn_fdis_iu6_i0_2ucode[0] = frn_fdis_iu6_t0_i0_2ucode; + assign frn_fdis_iu6_i0_fuse_nop[0] = frn_fdis_iu6_t0_i0_fuse_nop; + assign frn_fdis_iu6_i0_rte_lq[0] = frn_fdis_iu6_t0_i0_rte_lq; + assign frn_fdis_iu6_i0_rte_sq[0] = frn_fdis_iu6_t0_i0_rte_sq; + assign frn_fdis_iu6_i0_rte_fx0[0] = frn_fdis_iu6_t0_i0_rte_fx0; + assign frn_fdis_iu6_i0_rte_fx1[0] = frn_fdis_iu6_t0_i0_rte_fx1; + assign frn_fdis_iu6_i0_rte_axu0[0] = frn_fdis_iu6_t0_i0_rte_axu0; + assign frn_fdis_iu6_i0_rte_axu1[0] = frn_fdis_iu6_t0_i0_rte_axu1; + assign frn_fdis_iu6_i0_valop[0] = frn_fdis_iu6_t0_i0_valop; + assign frn_fdis_iu6_i0_ord[0] = frn_fdis_iu6_t0_i0_ord; + assign frn_fdis_iu6_i0_cord[0] = frn_fdis_iu6_t0_i0_cord; + assign frn_fdis_iu6_i0_error[0] = frn_fdis_iu6_t0_i0_error; + assign frn_fdis_iu6_i0_btb_entry[0] = frn_fdis_iu6_t0_i0_btb_entry; + assign frn_fdis_iu6_i0_btb_hist[0] = frn_fdis_iu6_t0_i0_btb_hist; + assign frn_fdis_iu6_i0_bta_val[0] = frn_fdis_iu6_t0_i0_bta_val; + assign frn_fdis_iu6_i0_fusion[0] = frn_fdis_iu6_t0_i0_fusion; + assign frn_fdis_iu6_i0_spec[0] = frn_fdis_iu6_t0_i0_spec; + assign frn_fdis_iu6_i0_type_fp[0] = frn_fdis_iu6_t0_i0_type_fp; + assign frn_fdis_iu6_i0_type_ap[0] = frn_fdis_iu6_t0_i0_type_ap; + assign frn_fdis_iu6_i0_type_spv[0] = frn_fdis_iu6_t0_i0_type_spv; + assign frn_fdis_iu6_i0_type_st[0] = frn_fdis_iu6_t0_i0_type_st; + assign frn_fdis_iu6_i0_async_block[0] = frn_fdis_iu6_t0_i0_async_block; + assign frn_fdis_iu6_i0_np1_flush[0] = frn_fdis_iu6_t0_i0_np1_flush; + assign frn_fdis_iu6_i0_core_block[0] = frn_fdis_iu6_t0_i0_core_block; + assign frn_fdis_iu6_i0_isram[0] = frn_fdis_iu6_t0_i0_isram; + assign frn_fdis_iu6_i0_isload[0] = frn_fdis_iu6_t0_i0_isload; + assign frn_fdis_iu6_i0_isstore[0] = frn_fdis_iu6_t0_i0_isstore; + assign frn_fdis_iu6_i0_instr[0] = frn_fdis_iu6_t0_i0_instr; + assign frn_fdis_iu6_i0_ifar[0] = frn_fdis_iu6_t0_i0_ifar; + assign frn_fdis_iu6_i0_bta[0] = frn_fdis_iu6_t0_i0_bta; + assign frn_fdis_iu6_i0_br_pred[0] = frn_fdis_iu6_t0_i0_br_pred; + assign frn_fdis_iu6_i0_bh_update[0] = frn_fdis_iu6_t0_i0_bh_update; + assign frn_fdis_iu6_i0_bh0_hist[0] = frn_fdis_iu6_t0_i0_bh0_hist; + assign frn_fdis_iu6_i0_bh1_hist[0] = frn_fdis_iu6_t0_i0_bh1_hist; + assign frn_fdis_iu6_i0_bh2_hist[0] = frn_fdis_iu6_t0_i0_bh2_hist; + assign frn_fdis_iu6_i0_gshare[0] = frn_fdis_iu6_t0_i0_gshare; + assign frn_fdis_iu6_i0_ls_ptr[0] = frn_fdis_iu6_t0_i0_ls_ptr; + assign frn_fdis_iu6_i0_match[0] = frn_fdis_iu6_t0_i0_match; + assign frn_fdis_iu6_i0_ilat[0] = frn_fdis_iu6_t0_i0_ilat; + assign frn_fdis_iu6_i0_t1_v[0] = frn_fdis_iu6_t0_i0_t1_v; + assign frn_fdis_iu6_i0_t1_t[0] = frn_fdis_iu6_t0_i0_t1_t; + assign frn_fdis_iu6_i0_t1_a[0] = frn_fdis_iu6_t0_i0_t1_a; + assign frn_fdis_iu6_i0_t1_p[0] = frn_fdis_iu6_t0_i0_t1_p; + assign frn_fdis_iu6_i0_t2_v[0] = frn_fdis_iu6_t0_i0_t2_v; + assign frn_fdis_iu6_i0_t2_a[0] = frn_fdis_iu6_t0_i0_t2_a; + assign frn_fdis_iu6_i0_t2_p[0] = frn_fdis_iu6_t0_i0_t2_p; + assign frn_fdis_iu6_i0_t2_t[0] = frn_fdis_iu6_t0_i0_t2_t; + assign frn_fdis_iu6_i0_t3_v[0] = frn_fdis_iu6_t0_i0_t3_v; + assign frn_fdis_iu6_i0_t3_a[0] = frn_fdis_iu6_t0_i0_t3_a; + assign frn_fdis_iu6_i0_t3_p[0] = frn_fdis_iu6_t0_i0_t3_p; + assign frn_fdis_iu6_i0_t3_t[0] = frn_fdis_iu6_t0_i0_t3_t; + assign frn_fdis_iu6_i0_s1_v[0] = frn_fdis_iu6_t0_i0_s1_v; + assign frn_fdis_iu6_i0_s1_a[0] = frn_fdis_iu6_t0_i0_s1_a; + assign frn_fdis_iu6_i0_s1_p[0] = frn_fdis_iu6_t0_i0_s1_p; + assign frn_fdis_iu6_i0_s1_itag[0] = frn_fdis_iu6_t0_i0_s1_itag; + assign frn_fdis_iu6_i0_s1_t[0] = frn_fdis_iu6_t0_i0_s1_t; + assign frn_fdis_iu6_i0_s2_v[0] = frn_fdis_iu6_t0_i0_s2_v; + assign frn_fdis_iu6_i0_s2_a[0] = frn_fdis_iu6_t0_i0_s2_a; + assign frn_fdis_iu6_i0_s2_p[0] = frn_fdis_iu6_t0_i0_s2_p; + assign frn_fdis_iu6_i0_s2_itag[0] = frn_fdis_iu6_t0_i0_s2_itag; + assign frn_fdis_iu6_i0_s2_t[0] = frn_fdis_iu6_t0_i0_s2_t; + assign frn_fdis_iu6_i0_s3_v[0] = frn_fdis_iu6_t0_i0_s3_v; + assign frn_fdis_iu6_i0_s3_a[0] = frn_fdis_iu6_t0_i0_s3_a; + assign frn_fdis_iu6_i0_s3_p[0] = frn_fdis_iu6_t0_i0_s3_p; + assign frn_fdis_iu6_i0_s3_itag[0] = frn_fdis_iu6_t0_i0_s3_itag; + assign frn_fdis_iu6_i0_s3_t[0] = frn_fdis_iu6_t0_i0_s3_t; + + assign frn_fdis_iu6_i1_vld[0] = frn_fdis_iu6_t0_i1_vld; + assign frn_fdis_iu6_i1_itag[0] = frn_fdis_iu6_t0_i1_itag; + assign frn_fdis_iu6_i1_ucode[0] = frn_fdis_iu6_t0_i1_ucode; + assign frn_fdis_iu6_i1_ucode_cnt[0] = frn_fdis_iu6_t0_i1_ucode_cnt; + assign frn_fdis_iu6_i1_fuse_nop[0] = frn_fdis_iu6_t0_i1_fuse_nop; + assign frn_fdis_iu6_i1_rte_lq[0] = frn_fdis_iu6_t0_i1_rte_lq; + assign frn_fdis_iu6_i1_rte_sq[0] = frn_fdis_iu6_t0_i1_rte_sq; + assign frn_fdis_iu6_i1_rte_fx0[0] = frn_fdis_iu6_t0_i1_rte_fx0; + assign frn_fdis_iu6_i1_rte_fx1[0] = frn_fdis_iu6_t0_i1_rte_fx1; + assign frn_fdis_iu6_i1_rte_axu0[0] = frn_fdis_iu6_t0_i1_rte_axu0; + assign frn_fdis_iu6_i1_rte_axu1[0] = frn_fdis_iu6_t0_i1_rte_axu1; + assign frn_fdis_iu6_i1_valop[0] = frn_fdis_iu6_t0_i1_valop; + assign frn_fdis_iu6_i1_ord[0] = frn_fdis_iu6_t0_i1_ord; + assign frn_fdis_iu6_i1_cord[0] = frn_fdis_iu6_t0_i1_cord; + assign frn_fdis_iu6_i1_error[0] = frn_fdis_iu6_t0_i1_error; + assign frn_fdis_iu6_i1_btb_entry[0] = frn_fdis_iu6_t0_i1_btb_entry; + assign frn_fdis_iu6_i1_btb_hist[0] = frn_fdis_iu6_t0_i1_btb_hist; + assign frn_fdis_iu6_i1_bta_val[0] = frn_fdis_iu6_t0_i1_bta_val; + assign frn_fdis_iu6_i1_fusion[0] = frn_fdis_iu6_t0_i1_fusion; + assign frn_fdis_iu6_i1_spec[0] = frn_fdis_iu6_t0_i1_spec; + assign frn_fdis_iu6_i1_type_fp[0] = frn_fdis_iu6_t0_i1_type_fp; + assign frn_fdis_iu6_i1_type_ap[0] = frn_fdis_iu6_t0_i1_type_ap; + assign frn_fdis_iu6_i1_type_spv[0] = frn_fdis_iu6_t0_i1_type_spv; + assign frn_fdis_iu6_i1_type_st[0] = frn_fdis_iu6_t0_i1_type_st; + assign frn_fdis_iu6_i1_async_block[0] = frn_fdis_iu6_t0_i1_async_block; + assign frn_fdis_iu6_i1_np1_flush[0] = frn_fdis_iu6_t0_i1_np1_flush; + assign frn_fdis_iu6_i1_core_block[0] = frn_fdis_iu6_t0_i1_core_block; + assign frn_fdis_iu6_i1_isram[0] = frn_fdis_iu6_t0_i1_isram; + assign frn_fdis_iu6_i1_isload[0] = frn_fdis_iu6_t0_i1_isload; + assign frn_fdis_iu6_i1_isstore[0] = frn_fdis_iu6_t0_i1_isstore; + assign frn_fdis_iu6_i1_instr[0] = frn_fdis_iu6_t0_i1_instr; + assign frn_fdis_iu6_i1_ifar[0] = frn_fdis_iu6_t0_i1_ifar; + assign frn_fdis_iu6_i1_bta[0] = frn_fdis_iu6_t0_i1_bta; + assign frn_fdis_iu6_i1_br_pred[0] = frn_fdis_iu6_t0_i1_br_pred; + assign frn_fdis_iu6_i1_bh_update[0] = frn_fdis_iu6_t0_i1_bh_update; + assign frn_fdis_iu6_i1_bh0_hist[0] = frn_fdis_iu6_t0_i1_bh0_hist; + assign frn_fdis_iu6_i1_bh1_hist[0] = frn_fdis_iu6_t0_i1_bh1_hist; + assign frn_fdis_iu6_i1_bh2_hist[0] = frn_fdis_iu6_t0_i1_bh2_hist; + assign frn_fdis_iu6_i1_gshare[0] = frn_fdis_iu6_t0_i1_gshare; + assign frn_fdis_iu6_i1_ls_ptr[0] = frn_fdis_iu6_t0_i1_ls_ptr; + assign frn_fdis_iu6_i1_match[0] = frn_fdis_iu6_t0_i1_match; + assign frn_fdis_iu6_i1_ilat[0] = frn_fdis_iu6_t0_i1_ilat; + assign frn_fdis_iu6_i1_t1_v[0] = frn_fdis_iu6_t0_i1_t1_v; + assign frn_fdis_iu6_i1_t1_t[0] = frn_fdis_iu6_t0_i1_t1_t; + assign frn_fdis_iu6_i1_t1_a[0] = frn_fdis_iu6_t0_i1_t1_a; + assign frn_fdis_iu6_i1_t1_p[0] = frn_fdis_iu6_t0_i1_t1_p; + assign frn_fdis_iu6_i1_t2_v[0] = frn_fdis_iu6_t0_i1_t2_v; + assign frn_fdis_iu6_i1_t2_a[0] = frn_fdis_iu6_t0_i1_t2_a; + assign frn_fdis_iu6_i1_t2_p[0] = frn_fdis_iu6_t0_i1_t2_p; + assign frn_fdis_iu6_i1_t2_t[0] = frn_fdis_iu6_t0_i1_t2_t; + assign frn_fdis_iu6_i1_t3_v[0] = frn_fdis_iu6_t0_i1_t3_v; + assign frn_fdis_iu6_i1_t3_a[0] = frn_fdis_iu6_t0_i1_t3_a; + assign frn_fdis_iu6_i1_t3_p[0] = frn_fdis_iu6_t0_i1_t3_p; + assign frn_fdis_iu6_i1_t3_t[0] = frn_fdis_iu6_t0_i1_t3_t; + assign frn_fdis_iu6_i1_s1_v[0] = frn_fdis_iu6_t0_i1_s1_v; + assign frn_fdis_iu6_i1_s1_a[0] = frn_fdis_iu6_t0_i1_s1_a; + assign frn_fdis_iu6_i1_s1_p[0] = frn_fdis_iu6_t0_i1_s1_p; + assign frn_fdis_iu6_i1_s1_itag[0] = frn_fdis_iu6_t0_i1_s1_itag; + assign frn_fdis_iu6_i1_s1_t[0] = frn_fdis_iu6_t0_i1_s1_t; + assign frn_fdis_iu6_i1_s1_dep_hit[0] = frn_fdis_iu6_t0_i1_s1_dep_hit; + assign frn_fdis_iu6_i1_s2_v[0] = frn_fdis_iu6_t0_i1_s2_v; + assign frn_fdis_iu6_i1_s2_a[0] = frn_fdis_iu6_t0_i1_s2_a; + assign frn_fdis_iu6_i1_s2_p[0] = frn_fdis_iu6_t0_i1_s2_p; + assign frn_fdis_iu6_i1_s2_itag[0] = frn_fdis_iu6_t0_i1_s2_itag; + assign frn_fdis_iu6_i1_s2_t[0] = frn_fdis_iu6_t0_i1_s2_t; + assign frn_fdis_iu6_i1_s2_dep_hit[0] = frn_fdis_iu6_t0_i1_s2_dep_hit; + assign frn_fdis_iu6_i1_s3_v[0] = frn_fdis_iu6_t0_i1_s3_v; + assign frn_fdis_iu6_i1_s3_a[0] = frn_fdis_iu6_t0_i1_s3_a; + assign frn_fdis_iu6_i1_s3_p[0] = frn_fdis_iu6_t0_i1_s3_p; + assign frn_fdis_iu6_i1_s3_itag[0] = frn_fdis_iu6_t0_i1_s3_itag; + assign frn_fdis_iu6_i1_s3_t[0] = frn_fdis_iu6_t0_i1_s3_t; + assign frn_fdis_iu6_i1_s3_dep_hit[0] = frn_fdis_iu6_t0_i1_s3_dep_hit; + +`ifndef THREADS1 + assign frn_fdis_iu6_i0_vld[1] = frn_fdis_iu6_t1_i0_vld; + assign frn_fdis_iu6_i0_itag[1] = frn_fdis_iu6_t1_i0_itag; + assign frn_fdis_iu6_i0_ucode[1] = frn_fdis_iu6_t1_i0_ucode; + assign frn_fdis_iu6_i0_ucode_cnt[1] = frn_fdis_iu6_t1_i0_ucode_cnt; + assign frn_fdis_iu6_i0_2ucode[1] = frn_fdis_iu6_t1_i0_2ucode; + assign frn_fdis_iu6_i0_fuse_nop[1] = frn_fdis_iu6_t1_i0_fuse_nop; + assign frn_fdis_iu6_i0_rte_lq[1] = frn_fdis_iu6_t1_i0_rte_lq; + assign frn_fdis_iu6_i0_rte_sq[1] = frn_fdis_iu6_t1_i0_rte_sq; + assign frn_fdis_iu6_i0_rte_fx0[1] = frn_fdis_iu6_t1_i0_rte_fx0; + assign frn_fdis_iu6_i0_rte_fx1[1] = frn_fdis_iu6_t1_i0_rte_fx1; + assign frn_fdis_iu6_i0_rte_axu0[1] = frn_fdis_iu6_t1_i0_rte_axu0; + assign frn_fdis_iu6_i0_rte_axu1[1] = frn_fdis_iu6_t1_i0_rte_axu1; + assign frn_fdis_iu6_i0_valop[1] = frn_fdis_iu6_t1_i0_valop; + assign frn_fdis_iu6_i0_ord[1] = frn_fdis_iu6_t1_i0_ord; + assign frn_fdis_iu6_i0_cord[1] = frn_fdis_iu6_t1_i0_cord; + assign frn_fdis_iu6_i0_error[1] = frn_fdis_iu6_t1_i0_error; + assign frn_fdis_iu6_i0_btb_entry[1] = frn_fdis_iu6_t1_i0_btb_entry; + assign frn_fdis_iu6_i0_btb_hist[1] = frn_fdis_iu6_t1_i0_btb_hist; + assign frn_fdis_iu6_i0_bta_val[1] = frn_fdis_iu6_t1_i0_bta_val; + assign frn_fdis_iu6_i0_fusion[1] = frn_fdis_iu6_t1_i0_fusion; + assign frn_fdis_iu6_i0_spec[1] = frn_fdis_iu6_t1_i0_spec; + assign frn_fdis_iu6_i0_type_fp[1] = frn_fdis_iu6_t1_i0_type_fp; + assign frn_fdis_iu6_i0_type_ap[1] = frn_fdis_iu6_t1_i0_type_ap; + assign frn_fdis_iu6_i0_type_spv[1] = frn_fdis_iu6_t1_i0_type_spv; + assign frn_fdis_iu6_i0_type_st[1] = frn_fdis_iu6_t1_i0_type_st; + assign frn_fdis_iu6_i0_async_block[1] = frn_fdis_iu6_t1_i0_async_block; + assign frn_fdis_iu6_i0_np1_flush[1] = frn_fdis_iu6_t1_i0_np1_flush; + assign frn_fdis_iu6_i0_core_block[1] = frn_fdis_iu6_t1_i0_core_block; + assign frn_fdis_iu6_i0_isram[1] = frn_fdis_iu6_t1_i0_isram; + assign frn_fdis_iu6_i0_isload[1] = frn_fdis_iu6_t1_i0_isload; + assign frn_fdis_iu6_i0_isstore[1] = frn_fdis_iu6_t1_i0_isstore; + assign frn_fdis_iu6_i0_instr[1] = frn_fdis_iu6_t1_i0_instr; + assign frn_fdis_iu6_i0_ifar[1] = frn_fdis_iu6_t1_i0_ifar; + assign frn_fdis_iu6_i0_bta[1] = frn_fdis_iu6_t1_i0_bta; + assign frn_fdis_iu6_i0_br_pred[1] = frn_fdis_iu6_t1_i0_br_pred; + assign frn_fdis_iu6_i0_bh_update[1] = frn_fdis_iu6_t1_i0_bh_update; + assign frn_fdis_iu6_i0_bh0_hist[1] = frn_fdis_iu6_t1_i0_bh0_hist; + assign frn_fdis_iu6_i0_bh1_hist[1] = frn_fdis_iu6_t1_i0_bh1_hist; + assign frn_fdis_iu6_i0_bh2_hist[1] = frn_fdis_iu6_t1_i0_bh2_hist; + assign frn_fdis_iu6_i0_gshare[1] = frn_fdis_iu6_t1_i0_gshare; + assign frn_fdis_iu6_i0_ls_ptr[1] = frn_fdis_iu6_t1_i0_ls_ptr; + assign frn_fdis_iu6_i0_match[1] = frn_fdis_iu6_t1_i0_match; + assign frn_fdis_iu6_i0_ilat[1] = frn_fdis_iu6_t1_i0_ilat; + assign frn_fdis_iu6_i0_t1_v[1] = frn_fdis_iu6_t1_i0_t1_v; + assign frn_fdis_iu6_i0_t1_t[1] = frn_fdis_iu6_t1_i0_t1_t; + assign frn_fdis_iu6_i0_t1_a[1] = frn_fdis_iu6_t1_i0_t1_a; + assign frn_fdis_iu6_i0_t1_p[1] = frn_fdis_iu6_t1_i0_t1_p; + assign frn_fdis_iu6_i0_t2_v[1] = frn_fdis_iu6_t1_i0_t2_v; + assign frn_fdis_iu6_i0_t2_a[1] = frn_fdis_iu6_t1_i0_t2_a; + assign frn_fdis_iu6_i0_t2_p[1] = frn_fdis_iu6_t1_i0_t2_p; + assign frn_fdis_iu6_i0_t2_t[1] = frn_fdis_iu6_t1_i0_t2_t; + assign frn_fdis_iu6_i0_t3_v[1] = frn_fdis_iu6_t1_i0_t3_v; + assign frn_fdis_iu6_i0_t3_a[1] = frn_fdis_iu6_t1_i0_t3_a; + assign frn_fdis_iu6_i0_t3_p[1] = frn_fdis_iu6_t1_i0_t3_p; + assign frn_fdis_iu6_i0_t3_t[1] = frn_fdis_iu6_t1_i0_t3_t; + assign frn_fdis_iu6_i0_s1_v[1] = frn_fdis_iu6_t1_i0_s1_v; + assign frn_fdis_iu6_i0_s1_a[1] = frn_fdis_iu6_t1_i0_s1_a; + assign frn_fdis_iu6_i0_s1_p[1] = frn_fdis_iu6_t1_i0_s1_p; + assign frn_fdis_iu6_i0_s1_itag[1] = frn_fdis_iu6_t1_i0_s1_itag; + assign frn_fdis_iu6_i0_s1_t[1] = frn_fdis_iu6_t1_i0_s1_t; + assign frn_fdis_iu6_i0_s2_v[1] = frn_fdis_iu6_t1_i0_s2_v; + assign frn_fdis_iu6_i0_s2_a[1] = frn_fdis_iu6_t1_i0_s2_a; + assign frn_fdis_iu6_i0_s2_p[1] = frn_fdis_iu6_t1_i0_s2_p; + assign frn_fdis_iu6_i0_s2_itag[1] = frn_fdis_iu6_t1_i0_s2_itag; + assign frn_fdis_iu6_i0_s2_t[1] = frn_fdis_iu6_t1_i0_s2_t; + assign frn_fdis_iu6_i0_s3_v[1] = frn_fdis_iu6_t1_i0_s3_v; + assign frn_fdis_iu6_i0_s3_a[1] = frn_fdis_iu6_t1_i0_s3_a; + assign frn_fdis_iu6_i0_s3_p[1] = frn_fdis_iu6_t1_i0_s3_p; + assign frn_fdis_iu6_i0_s3_itag[1] = frn_fdis_iu6_t1_i0_s3_itag; + assign frn_fdis_iu6_i0_s3_t[1] = frn_fdis_iu6_t1_i0_s3_t; + + assign frn_fdis_iu6_i1_vld[1] = frn_fdis_iu6_t1_i1_vld; + assign frn_fdis_iu6_i1_itag[1] = frn_fdis_iu6_t1_i1_itag; + assign frn_fdis_iu6_i1_ucode[1] = frn_fdis_iu6_t1_i1_ucode; + assign frn_fdis_iu6_i1_ucode_cnt[1] = frn_fdis_iu6_t1_i1_ucode_cnt; + assign frn_fdis_iu6_i1_fuse_nop[1] = frn_fdis_iu6_t1_i1_fuse_nop; + assign frn_fdis_iu6_i1_rte_lq[1] = frn_fdis_iu6_t1_i1_rte_lq; + assign frn_fdis_iu6_i1_rte_sq[1] = frn_fdis_iu6_t1_i1_rte_sq; + assign frn_fdis_iu6_i1_rte_fx0[1] = frn_fdis_iu6_t1_i1_rte_fx0; + assign frn_fdis_iu6_i1_rte_fx1[1] = frn_fdis_iu6_t1_i1_rte_fx1; + assign frn_fdis_iu6_i1_rte_axu0[1] = frn_fdis_iu6_t1_i1_rte_axu0; + assign frn_fdis_iu6_i1_rte_axu1[1] = frn_fdis_iu6_t1_i1_rte_axu1; + assign frn_fdis_iu6_i1_valop[1] = frn_fdis_iu6_t1_i1_valop; + assign frn_fdis_iu6_i1_ord[1] = frn_fdis_iu6_t1_i1_ord; + assign frn_fdis_iu6_i1_cord[1] = frn_fdis_iu6_t1_i1_cord; + assign frn_fdis_iu6_i1_error[1] = frn_fdis_iu6_t1_i1_error; + assign frn_fdis_iu6_i1_btb_entry[1] = frn_fdis_iu6_t1_i1_btb_entry; + assign frn_fdis_iu6_i1_btb_hist[1] = frn_fdis_iu6_t1_i1_btb_hist; + assign frn_fdis_iu6_i1_bta_val[1] = frn_fdis_iu6_t1_i1_bta_val; + assign frn_fdis_iu6_i1_fusion[1] = frn_fdis_iu6_t1_i1_fusion; + assign frn_fdis_iu6_i1_spec[1] = frn_fdis_iu6_t1_i1_spec; + assign frn_fdis_iu6_i1_type_fp[1] = frn_fdis_iu6_t1_i1_type_fp; + assign frn_fdis_iu6_i1_type_ap[1] = frn_fdis_iu6_t1_i1_type_ap; + assign frn_fdis_iu6_i1_type_spv[1] = frn_fdis_iu6_t1_i1_type_spv; + assign frn_fdis_iu6_i1_type_st[1] = frn_fdis_iu6_t1_i1_type_st; + assign frn_fdis_iu6_i1_async_block[1] = frn_fdis_iu6_t1_i1_async_block; + assign frn_fdis_iu6_i1_np1_flush[1] = frn_fdis_iu6_t1_i1_np1_flush; + assign frn_fdis_iu6_i1_core_block[1] = frn_fdis_iu6_t1_i1_core_block; + assign frn_fdis_iu6_i1_isram[1] = frn_fdis_iu6_t1_i1_isram; + assign frn_fdis_iu6_i1_isload[1] = frn_fdis_iu6_t1_i1_isload; + assign frn_fdis_iu6_i1_isstore[1] = frn_fdis_iu6_t1_i1_isstore; + assign frn_fdis_iu6_i1_instr[1] = frn_fdis_iu6_t1_i1_instr; + assign frn_fdis_iu6_i1_ifar[1] = frn_fdis_iu6_t1_i1_ifar; + assign frn_fdis_iu6_i1_bta[1] = frn_fdis_iu6_t1_i1_bta; + assign frn_fdis_iu6_i1_br_pred[1] = frn_fdis_iu6_t1_i1_br_pred; + assign frn_fdis_iu6_i1_bh_update[1] = frn_fdis_iu6_t1_i1_bh_update; + assign frn_fdis_iu6_i1_bh0_hist[1] = frn_fdis_iu6_t1_i1_bh0_hist; + assign frn_fdis_iu6_i1_bh1_hist[1] = frn_fdis_iu6_t1_i1_bh1_hist; + assign frn_fdis_iu6_i1_bh2_hist[1] = frn_fdis_iu6_t1_i1_bh2_hist; + assign frn_fdis_iu6_i1_gshare[1] = frn_fdis_iu6_t1_i1_gshare; + assign frn_fdis_iu6_i1_ls_ptr[1] = frn_fdis_iu6_t1_i1_ls_ptr; + assign frn_fdis_iu6_i1_match[1] = frn_fdis_iu6_t1_i1_match; + assign frn_fdis_iu6_i1_ilat[1] = frn_fdis_iu6_t1_i1_ilat; + assign frn_fdis_iu6_i1_t1_v[1] = frn_fdis_iu6_t1_i1_t1_v; + assign frn_fdis_iu6_i1_t1_t[1] = frn_fdis_iu6_t1_i1_t1_t; + assign frn_fdis_iu6_i1_t1_a[1] = frn_fdis_iu6_t1_i1_t1_a; + assign frn_fdis_iu6_i1_t1_p[1] = frn_fdis_iu6_t1_i1_t1_p; + assign frn_fdis_iu6_i1_t2_v[1] = frn_fdis_iu6_t1_i1_t2_v; + assign frn_fdis_iu6_i1_t2_a[1] = frn_fdis_iu6_t1_i1_t2_a; + assign frn_fdis_iu6_i1_t2_p[1] = frn_fdis_iu6_t1_i1_t2_p; + assign frn_fdis_iu6_i1_t2_t[1] = frn_fdis_iu6_t1_i1_t2_t; + assign frn_fdis_iu6_i1_t3_v[1] = frn_fdis_iu6_t1_i1_t3_v; + assign frn_fdis_iu6_i1_t3_a[1] = frn_fdis_iu6_t1_i1_t3_a; + assign frn_fdis_iu6_i1_t3_p[1] = frn_fdis_iu6_t1_i1_t3_p; + assign frn_fdis_iu6_i1_t3_t[1] = frn_fdis_iu6_t1_i1_t3_t; + assign frn_fdis_iu6_i1_s1_v[1] = frn_fdis_iu6_t1_i1_s1_v; + assign frn_fdis_iu6_i1_s1_a[1] = frn_fdis_iu6_t1_i1_s1_a; + assign frn_fdis_iu6_i1_s1_p[1] = frn_fdis_iu6_t1_i1_s1_p; + assign frn_fdis_iu6_i1_s1_itag[1] = frn_fdis_iu6_t1_i1_s1_itag; + assign frn_fdis_iu6_i1_s1_t[1] = frn_fdis_iu6_t1_i1_s1_t; + assign frn_fdis_iu6_i1_s1_dep_hit[1] = frn_fdis_iu6_t1_i1_s1_dep_hit; + assign frn_fdis_iu6_i1_s2_v[1] = frn_fdis_iu6_t1_i1_s2_v; + assign frn_fdis_iu6_i1_s2_a[1] = frn_fdis_iu6_t1_i1_s2_a; + assign frn_fdis_iu6_i1_s2_p[1] = frn_fdis_iu6_t1_i1_s2_p; + assign frn_fdis_iu6_i1_s2_itag[1] = frn_fdis_iu6_t1_i1_s2_itag; + assign frn_fdis_iu6_i1_s2_t[1] = frn_fdis_iu6_t1_i1_s2_t; + assign frn_fdis_iu6_i1_s2_dep_hit[1] = frn_fdis_iu6_t1_i1_s2_dep_hit; + assign frn_fdis_iu6_i1_s3_v[1] = frn_fdis_iu6_t1_i1_s3_v; + assign frn_fdis_iu6_i1_s3_a[1] = frn_fdis_iu6_t1_i1_s3_a; + assign frn_fdis_iu6_i1_s3_p[1] = frn_fdis_iu6_t1_i1_s3_p; + assign frn_fdis_iu6_i1_s3_itag[1] = frn_fdis_iu6_t1_i1_s3_itag; + assign frn_fdis_iu6_i1_s3_t[1] = frn_fdis_iu6_t1_i1_s3_t; + assign frn_fdis_iu6_i1_s3_dep_hit[1] = frn_fdis_iu6_t1_i1_s3_dep_hit; +`endif + + + assign tiup = 1'b1; + + assign dp_cp_hold_req = (mm_iu_flush_req_l2 & ~(in_ucode_l2 | in_fusion_l2)); + assign dp_cp_bus_snoop_hold_req = (mm_iu_bus_snoop_hold_req_l2 & ~(in_ucode_l2 | in_fusion_l2)); + assign mm_iu_flush_req_d = mm_iu_flush_req | (mm_iu_flush_req_l2 & (in_ucode_l2 | in_fusion_l2)); + assign mm_iu_bus_snoop_hold_req_d = mm_iu_bus_snoop_hold_req | (mm_iu_bus_snoop_hold_req_l2 & (in_ucode_l2 | in_fusion_l2)); + + // Added logic for Erat invalidates to stop dispatch + generate + begin : xhdl1 + genvar i; + for (i = 0; i <= `THREADS - 1; i = i + 1) + begin : send_cnt + //IN V0 12 V1 12 | IN + // - 1 1- 0 -- | 1 + // - - -- 1 1- | 1 + // - 1 -1 0 -- | 0 + // - - -- 1 -1 | 0 + assign in_ucode_d[i] = (cp_flush_l2[i] == 1'b1) ? 1'b0 : + (iu_rv_iu6_i0_vld_int[i] == 1'b1 & frn_fdis_iu6_i0_ucode[i][1] == 1'b1 & iu_rv_iu6_i1_vld_int[i] == 1'b0) ? 1'b1 : + (iu_rv_iu6_i1_vld_int[i] == 1'b1 & frn_fdis_iu6_i1_ucode[i][1] == 1'b1) ? 1'b1 : + (iu_rv_iu6_i0_vld_int[i] == 1'b1 & frn_fdis_iu6_i0_ucode[i][2] == 1'b1 & iu_rv_iu6_i1_vld_int[i] == 1'b0) ? 1'b0 : + (iu_rv_iu6_i1_vld_int[i] == 1'b1 & frn_fdis_iu6_i1_ucode[i][2] == 1'b1) ? 1'b0 : + in_ucode_l2[i]; + + //IN V0 F V1 F | IN + // - 1 1 0 - | 1 + // - - - 1 1 | 1 + // - 1 0 0 - | 0 + // - - - 1 0 | 0 + assign in_fusion_d[i] = (cp_flush_l2[i] == 1'b1) ? 1'b0 : + (iu_rv_iu6_i0_vld_int[i] == 1'b1 & frn_fdis_iu6_i0_fuse_nop[i] == 1'b1 & iu_rv_iu6_i1_vld_int[i] == 1'b0) ? 1'b1 : + (iu_rv_iu6_i1_vld_int[i] == 1'b1 & frn_fdis_iu6_i1_fuse_nop[i] == 1'b1) ? 1'b1 : + (iu_rv_iu6_i0_vld_int[i] == 1'b1 & frn_fdis_iu6_i0_fuse_nop[i] == 1'b0 & iu_rv_iu6_i1_vld_int[i] == 1'b0) ? 1'b0 : + (iu_rv_iu6_i1_vld_int[i] == 1'b1 & frn_fdis_iu6_i1_fuse_nop[i] == 1'b0) ? 1'b0 : + in_fusion_l2[i]; + + assign mm_hold_req_d[i] = (mm_iu_flush_req_l2[i] & ~(in_ucode_l2[i] | in_fusion_l2[i])) | + (mm_hold_req_l2[i] & ~mm_hold_done_l2[i]); + + assign mm_hold_done_d[i] = mm_iu_hold_done_l2[i]; + + assign mm_bus_snoop_hold_req_d[i] = (mm_iu_bus_snoop_hold_req_l2[i] & ~(in_ucode_l2[i] | in_fusion_l2[i])) | + (mm_bus_snoop_hold_req_l2[i] & ~mm_bus_snoop_hold_done_l2[i]); + + assign mm_bus_snoop_hold_done_d[i] = mm_iu_bus_snoop_hold_done_l2[i]; + + assign hold_req_d[i] = (send_instructions[i] & core_block[i]) | + (hold_req_l2[i] & ~hold_done_l2[i]); + + assign hold_done_d[i] = cp_flush_l2[i]; + + assign ivax_hold_req_d[i] = (cp_dis_ivax[i]) | + (ivax_hold_req_l2[i] & ~mm_iu_tlbi_complete[i]); + + assign fx0_send_cnt[i] = {(frn_fdis_iu6_i0_rte_fx0[i] & (~frn_fdis_iu6_i0_rte_fx1[i] | dual_issue_use_fx0_l2[0])), + (frn_fdis_iu6_i1_rte_fx0[i] & (~frn_fdis_iu6_i1_rte_fx1[i] | dual_issue_use_fx0_l2[1]))}; + + assign fx1_send_cnt[i] = {(frn_fdis_iu6_i0_rte_fx1[i] & (~frn_fdis_iu6_i0_rte_fx0[i] | ~dual_issue_use_fx0_l2[0])), + (frn_fdis_iu6_i1_rte_fx1[i] & (~frn_fdis_iu6_i1_rte_fx0[i] | ~dual_issue_use_fx0_l2[1]))}; + + assign lq_cmdq_send_cnt[i] = {frn_fdis_iu6_i0_rte_lq[i], frn_fdis_iu6_i1_rte_lq[i]}; + + assign sq_cmdq_send_cnt[i] = {frn_fdis_iu6_i0_rte_sq[i], frn_fdis_iu6_i1_rte_sq[i]}; + + assign fu0_send_cnt[i] = {(frn_fdis_iu6_i0_rte_axu0[i] & ~(frn_fdis_iu6_i0_rte_lq[i] & frn_fdis_iu6_i0_isload[i])), + (frn_fdis_iu6_i1_rte_axu0[i] & ~(frn_fdis_iu6_i1_rte_lq[i] & frn_fdis_iu6_i1_isload[i]))}; + + assign fu1_send_cnt[i] = {(frn_fdis_iu6_i0_rte_axu1[i] & ~(frn_fdis_iu6_i0_rte_lq[i] & frn_fdis_iu6_i0_isload[i])), + (frn_fdis_iu6_i1_rte_axu1[i] & ~(frn_fdis_iu6_i1_rte_lq[i] & frn_fdis_iu6_i1_isload[i]))}; + + assign core_block[i] = (frn_fdis_iu6_i0_core_block[i] | frn_fdis_iu6_i1_core_block[i]); + end + end + endgenerate + + generate + begin : primux + genvar i; + for (i = 0; i <= `THREADS - 1; i = i + 1) + begin : credit_mux + assign fx0_credit_cnt_mux[i] = ({5{total_pri_mask_l2[i]}} & fx0_total_credit_cnt_l2) | + ({5{high_pri_mask_l2[i]}} & fx0_high_credit_cnt_l2[i]) | + ({5{med_pri_mask_l2[i]}} & fx0_med_credit_cnt_l2[i]); + + assign fx1_credit_cnt_mux[i] = ({5{total_pri_mask_l2[i]}} & fx1_total_credit_cnt_l2) | + ({5{high_pri_mask_l2[i]}} & fx1_high_credit_cnt_l2[i]) | + ({5{med_pri_mask_l2[i]}} & fx1_med_credit_cnt_l2[i]); + + assign lq_cmdq_credit_cnt_mux[i] = ({5{total_pri_mask_l2[i]}} & lq_cmdq_total_credit_cnt_l2) | + ({5{high_pri_mask_l2[i]}} & lq_cmdq_high_credit_cnt_l2[i]) | + ({5{med_pri_mask_l2[i]}} & lq_cmdq_med_credit_cnt_l2[i]); + + assign sq_cmdq_credit_cnt_mux[i] = ({5{total_pri_mask_l2[i]}} & sq_cmdq_total_credit_cnt_l2) | + ({5{high_pri_mask_l2[i]}} & sq_cmdq_high_credit_cnt_l2[i]) | + ({5{med_pri_mask_l2[i]}} & sq_cmdq_med_credit_cnt_l2[i]); + + assign fu0_credit_cnt_mux[i] = ({5{total_pri_mask_l2[i]}} & fu0_total_credit_cnt_l2) | + ({5{high_pri_mask_l2[i]}} & fu0_high_credit_cnt_l2[i]) | + ({5{med_pri_mask_l2[i]}} & fu0_med_credit_cnt_l2[i]); + + assign fu1_credit_cnt_mux[i] = ({5{total_pri_mask_l2[i]}} & fu1_total_credit_cnt_l2) | + ({5{high_pri_mask_l2[i]}} & fu1_high_credit_cnt_l2[i]) | + ({5{med_pri_mask_l2[i]}} & fu1_med_credit_cnt_l2[i]); + end + end + endgenerate + +`ifdef THREADS1 + // Checking to make sure we aren't in ucode so we can issue a core blocker + assign core_block_ok[0] = 1'b1; +`endif +`ifndef THREADS1 + assign core_block_ok[0] = ~(core_block[0] & (in_ucode_l2[1] | in_fusion_l2[1])); + assign core_block_ok[1] = ~(core_block[1] & (in_ucode_l2[0] | in_fusion_l2[0])); +`endif + +tri_nor2 fx0_send_cnt_t0_zero(fx0_send_cnt_zero[0], fx0_send_cnt[0][0], fx0_send_cnt[0][1]); +tri_xor2 fx0_send_cnt_t0_one (fx0_send_cnt_one[0], fx0_send_cnt[0][0], fx0_send_cnt[0][1]); +tri_nor2 fx1_send_cnt_t0_zero(fx1_send_cnt_zero[0], fx1_send_cnt[0][0], fx1_send_cnt[0][1]); +tri_xor2 fx1_send_cnt_t0_one (fx1_send_cnt_one[0], fx1_send_cnt[0][0], fx1_send_cnt[0][1]); +tri_nor2 fu0_send_cnt_t0_zero(fu0_send_cnt_zero[0], fu0_send_cnt[0][0], fu0_send_cnt[0][1]); +tri_xor2 fu0_send_cnt_t0_one (fu0_send_cnt_one[0], fu0_send_cnt[0][0], fu0_send_cnt[0][1]); +tri_nor2 fu1_send_cnt_t0_zero(fu1_send_cnt_zero[0], fu1_send_cnt[0][0], fu1_send_cnt[0][1]); +tri_xor2 fu1_send_cnt_t0_one (fu1_send_cnt_one[0], fu1_send_cnt[0][0], fu1_send_cnt[0][1]); +tri_nor2 lq_cmdq_send_cnt_t0_zero(lq_cmdq_send_cnt_zero[0], lq_cmdq_send_cnt[0][0], lq_cmdq_send_cnt[0][1]); +tri_xor2 lq_cmdq_send_cnt_t0_one (lq_cmdq_send_cnt_one[0], lq_cmdq_send_cnt[0][0], lq_cmdq_send_cnt[0][1]); +tri_nor2 sq_cmdq_send_cnt_t0_zero(sq_cmdq_send_cnt_zero[0], sq_cmdq_send_cnt[0][0], sq_cmdq_send_cnt[0][1]); +tri_xor2 sq_cmdq_send_cnt_t0_one (sq_cmdq_send_cnt_one[0], sq_cmdq_send_cnt[0][0], sq_cmdq_send_cnt[0][1]); + +`ifndef THREADS1 +tri_nor2 fx0_send_cnt_t1_zero(fx0_send_cnt_zero[1], fx0_send_cnt[1][0], fx0_send_cnt[1][1]); +tri_xor2 fx0_send_cnt_t1_one (fx0_send_cnt_one[1], fx0_send_cnt[1][0], fx0_send_cnt[1][1]); +tri_nor2 fx1_send_cnt_t1_zero(fx1_send_cnt_zero[1], fx1_send_cnt[1][0], fx1_send_cnt[1][1]); +tri_xor2 fx1_send_cnt_t1_one (fx1_send_cnt_one[1], fx1_send_cnt[1][0], fx1_send_cnt[1][1]); +tri_nor2 fu0_send_cnt_t1_zero(fu0_send_cnt_zero[1], fu0_send_cnt[1][0], fu0_send_cnt[1][1]); +tri_xor2 fu0_send_cnt_t1_one (fu0_send_cnt_one[1], fu0_send_cnt[1][0], fu0_send_cnt[1][1]); +tri_nor2 fu1_send_cnt_t1_zero(fu1_send_cnt_zero[1], fu1_send_cnt[1][0], fu1_send_cnt[1][1]); +tri_xor2 fu1_send_cnt_t1_one (fu1_send_cnt_one[1], fu1_send_cnt[1][0], fu1_send_cnt[1][1]); +tri_nor2 lq_cmdq_send_cnt_t1_zero(lq_cmdq_send_cnt_zero[1], lq_cmdq_send_cnt[1][0], lq_cmdq_send_cnt[1][1]); +tri_xor2 lq_cmdq_send_cnt_t1_one (lq_cmdq_send_cnt_one[1], lq_cmdq_send_cnt[1][0], lq_cmdq_send_cnt[1][1]); +tri_nor2 sq_cmdq_send_cnt_t1_zero(sq_cmdq_send_cnt_zero[1], sq_cmdq_send_cnt[1][0], sq_cmdq_send_cnt[1][1]); +tri_xor2 sq_cmdq_send_cnt_t1_one (sq_cmdq_send_cnt_one[1], sq_cmdq_send_cnt[1][0], sq_cmdq_send_cnt[1][1]); +`endif + + generate + begin : xhdl2 + genvar i; + for (i = 0; i <= `THREADS - 1; i = i + 1) + begin : credit_ok + // Checking the credits allocated for each thread + assign fx0_local_credit_ok[i] = ((fx0_send_cnt_zero[i]) | + ((fx0_send_cnt_one[i]) & |fx0_credit_cnt_mux[i]) | + (|fx0_credit_cnt_mux[i][0:3])); + + assign fx1_local_credit_ok[i] = ((fx1_send_cnt_zero[i]) | + ((fx1_send_cnt_one[i]) & |fx1_credit_cnt_mux[i]) | + (|fx1_credit_cnt_mux[i][0:3])); + + assign lq_cmdq_local_credit_ok[i] = ((lq_cmdq_send_cnt_zero[i]) | + ((lq_cmdq_send_cnt_one[i]) & |lq_cmdq_credit_cnt_mux[i]) | + (|lq_cmdq_credit_cnt_mux[i][0:3])); + + assign sq_cmdq_local_credit_ok[i] = ((sq_cmdq_send_cnt_zero[i]) | + ((sq_cmdq_send_cnt_one[i]) & |sq_cmdq_credit_cnt_mux[i]) | + (|sq_cmdq_credit_cnt_mux[i][0:3])); + + assign fu0_local_credit_ok[i] = ((fu0_send_cnt_zero[i]) | + ((fu0_send_cnt_one[i]) & |fu0_credit_cnt_mux[i]) | + (|fu0_credit_cnt_mux[i][0:3])); + + assign fu1_local_credit_ok[i] = ((fu1_send_cnt_zero[i]) | + ((fu1_send_cnt_one[i]) & |fu1_credit_cnt_mux[i]) | + (|fu1_credit_cnt_mux[i][0:3])); + + // Checking total credits if only issuing each thread individually + assign fx0_credit_ok[i] = ((fx0_send_cnt_zero[i]) | + ((fx0_send_cnt_one[i]) & |fx0_total_credit_cnt_l2) | + (|fx0_total_credit_cnt_l2[0:3])); + + assign fx1_credit_ok[i] = ((fx1_send_cnt_zero[i]) | + ((fx1_send_cnt_one[i]) & |fx1_total_credit_cnt_l2) | + (|fx1_total_credit_cnt_l2[0:3])); + + assign lq_cmdq_credit_ok[i] = ((lq_cmdq_send_cnt_zero[i]) | + ((lq_cmdq_send_cnt_one[i]) & |lq_cmdq_total_credit_cnt_l2) | + (|lq_cmdq_total_credit_cnt_l2[0:3])); + + assign sq_cmdq_credit_ok[i] = ((sq_cmdq_send_cnt_zero[i]) | + ((sq_cmdq_send_cnt_one[i]) & |sq_cmdq_total_credit_cnt_l2) | + (|sq_cmdq_total_credit_cnt_l2[0:3])); + + assign fu0_credit_ok[i] = ((fu0_send_cnt_zero[i]) | + ((fu0_send_cnt_one[i]) & |fu0_total_credit_cnt_l2) | + (|fu0_total_credit_cnt_l2[0:3])); + + assign fu1_credit_ok[i] = ((fu1_send_cnt_zero[i]) | + ((fu1_send_cnt_one[i]) & |fu1_total_credit_cnt_l2) | + (|fu1_total_credit_cnt_l2[0:3])); + + end + end + endgenerate + + + + generate + if (`THREADS == 1) + begin : thread_gen_1 + assign fx0_both_credit_ok = 1'b0; + assign fx1_both_credit_ok = 1'b0; + assign lq_cmdq_both_credit_ok = 1'b0; + assign sq_cmdq_both_credit_ok = 1'b0; + assign fu0_both_credit_ok = 1'b0; + assign fu1_both_credit_ok = 1'b0; + end + endgenerate + + generate + if (`THREADS == 2) + begin : thread_gen_2 + assign fx0_both_credit_ok = (fx0_send_cnt_zero[0] & fx0_send_cnt_zero[1]) | + (((fx0_send_cnt_zero[0] & fx0_send_cnt_one[1] ) | (fx0_send_cnt_zero[1] & fx0_send_cnt_one[0])) & (~(fx0_total_credit_cnt_l2 == {5{1'b0}}))) | + (((fx0_send_cnt_zero[0] | fx0_send_cnt_zero[1]) | (fx0_send_cnt_one[0] & fx0_send_cnt_one[1])) & |fx0_total_credit_cnt_l2[0:3]); + + assign fx1_both_credit_ok = (fx1_send_cnt_zero[0] & fx1_send_cnt_zero[1]) | + (((fx1_send_cnt_zero[0] & fx1_send_cnt_one[1] ) | (fx1_send_cnt_zero[1] & fx1_send_cnt_one[0])) & (~(fx1_total_credit_cnt_l2 == {5{1'b0}}))) | + (((fx1_send_cnt_zero[0] | fx1_send_cnt_zero[1]) | (fx1_send_cnt_one[0] & fx1_send_cnt_one[1])) & |fx1_total_credit_cnt_l2[0:3]); + + assign lq_cmdq_both_credit_ok = (lq_cmdq_send_cnt_zero[0] & lq_cmdq_send_cnt_zero[1]) | + (((lq_cmdq_send_cnt_zero[0] & lq_cmdq_send_cnt_one[1] ) | (lq_cmdq_send_cnt_zero[1] & lq_cmdq_send_cnt_one[0])) & (~(lq_cmdq_total_credit_cnt_l2 == {5{1'b0}}))) | + (((lq_cmdq_send_cnt_zero[0] | lq_cmdq_send_cnt_zero[1]) | (lq_cmdq_send_cnt_one[0] & lq_cmdq_send_cnt_one[1])) & |lq_cmdq_total_credit_cnt_l2[0:3]); + + assign sq_cmdq_both_credit_ok = (sq_cmdq_send_cnt_zero[0] & sq_cmdq_send_cnt_zero[1]) | + (((sq_cmdq_send_cnt_zero[0] & sq_cmdq_send_cnt_one[1] ) | (sq_cmdq_send_cnt_zero[1] & sq_cmdq_send_cnt_one[0])) & (~(sq_cmdq_total_credit_cnt_l2 == {5{1'b0}}))) | + (((sq_cmdq_send_cnt_zero[0] | sq_cmdq_send_cnt_zero[1]) | (sq_cmdq_send_cnt_one[0] & sq_cmdq_send_cnt_one[1])) & |sq_cmdq_total_credit_cnt_l2[0:3]); + + + assign fu0_both_credit_ok = (fu0_send_cnt_zero[0] & fu0_send_cnt_zero[1]) | + (((fu0_send_cnt_zero[0] & fu0_send_cnt_one[1] ) | (fu0_send_cnt_zero[1] & fu0_send_cnt_one[0])) & (~(fu0_total_credit_cnt_l2 == {5{1'b0}}))) | + (((fu0_send_cnt_zero[0] | fu0_send_cnt_zero[1]) | (fu0_send_cnt_one[0] & fu0_send_cnt_one[1])) & |fu0_total_credit_cnt_l2[0:3]); + + assign fu1_both_credit_ok = (fu1_send_cnt_zero[0] & fu1_send_cnt_zero[1]) | + (((fu1_send_cnt_zero[0] & fu1_send_cnt_one[1] ) | (fu1_send_cnt_zero[1] & fu1_send_cnt_one[0])) & (~(fu1_total_credit_cnt_l2 == {5{1'b0}}))) | + (((fu1_send_cnt_zero[0] | fu1_send_cnt_zero[1]) | (fu1_send_cnt_one[0] & fu1_send_cnt_one[1])) & |fu1_total_credit_cnt_l2[0:3]); + + end + endgenerate + + generate + begin : xhdl3 + genvar i; + for (i = 0; i <= `THREADS - 1; i = i + 1) + begin : send_ok + assign send_instructions_all[i] = (fx0_both_credit_ok & fx1_both_credit_ok & lq_cmdq_both_credit_ok & sq_cmdq_both_credit_ok & fu0_both_credit_ok & fu1_both_credit_ok) & + (core_block_ok[i] & fx0_local_credit_ok[i] & fx1_local_credit_ok[i] & lq_cmdq_local_credit_ok[i] & sq_cmdq_local_credit_ok[i] & + fu0_local_credit_ok[i] & fu1_local_credit_ok[i] & (low_pri_mask_l2[i] & frn_fdis_iu6_i0_vld[i])) & + (~(|(core_block) | hold_instructions_l2)); + + assign send_instructions_local[i] = ((fx0_credit_ok[i] & fx1_credit_ok[i] & lq_cmdq_credit_ok[i] & sq_cmdq_credit_ok[i] & fu0_credit_ok[i] & fu1_credit_ok[i]) & + (core_block_ok[i] & fx0_local_credit_ok[i] & fx1_local_credit_ok[i] & lq_cmdq_local_credit_ok[i] & sq_cmdq_local_credit_ok[i] & + fu0_local_credit_ok[i] & fu1_local_credit_ok[i] & (low_pri_mask_l2[i] & frn_fdis_iu6_i0_vld[i])) & + (frn_fdis_iu6_i0_ucode[i][0] | (~(hold_instructions_l2)))); + end + end + endgenerate + + assign hold_instructions_d = |(mm_hold_req_d | hold_req_d | ivax_hold_req_d); + + + generate + if (`THREADS == 1) + begin : send_thread_gen_1 + assign send_instructions[0] = (send_instructions_all[0] | send_instructions_local[0]) & frn_fdis_iu6_i0_vld[0]; + end + endgenerate + + generate + if (`THREADS == 2) + begin : send_thread_gen_2 + assign send_instructions[0] = (send_instructions_all[0] | (last_thread_l2[1] & send_instructions_local[0]) | (~send_instructions_local[1] & send_instructions_local[0])) & frn_fdis_iu6_i0_vld[0]; + + assign send_instructions[1] = (send_instructions_all[1] | (last_thread_l2[0] & send_instructions_local[1]) | (~send_instructions_local[0] & send_instructions_local[1])) & frn_fdis_iu6_i0_vld[1]; + end + endgenerate + + assign fdis_frn_iu6_stall = frn_fdis_iu6_i0_vld & (~send_instructions); + + assign last_thread_act = |send_instructions; + `ifdef THREADS1 + assign last_thread_d = last_thread_l2[0]; + `endif + `ifndef THREADS1 + assign last_thread_d = {last_thread_l2[1:`THREADS - 1], last_thread_l2[0]}; + `endif + + + generate + begin : local_credit_calc + genvar i; + for (i = 0; i <= `THREADS - 1; i = i + 1) + begin : local_credit_calc_thread + assign fx0_high_credit_cnt_plus1_temp[i] = fx0_high_credit_cnt_l2[i] + value_1[27:31]; + assign fx0_high_credit_cnt_minus1_temp[i] = fx0_high_credit_cnt_l2[i] - value_1[27:31]; + assign fx0_high_credit_cnt_minus2_temp[i] = fx0_high_credit_cnt_l2[i] - value_2[27:31]; + assign fx0_med_credit_cnt_plus1_temp[i] = fx0_med_credit_cnt_l2[i] + value_1[27:31]; + assign fx0_med_credit_cnt_minus1_temp[i] = fx0_med_credit_cnt_l2[i] - value_1[27:31]; + assign fx0_med_credit_cnt_minus2_temp[i] = fx0_med_credit_cnt_l2[i] - value_2[27:31]; + + assign fx1_high_credit_cnt_plus1_temp[i] = fx1_high_credit_cnt_l2[i] + value_1[27:31]; + assign fx1_high_credit_cnt_minus1_temp[i] = fx1_high_credit_cnt_l2[i] - value_1[27:31]; + assign fx1_high_credit_cnt_minus2_temp[i] = fx1_high_credit_cnt_l2[i] - value_2[27:31]; + assign fx1_med_credit_cnt_plus1_temp[i] = fx1_med_credit_cnt_l2[i] + value_1[27:31]; + assign fx1_med_credit_cnt_minus1_temp[i] = fx1_med_credit_cnt_l2[i] - value_1[27:31]; + assign fx1_med_credit_cnt_minus2_temp[i] = fx1_med_credit_cnt_l2[i] - value_2[27:31]; + + assign lq_cmdq_high_credit_cnt_plus1_temp[i] = lq_cmdq_high_credit_cnt_l2[i] + value_1[27:31]; + assign lq_cmdq_high_credit_cnt_minus1_temp[i] = lq_cmdq_high_credit_cnt_l2[i] - value_1[27:31]; + assign lq_cmdq_high_credit_cnt_minus2_temp[i] = lq_cmdq_high_credit_cnt_l2[i] - value_2[27:31]; + assign lq_cmdq_med_credit_cnt_plus1_temp[i] = lq_cmdq_med_credit_cnt_l2[i] + value_1[27:31]; + assign lq_cmdq_med_credit_cnt_minus1_temp[i] = lq_cmdq_med_credit_cnt_l2[i] - value_1[27:31]; + assign lq_cmdq_med_credit_cnt_minus2_temp[i] = lq_cmdq_med_credit_cnt_l2[i] - value_2[27:31]; + + assign sq_cmdq_high_credit_cnt_plus1_temp[i] = sq_cmdq_high_credit_cnt_l2[i] + value_1[27:31]; + assign sq_cmdq_high_credit_cnt_minus1_temp[i] = sq_cmdq_high_credit_cnt_l2[i] - value_1[27:31]; + assign sq_cmdq_high_credit_cnt_minus2_temp[i] = sq_cmdq_high_credit_cnt_l2[i] - value_2[27:31]; + assign sq_cmdq_med_credit_cnt_plus1_temp[i] = sq_cmdq_med_credit_cnt_l2[i] + value_1[27:31]; + assign sq_cmdq_med_credit_cnt_minus1_temp[i] = sq_cmdq_med_credit_cnt_l2[i] - value_1[27:31]; + assign sq_cmdq_med_credit_cnt_minus2_temp[i] = sq_cmdq_med_credit_cnt_l2[i] - value_2[27:31]; + + assign fu0_high_credit_cnt_plus1_temp[i] = fu0_high_credit_cnt_l2[i] + value_1[27:31]; + assign fu0_high_credit_cnt_minus1_temp[i] = fu0_high_credit_cnt_l2[i] - value_1[27:31]; + assign fu0_high_credit_cnt_minus2_temp[i] = fu0_high_credit_cnt_l2[i] - value_2[27:31]; + assign fu0_med_credit_cnt_plus1_temp[i] = fu0_med_credit_cnt_l2[i] + value_1[27:31]; + assign fu0_med_credit_cnt_minus1_temp[i] = fu0_med_credit_cnt_l2[i] - value_1[27:31]; + assign fu0_med_credit_cnt_minus2_temp[i] = fu0_med_credit_cnt_l2[i] - value_2[27:31]; + + assign fu1_high_credit_cnt_plus1_temp[i] = fu1_high_credit_cnt_l2[i] + value_1[27:31]; + assign fu1_high_credit_cnt_minus1_temp[i] = fu1_high_credit_cnt_l2[i] - value_1[27:31]; + assign fu1_high_credit_cnt_minus2_temp[i] = fu1_high_credit_cnt_l2[i] - value_2[27:31]; + assign fu1_med_credit_cnt_plus1_temp[i] = fu1_med_credit_cnt_l2[i] + value_1[27:31]; + assign fu1_med_credit_cnt_minus1_temp[i] = fu1_med_credit_cnt_l2[i] - value_1[27:31]; + assign fu1_med_credit_cnt_minus2_temp[i] = fu1_med_credit_cnt_l2[i] - value_2[27:31]; + + assign fx0_high_credit_cnt_plus1[i] = ((spr_cpcr_we[i] == 1'b1) | (&cp_flush_l2 == 1'b1)) ? spr_high_fx0_cnt[i] : + (fx0_high_credit_cnt_plus1_temp[i] > spr_high_fx0_cnt[i]) ? spr_high_fx0_cnt[i] : + fx0_high_credit_cnt_plus1_temp[i]; + + assign fx0_high_credit_cnt_minus1[i] = ((spr_cpcr_we[i] == 1'b1) | (&cp_flush_l2 == 1'b1)) ? spr_high_fx0_cnt[i] : + (fx0_high_credit_cnt_minus1_temp[i][0] == 1'b1) ? 5'b0 : + fx0_high_credit_cnt_minus1_temp[i]; + + assign fx0_high_credit_cnt_minus2[i] = ((spr_cpcr_we[i] == 1'b1) | (&cp_flush_l2 == 1'b1)) ? spr_high_fx0_cnt[i] : + (fx0_high_credit_cnt_minus2_temp[i][0] == 1'b1) ? 5'b0 : + fx0_high_credit_cnt_minus2_temp[i]; + + assign fx0_med_credit_cnt_plus1[i] = ((spr_cpcr_we[i] == 1'b1) | (&cp_flush_l2 == 1'b1)) ? spr_med_fx0_cnt[i] : + (fx0_med_credit_cnt_plus1_temp[i] > spr_med_fx0_cnt[i]) ? spr_med_fx0_cnt[i] : + fx0_med_credit_cnt_plus1_temp[i]; + + assign fx0_med_credit_cnt_minus1[i] = ((spr_cpcr_we[i] == 1'b1) | (&cp_flush_l2 == 1'b1)) ? spr_med_fx0_cnt[i] : + (fx0_med_credit_cnt_minus1_temp[i][0] == 1'b1) ? 5'b0 : + fx0_med_credit_cnt_minus1_temp[i]; + + assign fx0_med_credit_cnt_minus2[i] = ((spr_cpcr_we[i] == 1'b1) | (&cp_flush_l2 == 1'b1)) ? spr_med_fx0_cnt[i] : + (fx0_med_credit_cnt_minus2_temp[i][0] == 1'b1) ? 5'b0 : + fx0_med_credit_cnt_minus2_temp[i]; + + assign fx1_high_credit_cnt_plus1[i] = ((spr_cpcr_we[i] == 1'b1) | (&cp_flush_l2 == 1'b1)) ? spr_high_fx1_cnt[i] : + (fx1_high_credit_cnt_plus1_temp[i] > spr_high_fx1_cnt[i]) ? spr_high_fx1_cnt[i] : + fx1_high_credit_cnt_plus1_temp[i]; + + assign fx1_high_credit_cnt_minus1[i] = ((spr_cpcr_we[i] == 1'b1) | (&cp_flush_l2 == 1'b1)) ? spr_high_fx1_cnt[i] : + (fx1_high_credit_cnt_minus1_temp[i][0] == 1'b1) ? 5'b0 : + fx1_high_credit_cnt_minus1_temp[i]; + + assign fx1_high_credit_cnt_minus2[i] = ((spr_cpcr_we[i] == 1'b1) | (&cp_flush_l2 == 1'b1)) ? spr_high_fx1_cnt[i] : + (fx1_high_credit_cnt_minus2_temp[i][0] == 1'b1) ? 5'b0 : + fx1_high_credit_cnt_minus2_temp[i]; + + assign fx1_med_credit_cnt_plus1[i] = ((spr_cpcr_we[i] == 1'b1) | (&cp_flush_l2 == 1'b1)) ? spr_med_fx1_cnt[i] : + (fx1_med_credit_cnt_plus1_temp[i] > spr_med_fx1_cnt[i]) ? spr_med_fx1_cnt[i] : + fx1_med_credit_cnt_plus1_temp[i]; + + assign fx1_med_credit_cnt_minus1[i] = ((spr_cpcr_we[i] == 1'b1) | (&cp_flush_l2 == 1'b1)) ? spr_med_fx1_cnt[i] : + (fx1_med_credit_cnt_minus1_temp[i][0] == 1'b1) ? 5'b0 : + fx1_med_credit_cnt_minus1_temp[i]; + + assign fx1_med_credit_cnt_minus2[i] = ((spr_cpcr_we[i] == 1'b1) | (&cp_flush_l2 == 1'b1)) ? spr_med_fx1_cnt[i] : + (fx1_med_credit_cnt_minus2_temp[i][0] == 1'b1) ? 5'b0 : + fx1_med_credit_cnt_minus2_temp[i]; + + assign lq_cmdq_high_credit_cnt_plus1[i] = (spr_cpcr_we[i] == 1'b1) ? spr_high_lq_cnt[i] : + (lq_cmdq_high_credit_cnt_plus1_temp[i] > spr_high_lq_cnt[i]) ? spr_high_lq_cnt[i] : + lq_cmdq_high_credit_cnt_plus1_temp[i]; + + assign lq_cmdq_high_credit_cnt_minus1[i] = (spr_cpcr_we[i] == 1'b1) ? spr_high_lq_cnt[i] : + (lq_cmdq_high_credit_cnt_minus1_temp[i][0] == 1'b1) ? 5'b0 : + lq_cmdq_high_credit_cnt_minus1_temp[i]; + + assign lq_cmdq_high_credit_cnt_minus2[i] = (spr_cpcr_we[i] == 1'b1) ? spr_high_lq_cnt[i] : + (lq_cmdq_high_credit_cnt_minus2_temp[i][0] == 1'b1) ? 5'b0 : + lq_cmdq_high_credit_cnt_minus2_temp[i]; + + assign lq_cmdq_med_credit_cnt_plus1[i] = (spr_cpcr_we[i] == 1'b1) ? spr_med_lq_cnt[i] : + (lq_cmdq_med_credit_cnt_plus1_temp[i] > spr_med_lq_cnt[i]) ? spr_med_lq_cnt[i] : + lq_cmdq_med_credit_cnt_plus1_temp[i]; + + assign lq_cmdq_med_credit_cnt_minus1[i] = (spr_cpcr_we[i] == 1'b1) ? spr_med_lq_cnt[i] : + (lq_cmdq_med_credit_cnt_minus1_temp[i][0] == 1'b1) ? 5'b0 : + lq_cmdq_med_credit_cnt_minus1_temp[i]; + + assign lq_cmdq_med_credit_cnt_minus2[i] = (spr_cpcr_we[i] == 1'b1) ? spr_med_lq_cnt[i] : + (lq_cmdq_med_credit_cnt_minus2_temp[i][0] == 1'b1) ? 5'b0 : + lq_cmdq_med_credit_cnt_minus2_temp[i]; + + assign sq_cmdq_high_credit_cnt_plus1[i] = (spr_cpcr_we[i] == 1'b1) ? spr_high_sq_cnt[i] : + (sq_cmdq_high_credit_cnt_plus1_temp[i] > spr_high_sq_cnt[i]) ? spr_high_sq_cnt[i] : + sq_cmdq_high_credit_cnt_plus1_temp[i]; + + assign sq_cmdq_high_credit_cnt_minus1[i] = (spr_cpcr_we[i] == 1'b1) ? spr_high_sq_cnt[i] : + (sq_cmdq_high_credit_cnt_minus1_temp[i][0] == 1'b1) ? 5'b0 : + sq_cmdq_high_credit_cnt_minus1_temp[i]; + + assign sq_cmdq_high_credit_cnt_minus2[i] = (spr_cpcr_we[i] == 1'b1) ? spr_high_sq_cnt[i] : + (sq_cmdq_high_credit_cnt_minus2_temp[i][0] == 1'b1) ? 5'b0 : + sq_cmdq_high_credit_cnt_minus2_temp[i]; + + assign sq_cmdq_med_credit_cnt_plus1[i] = (spr_cpcr_we[i] == 1'b1) ? spr_med_sq_cnt[i] : + (sq_cmdq_med_credit_cnt_plus1_temp[i] > spr_med_sq_cnt[i]) ? spr_med_sq_cnt[i] : + sq_cmdq_med_credit_cnt_plus1_temp[i]; + + assign sq_cmdq_med_credit_cnt_minus1[i] = (spr_cpcr_we[i] == 1'b1) ? spr_med_sq_cnt[i] : + (sq_cmdq_med_credit_cnt_minus1_temp[i][0] == 1'b1) ? 5'b0 : + sq_cmdq_med_credit_cnt_minus1_temp[i]; + + assign sq_cmdq_med_credit_cnt_minus2[i] = (spr_cpcr_we[i] == 1'b1) ? spr_med_sq_cnt[i] : + (sq_cmdq_med_credit_cnt_minus2_temp[i][0] == 1'b1) ? 5'b0 : + sq_cmdq_med_credit_cnt_minus2_temp[i]; + + assign fu0_high_credit_cnt_plus1[i] = ((spr_cpcr_we[i] == 1'b1) | (&cp_flush_l2 == 1'b1)) ? spr_high_fu0_cnt[i] : + (fu0_high_credit_cnt_plus1_temp[i] > spr_high_fu0_cnt[i]) ? spr_high_fu0_cnt[i] : + fu0_high_credit_cnt_plus1_temp[i]; + + assign fu0_high_credit_cnt_minus1[i] = ((spr_cpcr_we[i] == 1'b1) | (&cp_flush_l2 == 1'b1)) ? spr_high_fu0_cnt[i] : + (fu0_high_credit_cnt_minus1_temp[i][0] == 1'b1) ? 5'b0 : + fu0_high_credit_cnt_minus1_temp[i]; + + assign fu0_high_credit_cnt_minus2[i] = ((spr_cpcr_we[i] == 1'b1) | (&cp_flush_l2 == 1'b1)) ? spr_high_fu0_cnt[i] : + (fu0_high_credit_cnt_minus2_temp[i][0] == 1'b1) ? 5'b0 : + fu0_high_credit_cnt_minus2_temp[i]; + + assign fu0_med_credit_cnt_plus1[i] = ((spr_cpcr_we[i] == 1'b1) | (&cp_flush_l2 == 1'b1)) ? spr_med_fu0_cnt[i] : + (fu0_med_credit_cnt_plus1_temp[i] > spr_med_fu0_cnt[i]) ? spr_med_fu0_cnt[i] : + fu0_med_credit_cnt_plus1_temp[i]; + + assign fu0_med_credit_cnt_minus1[i] = ((spr_cpcr_we[i] == 1'b1) | (&cp_flush_l2 == 1'b1)) ? spr_med_fu0_cnt[i] : + (fu0_med_credit_cnt_minus1_temp[i][0] == 1'b1) ? 5'b0 : + fu0_med_credit_cnt_minus1_temp[i]; + + assign fu0_med_credit_cnt_minus2[i] = ((spr_cpcr_we[i] == 1'b1) | (&cp_flush_l2 == 1'b1)) ? spr_med_fu0_cnt[i] : + (fu0_med_credit_cnt_minus2_temp[i][0] == 1'b1) ? 5'b0 : + fu0_med_credit_cnt_minus2_temp[i]; + + assign fu1_high_credit_cnt_plus1[i] = ((spr_cpcr_we[i] == 1'b1) | (&cp_flush_l2 == 1'b1)) ? spr_high_fu1_cnt[i] : + (fu1_high_credit_cnt_plus1_temp[i] > spr_high_fu1_cnt[i]) ? spr_high_fu1_cnt[i] : + fu1_high_credit_cnt_plus1_temp[i]; + + assign fu1_high_credit_cnt_minus1[i] = ((spr_cpcr_we[i] == 1'b1) | (&cp_flush_l2 == 1'b1)) ? spr_high_fu1_cnt[i] : + (fu1_high_credit_cnt_minus1_temp[i][0] == 1'b1) ? 5'b0 : + fu1_high_credit_cnt_minus1_temp[i]; + + assign fu1_high_credit_cnt_minus2[i] = ((spr_cpcr_we[i] == 1'b1) | (&cp_flush_l2 == 1'b1)) ? spr_high_fu1_cnt[i] : + (fu1_high_credit_cnt_minus2_temp[i][0] == 1'b1) ? 5'b0 : + fu1_high_credit_cnt_minus2_temp[i]; + + assign fu1_med_credit_cnt_plus1[i] = ((spr_cpcr_we[i] == 1'b1) | (&cp_flush_l2 == 1'b1)) ? spr_med_fu1_cnt[i] : + (fu1_med_credit_cnt_plus1_temp[i] > spr_med_fu1_cnt[i]) ? spr_med_fu1_cnt[i] : + fu1_med_credit_cnt_plus1_temp[i]; + + assign fu1_med_credit_cnt_minus1[i] = ((spr_cpcr_we[i] == 1'b1) | (&cp_flush_l2 == 1'b1)) ? spr_med_fu1_cnt[i] : + (fu1_med_credit_cnt_minus1_temp[i][0] == 1'b1) ? 5'b0 : + fu1_med_credit_cnt_minus1_temp[i]; + + assign fu1_med_credit_cnt_minus2[i] = ((spr_cpcr_we[i] == 1'b1) | (&cp_flush_l2 == 1'b1)) ? spr_med_fu1_cnt[i] : + (fu1_med_credit_cnt_minus2_temp[i][0] == 1'b1) ? 5'b0 : + fu1_med_credit_cnt_minus2_temp[i]; + end + end + endgenerate + + + generate + begin : xhdl4 + genvar i; + for (i = 0; i <= `THREADS - 1; i = i + 1) + begin : credit_proc + always @(*) + begin: fx0_credit_proc + fx0_high_credit_cnt_d[i] = ((spr_cpcr_we[i] == 1'b1) | (&cp_flush_l2 == 1'b1)) ? spr_high_fx0_cnt[i] : fx0_high_credit_cnt_l2[i]; + fx0_med_credit_cnt_d[i] = ((spr_cpcr_we[i] == 1'b1) | (&cp_flush_l2 == 1'b1)) ? spr_med_fx0_cnt[i] : fx0_med_credit_cnt_l2[i]; + fx0_credit_cnt_minus_1[i] = 1'b0; + fx0_credit_cnt_minus_2[i] = 1'b0; + fx0_credit_cnt_plus_1[i] = 1'b0; + fx0_credit_cnt_zero[i] = 1'b1; + + if (rv_iu_fx0_credit_free[i] == 1'b1 & (send_instructions[i] == 1'b0 | fx0_send_cnt[i] == 2'b00)) + begin + fx0_high_credit_cnt_d[i] = fx0_high_credit_cnt_plus1[i]; + fx0_med_credit_cnt_d[i] = fx0_med_credit_cnt_plus1[i]; + fx0_credit_cnt_plus_1[i] = 1'b1; + fx0_credit_cnt_zero[i] = 1'b0; + end + if ((send_instructions[i] == 1'b1) & (((fx0_send_cnt[i][0] == 1'b1 ^ fx0_send_cnt[i][1] == 1'b1) & rv_iu_fx0_credit_free[i] == 1'b0) | ((fx0_send_cnt[i] == 2'b11) & rv_iu_fx0_credit_free[i] == 1'b1))) + begin + fx0_high_credit_cnt_d[i] = fx0_high_credit_cnt_minus1[i]; + fx0_med_credit_cnt_d[i] = fx0_med_credit_cnt_minus1[i]; + fx0_credit_cnt_minus_1[i] = 1'b1; + fx0_credit_cnt_zero[i] = 1'b0; + end + if (send_instructions[i] == 1'b1 & fx0_send_cnt[i] == 2'b11 & rv_iu_fx0_credit_free[i] == 1'b0) + begin + fx0_high_credit_cnt_d[i] = fx0_high_credit_cnt_minus2[i]; + fx0_med_credit_cnt_d[i] = fx0_med_credit_cnt_minus2[i]; + fx0_credit_cnt_minus_2[i] = 1'b1; + fx0_credit_cnt_zero[i] = 1'b0; + end + end + + always @(*) + begin: fx1_credit_proc + fx1_high_credit_cnt_d[i] = ((spr_cpcr_we[i] == 1'b1) | (&cp_flush_l2 == 1'b1)) ? spr_high_fx1_cnt[i] : fx1_high_credit_cnt_l2[i]; + fx1_med_credit_cnt_d[i] = ((spr_cpcr_we[i] == 1'b1) | (&cp_flush_l2 == 1'b1)) ? spr_med_fx1_cnt[i] : fx1_med_credit_cnt_l2[i]; + fx1_credit_cnt_minus_1[i] = 1'b0; + fx1_credit_cnt_minus_2[i] = 1'b0; + fx1_credit_cnt_plus_1[i] = 1'b0; + fx1_credit_cnt_zero[i] = 1'b1; + + if ((rv_iu_fx1_credit_free[i] == 1'b1) & (send_instructions[i] == 1'b0 | fx1_send_cnt[i] == 2'b00)) + begin + fx1_high_credit_cnt_d[i] = fx1_high_credit_cnt_plus1[i]; + fx1_med_credit_cnt_d[i] = fx1_med_credit_cnt_plus1[i]; + fx1_credit_cnt_plus_1[i] = 1'b1; + fx1_credit_cnt_zero[i] = 1'b0; + end + if ((send_instructions[i] == 1'b1) & (((fx1_send_cnt[i][0] == 1'b1 ^ fx1_send_cnt[i][1] == 1'b1) & rv_iu_fx1_credit_free[i] == 1'b0) | ((fx1_send_cnt[i] == 2'b11) & rv_iu_fx1_credit_free[i] == 1'b1))) + begin + fx1_high_credit_cnt_d[i] = fx1_high_credit_cnt_minus1[i]; + fx1_med_credit_cnt_d[i] = fx1_med_credit_cnt_minus1[i]; + fx1_credit_cnt_minus_1[i] = 1'b1; + fx1_credit_cnt_zero[i] = 1'b0; + end + if (send_instructions[i] == 1'b1 & fx1_send_cnt[i] == 2'b11 & rv_iu_fx1_credit_free[i] == 1'b0) + begin + fx1_high_credit_cnt_d[i] = fx1_high_credit_cnt_minus2[i]; + fx1_med_credit_cnt_d[i] = fx1_med_credit_cnt_minus2[i]; + fx1_credit_cnt_minus_2[i] = 1'b1; + fx1_credit_cnt_zero[i] = 1'b0; + end + + end + + always @(*) + begin: lq_cmdq_credit_proc + lq_cmdq_high_credit_cnt_d[i] = (spr_cpcr_we[i] == 1'b1) ? spr_high_lq_cnt[i] : lq_cmdq_high_credit_cnt_l2[i]; + lq_cmdq_med_credit_cnt_d[i] = (spr_cpcr_we[i] == 1'b1) ? spr_med_lq_cnt[i] : lq_cmdq_med_credit_cnt_l2[i]; + lq_cmdq_credit_cnt_minus_1[i] = 1'b0; + lq_cmdq_credit_cnt_minus_2[i] = 1'b0; + lq_cmdq_credit_cnt_plus_1[i] = 1'b0; + lq_cmdq_credit_cnt_zero[i] = 1'b1; + + if ((lq_iu_credit_free[i] == 1'b1) & (send_instructions[i] == 1'b0 | lq_cmdq_send_cnt[i] == 2'b00)) + begin + lq_cmdq_high_credit_cnt_d[i] = lq_cmdq_high_credit_cnt_plus1[i]; + lq_cmdq_med_credit_cnt_d[i] = lq_cmdq_med_credit_cnt_plus1[i]; + lq_cmdq_credit_cnt_plus_1[i] = 1'b1; + lq_cmdq_credit_cnt_zero[i] = 1'b0; + end + if ((send_instructions[i] == 1'b1) & (((lq_cmdq_send_cnt[i][0] == 1'b1 ^ lq_cmdq_send_cnt[i][1] == 1'b1) & lq_iu_credit_free[i] == 1'b0) | ((lq_cmdq_send_cnt[i] == 2'b11) & lq_iu_credit_free[i] == 1'b1))) + begin + lq_cmdq_high_credit_cnt_d[i] = lq_cmdq_high_credit_cnt_minus1[i]; + lq_cmdq_med_credit_cnt_d[i] = lq_cmdq_med_credit_cnt_minus1[i]; + lq_cmdq_credit_cnt_minus_1[i] = 1'b1; + lq_cmdq_credit_cnt_zero[i] = 1'b0; + end + if (send_instructions[i] == 1'b1 & lq_cmdq_send_cnt[i] == 2'b11 & lq_iu_credit_free[i] == 1'b0) + begin + lq_cmdq_high_credit_cnt_d[i] = lq_cmdq_high_credit_cnt_minus2[i]; + lq_cmdq_med_credit_cnt_d[i] = lq_cmdq_med_credit_cnt_minus2[i]; + lq_cmdq_credit_cnt_minus_2[i] = 1'b1; + lq_cmdq_credit_cnt_zero[i] = 1'b0; + end + end + + always @(*) + begin: sq_cmdq_credit_proc + sq_cmdq_high_credit_cnt_d[i] = (spr_cpcr_we[i] == 1'b1) ? spr_high_sq_cnt[i] : sq_cmdq_high_credit_cnt_l2[i]; + sq_cmdq_med_credit_cnt_d[i] = (spr_cpcr_we[i] == 1'b1) ? spr_med_sq_cnt[i] : sq_cmdq_med_credit_cnt_l2[i]; + sq_cmdq_credit_cnt_minus_1[i] = 1'b0; + sq_cmdq_credit_cnt_minus_2[i] = 1'b0; + sq_cmdq_credit_cnt_plus_1[i] = 1'b0; + sq_cmdq_credit_cnt_zero[i] = 1'b1; + + if ((sq_iu_credit_free[i] == 1'b1) & (send_instructions[i] == 1'b0 | sq_cmdq_send_cnt[i] == 2'b00)) + begin + sq_cmdq_high_credit_cnt_d[i] = sq_cmdq_high_credit_cnt_plus1[i]; + sq_cmdq_med_credit_cnt_d[i] = sq_cmdq_med_credit_cnt_plus1[i]; + sq_cmdq_credit_cnt_plus_1[i] = 1'b1; + sq_cmdq_credit_cnt_zero[i] = 1'b0; + end + if ((send_instructions[i] == 1'b1) & (((sq_cmdq_send_cnt[i][0] == 1'b1 ^ sq_cmdq_send_cnt[i][1] == 1'b1) & sq_iu_credit_free[i] == 1'b0) | ((sq_cmdq_send_cnt[i] == 2'b11) & sq_iu_credit_free[i] == 1'b1))) + begin + sq_cmdq_high_credit_cnt_d[i] = sq_cmdq_high_credit_cnt_minus1[i]; + sq_cmdq_med_credit_cnt_d[i] = sq_cmdq_med_credit_cnt_minus1[i]; + sq_cmdq_credit_cnt_minus_1[i] = 1'b1; + sq_cmdq_credit_cnt_zero[i] = 1'b0; + end + if (send_instructions[i] == 1'b1 & sq_cmdq_send_cnt[i] == 2'b11 & sq_iu_credit_free[i] == 1'b0) + begin + sq_cmdq_high_credit_cnt_d[i] = sq_cmdq_high_credit_cnt_minus2[i]; + sq_cmdq_med_credit_cnt_d[i] = sq_cmdq_med_credit_cnt_minus2[i]; + sq_cmdq_credit_cnt_minus_2[i] = 1'b1; + sq_cmdq_credit_cnt_zero[i] = 1'b0; + end + end + + always @(*) + begin: fu0_credit_proc + fu0_high_credit_cnt_d[i] = ((spr_cpcr_we[i] == 1'b1) | (&cp_flush_l2 == 1'b1)) ? spr_high_fu0_cnt[i] : fu0_high_credit_cnt_l2[i]; + fu0_med_credit_cnt_d[i] = ((spr_cpcr_we[i] == 1'b1) | (&cp_flush_l2 == 1'b1)) ? spr_med_fu0_cnt[i] : fu0_med_credit_cnt_l2[i]; + fu0_credit_cnt_minus_1[i] = 1'b0; + fu0_credit_cnt_minus_2[i] = 1'b0; + fu0_credit_cnt_plus_1[i] = 1'b0; + fu0_credit_cnt_zero[i] = 1'b1; + + if ((axu0_iu_credit_free[i] == 1'b1) & (send_instructions[i] == 1'b0 | fu0_send_cnt[i] == 2'b00)) + begin + fu0_high_credit_cnt_d[i] = fu0_high_credit_cnt_plus1[i]; + fu0_med_credit_cnt_d[i] = fu0_med_credit_cnt_plus1[i]; + fu0_credit_cnt_plus_1[i] = 1'b1; + fu0_credit_cnt_zero[i] = 1'b0; + end + if ((send_instructions[i] == 1'b1) & (((fu0_send_cnt[i][0] == 1'b1 ^ fu0_send_cnt[i][1] == 1'b1) & axu0_iu_credit_free[i] == 1'b0) | ((fu0_send_cnt[i] == 2'b11) & axu0_iu_credit_free[i] == 1'b1))) + begin + fu0_high_credit_cnt_d[i] = fu0_high_credit_cnt_minus1[i]; + fu0_med_credit_cnt_d[i] = fu0_med_credit_cnt_minus1[i]; + fu0_credit_cnt_minus_1[i] = 1'b1; + fu0_credit_cnt_zero[i] = 1'b0; + end + if (send_instructions[i] == 1'b1 & fu0_send_cnt[i] == 2'b11 & axu0_iu_credit_free[i] == 1'b0) + begin + fu0_high_credit_cnt_d[i] = fu0_high_credit_cnt_minus2[i]; + fu0_med_credit_cnt_d[i] = fu0_med_credit_cnt_minus2[i]; + fu0_credit_cnt_minus_2[i] = 1'b1; + fu0_credit_cnt_zero[i] = 1'b0; + end + end + + always @(*) + begin: fu1_credit_proc + fu1_high_credit_cnt_d[i] = ((spr_cpcr_we[i] == 1'b1) | (&cp_flush_l2 == 1'b1)) ? spr_high_fu1_cnt[i] : fu1_high_credit_cnt_l2[i]; + fu1_med_credit_cnt_d[i] = ((spr_cpcr_we[i] == 1'b1) | (&cp_flush_l2 == 1'b1)) ? spr_med_fu1_cnt[i] : fu1_med_credit_cnt_l2[i]; + fu1_credit_cnt_minus_1[i] = 1'b0; + fu1_credit_cnt_minus_2[i] = 1'b0; + fu1_credit_cnt_plus_1[i] = 1'b0; + fu1_credit_cnt_zero[i] = 1'b1; + + if ((axu1_iu_credit_free[i] == 1'b1) & (send_instructions[i] == 1'b0 | fu1_send_cnt[i] == 2'b00)) + begin + fu1_high_credit_cnt_d[i] = fu1_high_credit_cnt_plus1[i]; + fu1_med_credit_cnt_d[i] = fu1_med_credit_cnt_plus1[i]; + fu1_credit_cnt_plus_1[i] = 1'b1; + fu1_credit_cnt_zero[i] = 1'b0; + end + if ((send_instructions[i] == 1'b1) & (((fu1_send_cnt[i][0] == 1'b1 ^ fu1_send_cnt[i][1] == 1'b1) & axu1_iu_credit_free[i] == 1'b0) | ((fu1_send_cnt[i] == 2'b11) & axu1_iu_credit_free[i] == 1'b1))) + begin + fu1_high_credit_cnt_d[i] = fu1_high_credit_cnt_minus1[i]; + fu1_med_credit_cnt_d[i] = fu1_med_credit_cnt_minus1[i]; + fu1_credit_cnt_minus_1[i] = 1'b1; + fu1_credit_cnt_zero[i] = 1'b0; + end + if (send_instructions[i] == 1'b1 & fu1_send_cnt[i] == 2'b11 & axu1_iu_credit_free[i] == 1'b0) + begin + fu1_high_credit_cnt_d[i] = fu1_high_credit_cnt_minus2[i]; + fu1_med_credit_cnt_d[i] = fu1_med_credit_cnt_minus2[i]; + fu1_credit_cnt_minus_2[i] = 1'b1; + fu1_credit_cnt_zero[i] = 1'b0; + end + end + end + end + endgenerate + +`ifdef THREADS1 + always @(*) + begin: thread1_credit_proc + fx0_credit_cnt_minus_1[1] = 1'b0; + fx0_credit_cnt_minus_2[1] = 1'b0; + fx0_credit_cnt_plus_1[1] = 1'b0; + fx0_credit_cnt_zero[1] = 1'b1; + fx1_credit_cnt_minus_1[1] = 1'b0; + fx1_credit_cnt_minus_2[1] = 1'b0; + fx1_credit_cnt_plus_1[1] = 1'b0; + fx1_credit_cnt_zero[1] = 1'b1; + lq_cmdq_credit_cnt_minus_1[1] = 1'b0; + lq_cmdq_credit_cnt_minus_2[1] = 1'b0; + lq_cmdq_credit_cnt_plus_1[1] = 1'b0; + lq_cmdq_credit_cnt_zero[1] = 1'b1; + sq_cmdq_credit_cnt_minus_1[1] = 1'b0; + sq_cmdq_credit_cnt_minus_2[1] = 1'b0; + sq_cmdq_credit_cnt_plus_1[1] = 1'b0; + sq_cmdq_credit_cnt_zero[1] = 1'b1; + fu0_credit_cnt_minus_1[1] = 1'b0; + fu0_credit_cnt_minus_2[1] = 1'b0; + fu0_credit_cnt_plus_1[1] = 1'b0; + fu0_credit_cnt_zero[1] = 1'b1; + fu1_credit_cnt_minus_1[1] = 1'b0; + fu1_credit_cnt_minus_2[1] = 1'b0; + fu1_credit_cnt_plus_1[1] = 1'b0; + fu1_credit_cnt_zero[1] = 1'b1; + end +`endif + + always @(*) + begin: fx0_total_credit_proc + + fx0_total_credit_cnt_d = fx0_total_credit_cnt_l2; + + if (|spr_cpcr_we == 1'b1 | &cp_flush_l2 == 1'b1) + fx0_total_credit_cnt_d = spr_cpcr0_fx0_cnt; + else + begin + if(fx0_credit_cnt_minus_2[0] & fx0_credit_cnt_minus_2[1]) + fx0_total_credit_cnt_d = fx0_total_credit_cnt_l2 - value_4[27:31]; + if((fx0_credit_cnt_minus_2[0] & fx0_credit_cnt_minus_1[1]) | (fx0_credit_cnt_minus_1[0] & fx0_credit_cnt_minus_2[1])) + fx0_total_credit_cnt_d = fx0_total_credit_cnt_l2 - value_3[27:31]; + if((fx0_credit_cnt_minus_2[0] & fx0_credit_cnt_zero[1]) | (fx0_credit_cnt_minus_1[0] & fx0_credit_cnt_minus_1[1]) | (fx0_credit_cnt_zero[0] & fx0_credit_cnt_minus_2[1])) + fx0_total_credit_cnt_d = fx0_total_credit_cnt_l2 - value_2[27:31]; + if((fx0_credit_cnt_minus_2[0] & fx0_credit_cnt_plus_1[1]) | (fx0_credit_cnt_minus_1[0] & fx0_credit_cnt_zero[1]) | (fx0_credit_cnt_zero[0] & fx0_credit_cnt_minus_1[1]) | (fx0_credit_cnt_plus_1[0] & fx0_credit_cnt_minus_2[1])) + fx0_total_credit_cnt_d = fx0_total_credit_cnt_l2 - value_1[27:31]; + if((fx0_credit_cnt_zero[0] & fx0_credit_cnt_plus_1[1]) | (fx0_credit_cnt_plus_1[0] & fx0_credit_cnt_zero[1])) + fx0_total_credit_cnt_d = fx0_total_credit_cnt_l2 + value_1[27:31]; + if(fx0_credit_cnt_plus_1[0] & fx0_credit_cnt_plus_1[1]) + fx0_total_credit_cnt_d = fx0_total_credit_cnt_l2 + value_2[27:31]; + end + end + + always @(*) + begin: fx1_total_credit_proc + + fx1_total_credit_cnt_d = fx1_total_credit_cnt_l2; + + if (|spr_cpcr_we == 1'b1 | &cp_flush_l2 == 1'b1) + fx1_total_credit_cnt_d = spr_cpcr0_fx1_cnt; + else + begin + if(fx1_credit_cnt_minus_2[0] & fx1_credit_cnt_minus_2[1]) + fx1_total_credit_cnt_d = fx1_total_credit_cnt_l2 - value_4[27:31]; + if((fx1_credit_cnt_minus_2[0] & fx1_credit_cnt_minus_1[1]) | (fx1_credit_cnt_minus_1[0] & fx1_credit_cnt_minus_2[1])) + fx1_total_credit_cnt_d = fx1_total_credit_cnt_l2 - value_3[27:31]; + if((fx1_credit_cnt_minus_2[0] & fx1_credit_cnt_zero[1]) | (fx1_credit_cnt_minus_1[0] & fx1_credit_cnt_minus_1[1]) | (fx1_credit_cnt_zero[0] & fx1_credit_cnt_minus_2[1])) + fx1_total_credit_cnt_d = fx1_total_credit_cnt_l2 - value_2[27:31]; + if((fx1_credit_cnt_minus_2[0] & fx1_credit_cnt_plus_1[1]) | (fx1_credit_cnt_minus_1[0] & fx1_credit_cnt_zero[1]) | (fx1_credit_cnt_zero[0] & fx1_credit_cnt_minus_1[1]) | (fx1_credit_cnt_plus_1[0] & fx1_credit_cnt_minus_2[1])) + fx1_total_credit_cnt_d = fx1_total_credit_cnt_l2 - value_1[27:31]; + if((fx1_credit_cnt_zero[0] & fx1_credit_cnt_plus_1[1]) | (fx1_credit_cnt_plus_1[0] & fx1_credit_cnt_zero[1])) + fx1_total_credit_cnt_d = fx1_total_credit_cnt_l2 + value_1[27:31]; + if(fx1_credit_cnt_plus_1[0] & fx1_credit_cnt_plus_1[1]) + fx1_total_credit_cnt_d = fx1_total_credit_cnt_l2 + value_2[27:31]; + end + end + + always @(*) + begin: lq_cmdq_total_credit_proc + + lq_cmdq_total_credit_cnt_d = lq_cmdq_total_credit_cnt_l2; + + if (|spr_cpcr_we == 1'b1) + lq_cmdq_total_credit_cnt_d = spr_cpcr0_lq_cnt; + else + begin + if(lq_cmdq_credit_cnt_minus_2[0] & lq_cmdq_credit_cnt_minus_2[1]) + lq_cmdq_total_credit_cnt_d = lq_cmdq_total_credit_cnt_l2 - value_4[27:31]; + if((lq_cmdq_credit_cnt_minus_2[0] & lq_cmdq_credit_cnt_minus_1[1]) | (lq_cmdq_credit_cnt_minus_1[0] & lq_cmdq_credit_cnt_minus_2[1])) + lq_cmdq_total_credit_cnt_d = lq_cmdq_total_credit_cnt_l2 - value_3[27:31]; + if((lq_cmdq_credit_cnt_minus_2[0] & lq_cmdq_credit_cnt_zero[1]) | (lq_cmdq_credit_cnt_minus_1[0] & lq_cmdq_credit_cnt_minus_1[1]) | (lq_cmdq_credit_cnt_zero[0] & lq_cmdq_credit_cnt_minus_2[1])) + lq_cmdq_total_credit_cnt_d = lq_cmdq_total_credit_cnt_l2 - value_2[27:31]; + if((lq_cmdq_credit_cnt_minus_2[0] & lq_cmdq_credit_cnt_plus_1[1]) | (lq_cmdq_credit_cnt_minus_1[0] & lq_cmdq_credit_cnt_zero[1]) | (lq_cmdq_credit_cnt_zero[0] & lq_cmdq_credit_cnt_minus_1[1]) | + (lq_cmdq_credit_cnt_plus_1[0] & lq_cmdq_credit_cnt_minus_2[1])) + lq_cmdq_total_credit_cnt_d = lq_cmdq_total_credit_cnt_l2 - value_1[27:31]; + if((lq_cmdq_credit_cnt_zero[0] & lq_cmdq_credit_cnt_plus_1[1]) | (lq_cmdq_credit_cnt_plus_1[0] & lq_cmdq_credit_cnt_zero[1])) + lq_cmdq_total_credit_cnt_d = lq_cmdq_total_credit_cnt_l2 + value_1[27:31]; + if(lq_cmdq_credit_cnt_plus_1[0] & lq_cmdq_credit_cnt_plus_1[1]) + lq_cmdq_total_credit_cnt_d = lq_cmdq_total_credit_cnt_l2 + value_2[27:31]; + end + end + + always @(*) + begin: sq_cmdq_total_credit_proc + + sq_cmdq_total_credit_cnt_d = sq_cmdq_total_credit_cnt_l2; + + if (|spr_cpcr_we == 1'b1) + sq_cmdq_total_credit_cnt_d = spr_cpcr0_sq_cnt; + else + begin + if(sq_cmdq_credit_cnt_minus_2[0] & sq_cmdq_credit_cnt_minus_2[1]) + sq_cmdq_total_credit_cnt_d = sq_cmdq_total_credit_cnt_l2 - value_4[27:31]; + if((sq_cmdq_credit_cnt_minus_2[0] & sq_cmdq_credit_cnt_minus_1[1]) | (sq_cmdq_credit_cnt_minus_1[0] & sq_cmdq_credit_cnt_minus_2[1])) + sq_cmdq_total_credit_cnt_d = sq_cmdq_total_credit_cnt_l2 - value_3[27:31]; + if((sq_cmdq_credit_cnt_minus_2[0] & sq_cmdq_credit_cnt_zero[1]) | (sq_cmdq_credit_cnt_minus_1[0] & sq_cmdq_credit_cnt_minus_1[1]) | + (sq_cmdq_credit_cnt_zero[0] & sq_cmdq_credit_cnt_minus_2[1])) + sq_cmdq_total_credit_cnt_d = sq_cmdq_total_credit_cnt_l2 - value_2[27:31]; + if((sq_cmdq_credit_cnt_minus_2[0] & sq_cmdq_credit_cnt_plus_1[1]) | (sq_cmdq_credit_cnt_minus_1[0] & sq_cmdq_credit_cnt_zero[1]) | + (sq_cmdq_credit_cnt_zero[0] & sq_cmdq_credit_cnt_minus_1[1]) | (sq_cmdq_credit_cnt_plus_1[0] & sq_cmdq_credit_cnt_minus_2[1])) + sq_cmdq_total_credit_cnt_d = sq_cmdq_total_credit_cnt_l2 - value_1[27:31]; + if((sq_cmdq_credit_cnt_zero[0] & sq_cmdq_credit_cnt_plus_1[1]) | (sq_cmdq_credit_cnt_plus_1[0] & sq_cmdq_credit_cnt_zero[1])) + sq_cmdq_total_credit_cnt_d = sq_cmdq_total_credit_cnt_l2 + value_1[27:31]; + if(sq_cmdq_credit_cnt_plus_1[0] & sq_cmdq_credit_cnt_plus_1[1]) + sq_cmdq_total_credit_cnt_d = sq_cmdq_total_credit_cnt_l2 + value_2[27:31]; + end + end + + always @(*) + begin: fu0_total_credit_proc + + fu0_total_credit_cnt_d = fu0_total_credit_cnt_l2; + + if (|spr_cpcr_we == 1'b1 | &cp_flush_l2 == 1'b1) + fu0_total_credit_cnt_d = spr_cpcr1_fu0_cnt; + else + begin + if(fu0_credit_cnt_minus_2[0] & fu0_credit_cnt_minus_2[1]) + fu0_total_credit_cnt_d = fu0_total_credit_cnt_l2 - value_4[27:31]; + if((fu0_credit_cnt_minus_2[0] & fu0_credit_cnt_minus_1[1]) | (fu0_credit_cnt_minus_1[0] & fu0_credit_cnt_minus_2[1])) + fu0_total_credit_cnt_d = fu0_total_credit_cnt_l2 - value_3[27:31]; + if((fu0_credit_cnt_minus_2[0] & fu0_credit_cnt_zero[1]) | (fu0_credit_cnt_minus_1[0] & fu0_credit_cnt_minus_1[1]) | (fu0_credit_cnt_zero[0] & fu0_credit_cnt_minus_2[1])) + fu0_total_credit_cnt_d = fu0_total_credit_cnt_l2 - value_2[27:31]; + if((fu0_credit_cnt_minus_2[0] & fu0_credit_cnt_plus_1[1]) | (fu0_credit_cnt_minus_1[0] & fu0_credit_cnt_zero[1]) | (fu0_credit_cnt_zero[0] & fu0_credit_cnt_minus_1[1]) | (fu0_credit_cnt_plus_1[0] & fu0_credit_cnt_minus_2[1])) + fu0_total_credit_cnt_d = fu0_total_credit_cnt_l2 - value_1[27:31]; + if((fu0_credit_cnt_zero[0] & fu0_credit_cnt_plus_1[1]) | (fu0_credit_cnt_plus_1[0] & fu0_credit_cnt_zero[1])) + fu0_total_credit_cnt_d = fu0_total_credit_cnt_l2 + value_1[27:31]; + if(fu0_credit_cnt_plus_1[0] & fu0_credit_cnt_plus_1[1]) + fu0_total_credit_cnt_d = fu0_total_credit_cnt_l2 + value_2[27:31]; + end + end + + always @(*) + begin: fu1_total_credit_proc + + fu1_total_credit_cnt_d = fu1_total_credit_cnt_l2; + + if (|spr_cpcr_we == 1'b1 | &cp_flush_l2 == 1'b1) + fu1_total_credit_cnt_d = spr_cpcr1_fu1_cnt; + else + begin + if(fu1_credit_cnt_minus_2[0] & fu1_credit_cnt_minus_2[1]) + fu1_total_credit_cnt_d = fu1_total_credit_cnt_l2 - value_4[27:31]; + if((fu1_credit_cnt_minus_2[0] & fu1_credit_cnt_minus_1[1]) | (fu1_credit_cnt_minus_1[0] & fu1_credit_cnt_minus_2[1])) + fu1_total_credit_cnt_d = fu1_total_credit_cnt_l2 - value_3[27:31]; + if((fu1_credit_cnt_minus_2[0] & fu1_credit_cnt_zero[1]) | (fu1_credit_cnt_minus_1[0] & fu1_credit_cnt_minus_1[1]) | (fu1_credit_cnt_zero[0] & fu1_credit_cnt_minus_2[1])) + fu1_total_credit_cnt_d = fu1_total_credit_cnt_l2 - value_2[27:31]; + if((fu1_credit_cnt_minus_2[0] & fu1_credit_cnt_plus_1[1]) | (fu1_credit_cnt_minus_1[0] & fu1_credit_cnt_zero[1]) | (fu1_credit_cnt_zero[0] & fu1_credit_cnt_minus_1[1]) | (fu1_credit_cnt_plus_1[0] & fu1_credit_cnt_minus_2[1])) + fu1_total_credit_cnt_d = fu1_total_credit_cnt_l2 - value_1[27:31]; + if((fu1_credit_cnt_zero[0] & fu1_credit_cnt_plus_1[1]) | (fu1_credit_cnt_plus_1[0] & fu1_credit_cnt_zero[1])) + fu1_total_credit_cnt_d = fu1_total_credit_cnt_l2 + value_1[27:31]; + if(fu1_credit_cnt_plus_1[0] & fu1_credit_cnt_plus_1[1]) + fu1_total_credit_cnt_d = fu1_total_credit_cnt_l2 + value_2[27:31]; + end + end + +assign iu_xu_credits_returned_d = (fx0_total_credit_cnt_l2 == spr_cpcr0_fx0_cnt) & + (fx1_total_credit_cnt_l2 == spr_cpcr0_fx1_cnt) & + (lq_cmdq_total_credit_cnt_l2 == spr_cpcr0_lq_cnt ) & + (sq_cmdq_total_credit_cnt_l2 == spr_cpcr0_sq_cnt ) & + (fu0_total_credit_cnt_l2 == spr_cpcr1_fu0_cnt) & + (fu1_total_credit_cnt_l2 == spr_cpcr1_fu1_cnt) ; + +assign iu_xu_credits_returned = iu_xu_credits_returned_l2; + +`ifdef THREADS1 + assign total_pri_mask_d[0] = (spr_high_pri_mask[0] | spr_med_pri_mask[0]); + assign high_pri_mask_d[0] = 1'b0; + assign med_pri_mask_d[0] = (~spr_high_pri_mask[0] & ~spr_med_pri_mask[0] & low_pri_en[0]); + assign low_pri_mask_d[0] = spr_high_pri_mask[0] | spr_med_pri_mask[0] | (~spr_high_pri_mask[0] & ~spr_med_pri_mask[0] & low_pri_en[0]); +`endif +`ifndef THREADS1 + assign total_pri_mask_d[0] = (spr_high_pri_mask[0] | spr_med_pri_mask[0]) & ~xu_iu_run_thread_l2[1]; + assign high_pri_mask_d[0] = spr_high_pri_mask[0] & xu_iu_run_thread_l2[1]; + assign med_pri_mask_d[0] = (~spr_high_pri_mask[0] & ~spr_med_pri_mask[0] & low_pri_en[0]) | (spr_med_pri_mask[0] & xu_iu_run_thread_l2[1]); + assign low_pri_mask_d[0] = spr_high_pri_mask[0] | spr_med_pri_mask[0] | (~spr_high_pri_mask[0] & ~spr_med_pri_mask[0] & low_pri_en[0]); + + assign total_pri_mask_d[1] = (spr_high_pri_mask[1] | spr_med_pri_mask[1]) & ~xu_iu_run_thread_l2[0]; + assign high_pri_mask_d[1] = spr_high_pri_mask[1] & xu_iu_run_thread_l2[0]; + assign med_pri_mask_d[1] = (~spr_high_pri_mask[1] & ~spr_med_pri_mask[1] & low_pri_en[1]) | (spr_med_pri_mask[1] & xu_iu_run_thread_l2[0]); + assign low_pri_mask_d[1] = spr_high_pri_mask[1] | spr_med_pri_mask[1] | (~spr_high_pri_mask[1] & ~spr_med_pri_mask[1] & low_pri_en[1]); +`endif + + generate + begin : pri_mask + genvar i; + for (i = 0; i <= `THREADS - 1; i = i + 1) + begin : pri_mask_set + assign low_pri_max_d[i] = spr_low_pri_count[i]; + + assign low_pri_cnt_d[i] = (iu_rv_iu6_i0_vld_int[i]) ? {8{1'b0}} : + low_pri_cnt_l2[i] + value_1[24:31]; + + assign low_pri_cnt_act[i] = ((low_pri_cnt_l2[i][0:5] != low_pri_max_l2[i]) | + iu_rv_iu6_i0_vld_int[i]) & ~spr_high_pri_mask[i] & ~spr_med_pri_mask[i]; + + assign low_pri_en[i] = (low_pri_max_l2[i] == low_pri_cnt_l2[i][0:5]) & ~iu_rv_iu6_i0_vld_int[i] & ~spr_high_pri_mask[i] & ~spr_med_pri_mask[i]; + end + end + endgenerate + + always @(*) + begin: dual_iss_fx0_proc + dual_issue_use_fx0_d = 2'b11; + if (`FXU1_ENABLE == 1 & fx0_total_credit_cnt_l2 < fx1_total_credit_cnt_l2) + dual_issue_use_fx0_d = 2'b00; + if (`FXU1_ENABLE == 1 & fx0_total_credit_cnt_l2 == fx1_total_credit_cnt_l2) + dual_issue_use_fx0_d = 2'b10; + end + + + assign iu_rv_iu6_i0_vld_int = send_instructions & frn_fdis_iu6_i0_vld; + assign iu_rv_iu6_i1_vld_int = send_instructions & frn_fdis_iu6_i1_vld; + + assign iu_rv_iu6_t0_i0_vld = iu_rv_iu6_i0_vld_int[0]; + assign iu_rv_iu6_t0_i0_act = frn_fdis_iu6_i0_vld[0]; + assign iu_rv_iu6_t0_i0_itag = frn_fdis_iu6_i0_itag[0]; + assign iu_rv_iu6_t0_i0_rte_lq = frn_fdis_iu6_i0_rte_lq[0]; + assign iu_rv_iu6_t0_i0_rte_sq = frn_fdis_iu6_i0_rte_sq[0]; + assign iu_rv_iu6_t0_i0_rte_fx0 = fx0_send_cnt[0][0] & frn_fdis_iu6_i0_rte_fx0[0]; + assign iu_rv_iu6_t0_i0_rte_fx1 = fx1_send_cnt[0][0] & frn_fdis_iu6_i0_rte_fx1[0]; + assign iu_rv_iu6_t0_i0_rte_axu0 = frn_fdis_iu6_i0_rte_axu0[0]; + assign iu_rv_iu6_t0_i0_rte_axu1 = frn_fdis_iu6_i0_rte_axu1[0]; + assign iu_rv_iu6_t0_i0_ucode = frn_fdis_iu6_i0_ucode[0]; + assign iu_rv_iu6_t0_i0_ucode_cnt = frn_fdis_iu6_i0_ucode_cnt[0]; + assign iu_rv_iu6_t0_i0_2ucode = frn_fdis_iu6_i0_2ucode[0]; + assign iu_rv_iu6_t0_i0_fuse_nop = frn_fdis_iu6_i0_fuse_nop[0]; + assign iu_rv_iu6_t0_i0_valop = frn_fdis_iu6_i0_valop[0]; + assign iu_rv_iu6_t0_i0_ord = frn_fdis_iu6_i0_ord[0]; + assign iu_rv_iu6_t0_i0_cord = frn_fdis_iu6_i0_cord[0]; + assign iu_rv_iu6_t0_i0_error = frn_fdis_iu6_i0_error[0]; + assign iu_rv_iu6_t0_i0_btb_entry = frn_fdis_iu6_i0_btb_entry[0]; + assign iu_rv_iu6_t0_i0_btb_hist = frn_fdis_iu6_i0_btb_hist[0]; + assign iu_rv_iu6_t0_i0_bta_val = frn_fdis_iu6_i0_bta_val[0]; + assign iu_rv_iu6_t0_i0_fusion = frn_fdis_iu6_i0_fusion[0]; + assign iu_rv_iu6_t0_i0_spec = frn_fdis_iu6_i0_spec[0]; + assign iu_rv_iu6_t0_i0_type_fp = frn_fdis_iu6_i0_type_fp[0]; + assign iu_rv_iu6_t0_i0_type_ap = frn_fdis_iu6_i0_type_ap[0]; + assign iu_rv_iu6_t0_i0_type_spv = frn_fdis_iu6_i0_type_spv[0]; + assign iu_rv_iu6_t0_i0_type_st = frn_fdis_iu6_i0_type_st[0]; + assign iu_rv_iu6_t0_i0_async_block = frn_fdis_iu6_i0_async_block[0]; + assign iu_rv_iu6_t0_i0_np1_flush = frn_fdis_iu6_i0_np1_flush[0]; + assign iu_rv_iu6_t0_i0_isram = frn_fdis_iu6_i0_isram[0]; + assign iu_rv_iu6_t0_i0_isload = frn_fdis_iu6_i0_isload[0]; + assign iu_rv_iu6_t0_i0_isstore = frn_fdis_iu6_i0_isstore[0]; + assign iu_rv_iu6_t0_i0_instr = frn_fdis_iu6_i0_instr[0]; + assign iu_rv_iu6_t0_i0_ifar = frn_fdis_iu6_i0_ifar[0]; + assign iu_rv_iu6_t0_i0_bta = frn_fdis_iu6_i0_bta[0]; + assign iu_rv_iu6_t0_i0_br_pred = frn_fdis_iu6_i0_br_pred[0]; + assign iu_rv_iu6_t0_i0_bh_update = frn_fdis_iu6_i0_bh_update[0]; + assign iu_rv_iu6_t0_i0_bh0_hist = frn_fdis_iu6_i0_bh0_hist[0]; + assign iu_rv_iu6_t0_i0_bh1_hist = frn_fdis_iu6_i0_bh1_hist[0]; + assign iu_rv_iu6_t0_i0_bh2_hist = frn_fdis_iu6_i0_bh2_hist[0]; + assign iu_rv_iu6_t0_i0_gshare = frn_fdis_iu6_i0_gshare[0]; + assign iu_rv_iu6_t0_i0_ls_ptr = frn_fdis_iu6_i0_ls_ptr[0]; + assign iu_rv_iu6_t0_i0_match = frn_fdis_iu6_i0_match[0]; + assign iu_rv_iu6_t0_i0_ilat = frn_fdis_iu6_i0_ilat[0]; + assign iu_rv_iu6_t0_i0_t1_v = frn_fdis_iu6_i0_t1_v[0]; + assign iu_rv_iu6_t0_i0_t1_t = frn_fdis_iu6_i0_t1_t[0]; + assign iu_rv_iu6_t0_i0_t1_a = frn_fdis_iu6_i0_t1_a[0]; + assign iu_rv_iu6_t0_i0_t1_p = frn_fdis_iu6_i0_t1_p[0]; + assign iu_rv_iu6_t0_i0_t2_v = frn_fdis_iu6_i0_t2_v[0]; + assign iu_rv_iu6_t0_i0_t2_a = frn_fdis_iu6_i0_t2_a[0]; + assign iu_rv_iu6_t0_i0_t2_p = frn_fdis_iu6_i0_t2_p[0]; + assign iu_rv_iu6_t0_i0_t2_t = frn_fdis_iu6_i0_t2_t[0]; + assign iu_rv_iu6_t0_i0_t3_v = frn_fdis_iu6_i0_t3_v[0]; + assign iu_rv_iu6_t0_i0_t3_a = frn_fdis_iu6_i0_t3_a[0]; + assign iu_rv_iu6_t0_i0_t3_p = frn_fdis_iu6_i0_t3_p[0]; + assign iu_rv_iu6_t0_i0_t3_t = frn_fdis_iu6_i0_t3_t[0]; + assign iu_rv_iu6_t0_i0_s1_v = frn_fdis_iu6_i0_s1_v[0]; + assign iu_rv_iu6_t0_i0_s1_a = frn_fdis_iu6_i0_s1_a[0]; + assign iu_rv_iu6_t0_i0_s1_p = frn_fdis_iu6_i0_s1_p[0]; + assign iu_rv_iu6_t0_i0_s1_itag = frn_fdis_iu6_i0_s1_itag[0]; + assign iu_rv_iu6_t0_i0_s1_t = frn_fdis_iu6_i0_s1_t[0]; + assign iu_rv_iu6_t0_i0_s2_v = frn_fdis_iu6_i0_s2_v[0]; + assign iu_rv_iu6_t0_i0_s2_a = frn_fdis_iu6_i0_s2_a[0]; + assign iu_rv_iu6_t0_i0_s2_p = frn_fdis_iu6_i0_s2_p[0]; + assign iu_rv_iu6_t0_i0_s2_itag = frn_fdis_iu6_i0_s2_itag[0]; + assign iu_rv_iu6_t0_i0_s2_t = frn_fdis_iu6_i0_s2_t[0]; + assign iu_rv_iu6_t0_i0_s3_v = frn_fdis_iu6_i0_s3_v[0]; + assign iu_rv_iu6_t0_i0_s3_a = frn_fdis_iu6_i0_s3_a[0]; + assign iu_rv_iu6_t0_i0_s3_p = frn_fdis_iu6_i0_s3_p[0]; + assign iu_rv_iu6_t0_i0_s3_itag = frn_fdis_iu6_i0_s3_itag[0]; + assign iu_rv_iu6_t0_i0_s3_t = frn_fdis_iu6_i0_s3_t[0]; + assign iu_rv_iu6_t0_i1_vld = iu_rv_iu6_i1_vld_int[0]; + assign iu_rv_iu6_t0_i1_act = frn_fdis_iu6_i1_vld[0]; + assign iu_rv_iu6_t0_i1_itag = frn_fdis_iu6_i1_itag[0]; + assign iu_rv_iu6_t0_i1_rte_lq = frn_fdis_iu6_i1_rte_lq[0]; + assign iu_rv_iu6_t0_i1_rte_sq = frn_fdis_iu6_i1_rte_sq[0]; + assign iu_rv_iu6_t0_i1_rte_fx0 = fx0_send_cnt[0][1] & frn_fdis_iu6_i1_rte_fx0[0]; + assign iu_rv_iu6_t0_i1_rte_fx1 = fx1_send_cnt[0][1] & frn_fdis_iu6_i1_rte_fx1[0]; + assign iu_rv_iu6_t0_i1_rte_axu0 = frn_fdis_iu6_i1_rte_axu0[0]; + assign iu_rv_iu6_t0_i1_rte_axu1 = frn_fdis_iu6_i1_rte_axu1[0]; + assign iu_rv_iu6_t0_i1_ucode = frn_fdis_iu6_i1_ucode[0]; + assign iu_rv_iu6_t0_i1_ucode_cnt = frn_fdis_iu6_i1_ucode_cnt[0]; + assign iu_rv_iu6_t0_i1_fuse_nop = frn_fdis_iu6_i1_fuse_nop[0]; + assign iu_rv_iu6_t0_i1_valop = frn_fdis_iu6_i1_valop[0]; + assign iu_rv_iu6_t0_i1_ord = frn_fdis_iu6_i1_ord[0]; + assign iu_rv_iu6_t0_i1_cord = frn_fdis_iu6_i1_cord[0]; + assign iu_rv_iu6_t0_i1_error = frn_fdis_iu6_i1_error[0]; + assign iu_rv_iu6_t0_i1_btb_entry = frn_fdis_iu6_i1_btb_entry[0]; + assign iu_rv_iu6_t0_i1_btb_hist = frn_fdis_iu6_i1_btb_hist[0]; + assign iu_rv_iu6_t0_i1_bta_val = frn_fdis_iu6_i1_bta_val[0]; + assign iu_rv_iu6_t0_i1_fusion = frn_fdis_iu6_i1_fusion[0]; + assign iu_rv_iu6_t0_i1_spec = frn_fdis_iu6_i1_spec[0]; + assign iu_rv_iu6_t0_i1_type_fp = frn_fdis_iu6_i1_type_fp[0]; + assign iu_rv_iu6_t0_i1_type_ap = frn_fdis_iu6_i1_type_ap[0]; + assign iu_rv_iu6_t0_i1_type_spv = frn_fdis_iu6_i1_type_spv[0]; + assign iu_rv_iu6_t0_i1_type_st = frn_fdis_iu6_i1_type_st[0]; + assign iu_rv_iu6_t0_i1_async_block = frn_fdis_iu6_i1_async_block[0]; + assign iu_rv_iu6_t0_i1_np1_flush = frn_fdis_iu6_i1_np1_flush[0]; + assign iu_rv_iu6_t0_i1_isram = frn_fdis_iu6_i1_isram[0]; + assign iu_rv_iu6_t0_i1_isload = frn_fdis_iu6_i1_isload[0]; + assign iu_rv_iu6_t0_i1_isstore = frn_fdis_iu6_i1_isstore[0]; + assign iu_rv_iu6_t0_i1_instr = frn_fdis_iu6_i1_instr[0]; + assign iu_rv_iu6_t0_i1_ifar = frn_fdis_iu6_i1_ifar[0]; + assign iu_rv_iu6_t0_i1_bta = frn_fdis_iu6_i1_bta[0]; + assign iu_rv_iu6_t0_i1_br_pred = frn_fdis_iu6_i1_br_pred[0]; + assign iu_rv_iu6_t0_i1_bh_update = frn_fdis_iu6_i1_bh_update[0]; + assign iu_rv_iu6_t0_i1_bh0_hist = frn_fdis_iu6_i1_bh0_hist[0]; + assign iu_rv_iu6_t0_i1_bh1_hist = frn_fdis_iu6_i1_bh1_hist[0]; + assign iu_rv_iu6_t0_i1_bh2_hist = frn_fdis_iu6_i1_bh2_hist[0]; + assign iu_rv_iu6_t0_i1_gshare = frn_fdis_iu6_i1_gshare[0]; + assign iu_rv_iu6_t0_i1_ls_ptr = frn_fdis_iu6_i1_ls_ptr[0]; + assign iu_rv_iu6_t0_i1_match = frn_fdis_iu6_i1_match[0]; + assign iu_rv_iu6_t0_i1_ilat = frn_fdis_iu6_i1_ilat[0]; + assign iu_rv_iu6_t0_i1_t1_v = frn_fdis_iu6_i1_t1_v[0]; + assign iu_rv_iu6_t0_i1_t1_t = frn_fdis_iu6_i1_t1_t[0]; + assign iu_rv_iu6_t0_i1_t1_a = frn_fdis_iu6_i1_t1_a[0]; + assign iu_rv_iu6_t0_i1_t1_p = frn_fdis_iu6_i1_t1_p[0]; + assign iu_rv_iu6_t0_i1_t2_v = frn_fdis_iu6_i1_t2_v[0]; + assign iu_rv_iu6_t0_i1_t2_a = frn_fdis_iu6_i1_t2_a[0]; + assign iu_rv_iu6_t0_i1_t2_p = frn_fdis_iu6_i1_t2_p[0]; + assign iu_rv_iu6_t0_i1_t2_t = frn_fdis_iu6_i1_t2_t[0]; + assign iu_rv_iu6_t0_i1_t3_v = frn_fdis_iu6_i1_t3_v[0]; + assign iu_rv_iu6_t0_i1_t3_a = frn_fdis_iu6_i1_t3_a[0]; + assign iu_rv_iu6_t0_i1_t3_p = frn_fdis_iu6_i1_t3_p[0]; + assign iu_rv_iu6_t0_i1_t3_t = frn_fdis_iu6_i1_t3_t[0]; + assign iu_rv_iu6_t0_i1_s1_v = frn_fdis_iu6_i1_s1_v[0]; + assign iu_rv_iu6_t0_i1_s1_a = frn_fdis_iu6_i1_s1_a[0]; + assign iu_rv_iu6_t0_i1_s1_p = frn_fdis_iu6_i1_s1_p[0]; + assign iu_rv_iu6_t0_i1_s1_itag = frn_fdis_iu6_i1_s1_itag[0]; + assign iu_rv_iu6_t0_i1_s1_t = frn_fdis_iu6_i1_s1_t[0]; + assign iu_rv_iu6_t0_i1_s1_dep_hit = frn_fdis_iu6_i1_s1_dep_hit[0]; + assign iu_rv_iu6_t0_i1_s2_v = frn_fdis_iu6_i1_s2_v[0]; + assign iu_rv_iu6_t0_i1_s2_a = frn_fdis_iu6_i1_s2_a[0]; + assign iu_rv_iu6_t0_i1_s2_p = frn_fdis_iu6_i1_s2_p[0]; + assign iu_rv_iu6_t0_i1_s2_itag = frn_fdis_iu6_i1_s2_itag[0]; + assign iu_rv_iu6_t0_i1_s2_t = frn_fdis_iu6_i1_s2_t[0]; + assign iu_rv_iu6_t0_i1_s2_dep_hit = frn_fdis_iu6_i1_s2_dep_hit[0]; + assign iu_rv_iu6_t0_i1_s3_v = frn_fdis_iu6_i1_s3_v[0]; + assign iu_rv_iu6_t0_i1_s3_a = frn_fdis_iu6_i1_s3_a[0]; + assign iu_rv_iu6_t0_i1_s3_p = frn_fdis_iu6_i1_s3_p[0]; + assign iu_rv_iu6_t0_i1_s3_itag = frn_fdis_iu6_i1_s3_itag[0]; + assign iu_rv_iu6_t0_i1_s3_t = frn_fdis_iu6_i1_s3_t[0]; + assign iu_rv_iu6_t0_i1_s3_dep_hit = frn_fdis_iu6_i1_s3_dep_hit[0]; + +`ifndef THREADS1 + assign iu_rv_iu6_t1_i0_vld = iu_rv_iu6_i0_vld_int[1]; + assign iu_rv_iu6_t1_i0_act = frn_fdis_iu6_i0_vld[1]; + assign iu_rv_iu6_t1_i0_itag = frn_fdis_iu6_i0_itag[1]; + assign iu_rv_iu6_t1_i0_rte_lq = frn_fdis_iu6_i0_rte_lq[1]; + assign iu_rv_iu6_t1_i0_rte_sq = frn_fdis_iu6_i0_rte_sq[1]; + assign iu_rv_iu6_t1_i0_rte_fx0 = fx0_send_cnt[1][0] & frn_fdis_iu6_i0_rte_fx0[1]; + assign iu_rv_iu6_t1_i0_rte_fx1 = fx1_send_cnt[1][0] & frn_fdis_iu6_i0_rte_fx1[1]; + assign iu_rv_iu6_t1_i0_rte_axu0 = frn_fdis_iu6_i0_rte_axu0[1]; + assign iu_rv_iu6_t1_i0_rte_axu1 = frn_fdis_iu6_i0_rte_axu1[1]; + assign iu_rv_iu6_t1_i0_ucode = frn_fdis_iu6_i0_ucode[1]; + assign iu_rv_iu6_t1_i0_ucode_cnt = frn_fdis_iu6_i0_ucode_cnt[1]; + assign iu_rv_iu6_t1_i0_2ucode = frn_fdis_iu6_i0_2ucode[1]; + assign iu_rv_iu6_t1_i0_fuse_nop = frn_fdis_iu6_i0_fuse_nop[1]; + assign iu_rv_iu6_t1_i0_valop = frn_fdis_iu6_i0_valop[1]; + assign iu_rv_iu6_t1_i0_ord = frn_fdis_iu6_i0_ord[1]; + assign iu_rv_iu6_t1_i0_cord = frn_fdis_iu6_i0_cord[1]; + assign iu_rv_iu6_t1_i0_error = frn_fdis_iu6_i0_error[1]; + assign iu_rv_iu6_t1_i0_btb_entry = frn_fdis_iu6_i0_btb_entry[1]; + assign iu_rv_iu6_t1_i0_btb_hist = frn_fdis_iu6_i0_btb_hist[1]; + assign iu_rv_iu6_t1_i0_bta_val = frn_fdis_iu6_i0_bta_val[1]; + assign iu_rv_iu6_t1_i0_fusion = frn_fdis_iu6_i0_fusion[1]; + assign iu_rv_iu6_t1_i0_spec = frn_fdis_iu6_i0_spec[1]; + assign iu_rv_iu6_t1_i0_type_fp = frn_fdis_iu6_i0_type_fp[1]; + assign iu_rv_iu6_t1_i0_type_ap = frn_fdis_iu6_i0_type_ap[1]; + assign iu_rv_iu6_t1_i0_type_spv = frn_fdis_iu6_i0_type_spv[1]; + assign iu_rv_iu6_t1_i0_type_st = frn_fdis_iu6_i0_type_st[1]; + assign iu_rv_iu6_t1_i0_async_block = frn_fdis_iu6_i0_async_block[1]; + assign iu_rv_iu6_t1_i0_np1_flush = frn_fdis_iu6_i0_np1_flush[1]; + assign iu_rv_iu6_t1_i0_isram = frn_fdis_iu6_i0_isram[1]; + assign iu_rv_iu6_t1_i0_isload = frn_fdis_iu6_i0_isload[1]; + assign iu_rv_iu6_t1_i0_isstore = frn_fdis_iu6_i0_isstore[1]; + assign iu_rv_iu6_t1_i0_instr = frn_fdis_iu6_i0_instr[1]; + assign iu_rv_iu6_t1_i0_ifar = frn_fdis_iu6_i0_ifar[1]; + assign iu_rv_iu6_t1_i0_bta = frn_fdis_iu6_i0_bta[1]; + assign iu_rv_iu6_t1_i0_br_pred = frn_fdis_iu6_i0_br_pred[1]; + assign iu_rv_iu6_t1_i0_bh_update = frn_fdis_iu6_i0_bh_update[1]; + assign iu_rv_iu6_t1_i0_bh0_hist = frn_fdis_iu6_i0_bh0_hist[1]; + assign iu_rv_iu6_t1_i0_bh1_hist = frn_fdis_iu6_i0_bh1_hist[1]; + assign iu_rv_iu6_t1_i0_bh2_hist = frn_fdis_iu6_i0_bh2_hist[1]; + assign iu_rv_iu6_t1_i0_gshare = frn_fdis_iu6_i0_gshare[1]; + assign iu_rv_iu6_t1_i0_ls_ptr = frn_fdis_iu6_i0_ls_ptr[1]; + assign iu_rv_iu6_t1_i0_match = frn_fdis_iu6_i0_match[1]; + assign iu_rv_iu6_t1_i0_ilat = frn_fdis_iu6_i0_ilat[1]; + assign iu_rv_iu6_t1_i0_t1_v = frn_fdis_iu6_i0_t1_v[1]; + assign iu_rv_iu6_t1_i0_t1_t = frn_fdis_iu6_i0_t1_t[1]; + assign iu_rv_iu6_t1_i0_t1_a = frn_fdis_iu6_i0_t1_a[1]; + assign iu_rv_iu6_t1_i0_t1_p = frn_fdis_iu6_i0_t1_p[1]; + assign iu_rv_iu6_t1_i0_t2_v = frn_fdis_iu6_i0_t2_v[1]; + assign iu_rv_iu6_t1_i0_t2_a = frn_fdis_iu6_i0_t2_a[1]; + assign iu_rv_iu6_t1_i0_t2_p = frn_fdis_iu6_i0_t2_p[1]; + assign iu_rv_iu6_t1_i0_t2_t = frn_fdis_iu6_i0_t2_t[1]; + assign iu_rv_iu6_t1_i0_t3_v = frn_fdis_iu6_i0_t3_v[1]; + assign iu_rv_iu6_t1_i0_t3_a = frn_fdis_iu6_i0_t3_a[1]; + assign iu_rv_iu6_t1_i0_t3_p = frn_fdis_iu6_i0_t3_p[1]; + assign iu_rv_iu6_t1_i0_t3_t = frn_fdis_iu6_i0_t3_t[1]; + assign iu_rv_iu6_t1_i0_s1_v = frn_fdis_iu6_i0_s1_v[1]; + assign iu_rv_iu6_t1_i0_s1_a = frn_fdis_iu6_i0_s1_a[1]; + assign iu_rv_iu6_t1_i0_s1_p = frn_fdis_iu6_i0_s1_p[1]; + assign iu_rv_iu6_t1_i0_s1_itag = frn_fdis_iu6_i0_s1_itag[1]; + assign iu_rv_iu6_t1_i0_s1_t = frn_fdis_iu6_i0_s1_t[1]; + assign iu_rv_iu6_t1_i0_s2_v = frn_fdis_iu6_i0_s2_v[1]; + assign iu_rv_iu6_t1_i0_s2_a = frn_fdis_iu6_i0_s2_a[1]; + assign iu_rv_iu6_t1_i0_s2_p = frn_fdis_iu6_i0_s2_p[1]; + assign iu_rv_iu6_t1_i0_s2_itag = frn_fdis_iu6_i0_s2_itag[1]; + assign iu_rv_iu6_t1_i0_s2_t = frn_fdis_iu6_i0_s2_t[1]; + assign iu_rv_iu6_t1_i0_s3_v = frn_fdis_iu6_i0_s3_v[1]; + assign iu_rv_iu6_t1_i0_s3_a = frn_fdis_iu6_i0_s3_a[1]; + assign iu_rv_iu6_t1_i0_s3_p = frn_fdis_iu6_i0_s3_p[1]; + assign iu_rv_iu6_t1_i0_s3_itag = frn_fdis_iu6_i0_s3_itag[1]; + assign iu_rv_iu6_t1_i0_s3_t = frn_fdis_iu6_i0_s3_t[1]; + assign iu_rv_iu6_t1_i1_vld = iu_rv_iu6_i1_vld_int[1]; + assign iu_rv_iu6_t1_i1_act = frn_fdis_iu6_i1_vld[1]; + assign iu_rv_iu6_t1_i1_itag = frn_fdis_iu6_i1_itag[1]; + assign iu_rv_iu6_t1_i1_rte_lq = frn_fdis_iu6_i1_rte_lq[1]; + assign iu_rv_iu6_t1_i1_rte_sq = frn_fdis_iu6_i1_rte_sq[1]; + assign iu_rv_iu6_t1_i1_rte_fx0 = fx0_send_cnt[1][1] & frn_fdis_iu6_i1_rte_fx0[1]; + assign iu_rv_iu6_t1_i1_rte_fx1 = fx1_send_cnt[1][1] & frn_fdis_iu6_i1_rte_fx1[1]; + assign iu_rv_iu6_t1_i1_rte_axu0 = frn_fdis_iu6_i1_rte_axu0[1]; + assign iu_rv_iu6_t1_i1_rte_axu1 = frn_fdis_iu6_i1_rte_axu1[1]; + assign iu_rv_iu6_t1_i1_ucode = frn_fdis_iu6_i1_ucode[1]; + assign iu_rv_iu6_t1_i1_ucode_cnt = frn_fdis_iu6_i1_ucode_cnt[1]; + assign iu_rv_iu6_t1_i1_fuse_nop = frn_fdis_iu6_i1_fuse_nop[1]; + assign iu_rv_iu6_t1_i1_valop = frn_fdis_iu6_i1_valop[1]; + assign iu_rv_iu6_t1_i1_ord = frn_fdis_iu6_i1_ord[1]; + assign iu_rv_iu6_t1_i1_cord = frn_fdis_iu6_i1_cord[1]; + assign iu_rv_iu6_t1_i1_error = frn_fdis_iu6_i1_error[1]; + assign iu_rv_iu6_t1_i1_btb_entry = frn_fdis_iu6_i1_btb_entry[1]; + assign iu_rv_iu6_t1_i1_btb_hist = frn_fdis_iu6_i1_btb_hist[1]; + assign iu_rv_iu6_t1_i1_bta_val = frn_fdis_iu6_i1_bta_val[1]; + assign iu_rv_iu6_t1_i1_fusion = frn_fdis_iu6_i1_fusion[1]; + assign iu_rv_iu6_t1_i1_spec = frn_fdis_iu6_i1_spec[1]; + assign iu_rv_iu6_t1_i1_type_fp = frn_fdis_iu6_i1_type_fp[1]; + assign iu_rv_iu6_t1_i1_type_ap = frn_fdis_iu6_i1_type_ap[1]; + assign iu_rv_iu6_t1_i1_type_spv = frn_fdis_iu6_i1_type_spv[1]; + assign iu_rv_iu6_t1_i1_type_st = frn_fdis_iu6_i1_type_st[1]; + assign iu_rv_iu6_t1_i1_async_block = frn_fdis_iu6_i1_async_block[1]; + assign iu_rv_iu6_t1_i1_np1_flush = frn_fdis_iu6_i1_np1_flush[1]; + assign iu_rv_iu6_t1_i1_isram = frn_fdis_iu6_i1_isram[1]; + assign iu_rv_iu6_t1_i1_isload = frn_fdis_iu6_i1_isload[1]; + assign iu_rv_iu6_t1_i1_isstore = frn_fdis_iu6_i1_isstore[1]; + assign iu_rv_iu6_t1_i1_instr = frn_fdis_iu6_i1_instr[1]; + assign iu_rv_iu6_t1_i1_ifar = frn_fdis_iu6_i1_ifar[1]; + assign iu_rv_iu6_t1_i1_bta = frn_fdis_iu6_i1_bta[1]; + assign iu_rv_iu6_t1_i1_br_pred = frn_fdis_iu6_i1_br_pred[1]; + assign iu_rv_iu6_t1_i1_bh_update = frn_fdis_iu6_i1_bh_update[1]; + assign iu_rv_iu6_t1_i1_bh0_hist = frn_fdis_iu6_i1_bh0_hist[1]; + assign iu_rv_iu6_t1_i1_bh1_hist = frn_fdis_iu6_i1_bh1_hist[1]; + assign iu_rv_iu6_t1_i1_bh2_hist = frn_fdis_iu6_i1_bh2_hist[1]; + assign iu_rv_iu6_t1_i1_gshare = frn_fdis_iu6_i1_gshare[1]; + assign iu_rv_iu6_t1_i1_ls_ptr = frn_fdis_iu6_i1_ls_ptr[1]; + assign iu_rv_iu6_t1_i1_match = frn_fdis_iu6_i1_match[1]; + assign iu_rv_iu6_t1_i1_ilat = frn_fdis_iu6_i1_ilat[1]; + assign iu_rv_iu6_t1_i1_t1_v = frn_fdis_iu6_i1_t1_v[1]; + assign iu_rv_iu6_t1_i1_t1_t = frn_fdis_iu6_i1_t1_t[1]; + assign iu_rv_iu6_t1_i1_t1_a = frn_fdis_iu6_i1_t1_a[1]; + assign iu_rv_iu6_t1_i1_t1_p = frn_fdis_iu6_i1_t1_p[1]; + assign iu_rv_iu6_t1_i1_t2_v = frn_fdis_iu6_i1_t2_v[1]; + assign iu_rv_iu6_t1_i1_t2_a = frn_fdis_iu6_i1_t2_a[1]; + assign iu_rv_iu6_t1_i1_t2_p = frn_fdis_iu6_i1_t2_p[1]; + assign iu_rv_iu6_t1_i1_t2_t = frn_fdis_iu6_i1_t2_t[1]; + assign iu_rv_iu6_t1_i1_t3_v = frn_fdis_iu6_i1_t3_v[1]; + assign iu_rv_iu6_t1_i1_t3_a = frn_fdis_iu6_i1_t3_a[1]; + assign iu_rv_iu6_t1_i1_t3_p = frn_fdis_iu6_i1_t3_p[1]; + assign iu_rv_iu6_t1_i1_t3_t = frn_fdis_iu6_i1_t3_t[1]; + assign iu_rv_iu6_t1_i1_s1_v = frn_fdis_iu6_i1_s1_v[1]; + assign iu_rv_iu6_t1_i1_s1_a = frn_fdis_iu6_i1_s1_a[1]; + assign iu_rv_iu6_t1_i1_s1_p = frn_fdis_iu6_i1_s1_p[1]; + assign iu_rv_iu6_t1_i1_s1_itag = frn_fdis_iu6_i1_s1_itag[1]; + assign iu_rv_iu6_t1_i1_s1_t = frn_fdis_iu6_i1_s1_t[1]; + assign iu_rv_iu6_t1_i1_s1_dep_hit = frn_fdis_iu6_i1_s1_dep_hit[1]; + assign iu_rv_iu6_t1_i1_s2_v = frn_fdis_iu6_i1_s2_v[1]; + assign iu_rv_iu6_t1_i1_s2_a = frn_fdis_iu6_i1_s2_a[1]; + assign iu_rv_iu6_t1_i1_s2_p = frn_fdis_iu6_i1_s2_p[1]; + assign iu_rv_iu6_t1_i1_s2_itag = frn_fdis_iu6_i1_s2_itag[1]; + assign iu_rv_iu6_t1_i1_s2_t = frn_fdis_iu6_i1_s2_t[1]; + assign iu_rv_iu6_t1_i1_s2_dep_hit = frn_fdis_iu6_i1_s2_dep_hit[1]; + assign iu_rv_iu6_t1_i1_s3_v = frn_fdis_iu6_i1_s3_v[1]; + assign iu_rv_iu6_t1_i1_s3_a = frn_fdis_iu6_i1_s3_a[1]; + assign iu_rv_iu6_t1_i1_s3_p = frn_fdis_iu6_i1_s3_p[1]; + assign iu_rv_iu6_t1_i1_s3_itag = frn_fdis_iu6_i1_s3_itag[1]; + assign iu_rv_iu6_t1_i1_s3_t = frn_fdis_iu6_i1_s3_t[1]; + assign iu_rv_iu6_t1_i1_s3_dep_hit = frn_fdis_iu6_i1_s3_dep_hit[1]; +`endif + + + + + + // Perf counters + generate + begin : perf_set + genvar i; + for (i = 0; i <= `THREADS - 1; i = i + 1) + begin : perf_mask_set + assign perf_iu6_stall_d[i] = frn_fdis_iu6_i0_vld[i] & (~send_instructions[i]); + + assign perf_iu6_dispatch_fx0_d[i][0] = ((iu_rv_iu6_i1_vld_int[i] & fx0_send_cnt[i][1] & frn_fdis_iu6_i1_rte_fx0[i]) & perf_iu6_dispatch_fx0_l2[i][1]) | + ((iu_rv_iu6_i0_vld_int[i] & fx0_send_cnt[i][0] & frn_fdis_iu6_i0_rte_fx0[i]) & perf_iu6_dispatch_fx0_l2[i][1]) | + (iu_rv_iu6_i0_vld_int[i] & fx0_send_cnt[i][0] & frn_fdis_iu6_i0_rte_fx0[i]) & (iu_rv_iu6_i1_vld_int[i] & fx0_send_cnt[i][1] & frn_fdis_iu6_i1_rte_fx0[i]); + + assign perf_iu6_dispatch_fx0_d[i][1] = (~(iu_rv_iu6_i0_vld_int[i] & fx0_send_cnt[i][0] & frn_fdis_iu6_i0_rte_fx0[i]) & ~(iu_rv_iu6_i1_vld_int[i] & fx0_send_cnt[i][1] & frn_fdis_iu6_i1_rte_fx0[i]) & perf_iu6_dispatch_fx0_l2[i][1]) | + (~(iu_rv_iu6_i0_vld_int[i] & fx0_send_cnt[i][0] & frn_fdis_iu6_i0_rte_fx0[i]) & (iu_rv_iu6_i1_vld_int[i] & fx0_send_cnt[i][1] & frn_fdis_iu6_i1_rte_fx0[i]) & ~perf_iu6_dispatch_fx0_l2[i][1]) | + ((iu_rv_iu6_i0_vld_int[i] & fx0_send_cnt[i][0] & frn_fdis_iu6_i0_rte_fx0[i]) & ~(iu_rv_iu6_i1_vld_int[i] & fx0_send_cnt[i][1] & frn_fdis_iu6_i1_rte_fx0[i]) & ~perf_iu6_dispatch_fx0_l2[i][1]) | + ((iu_rv_iu6_i0_vld_int[i] & fx0_send_cnt[i][0] & frn_fdis_iu6_i0_rte_fx0[i]) & (iu_rv_iu6_i1_vld_int[i] & fx0_send_cnt[i][1] & frn_fdis_iu6_i1_rte_fx0[i]) & perf_iu6_dispatch_fx0_l2[i][1]); + + assign perf_iu6_dispatch_fx1_d[i][0] = ((iu_rv_iu6_i1_vld_int[i] & fx1_send_cnt[i][1] & frn_fdis_iu6_i1_rte_fx1[i]) & perf_iu6_dispatch_fx1_l2[i][1]) | + ((iu_rv_iu6_i0_vld_int[i] & fx1_send_cnt[i][0] & frn_fdis_iu6_i0_rte_fx1[i]) & perf_iu6_dispatch_fx1_l2[i][1]) | + (iu_rv_iu6_i0_vld_int[i] & fx1_send_cnt[i][0] & frn_fdis_iu6_i0_rte_fx1[i]) & (iu_rv_iu6_i1_vld_int[i] & fx1_send_cnt[i][1] & frn_fdis_iu6_i1_rte_fx1[i]); + + assign perf_iu6_dispatch_fx1_d[i][1] = (~(iu_rv_iu6_i0_vld_int[i] & fx1_send_cnt[i][0] & frn_fdis_iu6_i0_rte_fx1[i]) & ~(iu_rv_iu6_i1_vld_int[i] & fx1_send_cnt[i][1] & frn_fdis_iu6_i1_rte_fx1[i]) & perf_iu6_dispatch_fx1_l2[i][1]) | + (~(iu_rv_iu6_i0_vld_int[i] & fx1_send_cnt[i][0] & frn_fdis_iu6_i0_rte_fx1[i]) & (iu_rv_iu6_i1_vld_int[i] & fx1_send_cnt[i][1] & frn_fdis_iu6_i1_rte_fx1[i]) & ~perf_iu6_dispatch_fx1_l2[i][1]) | + ((iu_rv_iu6_i0_vld_int[i] & fx1_send_cnt[i][0] & frn_fdis_iu6_i0_rte_fx1[i]) & ~(iu_rv_iu6_i1_vld_int[i] & fx1_send_cnt[i][1] & frn_fdis_iu6_i1_rte_fx1[i]) & ~perf_iu6_dispatch_fx1_l2[i][1]) | + ((iu_rv_iu6_i0_vld_int[i] & fx1_send_cnt[i][0] & frn_fdis_iu6_i0_rte_fx1[i]) & (iu_rv_iu6_i1_vld_int[i] & fx1_send_cnt[i][1] & frn_fdis_iu6_i1_rte_fx1[i]) & perf_iu6_dispatch_fx1_l2[i][1]); + + assign perf_iu6_dispatch_lq_d[i][0] = ((iu_rv_iu6_i1_vld_int[i] & frn_fdis_iu6_i1_rte_lq[i]) & perf_iu6_dispatch_fx1_l2[i][1]) | + ((iu_rv_iu6_i0_vld_int[i] & frn_fdis_iu6_i0_rte_lq[i]) & perf_iu6_dispatch_fx1_l2[i][1]) | + (iu_rv_iu6_i0_vld_int[i] & frn_fdis_iu6_i0_rte_lq[i]) & (iu_rv_iu6_i1_vld_int[i] & frn_fdis_iu6_i1_rte_lq[i]); + + assign perf_iu6_dispatch_lq_d[i][1] = (~(iu_rv_iu6_i0_vld_int[i] & frn_fdis_iu6_i0_rte_lq[i]) & ~(iu_rv_iu6_i1_vld_int[i] & frn_fdis_iu6_i1_rte_lq[i]) & perf_iu6_dispatch_fx0_l2[i][1]) | + (~(iu_rv_iu6_i0_vld_int[i] & frn_fdis_iu6_i0_rte_lq[i]) & (iu_rv_iu6_i1_vld_int[i] & frn_fdis_iu6_i1_rte_lq[i]) & ~perf_iu6_dispatch_fx0_l2[i][1]) | + ((iu_rv_iu6_i0_vld_int[i] & frn_fdis_iu6_i0_rte_lq[i]) & ~(iu_rv_iu6_i1_vld_int[i] & frn_fdis_iu6_i1_rte_lq[i]) & ~perf_iu6_dispatch_fx0_l2[i][1]) | + ((iu_rv_iu6_i0_vld_int[i] & frn_fdis_iu6_i0_rte_lq[i]) & (iu_rv_iu6_i1_vld_int[i] & frn_fdis_iu6_i1_rte_lq[i]) & perf_iu6_dispatch_fx0_l2[i][1]); + + assign perf_iu6_dispatch_axu0_d[i][0] = ((iu_rv_iu6_i1_vld_int[i] & frn_fdis_iu6_i1_rte_axu0[i]) & perf_iu6_dispatch_fx1_l2[i][1]) | + ((iu_rv_iu6_i0_vld_int[i] & frn_fdis_iu6_i0_rte_axu0[i]) & perf_iu6_dispatch_fx1_l2[i][1]) | + (iu_rv_iu6_i0_vld_int[i] & frn_fdis_iu6_i0_rte_axu0[i]) & (iu_rv_iu6_i1_vld_int[i] & frn_fdis_iu6_i1_rte_axu0[i]); + + assign perf_iu6_dispatch_axu0_d[i][1] = (~(iu_rv_iu6_i0_vld_int[i] & frn_fdis_iu6_i0_rte_axu0[i]) & ~(iu_rv_iu6_i1_vld_int[i] & frn_fdis_iu6_i1_rte_axu0[i]) & perf_iu6_dispatch_fx0_l2[i][1]) | + (~(iu_rv_iu6_i0_vld_int[i] & frn_fdis_iu6_i0_rte_axu0[i]) & (iu_rv_iu6_i1_vld_int[i] & frn_fdis_iu6_i1_rte_axu0[i]) & ~perf_iu6_dispatch_fx0_l2[i][1]) | + ((iu_rv_iu6_i0_vld_int[i] & frn_fdis_iu6_i0_rte_axu0[i]) & ~(iu_rv_iu6_i1_vld_int[i] & frn_fdis_iu6_i1_rte_axu0[i]) & ~perf_iu6_dispatch_fx0_l2[i][1]) | + ((iu_rv_iu6_i0_vld_int[i] & frn_fdis_iu6_i0_rte_axu0[i]) & (iu_rv_iu6_i1_vld_int[i] & frn_fdis_iu6_i1_rte_axu0[i]) & perf_iu6_dispatch_fx0_l2[i][1]); + + assign perf_iu6_dispatch_axu1_d[i][0] = ((iu_rv_iu6_i1_vld_int[i] & frn_fdis_iu6_i1_rte_axu1[i]) & perf_iu6_dispatch_fx1_l2[i][1]) | + ((iu_rv_iu6_i0_vld_int[i] & frn_fdis_iu6_i0_rte_axu1[i]) & perf_iu6_dispatch_fx1_l2[i][1]) | + (iu_rv_iu6_i0_vld_int[i] & frn_fdis_iu6_i0_rte_axu1[i]) & (iu_rv_iu6_i1_vld_int[i] & frn_fdis_iu6_i1_rte_axu1[i]); + + assign perf_iu6_dispatch_axu1_d[i][1] = (~(iu_rv_iu6_i0_vld_int[i] & frn_fdis_iu6_i0_rte_axu1[i]) & ~(iu_rv_iu6_i1_vld_int[i] & frn_fdis_iu6_i1_rte_axu1[i]) & perf_iu6_dispatch_fx0_l2[i][1]) | + (~(iu_rv_iu6_i0_vld_int[i] & frn_fdis_iu6_i0_rte_axu1[i]) & (iu_rv_iu6_i1_vld_int[i] & frn_fdis_iu6_i1_rte_axu1[i]) & ~perf_iu6_dispatch_fx0_l2[i][1]) | + ((iu_rv_iu6_i0_vld_int[i] & frn_fdis_iu6_i0_rte_axu1[i]) & ~(iu_rv_iu6_i1_vld_int[i] & frn_fdis_iu6_i1_rte_axu1[i]) & ~perf_iu6_dispatch_fx0_l2[i][1]) | + ((iu_rv_iu6_i0_vld_int[i] & frn_fdis_iu6_i0_rte_axu1[i]) & (iu_rv_iu6_i1_vld_int[i] & frn_fdis_iu6_i1_rte_axu1[i]) & perf_iu6_dispatch_fx0_l2[i][1]); + + assign perf_iu6_fx0_credit_stall_d[i] = frn_fdis_iu6_i0_vld[i] & (~fx0_credit_ok[i] | ~fx0_local_credit_ok[i]); + assign perf_iu6_fx1_credit_stall_d[i] = frn_fdis_iu6_i0_vld[i] & (~fx1_credit_ok[i] | ~fx1_local_credit_ok[i]); + assign perf_iu6_lq_credit_stall_d[i] = frn_fdis_iu6_i0_vld[i] & (~lq_cmdq_credit_ok[i] | ~lq_cmdq_local_credit_ok[i]); + assign perf_iu6_sq_credit_stall_d[i] = frn_fdis_iu6_i0_vld[i] & (~sq_cmdq_credit_ok[i] | ~sq_cmdq_local_credit_ok[i]); + assign perf_iu6_axu0_credit_stall_d[i] = frn_fdis_iu6_i0_vld[i] & (~fu0_credit_ok[i] | ~fu0_local_credit_ok[i]); + assign perf_iu6_axu1_credit_stall_d[i] = frn_fdis_iu6_i0_vld[i] & (~fu1_credit_ok[i] | ~fu1_local_credit_ok[i]); + + assign iu_pc_fx0_credit_ok_d[i] = fx0_credit_ok[i] & fx0_local_credit_ok[i]; + assign iu_pc_fx1_credit_ok_d[i] = fx1_credit_ok[i] & fx1_local_credit_ok[i]; + assign iu_pc_lq_credit_ok_d[i] = lq_cmdq_credit_ok[i] & lq_cmdq_local_credit_ok[i]; + assign iu_pc_sq_credit_ok_d[i] = sq_cmdq_credit_ok[i] & sq_cmdq_local_credit_ok[i]; + assign iu_pc_axu0_credit_ok_d[i] = fu0_credit_ok[i] & fu0_local_credit_ok[i]; + assign iu_pc_axu1_credit_ok_d[i] = fu1_credit_ok[i] & fu1_local_credit_ok[i]; + + end + end + endgenerate + + + assign perf_iu6_stall = perf_iu6_stall_l2; +`ifdef THREADS1 + assign perf_iu6_dispatch_fx0 = perf_iu6_dispatch_fx0_l2[0][0]; + assign perf_iu6_dispatch_fx1 = perf_iu6_dispatch_fx1_l2[0][0]; + assign perf_iu6_dispatch_lq = perf_iu6_dispatch_lq_l2[0][0]; + assign perf_iu6_dispatch_axu0 = perf_iu6_dispatch_axu0_l2[0][0]; + assign perf_iu6_dispatch_axu1 = perf_iu6_dispatch_axu1_l2[0][0]; +`endif +`ifndef THREADS1 + assign perf_iu6_dispatch_fx0 = {perf_iu6_dispatch_fx0_l2[0][0], perf_iu6_dispatch_fx0_l2[1][0]}; + assign perf_iu6_dispatch_fx1 = {perf_iu6_dispatch_fx1_l2[0][0], perf_iu6_dispatch_fx1_l2[1][0]}; + assign perf_iu6_dispatch_lq = {perf_iu6_dispatch_lq_l2[0][0], perf_iu6_dispatch_lq_l2[1][0]}; + assign perf_iu6_dispatch_axu0 = {perf_iu6_dispatch_axu0_l2[0][0], perf_iu6_dispatch_axu0_l2[1][0]}; + assign perf_iu6_dispatch_axu1 = {perf_iu6_dispatch_axu1_l2[0][0], perf_iu6_dispatch_axu1_l2[1][0]}; +`endif + assign perf_iu6_fx0_credit_stall = perf_iu6_fx0_credit_stall_l2; + assign perf_iu6_fx1_credit_stall = perf_iu6_fx1_credit_stall_l2; + assign perf_iu6_lq_credit_stall = perf_iu6_lq_credit_stall_l2; + assign perf_iu6_sq_credit_stall = perf_iu6_sq_credit_stall_l2; + assign perf_iu6_axu0_credit_stall = perf_iu6_axu0_credit_stall_l2; + assign perf_iu6_axu1_credit_stall = perf_iu6_axu1_credit_stall_l2; + + assign iu_pc_fx0_credit_ok = iu_pc_fx0_credit_ok_l2; + assign iu_pc_fx1_credit_ok = iu_pc_fx1_credit_ok_l2; + assign iu_pc_axu0_credit_ok = iu_pc_axu0_credit_ok_l2; + assign iu_pc_axu1_credit_ok = iu_pc_axu1_credit_ok_l2; + assign iu_pc_lq_credit_ok = iu_pc_lq_credit_ok_l2; + assign iu_pc_sq_credit_ok = iu_pc_sq_credit_ok_l2; + + + generate + begin : xhdl7 + genvar i; + for (i = 0; i <= `THREADS - 1; i = i + 1) + begin : thread_latches + tri_rlmreg_p #(.WIDTH(5), .INIT(`RV_FX0_ENTRIES - 2)) fx0_high_credit_cnt_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[fx0_high_credit_cnt_offset + 5 * i:fx0_high_credit_cnt_offset + (5 * (i + 1)-1)]), + .scout(sov[fx0_high_credit_cnt_offset + 5 * i:fx0_high_credit_cnt_offset + (5 * (i + 1)-1)]), + .din(fx0_high_credit_cnt_d[i]), + .dout(fx0_high_credit_cnt_l2[i]) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(`RV_FX1_ENTRIES - 2)) fx1_high_credit_cnt_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[fx1_high_credit_cnt_offset + 5 * i:fx1_high_credit_cnt_offset + (5 * (i + 1)-1)]), + .scout(sov[fx1_high_credit_cnt_offset + 5 * i:fx1_high_credit_cnt_offset + (5 * (i + 1)-1)]), + .din(fx1_high_credit_cnt_d[i]), + .dout(fx1_high_credit_cnt_l2[i]) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(`LDSTQ_ENTRIES - 2)) lq_cmdq_high_cnt_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[lq_cmdq_high_credit_cnt_offset + 5 * i:lq_cmdq_high_credit_cnt_offset + (5 * (i + 1)-1)]), + .scout(sov[lq_cmdq_high_credit_cnt_offset + 5 * i:lq_cmdq_high_credit_cnt_offset + (5 * (i + 1)-1)]), + .din(lq_cmdq_high_credit_cnt_d[i]), + .dout(lq_cmdq_high_credit_cnt_l2[i]) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(`STQ_ENTRIES - 2)) sq_cmdq_high_cnt_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[sq_cmdq_high_credit_cnt_offset + 5 * i:sq_cmdq_high_credit_cnt_offset + (5 * (i + 1)-1)]), + .scout(sov[sq_cmdq_high_credit_cnt_offset + 5 * i:sq_cmdq_high_credit_cnt_offset + (5 * (i + 1)-1)]), + .din(sq_cmdq_high_credit_cnt_d[i]), + .dout(sq_cmdq_high_credit_cnt_l2[i]) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(`RV_AXU0_ENTRIES - 2)) fu0_high_credit_cnt_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[fu0_high_credit_cnt_offset + 5 * i:fu0_high_credit_cnt_offset + (5 * (i + 1)-1)]), + .scout(sov[fu0_high_credit_cnt_offset + 5 * i:fu0_high_credit_cnt_offset + (5 * (i + 1)-1)]), + .din(fu0_high_credit_cnt_d[i]), + .dout(fu0_high_credit_cnt_l2[i]) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(`RV_AXU1_ENTRIES - 2)) fu1_high_credit_cnt_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[fu1_high_credit_cnt_offset + 5 * i:fu1_high_credit_cnt_offset + (5 * (i + 1)-1)]), + .scout(sov[fu1_high_credit_cnt_offset + 5 * i:fu1_high_credit_cnt_offset + (5 * (i + 1)-1)]), + .din(fu1_high_credit_cnt_d[i]), + .dout(fu1_high_credit_cnt_l2[i]) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(`RV_FX0_ENTRIES / 2)) fx0_med_credit_cnt_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[fx0_med_credit_cnt_offset + 5 * i:fx0_med_credit_cnt_offset + (5 * (i + 1)-1)]), + .scout(sov[fx0_med_credit_cnt_offset + 5 * i:fx0_med_credit_cnt_offset + (5 * (i + 1)-1)]), + .din(fx0_med_credit_cnt_d[i]), + .dout(fx0_med_credit_cnt_l2[i]) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(`RV_FX1_ENTRIES / 2)) fx1_med_credit_cnt_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[fx1_med_credit_cnt_offset + 5 * i:fx1_med_credit_cnt_offset + (5 * (i + 1)-1)]), + .scout(sov[fx1_med_credit_cnt_offset + 5 * i:fx1_med_credit_cnt_offset + (5 * (i + 1)-1)]), + .din(fx1_med_credit_cnt_d[i]), + .dout(fx1_med_credit_cnt_l2[i]) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(`LDSTQ_ENTRIES / 2)) lq_cmdq_med_cnt_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[lq_cmdq_med_credit_cnt_offset + 5 * i:lq_cmdq_med_credit_cnt_offset + (5 * (i + 1)-1)]), + .scout(sov[lq_cmdq_med_credit_cnt_offset + 5 * i:lq_cmdq_med_credit_cnt_offset + (5 * (i + 1)-1)]), + .din(lq_cmdq_med_credit_cnt_d[i]), + .dout(lq_cmdq_med_credit_cnt_l2[i]) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(`STQ_ENTRIES / 2)) sq_cmdq_med_cnt_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[sq_cmdq_med_credit_cnt_offset + 5 * i:sq_cmdq_med_credit_cnt_offset + (5 * (i + 1)-1)]), + .scout(sov[sq_cmdq_med_credit_cnt_offset + 5 * i:sq_cmdq_med_credit_cnt_offset + (5 * (i + 1)-1)]), + .din(sq_cmdq_med_credit_cnt_d[i]), + .dout(sq_cmdq_med_credit_cnt_l2[i]) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(`RV_AXU0_ENTRIES / 2)) fu0_med_credit_cnt_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[fu0_med_credit_cnt_offset + 5 * i:fu0_med_credit_cnt_offset + (5 * (i + 1)-1)]), + .scout(sov[fu0_med_credit_cnt_offset + 5 * i:fu0_med_credit_cnt_offset + (5 * (i + 1)-1)]), + .din(fu0_med_credit_cnt_d[i]), + .dout(fu0_med_credit_cnt_l2[i]) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(`RV_AXU1_ENTRIES / 2)) fu1_med_credit_cnt_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[fu1_med_credit_cnt_offset + 5 * i:fu1_med_credit_cnt_offset + (5 * (i + 1)-1)]), + .scout(sov[fu1_med_credit_cnt_offset + 5 * i:fu1_med_credit_cnt_offset + (5 * (i + 1)-1)]), + .din(fu1_med_credit_cnt_d[i]), + .dout(fu1_med_credit_cnt_l2[i]) + ); + end + end + endgenerate + + tri_rlmreg_p #(.WIDTH(5), .INIT(`RV_FX0_ENTRIES)) fx0_total_credit_cnt_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[fx0_total_credit_cnt_offset:fx0_total_credit_cnt_offset + 5 - 1]), + .scout(sov[fx0_total_credit_cnt_offset:fx0_total_credit_cnt_offset + 5 - 1]), + .din(fx0_total_credit_cnt_d), + .dout(fx0_total_credit_cnt_l2) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(`RV_FX1_ENTRIES)) fx1_total_credit_cnt_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[fx1_total_credit_cnt_offset:fx1_total_credit_cnt_offset + 5 - 1]), + .scout(sov[fx1_total_credit_cnt_offset:fx1_total_credit_cnt_offset + 5 - 1]), + .din(fx1_total_credit_cnt_d), + .dout(fx1_total_credit_cnt_l2) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(`LDSTQ_ENTRIES)) lq_cmdq_total_cnt_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[lq_cmdq_total_credit_cnt_offset:lq_cmdq_total_credit_cnt_offset + 5 - 1]), + .scout(sov[lq_cmdq_total_credit_cnt_offset:lq_cmdq_total_credit_cnt_offset + 5 - 1]), + .din(lq_cmdq_total_credit_cnt_d), + .dout(lq_cmdq_total_credit_cnt_l2) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(`STQ_ENTRIES)) sq_cmdq_total_cnt_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[sq_cmdq_total_credit_cnt_offset:sq_cmdq_total_credit_cnt_offset + 5 - 1]), + .scout(sov[sq_cmdq_total_credit_cnt_offset:sq_cmdq_total_credit_cnt_offset + 5 - 1]), + .din(sq_cmdq_total_credit_cnt_d), + .dout(sq_cmdq_total_credit_cnt_l2) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(`RV_AXU0_ENTRIES)) fu0_total_credit_cnt_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[fu0_total_credit_cnt_offset:fu0_total_credit_cnt_offset + 5 - 1]), + .scout(sov[fu0_total_credit_cnt_offset:fu0_total_credit_cnt_offset + 5 - 1]), + .din(fu0_total_credit_cnt_d), + .dout(fu0_total_credit_cnt_l2) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(`RV_AXU1_ENTRIES)) fu1_total_credit_cnt_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[fu1_total_credit_cnt_offset:fu1_total_credit_cnt_offset + 5 - 1]), + .scout(sov[fu1_total_credit_cnt_offset:fu1_total_credit_cnt_offset + 5 - 1]), + .din(fu1_total_credit_cnt_d), + .dout(fu1_total_credit_cnt_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) cp_flush_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[cp_flush_offset:cp_flush_offset + `THREADS - 1]), + .scout(sov[cp_flush_offset:cp_flush_offset + `THREADS - 1]), + .din(cp_flush), + .dout(cp_flush_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) xu_iu_run_thread_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[xu_iu_run_thread_offset:xu_iu_run_thread_offset + `THREADS - 1]), + .scout(sov[xu_iu_run_thread_offset:xu_iu_run_thread_offset + `THREADS - 1]), + .din(xu_iu_run_thread), + .dout(xu_iu_run_thread_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) iu_xu_credits_returned_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[iu_xu_credits_returned_offset]), + .scout(sov[iu_xu_credits_returned_offset]), + .din(iu_xu_credits_returned_d), + .dout(iu_xu_credits_returned_l2) + ); + + + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) dual_issue_use_fx0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[dual_issue_use_fx0_offset:dual_issue_use_fx0_offset + 2 - 1]), + .scout(sov[dual_issue_use_fx0_offset:dual_issue_use_fx0_offset + 2 - 1]), + .din(dual_issue_use_fx0_d), + .dout(dual_issue_use_fx0_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(1)) last_thread_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(last_thread_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[last_thread_offset:last_thread_offset + `THREADS - 1]), + .scout(sov[last_thread_offset:last_thread_offset + `THREADS - 1]), + .din(last_thread_d), + .dout(last_thread_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) mm_hold_req_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(funcslp_force), + .thold_b(pc_iu_func_slp_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[mm_hold_req_offset:mm_hold_req_offset + `THREADS - 1]), + .scout(sov[mm_hold_req_offset:mm_hold_req_offset + `THREADS - 1]), + .din(mm_hold_req_d), + .dout(mm_hold_req_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) mm_hold_done_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(funcslp_force), + .thold_b(pc_iu_func_slp_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[mm_hold_done_offset:mm_hold_done_offset + `THREADS - 1]), + .scout(sov[mm_hold_done_offset:mm_hold_done_offset + `THREADS - 1]), + .din(mm_hold_done_d), + .dout(mm_hold_done_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) mm_bus_snoop_hold_req_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(funcslp_force), + .thold_b(pc_iu_func_slp_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[mm_bus_snoop_hold_req_offset:mm_bus_snoop_hold_req_offset + `THREADS - 1]), + .scout(sov[mm_bus_snoop_hold_req_offset:mm_bus_snoop_hold_req_offset + `THREADS - 1]), + .din(mm_bus_snoop_hold_req_d), + .dout(mm_bus_snoop_hold_req_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) mm_bus_snoop_hold_done_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(funcslp_force), + .thold_b(pc_iu_func_slp_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[mm_bus_snoop_hold_done_offset:mm_bus_snoop_hold_done_offset + `THREADS - 1]), + .scout(sov[mm_bus_snoop_hold_done_offset:mm_bus_snoop_hold_done_offset + `THREADS - 1]), + .din(mm_bus_snoop_hold_done_d), + .dout(mm_bus_snoop_hold_done_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) hold_instructions_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[hold_instructions_offset]), + .scout(sov[hold_instructions_offset]), + .din(hold_instructions_d), + .dout(hold_instructions_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) hold_req_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[hold_req_offset:hold_req_offset + `THREADS - 1]), + .scout(sov[hold_req_offset:hold_req_offset + `THREADS - 1]), + .din(hold_req_d), + .dout(hold_req_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) ivax_hold_req_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[ivax_hold_req_offset:ivax_hold_req_offset + `THREADS - 1]), + .scout(sov[ivax_hold_req_offset:ivax_hold_req_offset + `THREADS - 1]), + .din(ivax_hold_req_d), + .dout(ivax_hold_req_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) hold_done_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[hold_done_offset:hold_done_offset + `THREADS - 1]), + .scout(sov[hold_done_offset:hold_done_offset + `THREADS - 1]), + .din(hold_done_d), + .dout(hold_done_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) mm_iu_flush_req_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(funcslp_force), + .thold_b(pc_iu_func_slp_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[mm_iu_flush_req_offset:mm_iu_flush_req_offset + `THREADS - 1]), + .scout(sov[mm_iu_flush_req_offset:mm_iu_flush_req_offset + `THREADS - 1]), + .din(mm_iu_flush_req_d), + .dout(mm_iu_flush_req_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) mm_iu_hold_done_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(funcslp_force), + .thold_b(pc_iu_func_slp_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[mm_iu_hold_done_offset:mm_iu_hold_done_offset + `THREADS - 1]), + .scout(sov[mm_iu_hold_done_offset:mm_iu_hold_done_offset + `THREADS - 1]), + .din(mm_iu_hold_done), + .dout(mm_iu_hold_done_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) mm_iu_bus_snoop_hold_req_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(funcslp_force), + .thold_b(pc_iu_func_slp_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[mm_iu_bus_snoop_hold_req_offset:mm_iu_bus_snoop_hold_req_offset + `THREADS - 1]), + .scout(sov[mm_iu_bus_snoop_hold_req_offset:mm_iu_bus_snoop_hold_req_offset + `THREADS - 1]), + .din(mm_iu_bus_snoop_hold_req_d), + .dout(mm_iu_bus_snoop_hold_req_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) mm_iu_bus_snoop_hold_done_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(funcslp_force), + .thold_b(pc_iu_func_slp_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[mm_iu_bus_snoop_hold_done_offset:mm_iu_bus_snoop_hold_done_offset + `THREADS - 1]), + .scout(sov[mm_iu_bus_snoop_hold_done_offset:mm_iu_bus_snoop_hold_done_offset + `THREADS - 1]), + .din(mm_iu_bus_snoop_hold_done), + .dout(mm_iu_bus_snoop_hold_done_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) in_ucode_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[in_ucode_offset:in_ucode_offset + `THREADS - 1]), + .scout(sov[in_ucode_offset:in_ucode_offset + `THREADS - 1]), + .din(in_ucode_d), + .dout(in_ucode_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) in_fusion_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[in_fusion_offset:in_fusion_offset + `THREADS - 1]), + .scout(sov[in_fusion_offset:in_fusion_offset + `THREADS - 1]), + .din(in_fusion_d), + .dout(in_fusion_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) total_pri_mask_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[total_pri_mask_offset:total_pri_mask_offset + `THREADS - 1]), + .scout(sov[total_pri_mask_offset:total_pri_mask_offset + `THREADS - 1]), + .din(total_pri_mask_d), + .dout(total_pri_mask_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) high_pri_mask_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[high_pri_mask_offset:high_pri_mask_offset + `THREADS - 1]), + .scout(sov[high_pri_mask_offset:high_pri_mask_offset + `THREADS - 1]), + .din(high_pri_mask_d), + .dout(high_pri_mask_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) med_pri_mask_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[med_pri_mask_offset:med_pri_mask_offset + `THREADS - 1]), + .scout(sov[med_pri_mask_offset:med_pri_mask_offset + `THREADS - 1]), + .din(med_pri_mask_d), + .dout(med_pri_mask_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) low_pri_mask_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[low_pri_mask_offset:low_pri_mask_offset + `THREADS - 1]), + .scout(sov[low_pri_mask_offset:low_pri_mask_offset + `THREADS - 1]), + .din(low_pri_mask_d), + .dout(low_pri_mask_l2) + ); + + generate + begin : low_pri_counts + genvar i; + for (i = 0; i <= `THREADS - 1; i = i + 1) + begin : thread_latches + tri_rlmreg_p #(.WIDTH(8), .INIT(0)) low_pri_cnt_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(low_pri_cnt_act[i]), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[low_pri_cnt_offset + 8 * i:low_pri_cnt_offset + (8 * (i + 1)-1)]), + .scout(sov[low_pri_cnt_offset + 8 * i:low_pri_cnt_offset + (8 * (i + 1)-1)]), + .din(low_pri_cnt_d[i]), + .dout(low_pri_cnt_l2[i]) + ); + + tri_rlmreg_p #(.WIDTH(6), .INIT(0)) low_pri_max_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[low_pri_max_offset + 6 * i:low_pri_max_offset + (6 * (i + 1)-1)]), + .scout(sov[low_pri_max_offset + 6 * i:low_pri_max_offset + (6 * (i + 1)-1)]), + .din(low_pri_max_d[i]), + .dout(low_pri_max_l2[i]) + ); + end + end + endgenerate + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) perf_iu6_stall_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pc_iu_event_bus_enable), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[perf_iu6_stall_offset:perf_iu6_stall_offset + `THREADS - 1]), + .scout(sov[perf_iu6_stall_offset:perf_iu6_stall_offset + `THREADS - 1]), + .din(perf_iu6_stall_d), + .dout(perf_iu6_stall_l2) + ); + + generate + begin : perf_counts + genvar i; + for (i = 0; i <= `THREADS - 1; i = i + 1) + begin : thread_latches + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) perf_iu6_dispatch_fx0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pc_iu_event_bus_enable), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[perf_iu6_dispatch_fx0_offset+2*i:perf_iu6_dispatch_fx0_offset + (2 * (i + 1)-1)]), + .scout(sov[perf_iu6_dispatch_fx0_offset+2*i:perf_iu6_dispatch_fx0_offset + (2 * (i + 1)-1)]), + .din(perf_iu6_dispatch_fx0_d[i]), + .dout(perf_iu6_dispatch_fx0_l2[i]) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) perf_iu6_dispatch_fx1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pc_iu_event_bus_enable), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[perf_iu6_dispatch_fx1_offset+2*i:perf_iu6_dispatch_fx1_offset + (2 * (i + 1)-1)]), + .scout(sov[perf_iu6_dispatch_fx1_offset+2*i:perf_iu6_dispatch_fx1_offset + (2 * (i + 1)-1)]), + .din(perf_iu6_dispatch_fx1_d[i]), + .dout(perf_iu6_dispatch_fx1_l2[i]) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) perf_iu6_dispatch_lq_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pc_iu_event_bus_enable), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[perf_iu6_dispatch_lq_offset+2*i:perf_iu6_dispatch_lq_offset + (2 * (i + 1)-1)]), + .scout(sov[perf_iu6_dispatch_lq_offset+2*i:perf_iu6_dispatch_lq_offset + (2 * (i + 1)-1)]), + .din(perf_iu6_dispatch_lq_d[i]), + .dout(perf_iu6_dispatch_lq_l2[i]) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) perf_iu6_dispatch_axu0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pc_iu_event_bus_enable), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[perf_iu6_dispatch_axu0_offset+2*i:perf_iu6_dispatch_axu0_offset + (2 * (i + 1)-1)]), + .scout(sov[perf_iu6_dispatch_axu0_offset+2*i:perf_iu6_dispatch_axu0_offset + (2 * (i + 1)-1)]), + .din(perf_iu6_dispatch_axu0_d[i]), + .dout(perf_iu6_dispatch_axu0_l2[i]) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) perf_iu6_dispatch_axu1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pc_iu_event_bus_enable), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[perf_iu6_dispatch_axu1_offset+2*i:perf_iu6_dispatch_axu1_offset + (2 * (i + 1)-1)]), + .scout(sov[perf_iu6_dispatch_axu1_offset+2*i:perf_iu6_dispatch_axu1_offset + (2 * (i + 1)-1)]), + .din(perf_iu6_dispatch_axu1_d[i]), + .dout(perf_iu6_dispatch_axu1_l2[i]) + ); + end + end + endgenerate + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) perf_iu6_fx0_credit_stall_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pc_iu_event_bus_enable), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[perf_iu6_fx0_credit_stall_offset:perf_iu6_fx0_credit_stall_offset + `THREADS - 1]), + .scout(sov[perf_iu6_fx0_credit_stall_offset:perf_iu6_fx0_credit_stall_offset + `THREADS - 1]), + .din(perf_iu6_fx0_credit_stall_d), + .dout(perf_iu6_fx0_credit_stall_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) perf_iu6_fx1_credit_stall_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pc_iu_event_bus_enable), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[perf_iu6_fx1_credit_stall_offset:perf_iu6_fx1_credit_stall_offset + `THREADS - 1]), + .scout(sov[perf_iu6_fx1_credit_stall_offset:perf_iu6_fx1_credit_stall_offset + `THREADS - 1]), + .din(perf_iu6_fx1_credit_stall_d), + .dout(perf_iu6_fx1_credit_stall_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) perf_iu6_lq_credit_stall_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pc_iu_event_bus_enable), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[perf_iu6_lq_credit_stall_offset:perf_iu6_lq_credit_stall_offset + `THREADS - 1]), + .scout(sov[perf_iu6_lq_credit_stall_offset:perf_iu6_lq_credit_stall_offset + `THREADS - 1]), + .din(perf_iu6_lq_credit_stall_d), + .dout(perf_iu6_lq_credit_stall_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) perf_iu6_sq_credit_stall_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pc_iu_event_bus_enable), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[perf_iu6_sq_credit_stall_offset:perf_iu6_sq_credit_stall_offset + `THREADS - 1]), + .scout(sov[perf_iu6_sq_credit_stall_offset:perf_iu6_sq_credit_stall_offset + `THREADS - 1]), + .din(perf_iu6_sq_credit_stall_d), + .dout(perf_iu6_sq_credit_stall_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) perf_iu6_axu0_credit_stall_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pc_iu_event_bus_enable), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[perf_iu6_axu0_credit_stall_offset:perf_iu6_axu0_credit_stall_offset + `THREADS - 1]), + .scout(sov[perf_iu6_axu0_credit_stall_offset:perf_iu6_axu0_credit_stall_offset + `THREADS - 1]), + .din(perf_iu6_axu0_credit_stall_d), + .dout(perf_iu6_axu0_credit_stall_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) perf_iu6_axu1_credit_stall_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pc_iu_event_bus_enable), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[perf_iu6_axu1_credit_stall_offset:perf_iu6_axu1_credit_stall_offset + `THREADS - 1]), + .scout(sov[perf_iu6_axu1_credit_stall_offset:perf_iu6_axu1_credit_stall_offset + `THREADS - 1]), + .din(perf_iu6_axu1_credit_stall_d), + .dout(perf_iu6_axu1_credit_stall_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu_pc_fx0_credit_ok_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[iu_pc_fx0_credit_ok_offset:iu_pc_fx0_credit_ok_offset + `THREADS - 1]), + .scout(sov[iu_pc_fx0_credit_ok_offset:iu_pc_fx0_credit_ok_offset + `THREADS - 1]), + .din(iu_pc_fx0_credit_ok_d), + .dout(iu_pc_fx0_credit_ok_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu_pc_fx1_credit_ok_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[iu_pc_fx1_credit_ok_offset:iu_pc_fx1_credit_ok_offset + `THREADS - 1]), + .scout(sov[iu_pc_fx1_credit_ok_offset:iu_pc_fx1_credit_ok_offset + `THREADS - 1]), + .din(iu_pc_fx1_credit_ok_d), + .dout(iu_pc_fx1_credit_ok_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu_pc_lq_credit_ok_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[iu_pc_lq_credit_ok_offset:iu_pc_lq_credit_ok_offset + `THREADS - 1]), + .scout(sov[iu_pc_lq_credit_ok_offset:iu_pc_lq_credit_ok_offset + `THREADS - 1]), + .din(iu_pc_lq_credit_ok_d), + .dout(iu_pc_lq_credit_ok_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu_pc_sq_credit_ok_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[iu_pc_sq_credit_ok_offset:iu_pc_sq_credit_ok_offset + `THREADS - 1]), + .scout(sov[iu_pc_sq_credit_ok_offset:iu_pc_sq_credit_ok_offset + `THREADS - 1]), + .din(iu_pc_sq_credit_ok_d), + .dout(iu_pc_sq_credit_ok_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu_pc_axu0_credit_ok_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[iu_pc_axu0_credit_ok_offset:iu_pc_axu0_credit_ok_offset + `THREADS - 1]), + .scout(sov[iu_pc_axu0_credit_ok_offset:iu_pc_axu0_credit_ok_offset + `THREADS - 1]), + .din(iu_pc_axu0_credit_ok_d), + .dout(iu_pc_axu0_credit_ok_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu_pc_axu1_credit_ok_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[iu_pc_axu1_credit_ok_offset:iu_pc_axu1_credit_ok_offset + `THREADS - 1]), + .scout(sov[iu_pc_axu1_credit_ok_offset:iu_pc_axu1_credit_ok_offset + `THREADS - 1]), + .din(iu_pc_axu1_credit_ok_d), + .dout(iu_pc_axu1_credit_ok_l2) + ); + + + + //----------------------------------------------- + // pervasive + //----------------------------------------------- + + tri_plat #(.WIDTH(3)) perv_2to1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + .din({pc_iu_func_sl_thold_2, pc_iu_func_slp_sl_thold_2, pc_iu_sg_2}), + .q({pc_iu_func_sl_thold_1, pc_iu_func_slp_sl_thold_1, pc_iu_sg_1}) + ); + + tri_plat #(.WIDTH(3)) perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + .din({pc_iu_func_sl_thold_1, pc_iu_func_slp_sl_thold_1, pc_iu_sg_1}), + .q({pc_iu_func_sl_thold_0, pc_iu_func_slp_sl_thold_0, pc_iu_sg_0}) + ); + + tri_lcbor perv_lcbor_sl( + .clkoff_b(clkoff_b), + .thold(pc_iu_func_sl_thold_0), + .sg(pc_iu_sg_0), + .act_dis(act_dis), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b) + ); + + tri_lcbor perv_lcbor_slp_sl( + .clkoff_b(clkoff_b), + .thold(pc_iu_func_slp_sl_thold_0), + .sg(pc_iu_sg_0), + .act_dis(act_dis), + .force_t(funcslp_force), + .thold_b(pc_iu_func_slp_sl_thold_0_b) + ); + + //--------------------------------------------------------------------- + // Scan + //--------------------------------------------------------------------- + assign siv[0:scan_right] = {sov[1:scan_right], scan_in}; + assign scan_out = sov[0]; +endmodule diff --git a/dev/verilog/work/iuq_ibuf.v b/dev/verilog/work/iuq_ibuf.v new file mode 100755 index 0000000..6e796b5 --- /dev/null +++ b/dev/verilog/work/iuq_ibuf.v @@ -0,0 +1,1408 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//******************************************************************** +//* +//* TITLE: Instruction Buffer +//* +//* NAME: iuq_ibuf.v +//* +//********************************************************************* + +`include "tri_a2o.vh" + +module iuq_ibuf( + inout vdd, + inout gnd, + input [0:`NCLK_WIDTH-1] nclk, + input pc_iu_sg_2, + input pc_iu_func_sl_thold_2, + input clkoff_b, + input act_dis, + input tc_ac_ccflush_dc, + input d_mode, + input delay_lclkr, + input mpw1_b, + input mpw2_b, + input scan_in, + output scan_out, + + output ib_rm_rdy, + input rm_ib_iu3_val, + input [0:35] rm_ib_iu3_instr, + + input [0:3] uc_ib_iu3_invalid, + input cp_iu_iu3_flush, + input cp_flush_into_uc, + input br_iu_redirect, + input id_ib_iu4_stall, + input uc_ib_iu3_flush_all, + + output [0:(`IBUFF_DEPTH/4)-1] ib_ic_need_fetch, + + input [62-`EFF_IFAR_WIDTH:61] bp_ib_iu3_ifar, + input [0:3] bp_ib_iu3_val, + input [0:`IBUFF_INSTR_WIDTH-1] bp_ib_iu3_0_instr, + input [0:`IBUFF_INSTR_WIDTH-1] bp_ib_iu3_1_instr, + input [0:`IBUFF_INSTR_WIDTH-1] bp_ib_iu3_2_instr, + input [0:`IBUFF_INSTR_WIDTH-1] bp_ib_iu3_3_instr, + input [62-`EFF_IFAR_WIDTH:61] bp_ib_iu3_bta, + + output ib_uc_rdy, + input [0:1] uc_ib_val, + input uc_ib_done, + input [0:31] uc_ib_instr0, + input [0:31] uc_ib_instr1, + input [62-`EFF_IFAR_WIDTH:61] uc_ib_ifar0, + input [62-`EFF_IFAR_WIDTH:61] uc_ib_ifar1, + input [0:3] uc_ib_ext0, + input [0:3] uc_ib_ext1, + + output ib_id_iu4_0_valid, + output [62-`EFF_IFAR_WIDTH:61] ib_id_iu4_0_ifar, + output [62-`EFF_IFAR_WIDTH:61] ib_id_iu4_0_bta, + output [0:`IBUFF_INSTR_WIDTH-1] ib_id_iu4_0_instr, + output [0:2] ib_id_iu4_0_ucode, + output [0:3] ib_id_iu4_0_ucode_ext, + output ib_id_iu4_0_isram, + output ib_id_iu4_0_fuse_val, + output [0:31] ib_id_iu4_0_fuse_data, + + output ib_id_iu4_1_valid, + output [62-`EFF_IFAR_WIDTH:61] ib_id_iu4_1_ifar, + output [62-`EFF_IFAR_WIDTH:61] ib_id_iu4_1_bta, + output [0:`IBUFF_INSTR_WIDTH-1] ib_id_iu4_1_instr, + output [0:2] ib_id_iu4_1_ucode, + output [0:3] ib_id_iu4_1_ucode_ext, + output ib_id_iu4_1_isram, + output ib_id_iu4_1_fuse_val, + output [0:31] ib_id_iu4_1_fuse_data + ); + + // buffer constants + parameter IDATA_WIDTH = (`IBUFF_INSTR_WIDTH + `EFF_IFAR_WIDTH + `EFF_IFAR_WIDTH); + parameter IBUFF_WIDTH = (`IBUFF_INSTR_WIDTH + `EFF_IFAR_WIDTH + `IBUFF_IFAR_WIDTH); + parameter IBUFF_DEPTH = (`IBUFF_DEPTH); + + // types for configurable width/depth + + wire cp_flush_d; + wire cp_flush_q; + wire br_iu_redirect_d; + wire br_iu_redirect_q; + + // incoming valid + wire [0:3] iu3_val; + + // incoming stall + wire iu4_stall; + + // buffer latches + reg [0:IBUFF_WIDTH-1] buffer_data_din[0:`IBUFF_DEPTH-1]; + reg [0:IBUFF_WIDTH-1] buffer_data_d[0:`IBUFF_DEPTH-1]; + reg [0:IBUFF_WIDTH-1] buffer_data_q[0:`IBUFF_DEPTH-1]; + wire buffer_valid_act; + wire [0:`IBUFF_DEPTH-1] buffer_valid_din; + wire [0:`IBUFF_DEPTH-1] buffer_valid_d; + wire [0:`IBUFF_DEPTH-1] buffer_valid_q; + wire buffer_head_act; + wire [0:`IBUFF_DEPTH-1] buffer_head_din; + wire [0:`IBUFF_DEPTH-1] buffer_head_d; + wire [0:IBUFF_DEPTH-1] buffer_head_q; + wire buffer_tail_act; + wire [0:`IBUFF_DEPTH-1] buffer_tail_din; + wire [0:`IBUFF_DEPTH-1] buffer_tail_d; + wire [0:IBUFF_DEPTH-1] buffer_tail_q; + reg [0:`IBUFF_DEPTH*IBUFF_WIDTH-1] buffer_array_d; + wire [0:`IBUFF_DEPTH*IBUFF_WIDTH-1] buffer_array_q; + + // stall buffer + wire [0:IDATA_WIDTH-1] stall_buffer_data0_d; + wire [0:IDATA_WIDTH-1] stall_buffer_data0_q; + wire [0:IDATA_WIDTH-1] stall_buffer_data1_d; + wire [0:IDATA_WIDTH-1] stall_buffer_data1_q; + wire [0:1] stall_d; + wire [0:1] stall_q; + wire [0:1] stall_buffer_act; + + // buffer control + wire buffer_valid_flush; + wire [0:2] buffer_advance; + wire [0:2] buffer_bypass; + + // ifar extension bits + wire [60:61] ifar_1_ext; + wire [60:61] ifar_2_ext; + wire [60:61] ifar_3_ext; + + // data/valid in + wire [0:3] valid_in; + wire [0:IBUFF_WIDTH-1] data0_in; + wire [0:IBUFF_WIDTH-1] data1_in; + wire [0:IBUFF_WIDTH-1] data2_in; + wire [0:IBUFF_WIDTH-1] data3_in; + wire [0:IDATA_WIDTH-1] fast_data0; + wire [0:IDATA_WIDTH-1] fast_data1; + + // data/valid out + wire [0:1] valid_int; + wire [0:1] valid_out; + wire [0:IDATA_WIDTH-1] data0_out; + wire [0:IDATA_WIDTH-1] data1_out; + wire [0:IBUFF_WIDTH-1] buffer0_ibuff_data; + wire [0:IBUFF_WIDTH-1] buffer1_ibuff_data; + wire [0:IDATA_WIDTH-1] buffer0_data; + wire [0:IDATA_WIDTH-1] buffer1_data; + reg [0:IBUFF_WIDTH-1] buffer0_data_muxed[0:`IBUFF_DEPTH-1]; + reg [0:IBUFF_WIDTH-1] buffer1_data_muxed[0:`IBUFF_DEPTH-1]; + + // output latches + wire iu4_0_valid_din; + reg iu4_0_valid_d; + wire iu4_0_valid_q; + wire [0:`IBUFF_INSTR_WIDTH-1] iu4_0_instr_din; + reg [0:`IBUFF_INSTR_WIDTH-1] iu4_0_instr_d; + wire [0:`IBUFF_INSTR_WIDTH-1] iu4_0_instr_q; + wire [62-`EFF_IFAR_WIDTH:61] iu4_0_ifar_din; + reg [62-`EFF_IFAR_WIDTH:61] iu4_0_ifar_d; + wire [62-`EFF_IFAR_WIDTH:61] iu4_0_ifar_q; + wire [62-`EFF_IFAR_WIDTH:61] iu4_0_bta_din; + reg [62-`EFF_IFAR_WIDTH:61] iu4_0_bta_d; + wire [62-`EFF_IFAR_WIDTH:61] iu4_0_bta_q; + wire [0:2] iu4_0_ucode_din; + reg [0:2] iu4_0_ucode_d; + wire [0:2] iu4_0_ucode_q; + wire [0:3] iu4_0_ucode_ext_din; + reg [0:3] iu4_0_ucode_ext_d; + wire [0:3] iu4_0_ucode_ext_q; + wire iu4_0_isram_din; + reg iu4_0_isram_d; + wire iu4_0_isram_q; + wire iu4_0_fuse_val_din; + reg iu4_0_fuse_val_d; + wire iu4_0_fuse_val_q; + wire [0:31] iu4_0_fuse_data_din; + reg [0:31] iu4_0_fuse_data_d; + wire [0:31] iu4_0_fuse_data_q; + + wire iu4_1_valid_din; + reg iu4_1_valid_d; + wire iu4_1_valid_q; + wire [0:`IBUFF_INSTR_WIDTH-1] iu4_1_instr_din; + reg [0:`IBUFF_INSTR_WIDTH-1] iu4_1_instr_d; + wire [0:`IBUFF_INSTR_WIDTH-1] iu4_1_instr_q; + wire [62-`EFF_IFAR_WIDTH:61] iu4_1_ifar_din; + reg [62-`EFF_IFAR_WIDTH:61] iu4_1_ifar_d; + wire [62-`EFF_IFAR_WIDTH:61] iu4_1_ifar_q; + wire [62-`EFF_IFAR_WIDTH:61] iu4_1_bta_din; + reg [62-`EFF_IFAR_WIDTH:61] iu4_1_bta_d; + wire [62-`EFF_IFAR_WIDTH:61] iu4_1_bta_q; + wire [0:2] iu4_1_ucode_din; + reg [0:2] iu4_1_ucode_d; + wire [0:2] iu4_1_ucode_q; + wire [0:3] iu4_1_ucode_ext_din; + reg [0:3] iu4_1_ucode_ext_d; + wire [0:3] iu4_1_ucode_ext_q; + wire iu4_1_isram_din; + reg iu4_1_isram_d; + wire iu4_1_isram_q; + wire iu4_1_fuse_val_din; + reg iu4_1_fuse_val_d; + wire iu4_1_fuse_val_q; + wire [0:31] iu4_1_fuse_data_din; + reg [0:31] iu4_1_fuse_data_d; + wire [0:31] iu4_1_fuse_data_q; + + wire uc_select_d; + wire uc_select_q; + + // ucode + wire [0:1] iu4_uc_mode_din; + reg [0:1] iu4_uc_mode_d; + wire [0:1] iu4_uc_mode_q; + + wire [0:1] ucode_out; + wire [0:1] uc_hole; + wire uc_stall; + wire uc_select; + wire uc_swap; + + wire [0:1] cp_flush_into_uc_delay_d; + wire [0:1] cp_flush_into_uc_delay_q; + + // error + wire [0:1] error_hole; + wire [0:2] error0_out; + wire [0:2] error1_out; + + // fusion + wire [0:1] fuse_en; + + // Pervasive + wire pc_iu_func_sl_thold_1; + wire pc_iu_func_sl_thold_0; + wire pc_iu_func_sl_thold_0_b; + wire pc_iu_sg_1; + wire pc_iu_sg_0; + wire force_t; + + // ties + wire tiup; + + // scan chain + parameter uc_select_offset = 0; + parameter buffer_valid_offset = uc_select_offset + 1; + parameter buffer_head_offset = buffer_valid_offset + `IBUFF_DEPTH; + parameter buffer_tail_offset = buffer_head_offset + `IBUFF_DEPTH; + parameter buffer_array_offset = buffer_tail_offset + `IBUFF_DEPTH; + parameter stall_offset = buffer_array_offset + (`IBUFF_DEPTH*IBUFF_WIDTH-1+1); + parameter stall_buffer_data0_offset = stall_offset + 2; + parameter stall_buffer_data1_offset = stall_buffer_data0_offset + IDATA_WIDTH; + parameter iu4_uc_mode_offset = stall_buffer_data1_offset + IDATA_WIDTH; + parameter iu4_0_valid_offset = iu4_uc_mode_offset + 2; + parameter iu4_0_instr_offset = iu4_0_valid_offset + 1; + parameter iu4_0_ifar_offset = iu4_0_instr_offset + `IBUFF_INSTR_WIDTH; + parameter iu4_0_bta_offset = iu4_0_ifar_offset + `EFF_IFAR_WIDTH; + parameter iu4_0_ucode_offset = iu4_0_bta_offset + `EFF_IFAR_WIDTH; + parameter iu4_0_ucode_ext_offset = iu4_0_ucode_offset + 3; + parameter iu4_0_isram_offset = iu4_0_ucode_ext_offset + 4; + parameter iu4_0_fuse_val_offset = iu4_0_isram_offset + 1; + parameter iu4_0_fuse_data_offset = iu4_0_fuse_val_offset + 1; + parameter iu4_1_valid_offset = iu4_0_fuse_data_offset + 32; + parameter iu4_1_instr_offset = iu4_1_valid_offset + 1; + parameter iu4_1_ifar_offset = iu4_1_instr_offset + `IBUFF_INSTR_WIDTH; + parameter iu4_1_bta_offset = iu4_1_ifar_offset + `EFF_IFAR_WIDTH; + parameter iu4_1_ucode_offset = iu4_1_bta_offset + `EFF_IFAR_WIDTH; + parameter iu4_1_ucode_ext_offset = iu4_1_ucode_offset + 3; + parameter iu4_1_isram_offset = iu4_1_ucode_ext_offset + 4; + parameter iu4_1_fuse_val_offset = iu4_1_isram_offset + 1; + parameter iu4_1_fuse_data_offset = iu4_1_fuse_val_offset + 1; + parameter cp_flush_offset = iu4_1_fuse_data_offset + 32; + parameter br_iu_redirect_offset = cp_flush_offset + 1; + parameter cp_flush_into_uc_offset = br_iu_redirect_offset + 1; + parameter scan_right = cp_flush_into_uc_offset + 2 - 1; + + // scan + wire [0:scan_right] siv; + wire [0:scan_right] sov; + + //wtf:icarus $dumpvars cannot dump a vpiMemory + generate + genvar i; + for (i = 0; i < IBUFF_DEPTH; i=i+1) begin: ibuf + wire [0:IBUFF_WIDTH-1] q; + assign q = buffer_data_q[i]; + end + endgenerate + + //--------------------------------------------------------------------- + // Logic + //--------------------------------------------------------------------- + + //tidn <= '0'; + assign tiup = 1'b1; + + assign cp_flush_d = cp_iu_iu3_flush | uc_ib_iu3_flush_all; + assign br_iu_redirect_d = br_iu_redirect & (~(cp_flush_q)); + assign cp_flush_into_uc_delay_d = {(cp_flush_into_uc), (cp_flush_into_uc_delay_q[0] & (~(cp_iu_iu3_flush)))}; + + //-------------------------------------- + // incoming valid + //-------------------------------------- + + assign iu3_val = bp_ib_iu3_val & (~uc_ib_iu3_invalid); + + //-------------------------------------- + // ibuff control + //-------------------------------------- + + assign ifar_1_ext = (bp_ib_iu3_ifar[60:61] == 2'b10) ? 2'b11 : + (bp_ib_iu3_ifar[60:61] == 2'b01) ? 2'b10 : + 2'b01; + assign ifar_2_ext = {1'b1, bp_ib_iu3_ifar[61]}; + assign ifar_3_ext = 2'b11; + + assign buffer_valid_flush = cp_flush_q | br_iu_redirect_q; + + assign buffer_advance[0] = stall_q[1]; + assign buffer_advance[1] = stall_q[0] & (~stall_q[1]); + assign buffer_advance[2] = (~stall_q[0]) & (~stall_q[1]); + + //-------------------------------------- + // ibuff + //-------------------------------------- + + //set latch inputs + assign buffer_head_d = (buffer_valid_flush == 1'b1) ? {1'b1, {(`IBUFF_DEPTH-1){1'b0}}} : + buffer_head_din[0:`IBUFF_DEPTH - 1]; + assign buffer_tail_d = (buffer_valid_flush == 1'b1) ? {1'b1, {(`IBUFF_DEPTH-1){1'b0}}} : + buffer_tail_din[0:`IBUFF_DEPTH - 1]; + assign buffer_valid_d = ((~buffer_valid_flush) ? buffer_valid_din[0:`IBUFF_DEPTH - 1] : 0 ); + + //construct buffer data + assign data0_in[0:IBUFF_WIDTH - 1] = {bp_ib_iu3_0_instr[0:`IBUFF_INSTR_WIDTH - 1], bp_ib_iu3_bta, bp_ib_iu3_ifar[62 - `IBUFF_IFAR_WIDTH:61]}; + assign data1_in[0:IBUFF_WIDTH - 1] = {bp_ib_iu3_1_instr[0:`IBUFF_INSTR_WIDTH - 1], bp_ib_iu3_bta, bp_ib_iu3_ifar[62 - `IBUFF_IFAR_WIDTH:59], ifar_1_ext[60:61]}; + assign data2_in[0:IBUFF_WIDTH - 1] = {bp_ib_iu3_2_instr[0:`IBUFF_INSTR_WIDTH - 1], bp_ib_iu3_bta, bp_ib_iu3_ifar[62 - `IBUFF_IFAR_WIDTH:59], ifar_2_ext[60:61]}; + assign data3_in[0:IBUFF_WIDTH - 1] = {bp_ib_iu3_3_instr[0:`IBUFF_INSTR_WIDTH - 1], bp_ib_iu3_bta, bp_ib_iu3_ifar[62 - `IBUFF_IFAR_WIDTH:59], ifar_3_ext[60:61]}; + + //construct fastpath/stall data + assign fast_data0[0:IDATA_WIDTH - 1] = {bp_ib_iu3_0_instr[0:`IBUFF_INSTR_WIDTH - 1], bp_ib_iu3_bta, bp_ib_iu3_ifar[62 - `EFF_IFAR_WIDTH:61]}; + assign fast_data1[0:IDATA_WIDTH - 1] = {bp_ib_iu3_1_instr[0:`IBUFF_INSTR_WIDTH - 1], bp_ib_iu3_bta, bp_ib_iu3_ifar[62 - `EFF_IFAR_WIDTH:59], ifar_1_ext[60:61]}; + + assign valid_in[0:3] = iu3_val[0:3]; + + assign buffer_valid_act = buffer_valid_flush | valid_in[0] | (buffer_valid_q[0] & (buffer_advance[1] | buffer_advance[2])); + + //wtf update for IBUFF_DEPTH < 5 + assign buffer_valid_din[0:`IBUFF_DEPTH - 1] = (buffer_advance[0] == 1'b1 & valid_in[3] == 1'b1) ? {4'b1111, buffer_valid_q[0:`IBUFF_DEPTH - 5]} : + (buffer_advance[1] == 1'b1 & valid_in[3] == 1'b1) ? {3'b111, buffer_valid_q[0:`IBUFF_DEPTH - 4]} : + (buffer_advance[2] == 1'b1 & valid_in[3] == 1'b1) ? {2'b11, buffer_valid_q[0:`IBUFF_DEPTH - 3]} : + (buffer_advance[0] == 1'b1 & valid_in[2] == 1'b1) ? {3'b111, buffer_valid_q[0:`IBUFF_DEPTH - 4]} : + (buffer_advance[1] == 1'b1 & valid_in[2] == 1'b1) ? {2'b11, buffer_valid_q[0:`IBUFF_DEPTH - 3]} : + (buffer_advance[2] == 1'b1 & valid_in[2] == 1'b1) ? {1'b1, buffer_valid_q[0:`IBUFF_DEPTH - 2]} : + (buffer_advance[0] == 1'b1 & valid_in[1] == 1'b1) ? {2'b11, buffer_valid_q[0:`IBUFF_DEPTH - 3]} : + (buffer_advance[1] == 1'b1 & valid_in[1] == 1'b1) ? {1'b1, buffer_valid_q[0:`IBUFF_DEPTH - 2]} : + (buffer_advance[2] == 1'b1 & valid_in[1] == 1'b1) ? buffer_valid_q[0:`IBUFF_DEPTH - 1] : + (buffer_advance[0] == 1'b1 & valid_in[0] == 1'b1) ? {1'b1, buffer_valid_q[0:`IBUFF_DEPTH - 2]} : + (buffer_advance[1] == 1'b1 & valid_in[0] == 1'b1) ? buffer_valid_q[0:`IBUFF_DEPTH - 1] : + (buffer_advance[2] == 1'b1 & valid_in[0] == 1'b1) ? {buffer_valid_q[1:`IBUFF_DEPTH - 1], 1'b0} : + (buffer_advance[0] == 1'b1 & valid_in[0] == 1'b0) ? buffer_valid_q[0:`IBUFF_DEPTH - 1] : + (buffer_advance[1] == 1'b1 & valid_in[0] == 1'b0) ? {buffer_valid_q[1:`IBUFF_DEPTH - 1], 1'b0} : + {buffer_valid_q[2:`IBUFF_DEPTH - 1], 2'b00}; + + assign buffer_bypass[2] = (buffer_advance[2] == 1'b1 & buffer_valid_q[0] == 1'b0); + assign buffer_bypass[1] = (buffer_advance[2] == 1'b1 & buffer_valid_q[0] == 1'b1 & buffer_valid_q[1] == 1'b0) | (buffer_advance[1] == 1'b1 & buffer_valid_q[0] == 1'b0); + assign buffer_bypass[0] = (buffer_advance[2] == 1'b1 & buffer_valid_q[1] == 1'b1) | (buffer_advance[1] == 1'b1 & buffer_valid_q[0] == 1'b1) | (buffer_advance[0] == 1'b1); + + assign buffer_head_act = buffer_valid_flush | valid_in[0]; + + //wtf update for IBUFF_DEPTH < 5 + assign buffer_head_din[0:`IBUFF_DEPTH - 1] = (buffer_bypass[2] == 1'b1 & valid_in[3] == 1'b1) ? {buffer_head_q[`IBUFF_DEPTH - 2:`IBUFF_DEPTH - 1], buffer_head_q[0:`IBUFF_DEPTH - 3]} : + (buffer_bypass[2] == 1'b1 & valid_in[2] == 1'b1) ? {buffer_head_q[`IBUFF_DEPTH - 1], buffer_head_q[0:`IBUFF_DEPTH - 2]} : + (buffer_bypass[1] == 1'b1 & valid_in[3] == 1'b1) ? {buffer_head_q[`IBUFF_DEPTH - 3:`IBUFF_DEPTH - 1], buffer_head_q[0:`IBUFF_DEPTH - 4]} : + (buffer_bypass[1] == 1'b1 & valid_in[2] == 1'b1) ? {buffer_head_q[`IBUFF_DEPTH - 2:`IBUFF_DEPTH - 1], buffer_head_q[0:`IBUFF_DEPTH - 3]} : + (buffer_bypass[1] == 1'b1 & valid_in[1] == 1'b1) ? {buffer_head_q[`IBUFF_DEPTH - 1], buffer_head_q[0:`IBUFF_DEPTH - 2]} : + (buffer_bypass[0] == 1'b1 & valid_in[3] == 1'b1) ? {buffer_head_q[`IBUFF_DEPTH - 4:`IBUFF_DEPTH - 1], buffer_head_q[0:`IBUFF_DEPTH - 5]} : + (buffer_bypass[0] == 1'b1 & valid_in[2] == 1'b1) ? {buffer_head_q[`IBUFF_DEPTH - 3:`IBUFF_DEPTH - 1], buffer_head_q[0:`IBUFF_DEPTH - 4]} : + (buffer_bypass[0] == 1'b1 & valid_in[1] == 1'b1) ? {buffer_head_q[`IBUFF_DEPTH - 2:`IBUFF_DEPTH - 1], buffer_head_q[0:`IBUFF_DEPTH - 3]} : + (buffer_bypass[0] == 1'b1 & valid_in[0] == 1'b1) ? {buffer_head_q[`IBUFF_DEPTH - 1], buffer_head_q[0:`IBUFF_DEPTH - 2]} : + buffer_head_q[0:`IBUFF_DEPTH - 1]; + + assign buffer_tail_act = buffer_valid_flush | (buffer_valid_q[0] & (buffer_advance[1] | buffer_advance[2])); + + assign buffer_tail_din[0:`IBUFF_DEPTH - 1] = (buffer_advance[2] == 1'b1 & buffer_valid_q[1] == 1'b1) ? {buffer_tail_q[`IBUFF_DEPTH - 2:`IBUFF_DEPTH - 1], buffer_tail_q[0:`IBUFF_DEPTH - 3]} : + (buffer_advance[2] == 1'b1 & buffer_valid_q[0] == 1'b1) ? {buffer_tail_q[`IBUFF_DEPTH - 1], buffer_tail_q[0:`IBUFF_DEPTH - 2]} : + (buffer_advance[1] == 1'b1 & buffer_valid_q[0] == 1'b1) ? {buffer_tail_q[`IBUFF_DEPTH - 1], buffer_tail_q[0:`IBUFF_DEPTH - 2]} : + buffer_tail_q[0:`IBUFF_DEPTH - 1]; + + //configurable depth buffer + generate + begin : xhdl1 + genvar i; + for (i = 0; i <= `IBUFF_DEPTH - 1; i = i + 1) + begin : buffer_gen + always @( * ) + begin + if (i == 0) + begin : b0 + + buffer_data_din[0] = (buffer_bypass[0] == 1'b1 & buffer_head_q[0] == 1'b1) ? data0_in : + (buffer_bypass[0] == 1'b1 & buffer_head_q[`IBUFF_DEPTH - 1] == 1'b1) ? data1_in : + (buffer_bypass[0] == 1'b1 & buffer_head_q[`IBUFF_DEPTH - 2] == 1'b1) ? data2_in : + (buffer_bypass[0] == 1'b1 & buffer_head_q[`IBUFF_DEPTH - 3] == 1'b1) ? data3_in : + (buffer_bypass[1] == 1'b1 & buffer_head_q[0] == 1'b1) ? data1_in : + (buffer_bypass[1] == 1'b1 & buffer_head_q[`IBUFF_DEPTH - 1] == 1'b1) ? data2_in : + (buffer_bypass[1] == 1'b1 & buffer_head_q[`IBUFF_DEPTH - 2] == 1'b1) ? data3_in : + (buffer_bypass[2] == 1'b1 & buffer_head_q[0] == 1'b1) ? data2_in : + (buffer_bypass[2] == 1'b1 & buffer_head_q[`IBUFF_DEPTH - 1] == 1'b1) ? data3_in : + buffer_data_q[0]; + end + + if (i == 1) + begin : b1 + buffer_data_din[1] = (buffer_bypass[0] == 1'b1 & buffer_head_q[1] == 1'b1) ? data0_in : + (buffer_bypass[0] == 1'b1 & buffer_head_q[0] == 1'b1) ? data1_in : + (buffer_bypass[0] == 1'b1 & buffer_head_q[`IBUFF_DEPTH - 1] == 1'b1) ? data2_in : + (buffer_bypass[0] == 1'b1 & buffer_head_q[`IBUFF_DEPTH - 2] == 1'b1) ? data3_in : + (buffer_bypass[1] == 1'b1 & buffer_head_q[1] == 1'b1) ? data1_in : + (buffer_bypass[1] == 1'b1 & buffer_head_q[0] == 1'b1) ? data2_in : + (buffer_bypass[1] == 1'b1 & buffer_head_q[`IBUFF_DEPTH - 1] == 1'b1) ? data3_in : + (buffer_bypass[2] == 1'b1 & buffer_head_q[1] == 1'b1) ? data2_in : + (buffer_bypass[2] == 1'b1 & buffer_head_q[0] == 1'b1) ? data3_in : + buffer_data_q[1]; + end + + if (i == 2) + begin : b2 + buffer_data_din[2] = (buffer_bypass[0] == 1'b1 & buffer_head_q[2] == 1'b1) ? data0_in : + (buffer_bypass[0] == 1'b1 & buffer_head_q[1] == 1'b1) ? data1_in : + (buffer_bypass[0] == 1'b1 & buffer_head_q[0] == 1'b1) ? data2_in : + (buffer_bypass[0] == 1'b1 & buffer_head_q[`IBUFF_DEPTH - 1] == 1'b1) ? data3_in : + (buffer_bypass[1] == 1'b1 & buffer_head_q[2] == 1'b1) ? data1_in : + (buffer_bypass[1] == 1'b1 & buffer_head_q[1] == 1'b1) ? data2_in : + (buffer_bypass[1] == 1'b1 & buffer_head_q[0] == 1'b1) ? data3_in : + (buffer_bypass[2] == 1'b1 & buffer_head_q[2] == 1'b1) ? data2_in : + (buffer_bypass[2] == 1'b1 & buffer_head_q[1] == 1'b1) ? data3_in : + buffer_data_q[2]; + end + + if (i == 3) + begin : b3 + buffer_data_din[3] = (buffer_bypass[0] == 1'b1 & buffer_head_q[3] == 1'b1) ? data0_in : + (buffer_bypass[0] == 1'b1 & buffer_head_q[2] == 1'b1) ? data1_in : + (buffer_bypass[0] == 1'b1 & buffer_head_q[1] == 1'b1) ? data2_in : + (buffer_bypass[0] == 1'b1 & buffer_head_q[0] == 1'b1) ? data3_in : + (buffer_bypass[1] == 1'b1 & buffer_head_q[3] == 1'b1) ? data1_in : + (buffer_bypass[1] == 1'b1 & buffer_head_q[2] == 1'b1) ? data2_in : + (buffer_bypass[1] == 1'b1 & buffer_head_q[1] == 1'b1) ? data3_in : + (buffer_bypass[2] == 1'b1 & buffer_head_q[3] == 1'b1) ? data2_in : + (buffer_bypass[2] == 1'b1 & buffer_head_q[2] == 1'b1) ? data3_in : + buffer_data_q[3]; + end + + if (i > 3) + begin : bi + buffer_data_din[i] = (buffer_bypass[0] == 1'b1 & buffer_head_q[i] == 1'b1) ? data0_in : + (buffer_bypass[0] == 1'b1 & buffer_head_q[i - 1] == 1'b1) ? data1_in : + (buffer_bypass[0] == 1'b1 & buffer_head_q[i - 2] == 1'b1) ? data2_in : + (buffer_bypass[0] == 1'b1 & buffer_head_q[i - 3] == 1'b1) ? data3_in : + (buffer_bypass[1] == 1'b1 & buffer_head_q[i] == 1'b1) ? data1_in : + (buffer_bypass[1] == 1'b1 & buffer_head_q[i - 1] == 1'b1) ? data2_in : + (buffer_bypass[1] == 1'b1 & buffer_head_q[i - 2] == 1'b1) ? data3_in : + (buffer_bypass[2] == 1'b1 & buffer_head_q[i] == 1'b1) ? data2_in : + (buffer_bypass[2] == 1'b1 & buffer_head_q[i - 1] == 1'b1) ? data3_in : + buffer_data_q[i]; + end + +if (i < `IBUFF_DEPTH) +begin : ba + + buffer_data_d[i] = buffer_data_din[i]; + + buffer_array_d[i * IBUFF_WIDTH:(i + 1) * IBUFF_WIDTH - 1] = buffer_data_d[i]; + buffer_data_q[i] = buffer_array_q[i * IBUFF_WIDTH:(i + 1) * IBUFF_WIDTH - 1]; + +end +end +end +end +endgenerate + + + +// reconstruct buffer data +generate +begin : xhdl2 +genvar i; +for (i = 0; i <= `IBUFF_DEPTH - 1; i = i + 1) +begin : buff0_mux +always @( * ) +begin +if (i == 0) + begin : m0 + buffer0_data_muxed[0] = (buffer_tail_q[0] ? buffer_data_q[0] : 0 ); +end +if (i >= 1) + begin : mi + buffer0_data_muxed[i] = (buffer_tail_q[i] ? buffer_data_q[i] : 0 ) | buffer0_data_muxed[i - 1]; +end +end +end +end +endgenerate +assign buffer0_ibuff_data = buffer0_data_muxed[`IBUFF_DEPTH - 1]; + +generate +begin : xhdl3 +genvar i; +for (i = 0; i <= `IBUFF_DEPTH - 1; i = i + 1) +begin : buff1_mux +always @( * ) +begin +if (i == 0) + begin : m0 + buffer1_data_muxed[0] = (buffer_tail_q[`IBUFF_DEPTH - 1] ? buffer_data_q[0] : 0 ); +end +if (i >= 1) + begin : mi + buffer1_data_muxed[i] = (buffer_tail_q[i-1] ? buffer_data_q[i] : 0 ) | buffer1_data_muxed[i - 1]; +end +end +end +end +endgenerate +assign buffer1_ibuff_data = buffer1_data_muxed[`IBUFF_DEPTH - 1]; + +assign buffer0_data = buffer0_ibuff_data[0:IBUFF_WIDTH - 1]; +assign buffer1_data = buffer1_ibuff_data[0:IBUFF_WIDTH - 1]; + +//-------------------------------------- +// watermarks +//-------------------------------------- + +generate +begin : xhdl4 + genvar i; + for (i = 0; i <= ((`IBUFF_DEPTH/4) - 1); i = i + 1) + begin : fetch_gen + assign ib_ic_need_fetch[i] = (~buffer_valid_q[i * 4]); + end +end +endgenerate + +//-------------------------------------- +// incoming stall +//-------------------------------------- + +assign iu4_stall = iu4_0_valid_q & id_ib_iu4_stall; + +//-------------------------------------- +// stall buffer +//-------------------------------------- + +assign valid_int[0] = buffer_valid_q[0] | iu3_val[0] | stall_q[0]; +assign valid_int[1] = (stall_q[0] == 1'b0) ? (buffer_valid_q[0] & iu3_val[0]) | buffer_valid_q[1] | iu3_val[1] | stall_q[1] : + buffer_valid_q[0] | iu3_val[0] | stall_q[1]; + +assign valid_out[0] = valid_int[0]; +assign valid_out[1] = valid_int[1] & (~uc_hole[1]) & (~error_hole[1]); + +assign stall_d[0] = (uc_swap == 1'b0) ? valid_int[0] & (iu4_stall | uc_stall) & (~buffer_valid_flush) : + (stall_q[1] == 1'b0) ? valid_int[1] & (iu4_stall | uc_stall) & (~buffer_valid_flush) : + (~buffer_valid_flush); +assign stall_d[1] = (uc_swap == 1'b0) ? valid_int[1] & (iu4_stall | uc_stall) & (~buffer_valid_flush) : + 1'b0; + +assign stall_buffer_act[0] = (~stall_q[0]) | uc_swap; +assign stall_buffer_act[1] = (~stall_q[1]); + +assign stall_buffer_data0_d = (uc_swap == 1'b1) ? data1_out : + (buffer_valid_q[0] == 1'b1) ? buffer0_data : + fast_data0; + +assign stall_buffer_data1_d = (buffer_valid_q[1] == 1'b1 & stall_q[0] == 1'b0) ? buffer1_data : + (buffer_valid_q[0] == 1'b1 & stall_q[0] == 1'b1) ? buffer0_data : + (buffer_valid_q[0] == 1'b0 & stall_q[0] == 1'b0) ? fast_data1 : + fast_data0; + +assign data0_out = (stall_q[0] == 1'b1) ? stall_buffer_data0_q : + stall_buffer_data0_d; + +assign data1_out = (stall_q[1] == 1'b1) ? stall_buffer_data1_q : + stall_buffer_data1_d; + +//-------------------------------------- +// branch fusion +//-------------------------------------- + +assign fuse_en[0] = data0_out[57]; +assign fuse_en[1] = iu4_1_instr_q[57]; + +assign iu4_0_fuse_val_din = (uc_select == 1'b1) ? 1'b0 : + (fuse_en[1] == 1'b1 & iu4_1_valid_q == 1'b1) ? 1'b1 : + (iu4_0_fuse_val_q == 1'b1 & iu4_0_valid_q == 1'b1) ? 1'b0 : + iu4_0_fuse_val_q; + +assign iu4_0_fuse_data_din = (fuse_en[1] == 1'b1 & iu4_1_valid_q == 1'b1) ? iu4_1_instr_q[0:31] : + iu4_0_fuse_data_q; + +assign iu4_1_fuse_val_din = fuse_en[0] & valid_out[0] & (~(uc_select)); + +assign iu4_1_fuse_data_din = data0_out[0:31]; + +//-------------------------------------- +// ucode muxing +//-------------------------------------- + +assign ucode_out[0] = data0_out[56]; +assign ucode_out[1] = data1_out[56]; + +assign iu4_uc_mode_din[0] = (cp_flush_into_uc_delay_q[1] == 1'b1) ? 1'b1 : + (|(uc_ib_val) == 1'b1 & uc_ib_done == 1'b1 & uc_select == 1'b1) ? 1'b0 : + (valid_out[0] == 1'b1 & ucode_out[0] == 1'b1 & uc_select == 1'b0) ? 1'b1 : + iu4_uc_mode_q[0]; + +assign iu4_uc_mode_din[1] = (cp_flush_into_uc_delay_q[1] == 1'b1) ? 1'b0 : + (|(uc_ib_val) == 1'b1 & uc_ib_done == 1'b1 & uc_select == 1'b1) ? 1'b0 : + (valid_out[1] == 1'b1 & ucode_out[1] == 1'b1 & uc_select == 1'b0) ? 1'b1 : + iu4_uc_mode_q[1]; + +assign uc_stall = iu4_uc_mode_d[0] | iu4_uc_mode_q[0] | iu4_uc_mode_q[1]; +assign uc_select = |(iu4_uc_mode_q[0:1]); +assign uc_hole[0] = 1'b0; +assign uc_hole[1] = valid_out[0] & ucode_out[0]; +assign uc_swap = iu4_0_ucode_q[1] & uc_select_d & (~uc_select_q); //ucode in instr0, and ucode select edge detect +assign uc_select_d = uc_select; + +assign ib_uc_rdy = uc_select & (~iu4_stall); +assign ib_rm_rdy = (~iu4_stall); + +//-------------------------------------- +// erat error single instruction issue +//-------------------------------------- + +assign error0_out[0:2] = data0_out[53:55]; +assign error1_out[0:2] = data1_out[53:55]; + +assign error_hole[0] = 1'b0; +assign error_hole[1] = valid_out[0] & error0_out == 3'b111; + +assign iu4_0_valid_din = (uc_select == 1'b1) ? uc_ib_val[0] : + valid_out[0] | rm_ib_iu3_val; + assign iu4_0_instr_din = (uc_select == 1'b1) ? {uc_ib_instr0[0:31], {(`IBUFF_INSTR_WIDTH-32){1'b0}}} : + (rm_ib_iu3_val == 1'b1) ? {rm_ib_iu3_instr[0:31], {(`IBUFF_INSTR_WIDTH-32){1'b0}}} : + data0_out[0:`IBUFF_INSTR_WIDTH - 1]; +assign iu4_0_bta_din = data0_out[`IBUFF_INSTR_WIDTH:`IBUFF_INSTR_WIDTH + `EFF_IFAR_WIDTH - 1]; +assign iu4_0_ifar_din = (uc_select == 1'b1) ? uc_ib_ifar0[62 - `EFF_IFAR_WIDTH:61] : + data0_out[`IBUFF_INSTR_WIDTH + `EFF_IFAR_WIDTH:IDATA_WIDTH - 1]; +assign iu4_0_ucode_ext_din = (uc_select ? uc_ib_ext0 : 0 ) | (rm_ib_iu3_val ? rm_ib_iu3_instr[32:35] : 0 ); + +assign iu4_0_ucode_din[0] = uc_select; +assign iu4_0_ucode_din[1] = (~uc_select) & valid_out[0] & ucode_out[0]; +assign iu4_0_ucode_din[2] = uc_select & uc_ib_done & uc_ib_val[0] & (~uc_ib_val[1]); +assign iu4_0_isram_din = rm_ib_iu3_val; + +assign iu4_1_valid_din = (uc_select == 1'b1) ? uc_ib_val[1] : + valid_out[1]; +assign iu4_1_instr_din = (uc_select == 1'b1) ? {uc_ib_instr1[0:31], {(`IBUFF_INSTR_WIDTH-32){1'b0}}} : + data1_out[0:`IBUFF_INSTR_WIDTH - 1]; +assign iu4_1_bta_din = data1_out[`IBUFF_INSTR_WIDTH:`IBUFF_INSTR_WIDTH + `EFF_IFAR_WIDTH - 1]; +assign iu4_1_ifar_din = (uc_select == 1'b1) ? uc_ib_ifar1[62 - `EFF_IFAR_WIDTH:61] : + data1_out[`IBUFF_INSTR_WIDTH + `EFF_IFAR_WIDTH:IDATA_WIDTH - 1]; +assign iu4_1_ucode_ext_din = (uc_select ? uc_ib_ext1 : 0 ); + +assign iu4_1_ucode_din[0] = uc_select; +assign iu4_1_ucode_din[1] = (~uc_select) & valid_out[1] & ucode_out[1]; +assign iu4_1_ucode_din[2] = uc_select & uc_ib_done & uc_ib_val[1]; +assign iu4_1_isram_din = 1'b0; + +//-------------------------------------- +// output latches +//-------------------------------------- + + +always @(iu4_stall or buffer_valid_flush or iu4_uc_mode_din or iu4_0_valid_din or iu4_0_instr_din or iu4_0_bta_din or iu4_0_ifar_din or iu4_0_ucode_din or iu4_0_ucode_ext_din or iu4_0_isram_din or iu4_0_fuse_val_din or iu4_0_fuse_data_din or iu4_1_valid_din or iu4_1_instr_din or iu4_1_bta_din or iu4_1_ifar_din or iu4_1_ucode_din or iu4_1_ucode_ext_din or iu4_1_isram_din or iu4_1_fuse_val_din or iu4_1_fuse_data_din or iu4_uc_mode_q or iu4_0_valid_q or iu4_0_instr_q or iu4_0_bta_q or iu4_0_ifar_q or iu4_0_ucode_q or iu4_0_ucode_ext_q or iu4_0_isram_q or iu4_0_fuse_val_q or iu4_0_fuse_data_q or iu4_1_valid_q or iu4_1_instr_q or iu4_1_bta_q or iu4_1_ifar_q or iu4_1_ucode_q or iu4_1_ucode_ext_q or iu4_1_isram_q or iu4_1_fuse_val_q or iu4_1_fuse_data_q) +begin: iu4_proc + + iu4_uc_mode_d = iu4_uc_mode_din; + iu4_0_valid_d = iu4_0_valid_din; + iu4_0_instr_d = iu4_0_instr_din; + iu4_0_bta_d = iu4_0_bta_din; + iu4_0_ifar_d = iu4_0_ifar_din; + iu4_0_ucode_d = iu4_0_ucode_din; + iu4_0_ucode_ext_d = iu4_0_ucode_ext_din; + iu4_0_isram_d = iu4_0_isram_din; + iu4_0_fuse_val_d = iu4_0_fuse_val_din; + iu4_0_fuse_data_d = iu4_0_fuse_data_din; + iu4_1_valid_d = iu4_1_valid_din; + iu4_1_instr_d = iu4_1_instr_din; + iu4_1_bta_d = iu4_1_bta_din; + iu4_1_ifar_d = iu4_1_ifar_din; + iu4_1_ucode_d = iu4_1_ucode_din; + iu4_1_ucode_ext_d = iu4_1_ucode_ext_din; + iu4_1_isram_d = iu4_1_isram_din; + iu4_1_fuse_val_d = iu4_1_fuse_val_din; + iu4_1_fuse_data_d = iu4_1_fuse_data_din; + + if (iu4_stall == 1'b1) + begin + iu4_uc_mode_d = iu4_uc_mode_q; + iu4_0_valid_d = iu4_0_valid_q; + iu4_0_instr_d = iu4_0_instr_q; + iu4_0_bta_d = iu4_0_bta_q; + iu4_0_ifar_d = iu4_0_ifar_q; + iu4_0_ucode_d = iu4_0_ucode_q; + iu4_0_ucode_ext_d = iu4_0_ucode_ext_q; + iu4_0_isram_d = iu4_0_isram_q; + iu4_0_fuse_val_d = iu4_0_fuse_val_q; + iu4_0_fuse_data_d = iu4_0_fuse_data_q; + iu4_1_valid_d = iu4_1_valid_q; + iu4_1_instr_d = iu4_1_instr_q; + iu4_1_bta_d = iu4_1_bta_q; + iu4_1_ifar_d = iu4_1_ifar_q; + iu4_1_ucode_d = iu4_1_ucode_q; + iu4_1_ucode_ext_d = iu4_1_ucode_ext_q; + iu4_1_isram_d = iu4_1_isram_q; + iu4_1_fuse_val_d = iu4_1_fuse_val_q; + iu4_1_fuse_data_d = iu4_1_fuse_data_q; + end + + if (buffer_valid_flush == 1'b1) + begin + iu4_uc_mode_d = 2'b0; + iu4_0_valid_d = 1'b0; + iu4_1_valid_d = 1'b0; + iu4_0_fuse_val_d = 1'b0; + iu4_1_fuse_val_d = 1'b0; + end + +end + +//-------------------------------------- +// instruction output +//-------------------------------------- + +assign ib_id_iu4_0_valid = iu4_0_valid_q; +assign ib_id_iu4_0_instr = iu4_0_instr_q; +assign ib_id_iu4_0_ucode = iu4_0_ucode_q; +assign ib_id_iu4_0_ucode_ext = iu4_0_ucode_ext_q; +assign ib_id_iu4_0_bta = iu4_0_bta_q; +assign ib_id_iu4_0_ifar = iu4_0_ifar_q; +assign ib_id_iu4_0_isram = iu4_0_isram_q; +assign ib_id_iu4_0_fuse_val = iu4_0_fuse_val_q; +assign ib_id_iu4_0_fuse_data = iu4_0_fuse_data_q; + +assign ib_id_iu4_1_valid = iu4_1_valid_q; +assign ib_id_iu4_1_instr = iu4_1_instr_q; +assign ib_id_iu4_1_ucode = iu4_1_ucode_q; +assign ib_id_iu4_1_ucode_ext = iu4_1_ucode_ext_q; +assign ib_id_iu4_1_bta = iu4_1_bta_q; +assign ib_id_iu4_1_ifar = iu4_1_ifar_q; +assign ib_id_iu4_1_isram = iu4_1_isram_q; +assign ib_id_iu4_1_fuse_val = iu4_1_fuse_val_q; +assign ib_id_iu4_1_fuse_data = iu4_1_fuse_data_q; + +//--------------------------------------------------------------------- +// Latches +//--------------------------------------------------------------------- + + +tri_rlmlatch_p #(.INIT(0)) uc_select_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[uc_select_offset]), + .scout(sov[uc_select_offset]), + .din(uc_select_d), + .dout(uc_select_q) +); + + +tri_rlmreg_p #(.WIDTH(`IBUFF_DEPTH), .INIT(0)) buffer_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(buffer_valid_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[buffer_valid_offset:buffer_valid_offset + `IBUFF_DEPTH - 1]), + .scout(sov[buffer_valid_offset:buffer_valid_offset + `IBUFF_DEPTH - 1]), + .din(buffer_valid_d), + .dout(buffer_valid_q[0:`IBUFF_DEPTH - 1]) +); + + +tri_rlmreg_p #(.WIDTH(`IBUFF_DEPTH), .INIT(1)) buffer_head_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(buffer_head_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[buffer_head_offset:buffer_head_offset + `IBUFF_DEPTH - 1]), + .scout(sov[buffer_head_offset:buffer_head_offset + `IBUFF_DEPTH - 1]), + .din(buffer_head_d), + .dout(buffer_head_q[0:`IBUFF_DEPTH - 1]) +); + + +tri_rlmreg_p #(.WIDTH(`IBUFF_DEPTH), .INIT(1)) buffer_tail_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(buffer_tail_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[buffer_tail_offset:buffer_tail_offset + `IBUFF_DEPTH - 1]), + .scout(sov[buffer_tail_offset:buffer_tail_offset + `IBUFF_DEPTH - 1]), + .din(buffer_tail_d), + .dout(buffer_tail_q[0:`IBUFF_DEPTH - 1]) +); + + +tri_rlmreg_p #(.WIDTH((`IBUFF_DEPTH*IBUFF_WIDTH-1+1)), .INIT(0)) buffer_array_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu3_val[0]), //tiup, + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[buffer_array_offset:buffer_array_offset + (`IBUFF_DEPTH*IBUFF_WIDTH-1+1) - 1]), + .scout(sov[buffer_array_offset:buffer_array_offset + (`IBUFF_DEPTH*IBUFF_WIDTH-1+1) - 1]), + .din(buffer_array_d), + .dout(buffer_array_q) +); + + +tri_rlmreg_p #(.WIDTH(IDATA_WIDTH), .INIT(0)) stall_buffer_data0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_buffer_act[0]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_buffer_data0_offset:stall_buffer_data0_offset + IDATA_WIDTH - 1]), + .scout(sov[stall_buffer_data0_offset:stall_buffer_data0_offset + IDATA_WIDTH - 1]), + .din(stall_buffer_data0_d), + .dout(stall_buffer_data0_q) +); + + +tri_rlmreg_p #(.WIDTH(IDATA_WIDTH), .INIT(0)) stall_buffer_data1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_buffer_act[1]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_buffer_data1_offset:stall_buffer_data1_offset + IDATA_WIDTH - 1]), + .scout(sov[stall_buffer_data1_offset:stall_buffer_data1_offset + IDATA_WIDTH - 1]), + .din(stall_buffer_data1_d), + .dout(stall_buffer_data1_q) +); + + +tri_rlmreg_p #(.WIDTH(2), .INIT(0)) stall_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_offset:stall_offset + 2 - 1]), + .scout(sov[stall_offset:stall_offset + 2 - 1]), + .din(stall_d), + .dout(stall_q) +); + + +tri_rlmreg_p #(.WIDTH(2), .INIT(0)) iu4_uc_mode_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu4_uc_mode_offset:iu4_uc_mode_offset + 2 - 1]), + .scout(sov[iu4_uc_mode_offset:iu4_uc_mode_offset + 2 - 1]), + .din(iu4_uc_mode_d), + .dout(iu4_uc_mode_q) +); + + +tri_rlmlatch_p #(.INIT(0)) iu4_0_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu4_0_valid_offset]), + .scout(sov[iu4_0_valid_offset]), + .din(iu4_0_valid_d), + .dout(iu4_0_valid_q) +); + + +tri_rlmreg_p #(.WIDTH(`IBUFF_INSTR_WIDTH), .INIT(0)) iu4_0_instr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu4_0_valid_din), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu4_0_instr_offset:iu4_0_instr_offset + `IBUFF_INSTR_WIDTH - 1]), + .scout(sov[iu4_0_instr_offset:iu4_0_instr_offset + `IBUFF_INSTR_WIDTH - 1]), + .din(iu4_0_instr_d), + .dout(iu4_0_instr_q) +); + + +tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) iu4_0_ifar_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu4_0_valid_din), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu4_0_ifar_offset:iu4_0_ifar_offset + (`EFF_IFAR_WIDTH) - 1]), + .scout(sov[iu4_0_ifar_offset:iu4_0_ifar_offset + (`EFF_IFAR_WIDTH) - 1]), + .din(iu4_0_ifar_d), + .dout(iu4_0_ifar_q) +); + + +tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) iu4_0_bta_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu4_0_valid_din), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu4_0_bta_offset:iu4_0_bta_offset + (`EFF_IFAR_WIDTH) - 1]), + .scout(sov[iu4_0_bta_offset:iu4_0_bta_offset + (`EFF_IFAR_WIDTH) - 1]), + .din(iu4_0_bta_d), + .dout(iu4_0_bta_q) +); + + +tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu4_0_ucode_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu4_0_valid_din), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu4_0_ucode_offset:iu4_0_ucode_offset + 3 - 1]), + .scout(sov[iu4_0_ucode_offset:iu4_0_ucode_offset + 3 - 1]), + .din(iu4_0_ucode_d), + .dout(iu4_0_ucode_q) +); + + +tri_rlmreg_p #(.WIDTH(4), .INIT(0)) iu4_0_ucode_ext_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu4_0_valid_din), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu4_0_ucode_ext_offset:iu4_0_ucode_ext_offset + 4 - 1]), + .scout(sov[iu4_0_ucode_ext_offset:iu4_0_ucode_ext_offset + 4 - 1]), + .din(iu4_0_ucode_ext_d), + .dout(iu4_0_ucode_ext_q) +); + + +tri_rlmlatch_p #(.INIT(0)) iu4_0_isram_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu4_0_valid_din), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu4_0_isram_offset]), + .scout(sov[iu4_0_isram_offset]), + .din(iu4_0_isram_d), + .dout(iu4_0_isram_q) +); + + +tri_rlmlatch_p #(.INIT(0)) iu4_0_fuse_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu4_0_fuse_val_offset]), + .scout(sov[iu4_0_fuse_val_offset]), + .din(iu4_0_fuse_val_d), + .dout(iu4_0_fuse_val_q) +); + + +tri_rlmreg_p #(.WIDTH(32), .INIT(0)) iu4_0_fuse_data_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu4_0_fuse_val_din), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu4_0_fuse_data_offset:iu4_0_fuse_data_offset + 32 - 1]), + .scout(sov[iu4_0_fuse_data_offset:iu4_0_fuse_data_offset + 32 - 1]), + .din(iu4_0_fuse_data_d), + .dout(iu4_0_fuse_data_q) +); + + +tri_rlmlatch_p #(.INIT(0)) iu4_1_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu4_1_valid_offset]), + .scout(sov[iu4_1_valid_offset]), + .din(iu4_1_valid_d), + .dout(iu4_1_valid_q) +); + + +tri_rlmreg_p #(.WIDTH(`IBUFF_INSTR_WIDTH), .INIT(0)) iu4_1_instr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu4_1_valid_din), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu4_1_instr_offset:iu4_1_instr_offset + `IBUFF_INSTR_WIDTH - 1]), + .scout(sov[iu4_1_instr_offset:iu4_1_instr_offset + `IBUFF_INSTR_WIDTH - 1]), + .din(iu4_1_instr_d), + .dout(iu4_1_instr_q) +); + + +tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) iu4_1_ifar_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu4_1_valid_din), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu4_1_ifar_offset:iu4_1_ifar_offset + (`EFF_IFAR_WIDTH) - 1]), + .scout(sov[iu4_1_ifar_offset:iu4_1_ifar_offset + (`EFF_IFAR_WIDTH) - 1]), + .din(iu4_1_ifar_d), + .dout(iu4_1_ifar_q) +); + + +tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) iu4_1_bta_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu4_1_valid_din), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu4_1_bta_offset:iu4_1_bta_offset + (`EFF_IFAR_WIDTH) - 1]), + .scout(sov[iu4_1_bta_offset:iu4_1_bta_offset + (`EFF_IFAR_WIDTH) - 1]), + .din(iu4_1_bta_d), + .dout(iu4_1_bta_q) +); + + +tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu4_1_ucode_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu4_1_valid_din), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu4_1_ucode_offset:iu4_1_ucode_offset + 3 - 1]), + .scout(sov[iu4_1_ucode_offset:iu4_1_ucode_offset + 3 - 1]), + .din(iu4_1_ucode_d), + .dout(iu4_1_ucode_q) +); + + +tri_rlmreg_p #(.WIDTH(4), .INIT(0)) iu4_1_ucode_ext_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu4_1_valid_din), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu4_1_ucode_ext_offset:iu4_1_ucode_ext_offset + 4 - 1]), + .scout(sov[iu4_1_ucode_ext_offset:iu4_1_ucode_ext_offset + 4 - 1]), + .din(iu4_1_ucode_ext_d), + .dout(iu4_1_ucode_ext_q) +); + + +tri_rlmlatch_p #(.INIT(0)) iu4_1_isram_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu4_1_valid_din), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu4_1_isram_offset]), + .scout(sov[iu4_1_isram_offset]), + .din(iu4_1_isram_d), + .dout(iu4_1_isram_q) +); + + +tri_rlmlatch_p #(.INIT(0)) iu4_1_fuse_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu4_1_fuse_val_offset]), + .scout(sov[iu4_1_fuse_val_offset]), + .din(iu4_1_fuse_val_d), + .dout(iu4_1_fuse_val_q) +); + + +tri_rlmreg_p #(.WIDTH(32), .INIT(0)) iu4_1_fuse_data_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu4_1_fuse_val_din), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu4_1_fuse_data_offset:iu4_1_fuse_data_offset + 32 - 1]), + .scout(sov[iu4_1_fuse_data_offset:iu4_1_fuse_data_offset + 32 - 1]), + .din(iu4_1_fuse_data_d), + .dout(iu4_1_fuse_data_q) +); + + +tri_rlmlatch_p #(.INIT(0)) cp_flush_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[cp_flush_offset]), + .scout(sov[cp_flush_offset]), + .din(cp_flush_d), + .dout(cp_flush_q) +); + + +tri_rlmlatch_p #(.INIT(0)) br_iu_redirect_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[br_iu_redirect_offset]), + .scout(sov[br_iu_redirect_offset]), + .din(br_iu_redirect_d), + .dout(br_iu_redirect_q) +); + + +tri_rlmreg_p #(.WIDTH(2), .INIT(0)) cp_flush_into_uc_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[cp_flush_into_uc_offset:cp_flush_into_uc_offset + 2 - 1]), + .scout(sov[cp_flush_into_uc_offset:cp_flush_into_uc_offset + 2 - 1]), + .din(cp_flush_into_uc_delay_d), + .dout(cp_flush_into_uc_delay_q) +); + + +//----------------------------------------------- +// pervasive +//----------------------------------------------- + + + tri_plat #(.WIDTH(2)) perv_2to1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + .din({pc_iu_func_sl_thold_2,pc_iu_sg_2}), + .q({pc_iu_func_sl_thold_1,pc_iu_sg_1}) + ); + + + tri_plat #(.WIDTH(2)) perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + .din({pc_iu_func_sl_thold_1,pc_iu_sg_1}), + .q({pc_iu_func_sl_thold_0,pc_iu_sg_0}) + ); + + +tri_lcbor perv_lcbor( + .clkoff_b(clkoff_b), + .thold(pc_iu_func_sl_thold_0), + .sg(pc_iu_sg_0), + .act_dis(act_dis), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b) +); + +//--------------------------------------------------------------------- +// Scan +//--------------------------------------------------------------------- +assign siv[0:scan_right] = {sov[1:scan_right], scan_in}; +assign scan_out = sov[0]; + + +endmodule diff --git a/dev/verilog/work/iuq_ic.v b/dev/verilog/work/iuq_ic.v new file mode 100755 index 0000000..08f7be6 --- /dev/null +++ b/dev/verilog/work/iuq_ic.v @@ -0,0 +1,1281 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//******************************************************************** +//* +//* TITLE: Instruction Cache +//* +//* NAME: iuq_ic.v +//* +//********************************************************************* + +`include "tri_a2o.vh" + +module iuq_ic( + inout vcs, + inout vdd, + inout gnd, + (* pin_data="PIN_FUNCTION=/G_CLK/" *) + input [0:`NCLK_WIDTH-1] nclk, + + input tc_ac_ccflush_dc, + input tc_ac_scan_dis_dc_b, + input tc_ac_scan_diag_dc, + + input pc_iu_func_sl_thold_2, + input pc_iu_func_slp_sl_thold_2, + input pc_iu_func_nsl_thold_2, // added for custom cam + input pc_iu_cfg_slp_sl_thold_2, // for boot config slats + input pc_iu_regf_slp_sl_thold_2, + input pc_iu_time_sl_thold_2, + input pc_iu_abst_sl_thold_2, + input pc_iu_abst_slp_sl_thold_2, + input pc_iu_repr_sl_thold_2, + input pc_iu_ary_nsl_thold_2, + input pc_iu_ary_slp_nsl_thold_2, + input pc_iu_func_slp_nsl_thold_2, + input pc_iu_bolt_sl_thold_2, + input pc_iu_sg_2, + input pc_iu_fce_2, + input clkoff_b, + input act_dis, + input d_mode, + input delay_lclkr, + input mpw1_b, + input mpw2_b, + input g8t_clkoff_b, + input g8t_d_mode, + input [0:4] g8t_delay_lclkr, + input [0:4] g8t_mpw1_b, + input g8t_mpw2_b, + input g6t_clkoff_b, + input g6t_act_dis, + input g6t_d_mode, + input [0:3] g6t_delay_lclkr, + input [0:4] g6t_mpw1_b, + input g6t_mpw2_b, + input cam_clkoff_b, + input cam_act_dis, + input cam_d_mode, + input [0:4] cam_delay_lclkr, + input [0:4] cam_mpw1_b, + input cam_mpw2_b, + + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + input func_scan_in, + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + output func_scan_out, + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + input ac_ccfg_scan_in, + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + output ac_ccfg_scan_out, + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + input time_scan_in, + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + output time_scan_out, + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + input repr_scan_in, + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + output repr_scan_out, + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + input [0:2] abst_scan_in, + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + output [0:2] abst_scan_out, + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + input [0:4] regf_scan_in, + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + output [0:4] regf_scan_out, + + output iu_pc_err_icache_parity, + output iu_pc_err_icachedir_parity, + output iu_pc_err_icachedir_multihit, + output iu_pc_err_ierat_multihit, + output iu_pc_err_ierat_parity, + + input pc_iu_inj_icache_parity, + input pc_iu_inj_icachedir_parity, + input pc_iu_inj_icachedir_multihit, + + input pc_iu_abist_g8t_wenb, + input pc_iu_abist_g8t1p_renb_0, + input [0:3] pc_iu_abist_di_0, + input pc_iu_abist_g8t_bw_1, + input pc_iu_abist_g8t_bw_0, + input [3:9] pc_iu_abist_waddr_0, + input [1:9] pc_iu_abist_raddr_0, + input pc_iu_abist_ena_dc, + input pc_iu_abist_wl128_comp_ena, + input pc_iu_abist_raw_dc_b, + input [0:3] pc_iu_abist_g8t_dcomp, + input [0:1] pc_iu_abist_g6t_bw, + input [0:3] pc_iu_abist_di_g6t_2r, + input pc_iu_abist_wl512_comp_ena, + input [0:3] pc_iu_abist_dcomp_g6t_2r, + input pc_iu_abist_g6t_r_wb, + input an_ac_lbist_ary_wrt_thru_dc, + input an_ac_lbist_en_dc, + input an_ac_atpg_en_dc, + input an_ac_grffence_en_dc, + + input pc_iu_bo_enable_3, // bolt-on ABIST + input pc_iu_bo_reset, + input pc_iu_bo_unload, + input pc_iu_bo_repair, + input pc_iu_bo_shdata, + input [0:3] pc_iu_bo_select, + output [0:3] iu_pc_bo_fail, + output [0:3] iu_pc_bo_diagout, + + // ICBI Interface to IU + input [0:`THREADS-1] lq_iu_icbi_val, + input [64-`REAL_IFAR_WIDTH:57] lq_iu_icbi_addr, + output [0:`THREADS-1] iu_lq_icbi_complete, + input lq_iu_ici_val, + + // ERAT + input pc_iu_init_reset, + + // XU IERAT interface + input [0:`THREADS-1] xu_iu_val, + input xu_iu_is_eratre, + input xu_iu_is_eratwe, + input xu_iu_is_eratsx, + input xu_iu_is_eratilx, + input cp_is_isync, + input cp_is_csync, + input [0:1] xu_iu_ws, + input [0:3] xu_iu_ra_entry, + + input [64-`GPR_WIDTH:51] xu_iu_rb, + input [64-`GPR_WIDTH:63] xu_iu_rs_data, + output iu_xu_ord_read_done, + output iu_xu_ord_write_done, + output iu_xu_ord_par_err, + output iu_xu_ord_n_flush_req, + input [0:`THREADS-1] xu_iu_msr_hv, + input [0:`THREADS-1] xu_iu_msr_pr, + input [0:`THREADS-1] xu_iu_msr_is, + input xu_iu_hid_mmu_mode, + input xu_iu_spr_ccr2_ifrat, + input [0:8] xu_iu_spr_ccr2_ifratsc, // 0:4: wimge, 5:8: u0:3 + input xu_iu_xucr4_mmu_mchk, + output [64-`GPR_WIDTH:63] iu_xu_ex5_data, + + output iu_mm_ierat_req, + output iu_mm_ierat_req_nonspec, + output [0:51] iu_mm_ierat_epn, + output [0:`THREADS-1] iu_mm_ierat_thdid, + output [0:3] iu_mm_ierat_state, + output [0:13] iu_mm_ierat_tid, + output [0:`THREADS-1] iu_mm_ierat_flush, + output [0:`THREADS-1] iu_mm_perf_itlb, + + input [0:4] mm_iu_ierat_rel_val, + input [0:131] mm_iu_ierat_rel_data, + + input [0:13] mm_iu_t0_ierat_pid, + input [0:19] mm_iu_t0_ierat_mmucr0, + `ifndef THREADS1 + input [0:13] mm_iu_t1_ierat_pid, + input [0:19] mm_iu_t1_ierat_mmucr0, + `endif + output [0:17] iu_mm_ierat_mmucr0, + output [0:`THREADS-1] iu_mm_ierat_mmucr0_we, + input [0:8] mm_iu_ierat_mmucr1, + output [0:3] iu_mm_ierat_mmucr1, + output [0:`THREADS-1] iu_mm_ierat_mmucr1_we, + + input mm_iu_ierat_snoop_coming, + input mm_iu_ierat_snoop_val, + input [0:25] mm_iu_ierat_snoop_attr, + input [62-`EFF_IFAR_ARCH:51] mm_iu_ierat_snoop_vpn, + output iu_mm_ierat_snoop_ack, + + // MMU Connections + input [0:`THREADS-1] mm_iu_hold_req, + input [0:`THREADS-1] mm_iu_hold_done, + input [0:`THREADS-1] mm_iu_bus_snoop_hold_req, + input [0:`THREADS-1] mm_iu_bus_snoop_hold_done, + + // SELECT, DIR, & MISS + input [0:`THREADS-1] pc_iu_ram_active, + input [0:`THREADS-1] pc_iu_pm_fetch_halt, + input [0:`THREADS-1] xu_iu_run_thread, + input [0:`THREADS-1] cp_ic_stop, + input [0:`THREADS-1] xu_iu_msr_cm, + + input [0:`THREADS-1] iu_flush, + input [0:`THREADS-1] br_iu_redirect, + input [62-`EFF_IFAR_ARCH:61] br_iu_bta, + input [0:`THREADS-1] cp_flush, + input [0:`THREADS-1] cp_flush_into_uc, + input [62-`EFF_IFAR_ARCH:61] cp_iu0_t0_flush_ifar, + `ifndef THREADS1 + input [62-`EFF_IFAR_ARCH:61] cp_iu0_t1_flush_ifar, + `endif + input [0:`THREADS-1] cp_iu0_flush_2ucode, + input [0:`THREADS-1] cp_iu0_flush_2ucode_type, + input [0:`THREADS-1] cp_iu0_flush_nonspec, + + output [0:`THREADS-1] ic_cp_nonspec_hit, + + input an_ac_back_inv, + input [64-`REAL_IFAR_WIDTH:57] an_ac_back_inv_addr, + input an_ac_back_inv_target, // connect to bit(0) + + input [0:3] spr_ic_bp_config, // (0): bc, (1): bclr, (2): bcctr, (3): sw + + input spr_ic_cls, // (0): 64B cacheline, (1): 128B cacheline + input spr_ic_prefetch_dis, + input spr_ic_ierat_byp_dis, + + input spr_ic_idir_read, + input [0:1] spr_ic_idir_way, + input [51:57] spr_ic_idir_row, + output ic_spr_idir_done, + output [0:2] ic_spr_idir_lru, + output [0:3] ic_spr_idir_parity, + output ic_spr_idir_endian, + output ic_spr_idir_valid, + output [0:28] ic_spr_idir_tag, + + output [0:`THREADS-1] iu_lq_request, + output [0:1] iu_lq_ctag, + output [64-`REAL_IFAR_WIDTH:59] iu_lq_ra, + output [0:4] iu_lq_wimge, + output [0:3] iu_lq_userdef, + + + input [0:`THREADS-1] cp_async_block, + output iu_mm_lmq_empty, + output [0:`THREADS-1] iu_xu_icache_quiesce, + output [0:`THREADS-1] iu_pc_icache_quiesce, + + input an_ac_reld_data_vld, + input [0:4] an_ac_reld_core_tag, + input [58:59] an_ac_reld_qw, + input [0:127] an_ac_reld_data, + input an_ac_reld_ecc_err, + input an_ac_reld_ecc_err_ue, + + //iu5 hold/redirect + input [0:`THREADS-1] bp_ic_iu2_redirect, + input [0:`THREADS-1] bp_ic_iu3_redirect, + input [0:`THREADS-1] bp_ic_iu4_redirect, + input [62-`EFF_IFAR_WIDTH:61] bp_ic_t0_redirect_ifar, + `ifndef THREADS1 + input [62-`EFF_IFAR_WIDTH:61] bp_ic_t1_redirect_ifar, + `endif + + // iu1 + output [0:`THREADS-1] ic_bp_iu0_val, + output [50:59] ic_bp_iu0_ifar, + + // iu3 + output [0:3] ic_bp_iu2_t0_val, + `ifndef THREADS1 + output [0:3] ic_bp_iu2_t1_val, + `endif + output [62-`EFF_IFAR_WIDTH:61] ic_bp_iu2_ifar, + output ic_bp_iu2_2ucode, + output ic_bp_iu2_2ucode_type, + output [0:2] ic_bp_iu2_error, + output [0:`THREADS-1] ic_bp_iu2_flush, + output [0:`THREADS-1] ic_bp_iu3_flush, + + // iu3 instruction(0:31) + predecode(32:35) + output [0:35] ic_bp_iu2_0_instr, + output [0:35] ic_bp_iu2_1_instr, + output [0:35] ic_bp_iu2_2_instr, + output [0:35] ic_bp_iu2_3_instr, + + output ic_bp_iu3_ecc_err, + + //Instruction Buffer + input [0:`IBUFF_DEPTH/4-1] ib_ic_t0_need_fetch, + `ifndef THREADS1 + input [0:`IBUFF_DEPTH/4-1] ib_ic_t1_need_fetch, + `endif + + // ucode + input [0:`THREADS-1] uc_iu4_flush, + input [62-`EFF_IFAR_WIDTH:61] uc_iu4_t0_flush_ifar, + `ifndef THREADS1 + input [62-`EFF_IFAR_WIDTH:61] uc_iu4_t1_flush_ifar, + `endif + input [0:`THREADS-1] uc_ic_hold, + + input pc_iu_event_bus_enable, + input [0:2] pc_iu_event_count_mode, + + + input [0:24*`THREADS-1] spr_perf_event_mux_ctrls, + input [0:20] slice_ic_t0_perf_events, + `ifndef THREADS1 + input [0:20] slice_ic_t1_perf_events, + `endif + input [0:4*`THREADS-1] event_bus_in, + output [0:4*`THREADS-1] event_bus_out +); + + localparam perf_bus_offset = 5; + localparam scan_right = perf_bus_offset + 4*`THREADS - 1; + + wire iu_ierat_iu0_val; + wire [0:`THREADS-1] iu_ierat_iu0_thdid; + wire [0:51] iu_ierat_iu0_ifar; + wire iu_ierat_iu0_nonspec; + wire iu_ierat_iu0_prefetch; + wire [0:`THREADS-1] iu_ierat_flush; + wire iu_ierat_iu1_back_inv; + wire iu_ierat_ium1_back_inv; + wire [22:51] ierat_iu_iu2_rpn; + wire [0:4] ierat_iu_iu2_wimge; + wire [0:3] ierat_iu_iu2_u; + wire [0:2] ierat_iu_iu2_error; + wire ierat_iu_iu2_miss; + wire ierat_iu_iu2_multihit; + wire ierat_iu_cam_change; + wire ierat_iu_iu2_isi; + wire [0:`THREADS-1] ierat_iu_hold_req; + wire [0:`THREADS-1] ierat_iu_iu2_flush_req; + + wire ics_icd_dir_rd_act; + wire [0:1] ics_icd_data_rd_act; + wire ics_icd_iu0_valid; + wire [0:`THREADS-1] ics_icd_iu0_tid; + wire [62-`EFF_IFAR_ARCH:61] ics_icd_iu0_ifar; + wire ics_icd_iu0_index51; + wire ics_icd_iu0_inval; + wire ics_icd_iu0_2ucode; + wire ics_icd_iu0_2ucode_type; + wire ics_icd_iu0_prefetch; + wire ics_icd_iu0_read_erat; + wire ics_icd_iu0_spr_idir_read; + wire [0:`THREADS-1] ics_icd_iu1_flush; + wire [0:`THREADS-1] ics_icd_iu2_flush; + wire icd_ics_iu1_valid; + wire [0:`THREADS-1] icd_ics_iu1_tid; + wire [62-`EFF_IFAR_WIDTH:61] icd_ics_iu1_ifar; + wire icd_ics_iu1_2ucode; + wire icd_ics_iu1_2ucode_type; + wire [0:`THREADS-1] icd_ics_iu1_read_erat; + wire [0:`THREADS-1] icd_ics_iu3_miss_flush; + wire [0:`THREADS-1] icd_ics_iu2_wrong_ra_flush; + wire [0:`THREADS-1] icd_ics_iu2_cam_etc_flush; + wire [62-`EFF_IFAR_WIDTH:61] icd_ics_iu2_ifar_eff; + wire icd_ics_iu2_2ucode; + wire icd_ics_iu2_2ucode_type; + wire icd_ics_iu2_valid; + wire [0:`THREADS-1] icd_ics_iu2_read_erat_error; + wire [0:`THREADS-1] icd_ics_iu3_parity_flush; + wire [62-`EFF_IFAR_WIDTH:61] icd_ics_iu3_ifar; + wire icd_ics_iu3_2ucode; + wire icd_ics_iu3_2ucode_type; + wire [0:`THREADS-1] icm_ics_iu0_preload_val; + wire [50:59] icm_ics_iu0_preload_ifar; + wire [0:`THREADS-1] icm_ics_prefetch_req; + wire [0:`THREADS-1] icm_ics_prefetch_sm_idle; + wire [0:`THREADS-1] icm_ics_hold_thread; + wire icm_ics_hold_iu0; + wire icm_ics_iu3_miss_match; + wire [0:`THREADS-1] icm_ics_iu3_ecc_fp_cancel; + + wire [46:52] ics_icm_iu0_t0_ifar; + `ifndef THREADS1 + wire [46:52] ics_icm_iu0_t1_ifar; + `endif + wire ics_icm_iu0_inval; + wire [51:57] ics_icm_iu0_inval_addr; + wire [0:`THREADS-1] ics_icm_iu2_flush; + + wire [51:57] icm_icd_lru_addr; + wire icm_icd_dir_inval; + wire icm_icd_dir_val; + wire icm_icd_data_write; + wire [51:59] icm_icd_reload_addr; + wire [0:143] icm_icd_reload_data; + wire [0:3] icm_icd_reload_way; + wire [0:`THREADS-1] icm_icd_load; + wire [62-`EFF_IFAR_WIDTH:61] icm_icd_load_addr; + wire icm_icd_load_2ucode; + wire icm_icd_load_2ucode_type; + wire icm_icd_dir_write; + wire [64-`REAL_IFAR_WIDTH:57] icm_icd_dir_write_addr; + wire icm_icd_dir_write_endian; + wire [0:3] icm_icd_dir_write_way; + wire icm_icd_lru_write; + wire [51:57] icm_icd_lru_write_addr; + wire [0:3] icm_icd_lru_write_way; + wire icm_icd_ecc_inval; + wire [51:57] icm_icd_ecc_addr; + wire [0:3] icm_icd_ecc_way; + wire icm_icd_iu3_ecc_fp_cancel; + wire icm_icd_any_reld_r2; + wire icd_icm_miss; + wire icd_icm_prefetch; + wire [0:`THREADS-1] icd_icm_tid; + wire [64-`REAL_IFAR_WIDTH:61] icd_icm_addr_real; + wire [62-`EFF_IFAR_WIDTH:51] icd_icm_addr_eff; + wire [0:4] icd_icm_wimge; + wire [0:3] icd_icm_userdef; + wire icd_icm_2ucode; + wire icd_icm_2ucode_type; + wire icd_icm_iu2_inval; + wire icd_icm_any_iu2_valid; + wire [0:2] icd_icm_row_lru; + wire [0:3] icd_icm_row_val; + + wire [0:87] ierat_iu_debug_group0; + wire [0:87] ierat_iu_debug_group1; + wire [0:87] ierat_iu_debug_group2; + wire [0:87] ierat_iu_debug_group3; + + wire [0:`THREADS-1] br_iu_flush; + + wire [1:63] unit_t0_events_in; + wire unit_t0_events_en; + + `ifndef THREADS1 + wire [1:63] unit_t1_events_in; + wire unit_t1_events_en; + `endif + + wire pc_iu_func_sl_thold_1; + wire pc_iu_func_sl_thold_0; + wire pc_iu_func_sl_thold_0_b; + wire pc_iu_func_slp_sl_thold_1; + wire pc_iu_func_slp_sl_thold_0; + wire pc_iu_func_slp_sl_thold_0_b; + wire pc_iu_time_sl_thold_1; + wire pc_iu_time_sl_thold_0; + wire pc_iu_abst_sl_thold_1; + wire pc_iu_abst_sl_thold_0; + wire pc_iu_abst_sl_thold_0_b; + wire pc_iu_abst_slp_sl_thold_1; + wire pc_iu_abst_slp_sl_thold_0; + wire pc_iu_repr_sl_thold_1; + wire pc_iu_repr_sl_thold_0; + wire pc_iu_ary_nsl_thold_1; + wire pc_iu_ary_nsl_thold_0; + wire pc_iu_ary_slp_nsl_thold_1; + wire pc_iu_ary_slp_nsl_thold_0; + wire pc_iu_regf_slp_sl_thold_1; + wire pc_iu_regf_slp_sl_thold_0; + wire pc_iu_bolt_sl_thold_1; + wire pc_iu_bolt_sl_thold_0; + wire pc_iu_sg_1; + wire pc_iu_sg_0; + wire force_t; + wire funcslp_force; + wire abst_force; + wire pc_iu_bo_enable_2; + + wire [0:scan_right] siv; + wire [0:scan_right] sov; + wire [0:1] tsiv; // time scan path + wire [0:1] tsov; // time scan path + wire func_scan_in_cam; + wire func_scan_out_cam; + + wire [0:1] lcb_mpw1_dc_b; + wire [0:1] lcb_delay_lclkr_dc; + + wire [0:11] ic_perf_t0_event; + `ifndef THREADS1 + wire [0:11] ic_perf_t1_event; + `endif + wire [0:1] ic_perf_event; + wire [0:4*`THREADS-1] event_bus_out_d; + wire [0:4*`THREADS-1] event_bus_out_l2; + + assign br_iu_flush = br_iu_redirect; + + // ??? Temp: Need to connect + assign lcb_mpw1_dc_b = {2{mpw1_b}}; + assign lcb_delay_lclkr_dc = {2{delay_lclkr}}; + + iuq_ic_ierat iuq_ic_ierat0( + // POWER PINS + .gnd(gnd), + .vdd(vdd), + .vcs(vdd), + + // CLOCK and CLOCKCONTROL ports + .nclk(nclk), + .pc_iu_init_reset(pc_iu_init_reset), + .tc_ccflush_dc(tc_ac_ccflush_dc), + .tc_scan_dis_dc_b(tc_ac_scan_dis_dc_b), + .tc_scan_diag_dc(tc_ac_scan_diag_dc), + .tc_lbist_en_dc(an_ac_lbist_en_dc), + .an_ac_atpg_en_dc(an_ac_atpg_en_dc), + .an_ac_grffence_en_dc(an_ac_grffence_en_dc), + .lcb_d_mode_dc(d_mode), + .lcb_clkoff_dc_b(clkoff_b), + .lcb_act_dis_dc(act_dis), + .lcb_mpw1_dc_b(lcb_mpw1_dc_b), + .lcb_mpw2_dc_b(mpw2_b), + .lcb_delay_lclkr_dc(lcb_delay_lclkr_dc), + .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), + .pc_iu_func_slp_sl_thold_2(pc_iu_func_slp_sl_thold_2), + .pc_iu_func_slp_nsl_thold_2(pc_iu_func_slp_nsl_thold_2), + .pc_iu_cfg_slp_sl_thold_2(pc_iu_func_sl_thold_2), + .pc_iu_regf_slp_sl_thold_2(pc_iu_regf_slp_sl_thold_2), + .pc_iu_time_sl_thold_2(pc_iu_time_sl_thold_2), + .pc_iu_sg_2(pc_iu_sg_2), + .pc_iu_fce_2(pc_iu_sg_2), + .cam_clkoff_b(cam_clkoff_b), + .cam_act_dis(cam_act_dis), + .cam_d_mode(cam_d_mode), + .cam_delay_lclkr(cam_delay_lclkr), + .cam_mpw1_b(cam_mpw1_b), + .cam_mpw2_b(cam_mpw2_b), + .ac_func_scan_in(siv[0:1]), + .ac_func_scan_out(sov[0:1]), + .ac_ccfg_scan_in(ac_ccfg_scan_in), + .ac_ccfg_scan_out(ac_ccfg_scan_out), + .func_scan_in_cam(func_scan_in_cam), + .func_scan_out_cam(func_scan_out_cam), + .time_scan_in(tsiv[0]), + .time_scan_out(tsov[0]), + .regf_scan_in(regf_scan_in), + .regf_scan_out(regf_scan_out), + + // Functional ports + // act control + .spr_ic_clockgate_dis(1'b0), + // ttypes + .iu_ierat_iu0_val(iu_ierat_iu0_val), + .iu_ierat_iu0_thdid(iu_ierat_iu0_thdid), + .iu_ierat_iu0_ifar(iu_ierat_iu0_ifar), + .iu_ierat_iu0_nonspec(iu_ierat_iu0_nonspec), + .iu_ierat_iu0_prefetch(iu_ierat_iu0_prefetch), + + .iu_ierat_iu0_flush(iu_ierat_flush), + .iu_ierat_iu1_flush(iu_ierat_flush), + + // ordered instructions + .xu_iu_val(xu_iu_val), + .xu_iu_is_eratre(xu_iu_is_eratre), + .xu_iu_is_eratwe(xu_iu_is_eratwe), + .xu_iu_is_eratsx(xu_iu_is_eratsx), + .xu_iu_is_eratilx(xu_iu_is_eratilx), + .xu_iu_ws(xu_iu_ws), + .xu_iu_ra_entry(xu_iu_ra_entry), + .xu_iu_rs_data(xu_iu_rs_data), + .xu_iu_rb(xu_iu_rb), + .iu_xu_ex4_data(iu_xu_ex5_data), + .iu_xu_ord_read_done(iu_xu_ord_read_done), + .iu_xu_ord_write_done(iu_xu_ord_write_done), + .iu_xu_ord_par_err(iu_xu_ord_par_err), + + // context synchronizing event + .cp_ic_is_isync(cp_is_isync), + .cp_ic_is_csync(cp_is_csync), + + // reload from mmu + .mm_iu_ierat_rel_val(mm_iu_ierat_rel_val), + .mm_iu_ierat_rel_data(mm_iu_ierat_rel_data), + + .ierat_iu_hold_req(ierat_iu_hold_req), + + // I$ snoop + .iu_ierat_iu1_back_inv(iu_ierat_iu1_back_inv), + .iu_ierat_ium1_back_inv(iu_ierat_ium1_back_inv), + + // tlbivax or tlbilx snoop + .mm_iu_ierat_snoop_coming(mm_iu_ierat_snoop_coming), + .mm_iu_ierat_snoop_val(mm_iu_ierat_snoop_val), + .mm_iu_ierat_snoop_attr(mm_iu_ierat_snoop_attr), + .mm_iu_ierat_snoop_vpn(mm_iu_ierat_snoop_vpn), + .iu_mm_ierat_snoop_ack(iu_mm_ierat_snoop_ack), + + // pipeline controls + .xu_iu_flush(iu_flush), + .br_iu_flush(br_iu_flush), + + // all tied to cp_flush + .xu_rf1_flush(cp_flush), + .xu_ex1_flush(cp_flush), + .xu_ex2_flush(cp_flush), + .xu_ex3_flush(cp_flush), + .xu_ex4_flush(cp_flush), + .xu_ex5_flush(cp_flush), + + // cam _np2 ports + .ierat_iu_iu2_rpn(ierat_iu_iu2_rpn), + .ierat_iu_iu2_wimge(ierat_iu_iu2_wimge), + .ierat_iu_iu2_u(ierat_iu_iu2_u), + + .ierat_iu_iu2_miss(ierat_iu_iu2_miss), + .ierat_iu_iu2_isi(ierat_iu_iu2_isi), + .ierat_iu_iu2_error(ierat_iu_iu2_error), + .ierat_iu_iu2_multihit(ierat_iu_iu2_multihit), + + .ierat_iu_cam_change(ierat_iu_cam_change), + + .iu_pc_err_ierat_multihit(iu_pc_err_ierat_multihit), + .iu_pc_err_ierat_parity(iu_pc_err_ierat_parity), + + // noop_touch + // fir_par, fir_multihit + + // erat request to mmu + .iu_mm_ierat_req(iu_mm_ierat_req), + .iu_mm_ierat_req_nonspec(iu_mm_ierat_req_nonspec), + .iu_mm_ierat_thdid(iu_mm_ierat_thdid), + .iu_mm_ierat_state(iu_mm_ierat_state), + .iu_mm_ierat_tid(iu_mm_ierat_tid), + .iu_mm_ierat_flush(iu_mm_ierat_flush), + .iu_mm_perf_itlb(iu_mm_perf_itlb), + + // write interface to mmucr0,1 + .iu_mm_ierat_mmucr0(iu_mm_ierat_mmucr0), + .iu_mm_ierat_mmucr0_we(iu_mm_ierat_mmucr0_we), + .iu_mm_ierat_mmucr1(iu_mm_ierat_mmucr1), + .iu_mm_ierat_mmucr1_we(iu_mm_ierat_mmucr1_we), + + // spr's + // clkg_ctl + .xu_iu_msr_hv(xu_iu_msr_hv), + .xu_iu_msr_pr(xu_iu_msr_pr), + .xu_iu_msr_is(xu_iu_msr_is), + .xu_iu_msr_cm(xu_iu_msr_cm), + .xu_iu_hid_mmu_mode(xu_iu_hid_mmu_mode), + .xu_iu_spr_ccr2_ifrat(xu_iu_spr_ccr2_ifrat), + .xu_iu_spr_ccr2_ifratsc(xu_iu_spr_ccr2_ifratsc), + .xu_iu_xucr4_mmu_mchk(xu_iu_xucr4_mmu_mchk), + + .ierat_iu_iu2_flush_req(ierat_iu_iu2_flush_req), + + .iu_xu_ord_n_flush_req(iu_xu_ord_n_flush_req), + + .mm_iu_t0_ierat_pid(mm_iu_t0_ierat_pid), + .mm_iu_t0_ierat_mmucr0(mm_iu_t0_ierat_mmucr0), + `ifndef THREADS1 + .mm_iu_t1_ierat_pid(mm_iu_t1_ierat_pid), + .mm_iu_t1_ierat_mmucr0(mm_iu_t1_ierat_mmucr0), + `endif + .mm_iu_ierat_mmucr1(mm_iu_ierat_mmucr1), + + // debug + .pc_iu_trace_bus_enable(1'b0), + .ierat_iu_debug_group0(ierat_iu_debug_group0), + .ierat_iu_debug_group1(ierat_iu_debug_group1), + .ierat_iu_debug_group2(ierat_iu_debug_group2), + .ierat_iu_debug_group3(ierat_iu_debug_group3) + ); + + + iuq_ic_select iuq_ic_select0( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .pc_iu_func_sl_thold_0_b(pc_iu_func_sl_thold_0_b), + .pc_iu_func_slp_sl_thold_0_b(pc_iu_func_slp_sl_thold_0_b), + .pc_iu_sg_0(pc_iu_sg_0), + .force_t(force_t), + .funcslp_force(funcslp_force), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .func_scan_in(siv[2]), + .func_scan_out(sov[2]), + .pc_iu_ram_active(pc_iu_ram_active), + .pc_iu_pm_fetch_halt(pc_iu_pm_fetch_halt), + .xu_iu_run_thread(xu_iu_run_thread), + .cp_ic_stop(cp_ic_stop), + .xu_iu_msr_cm(xu_iu_msr_cm), + .cp_flush(iu_flush), + .cp_flush_into_uc(cp_flush_into_uc), + .br_iu_redirect(br_iu_redirect), + .br_iu_bta(br_iu_bta), + .cp_iu0_t0_flush_ifar(cp_iu0_t0_flush_ifar), + `ifndef THREADS1 + .cp_iu0_t1_flush_ifar(cp_iu0_t1_flush_ifar), + `endif + .cp_iu0_flush_2ucode(cp_iu0_flush_2ucode), + .cp_iu0_flush_2ucode_type(cp_iu0_flush_2ucode_type), + .cp_iu0_flush_nonspec(cp_iu0_flush_nonspec), + .ic_cp_nonspec_hit(ic_cp_nonspec_hit), + .an_ac_back_inv(an_ac_back_inv), + .an_ac_back_inv_addr(an_ac_back_inv_addr), + .an_ac_back_inv_target(an_ac_back_inv_target), + .spr_ic_prefetch_dis(spr_ic_prefetch_dis), + .spr_ic_ierat_byp_dis(spr_ic_ierat_byp_dis), + .spr_ic_idir_read(spr_ic_idir_read), + .spr_ic_idir_row(spr_ic_idir_row), + .ic_perf_t0_event(ic_perf_t0_event[3:8]), + `ifndef THREADS1 + .ic_perf_t1_event(ic_perf_t1_event[3:8]), + `endif + .iu_ierat_iu0_val(iu_ierat_iu0_val), + .iu_ierat_iu0_thdid(iu_ierat_iu0_thdid), + .iu_ierat_iu0_ifar(iu_ierat_iu0_ifar), + .iu_ierat_iu0_nonspec(iu_ierat_iu0_nonspec), + .iu_ierat_iu0_prefetch(iu_ierat_iu0_prefetch), + .iu_ierat_flush(iu_ierat_flush), + .iu_ierat_ium1_back_inv(iu_ierat_ium1_back_inv), + .ierat_iu_hold_req(ierat_iu_hold_req), + .ierat_iu_iu2_flush_req(ierat_iu_iu2_flush_req), + .ierat_iu_iu2_miss(ierat_iu_iu2_miss), + .ierat_iu_cam_change(ierat_iu_cam_change), + .mm_iu_hold_req(mm_iu_hold_req), + .mm_iu_hold_done(mm_iu_hold_done), + .mm_iu_bus_snoop_hold_req(mm_iu_bus_snoop_hold_req), + .mm_iu_bus_snoop_hold_done(mm_iu_bus_snoop_hold_done), + .lq_iu_icbi_val(lq_iu_icbi_val), + .lq_iu_icbi_addr(lq_iu_icbi_addr), + .iu_lq_icbi_complete(iu_lq_icbi_complete), + .icm_ics_iu0_preload_val(icm_ics_iu0_preload_val), + .icm_ics_iu0_preload_ifar(icm_ics_iu0_preload_ifar), + .icm_ics_prefetch_req(icm_ics_prefetch_req), + .icm_ics_prefetch_sm_idle(icm_ics_prefetch_sm_idle), + .icm_ics_hold_thread(icm_ics_hold_thread), + .icm_ics_hold_iu0(icm_ics_hold_iu0), + .icm_ics_iu3_miss_match(icm_ics_iu3_miss_match), + .icm_ics_iu3_ecc_fp_cancel(icm_ics_iu3_ecc_fp_cancel), + .ics_icm_iu0_t0_ifar(ics_icm_iu0_t0_ifar), + `ifndef THREADS1 + .ics_icm_iu0_t1_ifar(ics_icm_iu0_t1_ifar), + `endif + .ics_icm_iu0_inval(ics_icm_iu0_inval), + .ics_icm_iu0_inval_addr(ics_icm_iu0_inval_addr), + .ics_icm_iu2_flush(ics_icm_iu2_flush), + .ics_icd_dir_rd_act(ics_icd_dir_rd_act), + .ics_icd_data_rd_act(ics_icd_data_rd_act), + .ics_icd_iu0_valid(ics_icd_iu0_valid), + .ics_icd_iu0_tid(ics_icd_iu0_tid), + .ics_icd_iu0_ifar(ics_icd_iu0_ifar), + .ics_icd_iu0_index51(ics_icd_iu0_index51), + .ics_icd_iu0_inval(ics_icd_iu0_inval), + .ics_icd_iu0_2ucode(ics_icd_iu0_2ucode), + .ics_icd_iu0_2ucode_type(ics_icd_iu0_2ucode_type), + .ics_icd_iu0_prefetch(ics_icd_iu0_prefetch), + .ics_icd_iu0_read_erat(ics_icd_iu0_read_erat), + .ics_icd_iu0_spr_idir_read(ics_icd_iu0_spr_idir_read), + .ics_icd_iu1_flush(ics_icd_iu1_flush), + .ics_icd_iu2_flush(ics_icd_iu2_flush), + .icd_ics_iu1_valid(icd_ics_iu1_valid), + .icd_ics_iu1_tid(icd_ics_iu1_tid), + .icd_ics_iu1_ifar(icd_ics_iu1_ifar), + .icd_ics_iu1_2ucode(icd_ics_iu1_2ucode), + .icd_ics_iu1_2ucode_type(icd_ics_iu1_2ucode_type), + .icd_ics_iu1_read_erat(icd_ics_iu1_read_erat), + .icd_ics_iu3_miss_flush(icd_ics_iu3_miss_flush), + .icd_ics_iu2_wrong_ra_flush(icd_ics_iu2_wrong_ra_flush), + .icd_ics_iu2_cam_etc_flush(icd_ics_iu2_cam_etc_flush), + .icd_ics_iu2_ifar_eff(icd_ics_iu2_ifar_eff), + .icd_ics_iu2_2ucode(icd_ics_iu2_2ucode), + .icd_ics_iu2_2ucode_type(icd_ics_iu2_2ucode_type), + .icd_ics_iu2_valid(icd_ics_iu2_valid), + .icd_ics_iu2_read_erat_error(icd_ics_iu2_read_erat_error), + .icd_ics_iu3_parity_flush(icd_ics_iu3_parity_flush), + .icd_ics_iu3_ifar(icd_ics_iu3_ifar), + .icd_ics_iu3_2ucode(icd_ics_iu3_2ucode), + .icd_ics_iu3_2ucode_type(icd_ics_iu3_2ucode_type), + .ic_bp_iu0_val(ic_bp_iu0_val), + .ic_bp_iu0_ifar(ic_bp_iu0_ifar), + .ic_bp_iu2_flush(ic_bp_iu2_flush), + .bp_ic_iu2_redirect(bp_ic_iu2_redirect), + .bp_ic_iu3_redirect(bp_ic_iu3_redirect), + .bp_ic_iu4_redirect(bp_ic_iu4_redirect), + .bp_ic_t0_redirect_ifar(bp_ic_t0_redirect_ifar), + `ifndef THREADS1 + .bp_ic_t1_redirect_ifar(bp_ic_t1_redirect_ifar), + `endif + .uc_ic_hold(uc_ic_hold), + .uc_iu4_flush(uc_iu4_flush), + .uc_iu4_t0_flush_ifar(uc_iu4_t0_flush_ifar), + `ifndef THREADS1 + .uc_iu4_t1_flush_ifar(uc_iu4_t1_flush_ifar), + .ib_ic_t1_need_fetch(ib_ic_t1_need_fetch), + `endif + .ib_ic_t0_need_fetch(ib_ic_t0_need_fetch), + .event_bus_enable(pc_iu_event_bus_enable) + ); + + + iuq_ic_dir iuq_ic_dir0( + .vcs(vdd), + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .pc_iu_func_sl_thold_0_b(pc_iu_func_sl_thold_0_b), + .pc_iu_func_slp_sl_thold_0_b(pc_iu_func_slp_sl_thold_0_b), + .pc_iu_time_sl_thold_0(pc_iu_time_sl_thold_0), + .pc_iu_repr_sl_thold_0(pc_iu_repr_sl_thold_0), + .pc_iu_abst_sl_thold_0(pc_iu_abst_sl_thold_0), + .pc_iu_abst_sl_thold_0_b(pc_iu_abst_sl_thold_0_b), + .pc_iu_abst_slp_sl_thold_0(pc_iu_abst_slp_sl_thold_0), + .pc_iu_ary_nsl_thold_0(pc_iu_ary_nsl_thold_0), + .pc_iu_ary_slp_nsl_thold_0(pc_iu_ary_slp_nsl_thold_0), + .pc_iu_bolt_sl_thold_0(pc_iu_bolt_sl_thold_0), + .pc_iu_sg_0(pc_iu_sg_0), + .pc_iu_sg_1(pc_iu_sg_1), + .force_t(force_t), + .funcslp_force(funcslp_force), + .abst_force(abst_force), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .clkoff_b(clkoff_b), + .act_dis(act_dis), + .g8t_clkoff_b(g8t_clkoff_b), + .g8t_d_mode(g8t_d_mode), + .g8t_delay_lclkr(g8t_delay_lclkr), + .g8t_mpw1_b(g8t_mpw1_b), + .g8t_mpw2_b(g8t_mpw2_b), + .g6t_clkoff_b(g6t_clkoff_b), + .g6t_act_dis(g6t_act_dis), + .g6t_d_mode(g6t_d_mode), + .g6t_delay_lclkr(g6t_delay_lclkr), + .g6t_mpw1_b(g6t_mpw1_b), + .g6t_mpw2_b(g6t_mpw2_b), + .tc_ac_ccflush_dc(tc_ac_ccflush_dc), + .tc_ac_scan_dis_dc_b(tc_ac_scan_dis_dc_b), + .tc_ac_scan_diag_dc(tc_ac_scan_diag_dc), + .func_scan_in(siv[3]), + .time_scan_in(tsiv[1]), + .repr_scan_in(repr_scan_in), + .abst_scan_in(abst_scan_in), + .func_scan_out(sov[3]), + .time_scan_out(tsov[1]), + .repr_scan_out(repr_scan_out), + .abst_scan_out(abst_scan_out), + .spr_ic_cls(spr_ic_cls), + .spr_ic_ierat_byp_dis(spr_ic_ierat_byp_dis), + .spr_ic_idir_way(spr_ic_idir_way), + .ic_spr_idir_done(ic_spr_idir_done), + .ic_spr_idir_lru(ic_spr_idir_lru), + .ic_spr_idir_parity(ic_spr_idir_parity), + .ic_spr_idir_endian(ic_spr_idir_endian), + .ic_spr_idir_valid(ic_spr_idir_valid), + .ic_spr_idir_tag(ic_spr_idir_tag), + .ic_perf_t0_event(ic_perf_t0_event[9:11]), + `ifndef THREADS1 + .ic_perf_t1_event(ic_perf_t1_event[9:11]), + `endif + .ic_perf_event(ic_perf_event), + .iu_pc_err_icache_parity(iu_pc_err_icache_parity), + .iu_pc_err_icachedir_parity(iu_pc_err_icachedir_parity), + .iu_pc_err_icachedir_multihit(iu_pc_err_icachedir_multihit), + .pc_iu_inj_icache_parity(pc_iu_inj_icache_parity), + .pc_iu_inj_icachedir_parity(pc_iu_inj_icachedir_parity), + .pc_iu_inj_icachedir_multihit(pc_iu_inj_icachedir_multihit), + .pc_iu_abist_g8t_wenb(pc_iu_abist_g8t_wenb), + .pc_iu_abist_g8t1p_renb_0(pc_iu_abist_g8t1p_renb_0), + .pc_iu_abist_di_0(pc_iu_abist_di_0), + .pc_iu_abist_g8t_bw_1(pc_iu_abist_g8t_bw_1), + .pc_iu_abist_g8t_bw_0(pc_iu_abist_g8t_bw_0), + .pc_iu_abist_waddr_0(pc_iu_abist_waddr_0), + .pc_iu_abist_raddr_0(pc_iu_abist_raddr_0), + .pc_iu_abist_ena_dc(pc_iu_abist_ena_dc), + .pc_iu_abist_wl128_comp_ena(pc_iu_abist_wl128_comp_ena), + .pc_iu_abist_raw_dc_b(pc_iu_abist_raw_dc_b), + .pc_iu_abist_g8t_dcomp(pc_iu_abist_g8t_dcomp), + .pc_iu_abist_g6t_bw(pc_iu_abist_g6t_bw), + .pc_iu_abist_di_g6t_2r(pc_iu_abist_di_g6t_2r), + .pc_iu_abist_wl512_comp_ena(pc_iu_abist_wl512_comp_ena), + .pc_iu_abist_dcomp_g6t_2r(pc_iu_abist_dcomp_g6t_2r), + .pc_iu_abist_g6t_r_wb(pc_iu_abist_g6t_r_wb), + .an_ac_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc), + .pc_iu_bo_enable_2(pc_iu_bo_enable_2), + .pc_iu_bo_reset(pc_iu_bo_reset), + .pc_iu_bo_unload(pc_iu_bo_unload), + .pc_iu_bo_repair(pc_iu_bo_repair), + .pc_iu_bo_shdata(pc_iu_bo_shdata), + .pc_iu_bo_select(pc_iu_bo_select), + .iu_pc_bo_fail(iu_pc_bo_fail), + .iu_pc_bo_diagout(iu_pc_bo_diagout), + .iu_mm_ierat_epn(iu_mm_ierat_epn), + .iu_ierat_iu1_back_inv(iu_ierat_iu1_back_inv), + .ierat_iu_iu2_rpn(ierat_iu_iu2_rpn), + .ierat_iu_iu2_wimge(ierat_iu_iu2_wimge), + .ierat_iu_iu2_u(ierat_iu_iu2_u), + .ierat_iu_iu2_error(ierat_iu_iu2_error), + .ierat_iu_iu2_miss(ierat_iu_iu2_miss), + .ierat_iu_iu2_multihit(ierat_iu_iu2_multihit), + .ierat_iu_iu2_isi(ierat_iu_iu2_isi), + .ierat_iu_iu2_flush_req(ierat_iu_iu2_flush_req), + .ierat_iu_cam_change(ierat_iu_cam_change), + .lq_iu_ici_val(lq_iu_ici_val), + .ics_icd_dir_rd_act(ics_icd_dir_rd_act), + .ics_icd_data_rd_act(ics_icd_data_rd_act), + .ics_icd_iu0_valid(ics_icd_iu0_valid), + .ics_icd_iu0_tid(ics_icd_iu0_tid), + .ics_icd_iu0_ifar(ics_icd_iu0_ifar), + .ics_icd_iu0_index51(ics_icd_iu0_index51), + .ics_icd_iu0_inval(ics_icd_iu0_inval), + .ics_icd_iu0_2ucode(ics_icd_iu0_2ucode), + .ics_icd_iu0_2ucode_type(ics_icd_iu0_2ucode_type), + .ics_icd_iu0_prefetch(ics_icd_iu0_prefetch), + .ics_icd_iu0_read_erat(ics_icd_iu0_read_erat), + .ics_icd_iu0_spr_idir_read(ics_icd_iu0_spr_idir_read), + .ics_icd_iu1_flush(ics_icd_iu1_flush), + .ics_icd_iu2_flush(ics_icd_iu2_flush), + .icd_ics_iu1_valid(icd_ics_iu1_valid), + .icd_ics_iu1_tid(icd_ics_iu1_tid), + .icd_ics_iu1_ifar(icd_ics_iu1_ifar), + .icd_ics_iu1_2ucode(icd_ics_iu1_2ucode), + .icd_ics_iu1_2ucode_type(icd_ics_iu1_2ucode_type), + .icd_ics_iu1_read_erat(icd_ics_iu1_read_erat), + .icd_ics_iu3_miss_flush(icd_ics_iu3_miss_flush), + .icd_ics_iu2_wrong_ra_flush(icd_ics_iu2_wrong_ra_flush), + .icd_ics_iu2_cam_etc_flush(icd_ics_iu2_cam_etc_flush), + .icd_ics_iu2_ifar_eff(icd_ics_iu2_ifar_eff), + .icd_ics_iu2_2ucode(icd_ics_iu2_2ucode), + .icd_ics_iu2_2ucode_type(icd_ics_iu2_2ucode_type), + .icd_ics_iu2_valid(icd_ics_iu2_valid), + .icd_ics_iu2_read_erat_error(icd_ics_iu2_read_erat_error), + .icd_ics_iu3_parity_flush(icd_ics_iu3_parity_flush), + .icd_ics_iu3_ifar(icd_ics_iu3_ifar), + .icd_ics_iu3_2ucode(icd_ics_iu3_2ucode), + .icd_ics_iu3_2ucode_type(icd_ics_iu3_2ucode_type), + .icm_icd_lru_addr(icm_icd_lru_addr), + .icm_icd_dir_inval(icm_icd_dir_inval), + .icm_icd_dir_val(icm_icd_dir_val), + .icm_icd_data_write(icm_icd_data_write), + .icm_icd_reload_addr(icm_icd_reload_addr), + .icm_icd_reload_data(icm_icd_reload_data), + .icm_icd_reload_way(icm_icd_reload_way), + .icm_icd_load(icm_icd_load), + .icm_icd_load_addr(icm_icd_load_addr), + .icm_icd_load_2ucode(icm_icd_load_2ucode), + .icm_icd_load_2ucode_type(icm_icd_load_2ucode_type), + .icm_icd_dir_write(icm_icd_dir_write), + .icm_icd_dir_write_addr(icm_icd_dir_write_addr), + .icm_icd_dir_write_endian(icm_icd_dir_write_endian), + .icm_icd_dir_write_way(icm_icd_dir_write_way), + .icm_icd_lru_write(icm_icd_lru_write), + .icm_icd_lru_write_addr(icm_icd_lru_write_addr), + .icm_icd_lru_write_way(icm_icd_lru_write_way), + .icm_icd_ecc_inval(icm_icd_ecc_inval), + .icm_icd_ecc_addr(icm_icd_ecc_addr), + .icm_icd_ecc_way(icm_icd_ecc_way), + .icm_icd_iu3_ecc_fp_cancel(icm_icd_iu3_ecc_fp_cancel), + .icm_icd_any_reld_r2(icm_icd_any_reld_r2), + .icd_icm_miss(icd_icm_miss), + .icd_icm_prefetch(icd_icm_prefetch), + .icd_icm_tid(icd_icm_tid), + .icd_icm_addr_real(icd_icm_addr_real), + .icd_icm_addr_eff(icd_icm_addr_eff), + .icd_icm_wimge(icd_icm_wimge), + .icd_icm_userdef(icd_icm_userdef), + .icd_icm_2ucode(icd_icm_2ucode), + .icd_icm_2ucode_type(icd_icm_2ucode_type), + .icd_icm_iu2_inval(icd_icm_iu2_inval), + .icd_icm_any_iu2_valid(icd_icm_any_iu2_valid), + .icd_icm_row_lru(icd_icm_row_lru), + .icd_icm_row_val(icd_icm_row_val), + .ic_bp_iu2_t0_val(ic_bp_iu2_t0_val), + `ifndef THREADS1 + .ic_bp_iu2_t1_val(ic_bp_iu2_t1_val), + `endif + .ic_bp_iu2_ifar(ic_bp_iu2_ifar), + .ic_bp_iu2_2ucode(ic_bp_iu2_2ucode), + .ic_bp_iu2_2ucode_type(ic_bp_iu2_2ucode_type), + .ic_bp_iu2_error(ic_bp_iu2_error), + .ic_bp_iu3_flush(ic_bp_iu3_flush), + .ic_bp_iu2_0_instr(ic_bp_iu2_0_instr), + .ic_bp_iu2_1_instr(ic_bp_iu2_1_instr), + .ic_bp_iu2_2_instr(ic_bp_iu2_2_instr), + .ic_bp_iu2_3_instr(ic_bp_iu2_3_instr), + .event_bus_enable(pc_iu_event_bus_enable) + ); + + + iuq_ic_miss iuq_ic_miss0( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .pc_iu_func_sl_thold_0_b(pc_iu_func_sl_thold_0_b), + .pc_iu_sg_0(pc_iu_sg_0), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scan_in(siv[4]), + .scan_out(sov[4]), + .iu_flush(iu_flush), + .br_iu_redirect(br_iu_redirect), + .bp_ic_iu4_redirect(bp_ic_iu4_redirect), + .ic_bp_iu3_ecc_err(ic_bp_iu3_ecc_err), + .ics_icm_iu0_t0_ifar(ics_icm_iu0_t0_ifar), + `ifndef THREADS1 + .ics_icm_iu0_t1_ifar(ics_icm_iu0_t1_ifar), + `endif + .ics_icm_iu0_inval(ics_icm_iu0_inval), + .ics_icm_iu0_inval_addr(ics_icm_iu0_inval_addr), + .ics_icm_iu2_flush(ics_icm_iu2_flush), + .icm_ics_hold_thread(icm_ics_hold_thread), + .icm_ics_hold_iu0(icm_ics_hold_iu0), + .icm_ics_iu3_miss_match(icm_ics_iu3_miss_match), + .icm_ics_iu3_ecc_fp_cancel(icm_ics_iu3_ecc_fp_cancel), + .icm_ics_iu0_preload_val(icm_ics_iu0_preload_val), + .icm_ics_iu0_preload_ifar(icm_ics_iu0_preload_ifar), + .icm_ics_prefetch_req(icm_ics_prefetch_req), + .icm_ics_prefetch_sm_idle(icm_ics_prefetch_sm_idle), + .icm_icd_lru_addr(icm_icd_lru_addr), + .icm_icd_dir_inval(icm_icd_dir_inval), + .icm_icd_dir_val(icm_icd_dir_val), + .icm_icd_data_write(icm_icd_data_write), + .icm_icd_reload_addr(icm_icd_reload_addr), + .icm_icd_reload_data(icm_icd_reload_data), + .icm_icd_reload_way(icm_icd_reload_way), + .icm_icd_load(icm_icd_load), + .icm_icd_load_addr(icm_icd_load_addr), + .icm_icd_load_2ucode(icm_icd_load_2ucode), + .icm_icd_load_2ucode_type(icm_icd_load_2ucode_type), + .icm_icd_dir_write(icm_icd_dir_write), + .icm_icd_dir_write_addr(icm_icd_dir_write_addr), + .icm_icd_dir_write_endian(icm_icd_dir_write_endian), + .icm_icd_dir_write_way(icm_icd_dir_write_way), + .icm_icd_lru_write(icm_icd_lru_write), + .icm_icd_lru_write_addr(icm_icd_lru_write_addr), + .icm_icd_lru_write_way(icm_icd_lru_write_way), + .icm_icd_ecc_inval(icm_icd_ecc_inval), + .icm_icd_ecc_addr(icm_icd_ecc_addr), + .icm_icd_ecc_way(icm_icd_ecc_way), + .icm_icd_iu3_ecc_fp_cancel(icm_icd_iu3_ecc_fp_cancel), + .icm_icd_any_reld_r2(icm_icd_any_reld_r2), + .icd_icm_miss(icd_icm_miss), + .icd_icm_prefetch(icd_icm_prefetch), + .icd_icm_tid(icd_icm_tid), + .icd_icm_addr_real(icd_icm_addr_real), + .icd_icm_addr_eff(icd_icm_addr_eff), + .icd_icm_wimge(icd_icm_wimge), + .icd_icm_userdef(icd_icm_userdef), + .icd_icm_2ucode(icd_icm_2ucode), + .icd_icm_2ucode_type(icd_icm_2ucode_type), + .icd_icm_iu2_inval(icd_icm_iu2_inval), + .icd_icm_any_iu2_valid(icd_icm_any_iu2_valid), + .icd_icm_row_lru(icd_icm_row_lru), + .icd_icm_row_val(icd_icm_row_val), + .ic_perf_t0_event(ic_perf_t0_event[0:2]), + `ifndef THREADS1 + .ic_perf_t1_event(ic_perf_t1_event[0:2]), + `endif + .cp_async_block(cp_async_block), + .iu_mm_lmq_empty(iu_mm_lmq_empty), + .iu_xu_icache_quiesce(iu_xu_icache_quiesce), + .iu_pc_icache_quiesce(iu_pc_icache_quiesce), + .an_ac_reld_data_vld(an_ac_reld_data_vld), + .an_ac_reld_core_tag(an_ac_reld_core_tag), + .an_ac_reld_qw(an_ac_reld_qw), + .an_ac_reld_data(an_ac_reld_data), + .an_ac_reld_ecc_err(an_ac_reld_ecc_err), + .an_ac_reld_ecc_err_ue(an_ac_reld_ecc_err_ue), + .spr_ic_cls(spr_ic_cls), + .spr_ic_bp_config(spr_ic_bp_config), + .iu_lq_request(iu_lq_request), + .iu_lq_ctag(iu_lq_ctag), + .iu_lq_ra(iu_lq_ra), + .iu_lq_wimge(iu_lq_wimge), + .iu_lq_userdef(iu_lq_userdef), + .event_bus_enable(pc_iu_event_bus_enable) + ); + + //----------------------------------------------- + // performance + //----------------------------------------------- + + assign unit_t0_events_en = (pc_iu_event_count_mode[0] & xu_iu_msr_pr[0] ) | //problem state + (pc_iu_event_count_mode[1] & ~xu_iu_msr_pr[0] & xu_iu_msr_hv[0]) | //guest supervisor state + (pc_iu_event_count_mode[2] & ~xu_iu_msr_pr[0] & ~xu_iu_msr_hv[0]) ; //hypervisor state + + // events_in(1:63). Decode 0 is used for event_bus_in + assign unit_t0_events_in = {ic_perf_t0_event[0:11], ic_perf_event[0:1], 1'b0, + 16'b0, + slice_ic_t0_perf_events, 11'b0} & + {63{unit_t0_events_en}}; + + tri_event_mux1t #(.EVENTS_IN(64), .EVENTS_OUT(4)) iuq_perf0( + .vd(vdd), + .gd(gnd), + .select_bits(spr_perf_event_mux_ctrls[0:23]), + .unit_events_in(unit_t0_events_in), + .event_bus_in(event_bus_in[0:3]), + .event_bus_out(event_bus_out_d[0:3]) + ); + + `ifndef THREADS1 + assign unit_t1_events_en = (pc_iu_event_count_mode[0] & xu_iu_msr_pr[1] ) | //problem state + (pc_iu_event_count_mode[1] & ~xu_iu_msr_pr[1] & xu_iu_msr_hv[1]) | //guest supervisor state + (pc_iu_event_count_mode[2] & ~xu_iu_msr_pr[1] & ~xu_iu_msr_hv[1]) ; //hypervisor state + + + assign unit_t1_events_in = {ic_perf_t1_event[0:11], ic_perf_event[0:1], 1'b0, + 16'b0, + slice_ic_t1_perf_events, 11'b0} & + {63{unit_t1_events_en}}; + + tri_event_mux1t #(.EVENTS_IN(64), .EVENTS_OUT(4)) iuq_perf1( + .vd(vdd), + .gd(gnd), + .select_bits(spr_perf_event_mux_ctrls[24:47]), + .unit_events_in(unit_t1_events_in), + .event_bus_in(event_bus_in[4:7]), + .event_bus_out(event_bus_out_d[4:7]) + ); + `endif + + tri_rlmreg_p #(.WIDTH(4*`THREADS), .INIT(0)) perf_bus_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pc_iu_event_bus_enable), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[perf_bus_offset:perf_bus_offset + 4*`THREADS - 1]), + .scout(sov[perf_bus_offset:perf_bus_offset + 4*`THREADS - 1]), + .din(event_bus_out_d), + .dout(event_bus_out_l2) + ); + + assign event_bus_out = event_bus_out_l2; + + //----------------------------------------------- + // pervasive + //----------------------------------------------- + + tri_plat #(.WIDTH(1)) perv_3to2_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + .din(pc_iu_bo_enable_3), + .q(pc_iu_bo_enable_2) + ); + + tri_plat #(.WIDTH(11)) perv_2to1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + .din({pc_iu_func_sl_thold_2, + pc_iu_func_slp_sl_thold_2, + pc_iu_time_sl_thold_2, + pc_iu_repr_sl_thold_2, + pc_iu_abst_sl_thold_2, + pc_iu_abst_slp_sl_thold_2, + pc_iu_ary_nsl_thold_2, + pc_iu_ary_slp_nsl_thold_2, + pc_iu_regf_slp_sl_thold_2, + pc_iu_bolt_sl_thold_2, + pc_iu_sg_2}), + .q( {pc_iu_func_sl_thold_1, + pc_iu_func_slp_sl_thold_1, + pc_iu_time_sl_thold_1, + pc_iu_repr_sl_thold_1, + pc_iu_abst_sl_thold_1, + pc_iu_abst_slp_sl_thold_1, + pc_iu_ary_nsl_thold_1, + pc_iu_ary_slp_nsl_thold_1, + pc_iu_regf_slp_sl_thold_1, + pc_iu_bolt_sl_thold_1, + pc_iu_sg_1}) + ); + + tri_plat #(.WIDTH(11)) perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + .din({pc_iu_func_sl_thold_1, + pc_iu_func_slp_sl_thold_1, + pc_iu_time_sl_thold_1, + pc_iu_repr_sl_thold_1, + pc_iu_abst_sl_thold_1, + pc_iu_abst_slp_sl_thold_1, + pc_iu_ary_nsl_thold_1, + pc_iu_ary_slp_nsl_thold_1, + pc_iu_regf_slp_sl_thold_1, + pc_iu_bolt_sl_thold_1, + pc_iu_sg_1}), + .q( {pc_iu_func_sl_thold_0, + pc_iu_func_slp_sl_thold_0, + pc_iu_time_sl_thold_0, + pc_iu_repr_sl_thold_0, + pc_iu_abst_sl_thold_0, + pc_iu_abst_slp_sl_thold_0, + pc_iu_ary_nsl_thold_0, + pc_iu_ary_slp_nsl_thold_0, + pc_iu_regf_slp_sl_thold_0, + pc_iu_bolt_sl_thold_0, + pc_iu_sg_0}) + ); + + tri_lcbor perv_lcbor( + .clkoff_b(clkoff_b), + .thold(pc_iu_func_sl_thold_0), + .sg(pc_iu_sg_0), + .act_dis(act_dis), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b) + ); + + tri_lcbor func_slp_lcbor( + .clkoff_b(clkoff_b), + .thold(pc_iu_func_slp_sl_thold_0), + .sg(pc_iu_sg_0), + .act_dis(act_dis), + .force_t(funcslp_force), + .thold_b(pc_iu_func_slp_sl_thold_0_b) + ); + + tri_lcbor abst_lcbor( + .clkoff_b(clkoff_b), + .thold(pc_iu_abst_sl_thold_0), + .sg(pc_iu_sg_0), + .act_dis(act_dis), + .force_t(abst_force), + .thold_b(pc_iu_abst_sl_thold_0_b) + ); + + //--------------------------------------------------------------------- + // Scan + //--------------------------------------------------------------------- + assign func_scan_in_cam = func_scan_in; + assign siv = {func_scan_out_cam, sov[0:scan_right-1]}; + assign func_scan_out = sov[scan_right] & tc_ac_scan_dis_dc_b; + + assign tsiv = {time_scan_in, tsov[0]}; + assign time_scan_out = tsov[1] & tc_ac_scan_dis_dc_b; + +endmodule diff --git a/dev/verilog/work/iuq_ic_dir.v b/dev/verilog/work/iuq_ic_dir.v new file mode 100755 index 0000000..c713021 --- /dev/null +++ b/dev/verilog/work/iuq_ic_dir.v @@ -0,0 +1,2487 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//******************************************************************** +//* +//* TITLE: +//* +//* NAME: iuq_ic_dir.v +//* +//********************************************************************* + +`include "tri_a2o.vh" + +module iuq_ic_dir( + inout vcs, + inout vdd, + inout gnd, + (* pin_data ="PIN_FUNCTION=/G_CLK/" *) + input [0:`NCLK_WIDTH-1] nclk, + input pc_iu_func_sl_thold_0_b, + input pc_iu_func_slp_sl_thold_0_b, + input pc_iu_time_sl_thold_0, + input pc_iu_repr_sl_thold_0, + input pc_iu_abst_sl_thold_0, + input pc_iu_abst_sl_thold_0_b, + input pc_iu_abst_slp_sl_thold_0, + input pc_iu_ary_nsl_thold_0, + input pc_iu_ary_slp_nsl_thold_0, + input pc_iu_bolt_sl_thold_0, + input pc_iu_sg_0, + input pc_iu_sg_1, + input force_t, + input funcslp_force, + input abst_force, + + input d_mode, + input delay_lclkr, + input mpw1_b, + input mpw2_b, + input clkoff_b, + input act_dis, + + input g8t_clkoff_b, + input g8t_d_mode, + input [0:4] g8t_delay_lclkr, + input [0:4] g8t_mpw1_b, + input g8t_mpw2_b, + + input g6t_clkoff_b, + input g6t_act_dis, + input g6t_d_mode, + input [0:3] g6t_delay_lclkr, + input [0:4] g6t_mpw1_b, + input g6t_mpw2_b, + + input tc_ac_ccflush_dc, + input tc_ac_scan_dis_dc_b, + input tc_ac_scan_diag_dc, + (* pin_data ="PIN_FUNCTION=/SCAN_IN/" *) + input func_scan_in, + (* pin_data ="PIN_FUNCTION=/SCAN_IN/" *) + input time_scan_in, + (* pin_data ="PIN_FUNCTION=/SCAN_IN/" *) + input repr_scan_in, + (* pin_data ="PIN_FUNCTION=/SCAN_IN/" *) + input [0:2] abst_scan_in, + (* pin_data ="PIN_FUNCTION=/SCAN_OUT/" *) + output func_scan_out, + (* pin_data ="PIN_FUNCTION=/SCAN_OUT/" *) + output time_scan_out, + (* pin_data ="PIN_FUNCTION=/SCAN_OUT/" *) + output repr_scan_out, + (* pin_data ="PIN_FUNCTION=/SCAN_OUT/" *) + output [0:2] abst_scan_out, + + input spr_ic_cls, // (0): 64B cacheline, (1): 128B cacheline + input spr_ic_ierat_byp_dis, + + input [0:1] spr_ic_idir_way, + output ic_spr_idir_done, + output [0:2] ic_spr_idir_lru, + output [0:3] ic_spr_idir_parity, + output ic_spr_idir_endian, + output ic_spr_idir_valid, + output [0:28] ic_spr_idir_tag, + + output [9:11] ic_perf_t0_event, + `ifndef THREADS1 + output [9:11] ic_perf_t1_event, + `endif + output [0:1] ic_perf_event, + + output iu_pc_err_icache_parity, + output iu_pc_err_icachedir_parity, + output iu_pc_err_icachedir_multihit, + + input pc_iu_inj_icache_parity, + input pc_iu_inj_icachedir_parity, + input pc_iu_inj_icachedir_multihit, + + input pc_iu_abist_g8t_wenb, + input pc_iu_abist_g8t1p_renb_0, + input [0:3] pc_iu_abist_di_0, + input pc_iu_abist_g8t_bw_1, + input pc_iu_abist_g8t_bw_0, + input [3:9] pc_iu_abist_waddr_0, + input [1:9] pc_iu_abist_raddr_0, + input pc_iu_abist_ena_dc, + input pc_iu_abist_wl128_comp_ena, + input pc_iu_abist_raw_dc_b, + input [0:3] pc_iu_abist_g8t_dcomp, + input [0:1] pc_iu_abist_g6t_bw, + input [0:3] pc_iu_abist_di_g6t_2r, + input pc_iu_abist_wl512_comp_ena, + input [0:3] pc_iu_abist_dcomp_g6t_2r, + input pc_iu_abist_g6t_r_wb, + input an_ac_lbist_ary_wrt_thru_dc, + + input pc_iu_bo_enable_2, // bolt-on ABIST + input pc_iu_bo_reset, + input pc_iu_bo_unload, + input pc_iu_bo_repair, + input pc_iu_bo_shdata, + input [0:3] pc_iu_bo_select, + output [0:3] iu_pc_bo_fail, + output [0:3] iu_pc_bo_diagout, + + output [0:51] iu_mm_ierat_epn, + + output iu_ierat_iu1_back_inv, + + input [64-`REAL_IFAR_WIDTH:51] ierat_iu_iu2_rpn, + input [0:4] ierat_iu_iu2_wimge, + input [0:3] ierat_iu_iu2_u, + input [0:2] ierat_iu_iu2_error, + input ierat_iu_iu2_miss, + input ierat_iu_iu2_multihit, + input ierat_iu_iu2_isi, + input [0:`THREADS-1] ierat_iu_iu2_flush_req, + input ierat_iu_cam_change, + + // Cache invalidate + input lq_iu_ici_val, + + // IU IC Select + input ics_icd_dir_rd_act, + input [0:1] ics_icd_data_rd_act, + input ics_icd_iu0_valid, + input [0:`THREADS-1] ics_icd_iu0_tid, + input [62-`EFF_IFAR_ARCH:61] ics_icd_iu0_ifar, + input ics_icd_iu0_index51, + input ics_icd_iu0_inval, + input ics_icd_iu0_2ucode, + input ics_icd_iu0_2ucode_type, + input ics_icd_iu0_prefetch, + input ics_icd_iu0_read_erat, + input ics_icd_iu0_spr_idir_read, + + input [0:`THREADS-1] ics_icd_iu1_flush, + input [0:`THREADS-1] ics_icd_iu2_flush, + output icd_ics_iu1_valid, + output [0:`THREADS-1] icd_ics_iu1_tid, + output [62-`EFF_IFAR_WIDTH:61] icd_ics_iu1_ifar, + output icd_ics_iu1_2ucode, + output icd_ics_iu1_2ucode_type, + output [0:`THREADS-1] icd_ics_iu1_read_erat, + output [0:`THREADS-1] icd_ics_iu2_wrong_ra_flush, + output [0:`THREADS-1] icd_ics_iu2_cam_etc_flush, + output [62-`EFF_IFAR_WIDTH:61] icd_ics_iu2_ifar_eff, + output icd_ics_iu2_2ucode, + output icd_ics_iu2_2ucode_type, + output icd_ics_iu2_valid, + output [0:`THREADS-1] icd_ics_iu2_read_erat_error, + output [0:`THREADS-1] icd_ics_iu3_miss_flush, + output [0:`THREADS-1] icd_ics_iu3_parity_flush, + output [62-`EFF_IFAR_WIDTH:61] icd_ics_iu3_ifar, + output icd_ics_iu3_2ucode, + output icd_ics_iu3_2ucode_type, + + // IU IC Miss + input [51:57] icm_icd_lru_addr, + input icm_icd_dir_inval, + input icm_icd_dir_val, + input icm_icd_data_write, + input [51:59] icm_icd_reload_addr, + input [0:143] icm_icd_reload_data, + input [0:3] icm_icd_reload_way, + input [0:`THREADS-1] icm_icd_load, + input [62-`EFF_IFAR_WIDTH:61] icm_icd_load_addr, + input icm_icd_load_2ucode, + input icm_icd_load_2ucode_type, + input icm_icd_dir_write, + input [64-`REAL_IFAR_WIDTH:57] icm_icd_dir_write_addr, + input icm_icd_dir_write_endian, + input [0:3] icm_icd_dir_write_way, + input icm_icd_lru_write, + input [51:57] icm_icd_lru_write_addr, + input [0:3] icm_icd_lru_write_way, + input icm_icd_ecc_inval, + input [51:57] icm_icd_ecc_addr, + input [0:3] icm_icd_ecc_way, + input icm_icd_iu3_ecc_fp_cancel, + input icm_icd_any_reld_r2, + + output icd_icm_miss, + output icd_icm_prefetch, + output [0:`THREADS-1] icd_icm_tid, + output [64-`REAL_IFAR_WIDTH:61] icd_icm_addr_real, + output [62-`EFF_IFAR_WIDTH:51] icd_icm_addr_eff, + output [0:4] icd_icm_wimge, // (1): CI + output [0:3] icd_icm_userdef, + output icd_icm_2ucode, + output icd_icm_2ucode_type, + output icd_icm_iu2_inval, + output icd_icm_any_iu2_valid, + + output [0:2] icd_icm_row_lru, + output [0:3] icd_icm_row_val, + + //Branch Predict + // iu3 + output [0:3] ic_bp_iu2_t0_val, + `ifndef THREADS1 + output [0:3] ic_bp_iu2_t1_val, + `endif + output [62-`EFF_IFAR_WIDTH:61] ic_bp_iu2_ifar, + output ic_bp_iu2_2ucode, + output ic_bp_iu2_2ucode_type, + output [0:2] ic_bp_iu2_error, + output [0:`THREADS-1] ic_bp_iu3_flush, + + // iu3 instruction(0:31) + predecode(32:35) + output [0:35] ic_bp_iu2_0_instr, + output [0:35] ic_bp_iu2_1_instr, + output [0:35] ic_bp_iu2_2_instr, + output [0:35] ic_bp_iu2_3_instr, + + input event_bus_enable +); + + parameter ways = 4; + parameter dir_way_width = 34; + parameter dir_ext_bits = 8 - ((52 - (64 - `REAL_IFAR_WIDTH)) % 8); + parameter dir_parity_width = (52 - (64 - `REAL_IFAR_WIDTH) + dir_ext_bits)/8; + + + parameter iu1_valid_offset = 0; + parameter iu1_tid_offset = iu1_valid_offset + 1; + parameter iu1_ifar_offset = iu1_tid_offset + `THREADS; + parameter iu1_index51_offset = iu1_ifar_offset + `EFF_IFAR_ARCH; + parameter iu1_inval_offset = iu1_index51_offset + 1; + parameter iu1_prefetch_offset = iu1_inval_offset + 1; + parameter iu1_read_erat_offset = iu1_prefetch_offset + 1; + parameter iu1_2ucode_offset = iu1_read_erat_offset + 1; + parameter iu1_2ucode_type_offset = iu1_2ucode_offset + 1; + parameter iu2_valid_offset = iu1_2ucode_type_offset + 1; + parameter iu2_tid_offset = iu2_valid_offset + 1; + parameter iu2_ifar_eff_offset = iu2_tid_offset + `THREADS; + parameter iu2_index51_offset = iu2_ifar_eff_offset + `EFF_IFAR_ARCH; + parameter iu2_2ucode_offset = iu2_index51_offset + 1; + parameter iu2_2ucode_type_offset = iu2_2ucode_offset + 1; + parameter iu2_inval_offset = iu2_2ucode_type_offset + 1; + parameter iu2_prefetch_offset = iu2_inval_offset + 1; + parameter iu2_read_erat_offset = iu2_prefetch_offset + 1; + parameter iu2_cam_change_etc_offset = iu2_read_erat_offset + 1; + parameter iu2_stored_rpn_offset = iu2_cam_change_etc_offset + 1; + parameter iu2_dir_rd_val_offset = iu2_stored_rpn_offset + `REAL_IFAR_WIDTH-12; + parameter iu2_dir_dataout_offset = iu2_dir_rd_val_offset + 4; + parameter iu3_dir_parity_err_way_offset = iu2_dir_dataout_offset + 1; //handled in tri + parameter iu2_data_dataout_offset = iu3_dir_parity_err_way_offset + 4; + parameter dir_val_offset = iu2_data_dataout_offset + 1; //handled in tri + parameter dir_lru_offset = dir_val_offset + (128 * 4); + parameter iu3_miss_flush_offset = dir_lru_offset + (128 * 3); + parameter iu3_tid_offset = iu3_miss_flush_offset + 1; + parameter iu3_ifar_offset = iu3_tid_offset + `THREADS; + parameter iu3_2ucode_offset = iu3_ifar_offset + `EFF_IFAR_WIDTH; + parameter iu3_2ucode_type_offset = iu3_2ucode_offset + 1; + parameter iu3_erat_err_offset = iu3_2ucode_type_offset + 1; + parameter iu3_multihit_err_way_offset = iu3_erat_err_offset + 1; + parameter iu3_multihit_flush_offset = iu3_multihit_err_way_offset + 4; + parameter iu3_data_parity_err_way_offset = iu3_multihit_flush_offset + 1; + parameter iu3_parity_needs_flush_offset = iu3_data_parity_err_way_offset + 4; + parameter iu3_parity_tag_offset = iu3_parity_needs_flush_offset + 1; + parameter ici_val_offset = iu3_parity_tag_offset + 7; + parameter spr_ic_cls_offset = ici_val_offset + 1; + parameter spr_ic_idir_way_offset = spr_ic_cls_offset + 1; + parameter iu1_spr_idir_read_offset = spr_ic_idir_way_offset + 2; + parameter iu2_spr_idir_read_offset = iu1_spr_idir_read_offset + 1; + parameter iu2_spr_idir_lru_offset = iu2_spr_idir_read_offset + 1; + parameter stored_erat_rpn_offset = iu2_spr_idir_lru_offset + 3; + parameter stored_erat_wimge_offset = stored_erat_rpn_offset + (`REAL_IFAR_WIDTH - 12) * `THREADS; + parameter stored_erat_u_offset = stored_erat_wimge_offset + 5 * `THREADS; + parameter perf_instr_count_offset = stored_erat_u_offset + 4 * `THREADS; + parameter perf_t_event_offset = perf_instr_count_offset + 2 * `THREADS; + parameter perf_event_offset = perf_t_event_offset + 3 * `THREADS; + parameter pc_iu_inj_offset = perf_event_offset + 2; + parameter scan_right = pc_iu_inj_offset + 3 - 1; + + wire tidn; + wire tiup; + + // Latch inputs + // IU1 pipeline + wire iu1_valid_d; + wire iu1_valid_l2; + wire [0:`THREADS-1] iu1_tid_d; + wire [0:`THREADS-1] iu1_tid_l2; + wire [62-`EFF_IFAR_ARCH:61] iu1_ifar_d; + wire [62-`EFF_IFAR_ARCH:61] iu1_ifar_l2; + wire iu1_index51_d; + wire iu1_index51_l2; + wire iu1_inval_d; + wire iu1_inval_l2; + wire iu1_prefetch_d; + wire iu1_prefetch_l2; + wire iu1_read_erat_d; + wire iu1_read_erat_l2; + wire iu1_2ucode_d; + wire iu1_2ucode_l2; + wire iu1_2ucode_type_d; + wire iu1_2ucode_type_l2; + + // IU2 pipeline + wire iu2_valid_d; + wire iu2_valid_l2; + wire [0:`THREADS-1] iu2_tid_d; + wire [0:`THREADS-1] iu2_tid_l2; + wire [62-`EFF_IFAR_ARCH:61] iu2_ifar_eff_d; + wire [62-`EFF_IFAR_ARCH:61] iu2_ifar_eff_l2; + wire iu2_index51_d; + wire iu2_index51_l2; + wire iu2_2ucode_d; + wire iu2_2ucode_l2; + wire iu2_2ucode_type_d; + wire iu2_2ucode_type_l2; + wire iu2_inval_d; + wire iu2_inval_l2; + wire iu2_prefetch_d; + wire iu2_prefetch_l2; + wire iu2_read_erat_d; + wire iu2_read_erat_l2; + wire iu2_cam_change_etc_d; + wire iu2_cam_change_etc_l2; + reg [64-`REAL_IFAR_WIDTH:51] iu2_stored_rpn_d; + wire [64-`REAL_IFAR_WIDTH:51] iu2_stored_rpn_l2; + wire [0:3] iu2_dir_rd_val_d; + wire [0:3] iu2_dir_rd_val_l2; + wire [0:3] iu3_dir_parity_err_way_d; + wire [0:3] iu3_dir_parity_err_way_l2; + + // Dir val & LRU + wire [0:3] dir_val_d[0:127]; + wire [0:3] dir_val_l2[0:127]; + wire [0:2] dir_lru_d[0:127]; + wire [0:2] dir_lru_l2[0:127]; + + // IU3 pipeline + wire iu3_miss_flush_d; + wire iu3_miss_flush_l2; + wire [0:3] iu3_instr_valid_d; + wire [0:`THREADS-1] iu3_tid_d; + wire [0:`THREADS-1] iu3_tid_l2; + wire [62-`EFF_IFAR_WIDTH:61] iu3_ifar_d; + wire [62-`EFF_IFAR_WIDTH:61] iu3_ifar_l2; //20 + wire iu3_2ucode_d; + wire iu3_2ucode_l2; + wire iu3_2ucode_type_d; + wire iu3_2ucode_type_l2; + wire [0:2] iu3_erat_err_d; + wire [0:0] iu3_erat_err_l2; // Only latch 1 bit + wire [0:3] iu3_multihit_err_way_d; + wire [0:3] iu3_multihit_err_way_l2; + wire iu3_multihit_flush_d; + wire iu3_multihit_flush_l2; + wire [0:3] iu3_data_parity_err_way_d; + wire [0:3] iu3_data_parity_err_way_l2; + wire iu3_parity_needs_flush_d; + wire iu3_parity_needs_flush_l2; + wire [51:57] iu3_parity_tag_d; + wire [51:57] iu3_parity_tag_l2; + + // ICI + wire ici_val_d; + wire ici_val_l2; + + wire spr_ic_cls_d; + wire spr_ic_cls_l2; + wire [0:1] spr_ic_idir_way_d; + wire [0:1] spr_ic_idir_way_l2; + wire iu1_spr_idir_read_d; + wire iu1_spr_idir_read_l2; + wire iu2_spr_idir_read_d; + wire iu2_spr_idir_read_l2; + wire [0:2] iu2_spr_idir_lru_d; + wire [0:2] iu2_spr_idir_lru_l2; + + // IERAT Storing + wire [64-`REAL_IFAR_WIDTH:51] stored_erat_rpn_d[0:`THREADS-1]; + wire [64-`REAL_IFAR_WIDTH:51] stored_erat_rpn_l2[0:`THREADS-1]; + wire [0:4] stored_erat_wimge_d[0:`THREADS-1]; + wire [0:4] stored_erat_wimge_l2[0:`THREADS-1]; + wire [0:3] stored_erat_u_d[0:`THREADS-1]; + wire [0:3] stored_erat_u_l2[0:`THREADS-1]; + + wire [0:1] perf_instr_count_d[0:`THREADS-1]; + wire [0:1] perf_instr_count_l2[0:`THREADS-1]; + wire [9:11] perf_t_event_d[0:`THREADS-1]; + wire [9:11] perf_t_event_l2[0:`THREADS-1]; + wire [0:1] perf_event_d; + wire [0:1] perf_event_l2; + wire pc_iu_inj_icache_parity_l2; + wire pc_iu_inj_icachedir_parity_l2; + wire pc_iu_inj_icachedir_multihit_l2; + + // Stored IERAT + wire iu2_valid_erat_read; + wire [0:`THREADS-1] stored_erat_act; + wire iu1_stored_erat_updating; + reg [0:4] iu2_stored_wimge; + reg [0:3] iu2_stored_u; + wire [64-`REAL_IFAR_WIDTH:51] iu2_rpn; + wire [0:4] iu2_wimge; + wire [0:3] iu2_u; + wire [0:2] iu2_ierat_error; + + wire iu2_ci; + wire iu2_endian; + + // IDIR + wire dir_rd_act; + wire dir_write; + wire [0:ways-1] dir_way; + wire [0:6] dir_wr_addr; + wire [0:6] dir_rd_addr; + wire [0:dir_parity_width*8-1] ext_dir_datain; + wire [0:dir_parity_width-1] dir_parity_in; + wire [0:dir_way_width-1] way_datain; + wire [0:dir_way_width*ways-1] dir_datain; + wire [0:dir_way_width*ways-1] iu2_dir_dataout; + wire dir_dataout_act; + + wire [51:57] iu1_ifar_cacheline; + reg [0:3] dir_rd_val; + reg [0:2] iu1_spr_idir_lru; + + // IDATA + wire [0:1] data_read; + wire data_write; + wire [0:3] data_write_act; + wire [0:ways-1] data_way; + wire [0:8] data_addr; + wire [0:17] data_parity_in; + wire [0:161] data_datain; + wire [0:162*ways-1] data_dataout; + wire [0:162*ways-1] iu2_data_dataout; + + // Compare + wire [0:3] iu2_rd_tag_hit; + wire [0:3] iu2_rd_hit; + wire [0:3] iu2_rd_tag_hit_erat; + wire [0:3] iu2_rd_hit_erat; + wire [0:3] iu2_rd_tag_hit_stored; + wire [0:3] iu2_rd_hit_stored; + wire iu2_dir_miss; + wire iu2_wrong_ra; + wire iu2_cam_change_etc_flush; + wire [51:57] iu2_ifar_eff_cacheline; + wire [51:57] reload_cacheline; + wire [51:57] ecc_inval_cacheline; + wire [51:57] lru_write_cacheline; + wire [0:3] iu3_any_parity_err_way; + wire dir_val_act; + wire iu2_erat_err_lite; + wire iu2_lru_rd_update; + reg [0:2] dir_lru_read[0:127]; + reg [0:2] dir_lru_write[0:127]; + wire [0:15] dir_lru_act; + // Check multihit + wire iu2_multihit_err; + wire iu3_multihit_err; + wire iu2_pc_inj_icachedir_multihit; + + // Check parity + wire [0:dir_parity_width*8-1] ext_dir_dataout[0:3]; + wire [0:dir_parity_width-1] dir_parity_out[0:3]; + wire [0:dir_parity_width-1] dir_parity_err_byte[0:3]; + wire [0:dir_parity_width-1] gen_dir_parity_out[0:3]; + + wire [0:3] iu2_dir_parity_err_way; + wire iu2_rd_parity_err; + wire iu3_dir_parity_err; + + wire [0:17] data_parity_out[0:3]; + wire [0:17] data_parity_err_byte[0:3]; + wire [0:17] gen_data_parity_out[0:3]; + + wire data_parity_err; + + // Update Valid Bit + reg [0:2] return_lru; + reg [0:3] return_val; + + // IU2 + wire iu2_rd_miss; + wire iu2_valid_or_load; + wire [0:35] iu2_instr0_cache_rot[0:3]; // 4 ways + wire [0:35] iu2_instr1_cache_rot[0:3]; + wire [0:35] iu2_instr2_cache_rot[0:3]; + wire [0:35] iu2_instr3_cache_rot[0:3]; + wire [0:35] iu2_reload_rot[0:3]; // instructions 0-3 + wire [0:35] iu2_hit_rot[0:3]; + wire [0:35] iu2_instr[0:3]; + wire [0:3] iu2_uc_illegal_cache_rot; + wire iu2_uc_illegal_reload; + wire iu2_uc_illegal_cache; + wire iu2_uc_illegal; + + // performance events + wire [0:2] iu2_instr_count; + wire [0:2] perf_instr_count_new[0:`THREADS-1]; + + // abist + wire stage_abist_g8t_wenb; + wire stage_abist_g8t1p_renb_0; + wire [0:3] stage_abist_di_0; + wire stage_abist_g8t_bw_1; + wire stage_abist_g8t_bw_0; + wire [3:9] stage_abist_waddr_0; + wire [1:9] stage_abist_raddr_0; + wire stage_abist_wl128_comp_ena; + wire [0:3] stage_abist_g8t_dcomp; + wire [0:1] stage_abist_g6t_bw; + wire [0:3] stage_abist_di_g6t_2r; + wire stage_abist_wl512_comp_ena; + wire [0:3] stage_abist_dcomp_g6t_2r; + wire stage_abist_g6t_r_wb; + + // scan + wire [0:scan_right] siv; + wire [0:scan_right] sov; + wire [0:44] abst_siv; + wire [0:44] abst_sov; + wire [0:1] time_siv; + wire [0:1] time_sov; + wire [0:1] repr_siv; + wire [0:1] repr_sov; + + assign tidn = 1'b0; + assign tiup = 1'b1; + + assign spr_ic_cls_d = spr_ic_cls; + assign spr_ic_idir_way_d = spr_ic_idir_way; + + //--------------------------------------------------------------------- + // IU1 Latches + //--------------------------------------------------------------------- + assign iu1_valid_d = ics_icd_iu0_valid; + assign iu1_tid_d = ics_icd_iu0_tid; + assign iu1_ifar_d = ics_icd_iu0_ifar; + assign iu1_index51_d = ics_icd_iu0_index51; + assign iu1_inval_d = ics_icd_iu0_inval; + assign iu1_2ucode_d = ics_icd_iu0_2ucode; + assign iu1_2ucode_type_d = ics_icd_iu0_2ucode_type; + assign iu1_prefetch_d = ics_icd_iu0_prefetch; + assign iu1_read_erat_d = ics_icd_iu0_read_erat; + assign iu1_spr_idir_read_d = ics_icd_iu0_spr_idir_read; + + assign iu_ierat_iu1_back_inv = iu1_inval_l2; + + assign icd_ics_iu1_valid = iu1_valid_l2; + assign icd_ics_iu1_tid = iu1_tid_l2; + assign icd_ics_iu1_ifar = iu1_ifar_l2[62-`EFF_IFAR_WIDTH:61]; + assign icd_ics_iu1_2ucode = iu1_2ucode_l2; + assign icd_ics_iu1_2ucode_type = iu1_2ucode_type_l2; + + //--------------------------------------------------------------------- + // Stored IERAT + //--------------------------------------------------------------------- + // Keep copy of IERAT output so it is not necessary to read IERAT each time, for power savings + assign iu2_valid_erat_read = (iu2_valid_l2 | iu2_prefetch_l2) & iu2_read_erat_l2; + assign stored_erat_act = {`THREADS{iu2_valid_erat_read & (~spr_ic_ierat_byp_dis)}} & iu2_tid_l2; + assign iu1_stored_erat_updating = |(stored_erat_act & iu1_tid_l2); //'1' if stored erat is updating in IU2 for same thread that is in IU1 + + generate + begin : xhdl1 + genvar i; + for (i = 0; i < `THREADS; i = i + 1) + begin : erat_val_gen + assign stored_erat_rpn_d[i] = ierat_iu_iu2_rpn; + assign stored_erat_wimge_d[i] = ierat_iu_iu2_wimge; + assign stored_erat_u_d[i] = ierat_iu_iu2_u; + end + end + endgenerate + + //--------------------------------------------------------------------- + // ERAT Output + //--------------------------------------------------------------------- + // Need to mux between threads + // Need to mux between stored & non-stored + + //always @(iu2_tid_l2 or stored_erat_rpn_l2 or stored_erat_wimge_l2 or stored_erat_u_l2) + always @ (*) + begin: stored_erat_proc + reg [64-`REAL_IFAR_WIDTH:51] iu1_stored_rpn_calc; + reg [0:4] iu2_stored_wimge_calc; + reg [0:3] iu2_stored_u_calc; + //(* analysis_not_referenced="true" *) + integer i; + iu1_stored_rpn_calc = {`REAL_IFAR_WIDTH-12{1'b0}}; + iu2_stored_wimge_calc = 5'b0; + iu2_stored_u_calc = 4'b0; + + for (i = 0; i < `THREADS; i = i + 1) + begin + iu1_stored_rpn_calc = iu1_stored_rpn_calc | ({`REAL_IFAR_WIDTH-12{iu1_tid_l2[i]}} & stored_erat_rpn_l2[i]); + iu2_stored_wimge_calc = iu2_stored_wimge_calc | ({5{iu2_tid_l2[i]}} & stored_erat_wimge_l2[i]); + iu2_stored_u_calc = iu2_stored_u_calc | ({4{iu2_tid_l2[i]}} & stored_erat_u_l2[i]); + end + iu2_stored_rpn_d = iu1_stored_erat_updating ? ierat_iu_iu2_rpn : iu1_stored_rpn_calc; + iu2_stored_wimge = iu2_stored_wimge_calc; + iu2_stored_u = iu2_stored_u_calc; + end + + assign iu2_rpn = ((iu2_read_erat_l2 | iu2_inval_l2) == 1'b1) ? ierat_iu_iu2_rpn : + iu2_stored_rpn_l2; + + assign iu2_rd_tag_hit = ((iu2_read_erat_l2 | iu2_inval_l2) == 1'b1) ? iu2_rd_tag_hit_erat : + iu2_rd_tag_hit_stored; + + assign iu2_rd_hit = ((iu2_read_erat_l2 | iu2_inval_l2) == 1'b1) ? iu2_rd_hit_erat : + iu2_rd_hit_stored; + + assign iu2_wimge = ((iu2_read_erat_l2 | iu2_inval_l2) == 1'b1) ? ierat_iu_iu2_wimge : + iu2_stored_wimge; + + assign iu2_u = ((iu2_read_erat_l2 | iu2_inval_l2) == 1'b1) ? ierat_iu_iu2_u : + iu2_stored_u; + + assign iu2_ierat_error = {3{iu2_read_erat_l2}} & ierat_iu_iu2_error; + + assign iu2_ci = iu2_wimge[1]; // Note: Must check iu2_valid everywhere this is used. Otherwise, set to 0 if iu2_inval_l2 + assign iu2_endian = iu2_wimge[4]; + + // Timing: Moved muxing to ierat, since similar mux exists there + + assign iu2_ifar_eff_d = iu1_ifar_l2; + assign iu2_index51_d = iu1_index51_l2; + + //--------------------------------------------------------------------- + // Access IDIR, Valid, & LRU + //--------------------------------------------------------------------- + assign dir_rd_act = ics_icd_dir_rd_act; + assign dir_write = icm_icd_dir_write; + assign dir_way = icm_icd_dir_write_way; + assign dir_wr_addr = {icm_icd_dir_write_addr[51:56], (icm_icd_dir_write_addr[57] & (~spr_ic_cls_l2))}; // Use even row for 128B mode + assign dir_rd_addr = {ics_icd_iu0_index51, ics_icd_iu0_ifar[52:56], (ics_icd_iu0_ifar[57] & (~(spr_ic_cls_l2 & (~ics_icd_iu0_spr_idir_read))))}; + + generate + begin : xhdl2 + genvar i; + for (i = 0; i < dir_parity_width*8; i = i + 1) + begin : calc_ext_dir_data + if (i < 51 - (64 - `REAL_IFAR_WIDTH)) + assign ext_dir_datain[i] = icm_icd_dir_write_addr[(64 - `REAL_IFAR_WIDTH) + i]; + if (i == 51 - (64 - `REAL_IFAR_WIDTH)) + assign ext_dir_datain[i] = icm_icd_dir_write_endian; + if (i > 51 - (64 - `REAL_IFAR_WIDTH)) + assign ext_dir_datain[i] = 1'b0; + end + + //genvar i; + for (i = 0; i < dir_parity_width; i = i + 1) + begin : gen_dir_parity + assign dir_parity_in[i] = ^(ext_dir_datain[i * 8:i * 8 + 7]); + end + end + endgenerate + + assign way_datain[0:50 - (64 - `REAL_IFAR_WIDTH)] = icm_icd_dir_write_addr[(64 - `REAL_IFAR_WIDTH):50]; + assign way_datain[51 - (64 - `REAL_IFAR_WIDTH)] = icm_icd_dir_write_endian; + assign way_datain[52 - (64 - `REAL_IFAR_WIDTH):52 - (64 - `REAL_IFAR_WIDTH) + dir_parity_width - 1] = dir_parity_in; + generate + if (52 - (64 - `REAL_IFAR_WIDTH) + dir_parity_width < dir_way_width) + assign way_datain[52 - (64 - `REAL_IFAR_WIDTH) + dir_parity_width:dir_way_width-1] = {dir_way_width-52+64-`REAL_IFAR_WIDTH-dir_parity_width{1'b0}}; + endgenerate + + assign dir_datain = {way_datain, way_datain, way_datain, way_datain}; + + // 0:28 - tag, 29 - endianness, 30:33 - parity + tri_128x34_4w_1r1w idir( + .gnd(gnd), + .vdd(vdd), + .vcs(vdd), + .nclk(nclk), + .rd_act(dir_rd_act), + .wr_act(dir_write), + .sg_0(pc_iu_sg_0), + .abst_sl_thold_0(pc_iu_abst_slp_sl_thold_0), + .ary_nsl_thold_0(pc_iu_ary_slp_nsl_thold_0), + .time_sl_thold_0(pc_iu_time_sl_thold_0), + .repr_sl_thold_0(pc_iu_repr_sl_thold_0), + .func_sl_thold_0_b(pc_iu_func_slp_sl_thold_0_b), + .func_force(funcslp_force), + .clkoff_dc_b(g8t_clkoff_b), + .ccflush_dc(tc_ac_ccflush_dc), + .scan_dis_dc_b(tc_ac_scan_dis_dc_b), + .scan_diag_dc(tc_ac_scan_diag_dc), + .d_mode_dc(g8t_d_mode), + .mpw1_dc_b(g8t_mpw1_b), + .mpw2_dc_b(g8t_mpw2_b), + .delay_lclkr_dc(g8t_delay_lclkr), + .wr_abst_act(stage_abist_g8t_wenb), + .rd0_abst_act(stage_abist_g8t1p_renb_0), + .abist_di(stage_abist_di_0), + .abist_bw_odd(stage_abist_g8t_bw_1), + .abist_bw_even(stage_abist_g8t_bw_0), + .abist_wr_adr(stage_abist_waddr_0[3:9]), + .abist_rd0_adr(stage_abist_raddr_0[3:9]), + .tc_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc), + .abist_ena_1(pc_iu_abist_ena_dc), + .abist_g8t_rd0_comp_ena(stage_abist_wl128_comp_ena), + .abist_raw_dc_b(pc_iu_abist_raw_dc_b), + .obs0_abist_cmp(stage_abist_g8t_dcomp), + .abst_scan_in({abst_siv[0], abst_siv[2]}), + .time_scan_in(time_siv[0]), + .repr_scan_in(repr_siv[0]), + .func_scan_in(siv[iu2_dir_dataout_offset]), + .abst_scan_out({abst_sov[0], abst_sov[2]}), + .time_scan_out(time_sov[0]), + .repr_scan_out(repr_sov[0]), + .func_scan_out(sov[iu2_dir_dataout_offset]), + .lcb_bolt_sl_thold_0(pc_iu_bolt_sl_thold_0), + .pc_bo_enable_2(pc_iu_bo_enable_2), + .pc_bo_reset(pc_iu_bo_reset), + .pc_bo_unload(pc_iu_bo_unload), + .pc_bo_repair(pc_iu_bo_repair), + .pc_bo_shdata(pc_iu_bo_shdata), + .pc_bo_select(pc_iu_bo_select[0:1]), + .bo_pc_failout(iu_pc_bo_fail[0:1]), + .bo_pc_diagloop(iu_pc_bo_diagout[0:1]), + .tri_lcb_mpw1_dc_b(mpw1_b), + .tri_lcb_mpw2_dc_b(mpw2_b), + .tri_lcb_delay_lclkr_dc(delay_lclkr), + .tri_lcb_clkoff_dc_b(clkoff_b), + .tri_lcb_act_dis_dc(act_dis), + .wr_way(dir_way), + .wr_addr(dir_wr_addr), + .data_in(dir_datain), + .rd_addr(dir_rd_addr), + .data_out(iu2_dir_dataout) + ); + + assign dir_dataout_act = iu1_valid_l2 | iu1_inval_l2 | iu1_spr_idir_read_l2 | iu1_prefetch_l2; + + // Muxing the val for directory access + assign iu1_ifar_cacheline = {iu1_index51_l2, iu1_ifar_l2[52:56], + (iu1_ifar_l2[57] & (~(spr_ic_cls_l2 & (~iu1_spr_idir_read_l2))))}; + + + //always @(iu1_ifar_cacheline or dir_val_l2) + always @(*) + begin: dir_rd_val_proc + //(* analysis_not_referenced="true" *) + integer i; + dir_rd_val = 4'b0000; + for (i = 0; i < 128; i = i + 1) + if (iu1_ifar_cacheline == i[6:0]) + dir_rd_val = dir_val_l2[i]; + end + + assign iu2_dir_rd_val_d = dir_rd_val; + + assign ic_spr_idir_valid = (spr_ic_idir_way_l2 == 2'b00) ? iu2_dir_rd_val_l2[0] : + (spr_ic_idir_way_l2 == 2'b01) ? iu2_dir_rd_val_l2[1] : + (spr_ic_idir_way_l2 == 2'b10) ? iu2_dir_rd_val_l2[2] : + iu2_dir_rd_val_l2[3]; + + //always @(iu1_index51_l2 or iu1_ifar_l2 or dir_lru_l2) + always @ (*) + begin: iu2_spr_idir_lru_proc + //(* analysis_not_referenced="true" *) + integer i; + iu1_spr_idir_lru = 3'b000; + for (i = 0; i < 128; i = i + 1) + if ({iu1_index51_l2, iu1_ifar_l2[52:57]} == i[6:0]) + iu1_spr_idir_lru = dir_lru_l2[i]; + end + + assign iu2_spr_idir_lru_d = {3{iu1_spr_idir_read_l2}} & iu1_spr_idir_lru; // gate to reduce switching/power + + assign ic_spr_idir_lru = iu2_spr_idir_lru_l2; + + assign ic_spr_idir_tag = (spr_ic_idir_way_l2 == 2'b00) ? iu2_dir_dataout[0:28] : + (spr_ic_idir_way_l2 == 2'b01) ? iu2_dir_dataout[ dir_way_width: dir_way_width + 28] : + (spr_ic_idir_way_l2 == 2'b10) ? iu2_dir_dataout[2 * dir_way_width:2 * dir_way_width + 28] : + iu2_dir_dataout[3 * dir_way_width:3 * dir_way_width + 28]; + + assign ic_spr_idir_endian = (spr_ic_idir_way_l2 == 2'b00) ? iu2_dir_dataout[29] : + (spr_ic_idir_way_l2 == 2'b01) ? iu2_dir_dataout[ dir_way_width + 29] : + (spr_ic_idir_way_l2 == 2'b10) ? iu2_dir_dataout[2 * dir_way_width + 29] : + iu2_dir_dataout[3 * dir_way_width + 29]; + + assign ic_spr_idir_parity = (spr_ic_idir_way_l2 == 2'b00) ? iu2_dir_dataout[30:33] : + (spr_ic_idir_way_l2 == 2'b01) ? iu2_dir_dataout[ dir_way_width + 30:2 * dir_way_width - 1] : + (spr_ic_idir_way_l2 == 2'b10) ? iu2_dir_dataout[2 * dir_way_width + 30:3 * dir_way_width - 1] : + iu2_dir_dataout[3 * dir_way_width + 30:4 * dir_way_width - 1]; + assign ic_spr_idir_done = iu2_spr_idir_read_l2; + + //--------------------------------------------------------------------- + // Access IData + //--------------------------------------------------------------------- + assign data_read = ics_icd_data_rd_act; + assign data_write = icm_icd_data_write; + assign data_way = icm_icd_reload_way; // write + + assign data_addr = (data_write == 1'b1) ? icm_icd_reload_addr[51:59] : + {ics_icd_iu0_index51, ics_icd_iu0_ifar[52:59]}; + + assign data_write_act[0] = (data_way[0] | data_way[1]) & (~icm_icd_reload_addr[51]); + assign data_write_act[1] = (data_way[2] | data_way[3]) & (~icm_icd_reload_addr[51]); + assign data_write_act[2] = (data_way[0] | data_way[1]) & icm_icd_reload_addr[51]; + assign data_write_act[3] = (data_way[2] | data_way[3]) & icm_icd_reload_addr[51]; + + generate + begin : xhdl4 + genvar i; + for (i = 0; i < 18; i = i + 1) + begin : gen_data_parity + assign data_parity_in[i] = ^(icm_icd_reload_data[i * 8:i * 8 + 7]); + end + end + endgenerate + + assign data_datain = {icm_icd_reload_data, data_parity_in}; + + + + tri_512x162_4w_0 idata( + .gnd(gnd), + .vdd(vdd), + .vcs(vdd), + .nclk(nclk), + .ccflush_dc(tc_ac_ccflush_dc), + .lcb_clkoff_dc_b(g6t_clkoff_b), + .lcb_d_mode_dc(g6t_d_mode), + .lcb_act_dis_dc(g6t_act_dis), + .lcb_ary_nsl_thold_0(pc_iu_ary_nsl_thold_0), + .lcb_sg_1(pc_iu_sg_1), + .lcb_abst_sl_thold_0(pc_iu_abst_sl_thold_0), + .lcb_func_sl_thold_0_b(pc_iu_func_sl_thold_0_b), + .func_force(force_t), + .scan_diag_dc(tc_ac_scan_diag_dc), + .scan_dis_dc_b(tc_ac_scan_dis_dc_b), + .func_scan_in(siv[iu2_data_dataout_offset]), + .func_scan_out(sov[iu2_data_dataout_offset]), + .abst_scan_in({abst_siv[1], abst_siv[3]}), + .abst_scan_out({abst_sov[1], abst_sov[3]}), + .lcb_delay_lclkr_np_dc(g6t_delay_lclkr[0]), + .ctrl_lcb_delay_lclkr_np_dc(g6t_delay_lclkr[1]), + .dibw_lcb_delay_lclkr_np_dc(g6t_delay_lclkr[2]), + .ctrl_lcb_mpw1_np_dc_b(g6t_mpw1_b[0]), + .dibw_lcb_mpw1_np_dc_b(g6t_mpw1_b[1]), + .lcb_mpw1_pp_dc_b(g6t_mpw1_b[2]), + .lcb_mpw1_2_pp_dc_b(g6t_mpw1_b[3]), + .aodo_lcb_delay_lclkr_dc(g6t_delay_lclkr[3]), + .aodo_lcb_mpw1_dc_b(g6t_mpw1_b[4]), + .aodo_lcb_mpw2_dc_b(g6t_mpw2_b), + .lcb_time_sg_0(pc_iu_sg_0), + .lcb_time_sl_thold_0(pc_iu_time_sl_thold_0), + .time_scan_in(time_siv[1]), + .time_scan_out(time_sov[1]), + .bitw_abist(stage_abist_g6t_bw), + .lcb_repr_sl_thold_0(pc_iu_repr_sl_thold_0), + .lcb_repr_sg_0(pc_iu_sg_0), + .repr_scan_in(repr_siv[1]), + .repr_scan_out(repr_sov[1]), + .tc_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc), + .abist_en_1(pc_iu_abist_ena_dc), + .din_abist(stage_abist_di_g6t_2r), + .abist_cmp_en(stage_abist_wl512_comp_ena), + .abist_raw_b_dc(pc_iu_abist_raw_dc_b), + .data_cmp_abist(stage_abist_dcomp_g6t_2r), + .addr_abist(stage_abist_raddr_0[1:9]), + .r_wb_abist(stage_abist_g6t_r_wb), + .write_thru_en_dc(tidn), + .lcb_bolt_sl_thold_0(pc_iu_bolt_sl_thold_0), + .pc_bo_enable_2(pc_iu_bo_enable_2), + .pc_bo_reset(pc_iu_bo_reset), + .pc_bo_unload(pc_iu_bo_unload), + .pc_bo_repair(pc_iu_bo_repair), + .pc_bo_shdata(pc_iu_bo_shdata), + .pc_bo_select(pc_iu_bo_select[2:3]), + .bo_pc_failout(iu_pc_bo_fail[2:3]), + .bo_pc_diagloop(iu_pc_bo_diagout[2:3]), + .tri_lcb_mpw1_dc_b(mpw1_b), + .tri_lcb_mpw2_dc_b(mpw2_b), + .tri_lcb_delay_lclkr_dc(delay_lclkr), + .tri_lcb_clkoff_dc_b(clkoff_b), + .tri_lcb_act_dis_dc(act_dis), + .read_act(data_read), + .write_act(data_write_act), + .write_enable(data_write), + .write_way(data_way), + .addr(data_addr), + .data_in(data_datain), + .data_out(data_dataout) + ); + + assign iu2_data_dataout[0] = data_dataout[0] ^ pc_iu_inj_icache_parity_l2; + assign iu2_data_dataout[1:162*ways-1] = data_dataout[1:162*ways-1]; + + //--------------------------------------------------------------------- + // Compare Tag + //--------------------------------------------------------------------- + generate + begin : xhdl5 + genvar i; + for (i = 0; i < 4; i = i + 1) + begin : rd_tag_hit0 + assign iu2_rd_tag_hit_erat[i] = ierat_iu_iu2_rpn[(64 - `REAL_IFAR_WIDTH):50] == iu2_dir_dataout[i * dir_way_width:i * dir_way_width + 50 - (64 - `REAL_IFAR_WIDTH)]; + + assign iu2_rd_hit_erat[i] = iu2_dir_rd_val_l2[i] & iu2_rd_tag_hit_erat[i] & (ierat_iu_iu2_rpn[51] == iu2_index51_l2) & (iu2_endian == iu2_dir_dataout[i * dir_way_width + 51 - (64 - `REAL_IFAR_WIDTH)]); + + assign iu2_rd_tag_hit_stored[i] = iu2_stored_rpn_l2[(64 - `REAL_IFAR_WIDTH):50] == iu2_dir_dataout[i * dir_way_width:i * dir_way_width + 50 - (64 - `REAL_IFAR_WIDTH)]; + + assign iu2_rd_hit_stored[i] = iu2_dir_rd_val_l2[i] & iu2_rd_tag_hit_stored[i] & (iu2_stored_rpn_l2[51] == iu2_index51_l2) & (iu2_endian == iu2_dir_dataout[i * dir_way_width + 51 - (64 - `REAL_IFAR_WIDTH)]); + end + end + endgenerate + + + assign iu2_dir_miss = (~|(iu2_rd_hit)); + + assign iu2_wrong_ra = (iu2_rpn[51] != iu2_index51_l2) & (~iu2_ierat_error[0]) & (~iu2_cam_change_etc_flush); + assign icd_ics_iu2_wrong_ra_flush = {`THREADS{iu2_valid_l2 & iu2_wrong_ra}} & iu2_tid_l2; + + // Cam change is IU1 phase. Need to flush if cam changes and we didn't read erat. + // Latch IU1 flushes and do flush in IU2 (less muxing for IU0 ifar). Flush if cam changes & didn't read erat + assign iu2_cam_change_etc_d = (ierat_iu_cam_change & (~iu1_read_erat_l2)) | + (ierat_iu_iu2_error[0] & iu2_valid_erat_read & (~iu1_read_erat_l2) & (iu1_tid_l2 == iu2_tid_l2)) | // Flush next command (IU1) if IU2 error + (|(ierat_iu_iu2_flush_req & iu1_tid_l2) & (iu1_tid_l2 == iu2_tid_l2)); // Flush next command (IU1) if ierat flush and iu2_prefetch, in order to get the correct iu0_ifar + + assign iu2_cam_change_etc_flush = iu2_cam_change_etc_l2 & (iu2_valid_l2 | iu2_prefetch_l2); + assign icd_ics_iu2_cam_etc_flush = {`THREADS{iu2_cam_change_etc_flush}} & iu2_tid_l2; + + assign iu2_valid_d = iu1_valid_l2 & (|(iu1_tid_l2 & (~ics_icd_iu1_flush))); + + assign iu2_tid_d = iu1_tid_l2; + + assign iu2_2ucode_d = iu1_2ucode_l2; + assign iu2_2ucode_type_d = iu1_2ucode_type_l2; + + assign iu2_inval_d = iu1_inval_l2; + + assign iu2_prefetch_d = iu1_prefetch_l2 & (|(iu1_tid_l2 & (~ics_icd_iu1_flush))); + + assign iu2_read_erat_d = iu1_read_erat_l2; + + assign iu2_spr_idir_read_d = iu1_spr_idir_read_l2; + + assign icd_ics_iu1_read_erat = {`THREADS{(iu1_valid_l2 | iu1_prefetch_l2) & iu1_read_erat_l2}} & iu1_tid_l2; + assign icd_ics_iu2_read_erat_error = {`THREADS{(iu2_valid_l2 | iu2_prefetch_l2) & iu2_read_erat_l2 & ierat_iu_iu2_error[0]}} & iu2_tid_l2; + + //--------------------------------------------------------------------- + // Check Multihit + //--------------------------------------------------------------------- + // Set if more than 1 way matches (not 0000, 0001, 0010, 0100, 1000) + assign iu2_multihit_err = (iu2_valid_l2 | iu2_inval_l2 | iu2_spr_idir_read_l2 | iu2_prefetch_l2) & // Don't want to set error if array not read this cycle + (~((iu2_rd_hit[0:2] == 3'b000) | + (({iu2_rd_hit[0:1], iu2_rd_hit[3]}) == 3'b000) | + (({iu2_rd_hit[0], iu2_rd_hit[2:3]}) == 3'b000) | + (iu2_rd_hit[1:3] == 3'b000))); + + assign iu2_pc_inj_icachedir_multihit = (iu2_valid_l2 | iu2_inval_l2 | iu2_spr_idir_read_l2 | iu2_prefetch_l2) & pc_iu_inj_icachedir_multihit_l2 & (~iu2_dir_miss); + + assign iu3_multihit_err_way_d = ({4{iu2_multihit_err}} & iu2_rd_hit) | + {4{iu2_pc_inj_icachedir_multihit}}; + + assign iu3_multihit_err = |(iu3_multihit_err_way_l2); + + assign iu3_multihit_flush_d = (iu2_multihit_err | (pc_iu_inj_icachedir_multihit_l2 & (~iu2_dir_miss))) & (iu2_valid_l2 & (|(iu2_tid_l2 & (~ics_icd_iu2_flush))) & (~iu2_ci)); + + tri_direct_err_rpt #(.WIDTH(1)) err_icachedir_multihit( + .vd(vdd), + .gd(gnd), + .err_in(iu3_multihit_err), + .err_out(iu_pc_err_icachedir_multihit) + ); + + //--------------------------------------------------------------------- + // Check Parity + //--------------------------------------------------------------------- + // Dir + generate + begin : xhdl9 + genvar w; + for (w = 0; w < 4; w = w + 1) + begin : calc_ext_dir_0 + genvar i; + for (i = 0; i < dir_parity_width*8; i = i + 1) + begin : calc_ext_dir_dataout0 + if (i < 52 - (64 - `REAL_IFAR_WIDTH)) + assign ext_dir_dataout[w][i] = iu2_dir_dataout[i + w * dir_way_width]; + if (i >= 52 - (64 - `REAL_IFAR_WIDTH)) + assign ext_dir_dataout[w][i] = 1'b0; + end + + assign dir_parity_out[w] = iu2_dir_dataout[w * dir_way_width + 52 - (64 - `REAL_IFAR_WIDTH):w * dir_way_width + 52 - (64 - `REAL_IFAR_WIDTH) + dir_parity_width - 1]; + + //genvar i; + for (i = 0; i < dir_parity_width; i = i + 1) + begin : chk_dir_parity + assign gen_dir_parity_out[w][i] = ^(ext_dir_dataout[w][i * 8:i * 8 + 7]) ^ pc_iu_inj_icachedir_parity_l2; + end + + assign dir_parity_err_byte[w] = dir_parity_out[w] ^ gen_dir_parity_out[w]; + + assign iu2_dir_parity_err_way[w] = (|(dir_parity_err_byte[w])) & iu2_dir_rd_val_l2[w] & (iu2_valid_l2 | iu2_inval_l2 | iu2_spr_idir_read_l2 | iu2_prefetch_l2); // Don't want to set error if array not read this cycle + end + end + endgenerate + + assign iu2_rd_parity_err = |(iu2_dir_parity_err_way & iu2_rd_hit); + + assign iu3_dir_parity_err_way_d = iu2_dir_parity_err_way; + + assign iu3_dir_parity_err = |(iu3_dir_parity_err_way_l2); + + + tri_direct_err_rpt #(.WIDTH(1)) err_icachedir_parity( + .vd(vdd), + .gd(gnd), + .err_in(iu3_dir_parity_err), + .err_out(iu_pc_err_icachedir_parity) + ); + + //Data + generate + begin : xhdl11 + genvar w; + for (w = 0; w < 4; w = w + 1) + begin : data_parity_out_gen + assign data_parity_out[w] = iu2_data_dataout[w * 162 + 144:w * 162 + 144 + 18 - 1]; + + genvar i; + for (i = 0; i < 18; i = i + 1) + begin : chk_data_parity + assign gen_data_parity_out[w][i] = ^(iu2_data_dataout[w * 162 + i * 8:w * 162 + i * 8 + 7]); + end + + assign data_parity_err_byte[w] = data_parity_out[w] ^ gen_data_parity_out[w]; + + assign iu3_data_parity_err_way_d[w] = (|(data_parity_err_byte[w])) & iu2_dir_rd_val_l2[w] & iu2_valid_l2; + end + end + endgenerate + + assign data_parity_err = |(iu3_data_parity_err_way_l2); + + + tri_direct_err_rpt #(.WIDTH(1)) err_icache_parity( + .vd(vdd), + .gd(gnd), + .err_in(data_parity_err), + .err_out(iu_pc_err_icache_parity) + ); + + assign iu3_parity_needs_flush_d = iu2_valid_l2 & (|(iu2_tid_l2 & (~ics_icd_iu2_flush))) & (~iu2_rd_miss) & (|(iu3_data_parity_err_way_d & iu2_rd_hit)); + assign icd_ics_iu3_parity_flush = {`THREADS{iu3_parity_needs_flush_l2 | iu3_multihit_flush_l2}} & iu3_tid_l2; + + assign iu3_parity_tag_d = {iu2_index51_l2, iu2_ifar_eff_l2[52:56], (iu2_ifar_eff_l2[57] & (~(spr_ic_cls_l2 & (~iu2_spr_idir_read_l2))))}; + + //--------------------------------------------------------------------- + // Update LRU + //--------------------------------------------------------------------- + // For 128B cacheline mode, use even dir rows + assign iu2_ifar_eff_cacheline = {iu2_index51_l2, iu2_ifar_eff_l2[52:56], (iu2_ifar_eff_l2[57] & (~(spr_ic_cls_l2 & (~iu2_spr_idir_read_l2))))}; + assign reload_cacheline = {icm_icd_reload_addr[51:56], (icm_icd_reload_addr[57] & (~spr_ic_cls_l2))}; + assign ecc_inval_cacheline = {icm_icd_ecc_addr[51:56], (icm_icd_ecc_addr[57] & (~spr_ic_cls_l2))}; + assign lru_write_cacheline = {icm_icd_lru_write_addr[51:56], (icm_icd_lru_write_addr[57] & (~spr_ic_cls_l2))}; + + assign iu3_any_parity_err_way = iu3_multihit_err_way_l2 | iu3_dir_parity_err_way_l2 | iu3_data_parity_err_way_l2; + + // ICI Latches + assign ici_val_d = lq_iu_ici_val; + + // update LRU in IU2 on read hit or dir_write + generate + begin : xhdl12 + genvar a; + for (a = 0; a < 128; a = a + 1) + begin : dir_lru_gen + wire [0:6] index_v7 = a; + assign dir_lru_d[a] = (icm_icd_lru_write == 1'b0) ? dir_lru_read[a] : + dir_lru_write[a]; + + //always @(dir_lru_l2 or iu2_lru_rd_update or iu2_ifar_eff_cacheline or iu2_way_select_no_par_err or icm_icd_lru_write or lru_write_cacheline or icm_icd_lru_write_way) + always @ (*) + begin: lru_proc + dir_lru_read[a] = dir_lru_l2[a]; + dir_lru_write[a] = dir_lru_l2[a]; + if (iu2_lru_rd_update == 1'b1 & (iu2_ifar_eff_cacheline == index_v7)) + dir_lru_read[a] = ({3{iu2_rd_hit[0]}} & {2'b11, dir_lru_l2[a][2]}) | + ({3{iu2_rd_hit[1]}} & {2'b10, dir_lru_l2[a][2]}) | + ({3{iu2_rd_hit[2]}} & {1'b0, dir_lru_l2[a][1], 1'b1}) | + ({3{iu2_rd_hit[3]}} & {1'b0, dir_lru_l2[a][1], 1'b0}); + if (icm_icd_lru_write == 1'b1 & (lru_write_cacheline == index_v7)) + dir_lru_write[a] = ({3{icm_icd_lru_write_way[0]}} & {2'b11, dir_lru_l2[a][2]}) | + ({3{icm_icd_lru_write_way[1]}} & {2'b10, dir_lru_l2[a][2]}) | + ({3{icm_icd_lru_write_way[2]}} & {1'b0, dir_lru_l2[a][1], 1'b1}) | + ({3{icm_icd_lru_write_way[3]}} & {1'b0, dir_lru_l2[a][1], 1'b0}); + end + + //--------------------------------------------------------------------- + // Update Valid Bits + //--------------------------------------------------------------------- + + assign dir_val_d[a] = + ((dir_val_l2[a] & + (~({4{iu3_parity_tag_l2[51:57] == index_v7}} & iu3_any_parity_err_way))) | // clear on dir parity, data parity, or multihit error + ({4{icm_icd_dir_val & (reload_cacheline[51:57] == index_v7)}} & icm_icd_reload_way)) & // set when writing to this entry + (~({4{icm_icd_dir_inval & (reload_cacheline[51:57] == index_v7)}} & icm_icd_reload_way)) & // clear when invalidating way for new reload + (~({4{icm_icd_ecc_inval & (ecc_inval_cacheline[51:57] == index_v7)}} & icm_icd_ecc_way)) & // clear when bad ecc on data written last cycle + (~(({4{iu2_inval_l2 & (iu2_ifar_eff_cacheline[51:57] == index_v7)}} & dir_val_l2[a]) & iu2_rd_tag_hit)) & // clear on back_invalidate + (~({4{ici_val_l2}})); // clear on ICI + end + end + endgenerate + + generate + begin : xhdl13 + genvar a; + for (a = 0; a < 16; a = a + 1) + begin : dir_lru_act_gen + wire [0:3] index_v4 = a; + assign dir_lru_act[a] = (icm_icd_lru_write & (lru_write_cacheline[51:54] == index_v4)) | + (iu2_valid_l2 & (iu2_ifar_eff_cacheline[51:54] == index_v4)); + end + end + endgenerate + + assign dir_val_act = ici_val_l2 | (|(iu3_any_parity_err_way)) | icm_icd_any_reld_r2 | icm_icd_ecc_inval | iu2_inval_l2; + + // All erat errors except for erat parity error, for timing + assign iu2_erat_err_lite = (ierat_iu_iu2_miss | ierat_iu_iu2_multihit | ierat_iu_iu2_isi) & iu2_read_erat_l2; + + // Note: if timing is bad, can remove parity err check + assign iu2_lru_rd_update = iu2_valid_l2 & (~iu2_erat_err_lite) & (|(iu2_rd_hit)) & (~iu2_rd_parity_err) & (~iu2_multihit_err) & (~pc_iu_inj_icachedir_multihit_l2); + + // ic miss latches the location for data write to prevent data from moving around in Data cache + + //always @(icm_icd_lru_addr or dir_lru_l2) + always @ (*) + begin: return_lru_proc + //(* analysis_not_referenced="true" *) + integer i; + return_lru = 3'b000; + for (i = 0; i < 128; i = i + 1) + if (icm_icd_lru_addr[51:57] == i[6:0]) + return_lru = dir_lru_l2[i]; + end + + assign icd_icm_row_lru = return_lru; + + + //always @(icm_icd_lru_addr or dir_val_l2) + always @ (*) + begin: return_val_proc + //(* analysis_not_referenced="true" *) + integer i; + return_val = 4'b0000; + for (i = 0; i < 128; i = i + 1) + if (icm_icd_lru_addr[51:57] == i[6:0]) + return_val = dir_val_l2[i]; + end + + assign icd_icm_row_val = return_val; + + //--------------------------------------------------------------------- + // IU2 + //--------------------------------------------------------------------- + // IU2 Output + generate + begin : xhdl14 + genvar i; + for (i = 0; i < 52; i = i + 1) + begin : mm_epn + if (i < (62 - `EFF_IFAR_ARCH)) + assign iu_mm_ierat_epn[i] = 1'b0; + if (i >= (62 - `EFF_IFAR_ARCH)) + assign iu_mm_ierat_epn[i] = iu2_ifar_eff_l2[i]; + end + end + endgenerate + + // Handle Miss + assign iu2_rd_miss = (iu2_valid_l2 | iu2_prefetch_l2) & (~|(ierat_iu_iu2_flush_req)) & + (iu2_dir_miss | iu2_ci | iu2_rd_parity_err) & + (~iu2_ierat_error[0]) & (~iu2_cam_change_etc_flush) & (~iu2_wrong_ra) & + (~(iu3_miss_flush_l2 & |(iu3_tid_l2 & iu2_tid_l2))); + assign iu3_miss_flush_d = iu2_rd_miss & (~iu2_prefetch_l2) & (|(iu2_tid_l2 & (~ics_icd_iu2_flush))); + assign icd_icm_miss = iu2_rd_miss; + assign icd_icm_prefetch = iu2_prefetch_l2; + assign icd_icm_tid = iu2_tid_l2; + assign icd_icm_addr_real = {iu2_rpn[64 - `REAL_IFAR_WIDTH:51], iu2_ifar_eff_l2[52:61]}; // ???? Could use iu2_index51 + assign icd_icm_addr_eff = iu2_ifar_eff_l2[62 - `EFF_IFAR_WIDTH:51]; + assign icd_icm_wimge = iu2_wimge; + assign icd_icm_userdef = iu2_u; + assign icd_icm_2ucode = iu2_2ucode_l2; + assign icd_icm_2ucode_type = iu2_2ucode_type_l2; + assign icd_icm_iu2_inval = iu2_inval_l2; + assign icd_icm_any_iu2_valid = iu2_valid_l2 | iu2_prefetch_l2; // for act's in ic_miss + + assign icd_ics_iu3_miss_flush = {`THREADS{iu3_miss_flush_l2}} & iu3_tid_l2 ; + assign icd_ics_iu2_ifar_eff = iu2_ifar_eff_l2[62 - `EFF_IFAR_WIDTH:61]; + assign icd_ics_iu2_2ucode = iu2_2ucode_l2; + assign icd_ics_iu2_2ucode_type = iu2_2ucode_type_l2; + assign icd_ics_iu2_valid = iu2_valid_l2; + + // Moved flushes to ic_bp_iu2_flush + // Note: iu2_valid_l2 and icm_icd_load must never be on at same time + assign iu2_valid_or_load = iu2_valid_l2 | (|(icm_icd_load)); + + assign iu3_instr_valid_d[0:3] = ({iu2_valid_or_load, iu3_ifar_d[60:61]} == 3'b100) ? 4'b1111 : + ({iu2_valid_or_load, iu3_ifar_d[60:61]} == 3'b101) ? 4'b1110 : + ({iu2_valid_or_load, iu3_ifar_d[60:61]} == 3'b110) ? 4'b1100 : + ({iu2_valid_or_load, iu3_ifar_d[60:61]} == 3'b111) ? 4'b1000 : + 4'b0000; + + assign iu3_tid_d = (iu2_valid_l2 == 1'b1) ? iu2_tid_l2 : + icm_icd_load; + + assign iu3_ifar_d = (iu2_valid_l2 == 1'b1) ? iu2_ifar_eff_l2[62 - `EFF_IFAR_WIDTH:61] : + icm_icd_load_addr; + + assign iu3_2ucode_d = (iu2_valid_l2 == 1'b1) ? iu2_2ucode_l2 : + icm_icd_load_2ucode; + + assign iu3_2ucode_type_d = (iu2_valid_l2 == 1'b1) ? iu2_2ucode_type_l2 : + icm_icd_load_2ucode_type; + + assign iu3_erat_err_d = iu2_ierat_error[0:2] & {3{iu2_valid_l2}}; + + // Rotate instructions + generate + begin : xhdl15 + genvar w; + for (w = 0; w < 4; w = w + 1) + begin : iu2_instr_rot0 + assign iu2_instr0_cache_rot[w] = + (iu2_ifar_eff_l2[60:61] == 2'b00) ? iu2_data_dataout[w * 162 :w * 162 + 35] : + (iu2_ifar_eff_l2[60:61] == 2'b01) ? iu2_data_dataout[w * 162 + 36 :w * 162 + 71] : + (iu2_ifar_eff_l2[60:61] == 2'b10) ? iu2_data_dataout[w * 162 + 72 :w * 162 + 107] : + iu2_data_dataout[w * 162 + 108:w * 162 + 143]; + + assign iu2_instr1_cache_rot[w] = + (iu2_ifar_eff_l2[60:61] == 2'b00) ? iu2_data_dataout[w * 162 + 36 :w * 162 + 71] : + (iu2_ifar_eff_l2[60:61] == 2'b01) ? iu2_data_dataout[w * 162 + 72 :w * 162 + 107] : + iu2_data_dataout[w * 162 + 108:w * 162 + 143]; + + assign iu2_instr2_cache_rot[w] = + (iu2_ifar_eff_l2[61] == 1'b0) ? iu2_data_dataout[w * 162 + 72 :w * 162 + 107] : + iu2_data_dataout[w * 162 + 108:w * 162 + 143]; + + assign iu2_instr3_cache_rot[w] = iu2_data_dataout[w * 162 + 108:w * 162 + 143]; + + // Force 2ucode to 0 if branch instructions or no-op. No other + // instructions are legal when dynamically changing code. + // Note: This signal does not include all non-ucode ops - just the ones + // that will cause problems with flush_2ucode. + assign iu2_uc_illegal_cache_rot[w] = iu2_instr0_cache_rot[w][32] | (iu2_instr0_cache_rot[w][0:5] == 6'b011000); + end + end + endgenerate + + assign iu2_reload_rot[0] = (icm_icd_load_addr[60:61] == 2'b00) ? icm_icd_reload_data[0:35] : + (icm_icd_load_addr[60:61] == 2'b01) ? icm_icd_reload_data[36:71] : + (icm_icd_load_addr[60:61] == 2'b10) ? icm_icd_reload_data[72:107] : + icm_icd_reload_data[108:143]; + + assign iu2_reload_rot[1] = (icm_icd_load_addr[60:61] == 2'b00) ? icm_icd_reload_data[36:71] : + (icm_icd_load_addr[60:61] == 2'b01) ? icm_icd_reload_data[72:107] : + icm_icd_reload_data[108:143]; + + assign iu2_reload_rot[2] = (icm_icd_load_addr[61] == 1'b0) ? icm_icd_reload_data[72:107] : + icm_icd_reload_data[108:143]; + + assign iu2_reload_rot[3] = icm_icd_reload_data[108:143]; + + assign iu2_uc_illegal_reload = iu2_reload_rot[0][32] | (iu2_reload_rot[0][0:5] == 6'b011000); + + // Select way hit + assign iu2_hit_rot[0] = ({36{iu2_rd_hit[0]}} & iu2_instr0_cache_rot[0]) | + ({36{iu2_rd_hit[1]}} & iu2_instr0_cache_rot[1]) | + ({36{iu2_rd_hit[2]}} & iu2_instr0_cache_rot[2]) | + ({36{iu2_rd_hit[3]}} & iu2_instr0_cache_rot[3]); + + assign iu2_hit_rot[1] = ({36{iu2_rd_hit[0]}} & iu2_instr1_cache_rot[0]) | + ({36{iu2_rd_hit[1]}} & iu2_instr1_cache_rot[1]) | + ({36{iu2_rd_hit[2]}} & iu2_instr1_cache_rot[2]) | + ({36{iu2_rd_hit[3]}} & iu2_instr1_cache_rot[3]); + + assign iu2_hit_rot[2] = ({36{iu2_rd_hit[0]}} & iu2_instr2_cache_rot[0]) | + ({36{iu2_rd_hit[1]}} & iu2_instr2_cache_rot[1]) | + ({36{iu2_rd_hit[2]}} & iu2_instr2_cache_rot[2]) | + ({36{iu2_rd_hit[3]}} & iu2_instr2_cache_rot[3]); + + assign iu2_hit_rot[3] = ({36{iu2_rd_hit[0]}} & iu2_instr3_cache_rot[0]) | + ({36{iu2_rd_hit[1]}} & iu2_instr3_cache_rot[1]) | + ({36{iu2_rd_hit[2]}} & iu2_instr3_cache_rot[2]) | + ({36{iu2_rd_hit[3]}} & iu2_instr3_cache_rot[3]); + + assign iu2_uc_illegal_cache = |(iu2_rd_hit & iu2_uc_illegal_cache_rot); + + // Timing: moved xnop to bp + // Using xori 0,0,0 (xnop) when erat error + //xnop <= "011010" & ZEROS(6 to 35); + + generate + begin : xhdl16 + genvar i; + for (i = 0; i < 4; i = i + 1) + begin : gen_instr + assign iu2_instr[i] = (iu2_valid_l2 == 1'b1) ? iu2_hit_rot[i] : + iu2_reload_rot[i]; + end + end + endgenerate + + assign iu2_uc_illegal = (iu2_valid_l2 == 1'b1) ? iu2_uc_illegal_cache : + iu2_uc_illegal_reload; + + //--------------------------------------------------------------------- + // IU3 + //--------------------------------------------------------------------- + + assign ic_bp_iu2_t0_val = {4{iu3_tid_d[0]}} & iu3_instr_valid_d; + `ifndef THREADS1 + assign ic_bp_iu2_t1_val = {4{iu3_tid_d[1]}} & iu3_instr_valid_d; + `endif + + assign ic_bp_iu2_ifar = iu3_ifar_d; + assign ic_bp_iu2_2ucode = iu3_2ucode_d & (~iu2_uc_illegal); + assign ic_bp_iu2_2ucode_type = iu3_2ucode_type_d; + // Moved ecc_err muxing to BP IU3 + assign ic_bp_iu2_error = iu3_erat_err_d; + assign ic_bp_iu2_0_instr = iu2_instr[0]; + assign ic_bp_iu2_1_instr = iu2_instr[1]; + assign ic_bp_iu2_2_instr = iu2_instr[2]; + assign ic_bp_iu2_3_instr = iu2_instr[3]; + + // Moved ic_bp_iu2_flush to iuq_ic_select + assign ic_bp_iu3_flush = {`THREADS{iu3_miss_flush_l2 | icm_icd_iu3_ecc_fp_cancel | ((iu3_parity_needs_flush_l2 | iu3_multihit_flush_l2) & (~iu3_erat_err_l2[0]))}} & iu3_tid_l2; + + assign icd_ics_iu3_ifar = iu3_ifar_l2; + assign icd_ics_iu3_2ucode = iu3_2ucode_l2; + assign icd_ics_iu3_2ucode_type = iu3_2ucode_type_l2; + + //--------------------------------------------------------------------- + // Performance Events + //--------------------------------------------------------------------- + generate + begin : xhdl10 + genvar i; + for (i = 0; i < `THREADS; i = i + 1) + begin : gen_perf + // IERAT Miss + // - IU2 ierat miss + assign perf_t_event_d[i][9] = iu2_valid_l2 & iu2_tid_l2[i] & iu2_read_erat_l2 & ierat_iu_iu2_miss; + + // I-Cache Fetch + // - Number of times ICache is read for instruction + assign perf_t_event_d[i][10] = iu2_valid_l2 & iu2_tid_l2[i]; + + // Instructions Fetched + // - Number of instructions fetched, divided by 4. + assign perf_instr_count_new[i][0:2] = {1'b0, perf_instr_count_l2[i][0:1]} + iu2_instr_count; + assign perf_instr_count_d[i][0:1] = (iu2_valid_l2 & iu2_tid_l2[i]) ? perf_instr_count_new[i][1:2] : + perf_instr_count_l2[i]; + assign perf_t_event_d[i][11] = iu2_valid_l2 & iu2_tid_l2[i] & perf_instr_count_new[i][0]; + end + end + endgenerate + + assign iu2_instr_count = (iu2_ifar_eff_l2[60:61] == 2'b00) ? 3'b100 : + (iu2_ifar_eff_l2[60:61] == 2'b01) ? 3'b011 : + (iu2_ifar_eff_l2[60:61] == 2'b10) ? 3'b010 : + 3'b001; + + // Events not per thread + // L2 Back Invalidates I-Cache + assign perf_event_d[0] = iu2_inval_l2; + + // L2 Back Invalidates I-Cache - Hits + assign perf_event_d[1] = iu2_inval_l2 & |(iu2_rd_tag_hit & iu2_dir_rd_val_l2); + + assign ic_perf_t0_event = perf_t_event_l2[0]; + `ifndef THREADS1 + assign ic_perf_t1_event = perf_t_event_l2[1]; + `endif + assign ic_perf_event = perf_event_l2; + + //--------------------------------------------------------------------- + // Latches + //--------------------------------------------------------------------- + + // IU1 + tri_rlmlatch_p #(.INIT(0)) iu1_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu1_valid_offset]), + .scout(sov[iu1_valid_offset]), + .din(iu1_valid_d), + .dout(iu1_valid_l2) + ); + + generate + if (`THREADS == 1) + begin : iu1_tid1 + assign iu1_tid_l2 = iu1_tid_d | 1'b1; // Need to always be '1' when single thread since we aren't latching. + // 'iu1_tid_d' part is to get rid of unused warnings + assign sov[iu1_tid_offset] = siv[iu1_tid_offset]; + end + endgenerate + + generate + if (`THREADS != 1) + begin : iu1_tid2 + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu1_tid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(dir_rd_act), // ??? Is this act worth it? Only tid, 2ucode, & 2ucode_type use for non-slp + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu1_tid_offset:iu1_tid_offset + `THREADS - 1]), + .scout(sov[iu1_tid_offset:iu1_tid_offset + `THREADS - 1]), + .din(iu1_tid_d), + .dout(iu1_tid_l2) + ); + end + endgenerate + + // Note: Technically, only need REAL_IFAR range during sleep mode + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0), .NEEDS_SRESET(0)) iu1_ifar_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(dir_rd_act), + .thold_b(pc_iu_func_slp_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(funcslp_force), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu1_ifar_offset:iu1_ifar_offset + `EFF_IFAR_ARCH - 1]), + .scout(sov[iu1_ifar_offset:iu1_ifar_offset + `EFF_IFAR_ARCH - 1]), + .din(iu1_ifar_d), + .dout(iu1_ifar_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) iu1_index51_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(dir_rd_act), + .thold_b(pc_iu_func_slp_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(funcslp_force), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu1_index51_offset]), + .scout(sov[iu1_index51_offset]), + .din(iu1_index51_d), + .dout(iu1_index51_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) iu1_inval_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_slp_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(funcslp_force), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu1_inval_offset]), + .scout(sov[iu1_inval_offset]), + .din(iu1_inval_d), + .dout(iu1_inval_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) iu1_prefetch_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu1_prefetch_offset]), + .scout(sov[iu1_prefetch_offset]), + .din(iu1_prefetch_d), + .dout(iu1_prefetch_l2) + ); + + generate + if (`INCLUDE_IERAT_BYPASS == 0) + begin : gen_iu1_read_erat0 + assign iu1_read_erat_l2 = 1'b1 | iu1_read_erat_d; + assign sov[iu1_read_erat_offset] = siv[iu1_read_erat_offset]; + end + endgenerate + + generate + if (`INCLUDE_IERAT_BYPASS == 1) + begin : gen_iu1_read_erat1 + tri_rlmlatch_p #(.INIT(0)) iu1_read_erat_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(dir_rd_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu1_read_erat_offset]), + .scout(sov[iu1_read_erat_offset]), + .din(iu1_read_erat_d), + .dout(iu1_read_erat_l2) + ); + end + endgenerate + + tri_rlmlatch_p #(.INIT(0)) iu1_2ucode_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(dir_rd_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu1_2ucode_offset]), + .scout(sov[iu1_2ucode_offset]), + .din(iu1_2ucode_d), + .dout(iu1_2ucode_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) iu1_2ucode_type_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(dir_rd_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu1_2ucode_type_offset]), + .scout(sov[iu1_2ucode_type_offset]), + .din(iu1_2ucode_type_d), + .dout(iu1_2ucode_type_l2) + ); + + // IU2 + tri_rlmlatch_p #(.INIT(0)) iu2_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu2_valid_offset]), + .scout(sov[iu2_valid_offset]), + .din(iu2_valid_d), + .dout(iu2_valid_l2) + ); + + generate + if (`THREADS == 1) + begin : iu2_tid1 + assign iu2_tid_l2 = iu2_tid_d; + assign sov[iu2_tid_offset] = siv[iu2_tid_offset]; + end + endgenerate + + generate + if (`THREADS != 1) + begin : iu2_tid2 + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu2_tid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(dir_dataout_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu2_tid_offset:iu2_tid_offset + `THREADS - 1]), + .scout(sov[iu2_tid_offset:iu2_tid_offset + `THREADS - 1]), + .din(iu2_tid_d), + .dout(iu2_tid_l2) + ); + end + endgenerate + + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH-10), .INIT(0), .NEEDS_SRESET(0)) iu2_ifar_eff_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(dir_dataout_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu2_ifar_eff_offset:iu2_ifar_eff_offset + `EFF_IFAR_ARCH-10 - 1]), + .scout(sov[iu2_ifar_eff_offset:iu2_ifar_eff_offset + `EFF_IFAR_ARCH-10 - 1]), + .din(iu2_ifar_eff_d[62 - `EFF_IFAR_ARCH:51]), + .dout(iu2_ifar_eff_l2[62 - `EFF_IFAR_ARCH:51]) + ); + + // Only need 52:57 in sleep mode + tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(0)) iu2_ifar_eff_slp_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(dir_dataout_act), + .thold_b(pc_iu_func_slp_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(funcslp_force), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu2_ifar_eff_offset + `EFF_IFAR_ARCH-10:iu2_ifar_eff_offset + `EFF_IFAR_ARCH - 1]), + .scout(sov[iu2_ifar_eff_offset + `EFF_IFAR_ARCH-10:iu2_ifar_eff_offset + `EFF_IFAR_ARCH - 1]), + .din(iu2_ifar_eff_d[52:61]), + .dout(iu2_ifar_eff_l2[52:61]) + ); + + tri_rlmlatch_p #(.INIT(0)) iu2_2ucode_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu1_valid_l2), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu2_2ucode_offset]), + .scout(sov[iu2_2ucode_offset]), + .din(iu2_2ucode_d), + .dout(iu2_2ucode_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) iu2_2ucode_type_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu1_valid_l2), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu2_2ucode_type_offset]), + .scout(sov[iu2_2ucode_type_offset]), + .din(iu2_2ucode_type_d), + .dout(iu2_2ucode_type_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) iu2_index51_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(dir_dataout_act), + .thold_b(pc_iu_func_slp_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(funcslp_force), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu2_index51_offset]), + .scout(sov[iu2_index51_offset]), + .din(iu2_index51_d), + .dout(iu2_index51_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) iu2_inval_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_slp_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(funcslp_force), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu2_inval_offset]), + .scout(sov[iu2_inval_offset]), + .din(iu2_inval_d), + .dout(iu2_inval_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) iu2_prefetch_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu2_prefetch_offset]), + .scout(sov[iu2_prefetch_offset]), + .din(iu2_prefetch_d), + .dout(iu2_prefetch_l2) + ); + + generate + if (`INCLUDE_IERAT_BYPASS == 0) + begin : gen_iu2_read_erat0 + assign iu2_read_erat_l2 = 1'b1 | iu2_read_erat_d; + assign iu2_cam_change_etc_l2 = 1'b0 & iu2_cam_change_etc_d; + assign sov[iu2_read_erat_offset] = siv[iu2_read_erat_offset]; + assign sov[iu2_cam_change_etc_offset] = siv[iu2_cam_change_etc_offset]; + end + endgenerate + + generate + if (`INCLUDE_IERAT_BYPASS == 1) + begin : gen_iu2_read_erat1 + tri_rlmlatch_p #(.INIT(0)) iu2_read_erat_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(dir_dataout_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu2_read_erat_offset]), + .scout(sov[iu2_read_erat_offset]), + .din(iu2_read_erat_d), + .dout(iu2_read_erat_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) iu2_cam_change_etc_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu2_cam_change_etc_offset]), + .scout(sov[iu2_cam_change_etc_offset]), + .din(iu2_cam_change_etc_d), + .dout(iu2_cam_change_etc_l2) + ); + end + endgenerate + + tri_rlmreg_p #(.WIDTH(`REAL_IFAR_WIDTH-12), .INIT(0), .NEEDS_SRESET(0)) iu2_stored_rpn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(dir_dataout_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu2_stored_rpn_offset:iu2_stored_rpn_offset + `REAL_IFAR_WIDTH-12 - 1]), + .scout(sov[iu2_stored_rpn_offset:iu2_stored_rpn_offset + `REAL_IFAR_WIDTH-12 - 1]), + .din(iu2_stored_rpn_d), + .dout(iu2_stored_rpn_l2) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) iu2_dir_rd_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(dir_dataout_act), + .thold_b(pc_iu_func_slp_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(funcslp_force), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu2_dir_rd_val_offset:iu2_dir_rd_val_offset + 4 - 1]), + .scout(sov[iu2_dir_rd_val_offset:iu2_dir_rd_val_offset + 4 - 1]), + .din(iu2_dir_rd_val_d), + .dout(iu2_dir_rd_val_l2) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) iu3_dir_parity_err_way_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_slp_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(funcslp_force), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu3_dir_parity_err_way_offset:iu3_dir_parity_err_way_offset + 4 - 1]), + .scout(sov[iu3_dir_parity_err_way_offset:iu3_dir_parity_err_way_offset + 4 - 1]), + .din(iu3_dir_parity_err_way_d), + .dout(iu3_dir_parity_err_way_l2) + ); + + // Dir + generate + begin : xhdl17 + genvar a; + for (a = 0; a < 128; a = a + 1) + begin : dir_val_latch_gen + + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) dir_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(dir_val_act), + .thold_b(pc_iu_func_slp_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(funcslp_force), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[dir_val_offset + 4 * a:(dir_val_offset + 4 * (a + 1)) - 1]), + .scout(sov[dir_val_offset + 4 * a:(dir_val_offset + 4 * (a + 1)) - 1]), + .din(dir_val_d[a]), + .dout(dir_val_l2[a]) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) dir_lru_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(dir_lru_act[a/8]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[dir_lru_offset + 3 * a:(dir_lru_offset + 3 * (a + 1)) - 1]), + .scout(sov[dir_lru_offset + 3 * a:(dir_lru_offset + 3 * (a + 1)) - 1]), + .din(dir_lru_d[a]), + .dout(dir_lru_l2[a]) + ); + end + end + endgenerate + + tri_rlmlatch_p #(.INIT(0)) iu3_miss_flush( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu3_miss_flush_offset]), + .scout(sov[iu3_miss_flush_offset]), + .din(iu3_miss_flush_d), + .dout(iu3_miss_flush_l2) + ); + + generate + if (`THREADS == 1) + begin : iu3_tid1 + assign iu3_tid_l2 = iu3_tid_d | 1'b1; // Need to always be '1' when single thread since we aren't latching. + // 'iu3_tid_d' part is to get rid of unused warnings + assign sov[iu3_tid_offset] = siv[iu3_tid_offset]; + end + endgenerate + + generate + if (`THREADS != 1) + begin : iu3_tid2 + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu3_tid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu3_tid_offset:iu3_tid_offset + `THREADS - 1]), + .scout(sov[iu3_tid_offset:iu3_tid_offset + `THREADS - 1]), + .din(iu3_tid_d), + .dout(iu3_tid_l2) + ); + end + endgenerate + + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0), .NEEDS_SRESET(0)) iu3_ifar_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu2_valid_l2), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu3_ifar_offset:iu3_ifar_offset + `EFF_IFAR_WIDTH - 1]), + .scout(sov[iu3_ifar_offset:iu3_ifar_offset + `EFF_IFAR_WIDTH - 1]), + .din(iu3_ifar_d), + .dout(iu3_ifar_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) iu3_2ucode_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu2_valid_l2), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu3_2ucode_offset]), + .scout(sov[iu3_2ucode_offset]), + .din(iu3_2ucode_d), + .dout(iu3_2ucode_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) iu3_2ucode_type_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu2_valid_l2), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu3_2ucode_type_offset]), + .scout(sov[iu3_2ucode_type_offset]), + .din(iu3_2ucode_type_d), + .dout(iu3_2ucode_type_l2) + ); + + tri_rlmreg_p #(.WIDTH(1), .INIT(0)) iu3_erat_err_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu3_erat_err_offset:iu3_erat_err_offset + 1 - 1]), + .scout(sov[iu3_erat_err_offset:iu3_erat_err_offset + 1 - 1]), + .din(iu3_erat_err_d[0:0]), + .dout(iu3_erat_err_l2) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) iu3_multihit_err_way_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_slp_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(funcslp_force), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu3_multihit_err_way_offset:iu3_multihit_err_way_offset + 4 - 1]), + .scout(sov[iu3_multihit_err_way_offset:iu3_multihit_err_way_offset + 4 - 1]), + .din(iu3_multihit_err_way_d), + .dout(iu3_multihit_err_way_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) iu3_multihit_flush_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu3_multihit_flush_offset]), + .scout(sov[iu3_multihit_flush_offset]), + .din(iu3_multihit_flush_d), + .dout(iu3_multihit_flush_l2) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) iu3_data_parity_err_way_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu3_data_parity_err_way_offset:iu3_data_parity_err_way_offset + 4 - 1]), + .scout(sov[iu3_data_parity_err_way_offset:iu3_data_parity_err_way_offset + 4 - 1]), + .din(iu3_data_parity_err_way_d), + .dout(iu3_data_parity_err_way_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) iu3_parity_needs_flush_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu3_parity_needs_flush_offset]), + .scout(sov[iu3_parity_needs_flush_offset]), + .din(iu3_parity_needs_flush_d), + .dout(iu3_parity_needs_flush_l2) + ); + + tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(0)) iu3_parity_tag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_slp_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(funcslp_force), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu3_parity_tag_offset:iu3_parity_tag_offset + 7 - 1]), + .scout(sov[iu3_parity_tag_offset:iu3_parity_tag_offset + 7 - 1]), + .din(iu3_parity_tag_d), + .dout(iu3_parity_tag_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) ici_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[ici_val_offset]), + .scout(sov[ici_val_offset]), + .din(ici_val_d), + .dout(ici_val_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) spr_ic_cls_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[spr_ic_cls_offset]), + .scout(sov[spr_ic_cls_offset]), + .din(spr_ic_cls_d), + .dout(spr_ic_cls_l2) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) spr_ic_idir_way_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(dir_dataout_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[spr_ic_idir_way_offset:spr_ic_idir_way_offset + 2 - 1]), + .scout(sov[spr_ic_idir_way_offset:spr_ic_idir_way_offset + 2 - 1]), + .din(spr_ic_idir_way_d), + .dout(spr_ic_idir_way_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) iu1_spr_idir_read_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu1_spr_idir_read_offset]), + .scout(sov[iu1_spr_idir_read_offset]), + .din(iu1_spr_idir_read_d), + .dout(iu1_spr_idir_read_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) iu2_spr_idir_read_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu2_spr_idir_read_offset]), + .scout(sov[iu2_spr_idir_read_offset]), + .din(iu2_spr_idir_read_d), + .dout(iu2_spr_idir_read_l2) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu2_spr_idir_lru_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(dir_dataout_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu2_spr_idir_lru_offset:iu2_spr_idir_lru_offset + 3 - 1]), + .scout(sov[iu2_spr_idir_lru_offset:iu2_spr_idir_lru_offset + 3 - 1]), + .din(iu2_spr_idir_lru_d), + .dout(iu2_spr_idir_lru_l2) + ); + + generate + begin : xhdl19 + if (`INCLUDE_IERAT_BYPASS == 0) + begin : gen0 + genvar i; + for (i = 0; i < `THREADS; i = i + 1) + begin : thr0 + assign stored_erat_rpn_l2[i] = {`REAL_IFAR_WIDTH-12{1'b0}} & stored_erat_rpn_d[i]; // ..._d part is to get rid of unused warnings + assign stored_erat_wimge_l2[i] = 5'b0 & stored_erat_wimge_d[i]; + assign stored_erat_u_l2[i] = 4'b0 & stored_erat_u_d[i]; + end + + assign sov[stored_erat_rpn_offset:stored_erat_u_offset + 4 * `THREADS - 1] = siv[stored_erat_rpn_offset:stored_erat_u_offset + 4 * `THREADS - 1]; + end + + if (`INCLUDE_IERAT_BYPASS == 1) + begin : gen1 + genvar i; + for (i = 0; i < `THREADS; i = i + 1) + begin : thr + tri_rlmreg_p #(.WIDTH(`REAL_IFAR_WIDTH-12), .INIT(0)) stored_erat_rpn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stored_erat_act[i]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stored_erat_rpn_offset + i * (`REAL_IFAR_WIDTH-12):stored_erat_rpn_offset + (i + 1) * (`REAL_IFAR_WIDTH-12) - 1]), + .scout(sov[stored_erat_rpn_offset + i * (`REAL_IFAR_WIDTH-12):stored_erat_rpn_offset + (i + 1) * (`REAL_IFAR_WIDTH-12) - 1]), + .din(stored_erat_rpn_d[i]), + .dout(stored_erat_rpn_l2[i]) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(0)) stored_erat_wimge_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stored_erat_act[i]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stored_erat_wimge_offset + i * 5:stored_erat_wimge_offset + (i + 1) * 5 - 1]), + .scout(sov[stored_erat_wimge_offset + i * 5:stored_erat_wimge_offset + (i + 1) * 5 - 1]), + .din(stored_erat_wimge_d[i]), + .dout(stored_erat_wimge_l2[i]) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) stored_erat_u_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stored_erat_act[i]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stored_erat_u_offset + i * 4:stored_erat_u_offset + (i + 1) * 4 - 1]), + .scout(sov[stored_erat_u_offset + i * 4:stored_erat_u_offset + (i + 1) * 4 - 1]), + .din(stored_erat_u_d[i]), + .dout(stored_erat_u_l2[i]) + ); + end + end + end + endgenerate + + generate + begin : xhdl18 + genvar i; + for (i = 0; i < `THREADS; i = i + 1) + begin : gen_perf_reg + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) perf_instr_count_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(event_bus_enable), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[perf_instr_count_offset + i * 2:perf_instr_count_offset + (i + 1) * 2 - 1]), + .scout(sov[perf_instr_count_offset + i * 2:perf_instr_count_offset + (i + 1) * 2 - 1]), + .din(perf_instr_count_d[i]), + .dout(perf_instr_count_l2[i]) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) perf_t_event_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(event_bus_enable), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[perf_t_event_offset + i * 3:perf_t_event_offset + (i + 1) * 3 - 1]), + .scout(sov[perf_t_event_offset + i * 3:perf_t_event_offset + (i + 1) * 3 - 1]), + .din(perf_t_event_d[i]), + .dout(perf_t_event_l2[i]) + ); + end + end + endgenerate + + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) perf_event_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(event_bus_enable), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[perf_event_offset:perf_event_offset + 2 - 1]), + .scout(sov[perf_event_offset:perf_event_offset + 2 - 1]), + .din(perf_event_d), + .dout(perf_event_l2) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) pc_iu_inj_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[pc_iu_inj_offset:pc_iu_inj_offset + 3 - 1]), + .scout(sov[pc_iu_inj_offset:pc_iu_inj_offset + 3 - 1]), + .din({pc_iu_inj_icache_parity, + pc_iu_inj_icachedir_parity, + pc_iu_inj_icachedir_multihit}), + .dout({pc_iu_inj_icache_parity_l2, + pc_iu_inj_icachedir_parity_l2, + pc_iu_inj_icachedir_multihit_l2}) + ); + + //--------------------------------------------------------------------- + // abist latches + //--------------------------------------------------------------------- + tri_rlmreg_p #(.INIT(0), .WIDTH(41), .NEEDS_SRESET(0)) ab_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pc_iu_abist_ena_dc), + .thold_b(pc_iu_abst_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(abst_force), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(abst_siv[4:44]), + .scout(abst_sov[4:44]), + .din({pc_iu_abist_g8t_wenb, pc_iu_abist_g8t1p_renb_0, pc_iu_abist_di_0, + pc_iu_abist_g8t_bw_1, pc_iu_abist_g8t_bw_0, pc_iu_abist_waddr_0, + pc_iu_abist_wl128_comp_ena, pc_iu_abist_g8t_dcomp, pc_iu_abist_raddr_0, + pc_iu_abist_g6t_bw, pc_iu_abist_di_g6t_2r, pc_iu_abist_wl512_comp_ena, + pc_iu_abist_dcomp_g6t_2r, pc_iu_abist_g6t_r_wb}), + .dout({stage_abist_g8t_wenb, stage_abist_g8t1p_renb_0, stage_abist_di_0, + stage_abist_g8t_bw_1, stage_abist_g8t_bw_0, stage_abist_waddr_0, + stage_abist_wl128_comp_ena, stage_abist_g8t_dcomp, stage_abist_raddr_0, + stage_abist_g6t_bw, stage_abist_di_g6t_2r, stage_abist_wl512_comp_ena, + stage_abist_dcomp_g6t_2r, stage_abist_g6t_r_wb}) + ); + + //--------------------------------------------------------------------- + // Scan + //--------------------------------------------------------------------- + assign siv[0:scan_right] = {sov[1:scan_right], func_scan_in}; + assign func_scan_out = sov[0] & tc_ac_scan_dis_dc_b; + // Chain 0: WAY01 IDIR & IDATA + assign abst_siv[0:1] = {abst_sov[1], abst_scan_in[0]}; + assign abst_scan_out[0] = abst_sov[0] & tc_ac_scan_dis_dc_b; + + // Chain 1: WAY23 IDIR & IDATA + assign abst_siv[2:3] = {abst_sov[3], abst_scan_in[1]}; + assign abst_scan_out[1] = abst_sov[2] & tc_ac_scan_dis_dc_b; + + // Chain 2: AB_REG - tack on to BHT's scan chain + assign abst_siv[4:44] = {abst_sov[5:44], abst_scan_in[2]}; + assign abst_scan_out[2] = abst_sov[4] & tc_ac_scan_dis_dc_b; + + assign time_siv = {time_sov[1:1], time_scan_in}; + assign time_scan_out = time_sov[0] & tc_ac_scan_dis_dc_b; + assign repr_siv = {repr_sov[1:1], repr_scan_in}; + assign repr_scan_out = repr_sov[0] & tc_ac_scan_dis_dc_b; + +endmodule diff --git a/dev/verilog/work/iuq_ic_ierat.v b/dev/verilog/work/iuq_ic_ierat.v new file mode 100755 index 0000000..919457f --- /dev/null +++ b/dev/verilog/work/iuq_ic_ierat.v @@ -0,0 +1,7307 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//******************************************************************** +//* TITLE: Instruction Effective to Real Address Translation +//* NAME: iuq_ic_ierat.v +//********************************************************************* + +`include "tri_a2o.vh" + +module iuq_ic_ierat( + // POWER PINS + inout gnd, + inout vdd, + inout vcs, + + // CLOCK and CLOCKCONTROL ports + (* pin_data ="PIN_FUNCTION=/G_CLK/" *) + input [0:`NCLK_WIDTH-1] nclk, + input pc_iu_init_reset, + input tc_ccflush_dc, + input tc_scan_dis_dc_b, + input tc_scan_diag_dc, + input tc_lbist_en_dc, + input an_ac_atpg_en_dc, + input an_ac_grffence_en_dc, + + input lcb_d_mode_dc, + input lcb_clkoff_dc_b, + input lcb_act_dis_dc, + input [0:1] lcb_mpw1_dc_b, + input lcb_mpw2_dc_b, + input [0:1] lcb_delay_lclkr_dc, + + input pc_iu_func_sl_thold_2, + input pc_iu_func_slp_sl_thold_2, + input pc_iu_func_slp_nsl_thold_2, + input pc_iu_cfg_slp_sl_thold_2, + input pc_iu_regf_slp_sl_thold_2, + input pc_iu_time_sl_thold_2, + input pc_iu_sg_2, + input pc_iu_fce_2, + + input cam_clkoff_b, + input cam_act_dis, + input cam_d_mode, + input [0:4] cam_delay_lclkr, + input [0:4] cam_mpw1_b, + input cam_mpw2_b, + + (* pin_data ="PIN_FUNCTION=/SCAN_IN/" *) + input [0:1] ac_func_scan_in, + (* pin_data ="PIN_FUNCTION=/SCAN_OUT/" *) + output [0:1] ac_func_scan_out, + (* pin_data ="PIN_FUNCTION=/SCAN_IN/" *) + input ac_ccfg_scan_in, + (* pin_data ="PIN_FUNCTION=/SCAN_OUT/" *) + output ac_ccfg_scan_out, + (* pin_data ="PIN_FUNCTION=/SCAN_IN/" *) + input func_scan_in_cam, // unique to iu + (* pin_data ="PIN_FUNCTION=/SCAN_OUT/" *) + output func_scan_out_cam, // unique to iu + (* pin_data ="PIN_FUNCTION=/SCAN_IN/" *) + input time_scan_in, + (* pin_data ="PIN_FUNCTION=/SCAN_OUT/" *) + output time_scan_out, + (* pin_data ="PIN_FUNCTION=/SCAN_IN/" *) + input [0:4] regf_scan_in, + (* pin_data ="PIN_FUNCTION=/SCAN_OUT/" *) + output [0:4] regf_scan_out, + + // Functional ports + // act control + input spr_ic_clockgate_dis, + // ttypes + input iu_ierat_iu0_val, // xu has 4 vals, no thdid + input [0:`THREADS-1] iu_ierat_iu0_thdid, + input [0:51] iu_ierat_iu0_ifar, // xu used GPR_WIDTH_ENC + input iu_ierat_iu0_nonspec, + input iu_ierat_iu0_prefetch, + + input [0:`THREADS-1] iu_ierat_iu0_flush, + input [0:`THREADS-1] iu_ierat_iu1_flush, // latched and is output below iu_mm_ierat_flush + + // ordered instructions + input [0:`THREADS-1] xu_iu_val, + input xu_iu_is_eratre, + input xu_iu_is_eratwe, + input xu_iu_is_eratsx, + input xu_iu_is_eratilx, + input [0:1] xu_iu_ws, + input [0:3] xu_iu_ra_entry, + input [64-`GPR_WIDTH:63] xu_iu_rs_data, // eratwe + input [64-`GPR_WIDTH:51] xu_iu_rb, // eratsx + output [64-`GPR_WIDTH:63] iu_xu_ex4_data, // eratre + + output iu_xu_ord_read_done, + output iu_xu_ord_write_done, + output iu_xu_ord_par_err, + + // context synchronizing event + input cp_ic_is_isync, + input cp_ic_is_csync, + + // reload from mmu + input [0:4] mm_iu_ierat_rel_val, // bit 4 is hit/miss + input [0:131] mm_iu_ierat_rel_data, + output [0:`THREADS-1] ierat_iu_hold_req, + + // I$ snoop + input iu_ierat_iu1_back_inv, + input iu_ierat_ium1_back_inv, // ??? + + // tlbivax or tlbilx snoop + input mm_iu_ierat_snoop_coming, + input mm_iu_ierat_snoop_val, + input [0:25] mm_iu_ierat_snoop_attr, + input [0:51] mm_iu_ierat_snoop_vpn, + output iu_mm_ierat_snoop_ack, + + // pipeline controls + input [0:`THREADS-1] xu_iu_flush, + input [0:`THREADS-1] br_iu_flush, + // all tied to cp_flush + input [0:`THREADS-1] xu_rf1_flush, + input [0:`THREADS-1] xu_ex1_flush, + input [0:`THREADS-1] xu_ex2_flush, + input [0:`THREADS-1] xu_ex3_flush, + input [0:`THREADS-1] xu_ex4_flush, + input [0:`THREADS-1] xu_ex5_flush, + + // cam _np2 ports + output [22:51] ierat_iu_iu2_rpn, + output [0:4] ierat_iu_iu2_wimge, + output [0:3] ierat_iu_iu2_u, // wlc, attr, vf not needed ? + output ierat_iu_iu2_miss, + output ierat_iu_iu2_isi, + output [0:2] ierat_iu_iu2_error, + output ierat_iu_iu2_multihit, + + output ierat_iu_cam_change, + + output iu_pc_err_ierat_multihit, + output iu_pc_err_ierat_parity, + + // erat request to mmu + output iu_mm_ierat_req, + output iu_mm_ierat_req_nonspec, + output [0:`THREADS-1] iu_mm_ierat_thdid, + output [0:3] iu_mm_ierat_state, + output [0:13] iu_mm_ierat_tid, + output [0:`THREADS-1] iu_mm_ierat_flush, // latched version of iu_mm_ierat_flush input above + // may not be needed, MMU can tie to cp_flush + // write interface to mmucr0,1 + output [0:17] iu_mm_ierat_mmucr0, + output [0:`THREADS-1] iu_mm_ierat_mmucr0_we, + output [0:3] iu_mm_ierat_mmucr1, + output [0:`THREADS-1] iu_mm_ierat_mmucr1_we, + output [0:`THREADS-1] iu_mm_perf_itlb, + + // spr's + input [0:`THREADS-1] xu_iu_msr_hv, + input [0:`THREADS-1] xu_iu_msr_pr, + input [0:`THREADS-1] xu_iu_msr_is, + input [0:`THREADS-1] xu_iu_msr_cm, + input xu_iu_hid_mmu_mode, + input xu_iu_spr_ccr2_ifrat, + input [0:8] xu_iu_spr_ccr2_ifratsc, + input xu_iu_xucr4_mmu_mchk, + + output [0:`THREADS-1] ierat_iu_iu2_flush_req, // xu only had ex3_n_flush out + // local flush for timing + output iu_xu_ord_n_flush_req, + + input [0:13] mm_iu_t0_ierat_pid, + input [0:19] mm_iu_t0_ierat_mmucr0, + `ifndef THREADS1 + input [0:13] mm_iu_t1_ierat_pid, + input [0:19] mm_iu_t1_ierat_mmucr0, + `endif + input [0:8] mm_iu_ierat_mmucr1, + + // debug + input pc_iu_trace_bus_enable, + output [0:87] ierat_iu_debug_group0, + output [0:87] ierat_iu_debug_group1, + output [0:87] ierat_iu_debug_group2, + output [0:87] ierat_iu_debug_group3 +); + + //-------------------------- + // constants + //-------------------------- + // Field/Signal sizes + parameter ttype_width = 3; + parameter state_width = 4; + parameter pid_width = 14; + parameter pid_width_erat = 8; + parameter extclass_width = 2; + parameter tlbsel_width = 2; + parameter epn_width = 52; + parameter vpn_width = 61; + parameter rpn_width = 30; // real_addr_width-12 + parameter ws_width = 2; + parameter ra_entry_width = 4; + parameter rs_data_width = 64; // 32 or 64 for n-bit design (not cm mode) + parameter data_out_width = 64; // 32 or 64 for n-bit design (not cm mode) + parameter error_width = 3; + parameter cam_data_width = 84; + parameter array_data_width = 68; // 16x143 version + parameter num_entry = 16; + parameter num_entry_log2 = 4; + parameter por_seq_width = 3; + parameter watermark_width = 4; + parameter eptr_width = 4; + parameter lru_width = 15; + parameter bcfg_width = 123; + parameter check_parity = 1; // 1=erat parity implemented in rtx + + parameter MMU_Mode_Value = 1'b0; + parameter [0:1] TlbSel_Tlb = 2'b00; + parameter [0:1] TlbSel_IErat = 2'b10; + parameter [0:1] TlbSel_DErat = 2'b11; + + parameter [0:2] CAM_PgSize_1GB = 3'b110; + parameter [0:2] CAM_PgSize_16MB = 3'b111; + parameter [0:2] CAM_PgSize_1MB = 3'b101; + parameter [0:2] CAM_PgSize_64KB = 3'b011; + parameter [0:2] CAM_PgSize_4KB = 3'b001; + parameter [0:3] WS0_PgSize_1GB = 4'b1010; + parameter [0:3] WS0_PgSize_16MB = 4'b0111; + parameter [0:3] WS0_PgSize_1MB = 4'b0101; + parameter [0:3] WS0_PgSize_64KB = 4'b0011; + parameter [0:3] WS0_PgSize_4KB = 4'b0001; + + parameter eratpos_epn = 0; + parameter eratpos_x = 52; + parameter eratpos_size = 53; + parameter eratpos_v = 56; + parameter eratpos_thdid = 57; + parameter eratpos_class = 61; + parameter eratpos_extclass = 63; + parameter eratpos_wren = 65; + parameter eratpos_rpnrsvd = 66; + parameter eratpos_rpn = 70; + parameter eratpos_r = 100; + parameter eratpos_c = 101; + parameter eratpos_relsoon = 102; + parameter eratpos_wlc = 103; + parameter eratpos_resvattr = 105; + parameter eratpos_vf = 106; + parameter eratpos_ubits = 107; + parameter eratpos_wimge = 111; + parameter eratpos_usxwr = 116; + parameter eratpos_gs = 122; + parameter eratpos_ts = 123; + parameter eratpos_tid = 124; // 8 bits + + parameter [0:2] PorSeq_Idle = 3'b000; + parameter [0:2] PorSeq_Stg1 = 3'b001; + parameter [0:2] PorSeq_Stg2 = 3'b011; + parameter [0:2] PorSeq_Stg3 = 3'b010; + parameter [0:2] PorSeq_Stg4 = 3'b110; + parameter [0:2] PorSeq_Stg5 = 3'b100; + parameter [0:2] PorSeq_Stg6 = 3'b101; + parameter [0:2] PorSeq_Stg7 = 3'b111; + + parameter [0:num_entry_log2-1] Por_Wr_Entry_Num1 = 4'b1110; + parameter [0:num_entry_log2-1] Por_Wr_Entry_Num2 = 4'b1111; + + // wr_cam_data ----------------------------------------------------------------- + // 0:51 - EPN + // 52 - X + // 53:55 - SIZE + // 56 - V + // 57:60 - ThdID + // 61:62 - Class + // 63:64 - ExtClass | TID_NZ + // 65 - TGS + // 66 - TS + // 67:74 - TID + // 75:78 - epn_cmpmasks: 34_39, 40_43, 44_47, 48_51 + // 79:82 - xbit_cmpmasks: 34_51, 40_51, 44_51, 48_51 + // 83 - parity for 75:82 + + parameter [0:83] Por_Wr_Cam_Data1 = {52'b0000000000000000000000000000000011111111111111111111, 1'b0, 3'b001, 1'b1, 4'b1111, 2'b00, 2'b00, 2'b00, 8'b00000000, 8'b11110000, 1'b0}; + parameter [0:83] Por_Wr_Cam_Data2 = {52'b0000000000000000000000000000000000000000000000000000, 1'b0, 3'b001, 1'b1, 4'b1111, 2'b00, 2'b10, 2'b00, 8'b00000000, 8'b11110000, 1'b0}; + + // 16x143 version, 42b RA + // wr_array_data + // 0:29 - RPN + // 30:31 - R,C + // 32:33 - WLC + // 34 - ResvAttr + // 35 - VF + // 36:39 - U0-U3 + // 40:44 - WIMGE + // 45:47 - UX,UW,UR + // 48:50 - SX,SW,SR + // 45:46 - UX,SX + // 47:48 - UW,SW + // 49:50 - UR,SR + // 51:60 - CAM parity + // 61:67 - Array parity + + parameter [0:67] Por_Wr_Array_Data1 = {30'b111111111111111111111111111111, 2'b00, 4'b0000, 4'b0000, 5'b01010, 2'b01, 2'b00, 2'b01, 10'b0000001000, 7'b0000000}; + parameter [0:67] Por_Wr_Array_Data2 = {30'b000000000000000000000000000000, 2'b00, 4'b0000, 4'b0000, 5'b01010, 2'b01, 2'b00, 2'b01, 10'b0000001010, 7'b0000000}; + + parameter ex1_valid_offset = 0; + parameter ex1_ttype_offset = ex1_valid_offset + `THREADS; + parameter ex1_ws_offset = ex1_ttype_offset + ttype_width; + parameter ex1_ra_entry_offset = ex1_ws_offset + ws_width; + parameter ex1_state_offset = ex1_ra_entry_offset + ra_entry_width; + parameter ex1_pid_offset = ex1_state_offset + state_width; + parameter ex1_extclass_offset = ex1_pid_offset + pid_width; + parameter ex1_tlbsel_offset = ex1_extclass_offset + extclass_width; + + parameter ex2_valid_offset = ex1_tlbsel_offset + tlbsel_width; + parameter ex2_ttype_offset = ex2_valid_offset + `THREADS; + parameter ex2_ws_offset = ex2_ttype_offset + ttype_width; + parameter ex2_ra_entry_offset = ex2_ws_offset + ws_width; + parameter ex2_state_offset = ex2_ra_entry_offset + ra_entry_width; + parameter ex2_pid_offset = ex2_state_offset + state_width; + parameter ex2_extclass_offset = ex2_pid_offset + pid_width; + parameter ex2_tlbsel_offset = ex2_extclass_offset + extclass_width; + + parameter ex3_valid_offset = ex2_tlbsel_offset + tlbsel_width; + parameter ex3_ttype_offset = ex3_valid_offset + `THREADS; + parameter ex3_ws_offset = ex3_ttype_offset + ttype_width; + parameter ex3_ra_entry_offset = ex3_ws_offset + ws_width; + parameter ex3_state_offset = ex3_ra_entry_offset + ra_entry_width; + parameter ex3_pid_offset = ex3_state_offset + state_width; + parameter ex3_extclass_offset = ex3_pid_offset + pid_width; + parameter ex3_tlbsel_offset = ex3_extclass_offset + extclass_width; + parameter ex3_eratsx_data_offset = ex3_tlbsel_offset + tlbsel_width; + + parameter ex4_valid_offset = ex3_eratsx_data_offset + 2 + num_entry_log2; + parameter ex4_ttype_offset = ex4_valid_offset + `THREADS; + parameter ex4_ws_offset = ex4_ttype_offset + ttype_width; + parameter ex4_ra_entry_offset = ex4_ws_offset + ws_width; + parameter ex4_state_offset = ex4_ra_entry_offset + ra_entry_width; + parameter ex4_pid_offset = ex4_state_offset + state_width; + parameter ex4_extclass_offset = ex4_pid_offset + pid_width; + parameter ex4_tlbsel_offset = ex4_extclass_offset + extclass_width; + parameter ex4_data_out_offset = ex4_tlbsel_offset + tlbsel_width; + + parameter ex5_valid_offset = ex4_data_out_offset + data_out_width; + parameter ex5_ttype_offset = ex5_valid_offset + `THREADS; + parameter ex5_ws_offset = ex5_ttype_offset + ttype_width; + parameter ex5_ra_entry_offset = ex5_ws_offset + ws_width; + parameter ex5_state_offset = ex5_ra_entry_offset + ra_entry_width; + parameter ex5_pid_offset = ex5_state_offset + state_width; + parameter ex5_extclass_offset = ex5_pid_offset + pid_width; + parameter ex5_tlbsel_offset = ex5_extclass_offset + extclass_width; + parameter ex5_data_in_offset = ex5_tlbsel_offset + tlbsel_width; + + parameter ex6_valid_offset = ex5_data_in_offset + rs_data_width; + parameter ex6_ttype_offset = ex6_valid_offset + `THREADS; + parameter ex6_ws_offset = ex6_ttype_offset + ttype_width; + parameter ex6_ra_entry_offset = ex6_ws_offset + ws_width; + parameter ex6_state_offset = ex6_ra_entry_offset + ra_entry_width; + parameter ex6_pid_offset = ex6_state_offset + state_width; + parameter ex6_extclass_offset = ex6_pid_offset + pid_width; + parameter ex6_tlbsel_offset = ex6_extclass_offset + extclass_width; + parameter ex6_data_in_offset = ex6_tlbsel_offset + tlbsel_width; + + parameter iu1_flush_enab_offset = ex6_data_in_offset + rs_data_width; + parameter iu2_n_flush_req_offset = iu1_flush_enab_offset + 1; + parameter hold_req_offset = iu2_n_flush_req_offset + `THREADS; + parameter tlb_miss_offset = hold_req_offset + `THREADS; + parameter tlb_flushed_offset = tlb_miss_offset + `THREADS; + parameter tlb_req_inprogress_offset = tlb_flushed_offset + `THREADS; + parameter iu1_valid_offset = tlb_req_inprogress_offset + `THREADS; + parameter iu1_state_offset = iu1_valid_offset + `THREADS; + parameter iu1_pid_offset = iu1_state_offset + state_width; + parameter iu1_nonspec_offset = iu1_pid_offset + pid_width; + parameter iu1_prefetch_offset = iu1_nonspec_offset + 1; + parameter iu2_prefetch_offset = iu1_prefetch_offset + 1; + parameter iu2_valid_offset = iu2_prefetch_offset + 1; + parameter iu2_state_offset = iu2_valid_offset + `THREADS; + parameter iu2_pid_offset = iu2_state_offset + state_width; + parameter iu2_nonspec_offset = iu2_pid_offset + pid_width; + parameter iu2_miss_offset = iu2_nonspec_offset + 1; + parameter iu2_multihit_offset = iu2_miss_offset + 2; + parameter iu2_parerr_offset = iu2_multihit_offset + 2; + parameter iu2_isi_offset = iu2_parerr_offset + 2; + parameter iu2_tlbreq_offset = iu2_isi_offset + 6; + parameter iu2_perf_itlb_offset = iu2_tlbreq_offset + 1; + parameter iu2_multihit_b_pt_offset = iu2_perf_itlb_offset + `THREADS; + parameter iu2_first_hit_entry_pt_offset = iu2_multihit_b_pt_offset + num_entry; + parameter iu2_cam_cmp_data_offset = iu2_first_hit_entry_pt_offset + num_entry - 1; + parameter iu2_array_cmp_data_offset = iu2_cam_cmp_data_offset + cam_data_width; + parameter ex4_rd_cam_data_offset = iu2_array_cmp_data_offset + array_data_width; + parameter ex4_rd_array_data_offset = ex4_rd_cam_data_offset + cam_data_width; + parameter ex3_parerr_offset = ex4_rd_array_data_offset + array_data_width; + parameter ex4_parerr_offset = ex3_parerr_offset + `THREADS + 1; + parameter ex4_ieen_offset = ex4_parerr_offset + `THREADS + 3; + parameter ex5_ieen_offset = ex4_ieen_offset + `THREADS + num_entry_log2; + parameter ex6_ieen_offset = ex5_ieen_offset + `THREADS + num_entry_log2; + parameter mmucr1_offset = ex6_ieen_offset + `THREADS + num_entry_log2; + parameter rpn_holdreg_offset = mmucr1_offset + 9; + parameter entry_valid_offset = rpn_holdreg_offset + 64 * `THREADS; + parameter entry_match_offset = entry_valid_offset + 16; + parameter watermark_offset = entry_match_offset + 16; + parameter eptr_offset = watermark_offset + watermark_width; + parameter lru_offset = eptr_offset + eptr_width; + parameter lru_update_event_offset = lru_offset + lru_width; + parameter lru_debug_offset = lru_update_event_offset + 10; + parameter iu_xu_ord_write_done_offset = lru_debug_offset + 24; + parameter iu_xu_ord_read_done_offset = iu_xu_ord_write_done_offset + 1; + parameter iu_xu_ord_par_err_offset = iu_xu_ord_read_done_offset + 1; + parameter cp_ic_csinv_comp_offset = iu_xu_ord_par_err_offset + 1; + parameter scan_right_0 = cp_ic_csinv_comp_offset + 4 - 1; + // NOTE: scan_right_0 is maxed out! use scan_right_1 chain for new additions! + + parameter snoop_val_offset = 0; + parameter spare_a_offset = snoop_val_offset + 3; + parameter snoop_attr_offset = spare_a_offset + 16; + parameter snoop_addr_offset = snoop_attr_offset + 26; + parameter spare_b_offset = snoop_addr_offset + epn_width; + parameter por_seq_offset = spare_b_offset + 16; + parameter tlb_rel_val_offset = por_seq_offset + 3; + parameter tlb_rel_data_offset = tlb_rel_val_offset + 5; + parameter iu_mm_ierat_flush_offset = tlb_rel_data_offset + 132; + parameter iu_xu_ierat_ex2_flush_offset = iu_mm_ierat_flush_offset + `THREADS; + parameter ccr2_frat_paranoia_offset = iu_xu_ierat_ex2_flush_offset + `THREADS; + parameter ccr2_notlb_offset = ccr2_frat_paranoia_offset + 10; + parameter xucr4_mmu_mchk_offset = ccr2_notlb_offset + 1; + parameter mchk_flash_inv_offset = xucr4_mmu_mchk_offset + 1; + parameter ex7_valid_offset = mchk_flash_inv_offset + 4; + parameter ex7_ttype_offset = ex7_valid_offset + `THREADS; + parameter ex7_tlbsel_offset = ex7_ttype_offset + ttype_width; + parameter iu1_debug_offset = ex7_tlbsel_offset + 2; + parameter iu2_debug_offset = iu1_debug_offset + 11; + + parameter iu1_stg_act_offset = iu2_debug_offset + 17; + parameter iu2_stg_act_offset = iu1_stg_act_offset + 1; + parameter iu3_stg_act_offset = iu2_stg_act_offset + 1; + parameter ex1_stg_act_offset = iu3_stg_act_offset + 1; + parameter ex2_stg_act_offset = ex1_stg_act_offset + 1; + parameter ex3_stg_act_offset = ex2_stg_act_offset + 1; + parameter ex4_stg_act_offset = ex3_stg_act_offset + 1; + parameter ex5_stg_act_offset = ex4_stg_act_offset + 1; + parameter ex6_stg_act_offset = ex5_stg_act_offset + 1; + parameter ex7_stg_act_offset = ex6_stg_act_offset + 1; + parameter tlb_rel_act_offset = ex7_stg_act_offset + 1; + parameter snoop_act_offset = tlb_rel_act_offset + 1; + parameter iu_pc_err_ierat_multihit_offset = snoop_act_offset + 1; + parameter iu_pc_err_ierat_parity_offset = iu_pc_err_ierat_multihit_offset + 1; + parameter trace_bus_enable_offset = iu_pc_err_ierat_parity_offset + 1; + parameter an_ac_grffence_en_dc_offset = trace_bus_enable_offset + 1; + parameter scan_right_1 = an_ac_grffence_en_dc_offset + 1 - 1; + + parameter bcfg_offset = 0; + parameter boot_scan_right = bcfg_offset + bcfg_width - 1; + + //-------------------------- + // signals + //-------------------------- + //@@ Signal Declarations + wire [1:19] cam_mask_bits_pt; + wire [1:15] iu1_first_hit_entry_pt; + wire [1:16] iu1_multihit_b_pt; + wire [1:17] lru_rmt_vec_pt; + wire [1:80] lru_set_reset_vec_pt; + wire [1:15] lru_watermark_mask_pt; + wire [1:15] lru_way_encode_pt; + + + // Latch signals + wire [0:`THREADS-1] ex1_valid_d; + wire [0:`THREADS-1] ex1_valid_q; + wire [0:ttype_width-1] ex1_ttype_d; + wire [0:ttype_width-1] ex1_ttype_q; + wire [0:ws_width-1] ex1_ws_d; + wire [0:ws_width-1] ex1_ws_q; + wire [0:ra_entry_width-1] ex1_ra_entry_d; + wire [0:ra_entry_width-1] ex1_ra_entry_q; + wire [0:state_width-1] ex1_state_d; + wire [0:state_width-1] ex1_state_q; + wire [0:pid_width-1] ex1_pid_d; + wire [0:pid_width-1] ex1_pid_q; + reg [0:extclass_width-1] ex1_extclass_d; + wire [0:extclass_width-1] ex1_extclass_q; + reg [0:tlbsel_width-1] ex1_tlbsel_d; + wire [0:tlbsel_width-1] ex1_tlbsel_q; + + wire [0:`THREADS-1] ex2_valid_d; + wire [0:`THREADS-1] ex2_valid_q; + wire [0:ttype_width-1] ex2_ttype_d; + wire [0:ttype_width-1] ex2_ttype_q; + wire [0:ws_width-1] ex2_ws_d; + wire [0:ws_width-1] ex2_ws_q; + wire [0:ra_entry_width-1] ex2_ra_entry_d; + wire [0:ra_entry_width-1] ex2_ra_entry_q; + wire [0:state_width-1] ex2_state_d; + wire [0:state_width-1] ex2_state_q; + wire [0:pid_width-1] ex2_pid_d; + wire [0:pid_width-1] ex2_pid_q; + wire [0:extclass_width-1] ex2_extclass_d; + wire [0:extclass_width-1] ex2_extclass_q; + wire [0:tlbsel_width-1] ex2_tlbsel_d; + wire [0:tlbsel_width-1] ex2_tlbsel_q; + + wire [0:`THREADS-1] ex3_valid_d; + wire [0:`THREADS-1] ex3_valid_q; + wire [0:ttype_width-1] ex3_ttype_d; + wire [0:ttype_width-1] ex3_ttype_q; + wire [0:ws_width-1] ex3_ws_d; + wire [0:ws_width-1] ex3_ws_q; + wire [0:ra_entry_width-1] ex3_ra_entry_d; + wire [0:ra_entry_width-1] ex3_ra_entry_q; + wire [0:state_width-1] ex3_state_d; + wire [0:state_width-1] ex3_state_q; + wire [0:pid_width-1] ex3_pid_d; + wire [0:pid_width-1] ex3_pid_q; + wire [0:extclass_width-1] ex3_extclass_d; + wire [0:extclass_width-1] ex3_extclass_q; + wire [0:tlbsel_width-1] ex3_tlbsel_d; + wire [0:tlbsel_width-1] ex3_tlbsel_q; + wire [0:2+num_entry_log2-1] ex3_eratsx_data_d; + wire [0:2+num_entry_log2-1] ex3_eratsx_data_q; + + wire [0:`THREADS-1] ex4_valid_d; + wire [0:`THREADS-1] ex4_valid_q; + wire [0:ttype_width-1] ex4_ttype_d; + wire [0:ttype_width-1] ex4_ttype_q; + wire [0:ws_width-1] ex4_ws_d; + wire [0:ws_width-1] ex4_ws_q; + wire [0:ra_entry_width-1] ex4_ra_entry_d; + wire [0:ra_entry_width-1] ex4_ra_entry_q; + wire [0:state_width-1] ex4_state_d; + wire [0:state_width-1] ex4_state_q; + wire [0:pid_width-1] ex4_pid_d; + wire [0:pid_width-1] ex4_pid_q; + wire [0:extclass_width-1] ex4_extclass_d; + wire [0:extclass_width-1] ex4_extclass_q; + wire [0:tlbsel_width-1] ex4_tlbsel_d; + wire [0:tlbsel_width-1] ex4_tlbsel_q; + wire [64-data_out_width:63] ex4_data_out_d; + wire [64-data_out_width:63] ex4_data_out_q; + + wire [0:`THREADS-1] ex5_valid_d; + wire [0:`THREADS-1] ex5_valid_q; + wire [0:ttype_width-1] ex5_ttype_d; + wire [0:ttype_width-1] ex5_ttype_q; + wire [0:ws_width-1] ex5_ws_d; + wire [0:ws_width-1] ex5_ws_q; + wire [0:ra_entry_width-1] ex5_ra_entry_d; + wire [0:ra_entry_width-1] ex5_ra_entry_q; + wire [0:state_width-1] ex5_state_d; + wire [0:state_width-1] ex5_state_q; + wire [0:pid_width-1] ex5_pid_d; + wire [0:pid_width-1] ex5_pid_q; + wire [0:extclass_width-1] ex5_extclass_d; + wire [0:extclass_width-1] ex5_extclass_q; + wire [0:tlbsel_width-1] ex5_tlbsel_d; + wire [0:tlbsel_width-1] ex5_tlbsel_q; + wire [64-rs_data_width:63] ex5_data_in_d; + wire [64-rs_data_width:63] ex5_data_in_q; + + wire [0:`THREADS-1] ex6_valid_d; + wire [0:`THREADS-1] ex6_valid_q; + wire [0:ttype_width-1] ex6_ttype_d; + wire [0:ttype_width-1] ex6_ttype_q; + wire [0:ws_width-1] ex6_ws_d; + wire [0:ws_width-1] ex6_ws_q; + wire [0:ra_entry_width-1] ex6_ra_entry_d; + wire [0:ra_entry_width-1] ex6_ra_entry_q; + reg [0:state_width-1] ex6_state_d; + wire [0:state_width-1] ex6_state_q; + reg [0:pid_width-1] ex6_pid_d; + wire [0:pid_width-1] ex6_pid_q; + reg [0:extclass_width-1] ex6_extclass_d; + wire [0:extclass_width-1] ex6_extclass_q; + reg [0:tlbsel_width-1] ex6_tlbsel_d; + wire [0:tlbsel_width-1] ex6_tlbsel_q; + wire [64-rs_data_width:63] ex6_data_in_d; + wire [64-rs_data_width:63] ex6_data_in_q; + + wire [0:`THREADS-1] ex7_valid_d; + wire [0:`THREADS-1] ex7_valid_q; + wire [0:ttype_width-1] ex7_ttype_d; + wire [0:ttype_width-1] ex7_ttype_q; + wire [0:tlbsel_width-1] ex7_tlbsel_d; + wire [0:tlbsel_width-1] ex7_tlbsel_q; + + wire [0:`THREADS-1] iu1_valid_d; + wire [0:`THREADS-1] iu1_valid_q; + wire [0:state_width-1] iu1_state_d; + wire [0:state_width-1] iu1_state_q; + reg [0:pid_width-1] iu1_pid_d; + wire [0:pid_width-1] iu1_pid_q; + wire [0:`THREADS-1] iu2_valid_d; + wire [0:`THREADS-1] iu2_valid_q; + wire [0:`THREADS-1] iu2_perf_itlb_d, iu2_perf_itlb_q; + wire [0:state_width-1] iu2_state_d; + wire [0:state_width-1] iu2_state_q; + wire [0:pid_width-1] iu2_pid_d; + wire [0:pid_width-1] iu2_pid_q; + wire iu1_prefetch_d; + wire iu1_prefetch_q; + wire iu2_prefetch_d; + wire iu2_prefetch_q; + wire iu1_nonspec_d; + wire iu1_nonspec_q; + wire iu2_nonspec_d; + wire iu2_nonspec_q; + + (* NO_MODIFICATION="TRUE" *) + wire iu1_flush_enab_d; + wire iu1_flush_enab_q; + (* NO_MODIFICATION="TRUE" *) + wire [0:`THREADS-1] iu2_n_flush_req_d; + wire [0:`THREADS-1] iu2_n_flush_req_q; + (* NO_MODIFICATION="TRUE" *) + wire [0:`THREADS-1] hold_req_d; + wire [0:`THREADS-1] hold_req_q; + (* NO_MODIFICATION="TRUE" *) + wire [0:`THREADS-1] tlb_miss_d; + wire [0:`THREADS-1] tlb_miss_q; + (* NO_MODIFICATION="TRUE" *) + wire [0:`THREADS-1] tlb_flushed_d; + wire [0:`THREADS-1] tlb_flushed_q; + (* NO_MODIFICATION="TRUE" *) + wire [0:`THREADS-1] tlb_req_inprogress_d; + wire [0:`THREADS-1] tlb_req_inprogress_q; + + (* NO_MODIFICATION="TRUE" *) + wire iu2_tlbreq_d; + wire iu2_tlbreq_q; + wire [0:1] iu2_miss_d; + wire [0:1] iu2_miss_q; + wire [0:1] iu2_multihit_d; + wire [0:1] iu2_multihit_q; + wire [0:1] iu2_parerr_d; + wire [0:1] iu2_parerr_q; + wire [0:5] iu2_isi_d; + wire [0:5] iu2_isi_q; + wire [0:10] iu1_debug_d; + wire [0:10] iu1_debug_q; + wire [0:16] iu2_debug_d; + wire [0:16] iu2_debug_q; + + wire [1:num_entry] iu2_multihit_b_pt_d; + wire [1:num_entry] iu2_multihit_b_pt_q; + wire [1:num_entry-1] iu2_first_hit_entry_pt_d; + wire [1:num_entry-1] iu2_first_hit_entry_pt_q; + wire [0:cam_data_width-1] iu2_cam_cmp_data_d; + wire [0:cam_data_width-1] iu2_cam_cmp_data_q; + wire [0:array_data_width-1] iu2_array_cmp_data_d; + wire [0:array_data_width-1] iu2_array_cmp_data_q; + + wire [0:cam_data_width-1] ex4_rd_cam_data_d; + wire [0:cam_data_width-1] ex4_rd_cam_data_q; + wire [0:array_data_width-1] ex4_rd_array_data_d; + wire [0:array_data_width-1] ex4_rd_array_data_q; + + reg [0:2] por_seq_d; + wire [0:2] por_seq_q; + + wire [0:`THREADS] ex3_parerr_d; + wire [0:`THREADS] ex3_parerr_q; + wire [0:`THREADS+2] ex4_parerr_d; + wire [0:`THREADS+2] ex4_parerr_q; + + wire [0:`THREADS+num_entry_log2-1] ex4_ieen_d; + wire [0:`THREADS+num_entry_log2-1] ex4_ieen_q; + wire [0:`THREADS+num_entry_log2-1] ex5_ieen_d; + wire [0:`THREADS+num_entry_log2-1] ex5_ieen_q; + wire [0:`THREADS+num_entry_log2-1] ex6_ieen_d; + wire [0:`THREADS+num_entry_log2-1] ex6_ieen_q; + wire [0:8] mmucr1_d; + wire [0:8] mmucr1_q; + + wire [0:63] rpn_holdreg_d[0:`THREADS-1]; + wire [0:63] rpn_holdreg_q[0:`THREADS-1]; + reg [0:63] ex6_rpn_holdreg; + + wire [0:watermark_width-1] watermark_d; + wire [0:watermark_width-1] watermark_q; + wire [0:eptr_width-1] eptr_d; + wire [0:eptr_width-1] eptr_q; + wire [1:lru_width] lru_d; + wire [1:lru_width] lru_q; + wire [0:9] lru_update_event_d; + wire [0:9] lru_update_event_q; + wire [0:23] lru_debug_d; + wire [0:23] lru_debug_q; + + wire [0:2] snoop_val_d; + wire [0:2] snoop_val_q; + wire [0:25] snoop_attr_d; + wire [0:25] snoop_attr_q; + wire [52-epn_width:51] snoop_addr_d; + wire [52-epn_width:51] snoop_addr_q; + + wire [0:4] tlb_rel_val_d; // bit 4 is hit/miss + wire [0:4] tlb_rel_val_q; + wire [0:131] tlb_rel_data_d; // bit 65 is write enab + wire [0:131] tlb_rel_data_q; + wire [0:`THREADS-1] iu_mm_ierat_flush_d; // flush for ierat requests to mmu + wire [0:`THREADS-1] iu_mm_ierat_flush_q; + wire [0:`THREADS-1] iu_xu_ierat_ex2_flush_d; // flush for eratsx collision with I$ back_inv + wire [0:`THREADS-1] iu_xu_ierat_ex2_flush_q; + wire [0:9] ccr2_frat_paranoia_d; // bit9=enable, force ra=ea bypass + wire [0:9] ccr2_frat_paranoia_q; + wire ccr2_notlb_q; + wire xucr4_mmu_mchk_q; + wire [0:3] mchk_flash_inv_d; + wire [0:3] mchk_flash_inv_q; + wire mchk_flash_inv_enab; + + wire [0:31] spare_q; + + wire [0:bcfg_width-1] bcfg_q; // boot config ring values + wire [0:bcfg_width-1] bcfg_q_b; + + // logic signals + (* NO_MODIFICATION="TRUE" *) + wire iu2_isi_sig; + (* NO_MODIFICATION="TRUE" *) + wire iu2_miss_sig; + (* NO_MODIFICATION="TRUE" *) + wire iu2_parerr_sig; + (* NO_MODIFICATION="TRUE" *) + wire iu2_multihit_sig; + (* NO_MODIFICATION="TRUE" *) + wire iu1_multihit; + (* NO_MODIFICATION="TRUE" *) + wire iu1_multihit_b; + (* NO_MODIFICATION="TRUE" *) + wire [0:num_entry_log2-1] iu1_first_hit_entry; + (* NO_MODIFICATION="TRUE" *) + wire [0:num_entry_log2-1] iu2_first_hit_entry; + (* NO_MODIFICATION="TRUE" *) + wire iu2_multihit_enab; + (* NO_MODIFICATION="TRUE" *) + reg [0:1] por_wr_cam_val; + (* NO_MODIFICATION="TRUE" *) + reg [0:1] por_wr_array_val; + (* NO_MODIFICATION="TRUE" *) + reg [0:cam_data_width-1] por_wr_cam_data; + (* NO_MODIFICATION="TRUE" *) + reg [0:array_data_width-1] por_wr_array_data; + (* NO_MODIFICATION="TRUE" *) + reg [0:num_entry_log2-1] por_wr_entry; + (* NO_MODIFICATION="TRUE" *) + reg [0:`THREADS-1] por_hold_req; + (* NO_MODIFICATION="TRUE" *) + wire [0:num_entry_log2-1] lru_way_encode; + (* NO_MODIFICATION="TRUE" *) + wire [0:lru_width] lru_rmt_vec; + (* NO_MODIFICATION="TRUE" *) + wire [1:lru_width] lru_reset_vec; + (* NO_MODIFICATION="TRUE" *) + wire [1:lru_width] lru_set_vec; + wire [1:lru_width] lru_op_vec; + wire [1:lru_width] lru_vp_vec; + (* NO_MODIFICATION="TRUE" *) + wire [1:lru_width] lru_eff; + wire [0:lru_width] lru_watermark_mask; + wire [0:lru_width] entry_valid_watermarked; + + wire [0:eptr_width-1] eptr_p1; + wire ex1_ieratre; + wire ex1_ieratwe; + wire ex1_ieratsx; + wire ex3_parerr_enab; + wire ex4_parerr_enab; + wire ex3_ieratwe; + wire ex4_ieratwe; + wire ex5_ieratwe; + wire ex6_ieratwe; + wire ex7_ieratwe; + wire ex5_ieratwe_ws0; + wire ex6_ieratwe_ws3; + + (* NO_MODIFICATION="TRUE" *) + wire [50:67] iu2_cmp_data_calc_par; // bit 50 is cmp/x mask parity on epn side + + (* NO_MODIFICATION="TRUE" *) + wire iu2_cmp_data_parerr_epn; + (* NO_MODIFICATION="TRUE" *) + wire iu2_cmp_data_parerr_rpn; + (* NO_MODIFICATION="TRUE" *) + wire [50:67] ex4_rd_data_calc_par; // bit 50 is cmp/x mask parity on epn side + (* NO_MODIFICATION="TRUE" *) + wire ex4_rd_data_parerr_epn; + (* NO_MODIFICATION="TRUE" *) + wire ex4_rd_data_parerr_rpn; + + (* analysis_not_referenced="true" *) + wire [0:29] unused_dc; + + + wire [0:19] ierat_mmucr0[0:`THREADS-1]; + wire [0:`THREADS-1] mmucr0_gs_vec; + wire [0:`THREADS-1] mmucr0_ts_vec; + wire [0:13] ierat_pid[0:`THREADS-1]; + + wire [0:3] tlb_rel_cmpmask; + wire [0:3] tlb_rel_xbitmask; + wire tlb_rel_maskpar; + wire [0:3] ex6_data_cmpmask; + wire [0:3] ex6_data_xbitmask; + wire ex6_data_maskpar; + + wire [0:51] comp_addr_mux1; + wire comp_addr_mux1_sel; + wire lru_way_is_written; + wire lru_way_is_hit_entry; + + // Added for timing changes + reg [0:pid_width-1] ex1_pid_0; + reg [0:pid_width-1] ex1_pid_1; + + + // CAM/Array signals + // Read Port + (* NO_MODIFICATION="TRUE" *) + wire rd_val; + (* NO_MODIFICATION="TRUE" *) + wire [0:3] rw_entry; + // Write Port + (* NO_MODIFICATION="TRUE" *) + wire [51:67] wr_array_par; + (* NO_MODIFICATION="TRUE" *) + wire [0:array_data_width-1-10-7] wr_array_data_nopar; + (* NO_MODIFICATION="TRUE" *) + wire [0:array_data_width-1] wr_array_data; + (* NO_MODIFICATION="TRUE" *) + wire [0:cam_data_width-1] wr_cam_data; + (* NO_MODIFICATION="TRUE" *) + wire [0:1] wr_array_val; + (* NO_MODIFICATION="TRUE" *) + wire [0:1] wr_cam_val; + (* NO_MODIFICATION="TRUE" *) + wire wr_val_early; // act pin for write port + // CAM Port + (* NO_MODIFICATION="TRUE" *) + wire comp_request; + (* NO_MODIFICATION="TRUE" *) + wire [0:51] comp_addr; + (* NO_MODIFICATION="TRUE" *) + wire [0:1] addr_enable; + (* NO_MODIFICATION="TRUE" *) + wire [0:2] comp_pgsize; + (* NO_MODIFICATION="TRUE" *) + wire pgsize_enable; + (* NO_MODIFICATION="TRUE" *) + wire [0:1] comp_class; + (* NO_MODIFICATION="TRUE" *) + wire [0:2] class_enable; + (* NO_MODIFICATION="TRUE" *) + wire [0:1] comp_extclass; + (* NO_MODIFICATION="TRUE" *) + wire [0:1] extclass_enable; + (* NO_MODIFICATION="TRUE" *) + wire [0:1] comp_state; + (* NO_MODIFICATION="TRUE" *) + wire [0:1] state_enable; + (* NO_MODIFICATION="TRUE" *) + wire [0:3] comp_thdid; + (* NO_MODIFICATION="TRUE" *) + wire [0:1] thdid_enable; + (* NO_MODIFICATION="TRUE" *) + wire [0:7] comp_pid; + (* NO_MODIFICATION="TRUE" *) + wire pid_enable; + (* NO_MODIFICATION="TRUE" *) + wire comp_invalidate; + (* NO_MODIFICATION="TRUE" *) + wire flash_invalidate; + // Array Outputs + (* NO_MODIFICATION="TRUE" *) + wire [0:array_data_width-1] array_cmp_data; + (* NO_MODIFICATION="TRUE" *) + wire [0:array_data_width-1] rd_array_data; + // CAM Outputs + (* NO_MODIFICATION="TRUE" *) + wire [0:cam_data_width-1] cam_cmp_data; + (* NO_MODIFICATION="TRUE" *) + wire cam_hit; + (* NO_MODIFICATION="TRUE" *) + wire [0:3] cam_hit_entry; + (* NO_MODIFICATION="TRUE" *) + wire [0:15] entry_match; + wire [0:15] entry_match_q; + (* NO_MODIFICATION="TRUE" *) + wire [0:15] entry_valid; + wire [0:15] entry_valid_q; + (* NO_MODIFICATION="TRUE" *) + wire [0:cam_data_width-1] rd_cam_data; + + + wire [0:2] cam_pgsize; + wire [0:3] ws0_pgsize; + + // new cam _np2 signals + wire bypass_mux_enab_np1; + wire [0:20] bypass_attr_np1; + wire [0:20] attr_np2; + wire [22:51] rpn_np2; + + // Pervasive + wire pc_sg_1; + wire pc_sg_0; + wire pc_func_sl_thold_1; + wire pc_func_sl_thold_0; + wire pc_func_sl_thold_0_b; + wire pc_func_slp_sl_thold_1; + wire pc_func_slp_sl_thold_0; + wire pc_func_slp_sl_thold_0_b; + wire pc_func_sl_force; + wire pc_func_slp_sl_force; + wire pc_cfg_slp_sl_thold_1; + wire pc_cfg_slp_sl_thold_0; + wire pc_cfg_slp_sl_thold_0_b; + wire pc_cfg_slp_sl_force; + wire lcb_dclk; + wire [0:`NCLK_WIDTH-1] lcb_lclk; + wire init_alias; + + // Clock Gating + wire iu1_stg_act_d; + wire iu1_stg_act_q; + wire iu2_stg_act_d; + wire iu2_stg_act_q; + wire iu3_stg_act_d; + wire iu3_stg_act_q; + wire ex1_stg_act_d; + wire ex1_stg_act_q; + wire ex2_stg_act_d; + wire ex2_stg_act_q; + wire ex3_stg_act_d; + wire ex3_stg_act_q; + wire ex4_stg_act_d; + wire ex4_stg_act_q; + wire ex5_stg_act_d; + wire ex5_stg_act_q; + wire ex6_stg_act_d; + wire ex6_stg_act_q; + wire ex7_stg_act_d; + wire ex7_stg_act_q; + wire iu1_cmp_data_act; + wire iu1_grffence_act; + wire iu1_or_iu2_grffence_act; + wire iu2_or_iu3_grffence_act; + wire ex3_rd_data_act; + wire ex3_data_out_act; + wire ex2_grffence_act; + wire ex3_grffence_act; + wire an_ac_grffence_en_dc_q; + wire trace_bus_enable_q; + wire entry_valid_act; + wire entry_match_act; + wire not_grffence_act; + wire notlb_grffence_act; + wire tlb_rel_act_d; + wire tlb_rel_act_q; + wire tlb_rel_act; + wire snoop_act_q; + wire iu_pc_err_ierat_multihit_d; + wire iu_pc_err_ierat_multihit_q; + wire iu_pc_err_ierat_parity_d; + wire iu_pc_err_ierat_parity_q; + wire lru_update_act; + wire debug_grffence_act; + wire eratsx_data_act; + wire iu_xu_ord_write_done_d, iu_xu_ord_write_done_q; + wire iu_xu_ord_read_done_d, iu_xu_ord_read_done_q; + wire iu_xu_ord_par_err_d, iu_xu_ord_par_err_q; + wire [0:3] cp_ic_csinv_comp_d; + wire [0:3] cp_ic_csinv_comp_q; + wire csinv_complete; + + wire [0:scan_right_0] siv_0; + wire [0:scan_right_0] sov_0; + wire [0:scan_right_1] siv_1; + wire [0:scan_right_1] sov_1; + wire [0:boot_scan_right] bsiv; + wire [0:boot_scan_right] bsov; + + wire tiup; + + //@@ START OF EXECUTABLE CODE FOR IUQ_IC_IERAT + + //## figtree_source: iuq_ic_ierat.fig; + + // ttype <= 0:eratre & 1:eratwe & 2:eratsx & 3:eratilx & 4:csync & 5:isync; + // ERAT Operation is Complete + assign iu_xu_ord_write_done_d = (|(ex4_valid_q & (~(xu_iu_flush)))) & (ex4_ttype_q[0] | ex4_ttype_q[2]); // ERATRE/ERATSX Completed + assign iu_xu_ord_read_done_d = (|(ex4_valid_q & (~(xu_iu_flush)))) & ex4_ttype_q[1]; + assign iu_xu_ord_write_done = iu_xu_ord_write_done_q; + assign iu_xu_ord_read_done = iu_xu_ord_read_done_q; + + //--------------------------------------------------------------------- + // ACT Generation + //--------------------------------------------------------------------- + + assign iu1_stg_act_d = comp_request | spr_ic_clockgate_dis; + assign iu2_stg_act_d = iu1_stg_act_q; + assign iu3_stg_act_d = iu2_stg_act_q; + + assign ex1_stg_act_d = (|(xu_iu_val)) | spr_ic_clockgate_dis; + assign ex2_stg_act_d = ex1_stg_act_q; + assign ex3_stg_act_d = ex2_stg_act_q; + assign ex4_stg_act_d = ex3_stg_act_q; + assign ex5_stg_act_d = ex4_stg_act_q; + assign ex6_stg_act_d = ex5_stg_act_q; + assign ex7_stg_act_d = ex6_stg_act_q; + + assign iu1_cmp_data_act = iu1_stg_act_q & (~(an_ac_grffence_en_dc)); + assign iu1_grffence_act = iu1_stg_act_q & (~(an_ac_grffence_en_dc)); + assign iu1_or_iu2_grffence_act = (iu1_stg_act_q | iu2_stg_act_q) & (~(an_ac_grffence_en_dc)); + assign iu2_or_iu3_grffence_act = (iu2_stg_act_q | iu3_stg_act_q) & (~(an_ac_grffence_en_dc)); + + assign ex2_grffence_act = ex2_stg_act_q & (~(an_ac_grffence_en_dc)); + + assign ex3_rd_data_act = ex3_stg_act_q & (~(an_ac_grffence_en_dc)); + assign ex3_data_out_act = ex3_stg_act_q & (~(an_ac_grffence_en_dc)); + assign ex3_grffence_act = ex3_stg_act_q & (~(an_ac_grffence_en_dc)); + + assign entry_valid_act = (~an_ac_grffence_en_dc); + assign entry_match_act = (~an_ac_grffence_en_dc); + assign not_grffence_act = (~an_ac_grffence_en_dc); + + assign lru_update_act = ex6_stg_act_q | ex7_stg_act_q | lru_update_event_q[4] | lru_update_event_q[8] | flash_invalidate | ex6_ieratwe_ws3; + assign notlb_grffence_act = ((~(ccr2_notlb_q)) | spr_ic_clockgate_dis) & (~(an_ac_grffence_en_dc)); + assign debug_grffence_act = trace_bus_enable_q & (~(an_ac_grffence_en_dc)); + assign eratsx_data_act = (iu1_stg_act_q | ex2_stg_act_q) & (~(an_ac_grffence_en_dc)); + + //--------------------------------------------------------------------- + // Logic + //--------------------------------------------------------------------- + //tidn <= '0'; + assign tiup = 1'b1; + assign init_alias = pc_iu_init_reset; // high active + + // timing latches for the reloads + assign tlb_rel_val_d = mm_iu_ierat_rel_val; // std_ulogic_vector(0 to 4); -- bit 4 is hit/miss + assign tlb_rel_data_d = mm_iu_ierat_rel_data; //std_ulogic_vector(0 to 131); + assign tlb_rel_act_d = mm_iu_ierat_rel_data[eratpos_relsoon]; // reload coming from tlb, asserted tag0 thru tag6 in tlb + assign tlb_rel_act = (tlb_rel_act_q & (~(ccr2_notlb_q))); // reload coming from tlb, gated with notlb + + // timing latches for the ifrat delusional paranoia real mode + assign ccr2_frat_paranoia_d[0:8] = xu_iu_spr_ccr2_ifratsc; + assign ccr2_frat_paranoia_d[9] = xu_iu_spr_ccr2_ifrat; // enable paranoia + + assign cp_ic_csinv_comp_d[0] = cp_ic_is_csync; // this is iuq_cpl csync complete pulse, qualified with valid + assign cp_ic_csinv_comp_d[1] = cp_ic_is_isync; // this is iuq_cpl isync complete pulse, qualified with valid + + // mmucr1_q: 0-IRRE, 1-REE, 2-CEE, 3-csync_dis, 4-isync_dis, 5:6-IPEI, 7:8-ICTID/ITTID + assign cp_ic_csinv_comp_d[2] = ((mmucr1_q[3] == 1'b0) & (ccr2_notlb_q == MMU_Mode_Value)) ? cp_ic_csinv_comp_q[0] : // mmu mode, csync allowed + 1'b0; + assign cp_ic_csinv_comp_d[3] = ((mmucr1_q[4] == 1'b0) & (ccr2_notlb_q == MMU_Mode_Value)) ? cp_ic_csinv_comp_q[1] : // mmu mode, isync allowed + 1'b0; + + //------------------------------------------------ + assign ex1_valid_d = xu_iu_val & (~(xu_rf1_flush)); + assign ex1_ttype_d[0:ttype_width - 1] = {xu_iu_is_eratre, xu_iu_is_eratwe, xu_iu_is_eratsx}; + assign ex1_ws_d = xu_iu_ws; + assign ex1_ra_entry_d = {ra_entry_width{1'b0}}; + + assign ierat_mmucr0[0] = mm_iu_t0_ierat_mmucr0; + assign mmucr0_gs_vec[0] = mm_iu_t0_ierat_mmucr0[2]; + assign mmucr0_ts_vec[0] = mm_iu_t0_ierat_mmucr0[3]; + assign ierat_pid[0] = mm_iu_t0_ierat_pid; + + `ifndef THREADS1 + assign ierat_mmucr0[1] = mm_iu_t1_ierat_mmucr0; + assign mmucr0_gs_vec[1] = mm_iu_t1_ierat_mmucr0[2]; + assign mmucr0_ts_vec[1] = mm_iu_t1_ierat_mmucr0[3]; + assign ierat_pid[1] = mm_iu_t1_ierat_pid; + `endif + + //always @(ierat_mmucr0 or ierat_pid or rpn_holdreg_q or xu_iu_val or ex6_valid_q or iu_ierat_iu0_thdid) + always @ (*) + begin: tidSpr + reg [0:13] pid_0; + reg [0:13] pid_1; + reg [0:1] extclass; + reg [0:1] tlbsel; + reg [0:63] rpnHold; + reg [0:13] iu1_pid; + //(* analysis_not_referenced="true" *) + integer tid; + + pid_0 = 14'b0; + pid_1 = 14'b0; + extclass = 2'b0; + tlbsel = 2'b0; + rpnHold = 64'b0; + iu1_pid = 14'b0; + for (tid = 0; tid <= `THREADS - 1; tid = tid + 1) + begin + pid_0 = (ierat_mmucr0[tid][6:19] & {14{xu_iu_val[tid]}}) | pid_0; + pid_1 = (ierat_pid[tid] & {14{xu_iu_val[tid]}}) | pid_1; + extclass = (ierat_mmucr0[tid][0:1] & { 2{xu_iu_val[tid]}}) | extclass; + tlbsel = (ierat_mmucr0[tid][4:5] & { 2{xu_iu_val[tid]}}) | tlbsel; + rpnHold = (rpn_holdreg_q[tid] & {64{ex6_valid_q[tid]}}) | rpnHold; + iu1_pid = (ierat_pid[tid] & {14{iu_ierat_iu0_thdid[tid]}}) | iu1_pid; + end + ex1_pid_0 = pid_0; + ex1_pid_1 = pid_1; + ex1_extclass_d = extclass; + ex1_tlbsel_d = tlbsel; + ex6_rpn_holdreg = rpnHold; + iu1_pid_d = iu1_pid; + end + + assign iu1_nonspec_d = iu_ierat_iu0_nonspec; + assign iu1_prefetch_d = iu_ierat_iu0_prefetch; + + // state: 0:pr 1:hs 2:ds 3:cm + assign ex1_state_d[0] = |(xu_iu_msr_pr & xu_iu_val); + assign ex1_state_d[1] = ((|(xu_iu_msr_hv & xu_iu_val)) & (~xu_iu_is_eratsx)) | + ((|(mmucr0_gs_vec & xu_iu_val)) & xu_iu_is_eratsx); + assign ex1_state_d[2] = ((|(xu_iu_msr_is & xu_iu_val)) & (~xu_iu_is_eratsx)) | + ((|(mmucr0_ts_vec & xu_iu_val)) & xu_iu_is_eratsx); + assign ex1_state_d[3] = |(xu_iu_msr_cm & xu_iu_val); + + //----------------------------------------- + + // mmucr0: 0:1-ECL|TID_NZ, 2:3-tgs/ts, 4:5-tlbsel, 6:19-tid, + + assign ex1_pid_d = (xu_iu_is_eratsx == 1'b1) ? ex1_pid_0 : + ex1_pid_1; + + assign iu2_nonspec_d = iu1_nonspec_q; + assign iu2_prefetch_d = iu1_prefetch_q; + + assign ex1_ieratre = (|(ex1_valid_q[0:`THREADS - 1])) & ex1_ttype_q[0] & ex1_tlbsel_q[0] & (~ex1_tlbsel_q[1]); + assign ex1_ieratwe = (|(ex1_valid_q[0:`THREADS - 1])) & ex1_ttype_q[1] & ex1_tlbsel_q[0] & (~ex1_tlbsel_q[1]); + assign ex1_ieratsx = (|(ex1_valid_q[0:`THREADS - 1])) & ex1_ttype_q[2] & ex1_tlbsel_q[0] & (~ex1_tlbsel_q[1]); + + //------------------------------------------------ + assign ex2_valid_d = ex1_valid_q & (~(xu_ex1_flush)); + assign ex2_ttype_d = ex1_ttype_q; + assign ex2_ws_d = ex1_ws_q; + assign ex2_ra_entry_d = xu_iu_ra_entry; + assign ex2_state_d = ex1_state_q; + assign ex2_pid_d = ex1_pid_q; + assign ex2_extclass_d = ex1_extclass_q; + assign ex2_tlbsel_d = ex1_tlbsel_q; + + //------------------------------------------------ + assign ex3_valid_d = ex2_valid_q & (~(xu_ex2_flush)) & (~(iu_xu_ierat_ex2_flush_q)); + assign ex3_ra_entry_d = (ex2_ttype_q[2] == 1'b1) ? iu1_first_hit_entry : // eratsx + ex2_ra_entry_q; + assign ex3_ttype_d = ex2_ttype_q; + assign ex3_ws_d = ex2_ws_q; + assign ex3_tlbsel_d = ex2_tlbsel_q; + assign ex3_extclass_d = ex2_extclass_q; + // state: 0:pr 1:hs 2:ds 3:cm + assign ex3_state_d = ex2_state_q; + assign ex3_pid_d = ex2_pid_q; + + assign ex3_ieratwe = (|(ex3_valid_q)) & ex3_ttype_q[1] & ex3_tlbsel_q[0] & (~ex3_tlbsel_q[1]); + + //------------------------------------------------ + assign ex4_valid_d = ex3_valid_q & (~(xu_ex3_flush)); + assign ex4_ttype_d = ex3_ttype_q; + assign ex4_ws_d = ex3_ws_q; + assign ex4_ra_entry_d = ex3_ra_entry_q; + assign ex4_tlbsel_d = ex3_tlbsel_q; + // muxes for eratre and sending mmucr0 ExtClass,State,TID + assign ex4_extclass_d = ((|(ex3_valid_q)) == 1'b1 & ex3_ttype_q[0] == 1'b1 & ex3_ws_q == 2'b00) ? rd_cam_data[63:64] : // eratre, WS=0 + ex3_extclass_q; + // state: 0:pr 1:hs 2:ds 3:cm + assign ex4_state_d = ((|(ex3_valid_q)) == 1'b1 & ex3_ttype_q[0] == 1'b1 & ex3_ws_q == 2'b00) ? {ex3_state_q[0], rd_cam_data[65:66], ex3_state_q[3]} : // eratre, WS=0 + ex3_state_q; + assign ex4_pid_d = ((|(ex3_valid_q)) == 1'b1 & ex3_ttype_q[0] == 1'b1 & ex3_ws_q == 2'b00) ? {rd_cam_data[61:62], rd_cam_data[57:60], rd_cam_data[67:74]} : // class | thdid | tid -> 14-bit tid // eratre, WS=0 + ex3_pid_q; + assign ex4_ieratwe = (|(ex4_valid_q)) & ex4_ttype_q[1] & ex4_tlbsel_q[0] & (~ex4_tlbsel_q[1]); + + //------------------------------------------------ + assign ex5_valid_d = ex4_valid_q & (~(xu_ex4_flush)); + assign ex5_ws_d = ex4_ws_q; + assign ex5_ra_entry_d = ex4_ra_entry_q; + + // ttype <= 0:eratre & 1:eratwe & 2:eratsx & 3:eratilx & 4:csync & 5:isync; + assign ex5_ttype_d = ex4_ttype_q; + + // mmucr0: 0:1-ECL|TID_NZ, 2:3-tgs/ts, 4:5-tlbsel, 6:19-tid, + assign ex5_extclass_d = ex4_extclass_q; + + // state: 0:pr 1:hs 2:ds 3:cm + assign ex5_state_d = ex4_state_q; + assign ex5_pid_d = ex4_pid_q; + assign ex5_tlbsel_d = ex4_tlbsel_q; + + assign ex5_data_in_d = xu_iu_rs_data; + + assign ex5_ieratwe = (|(ex5_valid_q)) & ex5_ttype_q[1] & ex5_tlbsel_q[0] & (~ex5_tlbsel_q[1]); + assign ex5_ieratwe_ws0 = (|(ex5_valid_q)) & ex5_ttype_q[1] & ex5_tlbsel_q[0] & (~ex5_tlbsel_q[1]) & (~|(ex5_ws_q)); + + //------------------------------------------------ + assign ex6_valid_d = ex5_valid_q & (~(xu_ex5_flush)); + assign ex6_ws_d = ex5_ws_q; + assign ex6_ra_entry_d = ex5_ra_entry_q; + + assign ex6_ttype_d = ex5_ttype_q; + + //always @(ex5_valid_q or ex5_ieratwe_ws0 or ierat_mmucr0 or mmucr0_gs_vec or mmucr0_ts_vec or xu_iu_msr_pr or //xu_iu_msr_cm or ex5_extclass_q or ex5_state_q or ex5_pid_q or ex5_tlbsel_q) + always @ (*) + begin: tidEx6 + reg [0:13] pid; + reg [0:3] state; + reg [0:1] extclass; + reg [0:1] tlbsel; + //(* analysis_not_referenced="true" *) + integer tid; + + pid = 14'b0; + state = 4'b0; + extclass = 2'b0; + tlbsel = 2'b0; + // mmucr0: 0:1-ECL|TID_NZ, 2:3-tgs/ts, 4:5-tlbsel, 6:19-tid, + // state: 0:pr 1:hs 2:ds 3:cm + for (tid = 0; tid <= `THREADS - 1; tid = tid + 1) + begin + extclass = (ierat_mmucr0[tid][0:1] & {2{ex5_valid_q[tid]}}) | extclass; + state = ({xu_iu_msr_pr[tid], mmucr0_gs_vec[tid], mmucr0_ts_vec[tid], xu_iu_msr_cm[tid]} & {4{ex5_valid_q[tid]}}) | state; + tlbsel = (ierat_mmucr0[tid][4:5] & {2{ex5_valid_q[tid]}}) | tlbsel; + pid = (ierat_mmucr0[tid][6:19] & {14{ex5_valid_q[tid]}}) | pid; + end + ex6_extclass_d = (extclass & {2{ex5_ieratwe_ws0}}) | (ex5_extclass_q & {2{~(ex5_ieratwe_ws0)}}); + ex6_state_d = (state & {4{ex5_ieratwe_ws0}}) | (ex5_state_q & {4{~(ex5_ieratwe_ws0)}}); + ex6_pid_d = (pid & {14{ex5_ieratwe_ws0}}) | (ex5_pid_q & {14{~(ex5_ieratwe_ws0)}}); + ex6_tlbsel_d = (tlbsel & {2{ex5_ieratwe_ws0}}) | (ex5_tlbsel_q & {2{~(ex5_ieratwe_ws0)}}); + end + + assign ex6_data_in_d = ex5_data_in_q; + + assign ex6_ieratwe = (|(ex6_valid_q)) & ex6_ttype_q[1] & ex6_tlbsel_q[0] & (~ex6_tlbsel_q[1]); + + //------------------------------------------------ + // for flushing + assign ex7_valid_d = ex6_valid_q; + assign ex7_ttype_d = ex6_ttype_q; + assign ex7_tlbsel_d = ex6_tlbsel_q; + + assign ex7_ieratwe = (|(ex7_valid_q)) & ex7_ttype_q[1] & ex7_tlbsel_q[0] & (~ex7_tlbsel_q[1]); + + // adding local iu2 flush request for timing + assign iu1_valid_d = iu_ierat_iu0_thdid & {`THREADS{iu_ierat_iu0_val}} & (~(iu_ierat_iu0_flush)) & (~(xu_iu_flush | br_iu_flush)) & (~(iu2_n_flush_req_q)); + + // state: 0:pr 1:hs 2:ds 3:cm + assign iu1_state_d[0] = |(xu_iu_msr_pr & iu_ierat_iu0_thdid); + assign iu1_state_d[1] = |(xu_iu_msr_hv & iu_ierat_iu0_thdid); + assign iu1_state_d[2] = |(xu_iu_msr_is & iu_ierat_iu0_thdid); + assign iu1_state_d[3] = |(xu_iu_msr_cm & iu_ierat_iu0_thdid); + + // adding local iu2 flush request for timing + assign iu2_valid_d = iu1_valid_q & (~(iu_ierat_iu1_flush)) & (~(xu_iu_flush | br_iu_flush)) & (~(iu2_n_flush_req_q)); + assign iu2_state_d = iu1_state_q; + assign iu2_pid_d = iu1_pid_q; + + assign iu_mm_ierat_flush_d = iu_ierat_iu1_flush; + + assign mmucr1_d = mm_iu_ierat_mmucr1; + +// formation of iu1 phase multihit complement signal +/* +//table_start +?TABLE iu1_multihit_b LISTING(final) OPTIMIZE PARMS(ON-SET); +*INPUTS*==============*OUTPUTS*==========* +| | | +| entry_match | iu1_multihit_b | +| | | | | +| | | | | +| | | | | +| | 111111 | | | +| 0123456789012345 | | | +*TYPE*================+==================+ +| PPPPPPPPPPPPPPPP | P | +*OPTIMIZE*----------->| A | +*TERMS*===============+==================+ +| 0000000000000000 | 1 | no hit +| 1000000000000000 | 1 | exactly one hit +| 0100000000000000 | 1 | exactly one hit +| 0010000000000000 | 1 | exactly one hit +| 0001000000000000 | 1 | exactly one hit +| 0000100000000000 | 1 | exactly one hit +| 0000010000000000 | 1 | exactly one hit +| 0000001000000000 | 1 | exactly one hit +| 0000000100000000 | 1 | exactly one hit +| 0000000010000000 | 1 | exactly one hit +| 0000000001000000 | 1 | exactly one hit +| 0000000000100000 | 1 | exactly one hit +| 0000000000010000 | 1 | exactly one hit +| 0000000000001000 | 1 | exactly one hit +| 0000000000000100 | 1 | exactly one hit +| 0000000000000010 | 1 | exactly one hit +| 0000000000000001 | 1 | exactly one hit +*END*=================+==================+ +?TABLE END iu1_multihit_b; +//table_end +*/ + + + assign iu1_multihit = (~iu1_multihit_b); + assign iu2_multihit_b_pt_d = iu1_multihit_b_pt; + assign iu2_multihit_enab = (~|(iu2_multihit_b_pt_q)); + + +// Encoder for the iu1 phase first hit entry number +/* +//table_start +?TABLE iu1_first_hit_entry LISTING(final) OPTIMIZE PARMS(ON-SET); +*INPUTS*==============*OUTPUTS*==============* +| | | +| entry_match | iu1_first_hit_entry | +| | | | | +| | | | | +| | | | | +| | 111111 | | | +| 0123456789012345 | 0123 | +*TYPE*================+======================+ +| PPPPPPPPPPPPPPPP | PPPP | +*OPTIMIZE*----------->| AAAA | +*TERMS*===============+======================+ +| 1--------------- | 0000 | +| 01-------------- | 0001 | +| 001------------- | 0010 | +| 0001------------ | 0011 | +| 00001----------- | 0100 | +| 000001---------- | 0101 | +| 0000001--------- | 0110 | +| 00000001-------- | 0111 | +| 000000001------- | 1000 | +| 0000000001------ | 1001 | +| 00000000001----- | 1010 | +| 000000000001---- | 1011 | +| 0000000000001--- | 1100 | +| 00000000000001-- | 1101 | +| 000000000000001- | 1110 | +| 0000000000000001 | 1111 | +*END*=================+======================+ +?TABLE END iu1_first_hit_entry; +//table_end +*/ + + assign iu2_first_hit_entry_pt_d = iu1_first_hit_entry_pt; + assign iu2_first_hit_entry[0] = (iu2_first_hit_entry_pt_q[1] | iu2_first_hit_entry_pt_q[2] | iu2_first_hit_entry_pt_q[3] | iu2_first_hit_entry_pt_q[4] | iu2_first_hit_entry_pt_q[5] | iu2_first_hit_entry_pt_q[6] | iu2_first_hit_entry_pt_q[7] | iu2_first_hit_entry_pt_q[8]); + assign iu2_first_hit_entry[1] = (iu2_first_hit_entry_pt_q[1] | iu2_first_hit_entry_pt_q[2] | iu2_first_hit_entry_pt_q[3] | iu2_first_hit_entry_pt_q[4] | iu2_first_hit_entry_pt_q[9] | iu2_first_hit_entry_pt_q[10] | iu2_first_hit_entry_pt_q[11] | iu2_first_hit_entry_pt_q[12]); + assign iu2_first_hit_entry[2] = (iu2_first_hit_entry_pt_q[1] | iu2_first_hit_entry_pt_q[2] | iu2_first_hit_entry_pt_q[5] | iu2_first_hit_entry_pt_q[6] | iu2_first_hit_entry_pt_q[9] | iu2_first_hit_entry_pt_q[10] | iu2_first_hit_entry_pt_q[13] | iu2_first_hit_entry_pt_q[14]); + assign iu2_first_hit_entry[3] = (iu2_first_hit_entry_pt_q[1] | iu2_first_hit_entry_pt_q[3] | iu2_first_hit_entry_pt_q[5] | iu2_first_hit_entry_pt_q[7] | iu2_first_hit_entry_pt_q[9] | iu2_first_hit_entry_pt_q[11] | iu2_first_hit_entry_pt_q[13] | iu2_first_hit_entry_pt_q[15]); + + assign iu2_cam_cmp_data_d = cam_cmp_data; + assign iu2_array_cmp_data_d = array_cmp_data; + + assign iu2_miss_d[0] = ( (|(iu1_valid_q & (~(iu_ierat_iu1_flush)) & (~(xu_iu_flush | br_iu_flush)) & (~(iu2_n_flush_req_q)))) & + (~iu1_flush_enab_q) & (~ccr2_frat_paranoia_q[9]) & (~iu_ierat_iu1_back_inv) ); + assign iu2_miss_d[1] = (~cam_hit); + assign iu2_miss_sig = iu2_miss_q[0] & iu2_miss_q[1]; + + assign iu2_multihit_d[0] = (cam_hit & iu1_multihit & + (|(iu1_valid_q & (~(iu_ierat_iu1_flush)) & (~(xu_iu_flush | br_iu_flush)) & (~(iu2_n_flush_req_q)))) & + (~iu1_flush_enab_q) & (~ccr2_frat_paranoia_q[9])); + assign iu2_multihit_d[1] = iu1_multihit; + assign iu2_multihit_sig = iu2_multihit_q[0] & iu2_multihit_q[1]; + + assign iu2_parerr_d[0] = (cam_hit & iu1_multihit_b & + (|(iu1_valid_q & (~(iu_ierat_iu1_flush)) & (~(xu_iu_flush | br_iu_flush)) & (~(iu2_n_flush_req_q)))) & + (~iu1_flush_enab_q) & (~ccr2_frat_paranoia_q[9])); // txlate parity error + assign iu2_parerr_d[1] = (cam_hit & iu1_multihit_b & + (|(iu1_valid_q & (~(iu_ierat_iu1_flush)) & (~(xu_iu_flush | br_iu_flush)) & (~(iu2_n_flush_req_q)))) & + (~iu1_flush_enab_q) & (~ccr2_frat_paranoia_q[9])); // txlate parity error + assign iu2_parerr_sig = (iu2_parerr_q[0] & iu2_cmp_data_parerr_epn) | // txlate epn parity error + (iu2_parerr_q[1] & iu2_cmp_data_parerr_rpn); + + // 16x143 version, 42b RA + // wr_array_data + // 0:29 - RPN + // 30:31 - R,C + // 32:33 - WLC + // 34 - ResvAttr + // 35 - VF + // 36:39 - U0-U3 + // 40:44 - WIMGE + // attribute re-ordering + // 45:46 - UX,SX + // 47:48 - UW,SW + // 49:50 - UR,SR + // 51:60 - CAM parity + // 61:67 - Array parity + + // mmucr1_q: 0-IRRE, 1-REE, 2-CEE, 3-csync_dis, 4-isync_dis, 5:6-IPEI, 7:8-ICTID/ITTID + // state: 0:pr 1:hs 2:ds 3:cm + + assign iu2_isi_d[0] = ( (|(iu1_valid_q & (~(iu_ierat_iu1_flush)) & (~(xu_iu_flush | br_iu_flush)) & (~(iu2_n_flush_req_q)))) & + cam_hit & + (~iu1_flush_enab_q) & iu1_state_q[0] & (~ccr2_frat_paranoia_q[9]) ); + // not user executable + assign iu2_isi_d[2] = ( (|(iu1_valid_q & (~(iu_ierat_iu1_flush)) & (~(xu_iu_flush | br_iu_flush)) & (~(iu2_n_flush_req_q)))) & + cam_hit & + (~iu1_flush_enab_q) & (~iu1_state_q[0]) & (~ccr2_frat_paranoia_q[9]) ); + // not supervisor executable + assign iu2_isi_d[4] = ( (|(iu1_valid_q & (~(iu_ierat_iu1_flush)) & (~(xu_iu_flush | br_iu_flush)) & (~(iu2_n_flush_req_q)))) & + cam_hit & + (~iu1_flush_enab_q) & mmucr1_q[1] & (~ccr2_frat_paranoia_q[9]) ); + // R=0 when reference exception enabled + assign iu2_isi_d[1] = (~array_cmp_data[45]); + assign iu2_isi_d[3] = (~array_cmp_data[46]); + assign iu2_isi_d[5] = (~array_cmp_data[30]); + assign iu2_isi_sig = (iu2_isi_q[0] & iu2_isi_q[1]) | + (iu2_isi_q[2] & iu2_isi_q[3]) | + (iu2_isi_q[4] & iu2_isi_q[5]); + + assign ex3_eratsx_data_d = {iu1_multihit, cam_hit, iu1_first_hit_entry}; // ex2 phase data out of cam for eratsx + + assign ex3_parerr_d[0:`THREADS - 1] = ex2_valid_q & (~(xu_ex2_flush)) & (~(iu_xu_ierat_ex2_flush_q)); + + assign ex3_parerr_d[`THREADS] = ( cam_hit & iu1_multihit_b & ex2_ttype_q[2] & ex2_tlbsel_q[0] & (~(ex2_tlbsel_q[1])) & // eratsx epn parity error + (~(ex3_ieratwe | ex4_ieratwe | ex5_ieratwe | ex6_ieratwe | ex7_ieratwe)) & + (|(ex2_valid_q & (~(xu_ex2_flush)) & (~(iu_xu_ierat_ex2_flush_q)))) ); + assign ex3_parerr_enab = ex3_parerr_q[`THREADS] & iu2_cmp_data_parerr_epn; + + assign ex4_rd_array_data_d = rd_array_data; + assign ex4_rd_cam_data_d = rd_cam_data; + + assign ex4_parerr_d[0:`THREADS - 1] = ex3_valid_q & (~(xu_ex3_flush)); + + assign ex4_parerr_d[`THREADS] = (ex3_ttype_q[0] & (~ex3_ws_q[0]) & (~ex3_ws_q[1]) & ex3_tlbsel_q[0] & (~ex3_tlbsel_q[1]) & + (~tlb_rel_act_q) & + (~(ex4_ieratwe | ex5_ieratwe | ex6_ieratwe))); // eratre, epn ws=0 + + assign ex4_parerr_d[`THREADS + 1] = (ex3_ttype_q[0] & (^ex3_ws_q) & ex3_tlbsel_q[0] & (~ex3_tlbsel_q[1]) & + (~tlb_rel_act_q) & + (~(ex4_ieratwe | ex5_ieratwe | ex6_ieratwe))); // eratre, rpn ws=1 or 2 + + assign ex4_parerr_d[`THREADS + 2] = |(ex3_parerr_q[0:`THREADS - 1]) & ex3_parerr_enab; + + + assign ex4_parerr_enab = (ex4_parerr_q[`THREADS] & ex4_rd_data_parerr_epn) | + (ex4_parerr_q[`THREADS + 1] & ex4_rd_data_parerr_rpn); + + assign iu_xu_ord_par_err_d = ex4_parerr_q[`THREADS + 2] | (|(ex4_parerr_q[0:`THREADS-1]) & ex4_parerr_enab); // eratsx or eratre parerr + assign iu_xu_ord_par_err = iu_xu_ord_par_err_q; + + assign ex4_ieen_d[0:`THREADS - 1] = (ex3_ttype_q[2] == 1'b1) ? (ex3_parerr_q[0:`THREADS-1] & {`THREADS{ex3_parerr_enab}} & (~(xu_ex3_flush))) : // eratsx + ((iu2_multihit_sig == 1'b1) | (iu2_parerr_sig == 1'b1)) ? (iu2_valid_q & (~iu2_n_flush_req_q)) : // fetch with multihit or parerr + {`THREADS{1'b0}}; + + assign ex4_ieen_d[`THREADS:`THREADS + num_entry_log2 - 1] = (ex3_ttype_q[2] == 1'b1) ? ex3_eratsx_data_q[2:2 + num_entry_log2 - 1] : // eratsx, first hit entry + ((ex3_ttype_q[0] == 1'b1) & (ex3_ws_q == 2'b00) & (ex3_tlbsel_q == TlbSel_IErat)) ? ex3_ra_entry_q : // eratre, epn ws=0 + ((ex3_ttype_q[0] == 1'b1) & ((ex3_ws_q == 2'b01) | (ex3_ws_q == 2'b10)) & (ex3_tlbsel_q == TlbSel_IErat)) ? ex3_ra_entry_q : // eratre, rpn ws=1 or 2 + ((iu2_multihit_sig == 1'b1) | (iu2_parerr_sig == 1'b1)) ? ex3_eratsx_data_q[2:2 + num_entry_log2 - 1] : // fetch with multihit or parerr + {num_entry_log2{1'b0}}; + + assign ex5_ieen_d[0:`THREADS - 1] = (ex4_ieen_q[0:`THREADS - 1] & (~(xu_ex4_flush))) | // eratsx, or fetch + (ex4_parerr_q[0:`THREADS - 1] & {`THREADS{ex4_parerr_enab}} & (~(xu_ex4_flush))); // eratre + // eratsx, or fetch + assign ex5_ieen_d[`THREADS:`THREADS + num_entry_log2 - 1] = ex4_ieen_q[`THREADS:`THREADS + num_entry_log2 - 1]; + + assign ex6_ieen_d = {( ex5_ieen_q[0:`THREADS - 1] & (~(xu_ex5_flush)) & (~{`THREADS{mchk_flash_inv_q[3]}}) ), ex5_ieen_q[`THREADS:`THREADS + num_entry_log2 - 1]}; + + assign mchk_flash_inv_d[0] = |(iu2_valid_q & (~(xu_iu_flush | br_iu_flush)) & (~(iu2_n_flush_req_q))); // iu2 phase + assign mchk_flash_inv_d[1] = iu2_parerr_sig; // iu2 phase, parerr on fetch and cam hit + assign mchk_flash_inv_d[2] = iu2_multihit_sig; // iu2 phase, multihit on fetch and cam hit + assign mchk_flash_inv_d[3] = mchk_flash_inv_enab; + // mchk_flash_inv_q[3] ex5_ieen phase gates mmucr1 updates when h/w recovery flash invalidates erat + + assign mchk_flash_inv_enab = mchk_flash_inv_q[0] & (mchk_flash_inv_q[1] | mchk_flash_inv_q[2]) & (~(ccr2_notlb_q)) & (~(xucr4_mmu_mchk_q)); // iu3 phase, parerr/multihit on fetch and tlb mode and mmu_mchk disabled + + assign iu1_flush_enab_d = (((tlb_rel_val_q[0:3] != 4'b0000) & (tlb_rel_val_q[4] == 1'b1)) | tlb_rel_act_q) | // tlb hit reload + (snoop_val_q[0:1] == 2'b11) | // invalidate snoop + ((|(ex1_valid_q[0:`THREADS - 1])) & ex1_ttype_q[2] & (ex1_tlbsel_q == TlbSel_IErat)) | // eratsx + ((|(ex6_valid_q[0:`THREADS - 1])) & ex6_ttype_q[1] & (ex6_ws_q == 2'b00) & (ex6_tlbsel_q == TlbSel_IErat)) | // eratwe WS=0 + (csinv_complete | mchk_flash_inv_enab); // csync or isync enabled and complete, or mchk flash inval due to parerr/multihit + + // adding local iu2 flush request for timing + assign iu2_n_flush_req_d = (iu1_flush_enab_q == 1'b1) ? (iu1_valid_q & (~(iu_ierat_iu1_flush | xu_iu_flush | br_iu_flush | iu2_n_flush_req_q))) : // delayed iu0 flush enable + ((cam_hit == 1'b0) & (ccr2_notlb_q == MMU_Mode_Value) & (ccr2_frat_paranoia_q[9] == 1'b0) & (iu1_prefetch_q == 1'b0))? (iu1_valid_q & (~(iu_ierat_iu1_flush | xu_iu_flush | br_iu_flush | iu2_n_flush_req_q)) & (~(tlb_miss_q))): + {`THREADS{1'b0}}; + + // adding local iu2 flush request for timing + // adding frat paranoia for ra=ea + + // tlb-mode sequence of events: + // 1) non-prefetch ierat miss sets hold and flushes op via iu2_n_flush_req_q, + // 2) request sent to tlb, + // 3) tlb-reload hit/miss, + // 4) hold is cleared, tlb-miss sets tlb_miss_q=1, tlb-hit writes erat + // 5) replay of op clears tlb_miss_q if set, erat miss sets hold again but no flush this time + generate + begin : xhdl1 + genvar tid; + for (tid = 0; tid <= `THREADS - 1; tid = tid + 1) + begin : holdTid + assign hold_req_d[tid] = (por_hold_req[tid] == 1'b1) ? 1'b1 : + (ccr2_frat_paranoia_q[9] == 1'b1) ? 1'b0 : + ((xu_iu_flush[tid] == 1'b1 | br_iu_flush[tid] == 1'b1 | iu_ierat_iu1_flush[tid] == 1'b1) & tlb_req_inprogress_d[tid] == 1'b0) ? 1'b0 : + (tlb_rel_val_q[tid] == 1'b1 & ccr2_notlb_q == MMU_Mode_Value) ? 1'b0 : // any tlb reload clears hold + (cam_hit == 1'b0 & iu1_valid_q[tid] == 1'b1 & + iu1_prefetch_q == 1'b0 & + iu_ierat_iu1_flush[tid] == 1'b0 & xu_iu_flush[tid] == 1'b0 & br_iu_flush[tid] == 1'b0 & iu1_flush_enab_q == 1'b0 & + iu2_n_flush_req_q[tid] == 1'b0 & ccr2_notlb_q == MMU_Mode_Value) ? 1'b1 : // any non-flushed, non-prefetch cam miss + hold_req_q[tid]; + + assign tlb_miss_d[tid] = (ccr2_notlb_q != MMU_Mode_Value | por_seq_q != PorSeq_Idle | ccr2_frat_paranoia_q[9] == 1'b1) ? 1'b0 : + (xu_iu_flush[tid] == 1'b1 | br_iu_flush[tid] == 1'b1) ? 1'b0 : + (iu1_valid_q[tid] == 1'b1 & iu_ierat_iu1_flush[tid] == 1'b0 & xu_iu_flush[tid] == 1'b0 & br_iu_flush[tid] == 1'b0 & iu1_flush_enab_q == 1'b0 & + iu2_n_flush_req_q[tid] == 1'b0 & tlb_miss_q[tid] == 1'b1) ? 1'b0 : // replay of previous tlb miss + (tlb_rel_val_q[tid] == 1'b1 & tlb_rel_val_q[4] == 1'b0 & tlb_miss_q[tid] == 1'b0 & tlb_flushed_q[tid] == 1'b0) ? hold_req_q[tid] : // tlb-miss reload + tlb_miss_q[tid]; + + assign tlb_flushed_d[tid] = (tlb_req_inprogress_d[tid] == 1'b1 & (xu_iu_flush[tid] == 1'b1 | br_iu_flush[tid] == 1'b1 | iu_ierat_iu1_flush[tid] == 1'b1)) ? 1'b1 : + (tlb_rel_val_q[tid] == 1'b1) ? 1'b0 : + tlb_flushed_q[tid]; + + assign tlb_req_inprogress_d[tid] = (ccr2_frat_paranoia_q[9] == 1'b1 | por_hold_req[tid] == 1'b1 | ccr2_notlb_q != MMU_Mode_Value | tlb_rel_val_q[tid] == 1'b1) ? 1'b0 : // mode, por, or tlb reload + (xu_iu_flush[tid] == 1'b0 & br_iu_flush[tid] == 1'b0 & iu2_valid_q[tid] == 1'b1 & hold_req_q[tid] == 1'b0) ? 1'b0 : // erat miss flush from xu is gone and iu is running again + (iu2_tlbreq_q == 1'b1 & iu2_valid_q[tid] == 1'b1 & ccr2_notlb_q == MMU_Mode_Value) ? 1'b1 : // tlb service request for this thread + tlb_req_inprogress_q[tid]; + end + end + endgenerate + + assign iu2_tlbreq_d = (cam_hit == 1'b0 & iu1_flush_enab_q == 1'b0 & ccr2_notlb_q == MMU_Mode_Value & ccr2_frat_paranoia_q[9] == 1'b0 & iu_ierat_iu1_back_inv == 1'b0 & + iu1_prefetch_q == 1'b0 & + (|(iu1_valid_q & (~(iu_ierat_iu1_flush)) & (~(xu_iu_flush | br_iu_flush)) & (~(iu2_n_flush_req_q)) & (~(tlb_miss_q)) & (~(hold_req_q)))) == 1'b1) ? 1'b1 : + 1'b0; + + assign snoop_val_d[0] = (snoop_val_q[0] == 1'b0) ? mm_iu_ierat_snoop_val : + (tlb_rel_val_q[4] == 1'b0 & snoop_val_q[1] == 1'b1) ? 1'b0 : // no tlb hit reload, and no I$ backinv + snoop_val_q[0]; + assign snoop_val_d[1] = (~iu_ierat_ium1_back_inv); + assign snoop_val_d[2] = (tlb_rel_val_q[4] == 1'b1 | snoop_val_q[1] == 1'b0) ? 1'b0 : // a tlb hit reload, or I$ backinv + snoop_val_q[0]; + assign snoop_attr_d = (snoop_val_q[0] == 1'b0) ? mm_iu_ierat_snoop_attr : + snoop_attr_q; + assign snoop_addr_d = (snoop_val_q[0] == 1'b0) ? mm_iu_ierat_snoop_vpn : + snoop_addr_q; + assign iu_mm_ierat_snoop_ack = snoop_val_q[2]; + + + generate + begin : xhdl2 + genvar tid; + for (tid = 0; tid <= `THREADS - 1; tid = tid + 1) + begin : rpnTid + if (rs_data_width == 64) + begin : gen64_holdreg + assign rpn_holdreg_d[tid][0:19] = (ex6_valid_q[tid] == 1'b1 & ex6_ttype_q[1] == 1'b1 & ex6_ws_q == 2'b01 & ex6_tlbsel_q == TlbSel_IErat & ex6_state_q[3] == 1'b1) ? ex6_data_in_q[0:19] : // eratwe WS=1, cm=64b + (ex6_valid_q[tid] == 1'b1 & ex6_ttype_q[1] == 1'b1 & ex6_ws_q == 2'b10 & ex6_tlbsel_q == TlbSel_IErat & ex6_state_q[3] == 1'b0) ? ex6_data_in_q[32:51] : // eratwe WS=2, cm=32b + rpn_holdreg_q[tid][0:19]; // hold value; + assign rpn_holdreg_d[tid][20:31] = (ex6_valid_q[tid] == 1'b1 & ex6_ttype_q[1] == 1'b1 & ex6_ws_q == 2'b01 & ex6_tlbsel_q == TlbSel_IErat & ex6_state_q[3] == 1'b1) ? ex6_data_in_q[20:31] : // eratwe WS=1, cm=64b + (ex6_valid_q[tid] == 1'b1 & ex6_ttype_q[1] == 1'b1 & ex6_ws_q == 2'b01 & ex6_tlbsel_q == TlbSel_IErat & ex6_state_q[3] == 1'b0) ? ex6_data_in_q[52:63] : // eratwe WS=1, cm=32b + rpn_holdreg_q[tid][20:31]; // hold value; + assign rpn_holdreg_d[tid][32:51] = (ex6_valid_q[tid] == 1'b1 & ex6_ttype_q[1] == 1'b1 & ex6_ws_q == 2'b01 & ex6_tlbsel_q == TlbSel_IErat & ex6_state_q[3] == 1'b1) ? ex6_data_in_q[32:51] : // eratwe WS=1, cm=64b + (ex6_valid_q[tid] == 1'b1 & ex6_ttype_q[1] == 1'b1 & ex6_ws_q == 2'b01 & ex6_tlbsel_q == TlbSel_IErat & ex6_state_q[3] == 1'b0) ? ex6_data_in_q[32:51] : // eratwe WS=2, cm=32b + rpn_holdreg_q[tid][32:51]; // hold value; + assign rpn_holdreg_d[tid][52:63] = (ex6_valid_q[tid] == 1'b1 & ex6_ttype_q[1] == 1'b1 & ex6_ws_q == 2'b01 & ex6_tlbsel_q == TlbSel_IErat & ex6_state_q[3] == 1'b1) ? ex6_data_in_q[52:63] : // eratwe WS=1, cm=64b + (ex6_valid_q[tid] == 1'b1 & ex6_ttype_q[1] == 1'b1 & ex6_ws_q == 2'b10 & ex6_tlbsel_q == TlbSel_IErat & ex6_state_q[3] == 1'b0) ? ex6_data_in_q[52:63] : // eratwe WS=2, cm=32b + rpn_holdreg_q[tid][52:63]; // hold value; + end + end + end + endgenerate + + assign ex6_ieratwe_ws3 = (|(ex6_valid_q[0:`THREADS - 1])) & ex6_ttype_q[1] & (ex6_ws_q == 2'b11) & (ex6_tlbsel_q == TlbSel_IErat); // eratwe WS=3 + + assign watermark_d = (ex6_ieratwe_ws3 == 1'b1) ? ex6_data_in_q[64-watermark_width:63] : // eratwe WS=3 + watermark_q; // hold value; + + assign eptr_d = ((ex6_ieratwe_ws3 == 1'b1 | csinv_complete == 1'b1) & mmucr1_q[0] == 1'b1) ? {eptr_width{1'b0}} : // write watermark and round-robin mode + ((eptr_q == 4'b1111 | eptr_q == watermark_q) & + ( ((|(ex6_valid_q[0:`THREADS - 1])) == 1'b1 & ex6_ttype_q[1] == 1'b1 & ex6_ws_q == 2'b00 & ex6_tlbsel_q == TlbSel_IErat & mmucr1_q[0] == 1'b1) | // eratwe WS=0, max rollover, or watermark rollover + (tlb_rel_val_q[0:3] != 4'b0000 & tlb_rel_val_q[4] == 1'b1 & tlb_rel_data_q[eratpos_wren] == 1'b1 & mmucr1_q[0] == 1'b1))) ? {eptr_width{1'b0}} : // tlb reload write, max rollover, or watermark rollover + ( ((|(ex6_valid_q[0:`THREADS - 1])) == 1'b1 & ex6_ttype_q[1] == 1'b1 & ex6_ws_q == 2'b00 & ex6_tlbsel_q == TlbSel_IErat & mmucr1_q[0] == 1'b1) | // eratwe WS=0, increment + (tlb_rel_val_q[0:3] != 4'b0000 & tlb_rel_val_q[4] == 1'b1 & tlb_rel_data_q[eratpos_wren] == 1'b1 & mmucr1_q[0] == 1'b1) ) ? eptr_p1 : // tlb reload write, increment + eptr_q; + + assign eptr_p1 = (eptr_q == 4'b0000) ? 4'b0001 : + (eptr_q == 4'b0001) ? 4'b0010 : + (eptr_q == 4'b0010) ? 4'b0011 : + (eptr_q == 4'b0011) ? 4'b0100 : + (eptr_q == 4'b0100) ? 4'b0101 : + (eptr_q == 4'b0101) ? 4'b0110 : + (eptr_q == 4'b0110) ? 4'b0111 : + (eptr_q == 4'b0111) ? 4'b1000 : + (eptr_q == 4'b1000) ? 4'b1001 : + (eptr_q == 4'b1001) ? 4'b1010 : + (eptr_q == 4'b1010) ? 4'b1011 : + (eptr_q == 4'b1011) ? 4'b1100 : + (eptr_q == 4'b1100) ? 4'b1101 : + (eptr_q == 4'b1101) ? 4'b1110 : + (eptr_q == 4'b1110) ? 4'b1111 : + 4'b0000; + + assign lru_way_is_written = lru_way_encode == ex6_ra_entry_q; + assign lru_way_is_hit_entry = lru_way_encode == iu1_first_hit_entry; + + // lru_update_event + // 0: tlb reload + // 1: invalidate snoop + // 2: csync or isync enabled + // 3: eratwe WS=0 + // 4: fetch hit + // 5: iu2 cam write type events + // 6: iu2 cam invalidate type events + // 7: iu2 cam translation type events + // 8: iu2, superset of non-translation events + + assign lru_update_event_d[0] = ( tlb_rel_data_q[eratpos_wren] & (|(tlb_rel_val_q[0:3])) & tlb_rel_val_q[4] ); // tlb reload + + assign lru_update_event_d[1] = ( snoop_val_q[0] & snoop_val_q[1] ); // invalidate snoop + + assign lru_update_event_d[2] = ( csinv_complete ); // csync or isync enabled and completed + + assign lru_update_event_d[3] = ( (|(ex6_valid_q[0:`THREADS-1])) & ex6_ttype_q[1] & (~ex6_ws_q[0]) & (~ex6_ws_q[1]) & ex6_tlbsel_q[0] & (~ex6_tlbsel_q[1]) & lru_way_is_written ); // eratwe WS=0, lru=target + + assign lru_update_event_d[4] = ( (|(iu1_valid_q & (~(iu_ierat_iu1_flush)) & (~(xu_iu_flush | br_iu_flush)) & (~(iu2_n_flush_req_q)))) & + (~iu1_flush_enab_q) & cam_hit & lru_way_is_hit_entry ); // fetch hit with no error or flush, lru=hit + + assign lru_update_event_d[5] = lru_update_event_q[0] | lru_update_event_q[3]; // 5: iu2 cam write type events + + assign lru_update_event_d[6] = lru_update_event_q[1] | lru_update_event_q[2]; // 6: iu2 cam invalidate type events + + assign lru_update_event_d[7] = ( (|(iu1_valid_q & (~(iu_ierat_iu1_flush)) & (~(xu_iu_flush | br_iu_flush)) & (~(iu2_n_flush_req_q)))) & + (~iu1_flush_enab_q) & cam_hit & lru_way_is_hit_entry ); // 7: iu2 cam translation type events + assign lru_update_event_d[8] = lru_update_event_q[0] | lru_update_event_q[1] | lru_update_event_q[2] | lru_update_event_q[3]; // iu2, non-fetch superset + + assign lru_update_event_d[9] = ( (|(tlb_rel_val_q[0:3])) & tlb_rel_val_q[4] & tlb_rel_data_q[eratpos_wren] ) | // tlb reload + ( (|(ex6_valid_q[0:`THREADS - 1]) & ex6_ttype_q[1] & ex6_ws_q == 2'b00 & ex6_tlbsel_q == TlbSel_IErat) ) | // i-eratwe WS=0 + ( snoop_val_q[0] & snoop_val_q[1] ) | // invalidate snoop + csinv_complete | // csync or isync enabled and completed + mchk_flash_inv_enab; // mcheck flash invalidate + + assign lru_d[1] = ((ex6_ieratwe_ws3 == 1'b1 & mmucr1_q[0] == 1'b0) | flash_invalidate == 1'b1) ? 1'b0 : // write watermark and not round-robin mode, or flash inv all v bits + (lru_reset_vec[1] == 1'b1 & mmucr1_q[0] == 1'b0 & lru_op_vec[1] == 1'b0 & ccr2_frat_paranoia_q[9] == 1'b0 & (lru_update_event_q[8] == 1'b1 | (lru_update_event_q[4] & (~(iu2_multihit_sig | iu2_parerr_sig | iu2_isi_sig))) == 1'b1)) ? 1'b0 : + (lru_set_vec[1] == 1'b1 & mmucr1_q[0] == 1'b0 & lru_op_vec[1] == 1'b0 & ccr2_frat_paranoia_q[9] == 1'b0 & (lru_update_event_q[8] == 1'b1 | (lru_update_event_q[4] & (~(iu2_multihit_sig | iu2_parerr_sig | iu2_isi_sig))) == 1'b1)) ? 1'b1 : + lru_q[1]; + assign lru_eff[1] = (lru_vp_vec[1] & lru_op_vec[1]) | (lru_q[1] & (~lru_op_vec[1])); + assign lru_d[2] = ((ex6_ieratwe_ws3 == 1'b1 & mmucr1_q[0] == 1'b0) | flash_invalidate == 1'b1) ? 1'b0 : + (lru_reset_vec[2] == 1'b1 & mmucr1_q[0] == 1'b0 & lru_op_vec[2] == 1'b0 & ccr2_frat_paranoia_q[9] == 1'b0 & (lru_update_event_q[8] == 1'b1 | (lru_update_event_q[4] & (~(iu2_multihit_sig | iu2_parerr_sig | iu2_isi_sig))) == 1'b1)) ? 1'b0 : + (lru_set_vec[2] == 1'b1 & mmucr1_q[0] == 1'b0 & lru_op_vec[2] == 1'b0 & ccr2_frat_paranoia_q[9] == 1'b0 & (lru_update_event_q[8] == 1'b1 | (lru_update_event_q[4] & (~(iu2_multihit_sig | iu2_parerr_sig | iu2_isi_sig))) == 1'b1)) ? 1'b1 : + lru_q[2]; + assign lru_eff[2] = (lru_vp_vec[2] & lru_op_vec[2]) | (lru_q[2] & (~lru_op_vec[2])); + assign lru_d[3] = ((ex6_ieratwe_ws3 == 1'b1 & mmucr1_q[0] == 1'b0) | flash_invalidate == 1'b1) ? 1'b0 : + (lru_reset_vec[3] == 1'b1 & mmucr1_q[0] == 1'b0 & lru_op_vec[3] == 1'b0 & ccr2_frat_paranoia_q[9] == 1'b0 & (lru_update_event_q[8] == 1'b1 | (lru_update_event_q[4] & (~(iu2_multihit_sig | iu2_parerr_sig | iu2_isi_sig))) == 1'b1)) ? 1'b0 : + (lru_set_vec[3] == 1'b1 & mmucr1_q[0] == 1'b0 & lru_op_vec[3] == 1'b0 & ccr2_frat_paranoia_q[9] == 1'b0 & (lru_update_event_q[8] == 1'b1 | (lru_update_event_q[4] & (~(iu2_multihit_sig | iu2_parerr_sig | iu2_isi_sig))) == 1'b1)) ? 1'b1 : + lru_q[3]; + assign lru_eff[3] = (lru_vp_vec[3] & lru_op_vec[3]) | (lru_q[3] & (~lru_op_vec[3])); + assign lru_d[4] = ((ex6_ieratwe_ws3 == 1'b1 & mmucr1_q[0] == 1'b0) | flash_invalidate == 1'b1) ? 1'b0 : + (lru_reset_vec[4] == 1'b1 & mmucr1_q[0] == 1'b0 & lru_op_vec[4] == 1'b0 & ccr2_frat_paranoia_q[9] == 1'b0 & (lru_update_event_q[8] == 1'b1 | (lru_update_event_q[4] & (~(iu2_multihit_sig | iu2_parerr_sig | iu2_isi_sig))) == 1'b1)) ? 1'b0 : + (lru_set_vec[4] == 1'b1 & mmucr1_q[0] == 1'b0 & lru_op_vec[4] == 1'b0 & ccr2_frat_paranoia_q[9] == 1'b0 & (lru_update_event_q[8] == 1'b1 | (lru_update_event_q[4] & (~(iu2_multihit_sig | iu2_parerr_sig | iu2_isi_sig))) == 1'b1)) ? 1'b1 : + lru_q[4]; + assign lru_eff[4] = (lru_vp_vec[4] & lru_op_vec[4]) | (lru_q[4] & (~lru_op_vec[4])); + assign lru_d[5] = ((ex6_ieratwe_ws3 == 1'b1 & mmucr1_q[0] == 1'b0) | flash_invalidate == 1'b1) ? 1'b0 : + (lru_reset_vec[5] == 1'b1 & mmucr1_q[0] == 1'b0 & lru_op_vec[5] == 1'b0 & ccr2_frat_paranoia_q[9] == 1'b0 & (lru_update_event_q[8] == 1'b1 | (lru_update_event_q[4] & (~(iu2_multihit_sig | iu2_parerr_sig | iu2_isi_sig))) == 1'b1)) ? 1'b0 : + (lru_set_vec[5] == 1'b1 & mmucr1_q[0] == 1'b0 & lru_op_vec[5] == 1'b0 & ccr2_frat_paranoia_q[9] == 1'b0 & (lru_update_event_q[8] == 1'b1 | (lru_update_event_q[4] & (~(iu2_multihit_sig | iu2_parerr_sig | iu2_isi_sig))) == 1'b1)) ? 1'b1 : + lru_q[5]; + assign lru_eff[5] = (lru_vp_vec[5] & lru_op_vec[5]) | (lru_q[5] & (~lru_op_vec[5])); + assign lru_d[6] = ((ex6_ieratwe_ws3 == 1'b1 & mmucr1_q[0] == 1'b0) | flash_invalidate == 1'b1) ? 1'b0 : + (lru_reset_vec[6] == 1'b1 & mmucr1_q[0] == 1'b0 & lru_op_vec[6] == 1'b0 & ccr2_frat_paranoia_q[9] == 1'b0 & (lru_update_event_q[8] == 1'b1 | (lru_update_event_q[4] & (~(iu2_multihit_sig | iu2_parerr_sig | iu2_isi_sig))) == 1'b1)) ? 1'b0 : + (lru_set_vec[6] == 1'b1 & mmucr1_q[0] == 1'b0 & lru_op_vec[6] == 1'b0 & ccr2_frat_paranoia_q[9] == 1'b0 & (lru_update_event_q[8] == 1'b1 | (lru_update_event_q[4] & (~(iu2_multihit_sig | iu2_parerr_sig | iu2_isi_sig))) == 1'b1)) ? 1'b1 : + lru_q[6]; + assign lru_eff[6] = (lru_vp_vec[6] & lru_op_vec[6]) | (lru_q[6] & (~lru_op_vec[6])); + assign lru_d[7] = ((ex6_ieratwe_ws3 == 1'b1 & mmucr1_q[0] == 1'b0) | flash_invalidate == 1'b1) ? 1'b0 : + (lru_reset_vec[7] == 1'b1 & mmucr1_q[0] == 1'b0 & lru_op_vec[7] == 1'b0 & ccr2_frat_paranoia_q[9] == 1'b0 & (lru_update_event_q[8] == 1'b1 | (lru_update_event_q[4] & (~(iu2_multihit_sig | iu2_parerr_sig | iu2_isi_sig))) == 1'b1)) ? 1'b0 : + (lru_set_vec[7] == 1'b1 & mmucr1_q[0] == 1'b0 & lru_op_vec[7] == 1'b0 & ccr2_frat_paranoia_q[9] == 1'b0 & (lru_update_event_q[8] == 1'b1 | (lru_update_event_q[4] & (~(iu2_multihit_sig | iu2_parerr_sig | iu2_isi_sig))) == 1'b1)) ? 1'b1 : + lru_q[7]; + assign lru_eff[7] = (lru_vp_vec[7] & lru_op_vec[7]) | (lru_q[7] & (~lru_op_vec[7])); + assign lru_d[8] = ((ex6_ieratwe_ws3 == 1'b1 & mmucr1_q[0] == 1'b0) | flash_invalidate == 1'b1) ? 1'b0 : + (lru_reset_vec[8] == 1'b1 & mmucr1_q[0] == 1'b0 & lru_op_vec[8] == 1'b0 & ccr2_frat_paranoia_q[9] == 1'b0 & (lru_update_event_q[8] == 1'b1 | (lru_update_event_q[4] & (~(iu2_multihit_sig | iu2_parerr_sig | iu2_isi_sig))) == 1'b1)) ? 1'b0 : + (lru_set_vec[8] == 1'b1 & mmucr1_q[0] == 1'b0 & lru_op_vec[8] == 1'b0 & ccr2_frat_paranoia_q[9] == 1'b0 & (lru_update_event_q[8] == 1'b1 | (lru_update_event_q[4] & (~(iu2_multihit_sig | iu2_parerr_sig | iu2_isi_sig))) == 1'b1)) ? 1'b1 : + lru_q[8]; + assign lru_eff[8] = (lru_vp_vec[8] & lru_op_vec[8]) | (lru_q[8] & (~lru_op_vec[8])); + assign lru_d[9] = ((ex6_ieratwe_ws3 == 1'b1 & mmucr1_q[0] == 1'b0) | flash_invalidate == 1'b1) ? 1'b0 : + (lru_reset_vec[9] == 1'b1 & mmucr1_q[0] == 1'b0 & lru_op_vec[9] == 1'b0 & ccr2_frat_paranoia_q[9] == 1'b0 & (lru_update_event_q[8] == 1'b1 | (lru_update_event_q[4] & (~(iu2_multihit_sig | iu2_parerr_sig | iu2_isi_sig))) == 1'b1)) ? 1'b0 : + (lru_set_vec[9] == 1'b1 & mmucr1_q[0] == 1'b0 & lru_op_vec[9] == 1'b0 & ccr2_frat_paranoia_q[9] == 1'b0 & (lru_update_event_q[8] == 1'b1 | (lru_update_event_q[4] & (~(iu2_multihit_sig | iu2_parerr_sig | iu2_isi_sig))) == 1'b1)) ? 1'b1 : + lru_q[9]; + assign lru_eff[9] = (lru_vp_vec[9] & lru_op_vec[9]) | (lru_q[9] & (~lru_op_vec[9])); + assign lru_d[10] = ((ex6_ieratwe_ws3 == 1'b1 & mmucr1_q[0] == 1'b0) | flash_invalidate == 1'b1) ? 1'b0 : + (lru_reset_vec[10] == 1'b1 & mmucr1_q[0] == 1'b0 & lru_op_vec[10] == 1'b0 & ccr2_frat_paranoia_q[9] == 1'b0 & (lru_update_event_q[8] == 1'b1 | (lru_update_event_q[4] & (~(iu2_multihit_sig | iu2_parerr_sig | iu2_isi_sig))) == 1'b1)) ? 1'b0 : + (lru_set_vec[10] == 1'b1 & mmucr1_q[0] == 1'b0 & lru_op_vec[10] == 1'b0 & ccr2_frat_paranoia_q[9] == 1'b0 & (lru_update_event_q[8] == 1'b1 | (lru_update_event_q[4] & (~(iu2_multihit_sig | iu2_parerr_sig | iu2_isi_sig))) == 1'b1)) ? 1'b1 : + lru_q[10]; + assign lru_eff[10] = (lru_vp_vec[10] & lru_op_vec[10]) | (lru_q[10] & (~lru_op_vec[10])); + assign lru_d[11] = ((ex6_ieratwe_ws3 == 1'b1 & mmucr1_q[0] == 1'b0) | flash_invalidate == 1'b1) ? 1'b0 : + (lru_reset_vec[11] == 1'b1 & mmucr1_q[0] == 1'b0 & lru_op_vec[11] == 1'b0 & ccr2_frat_paranoia_q[9] == 1'b0 & (lru_update_event_q[8] == 1'b1 | (lru_update_event_q[4] & (~(iu2_multihit_sig | iu2_parerr_sig | iu2_isi_sig))) == 1'b1)) ? 1'b0 : + (lru_set_vec[11] == 1'b1 & mmucr1_q[0] == 1'b0 & lru_op_vec[11] == 1'b0 & ccr2_frat_paranoia_q[9] == 1'b0 & (lru_update_event_q[8] == 1'b1 | (lru_update_event_q[4] & (~(iu2_multihit_sig | iu2_parerr_sig | iu2_isi_sig))) == 1'b1)) ? 1'b1 : + lru_q[11]; + assign lru_eff[11] = (lru_vp_vec[11] & lru_op_vec[11]) | (lru_q[11] & (~lru_op_vec[11])); + assign lru_d[12] = ((ex6_ieratwe_ws3 == 1'b1 & mmucr1_q[0] == 1'b0) | flash_invalidate == 1'b1) ? 1'b0 : + (lru_reset_vec[12] == 1'b1 & mmucr1_q[0] == 1'b0 & lru_op_vec[12] == 1'b0 & ccr2_frat_paranoia_q[9] == 1'b0 & (lru_update_event_q[8] == 1'b1 | (lru_update_event_q[4] & (~(iu2_multihit_sig | iu2_parerr_sig | iu2_isi_sig))) == 1'b1)) ? 1'b0 : + (lru_set_vec[12] == 1'b1 & mmucr1_q[0] == 1'b0 & lru_op_vec[12] == 1'b0 & ccr2_frat_paranoia_q[9] == 1'b0 & (lru_update_event_q[8] == 1'b1 | (lru_update_event_q[4] & (~(iu2_multihit_sig | iu2_parerr_sig | iu2_isi_sig))) == 1'b1)) ? 1'b1 : + lru_q[12]; + assign lru_eff[12] = (lru_vp_vec[12] & lru_op_vec[12]) | (lru_q[12] & (~lru_op_vec[12])); + assign lru_d[13] = ((ex6_ieratwe_ws3 == 1'b1 & mmucr1_q[0] == 1'b0) | flash_invalidate == 1'b1) ? 1'b0 : + (lru_reset_vec[13] == 1'b1 & mmucr1_q[0] == 1'b0 & lru_op_vec[13] == 1'b0 & ccr2_frat_paranoia_q[9] == 1'b0 & (lru_update_event_q[8] == 1'b1 | (lru_update_event_q[4] & (~(iu2_multihit_sig | iu2_parerr_sig | iu2_isi_sig))) == 1'b1)) ? 1'b0 : + (lru_set_vec[13] == 1'b1 & mmucr1_q[0] == 1'b0 & lru_op_vec[13] == 1'b0 & ccr2_frat_paranoia_q[9] == 1'b0 & (lru_update_event_q[8] == 1'b1 | (lru_update_event_q[4] & (~(iu2_multihit_sig | iu2_parerr_sig | iu2_isi_sig))) == 1'b1)) ? 1'b1 : + lru_q[13]; + assign lru_eff[13] = (lru_vp_vec[13] & lru_op_vec[13]) | (lru_q[13] & (~lru_op_vec[13])); + assign lru_d[14] = ((ex6_ieratwe_ws3 == 1'b1 & mmucr1_q[0] == 1'b0) | flash_invalidate == 1'b1) ? 1'b0 : + (lru_reset_vec[14] == 1'b1 & mmucr1_q[0] == 1'b0 & lru_op_vec[14] == 1'b0 & ccr2_frat_paranoia_q[9] == 1'b0 & (lru_update_event_q[8] == 1'b1 | (lru_update_event_q[4] & (~(iu2_multihit_sig | iu2_parerr_sig | iu2_isi_sig))) == 1'b1)) ? 1'b0 : + (lru_set_vec[14] == 1'b1 & mmucr1_q[0] == 1'b0 & lru_op_vec[14] == 1'b0 & ccr2_frat_paranoia_q[9] == 1'b0 & (lru_update_event_q[8] == 1'b1 | (lru_update_event_q[4] & (~(iu2_multihit_sig | iu2_parerr_sig | iu2_isi_sig))) == 1'b1)) ? 1'b1 : + lru_q[14]; + assign lru_eff[14] = (lru_vp_vec[14] & lru_op_vec[14]) | (lru_q[14] & (~lru_op_vec[14])); + assign lru_d[15] = ((ex6_ieratwe_ws3 == 1'b1 & mmucr1_q[0] == 1'b0) | flash_invalidate == 1'b1) ? 1'b0 : + (lru_reset_vec[15] == 1'b1 & mmucr1_q[0] == 1'b0 & lru_op_vec[15] == 1'b0 & ccr2_frat_paranoia_q[9] == 1'b0 & (lru_update_event_q[8] == 1'b1 | (lru_update_event_q[4] & (~(iu2_multihit_sig | iu2_parerr_sig | iu2_isi_sig))) == 1'b1)) ? 1'b0 : + (lru_set_vec[15] == 1'b1 & mmucr1_q[0] == 1'b0 & lru_op_vec[15] == 1'b0 & ccr2_frat_paranoia_q[9] == 1'b0 & (lru_update_event_q[8] == 1'b1 | (lru_update_event_q[4] & (~(iu2_multihit_sig | iu2_parerr_sig | iu2_isi_sig))) == 1'b1)) ? 1'b1 : + lru_q[15]; + assign lru_eff[15] = (lru_vp_vec[15] & lru_op_vec[15]) | (lru_q[15] & (~lru_op_vec[15])); + + // RMT override enable: Op= OR(all RMT entries below and left of p) XOR OR(all RMT entries below and right of p) + assign lru_op_vec[1] = (lru_rmt_vec[0] | lru_rmt_vec[1] | lru_rmt_vec[2] | lru_rmt_vec[3] | lru_rmt_vec[4] | lru_rmt_vec[5] | lru_rmt_vec[6] | lru_rmt_vec[7]) ^ (lru_rmt_vec[8] | lru_rmt_vec[9] | lru_rmt_vec[10] | lru_rmt_vec[11] | lru_rmt_vec[12] | lru_rmt_vec[13] | lru_rmt_vec[14] | lru_rmt_vec[15]); + assign lru_op_vec[2] = (lru_rmt_vec[0] | lru_rmt_vec[1] | lru_rmt_vec[2] | lru_rmt_vec[3]) ^ (lru_rmt_vec[4] | lru_rmt_vec[5] | lru_rmt_vec[6] | lru_rmt_vec[7]); + assign lru_op_vec[3] = (lru_rmt_vec[8] | lru_rmt_vec[9] | lru_rmt_vec[10] | lru_rmt_vec[11]) ^ (lru_rmt_vec[12] | lru_rmt_vec[13] | lru_rmt_vec[14] | lru_rmt_vec[15]); + assign lru_op_vec[4] = (lru_rmt_vec[0] | lru_rmt_vec[1]) ^ (lru_rmt_vec[2] | lru_rmt_vec[3]); + assign lru_op_vec[5] = (lru_rmt_vec[4] | lru_rmt_vec[5]) ^ (lru_rmt_vec[6] | lru_rmt_vec[7]); + assign lru_op_vec[6] = (lru_rmt_vec[8] | lru_rmt_vec[9]) ^ (lru_rmt_vec[10] | lru_rmt_vec[11]); + assign lru_op_vec[7] = (lru_rmt_vec[12] | lru_rmt_vec[13]) ^ (lru_rmt_vec[14] | lru_rmt_vec[15]); + assign lru_op_vec[8] = lru_rmt_vec[0] ^ lru_rmt_vec[1]; + assign lru_op_vec[9] = lru_rmt_vec[2] ^ lru_rmt_vec[3]; + assign lru_op_vec[10] = lru_rmt_vec[4] ^ lru_rmt_vec[5]; + assign lru_op_vec[11] = lru_rmt_vec[6] ^ lru_rmt_vec[7]; + assign lru_op_vec[12] = lru_rmt_vec[8] ^ lru_rmt_vec[9]; + assign lru_op_vec[13] = lru_rmt_vec[10] ^ lru_rmt_vec[11]; + assign lru_op_vec[14] = lru_rmt_vec[12] ^ lru_rmt_vec[13]; + assign lru_op_vec[15] = lru_rmt_vec[14] ^ lru_rmt_vec[15]; + + // RMT override value: Vp= OR(all RMT entries below and right of p) + assign lru_vp_vec[1] = (lru_rmt_vec[8] | lru_rmt_vec[9] | lru_rmt_vec[10] | lru_rmt_vec[11] | lru_rmt_vec[12] | lru_rmt_vec[13] | lru_rmt_vec[14] | lru_rmt_vec[15]); + assign lru_vp_vec[2] = (lru_rmt_vec[4] | lru_rmt_vec[5] | lru_rmt_vec[6] | lru_rmt_vec[7]); + assign lru_vp_vec[3] = (lru_rmt_vec[12] | lru_rmt_vec[13] | lru_rmt_vec[14] | lru_rmt_vec[15]); + assign lru_vp_vec[4] = (lru_rmt_vec[2] | lru_rmt_vec[3]); + assign lru_vp_vec[5] = (lru_rmt_vec[6] | lru_rmt_vec[7]); + assign lru_vp_vec[6] = (lru_rmt_vec[10] | lru_rmt_vec[11]); + assign lru_vp_vec[7] = (lru_rmt_vec[14] | lru_rmt_vec[15]); + assign lru_vp_vec[8] = lru_rmt_vec[1]; + assign lru_vp_vec[9] = lru_rmt_vec[3]; + assign lru_vp_vec[10] = lru_rmt_vec[5]; + assign lru_vp_vec[11] = lru_rmt_vec[7]; + assign lru_vp_vec[12] = lru_rmt_vec[9]; + assign lru_vp_vec[13] = lru_rmt_vec[11]; + assign lru_vp_vec[14] = lru_rmt_vec[13]; + assign lru_vp_vec[15] = lru_rmt_vec[15]; + + // mmucr1_q: 0-IRRE, 1-REE, 2-CEE, 3-csync_dis, 4-isync_dis, 5:6-IPEI, 7:8-ICTID/ITTID + +// Encoder for the LRU watermark psuedo-RMT +/* +//table_start +?TABLE lru_rmt_vec LISTING(final) OPTIMIZE PARMS(ON-SET, OFF-SET); +*INPUTS*==================*OUTPUTS*============* +| | | +| mmucr1_q | lru_rmt_vec | +| | watermark_q | | | +| | | | | | +| | | | | | +| | | | | 111111 | +| 012345678 0123 | 0123456789012345 | +*TYPE*====================+====================+ +| PPPPPPPPP PPPP | PPPPPPPPPPPPPPPP | +*OPTIMIZE*--------------->| AAAAAAAAAAAAAAAA | +*TERMS*===================+====================+ +| 1-------- ---- | 1111111111111111 | round-robin enabled +| 0-------- 0000 | 1000000000000000 | +| 0-------- 0001 | 1100000000000000 | +| 0-------- 0010 | 1110000000000000 | +| 0-------- 0011 | 1111000000000000 | +| 0-------- 0100 | 1111100000000000 | +| 0-------- 0101 | 1111110000000000 | +| 0-------- 0110 | 1111111000000000 | +| 0-------- 0111 | 1111111100000000 | +| 0-------- 1000 | 1111111110000000 | +| 0-------- 1001 | 1111111111000000 | +| 0-------- 1010 | 1111111111100000 | +| 0-------- 1011 | 1111111111110000 | +| 0-------- 1100 | 1111111111111000 | +| 0-------- 1101 | 1111111111111100 | +| 0-------- 1110 | 1111111111111110 | +| 0-------- 1111 | 1111111111111111 | +*END*=====================+====================+ +?TABLE END lru_rmt_vec; +//table_end +*/ + +/* +//table_start +?TABLE lru_watermark_mask LISTING(final) OPTIMIZE PARMS(ON-SET, OFF-SET); +*INPUTS*==================*OUTPUTS*===============* +| | | +| mmucr1_q | lru_watermark_mask | +| | watermark_q | | | +| | | | | | +| | | | | | +| | | | | 111111 | +| 012345678 0123 | 0123456789012345 | +*TYPE*====================+=======================+ +| PPPPPPPPP PPPP | PPPPPPPPPPPPPPPP | +*OPTIMIZE*--------------->| AAAAAAAAAAAAAAAA | +*TERMS*===================+=======================+ +| --------- 0000 | 0111111111111111 | +| --------- 0001 | 0011111111111111 | +| --------- 0010 | 0001111111111111 | +| --------- 0011 | 0000111111111111 | +| --------- 0100 | 0000011111111111 | +| --------- 0101 | 0000001111111111 | +| --------- 0110 | 0000000111111111 | +| --------- 0111 | 0000000011111111 | +| --------- 1000 | 0000000001111111 | +| --------- 1001 | 0000000000111111 | +| --------- 1010 | 0000000000011111 | +| --------- 1011 | 0000000000001111 | +| --------- 1100 | 0000000000000111 | +| --------- 1101 | 0000000000000011 | +| --------- 1110 | 0000000000000001 | +| --------- 1111 | 0000000000000000 | +*END*=====================+=======================+ +?TABLE END lru_watermark_mask; +//table_end +*/ + + assign entry_valid_watermarked = entry_valid_q | lru_watermark_mask; + + // lru_update_event + // 0: tlb reload + // 1: invalidate snoop + // 2: csync or isync enabled + // 3: eratwe WS=0 + // 4: fetch hit + // 5: iu2 cam write type events + // 6: iu2 cam invalidate type events + // 7: iu2 cam translation type events + // 8: superset, ex2 + // 9: superset, delayed to ex3 + +// logic for the LRU reset and set bit vectors +/* +//table_start +?TABLE lru_set_reset_vec LISTING(final) OPTIMIZE PARMS(ON-SET); +*INPUTS*======================================================*OUTPUTS*===========================* +| | | +| lru_update_event_q | lru_reset_vec | +| | entry_valid_watermarked | | lru_set_vec | +| | | lru_q | | | | +| | | | entry_match_q | | | | +| | | | | | | | | +| | | 111111 | 111111 | 111111 | | 111111 | 111111 | +| 012345678 0123456789012345 123456789012345 0123456789012345 | 123456789012345 123456789012345 | +*TYPE*========================================================+===================================+ +| PPPPPPPPP PPPPPPPPPPPPPPPP PPPPPPPPPPPPPPP PPPPPPPPPPPPPPPP | PPPPPPPPPPPPPPP PPPPPPPPPPPPPPP | +*OPTIMIZE*--------------------------------------------------->| AAAAAAAAAAAAAAA BBBBBBBBBBBBBBB | +*TERMS*=======================================================+===================================+ +| --------- 0--------------- --------------- ---------------- | 11-1---1------- 00-0---0------- | cam not full, point to a nonvalid entry +| --------- 10-------------- --------------- ---------------- | 11-1---0------- 00-0---1------- | +| --------- 110------------- --------------- ---------------- | 11-0----1------ 00-1----0------ | +| --------- 1110------------ --------------- ---------------- | 11-0----0------ 00-1----1------ | +| --------- 11110----------- --------------- ---------------- | 10--1----1----- 01--0----0----- | +| --------- 111110---------- --------------- ---------------- | 10--1----0----- 01--0----1----- | +| --------- 1111110--------- --------------- ---------------- | 10--0-----1---- 01--1-----0---- | +| --------- 11111110-------- --------------- ---------------- | 10--0-----0---- 01--1-----1---- | +| --------- 111111110------- --------------- ---------------- | 0-1--1-----1--- 1-0--0-----0--- | +| --------- 1111111110------ --------------- ---------------- | 0-1--1-----0--- 1-0--0-----1--- | +| --------- 11111111110----- --------------- ---------------- | 0-1--0------1-- 1-0--1------0-- | +| --------- 111111111110---- --------------- ---------------- | 0-1--0------0-- 1-0--1------1-- | +| --------- 1111111111110--- --------------- ---------------- | 0-0---1------1- 1-1---0------0- | +| --------- 11111111111110-- --------------- ---------------- | 0-0---1------0- 1-1---0------1- | +| --------- 111111111111110- --------------- ---------------- | 0-0---0-------1 1-1---1-------0 | +| --------- 1111111111111110 --------------- ---------------- | 0-0---0-------0 1-1---1-------1 | +| -----1--- 1111111111111111 00-0---0------- ---------------- | 00-0---0------- 11-1---1------- | cam full, write moves away from current lru +| -----1--- 1111111111111111 00-0---1------- ---------------- | 00-0---1------- 11-1---0------- | +| -----1--- 1111111111111111 00-1----0------ ---------------- | 00-1----0------ 11-0----1------ | +| -----1--- 1111111111111111 00-1----1------ ---------------- | 00-1----1------ 11-0----0------ | +| -----1--- 1111111111111111 01--0----0----- ---------------- | 01--0----0----- 10--1----1----- | +| -----1--- 1111111111111111 01--0----1----- ---------------- | 01--0----1----- 10--1----0----- | +| -----1--- 1111111111111111 01--1-----0---- ---------------- | 01--1-----0---- 10--0-----1---- | +| -----1--- 1111111111111111 01--1-----1---- ---------------- | 01--1-----1---- 10--0-----0---- | +| -----1--- 1111111111111111 1-0--0-----0--- ---------------- | 1-0--0-----0--- 0-1--1-----1--- | +| -----1--- 1111111111111111 1-0--0-----1--- ---------------- | 1-0--0-----1--- 0-1--1-----0--- | +| -----1--- 1111111111111111 1-0--1------0-- ---------------- | 1-0--1------0-- 0-1--0------1-- | +| -----1--- 1111111111111111 1-0--1------1-- ---------------- | 1-0--1------1-- 0-1--0------0-- | +| -----1--- 1111111111111111 1-1---0------0- ---------------- | 1-1---0------0- 0-0---1------1- | +| -----1--- 1111111111111111 1-1---0------1- ---------------- | 1-1---0------1- 0-0---1------0- | +| -----1--- 1111111111111111 1-1---1-------0 ---------------- | 1-1---1-------0 0-0---0-------1 | +| -----1--- 1111111111111111 1-1---1-------1 ---------------- | 1-1---1-------1 0-0---0-------0 | +| -----001- 1111111111111111 --------------- 1--------------- | 00-0---0------- 11-1---1------- | cam full, hit moves away from match entr +| -----001- 1111111111111111 --------------- 01-------------- | 00-0---1------- 11-1---0------- | +| -----001- 1111111111111111 --------------- 001------------- | 00-1----0------ 11-0----1------ | +| -----001- 1111111111111111 --------------- 0001------------ | 00-1----1------ 11-0----0------ | +| -----001- 1111111111111111 --------------- 00001----------- | 01--0----0----- 10--1----1----- | +| -----001- 1111111111111111 --------------- 000001---------- | 01--0----1----- 10--1----0----- | +| -----001- 1111111111111111 --------------- 0000001--------- | 01--1-----0---- 10--0-----1---- | +| -----001- 1111111111111111 --------------- 00000001-------- | 01--1-----1---- 10--0-----0---- | +| -----001- 1111111111111111 --------------- 000000001------- | 1-0--0-----0--- 0-1--1-----1--- | +| -----001- 1111111111111111 --------------- 0000000001------ | 1-0--0-----1--- 0-1--1-----0--- | +| -----001- 1111111111111111 --------------- 00000000001----- | 1-0--1------0-- 0-1--0------1-- | +| -----001- 1111111111111111 --------------- 000000000001---- | 1-0--1------1-- 0-1--0------0-- | +| -----001- 1111111111111111 --------------- 0000000000001--- | 1-1---0------0- 0-0---1------1- | +| -----001- 1111111111111111 --------------- 00000000000001-- | 1-1---0------1- 0-0---1------0- | +| -----001- 1111111111111111 --------------- 000000000000001- | 1-1---1-------0 0-0---0-------1 | +| -----001- 1111111111111111 --------------- 0000000000000001 | 1-1---1-------1 0-0---0-------0 | +*END*=========================================================+===================================+ +?TABLE END lru_set_reset_vec; +//table_end +*/ + + +// Encoder for the LRU selected entry +/* +//table_start +?TABLE lru_way_encode LISTING(final) OPTIMIZE PARMS(ON-SET, OFF-SET); +*INPUTS*==========================*OUTPUTS*==========* +| | | +| mmucr1_q | lru_way_encode | +| | lru_eff | | | +| | | | | | +| | | | | | +| | | 111111 | | | +| 012345678 123456789012345 | 0123 | +*TYPE*============================+==================+ +| PPPPPPPPP PPPPPPPPPPPPPPP | PPPP | +*OPTIMIZE*----------------------->| AAAA | +*TERMS*===========================+==================+ +| --------- 00-0---0------- | 0000 | +| --------- 00-0---1------- | 0001 | +| --------- 00-1----0------ | 0010 | +| --------- 00-1----1------ | 0011 | +| --------- 01--0----0----- | 0100 | +| --------- 01--0----1----- | 0101 | +| --------- 01--1-----0---- | 0110 | +| --------- 01--1-----1---- | 0111 | +| --------- 1-0--0-----0--- | 1000 | +| --------- 1-0--0-----1--- | 1001 | +| --------- 1-0--1------0-- | 1010 | +| --------- 1-0--1------1-- | 1011 | +| --------- 1-1---0------0- | 1100 | +| --------- 1-1---0------1- | 1101 | +| --------- 1-1---1-------0 | 1110 | +| --------- 1-1---1-------1 | 1111 | +*END*=============================+==================+ +?TABLE END lru_way_encode; +//table_end +*/ + + // power-on reset sequencer to load initial erat entries + always @(por_seq_q or init_alias or bcfg_q[0:106]) + begin: Por_Sequencer + por_wr_cam_val = 2'b0; + por_wr_array_val = 2'b0; + por_wr_cam_data = {cam_data_width{1'b0}}; + por_wr_array_data = {array_data_width{1'b0}}; + por_wr_entry = {num_entry_log2{1'b0}}; + + case (por_seq_q) + // install initial erat entry sequencer + PorSeq_Idle : + begin + por_wr_cam_val = 2'b0; + por_wr_array_val = 2'b0; + por_hold_req = {`THREADS{init_alias}}; + + if (init_alias == 1'b1) // reset is asserted + por_seq_d = PorSeq_Stg1; + else + por_seq_d = PorSeq_Idle; + end + PorSeq_Stg1 : + begin + // let cam see the reset gone + por_wr_cam_val = 2'b0; + por_wr_array_val = 2'b0; + por_seq_d = PorSeq_Stg2; + por_hold_req = {`THREADS{1'b1}}; + end + + PorSeq_Stg2 : + begin + // write cam entry 0 + por_wr_cam_val = {2{1'b1}}; + por_wr_array_val = {2{1'b1}}; + por_wr_entry = Por_Wr_Entry_Num1; + por_wr_cam_data = {bcfg_q[0:51], Por_Wr_Cam_Data1[52:83]}; + // 16x143 version, 42b RA + // wr_array_data + // 0:29 - RPN + // 30:31 - R,C + // 32:33 - WLC + // 34 - ResvAttr + // 35 - VF + // 36:39 - U0-U3 + // 40:44 - WIMGE + // 45:46 - UX,SX + // 47:48 - UW,SW + // 49:50 - UR,SR + // 51:60 - CAM parity + // 61:67 - Array parity + por_wr_array_data = {bcfg_q[52:81], Por_Wr_Array_Data1[30:35], bcfg_q[82:85], Por_Wr_Array_Data1[40:43], bcfg_q[86], Por_Wr_Array_Data1[45:67]}; // 16x143 version + por_hold_req = {`THREADS{1'b1}}; + por_seq_d = PorSeq_Stg3; + end + + PorSeq_Stg3 : + begin + // de-assert the cam write + por_wr_cam_val = 2'b0; + por_wr_array_val = 2'b0; + por_hold_req = {`THREADS{1'b1}}; + por_seq_d = PorSeq_Stg4; + end + + PorSeq_Stg4 : + begin + // write cam entry 1 + por_wr_cam_val = {2{1'b1}}; + por_wr_array_val = {2{1'b1}}; + por_wr_entry = Por_Wr_Entry_Num2; + por_wr_cam_data = Por_Wr_Cam_Data2; + + por_wr_array_data = {bcfg_q[52:61], bcfg_q[87:106], Por_Wr_Array_Data2[30:35], bcfg_q[82:85], Por_Wr_Array_Data2[40:43], bcfg_q[86], Por_Wr_Array_Data2[45:67]}; // same 22:31, unique 32:51 + por_hold_req = {`THREADS{1'b1}}; + por_seq_d = PorSeq_Stg5; + end + + PorSeq_Stg5 : + begin + // de-assert the cam write + por_wr_cam_val = 2'b0; + por_wr_array_val = 2'b0; + por_hold_req = {`THREADS{1'b1}}; + por_seq_d = PorSeq_Stg6; + end + + PorSeq_Stg6 : + begin + // release thread hold + por_wr_cam_val = 2'b0; + por_wr_array_val = 2'b0; + por_hold_req = {`THREADS{1'b0}}; + por_seq_d = PorSeq_Stg7; + end + + PorSeq_Stg7 : + begin + // all done.. hang out here until reset removed + por_wr_cam_val = 2'b0; + por_wr_array_val = 2'b0; + por_hold_req = {`THREADS{1'b0}}; + + if (init_alias == 1'b0) // reset removed, go idle + por_seq_d = PorSeq_Idle; + else + por_seq_d = PorSeq_Stg7; + end + + default : + por_seq_d = PorSeq_Idle; // go idle + endcase + end + + assign cam_pgsize[0:2] = (CAM_PgSize_1GB & {3{ex6_data_in_q[56:59] == WS0_PgSize_1GB }}) | + (CAM_PgSize_16MB & {3{ex6_data_in_q[56:59] == WS0_PgSize_16MB}}) | + (CAM_PgSize_1MB & {3{ex6_data_in_q[56:59] == WS0_PgSize_1MB }}) | + (CAM_PgSize_64KB & {3{ex6_data_in_q[56:59] == WS0_PgSize_64KB}}) | + (CAM_PgSize_4KB & {3{~((ex6_data_in_q[56:59] == WS0_PgSize_1GB) | + (ex6_data_in_q[56:59] == WS0_PgSize_16MB) | + (ex6_data_in_q[56:59] == WS0_PgSize_1MB) | + (ex6_data_in_q[56:59] == WS0_PgSize_64KB))}}); + + assign ws0_pgsize[0:3] = (WS0_PgSize_1GB & {4{rd_cam_data[53:55] == CAM_PgSize_1GB }}) | + (WS0_PgSize_16MB & {4{rd_cam_data[53:55] == CAM_PgSize_16MB}}) | + (WS0_PgSize_1MB & {4{rd_cam_data[53:55] == CAM_PgSize_1MB }}) | + (WS0_PgSize_64KB & {4{rd_cam_data[53:55] == CAM_PgSize_64KB}}) | + (WS0_PgSize_4KB & {4{rd_cam_data[53:55] == CAM_PgSize_4KB }}); + + // CAM control signal assignments + // ttype: eratre & eratwe & eratsx & erativax; + // mmucr1_q: 0-IRRE, 1-REE, 2-CEE, 3-csync_dis, 4-isync_dis, 5:6-IPEI, 7:8-ICTID/ITTID + + assign csinv_complete = |(cp_ic_csinv_comp_q[2:3]); // csync or isync enabled and complete + + assign rd_val = (|(ex2_valid_q)) & ex2_ttype_q[0] & (ex2_tlbsel_q == TlbSel_IErat); // eratre ttype + + assign rw_entry = (por_wr_entry & {4{|(por_seq_q)}}) | + (eptr_q & {4{(|(tlb_rel_val_q[0:3])) & tlb_rel_val_q[4] & mmucr1_q[0]}}) | // tlb hit reload, rrobin mode + (lru_way_encode & {4{(|(tlb_rel_val_q[0:3])) & tlb_rel_val_q[4] & (~mmucr1_q[0])}}) | // tlb hit reload LRU + (eptr_q & {4{(|(ex6_valid_q[0:`THREADS-1])) & ex6_ttype_q[1] & (ex6_tlbsel_q == TlbSel_IErat) & (~tlb_rel_val_q[4]) & mmucr1_q[0]}}) | // eratwe, rrobin mode + (ex6_ra_entry_q & {4{(|(ex6_valid_q[0:`THREADS-1])) & ex6_ttype_q[1] & (ex6_tlbsel_q == TlbSel_IErat) & (~tlb_rel_val_q[4]) & (~mmucr1_q[0])}}) | // eratwe + (ex2_ra_entry_q & {4{(|(ex2_valid_q)) & ex2_ttype_q[0] & (~( (|(ex6_valid_q[0:`THREADS - 1])) & ex6_ttype_q[1] & (ex6_tlbsel_q == TlbSel_IErat))) & (~tlb_rel_val_q[4])}}); // eratre + + // Write Port + // wr_cam_val(0) -> epn(0:51), xbit, size(0:2), V, ThdID, class(0:1), cmpmask(0:7), cmpmask_par + // wr_cam_val(1) -> extclass, tid_nz, gs, as, pid(6:13) + assign wr_cam_val = (por_seq_q != PorSeq_Idle) ? por_wr_cam_val : + (csinv_complete == 1'b1) ? 2'b0 : // csync or isync enabled and complete + (tlb_rel_val_q[0:3] != 4'b0000 & tlb_rel_val_q[4] == 1'b1) ? {2{tlb_rel_data_q[eratpos_wren]}} : // tlb hit reload + ((|(ex6_valid_q[0:`THREADS-1])) == 1'b1 & ex6_ttype_q[1] == 1'b1 & ex6_ws_q == 2'b00 & ex6_tlbsel_q == TlbSel_IErat) ? {2{1'b1}} : // eratwe WS=0 + 2'b0; + + // write port act pin + assign wr_val_early = (|(por_seq_q)) | + (|(tlb_req_inprogress_q)) | + ( (|(ex5_valid_q)) & ex5_ttype_q[1] & (ex5_ws_q == 2'b00) & (ex5_tlbsel_q == TlbSel_IErat)) | // ex5 eratwe WS=0 + ( (|(ex6_valid_q[0:`THREADS - 1])) & ex6_ttype_q[1] & (ex6_ws_q == 2'b00) & (ex6_tlbsel_q == TlbSel_IErat)); // ex6 eratwe WS=0 + + //state <= PR & GS or mmucr0(8) & IS or mmucr0(9) + + // tlb_low_data + // 0:51 - EPN + // 52:55 - SIZE (4b) + // 56:59 - ThdID + // 60:61 - Class + // 62 - ExtClass + // 63 - TID_NZ + // 64:65 - reserved (2b) + // 66:73 - 8b for LPID + // 74:83 - parity 10bits + + // wr_ws0_data (LO) + // 0:51 - EPN + // 52:53 - Class + // 54 - V + // 55 - X + // 56:59 - SIZE + // 60:63 - ThdID + + // wr_cam_data + // 0:51 - EPN + // 52 - X + // 53:55 - SIZE + // 56 - V + // 57:60 - ThdID + // 61:62 - Class + // 63:64 - ExtClass | TID_NZ + // 65 - TGS + // 66 - TS + // 67:74 - TID + // 75:78 - epn_cmpmasks: 34_39, 40_43, 44_47, 48_51 + // 79:82 - xbit_cmpmasks: 34_51, 40_51, 44_51, 48_51 + // 83 - parity for 75:82 + + //--------- this is what the erat expects on reload bus + // 0:51 - EPN + // 52 - X + // 53:55 - SIZE + // 56 - V + // 57:60 - ThdID + // 61:62 - Class + // 63:64 - ExtClass | TID_NZ + // 65 - write enable + + // 0:3 66:69 - reserved RPN + // 4:33 70:99 - RPN + // 34:35 100:101 - R,C + // 36 102 - reserved + // 37:38 103:104 - WLC + // 39 105 - ResvAttr + // 40 106 - VF + // 41:44 107:110 - U0-U3 + // 45:49 111:115 - WIMGE + // 50:51 116:117 - UX,SX + // 52:53 118:119 - UW,SW + // 54:55 120:121 - UR,SR + // 56 122 - GS + // 57 123 - TS + // 58:65 124:131 - TID lsbs + + // mmucr1_q: 0-IRRE, 1-REE, 2-CEE, 3-csync_dis, 4-isync_dis, 5:6-IPEI, 7:8-ICTID/ITTID + + generate + if (rs_data_width == 64) + begin : gen64_wr_cam_data + assign wr_cam_data = (por_wr_cam_data & {84{(por_seq_q[0] | por_seq_q[1] | por_seq_q[2])}}) | + (({tlb_rel_data_q[0:64], tlb_rel_data_q[122:131], tlb_rel_cmpmask[0:3], tlb_rel_xbitmask[0:3], tlb_rel_maskpar}) & + ({84{((tlb_rel_val_q[0] | tlb_rel_val_q[1] | tlb_rel_val_q[2] | tlb_rel_val_q[3]) & tlb_rel_val_q[4])}})) | + (({(ex6_data_in_q[0:31] & ({32{ex6_state_q[3]}})), ex6_data_in_q[32:51], + ex6_data_in_q[55], cam_pgsize[0:2], ex6_data_in_q[54], + (({ex6_data_in_q[60:61], 2'b00} & {4{~(mmucr1_q[8])}}) | (ex6_pid_q[pid_width-12 : pid_width-9] & {4{mmucr1_q[8]}})), + (( ex6_data_in_q[52:53] & {2{~(mmucr1_q[7])}}) | (ex6_pid_q[pid_width-14 : pid_width-13] & {2{mmucr1_q[7]}})), + ex6_extclass_q, ex6_state_q[1:2], ex6_pid_q[pid_width - 8:pid_width - 1], + ex6_data_cmpmask[0:3], ex6_data_xbitmask[0:3], ex6_data_maskpar}) & + ({84{(|(ex6_valid_q[0:`THREADS - 1]) & ex6_ttype_q[1] & (~ex6_ws_q[0]) & (~ex6_ws_q[1]) & (~tlb_rel_val_q[4]))}})); + end + endgenerate + + generate + if (rs_data_width == 32) + begin : gen32_wr_cam_data + assign wr_cam_data = (por_wr_cam_data & ({84{(por_seq_q[0] | por_seq_q[1] | por_seq_q[2])}})) | + (({tlb_rel_data_q[0:64], tlb_rel_data_q[122:131], tlb_rel_cmpmask[0:3], tlb_rel_xbitmask[0:3], tlb_rel_maskpar}) & + ({84{((tlb_rel_val_q[0] | tlb_rel_val_q[1] | tlb_rel_val_q[2] | tlb_rel_val_q[3]) & tlb_rel_val_q[4])}})) | + (({({32{1'b0}}), ex6_data_in_q[32:51], ex6_data_in_q[55], cam_pgsize[0:2], ex6_data_in_q[54], + (({ex6_data_in_q[60:61], 2'b00} & {4{~(mmucr1_q[8])}}) | (ex6_pid_q[pid_width-12 : pid_width-9] & {4{(mmucr1_q[8])}})), + (( ex6_data_in_q[52:53] & {2{~(mmucr1_q[7])}}) | (ex6_pid_q[pid_width-14 : pid_width-13] & {2{(mmucr1_q[7])}})), + ex6_extclass_q, ex6_state_q[1:2], ex6_pid_q[pid_width - 8:pid_width - 1], ex6_data_cmpmask[0:3], ex6_data_xbitmask[0:3], ex6_data_maskpar}) & + ({84{(|(ex6_valid_q[0:`THREADS - 1]) & ex6_ttype_q[1] & (~ex6_ws_q[0]) & (~ex6_ws_q[1]) & (~tlb_rel_val_q[4]))}})); + end + endgenerate + + // cmpmask(0) (1) (2) (3) xbitmask(0) (1) (2) (3) + // xbit pgsize 34_39 40_43 44_47 48_51 34_39 40_43 44_47 48_51 size + // 0 001 1 1 1 1 0 0 0 0 4K + // 0 011 1 1 1 0 0 0 0 0 64K + // 0 101 1 1 0 0 0 0 0 0 1M + // 0 111 1 0 0 0 0 0 0 0 16M + // 0 110 0 0 0 0 0 0 0 0 1G + // 1 001 1 1 1 1 0 0 0 0 4K + // 1 011 1 1 1 0 0 0 0 1 64K + // 1 101 1 1 0 0 0 0 1 0 1M + // 1 111 1 0 0 0 0 1 0 0 16M + // 1 110 0 0 0 0 1 0 0 0 1G + + +// Encoder for the cam compare mask bits write data +/* +//table_start +?TABLE cam_mask_bits LISTING(final) OPTIMIZE PARMS(ON-SET, OFF-SET); +*INPUTS*==================*OUTPUTS*===================================* +| | | +| tlb_rel_data_q | tlb_rel_cmpmask | +| | ex6_data_in_q | | tlb_rel_xbitmask | +| | | | | | tlb_rel_maskpar | +| | | | | | | ex6_data_cmpmask | +| | | | | | | | ex6_data_xbitmask | +| | | | | | | | | ex6_data_maskpar | +| | | | | | | | | | | +| 5555 55555 | | | | | | | | +| 2345 56789 | 0123 0123 | 0123 0123 | | +*TYPE*====================+===========================================+ +| PPPP PPPPP | PPPP PPPP P PPPP PPPP P | +*OPTIMIZE*--------------->| AAAA AAAA A AAAA AAAA A | +*TERMS*===================+===========================================+ +| 0001 ----- | 1111 0000 0 ---- ---- - | tlb reload, xbit=0, 4K +| 0011 ----- | 1110 0000 1 ---- ---- - | tlb reload, xbit=0, 64K +| 0101 ----- | 1100 0000 0 ---- ---- - | tlb reload, xbit=0, 1M +| 0111 ----- | 1000 0000 1 ---- ---- - | tlb reload, xbit=0, 16M +| 0110 ----- | 0000 0000 0 ---- ---- - | tlb reload, xbit=0, 1G +| 1001 ----- | 1111 0000 0 ---- ---- - | tlb reload, xbit=1, no xmask, 4K +| 1011 ----- | 1110 0001 0 ---- ---- - | tlb reload, xbit=1, xmask_48_51=1, 64K +| 1101 ----- | 1100 0010 1 ---- ---- - | tlb reload, xbit=1, xmask_44_51=1, 1M +| 1111 ----- | 1000 0100 0 ---- ---- - | tlb reload, xbit=1, xmask_40_51=1, 16M +| 1110 ----- | 0000 1000 1 ---- ---- - | tlb reload, xbit=1, xmask_34_51=1, 1G +| ---- 00001 | ---- ---- - 1111 0000 0 | eratwe, xbit=0, 4K +| ---- 00011 | ---- ---- - 1110 0000 1 | eratwe, xbit=0, 64K +| ---- 00101 | ---- ---- - 1100 0000 0 | eratwe, xbit=0, 1M +| ---- 00111 | ---- ---- - 1000 0000 1 | eratwe, xbit=0, 16M +| ---- 01010 | ---- ---- - 0000 0000 0 | eratwe, xbit=0, 1G +| ---- 00000 | ---- ---- - 1111 0000 0 | eratwe, xbit=0, default to 4K +| ---- 00010 | ---- ---- - 1111 0000 0 | eratwe, xbit=0, default to 4K +| ---- 00100 | ---- ---- - 1111 0000 0 | eratwe, xbit=0, default to 4K +| ---- 00110 | ---- ---- - 1111 0000 0 | eratwe, xbit=0, default to 4K +| ---- 01000 | ---- ---- - 1111 0000 0 | eratwe, xbit=0, default to 4K +| ---- 01001 | ---- ---- - 1111 0000 0 | eratwe, xbit=0, default to 4K +| ---- 01011 | ---- ---- - 1111 0000 0 | eratwe, xbit=0, default to 4K +| ---- 01100 | ---- ---- - 1111 0000 0 | eratwe, xbit=0, default to 4K +| ---- 01101 | ---- ---- - 1111 0000 0 | eratwe, xbit=0, default to 4K +| ---- 01110 | ---- ---- - 1111 0000 0 | eratwe, xbit=0, default to 4K +| ---- 01111 | ---- ---- - 1111 0000 0 | eratwe, xbit=0, default to 4K +| ---- 10001 | ---- ---- - 1111 0000 0 | eratwe, xbit=1, no xmask, 4K +| ---- 10011 | ---- ---- - 1110 0001 0 | eratwe, xbit=1, xmask_48_51=1, 64K +| ---- 10101 | ---- ---- - 1100 0010 1 | eratwe, xbit=1, xmask_44_51=1, 1M +| ---- 10111 | ---- ---- - 1000 0100 0 | eratwe, xbit=1, xmask_40_51=1, 16M +| ---- 11010 | ---- ---- - 0000 1000 1 | eratwe, xbit=1, xmask_34_51=1, 1G +| ---- 10000 | ---- ---- - 1111 0000 0 | eratwe, xbit=1, default to 4K +| ---- 10010 | ---- ---- - 1111 0000 0 | eratwe, xbit=1, default to 4K +| ---- 10100 | ---- ---- - 1111 0000 0 | eratwe, xbit=1, default to 4K +| ---- 10110 | ---- ---- - 1111 0000 0 | eratwe, xbit=1, default to 4K +| ---- 11000 | ---- ---- - 1111 0000 0 | eratwe, xbit=1, default to 4K +| ---- 11001 | ---- ---- - 1111 0000 0 | eratwe, xbit=1, default to 4K +| ---- 11011 | ---- ---- - 1111 0000 0 | eratwe, xbit=1, default to 4K +| ---- 11100 | ---- ---- - 1111 0000 0 | eratwe, xbit=1, default to 4K +| ---- 11101 | ---- ---- - 1111 0000 0 | eratwe, xbit=1, default to 4K +| ---- 11110 | ---- ---- - 1111 0000 0 | eratwe, xbit=1, default to 4K +| ---- 11111 | ---- ---- - 1111 0000 0 | eratwe, xbit=1, default to 4K +*END*=====================+===========================================+ +?TABLE END cam_mask_bits; +//table_end +*/ + +//assign_start + +assign iu1_multihit_b_pt[1] = + (({ entry_match[1] , entry_match[2] , + entry_match[3] , entry_match[4] , + entry_match[5] , entry_match[6] , + entry_match[7] , entry_match[8] , + entry_match[9] , entry_match[10] , + entry_match[11] , entry_match[12] , + entry_match[13] , entry_match[14] , + entry_match[15] }) === 15'b000000000000000); +assign iu1_multihit_b_pt[2] = + (({ entry_match[0] , entry_match[2] , + entry_match[3] , entry_match[4] , + entry_match[5] , entry_match[6] , + entry_match[7] , entry_match[8] , + entry_match[9] , entry_match[10] , + entry_match[11] , entry_match[12] , + entry_match[13] , entry_match[14] , + entry_match[15] }) === 15'b000000000000000); +assign iu1_multihit_b_pt[3] = + (({ entry_match[0] , entry_match[1] , + entry_match[3] , entry_match[4] , + entry_match[5] , entry_match[6] , + entry_match[7] , entry_match[8] , + entry_match[9] , entry_match[10] , + entry_match[11] , entry_match[12] , + entry_match[13] , entry_match[14] , + entry_match[15] }) === 15'b000000000000000); +assign iu1_multihit_b_pt[4] = + (({ entry_match[0] , entry_match[1] , + entry_match[2] , entry_match[4] , + entry_match[5] , entry_match[6] , + entry_match[7] , entry_match[8] , + entry_match[9] , entry_match[10] , + entry_match[11] , entry_match[12] , + entry_match[13] , entry_match[14] , + entry_match[15] }) === 15'b000000000000000); +assign iu1_multihit_b_pt[5] = + (({ entry_match[0] , entry_match[1] , + entry_match[2] , entry_match[3] , + entry_match[5] , entry_match[6] , + entry_match[7] , entry_match[8] , + entry_match[9] , entry_match[10] , + entry_match[11] , entry_match[12] , + entry_match[13] , entry_match[14] , + entry_match[15] }) === 15'b000000000000000); +assign iu1_multihit_b_pt[6] = + (({ entry_match[0] , entry_match[1] , + entry_match[2] , entry_match[3] , + entry_match[4] , entry_match[6] , + entry_match[7] , entry_match[8] , + entry_match[9] , entry_match[10] , + entry_match[11] , entry_match[12] , + entry_match[13] , entry_match[14] , + entry_match[15] }) === 15'b000000000000000); +assign iu1_multihit_b_pt[7] = + (({ entry_match[0] , entry_match[1] , + entry_match[2] , entry_match[3] , + entry_match[4] , entry_match[5] , + entry_match[7] , entry_match[8] , + entry_match[9] , entry_match[10] , + entry_match[11] , entry_match[12] , + entry_match[13] , entry_match[14] , + entry_match[15] }) === 15'b000000000000000); +assign iu1_multihit_b_pt[8] = + (({ entry_match[0] , entry_match[1] , + entry_match[2] , entry_match[3] , + entry_match[4] , entry_match[5] , + entry_match[6] , entry_match[8] , + entry_match[9] , entry_match[10] , + entry_match[11] , entry_match[12] , + entry_match[13] , entry_match[14] , + entry_match[15] }) === 15'b000000000000000); +assign iu1_multihit_b_pt[9] = + (({ entry_match[0] , entry_match[1] , + entry_match[2] , entry_match[3] , + entry_match[4] , entry_match[5] , + entry_match[6] , entry_match[7] , + entry_match[9] , entry_match[10] , + entry_match[11] , entry_match[12] , + entry_match[13] , entry_match[14] , + entry_match[15] }) === 15'b000000000000000); +assign iu1_multihit_b_pt[10] = + (({ entry_match[0] , entry_match[1] , + entry_match[2] , entry_match[3] , + entry_match[4] , entry_match[5] , + entry_match[6] , entry_match[7] , + entry_match[8] , entry_match[10] , + entry_match[11] , entry_match[12] , + entry_match[13] , entry_match[14] , + entry_match[15] }) === 15'b000000000000000); +assign iu1_multihit_b_pt[11] = + (({ entry_match[0] , entry_match[1] , + entry_match[2] , entry_match[3] , + entry_match[4] , entry_match[5] , + entry_match[6] , entry_match[7] , + entry_match[8] , entry_match[9] , + entry_match[11] , entry_match[12] , + entry_match[13] , entry_match[14] , + entry_match[15] }) === 15'b000000000000000); +assign iu1_multihit_b_pt[12] = + (({ entry_match[0] , entry_match[1] , + entry_match[2] , entry_match[3] , + entry_match[4] , entry_match[5] , + entry_match[6] , entry_match[7] , + entry_match[8] , entry_match[9] , + entry_match[10] , entry_match[12] , + entry_match[13] , entry_match[14] , + entry_match[15] }) === 15'b000000000000000); +assign iu1_multihit_b_pt[13] = + (({ entry_match[0] , entry_match[1] , + entry_match[2] , entry_match[3] , + entry_match[4] , entry_match[5] , + entry_match[6] , entry_match[7] , + entry_match[8] , entry_match[9] , + entry_match[10] , entry_match[11] , + entry_match[13] , entry_match[14] , + entry_match[15] }) === 15'b000000000000000); +assign iu1_multihit_b_pt[14] = + (({ entry_match[0] , entry_match[1] , + entry_match[2] , entry_match[3] , + entry_match[4] , entry_match[5] , + entry_match[6] , entry_match[7] , + entry_match[8] , entry_match[9] , + entry_match[10] , entry_match[11] , + entry_match[12] , entry_match[14] , + entry_match[15] }) === 15'b000000000000000); +assign iu1_multihit_b_pt[15] = + (({ entry_match[0] , entry_match[1] , + entry_match[2] , entry_match[3] , + entry_match[4] , entry_match[5] , + entry_match[6] , entry_match[7] , + entry_match[8] , entry_match[9] , + entry_match[10] , entry_match[11] , + entry_match[12] , entry_match[13] , + entry_match[15] }) === 15'b000000000000000); +assign iu1_multihit_b_pt[16] = + (({ entry_match[0] , entry_match[1] , + entry_match[2] , entry_match[3] , + entry_match[4] , entry_match[5] , + entry_match[6] , entry_match[7] , + entry_match[8] , entry_match[9] , + entry_match[10] , entry_match[11] , + entry_match[12] , entry_match[13] , + entry_match[14] }) === 15'b000000000000000); +assign iu1_multihit_b = + (iu1_multihit_b_pt[1] | iu1_multihit_b_pt[2] + | iu1_multihit_b_pt[3] | iu1_multihit_b_pt[4] + | iu1_multihit_b_pt[5] | iu1_multihit_b_pt[6] + | iu1_multihit_b_pt[7] | iu1_multihit_b_pt[8] + | iu1_multihit_b_pt[9] | iu1_multihit_b_pt[10] + | iu1_multihit_b_pt[11] | iu1_multihit_b_pt[12] + | iu1_multihit_b_pt[13] | iu1_multihit_b_pt[14] + | iu1_multihit_b_pt[15] | iu1_multihit_b_pt[16] + ); + +//assign_end +//assign_start + +assign iu1_first_hit_entry_pt[1] = + (({ entry_match[0] , entry_match[1] , + entry_match[2] , entry_match[3] , + entry_match[4] , entry_match[5] , + entry_match[6] , entry_match[7] , + entry_match[8] , entry_match[9] , + entry_match[10] , entry_match[11] , + entry_match[12] , entry_match[13] , + entry_match[14] , entry_match[15] + }) === 16'b0000000000000001); +assign iu1_first_hit_entry_pt[2] = + (({ entry_match[0] , entry_match[1] , + entry_match[2] , entry_match[3] , + entry_match[4] , entry_match[5] , + entry_match[6] , entry_match[7] , + entry_match[8] , entry_match[9] , + entry_match[10] , entry_match[11] , + entry_match[12] , entry_match[13] , + entry_match[14] }) === 15'b000000000000001); +assign iu1_first_hit_entry_pt[3] = + (({ entry_match[0] , entry_match[1] , + entry_match[2] , entry_match[3] , + entry_match[4] , entry_match[5] , + entry_match[6] , entry_match[7] , + entry_match[8] , entry_match[9] , + entry_match[10] , entry_match[11] , + entry_match[12] , entry_match[13] + }) === 14'b00000000000001); +assign iu1_first_hit_entry_pt[4] = + (({ entry_match[0] , entry_match[1] , + entry_match[2] , entry_match[3] , + entry_match[4] , entry_match[5] , + entry_match[6] , entry_match[7] , + entry_match[8] , entry_match[9] , + entry_match[10] , entry_match[11] , + entry_match[12] }) === 13'b0000000000001); +assign iu1_first_hit_entry_pt[5] = + (({ entry_match[0] , entry_match[1] , + entry_match[2] , entry_match[3] , + entry_match[4] , entry_match[5] , + entry_match[6] , entry_match[7] , + entry_match[8] , entry_match[9] , + entry_match[10] , entry_match[11] + }) === 12'b000000000001); +assign iu1_first_hit_entry_pt[6] = + (({ entry_match[0] , entry_match[1] , + entry_match[2] , entry_match[3] , + entry_match[4] , entry_match[5] , + entry_match[6] , entry_match[7] , + entry_match[8] , entry_match[9] , + entry_match[10] }) === 11'b00000000001); +assign iu1_first_hit_entry_pt[7] = + (({ entry_match[0] , entry_match[1] , + entry_match[2] , entry_match[3] , + entry_match[4] , entry_match[5] , + entry_match[6] , entry_match[7] , + entry_match[8] , entry_match[9] + }) === 10'b0000000001); +assign iu1_first_hit_entry_pt[8] = + (({ entry_match[0] , entry_match[1] , + entry_match[2] , entry_match[3] , + entry_match[4] , entry_match[5] , + entry_match[6] , entry_match[7] , + entry_match[8] }) === 9'b000000001); +assign iu1_first_hit_entry_pt[9] = + (({ entry_match[0] , entry_match[1] , + entry_match[2] , entry_match[3] , + entry_match[4] , entry_match[5] , + entry_match[6] , entry_match[7] + }) === 8'b00000001); +assign iu1_first_hit_entry_pt[10] = + (({ entry_match[0] , entry_match[1] , + entry_match[2] , entry_match[3] , + entry_match[4] , entry_match[5] , + entry_match[6] }) === 7'b0000001); +assign iu1_first_hit_entry_pt[11] = + (({ entry_match[0] , entry_match[1] , + entry_match[2] , entry_match[3] , + entry_match[4] , entry_match[5] + }) === 6'b000001); +assign iu1_first_hit_entry_pt[12] = + (({ entry_match[0] , entry_match[1] , + entry_match[2] , entry_match[3] , + entry_match[4] }) === 5'b00001); +assign iu1_first_hit_entry_pt[13] = + (({ entry_match[0] , entry_match[1] , + entry_match[2] , entry_match[3] + }) === 4'b0001); +assign iu1_first_hit_entry_pt[14] = + (({ entry_match[0] , entry_match[1] , + entry_match[2] }) === 3'b001); +assign iu1_first_hit_entry_pt[15] = + (({ entry_match[0] , entry_match[1] + }) === 2'b01); +assign iu1_first_hit_entry[0] = + (iu1_first_hit_entry_pt[1] | iu1_first_hit_entry_pt[2] + | iu1_first_hit_entry_pt[3] | iu1_first_hit_entry_pt[4] + | iu1_first_hit_entry_pt[5] | iu1_first_hit_entry_pt[6] + | iu1_first_hit_entry_pt[7] | iu1_first_hit_entry_pt[8] + ); +assign iu1_first_hit_entry[1] = + (iu1_first_hit_entry_pt[1] | iu1_first_hit_entry_pt[2] + | iu1_first_hit_entry_pt[3] | iu1_first_hit_entry_pt[4] + | iu1_first_hit_entry_pt[9] | iu1_first_hit_entry_pt[10] + | iu1_first_hit_entry_pt[11] | iu1_first_hit_entry_pt[12] + ); +assign iu1_first_hit_entry[2] = + (iu1_first_hit_entry_pt[1] | iu1_first_hit_entry_pt[2] + | iu1_first_hit_entry_pt[5] | iu1_first_hit_entry_pt[6] + | iu1_first_hit_entry_pt[9] | iu1_first_hit_entry_pt[10] + | iu1_first_hit_entry_pt[13] | iu1_first_hit_entry_pt[14] + ); +assign iu1_first_hit_entry[3] = + (iu1_first_hit_entry_pt[1] | iu1_first_hit_entry_pt[3] + | iu1_first_hit_entry_pt[5] | iu1_first_hit_entry_pt[7] + | iu1_first_hit_entry_pt[9] | iu1_first_hit_entry_pt[11] + | iu1_first_hit_entry_pt[13] | iu1_first_hit_entry_pt[15] + ); + +//assign_end +//assign_start + +assign lru_rmt_vec_pt[1] = + (({ watermark_q[0] , watermark_q[1] , + watermark_q[2] , watermark_q[3] + }) === 4'b1111); +assign lru_rmt_vec_pt[2] = + (({ watermark_q[1] , watermark_q[2] , + watermark_q[3] }) === 3'b111); +assign lru_rmt_vec_pt[3] = + (({ watermark_q[0] , watermark_q[2] , + watermark_q[3] }) === 3'b111); +assign lru_rmt_vec_pt[4] = + (({ watermark_q[2] , watermark_q[3] + }) === 2'b11); +assign lru_rmt_vec_pt[5] = + (({ watermark_q[0] , watermark_q[1] , + watermark_q[3] }) === 3'b111); +assign lru_rmt_vec_pt[6] = + (({ watermark_q[1] , watermark_q[3] + }) === 2'b11); +assign lru_rmt_vec_pt[7] = + (({ watermark_q[0] , watermark_q[3] + }) === 2'b11); +assign lru_rmt_vec_pt[8] = + (({ watermark_q[3] }) === 1'b1); +assign lru_rmt_vec_pt[9] = + (({ watermark_q[0] , watermark_q[1] , + watermark_q[2] }) === 3'b111); +assign lru_rmt_vec_pt[10] = + (({ watermark_q[1] , watermark_q[2] + }) === 2'b11); +assign lru_rmt_vec_pt[11] = + (({ watermark_q[0] , watermark_q[2] + }) === 2'b11); +assign lru_rmt_vec_pt[12] = + (({ watermark_q[2] }) === 1'b1); +assign lru_rmt_vec_pt[13] = + (({ watermark_q[0] , watermark_q[1] + }) === 2'b11); +assign lru_rmt_vec_pt[14] = + (({ watermark_q[1] }) === 1'b1); +assign lru_rmt_vec_pt[15] = + (({ watermark_q[0] }) === 1'b1); +assign lru_rmt_vec_pt[16] = + (({ mmucr1_q[0] }) === 1'b1); +assign lru_rmt_vec_pt[17] = + 1'b1; +assign lru_rmt_vec[0] = + (lru_rmt_vec_pt[17]); +assign lru_rmt_vec[1] = + (lru_rmt_vec_pt[8] | lru_rmt_vec_pt[12] + | lru_rmt_vec_pt[14] | lru_rmt_vec_pt[15] + | lru_rmt_vec_pt[16]); +assign lru_rmt_vec[2] = + (lru_rmt_vec_pt[12] | lru_rmt_vec_pt[14] + | lru_rmt_vec_pt[15] | lru_rmt_vec_pt[16] + ); +assign lru_rmt_vec[3] = + (lru_rmt_vec_pt[4] | lru_rmt_vec_pt[14] + | lru_rmt_vec_pt[15] | lru_rmt_vec_pt[16] + ); +assign lru_rmt_vec[4] = + (lru_rmt_vec_pt[14] | lru_rmt_vec_pt[15] + | lru_rmt_vec_pt[16]); +assign lru_rmt_vec[5] = + (lru_rmt_vec_pt[6] | lru_rmt_vec_pt[10] + | lru_rmt_vec_pt[15] | lru_rmt_vec_pt[16] + ); +assign lru_rmt_vec[6] = + (lru_rmt_vec_pt[10] | lru_rmt_vec_pt[15] + | lru_rmt_vec_pt[16]); +assign lru_rmt_vec[7] = + (lru_rmt_vec_pt[2] | lru_rmt_vec_pt[15] + | lru_rmt_vec_pt[16]); +assign lru_rmt_vec[8] = + (lru_rmt_vec_pt[15] | lru_rmt_vec_pt[16] + ); +assign lru_rmt_vec[9] = + (lru_rmt_vec_pt[7] | lru_rmt_vec_pt[11] + | lru_rmt_vec_pt[13] | lru_rmt_vec_pt[16] + ); +assign lru_rmt_vec[10] = + (lru_rmt_vec_pt[11] | lru_rmt_vec_pt[13] + | lru_rmt_vec_pt[16]); +assign lru_rmt_vec[11] = + (lru_rmt_vec_pt[3] | lru_rmt_vec_pt[13] + | lru_rmt_vec_pt[16]); +assign lru_rmt_vec[12] = + (lru_rmt_vec_pt[13] | lru_rmt_vec_pt[16] + ); +assign lru_rmt_vec[13] = + (lru_rmt_vec_pt[5] | lru_rmt_vec_pt[9] + | lru_rmt_vec_pt[16]); +assign lru_rmt_vec[14] = + (lru_rmt_vec_pt[9] | lru_rmt_vec_pt[16] + ); +assign lru_rmt_vec[15] = + (lru_rmt_vec_pt[1] | lru_rmt_vec_pt[16] + ); + +//assign_end +//assign_start + +assign lru_watermark_mask_pt[1] = + (({ watermark_q[0] , watermark_q[1] , + watermark_q[2] , watermark_q[3] + }) === 4'b0000); +assign lru_watermark_mask_pt[2] = + (({ watermark_q[1] , watermark_q[2] , + watermark_q[3] }) === 3'b000); +assign lru_watermark_mask_pt[3] = + (({ watermark_q[0] , watermark_q[2] , + watermark_q[3] }) === 3'b000); +assign lru_watermark_mask_pt[4] = + (({ watermark_q[2] , watermark_q[3] + }) === 2'b00); +assign lru_watermark_mask_pt[5] = + (({ watermark_q[0] , watermark_q[1] , + watermark_q[3] }) === 3'b000); +assign lru_watermark_mask_pt[6] = + (({ watermark_q[1] , watermark_q[3] + }) === 2'b00); +assign lru_watermark_mask_pt[7] = + (({ watermark_q[0] , watermark_q[3] + }) === 2'b00); +assign lru_watermark_mask_pt[8] = + (({ watermark_q[3] }) === 1'b0); +assign lru_watermark_mask_pt[9] = + (({ watermark_q[0] , watermark_q[1] , + watermark_q[2] }) === 3'b000); +assign lru_watermark_mask_pt[10] = + (({ watermark_q[1] , watermark_q[2] + }) === 2'b00); +assign lru_watermark_mask_pt[11] = + (({ watermark_q[0] , watermark_q[2] + }) === 2'b00); +assign lru_watermark_mask_pt[12] = + (({ watermark_q[2] }) === 1'b0); +assign lru_watermark_mask_pt[13] = + (({ watermark_q[0] , watermark_q[1] + }) === 2'b00); +assign lru_watermark_mask_pt[14] = + (({ watermark_q[1] }) === 1'b0); +assign lru_watermark_mask_pt[15] = + (({ watermark_q[0] }) === 1'b0); +assign lru_watermark_mask[0] = + 1'b0; +assign lru_watermark_mask[1] = + (lru_watermark_mask_pt[1]); +assign lru_watermark_mask[2] = + (lru_watermark_mask_pt[9]); +assign lru_watermark_mask[3] = + (lru_watermark_mask_pt[5] | lru_watermark_mask_pt[9] + ); +assign lru_watermark_mask[4] = + (lru_watermark_mask_pt[13]); +assign lru_watermark_mask[5] = + (lru_watermark_mask_pt[3] | lru_watermark_mask_pt[13] + ); +assign lru_watermark_mask[6] = + (lru_watermark_mask_pt[11] | lru_watermark_mask_pt[13] + ); +assign lru_watermark_mask[7] = + (lru_watermark_mask_pt[7] | lru_watermark_mask_pt[11] + | lru_watermark_mask_pt[13]); +assign lru_watermark_mask[8] = + (lru_watermark_mask_pt[15]); +assign lru_watermark_mask[9] = + (lru_watermark_mask_pt[2] | lru_watermark_mask_pt[15] + ); +assign lru_watermark_mask[10] = + (lru_watermark_mask_pt[10] | lru_watermark_mask_pt[15] + ); +assign lru_watermark_mask[11] = + (lru_watermark_mask_pt[6] | lru_watermark_mask_pt[10] + | lru_watermark_mask_pt[15]); +assign lru_watermark_mask[12] = + (lru_watermark_mask_pt[14] | lru_watermark_mask_pt[15] + ); +assign lru_watermark_mask[13] = + (lru_watermark_mask_pt[4] | lru_watermark_mask_pt[14] + | lru_watermark_mask_pt[15]); +assign lru_watermark_mask[14] = + (lru_watermark_mask_pt[12] | lru_watermark_mask_pt[14] + | lru_watermark_mask_pt[15]); +assign lru_watermark_mask[15] = + (lru_watermark_mask_pt[8] | lru_watermark_mask_pt[12] + | lru_watermark_mask_pt[14] | lru_watermark_mask_pt[15] + ); + +//assign_end +//assign_start + +assign lru_set_reset_vec_pt[1] = + (({ lru_update_event_q[5] , lru_update_event_q[6] , + lru_update_event_q[7] , entry_valid_watermarked[0] , + entry_valid_watermarked[1] , entry_valid_watermarked[2] , + entry_valid_watermarked[3] , entry_valid_watermarked[4] , + entry_valid_watermarked[5] , entry_valid_watermarked[6] , + entry_valid_watermarked[7] , entry_valid_watermarked[8] , + entry_valid_watermarked[9] , entry_valid_watermarked[10] , + entry_valid_watermarked[11] , entry_valid_watermarked[12] , + entry_valid_watermarked[13] , entry_valid_watermarked[14] , + entry_valid_watermarked[15] , entry_match_q[0] , + entry_match_q[1] , entry_match_q[2] , + entry_match_q[3] , entry_match_q[4] , + entry_match_q[5] , entry_match_q[6] , + entry_match_q[7] , entry_match_q[8] , + entry_match_q[9] , entry_match_q[10] , + entry_match_q[11] , entry_match_q[12] , + entry_match_q[13] , entry_match_q[14] , + entry_match_q[15] }) === 35'b00111111111111111110000000000000001); +assign lru_set_reset_vec_pt[2] = + (({ lru_update_event_q[5] , lru_update_event_q[6] , + lru_update_event_q[7] , entry_valid_watermarked[0] , + entry_valid_watermarked[1] , entry_valid_watermarked[2] , + entry_valid_watermarked[3] , entry_valid_watermarked[4] , + entry_valid_watermarked[5] , entry_valid_watermarked[6] , + entry_valid_watermarked[7] , entry_valid_watermarked[8] , + entry_valid_watermarked[9] , entry_valid_watermarked[10] , + entry_valid_watermarked[11] , entry_valid_watermarked[12] , + entry_valid_watermarked[13] , entry_valid_watermarked[14] , + entry_valid_watermarked[15] , entry_match_q[0] , + entry_match_q[1] , entry_match_q[2] , + entry_match_q[3] , entry_match_q[4] , + entry_match_q[5] , entry_match_q[6] , + entry_match_q[7] , entry_match_q[8] , + entry_match_q[9] , entry_match_q[10] , + entry_match_q[11] , entry_match_q[12] , + entry_match_q[13] , entry_match_q[14] + }) === 34'b0011111111111111111000000000000001); +assign lru_set_reset_vec_pt[3] = + (({ lru_update_event_q[5] , lru_update_event_q[6] , + lru_update_event_q[7] , entry_valid_watermarked[0] , + entry_valid_watermarked[1] , entry_valid_watermarked[2] , + entry_valid_watermarked[3] , entry_valid_watermarked[4] , + entry_valid_watermarked[5] , entry_valid_watermarked[6] , + entry_valid_watermarked[7] , entry_valid_watermarked[8] , + entry_valid_watermarked[9] , entry_valid_watermarked[10] , + entry_valid_watermarked[11] , entry_valid_watermarked[12] , + entry_valid_watermarked[13] , entry_valid_watermarked[14] , + entry_match_q[0] , entry_match_q[1] , + entry_match_q[2] , entry_match_q[3] , + entry_match_q[4] , entry_match_q[5] , + entry_match_q[6] , entry_match_q[7] , + entry_match_q[8] , entry_match_q[9] , + entry_match_q[10] , entry_match_q[11] , + entry_match_q[12] , entry_match_q[13] , + entry_match_q[14] }) === 33'b001111111111111111000000000000001); +assign lru_set_reset_vec_pt[4] = + (({ lru_update_event_q[5] , lru_update_event_q[6] , + lru_update_event_q[7] , entry_valid_watermarked[0] , + entry_valid_watermarked[1] , entry_valid_watermarked[2] , + entry_valid_watermarked[3] , entry_valid_watermarked[4] , + entry_valid_watermarked[5] , entry_valid_watermarked[6] , + entry_valid_watermarked[7] , entry_valid_watermarked[8] , + entry_valid_watermarked[9] , entry_valid_watermarked[10] , + entry_valid_watermarked[11] , entry_valid_watermarked[12] , + entry_valid_watermarked[13] , entry_valid_watermarked[14] , + entry_valid_watermarked[15] , entry_match_q[0] , + entry_match_q[1] , entry_match_q[2] , + entry_match_q[3] , entry_match_q[4] , + entry_match_q[5] , entry_match_q[6] , + entry_match_q[7] , entry_match_q[8] , + entry_match_q[9] , entry_match_q[10] , + entry_match_q[11] , entry_match_q[12] , + entry_match_q[13] }) === 33'b001111111111111111100000000000001); +assign lru_set_reset_vec_pt[5] = + (({ lru_update_event_q[5] , lru_update_event_q[6] , + lru_update_event_q[7] , entry_valid_watermarked[0] , + entry_valid_watermarked[1] , entry_valid_watermarked[2] , + entry_valid_watermarked[3] , entry_valid_watermarked[4] , + entry_valid_watermarked[5] , entry_valid_watermarked[6] , + entry_valid_watermarked[7] , entry_valid_watermarked[8] , + entry_valid_watermarked[9] , entry_valid_watermarked[10] , + entry_valid_watermarked[11] , entry_valid_watermarked[12] , + entry_valid_watermarked[13] , entry_match_q[0] , + entry_match_q[1] , entry_match_q[2] , + entry_match_q[3] , entry_match_q[4] , + entry_match_q[5] , entry_match_q[6] , + entry_match_q[7] , entry_match_q[8] , + entry_match_q[9] , entry_match_q[10] , + entry_match_q[11] , entry_match_q[13] + }) === 30'b001111111111111110000000000001); +assign lru_set_reset_vec_pt[6] = + (({ lru_update_event_q[5] , lru_update_event_q[6] , + lru_update_event_q[7] , entry_valid_watermarked[0] , + entry_valid_watermarked[1] , entry_valid_watermarked[2] , + entry_valid_watermarked[3] , entry_valid_watermarked[4] , + entry_valid_watermarked[5] , entry_valid_watermarked[6] , + entry_valid_watermarked[7] , entry_valid_watermarked[8] , + entry_valid_watermarked[9] , entry_valid_watermarked[10] , + entry_valid_watermarked[11] , entry_valid_watermarked[12] , + entry_valid_watermarked[13] , entry_valid_watermarked[14] , + entry_valid_watermarked[15] , entry_match_q[0] , + entry_match_q[1] , entry_match_q[2] , + entry_match_q[3] , entry_match_q[4] , + entry_match_q[5] , entry_match_q[6] , + entry_match_q[7] , entry_match_q[8] , + entry_match_q[9] , entry_match_q[10] , + entry_match_q[11] , entry_match_q[12] + }) === 32'b00111111111111111110000000000001); +assign lru_set_reset_vec_pt[7] = + (({ lru_update_event_q[5] , lru_update_event_q[6] , + lru_update_event_q[7] , entry_valid_watermarked[0] , + entry_valid_watermarked[1] , entry_valid_watermarked[2] , + entry_valid_watermarked[3] , entry_valid_watermarked[4] , + entry_valid_watermarked[5] , entry_valid_watermarked[6] , + entry_valid_watermarked[7] , entry_valid_watermarked[8] , + entry_valid_watermarked[9] , entry_valid_watermarked[10] , + entry_valid_watermarked[11] , entry_valid_watermarked[12] , + entry_valid_watermarked[13] , entry_valid_watermarked[14] , + entry_valid_watermarked[15] , entry_match_q[0] , + entry_match_q[1] , entry_match_q[2] , + entry_match_q[3] , entry_match_q[4] , + entry_match_q[5] , entry_match_q[6] , + entry_match_q[7] , entry_match_q[8] , + entry_match_q[9] , entry_match_q[10] , + entry_match_q[11] }) === 31'b0011111111111111111000000000001); +assign lru_set_reset_vec_pt[8] = + (({ lru_update_event_q[5] , lru_update_event_q[6] , + lru_update_event_q[7] , entry_valid_watermarked[0] , + entry_valid_watermarked[1] , entry_valid_watermarked[2] , + entry_valid_watermarked[3] , entry_valid_watermarked[4] , + entry_valid_watermarked[5] , entry_valid_watermarked[6] , + entry_valid_watermarked[7] , entry_valid_watermarked[8] , + entry_valid_watermarked[9] , entry_valid_watermarked[10] , + entry_valid_watermarked[11] , entry_match_q[0] , + entry_match_q[1] , entry_match_q[2] , + entry_match_q[3] , entry_match_q[4] , + entry_match_q[5] , entry_match_q[6] , + entry_match_q[7] , entry_match_q[11] + }) === 24'b001111111111111000000001); +assign lru_set_reset_vec_pt[9] = + (({ lru_update_event_q[5] , lru_update_event_q[6] , + lru_update_event_q[7] , entry_valid_watermarked[0] , + entry_valid_watermarked[1] , entry_valid_watermarked[2] , + entry_valid_watermarked[3] , entry_valid_watermarked[4] , + entry_valid_watermarked[5] , entry_valid_watermarked[6] , + entry_valid_watermarked[7] , entry_valid_watermarked[8] , + entry_valid_watermarked[9] , entry_valid_watermarked[10] , + entry_valid_watermarked[11] , entry_valid_watermarked[12] , + entry_valid_watermarked[13] , entry_valid_watermarked[14] , + entry_valid_watermarked[15] , entry_match_q[0] , + entry_match_q[1] , entry_match_q[2] , + entry_match_q[3] , entry_match_q[4] , + entry_match_q[5] , entry_match_q[6] , + entry_match_q[7] , entry_match_q[8] , + entry_match_q[9] , entry_match_q[10] + }) === 30'b001111111111111111100000000001); +assign lru_set_reset_vec_pt[10] = + (({ lru_update_event_q[5] , lru_update_event_q[6] , + lru_update_event_q[7] , entry_valid_watermarked[0] , + entry_valid_watermarked[1] , entry_valid_watermarked[2] , + entry_valid_watermarked[3] , entry_valid_watermarked[4] , + entry_valid_watermarked[5] , entry_valid_watermarked[6] , + entry_valid_watermarked[7] , entry_valid_watermarked[8] , + entry_valid_watermarked[9] , entry_valid_watermarked[10] , + entry_valid_watermarked[11] , entry_valid_watermarked[12] , + entry_valid_watermarked[13] , entry_valid_watermarked[14] , + entry_valid_watermarked[15] , entry_match_q[0] , + entry_match_q[1] , entry_match_q[2] , + entry_match_q[3] , entry_match_q[4] , + entry_match_q[5] , entry_match_q[6] , + entry_match_q[7] , entry_match_q[8] , + entry_match_q[9] }) === 29'b00111111111111111110000000001); +assign lru_set_reset_vec_pt[11] = + (({ lru_update_event_q[5] , lru_update_event_q[6] , + lru_update_event_q[7] , entry_valid_watermarked[0] , + entry_valid_watermarked[1] , entry_valid_watermarked[2] , + entry_valid_watermarked[3] , entry_valid_watermarked[4] , + entry_valid_watermarked[5] , entry_valid_watermarked[6] , + entry_valid_watermarked[7] , entry_valid_watermarked[8] , + entry_valid_watermarked[9] , entry_valid_watermarked[10] , + entry_valid_watermarked[11] , entry_valid_watermarked[12] , + entry_valid_watermarked[13] , entry_valid_watermarked[14] , + entry_valid_watermarked[15] , entry_match_q[0] , + entry_match_q[1] , entry_match_q[2] , + entry_match_q[3] , entry_match_q[4] , + entry_match_q[5] , entry_match_q[6] , + entry_match_q[7] , entry_match_q[9] + }) === 28'b0011111111111111111000000001); +assign lru_set_reset_vec_pt[12] = + (({ lru_update_event_q[5] , lru_update_event_q[6] , + lru_update_event_q[7] , entry_valid_watermarked[0] , + entry_valid_watermarked[1] , entry_valid_watermarked[2] , + entry_valid_watermarked[3] , entry_valid_watermarked[4] , + entry_valid_watermarked[5] , entry_valid_watermarked[6] , + entry_valid_watermarked[7] , entry_valid_watermarked[8] , + entry_valid_watermarked[9] , entry_valid_watermarked[10] , + entry_valid_watermarked[11] , entry_valid_watermarked[12] , + entry_valid_watermarked[13] , entry_valid_watermarked[14] , + entry_valid_watermarked[15] , entry_match_q[0] , + entry_match_q[1] , entry_match_q[2] , + entry_match_q[3] , entry_match_q[4] , + entry_match_q[5] , entry_match_q[6] , + entry_match_q[7] , entry_match_q[8] + }) === 28'b0011111111111111111000000001); +assign lru_set_reset_vec_pt[13] = + (({ lru_update_event_q[5] , lru_update_event_q[6] , + lru_update_event_q[7] , entry_valid_watermarked[8] , + entry_valid_watermarked[9] , entry_valid_watermarked[10] , + entry_valid_watermarked[11] , entry_valid_watermarked[12] , + entry_valid_watermarked[13] , entry_valid_watermarked[14] , + entry_valid_watermarked[15] , entry_match_q[0] , + entry_match_q[1] , entry_match_q[2] , + entry_match_q[3] , entry_match_q[4] , + entry_match_q[5] , entry_match_q[6] , + entry_match_q[7] , entry_match_q[8] + }) === 20'b00111111111000000001); +assign lru_set_reset_vec_pt[14] = + (({ lru_update_event_q[5] , lru_update_event_q[6] , + lru_update_event_q[7] , entry_valid_watermarked[0] , + entry_valid_watermarked[1] , entry_valid_watermarked[2] , + entry_valid_watermarked[3] , entry_valid_watermarked[4] , + entry_valid_watermarked[5] , entry_valid_watermarked[6] , + entry_valid_watermarked[7] , entry_valid_watermarked[8] , + entry_valid_watermarked[9] , entry_valid_watermarked[10] , + entry_valid_watermarked[11] , entry_valid_watermarked[12] , + entry_valid_watermarked[13] , entry_valid_watermarked[14] , + entry_valid_watermarked[15] , entry_match_q[0] , + entry_match_q[1] , entry_match_q[2] , + entry_match_q[3] , entry_match_q[4] , + entry_match_q[5] , entry_match_q[6] , + entry_match_q[7] }) === 27'b001111111111111111100000001); +assign lru_set_reset_vec_pt[15] = + (({ lru_update_event_q[5] , lru_update_event_q[6] , + lru_update_event_q[7] , entry_valid_watermarked[0] , + entry_valid_watermarked[1] , entry_valid_watermarked[2] , + entry_valid_watermarked[3] , entry_valid_watermarked[4] , + entry_valid_watermarked[5] , entry_valid_watermarked[6] , + entry_valid_watermarked[7] , entry_match_q[7] + }) === 12'b001111111111); +assign lru_set_reset_vec_pt[16] = + (({ lru_update_event_q[5] , lru_update_event_q[6] , + lru_update_event_q[7] , entry_valid_watermarked[0] , + entry_valid_watermarked[1] , entry_valid_watermarked[2] , + entry_valid_watermarked[3] , entry_valid_watermarked[4] , + entry_valid_watermarked[5] , entry_valid_watermarked[6] , + entry_valid_watermarked[7] , entry_valid_watermarked[8] , + entry_valid_watermarked[9] , entry_valid_watermarked[10] , + entry_valid_watermarked[11] , entry_valid_watermarked[12] , + entry_valid_watermarked[13] , entry_valid_watermarked[14] , + entry_valid_watermarked[15] , entry_match_q[0] , + entry_match_q[1] , entry_match_q[2] , + entry_match_q[3] , entry_match_q[4] , + entry_match_q[5] , entry_match_q[6] + }) === 26'b00111111111111111110000001); +assign lru_set_reset_vec_pt[17] = + (({ lru_update_event_q[5] , lru_update_event_q[6] , + lru_update_event_q[7] , entry_valid_watermarked[0] , + entry_valid_watermarked[1] , entry_valid_watermarked[2] , + entry_valid_watermarked[3] , entry_valid_watermarked[4] , + entry_valid_watermarked[5] , entry_valid_watermarked[6] , + entry_valid_watermarked[7] , entry_valid_watermarked[8] , + entry_valid_watermarked[9] , entry_valid_watermarked[10] , + entry_valid_watermarked[11] , entry_valid_watermarked[12] , + entry_valid_watermarked[13] , entry_valid_watermarked[14] , + entry_valid_watermarked[15] , entry_match_q[0] , + entry_match_q[1] , entry_match_q[2] , + entry_match_q[3] , entry_match_q[4] , + entry_match_q[5] }) === 25'b0011111111111111111000001); +assign lru_set_reset_vec_pt[18] = + (({ lru_update_event_q[5] , lru_update_event_q[6] , + lru_update_event_q[7] , entry_valid_watermarked[0] , + entry_valid_watermarked[1] , entry_valid_watermarked[2] , + entry_valid_watermarked[3] , entry_valid_watermarked[4] , + entry_valid_watermarked[5] , entry_valid_watermarked[6] , + entry_valid_watermarked[7] , entry_valid_watermarked[8] , + entry_valid_watermarked[9] , entry_valid_watermarked[10] , + entry_valid_watermarked[11] , entry_valid_watermarked[12] , + entry_valid_watermarked[13] , entry_valid_watermarked[14] , + entry_valid_watermarked[15] , entry_match_q[0] , + entry_match_q[1] , entry_match_q[2] , + entry_match_q[3] , entry_match_q[5] + }) === 24'b001111111111111111100001); +assign lru_set_reset_vec_pt[19] = + (({ lru_update_event_q[5] , lru_update_event_q[6] , + lru_update_event_q[7] , entry_valid_watermarked[0] , + entry_valid_watermarked[1] , entry_valid_watermarked[2] , + entry_valid_watermarked[3] , entry_valid_watermarked[4] , + entry_valid_watermarked[5] , entry_valid_watermarked[6] , + entry_valid_watermarked[7] , entry_valid_watermarked[8] , + entry_valid_watermarked[9] , entry_valid_watermarked[10] , + entry_valid_watermarked[11] , entry_valid_watermarked[12] , + entry_valid_watermarked[13] , entry_valid_watermarked[14] , + entry_valid_watermarked[15] , entry_match_q[0] , + entry_match_q[1] , entry_match_q[2] , + entry_match_q[3] , entry_match_q[4] + }) === 24'b001111111111111111100001); +assign lru_set_reset_vec_pt[20] = + (({ lru_update_event_q[5] , lru_update_event_q[6] , + lru_update_event_q[7] , entry_valid_watermarked[4] , + entry_valid_watermarked[5] , entry_valid_watermarked[6] , + entry_valid_watermarked[7] , entry_valid_watermarked[8] , + entry_valid_watermarked[9] , entry_valid_watermarked[10] , + entry_valid_watermarked[11] , entry_valid_watermarked[12] , + entry_valid_watermarked[13] , entry_valid_watermarked[14] , + entry_valid_watermarked[15] , entry_match_q[0] , + entry_match_q[1] , entry_match_q[2] , + entry_match_q[3] , entry_match_q[4] + }) === 20'b00111111111111100001); +assign lru_set_reset_vec_pt[21] = + (({ lru_update_event_q[5] , lru_update_event_q[6] , + lru_update_event_q[7] , entry_valid_watermarked[0] , + entry_valid_watermarked[1] , entry_valid_watermarked[2] , + entry_valid_watermarked[3] , entry_valid_watermarked[4] , + entry_valid_watermarked[5] , entry_valid_watermarked[6] , + entry_valid_watermarked[7] , entry_valid_watermarked[8] , + entry_valid_watermarked[9] , entry_valid_watermarked[10] , + entry_valid_watermarked[11] , entry_valid_watermarked[12] , + entry_valid_watermarked[13] , entry_valid_watermarked[14] , + entry_valid_watermarked[15] , entry_match_q[0] , + entry_match_q[1] , entry_match_q[2] , + entry_match_q[3] }) === 23'b00111111111111111110001); +assign lru_set_reset_vec_pt[22] = + (({ lru_update_event_q[5] , lru_update_event_q[6] , + lru_update_event_q[7] , entry_valid_watermarked[0] , + entry_valid_watermarked[1] , entry_valid_watermarked[2] , + entry_valid_watermarked[3] , entry_valid_watermarked[4] , + entry_valid_watermarked[5] , entry_valid_watermarked[6] , + entry_valid_watermarked[7] , entry_valid_watermarked[8] , + entry_valid_watermarked[9] , entry_valid_watermarked[10] , + entry_valid_watermarked[11] , entry_valid_watermarked[12] , + entry_valid_watermarked[13] , entry_valid_watermarked[14] , + entry_valid_watermarked[15] , entry_match_q[3] + }) === 20'b00111111111111111111); +assign lru_set_reset_vec_pt[23] = + (({ lru_update_event_q[5] , lru_update_event_q[6] , + lru_update_event_q[7] , entry_valid_watermarked[0] , + entry_valid_watermarked[1] , entry_valid_watermarked[2] , + entry_valid_watermarked[3] , entry_valid_watermarked[4] , + entry_valid_watermarked[5] , entry_valid_watermarked[6] , + entry_valid_watermarked[7] , entry_valid_watermarked[8] , + entry_valid_watermarked[9] , entry_valid_watermarked[10] , + entry_valid_watermarked[11] , entry_valid_watermarked[12] , + entry_valid_watermarked[13] , entry_valid_watermarked[14] , + entry_valid_watermarked[15] , entry_match_q[0] , + entry_match_q[1] , entry_match_q[2] + }) === 22'b0011111111111111111001); +assign lru_set_reset_vec_pt[24] = + (({ lru_update_event_q[5] , lru_update_event_q[6] , + lru_update_event_q[7] , entry_valid_watermarked[2] , + entry_valid_watermarked[3] , entry_valid_watermarked[4] , + entry_valid_watermarked[5] , entry_valid_watermarked[6] , + entry_valid_watermarked[7] , entry_valid_watermarked[8] , + entry_valid_watermarked[9] , entry_valid_watermarked[10] , + entry_valid_watermarked[11] , entry_valid_watermarked[12] , + entry_valid_watermarked[13] , entry_valid_watermarked[14] , + entry_valid_watermarked[15] , entry_match_q[0] , + entry_match_q[1] , entry_match_q[2] + }) === 20'b00111111111111111001); +assign lru_set_reset_vec_pt[25] = + (({ lru_update_event_q[5] , lru_update_event_q[6] , + lru_update_event_q[7] , entry_valid_watermarked[1] , + entry_valid_watermarked[2] , entry_valid_watermarked[3] , + entry_valid_watermarked[4] , entry_valid_watermarked[5] , + entry_valid_watermarked[6] , entry_valid_watermarked[7] , + entry_valid_watermarked[8] , entry_valid_watermarked[9] , + entry_valid_watermarked[10] , entry_valid_watermarked[11] , + entry_valid_watermarked[12] , entry_valid_watermarked[13] , + entry_valid_watermarked[14] , entry_valid_watermarked[15] , + entry_match_q[0] , entry_match_q[1] + }) === 20'b00111111111111111101); +assign lru_set_reset_vec_pt[26] = + (({ lru_update_event_q[5] , lru_update_event_q[6] , + lru_update_event_q[7] , entry_valid_watermarked[0] , + entry_valid_watermarked[1] , entry_valid_watermarked[2] , + entry_valid_watermarked[3] , entry_valid_watermarked[4] , + entry_valid_watermarked[5] , entry_valid_watermarked[6] , + entry_valid_watermarked[7] , entry_valid_watermarked[8] , + entry_valid_watermarked[9] , entry_valid_watermarked[10] , + entry_valid_watermarked[11] , entry_valid_watermarked[12] , + entry_valid_watermarked[13] , entry_valid_watermarked[14] , + entry_valid_watermarked[15] , entry_match_q[1] + }) === 20'b00111111111111111111); +assign lru_set_reset_vec_pt[27] = + (({ lru_update_event_q[5] , lru_update_event_q[6] , + lru_update_event_q[7] , entry_valid_watermarked[0] , + entry_valid_watermarked[1] , entry_valid_watermarked[2] , + entry_valid_watermarked[3] , entry_valid_watermarked[4] , + entry_valid_watermarked[5] , entry_valid_watermarked[6] , + entry_valid_watermarked[7] , entry_valid_watermarked[8] , + entry_valid_watermarked[9] , entry_valid_watermarked[10] , + entry_valid_watermarked[11] , entry_valid_watermarked[12] , + entry_valid_watermarked[13] , entry_valid_watermarked[14] , + entry_valid_watermarked[15] , entry_match_q[0] + }) === 20'b00111111111111111111); +assign lru_set_reset_vec_pt[28] = + (({ lru_update_event_q[5] , entry_valid_watermarked[0] , + entry_valid_watermarked[1] , entry_valid_watermarked[2] , + entry_valid_watermarked[3] , entry_valid_watermarked[4] , + entry_valid_watermarked[5] , entry_valid_watermarked[6] , + entry_valid_watermarked[7] , entry_valid_watermarked[8] , + entry_valid_watermarked[9] , entry_valid_watermarked[10] , + entry_valid_watermarked[11] , entry_valid_watermarked[12] , + entry_valid_watermarked[13] , entry_valid_watermarked[14] , + lru_q[1] , lru_q[3] , + lru_q[7] , lru_q[15] + }) === 20'b11111111111111111110); +assign lru_set_reset_vec_pt[29] = + (({ lru_update_event_q[5] , entry_valid_watermarked[0] , + entry_valid_watermarked[1] , entry_valid_watermarked[2] , + entry_valid_watermarked[3] , entry_valid_watermarked[4] , + entry_valid_watermarked[5] , entry_valid_watermarked[6] , + entry_valid_watermarked[7] , entry_valid_watermarked[8] , + entry_valid_watermarked[9] , entry_valid_watermarked[10] , + entry_valid_watermarked[11] , entry_valid_watermarked[12] , + entry_valid_watermarked[13] , entry_valid_watermarked[15] , + lru_q[1] , lru_q[3] , + lru_q[7] , lru_q[15] + }) === 20'b11111111111111111111); +assign lru_set_reset_vec_pt[30] = + (({ lru_update_event_q[5] , entry_valid_watermarked[0] , + entry_valid_watermarked[1] , entry_valid_watermarked[2] , + entry_valid_watermarked[3] , entry_valid_watermarked[4] , + entry_valid_watermarked[5] , entry_valid_watermarked[6] , + entry_valid_watermarked[7] , entry_valid_watermarked[8] , + entry_valid_watermarked[9] , entry_valid_watermarked[10] , + entry_valid_watermarked[11] , entry_valid_watermarked[12] , + entry_valid_watermarked[14] , entry_valid_watermarked[15] , + lru_q[1] , lru_q[3] , + lru_q[7] , lru_q[14] + }) === 20'b11111111111111111100); +assign lru_set_reset_vec_pt[31] = + (({ lru_update_event_q[5] , entry_valid_watermarked[0] , + entry_valid_watermarked[1] , entry_valid_watermarked[2] , + entry_valid_watermarked[3] , entry_valid_watermarked[4] , + entry_valid_watermarked[5] , entry_valid_watermarked[6] , + entry_valid_watermarked[7] , entry_valid_watermarked[8] , + entry_valid_watermarked[9] , entry_valid_watermarked[10] , + entry_valid_watermarked[11] , entry_valid_watermarked[13] , + entry_valid_watermarked[14] , entry_valid_watermarked[15] , + lru_q[1] , lru_q[3] , + lru_q[7] , lru_q[14] + }) === 20'b11111111111111111101); +assign lru_set_reset_vec_pt[32] = + (({ lru_update_event_q[5] , entry_valid_watermarked[0] , + entry_valid_watermarked[1] , entry_valid_watermarked[2] , + entry_valid_watermarked[3] , entry_valid_watermarked[4] , + entry_valid_watermarked[5] , entry_valid_watermarked[6] , + entry_valid_watermarked[7] , entry_valid_watermarked[8] , + entry_valid_watermarked[9] , entry_valid_watermarked[10] , + entry_valid_watermarked[12] , entry_valid_watermarked[13] , + entry_valid_watermarked[14] , entry_valid_watermarked[15] , + lru_q[1] , lru_q[3] , + lru_q[6] , lru_q[13] + }) === 20'b11111111111111111010); +assign lru_set_reset_vec_pt[33] = + (({ lru_update_event_q[5] , entry_valid_watermarked[0] , + entry_valid_watermarked[1] , entry_valid_watermarked[2] , + entry_valid_watermarked[3] , entry_valid_watermarked[4] , + entry_valid_watermarked[5] , entry_valid_watermarked[6] , + entry_valid_watermarked[7] , entry_valid_watermarked[8] , + entry_valid_watermarked[9] , entry_valid_watermarked[11] , + entry_valid_watermarked[12] , entry_valid_watermarked[13] , + entry_valid_watermarked[14] , entry_valid_watermarked[15] , + lru_q[1] , lru_q[3] , + lru_q[6] , lru_q[13] + }) === 20'b11111111111111111011); +assign lru_set_reset_vec_pt[34] = + (({ lru_update_event_q[5] , entry_valid_watermarked[0] , + entry_valid_watermarked[1] , entry_valid_watermarked[2] , + entry_valid_watermarked[3] , entry_valid_watermarked[4] , + entry_valid_watermarked[5] , entry_valid_watermarked[6] , + entry_valid_watermarked[7] , entry_valid_watermarked[8] , + entry_valid_watermarked[10] , entry_valid_watermarked[11] , + entry_valid_watermarked[12] , entry_valid_watermarked[13] , + entry_valid_watermarked[14] , entry_valid_watermarked[15] , + lru_q[1] , lru_q[3] , + lru_q[6] , lru_q[12] + }) === 20'b11111111111111111000); +assign lru_set_reset_vec_pt[35] = + (({ lru_update_event_q[5] , entry_valid_watermarked[0] , + entry_valid_watermarked[1] , entry_valid_watermarked[2] , + entry_valid_watermarked[3] , entry_valid_watermarked[4] , + entry_valid_watermarked[5] , entry_valid_watermarked[6] , + entry_valid_watermarked[7] , entry_valid_watermarked[9] , + entry_valid_watermarked[10] , entry_valid_watermarked[11] , + entry_valid_watermarked[12] , entry_valid_watermarked[13] , + entry_valid_watermarked[14] , entry_valid_watermarked[15] , + lru_q[1] , lru_q[3] , + lru_q[6] , lru_q[12] + }) === 20'b11111111111111111001); +assign lru_set_reset_vec_pt[36] = + (({ lru_update_event_q[5] , entry_valid_watermarked[0] , + entry_valid_watermarked[1] , entry_valid_watermarked[2] , + entry_valid_watermarked[3] , entry_valid_watermarked[4] , + entry_valid_watermarked[5] , entry_valid_watermarked[6] , + entry_valid_watermarked[8] , entry_valid_watermarked[9] , + entry_valid_watermarked[10] , entry_valid_watermarked[11] , + entry_valid_watermarked[12] , entry_valid_watermarked[13] , + entry_valid_watermarked[14] , entry_valid_watermarked[15] , + lru_q[1] , lru_q[2] , + lru_q[5] , lru_q[11] + }) === 20'b11111111111111110110); +assign lru_set_reset_vec_pt[37] = + (({ lru_update_event_q[5] , entry_valid_watermarked[0] , + entry_valid_watermarked[1] , entry_valid_watermarked[2] , + entry_valid_watermarked[3] , entry_valid_watermarked[4] , + entry_valid_watermarked[5] , entry_valid_watermarked[7] , + entry_valid_watermarked[8] , entry_valid_watermarked[9] , + entry_valid_watermarked[10] , entry_valid_watermarked[11] , + entry_valid_watermarked[12] , entry_valid_watermarked[13] , + entry_valid_watermarked[14] , entry_valid_watermarked[15] , + lru_q[1] , lru_q[2] , + lru_q[5] , lru_q[11] + }) === 20'b11111111111111110111); +assign lru_set_reset_vec_pt[38] = + (({ lru_update_event_q[5] , entry_valid_watermarked[0] , + entry_valid_watermarked[1] , entry_valid_watermarked[2] , + entry_valid_watermarked[3] , entry_valid_watermarked[4] , + entry_valid_watermarked[6] , entry_valid_watermarked[7] , + entry_valid_watermarked[8] , entry_valid_watermarked[9] , + entry_valid_watermarked[10] , entry_valid_watermarked[11] , + entry_valid_watermarked[12] , entry_valid_watermarked[13] , + entry_valid_watermarked[14] , entry_valid_watermarked[15] , + lru_q[1] , lru_q[2] , + lru_q[5] , lru_q[10] + }) === 20'b11111111111111110100); +assign lru_set_reset_vec_pt[39] = + (({ lru_update_event_q[5] , entry_valid_watermarked[0] , + entry_valid_watermarked[1] , entry_valid_watermarked[2] , + entry_valid_watermarked[3] , entry_valid_watermarked[5] , + entry_valid_watermarked[6] , entry_valid_watermarked[7] , + entry_valid_watermarked[8] , entry_valid_watermarked[9] , + entry_valid_watermarked[10] , entry_valid_watermarked[11] , + entry_valid_watermarked[12] , entry_valid_watermarked[13] , + entry_valid_watermarked[14] , entry_valid_watermarked[15] , + lru_q[1] , lru_q[2] , + lru_q[5] , lru_q[10] + }) === 20'b11111111111111110101); +assign lru_set_reset_vec_pt[40] = + (({ lru_update_event_q[5] , entry_valid_watermarked[0] , + entry_valid_watermarked[1] , entry_valid_watermarked[2] , + entry_valid_watermarked[4] , entry_valid_watermarked[5] , + entry_valid_watermarked[6] , entry_valid_watermarked[7] , + entry_valid_watermarked[8] , entry_valid_watermarked[9] , + entry_valid_watermarked[10] , entry_valid_watermarked[11] , + entry_valid_watermarked[12] , entry_valid_watermarked[13] , + entry_valid_watermarked[14] , entry_valid_watermarked[15] , + lru_q[1] , lru_q[2] , + lru_q[4] , lru_q[9] + }) === 20'b11111111111111110010); +assign lru_set_reset_vec_pt[41] = + (({ lru_update_event_q[5] , entry_valid_watermarked[0] , + entry_valid_watermarked[1] , entry_valid_watermarked[3] , + entry_valid_watermarked[4] , entry_valid_watermarked[5] , + entry_valid_watermarked[6] , entry_valid_watermarked[7] , + entry_valid_watermarked[8] , entry_valid_watermarked[9] , + entry_valid_watermarked[10] , entry_valid_watermarked[11] , + entry_valid_watermarked[12] , entry_valid_watermarked[13] , + entry_valid_watermarked[14] , entry_valid_watermarked[15] , + lru_q[1] , lru_q[2] , + lru_q[4] , lru_q[9] + }) === 20'b11111111111111110011); +assign lru_set_reset_vec_pt[42] = + (({ lru_update_event_q[5] , entry_valid_watermarked[0] , + entry_valid_watermarked[2] , entry_valid_watermarked[3] , + entry_valid_watermarked[4] , entry_valid_watermarked[5] , + entry_valid_watermarked[6] , entry_valid_watermarked[7] , + entry_valid_watermarked[8] , entry_valid_watermarked[9] , + entry_valid_watermarked[10] , entry_valid_watermarked[11] , + entry_valid_watermarked[12] , entry_valid_watermarked[13] , + entry_valid_watermarked[14] , entry_valid_watermarked[15] , + lru_q[1] , lru_q[2] , + lru_q[4] , lru_q[8] + }) === 20'b11111111111111110000); +assign lru_set_reset_vec_pt[43] = + (({ lru_update_event_q[5] , entry_valid_watermarked[1] , + entry_valid_watermarked[2] , entry_valid_watermarked[3] , + entry_valid_watermarked[4] , entry_valid_watermarked[5] , + entry_valid_watermarked[6] , entry_valid_watermarked[7] , + entry_valid_watermarked[8] , entry_valid_watermarked[9] , + entry_valid_watermarked[10] , entry_valid_watermarked[11] , + entry_valid_watermarked[12] , entry_valid_watermarked[13] , + entry_valid_watermarked[14] , entry_valid_watermarked[15] , + lru_q[1] , lru_q[2] , + lru_q[4] , lru_q[8] + }) === 20'b11111111111111110001); +assign lru_set_reset_vec_pt[44] = + (({ lru_update_event_q[5] , entry_valid_watermarked[0] , + entry_valid_watermarked[1] , entry_valid_watermarked[2] , + entry_valid_watermarked[3] , entry_valid_watermarked[4] , + entry_valid_watermarked[5] , entry_valid_watermarked[6] , + entry_valid_watermarked[7] , entry_valid_watermarked[8] , + entry_valid_watermarked[9] , entry_valid_watermarked[10] , + entry_valid_watermarked[11] , entry_valid_watermarked[12] , + entry_valid_watermarked[13] , lru_q[1] , + lru_q[3] , lru_q[7] + }) === 18'b111111111111111110); +assign lru_set_reset_vec_pt[45] = + (({ lru_update_event_q[5] , entry_valid_watermarked[0] , + entry_valid_watermarked[1] , entry_valid_watermarked[2] , + entry_valid_watermarked[3] , entry_valid_watermarked[4] , + entry_valid_watermarked[5] , entry_valid_watermarked[6] , + entry_valid_watermarked[7] , entry_valid_watermarked[8] , + entry_valid_watermarked[9] , entry_valid_watermarked[10] , + entry_valid_watermarked[11] , entry_valid_watermarked[14] , + entry_valid_watermarked[15] , lru_q[1] , + lru_q[3] , lru_q[7] + }) === 18'b111111111111111111); +assign lru_set_reset_vec_pt[46] = + (({ lru_update_event_q[5] , entry_valid_watermarked[0] , + entry_valid_watermarked[1] , entry_valid_watermarked[2] , + entry_valid_watermarked[3] , entry_valid_watermarked[4] , + entry_valid_watermarked[5] , entry_valid_watermarked[6] , + entry_valid_watermarked[7] , entry_valid_watermarked[8] , + entry_valid_watermarked[9] , entry_valid_watermarked[12] , + entry_valid_watermarked[13] , entry_valid_watermarked[14] , + entry_valid_watermarked[15] , lru_q[1] , + lru_q[3] , lru_q[6] + }) === 18'b111111111111111100); +assign lru_set_reset_vec_pt[47] = + (({ lru_update_event_q[5] , entry_valid_watermarked[0] , + entry_valid_watermarked[1] , entry_valid_watermarked[2] , + entry_valid_watermarked[3] , entry_valid_watermarked[4] , + entry_valid_watermarked[5] , entry_valid_watermarked[6] , + entry_valid_watermarked[7] , entry_valid_watermarked[10] , + entry_valid_watermarked[11] , entry_valid_watermarked[12] , + entry_valid_watermarked[13] , entry_valid_watermarked[14] , + entry_valid_watermarked[15] , lru_q[1] , + lru_q[3] , lru_q[6] + }) === 18'b111111111111111101); +assign lru_set_reset_vec_pt[48] = + (({ lru_update_event_q[5] , entry_valid_watermarked[0] , + entry_valid_watermarked[1] , entry_valid_watermarked[2] , + entry_valid_watermarked[3] , entry_valid_watermarked[4] , + entry_valid_watermarked[5] , entry_valid_watermarked[8] , + entry_valid_watermarked[9] , entry_valid_watermarked[10] , + entry_valid_watermarked[11] , entry_valid_watermarked[12] , + entry_valid_watermarked[13] , entry_valid_watermarked[14] , + entry_valid_watermarked[15] , lru_q[1] , + lru_q[2] , lru_q[5] + }) === 18'b111111111111111010); +assign lru_set_reset_vec_pt[49] = + (({ lru_update_event_q[5] , entry_valid_watermarked[0] , + entry_valid_watermarked[1] , entry_valid_watermarked[2] , + entry_valid_watermarked[3] , entry_valid_watermarked[6] , + entry_valid_watermarked[7] , entry_valid_watermarked[8] , + entry_valid_watermarked[9] , entry_valid_watermarked[10] , + entry_valid_watermarked[11] , entry_valid_watermarked[12] , + entry_valid_watermarked[13] , entry_valid_watermarked[14] , + entry_valid_watermarked[15] , lru_q[1] , + lru_q[2] , lru_q[5] + }) === 18'b111111111111111011); +assign lru_set_reset_vec_pt[50] = + (({ lru_update_event_q[5] , entry_valid_watermarked[0] , + entry_valid_watermarked[1] , entry_valid_watermarked[4] , + entry_valid_watermarked[5] , entry_valid_watermarked[6] , + entry_valid_watermarked[7] , entry_valid_watermarked[8] , + entry_valid_watermarked[9] , entry_valid_watermarked[10] , + entry_valid_watermarked[11] , entry_valid_watermarked[12] , + entry_valid_watermarked[13] , entry_valid_watermarked[14] , + entry_valid_watermarked[15] , lru_q[1] , + lru_q[2] , lru_q[4] + }) === 18'b111111111111111000); +assign lru_set_reset_vec_pt[51] = + (({ lru_update_event_q[5] , entry_valid_watermarked[2] , + entry_valid_watermarked[3] , entry_valid_watermarked[4] , + entry_valid_watermarked[5] , entry_valid_watermarked[6] , + entry_valid_watermarked[7] , entry_valid_watermarked[8] , + entry_valid_watermarked[9] , entry_valid_watermarked[10] , + entry_valid_watermarked[11] , entry_valid_watermarked[12] , + entry_valid_watermarked[13] , entry_valid_watermarked[14] , + entry_valid_watermarked[15] , lru_q[1] , + lru_q[2] , lru_q[4] + }) === 18'b111111111111111001); +assign lru_set_reset_vec_pt[52] = + (({ lru_update_event_q[5] , entry_valid_watermarked[0] , + entry_valid_watermarked[1] , entry_valid_watermarked[2] , + entry_valid_watermarked[3] , entry_valid_watermarked[4] , + entry_valid_watermarked[5] , entry_valid_watermarked[6] , + entry_valid_watermarked[7] , entry_valid_watermarked[8] , + entry_valid_watermarked[9] , entry_valid_watermarked[10] , + entry_valid_watermarked[11] , lru_q[1] , + lru_q[3] }) === 15'b111111111111110); +assign lru_set_reset_vec_pt[53] = + (({ lru_update_event_q[5] , entry_valid_watermarked[0] , + entry_valid_watermarked[1] , entry_valid_watermarked[2] , + entry_valid_watermarked[3] , entry_valid_watermarked[4] , + entry_valid_watermarked[5] , entry_valid_watermarked[6] , + entry_valid_watermarked[7] , entry_valid_watermarked[12] , + entry_valid_watermarked[13] , entry_valid_watermarked[14] , + entry_valid_watermarked[15] , lru_q[1] , + lru_q[3] }) === 15'b111111111111111); +assign lru_set_reset_vec_pt[54] = + (({ lru_update_event_q[5] , entry_valid_watermarked[0] , + entry_valid_watermarked[1] , entry_valid_watermarked[2] , + entry_valid_watermarked[3] , entry_valid_watermarked[8] , + entry_valid_watermarked[9] , entry_valid_watermarked[10] , + entry_valid_watermarked[11] , entry_valid_watermarked[12] , + entry_valid_watermarked[13] , entry_valid_watermarked[14] , + entry_valid_watermarked[15] , lru_q[1] , + lru_q[2] }) === 15'b111111111111100); +assign lru_set_reset_vec_pt[55] = + (({ lru_update_event_q[5] , entry_valid_watermarked[4] , + entry_valid_watermarked[5] , entry_valid_watermarked[6] , + entry_valid_watermarked[7] , entry_valid_watermarked[8] , + entry_valid_watermarked[9] , entry_valid_watermarked[10] , + entry_valid_watermarked[11] , entry_valid_watermarked[12] , + entry_valid_watermarked[13] , entry_valid_watermarked[14] , + entry_valid_watermarked[15] , lru_q[1] , + lru_q[2] }) === 15'b111111111111101); +assign lru_set_reset_vec_pt[56] = + (({ lru_update_event_q[5] , entry_valid_watermarked[0] , + entry_valid_watermarked[1] , entry_valid_watermarked[2] , + entry_valid_watermarked[3] , entry_valid_watermarked[4] , + entry_valid_watermarked[5] , entry_valid_watermarked[6] , + entry_valid_watermarked[7] , lru_q[1] + }) === 10'b1111111110); +assign lru_set_reset_vec_pt[57] = + (({ lru_update_event_q[5] , entry_valid_watermarked[8] , + entry_valid_watermarked[9] , entry_valid_watermarked[10] , + entry_valid_watermarked[11] , entry_valid_watermarked[12] , + entry_valid_watermarked[13] , entry_valid_watermarked[14] , + entry_valid_watermarked[15] , lru_q[1] + }) === 10'b1111111111); +assign lru_set_reset_vec_pt[58] = + (({ entry_valid_watermarked[0] , entry_valid_watermarked[1] , + entry_valid_watermarked[2] , entry_valid_watermarked[3] , + entry_valid_watermarked[4] , entry_valid_watermarked[5] , + entry_valid_watermarked[6] , entry_valid_watermarked[7] , + entry_valid_watermarked[8] , entry_valid_watermarked[9] , + entry_valid_watermarked[10] , entry_valid_watermarked[11] , + entry_valid_watermarked[12] , entry_valid_watermarked[13] , + entry_valid_watermarked[14] , entry_valid_watermarked[15] + }) === 16'b1111111111111110); +assign lru_set_reset_vec_pt[59] = + (({ entry_valid_watermarked[0] , entry_valid_watermarked[1] , + entry_valid_watermarked[2] , entry_valid_watermarked[3] , + entry_valid_watermarked[4] , entry_valid_watermarked[5] , + entry_valid_watermarked[6] , entry_valid_watermarked[7] , + entry_valid_watermarked[8] , entry_valid_watermarked[9] , + entry_valid_watermarked[10] , entry_valid_watermarked[11] , + entry_valid_watermarked[12] , entry_valid_watermarked[13] , + entry_valid_watermarked[14] }) === 15'b111111111111110); +assign lru_set_reset_vec_pt[60] = + (({ entry_valid_watermarked[0] , entry_valid_watermarked[1] , + entry_valid_watermarked[2] , entry_valid_watermarked[3] , + entry_valid_watermarked[4] , entry_valid_watermarked[5] , + entry_valid_watermarked[6] , entry_valid_watermarked[7] , + entry_valid_watermarked[8] , entry_valid_watermarked[9] , + entry_valid_watermarked[10] , entry_valid_watermarked[11] , + entry_valid_watermarked[12] , entry_valid_watermarked[13] + }) === 14'b11111111111110); +assign lru_set_reset_vec_pt[61] = + (({ entry_valid_watermarked[0] , entry_valid_watermarked[1] , + entry_valid_watermarked[2] , entry_valid_watermarked[3] , + entry_valid_watermarked[4] , entry_valid_watermarked[5] , + entry_valid_watermarked[6] , entry_valid_watermarked[7] , + entry_valid_watermarked[8] , entry_valid_watermarked[9] , + entry_valid_watermarked[10] , entry_valid_watermarked[11] , + entry_valid_watermarked[13] }) === 13'b1111111111110); +assign lru_set_reset_vec_pt[62] = + (({ entry_valid_watermarked[0] , entry_valid_watermarked[1] , + entry_valid_watermarked[2] , entry_valid_watermarked[3] , + entry_valid_watermarked[4] , entry_valid_watermarked[5] , + entry_valid_watermarked[6] , entry_valid_watermarked[7] , + entry_valid_watermarked[8] , entry_valid_watermarked[9] , + entry_valid_watermarked[10] , entry_valid_watermarked[11] , + entry_valid_watermarked[12] }) === 13'b1111111111110); +assign lru_set_reset_vec_pt[63] = + (({ entry_valid_watermarked[0] , entry_valid_watermarked[1] , + entry_valid_watermarked[2] , entry_valid_watermarked[3] , + entry_valid_watermarked[4] , entry_valid_watermarked[5] , + entry_valid_watermarked[6] , entry_valid_watermarked[7] , + entry_valid_watermarked[8] , entry_valid_watermarked[9] , + entry_valid_watermarked[10] , entry_valid_watermarked[11] + }) === 12'b111111111110); +assign lru_set_reset_vec_pt[64] = + (({ entry_valid_watermarked[0] , entry_valid_watermarked[1] , + entry_valid_watermarked[2] , entry_valid_watermarked[3] , + entry_valid_watermarked[4] , entry_valid_watermarked[5] , + entry_valid_watermarked[6] , entry_valid_watermarked[7] , + entry_valid_watermarked[11] }) === 9'b111111110); +assign lru_set_reset_vec_pt[65] = + (({ entry_valid_watermarked[0] , entry_valid_watermarked[1] , + entry_valid_watermarked[2] , entry_valid_watermarked[3] , + entry_valid_watermarked[4] , entry_valid_watermarked[5] , + entry_valid_watermarked[6] , entry_valid_watermarked[7] , + entry_valid_watermarked[8] , entry_valid_watermarked[9] , + entry_valid_watermarked[10] }) === 11'b11111111110); +assign lru_set_reset_vec_pt[66] = + (({ entry_valid_watermarked[0] , entry_valid_watermarked[1] , + entry_valid_watermarked[2] , entry_valid_watermarked[3] , + entry_valid_watermarked[4] , entry_valid_watermarked[5] , + entry_valid_watermarked[6] , entry_valid_watermarked[7] , + entry_valid_watermarked[8] , entry_valid_watermarked[9] + }) === 10'b1111111110); +assign lru_set_reset_vec_pt[67] = + (({ entry_valid_watermarked[0] , entry_valid_watermarked[1] , + entry_valid_watermarked[2] , entry_valid_watermarked[3] , + entry_valid_watermarked[4] , entry_valid_watermarked[5] , + entry_valid_watermarked[6] , entry_valid_watermarked[7] , + entry_valid_watermarked[9] }) === 9'b111111110); +assign lru_set_reset_vec_pt[68] = + (({ entry_valid_watermarked[0] , entry_valid_watermarked[1] , + entry_valid_watermarked[2] , entry_valid_watermarked[3] , + entry_valid_watermarked[4] , entry_valid_watermarked[5] , + entry_valid_watermarked[6] , entry_valid_watermarked[7] , + entry_valid_watermarked[8] }) === 9'b111111110); +assign lru_set_reset_vec_pt[69] = + (({ entry_valid_watermarked[0] , entry_valid_watermarked[1] , + entry_valid_watermarked[2] , entry_valid_watermarked[3] , + entry_valid_watermarked[4] , entry_valid_watermarked[5] , + entry_valid_watermarked[6] , entry_valid_watermarked[7] + }) === 8'b11111110); +assign lru_set_reset_vec_pt[70] = + (({ entry_valid_watermarked[7] }) === 1'b0); +assign lru_set_reset_vec_pt[71] = + (({ entry_valid_watermarked[0] , entry_valid_watermarked[1] , + entry_valid_watermarked[2] , entry_valid_watermarked[3] , + entry_valid_watermarked[4] , entry_valid_watermarked[5] , + entry_valid_watermarked[6] }) === 7'b1111110); +assign lru_set_reset_vec_pt[72] = + (({ entry_valid_watermarked[0] , entry_valid_watermarked[1] , + entry_valid_watermarked[2] , entry_valid_watermarked[3] , + entry_valid_watermarked[4] , entry_valid_watermarked[5] + }) === 6'b111110); +assign lru_set_reset_vec_pt[73] = + (({ entry_valid_watermarked[0] , entry_valid_watermarked[1] , + entry_valid_watermarked[2] , entry_valid_watermarked[3] , + entry_valid_watermarked[5] }) === 5'b11110); +assign lru_set_reset_vec_pt[74] = + (({ entry_valid_watermarked[0] , entry_valid_watermarked[1] , + entry_valid_watermarked[2] , entry_valid_watermarked[3] , + entry_valid_watermarked[4] }) === 5'b11110); +assign lru_set_reset_vec_pt[75] = + (({ entry_valid_watermarked[0] , entry_valid_watermarked[1] , + entry_valid_watermarked[2] , entry_valid_watermarked[3] + }) === 4'b1110); +assign lru_set_reset_vec_pt[76] = + (({ entry_valid_watermarked[3] }) === 1'b0); +assign lru_set_reset_vec_pt[77] = + (({ entry_valid_watermarked[0] , entry_valid_watermarked[1] , + entry_valid_watermarked[2] }) === 3'b110); +assign lru_set_reset_vec_pt[78] = + (({ entry_valid_watermarked[0] , entry_valid_watermarked[1] + }) === 2'b10); +assign lru_set_reset_vec_pt[79] = + (({ entry_valid_watermarked[1] }) === 1'b0); +assign lru_set_reset_vec_pt[80] = + (({ entry_valid_watermarked[0] }) === 1'b0); +assign lru_reset_vec[1] = + (lru_set_reset_vec_pt[1] | lru_set_reset_vec_pt[2] + | lru_set_reset_vec_pt[4] | lru_set_reset_vec_pt[6] + | lru_set_reset_vec_pt[7] | lru_set_reset_vec_pt[9] + | lru_set_reset_vec_pt[10] | lru_set_reset_vec_pt[13] + | lru_set_reset_vec_pt[57] | lru_set_reset_vec_pt[70] + | lru_set_reset_vec_pt[71] | lru_set_reset_vec_pt[73] + | lru_set_reset_vec_pt[74] | lru_set_reset_vec_pt[76] + | lru_set_reset_vec_pt[77] | lru_set_reset_vec_pt[79] + | lru_set_reset_vec_pt[80]); +assign lru_reset_vec[2] = + (lru_set_reset_vec_pt[14] | lru_set_reset_vec_pt[16] + | lru_set_reset_vec_pt[17] | lru_set_reset_vec_pt[20] + | lru_set_reset_vec_pt[55] | lru_set_reset_vec_pt[76] + | lru_set_reset_vec_pt[77] | lru_set_reset_vec_pt[79] + | lru_set_reset_vec_pt[80]); +assign lru_reset_vec[3] = + (lru_set_reset_vec_pt[1] | lru_set_reset_vec_pt[2] + | lru_set_reset_vec_pt[4] | lru_set_reset_vec_pt[6] + | lru_set_reset_vec_pt[53] | lru_set_reset_vec_pt[64] + | lru_set_reset_vec_pt[65] | lru_set_reset_vec_pt[67] + | lru_set_reset_vec_pt[68]); +assign lru_reset_vec[4] = + (lru_set_reset_vec_pt[21] | lru_set_reset_vec_pt[24] + | lru_set_reset_vec_pt[51] | lru_set_reset_vec_pt[79] + | lru_set_reset_vec_pt[80]); +assign lru_reset_vec[5] = + (lru_set_reset_vec_pt[14] | lru_set_reset_vec_pt[16] + | lru_set_reset_vec_pt[49] | lru_set_reset_vec_pt[73] + | lru_set_reset_vec_pt[74]); +assign lru_reset_vec[6] = + (lru_set_reset_vec_pt[7] | lru_set_reset_vec_pt[9] + | lru_set_reset_vec_pt[47] | lru_set_reset_vec_pt[67] + | lru_set_reset_vec_pt[68]); +assign lru_reset_vec[7] = + (lru_set_reset_vec_pt[1] | lru_set_reset_vec_pt[2] + | lru_set_reset_vec_pt[45] | lru_set_reset_vec_pt[61] + | lru_set_reset_vec_pt[62]); +assign lru_reset_vec[8] = + (lru_set_reset_vec_pt[25] | lru_set_reset_vec_pt[43] + | lru_set_reset_vec_pt[80]); +assign lru_reset_vec[9] = + (lru_set_reset_vec_pt[21] | lru_set_reset_vec_pt[41] + | lru_set_reset_vec_pt[77]); +assign lru_reset_vec[10] = + (lru_set_reset_vec_pt[17] | lru_set_reset_vec_pt[39] + | lru_set_reset_vec_pt[74]); +assign lru_reset_vec[11] = + (lru_set_reset_vec_pt[14] | lru_set_reset_vec_pt[37] + | lru_set_reset_vec_pt[71]); +assign lru_reset_vec[12] = + (lru_set_reset_vec_pt[10] | lru_set_reset_vec_pt[35] + | lru_set_reset_vec_pt[68]); +assign lru_reset_vec[13] = + (lru_set_reset_vec_pt[7] | lru_set_reset_vec_pt[33] + | lru_set_reset_vec_pt[65]); +assign lru_reset_vec[14] = + (lru_set_reset_vec_pt[4] | lru_set_reset_vec_pt[31] + | lru_set_reset_vec_pt[62]); +assign lru_reset_vec[15] = + (lru_set_reset_vec_pt[1] | lru_set_reset_vec_pt[29] + | lru_set_reset_vec_pt[59]); +assign lru_set_vec[1] = + (lru_set_reset_vec_pt[15] | lru_set_reset_vec_pt[16] + | lru_set_reset_vec_pt[18] | lru_set_reset_vec_pt[19] + | lru_set_reset_vec_pt[22] | lru_set_reset_vec_pt[23] + | lru_set_reset_vec_pt[26] | lru_set_reset_vec_pt[27] + | lru_set_reset_vec_pt[56] | lru_set_reset_vec_pt[58] + | lru_set_reset_vec_pt[59] | lru_set_reset_vec_pt[60] + | lru_set_reset_vec_pt[62] | lru_set_reset_vec_pt[63] + | lru_set_reset_vec_pt[65] | lru_set_reset_vec_pt[66] + | lru_set_reset_vec_pt[68]); +assign lru_set_vec[2] = + (lru_set_reset_vec_pt[22] | lru_set_reset_vec_pt[23] + | lru_set_reset_vec_pt[26] | lru_set_reset_vec_pt[27] + | lru_set_reset_vec_pt[54] | lru_set_reset_vec_pt[69] + | lru_set_reset_vec_pt[71] | lru_set_reset_vec_pt[72] + | lru_set_reset_vec_pt[74]); +assign lru_set_vec[3] = + (lru_set_reset_vec_pt[8] | lru_set_reset_vec_pt[9] + | lru_set_reset_vec_pt[11] | lru_set_reset_vec_pt[12] + | lru_set_reset_vec_pt[52] | lru_set_reset_vec_pt[58] + | lru_set_reset_vec_pt[59] | lru_set_reset_vec_pt[60] + | lru_set_reset_vec_pt[62]); +assign lru_set_vec[4] = + (lru_set_reset_vec_pt[26] | lru_set_reset_vec_pt[27] + | lru_set_reset_vec_pt[50] | lru_set_reset_vec_pt[75] + | lru_set_reset_vec_pt[77]); +assign lru_set_vec[5] = + (lru_set_reset_vec_pt[18] | lru_set_reset_vec_pt[19] + | lru_set_reset_vec_pt[48] | lru_set_reset_vec_pt[69] + | lru_set_reset_vec_pt[71]); +assign lru_set_vec[6] = + (lru_set_reset_vec_pt[11] | lru_set_reset_vec_pt[12] + | lru_set_reset_vec_pt[46] | lru_set_reset_vec_pt[63] + | lru_set_reset_vec_pt[65]); +assign lru_set_vec[7] = + (lru_set_reset_vec_pt[5] | lru_set_reset_vec_pt[6] + | lru_set_reset_vec_pt[44] | lru_set_reset_vec_pt[58] + | lru_set_reset_vec_pt[59]); +assign lru_set_vec[8] = + (lru_set_reset_vec_pt[27] | lru_set_reset_vec_pt[42] + | lru_set_reset_vec_pt[78]); +assign lru_set_vec[9] = + (lru_set_reset_vec_pt[23] | lru_set_reset_vec_pt[40] + | lru_set_reset_vec_pt[75]); +assign lru_set_vec[10] = + (lru_set_reset_vec_pt[19] | lru_set_reset_vec_pt[38] + | lru_set_reset_vec_pt[72]); +assign lru_set_vec[11] = + (lru_set_reset_vec_pt[16] | lru_set_reset_vec_pt[36] + | lru_set_reset_vec_pt[69]); +assign lru_set_vec[12] = + (lru_set_reset_vec_pt[12] | lru_set_reset_vec_pt[34] + | lru_set_reset_vec_pt[66]); +assign lru_set_vec[13] = + (lru_set_reset_vec_pt[9] | lru_set_reset_vec_pt[32] + | lru_set_reset_vec_pt[63]); +assign lru_set_vec[14] = + (lru_set_reset_vec_pt[6] | lru_set_reset_vec_pt[30] + | lru_set_reset_vec_pt[60]); +assign lru_set_vec[15] = + (lru_set_reset_vec_pt[3] | lru_set_reset_vec_pt[28] + | lru_set_reset_vec_pt[58]); + +//assign_end +//assign_start + +assign lru_way_encode_pt[1] = + (({ lru_eff[1] , lru_eff[3] , + lru_eff[7] , lru_eff[15] + }) === 4'b1111); +assign lru_way_encode_pt[2] = + (({ lru_eff[1] , lru_eff[3] , + lru_eff[7] , lru_eff[14] + }) === 4'b1101); +assign lru_way_encode_pt[3] = + (({ lru_eff[1] , lru_eff[3] , + lru_eff[6] , lru_eff[13] + }) === 4'b1011); +assign lru_way_encode_pt[4] = + (({ lru_eff[1] , lru_eff[3] , + lru_eff[6] , lru_eff[12] + }) === 4'b1001); +assign lru_way_encode_pt[5] = + (({ lru_eff[1] , lru_eff[2] , + lru_eff[5] , lru_eff[11] + }) === 4'b0111); +assign lru_way_encode_pt[6] = + (({ lru_eff[1] , lru_eff[2] , + lru_eff[5] , lru_eff[10] + }) === 4'b0101); +assign lru_way_encode_pt[7] = + (({ lru_eff[1] , lru_eff[2] , + lru_eff[4] , lru_eff[9] + }) === 4'b0011); +assign lru_way_encode_pt[8] = + (({ lru_eff[1] , lru_eff[2] , + lru_eff[4] , lru_eff[8] + }) === 4'b0001); +assign lru_way_encode_pt[9] = + (({ lru_eff[1] , lru_eff[3] , + lru_eff[7] }) === 3'b111); +assign lru_way_encode_pt[10] = + (({ lru_eff[1] , lru_eff[3] , + lru_eff[6] }) === 3'b101); +assign lru_way_encode_pt[11] = + (({ lru_eff[1] , lru_eff[2] , + lru_eff[5] }) === 3'b011); +assign lru_way_encode_pt[12] = + (({ lru_eff[1] , lru_eff[2] , + lru_eff[4] }) === 3'b001); +assign lru_way_encode_pt[13] = + (({ lru_eff[1] , lru_eff[3] + }) === 2'b11); +assign lru_way_encode_pt[14] = + (({ lru_eff[1] , lru_eff[2] + }) === 2'b01); +assign lru_way_encode_pt[15] = + (({ lru_eff[1] }) === 1'b1); +assign lru_way_encode[0] = + (lru_way_encode_pt[15]); +assign lru_way_encode[1] = + (lru_way_encode_pt[13] | lru_way_encode_pt[14] + ); +assign lru_way_encode[2] = + (lru_way_encode_pt[9] | lru_way_encode_pt[10] + | lru_way_encode_pt[11] | lru_way_encode_pt[12] + ); +assign lru_way_encode[3] = + (lru_way_encode_pt[1] | lru_way_encode_pt[2] + | lru_way_encode_pt[3] | lru_way_encode_pt[4] + | lru_way_encode_pt[5] | lru_way_encode_pt[6] + | lru_way_encode_pt[7] | lru_way_encode_pt[8] + ); + +//assign_end +//assign_start + +assign cam_mask_bits_pt[1] = + (({ ex6_data_in_q[55] , ex6_data_in_q[56] , + ex6_data_in_q[57] , ex6_data_in_q[58] , + ex6_data_in_q[59] }) === 5'b11010); +assign cam_mask_bits_pt[2] = + (({ ex6_data_in_q[56] , ex6_data_in_q[59] + }) === 2'b00); +assign cam_mask_bits_pt[3] = + (({ ex6_data_in_q[55] , ex6_data_in_q[56] , + ex6_data_in_q[57] , ex6_data_in_q[58] , + ex6_data_in_q[59] }) === 5'b10101); +assign cam_mask_bits_pt[4] = + (({ ex6_data_in_q[55] , ex6_data_in_q[56] , + ex6_data_in_q[57] , ex6_data_in_q[58] , + ex6_data_in_q[59] }) === 5'b10011); +assign cam_mask_bits_pt[5] = + (({ ex6_data_in_q[55] , ex6_data_in_q[56] , + ex6_data_in_q[57] , ex6_data_in_q[58] , + ex6_data_in_q[59] }) === 5'b10111); +assign cam_mask_bits_pt[6] = + (({ ex6_data_in_q[55] , ex6_data_in_q[56] , + ex6_data_in_q[58] , ex6_data_in_q[59] + }) === 4'b0011); +assign cam_mask_bits_pt[7] = + (({ ex6_data_in_q[56] , ex6_data_in_q[59] + }) === 2'b11); +assign cam_mask_bits_pt[8] = + (({ ex6_data_in_q[57] , ex6_data_in_q[58] + }) === 2'b00); +assign cam_mask_bits_pt[9] = + (({ ex6_data_in_q[58] }) === 1'b0); +assign cam_mask_bits_pt[10] = + (({ ex6_data_in_q[56] , ex6_data_in_q[57] + }) === 2'b00); +assign cam_mask_bits_pt[11] = + (({ ex6_data_in_q[56] , ex6_data_in_q[57] + }) === 2'b11); +assign cam_mask_bits_pt[12] = + (({ tlb_rel_data_q[52] , tlb_rel_data_q[55] + }) === 2'b10); +assign cam_mask_bits_pt[13] = + (({ tlb_rel_data_q[52] , tlb_rel_data_q[53] , + tlb_rel_data_q[54] , tlb_rel_data_q[55] + }) === 4'b1111); +assign cam_mask_bits_pt[14] = + (({ tlb_rel_data_q[52] , tlb_rel_data_q[54] , + tlb_rel_data_q[55] }) === 3'b011); +assign cam_mask_bits_pt[15] = + (({ tlb_rel_data_q[53] , tlb_rel_data_q[54] + }) === 2'b00); +assign cam_mask_bits_pt[16] = + (({ tlb_rel_data_q[52] , tlb_rel_data_q[53] , + tlb_rel_data_q[54] }) === 3'b110); +assign cam_mask_bits_pt[17] = + (({ tlb_rel_data_q[54] }) === 1'b0); +assign cam_mask_bits_pt[18] = + (({ tlb_rel_data_q[52] , tlb_rel_data_q[53] , + tlb_rel_data_q[54] }) === 3'b101); +assign cam_mask_bits_pt[19] = + (({ tlb_rel_data_q[53] }) === 1'b0); +assign tlb_rel_cmpmask[0] = + (cam_mask_bits_pt[13] | cam_mask_bits_pt[14] + | cam_mask_bits_pt[17] | cam_mask_bits_pt[18] + ); +assign tlb_rel_cmpmask[1] = + (cam_mask_bits_pt[17] | cam_mask_bits_pt[19] + ); +assign tlb_rel_cmpmask[2] = + (cam_mask_bits_pt[19]); +assign tlb_rel_cmpmask[3] = + (cam_mask_bits_pt[15]); +assign tlb_rel_xbitmask[0] = + (cam_mask_bits_pt[12]); +assign tlb_rel_xbitmask[1] = + (cam_mask_bits_pt[13]); +assign tlb_rel_xbitmask[2] = + (cam_mask_bits_pt[16]); +assign tlb_rel_xbitmask[3] = + (cam_mask_bits_pt[18]); +assign tlb_rel_maskpar = + (cam_mask_bits_pt[12] | cam_mask_bits_pt[14] + | cam_mask_bits_pt[16]); +assign ex6_data_cmpmask[0] = + (cam_mask_bits_pt[2] | cam_mask_bits_pt[4] + | cam_mask_bits_pt[5] | cam_mask_bits_pt[6] + | cam_mask_bits_pt[7] | cam_mask_bits_pt[9] + | cam_mask_bits_pt[11]); +assign ex6_data_cmpmask[1] = + (cam_mask_bits_pt[2] | cam_mask_bits_pt[7] + | cam_mask_bits_pt[9] | cam_mask_bits_pt[10] + | cam_mask_bits_pt[11]); +assign ex6_data_cmpmask[2] = + (cam_mask_bits_pt[2] | cam_mask_bits_pt[7] + | cam_mask_bits_pt[8] | cam_mask_bits_pt[10] + | cam_mask_bits_pt[11]); +assign ex6_data_cmpmask[3] = + (cam_mask_bits_pt[2] | cam_mask_bits_pt[7] + | cam_mask_bits_pt[8] | cam_mask_bits_pt[11] + ); +assign ex6_data_xbitmask[0] = + (cam_mask_bits_pt[1]); +assign ex6_data_xbitmask[1] = + (cam_mask_bits_pt[5]); +assign ex6_data_xbitmask[2] = + (cam_mask_bits_pt[3]); +assign ex6_data_xbitmask[3] = + (cam_mask_bits_pt[4]); +assign ex6_data_maskpar = + (cam_mask_bits_pt[1] | cam_mask_bits_pt[3] + | cam_mask_bits_pt[6]); + +//assign_end + + assign wr_array_val = (por_seq_q != PorSeq_Idle) ? por_wr_array_val : + (csinv_complete == 1'b1) ? 2'b0 : // csync or isync enabled and complete + (tlb_rel_val_q[0:3] != 4'b0000 & tlb_rel_val_q[4] == 1'b1) ? {2{tlb_rel_data_q[eratpos_wren]}} : // tlb hit reload + ((|(ex6_valid_q[0:`THREADS - 1])) == 1'b1 & ex6_ttype_q[1] == 1'b1 & ex6_ws_q == 2'b00 & ex6_tlbsel_q == TlbSel_IErat) ? {2{1'b1}} : // eratwe WS=0 + 2'b0; + // tlb_high_data + // 84 - 0 - X-bit + // 85:87 - 1:3 - reserved (3b) + // 88:117 - 4:33 - RPN (30b) + // 118:119 - 34:35 - R,C + // 120:121 - 36:37 - WLC (2b) + // 122 - 38 - ResvAttr + // 123 - 39 - VF + // 124 - 40 - IND + // 125:128 - 41:44 - U0-U3 + // 129:133 - 45:49 - WIMGE + // 134:136 - 50:52 - UX,UW,UR + // 137:139 - 53:55 - SX,SW,SR + // 140 - 56 - GS + // 141 - 57 - TS + // 142:143 - 58:59 - reserved (2b) + // 144:149 - 60:65 - 6b TID msbs + // 150:157 - 66:73 - 8b TID lsbs + // 158:167 - 74:83 - parity 10bits + + // 16x143 version, 42b RA + // wr_array_data + // 0:29 - RPN + // 30:31 - R,C + // 32:33 - WLC + // 34 - ResvAttr + // 35 - VF + // 36:39 - U0-U3 + // 40:44 - WIMGE + // 45:46 - UX,SX + // 47:48 - UW,SW + // 49:50 - UR,SR + // 51:60 - CAM parity + // 61:67 - Array parity + + // wr_ws1_data (HI) + // 0:7 - unused + // 8:9 - WLC + // 10 - ResvAttr + // 11 - unused + // 12:15 - U0-U3 + // 16:17 - R,C + // 18:21 - unused + // 22:51 - RPN + // 52:56 - WIMGE + // 57 - VF (not supported in ierat) + // 58:59 - UX,SX + // 60:61 - UW,SW + // 62:63 - UR,SR + + assign wr_array_data_nopar = (por_seq_q != PorSeq_Idle) ? por_wr_array_data[0:50] : + (tlb_rel_val_q[0:3] != 4'b0000 & tlb_rel_val_q[4] == 1'b1) ? {tlb_rel_data_q[70:101], tlb_rel_data_q[103:121]} : // tlb hit reload + ((|(ex6_valid_q[0:`THREADS - 1])) == 1'b1 & ex6_ttype_q[1] == 1'b1 & ex6_ws_q == 2'b00) ? {ex6_rpn_holdreg[22:51], ex6_rpn_holdreg[16:17], ex6_rpn_holdreg[8:10], 1'b0, ex6_rpn_holdreg[12:15], ex6_rpn_holdreg[52:56], ex6_rpn_holdreg[58:63]} : // eratwe WS=0 + {array_data_width-17{1'b0}}; + + // PARITY DEF's + // wr_cam_val(0) -> cmpmask(0:7), cmpmask_par + // cmpmasks(0:7) - wr_cam_data 75:82 - wr_cam_data(83) <- parity from table + // wr_cam_val(0) -> epn(0:51), xbit, size(0:2), V, ThdID(0:3), class(0:1), array_dat(51:58) + // epn(0:7) - wr_cam_data 0:7 - wr_array_par(51) + // epn(8:15) - wr_cam_data 8:15 - wr_array_par(52) + // epn(16:23) - wr_cam_data 16:23 - wr_array_par(53) + // epn(24:31) - wr_cam_data 24:31 - wr_array_par(54) + // epn(32:39) - wr_cam_data 32:39 - wr_array_par(55) + // epn(40:47) - wr_cam_data 40:47 - wr_array_par(56) + // epn(48:51),xbit,size(0:2) - wr_cam_data 48:55 - wr_array_par(57) + // V,ThdID(0:3),class(0:1) - wr_cam_data 56:62 - wr_array_par(58) + assign wr_array_par[51] = ^(wr_cam_data[0:7]); + assign wr_array_par[52] = ^(wr_cam_data[8:15]); + assign wr_array_par[53] = ^(wr_cam_data[16:23]); + assign wr_array_par[54] = ^(wr_cam_data[24:31]); + assign wr_array_par[55] = ^(wr_cam_data[32:39]); + assign wr_array_par[56] = ^(wr_cam_data[40:47]); + assign wr_array_par[57] = ^(wr_cam_data[48:55]); + assign wr_array_par[58] = ^(wr_cam_data[57:62]); // leave V-bit 56 out of parity calculation + + // wr_cam_val(1) -> extclass, tid_nz, gs, as, tid(6:13), array_dat(59:60) + // extclass,tid_nz,gs,as - wr_cam_data 63:66 - wr_array_par(59) + // tid(6:13) - wr_cam_data 67:74 - wr_array_par(60) + assign wr_array_par[59] = ^(wr_cam_data[63:66]); + assign wr_array_par[60] = ^(wr_cam_data[67:74]); + + // wr_array_val(0) -> rpn(22:51), array_dat(61:64) + // rpn(22:27) - wr_array_data 0:5 - wr_array_par(61) + // rpn(28:35) - wr_array_data 6:13 - wr_array_par(62) + // rpn(36:43) - wr_array_data 14:21 - wr_array_par(63) + // rpn(44:51) - wr_array_data 22:29 - wr_array_par(64) + assign wr_array_par[61] = ^(wr_array_data_nopar[0:5]); + assign wr_array_par[62] = ^(wr_array_data_nopar[6:13]); + assign wr_array_par[63] = ^(wr_array_data_nopar[14:21]); + assign wr_array_par[64] = ^(wr_array_data_nopar[22:29]); + // wr_array_val(1) -> R,C, WLC(0:1), resvattr, VF, ubits(0:3), wimge(0:4), UX,SX,UW,SW,UR,SR, array_dat(65:67) + // R,C,WLC(0:1),resvattr,VF,ubits(0:1) - wr_array_data 30:37 - wr_array_par(65) + // ubits(2:3),WIMGE(0:4) - wr_array_data 38:44 - wr_array_par(66) + // UX,SX,UW,SW,UR,SR - wr_array_data 45:50 - wr_array_par(67) + assign wr_array_par[65] = ^(wr_array_data_nopar[30:37]); + assign wr_array_par[66] = ^(wr_array_data_nopar[38:44]); + assign wr_array_par[67] = ^(wr_array_data_nopar[45:50]); + + assign wr_array_data[0:50] = wr_array_data_nopar; + + assign wr_array_data[51:67] = ((tlb_rel_val_q[0:3] != 4'b0000 & tlb_rel_val_q[4] == 1'b1) | // tlb hit reload + por_seq_q != PorSeq_Idle) ? // por boot sequence + {wr_array_par[51:60], wr_array_par[61:67]} : + // mmucr1_q(5 to 6): IPEI parity error inject on epn or rpn side + ((|(ex6_valid_q[0:`THREADS-1])) == 1'b1 & ex6_ttype_q[1] == 1'b1 & ex6_ws_q == 2'b00) ? {(wr_array_par[51] ^ mmucr1_q[5]), wr_array_par[52:60], (wr_array_par[61] ^ mmucr1_q[6]), wr_array_par[62:67]} : // eratwe WS=0 + 17'b0; + + // Parity Checking + assign unused_dc[22] = lcb_delay_lclkr_dc[1] | lcb_mpw1_dc_b[1]; + assign iu2_cmp_data_calc_par[50] = ^(iu2_cam_cmp_data_q[75:82]); // cmp/x mask on epn side + + assign iu2_cmp_data_calc_par[51] = ^(iu2_cam_cmp_data_q[0:7]); + assign iu2_cmp_data_calc_par[52] = ^(iu2_cam_cmp_data_q[8:15]); + assign iu2_cmp_data_calc_par[53] = ^(iu2_cam_cmp_data_q[16:23]); + assign iu2_cmp_data_calc_par[54] = ^(iu2_cam_cmp_data_q[24:31]); + assign iu2_cmp_data_calc_par[55] = ^(iu2_cam_cmp_data_q[32:39]); + assign iu2_cmp_data_calc_par[56] = ^(iu2_cam_cmp_data_q[40:47]); + assign iu2_cmp_data_calc_par[57] = ^(iu2_cam_cmp_data_q[48:55]); + assign iu2_cmp_data_calc_par[58] = ^(iu2_cam_cmp_data_q[57:62]); // leave V-bit 56 out of parity calc + assign iu2_cmp_data_calc_par[59] = ^(iu2_cam_cmp_data_q[63:66]); + assign iu2_cmp_data_calc_par[60] = ^(iu2_cam_cmp_data_q[67:74]); + + assign iu2_cmp_data_calc_par[61] = ^(iu2_array_cmp_data_q[0:5]); + assign iu2_cmp_data_calc_par[62] = ^(iu2_array_cmp_data_q[6:13]); + assign iu2_cmp_data_calc_par[63] = ^(iu2_array_cmp_data_q[14:21]); + assign iu2_cmp_data_calc_par[64] = ^(iu2_array_cmp_data_q[22:29]); + assign iu2_cmp_data_calc_par[65] = ^(iu2_array_cmp_data_q[30:37]); + assign iu2_cmp_data_calc_par[66] = ^(iu2_array_cmp_data_q[38:44]); + assign iu2_cmp_data_calc_par[67] = ^(iu2_array_cmp_data_q[45:50]); + + + assign ex4_rd_data_calc_par[50] = ^(ex4_rd_cam_data_q[75:82]); // cmp/x mask on epn side + + assign ex4_rd_data_calc_par[51] = ^(ex4_rd_cam_data_q[0:7]); + assign ex4_rd_data_calc_par[52] = ^(ex4_rd_cam_data_q[8:15]); + assign ex4_rd_data_calc_par[53] = ^(ex4_rd_cam_data_q[16:23]); + assign ex4_rd_data_calc_par[54] = ^(ex4_rd_cam_data_q[24:31]); + assign ex4_rd_data_calc_par[55] = ^(ex4_rd_cam_data_q[32:39]); + assign ex4_rd_data_calc_par[56] = ^(ex4_rd_cam_data_q[40:47]); + assign ex4_rd_data_calc_par[57] = ^(ex4_rd_cam_data_q[48:55]); + assign ex4_rd_data_calc_par[58] = ^(ex4_rd_cam_data_q[57:62]); // leave V-bit 56 out of parity calc + assign ex4_rd_data_calc_par[59] = ^(ex4_rd_cam_data_q[63:66]); + assign ex4_rd_data_calc_par[60] = ^(ex4_rd_cam_data_q[67:74]); + + assign ex4_rd_data_calc_par[61] = ^(ex4_rd_array_data_q[0:5]); + assign ex4_rd_data_calc_par[62] = ^(ex4_rd_array_data_q[6:13]); + assign ex4_rd_data_calc_par[63] = ^(ex4_rd_array_data_q[14:21]); + assign ex4_rd_data_calc_par[64] = ^(ex4_rd_array_data_q[22:29]); + assign ex4_rd_data_calc_par[65] = ^(ex4_rd_array_data_q[30:37]); + assign ex4_rd_data_calc_par[66] = ^(ex4_rd_array_data_q[38:44]); + assign ex4_rd_data_calc_par[67] = ^(ex4_rd_array_data_q[45:50]); + + generate + begin + if (check_parity == 0) + begin + assign iu2_cmp_data_parerr_epn = 1'b0; + assign iu2_cmp_data_parerr_rpn = 1'b0; + end + if (check_parity == 1) + begin + assign iu2_cmp_data_parerr_epn = |(iu2_cmp_data_calc_par[50:60] ^ {iu2_cam_cmp_data_q[83], iu2_array_cmp_data_q[51:60]}); // epn side cmp out parity error + assign iu2_cmp_data_parerr_rpn = |(iu2_cmp_data_calc_par[61:67] ^ iu2_array_cmp_data_q[61:67]); // rpn side cmp out parity error + end + + if (check_parity == 0) + begin + assign ex4_rd_data_parerr_epn = 1'b0; + assign ex4_rd_data_parerr_rpn = 1'b0; + end + if (check_parity == 1) + begin + assign ex4_rd_data_parerr_epn = |(ex4_rd_data_calc_par[50:60] ^ {ex4_rd_cam_data_q[83], ex4_rd_array_data_q[51:60]}); // epn side rd out parity error + assign ex4_rd_data_parerr_rpn = |(ex4_rd_data_calc_par[61:67] ^ ex4_rd_array_data_q[61:67]); // rpn side rd out parity error + end + end + endgenerate + + + // CAM Port + assign flash_invalidate = (por_seq_q == PorSeq_Stg1) | mchk_flash_inv_enab; + + assign comp_invalidate = (csinv_complete == 1'b1) ? 1'b1 : // csync or isync enabled and complete + (tlb_rel_val_q[0:3] != 4'b0000 & tlb_rel_val_q[4] == 1'b1) ? 1'b0 : // tlb hit reload + (snoop_val_q[0:1] == 2'b11) ? 1'b1 : // invalidate snoop + 1'b0; + + assign comp_request = (csinv_complete) | // csync or isync enabled and complete + (snoop_val_q[0] & snoop_val_q[1] & (~(|(tlb_rel_val_q[0:3]))) ) | // invalidate snoop + (ex1_ieratsx) | // eratsx + (iu_ierat_iu0_val); // fetch + + generate + if (rs_data_width == 64) + begin + assign comp_addr_mux1 = (snoop_addr_q & {epn_width{snoop_val_q[0] & snoop_val_q[1]}}) | // invalidate snoop + (xu_iu_rb & {rs_data_width-12{(~(snoop_val_q[0] & snoop_val_q[1])) & ex1_ieratsx}}); // eratsx + + assign comp_addr_mux1_sel = (snoop_val_q[0] & snoop_val_q[1]) | (ex1_ieratsx & snoop_val_q[1]); // snoop or eratsx + + assign comp_addr = (comp_addr_mux1 & {epn_width{comp_addr_mux1_sel}}) | // invalidate snoop or eratsx + (iu_ierat_iu0_ifar & {epn_width{~comp_addr_mux1_sel}}); // fetch, or I$ back_inv + end + endgenerate // 64-bit model + + assign iu_xu_ierat_ex2_flush_d = (ex1_valid_q & (~(xu_ex1_flush)) & {`THREADS{ex1_ieratsx & (csinv_complete | ~snoop_val_q[1])}}) | + (ex1_valid_q & (~(xu_ex1_flush)) & {`THREADS{(ex1_ieratre | ex1_ieratwe | ex1_ieratsx) & tlb_rel_act_q}}); + + assign iu_xu_ord_n_flush_req = |(iu_xu_ierat_ex2_flush_q); + + // snoop_attr: + // 0 -> Local + // 1:3 -> IS/Class: 0=all, 1=tid, 2=gs, 3=epn, 4=class0, 5=class1, 6=class2, 7=class3 + // 4:5 -> GS/TS + // 6:13 -> TID(6:13) + // 14:17 -> Size + // 18 -> reserved for tlb, extclass_enable(0) for erats + // 19 -> mmucsr0.tlb0fi for tlb, or TID_NZ for erats + // 20:25 -> TID(0:5) + + assign addr_enable[0] = (~(csinv_complete)) & // not csync or isync enabled and complete + ( (snoop_val_q[0] & snoop_val_q[1] & (~snoop_attr_q[1]) & snoop_attr_q[2] & snoop_attr_q[3]) | // T=3, va invalidate snoop + ( (|(ex1_valid_q[0:`THREADS-1])) & ex1_ttype_q[2] & ex1_tlbsel_q[0] & (~ex1_tlbsel_q[1]) & (~(snoop_val_q[0] & snoop_val_q[1])) ) | // eratsx, tlbsel=2 + ( iu_ierat_iu0_val & (~(snoop_val_q[0] & snoop_val_q[1])) ) ); // fetch + + assign addr_enable[1] = (~(csinv_complete)) & // not csync or isync enabled and complete + ( (snoop_val_q[0] & snoop_val_q[1] & snoop_attr_q[0] & (~snoop_attr_q[1]) & snoop_attr_q[2] & snoop_attr_q[3]) | // Local T=3, va invalidate snoop + ( (|(ex1_valid_q[0:`THREADS-1])) & ex1_ttype_q[2] & ex1_tlbsel_q[0] & (~ex1_tlbsel_q[1]) & (~(snoop_val_q[0] & snoop_val_q[1])) ) | // eratsx, tlbsel=2 + ( iu_ierat_iu0_val & (~(snoop_val_q[0] & snoop_val_q[1])) ) ); // fetch + + assign comp_pgsize = (snoop_attr_q[14:17] == WS0_PgSize_1GB) ? CAM_PgSize_1GB : + (snoop_attr_q[14:17] == WS0_PgSize_16MB) ? CAM_PgSize_16MB : + (snoop_attr_q[14:17] == WS0_PgSize_1MB) ? CAM_PgSize_1MB : + (snoop_attr_q[14:17] == WS0_PgSize_64KB) ? CAM_PgSize_64KB : + CAM_PgSize_4KB; + + assign pgsize_enable = (csinv_complete == 1'b1) ? 1'b0 : // csync or isync enabled and complete + (snoop_val_q[0:1] == 2'b11 & snoop_attr_q[0:3] == 4'b0011) ? 1'b1 : // non-local va-based invalidate snoop + 1'b0; + + // mmucr1_q: 0-IRRE, 1-REE, 2-CEE, 3-csync_dis, 4-isync_dis, 5:6-IPEI, 7:8-ICTID/ITTID + + assign comp_class = (snoop_attr_q[20:21] & {2{snoop_val_q[0] & snoop_val_q[1] & mmucr1_q[7]}}) | // ICTID=1 invalidate snoop + (snoop_attr_q[2:3] & {2{snoop_val_q[0] & snoop_val_q[1] & (~mmucr1_q[7])}}) | // T=4to7 + (ex1_pid_q[pid_width - 14:pid_width - 13] & {2{(~(snoop_val_q[0] & snoop_val_q[1])) & mmucr1_q[7] & ex1_ieratsx}}) | // ICTID=1 eratsx + (iu1_pid_d[pid_width - 14:pid_width - 13] & {2{(~(snoop_val_q[0] & snoop_val_q[1])) & mmucr1_q[7] & (~(ex1_ieratsx))}}); // ICTID=1 + + assign class_enable[0] = (mmucr1_q[7] == 1'b1) ? 1'b0 : // mmucr1.ICTID=1 + (csinv_complete == 1'b1) ? 1'b0 : // csync or isync enabled and complete + (snoop_val_q[0:1] == 2'b11 & snoop_attr_q[1] == 1'b1) ? 1'b1 : // T=4to7, class invalidate snoop + 1'b0; + assign class_enable[1] = (mmucr1_q[7] == 1'b1) ? 1'b0 : // mmucr1.ICTID=1 + (csinv_complete == 1'b1) ? 1'b0 : // csync or isync enabled and complete + (snoop_val_q[0:1] == 2'b11 & snoop_attr_q[1] == 1'b1) ? 1'b1 : // T=4to7, class invalidate snoop + 1'b0; + assign class_enable[2] = (mmucr1_q[7] == 1'b0) ? 1'b0 : // mmucr1.ICTID=0 + pid_enable; + + // snoop_attr: + // 0 -> Local + // 1:3 -> IS/Class: 0=all, 1=tid, 2=gs, 3=epn, 4=class0, 5=class1, 6=class2, 7=class3 + // 4:5 -> GS/TS + // 6:13 -> TID(6:13) + // 14:17 -> Size + // 18 -> reserved for tlb, extclass_enable(0) for erats + // 19 -> mmucsr0.tlb0fi for tlb, or TID_NZ for erats + // 20:25 -> TID(0:5) + assign comp_extclass[0] = 1'b0; //extclass compare value + assign comp_extclass[1] = snoop_attr_q[19]; //TID_NZ compare value + + assign extclass_enable[0] = csinv_complete | // csync or isync enabled and complete + (snoop_val_q[0] & snoop_val_q[1] & snoop_attr_q[18]); // any invalidate snoop + assign extclass_enable[1] = (~csinv_complete) & + (snoop_val_q[0] & snoop_val_q[1] & (~snoop_attr_q[1]) & snoop_attr_q[3]); // any invalidate snoop, compare TID_NZ for inval by pid or va + + + // state: 0:pr 1:gs 2:is 3:cm + // cam state bits are 0:HS, 1:AS + assign comp_state = (snoop_attr_q[4:5] & {2{snoop_val_q[0] & snoop_val_q[1] & (~snoop_attr_q[1]) & snoop_attr_q[2]}}) | // attr="01", gs or va snoop; + (ex1_state_q[1:2] & {2{(~(snoop_val_q[0] & snoop_val_q[1])) & ex1_ieratsx}}) | // eratsx + (iu1_state_d[1:2] & {2{(~(snoop_val_q[0] & snoop_val_q[1])) & (~ex1_ieratsx)}}); + + assign state_enable[0] = (~(csinv_complete)) & // not csync or isync enabled and complete + ( (snoop_val_q[0] & snoop_val_q[1] & (~snoop_attr_q[1]) & snoop_attr_q[2]) | // T=2 or 3, gs or va invalidate snoop + ( (|(ex1_valid_q[0:`THREADS-1])) & ex1_ttype_q[2] & ex1_tlbsel_q[0] & (~ex1_tlbsel_q[1]) & (~(snoop_val_q[0] & snoop_val_q[1])) ) | // eratsx, tlbsel=2 + ( iu_ierat_iu0_val & (~(snoop_val_q[0] & snoop_val_q[1])) ) ); // fetch + + assign state_enable[1] = (~(csinv_complete)) & // not csync or isync enabled and complete + ( (snoop_val_q[0] & snoop_val_q[1] & (~snoop_attr_q[1]) & snoop_attr_q[2] & snoop_attr_q[3]) | // T=3, va invalidate snoop + ( (|(ex1_valid_q[0:`THREADS-1])) & ex1_ttype_q[2] & ex1_tlbsel_q[0] & (~ex1_tlbsel_q[1]) & (~(snoop_val_q[0] & snoop_val_q[1])) ) | // eratsx, tlbsel=2 + ( iu_ierat_iu0_val & (~(snoop_val_q[0] & snoop_val_q[1])) ) ); // fetch + + generate + begin : xhdl3 + genvar tid; + for (tid = 0; tid <= 3; tid = tid + 1) + begin : compTids + if (tid < `THREADS) + begin : validTid + assign comp_thdid[tid] = (snoop_attr_q[22+tid] & (mmucr1_q[8] & snoop_val_q[0] & snoop_val_q[1])) | // ITTID=1 invalidate snoop + (ex1_pid_q[pid_width-12+tid] & (mmucr1_q[8] & (~(snoop_val_q[0] & snoop_val_q[1])) & ex1_ieratsx)) | // ITTID=1 eratsx + (iu1_pid_d[pid_width-12+tid] & (mmucr1_q[8] & (~(snoop_val_q[0] & snoop_val_q[1])) & (~ex1_ieratsx))) | // ITTID=1 + (snoop_val_q[0] & snoop_val_q[1] & (~mmucr1_q[8])) | // invalidate snoop + (ex1_valid_q[tid] & (ex1_ttype_q[2] & ex1_tlbsel_q[0] & (~ex1_tlbsel_q[1]) & (~(snoop_val_q[0] & snoop_val_q[1])) & (~mmucr1_q[8]))) | // eratsx + (iu_ierat_iu0_thdid[tid] & (((~|(ex1_valid_q[0:`THREADS - 1])) | (~ex1_ttype_q[2]) | (ex1_tlbsel_q != TlbSel_IErat)) & (~(snoop_val_q[0] & snoop_val_q[1])) & (~mmucr1_q[8])) ); + end + if (tid >= `THREADS) + begin : nonValidTid + assign comp_thdid[tid] = (snoop_attr_q[22+tid] & (mmucr1_q[8] & snoop_val_q[0] & snoop_val_q[1])) | // ITTID=1 invalidate snoop + (ex1_pid_q[pid_width-12+tid] & (mmucr1_q[8] & (~(snoop_val_q[0] & snoop_val_q[1])) & ex1_ieratsx)) | // ITTID=1 eratsx + (iu1_pid_d[pid_width-12+tid] & (mmucr1_q[8] & (~(snoop_val_q[0] & snoop_val_q[1])) & (~ex1_ieratsx))) | // ITTID=1 + (snoop_val_q[0] & snoop_val_q[1] & (~mmucr1_q[8])); // invalidate snoop + end + end + end + endgenerate + + assign thdid_enable[0] = ( (iu_ierat_iu0_val | (|(ex1_valid_q[0:`THREADS - 1])) & ex1_ttype_q[2] & ex1_tlbsel_q[0] & (~ex1_tlbsel_q[1])) & + ((~mmucr1_q[8]) & (~(snoop_val_q[0] & snoop_val_q[1])) & (~(csinv_complete))) ); + assign thdid_enable[1] = pid_enable & mmucr1_q[8]; // 0 when mmucr1.ITTID=0 + + assign comp_pid = (snoop_attr_q[6:13] & {8{snoop_val_q[0] & snoop_val_q[1]}}) | // invalidate snoop + (ex1_pid_q[pid_width-8:pid_width-1] & + {8{ (|(ex1_valid_q[0:`THREADS - 1])) & ex1_ttype_q[2] & ex1_tlbsel_q[0] & (~ex1_tlbsel_q[1]) & (~(snoop_val_q[0] & snoop_val_q[1]))}} ) | // eratsx + (iu1_pid_d[pid_width-8:pid_width-1] & + {8{( ~( (|(ex1_valid_q[0:`THREADS - 1])) & ex1_ttype_q[2] & ex1_tlbsel_q[0] & (~ex1_tlbsel_q[1])) & (~(snoop_val_q[0] & snoop_val_q[1])))}} ); + + assign pid_enable = (~(csinv_complete)) & // not csync or isync enabled and complete + ( (snoop_val_q[0] & snoop_val_q[1] & (~snoop_attr_q[1]) & snoop_attr_q[3]) | // T=1, pid invalidate snoop, T=3, va invalidate snoop + ( (|(ex1_valid_q[0:`THREADS - 1])) & ex1_ttype_q[2] & ex1_tlbsel_q[0] & (~ex1_tlbsel_q[1]) & (~(snoop_val_q[0] & snoop_val_q[1])) ) | // eratsx, tlbsel=2 + (iu_ierat_iu0_val & (~(snoop_val_q[0] & snoop_val_q[1]))) ); // fetch + + // wr_cam_data + // 0:51 - EPN + // 52 - X + // 53:55 - SIZE + // 56 - V + // 57:60 - ThdID + // 61:62 - Class + // 63:64 - ExtClass | TID_NZ + // 65 - TGS + // 66 - TS + // 67:74 - TID + // 75:78 - epn_cmpmasks: 34_39, 40_43, 44_47, 48_51 + // 79:82 - xbit_cmpmasks: 34_51, 40_51, 44_51, 48_51 + // 83 - parity for 75:82 + + // 16x143 version, 42b RA + // wr_array_data + // 0:29 - RPN + // 30:31 - R,C + // 32:33 - WLC + // 34 - ResvAttr + // 35 - VF + // 36:39 - U0-U3 + // 40:44 - WIMGE + // 45:46 - UX,SX + // 47:48 - UW,SW + // 49:50 - UR,SR + // 51:60 - CAM parity + // 61:67 - Array parity + + // wr_ws0_data (LO) + // 0:51 - EPN + // 52:53 - Class + // 54 - V + // 55 - X + // 56:59 - SIZE + // 60:63 - ThdID + + // CAM.ExtClass - MMUCR ExtClass + // CAM.TS - MMUCR TS + // CAM.TID - MMUCR TID + + // wr_ws1_data (HI) + // 0:7 - unused + // 8:9 - WLC + // 10 - ResvAttr + // 11 - unused + // 12:15 - U0-U3 + // 16:17 - R,C + // 18:21 - unused + // 22:51 - RPN + // 52:56 - WIMGE + // 57 - VF (not supported in ierat) + // 58:59 - UX,SX + // 60:61 - UW,SW + // 62:63 - UR,SR + + generate + if (data_out_width == 64) + begin : gen64_data_out + assign ex4_data_out_d = + ( {32'b0, rd_cam_data[32:51], + (rd_cam_data[61:62] & {2{~(mmucr1_q[7])}}), + rd_cam_data[56], rd_cam_data[52], ws0_pgsize[0:3], + (rd_cam_data[57:58] | {2{mmucr1_q[8]}}), 2'b0} & + {data_out_width{(|(ex3_valid_q)) & ex3_ttype_q[0] & (~ex3_ws_q[0]) & (~ex3_ws_q[1]) & (~ex3_state_q[3])}} ) | // eratre, WS=0, cm=32b + ( {32'b0, rd_array_data[10:29], 2'b00, rd_array_data[0:9]} & + {data_out_width{(|(ex3_valid_q)) & ex3_ttype_q[0] & (~ex3_ws_q[0]) & ex3_ws_q[1] & (~ex3_state_q[3])}} ) | // eratre, WS=1, cm=32b + ( {32'b0, 8'b00000000, rd_array_data[32:34], 1'b0, rd_array_data[36:39], rd_array_data[30:31], 2'b00, + rd_array_data[40:44], 1'b0, rd_array_data[45:50]} & // VF doesn't exist in ierat + {data_out_width{(|(ex3_valid_q)) & ex3_ttype_q[0] & ex3_ws_q[0] & (~ex3_ws_q[1]) & (~ex3_state_q[3])}} ) | // eratre, WS=2, cm=32b + ( {rd_cam_data[0:51], + (rd_cam_data[61:62] & {2{~(mmucr1_q[7])}}), + rd_cam_data[56], rd_cam_data[52], ws0_pgsize[0:3], + (rd_cam_data[57:58] | {2{mmucr1_q[8]}}), 2'b0} & + {data_out_width{(|(ex3_valid_q)) & ex3_ttype_q[0] & (~ex3_ws_q[0]) & (~ex3_ws_q[1]) & ex3_state_q[3]}} ) | // eratre, WS=0, cm=64b + ( {8'b00000000, rd_array_data[32:34], 1'b0, rd_array_data[36:39], rd_array_data[30:31], 4'b0000, rd_array_data[0:29], rd_array_data[40:44], 1'b0, rd_array_data[45:50]} & // VF doesn't exist in ierat + {data_out_width{(|(ex3_valid_q)) & ex3_ttype_q[0] & (~ex3_ws_q[0]) & ex3_ws_q[1] & ex3_state_q[3]}} ) | // eratre, WS=1, cm=64b + ( {60'b0, eptr_q} & + {data_out_width{(|(ex3_valid_q)) & ex3_ttype_q[0] & ex3_ws_q[0] & ex3_ws_q[1] & mmucr1_q[0]}} ) | // eratre, WS=3, IRRE=1 + ( {60'b0, lru_way_encode} & + {data_out_width{(|(ex3_valid_q)) & ex3_ttype_q[0] & ex3_ws_q[0] & ex3_ws_q[1] & (~mmucr1_q[0])}} ) | // eratre, WS=3, IRRE=0 + ( {50'b0, ex3_eratsx_data_q[0:1], 8'b0, ex3_eratsx_data_q[2:2 + num_entry_log2 - 1]} & + {data_out_width{(|(ex3_valid_q)) & ex3_ttype_q[2]}} ); // eratsx + end + endgenerate + + generate + if (data_out_width == 32) + begin : gen32_data_out + assign ex4_data_out_d = (({rd_cam_data[32:51], + (rd_cam_data[61:62] & {2{~(mmucr1_q[7])}}), + rd_cam_data[56], rd_cam_data[52], ws0_pgsize[0:3], + (rd_cam_data[57:58] | {2{mmucr1_q[8]}}), 2'b0}) & + ({data_out_width{(|(ex3_valid_q) & ex3_ttype_q[0] & (~ex3_ws_q[0]) & (~ex3_ws_q[1]))}})) | + (({rd_array_data[10:29], 2'b00, rd_array_data[0:9]}) & + ({data_out_width{(|(ex3_valid_q) & ex3_ttype_q[0] & (~ex3_ws_q[0]) & ex3_ws_q[1])}})) | + (({8'b00000000, rd_array_data[32:34], 1'b0, rd_array_data[36:39], rd_array_data[30:31], 2'b00, + rd_array_data[40:44], 1'b0, rd_array_data[45:50]}) & // VF doesn't exist in ierat + ({data_out_width{(|(ex3_valid_q) & ex3_ttype_q[0] & ex3_ws_q[0] & (~ex3_ws_q[1]))}})) | + (({({28{1'b0}}), eptr_q}) & + ({data_out_width{(|(ex3_valid_q) & ex3_ttype_q[0] & ex3_ws_q[0] & ex3_ws_q[1] & mmucr1_q[0])}})) | + (({({28{1'b0}}), lru_way_encode}) & + ({data_out_width{(|(ex3_valid_q) & ex3_ttype_q[0] & ex3_ws_q[0] & ex3_ws_q[1] & (~mmucr1_q[0]))}})) | + (({({18{1'b0}}), ex3_eratsx_data_q[0:1], ({8{1'b0}}), ex3_eratsx_data_q[2:2 + num_entry_log2 - 1]}) & + ({data_out_width{(|(ex3_valid_q) & ex3_ttype_q[2])}})); + end + endgenerate + + // TIMING FIX RESTRUCTURING use cam_cmp_data(75:78) cmpmask bits + // wr_cam_data(75) (76) (77) (78) (79) (80) (81) (82) + // cmpmask(0) (1) (2) (3) xbitmask(0) (1) (2) (3) + // xbit pgsize 34_39 40_43 44_47 48_51 34_39 40_43 44_47 48_51 size + // 0 001 1 1 1 1 0 0 0 0 4K + // 0 011 1 1 1 0 0 0 0 0 64K + // 0 101 1 1 0 0 0 0 0 0 1M + // 0 111 1 0 0 0 0 0 0 0 16M + // 0 110 0 0 0 0 0 0 0 0 1G + + // new cam _np2 bypass attributes (bit numbering per array) + // 30:31 - R,C + // 32:33 - WLC + // 34 - ResvAttr + // 35 - VF + // 36:39 - U0-U3 + // 40:44 - WIMGE + // 45:46 - UX,SX + // 47:48 - UW,SW + // 49:50 - UR,SR + + assign bypass_mux_enab_np1 = (ccr2_frat_paranoia_q[9] | iu_ierat_iu1_back_inv | an_ac_grffence_en_dc); + assign bypass_attr_np1[0:5] = 6'b0; // new cam _np1 bypass attributes in + assign bypass_attr_np1[6:9] = ccr2_frat_paranoia_q[5:8]; // new cam _np1 bypass ubits attributes in + assign bypass_attr_np1[10:14] = ccr2_frat_paranoia_q[0:4]; // new cam _np1 bypass wimge attributes in + assign bypass_attr_np1[15:20] = 6'b111111; // new cam _np1 bypass protection attributes in + + assign ierat_iu_iu2_error[0] = iu2_miss_sig | iu2_multihit_sig | iu2_parerr_sig | iu2_isi_sig; + assign ierat_iu_iu2_error[1] = iu2_miss_sig | iu2_multihit_sig; + assign ierat_iu_iu2_error[2] = iu2_miss_sig | iu2_parerr_sig; + + // added these outputs for timing in iuq_ic + assign ierat_iu_iu2_miss = iu2_miss_sig; + assign ierat_iu_iu2_multihit = iu2_multihit_sig; + assign ierat_iu_iu2_isi = iu2_isi_sig; + + assign ierat_iu_hold_req = hold_req_q; + assign ierat_iu_iu2_flush_req = iu2_n_flush_req_q; + assign iu_xu_ex4_data = ex4_data_out_q; + + assign iu_mm_ierat_req = iu2_tlbreq_q; + assign iu_mm_ierat_req_nonspec = iu2_nonspec_q; + assign iu_mm_ierat_thdid = iu2_valid_q; + assign iu_mm_ierat_state = iu2_state_q; + assign iu_mm_ierat_tid = iu2_pid_q; + assign iu_mm_ierat_flush = iu_mm_ierat_flush_q; + + assign iu_mm_ierat_mmucr0 = {ex6_extclass_q, ex6_state_q[1:2], ex6_pid_q}; + assign iu_mm_ierat_mmucr0_we = ((ex6_ttype_q[0] == 1'b1 & ex6_ws_q == 2'b00 & ex6_tlbsel_q == TlbSel_IErat)) ? ex6_valid_q : + {`THREADS{1'b0}}; + + assign iu_mm_ierat_mmucr1 = ex6_ieen_q[`THREADS:`THREADS+num_entry_log2-1]; // error entry found + assign iu_mm_ierat_mmucr1_we = ex6_ieen_q[0:`THREADS-1]; // eratsx, eratre parity error + + assign iu2_perf_itlb_d = iu1_valid_q; + assign iu_mm_perf_itlb = iu2_perf_itlb_q & {`THREADS{iu2_miss_sig}}; + + assign iu_pc_err_ierat_parity_d = iu2_parerr_sig; + + tri_direct_err_rpt #(.WIDTH(1)) err_ierat_parity( + .vd(vdd), + .gd(gnd), + .err_in(iu_pc_err_ierat_parity_q), + .err_out(iu_pc_err_ierat_parity) + ); + + assign iu_pc_err_ierat_multihit_d = iu2_multihit_sig; + + tri_direct_err_rpt #(.WIDTH(1)) err_ierat_multihit( + .vd(vdd), + .gd(gnd), + .err_in(iu_pc_err_ierat_multihit_q), + .err_out(iu_pc_err_ierat_multihit) + ); + + // NOTE: example parity generation/checks in iuq_ic_dir.vhdl or xuq_lsu_dc_arr.vhdl. + + //--------------------------------------------------------------------- + // CAM Instantiation + //--------------------------------------------------------------------- + //ierat_cam: entity work.tri_cam_16x143_1r1w1c + + tri_cam_16x143_1r1w1c ierat_cam( + .gnd(gnd), + .vdd(vdd), + .vcs(vcs), + .nclk(nclk), + + .tc_ccflush_dc(tc_ccflush_dc), + .tc_scan_dis_dc_b(tc_scan_dis_dc_b), + .tc_scan_diag_dc(tc_scan_diag_dc), + .tc_lbist_en_dc(tc_lbist_en_dc), + .an_ac_atpg_en_dc(an_ac_atpg_en_dc), + + .lcb_d_mode_dc(cam_d_mode), + .lcb_clkoff_dc_b(cam_clkoff_b), + .lcb_act_dis_dc(cam_act_dis), + .lcb_mpw1_dc_b(cam_mpw1_b[0:3]), + .lcb_mpw2_dc_b(cam_mpw2_b), + .lcb_delay_lclkr_dc(cam_delay_lclkr[0:3]), + + .pc_sg_2(pc_iu_sg_2), + .pc_func_slp_sl_thold_2(pc_iu_func_slp_sl_thold_2), + .pc_func_slp_nsl_thold_2(pc_iu_func_slp_nsl_thold_2), + .pc_regf_slp_sl_thold_2(pc_iu_regf_slp_sl_thold_2), + .pc_time_sl_thold_2(pc_iu_time_sl_thold_2), + .pc_fce_2(pc_iu_fce_2), + + .func_scan_in(func_scan_in_cam), + .func_scan_out(func_scan_out_cam), + .regfile_scan_in(regf_scan_in), // 0:2 -> CAM, 3:4 -> RAM + .regfile_scan_out(regf_scan_out), + .time_scan_in(time_scan_in), + .time_scan_out(time_scan_out), + + .rd_val(rd_val), // this is actually the internal read act pin + .rd_val_late(tiup), // this is actually the internal read functional pin + .rw_entry(rw_entry), + + .wr_array_data(wr_array_data), + .wr_cam_data(wr_cam_data), + .wr_array_val(wr_array_val), //this is actually the internal write functional pin + .wr_cam_val(wr_cam_val), //this is actually the internal write functional pin + .wr_val_early(wr_val_early), //this is actually the internal write act pin + + .comp_request(comp_request), + .comp_addr(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .comp_class(comp_class), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .state_enable(state_enable), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .comp_invalidate(comp_invalidate), + .flash_invalidate(flash_invalidate), + + .array_cmp_data(array_cmp_data), + .rd_array_data(rd_array_data), + + .cam_cmp_data(cam_cmp_data), + .cam_hit(cam_hit), + .cam_hit_entry(cam_hit_entry), + .entry_match(entry_match), + .entry_valid(entry_valid), + .rd_cam_data(rd_cam_data), + + //--- new ports for IO plus ----------------------- + .bypass_mux_enab_np1(bypass_mux_enab_np1), + .bypass_attr_np1(bypass_attr_np1), + .attr_np2(attr_np2), + .rpn_np2(rpn_np2) + ); + + // bypass attributes (bit numbering per array) + // 30:31 - R,C + // 32:33 - WLC + // 34 - ResvAttr + // 35 - VF + // 36:39 - U0-U3 + // 40:44 - WIMGE + // 45:46 - UX,SX + // 47:48 - UW,SW + // 49:50 - UR,SR + assign ierat_iu_iu2_rpn = rpn_np2; // erat array will always be 30 bits RPN + assign ierat_iu_iu2_wimge = attr_np2[10:14]; + assign ierat_iu_iu2_u = attr_np2[6:9]; + + assign ierat_iu_cam_change = lru_update_event_q[9]; + + // debug bus outputs + assign iu1_debug_d[0] = comp_request; + assign iu1_debug_d[1] = comp_invalidate; + assign iu1_debug_d[2] = csinv_complete; // comp_request term1, csync or isync enabled and complete + assign iu1_debug_d[3] = 1'b0; // comp_request term2, spare + assign iu1_debug_d[4] = (snoop_val_q[0] & snoop_val_q[1] & (~|(tlb_rel_val_q[0:3])) ); // comp_request term3, invalidate snoop, not reload; + assign iu1_debug_d[5] = (ex1_ieratsx); // comp_request term4, eratsx + assign iu1_debug_d[6] = (iu_ierat_iu0_val); // comp_request term5, fetch + assign iu1_debug_d[7] = ( (|(tlb_rel_val_q[0:3])) & tlb_rel_val_q[4] ); // comp_invalidate term2, tlb reload + assign iu1_debug_d[8] = |(tlb_rel_val_q[0:3]); // any tlb reload + assign iu1_debug_d[9] = (snoop_val_q[0] & snoop_val_q[1]); // any snoop + assign iu1_debug_d[10] = 1'b0; // spare + + assign iu2_debug_d[0:10] = iu1_debug_q[0:10]; + assign iu2_debug_d[11:15] = {1'b0, iu1_first_hit_entry}; + assign iu2_debug_d[16] = iu1_multihit; + + assign lru_debug_d[0] = (tlb_rel_data_q[eratpos_wren] & (|(tlb_rel_val_q[0:3])) & tlb_rel_val_q[4]); // lru update term1: tlb reload + assign lru_debug_d[1] = (snoop_val_q[0] & snoop_val_q[1]); //lru update term2: invalidate snoop + assign lru_debug_d[2] = (csinv_complete); // lru update term3: csync or isync enabled and complete + assign lru_debug_d[3] = ( (|(ex6_valid_q[0:`THREADS-1])) & ex6_ttype_q[1] & (~ex6_ws_q[0]) & (~ex6_ws_q[1]) & ex6_tlbsel_q[0] & (~ex6_tlbsel_q[1]) & lru_way_is_written ); // lru update term4: eratwe WS=0 + assign lru_debug_d[4] = ( (|(iu1_valid_q & (~(iu_ierat_iu1_flush)) & (~(xu_iu_flush | br_iu_flush)) & (~(iu2_n_flush_req_q)))) & + (~iu1_flush_enab_q) & cam_hit & lru_way_is_hit_entry ); // lru update term5: fetch hit + assign lru_debug_d[5:19] = lru_eff; + assign lru_debug_d[20:23] = lru_way_encode; + + // debug groups: out std_ulogic_vector(0 to 87); + assign ierat_iu_debug_group0[0:83] = iu2_cam_cmp_data_q[0:83]; + assign ierat_iu_debug_group0[84] = ex3_eratsx_data_q[1]; // cam_hit delayed, iu2 phase in reality + assign ierat_iu_debug_group0[85] = iu2_debug_q[0]; // comp_request + assign ierat_iu_debug_group0[86] = iu2_debug_q[1]; // comp_invalidate + assign ierat_iu_debug_group0[87] = iu2_debug_q[9]; // any snoop + + assign ierat_iu_debug_group1[0:67] = iu2_array_cmp_data_q[0:67]; + assign ierat_iu_debug_group1[68] = ex3_eratsx_data_q[1]; // cam_hit delayed, iu2 phase in reality + assign ierat_iu_debug_group1[69] = iu2_debug_q[16]; //multihit + assign ierat_iu_debug_group1[70:74] = iu2_debug_q[11:15]; //iu2 cam_hit_entry + assign ierat_iu_debug_group1[75] = iu2_debug_q[0]; // comp_request + assign ierat_iu_debug_group1[76] = iu2_debug_q[1]; // comp_invalidate + assign ierat_iu_debug_group1[77] = iu2_debug_q[2]; // comp_request term1, csync or isync enabled + assign ierat_iu_debug_group1[78] = iu2_debug_q[3]; // comp_request term2, write to eplc or epsc, DCTID=0 + assign ierat_iu_debug_group1[79] = iu2_debug_q[4]; // comp_request term3, invalidate snoop, not reload; + assign ierat_iu_debug_group1[80] = iu2_debug_q[5]; // comp_request term4, eratsx + assign ierat_iu_debug_group1[81] = iu2_debug_q[6]; // comp_request term5, load or store + assign ierat_iu_debug_group1[82] = iu2_debug_q[7]; // comp_invalidate term2, tlb reload + assign ierat_iu_debug_group1[83] = iu2_debug_q[8]; // any tlb reload + assign ierat_iu_debug_group1[84] = iu2_debug_q[9]; // any snoop + assign ierat_iu_debug_group1[85] = iu2_debug_q[10]; // spare + assign ierat_iu_debug_group1[86] = iu2_prefetch_q; // spare + assign ierat_iu_debug_group1[87] = lru_update_event_q[7] | lru_update_event_q[8]; // any lru update event + + assign ierat_iu_debug_group2[0:15] = entry_valid_q[0:15]; + assign ierat_iu_debug_group2[16:31] = entry_match_q[0:15]; + assign ierat_iu_debug_group2[32:47] = {1'b0, lru_q[1:15]}; + assign ierat_iu_debug_group2[48:63] = {1'b0, lru_debug_q[5:19]}; // lru_eff(1 to 15) + assign ierat_iu_debug_group2[64:73] = {lru_update_event_q[0:8], iu2_debug_q[16]}; // update events, multihit + assign ierat_iu_debug_group2[74:78] = {1'b0, lru_debug_q[20:23]}; // '0' & lru_way_encode + assign ierat_iu_debug_group2[79:83] = {1'b0, watermark_q[0:3]}; + assign ierat_iu_debug_group2[84] = ex3_eratsx_data_q[1]; // cam_hit delayed + assign ierat_iu_debug_group2[85] = iu2_debug_q[0]; // comp_request + assign ierat_iu_debug_group2[86] = iu2_debug_q[1]; // comp_invalidate + assign ierat_iu_debug_group2[87] = iu2_debug_q[9]; // any snoop + + assign ierat_iu_debug_group3[0] = ex3_eratsx_data_q[1]; // cam_hit delayed + assign ierat_iu_debug_group3[1] = iu2_debug_q[0]; // comp_request + assign ierat_iu_debug_group3[2] = iu2_debug_q[1]; // comp_invalidate + assign ierat_iu_debug_group3[3] = iu2_debug_q[9]; // any snoop + assign ierat_iu_debug_group3[4:8] = iu2_debug_q[11:15]; // '0' & cam_hit_entry + assign ierat_iu_debug_group3[9] = lru_update_event_q[7] | lru_update_event_q[8]; // any lru update event + assign ierat_iu_debug_group3[10:14] = lru_debug_q[0:4]; // lru update terms: tlb_reload, snoop, csync/isync, eratwe, fetch hit + assign ierat_iu_debug_group3[15:19] = {1'b0, watermark_q[0:3]}; + assign ierat_iu_debug_group3[20:35] = entry_valid_q[0:15]; + assign ierat_iu_debug_group3[36:51] = entry_match_q[0:15]; + assign ierat_iu_debug_group3[52:67] = {1'b0, lru_q[1:15]}; + assign ierat_iu_debug_group3[68:83] = {1'b0, lru_debug_q[5:19]}; // lru_eff(1 to 15) + assign ierat_iu_debug_group3[84:87] = lru_debug_q[20:23]; // lru_way_encode + + + // unused spare signal assignments + assign unused_dc[0] = mmucr1_q[2]; + assign unused_dc[1] = iu2_multihit_enab & (|(iu2_first_hit_entry)); + assign unused_dc[2] = ex6_ttype_q[2] & ex6_state_q[0]; + assign unused_dc[3] = |(tlb_rel_data_q[eratpos_rpnrsvd:eratpos_rpnrsvd + 3]); + assign unused_dc[4] = iu2_cam_cmp_data_q[56] | ex4_rd_cam_data_q[56]; + assign unused_dc[5] = |(attr_np2[0:5]); + assign unused_dc[6] = |(attr_np2[15:20]); + assign unused_dc[7] = |(cam_hit_entry); + assign unused_dc[8] = |(bcfg_q_b[0:15]); + assign unused_dc[9] = |(bcfg_q_b[16:31]); + assign unused_dc[10] = |(bcfg_q_b[32:47]); + assign unused_dc[11] = |(bcfg_q_b[48:51]); + assign unused_dc[12] = |(bcfg_q_b[52:61]); + assign unused_dc[13] = |(bcfg_q_b[62:77]); + assign unused_dc[14] = |(bcfg_q_b[78:81]); + assign unused_dc[15] = |(bcfg_q_b[82:86]); + assign unused_dc[16] = |(ex1_ra_entry_q); + assign unused_dc[17] = xu_iu_is_eratilx; + assign unused_dc[18] = 1'b0; + assign unused_dc[19] = pc_func_sl_thold_0_b | pc_func_sl_force; + assign unused_dc[20] = cam_mpw1_b[4] | cam_delay_lclkr[4]; + assign unused_dc[21] = 1'b0; + // bit 22 used elsewhere + assign unused_dc[23] = ex7_ttype_q[0]; + assign unused_dc[24] = ex7_ttype_q[2]; + assign unused_dc[25] = |(por_wr_array_data[51:67]); + assign unused_dc[26] = |(bcfg_q_b[87:102]); + assign unused_dc[27] = |(bcfg_q_b[103:106]); + assign unused_dc[28] = |(bcfg_q[107:122]); + assign unused_dc[29] = |(bcfg_q_b[107:122]); + + //--------------------------------------------------------------------- + // Latches + //--------------------------------------------------------------------- + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex1_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex1_valid_offset:ex1_valid_offset + `THREADS - 1]), + .scout(sov_0[ex1_valid_offset:ex1_valid_offset + `THREADS - 1]), + .din(ex1_valid_d[0:`THREADS - 1]), + .dout(ex1_valid_q[0:`THREADS - 1]) + ); + + tri_rlmreg_p #(.WIDTH(ttype_width), .INIT(0), .NEEDS_SRESET(1)) ex1_ttype_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex1_ttype_offset:ex1_ttype_offset + ttype_width - 1]), + .scout(sov_0[ex1_ttype_offset:ex1_ttype_offset + ttype_width - 1]), + .din(ex1_ttype_d), + .dout(ex1_ttype_q) + ); + + tri_rlmreg_p #(.WIDTH(ws_width), .INIT(0), .NEEDS_SRESET(1)) ex1_ws_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex1_ws_offset:ex1_ws_offset + ws_width - 1]), + .scout(sov_0[ex1_ws_offset:ex1_ws_offset + ws_width - 1]), + .din(ex1_ws_d[0:ws_width - 1]), + .dout(ex1_ws_q[0:ws_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(ra_entry_width), .INIT(0), .NEEDS_SRESET(1)) ex1_ra_entry_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex1_ra_entry_offset:ex1_ra_entry_offset + ra_entry_width - 1]), + .scout(sov_0[ex1_ra_entry_offset:ex1_ra_entry_offset + ra_entry_width - 1]), + .din(ex1_ra_entry_d[0:ra_entry_width - 1]), + .dout(ex1_ra_entry_q[0:ra_entry_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(state_width), .INIT(0), .NEEDS_SRESET(1)) ex1_state_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex1_state_offset:ex1_state_offset + state_width - 1]), + .scout(sov_0[ex1_state_offset:ex1_state_offset + state_width - 1]), + .din(ex1_state_d[0:state_width - 1]), + .dout(ex1_state_q[0:state_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(pid_width), .INIT(0), .NEEDS_SRESET(1)) ex1_pid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex1_pid_offset:ex1_pid_offset + pid_width - 1]), + .scout(sov_0[ex1_pid_offset:ex1_pid_offset + pid_width - 1]), + .din(ex1_pid_d), + .dout(ex1_pid_q) + ); + + tri_rlmreg_p #(.WIDTH(extclass_width), .INIT(0), .NEEDS_SRESET(1)) ex1_extclass_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex1_extclass_offset:ex1_extclass_offset + extclass_width - 1]), + .scout(sov_0[ex1_extclass_offset:ex1_extclass_offset + extclass_width - 1]), + .din(ex1_extclass_d[0:extclass_width - 1]), + .dout(ex1_extclass_q[0:extclass_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(tlbsel_width), .INIT(0), .NEEDS_SRESET(1)) ex1_tlbsel_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex1_tlbsel_offset:ex1_tlbsel_offset + tlbsel_width - 1]), + .scout(sov_0[ex1_tlbsel_offset:ex1_tlbsel_offset + tlbsel_width - 1]), + .din(ex1_tlbsel_d[0:tlbsel_width - 1]), + .dout(ex1_tlbsel_q[0:tlbsel_width - 1]) + ); + //----------------------------------------------------------------------------- + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex2_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex2_valid_offset:ex2_valid_offset + `THREADS - 1]), + .scout(sov_0[ex2_valid_offset:ex2_valid_offset + `THREADS - 1]), + .din(ex2_valid_d[0:`THREADS - 1]), + .dout(ex2_valid_q[0:`THREADS - 1]) + ); + + tri_rlmreg_p #(.WIDTH(ttype_width), .INIT(0), .NEEDS_SRESET(1)) ex2_ttype_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex2_ttype_offset:ex2_ttype_offset + ttype_width - 1]), + .scout(sov_0[ex2_ttype_offset:ex2_ttype_offset + ttype_width - 1]), + .din(ex2_ttype_d[0:ttype_width - 1]), + .dout(ex2_ttype_q[0:ttype_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(ws_width), .INIT(0), .NEEDS_SRESET(1)) ex2_ws_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex2_ws_offset:ex2_ws_offset + ws_width - 1]), + .scout(sov_0[ex2_ws_offset:ex2_ws_offset + ws_width - 1]), + .din(ex2_ws_d[0:ws_width - 1]), + .dout(ex2_ws_q[0:ws_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(ra_entry_width), .INIT(0), .NEEDS_SRESET(1)) ex2_ra_entry_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex2_ra_entry_offset:ex2_ra_entry_offset + ra_entry_width - 1]), + .scout(sov_0[ex2_ra_entry_offset:ex2_ra_entry_offset + ra_entry_width - 1]), + .din(ex2_ra_entry_d[0:ra_entry_width - 1]), + .dout(ex2_ra_entry_q[0:ra_entry_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(state_width), .INIT(0), .NEEDS_SRESET(1)) ex2_state_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex2_state_offset:ex2_state_offset + state_width - 1]), + .scout(sov_0[ex2_state_offset:ex2_state_offset + state_width - 1]), + .din(ex2_state_d[0:state_width - 1]), + .dout(ex2_state_q[0:state_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(pid_width), .INIT(0), .NEEDS_SRESET(1)) ex2_pid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex2_pid_offset:ex2_pid_offset + pid_width - 1]), + .scout(sov_0[ex2_pid_offset:ex2_pid_offset + pid_width - 1]), + .din(ex2_pid_d), + .dout(ex2_pid_q) + ); + + tri_rlmreg_p #(.WIDTH(extclass_width), .INIT(0), .NEEDS_SRESET(1)) ex2_extclass_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex2_extclass_offset:ex2_extclass_offset + extclass_width - 1]), + .scout(sov_0[ex2_extclass_offset:ex2_extclass_offset + extclass_width - 1]), + .din(ex2_extclass_d[0:extclass_width - 1]), + .dout(ex2_extclass_q[0:extclass_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(tlbsel_width), .INIT(0), .NEEDS_SRESET(1)) ex2_tlbsel_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex2_tlbsel_offset:ex2_tlbsel_offset + tlbsel_width - 1]), + .scout(sov_0[ex2_tlbsel_offset:ex2_tlbsel_offset + tlbsel_width - 1]), + .din(ex2_tlbsel_d[0:tlbsel_width - 1]), + .dout(ex2_tlbsel_q[0:tlbsel_width - 1]) + ); + + //----------------------------------------------------------------------------- + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex3_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex3_valid_offset:ex3_valid_offset + `THREADS - 1]), + .scout(sov_0[ex3_valid_offset:ex3_valid_offset + `THREADS - 1]), + .din(ex3_valid_d[0:`THREADS - 1]), + .dout(ex3_valid_q[0:`THREADS - 1]) + ); + + tri_rlmreg_p #(.WIDTH(ttype_width), .INIT(0), .NEEDS_SRESET(1)) ex3_ttype_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex3_ttype_offset:ex3_ttype_offset + ttype_width - 1]), + .scout(sov_0[ex3_ttype_offset:ex3_ttype_offset + ttype_width - 1]), + .din(ex3_ttype_d[0:ttype_width - 1]), + .dout(ex3_ttype_q[0:ttype_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(ws_width), .INIT(0), .NEEDS_SRESET(1)) ex3_ws_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex3_ws_offset:ex3_ws_offset + ws_width - 1]), + .scout(sov_0[ex3_ws_offset:ex3_ws_offset + ws_width - 1]), + .din(ex3_ws_d[0:ws_width - 1]), + .dout(ex3_ws_q[0:ws_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(ra_entry_width), .INIT(0), .NEEDS_SRESET(1)) ex3_ra_entry_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_grffence_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex3_ra_entry_offset:ex3_ra_entry_offset + ra_entry_width - 1]), + .scout(sov_0[ex3_ra_entry_offset:ex3_ra_entry_offset + ra_entry_width - 1]), + .din(ex3_ra_entry_d[0:ra_entry_width - 1]), + .dout(ex3_ra_entry_q[0:ra_entry_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(state_width), .INIT(0), .NEEDS_SRESET(1)) ex3_state_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex3_state_offset:ex3_state_offset + state_width - 1]), + .scout(sov_0[ex3_state_offset:ex3_state_offset + state_width - 1]), + .din(ex3_state_d[0:state_width - 1]), + .dout(ex3_state_q[0:state_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(pid_width), .INIT(0), .NEEDS_SRESET(1)) ex3_pid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex3_pid_offset:ex3_pid_offset + pid_width - 1]), + .scout(sov_0[ex3_pid_offset:ex3_pid_offset + pid_width - 1]), + .din(ex3_pid_d), + .dout(ex3_pid_q) + ); + + tri_rlmreg_p #(.WIDTH(extclass_width), .INIT(0), .NEEDS_SRESET(1)) ex3_extclass_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex3_extclass_offset:ex3_extclass_offset + extclass_width - 1]), + .scout(sov_0[ex3_extclass_offset:ex3_extclass_offset + extclass_width - 1]), + .din(ex3_extclass_d[0:extclass_width - 1]), + .dout(ex3_extclass_q[0:extclass_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(tlbsel_width), .INIT(0), .NEEDS_SRESET(1)) ex3_tlbsel_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex3_tlbsel_offset:ex3_tlbsel_offset + tlbsel_width - 1]), + .scout(sov_0[ex3_tlbsel_offset:ex3_tlbsel_offset + tlbsel_width - 1]), + .din(ex3_tlbsel_d[0:tlbsel_width - 1]), + .dout(ex3_tlbsel_q[0:tlbsel_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(2+num_entry_log2), .INIT(0), .NEEDS_SRESET(1)) ex3_eratsx_data_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(eratsx_data_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex3_eratsx_data_offset:ex3_eratsx_data_offset + (2+num_entry_log2) - 1]), + .scout(sov_0[ex3_eratsx_data_offset:ex3_eratsx_data_offset + (2+num_entry_log2) - 1]), + .din(ex3_eratsx_data_d[0:2 + num_entry_log2 - 1]), + .dout(ex3_eratsx_data_q[0:2 + num_entry_log2 - 1]) + ); + //----------------------------------------------------------------------------- + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex4_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex4_valid_offset:ex4_valid_offset + `THREADS - 1]), + .scout(sov_0[ex4_valid_offset:ex4_valid_offset + `THREADS - 1]), + .din(ex4_valid_d[0:`THREADS - 1]), + .dout(ex4_valid_q[0:`THREADS - 1]) + ); + + tri_rlmreg_p #(.WIDTH(ttype_width), .INIT(0), .NEEDS_SRESET(1)) ex4_ttype_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex4_ttype_offset:ex4_ttype_offset + ttype_width - 1]), + .scout(sov_0[ex4_ttype_offset:ex4_ttype_offset + ttype_width - 1]), + .din(ex4_ttype_d[0:ttype_width - 1]), + .dout(ex4_ttype_q[0:ttype_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(ws_width), .INIT(0), .NEEDS_SRESET(1)) ex4_ws_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex4_ws_offset:ex4_ws_offset + ws_width - 1]), + .scout(sov_0[ex4_ws_offset:ex4_ws_offset + ws_width - 1]), + .din(ex4_ws_d[0:ws_width - 1]), + .dout(ex4_ws_q[0:ws_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(ra_entry_width), .INIT(0), .NEEDS_SRESET(1)) ex4_ra_entry_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex4_ra_entry_offset:ex4_ra_entry_offset + ra_entry_width - 1]), + .scout(sov_0[ex4_ra_entry_offset:ex4_ra_entry_offset + ra_entry_width - 1]), + .din(ex4_ra_entry_d[0:ra_entry_width - 1]), + .dout(ex4_ra_entry_q[0:ra_entry_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(state_width), .INIT(0), .NEEDS_SRESET(1)) ex4_state_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_grffence_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex4_state_offset:ex4_state_offset + state_width - 1]), + .scout(sov_0[ex4_state_offset:ex4_state_offset + state_width - 1]), + .din(ex4_state_d[0:state_width - 1]), + .dout(ex4_state_q[0:state_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(pid_width), .INIT(0), .NEEDS_SRESET(1)) ex4_pid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_grffence_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex4_pid_offset:ex4_pid_offset + pid_width - 1]), + .scout(sov_0[ex4_pid_offset:ex4_pid_offset + pid_width - 1]), + .din(ex4_pid_d), + .dout(ex4_pid_q) + ); + + tri_rlmreg_p #(.WIDTH(extclass_width), .INIT(0), .NEEDS_SRESET(1)) ex4_extclass_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_grffence_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex4_extclass_offset:ex4_extclass_offset + extclass_width - 1]), + .scout(sov_0[ex4_extclass_offset:ex4_extclass_offset + extclass_width - 1]), + .din(ex4_extclass_d[0:extclass_width - 1]), + .dout(ex4_extclass_q[0:extclass_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(tlbsel_width), .INIT(0), .NEEDS_SRESET(1)) ex4_tlbsel_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex4_tlbsel_offset:ex4_tlbsel_offset + tlbsel_width - 1]), + .scout(sov_0[ex4_tlbsel_offset:ex4_tlbsel_offset + tlbsel_width - 1]), + .din(ex4_tlbsel_d[0:tlbsel_width - 1]), + .dout(ex4_tlbsel_q[0:tlbsel_width - 1]) + ); + //------------------------------------------------ + + tri_rlmreg_p #(.WIDTH(data_out_width), .INIT(0), .NEEDS_SRESET(1)) ex4_data_out_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_data_out_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex4_data_out_offset:ex4_data_out_offset + data_out_width - 1]), + .scout(sov_0[ex4_data_out_offset:ex4_data_out_offset + data_out_width - 1]), + .din(ex4_data_out_d[64 - data_out_width:63]), + .dout(ex4_data_out_q[64 - data_out_width:63]) + ); + //----------------------------------------------------------------------------- + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex5_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex5_valid_offset:ex5_valid_offset + `THREADS - 1]), + .scout(sov_0[ex5_valid_offset:ex5_valid_offset + `THREADS - 1]), + .din(ex5_valid_d[0:`THREADS - 1]), + .dout(ex5_valid_q[0:`THREADS - 1]) + ); + + tri_rlmreg_p #(.WIDTH(ttype_width), .INIT(0), .NEEDS_SRESET(1)) ex5_ttype_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex5_ttype_offset:ex5_ttype_offset + ttype_width - 1]), + .scout(sov_0[ex5_ttype_offset:ex5_ttype_offset + ttype_width - 1]), + .din(ex5_ttype_d[0:ttype_width - 1]), + .dout(ex5_ttype_q[0:ttype_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(ws_width), .INIT(0), .NEEDS_SRESET(1)) ex5_ws_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex5_ws_offset:ex5_ws_offset + ws_width - 1]), + .scout(sov_0[ex5_ws_offset:ex5_ws_offset + ws_width - 1]), + .din(ex5_ws_d[0:ws_width - 1]), + .dout(ex5_ws_q[0:ws_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(ra_entry_width), .INIT(0), .NEEDS_SRESET(1)) ex5_ra_entry_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex5_ra_entry_offset:ex5_ra_entry_offset + ra_entry_width - 1]), + .scout(sov_0[ex5_ra_entry_offset:ex5_ra_entry_offset + ra_entry_width - 1]), + .din(ex5_ra_entry_d[0:ra_entry_width - 1]), + .dout(ex5_ra_entry_q[0:ra_entry_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(state_width), .INIT(0), .NEEDS_SRESET(1)) ex5_state_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex5_state_offset:ex5_state_offset + state_width - 1]), + .scout(sov_0[ex5_state_offset:ex5_state_offset + state_width - 1]), + .din(ex5_state_d[0:state_width - 1]), + .dout(ex5_state_q[0:state_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(pid_width), .INIT(0), .NEEDS_SRESET(1)) ex5_pid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex5_pid_offset:ex5_pid_offset + pid_width - 1]), + .scout(sov_0[ex5_pid_offset:ex5_pid_offset + pid_width - 1]), + .din(ex5_pid_d), + .dout(ex5_pid_q) + ); + + tri_rlmreg_p #(.WIDTH(extclass_width), .INIT(0), .NEEDS_SRESET(1)) ex5_extclass_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex5_extclass_offset:ex5_extclass_offset + extclass_width - 1]), + .scout(sov_0[ex5_extclass_offset:ex5_extclass_offset + extclass_width - 1]), + .din(ex5_extclass_d[0:extclass_width - 1]), + .dout(ex5_extclass_q[0:extclass_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(tlbsel_width), .INIT(0), .NEEDS_SRESET(1)) ex5_tlbsel_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex5_tlbsel_offset:ex5_tlbsel_offset + tlbsel_width - 1]), + .scout(sov_0[ex5_tlbsel_offset:ex5_tlbsel_offset + tlbsel_width - 1]), + .din(ex5_tlbsel_d[0:tlbsel_width - 1]), + .dout(ex5_tlbsel_q[0:tlbsel_width - 1]) + ); + //------------------------------------------------ + + tri_rlmreg_p #(.WIDTH(rs_data_width), .INIT(0), .NEEDS_SRESET(1)) ex5_data_in_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex5_data_in_offset:ex5_data_in_offset + rs_data_width - 1]), + .scout(sov_0[ex5_data_in_offset:ex5_data_in_offset + rs_data_width - 1]), + .din(ex5_data_in_d[64 - rs_data_width:63]), + .dout(ex5_data_in_q[64 - rs_data_width:63]) + ); + //----------------------------------------------------------------------------- + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex6_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex6_valid_offset:ex6_valid_offset + `THREADS - 1]), + .scout(sov_0[ex6_valid_offset:ex6_valid_offset + `THREADS - 1]), + .din(ex6_valid_d[0:`THREADS - 1]), + .dout(ex6_valid_q[0:`THREADS - 1]) + ); + + tri_rlmreg_p #(.WIDTH(ttype_width), .INIT(0), .NEEDS_SRESET(1)) ex6_ttype_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex6_ttype_offset:ex6_ttype_offset + ttype_width - 1]), + .scout(sov_0[ex6_ttype_offset:ex6_ttype_offset + ttype_width - 1]), + .din(ex6_ttype_d[0:ttype_width - 1]), + .dout(ex6_ttype_q[0:ttype_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(ws_width), .INIT(0), .NEEDS_SRESET(1)) ex6_ws_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex6_ws_offset:ex6_ws_offset + ws_width - 1]), + .scout(sov_0[ex6_ws_offset:ex6_ws_offset + ws_width - 1]), + .din(ex6_ws_d[0:ws_width - 1]), + .dout(ex6_ws_q[0:ws_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(ra_entry_width), .INIT(0), .NEEDS_SRESET(1)) ex6_ra_entry_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex6_ra_entry_offset:ex6_ra_entry_offset + ra_entry_width - 1]), + .scout(sov_0[ex6_ra_entry_offset:ex6_ra_entry_offset + ra_entry_width - 1]), + .din(ex6_ra_entry_d[0:ra_entry_width - 1]), + .dout(ex6_ra_entry_q[0:ra_entry_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(state_width), .INIT(0), .NEEDS_SRESET(1)) ex6_state_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex6_state_offset:ex6_state_offset + state_width - 1]), + .scout(sov_0[ex6_state_offset:ex6_state_offset + state_width - 1]), + .din(ex6_state_d[0:state_width - 1]), + .dout(ex6_state_q[0:state_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(pid_width), .INIT(0), .NEEDS_SRESET(1)) ex6_pid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex6_pid_offset:ex6_pid_offset + pid_width - 1]), + .scout(sov_0[ex6_pid_offset:ex6_pid_offset + pid_width - 1]), + .din(ex6_pid_d), + .dout(ex6_pid_q) + ); + + tri_rlmreg_p #(.WIDTH(extclass_width), .INIT(0), .NEEDS_SRESET(1)) ex6_extclass_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex6_extclass_offset:ex6_extclass_offset + extclass_width - 1]), + .scout(sov_0[ex6_extclass_offset:ex6_extclass_offset + extclass_width - 1]), + .din(ex6_extclass_d[0:extclass_width - 1]), + .dout(ex6_extclass_q[0:extclass_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(tlbsel_width), .INIT(0), .NEEDS_SRESET(1)) ex6_tlbsel_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex6_tlbsel_offset:ex6_tlbsel_offset + tlbsel_width - 1]), + .scout(sov_0[ex6_tlbsel_offset:ex6_tlbsel_offset + tlbsel_width - 1]), + .din(ex6_tlbsel_d[0:tlbsel_width - 1]), + .dout(ex6_tlbsel_q[0:tlbsel_width - 1]) + ); + + //------------------------------------------------ + + tri_rlmreg_p #(.WIDTH(rs_data_width), .INIT(0), .NEEDS_SRESET(1)) ex6_data_in_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex6_data_in_offset:ex6_data_in_offset + rs_data_width - 1]), + .scout(sov_0[ex6_data_in_offset:ex6_data_in_offset + rs_data_width - 1]), + .din(ex6_data_in_d[64 - rs_data_width:63]), + .dout(ex6_data_in_q[64 - rs_data_width:63]) + ); + + //------------------------------------------------ + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex7_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex7_valid_offset:ex7_valid_offset + `THREADS - 1]), + .scout(sov_1[ex7_valid_offset:ex7_valid_offset + `THREADS - 1]), + .din(ex7_valid_d[0:`THREADS - 1]), + .dout(ex7_valid_q[0:`THREADS - 1]) + ); + + tri_rlmreg_p #(.WIDTH(ttype_width), .INIT(0), .NEEDS_SRESET(1)) ex7_ttype_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex7_ttype_offset:ex7_ttype_offset + ttype_width - 1]), + .scout(sov_1[ex7_ttype_offset:ex7_ttype_offset + ttype_width - 1]), + .din(ex7_ttype_d[0:ttype_width - 1]), + .dout(ex7_ttype_q[0:ttype_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(tlbsel_width), .INIT(0), .NEEDS_SRESET(1)) ex7_tlbsel_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex6_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex7_tlbsel_offset:ex7_tlbsel_offset + tlbsel_width - 1]), + .scout(sov_1[ex7_tlbsel_offset:ex7_tlbsel_offset + tlbsel_width - 1]), + .din(ex7_tlbsel_d[0:tlbsel_width - 1]), + .dout(ex7_tlbsel_q[0:tlbsel_width - 1]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu1_flush_enab_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[iu1_flush_enab_offset]), + .scout(sov_0[iu1_flush_enab_offset]), + .din(iu1_flush_enab_d), + .dout(iu1_flush_enab_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) iu2_n_flush_req_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu1_or_iu2_grffence_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[iu2_n_flush_req_offset:iu2_n_flush_req_offset + `THREADS - 1]), + .scout(sov_0[iu2_n_flush_req_offset:iu2_n_flush_req_offset + `THREADS - 1]), + .din(iu2_n_flush_req_d[0:`THREADS - 1]), + .dout(iu2_n_flush_req_q[0:`THREADS - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(1), .NEEDS_SRESET(1)) hold_req_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(not_grffence_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[hold_req_offset:hold_req_offset + `THREADS - 1]), + .scout(sov_0[hold_req_offset:hold_req_offset + `THREADS - 1]), + .din(hold_req_d[0:`THREADS - 1]), + .dout(hold_req_q[0:`THREADS - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) tlb_miss_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_miss_offset:tlb_miss_offset + `THREADS - 1]), + .scout(sov_0[tlb_miss_offset:tlb_miss_offset + `THREADS - 1]), + .din(tlb_miss_d[0:`THREADS - 1]), + .dout(tlb_miss_q[0:`THREADS - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) tlb_flushed_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_flushed_offset:tlb_flushed_offset + `THREADS - 1]), + .scout(sov_0[tlb_flushed_offset:tlb_flushed_offset + `THREADS - 1]), + .din(tlb_flushed_d[0:`THREADS - 1]), + .dout(tlb_flushed_q[0:`THREADS - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) tlb_req_inprogress_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_req_inprogress_offset:tlb_req_inprogress_offset + `THREADS - 1]), + .scout(sov_0[tlb_req_inprogress_offset:tlb_req_inprogress_offset + `THREADS - 1]), + .din(tlb_req_inprogress_d[0:`THREADS - 1]), + .dout(tlb_req_inprogress_q[0:`THREADS - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) iu1_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[iu1_valid_offset:iu1_valid_offset + `THREADS - 1]), + .scout(sov_0[iu1_valid_offset:iu1_valid_offset + `THREADS - 1]), + .din(iu1_valid_d[0:`THREADS - 1]), + .dout(iu1_valid_q[0:`THREADS - 1]) + ); + + tri_rlmreg_p #(.WIDTH(state_width), .INIT(0), .NEEDS_SRESET(1)) iu1_state_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[iu1_state_offset:iu1_state_offset + state_width - 1]), + .scout(sov_0[iu1_state_offset:iu1_state_offset + state_width - 1]), + .din(iu1_state_d[0:state_width - 1]), + .dout(iu1_state_q[0:state_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(pid_width), .INIT(0), .NEEDS_SRESET(1)) iu1_pid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[iu1_pid_offset:iu1_pid_offset + pid_width - 1]), + .scout(sov_0[iu1_pid_offset:iu1_pid_offset + pid_width - 1]), + .din(iu1_pid_d), + .dout(iu1_pid_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu1_nonspec_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[iu1_nonspec_offset]), + .scout(sov_0[iu1_nonspec_offset]), + .din(iu1_nonspec_d), + .dout(iu1_nonspec_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu1_prefetch_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[iu1_prefetch_offset]), + .scout(sov_0[iu1_prefetch_offset]), + .din(iu1_prefetch_d), + .dout(iu1_prefetch_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) iu2_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[iu2_valid_offset:iu2_valid_offset + `THREADS - 1]), + .scout(sov_0[iu2_valid_offset:iu2_valid_offset + `THREADS - 1]), + .din(iu2_valid_d[0:`THREADS - 1]), + .dout(iu2_valid_q[0:`THREADS - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) iu2_perf_itlb_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[iu2_perf_itlb_offset:iu2_perf_itlb_offset + `THREADS - 1]), + .scout(sov_0[iu2_perf_itlb_offset:iu2_perf_itlb_offset + `THREADS - 1]), + .din(iu2_perf_itlb_d[0:`THREADS - 1]), + .dout(iu2_perf_itlb_q[0:`THREADS - 1]) + ); + + tri_rlmreg_p #(.WIDTH(state_width), .INIT(0), .NEEDS_SRESET(1)) iu2_state_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu1_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[iu2_state_offset:iu2_state_offset + state_width - 1]), + .scout(sov_0[iu2_state_offset:iu2_state_offset + state_width - 1]), + .din(iu2_state_d[0:state_width - 1]), + .dout(iu2_state_q[0:state_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(pid_width), .INIT(0), .NEEDS_SRESET(1)) iu2_pid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu1_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[iu2_pid_offset:iu2_pid_offset + pid_width - 1]), + .scout(sov_0[iu2_pid_offset:iu2_pid_offset + pid_width - 1]), + .din(iu2_pid_d), + .dout(iu2_pid_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu2_nonspec_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[iu2_nonspec_offset]), + .scout(sov_0[iu2_nonspec_offset]), + .din(iu2_nonspec_d), + .dout(iu2_nonspec_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu2_prefetch_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[iu2_prefetch_offset]), + .scout(sov_0[iu2_prefetch_offset]), + .din(iu2_prefetch_d), + .dout(iu2_prefetch_q) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) iu2_miss_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu1_or_iu2_grffence_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[iu2_miss_offset:iu2_miss_offset + 2 - 1]), + .scout(sov_0[iu2_miss_offset:iu2_miss_offset + 2 - 1]), + .din(iu2_miss_d), + .dout(iu2_miss_q) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) iu2_multihit_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu1_or_iu2_grffence_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[iu2_multihit_offset:iu2_multihit_offset + 2 - 1]), + .scout(sov_0[iu2_multihit_offset:iu2_multihit_offset + 2 - 1]), + .din(iu2_multihit_d), + .dout(iu2_multihit_q) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) iu2_parerr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu1_or_iu2_grffence_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[iu2_parerr_offset:iu2_parerr_offset + 2 - 1]), + .scout(sov_0[iu2_parerr_offset:iu2_parerr_offset + 2 - 1]), + .din(iu2_parerr_d), + .dout(iu2_parerr_q) + ); + + tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) iu2_isi_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(not_grffence_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[iu2_isi_offset:iu2_isi_offset + 6 - 1]), + .scout(sov_0[iu2_isi_offset:iu2_isi_offset + 6 - 1]), + .din(iu2_isi_d), + .dout(iu2_isi_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu2_tlbreq_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(notlb_grffence_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[iu2_tlbreq_offset]), + .scout(sov_0[iu2_tlbreq_offset]), + .din(iu2_tlbreq_d), + .dout(iu2_tlbreq_q) + ); + + tri_rlmreg_p #(.WIDTH(num_entry), .INIT(0), .NEEDS_SRESET(1)) iu2_multihit_b_pt_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu1_grffence_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[iu2_multihit_b_pt_offset:iu2_multihit_b_pt_offset + num_entry - 1]), + .scout(sov_0[iu2_multihit_b_pt_offset:iu2_multihit_b_pt_offset + num_entry - 1]), + .din(iu2_multihit_b_pt_d), + .dout(iu2_multihit_b_pt_q) + ); + + tri_rlmreg_p #(.WIDTH(num_entry-1), .INIT(0), .NEEDS_SRESET(1)) iu2_first_hit_entry_pt_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu1_grffence_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[iu2_first_hit_entry_pt_offset:iu2_first_hit_entry_pt_offset + (num_entry-1) - 1]), + .scout(sov_0[iu2_first_hit_entry_pt_offset:iu2_first_hit_entry_pt_offset + (num_entry-1) - 1]), + .din(iu2_first_hit_entry_pt_d), + .dout(iu2_first_hit_entry_pt_q) + ); + + tri_rlmreg_p #(.WIDTH(cam_data_width), .INIT(0), .NEEDS_SRESET(1)) iu2_cam_cmp_data_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu1_cmp_data_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[iu2_cam_cmp_data_offset:iu2_cam_cmp_data_offset + cam_data_width - 1]), + .scout(sov_0[iu2_cam_cmp_data_offset:iu2_cam_cmp_data_offset + cam_data_width - 1]), + .din(iu2_cam_cmp_data_d[0:cam_data_width - 1]), + .dout(iu2_cam_cmp_data_q[0:cam_data_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(array_data_width), .INIT(0), .NEEDS_SRESET(1)) iu2_array_cmp_data_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu1_cmp_data_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[iu2_array_cmp_data_offset:iu2_array_cmp_data_offset + array_data_width - 1]), + .scout(sov_0[iu2_array_cmp_data_offset:iu2_array_cmp_data_offset + array_data_width - 1]), + .din(iu2_array_cmp_data_d[0:array_data_width - 1]), + .dout(iu2_array_cmp_data_q[0:array_data_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(cam_data_width), .INIT(0), .NEEDS_SRESET(1)) ex4_rd_cam_data_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_rd_data_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex4_rd_cam_data_offset:ex4_rd_cam_data_offset + cam_data_width - 1]), + .scout(sov_0[ex4_rd_cam_data_offset:ex4_rd_cam_data_offset + cam_data_width - 1]), + .din(ex4_rd_cam_data_d[0:cam_data_width - 1]), + .dout(ex4_rd_cam_data_q[0:cam_data_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(array_data_width), .INIT(0), .NEEDS_SRESET(1)) ex4_rd_array_data_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_rd_data_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex4_rd_array_data_offset:ex4_rd_array_data_offset + array_data_width - 1]), + .scout(sov_0[ex4_rd_array_data_offset:ex4_rd_array_data_offset + array_data_width - 1]), + .din(ex4_rd_array_data_d[0:array_data_width - 1]), + .dout(ex4_rd_array_data_q[0:array_data_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS+1), .INIT(0), .NEEDS_SRESET(1)) ex3_parerr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(not_grffence_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex3_parerr_offset:ex3_parerr_offset + (`THREADS+1) - 1]), + .scout(sov_0[ex3_parerr_offset:ex3_parerr_offset + (`THREADS+1) - 1]), + .din(ex3_parerr_d), + .dout(ex3_parerr_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS+3), .INIT(0), .NEEDS_SRESET(1)) ex4_parerr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex4_parerr_offset:ex4_parerr_offset + (`THREADS+3) - 1]), + .scout(sov_0[ex4_parerr_offset:ex4_parerr_offset + (`THREADS+3) - 1]), + .din(ex4_parerr_d), + .dout(ex4_parerr_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS+num_entry_log2), .INIT(0), .NEEDS_SRESET(1)) ex4_ieen_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex4_ieen_offset:ex4_ieen_offset + `THREADS+num_entry_log2 - 1]), + .scout(sov_0[ex4_ieen_offset:ex4_ieen_offset + `THREADS+num_entry_log2 - 1]), + .din(ex4_ieen_d[0:`THREADS+num_entry_log2 - 1]), + .dout(ex4_ieen_q[0:`THREADS+num_entry_log2 - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS+num_entry_log2), .INIT(0), .NEEDS_SRESET(1)) ex5_ieen_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex5_ieen_offset:ex5_ieen_offset + `THREADS+num_entry_log2 - 1]), + .scout(sov_0[ex5_ieen_offset:ex5_ieen_offset + `THREADS+num_entry_log2 - 1]), + .din(ex5_ieen_d[0:`THREADS+num_entry_log2 - 1]), + .dout(ex5_ieen_q[0:`THREADS+num_entry_log2 - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS+num_entry_log2), .INIT(0), .NEEDS_SRESET(1)) ex6_ieen_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex6_ieen_offset:ex6_ieen_offset + `THREADS+num_entry_log2 - 1]), + .scout(sov_0[ex6_ieen_offset:ex6_ieen_offset + `THREADS+num_entry_log2 - 1]), + .din(ex6_ieen_d[0:`THREADS+num_entry_log2 - 1]), + .dout(ex6_ieen_q[0:`THREADS+num_entry_log2 - 1]) + ); + + tri_rlmreg_p #(.WIDTH(9), .INIT(0), .NEEDS_SRESET(1)) mmucr1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[mmucr1_offset:mmucr1_offset + 9 - 1]), + .scout(sov_0[mmucr1_offset:mmucr1_offset + 9 - 1]), + .din(mmucr1_d), + .dout(mmucr1_q) + ); + + generate + begin : xhdl4 + genvar tid; + for (tid = 0; tid <= `THREADS - 1; tid = tid + 1) + begin : rpn_holdreg + tri_rlmreg_p #(.WIDTH(64), .INIT(0), .NEEDS_SRESET(1)) rpn_holdreg_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex6_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[rpn_holdreg_offset + (64 * tid):rpn_holdreg_offset + (64 * (tid + 1)) - 1]), + .scout(sov_0[rpn_holdreg_offset + (64 * tid):rpn_holdreg_offset + (64 * (tid + 1)) - 1]), + .din(rpn_holdreg_d[tid][0:63]), + .dout(rpn_holdreg_q[tid][0:63]) + ); + end + end + endgenerate + + tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) entry_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(entry_valid_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[entry_valid_offset:entry_valid_offset + 16 - 1]), + .scout(sov_0[entry_valid_offset:entry_valid_offset + 16 - 1]), + .din(entry_valid), + .dout(entry_valid_q) + ); + + tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) entry_match_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(entry_match_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[entry_match_offset:entry_match_offset + 16 - 1]), + .scout(sov_0[entry_match_offset:entry_match_offset + 16 - 1]), + .din(entry_match), + .dout(entry_match_q) + ); + + tri_rlmreg_p #(.WIDTH(watermark_width), .INIT(13), .NEEDS_SRESET(1)) watermark_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex6_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[watermark_offset:watermark_offset + watermark_width - 1]), + .scout(sov_0[watermark_offset:watermark_offset + watermark_width - 1]), + .din(watermark_d[0:watermark_width - 1]), + .dout(watermark_q[0:watermark_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(eptr_width), .INIT(0), .NEEDS_SRESET(1)) eptr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mmucr1_q[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[eptr_offset:eptr_offset + eptr_width - 1]), + .scout(sov_0[eptr_offset:eptr_offset + eptr_width - 1]), + .din(eptr_d[0:eptr_width - 1]), + .dout(eptr_q[0:eptr_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(lru_width), .INIT(0), .NEEDS_SRESET(1)) lru_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lru_update_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[lru_offset:lru_offset + lru_width - 1]), + .scout(sov_0[lru_offset:lru_offset + lru_width - 1]), + .din(lru_d[1:lru_width]), + .dout(lru_q[1:lru_width]) + ); + + tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) lru_update_event_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(not_grffence_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[lru_update_event_offset:lru_update_event_offset + 10 - 1]), + .scout(sov_0[lru_update_event_offset:lru_update_event_offset + 10 - 1]), + .din(lru_update_event_d), + .dout(lru_update_event_q) + ); + + tri_rlmreg_p #(.WIDTH(24), .INIT(0), .NEEDS_SRESET(1)) lru_debug_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(debug_grffence_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[lru_debug_offset:lru_debug_offset + 24 - 1]), + .scout(sov_0[lru_debug_offset:lru_debug_offset + 24 - 1]), + .din(lru_debug_d), + .dout(lru_debug_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_xu_ord_write_done_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[iu_xu_ord_write_done_offset]), + .scout(sov_0[iu_xu_ord_write_done_offset]), + .din(iu_xu_ord_write_done_d), + .dout(iu_xu_ord_write_done_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_xu_ord_read_done_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[iu_xu_ord_read_done_offset]), + .scout(sov_0[iu_xu_ord_read_done_offset]), + .din(iu_xu_ord_read_done_d), + .dout(iu_xu_ord_read_done_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_xu_ord_par_err_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[iu_xu_ord_par_err_offset]), + .scout(sov_0[iu_xu_ord_par_err_offset]), + .din(iu_xu_ord_par_err_d), + .dout(iu_xu_ord_par_err_q) + ); + + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) cp_ic_csinv_comp_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[cp_ic_csinv_comp_offset:cp_ic_csinv_comp_offset + 4 - 1]), + .scout(sov_0[cp_ic_csinv_comp_offset:cp_ic_csinv_comp_offset + 4 - 1]), + .din(cp_ic_csinv_comp_d), + .dout(cp_ic_csinv_comp_q) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) snoop_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), // keep this as tiup, bit(1) is I$ backinv + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[snoop_val_offset:snoop_val_offset + 3 - 1]), + .scout(sov_1[snoop_val_offset:snoop_val_offset + 3 - 1]), + .din(snoop_val_d), + .dout(snoop_val_q) + ); + + tri_rlmreg_p #(.WIDTH(26), .INIT(0), .NEEDS_SRESET(1)) snoop_attr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(snoop_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[snoop_attr_offset:snoop_attr_offset + 26 - 1]), + .scout(sov_1[snoop_attr_offset:snoop_attr_offset + 26 - 1]), + .din(snoop_attr_d), + .dout(snoop_attr_q) + ); + + tri_rlmreg_p #(.WIDTH(epn_width), .INIT(0), .NEEDS_SRESET(1)) snoop_addr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(snoop_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[snoop_addr_offset:snoop_addr_offset + epn_width - 1]), + .scout(sov_1[snoop_addr_offset:snoop_addr_offset + epn_width - 1]), + .din(snoop_addr_d[52 - epn_width:51]), + .dout(snoop_addr_q[52 - epn_width:51]) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) por_seq_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[por_seq_offset:por_seq_offset + 3 - 1]), + .scout(sov_1[por_seq_offset:por_seq_offset + 3 - 1]), + .din(por_seq_d[0:por_seq_width - 1]), + .dout(por_seq_q[0:por_seq_width - 1]) + ); + + // timing latches for reloads + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) tlb_rel_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[tlb_rel_val_offset:tlb_rel_val_offset + 5 - 1]), + .scout(sov_1[tlb_rel_val_offset:tlb_rel_val_offset + 5 - 1]), + .din(tlb_rel_val_d), + .dout(tlb_rel_val_q) + ); + + tri_rlmreg_p #(.WIDTH(132), .INIT(0), .NEEDS_SRESET(1)) tlb_rel_data_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_rel_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[tlb_rel_data_offset:tlb_rel_data_offset + 132 - 1]), + .scout(sov_1[tlb_rel_data_offset:tlb_rel_data_offset + 132 - 1]), + .din(tlb_rel_data_d), + .dout(tlb_rel_data_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) iu_mm_ierat_flush_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[iu_mm_ierat_flush_offset:iu_mm_ierat_flush_offset + `THREADS - 1]), + .scout(sov_1[iu_mm_ierat_flush_offset:iu_mm_ierat_flush_offset + `THREADS - 1]), + .din(iu_mm_ierat_flush_d[0:`THREADS - 1]), + .dout(iu_mm_ierat_flush_q[0:`THREADS - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) iu_xu_ierat_ex2_flush_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[iu_xu_ierat_ex2_flush_offset:iu_xu_ierat_ex2_flush_offset + `THREADS - 1]), + .scout(sov_1[iu_xu_ierat_ex2_flush_offset:iu_xu_ierat_ex2_flush_offset + `THREADS - 1]), + .din(iu_xu_ierat_ex2_flush_d[0:`THREADS - 1]), + .dout(iu_xu_ierat_ex2_flush_q[0:`THREADS - 1]) + ); + + tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) ccr2_frat_paranoia_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ccr2_frat_paranoia_offset:ccr2_frat_paranoia_offset + 10 - 1]), + .scout(sov_1[ccr2_frat_paranoia_offset:ccr2_frat_paranoia_offset + 10 - 1]), + .din(ccr2_frat_paranoia_d), + .dout(ccr2_frat_paranoia_q) + ); + + tri_rlmlatch_p #(.INIT(1), .NEEDS_SRESET(1)) ccr2_notlb_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ccr2_notlb_offset]), + .scout(sov_1[ccr2_notlb_offset]), + .din(xu_iu_hid_mmu_mode), + .dout(ccr2_notlb_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) mchk_flash_inv_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu2_or_iu3_grffence_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mchk_flash_inv_offset:mchk_flash_inv_offset + 4 - 1]), + .scout(sov_1[mchk_flash_inv_offset:mchk_flash_inv_offset + 4 - 1]), + .din(mchk_flash_inv_d), + .dout(mchk_flash_inv_q) + ); + + tri_rlmlatch_p #(.INIT(1), .NEEDS_SRESET(1)) xucr4_mmu_mchk_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[xucr4_mmu_mchk_offset]), + .scout(sov_1[xucr4_mmu_mchk_offset]), + .din(xu_iu_xucr4_mmu_mchk), + .dout(xucr4_mmu_mchk_q) + ); + + tri_rlmreg_p #(.WIDTH(11), .INIT(0), .NEEDS_SRESET(1)) iu1_debug_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(trace_bus_enable_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[iu1_debug_offset:iu1_debug_offset + 11 - 1]), + .scout(sov_1[iu1_debug_offset:iu1_debug_offset + 11 - 1]), + .din(iu1_debug_d), + .dout(iu1_debug_q) + ); + + tri_rlmreg_p #(.WIDTH(17), .INIT(0), .NEEDS_SRESET(1)) iu2_debug_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(debug_grffence_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[iu2_debug_offset:iu2_debug_offset + 17 - 1]), + .scout(sov_1[iu2_debug_offset:iu2_debug_offset + 17 - 1]), + .din(iu2_debug_d), + .dout(iu2_debug_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu1_stg_act_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[iu1_stg_act_offset]), + .scout(sov_1[iu1_stg_act_offset]), + .din(iu1_stg_act_d), + .dout(iu1_stg_act_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu2_stg_act_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[iu2_stg_act_offset]), + .scout(sov_1[iu2_stg_act_offset]), + .din(iu2_stg_act_d), + .dout(iu2_stg_act_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu3_stg_act_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[iu3_stg_act_offset]), + .scout(sov_1[iu3_stg_act_offset]), + .din(iu3_stg_act_d), + .dout(iu3_stg_act_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_stg_act_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex1_stg_act_offset]), + .scout(sov_1[ex1_stg_act_offset]), + .din(ex1_stg_act_d), + .dout(ex1_stg_act_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_stg_act_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex2_stg_act_offset]), + .scout(sov_1[ex2_stg_act_offset]), + .din(ex2_stg_act_d), + .dout(ex2_stg_act_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_stg_act_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex3_stg_act_offset]), + .scout(sov_1[ex3_stg_act_offset]), + .din(ex3_stg_act_d), + .dout(ex3_stg_act_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_stg_act_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex4_stg_act_offset]), + .scout(sov_1[ex4_stg_act_offset]), + .din(ex4_stg_act_d), + .dout(ex4_stg_act_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_stg_act_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex5_stg_act_offset]), + .scout(sov_1[ex5_stg_act_offset]), + .din(ex5_stg_act_d), + .dout(ex5_stg_act_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_stg_act_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex6_stg_act_offset]), + .scout(sov_1[ex6_stg_act_offset]), + .din(ex6_stg_act_d), + .dout(ex6_stg_act_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex7_stg_act_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex7_stg_act_offset]), + .scout(sov_1[ex7_stg_act_offset]), + .din(ex7_stg_act_d), + .dout(ex7_stg_act_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_rel_act_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[tlb_rel_act_offset]), + .scout(sov_1[tlb_rel_act_offset]), + .din(tlb_rel_act_d), + .dout(tlb_rel_act_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) snoop_act_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[snoop_act_offset]), + .scout(sov_1[snoop_act_offset]), + .din(mm_iu_ierat_snoop_coming), + .dout(snoop_act_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_pc_err_ierat_multihit_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[iu_pc_err_ierat_multihit_offset]), + .scout(sov_1[iu_pc_err_ierat_multihit_offset]), + .din(iu_pc_err_ierat_multihit_d), + .dout(iu_pc_err_ierat_multihit_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_pc_err_ierat_parity_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[iu_pc_err_ierat_parity_offset]), + .scout(sov_1[iu_pc_err_ierat_parity_offset]), + .din(iu_pc_err_ierat_parity_d), + .dout(iu_pc_err_ierat_parity_q) + ); + // for debug trace bus latch act + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) trace_bus_enable_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[trace_bus_enable_offset]), + .scout(sov_1[trace_bus_enable_offset]), + .din(pc_iu_trace_bus_enable), + .dout(trace_bus_enable_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) an_ac_grffence_en_dc_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[an_ac_grffence_en_dc_offset]), + .scout(sov_1[an_ac_grffence_en_dc_offset]), + .din(an_ac_grffence_en_dc_q), + .dout(an_ac_grffence_en_dc_q) + ); + + tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) spare_a_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spare_a_offset:spare_a_offset + 15]), + .scout(sov_1[spare_a_offset:spare_a_offset + 15]), + .din(spare_q[0:15]), + .dout(spare_q[0:15]) + ); + + tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) spare_b_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spare_b_offset:spare_b_offset + 15]), + .scout(sov_1[spare_b_offset:spare_b_offset + 15]), + .din(spare_q[16:31]), + .dout(spare_q[16:31]) + ); + + + //------------------------------------------------ + // scan only latches for boot config + //------------------------------------------------ + + // epn rpn u0:3 E + // 0 31 32 51 52 54 61 62 81 86 + // 0 31 32 51 22 24 31 32 51 + //init => "0000_0000_0000_0000_0000_0000_0000_0000_1111_1111_1111_1111_1111_11_1111_1111_1111_1111_1111_1111_1111_0000_0", + + tri_slat_scan #(.WIDTH(16), .INIT(`IERAT_BCFG_EPN_0TO15), .RESET_INVERTS_SCAN(1'b1)) bcfg_epn_0to15_latch( + .vd(vdd), + .gd(gnd), + .dclk(lcb_dclk), + .lclk(lcb_lclk), + .scan_in(bsiv[bcfg_offset:bcfg_offset + 15]), + .scan_out(bsov[bcfg_offset:bcfg_offset + 15]), + .q(bcfg_q[0:15]), + .q_b(bcfg_q_b[0:15]) + ); + + tri_slat_scan #(.WIDTH(16), .INIT(`IERAT_BCFG_EPN_16TO31), .RESET_INVERTS_SCAN(1'b1)) bcfg_epn_16to31_latch( + .vd(vdd), + .gd(gnd), + .dclk(lcb_dclk), + .lclk(lcb_lclk), + .scan_in(bsiv[bcfg_offset + 16:bcfg_offset + 31]), + .scan_out(bsov[bcfg_offset + 16:bcfg_offset + 31]), + .q(bcfg_q[16:31]), + .q_b(bcfg_q_b[16:31]) + ); + + tri_slat_scan #(.WIDTH(16), .INIT(`IERAT_BCFG_EPN_32TO47), .RESET_INVERTS_SCAN(1'b1)) bcfg_epn_32to47_latch( + .vd(vdd), + .gd(gnd), + .dclk(lcb_dclk), + .lclk(lcb_lclk), + .scan_in(bsiv[bcfg_offset + 32:bcfg_offset + 47]), + .scan_out(bsov[bcfg_offset + 32:bcfg_offset + 47]), + .q(bcfg_q[32:47]), + .q_b(bcfg_q_b[32:47]) + ); + + tri_slat_scan #(.WIDTH(4), .INIT(`IERAT_BCFG_EPN_48TO51), .RESET_INVERTS_SCAN(1'b1)) bcfg_epn_48to51_latch( + .vd(vdd), + .gd(gnd), + .dclk(lcb_dclk), + .lclk(lcb_lclk), + .scan_in(bsiv[bcfg_offset + 48:bcfg_offset + 51]), + .scan_out(bsov[bcfg_offset + 48:bcfg_offset + 51]), + .q(bcfg_q[48:51]), + .q_b(bcfg_q_b[48:51]) + ); + + tri_slat_scan #(.WIDTH(10), .INIT(`IERAT_BCFG_RPN_22TO31), .RESET_INVERTS_SCAN(1'b1)) bcfg_rpn_22to31_latch( + .vd(vdd), + .gd(gnd), + .dclk(lcb_dclk), + .lclk(lcb_lclk), + .scan_in(bsiv[bcfg_offset + 52:bcfg_offset + 61]), + .scan_out(bsov[bcfg_offset + 52:bcfg_offset + 61]), + .q(bcfg_q[52:61]), + .q_b(bcfg_q_b[52:61]) + ); + + tri_slat_scan #(.WIDTH(16), .INIT(`IERAT_BCFG_RPN_32TO47), .RESET_INVERTS_SCAN(1'b1)) bcfg_rpn_32to47_latch( + .vd(vdd), + .gd(gnd), + .dclk(lcb_dclk), + .lclk(lcb_lclk), + .scan_in(bsiv[bcfg_offset + 62:bcfg_offset + 77]), + .scan_out(bsov[bcfg_offset + 62:bcfg_offset + 77]), + .q(bcfg_q[62:77]), + .q_b(bcfg_q_b[62:77]) + ); + + tri_slat_scan #(.WIDTH(4), .INIT(`IERAT_BCFG_RPN_48TO51), .RESET_INVERTS_SCAN(1'b1)) bcfg_rpn_48to51_latch( + .vd(vdd), + .gd(gnd), + .dclk(lcb_dclk), + .lclk(lcb_lclk), + .scan_in(bsiv[bcfg_offset + 78:bcfg_offset + 81]), + .scan_out(bsov[bcfg_offset + 78:bcfg_offset + 81]), + .q(bcfg_q[78:81]), + .q_b(bcfg_q_b[78:81]) + ); + + tri_slat_scan #(.WIDTH(5), .INIT(`IERAT_BCFG_ATTR), .RESET_INVERTS_SCAN(1'b1)) bcfg_attr_latch( + .vd(vdd), + .gd(gnd), + .dclk(lcb_dclk), + .lclk(lcb_lclk), + .scan_in(bsiv[bcfg_offset + 82:bcfg_offset + 86]), + .scan_out(bsov[bcfg_offset + 82:bcfg_offset + 86]), + .q(bcfg_q[82:86]), + .q_b(bcfg_q_b[82:86]) + ); + + tri_slat_scan #(.WIDTH(16), .INIT(`IERAT_BCFG_RPN2_32TO47), .RESET_INVERTS_SCAN(1'b1)) bcfg_rpn2_32to47_latch( + .vd(vdd), + .gd(gnd), + .dclk(lcb_dclk), + .lclk(lcb_lclk), + .scan_in(bsiv[bcfg_offset + 87:bcfg_offset + 102]), + .scan_out(bsov[bcfg_offset + 87:bcfg_offset + 102]), + .q(bcfg_q[87:102]), + .q_b(bcfg_q_b[87:102]) + ); + + tri_slat_scan #(.WIDTH(4), .INIT(`IERAT_BCFG_RPN2_48TO51), .RESET_INVERTS_SCAN(1'b1)) bcfg_rpn2_48to51_latch( + .vd(vdd), + .gd(gnd), + .dclk(lcb_dclk), + .lclk(lcb_lclk), + .scan_in(bsiv[bcfg_offset + 103:bcfg_offset + 106]), + .scan_out(bsov[bcfg_offset + 103:bcfg_offset + 106]), + .q(bcfg_q[103:106]), + .q_b(bcfg_q_b[103:106]) + ); + + tri_slat_scan #(.WIDTH(16), .INIT(0), .RESET_INVERTS_SCAN(1'b1)) bcfg_spare_latch( + .vd(vdd), + .gd(gnd), + .dclk(lcb_dclk), + .lclk(lcb_lclk), + .scan_in(bsiv[bcfg_offset + 107:bcfg_offset + 122]), + .scan_out(bsov[bcfg_offset + 107:bcfg_offset + 122]), + .q(bcfg_q[107:122]), + .q_b(bcfg_q_b[107:122]) + ); + + //------------------------------------------------ + // thold/sg latches + //------------------------------------------------ + + tri_plat #(.WIDTH(4)) perv_2to1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ccflush_dc), + .din({pc_iu_func_sl_thold_2, + pc_iu_func_slp_sl_thold_2, + pc_iu_cfg_slp_sl_thold_2, + pc_iu_sg_2}), + .q({pc_func_sl_thold_1, + pc_func_slp_sl_thold_1, + pc_cfg_slp_sl_thold_1, + pc_sg_1}) + ); + + tri_plat #(.WIDTH(4)) perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ccflush_dc), + .din({pc_func_sl_thold_1, + pc_func_slp_sl_thold_1, + pc_cfg_slp_sl_thold_1, + pc_sg_1}), + .q({pc_func_sl_thold_0, + pc_func_slp_sl_thold_0, + pc_cfg_slp_sl_thold_0, + pc_sg_0}) + ); + + tri_lcbor perv_lcbor_func_sl( + .clkoff_b(lcb_clkoff_dc_b), + .thold(pc_func_sl_thold_0), + .sg(pc_sg_0), + .act_dis(lcb_act_dis_dc), + .force_t(pc_func_sl_force), + .thold_b(pc_func_sl_thold_0_b) + ); + + tri_lcbor perv_lcbor_func_slp_sl( + .clkoff_b(lcb_clkoff_dc_b), + .thold(pc_func_slp_sl_thold_0), + .sg(pc_sg_0), + .act_dis(lcb_act_dis_dc), + .force_t(pc_func_slp_sl_force), + .thold_b(pc_func_slp_sl_thold_0_b) + ); + + //------------------------------------------------ + // local clock buffer for boot config + //------------------------------------------------ + + tri_lcbs bcfg_lcb( + .vd(vdd), + .gd(gnd), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .nclk(nclk), + .force_t(pc_cfg_slp_sl_force), + .thold_b(pc_cfg_slp_sl_thold_0_b), + .dclk(lcb_dclk), + .lclk(lcb_lclk) + ); + + // these terms in the absence of another lcbor component + // that drives the thold_b and force into the bcfg_lcb for slat's + assign pc_cfg_slp_sl_thold_0_b = (~pc_cfg_slp_sl_thold_0); + assign pc_cfg_slp_sl_force = pc_sg_0; + + //--------------------------------------------------------------------- + // Scan + //--------------------------------------------------------------------- + assign siv_0[0:scan_right_0] = {sov_0[1:scan_right_0], ac_func_scan_in[0]}; + assign ac_func_scan_out[0] = sov_0[0]; + assign siv_1[0:scan_right_1] = {sov_1[1:scan_right_1], ac_func_scan_in[1]}; + assign ac_func_scan_out[1] = sov_1[0]; + assign bsiv[0:boot_scan_right] = {bsov[1:boot_scan_right], ac_ccfg_scan_in}; + assign ac_ccfg_scan_out = bsov[0]; + +endmodule diff --git a/dev/verilog/work/iuq_ic_miss.v b/dev/verilog/work/iuq_ic_miss.v new file mode 100755 index 0000000..a173d1d --- /dev/null +++ b/dev/verilog/work/iuq_ic_miss.v @@ -0,0 +1,2225 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//******************************************************************** +//* +//* TITLE: +//* +//* NAME: iuq_ic_miss.v +//* +//********************************************************************* + +`include "tri_a2o.vh" + + +module iuq_ic_miss( + vdd, + gnd, + nclk, + pc_iu_func_sl_thold_0_b, + pc_iu_sg_0, + force_t, + d_mode, + delay_lclkr, + mpw1_b, + mpw2_b, + scan_in, + scan_out, + iu_flush, + br_iu_redirect, + bp_ic_iu4_redirect, + ic_bp_iu3_ecc_err, + ics_icm_iu0_t0_ifar, + `ifndef THREADS1 + ics_icm_iu0_t1_ifar, + `endif + ics_icm_iu0_inval, + ics_icm_iu0_inval_addr, + ics_icm_iu2_flush, + icm_ics_hold_thread, + icm_ics_hold_iu0, + icm_ics_iu3_miss_match, + icm_ics_iu3_ecc_fp_cancel, + icm_ics_iu0_preload_val, + icm_ics_iu0_preload_ifar, + icm_ics_prefetch_req, + icm_ics_prefetch_sm_idle, + icm_icd_lru_addr, + icm_icd_dir_inval, + icm_icd_dir_val, + icm_icd_data_write, + icm_icd_reload_addr, + icm_icd_reload_data, + icm_icd_reload_way, + icm_icd_load, + icm_icd_load_addr, + icm_icd_load_2ucode, + icm_icd_load_2ucode_type, + icm_icd_dir_write, + icm_icd_dir_write_addr, + icm_icd_dir_write_endian, + icm_icd_dir_write_way, + icm_icd_lru_write, + icm_icd_lru_write_addr, + icm_icd_lru_write_way, + icm_icd_ecc_inval, + icm_icd_ecc_addr, + icm_icd_ecc_way, + icm_icd_iu3_ecc_fp_cancel, + icm_icd_any_reld_r2, + icd_icm_miss, + icd_icm_prefetch, + icd_icm_tid, + icd_icm_addr_real, + icd_icm_addr_eff, + icd_icm_wimge, + icd_icm_userdef, + icd_icm_2ucode, + icd_icm_2ucode_type, + icd_icm_iu2_inval, + icd_icm_any_iu2_valid, + icd_icm_row_lru, + icd_icm_row_val, + ic_perf_t0_event, + `ifndef THREADS1 + ic_perf_t1_event, + `endif + cp_async_block, + iu_mm_lmq_empty, + iu_xu_icache_quiesce, + iu_pc_icache_quiesce, + an_ac_reld_data_vld, + an_ac_reld_core_tag, + an_ac_reld_qw, + an_ac_reld_data, + an_ac_reld_ecc_err, + an_ac_reld_ecc_err_ue, + spr_ic_cls, + spr_ic_bp_config, + iu_lq_request, + iu_lq_ctag, + iu_lq_ra, + iu_lq_wimge, + iu_lq_userdef, + event_bus_enable +); + + + inout vdd; + + inout gnd; + + (* pin_data ="PIN_FUNCTION=/G_CLK/" *) + input [0:`NCLK_WIDTH-1] nclk; + input pc_iu_func_sl_thold_0_b; + input pc_iu_sg_0; + input force_t; + input d_mode; + input delay_lclkr; + input mpw1_b; + input mpw2_b; + input scan_in; + output scan_out; + + input [0:`THREADS-1] iu_flush; + input [0:`THREADS-1] br_iu_redirect; + input [0:`THREADS-1] bp_ic_iu4_redirect; + + output ic_bp_iu3_ecc_err; + + input [46:52] ics_icm_iu0_t0_ifar; + `ifndef THREADS1 + input [46:52] ics_icm_iu0_t1_ifar; + `endif + + input ics_icm_iu0_inval; + input [51:57] ics_icm_iu0_inval_addr; + + input [0:`THREADS-1] ics_icm_iu2_flush; + output [0:`THREADS-1] icm_ics_hold_thread; + output icm_ics_hold_iu0; + output icm_ics_iu3_miss_match; + output [0:`THREADS-1] icm_ics_iu3_ecc_fp_cancel; + + output [0:`THREADS-1] icm_ics_iu0_preload_val; + output [50:59] icm_ics_iu0_preload_ifar; + output [0:`THREADS-1] icm_ics_prefetch_req; + output [0:`THREADS-1] icm_ics_prefetch_sm_idle; + + output [51:57] icm_icd_lru_addr; + output icm_icd_dir_inval; + output icm_icd_dir_val; + output icm_icd_data_write; + output [51:59] icm_icd_reload_addr; + output [0:143] icm_icd_reload_data; + output [0:3] icm_icd_reload_way; + output [0:`THREADS-1] icm_icd_load; + output [62-`EFF_IFAR_WIDTH:61] icm_icd_load_addr; + output icm_icd_load_2ucode; + output icm_icd_load_2ucode_type; + output icm_icd_dir_write; + output [64-`REAL_IFAR_WIDTH:57] icm_icd_dir_write_addr; + output icm_icd_dir_write_endian; + output [0:3] icm_icd_dir_write_way; + output icm_icd_lru_write; + output [51:57] icm_icd_lru_write_addr; + output [0:3] icm_icd_lru_write_way; + output icm_icd_ecc_inval; + output [51:57] icm_icd_ecc_addr; + output [0:3] icm_icd_ecc_way; + output icm_icd_iu3_ecc_fp_cancel; + output icm_icd_any_reld_r2; + + input icd_icm_miss; // These signals, except icd_icm_miss, come off a latch + input icd_icm_prefetch; + input [0:`THREADS-1] icd_icm_tid; + input [64-`REAL_IFAR_WIDTH:61] icd_icm_addr_real; + input [62-`EFF_IFAR_WIDTH:51] icd_icm_addr_eff; // Shares bits 52:61 with real_ifar + input [0:4] icd_icm_wimge; // (1): CI, (4): Endian + input [0:3] icd_icm_userdef; + input icd_icm_2ucode; + input icd_icm_2ucode_type; + input icd_icm_iu2_inval; + input icd_icm_any_iu2_valid; + + input [0:2] icd_icm_row_lru; // valid same cycle as read_lru + input [0:3] icd_icm_row_val; // valid same cycle as read_lru + + output [0:2] ic_perf_t0_event; + `ifndef THREADS1 + output [0:2] ic_perf_t1_event; + `endif + + input [0:`THREADS-1] cp_async_block; + output iu_mm_lmq_empty; + output [0:`THREADS-1] iu_xu_icache_quiesce; + output [0:`THREADS-1] iu_pc_icache_quiesce; + + input an_ac_reld_data_vld; // This comes back two cycles before the data + input [0:4] an_ac_reld_core_tag; // This signal comes active two cycles before the data + input [58:59] an_ac_reld_qw; // This signal comes active two cycles before the data + input [0:127] an_ac_reld_data; // This signal comes active two cycles after the valid + input an_ac_reld_ecc_err; // This signal comes active one cycle after data + input an_ac_reld_ecc_err_ue; // This signal comes active one cycle after data + + input spr_ic_cls; // (0): 64B cacheline, (1): 128B cacheline + input [0:3] spr_ic_bp_config; // (0): bc, (1): bclr, (2): bcctr, (3): sw + + output [0:`THREADS-1] iu_lq_request; + output [0:1] iu_lq_ctag; // (0): thread ID, (1): prefetch + output [64-`REAL_IFAR_WIDTH:59] iu_lq_ra; + output [0:4] iu_lq_wimge; + output [0:3] iu_lq_userdef; + + input event_bus_enable; + + + localparam [0:31] value_1 = 32'h00000001; + localparam [0:31] value_2 = 32'h00000002; + + parameter SM_MAX = 4; // max # of state machines (# of tables) + parameter TAGS_USED = `THREADS * 2; + + parameter spr_ic_cls_offset = 0; + parameter bp_config_offset = spr_ic_cls_offset + 1; + parameter an_ac_reld_data_vld_offset = bp_config_offset + 4; + parameter an_ac_reld_core_tag_offset = an_ac_reld_data_vld_offset + 1; + parameter an_ac_reld_qw_offset = an_ac_reld_core_tag_offset + 5; + parameter reld_data_offset = an_ac_reld_qw_offset + 2; + parameter an_ac_reld_ecc_err_offset = reld_data_offset + 128; + parameter an_ac_reld_ecc_err_ue_offset = an_ac_reld_ecc_err_offset + 1; + parameter reld_r1_val_offset = an_ac_reld_ecc_err_ue_offset + 1; + parameter reld_r1_qw_offset = reld_r1_val_offset + TAGS_USED; + parameter reld_r2_val_offset = reld_r1_qw_offset + 2; + parameter reld_r2_qw_offset = reld_r2_val_offset + TAGS_USED; + parameter r2_crit_qw_offset = reld_r2_qw_offset + 2; + parameter reld_r3_val_offset = r2_crit_qw_offset + 1; + parameter r3_loaded_offset = reld_r3_val_offset + TAGS_USED; + parameter request_offset = r3_loaded_offset + 1; + parameter req_ctag_offset = request_offset + `THREADS; + parameter req_ra_offset = req_ctag_offset + 2; + parameter req_wimge_offset = req_ra_offset + `REAL_IFAR_WIDTH - 4; + parameter req_userdef_offset = req_wimge_offset + 5; + parameter iu3_miss_match_offset = req_userdef_offset + 4; + + parameter miss_tid_sm_offset = iu3_miss_match_offset + 1; + parameter miss_count_offset = miss_tid_sm_offset + TAGS_USED * 6; + parameter miss_flush_occurred_offset = miss_count_offset + TAGS_USED * 3; + parameter miss_flushed_offset = miss_flush_occurred_offset + TAGS_USED; + parameter miss_inval_offset = miss_flushed_offset + TAGS_USED; + parameter miss_block_fp_offset = miss_inval_offset + TAGS_USED; + parameter miss_ecc_err_offset = miss_block_fp_offset + TAGS_USED; + parameter miss_ecc_err_ue_offset = miss_ecc_err_offset + TAGS_USED; + parameter miss_wrote_dir_offset = miss_ecc_err_ue_offset + TAGS_USED; + parameter miss_need_hold_offset = miss_wrote_dir_offset + TAGS_USED; + parameter miss_addr_real_offset = miss_need_hold_offset + TAGS_USED; + parameter miss_addr_eff_offset = miss_addr_real_offset + TAGS_USED * (`REAL_IFAR_WIDTH - 2); + parameter miss_ci_offset = miss_addr_eff_offset + TAGS_USED * (`EFF_IFAR_WIDTH - 10); + parameter miss_endian_offset = miss_ci_offset + TAGS_USED; + parameter miss_2ucode_offset = miss_endian_offset + TAGS_USED; + parameter miss_2ucode_type_offset = miss_2ucode_offset + TAGS_USED; + parameter miss_way_offset = miss_2ucode_type_offset + TAGS_USED; + parameter lru_write_next_cycle_offset = miss_way_offset + 4 * TAGS_USED; + parameter lru_write_offset = lru_write_next_cycle_offset + TAGS_USED; + parameter miss_prefetch_perf_offset = lru_write_offset + TAGS_USED; + parameter perf_event_offset = miss_prefetch_perf_offset + `THREADS; + parameter scan_right = perf_event_offset + `THREADS * 3 - 1; + + parameter IDLE = 0; + parameter WAITMISS = 1; + parameter WAITSTATE = 2; + parameter DATA = 3; + parameter CI = 4; + parameter CHECK_ECC = 5; + + wire [1:24] select_lru_way_pt; + + // Latch definition begin + wire [0:TAGS_USED-1] reld_r1_val_d; + wire spr_ic_cls_d; + wire [0:3] bp_config_d; + wire an_ac_reld_data_vld_d; + wire [0:4] an_ac_reld_core_tag_d; + wire [58:59] an_ac_reld_qw_d; + wire [0:127] reld_data_d; + wire an_ac_reld_ecc_err_d; + wire an_ac_reld_ecc_err_ue_d; + wire [0:1] reld_r1_qw_d; + wire [0:TAGS_USED-1] reld_r2_val_d; + wire [0:1] reld_r2_qw_d; + wire r2_crit_qw_d; + wire [0:TAGS_USED-1] reld_r3_val_d; + wire r3_loaded_d; + wire [0:`THREADS-1] request_d; + wire [0:1] req_ctag_d; + wire [64-`REAL_IFAR_WIDTH:59] req_ra_d; + wire [0:4] req_wimge_d; + wire [0:3] req_userdef_d; + wire iu3_miss_match_d; + wire [0:5] miss_tid_sm_d[0:SM_MAX-1]; + wire [0:2] miss_count_d[0:TAGS_USED-1]; + wire [64-`REAL_IFAR_WIDTH:61] miss_addr_real_d[0:TAGS_USED-1]; + wire [62-`EFF_IFAR_WIDTH:51] miss_addr_eff_d[0:TAGS_USED-1]; + wire [0:3] miss_way_d[0:TAGS_USED-1]; + wire [0:TAGS_USED-1] miss_flush_occurred_d; + wire [0:SM_MAX-1] miss_flushed_d; + wire [0:SM_MAX-1] miss_inval_d; + wire [0:TAGS_USED-1] miss_block_fp_d; + wire [0:TAGS_USED-1] miss_ecc_err_d; + wire [0:TAGS_USED-1] miss_ecc_err_ue_d; + wire [0:TAGS_USED-1] miss_wrote_dir_d; + wire [0:TAGS_USED-1] miss_need_hold_d; + wire [0:SM_MAX-1] miss_ci_d; + wire [0:TAGS_USED-1] miss_endian_d; + wire [0:TAGS_USED-1] miss_2ucode_d; + wire [0:TAGS_USED-1] miss_2ucode_type_d; + wire [0:TAGS_USED-1] lru_write_next_cycle_d; + wire [0:TAGS_USED-1] lru_write_d; + wire [0:`THREADS-1] miss_prefetch_perf_d; + wire [0:2] perf_event_d[0:`THREADS-1]; + + wire [0:SM_MAX-1] reld_r1_val_l2; + wire spr_ic_cls_l2; + wire [0:3] bp_config_l2; + wire an_ac_reld_data_vld_l2; + wire [0:4] an_ac_reld_core_tag_l2; + wire [58:59] an_ac_reld_qw_l2; + wire [0:127] reld_data_l2; + wire an_ac_reld_ecc_err_l2; + wire an_ac_reld_ecc_err_ue_l2; + wire [0:1] reld_r1_qw_l2; + wire [0:TAGS_USED-1] reld_r2_val_l2; + wire [0:1] reld_r2_qw_l2; + wire r2_crit_qw_l2; + wire [0:TAGS_USED-1] reld_r3_val_l2; + wire r3_loaded_l2; + wire [0:`THREADS-1] request_l2; + wire [0:1] req_ctag_l2; + wire [64-`REAL_IFAR_WIDTH:59] req_ra_l2; + wire [0:4] req_wimge_l2; + wire [0:3] req_userdef_l2; + wire iu3_miss_match_l2; + wire [0:5] miss_tid_sm_l2[0:SM_MAX-1]; //state machine for each tag + wire [0:2] miss_count_l2[0:TAGS_USED-1]; + wire [64-`REAL_IFAR_WIDTH:61] miss_addr_real_l2[0:TAGS_USED-1]; + wire [62-`EFF_IFAR_WIDTH:51] miss_addr_eff_l2[0:TAGS_USED-1]; + wire [0:3] miss_way_l2[0:TAGS_USED-1]; + wire [0:TAGS_USED-1] miss_flush_occurred_l2; + wire [0:SM_MAX-1] miss_flushed_l2; + wire [0:SM_MAX-1] miss_inval_l2; + wire [0:TAGS_USED-1] miss_block_fp_l2; //block fastpath + wire [0:TAGS_USED-1] miss_ecc_err_l2; + wire [0:TAGS_USED-1] miss_ecc_err_ue_l2; + wire [0:TAGS_USED-1] miss_wrote_dir_l2; + wire [0:TAGS_USED-1] miss_need_hold_l2; + wire [0:SM_MAX-1] miss_ci_l2; + wire [0:TAGS_USED-1] miss_endian_l2; + wire [0:TAGS_USED-1] miss_2ucode_l2; + wire [0:TAGS_USED-1] miss_2ucode_type_l2; + wire [0:TAGS_USED-1] lru_write_next_cycle_l2; + wire [0:TAGS_USED-1] lru_write_l2; + wire [0:`THREADS-1] miss_prefetch_perf_l2; + wire [0:2] perf_event_l2[0:`THREADS-1]; + // Latch definition end + + wire [46:52] iu0_ifar[0:TAGS_USED-1]; + + // Act control; only needed for power reduction + wire [0:TAGS_USED-1] default_reld_act_v; + wire default_reld_act; + wire miss_or_default_act; + wire reld_r2_act; + wire [0:TAGS_USED-1] miss_act; + + // reload pipeline + wire reld_r0_vld; + wire [0:TAGS_USED-1] reld_r0_tag; + wire [0:`THREADS-1] reld_r3_tid; + + wire [0:`THREADS-1] iu_xu_icache_quiesce_int; + + wire [0:SM_MAX-1] iu2_flush; + wire [0:SM_MAX-1] new_miss; + wire [0:SM_MAX-1] last_data; + wire [0:TAGS_USED-1] no_data; + wire [0:TAGS_USED-1] set_flush_occurred; + wire [0:TAGS_USED-1] flush_addr_outside_range; + + wire [0:TAGS_USED-1] set_flushed; + wire [0:TAGS_USED-1] inval_equal; + wire [0:TAGS_USED-1] set_invalidated; + wire [0:SM_MAX-1] reset_state; + wire [0:TAGS_USED-1] sent_fp; + wire [0:TAGS_USED-1] set_block_fp; + + // this signal will check incoming addr against current valid addresses + wire [0:TAGS_USED-1] addr_equal; + wire [0:TAGS_USED-1] addr_match_tag; + wire addr_match; + wire miss_thread_has_idle; + + wire release_sm; + wire [0:SM_MAX-1] release_sm_hold; + + // IU0 inval + wire [0:TAGS_USED-1] iu0_inval_match; + + // OR these together to get iu_lq_request + wire [0:SM_MAX-1] request_tag; + + // fastpath + wire [0:TAGS_USED-1] preload_r0_tag; + wire [0:`THREADS-1] preload_r0_tid; + wire [0:`THREADS-1] preload_hold_iu0; + reg [50:59] r0_addr; + wire [0:SM_MAX-1] load_tag; + reg [62-`EFF_IFAR_WIDTH:61] load_addr; + wire load_2ucode; + wire load_2ucode_type; + wire [0:TAGS_USED-1] load_tag_no_block; + wire [0:`THREADS-1] load_tid_no_block; + + // this signal indicates critical quadword is in r0, r1 + wire [0:TAGS_USED-1] r0_crit_qw; + wire [0:TAGS_USED-1] r1_crit_qw; + + // lru + wire lru_write_hit; + wire [0:2] hit_lru; + wire [0:2] row_lru; + wire [0:TAGS_USED-1] select_lru; + reg [51:57] lru_addr; + wire [0:TAGS_USED-1] lru_valid; + wire [0:TAGS_USED-1] row_match; + reg [0:3] row_match_way; + wire [0:3] val_or_match; + wire [0:3] next_lru_way; + wire [0:3] next_way; + + // this signal is set by each state machine; OR bits together for final holds + wire [0:SM_MAX-1] hold_tid; + wire hold_iu0; + + // OR these together to get icm_icd_* + wire [0:SM_MAX-1] write_dir_inval; + wire [0:SM_MAX-1] write_dir_val; + wire [0:SM_MAX-1] data_write; + wire [0:SM_MAX-1] dir_write; + wire [0:TAGS_USED-1] dir_write_no_block; + + reg [64-`REAL_IFAR_WIDTH:57] reload_addr; + reg [0:3] reload_way; + wire reload_endian; + wire reld_r1_endian; + wire [0:127] swap_endian_data; + + wire [0:3] branch_decode0; + wire [0:3] branch_decode1; + wire [0:3] branch_decode2; + wire [0:3] branch_decode3; + + wire [0:143] instr_data; + + wire [0:TAGS_USED-1] lru_write; + reg [51:57] lru_write_addr; + reg [0:3] lru_write_way; + + // ECC Error handling + wire [0:TAGS_USED-1] new_ecc_err; + wire [0:TAGS_USED-1] new_ecc_err_ue; + wire [0:SM_MAX-1] ecc_err; + wire [0:SM_MAX-1] ecc_err_ue; + wire [0:TAGS_USED-1] ecc_inval; + wire [0:TAGS_USED-1] ecc_block_iu0; + wire ecc_fp; + reg [51:57] r3_addr; + reg [0:3] r3_way; + + wire [0:SM_MAX-1] active_l1_miss; + wire [0:scan_right] siv; + wire [0:scan_right] sov; + + wire [0:31] tidn32; + + + (* analysis_not_referenced="true" *) + + wire miss_unused; + + //@@ START OF EXECUTABLE CODE FOR IUQ_IC_MISS + + assign tidn32 = 32'b0; + + generate + begin : xhdl1 + if (TAGS_USED < SM_MAX) + begin : gen_unused_t1 + assign miss_unused = | {load_tag[TAGS_USED:SM_MAX - 1], reset_state[TAGS_USED:SM_MAX - 1], request_tag[TAGS_USED:SM_MAX - 1], write_dir_val[TAGS_USED:SM_MAX - 1], hold_tid[TAGS_USED:SM_MAX - 1], dir_write[TAGS_USED:SM_MAX - 1], miss_ci_d[TAGS_USED:SM_MAX - 1], miss_flushed_d[TAGS_USED:SM_MAX - 1], miss_inval_d[TAGS_USED:SM_MAX - 1], active_l1_miss[TAGS_USED:SM_MAX-1], miss_tid_sm_d[TAGS_USED], miss_tid_sm_d[SM_MAX - 1]}; // ??? tid_sm isn't covered for (sm_max-tags_used > 2) + + // sourceless unused + assign iu2_flush[TAGS_USED:SM_MAX - 1] = {SM_MAX-TAGS_USED{1'b0}}; + assign new_miss[TAGS_USED:SM_MAX - 1] = {SM_MAX-TAGS_USED{1'b0}}; + assign last_data[TAGS_USED:SM_MAX - 1] = {SM_MAX-TAGS_USED{1'b0}}; + assign ecc_err[TAGS_USED:SM_MAX - 1] = {SM_MAX-TAGS_USED{1'b0}}; + assign ecc_err_ue[TAGS_USED:SM_MAX - 1] = {SM_MAX-TAGS_USED{1'b0}}; + + // Latches + assign reld_r1_val_l2[TAGS_USED:SM_MAX - 1] = {SM_MAX-TAGS_USED{1'b0}}; + + assign miss_flushed_d[TAGS_USED:SM_MAX - 1] = {SM_MAX-TAGS_USED{1'b0}}; + assign miss_inval_d[TAGS_USED:SM_MAX - 1] = {SM_MAX-TAGS_USED{1'b0}}; + assign miss_ci_d[TAGS_USED:SM_MAX - 1] = {SM_MAX-TAGS_USED{1'b0}}; + + assign miss_flushed_l2[TAGS_USED:SM_MAX - 1] = {SM_MAX-TAGS_USED{1'b0}}; + assign miss_inval_l2[TAGS_USED:SM_MAX - 1] = {SM_MAX-TAGS_USED{1'b0}}; + assign miss_ci_l2[TAGS_USED:SM_MAX - 1] = {SM_MAX-TAGS_USED{1'b0}}; + + genvar i; + for (i = TAGS_USED; i < SM_MAX; i = i + 1) + begin : gen_sm_t1 + assign miss_tid_sm_l2[i][0] = 1'b1; + assign miss_tid_sm_l2[i][1:CHECK_ECC] = {CHECK_ECC{1'b0}}; + end + end + + if (TAGS_USED >= SM_MAX) + begin : gen_unused_t2 + assign miss_unused = 1'b0; + end + + end + endgenerate + + assign iu0_ifar[0] = ics_icm_iu0_t0_ifar; + assign iu0_ifar[1] = ics_icm_iu0_t0_ifar; + + `ifndef THREADS1 + assign iu0_ifar[2] = ics_icm_iu0_t1_ifar; + assign iu0_ifar[3] = ics_icm_iu0_t1_ifar; + `endif + + //--------------------------------------------------------------------- + // Latch Inputs, Reload pipeline + //--------------------------------------------------------------------- + generate + begin : xhdl2 + genvar i; + for (i = 0; i < TAGS_USED; i = i + 1) + begin : gen_default_reld_act + assign default_reld_act_v[i] = (~miss_tid_sm_l2[i][IDLE]); + end + end + endgenerate + + assign default_reld_act = |(default_reld_act_v); + assign miss_or_default_act = default_reld_act | (|(miss_act)); + assign reld_r2_act = |(reld_r1_val_l2); + + assign bp_config_d = spr_ic_bp_config; // ??? Do I need to latch these? How far away is spr? + assign spr_ic_cls_d = spr_ic_cls; + + // d-2 (r0) + assign an_ac_reld_data_vld_d = an_ac_reld_data_vld; + assign an_ac_reld_core_tag_d = an_ac_reld_core_tag; + assign an_ac_reld_qw_d = an_ac_reld_qw; + + // d-1 (r1) + // Core_tag(0:2) specifies unit (IU is '010'); Core_tag(3:4) is encoded Thread ID + assign reld_r0_vld = an_ac_reld_data_vld_l2 & (an_ac_reld_core_tag_l2[0:2] == 3'b010); + + generate + begin : xhdl3 + genvar i; + for (i = 0; i < TAGS_USED; i = i + 1) + begin : gen_reld_tag + wire [0:1] index = i; + assign reld_r0_tag[i] = (an_ac_reld_core_tag_l2[3:4] == index); + end + end + endgenerate + + assign reld_r1_val_d = {TAGS_USED{reld_r0_vld}} & reld_r0_tag; + assign reld_r1_qw_d = an_ac_reld_qw_l2; + + // d (r2) + // Use reld_r1_vld as act to gate clock + assign reld_r2_val_d = reld_r1_val_l2[0:TAGS_USED - 1]; + assign reld_r2_qw_d = reld_r1_qw_l2; + + // d+1 (r3) + assign reld_r3_val_d = reld_r2_val_l2; + assign an_ac_reld_ecc_err_d = an_ac_reld_ecc_err; + assign an_ac_reld_ecc_err_ue_d = an_ac_reld_ecc_err_ue; + + generate + begin : xhdl4 + genvar i; + for (i = 0; i < `THREADS; i = i + 1) + begin : gen_reld_r3_tid + assign reld_r3_tid[i] = reld_r3_val_l2[2 * i] | reld_r3_val_l2[2 * i + 1]; + assign iu2_flush[2 * i] = ics_icm_iu2_flush[i]; + assign iu2_flush[2 * i + 1] = ics_icm_iu2_flush[i]; + end + end + endgenerate + + //--------------------------------------------------------------------- + // State Machine + //--------------------------------------------------------------------- + // Example State Ordering for cacheable reloads + // OLD: + // 64B Cacheline, No Gaps : (1)(3)(4)(5)(6)(11) - Wait 0, Data0, Data1, Data2, Data3, CheckECC + // 64B Cacheline, Always Gaps: (1)(3)(8)(4)(9)(5)(10)(6)(11) - Wait 0, Data0, Wait1, Data1, Wait2, Data2, Wait3, Data3, CheckECC + // 128B Cacheline, No Gaps : (1)(3)(4)(5)(12)(13)(14)(15)(6)(11) - Wait 0, Data0, Data1, Data2, Data3_128B, Data4_128B, Data5_128B, Data6_128B, Data3/7, CheckECC + // 128B Cacheline, Always Gaps: (1)(3)(8)(4)(9)(5)(16)(12)(17)(13)(18)(14)(19)(15)(10)(6)(11) + // - Wait 0, Data0, Wait1, Data1, Wait2, Data2, Wait3_128B, Data3_128B, Wait4_128B, Data4_128B, Wait5_128B, Data5_128B, Wait6_128B, Data6_128B, Data3/7, CheckECC + // + // New: + // 64B Cacheline, No Gaps : (2)(3)(3)(3)(3)(5) - Wait, Data, Data, Data, Data, CheckECC + // 64B Cacheline, Always Gaps : (2)(3)(2)(3)(2)(3)(2)(3)(5) - Wait, Data, Wait, Data, Wait, Data, Wait, Data, CheckECC + // similar pattern for 128B + // + // For now, always generating 4 tables, even if only 1 thread. Can't generate based on a generic, and don't want to include config file. Extra tables should optimize out when not needed. + // + generate + begin + genvar i; + for (i = 0; i < SM_MAX; i = i + 1) + begin : miss_sm_loop + iuq_ic_miss_table miss_sm( + .new_miss(new_miss[i]), + .miss_ci_l2(miss_ci_l2[i]), + .reld_r1_val_l2(reld_r1_val_l2[i]), + .r2_crit_qw_l2(r2_crit_qw_l2), + .ecc_err(ecc_err[i]), + .ecc_err_ue(ecc_err_ue[i]), + .addr_match(addr_match), + .iu2_flush(iu2_flush[i]), + .release_sm(release_sm), + .miss_flushed_l2(miss_flushed_l2[i]), + .miss_inval_l2(miss_inval_l2[i]), + .miss_tid_sm_l2(miss_tid_sm_l2[i]), + .last_data(last_data[i]), + .miss_tid_sm_d(miss_tid_sm_d[i]), + .reset_state(reset_state[i]), + .request_tag(request_tag[i]), + .write_dir_inval(write_dir_inval[i]), + .write_dir_val(write_dir_val[i]), + .hold_tid(hold_tid[i]), + .data_write(data_write[i]), + .dir_write(dir_write[i]), + .load_tag(load_tag[i]), + .release_sm_hold(release_sm_hold[i]) + ); + end + end + endgenerate + + //--------------------------------------------------------------------- + + assign iu_mm_lmq_empty = &(iu_xu_icache_quiesce_int) & (~(|(cp_async_block))); + assign iu_xu_icache_quiesce = iu_xu_icache_quiesce_int; + assign iu_pc_icache_quiesce = iu_xu_icache_quiesce_int; + + // SM0 is only for non-prefetches, SM1 is for prefetches, or for new IFetches if SM1 is free and SM0 is busy (e.g. sometimes after flush) + generate + begin : xhdl5 + genvar i; + for (i = 0; i < `THREADS; i = i + 1) + begin : gen_new_miss + assign new_miss[2*i] = icd_icm_miss & icd_icm_tid[i] & (~icd_icm_prefetch); + assign new_miss[2*i+1] = icd_icm_miss & icd_icm_tid[i] & ((icd_icm_prefetch & (~icd_icm_wimge[1]) & (~icd_icm_wimge[3])) | (~miss_tid_sm_l2[2*i][IDLE])); + + // Only active when performance enabled + assign miss_prefetch_perf_d[i] = (icd_icm_miss & icd_icm_tid[i] & miss_tid_sm_l2[2*i+1][IDLE]) ? + (icd_icm_prefetch & (~icd_icm_wimge[1]) & (~icd_icm_wimge[3])) : + miss_prefetch_perf_l2[i]; + + assign iu_xu_icache_quiesce_int[i] = miss_tid_sm_l2[2*i][IDLE] & miss_tid_sm_l2[2*i+1][IDLE]; + assign icm_ics_prefetch_req[i] = icd_icm_miss & icd_icm_tid[i] & (~icd_icm_prefetch) & (~icd_icm_wimge[1]) & (~icd_icm_wimge[3]) & (~addr_match) & (miss_tid_sm_l2[2*i][IDLE] | miss_tid_sm_l2[2*i+1][IDLE]) & (~ics_icm_iu2_flush[i]); + assign icm_ics_prefetch_sm_idle[i] = miss_tid_sm_l2[2*i+1][IDLE]; + end + + //genvar i; + for (i = 0; i < TAGS_USED; i = i + 1) + begin : gen_miss + // Count down from 3 (if 64B) or 7 (if 128B) + assign miss_count_d[i] = ((request_tag[i] | (miss_tid_sm_l2[i][CHECK_ECC] & ecc_err[i])) == 1'b1) ? {spr_ic_cls_l2, 2'b11} : + (miss_tid_sm_l2[i][DATA] == 1'b1) ? miss_count_l2[i] - 3'b001 : + miss_count_l2[i]; + + assign last_data[i] = miss_count_l2[i] == 3'b000; + assign no_data[i] = miss_count_l2[i] == {spr_ic_cls_l2, 2'b11}; + + assign miss_act[i] = miss_tid_sm_l2[i][IDLE] & icd_icm_any_iu2_valid & icd_icm_tid[i/2]; // Idle state and processing this thread + assign miss_addr_real_d[i] = icd_icm_addr_real; // uses miss_act + assign miss_addr_eff_d[i] = icd_icm_addr_eff; // uses miss_act + assign miss_ci_d[i] = icd_icm_wimge[1]; // uses miss_act + assign miss_endian_d[i] = icd_icm_wimge[4]; // uses miss_act + assign miss_2ucode_d[i] = icd_icm_2ucode; // uses miss_act + assign miss_2ucode_type_d[i] = icd_icm_2ucode_type; // uses miss_act + + // State-related latches + assign set_flush_occurred[i] = (iu_flush[i/2] | br_iu_redirect[i/2] | bp_ic_iu4_redirect[i/2]) & (~miss_tid_sm_l2[i][IDLE]) & (~miss_tid_sm_l2[i][WAITMISS]); + assign miss_flush_occurred_d[i] = (reset_state[i] == 1'b1) ? 1'b0 : // reset when going back to idle state + (set_flush_occurred[i] == 1'b1) ? 1'b1 : // set when new flush + miss_flush_occurred_l2[i]; + + // Flushed before entering Data0 - don't load ICache if flushed outside range + assign flush_addr_outside_range[i] = iu0_ifar[i] != {miss_addr_eff_l2[i][46:51], miss_addr_real_l2[i][52]}; // eff address shares lower bits with real addr + + assign set_flushed[i] = miss_flush_occurred_l2[i] & flush_addr_outside_range[i] & reld_r1_val_l2[i] & + ((miss_tid_sm_l2[i][WAITSTATE] & no_data[i]) | miss_tid_sm_l2[i][CHECK_ECC]); + + assign miss_flushed_d[i] = (reset_state[i] == 1'b1) ? 1'b0 : // reset when going back to idle state + (set_flushed[i] == 1'b1) ? 1'b1 : // set when new flush + miss_flushed_l2[i]; + end + + assign inval_equal = {TAGS_USED{icd_icm_iu2_inval}} & addr_equal; + + //genvar i; + for (i = 0; i < TAGS_USED; i = i + 1) + begin : gen_miss_inval + assign set_invalidated[i] = inval_equal[i] & (~miss_tid_sm_l2[i][IDLE]) & (~miss_tid_sm_l2[i][WAITMISS]) & (~miss_ci_l2[i]); + assign miss_inval_d[i] = (reset_state[i] == 1'b1) ? 1'b0 : // reset when going back to idle state + (set_invalidated[i] == 1'b1) ? 1'b1 : // set when new back_inv + miss_inval_l2[i]; + end + + //genvar i; + for (i = 0; i < TAGS_USED; i = i + 1) + begin : gen_miss_block_fp + assign sent_fp[i] = (r3_loaded_l2 & (~(an_ac_reld_ecc_err_l2))) & reld_r3_val_l2[i]; // sent critical qw last cycle (unless it was blocked) + assign set_block_fp[i] = sent_fp[i] | // sent critical qw last cycle and not ecc err + (iu2_flush[i] & (~(miss_tid_sm_l2[i][IDLE] | miss_tid_sm_l2[i][WAITMISS]))) | + (icd_icm_prefetch & new_miss[i] & miss_tid_sm_l2[i][IDLE] & miss_tid_sm_d[i][WAITSTATE]); + assign miss_block_fp_d[i] = (reset_state[i] == 1'b1) ? 1'b0 : // reset when going back to idle state + (set_block_fp[i] == 1'b1) ? 1'b1 : // set when new block condition + miss_block_fp_l2[i]; + end + + //genvar i; + for (i = 0; i < TAGS_USED; i = i + 1) + begin : gen_miss_ecc_err + assign miss_ecc_err_d[i] = ((miss_tid_sm_l2[i][WAITSTATE] & no_data[i]) == 1'b1) ? 1'b0 : // reset before starting or resending data + (new_ecc_err[i] == 1'b1) ? 1'b1 : + miss_ecc_err_l2[i]; + + assign miss_ecc_err_ue_d[i] = ((miss_tid_sm_l2[i][WAITSTATE] & no_data[i]) == 1'b1) ? 1'b0 : // reset before starting or resending data + (new_ecc_err_ue[i] == 1'b1) ? an_ac_reld_ecc_err_ue_l2 : + miss_ecc_err_ue_l2[i]; + + assign addr_equal[i] = (icd_icm_addr_real[64 - `REAL_IFAR_WIDTH:56] == miss_addr_real_l2[i][64 - `REAL_IFAR_WIDTH:56]) & + (spr_ic_cls_l2 | (icd_icm_addr_real[57] == miss_addr_real_l2[i][57])); + + assign addr_match_tag[i] = (addr_equal[i] & (~miss_tid_sm_l2[i][IDLE])); + end + + assign addr_match = |(addr_match_tag); + + if (`THREADS == 1) + begin : gen_is_idle_t1 + assign miss_thread_has_idle = miss_tid_sm_l2[0][IDLE] | miss_tid_sm_l2[1][IDLE]; + end + if (`THREADS == 2) + begin : gen_is_idle_t2 + assign miss_thread_has_idle = ((miss_tid_sm_l2[0][IDLE] | miss_tid_sm_l2[1][IDLE]) & icd_icm_tid[0]) | + ((miss_tid_sm_l2[2][IDLE] | miss_tid_sm_l2[3][IDLE]) & icd_icm_tid[1]); + end + + assign iu3_miss_match_d = (miss_thread_has_idle == 1'b1) ? addr_match : // new miss matches other reload + 1'b1; //(not miss_thread_has_idle) --2nd (or 3rd) miss for thread - SM's full; + assign icm_ics_iu3_miss_match = iu3_miss_match_l2; + + assign release_sm = |(release_sm_hold); + + //genvar i; + for (i = 0; i < TAGS_USED; i = i + 1) + begin : gen_miss_wrote + // Detect write through collision with invalidate array read + assign iu0_inval_match[i] = ics_icm_iu0_inval & (ics_icm_iu0_inval_addr[51:56] == miss_addr_real_l2[i][51:56]) & + (spr_ic_cls_l2 | (ics_icm_iu0_inval_addr[57] == miss_addr_real_l2[i][57])); + + assign miss_wrote_dir_d[i] = (reset_state[i] == 1'b1) ? 1'b0 : // reset when going back to idle state + (dir_write_no_block[i] | miss_wrote_dir_l2[i]); + end + + //genvar i; + for (i = 0; i < `THREADS; i = i + 1) + begin : gen_need_hold + // Hold if new miss to SM0, or if new miss and no SMs available + assign miss_need_hold_d[2*i] = (iu2_flush[2*i] == 1'b1) ? 1'b0 : + ((new_miss[2*i] & + (miss_tid_sm_l2[2*i][IDLE] | ((~miss_tid_sm_l2[2*i][IDLE]) & (~miss_tid_sm_l2[2*i+1][IDLE])))) == 1'b1) ? 1'b1 : + miss_need_hold_l2[2*i]; + + // Hold if new miss to SM1 + assign miss_need_hold_d[2*i+1] = ((iu2_flush[2*i+1] | reset_state[2*i+1]) == 1'b1) ? 1'b0 : + ((new_miss[2*i] & // -- yes, I meant new_miss(2*i) - this is miss and tid and not prefetch + miss_tid_sm_l2[2*i+1][IDLE] & (~miss_tid_sm_l2[2*i][IDLE])) == 1'b1) ? 1'b1 : + miss_need_hold_l2[2 * i + 1]; + end + end + endgenerate + + //--------------------------------------------------------------------- + // Send request + //--------------------------------------------------------------------- + generate + begin : xhdl12 + genvar i; + for (i = 0; i < `THREADS; i = i + 1) + begin : gen_request + assign request_d[i] = request_tag[2*i] | request_tag[2*i+1]; + end + + if (`THREADS == 1) + begin : gen_ctag_t1 + assign req_ctag_d[0] = 1'b0; + end + if (`THREADS == 2) + begin : gen_ctag_t2 + assign req_ctag_d[0] = icd_icm_tid[1]; + end + end + endgenerate + + assign req_ctag_d[1] = new_miss[1] | new_miss[TAGS_USED - 1]; // prefetch or extra IFetch + + assign req_ra_d = icd_icm_addr_real[64 - `REAL_IFAR_WIDTH:59]; + assign req_wimge_d = icd_icm_wimge; + assign req_userdef_d = icd_icm_userdef; + + assign iu_lq_request = request_l2; + assign iu_lq_ctag = req_ctag_l2; + assign iu_lq_ra = req_ra_l2; + assign iu_lq_wimge = req_wimge_l2; + assign iu_lq_userdef = req_userdef_l2; + + //--------------------------------------------------------------------- + // address muxing + //--------------------------------------------------------------------- + +// always @(reld_r0_tag or reld_r1_val_l2 or reld_r2_val_l2 or lru_write_l2 or reld_r3_val_l2 or row_match or miss_addr_eff_l2 or miss_addr_real_l2 or miss_way_l2) + always @(*) + begin: addr_mux_proc + reg [50:59] r0_addr_calc; + reg [51:57] lru_addr_calc; + reg [62-`EFF_IFAR_WIDTH:61] load_addr_calc; + reg [64-`REAL_IFAR_WIDTH:57] reload_addr_calc; + reg [0:3] reload_way_calc; + reg [51:57] lru_write_addr_calc; + reg [0:3] lru_write_way_calc; + reg [51:57] r3_addr_calc; + reg [0:3] r3_way_calc; + reg [0:3] row_match_way_calc; + //(* analysis_not_referenced="true" *) + integer i; + r0_addr_calc = 10'b0; + lru_addr_calc = 7'b0; + load_addr_calc = {`EFF_IFAR_WIDTH{1'b0}}; + reload_addr_calc = {`REAL_IFAR_WIDTH-6{1'b0}}; + reload_way_calc = 4'b0; + lru_write_addr_calc = 7'b0; + lru_write_way_calc = 4'b0; + r3_addr_calc = 7'b0; + r3_way_calc = 4'b0; + row_match_way_calc = 4'b0; + + for (i = 0; i < TAGS_USED; i = i + 1) + begin + r0_addr_calc = r0_addr_calc | + {10{reld_r0_tag[i]}} & {miss_addr_eff_l2[i][50:51], miss_addr_real_l2[i][52:59]}; + lru_addr_calc = lru_addr_calc | + {7{reld_r1_val_l2[i]}} & miss_addr_real_l2[i][51:57]; + load_addr_calc = load_addr_calc | + {`EFF_IFAR_WIDTH{reld_r2_val_l2[i]}} & {miss_addr_eff_l2[i], miss_addr_real_l2[i][52:61]}; + reload_addr_calc = reload_addr_calc | + {`REAL_IFAR_WIDTH-6{reld_r2_val_l2[i]}} & miss_addr_real_l2[i][64 - `REAL_IFAR_WIDTH:57]; + reload_way_calc = reload_way_calc | + {4{reld_r2_val_l2[i]}} & miss_way_l2[i]; + lru_write_addr_calc = lru_write_addr_calc | + {7{lru_write_l2[i]}} & miss_addr_real_l2[i][51:57]; + lru_write_way_calc = lru_write_way_calc | + {4{lru_write_l2[i]}} & miss_way_l2[i]; + r3_addr_calc = r3_addr_calc | + {7{reld_r3_val_l2[i]}} & miss_addr_real_l2[i][51:57]; + r3_way_calc = r3_way_calc | + {4{reld_r3_val_l2[i]}} & miss_way_l2[i]; + row_match_way_calc = row_match_way_calc | + {4{row_match[i]}} & miss_way_l2[i]; + end + r0_addr = r0_addr_calc; + lru_addr = lru_addr_calc; + load_addr = load_addr_calc; + reload_addr = reload_addr_calc; + reload_way = reload_way_calc; + lru_write_addr = lru_write_addr_calc; + lru_write_way = lru_write_way_calc; + r3_addr = r3_addr_calc; + r3_way = r3_way_calc; + row_match_way = row_match_way_calc; + end + + //--------------------------------------------------------------------- + // fastpath-related signals + //--------------------------------------------------------------------- + // for first beat of data: create hole in IU0 so we can fastpath data into IU2 + assign preload_r0_tag = r0_crit_qw & reld_r0_tag & (~miss_block_fp_l2) & (~miss_flushed_l2[0:TAGS_USED - 1]); + + generate + begin : xhdl13 + genvar i; + for (i = 0; i < `THREADS; i = i + 1) + begin : gen_preload_r0_tid + assign preload_r0_tid[i] = preload_r0_tag[2*i] | preload_r0_tag[2*i+1]; + end + end + endgenerate + + assign preload_hold_iu0 = {`THREADS{reld_r0_vld}} & preload_r0_tid; + + assign icm_ics_iu0_preload_val = preload_hold_iu0; + assign icm_ics_iu0_preload_ifar = r0_addr; + + assign load_2ucode = |(reld_r2_val_l2 & miss_2ucode_l2); + assign load_2ucode_type = |(reld_r2_val_l2 & miss_2ucode_type_l2); + assign load_tag_no_block = load_tag[0:TAGS_USED - 1] & (~miss_block_fp_l2[0:TAGS_USED - 1]); + + generate + begin : xhdl14 + genvar i; + for (i = 0; i < `THREADS; i = i + 1) + begin : gen_load_tid + assign load_tid_no_block[i] = load_tag_no_block[2*i] | load_tag_no_block[2*i+1]; + end + end + endgenerate + + assign icm_icd_load = load_tid_no_block; + assign icm_icd_load_addr = load_addr; + assign icm_icd_load_2ucode = load_2ucode; + assign icm_icd_load_2ucode_type = load_2ucode_type; + + assign r3_loaded_d = |(load_tid_no_block); + + //--------------------------------------------------------------------- + // Critical Quadword + //--------------------------------------------------------------------- + // Note: Could latch reld_crit_qw signal from L2, but we need addr (60:61), so might as well keep whole address + generate + begin : xhdl15 + genvar i; + for (i = 0; i < TAGS_USED; i = i + 1) + begin : gen_crit_qw + assign r0_crit_qw[i] = an_ac_reld_qw_l2[58:59] == miss_addr_real_l2[i][58:59]; + assign r1_crit_qw[i] = reld_r1_qw_l2 == miss_addr_real_l2[i][58:59]; + end + end + endgenerate + + assign r2_crit_qw_d = |(r1_crit_qw & reld_r1_val_l2[0:TAGS_USED - 1]); + + //--------------------------------------------------------------------- + // Get LRU + //--------------------------------------------------------------------- + // ??? Might have to read in r0 + + assign lru_write_hit = |(lru_write) & (lru_addr[51:56] == lru_write_addr[51:56]) & + (spr_ic_cls_l2 | (lru_addr[57] == lru_write_addr[57])); + + assign hit_lru = ({3{lru_write_way[0]}} & {2'b11, icd_icm_row_lru[2]}) | + ({3{lru_write_way[1]}} & {2'b10, icd_icm_row_lru[2]}) | + ({3{lru_write_way[2]}} & {1'b0, icd_icm_row_lru[1], 1'b1}) | + ({3{lru_write_way[3]}} & {1'b0, icd_icm_row_lru[1], 1'b0}); + + assign row_lru = (lru_write_hit == 1'b0) ? icd_icm_row_lru : + hit_lru; + + generate + begin : xhdl16 + genvar i; + for (i = 0; i < TAGS_USED; i = i + 1) + begin : gen_lru + // Select_lru in r1 + assign select_lru[i] = (~miss_ci_l2[i]) & reld_r1_val_l2[i] & (miss_tid_sm_l2[i][WAITSTATE] & no_data[i]) & (~miss_flushed_l2[i]) & (~miss_inval_l2[i]); + + // lru/way is valid in Data0-3, Wait1-3, CheckECC + // lru_valid() <= (miss_tid_sm_l2(3) or miss_tid_sm_l2(4) or miss_tid_sm_l2(5) or miss_tid_sm_l2(6) or + // miss_tid_sm_l2(8) or miss_tid_sm_l2(9) or miss_tid_sm_l2(10) or miss_tid_sm_l2(11) ) and not miss_flushed_l2 and not miss_inval_l2; + assign lru_valid[i] = (~(miss_tid_sm_l2[i][IDLE] | miss_tid_sm_l2[i][WAITMISS] | (miss_tid_sm_l2[i][WAITSTATE] & no_data[i]) | miss_flushed_l2[i] | miss_inval_l2[i] | miss_ci_l2[i])); + + // check if any other thread is writing into this spot in the cache + assign row_match[i] = lru_valid[i] & (lru_addr[51:56] == miss_addr_real_l2[i][51:56]) & (spr_ic_cls_l2 | (lru_addr[57] == miss_addr_real_l2[i][57])); + end + end + endgenerate + + assign val_or_match = icd_icm_row_val | row_match_way; + + // Old: Use if can never hit more than one entry, since only two reloads are in data mode at a time + //?TABLE select_lru_way LISTING(final) OPTIMIZE PARMS(ON-SET, OFF-SET); + //*INPUTS*=================*OUTPUTS*======* + //| | | + //| row_match_way | | + //| | row_lru | | + //| | | | next_lru_way | + //| | | | | | + //| | | | | | + //| 0123 012 | 0123 | + //*TYPE*===================+==============+ + //| PPPP PPP | PPPP | + //*TERMS*==================+==============+ + //| 0--- 00- | 1000 | + //| 1--- 000 | 0010 | + //| 1--- 001 | 0001 | + //| | | + //| -0-- 01- | 0100 | + //| -1-- 010 | 0010 | + //| -1-- 011 | 0001 | + //| | | + //| --0- 1-0 | 0010 | + //| --1- 100 | 1000 | + //| --1- 110 | 0100 | + //| | | + //| ---0 1-1 | 0001 | + //| ---1 101 | 1000 | + //| ---1 111 | 0100 | + //*END*====================+==============+ + //?TABLE END select_lru_way; + + // Could have all 4 tags going to same row +/* +//table_start +?TABLE select_lru_way LISTING(final) OPTIMIZE PARMS(ON-SET, OFF-SET); +*INPUTS*=================*OUTPUTS*======* +| | | +| row_lru | | +| | row_match_way | | +| | | | next_lru_way | +| | | | | | +| | | | | | +| 012 0123 | 0123 | +*TYPE*===================+==============+ +| PPP PPPP | PPPP | +*TERMS*==================+==============+ +| 00- 0--- | 1000 | +| 000 1-0- | 0010 | +| 000 101- | 0100 | +| 000 111- | 0001 | +| 001 1--0 | 0001 | +| 001 10-1 | 0100 | +| 001 11-1 | 0010 | +| | | +| 01- -0-- | 0100 | +| 010 -10- | 0010 | +| 010 011- | 1000 | +| 010 111- | 0001 | +| 011 -1-0 | 0001 | +| 011 01-1 | 1000 | +| 011 11-1 | 0010 | +| | | +| 1-0 --0- | 0010 | +| 100 0-1- | 1000 | +| 100 1-10 | 0001 | +| 100 1-11 | 0100 | +| 110 -01- | 0100 | +| 110 -110 | 0001 | +| 110 -111 | 1000 | +| | | +| 1-1 ---0 | 0001 | +| 101 0--1 | 1000 | +| 101 1-01 | 0010 | +| 101 1-11 | 0100 | +| 111 -0-1 | 0100 | +| 111 -101 | 0010 | +| 111 -111 | 1000 | +*END*====================+==============+ +?TABLE END select_lru_way; +//table_end +*/ + +//assign_start + +assign select_lru_way_pt[1] = + (({ row_lru[0] , row_lru[2] , + row_match_way[0] , row_match_way[1] , + row_match_way[3] }) === 5'b01011); +assign select_lru_way_pt[2] = + (({ row_lru[0] , row_lru[2] , + row_match_way[0] , row_match_way[1] , + row_match_way[2] }) === 5'b00011); +assign select_lru_way_pt[3] = + (({ row_lru[0] , row_lru[2] , + row_match_way[0] , row_match_way[1] , + row_match_way[3] }) === 5'b01101); +assign select_lru_way_pt[4] = + (({ row_lru[0] , row_lru[2] , + row_match_way[0] , row_match_way[1] , + row_match_way[2] }) === 5'b00101); +assign select_lru_way_pt[5] = + (({ row_lru[0] , row_lru[1] , + row_match_way[1] , row_match_way[2] , + row_match_way[3] }) === 5'b11101); +assign select_lru_way_pt[6] = + (({ row_lru[0] , row_lru[1] , + row_match_way[0] , row_match_way[2] , + row_match_way[3] }) === 5'b10101); +assign select_lru_way_pt[7] = + (({ row_lru[0] , row_lru[1] , + row_match_way[1] , row_match_way[2] , + row_match_way[3] }) === 5'b11110); +assign select_lru_way_pt[8] = + (({ row_lru[0] , row_lru[1] , + row_match_way[0] , row_match_way[2] , + row_match_way[3] }) === 5'b10110); +assign select_lru_way_pt[9] = + (({ row_lru[0] , row_lru[1] , + row_match_way[1] , row_match_way[2] , + row_match_way[3] }) === 5'b11111); +assign select_lru_way_pt[10] = + (({ row_lru[0] , row_lru[1] , + row_match_way[0] , row_match_way[2] , + row_match_way[3] }) === 5'b10111); +assign select_lru_way_pt[11] = + (({ row_lru[0] , row_lru[2] , + row_match_way[0] , row_match_way[1] , + row_match_way[3] }) === 5'b01111); +assign select_lru_way_pt[12] = + (({ row_lru[0] , row_lru[2] , + row_match_way[0] , row_match_way[1] , + row_match_way[2] }) === 5'b00111); +assign select_lru_way_pt[13] = + (({ row_lru[1] , row_lru[2] , + row_match_way[0] , row_match_way[3] + }) === 4'b0101); +assign select_lru_way_pt[14] = + (({ row_lru[1] , row_lru[2] , + row_match_way[0] , row_match_way[2] + }) === 4'b0001); +assign select_lru_way_pt[15] = + (({ row_lru[1] , row_lru[2] , + row_match_way[1] , row_match_way[3] + }) === 4'b1101); +assign select_lru_way_pt[16] = + (({ row_lru[1] , row_lru[2] , + row_match_way[1] , row_match_way[2] + }) === 4'b1001); +assign select_lru_way_pt[17] = + (({ row_lru[1] , row_lru[2] , + row_match_way[1] , row_match_way[2] + }) === 4'b1010); +assign select_lru_way_pt[18] = + (({ row_lru[1] , row_lru[2] , + row_match_way[0] , row_match_way[2] + }) === 4'b0010); +assign select_lru_way_pt[19] = + (({ row_lru[1] , row_lru[2] , + row_match_way[1] , row_match_way[3] + }) === 4'b1110); +assign select_lru_way_pt[20] = + (({ row_lru[1] , row_lru[2] , + row_match_way[0] , row_match_way[3] + }) === 4'b0110); +assign select_lru_way_pt[21] = + (({ row_lru[0] , row_lru[1] , + row_match_way[0] }) === 3'b000); +assign select_lru_way_pt[22] = + (({ row_lru[0] , row_lru[1] , + row_match_way[1] }) === 3'b010); +assign select_lru_way_pt[23] = + (({ row_lru[0] , row_lru[2] , + row_match_way[2] }) === 3'b100); +assign select_lru_way_pt[24] = + (({ row_lru[0] , row_lru[2] , + row_match_way[3] }) === 3'b110); +assign next_lru_way[0] = + (select_lru_way_pt[1] | select_lru_way_pt[2] + | select_lru_way_pt[9] | select_lru_way_pt[13] + | select_lru_way_pt[14] | select_lru_way_pt[21] + ); +assign next_lru_way[1] = + (select_lru_way_pt[3] | select_lru_way_pt[4] + | select_lru_way_pt[10] | select_lru_way_pt[15] + | select_lru_way_pt[16] | select_lru_way_pt[22] + ); +assign next_lru_way[2] = + (select_lru_way_pt[5] | select_lru_way_pt[6] + | select_lru_way_pt[11] | select_lru_way_pt[17] + | select_lru_way_pt[18] | select_lru_way_pt[23] + ); +assign next_lru_way[3] = + (select_lru_way_pt[7] | select_lru_way_pt[8] + | select_lru_way_pt[12] | select_lru_way_pt[19] + | select_lru_way_pt[20] | select_lru_way_pt[24] + ); + +//assign_end + + assign next_way = (val_or_match[0] == 1'b0) ? 4'b1000 : + (val_or_match[1] == 1'b0) ? 4'b0100 : + (val_or_match[2] == 1'b0) ? 4'b0010 : + (val_or_match[3] == 1'b0) ? 4'b0001 : + next_lru_way; + + generate + begin : xhdl17 + genvar i; + for (i = 0; i < TAGS_USED; i = i + 1) + begin : gen_miss_way + assign miss_way_d[i] = (select_lru[i] == 1'b1) ? next_way : + miss_way_l2[i]; + end + end + endgenerate + + //--------------------------------------------------------------------- + // setting output signals + //--------------------------------------------------------------------- + generate + begin : xhdl18 + genvar i; + for (i = 0; i < `THREADS ; i = i + 1) + begin : gen_hold_thread + assign icm_ics_hold_thread[i] = ((hold_tid[2*i] | ecc_block_iu0[2*i]) & miss_need_hold_l2[2*i]) | ((hold_tid[2*i+1] | ecc_block_iu0[2*i+1]) & miss_need_hold_l2[2*i+1]); + end + end + endgenerate + + // Note: If data_write timing is bad, can switch back to using hold_all_tids, but use reld_r2 + // Hold iu0 when writing into Data this cycle or fastpath 2 cycles from now. + // For reld in Wait0, not checking flush for timing reasons. + assign hold_iu0 = |(data_write) | (|(preload_hold_iu0)); + + assign icm_ics_hold_iu0 = hold_iu0; + assign icm_icd_lru_addr = lru_addr; + assign icm_icd_data_write = |(data_write); + assign icm_icd_dir_inval = |(write_dir_inval); + + // ??? Move inval_equal for timing? + assign icm_icd_dir_val = | (write_dir_val[0:TAGS_USED - 1] & miss_wrote_dir_l2 & (~inval_equal)); + + assign icm_icd_reload_addr = {reload_addr[51:57], reld_r2_qw_l2}; + assign icm_icd_reload_way = reload_way; + + // Check which endian + assign reload_endian = | (reld_r2_val_l2 & miss_endian_l2); + assign reld_r1_endian = | (reld_r1_val_l2[0:TAGS_USED - 1] & miss_endian_l2); + + assign swap_endian_data = + {an_ac_reld_data[24:31], an_ac_reld_data[16:23], an_ac_reld_data[8:15], an_ac_reld_data[0:7], + an_ac_reld_data[56:63], an_ac_reld_data[48:55], an_ac_reld_data[40:47], an_ac_reld_data[32:39], + an_ac_reld_data[88:95], an_ac_reld_data[80:87], an_ac_reld_data[72:79], an_ac_reld_data[64:71], + an_ac_reld_data[120:127], an_ac_reld_data[112:119], an_ac_reld_data[104:111], an_ac_reld_data[96:103]}; + + assign reld_data_d = (reld_r1_endian == 1'b0) ? an_ac_reld_data : + swap_endian_data; + + // Branch Decode + iuq_bd br_decode0( + .instruction(reld_data_l2[0:31]), + .instruction_next(reld_data_l2[32:63]), + .branch_decode(branch_decode0[0:3]), + .bp_bc_en(bp_config_l2[0]), + .bp_bclr_en(bp_config_l2[1]), + .bp_bcctr_en(bp_config_l2[2]), + .bp_sw_en(bp_config_l2[3]) + ); + + iuq_bd br_decode1( + .instruction(reld_data_l2[32:63]), + .instruction_next(reld_data_l2[64:95]), + .branch_decode(branch_decode1[0:3]), + .bp_bc_en(bp_config_l2[0]), + .bp_bclr_en(bp_config_l2[1]), + .bp_bcctr_en(bp_config_l2[2]), + .bp_sw_en(bp_config_l2[3]) + ); + + iuq_bd br_decode2( + .instruction(reld_data_l2[64:95]), + .instruction_next(reld_data_l2[96:127]), + .branch_decode(branch_decode2[0:3]), + .bp_bc_en(bp_config_l2[0]), + .bp_bclr_en(bp_config_l2[1]), + .bp_bcctr_en(bp_config_l2[2]), + .bp_sw_en(bp_config_l2[3]) + ); + + iuq_bd br_decode3( + .instruction(reld_data_l2[96:127]), + .instruction_next(tidn32[0:31]), + .branch_decode(branch_decode3[0:3]), + .bp_bc_en(bp_config_l2[0]), + .bp_bclr_en(bp_config_l2[1]), + .bp_bcctr_en(bp_config_l2[2]), + .bp_sw_en(bp_config_l2[3]) + ); + + assign instr_data = {reld_data_l2[0:31], branch_decode0[0:3], + reld_data_l2[32:63], branch_decode1[0:3], + reld_data_l2[64:95], branch_decode2[0:3], + reld_data_l2[96:127], branch_decode3[0:3]}; + + assign icm_icd_reload_data = instr_data; + + // Dir Write moved to r2 + assign dir_write_no_block = dir_write[0:TAGS_USED - 1] & (~iu0_inval_match); + assign icm_icd_dir_write = |(dir_write_no_block); + assign icm_icd_dir_write_addr = reload_addr; + assign icm_icd_dir_write_endian = reload_endian; + assign icm_icd_dir_write_way = reload_way; + + // LRU Write: Occurs 2 cycles after Data 2 data_write (64B mode) or Data6 (128B mode) + generate + begin : xhdl19 + genvar i; + for (i = 0; i < TAGS_USED; i = i + 1) + begin : gen_lru_write + assign lru_write_next_cycle_d[i] = data_write[i] & (miss_tid_sm_l2[i][DATA] & (miss_count_l2[i] == 3'b001)); + assign lru_write[i] = lru_write_l2[i] & (~miss_inval_l2[i]); + end + end + endgenerate + + assign lru_write_d = lru_write_next_cycle_l2; + + assign icm_icd_lru_write = |(lru_write); + assign icm_icd_lru_write_addr = lru_write_addr; + assign icm_icd_lru_write_way = lru_write_way; + + // For act's in idir + assign icm_icd_any_reld_r2 = |(reld_r2_val_l2); + + //--------------------------------------------------------------------- + // ECC Error handling + //--------------------------------------------------------------------- + assign new_ecc_err = {TAGS_USED{an_ac_reld_ecc_err_l2}} & reld_r3_val_l2; + assign new_ecc_err_ue = {TAGS_USED{an_ac_reld_ecc_err_ue_l2}} & reld_r3_val_l2; + assign ecc_err[0:TAGS_USED - 1] = new_ecc_err | miss_ecc_err_l2; + assign ecc_err_ue[0:TAGS_USED - 1] = new_ecc_err_ue | miss_ecc_err_ue_l2; + + generate + begin : xhdl20 + genvar i; + for (i = 0; i < TAGS_USED; i = i + 1) + begin : gen_ecc_inval + assign ecc_inval[i] = (an_ac_reld_ecc_err_l2 | an_ac_reld_ecc_err_ue_l2 | inval_equal[i]) & + miss_tid_sm_l2[i][CHECK_ECC] & (~miss_ci_l2[i]) & (~miss_flushed_l2[i]) & (~miss_inval_l2[i]); + assign ecc_block_iu0[i] = ecc_err[i] & (miss_tid_sm_l2[i][CHECK_ECC] | (miss_tid_sm_l2[i][DATA] & last_data[i])); // moved last data check here from hold_tid for timing; check need_hold in hold_thread logic + end + end + endgenerate + + // CheckECC stage + // Non-CI: If last beat of data has bad ECC, invalidate cache & flush IU1 + + // Back inval in Check ECC state + assign icm_icd_ecc_inval = |(ecc_inval); //or back_inval_check_ecc; + + assign icm_icd_ecc_addr = r3_addr[51:57]; + assign icm_icd_ecc_way = r3_way; + + // CI/Critical QW: Invalidate IU3 or set error bit + assign ecc_fp = r3_loaded_l2 & an_ac_reld_ecc_err_l2; + assign icm_icd_iu3_ecc_fp_cancel = ecc_fp; + assign icm_ics_iu3_ecc_fp_cancel = {`THREADS{ecc_fp}} & reld_r3_tid; + assign ic_bp_iu3_ecc_err = r3_loaded_l2 & an_ac_reld_ecc_err_ue_l2; + + //--------------------------------------------------------------------- + // Performance Events + //--------------------------------------------------------------------- + generate + begin : xhdl11 + genvar i; + for (i = 0; i < SM_MAX; i = i + 1) + begin : g11 + // - not CI, not Idle, not WaitMiss, & not (CheckECC & done) + assign active_l1_miss[i] = ~miss_ci_l2[i] & ~miss_tid_sm_l2[i][IDLE] & ~miss_tid_sm_l2[i][WAITMISS] & ~(miss_tid_sm_l2[i][CHECK_ECC] & ~ecc_err[i]); + end + + genvar t; + for (t = 0; t < `THREADS; t = t + 1) + begin : gen_perf + // IL1 Miss Cycles + // - not CI, not Idle, not WaitMiss, & not (CheckECC & done) + // - event mode/edge should not count multiple times if flushed and recycled + assign perf_event_d[t][0] = active_l1_miss[2*t] | (active_l1_miss[2*t+1] & ~miss_prefetch_perf_l2[t]); + + // IL1 Reload Dropped + // - not CI, flushed, & returning to Idle; includes prefetches + assign perf_event_d[t][1] = + (~miss_ci_l2[2*t] & miss_flushed_l2[2*t] & (miss_tid_sm_l2[2*t][CHECK_ECC] & ~ecc_err[2*t])) | + (~miss_ci_l2[2*t+1] & miss_flushed_l2[2*t+1] & (miss_tid_sm_l2[2*t+1][CHECK_ECC] & ~ecc_err[2*t+1])); + + // Prefetch cycles + assign perf_event_d[t][2] = active_l1_miss[2*t+1] & miss_prefetch_perf_l2[t]; + end + end + endgenerate + + assign ic_perf_t0_event = perf_event_l2[0]; + `ifndef THREADS1 + assign ic_perf_t1_event = perf_event_l2[1]; + `endif + + //--------------------------------------------------------------------- + // Latches + //--------------------------------------------------------------------- + + tri_rlmlatch_p #(.INIT(0)) spr_ic_cls_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(default_reld_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[spr_ic_cls_offset]), + .scout(sov[spr_ic_cls_offset]), + .din(spr_ic_cls_d), + .dout(spr_ic_cls_l2) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) bp_config_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(default_reld_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[bp_config_offset:bp_config_offset + 4 - 1]), + .scout(sov[bp_config_offset:bp_config_offset + 4 - 1]), + .din(bp_config_d), + .dout(bp_config_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) an_ac_reld_data_vld_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(default_reld_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[an_ac_reld_data_vld_offset]), + .scout(sov[an_ac_reld_data_vld_offset]), + .din(an_ac_reld_data_vld_d), + .dout(an_ac_reld_data_vld_l2) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(0)) an_ac_reld_core_tag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(default_reld_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[an_ac_reld_core_tag_offset:an_ac_reld_core_tag_offset + 5 - 1]), + .scout(sov[an_ac_reld_core_tag_offset:an_ac_reld_core_tag_offset + 5 - 1]), + .din(an_ac_reld_core_tag_d), + .dout(an_ac_reld_core_tag_l2) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) an_ac_reld_qw_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(default_reld_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[an_ac_reld_qw_offset:an_ac_reld_qw_offset + 2 - 1]), + .scout(sov[an_ac_reld_qw_offset:an_ac_reld_qw_offset + 2 - 1]), + .din(an_ac_reld_qw_d), + .dout(an_ac_reld_qw_l2) + ); + + tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0)) reld_r1_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(default_reld_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[reld_r1_val_offset:reld_r1_val_offset + TAGS_USED - 1]), + .scout(sov[reld_r1_val_offset:reld_r1_val_offset + TAGS_USED - 1]), + .din(reld_r1_val_d), + .dout(reld_r1_val_l2[0:TAGS_USED - 1]) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) reld_r1_qw_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(default_reld_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[reld_r1_qw_offset:reld_r1_qw_offset + 2 - 1]), + .scout(sov[reld_r1_qw_offset:reld_r1_qw_offset + 2 - 1]), + .din(reld_r1_qw_d), + .dout(reld_r1_qw_l2) + ); + + tri_rlmreg_p #(.WIDTH(128), .INIT(0)) reld_data_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(reld_r2_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[reld_data_offset:reld_data_offset + 128 - 1]), + .scout(sov[reld_data_offset:reld_data_offset + 128 - 1]), + .din(reld_data_d), + .dout(reld_data_l2) + ); + + tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0)) reld_r2_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(default_reld_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[reld_r2_val_offset:reld_r2_val_offset + TAGS_USED - 1]), + .scout(sov[reld_r2_val_offset:reld_r2_val_offset + TAGS_USED - 1]), + .din(reld_r2_val_d), + .dout(reld_r2_val_l2) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) reld_r2_qw_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(reld_r2_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[reld_r2_qw_offset:reld_r2_qw_offset + 2 - 1]), + .scout(sov[reld_r2_qw_offset:reld_r2_qw_offset + 2 - 1]), + .din(reld_r2_qw_d), + .dout(reld_r2_qw_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) r2_crit_qw_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(default_reld_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[r2_crit_qw_offset]), + .scout(sov[r2_crit_qw_offset]), + .din(r2_crit_qw_d), + .dout(r2_crit_qw_l2) + ); + + tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0)) reld_r3_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(default_reld_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[reld_r3_val_offset:reld_r3_val_offset + TAGS_USED - 1]), + .scout(sov[reld_r3_val_offset:reld_r3_val_offset + TAGS_USED - 1]), + .din(reld_r3_val_d), + .dout(reld_r3_val_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) r3_loaded_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(default_reld_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[r3_loaded_offset]), + .scout(sov[r3_loaded_offset]), + .din(r3_loaded_d), + .dout(r3_loaded_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) an_ac_reld_ecc_err_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(default_reld_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[an_ac_reld_ecc_err_offset]), + .scout(sov[an_ac_reld_ecc_err_offset]), + .din(an_ac_reld_ecc_err_d), + .dout(an_ac_reld_ecc_err_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) an_ac_reld_ecc_err_ue_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(default_reld_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[an_ac_reld_ecc_err_ue_offset]), + .scout(sov[an_ac_reld_ecc_err_ue_offset]), + .din(an_ac_reld_ecc_err_ue_d), + .dout(an_ac_reld_ecc_err_ue_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) request_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(miss_or_default_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[request_offset:request_offset + `THREADS - 1]), + .scout(sov[request_offset:request_offset + `THREADS - 1]), + .din(request_d), + .dout(request_l2) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) req_ctag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(icd_icm_any_iu2_valid), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[req_ctag_offset:req_ctag_offset + 2 - 1]), + .scout(sov[req_ctag_offset:req_ctag_offset + 2 - 1]), + .din(req_ctag_d), + .dout(req_ctag_l2) + ); + + tri_rlmreg_p #(.WIDTH(`REAL_IFAR_WIDTH-4), .INIT(0)) req_ra_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(icd_icm_any_iu2_valid), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[req_ra_offset:req_ra_offset + (`REAL_IFAR_WIDTH-4) - 1]), + .scout(sov[req_ra_offset:req_ra_offset + (`REAL_IFAR_WIDTH-4) - 1]), + .din(req_ra_d), + .dout(req_ra_l2) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(0)) req_wimge_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(icd_icm_any_iu2_valid), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[req_wimge_offset:req_wimge_offset + 5 - 1]), + .scout(sov[req_wimge_offset:req_wimge_offset + 5 - 1]), + .din(req_wimge_d), + .dout(req_wimge_l2) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) req_userdef_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(icd_icm_any_iu2_valid), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[req_userdef_offset:req_userdef_offset + 4 - 1]), + .scout(sov[req_userdef_offset:req_userdef_offset + 4 - 1]), + .din(req_userdef_d), + .dout(req_userdef_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) iu3_miss_match_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(icd_icm_any_iu2_valid), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu3_miss_match_offset]), + .scout(sov[iu3_miss_match_offset]), + .din(iu3_miss_match_d), + .dout(iu3_miss_match_l2) + ); + + generate + begin : xhdl21 + genvar i; + for (i = 0; i < TAGS_USED; i = i + 1) + begin : gen_sm + + tri_rlmreg_p #(.WIDTH(CHECK_ECC+1), .INIT({1'b1, {CHECK_ECC{1'b0}} })) miss_tid_sm_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(miss_or_default_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[miss_tid_sm_offset + i * (CHECK_ECC+1):miss_tid_sm_offset + (i + 1) * (CHECK_ECC+1) - 1]), + .scout(sov[miss_tid_sm_offset + i * (CHECK_ECC+1):miss_tid_sm_offset + (i + 1) * (CHECK_ECC+1) - 1]), + .din(miss_tid_sm_d[i]), + .dout(miss_tid_sm_l2[i]) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) miss_count_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(miss_or_default_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[miss_count_offset + i * 3:miss_count_offset + (i + 1) * 3 - 1]), + .scout(sov[miss_count_offset + i * 3:miss_count_offset + (i + 1) * 3 - 1]), + .din(miss_count_d[i]), + .dout(miss_count_l2[i]) + ); + end + end + endgenerate + + tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0)) miss_flush_occurred_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(default_reld_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[miss_flush_occurred_offset:miss_flush_occurred_offset + TAGS_USED - 1]), + .scout(sov[miss_flush_occurred_offset:miss_flush_occurred_offset + TAGS_USED - 1]), + .din(miss_flush_occurred_d), + .dout(miss_flush_occurred_l2) + ); + + tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0)) miss_flushed_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(default_reld_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[miss_flushed_offset:miss_flushed_offset + TAGS_USED - 1]), + .scout(sov[miss_flushed_offset:miss_flushed_offset + TAGS_USED - 1]), + .din(miss_flushed_d[0:TAGS_USED - 1]), + .dout(miss_flushed_l2[0:TAGS_USED - 1]) + ); + + tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0)) miss_inval_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(default_reld_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[miss_inval_offset:miss_inval_offset + TAGS_USED - 1]), + .scout(sov[miss_inval_offset:miss_inval_offset + TAGS_USED - 1]), + .din(miss_inval_d[0:TAGS_USED - 1]), + .dout(miss_inval_l2[0:TAGS_USED - 1]) + ); + + tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0)) miss_block_fp_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(miss_or_default_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[miss_block_fp_offset:miss_block_fp_offset + TAGS_USED - 1]), + .scout(sov[miss_block_fp_offset:miss_block_fp_offset + TAGS_USED - 1]), + .din(miss_block_fp_d), + .dout(miss_block_fp_l2) + ); + + tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0)) miss_ecc_err_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(default_reld_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[miss_ecc_err_offset:miss_ecc_err_offset + TAGS_USED - 1]), + .scout(sov[miss_ecc_err_offset:miss_ecc_err_offset + TAGS_USED - 1]), + .din(miss_ecc_err_d), + .dout(miss_ecc_err_l2) + ); + + tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0)) miss_ecc_err_ue_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(default_reld_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[miss_ecc_err_ue_offset:miss_ecc_err_ue_offset + TAGS_USED - 1]), + .scout(sov[miss_ecc_err_ue_offset:miss_ecc_err_ue_offset + TAGS_USED - 1]), + .din(miss_ecc_err_ue_d), + .dout(miss_ecc_err_ue_l2) + ); + + tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0), .NEEDS_SRESET(1)) miss_wrote_dir_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(default_reld_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[miss_wrote_dir_offset:miss_wrote_dir_offset + TAGS_USED - 1]), + .scout(sov[miss_wrote_dir_offset:miss_wrote_dir_offset + TAGS_USED - 1]), + .din(miss_wrote_dir_d), + .dout(miss_wrote_dir_l2) + ); + + tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0), .NEEDS_SRESET(1)) miss_need_hold_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(miss_or_default_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[miss_need_hold_offset:miss_need_hold_offset + TAGS_USED - 1]), + .scout(sov[miss_need_hold_offset:miss_need_hold_offset + TAGS_USED - 1]), + .din(miss_need_hold_d), + .dout(miss_need_hold_l2) + ); + + generate + begin : xhdl22 + genvar i; + for (i = 0; i < TAGS_USED; i = i + 1) + begin : gen + tri_rlmreg_p #(.WIDTH(`REAL_IFAR_WIDTH - 2), .INIT(0)) miss_addr_real_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(miss_act[i]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[miss_addr_real_offset + i * (`REAL_IFAR_WIDTH - 2):miss_addr_real_offset + (i + 1) * (`REAL_IFAR_WIDTH - 2) - 1]), + .scout(sov[miss_addr_real_offset + i * (`REAL_IFAR_WIDTH - 2):miss_addr_real_offset + (i + 1) * (`REAL_IFAR_WIDTH - 2) - 1]), + .din(miss_addr_real_d[i]), + .dout(miss_addr_real_l2[i]) + ); + + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH - 10), .INIT(0)) miss_addr_eff_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(miss_act[i]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[miss_addr_eff_offset + i * (`EFF_IFAR_WIDTH - 10):miss_addr_eff_offset + (i + 1) * (`EFF_IFAR_WIDTH - 10) - 1]), + .scout(sov[miss_addr_eff_offset + i * (`EFF_IFAR_WIDTH - 10):miss_addr_eff_offset + (i + 1) * (`EFF_IFAR_WIDTH - 10) - 1]), + .din(miss_addr_eff_d[i]), + .dout(miss_addr_eff_l2[i]) + ); + + tri_rlmlatch_p #(.INIT(0)) miss_ci_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(miss_act[i]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[miss_ci_offset + i]), + .scout(sov[miss_ci_offset + i]), + .din(miss_ci_d[i]), + .dout(miss_ci_l2[i]) + ); + + tri_rlmlatch_p #(.INIT(0)) miss_endian_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(miss_act[i]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[miss_endian_offset + i]), + .scout(sov[miss_endian_offset + i]), + .din(miss_endian_d[i]), + .dout(miss_endian_l2[i]) + ); + + tri_rlmlatch_p #(.INIT(0)) miss_2ucode_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(miss_act[i]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[miss_2ucode_offset + i]), + .scout(sov[miss_2ucode_offset + i]), + .din(miss_2ucode_d[i]), + .dout(miss_2ucode_l2[i]) + ); + + tri_rlmlatch_p #(.INIT(0)) miss_2ucode_type_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(miss_act[i]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[miss_2ucode_type_offset + i]), + .scout(sov[miss_2ucode_type_offset + i]), + .din(miss_2ucode_type_d[i]), + .dout(miss_2ucode_type_l2[i]) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) miss_way_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(reld_r2_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[miss_way_offset + i * 4:miss_way_offset + (i + 1) * 4 - 1]), + .scout(sov[miss_way_offset + i * 4:miss_way_offset + (i + 1) * 4 - 1]), + .din(miss_way_d[i]), + .dout(miss_way_l2[i]) + ); + end + end + endgenerate + + tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0)) lru_write_next_cycle_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(default_reld_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[lru_write_next_cycle_offset:lru_write_next_cycle_offset + TAGS_USED - 1]), + .scout(sov[lru_write_next_cycle_offset:lru_write_next_cycle_offset + TAGS_USED - 1]), + .din(lru_write_next_cycle_d), + .dout(lru_write_next_cycle_l2) + ); + + tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0)) lru_write_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(default_reld_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[lru_write_offset:lru_write_offset + TAGS_USED - 1]), + .scout(sov[lru_write_offset:lru_write_offset + TAGS_USED - 1]), + .din(lru_write_d), + .dout(lru_write_l2) + ); + + generate + begin : xhdl23 + genvar i; + for (i = 0; i < `THREADS; i = i + 1) + begin : t + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) perf_event_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(event_bus_enable), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[perf_event_offset + i * 3:perf_event_offset + (i+1) * 3 - 1]), + .scout(sov[perf_event_offset + i * 3:perf_event_offset + (i+1) * 3 - 1]), + .din(perf_event_d[i]), + .dout(perf_event_l2[i]) + ); + end + end + endgenerate + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) miss_prefetch_perf_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(event_bus_enable), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[miss_prefetch_perf_offset:miss_prefetch_perf_offset + `THREADS - 1]), + .scout(sov[miss_prefetch_perf_offset:miss_prefetch_perf_offset + `THREADS - 1]), + .din(miss_prefetch_perf_d), + .dout(miss_prefetch_perf_l2) + ); + + //--------------------------------------------------------------------- + // Scan + //--------------------------------------------------------------------- + assign siv[0:scan_right] = {sov[1:scan_right], scan_in}; + assign scan_out = sov[0]; + +endmodule diff --git a/dev/verilog/work/iuq_ic_miss_table.v b/dev/verilog/work/iuq_ic_miss_table.v new file mode 100755 index 0000000..28f5e67 --- /dev/null +++ b/dev/verilog/work/iuq_ic_miss_table.v @@ -0,0 +1,277 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//******************************************************************** +//* +//* DESCRIPTION: State Machine Table for ICache Miss +//* +//* NAME: iuq_ic_miss_table.v +//* +//********************************************************************* + + +module iuq_ic_miss_table( + input new_miss, + input miss_ci_l2, + input reld_r1_val_l2, + input r2_crit_qw_l2, + input ecc_err, + input ecc_err_ue, + + input addr_match, + input iu2_flush, + input release_sm, + input miss_flushed_l2, + input miss_inval_l2, + input [0:5] miss_tid_sm_l2, + input last_data, + + output [0:5] miss_tid_sm_d, + output reset_state, + output request_tag, + output write_dir_inval, + output write_dir_val, + output hold_tid, + output data_write, + output dir_write, + output load_tag, + output release_sm_hold +); + + wire [1:23] miss_sm_pt; + + // Example State Ordering for cacheable reloads + // 64B Cacheline, No Gaps : (2)(3)(3)(3)(3)(5) - Wait, Data, Data, Data, Data, CheckECC + // 64B Cacheline, Always Gaps : (2)(3)(2)(3)(2)(3)(2)(3)(5) - Wait, Data, Wait, Data, Wait, Data, Wait, Data, CheckECC + // similar pattern for 128B +/* +//table_start +?TABLE miss_sm LISTING(final) OPTIMIZE PARMS(ON-SET, OFF-SET); +*INPUTS*=========================================*OUTPUTS*========================================* +| | | +| new_miss | miss_tid_sm_d | +| | | | | +| | | | reset_state | +| | | | | | +| | miss_ci_l2 | | | request_tag | +| | | reld_r1_val_l2 | | | | write_dir_inval | +| | | | r2_crit_qw_l2 | | | | | write_dir_val | +| | | | | ecc_err | | | | | | | +| | | | | | ecc_err_ue | | | | | | | +| | | | | | | | | | | | | | +| | | | | | | | | | | | | | +| | | | | | | addr_match | | | | | | | +| | | | | | | | iu2_flush | | | | | | hold_tid | -- this holds 1 tid and gates iu2 +| | | | | | | | | release_sm | | | | | | | | +| | | | | | | | | | miss_flushed_l2 | | | | | | | | +| | | | | | | | | | | miss_inval_l2 | | | | | | | | +| | | | | | | | | | | | miss_tid_sm_l2 | | | | | | | | +| | | | | | | | | | | | | last_data | | | | | | | | +| | | | | | | | | | | | | | | | | | | | | data_write | +| | | | | | | | | | | | | | | | | | | | | | dir_write | +| | | | | | | | | | | | | | | | | | | | | | | | +| | | | | | | | | | | | | | | | | | | | | | | load_tag | +| | | | | | | | | | | | | | | | | | | | | | | | | +| | | | | | | | | | | | | | | | | | | | | | | | release_sm_hold | +| | | | | | | | | | | | | | | | | | | | | | | | | | +| | | | | | | | | | | | | | | | | | | | | | | | | | +| | | | | | | | | | | | | | | | | | | | | | | | | | +| | | | | | | | | | | | 012345 | | 012345 | | | | | | | | | | +*TYPE*===========================================+================================================+ +| P P P P P P P P P P P PPPPPP P | PPPPPP P P P P P P P P P | +*OPTIMIZE*-------------------------------------->| AAAAAA A A A A B A A A A | +*TERMS*==========================================+================================================+ +| 0 - - - - - - 0 - - - 100000 - | 100000 0 0 0 0 0 0 0 0 0 | -- In idle and stay in idle +| 1 - - - - - 0 0 - - - 100000 - | 001000 0 1 0 0 0 0 0 0 0 | -- In idle and we got a miss for my tag not CI and no match +| 1 - - - - - 1 0 0 - - 100000 - | 010000 0 0 0 0 0 0 0 0 0 | -- In Idle miss that matches a current tag's outstanding address +| 1 - - - - - 1 0 1 - - 100000 - | 100000 0 0 0 0 0 0 0 0 0 | -- In Idle miss that matches a current tag's outstanding address, release_sm +| - - - - - - - 1 - - - 100000 - | 100000 0 0 0 0 0 0 0 0 0 | -- Flush while in idle +| | | +| - - - - - - - 0 0 - - 010000 - | 010000 0 0 0 0 1 0 0 0 0 | -- (1) In WaitMiss no valid stay in WaitMiss +| - - - - - - - 0 1 - - 010000 - | 100000 0 0 0 0 1 0 0 0 0 | -- (1) In WaitMiss got a valid to another tag, release hold +| - - - - - - - 1 - - - 010000 - | 100000 0 0 0 0 1 0 0 0 0 | -- (1) In WaitMiss and flushed, go to idle +| | | +| - - 0 - - - - - - - - 001000 - | 001000 0 0 0 0 1 0 0 0 0 | -- (2) In Wait0 no valid to tag, stay in wait0 +| - 0 1 - - - - - - - - 001000 - | 000100 0 0 0 0 1 0 0 0 0 | -- (2) In Wait0 Got a valid command and not CI +| - 1 1 - - - - - - - - 001000 - | 000010 0 0 0 0 1 0 0 0 0 | -- (2) In Wait0 Got a valid command and CI +| | | +| - - 0 1 - - - - - 0 0 000100 0 | 001000 0 0 1 0 1 1 1 1 0 | -- (3) In Data0 no valid, goto Wait1 - Crit QW +| - - 1 1 - - - - - 0 0 000100 0 | 000100 0 0 1 0 1 1 1 1 0 | -- (3) In Data0 valid, goto Data1 - Crit QW +| - - 0 0 - - - - - 0 0 000100 0 | 001000 0 0 1 0 1 1 1 0 0 | -- (3) In Data0 no valid, goto Wait1 +| - - 1 0 - - - - - 0 0 000100 0 | 000100 0 0 1 0 1 1 1 0 0 | -- (3) In Data0 valid, goto Data1 +| - - 0 - - - - - - 1 - 000100 0 | 001000 0 0 0 0 1 0 0 0 0 | -- (3) In Data0 no valid, goto Wait1; Flushed +| - - 1 - - - - - - 1 - 000100 0 | 000100 0 0 0 0 1 0 0 0 0 | -- (3) In Data0 valid, goto Data1; Flushed +| - - 0 0 - - - - - 0 1 000100 0 | 001000 0 0 0 0 1 0 0 0 0 | -- (3) In Data0 no valid, goto Wait1; Invalidated - don't cache +| - - 1 0 - - - - - 0 1 000100 0 | 000100 0 0 0 0 1 0 0 0 0 | -- (3) In Data0 valid, goto Data1; Invalidated - don't cache +| - - 0 1 - - - - - 0 1 000100 0 | 001000 0 0 0 0 1 0 0 1 0 | -- (3) In Data0 no valid, goto Wait1; Invalidated - don't cache +| - - 1 1 - - - - - 0 1 000100 0 | 000100 0 0 0 0 1 0 0 1 0 | -- (3) In Data0 valid, goto Data1; Invalidated - don't cache +| | | +| - - 0 1 0 0 - - - 0 0 000100 1 | 000001 0 0 0 1 0 1 0 1 1 | -- (3) In Data3/7 goto CheckECC - Crit QW +| - - 0 0 0 0 - - - 0 0 000100 1 | 000001 0 0 0 1 0 1 0 0 1 | -- (3) In Data3/7 goto CheckECC +| - - 0 1 1 - - - - 0 0 000100 1 | 000001 0 0 0 0 0 1 0 1 1 | -- (3) In Data3/7 ECC don't write dir; goto CheckECC - Crit QW +| - - 0 0 1 - - - - 0 0 000100 1 | 000001 0 0 0 0 0 1 0 0 1 | -- (3) In Data3/7 ECC don't write dir; goto CheckECC +| - - 0 1 - 1 - - - 0 0 000100 1 | 000001 0 0 0 0 0 1 0 1 1 | -- (3) In Data3/7 UE don't write dir; goto CheckECC - Crit QW +| - - 0 0 - 1 - - - 0 0 000100 1 | 000001 0 0 0 0 0 1 0 0 1 | -- (3) In Data3/7 UE don't write dir; goto CheckECC +| - - 0 - - - - - - 1 - 000100 1 | 000001 0 0 0 0 0 0 0 0 1 | -- (3) In Data3/7 goto CheckECC; Flushed +| - - 0 0 - - - - - 0 1 000100 1 | 000001 0 0 0 0 0 0 0 0 1 | -- (3) In Data3/7 goto CheckECC; Invalidated +| - - 0 1 - - - - - 0 1 000100 1 | 000001 0 0 0 0 0 0 0 1 1 | -- (3) In Data3/7 goto CheckECC; Invalidated +| | | +| - - - - - - - - - 0 - 000010 - | 000001 0 0 0 0 0 0 0 1 1 | -- (4) In Load data to IU2 +| - - - - - - - - - 1 - 000010 - | 000001 0 0 0 0 0 0 0 0 1 | -- (4) In Load data to IU2; Flushed +| | | +| - - - - 0 0 - - - - - 000001 - | 100000 1 0 0 0 0 0 0 0 1 | -- (5) In CheckECC, no error; go to idle +| - - - - 0 1 - - - - - 000001 - | 100000 1 0 0 0 0 0 0 0 1 | -- (5) In CheckECC, uncorrectable error; go to idle +| - - - - 1 - - - - - - 000001 - | 001000 0 0 0 0 0 0 0 0 0 | -- (5) In CheckECC, correctable error; go to wait state +*END*============================================+================================================+ +?TABLE END miss_sm; +//table_end +*/ + +//assign_start + +assign miss_sm_pt[1] = + (({ miss_flushed_l2 , miss_inval_l2 , + miss_tid_sm_l2[3] , last_data + }) === 4'b0010); +assign miss_sm_pt[2] = + (({ reld_r1_val_l2 , miss_tid_sm_l2[3] , + last_data }) === 3'b010); +assign miss_sm_pt[3] = + (({ miss_tid_sm_l2[3] , last_data + }) === 2'b10); +assign miss_sm_pt[4] = + (({ ecc_err , ecc_err_ue , + miss_flushed_l2 , miss_inval_l2 , + miss_tid_sm_l2[3] , last_data + }) === 6'b000011); +assign miss_sm_pt[5] = + (({ miss_tid_sm_l2[3] , last_data + }) === 2'b11); +assign miss_sm_pt[6] = + (({ iu2_flush , miss_tid_sm_l2[2] , + miss_tid_sm_l2[3] , miss_tid_sm_l2[4] , + miss_tid_sm_l2[5] }) === 5'b10000); +assign miss_sm_pt[7] = + (({ miss_tid_sm_l2[0] , miss_tid_sm_l2[3] , + miss_tid_sm_l2[4] , miss_tid_sm_l2[5] + }) === 4'b0000); +assign miss_sm_pt[8] = + (({ ecc_err , miss_tid_sm_l2[5] + }) === 2'b01); +assign miss_sm_pt[9] = + (({ ecc_err , miss_tid_sm_l2[5] + }) === 2'b11); +assign miss_sm_pt[10] = + (({ miss_flushed_l2 , miss_tid_sm_l2[4] + }) === 2'b01); +assign miss_sm_pt[11] = + (({ miss_tid_sm_l2[4] }) === 1'b1); +assign miss_sm_pt[12] = + (({ miss_flushed_l2 , miss_inval_l2 , + miss_tid_sm_l2[3] }) === 3'b001); +assign miss_sm_pt[13] = + (({ r2_crit_qw_l2 , miss_flushed_l2 , + miss_tid_sm_l2[3] }) === 3'b101); +assign miss_sm_pt[14] = + (({ reld_r1_val_l2 , miss_tid_sm_l2[3] + }) === 2'b11); +assign miss_sm_pt[15] = + (({ reld_r1_val_l2 , miss_tid_sm_l2[2] + }) === 2'b01); +assign miss_sm_pt[16] = + (({ miss_ci_l2 , reld_r1_val_l2 , + miss_tid_sm_l2[2] }) === 3'b011); +assign miss_sm_pt[17] = + (({ miss_ci_l2 , reld_r1_val_l2 , + miss_tid_sm_l2[2] }) === 3'b111); +assign miss_sm_pt[18] = + (({ iu2_flush , release_sm , + miss_tid_sm_l2[1] }) === 3'b001); +assign miss_sm_pt[19] = + (({ release_sm , miss_tid_sm_l2[1] + }) === 2'b11); +assign miss_sm_pt[20] = + (({ new_miss , addr_match , + iu2_flush , release_sm , + miss_tid_sm_l2[0] }) === 5'b11001); +assign miss_sm_pt[21] = + (({ addr_match , release_sm , + miss_tid_sm_l2[0] }) === 3'b111); +assign miss_sm_pt[22] = + (({ new_miss , addr_match , + iu2_flush , miss_tid_sm_l2[0] + }) === 4'b1001); +assign miss_sm_pt[23] = + (({ new_miss , miss_tid_sm_l2[0] + }) === 2'b01); +assign miss_tid_sm_d[0] = + (miss_sm_pt[6] | miss_sm_pt[8] + | miss_sm_pt[19] | miss_sm_pt[21] + | miss_sm_pt[23]); +assign miss_tid_sm_d[1] = + (miss_sm_pt[18] | miss_sm_pt[20] + ); +assign miss_tid_sm_d[2] = + (miss_sm_pt[2] | miss_sm_pt[9] + | miss_sm_pt[15] | miss_sm_pt[22] + ); +assign miss_tid_sm_d[3] = + (miss_sm_pt[14] | miss_sm_pt[16] + ); +assign miss_tid_sm_d[4] = + (miss_sm_pt[17]); +assign miss_tid_sm_d[5] = + (miss_sm_pt[5] | miss_sm_pt[11] + ); +assign reset_state = + (miss_sm_pt[8]); +assign request_tag = + (miss_sm_pt[22]); +assign write_dir_inval = + (miss_sm_pt[1]); +assign write_dir_val = + (miss_sm_pt[4]); +assign hold_tid = + (miss_sm_pt[3] | miss_sm_pt[7] + ); +assign data_write = + (miss_sm_pt[12]); +assign dir_write = + (miss_sm_pt[1]); +assign load_tag = + (miss_sm_pt[10] | miss_sm_pt[13] + ); +assign release_sm_hold = + (miss_sm_pt[5] | miss_sm_pt[8] + | miss_sm_pt[11]); + +//assign_end + +endmodule diff --git a/dev/verilog/work/iuq_ic_select.v b/dev/verilog/work/iuq_ic_select.v new file mode 100755 index 0000000..b56d3b5 --- /dev/null +++ b/dev/verilog/work/iuq_ic_select.v @@ -0,0 +1,1922 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//******************************************************************** +//* +//* TITLE: Instruction Select +//* +//* NAME: iuq_ic_select.v +//* +//********************************************************************* + +`include "tri_a2o.vh" + +module iuq_ic_select( + inout vdd, + inout gnd, + + (* pin_data ="PIN_FUNCTION=/G_CLK/" *) + input [0:`NCLK_WIDTH-1] nclk, + input pc_iu_func_sl_thold_0_b, + input pc_iu_func_slp_sl_thold_0_b, + input pc_iu_sg_0, + input force_t, + input funcslp_force, + input d_mode, + input delay_lclkr, + input mpw1_b, + input mpw2_b, + (* pin_data ="PIN_FUNCTION=/SCAN_IN/" *) + input func_scan_in, + (* pin_data ="PIN_FUNCTION=/SCAN_OUT/" *) + output func_scan_out, + + input [0:`THREADS-1] pc_iu_ram_active, + input [0:`THREADS-1] pc_iu_pm_fetch_halt, + input [0:`THREADS-1] xu_iu_run_thread, + input [0:`THREADS-1] cp_ic_stop, + input [0:`THREADS-1] xu_iu_msr_cm, // 0=32bit, 1=64bit address mode + + input [0:`THREADS-1] cp_flush, + input [0:`THREADS-1] cp_flush_into_uc, + input [0:`THREADS-1] br_iu_redirect, + input [62-`EFF_IFAR_ARCH:61] br_iu_bta, + input [62-`EFF_IFAR_ARCH:61] cp_iu0_t0_flush_ifar, + `ifndef THREADS1 + input [62-`EFF_IFAR_ARCH:61] cp_iu0_t1_flush_ifar, + `endif + input [0:`THREADS-1] cp_iu0_flush_2ucode, + input [0:`THREADS-1] cp_iu0_flush_2ucode_type, + input [0:`THREADS-1] cp_iu0_flush_nonspec, + + output [0:`THREADS-1] ic_cp_nonspec_hit, + + input an_ac_back_inv, // Arrives 1 cycle before addr + input [64-`REAL_IFAR_WIDTH:57] an_ac_back_inv_addr, + input an_ac_back_inv_target, // connect to bit(0); arrives 1 cycle before addr + + input spr_ic_prefetch_dis, + input spr_ic_ierat_byp_dis, + + input spr_ic_idir_read, + input [51:57] spr_ic_idir_row, + + output [3:8] ic_perf_t0_event, + `ifndef THREADS1 + output [3:8] ic_perf_t1_event, + `endif + + output iu_ierat_iu0_val, + output [0:`THREADS-1] iu_ierat_iu0_thdid, + output [0:51] iu_ierat_iu0_ifar, + output iu_ierat_iu0_nonspec, + output iu_ierat_iu0_prefetch, + output [0:`THREADS-1] iu_ierat_flush, + output iu_ierat_ium1_back_inv, + input [0:`THREADS-1] ierat_iu_hold_req, + input [0:`THREADS-1] ierat_iu_iu2_flush_req, + input ierat_iu_iu2_miss, + input ierat_iu_cam_change, + + // MMU Connections + input [0:`THREADS-1] mm_iu_hold_req, + input [0:`THREADS-1] mm_iu_hold_done, + input [0:`THREADS-1] mm_iu_bus_snoop_hold_req, + input [0:`THREADS-1] mm_iu_bus_snoop_hold_done, + + // ICBI Interface to IU + input [0:`THREADS-1] lq_iu_icbi_val, + input [64-`REAL_IFAR_WIDTH:57] lq_iu_icbi_addr, + output [0:`THREADS-1] iu_lq_icbi_complete, + + // IU IC Miss + input [0:`THREADS-1] icm_ics_iu0_preload_val, + input [50:59] icm_ics_iu0_preload_ifar, + input [0:`THREADS-1] icm_ics_prefetch_req, + input [0:`THREADS-1] icm_ics_prefetch_sm_idle, + + input [0:`THREADS-1] icm_ics_hold_thread, + input icm_ics_hold_iu0, + input icm_ics_iu3_miss_match, + input [0:`THREADS-1] icm_ics_iu3_ecc_fp_cancel, + + output [46:52] ics_icm_iu0_t0_ifar, + `ifndef THREADS1 + output [46:52] ics_icm_iu0_t1_ifar, + `endif + output ics_icm_iu0_inval, + output [51:57] ics_icm_iu0_inval_addr, + output [0:`THREADS-1] ics_icm_iu2_flush, + + // IU IC Dir + output ics_icd_dir_rd_act, + output [0:1] ics_icd_data_rd_act, + output ics_icd_iu0_valid, + output [0:`THREADS-1] ics_icd_iu0_tid, + output [62-`EFF_IFAR_ARCH:61] ics_icd_iu0_ifar, + output ics_icd_iu0_index51, + output ics_icd_iu0_inval, + output ics_icd_iu0_2ucode, + output ics_icd_iu0_2ucode_type, + output ics_icd_iu0_prefetch, + output ics_icd_iu0_read_erat, + output ics_icd_iu0_spr_idir_read, + + output [0:`THREADS-1] ics_icd_iu1_flush, + output [0:`THREADS-1] ics_icd_iu2_flush, + input icd_ics_iu1_valid, + input [0:`THREADS-1] icd_ics_iu1_tid, + input [62-`EFF_IFAR_WIDTH:61] icd_ics_iu1_ifar, + input icd_ics_iu1_2ucode, + input icd_ics_iu1_2ucode_type, + input [0:`THREADS-1] icd_ics_iu1_read_erat, + input [0:`THREADS-1] icd_ics_iu3_miss_flush, + input [0:`THREADS-1] icd_ics_iu2_wrong_ra_flush, + input [0:`THREADS-1] icd_ics_iu2_cam_etc_flush, + input [62-`EFF_IFAR_WIDTH:61] icd_ics_iu2_ifar_eff, + input icd_ics_iu2_2ucode, + input icd_ics_iu2_2ucode_type, + input icd_ics_iu2_valid, + input [0:`THREADS-1] icd_ics_iu2_read_erat_error, + input [0:`THREADS-1] icd_ics_iu3_parity_flush, + input [62-`EFF_IFAR_WIDTH:61] icd_ics_iu3_ifar, + input icd_ics_iu3_2ucode, + input icd_ics_iu3_2ucode_type, + + // BP + output [0:`THREADS-1] ic_bp_iu0_val, + output [50:59] ic_bp_iu0_ifar, + output [0:`THREADS-1] ic_bp_iu2_flush, + + //iu5 hold/redirect + input [0:`THREADS-1] bp_ic_iu2_redirect, + input [0:`THREADS-1] bp_ic_iu3_redirect, + input [0:`THREADS-1] bp_ic_iu4_redirect, + input [62-`EFF_IFAR_WIDTH:61] bp_ic_t0_redirect_ifar, + `ifndef THREADS1 + input [62-`EFF_IFAR_WIDTH:61] bp_ic_t1_redirect_ifar, + `endif + + // ucode + input [0:`THREADS-1] uc_ic_hold, + input [0:`THREADS-1] uc_iu4_flush, + input [62-`EFF_IFAR_WIDTH:61] uc_iu4_t0_flush_ifar, + `ifndef THREADS1 + input [62-`EFF_IFAR_WIDTH:61] uc_iu4_t1_flush_ifar, + `endif + + //Instruction Buffer + `ifndef THREADS1 + input [0:`IBUFF_DEPTH/4-1] ib_ic_t1_need_fetch, + `endif + input [0:`IBUFF_DEPTH/4-1] ib_ic_t0_need_fetch, + + input event_bus_enable +); + + // iuq_ic_select + + localparam [0:31] value_1 = 32'h00000001; + + parameter an_ac_back_inv_offset = 0; + parameter an_ac_back_inv_target_offset = an_ac_back_inv_offset + 1; + parameter an_ac_back_inv_addr_offset = an_ac_back_inv_target_offset + 1; + parameter spr_idir_read_offset = an_ac_back_inv_addr_offset + `REAL_IFAR_WIDTH - 6; + parameter spr_idir_row_offset = spr_idir_read_offset + 1; + parameter oldest_prefetch_offset = spr_idir_row_offset + 7; + parameter iu0_need_prefetch_offset = oldest_prefetch_offset + `THREADS - 1; + parameter iu0_prefetch_ifar_offset = iu0_need_prefetch_offset + `THREADS; + parameter lq_iu_icbi_val_offset = iu0_prefetch_ifar_offset + (`THREADS) * (`EFF_IFAR_WIDTH - 4); + parameter lq_iu_icbi_addr_offset = lq_iu_icbi_val_offset + `THREADS * `THREADS; //4 + parameter back_inv_offset = lq_iu_icbi_addr_offset + (`THREADS) * (`REAL_IFAR_WIDTH - 6); + parameter back_inv_icbi_offset = back_inv_offset + 1; + parameter xu_iu_msr_cm_offset = back_inv_icbi_offset + `THREADS; + parameter xu_iu_msr_cm2_offset = xu_iu_msr_cm_offset + `THREADS; + parameter xu_iu_msr_cm3_offset = xu_iu_msr_cm2_offset + `THREADS; + parameter xu_iu_run_thread_offset = xu_iu_msr_cm3_offset + `THREADS; + parameter cp_ic_stop_offset = xu_iu_run_thread_offset + `THREADS; //2 + parameter pc_iu_pm_fetch_halt_offset = cp_ic_stop_offset + `THREADS; //2 + parameter ierat_hold_offset = pc_iu_pm_fetch_halt_offset + `THREADS; //2 + parameter iu0_2ucode_offset = ierat_hold_offset + `THREADS; //2 + parameter iu0_2ucode_type_offset = iu0_2ucode_offset + `THREADS; //2 + parameter iu0_flip_index51_offset = iu0_2ucode_type_offset + `THREADS; //2 + parameter iu0_last_tid_sent_offset = iu0_flip_index51_offset + `THREADS; //2 + parameter iu0_sent_offset = iu0_last_tid_sent_offset + 1 * (`THREADS - 1); //1 + parameter iu0_ifar_offset = iu0_sent_offset + `THREADS * 3 * (`IBUFF_DEPTH/4); + parameter stored_erat_ifar_offset = iu0_ifar_offset + `THREADS * `EFF_IFAR_ARCH; + parameter stored_erat_valid_offset = stored_erat_ifar_offset + `THREADS * (`EFF_IFAR_WIDTH - 10); + parameter mm_hold_req_offset = stored_erat_valid_offset + `THREADS; + parameter mm_bus_snoop_hold_req_offset = mm_hold_req_offset + `THREADS; //2 + parameter cp_flush_offset = mm_bus_snoop_hold_req_offset + `THREADS; //2 + parameter cp_flush_into_uc_offset = cp_flush_offset + `THREADS; //2 + parameter cp_flush_ifar_offset = cp_flush_into_uc_offset + `THREADS; //2 + parameter cp_flush_2ucode_offset = cp_flush_ifar_offset + `THREADS * `EFF_IFAR_ARCH; + parameter cp_flush_2ucode_type_offset = cp_flush_2ucode_offset + `THREADS; //2 + parameter cp_flush_nonspec_offset = cp_flush_2ucode_type_offset + `THREADS; //2 + parameter br_iu_redirect_offset = cp_flush_nonspec_offset + `THREADS; //2 + parameter br_iu_bta_offset = br_iu_redirect_offset + `THREADS; //2 + parameter next_fetch_nonspec_offset = br_iu_bta_offset + `EFF_IFAR_ARCH; + parameter iu1_nonspec_offset = next_fetch_nonspec_offset + `THREADS; + parameter iu2_nonspec_offset = iu1_nonspec_offset + `THREADS; + parameter perf_event_offset = iu2_nonspec_offset + `THREADS; + parameter scan_right = perf_event_offset + `THREADS * 6 - 1; + + wire tiup; + + // Latch inputs + wire an_ac_back_inv_d; + wire an_ac_back_inv_l2; + + wire an_ac_back_inv_target_d; + wire an_ac_back_inv_target_l2; + + wire [64-`REAL_IFAR_WIDTH:57] an_ac_back_inv_addr_d; + wire [64-`REAL_IFAR_WIDTH:57] an_ac_back_inv_addr_l2; + + wire spr_idir_read_d; + wire spr_idir_read_l2; + + wire [51:57] spr_idir_row_d; + wire [51:57] spr_idir_row_l2; + + wire oldest_prefetch_d; + wire oldest_prefetch_l2; + + wire [0:`THREADS-1] iu0_need_prefetch_d; + wire [0:`THREADS-1] iu0_need_prefetch_l2; + + wire [62-`EFF_IFAR_WIDTH:57] iu0_prefetch_ifar_d[0:`THREADS-1]; + wire [62-`EFF_IFAR_WIDTH:57] iu0_prefetch_ifar_l2[0:`THREADS-1]; + + wire [0:`THREADS*`THREADS-1] lq_iu_icbi_val_d; // 2*2 + wire [0:`THREADS*`THREADS-1] lq_iu_icbi_val_l2; // 2*2 + + wire [64-`REAL_IFAR_WIDTH:57] lq_iu_icbi_addr_d[0:`THREADS-1]; + wire [64-`REAL_IFAR_WIDTH:57] lq_iu_icbi_addr_l2[0:`THREADS-1]; + + wire back_inv_d; + wire back_inv_l2; + + wire [0:`THREADS-1] back_inv_icbi_d; + wire [0:`THREADS-1] back_inv_icbi_l2; + + wire [0:`THREADS-1] xu_iu_run_thread_d; + wire [0:`THREADS-1] xu_iu_run_thread_l2; + + wire [0:`THREADS-1] xu_iu_msr_cm_d; + wire [0:`THREADS-1] xu_iu_msr_cm_l2; + + wire [0:`THREADS-1] xu_iu_msr_cm2_d; + wire [0:`THREADS-1] xu_iu_msr_cm2_l2; + + wire [0:`THREADS-1] xu_iu_msr_cm3_d; + wire [0:`THREADS-1] xu_iu_msr_cm3_l2; + + wire [0:`THREADS-1] cp_ic_stop_d; + wire [0:`THREADS-1] cp_ic_stop_l2; + + wire [0:`THREADS-1] pc_iu_pm_fetch_halt_d; + wire [0:`THREADS-1] pc_iu_pm_fetch_halt_l2; + + wire [0:`THREADS-1] ierat_hold_d; + wire [0:`THREADS-1] ierat_hold_l2; + + // Current IFARs for each of the threads + reg [62-`EFF_IFAR_ARCH:61] iu0_ifar_temp[0:`THREADS-1]; + wire [62-`EFF_IFAR_ARCH:61] iu0_ifar_d[0:`THREADS-1]; + wire [62-`EFF_IFAR_ARCH:61] iu0_ifar_l2[0:`THREADS-1]; + + reg [0:`THREADS-1] iu0_2ucode_d; + wire [0:`THREADS-1] iu0_2ucode_l2; + reg [0:`THREADS-1] iu0_2ucode_type_d; + wire [0:`THREADS-1] iu0_2ucode_type_l2; + + wire [0:`THREADS-1] iu0_flip_index51_d; + wire [0:`THREADS-1] iu0_flip_index51_l2; + + wire [62-`EFF_IFAR_WIDTH:51] stored_erat_ifar_d[0:`THREADS-1]; + wire [62-`EFF_IFAR_WIDTH:51] stored_erat_ifar_l2[0:`THREADS-1]; + wire [0:`THREADS-1] stored_erat_valid_d; + wire [0:`THREADS-1] stored_erat_valid_l2; + + wire [0:`THREADS-1] mm_hold_req_d; + wire [0:`THREADS-1] mm_hold_req_l2; + + wire [0:`THREADS-1] mm_bus_snoop_hold_req_d; + wire [0:`THREADS-1] mm_bus_snoop_hold_req_l2; + + wire [0:`THREADS-1] cp_flush_l2; + wire [0:`THREADS-1] cp_flush_into_uc_l2; + wire [0:`THREADS-1] br_iu_redirect_d; + wire [62-`EFF_IFAR_ARCH:61] cp_flush_ifar_d[0:`THREADS-1]; + wire [0:`THREADS-1] br_iu_redirect_l2; + wire [62-`EFF_IFAR_ARCH:61] br_iu_bta_l2; + wire [62-`EFF_IFAR_ARCH:61] cp_flush_ifar_l2[0:`THREADS-1]; + wire [0:`THREADS-1] cp_flush_2ucode_l2; + wire [0:`THREADS-1] cp_flush_2ucode_type_l2; + wire [0:`THREADS-1] cp_flush_nonspec_l2; + + wire [0:`THREADS-1] next_fetch_nonspec_d; + wire [0:`THREADS-1] next_fetch_nonspec_l2; + + wire [0:`THREADS-1] iu1_nonspec_d; + wire [0:`THREADS-1] iu2_nonspec_d; + wire [0:`THREADS-1] iu1_nonspec_l2; + wire [0:`THREADS-1] iu2_nonspec_l2; + + wire iu0_last_tid_sent_d; + wire iu0_last_tid_sent_l2; + + // Used to keep track of the commands in flight to IB + reg [0:2] iu0_sent_d[0:`THREADS-1][0:(`IBUFF_DEPTH/4)-1]; + wire [0:2] iu0_sent_l2[0:`THREADS-1][0:(`IBUFF_DEPTH/4)-1]; + + wire [3:8] perf_event_d[0:`THREADS-1]; + wire [3:8] perf_event_l2[0:`THREADS-1]; + + wire [62-`EFF_IFAR_WIDTH:61] bp_ic_redirect_ifar[0:`THREADS-1]; + wire [62-`EFF_IFAR_WIDTH:61] uc_iu4_flush_ifar[0:`THREADS-1]; + wire [0:`IBUFF_DEPTH/4-1] ib_ic_need_fetch[0:`THREADS-1]; + + + wire [62-`EFF_IFAR_WIDTH:57] new_prefetch_ifar; + wire prefetch_wrap; + wire [0:`THREADS-1] msr_cm_changed; + wire [0:`THREADS-1] oldest_prefetch_v; + wire [0:`THREADS-1] iu2_prefetch_retry; + wire [0:`THREADS-1] iu0_prefetch_ifar_act; + wire [0:`THREADS-1] prefetch_addr_outside_range; + wire [0:`THREADS-1] flush_prefetch; + wire [0:`THREADS-1] prefetch_ready; + wire [0:`THREADS-1] next_prefetch; + wire [0:`THREADS-1] send_prefetch; + + wire back_inv_addr_act; + + wire [0:`THREADS-1] toggle_flip; + + wire [0:`THREADS-1] iu0_need_new_erat; + wire [0:`THREADS-1] clear_erat_valid; + wire [0:`THREADS-1] stored_erat_act; + wire [0:`THREADS-1] iu0_cross_4k_fetch; + wire [0:`THREADS-1] iu0_cross_4k_prefetch; + wire [0:`THREADS-1] iu0_cross_4k; + wire [0:`THREADS-1] iu0_read_erat; + + wire [0:`THREADS-1] hold_thread; + wire [0:`THREADS-1] hold_thread_perf_lite; + wire [0:`THREADS-1] hold_prefetch; + wire iu0_erat_valid; + wire [0:`THREADS-1] iu0_erat_tid; + + wire [0:`THREADS-1] need_fetch_reduce; + reg [0:(`IBUFF_DEPTH/4)-1] need_fetch[0:`THREADS-1]; + reg [0:(`IBUFF_DEPTH/4)-1] next_fetch[0:`THREADS-1]; + reg [0:(`IBUFF_DEPTH/4)-2] shift1_sent[0:`THREADS-1]; + reg [0:`THREADS-1] shift1_sent_reduce; + reg [0:(`IBUFF_DEPTH/4)-3] shift2_sent[0:`THREADS-1]; + reg [0:`THREADS-1] shift2_sent_reduce; + + reg [0:`THREADS-1] set_sent; + wire [0:`THREADS-1] thread_ready; + wire iu0_valid; + wire [0:`THREADS-1] iu0_tid; + wire [0:`THREADS-1] iu0_flush; + wire [0:`THREADS-1] iu1_flush; + wire [0:`THREADS-1] iu2_flush; + wire [0:`THREADS-1] iu3_flush; + wire [0:`THREADS-1] iu1_ecc_flush; + + wire [0:1] data_rd_act; + + wire [62-`EFF_IFAR_ARCH:61] iu0_ifar; + + wire block_spr_idir_read; + + // scan + wire [0:scan_right] siv; + wire [0:scan_right] sov; + + // BEGIN + + //tidn <= '0'; + assign tiup = 1'b1; + + assign br_iu_redirect_d = br_iu_redirect & (~(cp_flush_l2)); + + assign cp_flush_ifar_d[0] = cp_iu0_t0_flush_ifar; + assign bp_ic_redirect_ifar[0] = bp_ic_t0_redirect_ifar; + assign uc_iu4_flush_ifar[0] = uc_iu4_t0_flush_ifar; + assign ib_ic_need_fetch[0] = ib_ic_t0_need_fetch; + `ifndef THREADS1 + assign cp_flush_ifar_d[1] = cp_iu0_t1_flush_ifar; + assign bp_ic_redirect_ifar[1] = bp_ic_t1_redirect_ifar; + assign uc_iu4_flush_ifar[1] = uc_iu4_t1_flush_ifar; + assign ib_ic_need_fetch[1] = ib_ic_t1_need_fetch; + `endif + + // Added logic for Erat invalidates + assign mm_hold_req_d = (mm_iu_hold_req | mm_hold_req_l2) & (~(mm_iu_hold_done)); + + assign mm_bus_snoop_hold_req_d = (mm_iu_bus_snoop_hold_req | mm_bus_snoop_hold_req_l2) & (~(mm_iu_bus_snoop_hold_done)); + + //--------------------------------------------------------------------- + // SPR IDir Read + //--------------------------------------------------------------------- + assign block_spr_idir_read = back_inv_l2 | icm_ics_hold_iu0; + + assign spr_idir_read_d = spr_ic_idir_read | (spr_idir_read_l2 & block_spr_idir_read); // Invalidates & dir writes have priority + + assign spr_idir_row_d = spr_ic_idir_row; + + assign ics_icd_iu0_spr_idir_read = spr_idir_read_l2 & (~block_spr_idir_read); + + //--------------------------------------------------------------------- + // Prefetch + //--------------------------------------------------------------------- + assign new_prefetch_ifar = icd_ics_iu2_ifar_eff[62 - `EFF_IFAR_WIDTH:57] + value_1[36-`EFF_IFAR_WIDTH:31]; // ??? Need to change if cls = 128 B + assign prefetch_wrap = ~|(new_prefetch_ifar); + + // Prefetch request based off of old msr_cm value could occur two cycles after change, so need 3 latches + assign msr_cm_changed = (xu_iu_msr_cm_d ^ xu_iu_msr_cm_l2) | // prefetch request same cycle or earlier + (xu_iu_msr_cm_l2 ^ xu_iu_msr_cm2_l2) | // prefetch request 1 cycle after change + (xu_iu_msr_cm2_l2 ^ xu_iu_msr_cm3_l2); // prefetch request 2 cycles after change + + // icm_ics_prefetch_req & (ierat_iu_iu2_flush_req and iu2_prefetch) are mutually exclusive, + // since you cannot have both iu2_valid & iu2_prefetch at the same time + // Check iu0_need_prefetch=0 to make sure newer prefetch req didn't sneak in last two cycles + assign oldest_prefetch_d = ((icm_ics_prefetch_req[`THREADS - 1] | iu2_prefetch_retry[0]) == 1'b1) ? 1'b0 : // Thread 1 or Thr 0 when single thread + ((icm_ics_prefetch_req[0] | iu2_prefetch_retry[`THREADS - 1]) == 1'b1) ? 1'b1 : + oldest_prefetch_l2; + + assign oldest_prefetch_v[0] = (~oldest_prefetch_l2); + + `ifndef THREADS1 // THREADS > 1 + assign oldest_prefetch_v[`THREADS - 1] = oldest_prefetch_l2; + `endif + + generate + begin : xhdl1 + genvar i; + for (i = 0; i < `THREADS; i = i + 1) + begin : gen_prefetch + assign iu2_prefetch_retry[i] = (ierat_iu_iu2_flush_req[i] | icd_ics_iu2_cam_etc_flush[i]) & (~icd_ics_iu2_valid) & (~iu0_need_prefetch_l2[i]); + + assign iu0_need_prefetch_d[i] = ((icm_ics_prefetch_req[i] & (~prefetch_wrap)) | // don't wrap around + (iu0_need_prefetch_l2[i] & (~send_prefetch[i]) & (~flush_prefetch[i])) | + (iu2_prefetch_retry[i] & (~flush_prefetch[i]))) & + (~spr_ic_prefetch_dis) & (~msr_cm_changed[i]); + + assign iu0_prefetch_ifar_act[i] = (icm_ics_prefetch_req[i] & (~prefetch_wrap)) | iu2_prefetch_retry[i]; + + assign iu0_prefetch_ifar_d[i] = (icd_ics_iu2_valid == 1'b1) ? new_prefetch_ifar : + icd_ics_iu2_ifar_eff[62 - `EFF_IFAR_WIDTH:57]; // prefetch collision w/ ierat op (ierat_iu_iu2_flush_req) + + assign prefetch_addr_outside_range[i] = bp_ic_redirect_ifar[i][46:52] != iu0_prefetch_ifar_l2[i][46:52]; + assign flush_prefetch[i] = cp_flush_l2[i] | br_iu_redirect_l2[i] | (bp_ic_iu4_redirect[i] & prefetch_addr_outside_range[i]); + end + end + endgenerate + + assign prefetch_ready = iu0_need_prefetch_l2 & icm_ics_prefetch_sm_idle & (~hold_prefetch); + + assign next_prefetch = ((&(prefetch_ready)) == 1'b1) ? oldest_prefetch_v : // both are valid, choose oldest + prefetch_ready; // 1 or 0 are valid + + assign send_prefetch = next_prefetch & (~flush_prefetch); + + //--------------------------------------------------------------------- + // IU0 + //--------------------------------------------------------------------- + assign an_ac_back_inv_d = an_ac_back_inv; + assign an_ac_back_inv_target_d = an_ac_back_inv_target; + assign an_ac_back_inv_addr_d = an_ac_back_inv_addr; + assign back_inv_addr_act = an_ac_back_inv_l2 & an_ac_back_inv_target_l2; + + generate + begin + if (`THREADS == 1) + begin : gen_icbi_val_t1 + assign lq_iu_icbi_val_d[0] = lq_iu_icbi_val[0] | (lq_iu_icbi_val_l2[0] & an_ac_back_inv_l2 & an_ac_back_inv_target_l2); + end + + // Two-deep buffer, with 2 bits for Thread0&1 + if (`THREADS == 2) + begin : gen_icbi_val_t2 + assign lq_iu_icbi_val_d[0:`THREADS - 1] = ((an_ac_back_inv_l2 & an_ac_back_inv_target_l2 & + (|(lq_iu_icbi_val_l2[0:`THREADS - 1]))) == 1'b1) ? lq_iu_icbi_val_l2[0:`THREADS - 1] : + ((|(lq_iu_icbi_val_l2[2:3])) == 1'b1) ? lq_iu_icbi_val_l2[2:3] : + lq_iu_icbi_val; + + assign lq_iu_icbi_val_d[2:3] = (an_ac_back_inv_l2 & an_ac_back_inv_target_l2 & (|(lq_iu_icbi_val_l2[2:3])) == 1'b1) ? lq_iu_icbi_val_l2[2:3] : + (an_ac_back_inv_l2 & an_ac_back_inv_target_l2 & (|(lq_iu_icbi_val_l2[0:`THREADS - 1])) == 1'b1) ? lq_iu_icbi_val : + 2'b00; + end + + genvar i; + for (i = 0; i < `THREADS; i = i + 1) + begin : gen_icbi_addr + assign lq_iu_icbi_addr_d[i] = lq_iu_icbi_addr; + end + end + endgenerate + + assign iu_lq_icbi_complete = {`THREADS{~(an_ac_back_inv_l2 & an_ac_back_inv_target_l2)}} & lq_iu_icbi_val_l2[0:`THREADS - 1]; + + assign back_inv_d = (an_ac_back_inv_l2 & an_ac_back_inv_target_l2) | (|(lq_iu_icbi_val_l2[0:`THREADS - 1])); + assign back_inv_icbi_d = {`THREADS{~(an_ac_back_inv_l2 & an_ac_back_inv_target_l2)}} & lq_iu_icbi_val_l2[0:`THREADS - 1]; + + assign iu_ierat_ium1_back_inv = back_inv_d; + + assign xu_iu_msr_cm_d = xu_iu_msr_cm; + assign xu_iu_msr_cm2_d = xu_iu_msr_cm_l2; + assign xu_iu_msr_cm3_d = xu_iu_msr_cm2_l2; + + assign xu_iu_run_thread_d = xu_iu_run_thread; + assign cp_ic_stop_d = cp_ic_stop; + assign pc_iu_pm_fetch_halt_d = pc_iu_pm_fetch_halt; + + assign ierat_hold_d = ierat_iu_hold_req; + + // This keeps track of the commands in flight to IB + // Note: icm_ics_iu0_preload_val should only be on if hold_thread='1' because of icm_ics_hold_iu0 + + //always @(iu0_sent_l2 or ib_ic_need_fetch or iu0_tid or need_fetch or next_fetch or shift1_sent or shift1_sent_reduce or shift2_sent or shift2_sent_reduce or set_sent or iu0_flush or iu1_flush or iu2_flush or icm_ics_iu0_preload_val) + always @ (*) + begin: sent_proc + reg [0:1] any_sent[0:`THREADS-1]; //(`THREADS)(0 to 1); + reg any_lower_fetch; + // (* analysis_not_referenced="true" *) + integer t; + // (* analysis_not_referenced="true" *) + integer i; + // (* analysis_not_referenced="true" *) + integer j; + + for (t = 0; t < `THREADS; t = t + 1) + begin + for (i = 0; i < `IBUFF_DEPTH/4; i = i + 1) + need_fetch[t][i] = ib_ic_need_fetch[t][i] & (~|(iu0_sent_l2[t][i])); + + next_fetch[t][0] = need_fetch[t][0]; + for (i = 1; i < `IBUFF_DEPTH/4; i = i + 1) + begin + any_lower_fetch = 0; + for (j=0; j < i; j = j + 1) + begin + any_lower_fetch = need_fetch[t][j] | any_lower_fetch; + end + + next_fetch[t][i] = need_fetch[t][i] & (~any_lower_fetch); + end + + // need to shift as buffer gets emptier + for (i = 0; i < ((`IBUFF_DEPTH/4) - 1); i = i + 1) + shift1_sent[t][i] = next_fetch[t][i] & (|(iu0_sent_l2[t][i + 1])); + shift1_sent_reduce[t] = |(shift1_sent[t]); + + for (i = 0; i < ((`IBUFF_DEPTH/4) - 2); i = i + 1) + shift2_sent[t][i] = next_fetch[t][i] & (|(iu0_sent_l2[t][i + 2])); + shift2_sent_reduce[t] = |(shift2_sent[t]); + + any_sent[t] = 2'b00; + for (i = 0; i < `IBUFF_DEPTH/4; i = i + 1) + begin + any_sent[t][0] = any_sent[t][0] | iu0_sent_l2[t][i][0]; + any_sent[t][1] = any_sent[t][1] | iu0_sent_l2[t][i][1]; + end + + set_sent[t] = (iu0_tid[t] | icm_ics_iu0_preload_val[t]) & (~iu0_flush[t]); + + for (i = 0; i < `IBUFF_DEPTH/4; i = i + 1) + iu0_sent_d[t][i] = iu0_sent_l2[t][i]; + + if (shift1_sent_reduce[t] == 1'b1) // shift 1 + begin + for (i = 0; i < `IBUFF_DEPTH/4; i = i + 1) + begin + // swap with current last position + if (any_sent[t][0] == 1'b1) + iu0_sent_d[t][i][0] = set_sent[t] & iu0_sent_l2[t][i][0]; + else if (any_sent[t][1] == 1'b1) + iu0_sent_d[t][i][0] = set_sent[t] & iu0_sent_l2[t][i][1]; + else + iu0_sent_d[t][i][0] = set_sent[t] & iu0_sent_l2[t][i][2]; + end + + // shift down + for (i = 0; i < ((`IBUFF_DEPTH/4) - 1); i = i + 1) + begin + iu0_sent_d[t][i][1] = iu0_sent_l2[t][i + 1][0] & (~(iu1_flush[t])); + iu0_sent_d[t][i][2] = iu0_sent_l2[t][i + 1][1] & (~(iu2_flush[t])); + end + iu0_sent_d[t][(`IBUFF_DEPTH/4) - 1][1] = 1'b0; + iu0_sent_d[t][(`IBUFF_DEPTH/4) - 1][2] = 1'b0; + end + + else if (shift2_sent_reduce[t] == 1'b1) // shift 2 + begin + for (i = 0; i < ((`IBUFF_DEPTH/4) - 1); i = i + 1) + begin + // swap with current last position & shift down one + if (any_sent[t][0] == 1'b1) + iu0_sent_d[t][i][0] = set_sent[t] & iu0_sent_l2[t][i + 1][0]; + else if (any_sent[t][1] == 1'b1) + iu0_sent_d[t][i][0] = set_sent[t] & iu0_sent_l2[t][i + 1][1]; + else + iu0_sent_d[t][i][0] = set_sent[t] & iu0_sent_l2[t][i + 1][2]; + end + iu0_sent_d[t][(`IBUFF_DEPTH/4) - 1][0] = 1'b0; + + // shift down + for (i = 0; i < ((`IBUFF_DEPTH/4) - 2); i = i + 1) + begin + iu0_sent_d[t][i][1] = iu0_sent_l2[t][i + 2][0] & (~(iu1_flush[t])); + iu0_sent_d[t][i][2] = iu0_sent_l2[t][i + 2][1] & (~(iu2_flush[t])); + end + iu0_sent_d[t][(`IBUFF_DEPTH/4) - 1][1] = 1'b0; + iu0_sent_d[t][(`IBUFF_DEPTH/4) - 1][2] = 1'b0; + + iu0_sent_d[t][(`IBUFF_DEPTH/4) - 2][1] = 1'b0; + iu0_sent_d[t][(`IBUFF_DEPTH/4) - 2][2] = 1'b0; + end + + else + begin + // no shifting + for (i = 0; i < `IBUFF_DEPTH/4; i = i + 1) + begin + iu0_sent_d[t][i][0] = set_sent[t] & next_fetch[t][i]; + //(next_fetch(i) and not(hold_thread) and not(iu0_flush)) or + //(next_load(i) and not (iu0_flush)); + iu0_sent_d[t][i][1] = iu0_sent_l2[t][i][0] & (~(iu1_flush[t])); + iu0_sent_d[t][i][2] = iu0_sent_l2[t][i][1] & (~(iu2_flush[t])); + end + end + end // t loop + end + + assign thread_ready = need_fetch_reduce & (~hold_thread); + + `ifdef THREADS1 //(`THREADS == 1) + assign iu0_tid[0] = thread_ready[0]; + `endif + `ifndef THREADS1 //(`THREADS == 2) + assign iu0_tid[0] = thread_ready[0] & ((iu0_last_tid_sent_l2 == 1'b1) | ((~thread_ready[1]))); + assign iu0_tid[1] = thread_ready[1] & ((iu0_last_tid_sent_l2 == 1'b0) | ((~thread_ready[0]))); + `endif + + assign iu0_last_tid_sent_d = (iu0_valid == 1'b1) ? iu0_tid[`THREADS - 1] : + iu0_last_tid_sent_l2; + + // We drop hold thread on the last beat of data, so there's 1 cycle where we might have sent the next ifar + assign iu1_ecc_flush = {`THREADS{icd_ics_iu1_valid}} & icd_ics_iu1_tid & icm_ics_iu3_ecc_fp_cancel; + + always @ (*) + begin: iu0_ifar_proc + //(* analysis_not_referenced="true" *) + integer i; + + iu0_2ucode_d = iu0_2ucode_l2; + iu0_2ucode_type_d = iu0_2ucode_type_l2; + + for (i = 0; i < `THREADS; i = i + 1) + begin + iu0_ifar_temp[i] = iu0_ifar_l2[i]; + + if ((cp_flush_l2[i] == 1'b1) & (cp_flush_into_uc_l2[i] == 1'b0)) + begin + iu0_ifar_temp[i] = cp_flush_ifar_l2[i]; + iu0_2ucode_d[i] = cp_flush_2ucode_l2[i] & (~pc_iu_ram_active[i]); + iu0_2ucode_type_d[i] = cp_flush_2ucode_type_l2[i] & (~pc_iu_ram_active[i]); + end + else if ((cp_flush_l2[i] == 1'b1) & (cp_flush_into_uc_l2[i] == 1'b1)) + begin + iu0_ifar_temp[i] = cp_flush_ifar_l2[i] + 1; + iu0_2ucode_d[i] = 1'b0; + iu0_2ucode_type_d[i] = 1'b0; + end + else if (br_iu_redirect_l2[i] == 1'b1) + begin + iu0_ifar_temp[i] = br_iu_bta_l2; + iu0_2ucode_d[i] = 1'b0; + iu0_2ucode_type_d[i] = 1'b0; + end + else if (uc_iu4_flush[i] == 1'b1) + begin + iu0_ifar_temp[i] = {iu0_ifar_l2[i][62-`EFF_IFAR_ARCH:62-`EFF_IFAR_WIDTH-1], uc_iu4_flush_ifar[i]}; + iu0_2ucode_d[i] = 1'b0; + iu0_2ucode_type_d[i] = 1'b0; + end + else if (bp_ic_iu4_redirect[i] == 1'b1) + begin + iu0_ifar_temp[i] = {iu0_ifar_l2[i][62-`EFF_IFAR_ARCH:62-`EFF_IFAR_WIDTH-1], bp_ic_redirect_ifar[i]}; + iu0_2ucode_d[i] = 1'b0; + iu0_2ucode_type_d[i] = 1'b0; + end + else if (icd_ics_iu3_parity_flush[i] == 1'b1 | (icd_ics_iu3_miss_flush[i] & icm_ics_iu3_miss_match)) + begin + iu0_ifar_temp[i] = {iu0_ifar_l2[i][62-`EFF_IFAR_ARCH:62-`EFF_IFAR_WIDTH-1], icd_ics_iu3_ifar}; + iu0_2ucode_d[i] = icd_ics_iu3_2ucode; + iu0_2ucode_type_d[i] = icd_ics_iu3_2ucode_type; + end + else if (icd_ics_iu3_miss_flush[i] == 1'b1) // and not icm_ics_iu2_miss_match + begin + iu0_ifar_temp[i] = {iu0_ifar_l2[i][62-`EFF_IFAR_ARCH:62-`EFF_IFAR_WIDTH-1], (icd_ics_iu3_ifar[62-`EFF_IFAR_WIDTH:59] + value_1[34-`EFF_IFAR_WIDTH:31]), 2'b00}; + iu0_2ucode_d[i] = 1'b0; + iu0_2ucode_type_d[i] = 1'b0; + end + else if ((bp_ic_iu3_redirect[i] == 1'b1) & (icm_ics_iu3_ecc_fp_cancel[i] == 1'b0)) + begin + iu0_ifar_temp[i] = {iu0_ifar_l2[i][62-`EFF_IFAR_ARCH:62-`EFF_IFAR_WIDTH-1], bp_ic_redirect_ifar[i]}; + iu0_2ucode_d[i] = 1'b0; + iu0_2ucode_type_d[i] = 1'b0; + end + // for ierat flush, only update ifar if iu2_valid (i.e. not iu2_prefetch) + else if ((((ierat_iu_iu2_flush_req[i] | icd_ics_iu2_cam_etc_flush[i]) & icd_ics_iu2_valid) | + icd_ics_iu2_wrong_ra_flush[i]) == 1'b1) + begin + iu0_ifar_temp[i] = {iu0_ifar_l2[i][62-`EFF_IFAR_ARCH:62-`EFF_IFAR_WIDTH-1], icd_ics_iu2_ifar_eff}; + iu0_2ucode_d[i] = icd_ics_iu2_2ucode; + iu0_2ucode_type_d[i] = icd_ics_iu2_2ucode_type; + end + else if ((bp_ic_iu2_redirect[i] == 1'b1) & (icm_ics_iu3_ecc_fp_cancel[i] == 1'b0)) + begin + iu0_ifar_temp[i] = {iu0_ifar_l2[i][62-`EFF_IFAR_ARCH:62-`EFF_IFAR_WIDTH-1], bp_ic_redirect_ifar[i]}; + iu0_2ucode_d[i] = 1'b0; + iu0_2ucode_type_d[i] = 1'b0; + end + else if(iu1_ecc_flush[i] == 1'b1) + begin + iu0_ifar_temp[i] = {iu0_ifar_l2[i][62-`EFF_IFAR_ARCH:62-`EFF_IFAR_WIDTH-1], icd_ics_iu1_ifar}; + iu0_2ucode_d[i] = icd_ics_iu1_2ucode; + iu0_2ucode_type_d[i] = icd_ics_iu1_2ucode_type; + end + else if (iu0_tid[i] == 1'b1) + begin + iu0_ifar_temp[i] = {iu0_ifar_l2[i][62-`EFF_IFAR_ARCH:62-`EFF_IFAR_WIDTH-1], (iu0_ifar_l2[i][62-`EFF_IFAR_WIDTH:59] + value_1[34-`EFF_IFAR_WIDTH:31]), 2'b00}; + iu0_2ucode_d[i] = 1'b0; + iu0_2ucode_type_d[i] = 1'b0; + end + end + end // iu0_ifar_proc + + generate + begin : xhdl4 + genvar t; + for (t = 0; t < `THREADS; t = t + 1) + begin : thread_iu0_ifar_mask + genvar i; + for (i = (62 - `EFF_IFAR_ARCH); i < 62; i = i + 1) + begin : iu0_ifar0_mask + if (i < 32) + begin + assign iu0_ifar_d[t][i] = (xu_iu_msr_cm[t] & iu0_ifar_temp[t][i]); + end + if (i >= 32) + begin + assign iu0_ifar_d[t][i] = iu0_ifar_temp[t][i]; + end + end + end + end + endgenerate + + assign toggle_flip = icd_ics_iu2_wrong_ra_flush & (~ierat_iu_iu2_flush_req) & (~iu3_flush); + assign iu0_flip_index51_d = ( toggle_flip & (~iu0_flip_index51_l2)) | + ((~toggle_flip) & iu0_flip_index51_l2); + + //--------------------------------------------------------------------- + // Stored ERAT + //--------------------------------------------------------------------- + // Keep 42:51 to compare, and flush if cp or br flush + + generate + begin : xhdl5 + genvar i; + for (i = 0; i < `THREADS; i = i + 1) + begin : stored_erat_gen + assign stored_erat_act[i] = iu0_read_erat[i] & (~spr_ic_ierat_byp_dis); + assign stored_erat_ifar_d[i] = iu0_ifar[62-`EFF_IFAR_WIDTH:51]; + + assign iu0_cross_4k_fetch[i] = (iu0_ifar_l2[i][62-`EFF_IFAR_WIDTH:51] != stored_erat_ifar_l2[i]); + assign iu0_cross_4k_prefetch[i] = (iu0_prefetch_ifar_l2[i][62-`EFF_IFAR_WIDTH:51] != stored_erat_ifar_l2[i]); + + assign iu0_cross_4k[i] = (iu0_tid[i] & iu0_cross_4k_fetch[i]) | + (next_prefetch[i] & iu0_cross_4k_prefetch[i]); + + assign iu0_read_erat[i] = (iu0_erat_valid & iu0_erat_tid[i]) & + ((~stored_erat_valid_l2[i]) | iu0_need_new_erat[i] | next_fetch_nonspec_l2[i] | spr_ic_ierat_byp_dis); + + // This is a subset of clear_erat_valid that does not include any of the flush terms + // (because we would be dropping fetch anyways if it is flushed). For timing & helps power. + assign iu0_need_new_erat[i] = (iu0_cross_4k[i] & (~bp_ic_iu4_redirect[i])) | + ierat_iu_cam_change | icd_ics_iu2_read_erat_error[i]; + + assign clear_erat_valid[i] = cp_flush_l2[i] | br_iu_redirect_l2[i] | (iu0_cross_4k[i] & (~bp_ic_iu4_redirect[i])) | // Might be on new page + ierat_iu_cam_change | icd_ics_iu2_read_erat_error[i] | + (icd_ics_iu2_valid & ierat_iu_iu2_flush_req[i]) | + (icd_ics_iu1_read_erat[i] & iu1_flush[i]); // not going to be stored + + assign stored_erat_valid_d[i] = (~spr_ic_ierat_byp_dis) & + ((iu0_read_erat[i] & (~iu0_flush[i])) | (stored_erat_valid_l2[i] & (~clear_erat_valid[i]))); + end + end + endgenerate + + assign ics_icd_iu0_read_erat = |(iu0_read_erat); + + //--------------------------------------------------------------------- + // Outputs + //--------------------------------------------------------------------- + // ???? Do I want to split up threaded/non-threaded signals? + generate + begin : xhdl6 + genvar i; + for (i = 0; i < `THREADS; i = i + 1) + begin : hold_t + assign hold_thread[i] = (~xu_iu_run_thread_l2[i] & ~next_fetch_nonspec_l2[i]) | cp_ic_stop_l2[i] | pc_iu_pm_fetch_halt_l2[i] | mm_hold_req_l2[i] | mm_bus_snoop_hold_req_l2[i] | + ierat_hold_l2[i] | back_inv_l2 | icm_ics_hold_iu0 | spr_idir_read_l2 | uc_ic_hold[i] | icm_ics_hold_thread[i]; + + // Everything except icm_ics_hold_iu0 + assign hold_thread_perf_lite[i] = (~xu_iu_run_thread_l2[i] & ~next_fetch_nonspec_l2[i]) | cp_ic_stop_l2[i] | pc_iu_pm_fetch_halt_l2[i] | mm_hold_req_l2[i] | mm_bus_snoop_hold_req_l2[i] | + ierat_hold_l2[i] | back_inv_l2 | spr_idir_read_l2 | uc_ic_hold[i] | icm_ics_hold_thread[i]; + + assign hold_prefetch[i] = (~xu_iu_run_thread_l2[i]) | cp_ic_stop_l2[i] | pc_iu_pm_fetch_halt_l2[i] | mm_hold_req_l2[i] | mm_bus_snoop_hold_req_l2[i] | + ierat_hold_l2[i] | back_inv_l2 | icm_ics_hold_iu0 | spr_idir_read_l2 | (|(need_fetch_reduce & (~hold_thread))); + end + + //genvar i; + for (i = 0; i < `THREADS; i = i + 1) + begin : gen_need_fetch_reduce + assign need_fetch_reduce[i] = |(need_fetch[i]); + end + end + endgenerate + + assign iu0_erat_valid = |(need_fetch_reduce & (~hold_thread)) | (|(prefetch_ready)); + assign iu0_erat_tid = iu0_tid | next_prefetch; + assign iu_ierat_iu0_val = |(iu0_read_erat); + assign iu_ierat_iu0_thdid = iu0_erat_tid; + assign iu_ierat_iu0_prefetch = |(prefetch_ready) & (~(|(need_fetch_reduce & (~hold_thread)))); + + generate + begin : xhdl8 + genvar i; + for (i = 0; i < 52; i = i + 1) + begin : ierat_ifar + if (i < 62 - `EFF_IFAR_ARCH) + assign iu_ierat_iu0_ifar[i] = 1'b0; + if (i >= 62 - `EFF_IFAR_ARCH) + assign iu_ierat_iu0_ifar[i] = iu0_ifar[i]; + end + end + endgenerate + + assign next_fetch_nonspec_d = (~cp_flush) & + (cp_flush_nonspec_l2 | (next_fetch_nonspec_l2 & (~iu0_tid)) | + ({`THREADS{icd_ics_iu2_valid}} & ierat_iu_iu2_flush_req & iu2_nonspec_l2)); + assign iu_ierat_iu0_nonspec = |(next_fetch_nonspec_l2 & iu0_tid); + + assign iu1_nonspec_d = {`THREADS{iu0_erat_valid}} & iu0_erat_tid & next_fetch_nonspec_l2 & (~cp_flush); + assign iu2_nonspec_d = iu1_nonspec_l2 & (~cp_flush); + + // Tell CP if nonspec hit in ierat + assign ic_cp_nonspec_hit = iu2_nonspec_l2 & ~{`THREADS{ierat_iu_iu2_miss}} & + ~cp_flush_l2 & ~({`THREADS{icd_ics_iu2_valid}} & ierat_iu_iu2_flush_req & iu2_nonspec_l2); + + assign iu_ierat_flush = cp_flush_l2 | uc_iu4_flush | icd_ics_iu3_miss_flush | ({`THREADS{icd_ics_iu2_valid}} & icd_ics_iu2_cam_etc_flush) | + icd_ics_iu2_wrong_ra_flush | icd_ics_iu3_parity_flush | (bp_ic_iu2_redirect & (~icm_ics_iu3_ecc_fp_cancel)) | (bp_ic_iu3_redirect & (~icm_ics_iu3_ecc_fp_cancel)) | bp_ic_iu4_redirect | br_iu_redirect_l2 | iu1_ecc_flush; + assign ics_icm_iu2_flush = cp_flush_l2 | uc_iu4_flush | icd_ics_iu3_parity_flush | + (bp_ic_iu3_redirect & (~icm_ics_iu3_ecc_fp_cancel) & (~icd_ics_iu3_miss_flush)) | bp_ic_iu4_redirect | br_iu_redirect_l2; + assign ics_icd_iu1_flush = cp_flush_l2 | uc_iu4_flush | ({`THREADS{icd_ics_iu2_valid}} & (ierat_iu_iu2_flush_req | icd_ics_iu2_cam_etc_flush)) | + icd_ics_iu3_miss_flush | icd_ics_iu2_wrong_ra_flush | icd_ics_iu3_parity_flush | (bp_ic_iu2_redirect & (~icm_ics_iu3_ecc_fp_cancel)) | (bp_ic_iu3_redirect & (~icm_ics_iu3_ecc_fp_cancel)) | bp_ic_iu4_redirect | br_iu_redirect_l2 | iu1_ecc_flush; + assign ics_icd_iu2_flush = cp_flush_l2 | uc_iu4_flush | ierat_iu_iu2_flush_req | icd_ics_iu2_cam_etc_flush | icd_ics_iu3_miss_flush | icd_ics_iu2_wrong_ra_flush | (bp_ic_iu3_redirect & (~icm_ics_iu3_ecc_fp_cancel)) | icd_ics_iu3_parity_flush | bp_ic_iu4_redirect | br_iu_redirect_l2; + + assign ic_bp_iu2_flush = ierat_iu_iu2_flush_req | icd_ics_iu2_cam_etc_flush | icd_ics_iu2_wrong_ra_flush; + + assign iu0_flush = cp_flush_l2 | uc_iu4_flush | ({`THREADS{icd_ics_iu2_valid}} & (ierat_iu_iu2_flush_req | icd_ics_iu2_cam_etc_flush)) | + icd_ics_iu3_miss_flush | icd_ics_iu2_wrong_ra_flush | icd_ics_iu3_parity_flush | (bp_ic_iu2_redirect & (~icm_ics_iu3_ecc_fp_cancel)) | (bp_ic_iu3_redirect & (~icm_ics_iu3_ecc_fp_cancel)) | bp_ic_iu4_redirect | br_iu_redirect_l2 | iu1_ecc_flush; + + assign iu1_flush = cp_flush_l2 | uc_iu4_flush | ierat_iu_iu2_flush_req | ({`THREADS{icd_ics_iu2_valid}} & icd_ics_iu2_cam_etc_flush) | + icd_ics_iu3_miss_flush | icd_ics_iu2_wrong_ra_flush | icd_ics_iu3_parity_flush | (bp_ic_iu2_redirect & (~icm_ics_iu3_ecc_fp_cancel)) | (bp_ic_iu3_redirect & (~icm_ics_iu3_ecc_fp_cancel)) | bp_ic_iu4_redirect | br_iu_redirect_l2 | iu1_ecc_flush; + + assign iu2_flush = cp_flush_l2 | uc_iu4_flush | ierat_iu_iu2_flush_req | ({`THREADS{icd_ics_iu2_valid}} & icd_ics_iu2_cam_etc_flush) | + icd_ics_iu3_miss_flush | icd_ics_iu2_wrong_ra_flush | icd_ics_iu3_parity_flush | (bp_ic_iu3_redirect & (~icm_ics_iu3_ecc_fp_cancel)) | bp_ic_iu4_redirect | br_iu_redirect_l2; + + assign iu3_flush = cp_flush_l2 | uc_iu4_flush | icd_ics_iu3_parity_flush | bp_ic_iu4_redirect | br_iu_redirect_l2 | + (icd_ics_iu3_miss_flush & {`THREADS{icm_ics_iu3_miss_match}}); // used by toggle_flip. If miss matches, will use old page; if miss hits, next address should be the same that caused wrong_ra, so want to flip for new page + + assign ics_icm_iu0_t0_ifar = iu0_ifar_l2[0][46:52]; + `ifndef THREADS1 + assign ics_icm_iu0_t1_ifar = iu0_ifar_l2[1][46:52]; + `endif + + assign ics_icd_dir_rd_act = |(need_fetch_reduce & (~(hold_thread))) | back_inv_l2 | (spr_idir_read_l2 & ~icm_ics_hold_iu0) | (|(prefetch_ready)); + assign data_rd_act[0] = (iu0_tid[0] & (~(iu0_ifar_l2[0][51] ^ iu0_flip_index51_l2[0]))) | (iu0_tid[`THREADS - 1] & (~(iu0_ifar_l2[`THREADS - 1][51] ^ iu0_flip_index51_l2[`THREADS - 1]))); + assign data_rd_act[1] = (iu0_tid[0] & (iu0_ifar_l2[0][51] ^ iu0_flip_index51_l2[0])) | (iu0_tid[`THREADS - 1] & (iu0_ifar_l2[`THREADS - 1][51] ^ iu0_flip_index51_l2[`THREADS - 1])); + assign ics_icd_data_rd_act = data_rd_act; + + assign iu0_valid = |(iu0_tid & (~iu0_flush)); + assign ics_icd_iu0_valid = iu0_valid; + assign ics_icd_iu0_tid = iu0_tid | next_prefetch; + + generate + begin + if (`THREADS == 1) + begin : gen_bp_iu0_val_t0 + assign ic_bp_iu0_val[0] = iu0_tid[0] | icm_ics_iu0_preload_val[0]; + end + + if (`THREADS == 2) + begin : gen_bp_iu0_val + assign ic_bp_iu0_val[0] = (iu0_tid[0] & (~icm_ics_iu0_preload_val[`THREADS - 1])) | icm_ics_iu0_preload_val[0]; + assign ic_bp_iu0_val[`THREADS - 1] = (iu0_tid[`THREADS - 1] & (~icm_ics_iu0_preload_val[0])) | icm_ics_iu0_preload_val[`THREADS - 1]; + end + end + endgenerate + + assign ic_bp_iu0_ifar = (|(icm_ics_iu0_preload_val) == 1'b1) ? icm_ics_iu0_preload_ifar[50:59] : + (iu0_tid[0] == 1'b1) ? iu0_ifar_l2[0][50:59] : + iu0_ifar_l2[`THREADS - 1][50:59]; + + generate + begin + if (`EFF_IFAR_ARCH > (`REAL_IFAR_WIDTH-2)) + begin : iu0_ifar_gen0 + + assign iu0_ifar = ({`EFF_IFAR_ARCH{(~(back_inv_l2 | spr_idir_read_l2)) & iu0_tid[0]}} & iu0_ifar_l2[0]) | + ({`EFF_IFAR_ARCH{(~(back_inv_l2 | spr_idir_read_l2)) & iu0_tid[`THREADS-1]}} & iu0_ifar_l2[`THREADS-1]) | // should be duplicate if 1 thread + ({ {(`EFF_IFAR_ARCH - `REAL_IFAR_WIDTH + 2){1'b0}}, ({(`REAL_IFAR_WIDTH-6){(back_inv_l2 & (~|(back_inv_icbi_l2)))}} & an_ac_back_inv_addr_l2), 4'b0000 }) | + ({ {(`EFF_IFAR_ARCH - `REAL_IFAR_WIDTH + 2){1'b0}}, ({(`REAL_IFAR_WIDTH-6){back_inv_icbi_l2[0]}} & lq_iu_icbi_addr_l2[0]), 4'b0000 }) | // back_inv_l2 includes back_inv_icbi_l2, was redundant + ({ {(`EFF_IFAR_ARCH - `REAL_IFAR_WIDTH + 2){1'b0}}, ({(`REAL_IFAR_WIDTH-6){back_inv_icbi_l2[`THREADS - 1]}} & lq_iu_icbi_addr_l2[`THREADS - 1]), 4'b0000}) | + ({ {(`EFF_IFAR_ARCH - 11){1'b0}}, ({7{(~(back_inv_l2)) & spr_idir_read_l2}} & spr_idir_row_l2), 4'b0000}) | + ({ ({(`EFF_IFAR_ARCH-4){next_prefetch[0]}} & {iu0_ifar_l2[0][62-`EFF_IFAR_ARCH:62-`EFF_IFAR_WIDTH-1], iu0_prefetch_ifar_l2[0]}), 4'b0000}) | + ({ ({(`EFF_IFAR_ARCH-4){next_prefetch[`THREADS - 1]}} & {iu0_ifar_l2[`THREADS-1][62-`EFF_IFAR_ARCH:62-`EFF_IFAR_WIDTH-1], iu0_prefetch_ifar_l2[`THREADS-1]}), 4'b0000}); + end + + if (`EFF_IFAR_ARCH <= (`REAL_IFAR_WIDTH-2)) + begin : iu0_ifar_gen1 + assign iu0_ifar = ({`EFF_IFAR_ARCH{(~(back_inv_l2 | spr_idir_read_l2)) & iu0_tid[0]}} & iu0_ifar_l2[0]) | + ({`EFF_IFAR_ARCH{(~(back_inv_l2 | spr_idir_read_l2)) & iu0_tid[`THREADS-1]}} & iu0_ifar_l2[`THREADS-1]) | + ({ ({`EFF_IFAR_ARCH-4{back_inv_l2 & (~|(back_inv_icbi_l2))}} & an_ac_back_inv_addr_l2[62-`EFF_IFAR_ARCH:57]), 4'b0000}) | + ({ ({`EFF_IFAR_ARCH-4{back_inv_icbi_l2[0]}} & lq_iu_icbi_addr_l2[0][62-`EFF_IFAR_ARCH:57]), 4'b0000}) | // back_inv_l2 includes back_inv_icbi_l2, was redundant + ({ ({`EFF_IFAR_ARCH-4{back_inv_icbi_l2[`THREADS-1]}} & lq_iu_icbi_addr_l2[`THREADS-1][62-`EFF_IFAR_ARCH:57]), 4'b0000}) | + ({ {(`EFF_IFAR_ARCH - 11){1'b0}}, ({7{(~(back_inv_l2)) & spr_idir_read_l2}} & spr_idir_row_l2), 4'b0000}) | + ({ ({(`EFF_IFAR_ARCH-4){next_prefetch[0]}} & {iu0_ifar_l2[0][62-`EFF_IFAR_ARCH:62-`EFF_IFAR_WIDTH-1], iu0_prefetch_ifar_l2[0]}), 4'b0000}) | + ({ ({(`EFF_IFAR_ARCH-4){next_prefetch[`THREADS-1]}} & {iu0_ifar_l2[`THREADS-1][62-`EFF_IFAR_ARCH:62-`EFF_IFAR_WIDTH-1], iu0_prefetch_ifar_l2[`THREADS-1]}), 4'b0000}); + end + end + endgenerate + + assign ics_icd_iu0_ifar = iu0_ifar; + assign ics_icd_iu0_index51 = ( ((~(back_inv_l2 | spr_idir_read_l2)) & iu0_tid[0]) & (iu0_ifar_l2[0][51] ^ iu0_flip_index51_l2[0])) | + ( ((~(back_inv_l2 | spr_idir_read_l2)) & iu0_tid[`THREADS - 1]) & (iu0_ifar_l2[`THREADS - 1][51] ^ iu0_flip_index51_l2[`THREADS - 1])) | // should be duplicate if `THREADS=1 + ( (back_inv_l2 & (~|(back_inv_icbi_l2))) & an_ac_back_inv_addr_l2[51]) | + ( back_inv_icbi_l2[0] & lq_iu_icbi_addr_l2[0][51]) | // back_inv_l2 includes back_inv_icbi_l2, was redundant + ( back_inv_icbi_l2[`THREADS - 1] & lq_iu_icbi_addr_l2[`THREADS - 1][51]) | + ( ((~(back_inv_l2)) & spr_idir_read_l2) & spr_idir_row_l2[51]) | + ( next_prefetch[0] & (iu0_prefetch_ifar_l2[0][51] ^ iu0_flip_index51_l2[0])) | + ( next_prefetch[`THREADS - 1] & (iu0_prefetch_ifar_l2[`THREADS - 1][51] ^ iu0_flip_index51_l2[`THREADS - 1])); + + assign ics_icd_iu0_2ucode = |(iu0_2ucode_l2 & iu0_tid); + assign ics_icd_iu0_2ucode_type = |(iu0_2ucode_type_l2 & iu0_tid); + + assign ics_icd_iu0_inval = back_inv_l2; + assign ics_icm_iu0_inval = back_inv_l2; + + assign ics_icm_iu0_inval_addr = ( {7{back_inv_l2 & (~|(back_inv_icbi_l2))}} & an_ac_back_inv_addr_l2[51:57]) | + ( {7{back_inv_icbi_l2[0]}} & lq_iu_icbi_addr_l2[0][51:57]) | + ( {7{back_inv_icbi_l2[`THREADS - 1]}} & lq_iu_icbi_addr_l2[`THREADS - 1][51:57]); + + // Block prefetch if new prefetch req on this thread + assign ics_icd_iu0_prefetch = |(send_prefetch & ~(icm_ics_prefetch_req & ~{`THREADS{prefetch_wrap}})); + + //--------------------------------------------------------------------- + // Performance Events + //--------------------------------------------------------------------- + + generate + begin : xhdl9 + genvar i; + for (i = 0; i < `THREADS; i = i + 1) + begin : perf + // Reload Collisions - Blocked by reload writing into the cache + assign perf_event_d[i][3] = icm_ics_hold_iu0 & need_fetch_reduce[i] & ~hold_thread_perf_lite[i]; + + // IU0 Redirected - any flush condition + assign perf_event_d[i][4] = iu0_flush[i]; + + // Various flushes: BP iu2, BP iu3, BP iu4, uc + assign perf_event_d[i][5] = bp_ic_iu2_redirect[i] & ~icm_ics_iu3_ecc_fp_cancel[i]; + assign perf_event_d[i][6] = bp_ic_iu3_redirect[i] & ~icm_ics_iu3_ecc_fp_cancel[i]; + assign perf_event_d[i][7] = bp_ic_iu4_redirect[i]; + assign perf_event_d[i][8] = uc_iu4_flush[i]; + end + end + endgenerate + + assign ic_perf_t0_event = perf_event_l2[0]; + `ifndef THREADS1 + assign ic_perf_t1_event = perf_event_l2[1]; + `endif + + //--------------------------------------------------------------------- + // Latches + //--------------------------------------------------------------------- + + tri_rlmlatch_p #(.INIT(0)) an_ac_back_inv_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_slp_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(funcslp_force), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[an_ac_back_inv_offset]), + .scout(sov[an_ac_back_inv_offset]), + .din(an_ac_back_inv_d), + .dout(an_ac_back_inv_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) an_ac_back_inv_target_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_slp_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(funcslp_force), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[an_ac_back_inv_target_offset]), + .scout(sov[an_ac_back_inv_target_offset]), + .din(an_ac_back_inv_target_d), + .dout(an_ac_back_inv_target_l2) + ); + + tri_rlmreg_p #(.WIDTH(`REAL_IFAR_WIDTH-6), .INIT(0)) an_ac_back_inv_addr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(back_inv_addr_act), //back_inv_d, + .thold_b(pc_iu_func_slp_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(funcslp_force), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[an_ac_back_inv_addr_offset:an_ac_back_inv_addr_offset + (`REAL_IFAR_WIDTH-6) - 1]), + .scout(sov[an_ac_back_inv_addr_offset:an_ac_back_inv_addr_offset + (`REAL_IFAR_WIDTH-6) - 1]), + .din(an_ac_back_inv_addr_d), + .dout(an_ac_back_inv_addr_l2) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_idir_read_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[spr_idir_read_offset]), + .scout(sov[spr_idir_read_offset]), + .din(spr_idir_read_d), + .dout(spr_idir_read_l2) + ); + + tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(0)) spr_idir_row_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[spr_idir_row_offset:spr_idir_row_offset + 7 - 1]), + .scout(sov[spr_idir_row_offset:spr_idir_row_offset + 7 - 1]), + .din(spr_idir_row_d), + .dout(spr_idir_row_l2) + ); + + generate + begin + if (`THREADS == 1) + begin : gen_oldest_t1 + assign oldest_prefetch_l2 = oldest_prefetch_d & 1'b0; + end + + if (`THREADS > 1) + begin : gen_oldest_t2 + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) oldest_prefetch_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[oldest_prefetch_offset]), + .scout(sov[oldest_prefetch_offset]), + .din(oldest_prefetch_d), + .dout(oldest_prefetch_l2) + ); + end + end + endgenerate + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu0_need_prefetch_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu0_need_prefetch_offset:iu0_need_prefetch_offset + `THREADS - 1]), + .scout(sov[iu0_need_prefetch_offset:iu0_need_prefetch_offset + `THREADS - 1]), + .din(iu0_need_prefetch_d), + .dout(iu0_need_prefetch_l2) + ); + + generate + begin : xhdl10 + genvar i; + for (i = 0; i < `THREADS; i = i + 1) + begin : t + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH-4), .INIT(0)) iu0_prefetch_ifar_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu0_prefetch_ifar_act[i]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu0_prefetch_ifar_offset + i * (`EFF_IFAR_WIDTH-4):iu0_prefetch_ifar_offset + ((i + 1) * (`EFF_IFAR_WIDTH-4)) - 1]), + .scout(sov[iu0_prefetch_ifar_offset + i * (`EFF_IFAR_WIDTH-4):iu0_prefetch_ifar_offset + ((i + 1) * (`EFF_IFAR_WIDTH-4)) - 1]), + .din(iu0_prefetch_ifar_d[i]), + .dout(iu0_prefetch_ifar_l2[i]) + ); + end + end + endgenerate + + tri_rlmreg_p #(.WIDTH((`THREADS*`THREADS-1+1)), .INIT(0)) lq_iu_icbi_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[lq_iu_icbi_val_offset:lq_iu_icbi_val_offset + (`THREADS*`THREADS-1+1) - 1]), + .scout(sov[lq_iu_icbi_val_offset:lq_iu_icbi_val_offset + (`THREADS*`THREADS-1+1) - 1]), + .din(lq_iu_icbi_val_d), + .dout(lq_iu_icbi_val_l2) + ); + + generate + begin : xhdl11 + genvar i; + for (i = 0; i < `THREADS; i = i + 1) + begin : t + tri_rlmreg_p #(.WIDTH(`REAL_IFAR_WIDTH-6), .INIT(0)) lq_iu_icbi_addr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lq_iu_icbi_val[i]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[lq_iu_icbi_addr_offset + i * (`REAL_IFAR_WIDTH-6):lq_iu_icbi_addr_offset + ((i + 1) * (`REAL_IFAR_WIDTH-6)) - 1]), + .scout(sov[lq_iu_icbi_addr_offset + i * (`REAL_IFAR_WIDTH-6):lq_iu_icbi_addr_offset + ((i + 1) * (`REAL_IFAR_WIDTH-6)) - 1]), + .din(lq_iu_icbi_addr_d[i]), + .dout(lq_iu_icbi_addr_l2[i]) + ); + end + end + endgenerate + + tri_rlmlatch_p #(.INIT(0)) back_inv_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_slp_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(funcslp_force), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[back_inv_offset]), + .scout(sov[back_inv_offset]), + .din(back_inv_d), + .dout(back_inv_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) back_inv_icbi_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[back_inv_icbi_offset:back_inv_icbi_offset + `THREADS - 1]), + .scout(sov[back_inv_icbi_offset:back_inv_icbi_offset + `THREADS - 1]), + .din(back_inv_icbi_d), + .dout(back_inv_icbi_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) xu_iu_run_thread_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[xu_iu_run_thread_offset:xu_iu_run_thread_offset + `THREADS - 1]), + .scout(sov[xu_iu_run_thread_offset:xu_iu_run_thread_offset + `THREADS - 1]), + .din(xu_iu_run_thread_d), + .dout(xu_iu_run_thread_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) xu_iu_msr_cm_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[xu_iu_msr_cm_offset:xu_iu_msr_cm_offset + `THREADS - 1]), + .scout(sov[xu_iu_msr_cm_offset:xu_iu_msr_cm_offset + `THREADS - 1]), + .din(xu_iu_msr_cm_d), + .dout(xu_iu_msr_cm_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) xu_iu_msr_cm2_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[xu_iu_msr_cm2_offset:xu_iu_msr_cm2_offset + `THREADS - 1]), + .scout(sov[xu_iu_msr_cm2_offset:xu_iu_msr_cm2_offset + `THREADS - 1]), + .din(xu_iu_msr_cm2_d), + .dout(xu_iu_msr_cm2_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) xu_iu_msr_cm3_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[xu_iu_msr_cm3_offset:xu_iu_msr_cm3_offset + `THREADS - 1]), + .scout(sov[xu_iu_msr_cm3_offset:xu_iu_msr_cm3_offset + `THREADS - 1]), + .din(xu_iu_msr_cm3_d), + .dout(xu_iu_msr_cm3_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) cp_ic_stop_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[cp_ic_stop_offset:cp_ic_stop_offset + `THREADS - 1]), + .scout(sov[cp_ic_stop_offset:cp_ic_stop_offset + `THREADS - 1]), + .din(cp_ic_stop_d), + .dout(cp_ic_stop_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) pc_iu_pm_fetch_halt_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[pc_iu_pm_fetch_halt_offset:pc_iu_pm_fetch_halt_offset + `THREADS - 1]), + .scout(sov[pc_iu_pm_fetch_halt_offset:pc_iu_pm_fetch_halt_offset + `THREADS - 1]), + .din(pc_iu_pm_fetch_halt_d), + .dout(pc_iu_pm_fetch_halt_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) ierat_hold_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[ierat_hold_offset:ierat_hold_offset + `THREADS - 1]), + .scout(sov[ierat_hold_offset:ierat_hold_offset + `THREADS - 1]), + .din(ierat_hold_d), + .dout(ierat_hold_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu0_2ucode_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_slp_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(funcslp_force), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu0_2ucode_offset:iu0_2ucode_offset + `THREADS - 1]), + .scout(sov[iu0_2ucode_offset:iu0_2ucode_offset + `THREADS - 1]), + .din(iu0_2ucode_d), + .dout(iu0_2ucode_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu0_2ucode_type_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_slp_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(funcslp_force), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu0_2ucode_type_offset:iu0_2ucode_type_offset + `THREADS - 1]), + .scout(sov[iu0_2ucode_type_offset:iu0_2ucode_type_offset + `THREADS - 1]), + .din(iu0_2ucode_type_d), + .dout(iu0_2ucode_type_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu0_flip_index51_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu0_flip_index51_offset:iu0_flip_index51_offset + `THREADS - 1]), + .scout(sov[iu0_flip_index51_offset:iu0_flip_index51_offset + `THREADS - 1]), + .din(iu0_flip_index51_d), + .dout(iu0_flip_index51_l2) + ); + + generate + begin + if (`THREADS == 1) + begin : gen_last_tid_t1 + assign iu0_last_tid_sent_l2 = 1'b0 & iu0_last_tid_sent_d; + end + + if (`THREADS > 1) + begin : gen_last_tid_t2 + tri_rlmlatch_p #(.INIT(0)) iu0_last_tid_sent_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu0_last_tid_sent_offset]), + .scout(sov[iu0_last_tid_sent_offset]), + .din(iu0_last_tid_sent_d), + .dout(iu0_last_tid_sent_l2) + ); + end + end + endgenerate + + generate + begin : xhdl13 + genvar t; + for (t = 0; t < `THREADS; t = t + 1) + begin : th + genvar i; + for (i = 0; i < `IBUFF_DEPTH/4; i = i + 1) + begin : ibuff + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu0_sent_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu0_sent_offset + (t * (`IBUFF_DEPTH/4) + i) * 3:iu0_sent_offset + (t * (`IBUFF_DEPTH/4) + i + 1) * 3 - 1]), + .scout(sov[iu0_sent_offset + (t * (`IBUFF_DEPTH/4) + i) * 3:iu0_sent_offset + (t * (`IBUFF_DEPTH/4) + i + 1) * 3 - 1]), + .din(iu0_sent_d[t][i]), + .dout(iu0_sent_l2[t][i]) + ); + end + end + end + endgenerate + + // IU0 + generate + begin : xhdl14 + genvar t; + for (t = 0; t < `THREADS; t = t + 1) + begin : th + genvar i; + for (i = 0; i < `EFF_IFAR_ARCH; i = i + 1) + begin : q_gen + if((62-`EFF_IFAR_ARCH+i) > 31) + tri_rlmlatch_p #(.INIT(1), .NEEDS_SRESET(1)) iu0_ifar_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_slp_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(funcslp_force), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu0_ifar_offset + t * `EFF_IFAR_ARCH + i]), + .scout(sov[iu0_ifar_offset + t * `EFF_IFAR_ARCH + i]), + .din(iu0_ifar_d[t][62 - `EFF_IFAR_ARCH + i]), + .dout(iu0_ifar_l2[t][62 - `EFF_IFAR_ARCH + i]) + ); + else + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu0_ifar_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_slp_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(funcslp_force), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu0_ifar_offset + t * `EFF_IFAR_ARCH + i]), + .scout(sov[iu0_ifar_offset + t * `EFF_IFAR_ARCH + i]), + .din(iu0_ifar_d[t][62 - `EFF_IFAR_ARCH + i]), + .dout(iu0_ifar_l2[t][62 - `EFF_IFAR_ARCH + i]) + ); + end + end + end + endgenerate + + generate + begin : xhdl15 + if (`INCLUDE_IERAT_BYPASS == 0) + begin : gen0 + genvar i; + for (i = 0; i < `THREADS; i = i + 1) + begin : t + //assign stored_erat_ifar_l2[i] = gate_and(1'b0, stored_erat_ifar_d[i]); // ..._d part is to get rid of unused warnings + //assign stored_erat_valid_l2[i] = gate_and(1'b0, stored_erat_valid_d[i]); // '0' + end + + assign sov[stored_erat_ifar_offset:stored_erat_valid_offset + `THREADS - 1] = siv[stored_erat_ifar_offset:stored_erat_valid_offset + `THREADS - 1]; + end + + if (`INCLUDE_IERAT_BYPASS == 1) + begin : gen1 + genvar i; + for (i = 0; i < `THREADS; i = i + 1) + begin : t + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH-10), .INIT(0)) stored_erat_ifar_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stored_erat_act[i]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stored_erat_ifar_offset + i * (`EFF_IFAR_WIDTH-10):stored_erat_ifar_offset + ((i + 1) * (`EFF_IFAR_WIDTH-10)) - 1]), + .scout(sov[stored_erat_ifar_offset + i * (`EFF_IFAR_WIDTH-10):stored_erat_ifar_offset + ((i + 1) * (`EFF_IFAR_WIDTH-10)) - 1]), + .din(stored_erat_ifar_d[i]), + .dout(stored_erat_ifar_l2[i]) + ); + end + end + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) stored_erat_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_slp_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(funcslp_force), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stored_erat_valid_offset:stored_erat_valid_offset + `THREADS - 1]), + .scout(sov[stored_erat_valid_offset:stored_erat_valid_offset + `THREADS - 1]), + .din(stored_erat_valid_d), + .dout(stored_erat_valid_l2) + ); + end + endgenerate + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) mm_hold_req_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_slp_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(funcslp_force), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[mm_hold_req_offset:mm_hold_req_offset + `THREADS - 1]), + .scout(sov[mm_hold_req_offset:mm_hold_req_offset + `THREADS - 1]), + .din(mm_hold_req_d), + .dout(mm_hold_req_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) mm_bus_snoop_hold_req_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_slp_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(funcslp_force), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[mm_bus_snoop_hold_req_offset:mm_bus_snoop_hold_req_offset + `THREADS - 1]), + .scout(sov[mm_bus_snoop_hold_req_offset:mm_bus_snoop_hold_req_offset + `THREADS - 1]), + .din(mm_bus_snoop_hold_req_d), + .dout(mm_bus_snoop_hold_req_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) cp_flush_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_slp_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(funcslp_force), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[cp_flush_offset:cp_flush_offset + `THREADS - 1]), + .scout(sov[cp_flush_offset:cp_flush_offset + `THREADS - 1]), + .din(cp_flush), + .dout(cp_flush_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) cp_flush_into_uc_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_slp_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(funcslp_force), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[cp_flush_into_uc_offset:cp_flush_into_uc_offset + `THREADS - 1]), + .scout(sov[cp_flush_into_uc_offset:cp_flush_into_uc_offset + `THREADS - 1]), + .din(cp_flush_into_uc), + .dout(cp_flush_into_uc_l2) + ); + + generate + begin : xhdl17 + genvar i; + for (i = 0; i < `THREADS; i = i + 1) + begin : t + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0)) cp_flush_ifar_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_slp_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(funcslp_force), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[cp_flush_ifar_offset + i * `EFF_IFAR_ARCH:cp_flush_ifar_offset + (i + 1) * `EFF_IFAR_ARCH - 1]), + .scout(sov[cp_flush_ifar_offset + i * `EFF_IFAR_ARCH:cp_flush_ifar_offset + (i + 1) * `EFF_IFAR_ARCH - 1]), + .din(cp_flush_ifar_d[i]), + .dout(cp_flush_ifar_l2[i]) + ); + end + end + endgenerate + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) cp_flush_2ucode_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_slp_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(funcslp_force), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[cp_flush_2ucode_offset:cp_flush_2ucode_offset + `THREADS - 1]), + .scout(sov[cp_flush_2ucode_offset:cp_flush_2ucode_offset + `THREADS - 1]), + .din(cp_iu0_flush_2ucode), + .dout(cp_flush_2ucode_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) cp_flush_2ucode_type_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_slp_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(funcslp_force), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[cp_flush_2ucode_type_offset:cp_flush_2ucode_type_offset + `THREADS - 1]), + .scout(sov[cp_flush_2ucode_type_offset:cp_flush_2ucode_type_offset + `THREADS - 1]), + .din(cp_iu0_flush_2ucode_type), + .dout(cp_flush_2ucode_type_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) cp_flush_nonspec_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_slp_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(funcslp_force), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[cp_flush_nonspec_offset:cp_flush_nonspec_offset + `THREADS - 1]), + .scout(sov[cp_flush_nonspec_offset:cp_flush_nonspec_offset + `THREADS - 1]), + .din(cp_iu0_flush_nonspec), + .dout(cp_flush_nonspec_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) br_iu_redirect_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[br_iu_redirect_offset:br_iu_redirect_offset + `THREADS - 1]), + .scout(sov[br_iu_redirect_offset:br_iu_redirect_offset + `THREADS - 1]), + .din(br_iu_redirect_d), + .dout(br_iu_redirect_l2) + ); + + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0)) br_iu_bta_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[br_iu_bta_offset:br_iu_bta_offset + `EFF_IFAR_ARCH - 1]), + .scout(sov[br_iu_bta_offset:br_iu_bta_offset + `EFF_IFAR_ARCH - 1]), + .din(br_iu_bta), + .dout(br_iu_bta_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) next_fetch_nonspec_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[next_fetch_nonspec_offset:next_fetch_nonspec_offset + `THREADS - 1]), + .scout(sov[next_fetch_nonspec_offset:next_fetch_nonspec_offset + `THREADS - 1]), + .din(next_fetch_nonspec_d), + .dout(next_fetch_nonspec_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu1_nonspec_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu1_nonspec_offset:iu1_nonspec_offset + `THREADS - 1]), + .scout(sov[iu1_nonspec_offset:iu1_nonspec_offset + `THREADS - 1]), + .din(iu1_nonspec_d), + .dout(iu1_nonspec_l2) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu2_nonspec_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu2_nonspec_offset:iu2_nonspec_offset + `THREADS - 1]), + .scout(sov[iu2_nonspec_offset:iu2_nonspec_offset + `THREADS - 1]), + .din(iu2_nonspec_d), + .dout(iu2_nonspec_l2) + ); + + generate + begin : xhdl18 + genvar i; + for (i = 0; i < `THREADS; i = i + 1) + begin : t + tri_rlmreg_p #(.WIDTH(6), .INIT(0)) perf_event_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(event_bus_enable), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[perf_event_offset + i * 6:perf_event_offset + (i + 1) * 6 - 1]), + .scout(sov[perf_event_offset + i * 6:perf_event_offset + (i + 1) * 6 - 1]), + .din(perf_event_d[i]), + .dout(perf_event_l2[i]) + ); + end + end + endgenerate + + //--------------------------------------------------------------------- + // Scan + //--------------------------------------------------------------------- + assign siv[0:scan_right] = {sov[1:scan_right], func_scan_in}; + assign func_scan_out = sov[0]; + +endmodule diff --git a/dev/verilog/work/iuq_idec.v b/dev/verilog/work/iuq_idec.v new file mode 100755 index 0000000..1514ef0 --- /dev/null +++ b/dev/verilog/work/iuq_idec.v @@ -0,0 +1,6854 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// VHDL 1076 Macro Expander C version 07/11/00 +// job was run on Thu Apr 14 13:14:38 2011 + +//******************************************************************** +//* +//* TITLE: +//* +//* NAME: iuq_idec.v +//* +//********************************************************************* + +module iuq_idec( + vdd, + gnd, + nclk, + pc_iu_sg_2, + pc_iu_func_sl_thold_2, + clkoff_b, + act_dis, + tc_ac_ccflush_dc, + d_mode, + delay_lclkr, + mpw1_b, + mpw2_b, + scan_in, + scan_out, + xu_iu_epcr_dgtmi, + xu_iu_msrp_uclep, + xu_iu_msr_pr, + xu_iu_msr_gs, + xu_iu_msr_ucle, + xu_iu_ccr2_ucode_dis, + mm_iu_tlbwe_binv, + spr_dec_mask, + spr_dec_match, + cp_iu_iu4_flush, + uc_ib_iu3_flush_all, + br_iu_redirect, + ib_id_iu4_valid, + ib_id_iu4_ifar, + ib_id_iu4_bta, + ib_id_iu4_instr, + ib_id_iu4_ucode, + ib_id_iu4_ucode_ext, + ib_id_iu4_isram, + ib_id_iu4_fuse_val, + ib_id_iu4_fuse_data, + au_iu_iu4_i_dec_b, + au_iu_iu4_ucode, + au_iu_iu4_t1_v, + au_iu_iu4_t1_t, + au_iu_iu4_t1_a, + au_iu_iu4_t2_v, + au_iu_iu4_t2_a, + au_iu_iu4_t2_t, + au_iu_iu4_t3_v, + au_iu_iu4_t3_a, + au_iu_iu4_t3_t, + au_iu_iu4_s1_v, + au_iu_iu4_s1_a, + au_iu_iu4_s1_t, + au_iu_iu4_s2_v, + au_iu_iu4_s2_a, + au_iu_iu4_s2_t, + au_iu_iu4_s3_v, + au_iu_iu4_s3_a, + au_iu_iu4_s3_t, + au_iu_iu4_ilat, + au_iu_iu4_ord, + au_iu_iu4_cord, + au_iu_iu4_spec, + au_iu_iu4_type_fp, + au_iu_iu4_type_ap, + au_iu_iu4_type_spv, + au_iu_iu4_type_st, + au_iu_iu4_async_block, + au_iu_iu4_isload, + au_iu_iu4_isstore, + au_iu_iu4_rte_lq, + au_iu_iu4_rte_sq, + au_iu_iu4_rte_axu0, + au_iu_iu4_rte_axu1, + au_iu_iu4_no_ram, + fdec_frn_iu5_ix_vld, + fdec_frn_iu5_ix_ucode, + fdec_frn_iu5_ix_2ucode, + fdec_frn_iu5_ix_fuse_nop, + fdec_frn_iu5_ix_rte_lq, + fdec_frn_iu5_ix_rte_sq, + fdec_frn_iu5_ix_rte_fx0, + fdec_frn_iu5_ix_rte_fx1, + fdec_frn_iu5_ix_rte_axu0, + fdec_frn_iu5_ix_rte_axu1, + fdec_frn_iu5_ix_valop, + fdec_frn_iu5_ix_ord, + fdec_frn_iu5_ix_cord, + fdec_frn_iu5_ix_error, + fdec_frn_iu5_ix_fusion, + fdec_frn_iu5_ix_spec, + fdec_frn_iu5_ix_type_fp, + fdec_frn_iu5_ix_type_ap, + fdec_frn_iu5_ix_type_spv, + fdec_frn_iu5_ix_type_st, + fdec_frn_iu5_ix_async_block, + fdec_frn_iu5_ix_np1_flush, + fdec_frn_iu5_ix_core_block, + fdec_frn_iu5_ix_isram, + fdec_frn_iu5_ix_isload, + fdec_frn_iu5_ix_isstore, + fdec_frn_iu5_ix_instr, + fdec_frn_iu5_ix_ifar, + fdec_frn_iu5_ix_bta, + fdec_frn_iu5_ix_ilat, + fdec_frn_iu5_ix_t1_v, + fdec_frn_iu5_ix_t1_t, + fdec_frn_iu5_ix_t1_a, + fdec_frn_iu5_ix_t2_v, + fdec_frn_iu5_ix_t2_a, + fdec_frn_iu5_ix_t2_t, + fdec_frn_iu5_ix_t3_v, + fdec_frn_iu5_ix_t3_a, + fdec_frn_iu5_ix_t3_t, + fdec_frn_iu5_ix_s1_v, + fdec_frn_iu5_ix_s1_a, + fdec_frn_iu5_ix_s1_t, + fdec_frn_iu5_ix_s2_v, + fdec_frn_iu5_ix_s2_a, + fdec_frn_iu5_ix_s2_t, + fdec_frn_iu5_ix_s3_v, + fdec_frn_iu5_ix_s3_a, + fdec_frn_iu5_ix_s3_t, + fdec_frn_iu5_ix_br_pred, + fdec_frn_iu5_ix_bh_update, + fdec_frn_iu5_ix_bh0_hist, + fdec_frn_iu5_ix_bh1_hist, + fdec_frn_iu5_ix_bh2_hist, + fdec_frn_iu5_ix_gshare, + fdec_frn_iu5_ix_ls_ptr, + fdec_frn_iu5_ix_match, + fdec_frn_iu5_ix_btb_entry, + fdec_frn_iu5_ix_btb_hist, + fdec_frn_iu5_ix_bta_val, + frn_fdec_iu5_stall +); +// parameter `GPR_WIDTH = 64; +// parameter `EFF_IFAR_ARCH = 62; +// parameter `EFF_IFAR_WIDTH = 20; +// parameter `GPR_POOL_ENC = 6; +`include "tri_a2o.vh" + inout vdd; + inout gnd; + input [0:`NCLK_WIDTH-1] nclk; + input pc_iu_sg_2; + input pc_iu_func_sl_thold_2; + input clkoff_b; + input act_dis; + input tc_ac_ccflush_dc; + input d_mode; + input delay_lclkr; + input mpw1_b; + input mpw2_b; + input scan_in; + output scan_out; + + input xu_iu_epcr_dgtmi; + input xu_iu_msrp_uclep; + input xu_iu_msr_pr; + input xu_iu_msr_gs; + input xu_iu_msr_ucle; + input xu_iu_ccr2_ucode_dis; + input mm_iu_tlbwe_binv; + + input [0:31] spr_dec_mask; + input [0:31] spr_dec_match; + + input cp_iu_iu4_flush; + input uc_ib_iu3_flush_all; + input br_iu_redirect; + + input ib_id_iu4_valid; + input [62-`EFF_IFAR_WIDTH:61] ib_id_iu4_ifar; + input [62-`EFF_IFAR_WIDTH:61] ib_id_iu4_bta; + input [0:69] ib_id_iu4_instr; + input [0:2] ib_id_iu4_ucode; + input [0:3] ib_id_iu4_ucode_ext; + input ib_id_iu4_isram; + input ib_id_iu4_fuse_val; + input [0:31] ib_id_iu4_fuse_data; + + input au_iu_iu4_i_dec_b; + input [0:2] au_iu_iu4_ucode; + input au_iu_iu4_t1_v; + input [0:2] au_iu_iu4_t1_t; + input [0:`GPR_POOL_ENC-1] au_iu_iu4_t1_a; + input au_iu_iu4_t2_v; + input [0:`GPR_POOL_ENC-1] au_iu_iu4_t2_a; + input [0:2] au_iu_iu4_t2_t; + input au_iu_iu4_t3_v; + input [0:`GPR_POOL_ENC-1] au_iu_iu4_t3_a; + input [0:2] au_iu_iu4_t3_t; + input au_iu_iu4_s1_v; + input [0:`GPR_POOL_ENC-1] au_iu_iu4_s1_a; + input [0:2] au_iu_iu4_s1_t; + input au_iu_iu4_s2_v; + input [0:`GPR_POOL_ENC-1] au_iu_iu4_s2_a; + input [0:2] au_iu_iu4_s2_t; + input au_iu_iu4_s3_v; + input [0:`GPR_POOL_ENC-1] au_iu_iu4_s3_a; + input [0:2] au_iu_iu4_s3_t; + input [0:2] au_iu_iu4_ilat; + input au_iu_iu4_ord; + input au_iu_iu4_cord; + input au_iu_iu4_spec; + input au_iu_iu4_type_fp; + input au_iu_iu4_type_ap; + input au_iu_iu4_type_spv; + input au_iu_iu4_type_st; + input au_iu_iu4_async_block; + input au_iu_iu4_isload; + input au_iu_iu4_isstore; + input au_iu_iu4_rte_lq; + input au_iu_iu4_rte_sq; + input au_iu_iu4_rte_axu0; + input au_iu_iu4_rte_axu1; + input au_iu_iu4_no_ram; + + output fdec_frn_iu5_ix_vld; + output [0:2] fdec_frn_iu5_ix_ucode; + output fdec_frn_iu5_ix_2ucode; + output fdec_frn_iu5_ix_fuse_nop; + output fdec_frn_iu5_ix_rte_lq; + output fdec_frn_iu5_ix_rte_sq; + output fdec_frn_iu5_ix_rte_fx0; + output fdec_frn_iu5_ix_rte_fx1; + output fdec_frn_iu5_ix_rte_axu0; + output fdec_frn_iu5_ix_rte_axu1; + output fdec_frn_iu5_ix_valop; + output fdec_frn_iu5_ix_ord; + output fdec_frn_iu5_ix_cord; + output [0:2] fdec_frn_iu5_ix_error; + output [0:19] fdec_frn_iu5_ix_fusion; + output fdec_frn_iu5_ix_spec; + output fdec_frn_iu5_ix_type_fp; + output fdec_frn_iu5_ix_type_ap; + output fdec_frn_iu5_ix_type_spv; + output fdec_frn_iu5_ix_type_st; + output fdec_frn_iu5_ix_async_block; + output fdec_frn_iu5_ix_np1_flush; + output fdec_frn_iu5_ix_core_block; + output fdec_frn_iu5_ix_isram; + output fdec_frn_iu5_ix_isload; + output fdec_frn_iu5_ix_isstore; + output [0:31] fdec_frn_iu5_ix_instr; + output [62-`EFF_IFAR_WIDTH:61] fdec_frn_iu5_ix_ifar; + output [62-`EFF_IFAR_WIDTH:61] fdec_frn_iu5_ix_bta; + output [0:3] fdec_frn_iu5_ix_ilat; + output fdec_frn_iu5_ix_t1_v; + output [0:2] fdec_frn_iu5_ix_t1_t; + output [0:`GPR_POOL_ENC-1] fdec_frn_iu5_ix_t1_a; + output fdec_frn_iu5_ix_t2_v; + output [0:`GPR_POOL_ENC-1] fdec_frn_iu5_ix_t2_a; + output [0:2] fdec_frn_iu5_ix_t2_t; + output fdec_frn_iu5_ix_t3_v; + output [0:`GPR_POOL_ENC-1] fdec_frn_iu5_ix_t3_a; + output [0:2] fdec_frn_iu5_ix_t3_t; + output fdec_frn_iu5_ix_s1_v; + output [0:`GPR_POOL_ENC-1] fdec_frn_iu5_ix_s1_a; + output [0:2] fdec_frn_iu5_ix_s1_t; + output fdec_frn_iu5_ix_s2_v; + output [0:`GPR_POOL_ENC-1] fdec_frn_iu5_ix_s2_a; + output [0:2] fdec_frn_iu5_ix_s2_t; + output fdec_frn_iu5_ix_s3_v; + output [0:`GPR_POOL_ENC-1] fdec_frn_iu5_ix_s3_a; + output [0:2] fdec_frn_iu5_ix_s3_t; + output fdec_frn_iu5_ix_br_pred; + output fdec_frn_iu5_ix_bh_update; + output [0:1] fdec_frn_iu5_ix_bh0_hist; + output [0:1] fdec_frn_iu5_ix_bh1_hist; + output [0:1] fdec_frn_iu5_ix_bh2_hist; + output [0:17] fdec_frn_iu5_ix_gshare; + output [0:2] fdec_frn_iu5_ix_ls_ptr; + output fdec_frn_iu5_ix_match; + output fdec_frn_iu5_ix_btb_entry; + output [0:1] fdec_frn_iu5_ix_btb_hist; + output fdec_frn_iu5_ix_bta_val; + + input frn_fdec_iu5_stall; + + + //@@ Signal Declarations + wire [1:107] br_dep_pt; + wire [1:223] instruction_decoder_pt; + wire updatescr; + wire [0:1] updatescr_sel; + wire updatesctr; + wire updateslr; + wire updatesxer; + wire usescr; + wire usescr2; + wire [0:1] usescr_sel; + wire usesctr; + wire useslr; + wire usestar; + wire usesxer; + wire async_block; + wire core_block; + wire dec_val; + wire isload; + wire issue_fx0; + wire issue_fx1; + wire issue_lq; + wire issue_sq; + wire [0:3] latency; + wire no_pre; + wire no_ram; + wire np1_flush; + wire ordered; + wire s1_sel; + wire s1_vld; + wire s2_sel; + wire s2_vld; + wire s3_vld; + wire spec; + wire ta_sel; + wire ta_vld; + wire zero_r0; + // Scan chain connenctions + parameter iu5_vld_offset = 0; + parameter iu5_ucode_offset = iu5_vld_offset + 1; + parameter iu5_2ucode_offset = iu5_ucode_offset + 3; + parameter iu5_fuse_nop_offset = iu5_2ucode_offset + 1; + parameter iu5_error_offset = iu5_fuse_nop_offset + 1; + parameter iu5_btb_entry_offset = iu5_error_offset + 3; + parameter iu5_btb_hist_offset = iu5_btb_entry_offset + 1; + parameter iu5_bta_val_offset = iu5_btb_hist_offset + 2; + parameter iu5_fusion_offset = iu5_bta_val_offset + 1; + parameter iu5_rte_lq_offset = iu5_fusion_offset + 20; + parameter iu5_rte_sq_offset = iu5_rte_lq_offset + 1; + parameter iu5_rte_fx0_offset = iu5_rte_sq_offset + 1; + parameter iu5_rte_fx1_offset = iu5_rte_fx0_offset + 1; + parameter iu5_rte_axu0_offset = iu5_rte_fx1_offset + 1; + parameter iu5_rte_axu1_offset = iu5_rte_axu0_offset + 1; + parameter iu5_valop_offset = iu5_rte_axu1_offset + 1; + parameter iu5_ord_offset = iu5_valop_offset + 1; + parameter iu5_cord_offset = iu5_ord_offset + 1; + parameter iu5_spec_offset = iu5_cord_offset + 1; + parameter iu5_isram_offset = iu5_spec_offset + 1; + parameter iu5_type_fp_offset = iu5_isram_offset + 1; + parameter iu5_type_ap_offset = iu5_type_fp_offset + 1; + parameter iu5_type_spv_offset = iu5_type_ap_offset + 1; + parameter iu5_type_st_offset = iu5_type_spv_offset + 1; + parameter iu5_async_block_offset = iu5_type_st_offset + 1; + parameter iu5_np1_flush_offset = iu5_async_block_offset + 1; + parameter iu5_core_block_offset = iu5_np1_flush_offset + 1; + parameter iu5_isload_offset = iu5_core_block_offset + 1; + parameter iu5_isstore_offset = iu5_isload_offset + 1; + parameter iu5_instr_offset = iu5_isstore_offset + 1; + parameter iu5_ifar_offset = iu5_instr_offset + 32; + parameter iu5_bta_offset = iu5_ifar_offset + `EFF_IFAR_WIDTH; + parameter iu5_ilat_offset = iu5_bta_offset + `EFF_IFAR_WIDTH; + parameter iu5_t1_v_offset = iu5_ilat_offset + 4; + parameter iu5_t1_t_offset = iu5_t1_v_offset + 1; + parameter iu5_t1_a_offset = iu5_t1_t_offset + 3; + parameter iu5_t2_v_offset = iu5_t1_a_offset + `GPR_POOL_ENC; + parameter iu5_t2_a_offset = iu5_t2_v_offset + 1; + parameter iu5_t2_t_offset = iu5_t2_a_offset + `GPR_POOL_ENC; + parameter iu5_t3_v_offset = iu5_t2_t_offset + 3; + parameter iu5_t3_a_offset = iu5_t3_v_offset + 1; + parameter iu5_t3_t_offset = iu5_t3_a_offset + `GPR_POOL_ENC; + parameter iu5_s1_v_offset = iu5_t3_t_offset + 3; + parameter iu5_s1_a_offset = iu5_s1_v_offset + 1; + parameter iu5_s1_t_offset = iu5_s1_a_offset + `GPR_POOL_ENC; + parameter iu5_s2_v_offset = iu5_s1_t_offset + 3; + parameter iu5_s2_a_offset = iu5_s2_v_offset + 1; + parameter iu5_s2_t_offset = iu5_s2_a_offset + `GPR_POOL_ENC; + parameter iu5_s3_v_offset = iu5_s2_t_offset + 3; + parameter iu5_s3_a_offset = iu5_s3_v_offset + 1; + parameter iu5_s3_t_offset = iu5_s3_a_offset + `GPR_POOL_ENC; + parameter iu5_br_pred_offset = iu5_s3_t_offset + 3; + parameter iu5_bh_update_offset = iu5_br_pred_offset + 1; + parameter iu5_bh0_hist_offset = iu5_bh_update_offset + 1; + parameter iu5_bh1_hist_offset = iu5_bh0_hist_offset + 2; + parameter iu5_bh2_hist_offset = iu5_bh1_hist_offset + 2; + parameter iu5_gshare_offset = iu5_bh2_hist_offset + 2; + parameter iu5_ls_ptr_offset = iu5_gshare_offset + 18; + parameter iu5_match_offset = iu5_ls_ptr_offset + 3; + parameter spr_epcr_dgtmi_offset = iu5_match_offset + 1; + parameter spr_msrp_uclep_offset = spr_epcr_dgtmi_offset + 1; + parameter spr_msr_pr_offset = spr_msrp_uclep_offset + 1; + parameter spr_msr_gs_offset = spr_msr_pr_offset + 1; + parameter spr_msr_ucle_offset = spr_msr_gs_offset + 1; + parameter spr_ccr2_ucode_dis_offset = spr_msr_ucle_offset + 1; + parameter cp_flush_offset = spr_ccr2_ucode_dis_offset + 1; + parameter scan_right = cp_flush_offset + 1 - 1; + // signals for hooking up scanchains + wire [0:scan_right] siv; + wire [0:scan_right] sov; + // hard ties + wire tiup; + wire core64; + wire cp_flush_d; + wire cp_flush_q; + // instruction fields + wire iu4_instr_vld; + wire [62-`EFF_IFAR_WIDTH:61] iu4_ifar; + wire [62-`EFF_IFAR_WIDTH:61] iu4_bta; + wire [0:31] iu4_instr; + wire [0:3] iu4_instr_ucode_ext; + wire iu4_instr_br_pred; + wire iu4_instr_bh_update; + wire [0:1] iu4_instr_bh0_hist; + wire [0:1] iu4_instr_bh1_hist; + wire [0:1] iu4_instr_bh2_hist; + wire [0:17] iu4_instr_gshare; + wire [0:2] iu4_instr_ls_ptr; + wire iu4_instr_match; + wire [0:2] iu4_instr_error; + wire iu4_instr_btb_entry; + wire [0:1] iu4_instr_btb_hist; + wire iu4_instr_bta_val; + wire [0:2] iu4_instr_ucode; + wire iu4_instr_2ucode; + wire iu4_instr_isram; + wire iu4_fuse_val; + wire [0:31] iu4_fuse_cmp; + wire iu4_fuse_nop; + wire iu4_is_mtcpcr; + // Latch definitions + reg iu5_vld_d; + reg [0:2] iu5_ucode_d; + reg iu5_2ucode_d; + reg iu5_fuse_nop_d; + reg [0:2] iu5_error_d; + reg iu5_btb_entry_d; + reg [0:1] iu5_btb_hist_d; + reg iu5_bta_val_d; + reg [0:19] iu5_fusion_d; + reg iu5_rte_lq_d; + reg iu5_rte_sq_d; + reg iu5_rte_fx0_d; + reg iu5_rte_fx1_d; + reg iu5_rte_axu0_d; + reg iu5_rte_axu1_d; + reg iu5_valop_d; + reg iu5_ord_d; + reg iu5_cord_d; + reg iu5_spec_d; + reg iu5_type_fp_d; + reg iu5_type_ap_d; + reg iu5_type_spv_d; + reg iu5_type_st_d; + reg iu5_async_block_d; + reg iu5_np1_flush_d; + reg iu5_core_block_d; + reg iu5_isram_d; + reg iu5_isload_d; + reg iu5_isstore_d; + reg [0:31] iu5_instr_d; + reg [62-`EFF_IFAR_WIDTH:61] iu5_ifar_d; + reg [62-`EFF_IFAR_WIDTH:61] iu5_bta_d; + reg [0:3] iu5_ilat_d; + reg iu5_t1_v_d; + reg [0:2] iu5_t1_t_d; + reg [0:`GPR_POOL_ENC-1] iu5_t1_a_d; + reg iu5_t2_v_d; + reg [0:`GPR_POOL_ENC-1] iu5_t2_a_d; + reg [0:2] iu5_t2_t_d; + reg iu5_t3_v_d; + reg [0:`GPR_POOL_ENC-1] iu5_t3_a_d; + reg [0:2] iu5_t3_t_d; + reg iu5_s1_v_d; + reg [0:`GPR_POOL_ENC-1] iu5_s1_a_d; + reg [0:2] iu5_s1_t_d; + reg iu5_s2_v_d; + reg [0:`GPR_POOL_ENC-1] iu5_s2_a_d; + reg [0:2] iu5_s2_t_d; + reg iu5_s3_v_d; + reg [0:`GPR_POOL_ENC-1] iu5_s3_a_d; + reg [0:2] iu5_s3_t_d; + reg iu5_br_pred_d; + reg iu5_bh_update_d; + reg [0:1] iu5_bh0_hist_d; + reg [0:1] iu5_bh1_hist_d; + reg [0:1] iu5_bh2_hist_d; + reg [0:17] iu5_gshare_d; + reg [0:2] iu5_ls_ptr_d; + reg iu5_match_d; + wire iu5_vld_q; + wire [0:2] iu5_ucode_q; + wire iu5_2ucode_q; + wire iu5_fuse_nop_q; + wire [0:2] iu5_error_q; + wire iu5_btb_entry_q; + wire [0:1] iu5_btb_hist_q; + wire iu5_bta_val_q; + wire [0:19] iu5_fusion_q; + wire iu5_rte_lq_q; + wire iu5_rte_sq_q; + wire iu5_rte_fx0_q; + wire iu5_rte_fx1_q; + wire iu5_rte_axu0_q; + wire iu5_rte_axu1_q; + wire iu5_valop_q; + wire iu5_ord_q; + wire iu5_cord_q; + wire iu5_spec_q; + wire iu5_type_fp_q; + wire iu5_type_ap_q; + wire iu5_type_spv_q; + wire iu5_type_st_q; + wire iu5_async_block_q; + wire iu5_np1_flush_q; + wire iu5_core_block_q; + wire iu5_isram_q; + wire iu5_isload_q; + wire iu5_isstore_q; + wire [0:31] iu5_instr_q; + wire [62-`EFF_IFAR_WIDTH:61] iu5_ifar_q; + wire [62-`EFF_IFAR_WIDTH:61] iu5_bta_q; + wire [0:3] iu5_ilat_q; + wire iu5_t1_v_q; + wire [0:2] iu5_t1_t_q; + wire [0:`GPR_POOL_ENC-1] iu5_t1_a_q; + wire iu5_t2_v_q; + wire [0:`GPR_POOL_ENC-1] iu5_t2_a_q; + wire [0:2] iu5_t2_t_q; + wire iu5_t3_v_q; + wire [0:`GPR_POOL_ENC-1] iu5_t3_a_q; + wire [0:2] iu5_t3_t_q; + wire iu5_s1_v_q; + wire [0:`GPR_POOL_ENC-1] iu5_s1_a_q; + wire [0:2] iu5_s1_t_q; + wire iu5_s2_v_q; + wire [0:`GPR_POOL_ENC-1] iu5_s2_a_q; + wire [0:2] iu5_s2_t_q; + wire iu5_s3_v_q; + wire [0:`GPR_POOL_ENC-1] iu5_s3_a_q; + wire [0:2] iu5_s3_t_q; + wire iu5_br_pred_q; + wire iu5_bh_update_q; + wire [0:1] iu5_bh0_hist_q; + wire [0:1] iu5_bh1_hist_q; + wire [0:1] iu5_bh2_hist_q; + wire [0:17] iu5_gshare_q; + wire [0:2] iu5_ls_ptr_q; + wire iu5_match_q; + wire iu5_vld_din; + wire [0:2] iu5_ucode_din; + wire iu5_2ucode_din; + wire iu5_fuse_nop_din; + wire [0:2] iu5_error_din; + wire iu5_btb_entry_din; + wire [0:1] iu5_btb_hist_din; + wire iu5_bta_val_din; + wire [0:19] iu5_fusion_din; + wire iu5_rte_lq_din; + wire iu5_rte_sq_din; + wire iu5_rte_fx0_din; + wire iu5_rte_fx1_din; + wire iu5_rte_axu0_din; + wire iu5_rte_axu1_din; + wire iu5_valop_din; + wire iu5_ord_din; + wire iu5_cord_din; + wire iu5_spec_din; + wire iu5_type_fp_din; + wire iu5_type_ap_din; + wire iu5_type_spv_din; + wire iu5_type_st_din; + wire iu5_async_block_din; + wire iu5_np1_flush_din; + wire iu5_core_block_din; + wire iu5_isram_din; + wire iu5_isload_din; + wire iu5_isstore_din; + wire [0:31] iu5_instr_din; + wire [62-`EFF_IFAR_WIDTH:61] iu5_ifar_din; + wire [62-`EFF_IFAR_WIDTH:61] iu5_bta_din; + wire [0:3] iu5_ilat_din; + wire iu5_t1_v_din; + wire [0:2] iu5_t1_t_din; + wire [0:`GPR_POOL_ENC-1] iu5_t1_a_din; + wire iu5_t2_v_din; + wire [0:`GPR_POOL_ENC-1] iu5_t2_a_din; + wire [0:2] iu5_t2_t_din; + wire iu5_t3_v_din; + wire [0:`GPR_POOL_ENC-1] iu5_t3_a_din; + wire [0:2] iu5_t3_t_din; + wire iu5_s1_v_din; + wire [0:`GPR_POOL_ENC-1] iu5_s1_a_din; + wire [0:2] iu5_s1_t_din; + wire iu5_s2_v_din; + wire [0:`GPR_POOL_ENC-1] iu5_s2_a_din; + wire [0:2] iu5_s2_t_din; + wire iu5_s3_v_din; + wire [0:`GPR_POOL_ENC-1] iu5_s3_a_din; + wire [0:2] iu5_s3_t_din; + wire iu5_br_pred_din; + wire iu5_bh_update_din; + wire [0:1] iu5_bh0_hist_din; + wire [0:1] iu5_bh1_hist_din; + wire [0:1] iu5_bh2_hist_din; + wire [0:17] iu5_gshare_din; + wire [0:2] iu5_ls_ptr_din; + wire iu5_match_din; + wire iu5_vld_woaxu; + wire [0:2] iu5_ucode_woaxu; + wire iu5_2ucode_woaxu; + wire iu5_fuse_nop_woaxu; + wire [0:2] iu5_error_woaxu; + wire iu5_btb_entry_woaxu; + wire [0:1] iu5_btb_hist_woaxu; + wire iu5_bta_val_woaxu; + wire [0:19] iu5_fusion_woaxu; + wire iu5_rte_lq_woaxu; + wire iu5_rte_sq_woaxu; + wire iu5_rte_fx0_woaxu; + wire iu5_rte_fx1_woaxu; + wire iu5_rte_axu0_woaxu; + wire iu5_rte_axu1_woaxu; + wire iu5_valop_woaxu; + wire iu5_ord_woaxu; + wire iu5_cord_woaxu; + wire iu5_spec_woaxu; + wire iu5_type_fp_woaxu; + wire iu5_type_ap_woaxu; + wire iu5_type_spv_woaxu; + wire iu5_type_st_woaxu; + wire iu5_async_block_woaxu; + wire iu5_np1_flush_woaxu; + wire iu5_core_block_woaxu; + wire iu5_isram_woaxu; + wire iu5_isload_woaxu; + wire iu5_isstore_woaxu; + wire [0:31] iu5_instr_woaxu; + wire [62-`EFF_IFAR_WIDTH:61] iu5_ifar_woaxu; + wire [62-`EFF_IFAR_WIDTH:61] iu5_bta_woaxu; + wire [0:3] iu5_ilat_woaxu; + wire iu5_t1_v_woaxu; + wire [0:2] iu5_t1_t_woaxu; + wire [0:`GPR_POOL_ENC-1] iu5_t1_a_woaxu; + wire iu5_t2_v_woaxu; + wire [0:`GPR_POOL_ENC-1] iu5_t2_a_woaxu; + wire [0:2] iu5_t2_t_woaxu; + wire iu5_t3_v_woaxu; + wire [0:`GPR_POOL_ENC-1] iu5_t3_a_woaxu; + wire [0:2] iu5_t3_t_woaxu; + wire iu5_s1_v_woaxu; + wire [0:`GPR_POOL_ENC-1] iu5_s1_a_woaxu; + wire [0:2] iu5_s1_t_woaxu; + wire iu5_s2_v_woaxu; + wire [0:`GPR_POOL_ENC-1] iu5_s2_a_woaxu; + wire [0:2] iu5_s2_t_woaxu; + wire iu5_s3_v_woaxu; + wire [0:`GPR_POOL_ENC-1] iu5_s3_a_woaxu; + wire [0:2] iu5_s3_t_woaxu; + wire iu5_br_pred_woaxu; + wire iu5_bh_update_woaxu; + wire [0:1] iu5_bh0_hist_woaxu; + wire [0:1] iu5_bh1_hist_woaxu; + wire [0:1] iu5_bh2_hist_woaxu; + wire [0:17] iu5_gshare_woaxu; + wire [0:2] iu5_ls_ptr_woaxu; + wire iu5_match_woaxu; + wire [0:5] iu5_t1_a_woaxu6; + wire [0:5] iu5_t2_a_woaxu6; + wire [0:5] iu5_t3_a_woaxu6; + wire [0:5] iu5_s1_a_woaxu6; + wire [0:5] iu5_s2_a_woaxu6; + wire [0:5] iu5_s3_a_woaxu6; + wire iu5_valid_act; + wire iu5_instr_act; + wire iu4_is_mtiar; + wire spr_epcr_dgtmi_q; + wire spr_msrp_uclep_q; + wire spr_msr_pr_q; + wire spr_msr_gs_q; + wire spr_msr_ucle_q; + wire spr_ccr2_ucode_dis_q; + // Pervasive + wire pc_iu_func_sl_thold_1; + wire pc_iu_func_sl_thold_0; + wire pc_iu_func_sl_thold_0_b; + wire pc_iu_sg_1; + wire pc_iu_sg_0; + wire force_t; + wire axu; + wire naxu; + wire multi_cr; + wire or_ppr32_val; + wire or_ppr32; + wire mtspr_trace_val; + wire erativax_val; + wire tlbwe_with_binv; + wire mtspr_nop; + wire mfspr_nop; + wire spr_nop; + wire mtspr_tar; + wire mfspr_tar; + wire mtspr_tenc; + wire mtspr_xucr0; + wire mtspr_ccr0; + wire mfspr_mmucr1; + //temp + wire [0:5] SPR_addr; + //@@ START OF EXECUTABLE CODE FOR IUQ_IDEC + + assign tiup = 1'b1; + assign cp_flush_d = cp_iu_iu4_flush | br_iu_redirect | uc_ib_iu3_flush_all; + assign iu4_instr_vld = ib_id_iu4_valid; + assign iu4_ifar = ib_id_iu4_ifar; + assign iu4_bta = ib_id_iu4_bta; + assign iu4_instr = ib_id_iu4_instr[0:31]; + assign iu4_instr_br_pred = ib_id_iu4_instr[32]; + assign iu4_instr_bh_update = ib_id_iu4_instr[33]; + assign iu4_instr_bh0_hist = ib_id_iu4_instr[34:35]; + assign iu4_instr_bh1_hist = ib_id_iu4_instr[36:37]; + assign iu4_instr_bh2_hist = ib_id_iu4_instr[38:39]; + assign iu4_instr_gshare = {ib_id_iu4_instr[40:49], ib_id_iu4_instr[62:69]}; + assign iu4_instr_ls_ptr = ib_id_iu4_instr[50:52]; + assign iu4_instr_match = (spr_dec_mask[0:31] & iu4_instr[0:31]) == (spr_dec_mask[0:31] & spr_dec_match[0:31]); + assign iu4_instr_error = ib_id_iu4_instr[53:55]; + // bit 56 = to ucode, and is not used by decode any more + // bit 57 = fuse en, and is not used by decode any more + assign iu4_fuse_nop = ib_id_iu4_instr[57]; + assign iu4_instr_btb_entry = ib_id_iu4_instr[58]; + assign iu4_instr_btb_hist = ib_id_iu4_instr[59:60]; + assign iu4_instr_bta_val = ib_id_iu4_instr[61]; + assign iu4_instr_ucode_ext = ib_id_iu4_ucode_ext; + assign iu4_instr_ucode = ib_id_iu4_ucode; + assign iu4_instr_2ucode = ib_id_iu4_instr[59]; + assign iu4_instr_isram = ib_id_iu4_isram; + assign iu4_is_mtiar = ((iu4_instr[0:5] == 6'b011111) & (iu4_instr[11:20] == 10'b1001011011) & (iu4_instr[21:30] == 10'b0111010011)) ? 1'b1 : + 1'b0; + assign iu4_fuse_val = ib_id_iu4_fuse_val; + assign iu4_fuse_cmp = ib_id_iu4_fuse_data; + + assign iu4_is_mtcpcr = (~iu4_fuse_val & (iu4_instr[0:5] == 6'b011111) & (iu4_instr[21:30] == 10'b0111010011)) & + ((iu4_instr[11:20] == 10'b1000011001) | (iu4_instr[11:20] == 10'b1000111001) | (iu4_instr[11:20] == 10'b1001011001) | + (iu4_instr[11:20] == 10'b1010011001) | (iu4_instr[11:20] == 10'b1010111001) | (iu4_instr[11:20] == 10'b1011011001)); + + //64-bit core + generate + if (`GPR_WIDTH == 64) + begin : c64 + assign core64 = 1'b1; + end + endgenerate + //32-bit core + generate + if (`GPR_WIDTH == 32) + begin : c32 + assign core64 = 1'b0; + end + endgenerate + assign multi_cr = (~(iu4_instr[12:19] == 8'b00000000 | iu4_instr[12:19] == 8'b10000000 | iu4_instr[12:19] == 8'b01000000 | iu4_instr[12:19] == 8'b00100000 | iu4_instr[12:19] == 8'b00010000 | iu4_instr[12:19] == 8'b00001000 | iu4_instr[12:19] == 8'b00000100 | iu4_instr[12:19] == 8'b00000010 | iu4_instr[12:19] == 8'b00000001)); + assign or_ppr32 = (iu4_instr[0:5] == 6'b011111 & iu4_instr[21:31] == 11'b01101111000) & (iu4_instr[6:10] == iu4_instr[11:15] & iu4_instr[11:15] == iu4_instr[16:20]); + assign or_ppr32_val = (iu4_instr[16:20] == 5'b11111 | iu4_instr[16:20] == 5'b00001 | iu4_instr[16:20] == 5'b00110 | iu4_instr[16:20] == 5'b00010 | iu4_instr[16:20] == 5'b00101 | iu4_instr[16:20] == 5'b00011 | iu4_instr[16:20] == 5'b00111) & or_ppr32 & (~(|(iu4_instr_ucode))); + assign mtspr_trace_val = (iu4_instr[0:5] == 6'b011111) & (iu4_instr[11:30] == 20'b01110111110111010011); + assign erativax_val = (iu4_instr[0:5] == 6'b011111 & iu4_instr[21:30] == 10'b1100110011); + assign tlbwe_with_binv = (iu4_instr[0:5] == 6'b011111 & iu4_instr[21:30] == 10'b1111010010) & mm_iu_tlbwe_binv; + assign mtspr_nop = iu4_instr[0:5] == 6'b011111 & iu4_instr[11:13] == 3'b010 & iu4_instr[16:30] == 15'b110010111010011; + assign mfspr_nop = iu4_instr[0:5] == 6'b011111 & iu4_instr[11:13] == 3'b010 & iu4_instr[16:30] == 15'b110010101010011; + assign spr_nop = mtspr_nop | mfspr_nop; + assign mtspr_tar = iu4_instr[0:5] == 6'b011111 & iu4_instr[11:20] == 10'b0111111001 & iu4_instr[21:30] == 10'b0111010011; + assign mfspr_tar = iu4_instr[0:5] == 6'b011111 & iu4_instr[11:20] == 10'b0111111001 & iu4_instr[21:30] == 10'b0101010011; + assign mtspr_tenc = iu4_instr[0:5] == 6'b011111 & iu4_instr[11:20] == 10'b1011101101 & iu4_instr[21:30] == 10'b0111010011; + assign mtspr_xucr0 = iu4_instr[0:5] == 6'b011111 & iu4_instr[11:20] == 10'b1011011111 & iu4_instr[21:30] == 10'b0111010011; + assign mtspr_ccr0 = iu4_instr[0:5] == 6'b011111 & iu4_instr[11:20] == 10'b1000011111 & iu4_instr[21:30] == 10'b0111010011; + assign mfspr_mmucr1 = iu4_instr[0:5] == 6'b011111 & iu4_instr[11:20] == 10'b1110111111 & iu4_instr[21:30] == 10'b0101010011; + + + //------------------------------------------------------------------------------------------------------- + // branch dependency. branches bite. branches can update LR and CTR, and can use LR, CR, and CTR. + //------------------------------------------------------------------------------------------------------- + //------------------------------------------------------------------------------------------------------- + // Main Instruction Decoder. Select and Type definitions + //------------------------------------------------------------------------------------------------------- + +//table_start +//?TABLE br_dep LISTING(final) OPTIMIZE PARMS(ON-SET,DC-SET); +//*INPUTS*===========================================================*OUTPUTS*=============================================* +//| | | +//| | updateslr | +//| | | updatescr | +//| | | | updatesctr | +//| | | | | updatesxer | +//| core64 | | | | | | +//| | iu4_fuse_val | | | | | | +//| | iu4_instr | iu4_fuse_cmp | | | | | useslr | +//| | | iu4_instr | | | | | | | | usescr | +//| | | | iu4_instr | | | | | | | | | usesctr | +//| | | | | iu4_instr iu4_instr | | iu4_fuse_cmp | | | | | | | | usesxer usescr2 | +//| | | | | | | | | | | | | | | | | | | usestar | usescr_sel | +//| | | | | | | | | | | | | | | | | | | | | | updatescr_sel| +//| | | | | 1111111112 22222222233 | | 22222222233 | | | | | | | | | | | | | | +//| | 012345 6 8 1234567890 12345678901 | 012345 12345678901 | | | | | | | | | | | 01 01 | +//*TYPE*=============================================================+=====================================================+ +//| P PPPPPP P P PPPPPPPPPP PPPPPPPPPPP P PPPPPP PPPPPPPPPPP | S S S S S S S S S S SS SS | +//*TERMS*============================================================+=====================================================+ +//| . 010000 . 0 .......... ..........0 1 00101. ........... | 0 1 1 0 0 0 1 1 0 0 00 01 | cmpi/cmpli -> bc/bca +//| . 010000 . 0 .......... ..........1 1 00101. ........... | 1 1 1 0 0 0 1 1 0 0 00 01 | cmpi/cmpli -> bcl/bcla +//| . 010000 . 1 .......... ..........0 1 00101. ........... | 0 1 0 0 0 0 0 1 0 0 00 01 | cmpi/cmpli -> bc/bca +//| . 010000 . 1 .......... ..........1 1 00101. ........... | 1 1 0 0 0 0 0 1 0 0 00 01 | cmpi/cmpli -> bcl/bcla +//| . 010011 . 1 .......... 00000100000 1 00101. ........... | 0 1 0 0 1 0 0 1 0 0 00 01 | cmpi/cmpli -> bclr +//| . 010011 . 1 .......... 00000100001 1 00101. ........... | 1 1 0 0 1 0 0 1 0 0 00 01 | cmpi/cmpli -> bclrl +//| . 010011 . 1 .......... 10001100000 1 00101. ........... | 0 1 0 0 0 0 0 1 1 0 00 01 | cmpi/cmpli -> bctar +//| . 010011 . 1 .......... 10001100001 1 00101. ........... | 1 1 0 0 0 0 0 1 1 0 00 01 | cmpi/cmpli -> bctarl +//| . 010011 . 1 .......... 10000100000 1 00101. ........... | 0 1 0 0 0 0 1 1 0 0 00 01 | cmpi/cmpli -> bcctr +//| . 010011 . 1 .......... 10000100001 1 00101. ........... | 1 1 0 0 0 0 1 1 0 0 00 01 | cmpi/cmpli -> bcctrl +//| . 010000 . 1 .......... ..........0 1 011111 0000.00000. | 0 1 0 0 0 0 0 1 0 0 00 01 | cmp/cmpl -> bc/bca +//| . 010000 . 1 .......... ..........1 1 011111 0000.00000. | 1 1 0 0 0 0 0 1 0 0 00 01 | cmp/cmpl -> bcl/bcla +//| . 011111 . . .......... 01000010101 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | add. +//| . 011111 . . .......... 00000010100 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | addc +//| . 011111 . . .......... 00000010101 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | addc. +//| . 011111 . . .......... 10000010100 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | addco +//| . 011111 . . .......... 10000010101 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | addco. +//| . 011111 . . .......... 00100010100 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | adde +//| . 011111 . . .......... 00100010101 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | adde. +//| . 011111 . . .......... 10100010100 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | addeo +//| . 011111 . . .......... 10100010101 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | addeo. +//| . 001100 . . .......... ........... 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | addic +//| . 001101 . . .......... ........... 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | addic. +//| . 011111 . . .......... 00111010100 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | addme +//| . 011111 . . .......... 00111010101 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | addme. +//| . 011111 . . .......... 10111010100 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | addmeo +//| . 011111 . . .......... 10111010101 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | addmeo. +//| . 011111 . . .......... 11000010100 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | addo +//| . 011111 . . .......... 11000010101 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | addo. +//| . 011111 . . .......... 00110010100 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | addze +//| . 011111 . . .......... 00110010101 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | addze. +//| . 011111 . . .......... 10110010100 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | addzeo +//| . 011111 . . .......... 10110010101 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | addzeo. +//| . 011111 . . .......... 00000111001 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | and. +//| . 011111 . . .......... 00001111001 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | andc. +//| . 011100 . . .......... ........... 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | andi. +//| . 011101 . . .......... ........... 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | andis. +//| . 010000 0 0 .......... .........00 0 ...... ........... | 0 0 1 0 0 1 1 0 0 0 01 00 | bc +//| . 010000 0 1 .......... .........00 0 ...... ........... | 0 0 0 0 0 1 0 0 0 0 01 00 | bc +//| . 010000 0 0 .......... .........10 0 ...... ........... | 0 0 1 0 0 1 1 0 0 0 01 00 | bca +//| . 010000 0 1 .......... .........10 0 ...... ........... | 0 0 0 0 0 1 0 0 0 0 01 00 | bca +//| . 010011 0 1 .......... 10000100000 0 ...... ........... | 0 0 0 0 0 1 1 0 0 0 01 00 | bcctr +//| . 010011 0 1 .......... 10000100001 0 ...... ........... | 1 0 0 0 0 1 1 0 0 0 01 00 | bcctrl +//| . 010000 0 0 .......... .........01 0 ...... ........... | 1 0 1 0 0 1 1 0 0 0 01 00 | bcl +//| . 010000 0 1 .......... .........01 0 ...... ........... | 1 0 0 0 0 1 0 0 0 0 01 00 | bcl +//| . 010000 0 0 .......... .........11 0 ...... ........... | 1 0 1 0 0 1 1 0 0 0 01 00 | bcla +//| . 010000 0 1 .......... .........11 0 ...... ........... | 1 0 0 0 0 1 0 0 0 0 01 00 | bcla +//| . 010011 0 0 .......... 00000100000 0 ...... ........... | 0 0 1 0 1 1 1 0 0 0 01 00 | bclr +//| . 010011 0 1 .......... 00000100000 0 ...... ........... | 0 0 0 0 1 1 0 0 0 0 01 00 | bclr +//| . 010011 0 0 .......... 00000100001 0 ...... ........... | 1 0 1 0 1 1 1 0 0 0 01 00 | bclrl +//| . 010011 0 1 .......... 00000100001 0 ...... ........... | 1 0 0 0 1 1 0 0 0 0 01 00 | bclrl +//| . 010011 0 0 .......... 10001100000 0 ...... ........... | 0 0 1 0 0 1 1 0 1 0 01 00 | bctar +//| . 010011 0 1 .......... 10001100000 0 ...... ........... | 0 0 0 0 0 1 0 0 1 0 01 00 | bctar +//| . 010011 0 0 .......... 10001100001 0 ...... ........... | 1 0 1 0 0 1 1 0 1 0 01 00 | bctarl +//| . 010011 0 1 .......... 10001100001 0 ...... ........... | 1 0 0 0 0 1 0 0 1 0 01 00 | bctarl +//| . 010000 1 0 .......... .........00 0 ...... ........... | 0 0 1 0 0 0 1 0 0 0 01 00 | bc +//| . 010000 1 1 .......... .........00 0 ...... ........... | 0 0 0 0 0 0 0 0 0 0 01 00 | bc +//| . 010000 1 0 .......... .........10 0 ...... ........... | 0 0 1 0 0 0 1 0 0 0 01 00 | bca +//| . 010000 1 1 .......... .........10 0 ...... ........... | 0 0 0 0 0 0 0 0 0 0 01 00 | bca +//| . 010011 1 1 .......... 10000100000 0 ...... ........... | 0 0 0 0 0 0 1 0 0 0 01 00 | bcctr +//| . 010011 1 1 .......... 10000100001 0 ...... ........... | 1 0 0 0 0 0 1 0 0 0 01 00 | bcctrl +//| . 010000 1 0 .......... .........01 0 ...... ........... | 1 0 1 0 0 0 1 0 0 0 01 00 | bcl +//| . 010000 1 1 .......... .........01 0 ...... ........... | 1 0 0 0 0 0 0 0 0 0 01 00 | bcl +//| . 010000 1 0 .......... .........11 0 ...... ........... | 1 0 1 0 0 0 1 0 0 0 01 00 | bcla +//| . 010000 1 1 .......... .........11 0 ...... ........... | 1 0 0 0 0 0 0 0 0 0 01 00 | bcla +//| . 010011 1 0 .......... 00000100000 0 ...... ........... | 0 0 1 0 1 0 1 0 0 0 01 00 | bclr +//| . 010011 1 1 .......... 00000100000 0 ...... ........... | 0 0 0 0 1 0 0 0 0 0 01 00 | bclr +//| . 010011 1 0 .......... 00000100001 0 ...... ........... | 1 0 1 0 1 0 1 0 0 0 01 00 | bclrl +//| . 010011 1 1 .......... 00000100001 0 ...... ........... | 1 0 0 0 1 0 0 0 0 0 01 00 | bclrl +//| . 010011 1 0 .......... 10001100000 0 ...... ........... | 0 0 1 0 0 0 1 0 1 0 01 00 | bctar +//| . 010011 1 1 .......... 10001100000 0 ...... ........... | 0 0 0 0 0 0 0 0 1 0 01 00 | bctar +//| . 010011 1 0 .......... 10001100001 0 ...... ........... | 1 0 1 0 0 0 1 0 1 0 01 00 | bctarl +//| . 010011 1 1 .......... 10001100001 0 ...... ........... | 1 0 0 0 0 0 0 0 1 0 01 00 | bctarl +//| . 010010 . . .......... .........01 0 ...... ........... | 1 0 0 0 0 0 0 0 0 0 00 00 | bl +//| . 010010 . . .......... .........11 0 ...... ........... | 1 0 0 0 0 0 0 0 0 0 00 00 | bla +//| . 011111 . . .......... 0000000000. 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 10 | cmp +//| . 001011 . . .......... ........... 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 10 | cmpi +//| . 011111 . . .......... 0000100000. 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 10 | cmpl +//| . 001010 . . .......... ........... 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 10 | cmpli +//| 1 011111 . . .......... 00001110101 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | cntlzd. +//| . 011111 . . .......... 00000110101 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | cntlzw. +//| . 010011 . . .......... 0100000001. 0 ...... ........... | 0 1 0 0 0 1 0 0 0 1 01 10 | crand +//| . 010011 . . .......... 0010000001. 0 ...... ........... | 0 1 0 0 0 1 0 0 0 1 01 10 | crandc +//| . 010011 . . .......... 0100100001. 0 ...... ........... | 0 1 0 0 0 1 0 0 0 1 01 10 | creqv +//| . 010011 . . .......... 0011100001. 0 ...... ........... | 0 1 0 0 0 1 0 0 0 1 01 10 | crnand +//| . 010011 . . .......... 0000100001. 0 ...... ........... | 0 1 0 0 0 1 0 0 0 1 01 10 | crnor +//| . 010011 . . .......... 0111000001. 0 ...... ........... | 0 1 0 0 0 1 0 0 0 1 01 10 | cror +//| . 010011 . . .......... 0110100001. 0 ...... ........... | 0 1 0 0 0 1 0 0 0 1 01 10 | crorc +//| . 010011 . . .......... 0011000001. 0 ...... ........... | 0 1 0 0 0 1 0 0 0 1 01 10 | crxor +//| 1 011111 . . .......... 01111010011 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | divd. +//| 1 011111 . . .......... 01101010011 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | divde. +//| 1 011111 . . .......... 11101010010 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | divdeo +//| 1 011111 . . .......... 11101010011 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | divdeo. +//| 1 011111 . . .......... 01100010011 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | divdeu. +//| 1 011111 . . .......... 11100010010 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | divdeuo +//| 1 011111 . . .......... 11100010011 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | divdeuo. +//| 1 011111 . . .......... 11111010010 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | divdo +//| 1 011111 . . .......... 11111010011 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | divdo. +//| 1 011111 . . .......... 01110010011 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | divdu. +//| 1 011111 . . .......... 11110010010 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | divduo +//| 1 011111 . . .......... 11110010011 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | divduo. +//| . 011111 . . .......... 01111010111 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | divw. +//| . 011111 . . .......... 01101010111 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | divwe. +//| . 011111 . . .......... 11101010110 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | divweo +//| . 011111 . . .......... 11101010111 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | divweo. +//| . 011111 . . .......... 01100010111 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | divweu. +//| . 011111 . . .......... 11100010110 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | divweuo +//| . 011111 . . .......... 11100010111 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | divweuo. +//| . 011111 . . .......... 11111010110 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | divwo +//| . 011111 . . .......... 11111010111 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | divwo. +//| . 011111 . . .......... 01110010111 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | divwu. +//| . 011111 . . .......... 11110010110 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | divwuo +//| . 011111 . . .......... 11110010111 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | divwuo. +//| . 011111 . . .......... 00010011100 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | dlmzb +//| . 011111 . . .......... 00010011101 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | dlmzb. +//| . 011111 . . .......... 01000111001 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | eqv. +//| . 011111 . . .......... 00100100111 0 ...... ........... | 0 1 0 0 0 0 0 0 0 0 00 00 | eratsx. +//| . 011111 . . .......... 11101110101 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | extsb. +//| . 011111 . . .......... 11100110101 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | extsh. +//| 1 011111 . . .......... 11110110101 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | extsw. +//| . 011111 . . .......... 11101101100 0 ...... ........... | 0 0 0 0 0 0 0 0 0 0 00 00 | icswepx +//| . 011111 . . .......... 11101101101 0 ...... ........... | 0 1 0 0 0 0 0 0 0 0 00 00 | icswepx. +//| . 011111 . . .......... 01100101100 0 ...... ........... | 0 0 0 0 0 0 0 0 0 0 00 00 | icswx +//| . 011111 . . .......... 01100101101 0 ...... ........... | 0 1 0 0 0 0 0 0 0 0 00 00 | icswx. +//| . 011111 . . .......... .....01111. 0 ...... ........... | 0 0 0 0 0 1 0 0 0 0 10 00 | isel +//| . 011111 . . .......... 00110101001 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | ldawx. +//| . 011111 . . .......... 1000010101. 0 ...... ........... | 0 0 0 0 0 0 0 1 0 0 00 00 | lswx +//| . 010011 . . .......... 0000000000. 0 ...... ........... | 0 1 0 0 0 1 0 0 0 0 01 10 | mcrf +//| . 011111 . . .......... 1000000000. 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 10 | mcrxr +//| . 011111 . . 0......... 0000010011. 0 ...... ........... | 0 0 0 0 0 1 0 0 0 0 00 00 | mfcr +//| . 011111 . . .......... 00001000111 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | mfdp. +//| . 011111 . . .......... 00000000111 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | mfdpx. +//| . 011111 . . .......... 0001010011. 0 ...... ........... | 0 0 0 0 0 0 0 0 0 0 00 00 | mfmsr +//| . 011111 . . 1......... 0000010011. 0 ...... ........... | 0 0 0 0 0 1 0 0 0 0 11 00 | mfocrf Script needs update +//| . 011111 . . 0100000000 0101010011. 0 ...... ........... | 0 0 0 0 1 0 0 0 0 0 00 00 | mfspr (lr ) +//| . 011111 . . 0100100000 0101010011. 0 ...... ........... | 0 0 0 0 0 0 1 0 0 0 00 00 | mfspr (ctr) +//| . 011111 . . 0000100000 0101010011. 0 ...... ........... | 0 0 0 0 0 0 0 1 0 0 00 00 | mfspr (xer) +//| . 011111 . . P.PP.PPPPP 0101010011. 0 ...... ........... | 0 0 0 0 0 0 0 0 0 0 00 00 | mfspr (spr) Not sure why script is putting next line in +//| . 011111 . . .......... 0101110011. 0 ...... ........... | 0 0 0 0 0 0 0 0 0 0 00 00 | mftb +//| . 011111 . . 0......... 0010010000. 0 ...... ........... | 0 1 0 0 0 0 0 0 0 0 00 00 | mtcrf +//| . 011111 . . .......... 00011000111 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | mtdp. +//| . 011111 . . .......... 00010000111 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | mtdpx. +//| . 011111 . . .......... 0010010010. 0 ...... ........... | 0 0 0 0 0 0 0 0 0 0 00 00 | mtmsr +//| . 011111 . . 1PPPPPPPP. 0010010000. 0 ...... ........... | 0 1 0 0 0 0 0 0 0 0 00 11 | mtocrf +//| . 011111 . . 100000000. 0010010000. 0 ...... ........... | 0 0 0 0 0 0 0 0 0 0 00 00 | mtocrf +//| . 011111 . . 0100000000 0111010011. 0 ...... ........... | 1 0 0 0 0 0 0 0 0 0 00 00 | mtspr (lr ) +//| . 011111 . . 0100100000 0111010011. 0 ...... ........... | 0 0 1 0 0 0 0 0 0 0 00 00 | mtspr (ctr) +//| . 011111 . . 0000100000 0111010011. 0 ...... ........... | 0 0 0 1 0 0 0 0 0 0 00 00 | mtspr (xer) +//| . 011111 . . P.PP.PPPPP 0111010011. 0 ...... ........... | 0 0 0 0 0 0 0 0 0 0 00 00 | mtspr (spr) Not sure why script is putting next line in +//| 1 011111 . . .......... .0010010011 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | mulhd. +//| 1 011111 . . .......... .0000010011 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | mulhdu. +//| . 011111 . . .......... .0010010111 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | mulhw. +//| . 011111 . . .......... .0000010111 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | mulhwu. +//| 1 011111 . . .......... 00111010011 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | mulld. +//| 1 011111 . . .......... 10111010010 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | mulldo +//| 1 011111 . . .......... 10111010011 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | mulldo. +//| . 011111 . . .......... 00111010111 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | mullw. +//| . 011111 . . .......... 10111010110 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | mullwo +//| . 011111 . . .......... 10111010111 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | mullwo. +//| . 011111 . . .......... 01110111001 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | nand. +//| . 011111 . . .......... 00011010001 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | neg. +//| . 011111 . . .......... 10011010000 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | nego +//| . 011111 . . .......... 10011010001 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | nego. +//| . 011111 . . .......... 00011111001 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | nor. +//| . 011111 . . .......... 01101111001 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | or. +//| . 011111 . . .......... 01100111001 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | orc. +//| . 010011 . . .......... 0000110011. 0 ...... ........... | 0 0 0 0 0 0 0 0 0 0 00 00 | rfci +//| . 010011 . . .......... 0001100110. 0 ...... ........... | 0 0 0 0 0 0 0 0 0 0 00 00 | rfgi +//| . 010011 . . .......... 0000110010. 0 ...... ........... | 0 0 0 0 0 0 0 0 0 0 00 00 | rfi +//| . 010011 . . .......... 0000100110. 0 ...... ........... | 0 0 0 0 0 0 0 0 0 0 00 00 | rfmci +//| 1 011110 . . .......... ......10001 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | rldcl. +//| 1 011110 . . .......... ......10011 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | rldcr. +//| 1 011110 . . .......... ......010.1 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | rldic. +//| 1 011110 . . .......... ......000.1 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | rldicl. +//| 1 011110 . . .......... ......001.1 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | rldicr. +//| 1 011110 . . .......... ......011.1 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | rldimi. +//| . 010100 . . .......... ..........1 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | rlwimi. +//| . 010101 . . .......... ..........1 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | rlwinm. +//| . 010111 . . .......... ..........1 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | rlwnm. +//| . 010001 . . .......... .........1. 0 ...... ........... | 0 0 0 0 0 0 0 0 0 0 00 00 | sc +//| 1 011111 . . .......... 00000110111 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | sld. +//| . 011111 . . .......... 00000110001 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | slw. +//| 1 011111 . . .......... 11000110100 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | srad +//| 1 011111 . . .......... 11000110101 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | srad. +//| 1 011111 . . .......... 110011101.0 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | sradi +//| 1 011111 . . .......... 110011101.1 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | sradi. +//| . 011111 . . .......... 11000110000 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | sraw +//| . 011111 . . .......... 11000110001 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | sraw. +//| . 011111 . . .......... 11001110000 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | srawi +//| . 011111 . . .......... 11001110001 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | srawi. +//| 1 011111 . . .......... 10000110111 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | srd. +//| . 011111 . . .......... 10000110001 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | srw. +//| . 011111 . . .......... 10101101101 0 ...... ........... | 0 1 0 0 0 0 0 0 0 0 00 00 | stbcx. had to remove xer user to fix string ops that have 4 sources +//| 1 011111 . . .......... 00110101101 0 ...... ........... | 0 1 0 0 0 0 0 0 0 0 00 00 | stdcx. had to remove xer user to fix string ops that have 4 sources +//| . 011111 . . .......... 10110101101 0 ...... ........... | 0 1 0 0 0 0 0 0 0 0 00 00 | sthcx. had to remove xer user to fix string ops that have 4 sources +//| . 011111 . . .......... 1010010101. 0 ...... ........... | 0 0 0 0 0 0 0 1 0 0 00 00 | stswx +//| . 011111 . . .......... 00100101101 0 ...... ........... | 0 1 0 0 0 0 0 0 0 0 00 00 | stwcx. had to remove xer user to fix string ops that have 4 sources +//| . 011111 . . .......... 00001010001 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | subf. +//| . 011111 . . .......... 00000010000 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | subfc +//| . 011111 . . .......... 00000010001 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | subfc. +//| . 011111 . . .......... 10000010000 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | subfco +//| . 011111 . . .......... 10000010001 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | subfco. +//| . 011111 . . .......... 00100010000 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | subfe +//| . 011111 . . .......... 00100010001 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | subfe. +//| . 011111 . . .......... 10100010000 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | subfeo +//| . 011111 . . .......... 10100010001 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | subfeo. +//| . 001000 . . .......... ........... 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | subfic +//| . 011111 . . .......... 00111010000 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | subfme +//| . 011111 . . .......... 00111010001 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | subfme. +//| . 011111 . . .......... 10111010000 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | subfmeo +//| . 011111 . . .......... 10111010001 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | subfmeo. +//| . 011111 . . .......... 10001010000 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | subfo +//| . 011111 . . .......... 10001010001 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | subfo. +//| . 011111 . . .......... 00110010000 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | subfze +//| . 011111 . . .......... 00110010001 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | subfze. +//| . 011111 . . .......... 10110010000 0 ...... ........... | 0 0 0 1 0 0 0 1 0 0 00 00 | subfzeo +//| . 011111 . . .......... 10110010001 0 ...... ........... | 0 1 0 1 0 0 0 1 0 0 00 00 | subfzeo. +//| . 011111 . . .......... 11010100101 0 ...... ........... | 0 1 0 0 0 0 0 0 0 0 00 00 | tlbsrx. +//| . 011111 . . .......... 11100100101 0 ...... ........... | 0 1 0 0 0 0 0 0 0 0 00 00 | tlbsx. +//| . 011111 . . .......... 1110000110. 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 10 | wchkall +//| . 011111 . . .......... 1110100110. 0 ...... ........... | 0 0 0 0 0 0 0 0 0 0 00 00 | wclr +//| . 011111 . . .......... 0010000011. 0 ...... ........... | 0 0 0 0 0 0 0 0 0 0 00 00 | wrtee +//| . 011111 . . .......... 0010100011. 0 ...... ........... | 0 0 0 0 0 0 0 0 0 0 00 00 | wrteei +//| . 011111 . . .......... 01001111001 0 ...... ........... | 0 1 0 0 0 0 0 1 0 0 00 00 | xor. +//*END*==============================================================+=====================================================+ +//?TABLE END br_dep; +// +//?TABLE instruction_decoder LISTING(final) OPTIMIZE PARMS(ON-SET,DC-SET); +//*INPUTS*========================================================*OUTPUTS*========================================================================================* +//| | | +//| core64 | | +//| | iu4_fuse_val | | +//| | iu4_instr | iu4_fuse_cmp | ta_vld s1_vld s2_vld s3_vld | +//| | | iu4_instr | | | | | | | | +//| | | | iu4_instr | | | | ta_sel | s1_sel | s2_sel | | +//| | | | | iu4_instr | | iu4_fuse_cmp | | | | | | | | | +//| | | | | | | | | | | | | | | | | | +//| | | | | | | | | | | | | | | | | | +//| | | | | | | | | | | | | | | | | ordered | +//| | | | | | | | | | | | | | | | | | spec | +//| | | | | | | | | | | | | | | | | | | isload | +//| | | | | | | | | | | | | | | | | | | | zero_r0 | +//| | | | | | | | | | | | | | | | | | | | | dec_val | +//| | | | | | | | | | | | | | | | | issue_lq | | | | | | +//| | | | | | | | | | | | | | | | | | issue_sq | | | | | async_block | +//| | | | | | | | | | | | | | | | | | | issue_fx0 | | | | | | np1_flush | +//| | | | | | | | | | | | | | | | | | | | issue_fx1 latency | | | | | | | core_block | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | no_ram | +//| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | no_pre | +//| | | | 1 1111111112 22222222233 | | 22222222233 | | | | | | | | | | | | | | | | | | | | | | | | +//| | 012345 67890 1234567890 12345678901 | 012345 12345678901 | | | | | | | | | | | | 0123 | | | | | | | | | | | +//*TYPE*==========================================================+================================================================================================+ +//| P PPPPPP PPPPP PPPPPPPPPP PPPPPPPPPPP P PPPPPP PPPPPPPPPPP | S S S S S S S S S S S SSSS S S S S S S S S S S | +//*TERMS*=========================================================+================================================================================================+ +//| . ...... ..... .......... ........... 1 011111 0000000000. | 0 - 1 0 1 0 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | cmp (fused) +//| . ...... ..... .......... ........... 1 001011 ........... | 0 - 1 0 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | cmpi (fused) +//| . ...... ..... .......... ........... 1 011111 0000100000. | 0 - 1 0 1 0 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | cmpl (fused) +//| . ...... ..... .......... ........... 1 001010 ........... | 0 - 1 0 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | cmpli (fused) +//| . 011111 ..... .......... 01000010100 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0000 0 0 0 0 1 0 0 0 0 0 | add +//| . 011111 ..... .......... 01000010101 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | add. +//| . 011111 ..... .......... 00000010100 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | addc +//| . 011111 ..... .......... 00000010101 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | addc. +//| . 011111 ..... .......... 10000010100 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | addco +//| . 011111 ..... .......... 10000010101 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | addco. +//| . 011111 ..... .......... 00100010100 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | adde +//| . 011111 ..... .......... 00100010101 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | adde. +//| . 011111 ..... .......... 10100010100 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | addeo +//| . 011111 ..... .......... 10100010101 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | addeo. +//| . 011111 ..... .......... .001001010. 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0010 0 0 0 0 1 0 0 0 0 0 | addg6s +//| . 001110 ..... .......... ........... 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0000 0 0 0 1 1 0 0 0 0 0 | addi +//| . 001100 ..... .......... ........... 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | addic +//| . 001101 ..... .......... ........... 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | addic. +//| . 001111 ..... .......... ........... 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0000 0 0 0 1 1 0 0 0 0 0 | addis +//| . 011111 ..... .......... 00111010100 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | addme +//| . 011111 ..... .......... 00111010101 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | addme. +//| . 011111 ..... .......... 10111010100 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | addmeo +//| . 011111 ..... .......... 10111010101 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | addmeo. +//| . 011111 ..... .......... 11000010100 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | addo +//| . 011111 ..... .......... 11000010101 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | addo. +//| . 011111 ..... .......... 00110010100 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | addze +//| . 011111 ..... .......... 00110010101 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | addze. +//| . 011111 ..... .......... 10110010100 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | addzeo +//| . 011111 ..... .......... 10110010101 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | addzeo. +//| . 011111 ..... .......... 00000111000 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | and +//| . 011111 ..... .......... 00000111001 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | and. +//| . 011111 ..... .......... 00001111000 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | andc +//| . 011111 ..... .......... 00001111001 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | andc. +//| . 011100 ..... .......... ........... 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | andi. +//| . 011101 ..... .......... ........... 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | andis. +//| . 000000 ..... .......... 0100000000. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0110 0 0 0 0 1 0 1 0 0 0 | attn +//| . 010010 ..... .......... .........00 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | b +//| . 010010 ..... .......... .........10 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | ba +//| . 010000 ..0.. .......... .........00 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | bc +//| . 010000 ..1.. .......... .........00 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | bc +//| . 010000 ..0.. .......... .........10 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | bca +//| . 010000 ..1.. .......... .........10 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | bca +//| . 010011 ..1.. .......... 10000100000 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | bcctr +//| . 010011 ..1.. .......... 10000100001 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | bcctrl +//| . 010000 ..0.. .......... .........01 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | bcl +//| . 010000 ..1.. .......... .........01 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | bcl +//| . 010000 ..0.. .......... .........11 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | bcla +//| . 010000 ..1.. .......... .........11 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | bcla +//| . 010011 ..0.. .......... 00000100000 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | bclr +//| . 010011 ..1.. .......... 00000100000 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | bclr +//| . 010011 ..0.. .......... 00000100001 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | bclrl +//| . 010011 ..1.. .......... 00000100001 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | bclrl +//| . 010011 ..0.. .......... 10001100000 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | bctar +//| . 010011 ..1.. .......... 10001100000 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | bctar +//| . 010011 ..0.. .......... 10001100001 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | bctarl +//| . 010011 ..1.. .......... 10001100001 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | bctarl +//| . 010010 ..... .......... .........01 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | bl +//| . 010010 ..... .......... .........11 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | bla +//| 1 011111 ..... .......... 0011111100. 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 0 0010 0 0 0 0 1 0 0 0 0 0 | bpermd +//| . 011111 ..... .......... 0100111010. 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 0 0010 0 0 0 0 1 0 0 0 0 0 | cbcdtd +//| . 011111 ..... .......... 0100011010. 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 0 0010 0 0 0 0 1 0 0 0 0 0 | cdtbcd +//| . 011111 ..... .......... 0000000000. 0 ...... ........... | 0 - 1 0 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | cmp +//| . 011111 ..... .......... 0111111100. 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | cmpb +//| . 001011 ..... .......... ........... 0 ...... ........... | 0 - 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | cmpi +//| . 011111 ..... .......... 0000100000. 0 ...... ........... | 0 - 1 0 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | cmpl +//| . 001010 ..... .......... ........... 0 ...... ........... | 0 - 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | cmpli +//| 1 011111 ..... .......... 00001110100 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 0 0010 0 0 0 0 1 0 0 0 0 0 | cntlzd +//| 1 011111 ..... .......... 00001110101 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 0 0010 0 0 0 0 1 0 0 0 0 0 | cntlzd. +//| . 011111 ..... .......... 00000110100 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 0 0010 0 0 0 0 1 0 0 0 0 0 | cntlzw +//| . 011111 ..... .......... 00000110101 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 0 0010 0 0 0 0 1 0 0 0 0 0 | cntlzw. +//| . 010011 ..... .......... 0100000001. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | crand +//| . 010011 ..... .......... 0010000001. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | crandc +//| . 010011 ..... .......... 0100100001. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | creqv +//| . 010011 ..... .......... 0011100001. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | crnand +//| . 010011 ..... .......... 0000100001. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | crnor +//| . 010011 ..... .......... 0111000001. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | cror +//| . 010011 ..... .......... 0110100001. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | crorc +//| . 010011 ..... .......... 0011000001. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0011 0 0 0 0 1 0 0 0 0 0 | crxor +//| . 011111 ..... .......... 1011110110. 0 ...... ........... | 0 - 1 0 1 0 0 0 0 0 0 ---- 0 0 0 1 1 0 0 0 0 0 | dcba +//| . 011111 ..... .......... 0001010110. 0 ...... ........... | 0 - 1 0 1 0 0 1 1 0 0 0011 0 1 0 1 1 0 0 0 0 0 | dcbf +//| . 011111 ..... .......... 0001111111. 0 ...... ........... | 0 - 1 0 1 0 0 1 1 0 0 0011 0 1 0 1 1 0 0 0 0 0 | dcbfep +//| . 011111 ..... .......... 0111010110. 0 ...... ........... | 0 - 1 0 1 0 0 1 1 0 0 0011 0 1 0 1 1 0 0 0 0 0 | dcbi +//| . 011111 ..... .......... 0110000110. 0 ...... ........... | 0 - 1 0 1 0 0 1 1 0 0 0011 0 1 0 1 1 0 0 0 0 0 | dcblc +//| . 011111 ..... .......... 0000110110. 0 ...... ........... | 0 - 1 0 1 0 0 1 1 0 0 0011 0 1 0 1 1 0 0 0 0 0 | dcbst +//| . 011111 ..... .......... 0000111111. 0 ...... ........... | 0 - 1 0 1 0 0 1 1 0 0 0011 0 1 0 1 1 0 0 0 0 0 | dcbstep +//| . 011111 ..... .......... 0100010110. 0 ...... ........... | 0 - 1 0 1 0 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | dcbt +//| . 011111 ..... .......... 0100111111. 0 ...... ........... | 0 - 1 0 1 0 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | dcbtep +//| . 011111 ..... .......... 0010100110. 0 ...... ........... | 0 - 1 0 1 0 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | dcbtls +//| . 011111 ..... .......... 0011110110. 0 ...... ........... | 0 - 1 0 1 0 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | dcbtst +//| . 011111 ..... .......... 0011111111. 0 ...... ........... | 0 - 1 0 1 0 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | dcbtstep +//| . 011111 ..... .......... 0010000110. 0 ...... ........... | 0 - 1 0 1 0 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | dcbtstls +//| . 011111 ..... .......... 1111110110. 0 ...... ........... | 0 - 1 0 1 0 0 1 1 0 0 0011 0 1 0 1 1 0 0 0 0 0 | dcbz +//| . 011111 ..... .......... 1111111111. 0 ...... ........... | 0 - 1 0 1 0 0 1 1 0 0 0011 0 1 0 1 1 0 0 0 0 0 | dcbzep +//| . 011111 ..... .......... 0111000110. 0 ...... ........... | 0 - 0 - 0 - 0 1 1 0 0 0011 0 0 0 0 1 0 0 0 0 0 | dci +//| 1 011111 ..... .......... 01111010010 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divd +//| 1 011111 ..... .......... 01111010011 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divd. +//| 1 011111 ..... .......... 01101010010 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divde +//| 1 011111 ..... .......... 01101010011 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divde. +//| 1 011111 ..... .......... 11101010010 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divdeo +//| 1 011111 ..... .......... 11101010011 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divdeo. +//| 1 011111 ..... .......... 01100010010 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divdeu +//| 1 011111 ..... .......... 01100010011 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divdeu. +//| 1 011111 ..... .......... 11100010010 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divdeuo +//| 1 011111 ..... .......... 11100010011 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divdeuo. +//| 1 011111 ..... .......... 11111010010 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divdo +//| 1 011111 ..... .......... 11111010011 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divdo. +//| 1 011111 ..... .......... 01110010010 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divdu +//| 1 011111 ..... .......... 01110010011 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divdu. +//| 1 011111 ..... .......... 11110010010 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divduo +//| 1 011111 ..... .......... 11110010011 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divduo. +//| . 011111 ..... .......... 01111010110 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divw +//| . 011111 ..... .......... 01111010111 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divw. +//| . 011111 ..... .......... 01101010110 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divwe +//| . 011111 ..... .......... 01101010111 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divwe. +//| . 011111 ..... .......... 11101010110 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divweo +//| . 011111 ..... .......... 11101010111 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divweo. +//| . 011111 ..... .......... 01100010110 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divweu +//| . 011111 ..... .......... 01100010111 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divweu. +//| . 011111 ..... .......... 11100010110 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divweuo +//| . 011111 ..... .......... 11100010111 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divweuo. +//| . 011111 ..... .......... 11111010110 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divwo +//| . 011111 ..... .......... 11111010111 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divwo. +//| . 011111 ..... .......... 01110010110 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divwu +//| . 011111 ..... .......... 01110010111 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divwu. +//| . 011111 ..... .......... 11110010110 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divwuo +//| . 011111 ..... .......... 11110010111 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | divwuo. +//| . 011111 ..... .......... 00010011100 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 0 0001 0 0 0 0 1 0 0 0 0 0 | dlmzb +//| . 011111 ..... .......... 00010011101 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 0 0001 0 0 0 0 1 0 0 0 0 0 | dlmzb. +//| . 010011 ..... .......... 0011000110. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0111 1 0 0 0 1 1 1 0 0 0 | dnh +//| . 011111 ..... .......... 0100001110. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0001 0 0 0 0 1 0 0 0 0 0 | ehpriv +//| . 011111 ..... .......... 01000111000 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | eqv +//| . 011111 ..... .......... 01000111001 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | eqv. +//| . 011111 ..... .......... 0000110011. 0 ...... ........... | 0 - 1 0 1 0 0 0 0 1 0 0111 1 0 0 1 1 1 1 1 0 0 | eratilx +//| . 011111 ..... .......... 1100110011. 0 ...... ........... | 0 - 1 0 1 0 1 0 0 1 0 0111 1 0 0 1 1 1 1 1 0 0 | erativax +//| . 011111 ..... .......... 0010110011. 0 ...... ........... | 1 0 0 - 1 1 0 0 0 1 0 0111 1 0 0 0 1 1 0 0 0 0 | eratre +//| . 011111 ..... .......... 0010010011. 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 1 1 1 0 0 0 0 | eratsx +//| . 011111 ..... .......... 00100100111 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 1 0 0 0 1 1 0 0 0 0 | eratsx. +//| . 011111 ..... .......... 0011010011. 0 ...... ........... | 0 - 1 1 1 1 0 0 0 1 0 0111 1 0 0 0 1 1 0 0 0 0 | eratwe +//| . 011111 ..... .......... 11101110100 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | extsb +//| . 011111 ..... .......... 11101110101 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | extsb. +//| . 011111 ..... .......... 11100110100 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | extsh +//| . 011111 ..... .......... 11100110101 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | extsh. +//| 1 011111 ..... .......... 11110110100 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | extsw +//| 1 011111 ..... .......... 11110110101 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | extsw. +//| . 011111 ..... .......... 1111010110. 0 ...... ........... | 0 - 1 0 1 0 0 1 1 0 0 0011 0 1 0 1 1 0 0 0 0 0 | icbi +//| . 011111 ..... .......... 1111011111. 0 ...... ........... | 0 - 1 0 1 0 0 1 1 0 0 0011 0 1 0 1 1 0 0 0 0 0 | icbiep +//| . 011111 ..... .......... 0011100110. 0 ...... ........... | 0 - 1 0 1 0 0 1 1 0 0 0011 0 1 0 1 1 0 0 0 0 0 | icblc +//| . 011111 ..... .......... 0000010110. 0 ...... ........... | 0 - 1 0 1 0 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | icbt +//| . 011111 ..... .......... 0111100110. 0 ...... ........... | 0 - 1 0 1 0 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | icbtls +//| . 011111 ..... .......... 1111000110. 0 ...... ........... | 0 - 0 - 0 - 0 1 1 0 0 0011 0 0 0 0 1 0 0 0 0 0 | ici +//| . 011111 ..... .......... 11101101100 0 ...... ........... | 0 - 1 0 1 0 1 1 1 0 1 0011 0 1 0 1 1 0 0 0 0 0 | icswepx +//| . 011111 ..... .......... 11101101101 0 ...... ........... | 0 - 1 0 1 0 1 1 1 0 1 0011 0 1 0 1 1 0 1 0 0 0 | icswepx. +//| . 011111 ..... .......... 01100101100 0 ...... ........... | 0 - 1 0 1 0 1 1 1 0 1 0011 0 1 0 1 1 0 0 0 0 0 | icswx +//| . 011111 ..... .......... 01100101101 0 ...... ........... | 0 - 1 0 1 0 1 1 1 0 1 0011 0 1 0 1 1 0 1 0 0 0 | icswx. +//| . 011111 ..... .......... .....01111. 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0001 0 0 0 1 1 0 0 0 0 0 | isel +//| . 010011 ..... .......... 0010010110. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 0 0 ---- 0 0 0 0 1 0 1 0 0 0 | isync +//| . 011111 ..... .......... 0000110100. 0 ...... ........... | 1 0 1 0 1 0 0 1 0 0 0 0111 0 1 1 1 1 0 0 0 0 0 | lbarx +//| . 011111 ..... .......... 0001011111. 0 ...... ........... | 1 0 1 0 1 0 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | lbepx +//| . 100010 ..... .......... ........... 0 ...... ........... | 1 0 1 0 0 - 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | lbz +//| . 100011 ..... .......... ........... 0 ...... ........... | 1 0 1 0 0 - 0 1 0 0 0 0011 0 1 0 0 1 0 0 0 1 0 | lbzu +//| . 011111 ..... .......... 0001110111. 0 ...... ........... | 1 0 1 0 1 0 0 1 0 0 0 0011 0 1 0 0 1 0 0 0 1 0 | lbzux +//| . 011111 ..... .......... 0001010111. 0 ...... ........... | 1 0 1 0 1 0 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | lbzx +//| 1 111010 ..... .......... .........00 0 ...... ........... | 1 0 1 0 0 - 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | ld +//| 1 011111 ..... .......... 0001010100. 0 ...... ........... | 1 0 1 0 1 0 0 1 0 0 0 0111 0 1 1 1 1 0 0 0 0 0 | ldarx +//| . 011111 ..... .......... 00110101001 0 ...... ........... | 1 0 1 0 1 0 0 1 0 0 0 0111 0 1 1 1 1 0 0 0 0 0 | ldawx. +//| 1 011111 ..... .......... 1000010100. 0 ...... ........... | 1 0 1 0 1 0 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | ldbrx +//| 1 011111 ..... .......... 0000011101. 0 ...... ........... | 1 0 1 0 1 0 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | ldepx +//| 1 111010 ..... .......... .........01 0 ...... ........... | 1 0 1 0 0 - 0 1 0 0 0 0011 0 1 0 0 1 0 0 0 1 0 | ldu +//| 1 011111 ..... .......... 0000110101. 0 ...... ........... | 1 0 1 0 1 0 0 1 0 0 0 0011 0 1 0 0 1 0 0 0 1 0 | ldux +//| 1 011111 ..... .......... 0000010101. 0 ...... ........... | 1 0 1 0 1 0 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | ldx +//| . 101010 ..... .......... ........... 0 ...... ........... | 1 0 1 0 0 - 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | lha +//| . 011111 ..... .......... 0001110100. 0 ...... ........... | 1 0 1 0 1 0 0 1 0 0 0 0111 0 1 1 1 1 0 0 0 0 0 | lharx +//| . 101011 ..... .......... ........... 0 ...... ........... | 1 0 1 0 0 - 0 1 0 0 0 0011 0 1 0 0 1 0 0 0 1 0 | lhau +//| . 011111 ..... .......... 0101110111. 0 ...... ........... | 1 0 1 0 1 0 0 1 0 0 0 0011 0 1 0 0 1 0 0 0 1 0 | lhaux +//| . 011111 ..... .......... 0101010111. 0 ...... ........... | 1 0 1 0 1 0 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | lhax +//| . 011111 ..... .......... 1100010110. 0 ...... ........... | 1 0 1 0 1 0 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | lhbrx +//| . 011111 ..... .......... 0100011111. 0 ...... ........... | 1 0 1 0 1 0 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | lhepx +//| . 101000 ..... .......... ........... 0 ...... ........... | 1 0 1 0 0 - 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | lhz +//| . 101001 ..... .......... ........... 0 ...... ........... | 1 0 1 0 0 - 0 1 0 0 0 0011 0 1 0 0 1 0 0 0 1 0 | lhzu +//| . 011111 ..... .......... 0100110111. 0 ...... ........... | 1 0 1 0 1 0 0 1 0 0 0 0011 0 1 0 0 1 0 0 0 1 0 | lhzux +//| . 011111 ..... .......... 0100010111. 0 ...... ........... | 1 0 1 0 1 0 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | lhzx +//| . 101110 ..... .......... ........... 0 ...... ........... | 1 0 1 0 0 - 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 1 0 | lmw +//| . 011111 ..... .......... 1001010101. 0 ...... ........... | 1 0 1 0 0 - 0 1 0 0 0 0011 0 1 0 1 1 0 0 0 1 0 | lswi +//| . 011111 ..... .......... 1000010101. 0 ...... ........... | 1 0 1 0 1 0 0 1 1 0 1 0011 0 1 0 1 1 0 0 0 1 0 | lswx +//| 1 111010 ..... .......... .........10 0 ...... ........... | 1 0 1 0 0 - 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | lwa +//| . 011111 ..... .......... 0000010100. 0 ...... ........... | 1 0 1 0 1 0 0 1 0 0 0 0111 0 1 1 1 1 0 0 0 0 0 | lwarx +//| 1 011111 ..... .......... 0101110101. 0 ...... ........... | 1 0 1 0 1 0 0 1 0 0 0 0011 0 1 0 0 1 0 0 0 1 0 | lwaux +//| 1 011111 ..... .......... 0101010101. 0 ...... ........... | 1 0 1 0 1 0 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | lwax +//| . 011111 ..... .......... 1000010110. 0 ...... ........... | 1 0 1 0 1 0 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | lwbrx +//| . 011111 ..... .......... 0000011111. 0 ...... ........... | 1 0 1 0 1 0 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | lwepx +//| . 100000 ..... .......... ........... 0 ...... ........... | 1 0 1 0 0 - 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | lwz +//| . 100001 ..... .......... ........... 0 ...... ........... | 1 0 1 0 0 - 0 1 0 0 0 0011 0 1 0 0 1 0 0 0 1 0 | lwzu +//| . 011111 ..... .......... 0000110111. 0 ...... ........... | 1 0 1 0 1 0 0 1 0 0 0 0011 0 1 0 0 1 0 0 0 1 0 | lwzux +//| . 011111 ..... .......... 0000010111. 0 ...... ........... | 1 0 1 0 1 0 0 1 0 0 0 0011 0 1 1 1 1 0 0 0 0 0 | lwzx +//| . 011111 ..... .......... 0000110010. 0 ...... ........... | 0 - 0 - 0 - 0 1 1 0 0 0011 0 0 0 0 1 0 0 0 0 0 | makeitso +//| . 011111 ..... .......... 1101010110. 0 ...... ........... | 0 - 0 - 0 - 0 1 1 0 0 0011 0 0 0 0 1 0 0 0 0 0 | mbar +//| . 010011 ..... .......... 0000000000. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0001 0 0 0 0 1 0 0 0 0 0 | mcrf +//| . 011111 ..... .......... 1000000000. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 0 0 ---- 0 0 0 0 1 0 0 0 1 0 | mcrxr +//| . 011111 ..... 0......... 0000010011. 0 ...... ........... | 1 0 0 - 0 - 0 0 0 0 0 ---- 0 0 0 0 1 0 0 0 1 0 | mfcr +//| . 011111 ..... .......... 0101000011. 0 ...... ........... | 0 0 0 - 0 - 0 0 0 0 0 ---- 1 0 0 0 1 0 0 0 0 0 | mfdcr +//| . 011111 ..... .......... 0100100011. 0 ...... ........... | 0 0 0 - 1 1 0 0 0 0 0 ---- 1 0 0 0 1 0 0 0 0 0 | mfdcrux +//| . 011111 ..... .......... 0100000011. 0 ...... ........... | 0 0 0 - 1 1 0 0 0 0 0 ---- 1 0 0 0 1 0 0 0 0 0 | mfdcrx +//| . 011111 ..... .......... 00001000110 0 ...... ........... | 1 0 0 - 0 - 0 1 0 0 0 0111 0 0 0 0 1 0 0 0 0 0 | mfdp +//| . 011111 ..... .......... 00001000111 0 ...... ........... | 1 0 0 - 0 - 0 1 0 0 0 0111 0 0 0 0 1 0 0 0 0 0 | mfdp. +//| . 011111 ..... .......... 00000000110 0 ...... ........... | 1 0 1 0 0 - 0 1 0 0 0 0111 0 0 0 0 1 0 0 0 0 0 | mfdpx +//| . 011111 ..... .......... 00000000111 0 ...... ........... | 1 0 1 0 0 - 0 1 0 0 0 0111 0 0 0 0 1 0 0 0 0 0 | mfdpx. +//| . 011111 ..... .......... 0001010011. 0 ...... ........... | 1 0 0 - 0 - 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | mfmsr +//| . 011111 ..... 1......... 0000010011. 0 ...... ........... | 1 0 0 - 0 - 0 0 0 1 0 0001 0 0 0 0 1 0 0 0 0 0 | mfocrf +//| . 011111 ..... 0100000000 0101010011. 0 ...... ........... | 1 0 0 - 0 - 0 0 0 1 0 0001 0 0 0 0 1 0 0 0 0 0 | mfspr (lr) need clean up +//| . 011111 ..... 0100100000 0101010011. 0 ...... ........... | 1 0 0 - 0 - 0 0 0 1 0 0001 0 0 0 0 1 0 0 0 0 0 | mfspr (ctr) +//| . 011111 ..... 0000100000 0101010011. 0 ...... ........... | 1 0 0 - 0 - 0 0 0 1 0 0001 0 0 0 0 1 0 0 0 0 0 | mfspr (xer) +//| . 011111 ..... 0000000000 0101010011. 0 ...... ........... | 1 0 0 - 0 - 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | mfspr (spr) +//| . 011111 ..... P.PP.PPPPP 0101010011. 0 ...... ........... | 1 0 0 - 0 - 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | mfspr (spr) +//| . 011111 ..... .......... 0101110011. 0 ...... ........... | 1 0 0 - 0 - 0 0 0 1 0 0111 1 0 0 0 1 0 0 0 0 0 | mftb +//| . 011111 ..... .......... 0011101110. 0 ...... ........... | 0 - 0 - 1 0 0 0 0 1 0 0111 1 0 0 0 1 1 0 0 0 0 | msgclr +//| . 011111 ..... .......... 0011001110. 0 ...... ........... | 0 - 0 - 1 0 0 1 1 0 0 0011 0 0 0 0 1 0 0 0 0 0 | msgsnd +//| . 011111 ..... 0......... 0010010000. 0 ...... ........... | 0 - 1 1 0 - 0 0 0 0 0 ---- 0 0 0 0 1 0 0 0 1 0 | mtcrf +//| . 011111 ..... .......... 0111000011. 0 ...... ........... | 0 - 1 1 0 - 0 0 0 0 0 ---- 1 0 0 0 1 0 0 0 0 0 | mtdcr +//| . 011111 ..... .......... 0110100011. 0 ...... ........... | 0 - 1 1 1 1 0 0 0 0 0 ---- 1 0 0 0 1 0 0 0 0 0 | mtdcrux +//| . 011111 ..... .......... 0110000011. 0 ...... ........... | 0 - 1 1 1 1 0 0 0 0 0 ---- 1 0 0 0 1 0 0 0 0 0 | mtdcrx +//| . 011111 ..... .......... 00011000110 0 ...... ........... | 0 - 0 - 0 - 1 1 0 0 0 0011 0 0 0 0 1 0 0 0 0 0 | mtdp +//| . 011111 ..... .......... 00011000111 0 ...... ........... | 0 - 0 - 0 - 1 1 0 0 0 0111 0 0 0 0 1 0 0 0 0 0 | mtdp. +//| . 011111 ..... .......... 00010000110 0 ...... ........... | 0 - 1 0 0 - 1 1 0 0 0 0011 0 0 0 0 1 0 0 0 0 0 | mtdpx +//| . 011111 ..... .......... 00010000111 0 ...... ........... | 0 - 1 0 0 - 1 1 0 0 0 0111 0 0 0 0 1 0 0 0 0 0 | mtdpx. +//| . 011111 ..... .......... 0010010010. 0 ...... ........... | 0 - 1 1 0 - 0 0 0 1 0 0111 1 0 0 0 1 1 0 0 0 0 | mtmsr +//| . 011111 ..... 1PPPPPPPP. 0010010000. 0 ...... ........... | 0 - 1 1 0 - 0 0 0 1 0 0001 0 0 0 0 1 0 0 0 0 0 | mtocrf +//| . 011111 ..... 100000000. 0010010000. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 0 0 ---- 0 0 0 0 1 0 0 0 0 0 | mtocrf +//| . 011111 ..... 0100000000 0111010011. 0 ...... ........... | 0 - 1 1 0 - 0 0 0 1 0 0001 0 0 0 0 1 1 0 0 0 0 | mtspr (lr) +//| . 011111 ..... 0100100000 0111010011. 0 ...... ........... | 0 - 1 1 0 - 0 0 0 1 0 0001 0 0 0 0 1 1 0 0 0 0 | mtspr (ctr) +//| . 011111 ..... 0000100000 0111010011. 0 ...... ........... | 0 - 1 1 0 - 0 0 0 1 0 0001 0 0 0 0 1 1 0 0 0 0 | mtspr (xer) +//| . 011111 ..... 0000000000 0111010011. 0 ...... ........... | 0 - 1 1 0 - 0 0 0 1 0 0111 1 0 0 0 1 1 0 0 0 0 | mtspr (spr) +//| . 011111 ..... P.PP.PPPPP 0111010011. 0 ...... ........... | 0 - 1 1 0 - 0 0 0 1 0 0111 1 0 0 0 1 1 0 0 0 0 | mtspr (spr) +//| 1 011111 ..... .......... .0010010010 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 0 0 0 0 1 0 0 0 0 0 | mulhd +//| 1 011111 ..... .......... .0010010011 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 0 0 0 0 1 0 0 0 0 0 | mulhd. +//| 1 011111 ..... .......... .0000010010 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 0 0 0 0 1 0 0 0 0 0 | mulhdu +//| 1 011111 ..... .......... .0000010011 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 0 0 0 0 1 0 0 0 0 0 | mulhdu. +//| . 011111 ..... .......... .0010010110 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0100 0 0 0 0 1 0 0 0 0 0 | mulhw +//| . 011111 ..... .......... .0010010111 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0100 0 0 0 0 1 0 0 0 0 0 | mulhw. +//| . 011111 ..... .......... .0000010110 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0100 0 0 0 0 1 0 0 0 0 0 | mulhwu +//| . 011111 ..... .......... .0000010111 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0100 0 0 0 0 1 0 0 0 0 0 | mulhwu. +//| 1 011111 ..... .......... 00111010010 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0110 0 0 0 0 1 0 0 0 0 0 | mulld +//| 1 011111 ..... .......... 00111010011 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0110 0 0 0 0 1 0 0 0 0 0 | mulld. +//| 1 011111 ..... .......... 10111010010 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 0 0 0 0 1 0 0 0 0 0 | mulldo +//| 1 011111 ..... .......... 10111010011 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0111 0 0 0 0 1 0 0 0 0 0 | mulldo. +//| . 000111 ..... .......... ........... 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 0 0101 0 0 0 0 1 0 0 0 0 0 | mulli +//| . 011111 ..... .......... 00111010110 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0100 0 0 0 0 1 0 0 0 0 0 | mullw +//| . 011111 ..... .......... 00111010111 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0100 0 0 0 0 1 0 0 0 0 0 | mullw. +//| . 011111 ..... .......... 10111010110 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0100 0 0 0 0 1 0 0 0 0 0 | mullwo +//| . 011111 ..... .......... 10111010111 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 0 0100 0 0 0 0 1 0 0 0 0 0 | mullwo. +//| . 011111 ..... .......... 01110111000 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | nand +//| . 011111 ..... .......... 01110111001 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | nand. +//| . 011111 ..... .......... 00011010000 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | neg +//| . 011111 ..... .......... 00011010001 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | neg. +//| . 011111 ..... .......... 10011010000 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | nego +//| . 011111 ..... .......... 10011010001 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | nego. +//| . 011111 ..... .......... 00011111000 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | nor +//| . 011111 ..... .......... 00011111001 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | nor. +//| . 011111 ..... .......... 01101111000 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | or +//| . 011111 ..... .......... 01101111001 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | or. +//| . 011111 ..... .......... 01100111000 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | orc +//| . 011111 ..... .......... 01100111001 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | orc. +//| . 011000 00000 0000000000 00000000000 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | ori (nop) +//| . 011000 PPPPP PPPPPPPPPP PPPPPPPPPPP 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | ori (ori) +//| . 011001 ..... .......... ........... 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | oris +//| . 011111 ..... .......... 0001111010. 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 0 0111 0 0 0 0 1 0 0 0 0 0 | popcntb +//| 1 011111 ..... .......... 0111111010. 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 0 0111 0 0 0 0 1 0 0 0 0 0 | popcntd +//| . 011111 ..... .......... 0101111010. 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 0 0111 0 0 0 0 1 0 0 0 0 0 | popcntw +//| 1 011111 ..... .......... 0010111010. 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | prtyd +//| . 011111 ..... .......... 0010011010. 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | prtyw +//| . 011111 ..... .......... 1000010010. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 0 0 ---- 0 0 0 0 1 0 0 0 0 0 | reserved +//| . 011111 ..... .......... 1000110010. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 0 0 ---- 0 0 0 0 1 0 0 0 0 0 | reserved +//| . 011111 ..... .......... 1001010010. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 0 0 ---- 0 0 0 0 1 0 0 0 0 0 | reserved +//| . 011111 ..... .......... 1001110010. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 0 0 ---- 0 0 0 0 1 0 0 0 0 0 | reserved +//| . 011111 ..... .......... 1010010010. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 0 0 ---- 0 0 0 0 1 0 0 0 0 0 | reserved +//| . 011111 ..... .......... 1010110010. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 0 0 ---- 0 0 0 0 1 0 0 0 0 0 | reserved +//| . 011111 ..... .......... 1011010010. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 0 0 ---- 0 0 0 0 1 0 0 0 0 0 | reserved +//| . 011111 ..... .......... 1011110010. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 0 0 ---- 0 0 0 0 1 0 0 0 0 0 | reserved +//| . 010011 ..... .......... 0000110011. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 0 0 ---- 1 0 0 0 1 0 0 0 0 0 | rfci +//| . 010011 ..... .......... 0001100110. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 0 0 ---- 1 0 0 0 1 0 0 0 0 0 | rfgi +//| . 010011 ..... .......... 0000110010. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 0 0 ---- 1 0 0 0 1 0 0 0 0 0 | rfi +//| . 010011 ..... .......... 0000100110. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 0 0 ---- 1 0 0 0 1 0 0 0 0 0 | rfmci +//| 1 011110 ..... .......... ......10000 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | rldcl +//| 1 011110 ..... .......... ......10001 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | rldcl. +//| 1 011110 ..... .......... ......10010 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | rldcr +//| 1 011110 ..... .......... ......10011 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | rldcr. +//| 1 011110 ..... .......... ......010.0 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | rldic +//| 1 011110 ..... .......... ......010.1 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | rldic. +//| 1 011110 ..... .......... ......000.0 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | rldicl +//| 1 011110 ..... .......... ......000.1 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | rldicl. +//| 1 011110 ..... .......... ......001.0 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | rldicr +//| 1 011110 ..... .......... ......001.1 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | rldicr. +//| 1 011110 ..... .......... ......011.0 0 ...... ........... | 1 1 1 1 1 1 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | rldimi +//| 1 011110 ..... .......... ......011.1 0 ...... ........... | 1 1 1 1 1 1 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | rldimi. +//| . 010100 ..... .......... ..........0 0 ...... ........... | 1 1 1 1 1 1 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | rlwimi +//| . 010100 ..... .......... ..........1 0 ...... ........... | 1 1 1 1 1 1 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | rlwimi. +//| . 010101 ..... .......... ..........0 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | rlwinm +//| . 010101 ..... .......... ..........1 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | rlwinm. +//| . 010111 ..... .......... ..........0 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | rlwnm +//| . 010111 ..... .......... ..........1 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | rlwnm. +//| . 010001 ..... .......... .........1. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 0 0 ---- 1 0 0 0 1 0 0 0 0 0 | sc +//| 1 011111 ..... .......... 00000110110 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | sld +//| 1 011111 ..... .......... 00000110111 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | sld. +//| . 011111 ..... .......... 00000110000 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | slw +//| . 011111 ..... .......... 00000110001 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | slw. +//| 1 011111 ..... .......... 11000110100 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | srad +//| 1 011111 ..... .......... 11000110101 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | srad. +//| 1 011111 ..... .......... 110011101.0 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | sradi +//| 1 011111 ..... .......... 110011101.1 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | sradi. +//| . 011111 ..... .......... 11000110000 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | sraw +//| . 011111 ..... .......... 11000110001 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | sraw. +//| . 011111 ..... .......... 11001110000 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | srawi +//| . 011111 ..... .......... 11001110001 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | srawi. +//| 1 011111 ..... .......... 10000110110 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | srd +//| 1 011111 ..... .......... 10000110111 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | srd. +//| . 011111 ..... .......... 10000110000 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | srw +//| . 011111 ..... .......... 10000110001 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | srw. +//| . 100110 ..... .......... ........... 0 ...... ........... | 0 - 1 0 0 - 1 1 1 0 1 0011 0 1 0 1 1 0 0 0 0 1 | stb +//| . 011111 ..... .......... 10101101101 0 ...... ........... | 0 - 1 0 1 0 1 1 1 0 1 0111 0 1 0 1 1 0 1 0 0 1 | stbcx. +//| . 011111 ..... .......... 0011011111. 0 ...... ........... | 0 - 1 0 1 0 1 1 1 0 1 0011 0 1 0 1 1 0 0 0 0 1 | stbepx +//| . 100111 ..... .......... ........... 0 ...... ........... | 1 1 1 0 0 - 1 1 1 0 1 0011 0 1 0 0 1 0 0 0 0 1 | stbu +//| . 011111 ..... .......... 0011110111. 0 ...... ........... | 1 1 1 0 1 0 1 1 1 0 1 0011 0 1 0 0 1 0 0 0 0 1 | stbux +//| . 011111 ..... .......... 0011010111. 0 ...... ........... | 0 - 1 0 1 0 1 1 1 0 1 0011 0 1 0 1 1 0 0 0 0 1 | stbx +//| 1 111110 ..... .......... .........00 0 ...... ........... | 0 - 1 0 0 - 1 1 1 0 1 0011 0 1 0 1 1 0 0 0 0 1 | std +//| 1 011111 ..... .......... 1010010100. 0 ...... ........... | 0 - 1 0 1 0 1 1 1 0 1 0011 0 1 0 1 1 0 0 0 0 1 | stdbrx +//| 1 011111 ..... .......... 00110101101 0 ...... ........... | 0 - 1 0 1 0 1 1 1 0 1 0111 0 1 0 1 1 0 1 0 0 1 | stdcx. +//| 1 011111 ..... .......... 0010011101. 0 ...... ........... | 0 - 1 0 1 0 1 1 1 0 1 0011 0 1 0 1 1 0 0 0 0 1 | stdepx +//| 1 111110 ..... .......... .........01 0 ...... ........... | 1 1 1 0 0 - 1 1 1 0 1 0011 0 1 0 0 1 0 0 0 0 1 | stdu +//| 1 011111 ..... .......... 0010110101. 0 ...... ........... | 1 1 1 0 1 0 1 1 1 0 1 0011 0 1 0 0 1 0 0 0 0 1 | stdux +//| 1 011111 ..... .......... 0010010101. 0 ...... ........... | 0 - 1 0 1 0 1 1 1 0 1 0011 0 1 0 1 1 0 0 0 0 1 | stdx +//| . 101100 ..... .......... ........... 0 ...... ........... | 0 - 1 0 0 - 1 1 1 0 1 0011 0 1 0 1 1 0 0 0 0 1 | sth +//| . 011111 ..... .......... 1110010110. 0 ...... ........... | 0 - 1 0 1 0 1 1 1 0 1 0011 0 1 0 1 1 0 0 0 0 1 | sthbrx +//| . 011111 ..... .......... 10110101101 0 ...... ........... | 0 - 1 0 1 0 1 1 1 0 1 0111 0 1 0 1 1 0 1 0 0 1 | sthcx. +//| . 011111 ..... .......... 0110011111. 0 ...... ........... | 0 - 1 0 1 0 1 1 1 0 1 0011 0 1 0 1 1 0 0 0 0 1 | sthepx +//| . 101101 ..... .......... ........... 0 ...... ........... | 1 1 1 0 0 - 1 1 1 0 1 0011 0 1 0 0 1 0 0 0 0 1 | sthu +//| . 011111 ..... .......... 0110110111. 0 ...... ........... | 1 1 1 0 1 0 1 1 1 0 1 0011 0 1 0 0 1 0 0 0 0 1 | sthux +//| . 011111 ..... .......... 0110010111. 0 ...... ........... | 0 - 1 0 1 0 1 1 1 0 1 0011 0 1 0 1 1 0 0 0 0 1 | sthx +//| . 101111 ..... .......... ........... 0 ...... ........... | 0 - 1 0 0 - 0 1 0 0 0 0011 0 1 0 1 1 0 0 0 1 0 | stmw always ucode only preissue +//| . 011111 ..... .......... 1011010101. 0 ...... ........... | 0 - 1 0 0 - 0 1 0 0 0 0011 0 1 0 1 1 0 0 0 1 0 | stswi always ucode only preissue +//| . 011111 ..... .......... 1010010101. 0 ...... ........... | 0 - 1 0 1 0 0 1 1 0 1 0011 0 1 0 1 1 0 0 0 1 0 | stswx always ucode only preissue +//| . 100100 ..... .......... ........... 0 ...... ........... | 0 - 1 0 0 - 1 1 1 0 1 0011 0 1 0 1 1 0 0 0 0 1 | stw +//| . 011111 ..... .......... 1010010110. 0 ...... ........... | 0 - 1 0 1 0 1 1 1 0 1 0011 0 1 0 1 1 0 0 0 0 1 | stwbrx +//| . 011111 ..... .......... 00100101101 0 ...... ........... | 0 - 1 0 1 0 1 1 1 0 1 0111 0 1 0 1 1 0 1 0 0 1 | stwcx. +//| . 011111 ..... .......... 0010011111. 0 ...... ........... | 0 - 1 0 1 0 1 1 1 0 1 0011 0 1 0 1 1 0 0 0 0 1 | stwepx +//| . 100101 ..... .......... ........... 0 ...... ........... | 1 1 1 0 0 - 1 1 1 0 1 0011 0 1 0 0 1 0 0 0 0 1 | stwu +//| . 011111 ..... .......... 0010110111. 0 ...... ........... | 1 1 1 0 1 0 1 1 1 0 1 0011 0 1 0 0 1 0 0 0 0 1 | stwux +//| . 011111 ..... .......... 0010010111. 0 ...... ........... | 0 - 1 0 1 0 1 1 1 0 1 0011 0 1 0 1 1 0 0 0 0 1 | stwx +//| . 011111 ..... .......... 00001010000 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0000 0 0 0 0 1 0 0 0 0 0 | subf +//| . 011111 ..... .......... 00001010001 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | subf. +//| . 011111 ..... .......... 00000010000 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | subfc +//| . 011111 ..... .......... 00000010001 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | subfc. +//| . 011111 ..... .......... 10000010000 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | subfco +//| . 011111 ..... .......... 10000010001 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | subfco. +//| . 011111 ..... .......... 00100010000 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | subfe +//| . 011111 ..... .......... 00100010001 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | subfe. +//| . 011111 ..... .......... 10100010000 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | subfeo +//| . 011111 ..... .......... 10100010001 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | subfeo. +//| . 001000 ..... .......... ........... 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | subfic +//| . 011111 ..... .......... 00111010000 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | subfme +//| . 011111 ..... .......... 00111010001 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | subfme. +//| . 011111 ..... .......... 10111010000 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | subfmeo +//| . 011111 ..... .......... 10111010001 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | subfmeo. +//| . 011111 ..... .......... 10001010000 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | subfo +//| . 011111 ..... .......... 10001010001 0 ...... ........... | 1 0 1 0 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | subfo. +//| . 011111 ..... .......... 00110010000 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | subfze +//| . 011111 ..... .......... 00110010001 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | subfze. +//| . 011111 ..... .......... 10110010000 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | subfzeo +//| . 011111 ..... .......... 10110010001 0 ...... ........... | 1 0 1 0 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | subfzeo. +//| . 011111 ...00 .......... 1001010110. 0 ...... ........... | 0 - 0 - 0 - 0 1 1 0 0 0011 0 0 0 0 1 0 1 0 0 0 | hwsync +//| . 011111 ...01 .......... 1001010110. 0 ...... ........... | 0 - 0 - 0 - 0 1 1 0 0 0011 0 0 0 0 1 0 0 0 0 0 | lwsync +//| . 011111 ...10 .......... 1001010110. 0 ...... ........... | 0 - 0 - 0 - 0 1 1 0 0 0011 0 0 0 0 1 0 1 0 0 0 | reserve sync +//| . 011111 ...11 .......... 1001010110. 0 ...... ........... | 0 - 0 - 0 - 0 1 1 0 0 0011 0 0 0 0 1 0 1 0 0 0 | reserve sync +//| 1 011111 ..... .......... 0001000100. 0 ...... ........... | 0 - 1 0 1 0 0 0 0 1 0 0000 0 0 0 0 1 0 0 0 0 0 | td +//| 1 000010 ..... .......... ........... 0 ...... ........... | 0 - 1 0 0 - 0 0 0 1 0 0000 0 0 0 0 1 0 0 0 0 0 | tdi +//| . 011111 ..... .......... 0000010010. 0 ...... ........... | 0 - 1 0 1 0 0 0 0 1 0 0110 1 0 0 1 1 1 1 1 0 0 | tlbilx +//| . 011111 ..... .......... 1100010010. 0 ...... ........... | 0 - 1 0 1 0 0 0 0 1 0 0110 1 0 0 1 1 1 1 1 0 0 | tlbivax +//| . 011111 ..... .......... 1110110010. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0110 1 0 0 0 1 1 0 0 0 0 | tlbre +//| . 011111 ..... .......... 11010100101 0 ...... ........... | 0 - 1 0 1 0 0 0 0 1 0 0110 1 0 0 1 1 1 0 0 0 0 | tlbsrx. +//| . 011111 ..... .......... 1110010010. 0 ...... ........... | 0 - 1 0 1 0 0 0 0 1 0 0110 1 0 0 1 1 1 0 0 0 0 | tlbsx +//| . 011111 ..... .......... 11100100101 0 ...... ........... | 0 - 1 0 1 0 0 0 0 1 0 0110 1 0 0 0 1 1 0 0 0 0 | tlbsx. +//| . 011111 ..... .......... 1000110110. 0 ...... ........... | 0 - 0 - 0 - 0 1 1 0 0 0011 0 0 0 0 1 0 1 0 0 0 | tlbsync +//| . 011111 ..... .......... 1111010010. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0110 1 0 0 0 1 1 1 0 0 0 | tlbwe +//| . 011111 ..... .......... 0000000100. 0 ...... ........... | 0 - 1 0 1 0 0 0 0 1 0 0000 0 0 0 0 1 0 0 0 0 0 | tw +//| . 000011 ..... .......... ........... 0 ...... ........... | 0 - 1 0 0 - 0 0 0 1 0 0000 0 0 0 0 1 0 0 0 0 0 | twi +//| . 011111 ..... .......... 0000111110. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0000 1 0 0 0 1 1 0 0 0 0 | wait +//| . 011111 ..... .......... 1110000110. 0 ...... ........... | 0 - 0 - 0 - 0 1 0 0 0 0011 0 1 0 0 1 0 0 0 0 0 | wchkall +//| . 011111 ..... .......... 1110100110. 0 ...... ........... | 0 - 1 0 1 0 0 1 1 0 0 0011 0 1 0 1 1 0 0 0 0 0 | wclr +//| . 011111 ..... .......... 0010000011. 0 ...... ........... | 0 - 1 1 0 - 0 0 0 1 0 0111 1 0 0 0 1 1 0 0 0 0 | wrtee +//| . 011111 ..... .......... 0010100011. 0 ...... ........... | 0 - 0 - 0 - 0 0 0 1 0 0111 1 0 0 0 1 1 0 0 0 0 | wrteei +//| . 011111 ..... .......... 01001111000 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | xor +//| . 011111 ..... .......... 01001111001 0 ...... ........... | 1 1 1 1 1 0 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | xor. +//| . 011010 ..... .......... ........... 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | xori +//| . 011011 ..... .......... ........... 0 ...... ........... | 1 1 1 1 0 - 0 0 0 1 1 0001 0 0 0 0 1 0 0 0 0 0 | xoris +//*END*===========================================================+================================================================================================+ +//?TABLE END instruction_decoder ; +//table_end + + +//assign_start + +assign br_dep_pt[1] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[8] , iu4_instr[31] , + iu4_fuse_cmp[0] , iu4_fuse_cmp[1] , + iu4_fuse_cmp[2] , iu4_fuse_cmp[3] , + iu4_fuse_cmp[4] , iu4_fuse_cmp[5] , + iu4_fuse_cmp[21] , iu4_fuse_cmp[22] , + iu4_fuse_cmp[23] , iu4_fuse_cmp[24] , + iu4_fuse_cmp[26] , iu4_fuse_cmp[27] , + iu4_fuse_cmp[28] , iu4_fuse_cmp[29] , + iu4_fuse_cmp[30] }) === 23'b01000011011111000000000); +assign br_dep_pt[2] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[8] , iu4_fuse_val , + iu4_fuse_cmp[0] , iu4_fuse_cmp[1] , + iu4_fuse_cmp[2] , iu4_fuse_cmp[3] , + iu4_fuse_cmp[4] , iu4_fuse_cmp[5] , + iu4_fuse_cmp[21] , iu4_fuse_cmp[22] , + iu4_fuse_cmp[23] , iu4_fuse_cmp[24] , + iu4_fuse_cmp[26] , iu4_fuse_cmp[27] , + iu4_fuse_cmp[28] , iu4_fuse_cmp[29] , + iu4_fuse_cmp[30] }) === 23'b01000011011111000000000); +assign br_dep_pt[3] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[11] , iu4_instr[12] , + iu4_instr[13] , iu4_instr[14] , + iu4_instr[15] , iu4_instr[16] , + iu4_instr[17] , iu4_instr[18] , + iu4_instr[19] , iu4_instr[20] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 27'b011111010010000001110100110); +assign br_dep_pt[4] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[11] , iu4_instr[12] , + iu4_instr[13] , iu4_instr[14] , + iu4_instr[15] , iu4_instr[16] , + iu4_instr[17] , iu4_instr[18] , + iu4_instr[19] , iu4_instr[20] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 27'b011111010000000001110100110); +assign br_dep_pt[5] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[11] , iu4_instr[12] , + iu4_instr[13] , iu4_instr[14] , + iu4_instr[15] , iu4_instr[16] , + iu4_instr[17] , iu4_instr[18] , + iu4_instr[19] , iu4_instr[20] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 27'b011111010000000001010100110); +assign br_dep_pt[6] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[11] , iu4_instr[12] , + iu4_instr[13] , iu4_instr[14] , + iu4_instr[15] , iu4_instr[16] , + iu4_instr[17] , iu4_instr[18] , + iu4_instr[19] , iu4_instr[20] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 27'b011111000010000001110100110); +assign br_dep_pt[7] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[11] , iu4_instr[12] , + iu4_instr[13] , iu4_instr[14] , + iu4_instr[15] , iu4_instr[16] , + iu4_instr[17] , iu4_instr[18] , + iu4_instr[19] , iu4_instr[20] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 27'b011111010010000001010100110); +assign br_dep_pt[8] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[5] , iu4_instr[11] , + iu4_instr[12] , iu4_instr[13] , + iu4_instr[14] , iu4_instr[15] , + iu4_instr[16] , iu4_instr[17] , + iu4_instr[18] , iu4_instr[19] , + iu4_instr[20] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 26'b01111000010000001010100110); +assign br_dep_pt[9] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[8] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_instr[31] , iu4_fuse_cmp[0] , + iu4_fuse_cmp[1] , iu4_fuse_cmp[2] , + iu4_fuse_cmp[3] , iu4_fuse_cmp[4] + }) === 22'b0100111000010000100101); +assign br_dep_pt[10] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[8] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_instr[31] , iu4_fuse_cmp[0] , + iu4_fuse_cmp[1] , iu4_fuse_cmp[2] , + iu4_fuse_cmp[3] , iu4_fuse_cmp[4] + }) === 22'b0100111100010000100101); +assign br_dep_pt[11] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[8] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val , + iu4_fuse_cmp[0] , iu4_fuse_cmp[1] , + iu4_fuse_cmp[2] , iu4_fuse_cmp[3] , + iu4_fuse_cmp[4] }) === 23'b01001111000110000100101); +assign br_dep_pt[12] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[8] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val , + iu4_fuse_cmp[0] , iu4_fuse_cmp[1] , + iu4_fuse_cmp[2] , iu4_fuse_cmp[3] , + iu4_fuse_cmp[4] }) === 23'b01001111000010000100101); +assign br_dep_pt[13] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[8] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val , + iu4_fuse_cmp[0] , iu4_fuse_cmp[1] , + iu4_fuse_cmp[2] , iu4_fuse_cmp[3] , + iu4_fuse_cmp[4] }) === 23'b01001110000010000100101); +assign br_dep_pt[14] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[8] , iu4_fuse_cmp[0] , + iu4_fuse_cmp[1] , iu4_fuse_cmp[2] , + iu4_fuse_cmp[3] , iu4_fuse_cmp[4] + }) === 12'b010000000101); +assign br_dep_pt[15] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[31] , iu4_fuse_cmp[0] , + iu4_fuse_cmp[1] , iu4_fuse_cmp[2] , + iu4_fuse_cmp[3] , iu4_fuse_cmp[4] + }) === 12'b010000100101); +assign br_dep_pt[16] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[6] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 17'b01001100000000000); +assign br_dep_pt[17] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_instr[31] , + iu4_fuse_val }) === 17'b01001000001000010); +assign br_dep_pt[18] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[6] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 18'b010011010001100000); +assign br_dep_pt[19] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[8] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 18'b010011010001100000); +assign br_dep_pt[20] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[6] , iu4_instr[8] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 18'b010011010000100000); +assign br_dep_pt[21] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_instr[31] , + iu4_fuse_val }) === 17'b01001100011000010); +assign br_dep_pt[22] = + (({ core64 , iu4_instr[0] , + iu4_instr[1] , iu4_instr[3] , + iu4_instr[5] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[31] , iu4_fuse_val + }) === 16'b1011111001110110); +assign br_dep_pt[23] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[3] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_instr[31] , iu4_fuse_val + }) === 16'b0111000100111010); +assign br_dep_pt[24] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[8] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 18'b010011110000100000); +assign br_dep_pt[25] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[8] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 18'b010011000000100000); +assign br_dep_pt[26] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[8] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_instr[31] , + iu4_fuse_val }) === 17'b01001100001000010); +assign br_dep_pt[27] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[11] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 18'b011111100000100110); +assign br_dep_pt[28] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[11] , iu4_instr[19] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 19'b0111111100100100000); +assign br_dep_pt[29] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[11] , iu4_instr[18] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 19'b0111111100100100000); +assign br_dep_pt[30] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[11] , iu4_instr[17] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 19'b0111111100100100000); +assign br_dep_pt[31] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[11] , iu4_instr[16] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 19'b0111111100100100000); +assign br_dep_pt[32] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[11] , iu4_instr[14] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 19'b0111111100100100000); +assign br_dep_pt[33] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[11] , iu4_instr[13] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 19'b0111111100100100000); +assign br_dep_pt[34] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[11] , iu4_instr[15] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 19'b0111111100100100000); +assign br_dep_pt[35] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[11] , iu4_instr[12] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 19'b0111111100100100000); +assign br_dep_pt[36] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_fuse_val , iu4_fuse_cmp[0] , + iu4_fuse_cmp[1] , iu4_fuse_cmp[2] , + iu4_fuse_cmp[3] , iu4_fuse_cmp[4] + }) === 12'b010000100101); +assign br_dep_pt[37] = + (({ core64 , iu4_instr[0] , + iu4_instr[1] , iu4_instr[2] , + iu4_instr[3] , iu4_instr[4] , + iu4_instr[5] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_fuse_val }) === 17'b10111111100111010); +assign br_dep_pt[38] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 17'b01001110001100000); +assign br_dep_pt[39] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 17'b01111100010011100); +assign br_dep_pt[40] = + (({ core64 , iu4_instr[0] , + iu4_instr[1] , iu4_instr[2] , + iu4_instr[3] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[30] , + iu4_instr[31] , iu4_fuse_val + }) === 16'b1011100110101010); +assign br_dep_pt[41] = + (({ core64 , iu4_instr[0] , + iu4_instr[1] , iu4_instr[2] , + iu4_instr[3] , iu4_instr[4] , + iu4_instr[5] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_fuse_val + }) === 16'b1011111101110100); +assign br_dep_pt[42] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 17'b01001100000100000); +assign br_dep_pt[43] = + (({ core64 , iu4_instr[0] , + iu4_instr[1] , iu4_instr[3] , + iu4_instr[5] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[30] , iu4_instr[31] , + iu4_fuse_val }) === 15'b101111100110010); +assign br_dep_pt[44] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_fuse_val + }) === 16'b0111111011101010); +assign br_dep_pt[45] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 17'b01111100000100110); +assign br_dep_pt[46] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[3] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_instr[31] , iu4_fuse_val + }) === 16'b0111101101011010); +assign br_dep_pt[47] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 17'b01111111100001100); +assign br_dep_pt[48] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[3] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_instr[31] , + iu4_fuse_val }) === 15'b011111001100010); +assign br_dep_pt[49] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0100110101000010); +assign br_dep_pt[50] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[5] , iu4_instr[11] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 17'b01111000100100000); +assign br_dep_pt[51] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0100110110000010); +assign br_dep_pt[52] = + (({ core64 , iu4_instr[0] , + iu4_instr[1] , iu4_instr[2] , + iu4_instr[3] , iu4_instr[4] , + iu4_instr[5] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[30] , + iu4_fuse_val }) === 15'b101111111101010); +assign br_dep_pt[53] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0100110011000010); +assign br_dep_pt[54] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[3] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_instr[31] , iu4_fuse_val + }) === 16'b0111110101001010); +assign br_dep_pt[55] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0100110001000010); +assign br_dep_pt[56] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[3] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_instr[31] , + iu4_fuse_val }) === 15'b011111011011010); +assign br_dep_pt[57] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 15'b011111111010110); +assign br_dep_pt[58] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0100110100000010); +assign br_dep_pt[59] = + (({ core64 , iu4_instr[0] , + iu4_instr[1] , iu4_instr[2] , + iu4_instr[3] , iu4_instr[4] , + iu4_instr[5] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b1011111110011000); +assign br_dep_pt[60] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111111001010000); +assign br_dep_pt[61] = + (({ core64 , iu4_instr[0] , + iu4_instr[1] , iu4_instr[3] , + iu4_instr[5] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_instr[31] , iu4_fuse_val + }) === 16'b1011111101101010); +assign br_dep_pt[62] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 17'b01001100000000000); +assign br_dep_pt[63] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0100110010000010); +assign br_dep_pt[64] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[5] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 15'b011111000101010); +assign br_dep_pt[65] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[3] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_instr[31] , iu4_fuse_val + }) === 16'b0111001101010010); +assign br_dep_pt[66] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[3] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_instr[31] , iu4_fuse_val + }) === 16'b0111001001001110); +assign br_dep_pt[67] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111111000010100); +assign br_dep_pt[68] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111111100110000); +assign br_dep_pt[69] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[3] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_instr[31] , + iu4_fuse_val }) === 15'b011101001011010); +assign br_dep_pt[70] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[3] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_instr[31] , + iu4_fuse_val }) === 15'b011101101110010); +assign br_dep_pt[71] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[3] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_instr[31] , + iu4_fuse_val }) === 15'b011111100101010); +assign br_dep_pt[72] = + (({ core64 , iu4_instr[0] , + iu4_instr[1] , iu4_instr[3] , + iu4_instr[5] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_instr[31] , iu4_fuse_val + }) === 16'b1011100001101010); +assign br_dep_pt[73] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[3] , iu4_instr[5] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[30] , iu4_instr[31] , + iu4_fuse_val }) === 13'b0111011010010); +assign br_dep_pt[74] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[3] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_instr[31] , + iu4_fuse_val }) === 15'b011100011110010); +assign br_dep_pt[75] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 17'b01111110000000000); +assign br_dep_pt[76] = + (({ core64 , iu4_instr[0] , + iu4_instr[1] , iu4_instr[3] , + iu4_instr[5] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[31] , iu4_fuse_val + }) === 14'b10111011101010); +assign br_dep_pt[77] = + (({ core64 , iu4_instr[0] , + iu4_instr[1] , iu4_instr[3] , + iu4_instr[5] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_instr[31] , + iu4_fuse_val }) === 15'b101110000101110); +assign br_dep_pt[78] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[3] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_instr[31] , + iu4_fuse_val }) === 15'b011111101101010); +assign br_dep_pt[79] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[3] , iu4_instr[5] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[31] , iu4_fuse_val + }) === 14'b01110111010110); +assign br_dep_pt[80] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 12'b011111011110); +assign br_dep_pt[81] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[3] , iu4_instr[5] , + iu4_instr[22] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[30] , iu4_instr[31] , + iu4_fuse_val }) === 13'b0111000010010); +assign br_dep_pt[82] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[30] , iu4_fuse_val + }) === 14'b01111101101000); +assign br_dep_pt[83] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[3] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[24] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_instr[31] , iu4_fuse_val + }) === 14'b01110101110010); +assign br_dep_pt[84] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111110000000000); +assign br_dep_pt[85] = + (({ core64 , iu4_instr[0] , + iu4_instr[1] , iu4_instr[3] , + iu4_instr[5] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[30] , + iu4_instr[31] , iu4_fuse_val + }) === 14'b10111000010110); +assign br_dep_pt[86] = + (({ core64 , iu4_instr[0] , + iu4_instr[1] , iu4_instr[3] , + iu4_instr[5] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[30] , iu4_instr[31] , + iu4_fuse_val }) === 13'b1011111010110); +assign br_dep_pt[87] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[3] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_instr[31] , iu4_fuse_val + }) === 14'b01110001110010); +assign br_dep_pt[88] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[3] , iu4_instr[5] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_instr[31] , iu4_fuse_val + }) === 14'b01110000101110); +assign br_dep_pt[89] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[3] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_instr[31] , iu4_fuse_val + }) === 14'b01110000001110); +assign br_dep_pt[90] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[3] , iu4_instr[5] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_instr[31] , + iu4_fuse_val }) === 13'b0111110101110); +assign br_dep_pt[91] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[3] , iu4_instr[5] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_instr[31] , iu4_fuse_val + }) === 14'b01110010100010); +assign br_dep_pt[92] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[22] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[30] , iu4_fuse_val + }) === 14'b01111100001000); +assign br_dep_pt[93] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[3] , iu4_instr[5] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_instr[31] , iu4_fuse_val + }) === 14'b01110000101010); +assign br_dep_pt[94] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[6] , iu4_fuse_val + }) === 8'b01000000); +assign br_dep_pt[95] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[8] , iu4_fuse_val + }) === 8'b01000000); +assign br_dep_pt[96] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[3] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[30] , + iu4_instr[31] , iu4_fuse_val + }) === 14'b01110000010010); +assign br_dep_pt[97] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[3] , iu4_instr[5] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_instr[31] , iu4_fuse_val + }) === 14'b01110000100010); +assign br_dep_pt[98] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_fuse_val }) === 7'b0100000); +assign br_dep_pt[99] = + (({ core64 , iu4_instr[0] , + iu4_instr[1] , iu4_instr[2] , + iu4_instr[3] , iu4_instr[5] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[31] , iu4_fuse_val + }) === 10'b1011100010); +assign br_dep_pt[100] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[5] , iu4_instr[31] , + iu4_fuse_val }) === 7'b0100010); +assign br_dep_pt[101] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[4] , + iu4_instr[5] , iu4_fuse_val + }) === 6'b001000); +assign br_dep_pt[102] = + (({ core64 , iu4_instr[0] , + iu4_instr[1] , iu4_instr[2] , + iu4_instr[3] , iu4_instr[5] , + iu4_instr[27] , iu4_instr[31] , + iu4_fuse_val }) === 9'b101110010); +assign br_dep_pt[103] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_fuse_val }) === 7'b0011010); +assign br_dep_pt[104] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_fuse_val + }) === 6'b001010); +assign br_dep_pt[105] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[3] , iu4_instr[4] , + iu4_instr[31] , iu4_fuse_val + }) === 6'b011010); +assign br_dep_pt[106] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_fuse_val + }) === 6'b011100); +assign br_dep_pt[107] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[5] , iu4_instr[31] , + iu4_fuse_val }) === 7'b0101110); +assign updateslr = + (br_dep_pt[1] | br_dep_pt[4] + | br_dep_pt[9] | br_dep_pt[10] + | br_dep_pt[15] | br_dep_pt[17] + | br_dep_pt[21] | br_dep_pt[26] + | br_dep_pt[100]); +assign updatescr = + (br_dep_pt[2] | br_dep_pt[11] + | br_dep_pt[12] | br_dep_pt[13] + | br_dep_pt[22] | br_dep_pt[23] + | br_dep_pt[28] | br_dep_pt[29] + | br_dep_pt[30] | br_dep_pt[31] + | br_dep_pt[32] | br_dep_pt[33] + | br_dep_pt[34] | br_dep_pt[35] + | br_dep_pt[36] | br_dep_pt[40] + | br_dep_pt[43] | br_dep_pt[46] + | br_dep_pt[47] | br_dep_pt[48] + | br_dep_pt[49] | br_dep_pt[50] + | br_dep_pt[51] | br_dep_pt[53] + | br_dep_pt[54] | br_dep_pt[55] + | br_dep_pt[56] | br_dep_pt[58] + | br_dep_pt[61] | br_dep_pt[62] + | br_dep_pt[63] | br_dep_pt[65] + | br_dep_pt[66] | br_dep_pt[69] + | br_dep_pt[70] | br_dep_pt[71] + | br_dep_pt[72] | br_dep_pt[73] + | br_dep_pt[74] | br_dep_pt[75] + | br_dep_pt[76] | br_dep_pt[77] + | br_dep_pt[78] | br_dep_pt[79] + | br_dep_pt[81] | br_dep_pt[83] + | br_dep_pt[84] | br_dep_pt[85] + | br_dep_pt[86] | br_dep_pt[87] + | br_dep_pt[88] | br_dep_pt[89] + | br_dep_pt[90] | br_dep_pt[91] + | br_dep_pt[93] | br_dep_pt[96] + | br_dep_pt[97] | br_dep_pt[99] + | br_dep_pt[102] | br_dep_pt[103] + | br_dep_pt[104] | br_dep_pt[105] + | br_dep_pt[106] | br_dep_pt[107] + ); +assign updatesctr = + (br_dep_pt[3] | br_dep_pt[14] + | br_dep_pt[19] | br_dep_pt[25] + | br_dep_pt[95]); +assign updatesxer = + (br_dep_pt[6] | br_dep_pt[37] + | br_dep_pt[39] | br_dep_pt[41] + | br_dep_pt[44] | br_dep_pt[52] + | br_dep_pt[57] | br_dep_pt[59] + | br_dep_pt[60] | br_dep_pt[67] + | br_dep_pt[68] | br_dep_pt[75] + | br_dep_pt[82] | br_dep_pt[92] + | br_dep_pt[101] | br_dep_pt[103] + ); +assign useslr = + (br_dep_pt[5] | br_dep_pt[13] + | br_dep_pt[42]); +assign usescr = + (br_dep_pt[16] | br_dep_pt[18] + | br_dep_pt[20] | br_dep_pt[45] + | br_dep_pt[49] | br_dep_pt[51] + | br_dep_pt[53] | br_dep_pt[55] + | br_dep_pt[58] | br_dep_pt[62] + | br_dep_pt[63] | br_dep_pt[80] + | br_dep_pt[94]); +assign usesctr = + (br_dep_pt[7] | br_dep_pt[12] + | br_dep_pt[14] | br_dep_pt[19] + | br_dep_pt[24] | br_dep_pt[25] + | br_dep_pt[95]); +assign usesxer = + (br_dep_pt[2] | br_dep_pt[8] + | br_dep_pt[11] | br_dep_pt[12] + | br_dep_pt[13] | br_dep_pt[36] + | br_dep_pt[37] | br_dep_pt[39] + | br_dep_pt[41] | br_dep_pt[44] + | br_dep_pt[47] | br_dep_pt[52] + | br_dep_pt[57] | br_dep_pt[59] + | br_dep_pt[60] | br_dep_pt[61] + | br_dep_pt[64] | br_dep_pt[65] + | br_dep_pt[67] | br_dep_pt[68] + | br_dep_pt[70] | br_dep_pt[72] + | br_dep_pt[74] | br_dep_pt[75] + | br_dep_pt[76] | br_dep_pt[77] + | br_dep_pt[78] | br_dep_pt[79] + | br_dep_pt[82] | br_dep_pt[83] + | br_dep_pt[84] | br_dep_pt[85] + | br_dep_pt[86] | br_dep_pt[87] + | br_dep_pt[88] | br_dep_pt[89] + | br_dep_pt[90] | br_dep_pt[91] + | br_dep_pt[92] | br_dep_pt[93] + | br_dep_pt[96] | br_dep_pt[97] + | br_dep_pt[99] | br_dep_pt[101] + | br_dep_pt[102] | br_dep_pt[103] + | br_dep_pt[104] | br_dep_pt[105] + | br_dep_pt[106] | br_dep_pt[107] + ); +assign usestar = + (br_dep_pt[11] | br_dep_pt[38] + ); +assign usescr2 = + (br_dep_pt[49] | br_dep_pt[51] + | br_dep_pt[53] | br_dep_pt[55] + | br_dep_pt[58] | br_dep_pt[63] + ); +assign usescr_sel[0] = + (br_dep_pt[27] | br_dep_pt[80] + ); +assign usescr_sel[1] = + (br_dep_pt[24] | br_dep_pt[27] + | br_dep_pt[38] | br_dep_pt[42] + | br_dep_pt[49] | br_dep_pt[51] + | br_dep_pt[53] | br_dep_pt[55] + | br_dep_pt[58] | br_dep_pt[62] + | br_dep_pt[63] | br_dep_pt[98] + ); +assign updatescr_sel[0] = + (br_dep_pt[28] | br_dep_pt[29] + | br_dep_pt[30] | br_dep_pt[31] + | br_dep_pt[32] | br_dep_pt[33] + | br_dep_pt[34] | br_dep_pt[35] + | br_dep_pt[47] | br_dep_pt[49] + | br_dep_pt[51] | br_dep_pt[53] + | br_dep_pt[55] | br_dep_pt[58] + | br_dep_pt[62] | br_dep_pt[63] + | br_dep_pt[75] | br_dep_pt[84] + | br_dep_pt[104]); +assign updatescr_sel[1] = + (br_dep_pt[2] | br_dep_pt[11] + | br_dep_pt[12] | br_dep_pt[13] + | br_dep_pt[28] | br_dep_pt[29] + | br_dep_pt[30] | br_dep_pt[31] + | br_dep_pt[32] | br_dep_pt[33] + | br_dep_pt[34] | br_dep_pt[35] + | br_dep_pt[36]); + +assign instruction_decoder_pt[1] = + (({ iu4_fuse_val , iu4_fuse_cmp[0] , + iu4_fuse_cmp[1] , iu4_fuse_cmp[2] , + iu4_fuse_cmp[3] , iu4_fuse_cmp[4] , + iu4_fuse_cmp[5] , iu4_fuse_cmp[21] , + iu4_fuse_cmp[22] , iu4_fuse_cmp[23] , + iu4_fuse_cmp[24] , iu4_fuse_cmp[26] , + iu4_fuse_cmp[27] , iu4_fuse_cmp[28] , + iu4_fuse_cmp[29] , iu4_fuse_cmp[30] + }) === 16'b1011111000000000); +assign instruction_decoder_pt[2] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 17'b00000001000000000); +assign instruction_decoder_pt[3] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[10] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 18'b011111010010101100); +assign instruction_decoder_pt[4] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[9] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 18'b011111110010101100); +assign instruction_decoder_pt[5] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_instr[31] , + iu4_fuse_val }) === 17'b01111111011011010); +assign instruction_decoder_pt[6] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0100100000100000); +assign instruction_decoder_pt[7] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 17'b01001100100101100); +assign instruction_decoder_pt[8] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[11] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 18'b011111000100100000); +assign instruction_decoder_pt[9] = + (({ core64 , iu4_instr[0] , + iu4_instr[1] , iu4_instr[2] , + iu4_instr[21] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 14'b10111111010010); +assign instruction_decoder_pt[10] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0100110001001100); +assign instruction_decoder_pt[11] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 17'b01111111000100100); +assign instruction_decoder_pt[12] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_instr[31] , + iu4_fuse_val }) === 17'b01111101001011010); +assign instruction_decoder_pt[13] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[12] , iu4_instr[15] , + iu4_instr[21] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 17'b01111100010100110); +assign instruction_decoder_pt[14] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 17'b01111110000000000); +assign instruction_decoder_pt[15] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_fuse_val + }) === 16'b0100110000110010); +assign instruction_decoder_pt[16] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[11] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 18'b011111000000100110); +assign instruction_decoder_pt[17] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_instr[31] , iu4_fuse_val + }) === 16'b0111110000001110); +assign instruction_decoder_pt[18] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 17'b01111101011100110); +assign instruction_decoder_pt[19] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[8] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0100111000100000); +assign instruction_decoder_pt[20] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[3] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 14'b01111000101010); +assign instruction_decoder_pt[21] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0100110001100000); +assign instruction_decoder_pt[22] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111111110101100); +assign instruction_decoder_pt[23] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[5] , + iu4_instr[11] , iu4_instr[15] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111110010010000); +assign instruction_decoder_pt[24] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[5] , + iu4_instr[11] , iu4_instr[12] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111110010010000); +assign instruction_decoder_pt[25] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[5] , + iu4_instr[11] , iu4_instr[19] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111110010010000); +assign instruction_decoder_pt[26] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[5] , + iu4_instr[11] , iu4_instr[18] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111110010010000); +assign instruction_decoder_pt[27] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[5] , + iu4_instr[11] , iu4_instr[17] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111110010010000); +assign instruction_decoder_pt[28] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[5] , + iu4_instr[11] , iu4_instr[16] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111110010010000); +assign instruction_decoder_pt[29] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[5] , + iu4_instr[11] , iu4_instr[14] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111110010010000); +assign instruction_decoder_pt[30] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[5] , + iu4_instr[11] , iu4_instr[13] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111110010010000); +assign instruction_decoder_pt[31] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 17'b01111100101100110); +assign instruction_decoder_pt[32] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[5] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_instr[31] , iu4_fuse_val + }) === 14'b01110000100010); +assign instruction_decoder_pt[33] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111111000101010); +assign instruction_decoder_pt[34] = + (({ iu4_instr[0] , iu4_instr[2] , + iu4_instr[3] , iu4_instr[4] , + iu4_instr[5] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111100100100110); +assign instruction_decoder_pt[35] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_fuse_val + }) === 16'b0111110110010110); +assign instruction_decoder_pt[36] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 15'b010010101000010); +assign instruction_decoder_pt[37] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 17'b01111100001111100); +assign instruction_decoder_pt[38] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 14'b01111000010000); +assign instruction_decoder_pt[39] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[3] , iu4_instr[5] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_instr[31] , iu4_fuse_val + }) === 14'b01110000101010); +assign instruction_decoder_pt[40] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 17'b01001100110001100); +assign instruction_decoder_pt[41] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[21] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 15'b010010001000010); +assign instruction_decoder_pt[42] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 15'b010010100000010); +assign instruction_decoder_pt[43] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 15'b010010011000010); +assign instruction_decoder_pt[44] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[21] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 15'b010010110000010); +assign instruction_decoder_pt[45] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[20] , iu4_instr[21] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111111010100110); +assign instruction_decoder_pt[46] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[19] , iu4_instr[21] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111111010100110); +assign instruction_decoder_pt[47] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[18] , iu4_instr[21] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111111010100110); +assign instruction_decoder_pt[48] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[17] , iu4_instr[21] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111111010100110); +assign instruction_decoder_pt[49] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[16] , iu4_instr[21] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111111010100110); +assign instruction_decoder_pt[50] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[14] , iu4_instr[21] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111111010100110); +assign instruction_decoder_pt[51] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[13] , iu4_instr[21] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111111010100110); +assign instruction_decoder_pt[52] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[3] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 14'b01111000010100); +assign instruction_decoder_pt[53] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[11] , iu4_instr[21] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111111010100110); +assign instruction_decoder_pt[54] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 15'b010010010000010); +assign instruction_decoder_pt[55] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111111110101100); +assign instruction_decoder_pt[56] = + (({ core64 , iu4_instr[0] , + iu4_instr[1] , iu4_instr[2] , + iu4_instr[3] , iu4_instr[4] , + iu4_instr[5] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 18'b101111100111111000); +assign instruction_decoder_pt[57] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 17'b01111111110100100); +assign instruction_decoder_pt[58] = + (({ core64 , iu4_instr[0] , + iu4_instr[1] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b1011110000001000); +assign instruction_decoder_pt[59] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[3] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 13'b0111000011110); +assign instruction_decoder_pt[60] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 15'b011111010000110); +assign instruction_decoder_pt[61] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 14'b01110110000110); +assign instruction_decoder_pt[62] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 14'b01110110000110); +assign instruction_decoder_pt[63] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 17'b01111110001101100); +assign instruction_decoder_pt[64] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 17'b01111100110011100); +assign instruction_decoder_pt[65] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111110010100110); +assign instruction_decoder_pt[66] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111111111101100); +assign instruction_decoder_pt[67] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 17'b01111100111011100); +assign instruction_decoder_pt[68] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 14'b01110100000110); +assign instruction_decoder_pt[69] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[3] , iu4_instr[4] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 14'b01010000000000); +assign instruction_decoder_pt[70] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[24] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 15'b011111010000110); +assign instruction_decoder_pt[71] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_fuse_val + }) === 14'b01110100001110); +assign instruction_decoder_pt[72] = + (({ core64 , iu4_instr[0] , + iu4_instr[1] , iu4_instr[2] , + iu4_instr[3] , iu4_instr[4] , + iu4_instr[5] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b1011111111010010); +assign instruction_decoder_pt[73] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111111110100100); +assign instruction_decoder_pt[74] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111110001000110); +assign instruction_decoder_pt[75] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 13'b0111000000110); +assign instruction_decoder_pt[76] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111111010101100); +assign instruction_decoder_pt[77] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 15'b011111111101100); +assign instruction_decoder_pt[78] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[3] , iu4_instr[4] , + iu4_instr[5] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 15'b011110000000000); +assign instruction_decoder_pt[79] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 15'b011111110101100); +assign instruction_decoder_pt[80] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[5] , + iu4_instr[11] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 15'b011110000100110); +assign instruction_decoder_pt[81] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_instr[31] , + iu4_fuse_val }) === 17'b01111111001001010); +assign instruction_decoder_pt[82] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111110000110100); +assign instruction_decoder_pt[83] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 17'b01111101111001100); +assign instruction_decoder_pt[84] = + (({ core64 , iu4_instr[0] , + iu4_instr[1] , iu4_instr[2] , + iu4_instr[3] , iu4_instr[4] , + iu4_instr[5] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[30] , + iu4_fuse_val }) === 17'b10111110101110110); +assign instruction_decoder_pt[85] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_fuse_val + }) === 16'b0111110010010010); +assign instruction_decoder_pt[86] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[30] , + iu4_fuse_val }) === 15'b011111000010100); +assign instruction_decoder_pt[87] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 17'b01111100111111110); +assign instruction_decoder_pt[88] = + (({ core64 , iu4_instr[0] , + iu4_instr[1] , iu4_instr[2] , + iu4_instr[3] , iu4_instr[4] , + iu4_instr[5] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 17'b10111110111110100); +assign instruction_decoder_pt[89] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_instr[31] , iu4_fuse_val + }) === 18'b011111101011011010); +assign instruction_decoder_pt[90] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 17'b01111100010100110); +assign instruction_decoder_pt[91] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[30] , iu4_fuse_val + }) === 14'b01110010010000); +assign instruction_decoder_pt[92] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 15'b011111111001100); +assign instruction_decoder_pt[93] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_instr[31] , iu4_fuse_val + }) === 18'b011111001101010010); +assign instruction_decoder_pt[94] = + (({ core64 , iu4_instr[0] , + iu4_instr[1] , iu4_instr[2] , + iu4_instr[5] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_fuse_val }) === 15'b101111100111010); +assign instruction_decoder_pt[95] = + (({ core64 , iu4_instr[0] , + iu4_instr[1] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b1011111100011000); +assign instruction_decoder_pt[96] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 15'b011111111001100); +assign instruction_decoder_pt[97] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_instr[31] , iu4_fuse_val + }) === 18'b011111101101011010); +assign instruction_decoder_pt[98] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[3] , iu4_instr[4] , + iu4_instr[5] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111100010011100); +assign instruction_decoder_pt[99] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 15'b011111111010110); +assign instruction_decoder_pt[100] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 17'b01111100111001100); +assign instruction_decoder_pt[101] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111110010010100); +assign instruction_decoder_pt[102] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111110110100110); +assign instruction_decoder_pt[103] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111110000000110); +assign instruction_decoder_pt[104] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 14'b01110101100110); +assign instruction_decoder_pt[105] = + (({ core64 , iu4_instr[0] , + iu4_instr[1] , iu4_instr[2] , + iu4_instr[5] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 15'b101111110110100); +assign instruction_decoder_pt[106] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111110000101000); +assign instruction_decoder_pt[107] = + (({ core64 , iu4_instr[0] , + iu4_instr[1] , iu4_instr[2] , + iu4_instr[3] , iu4_instr[4] , + iu4_instr[5] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_fuse_val }) === 11'b10111100110); +assign instruction_decoder_pt[108] = + (({ core64 , iu4_instr[0] , + iu4_instr[1] , iu4_instr[2] , + iu4_instr[3] , iu4_instr[4] , + iu4_instr[5] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[30] , + iu4_fuse_val }) === 17'b10111110000110110); +assign instruction_decoder_pt[109] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111111111111110); +assign instruction_decoder_pt[110] = + (({ core64 , iu4_instr[0] , + iu4_instr[1] , iu4_instr[2] , + iu4_instr[3] , iu4_instr[4] , + iu4_instr[5] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_instr[31] , iu4_fuse_val + }) === 18'b101111100101011010); +assign instruction_decoder_pt[111] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 17'b01111100111101100); +assign instruction_decoder_pt[112] = + (({ core64 , iu4_instr[0] , + iu4_instr[1] , iu4_instr[2] , + iu4_instr[3] , iu4_instr[4] , + iu4_instr[5] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b1011111000010010); +assign instruction_decoder_pt[113] = + (({ core64 , iu4_instr[0] , + iu4_instr[1] , iu4_instr[2] , + iu4_instr[3] , iu4_instr[4] , + iu4_instr[5] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[30] , + iu4_fuse_val }) === 17'b10111110101010110); +assign instruction_decoder_pt[114] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 12'b011110100100); +assign instruction_decoder_pt[115] = + (({ core64 , iu4_instr[0] , + iu4_instr[1] , iu4_instr[2] , + iu4_instr[3] , iu4_instr[4] , + iu4_instr[5] , iu4_instr[21] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b1011111000110100); +assign instruction_decoder_pt[116] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 17'b01111111001100110); +assign instruction_decoder_pt[117] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111110100110100); +assign instruction_decoder_pt[118] = + (({ core64 , iu4_instr[0] , + iu4_instr[1] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b1011110000110110); +assign instruction_decoder_pt[119] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[3] , iu4_instr[4] , + iu4_instr[5] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 15'b011110000000000); +assign instruction_decoder_pt[120] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_instr[31] , iu4_fuse_val + }) === 18'b011111001001011010); +assign instruction_decoder_pt[121] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 15'b011111000010110); +assign instruction_decoder_pt[122] = + (({ core64 , iu4_instr[0] , + iu4_instr[1] , iu4_instr[2] , + iu4_instr[3] , iu4_instr[4] , + iu4_instr[5] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[30] , + iu4_fuse_val }) === 17'b10111111010010100); +assign instruction_decoder_pt[123] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[3] , iu4_instr[4] , + iu4_instr[5] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 14'b01111000010000); +assign instruction_decoder_pt[124] = + (({ core64 , iu4_instr[0] , + iu4_instr[1] , iu4_instr[2] , + iu4_instr[3] , iu4_instr[4] , + iu4_instr[5] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[30] , + iu4_fuse_val }) === 17'b10111111000010100); +assign instruction_decoder_pt[125] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 17'b01111100000100100); +assign instruction_decoder_pt[126] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111110000110100); +assign instruction_decoder_pt[127] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 17'b01111100010101100); +assign instruction_decoder_pt[128] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111111100100100); +assign instruction_decoder_pt[129] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111110100111110); +assign instruction_decoder_pt[130] = + (({ core64 , iu4_instr[0] , + iu4_instr[1] , iu4_instr[2] , + iu4_instr[5] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 15'b101110010110100); +assign instruction_decoder_pt[131] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111110001111110); +assign instruction_decoder_pt[132] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 14'b01111100110000); +assign instruction_decoder_pt[133] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 15'b011111001000110); +assign instruction_decoder_pt[134] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 17'b01111100001100110); +assign instruction_decoder_pt[135] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[3] , iu4_instr[4] , + iu4_instr[5] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 15'b011110001111000); +assign instruction_decoder_pt[136] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[3] , iu4_instr[4] , + iu4_instr[5] , iu4_instr[21] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 15'b011111000110000); +assign instruction_decoder_pt[137] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[3] , iu4_instr[4] , + iu4_instr[5] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 14'b01111000010100); +assign instruction_decoder_pt[138] = + (({ core64 , iu4_instr[0] , + iu4_instr[1] , iu4_instr[2] , + iu4_instr[3] , iu4_instr[4] , + iu4_instr[5] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[30] , + iu4_fuse_val }) === 17'b10111110010110110); +assign instruction_decoder_pt[139] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[5] , + iu4_instr[22] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 13'b0111011010000); +assign instruction_decoder_pt[140] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 15'b011111100101010); +assign instruction_decoder_pt[141] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111110011110100); +assign instruction_decoder_pt[142] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 15'b011100100110100); +assign instruction_decoder_pt[143] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111110010001100); +assign instruction_decoder_pt[144] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 14'b01111110110100); +assign instruction_decoder_pt[145] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[24] , + iu4_instr[25] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111110110001100); +assign instruction_decoder_pt[146] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[3] , iu4_instr[4] , + iu4_instr[5] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 15'b011110000011000); +assign instruction_decoder_pt[147] = + (({ iu4_fuse_val , iu4_fuse_cmp[0] , + iu4_fuse_cmp[1] , iu4_fuse_cmp[2] , + iu4_fuse_cmp[3] , iu4_fuse_cmp[4] + }) === 6'b100101); +assign instruction_decoder_pt[148] = + (({ core64 , iu4_instr[0] , + iu4_instr[1] , iu4_instr[2] , + iu4_instr[3] , iu4_instr[4] , + iu4_instr[5] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[28] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b1011111001001110); +assign instruction_decoder_pt[149] = + (({ core64 , iu4_instr[0] , + iu4_instr[1] , iu4_instr[2] , + iu4_instr[3] , iu4_instr[4] , + iu4_instr[5] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[28] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b1011111000001110); +assign instruction_decoder_pt[150] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[4] , + iu4_instr[5] , iu4_fuse_val + }) === 6'b101100); +assign instruction_decoder_pt[151] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[3] , iu4_instr[4] , + iu4_instr[5] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 14'b01111011111000); +assign instruction_decoder_pt[152] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[30] , iu4_fuse_val + }) === 8'b01000110); +assign instruction_decoder_pt[153] = + (({ core64 , iu4_instr[0] , + iu4_instr[1] , iu4_instr[2] , + iu4_instr[3] , iu4_instr[4] , + iu4_instr[5] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b1011111000101000); +assign instruction_decoder_pt[154] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111110001101000); +assign instruction_decoder_pt[155] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[3] , iu4_instr[4] , + iu4_instr[5] , iu4_instr[21] , + iu4_instr[22] , iu4_instr[24] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 14'b01111010111000); +assign instruction_decoder_pt[156] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111111100101100); +assign instruction_decoder_pt[157] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111111000101100); +assign instruction_decoder_pt[158] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_fuse_val }) === 7'b0101000); +assign instruction_decoder_pt[159] = + (({ core64 , iu4_instr[0] , + iu4_instr[1] , iu4_instr[2] , + iu4_instr[3] , iu4_instr[4] , + iu4_instr[5] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[30] , iu4_fuse_val + }) === 14'b10111111101010); +assign instruction_decoder_pt[160] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[23] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 15'b011111001101110); +assign instruction_decoder_pt[161] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111110101101110); +assign instruction_decoder_pt[162] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 16'b0111110011101110); +assign instruction_decoder_pt[163] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[5] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[30] , iu4_fuse_val + }) === 12'b011101101000); +assign instruction_decoder_pt[164] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_fuse_val }) === 15'b011111000010110); +assign instruction_decoder_pt[165] = + (({ core64 , iu4_instr[0] , + iu4_instr[1] , iu4_instr[2] , + iu4_instr[3] , iu4_instr[4] , + iu4_instr[5] , iu4_instr[30] , + iu4_instr[31] , iu4_fuse_val + }) === 10'b1111010010); +assign instruction_decoder_pt[166] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[3] , iu4_instr[4] , + iu4_instr[5] , iu4_instr[22] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[30] , + iu4_fuse_val }) === 13'b0111100001000); +assign instruction_decoder_pt[167] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[22] , iu4_instr[23] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 14'b01111111010110); +assign instruction_decoder_pt[168] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[23] , + iu4_instr[24] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 15'b011111010011110); +assign instruction_decoder_pt[169] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 15'b011111001011110); +assign instruction_decoder_pt[170] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[22] , + iu4_instr[23] , iu4_instr[25] , + iu4_instr[26] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 15'b011111000011110); +assign instruction_decoder_pt[171] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[21] , iu4_instr[23] , + iu4_instr[25] , iu4_instr[26] , + iu4_instr[27] , iu4_instr[28] , + iu4_instr[29] , iu4_instr[30] , + iu4_fuse_val }) === 15'b011111000101110); +assign instruction_decoder_pt[172] = + (({ iu4_instr[0] , iu4_instr[2] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[10] , iu4_fuse_val + }) === 6'b010010); +assign instruction_decoder_pt[173] = + (({ iu4_instr[0] , iu4_instr[2] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[7] , iu4_fuse_val + }) === 6'b010010); +assign instruction_decoder_pt[174] = + (({ iu4_instr[0] , iu4_instr[2] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[6] , iu4_fuse_val + }) === 6'b010010); +assign instruction_decoder_pt[175] = + (({ iu4_instr[0] , iu4_instr[2] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[20] , iu4_fuse_val + }) === 6'b010010); +assign instruction_decoder_pt[176] = + (({ iu4_instr[0] , iu4_instr[2] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[9] , iu4_fuse_val + }) === 6'b010010); +assign instruction_decoder_pt[177] = + (({ iu4_instr[0] , iu4_instr[2] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[8] , iu4_fuse_val + }) === 6'b010010); +assign instruction_decoder_pt[178] = + (({ iu4_instr[0] , iu4_instr[2] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[31] , iu4_fuse_val + }) === 6'b010010); +assign instruction_decoder_pt[179] = + (({ core64 , iu4_instr[0] , + iu4_instr[1] , iu4_instr[2] , + iu4_instr[3] , iu4_instr[4] , + iu4_instr[5] , iu4_instr[30] , + iu4_instr[31] , iu4_fuse_val + }) === 10'b1111110000); +assign instruction_decoder_pt[180] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_fuse_val }) === 7'b0001110); +assign instruction_decoder_pt[181] = + (({ core64 , iu4_instr[0] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[31] , iu4_fuse_val + }) === 8'b11101000); +assign instruction_decoder_pt[182] = + (({ core64 , iu4_instr[0] , + iu4_instr[1] , iu4_instr[2] , + iu4_instr[3] , iu4_instr[4] , + iu4_instr[5] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_fuse_val }) === 11'b10111101000); +assign instruction_decoder_pt[183] = + (({ core64 , iu4_instr[0] , + iu4_instr[1] , iu4_instr[3] , + iu4_instr[4] , iu4_fuse_val + }) === 6'b100010); +assign instruction_decoder_pt[184] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_instr[26] , iu4_instr[27] , + iu4_instr[28] , iu4_instr[29] , + iu4_instr[30] , iu4_fuse_val + }) === 12'b011111011110); +assign instruction_decoder_pt[185] = + (({ core64 , iu4_instr[0] , + iu4_instr[1] , iu4_instr[2] , + iu4_instr[3] , iu4_instr[4] , + iu4_instr[5] , iu4_instr[30] , + iu4_instr[31] , iu4_fuse_val + }) === 10'b1111110010); +assign instruction_decoder_pt[186] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[4] , + iu4_instr[15] , iu4_fuse_val + }) === 6'b011010); +assign instruction_decoder_pt[187] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[4] , + iu4_instr[12] , iu4_fuse_val + }) === 6'b011010); +assign instruction_decoder_pt[188] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[4] , + iu4_instr[19] , iu4_fuse_val + }) === 6'b011010); +assign instruction_decoder_pt[189] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[4] , + iu4_instr[18] , iu4_fuse_val + }) === 6'b011010); +assign instruction_decoder_pt[190] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[4] , + iu4_instr[17] , iu4_fuse_val + }) === 6'b011010); +assign instruction_decoder_pt[191] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[4] , + iu4_instr[16] , iu4_fuse_val + }) === 6'b011010); +assign instruction_decoder_pt[192] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[4] , + iu4_instr[14] , iu4_fuse_val + }) === 6'b011010); +assign instruction_decoder_pt[193] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[4] , + iu4_instr[13] , iu4_fuse_val + }) === 6'b011010); +assign instruction_decoder_pt[194] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[4] , + iu4_instr[11] , iu4_fuse_val + }) === 6'b011010); +assign instruction_decoder_pt[195] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_fuse_val + }) === 6'b011010); +assign instruction_decoder_pt[196] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[4] , + iu4_instr[25] , iu4_fuse_val + }) === 6'b011010); +assign instruction_decoder_pt[197] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[4] , + iu4_instr[21] , iu4_fuse_val + }) === 6'b011010); +assign instruction_decoder_pt[198] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[4] , + iu4_instr[22] , iu4_fuse_val + }) === 6'b011010); +assign instruction_decoder_pt[199] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[4] , + iu4_instr[24] , iu4_fuse_val + }) === 6'b011010); +assign instruction_decoder_pt[200] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[4] , + iu4_instr[27] , iu4_fuse_val + }) === 6'b011010); +assign instruction_decoder_pt[201] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[5] , iu4_fuse_val + }) === 6'b010000); +assign instruction_decoder_pt[202] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[4] , + iu4_instr[30] , iu4_fuse_val + }) === 6'b011010); +assign instruction_decoder_pt[203] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[4] , + iu4_instr[28] , iu4_fuse_val + }) === 6'b011010); +assign instruction_decoder_pt[204] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[4] , + iu4_instr[23] , iu4_fuse_val + }) === 6'b011010); +assign instruction_decoder_pt[205] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[4] , + iu4_instr[29] , iu4_fuse_val + }) === 6'b011010); +assign instruction_decoder_pt[206] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[4] , + iu4_instr[26] , iu4_fuse_val + }) === 6'b011010); +assign instruction_decoder_pt[207] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[5] , iu4_fuse_val + }) === 6'b100100); +assign instruction_decoder_pt[208] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[3] , iu4_instr[4] , + iu4_instr[5] , iu4_fuse_val + }) === 6'b101000); +assign instruction_decoder_pt[209] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[4] , + iu4_instr[5] , iu4_fuse_val + }) === 6'b011010); +assign instruction_decoder_pt[210] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[3] , iu4_instr[5] , + iu4_fuse_val }) === 5'b10000); +assign instruction_decoder_pt[211] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[4] , + iu4_instr[5] , iu4_fuse_val + }) === 6'b001000); +assign instruction_decoder_pt[212] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[4] , iu4_instr[5] , + iu4_fuse_val }) === 5'b00110); +assign instruction_decoder_pt[213] = + (({ core64 , iu4_instr[0] , + iu4_instr[1] , iu4_instr[2] , + iu4_instr[3] , iu4_instr[5] , + iu4_instr[27] , iu4_fuse_val + }) === 8'b10111000); +assign instruction_decoder_pt[214] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[3] , iu4_instr[5] , + iu4_fuse_val }) === 5'b10010); +assign instruction_decoder_pt[215] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_fuse_val + }) === 6'b101110); +assign instruction_decoder_pt[216] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[5] , iu4_fuse_val + }) === 6'b100110); +assign instruction_decoder_pt[217] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[3] , iu4_instr[4] , + iu4_instr[5] , iu4_fuse_val + }) === 6'b101010); +assign instruction_decoder_pt[218] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_fuse_val + }) === 6'b001110); +assign instruction_decoder_pt[219] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[4] , + iu4_fuse_val }) === 5'b01100); +assign instruction_decoder_pt[220] = + (({ iu4_instr[0] , iu4_instr[2] , + iu4_instr[3] , iu4_instr[4] , + iu4_fuse_val }) === 5'b01010); +assign instruction_decoder_pt[221] = + (({ iu4_instr[0] , iu4_instr[2] , + iu4_instr[3] , iu4_instr[4] , + iu4_fuse_val }) === 5'b01100); +assign instruction_decoder_pt[222] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[2] , iu4_instr[3] , + iu4_instr[4] , iu4_instr[5] , + iu4_fuse_val }) === 7'b0101110); +assign instruction_decoder_pt[223] = + (({ iu4_instr[0] , iu4_instr[1] , + iu4_instr[3] , iu4_instr[4] , + iu4_fuse_val }) === 5'b01100); +assign ta_vld = + (instruction_decoder_pt[16] | instruction_decoder_pt[20] + | instruction_decoder_pt[31] | instruction_decoder_pt[34] + | instruction_decoder_pt[56] | instruction_decoder_pt[59] + | instruction_decoder_pt[72] | instruction_decoder_pt[80] + | instruction_decoder_pt[84] | instruction_decoder_pt[88] + | instruction_decoder_pt[90] | instruction_decoder_pt[93] + | instruction_decoder_pt[94] | instruction_decoder_pt[95] + | instruction_decoder_pt[98] | instruction_decoder_pt[99] + | instruction_decoder_pt[101] | instruction_decoder_pt[103] + | instruction_decoder_pt[104] | instruction_decoder_pt[105] + | instruction_decoder_pt[106] | instruction_decoder_pt[108] + | instruction_decoder_pt[112] | instruction_decoder_pt[113] + | instruction_decoder_pt[115] | instruction_decoder_pt[117] + | instruction_decoder_pt[118] | instruction_decoder_pt[121] + | instruction_decoder_pt[123] | instruction_decoder_pt[124] + | instruction_decoder_pt[126] | instruction_decoder_pt[130] + | instruction_decoder_pt[132] | instruction_decoder_pt[135] + | instruction_decoder_pt[136] | instruction_decoder_pt[137] + | instruction_decoder_pt[138] | instruction_decoder_pt[139] + | instruction_decoder_pt[141] | instruction_decoder_pt[142] + | instruction_decoder_pt[144] | instruction_decoder_pt[146] + | instruction_decoder_pt[149] | instruction_decoder_pt[150] + | instruction_decoder_pt[151] | instruction_decoder_pt[153] + | instruction_decoder_pt[154] | instruction_decoder_pt[155] + | instruction_decoder_pt[157] | instruction_decoder_pt[159] + | instruction_decoder_pt[160] | instruction_decoder_pt[161] + | instruction_decoder_pt[162] | instruction_decoder_pt[163] + | instruction_decoder_pt[165] | instruction_decoder_pt[166] + | instruction_decoder_pt[167] | instruction_decoder_pt[170] + | instruction_decoder_pt[171] | instruction_decoder_pt[172] + | instruction_decoder_pt[173] | instruction_decoder_pt[174] + | instruction_decoder_pt[175] | instruction_decoder_pt[176] + | instruction_decoder_pt[177] | instruction_decoder_pt[178] + | instruction_decoder_pt[180] | instruction_decoder_pt[181] + | instruction_decoder_pt[182] | instruction_decoder_pt[184] + | instruction_decoder_pt[185] | instruction_decoder_pt[186] + | instruction_decoder_pt[187] | instruction_decoder_pt[188] + | instruction_decoder_pt[189] | instruction_decoder_pt[190] + | instruction_decoder_pt[191] | instruction_decoder_pt[192] + | instruction_decoder_pt[193] | instruction_decoder_pt[194] + | instruction_decoder_pt[195] | instruction_decoder_pt[196] + | instruction_decoder_pt[197] | instruction_decoder_pt[198] + | instruction_decoder_pt[199] | instruction_decoder_pt[200] + | instruction_decoder_pt[202] | instruction_decoder_pt[203] + | instruction_decoder_pt[204] | instruction_decoder_pt[205] + | instruction_decoder_pt[206] | instruction_decoder_pt[209] + | instruction_decoder_pt[210] | instruction_decoder_pt[211] + | instruction_decoder_pt[213] | instruction_decoder_pt[214] + | instruction_decoder_pt[216] | instruction_decoder_pt[217] + | instruction_decoder_pt[218] | instruction_decoder_pt[221] + | instruction_decoder_pt[222] | instruction_decoder_pt[223] + ); +assign ta_sel = + (instruction_decoder_pt[56] | instruction_decoder_pt[88] + | instruction_decoder_pt[94] | instruction_decoder_pt[95] + | instruction_decoder_pt[98] | instruction_decoder_pt[105] + | instruction_decoder_pt[115] | instruction_decoder_pt[117] + | instruction_decoder_pt[118] | instruction_decoder_pt[126] + | instruction_decoder_pt[130] | instruction_decoder_pt[132] + | instruction_decoder_pt[135] | instruction_decoder_pt[136] + | instruction_decoder_pt[138] | instruction_decoder_pt[141] + | instruction_decoder_pt[142] | instruction_decoder_pt[144] + | instruction_decoder_pt[146] | instruction_decoder_pt[151] + | instruction_decoder_pt[155] | instruction_decoder_pt[161] + | instruction_decoder_pt[162] | instruction_decoder_pt[182] + | instruction_decoder_pt[185] | instruction_decoder_pt[213] + | instruction_decoder_pt[216] | instruction_decoder_pt[217] + | instruction_decoder_pt[219] | instruction_decoder_pt[220] + | instruction_decoder_pt[222] | instruction_decoder_pt[223] + ); +assign s1_vld = + (instruction_decoder_pt[1] | instruction_decoder_pt[8] + | instruction_decoder_pt[23] | instruction_decoder_pt[24] + | instruction_decoder_pt[25] | instruction_decoder_pt[26] + | instruction_decoder_pt[27] | instruction_decoder_pt[28] + | instruction_decoder_pt[29] | instruction_decoder_pt[30] + | instruction_decoder_pt[55] | instruction_decoder_pt[56] + | instruction_decoder_pt[58] | instruction_decoder_pt[61] + | instruction_decoder_pt[62] | instruction_decoder_pt[66] + | instruction_decoder_pt[68] | instruction_decoder_pt[72] + | instruction_decoder_pt[75] | instruction_decoder_pt[78] + | instruction_decoder_pt[79] | instruction_decoder_pt[81] + | instruction_decoder_pt[83] | instruction_decoder_pt[84] + | instruction_decoder_pt[85] | instruction_decoder_pt[86] + | instruction_decoder_pt[87] | instruction_decoder_pt[88] + | instruction_decoder_pt[89] | instruction_decoder_pt[93] + | instruction_decoder_pt[94] | instruction_decoder_pt[95] + | instruction_decoder_pt[97] | instruction_decoder_pt[98] + | instruction_decoder_pt[99] | instruction_decoder_pt[100] + | instruction_decoder_pt[101] | instruction_decoder_pt[102] + | instruction_decoder_pt[105] | instruction_decoder_pt[108] + | instruction_decoder_pt[109] | instruction_decoder_pt[110] + | instruction_decoder_pt[111] | instruction_decoder_pt[112] + | instruction_decoder_pt[113] | instruction_decoder_pt[115] + | instruction_decoder_pt[116] | instruction_decoder_pt[117] + | instruction_decoder_pt[118] | instruction_decoder_pt[119] + | instruction_decoder_pt[120] | instruction_decoder_pt[121] + | instruction_decoder_pt[122] | instruction_decoder_pt[123] + | instruction_decoder_pt[124] | instruction_decoder_pt[125] + | instruction_decoder_pt[126] | instruction_decoder_pt[127] + | instruction_decoder_pt[128] | instruction_decoder_pt[129] + | instruction_decoder_pt[130] | instruction_decoder_pt[131] + | instruction_decoder_pt[132] | instruction_decoder_pt[134] + | instruction_decoder_pt[135] | instruction_decoder_pt[136] + | instruction_decoder_pt[137] | instruction_decoder_pt[138] + | instruction_decoder_pt[139] | instruction_decoder_pt[140] + | instruction_decoder_pt[141] | instruction_decoder_pt[142] + | instruction_decoder_pt[143] | instruction_decoder_pt[144] + | instruction_decoder_pt[145] | instruction_decoder_pt[146] + | instruction_decoder_pt[147] | instruction_decoder_pt[148] + | instruction_decoder_pt[149] | instruction_decoder_pt[151] + | instruction_decoder_pt[153] | instruction_decoder_pt[154] + | instruction_decoder_pt[155] | instruction_decoder_pt[156] + | instruction_decoder_pt[157] | instruction_decoder_pt[159] + | instruction_decoder_pt[160] | instruction_decoder_pt[161] + | instruction_decoder_pt[162] | instruction_decoder_pt[163] + | instruction_decoder_pt[164] | instruction_decoder_pt[165] + | instruction_decoder_pt[166] | instruction_decoder_pt[167] + | instruction_decoder_pt[168] | instruction_decoder_pt[169] + | instruction_decoder_pt[170] | instruction_decoder_pt[171] + | instruction_decoder_pt[172] | instruction_decoder_pt[173] + | instruction_decoder_pt[174] | instruction_decoder_pt[175] + | instruction_decoder_pt[176] | instruction_decoder_pt[177] + | instruction_decoder_pt[178] | instruction_decoder_pt[179] + | instruction_decoder_pt[181] | instruction_decoder_pt[182] + | instruction_decoder_pt[183] | instruction_decoder_pt[184] + | instruction_decoder_pt[185] | instruction_decoder_pt[186] + | instruction_decoder_pt[187] | instruction_decoder_pt[188] + | instruction_decoder_pt[189] | instruction_decoder_pt[190] + | instruction_decoder_pt[191] | instruction_decoder_pt[192] + | instruction_decoder_pt[193] | instruction_decoder_pt[194] + | instruction_decoder_pt[196] | instruction_decoder_pt[197] + | instruction_decoder_pt[198] | instruction_decoder_pt[199] + | instruction_decoder_pt[200] | instruction_decoder_pt[202] + | instruction_decoder_pt[203] | instruction_decoder_pt[204] + | instruction_decoder_pt[205] | instruction_decoder_pt[206] + | instruction_decoder_pt[207] | instruction_decoder_pt[208] + | instruction_decoder_pt[209] | instruction_decoder_pt[210] + | instruction_decoder_pt[211] | instruction_decoder_pt[212] + | instruction_decoder_pt[213] | instruction_decoder_pt[214] + | instruction_decoder_pt[215] | instruction_decoder_pt[216] + | instruction_decoder_pt[217] | instruction_decoder_pt[218] + | instruction_decoder_pt[220] | instruction_decoder_pt[221] + | instruction_decoder_pt[222] | instruction_decoder_pt[223] + ); +assign s1_sel = + (instruction_decoder_pt[56] | instruction_decoder_pt[61] + | instruction_decoder_pt[62] | instruction_decoder_pt[68] + | instruction_decoder_pt[88] | instruction_decoder_pt[91] + | instruction_decoder_pt[94] | instruction_decoder_pt[95] + | instruction_decoder_pt[98] | instruction_decoder_pt[102] + | instruction_decoder_pt[105] | instruction_decoder_pt[115] + | instruction_decoder_pt[117] | instruction_decoder_pt[118] + | instruction_decoder_pt[126] | instruction_decoder_pt[130] + | instruction_decoder_pt[132] | instruction_decoder_pt[135] + | instruction_decoder_pt[136] | instruction_decoder_pt[141] + | instruction_decoder_pt[142] | instruction_decoder_pt[144] + | instruction_decoder_pt[146] | instruction_decoder_pt[151] + | instruction_decoder_pt[155] | instruction_decoder_pt[182] + | instruction_decoder_pt[195] | instruction_decoder_pt[213] + | instruction_decoder_pt[219] | instruction_decoder_pt[222] + | instruction_decoder_pt[223]); +assign s2_vld = + (instruction_decoder_pt[1] | instruction_decoder_pt[31] + | instruction_decoder_pt[33] | instruction_decoder_pt[55] + | instruction_decoder_pt[56] | instruction_decoder_pt[58] + | instruction_decoder_pt[64] | instruction_decoder_pt[65] + | instruction_decoder_pt[66] | instruction_decoder_pt[67] + | instruction_decoder_pt[70] | instruction_decoder_pt[72] + | instruction_decoder_pt[78] | instruction_decoder_pt[79] + | instruction_decoder_pt[81] | instruction_decoder_pt[83] + | instruction_decoder_pt[84] | instruction_decoder_pt[86] + | instruction_decoder_pt[87] | instruction_decoder_pt[89] + | instruction_decoder_pt[93] | instruction_decoder_pt[95] + | instruction_decoder_pt[97] | instruction_decoder_pt[98] + | instruction_decoder_pt[99] | instruction_decoder_pt[100] + | instruction_decoder_pt[101] | instruction_decoder_pt[107] + | instruction_decoder_pt[108] | instruction_decoder_pt[109] + | instruction_decoder_pt[110] | instruction_decoder_pt[111] + | instruction_decoder_pt[112] | instruction_decoder_pt[113] + | instruction_decoder_pt[116] | instruction_decoder_pt[118] + | instruction_decoder_pt[119] | instruction_decoder_pt[120] + | instruction_decoder_pt[121] | instruction_decoder_pt[122] + | instruction_decoder_pt[123] | instruction_decoder_pt[124] + | instruction_decoder_pt[125] | instruction_decoder_pt[127] + | instruction_decoder_pt[128] | instruction_decoder_pt[129] + | instruction_decoder_pt[131] | instruction_decoder_pt[134] + | instruction_decoder_pt[135] | instruction_decoder_pt[136] + | instruction_decoder_pt[137] | instruction_decoder_pt[138] + | instruction_decoder_pt[143] | instruction_decoder_pt[145] + | instruction_decoder_pt[146] | instruction_decoder_pt[148] + | instruction_decoder_pt[149] | instruction_decoder_pt[151] + | instruction_decoder_pt[153] | instruction_decoder_pt[154] + | instruction_decoder_pt[155] | instruction_decoder_pt[156] + | instruction_decoder_pt[157] | instruction_decoder_pt[158] + | instruction_decoder_pt[159] | instruction_decoder_pt[160] + | instruction_decoder_pt[161] | instruction_decoder_pt[162] + | instruction_decoder_pt[164] | instruction_decoder_pt[166] + | instruction_decoder_pt[167] | instruction_decoder_pt[168] + | instruction_decoder_pt[169] | instruction_decoder_pt[170] + | instruction_decoder_pt[171] | instruction_decoder_pt[182] + | instruction_decoder_pt[184] | instruction_decoder_pt[222] + ); +assign s2_sel = + (instruction_decoder_pt[31] | instruction_decoder_pt[70] + | instruction_decoder_pt[102] | instruction_decoder_pt[213] + | instruction_decoder_pt[223]); +assign s3_vld = + (instruction_decoder_pt[22] | instruction_decoder_pt[35] + | instruction_decoder_pt[74] | instruction_decoder_pt[89] + | instruction_decoder_pt[97] | instruction_decoder_pt[110] + | instruction_decoder_pt[116] | instruction_decoder_pt[120] + | instruction_decoder_pt[122] | instruction_decoder_pt[138] + | instruction_decoder_pt[148] | instruction_decoder_pt[156] + | instruction_decoder_pt[161] | instruction_decoder_pt[162] + | instruction_decoder_pt[168] | instruction_decoder_pt[169] + | instruction_decoder_pt[179] | instruction_decoder_pt[185] + | instruction_decoder_pt[207] | instruction_decoder_pt[208] + | instruction_decoder_pt[216] | instruction_decoder_pt[217] + ); +assign issue_lq = + (instruction_decoder_pt[63] | instruction_decoder_pt[64] + | instruction_decoder_pt[74] | instruction_decoder_pt[76] + | instruction_decoder_pt[77] | instruction_decoder_pt[82] + | instruction_decoder_pt[83] | instruction_decoder_pt[84] + | instruction_decoder_pt[87] | instruction_decoder_pt[89] + | instruction_decoder_pt[92] | instruction_decoder_pt[93] + | instruction_decoder_pt[96] | instruction_decoder_pt[97] + | instruction_decoder_pt[100] | instruction_decoder_pt[103] + | instruction_decoder_pt[106] | instruction_decoder_pt[108] + | instruction_decoder_pt[109] | instruction_decoder_pt[110] + | instruction_decoder_pt[111] | instruction_decoder_pt[113] + | instruction_decoder_pt[120] | instruction_decoder_pt[122] + | instruction_decoder_pt[124] | instruction_decoder_pt[127] + | instruction_decoder_pt[129] | instruction_decoder_pt[131] + | instruction_decoder_pt[138] | instruction_decoder_pt[140] + | instruction_decoder_pt[143] | instruction_decoder_pt[145] + | instruction_decoder_pt[148] | instruction_decoder_pt[149] + | instruction_decoder_pt[153] | instruction_decoder_pt[154] + | instruction_decoder_pt[156] | instruction_decoder_pt[157] + | instruction_decoder_pt[160] | instruction_decoder_pt[161] + | instruction_decoder_pt[162] | instruction_decoder_pt[164] + | instruction_decoder_pt[165] | instruction_decoder_pt[168] + | instruction_decoder_pt[169] | instruction_decoder_pt[170] + | instruction_decoder_pt[171] | instruction_decoder_pt[179] + | instruction_decoder_pt[181] | instruction_decoder_pt[185] + | instruction_decoder_pt[207] | instruction_decoder_pt[208] + | instruction_decoder_pt[210] | instruction_decoder_pt[214] + | instruction_decoder_pt[215] | instruction_decoder_pt[216] + | instruction_decoder_pt[217]); +assign issue_sq = + (instruction_decoder_pt[33] | instruction_decoder_pt[55] + | instruction_decoder_pt[63] | instruction_decoder_pt[64] + | instruction_decoder_pt[76] | instruction_decoder_pt[77] + | instruction_decoder_pt[82] | instruction_decoder_pt[89] + | instruction_decoder_pt[92] | instruction_decoder_pt[97] + | instruction_decoder_pt[100] | instruction_decoder_pt[109] + | instruction_decoder_pt[110] | instruction_decoder_pt[120] + | instruction_decoder_pt[122] | instruction_decoder_pt[127] + | instruction_decoder_pt[131] | instruction_decoder_pt[138] + | instruction_decoder_pt[145] | instruction_decoder_pt[148] + | instruction_decoder_pt[156] | instruction_decoder_pt[161] + | instruction_decoder_pt[162] | instruction_decoder_pt[168] + | instruction_decoder_pt[169] | instruction_decoder_pt[179] + | instruction_decoder_pt[185] | instruction_decoder_pt[207] + | instruction_decoder_pt[208] | instruction_decoder_pt[216] + | instruction_decoder_pt[217]); +assign issue_fx0 = + (instruction_decoder_pt[1] | instruction_decoder_pt[2] + | instruction_decoder_pt[19] | instruction_decoder_pt[21] + | instruction_decoder_pt[23] | instruction_decoder_pt[24] + | instruction_decoder_pt[25] | instruction_decoder_pt[26] + | instruction_decoder_pt[27] | instruction_decoder_pt[28] + | instruction_decoder_pt[29] | instruction_decoder_pt[30] + | instruction_decoder_pt[36] | instruction_decoder_pt[37] + | instruction_decoder_pt[40] | instruction_decoder_pt[41] + | instruction_decoder_pt[42] | instruction_decoder_pt[43] + | instruction_decoder_pt[44] | instruction_decoder_pt[54] + | instruction_decoder_pt[56] | instruction_decoder_pt[57] + | instruction_decoder_pt[58] | instruction_decoder_pt[67] + | instruction_decoder_pt[69] | instruction_decoder_pt[71] + | instruction_decoder_pt[72] | instruction_decoder_pt[73] + | instruction_decoder_pt[78] | instruction_decoder_pt[80] + | instruction_decoder_pt[81] | instruction_decoder_pt[85] + | instruction_decoder_pt[88] | instruction_decoder_pt[90] + | instruction_decoder_pt[94] | instruction_decoder_pt[95] + | instruction_decoder_pt[98] | instruction_decoder_pt[99] + | instruction_decoder_pt[101] | instruction_decoder_pt[102] + | instruction_decoder_pt[104] | instruction_decoder_pt[105] + | instruction_decoder_pt[112] | instruction_decoder_pt[115] + | instruction_decoder_pt[116] | instruction_decoder_pt[117] + | instruction_decoder_pt[118] | instruction_decoder_pt[119] + | instruction_decoder_pt[121] | instruction_decoder_pt[123] + | instruction_decoder_pt[125] | instruction_decoder_pt[126] + | instruction_decoder_pt[128] | instruction_decoder_pt[130] + | instruction_decoder_pt[132] | instruction_decoder_pt[133] + | instruction_decoder_pt[134] | instruction_decoder_pt[135] + | instruction_decoder_pt[136] | instruction_decoder_pt[137] + | instruction_decoder_pt[139] | instruction_decoder_pt[141] + | instruction_decoder_pt[142] | instruction_decoder_pt[144] + | instruction_decoder_pt[146] | instruction_decoder_pt[147] + | instruction_decoder_pt[151] | instruction_decoder_pt[155] + | instruction_decoder_pt[159] | instruction_decoder_pt[163] + | instruction_decoder_pt[166] | instruction_decoder_pt[167] + | instruction_decoder_pt[182] | instruction_decoder_pt[183] + | instruction_decoder_pt[184] | instruction_decoder_pt[201] + | instruction_decoder_pt[211] | instruction_decoder_pt[212] + | instruction_decoder_pt[213] | instruction_decoder_pt[218] + | instruction_decoder_pt[219] | instruction_decoder_pt[220] + | instruction_decoder_pt[221] | instruction_decoder_pt[222] + | instruction_decoder_pt[223]); +assign issue_fx1 = + (instruction_decoder_pt[22] | instruction_decoder_pt[33] + | instruction_decoder_pt[35] | instruction_decoder_pt[89] + | instruction_decoder_pt[94] | instruction_decoder_pt[95] + | instruction_decoder_pt[97] | instruction_decoder_pt[105] + | instruction_decoder_pt[110] | instruction_decoder_pt[118] + | instruction_decoder_pt[119] | instruction_decoder_pt[120] + | instruction_decoder_pt[122] | instruction_decoder_pt[123] + | instruction_decoder_pt[130] | instruction_decoder_pt[132] + | instruction_decoder_pt[135] | instruction_decoder_pt[136] + | instruction_decoder_pt[137] | instruction_decoder_pt[138] + | instruction_decoder_pt[139] | instruction_decoder_pt[142] + | instruction_decoder_pt[144] | instruction_decoder_pt[146] + | instruction_decoder_pt[148] | instruction_decoder_pt[151] + | instruction_decoder_pt[155] | instruction_decoder_pt[156] + | instruction_decoder_pt[161] | instruction_decoder_pt[162] + | instruction_decoder_pt[163] | instruction_decoder_pt[166] + | instruction_decoder_pt[168] | instruction_decoder_pt[169] + | instruction_decoder_pt[179] | instruction_decoder_pt[182] + | instruction_decoder_pt[184] | instruction_decoder_pt[185] + | instruction_decoder_pt[207] | instruction_decoder_pt[208] + | instruction_decoder_pt[211] | instruction_decoder_pt[213] + | instruction_decoder_pt[216] | instruction_decoder_pt[217] + | instruction_decoder_pt[218] | instruction_decoder_pt[219] + | instruction_decoder_pt[220] | instruction_decoder_pt[221] + | instruction_decoder_pt[222] | instruction_decoder_pt[223] + ); +assign latency[0] = + 1'b0; +assign latency[1] = + (instruction_decoder_pt[2] | instruction_decoder_pt[13] + | instruction_decoder_pt[17] | instruction_decoder_pt[18] + | instruction_decoder_pt[40] | instruction_decoder_pt[45] + | instruction_decoder_pt[46] | instruction_decoder_pt[47] + | instruction_decoder_pt[48] | instruction_decoder_pt[49] + | instruction_decoder_pt[50] | instruction_decoder_pt[51] + | instruction_decoder_pt[53] | instruction_decoder_pt[57] + | instruction_decoder_pt[65] | instruction_decoder_pt[67] + | instruction_decoder_pt[72] | instruction_decoder_pt[73] + | instruction_decoder_pt[81] | instruction_decoder_pt[85] + | instruction_decoder_pt[88] | instruction_decoder_pt[89] + | instruction_decoder_pt[90] | instruction_decoder_pt[93] + | instruction_decoder_pt[97] | instruction_decoder_pt[99] + | instruction_decoder_pt[103] | instruction_decoder_pt[106] + | instruction_decoder_pt[110] | instruction_decoder_pt[112] + | instruction_decoder_pt[116] | instruction_decoder_pt[120] + | instruction_decoder_pt[121] | instruction_decoder_pt[125] + | instruction_decoder_pt[128] | instruction_decoder_pt[133] + | instruction_decoder_pt[134] | instruction_decoder_pt[141] + | instruction_decoder_pt[153] | instruction_decoder_pt[154] + | instruction_decoder_pt[159] | instruction_decoder_pt[167] + | instruction_decoder_pt[180]); +assign latency[2] = + (instruction_decoder_pt[1] | instruction_decoder_pt[2] + | instruction_decoder_pt[6] | instruction_decoder_pt[13] + | instruction_decoder_pt[18] | instruction_decoder_pt[19] + | instruction_decoder_pt[21] | instruction_decoder_pt[36] + | instruction_decoder_pt[40] | instruction_decoder_pt[41] + | instruction_decoder_pt[42] | instruction_decoder_pt[43] + | instruction_decoder_pt[44] | instruction_decoder_pt[45] + | instruction_decoder_pt[46] | instruction_decoder_pt[47] + | instruction_decoder_pt[48] | instruction_decoder_pt[49] + | instruction_decoder_pt[50] | instruction_decoder_pt[51] + | instruction_decoder_pt[53] | instruction_decoder_pt[54] + | instruction_decoder_pt[56] | instruction_decoder_pt[57] + | instruction_decoder_pt[63] | instruction_decoder_pt[64] + | instruction_decoder_pt[65] | instruction_decoder_pt[67] + | instruction_decoder_pt[72] | instruction_decoder_pt[73] + | instruction_decoder_pt[74] | instruction_decoder_pt[76] + | instruction_decoder_pt[77] | instruction_decoder_pt[81] + | instruction_decoder_pt[82] | instruction_decoder_pt[83] + | instruction_decoder_pt[84] | instruction_decoder_pt[85] + | instruction_decoder_pt[87] | instruction_decoder_pt[88] + | instruction_decoder_pt[89] | instruction_decoder_pt[90] + | instruction_decoder_pt[92] | instruction_decoder_pt[93] + | instruction_decoder_pt[96] | instruction_decoder_pt[97] + | instruction_decoder_pt[100] | instruction_decoder_pt[101] + | instruction_decoder_pt[103] | instruction_decoder_pt[106] + | instruction_decoder_pt[108] | instruction_decoder_pt[109] + | instruction_decoder_pt[110] | instruction_decoder_pt[111] + | instruction_decoder_pt[112] | instruction_decoder_pt[113] + | instruction_decoder_pt[115] | instruction_decoder_pt[116] + | instruction_decoder_pt[117] | instruction_decoder_pt[120] + | instruction_decoder_pt[122] | instruction_decoder_pt[124] + | instruction_decoder_pt[125] | instruction_decoder_pt[126] + | instruction_decoder_pt[127] | instruction_decoder_pt[128] + | instruction_decoder_pt[129] | instruction_decoder_pt[131] + | instruction_decoder_pt[133] | instruction_decoder_pt[134] + | instruction_decoder_pt[138] | instruction_decoder_pt[140] + | instruction_decoder_pt[141] | instruction_decoder_pt[143] + | instruction_decoder_pt[145] | instruction_decoder_pt[147] + | instruction_decoder_pt[148] | instruction_decoder_pt[149] + | instruction_decoder_pt[153] | instruction_decoder_pt[154] + | instruction_decoder_pt[156] | instruction_decoder_pt[157] + | instruction_decoder_pt[159] | instruction_decoder_pt[160] + | instruction_decoder_pt[161] | instruction_decoder_pt[162] + | instruction_decoder_pt[164] | instruction_decoder_pt[165] + | instruction_decoder_pt[167] | instruction_decoder_pt[168] + | instruction_decoder_pt[169] | instruction_decoder_pt[170] + | instruction_decoder_pt[171] | instruction_decoder_pt[179] + | instruction_decoder_pt[181] | instruction_decoder_pt[185] + | instruction_decoder_pt[201] | instruction_decoder_pt[207] + | instruction_decoder_pt[208] | instruction_decoder_pt[210] + | instruction_decoder_pt[214] | instruction_decoder_pt[215] + | instruction_decoder_pt[216] | instruction_decoder_pt[217] + ); +assign latency[3] = + (instruction_decoder_pt[1] | instruction_decoder_pt[9] + | instruction_decoder_pt[19] | instruction_decoder_pt[21] + | instruction_decoder_pt[32] | instruction_decoder_pt[36] + | instruction_decoder_pt[38] | instruction_decoder_pt[39] + | instruction_decoder_pt[40] | instruction_decoder_pt[41] + | instruction_decoder_pt[42] | instruction_decoder_pt[43] + | instruction_decoder_pt[44] | instruction_decoder_pt[52] + | instruction_decoder_pt[54] | instruction_decoder_pt[63] + | instruction_decoder_pt[64] | instruction_decoder_pt[67] + | instruction_decoder_pt[69] | instruction_decoder_pt[71] + | instruction_decoder_pt[74] | instruction_decoder_pt[76] + | instruction_decoder_pt[77] | instruction_decoder_pt[80] + | instruction_decoder_pt[82] | instruction_decoder_pt[83] + | instruction_decoder_pt[84] | instruction_decoder_pt[87] + | instruction_decoder_pt[88] | instruction_decoder_pt[89] + | instruction_decoder_pt[90] | instruction_decoder_pt[91] + | instruction_decoder_pt[92] | instruction_decoder_pt[93] + | instruction_decoder_pt[94] | instruction_decoder_pt[95] + | instruction_decoder_pt[96] | instruction_decoder_pt[97] + | instruction_decoder_pt[98] | instruction_decoder_pt[100] + | instruction_decoder_pt[102] | instruction_decoder_pt[103] + | instruction_decoder_pt[104] | instruction_decoder_pt[105] + | instruction_decoder_pt[106] | instruction_decoder_pt[108] + | instruction_decoder_pt[109] | instruction_decoder_pt[110] + | instruction_decoder_pt[111] | instruction_decoder_pt[112] + | instruction_decoder_pt[113] | instruction_decoder_pt[116] + | instruction_decoder_pt[118] | instruction_decoder_pt[119] + | instruction_decoder_pt[120] | instruction_decoder_pt[122] + | instruction_decoder_pt[124] | instruction_decoder_pt[127] + | instruction_decoder_pt[129] | instruction_decoder_pt[130] + | instruction_decoder_pt[131] | instruction_decoder_pt[132] + | instruction_decoder_pt[133] | instruction_decoder_pt[134] + | instruction_decoder_pt[135] | instruction_decoder_pt[136] + | instruction_decoder_pt[138] | instruction_decoder_pt[139] + | instruction_decoder_pt[140] | instruction_decoder_pt[141] + | instruction_decoder_pt[142] | instruction_decoder_pt[143] + | instruction_decoder_pt[144] | instruction_decoder_pt[145] + | instruction_decoder_pt[146] | instruction_decoder_pt[147] + | instruction_decoder_pt[148] | instruction_decoder_pt[149] + | instruction_decoder_pt[151] | instruction_decoder_pt[153] + | instruction_decoder_pt[154] | instruction_decoder_pt[155] + | instruction_decoder_pt[156] | instruction_decoder_pt[157] + | instruction_decoder_pt[159] | instruction_decoder_pt[160] + | instruction_decoder_pt[161] | instruction_decoder_pt[162] + | instruction_decoder_pt[163] | instruction_decoder_pt[164] + | instruction_decoder_pt[165] | instruction_decoder_pt[166] + | instruction_decoder_pt[167] | instruction_decoder_pt[168] + | instruction_decoder_pt[169] | instruction_decoder_pt[170] + | instruction_decoder_pt[171] | instruction_decoder_pt[179] + | instruction_decoder_pt[180] | instruction_decoder_pt[181] + | instruction_decoder_pt[182] | instruction_decoder_pt[184] + | instruction_decoder_pt[185] | instruction_decoder_pt[201] + | instruction_decoder_pt[207] | instruction_decoder_pt[208] + | instruction_decoder_pt[210] | instruction_decoder_pt[211] + | instruction_decoder_pt[213] | instruction_decoder_pt[214] + | instruction_decoder_pt[215] | instruction_decoder_pt[216] + | instruction_decoder_pt[217] | instruction_decoder_pt[219] + | instruction_decoder_pt[220] | instruction_decoder_pt[221] + | instruction_decoder_pt[222] | instruction_decoder_pt[223] + ); +assign ordered = + (instruction_decoder_pt[10] | instruction_decoder_pt[13] + | instruction_decoder_pt[15] | instruction_decoder_pt[18] + | instruction_decoder_pt[37] | instruction_decoder_pt[40] + | instruction_decoder_pt[45] | instruction_decoder_pt[46] + | instruction_decoder_pt[47] | instruction_decoder_pt[48] + | instruction_decoder_pt[49] | instruction_decoder_pt[50] + | instruction_decoder_pt[51] | instruction_decoder_pt[53] + | instruction_decoder_pt[57] | instruction_decoder_pt[60] + | instruction_decoder_pt[65] | instruction_decoder_pt[67] + | instruction_decoder_pt[70] | instruction_decoder_pt[73] + | instruction_decoder_pt[81] | instruction_decoder_pt[85] + | instruction_decoder_pt[90] | instruction_decoder_pt[116] + | instruction_decoder_pt[125] | instruction_decoder_pt[128] + | instruction_decoder_pt[133] | instruction_decoder_pt[134] + | instruction_decoder_pt[152] | instruction_decoder_pt[159] + | instruction_decoder_pt[167]); +assign spec = + (instruction_decoder_pt[77] | instruction_decoder_pt[79] + | instruction_decoder_pt[83] | instruction_decoder_pt[84] + | instruction_decoder_pt[86] | instruction_decoder_pt[87] + | instruction_decoder_pt[89] | instruction_decoder_pt[93] + | instruction_decoder_pt[96] | instruction_decoder_pt[97] + | instruction_decoder_pt[100] | instruction_decoder_pt[108] + | instruction_decoder_pt[109] | instruction_decoder_pt[110] + | instruction_decoder_pt[111] | instruction_decoder_pt[113] + | instruction_decoder_pt[120] | instruction_decoder_pt[122] + | instruction_decoder_pt[124] | instruction_decoder_pt[127] + | instruction_decoder_pt[129] | instruction_decoder_pt[131] + | instruction_decoder_pt[138] | instruction_decoder_pt[140] + | instruction_decoder_pt[143] | instruction_decoder_pt[145] + | instruction_decoder_pt[148] | instruction_decoder_pt[149] + | instruction_decoder_pt[153] | instruction_decoder_pt[154] + | instruction_decoder_pt[156] | instruction_decoder_pt[157] + | instruction_decoder_pt[160] | instruction_decoder_pt[161] + | instruction_decoder_pt[162] | instruction_decoder_pt[164] + | instruction_decoder_pt[165] | instruction_decoder_pt[168] + | instruction_decoder_pt[169] | instruction_decoder_pt[170] + | instruction_decoder_pt[171] | instruction_decoder_pt[179] + | instruction_decoder_pt[181] | instruction_decoder_pt[185] + | instruction_decoder_pt[207] | instruction_decoder_pt[208] + | instruction_decoder_pt[210] | instruction_decoder_pt[214] + | instruction_decoder_pt[215] | instruction_decoder_pt[216] + | instruction_decoder_pt[217]); +assign isload = + (instruction_decoder_pt[83] | instruction_decoder_pt[87] + | instruction_decoder_pt[93] | instruction_decoder_pt[106] + | instruction_decoder_pt[111] | instruction_decoder_pt[113] + | instruction_decoder_pt[124] | instruction_decoder_pt[129] + | instruction_decoder_pt[143] | instruction_decoder_pt[149] + | instruction_decoder_pt[150] | instruction_decoder_pt[153] + | instruction_decoder_pt[154] | instruction_decoder_pt[157] + | instruction_decoder_pt[164] | instruction_decoder_pt[170] + | instruction_decoder_pt[171] | instruction_decoder_pt[181] + | instruction_decoder_pt[210]); +assign zero_r0 = + (instruction_decoder_pt[34] | instruction_decoder_pt[55] + | instruction_decoder_pt[66] | instruction_decoder_pt[79] + | instruction_decoder_pt[81] | instruction_decoder_pt[83] + | instruction_decoder_pt[86] | instruction_decoder_pt[87] + | instruction_decoder_pt[89] | instruction_decoder_pt[93] + | instruction_decoder_pt[97] | instruction_decoder_pt[100] + | instruction_decoder_pt[109] | instruction_decoder_pt[110] + | instruction_decoder_pt[111] | instruction_decoder_pt[113] + | instruction_decoder_pt[116] | instruction_decoder_pt[120] + | instruction_decoder_pt[122] | instruction_decoder_pt[124] + | instruction_decoder_pt[125] | instruction_decoder_pt[127] + | instruction_decoder_pt[128] | instruction_decoder_pt[129] + | instruction_decoder_pt[131] | instruction_decoder_pt[134] + | instruction_decoder_pt[140] | instruction_decoder_pt[143] + | instruction_decoder_pt[145] | instruction_decoder_pt[148] + | instruction_decoder_pt[149] | instruction_decoder_pt[153] + | instruction_decoder_pt[154] | instruction_decoder_pt[156] + | instruction_decoder_pt[157] | instruction_decoder_pt[164] + | instruction_decoder_pt[168] | instruction_decoder_pt[169] + | instruction_decoder_pt[170] | instruction_decoder_pt[171] + | instruction_decoder_pt[179] | instruction_decoder_pt[181] + | instruction_decoder_pt[184] | instruction_decoder_pt[207] + | instruction_decoder_pt[208] | instruction_decoder_pt[210] + | instruction_decoder_pt[215] | instruction_decoder_pt[218] + ); +assign dec_val = + (instruction_decoder_pt[1] | instruction_decoder_pt[2] + | instruction_decoder_pt[7] | instruction_decoder_pt[10] + | instruction_decoder_pt[14] | instruction_decoder_pt[15] + | instruction_decoder_pt[16] | instruction_decoder_pt[19] + | instruction_decoder_pt[21] | instruction_decoder_pt[36] + | instruction_decoder_pt[37] | instruction_decoder_pt[40] + | instruction_decoder_pt[41] | instruction_decoder_pt[42] + | instruction_decoder_pt[43] | instruction_decoder_pt[44] + | instruction_decoder_pt[54] | instruction_decoder_pt[56] + | instruction_decoder_pt[57] | instruction_decoder_pt[58] + | instruction_decoder_pt[60] | instruction_decoder_pt[63] + | instruction_decoder_pt[64] | instruction_decoder_pt[66] + | instruction_decoder_pt[67] | instruction_decoder_pt[69] + | instruction_decoder_pt[70] | instruction_decoder_pt[71] + | instruction_decoder_pt[72] | instruction_decoder_pt[73] + | instruction_decoder_pt[74] | instruction_decoder_pt[76] + | instruction_decoder_pt[78] | instruction_decoder_pt[80] + | instruction_decoder_pt[81] | instruction_decoder_pt[82] + | instruction_decoder_pt[83] | instruction_decoder_pt[84] + | instruction_decoder_pt[87] | instruction_decoder_pt[88] + | instruction_decoder_pt[89] | instruction_decoder_pt[90] + | instruction_decoder_pt[91] | instruction_decoder_pt[92] + | instruction_decoder_pt[93] | instruction_decoder_pt[94] + | instruction_decoder_pt[95] | instruction_decoder_pt[96] + | instruction_decoder_pt[97] | instruction_decoder_pt[98] + | instruction_decoder_pt[99] | instruction_decoder_pt[100] + | instruction_decoder_pt[101] | instruction_decoder_pt[102] + | instruction_decoder_pt[103] | instruction_decoder_pt[104] + | instruction_decoder_pt[105] | instruction_decoder_pt[106] + | instruction_decoder_pt[108] | instruction_decoder_pt[109] + | instruction_decoder_pt[110] | instruction_decoder_pt[111] + | instruction_decoder_pt[112] | instruction_decoder_pt[113] + | instruction_decoder_pt[114] | instruction_decoder_pt[115] + | instruction_decoder_pt[116] | instruction_decoder_pt[117] + | instruction_decoder_pt[118] | instruction_decoder_pt[119] + | instruction_decoder_pt[120] | instruction_decoder_pt[121] + | instruction_decoder_pt[122] | instruction_decoder_pt[123] + | instruction_decoder_pt[124] | instruction_decoder_pt[125] + | instruction_decoder_pt[126] | instruction_decoder_pt[127] + | instruction_decoder_pt[128] | instruction_decoder_pt[129] + | instruction_decoder_pt[130] | instruction_decoder_pt[131] + | instruction_decoder_pt[132] | instruction_decoder_pt[133] + | instruction_decoder_pt[134] | instruction_decoder_pt[135] + | instruction_decoder_pt[136] | instruction_decoder_pt[137] + | instruction_decoder_pt[138] | instruction_decoder_pt[139] + | instruction_decoder_pt[140] | instruction_decoder_pt[141] + | instruction_decoder_pt[142] | instruction_decoder_pt[143] + | instruction_decoder_pt[144] | instruction_decoder_pt[145] + | instruction_decoder_pt[146] | instruction_decoder_pt[147] + | instruction_decoder_pt[148] | instruction_decoder_pt[149] + | instruction_decoder_pt[151] | instruction_decoder_pt[152] + | instruction_decoder_pt[153] | instruction_decoder_pt[154] + | instruction_decoder_pt[155] | instruction_decoder_pt[156] + | instruction_decoder_pt[157] | instruction_decoder_pt[159] + | instruction_decoder_pt[160] | instruction_decoder_pt[161] + | instruction_decoder_pt[162] | instruction_decoder_pt[163] + | instruction_decoder_pt[164] | instruction_decoder_pt[165] + | instruction_decoder_pt[166] | instruction_decoder_pt[167] + | instruction_decoder_pt[168] | instruction_decoder_pt[169] + | instruction_decoder_pt[170] | instruction_decoder_pt[171] + | instruction_decoder_pt[179] | instruction_decoder_pt[181] + | instruction_decoder_pt[182] | instruction_decoder_pt[183] + | instruction_decoder_pt[184] | instruction_decoder_pt[185] + | instruction_decoder_pt[201] | instruction_decoder_pt[207] + | instruction_decoder_pt[208] | instruction_decoder_pt[210] + | instruction_decoder_pt[211] | instruction_decoder_pt[212] + | instruction_decoder_pt[213] | instruction_decoder_pt[214] + | instruction_decoder_pt[215] | instruction_decoder_pt[216] + | instruction_decoder_pt[217] | instruction_decoder_pt[218] + | instruction_decoder_pt[219] | instruction_decoder_pt[220] + | instruction_decoder_pt[221] | instruction_decoder_pt[222] + | instruction_decoder_pt[223]); +assign async_block = + (instruction_decoder_pt[37] | instruction_decoder_pt[40] + | instruction_decoder_pt[57] | instruction_decoder_pt[67] + | instruction_decoder_pt[73] | instruction_decoder_pt[81] + | instruction_decoder_pt[85] | instruction_decoder_pt[102] + | instruction_decoder_pt[116] | instruction_decoder_pt[125] + | instruction_decoder_pt[128] | instruction_decoder_pt[133] + | instruction_decoder_pt[134]); +assign np1_flush = + (instruction_decoder_pt[2] | instruction_decoder_pt[3] + | instruction_decoder_pt[4] | instruction_decoder_pt[5] + | instruction_decoder_pt[7] | instruction_decoder_pt[11] + | instruction_decoder_pt[12] | instruction_decoder_pt[40] + | instruction_decoder_pt[57] | instruction_decoder_pt[63] + | instruction_decoder_pt[97] | instruction_decoder_pt[110] + | instruction_decoder_pt[116] | instruction_decoder_pt[125] + | instruction_decoder_pt[134]); +assign core_block = + (instruction_decoder_pt[11] | instruction_decoder_pt[116] + | instruction_decoder_pt[125] | instruction_decoder_pt[134] + ); +assign no_ram = + (instruction_decoder_pt[8] | instruction_decoder_pt[14] + | instruction_decoder_pt[16] | instruction_decoder_pt[84] + | instruction_decoder_pt[108] | instruction_decoder_pt[140] + | instruction_decoder_pt[160] | instruction_decoder_pt[165] + | instruction_decoder_pt[214] | instruction_decoder_pt[215] + ); +assign no_pre = + (instruction_decoder_pt[89] | instruction_decoder_pt[97] + | instruction_decoder_pt[110] | instruction_decoder_pt[120] + | instruction_decoder_pt[122] | instruction_decoder_pt[138] + | instruction_decoder_pt[148] | instruction_decoder_pt[156] + | instruction_decoder_pt[161] | instruction_decoder_pt[162] + | instruction_decoder_pt[168] | instruction_decoder_pt[169] + | instruction_decoder_pt[179] | instruction_decoder_pt[185] + | instruction_decoder_pt[207] | instruction_decoder_pt[208] + | instruction_decoder_pt[216] | instruction_decoder_pt[217] + ); + +//assign_end + + + //-------------------------- + // latch inputs + //-------------------------- + //temp + assign SPR_addr = 6'b000000; + // + assign iu5_vld_woaxu = iu4_instr_vld; + assign iu5_ucode_woaxu = iu4_instr_ucode; + assign iu5_2ucode_woaxu = iu4_instr_2ucode; + assign iu5_fuse_nop_woaxu = iu4_fuse_nop; + assign iu5_rte_lq_woaxu = (issue_lq | mtspr_trace_val); + assign iu5_rte_sq_woaxu = (issue_sq | mtspr_trace_val); + assign iu5_rte_fx0_woaxu = (issue_fx0 | or_ppr32_val) & (~(mtspr_trace_val)) & (~iu4_fuse_nop) & (~spr_nop); + assign iu5_rte_fx1_woaxu = issue_fx1 & (~(or_ppr32_val)) & (~iu4_fuse_nop); + assign iu5_rte_axu0_woaxu = 1'b0; + assign iu5_rte_axu1_woaxu = 1'b0; + assign iu5_valop_woaxu = dec_val; + assign iu5_ord_woaxu = (ordered | or_ppr32_val | iu4_is_mtcpcr) & (~(mfspr_tar | mtspr_tar)) & (~(mtspr_trace_val)); + assign iu5_cord_woaxu = erativax_val; + assign iu5_spec_woaxu = spec; + assign iu5_type_fp_woaxu = 1'b0; + assign iu5_type_ap_woaxu = 1'b0; + assign iu5_type_spv_woaxu = 1'b0; + assign iu5_type_st_woaxu = 1'b0; + assign iu5_async_block_woaxu = iu4_fuse_nop | iu4_fuse_val | iu4_instr_ucode[0] | async_block | or_ppr32_val | mfspr_mmucr1; + assign iu5_np1_flush_woaxu = mtspr_tenc | mtspr_xucr0 | mtspr_ccr0 | np1_flush | iu4_is_mtcpcr; + assign iu5_core_block_woaxu = tlbwe_with_binv | mtspr_tenc | mtspr_xucr0 | mtspr_ccr0 | core_block | iu4_is_mtcpcr; + assign iu5_isram_woaxu = iu4_instr_isram; + assign iu5_isload_woaxu = isload; + assign iu5_isstore_woaxu = issue_sq | mtspr_trace_val; + assign iu5_instr_woaxu = iu4_instr; + assign iu5_ifar_woaxu = iu4_ifar; + assign iu5_bta_woaxu = iu4_bta; + assign iu5_ilat_woaxu = ((mfspr_tar | mtspr_tar) == 1'b1) ? 4'b0001 : + latency; + assign iu5_t1_v_woaxu = (ta_vld | iu4_fuse_val) & (~(iu4_instr_ucode[1] | or_ppr32_val)) & (~iu4_fuse_nop) & (~spr_nop); + assign iu5_t1_a_woaxu6 = (iu4_fuse_val == 1'b1) ? {3'b000, iu4_fuse_cmp[6:8]} : + (ta_sel == 1'b0) ? {iu4_instr_ucode_ext[0], iu4_instr[6:10]} : + {iu4_instr_ucode_ext[0], iu4_instr[11:15]}; + assign iu5_t1_t_woaxu = (iu4_fuse_val == 1'b1) ? `cr_t : + `gpr_t; + assign iu5_t2_v_woaxu = (updatesxer | updatesctr) & (~(iu4_instr_ucode[1] | or_ppr32_val)) & (~iu4_fuse_nop); + assign iu5_t2_a_woaxu6 = SPR_addr; + assign iu5_t2_t_woaxu = (updatesxer ? `xer_t : 0 ) | (updatesctr ? `ctr_t : 0 ); + assign iu5_t3_v_woaxu = ((updatescr & (~iu4_fuse_val)) | updateslr | mtspr_tar) & (~(iu4_instr_ucode[1] | or_ppr32_val)) & (~iu4_fuse_nop); + assign iu5_t3_a_woaxu6 = (updatescr_sel == 2'b10 ? {3'b000, iu4_instr[6:8]} : 0 ) | + (iu4_instr[13] & updatescr_sel == 2'b11 ? 6'b000001 : 0 ) | + (iu4_instr[14] & updatescr_sel == 2'b11 ? 6'b000010 : 0 ) | + (iu4_instr[15] & updatescr_sel == 2'b11 ? 6'b000011 : 0 ) | + (iu4_instr[16] & updatescr_sel == 2'b11 ? 6'b000100 : 0 ) | + (iu4_instr[17] & updatescr_sel == 2'b11 ? 6'b000101 : 0 ) | + (iu4_instr[18] & updatescr_sel == 2'b11 ? 6'b000110 : 0 ) | + (iu4_instr[19] & updatescr_sel == 2'b11 ? 6'b000111 : 0 ) | + (mtspr_tar ? 6'b000001 : 0 ); + assign iu5_t3_t_woaxu = (updatescr & (~iu4_fuse_val) ? `cr_t : 0 ) | ((updateslr | mtspr_tar) ? `lr_t : 0 ); + assign iu5_s1_v_woaxu = (s1_vld & (~(zero_r0 & iu5_s1_a_woaxu[0:5] == 6'b000000))) | useslr | mfspr_tar | usescr2 | usestar; + assign iu5_s1_a_woaxu6 = (s1_vld == 1'b1 & s1_sel == 1'b0 & iu4_fuse_val == 1'b1) ? {iu4_instr_ucode_ext[1], iu4_fuse_cmp[11:15]} : + (s1_vld == 1'b1 & s1_sel == 1'b0 & iu4_fuse_val == 1'b0) ? {iu4_instr_ucode_ext[1], iu4_instr[11:15]} : + (s1_vld == 1'b1 & s1_sel == 1'b1) ? {iu4_instr_ucode_ext[1], iu4_instr[6:10]} : + (usescr2 == 1'b1) ? {3'b000, iu4_instr[6:8]} : + ((usestar | mfspr_tar) == 1'b1) ? 6'b000001 : + 0; + assign iu5_s1_t_woaxu = (s1_vld == 1'b1) ? `gpr_t : + ((useslr | mfspr_tar) == 1'b1) ? `lr_t : + ((usestar | mfspr_tar) == 1'b1) ? `lr_t : + (usescr2 == 1'b1) ? `cr_t : + `spr_t; + assign iu5_s2_v_woaxu = s2_vld | usesctr | usescr2 | (usesxer & s3_vld) | ((useslr | usestar) & iu4_fuse_val); + assign iu5_s2_a_woaxu6 = (s2_vld == 1'b1 & s2_sel == 1'b0 & iu4_fuse_val == 1'b1) ? {iu4_instr_ucode_ext[2], iu4_fuse_cmp[16:20]} : + (s2_vld == 1'b1 & s2_sel == 1'b0 & iu4_fuse_val == 1'b0) ? {iu4_instr_ucode_ext[2], iu4_instr[16:20]} : + (s2_vld == 1'b1 & s2_sel == 1'b1) ? {iu4_instr_ucode_ext[2], iu4_instr[11:15]} : + (usescr2 == 1'b1) ? {3'b000, iu4_instr[16:18]} : + (usestar == 1'b1 & iu4_fuse_val == 1'b1) ? 6'b000001 : + 0; + assign iu5_s2_t_woaxu = (s2_vld == 1'b1) ? `gpr_t : + (usesctr == 1'b1) ? `ctr_t : + (usescr2 == 1'b1) ? `cr_t : + (useslr == 1'b1 & iu4_fuse_val == 1'b1) ? `lr_t : + (usestar == 1'b1 & iu4_fuse_val == 1'b1) ? `lr_t : + `xer_t; + assign iu5_s3_v_woaxu = s3_vld | usescr | usesxer; + assign iu5_s3_a_woaxu6 = (usesxer == 1'b1) ? 0 : + (s3_vld == 1'b1) ? {iu4_instr_ucode_ext[3], iu4_instr[6:10]} : + (usescr == 1'b1) ? + ((usescr_sel == 2'b01 ? {3'b000, iu4_instr[11:13]} : 0 ) | + (usescr_sel == 2'b10 ? {3'b000, iu4_instr[21:23]} : 0 ) | + ((iu4_instr[13] & (~(multi_cr))) & usescr_sel == 2'b11 ? 6'b000001 : 0 ) | + ((iu4_instr[14] & (~(multi_cr))) & usescr_sel == 2'b11 ? 6'b000010 : 0 ) | + ((iu4_instr[15] & (~(multi_cr))) & usescr_sel == 2'b11 ? 6'b000011 : 0 ) | + ((iu4_instr[16] & (~(multi_cr))) & usescr_sel == 2'b11 ? 6'b000100 : 0 ) | + ((iu4_instr[17] & (~(multi_cr))) & usescr_sel == 2'b11 ? 6'b000101 : 0 ) | + ((iu4_instr[18] & (~(multi_cr))) & usescr_sel == 2'b11 ? 6'b000110 : 0 ) | + ((iu4_instr[19] & (~(multi_cr))) & usescr_sel == 2'b11 ? 6'b000111 : 0 ) ) : + 0; + assign iu5_s3_t_woaxu = (usesxer == 1'b1) ? `xer_t : + (usescr == 1'b1) ? `cr_t : + `gpr_t; + generate + if (`GPR_POOL_ENC > 6) + begin : gpr_pool + assign iu5_t1_a_woaxu[0:`GPR_POOL_ENC - 7] = 1'b0; + assign iu5_t2_a_woaxu[0:`GPR_POOL_ENC - 7] = 1'b0; + assign iu5_t3_a_woaxu[0:`GPR_POOL_ENC - 7] = 1'b0; + assign iu5_s1_a_woaxu[0:`GPR_POOL_ENC - 7] = 1'b0; + assign iu5_s2_a_woaxu[0:`GPR_POOL_ENC - 7] = 1'b0; + assign iu5_s3_a_woaxu[0:`GPR_POOL_ENC - 7] = 1'b0; + end + endgenerate + assign iu5_t1_a_woaxu[`GPR_POOL_ENC - 6:`GPR_POOL_ENC - 1] = iu5_t1_a_woaxu6[0:5]; + assign iu5_t2_a_woaxu[`GPR_POOL_ENC - 6:`GPR_POOL_ENC - 1] = iu5_t2_a_woaxu6[0:5]; + assign iu5_t3_a_woaxu[`GPR_POOL_ENC - 6:`GPR_POOL_ENC - 1] = iu5_t3_a_woaxu6[0:5]; + assign iu5_s1_a_woaxu[`GPR_POOL_ENC - 6:`GPR_POOL_ENC - 1] = iu5_s1_a_woaxu6[0:5]; + assign iu5_s2_a_woaxu[`GPR_POOL_ENC - 6:`GPR_POOL_ENC - 1] = iu5_s2_a_woaxu6[0:5]; + assign iu5_s3_a_woaxu[`GPR_POOL_ENC - 6:`GPR_POOL_ENC - 1] = iu5_s3_a_woaxu6[0:5]; + assign iu5_br_pred_woaxu = iu4_instr_br_pred; + assign iu5_bh_update_woaxu = iu4_instr_bh_update; + assign iu5_bh0_hist_woaxu = iu4_instr_bh0_hist; + assign iu5_bh1_hist_woaxu = iu4_instr_bh1_hist; + assign iu5_bh2_hist_woaxu = iu4_instr_bh2_hist; + assign iu5_gshare_woaxu = iu4_instr_gshare; + assign iu5_ls_ptr_woaxu = iu4_instr_ls_ptr; + assign iu5_match_woaxu = iu4_instr_match; + assign iu5_error_woaxu = iu4_instr_error | {3{(iu4_instr_isram & no_ram & naxu)}} | {3{(iu4_instr_isram & au_iu_iu4_no_ram & axu)}}; + assign iu5_btb_entry_woaxu = iu4_instr_btb_entry; + assign iu5_btb_hist_woaxu = iu4_instr_btb_hist; + assign iu5_bta_val_woaxu = iu4_instr_bta_val; + //fused branch/compare + assign iu5_fusion_woaxu[0] = iu4_fuse_val; + assign iu5_fusion_woaxu[1:2] = (iu4_fuse_cmp[0:5] == 6'b011111 & iu4_fuse_cmp[21:30] == 10'b0000000000 ? 2'b00 : 0 ) | + (iu4_fuse_cmp[0:5] == 6'b001011 ? 2'b01 : 0 ) | + (iu4_fuse_cmp[0:5] == 6'b011111 & iu4_fuse_cmp[21:30] == 10'b0000100000 ? 2'b10 : 0 ) | + (iu4_fuse_cmp[0:5] == 6'b001010 ? 2'b11 : 0 ); + assign iu5_fusion_woaxu[3] = iu4_fuse_cmp[10]; + assign iu5_fusion_woaxu[4:19] = iu4_fuse_cmp[16:31]; + assign naxu = au_iu_iu4_i_dec_b; + assign axu = (~au_iu_iu4_i_dec_b); + assign iu5_vld_din = iu5_vld_woaxu; + assign iu5_ucode_din = (iu4_instr_vld ? ((naxu == 1'b1 ? iu5_ucode_woaxu[0:2] : 0 ) | (axu == 1'b1 ? au_iu_iu4_ucode[0:2] : 0 )) : 0 ); + assign iu5_2ucode_din = iu5_2ucode_woaxu; + assign iu5_fuse_nop_din = iu5_fuse_nop_woaxu; + assign iu5_rte_lq_din = (~|(iu5_error_din)) & iu4_instr_vld & (~(spr_ccr2_ucode_dis_q & iu5_ucode_din[1])) & ((iu5_rte_lq_woaxu & naxu) | (au_iu_iu4_rte_lq & axu)); + assign iu5_rte_sq_din = (~|(iu5_error_din)) & iu4_instr_vld & (~(spr_ccr2_ucode_dis_q & iu5_ucode_din[1])) & ((iu5_rte_sq_woaxu & naxu) | (au_iu_iu4_rte_sq & axu)); + assign iu5_rte_fx0_din = (~|(iu5_error_din)) & iu4_instr_vld & (~(spr_ccr2_ucode_dis_q & iu5_ucode_din[1])) & (iu5_rte_fx0_woaxu & (~axu)); + assign iu5_rte_fx1_din = (~|(iu5_error_din)) & iu4_instr_vld & (~((spr_ccr2_ucode_dis_q | no_pre) & iu5_ucode_din[1])) & (iu5_rte_fx1_woaxu & (~axu)); + assign iu5_rte_axu0_din = (~|(iu5_error_din)) & iu4_instr_vld & (~(spr_ccr2_ucode_dis_q & iu5_ucode_din[1])) & ((iu5_rte_axu0_woaxu & naxu) | (au_iu_iu4_rte_axu0 & axu)); + assign iu5_rte_axu1_din = (~|(iu5_error_din)) & iu4_instr_vld & (~(spr_ccr2_ucode_dis_q & iu5_ucode_din[1])) & ((iu5_rte_axu1_woaxu & naxu) | (au_iu_iu4_rte_axu1 & axu)); + assign iu5_valop_din = iu5_valop_woaxu | axu; + assign iu5_ord_din = (iu5_ord_woaxu & naxu) | (au_iu_iu4_ord & axu); + assign iu5_cord_din = (iu5_cord_woaxu & naxu) | (au_iu_iu4_cord & axu); + assign iu5_spec_din = (iu5_spec_woaxu & naxu) | (au_iu_iu4_spec & axu); + assign iu5_type_fp_din = ((iu5_type_fp_woaxu & naxu) | (au_iu_iu4_type_fp & axu)); + assign iu5_type_ap_din = ((iu5_type_ap_woaxu & naxu) | (au_iu_iu4_type_ap & axu)); + assign iu5_type_spv_din = ((iu5_type_spv_woaxu & naxu) | (au_iu_iu4_type_spv & axu)); + assign iu5_type_st_din = ((iu5_type_st_woaxu & naxu) | (au_iu_iu4_type_st & axu)); + assign iu5_async_block_din = ((iu5_async_block_woaxu & naxu) | (au_iu_iu4_async_block & axu)); + assign iu5_np1_flush_din = iu5_np1_flush_woaxu; + assign iu5_core_block_din = iu4_instr_vld & iu5_core_block_woaxu; + assign iu5_isram_din = iu5_isram_woaxu; + assign iu5_isload_din = (~|(iu5_error_din)) & (~(iu4_instr_ucode[1])) & ((iu5_isload_woaxu & naxu) | (au_iu_iu4_isload & axu)); + assign iu5_isstore_din = (~|(iu5_error_din)) & (~(iu4_instr_ucode[1])) & ((iu5_isstore_woaxu & naxu) | (au_iu_iu4_isstore & axu)); + assign iu5_instr_din = iu5_instr_woaxu; + assign iu5_ifar_din = iu5_ifar_woaxu; + assign iu5_bta_din = iu5_bta_woaxu; + assign iu5_ilat_din = (naxu ? iu5_ilat_woaxu : 4'b0 ) | ({1'b0, (axu ? au_iu_iu4_ilat : 3'b0 )}); + assign iu5_t1_v_din = iu4_instr_vld & ((iu5_t1_v_woaxu & naxu) | (au_iu_iu4_t1_v & axu)); + assign iu5_t1_t_din = (iu5_t1_t_woaxu & {3{naxu}}) | (au_iu_iu4_t1_t & {3{axu}}); + assign iu5_t1_a_din = (naxu ? iu5_t1_a_woaxu[0:`GPR_POOL_ENC - 1] : 0 ) | (axu ? au_iu_iu4_t1_a[0:`GPR_POOL_ENC - 1] : 0 ); + assign iu5_t2_v_din = iu4_instr_vld & ((iu5_t2_v_woaxu & naxu) | (au_iu_iu4_t2_v & axu)); + assign iu5_t2_a_din = (naxu ? iu5_t2_a_woaxu[0:`GPR_POOL_ENC - 1] : 0 ) | (axu ? au_iu_iu4_t2_a[0:`GPR_POOL_ENC - 1] : 0 ); + assign iu5_t2_t_din = (naxu ? iu5_t2_t_woaxu[0:2] : 0 ) | (axu ? au_iu_iu4_t2_t[0:2] : 0 ); + assign iu5_t3_v_din = iu4_instr_vld & ((iu5_t3_v_woaxu & naxu) | (au_iu_iu4_t3_v & axu)); + assign iu5_t3_a_din = (naxu ? iu5_t3_a_woaxu[0:`GPR_POOL_ENC - 1] : 0 ) | (axu ? au_iu_iu4_t3_a[0:`GPR_POOL_ENC - 1] : 0 ); + assign iu5_t3_t_din = (naxu ? iu5_t3_t_woaxu[0:2] : 0 ) | (axu ? au_iu_iu4_t3_t[0:2] : 0 ); + assign iu5_s1_v_din = (iu5_s1_v_woaxu & naxu) | (au_iu_iu4_s1_v & axu); + assign iu5_s1_a_din = (naxu ? iu5_s1_a_woaxu[0:`GPR_POOL_ENC - 1] : 0 ) | (axu ? au_iu_iu4_s1_a[0:`GPR_POOL_ENC - 1] : 0 ); + assign iu5_s1_t_din = (naxu ? iu5_s1_t_woaxu[0:2] : 0 ) | (axu ? au_iu_iu4_s1_t[0:2] : 0 ); + assign iu5_s2_v_din = (iu5_s2_v_woaxu & naxu) | (au_iu_iu4_s2_v & axu); + assign iu5_s2_a_din = (naxu ? iu5_s2_a_woaxu[0:`GPR_POOL_ENC - 1] : 0 ) | (axu ? au_iu_iu4_s2_a[0:`GPR_POOL_ENC - 1] : 0 ); + assign iu5_s2_t_din = (naxu ? iu5_s2_t_woaxu[0:2] : 0 ) | (axu ? au_iu_iu4_s2_t[0:2] : 0 ); + assign iu5_s3_v_din = (iu5_s3_v_woaxu & naxu) | (au_iu_iu4_s3_v & axu); + assign iu5_s3_a_din = (naxu ? iu5_s3_a_woaxu[0:`GPR_POOL_ENC - 1] : 0 ) | (axu ? au_iu_iu4_s3_a[0:`GPR_POOL_ENC - 1] : 0 ); + assign iu5_s3_t_din = (naxu ? iu5_s3_t_woaxu[0:2] : 0 ) | (axu ? au_iu_iu4_s3_t[0:2] : 0 ); + assign iu5_br_pred_din = iu5_br_pred_woaxu; + assign iu5_bh_update_din = iu5_bh_update_woaxu; + assign iu5_bh0_hist_din = iu5_bh0_hist_woaxu; + assign iu5_bh1_hist_din = iu5_bh1_hist_woaxu; + assign iu5_bh2_hist_din = iu5_bh2_hist_woaxu; + assign iu5_gshare_din = iu5_gshare_woaxu; + assign iu5_ls_ptr_din = iu5_ls_ptr_woaxu; + assign iu5_match_din = iu5_match_woaxu; + assign iu5_error_din = iu5_error_woaxu; + assign iu5_btb_entry_din = iu5_btb_entry_woaxu; + assign iu5_btb_hist_din = iu5_btb_hist_woaxu; + assign iu5_bta_val_din = iu5_bta_val_woaxu; + assign iu5_fusion_din = iu5_fusion_woaxu; + + always @(iu5_vld_q or cp_flush_q or frn_fdec_iu5_stall or iu5_vld_din or iu5_ucode_din or iu5_2ucode_din or iu5_fuse_nop_din or iu5_error_din or iu5_btb_entry_din or iu5_btb_hist_din or iu5_bta_val_din or iu5_fusion_din or iu5_rte_lq_din or iu5_rte_sq_din or iu5_rte_fx0_din or iu5_rte_fx1_din or iu5_rte_axu0_din or iu5_rte_axu1_din or iu5_valop_din or iu5_ord_din or iu5_cord_din or iu5_spec_din or iu5_isram_din or iu5_isload_din or iu5_isstore_din or iu5_instr_din or iu5_ifar_din or iu5_bta_din or iu5_ilat_din or iu5_t1_v_din or iu5_t1_t_din or iu5_t1_a_din or iu5_t2_v_din or iu5_t2_a_din or iu5_t2_t_din or iu5_t3_v_din or iu5_t3_a_din or iu5_t3_t_din or iu5_s1_v_din or iu5_s1_a_din or iu5_s1_t_din or iu5_s2_v_din or iu5_s2_a_din or iu5_s2_t_din or iu5_s3_v_din or iu5_s3_a_din or iu5_s3_t_din or iu5_br_pred_din or iu5_bh_update_din or iu5_bh0_hist_din or iu5_bh1_hist_din or iu5_bh2_hist_din or iu5_gshare_din or iu5_ls_ptr_din or iu5_match_din or iu5_async_block_din or iu5_np1_flush_din or iu5_core_block_din or iu5_type_fp_din or iu5_type_ap_din or iu5_type_spv_din or iu5_type_st_din or iu5_ucode_q or iu5_2ucode_q or iu5_fuse_nop_q or iu5_error_q or iu5_btb_hist_q or iu5_btb_entry_q or iu5_bta_val_q or iu5_fusion_q or iu5_rte_lq_q or iu5_rte_sq_q or iu5_rte_fx0_q or iu5_rte_fx1_q or iu5_rte_axu0_q or iu5_rte_axu1_q or iu5_valop_q or iu5_ord_q or iu5_cord_q or iu5_spec_q or iu5_isram_q or iu5_isload_q or iu5_isstore_q or iu5_instr_q or iu5_ifar_q or iu5_bta_q or iu5_ilat_q or iu5_t1_v_q or iu5_t1_t_q or iu5_t1_a_q or iu5_t2_v_q or iu5_t2_a_q or iu5_t2_t_q or iu5_t3_v_q or iu5_t3_a_q or iu5_t3_t_q or iu5_s1_v_q or iu5_s1_a_q or iu5_s1_t_q or iu5_s2_v_q or iu5_s2_a_q or iu5_s2_t_q or iu5_s3_v_q or iu5_s3_a_q or iu5_s3_t_q or iu5_br_pred_q or iu5_bh_update_q or iu5_bh0_hist_q or iu5_bh1_hist_q or iu5_bh2_hist_q or iu5_gshare_q or iu5_ls_ptr_q or iu5_match_q or iu5_async_block_q or iu5_np1_flush_q or iu5_core_block_q or iu5_type_fp_q or iu5_type_ap_q or iu5_type_spv_q or iu5_type_st_q) + begin: iu5_instr_proc + + iu5_vld_d = iu5_vld_din; + iu5_ucode_d = iu5_ucode_din; + iu5_2ucode_d = iu5_2ucode_din; + iu5_fuse_nop_d = iu5_fuse_nop_din; + iu5_error_d = iu5_error_din; + iu5_btb_entry_d = iu5_btb_entry_din; + iu5_btb_hist_d = iu5_btb_hist_din; + iu5_bta_val_d = iu5_bta_val_din; + iu5_fusion_d = iu5_fusion_din; + iu5_rte_lq_d = iu5_rte_lq_din; + iu5_rte_sq_d = iu5_rte_sq_din; + iu5_rte_fx0_d = iu5_rte_fx0_din; + iu5_rte_fx1_d = iu5_rte_fx1_din; + iu5_rte_axu0_d = iu5_rte_axu0_din; + iu5_rte_axu1_d = iu5_rte_axu1_din; + iu5_valop_d = iu5_valop_din; + iu5_ord_d = iu5_ord_din; + iu5_cord_d = iu5_cord_din; + iu5_spec_d = iu5_spec_din; + iu5_isram_d = iu5_isram_din; + iu5_isload_d = iu5_isload_din; + iu5_isstore_d = iu5_isstore_din; + iu5_instr_d = iu5_instr_din; + iu5_ifar_d = iu5_ifar_din; + iu5_bta_d = iu5_bta_din; + iu5_ilat_d = iu5_ilat_din; + iu5_t1_v_d = iu5_t1_v_din; + iu5_t1_t_d = iu5_t1_t_din; + iu5_t1_a_d = iu5_t1_a_din; + iu5_t2_v_d = iu5_t2_v_din; + iu5_t2_a_d = iu5_t2_a_din; + iu5_t2_t_d = iu5_t2_t_din; + iu5_t3_v_d = iu5_t3_v_din; + iu5_t3_a_d = iu5_t3_a_din; + iu5_t3_t_d = iu5_t3_t_din; + iu5_s1_v_d = iu5_s1_v_din; + iu5_s1_a_d = iu5_s1_a_din; + iu5_s1_t_d = iu5_s1_t_din; + iu5_s2_v_d = iu5_s2_v_din; + iu5_s2_a_d = iu5_s2_a_din; + iu5_s2_t_d = iu5_s2_t_din; + iu5_s3_v_d = iu5_s3_v_din; + iu5_s3_a_d = iu5_s3_a_din; + iu5_s3_t_d = iu5_s3_t_din; + iu5_br_pred_d = iu5_br_pred_din; + iu5_bh_update_d = iu5_bh_update_din; + iu5_bh0_hist_d = iu5_bh0_hist_din; + iu5_bh1_hist_d = iu5_bh1_hist_din; + iu5_bh2_hist_d = iu5_bh2_hist_din; + iu5_gshare_d = iu5_gshare_din; + iu5_ls_ptr_d = iu5_ls_ptr_din; + iu5_match_d = iu5_match_din; + iu5_async_block_d = iu5_async_block_din; + iu5_np1_flush_d = iu5_np1_flush_din; + iu5_core_block_d = iu5_core_block_din; + iu5_type_fp_d = iu5_type_fp_din; + iu5_type_ap_d = iu5_type_ap_din; + iu5_type_spv_d = iu5_type_spv_din; + iu5_type_st_d = iu5_type_st_din; + if (frn_fdec_iu5_stall == 1'b1) + begin + iu5_vld_d = iu5_vld_q; + iu5_ucode_d = iu5_ucode_q; + iu5_2ucode_d = iu5_2ucode_q; + iu5_fuse_nop_d = iu5_fuse_nop_q; + iu5_error_d = iu5_error_q; + iu5_btb_entry_d = iu5_btb_entry_q; + iu5_btb_hist_d = iu5_btb_hist_q; + iu5_bta_val_d = iu5_bta_val_q; + iu5_fusion_d = iu5_fusion_q; + iu5_rte_lq_d = iu5_rte_lq_q; + iu5_rte_sq_d = iu5_rte_sq_q; + iu5_rte_fx0_d = iu5_rte_fx0_q; + iu5_rte_fx1_d = iu5_rte_fx1_q; + iu5_rte_axu0_d = iu5_rte_axu0_q; + iu5_rte_axu1_d = iu5_rte_axu1_q; + iu5_valop_d = iu5_valop_q; + iu5_ord_d = iu5_ord_q; + iu5_cord_d = iu5_cord_q; + iu5_spec_d = iu5_spec_q; + iu5_isram_d = iu5_isram_q; + iu5_isload_d = iu5_isload_q; + iu5_isstore_d = iu5_isstore_q; + iu5_instr_d = iu5_instr_q; + iu5_ifar_d = iu5_ifar_q; + iu5_bta_d = iu5_bta_q; + iu5_ilat_d = iu5_ilat_q; + iu5_t1_v_d = iu5_t1_v_q; + iu5_t1_t_d = iu5_t1_t_q; + iu5_t1_a_d = iu5_t1_a_q; + iu5_t2_v_d = iu5_t2_v_q; + iu5_t2_a_d = iu5_t2_a_q; + iu5_t2_t_d = iu5_t2_t_q; + iu5_t3_v_d = iu5_t3_v_q; + iu5_t3_a_d = iu5_t3_a_q; + iu5_t3_t_d = iu5_t3_t_q; + iu5_s1_v_d = iu5_s1_v_q; + iu5_s1_a_d = iu5_s1_a_q; + iu5_s1_t_d = iu5_s1_t_q; + iu5_s2_v_d = iu5_s2_v_q; + iu5_s2_a_d = iu5_s2_a_q; + iu5_s2_t_d = iu5_s2_t_q; + iu5_s3_v_d = iu5_s3_v_q; + iu5_s3_a_d = iu5_s3_a_q; + iu5_s3_t_d = iu5_s3_t_q; + iu5_br_pred_d = iu5_br_pred_q; + iu5_bh_update_d = iu5_bh_update_q; + iu5_bh0_hist_d = iu5_bh0_hist_q; + iu5_bh1_hist_d = iu5_bh1_hist_q; + iu5_bh2_hist_d = iu5_bh2_hist_q; + iu5_gshare_d = iu5_gshare_q; + iu5_ls_ptr_d = iu5_ls_ptr_q; + iu5_match_d = iu5_match_q; + iu5_async_block_d = iu5_async_block_q; + iu5_np1_flush_d = iu5_np1_flush_q; + iu5_core_block_d = iu5_core_block_q; + iu5_type_fp_d = iu5_type_fp_q; + iu5_type_ap_d = iu5_type_ap_q; + iu5_type_spv_d = iu5_type_spv_q; + iu5_type_st_d = iu5_type_st_q; + end + if (cp_flush_q == 1'b1) + begin + iu5_vld_d = 1'b0; + iu5_rte_lq_d = 1'b0; + iu5_rte_sq_d = 1'b0; + iu5_rte_fx0_d = 1'b0; + iu5_rte_fx1_d = 1'b0; + iu5_rte_axu0_d = 1'b0; + iu5_rte_axu1_d = 1'b0; + iu5_isload_d = 1'b0; + iu5_isstore_d = 1'b0; + iu5_ucode_d = 3'b0; + iu5_2ucode_d = 1'b0; + iu5_t1_v_d = 1'b0; + iu5_t2_v_d = 1'b0; + iu5_t3_v_d = 1'b0; + iu5_core_block_d = 1'b0; + end + end + assign iu5_valid_act = iu5_vld_din | iu5_vld_q | cp_flush_q; + assign iu5_instr_act = iu5_vld_din; + + tri_rlmlatch_p #(.INIT(0)) iu5_vld( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_valid_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_vld_offset]), + .scout(sov[iu5_vld_offset]), + .din(iu5_vld_d), + .dout(iu5_vld_q) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu5_ucode( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_valid_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_ucode_offset:iu5_ucode_offset + 3 - 1]), + .scout(sov[iu5_ucode_offset:iu5_ucode_offset + 3 - 1]), + .din(iu5_ucode_d), + .dout(iu5_ucode_q) + ); + + tri_rlmlatch_p #(.INIT(0)) iu5_2ucode( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_instr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_2ucode_offset]), + .scout(sov[iu5_2ucode_offset]), + .din(iu5_2ucode_d), + .dout(iu5_2ucode_q) + ); + + tri_rlmlatch_p #(.INIT(0)) iu5_fuse_nop( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_instr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_fuse_nop_offset]), + .scout(sov[iu5_fuse_nop_offset]), + .din(iu5_fuse_nop_d), + .dout(iu5_fuse_nop_q) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu5_error( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_instr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_error_offset:iu5_error_offset + 3 - 1]), + .scout(sov[iu5_error_offset:iu5_error_offset + 3 - 1]), + .din(iu5_error_d), + .dout(iu5_error_q) + ); + + tri_rlmlatch_p #(.INIT(0)) iu5_btb_entry( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_instr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_btb_entry_offset]), + .scout(sov[iu5_btb_entry_offset]), + .din(iu5_btb_entry_d), + .dout(iu5_btb_entry_q) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) iu5_btb_hist( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_instr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_btb_hist_offset:iu5_btb_hist_offset + 2 - 1]), + .scout(sov[iu5_btb_hist_offset:iu5_btb_hist_offset + 2 - 1]), + .din(iu5_btb_hist_d), + .dout(iu5_btb_hist_q) + ); + + tri_rlmlatch_p #(.INIT(0)) iu5_bta_val( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_instr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_bta_val_offset]), + .scout(sov[iu5_bta_val_offset]), + .din(iu5_bta_val_d), + .dout(iu5_bta_val_q) + ); + + tri_rlmreg_p #(.WIDTH(20), .INIT(0)) iu5_fusion( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_instr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_fusion_offset:iu5_fusion_offset + 20 - 1]), + .scout(sov[iu5_fusion_offset:iu5_fusion_offset + 20 - 1]), + .din(iu5_fusion_d), + .dout(iu5_fusion_q) + ); + + tri_rlmlatch_p #(.INIT(0)) iu5_rte_lq( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_valid_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_rte_lq_offset]), + .scout(sov[iu5_rte_lq_offset]), + .din(iu5_rte_lq_d), + .dout(iu5_rte_lq_q) + ); + + tri_rlmlatch_p #(.INIT(0)) iu5_rte_sq( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_valid_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_rte_sq_offset]), + .scout(sov[iu5_rte_sq_offset]), + .din(iu5_rte_sq_d), + .dout(iu5_rte_sq_q) + ); + + tri_rlmlatch_p #(.INIT(0)) iu5_rte_fx0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_valid_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_rte_fx0_offset]), + .scout(sov[iu5_rte_fx0_offset]), + .din(iu5_rte_fx0_d), + .dout(iu5_rte_fx0_q) + ); + + tri_rlmlatch_p #(.INIT(0)) iu5_rte_fx1( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_valid_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_rte_fx1_offset]), + .scout(sov[iu5_rte_fx1_offset]), + .din(iu5_rte_fx1_d), + .dout(iu5_rte_fx1_q) + ); + + tri_rlmlatch_p #(.INIT(0)) iu5_rte_axu0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_valid_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_rte_axu0_offset]), + .scout(sov[iu5_rte_axu0_offset]), + .din(iu5_rte_axu0_d), + .dout(iu5_rte_axu0_q) + ); + + tri_rlmlatch_p #(.INIT(0)) iu5_rte_axu1( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_valid_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_rte_axu1_offset]), + .scout(sov[iu5_rte_axu1_offset]), + .din(iu5_rte_axu1_d), + .dout(iu5_rte_axu1_q) + ); + + tri_rlmlatch_p #(.INIT(0)) iu5_valop( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_instr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_valop_offset]), + .scout(sov[iu5_valop_offset]), + .din(iu5_valop_d), + .dout(iu5_valop_q) + ); + + tri_rlmlatch_p #(.INIT(0)) iu5_ord( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_instr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_ord_offset]), + .scout(sov[iu5_ord_offset]), + .din(iu5_ord_d), + .dout(iu5_ord_q) + ); + + tri_rlmlatch_p #(.INIT(0)) iu5_cord( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_instr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_cord_offset]), + .scout(sov[iu5_cord_offset]), + .din(iu5_cord_d), + .dout(iu5_cord_q) + ); + + tri_rlmlatch_p #(.INIT(0)) iu5_spec( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_instr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_spec_offset]), + .scout(sov[iu5_spec_offset]), + .din(iu5_spec_d), + .dout(iu5_spec_q) + ); + + tri_rlmlatch_p #(.INIT(0)) iu5_type_fp( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_instr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_type_fp_offset]), + .scout(sov[iu5_type_fp_offset]), + .din(iu5_type_fp_d), + .dout(iu5_type_fp_q) + ); + + tri_rlmlatch_p #(.INIT(0)) iu5_type_ap( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_instr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_type_ap_offset]), + .scout(sov[iu5_type_ap_offset]), + .din(iu5_type_ap_d), + .dout(iu5_type_ap_q) + ); + + tri_rlmlatch_p #(.INIT(0)) iu5_type_spv( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_instr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_type_spv_offset]), + .scout(sov[iu5_type_spv_offset]), + .din(iu5_type_spv_d), + .dout(iu5_type_spv_q) + ); + + tri_rlmlatch_p #(.INIT(0)) iu5_type_st( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_instr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_type_st_offset]), + .scout(sov[iu5_type_st_offset]), + .din(iu5_type_st_d), + .dout(iu5_type_st_q) + ); + + tri_rlmlatch_p #(.INIT(0)) iu5_async_block( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_instr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_async_block_offset]), + .scout(sov[iu5_async_block_offset]), + .din(iu5_async_block_d), + .dout(iu5_async_block_q) + ); + + tri_rlmlatch_p #(.INIT(0)) iu5_np1_flush( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_instr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_np1_flush_offset]), + .scout(sov[iu5_np1_flush_offset]), + .din(iu5_np1_flush_d), + .dout(iu5_np1_flush_q) + ); + + tri_rlmlatch_p #(.INIT(0)) iu5_core_block( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_valid_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_core_block_offset]), + .scout(sov[iu5_core_block_offset]), + .din(iu5_core_block_d), + .dout(iu5_core_block_q) + ); + + tri_rlmlatch_p #(.INIT(0)) iu5_isram( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_instr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_isram_offset]), + .scout(sov[iu5_isram_offset]), + .din(iu5_isram_d), + .dout(iu5_isram_q) + ); + + tri_rlmlatch_p #(.INIT(0)) iu5_isload( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_valid_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_isload_offset]), + .scout(sov[iu5_isload_offset]), + .din(iu5_isload_d), + .dout(iu5_isload_q) + ); + + tri_rlmlatch_p #(.INIT(0)) iu5_isstore( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_valid_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_isstore_offset]), + .scout(sov[iu5_isstore_offset]), + .din(iu5_isstore_d), + .dout(iu5_isstore_q) + ); + + tri_rlmreg_p #(.WIDTH(32), .INIT(0)) iu5_instr( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_instr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_instr_offset:iu5_instr_offset + 32 - 1]), + .scout(sov[iu5_instr_offset:iu5_instr_offset + 32 - 1]), + .din(iu5_instr_d), + .dout(iu5_instr_q) + ); + + tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) iu5_ifar( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_instr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_ifar_offset:iu5_ifar_offset + (`EFF_IFAR_WIDTH) - 1]), + .scout(sov[iu5_ifar_offset:iu5_ifar_offset + (`EFF_IFAR_WIDTH) - 1]), + .din(iu5_ifar_d), + .dout(iu5_ifar_q) + ); + + tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) iu5_bta( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_instr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_bta_offset:iu5_bta_offset + (`EFF_IFAR_WIDTH) - 1]), + .scout(sov[iu5_bta_offset:iu5_bta_offset + (`EFF_IFAR_WIDTH) - 1]), + .din(iu5_bta_d), + .dout(iu5_bta_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) iu5_ilat( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_instr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_ilat_offset:iu5_ilat_offset + 4 - 1]), + .scout(sov[iu5_ilat_offset:iu5_ilat_offset + 4 - 1]), + .din(iu5_ilat_d), + .dout(iu5_ilat_q) + ); + + tri_rlmlatch_p #(.INIT(0)) iu5_t1_v( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_valid_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_t1_v_offset]), + .scout(sov[iu5_t1_v_offset]), + .din(iu5_t1_v_d), + .dout(iu5_t1_v_q) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu5_t1_t( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_instr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_t1_t_offset:iu5_t1_t_offset + 3 - 1]), + .scout(sov[iu5_t1_t_offset:iu5_t1_t_offset + 3 - 1]), + .din(iu5_t1_t_d), + .dout(iu5_t1_t_q) + ); + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) iu5_t1_a( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_instr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_t1_a_offset:iu5_t1_a_offset + `GPR_POOL_ENC - 1]), + .scout(sov[iu5_t1_a_offset:iu5_t1_a_offset + `GPR_POOL_ENC - 1]), + .din(iu5_t1_a_d), + .dout(iu5_t1_a_q) + ); + + tri_rlmlatch_p #(.INIT(0)) iu5_t2_v( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_valid_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_t2_v_offset]), + .scout(sov[iu5_t2_v_offset]), + .din(iu5_t2_v_d), + .dout(iu5_t2_v_q) + ); + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) iu5_t2_a( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_instr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_t2_a_offset:iu5_t2_a_offset + `GPR_POOL_ENC - 1]), + .scout(sov[iu5_t2_a_offset:iu5_t2_a_offset + `GPR_POOL_ENC - 1]), + .din(iu5_t2_a_d), + .dout(iu5_t2_a_q) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu5_t2_t( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_instr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_t2_t_offset:iu5_t2_t_offset + 3 - 1]), + .scout(sov[iu5_t2_t_offset:iu5_t2_t_offset + 3 - 1]), + .din(iu5_t2_t_d), + .dout(iu5_t2_t_q) + ); + + tri_rlmlatch_p #(.INIT(0)) iu5_t3_v( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_valid_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_t3_v_offset]), + .scout(sov[iu5_t3_v_offset]), + .din(iu5_t3_v_d), + .dout(iu5_t3_v_q) + ); + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) iu5_t3_a( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_instr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_t3_a_offset:iu5_t3_a_offset + `GPR_POOL_ENC - 1]), + .scout(sov[iu5_t3_a_offset:iu5_t3_a_offset + `GPR_POOL_ENC - 1]), + .din(iu5_t3_a_d), + .dout(iu5_t3_a_q) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu5_t3_t( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_instr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_t3_t_offset:iu5_t3_t_offset + 3 - 1]), + .scout(sov[iu5_t3_t_offset:iu5_t3_t_offset + 3 - 1]), + .din(iu5_t3_t_d), + .dout(iu5_t3_t_q) + ); + + tri_rlmlatch_p #(.INIT(0)) iu5_s1_v( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_instr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_s1_v_offset]), + .scout(sov[iu5_s1_v_offset]), + .din(iu5_s1_v_d), + .dout(iu5_s1_v_q) + ); + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) iu5_s1_a( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_instr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_s1_a_offset:iu5_s1_a_offset + `GPR_POOL_ENC - 1]), + .scout(sov[iu5_s1_a_offset:iu5_s1_a_offset + `GPR_POOL_ENC - 1]), + .din(iu5_s1_a_d), + .dout(iu5_s1_a_q) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu5_s1_t( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_instr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_s1_t_offset:iu5_s1_t_offset + 3 - 1]), + .scout(sov[iu5_s1_t_offset:iu5_s1_t_offset + 3 - 1]), + .din(iu5_s1_t_d), + .dout(iu5_s1_t_q) + ); + + tri_rlmlatch_p #(.INIT(0)) iu5_s2_v( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_instr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_s2_v_offset]), + .scout(sov[iu5_s2_v_offset]), + .din(iu5_s2_v_d), + .dout(iu5_s2_v_q) + ); + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) iu5_s2_a( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_instr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_s2_a_offset:iu5_s2_a_offset + `GPR_POOL_ENC - 1]), + .scout(sov[iu5_s2_a_offset:iu5_s2_a_offset + `GPR_POOL_ENC - 1]), + .din(iu5_s2_a_d), + .dout(iu5_s2_a_q) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu5_s2_t( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_instr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_s2_t_offset:iu5_s2_t_offset + 3 - 1]), + .scout(sov[iu5_s2_t_offset:iu5_s2_t_offset + 3 - 1]), + .din(iu5_s2_t_d), + .dout(iu5_s2_t_q) + ); + + tri_rlmlatch_p #(.INIT(0)) iu5_s3_v( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_instr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_s3_v_offset]), + .scout(sov[iu5_s3_v_offset]), + .din(iu5_s3_v_d), + .dout(iu5_s3_v_q) + ); + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) iu5_s3_a( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_instr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_s3_a_offset:iu5_s3_a_offset + `GPR_POOL_ENC - 1]), + .scout(sov[iu5_s3_a_offset:iu5_s3_a_offset + `GPR_POOL_ENC - 1]), + .din(iu5_s3_a_d), + .dout(iu5_s3_a_q) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu5_s3_t( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_instr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_s3_t_offset:iu5_s3_t_offset + 3 - 1]), + .scout(sov[iu5_s3_t_offset:iu5_s3_t_offset + 3 - 1]), + .din(iu5_s3_t_d), + .dout(iu5_s3_t_q) + ); + + tri_rlmlatch_p #(.INIT(0)) iu5_br_pred( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_instr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_br_pred_offset]), + .scout(sov[iu5_br_pred_offset]), + .din(iu5_br_pred_d), + .dout(iu5_br_pred_q) + ); + + tri_rlmlatch_p #(.INIT(0)) iu5_bh_update( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_instr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_bh_update_offset]), + .scout(sov[iu5_bh_update_offset]), + .din(iu5_bh_update_d), + .dout(iu5_bh_update_q) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) iu5_bh0_hist( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_instr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_bh0_hist_offset:iu5_bh0_hist_offset + 2 - 1]), + .scout(sov[iu5_bh0_hist_offset:iu5_bh0_hist_offset + 2 - 1]), + .din(iu5_bh0_hist_d), + .dout(iu5_bh0_hist_q) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) iu5_bh1_hist( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_instr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_bh1_hist_offset:iu5_bh1_hist_offset + 2 - 1]), + .scout(sov[iu5_bh1_hist_offset:iu5_bh1_hist_offset + 2 - 1]), + .din(iu5_bh1_hist_d), + .dout(iu5_bh1_hist_q) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) iu5_bh2_hist( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_instr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_bh2_hist_offset:iu5_bh2_hist_offset + 2 - 1]), + .scout(sov[iu5_bh2_hist_offset:iu5_bh2_hist_offset + 2 - 1]), + .din(iu5_bh2_hist_d), + .dout(iu5_bh2_hist_q) + ); + + tri_rlmreg_p #(.WIDTH(18), .INIT(0)) iu5_gshare( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_instr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_gshare_offset:iu5_gshare_offset + 18 - 1]), + .scout(sov[iu5_gshare_offset:iu5_gshare_offset + 18 - 1]), + .din(iu5_gshare_d), + .dout(iu5_gshare_q) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu5_ls_ptr( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_instr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_ls_ptr_offset:iu5_ls_ptr_offset + 3 - 1]), + .scout(sov[iu5_ls_ptr_offset:iu5_ls_ptr_offset + 3 - 1]), + .din(iu5_ls_ptr_d), + .dout(iu5_ls_ptr_q) + ); + + tri_rlmlatch_p #(.INIT(0)) iu5_match( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu5_instr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu5_match_offset]), + .scout(sov[iu5_match_offset]), + .din(iu5_match_d), + .dout(iu5_match_q) + ); + + tri_rlmlatch_p #(.INIT(0)) spr_epcr_dgtmi_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[spr_epcr_dgtmi_offset]), + .scout(sov[spr_epcr_dgtmi_offset]), + .din(xu_iu_epcr_dgtmi), + .dout(spr_epcr_dgtmi_q) + ); + + tri_rlmlatch_p #(.INIT(0)) spr_msrp_uclep_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[spr_msrp_uclep_offset]), + .scout(sov[spr_msrp_uclep_offset]), + .din(xu_iu_msrp_uclep), + .dout(spr_msrp_uclep_q) + ); + + tri_rlmlatch_p #(.INIT(0)) spr_msr_pr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[spr_msr_pr_offset]), + .scout(sov[spr_msr_pr_offset]), + .din(xu_iu_msr_pr), + .dout(spr_msr_pr_q) + ); + + tri_rlmlatch_p #(.INIT(0)) spr_msr_gs_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[spr_msr_gs_offset]), + .scout(sov[spr_msr_gs_offset]), + .din(xu_iu_msr_gs), + .dout(spr_msr_gs_q) + ); + + tri_rlmlatch_p #(.INIT(0)) spr_msr_ucle_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[spr_msr_ucle_offset]), + .scout(sov[spr_msr_ucle_offset]), + .din(xu_iu_msr_ucle), + .dout(spr_msr_ucle_q) + ); + + tri_rlmlatch_p #(.INIT(0)) spr_ccr2_ucode_dis_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[spr_ccr2_ucode_dis_offset]), + .scout(sov[spr_ccr2_ucode_dis_offset]), + .din(xu_iu_ccr2_ucode_dis), + .dout(spr_ccr2_ucode_dis_q) + ); + + tri_rlmlatch_p #(.INIT(0)) cp_flush_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[cp_flush_offset]), + .scout(sov[cp_flush_offset]), + .din(cp_flush_d), + .dout(cp_flush_q) + ); + // Outputs to rename + assign fdec_frn_iu5_ix_vld = iu5_vld_q; + assign fdec_frn_iu5_ix_ucode = iu5_ucode_q; + assign fdec_frn_iu5_ix_2ucode = iu5_2ucode_q; + assign fdec_frn_iu5_ix_fuse_nop = iu5_fuse_nop_q; + assign fdec_frn_iu5_ix_error = iu5_error_q; + assign fdec_frn_iu5_ix_fusion = iu5_fusion_q; + assign fdec_frn_iu5_ix_rte_lq = iu5_rte_lq_q; + assign fdec_frn_iu5_ix_rte_sq = iu5_rte_sq_q; + assign fdec_frn_iu5_ix_rte_fx0 = iu5_rte_fx0_q; + assign fdec_frn_iu5_ix_rte_fx1 = iu5_rte_fx1_q; + assign fdec_frn_iu5_ix_rte_axu0 = iu5_rte_axu0_q; + assign fdec_frn_iu5_ix_rte_axu1 = iu5_rte_axu1_q; + assign fdec_frn_iu5_ix_valop = iu5_valop_q; + assign fdec_frn_iu5_ix_ord = iu5_ord_q; + assign fdec_frn_iu5_ix_cord = iu5_cord_q; + assign fdec_frn_iu5_ix_spec = iu5_spec_q; + assign fdec_frn_iu5_ix_type_fp = iu5_type_fp_q; + assign fdec_frn_iu5_ix_type_ap = iu5_type_ap_q; + assign fdec_frn_iu5_ix_type_spv = iu5_type_spv_q; + assign fdec_frn_iu5_ix_type_st = iu5_type_st_q; + assign fdec_frn_iu5_ix_async_block = iu5_async_block_q; + assign fdec_frn_iu5_ix_np1_flush = iu5_np1_flush_q; + assign fdec_frn_iu5_ix_core_block = iu5_core_block_q; + assign fdec_frn_iu5_ix_isram = iu5_isram_q; + assign fdec_frn_iu5_ix_isload = iu5_isload_q; + assign fdec_frn_iu5_ix_isstore = iu5_isstore_q; + assign fdec_frn_iu5_ix_instr = iu5_instr_q; + assign fdec_frn_iu5_ix_ifar = iu5_ifar_q; + assign fdec_frn_iu5_ix_bta = iu5_bta_q; + assign fdec_frn_iu5_ix_ilat = iu5_ilat_q; + assign fdec_frn_iu5_ix_t1_v = iu5_t1_v_q; + assign fdec_frn_iu5_ix_t1_t = iu5_t1_t_q; + assign fdec_frn_iu5_ix_t1_a = iu5_t1_a_q; + assign fdec_frn_iu5_ix_t2_v = iu5_t2_v_q; + assign fdec_frn_iu5_ix_t2_a = iu5_t2_a_q; + assign fdec_frn_iu5_ix_t2_t = iu5_t2_t_q; + assign fdec_frn_iu5_ix_t3_v = iu5_t3_v_q; + assign fdec_frn_iu5_ix_t3_a = iu5_t3_a_q; + assign fdec_frn_iu5_ix_t3_t = iu5_t3_t_q; + assign fdec_frn_iu5_ix_s1_v = iu5_s1_v_q; + assign fdec_frn_iu5_ix_s1_a = iu5_s1_a_q; + assign fdec_frn_iu5_ix_s1_t = iu5_s1_t_q; + assign fdec_frn_iu5_ix_s2_v = iu5_s2_v_q; + assign fdec_frn_iu5_ix_s2_a = iu5_s2_a_q; + assign fdec_frn_iu5_ix_s2_t = iu5_s2_t_q; + assign fdec_frn_iu5_ix_s3_v = iu5_s3_v_q; + assign fdec_frn_iu5_ix_s3_a = iu5_s3_a_q; + assign fdec_frn_iu5_ix_s3_t = iu5_s3_t_q; + assign fdec_frn_iu5_ix_br_pred = iu5_br_pred_q; + assign fdec_frn_iu5_ix_bh_update = iu5_bh_update_q; + assign fdec_frn_iu5_ix_bh0_hist = iu5_bh0_hist_q; + assign fdec_frn_iu5_ix_bh1_hist = iu5_bh1_hist_q; + assign fdec_frn_iu5_ix_bh2_hist = iu5_bh2_hist_q; + assign fdec_frn_iu5_ix_gshare = iu5_gshare_q; + assign fdec_frn_iu5_ix_ls_ptr = iu5_ls_ptr_q; + assign fdec_frn_iu5_ix_match = iu5_match_q; + assign fdec_frn_iu5_ix_btb_entry = iu5_btb_entry_q; + assign fdec_frn_iu5_ix_btb_hist = iu5_btb_hist_q; + assign fdec_frn_iu5_ix_bta_val = iu5_bta_val_q; + //----------------------------------------------- + // pervasive + //----------------------------------------------- + + tri_plat #(.WIDTH(2)) perv_2to1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + .din({pc_iu_func_sl_thold_2,pc_iu_sg_2}), + .q({pc_iu_func_sl_thold_1,pc_iu_sg_1}) + ); + + + tri_plat #(.WIDTH(2)) perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + .din({pc_iu_func_sl_thold_1,pc_iu_sg_1}), + .q({pc_iu_func_sl_thold_0,pc_iu_sg_0}) + ); + + tri_lcbor perv_lcbor( + .clkoff_b(clkoff_b), + .thold(pc_iu_func_sl_thold_0), + .sg(pc_iu_sg_0), + .act_dis(act_dis), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b) + ); + //--------------------------------------------------------------------- + // Scan + //--------------------------------------------------------------------- + assign siv[0:scan_right] = {sov[1:scan_right], scan_in}; + assign scan_out = sov[0]; + +endmodule diff --git a/dev/verilog/work/iuq_ifetch.v b/dev/verilog/work/iuq_ifetch.v new file mode 100755 index 0000000..2a17659 --- /dev/null +++ b/dev/verilog/work/iuq_ifetch.v @@ -0,0 +1,1475 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//******************************************************************** +//* +//* TITLE: Instruction Fetch RLM wrapper +//* +//* NAME: iuq_ifetch.v +//* +//********************************************************************* + +`include "tri_a2o.vh" + +module iuq_ifetch( + (* pin_data="PIN_FUNCTION=/G_CLK/" *) + input [0:`NCLK_WIDTH-1] nclk, + + input tc_ac_ccflush_dc, + input tc_ac_scan_dis_dc_b, + input tc_ac_scan_diag_dc, + + input pc_iu_func_sl_thold_2, + input pc_iu_func_slp_sl_thold_2, + input pc_iu_func_nsl_thold_2, // added for custom cam + input pc_iu_cfg_slp_sl_thold_2, // for boot config slats + input pc_iu_regf_slp_sl_thold_2, + input pc_iu_time_sl_thold_2, + input pc_iu_abst_sl_thold_2, + input pc_iu_abst_slp_sl_thold_2, + input pc_iu_repr_sl_thold_2, + input pc_iu_ary_nsl_thold_2, + input pc_iu_ary_slp_nsl_thold_2, + input pc_iu_func_slp_nsl_thold_2, + input pc_iu_bolt_sl_thold_2, + input pc_iu_sg_2, + input pc_iu_fce_2, + input clkoff_b, + input act_dis, + input delay_lclkr, + input mpw1_b, + input g8t_clkoff_b, + input g8t_d_mode, + input [0:4] g8t_delay_lclkr, + input [0:4] g8t_mpw1_b, + input g8t_mpw2_b, + input g6t_clkoff_b, + input g6t_act_dis, + input g6t_d_mode, + input [0:3] g6t_delay_lclkr, + input [0:4] g6t_mpw1_b, + input g6t_mpw2_b, + input cam_clkoff_b, + input cam_act_dis, + input cam_d_mode, + input [0:4] cam_delay_lclkr, + input [0:4] cam_mpw1_b, + input cam_mpw2_b, + + (* pin_data ="PIN_FUNCTION=/SCAN_IN/" *) + input func_scan_in, + (* pin_data ="PIN_FUNCTION=/SCAN_OUT/" *) + output func_scan_out, + (* pin_data ="PIN_FUNCTION=/SCAN_IN/" *) + input ac_ccfg_scan_in, + (* pin_data ="PIN_FUNCTION=/SCAN_OUT/" *) + output ac_ccfg_scan_out, + (* pin_data ="PIN_FUNCTION=/SCAN_IN/" *) + input time_scan_in, + (* pin_data ="PIN_FUNCTION=/SCAN_OUT/" *) + output time_scan_out, + (* pin_data ="PIN_FUNCTION=/SCAN_IN/" *) + input repr_scan_in, + (* pin_data ="PIN_FUNCTION=/SCAN_OUT/" *) + output repr_scan_out, + (* pin_data ="PIN_FUNCTION=/SCAN_IN/" *) + input [0:2] abst_scan_in, + (* pin_data ="PIN_FUNCTION=/SCAN_OUT/" *) + output [0:2] abst_scan_out, + (* pin_data ="PIN_FUNCTION=/SCAN_IN/" *) + input [0:4] regf_scan_in, + (* pin_data ="PIN_FUNCTION=/SCAN_OUT/" *) + output [0:4] regf_scan_out, + + output iu_pc_err_icache_parity, + output iu_pc_err_icachedir_parity, + output iu_pc_err_icachedir_multihit, + output iu_pc_err_ierat_multihit, + output iu_pc_err_ierat_parity, + + input pc_iu_inj_icache_parity, + input pc_iu_inj_icachedir_parity, + input pc_iu_inj_icachedir_multihit, + + input pc_iu_abist_g8t_wenb, + input pc_iu_abist_g8t1p_renb_0, + input [0:3] pc_iu_abist_di_0, + input pc_iu_abist_g8t_bw_1, + input pc_iu_abist_g8t_bw_0, + input [3:9] pc_iu_abist_waddr_0, + input [1:9] pc_iu_abist_raddr_0, + input pc_iu_abist_ena_dc, + input pc_iu_abist_wl128_comp_ena, + input pc_iu_abist_raw_dc_b, + input [0:3] pc_iu_abist_g8t_dcomp, + input [0:1] pc_iu_abist_g6t_bw, + input [0:3] pc_iu_abist_di_g6t_2r, + input pc_iu_abist_wl512_comp_ena, + input [0:3] pc_iu_abist_dcomp_g6t_2r, + input pc_iu_abist_g6t_r_wb, + input an_ac_lbist_ary_wrt_thru_dc, + input an_ac_lbist_en_dc, + input an_ac_atpg_en_dc, + input an_ac_grffence_en_dc, + + input pc_iu_bo_enable_3, // bolt-on ABIST + input pc_iu_bo_reset, + input pc_iu_bo_unload, + input pc_iu_bo_repair, + input pc_iu_bo_shdata, + input [0:3] pc_iu_bo_select, + output [0:3] iu_pc_bo_fail, + output [0:3] iu_pc_bo_diagout, + + // ICBI Interface to IU + input [0:`THREADS-1] lq_iu_icbi_val, + input [64-`REAL_IFAR_WIDTH:57] lq_iu_icbi_addr, + output [0:`THREADS-1] iu_lq_icbi_complete, + input lq_iu_ici_val, + output iu_lq_spr_iucr0_icbi_ack, + + // ERAT + input pc_iu_init_reset, + + // XU IERAT interface + input [0:`THREADS-1] xu_iu_val, + input xu_iu_is_eratre, + input xu_iu_is_eratwe, + input xu_iu_is_eratsx, + input xu_iu_is_eratilx, + input cp_is_isync, + input cp_is_csync, + input [0:1] xu_iu_ws, + input [0:3] xu_iu_ra_entry, + + input [64-`GPR_WIDTH:51] xu_iu_rb, + input [64-`GPR_WIDTH:63] xu_iu_rs_data, + output iu_xu_ord_read_done, + output iu_xu_ord_write_done, + output iu_xu_ord_par_err, + output iu_xu_ord_n_flush_req, + input [0:`THREADS-1] xu_iu_msr_gs, + input [0:`THREADS-1] xu_iu_msr_pr, + input [0:`THREADS-1] xu_iu_msr_is, + input xu_iu_hid_mmu_mode, + input xu_iu_spr_ccr2_ifrat, + input [0:8] xu_iu_spr_ccr2_ifratsc, // 0:4: wimge, 5:8: u0:3 + input xu_iu_xucr4_mmu_mchk, + output [64-`GPR_WIDTH:63] iu_xu_ex5_data, + + output iu_mm_ierat_req, + output iu_mm_ierat_req_nonspec, + output [0:51] iu_mm_ierat_epn, + output [0:`THREADS-1] iu_mm_ierat_thdid, + output [0:3] iu_mm_ierat_state, + output [0:13] iu_mm_ierat_tid, + output [0:`THREADS-1] iu_mm_ierat_flush, + output [0:`THREADS-1] iu_mm_perf_itlb, + + input [0:4] mm_iu_ierat_rel_val, + input [0:131] mm_iu_ierat_rel_data, + + input [0:13] mm_iu_t0_ierat_pid, + input [0:19] mm_iu_t0_ierat_mmucr0, + `ifndef THREADS1 + input [0:13] mm_iu_t1_ierat_pid, + input [0:19] mm_iu_t1_ierat_mmucr0, + `endif + output [0:17] iu_mm_ierat_mmucr0, + output [0:`THREADS-1] iu_mm_ierat_mmucr0_we, + input [0:8] mm_iu_ierat_mmucr1, + output [0:3] iu_mm_ierat_mmucr1, + output [0:`THREADS-1] iu_mm_ierat_mmucr1_we, + + input mm_iu_ierat_snoop_coming, + input mm_iu_ierat_snoop_val, + input [0:25] mm_iu_ierat_snoop_attr, + input [62-`EFF_IFAR_ARCH:51] mm_iu_ierat_snoop_vpn, + output iu_mm_ierat_snoop_ack, + + // MMU Connections + input [0:`THREADS-1] mm_iu_hold_req, + input [0:`THREADS-1] mm_iu_hold_done, + input [0:`THREADS-1] mm_iu_bus_snoop_hold_req, + input [0:`THREADS-1] mm_iu_bus_snoop_hold_done, + + // SELECT, DIR, & MISS + input [0:`THREADS-1] pc_iu_pm_fetch_halt, + input [0:`THREADS-1] xu_iu_run_thread, + input [0:`THREADS-1] cp_ic_stop, + input [0:`THREADS-1] xu_iu_msr_cm, + + input [0:`THREADS-1] iu_flush, + input [0:`THREADS-1] br_iu_redirect, + input [62-`EFF_IFAR_ARCH:61] br_iu_bta, + input [0:`THREADS-1] cp_flush, + input [62-`EFF_IFAR_ARCH:61] cp_iu0_t0_flush_ifar, + `ifndef THREADS1 + input [62-`EFF_IFAR_ARCH:61] cp_iu0_t1_flush_ifar, + `endif + input [0:`THREADS-1] cp_iu0_flush_2ucode, + input [0:`THREADS-1] cp_iu0_flush_2ucode_type, + input [0:`THREADS-1] cp_iu0_flush_nonspec, + input [0:`THREADS-1] cp_flush_into_uc, + input [0:`THREADS-1] cp_uc_np1_flush, + input [43:61] cp_uc_t0_flush_ifar, + `ifndef THREADS1 + input [43:61] cp_uc_t1_flush_ifar, + `endif + input [0:`THREADS-1] cp_uc_credit_free, + + output [0:`THREADS-1] ic_cp_nonspec_hit, + + input an_ac_back_inv, + input [64-`REAL_IFAR_WIDTH:57] an_ac_back_inv_addr, + input an_ac_back_inv_target, // connect to bit(0) + + output [0:`THREADS-1] iu_lq_request, + output [0:1] iu_lq_ctag, + output [64-`REAL_IFAR_WIDTH:59] iu_lq_ra, + output [0:4] iu_lq_wimge, + output [0:3] iu_lq_userdef, + + input an_ac_reld_data_vld, + input [0:4] an_ac_reld_core_tag, + input [58:59] an_ac_reld_qw, + input [0:127] an_ac_reld_data, + input an_ac_reld_ecc_err, + input an_ac_reld_ecc_err_ue, + + //Instruction Buffer + input [0:`IBUFF_DEPTH/4-1] ib_ic_t0_need_fetch, + `ifndef THREADS1 + input [0:`IBUFF_DEPTH/4-1] ib_ic_t1_need_fetch, + `endif + + input [0:`THREADS-1] cp_async_block, + output iu_mm_lmq_empty, + output [0:`THREADS-1] iu_xu_icache_quiesce, + output [0:`THREADS-1] iu_pc_icache_quiesce, + + //---------Branch Predict + //in from bht + input [0:1] iu2_0_bh0_rd_data, + input [0:1] iu2_1_bh0_rd_data, + input [0:1] iu2_2_bh0_rd_data, + input [0:1] iu2_3_bh0_rd_data, + + input [0:1] iu2_0_bh1_rd_data, + input [0:1] iu2_1_bh1_rd_data, + input [0:1] iu2_2_bh1_rd_data, + input [0:1] iu2_3_bh1_rd_data, + + input iu2_0_bh2_rd_data, + input iu2_1_bh2_rd_data, + input iu2_2_bh2_rd_data, + input iu2_3_bh2_rd_data, + + //out to bht + output reg [0:9] iu0_bh0_rd_addr, + output reg [0:9] iu0_bh1_rd_addr, + output reg [0:8] iu0_bh2_rd_addr, + output reg iu0_bh0_rd_act, + output reg iu0_bh1_rd_act, + output reg iu0_bh2_rd_act, + output reg [0:1] ex5_bh0_wr_data, + output reg [0:1] ex5_bh1_wr_data, + output reg ex5_bh2_wr_data, + output reg [0:9] ex5_bh0_wr_addr, + output reg [0:9] ex5_bh1_wr_addr, + output reg [0:8] ex5_bh2_wr_addr, + output reg [0:3] ex5_bh0_wr_act, + output reg [0:3] ex5_bh1_wr_act, + output reg [0:3] ex5_bh2_wr_act, + + //in/out to btb + output reg [0:5] iu0_btb_rd_addr, + output reg iu0_btb_rd_act, + input [0:63] iu2_btb_rd_data, + output reg [0:5] ex5_btb_wr_addr, + output reg ex5_btb_wr_act, + output reg [0:63] ex5_btb_wr_data, + + //iu3 + output [0:3] bp_ib_iu3_t0_val, + output [62-`EFF_IFAR_WIDTH:61] bp_ib_iu3_t0_ifar, + output [62-`EFF_IFAR_WIDTH:61] bp_ib_iu3_t0_bta, + + //iu3 instruction(0:31) + + output [0:69] bp_ib_iu3_t0_0_instr, + output [0:69] bp_ib_iu3_t0_1_instr, + output [0:69] bp_ib_iu3_t0_2_instr, + output [0:69] bp_ib_iu3_t0_3_instr, + `ifndef THREADS1 + output [0:3] bp_ib_iu3_t1_val, + output [62-`EFF_IFAR_WIDTH:61] bp_ib_iu3_t1_ifar, + output [62-`EFF_IFAR_WIDTH:61] bp_ib_iu3_t1_bta, + + //iu3 instruction(0:31) + + output [0:69] bp_ib_iu3_t1_0_instr, + output [0:69] bp_ib_iu3_t1_1_instr, + output [0:69] bp_ib_iu3_t1_2_instr, + output [0:69] bp_ib_iu3_t1_3_instr, + `endif + + //ex4 update + input [0:`THREADS-1] cp_bp_val, + input [62-`EFF_IFAR_WIDTH:61] cp_bp_t0_ifar, + input [0:1] cp_bp_t0_bh0_hist, + input [0:1] cp_bp_t0_bh1_hist, + input [0:1] cp_bp_t0_bh2_hist, + `ifndef THREADS1 + input [62-`EFF_IFAR_WIDTH:61] cp_bp_t1_ifar, + input [0:1] cp_bp_t1_bh0_hist, + input [0:1] cp_bp_t1_bh1_hist, + input [0:1] cp_bp_t1_bh2_hist, + `endif + input [0:`THREADS-1] cp_bp_br_pred, + input [0:`THREADS-1] cp_bp_br_taken, + input [0:`THREADS-1] cp_bp_bh_update, + input [0:`THREADS-1] cp_bp_bcctr, + input [0:`THREADS-1] cp_bp_bclr, + input [0:`THREADS-1] cp_bp_getNIA, + input [0:`THREADS-1] cp_bp_group, + input [0:`THREADS-1] cp_bp_lk, + input [0:1] cp_bp_t0_bh, + input [62-`EFF_IFAR_WIDTH:61] cp_bp_t0_bta, + input [0:9] cp_bp_t0_gshare, + input [0:2] cp_bp_t0_ls_ptr, + input [0:1] cp_bp_t0_btb_hist, + `ifndef THREADS1 + input [0:1] cp_bp_t1_bh, + input [62-`EFF_IFAR_WIDTH:61] cp_bp_t1_bta, + input [0:9] cp_bp_t1_gshare, + input [0:2] cp_bp_t1_ls_ptr, + input [0:1] cp_bp_t1_btb_hist, + `endif + input [0:`THREADS-1] cp_bp_btb_entry, + + //config bits + input [0:17] br_iu_gshare, + input [0:2] br_iu_ls_ptr, + input [62-`EFF_IFAR_WIDTH:61] br_iu_ls_data, + input br_iu_ls_update, + + input [0:`THREADS-1] xu_iu_msr_de, + input [0:`THREADS-1] xu_iu_dbcr0_icmp, + input [0:`THREADS-1] xu_iu_dbcr0_brt, + input [0:`THREADS-1] xu_iu_iac1_en, + input [0:`THREADS-1] xu_iu_iac2_en, + input [0:`THREADS-1] xu_iu_iac3_en, + input [0:`THREADS-1] xu_iu_iac4_en, + input [0:`THREADS-1] lq_iu_spr_dbcr3_ivc, + input [0:`THREADS-1] xu_iu_single_instr_mode, + input [0:`THREADS-1] xu_iu_raise_iss_pri, + + (* pin_data ="PIN_FUNCTION=/SCAN_IN/" *) + input [0:2*`THREADS-1] bp_scan_in, + (* pin_data ="PIN_FUNCTION=/SCAN_OUT/" *) + output [0:2*`THREADS-1] bp_scan_out, + + //-------------RAM + input [0:31] pc_iu_ram_instr, + input [0:3] pc_iu_ram_instr_ext, + input pc_iu_ram_issue, + input [0:`THREADS-1] pc_iu_ram_active, + + input iu_pc_ram_done, + + input [0:`THREADS-1] ib_rm_rdy, + + output [0:`THREADS-1] rm_ib_iu3_val, + output [0:35] rm_ib_iu3_instr, + + input ram_scan_in, + output ram_scan_out, + + //-------------UCode + input [0:`THREADS-1] uc_scan_in, + output [0:`THREADS-1] uc_scan_out, + + output [0:`THREADS-1] iu_pc_err_ucode_illegal, + + input [0:`THREADS-1] xu_iu_ucode_xer_val, + input [57:63] xu_iu_ucode_xer, + + input [0:`THREADS-1] ib_uc_rdy, + + output [0:3] uc_ib_iu3_t0_invalid, + output [0:1] uc_ib_t0_val, + `ifndef THREADS1 + output [0:3] uc_ib_iu3_t1_invalid, + output [0:1] uc_ib_t1_val, + `endif + output [0:`THREADS-1] uc_ib_done, + output [0:`THREADS-1] uc_ib_iu3_flush_all, + + output [0:31] uc_ib_t0_instr0, + output [0:31] uc_ib_t0_instr1, + output [62-`EFF_IFAR_WIDTH:61] uc_ib_t0_ifar0, + output [62-`EFF_IFAR_WIDTH:61] uc_ib_t0_ifar1, + output [0:3] uc_ib_t0_ext0, + output [0:3] uc_ib_t0_ext1, + `ifndef THREADS1 + output [0:31] uc_ib_t1_instr0, + output [0:31] uc_ib_t1_instr1, + output [62-`EFF_IFAR_WIDTH:61] uc_ib_t1_ifar0, + output [62-`EFF_IFAR_WIDTH:61] uc_ib_t1_ifar1, + output [0:3] uc_ib_t1_ext0, + output [0:3] uc_ib_t1_ext1, + `endif + + //--------------SPR + // inputs from xx + input iu_slowspr_val_in, + input iu_slowspr_rw_in, + input [0:1] iu_slowspr_etid_in, + input [0:9] iu_slowspr_addr_in, + input [64-`GPR_WIDTH:63] iu_slowspr_data_in, + input iu_slowspr_done_in, + + // outputs to xx + output iu_slowspr_val_out, + output iu_slowspr_rw_out, + output [0:1] iu_slowspr_etid_out, + output [0:9] iu_slowspr_addr_out, + output [64-`GPR_WIDTH:63] iu_slowspr_data_out, + output iu_slowspr_done_out, + + output [0:31] spr_dec_mask, + output [0:31] spr_dec_match, + output [0:`THREADS-1] spr_single_issue, + output [0:7] iu_au_t0_config_iucr, + `ifndef THREADS1 + output [0:7] iu_au_t1_config_iucr, + `endif + + input [0:`THREADS-1] xu_iu_pri_val, + input [0:2] xu_iu_pri, + + input [0:20] slice_ic_t0_perf_events, + `ifndef THREADS1 + input [0:20] slice_ic_t1_perf_events, + `endif + output [0:31] spr_cp_perf_event_mux_ctrls, + + output [64-`GPR_WIDTH:51] spr_ivpr, + output [64-`GPR_WIDTH:51] spr_givpr, + + output [62-`EFF_IFAR_ARCH:61] spr_iac1, + output [62-`EFF_IFAR_ARCH:61] spr_iac2, + output [62-`EFF_IFAR_ARCH:61] spr_iac3, + output [62-`EFF_IFAR_ARCH:61] spr_iac4, + + output [0:`THREADS-1] spr_cpcr_we, + + output [0:4] spr_t0_cpcr2_fx0_cnt, + output [0:4] spr_t0_cpcr2_fx1_cnt, + output [0:4] spr_t0_cpcr2_lq_cnt, + output [0:4] spr_t0_cpcr2_sq_cnt, + output [0:4] spr_t0_cpcr3_fu0_cnt, + output [0:4] spr_t0_cpcr3_fu1_cnt, + output [0:6] spr_t0_cpcr3_cp_cnt, + output [0:4] spr_t0_cpcr4_fx0_cnt, + output [0:4] spr_t0_cpcr4_fx1_cnt, + output [0:4] spr_t0_cpcr4_lq_cnt, + output [0:4] spr_t0_cpcr4_sq_cnt, + output [0:4] spr_t0_cpcr5_fu0_cnt, + output [0:4] spr_t0_cpcr5_fu1_cnt, + output [0:6] spr_t0_cpcr5_cp_cnt, + `ifndef THREADS1 + output [0:4] spr_t1_cpcr2_fx0_cnt, + output [0:4] spr_t1_cpcr2_fx1_cnt, + output [0:4] spr_t1_cpcr2_lq_cnt, + output [0:4] spr_t1_cpcr2_sq_cnt, + output [0:4] spr_t1_cpcr3_fu0_cnt, + output [0:4] spr_t1_cpcr3_fu1_cnt, + output [0:6] spr_t1_cpcr3_cp_cnt, + output [0:4] spr_t1_cpcr4_fx0_cnt, + output [0:4] spr_t1_cpcr4_fx1_cnt, + output [0:4] spr_t1_cpcr4_lq_cnt, + output [0:4] spr_t1_cpcr4_sq_cnt, + output [0:4] spr_t1_cpcr5_fu0_cnt, + output [0:4] spr_t1_cpcr5_fu1_cnt, + output [0:6] spr_t1_cpcr5_cp_cnt, + `endif + output [0:4] spr_cpcr0_fx0_cnt, + output [0:4] spr_cpcr0_fx1_cnt, + output [0:4] spr_cpcr0_lq_cnt, + output [0:4] spr_cpcr0_sq_cnt, + output [0:4] spr_cpcr1_fu0_cnt, + output [0:4] spr_cpcr1_fu1_cnt, + + output [0:`THREADS-1] spr_high_pri_mask, + output [0:`THREADS-1] spr_med_pri_mask, + output [0:5] spr_t0_low_pri_count, +`ifndef THREADS1 + output [0:5] spr_t1_low_pri_count, +`endif + + input [0:`THREADS-1] iu_spr_eheir_update, + input [0:31] iu_spr_t0_eheir, + `ifndef THREADS1 + input [0:31] iu_spr_t1_eheir, + `endif + + input spr_scan_in, + output spr_scan_out, + + //---Performance + input pc_iu_event_bus_enable, + input [0:2] pc_iu_event_count_mode, + input [0:4*`THREADS-1] event_bus_in, + output [0:4*`THREADS-1] event_bus_out, + + //---Debug + (* pin_data ="PIN_FUNCTION=/SCAN_IN/" *) + input dbg1_scan_in, + (* pin_data ="PIN_FUNCTION=/SCAN_OUT/" *) + output dbg1_scan_out, + + input pc_iu_trace_bus_enable, + input [0:10] pc_iu_debug_mux1_ctrls, + + input [0:31] debug_bus_in, + output [0:31] debug_bus_out, + input [0:3] coretrace_ctrls_in, + output [0:3] coretrace_ctrls_out +); + + wire [0:`THREADS-1] bp_ic_iu2_redirect; + wire [0:`THREADS-1] bp_ic_iu3_redirect; + wire [0:`THREADS-1] bp_ic_iu4_redirect; + wire [62-`EFF_IFAR_WIDTH:61] bp_ic_redirect_ifar[0:`THREADS-1]; + wire [0:`THREADS-1] ic_bp_iu0_val; + wire [50:59] ic_bp_iu0_ifar; + wire [0:2] ic_bp_iu2_error; + + wire [0:3] ic_bp_iu2_val[0:`THREADS-1]; + wire [62-`EFF_IFAR_WIDTH:61] ic_bp_iu2_ifar; + wire ic_bp_iu2_2ucode; + wire ic_bp_iu2_2ucode_type; + wire [0:`THREADS-1] ic_bp_iu2_flush; + wire [0:`THREADS-1] ic_bp_iu3_flush; + wire [0:35] ic_bp_iu2_0_instr; + wire [0:35] ic_bp_iu2_1_instr; + wire [0:35] ic_bp_iu2_2_instr; + wire [0:35] ic_bp_iu2_3_instr; + wire ic_bp_iu3_ecc_err; + wire [0:`THREADS-1] uc_ic_hold; + wire [0:`THREADS-1] uc_iu4_flush; + wire [62-`EFF_IFAR_WIDTH:61] uc_iu4_flush_ifar[0:`THREADS-1]; + + wire [0:3] spr_ic_bp_config; + wire [0:5] spr_bp_config; + wire [0:1] spr_bp_size; + + wire spr_ic_idir_read; + wire [0:1] spr_ic_idir_way; + wire [51:57] spr_ic_idir_row; + wire ic_spr_idir_done; + wire [0:2] ic_spr_idir_lru; + wire [0:3] ic_spr_idir_parity; + wire ic_spr_idir_endian; + wire ic_spr_idir_valid; + wire [0:28] ic_spr_idir_tag; + wire spr_ic_icbi_ack_en; + wire spr_ic_cls; + wire spr_ic_clockgate_dis; + wire spr_ic_prefetch_dis; + wire spr_ic_ierat_byp_dis; + wire [0:47] spr_perf_event_mux_ctrls; + + wire d_mode; + wire mpw2_b; + + wire [0:9] iu0_bh0_rd_addr_int[0:`THREADS-1]; + wire [0:9] iu0_bh1_rd_addr_int[0:`THREADS-1]; + wire [0:8] iu0_bh2_rd_addr_int[0:`THREADS-1]; + wire [0:`THREADS-1] iu0_bh0_rd_act_int; + wire [0:`THREADS-1] iu0_bh1_rd_act_int; + wire [0:`THREADS-1] iu0_bh2_rd_act_int; + wire [0:1] ex5_bh0_wr_data_int[0:`THREADS-1]; + wire [0:1] ex5_bh1_wr_data_int[0:`THREADS-1]; + wire ex5_bh2_wr_data_int[0:`THREADS-1]; + wire [0:9] ex5_bh0_wr_addr_int[0:`THREADS-1]; + wire [0:9] ex5_bh1_wr_addr_int[0:`THREADS-1]; + wire [0:8] ex5_bh2_wr_addr_int[0:`THREADS-1]; + wire [0:3] ex5_bh0_wr_act_int[0:`THREADS-1]; + wire [0:3] ex5_bh1_wr_act_int[0:`THREADS-1]; + wire [0:3] ex5_bh2_wr_act_int[0:`THREADS-1]; + wire [0:5] iu0_btb_rd_addr_int[0:`THREADS-1]; + wire [0:`THREADS-1] iu0_btb_rd_act_int; + wire [0:5] ex5_btb_wr_addr_int[0:`THREADS-1]; + wire [0:`THREADS-1] ex5_btb_wr_act_int; + wire [0:63] ex5_btb_wr_data_int[0:`THREADS-1]; + + wire [0:3] bp_ib_iu3_val_int[0:`THREADS-1]; + wire [62-`EFF_IFAR_WIDTH:61] bp_ib_iu3_ifar[0:`THREADS-1]; + wire [62-`EFF_IFAR_WIDTH:61] bp_ib_iu3_bta[0:`THREADS-1]; + wire [0:69] bp_ib_iu3_0_instr[0:`THREADS-1]; + wire [0:69] bp_ib_iu3_1_instr[0:`THREADS-1]; + wire [0:69] bp_ib_iu3_2_instr[0:`THREADS-1]; + wire [0:69] bp_ib_iu3_3_instr[0:`THREADS-1]; + + wire [0:`THREADS-1] spr_single_issue_int; + + wire [62-`EFF_IFAR_WIDTH:61] cp_bp_ifar[0:`THREADS-1]; + wire [0:1] cp_bp_bh0_hist[0:`THREADS-1]; + wire [0:1] cp_bp_bh1_hist[0:`THREADS-1]; + wire [0:1] cp_bp_bh2_hist[0:`THREADS-1]; + wire [0:1] cp_bp_bh[0:`THREADS-1]; + wire [62-`EFF_IFAR_WIDTH:61] cp_bp_bta[0:`THREADS-1]; + wire [0:9] cp_bp_gshare[0:`THREADS-1]; + wire [0:2] cp_bp_ls_ptr[0:`THREADS-1]; + wire [0:1] cp_bp_btb_hist[0:`THREADS-1]; + wire [43:61] cp_uc_flush_ifar[0:`THREADS-1]; + + wire [0:3] uc_ib_iu3_invalid[0:`THREADS-1]; + wire [0:1] uc_ib_val[0:`THREADS-1]; + wire [0:31] uc_ib_instr0[0:`THREADS-1]; + wire [0:31] uc_ib_instr1[0:`THREADS-1]; + wire [62-`EFF_IFAR_WIDTH:61] uc_ib_ifar0[0:`THREADS-1]; + wire [62-`EFF_IFAR_WIDTH:61] uc_ib_ifar1[0:`THREADS-1]; + wire [0:3] uc_ib_ext0[0:`THREADS-1]; + wire [0:3] uc_ib_ext1[0:`THREADS-1]; + + wire [0:31] unit_dbg_data0; + wire [0:31] unit_dbg_data1; + wire [0:31] unit_dbg_data2; + wire [0:31] unit_dbg_data3; + wire [0:31] unit_dbg_data4; + wire [0:31] unit_dbg_data5; + wire [0:31] unit_dbg_data6; + wire [0:31] unit_dbg_data7; + wire [0:31] unit_dbg_data8; + wire [0:31] unit_dbg_data9; + wire [0:31] unit_dbg_data10; + wire [0:31] unit_dbg_data11; + wire [0:31] unit_dbg_data12; + wire [0:31] unit_dbg_data13; + wire [0:31] unit_dbg_data14; + wire [0:31] unit_dbg_data15; + + wire vdd; + wire gnd; + + assign vdd = 1'b1; + assign gnd = 1'b0; + + assign iu_lq_spr_iucr0_icbi_ack = spr_ic_icbi_ack_en; + assign d_mode = 1'b0; + assign mpw2_b = 1'b1; + assign spr_single_issue = spr_single_issue_int; + assign spr_ic_ierat_byp_dis = 1'b0; + + iuq_spr iuq_spr0( + .vdd(vdd), + .gnd(gnd), + .iu_slowspr_val_in(iu_slowspr_val_in), + .iu_slowspr_rw_in(iu_slowspr_rw_in), + .iu_slowspr_etid_in(iu_slowspr_etid_in), + .iu_slowspr_addr_in(iu_slowspr_addr_in), + .iu_slowspr_data_in(iu_slowspr_data_in), + .iu_slowspr_done_in(iu_slowspr_done_in), + .iu_slowspr_val_out(iu_slowspr_val_out), + .iu_slowspr_rw_out(iu_slowspr_rw_out), + .iu_slowspr_etid_out(iu_slowspr_etid_out), + .iu_slowspr_addr_out(iu_slowspr_addr_out), + .iu_slowspr_data_out(iu_slowspr_data_out), + .iu_slowspr_done_out(iu_slowspr_done_out), + .cp_flush(cp_flush), + .spr_ic_bp_config(spr_ic_bp_config), + .spr_bp_config(spr_bp_config), + .spr_bp_size(spr_bp_size), + .spr_dec_mask(spr_dec_mask), + .spr_dec_match(spr_dec_match), + .spr_single_issue(spr_single_issue_int), + .iu_au_t0_config_iucr(iu_au_t0_config_iucr), + `ifndef THREADS1 + .iu_au_t1_config_iucr(iu_au_t1_config_iucr), + `endif + .spr_high_pri_mask(spr_high_pri_mask), + .spr_med_pri_mask(spr_med_pri_mask), + .spr_t0_low_pri_count(spr_t0_low_pri_count), + `ifndef THREADS1 + .spr_t1_low_pri_count(spr_t1_low_pri_count), + `endif + .xu_iu_raise_iss_pri(xu_iu_raise_iss_pri), + .xu_iu_pri_val(xu_iu_pri_val), + .xu_iu_pri(xu_iu_pri), + .spr_msr_gs(xu_iu_msr_gs), + .spr_msr_pr(xu_iu_msr_pr), + .spr_ivpr(spr_ivpr), + .spr_givpr(spr_givpr), + .spr_iac1(spr_iac1), + .spr_iac2(spr_iac2), + .spr_iac3(spr_iac3), + .spr_iac4(spr_iac4), + .spr_cpcr_we(spr_cpcr_we), + .spr_t0_cpcr2_fx0_cnt(spr_t0_cpcr2_fx0_cnt), + .spr_t0_cpcr2_fx1_cnt(spr_t0_cpcr2_fx1_cnt), + .spr_t0_cpcr2_lq_cnt(spr_t0_cpcr2_lq_cnt), + .spr_t0_cpcr2_sq_cnt(spr_t0_cpcr2_sq_cnt), + .spr_t0_cpcr3_fu0_cnt(spr_t0_cpcr3_fu0_cnt), + .spr_t0_cpcr3_fu1_cnt(spr_t0_cpcr3_fu1_cnt), + .spr_t0_cpcr3_cp_cnt(spr_t0_cpcr3_cp_cnt), + .spr_t0_cpcr4_fx0_cnt(spr_t0_cpcr4_fx0_cnt), + .spr_t0_cpcr4_fx1_cnt(spr_t0_cpcr4_fx1_cnt), + .spr_t0_cpcr4_lq_cnt(spr_t0_cpcr4_lq_cnt), + .spr_t0_cpcr4_sq_cnt(spr_t0_cpcr4_sq_cnt), + .spr_t0_cpcr5_fu0_cnt(spr_t0_cpcr5_fu0_cnt), + .spr_t0_cpcr5_fu1_cnt(spr_t0_cpcr5_fu1_cnt), + .spr_t0_cpcr5_cp_cnt(spr_t0_cpcr5_cp_cnt), + `ifndef THREADS1 + .spr_t1_cpcr2_fx0_cnt(spr_t1_cpcr2_fx0_cnt), + .spr_t1_cpcr2_fx1_cnt(spr_t1_cpcr2_fx1_cnt), + .spr_t1_cpcr2_lq_cnt(spr_t1_cpcr2_lq_cnt), + .spr_t1_cpcr2_sq_cnt(spr_t1_cpcr2_sq_cnt), + .spr_t1_cpcr3_fu0_cnt(spr_t1_cpcr3_fu0_cnt), + .spr_t1_cpcr3_fu1_cnt(spr_t1_cpcr3_fu1_cnt), + .spr_t1_cpcr3_cp_cnt(spr_t1_cpcr3_cp_cnt), + .spr_t1_cpcr4_fx0_cnt(spr_t1_cpcr4_fx0_cnt), + .spr_t1_cpcr4_fx1_cnt(spr_t1_cpcr4_fx1_cnt), + .spr_t1_cpcr4_lq_cnt(spr_t1_cpcr4_lq_cnt), + .spr_t1_cpcr4_sq_cnt(spr_t1_cpcr4_sq_cnt), + .spr_t1_cpcr5_fu0_cnt(spr_t1_cpcr5_fu0_cnt), + .spr_t1_cpcr5_fu1_cnt(spr_t1_cpcr5_fu1_cnt), + .spr_t1_cpcr5_cp_cnt(spr_t1_cpcr5_cp_cnt), + `endif + .spr_cpcr0_fx0_cnt(spr_cpcr0_fx0_cnt), + .spr_cpcr0_fx1_cnt(spr_cpcr0_fx1_cnt), + .spr_cpcr0_lq_cnt(spr_cpcr0_lq_cnt), + .spr_cpcr0_sq_cnt(spr_cpcr0_sq_cnt), + .spr_cpcr1_fu0_cnt(spr_cpcr1_fu0_cnt), + .spr_cpcr1_fu1_cnt(spr_cpcr1_fu1_cnt), + .iu_spr_eheir_update(iu_spr_eheir_update), + .iu_spr_t0_eheir(iu_spr_t0_eheir), + `ifndef THREADS1 + .iu_spr_t1_eheir(iu_spr_t1_eheir), + `endif + .spr_ic_idir_read(spr_ic_idir_read), + .spr_ic_idir_way(spr_ic_idir_way), + .spr_ic_idir_row(spr_ic_idir_row), + .ic_spr_idir_done(ic_spr_idir_done), + .ic_spr_idir_lru(ic_spr_idir_lru), + .ic_spr_idir_parity(ic_spr_idir_parity), + .ic_spr_idir_endian(ic_spr_idir_endian), + .ic_spr_idir_valid(ic_spr_idir_valid), + .ic_spr_idir_tag(ic_spr_idir_tag), + .spr_ic_icbi_ack_en(spr_ic_icbi_ack_en), + .spr_ic_cls(spr_ic_cls), + .spr_ic_clockgate_dis(spr_ic_clockgate_dis), + .spr_ic_prefetch_dis(spr_ic_prefetch_dis), + .spr_perf_event_mux_ctrls(spr_perf_event_mux_ctrls), + .spr_cp_perf_event_mux_ctrls(spr_cp_perf_event_mux_ctrls), + .nclk(nclk), + .pc_iu_sg_2(pc_iu_sg_2), + .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), + .clkoff_b(clkoff_b), + .act_dis(act_dis), + .tc_ac_ccflush_dc(tc_ac_ccflush_dc), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scan_in(spr_scan_in), + .scan_out(spr_scan_out) + ); + + + iuq_ic iuq_ic0( + .vcs(vdd), + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .tc_ac_ccflush_dc(tc_ac_ccflush_dc), + .tc_ac_scan_dis_dc_b(tc_ac_scan_dis_dc_b), + .tc_ac_scan_diag_dc(tc_ac_scan_diag_dc), + .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), + .pc_iu_func_slp_sl_thold_2(pc_iu_func_slp_sl_thold_2), + .pc_iu_func_nsl_thold_2(pc_iu_func_nsl_thold_2), + .pc_iu_cfg_slp_sl_thold_2(pc_iu_cfg_slp_sl_thold_2), + .pc_iu_regf_slp_sl_thold_2(pc_iu_regf_slp_sl_thold_2), + .pc_iu_time_sl_thold_2(pc_iu_time_sl_thold_2), + .pc_iu_abst_sl_thold_2(pc_iu_abst_sl_thold_2), + .pc_iu_abst_slp_sl_thold_2(pc_iu_abst_slp_sl_thold_2), + .pc_iu_repr_sl_thold_2(pc_iu_repr_sl_thold_2), + .pc_iu_ary_nsl_thold_2(pc_iu_ary_nsl_thold_2), + .pc_iu_ary_slp_nsl_thold_2(pc_iu_ary_slp_nsl_thold_2), + .pc_iu_func_slp_nsl_thold_2(pc_iu_func_slp_nsl_thold_2), + .pc_iu_bolt_sl_thold_2(pc_iu_bolt_sl_thold_2), + .pc_iu_sg_2(pc_iu_sg_2), + .pc_iu_fce_2(pc_iu_fce_2), + .clkoff_b(clkoff_b), + .act_dis(act_dis), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .g8t_clkoff_b(g8t_clkoff_b), + .g8t_d_mode(g8t_d_mode), + .g8t_delay_lclkr(g8t_delay_lclkr), + .g8t_mpw1_b(g8t_mpw1_b), + .g8t_mpw2_b(g8t_mpw2_b), + .g6t_clkoff_b(g6t_clkoff_b), + .g6t_act_dis(g6t_act_dis), + .g6t_d_mode(g6t_d_mode), + .g6t_delay_lclkr(g6t_delay_lclkr), + .g6t_mpw1_b(g6t_mpw1_b), + .g6t_mpw2_b(g6t_mpw2_b), + .cam_clkoff_b(cam_clkoff_b), + .cam_act_dis(cam_act_dis), + .cam_d_mode(cam_d_mode), + .cam_delay_lclkr(cam_delay_lclkr), + .cam_mpw1_b(cam_mpw1_b), + .cam_mpw2_b(cam_mpw2_b), + .func_scan_in(func_scan_in), + .func_scan_out(func_scan_out), + .ac_ccfg_scan_in(ac_ccfg_scan_in), + .ac_ccfg_scan_out(ac_ccfg_scan_out), + .time_scan_in(time_scan_in), + .time_scan_out(time_scan_out), + .repr_scan_in(repr_scan_in), + .repr_scan_out(repr_scan_out), + .abst_scan_in(abst_scan_in), + .abst_scan_out(abst_scan_out), + .regf_scan_in(regf_scan_in), + .regf_scan_out(regf_scan_out), + .iu_pc_err_icache_parity(iu_pc_err_icache_parity), + .iu_pc_err_icachedir_parity(iu_pc_err_icachedir_parity), + .iu_pc_err_icachedir_multihit(iu_pc_err_icachedir_multihit), + .iu_pc_err_ierat_multihit(iu_pc_err_ierat_multihit), + .iu_pc_err_ierat_parity(iu_pc_err_ierat_parity), + .pc_iu_inj_icache_parity(pc_iu_inj_icache_parity), + .pc_iu_inj_icachedir_parity(pc_iu_inj_icachedir_parity), + .pc_iu_inj_icachedir_multihit(pc_iu_inj_icachedir_multihit), + .pc_iu_abist_g8t_wenb(pc_iu_abist_g8t_wenb), + .pc_iu_abist_g8t1p_renb_0(pc_iu_abist_g8t1p_renb_0), + .pc_iu_abist_di_0(pc_iu_abist_di_0), + .pc_iu_abist_g8t_bw_1(pc_iu_abist_g8t_bw_1), + .pc_iu_abist_g8t_bw_0(pc_iu_abist_g8t_bw_0), + .pc_iu_abist_waddr_0(pc_iu_abist_waddr_0), + .pc_iu_abist_raddr_0(pc_iu_abist_raddr_0), + .pc_iu_abist_ena_dc(pc_iu_abist_ena_dc), + .pc_iu_abist_wl128_comp_ena(pc_iu_abist_wl128_comp_ena), + .pc_iu_abist_raw_dc_b(pc_iu_abist_raw_dc_b), + .pc_iu_abist_g8t_dcomp(pc_iu_abist_g8t_dcomp), + .pc_iu_abist_g6t_bw(pc_iu_abist_g6t_bw), + .pc_iu_abist_di_g6t_2r(pc_iu_abist_di_g6t_2r), + .pc_iu_abist_wl512_comp_ena(pc_iu_abist_wl512_comp_ena), + .pc_iu_abist_dcomp_g6t_2r(pc_iu_abist_dcomp_g6t_2r), + .pc_iu_abist_g6t_r_wb(pc_iu_abist_g6t_r_wb), + .an_ac_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc), + .an_ac_lbist_en_dc(an_ac_lbist_en_dc), + .an_ac_atpg_en_dc(an_ac_atpg_en_dc), + .an_ac_grffence_en_dc(an_ac_grffence_en_dc), + .pc_iu_bo_enable_3(pc_iu_bo_enable_3), + .pc_iu_bo_reset(pc_iu_bo_reset), + .pc_iu_bo_unload(pc_iu_bo_unload), + .pc_iu_bo_repair(pc_iu_bo_repair), + .pc_iu_bo_shdata(pc_iu_bo_shdata), + .pc_iu_bo_select(pc_iu_bo_select), + .iu_pc_bo_fail(iu_pc_bo_fail), + .iu_pc_bo_diagout(iu_pc_bo_diagout), + .lq_iu_icbi_val(lq_iu_icbi_val), + .lq_iu_icbi_addr(lq_iu_icbi_addr), + .iu_lq_icbi_complete(iu_lq_icbi_complete), + .lq_iu_ici_val(lq_iu_ici_val), + .pc_iu_init_reset(pc_iu_init_reset), + .xu_iu_val(xu_iu_val), + .xu_iu_is_eratre(xu_iu_is_eratre), + .xu_iu_is_eratwe(xu_iu_is_eratwe), + .xu_iu_is_eratsx(xu_iu_is_eratsx), + .xu_iu_is_eratilx(xu_iu_is_eratilx), + .cp_is_isync(cp_is_isync), + .cp_is_csync(cp_is_csync), + .xu_iu_ws(xu_iu_ws), + .xu_iu_ra_entry(xu_iu_ra_entry), + .xu_iu_rb(xu_iu_rb), + .xu_iu_rs_data(xu_iu_rs_data), + .iu_xu_ord_read_done(iu_xu_ord_read_done), + .iu_xu_ord_write_done(iu_xu_ord_write_done), + .iu_xu_ord_par_err(iu_xu_ord_par_err), + .iu_xu_ord_n_flush_req(iu_xu_ord_n_flush_req), + .xu_iu_msr_hv(xu_iu_msr_gs), + .xu_iu_msr_pr(xu_iu_msr_pr), + .xu_iu_msr_is(xu_iu_msr_is), + .xu_iu_hid_mmu_mode(xu_iu_hid_mmu_mode), + .xu_iu_spr_ccr2_ifrat(xu_iu_spr_ccr2_ifrat), + .xu_iu_spr_ccr2_ifratsc(xu_iu_spr_ccr2_ifratsc), + .xu_iu_xucr4_mmu_mchk(xu_iu_xucr4_mmu_mchk), + .iu_xu_ex5_data(iu_xu_ex5_data), + .iu_mm_ierat_req(iu_mm_ierat_req), + .iu_mm_ierat_req_nonspec(iu_mm_ierat_req_nonspec), + .iu_mm_ierat_epn(iu_mm_ierat_epn), + .iu_mm_ierat_thdid(iu_mm_ierat_thdid), + .iu_mm_ierat_state(iu_mm_ierat_state), + .iu_mm_ierat_tid(iu_mm_ierat_tid), + .iu_mm_ierat_flush(iu_mm_ierat_flush), + .iu_mm_perf_itlb(iu_mm_perf_itlb), + .mm_iu_ierat_rel_val(mm_iu_ierat_rel_val), + .mm_iu_ierat_rel_data(mm_iu_ierat_rel_data), + .mm_iu_t0_ierat_pid(mm_iu_t0_ierat_pid), + .mm_iu_t0_ierat_mmucr0(mm_iu_t0_ierat_mmucr0), + `ifndef THREADS1 + .mm_iu_t1_ierat_pid(mm_iu_t1_ierat_pid), + .mm_iu_t1_ierat_mmucr0(mm_iu_t1_ierat_mmucr0), + `endif + .iu_mm_ierat_mmucr0(iu_mm_ierat_mmucr0), + .iu_mm_ierat_mmucr0_we(iu_mm_ierat_mmucr0_we), + .mm_iu_ierat_mmucr1(mm_iu_ierat_mmucr1), + .iu_mm_ierat_mmucr1(iu_mm_ierat_mmucr1), + .iu_mm_ierat_mmucr1_we(iu_mm_ierat_mmucr1_we), + .mm_iu_ierat_snoop_coming(mm_iu_ierat_snoop_coming), + .mm_iu_ierat_snoop_val(mm_iu_ierat_snoop_val), + .mm_iu_ierat_snoop_attr(mm_iu_ierat_snoop_attr), + .mm_iu_ierat_snoop_vpn(mm_iu_ierat_snoop_vpn), + .iu_mm_ierat_snoop_ack(iu_mm_ierat_snoop_ack), + .mm_iu_hold_req(mm_iu_hold_req), + .mm_iu_hold_done(mm_iu_hold_done), + .mm_iu_bus_snoop_hold_req(mm_iu_bus_snoop_hold_req), + .mm_iu_bus_snoop_hold_done(mm_iu_bus_snoop_hold_done), + .pc_iu_ram_active(pc_iu_ram_active), + .pc_iu_pm_fetch_halt(pc_iu_pm_fetch_halt), + .xu_iu_run_thread(xu_iu_run_thread), + .cp_ic_stop(cp_ic_stop), + .xu_iu_msr_cm(xu_iu_msr_cm), + .iu_flush(iu_flush), + .br_iu_redirect(br_iu_redirect), + .br_iu_bta(br_iu_bta), + .cp_flush(cp_flush), + .cp_flush_into_uc(cp_flush_into_uc), + .cp_iu0_t0_flush_ifar(cp_iu0_t0_flush_ifar), + `ifndef THREADS1 + .cp_iu0_t1_flush_ifar(cp_iu0_t1_flush_ifar), + `endif + .cp_iu0_flush_2ucode(cp_iu0_flush_2ucode), + .cp_iu0_flush_2ucode_type(cp_iu0_flush_2ucode_type), + .cp_iu0_flush_nonspec(cp_iu0_flush_nonspec), + .ic_cp_nonspec_hit(ic_cp_nonspec_hit), + .an_ac_back_inv(an_ac_back_inv), + .an_ac_back_inv_addr(an_ac_back_inv_addr), + .an_ac_back_inv_target(an_ac_back_inv_target), + .spr_ic_bp_config(spr_ic_bp_config), + .spr_ic_cls(spr_ic_cls), + .spr_ic_prefetch_dis(spr_ic_prefetch_dis), + .spr_ic_ierat_byp_dis(spr_ic_ierat_byp_dis), + .spr_ic_idir_read(spr_ic_idir_read), + .spr_ic_idir_way(spr_ic_idir_way), + .spr_ic_idir_row(spr_ic_idir_row), + .ic_spr_idir_done(ic_spr_idir_done), + .ic_spr_idir_lru(ic_spr_idir_lru), + .ic_spr_idir_parity(ic_spr_idir_parity), + .ic_spr_idir_endian(ic_spr_idir_endian), + .ic_spr_idir_valid(ic_spr_idir_valid), + .ic_spr_idir_tag(ic_spr_idir_tag), + .iu_lq_request(iu_lq_request), + .iu_lq_ctag(iu_lq_ctag), + .iu_lq_ra(iu_lq_ra), + .iu_lq_wimge(iu_lq_wimge), + .iu_lq_userdef(iu_lq_userdef), + .cp_async_block(cp_async_block), + .iu_mm_lmq_empty(iu_mm_lmq_empty), + .iu_xu_icache_quiesce(iu_xu_icache_quiesce), + .iu_pc_icache_quiesce(iu_pc_icache_quiesce), + .an_ac_reld_data_vld(an_ac_reld_data_vld), + .an_ac_reld_core_tag(an_ac_reld_core_tag), + .an_ac_reld_qw(an_ac_reld_qw), + .an_ac_reld_data(an_ac_reld_data), + .an_ac_reld_ecc_err(an_ac_reld_ecc_err), + .an_ac_reld_ecc_err_ue(an_ac_reld_ecc_err_ue), + .bp_ic_iu2_redirect(bp_ic_iu2_redirect), + .bp_ic_iu3_redirect(bp_ic_iu3_redirect), + .bp_ic_iu4_redirect(bp_ic_iu4_redirect), + .bp_ic_t0_redirect_ifar(bp_ic_redirect_ifar[0]), + `ifndef THREADS1 + .bp_ic_t1_redirect_ifar(bp_ic_redirect_ifar[1]), + `endif + .ic_bp_iu0_val(ic_bp_iu0_val), + .ic_bp_iu0_ifar(ic_bp_iu0_ifar), + .ic_bp_iu2_t0_val(ic_bp_iu2_val[0]), + `ifndef THREADS1 + .ic_bp_iu2_t1_val(ic_bp_iu2_val[1]), + `endif + .ic_bp_iu2_ifar(ic_bp_iu2_ifar), + .ic_bp_iu2_2ucode(ic_bp_iu2_2ucode), + .ic_bp_iu2_2ucode_type(ic_bp_iu2_2ucode_type), + .ic_bp_iu2_error(ic_bp_iu2_error), + .ic_bp_iu2_flush(ic_bp_iu2_flush), + .ic_bp_iu3_flush(ic_bp_iu3_flush), + .ic_bp_iu2_0_instr(ic_bp_iu2_0_instr), + .ic_bp_iu2_1_instr(ic_bp_iu2_1_instr), + .ic_bp_iu2_2_instr(ic_bp_iu2_2_instr), + .ic_bp_iu2_3_instr(ic_bp_iu2_3_instr), + .ic_bp_iu3_ecc_err(ic_bp_iu3_ecc_err), + .ib_ic_t0_need_fetch(ib_ic_t0_need_fetch), + `ifndef THREADS1 + .ib_ic_t1_need_fetch(ib_ic_t1_need_fetch), + `endif + .uc_iu4_flush(uc_iu4_flush), + .uc_iu4_t0_flush_ifar(uc_iu4_flush_ifar[0]), + `ifndef THREADS1 + .uc_iu4_t1_flush_ifar(uc_iu4_flush_ifar[1]), + `endif + .uc_ic_hold(uc_ic_hold), + .pc_iu_event_bus_enable(pc_iu_event_bus_enable), + .pc_iu_event_count_mode(pc_iu_event_count_mode), + .spr_perf_event_mux_ctrls(spr_perf_event_mux_ctrls[0:24*`THREADS-1]), + .slice_ic_t0_perf_events(slice_ic_t0_perf_events), + `ifndef THREADS1 + .slice_ic_t1_perf_events(slice_ic_t1_perf_events), + `endif + .event_bus_in(event_bus_in), + .event_bus_out(event_bus_out) + ); + + + generate + begin : xhdl0 + genvar i; + for (i = 0; i < `THREADS; i = i + 1) + begin : bp_gen + iuq_bp iuq_bp0( + .iu2_0_bh0_rd_data(iu2_0_bh0_rd_data), + .iu2_1_bh0_rd_data(iu2_1_bh0_rd_data), + .iu2_2_bh0_rd_data(iu2_2_bh0_rd_data), + .iu2_3_bh0_rd_data(iu2_3_bh0_rd_data), + .iu2_0_bh1_rd_data(iu2_0_bh1_rd_data), + .iu2_1_bh1_rd_data(iu2_1_bh1_rd_data), + .iu2_2_bh1_rd_data(iu2_2_bh1_rd_data), + .iu2_3_bh1_rd_data(iu2_3_bh1_rd_data), + .iu2_0_bh2_rd_data(iu2_0_bh2_rd_data), + .iu2_1_bh2_rd_data(iu2_1_bh2_rd_data), + .iu2_2_bh2_rd_data(iu2_2_bh2_rd_data), + .iu2_3_bh2_rd_data(iu2_3_bh2_rd_data), + .iu0_bh0_rd_addr(iu0_bh0_rd_addr_int[i]), + .iu0_bh1_rd_addr(iu0_bh1_rd_addr_int[i]), + .iu0_bh2_rd_addr(iu0_bh2_rd_addr_int[i]), + .iu0_bh0_rd_act(iu0_bh0_rd_act_int[i]), + .iu0_bh1_rd_act(iu0_bh1_rd_act_int[i]), + .iu0_bh2_rd_act(iu0_bh2_rd_act_int[i]), + .ex5_bh0_wr_data(ex5_bh0_wr_data_int[i]), + .ex5_bh1_wr_data(ex5_bh1_wr_data_int[i]), + .ex5_bh2_wr_data(ex5_bh2_wr_data_int[i]), + .ex5_bh0_wr_addr(ex5_bh0_wr_addr_int[i]), + .ex5_bh1_wr_addr(ex5_bh1_wr_addr_int[i]), + .ex5_bh2_wr_addr(ex5_bh2_wr_addr_int[i]), + .ex5_bh0_wr_act(ex5_bh0_wr_act_int[i]), + .ex5_bh1_wr_act(ex5_bh1_wr_act_int[i]), + .ex5_bh2_wr_act(ex5_bh2_wr_act_int[i]), + .iu0_btb_rd_addr(iu0_btb_rd_addr_int[i]), + .iu0_btb_rd_act(iu0_btb_rd_act_int[i]), + .iu2_btb_rd_data(iu2_btb_rd_data), + .ex5_btb_wr_addr(ex5_btb_wr_addr_int[i]), + .ex5_btb_wr_act(ex5_btb_wr_act_int[i]), + .ex5_btb_wr_data(ex5_btb_wr_data_int[i]), + .ic_bp_iu0_val(ic_bp_iu0_val[i]), + .ic_bp_iu0_ifar(ic_bp_iu0_ifar), + .ic_bp_iu2_val(ic_bp_iu2_val[i]), + .ic_bp_iu2_ifar(ic_bp_iu2_ifar), + .ic_bp_iu2_error(ic_bp_iu2_error), + .ic_bp_iu2_2ucode(ic_bp_iu2_2ucode), + .ic_bp_iu2_flush(ic_bp_iu2_flush[i]), + .ic_bp_iu3_flush(ic_bp_iu3_flush[i]), + .ic_bp_iu2_0_instr(ic_bp_iu2_0_instr), + .ic_bp_iu2_1_instr(ic_bp_iu2_1_instr), + .ic_bp_iu2_2_instr(ic_bp_iu2_2_instr), + .ic_bp_iu2_3_instr(ic_bp_iu2_3_instr), + .ic_bp_iu3_ecc_err(ic_bp_iu3_ecc_err), + .bp_ib_iu3_val(bp_ib_iu3_val_int[i]), + .bp_ib_iu3_ifar(bp_ib_iu3_ifar[i]), + .bp_ib_iu3_bta(bp_ib_iu3_bta[i]), + .bp_ib_iu3_0_instr(bp_ib_iu3_0_instr[i]), + .bp_ib_iu3_1_instr(bp_ib_iu3_1_instr[i]), + .bp_ib_iu3_2_instr(bp_ib_iu3_2_instr[i]), + .bp_ib_iu3_3_instr(bp_ib_iu3_3_instr[i]), + .bp_ic_iu2_redirect(bp_ic_iu2_redirect[i]), + .bp_ic_iu3_redirect(bp_ic_iu3_redirect[i]), + .bp_ic_iu4_redirect(bp_ic_iu4_redirect[i]), + .bp_ic_redirect_ifar(bp_ic_redirect_ifar[i]), + .cp_bp_ifar(cp_bp_ifar[i]), + .cp_bp_val(cp_bp_val[i]), + .cp_bp_bh0_hist(cp_bp_bh0_hist[i]), + .cp_bp_bh1_hist(cp_bp_bh1_hist[i]), + .cp_bp_bh2_hist(cp_bp_bh2_hist[i]), + .cp_bp_br_pred(cp_bp_br_pred[i]), + .cp_bp_br_taken(cp_bp_br_taken[i]), + .cp_bp_bh_update(cp_bp_bh_update[i]), + .cp_bp_bcctr(cp_bp_bcctr[i]), + .cp_bp_bclr(cp_bp_bclr[i]), + .cp_bp_getNIA(cp_bp_getNIA[i]), + .cp_bp_group(cp_bp_group[i]), + .cp_bp_lk(cp_bp_lk[i]), + .cp_bp_bh(cp_bp_bh[i]), + .cp_bp_bta(cp_bp_bta[i]), + .cp_bp_gshare(cp_bp_gshare[i]), + .cp_bp_ls_ptr(cp_bp_ls_ptr[i]), + .cp_bp_btb_entry(cp_bp_btb_entry[i]), + .cp_bp_btb_hist(cp_bp_btb_hist[i]), + .br_iu_gshare(br_iu_gshare), + .br_iu_ls_ptr(br_iu_ls_ptr), + .br_iu_ls_data(br_iu_ls_data), + .br_iu_ls_update(br_iu_ls_update), + .iu_flush(iu_flush[i]), + .br_iu_redirect(br_iu_redirect[i]), + .cp_flush(cp_flush[i]), + .ib_ic_iu4_redirect(1'b0), + .uc_iu4_flush(uc_iu4_flush[i]), + .spr_bp_config(spr_bp_config), + .spr_bp_size(spr_bp_size), + .xu_iu_msr_de(xu_iu_msr_de[i]), + .xu_iu_dbcr0_icmp(xu_iu_dbcr0_icmp[i]), + .xu_iu_dbcr0_brt(xu_iu_dbcr0_brt[i]), + .xu_iu_iac1_en(xu_iu_iac1_en[i]), + .xu_iu_iac2_en(xu_iu_iac2_en[i]), + .xu_iu_iac3_en(xu_iu_iac3_en[i]), + .xu_iu_iac4_en(xu_iu_iac4_en[i]), + .lq_iu_spr_dbcr3_ivc(lq_iu_spr_dbcr3_ivc[i]), + .xu_iu_single_instr_mode(xu_iu_single_instr_mode[i]), + .spr_single_issue(spr_single_issue_int[i]), + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .pc_iu_sg_2(pc_iu_sg_2), + .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), + .clkoff_b(clkoff_b), + .act_dis(act_dis), + .tc_ac_ccflush_dc(tc_ac_ccflush_dc), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scan_in(bp_scan_in[2 * i:2 * i + 1]), + .scan_out(bp_scan_out[2 * i:2 * i + 1]) + ); + end + end + endgenerate + + +/* always @(iu0_bh0_rd_addr_int or iu0_bh0_rd_act_int or iu0_bh1_rd_addr_int or iu0_bh1_rd_act_int or iu0_bh2_rd_addr_int or iu0_bh2_rd_act_int or ex5_bh0_wr_data_int or ex5_bh0_wr_act_int or ex5_bh1_wr_data_int or ex5_bh1_wr_act_int or ex5_bh2_wr_data_int or ex5_bh2_wr_act_int or ex5_bh0_wr_addr_int or ex5_bh1_wr_addr_int or ex5_bh2_wr_addr_int or iu0_btb_rd_addr_int or iu0_btb_rd_act_int or ex5_btb_wr_addr_int or ex5_btb_wr_act_int or ex5_btb_wr_data_int or bp_ib_iu3_ifar or bp_ib_iu3_val_int or bp_ib_iu3_bta or bp_ib_iu3_0_instr or bp_ib_iu3_1_instr or bp_ib_iu3_2_instr or bp_ib_iu3_3_instr) +*/ + always @ (*) + begin: or_proc + reg [0:9] iu0_bh0_rd_addr_calc; + reg [0:9] iu0_bh1_rd_addr_calc; + reg [0:8] iu0_bh2_rd_addr_calc; + reg [0:1] ex5_bh0_wr_data_calc; + reg [0:1] ex5_bh1_wr_data_calc; + reg ex5_bh2_wr_data_calc; + reg [0:9] ex5_bh0_wr_addr_calc; + reg [0:9] ex5_bh1_wr_addr_calc; + reg [0:8] ex5_bh2_wr_addr_calc; + reg [0:5] iu0_btb_rd_addr_calc; + reg [0:5] ex5_btb_wr_addr_calc; + reg [0:63] ex5_btb_wr_data_calc; + reg [0:3] ex5_bh0_wr_act_calc; + reg [0:3] ex5_bh1_wr_act_calc; + reg [0:3] ex5_bh2_wr_act_calc; + reg ex5_btb_wr_act_calc; + reg iu0_bh0_rd_act_calc; + reg iu0_bh1_rd_act_calc; + reg iu0_bh2_rd_act_calc; + reg iu0_btb_rd_act_calc; + //(* analysis_not_referenced="true" *) + integer i; + + iu0_bh0_rd_addr_calc = 10'b0; + iu0_bh1_rd_addr_calc = 10'b0; + iu0_bh2_rd_addr_calc = 9'b0; + ex5_bh0_wr_data_calc = 2'b0; + ex5_bh1_wr_data_calc = 2'b0; + ex5_bh2_wr_data_calc = 1'b0; + ex5_bh0_wr_addr_calc = 10'b0; + ex5_bh1_wr_addr_calc = 10'b0; + ex5_bh2_wr_addr_calc = 9'b0; + iu0_btb_rd_addr_calc = 6'b0; + ex5_btb_wr_addr_calc = 6'b0; + ex5_btb_wr_data_calc = 64'b0; + ex5_bh0_wr_act_calc = 4'b0; + ex5_bh1_wr_act_calc = 4'b0; + ex5_bh2_wr_act_calc = 4'b0; + ex5_btb_wr_act_calc = 1'b0; + iu0_bh0_rd_act_calc = 1'b0; + iu0_bh1_rd_act_calc = 1'b0; + iu0_bh2_rd_act_calc = 1'b0; + iu0_btb_rd_act_calc = 1'b0; + + for (i = 0; i < `THREADS; i = i + 1) + begin + + iu0_bh0_rd_addr_calc = iu0_bh0_rd_addr_calc | (iu0_bh0_rd_addr_int[i] & {10{ic_bp_iu0_val[i]}}); + iu0_bh1_rd_addr_calc = iu0_bh1_rd_addr_calc | (iu0_bh1_rd_addr_int[i] & {10{ic_bp_iu0_val[i]}}); + iu0_bh2_rd_addr_calc = iu0_bh2_rd_addr_calc | (iu0_bh2_rd_addr_int[i] & {9{ic_bp_iu0_val[i]}}); + ex5_bh0_wr_data_calc = ex5_bh0_wr_data_calc | (ex5_bh0_wr_data_int[i] & {2{ (|(ex5_bh0_wr_act_int[i]))}}); + ex5_bh1_wr_data_calc = ex5_bh1_wr_data_calc | (ex5_bh1_wr_data_int[i] & {2{ (|(ex5_bh1_wr_act_int[i]))}}); + ex5_bh2_wr_data_calc = ex5_bh2_wr_data_calc | (ex5_bh2_wr_data_int[i] & {1{ (|(ex5_bh2_wr_act_int[i]))}}); + ex5_bh0_wr_addr_calc = ex5_bh0_wr_addr_calc | (ex5_bh0_wr_addr_int[i] & {10{ (|(ex5_bh0_wr_act_int[i]))}}); + ex5_bh1_wr_addr_calc = ex5_bh1_wr_addr_calc | (ex5_bh1_wr_addr_int[i] & {10{ (|(ex5_bh1_wr_act_int[i]))}}); + ex5_bh2_wr_addr_calc = ex5_bh2_wr_addr_calc | (ex5_bh2_wr_addr_int[i] & {9{ (|(ex5_bh2_wr_act_int[i]))}}); + iu0_btb_rd_addr_calc = iu0_btb_rd_addr_calc | (iu0_btb_rd_addr_int[i] & {6{ic_bp_iu0_val[i]}}); + ex5_btb_wr_addr_calc = ex5_btb_wr_addr_calc | (ex5_btb_wr_addr_int[i] & {6{ex5_btb_wr_act_int[i]}}); + ex5_btb_wr_data_calc = ex5_btb_wr_data_calc | (ex5_btb_wr_data_int[i] & {64{ex5_btb_wr_act_int[i]}}); + + ex5_bh0_wr_act_calc = (ex5_bh0_wr_act_calc & {4{~|(ex5_bh0_wr_act_int[i])}}) | ((ex5_bh0_wr_act_int[i]) & {4{~|(ex5_bh0_wr_act_calc)}}); + ex5_bh1_wr_act_calc = (ex5_bh1_wr_act_calc & {4{~|(ex5_bh1_wr_act_int[i])}}) | ((ex5_bh1_wr_act_int[i]) & {4{~|(ex5_bh1_wr_act_calc)}}); + ex5_bh2_wr_act_calc = (ex5_bh2_wr_act_calc & {4{~|(ex5_bh2_wr_act_int[i])}}) | ((ex5_bh2_wr_act_int[i]) & {4{~|(ex5_bh2_wr_act_calc)}}); + + ex5_btb_wr_act_calc = ex5_btb_wr_act_calc ^ ex5_btb_wr_act_int[i]; + iu0_bh0_rd_act_calc = iu0_bh0_rd_act_calc ^ iu0_bh0_rd_act_int[i]; + iu0_bh1_rd_act_calc = iu0_bh1_rd_act_calc ^ iu0_bh1_rd_act_int[i]; + iu0_bh2_rd_act_calc = iu0_bh2_rd_act_calc ^ iu0_bh2_rd_act_int[i]; + iu0_btb_rd_act_calc = iu0_btb_rd_act_calc ^ iu0_btb_rd_act_int[i]; + + end + iu0_bh0_rd_addr = iu0_bh0_rd_addr_calc; + iu0_bh1_rd_addr = iu0_bh1_rd_addr_calc; + iu0_bh2_rd_addr = iu0_bh2_rd_addr_calc; + ex5_bh0_wr_data = ex5_bh0_wr_data_calc; + ex5_bh1_wr_data = ex5_bh1_wr_data_calc; + ex5_bh2_wr_data = ex5_bh2_wr_data_calc; + ex5_bh0_wr_addr = ex5_bh0_wr_addr_calc; + ex5_bh1_wr_addr = ex5_bh1_wr_addr_calc; + ex5_bh2_wr_addr = ex5_bh2_wr_addr_calc; + iu0_btb_rd_addr = iu0_btb_rd_addr_calc; + ex5_btb_wr_addr = ex5_btb_wr_addr_calc; + ex5_btb_wr_data = ex5_btb_wr_data_calc; + ex5_bh0_wr_act = ex5_bh0_wr_act_calc; + ex5_bh1_wr_act = ex5_bh1_wr_act_calc; + ex5_bh2_wr_act = ex5_bh2_wr_act_calc; + ex5_btb_wr_act = ex5_btb_wr_act_calc; + iu0_bh0_rd_act = iu0_bh0_rd_act_calc; + iu0_bh1_rd_act = iu0_bh1_rd_act_calc; + iu0_bh2_rd_act = iu0_bh2_rd_act_calc; + iu0_btb_rd_act = iu0_btb_rd_act_calc; + end + + // For Verilog lack of 2-D ports + assign bp_ib_iu3_t0_val = bp_ib_iu3_val_int[0]; + assign bp_ib_iu3_t0_ifar = bp_ib_iu3_ifar[0]; + assign bp_ib_iu3_t0_bta = bp_ib_iu3_bta[0]; + assign bp_ib_iu3_t0_0_instr = bp_ib_iu3_0_instr[0]; + assign bp_ib_iu3_t0_1_instr = bp_ib_iu3_1_instr[0]; + assign bp_ib_iu3_t0_2_instr = bp_ib_iu3_2_instr[0]; + assign bp_ib_iu3_t0_3_instr = bp_ib_iu3_3_instr[0]; + assign cp_bp_ifar[0] = cp_bp_t0_ifar; + assign cp_bp_bh0_hist[0] = cp_bp_t0_bh0_hist; + assign cp_bp_bh1_hist[0] = cp_bp_t0_bh1_hist; + assign cp_bp_bh2_hist[0] = cp_bp_t0_bh2_hist; + assign cp_bp_bh[0] = cp_bp_t0_bh; + assign cp_bp_bta[0] = cp_bp_t0_bta; + assign cp_bp_gshare[0] = cp_bp_t0_gshare; + assign cp_bp_ls_ptr[0] = cp_bp_t0_ls_ptr; + assign cp_bp_btb_hist[0] = cp_bp_t0_btb_hist; + assign cp_uc_flush_ifar[0] = cp_uc_t0_flush_ifar; + assign uc_ib_iu3_t0_invalid = uc_ib_iu3_invalid[0]; + assign uc_ib_t0_val = uc_ib_val[0]; + assign uc_ib_t0_instr0 = uc_ib_instr0[0]; + assign uc_ib_t0_instr1 = uc_ib_instr1[0]; + assign uc_ib_t0_ifar0 = uc_ib_ifar0[0]; + assign uc_ib_t0_ifar1 = uc_ib_ifar1[0]; + assign uc_ib_t0_ext0 = uc_ib_ext0[0]; + assign uc_ib_t0_ext1 = uc_ib_ext1[0]; + `ifndef THREADS1 + assign bp_ib_iu3_t1_val = bp_ib_iu3_val_int[1]; + assign bp_ib_iu3_t1_ifar = bp_ib_iu3_ifar[1]; + assign bp_ib_iu3_t1_bta = bp_ib_iu3_bta[1]; + assign bp_ib_iu3_t1_0_instr = bp_ib_iu3_0_instr[1]; + assign bp_ib_iu3_t1_1_instr = bp_ib_iu3_1_instr[1]; + assign bp_ib_iu3_t1_2_instr = bp_ib_iu3_2_instr[1]; + assign bp_ib_iu3_t1_3_instr = bp_ib_iu3_3_instr[1]; + assign cp_bp_ifar[1] = cp_bp_t1_ifar; + assign cp_bp_bh0_hist[1] = cp_bp_t1_bh0_hist; + assign cp_bp_bh1_hist[1] = cp_bp_t1_bh1_hist; + assign cp_bp_bh2_hist[1] = cp_bp_t1_bh2_hist; + assign cp_bp_bh[1] = cp_bp_t1_bh; + assign cp_bp_bta[1] = cp_bp_t1_bta; + assign cp_bp_gshare[1] = cp_bp_t1_gshare; + assign cp_bp_ls_ptr[1] = cp_bp_t1_ls_ptr; + assign cp_bp_btb_hist[1] = cp_bp_t1_btb_hist; + assign cp_uc_flush_ifar[1] = cp_uc_t1_flush_ifar; + assign uc_ib_iu3_t1_invalid = uc_ib_iu3_invalid[1]; + assign uc_ib_t1_val = uc_ib_val[1]; + assign uc_ib_t1_instr0 = uc_ib_instr0[1]; + assign uc_ib_t1_instr1 = uc_ib_instr1[1]; + assign uc_ib_t1_ifar0 = uc_ib_ifar0[1]; + assign uc_ib_t1_ifar1 = uc_ib_ifar1[1]; + assign uc_ib_t1_ext0 = uc_ib_ext0[1]; + assign uc_ib_t1_ext1 = uc_ib_ext1[1]; + `endif + + + iuq_ram iuq_ram0( + .pc_iu_ram_instr(pc_iu_ram_instr), + .pc_iu_ram_instr_ext(pc_iu_ram_instr_ext), + .pc_iu_ram_issue(pc_iu_ram_issue), + .pc_iu_ram_active(pc_iu_ram_active), + .iu_pc_ram_done(iu_pc_ram_done), + .cp_flush(cp_flush), + .ib_rm_rdy(ib_rm_rdy), + .rm_ib_iu3_val(rm_ib_iu3_val), + .rm_ib_iu3_instr(rm_ib_iu3_instr), + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .pc_iu_sg_2(pc_iu_sg_2), + .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), + .clkoff_b(clkoff_b), + .act_dis(act_dis), + .tc_ac_ccflush_dc(tc_ac_ccflush_dc), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scan_in(ram_scan_in), + .scan_out(ram_scan_out) + ); + + generate + begin : xhdl1 + genvar i; + for (i = 0; i < `THREADS; i = i + 1) + begin : uc_gen + iuq_uc iuq_uc0( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), + .pc_iu_sg_2(pc_iu_sg_2), + .tc_ac_ccflush_dc(tc_ac_ccflush_dc), + .clkoff_b(clkoff_b), + .act_dis(act_dis), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scan_in(uc_scan_in[i]), + .scan_out(uc_scan_out[i]), + .iu_pc_err_ucode_illegal(iu_pc_err_ucode_illegal[i]), + .xu_iu_ucode_xer_val(xu_iu_ucode_xer_val[i]), + .xu_iu_ucode_xer(xu_iu_ucode_xer), + .iu_flush(iu_flush[i]), + .br_iu_redirect(br_iu_redirect[i]), + .cp_flush_into_uc(cp_flush_into_uc[i]), + .cp_uc_np1_flush(cp_uc_np1_flush[i]), + .cp_uc_flush_ifar(cp_uc_flush_ifar[i]), + .cp_uc_credit_free(cp_uc_credit_free[i]), + .cp_flush(cp_flush[i]), + .uc_ic_hold(uc_ic_hold[i]), + .uc_iu4_flush(uc_iu4_flush[i]), + .uc_iu4_flush_ifar(uc_iu4_flush_ifar[i]), + .ic_bp_iu2_val(ic_bp_iu2_val[i]), + .ic_bp_iu2_ifar(ic_bp_iu2_ifar), + .ic_bp_iu2_2ucode(ic_bp_iu2_2ucode), + .ic_bp_iu2_2ucode_type(ic_bp_iu2_2ucode_type), + .ic_bp_iu2_error(ic_bp_iu2_error[0]), + .ic_bp_iu2_flush(ic_bp_iu2_flush[i]), + .ic_bp_iu3_flush(ic_bp_iu3_flush[i]), + .ic_bp_iu3_ecc_err(ic_bp_iu3_ecc_err), + .ic_bp_iu2_0_instr(ic_bp_iu2_0_instr[0:33]), + .ic_bp_iu2_1_instr(ic_bp_iu2_1_instr[0:33]), + .ic_bp_iu2_2_instr(ic_bp_iu2_2_instr[0:33]), + .ic_bp_iu2_3_instr(ic_bp_iu2_3_instr[0:33]), + .bp_ib_iu3_val(bp_ib_iu3_val_int[i]), + .ib_uc_rdy(ib_uc_rdy[i]), + .uc_ib_iu3_invalid(uc_ib_iu3_invalid[i]), + .uc_ib_iu3_flush_all(uc_ib_iu3_flush_all[i]), + .uc_ib_val(uc_ib_val[i]), + .uc_ib_done(uc_ib_done[i]), + .uc_ib_instr0(uc_ib_instr0[i]), + .uc_ib_instr1(uc_ib_instr1[i]), + .uc_ib_ifar0(uc_ib_ifar0[i]), + .uc_ib_ifar1(uc_ib_ifar1[i]), + .uc_ib_ext0(uc_ib_ext0[i]), + .uc_ib_ext1(uc_ib_ext1[i]) + ); + end + end + endgenerate + + //??? Temp - Need to connect + assign unit_dbg_data0 = bp_ib_iu3_0_instr[0][0:31]; + assign unit_dbg_data1 = bp_ib_iu3_1_instr[0][0:31]; + assign unit_dbg_data2 = bp_ib_iu3_2_instr[0][0:31]; + assign unit_dbg_data3 = bp_ib_iu3_3_instr[0][0:31]; + assign unit_dbg_data4 = { {30-`EFF_IFAR_WIDTH{1'b0}}, bp_ib_iu3_ifar[0], 2'b0 }; + assign unit_dbg_data5 = { {30-`EFF_IFAR_WIDTH{1'b0}}, bp_ib_iu3_ifar[`THREADS-1], 2'b0 }; + assign unit_dbg_data6 = 32'b0; + assign unit_dbg_data7 = 32'b0; + assign unit_dbg_data8 = bp_ib_iu3_0_instr[`THREADS-1][0:31]; + assign unit_dbg_data9 = bp_ib_iu3_1_instr[`THREADS-1][0:31]; + assign unit_dbg_data10 = bp_ib_iu3_2_instr[`THREADS-1][0:31]; + assign unit_dbg_data11 = bp_ib_iu3_3_instr[`THREADS-1][0:31]; + assign unit_dbg_data12 = 32'b0; + assign unit_dbg_data13 = 32'b0; + assign unit_dbg_data14 = 32'b0; + assign unit_dbg_data15 = 32'b0; + + iuq_dbg iuq_dbg0( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .thold_2(pc_iu_func_slp_sl_thold_2), + .pc_iu_sg_2(pc_iu_sg_2), + .clkoff_b(clkoff_b), + .act_dis(act_dis), + .tc_ac_ccflush_dc(tc_ac_ccflush_dc), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .func_scan_in(dbg1_scan_in), + .func_scan_out(dbg1_scan_out), + .unit_dbg_data0(unit_dbg_data0), + .unit_dbg_data1(unit_dbg_data1), + .unit_dbg_data2(unit_dbg_data2), + .unit_dbg_data3(unit_dbg_data3), + .unit_dbg_data4(unit_dbg_data4), + .unit_dbg_data5(unit_dbg_data5), + .unit_dbg_data6(unit_dbg_data6), + .unit_dbg_data7(unit_dbg_data7), + .unit_dbg_data8(unit_dbg_data8), + .unit_dbg_data9(unit_dbg_data9), + .unit_dbg_data10(unit_dbg_data10), + .unit_dbg_data11(unit_dbg_data11), + .unit_dbg_data12(unit_dbg_data12), + .unit_dbg_data13(unit_dbg_data13), + .unit_dbg_data14(unit_dbg_data14), + .unit_dbg_data15(unit_dbg_data15), + .pc_iu_trace_bus_enable(pc_iu_trace_bus_enable), + .pc_iu_debug_mux_ctrls(pc_iu_debug_mux1_ctrls), + .debug_bus_in(debug_bus_in), + .debug_bus_out(debug_bus_out), + .coretrace_ctrls_in(coretrace_ctrls_in), + .coretrace_ctrls_out(coretrace_ctrls_out) + ); + +endmodule diff --git a/dev/verilog/work/iuq_ram.v b/dev/verilog/work/iuq_ram.v new file mode 100755 index 0000000..f1839f3 --- /dev/null +++ b/dev/verilog/work/iuq_ram.v @@ -0,0 +1,315 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// ********************************************************************* +// +// This is the ENTITY for iuq_ram +// +// ********************************************************************* + +module iuq_ram( + pc_iu_ram_instr, + pc_iu_ram_instr_ext, + pc_iu_ram_issue, + pc_iu_ram_active, + iu_pc_ram_done, + cp_flush, + ib_rm_rdy, + rm_ib_iu3_val, + rm_ib_iu3_instr, + vdd, + gnd, + nclk, + pc_iu_sg_2, + pc_iu_func_sl_thold_2, + clkoff_b, + act_dis, + tc_ac_ccflush_dc, + d_mode, + delay_lclkr, + mpw1_b, + mpw2_b, + scan_in, + scan_out +); +`include "tri_a2o.vh" +// parameter `EXPAND_TYPE = 2; +// parameter `THREADS = 2; // 0 = ibm umbra, 1 = xilinx, 2 = ibm mpg + input [0:31] pc_iu_ram_instr; + input [0:3] pc_iu_ram_instr_ext; + input pc_iu_ram_issue; + input [0:`THREADS-1] pc_iu_ram_active; + + input iu_pc_ram_done; + input [0:`THREADS-1] cp_flush; + + input [0:`THREADS-1] ib_rm_rdy; + + output [0:`THREADS-1] rm_ib_iu3_val; + output [0:35] rm_ib_iu3_instr; + + //pervasive + inout vdd; + inout gnd; + (* pin_data="PIN_FUNCTION=/G_CLK/" *) + input [0:`NCLK_WIDTH-1] nclk; + input pc_iu_sg_2; + input pc_iu_func_sl_thold_2; + input clkoff_b; + input act_dis; + input tc_ac_ccflush_dc; + input d_mode; + input delay_lclkr; + input mpw1_b; + input mpw2_b; + input scan_in; + + output scan_out; + + //-------------------------- + // components + //-------------------------- + + //-------------------------- + // constants + //-------------------------- + + //scan chain + parameter cp_flush_offset = 0; + parameter ram_val_offset = cp_flush_offset + `THREADS; + parameter ram_act_offset = ram_val_offset + `THREADS; + parameter ram_instr_offset = ram_act_offset + `THREADS; + parameter ram_done_offset = ram_instr_offset + 36; + parameter scan_right = ram_done_offset + 1 - 1; + + //-------------------------- + // signals + //-------------------------- + + wire tiup; + + wire ram_valid; + + wire [0:`THREADS-1] ram_val_d; + wire [0:`THREADS-1] ram_val_q; + wire [0:`THREADS-1] ram_act_d; + wire [0:`THREADS-1] ram_act_q; + wire [0:35] ram_instr_d; + wire [0:35] ram_instr_q; + wire ram_done_d; + wire ram_done_q; + + wire [0:`THREADS-1] cp_flush_d; + wire [0:`THREADS-1] cp_flush_q; + + wire pc_iu_func_sl_thold_1; + wire pc_iu_func_sl_thold_0; + wire pc_iu_func_sl_thold_0_b; + wire pc_iu_sg_1; + wire pc_iu_sg_0; + wire force_t; + + wire [0:scan_right] siv; + wire [0:scan_right] sov; + + assign tiup = 1'b1; + //assign tidn = 1'b0; + + //----------------------------------------------- + // logic + //----------------------------------------------- + assign cp_flush_d = cp_flush; + assign ram_done_d = iu_pc_ram_done; + + generate + begin : xhdl1 + genvar i; + for (i = 0; i <= `THREADS - 1; i = i + 1) + begin : issue_gating + assign ram_val_d[i] = (pc_iu_ram_active[i] & pc_iu_ram_issue) | (ram_val_q[i] & (~ib_rm_rdy[i])) | (cp_flush_q[i] & ram_act_d[i]); + assign ram_act_d[i] = (ram_done_q == 1'b1) ? 1'b0 : + (ram_val_q[i] == 1'b1) ? 1'b1 : + ram_act_q[i]; + end + end + endgenerate + + assign ram_valid = pc_iu_ram_issue; + assign ram_instr_d = {pc_iu_ram_instr, pc_iu_ram_instr_ext}; + + //----------------------------------------------- + // outputs + //----------------------------------------------- + + assign rm_ib_iu3_val = ram_val_q; + assign rm_ib_iu3_instr = ram_instr_q; + + //----------------------------------------------- + // latches + //----------------------------------------------- + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) cp_flush_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[cp_flush_offset:cp_flush_offset + `THREADS - 1]), + .scout(sov[cp_flush_offset:cp_flush_offset + `THREADS - 1]), + .din(cp_flush_d), + .dout(cp_flush_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) ram_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[ram_val_offset:ram_val_offset + `THREADS - 1]), + .scout(sov[ram_val_offset:ram_val_offset + `THREADS - 1]), + .din(ram_val_d), + .dout(ram_val_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) ram_act_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[ram_act_offset:ram_act_offset + `THREADS - 1]), + .scout(sov[ram_act_offset:ram_act_offset + `THREADS - 1]), + .din(ram_act_d), + .dout(ram_act_q) + ); + + + tri_rlmreg_p #(.WIDTH(36), .INIT(0)) ram_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ram_valid), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[ram_instr_offset:ram_instr_offset + 35]), + .scout(sov[ram_instr_offset:ram_instr_offset + 35]), + .din(ram_instr_d[0:35]), + .dout(ram_instr_q[0:35]) + ); + + + tri_rlmlatch_p #(.INIT(0)) ram_done_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[ram_done_offset]), + .scout(sov[ram_done_offset]), + .din(ram_done_d), + .dout(ram_done_q) + ); + + //----------------------------------------------- + // pervasive + //----------------------------------------------- + + + tri_plat #(.WIDTH(2)) perv_2to1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + .din({pc_iu_func_sl_thold_2,pc_iu_sg_2}), + .q({pc_iu_func_sl_thold_1,pc_iu_sg_1}) + ); + + + tri_plat #(.WIDTH(2)) perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + .din({pc_iu_func_sl_thold_1,pc_iu_sg_1}), + .q({pc_iu_func_sl_thold_0,pc_iu_sg_0}) + ); + + + tri_lcbor perv_lcbor( + .clkoff_b(clkoff_b), + .thold(pc_iu_func_sl_thold_0), + .sg(pc_iu_sg_0), + .act_dis(act_dis), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b) + ); + + //----------------------------------------------- + // scan + //----------------------------------------------- + + assign siv[0:scan_right] = {scan_in, sov[0:scan_right - 1]}; + assign scan_out = sov[scan_right]; + + +endmodule diff --git a/dev/verilog/work/iuq_rn.v b/dev/verilog/work/iuq_rn.v new file mode 100755 index 0000000..59fdce7 --- /dev/null +++ b/dev/verilog/work/iuq_rn.v @@ -0,0 +1,8983 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//******************************************************************** +//* +//* TITLE: +//* +//* NAME: iuq_rn.vhdl +//* +//********************************************************************* + +`include "tri_a2o.vh" + + +module iuq_rn( + inout vdd, + inout gnd, + input [0:`NCLK_WIDTH-1] nclk, + input pc_iu_func_sl_thold_2, // acts as reset for non-ibm types + input pc_iu_sg_2, + input clkoff_b, + input act_dis, + input tc_ac_ccflush_dc, + input d_mode, + input delay_lclkr, + input mpw1_b, + input mpw2_b, + input func_scan_in, + output func_scan_out, + + //----------------------------- + // SPR connections + //----------------------------- + input spr_high_pri_mask, + input spr_cpcr_we, + input [0:6] spr_cpcr3_cp_cnt, + input [0:6] spr_cpcr5_cp_cnt, + input spr_single_issue, + + //------------------------------- + // Performance interface with I$ + //------------------------------- + input pc_iu_event_bus_enable, + output perf_iu5_stall, + output perf_iu5_cpl_credit_stall, + output perf_iu5_gpr_credit_stall, + output perf_iu5_cr_credit_stall, + output perf_iu5_lr_credit_stall, + output perf_iu5_ctr_credit_stall, + output perf_iu5_xer_credit_stall, + output perf_iu5_br_hold_stall, + output perf_iu5_axu_hold_stall, + + //----------------------------- + // Inputs to rename from decode + //----------------------------- + input fdec_frn_iu5_i0_vld, + input [0:2] fdec_frn_iu5_i0_ucode, + input fdec_frn_iu5_i0_2ucode, + input fdec_frn_iu5_i0_fuse_nop, + input fdec_frn_iu5_i0_rte_lq, + input fdec_frn_iu5_i0_rte_sq, + input fdec_frn_iu5_i0_rte_fx0, + input fdec_frn_iu5_i0_rte_fx1, + input fdec_frn_iu5_i0_rte_axu0, + input fdec_frn_iu5_i0_rte_axu1, + input fdec_frn_iu5_i0_valop, + input fdec_frn_iu5_i0_ord, + input fdec_frn_iu5_i0_cord, + input [0:2] fdec_frn_iu5_i0_error, + input fdec_frn_iu5_i0_btb_entry, + input [0:1] fdec_frn_iu5_i0_btb_hist, + input fdec_frn_iu5_i0_bta_val, + input [0:19] fdec_frn_iu5_i0_fusion, + input fdec_frn_iu5_i0_spec, + input fdec_frn_iu5_i0_type_fp, + input fdec_frn_iu5_i0_type_ap, + input fdec_frn_iu5_i0_type_spv, + input fdec_frn_iu5_i0_type_st, + input fdec_frn_iu5_i0_async_block, + input fdec_frn_iu5_i0_np1_flush, + input fdec_frn_iu5_i0_core_block, + input fdec_frn_iu5_i0_isram, + input fdec_frn_iu5_i0_isload, + input fdec_frn_iu5_i0_isstore, + input [0:31] fdec_frn_iu5_i0_instr, + input [62-`EFF_IFAR_WIDTH:61] fdec_frn_iu5_i0_ifar, + input [62-`EFF_IFAR_WIDTH:61] fdec_frn_iu5_i0_bta, + input fdec_frn_iu5_i0_br_pred, + input fdec_frn_iu5_i0_bh_update, + input [0:1] fdec_frn_iu5_i0_bh0_hist, + input [0:1] fdec_frn_iu5_i0_bh1_hist, + input [0:1] fdec_frn_iu5_i0_bh2_hist, + input [0:17] fdec_frn_iu5_i0_gshare, + input [0:2] fdec_frn_iu5_i0_ls_ptr, + input fdec_frn_iu5_i0_match, + input [0:3] fdec_frn_iu5_i0_ilat, + input fdec_frn_iu5_i0_t1_v, + input [0:2] fdec_frn_iu5_i0_t1_t, + input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i0_t1_a, + input fdec_frn_iu5_i0_t2_v, + input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i0_t2_a, + input [0:2] fdec_frn_iu5_i0_t2_t, + input fdec_frn_iu5_i0_t3_v, + input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i0_t3_a, + input [0:2] fdec_frn_iu5_i0_t3_t, + input fdec_frn_iu5_i0_s1_v, + input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i0_s1_a, + input [0:2] fdec_frn_iu5_i0_s1_t, + input fdec_frn_iu5_i0_s2_v, + input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i0_s2_a, + input [0:2] fdec_frn_iu5_i0_s2_t, + input fdec_frn_iu5_i0_s3_v, + input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i0_s3_a, + input [0:2] fdec_frn_iu5_i0_s3_t, + + input fdec_frn_iu5_i1_vld, + input [0:2] fdec_frn_iu5_i1_ucode, + input fdec_frn_iu5_i1_fuse_nop, + input fdec_frn_iu5_i1_rte_lq, + input fdec_frn_iu5_i1_rte_sq, + input fdec_frn_iu5_i1_rte_fx0, + input fdec_frn_iu5_i1_rte_fx1, + input fdec_frn_iu5_i1_rte_axu0, + input fdec_frn_iu5_i1_rte_axu1, + input fdec_frn_iu5_i1_valop, + input fdec_frn_iu5_i1_ord, + input fdec_frn_iu5_i1_cord, + input [0:2] fdec_frn_iu5_i1_error, + input fdec_frn_iu5_i1_btb_entry, + input [0:1] fdec_frn_iu5_i1_btb_hist, + input fdec_frn_iu5_i1_bta_val, + input [0:19] fdec_frn_iu5_i1_fusion, + input fdec_frn_iu5_i1_spec, + input fdec_frn_iu5_i1_type_fp, + input fdec_frn_iu5_i1_type_ap, + input fdec_frn_iu5_i1_type_spv, + input fdec_frn_iu5_i1_type_st, + input fdec_frn_iu5_i1_async_block, + input fdec_frn_iu5_i1_np1_flush, + input fdec_frn_iu5_i1_core_block, + input fdec_frn_iu5_i1_isram, + input fdec_frn_iu5_i1_isload, + input fdec_frn_iu5_i1_isstore, + input [0:31] fdec_frn_iu5_i1_instr, + input [62-`EFF_IFAR_WIDTH:61] fdec_frn_iu5_i1_ifar, + input [62-`EFF_IFAR_WIDTH:61] fdec_frn_iu5_i1_bta, + input fdec_frn_iu5_i1_br_pred, + input fdec_frn_iu5_i1_bh_update, + input [0:1] fdec_frn_iu5_i1_bh0_hist, + input [0:1] fdec_frn_iu5_i1_bh1_hist, + input [0:1] fdec_frn_iu5_i1_bh2_hist, + input [0:17] fdec_frn_iu5_i1_gshare, + input [0:2] fdec_frn_iu5_i1_ls_ptr, + input fdec_frn_iu5_i1_match, + input [0:3] fdec_frn_iu5_i1_ilat, + input fdec_frn_iu5_i1_t1_v, + input [0:2] fdec_frn_iu5_i1_t1_t, + input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i1_t1_a, + input fdec_frn_iu5_i1_t2_v, + input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i1_t2_a, + input [0:2] fdec_frn_iu5_i1_t2_t, + input fdec_frn_iu5_i1_t3_v, + input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i1_t3_a, + input [0:2] fdec_frn_iu5_i1_t3_t, + input fdec_frn_iu5_i1_s1_v, + input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i1_s1_a, + input [0:2] fdec_frn_iu5_i1_s1_t, + input fdec_frn_iu5_i1_s2_v, + input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i1_s2_a, + input [0:2] fdec_frn_iu5_i1_s2_t, + input fdec_frn_iu5_i1_s3_v, + input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i1_s3_a, + input [0:2] fdec_frn_iu5_i1_s3_t, + + //----------------------------- + // Stall to decode + //----------------------------- + output frn_fdec_iu5_stall, + input au_iu_iu5_stall, //AXU Rename stall + + //----------------------------- + // Stall from dispatch + //----------------------------- + input fdis_frn_iu6_stall, + + //---------------------------- + // Completion Interface + //---------------------------- + input cp_rn_empty, + input cp_rn_i0_v, + input [0:`ITAG_SIZE_ENC-1] cp_rn_i0_itag, + input cp_rn_i0_t1_v, + input [0:2] cp_rn_i0_t1_t, + input [0:`GPR_POOL_ENC-1] cp_rn_i0_t1_p, + input [0:`GPR_POOL_ENC-1] cp_rn_i0_t1_a, + input cp_rn_i0_t2_v, + input [0:2] cp_rn_i0_t2_t, + input [0:`GPR_POOL_ENC-1] cp_rn_i0_t2_p, + input [0:`GPR_POOL_ENC-1] cp_rn_i0_t2_a, + input cp_rn_i0_t3_v, + input [0:2] cp_rn_i0_t3_t, + input [0:`GPR_POOL_ENC-1] cp_rn_i0_t3_p, + input [0:`GPR_POOL_ENC-1] cp_rn_i0_t3_a, + + input cp_rn_i1_v, + input [0:`ITAG_SIZE_ENC-1] cp_rn_i1_itag, + input cp_rn_i1_t1_v, + input [0:2] cp_rn_i1_t1_t, + input [0:`GPR_POOL_ENC-1] cp_rn_i1_t1_p, + input [0:`GPR_POOL_ENC-1] cp_rn_i1_t1_a, + input cp_rn_i1_t2_v, + input [0:2] cp_rn_i1_t2_t, + input [0:`GPR_POOL_ENC-1] cp_rn_i1_t2_p, + input [0:`GPR_POOL_ENC-1] cp_rn_i1_t2_a, + input cp_rn_i1_t3_v, + input [0:2] cp_rn_i1_t3_t, + input [0:`GPR_POOL_ENC-1] cp_rn_i1_t3_p, + input [0:`GPR_POOL_ENC-1] cp_rn_i1_t3_a, + + input cp_flush, + input cp_flush_into_uc, + input br_iu_redirect, + input cp_rn_uc_credit_free, + + //---------------------------------------------------------------- + // AXU Interface + //---------------------------------------------------------------- + output iu_au_iu5_send_ok, + output [0:`ITAG_SIZE_ENC-1] iu_au_iu5_next_itag_i0, + output [0:`ITAG_SIZE_ENC-1] iu_au_iu5_next_itag_i1, + input au_iu_iu5_axu0_send_ok, + input au_iu_iu5_axu1_send_ok, + + input [0:`GPR_POOL_ENC-1] au_iu_iu5_i0_t1_p, + input [0:`GPR_POOL_ENC-1] au_iu_iu5_i0_t2_p, + input [0:`GPR_POOL_ENC-1] au_iu_iu5_i0_t3_p, + input [0:`GPR_POOL_ENC-1] au_iu_iu5_i0_s1_p, + input [0:`GPR_POOL_ENC-1] au_iu_iu5_i0_s2_p, + input [0:`GPR_POOL_ENC-1] au_iu_iu5_i0_s3_p, + + input [0:`ITAG_SIZE_ENC-1] au_iu_iu5_i0_s1_itag, + input [0:`ITAG_SIZE_ENC-1] au_iu_iu5_i0_s2_itag, + input [0:`ITAG_SIZE_ENC-1] au_iu_iu5_i0_s3_itag, + + input [0:`GPR_POOL_ENC-1] au_iu_iu5_i1_t1_p, + input [0:`GPR_POOL_ENC-1] au_iu_iu5_i1_t2_p, + input [0:`GPR_POOL_ENC-1] au_iu_iu5_i1_t3_p, + input [0:`GPR_POOL_ENC-1] au_iu_iu5_i1_s1_p, + input [0:`GPR_POOL_ENC-1] au_iu_iu5_i1_s2_p, + input [0:`GPR_POOL_ENC-1] au_iu_iu5_i1_s3_p, + input au_iu_iu5_i1_s1_dep_hit, + input au_iu_iu5_i1_s2_dep_hit, + input au_iu_iu5_i1_s3_dep_hit, + + input [0:`ITAG_SIZE_ENC-1] au_iu_iu5_i1_s1_itag, + input [0:`ITAG_SIZE_ENC-1] au_iu_iu5_i1_s2_itag, + input [0:`ITAG_SIZE_ENC-1] au_iu_iu5_i1_s3_itag, + + //---------------------------------------------------------------- + // Interface to reservation station - Completion is snooping also + //---------------------------------------------------------------- + output frn_fdis_iu6_i0_vld, + output [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i0_itag, + output [0:2] frn_fdis_iu6_i0_ucode, + output [0:`UCODE_ENTRIES_ENC-1] frn_fdis_iu6_i0_ucode_cnt, + output frn_fdis_iu6_i0_2ucode, + output frn_fdis_iu6_i0_fuse_nop, + output frn_fdis_iu6_i0_rte_lq, + output frn_fdis_iu6_i0_rte_sq, + output frn_fdis_iu6_i0_rte_fx0, + output frn_fdis_iu6_i0_rte_fx1, + output frn_fdis_iu6_i0_rte_axu0, + output frn_fdis_iu6_i0_rte_axu1, + output frn_fdis_iu6_i0_valop, + output frn_fdis_iu6_i0_ord, + output frn_fdis_iu6_i0_cord, + output [0:2] frn_fdis_iu6_i0_error, + output frn_fdis_iu6_i0_btb_entry, + output [0:1] frn_fdis_iu6_i0_btb_hist, + output frn_fdis_iu6_i0_bta_val, + output [0:19] frn_fdis_iu6_i0_fusion, + output frn_fdis_iu6_i0_spec, + output frn_fdis_iu6_i0_type_fp, + output frn_fdis_iu6_i0_type_ap, + output frn_fdis_iu6_i0_type_spv, + output frn_fdis_iu6_i0_type_st, + output frn_fdis_iu6_i0_async_block, + output frn_fdis_iu6_i0_np1_flush, + output frn_fdis_iu6_i0_core_block, + output frn_fdis_iu6_i0_isram, + output frn_fdis_iu6_i0_isload, + output frn_fdis_iu6_i0_isstore, + output [0:31] frn_fdis_iu6_i0_instr, + output [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_i0_ifar, + output [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_i0_bta, + output frn_fdis_iu6_i0_br_pred, + output frn_fdis_iu6_i0_bh_update, + output [0:1] frn_fdis_iu6_i0_bh0_hist, + output [0:1] frn_fdis_iu6_i0_bh1_hist, + output [0:1] frn_fdis_iu6_i0_bh2_hist, + output [0:17] frn_fdis_iu6_i0_gshare, + output [0:2] frn_fdis_iu6_i0_ls_ptr, + output frn_fdis_iu6_i0_match, + output [0:3] frn_fdis_iu6_i0_ilat, + output frn_fdis_iu6_i0_t1_v, + output [0:2] frn_fdis_iu6_i0_t1_t, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t1_a, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t1_p, + output frn_fdis_iu6_i0_t2_v, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t2_a, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t2_p, + output [0:2] frn_fdis_iu6_i0_t2_t, + output frn_fdis_iu6_i0_t3_v, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t3_a, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t3_p, + output [0:2] frn_fdis_iu6_i0_t3_t, + output frn_fdis_iu6_i0_s1_v, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s1_a, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s1_p, + output [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i0_s1_itag, + output [0:2] frn_fdis_iu6_i0_s1_t, + output frn_fdis_iu6_i0_s2_v, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s2_a, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s2_p, + output [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i0_s2_itag, + output [0:2] frn_fdis_iu6_i0_s2_t, + output frn_fdis_iu6_i0_s3_v, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s3_a, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s3_p, + output [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i0_s3_itag, + output [0:2] frn_fdis_iu6_i0_s3_t, + + output frn_fdis_iu6_i1_vld, + output [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i1_itag, + output [0:2] frn_fdis_iu6_i1_ucode, + output [0:`UCODE_ENTRIES_ENC-1] frn_fdis_iu6_i1_ucode_cnt, + output frn_fdis_iu6_i1_fuse_nop, + output frn_fdis_iu6_i1_rte_lq, + output frn_fdis_iu6_i1_rte_sq, + output frn_fdis_iu6_i1_rte_fx0, + output frn_fdis_iu6_i1_rte_fx1, + output frn_fdis_iu6_i1_rte_axu0, + output frn_fdis_iu6_i1_rte_axu1, + output frn_fdis_iu6_i1_valop, + output frn_fdis_iu6_i1_ord, + output frn_fdis_iu6_i1_cord, + output [0:2] frn_fdis_iu6_i1_error, + output frn_fdis_iu6_i1_btb_entry, + output [0:1] frn_fdis_iu6_i1_btb_hist, + output frn_fdis_iu6_i1_bta_val, + output [0:19] frn_fdis_iu6_i1_fusion, + output frn_fdis_iu6_i1_spec, + output frn_fdis_iu6_i1_type_fp, + output frn_fdis_iu6_i1_type_ap, + output frn_fdis_iu6_i1_type_spv, + output frn_fdis_iu6_i1_type_st, + output frn_fdis_iu6_i1_async_block, + output frn_fdis_iu6_i1_np1_flush, + output frn_fdis_iu6_i1_core_block, + output frn_fdis_iu6_i1_isram, + output frn_fdis_iu6_i1_isload, + output frn_fdis_iu6_i1_isstore, + output [0:31] frn_fdis_iu6_i1_instr, + output [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_i1_ifar, + output [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_i1_bta, + output frn_fdis_iu6_i1_br_pred, + output frn_fdis_iu6_i1_bh_update, + output [0:1] frn_fdis_iu6_i1_bh0_hist, + output [0:1] frn_fdis_iu6_i1_bh1_hist, + output [0:1] frn_fdis_iu6_i1_bh2_hist, + output [0:17] frn_fdis_iu6_i1_gshare, + output [0:2] frn_fdis_iu6_i1_ls_ptr, + output frn_fdis_iu6_i1_match, + output [0:3] frn_fdis_iu6_i1_ilat, + output frn_fdis_iu6_i1_t1_v, + output [0:2] frn_fdis_iu6_i1_t1_t, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t1_a, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t1_p, + output frn_fdis_iu6_i1_t2_v, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t2_a, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t2_p, + output [0:2] frn_fdis_iu6_i1_t2_t, + output frn_fdis_iu6_i1_t3_v, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t3_a, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t3_p, + output [0:2] frn_fdis_iu6_i1_t3_t, + output frn_fdis_iu6_i1_s1_v, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s1_a, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s1_p, + output [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i1_s1_itag, + output [0:2] frn_fdis_iu6_i1_s1_t, + output frn_fdis_iu6_i1_s1_dep_hit, + output frn_fdis_iu6_i1_s2_v, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s2_a, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s2_p, + output [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i1_s2_itag, + output [0:2] frn_fdis_iu6_i1_s2_t, + output frn_fdis_iu6_i1_s2_dep_hit, + output frn_fdis_iu6_i1_s3_v, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s3_a, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s3_p, + output [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i1_s3_itag, + output [0:2] frn_fdis_iu6_i1_s3_t, + output frn_fdis_iu6_i1_s3_dep_hit + + ); + + localparam [0:31] value_1 = 32'h00000001; + localparam [0:31] value_2 = 32'h00000002; + + parameter next_itag_0_offset = 0; + parameter next_itag_1_offset = next_itag_0_offset + `ITAG_SIZE_ENC; + parameter cp_high_credit_cnt_offset = next_itag_1_offset + `ITAG_SIZE_ENC; + parameter cp_med_credit_cnt_offset = cp_high_credit_cnt_offset + `CPL_Q_DEPTH_ENC + 1; + parameter ucode_cnt_offset = cp_med_credit_cnt_offset + `CPL_Q_DEPTH_ENC + 1; + parameter ucode_cnt_save_offset = ucode_cnt_offset + `UCODE_ENTRIES_ENC; + parameter cp_flush_offset = ucode_cnt_save_offset + `UCODE_ENTRIES_ENC; + parameter cp_flush_into_uc_offset = cp_flush_offset + 1; + parameter br_iu_hold_offset = cp_flush_into_uc_offset + 1; + parameter cp_rn_empty_offset = br_iu_hold_offset + 1; + parameter hold_instructions_offset = cp_rn_empty_offset + 1; + parameter high_pri_mask_offset = hold_instructions_offset + 1; + + parameter fdis_frn_iu6_stall_offset = high_pri_mask_offset + 1; + + parameter frn_fdis_iu6_i0_vld_offset = fdis_frn_iu6_stall_offset + 19; + parameter frn_fdis_iu6_i0_itag_offset = frn_fdis_iu6_i0_vld_offset + 1; + parameter frn_fdis_iu6_i0_ucode_offset = frn_fdis_iu6_i0_itag_offset + `ITAG_SIZE_ENC; + parameter frn_fdis_iu6_i0_ucode_cnt_offset = frn_fdis_iu6_i0_ucode_offset + 3; + parameter frn_fdis_iu6_i0_2ucode_offset = frn_fdis_iu6_i0_ucode_cnt_offset + `UCODE_ENTRIES_ENC; + parameter frn_fdis_iu6_i0_fuse_nop_offset = frn_fdis_iu6_i0_2ucode_offset + 1; + parameter frn_fdis_iu6_i0_rte_lq_offset = frn_fdis_iu6_i0_fuse_nop_offset + 1; + parameter frn_fdis_iu6_i0_rte_sq_offset = frn_fdis_iu6_i0_rte_lq_offset + 1; + parameter frn_fdis_iu6_i0_rte_fx0_offset = frn_fdis_iu6_i0_rte_sq_offset + 1; + parameter frn_fdis_iu6_i0_rte_fx1_offset = frn_fdis_iu6_i0_rte_fx0_offset + 1; + parameter frn_fdis_iu6_i0_rte_axu0_offset = frn_fdis_iu6_i0_rte_fx1_offset + 1; + parameter frn_fdis_iu6_i0_rte_axu1_offset = frn_fdis_iu6_i0_rte_axu0_offset + 1; + parameter frn_fdis_iu6_i0_valop_offset = frn_fdis_iu6_i0_rte_axu1_offset + 1; + parameter frn_fdis_iu6_i0_ord_offset = frn_fdis_iu6_i0_valop_offset + 1; + parameter frn_fdis_iu6_i0_cord_offset = frn_fdis_iu6_i0_ord_offset + 1; + parameter frn_fdis_iu6_i0_error_offset = frn_fdis_iu6_i0_cord_offset + 1; + parameter frn_fdis_iu6_i0_btb_entry_offset = frn_fdis_iu6_i0_error_offset + 3; + parameter frn_fdis_iu6_i0_btb_hist_offset = frn_fdis_iu6_i0_btb_entry_offset + 1; + parameter frn_fdis_iu6_i0_bta_val_offset = frn_fdis_iu6_i0_btb_hist_offset + 2; + parameter frn_fdis_iu6_i0_fusion_offset = frn_fdis_iu6_i0_bta_val_offset + 1; + parameter frn_fdis_iu6_i0_spec_offset = frn_fdis_iu6_i0_fusion_offset + 20; + parameter frn_fdis_iu6_i0_type_fp_offset = frn_fdis_iu6_i0_spec_offset + 1; + parameter frn_fdis_iu6_i0_type_ap_offset = frn_fdis_iu6_i0_type_fp_offset + 1; + parameter frn_fdis_iu6_i0_type_spv_offset = frn_fdis_iu6_i0_type_ap_offset + 1; + parameter frn_fdis_iu6_i0_type_st_offset = frn_fdis_iu6_i0_type_spv_offset + 1; + parameter frn_fdis_iu6_i0_async_block_offset = frn_fdis_iu6_i0_type_st_offset + 1; + parameter frn_fdis_iu6_i0_np1_flush_offset = frn_fdis_iu6_i0_async_block_offset + 1; + parameter frn_fdis_iu6_i0_core_block_offset = frn_fdis_iu6_i0_np1_flush_offset + 1; + parameter frn_fdis_iu6_i0_isram_offset = frn_fdis_iu6_i0_core_block_offset + 1; + parameter frn_fdis_iu6_i0_isload_offset = frn_fdis_iu6_i0_isram_offset + 1; + parameter frn_fdis_iu6_i0_isstore_offset = frn_fdis_iu6_i0_isload_offset + 1; + parameter frn_fdis_iu6_i0_instr_offset = frn_fdis_iu6_i0_isstore_offset + 1; + parameter frn_fdis_iu6_i0_ifar_offset = frn_fdis_iu6_i0_instr_offset + 32; + parameter frn_fdis_iu6_i0_bta_offset = frn_fdis_iu6_i0_ifar_offset + (`EFF_IFAR_WIDTH); + parameter frn_fdis_iu6_i0_br_pred_offset = frn_fdis_iu6_i0_bta_offset + (`EFF_IFAR_WIDTH); + parameter frn_fdis_iu6_i0_bh_update_offset = frn_fdis_iu6_i0_br_pred_offset + 1; + parameter frn_fdis_iu6_i0_bh0_hist_offset = frn_fdis_iu6_i0_bh_update_offset + 1; + parameter frn_fdis_iu6_i0_bh1_hist_offset = frn_fdis_iu6_i0_bh0_hist_offset + 2; + parameter frn_fdis_iu6_i0_bh2_hist_offset = frn_fdis_iu6_i0_bh1_hist_offset + 2; + parameter frn_fdis_iu6_i0_gshare_offset = frn_fdis_iu6_i0_bh2_hist_offset + 2; + parameter frn_fdis_iu6_i0_ls_ptr_offset = frn_fdis_iu6_i0_gshare_offset + 18; + parameter frn_fdis_iu6_i0_match_offset = frn_fdis_iu6_i0_ls_ptr_offset + 3; + parameter frn_fdis_iu6_i0_ilat_offset = frn_fdis_iu6_i0_match_offset + 1; + parameter frn_fdis_iu6_i0_t1_v_offset = frn_fdis_iu6_i0_ilat_offset + 4; + parameter frn_fdis_iu6_i0_t1_t_offset = frn_fdis_iu6_i0_t1_v_offset + 1; + parameter frn_fdis_iu6_i0_t1_a_offset = frn_fdis_iu6_i0_t1_t_offset + 3; + parameter frn_fdis_iu6_i0_t1_p_offset = frn_fdis_iu6_i0_t1_a_offset + `GPR_POOL_ENC; + parameter frn_fdis_iu6_i0_t2_v_offset = frn_fdis_iu6_i0_t1_p_offset + `GPR_POOL_ENC; + parameter frn_fdis_iu6_i0_t2_a_offset = frn_fdis_iu6_i0_t2_v_offset + 1; + parameter frn_fdis_iu6_i0_t2_p_offset = frn_fdis_iu6_i0_t2_a_offset + `GPR_POOL_ENC; + parameter frn_fdis_iu6_i0_t2_t_offset = frn_fdis_iu6_i0_t2_p_offset + `GPR_POOL_ENC; + parameter frn_fdis_iu6_i0_t3_v_offset = frn_fdis_iu6_i0_t2_t_offset + 3; + parameter frn_fdis_iu6_i0_t3_a_offset = frn_fdis_iu6_i0_t3_v_offset + 1; + parameter frn_fdis_iu6_i0_t3_p_offset = frn_fdis_iu6_i0_t3_a_offset + `GPR_POOL_ENC; + parameter frn_fdis_iu6_i0_t3_t_offset = frn_fdis_iu6_i0_t3_p_offset + `GPR_POOL_ENC; + parameter frn_fdis_iu6_i0_s1_v_offset = frn_fdis_iu6_i0_t3_t_offset + 3; + parameter frn_fdis_iu6_i0_s1_a_offset = frn_fdis_iu6_i0_s1_v_offset + 1; + parameter frn_fdis_iu6_i0_s1_p_offset = frn_fdis_iu6_i0_s1_a_offset + `GPR_POOL_ENC; + parameter frn_fdis_iu6_i0_s1_itag_offset = frn_fdis_iu6_i0_s1_p_offset + `GPR_POOL_ENC; + parameter frn_fdis_iu6_i0_s1_t_offset = frn_fdis_iu6_i0_s1_itag_offset + `ITAG_SIZE_ENC; + parameter frn_fdis_iu6_i0_s2_v_offset = frn_fdis_iu6_i0_s1_t_offset + 3; + parameter frn_fdis_iu6_i0_s2_a_offset = frn_fdis_iu6_i0_s2_v_offset + 1; + parameter frn_fdis_iu6_i0_s2_p_offset = frn_fdis_iu6_i0_s2_a_offset + `GPR_POOL_ENC; + parameter frn_fdis_iu6_i0_s2_itag_offset = frn_fdis_iu6_i0_s2_p_offset + `GPR_POOL_ENC; + parameter frn_fdis_iu6_i0_s2_t_offset = frn_fdis_iu6_i0_s2_itag_offset + `ITAG_SIZE_ENC; + parameter frn_fdis_iu6_i0_s3_v_offset = frn_fdis_iu6_i0_s2_t_offset + 3; + parameter frn_fdis_iu6_i0_s3_a_offset = frn_fdis_iu6_i0_s3_v_offset + 1; + parameter frn_fdis_iu6_i0_s3_p_offset = frn_fdis_iu6_i0_s3_a_offset + `GPR_POOL_ENC; + parameter frn_fdis_iu6_i0_s3_itag_offset = frn_fdis_iu6_i0_s3_p_offset + `GPR_POOL_ENC; + parameter frn_fdis_iu6_i0_s3_t_offset = frn_fdis_iu6_i0_s3_itag_offset + `ITAG_SIZE_ENC; + parameter frn_fdis_iu6_i1_vld_offset = frn_fdis_iu6_i0_s3_t_offset + 3; + parameter frn_fdis_iu6_i1_itag_offset = frn_fdis_iu6_i1_vld_offset + 1; + parameter frn_fdis_iu6_i1_ucode_offset = frn_fdis_iu6_i1_itag_offset + `ITAG_SIZE_ENC; + parameter frn_fdis_iu6_i1_ucode_cnt_offset = frn_fdis_iu6_i1_ucode_offset + 3; + parameter frn_fdis_iu6_i1_fuse_nop_offset = frn_fdis_iu6_i1_ucode_cnt_offset + `UCODE_ENTRIES_ENC; + parameter frn_fdis_iu6_i1_rte_lq_offset = frn_fdis_iu6_i1_fuse_nop_offset + 1; + parameter frn_fdis_iu6_i1_rte_sq_offset = frn_fdis_iu6_i1_rte_lq_offset + 1; + parameter frn_fdis_iu6_i1_rte_fx0_offset = frn_fdis_iu6_i1_rte_sq_offset + 1; + parameter frn_fdis_iu6_i1_rte_fx1_offset = frn_fdis_iu6_i1_rte_fx0_offset + 1; + parameter frn_fdis_iu6_i1_rte_axu0_offset = frn_fdis_iu6_i1_rte_fx1_offset + 1; + parameter frn_fdis_iu6_i1_rte_axu1_offset = frn_fdis_iu6_i1_rte_axu0_offset + 1; + parameter frn_fdis_iu6_i1_valop_offset = frn_fdis_iu6_i1_rte_axu1_offset + 1; + parameter frn_fdis_iu6_i1_ord_offset = frn_fdis_iu6_i1_valop_offset + 1; + parameter frn_fdis_iu6_i1_cord_offset = frn_fdis_iu6_i1_ord_offset + 1; + parameter frn_fdis_iu6_i1_error_offset = frn_fdis_iu6_i1_cord_offset + 1; + parameter frn_fdis_iu6_i1_btb_entry_offset = frn_fdis_iu6_i1_error_offset + 3; + parameter frn_fdis_iu6_i1_btb_hist_offset = frn_fdis_iu6_i1_btb_entry_offset + 1; + parameter frn_fdis_iu6_i1_bta_val_offset = frn_fdis_iu6_i1_btb_hist_offset + 2; + parameter frn_fdis_iu6_i1_fusion_offset = frn_fdis_iu6_i1_bta_val_offset + 1; + parameter frn_fdis_iu6_i1_spec_offset = frn_fdis_iu6_i1_fusion_offset + 20; + parameter frn_fdis_iu6_i1_type_fp_offset = frn_fdis_iu6_i1_spec_offset + 1; + parameter frn_fdis_iu6_i1_type_ap_offset = frn_fdis_iu6_i1_type_fp_offset + 1; + parameter frn_fdis_iu6_i1_type_spv_offset = frn_fdis_iu6_i1_type_ap_offset + 1; + parameter frn_fdis_iu6_i1_type_st_offset = frn_fdis_iu6_i1_type_spv_offset + 1; + parameter frn_fdis_iu6_i1_async_block_offset = frn_fdis_iu6_i1_type_st_offset + 1; + parameter frn_fdis_iu6_i1_np1_flush_offset = frn_fdis_iu6_i1_async_block_offset + 1; + parameter frn_fdis_iu6_i1_core_block_offset = frn_fdis_iu6_i1_np1_flush_offset + 1; + parameter frn_fdis_iu6_i1_isram_offset = frn_fdis_iu6_i1_core_block_offset + 1; + parameter frn_fdis_iu6_i1_isload_offset = frn_fdis_iu6_i1_isram_offset + 1; + parameter frn_fdis_iu6_i1_isstore_offset = frn_fdis_iu6_i1_isload_offset + 1; + parameter frn_fdis_iu6_i1_instr_offset = frn_fdis_iu6_i1_isstore_offset + 1; + parameter frn_fdis_iu6_i1_ifar_offset = frn_fdis_iu6_i1_instr_offset + 32; + parameter frn_fdis_iu6_i1_bta_offset = frn_fdis_iu6_i1_ifar_offset + (`EFF_IFAR_WIDTH); + parameter frn_fdis_iu6_i1_br_pred_offset = frn_fdis_iu6_i1_bta_offset + (`EFF_IFAR_WIDTH); + parameter frn_fdis_iu6_i1_bh_update_offset = frn_fdis_iu6_i1_br_pred_offset + 1; + parameter frn_fdis_iu6_i1_bh0_hist_offset = frn_fdis_iu6_i1_bh_update_offset + 1; + parameter frn_fdis_iu6_i1_bh1_hist_offset = frn_fdis_iu6_i1_bh0_hist_offset + 2; + parameter frn_fdis_iu6_i1_bh2_hist_offset = frn_fdis_iu6_i1_bh1_hist_offset + 2; + parameter frn_fdis_iu6_i1_gshare_offset = frn_fdis_iu6_i1_bh2_hist_offset + 2; + parameter frn_fdis_iu6_i1_ls_ptr_offset = frn_fdis_iu6_i1_gshare_offset + 18; + parameter frn_fdis_iu6_i1_match_offset = frn_fdis_iu6_i1_ls_ptr_offset + 3; + parameter frn_fdis_iu6_i1_ilat_offset = frn_fdis_iu6_i1_match_offset + 1; + parameter frn_fdis_iu6_i1_t1_v_offset = frn_fdis_iu6_i1_ilat_offset + 4; + parameter frn_fdis_iu6_i1_t1_t_offset = frn_fdis_iu6_i1_t1_v_offset + 1; + parameter frn_fdis_iu6_i1_t1_a_offset = frn_fdis_iu6_i1_t1_t_offset + 3; + parameter frn_fdis_iu6_i1_t1_p_offset = frn_fdis_iu6_i1_t1_a_offset + `GPR_POOL_ENC; + parameter frn_fdis_iu6_i1_t2_v_offset = frn_fdis_iu6_i1_t1_p_offset + `GPR_POOL_ENC; + parameter frn_fdis_iu6_i1_t2_a_offset = frn_fdis_iu6_i1_t2_v_offset + 1; + parameter frn_fdis_iu6_i1_t2_p_offset = frn_fdis_iu6_i1_t2_a_offset + `GPR_POOL_ENC; + parameter frn_fdis_iu6_i1_t2_t_offset = frn_fdis_iu6_i1_t2_p_offset + `GPR_POOL_ENC; + parameter frn_fdis_iu6_i1_t3_v_offset = frn_fdis_iu6_i1_t2_t_offset + 3; + parameter frn_fdis_iu6_i1_t3_a_offset = frn_fdis_iu6_i1_t3_v_offset + 1; + parameter frn_fdis_iu6_i1_t3_p_offset = frn_fdis_iu6_i1_t3_a_offset + `GPR_POOL_ENC; + parameter frn_fdis_iu6_i1_t3_t_offset = frn_fdis_iu6_i1_t3_p_offset + `GPR_POOL_ENC; + parameter frn_fdis_iu6_i1_s1_v_offset = frn_fdis_iu6_i1_t3_t_offset + 3; + parameter frn_fdis_iu6_i1_s1_a_offset = frn_fdis_iu6_i1_s1_v_offset + 1; + parameter frn_fdis_iu6_i1_s1_p_offset = frn_fdis_iu6_i1_s1_a_offset + `GPR_POOL_ENC; + parameter frn_fdis_iu6_i1_s1_itag_offset = frn_fdis_iu6_i1_s1_p_offset + `GPR_POOL_ENC; + parameter frn_fdis_iu6_i1_s1_t_offset = frn_fdis_iu6_i1_s1_itag_offset + `ITAG_SIZE_ENC; + parameter frn_fdis_iu6_i1_s1_dep_hit_offset = frn_fdis_iu6_i1_s1_t_offset + 3; + parameter frn_fdis_iu6_i1_s2_v_offset = frn_fdis_iu6_i1_s1_dep_hit_offset + 1; + parameter frn_fdis_iu6_i1_s2_a_offset = frn_fdis_iu6_i1_s2_v_offset + 1; + parameter frn_fdis_iu6_i1_s2_p_offset = frn_fdis_iu6_i1_s2_a_offset + `GPR_POOL_ENC; + parameter frn_fdis_iu6_i1_s2_itag_offset = frn_fdis_iu6_i1_s2_p_offset + `GPR_POOL_ENC; + parameter frn_fdis_iu6_i1_s2_t_offset = frn_fdis_iu6_i1_s2_itag_offset + `ITAG_SIZE_ENC; + parameter frn_fdis_iu6_i1_s2_dep_hit_offset = frn_fdis_iu6_i1_s2_t_offset + 3; + parameter frn_fdis_iu6_i1_s3_v_offset = frn_fdis_iu6_i1_s2_dep_hit_offset + 1; + parameter frn_fdis_iu6_i1_s3_a_offset = frn_fdis_iu6_i1_s3_v_offset + 1; + parameter frn_fdis_iu6_i1_s3_p_offset = frn_fdis_iu6_i1_s3_a_offset + `GPR_POOL_ENC; + parameter frn_fdis_iu6_i1_s3_itag_offset = frn_fdis_iu6_i1_s3_p_offset + `GPR_POOL_ENC; + parameter frn_fdis_iu6_i1_s3_t_offset = frn_fdis_iu6_i1_s3_itag_offset + `ITAG_SIZE_ENC; + parameter frn_fdis_iu6_i1_s3_dep_hit_offset = frn_fdis_iu6_i1_s3_t_offset + 3; + + parameter stall_frn_fdis_iu6_i0_vld_offset = frn_fdis_iu6_i1_s3_dep_hit_offset + 1; + parameter stall_frn_fdis_iu6_i0_itag_offset = stall_frn_fdis_iu6_i0_vld_offset + 1; + parameter stall_frn_fdis_iu6_i0_ucode_offset = stall_frn_fdis_iu6_i0_itag_offset + `ITAG_SIZE_ENC; + parameter stall_frn_fdis_iu6_i0_ucode_cnt_offset = stall_frn_fdis_iu6_i0_ucode_offset + 3; + parameter stall_frn_fdis_iu6_i0_fuse_nop_offset = stall_frn_fdis_iu6_i0_ucode_cnt_offset + `UCODE_ENTRIES_ENC; + parameter stall_frn_fdis_iu6_i0_2ucode_offset = stall_frn_fdis_iu6_i0_fuse_nop_offset + 1; + parameter stall_frn_fdis_iu6_i0_rte_lq_offset = stall_frn_fdis_iu6_i0_2ucode_offset + 1; + parameter stall_frn_fdis_iu6_i0_rte_sq_offset = stall_frn_fdis_iu6_i0_rte_lq_offset + 1; + parameter stall_frn_fdis_iu6_i0_rte_fx0_offset = stall_frn_fdis_iu6_i0_rte_sq_offset + 1; + parameter stall_frn_fdis_iu6_i0_rte_fx1_offset = stall_frn_fdis_iu6_i0_rte_fx0_offset + 1; + parameter stall_frn_fdis_iu6_i0_rte_axu0_offset = stall_frn_fdis_iu6_i0_rte_fx1_offset + 1; + parameter stall_frn_fdis_iu6_i0_rte_axu1_offset = stall_frn_fdis_iu6_i0_rte_axu0_offset + 1; + parameter stall_frn_fdis_iu6_i0_valop_offset = stall_frn_fdis_iu6_i0_rte_axu1_offset + 1; + parameter stall_frn_fdis_iu6_i0_ord_offset = stall_frn_fdis_iu6_i0_valop_offset + 1; + parameter stall_frn_fdis_iu6_i0_cord_offset = stall_frn_fdis_iu6_i0_ord_offset + 1; + parameter stall_frn_fdis_iu6_i0_error_offset = stall_frn_fdis_iu6_i0_cord_offset + 1; + parameter stall_frn_fdis_iu6_i0_btb_entry_offset = stall_frn_fdis_iu6_i0_error_offset + 3; + parameter stall_frn_fdis_iu6_i0_btb_hist_offset = stall_frn_fdis_iu6_i0_btb_entry_offset + 1; + parameter stall_frn_fdis_iu6_i0_bta_val_offset = stall_frn_fdis_iu6_i0_btb_hist_offset + 2; + parameter stall_frn_fdis_iu6_i0_fusion_offset = stall_frn_fdis_iu6_i0_bta_val_offset + 1; + parameter stall_frn_fdis_iu6_i0_spec_offset = stall_frn_fdis_iu6_i0_fusion_offset + 20; + parameter stall_frn_fdis_iu6_i0_type_fp_offset = stall_frn_fdis_iu6_i0_spec_offset + 1; + parameter stall_frn_fdis_iu6_i0_type_ap_offset = stall_frn_fdis_iu6_i0_type_fp_offset + 1; + parameter stall_frn_fdis_iu6_i0_type_spv_offset = stall_frn_fdis_iu6_i0_type_ap_offset + 1; + parameter stall_frn_fdis_iu6_i0_type_st_offset = stall_frn_fdis_iu6_i0_type_spv_offset + 1; + parameter stall_frn_fdis_iu6_i0_async_block_offset = stall_frn_fdis_iu6_i0_type_st_offset + 1; + parameter stall_frn_fdis_iu6_i0_np1_flush_offset = stall_frn_fdis_iu6_i0_async_block_offset + 1; + parameter stall_frn_fdis_iu6_i0_core_block_offset = stall_frn_fdis_iu6_i0_np1_flush_offset + 1; + parameter stall_frn_fdis_iu6_i0_isram_offset = stall_frn_fdis_iu6_i0_core_block_offset + 1; + parameter stall_frn_fdis_iu6_i0_isload_offset = stall_frn_fdis_iu6_i0_isram_offset + 1; + parameter stall_frn_fdis_iu6_i0_isstore_offset = stall_frn_fdis_iu6_i0_isload_offset + 1; + parameter stall_frn_fdis_iu6_i0_instr_offset = stall_frn_fdis_iu6_i0_isstore_offset + 1; + parameter stall_frn_fdis_iu6_i0_ifar_offset = stall_frn_fdis_iu6_i0_instr_offset + 32; + parameter stall_frn_fdis_iu6_i0_bta_offset = stall_frn_fdis_iu6_i0_ifar_offset + (`EFF_IFAR_WIDTH); + parameter stall_frn_fdis_iu6_i0_br_pred_offset = stall_frn_fdis_iu6_i0_bta_offset + (`EFF_IFAR_WIDTH); + parameter stall_frn_fdis_iu6_i0_bh_update_offset = stall_frn_fdis_iu6_i0_br_pred_offset + 1; + parameter stall_frn_fdis_iu6_i0_bh0_hist_offset = stall_frn_fdis_iu6_i0_bh_update_offset + 1; + parameter stall_frn_fdis_iu6_i0_bh1_hist_offset = stall_frn_fdis_iu6_i0_bh0_hist_offset + 2; + parameter stall_frn_fdis_iu6_i0_bh2_hist_offset = stall_frn_fdis_iu6_i0_bh1_hist_offset + 2; + parameter stall_frn_fdis_iu6_i0_gshare_offset = stall_frn_fdis_iu6_i0_bh2_hist_offset + 2; + parameter stall_frn_fdis_iu6_i0_ls_ptr_offset = stall_frn_fdis_iu6_i0_gshare_offset + 18; + parameter stall_frn_fdis_iu6_i0_match_offset = stall_frn_fdis_iu6_i0_ls_ptr_offset + 3; + parameter stall_frn_fdis_iu6_i0_ilat_offset = stall_frn_fdis_iu6_i0_match_offset + 1; + parameter stall_frn_fdis_iu6_i0_t1_v_offset = stall_frn_fdis_iu6_i0_ilat_offset + 4; + parameter stall_frn_fdis_iu6_i0_t1_t_offset = stall_frn_fdis_iu6_i0_t1_v_offset + 1; + parameter stall_frn_fdis_iu6_i0_t1_a_offset = stall_frn_fdis_iu6_i0_t1_t_offset + 3; + parameter stall_frn_fdis_iu6_i0_t1_p_offset = stall_frn_fdis_iu6_i0_t1_a_offset + `GPR_POOL_ENC; + parameter stall_frn_fdis_iu6_i0_t2_v_offset = stall_frn_fdis_iu6_i0_t1_p_offset + `GPR_POOL_ENC; + parameter stall_frn_fdis_iu6_i0_t2_a_offset = stall_frn_fdis_iu6_i0_t2_v_offset + 1; + parameter stall_frn_fdis_iu6_i0_t2_p_offset = stall_frn_fdis_iu6_i0_t2_a_offset + `GPR_POOL_ENC; + parameter stall_frn_fdis_iu6_i0_t2_t_offset = stall_frn_fdis_iu6_i0_t2_p_offset + `GPR_POOL_ENC; + parameter stall_frn_fdis_iu6_i0_t3_v_offset = stall_frn_fdis_iu6_i0_t2_t_offset + 3; + parameter stall_frn_fdis_iu6_i0_t3_a_offset = stall_frn_fdis_iu6_i0_t3_v_offset + 1; + parameter stall_frn_fdis_iu6_i0_t3_p_offset = stall_frn_fdis_iu6_i0_t3_a_offset + `GPR_POOL_ENC; + parameter stall_frn_fdis_iu6_i0_t3_t_offset = stall_frn_fdis_iu6_i0_t3_p_offset + `GPR_POOL_ENC; + parameter stall_frn_fdis_iu6_i0_s1_v_offset = stall_frn_fdis_iu6_i0_t3_t_offset + 3; + parameter stall_frn_fdis_iu6_i0_s1_a_offset = stall_frn_fdis_iu6_i0_s1_v_offset + 1; + parameter stall_frn_fdis_iu6_i0_s1_p_offset = stall_frn_fdis_iu6_i0_s1_a_offset + `GPR_POOL_ENC; + parameter stall_frn_fdis_iu6_i0_s1_itag_offset = stall_frn_fdis_iu6_i0_s1_p_offset + `GPR_POOL_ENC; + parameter stall_frn_fdis_iu6_i0_s1_t_offset = stall_frn_fdis_iu6_i0_s1_itag_offset + `ITAG_SIZE_ENC; + parameter stall_frn_fdis_iu6_i0_s2_v_offset = stall_frn_fdis_iu6_i0_s1_t_offset + 3; + parameter stall_frn_fdis_iu6_i0_s2_a_offset = stall_frn_fdis_iu6_i0_s2_v_offset + 1; + parameter stall_frn_fdis_iu6_i0_s2_p_offset = stall_frn_fdis_iu6_i0_s2_a_offset + `GPR_POOL_ENC; + parameter stall_frn_fdis_iu6_i0_s2_itag_offset = stall_frn_fdis_iu6_i0_s2_p_offset + `GPR_POOL_ENC; + parameter stall_frn_fdis_iu6_i0_s2_t_offset = stall_frn_fdis_iu6_i0_s2_itag_offset + `ITAG_SIZE_ENC; + parameter stall_frn_fdis_iu6_i0_s3_v_offset = stall_frn_fdis_iu6_i0_s2_t_offset + 3; + parameter stall_frn_fdis_iu6_i0_s3_a_offset = stall_frn_fdis_iu6_i0_s3_v_offset + 1; + parameter stall_frn_fdis_iu6_i0_s3_p_offset = stall_frn_fdis_iu6_i0_s3_a_offset + `GPR_POOL_ENC; + parameter stall_frn_fdis_iu6_i0_s3_itag_offset = stall_frn_fdis_iu6_i0_s3_p_offset + `GPR_POOL_ENC; + parameter stall_frn_fdis_iu6_i0_s3_t_offset = stall_frn_fdis_iu6_i0_s3_itag_offset + `ITAG_SIZE_ENC; + parameter stall_frn_fdis_iu6_i1_vld_offset = stall_frn_fdis_iu6_i0_s3_t_offset + 3; + parameter stall_frn_fdis_iu6_i1_itag_offset = stall_frn_fdis_iu6_i1_vld_offset + 1; + parameter stall_frn_fdis_iu6_i1_ucode_offset = stall_frn_fdis_iu6_i1_itag_offset + `ITAG_SIZE_ENC; + parameter stall_frn_fdis_iu6_i1_ucode_cnt_offset = stall_frn_fdis_iu6_i1_ucode_offset + 3; + parameter stall_frn_fdis_iu6_i1_fuse_nop_offset = stall_frn_fdis_iu6_i1_ucode_cnt_offset + `UCODE_ENTRIES_ENC; + parameter stall_frn_fdis_iu6_i1_rte_lq_offset = stall_frn_fdis_iu6_i1_fuse_nop_offset + 1; + parameter stall_frn_fdis_iu6_i1_rte_sq_offset = stall_frn_fdis_iu6_i1_rte_lq_offset + 1; + parameter stall_frn_fdis_iu6_i1_rte_fx0_offset = stall_frn_fdis_iu6_i1_rte_sq_offset + 1; + parameter stall_frn_fdis_iu6_i1_rte_fx1_offset = stall_frn_fdis_iu6_i1_rte_fx0_offset + 1; + parameter stall_frn_fdis_iu6_i1_rte_axu0_offset = stall_frn_fdis_iu6_i1_rte_fx1_offset + 1; + parameter stall_frn_fdis_iu6_i1_rte_axu1_offset = stall_frn_fdis_iu6_i1_rte_axu0_offset + 1; + parameter stall_frn_fdis_iu6_i1_valop_offset = stall_frn_fdis_iu6_i1_rte_axu1_offset + 1; + parameter stall_frn_fdis_iu6_i1_ord_offset = stall_frn_fdis_iu6_i1_valop_offset + 1; + parameter stall_frn_fdis_iu6_i1_cord_offset = stall_frn_fdis_iu6_i1_ord_offset + 1; + parameter stall_frn_fdis_iu6_i1_error_offset = stall_frn_fdis_iu6_i1_cord_offset + 1; + parameter stall_frn_fdis_iu6_i1_btb_entry_offset = stall_frn_fdis_iu6_i1_error_offset + 3; + parameter stall_frn_fdis_iu6_i1_btb_hist_offset = stall_frn_fdis_iu6_i1_btb_entry_offset + 1; + parameter stall_frn_fdis_iu6_i1_bta_val_offset = stall_frn_fdis_iu6_i1_btb_hist_offset + 2; + parameter stall_frn_fdis_iu6_i1_fusion_offset = stall_frn_fdis_iu6_i1_bta_val_offset + 1; + parameter stall_frn_fdis_iu6_i1_spec_offset = stall_frn_fdis_iu6_i1_fusion_offset + 20; + parameter stall_frn_fdis_iu6_i1_type_fp_offset = stall_frn_fdis_iu6_i1_spec_offset + 1; + parameter stall_frn_fdis_iu6_i1_type_ap_offset = stall_frn_fdis_iu6_i1_type_fp_offset + 1; + parameter stall_frn_fdis_iu6_i1_type_spv_offset = stall_frn_fdis_iu6_i1_type_ap_offset + 1; + parameter stall_frn_fdis_iu6_i1_type_st_offset = stall_frn_fdis_iu6_i1_type_spv_offset + 1; + parameter stall_frn_fdis_iu6_i1_async_block_offset = stall_frn_fdis_iu6_i1_type_st_offset + 1; + parameter stall_frn_fdis_iu6_i1_np1_flush_offset = stall_frn_fdis_iu6_i1_async_block_offset + 1; + parameter stall_frn_fdis_iu6_i1_core_block_offset = stall_frn_fdis_iu6_i1_np1_flush_offset + 1; + parameter stall_frn_fdis_iu6_i1_isram_offset = stall_frn_fdis_iu6_i1_core_block_offset + 1; + parameter stall_frn_fdis_iu6_i1_isload_offset = stall_frn_fdis_iu6_i1_isram_offset + 1; + parameter stall_frn_fdis_iu6_i1_isstore_offset = stall_frn_fdis_iu6_i1_isload_offset + 1; + parameter stall_frn_fdis_iu6_i1_instr_offset = stall_frn_fdis_iu6_i1_isstore_offset + 1; + parameter stall_frn_fdis_iu6_i1_ifar_offset = stall_frn_fdis_iu6_i1_instr_offset + 32; + parameter stall_frn_fdis_iu6_i1_bta_offset = stall_frn_fdis_iu6_i1_ifar_offset + (`EFF_IFAR_WIDTH); + parameter stall_frn_fdis_iu6_i1_br_pred_offset = stall_frn_fdis_iu6_i1_bta_offset + (`EFF_IFAR_WIDTH); + parameter stall_frn_fdis_iu6_i1_bh_update_offset = stall_frn_fdis_iu6_i1_br_pred_offset + 1; + parameter stall_frn_fdis_iu6_i1_bh0_hist_offset = stall_frn_fdis_iu6_i1_bh_update_offset + 1; + parameter stall_frn_fdis_iu6_i1_bh1_hist_offset = stall_frn_fdis_iu6_i1_bh0_hist_offset + 2; + parameter stall_frn_fdis_iu6_i1_bh2_hist_offset = stall_frn_fdis_iu6_i1_bh1_hist_offset + 2; + parameter stall_frn_fdis_iu6_i1_gshare_offset = stall_frn_fdis_iu6_i1_bh2_hist_offset + 2; + parameter stall_frn_fdis_iu6_i1_ls_ptr_offset = stall_frn_fdis_iu6_i1_gshare_offset + 18; + parameter stall_frn_fdis_iu6_i1_match_offset = stall_frn_fdis_iu6_i1_ls_ptr_offset + 3; + parameter stall_frn_fdis_iu6_i1_ilat_offset = stall_frn_fdis_iu6_i1_match_offset + 1; + parameter stall_frn_fdis_iu6_i1_t1_v_offset = stall_frn_fdis_iu6_i1_ilat_offset + 4; + parameter stall_frn_fdis_iu6_i1_t1_t_offset = stall_frn_fdis_iu6_i1_t1_v_offset + 1; + parameter stall_frn_fdis_iu6_i1_t1_a_offset = stall_frn_fdis_iu6_i1_t1_t_offset + 3; + parameter stall_frn_fdis_iu6_i1_t1_p_offset = stall_frn_fdis_iu6_i1_t1_a_offset + `GPR_POOL_ENC; + parameter stall_frn_fdis_iu6_i1_t2_v_offset = stall_frn_fdis_iu6_i1_t1_p_offset + `GPR_POOL_ENC; + parameter stall_frn_fdis_iu6_i1_t2_a_offset = stall_frn_fdis_iu6_i1_t2_v_offset + 1; + parameter stall_frn_fdis_iu6_i1_t2_p_offset = stall_frn_fdis_iu6_i1_t2_a_offset + `GPR_POOL_ENC; + parameter stall_frn_fdis_iu6_i1_t2_t_offset = stall_frn_fdis_iu6_i1_t2_p_offset + `GPR_POOL_ENC; + parameter stall_frn_fdis_iu6_i1_t3_v_offset = stall_frn_fdis_iu6_i1_t2_t_offset + 3; + parameter stall_frn_fdis_iu6_i1_t3_a_offset = stall_frn_fdis_iu6_i1_t3_v_offset + 1; + parameter stall_frn_fdis_iu6_i1_t3_p_offset = stall_frn_fdis_iu6_i1_t3_a_offset + `GPR_POOL_ENC; + parameter stall_frn_fdis_iu6_i1_t3_t_offset = stall_frn_fdis_iu6_i1_t3_p_offset + `GPR_POOL_ENC; + parameter stall_frn_fdis_iu6_i1_s1_v_offset = stall_frn_fdis_iu6_i1_t3_t_offset + 3; + parameter stall_frn_fdis_iu6_i1_s1_a_offset = stall_frn_fdis_iu6_i1_s1_v_offset + 1; + parameter stall_frn_fdis_iu6_i1_s1_p_offset = stall_frn_fdis_iu6_i1_s1_a_offset + `GPR_POOL_ENC; + parameter stall_frn_fdis_iu6_i1_s1_itag_offset = stall_frn_fdis_iu6_i1_s1_p_offset + `GPR_POOL_ENC; + parameter stall_frn_fdis_iu6_i1_s1_t_offset = stall_frn_fdis_iu6_i1_s1_itag_offset + `ITAG_SIZE_ENC; + parameter stall_frn_fdis_iu6_i1_s1_dep_hit_offset = stall_frn_fdis_iu6_i1_s1_t_offset + 3; + parameter stall_frn_fdis_iu6_i1_s2_v_offset = stall_frn_fdis_iu6_i1_s1_dep_hit_offset + 1; + parameter stall_frn_fdis_iu6_i1_s2_a_offset = stall_frn_fdis_iu6_i1_s2_v_offset + 1; + parameter stall_frn_fdis_iu6_i1_s2_p_offset = stall_frn_fdis_iu6_i1_s2_a_offset + `GPR_POOL_ENC; + parameter stall_frn_fdis_iu6_i1_s2_itag_offset = stall_frn_fdis_iu6_i1_s2_p_offset + `GPR_POOL_ENC; + parameter stall_frn_fdis_iu6_i1_s2_t_offset = stall_frn_fdis_iu6_i1_s2_itag_offset + `ITAG_SIZE_ENC; + parameter stall_frn_fdis_iu6_i1_s2_dep_hit_offset = stall_frn_fdis_iu6_i1_s2_t_offset + 3; + parameter stall_frn_fdis_iu6_i1_s3_v_offset = stall_frn_fdis_iu6_i1_s2_dep_hit_offset + 1; + parameter stall_frn_fdis_iu6_i1_s3_a_offset = stall_frn_fdis_iu6_i1_s3_v_offset + 1; + parameter stall_frn_fdis_iu6_i1_s3_p_offset = stall_frn_fdis_iu6_i1_s3_a_offset + `GPR_POOL_ENC; + parameter stall_frn_fdis_iu6_i1_s3_itag_offset = stall_frn_fdis_iu6_i1_s3_p_offset + `GPR_POOL_ENC; + parameter stall_frn_fdis_iu6_i1_s3_t_offset = stall_frn_fdis_iu6_i1_s3_itag_offset + `ITAG_SIZE_ENC; + parameter stall_frn_fdis_iu6_i1_s3_dep_hit_offset = stall_frn_fdis_iu6_i1_s3_t_offset + 3; + parameter perf_iu5_stall_offset = stall_frn_fdis_iu6_i1_s3_dep_hit_offset + 1; + parameter perf_iu5_cpl_credit_stall_offset = perf_iu5_stall_offset + 1; + parameter perf_iu5_gpr_credit_stall_offset = perf_iu5_cpl_credit_stall_offset + 1; + parameter perf_iu5_cr_credit_stall_offset = perf_iu5_gpr_credit_stall_offset + 1; + parameter perf_iu5_lr_credit_stall_offset = perf_iu5_cr_credit_stall_offset + 1; + parameter perf_iu5_ctr_credit_stall_offset = perf_iu5_lr_credit_stall_offset + 1; + parameter perf_iu5_xer_credit_stall_offset = perf_iu5_ctr_credit_stall_offset + 1; + parameter perf_iu5_br_hold_stall_offset = perf_iu5_xer_credit_stall_offset + 1; + parameter perf_iu5_axu_hold_stall_offset = perf_iu5_br_hold_stall_offset + 1; + parameter scan_right = perf_iu5_axu_hold_stall_offset + 1 - 1; + + + // scan + wire [0:scan_right] siv; + wire [0:scan_right] sov; + wire [0:4] map_siv; + wire [0:4] map_sov; + + wire tidn; + wire tiup; + + // iu6 latches + wire frn_fdis_iu6_i0_act; + wire frn_fdis_iu6_i0_vld_d; + wire frn_fdis_iu6_i0_vld_l2; + wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i0_itag_d; + wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i0_itag_l2; + wire [0:2] frn_fdis_iu6_i0_ucode_d; + wire [0:2] frn_fdis_iu6_i0_ucode_l2; + wire [0:`UCODE_ENTRIES_ENC-1] frn_fdis_iu6_i0_ucode_cnt_d; + wire [0:`UCODE_ENTRIES_ENC-1] frn_fdis_iu6_i0_ucode_cnt_l2; + wire frn_fdis_iu6_i0_2ucode_d; + wire frn_fdis_iu6_i0_2ucode_l2; + wire frn_fdis_iu6_i0_fuse_nop_d; + wire frn_fdis_iu6_i0_fuse_nop_l2; + wire frn_fdis_iu6_i0_rte_lq_d; + wire frn_fdis_iu6_i0_rte_lq_l2; + wire frn_fdis_iu6_i0_rte_sq_d; + wire frn_fdis_iu6_i0_rte_sq_l2; + wire frn_fdis_iu6_i0_rte_fx0_d; + wire frn_fdis_iu6_i0_rte_fx0_l2; + wire frn_fdis_iu6_i0_rte_fx1_d; + wire frn_fdis_iu6_i0_rte_fx1_l2; + wire frn_fdis_iu6_i0_rte_axu0_d; + wire frn_fdis_iu6_i0_rte_axu0_l2; + wire frn_fdis_iu6_i0_rte_axu1_d; + wire frn_fdis_iu6_i0_rte_axu1_l2; + wire frn_fdis_iu6_i0_valop_d; + wire frn_fdis_iu6_i0_valop_l2; + wire frn_fdis_iu6_i0_ord_d; + wire frn_fdis_iu6_i0_ord_l2; + wire frn_fdis_iu6_i0_cord_d; + wire frn_fdis_iu6_i0_cord_l2; + wire [0:2] frn_fdis_iu6_i0_error_d; + wire [0:2] frn_fdis_iu6_i0_error_l2; + wire frn_fdis_iu6_i0_btb_entry_d; + wire frn_fdis_iu6_i0_btb_entry_l2; + wire [0:1] frn_fdis_iu6_i0_btb_hist_d; + wire [0:1] frn_fdis_iu6_i0_btb_hist_l2; + wire frn_fdis_iu6_i0_bta_val_d; + wire frn_fdis_iu6_i0_bta_val_l2; + wire [0:19] frn_fdis_iu6_i0_fusion_d; + wire [0:19] frn_fdis_iu6_i0_fusion_l2; + wire frn_fdis_iu6_i0_spec_d; + wire frn_fdis_iu6_i0_spec_l2; + wire frn_fdis_iu6_i0_type_fp_d; + wire frn_fdis_iu6_i0_type_fp_l2; + wire frn_fdis_iu6_i0_type_ap_d; + wire frn_fdis_iu6_i0_type_ap_l2; + wire frn_fdis_iu6_i0_type_spv_d; + wire frn_fdis_iu6_i0_type_spv_l2; + wire frn_fdis_iu6_i0_type_st_d; + wire frn_fdis_iu6_i0_type_st_l2; + wire frn_fdis_iu6_i0_async_block_d; + wire frn_fdis_iu6_i0_async_block_l2; + wire frn_fdis_iu6_i0_np1_flush_d; + wire frn_fdis_iu6_i0_np1_flush_l2; + wire frn_fdis_iu6_i0_core_block_d; + wire frn_fdis_iu6_i0_core_block_l2; + wire frn_fdis_iu6_i0_isram_d; + wire frn_fdis_iu6_i0_isram_l2; + wire frn_fdis_iu6_i0_isload_d; + wire frn_fdis_iu6_i0_isload_l2; + wire frn_fdis_iu6_i0_isstore_d; + wire frn_fdis_iu6_i0_isstore_l2; + wire [0:31] frn_fdis_iu6_i0_instr_d; + wire [0:31] frn_fdis_iu6_i0_instr_l2; + wire [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_i0_ifar_d; + wire [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_i0_ifar_l2; + wire [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_i0_bta_d; + wire [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_i0_bta_l2; + wire frn_fdis_iu6_i0_br_pred_d; + wire frn_fdis_iu6_i0_br_pred_l2; + wire frn_fdis_iu6_i0_bh_update_d; + wire frn_fdis_iu6_i0_bh_update_l2; + wire [0:1] frn_fdis_iu6_i0_bh0_hist_d; + wire [0:1] frn_fdis_iu6_i0_bh0_hist_l2; + wire [0:1] frn_fdis_iu6_i0_bh1_hist_d; + wire [0:1] frn_fdis_iu6_i0_bh1_hist_l2; + wire [0:1] frn_fdis_iu6_i0_bh2_hist_d; + wire [0:1] frn_fdis_iu6_i0_bh2_hist_l2; + wire [0:17] frn_fdis_iu6_i0_gshare_d; + wire [0:17] frn_fdis_iu6_i0_gshare_l2; + wire [0:2] frn_fdis_iu6_i0_ls_ptr_d; + wire [0:2] frn_fdis_iu6_i0_ls_ptr_l2; + wire frn_fdis_iu6_i0_match_d; + wire frn_fdis_iu6_i0_match_l2; + wire [0:3] frn_fdis_iu6_i0_ilat_d; + wire [0:3] frn_fdis_iu6_i0_ilat_l2; + wire frn_fdis_iu6_i0_t1_v_d; + wire frn_fdis_iu6_i0_t1_v_l2; + wire [0:2] frn_fdis_iu6_i0_t1_t_d; + wire [0:2] frn_fdis_iu6_i0_t1_t_l2; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t1_a_d; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t1_a_l2; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t1_p_d; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t1_p_l2; + wire frn_fdis_iu6_i0_t2_v_d; + wire frn_fdis_iu6_i0_t2_v_l2; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t2_a_d; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t2_a_l2; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t2_p_d; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t2_p_l2; + wire [0:2] frn_fdis_iu6_i0_t2_t_d; + wire [0:2] frn_fdis_iu6_i0_t2_t_l2; + wire frn_fdis_iu6_i0_t3_v_d; + wire frn_fdis_iu6_i0_t3_v_l2; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t3_a_d; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t3_a_l2; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t3_p_d; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t3_p_l2; + wire [0:2] frn_fdis_iu6_i0_t3_t_d; + wire [0:2] frn_fdis_iu6_i0_t3_t_l2; + wire frn_fdis_iu6_i0_s1_v_d; + wire frn_fdis_iu6_i0_s1_v_l2; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s1_a_d; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s1_a_l2; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s1_p_d; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s1_p_l2; + wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i0_s1_itag_d; + wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i0_s1_itag_l2; + wire [0:2] frn_fdis_iu6_i0_s1_t_d; + wire [0:2] frn_fdis_iu6_i0_s1_t_l2; + wire frn_fdis_iu6_i0_s2_v_d; + wire frn_fdis_iu6_i0_s2_v_l2; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s2_a_d; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s2_a_l2; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s2_p_d; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s2_p_l2; + wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i0_s2_itag_d; + wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i0_s2_itag_l2; + wire [0:2] frn_fdis_iu6_i0_s2_t_d; + wire [0:2] frn_fdis_iu6_i0_s2_t_l2; + wire frn_fdis_iu6_i0_s3_v_d; + wire frn_fdis_iu6_i0_s3_v_l2; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s3_a_d; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s3_a_l2; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s3_p_d; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s3_p_l2; + wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i0_s3_itag_d; + wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i0_s3_itag_l2; + wire [0:2] frn_fdis_iu6_i0_s3_t_d; + wire [0:2] frn_fdis_iu6_i0_s3_t_l2; + wire frn_fdis_iu6_i1_act; + wire frn_fdis_iu6_i1_vld_d; + wire frn_fdis_iu6_i1_vld_l2; + wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i1_itag_d; + wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i1_itag_l2; + wire [0:2] frn_fdis_iu6_i1_ucode_d; + wire [0:2] frn_fdis_iu6_i1_ucode_l2; + wire [0:`UCODE_ENTRIES_ENC-1] frn_fdis_iu6_i1_ucode_cnt_d; + wire [0:`UCODE_ENTRIES_ENC-1] frn_fdis_iu6_i1_ucode_cnt_l2; + wire frn_fdis_iu6_i1_fuse_nop_d; + wire frn_fdis_iu6_i1_fuse_nop_l2; + wire frn_fdis_iu6_i1_rte_lq_d; + wire frn_fdis_iu6_i1_rte_lq_l2; + wire frn_fdis_iu6_i1_rte_sq_d; + wire frn_fdis_iu6_i1_rte_sq_l2; + wire frn_fdis_iu6_i1_rte_fx0_d; + wire frn_fdis_iu6_i1_rte_fx0_l2; + wire frn_fdis_iu6_i1_rte_fx1_d; + wire frn_fdis_iu6_i1_rte_fx1_l2; + wire frn_fdis_iu6_i1_rte_axu0_d; + wire frn_fdis_iu6_i1_rte_axu0_l2; + wire frn_fdis_iu6_i1_rte_axu1_d; + wire frn_fdis_iu6_i1_rte_axu1_l2; + wire frn_fdis_iu6_i1_valop_d; + wire frn_fdis_iu6_i1_valop_l2; + wire frn_fdis_iu6_i1_ord_d; + wire frn_fdis_iu6_i1_ord_l2; + wire frn_fdis_iu6_i1_cord_d; + wire frn_fdis_iu6_i1_cord_l2; + wire [0:2] frn_fdis_iu6_i1_error_d; + wire [0:2] frn_fdis_iu6_i1_error_l2; + wire frn_fdis_iu6_i1_btb_entry_d; + wire frn_fdis_iu6_i1_btb_entry_l2; + wire [0:1] frn_fdis_iu6_i1_btb_hist_d; + wire [0:1] frn_fdis_iu6_i1_btb_hist_l2; + wire frn_fdis_iu6_i1_bta_val_d; + wire frn_fdis_iu6_i1_bta_val_l2; + wire [0:19] frn_fdis_iu6_i1_fusion_d; + wire [0:19] frn_fdis_iu6_i1_fusion_l2; + wire frn_fdis_iu6_i1_spec_d; + wire frn_fdis_iu6_i1_spec_l2; + wire frn_fdis_iu6_i1_type_fp_d; + wire frn_fdis_iu6_i1_type_fp_l2; + wire frn_fdis_iu6_i1_type_ap_d; + wire frn_fdis_iu6_i1_type_ap_l2; + wire frn_fdis_iu6_i1_type_spv_d; + wire frn_fdis_iu6_i1_type_spv_l2; + wire frn_fdis_iu6_i1_type_st_d; + wire frn_fdis_iu6_i1_type_st_l2; + wire frn_fdis_iu6_i1_async_block_d; + wire frn_fdis_iu6_i1_async_block_l2; + wire frn_fdis_iu6_i1_np1_flush_d; + wire frn_fdis_iu6_i1_np1_flush_l2; + wire frn_fdis_iu6_i1_core_block_d; + wire frn_fdis_iu6_i1_core_block_l2; + wire frn_fdis_iu6_i1_isram_d; + wire frn_fdis_iu6_i1_isram_l2; + wire frn_fdis_iu6_i1_isload_d; + wire frn_fdis_iu6_i1_isload_l2; + wire frn_fdis_iu6_i1_isstore_d; + wire frn_fdis_iu6_i1_isstore_l2; + wire [0:31] frn_fdis_iu6_i1_instr_d; + wire [0:31] frn_fdis_iu6_i1_instr_l2; + wire [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_i1_ifar_d; + wire [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_i1_ifar_l2; + wire [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_i1_bta_d; + wire [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_i1_bta_l2; + wire frn_fdis_iu6_i1_br_pred_d; + wire frn_fdis_iu6_i1_br_pred_l2; + wire frn_fdis_iu6_i1_bh_update_d; + wire frn_fdis_iu6_i1_bh_update_l2; + wire [0:1] frn_fdis_iu6_i1_bh0_hist_d; + wire [0:1] frn_fdis_iu6_i1_bh0_hist_l2; + wire [0:1] frn_fdis_iu6_i1_bh1_hist_d; + wire [0:1] frn_fdis_iu6_i1_bh1_hist_l2; + wire [0:1] frn_fdis_iu6_i1_bh2_hist_d; + wire [0:1] frn_fdis_iu6_i1_bh2_hist_l2; + wire [0:17] frn_fdis_iu6_i1_gshare_d; + wire [0:17] frn_fdis_iu6_i1_gshare_l2; + wire [0:2] frn_fdis_iu6_i1_ls_ptr_d; + wire [0:2] frn_fdis_iu6_i1_ls_ptr_l2; + wire frn_fdis_iu6_i1_match_d; + wire frn_fdis_iu6_i1_match_l2; + wire [0:3] frn_fdis_iu6_i1_ilat_d; + wire [0:3] frn_fdis_iu6_i1_ilat_l2; + wire frn_fdis_iu6_i1_t1_v_d; + wire frn_fdis_iu6_i1_t1_v_l2; + wire [0:2] frn_fdis_iu6_i1_t1_t_d; + wire [0:2] frn_fdis_iu6_i1_t1_t_l2; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t1_a_d; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t1_a_l2; + reg [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t1_p_d; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t1_p_l2; + wire frn_fdis_iu6_i1_t2_v_d; + wire frn_fdis_iu6_i1_t2_v_l2; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t2_a_d; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t2_a_l2; + reg [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t2_p_d; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t2_p_l2; + wire [0:2] frn_fdis_iu6_i1_t2_t_d; + wire [0:2] frn_fdis_iu6_i1_t2_t_l2; + wire frn_fdis_iu6_i1_t3_v_d; + wire frn_fdis_iu6_i1_t3_v_l2; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t3_a_d; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t3_a_l2; + reg [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t3_p_d; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t3_p_l2; + wire [0:2] frn_fdis_iu6_i1_t3_t_d; + wire [0:2] frn_fdis_iu6_i1_t3_t_l2; + wire frn_fdis_iu6_i1_s1_v_d; + wire frn_fdis_iu6_i1_s1_v_l2; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s1_a_d; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s1_a_l2; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s1_p_d; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s1_p_l2; + wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i1_s1_itag_d; + wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i1_s1_itag_l2; + wire [0:2] frn_fdis_iu6_i1_s1_t_d; + wire [0:2] frn_fdis_iu6_i1_s1_t_l2; + wire frn_fdis_iu6_i1_s1_dep_hit_d; + wire frn_fdis_iu6_i1_s1_dep_hit_l2; + wire frn_fdis_iu6_i1_s2_v_d; + wire frn_fdis_iu6_i1_s2_v_l2; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s2_a_d; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s2_a_l2; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s2_p_d; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s2_p_l2; + wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i1_s2_itag_d; + wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i1_s2_itag_l2; + wire [0:2] frn_fdis_iu6_i1_s2_t_d; + wire [0:2] frn_fdis_iu6_i1_s2_t_l2; + wire frn_fdis_iu6_i1_s2_dep_hit_d; + wire frn_fdis_iu6_i1_s2_dep_hit_l2; + wire frn_fdis_iu6_i1_s3_v_d; + wire frn_fdis_iu6_i1_s3_v_l2; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s3_a_d; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s3_a_l2; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s3_p_d; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s3_p_l2; + wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i1_s3_itag_d; + wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i1_s3_itag_l2; + wire [0:2] frn_fdis_iu6_i1_s3_t_d; + wire [0:2] frn_fdis_iu6_i1_s3_t_l2; + wire frn_fdis_iu6_i1_s3_dep_hit_d; + wire frn_fdis_iu6_i1_s3_dep_hit_l2; + + // iu6 stall latches + wire stall_frn_fdis_iu6_i0_act; + wire stall_frn_fdis_iu6_i0_vld_d; + wire stall_frn_fdis_iu6_i0_vld_l2; + wire [0:`ITAG_SIZE_ENC-1] stall_frn_fdis_iu6_i0_itag_d; + wire [0:`ITAG_SIZE_ENC-1] stall_frn_fdis_iu6_i0_itag_l2; + wire [0:2] stall_frn_fdis_iu6_i0_ucode_d; + wire [0:2] stall_frn_fdis_iu6_i0_ucode_l2; + wire [0:`UCODE_ENTRIES_ENC-1] stall_frn_fdis_iu6_i0_ucode_cnt_d; + wire [0:`UCODE_ENTRIES_ENC-1] stall_frn_fdis_iu6_i0_ucode_cnt_l2; + wire stall_frn_fdis_iu6_i0_2ucode_d; + wire stall_frn_fdis_iu6_i0_2ucode_l2; + wire stall_frn_fdis_iu6_i0_fuse_nop_d; + wire stall_frn_fdis_iu6_i0_fuse_nop_l2; + wire stall_frn_fdis_iu6_i0_rte_lq_d; + wire stall_frn_fdis_iu6_i0_rte_lq_l2; + wire stall_frn_fdis_iu6_i0_rte_sq_d; + wire stall_frn_fdis_iu6_i0_rte_sq_l2; + wire stall_frn_fdis_iu6_i0_rte_fx0_d; + wire stall_frn_fdis_iu6_i0_rte_fx0_l2; + wire stall_frn_fdis_iu6_i0_rte_fx1_d; + wire stall_frn_fdis_iu6_i0_rte_fx1_l2; + wire stall_frn_fdis_iu6_i0_rte_axu0_d; + wire stall_frn_fdis_iu6_i0_rte_axu0_l2; + wire stall_frn_fdis_iu6_i0_rte_axu1_d; + wire stall_frn_fdis_iu6_i0_rte_axu1_l2; + wire stall_frn_fdis_iu6_i0_valop_d; + wire stall_frn_fdis_iu6_i0_valop_l2; + wire stall_frn_fdis_iu6_i0_ord_d; + wire stall_frn_fdis_iu6_i0_ord_l2; + wire stall_frn_fdis_iu6_i0_cord_d; + wire stall_frn_fdis_iu6_i0_cord_l2; + wire [0:2] stall_frn_fdis_iu6_i0_error_d; + wire [0:2] stall_frn_fdis_iu6_i0_error_l2; + wire stall_frn_fdis_iu6_i0_btb_entry_d; + wire stall_frn_fdis_iu6_i0_btb_entry_l2; + wire [0:1] stall_frn_fdis_iu6_i0_btb_hist_d; + wire [0:1] stall_frn_fdis_iu6_i0_btb_hist_l2; + wire stall_frn_fdis_iu6_i0_bta_val_d; + wire stall_frn_fdis_iu6_i0_bta_val_l2; + wire [0:19] stall_frn_fdis_iu6_i0_fusion_d; + wire [0:19] stall_frn_fdis_iu6_i0_fusion_l2; + wire stall_frn_fdis_iu6_i0_spec_d; + wire stall_frn_fdis_iu6_i0_spec_l2; + wire stall_frn_fdis_iu6_i0_type_fp_d; + wire stall_frn_fdis_iu6_i0_type_fp_l2; + wire stall_frn_fdis_iu6_i0_type_ap_d; + wire stall_frn_fdis_iu6_i0_type_ap_l2; + wire stall_frn_fdis_iu6_i0_type_spv_d; + wire stall_frn_fdis_iu6_i0_type_spv_l2; + wire stall_frn_fdis_iu6_i0_type_st_d; + wire stall_frn_fdis_iu6_i0_type_st_l2; + wire stall_frn_fdis_iu6_i0_async_block_d; + wire stall_frn_fdis_iu6_i0_async_block_l2; + wire stall_frn_fdis_iu6_i0_np1_flush_d; + wire stall_frn_fdis_iu6_i0_np1_flush_l2; + wire stall_frn_fdis_iu6_i0_core_block_d; + wire stall_frn_fdis_iu6_i0_core_block_l2; + wire stall_frn_fdis_iu6_i0_isram_d; + wire stall_frn_fdis_iu6_i0_isram_l2; + wire stall_frn_fdis_iu6_i0_isload_d; + wire stall_frn_fdis_iu6_i0_isload_l2; + wire stall_frn_fdis_iu6_i0_isstore_d; + wire stall_frn_fdis_iu6_i0_isstore_l2; + wire [0:31] stall_frn_fdis_iu6_i0_instr_d; + wire [0:31] stall_frn_fdis_iu6_i0_instr_l2; + wire [62-`EFF_IFAR_WIDTH:61] stall_frn_fdis_iu6_i0_ifar_d; + wire [62-`EFF_IFAR_WIDTH:61] stall_frn_fdis_iu6_i0_ifar_l2; + wire [62-`EFF_IFAR_WIDTH:61] stall_frn_fdis_iu6_i0_bta_d; + wire [62-`EFF_IFAR_WIDTH:61] stall_frn_fdis_iu6_i0_bta_l2; + wire stall_frn_fdis_iu6_i0_br_pred_d; + wire stall_frn_fdis_iu6_i0_br_pred_l2; + wire stall_frn_fdis_iu6_i0_bh_update_d; + wire stall_frn_fdis_iu6_i0_bh_update_l2; + wire [0:1] stall_frn_fdis_iu6_i0_bh0_hist_d; + wire [0:1] stall_frn_fdis_iu6_i0_bh0_hist_l2; + wire [0:1] stall_frn_fdis_iu6_i0_bh1_hist_d; + wire [0:1] stall_frn_fdis_iu6_i0_bh1_hist_l2; + wire [0:1] stall_frn_fdis_iu6_i0_bh2_hist_d; + wire [0:1] stall_frn_fdis_iu6_i0_bh2_hist_l2; + wire [0:17] stall_frn_fdis_iu6_i0_gshare_d; + wire [0:17] stall_frn_fdis_iu6_i0_gshare_l2; + wire [0:2] stall_frn_fdis_iu6_i0_ls_ptr_d; + wire [0:2] stall_frn_fdis_iu6_i0_ls_ptr_l2; + wire stall_frn_fdis_iu6_i0_match_d; + wire stall_frn_fdis_iu6_i0_match_l2; + wire [0:3] stall_frn_fdis_iu6_i0_ilat_d; + wire [0:3] stall_frn_fdis_iu6_i0_ilat_l2; + wire stall_frn_fdis_iu6_i0_t1_v_d; + wire stall_frn_fdis_iu6_i0_t1_v_l2; + wire [0:2] stall_frn_fdis_iu6_i0_t1_t_d; + wire [0:2] stall_frn_fdis_iu6_i0_t1_t_l2; + wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i0_t1_a_d; + wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i0_t1_a_l2; + wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i0_t1_p_d; + wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i0_t1_p_l2; + wire stall_frn_fdis_iu6_i0_t2_v_d; + wire stall_frn_fdis_iu6_i0_t2_v_l2; + wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i0_t2_a_d; + wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i0_t2_a_l2; + wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i0_t2_p_d; + wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i0_t2_p_l2; + wire [0:2] stall_frn_fdis_iu6_i0_t2_t_d; + wire [0:2] stall_frn_fdis_iu6_i0_t2_t_l2; + wire stall_frn_fdis_iu6_i0_t3_v_d; + wire stall_frn_fdis_iu6_i0_t3_v_l2; + wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i0_t3_a_d; + wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i0_t3_a_l2; + wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i0_t3_p_d; + wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i0_t3_p_l2; + wire [0:2] stall_frn_fdis_iu6_i0_t3_t_d; + wire [0:2] stall_frn_fdis_iu6_i0_t3_t_l2; + wire stall_frn_fdis_iu6_i0_s1_v_d; + wire stall_frn_fdis_iu6_i0_s1_v_l2; + wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i0_s1_a_d; + wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i0_s1_a_l2; + wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i0_s1_p_d; + wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i0_s1_p_l2; + wire [0:`ITAG_SIZE_ENC-1] stall_frn_fdis_iu6_i0_s1_itag_d; + wire [0:`ITAG_SIZE_ENC-1] stall_frn_fdis_iu6_i0_s1_itag_l2; + wire [0:2] stall_frn_fdis_iu6_i0_s1_t_d; + wire [0:2] stall_frn_fdis_iu6_i0_s1_t_l2; + wire stall_frn_fdis_iu6_i0_s2_v_d; + wire stall_frn_fdis_iu6_i0_s2_v_l2; + wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i0_s2_a_d; + wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i0_s2_a_l2; + wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i0_s2_p_d; + wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i0_s2_p_l2; + wire [0:`ITAG_SIZE_ENC-1] stall_frn_fdis_iu6_i0_s2_itag_d; + wire [0:`ITAG_SIZE_ENC-1] stall_frn_fdis_iu6_i0_s2_itag_l2; + wire [0:2] stall_frn_fdis_iu6_i0_s2_t_d; + wire [0:2] stall_frn_fdis_iu6_i0_s2_t_l2; + wire stall_frn_fdis_iu6_i0_s3_v_d; + wire stall_frn_fdis_iu6_i0_s3_v_l2; + wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i0_s3_a_d; + wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i0_s3_a_l2; + wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i0_s3_p_d; + wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i0_s3_p_l2; + wire [0:`ITAG_SIZE_ENC-1] stall_frn_fdis_iu6_i0_s3_itag_d; + wire [0:`ITAG_SIZE_ENC-1] stall_frn_fdis_iu6_i0_s3_itag_l2; + wire [0:2] stall_frn_fdis_iu6_i0_s3_t_d; + wire [0:2] stall_frn_fdis_iu6_i0_s3_t_l2; + wire stall_frn_fdis_iu6_i1_act; + wire stall_frn_fdis_iu6_i1_vld_d; + wire stall_frn_fdis_iu6_i1_vld_l2; + wire [0:`ITAG_SIZE_ENC-1] stall_frn_fdis_iu6_i1_itag_d; + wire [0:`ITAG_SIZE_ENC-1] stall_frn_fdis_iu6_i1_itag_l2; + wire [0:2] stall_frn_fdis_iu6_i1_ucode_d; + wire [0:2] stall_frn_fdis_iu6_i1_ucode_l2; + wire [0:`UCODE_ENTRIES_ENC-1] stall_frn_fdis_iu6_i1_ucode_cnt_d; + wire [0:`UCODE_ENTRIES_ENC-1] stall_frn_fdis_iu6_i1_ucode_cnt_l2; + wire stall_frn_fdis_iu6_i1_fuse_nop_d; + wire stall_frn_fdis_iu6_i1_fuse_nop_l2; + wire stall_frn_fdis_iu6_i1_rte_lq_d; + wire stall_frn_fdis_iu6_i1_rte_lq_l2; + wire stall_frn_fdis_iu6_i1_rte_sq_d; + wire stall_frn_fdis_iu6_i1_rte_sq_l2; + wire stall_frn_fdis_iu6_i1_rte_fx0_d; + wire stall_frn_fdis_iu6_i1_rte_fx0_l2; + wire stall_frn_fdis_iu6_i1_rte_fx1_d; + wire stall_frn_fdis_iu6_i1_rte_fx1_l2; + wire stall_frn_fdis_iu6_i1_rte_axu0_d; + wire stall_frn_fdis_iu6_i1_rte_axu0_l2; + wire stall_frn_fdis_iu6_i1_rte_axu1_d; + wire stall_frn_fdis_iu6_i1_rte_axu1_l2; + wire stall_frn_fdis_iu6_i1_valop_d; + wire stall_frn_fdis_iu6_i1_valop_l2; + wire stall_frn_fdis_iu6_i1_ord_d; + wire stall_frn_fdis_iu6_i1_ord_l2; + wire stall_frn_fdis_iu6_i1_cord_d; + wire stall_frn_fdis_iu6_i1_cord_l2; + wire [0:2] stall_frn_fdis_iu6_i1_error_d; + wire [0:2] stall_frn_fdis_iu6_i1_error_l2; + wire stall_frn_fdis_iu6_i1_btb_entry_d; + wire stall_frn_fdis_iu6_i1_btb_entry_l2; + wire [0:1] stall_frn_fdis_iu6_i1_btb_hist_d; + wire [0:1] stall_frn_fdis_iu6_i1_btb_hist_l2; + wire stall_frn_fdis_iu6_i1_bta_val_d; + wire stall_frn_fdis_iu6_i1_bta_val_l2; + wire [0:19] stall_frn_fdis_iu6_i1_fusion_d; + wire [0:19] stall_frn_fdis_iu6_i1_fusion_l2; + wire stall_frn_fdis_iu6_i1_spec_d; + wire stall_frn_fdis_iu6_i1_spec_l2; + wire stall_frn_fdis_iu6_i1_type_fp_d; + wire stall_frn_fdis_iu6_i1_type_fp_l2; + wire stall_frn_fdis_iu6_i1_type_ap_d; + wire stall_frn_fdis_iu6_i1_type_ap_l2; + wire stall_frn_fdis_iu6_i1_type_spv_d; + wire stall_frn_fdis_iu6_i1_type_spv_l2; + wire stall_frn_fdis_iu6_i1_type_st_d; + wire stall_frn_fdis_iu6_i1_type_st_l2; + wire stall_frn_fdis_iu6_i1_async_block_d; + wire stall_frn_fdis_iu6_i1_async_block_l2; + wire stall_frn_fdis_iu6_i1_np1_flush_d; + wire stall_frn_fdis_iu6_i1_np1_flush_l2; + wire stall_frn_fdis_iu6_i1_core_block_d; + wire stall_frn_fdis_iu6_i1_core_block_l2; + wire stall_frn_fdis_iu6_i1_isram_d; + wire stall_frn_fdis_iu6_i1_isram_l2; + wire stall_frn_fdis_iu6_i1_isload_d; + wire stall_frn_fdis_iu6_i1_isload_l2; + wire stall_frn_fdis_iu6_i1_isstore_d; + wire stall_frn_fdis_iu6_i1_isstore_l2; + wire [0:31] stall_frn_fdis_iu6_i1_instr_d; + wire [0:31] stall_frn_fdis_iu6_i1_instr_l2; + wire [62-`EFF_IFAR_WIDTH:61] stall_frn_fdis_iu6_i1_ifar_d; + wire [62-`EFF_IFAR_WIDTH:61] stall_frn_fdis_iu6_i1_ifar_l2; + wire [62-`EFF_IFAR_WIDTH:61] stall_frn_fdis_iu6_i1_bta_d; + wire [62-`EFF_IFAR_WIDTH:61] stall_frn_fdis_iu6_i1_bta_l2; + wire stall_frn_fdis_iu6_i1_br_pred_d; + wire stall_frn_fdis_iu6_i1_br_pred_l2; + wire stall_frn_fdis_iu6_i1_bh_update_d; + wire stall_frn_fdis_iu6_i1_bh_update_l2; + wire [0:1] stall_frn_fdis_iu6_i1_bh0_hist_d; + wire [0:1] stall_frn_fdis_iu6_i1_bh0_hist_l2; + wire [0:1] stall_frn_fdis_iu6_i1_bh1_hist_d; + wire [0:1] stall_frn_fdis_iu6_i1_bh1_hist_l2; + wire [0:1] stall_frn_fdis_iu6_i1_bh2_hist_d; + wire [0:1] stall_frn_fdis_iu6_i1_bh2_hist_l2; + wire [0:17] stall_frn_fdis_iu6_i1_gshare_d; + wire [0:17] stall_frn_fdis_iu6_i1_gshare_l2; + wire [0:2] stall_frn_fdis_iu6_i1_ls_ptr_d; + wire [0:2] stall_frn_fdis_iu6_i1_ls_ptr_l2; + wire stall_frn_fdis_iu6_i1_match_d; + wire stall_frn_fdis_iu6_i1_match_l2; + wire [0:3] stall_frn_fdis_iu6_i1_ilat_d; + wire [0:3] stall_frn_fdis_iu6_i1_ilat_l2; + wire stall_frn_fdis_iu6_i1_t1_v_d; + wire stall_frn_fdis_iu6_i1_t1_v_l2; + wire [0:2] stall_frn_fdis_iu6_i1_t1_t_d; + wire [0:2] stall_frn_fdis_iu6_i1_t1_t_l2; + wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i1_t1_a_d; + wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i1_t1_a_l2; + wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i1_t1_p_d; + wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i1_t1_p_l2; + wire stall_frn_fdis_iu6_i1_t2_v_d; + wire stall_frn_fdis_iu6_i1_t2_v_l2; + wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i1_t2_a_d; + wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i1_t2_a_l2; + wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i1_t2_p_d; + wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i1_t2_p_l2; + wire [0:2] stall_frn_fdis_iu6_i1_t2_t_d; + wire [0:2] stall_frn_fdis_iu6_i1_t2_t_l2; + wire stall_frn_fdis_iu6_i1_t3_v_d; + wire stall_frn_fdis_iu6_i1_t3_v_l2; + wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i1_t3_a_d; + wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i1_t3_a_l2; + wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i1_t3_p_d; + wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i1_t3_p_l2; + wire [0:2] stall_frn_fdis_iu6_i1_t3_t_d; + wire [0:2] stall_frn_fdis_iu6_i1_t3_t_l2; + wire stall_frn_fdis_iu6_i1_s1_v_d; + wire stall_frn_fdis_iu6_i1_s1_v_l2; + wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i1_s1_a_d; + wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i1_s1_a_l2; + wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i1_s1_p_d; + wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i1_s1_p_l2; + wire [0:`ITAG_SIZE_ENC-1] stall_frn_fdis_iu6_i1_s1_itag_d; + wire [0:`ITAG_SIZE_ENC-1] stall_frn_fdis_iu6_i1_s1_itag_l2; + wire [0:2] stall_frn_fdis_iu6_i1_s1_t_d; + wire [0:2] stall_frn_fdis_iu6_i1_s1_t_l2; + wire stall_frn_fdis_iu6_i1_s1_dep_hit_d; + wire stall_frn_fdis_iu6_i1_s1_dep_hit_l2; + wire stall_frn_fdis_iu6_i1_s2_v_d; + wire stall_frn_fdis_iu6_i1_s2_v_l2; + wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i1_s2_a_d; + wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i1_s2_a_l2; + wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i1_s2_p_d; + wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i1_s2_p_l2; + wire [0:`ITAG_SIZE_ENC-1] stall_frn_fdis_iu6_i1_s2_itag_d; + wire [0:`ITAG_SIZE_ENC-1] stall_frn_fdis_iu6_i1_s2_itag_l2; + wire [0:2] stall_frn_fdis_iu6_i1_s2_t_d; + wire [0:2] stall_frn_fdis_iu6_i1_s2_t_l2; + wire stall_frn_fdis_iu6_i1_s2_dep_hit_d; + wire stall_frn_fdis_iu6_i1_s2_dep_hit_l2; + wire stall_frn_fdis_iu6_i1_s3_v_d; + wire stall_frn_fdis_iu6_i1_s3_v_l2; + wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i1_s3_a_d; + wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i1_s3_a_l2; + wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i1_s3_p_d; + wire [0:`GPR_POOL_ENC-1] stall_frn_fdis_iu6_i1_s3_p_l2; + wire [0:`ITAG_SIZE_ENC-1] stall_frn_fdis_iu6_i1_s3_itag_d; + wire [0:`ITAG_SIZE_ENC-1] stall_frn_fdis_iu6_i1_s3_itag_l2; + wire [0:2] stall_frn_fdis_iu6_i1_s3_t_d; + wire [0:2] stall_frn_fdis_iu6_i1_s3_t_l2; + wire stall_frn_fdis_iu6_i1_s3_dep_hit_d; + wire stall_frn_fdis_iu6_i1_s3_dep_hit_l2; + + //stall + wire [0:18] fdis_frn_iu6_stall_d; + wire [0:18] fdis_frn_iu6_stall_l2; + wire fdis_frn_iu6_stall_dly; + + // Next Itags + wire [0:`ITAG_SIZE_ENC-1] next_itag_0_d; + wire [0:`ITAG_SIZE_ENC-1] next_itag_0_l2; + wire [0:`ITAG_SIZE_ENC-1] next_itag_1_d; + wire [0:`ITAG_SIZE_ENC-1] next_itag_1_l2; + wire [0:`ITAG_SIZE_ENC-1] i0_itag_next; + wire [0:`ITAG_SIZE_ENC-1] i1_itag_next; + wire inc_0; + wire inc_1; + + // Credit counters + reg [0:`CPL_Q_DEPTH_ENC] cp_high_credit_cnt_d; + wire [0:`CPL_Q_DEPTH_ENC] cp_high_credit_cnt_l2; + reg [0:`CPL_Q_DEPTH_ENC] cp_med_credit_cnt_d; + wire [0:`CPL_Q_DEPTH_ENC] cp_med_credit_cnt_l2; + + wire [0:`CPL_Q_DEPTH_ENC] cp_credit_cnt_mux; + + wire [0:`CPL_Q_DEPTH_ENC] high_cnt_plus2_temp, high_cnt_plus2; + wire [0:`CPL_Q_DEPTH_ENC] high_cnt_plus1_temp, high_cnt_plus1; + wire [0:`CPL_Q_DEPTH_ENC] high_cnt_minus1_temp, high_cnt_minus1; + wire [0:`CPL_Q_DEPTH_ENC] high_cnt_minus2_temp, high_cnt_minus2; + wire [0:`CPL_Q_DEPTH_ENC] med_cnt_plus2_temp, med_cnt_plus2; + wire [0:`CPL_Q_DEPTH_ENC] med_cnt_plus1_temp, med_cnt_plus1; + wire [0:`CPL_Q_DEPTH_ENC] med_cnt_minus1_temp, med_cnt_minus1; + wire [0:`CPL_Q_DEPTH_ENC] med_cnt_minus2_temp, med_cnt_minus2; + + // Rolling count for ucode instructions + reg [0:`UCODE_ENTRIES_ENC-1] ucode_cnt_d; + wire [0:`UCODE_ENTRIES_ENC-1] ucode_cnt_l2; + // Save count to flush to for flushing to ucode + reg [0:`UCODE_ENTRIES_ENC-1] ucode_cnt_save_d; + wire [0:`UCODE_ENTRIES_ENC-1] ucode_cnt_save_l2; + + // Latch to delay the flush signal + wire cp_flush_d; + wire cp_flush_l2; + wire cp_flush_into_uc_d; + wire cp_flush_into_uc_l2; + wire br_iu_hold_d; + wire br_iu_hold_l2; + wire hold_instructions_d; + wire hold_instructions_l2; + + // completion queue is empty + wire cp_rn_empty_l2; + + wire high_pri_mask_l2; + + // Source lookups from pools note may not be valid if source if type not of the right type + wire [0:`GPR_POOL_ENC-1] gpr_iu5_i0_src1_p; + wire [0:`GPR_POOL_ENC-1] gpr_iu5_i0_src2_p; + wire [0:`GPR_POOL_ENC-1] gpr_iu5_i0_src3_p; + wire [0:`GPR_POOL_ENC-1] gpr_iu5_i1_src1_p; + wire [0:`GPR_POOL_ENC-1] gpr_iu5_i1_src2_p; + wire [0:`GPR_POOL_ENC-1] gpr_iu5_i1_src3_p; + + // Source lookups from pools note may not be valid if source if type not of the right type + wire [0:`ITAG_SIZE_ENC-1] gpr_iu5_i0_src1_itag; + wire [0:`ITAG_SIZE_ENC-1] gpr_iu5_i0_src2_itag; + wire [0:`ITAG_SIZE_ENC-1] gpr_iu5_i0_src3_itag; + wire [0:`ITAG_SIZE_ENC-1] gpr_iu5_i1_src1_itag; + wire [0:`ITAG_SIZE_ENC-1] gpr_iu5_i1_src2_itag; + wire [0:`ITAG_SIZE_ENC-1] gpr_iu5_i1_src3_itag; + + // I1 dependency hit vs I0 for each source this is used by RV + wire gpr_s1_dep_hit; + wire gpr_s2_dep_hit; + wire gpr_s3_dep_hit; + + // Free from completion to the gpr pool + wire gpr_cp_i0_wr_v; + wire [0:`GPR_POOL_ENC-1] gpr_cp_i0_wr_a; + wire [0:`GPR_POOL_ENC-1] gpr_cp_i0_wr_p; + wire [0:`ITAG_SIZE_ENC-1] gpr_cp_i0_wr_itag; + wire gpr_cp_i1_wr_v; + wire [0:`GPR_POOL_ENC-1] gpr_cp_i1_wr_a; + wire [0:`GPR_POOL_ENC-1] gpr_cp_i1_wr_p; + wire [0:`ITAG_SIZE_ENC-1] gpr_cp_i1_wr_itag; + + wire gpr_spec_i0_wr_v; + wire gpr_spec_i0_wr_v_fast; + wire [0:`GPR_POOL_ENC-1] gpr_spec_i0_wr_a; + wire [0:`GPR_POOL_ENC-1] gpr_spec_i0_wr_p; + wire [0:`ITAG_SIZE_ENC-1] gpr_spec_i0_wr_itag; + wire gpr_spec_i1_wr_v; + wire gpr_spec_i1_wr_v_fast; + wire [0:`GPR_POOL_ENC-1] gpr_spec_i1_wr_a; + wire [0:`GPR_POOL_ENC-1] gpr_spec_i1_wr_p; + wire [0:`ITAG_SIZE_ENC-1] gpr_spec_i1_wr_itag; + + wire next_gpr_0_v; + wire [0:`GPR_POOL_ENC-1] next_gpr_0; + wire next_gpr_1_v; + wire [0:`GPR_POOL_ENC-1] next_gpr_1; + + // Source lookups from pools note may not be valid if source if type not of the right type + wire [0:`CR_POOL_ENC-1] cr_iu5_i0_src1_p; + wire [0:`CR_POOL_ENC-1] cr_iu5_i0_src2_p; + wire [0:`CR_POOL_ENC-1] cr_iu5_i0_src3_p; + wire [0:`CR_POOL_ENC-1] cr_iu5_i1_src1_p; + wire [0:`CR_POOL_ENC-1] cr_iu5_i1_src2_p; + wire [0:`CR_POOL_ENC-1] cr_iu5_i1_src3_p; + + // Source lookups from pools note may not be valid if source if type not of the right type + wire [0:`ITAG_SIZE_ENC-1] cr_iu5_i0_src1_itag; + wire [0:`ITAG_SIZE_ENC-1] cr_iu5_i0_src2_itag; + wire [0:`ITAG_SIZE_ENC-1] cr_iu5_i0_src3_itag; + wire [0:`ITAG_SIZE_ENC-1] cr_iu5_i1_src1_itag; + wire [0:`ITAG_SIZE_ENC-1] cr_iu5_i1_src2_itag; + wire [0:`ITAG_SIZE_ENC-1] cr_iu5_i1_src3_itag; + + // I1 dependency hit vs I0 for each source this is used by RV + wire cr_s1_dep_hit; + wire cr_s2_dep_hit; + wire cr_s3_dep_hit; + + // Free from completion to the cr pool + wire cr_cp_i0_wr_v; + wire [0:`CR_POOL_ENC-1] cr_cp_i0_wr_a; + wire [0:`CR_POOL_ENC-1] cr_cp_i0_wr_p; + wire [0:`ITAG_SIZE_ENC-1] cr_cp_i0_wr_itag; + wire cr_cp_i1_wr_v; + wire [0:`CR_POOL_ENC-1] cr_cp_i1_wr_a; + wire [0:`CR_POOL_ENC-1] cr_cp_i1_wr_p; + wire [0:`ITAG_SIZE_ENC-1] cr_cp_i1_wr_itag; + + wire cr_spec_i0_wr_v; + wire cr_spec_i0_wr_v_fast; + wire [0:`CR_POOL_ENC-1] cr_spec_i0_wr_a; + wire [0:`CR_POOL_ENC-1] cr_spec_i0_wr_p; + wire [0:`ITAG_SIZE_ENC-1] cr_spec_i0_wr_itag; + wire cr_spec_i1_wr_v; + wire cr_spec_i1_wr_v_fast; + wire [0:`CR_POOL_ENC-1] cr_spec_i1_wr_a; + wire [0:`CR_POOL_ENC-1] cr_spec_i1_wr_p; + wire [0:`ITAG_SIZE_ENC-1] cr_spec_i1_wr_itag; + + wire next_cr_0_v; + wire [0:`CR_POOL_ENC-1] next_cr_0; + wire next_cr_1_v; + wire [0:`CR_POOL_ENC-1] next_cr_1; + + // Source lookups from pools note may not be valid if source if type not of the right type + wire [0:`LR_POOL_ENC-1] lr_iu5_i0_src1_p; + wire [0:`LR_POOL_ENC-1] lr_iu5_i0_src2_p; + wire [0:`LR_POOL_ENC-1] lr_iu5_i0_src3_p; + wire [0:`LR_POOL_ENC-1] lr_iu5_i1_src1_p; + wire [0:`LR_POOL_ENC-1] lr_iu5_i1_src2_p; + wire [0:`LR_POOL_ENC-1] lr_iu5_i1_src3_p; + + // Source lookups from pools note may not be valid if source if type not of the right type + wire [0:`ITAG_SIZE_ENC-1] lr_iu5_i0_src1_itag; + wire [0:`ITAG_SIZE_ENC-1] lr_iu5_i0_src2_itag; + wire [0:`ITAG_SIZE_ENC-1] lr_iu5_i0_src3_itag; + wire [0:`ITAG_SIZE_ENC-1] lr_iu5_i1_src1_itag; + wire [0:`ITAG_SIZE_ENC-1] lr_iu5_i1_src2_itag; + wire [0:`ITAG_SIZE_ENC-1] lr_iu5_i1_src3_itag; + + // I1 dependency hit vs I0 for each source this is used by RV + wire lr_s1_dep_hit; + wire lr_s2_dep_hit; + wire lr_s3_dep_hit; + + // Free from completion to the lr pool + wire lr_cp_i0_wr_v; + wire [0:`LR_POOL_ENC-1] lr_cp_i0_wr_a; + wire [0:`LR_POOL_ENC-1] lr_cp_i0_wr_p; + wire [0:`ITAG_SIZE_ENC-1] lr_cp_i0_wr_itag; + wire lr_cp_i1_wr_v; + wire [0:`LR_POOL_ENC-1] lr_cp_i1_wr_a; + wire [0:`LR_POOL_ENC-1] lr_cp_i1_wr_p; + wire [0:`ITAG_SIZE_ENC-1] lr_cp_i1_wr_itag; + + wire lr_spec_i0_wr_v; + wire lr_spec_i0_wr_v_fast; + wire [0:`LR_POOL_ENC-1] lr_spec_i0_wr_a; + wire [0:`LR_POOL_ENC-1] lr_spec_i0_wr_p; + wire [0:`ITAG_SIZE_ENC-1] lr_spec_i0_wr_itag; + wire lr_spec_i1_wr_v; + wire lr_spec_i1_wr_v_fast; + wire [0:`LR_POOL_ENC-1] lr_spec_i1_wr_a; + wire [0:`LR_POOL_ENC-1] lr_spec_i1_wr_p; + wire [0:`ITAG_SIZE_ENC-1] lr_spec_i1_wr_itag; + + wire next_lr_0_v; + wire [0:`LR_POOL_ENC-1] next_lr_0; + wire next_lr_1_v; + wire [0:`LR_POOL_ENC-1] next_lr_1; + + // Source lookups from pools note may not be valid if source if type not of the right type + wire [0:`CTR_POOL_ENC-1] ctr_iu5_i0_src1_p; + wire [0:`CTR_POOL_ENC-1] ctr_iu5_i0_src2_p; + wire [0:`CTR_POOL_ENC-1] ctr_iu5_i0_src3_p; + wire [0:`CTR_POOL_ENC-1] ctr_iu5_i1_src1_p; + wire [0:`CTR_POOL_ENC-1] ctr_iu5_i1_src2_p; + wire [0:`CTR_POOL_ENC-1] ctr_iu5_i1_src3_p; + + // Source lookups from pools note may not be valid if source if type not of the right type + wire [0:`ITAG_SIZE_ENC-1] ctr_iu5_i0_src1_itag; + wire [0:`ITAG_SIZE_ENC-1] ctr_iu5_i0_src2_itag; + wire [0:`ITAG_SIZE_ENC-1] ctr_iu5_i0_src3_itag; + wire [0:`ITAG_SIZE_ENC-1] ctr_iu5_i1_src1_itag; + wire [0:`ITAG_SIZE_ENC-1] ctr_iu5_i1_src2_itag; + wire [0:`ITAG_SIZE_ENC-1] ctr_iu5_i1_src3_itag; + + // I1 dependency hit vs I0 for each source this is used by RV + wire ctr_s1_dep_hit; + wire ctr_s2_dep_hit; + wire ctr_s3_dep_hit; + + // Free from completion to the ctr pool + wire ctr_cp_i0_wr_v; + wire [0:`CTR_POOL_ENC-1] ctr_cp_i0_wr_a; + wire [0:`CTR_POOL_ENC-1] ctr_cp_i0_wr_p; + wire [0:`ITAG_SIZE_ENC-1] ctr_cp_i0_wr_itag; + wire ctr_cp_i1_wr_v; + wire [0:`CTR_POOL_ENC-1] ctr_cp_i1_wr_a; + wire [0:`CTR_POOL_ENC-1] ctr_cp_i1_wr_p; + wire [0:`ITAG_SIZE_ENC-1] ctr_cp_i1_wr_itag; + + wire ctr_spec_i0_wr_v; + wire ctr_spec_i0_wr_v_fast; + wire [0:`CTR_POOL_ENC-1] ctr_spec_i0_wr_a; + wire [0:`CTR_POOL_ENC-1] ctr_spec_i0_wr_p; + wire [0:`ITAG_SIZE_ENC-1] ctr_spec_i0_wr_itag; + wire ctr_spec_i1_wr_v; + wire ctr_spec_i1_wr_v_fast; + wire [0:`CTR_POOL_ENC-1] ctr_spec_i1_wr_a; + wire [0:`CTR_POOL_ENC-1] ctr_spec_i1_wr_p; + wire [0:`ITAG_SIZE_ENC-1] ctr_spec_i1_wr_itag; + + wire next_ctr_0_v; + wire [0:`CTR_POOL_ENC-1] next_ctr_0; + wire next_ctr_1_v; + wire [0:`CTR_POOL_ENC-1] next_ctr_1; + + // Source lookups from pools note may not be valid if source if type not of the right type + wire [0:`XER_POOL_ENC-1] xer_iu5_i0_src1_p; + wire [0:`XER_POOL_ENC-1] xer_iu5_i0_src2_p; + wire [0:`XER_POOL_ENC-1] xer_iu5_i0_src3_p; + wire [0:`XER_POOL_ENC-1] xer_iu5_i1_src1_p; + wire [0:`XER_POOL_ENC-1] xer_iu5_i1_src2_p; + wire [0:`XER_POOL_ENC-1] xer_iu5_i1_src3_p; + + // Source lookups from pools note may not be valid if source if type not of the right type + wire [0:`ITAG_SIZE_ENC-1] xer_iu5_i0_src1_itag; + wire [0:`ITAG_SIZE_ENC-1] xer_iu5_i0_src2_itag; + wire [0:`ITAG_SIZE_ENC-1] xer_iu5_i0_src3_itag; + wire [0:`ITAG_SIZE_ENC-1] xer_iu5_i1_src1_itag; + wire [0:`ITAG_SIZE_ENC-1] xer_iu5_i1_src2_itag; + wire [0:`ITAG_SIZE_ENC-1] xer_iu5_i1_src3_itag; + + // I1 dependency hit vs I0 for each source this is used by RV + wire xer_s1_dep_hit; + wire xer_s2_dep_hit; + wire xer_s3_dep_hit; + + // Free from completion to the xer pool + wire xer_cp_i0_wr_v; + wire [0:`XER_POOL_ENC-1] xer_cp_i0_wr_a; + wire [0:`XER_POOL_ENC-1] xer_cp_i0_wr_p; + wire [0:`ITAG_SIZE_ENC-1] xer_cp_i0_wr_itag; + wire xer_cp_i1_wr_v; + wire [0:`XER_POOL_ENC-1] xer_cp_i1_wr_a; + wire [0:`XER_POOL_ENC-1] xer_cp_i1_wr_p; + wire [0:`ITAG_SIZE_ENC-1] xer_cp_i1_wr_itag; + + wire xer_spec_i0_wr_v; + wire xer_spec_i0_wr_v_fast; + wire [0:`XER_POOL_ENC-1] xer_spec_i0_wr_a; + wire [0:`XER_POOL_ENC-1] xer_spec_i0_wr_p; + wire [0:`ITAG_SIZE_ENC-1] xer_spec_i0_wr_itag; + wire xer_spec_i1_wr_v; + wire xer_spec_i1_wr_v_fast; + wire [0:`XER_POOL_ENC-1] xer_spec_i1_wr_a; + wire [0:`XER_POOL_ENC-1] xer_spec_i1_wr_p; + wire [0:`ITAG_SIZE_ENC-1] xer_spec_i1_wr_itag; + + wire next_xer_0_v; + wire [0:`XER_POOL_ENC-1] next_xer_0; + wire next_xer_1_v; + wire [0:`XER_POOL_ENC-1] next_xer_1; + + wire [0:1] gpr_send_cnt; + wire [0:1] cr_send_cnt; + wire [0:1] cr_send_t1_cnt; + wire [0:1] cr_send_t3_cnt; + wire [0:1] lr_send_cnt; + wire [0:1] ctr_send_cnt; + wire [0:1] xer_send_cnt; + wire [0:1] ucode_send_cnt; + wire [0:`UCODE_ENTRIES_ENC-1] ucode_cnt_i0; + wire [0:`UCODE_ENTRIES_ENC-1] ucode_cnt_i1; + + wire cpl_credit_ok; + wire gpr_send_ok; + wire cr_send_ok; + wire lr_send_ok; + wire ctr_send_ok; + wire xer_send_ok; + wire cp_empty_ok; + + wire send_instructions; + + // Perfmon + wire perf_iu5_stall_d, perf_iu5_stall_l2; + wire perf_iu5_cpl_credit_stall_d, perf_iu5_cpl_credit_stall_l2; + wire perf_iu5_gpr_credit_stall_d, perf_iu5_gpr_credit_stall_l2; + wire perf_iu5_cr_credit_stall_d, perf_iu5_cr_credit_stall_l2; + wire perf_iu5_lr_credit_stall_d, perf_iu5_lr_credit_stall_l2; + wire perf_iu5_ctr_credit_stall_d, perf_iu5_ctr_credit_stall_l2; + wire perf_iu5_xer_credit_stall_d, perf_iu5_xer_credit_stall_l2; + wire perf_iu5_br_hold_stall_d, perf_iu5_br_hold_stall_l2; + wire perf_iu5_axu_hold_stall_d, perf_iu5_axu_hold_stall_l2; + + + // Pervasive + wire pc_iu_func_sl_thold_1; + wire pc_iu_func_sl_thold_0; + wire pc_iu_func_sl_thold_0_b; + wire pc_iu_sg_1; + wire pc_iu_sg_0; + wire force_t; + + assign tidn = 1'b0; + assign tiup = 1'b1; + + // outputs + assign frn_fdis_iu6_i0_vld = (fdis_frn_iu6_stall_l2[3] == 1'b0) ? frn_fdis_iu6_i0_vld_l2 : + stall_frn_fdis_iu6_i0_vld_l2; + assign frn_fdis_iu6_i0_itag = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_itag_l2 : + stall_frn_fdis_iu6_i0_itag_l2; + assign frn_fdis_iu6_i0_ucode = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_ucode_l2 : + stall_frn_fdis_iu6_i0_ucode_l2; + assign frn_fdis_iu6_i0_ucode_cnt = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_ucode_cnt_l2 : + stall_frn_fdis_iu6_i0_ucode_cnt_l2; + assign frn_fdis_iu6_i0_2ucode = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_2ucode_l2 : + stall_frn_fdis_iu6_i0_2ucode_l2; + assign frn_fdis_iu6_i0_fuse_nop = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_fuse_nop_l2 : + stall_frn_fdis_iu6_i0_fuse_nop_l2; + assign frn_fdis_iu6_i0_rte_lq = (fdis_frn_iu6_stall_l2[5] == 1'b0) ? frn_fdis_iu6_i0_rte_lq_l2 : + stall_frn_fdis_iu6_i0_rte_lq_l2; + assign frn_fdis_iu6_i0_rte_sq = (fdis_frn_iu6_stall_l2[7] == 1'b0) ? frn_fdis_iu6_i0_rte_sq_l2 : + stall_frn_fdis_iu6_i0_rte_sq_l2; + assign frn_fdis_iu6_i0_rte_fx0 = (fdis_frn_iu6_stall_l2[9] == 1'b0) ? frn_fdis_iu6_i0_rte_fx0_l2 : + stall_frn_fdis_iu6_i0_rte_fx0_l2; + assign frn_fdis_iu6_i0_rte_fx1 = (fdis_frn_iu6_stall_l2[11] == 1'b0) ? frn_fdis_iu6_i0_rte_fx1_l2 : + stall_frn_fdis_iu6_i0_rte_fx1_l2; + assign frn_fdis_iu6_i0_rte_axu0 = (fdis_frn_iu6_stall_l2[13] == 1'b0) ? frn_fdis_iu6_i0_rte_axu0_l2 : + stall_frn_fdis_iu6_i0_rte_axu0_l2; + assign frn_fdis_iu6_i0_rte_axu1 = (fdis_frn_iu6_stall_l2[15] == 1'b0) ? frn_fdis_iu6_i0_rte_axu1_l2 : + stall_frn_fdis_iu6_i0_rte_axu1_l2; + assign frn_fdis_iu6_i0_valop = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_valop_l2 : + stall_frn_fdis_iu6_i0_valop_l2; + assign frn_fdis_iu6_i0_ord = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_ord_l2 : + stall_frn_fdis_iu6_i0_ord_l2; + assign frn_fdis_iu6_i0_cord = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_cord_l2 : + stall_frn_fdis_iu6_i0_cord_l2; + assign frn_fdis_iu6_i0_error = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_error_l2 : + stall_frn_fdis_iu6_i0_error_l2; + assign frn_fdis_iu6_i0_btb_entry = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_btb_entry_l2 : + stall_frn_fdis_iu6_i0_btb_entry_l2; + assign frn_fdis_iu6_i0_btb_hist = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_btb_hist_l2 : + stall_frn_fdis_iu6_i0_btb_hist_l2; + assign frn_fdis_iu6_i0_bta_val = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_bta_val_l2 : + stall_frn_fdis_iu6_i0_bta_val_l2; + assign frn_fdis_iu6_i0_fusion = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_fusion_l2 : + stall_frn_fdis_iu6_i0_fusion_l2; + assign frn_fdis_iu6_i0_spec = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_spec_l2 : + stall_frn_fdis_iu6_i0_spec_l2; + assign frn_fdis_iu6_i0_type_fp = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_type_fp_l2 : + stall_frn_fdis_iu6_i0_type_fp_l2; + assign frn_fdis_iu6_i0_type_ap = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_type_ap_l2 : + stall_frn_fdis_iu6_i0_type_ap_l2; + assign frn_fdis_iu6_i0_type_spv = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_type_spv_l2 : + stall_frn_fdis_iu6_i0_type_spv_l2; + assign frn_fdis_iu6_i0_type_st = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_type_st_l2 : + stall_frn_fdis_iu6_i0_type_st_l2; + assign frn_fdis_iu6_i0_async_block = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_async_block_l2 : + stall_frn_fdis_iu6_i0_async_block_l2; + assign frn_fdis_iu6_i0_np1_flush = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_np1_flush_l2 : + stall_frn_fdis_iu6_i0_np1_flush_l2; + assign frn_fdis_iu6_i0_core_block = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_core_block_l2 : + stall_frn_fdis_iu6_i0_core_block_l2; + assign frn_fdis_iu6_i0_isram = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_isram_l2 : + stall_frn_fdis_iu6_i0_isram_l2; + assign frn_fdis_iu6_i0_isload = (fdis_frn_iu6_stall_l2[17] == 1'b0) ? frn_fdis_iu6_i0_isload_l2 : + stall_frn_fdis_iu6_i0_isload_l2; + assign frn_fdis_iu6_i0_isstore = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_isstore_l2 : + stall_frn_fdis_iu6_i0_isstore_l2; + assign frn_fdis_iu6_i0_instr = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_instr_l2 : + stall_frn_fdis_iu6_i0_instr_l2; + assign frn_fdis_iu6_i0_ifar = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_ifar_l2 : + stall_frn_fdis_iu6_i0_ifar_l2; + assign frn_fdis_iu6_i0_bta = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_bta_l2 : + stall_frn_fdis_iu6_i0_bta_l2; + assign frn_fdis_iu6_i0_br_pred = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_br_pred_l2 : + stall_frn_fdis_iu6_i0_br_pred_l2; + assign frn_fdis_iu6_i0_bh_update = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_bh_update_l2 : + stall_frn_fdis_iu6_i0_bh_update_l2; + assign frn_fdis_iu6_i0_bh0_hist = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_bh0_hist_l2 : + stall_frn_fdis_iu6_i0_bh0_hist_l2; + assign frn_fdis_iu6_i0_bh1_hist = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_bh1_hist_l2 : + stall_frn_fdis_iu6_i0_bh1_hist_l2; + assign frn_fdis_iu6_i0_bh2_hist = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_bh2_hist_l2 : + stall_frn_fdis_iu6_i0_bh2_hist_l2; + assign frn_fdis_iu6_i0_gshare = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_gshare_l2 : + stall_frn_fdis_iu6_i0_gshare_l2; + assign frn_fdis_iu6_i0_ls_ptr = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_ls_ptr_l2 : + stall_frn_fdis_iu6_i0_ls_ptr_l2; + assign frn_fdis_iu6_i0_match = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_match_l2 : + stall_frn_fdis_iu6_i0_match_l2; + assign frn_fdis_iu6_i0_ilat = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_ilat_l2 : + stall_frn_fdis_iu6_i0_ilat_l2; + assign frn_fdis_iu6_i0_t1_v = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_t1_v_l2 : + stall_frn_fdis_iu6_i0_t1_v_l2; + assign frn_fdis_iu6_i0_t1_t = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_t1_t_l2 : + stall_frn_fdis_iu6_i0_t1_t_l2; + assign frn_fdis_iu6_i0_t1_a = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_t1_a_l2 : + stall_frn_fdis_iu6_i0_t1_a_l2; + assign frn_fdis_iu6_i0_t1_p = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_t1_p_l2 : + stall_frn_fdis_iu6_i0_t1_p_l2; + assign frn_fdis_iu6_i0_t2_v = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_t2_v_l2 : + stall_frn_fdis_iu6_i0_t2_v_l2; + assign frn_fdis_iu6_i0_t2_a = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_t2_a_l2 : + stall_frn_fdis_iu6_i0_t2_a_l2; + assign frn_fdis_iu6_i0_t2_p = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_t2_p_l2 : + stall_frn_fdis_iu6_i0_t2_p_l2; + assign frn_fdis_iu6_i0_t2_t = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_t2_t_l2 : + stall_frn_fdis_iu6_i0_t2_t_l2; + assign frn_fdis_iu6_i0_t3_v = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_t3_v_l2 : + stall_frn_fdis_iu6_i0_t3_v_l2; + assign frn_fdis_iu6_i0_t3_a = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_t3_a_l2 : + stall_frn_fdis_iu6_i0_t3_a_l2; + assign frn_fdis_iu6_i0_t3_p = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_t3_p_l2 : + stall_frn_fdis_iu6_i0_t3_p_l2; + assign frn_fdis_iu6_i0_t3_t = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_t3_t_l2 : + stall_frn_fdis_iu6_i0_t3_t_l2; + assign frn_fdis_iu6_i0_s1_v = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_s1_v_l2 : + stall_frn_fdis_iu6_i0_s1_v_l2; + assign frn_fdis_iu6_i0_s1_a = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_s1_a_l2 : + stall_frn_fdis_iu6_i0_s1_a_l2; + assign frn_fdis_iu6_i0_s1_p = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_s1_p_l2 : + stall_frn_fdis_iu6_i0_s1_p_l2; + assign frn_fdis_iu6_i0_s1_itag = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_s1_itag_l2 : + stall_frn_fdis_iu6_i0_s1_itag_l2; + assign frn_fdis_iu6_i0_s1_t = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_s1_t_l2 : + stall_frn_fdis_iu6_i0_s1_t_l2; + assign frn_fdis_iu6_i0_s2_v = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_s2_v_l2 : + stall_frn_fdis_iu6_i0_s2_v_l2; + assign frn_fdis_iu6_i0_s2_a = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_s2_a_l2 : + stall_frn_fdis_iu6_i0_s2_a_l2; + assign frn_fdis_iu6_i0_s2_p = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_s2_p_l2 : + stall_frn_fdis_iu6_i0_s2_p_l2; + assign frn_fdis_iu6_i0_s2_itag = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_s2_itag_l2 : + stall_frn_fdis_iu6_i0_s2_itag_l2; + assign frn_fdis_iu6_i0_s2_t = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_s2_t_l2 : + stall_frn_fdis_iu6_i0_s2_t_l2; + assign frn_fdis_iu6_i0_s3_v = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_s3_v_l2 : + stall_frn_fdis_iu6_i0_s3_v_l2; + assign frn_fdis_iu6_i0_s3_a = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_s3_a_l2 : + stall_frn_fdis_iu6_i0_s3_a_l2; + assign frn_fdis_iu6_i0_s3_p = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_s3_p_l2 : + stall_frn_fdis_iu6_i0_s3_p_l2; + assign frn_fdis_iu6_i0_s3_itag = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_s3_itag_l2 : + stall_frn_fdis_iu6_i0_s3_itag_l2; + assign frn_fdis_iu6_i0_s3_t = (fdis_frn_iu6_stall_l2[1] == 1'b0) ? frn_fdis_iu6_i0_s3_t_l2 : + stall_frn_fdis_iu6_i0_s3_t_l2; + + assign frn_fdis_iu6_i1_vld = (fdis_frn_iu6_stall_l2[4] == 1'b0) ? frn_fdis_iu6_i1_vld_l2 : + stall_frn_fdis_iu6_i1_vld_l2; + assign frn_fdis_iu6_i1_itag = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_itag_l2 : + stall_frn_fdis_iu6_i1_itag_l2; + assign frn_fdis_iu6_i1_ucode = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_ucode_l2 : + stall_frn_fdis_iu6_i1_ucode_l2; + assign frn_fdis_iu6_i1_ucode_cnt = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_ucode_cnt_l2 : + stall_frn_fdis_iu6_i1_ucode_cnt_l2; + assign frn_fdis_iu6_i1_fuse_nop = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_fuse_nop_l2 : + stall_frn_fdis_iu6_i1_fuse_nop_l2; + assign frn_fdis_iu6_i1_rte_lq = (fdis_frn_iu6_stall_l2[6] == 1'b0) ? frn_fdis_iu6_i1_rte_lq_l2 : + stall_frn_fdis_iu6_i1_rte_lq_l2; + assign frn_fdis_iu6_i1_rte_sq = (fdis_frn_iu6_stall_l2[8] == 1'b0) ? frn_fdis_iu6_i1_rte_sq_l2 : + stall_frn_fdis_iu6_i1_rte_sq_l2; + assign frn_fdis_iu6_i1_rte_fx0 = (fdis_frn_iu6_stall_l2[10] == 1'b0) ? frn_fdis_iu6_i1_rte_fx0_l2 : + stall_frn_fdis_iu6_i1_rte_fx0_l2; + assign frn_fdis_iu6_i1_rte_fx1 = (fdis_frn_iu6_stall_l2[12] == 1'b0) ? frn_fdis_iu6_i1_rte_fx1_l2 : + stall_frn_fdis_iu6_i1_rte_fx1_l2; + assign frn_fdis_iu6_i1_rte_axu0 = (fdis_frn_iu6_stall_l2[14] == 1'b0) ? frn_fdis_iu6_i1_rte_axu0_l2 : + stall_frn_fdis_iu6_i1_rte_axu0_l2; + assign frn_fdis_iu6_i1_rte_axu1 = (fdis_frn_iu6_stall_l2[16] == 1'b0) ? frn_fdis_iu6_i1_rte_axu1_l2 : + stall_frn_fdis_iu6_i1_rte_axu1_l2; + assign frn_fdis_iu6_i1_valop = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_valop_l2 : + stall_frn_fdis_iu6_i1_valop_l2; + assign frn_fdis_iu6_i1_ord = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_ord_l2 : + stall_frn_fdis_iu6_i1_ord_l2; + assign frn_fdis_iu6_i1_cord = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_cord_l2 : + stall_frn_fdis_iu6_i1_cord_l2; + assign frn_fdis_iu6_i1_error = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_error_l2 : + stall_frn_fdis_iu6_i1_error_l2; + assign frn_fdis_iu6_i1_btb_entry = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_btb_entry_l2 : + stall_frn_fdis_iu6_i1_btb_entry_l2; + assign frn_fdis_iu6_i1_btb_hist = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_btb_hist_l2 : + stall_frn_fdis_iu6_i1_btb_hist_l2; + assign frn_fdis_iu6_i1_bta_val = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_bta_val_l2 : + stall_frn_fdis_iu6_i1_bta_val_l2; + assign frn_fdis_iu6_i1_fusion = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_fusion_l2 : + stall_frn_fdis_iu6_i1_fusion_l2; + assign frn_fdis_iu6_i1_spec = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_spec_l2 : + stall_frn_fdis_iu6_i1_spec_l2; + assign frn_fdis_iu6_i1_type_fp = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_type_fp_l2 : + stall_frn_fdis_iu6_i1_type_fp_l2; + assign frn_fdis_iu6_i1_type_ap = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_type_ap_l2 : + stall_frn_fdis_iu6_i1_type_ap_l2; + assign frn_fdis_iu6_i1_type_spv = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_type_spv_l2 : + stall_frn_fdis_iu6_i1_type_spv_l2; + assign frn_fdis_iu6_i1_type_st = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_type_st_l2 : + stall_frn_fdis_iu6_i1_type_st_l2; + assign frn_fdis_iu6_i1_async_block = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_async_block_l2 : + stall_frn_fdis_iu6_i1_async_block_l2; + assign frn_fdis_iu6_i1_np1_flush = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_np1_flush_l2 : + stall_frn_fdis_iu6_i1_np1_flush_l2; + assign frn_fdis_iu6_i1_core_block = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_core_block_l2 : + stall_frn_fdis_iu6_i1_core_block_l2; + assign frn_fdis_iu6_i1_isram = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_isram_l2 : + stall_frn_fdis_iu6_i1_isram_l2; + assign frn_fdis_iu6_i1_isload = (fdis_frn_iu6_stall_l2[18] == 1'b0) ? frn_fdis_iu6_i1_isload_l2 : + stall_frn_fdis_iu6_i1_isload_l2; + assign frn_fdis_iu6_i1_isstore = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_isstore_l2 : + stall_frn_fdis_iu6_i1_isstore_l2; + assign frn_fdis_iu6_i1_instr = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_instr_l2 : + stall_frn_fdis_iu6_i1_instr_l2; + assign frn_fdis_iu6_i1_ifar = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_ifar_l2 : + stall_frn_fdis_iu6_i1_ifar_l2; + assign frn_fdis_iu6_i1_bta = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_bta_l2 : + stall_frn_fdis_iu6_i1_bta_l2; + assign frn_fdis_iu6_i1_br_pred = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_br_pred_l2 : + stall_frn_fdis_iu6_i1_br_pred_l2; + assign frn_fdis_iu6_i1_bh_update = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_bh_update_l2 : + stall_frn_fdis_iu6_i1_bh_update_l2; + assign frn_fdis_iu6_i1_bh0_hist = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_bh0_hist_l2 : + stall_frn_fdis_iu6_i1_bh0_hist_l2; + assign frn_fdis_iu6_i1_bh1_hist = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_bh1_hist_l2 : + stall_frn_fdis_iu6_i1_bh1_hist_l2; + assign frn_fdis_iu6_i1_bh2_hist = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_bh2_hist_l2 : + stall_frn_fdis_iu6_i1_bh2_hist_l2; + assign frn_fdis_iu6_i1_gshare = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_gshare_l2 : + stall_frn_fdis_iu6_i1_gshare_l2; + assign frn_fdis_iu6_i1_ls_ptr = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_ls_ptr_l2 : + stall_frn_fdis_iu6_i1_ls_ptr_l2; + assign frn_fdis_iu6_i1_match = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_match_l2 : + stall_frn_fdis_iu6_i1_match_l2; + assign frn_fdis_iu6_i1_ilat = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_ilat_l2 : + stall_frn_fdis_iu6_i1_ilat_l2; + assign frn_fdis_iu6_i1_t1_v = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_t1_v_l2 : + stall_frn_fdis_iu6_i1_t1_v_l2; + assign frn_fdis_iu6_i1_t1_t = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_t1_t_l2 : + stall_frn_fdis_iu6_i1_t1_t_l2; + assign frn_fdis_iu6_i1_t1_a = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_t1_a_l2 : + stall_frn_fdis_iu6_i1_t1_a_l2; + assign frn_fdis_iu6_i1_t1_p = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_t1_p_l2 : + stall_frn_fdis_iu6_i1_t1_p_l2; + assign frn_fdis_iu6_i1_t2_v = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_t2_v_l2 : + stall_frn_fdis_iu6_i1_t2_v_l2; + assign frn_fdis_iu6_i1_t2_a = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_t2_a_l2 : + stall_frn_fdis_iu6_i1_t2_a_l2; + assign frn_fdis_iu6_i1_t2_p = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_t2_p_l2 : + stall_frn_fdis_iu6_i1_t2_p_l2; + assign frn_fdis_iu6_i1_t2_t = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_t2_t_l2 : + stall_frn_fdis_iu6_i1_t2_t_l2; + assign frn_fdis_iu6_i1_t3_v = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_t3_v_l2 : + stall_frn_fdis_iu6_i1_t3_v_l2; + assign frn_fdis_iu6_i1_t3_a = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_t3_a_l2 : + stall_frn_fdis_iu6_i1_t3_a_l2; + assign frn_fdis_iu6_i1_t3_p = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_t3_p_l2 : + stall_frn_fdis_iu6_i1_t3_p_l2; + assign frn_fdis_iu6_i1_t3_t = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_t3_t_l2 : + stall_frn_fdis_iu6_i1_t3_t_l2; + assign frn_fdis_iu6_i1_s1_v = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_s1_v_l2 : + stall_frn_fdis_iu6_i1_s1_v_l2; + assign frn_fdis_iu6_i1_s1_a = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_s1_a_l2 : + stall_frn_fdis_iu6_i1_s1_a_l2; + assign frn_fdis_iu6_i1_s1_p = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_s1_p_l2 : + stall_frn_fdis_iu6_i1_s1_p_l2; + assign frn_fdis_iu6_i1_s1_itag = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_s1_itag_l2 : + stall_frn_fdis_iu6_i1_s1_itag_l2; + assign frn_fdis_iu6_i1_s1_t = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_s1_t_l2 : + stall_frn_fdis_iu6_i1_s1_t_l2; + assign frn_fdis_iu6_i1_s1_dep_hit = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_s1_dep_hit_l2 : + stall_frn_fdis_iu6_i1_s1_dep_hit_l2; + assign frn_fdis_iu6_i1_s2_v = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_s2_v_l2 : + stall_frn_fdis_iu6_i1_s2_v_l2; + assign frn_fdis_iu6_i1_s2_a = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_s2_a_l2 : + stall_frn_fdis_iu6_i1_s2_a_l2; + assign frn_fdis_iu6_i1_s2_p = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_s2_p_l2 : + stall_frn_fdis_iu6_i1_s2_p_l2; + assign frn_fdis_iu6_i1_s2_itag = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_s2_itag_l2 : + stall_frn_fdis_iu6_i1_s2_itag_l2; + assign frn_fdis_iu6_i1_s2_t = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_s2_t_l2 : + stall_frn_fdis_iu6_i1_s2_t_l2; + assign frn_fdis_iu6_i1_s2_dep_hit = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_s2_dep_hit_l2 : + stall_frn_fdis_iu6_i1_s2_dep_hit_l2; + assign frn_fdis_iu6_i1_s3_v = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_s3_v_l2 : + stall_frn_fdis_iu6_i1_s3_v_l2; + assign frn_fdis_iu6_i1_s3_a = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_s3_a_l2 : + stall_frn_fdis_iu6_i1_s3_a_l2; + assign frn_fdis_iu6_i1_s3_p = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_s3_p_l2 : + stall_frn_fdis_iu6_i1_s3_p_l2; + assign frn_fdis_iu6_i1_s3_itag = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_s3_itag_l2 : + stall_frn_fdis_iu6_i1_s3_itag_l2; + assign frn_fdis_iu6_i1_s3_t = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_s3_t_l2 : + stall_frn_fdis_iu6_i1_s3_t_l2; + assign frn_fdis_iu6_i1_s3_dep_hit = (fdis_frn_iu6_stall_l2[2] == 1'b0) ? frn_fdis_iu6_i1_s3_dep_hit_l2 : + stall_frn_fdis_iu6_i1_s3_dep_hit_l2; + + // output stall + assign fdis_frn_iu6_stall_d = {19{((frn_fdis_iu6_i0_vld_l2 | fdis_frn_iu6_stall_l2[0]) & fdis_frn_iu6_stall & (~cp_flush_l2))}}; + // validate stall with iu6 vld for all upstream stages to eliminate any bubbles + assign fdis_frn_iu6_stall_dly = fdis_frn_iu6_stall_l2[0] & frn_fdis_iu6_i0_vld_l2; + + assign stall_frn_fdis_iu6_i0_act = (~fdis_frn_iu6_stall_l2[0]); + assign stall_frn_fdis_iu6_i0_vld_d = frn_fdis_iu6_i0_vld_l2; + assign stall_frn_fdis_iu6_i0_itag_d = frn_fdis_iu6_i0_itag_l2; + assign stall_frn_fdis_iu6_i0_ucode_d = frn_fdis_iu6_i0_ucode_l2; + assign stall_frn_fdis_iu6_i0_ucode_cnt_d = frn_fdis_iu6_i0_ucode_cnt_l2; + assign stall_frn_fdis_iu6_i0_2ucode_d = frn_fdis_iu6_i0_2ucode_l2; + assign stall_frn_fdis_iu6_i0_fuse_nop_d = frn_fdis_iu6_i0_fuse_nop_l2; + assign stall_frn_fdis_iu6_i0_rte_lq_d = frn_fdis_iu6_i0_rte_lq_l2; + assign stall_frn_fdis_iu6_i0_rte_sq_d = frn_fdis_iu6_i0_rte_sq_l2; + assign stall_frn_fdis_iu6_i0_rte_fx0_d = frn_fdis_iu6_i0_rte_fx0_l2; + assign stall_frn_fdis_iu6_i0_rte_fx1_d = frn_fdis_iu6_i0_rte_fx1_l2; + assign stall_frn_fdis_iu6_i0_rte_axu0_d = frn_fdis_iu6_i0_rte_axu0_l2; + assign stall_frn_fdis_iu6_i0_rte_axu1_d = frn_fdis_iu6_i0_rte_axu1_l2; + assign stall_frn_fdis_iu6_i0_valop_d = frn_fdis_iu6_i0_valop_l2; + assign stall_frn_fdis_iu6_i0_ord_d = frn_fdis_iu6_i0_ord_l2; + assign stall_frn_fdis_iu6_i0_cord_d = frn_fdis_iu6_i0_cord_l2; + assign stall_frn_fdis_iu6_i0_error_d = frn_fdis_iu6_i0_error_l2; + assign stall_frn_fdis_iu6_i0_btb_entry_d = frn_fdis_iu6_i0_btb_entry_l2; + assign stall_frn_fdis_iu6_i0_btb_hist_d = frn_fdis_iu6_i0_btb_hist_l2; + assign stall_frn_fdis_iu6_i0_bta_val_d = frn_fdis_iu6_i0_bta_val_l2; + assign stall_frn_fdis_iu6_i0_fusion_d = frn_fdis_iu6_i0_fusion_l2; + assign stall_frn_fdis_iu6_i0_spec_d = frn_fdis_iu6_i0_spec_l2; + assign stall_frn_fdis_iu6_i0_type_fp_d = frn_fdis_iu6_i0_type_fp_l2; + assign stall_frn_fdis_iu6_i0_type_ap_d = frn_fdis_iu6_i0_type_ap_l2; + assign stall_frn_fdis_iu6_i0_type_spv_d = frn_fdis_iu6_i0_type_spv_l2; + assign stall_frn_fdis_iu6_i0_type_st_d = frn_fdis_iu6_i0_type_st_l2; + assign stall_frn_fdis_iu6_i0_async_block_d = frn_fdis_iu6_i0_async_block_l2; + assign stall_frn_fdis_iu6_i0_np1_flush_d = frn_fdis_iu6_i0_np1_flush_l2; + assign stall_frn_fdis_iu6_i0_core_block_d = frn_fdis_iu6_i0_core_block_l2; + assign stall_frn_fdis_iu6_i0_isram_d = frn_fdis_iu6_i0_isram_l2; + assign stall_frn_fdis_iu6_i0_isload_d = frn_fdis_iu6_i0_isload_l2; + assign stall_frn_fdis_iu6_i0_isstore_d = frn_fdis_iu6_i0_isstore_l2; + assign stall_frn_fdis_iu6_i0_instr_d = frn_fdis_iu6_i0_instr_l2; + assign stall_frn_fdis_iu6_i0_ifar_d = frn_fdis_iu6_i0_ifar_l2; + assign stall_frn_fdis_iu6_i0_bta_d = frn_fdis_iu6_i0_bta_l2; + assign stall_frn_fdis_iu6_i0_br_pred_d = frn_fdis_iu6_i0_br_pred_l2; + assign stall_frn_fdis_iu6_i0_bh_update_d = frn_fdis_iu6_i0_bh_update_l2; + assign stall_frn_fdis_iu6_i0_bh0_hist_d = frn_fdis_iu6_i0_bh0_hist_l2; + assign stall_frn_fdis_iu6_i0_bh1_hist_d = frn_fdis_iu6_i0_bh1_hist_l2; + assign stall_frn_fdis_iu6_i0_bh2_hist_d = frn_fdis_iu6_i0_bh2_hist_l2; + assign stall_frn_fdis_iu6_i0_gshare_d = frn_fdis_iu6_i0_gshare_l2; + assign stall_frn_fdis_iu6_i0_ls_ptr_d = frn_fdis_iu6_i0_ls_ptr_l2; + assign stall_frn_fdis_iu6_i0_match_d = frn_fdis_iu6_i0_match_l2; + assign stall_frn_fdis_iu6_i0_ilat_d = frn_fdis_iu6_i0_ilat_l2; + assign stall_frn_fdis_iu6_i0_t1_v_d = frn_fdis_iu6_i0_t1_v_l2; + assign stall_frn_fdis_iu6_i0_t1_t_d = frn_fdis_iu6_i0_t1_t_l2; + assign stall_frn_fdis_iu6_i0_t1_a_d = frn_fdis_iu6_i0_t1_a_l2; + assign stall_frn_fdis_iu6_i0_t1_p_d = frn_fdis_iu6_i0_t1_p_l2; + assign stall_frn_fdis_iu6_i0_t2_v_d = frn_fdis_iu6_i0_t2_v_l2; + assign stall_frn_fdis_iu6_i0_t2_a_d = frn_fdis_iu6_i0_t2_a_l2; + assign stall_frn_fdis_iu6_i0_t2_p_d = frn_fdis_iu6_i0_t2_p_l2; + assign stall_frn_fdis_iu6_i0_t2_t_d = frn_fdis_iu6_i0_t2_t_l2; + assign stall_frn_fdis_iu6_i0_t3_v_d = frn_fdis_iu6_i0_t3_v_l2; + assign stall_frn_fdis_iu6_i0_t3_a_d = frn_fdis_iu6_i0_t3_a_l2; + assign stall_frn_fdis_iu6_i0_t3_p_d = frn_fdis_iu6_i0_t3_p_l2; + assign stall_frn_fdis_iu6_i0_t3_t_d = frn_fdis_iu6_i0_t3_t_l2; + assign stall_frn_fdis_iu6_i0_s1_v_d = frn_fdis_iu6_i0_s1_v_l2; + assign stall_frn_fdis_iu6_i0_s1_a_d = frn_fdis_iu6_i0_s1_a_l2; + assign stall_frn_fdis_iu6_i0_s1_p_d = frn_fdis_iu6_i0_s1_p_l2; + assign stall_frn_fdis_iu6_i0_s1_itag_d = frn_fdis_iu6_i0_s1_itag_l2; + assign stall_frn_fdis_iu6_i0_s1_t_d = frn_fdis_iu6_i0_s1_t_l2; + assign stall_frn_fdis_iu6_i0_s2_v_d = frn_fdis_iu6_i0_s2_v_l2; + assign stall_frn_fdis_iu6_i0_s2_a_d = frn_fdis_iu6_i0_s2_a_l2; + assign stall_frn_fdis_iu6_i0_s2_p_d = frn_fdis_iu6_i0_s2_p_l2; + assign stall_frn_fdis_iu6_i0_s2_itag_d = frn_fdis_iu6_i0_s2_itag_l2; + assign stall_frn_fdis_iu6_i0_s2_t_d = frn_fdis_iu6_i0_s2_t_l2; + assign stall_frn_fdis_iu6_i0_s3_v_d = frn_fdis_iu6_i0_s3_v_l2; + assign stall_frn_fdis_iu6_i0_s3_a_d = frn_fdis_iu6_i0_s3_a_l2; + assign stall_frn_fdis_iu6_i0_s3_p_d = frn_fdis_iu6_i0_s3_p_l2; + assign stall_frn_fdis_iu6_i0_s3_itag_d = frn_fdis_iu6_i0_s3_itag_l2; + assign stall_frn_fdis_iu6_i0_s3_t_d = frn_fdis_iu6_i0_s3_t_l2; + + assign stall_frn_fdis_iu6_i1_act = (~fdis_frn_iu6_stall_l2[0]); + assign stall_frn_fdis_iu6_i1_vld_d = frn_fdis_iu6_i1_vld_l2; + assign stall_frn_fdis_iu6_i1_itag_d = frn_fdis_iu6_i1_itag_l2; + assign stall_frn_fdis_iu6_i1_ucode_d = frn_fdis_iu6_i1_ucode_l2; + assign stall_frn_fdis_iu6_i1_ucode_cnt_d = frn_fdis_iu6_i1_ucode_cnt_l2; + assign stall_frn_fdis_iu6_i1_fuse_nop_d = frn_fdis_iu6_i1_fuse_nop_l2; + assign stall_frn_fdis_iu6_i1_rte_lq_d = frn_fdis_iu6_i1_rte_lq_l2; + assign stall_frn_fdis_iu6_i1_rte_sq_d = frn_fdis_iu6_i1_rte_sq_l2; + assign stall_frn_fdis_iu6_i1_rte_fx0_d = frn_fdis_iu6_i1_rte_fx0_l2; + assign stall_frn_fdis_iu6_i1_rte_fx1_d = frn_fdis_iu6_i1_rte_fx1_l2; + assign stall_frn_fdis_iu6_i1_rte_axu0_d = frn_fdis_iu6_i1_rte_axu0_l2; + assign stall_frn_fdis_iu6_i1_rte_axu1_d = frn_fdis_iu6_i1_rte_axu1_l2; + assign stall_frn_fdis_iu6_i1_valop_d = frn_fdis_iu6_i1_valop_l2; + assign stall_frn_fdis_iu6_i1_ord_d = frn_fdis_iu6_i1_ord_l2; + assign stall_frn_fdis_iu6_i1_cord_d = frn_fdis_iu6_i1_cord_l2; + assign stall_frn_fdis_iu6_i1_error_d = frn_fdis_iu6_i1_error_l2; + assign stall_frn_fdis_iu6_i1_btb_entry_d = frn_fdis_iu6_i1_btb_entry_l2; + assign stall_frn_fdis_iu6_i1_btb_hist_d = frn_fdis_iu6_i1_btb_hist_l2; + assign stall_frn_fdis_iu6_i1_bta_val_d = frn_fdis_iu6_i1_bta_val_l2; + assign stall_frn_fdis_iu6_i1_fusion_d = frn_fdis_iu6_i1_fusion_l2; + assign stall_frn_fdis_iu6_i1_spec_d = frn_fdis_iu6_i1_spec_l2; + assign stall_frn_fdis_iu6_i1_type_fp_d = frn_fdis_iu6_i1_type_fp_l2; + assign stall_frn_fdis_iu6_i1_type_ap_d = frn_fdis_iu6_i1_type_ap_l2; + assign stall_frn_fdis_iu6_i1_type_spv_d = frn_fdis_iu6_i1_type_spv_l2; + assign stall_frn_fdis_iu6_i1_type_st_d = frn_fdis_iu6_i1_type_st_l2; + assign stall_frn_fdis_iu6_i1_async_block_d = frn_fdis_iu6_i1_async_block_l2; + assign stall_frn_fdis_iu6_i1_np1_flush_d = frn_fdis_iu6_i1_np1_flush_l2; + assign stall_frn_fdis_iu6_i1_core_block_d = frn_fdis_iu6_i1_core_block_l2; + assign stall_frn_fdis_iu6_i1_isram_d = frn_fdis_iu6_i1_isram_l2; + assign stall_frn_fdis_iu6_i1_isload_d = frn_fdis_iu6_i1_isload_l2; + assign stall_frn_fdis_iu6_i1_isstore_d = frn_fdis_iu6_i1_isstore_l2; + assign stall_frn_fdis_iu6_i1_instr_d = frn_fdis_iu6_i1_instr_l2; + assign stall_frn_fdis_iu6_i1_ifar_d = frn_fdis_iu6_i1_ifar_l2; + assign stall_frn_fdis_iu6_i1_bta_d = frn_fdis_iu6_i1_bta_l2; + assign stall_frn_fdis_iu6_i1_br_pred_d = frn_fdis_iu6_i1_br_pred_l2; + assign stall_frn_fdis_iu6_i1_bh_update_d = frn_fdis_iu6_i1_bh_update_l2; + assign stall_frn_fdis_iu6_i1_bh0_hist_d = frn_fdis_iu6_i1_bh0_hist_l2; + assign stall_frn_fdis_iu6_i1_bh1_hist_d = frn_fdis_iu6_i1_bh1_hist_l2; + assign stall_frn_fdis_iu6_i1_bh2_hist_d = frn_fdis_iu6_i1_bh2_hist_l2; + assign stall_frn_fdis_iu6_i1_gshare_d = frn_fdis_iu6_i1_gshare_l2; + assign stall_frn_fdis_iu6_i1_ls_ptr_d = frn_fdis_iu6_i1_ls_ptr_l2; + assign stall_frn_fdis_iu6_i1_match_d = frn_fdis_iu6_i1_match_l2; + assign stall_frn_fdis_iu6_i1_ilat_d = frn_fdis_iu6_i1_ilat_l2; + assign stall_frn_fdis_iu6_i1_t1_v_d = frn_fdis_iu6_i1_t1_v_l2; + assign stall_frn_fdis_iu6_i1_t1_t_d = frn_fdis_iu6_i1_t1_t_l2; + assign stall_frn_fdis_iu6_i1_t1_a_d = frn_fdis_iu6_i1_t1_a_l2; + assign stall_frn_fdis_iu6_i1_t1_p_d = frn_fdis_iu6_i1_t1_p_l2; + assign stall_frn_fdis_iu6_i1_t2_v_d = frn_fdis_iu6_i1_t2_v_l2; + assign stall_frn_fdis_iu6_i1_t2_a_d = frn_fdis_iu6_i1_t2_a_l2; + assign stall_frn_fdis_iu6_i1_t2_p_d = frn_fdis_iu6_i1_t2_p_l2; + assign stall_frn_fdis_iu6_i1_t2_t_d = frn_fdis_iu6_i1_t2_t_l2; + assign stall_frn_fdis_iu6_i1_t3_v_d = frn_fdis_iu6_i1_t3_v_l2; + assign stall_frn_fdis_iu6_i1_t3_a_d = frn_fdis_iu6_i1_t3_a_l2; + assign stall_frn_fdis_iu6_i1_t3_p_d = frn_fdis_iu6_i1_t3_p_l2; + assign stall_frn_fdis_iu6_i1_t3_t_d = frn_fdis_iu6_i1_t3_t_l2; + assign stall_frn_fdis_iu6_i1_s1_v_d = frn_fdis_iu6_i1_s1_v_l2; + assign stall_frn_fdis_iu6_i1_s1_a_d = frn_fdis_iu6_i1_s1_a_l2; + assign stall_frn_fdis_iu6_i1_s1_p_d = frn_fdis_iu6_i1_s1_p_l2; + assign stall_frn_fdis_iu6_i1_s1_itag_d = frn_fdis_iu6_i1_s1_itag_l2; + assign stall_frn_fdis_iu6_i1_s1_t_d = frn_fdis_iu6_i1_s1_t_l2; + assign stall_frn_fdis_iu6_i1_s1_dep_hit_d = frn_fdis_iu6_i1_s1_dep_hit_l2; + assign stall_frn_fdis_iu6_i1_s2_v_d = frn_fdis_iu6_i1_s2_v_l2; + assign stall_frn_fdis_iu6_i1_s2_a_d = frn_fdis_iu6_i1_s2_a_l2; + assign stall_frn_fdis_iu6_i1_s2_p_d = frn_fdis_iu6_i1_s2_p_l2; + assign stall_frn_fdis_iu6_i1_s2_itag_d = frn_fdis_iu6_i1_s2_itag_l2; + assign stall_frn_fdis_iu6_i1_s2_t_d = frn_fdis_iu6_i1_s2_t_l2; + assign stall_frn_fdis_iu6_i1_s2_dep_hit_d = frn_fdis_iu6_i1_s2_dep_hit_l2; + assign stall_frn_fdis_iu6_i1_s3_v_d = frn_fdis_iu6_i1_s3_v_l2; + assign stall_frn_fdis_iu6_i1_s3_a_d = frn_fdis_iu6_i1_s3_a_l2; + assign stall_frn_fdis_iu6_i1_s3_p_d = frn_fdis_iu6_i1_s3_p_l2; + assign stall_frn_fdis_iu6_i1_s3_itag_d = frn_fdis_iu6_i1_s3_itag_l2; + assign stall_frn_fdis_iu6_i1_s3_t_d = frn_fdis_iu6_i1_s3_t_l2; + assign stall_frn_fdis_iu6_i1_s3_dep_hit_d = frn_fdis_iu6_i1_s3_dep_hit_l2; + + assign inc_0 = (fdec_frn_iu5_i0_vld & send_instructions); + assign inc_1 = (fdec_frn_iu5_i1_vld & send_instructions); + + + iuq_cpl_ctrl_inc #(.SIZE(`ITAG_SIZE_ENC), .WRAP(`CPL_Q_DEPTH - 1)) iu6_i0_itag_inc( + .inc({inc_0, inc_1}), + .i(next_itag_0_l2), + .o(i0_itag_next) + ); + + + iuq_cpl_ctrl_inc #(.SIZE(`ITAG_SIZE_ENC), .WRAP(`CPL_Q_DEPTH - 1)) iu6_i1_itag_inc( + .inc({inc_0, inc_1}), + .i(next_itag_1_l2), + .o(i1_itag_next) + ); + + assign next_itag_0_d = ((cp_flush_l2) == 1'b1) ? cp_rn_i0_itag : + i0_itag_next; + + assign next_itag_1_d = ((cp_flush_l2) == 1'b1) ? cp_rn_i1_itag : + i1_itag_next; + + assign cp_flush_d = cp_flush; + assign cp_flush_into_uc_d = cp_flush_into_uc; + assign br_iu_hold_d = ((br_iu_redirect | br_iu_hold_l2) | + (send_instructions & fdec_frn_iu5_i0_np1_flush) | + (send_instructions & fdec_frn_iu5_i1_vld & fdec_frn_iu5_i1_np1_flush)) & (~cp_flush_l2); + + assign gpr_send_cnt = {(fdec_frn_iu5_i0_t1_v & ~fdec_frn_iu5_i0_t1_t[0] & ~fdec_frn_iu5_i0_t1_t[1] & ~fdec_frn_iu5_i0_t1_t[2]), + (fdec_frn_iu5_i1_t1_v & ~fdec_frn_iu5_i1_t1_t[0] & ~fdec_frn_iu5_i1_t1_t[1] & ~fdec_frn_iu5_i1_t1_t[2])}; + + assign cr_send_cnt = {((fdec_frn_iu5_i0_t3_v & ~fdec_frn_iu5_i0_t3_t[0] & ~fdec_frn_iu5_i0_t3_t[1] & fdec_frn_iu5_i0_t3_t[2]) | + (fdec_frn_iu5_i0_t1_v & ~fdec_frn_iu5_i0_t1_t[0] & ~fdec_frn_iu5_i0_t1_t[1] & fdec_frn_iu5_i0_t1_t[2])), + ((fdec_frn_iu5_i1_t3_v & ~fdec_frn_iu5_i1_t3_t[0] & ~fdec_frn_iu5_i1_t3_t[1] & fdec_frn_iu5_i1_t3_t[2]) | + (fdec_frn_iu5_i1_t1_v & ~fdec_frn_iu5_i1_t1_t[0] & ~fdec_frn_iu5_i1_t1_t[1] & fdec_frn_iu5_i1_t1_t[2]))}; + + assign cr_send_t1_cnt = {(fdec_frn_iu5_i0_t1_v & ~fdec_frn_iu5_i0_t1_t[0] & ~fdec_frn_iu5_i0_t1_t[1] & fdec_frn_iu5_i0_t1_t[2]), + (fdec_frn_iu5_i1_t1_v & ~fdec_frn_iu5_i1_t1_t[0] & ~fdec_frn_iu5_i1_t1_t[1] & fdec_frn_iu5_i1_t1_t[2])}; + + assign cr_send_t3_cnt = {(fdec_frn_iu5_i0_t3_v & ~fdec_frn_iu5_i0_t3_t[0] & ~fdec_frn_iu5_i0_t3_t[1] & fdec_frn_iu5_i0_t3_t[2]), + (fdec_frn_iu5_i1_t3_v & ~fdec_frn_iu5_i1_t3_t[0] & ~fdec_frn_iu5_i1_t3_t[1] & fdec_frn_iu5_i1_t3_t[2])}; + + assign lr_send_cnt = {(fdec_frn_iu5_i0_t3_v & ~fdec_frn_iu5_i0_t3_t[0] & fdec_frn_iu5_i0_t3_t[1] & ~fdec_frn_iu5_i0_t3_t[2]), + (fdec_frn_iu5_i1_t3_v & ~fdec_frn_iu5_i1_t3_t[0] & fdec_frn_iu5_i1_t3_t[1] & ~fdec_frn_iu5_i1_t3_t[2])}; + + assign ctr_send_cnt = {(fdec_frn_iu5_i0_t2_v & ~fdec_frn_iu5_i0_t2_t[0] & fdec_frn_iu5_i0_t2_t[1] & fdec_frn_iu5_i0_t2_t[2]), + (fdec_frn_iu5_i1_t2_v & ~fdec_frn_iu5_i1_t2_t[0] & fdec_frn_iu5_i1_t2_t[1] & fdec_frn_iu5_i1_t2_t[2])}; + + assign xer_send_cnt = {(fdec_frn_iu5_i0_t2_v & fdec_frn_iu5_i0_t2_t[0] & ~fdec_frn_iu5_i0_t2_t[1] & ~fdec_frn_iu5_i0_t2_t[2]), + (fdec_frn_iu5_i1_t2_v & fdec_frn_iu5_i1_t2_t[0] & ~fdec_frn_iu5_i1_t2_t[1] & ~fdec_frn_iu5_i1_t2_t[2])}; + + assign ucode_send_cnt = {(fdec_frn_iu5_i0_ucode[1]), (fdec_frn_iu5_i1_ucode[1])}; + + assign cp_credit_cnt_mux = ({`CPL_Q_DEPTH_ENC{high_pri_mask_l2}} & cp_high_credit_cnt_l2) | + ({`CPL_Q_DEPTH_ENC{~high_pri_mask_l2}} & cp_med_credit_cnt_l2); + + assign cpl_credit_ok = ((~fdec_frn_iu5_i0_vld & ~fdec_frn_iu5_i1_vld) | + ((fdec_frn_iu5_i0_vld ^ fdec_frn_iu5_i1_vld) & |cp_credit_cnt_mux) | + (|cp_credit_cnt_mux[0:`CPL_Q_DEPTH_ENC - 1])); + + assign gpr_send_ok = (~gpr_send_cnt[0] & ~gpr_send_cnt[1]) | + ((gpr_send_cnt[0] ^ gpr_send_cnt[1]) & next_gpr_0_v) | + (next_gpr_0_v & next_gpr_1_v); + + assign cr_send_ok = (~cr_send_cnt[0] & ~cr_send_cnt[1]) | + ((cr_send_cnt[0] ^ cr_send_cnt[1]) & next_cr_0_v) | + (next_cr_0_v & next_cr_1_v); + + assign lr_send_ok = (~lr_send_cnt[0] & ~lr_send_cnt[1]) | + ((lr_send_cnt[0] ^ lr_send_cnt[1]) & next_lr_0_v) | + (next_lr_0_v & next_lr_1_v); + + assign ctr_send_ok = (~ctr_send_cnt[0] & ~ctr_send_cnt[1]) | + ((ctr_send_cnt[0] ^ ctr_send_cnt[1]) & next_ctr_0_v) | + (next_ctr_0_v & next_ctr_1_v); + + assign xer_send_ok = (~xer_send_cnt[0] & ~xer_send_cnt[1]) | + ((xer_send_cnt[0] ^ xer_send_cnt[1]) & next_xer_0_v) | + (next_xer_0_v & next_xer_1_v); + + assign cp_empty_ok = (((fdec_frn_iu5_i0_vld & fdec_frn_iu5_i0_core_block) | (fdec_frn_iu5_i1_vld & fdec_frn_iu5_i1_core_block)) & cp_rn_empty_l2) | + (~(fdec_frn_iu5_i0_vld & fdec_frn_iu5_i0_core_block) & ~(fdec_frn_iu5_i1_vld & fdec_frn_iu5_i1_core_block)); + + assign send_instructions = (cpl_credit_ok & gpr_send_ok & cr_send_ok & lr_send_ok & ctr_send_ok & xer_send_ok & cp_empty_ok & + au_iu_iu5_axu0_send_ok & au_iu_iu5_axu1_send_ok & fdec_frn_iu5_i0_vld) & (~(hold_instructions_l2)); + + assign hold_instructions_d = (fdis_frn_iu6_stall_d[0] & frn_fdis_iu6_i0_vld_d) | br_iu_hold_d | cp_flush_d; + + + // To AXU rename + assign iu_au_iu5_send_ok = (cpl_credit_ok & gpr_send_ok & cr_send_ok & lr_send_ok & ctr_send_ok & xer_send_ok & cp_empty_ok) & (~fdis_frn_iu6_stall_dly); + assign iu_au_iu5_next_itag_i0 = next_itag_0_l2; + assign iu_au_iu5_next_itag_i1 = next_itag_1_l2; + + + assign high_cnt_plus2_temp = cp_high_credit_cnt_l2 + value_2[31-`CPL_Q_DEPTH_ENC:31]; + assign high_cnt_plus2 = (high_cnt_plus2_temp > spr_cpcr3_cp_cnt) ? spr_cpcr3_cp_cnt : + high_cnt_plus2_temp; + + assign high_cnt_plus1_temp = cp_high_credit_cnt_l2 + value_1[31-`CPL_Q_DEPTH_ENC:31]; + assign high_cnt_plus1 = (high_cnt_plus1_temp > spr_cpcr3_cp_cnt) ? spr_cpcr3_cp_cnt : + high_cnt_plus1_temp; + + assign high_cnt_minus1_temp = cp_high_credit_cnt_l2 - value_1[31-`CPL_Q_DEPTH_ENC:31]; + assign high_cnt_minus1 = high_cnt_minus1_temp[0] == 1'b1 ? {1'b0, `CPL_Q_DEPTH_ENC'b0} : + high_cnt_minus1_temp; + + assign high_cnt_minus2_temp = cp_high_credit_cnt_l2 - value_2[31-`CPL_Q_DEPTH_ENC:31]; + assign high_cnt_minus2 = high_cnt_minus2_temp[0] == 1'b1 ? {1'b0, `CPL_Q_DEPTH_ENC'b0} : + high_cnt_minus2_temp; + + assign med_cnt_plus2_temp = cp_med_credit_cnt_l2 + value_2[31-`CPL_Q_DEPTH_ENC:31]; + assign med_cnt_plus2 = (med_cnt_plus2_temp > spr_cpcr5_cp_cnt) ? spr_cpcr5_cp_cnt : + med_cnt_plus2_temp; + + assign med_cnt_plus1_temp = cp_med_credit_cnt_l2 + value_1[31-`CPL_Q_DEPTH_ENC:31]; + assign med_cnt_plus1 = (med_cnt_plus1_temp > spr_cpcr5_cp_cnt) ? spr_cpcr5_cp_cnt : + med_cnt_plus1_temp; + + assign med_cnt_minus1_temp = cp_med_credit_cnt_l2 - value_1[31-`CPL_Q_DEPTH_ENC:31]; + assign med_cnt_minus1 = med_cnt_minus1_temp[0] == 1'b1 ? {1'b0, `CPL_Q_DEPTH_ENC'b0} : + med_cnt_minus1_temp; + + assign med_cnt_minus2_temp = cp_med_credit_cnt_l2 - value_2[31-`CPL_Q_DEPTH_ENC:31]; + assign med_cnt_minus2 = med_cnt_minus2_temp[0] == 1'b1 ? {1'b0, `CPL_Q_DEPTH_ENC'b0} : + med_cnt_minus2_temp; + + + always @(*) + begin: cp_credit_proc + cp_high_credit_cnt_d = cp_high_credit_cnt_l2; + cp_med_credit_cnt_d = cp_med_credit_cnt_l2; + + if (spr_cpcr_we == 1'b1 | cp_flush_l2 == 1'b1) + if (spr_single_issue == 1'b1) + begin + cp_high_credit_cnt_d = 7'b0000010; + cp_med_credit_cnt_d = 7'b0000010; + end + else if(spr_cpcr_we == 1'b1) + begin + cp_high_credit_cnt_d = spr_cpcr3_cp_cnt - value_1[31-`CPL_Q_DEPTH_ENC:31]; + cp_med_credit_cnt_d = spr_cpcr5_cp_cnt - value_1[31-`CPL_Q_DEPTH_ENC:31]; + end + else + begin + cp_high_credit_cnt_d = spr_cpcr3_cp_cnt; + cp_med_credit_cnt_d = spr_cpcr5_cp_cnt; + end + else + if (send_instructions == 1'b0) + begin + if (cp_rn_i0_v == 1'b1 ^ cp_rn_i1_v == 1'b1) + begin + cp_high_credit_cnt_d = high_cnt_plus1; + cp_med_credit_cnt_d = med_cnt_plus1; + end + else if (cp_rn_i0_v == 1'b1 & cp_rn_i1_v == 1'b1) + begin + cp_high_credit_cnt_d = high_cnt_plus2; + cp_med_credit_cnt_d = med_cnt_plus2; + end + end + else if (send_instructions == 1'b1) + begin + if (fdec_frn_iu5_i1_vld == 1'b1 & (cp_rn_i0_v == 1'b1 ^ cp_rn_i1_v == 1'b1)) + begin + cp_high_credit_cnt_d = high_cnt_minus1; + cp_med_credit_cnt_d = med_cnt_minus1; + end + else if (fdec_frn_iu5_i1_vld == 1'b0 & (cp_rn_i0_v == 1'b1 & cp_rn_i1_v == 1'b1)) + begin + cp_high_credit_cnt_d = high_cnt_plus1; + cp_med_credit_cnt_d = med_cnt_plus1; + end + else if (cp_rn_i0_v == 1'b0 & cp_rn_i1_v == 1'b0) + begin + if (fdec_frn_iu5_i1_vld == 1'b1) + begin + cp_high_credit_cnt_d = high_cnt_minus2; + cp_med_credit_cnt_d = med_cnt_minus2; + end + else + begin + cp_high_credit_cnt_d = high_cnt_minus1; + cp_med_credit_cnt_d = med_cnt_minus1; + end + end + end + end + + + always @(*) + begin: ucode_cnt_proc + ucode_cnt_d = ucode_cnt_l2; + + if (cp_flush_l2 == 1'b1 & cp_flush_into_uc_l2 == 1'b0) + ucode_cnt_d = ucode_cnt_save_l2 - value_1[32-`UCODE_ENTRIES_ENC:31]; + else if (cp_flush_l2 == 1'b1 & cp_flush_into_uc_l2 == 1'b1) + ucode_cnt_d = ucode_cnt_save_l2; + else + if (send_instructions == 1'b1 & (ucode_send_cnt[0] == 1'b1 | ucode_send_cnt[1] == 1'b1)) + ucode_cnt_d = ucode_cnt_l2 + value_1[32-`UCODE_ENTRIES_ENC:31]; + end + + + always @(*) + begin: ucode_cnt_save_proc + ucode_cnt_save_d = ucode_cnt_save_l2; + + if (cp_rn_uc_credit_free == 1'b1) + ucode_cnt_save_d = ucode_cnt_save_l2 + value_1[32-`UCODE_ENTRIES_ENC:31]; + end + + assign ucode_cnt_i0 = (ucode_send_cnt[0] == 1'b1) ? ucode_cnt_l2 + value_1[32-`UCODE_ENTRIES_ENC:31] : + ucode_cnt_l2; + assign ucode_cnt_i1 = (ucode_send_cnt[1] == 1'b1) ? ucode_cnt_l2 + value_1[32-`UCODE_ENTRIES_ENC:31] : + ucode_cnt_l2; + + //----------------------------------------------------------------------- + //-- Outputs + //----------------------------------------------------------------------- + + assign frn_fdec_iu5_stall = (~(cpl_credit_ok & gpr_send_ok & cr_send_ok & lr_send_ok & ctr_send_ok & xer_send_ok & cp_empty_ok)) | br_iu_hold_l2 | au_iu_iu5_stall | (fdec_frn_iu5_i0_vld & fdis_frn_iu6_stall_dly); // AXU Rename Stall + + assign frn_fdis_iu6_i0_act = fdec_frn_iu5_i0_vld & (~(fdis_frn_iu6_stall_dly)); + assign frn_fdis_iu6_i0_vld_d = ((send_instructions & fdec_frn_iu5_i0_vld) | (frn_fdis_iu6_i0_vld_l2 & fdis_frn_iu6_stall_dly)) & (~(cp_flush_l2)); + assign frn_fdis_iu6_i0_itag_d = next_itag_0_l2; + assign frn_fdis_iu6_i0_ucode_d = fdec_frn_iu5_i0_ucode; + assign frn_fdis_iu6_i0_ucode_cnt_d = ucode_cnt_i0; + assign frn_fdis_iu6_i0_2ucode_d = fdec_frn_iu5_i0_2ucode; + assign frn_fdis_iu6_i0_fuse_nop_d = fdec_frn_iu5_i0_fuse_nop; + assign frn_fdis_iu6_i0_rte_fx0_d = fdec_frn_iu5_i0_rte_fx0; + assign frn_fdis_iu6_i0_rte_fx1_d = fdec_frn_iu5_i0_rte_fx1; + assign frn_fdis_iu6_i0_rte_lq_d = fdec_frn_iu5_i0_rte_lq; + assign frn_fdis_iu6_i0_rte_sq_d = fdec_frn_iu5_i0_rte_sq; + assign frn_fdis_iu6_i0_rte_axu0_d = fdec_frn_iu5_i0_rte_axu0; + assign frn_fdis_iu6_i0_rte_axu1_d = fdec_frn_iu5_i0_rte_axu1; + assign frn_fdis_iu6_i0_valop_d = fdec_frn_iu5_i0_valop; + assign frn_fdis_iu6_i0_ord_d = fdec_frn_iu5_i0_ord; + assign frn_fdis_iu6_i0_cord_d = fdec_frn_iu5_i0_cord; + assign frn_fdis_iu6_i0_error_d = fdec_frn_iu5_i0_error; + assign frn_fdis_iu6_i0_btb_entry_d = fdec_frn_iu5_i0_btb_entry; + assign frn_fdis_iu6_i0_btb_hist_d = fdec_frn_iu5_i0_btb_hist; + assign frn_fdis_iu6_i0_bta_val_d = fdec_frn_iu5_i0_bta_val; + assign frn_fdis_iu6_i0_fusion_d = fdec_frn_iu5_i0_fusion; + assign frn_fdis_iu6_i0_spec_d = fdec_frn_iu5_i0_spec; + assign frn_fdis_iu6_i0_type_fp_d = fdec_frn_iu5_i0_type_fp; + assign frn_fdis_iu6_i0_type_ap_d = fdec_frn_iu5_i0_type_ap; + assign frn_fdis_iu6_i0_type_spv_d = fdec_frn_iu5_i0_type_spv; + assign frn_fdis_iu6_i0_type_st_d = fdec_frn_iu5_i0_type_st; + assign frn_fdis_iu6_i0_async_block_d = fdec_frn_iu5_i0_async_block; + assign frn_fdis_iu6_i0_np1_flush_d = fdec_frn_iu5_i0_np1_flush; + assign frn_fdis_iu6_i0_core_block_d = fdec_frn_iu5_i0_core_block; + assign frn_fdis_iu6_i0_isram_d = fdec_frn_iu5_i0_isram; + assign frn_fdis_iu6_i0_isload_d = fdec_frn_iu5_i0_rte_lq & fdec_frn_iu5_i0_isload; + assign frn_fdis_iu6_i0_isstore_d = fdec_frn_iu5_i0_rte_sq & fdec_frn_iu5_i0_isstore; + assign frn_fdis_iu6_i0_instr_d = fdec_frn_iu5_i0_instr; + assign frn_fdis_iu6_i0_ifar_d = fdec_frn_iu5_i0_ifar; + assign frn_fdis_iu6_i0_bta_d = fdec_frn_iu5_i0_bta; + assign frn_fdis_iu6_i0_br_pred_d = fdec_frn_iu5_i0_br_pred; + assign frn_fdis_iu6_i0_bh_update_d = fdec_frn_iu5_i0_bh_update; + assign frn_fdis_iu6_i0_bh0_hist_d = fdec_frn_iu5_i0_bh0_hist; + assign frn_fdis_iu6_i0_bh1_hist_d = fdec_frn_iu5_i0_bh1_hist; + assign frn_fdis_iu6_i0_bh2_hist_d = fdec_frn_iu5_i0_bh2_hist; + assign frn_fdis_iu6_i0_gshare_d = fdec_frn_iu5_i0_gshare; + assign frn_fdis_iu6_i0_ls_ptr_d = fdec_frn_iu5_i0_ls_ptr; + assign frn_fdis_iu6_i0_match_d = fdec_frn_iu5_i0_match; + assign frn_fdis_iu6_i0_ilat_d = fdec_frn_iu5_i0_ilat; + assign frn_fdis_iu6_i0_t1_v_d = fdec_frn_iu5_i0_t1_v & (send_instructions & fdec_frn_iu5_i0_vld); + assign frn_fdis_iu6_i0_t1_t_d = fdec_frn_iu5_i0_t1_t; + assign frn_fdis_iu6_i0_t1_a_d = fdec_frn_iu5_i0_t1_a; + assign frn_fdis_iu6_i0_t1_p_d = ({`GPR_POOL_ENC{(fdec_frn_iu5_i0_t1_t == `gpr_t)}} & next_gpr_0) | + ({`GPR_POOL_ENC{(fdec_frn_iu5_i0_t1_t == `cr_t)}} & {1'b0, next_cr_0}) | + ({`GPR_POOL_ENC{(fdec_frn_iu5_i0_t1_t == `axu0_t)}} & au_iu_iu5_i0_t1_p) | + ({`GPR_POOL_ENC{(fdec_frn_iu5_i0_t1_t == `axu1_t)}} & au_iu_iu5_i0_t1_p); + assign frn_fdis_iu6_i0_t2_v_d = fdec_frn_iu5_i0_t2_v & (send_instructions & fdec_frn_iu5_i0_vld); + assign frn_fdis_iu6_i0_t2_a_d = fdec_frn_iu5_i0_t2_a; + assign frn_fdis_iu6_i0_t2_p_d = ({`GPR_POOL_ENC{(fdec_frn_iu5_i0_t2_t == `ctr_t)}} & {{`GPR_POOL_ENC-`CTR_POOL_ENC{1'b0}}, next_ctr_0}) | + ({`GPR_POOL_ENC{(fdec_frn_iu5_i0_t2_t == `xer_t)}} & {{`GPR_POOL_ENC-`XER_POOL_ENC{1'b0}}, next_xer_0}) | + ({`GPR_POOL_ENC{(fdec_frn_iu5_i0_t2_t == `axu0_t)}} & au_iu_iu5_i0_t2_p) | + ({`GPR_POOL_ENC{(fdec_frn_iu5_i0_t2_t == `axu1_t)}} & au_iu_iu5_i0_t2_p); + assign frn_fdis_iu6_i0_t2_t_d = fdec_frn_iu5_i0_t2_t; + assign frn_fdis_iu6_i0_t3_v_d = fdec_frn_iu5_i0_t3_v & (send_instructions & fdec_frn_iu5_i0_vld); + assign frn_fdis_iu6_i0_t3_a_d = fdec_frn_iu5_i0_t3_a; + assign frn_fdis_iu6_i0_t3_p_d = ({`GPR_POOL_ENC{(fdec_frn_iu5_i0_t3_t == `lr_t)}} & {{`GPR_POOL_ENC-`LR_POOL_ENC{1'b0}}, next_lr_0}) | + ({`GPR_POOL_ENC{(fdec_frn_iu5_i0_t3_t == `cr_t)}} & {1'b0, next_cr_0}); + assign frn_fdis_iu6_i0_t3_t_d = fdec_frn_iu5_i0_t3_t; + + assign frn_fdis_iu6_i0_s1_v_d = fdec_frn_iu5_i0_s1_v & (send_instructions & fdec_frn_iu5_i0_vld); + assign frn_fdis_iu6_i0_s1_a_d = fdec_frn_iu5_i0_s1_a; + assign frn_fdis_iu6_i0_s1_p_d = ({`GPR_POOL_ENC{(fdec_frn_iu5_i0_s1_t == `gpr_t)}} & gpr_iu5_i0_src1_p) | + ({`GPR_POOL_ENC{(fdec_frn_iu5_i0_s1_t == `cr_t)}} & {{`GPR_POOL_ENC-`CR_POOL_ENC{1'b0}}, cr_iu5_i0_src1_p}) | + ({`GPR_POOL_ENC{(fdec_frn_iu5_i0_s1_t == `lr_t)}} & {{`GPR_POOL_ENC-`LR_POOL_ENC{1'b0}}, lr_iu5_i0_src1_p}) | + ({`GPR_POOL_ENC{(fdec_frn_iu5_i0_s1_t == `ctr_t)}} & {{`GPR_POOL_ENC-`CTR_POOL_ENC{1'b0}}, ctr_iu5_i0_src1_p}) | + ({`GPR_POOL_ENC{(fdec_frn_iu5_i0_s1_t == `xer_t)}} & {{`GPR_POOL_ENC-`XER_POOL_ENC{1'b0}}, xer_iu5_i0_src1_p}) | + ({`GPR_POOL_ENC{(fdec_frn_iu5_i0_s1_t == `axu0_t)}} & au_iu_iu5_i0_s1_p) | + ({`GPR_POOL_ENC{(fdec_frn_iu5_i0_s1_t == `axu1_t)}} & au_iu_iu5_i0_s1_p); + assign frn_fdis_iu6_i0_s1_itag_d = ({`ITAG_SIZE_ENC{(fdec_frn_iu5_i0_s1_t == `gpr_t)}} & gpr_iu5_i0_src1_itag) | + ({`ITAG_SIZE_ENC{(fdec_frn_iu5_i0_s1_t == `cr_t)}} & cr_iu5_i0_src1_itag) | + ({`ITAG_SIZE_ENC{(fdec_frn_iu5_i0_s1_t == `lr_t)}} & lr_iu5_i0_src1_itag) | + ({`ITAG_SIZE_ENC{(fdec_frn_iu5_i0_s1_t == `ctr_t)}} & ctr_iu5_i0_src1_itag) | + ({`ITAG_SIZE_ENC{(fdec_frn_iu5_i0_s1_t == `xer_t)}} & xer_iu5_i0_src1_itag) | + ({`ITAG_SIZE_ENC{(fdec_frn_iu5_i0_s1_t == `axu0_t)}} & au_iu_iu5_i0_s1_itag) | + ({`ITAG_SIZE_ENC{(fdec_frn_iu5_i0_s1_t == `axu1_t)}} & au_iu_iu5_i0_s1_itag); + assign frn_fdis_iu6_i0_s1_t_d = fdec_frn_iu5_i0_s1_t; + assign frn_fdis_iu6_i0_s2_v_d = fdec_frn_iu5_i0_s2_v & (send_instructions & fdec_frn_iu5_i0_vld); + assign frn_fdis_iu6_i0_s2_a_d = fdec_frn_iu5_i0_s2_a; + assign frn_fdis_iu6_i0_s2_p_d = ({`GPR_POOL_ENC{(fdec_frn_iu5_i0_s2_t == `gpr_t)}} & gpr_iu5_i0_src2_p) | + ({`GPR_POOL_ENC{(fdec_frn_iu5_i0_s2_t == `cr_t)}} & {{`GPR_POOL_ENC-`CR_POOL_ENC{1'b0}}, cr_iu5_i0_src2_p}) | + ({`GPR_POOL_ENC{(fdec_frn_iu5_i0_s2_t == `lr_t)}} & {{`GPR_POOL_ENC-`LR_POOL_ENC{1'b0}}, lr_iu5_i0_src2_p}) | + ({`GPR_POOL_ENC{(fdec_frn_iu5_i0_s2_t == `ctr_t)}} & {{`GPR_POOL_ENC-`CTR_POOL_ENC{1'b0}}, ctr_iu5_i0_src2_p}) | + ({`GPR_POOL_ENC{(fdec_frn_iu5_i0_s2_t == `xer_t)}} & {{`GPR_POOL_ENC-`XER_POOL_ENC{1'b0}}, xer_iu5_i0_src2_p}) | + ({`GPR_POOL_ENC{(fdec_frn_iu5_i0_s2_t == `axu0_t)}} & au_iu_iu5_i0_s2_p) | + ({`GPR_POOL_ENC{(fdec_frn_iu5_i0_s2_t == `axu1_t)}} & au_iu_iu5_i0_s2_p); + assign frn_fdis_iu6_i0_s2_itag_d = ({`ITAG_SIZE_ENC{(fdec_frn_iu5_i0_s2_t == `gpr_t)}} & gpr_iu5_i0_src2_itag) | + ({`ITAG_SIZE_ENC{(fdec_frn_iu5_i0_s2_t == `cr_t)}} & cr_iu5_i0_src2_itag) | + ({`ITAG_SIZE_ENC{(fdec_frn_iu5_i0_s2_t == `lr_t)}} & lr_iu5_i0_src2_itag) | + ({`ITAG_SIZE_ENC{(fdec_frn_iu5_i0_s2_t == `ctr_t)}} & ctr_iu5_i0_src2_itag) | + ({`ITAG_SIZE_ENC{(fdec_frn_iu5_i0_s2_t == `xer_t)}} & xer_iu5_i0_src2_itag) | + ({`ITAG_SIZE_ENC{(fdec_frn_iu5_i0_s2_t == `axu0_t)}} & au_iu_iu5_i0_s2_itag) | + ({`ITAG_SIZE_ENC{(fdec_frn_iu5_i0_s2_t == `axu1_t)}} & au_iu_iu5_i0_s2_itag); + assign frn_fdis_iu6_i0_s2_t_d = fdec_frn_iu5_i0_s2_t; + assign frn_fdis_iu6_i0_s3_v_d = fdec_frn_iu5_i0_s3_v & (send_instructions & fdec_frn_iu5_i0_vld); + assign frn_fdis_iu6_i0_s3_a_d = fdec_frn_iu5_i0_s3_a; + assign frn_fdis_iu6_i0_s3_p_d = ({`GPR_POOL_ENC{(fdec_frn_iu5_i0_s3_t == `gpr_t)}} & gpr_iu5_i0_src3_p) | + ({`GPR_POOL_ENC{(fdec_frn_iu5_i0_s3_t == `cr_t)}} & {{`GPR_POOL_ENC-`CR_POOL_ENC{1'b0}}, cr_iu5_i0_src3_p}) | + ({`GPR_POOL_ENC{(fdec_frn_iu5_i0_s3_t == `lr_t)}} & {{`GPR_POOL_ENC-`LR_POOL_ENC{1'b0}}, lr_iu5_i0_src3_p}) | + ({`GPR_POOL_ENC{(fdec_frn_iu5_i0_s3_t == `ctr_t)}} & {{`GPR_POOL_ENC-`CTR_POOL_ENC{1'b0}}, ctr_iu5_i0_src3_p}) | + ({`GPR_POOL_ENC{(fdec_frn_iu5_i0_s3_t == `xer_t)}} & {{`GPR_POOL_ENC-`XER_POOL_ENC{1'b0}}, xer_iu5_i0_src3_p}) | + ({`GPR_POOL_ENC{(fdec_frn_iu5_i0_s3_t == `axu0_t)}} & au_iu_iu5_i0_s3_p) | + ({`GPR_POOL_ENC{(fdec_frn_iu5_i0_s3_t == `axu1_t)}} & au_iu_iu5_i0_s3_p); + assign frn_fdis_iu6_i0_s3_itag_d = ({`ITAG_SIZE_ENC{(fdec_frn_iu5_i0_s3_t == `gpr_t)}} & gpr_iu5_i0_src3_itag) | + ({`ITAG_SIZE_ENC{(fdec_frn_iu5_i0_s3_t == `cr_t)}} & cr_iu5_i0_src3_itag) | + ({`ITAG_SIZE_ENC{(fdec_frn_iu5_i0_s3_t == `lr_t)}} & lr_iu5_i0_src3_itag) | + ({`ITAG_SIZE_ENC{(fdec_frn_iu5_i0_s3_t == `ctr_t)}} & ctr_iu5_i0_src3_itag) | + ({`ITAG_SIZE_ENC{(fdec_frn_iu5_i0_s3_t == `xer_t)}} & xer_iu5_i0_src3_itag) | + ({`ITAG_SIZE_ENC{(fdec_frn_iu5_i0_s3_t == `axu0_t)}} & au_iu_iu5_i0_s3_itag) | + ({`ITAG_SIZE_ENC{(fdec_frn_iu5_i0_s3_t == `axu1_t)}} & au_iu_iu5_i0_s3_itag); + assign frn_fdis_iu6_i0_s3_t_d = fdec_frn_iu5_i0_s3_t; + + assign frn_fdis_iu6_i1_act = fdec_frn_iu5_i0_vld & (~(fdis_frn_iu6_stall_dly)); // This is purposely I0 to allow single instruction issue + assign frn_fdis_iu6_i1_vld_d = (((send_instructions & fdec_frn_iu5_i1_vld) & (~(fdec_frn_iu5_i0_vld & fdec_frn_iu5_i0_np1_flush))) | (frn_fdis_iu6_i1_vld_l2 & fdis_frn_iu6_stall_dly)) & (~(cp_flush_l2)); + assign frn_fdis_iu6_i1_itag_d = next_itag_1_l2; + assign frn_fdis_iu6_i1_ucode_d = fdec_frn_iu5_i1_ucode; + assign frn_fdis_iu6_i1_ucode_cnt_d = ucode_cnt_i1; + assign frn_fdis_iu6_i1_fuse_nop_d = fdec_frn_iu5_i1_fuse_nop; + assign frn_fdis_iu6_i1_rte_fx0_d = fdec_frn_iu5_i1_rte_fx0 & ~spr_single_issue & ~(fdec_frn_iu5_i0_vld & fdec_frn_iu5_i0_np1_flush); + assign frn_fdis_iu6_i1_rte_fx1_d = fdec_frn_iu5_i1_rte_fx1 & ~spr_single_issue & ~(fdec_frn_iu5_i0_vld & fdec_frn_iu5_i0_np1_flush); + assign frn_fdis_iu6_i1_rte_lq_d = fdec_frn_iu5_i1_rte_lq & ~spr_single_issue & ~(fdec_frn_iu5_i0_vld & fdec_frn_iu5_i0_np1_flush); + assign frn_fdis_iu6_i1_rte_sq_d = fdec_frn_iu5_i1_rte_sq & ~spr_single_issue & ~(fdec_frn_iu5_i0_vld & fdec_frn_iu5_i0_np1_flush); + assign frn_fdis_iu6_i1_rte_axu0_d = fdec_frn_iu5_i1_rte_axu0 & ~spr_single_issue & ~(fdec_frn_iu5_i0_vld & fdec_frn_iu5_i0_np1_flush); + assign frn_fdis_iu6_i1_rte_axu1_d = fdec_frn_iu5_i1_rte_axu1 & ~spr_single_issue & ~(fdec_frn_iu5_i0_vld & fdec_frn_iu5_i0_np1_flush); + assign frn_fdis_iu6_i1_valop_d = fdec_frn_iu5_i1_valop; + assign frn_fdis_iu6_i1_ord_d = fdec_frn_iu5_i1_ord; + assign frn_fdis_iu6_i1_cord_d = fdec_frn_iu5_i1_cord; + assign frn_fdis_iu6_i1_error_d = fdec_frn_iu5_i1_error; + assign frn_fdis_iu6_i1_btb_entry_d = fdec_frn_iu5_i1_btb_entry; + assign frn_fdis_iu6_i1_btb_hist_d = fdec_frn_iu5_i1_btb_hist; + assign frn_fdis_iu6_i1_bta_val_d = fdec_frn_iu5_i1_bta_val; + assign frn_fdis_iu6_i1_fusion_d = fdec_frn_iu5_i1_fusion; + assign frn_fdis_iu6_i1_spec_d = fdec_frn_iu5_i1_spec; + assign frn_fdis_iu6_i1_type_fp_d = fdec_frn_iu5_i1_type_fp; + assign frn_fdis_iu6_i1_type_ap_d = fdec_frn_iu5_i1_type_ap; + assign frn_fdis_iu6_i1_type_spv_d = fdec_frn_iu5_i1_type_spv; + assign frn_fdis_iu6_i1_type_st_d = fdec_frn_iu5_i1_type_st; + assign frn_fdis_iu6_i1_async_block_d = fdec_frn_iu5_i1_async_block; + assign frn_fdis_iu6_i1_np1_flush_d = fdec_frn_iu5_i1_np1_flush; + assign frn_fdis_iu6_i1_core_block_d = fdec_frn_iu5_i1_core_block; + assign frn_fdis_iu6_i1_isram_d = fdec_frn_iu5_i1_isram; + assign frn_fdis_iu6_i1_isload_d = fdec_frn_iu5_i1_rte_lq & fdec_frn_iu5_i1_isload; + assign frn_fdis_iu6_i1_isstore_d = fdec_frn_iu5_i1_rte_sq & fdec_frn_iu5_i1_isstore; + assign frn_fdis_iu6_i1_instr_d = fdec_frn_iu5_i1_instr; + assign frn_fdis_iu6_i1_ifar_d = fdec_frn_iu5_i1_ifar; + assign frn_fdis_iu6_i1_bta_d = fdec_frn_iu5_i1_bta; + assign frn_fdis_iu6_i1_br_pred_d = fdec_frn_iu5_i1_br_pred; + assign frn_fdis_iu6_i1_bh_update_d = fdec_frn_iu5_i1_bh_update; + assign frn_fdis_iu6_i1_bh0_hist_d = fdec_frn_iu5_i1_bh0_hist; + assign frn_fdis_iu6_i1_bh1_hist_d = fdec_frn_iu5_i1_bh1_hist; + assign frn_fdis_iu6_i1_bh2_hist_d = fdec_frn_iu5_i1_bh2_hist; + assign frn_fdis_iu6_i1_gshare_d = fdec_frn_iu5_i1_gshare; + assign frn_fdis_iu6_i1_ls_ptr_d = fdec_frn_iu5_i1_ls_ptr; + assign frn_fdis_iu6_i1_match_d = fdec_frn_iu5_i1_match; + assign frn_fdis_iu6_i1_ilat_d = fdec_frn_iu5_i1_ilat; + assign frn_fdis_iu6_i1_t1_v_d = fdec_frn_iu5_i1_t1_v & (send_instructions & fdec_frn_iu5_i1_vld); + assign frn_fdis_iu6_i1_t1_t_d = fdec_frn_iu5_i1_t1_t; + assign frn_fdis_iu6_i1_t1_a_d = fdec_frn_iu5_i1_t1_a; + assign frn_fdis_iu6_i1_t2_v_d = fdec_frn_iu5_i1_t2_v & (send_instructions & fdec_frn_iu5_i1_vld); + assign frn_fdis_iu6_i1_t2_a_d = fdec_frn_iu5_i1_t2_a; + + + always @(fdec_frn_iu5_i0_t1_v or fdec_frn_iu5_i0_t1_t or fdec_frn_iu5_i1_t1_t or fdec_frn_iu5_i1_t1_a or next_gpr_0 or next_gpr_1 or next_cr_1 or next_cr_0 or au_iu_iu5_i0_t1_p or au_iu_iu5_i1_t1_p) + begin: tar1_proc + frn_fdis_iu6_i1_t1_p_d = fdec_frn_iu5_i1_t1_a; + if (fdec_frn_iu5_i0_t1_v == 1'b1 & fdec_frn_iu5_i0_t1_t == `gpr_t & fdec_frn_iu5_i1_t1_t == `gpr_t) + frn_fdis_iu6_i1_t1_p_d = next_gpr_1; + else if (fdec_frn_iu5_i1_t1_t == `gpr_t) + frn_fdis_iu6_i1_t1_p_d = next_gpr_0; + else if (fdec_frn_iu5_i0_t1_v == 1'b1 & fdec_frn_iu5_i0_t1_t == `cr_t & fdec_frn_iu5_i1_t1_t == `cr_t) + frn_fdis_iu6_i1_t1_p_d = {1'b0, next_cr_1}; + else if (fdec_frn_iu5_i1_t1_t == `cr_t) + frn_fdis_iu6_i1_t1_p_d = {1'b0, next_cr_0}; + //AXU + else if (fdec_frn_iu5_i0_t1_v == 1'b1 & fdec_frn_iu5_i0_t1_t == `axu1_t & fdec_frn_iu5_i1_t1_t == `axu1_t) + frn_fdis_iu6_i1_t1_p_d = au_iu_iu5_i1_t1_p; + else if ((fdec_frn_iu5_i1_t1_t == `axu0_t) | (fdec_frn_iu5_i1_t1_t == `axu1_t)) + frn_fdis_iu6_i1_t1_p_d = au_iu_iu5_i0_t1_p; + end + + + always @(fdec_frn_iu5_i0_t2_v or fdec_frn_iu5_i0_t2_t or fdec_frn_iu5_i1_t2_t or fdec_frn_iu5_i1_t2_a or next_ctr_1 or next_xer_1 or next_ctr_0 or next_xer_0 or au_iu_iu5_i0_t2_p or au_iu_iu5_i1_t2_p) + begin: tar2_proc + frn_fdis_iu6_i1_t2_p_d = fdec_frn_iu5_i1_t2_a; + if (fdec_frn_iu5_i0_t2_v == 1'b1 & fdec_frn_iu5_i0_t2_t == `ctr_t & fdec_frn_iu5_i1_t2_t == `ctr_t) + frn_fdis_iu6_i1_t2_p_d = {{`GPR_POOL_ENC-`CTR_POOL_ENC{1'b0}}, next_ctr_1}; + else if (fdec_frn_iu5_i0_t2_v == 1'b1 & fdec_frn_iu5_i0_t2_t == `xer_t & fdec_frn_iu5_i1_t2_t == `xer_t) + frn_fdis_iu6_i1_t2_p_d = {{`GPR_POOL_ENC-`XER_POOL_ENC{1'b0}}, next_xer_1}; + else if (fdec_frn_iu5_i1_t2_t == `ctr_t) + frn_fdis_iu6_i1_t2_p_d = {{`GPR_POOL_ENC-`CTR_POOL_ENC{1'b0}}, next_ctr_0}; + else if (fdec_frn_iu5_i1_t2_t == `xer_t) + frn_fdis_iu6_i1_t2_p_d = {{`GPR_POOL_ENC-`XER_POOL_ENC{1'b0}}, next_xer_0}; + //AXU + else if (fdec_frn_iu5_i0_t2_v == 1'b1 & fdec_frn_iu5_i0_t2_t == `axu0_t & fdec_frn_iu5_i1_t2_t == `axu0_t) + frn_fdis_iu6_i1_t2_p_d = au_iu_iu5_i1_t2_p; + else if (fdec_frn_iu5_i1_t2_t == `axu0_t) + frn_fdis_iu6_i1_t2_p_d = au_iu_iu5_i0_t2_p; + end + + assign frn_fdis_iu6_i1_t2_t_d = fdec_frn_iu5_i1_t2_t; + assign frn_fdis_iu6_i1_t3_v_d = fdec_frn_iu5_i1_t3_v & (send_instructions & fdec_frn_iu5_i1_vld); + assign frn_fdis_iu6_i1_t3_a_d = fdec_frn_iu5_i1_t3_a; + + + always @(fdec_frn_iu5_i0_t3_v or fdec_frn_iu5_i0_t3_t or fdec_frn_iu5_i1_t3_t or fdec_frn_iu5_i1_t3_a or next_lr_1 or next_lr_0 or next_cr_1 or next_cr_0 or fdec_frn_iu5_i0_t1_v or fdec_frn_iu5_i0_t1_t) + begin: tar3_proc + frn_fdis_iu6_i1_t3_p_d = fdec_frn_iu5_i1_t3_a; + if (fdec_frn_iu5_i0_t3_v == 1'b1 & fdec_frn_iu5_i0_t3_t == `lr_t & fdec_frn_iu5_i1_t3_t == `lr_t) + frn_fdis_iu6_i1_t3_p_d = {{`GPR_POOL_ENC-`LR_POOL_ENC{1'b0}}, next_lr_1}; + else if (fdec_frn_iu5_i0_t3_v == 1'b1 & fdec_frn_iu5_i0_t3_t == `cr_t & fdec_frn_iu5_i1_t3_t == `cr_t) + frn_fdis_iu6_i1_t3_p_d = {{`GPR_POOL_ENC-`CR_POOL_ENC{1'b0}}, next_cr_1}; + else if (fdec_frn_iu5_i0_t1_v == 1'b1 & fdec_frn_iu5_i0_t1_t == `cr_t & fdec_frn_iu5_i1_t3_t == `cr_t) + frn_fdis_iu6_i1_t3_p_d = {{`GPR_POOL_ENC-`CR_POOL_ENC{1'b0}}, next_cr_1}; + else if (fdec_frn_iu5_i1_t3_t == `lr_t) + frn_fdis_iu6_i1_t3_p_d = {{`GPR_POOL_ENC-`LR_POOL_ENC{1'b0}}, next_lr_0}; + else if (fdec_frn_iu5_i1_t3_t == `cr_t) + frn_fdis_iu6_i1_t3_p_d = {{`GPR_POOL_ENC-`CR_POOL_ENC{1'b0}}, next_cr_0}; + end + + assign frn_fdis_iu6_i1_t3_t_d = fdec_frn_iu5_i1_t3_t; + assign frn_fdis_iu6_i1_s1_v_d = fdec_frn_iu5_i1_s1_v & (send_instructions & fdec_frn_iu5_i1_vld); + assign frn_fdis_iu6_i1_s1_a_d = fdec_frn_iu5_i1_s1_a; + assign frn_fdis_iu6_i1_s1_p_d = ({`GPR_POOL_ENC{(fdec_frn_iu5_i1_s1_t == `gpr_t)}} & gpr_iu5_i1_src1_p) | + ({`GPR_POOL_ENC{(fdec_frn_iu5_i1_s1_t == `cr_t)}} & {{`GPR_POOL_ENC-`CR_POOL_ENC{1'b0}}, cr_iu5_i1_src1_p}) | + ({`GPR_POOL_ENC{(fdec_frn_iu5_i1_s1_t == `lr_t)}} & {{`GPR_POOL_ENC-`LR_POOL_ENC{1'b0}}, lr_iu5_i1_src1_p}) | + ({`GPR_POOL_ENC{(fdec_frn_iu5_i1_s1_t == `ctr_t)}} & {{`GPR_POOL_ENC-`CTR_POOL_ENC{1'b0}}, ctr_iu5_i1_src1_p}) | + ({`GPR_POOL_ENC{(fdec_frn_iu5_i1_s1_t == `xer_t)}} & {{`GPR_POOL_ENC-`XER_POOL_ENC{1'b0}}, xer_iu5_i1_src1_p}) | + ({`GPR_POOL_ENC{(fdec_frn_iu5_i1_s1_t == `axu0_t)}} & au_iu_iu5_i1_s1_p) | + ({`GPR_POOL_ENC{(fdec_frn_iu5_i1_s1_t == `axu1_t)}} & au_iu_iu5_i1_s1_p); + assign frn_fdis_iu6_i1_s1_itag_d = ({`ITAG_SIZE_ENC{(fdec_frn_iu5_i1_s1_t == `gpr_t)}} & gpr_iu5_i1_src1_itag) | + ({`ITAG_SIZE_ENC{(fdec_frn_iu5_i1_s1_t == `cr_t)}} & cr_iu5_i1_src1_itag) | + ({`ITAG_SIZE_ENC{(fdec_frn_iu5_i1_s1_t == `lr_t)}} & lr_iu5_i1_src1_itag) | + ({`ITAG_SIZE_ENC{(fdec_frn_iu5_i1_s1_t == `ctr_t)}} & ctr_iu5_i1_src1_itag) | + ({`ITAG_SIZE_ENC{(fdec_frn_iu5_i1_s1_t == `xer_t)}} & xer_iu5_i1_src1_itag) | + ({`ITAG_SIZE_ENC{(fdec_frn_iu5_i1_s1_t == `axu0_t)}} & au_iu_iu5_i1_s1_itag) | + ({`ITAG_SIZE_ENC{(fdec_frn_iu5_i1_s1_t == `axu1_t)}} & au_iu_iu5_i1_s1_itag); + assign frn_fdis_iu6_i1_s1_t_d = fdec_frn_iu5_i1_s1_t; + assign frn_fdis_iu6_i1_s1_dep_hit_d = ((fdec_frn_iu5_i1_s1_t == `gpr_t) & gpr_s1_dep_hit) | + ((fdec_frn_iu5_i1_s1_t == `cr_t) & cr_s1_dep_hit) | + ((fdec_frn_iu5_i1_s1_t == `lr_t) & lr_s1_dep_hit) | + ((fdec_frn_iu5_i1_s1_t == `ctr_t) & ctr_s1_dep_hit) | + ((fdec_frn_iu5_i1_s1_t == `xer_t) & xer_s1_dep_hit) | + ((fdec_frn_iu5_i1_s1_t == `axu0_t) & au_iu_iu5_i1_s1_dep_hit) | + ((fdec_frn_iu5_i1_s1_t == `axu1_t) & au_iu_iu5_i1_s1_dep_hit); + assign frn_fdis_iu6_i1_s2_v_d = fdec_frn_iu5_i1_s2_v & (send_instructions & fdec_frn_iu5_i1_vld); + assign frn_fdis_iu6_i1_s2_a_d = fdec_frn_iu5_i1_s2_a; + assign frn_fdis_iu6_i1_s2_p_d = ({`GPR_POOL_ENC{(fdec_frn_iu5_i1_s2_t == `gpr_t)}} & gpr_iu5_i1_src2_p) | + ({`GPR_POOL_ENC{(fdec_frn_iu5_i1_s2_t == `cr_t)}} & {{`GPR_POOL_ENC-`CR_POOL_ENC{1'b0}}, cr_iu5_i1_src2_p}) | + ({`GPR_POOL_ENC{(fdec_frn_iu5_i1_s2_t == `lr_t)}} & {{`GPR_POOL_ENC-`LR_POOL_ENC{1'b0}}, lr_iu5_i1_src2_p}) | + ({`GPR_POOL_ENC{(fdec_frn_iu5_i1_s2_t == `ctr_t)}} & {{`GPR_POOL_ENC-`CTR_POOL_ENC{1'b0}}, ctr_iu5_i1_src2_p}) | + ({`GPR_POOL_ENC{(fdec_frn_iu5_i1_s2_t == `xer_t)}} & {{`GPR_POOL_ENC-`XER_POOL_ENC{1'b0}}, xer_iu5_i1_src2_p}) | + ({`GPR_POOL_ENC{(fdec_frn_iu5_i1_s2_t == `axu0_t)}} & au_iu_iu5_i1_s2_p) | + ({`GPR_POOL_ENC{(fdec_frn_iu5_i1_s2_t == `axu1_t)}} & au_iu_iu5_i1_s2_p); + assign frn_fdis_iu6_i1_s2_itag_d = ({`ITAG_SIZE_ENC{(fdec_frn_iu5_i1_s2_t == `gpr_t)}} & gpr_iu5_i1_src2_itag) | + ({`ITAG_SIZE_ENC{(fdec_frn_iu5_i1_s2_t == `cr_t)}} & cr_iu5_i1_src2_itag) | + ({`ITAG_SIZE_ENC{(fdec_frn_iu5_i1_s2_t == `lr_t)}} & lr_iu5_i1_src2_itag) | + ({`ITAG_SIZE_ENC{(fdec_frn_iu5_i1_s2_t == `ctr_t)}} & ctr_iu5_i1_src2_itag) | + ({`ITAG_SIZE_ENC{(fdec_frn_iu5_i1_s2_t == `xer_t)}} & xer_iu5_i1_src2_itag) | + ({`ITAG_SIZE_ENC{(fdec_frn_iu5_i1_s2_t == `axu0_t)}} & au_iu_iu5_i1_s2_itag) | + ({`ITAG_SIZE_ENC{(fdec_frn_iu5_i1_s2_t == `axu1_t)}} & au_iu_iu5_i1_s2_itag); + assign frn_fdis_iu6_i1_s2_t_d = fdec_frn_iu5_i1_s2_t; + assign frn_fdis_iu6_i1_s2_dep_hit_d = ((fdec_frn_iu5_i1_s2_t == `gpr_t) & gpr_s2_dep_hit) | + ((fdec_frn_iu5_i1_s2_t == `cr_t) & cr_s2_dep_hit) | + ((fdec_frn_iu5_i1_s2_t == `lr_t) & lr_s2_dep_hit) | + ((fdec_frn_iu5_i1_s2_t == `ctr_t) & ctr_s2_dep_hit) | + ((fdec_frn_iu5_i1_s2_t == `xer_t) & xer_s2_dep_hit) | + ((fdec_frn_iu5_i1_s2_t == `axu0_t) & au_iu_iu5_i1_s2_dep_hit) | + ((fdec_frn_iu5_i1_s2_t == `axu1_t) & au_iu_iu5_i1_s2_dep_hit); + assign frn_fdis_iu6_i1_s3_v_d = fdec_frn_iu5_i1_s3_v & (send_instructions & fdec_frn_iu5_i1_vld); + assign frn_fdis_iu6_i1_s3_a_d = fdec_frn_iu5_i1_s3_a; + assign frn_fdis_iu6_i1_s3_p_d = ({`GPR_POOL_ENC{(fdec_frn_iu5_i1_s3_t == `gpr_t)}} & gpr_iu5_i1_src3_p) | + ({`GPR_POOL_ENC{(fdec_frn_iu5_i1_s3_t == `cr_t)}} & {{`GPR_POOL_ENC-`CR_POOL_ENC{1'b0}}, cr_iu5_i1_src3_p}) | + ({`GPR_POOL_ENC{(fdec_frn_iu5_i1_s3_t == `lr_t)}} & {{`GPR_POOL_ENC-`LR_POOL_ENC{1'b0}}, lr_iu5_i1_src3_p}) | + ({`GPR_POOL_ENC{(fdec_frn_iu5_i1_s3_t == `ctr_t)}} & {{`GPR_POOL_ENC-`CTR_POOL_ENC{1'b0}}, ctr_iu5_i1_src3_p}) | + ({`GPR_POOL_ENC{(fdec_frn_iu5_i1_s3_t == `xer_t)}} & {{`GPR_POOL_ENC-`XER_POOL_ENC{1'b0}}, xer_iu5_i1_src3_p}) | + ({`GPR_POOL_ENC{(fdec_frn_iu5_i1_s3_t == `axu0_t)}} & au_iu_iu5_i1_s3_p) | + ({`GPR_POOL_ENC{(fdec_frn_iu5_i1_s3_t == `axu1_t)}} & au_iu_iu5_i1_s3_p); + assign frn_fdis_iu6_i1_s3_itag_d = ({`ITAG_SIZE_ENC{(fdec_frn_iu5_i1_s3_t == `gpr_t)}} & gpr_iu5_i1_src3_itag) | + ({`ITAG_SIZE_ENC{(fdec_frn_iu5_i1_s3_t == `cr_t)}} & cr_iu5_i1_src3_itag) | + ({`ITAG_SIZE_ENC{(fdec_frn_iu5_i1_s3_t == `lr_t)}} & lr_iu5_i1_src3_itag) | + ({`ITAG_SIZE_ENC{(fdec_frn_iu5_i1_s3_t == `ctr_t)}} & ctr_iu5_i1_src3_itag) | + ({`ITAG_SIZE_ENC{(fdec_frn_iu5_i1_s3_t == `xer_t)}} & xer_iu5_i1_src3_itag) | + ({`ITAG_SIZE_ENC{(fdec_frn_iu5_i1_s3_t == `axu0_t)}} & au_iu_iu5_i1_s3_itag) | + ({`ITAG_SIZE_ENC{(fdec_frn_iu5_i1_s3_t == `axu1_t)}} & au_iu_iu5_i1_s3_itag); + assign frn_fdis_iu6_i1_s3_t_d = fdec_frn_iu5_i1_s3_t; + assign frn_fdis_iu6_i1_s3_dep_hit_d = ((fdec_frn_iu5_i1_s3_t == `gpr_t) & gpr_s3_dep_hit) | + ((fdec_frn_iu5_i1_s3_t == `cr_t) & cr_s3_dep_hit) | + ((fdec_frn_iu5_i1_s3_t == `lr_t) & lr_s3_dep_hit) | + ((fdec_frn_iu5_i1_s3_t == `ctr_t) & ctr_s3_dep_hit) | + ((fdec_frn_iu5_i1_s3_t == `xer_t) & xer_s3_dep_hit) | + ((fdec_frn_iu5_i1_s3_t == `axu0_t) & au_iu_iu5_i1_s3_dep_hit) | + ((fdec_frn_iu5_i1_s3_t == `axu1_t) & au_iu_iu5_i1_s3_dep_hit); + + //----------------------------------------------------------------------- + //-- GPR Renamer + //----------------------------------------------------------------------- + assign gpr_cp_i0_wr_v = cp_rn_i0_t1_v & (cp_rn_i0_t1_t == `gpr_t); + assign gpr_cp_i0_wr_a = cp_rn_i0_t1_a; + assign gpr_cp_i0_wr_p = cp_rn_i0_t1_p; + assign gpr_cp_i0_wr_itag = cp_rn_i0_itag; + assign gpr_cp_i1_wr_v = cp_rn_i1_t1_v & (cp_rn_i1_t1_t == `gpr_t); + assign gpr_cp_i1_wr_a = cp_rn_i1_t1_a; + assign gpr_cp_i1_wr_p = cp_rn_i1_t1_p; + assign gpr_cp_i1_wr_itag = cp_rn_i1_itag; + + assign gpr_spec_i0_wr_v = send_instructions & (~(gpr_send_cnt[0:1] == 2'b00)); + assign gpr_spec_i0_wr_v_fast = (~(gpr_send_cnt[0:1] == 2'b00)); + assign gpr_spec_i0_wr_a = ({`GPR_POOL_ENC{gpr_send_cnt[0]}} & fdec_frn_iu5_i0_t1_a) | + ({`GPR_POOL_ENC{~gpr_send_cnt[0] & gpr_send_cnt[1]}} & fdec_frn_iu5_i1_t1_a); + assign gpr_spec_i0_wr_p = next_gpr_0; + assign gpr_spec_i0_wr_itag = ({`ITAG_SIZE_ENC{gpr_send_cnt[0]}} & next_itag_0_l2) | + ({`ITAG_SIZE_ENC{~gpr_send_cnt[0] & gpr_send_cnt[1]}} & next_itag_1_l2); + assign gpr_spec_i1_wr_v = send_instructions & (gpr_send_cnt[0:1] == 2'b11); + assign gpr_spec_i1_wr_v_fast = (gpr_send_cnt[0:1] == 2'b11); + assign gpr_spec_i1_wr_a = fdec_frn_iu5_i1_t1_a; + assign gpr_spec_i1_wr_p = next_gpr_1; + assign gpr_spec_i1_wr_itag = next_itag_1_l2; + + assign gpr_s1_dep_hit = gpr_spec_i0_wr_v_fast & gpr_send_cnt[0] & (gpr_spec_i0_wr_a == fdec_frn_iu5_i1_s1_a); + assign gpr_s2_dep_hit = gpr_spec_i0_wr_v_fast & gpr_send_cnt[0] & (gpr_spec_i0_wr_a == fdec_frn_iu5_i1_s2_a); + assign gpr_s3_dep_hit = gpr_spec_i0_wr_v_fast & gpr_send_cnt[0] & (gpr_spec_i0_wr_a == fdec_frn_iu5_i1_s3_a); + + iuq_rn_map #(.ARCHITECTED_REGISTER_DEPTH((32 + `GPR_UCODE_POOL)), .REGISTER_RENAME_DEPTH(`GPR_POOL), .STORAGE_WIDTH(`GPR_POOL_ENC)) gpr_rn_map( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .pc_iu_func_sl_thold_0_b(pc_iu_func_sl_thold_0_b), + .pc_iu_sg_0(pc_iu_sg_0), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .func_scan_in(map_siv[0]), + .func_scan_out(map_sov[0]), + + .take_a(gpr_spec_i0_wr_v), + .take_b(gpr_spec_i1_wr_v), + .next_reg_a_val(next_gpr_0_v), + .next_reg_a(next_gpr_0), + .next_reg_b_val(next_gpr_1_v), + .next_reg_b(next_gpr_1), + + .src1_a(fdec_frn_iu5_i0_s1_a), + .src1_p(gpr_iu5_i0_src1_p), + .src1_itag(gpr_iu5_i0_src1_itag), + .src2_a(fdec_frn_iu5_i0_s2_a), + .src2_p(gpr_iu5_i0_src2_p), + .src2_itag(gpr_iu5_i0_src2_itag), + .src3_a(fdec_frn_iu5_i0_s3_a), + .src3_p(gpr_iu5_i0_src3_p), + .src3_itag(gpr_iu5_i0_src3_itag), + .src4_a(fdec_frn_iu5_i1_s1_a), + .src4_p(gpr_iu5_i1_src1_p), + .src4_itag(gpr_iu5_i1_src1_itag), + .src5_a(fdec_frn_iu5_i1_s2_a), + .src5_p(gpr_iu5_i1_src2_p), + .src5_itag(gpr_iu5_i1_src2_itag), + .src6_a(fdec_frn_iu5_i1_s3_a), + .src6_p(gpr_iu5_i1_src3_p), + .src6_itag(gpr_iu5_i1_src3_itag), + + .comp_0_wr_val(gpr_cp_i0_wr_v), + .comp_0_wr_arc(gpr_cp_i0_wr_a), + .comp_0_wr_rename(gpr_cp_i0_wr_p), + .comp_0_wr_itag(gpr_cp_i0_wr_itag), + + .comp_1_wr_val(gpr_cp_i1_wr_v), + .comp_1_wr_arc(gpr_cp_i1_wr_a), + .comp_1_wr_rename(gpr_cp_i1_wr_p), + .comp_1_wr_itag(gpr_cp_i1_wr_itag), + + .spec_0_wr_val(gpr_spec_i0_wr_v), + .spec_0_wr_val_fast(gpr_spec_i0_wr_v_fast), + .spec_0_wr_arc(gpr_spec_i0_wr_a), + .spec_0_wr_rename(gpr_spec_i0_wr_p), + .spec_0_wr_itag(gpr_spec_i0_wr_itag), + + .spec_1_dep_hit_s1(gpr_s1_dep_hit), + .spec_1_dep_hit_s2(gpr_s2_dep_hit), + .spec_1_dep_hit_s3(gpr_s3_dep_hit), + .spec_1_wr_val(gpr_spec_i1_wr_v), + .spec_1_wr_val_fast(gpr_spec_i1_wr_v_fast), + .spec_1_wr_arc(gpr_spec_i1_wr_a), + .spec_1_wr_rename(gpr_spec_i1_wr_p), + .spec_1_wr_itag(gpr_spec_i1_wr_itag), + + .flush_map(cp_flush_l2) + ); + + //--------------------------------------------------------------------- + // CR Renamer + //--------------------------------------------------------------------- + assign cr_cp_i0_wr_v = (cp_rn_i0_t1_v & (cp_rn_i0_t1_t == `cr_t)) | (cp_rn_i0_t3_v & (cp_rn_i0_t3_t == `cr_t)); + assign cr_cp_i0_wr_a = ({`CR_POOL_ENC{cp_rn_i0_t1_v & (cp_rn_i0_t1_t == `cr_t)}} & cp_rn_i0_t1_a[`GPR_POOL_ENC - `CR_POOL_ENC:`GPR_POOL_ENC - 1]) | + ({`CR_POOL_ENC{cp_rn_i0_t3_v & (cp_rn_i0_t3_t == `cr_t)}} & cp_rn_i0_t3_a[`GPR_POOL_ENC - `CR_POOL_ENC:`GPR_POOL_ENC - 1]); + assign cr_cp_i0_wr_p = ({`CR_POOL_ENC{cp_rn_i0_t1_v & (cp_rn_i0_t1_t == `cr_t)}} & cp_rn_i0_t1_p[`GPR_POOL_ENC - `CR_POOL_ENC:`GPR_POOL_ENC - 1]) | + ({`CR_POOL_ENC{cp_rn_i0_t3_v & (cp_rn_i0_t3_t == `cr_t)}} & cp_rn_i0_t3_p[`GPR_POOL_ENC - `CR_POOL_ENC:`GPR_POOL_ENC - 1]); + assign cr_cp_i0_wr_itag = cp_rn_i0_itag; + assign cr_cp_i1_wr_v = (cp_rn_i1_t1_v & (cp_rn_i1_t1_t == `cr_t)) | + (cp_rn_i1_t3_v & (cp_rn_i1_t3_t == `cr_t)); + assign cr_cp_i1_wr_a = ({`CR_POOL_ENC{cp_rn_i1_t1_v & (cp_rn_i1_t1_t == `cr_t)}} & cp_rn_i1_t1_a[`GPR_POOL_ENC - `CR_POOL_ENC:`GPR_POOL_ENC - 1]) | + ({`CR_POOL_ENC{cp_rn_i1_t3_v & (cp_rn_i1_t3_t == `cr_t)}} & cp_rn_i1_t3_a[`GPR_POOL_ENC - `CR_POOL_ENC:`GPR_POOL_ENC - 1]); + assign cr_cp_i1_wr_p = ({`CR_POOL_ENC{cp_rn_i1_t1_v & (cp_rn_i1_t1_t == `cr_t)}} & cp_rn_i1_t1_p[`GPR_POOL_ENC - `CR_POOL_ENC:`GPR_POOL_ENC - 1]) | + ({`CR_POOL_ENC{cp_rn_i1_t3_v & (cp_rn_i1_t3_t == `cr_t)}} & cp_rn_i1_t3_p[`GPR_POOL_ENC - `CR_POOL_ENC:`GPR_POOL_ENC - 1]); + assign cr_cp_i1_wr_itag = cp_rn_i1_itag; + + assign cr_spec_i0_wr_v = send_instructions & (~(cr_send_cnt[0:1] == 2'b00)); + assign cr_spec_i0_wr_v_fast = (~(cr_send_cnt[0:1] == 2'b00)); + assign cr_spec_i0_wr_a = ({`CR_POOL_ENC{cr_send_cnt[0]}} & (({`CR_POOL_ENC{cr_send_t1_cnt[0]}} & fdec_frn_iu5_i0_t1_a[`GPR_POOL_ENC - `CR_POOL_ENC:`GPR_POOL_ENC - 1]) | + ({`CR_POOL_ENC{cr_send_t3_cnt[0]}} & fdec_frn_iu5_i0_t3_a[`GPR_POOL_ENC - `CR_POOL_ENC:`GPR_POOL_ENC - 1]))) | + ({`CR_POOL_ENC{~cr_send_cnt[0] & cr_send_cnt[1]}} & (({`CR_POOL_ENC{cr_send_t1_cnt[1]}} & fdec_frn_iu5_i1_t1_a[`GPR_POOL_ENC - `CR_POOL_ENC:`GPR_POOL_ENC - 1]) | + ({`CR_POOL_ENC{cr_send_t3_cnt[1]}} & fdec_frn_iu5_i1_t3_a[`GPR_POOL_ENC - `CR_POOL_ENC:`GPR_POOL_ENC - 1]))); + assign cr_spec_i0_wr_p = next_cr_0; + assign cr_spec_i0_wr_itag = ({`ITAG_SIZE_ENC{cr_send_cnt[0]}} & (({`ITAG_SIZE_ENC{cr_send_t1_cnt[0]}} & next_itag_0_l2) | ({`ITAG_SIZE_ENC{cr_send_t3_cnt[0]}} & next_itag_0_l2))) | + ({`ITAG_SIZE_ENC{~cr_send_cnt[0] & cr_send_cnt[1]}} & (({`ITAG_SIZE_ENC{cr_send_t1_cnt[1]}} & next_itag_1_l2) | ({`ITAG_SIZE_ENC{cr_send_t3_cnt[1]}} & next_itag_1_l2))); + assign cr_spec_i1_wr_v = send_instructions & (cr_send_cnt[0:1] == 2'b11); + assign cr_spec_i1_wr_v_fast = (cr_send_cnt[0:1] == 2'b11); + assign cr_spec_i1_wr_a = fdec_frn_iu5_i1_t3_a[`GPR_POOL_ENC - `CR_POOL_ENC:`GPR_POOL_ENC - 1]; + assign cr_spec_i1_wr_p = next_cr_1; + assign cr_spec_i1_wr_itag = next_itag_1_l2; + + assign cr_s1_dep_hit = cr_spec_i0_wr_v_fast & cr_send_cnt[0] & (cr_spec_i0_wr_a == fdec_frn_iu5_i1_s1_a[`GPR_POOL_ENC - `CR_POOL_ENC:`GPR_POOL_ENC - 1]); + assign cr_s2_dep_hit = cr_spec_i0_wr_v_fast & cr_send_cnt[0] & (cr_spec_i0_wr_a == fdec_frn_iu5_i1_s2_a[`GPR_POOL_ENC - `CR_POOL_ENC:`GPR_POOL_ENC - 1]); + assign cr_s3_dep_hit = cr_spec_i0_wr_v_fast & cr_send_cnt[0] & (cr_spec_i0_wr_a == fdec_frn_iu5_i1_s3_a[`GPR_POOL_ENC - `CR_POOL_ENC:`GPR_POOL_ENC - 1]); + + iuq_rn_map #(.ARCHITECTED_REGISTER_DEPTH((8 + `CR_UCODE_POOL)), .REGISTER_RENAME_DEPTH(`CR_POOL), .STORAGE_WIDTH(`CR_POOL_ENC)) cr_rn_map( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .pc_iu_func_sl_thold_0_b(pc_iu_func_sl_thold_0_b), + .pc_iu_sg_0(pc_iu_sg_0), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .func_scan_in(map_siv[1]), + .func_scan_out(map_sov[1]), + + .take_a(cr_spec_i0_wr_v), + .take_b(cr_spec_i1_wr_v), + .next_reg_a_val(next_cr_0_v), + .next_reg_a(next_cr_0), + .next_reg_b_val(next_cr_1_v), + .next_reg_b(next_cr_1), + + .src1_a(fdec_frn_iu5_i0_s1_a[`GPR_POOL_ENC - `CR_POOL_ENC:`GPR_POOL_ENC - 1]), + .src1_p(cr_iu5_i0_src1_p), + .src1_itag(cr_iu5_i0_src1_itag), + .src2_a(fdec_frn_iu5_i0_s2_a[`GPR_POOL_ENC - `CR_POOL_ENC:`GPR_POOL_ENC - 1]), + .src2_p(cr_iu5_i0_src2_p), + .src2_itag(cr_iu5_i0_src2_itag), + .src3_a(fdec_frn_iu5_i0_s3_a[`GPR_POOL_ENC - `CR_POOL_ENC:`GPR_POOL_ENC - 1]), + .src3_p(cr_iu5_i0_src3_p), + .src3_itag(cr_iu5_i0_src3_itag), + .src4_a(fdec_frn_iu5_i1_s1_a[`GPR_POOL_ENC - `CR_POOL_ENC:`GPR_POOL_ENC - 1]), + .src4_p(cr_iu5_i1_src1_p), + .src4_itag(cr_iu5_i1_src1_itag), + .src5_a(fdec_frn_iu5_i1_s2_a[`GPR_POOL_ENC - `CR_POOL_ENC:`GPR_POOL_ENC - 1]), + .src5_p(cr_iu5_i1_src2_p), + .src5_itag(cr_iu5_i1_src2_itag), + .src6_a(fdec_frn_iu5_i1_s3_a[`GPR_POOL_ENC - `CR_POOL_ENC:`GPR_POOL_ENC - 1]), + .src6_p(cr_iu5_i1_src3_p), + .src6_itag(cr_iu5_i1_src3_itag), + + .comp_0_wr_val(cr_cp_i0_wr_v), + .comp_0_wr_arc(cr_cp_i0_wr_a), + .comp_0_wr_rename(cr_cp_i0_wr_p), + .comp_0_wr_itag(cr_cp_i0_wr_itag), + + .comp_1_wr_val(cr_cp_i1_wr_v), + .comp_1_wr_arc(cr_cp_i1_wr_a), + .comp_1_wr_rename(cr_cp_i1_wr_p), + .comp_1_wr_itag(cr_cp_i1_wr_itag), + + .spec_0_wr_val(cr_spec_i0_wr_v), + .spec_0_wr_val_fast(cr_spec_i0_wr_v_fast), + .spec_0_wr_arc(cr_spec_i0_wr_a), + .spec_0_wr_rename(cr_spec_i0_wr_p), + .spec_0_wr_itag(cr_spec_i0_wr_itag), + + .spec_1_dep_hit_s1(cr_s1_dep_hit), + .spec_1_dep_hit_s2(cr_s2_dep_hit), + .spec_1_dep_hit_s3(cr_s3_dep_hit), + .spec_1_wr_val(cr_spec_i1_wr_v), + .spec_1_wr_val_fast(cr_spec_i1_wr_v_fast), + .spec_1_wr_arc(cr_spec_i1_wr_a), + .spec_1_wr_rename(cr_spec_i1_wr_p), + .spec_1_wr_itag(cr_spec_i1_wr_itag), + + .flush_map(cp_flush_l2) + ); + + //--------------------------------------------------------------------- + // LR Renamer + //--------------------------------------------------------------------- + assign lr_cp_i0_wr_v = cp_rn_i0_t3_v & (cp_rn_i0_t3_t == `lr_t); + assign lr_cp_i0_wr_a = cp_rn_i0_t3_a[`GPR_POOL_ENC - `LR_POOL_ENC:`GPR_POOL_ENC - 1]; + assign lr_cp_i0_wr_p = cp_rn_i0_t3_p[`GPR_POOL_ENC - `LR_POOL_ENC:`GPR_POOL_ENC - 1]; + assign lr_cp_i0_wr_itag = cp_rn_i0_itag; + assign lr_cp_i1_wr_v = cp_rn_i1_t3_v & (cp_rn_i1_t3_t == `lr_t); + assign lr_cp_i1_wr_a = cp_rn_i1_t3_a[`GPR_POOL_ENC - `LR_POOL_ENC:`GPR_POOL_ENC - 1]; + assign lr_cp_i1_wr_p = cp_rn_i1_t3_p[`GPR_POOL_ENC - `LR_POOL_ENC:`GPR_POOL_ENC - 1]; + assign lr_cp_i1_wr_itag = cp_rn_i1_itag; + + assign lr_spec_i0_wr_v = send_instructions & (~(lr_send_cnt[0:1] == 2'b00)); + assign lr_spec_i0_wr_v_fast = (~(lr_send_cnt[0:1] == 2'b00)); + assign lr_spec_i0_wr_a = ({`LR_POOL_ENC{lr_send_cnt[0]}} & fdec_frn_iu5_i0_t3_a[`GPR_POOL_ENC - `LR_POOL_ENC:`GPR_POOL_ENC - 1]) | + ({`LR_POOL_ENC{~lr_send_cnt[0] & lr_send_cnt[1]}} & fdec_frn_iu5_i1_t3_a[`GPR_POOL_ENC - `LR_POOL_ENC:`GPR_POOL_ENC - 1]); + assign lr_spec_i0_wr_p = next_lr_0; + assign lr_spec_i0_wr_itag = ({`ITAG_SIZE_ENC{lr_send_cnt[0]}} & next_itag_0_l2) | + ({`ITAG_SIZE_ENC{~lr_send_cnt[0] & lr_send_cnt[1]}} & next_itag_1_l2); + assign lr_spec_i1_wr_v = send_instructions & (lr_send_cnt[0:1] == 2'b11); + assign lr_spec_i1_wr_v_fast = (lr_send_cnt[0:1] == 2'b11); + assign lr_spec_i1_wr_a = fdec_frn_iu5_i1_t3_a[`GPR_POOL_ENC - `LR_POOL_ENC:`GPR_POOL_ENC - 1]; + assign lr_spec_i1_wr_p = next_lr_1; + assign lr_spec_i1_wr_itag = next_itag_1_l2; + + assign lr_s1_dep_hit = lr_spec_i0_wr_v_fast & lr_send_cnt[0] & (lr_spec_i0_wr_a == fdec_frn_iu5_i1_s1_a[`GPR_POOL_ENC - `LR_POOL_ENC:`GPR_POOL_ENC - 1]); + assign lr_s2_dep_hit = lr_spec_i0_wr_v_fast & lr_send_cnt[0] & (lr_spec_i0_wr_a == fdec_frn_iu5_i1_s2_a[`GPR_POOL_ENC - `LR_POOL_ENC:`GPR_POOL_ENC - 1]); + assign lr_s3_dep_hit = lr_spec_i0_wr_v_fast & lr_send_cnt[0] & (lr_spec_i0_wr_a == fdec_frn_iu5_i1_s3_a[`GPR_POOL_ENC - `LR_POOL_ENC:`GPR_POOL_ENC - 1]); + + iuq_rn_map #(.ARCHITECTED_REGISTER_DEPTH((2 + `LR_UCODE_POOL)), .REGISTER_RENAME_DEPTH(`LR_POOL), .STORAGE_WIDTH(`LR_POOL_ENC)) lr_rn_map( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .pc_iu_func_sl_thold_0_b(pc_iu_func_sl_thold_0_b), + .pc_iu_sg_0(pc_iu_sg_0), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .func_scan_in(map_siv[2]), + .func_scan_out(map_sov[2]), + + .take_a(lr_spec_i0_wr_v), + .take_b(lr_spec_i1_wr_v), + .next_reg_a_val(next_lr_0_v), + .next_reg_a(next_lr_0), + .next_reg_b_val(next_lr_1_v), + .next_reg_b(next_lr_1), + + .src1_a(fdec_frn_iu5_i0_s1_a[`GPR_POOL_ENC - `LR_POOL_ENC:`GPR_POOL_ENC - 1]), + .src1_p(lr_iu5_i0_src1_p), + .src1_itag(lr_iu5_i0_src1_itag), + .src2_a(fdec_frn_iu5_i0_s2_a[`GPR_POOL_ENC - `LR_POOL_ENC:`GPR_POOL_ENC - 1]), + .src2_p(lr_iu5_i0_src2_p), + .src2_itag(lr_iu5_i0_src2_itag), + .src3_a(fdec_frn_iu5_i0_s3_a[`GPR_POOL_ENC - `LR_POOL_ENC:`GPR_POOL_ENC - 1]), + .src3_p(lr_iu5_i0_src3_p), + .src3_itag(lr_iu5_i0_src3_itag), + .src4_a(fdec_frn_iu5_i1_s1_a[`GPR_POOL_ENC - `LR_POOL_ENC:`GPR_POOL_ENC - 1]), + .src4_p(lr_iu5_i1_src1_p), + .src4_itag(lr_iu5_i1_src1_itag), + .src5_a(fdec_frn_iu5_i1_s2_a[`GPR_POOL_ENC - `LR_POOL_ENC:`GPR_POOL_ENC - 1]), + .src5_p(lr_iu5_i1_src2_p), + .src5_itag(lr_iu5_i1_src2_itag), + .src6_a(fdec_frn_iu5_i1_s3_a[`GPR_POOL_ENC - `LR_POOL_ENC:`GPR_POOL_ENC - 1]), + .src6_p(lr_iu5_i1_src3_p), + .src6_itag(lr_iu5_i1_src3_itag), + + .comp_0_wr_val(lr_cp_i0_wr_v), + .comp_0_wr_arc(lr_cp_i0_wr_a), + .comp_0_wr_rename(lr_cp_i0_wr_p), + .comp_0_wr_itag(lr_cp_i0_wr_itag), + + .comp_1_wr_val(lr_cp_i1_wr_v), + .comp_1_wr_arc(lr_cp_i1_wr_a), + .comp_1_wr_rename(lr_cp_i1_wr_p), + .comp_1_wr_itag(lr_cp_i1_wr_itag), + + .spec_0_wr_val(lr_spec_i0_wr_v), + .spec_0_wr_val_fast(lr_spec_i0_wr_v_fast), + .spec_0_wr_arc(lr_spec_i0_wr_a), + .spec_0_wr_rename(lr_spec_i0_wr_p), + .spec_0_wr_itag(lr_spec_i0_wr_itag), + + .spec_1_dep_hit_s1(lr_s1_dep_hit), + .spec_1_dep_hit_s2(lr_s2_dep_hit), + .spec_1_dep_hit_s3(lr_s3_dep_hit), + .spec_1_wr_val(lr_spec_i1_wr_v), + .spec_1_wr_val_fast(lr_spec_i1_wr_v_fast), + .spec_1_wr_arc(lr_spec_i1_wr_a), + .spec_1_wr_rename(lr_spec_i1_wr_p), + .spec_1_wr_itag(lr_spec_i1_wr_itag), + + .flush_map(cp_flush_l2) + ); + + //--------------------------------------------------------------------- + // CTR Renamer + //--------------------------------------------------------------------- + assign ctr_cp_i0_wr_v = cp_rn_i0_t2_v & (cp_rn_i0_t2_t == `ctr_t); + assign ctr_cp_i0_wr_a = cp_rn_i0_t2_a[`GPR_POOL_ENC - `CTR_POOL_ENC:`GPR_POOL_ENC - 1]; + assign ctr_cp_i0_wr_p = cp_rn_i0_t2_p[`GPR_POOL_ENC - `CTR_POOL_ENC:`GPR_POOL_ENC - 1]; + assign ctr_cp_i0_wr_itag = cp_rn_i0_itag; + assign ctr_cp_i1_wr_v = cp_rn_i1_t2_v & (cp_rn_i1_t2_t == `ctr_t); + assign ctr_cp_i1_wr_a = cp_rn_i1_t2_a[`GPR_POOL_ENC - `CTR_POOL_ENC:`GPR_POOL_ENC - 1]; + assign ctr_cp_i1_wr_p = cp_rn_i1_t2_p[`GPR_POOL_ENC - `CTR_POOL_ENC:`GPR_POOL_ENC - 1]; + assign ctr_cp_i1_wr_itag = cp_rn_i1_itag; + + assign ctr_spec_i0_wr_v = send_instructions & (~(ctr_send_cnt[0:1] == 2'b00)); + assign ctr_spec_i0_wr_v_fast = (~(ctr_send_cnt[0:1] == 2'b00)); + assign ctr_spec_i0_wr_a = ({`CTR_POOL_ENC{ctr_send_cnt[0]}} & fdec_frn_iu5_i0_t2_a[`GPR_POOL_ENC - `CTR_POOL_ENC:`GPR_POOL_ENC - 1]) | + ({`CTR_POOL_ENC{~ctr_send_cnt[0] & ctr_send_cnt[1]}} & fdec_frn_iu5_i1_t2_a[`GPR_POOL_ENC - `CTR_POOL_ENC:`GPR_POOL_ENC - 1]); + assign ctr_spec_i0_wr_p = next_ctr_0; + assign ctr_spec_i0_wr_itag = ({`ITAG_SIZE_ENC{ctr_send_cnt[0]}} & next_itag_0_l2) | + ({`ITAG_SIZE_ENC{~ctr_send_cnt[0] & ctr_send_cnt[1]}} & next_itag_1_l2); + assign ctr_spec_i1_wr_v = send_instructions & (ctr_send_cnt[0:1] == 2'b11); + assign ctr_spec_i1_wr_v_fast = (ctr_send_cnt[0:1] == 2'b11); + assign ctr_spec_i1_wr_a = fdec_frn_iu5_i1_t2_a[`GPR_POOL_ENC - `CTR_POOL_ENC:`GPR_POOL_ENC - 1]; + assign ctr_spec_i1_wr_p = next_ctr_1; + assign ctr_spec_i1_wr_itag = next_itag_1_l2; + + assign ctr_s1_dep_hit = ctr_spec_i0_wr_v_fast & ctr_send_cnt[0] & (ctr_spec_i0_wr_a == fdec_frn_iu5_i1_s1_a[`GPR_POOL_ENC - `CTR_POOL_ENC:`GPR_POOL_ENC - 1]); + assign ctr_s2_dep_hit = ctr_spec_i0_wr_v_fast & ctr_send_cnt[0] & (ctr_spec_i0_wr_a == fdec_frn_iu5_i1_s2_a[`GPR_POOL_ENC - `CTR_POOL_ENC:`GPR_POOL_ENC - 1]); + assign ctr_s3_dep_hit = ctr_spec_i0_wr_v_fast & ctr_send_cnt[0] & (ctr_spec_i0_wr_a == fdec_frn_iu5_i1_s3_a[`GPR_POOL_ENC - `CTR_POOL_ENC:`GPR_POOL_ENC - 1]); + + iuq_rn_map #(.ARCHITECTED_REGISTER_DEPTH((1 + `CTR_UCODE_POOL)), .REGISTER_RENAME_DEPTH(`CTR_POOL), .STORAGE_WIDTH(`CTR_POOL_ENC)) ctr_rn_map( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .pc_iu_func_sl_thold_0_b(pc_iu_func_sl_thold_0_b), + .pc_iu_sg_0(pc_iu_sg_0), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .func_scan_in(map_siv[3]), + .func_scan_out(map_sov[3]), + + .take_a(ctr_spec_i0_wr_v), + .take_b(ctr_spec_i1_wr_v), + .next_reg_a_val(next_ctr_0_v), + .next_reg_a(next_ctr_0), + .next_reg_b_val(next_ctr_1_v), + .next_reg_b(next_ctr_1), + + .src1_a(fdec_frn_iu5_i0_s1_a[`GPR_POOL_ENC - `CTR_POOL_ENC:`GPR_POOL_ENC - 1]), + .src1_p(ctr_iu5_i0_src1_p), + .src1_itag(ctr_iu5_i0_src1_itag), + .src2_a(fdec_frn_iu5_i0_s2_a[`GPR_POOL_ENC - `CTR_POOL_ENC:`GPR_POOL_ENC - 1]), + .src2_p(ctr_iu5_i0_src2_p), + .src2_itag(ctr_iu5_i0_src2_itag), + .src3_a(fdec_frn_iu5_i0_s3_a[`GPR_POOL_ENC - `CTR_POOL_ENC:`GPR_POOL_ENC - 1]), + .src3_p(ctr_iu5_i0_src3_p), + .src3_itag(ctr_iu5_i0_src3_itag), + .src4_a(fdec_frn_iu5_i1_s1_a[`GPR_POOL_ENC - `CTR_POOL_ENC:`GPR_POOL_ENC - 1]), + .src4_p(ctr_iu5_i1_src1_p), + .src4_itag(ctr_iu5_i1_src1_itag), + .src5_a(fdec_frn_iu5_i1_s2_a[`GPR_POOL_ENC - `CTR_POOL_ENC:`GPR_POOL_ENC - 1]), + .src5_p(ctr_iu5_i1_src2_p), + .src5_itag(ctr_iu5_i1_src2_itag), + .src6_a(fdec_frn_iu5_i1_s3_a[`GPR_POOL_ENC - `CTR_POOL_ENC:`GPR_POOL_ENC - 1]), + .src6_p(ctr_iu5_i1_src3_p), + .src6_itag(ctr_iu5_i1_src3_itag), + + .comp_0_wr_val(ctr_cp_i0_wr_v), + .comp_0_wr_arc(ctr_cp_i0_wr_a), + .comp_0_wr_rename(ctr_cp_i0_wr_p), + .comp_0_wr_itag(ctr_cp_i0_wr_itag), + + .comp_1_wr_val(ctr_cp_i1_wr_v), + .comp_1_wr_arc(ctr_cp_i1_wr_a), + .comp_1_wr_rename(ctr_cp_i1_wr_p), + .comp_1_wr_itag(ctr_cp_i1_wr_itag), + + .spec_0_wr_val(ctr_spec_i0_wr_v), + .spec_0_wr_val_fast(ctr_spec_i0_wr_v_fast), + .spec_0_wr_arc(ctr_spec_i0_wr_a), + .spec_0_wr_rename(ctr_spec_i0_wr_p), + .spec_0_wr_itag(ctr_spec_i0_wr_itag), + + .spec_1_dep_hit_s1(ctr_s1_dep_hit), + .spec_1_dep_hit_s2(ctr_s2_dep_hit), + .spec_1_dep_hit_s3(ctr_s3_dep_hit), + .spec_1_wr_val(ctr_spec_i1_wr_v), + .spec_1_wr_val_fast(ctr_spec_i1_wr_v_fast), + .spec_1_wr_arc(ctr_spec_i1_wr_a), + .spec_1_wr_rename(ctr_spec_i1_wr_p), + .spec_1_wr_itag(ctr_spec_i1_wr_itag), + + .flush_map(cp_flush_l2) + ); + + //--------------------------------------------------------------------- + // XER Renamer + //--------------------------------------------------------------------- + assign xer_cp_i0_wr_v = cp_rn_i0_t2_v & (cp_rn_i0_t2_t == `xer_t); + assign xer_cp_i0_wr_a = cp_rn_i0_t2_a[`GPR_POOL_ENC - `XER_POOL_ENC:`GPR_POOL_ENC - 1]; + assign xer_cp_i0_wr_p = cp_rn_i0_t2_p[`GPR_POOL_ENC - `XER_POOL_ENC:`GPR_POOL_ENC - 1]; + assign xer_cp_i0_wr_itag = cp_rn_i0_itag; + assign xer_cp_i1_wr_v = cp_rn_i1_t2_v & (cp_rn_i1_t2_t == `xer_t); + assign xer_cp_i1_wr_a = cp_rn_i1_t2_a[`GPR_POOL_ENC - `XER_POOL_ENC:`GPR_POOL_ENC - 1]; + assign xer_cp_i1_wr_p = cp_rn_i1_t2_p[`GPR_POOL_ENC - `XER_POOL_ENC:`GPR_POOL_ENC - 1]; + assign xer_cp_i1_wr_itag = cp_rn_i1_itag; + + assign xer_spec_i0_wr_v = send_instructions & (~(xer_send_cnt[0:1] == 2'b00)); + assign xer_spec_i0_wr_v_fast = (~(xer_send_cnt[0:1] == 2'b00)); + assign xer_spec_i0_wr_a = ({`XER_POOL_ENC{xer_send_cnt[0]}} & fdec_frn_iu5_i0_t2_a[`GPR_POOL_ENC - `XER_POOL_ENC:`GPR_POOL_ENC - 1]) | + ({`XER_POOL_ENC{~xer_send_cnt[0] & xer_send_cnt[1]}} & fdec_frn_iu5_i1_t2_a[`GPR_POOL_ENC - `XER_POOL_ENC:`GPR_POOL_ENC - 1]); + assign xer_spec_i0_wr_p = next_xer_0; + assign xer_spec_i0_wr_itag = ({`ITAG_SIZE_ENC{xer_send_cnt[0]}} & next_itag_0_l2) | + ({`ITAG_SIZE_ENC{~xer_send_cnt[0] & xer_send_cnt[1]}} & next_itag_1_l2); + assign xer_spec_i1_wr_v = send_instructions & (xer_send_cnt[0:1] == 2'b11); + assign xer_spec_i1_wr_v_fast = (xer_send_cnt[0:1] == 2'b11); + assign xer_spec_i1_wr_a = fdec_frn_iu5_i1_t2_a[`GPR_POOL_ENC - `XER_POOL_ENC:`GPR_POOL_ENC - 1]; + assign xer_spec_i1_wr_p = next_xer_1; + assign xer_spec_i1_wr_itag = next_itag_1_l2; + + assign xer_s1_dep_hit = xer_spec_i0_wr_v_fast & xer_send_cnt[0] & (xer_spec_i0_wr_a == fdec_frn_iu5_i1_s1_a[`GPR_POOL_ENC - `XER_POOL_ENC:`GPR_POOL_ENC - 1]); + assign xer_s2_dep_hit = xer_spec_i0_wr_v_fast & xer_send_cnt[0] & (xer_spec_i0_wr_a == fdec_frn_iu5_i1_s2_a[`GPR_POOL_ENC - `XER_POOL_ENC:`GPR_POOL_ENC - 1]); + assign xer_s3_dep_hit = xer_spec_i0_wr_v_fast & xer_send_cnt[0] & (xer_spec_i0_wr_a == fdec_frn_iu5_i1_s3_a[`GPR_POOL_ENC - `XER_POOL_ENC:`GPR_POOL_ENC - 1]); + + iuq_rn_map #(.ARCHITECTED_REGISTER_DEPTH((1 + `XER_UCODE_POOL)), .REGISTER_RENAME_DEPTH(`XER_POOL), .STORAGE_WIDTH(`XER_POOL_ENC)) xer_rn_map( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .pc_iu_func_sl_thold_0_b(pc_iu_func_sl_thold_0_b), + .pc_iu_sg_0(pc_iu_sg_0), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .func_scan_in(map_siv[4]), + .func_scan_out(map_sov[4]), + + .take_a(xer_spec_i0_wr_v), + .take_b(xer_spec_i1_wr_v), + .next_reg_a_val(next_xer_0_v), + .next_reg_a(next_xer_0), + .next_reg_b_val(next_xer_1_v), + .next_reg_b(next_xer_1), + + .src1_a(fdec_frn_iu5_i0_s1_a[`GPR_POOL_ENC - `XER_POOL_ENC:`GPR_POOL_ENC - 1]), + .src1_p(xer_iu5_i0_src1_p), + .src1_itag(xer_iu5_i0_src1_itag), + .src2_a(fdec_frn_iu5_i0_s2_a[`GPR_POOL_ENC - `XER_POOL_ENC:`GPR_POOL_ENC - 1]), + .src2_p(xer_iu5_i0_src2_p), + .src2_itag(xer_iu5_i0_src2_itag), + .src3_a(fdec_frn_iu5_i0_s3_a[`GPR_POOL_ENC - `XER_POOL_ENC:`GPR_POOL_ENC - 1]), + .src3_p(xer_iu5_i0_src3_p), + .src3_itag(xer_iu5_i0_src3_itag), + .src4_a(fdec_frn_iu5_i1_s1_a[`GPR_POOL_ENC - `XER_POOL_ENC:`GPR_POOL_ENC - 1]), + .src4_p(xer_iu5_i1_src1_p), + .src4_itag(xer_iu5_i1_src1_itag), + .src5_a(fdec_frn_iu5_i1_s2_a[`GPR_POOL_ENC - `XER_POOL_ENC:`GPR_POOL_ENC - 1]), + .src5_p(xer_iu5_i1_src2_p), + .src5_itag(xer_iu5_i1_src2_itag), + .src6_a(fdec_frn_iu5_i1_s3_a[`GPR_POOL_ENC - `XER_POOL_ENC:`GPR_POOL_ENC - 1]), + .src6_p(xer_iu5_i1_src3_p), + .src6_itag(xer_iu5_i1_src3_itag), + + .comp_0_wr_val(xer_cp_i0_wr_v), + .comp_0_wr_arc(xer_cp_i0_wr_a), + .comp_0_wr_rename(xer_cp_i0_wr_p), + .comp_0_wr_itag(xer_cp_i0_wr_itag), + + .comp_1_wr_val(xer_cp_i1_wr_v), + .comp_1_wr_arc(xer_cp_i1_wr_a), + .comp_1_wr_rename(xer_cp_i1_wr_p), + .comp_1_wr_itag(xer_cp_i1_wr_itag), + + .spec_0_wr_val(xer_spec_i0_wr_v), + .spec_0_wr_val_fast(xer_spec_i0_wr_v_fast), + .spec_0_wr_arc(xer_spec_i0_wr_a), + .spec_0_wr_rename(xer_spec_i0_wr_p), + .spec_0_wr_itag(xer_spec_i0_wr_itag), + + .spec_1_dep_hit_s1(xer_s1_dep_hit), + .spec_1_dep_hit_s2(xer_s2_dep_hit), + .spec_1_dep_hit_s3(xer_s3_dep_hit), + .spec_1_wr_val(xer_spec_i1_wr_v), + .spec_1_wr_val_fast(xer_spec_i1_wr_v_fast), + .spec_1_wr_arc(xer_spec_i1_wr_a), + .spec_1_wr_rename(xer_spec_i1_wr_p), + .spec_1_wr_itag(xer_spec_i1_wr_itag), + + .flush_map(cp_flush_l2) + ); + + + //--------------------------------------------------------------------- + // Perfmon + //--------------------------------------------------------------------- + assign perf_iu5_stall_d = (~(cpl_credit_ok & gpr_send_ok & cr_send_ok & lr_send_ok & ctr_send_ok & xer_send_ok & cp_empty_ok)) | br_iu_hold_l2 | au_iu_iu5_stall | (fdec_frn_iu5_i0_vld & fdis_frn_iu6_stall_dly); + assign perf_iu5_cpl_credit_stall_d = fdec_frn_iu5_i0_vld & ~cpl_credit_ok; + assign perf_iu5_gpr_credit_stall_d = fdec_frn_iu5_i0_vld & ~gpr_send_ok; + assign perf_iu5_cr_credit_stall_d = fdec_frn_iu5_i0_vld & ~cr_send_ok; + assign perf_iu5_lr_credit_stall_d = fdec_frn_iu5_i0_vld & ~lr_send_ok; + assign perf_iu5_ctr_credit_stall_d = fdec_frn_iu5_i0_vld & ~ctr_send_ok; + assign perf_iu5_xer_credit_stall_d = fdec_frn_iu5_i0_vld & ~xer_send_ok; + assign perf_iu5_br_hold_stall_d = fdec_frn_iu5_i0_vld & br_iu_hold_l2; + assign perf_iu5_axu_hold_stall_d = fdec_frn_iu5_i0_vld & au_iu_iu5_stall; + + assign perf_iu5_stall = perf_iu5_stall_l2; + assign perf_iu5_cpl_credit_stall = perf_iu5_cpl_credit_stall_l2; + assign perf_iu5_gpr_credit_stall = perf_iu5_gpr_credit_stall_l2; + assign perf_iu5_cr_credit_stall = perf_iu5_cr_credit_stall_l2; + assign perf_iu5_lr_credit_stall = perf_iu5_lr_credit_stall_l2; + assign perf_iu5_ctr_credit_stall = perf_iu5_ctr_credit_stall_l2; + assign perf_iu5_xer_credit_stall = perf_iu5_xer_credit_stall_l2; + assign perf_iu5_br_hold_stall = perf_iu5_br_hold_stall_l2; + assign perf_iu5_axu_hold_stall = perf_iu5_axu_hold_stall_l2; + + + //--------------------------------------------------------------------- + // Latch definitions + //--------------------------------------------------------------------- + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(`CPL_Q_DEPTH)) next_itag_0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[next_itag_0_offset:next_itag_0_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[next_itag_0_offset:next_itag_0_offset + `ITAG_SIZE_ENC - 1]), + .din(next_itag_0_d), + .dout(next_itag_0_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(`CPL_Q_DEPTH)) next_itag_1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[next_itag_1_offset:next_itag_1_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[next_itag_1_offset:next_itag_1_offset + `ITAG_SIZE_ENC - 1]), + .din(next_itag_1_d), + .dout(next_itag_1_l2) + ); + + + tri_rlmreg_p #(.WIDTH((`CPL_Q_DEPTH_ENC+1)), .INIT(`CPL_Q_DEPTH)) cp_high_credit_cnt_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[cp_high_credit_cnt_offset:cp_high_credit_cnt_offset + (`CPL_Q_DEPTH_ENC+1) - 1]), + .scout(sov[cp_high_credit_cnt_offset:cp_high_credit_cnt_offset + (`CPL_Q_DEPTH_ENC+1) - 1]), + .din(cp_high_credit_cnt_d), + .dout(cp_high_credit_cnt_l2) + ); + + + tri_rlmreg_p #(.WIDTH((`CPL_Q_DEPTH_ENC+1)), .INIT(`CPL_Q_DEPTH/2)) cp_med_credit_cnt_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[cp_med_credit_cnt_offset:cp_med_credit_cnt_offset + (`CPL_Q_DEPTH_ENC+1) - 1]), + .scout(sov[cp_med_credit_cnt_offset:cp_med_credit_cnt_offset + (`CPL_Q_DEPTH_ENC+1) - 1]), + .din(cp_med_credit_cnt_d), + .dout(cp_med_credit_cnt_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`UCODE_ENTRIES_ENC), .INIT(0)) ucode_cnt_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[ucode_cnt_offset:ucode_cnt_offset + `UCODE_ENTRIES_ENC - 1]), + .scout(sov[ucode_cnt_offset:ucode_cnt_offset + `UCODE_ENTRIES_ENC - 1]), + .din(ucode_cnt_d), + .dout(ucode_cnt_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`UCODE_ENTRIES_ENC), .INIT(0)) ucode_cnt_save_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cp_rn_uc_credit_free), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[ucode_cnt_save_offset:ucode_cnt_save_offset + `UCODE_ENTRIES_ENC - 1]), + .scout(sov[ucode_cnt_save_offset:ucode_cnt_save_offset + `UCODE_ENTRIES_ENC - 1]), + .din(ucode_cnt_save_d), + .dout(ucode_cnt_save_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) cp_flush_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[cp_flush_offset]), + .scout(sov[cp_flush_offset]), + .din(cp_flush_d), + .dout(cp_flush_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) cp_flush_into_uc_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[cp_flush_into_uc_offset]), + .scout(sov[cp_flush_into_uc_offset]), + .din(cp_flush_into_uc_d), + .dout(cp_flush_into_uc_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) br_iu_hold_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[br_iu_hold_offset]), + .scout(sov[br_iu_hold_offset]), + .din(br_iu_hold_d), + .dout(br_iu_hold_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) hold_instructions_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[hold_instructions_offset]), + .scout(sov[hold_instructions_offset]), + .din(hold_instructions_d), + .dout(hold_instructions_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) cp_rn_empty_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[cp_rn_empty_offset]), + .scout(sov[cp_rn_empty_offset]), + .din(cp_rn_empty), + .dout(cp_rn_empty_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) high_pri_mask_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[high_pri_mask_offset]), + .scout(sov[high_pri_mask_offset]), + .din(spr_high_pri_mask), + .dout(high_pri_mask_l2) + ); + + tri_rlmreg_p #(.WIDTH(19), .INIT(0)) fdis_frn_iu6_stall_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[fdis_frn_iu6_stall_offset:fdis_frn_iu6_stall_offset + 19 - 1]), + .scout(sov[fdis_frn_iu6_stall_offset:fdis_frn_iu6_stall_offset + 19 - 1]), + .din(fdis_frn_iu6_stall_d), + .dout(fdis_frn_iu6_stall_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_vld_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i0_vld_offset]), + .scout(sov[frn_fdis_iu6_i0_vld_offset]), + .din(frn_fdis_iu6_i0_vld_d), + .dout(frn_fdis_iu6_i0_vld_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) frn_fdis_iu6_i0_itag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i0_itag_offset:frn_fdis_iu6_i0_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[frn_fdis_iu6_i0_itag_offset:frn_fdis_iu6_i0_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(frn_fdis_iu6_i0_itag_d), + .dout(frn_fdis_iu6_i0_itag_l2) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) frn_fdis_iu6_i0_ucode_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i0_ucode_offset:frn_fdis_iu6_i0_ucode_offset + 3 - 1]), + .scout(sov[frn_fdis_iu6_i0_ucode_offset:frn_fdis_iu6_i0_ucode_offset + 3 - 1]), + .din(frn_fdis_iu6_i0_ucode_d), + .dout(frn_fdis_iu6_i0_ucode_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`UCODE_ENTRIES_ENC), .INIT(0)) frn_fdis_iu6_i0_ucode_cnt_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i0_ucode_cnt_offset:frn_fdis_iu6_i0_ucode_cnt_offset + `UCODE_ENTRIES_ENC - 1]), + .scout(sov[frn_fdis_iu6_i0_ucode_cnt_offset:frn_fdis_iu6_i0_ucode_cnt_offset + `UCODE_ENTRIES_ENC - 1]), + .din(frn_fdis_iu6_i0_ucode_cnt_d), + .dout(frn_fdis_iu6_i0_ucode_cnt_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_2ucode_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i0_2ucode_offset]), + .scout(sov[frn_fdis_iu6_i0_2ucode_offset]), + .din(frn_fdis_iu6_i0_2ucode_d), + .dout(frn_fdis_iu6_i0_2ucode_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_fuse_nop_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i0_fuse_nop_offset]), + .scout(sov[frn_fdis_iu6_i0_fuse_nop_offset]), + .din(frn_fdis_iu6_i0_fuse_nop_d), + .dout(frn_fdis_iu6_i0_fuse_nop_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_rte_lq_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i0_rte_lq_offset]), + .scout(sov[frn_fdis_iu6_i0_rte_lq_offset]), + .din(frn_fdis_iu6_i0_rte_lq_d), + .dout(frn_fdis_iu6_i0_rte_lq_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_rte_sq_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i0_rte_sq_offset]), + .scout(sov[frn_fdis_iu6_i0_rte_sq_offset]), + .din(frn_fdis_iu6_i0_rte_sq_d), + .dout(frn_fdis_iu6_i0_rte_sq_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_rte_fx0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i0_rte_fx0_offset]), + .scout(sov[frn_fdis_iu6_i0_rte_fx0_offset]), + .din(frn_fdis_iu6_i0_rte_fx0_d), + .dout(frn_fdis_iu6_i0_rte_fx0_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_rte_fx1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i0_rte_fx1_offset]), + .scout(sov[frn_fdis_iu6_i0_rte_fx1_offset]), + .din(frn_fdis_iu6_i0_rte_fx1_d), + .dout(frn_fdis_iu6_i0_rte_fx1_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_rte_axu0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i0_rte_axu0_offset]), + .scout(sov[frn_fdis_iu6_i0_rte_axu0_offset]), + .din(frn_fdis_iu6_i0_rte_axu0_d), + .dout(frn_fdis_iu6_i0_rte_axu0_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_rte_axu1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i0_rte_axu1_offset]), + .scout(sov[frn_fdis_iu6_i0_rte_axu1_offset]), + .din(frn_fdis_iu6_i0_rte_axu1_d), + .dout(frn_fdis_iu6_i0_rte_axu1_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_valop_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i0_valop_offset]), + .scout(sov[frn_fdis_iu6_i0_valop_offset]), + .din(frn_fdis_iu6_i0_valop_d), + .dout(frn_fdis_iu6_i0_valop_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_ord_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i0_ord_offset]), + .scout(sov[frn_fdis_iu6_i0_ord_offset]), + .din(frn_fdis_iu6_i0_ord_d), + .dout(frn_fdis_iu6_i0_ord_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_cord_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i0_cord_offset]), + .scout(sov[frn_fdis_iu6_i0_cord_offset]), + .din(frn_fdis_iu6_i0_cord_d), + .dout(frn_fdis_iu6_i0_cord_l2) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) frn_fdis_iu6_i0_error_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i0_error_offset:frn_fdis_iu6_i0_error_offset + 3 - 1]), + .scout(sov[frn_fdis_iu6_i0_error_offset:frn_fdis_iu6_i0_error_offset + 3 - 1]), + .din(frn_fdis_iu6_i0_error_d), + .dout(frn_fdis_iu6_i0_error_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_btb_entry_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i0_btb_entry_offset]), + .scout(sov[frn_fdis_iu6_i0_btb_entry_offset]), + .din(frn_fdis_iu6_i0_btb_entry_d), + .dout(frn_fdis_iu6_i0_btb_entry_l2) + ); + + + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) frn_fdis_iu6_i0_btb_hist_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i0_btb_hist_offset:frn_fdis_iu6_i0_btb_hist_offset + 2 - 1]), + .scout(sov[frn_fdis_iu6_i0_btb_hist_offset:frn_fdis_iu6_i0_btb_hist_offset + 2 - 1]), + .din(frn_fdis_iu6_i0_btb_hist_d), + .dout(frn_fdis_iu6_i0_btb_hist_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_bta_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i0_bta_val_offset]), + .scout(sov[frn_fdis_iu6_i0_bta_val_offset]), + .din(frn_fdis_iu6_i0_bta_val_d), + .dout(frn_fdis_iu6_i0_bta_val_l2) + ); + + + tri_rlmreg_p #(.WIDTH(20), .INIT(0)) frn_fdis_iu6_i0_fusion_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i0_fusion_offset:frn_fdis_iu6_i0_fusion_offset + 20 - 1]), + .scout(sov[frn_fdis_iu6_i0_fusion_offset:frn_fdis_iu6_i0_fusion_offset + 20 - 1]), + .din(frn_fdis_iu6_i0_fusion_d), + .dout(frn_fdis_iu6_i0_fusion_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_spec_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i0_spec_offset]), + .scout(sov[frn_fdis_iu6_i0_spec_offset]), + .din(frn_fdis_iu6_i0_spec_d), + .dout(frn_fdis_iu6_i0_spec_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_type_fp_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i0_type_fp_offset]), + .scout(sov[frn_fdis_iu6_i0_type_fp_offset]), + .din(frn_fdis_iu6_i0_type_fp_d), + .dout(frn_fdis_iu6_i0_type_fp_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_type_ap_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i0_type_ap_offset]), + .scout(sov[frn_fdis_iu6_i0_type_ap_offset]), + .din(frn_fdis_iu6_i0_type_ap_d), + .dout(frn_fdis_iu6_i0_type_ap_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_type_spv_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i0_type_spv_offset]), + .scout(sov[frn_fdis_iu6_i0_type_spv_offset]), + .din(frn_fdis_iu6_i0_type_spv_d), + .dout(frn_fdis_iu6_i0_type_spv_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_type_st_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i0_type_st_offset]), + .scout(sov[frn_fdis_iu6_i0_type_st_offset]), + .din(frn_fdis_iu6_i0_type_st_d), + .dout(frn_fdis_iu6_i0_type_st_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_async_block_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i0_async_block_offset]), + .scout(sov[frn_fdis_iu6_i0_async_block_offset]), + .din(frn_fdis_iu6_i0_async_block_d), + .dout(frn_fdis_iu6_i0_async_block_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_np1_flush_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i0_np1_flush_offset]), + .scout(sov[frn_fdis_iu6_i0_np1_flush_offset]), + .din(frn_fdis_iu6_i0_np1_flush_d), + .dout(frn_fdis_iu6_i0_np1_flush_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_core_block_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i0_core_block_offset]), + .scout(sov[frn_fdis_iu6_i0_core_block_offset]), + .din(frn_fdis_iu6_i0_core_block_d), + .dout(frn_fdis_iu6_i0_core_block_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_isram_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i0_isram_offset]), + .scout(sov[frn_fdis_iu6_i0_isram_offset]), + .din(frn_fdis_iu6_i0_isram_d), + .dout(frn_fdis_iu6_i0_isram_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_isload_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i0_isload_offset]), + .scout(sov[frn_fdis_iu6_i0_isload_offset]), + .din(frn_fdis_iu6_i0_isload_d), + .dout(frn_fdis_iu6_i0_isload_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_isstore_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i0_isstore_offset]), + .scout(sov[frn_fdis_iu6_i0_isstore_offset]), + .din(frn_fdis_iu6_i0_isstore_d), + .dout(frn_fdis_iu6_i0_isstore_l2) + ); + + + tri_rlmreg_p #(.WIDTH(32), .INIT(0)) frn_fdis_iu6_i0_instr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i0_instr_offset:frn_fdis_iu6_i0_instr_offset + 32 - 1]), + .scout(sov[frn_fdis_iu6_i0_instr_offset:frn_fdis_iu6_i0_instr_offset + 32 - 1]), + .din(frn_fdis_iu6_i0_instr_d), + .dout(frn_fdis_iu6_i0_instr_l2) + ); + + + tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) frn_fdis_iu6_i0_ifar_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i0_ifar_offset:frn_fdis_iu6_i0_ifar_offset + (`EFF_IFAR_WIDTH) - 1]), + .scout(sov[frn_fdis_iu6_i0_ifar_offset:frn_fdis_iu6_i0_ifar_offset + (`EFF_IFAR_WIDTH) - 1]), + .din(frn_fdis_iu6_i0_ifar_d), + .dout(frn_fdis_iu6_i0_ifar_l2) + ); + + + tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) frn_fdis_iu6_i0_bta_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i0_bta_offset:frn_fdis_iu6_i0_bta_offset + (`EFF_IFAR_WIDTH) - 1]), + .scout(sov[frn_fdis_iu6_i0_bta_offset:frn_fdis_iu6_i0_bta_offset + (`EFF_IFAR_WIDTH) - 1]), + .din(frn_fdis_iu6_i0_bta_d), + .dout(frn_fdis_iu6_i0_bta_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_br_pred_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i0_br_pred_offset]), + .scout(sov[frn_fdis_iu6_i0_br_pred_offset]), + .din(frn_fdis_iu6_i0_br_pred_d), + .dout(frn_fdis_iu6_i0_br_pred_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_bh_update_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i0_bh_update_offset]), + .scout(sov[frn_fdis_iu6_i0_bh_update_offset]), + .din(frn_fdis_iu6_i0_bh_update_d), + .dout(frn_fdis_iu6_i0_bh_update_l2) + ); + + + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) frn_fdis_iu6_i0_bh0_hist_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i0_bh0_hist_offset:frn_fdis_iu6_i0_bh0_hist_offset + 2 - 1]), + .scout(sov[frn_fdis_iu6_i0_bh0_hist_offset:frn_fdis_iu6_i0_bh0_hist_offset + 2 - 1]), + .din(frn_fdis_iu6_i0_bh0_hist_d), + .dout(frn_fdis_iu6_i0_bh0_hist_l2) + ); + + + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) frn_fdis_iu6_i0_bh1_hist_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i0_bh1_hist_offset:frn_fdis_iu6_i0_bh1_hist_offset + 2 - 1]), + .scout(sov[frn_fdis_iu6_i0_bh1_hist_offset:frn_fdis_iu6_i0_bh1_hist_offset + 2 - 1]), + .din(frn_fdis_iu6_i0_bh1_hist_d), + .dout(frn_fdis_iu6_i0_bh1_hist_l2) + ); + + + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) frn_fdis_iu6_i0_bh2_hist_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i0_bh2_hist_offset:frn_fdis_iu6_i0_bh2_hist_offset + 2 - 1]), + .scout(sov[frn_fdis_iu6_i0_bh2_hist_offset:frn_fdis_iu6_i0_bh2_hist_offset + 2 - 1]), + .din(frn_fdis_iu6_i0_bh2_hist_d), + .dout(frn_fdis_iu6_i0_bh2_hist_l2) + ); + + + tri_rlmreg_p #(.WIDTH(18), .INIT(0)) frn_fdis_iu6_i0_gshare_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i0_gshare_offset:frn_fdis_iu6_i0_gshare_offset + 18 - 1]), + .scout(sov[frn_fdis_iu6_i0_gshare_offset:frn_fdis_iu6_i0_gshare_offset + 18 - 1]), + .din(frn_fdis_iu6_i0_gshare_d), + .dout(frn_fdis_iu6_i0_gshare_l2) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) frn_fdis_iu6_i0_ls_ptr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i0_ls_ptr_offset:frn_fdis_iu6_i0_ls_ptr_offset + 3 - 1]), + .scout(sov[frn_fdis_iu6_i0_ls_ptr_offset:frn_fdis_iu6_i0_ls_ptr_offset + 3 - 1]), + .din(frn_fdis_iu6_i0_ls_ptr_d), + .dout(frn_fdis_iu6_i0_ls_ptr_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_match_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i0_match_offset]), + .scout(sov[frn_fdis_iu6_i0_match_offset]), + .din(frn_fdis_iu6_i0_match_d), + .dout(frn_fdis_iu6_i0_match_l2) + ); + + + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) frn_fdis_iu6_i0_ilat_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i0_ilat_offset:frn_fdis_iu6_i0_ilat_offset + 4 - 1]), + .scout(sov[frn_fdis_iu6_i0_ilat_offset:frn_fdis_iu6_i0_ilat_offset + 4 - 1]), + .din(frn_fdis_iu6_i0_ilat_d), + .dout(frn_fdis_iu6_i0_ilat_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_t1_v_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i0_t1_v_offset]), + .scout(sov[frn_fdis_iu6_i0_t1_v_offset]), + .din(frn_fdis_iu6_i0_t1_v_d), + .dout(frn_fdis_iu6_i0_t1_v_l2) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) frn_fdis_iu6_i0_t1_t_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i0_t1_t_offset:frn_fdis_iu6_i0_t1_t_offset + 3 - 1]), + .scout(sov[frn_fdis_iu6_i0_t1_t_offset:frn_fdis_iu6_i0_t1_t_offset + 3 - 1]), + .din(frn_fdis_iu6_i0_t1_t_d), + .dout(frn_fdis_iu6_i0_t1_t_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) frn_fdis_iu6_i0_t1_a_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i0_t1_a_offset:frn_fdis_iu6_i0_t1_a_offset + `GPR_POOL_ENC - 1]), + .scout(sov[frn_fdis_iu6_i0_t1_a_offset:frn_fdis_iu6_i0_t1_a_offset + `GPR_POOL_ENC - 1]), + .din(frn_fdis_iu6_i0_t1_a_d), + .dout(frn_fdis_iu6_i0_t1_a_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) frn_fdis_iu6_i0_t1_p_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i0_t1_p_offset:frn_fdis_iu6_i0_t1_p_offset + `GPR_POOL_ENC - 1]), + .scout(sov[frn_fdis_iu6_i0_t1_p_offset:frn_fdis_iu6_i0_t1_p_offset + `GPR_POOL_ENC - 1]), + .din(frn_fdis_iu6_i0_t1_p_d), + .dout(frn_fdis_iu6_i0_t1_p_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_t2_v_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i0_t2_v_offset]), + .scout(sov[frn_fdis_iu6_i0_t2_v_offset]), + .din(frn_fdis_iu6_i0_t2_v_d), + .dout(frn_fdis_iu6_i0_t2_v_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) frn_fdis_iu6_i0_t2_a_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i0_t2_a_offset:frn_fdis_iu6_i0_t2_a_offset + `GPR_POOL_ENC - 1]), + .scout(sov[frn_fdis_iu6_i0_t2_a_offset:frn_fdis_iu6_i0_t2_a_offset + `GPR_POOL_ENC - 1]), + .din(frn_fdis_iu6_i0_t2_a_d), + .dout(frn_fdis_iu6_i0_t2_a_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) frn_fdis_iu6_i0_t2_p_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i0_t2_p_offset:frn_fdis_iu6_i0_t2_p_offset + `GPR_POOL_ENC - 1]), + .scout(sov[frn_fdis_iu6_i0_t2_p_offset:frn_fdis_iu6_i0_t2_p_offset + `GPR_POOL_ENC - 1]), + .din(frn_fdis_iu6_i0_t2_p_d), + .dout(frn_fdis_iu6_i0_t2_p_l2) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) frn_fdis_iu6_i0_t2_t_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i0_t2_t_offset:frn_fdis_iu6_i0_t2_t_offset + 3 - 1]), + .scout(sov[frn_fdis_iu6_i0_t2_t_offset:frn_fdis_iu6_i0_t2_t_offset + 3 - 1]), + .din(frn_fdis_iu6_i0_t2_t_d), + .dout(frn_fdis_iu6_i0_t2_t_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_t3_v_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i0_t3_v_offset]), + .scout(sov[frn_fdis_iu6_i0_t3_v_offset]), + .din(frn_fdis_iu6_i0_t3_v_d), + .dout(frn_fdis_iu6_i0_t3_v_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) frn_fdis_iu6_i0_t3_a_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i0_t3_a_offset:frn_fdis_iu6_i0_t3_a_offset + `GPR_POOL_ENC - 1]), + .scout(sov[frn_fdis_iu6_i0_t3_a_offset:frn_fdis_iu6_i0_t3_a_offset + `GPR_POOL_ENC - 1]), + .din(frn_fdis_iu6_i0_t3_a_d), + .dout(frn_fdis_iu6_i0_t3_a_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) frn_fdis_iu6_i0_t3_p_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i0_t3_p_offset:frn_fdis_iu6_i0_t3_p_offset + `GPR_POOL_ENC - 1]), + .scout(sov[frn_fdis_iu6_i0_t3_p_offset:frn_fdis_iu6_i0_t3_p_offset + `GPR_POOL_ENC - 1]), + .din(frn_fdis_iu6_i0_t3_p_d), + .dout(frn_fdis_iu6_i0_t3_p_l2) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) frn_fdis_iu6_i0_t3_t_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i0_t3_t_offset:frn_fdis_iu6_i0_t3_t_offset + 3 - 1]), + .scout(sov[frn_fdis_iu6_i0_t3_t_offset:frn_fdis_iu6_i0_t3_t_offset + 3 - 1]), + .din(frn_fdis_iu6_i0_t3_t_d), + .dout(frn_fdis_iu6_i0_t3_t_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_s1_v_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i0_s1_v_offset]), + .scout(sov[frn_fdis_iu6_i0_s1_v_offset]), + .din(frn_fdis_iu6_i0_s1_v_d), + .dout(frn_fdis_iu6_i0_s1_v_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) frn_fdis_iu6_i0_s1_a_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i0_s1_a_offset:frn_fdis_iu6_i0_s1_a_offset + `GPR_POOL_ENC - 1]), + .scout(sov[frn_fdis_iu6_i0_s1_a_offset:frn_fdis_iu6_i0_s1_a_offset + `GPR_POOL_ENC - 1]), + .din(frn_fdis_iu6_i0_s1_a_d), + .dout(frn_fdis_iu6_i0_s1_a_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) frn_fdis_iu6_i0_s1_p_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i0_s1_p_offset:frn_fdis_iu6_i0_s1_p_offset + `GPR_POOL_ENC - 1]), + .scout(sov[frn_fdis_iu6_i0_s1_p_offset:frn_fdis_iu6_i0_s1_p_offset + `GPR_POOL_ENC - 1]), + .din(frn_fdis_iu6_i0_s1_p_d), + .dout(frn_fdis_iu6_i0_s1_p_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) frn_fdis_iu6_i0_s1_itag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i0_s1_itag_offset:frn_fdis_iu6_i0_s1_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[frn_fdis_iu6_i0_s1_itag_offset:frn_fdis_iu6_i0_s1_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(frn_fdis_iu6_i0_s1_itag_d), + .dout(frn_fdis_iu6_i0_s1_itag_l2) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) frn_fdis_iu6_i0_s1_t_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i0_s1_t_offset:frn_fdis_iu6_i0_s1_t_offset + 3 - 1]), + .scout(sov[frn_fdis_iu6_i0_s1_t_offset:frn_fdis_iu6_i0_s1_t_offset + 3 - 1]), + .din(frn_fdis_iu6_i0_s1_t_d), + .dout(frn_fdis_iu6_i0_s1_t_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_s2_v_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i0_s2_v_offset]), + .scout(sov[frn_fdis_iu6_i0_s2_v_offset]), + .din(frn_fdis_iu6_i0_s2_v_d), + .dout(frn_fdis_iu6_i0_s2_v_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) frn_fdis_iu6_i0_s2_a_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i0_s2_a_offset:frn_fdis_iu6_i0_s2_a_offset + `GPR_POOL_ENC - 1]), + .scout(sov[frn_fdis_iu6_i0_s2_a_offset:frn_fdis_iu6_i0_s2_a_offset + `GPR_POOL_ENC - 1]), + .din(frn_fdis_iu6_i0_s2_a_d), + .dout(frn_fdis_iu6_i0_s2_a_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) frn_fdis_iu6_i0_s2_p_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i0_s2_p_offset:frn_fdis_iu6_i0_s2_p_offset + `GPR_POOL_ENC - 1]), + .scout(sov[frn_fdis_iu6_i0_s2_p_offset:frn_fdis_iu6_i0_s2_p_offset + `GPR_POOL_ENC - 1]), + .din(frn_fdis_iu6_i0_s2_p_d), + .dout(frn_fdis_iu6_i0_s2_p_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) frn_fdis_iu6_i0_s2_itag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i0_s2_itag_offset:frn_fdis_iu6_i0_s2_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[frn_fdis_iu6_i0_s2_itag_offset:frn_fdis_iu6_i0_s2_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(frn_fdis_iu6_i0_s2_itag_d), + .dout(frn_fdis_iu6_i0_s2_itag_l2) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) frn_fdis_iu6_i0_s2_t_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i0_s2_t_offset:frn_fdis_iu6_i0_s2_t_offset + 3 - 1]), + .scout(sov[frn_fdis_iu6_i0_s2_t_offset:frn_fdis_iu6_i0_s2_t_offset + 3 - 1]), + .din(frn_fdis_iu6_i0_s2_t_d), + .dout(frn_fdis_iu6_i0_s2_t_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_s3_v_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i0_s3_v_offset]), + .scout(sov[frn_fdis_iu6_i0_s3_v_offset]), + .din(frn_fdis_iu6_i0_s3_v_d), + .dout(frn_fdis_iu6_i0_s3_v_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) frn_fdis_iu6_i0_s3_a_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i0_s3_a_offset:frn_fdis_iu6_i0_s3_a_offset + `GPR_POOL_ENC - 1]), + .scout(sov[frn_fdis_iu6_i0_s3_a_offset:frn_fdis_iu6_i0_s3_a_offset + `GPR_POOL_ENC - 1]), + .din(frn_fdis_iu6_i0_s3_a_d), + .dout(frn_fdis_iu6_i0_s3_a_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) frn_fdis_iu6_i0_s3_p_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i0_s3_p_offset:frn_fdis_iu6_i0_s3_p_offset + `GPR_POOL_ENC - 1]), + .scout(sov[frn_fdis_iu6_i0_s3_p_offset:frn_fdis_iu6_i0_s3_p_offset + `GPR_POOL_ENC - 1]), + .din(frn_fdis_iu6_i0_s3_p_d), + .dout(frn_fdis_iu6_i0_s3_p_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) frn_fdis_iu6_i0_s3_itag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i0_s3_itag_offset:frn_fdis_iu6_i0_s3_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[frn_fdis_iu6_i0_s3_itag_offset:frn_fdis_iu6_i0_s3_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(frn_fdis_iu6_i0_s3_itag_d), + .dout(frn_fdis_iu6_i0_s3_itag_l2) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) frn_fdis_iu6_i0_s3_t_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i0_s3_t_offset:frn_fdis_iu6_i0_s3_t_offset + 3 - 1]), + .scout(sov[frn_fdis_iu6_i0_s3_t_offset:frn_fdis_iu6_i0_s3_t_offset + 3 - 1]), + .din(frn_fdis_iu6_i0_s3_t_d), + .dout(frn_fdis_iu6_i0_s3_t_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_vld_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i1_vld_offset]), + .scout(sov[frn_fdis_iu6_i1_vld_offset]), + .din(frn_fdis_iu6_i1_vld_d), + .dout(frn_fdis_iu6_i1_vld_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) frn_fdis_iu6_i1_itag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i1_itag_offset:frn_fdis_iu6_i1_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[frn_fdis_iu6_i1_itag_offset:frn_fdis_iu6_i1_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(frn_fdis_iu6_i1_itag_d), + .dout(frn_fdis_iu6_i1_itag_l2) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) frn_fdis_iu6_i1_ucode_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i1_ucode_offset:frn_fdis_iu6_i1_ucode_offset + 3 - 1]), + .scout(sov[frn_fdis_iu6_i1_ucode_offset:frn_fdis_iu6_i1_ucode_offset + 3 - 1]), + .din(frn_fdis_iu6_i1_ucode_d), + .dout(frn_fdis_iu6_i1_ucode_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`UCODE_ENTRIES_ENC), .INIT(0)) frn_fdis_iu6_i1_ucode_cnt_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i1_ucode_cnt_offset:frn_fdis_iu6_i1_ucode_cnt_offset + `UCODE_ENTRIES_ENC - 1]), + .scout(sov[frn_fdis_iu6_i1_ucode_cnt_offset:frn_fdis_iu6_i1_ucode_cnt_offset + `UCODE_ENTRIES_ENC - 1]), + .din(frn_fdis_iu6_i1_ucode_cnt_d), + .dout(frn_fdis_iu6_i1_ucode_cnt_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_fuse_nop_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i1_fuse_nop_offset]), + .scout(sov[frn_fdis_iu6_i1_fuse_nop_offset]), + .din(frn_fdis_iu6_i1_fuse_nop_d), + .dout(frn_fdis_iu6_i1_fuse_nop_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_rte_lq_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i1_rte_lq_offset]), + .scout(sov[frn_fdis_iu6_i1_rte_lq_offset]), + .din(frn_fdis_iu6_i1_rte_lq_d), + .dout(frn_fdis_iu6_i1_rte_lq_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_rte_sq_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i1_rte_sq_offset]), + .scout(sov[frn_fdis_iu6_i1_rte_sq_offset]), + .din(frn_fdis_iu6_i1_rte_sq_d), + .dout(frn_fdis_iu6_i1_rte_sq_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_rte_fx0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i1_rte_fx0_offset]), + .scout(sov[frn_fdis_iu6_i1_rte_fx0_offset]), + .din(frn_fdis_iu6_i1_rte_fx0_d), + .dout(frn_fdis_iu6_i1_rte_fx0_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_rte_fx1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i1_rte_fx1_offset]), + .scout(sov[frn_fdis_iu6_i1_rte_fx1_offset]), + .din(frn_fdis_iu6_i1_rte_fx1_d), + .dout(frn_fdis_iu6_i1_rte_fx1_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_rte_axu0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i1_rte_axu0_offset]), + .scout(sov[frn_fdis_iu6_i1_rte_axu0_offset]), + .din(frn_fdis_iu6_i1_rte_axu0_d), + .dout(frn_fdis_iu6_i1_rte_axu0_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_rte_axu1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i1_rte_axu1_offset]), + .scout(sov[frn_fdis_iu6_i1_rte_axu1_offset]), + .din(frn_fdis_iu6_i1_rte_axu1_d), + .dout(frn_fdis_iu6_i1_rte_axu1_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_valop_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i1_valop_offset]), + .scout(sov[frn_fdis_iu6_i1_valop_offset]), + .din(frn_fdis_iu6_i1_valop_d), + .dout(frn_fdis_iu6_i1_valop_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_ord_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i1_ord_offset]), + .scout(sov[frn_fdis_iu6_i1_ord_offset]), + .din(frn_fdis_iu6_i1_ord_d), + .dout(frn_fdis_iu6_i1_ord_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_cord_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i1_cord_offset]), + .scout(sov[frn_fdis_iu6_i1_cord_offset]), + .din(frn_fdis_iu6_i1_cord_d), + .dout(frn_fdis_iu6_i1_cord_l2) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) frn_fdis_iu6_i1_error_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i1_error_offset:frn_fdis_iu6_i1_error_offset + 3 - 1]), + .scout(sov[frn_fdis_iu6_i1_error_offset:frn_fdis_iu6_i1_error_offset + 3 - 1]), + .din(frn_fdis_iu6_i1_error_d), + .dout(frn_fdis_iu6_i1_error_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_btb_entry_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i1_btb_entry_offset]), + .scout(sov[frn_fdis_iu6_i1_btb_entry_offset]), + .din(frn_fdis_iu6_i1_btb_entry_d), + .dout(frn_fdis_iu6_i1_btb_entry_l2) + ); + + + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) frn_fdis_iu6_i1_btb_hist_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i1_btb_hist_offset:frn_fdis_iu6_i1_btb_hist_offset + 2 - 1]), + .scout(sov[frn_fdis_iu6_i1_btb_hist_offset:frn_fdis_iu6_i1_btb_hist_offset + 2 - 1]), + .din(frn_fdis_iu6_i1_btb_hist_d), + .dout(frn_fdis_iu6_i1_btb_hist_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_bta_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i1_bta_val_offset]), + .scout(sov[frn_fdis_iu6_i1_bta_val_offset]), + .din(frn_fdis_iu6_i1_bta_val_d), + .dout(frn_fdis_iu6_i1_bta_val_l2) + ); + + + tri_rlmreg_p #(.WIDTH(20), .INIT(0)) frn_fdis_iu6_i1_fusion_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i1_fusion_offset:frn_fdis_iu6_i1_fusion_offset + 20 - 1]), + .scout(sov[frn_fdis_iu6_i1_fusion_offset:frn_fdis_iu6_i1_fusion_offset + 20 - 1]), + .din(frn_fdis_iu6_i1_fusion_d), + .dout(frn_fdis_iu6_i1_fusion_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_spec_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i1_spec_offset]), + .scout(sov[frn_fdis_iu6_i1_spec_offset]), + .din(frn_fdis_iu6_i1_spec_d), + .dout(frn_fdis_iu6_i1_spec_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_type_fp_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i1_type_fp_offset]), + .scout(sov[frn_fdis_iu6_i1_type_fp_offset]), + .din(frn_fdis_iu6_i1_type_fp_d), + .dout(frn_fdis_iu6_i1_type_fp_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_type_ap_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i1_type_ap_offset]), + .scout(sov[frn_fdis_iu6_i1_type_ap_offset]), + .din(frn_fdis_iu6_i1_type_ap_d), + .dout(frn_fdis_iu6_i1_type_ap_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_type_spv_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i1_type_spv_offset]), + .scout(sov[frn_fdis_iu6_i1_type_spv_offset]), + .din(frn_fdis_iu6_i1_type_spv_d), + .dout(frn_fdis_iu6_i1_type_spv_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_type_st_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i1_type_st_offset]), + .scout(sov[frn_fdis_iu6_i1_type_st_offset]), + .din(frn_fdis_iu6_i1_type_st_d), + .dout(frn_fdis_iu6_i1_type_st_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_async_block_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i1_async_block_offset]), + .scout(sov[frn_fdis_iu6_i1_async_block_offset]), + .din(frn_fdis_iu6_i1_async_block_d), + .dout(frn_fdis_iu6_i1_async_block_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_np1_flush_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i1_np1_flush_offset]), + .scout(sov[frn_fdis_iu6_i1_np1_flush_offset]), + .din(frn_fdis_iu6_i1_np1_flush_d), + .dout(frn_fdis_iu6_i1_np1_flush_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_core_block_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i1_core_block_offset]), + .scout(sov[frn_fdis_iu6_i1_core_block_offset]), + .din(frn_fdis_iu6_i1_core_block_d), + .dout(frn_fdis_iu6_i1_core_block_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_isram_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i1_isram_offset]), + .scout(sov[frn_fdis_iu6_i1_isram_offset]), + .din(frn_fdis_iu6_i1_isram_d), + .dout(frn_fdis_iu6_i1_isram_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_isload_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i1_isload_offset]), + .scout(sov[frn_fdis_iu6_i1_isload_offset]), + .din(frn_fdis_iu6_i1_isload_d), + .dout(frn_fdis_iu6_i1_isload_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_isstore_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i1_isstore_offset]), + .scout(sov[frn_fdis_iu6_i1_isstore_offset]), + .din(frn_fdis_iu6_i1_isstore_d), + .dout(frn_fdis_iu6_i1_isstore_l2) + ); + + + tri_rlmreg_p #(.WIDTH(32), .INIT(0)) frn_fdis_iu6_i1_instr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i1_instr_offset:frn_fdis_iu6_i1_instr_offset + 32 - 1]), + .scout(sov[frn_fdis_iu6_i1_instr_offset:frn_fdis_iu6_i1_instr_offset + 32 - 1]), + .din(frn_fdis_iu6_i1_instr_d), + .dout(frn_fdis_iu6_i1_instr_l2) + ); + + + tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) frn_fdis_iu6_i1_ifar_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i1_ifar_offset:frn_fdis_iu6_i1_ifar_offset + (`EFF_IFAR_WIDTH) - 1]), + .scout(sov[frn_fdis_iu6_i1_ifar_offset:frn_fdis_iu6_i1_ifar_offset + (`EFF_IFAR_WIDTH) - 1]), + .din(frn_fdis_iu6_i1_ifar_d), + .dout(frn_fdis_iu6_i1_ifar_l2) + ); + + + tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) frn_fdis_iu6_i1_bta_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i1_bta_offset:frn_fdis_iu6_i1_bta_offset + (`EFF_IFAR_WIDTH) - 1]), + .scout(sov[frn_fdis_iu6_i1_bta_offset:frn_fdis_iu6_i1_bta_offset + (`EFF_IFAR_WIDTH) - 1]), + .din(frn_fdis_iu6_i1_bta_d), + .dout(frn_fdis_iu6_i1_bta_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_br_pred_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i1_br_pred_offset]), + .scout(sov[frn_fdis_iu6_i1_br_pred_offset]), + .din(frn_fdis_iu6_i1_br_pred_d), + .dout(frn_fdis_iu6_i1_br_pred_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_bh_update_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i1_bh_update_offset]), + .scout(sov[frn_fdis_iu6_i1_bh_update_offset]), + .din(frn_fdis_iu6_i1_bh_update_d), + .dout(frn_fdis_iu6_i1_bh_update_l2) + ); + + + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) frn_fdis_iu6_i1_bh0_hist_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i1_bh0_hist_offset:frn_fdis_iu6_i1_bh0_hist_offset + 2 - 1]), + .scout(sov[frn_fdis_iu6_i1_bh0_hist_offset:frn_fdis_iu6_i1_bh0_hist_offset + 2 - 1]), + .din(frn_fdis_iu6_i1_bh0_hist_d), + .dout(frn_fdis_iu6_i1_bh0_hist_l2) + ); + + + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) frn_fdis_iu6_i1_bh1_hist_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i1_bh1_hist_offset:frn_fdis_iu6_i1_bh1_hist_offset + 2 - 1]), + .scout(sov[frn_fdis_iu6_i1_bh1_hist_offset:frn_fdis_iu6_i1_bh1_hist_offset + 2 - 1]), + .din(frn_fdis_iu6_i1_bh1_hist_d), + .dout(frn_fdis_iu6_i1_bh1_hist_l2) + ); + + + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) frn_fdis_iu6_i1_bh2_hist_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i1_bh2_hist_offset:frn_fdis_iu6_i1_bh2_hist_offset + 2 - 1]), + .scout(sov[frn_fdis_iu6_i1_bh2_hist_offset:frn_fdis_iu6_i1_bh2_hist_offset + 2 - 1]), + .din(frn_fdis_iu6_i1_bh2_hist_d), + .dout(frn_fdis_iu6_i1_bh2_hist_l2) + ); + + + tri_rlmreg_p #(.WIDTH(18), .INIT(0)) frn_fdis_iu6_i1_gshare_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i1_gshare_offset:frn_fdis_iu6_i1_gshare_offset + 18 - 1]), + .scout(sov[frn_fdis_iu6_i1_gshare_offset:frn_fdis_iu6_i1_gshare_offset + 18 - 1]), + .din(frn_fdis_iu6_i1_gshare_d), + .dout(frn_fdis_iu6_i1_gshare_l2) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) frn_fdis_iu6_i1_ls_ptr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i1_ls_ptr_offset:frn_fdis_iu6_i1_ls_ptr_offset + 3 - 1]), + .scout(sov[frn_fdis_iu6_i1_ls_ptr_offset:frn_fdis_iu6_i1_ls_ptr_offset + 3 - 1]), + .din(frn_fdis_iu6_i1_ls_ptr_d), + .dout(frn_fdis_iu6_i1_ls_ptr_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_match_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i1_match_offset]), + .scout(sov[frn_fdis_iu6_i1_match_offset]), + .din(frn_fdis_iu6_i1_match_d), + .dout(frn_fdis_iu6_i1_match_l2) + ); + + + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) frn_fdis_iu6_i1_ilat_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i1_ilat_offset:frn_fdis_iu6_i1_ilat_offset + 4 - 1]), + .scout(sov[frn_fdis_iu6_i1_ilat_offset:frn_fdis_iu6_i1_ilat_offset + 4 - 1]), + .din(frn_fdis_iu6_i1_ilat_d), + .dout(frn_fdis_iu6_i1_ilat_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_t1_v_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i1_t1_v_offset]), + .scout(sov[frn_fdis_iu6_i1_t1_v_offset]), + .din(frn_fdis_iu6_i1_t1_v_d), + .dout(frn_fdis_iu6_i1_t1_v_l2) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) frn_fdis_iu6_i1_t1_t_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i1_t1_t_offset:frn_fdis_iu6_i1_t1_t_offset + 3 - 1]), + .scout(sov[frn_fdis_iu6_i1_t1_t_offset:frn_fdis_iu6_i1_t1_t_offset + 3 - 1]), + .din(frn_fdis_iu6_i1_t1_t_d), + .dout(frn_fdis_iu6_i1_t1_t_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) frn_fdis_iu6_i1_t1_a_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i1_t1_a_offset:frn_fdis_iu6_i1_t1_a_offset + `GPR_POOL_ENC - 1]), + .scout(sov[frn_fdis_iu6_i1_t1_a_offset:frn_fdis_iu6_i1_t1_a_offset + `GPR_POOL_ENC - 1]), + .din(frn_fdis_iu6_i1_t1_a_d), + .dout(frn_fdis_iu6_i1_t1_a_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) frn_fdis_iu6_i1_t1_p_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i1_t1_p_offset:frn_fdis_iu6_i1_t1_p_offset + `GPR_POOL_ENC - 1]), + .scout(sov[frn_fdis_iu6_i1_t1_p_offset:frn_fdis_iu6_i1_t1_p_offset + `GPR_POOL_ENC - 1]), + .din(frn_fdis_iu6_i1_t1_p_d), + .dout(frn_fdis_iu6_i1_t1_p_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_t2_v_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i1_t2_v_offset]), + .scout(sov[frn_fdis_iu6_i1_t2_v_offset]), + .din(frn_fdis_iu6_i1_t2_v_d), + .dout(frn_fdis_iu6_i1_t2_v_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) frn_fdis_iu6_i1_t2_a_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i1_t2_a_offset:frn_fdis_iu6_i1_t2_a_offset + `GPR_POOL_ENC - 1]), + .scout(sov[frn_fdis_iu6_i1_t2_a_offset:frn_fdis_iu6_i1_t2_a_offset + `GPR_POOL_ENC - 1]), + .din(frn_fdis_iu6_i1_t2_a_d), + .dout(frn_fdis_iu6_i1_t2_a_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) frn_fdis_iu6_i1_t2_p_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i1_t2_p_offset:frn_fdis_iu6_i1_t2_p_offset + `GPR_POOL_ENC - 1]), + .scout(sov[frn_fdis_iu6_i1_t2_p_offset:frn_fdis_iu6_i1_t2_p_offset + `GPR_POOL_ENC - 1]), + .din(frn_fdis_iu6_i1_t2_p_d), + .dout(frn_fdis_iu6_i1_t2_p_l2) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) frn_fdis_iu6_i1_t2_t_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i1_t2_t_offset:frn_fdis_iu6_i1_t2_t_offset + 3 - 1]), + .scout(sov[frn_fdis_iu6_i1_t2_t_offset:frn_fdis_iu6_i1_t2_t_offset + 3 - 1]), + .din(frn_fdis_iu6_i1_t2_t_d), + .dout(frn_fdis_iu6_i1_t2_t_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_t3_v_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i1_t3_v_offset]), + .scout(sov[frn_fdis_iu6_i1_t3_v_offset]), + .din(frn_fdis_iu6_i1_t3_v_d), + .dout(frn_fdis_iu6_i1_t3_v_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) frn_fdis_iu6_i1_t3_a_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i1_t3_a_offset:frn_fdis_iu6_i1_t3_a_offset + `GPR_POOL_ENC - 1]), + .scout(sov[frn_fdis_iu6_i1_t3_a_offset:frn_fdis_iu6_i1_t3_a_offset + `GPR_POOL_ENC - 1]), + .din(frn_fdis_iu6_i1_t3_a_d), + .dout(frn_fdis_iu6_i1_t3_a_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) frn_fdis_iu6_i1_t3_p_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i1_t3_p_offset:frn_fdis_iu6_i1_t3_p_offset + `GPR_POOL_ENC - 1]), + .scout(sov[frn_fdis_iu6_i1_t3_p_offset:frn_fdis_iu6_i1_t3_p_offset + `GPR_POOL_ENC - 1]), + .din(frn_fdis_iu6_i1_t3_p_d), + .dout(frn_fdis_iu6_i1_t3_p_l2) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) frn_fdis_iu6_i1_t3_t_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i1_t3_t_offset:frn_fdis_iu6_i1_t3_t_offset + 3 - 1]), + .scout(sov[frn_fdis_iu6_i1_t3_t_offset:frn_fdis_iu6_i1_t3_t_offset + 3 - 1]), + .din(frn_fdis_iu6_i1_t3_t_d), + .dout(frn_fdis_iu6_i1_t3_t_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_s1_v_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i1_s1_v_offset]), + .scout(sov[frn_fdis_iu6_i1_s1_v_offset]), + .din(frn_fdis_iu6_i1_s1_v_d), + .dout(frn_fdis_iu6_i1_s1_v_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) frn_fdis_iu6_i1_s1_a_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i1_s1_a_offset:frn_fdis_iu6_i1_s1_a_offset + `GPR_POOL_ENC - 1]), + .scout(sov[frn_fdis_iu6_i1_s1_a_offset:frn_fdis_iu6_i1_s1_a_offset + `GPR_POOL_ENC - 1]), + .din(frn_fdis_iu6_i1_s1_a_d), + .dout(frn_fdis_iu6_i1_s1_a_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) frn_fdis_iu6_i1_s1_p_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i1_s1_p_offset:frn_fdis_iu6_i1_s1_p_offset + `GPR_POOL_ENC - 1]), + .scout(sov[frn_fdis_iu6_i1_s1_p_offset:frn_fdis_iu6_i1_s1_p_offset + `GPR_POOL_ENC - 1]), + .din(frn_fdis_iu6_i1_s1_p_d), + .dout(frn_fdis_iu6_i1_s1_p_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) frn_fdis_iu6_i1_s1_itag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i1_s1_itag_offset:frn_fdis_iu6_i1_s1_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[frn_fdis_iu6_i1_s1_itag_offset:frn_fdis_iu6_i1_s1_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(frn_fdis_iu6_i1_s1_itag_d), + .dout(frn_fdis_iu6_i1_s1_itag_l2) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) frn_fdis_iu6_i1_s1_t_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i1_s1_t_offset:frn_fdis_iu6_i1_s1_t_offset + 3 - 1]), + .scout(sov[frn_fdis_iu6_i1_s1_t_offset:frn_fdis_iu6_i1_s1_t_offset + 3 - 1]), + .din(frn_fdis_iu6_i1_s1_t_d), + .dout(frn_fdis_iu6_i1_s1_t_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_s1_dep_hit_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i1_s1_dep_hit_offset]), + .scout(sov[frn_fdis_iu6_i1_s1_dep_hit_offset]), + .din(frn_fdis_iu6_i1_s1_dep_hit_d), + .dout(frn_fdis_iu6_i1_s1_dep_hit_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_s2_v_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i1_s2_v_offset]), + .scout(sov[frn_fdis_iu6_i1_s2_v_offset]), + .din(frn_fdis_iu6_i1_s2_v_d), + .dout(frn_fdis_iu6_i1_s2_v_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) frn_fdis_iu6_i1_s2_a_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i1_s2_a_offset:frn_fdis_iu6_i1_s2_a_offset + `GPR_POOL_ENC - 1]), + .scout(sov[frn_fdis_iu6_i1_s2_a_offset:frn_fdis_iu6_i1_s2_a_offset + `GPR_POOL_ENC - 1]), + .din(frn_fdis_iu6_i1_s2_a_d), + .dout(frn_fdis_iu6_i1_s2_a_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) frn_fdis_iu6_i1_s2_p_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i1_s2_p_offset:frn_fdis_iu6_i1_s2_p_offset + `GPR_POOL_ENC - 1]), + .scout(sov[frn_fdis_iu6_i1_s2_p_offset:frn_fdis_iu6_i1_s2_p_offset + `GPR_POOL_ENC - 1]), + .din(frn_fdis_iu6_i1_s2_p_d), + .dout(frn_fdis_iu6_i1_s2_p_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) frn_fdis_iu6_i1_s2_itag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i1_s2_itag_offset:frn_fdis_iu6_i1_s2_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[frn_fdis_iu6_i1_s2_itag_offset:frn_fdis_iu6_i1_s2_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(frn_fdis_iu6_i1_s2_itag_d), + .dout(frn_fdis_iu6_i1_s2_itag_l2) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) frn_fdis_iu6_i1_s2_t_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i1_s2_t_offset:frn_fdis_iu6_i1_s2_t_offset + 3 - 1]), + .scout(sov[frn_fdis_iu6_i1_s2_t_offset:frn_fdis_iu6_i1_s2_t_offset + 3 - 1]), + .din(frn_fdis_iu6_i1_s2_t_d), + .dout(frn_fdis_iu6_i1_s2_t_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_s2_dep_hit_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i1_s2_dep_hit_offset]), + .scout(sov[frn_fdis_iu6_i1_s2_dep_hit_offset]), + .din(frn_fdis_iu6_i1_s2_dep_hit_d), + .dout(frn_fdis_iu6_i1_s2_dep_hit_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_s3_v_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i1_s3_v_offset]), + .scout(sov[frn_fdis_iu6_i1_s3_v_offset]), + .din(frn_fdis_iu6_i1_s3_v_d), + .dout(frn_fdis_iu6_i1_s3_v_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) frn_fdis_iu6_i1_s3_a_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i1_s3_a_offset:frn_fdis_iu6_i1_s3_a_offset + `GPR_POOL_ENC - 1]), + .scout(sov[frn_fdis_iu6_i1_s3_a_offset:frn_fdis_iu6_i1_s3_a_offset + `GPR_POOL_ENC - 1]), + .din(frn_fdis_iu6_i1_s3_a_d), + .dout(frn_fdis_iu6_i1_s3_a_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) frn_fdis_iu6_i1_s3_p_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i1_s3_p_offset:frn_fdis_iu6_i1_s3_p_offset + `GPR_POOL_ENC - 1]), + .scout(sov[frn_fdis_iu6_i1_s3_p_offset:frn_fdis_iu6_i1_s3_p_offset + `GPR_POOL_ENC - 1]), + .din(frn_fdis_iu6_i1_s3_p_d), + .dout(frn_fdis_iu6_i1_s3_p_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) frn_fdis_iu6_i1_s3_itag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i1_s3_itag_offset:frn_fdis_iu6_i1_s3_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[frn_fdis_iu6_i1_s3_itag_offset:frn_fdis_iu6_i1_s3_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(frn_fdis_iu6_i1_s3_itag_d), + .dout(frn_fdis_iu6_i1_s3_itag_l2) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) frn_fdis_iu6_i1_s3_t_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[frn_fdis_iu6_i1_s3_t_offset:frn_fdis_iu6_i1_s3_t_offset + 3 - 1]), + .scout(sov[frn_fdis_iu6_i1_s3_t_offset:frn_fdis_iu6_i1_s3_t_offset + 3 - 1]), + .din(frn_fdis_iu6_i1_s3_t_d), + .dout(frn_fdis_iu6_i1_s3_t_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_s3_dep_hit_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[frn_fdis_iu6_i1_s3_dep_hit_offset]), + .scout(sov[frn_fdis_iu6_i1_s3_dep_hit_offset]), + .din(frn_fdis_iu6_i1_s3_dep_hit_d), + .dout(frn_fdis_iu6_i1_s3_dep_hit_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_vld_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i0_vld_offset]), + .scout(sov[stall_frn_fdis_iu6_i0_vld_offset]), + .din(stall_frn_fdis_iu6_i0_vld_d), + .dout(stall_frn_fdis_iu6_i0_vld_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) stall_frn_fdis_iu6_i0_itag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i0_itag_offset:stall_frn_fdis_iu6_i0_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[stall_frn_fdis_iu6_i0_itag_offset:stall_frn_fdis_iu6_i0_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(stall_frn_fdis_iu6_i0_itag_d), + .dout(stall_frn_fdis_iu6_i0_itag_l2) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) stall_frn_fdis_iu6_i0_ucode_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i0_ucode_offset:stall_frn_fdis_iu6_i0_ucode_offset + 3 - 1]), + .scout(sov[stall_frn_fdis_iu6_i0_ucode_offset:stall_frn_fdis_iu6_i0_ucode_offset + 3 - 1]), + .din(stall_frn_fdis_iu6_i0_ucode_d), + .dout(stall_frn_fdis_iu6_i0_ucode_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`UCODE_ENTRIES_ENC), .INIT(0)) stall_frn_fdis_iu6_i0_ucode_cnt_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i0_ucode_cnt_offset:stall_frn_fdis_iu6_i0_ucode_cnt_offset + `UCODE_ENTRIES_ENC - 1]), + .scout(sov[stall_frn_fdis_iu6_i0_ucode_cnt_offset:stall_frn_fdis_iu6_i0_ucode_cnt_offset + `UCODE_ENTRIES_ENC - 1]), + .din(stall_frn_fdis_iu6_i0_ucode_cnt_d), + .dout(stall_frn_fdis_iu6_i0_ucode_cnt_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_2ucode_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i0_2ucode_offset]), + .scout(sov[stall_frn_fdis_iu6_i0_2ucode_offset]), + .din(stall_frn_fdis_iu6_i0_2ucode_d), + .dout(stall_frn_fdis_iu6_i0_2ucode_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_fuse_nop_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i0_fuse_nop_offset]), + .scout(sov[stall_frn_fdis_iu6_i0_fuse_nop_offset]), + .din(stall_frn_fdis_iu6_i0_fuse_nop_d), + .dout(stall_frn_fdis_iu6_i0_fuse_nop_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_rte_lq_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i0_rte_lq_offset]), + .scout(sov[stall_frn_fdis_iu6_i0_rte_lq_offset]), + .din(stall_frn_fdis_iu6_i0_rte_lq_d), + .dout(stall_frn_fdis_iu6_i0_rte_lq_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_rte_sq_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i0_rte_sq_offset]), + .scout(sov[stall_frn_fdis_iu6_i0_rte_sq_offset]), + .din(stall_frn_fdis_iu6_i0_rte_sq_d), + .dout(stall_frn_fdis_iu6_i0_rte_sq_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_rte_fx0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i0_rte_fx0_offset]), + .scout(sov[stall_frn_fdis_iu6_i0_rte_fx0_offset]), + .din(stall_frn_fdis_iu6_i0_rte_fx0_d), + .dout(stall_frn_fdis_iu6_i0_rte_fx0_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_rte_fx1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i0_rte_fx1_offset]), + .scout(sov[stall_frn_fdis_iu6_i0_rte_fx1_offset]), + .din(stall_frn_fdis_iu6_i0_rte_fx1_d), + .dout(stall_frn_fdis_iu6_i0_rte_fx1_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_rte_axu0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i0_rte_axu0_offset]), + .scout(sov[stall_frn_fdis_iu6_i0_rte_axu0_offset]), + .din(stall_frn_fdis_iu6_i0_rte_axu0_d), + .dout(stall_frn_fdis_iu6_i0_rte_axu0_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_rte_axu1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i0_rte_axu1_offset]), + .scout(sov[stall_frn_fdis_iu6_i0_rte_axu1_offset]), + .din(stall_frn_fdis_iu6_i0_rte_axu1_d), + .dout(stall_frn_fdis_iu6_i0_rte_axu1_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_valop_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i0_valop_offset]), + .scout(sov[stall_frn_fdis_iu6_i0_valop_offset]), + .din(stall_frn_fdis_iu6_i0_valop_d), + .dout(stall_frn_fdis_iu6_i0_valop_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_ord_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i0_ord_offset]), + .scout(sov[stall_frn_fdis_iu6_i0_ord_offset]), + .din(stall_frn_fdis_iu6_i0_ord_d), + .dout(stall_frn_fdis_iu6_i0_ord_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_cord_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i0_cord_offset]), + .scout(sov[stall_frn_fdis_iu6_i0_cord_offset]), + .din(stall_frn_fdis_iu6_i0_cord_d), + .dout(stall_frn_fdis_iu6_i0_cord_l2) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) stall_frn_fdis_iu6_i0_error_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i0_error_offset:stall_frn_fdis_iu6_i0_error_offset + 3 - 1]), + .scout(sov[stall_frn_fdis_iu6_i0_error_offset:stall_frn_fdis_iu6_i0_error_offset + 3 - 1]), + .din(stall_frn_fdis_iu6_i0_error_d), + .dout(stall_frn_fdis_iu6_i0_error_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_btb_entry_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i0_btb_entry_offset]), + .scout(sov[stall_frn_fdis_iu6_i0_btb_entry_offset]), + .din(stall_frn_fdis_iu6_i0_btb_entry_d), + .dout(stall_frn_fdis_iu6_i0_btb_entry_l2) + ); + + + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) stall_frn_fdis_iu6_i0_btb_hist_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i0_btb_hist_offset:stall_frn_fdis_iu6_i0_btb_hist_offset + 2 - 1]), + .scout(sov[stall_frn_fdis_iu6_i0_btb_hist_offset:stall_frn_fdis_iu6_i0_btb_hist_offset + 2 - 1]), + .din(stall_frn_fdis_iu6_i0_btb_hist_d), + .dout(stall_frn_fdis_iu6_i0_btb_hist_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_bta_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i0_bta_val_offset]), + .scout(sov[stall_frn_fdis_iu6_i0_bta_val_offset]), + .din(stall_frn_fdis_iu6_i0_bta_val_d), + .dout(stall_frn_fdis_iu6_i0_bta_val_l2) + ); + + + tri_rlmreg_p #(.WIDTH(20), .INIT(0)) stall_frn_fdis_iu6_i0_fusion_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i0_fusion_offset:stall_frn_fdis_iu6_i0_fusion_offset + 20 - 1]), + .scout(sov[stall_frn_fdis_iu6_i0_fusion_offset:stall_frn_fdis_iu6_i0_fusion_offset + 20 - 1]), + .din(stall_frn_fdis_iu6_i0_fusion_d), + .dout(stall_frn_fdis_iu6_i0_fusion_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_spec_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i0_spec_offset]), + .scout(sov[stall_frn_fdis_iu6_i0_spec_offset]), + .din(stall_frn_fdis_iu6_i0_spec_d), + .dout(stall_frn_fdis_iu6_i0_spec_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_type_fp_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i0_type_fp_offset]), + .scout(sov[stall_frn_fdis_iu6_i0_type_fp_offset]), + .din(stall_frn_fdis_iu6_i0_type_fp_d), + .dout(stall_frn_fdis_iu6_i0_type_fp_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_type_ap_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i0_type_ap_offset]), + .scout(sov[stall_frn_fdis_iu6_i0_type_ap_offset]), + .din(stall_frn_fdis_iu6_i0_type_ap_d), + .dout(stall_frn_fdis_iu6_i0_type_ap_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_type_spv_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i0_type_spv_offset]), + .scout(sov[stall_frn_fdis_iu6_i0_type_spv_offset]), + .din(stall_frn_fdis_iu6_i0_type_spv_d), + .dout(stall_frn_fdis_iu6_i0_type_spv_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_type_st_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i0_type_st_offset]), + .scout(sov[stall_frn_fdis_iu6_i0_type_st_offset]), + .din(stall_frn_fdis_iu6_i0_type_st_d), + .dout(stall_frn_fdis_iu6_i0_type_st_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_async_block_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i0_async_block_offset]), + .scout(sov[stall_frn_fdis_iu6_i0_async_block_offset]), + .din(stall_frn_fdis_iu6_i0_async_block_d), + .dout(stall_frn_fdis_iu6_i0_async_block_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_np1_flush_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i0_np1_flush_offset]), + .scout(sov[stall_frn_fdis_iu6_i0_np1_flush_offset]), + .din(stall_frn_fdis_iu6_i0_np1_flush_d), + .dout(stall_frn_fdis_iu6_i0_np1_flush_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_core_block_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i0_core_block_offset]), + .scout(sov[stall_frn_fdis_iu6_i0_core_block_offset]), + .din(stall_frn_fdis_iu6_i0_core_block_d), + .dout(stall_frn_fdis_iu6_i0_core_block_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_isram_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i0_isram_offset]), + .scout(sov[stall_frn_fdis_iu6_i0_isram_offset]), + .din(stall_frn_fdis_iu6_i0_isram_d), + .dout(stall_frn_fdis_iu6_i0_isram_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_isload_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i0_isload_offset]), + .scout(sov[stall_frn_fdis_iu6_i0_isload_offset]), + .din(stall_frn_fdis_iu6_i0_isload_d), + .dout(stall_frn_fdis_iu6_i0_isload_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_isstore_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i0_isstore_offset]), + .scout(sov[stall_frn_fdis_iu6_i0_isstore_offset]), + .din(stall_frn_fdis_iu6_i0_isstore_d), + .dout(stall_frn_fdis_iu6_i0_isstore_l2) + ); + + + tri_rlmreg_p #(.WIDTH(32), .INIT(0)) stall_frn_fdis_iu6_i0_instr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i0_instr_offset:stall_frn_fdis_iu6_i0_instr_offset + 32 - 1]), + .scout(sov[stall_frn_fdis_iu6_i0_instr_offset:stall_frn_fdis_iu6_i0_instr_offset + 32 - 1]), + .din(stall_frn_fdis_iu6_i0_instr_d), + .dout(stall_frn_fdis_iu6_i0_instr_l2) + ); + + + tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) stall_frn_fdis_iu6_i0_ifar_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i0_ifar_offset:stall_frn_fdis_iu6_i0_ifar_offset + (`EFF_IFAR_WIDTH) - 1]), + .scout(sov[stall_frn_fdis_iu6_i0_ifar_offset:stall_frn_fdis_iu6_i0_ifar_offset + (`EFF_IFAR_WIDTH) - 1]), + .din(stall_frn_fdis_iu6_i0_ifar_d), + .dout(stall_frn_fdis_iu6_i0_ifar_l2) + ); + + + tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) stall_frn_fdis_iu6_i0_bta_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i0_bta_offset:stall_frn_fdis_iu6_i0_bta_offset + (`EFF_IFAR_WIDTH) - 1]), + .scout(sov[stall_frn_fdis_iu6_i0_bta_offset:stall_frn_fdis_iu6_i0_bta_offset + (`EFF_IFAR_WIDTH) - 1]), + .din(stall_frn_fdis_iu6_i0_bta_d), + .dout(stall_frn_fdis_iu6_i0_bta_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_br_pred_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i0_br_pred_offset]), + .scout(sov[stall_frn_fdis_iu6_i0_br_pred_offset]), + .din(stall_frn_fdis_iu6_i0_br_pred_d), + .dout(stall_frn_fdis_iu6_i0_br_pred_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_bh_update_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i0_bh_update_offset]), + .scout(sov[stall_frn_fdis_iu6_i0_bh_update_offset]), + .din(stall_frn_fdis_iu6_i0_bh_update_d), + .dout(stall_frn_fdis_iu6_i0_bh_update_l2) + ); + + + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) stall_frn_fdis_iu6_i0_bh0_hist_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i0_bh0_hist_offset:stall_frn_fdis_iu6_i0_bh0_hist_offset + 2 - 1]), + .scout(sov[stall_frn_fdis_iu6_i0_bh0_hist_offset:stall_frn_fdis_iu6_i0_bh0_hist_offset + 2 - 1]), + .din(stall_frn_fdis_iu6_i0_bh0_hist_d), + .dout(stall_frn_fdis_iu6_i0_bh0_hist_l2) + ); + + + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) stall_frn_fdis_iu6_i0_bh1_hist_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i0_bh1_hist_offset:stall_frn_fdis_iu6_i0_bh1_hist_offset + 2 - 1]), + .scout(sov[stall_frn_fdis_iu6_i0_bh1_hist_offset:stall_frn_fdis_iu6_i0_bh1_hist_offset + 2 - 1]), + .din(stall_frn_fdis_iu6_i0_bh1_hist_d), + .dout(stall_frn_fdis_iu6_i0_bh1_hist_l2) + ); + + + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) stall_frn_fdis_iu6_i0_bh2_hist_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i0_bh2_hist_offset:stall_frn_fdis_iu6_i0_bh2_hist_offset + 2 - 1]), + .scout(sov[stall_frn_fdis_iu6_i0_bh2_hist_offset:stall_frn_fdis_iu6_i0_bh2_hist_offset + 2 - 1]), + .din(stall_frn_fdis_iu6_i0_bh2_hist_d), + .dout(stall_frn_fdis_iu6_i0_bh2_hist_l2) + ); + + + tri_rlmreg_p #(.WIDTH(18), .INIT(0)) stall_frn_fdis_iu6_i0_gshare_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i0_gshare_offset:stall_frn_fdis_iu6_i0_gshare_offset + 18 - 1]), + .scout(sov[stall_frn_fdis_iu6_i0_gshare_offset:stall_frn_fdis_iu6_i0_gshare_offset + 18 - 1]), + .din(stall_frn_fdis_iu6_i0_gshare_d), + .dout(stall_frn_fdis_iu6_i0_gshare_l2) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) stall_frn_fdis_iu6_i0_ls_ptr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i0_ls_ptr_offset:stall_frn_fdis_iu6_i0_ls_ptr_offset + 3 - 1]), + .scout(sov[stall_frn_fdis_iu6_i0_ls_ptr_offset:stall_frn_fdis_iu6_i0_ls_ptr_offset + 3 - 1]), + .din(stall_frn_fdis_iu6_i0_ls_ptr_d), + .dout(stall_frn_fdis_iu6_i0_ls_ptr_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_match_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i0_match_offset]), + .scout(sov[stall_frn_fdis_iu6_i0_match_offset]), + .din(stall_frn_fdis_iu6_i0_match_d), + .dout(stall_frn_fdis_iu6_i0_match_l2) + ); + + + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) stall_frn_fdis_iu6_i0_ilat_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i0_ilat_offset:stall_frn_fdis_iu6_i0_ilat_offset + 4 - 1]), + .scout(sov[stall_frn_fdis_iu6_i0_ilat_offset:stall_frn_fdis_iu6_i0_ilat_offset + 4 - 1]), + .din(stall_frn_fdis_iu6_i0_ilat_d), + .dout(stall_frn_fdis_iu6_i0_ilat_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_t1_v_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i0_t1_v_offset]), + .scout(sov[stall_frn_fdis_iu6_i0_t1_v_offset]), + .din(stall_frn_fdis_iu6_i0_t1_v_d), + .dout(stall_frn_fdis_iu6_i0_t1_v_l2) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) stall_frn_fdis_iu6_i0_t1_t_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i0_t1_t_offset:stall_frn_fdis_iu6_i0_t1_t_offset + 3 - 1]), + .scout(sov[stall_frn_fdis_iu6_i0_t1_t_offset:stall_frn_fdis_iu6_i0_t1_t_offset + 3 - 1]), + .din(stall_frn_fdis_iu6_i0_t1_t_d), + .dout(stall_frn_fdis_iu6_i0_t1_t_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) stall_frn_fdis_iu6_i0_t1_a_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i0_t1_a_offset:stall_frn_fdis_iu6_i0_t1_a_offset + `GPR_POOL_ENC - 1]), + .scout(sov[stall_frn_fdis_iu6_i0_t1_a_offset:stall_frn_fdis_iu6_i0_t1_a_offset + `GPR_POOL_ENC - 1]), + .din(stall_frn_fdis_iu6_i0_t1_a_d), + .dout(stall_frn_fdis_iu6_i0_t1_a_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) stall_frn_fdis_iu6_i0_t1_p_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i0_t1_p_offset:stall_frn_fdis_iu6_i0_t1_p_offset + `GPR_POOL_ENC - 1]), + .scout(sov[stall_frn_fdis_iu6_i0_t1_p_offset:stall_frn_fdis_iu6_i0_t1_p_offset + `GPR_POOL_ENC - 1]), + .din(stall_frn_fdis_iu6_i0_t1_p_d), + .dout(stall_frn_fdis_iu6_i0_t1_p_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_t2_v_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i0_t2_v_offset]), + .scout(sov[stall_frn_fdis_iu6_i0_t2_v_offset]), + .din(stall_frn_fdis_iu6_i0_t2_v_d), + .dout(stall_frn_fdis_iu6_i0_t2_v_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) stall_frn_fdis_iu6_i0_t2_a_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i0_t2_a_offset:stall_frn_fdis_iu6_i0_t2_a_offset + `GPR_POOL_ENC - 1]), + .scout(sov[stall_frn_fdis_iu6_i0_t2_a_offset:stall_frn_fdis_iu6_i0_t2_a_offset + `GPR_POOL_ENC - 1]), + .din(stall_frn_fdis_iu6_i0_t2_a_d), + .dout(stall_frn_fdis_iu6_i0_t2_a_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) stall_frn_fdis_iu6_i0_t2_p_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i0_t2_p_offset:stall_frn_fdis_iu6_i0_t2_p_offset + `GPR_POOL_ENC - 1]), + .scout(sov[stall_frn_fdis_iu6_i0_t2_p_offset:stall_frn_fdis_iu6_i0_t2_p_offset + `GPR_POOL_ENC - 1]), + .din(stall_frn_fdis_iu6_i0_t2_p_d), + .dout(stall_frn_fdis_iu6_i0_t2_p_l2) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) stall_frn_fdis_iu6_i0_t2_t_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i0_t2_t_offset:stall_frn_fdis_iu6_i0_t2_t_offset + 3 - 1]), + .scout(sov[stall_frn_fdis_iu6_i0_t2_t_offset:stall_frn_fdis_iu6_i0_t2_t_offset + 3 - 1]), + .din(stall_frn_fdis_iu6_i0_t2_t_d), + .dout(stall_frn_fdis_iu6_i0_t2_t_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_t3_v_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i0_t3_v_offset]), + .scout(sov[stall_frn_fdis_iu6_i0_t3_v_offset]), + .din(stall_frn_fdis_iu6_i0_t3_v_d), + .dout(stall_frn_fdis_iu6_i0_t3_v_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) stall_frn_fdis_iu6_i0_t3_a_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i0_t3_a_offset:stall_frn_fdis_iu6_i0_t3_a_offset + `GPR_POOL_ENC - 1]), + .scout(sov[stall_frn_fdis_iu6_i0_t3_a_offset:stall_frn_fdis_iu6_i0_t3_a_offset + `GPR_POOL_ENC - 1]), + .din(stall_frn_fdis_iu6_i0_t3_a_d), + .dout(stall_frn_fdis_iu6_i0_t3_a_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) stall_frn_fdis_iu6_i0_t3_p_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i0_t3_p_offset:stall_frn_fdis_iu6_i0_t3_p_offset + `GPR_POOL_ENC - 1]), + .scout(sov[stall_frn_fdis_iu6_i0_t3_p_offset:stall_frn_fdis_iu6_i0_t3_p_offset + `GPR_POOL_ENC - 1]), + .din(stall_frn_fdis_iu6_i0_t3_p_d), + .dout(stall_frn_fdis_iu6_i0_t3_p_l2) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) stall_frn_fdis_iu6_i0_t3_t_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i0_t3_t_offset:stall_frn_fdis_iu6_i0_t3_t_offset + 3 - 1]), + .scout(sov[stall_frn_fdis_iu6_i0_t3_t_offset:stall_frn_fdis_iu6_i0_t3_t_offset + 3 - 1]), + .din(stall_frn_fdis_iu6_i0_t3_t_d), + .dout(stall_frn_fdis_iu6_i0_t3_t_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_s1_v_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i0_s1_v_offset]), + .scout(sov[stall_frn_fdis_iu6_i0_s1_v_offset]), + .din(stall_frn_fdis_iu6_i0_s1_v_d), + .dout(stall_frn_fdis_iu6_i0_s1_v_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) stall_frn_fdis_iu6_i0_s1_a_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i0_s1_a_offset:stall_frn_fdis_iu6_i0_s1_a_offset + `GPR_POOL_ENC - 1]), + .scout(sov[stall_frn_fdis_iu6_i0_s1_a_offset:stall_frn_fdis_iu6_i0_s1_a_offset + `GPR_POOL_ENC - 1]), + .din(stall_frn_fdis_iu6_i0_s1_a_d), + .dout(stall_frn_fdis_iu6_i0_s1_a_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) stall_frn_fdis_iu6_i0_s1_p_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i0_s1_p_offset:stall_frn_fdis_iu6_i0_s1_p_offset + `GPR_POOL_ENC - 1]), + .scout(sov[stall_frn_fdis_iu6_i0_s1_p_offset:stall_frn_fdis_iu6_i0_s1_p_offset + `GPR_POOL_ENC - 1]), + .din(stall_frn_fdis_iu6_i0_s1_p_d), + .dout(stall_frn_fdis_iu6_i0_s1_p_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) stall_frn_fdis_iu6_i0_s1_itag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i0_s1_itag_offset:stall_frn_fdis_iu6_i0_s1_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[stall_frn_fdis_iu6_i0_s1_itag_offset:stall_frn_fdis_iu6_i0_s1_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(stall_frn_fdis_iu6_i0_s1_itag_d), + .dout(stall_frn_fdis_iu6_i0_s1_itag_l2) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) stall_frn_fdis_iu6_i0_s1_t_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i0_s1_t_offset:stall_frn_fdis_iu6_i0_s1_t_offset + 3 - 1]), + .scout(sov[stall_frn_fdis_iu6_i0_s1_t_offset:stall_frn_fdis_iu6_i0_s1_t_offset + 3 - 1]), + .din(stall_frn_fdis_iu6_i0_s1_t_d), + .dout(stall_frn_fdis_iu6_i0_s1_t_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_s2_v_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i0_s2_v_offset]), + .scout(sov[stall_frn_fdis_iu6_i0_s2_v_offset]), + .din(stall_frn_fdis_iu6_i0_s2_v_d), + .dout(stall_frn_fdis_iu6_i0_s2_v_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) stall_frn_fdis_iu6_i0_s2_a_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i0_s2_a_offset:stall_frn_fdis_iu6_i0_s2_a_offset + `GPR_POOL_ENC - 1]), + .scout(sov[stall_frn_fdis_iu6_i0_s2_a_offset:stall_frn_fdis_iu6_i0_s2_a_offset + `GPR_POOL_ENC - 1]), + .din(stall_frn_fdis_iu6_i0_s2_a_d), + .dout(stall_frn_fdis_iu6_i0_s2_a_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) stall_frn_fdis_iu6_i0_s2_p_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i0_s2_p_offset:stall_frn_fdis_iu6_i0_s2_p_offset + `GPR_POOL_ENC - 1]), + .scout(sov[stall_frn_fdis_iu6_i0_s2_p_offset:stall_frn_fdis_iu6_i0_s2_p_offset + `GPR_POOL_ENC - 1]), + .din(stall_frn_fdis_iu6_i0_s2_p_d), + .dout(stall_frn_fdis_iu6_i0_s2_p_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) stall_frn_fdis_iu6_i0_s2_itag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i0_s2_itag_offset:stall_frn_fdis_iu6_i0_s2_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[stall_frn_fdis_iu6_i0_s2_itag_offset:stall_frn_fdis_iu6_i0_s2_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(stall_frn_fdis_iu6_i0_s2_itag_d), + .dout(stall_frn_fdis_iu6_i0_s2_itag_l2) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) stall_frn_fdis_iu6_i0_s2_t_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i0_s2_t_offset:stall_frn_fdis_iu6_i0_s2_t_offset + 3 - 1]), + .scout(sov[stall_frn_fdis_iu6_i0_s2_t_offset:stall_frn_fdis_iu6_i0_s2_t_offset + 3 - 1]), + .din(stall_frn_fdis_iu6_i0_s2_t_d), + .dout(stall_frn_fdis_iu6_i0_s2_t_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_s3_v_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i0_s3_v_offset]), + .scout(sov[stall_frn_fdis_iu6_i0_s3_v_offset]), + .din(stall_frn_fdis_iu6_i0_s3_v_d), + .dout(stall_frn_fdis_iu6_i0_s3_v_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) stall_frn_fdis_iu6_i0_s3_a_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i0_s3_a_offset:stall_frn_fdis_iu6_i0_s3_a_offset + `GPR_POOL_ENC - 1]), + .scout(sov[stall_frn_fdis_iu6_i0_s3_a_offset:stall_frn_fdis_iu6_i0_s3_a_offset + `GPR_POOL_ENC - 1]), + .din(stall_frn_fdis_iu6_i0_s3_a_d), + .dout(stall_frn_fdis_iu6_i0_s3_a_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) stall_frn_fdis_iu6_i0_s3_p_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i0_s3_p_offset:stall_frn_fdis_iu6_i0_s3_p_offset + `GPR_POOL_ENC - 1]), + .scout(sov[stall_frn_fdis_iu6_i0_s3_p_offset:stall_frn_fdis_iu6_i0_s3_p_offset + `GPR_POOL_ENC - 1]), + .din(stall_frn_fdis_iu6_i0_s3_p_d), + .dout(stall_frn_fdis_iu6_i0_s3_p_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) stall_frn_fdis_iu6_i0_s3_itag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i0_s3_itag_offset:stall_frn_fdis_iu6_i0_s3_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[stall_frn_fdis_iu6_i0_s3_itag_offset:stall_frn_fdis_iu6_i0_s3_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(stall_frn_fdis_iu6_i0_s3_itag_d), + .dout(stall_frn_fdis_iu6_i0_s3_itag_l2) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) stall_frn_fdis_iu6_i0_s3_t_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i0_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i0_s3_t_offset:stall_frn_fdis_iu6_i0_s3_t_offset + 3 - 1]), + .scout(sov[stall_frn_fdis_iu6_i0_s3_t_offset:stall_frn_fdis_iu6_i0_s3_t_offset + 3 - 1]), + .din(stall_frn_fdis_iu6_i0_s3_t_d), + .dout(stall_frn_fdis_iu6_i0_s3_t_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_vld_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i1_vld_offset]), + .scout(sov[stall_frn_fdis_iu6_i1_vld_offset]), + .din(stall_frn_fdis_iu6_i1_vld_d), + .dout(stall_frn_fdis_iu6_i1_vld_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) stall_frn_fdis_iu6_i1_itag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i1_itag_offset:stall_frn_fdis_iu6_i1_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[stall_frn_fdis_iu6_i1_itag_offset:stall_frn_fdis_iu6_i1_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(stall_frn_fdis_iu6_i1_itag_d), + .dout(stall_frn_fdis_iu6_i1_itag_l2) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) stall_frn_fdis_iu6_i1_ucode_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i1_ucode_offset:stall_frn_fdis_iu6_i1_ucode_offset + 3 - 1]), + .scout(sov[stall_frn_fdis_iu6_i1_ucode_offset:stall_frn_fdis_iu6_i1_ucode_offset + 3 - 1]), + .din(stall_frn_fdis_iu6_i1_ucode_d), + .dout(stall_frn_fdis_iu6_i1_ucode_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`UCODE_ENTRIES_ENC), .INIT(0)) stall_frn_fdis_iu6_i1_ucode_cnt_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i1_ucode_cnt_offset:stall_frn_fdis_iu6_i1_ucode_cnt_offset + `UCODE_ENTRIES_ENC - 1]), + .scout(sov[stall_frn_fdis_iu6_i1_ucode_cnt_offset:stall_frn_fdis_iu6_i1_ucode_cnt_offset + `UCODE_ENTRIES_ENC - 1]), + .din(stall_frn_fdis_iu6_i1_ucode_cnt_d), + .dout(stall_frn_fdis_iu6_i1_ucode_cnt_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_fuse_nop_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i1_fuse_nop_offset]), + .scout(sov[stall_frn_fdis_iu6_i1_fuse_nop_offset]), + .din(stall_frn_fdis_iu6_i1_fuse_nop_d), + .dout(stall_frn_fdis_iu6_i1_fuse_nop_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_rte_lq_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i1_rte_lq_offset]), + .scout(sov[stall_frn_fdis_iu6_i1_rte_lq_offset]), + .din(stall_frn_fdis_iu6_i1_rte_lq_d), + .dout(stall_frn_fdis_iu6_i1_rte_lq_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_rte_sq_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i1_rte_sq_offset]), + .scout(sov[stall_frn_fdis_iu6_i1_rte_sq_offset]), + .din(stall_frn_fdis_iu6_i1_rte_sq_d), + .dout(stall_frn_fdis_iu6_i1_rte_sq_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_rte_fx0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i1_rte_fx0_offset]), + .scout(sov[stall_frn_fdis_iu6_i1_rte_fx0_offset]), + .din(stall_frn_fdis_iu6_i1_rte_fx0_d), + .dout(stall_frn_fdis_iu6_i1_rte_fx0_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_rte_fx1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i1_rte_fx1_offset]), + .scout(sov[stall_frn_fdis_iu6_i1_rte_fx1_offset]), + .din(stall_frn_fdis_iu6_i1_rte_fx1_d), + .dout(stall_frn_fdis_iu6_i1_rte_fx1_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_rte_axu0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i1_rte_axu0_offset]), + .scout(sov[stall_frn_fdis_iu6_i1_rte_axu0_offset]), + .din(stall_frn_fdis_iu6_i1_rte_axu0_d), + .dout(stall_frn_fdis_iu6_i1_rte_axu0_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_rte_axu1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i1_rte_axu1_offset]), + .scout(sov[stall_frn_fdis_iu6_i1_rte_axu1_offset]), + .din(stall_frn_fdis_iu6_i1_rte_axu1_d), + .dout(stall_frn_fdis_iu6_i1_rte_axu1_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_valop_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i1_valop_offset]), + .scout(sov[stall_frn_fdis_iu6_i1_valop_offset]), + .din(stall_frn_fdis_iu6_i1_valop_d), + .dout(stall_frn_fdis_iu6_i1_valop_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_ord_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i1_ord_offset]), + .scout(sov[stall_frn_fdis_iu6_i1_ord_offset]), + .din(stall_frn_fdis_iu6_i1_ord_d), + .dout(stall_frn_fdis_iu6_i1_ord_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_cord_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i1_cord_offset]), + .scout(sov[stall_frn_fdis_iu6_i1_cord_offset]), + .din(stall_frn_fdis_iu6_i1_cord_d), + .dout(stall_frn_fdis_iu6_i1_cord_l2) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) stall_frn_fdis_iu6_i1_error_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i1_error_offset:stall_frn_fdis_iu6_i1_error_offset + 3 - 1]), + .scout(sov[stall_frn_fdis_iu6_i1_error_offset:stall_frn_fdis_iu6_i1_error_offset + 3 - 1]), + .din(stall_frn_fdis_iu6_i1_error_d), + .dout(stall_frn_fdis_iu6_i1_error_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_btb_entry_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i1_btb_entry_offset]), + .scout(sov[stall_frn_fdis_iu6_i1_btb_entry_offset]), + .din(stall_frn_fdis_iu6_i1_btb_entry_d), + .dout(stall_frn_fdis_iu6_i1_btb_entry_l2) + ); + + + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) stall_frn_fdis_iu6_i1_btb_hist_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i1_btb_hist_offset:stall_frn_fdis_iu6_i1_btb_hist_offset + 2 - 1]), + .scout(sov[stall_frn_fdis_iu6_i1_btb_hist_offset:stall_frn_fdis_iu6_i1_btb_hist_offset + 2 - 1]), + .din(stall_frn_fdis_iu6_i1_btb_hist_d), + .dout(stall_frn_fdis_iu6_i1_btb_hist_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_bta_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i1_bta_val_offset]), + .scout(sov[stall_frn_fdis_iu6_i1_bta_val_offset]), + .din(stall_frn_fdis_iu6_i1_bta_val_d), + .dout(stall_frn_fdis_iu6_i1_bta_val_l2) + ); + + + tri_rlmreg_p #(.WIDTH(20), .INIT(0)) stall_frn_fdis_iu6_i1_fusion_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i1_fusion_offset:stall_frn_fdis_iu6_i1_fusion_offset + 20 - 1]), + .scout(sov[stall_frn_fdis_iu6_i1_fusion_offset:stall_frn_fdis_iu6_i1_fusion_offset + 20 - 1]), + .din(stall_frn_fdis_iu6_i1_fusion_d), + .dout(stall_frn_fdis_iu6_i1_fusion_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_spec_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i1_spec_offset]), + .scout(sov[stall_frn_fdis_iu6_i1_spec_offset]), + .din(stall_frn_fdis_iu6_i1_spec_d), + .dout(stall_frn_fdis_iu6_i1_spec_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_type_fp_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i1_type_fp_offset]), + .scout(sov[stall_frn_fdis_iu6_i1_type_fp_offset]), + .din(stall_frn_fdis_iu6_i1_type_fp_d), + .dout(stall_frn_fdis_iu6_i1_type_fp_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_type_ap_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i1_type_ap_offset]), + .scout(sov[stall_frn_fdis_iu6_i1_type_ap_offset]), + .din(stall_frn_fdis_iu6_i1_type_ap_d), + .dout(stall_frn_fdis_iu6_i1_type_ap_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_type_spv_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i1_type_spv_offset]), + .scout(sov[stall_frn_fdis_iu6_i1_type_spv_offset]), + .din(stall_frn_fdis_iu6_i1_type_spv_d), + .dout(stall_frn_fdis_iu6_i1_type_spv_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_type_st_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i1_type_st_offset]), + .scout(sov[stall_frn_fdis_iu6_i1_type_st_offset]), + .din(stall_frn_fdis_iu6_i1_type_st_d), + .dout(stall_frn_fdis_iu6_i1_type_st_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_async_block_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i1_async_block_offset]), + .scout(sov[stall_frn_fdis_iu6_i1_async_block_offset]), + .din(stall_frn_fdis_iu6_i1_async_block_d), + .dout(stall_frn_fdis_iu6_i1_async_block_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_np1_flush_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i1_np1_flush_offset]), + .scout(sov[stall_frn_fdis_iu6_i1_np1_flush_offset]), + .din(stall_frn_fdis_iu6_i1_np1_flush_d), + .dout(stall_frn_fdis_iu6_i1_np1_flush_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_core_block_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i1_core_block_offset]), + .scout(sov[stall_frn_fdis_iu6_i1_core_block_offset]), + .din(stall_frn_fdis_iu6_i1_core_block_d), + .dout(stall_frn_fdis_iu6_i1_core_block_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_isram_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i1_isram_offset]), + .scout(sov[stall_frn_fdis_iu6_i1_isram_offset]), + .din(stall_frn_fdis_iu6_i1_isram_d), + .dout(stall_frn_fdis_iu6_i1_isram_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_isload_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i1_isload_offset]), + .scout(sov[stall_frn_fdis_iu6_i1_isload_offset]), + .din(stall_frn_fdis_iu6_i1_isload_d), + .dout(stall_frn_fdis_iu6_i1_isload_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_isstore_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i1_isstore_offset]), + .scout(sov[stall_frn_fdis_iu6_i1_isstore_offset]), + .din(stall_frn_fdis_iu6_i1_isstore_d), + .dout(stall_frn_fdis_iu6_i1_isstore_l2) + ); + + + tri_rlmreg_p #(.WIDTH(32), .INIT(0)) stall_frn_fdis_iu6_i1_instr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i1_instr_offset:stall_frn_fdis_iu6_i1_instr_offset + 32 - 1]), + .scout(sov[stall_frn_fdis_iu6_i1_instr_offset:stall_frn_fdis_iu6_i1_instr_offset + 32 - 1]), + .din(stall_frn_fdis_iu6_i1_instr_d), + .dout(stall_frn_fdis_iu6_i1_instr_l2) + ); + + + tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) stall_frn_fdis_iu6_i1_ifar_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i1_ifar_offset:stall_frn_fdis_iu6_i1_ifar_offset + (`EFF_IFAR_WIDTH) - 1]), + .scout(sov[stall_frn_fdis_iu6_i1_ifar_offset:stall_frn_fdis_iu6_i1_ifar_offset + (`EFF_IFAR_WIDTH) - 1]), + .din(stall_frn_fdis_iu6_i1_ifar_d), + .dout(stall_frn_fdis_iu6_i1_ifar_l2) + ); + + + tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) stall_frn_fdis_iu6_i1_bta_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i1_bta_offset:stall_frn_fdis_iu6_i1_bta_offset + (`EFF_IFAR_WIDTH) - 1]), + .scout(sov[stall_frn_fdis_iu6_i1_bta_offset:stall_frn_fdis_iu6_i1_bta_offset + (`EFF_IFAR_WIDTH) - 1]), + .din(stall_frn_fdis_iu6_i1_bta_d), + .dout(stall_frn_fdis_iu6_i1_bta_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_br_pred_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i1_br_pred_offset]), + .scout(sov[stall_frn_fdis_iu6_i1_br_pred_offset]), + .din(stall_frn_fdis_iu6_i1_br_pred_d), + .dout(stall_frn_fdis_iu6_i1_br_pred_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_bh_update_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i1_bh_update_offset]), + .scout(sov[stall_frn_fdis_iu6_i1_bh_update_offset]), + .din(stall_frn_fdis_iu6_i1_bh_update_d), + .dout(stall_frn_fdis_iu6_i1_bh_update_l2) + ); + + + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) stall_frn_fdis_iu6_i1_bh0_hist_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i1_bh0_hist_offset:stall_frn_fdis_iu6_i1_bh0_hist_offset + 2 - 1]), + .scout(sov[stall_frn_fdis_iu6_i1_bh0_hist_offset:stall_frn_fdis_iu6_i1_bh0_hist_offset + 2 - 1]), + .din(stall_frn_fdis_iu6_i1_bh0_hist_d), + .dout(stall_frn_fdis_iu6_i1_bh0_hist_l2) + ); + + + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) stall_frn_fdis_iu6_i1_bh1_hist_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i1_bh1_hist_offset:stall_frn_fdis_iu6_i1_bh1_hist_offset + 2 - 1]), + .scout(sov[stall_frn_fdis_iu6_i1_bh1_hist_offset:stall_frn_fdis_iu6_i1_bh1_hist_offset + 2 - 1]), + .din(stall_frn_fdis_iu6_i1_bh1_hist_d), + .dout(stall_frn_fdis_iu6_i1_bh1_hist_l2) + ); + + + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) stall_frn_fdis_iu6_i1_bh2_hist_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i1_bh2_hist_offset:stall_frn_fdis_iu6_i1_bh2_hist_offset + 2 - 1]), + .scout(sov[stall_frn_fdis_iu6_i1_bh2_hist_offset:stall_frn_fdis_iu6_i1_bh2_hist_offset + 2 - 1]), + .din(stall_frn_fdis_iu6_i1_bh2_hist_d), + .dout(stall_frn_fdis_iu6_i1_bh2_hist_l2) + ); + + + tri_rlmreg_p #(.WIDTH(18), .INIT(0)) stall_frn_fdis_iu6_i1_gshare_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i1_gshare_offset:stall_frn_fdis_iu6_i1_gshare_offset + 18 - 1]), + .scout(sov[stall_frn_fdis_iu6_i1_gshare_offset:stall_frn_fdis_iu6_i1_gshare_offset + 18 - 1]), + .din(stall_frn_fdis_iu6_i1_gshare_d), + .dout(stall_frn_fdis_iu6_i1_gshare_l2) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) stall_frn_fdis_iu6_i1_ls_ptr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i1_ls_ptr_offset:stall_frn_fdis_iu6_i1_ls_ptr_offset + 3 - 1]), + .scout(sov[stall_frn_fdis_iu6_i1_ls_ptr_offset:stall_frn_fdis_iu6_i1_ls_ptr_offset + 3 - 1]), + .din(stall_frn_fdis_iu6_i1_ls_ptr_d), + .dout(stall_frn_fdis_iu6_i1_ls_ptr_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_match_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i1_match_offset]), + .scout(sov[stall_frn_fdis_iu6_i1_match_offset]), + .din(stall_frn_fdis_iu6_i1_match_d), + .dout(stall_frn_fdis_iu6_i1_match_l2) + ); + + + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) stall_frn_fdis_iu6_i1_ilat_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i1_ilat_offset:stall_frn_fdis_iu6_i1_ilat_offset + 4 - 1]), + .scout(sov[stall_frn_fdis_iu6_i1_ilat_offset:stall_frn_fdis_iu6_i1_ilat_offset + 4 - 1]), + .din(stall_frn_fdis_iu6_i1_ilat_d), + .dout(stall_frn_fdis_iu6_i1_ilat_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_t1_v_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i1_t1_v_offset]), + .scout(sov[stall_frn_fdis_iu6_i1_t1_v_offset]), + .din(stall_frn_fdis_iu6_i1_t1_v_d), + .dout(stall_frn_fdis_iu6_i1_t1_v_l2) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) stall_frn_fdis_iu6_i1_t1_t_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i1_t1_t_offset:stall_frn_fdis_iu6_i1_t1_t_offset + 3 - 1]), + .scout(sov[stall_frn_fdis_iu6_i1_t1_t_offset:stall_frn_fdis_iu6_i1_t1_t_offset + 3 - 1]), + .din(stall_frn_fdis_iu6_i1_t1_t_d), + .dout(stall_frn_fdis_iu6_i1_t1_t_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) stall_frn_fdis_iu6_i1_t1_a_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i1_t1_a_offset:stall_frn_fdis_iu6_i1_t1_a_offset + `GPR_POOL_ENC - 1]), + .scout(sov[stall_frn_fdis_iu6_i1_t1_a_offset:stall_frn_fdis_iu6_i1_t1_a_offset + `GPR_POOL_ENC - 1]), + .din(stall_frn_fdis_iu6_i1_t1_a_d), + .dout(stall_frn_fdis_iu6_i1_t1_a_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) stall_frn_fdis_iu6_i1_t1_p_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i1_t1_p_offset:stall_frn_fdis_iu6_i1_t1_p_offset + `GPR_POOL_ENC - 1]), + .scout(sov[stall_frn_fdis_iu6_i1_t1_p_offset:stall_frn_fdis_iu6_i1_t1_p_offset + `GPR_POOL_ENC - 1]), + .din(stall_frn_fdis_iu6_i1_t1_p_d), + .dout(stall_frn_fdis_iu6_i1_t1_p_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_t2_v_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i1_t2_v_offset]), + .scout(sov[stall_frn_fdis_iu6_i1_t2_v_offset]), + .din(stall_frn_fdis_iu6_i1_t2_v_d), + .dout(stall_frn_fdis_iu6_i1_t2_v_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) stall_frn_fdis_iu6_i1_t2_a_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i1_t2_a_offset:stall_frn_fdis_iu6_i1_t2_a_offset + `GPR_POOL_ENC - 1]), + .scout(sov[stall_frn_fdis_iu6_i1_t2_a_offset:stall_frn_fdis_iu6_i1_t2_a_offset + `GPR_POOL_ENC - 1]), + .din(stall_frn_fdis_iu6_i1_t2_a_d), + .dout(stall_frn_fdis_iu6_i1_t2_a_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) stall_frn_fdis_iu6_i1_t2_p_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i1_t2_p_offset:stall_frn_fdis_iu6_i1_t2_p_offset + `GPR_POOL_ENC - 1]), + .scout(sov[stall_frn_fdis_iu6_i1_t2_p_offset:stall_frn_fdis_iu6_i1_t2_p_offset + `GPR_POOL_ENC - 1]), + .din(stall_frn_fdis_iu6_i1_t2_p_d), + .dout(stall_frn_fdis_iu6_i1_t2_p_l2) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) stall_frn_fdis_iu6_i1_t2_t_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i1_t2_t_offset:stall_frn_fdis_iu6_i1_t2_t_offset + 3 - 1]), + .scout(sov[stall_frn_fdis_iu6_i1_t2_t_offset:stall_frn_fdis_iu6_i1_t2_t_offset + 3 - 1]), + .din(stall_frn_fdis_iu6_i1_t2_t_d), + .dout(stall_frn_fdis_iu6_i1_t2_t_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_t3_v_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i1_t3_v_offset]), + .scout(sov[stall_frn_fdis_iu6_i1_t3_v_offset]), + .din(stall_frn_fdis_iu6_i1_t3_v_d), + .dout(stall_frn_fdis_iu6_i1_t3_v_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) stall_frn_fdis_iu6_i1_t3_a_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i1_t3_a_offset:stall_frn_fdis_iu6_i1_t3_a_offset + `GPR_POOL_ENC - 1]), + .scout(sov[stall_frn_fdis_iu6_i1_t3_a_offset:stall_frn_fdis_iu6_i1_t3_a_offset + `GPR_POOL_ENC - 1]), + .din(stall_frn_fdis_iu6_i1_t3_a_d), + .dout(stall_frn_fdis_iu6_i1_t3_a_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) stall_frn_fdis_iu6_i1_t3_p_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i1_t3_p_offset:stall_frn_fdis_iu6_i1_t3_p_offset + `GPR_POOL_ENC - 1]), + .scout(sov[stall_frn_fdis_iu6_i1_t3_p_offset:stall_frn_fdis_iu6_i1_t3_p_offset + `GPR_POOL_ENC - 1]), + .din(stall_frn_fdis_iu6_i1_t3_p_d), + .dout(stall_frn_fdis_iu6_i1_t3_p_l2) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) stall_frn_fdis_iu6_i1_t3_t_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i1_t3_t_offset:stall_frn_fdis_iu6_i1_t3_t_offset + 3 - 1]), + .scout(sov[stall_frn_fdis_iu6_i1_t3_t_offset:stall_frn_fdis_iu6_i1_t3_t_offset + 3 - 1]), + .din(stall_frn_fdis_iu6_i1_t3_t_d), + .dout(stall_frn_fdis_iu6_i1_t3_t_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_s1_v_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i1_s1_v_offset]), + .scout(sov[stall_frn_fdis_iu6_i1_s1_v_offset]), + .din(stall_frn_fdis_iu6_i1_s1_v_d), + .dout(stall_frn_fdis_iu6_i1_s1_v_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) stall_frn_fdis_iu6_i1_s1_a_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i1_s1_a_offset:stall_frn_fdis_iu6_i1_s1_a_offset + `GPR_POOL_ENC - 1]), + .scout(sov[stall_frn_fdis_iu6_i1_s1_a_offset:stall_frn_fdis_iu6_i1_s1_a_offset + `GPR_POOL_ENC - 1]), + .din(stall_frn_fdis_iu6_i1_s1_a_d), + .dout(stall_frn_fdis_iu6_i1_s1_a_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) stall_frn_fdis_iu6_i1_s1_p_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i1_s1_p_offset:stall_frn_fdis_iu6_i1_s1_p_offset + `GPR_POOL_ENC - 1]), + .scout(sov[stall_frn_fdis_iu6_i1_s1_p_offset:stall_frn_fdis_iu6_i1_s1_p_offset + `GPR_POOL_ENC - 1]), + .din(stall_frn_fdis_iu6_i1_s1_p_d), + .dout(stall_frn_fdis_iu6_i1_s1_p_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) stall_frn_fdis_iu6_i1_s1_itag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i1_s1_itag_offset:stall_frn_fdis_iu6_i1_s1_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[stall_frn_fdis_iu6_i1_s1_itag_offset:stall_frn_fdis_iu6_i1_s1_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(stall_frn_fdis_iu6_i1_s1_itag_d), + .dout(stall_frn_fdis_iu6_i1_s1_itag_l2) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) stall_frn_fdis_iu6_i1_s1_t_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i1_s1_t_offset:stall_frn_fdis_iu6_i1_s1_t_offset + 3 - 1]), + .scout(sov[stall_frn_fdis_iu6_i1_s1_t_offset:stall_frn_fdis_iu6_i1_s1_t_offset + 3 - 1]), + .din(stall_frn_fdis_iu6_i1_s1_t_d), + .dout(stall_frn_fdis_iu6_i1_s1_t_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_s1_dep_hit_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i1_s1_dep_hit_offset]), + .scout(sov[stall_frn_fdis_iu6_i1_s1_dep_hit_offset]), + .din(stall_frn_fdis_iu6_i1_s1_dep_hit_d), + .dout(stall_frn_fdis_iu6_i1_s1_dep_hit_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_s2_v_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i1_s2_v_offset]), + .scout(sov[stall_frn_fdis_iu6_i1_s2_v_offset]), + .din(stall_frn_fdis_iu6_i1_s2_v_d), + .dout(stall_frn_fdis_iu6_i1_s2_v_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) stall_frn_fdis_iu6_i1_s2_a_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i1_s2_a_offset:stall_frn_fdis_iu6_i1_s2_a_offset + `GPR_POOL_ENC - 1]), + .scout(sov[stall_frn_fdis_iu6_i1_s2_a_offset:stall_frn_fdis_iu6_i1_s2_a_offset + `GPR_POOL_ENC - 1]), + .din(stall_frn_fdis_iu6_i1_s2_a_d), + .dout(stall_frn_fdis_iu6_i1_s2_a_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) stall_frn_fdis_iu6_i1_s2_p_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i1_s2_p_offset:stall_frn_fdis_iu6_i1_s2_p_offset + `GPR_POOL_ENC - 1]), + .scout(sov[stall_frn_fdis_iu6_i1_s2_p_offset:stall_frn_fdis_iu6_i1_s2_p_offset + `GPR_POOL_ENC - 1]), + .din(stall_frn_fdis_iu6_i1_s2_p_d), + .dout(stall_frn_fdis_iu6_i1_s2_p_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) stall_frn_fdis_iu6_i1_s2_itag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i1_s2_itag_offset:stall_frn_fdis_iu6_i1_s2_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[stall_frn_fdis_iu6_i1_s2_itag_offset:stall_frn_fdis_iu6_i1_s2_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(stall_frn_fdis_iu6_i1_s2_itag_d), + .dout(stall_frn_fdis_iu6_i1_s2_itag_l2) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) stall_frn_fdis_iu6_i1_s2_t_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i1_s2_t_offset:stall_frn_fdis_iu6_i1_s2_t_offset + 3 - 1]), + .scout(sov[stall_frn_fdis_iu6_i1_s2_t_offset:stall_frn_fdis_iu6_i1_s2_t_offset + 3 - 1]), + .din(stall_frn_fdis_iu6_i1_s2_t_d), + .dout(stall_frn_fdis_iu6_i1_s2_t_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_s2_dep_hit_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i1_s2_dep_hit_offset]), + .scout(sov[stall_frn_fdis_iu6_i1_s2_dep_hit_offset]), + .din(stall_frn_fdis_iu6_i1_s2_dep_hit_d), + .dout(stall_frn_fdis_iu6_i1_s2_dep_hit_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_s3_v_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i1_s3_v_offset]), + .scout(sov[stall_frn_fdis_iu6_i1_s3_v_offset]), + .din(stall_frn_fdis_iu6_i1_s3_v_d), + .dout(stall_frn_fdis_iu6_i1_s3_v_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) stall_frn_fdis_iu6_i1_s3_a_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i1_s3_a_offset:stall_frn_fdis_iu6_i1_s3_a_offset + `GPR_POOL_ENC - 1]), + .scout(sov[stall_frn_fdis_iu6_i1_s3_a_offset:stall_frn_fdis_iu6_i1_s3_a_offset + `GPR_POOL_ENC - 1]), + .din(stall_frn_fdis_iu6_i1_s3_a_d), + .dout(stall_frn_fdis_iu6_i1_s3_a_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) stall_frn_fdis_iu6_i1_s3_p_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i1_s3_p_offset:stall_frn_fdis_iu6_i1_s3_p_offset + `GPR_POOL_ENC - 1]), + .scout(sov[stall_frn_fdis_iu6_i1_s3_p_offset:stall_frn_fdis_iu6_i1_s3_p_offset + `GPR_POOL_ENC - 1]), + .din(stall_frn_fdis_iu6_i1_s3_p_d), + .dout(stall_frn_fdis_iu6_i1_s3_p_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) stall_frn_fdis_iu6_i1_s3_itag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i1_s3_itag_offset:stall_frn_fdis_iu6_i1_s3_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[stall_frn_fdis_iu6_i1_s3_itag_offset:stall_frn_fdis_iu6_i1_s3_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(stall_frn_fdis_iu6_i1_s3_itag_d), + .dout(stall_frn_fdis_iu6_i1_s3_itag_l2) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) stall_frn_fdis_iu6_i1_s3_t_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[stall_frn_fdis_iu6_i1_s3_t_offset:stall_frn_fdis_iu6_i1_s3_t_offset + 3 - 1]), + .scout(sov[stall_frn_fdis_iu6_i1_s3_t_offset:stall_frn_fdis_iu6_i1_s3_t_offset + 3 - 1]), + .din(stall_frn_fdis_iu6_i1_s3_t_d), + .dout(stall_frn_fdis_iu6_i1_s3_t_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_s3_dep_hit_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stall_frn_fdis_iu6_i1_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[stall_frn_fdis_iu6_i1_s3_dep_hit_offset]), + .scout(sov[stall_frn_fdis_iu6_i1_s3_dep_hit_offset]), + .din(stall_frn_fdis_iu6_i1_s3_dep_hit_d), + .dout(stall_frn_fdis_iu6_i1_s3_dep_hit_l2) + ); + + //----------------------------------------------- + // performance + //----------------------------------------------- + tri_rlmlatch_p #(.INIT(0)) perf_iu5_stall_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pc_iu_event_bus_enable), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[perf_iu5_stall_offset]), + .scout(sov[perf_iu5_stall_offset]), + .din(perf_iu5_stall_d), + .dout(perf_iu5_stall_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) perf_iu5_cpl_credit_stall_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pc_iu_event_bus_enable), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[perf_iu5_cpl_credit_stall_offset]), + .scout(sov[perf_iu5_cpl_credit_stall_offset]), + .din(perf_iu5_cpl_credit_stall_d), + .dout(perf_iu5_cpl_credit_stall_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) perf_iu5_gpr_credit_stall_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pc_iu_event_bus_enable), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[perf_iu5_gpr_credit_stall_offset]), + .scout(sov[perf_iu5_gpr_credit_stall_offset]), + .din(perf_iu5_gpr_credit_stall_d), + .dout(perf_iu5_gpr_credit_stall_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) perf_iu5_cr_credit_stall_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pc_iu_event_bus_enable), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[perf_iu5_cr_credit_stall_offset]), + .scout(sov[perf_iu5_cr_credit_stall_offset]), + .din(perf_iu5_cr_credit_stall_d), + .dout(perf_iu5_cr_credit_stall_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) perf_iu5_lr_credit_stall_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pc_iu_event_bus_enable), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[perf_iu5_lr_credit_stall_offset]), + .scout(sov[perf_iu5_lr_credit_stall_offset]), + .din(perf_iu5_lr_credit_stall_d), + .dout(perf_iu5_lr_credit_stall_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) perf_iu5_ctr_credit_stall_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pc_iu_event_bus_enable), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[perf_iu5_ctr_credit_stall_offset]), + .scout(sov[perf_iu5_ctr_credit_stall_offset]), + .din(perf_iu5_ctr_credit_stall_d), + .dout(perf_iu5_ctr_credit_stall_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) perf_iu5_xer_credit_stall_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pc_iu_event_bus_enable), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[perf_iu5_xer_credit_stall_offset]), + .scout(sov[perf_iu5_xer_credit_stall_offset]), + .din(perf_iu5_xer_credit_stall_d), + .dout(perf_iu5_xer_credit_stall_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) perf_iu5_br_hold_stall_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pc_iu_event_bus_enable), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[perf_iu5_br_hold_stall_offset]), + .scout(sov[perf_iu5_br_hold_stall_offset]), + .din(perf_iu5_br_hold_stall_d), + .dout(perf_iu5_br_hold_stall_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) perf_iu5_axu_hold_stall_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pc_iu_event_bus_enable), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[perf_iu5_axu_hold_stall_offset]), + .scout(sov[perf_iu5_axu_hold_stall_offset]), + .din(perf_iu5_axu_hold_stall_d), + .dout(perf_iu5_axu_hold_stall_l2) + ); + + + //----------------------------------------------- + // pervasive + //----------------------------------------------- + + tri_plat #(.WIDTH(2)) perv_2to1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + .din({pc_iu_func_sl_thold_2,pc_iu_sg_2}), + .q({pc_iu_func_sl_thold_1,pc_iu_sg_1}) + ); + + + tri_plat #(.WIDTH(2)) perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + .din({pc_iu_func_sl_thold_1,pc_iu_sg_1}), + .q({pc_iu_func_sl_thold_0,pc_iu_sg_0}) + ); + + + tri_lcbor perv_lcbor( + .clkoff_b(clkoff_b), + .thold(pc_iu_func_sl_thold_0), + .sg(pc_iu_sg_0), + .act_dis(act_dis), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b) + ); + + //--------------------------------------------------------------------- + // Scan + //--------------------------------------------------------------------- + assign siv[0:scan_right] = {sov[1:scan_right], func_scan_in}; + assign map_siv[0] = sov[0]; + assign map_siv[1] = map_sov[0]; + assign map_siv[2] = map_sov[1]; + assign map_siv[3] = map_sov[2]; + assign map_siv[4] = map_sov[3]; + assign func_scan_out = map_sov[4]; + +endmodule diff --git a/dev/verilog/work/iuq_rn_map.v b/dev/verilog/work/iuq_rn_map.v new file mode 100755 index 0000000..4a1cf5e --- /dev/null +++ b/dev/verilog/work/iuq_rn_map.v @@ -0,0 +1,684 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//******************************************************************** +//* +//* TITLE: +//* +//* NAME: iuq_rn_map.v +//* +//********************************************************************* + +`include "tri_a2o.vh" + + +module iuq_rn_map #( + parameter ARCHITECTED_REGISTER_DEPTH = 36, + parameter REGISTER_RENAME_DEPTH = 64, + parameter STORAGE_WIDTH = 6) + ( + inout vdd, + inout gnd, + input [0:`NCLK_WIDTH-1] nclk, + input pc_iu_func_sl_thold_0_b, // acts as reset for non-ibm types + input pc_iu_sg_0, + input force_t, + input d_mode, + input delay_lclkr, + input mpw1_b, + input mpw2_b, + input func_scan_in, + output func_scan_out, + + input take_a, + input take_b, + output next_reg_a_val, + output reg [0:STORAGE_WIDTH-1] next_reg_a, + output next_reg_b_val, + output reg [0:STORAGE_WIDTH-1] next_reg_b, + + input [0:STORAGE_WIDTH-1] src1_a, + output reg [0:STORAGE_WIDTH-1] src1_p, + output reg [0:`ITAG_SIZE_ENC-1] src1_itag, + input [0:STORAGE_WIDTH-1] src2_a, + output reg [0:STORAGE_WIDTH-1] src2_p, + output reg [0:`ITAG_SIZE_ENC-1] src2_itag, + input [0:STORAGE_WIDTH-1] src3_a, + output reg [0:STORAGE_WIDTH-1] src3_p, + output reg [0:`ITAG_SIZE_ENC-1] src3_itag, + input [0:STORAGE_WIDTH-1] src4_a, + output [0:STORAGE_WIDTH-1] src4_p, + output [0:`ITAG_SIZE_ENC-1] src4_itag, + input [0:STORAGE_WIDTH-1] src5_a, + output [0:STORAGE_WIDTH-1] src5_p, + output [0:`ITAG_SIZE_ENC-1] src5_itag, + input [0:STORAGE_WIDTH-1] src6_a, + output [0:STORAGE_WIDTH-1] src6_p, + output [0:`ITAG_SIZE_ENC-1] src6_itag, + + input comp_0_wr_val, + input [0:STORAGE_WIDTH-1] comp_0_wr_arc, + input [0:STORAGE_WIDTH-1] comp_0_wr_rename, + input [0:`ITAG_SIZE_ENC-1] comp_0_wr_itag, + + input comp_1_wr_val, + input [0:STORAGE_WIDTH-1] comp_1_wr_arc, + input [0:STORAGE_WIDTH-1] comp_1_wr_rename, + input [0:`ITAG_SIZE_ENC-1] comp_1_wr_itag, + + input spec_0_wr_val, + input spec_0_wr_val_fast, + input [0:STORAGE_WIDTH-1] spec_0_wr_arc, + input [0:STORAGE_WIDTH-1] spec_0_wr_rename, + input [0:`ITAG_SIZE_ENC-1] spec_0_wr_itag, + + input spec_1_dep_hit_s1, + input spec_1_dep_hit_s2, + input spec_1_dep_hit_s3, + input spec_1_wr_val, + input spec_1_wr_val_fast, + input [0:STORAGE_WIDTH-1] spec_1_wr_arc, + input [0:STORAGE_WIDTH-1] spec_1_wr_rename, + input [0:`ITAG_SIZE_ENC-1] spec_1_wr_itag, + + input flush_map + ); + + localparam [0:31] value_1 = 32'h00000001; + localparam [0:31] value_2 = 32'h00000002; + + parameter comp_map_offset = 0; + parameter spec_map_arc_offset = comp_map_offset + STORAGE_WIDTH * ARCHITECTED_REGISTER_DEPTH; + parameter spec_map_itag_offset = spec_map_arc_offset + STORAGE_WIDTH * ARCHITECTED_REGISTER_DEPTH; + parameter buffer_pool_offset = spec_map_itag_offset + `ITAG_SIZE_ENC * ARCHITECTED_REGISTER_DEPTH; + parameter read_ptr_offset = buffer_pool_offset + (REGISTER_RENAME_DEPTH - ARCHITECTED_REGISTER_DEPTH) * STORAGE_WIDTH; + parameter write_ptr_offset = read_ptr_offset + STORAGE_WIDTH; + parameter free_cnt_offset = write_ptr_offset + STORAGE_WIDTH; + parameter pool_free_0_v_offset = free_cnt_offset + STORAGE_WIDTH; + parameter pool_free_0_offset = pool_free_0_v_offset + 1; + parameter pool_free_1_v_offset = pool_free_0_offset + STORAGE_WIDTH; + parameter pool_free_1_offset = pool_free_1_v_offset + 1; + parameter scan_right = pool_free_1_offset + STORAGE_WIDTH - 1; + + // scan + wire [0:scan_right] siv; + wire [0:scan_right] sov; + + wire tidn; + wire tiup; + + wire comp_map_act; + reg [0:STORAGE_WIDTH-1] comp_map_d[0:ARCHITECTED_REGISTER_DEPTH-1]; + wire [0:STORAGE_WIDTH-1] comp_map_l2[0:ARCHITECTED_REGISTER_DEPTH-1]; + wire spec_map_arc_act; + reg [0:STORAGE_WIDTH-1] spec_map_arc_d[0:ARCHITECTED_REGISTER_DEPTH-1]; + wire [0:STORAGE_WIDTH-1] spec_map_arc_l2[0:ARCHITECTED_REGISTER_DEPTH-1]; + wire spec_map_itag_act; + reg [0:`ITAG_SIZE_ENC-1] spec_map_itag_d[0:ARCHITECTED_REGISTER_DEPTH-1]; + wire [0:`ITAG_SIZE_ENC-1] spec_map_itag_l2[0:ARCHITECTED_REGISTER_DEPTH-1]; + reg [0:REGISTER_RENAME_DEPTH-ARCHITECTED_REGISTER_DEPTH-1] buffer_pool_act; + reg [0:STORAGE_WIDTH-1] buffer_pool_d[0:REGISTER_RENAME_DEPTH-ARCHITECTED_REGISTER_DEPTH-1]; + wire [0:STORAGE_WIDTH-1] buffer_pool_l2[0:REGISTER_RENAME_DEPTH-ARCHITECTED_REGISTER_DEPTH-1]; + + wire read_ptr_act; + wire [0:STORAGE_WIDTH-1] read_ptr_d; + wire [0:STORAGE_WIDTH-1] read_ptr_l2; + wire [0:STORAGE_WIDTH-1] read_ptr_inc; + reg [0:REGISTER_RENAME_DEPTH-ARCHITECTED_REGISTER_DEPTH-1] read_ptr; + wire [0:REGISTER_RENAME_DEPTH-ARCHITECTED_REGISTER_DEPTH-1] read_ptr_p1; + + wire write_ptr_act; + wire [0:STORAGE_WIDTH-1] write_ptr_d; + wire [0:STORAGE_WIDTH-1] write_ptr_l2; + reg [0:REGISTER_RENAME_DEPTH-ARCHITECTED_REGISTER_DEPTH-1] write_ptr; + wire [0:REGISTER_RENAME_DEPTH-ARCHITECTED_REGISTER_DEPTH-1] write_ptr_p1; + wire [0:STORAGE_WIDTH-1] write_ptr_value; + + wire free_cnt_act; + reg [0:STORAGE_WIDTH-1] free_cnt_d; + wire [0:STORAGE_WIDTH-1] free_cnt_l2; + + reg pool_free_0_v_d; + wire pool_free_0_v_l2; + reg [0:STORAGE_WIDTH-1] pool_free_0_d; + wire [0:STORAGE_WIDTH-1] pool_free_0_l2; + reg pool_free_1_v_d; + wire pool_free_1_v_l2; + reg [0:STORAGE_WIDTH-1] pool_free_1_d; + wire [0:STORAGE_WIDTH-1] pool_free_1_l2; + + // temporary signal prior to mux select for i0->i1 bypass + reg [0:STORAGE_WIDTH-1] src4_temp_p; + reg [0:STORAGE_WIDTH-1] src5_temp_p; + reg [0:STORAGE_WIDTH-1] src6_temp_p; + reg [0:`ITAG_SIZE_ENC-1] src4_temp_itag; + reg [0:`ITAG_SIZE_ENC-1] src5_temp_itag; + reg [0:`ITAG_SIZE_ENC-1] src6_temp_itag; + + assign tidn = 1'b0; + assign tiup = 1'b1; + + always @( * ) + begin: read_spec_map_arc_proc + integer i; + src1_p = 0; + src2_p = 0; + src3_p = 0; + src4_temp_p = 0; + src5_temp_p = 0; + src6_temp_p = 0; + for (i = 0; i <= ARCHITECTED_REGISTER_DEPTH - 1; i = i + 1) + begin + if (src1_a == i) + src1_p = spec_map_arc_l2[i]; + if (src2_a == i) + src2_p = spec_map_arc_l2[i]; + if (src3_a == i) + src3_p = spec_map_arc_l2[i]; + if (src4_a == i) + src4_temp_p = spec_map_arc_l2[i]; + if (src5_a == i) + src5_temp_p = spec_map_arc_l2[i]; + if (src6_a == i) + src6_temp_p = spec_map_arc_l2[i]; + end + end + + assign src4_p = spec_1_dep_hit_s1 ? spec_0_wr_rename : + src4_temp_p; + assign src5_p = spec_1_dep_hit_s2 ? spec_0_wr_rename : + src5_temp_p; + assign src6_p = spec_1_dep_hit_s3 ? spec_0_wr_rename : + src6_temp_p; + + always @( * ) + begin: read_spec_map_itag_proc + integer i; + src1_itag = 0; + src2_itag = 0; + src3_itag = 0; + src4_temp_itag = 0; + src5_temp_itag = 0; + src6_temp_itag = 0; + for (i = 0; i <= ARCHITECTED_REGISTER_DEPTH - 1; i = i + 1) + begin + if (src1_a == i) + src1_itag = spec_map_itag_l2[i]; + if (src2_a == i) + src2_itag = spec_map_itag_l2[i]; + if (src3_a == i) + src3_itag = spec_map_itag_l2[i]; + if (src4_a == i) + src4_temp_itag = spec_map_itag_l2[i]; + if (src5_a == i) + src5_temp_itag = spec_map_itag_l2[i]; + if (src6_a == i) + src6_temp_itag = spec_map_itag_l2[i]; + end + end + + assign src4_itag = spec_1_dep_hit_s1 ? spec_0_wr_itag : + src4_temp_itag; + assign src5_itag = spec_1_dep_hit_s2 ? spec_0_wr_itag : + src5_temp_itag; + assign src6_itag = spec_1_dep_hit_s3 ? spec_0_wr_itag : + src6_temp_itag; + + assign comp_map_act = comp_0_wr_val | comp_1_wr_val; + + always @( * ) + begin: set_comp_map_proc + integer i; + pool_free_0_v_d = 0; + pool_free_0_d = 0; + pool_free_1_v_d = 0; + pool_free_1_d = 0; + + for (i = 0; i <= ARCHITECTED_REGISTER_DEPTH - 1; i = i + 1) + begin + comp_map_d[i] = comp_map_l2[i]; + if ((comp_0_wr_val == 1'b1) & (comp_1_wr_val == 1'b1) & (comp_0_wr_arc == comp_1_wr_arc) & comp_0_wr_arc == i) + begin + comp_map_d[i] = comp_1_wr_rename; + pool_free_0_v_d = 1'b1; + pool_free_0_d = comp_map_l2[i]; + pool_free_1_v_d = 1'b1; + pool_free_1_d = comp_0_wr_rename; + end + else + begin + if ((comp_0_wr_val == 1'b1) & comp_0_wr_arc == i) + begin + comp_map_d[i] = comp_0_wr_rename; + pool_free_0_v_d = 1'b1; + pool_free_0_d = comp_map_l2[i]; + end + if ((comp_1_wr_val == 1'b1) & comp_1_wr_arc == i) + begin + comp_map_d[i] = comp_1_wr_rename; + pool_free_1_v_d = 1'b1; + pool_free_1_d = comp_map_l2[i]; + end + end + end + end + + assign spec_map_arc_act = flush_map | spec_0_wr_val_fast | spec_1_wr_val_fast; + assign spec_map_itag_act = 1'b1; + + generate + begin : xhdl1 + genvar i; + for (i = 0; i <= ARCHITECTED_REGISTER_DEPTH - 1; i = i + 1) + begin : map_set0 + + always @(flush_map or spec_0_wr_val or spec_0_wr_arc or spec_0_wr_rename or spec_1_wr_val or spec_1_wr_arc or spec_1_wr_rename or spec_map_arc_l2[i] or comp_map_l2[i]) + begin: set_spec_map_arc_proc + spec_map_arc_d[i] = spec_map_arc_l2[i]; + if (flush_map == 1'b1) + spec_map_arc_d[i] = comp_map_l2[i]; + else if ((spec_1_wr_val == 1'b1) & spec_1_wr_arc == i) + spec_map_arc_d[i] = spec_1_wr_rename; + else if ((spec_0_wr_val == 1'b1) & spec_0_wr_arc == i) + spec_map_arc_d[i] = spec_0_wr_rename; + end + + always @(flush_map or spec_0_wr_val or spec_0_wr_arc or spec_0_wr_itag or spec_1_wr_val or spec_1_wr_arc or spec_1_wr_itag or spec_map_itag_l2[i] or comp_0_wr_val or comp_0_wr_itag or comp_1_wr_val or comp_1_wr_itag) + begin: set_spec_map_itag_proc + spec_map_itag_d[i] = spec_map_itag_l2[i]; + if (flush_map == 1'b1) + spec_map_itag_d[i] = {`ITAG_SIZE_ENC{1'b1}}; + else if ((spec_1_wr_val == 1'b1) & spec_1_wr_arc == i) + spec_map_itag_d[i] = spec_1_wr_itag; + else if ((spec_0_wr_val == 1'b1) & spec_0_wr_arc == i) + spec_map_itag_d[i] = spec_0_wr_itag; + else + begin + if ((comp_0_wr_val == 1'b1) & comp_0_wr_itag == spec_map_itag_l2[i]) + spec_map_itag_d[i] = {`ITAG_SIZE_ENC{1'b1}}; + if ((comp_1_wr_val == 1'b1) & comp_1_wr_itag == spec_map_itag_l2[i]) + spec_map_itag_d[i] = {`ITAG_SIZE_ENC{1'b1}}; + end + end + end + end + endgenerate + + generate + begin : write_ptr_calc + genvar i; + for(i = 0; i <= (REGISTER_RENAME_DEPTH - ARCHITECTED_REGISTER_DEPTH - 1); i = i + 1) + begin : write_ptr_set + always @( * ) + if (write_ptr_l2 == i) + write_ptr[i] = (pool_free_0_v_l2 | pool_free_1_v_l2); + else + write_ptr[i] = 1'b0; + end + end + endgenerate + assign write_ptr_p1 = {REGISTER_RENAME_DEPTH - ARCHITECTED_REGISTER_DEPTH{pool_free_0_v_l2 & pool_free_1_v_l2}} & + ({write_ptr[REGISTER_RENAME_DEPTH-ARCHITECTED_REGISTER_DEPTH-1], write_ptr[0:REGISTER_RENAME_DEPTH-ARCHITECTED_REGISTER_DEPTH-2]}); + + assign write_ptr_value = ({pool_free_0_v_l2, pool_free_1_v_l2} == 2'b01) ? pool_free_1_l2 : + pool_free_0_l2; + generate + begin : xhdl2 + genvar i; + for (i = 0; i <= REGISTER_RENAME_DEPTH - ARCHITECTED_REGISTER_DEPTH - 1; i = i + 1) + begin : buffer_pool_gen + always @( * ) + begin + buffer_pool_act[i] = write_ptr[i] | write_ptr_p1[i]; + buffer_pool_d[i] = ({STORAGE_WIDTH{write_ptr[i]}} & write_ptr_value) | + ({STORAGE_WIDTH{write_ptr_p1[i]}} & pool_free_1_l2); + end + end + end + endgenerate + + iuq_rn_map_inc #(.SIZE(STORAGE_WIDTH), .WRAP(REGISTER_RENAME_DEPTH - ARCHITECTED_REGISTER_DEPTH - 1)) read_ptr_inc0( + .inc({take_a, take_b}), + .i(read_ptr_l2), + .o(read_ptr_inc) + ); + + assign read_ptr_act = take_a | take_b | flush_map; + + assign read_ptr_d = (flush_map == 1'b0) ? read_ptr_inc : + write_ptr_l2; + assign write_ptr_act = pool_free_0_v_l2 | pool_free_1_v_l2; + + + iuq_rn_map_inc #(.SIZE(STORAGE_WIDTH), .WRAP(REGISTER_RENAME_DEPTH - ARCHITECTED_REGISTER_DEPTH - 1)) write_ptr_inc0( + .inc({pool_free_0_v_l2, pool_free_1_v_l2}), + .i(write_ptr_l2), + .o(write_ptr_d) + ); + + assign free_cnt_act = flush_map | take_a | take_b | pool_free_0_v_l2 | pool_free_1_v_l2; + + always @(flush_map or take_a or take_b or pool_free_0_v_l2 or pool_free_1_v_l2 or free_cnt_l2) + begin: free_cnt_proc + free_cnt_d = free_cnt_l2; + + if (flush_map == 1'b1) + free_cnt_d = REGISTER_RENAME_DEPTH - ARCHITECTED_REGISTER_DEPTH; + else + begin + if ((take_a == 1'b0 & (pool_free_0_v_l2 == 1'b1 ^ pool_free_1_v_l2 == 1'b1)) | + (take_a == 1'b1 & take_b == 1'b0 & pool_free_0_v_l2 == 1'b1 & pool_free_1_v_l2 == 1'b1)) + free_cnt_d = free_cnt_l2 + value_1[32-STORAGE_WIDTH:31]; + if (take_a == 1'b0 & pool_free_0_v_l2 == 1'b1 & pool_free_1_v_l2 == 1'b1) + free_cnt_d = free_cnt_l2 + value_2[32-STORAGE_WIDTH:31]; + if ((take_a == 1'b1 & take_b == 1'b0 & pool_free_0_v_l2 == 1'b0 & pool_free_1_v_l2 == 1'b0) | + (take_a == 1'b1 & take_b == 1'b1 & (pool_free_0_v_l2 == 1'b1 ^ pool_free_1_v_l2 == 1'b1))) + free_cnt_d = free_cnt_l2 - value_1[32-STORAGE_WIDTH:31]; + if (take_a == 1'b1 & take_b == 1'b1 & pool_free_0_v_l2 == 1'b0 & pool_free_1_v_l2 == 1'b0) + free_cnt_d = free_cnt_l2 - value_2[32-STORAGE_WIDTH:31]; + end + end + + // Creating 1 hot muxing from pointers + generate + begin : read_ptr_calc + genvar i; + for(i = 0; i <= (REGISTER_RENAME_DEPTH - ARCHITECTED_REGISTER_DEPTH - 1); i = i + 1) + begin : read_ptr_set + + always @( * ) + if (read_ptr_l2 == i) + read_ptr[i] = 1'b1; + else + read_ptr[i] = 1'b0; + end + end + endgenerate + assign read_ptr_p1 = {read_ptr[REGISTER_RENAME_DEPTH - ARCHITECTED_REGISTER_DEPTH - 1], read_ptr[0:REGISTER_RENAME_DEPTH - ARCHITECTED_REGISTER_DEPTH - 2]}; + + // OUTPUTS + assign next_reg_a_val = (~(free_cnt_l2 == 0)); + assign next_reg_b_val = (~(free_cnt_l2 == 1)); + + always @( * ) + begin: next_reg_proc + integer e; + next_reg_a = 0; + next_reg_b = 0; + + for (e = 0; e <= (REGISTER_RENAME_DEPTH-ARCHITECTED_REGISTER_DEPTH-1+1) - 1; e = e + 1) + begin + if (read_ptr[e] == 1'b1) + next_reg_a = buffer_pool_l2[e]; + if (read_ptr_p1[e] == 1'b1) + next_reg_b = buffer_pool_l2[e]; + end + end + + generate + begin : xhdl3 + genvar i; + for (i = 0; i <= ARCHITECTED_REGISTER_DEPTH - 1; i = i + 1) + begin : comp_map0 + + tri_rlmreg_p #(.WIDTH(STORAGE_WIDTH), .INIT(i)) comp_map_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(comp_map_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[comp_map_offset + (STORAGE_WIDTH) * i:comp_map_offset + (STORAGE_WIDTH) * (i + 1) - 1]), + .scout(sov[comp_map_offset + (STORAGE_WIDTH) * i:comp_map_offset + (STORAGE_WIDTH) * (i + 1) - 1]), + .din(comp_map_d[i]), + .dout(comp_map_l2[i]) + ); + end + end + endgenerate + + generate + begin : xhdl4 + genvar i; + for (i = 0; i <= ARCHITECTED_REGISTER_DEPTH - 1; i = i + 1) + begin : spec_map0 + + tri_rlmreg_p #(.WIDTH(STORAGE_WIDTH), .INIT(i)) spec_map_arc_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spec_map_arc_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[spec_map_arc_offset + (STORAGE_WIDTH) * i:(spec_map_arc_offset + (STORAGE_WIDTH) * (i + 1)) - 1]), + .scout(sov[spec_map_arc_offset + (STORAGE_WIDTH) * i:(spec_map_arc_offset + (STORAGE_WIDTH) * (i + 1)) - 1]), + .din(spec_map_arc_d[i]), + .dout(spec_map_arc_l2[i]) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(i)) spec_map_itag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spec_map_itag_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[spec_map_itag_offset + (`ITAG_SIZE_ENC) * i:(spec_map_itag_offset + (`ITAG_SIZE_ENC) * (i + 1)) - 1]), + .scout(sov[spec_map_itag_offset + (`ITAG_SIZE_ENC) * i:(spec_map_itag_offset + (`ITAG_SIZE_ENC) * (i + 1)) - 1]), + .din(spec_map_itag_d[i]), + .dout(spec_map_itag_l2[i]) + ); + end + end + endgenerate + + generate + begin : xhdl5 + genvar i; + for (i = 0; i <= REGISTER_RENAME_DEPTH - ARCHITECTED_REGISTER_DEPTH - 1; i = i + 1) + begin : buffer_pool_lat + + tri_rlmreg_p #(.WIDTH(STORAGE_WIDTH), .INIT((i + ARCHITECTED_REGISTER_DEPTH))) buffer_pool_latch0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(buffer_pool_act[i]), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[buffer_pool_offset + (STORAGE_WIDTH) * i:(buffer_pool_offset + (STORAGE_WIDTH) * (i + 1)) - 1]), + .scout(sov[buffer_pool_offset + (STORAGE_WIDTH) * i:(buffer_pool_offset + (STORAGE_WIDTH) * (i + 1)) - 1]), + .din(buffer_pool_d[i]), + .dout(buffer_pool_l2[i]) + ); + end + end + endgenerate + + + tri_rlmreg_p #(.WIDTH(STORAGE_WIDTH), .INIT(0)) read_ptr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(read_ptr_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[read_ptr_offset:read_ptr_offset + STORAGE_WIDTH - 1]), + .scout(sov[read_ptr_offset:read_ptr_offset + STORAGE_WIDTH - 1]), + .din(read_ptr_d), + .dout(read_ptr_l2) + ); + + + tri_rlmreg_p #(.WIDTH(STORAGE_WIDTH), .INIT(0)) write_ptr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(write_ptr_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[write_ptr_offset:write_ptr_offset + STORAGE_WIDTH - 1]), + .scout(sov[write_ptr_offset:write_ptr_offset + STORAGE_WIDTH - 1]), + .din(write_ptr_d), + .dout(write_ptr_l2) + ); + + + tri_rlmreg_p #(.WIDTH(STORAGE_WIDTH), .INIT(REGISTER_RENAME_DEPTH - ARCHITECTED_REGISTER_DEPTH)) free_cnt_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(free_cnt_act), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[free_cnt_offset:free_cnt_offset + STORAGE_WIDTH - 1]), + .scout(sov[free_cnt_offset:free_cnt_offset + STORAGE_WIDTH - 1]), + .din(free_cnt_d), + .dout(free_cnt_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) pool_free_0_v_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[pool_free_0_v_offset]), + .scout(sov[pool_free_0_v_offset]), + .din(pool_free_0_v_d), + .dout(pool_free_0_v_l2) + ); + + + tri_rlmreg_p #(.WIDTH(STORAGE_WIDTH), .INIT(0)) pool_free_0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[pool_free_0_offset:pool_free_0_offset + STORAGE_WIDTH - 1]), + .scout(sov[pool_free_0_offset:pool_free_0_offset + STORAGE_WIDTH - 1]), + .din(pool_free_0_d), + .dout(pool_free_0_l2) + ); + + + tri_rlmlatch_p #(.INIT(0)) pool_free_1_v_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[pool_free_1_v_offset]), + .scout(sov[pool_free_1_v_offset]), + .din(pool_free_1_v_d), + .dout(pool_free_1_v_l2) + ); + + + tri_rlmreg_p #(.WIDTH(STORAGE_WIDTH), .INIT(0)) pool_free_1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b), + .d_mode(d_mode), + .sg(pc_iu_sg_0), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scin(siv[pool_free_1_offset:pool_free_1_offset + STORAGE_WIDTH - 1]), + .scout(sov[pool_free_1_offset:pool_free_1_offset + STORAGE_WIDTH - 1]), + .din(pool_free_1_d), + .dout(pool_free_1_l2) + ); + + //--------------------------------------------------------------------- + // Scan + //--------------------------------------------------------------------- + assign siv[0:scan_right] = {sov[1:scan_right], func_scan_in}; + assign func_scan_out = sov[0]; + +endmodule diff --git a/dev/verilog/work/iuq_rn_map_inc.v b/dev/verilog/work/iuq_rn_map_inc.v new file mode 100755 index 0000000..d270006 --- /dev/null +++ b/dev/verilog/work/iuq_rn_map_inc.v @@ -0,0 +1,85 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//***************************************************************************** +// Description: Saturating Incrementer +// +//***************************************************************************** + +`include "tri_a2o.vh" + + +module iuq_rn_map_inc #( + parameter SIZE = 7, + parameter WRAP = 40) + ( + inc, + i, + o + ); + input [0:1] inc; + input [0:SIZE-1] i; + + output [0:SIZE-1] o; + + localparam [0:31] value_1 = 32'h00000001; + + wire [0:SIZE] a; + wire [0:SIZE] b; + wire [0:SIZE] rslt; + wire rollover; + wire rollover_m1; + wire inc_1; + wire inc_2; + wire [0:1] wrap_sel; + + // Increment by 1 or 2. + // Go back to zero at WRAP + // Flip bit zero when a rollover occurs + // eg 0...39, 64..103 + + assign a = {i[0:SIZE - 1], inc[1]}; + assign b = {{SIZE-1{1'b0}}, inc[0], inc[1]}; + assign rslt = a + b; + + assign rollover = i[0:SIZE - 1] == WRAP; + assign rollover_m1 = i[0:SIZE - 1] == WRAP - 1; + + assign inc_1 = inc[0] ^ inc[1]; + assign inc_2 = inc[0] & inc[1]; + + assign wrap_sel[0] = (rollover & inc_1) | (rollover_m1 & inc_2); + assign wrap_sel[1] = rollover & inc_2; + + assign o[0:SIZE - 1] = (wrap_sel[0:1] == 2'b10) ? {SIZE{1'b0}} : + (wrap_sel[0:1] == 2'b01) ? value_1[32-SIZE:31] : + rslt[0:SIZE - 1]; + +endmodule diff --git a/dev/verilog/work/iuq_rn_top.v b/dev/verilog/work/iuq_rn_top.v new file mode 100755 index 0000000..4ca0ab6 --- /dev/null +++ b/dev/verilog/work/iuq_rn_top.v @@ -0,0 +1,980 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//******************************************************************** +//* +//* TITLE: +//* +//* NAME: iuq_rn_top.vhdl +//* +//********************************************************************* + +`include "tri_a2o.vh" + + +module iuq_rn_top( + inout vdd, + inout gnd, + input [0:`NCLK_WIDTH-1] nclk, + input pc_iu_func_sl_thold_2, // acts as reset for non-ibm types + input pc_iu_sg_2, + input clkoff_b, + input act_dis, + input tc_ac_ccflush_dc, + input d_mode, + input delay_lclkr, + input mpw1_b, + input mpw2_b, + input [0:1] func_scan_in, + output [0:1] func_scan_out, + + //------------------------------- + // Performance interface with I$ + //------------------------------- + input pc_iu_event_bus_enable, + output perf_iu5_stall, + output perf_iu5_cpl_credit_stall, + output perf_iu5_gpr_credit_stall, + output perf_iu5_cr_credit_stall, + output perf_iu5_lr_credit_stall, + output perf_iu5_ctr_credit_stall, + output perf_iu5_xer_credit_stall, + output perf_iu5_br_hold_stall, + output perf_iu5_axu_hold_stall, + + //----------------------------- + // Inputs to rename from decode + //----------------------------- + input fdec_frn_iu5_i0_vld, + input [0:2] fdec_frn_iu5_i0_ucode, + input fdec_frn_iu5_i0_2ucode, + input fdec_frn_iu5_i0_fuse_nop, + input fdec_frn_iu5_i0_rte_lq, + input fdec_frn_iu5_i0_rte_sq, + input fdec_frn_iu5_i0_rte_fx0, + input fdec_frn_iu5_i0_rte_fx1, + input fdec_frn_iu5_i0_rte_axu0, + input fdec_frn_iu5_i0_rte_axu1, + input fdec_frn_iu5_i0_valop, + input fdec_frn_iu5_i0_ord, + input fdec_frn_iu5_i0_cord, + input [0:2] fdec_frn_iu5_i0_error, + input fdec_frn_iu5_i0_btb_entry, + input [0:1] fdec_frn_iu5_i0_btb_hist, + input fdec_frn_iu5_i0_bta_val, + input [0:19] fdec_frn_iu5_i0_fusion, + input fdec_frn_iu5_i0_spec, + input fdec_frn_iu5_i0_type_fp, + input fdec_frn_iu5_i0_type_ap, + input fdec_frn_iu5_i0_type_spv, + input fdec_frn_iu5_i0_type_st, + input fdec_frn_iu5_i0_async_block, + input fdec_frn_iu5_i0_np1_flush, + input fdec_frn_iu5_i0_core_block, + input fdec_frn_iu5_i0_isram, + input fdec_frn_iu5_i0_isload, + input fdec_frn_iu5_i0_isstore, + input [0:31] fdec_frn_iu5_i0_instr, + input [62-`EFF_IFAR_WIDTH:61] fdec_frn_iu5_i0_ifar, + input [62-`EFF_IFAR_WIDTH:61] fdec_frn_iu5_i0_bta, + input fdec_frn_iu5_i0_br_pred, + input fdec_frn_iu5_i0_bh_update, + input [0:1] fdec_frn_iu5_i0_bh0_hist, + input [0:1] fdec_frn_iu5_i0_bh1_hist, + input [0:1] fdec_frn_iu5_i0_bh2_hist, + input [0:17] fdec_frn_iu5_i0_gshare, + input [0:2] fdec_frn_iu5_i0_ls_ptr, + input fdec_frn_iu5_i0_match, + input [0:3] fdec_frn_iu5_i0_ilat, + input fdec_frn_iu5_i0_t1_v, + input [0:2] fdec_frn_iu5_i0_t1_t, + input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i0_t1_a, + input fdec_frn_iu5_i0_t2_v, + input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i0_t2_a, + input [0:2] fdec_frn_iu5_i0_t2_t, + input fdec_frn_iu5_i0_t3_v, + input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i0_t3_a, + input [0:2] fdec_frn_iu5_i0_t3_t, + input fdec_frn_iu5_i0_s1_v, + input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i0_s1_a, + input [0:2] fdec_frn_iu5_i0_s1_t, + input fdec_frn_iu5_i0_s2_v, + input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i0_s2_a, + input [0:2] fdec_frn_iu5_i0_s2_t, + input fdec_frn_iu5_i0_s3_v, + input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i0_s3_a, + input [0:2] fdec_frn_iu5_i0_s3_t, + + input fdec_frn_iu5_i1_vld, + input [0:2] fdec_frn_iu5_i1_ucode, + input fdec_frn_iu5_i1_fuse_nop, + input fdec_frn_iu5_i1_rte_lq, + input fdec_frn_iu5_i1_rte_sq, + input fdec_frn_iu5_i1_rte_fx0, + input fdec_frn_iu5_i1_rte_fx1, + input fdec_frn_iu5_i1_rte_axu0, + input fdec_frn_iu5_i1_rte_axu1, + input fdec_frn_iu5_i1_valop, + input fdec_frn_iu5_i1_ord, + input fdec_frn_iu5_i1_cord, + input [0:2] fdec_frn_iu5_i1_error, + input fdec_frn_iu5_i1_btb_entry, + input [0:1] fdec_frn_iu5_i1_btb_hist, + input fdec_frn_iu5_i1_bta_val, + input [0:19] fdec_frn_iu5_i1_fusion, + input fdec_frn_iu5_i1_spec, + input fdec_frn_iu5_i1_type_fp, + input fdec_frn_iu5_i1_type_ap, + input fdec_frn_iu5_i1_type_spv, + input fdec_frn_iu5_i1_type_st, + input fdec_frn_iu5_i1_async_block, + input fdec_frn_iu5_i1_np1_flush, + input fdec_frn_iu5_i1_core_block, + input fdec_frn_iu5_i1_isram, + input fdec_frn_iu5_i1_isload, + input fdec_frn_iu5_i1_isstore, + input [0:31] fdec_frn_iu5_i1_instr, + input [62-`EFF_IFAR_WIDTH:61] fdec_frn_iu5_i1_ifar, + input [62-`EFF_IFAR_WIDTH:61] fdec_frn_iu5_i1_bta, + input fdec_frn_iu5_i1_br_pred, + input fdec_frn_iu5_i1_bh_update, + input [0:1] fdec_frn_iu5_i1_bh0_hist, + input [0:1] fdec_frn_iu5_i1_bh1_hist, + input [0:1] fdec_frn_iu5_i1_bh2_hist, + input [0:17] fdec_frn_iu5_i1_gshare, + input [0:2] fdec_frn_iu5_i1_ls_ptr, + input fdec_frn_iu5_i1_match, + input [0:3] fdec_frn_iu5_i1_ilat, + input fdec_frn_iu5_i1_t1_v, + input [0:2] fdec_frn_iu5_i1_t1_t, + input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i1_t1_a, + input fdec_frn_iu5_i1_t2_v, + input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i1_t2_a, + input [0:2] fdec_frn_iu5_i1_t2_t, + input fdec_frn_iu5_i1_t3_v, + input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i1_t3_a, + input [0:2] fdec_frn_iu5_i1_t3_t, + input fdec_frn_iu5_i1_s1_v, + input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i1_s1_a, + input [0:2] fdec_frn_iu5_i1_s1_t, + input fdec_frn_iu5_i1_s2_v, + input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i1_s2_a, + input [0:2] fdec_frn_iu5_i1_s2_t, + input fdec_frn_iu5_i1_s3_v, + input [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i1_s3_a, + input [0:2] fdec_frn_iu5_i1_s3_t, + + //----------------------------- + // SPR values + //----------------------------- + input spr_high_pri_mask, + input spr_cpcr_we, + input [0:6] spr_cpcr3_cp_cnt, + input [0:6] spr_cpcr5_cp_cnt, + input spr_single_issue, + + //----------------------------- + // Stall to decode + //----------------------------- + output frn_fdec_iu5_stall, + + //----------------------------- + // Stall from dispatch + //----------------------------- + input fdis_frn_iu6_stall, + + //---------------------------- + // Completion Interface + //---------------------------- + input cp_rn_i0_axu_exception_val, + input [0:3] cp_rn_i0_axu_exception, + input cp_rn_i1_axu_exception_val, + input [0:3] cp_rn_i1_axu_exception, + input cp_rn_empty, + input cp_rn_i0_v, + input [0:`ITAG_SIZE_ENC-1] cp_rn_i0_itag, + input cp_rn_i0_t1_v, + input [0:2] cp_rn_i0_t1_t, + input [0:`GPR_POOL_ENC-1] cp_rn_i0_t1_p, + input [0:`GPR_POOL_ENC-1] cp_rn_i0_t1_a, + input cp_rn_i0_t2_v, + input [0:2] cp_rn_i0_t2_t, + input [0:`GPR_POOL_ENC-1] cp_rn_i0_t2_p, + input [0:`GPR_POOL_ENC-1] cp_rn_i0_t2_a, + input cp_rn_i0_t3_v, + input [0:2] cp_rn_i0_t3_t, + input [0:`GPR_POOL_ENC-1] cp_rn_i0_t3_p, + input [0:`GPR_POOL_ENC-1] cp_rn_i0_t3_a, + + input cp_rn_i1_v, + input [0:`ITAG_SIZE_ENC-1] cp_rn_i1_itag, + input cp_rn_i1_t1_v, + input [0:2] cp_rn_i1_t1_t, + input [0:`GPR_POOL_ENC-1] cp_rn_i1_t1_p, + input [0:`GPR_POOL_ENC-1] cp_rn_i1_t1_a, + input cp_rn_i1_t2_v, + input [0:2] cp_rn_i1_t2_t, + input [0:`GPR_POOL_ENC-1] cp_rn_i1_t2_p, + input [0:`GPR_POOL_ENC-1] cp_rn_i1_t2_a, + input cp_rn_i1_t3_v, + input [0:2] cp_rn_i1_t3_t, + input [0:`GPR_POOL_ENC-1] cp_rn_i1_t3_p, + input [0:`GPR_POOL_ENC-1] cp_rn_i1_t3_a, + + input cp_flush, + input cp_flush_into_uc, + input br_iu_redirect, + input cp_rn_uc_credit_free, + + //---------------------------------------------------------------- + // Interface to reservation station - Completion is snooping also + //---------------------------------------------------------------- + output frn_fdis_iu6_i0_vld, + output [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i0_itag, + output [0:2] frn_fdis_iu6_i0_ucode, + output [0:`UCODE_ENTRIES_ENC-1] frn_fdis_iu6_i0_ucode_cnt, + output frn_fdis_iu6_i0_2ucode, + output frn_fdis_iu6_i0_fuse_nop, + output frn_fdis_iu6_i0_rte_lq, + output frn_fdis_iu6_i0_rte_sq, + output frn_fdis_iu6_i0_rte_fx0, + output frn_fdis_iu6_i0_rte_fx1, + output frn_fdis_iu6_i0_rte_axu0, + output frn_fdis_iu6_i0_rte_axu1, + output frn_fdis_iu6_i0_valop, + output frn_fdis_iu6_i0_ord, + output frn_fdis_iu6_i0_cord, + output [0:2] frn_fdis_iu6_i0_error, + output frn_fdis_iu6_i0_btb_entry, + output [0:1] frn_fdis_iu6_i0_btb_hist, + output frn_fdis_iu6_i0_bta_val, + output [0:19] frn_fdis_iu6_i0_fusion, + output frn_fdis_iu6_i0_spec, + output frn_fdis_iu6_i0_type_fp, + output frn_fdis_iu6_i0_type_ap, + output frn_fdis_iu6_i0_type_spv, + output frn_fdis_iu6_i0_type_st, + output frn_fdis_iu6_i0_async_block, + output frn_fdis_iu6_i0_np1_flush, + output frn_fdis_iu6_i0_core_block, + output frn_fdis_iu6_i0_isram, + output frn_fdis_iu6_i0_isload, + output frn_fdis_iu6_i0_isstore, + output [0:31] frn_fdis_iu6_i0_instr, + output [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_i0_ifar, + output [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_i0_bta, + output frn_fdis_iu6_i0_br_pred, + output frn_fdis_iu6_i0_bh_update, + output [0:1] frn_fdis_iu6_i0_bh0_hist, + output [0:1] frn_fdis_iu6_i0_bh1_hist, + output [0:1] frn_fdis_iu6_i0_bh2_hist, + output [0:17] frn_fdis_iu6_i0_gshare, + output [0:2] frn_fdis_iu6_i0_ls_ptr, + output frn_fdis_iu6_i0_match, + output [0:3] frn_fdis_iu6_i0_ilat, + output frn_fdis_iu6_i0_t1_v, + output [0:2] frn_fdis_iu6_i0_t1_t, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t1_a, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t1_p, + output frn_fdis_iu6_i0_t2_v, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t2_a, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t2_p, + output [0:2] frn_fdis_iu6_i0_t2_t, + output frn_fdis_iu6_i0_t3_v, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t3_a, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t3_p, + output [0:2] frn_fdis_iu6_i0_t3_t, + output frn_fdis_iu6_i0_s1_v, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s1_a, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s1_p, + output [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i0_s1_itag, + output [0:2] frn_fdis_iu6_i0_s1_t, + output frn_fdis_iu6_i0_s2_v, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s2_a, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s2_p, + output [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i0_s2_itag, + output [0:2] frn_fdis_iu6_i0_s2_t, + output frn_fdis_iu6_i0_s3_v, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s3_a, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s3_p, + output [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i0_s3_itag, + output [0:2] frn_fdis_iu6_i0_s3_t, + + output frn_fdis_iu6_i1_vld, + output [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i1_itag, + output [0:2] frn_fdis_iu6_i1_ucode, + output [0:`UCODE_ENTRIES_ENC-1] frn_fdis_iu6_i1_ucode_cnt, + output frn_fdis_iu6_i1_fuse_nop, + output frn_fdis_iu6_i1_rte_lq, + output frn_fdis_iu6_i1_rte_sq, + output frn_fdis_iu6_i1_rte_fx0, + output frn_fdis_iu6_i1_rte_fx1, + output frn_fdis_iu6_i1_rte_axu0, + output frn_fdis_iu6_i1_rte_axu1, + output frn_fdis_iu6_i1_valop, + output frn_fdis_iu6_i1_ord, + output frn_fdis_iu6_i1_cord, + output [0:2] frn_fdis_iu6_i1_error, + output frn_fdis_iu6_i1_btb_entry, + output [0:1] frn_fdis_iu6_i1_btb_hist, + output frn_fdis_iu6_i1_bta_val, + output [0:19] frn_fdis_iu6_i1_fusion, + output frn_fdis_iu6_i1_spec, + output frn_fdis_iu6_i1_type_fp, + output frn_fdis_iu6_i1_type_ap, + output frn_fdis_iu6_i1_type_spv, + output frn_fdis_iu6_i1_type_st, + output frn_fdis_iu6_i1_async_block, + output frn_fdis_iu6_i1_np1_flush, + output frn_fdis_iu6_i1_core_block, + output frn_fdis_iu6_i1_isram, + output frn_fdis_iu6_i1_isload, + output frn_fdis_iu6_i1_isstore, + output [0:31] frn_fdis_iu6_i1_instr, + output [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_i1_ifar, + output [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_i1_bta, + output frn_fdis_iu6_i1_br_pred, + output frn_fdis_iu6_i1_bh_update, + output [0:1] frn_fdis_iu6_i1_bh0_hist, + output [0:1] frn_fdis_iu6_i1_bh1_hist, + output [0:1] frn_fdis_iu6_i1_bh2_hist, + output [0:17] frn_fdis_iu6_i1_gshare, + output [0:2] frn_fdis_iu6_i1_ls_ptr, + output frn_fdis_iu6_i1_match, + output [0:3] frn_fdis_iu6_i1_ilat, + output frn_fdis_iu6_i1_t1_v, + output [0:2] frn_fdis_iu6_i1_t1_t, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t1_a, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t1_p, + output frn_fdis_iu6_i1_t2_v, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t2_a, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t2_p, + output [0:2] frn_fdis_iu6_i1_t2_t, + output frn_fdis_iu6_i1_t3_v, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t3_a, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t3_p, + output [0:2] frn_fdis_iu6_i1_t3_t, + output frn_fdis_iu6_i1_s1_v, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s1_a, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s1_p, + output [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i1_s1_itag, + output [0:2] frn_fdis_iu6_i1_s1_t, + output frn_fdis_iu6_i1_s1_dep_hit, + output frn_fdis_iu6_i1_s2_v, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s2_a, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s2_p, + output [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i1_s2_itag, + output [0:2] frn_fdis_iu6_i1_s2_t, + output frn_fdis_iu6_i1_s2_dep_hit, + output frn_fdis_iu6_i1_s3_v, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s3_a, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s3_p, + output [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i1_s3_itag, + output [0:2] frn_fdis_iu6_i1_s3_t, + output frn_fdis_iu6_i1_s3_dep_hit + + ); + + wire au_iu_iu5_stall; + wire iu_au_iu5_send_ok; + wire [0:`ITAG_SIZE_ENC-1] iu_au_iu5_next_itag_i0; + wire [0:`ITAG_SIZE_ENC-1] iu_au_iu5_next_itag_i1; + wire au_iu_iu5_axu0_send_ok; + wire au_iu_iu5_axu1_send_ok; + + wire [0:`GPR_POOL_ENC-1] au_iu_iu5_i0_t1_p; + wire [0:`GPR_POOL_ENC-1] au_iu_iu5_i0_t2_p; + wire [0:`GPR_POOL_ENC-1] au_iu_iu5_i0_t3_p; + wire [0:`GPR_POOL_ENC-1] au_iu_iu5_i0_s1_p; + wire [0:`GPR_POOL_ENC-1] au_iu_iu5_i0_s2_p; + wire [0:`GPR_POOL_ENC-1] au_iu_iu5_i0_s3_p; + wire [0:`ITAG_SIZE_ENC-1] au_iu_iu5_i0_s1_itag; + wire [0:`ITAG_SIZE_ENC-1] au_iu_iu5_i0_s2_itag; + wire [0:`ITAG_SIZE_ENC-1] au_iu_iu5_i0_s3_itag; + wire [0:`GPR_POOL_ENC-1] au_iu_iu5_i1_t1_p; + wire [0:`GPR_POOL_ENC-1] au_iu_iu5_i1_t2_p; + wire [0:`GPR_POOL_ENC-1] au_iu_iu5_i1_t3_p; + wire [0:`GPR_POOL_ENC-1] au_iu_iu5_i1_s1_p; + wire [0:`GPR_POOL_ENC-1] au_iu_iu5_i1_s2_p; + wire [0:`GPR_POOL_ENC-1] au_iu_iu5_i1_s3_p; + wire [0:`ITAG_SIZE_ENC-1] au_iu_iu5_i1_s1_itag; + wire [0:`ITAG_SIZE_ENC-1] au_iu_iu5_i1_s2_itag; + wire [0:`ITAG_SIZE_ENC-1] au_iu_iu5_i1_s3_itag; + wire au_iu_iu5_i1_s1_dep_hit; + wire au_iu_iu5_i1_s2_dep_hit; + wire au_iu_iu5_i1_s3_dep_hit; + + + iuq_rn fx_rn0( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), + .pc_iu_sg_2(pc_iu_sg_2), + .clkoff_b(clkoff_b), + .act_dis(act_dis), + .tc_ac_ccflush_dc(tc_ac_ccflush_dc), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .func_scan_in(func_scan_in[0]), + .func_scan_out(func_scan_out[0]), + + //------------------------------- + // Performance interface with I$ + //------------------------------- + .pc_iu_event_bus_enable(pc_iu_event_bus_enable), + .perf_iu5_stall(perf_iu5_stall), + .perf_iu5_cpl_credit_stall(perf_iu5_cpl_credit_stall), + .perf_iu5_gpr_credit_stall(perf_iu5_gpr_credit_stall), + .perf_iu5_cr_credit_stall(perf_iu5_cr_credit_stall), + .perf_iu5_lr_credit_stall(perf_iu5_lr_credit_stall), + .perf_iu5_ctr_credit_stall(perf_iu5_ctr_credit_stall), + .perf_iu5_xer_credit_stall(perf_iu5_xer_credit_stall), + .perf_iu5_br_hold_stall(perf_iu5_br_hold_stall), + .perf_iu5_axu_hold_stall(perf_iu5_axu_hold_stall), + + //----------------------------- + // Inputs to rename from decode + //----------------------------- + .fdec_frn_iu5_i0_vld(fdec_frn_iu5_i0_vld), + .fdec_frn_iu5_i0_ucode(fdec_frn_iu5_i0_ucode), + .fdec_frn_iu5_i0_2ucode(fdec_frn_iu5_i0_2ucode), + .fdec_frn_iu5_i0_fuse_nop(fdec_frn_iu5_i0_fuse_nop), + .fdec_frn_iu5_i0_rte_lq(fdec_frn_iu5_i0_rte_lq), + .fdec_frn_iu5_i0_rte_sq(fdec_frn_iu5_i0_rte_sq), + .fdec_frn_iu5_i0_rte_fx0(fdec_frn_iu5_i0_rte_fx0), + .fdec_frn_iu5_i0_rte_fx1(fdec_frn_iu5_i0_rte_fx1), + .fdec_frn_iu5_i0_rte_axu0(fdec_frn_iu5_i0_rte_axu0), + .fdec_frn_iu5_i0_rte_axu1(fdec_frn_iu5_i0_rte_axu1), + .fdec_frn_iu5_i0_valop(fdec_frn_iu5_i0_valop), + .fdec_frn_iu5_i0_ord(fdec_frn_iu5_i0_ord), + .fdec_frn_iu5_i0_cord(fdec_frn_iu5_i0_cord), + .fdec_frn_iu5_i0_error(fdec_frn_iu5_i0_error), + .fdec_frn_iu5_i0_btb_entry(fdec_frn_iu5_i0_btb_entry), + .fdec_frn_iu5_i0_btb_hist(fdec_frn_iu5_i0_btb_hist), + .fdec_frn_iu5_i0_bta_val(fdec_frn_iu5_i0_bta_val), + .fdec_frn_iu5_i0_fusion(fdec_frn_iu5_i0_fusion), + .fdec_frn_iu5_i0_spec(fdec_frn_iu5_i0_spec), + .fdec_frn_iu5_i0_type_fp(fdec_frn_iu5_i0_type_fp), + .fdec_frn_iu5_i0_type_ap(fdec_frn_iu5_i0_type_ap), + .fdec_frn_iu5_i0_type_spv(fdec_frn_iu5_i0_type_spv), + .fdec_frn_iu5_i0_type_st(fdec_frn_iu5_i0_type_st), + .fdec_frn_iu5_i0_async_block(fdec_frn_iu5_i0_async_block), + .fdec_frn_iu5_i0_np1_flush(fdec_frn_iu5_i0_np1_flush), + .fdec_frn_iu5_i0_core_block(fdec_frn_iu5_i0_core_block), + .fdec_frn_iu5_i0_isram(fdec_frn_iu5_i0_isram), + .fdec_frn_iu5_i0_isload(fdec_frn_iu5_i0_isload), + .fdec_frn_iu5_i0_isstore(fdec_frn_iu5_i0_isstore), + .fdec_frn_iu5_i0_instr(fdec_frn_iu5_i0_instr), + .fdec_frn_iu5_i0_ifar(fdec_frn_iu5_i0_ifar), + .fdec_frn_iu5_i0_bta(fdec_frn_iu5_i0_bta), + .fdec_frn_iu5_i0_br_pred(fdec_frn_iu5_i0_br_pred), + .fdec_frn_iu5_i0_bh_update(fdec_frn_iu5_i0_bh_update), + .fdec_frn_iu5_i0_bh0_hist(fdec_frn_iu5_i0_bh0_hist), + .fdec_frn_iu5_i0_bh1_hist(fdec_frn_iu5_i0_bh1_hist), + .fdec_frn_iu5_i0_bh2_hist(fdec_frn_iu5_i0_bh2_hist), + .fdec_frn_iu5_i0_gshare(fdec_frn_iu5_i0_gshare), + .fdec_frn_iu5_i0_ls_ptr(fdec_frn_iu5_i0_ls_ptr), + .fdec_frn_iu5_i0_match(fdec_frn_iu5_i0_match), + .fdec_frn_iu5_i0_ilat(fdec_frn_iu5_i0_ilat), + .fdec_frn_iu5_i0_t1_v(fdec_frn_iu5_i0_t1_v), + .fdec_frn_iu5_i0_t1_t(fdec_frn_iu5_i0_t1_t), + .fdec_frn_iu5_i0_t1_a(fdec_frn_iu5_i0_t1_a), + .fdec_frn_iu5_i0_t2_v(fdec_frn_iu5_i0_t2_v), + .fdec_frn_iu5_i0_t2_a(fdec_frn_iu5_i0_t2_a), + .fdec_frn_iu5_i0_t2_t(fdec_frn_iu5_i0_t2_t), + .fdec_frn_iu5_i0_t3_v(fdec_frn_iu5_i0_t3_v), + .fdec_frn_iu5_i0_t3_a(fdec_frn_iu5_i0_t3_a), + .fdec_frn_iu5_i0_t3_t(fdec_frn_iu5_i0_t3_t), + .fdec_frn_iu5_i0_s1_v(fdec_frn_iu5_i0_s1_v), + .fdec_frn_iu5_i0_s1_a(fdec_frn_iu5_i0_s1_a), + .fdec_frn_iu5_i0_s1_t(fdec_frn_iu5_i0_s1_t), + .fdec_frn_iu5_i0_s2_v(fdec_frn_iu5_i0_s2_v), + .fdec_frn_iu5_i0_s2_a(fdec_frn_iu5_i0_s2_a), + .fdec_frn_iu5_i0_s2_t(fdec_frn_iu5_i0_s2_t), + .fdec_frn_iu5_i0_s3_v(fdec_frn_iu5_i0_s3_v), + .fdec_frn_iu5_i0_s3_a(fdec_frn_iu5_i0_s3_a), + .fdec_frn_iu5_i0_s3_t(fdec_frn_iu5_i0_s3_t), + + .fdec_frn_iu5_i1_vld(fdec_frn_iu5_i1_vld), + .fdec_frn_iu5_i1_ucode(fdec_frn_iu5_i1_ucode), + .fdec_frn_iu5_i1_fuse_nop(fdec_frn_iu5_i1_fuse_nop), + .fdec_frn_iu5_i1_rte_lq(fdec_frn_iu5_i1_rte_lq), + .fdec_frn_iu5_i1_rte_sq(fdec_frn_iu5_i1_rte_sq), + .fdec_frn_iu5_i1_rte_fx0(fdec_frn_iu5_i1_rte_fx0), + .fdec_frn_iu5_i1_rte_fx1(fdec_frn_iu5_i1_rte_fx1), + .fdec_frn_iu5_i1_rte_axu0(fdec_frn_iu5_i1_rte_axu0), + .fdec_frn_iu5_i1_rte_axu1(fdec_frn_iu5_i1_rte_axu1), + .fdec_frn_iu5_i1_valop(fdec_frn_iu5_i1_valop), + .fdec_frn_iu5_i1_ord(fdec_frn_iu5_i1_ord), + .fdec_frn_iu5_i1_cord(fdec_frn_iu5_i1_cord), + .fdec_frn_iu5_i1_error(fdec_frn_iu5_i1_error), + .fdec_frn_iu5_i1_btb_entry(fdec_frn_iu5_i1_btb_entry), + .fdec_frn_iu5_i1_btb_hist(fdec_frn_iu5_i1_btb_hist), + .fdec_frn_iu5_i1_bta_val(fdec_frn_iu5_i1_bta_val), + .fdec_frn_iu5_i1_fusion(fdec_frn_iu5_i1_fusion), + .fdec_frn_iu5_i1_spec(fdec_frn_iu5_i1_spec), + .fdec_frn_iu5_i1_type_fp(fdec_frn_iu5_i1_type_fp), + .fdec_frn_iu5_i1_type_ap(fdec_frn_iu5_i1_type_ap), + .fdec_frn_iu5_i1_type_spv(fdec_frn_iu5_i1_type_spv), + .fdec_frn_iu5_i1_type_st(fdec_frn_iu5_i1_type_st), + .fdec_frn_iu5_i1_async_block(fdec_frn_iu5_i1_async_block), + .fdec_frn_iu5_i1_np1_flush(fdec_frn_iu5_i1_np1_flush), + .fdec_frn_iu5_i1_core_block(fdec_frn_iu5_i1_core_block), + .fdec_frn_iu5_i1_isram(fdec_frn_iu5_i1_isram), + .fdec_frn_iu5_i1_isload(fdec_frn_iu5_i1_isload), + .fdec_frn_iu5_i1_isstore(fdec_frn_iu5_i1_isstore), + .fdec_frn_iu5_i1_instr(fdec_frn_iu5_i1_instr), + .fdec_frn_iu5_i1_ifar(fdec_frn_iu5_i1_ifar), + .fdec_frn_iu5_i1_bta(fdec_frn_iu5_i1_bta), + .fdec_frn_iu5_i1_br_pred(fdec_frn_iu5_i1_br_pred), + .fdec_frn_iu5_i1_bh_update(fdec_frn_iu5_i1_bh_update), + .fdec_frn_iu5_i1_bh0_hist(fdec_frn_iu5_i1_bh0_hist), + .fdec_frn_iu5_i1_bh1_hist(fdec_frn_iu5_i1_bh1_hist), + .fdec_frn_iu5_i1_bh2_hist(fdec_frn_iu5_i1_bh2_hist), + .fdec_frn_iu5_i1_gshare(fdec_frn_iu5_i1_gshare), + .fdec_frn_iu5_i1_ls_ptr(fdec_frn_iu5_i1_ls_ptr), + .fdec_frn_iu5_i1_match(fdec_frn_iu5_i1_match), + .fdec_frn_iu5_i1_ilat(fdec_frn_iu5_i1_ilat), + .fdec_frn_iu5_i1_t1_v(fdec_frn_iu5_i1_t1_v), + .fdec_frn_iu5_i1_t1_t(fdec_frn_iu5_i1_t1_t), + .fdec_frn_iu5_i1_t1_a(fdec_frn_iu5_i1_t1_a), + .fdec_frn_iu5_i1_t2_v(fdec_frn_iu5_i1_t2_v), + .fdec_frn_iu5_i1_t2_a(fdec_frn_iu5_i1_t2_a), + .fdec_frn_iu5_i1_t2_t(fdec_frn_iu5_i1_t2_t), + .fdec_frn_iu5_i1_t3_v(fdec_frn_iu5_i1_t3_v), + .fdec_frn_iu5_i1_t3_a(fdec_frn_iu5_i1_t3_a), + .fdec_frn_iu5_i1_t3_t(fdec_frn_iu5_i1_t3_t), + .fdec_frn_iu5_i1_s1_v(fdec_frn_iu5_i1_s1_v), + .fdec_frn_iu5_i1_s1_a(fdec_frn_iu5_i1_s1_a), + .fdec_frn_iu5_i1_s1_t(fdec_frn_iu5_i1_s1_t), + .fdec_frn_iu5_i1_s2_v(fdec_frn_iu5_i1_s2_v), + .fdec_frn_iu5_i1_s2_a(fdec_frn_iu5_i1_s2_a), + .fdec_frn_iu5_i1_s2_t(fdec_frn_iu5_i1_s2_t), + .fdec_frn_iu5_i1_s3_v(fdec_frn_iu5_i1_s3_v), + .fdec_frn_iu5_i1_s3_a(fdec_frn_iu5_i1_s3_a), + .fdec_frn_iu5_i1_s3_t(fdec_frn_iu5_i1_s3_t), + + //----------------------------- + // SPR values + //----------------------------- + .spr_high_pri_mask(spr_high_pri_mask), + .spr_cpcr_we(spr_cpcr_we), + .spr_cpcr3_cp_cnt(spr_cpcr3_cp_cnt), + .spr_cpcr5_cp_cnt(spr_cpcr5_cp_cnt), + .spr_single_issue(spr_single_issue), + + //----------------------------- + // Stall to decode + //----------------------------- + .frn_fdec_iu5_stall(frn_fdec_iu5_stall), + .au_iu_iu5_stall(au_iu_iu5_stall), + + //----------------------------- + // Stall from dispatch + //----------------------------- + .fdis_frn_iu6_stall(fdis_frn_iu6_stall), + + //---------------------------- + // Completion Interface + //---------------------------- + .cp_rn_empty(cp_rn_empty), + .cp_rn_i0_v(cp_rn_i0_v), + .cp_rn_i0_itag(cp_rn_i0_itag), + .cp_rn_i0_t1_v(cp_rn_i0_t1_v), + .cp_rn_i0_t1_t(cp_rn_i0_t1_t), + .cp_rn_i0_t1_p(cp_rn_i0_t1_p), + .cp_rn_i0_t1_a(cp_rn_i0_t1_a), + .cp_rn_i0_t2_v(cp_rn_i0_t2_v), + .cp_rn_i0_t2_t(cp_rn_i0_t2_t), + .cp_rn_i0_t2_p(cp_rn_i0_t2_p), + .cp_rn_i0_t2_a(cp_rn_i0_t2_a), + .cp_rn_i0_t3_v(cp_rn_i0_t3_v), + .cp_rn_i0_t3_t(cp_rn_i0_t3_t), + .cp_rn_i0_t3_p(cp_rn_i0_t3_p), + .cp_rn_i0_t3_a(cp_rn_i0_t3_a), + + .cp_rn_i1_v(cp_rn_i1_v), + .cp_rn_i1_itag(cp_rn_i1_itag), + .cp_rn_i1_t1_v(cp_rn_i1_t1_v), + .cp_rn_i1_t1_t(cp_rn_i1_t1_t), + .cp_rn_i1_t1_p(cp_rn_i1_t1_p), + .cp_rn_i1_t1_a(cp_rn_i1_t1_a), + .cp_rn_i1_t2_v(cp_rn_i1_t2_v), + .cp_rn_i1_t2_t(cp_rn_i1_t2_t), + .cp_rn_i1_t2_p(cp_rn_i1_t2_p), + .cp_rn_i1_t2_a(cp_rn_i1_t2_a), + .cp_rn_i1_t3_v(cp_rn_i1_t3_v), + .cp_rn_i1_t3_t(cp_rn_i1_t3_t), + .cp_rn_i1_t3_p(cp_rn_i1_t3_p), + .cp_rn_i1_t3_a(cp_rn_i1_t3_a), + + .cp_flush(cp_flush), + .cp_flush_into_uc(cp_flush_into_uc), + .br_iu_redirect(br_iu_redirect), + .cp_rn_uc_credit_free(cp_rn_uc_credit_free), + + //---------------------------------------------------------------- + // AXU Interface + //---------------------------------------------------------------- + .iu_au_iu5_send_ok(iu_au_iu5_send_ok), + .iu_au_iu5_next_itag_i0(iu_au_iu5_next_itag_i0), + .iu_au_iu5_next_itag_i1(iu_au_iu5_next_itag_i1), + .au_iu_iu5_axu0_send_ok(au_iu_iu5_axu0_send_ok), + .au_iu_iu5_axu1_send_ok(au_iu_iu5_axu1_send_ok), + + .au_iu_iu5_i0_t1_p(au_iu_iu5_i0_t1_p), + .au_iu_iu5_i0_t2_p(au_iu_iu5_i0_t2_p), + .au_iu_iu5_i0_t3_p(au_iu_iu5_i0_t3_p), + .au_iu_iu5_i0_s1_p(au_iu_iu5_i0_s1_p), + .au_iu_iu5_i0_s2_p(au_iu_iu5_i0_s2_p), + .au_iu_iu5_i0_s3_p(au_iu_iu5_i0_s3_p), + + .au_iu_iu5_i0_s1_itag(au_iu_iu5_i0_s1_itag), + .au_iu_iu5_i0_s2_itag(au_iu_iu5_i0_s2_itag), + .au_iu_iu5_i0_s3_itag(au_iu_iu5_i0_s3_itag), + + .au_iu_iu5_i1_t1_p(au_iu_iu5_i1_t1_p), + .au_iu_iu5_i1_t2_p(au_iu_iu5_i1_t2_p), + .au_iu_iu5_i1_t3_p(au_iu_iu5_i1_t3_p), + .au_iu_iu5_i1_s1_p(au_iu_iu5_i1_s1_p), + .au_iu_iu5_i1_s2_p(au_iu_iu5_i1_s2_p), + .au_iu_iu5_i1_s3_p(au_iu_iu5_i1_s3_p), + + .au_iu_iu5_i1_s1_dep_hit(au_iu_iu5_i1_s1_dep_hit), + .au_iu_iu5_i1_s2_dep_hit(au_iu_iu5_i1_s2_dep_hit), + .au_iu_iu5_i1_s3_dep_hit(au_iu_iu5_i1_s3_dep_hit), + + .au_iu_iu5_i1_s1_itag(au_iu_iu5_i1_s1_itag), + .au_iu_iu5_i1_s2_itag(au_iu_iu5_i1_s2_itag), + .au_iu_iu5_i1_s3_itag(au_iu_iu5_i1_s3_itag), + + //---------------------------------------------------------------- + // Interface to reservation station - Completion is snooping also + //---------------------------------------------------------------- + .frn_fdis_iu6_i0_vld(frn_fdis_iu6_i0_vld), + .frn_fdis_iu6_i0_itag(frn_fdis_iu6_i0_itag), + .frn_fdis_iu6_i0_ucode(frn_fdis_iu6_i0_ucode), + .frn_fdis_iu6_i0_ucode_cnt(frn_fdis_iu6_i0_ucode_cnt), + .frn_fdis_iu6_i0_2ucode(frn_fdis_iu6_i0_2ucode), + .frn_fdis_iu6_i0_fuse_nop(frn_fdis_iu6_i0_fuse_nop), + .frn_fdis_iu6_i0_rte_lq(frn_fdis_iu6_i0_rte_lq), + .frn_fdis_iu6_i0_rte_sq(frn_fdis_iu6_i0_rte_sq), + .frn_fdis_iu6_i0_rte_fx0(frn_fdis_iu6_i0_rte_fx0), + .frn_fdis_iu6_i0_rte_fx1(frn_fdis_iu6_i0_rte_fx1), + .frn_fdis_iu6_i0_rte_axu0(frn_fdis_iu6_i0_rte_axu0), + .frn_fdis_iu6_i0_rte_axu1(frn_fdis_iu6_i0_rte_axu1), + .frn_fdis_iu6_i0_valop(frn_fdis_iu6_i0_valop), + .frn_fdis_iu6_i0_ord(frn_fdis_iu6_i0_ord), + .frn_fdis_iu6_i0_cord(frn_fdis_iu6_i0_cord), + .frn_fdis_iu6_i0_error(frn_fdis_iu6_i0_error), + .frn_fdis_iu6_i0_btb_entry(frn_fdis_iu6_i0_btb_entry), + .frn_fdis_iu6_i0_btb_hist(frn_fdis_iu6_i0_btb_hist), + .frn_fdis_iu6_i0_bta_val(frn_fdis_iu6_i0_bta_val), + .frn_fdis_iu6_i0_fusion(frn_fdis_iu6_i0_fusion), + .frn_fdis_iu6_i0_spec(frn_fdis_iu6_i0_spec), + .frn_fdis_iu6_i0_type_fp(frn_fdis_iu6_i0_type_fp), + .frn_fdis_iu6_i0_type_ap(frn_fdis_iu6_i0_type_ap), + .frn_fdis_iu6_i0_type_spv(frn_fdis_iu6_i0_type_spv), + .frn_fdis_iu6_i0_type_st(frn_fdis_iu6_i0_type_st), + .frn_fdis_iu6_i0_async_block(frn_fdis_iu6_i0_async_block), + .frn_fdis_iu6_i0_np1_flush(frn_fdis_iu6_i0_np1_flush), + .frn_fdis_iu6_i0_core_block(frn_fdis_iu6_i0_core_block), + .frn_fdis_iu6_i0_isram(frn_fdis_iu6_i0_isram), + .frn_fdis_iu6_i0_isload(frn_fdis_iu6_i0_isload), + .frn_fdis_iu6_i0_isstore(frn_fdis_iu6_i0_isstore), + .frn_fdis_iu6_i0_instr(frn_fdis_iu6_i0_instr), + .frn_fdis_iu6_i0_ifar(frn_fdis_iu6_i0_ifar), + .frn_fdis_iu6_i0_bta(frn_fdis_iu6_i0_bta), + .frn_fdis_iu6_i0_br_pred(frn_fdis_iu6_i0_br_pred), + .frn_fdis_iu6_i0_bh_update(frn_fdis_iu6_i0_bh_update), + .frn_fdis_iu6_i0_bh0_hist(frn_fdis_iu6_i0_bh0_hist), + .frn_fdis_iu6_i0_bh1_hist(frn_fdis_iu6_i0_bh1_hist), + .frn_fdis_iu6_i0_bh2_hist(frn_fdis_iu6_i0_bh2_hist), + .frn_fdis_iu6_i0_gshare(frn_fdis_iu6_i0_gshare), + .frn_fdis_iu6_i0_ls_ptr(frn_fdis_iu6_i0_ls_ptr), + .frn_fdis_iu6_i0_match(frn_fdis_iu6_i0_match), + .frn_fdis_iu6_i0_ilat(frn_fdis_iu6_i0_ilat), + .frn_fdis_iu6_i0_t1_v(frn_fdis_iu6_i0_t1_v), + .frn_fdis_iu6_i0_t1_t(frn_fdis_iu6_i0_t1_t), + .frn_fdis_iu6_i0_t1_a(frn_fdis_iu6_i0_t1_a), + .frn_fdis_iu6_i0_t1_p(frn_fdis_iu6_i0_t1_p), + .frn_fdis_iu6_i0_t2_v(frn_fdis_iu6_i0_t2_v), + .frn_fdis_iu6_i0_t2_a(frn_fdis_iu6_i0_t2_a), + .frn_fdis_iu6_i0_t2_p(frn_fdis_iu6_i0_t2_p), + .frn_fdis_iu6_i0_t2_t(frn_fdis_iu6_i0_t2_t), + .frn_fdis_iu6_i0_t3_v(frn_fdis_iu6_i0_t3_v), + .frn_fdis_iu6_i0_t3_a(frn_fdis_iu6_i0_t3_a), + .frn_fdis_iu6_i0_t3_p(frn_fdis_iu6_i0_t3_p), + .frn_fdis_iu6_i0_t3_t(frn_fdis_iu6_i0_t3_t), + .frn_fdis_iu6_i0_s1_v(frn_fdis_iu6_i0_s1_v), + .frn_fdis_iu6_i0_s1_a(frn_fdis_iu6_i0_s1_a), + .frn_fdis_iu6_i0_s1_p(frn_fdis_iu6_i0_s1_p), + .frn_fdis_iu6_i0_s1_itag(frn_fdis_iu6_i0_s1_itag), + .frn_fdis_iu6_i0_s1_t(frn_fdis_iu6_i0_s1_t), + .frn_fdis_iu6_i0_s2_v(frn_fdis_iu6_i0_s2_v), + .frn_fdis_iu6_i0_s2_a(frn_fdis_iu6_i0_s2_a), + .frn_fdis_iu6_i0_s2_p(frn_fdis_iu6_i0_s2_p), + .frn_fdis_iu6_i0_s2_itag(frn_fdis_iu6_i0_s2_itag), + .frn_fdis_iu6_i0_s2_t(frn_fdis_iu6_i0_s2_t), + .frn_fdis_iu6_i0_s3_v(frn_fdis_iu6_i0_s3_v), + .frn_fdis_iu6_i0_s3_a(frn_fdis_iu6_i0_s3_a), + .frn_fdis_iu6_i0_s3_p(frn_fdis_iu6_i0_s3_p), + .frn_fdis_iu6_i0_s3_itag(frn_fdis_iu6_i0_s3_itag), + .frn_fdis_iu6_i0_s3_t(frn_fdis_iu6_i0_s3_t), + + .frn_fdis_iu6_i1_vld(frn_fdis_iu6_i1_vld), + .frn_fdis_iu6_i1_itag(frn_fdis_iu6_i1_itag), + .frn_fdis_iu6_i1_ucode(frn_fdis_iu6_i1_ucode), + .frn_fdis_iu6_i1_ucode_cnt(frn_fdis_iu6_i1_ucode_cnt), + .frn_fdis_iu6_i1_fuse_nop(frn_fdis_iu6_i1_fuse_nop), + .frn_fdis_iu6_i1_rte_lq(frn_fdis_iu6_i1_rte_lq), + .frn_fdis_iu6_i1_rte_sq(frn_fdis_iu6_i1_rte_sq), + .frn_fdis_iu6_i1_rte_fx0(frn_fdis_iu6_i1_rte_fx0), + .frn_fdis_iu6_i1_rte_fx1(frn_fdis_iu6_i1_rte_fx1), + .frn_fdis_iu6_i1_rte_axu0(frn_fdis_iu6_i1_rte_axu0), + .frn_fdis_iu6_i1_rte_axu1(frn_fdis_iu6_i1_rte_axu1), + .frn_fdis_iu6_i1_valop(frn_fdis_iu6_i1_valop), + .frn_fdis_iu6_i1_ord(frn_fdis_iu6_i1_ord), + .frn_fdis_iu6_i1_cord(frn_fdis_iu6_i1_cord), + .frn_fdis_iu6_i1_error(frn_fdis_iu6_i1_error), + .frn_fdis_iu6_i1_btb_entry(frn_fdis_iu6_i1_btb_entry), + .frn_fdis_iu6_i1_btb_hist(frn_fdis_iu6_i1_btb_hist), + .frn_fdis_iu6_i1_bta_val(frn_fdis_iu6_i1_bta_val), + .frn_fdis_iu6_i1_fusion(frn_fdis_iu6_i1_fusion), + .frn_fdis_iu6_i1_spec(frn_fdis_iu6_i1_spec), + .frn_fdis_iu6_i1_type_fp(frn_fdis_iu6_i1_type_fp), + .frn_fdis_iu6_i1_type_ap(frn_fdis_iu6_i1_type_ap), + .frn_fdis_iu6_i1_type_spv(frn_fdis_iu6_i1_type_spv), + .frn_fdis_iu6_i1_type_st(frn_fdis_iu6_i1_type_st), + .frn_fdis_iu6_i1_async_block(frn_fdis_iu6_i1_async_block), + .frn_fdis_iu6_i1_np1_flush(frn_fdis_iu6_i1_np1_flush), + .frn_fdis_iu6_i1_core_block(frn_fdis_iu6_i1_core_block), + .frn_fdis_iu6_i1_isram(frn_fdis_iu6_i1_isram), + .frn_fdis_iu6_i1_isload(frn_fdis_iu6_i1_isload), + .frn_fdis_iu6_i1_isstore(frn_fdis_iu6_i1_isstore), + .frn_fdis_iu6_i1_instr(frn_fdis_iu6_i1_instr), + .frn_fdis_iu6_i1_ifar(frn_fdis_iu6_i1_ifar), + .frn_fdis_iu6_i1_bta(frn_fdis_iu6_i1_bta), + .frn_fdis_iu6_i1_br_pred(frn_fdis_iu6_i1_br_pred), + .frn_fdis_iu6_i1_bh_update(frn_fdis_iu6_i1_bh_update), + .frn_fdis_iu6_i1_bh0_hist(frn_fdis_iu6_i1_bh0_hist), + .frn_fdis_iu6_i1_bh1_hist(frn_fdis_iu6_i1_bh1_hist), + .frn_fdis_iu6_i1_bh2_hist(frn_fdis_iu6_i1_bh2_hist), + .frn_fdis_iu6_i1_gshare(frn_fdis_iu6_i1_gshare), + .frn_fdis_iu6_i1_ls_ptr(frn_fdis_iu6_i1_ls_ptr), + .frn_fdis_iu6_i1_match(frn_fdis_iu6_i1_match), + .frn_fdis_iu6_i1_ilat(frn_fdis_iu6_i1_ilat), + .frn_fdis_iu6_i1_t1_v(frn_fdis_iu6_i1_t1_v), + .frn_fdis_iu6_i1_t1_t(frn_fdis_iu6_i1_t1_t), + .frn_fdis_iu6_i1_t1_a(frn_fdis_iu6_i1_t1_a), + .frn_fdis_iu6_i1_t1_p(frn_fdis_iu6_i1_t1_p), + .frn_fdis_iu6_i1_t2_v(frn_fdis_iu6_i1_t2_v), + .frn_fdis_iu6_i1_t2_a(frn_fdis_iu6_i1_t2_a), + .frn_fdis_iu6_i1_t2_p(frn_fdis_iu6_i1_t2_p), + .frn_fdis_iu6_i1_t2_t(frn_fdis_iu6_i1_t2_t), + .frn_fdis_iu6_i1_t3_v(frn_fdis_iu6_i1_t3_v), + .frn_fdis_iu6_i1_t3_a(frn_fdis_iu6_i1_t3_a), + .frn_fdis_iu6_i1_t3_p(frn_fdis_iu6_i1_t3_p), + .frn_fdis_iu6_i1_t3_t(frn_fdis_iu6_i1_t3_t), + .frn_fdis_iu6_i1_s1_v(frn_fdis_iu6_i1_s1_v), + .frn_fdis_iu6_i1_s1_a(frn_fdis_iu6_i1_s1_a), + .frn_fdis_iu6_i1_s1_p(frn_fdis_iu6_i1_s1_p), + .frn_fdis_iu6_i1_s1_itag(frn_fdis_iu6_i1_s1_itag), + .frn_fdis_iu6_i1_s1_t(frn_fdis_iu6_i1_s1_t), + .frn_fdis_iu6_i1_s1_dep_hit(frn_fdis_iu6_i1_s1_dep_hit), + .frn_fdis_iu6_i1_s2_v(frn_fdis_iu6_i1_s2_v), + .frn_fdis_iu6_i1_s2_a(frn_fdis_iu6_i1_s2_a), + .frn_fdis_iu6_i1_s2_p(frn_fdis_iu6_i1_s2_p), + .frn_fdis_iu6_i1_s2_itag(frn_fdis_iu6_i1_s2_itag), + .frn_fdis_iu6_i1_s2_t(frn_fdis_iu6_i1_s2_t), + .frn_fdis_iu6_i1_s2_dep_hit(frn_fdis_iu6_i1_s2_dep_hit), + .frn_fdis_iu6_i1_s3_v(frn_fdis_iu6_i1_s3_v), + .frn_fdis_iu6_i1_s3_a(frn_fdis_iu6_i1_s3_a), + .frn_fdis_iu6_i1_s3_p(frn_fdis_iu6_i1_s3_p), + .frn_fdis_iu6_i1_s3_itag(frn_fdis_iu6_i1_s3_itag), + .frn_fdis_iu6_i1_s3_t(frn_fdis_iu6_i1_s3_t), + .frn_fdis_iu6_i1_s3_dep_hit(frn_fdis_iu6_i1_s3_dep_hit) + + ); + + + iuq_axu_fu_rn #(.FPR_POOL(`GPR_POOL), .FPR_UCODE_POOL(4), .FPSCR_POOL_ENC(5)) axu_rn0( + .vdd(vdd), // inout power_logic; + .gnd(gnd), // inout power_logic; + .nclk(nclk), // in clk_logic; + .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), // in std_ulogic; acts as reset for non-ibm types + .pc_iu_sg_2(pc_iu_sg_2), // in std_ulogic; + .clkoff_b(clkoff_b), // in std_ulogic; todo + .act_dis(act_dis), // in std_ulogic; todo + .tc_ac_ccflush_dc(tc_ac_ccflush_dc), // in std_ulogic; todo + .d_mode(d_mode), // in std_ulogic; + .delay_lclkr(delay_lclkr), // in std_ulogic; + .mpw1_b(mpw1_b), // in std_ulogic; + .mpw2_b(mpw2_b), // in std_ulogic; + .func_scan_in(func_scan_in[1]), // in std_ulogic; todo: hookup + .func_scan_out(func_scan_out[1]), // out std_ulogic; + + .iu_au_iu5_i0_vld(fdec_frn_iu5_i0_vld), + .iu_au_iu5_i0_ucode(fdec_frn_iu5_i0_ucode), + .iu_au_iu5_i0_rte_lq(fdec_frn_iu5_i0_rte_lq), + .iu_au_iu5_i0_rte_sq(fdec_frn_iu5_i0_rte_sq), + .iu_au_iu5_i0_rte_fx0(fdec_frn_iu5_i0_rte_fx0), + .iu_au_iu5_i0_rte_fx1(fdec_frn_iu5_i0_rte_fx1), + .iu_au_iu5_i0_rte_axu0(fdec_frn_iu5_i0_rte_axu0), + .iu_au_iu5_i0_rte_axu1(fdec_frn_iu5_i0_rte_axu1), + .iu_au_iu5_i0_ord(fdec_frn_iu5_i0_ord), + .iu_au_iu5_i0_cord(fdec_frn_iu5_i0_cord), + .iu_au_iu5_i0_instr(fdec_frn_iu5_i0_instr), + .iu_au_iu5_i0_ifar(fdec_frn_iu5_i0_ifar), + .iu_au_iu5_i0_gshare(fdec_frn_iu5_i0_gshare[0:9]), + .iu_au_iu5_i0_ilat(fdec_frn_iu5_i0_ilat), + .iu_au_iu5_i0_isload(fdec_frn_iu5_i0_isload), + .iu_au_iu5_i0_t1_v(fdec_frn_iu5_i0_t1_v), + .iu_au_iu5_i0_t1_t(fdec_frn_iu5_i0_t1_t), + .iu_au_iu5_i0_t1_a(fdec_frn_iu5_i0_t1_a), + .iu_au_iu5_i0_t2_v(fdec_frn_iu5_i0_t2_v), + .iu_au_iu5_i0_t2_t(fdec_frn_iu5_i0_t2_t), + .iu_au_iu5_i0_t2_a(fdec_frn_iu5_i0_t2_a), + .iu_au_iu5_i0_t3_v(fdec_frn_iu5_i0_t3_v), + .iu_au_iu5_i0_t3_t(fdec_frn_iu5_i0_t3_t), + .iu_au_iu5_i0_t3_a(fdec_frn_iu5_i0_t3_a), + .iu_au_iu5_i0_s1_v(fdec_frn_iu5_i0_s1_v), + .iu_au_iu5_i0_s1_t(fdec_frn_iu5_i0_s1_t), + .iu_au_iu5_i0_s1_a(fdec_frn_iu5_i0_s1_a), + .iu_au_iu5_i0_s2_v(fdec_frn_iu5_i0_s2_v), + .iu_au_iu5_i0_s2_t(fdec_frn_iu5_i0_s2_t), + .iu_au_iu5_i0_s2_a(fdec_frn_iu5_i0_s2_a), + .iu_au_iu5_i0_s3_v(fdec_frn_iu5_i0_s3_v), + .iu_au_iu5_i0_s3_t(fdec_frn_iu5_i0_s3_t), + .iu_au_iu5_i0_s3_a(fdec_frn_iu5_i0_s3_a), + .iu_au_iu5_i1_vld(fdec_frn_iu5_i1_vld), + .iu_au_iu5_i1_ucode(fdec_frn_iu5_i1_ucode), + .iu_au_iu5_i1_rte_lq(fdec_frn_iu5_i1_rte_lq), + .iu_au_iu5_i1_rte_sq(fdec_frn_iu5_i1_rte_sq), + .iu_au_iu5_i1_rte_fx0(fdec_frn_iu5_i1_rte_fx0), + .iu_au_iu5_i1_rte_fx1(fdec_frn_iu5_i1_rte_fx1), + .iu_au_iu5_i1_rte_axu0(fdec_frn_iu5_i1_rte_axu0), + .iu_au_iu5_i1_rte_axu1(fdec_frn_iu5_i1_rte_axu1), + .iu_au_iu5_i1_ord(fdec_frn_iu5_i1_ord), + .iu_au_iu5_i1_cord(fdec_frn_iu5_i1_cord), + .iu_au_iu5_i1_instr(fdec_frn_iu5_i1_instr), + .iu_au_iu5_i1_ifar(fdec_frn_iu5_i1_ifar), + .iu_au_iu5_i1_gshare(fdec_frn_iu5_i1_gshare[0:9]), + .iu_au_iu5_i1_ilat(fdec_frn_iu5_i1_ilat), + .iu_au_iu5_i1_isload(fdec_frn_iu5_i1_isload), + .iu_au_iu5_i1_t1_v(fdec_frn_iu5_i1_t1_v), + .iu_au_iu5_i1_t1_t(fdec_frn_iu5_i1_t1_t), + .iu_au_iu5_i1_t1_a(fdec_frn_iu5_i1_t1_a), + .iu_au_iu5_i1_t2_v(fdec_frn_iu5_i1_t2_v), + .iu_au_iu5_i1_t2_t(fdec_frn_iu5_i1_t2_t), + .iu_au_iu5_i1_t2_a(fdec_frn_iu5_i1_t2_a), + .iu_au_iu5_i1_t3_v(fdec_frn_iu5_i1_t3_v), + .iu_au_iu5_i1_t3_t(fdec_frn_iu5_i1_t3_t), + .iu_au_iu5_i1_t3_a(fdec_frn_iu5_i1_t3_a), + .iu_au_iu5_i1_s1_v(fdec_frn_iu5_i1_s1_v), + .iu_au_iu5_i1_s1_t(fdec_frn_iu5_i1_s1_t), + .iu_au_iu5_i1_s1_a(fdec_frn_iu5_i1_s1_a), + .iu_au_iu5_i1_s2_v(fdec_frn_iu5_i1_s2_v), + .iu_au_iu5_i1_s2_t(fdec_frn_iu5_i1_s2_t), + .iu_au_iu5_i1_s2_a(fdec_frn_iu5_i1_s2_a), + .iu_au_iu5_i1_s3_v(fdec_frn_iu5_i1_s3_v), + .iu_au_iu5_i1_s3_t(fdec_frn_iu5_i1_s3_t), + .iu_au_iu5_i1_s3_a(fdec_frn_iu5_i1_s3_a), + + .spr_single_issue(1'b0), // in std_ulogic; + + .au_iu_iu5_stall(au_iu_iu5_stall), // out std_ulogic; + + .cp_rn_i0_axu_exception_val(cp_rn_i0_axu_exception_val), + .cp_rn_i0_axu_exception(cp_rn_i0_axu_exception), + .cp_rn_i0_itag(cp_rn_i0_itag), + .cp_rn_i0_t1_v(cp_rn_i0_t1_v), // in std_ulogic; + .cp_rn_i0_t1_t(cp_rn_i0_t1_t), // in std_ulogic; + .cp_rn_i0_t1_p(cp_rn_i0_t1_p), // in std_ulogic_vector(0 to FPR_POOL_ENC-1); + .cp_rn_i0_t1_a(cp_rn_i0_t1_a), // in std_ulogic_vector(0 to FPR_POOL_ENC-1); + .cp_rn_i0_t2_v(cp_rn_i0_t2_v), // in std_ulogic; + .cp_rn_i0_t2_t(cp_rn_i0_t2_t), // in std_ulogic_vector(0 to 2); + .cp_rn_i0_t2_p(cp_rn_i0_t2_p), // in std_ulogic_vector(0 to FPR_POOL_ENC-1); + .cp_rn_i0_t2_a(cp_rn_i0_t2_a), // in std_ulogic_vector(0 to FPR_POOL_ENC-1); + .cp_rn_i0_t3_v(cp_rn_i0_t3_v), // in std_ulogic; + .cp_rn_i0_t3_t(cp_rn_i0_t3_t), // in std_ulogic_vector(0 to 2); + .cp_rn_i0_t3_p(cp_rn_i0_t3_p), // in std_ulogic_vector(0 to FPR_POOL_ENC-1); + .cp_rn_i0_t3_a(cp_rn_i0_t3_a), // in std_ulogic_vector(0 to FPR_POOL_ENC-1); + + .cp_rn_i1_axu_exception_val(cp_rn_i1_axu_exception_val), + .cp_rn_i1_axu_exception(cp_rn_i1_axu_exception), + .cp_rn_i1_itag(cp_rn_i1_itag), + .cp_rn_i1_t1_v(cp_rn_i1_t1_v), // in std_ulogic; + .cp_rn_i1_t1_t(cp_rn_i1_t1_t), // in std_ulogic; + .cp_rn_i1_t1_p(cp_rn_i1_t1_p), // in std_ulogic_vector(0 to FPR_POOL_ENC-1); + .cp_rn_i1_t1_a(cp_rn_i1_t1_a), // in std_ulogic_vector(0 to FPR_POOL_ENC-1); + .cp_rn_i1_t2_v(cp_rn_i1_t2_v), // in std_ulogic; + .cp_rn_i1_t2_t(cp_rn_i1_t2_t), // in std_ulogic_vector(0 to 2); + .cp_rn_i1_t2_p(cp_rn_i1_t2_p), // in std_ulogic_vector(0 to FPR_POOL_ENC-1); + .cp_rn_i1_t2_a(cp_rn_i1_t2_a), // in std_ulogic_vector(0 to FPR_POOL_ENC-1); + .cp_rn_i1_t3_v(cp_rn_i1_t3_v), // in std_ulogic; + .cp_rn_i1_t3_t(cp_rn_i1_t3_t), // in std_ulogic_vector(0 to 2); + .cp_rn_i1_t3_p(cp_rn_i1_t3_p), // in std_ulogic_vector(0 to FPR_POOL_ENC-1); + .cp_rn_i1_t3_a(cp_rn_i1_t3_a), // in std_ulogic_vector(0 to FPR_POOL_ENC-1); + + .cp_flush(cp_flush), // in std_ulogic; + .br_iu_redirect(br_iu_redirect), + .iu_au_iu5_send_ok(iu_au_iu5_send_ok), + .iu_au_iu5_next_itag_i0(iu_au_iu5_next_itag_i0), + .iu_au_iu5_next_itag_i1(iu_au_iu5_next_itag_i1), + .au_iu_iu5_axu0_send_ok(au_iu_iu5_axu0_send_ok), + .au_iu_iu5_axu1_send_ok(au_iu_iu5_axu1_send_ok), + .au_iu_iu5_i0_t1_p(au_iu_iu5_i0_t1_p), + .au_iu_iu5_i0_t2_p(au_iu_iu5_i0_t2_p), + .au_iu_iu5_i0_t3_p(au_iu_iu5_i0_t3_p), + .au_iu_iu5_i0_s1_p(au_iu_iu5_i0_s1_p), + .au_iu_iu5_i0_s2_p(au_iu_iu5_i0_s2_p), + .au_iu_iu5_i0_s3_p(au_iu_iu5_i0_s3_p), + .au_iu_iu5_i0_s1_itag(au_iu_iu5_i0_s1_itag), + .au_iu_iu5_i0_s2_itag(au_iu_iu5_i0_s2_itag), + .au_iu_iu5_i0_s3_itag(au_iu_iu5_i0_s3_itag), + .au_iu_iu5_i1_t1_p(au_iu_iu5_i1_t1_p), + .au_iu_iu5_i1_t2_p(au_iu_iu5_i1_t2_p), + .au_iu_iu5_i1_t3_p(au_iu_iu5_i1_t3_p), + .au_iu_iu5_i1_s1_p(au_iu_iu5_i1_s1_p), + .au_iu_iu5_i1_s2_p(au_iu_iu5_i1_s2_p), + .au_iu_iu5_i1_s3_p(au_iu_iu5_i1_s3_p), + .au_iu_iu5_i1_s1_dep_hit(au_iu_iu5_i1_s1_dep_hit), + .au_iu_iu5_i1_s2_dep_hit(au_iu_iu5_i1_s2_dep_hit), + .au_iu_iu5_i1_s3_dep_hit(au_iu_iu5_i1_s3_dep_hit), + .au_iu_iu5_i1_s1_itag(au_iu_iu5_i1_s1_itag), + .au_iu_iu5_i1_s2_itag(au_iu_iu5_i1_s2_itag), + .au_iu_iu5_i1_s3_itag(au_iu_iu5_i1_s3_itag) + ); + +endmodule diff --git a/dev/verilog/work/iuq_slice.v b/dev/verilog/work/iuq_slice.v new file mode 100755 index 0000000..5ed5f69 --- /dev/null +++ b/dev/verilog/work/iuq_slice.v @@ -0,0 +1,1072 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//******************************************************************** +//* +//* TITLE: +//* +//* NAME: iuq_slice.vhdl +//* +//********************************************************************* + +`include "tri_a2o.vh" + + +module iuq_slice( + inout vdd, + inout gnd, + input [0:`NCLK_WIDTH-1] nclk, + input pc_iu_sg_2, + input pc_iu_func_sl_thold_2, + input clkoff_b, + input act_dis, + input tc_ac_ccflush_dc, + input d_mode, + input delay_lclkr, + input mpw1_b, + input mpw2_b, + input [0:6] scan_in, + output [0:6] scan_out, + + //------------------------------- + // Performance interface with I$ + //------------------------------- + input pc_iu_event_bus_enable, + output perf_iu5_stall, + output perf_iu5_cpl_credit_stall, + output perf_iu5_gpr_credit_stall, + output perf_iu5_cr_credit_stall, + output perf_iu5_lr_credit_stall, + output perf_iu5_ctr_credit_stall, + output perf_iu5_xer_credit_stall, + output perf_iu5_br_hold_stall, + output perf_iu5_axu_hold_stall, + + input cp_iu_iu4_flush, + input cp_flush_into_uc, + + input xu_iu_epcr_dgtmi, + input xu_iu_msrp_uclep, + input xu_iu_msr_pr, + input xu_iu_msr_gs, + input xu_iu_msr_ucle, + input xu_iu_ccr2_ucode_dis, + + //----------------------------- + // SPR values + //----------------------------- + input spr_high_pri_mask, + input spr_cpcr_we, + input [0:6] spr_cpcr3_cp_cnt, + input [0:6] spr_cpcr5_cp_cnt, + input spr_single_issue, + input [0:31] spr_dec_mask, + input [0:31] spr_dec_match, + input [0:7] iu_au_config_iucr, + input mm_iu_tlbwe_binv, + + //---------------------------- + // Ifetch with slice + //---------------------------- + output ib_rm_rdy, + input rm_ib_iu3_val, + input [0:35] rm_ib_iu3_instr, + + input [0:3] uc_ib_iu3_invalid, + + output [0:(`IBUFF_DEPTH/4)-1] ib_ic_need_fetch, + + input [62-`EFF_IFAR_WIDTH:61] bp_ib_iu3_ifar, + input [0:3] bp_ib_iu3_val, + input [0:`IBUFF_INSTR_WIDTH-1] bp_ib_iu3_0_instr, + input [0:`IBUFF_INSTR_WIDTH-1] bp_ib_iu3_1_instr, + input [0:`IBUFF_INSTR_WIDTH-1] bp_ib_iu3_2_instr, + input [0:`IBUFF_INSTR_WIDTH-1] bp_ib_iu3_3_instr, + input [62-`EFF_IFAR_WIDTH:61] bp_ib_iu3_bta, + + //---------------------------- + // Ucode interface with IB + //---------------------------- + output ib_uc_rdy, + input [0:1] uc_ib_val, + input uc_ib_done, + input [0:31] uc_ib_instr0, + input [0:31] uc_ib_instr1, + input [62-`EFF_IFAR_WIDTH:61] uc_ib_ifar0, + input [62-`EFF_IFAR_WIDTH:61] uc_ib_ifar1, + input [0:3] uc_ib_ext0, + input [0:3] uc_ib_ext1, + + //---------------------------- + // Completion Interface + //---------------------------- + input cp_rn_i0_axu_exception_val, + input [0:3] cp_rn_i0_axu_exception, + input cp_rn_i1_axu_exception_val, + input [0:3] cp_rn_i1_axu_exception, + input cp_rn_empty, + input cp_rn_i0_v, + input [0:`ITAG_SIZE_ENC-1] cp_rn_i0_itag, + input cp_rn_i0_t1_v, + input [0:2] cp_rn_i0_t1_t, + input [0:`GPR_POOL_ENC-1] cp_rn_i0_t1_p, + input [0:`GPR_POOL_ENC-1] cp_rn_i0_t1_a, + input cp_rn_i0_t2_v, + input [0:2] cp_rn_i0_t2_t, + input [0:`GPR_POOL_ENC-1] cp_rn_i0_t2_p, + input [0:`GPR_POOL_ENC-1] cp_rn_i0_t2_a, + input cp_rn_i0_t3_v, + input [0:2] cp_rn_i0_t3_t, + input [0:`GPR_POOL_ENC-1] cp_rn_i0_t3_p, + input [0:`GPR_POOL_ENC-1] cp_rn_i0_t3_a, + + input cp_rn_i1_v, + input [0:`ITAG_SIZE_ENC-1] cp_rn_i1_itag, + input cp_rn_i1_t1_v, + input [0:2] cp_rn_i1_t1_t, + input [0:`GPR_POOL_ENC-1] cp_rn_i1_t1_p, + input [0:`GPR_POOL_ENC-1] cp_rn_i1_t1_a, + input cp_rn_i1_t2_v, + input [0:2] cp_rn_i1_t2_t, + input [0:`GPR_POOL_ENC-1] cp_rn_i1_t2_p, + input [0:`GPR_POOL_ENC-1] cp_rn_i1_t2_a, + input cp_rn_i1_t3_v, + input [0:2] cp_rn_i1_t3_t, + input [0:`GPR_POOL_ENC-1] cp_rn_i1_t3_p, + input [0:`GPR_POOL_ENC-1] cp_rn_i1_t3_a, + + input iu_flush, + input cp_flush, + input br_iu_redirect, + input uc_ib_iu3_flush_all, + input cp_rn_uc_credit_free, + + //----------------------------- + // Stall from dispatch + //----------------------------- + input fdis_frn_iu6_stall, + + //---------------------------------------------------------------- + // Interface to reservation station - Completion is snooping also + //---------------------------------------------------------------- + output frn_fdis_iu6_i0_vld, + output [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i0_itag, + output [0:2] frn_fdis_iu6_i0_ucode, + output [0:`UCODE_ENTRIES_ENC-1] frn_fdis_iu6_i0_ucode_cnt, + output frn_fdis_iu6_i0_2ucode, + output frn_fdis_iu6_i0_fuse_nop, + output frn_fdis_iu6_i0_rte_lq, + output frn_fdis_iu6_i0_rte_sq, + output frn_fdis_iu6_i0_rte_fx0, + output frn_fdis_iu6_i0_rte_fx1, + output frn_fdis_iu6_i0_rte_axu0, + output frn_fdis_iu6_i0_rte_axu1, + output frn_fdis_iu6_i0_valop, + output frn_fdis_iu6_i0_ord, + output frn_fdis_iu6_i0_cord, + output [0:2] frn_fdis_iu6_i0_error, + output [0:19] frn_fdis_iu6_i0_fusion, + output frn_fdis_iu6_i0_spec, + output frn_fdis_iu6_i0_type_fp, + output frn_fdis_iu6_i0_type_ap, + output frn_fdis_iu6_i0_type_spv, + output frn_fdis_iu6_i0_type_st, + output frn_fdis_iu6_i0_async_block, + output frn_fdis_iu6_i0_np1_flush, + output frn_fdis_iu6_i0_core_block, + output frn_fdis_iu6_i0_isram, + output frn_fdis_iu6_i0_isload, + output frn_fdis_iu6_i0_isstore, + output [0:31] frn_fdis_iu6_i0_instr, + output [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_i0_ifar, + output [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_i0_bta, + output frn_fdis_iu6_i0_br_pred, + output frn_fdis_iu6_i0_bh_update, + output [0:1] frn_fdis_iu6_i0_bh0_hist, + output [0:1] frn_fdis_iu6_i0_bh1_hist, + output [0:1] frn_fdis_iu6_i0_bh2_hist, + output [0:17] frn_fdis_iu6_i0_gshare, + output [0:2] frn_fdis_iu6_i0_ls_ptr, + output frn_fdis_iu6_i0_match, + output frn_fdis_iu6_i0_btb_entry, + output [0:1] frn_fdis_iu6_i0_btb_hist, + output frn_fdis_iu6_i0_bta_val, + output [0:3] frn_fdis_iu6_i0_ilat, + output frn_fdis_iu6_i0_t1_v, + output [0:2] frn_fdis_iu6_i0_t1_t, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t1_a, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t1_p, + output frn_fdis_iu6_i0_t2_v, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t2_a, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t2_p, + output [0:2] frn_fdis_iu6_i0_t2_t, + output frn_fdis_iu6_i0_t3_v, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t3_a, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_t3_p, + output [0:2] frn_fdis_iu6_i0_t3_t, + output frn_fdis_iu6_i0_s1_v, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s1_a, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s1_p, + output [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i0_s1_itag, + output [0:2] frn_fdis_iu6_i0_s1_t, + output frn_fdis_iu6_i0_s2_v, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s2_a, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s2_p, + output [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i0_s2_itag, + output [0:2] frn_fdis_iu6_i0_s2_t, + output frn_fdis_iu6_i0_s3_v, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s3_a, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i0_s3_p, + output [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i0_s3_itag, + output [0:2] frn_fdis_iu6_i0_s3_t, + + output frn_fdis_iu6_i1_vld, + output [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i1_itag, + output [0:2] frn_fdis_iu6_i1_ucode, + output [0:`UCODE_ENTRIES_ENC-1] frn_fdis_iu6_i1_ucode_cnt, + output frn_fdis_iu6_i1_fuse_nop, + output frn_fdis_iu6_i1_rte_lq, + output frn_fdis_iu6_i1_rte_sq, + output frn_fdis_iu6_i1_rte_fx0, + output frn_fdis_iu6_i1_rte_fx1, + output frn_fdis_iu6_i1_rte_axu0, + output frn_fdis_iu6_i1_rte_axu1, + output frn_fdis_iu6_i1_valop, + output frn_fdis_iu6_i1_ord, + output frn_fdis_iu6_i1_cord, + output [0:2] frn_fdis_iu6_i1_error, + output [0:19] frn_fdis_iu6_i1_fusion, + output frn_fdis_iu6_i1_spec, + output frn_fdis_iu6_i1_type_fp, + output frn_fdis_iu6_i1_type_ap, + output frn_fdis_iu6_i1_type_spv, + output frn_fdis_iu6_i1_type_st, + output frn_fdis_iu6_i1_async_block, + output frn_fdis_iu6_i1_np1_flush, + output frn_fdis_iu6_i1_core_block, + output frn_fdis_iu6_i1_isram, + output frn_fdis_iu6_i1_isload, + output frn_fdis_iu6_i1_isstore, + output [0:31] frn_fdis_iu6_i1_instr, + output [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_i1_ifar, + output [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_i1_bta, + output frn_fdis_iu6_i1_br_pred, + output frn_fdis_iu6_i1_bh_update, + output [0:1] frn_fdis_iu6_i1_bh0_hist, + output [0:1] frn_fdis_iu6_i1_bh1_hist, + output [0:1] frn_fdis_iu6_i1_bh2_hist, + output [0:17] frn_fdis_iu6_i1_gshare, + output [0:2] frn_fdis_iu6_i1_ls_ptr, + output frn_fdis_iu6_i1_match, + output frn_fdis_iu6_i1_btb_entry, + output [0:1] frn_fdis_iu6_i1_btb_hist, + output frn_fdis_iu6_i1_bta_val, + output [0:3] frn_fdis_iu6_i1_ilat, + output frn_fdis_iu6_i1_t1_v, + output [0:2] frn_fdis_iu6_i1_t1_t, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t1_a, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t1_p, + output frn_fdis_iu6_i1_t2_v, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t2_a, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t2_p, + output [0:2] frn_fdis_iu6_i1_t2_t, + output frn_fdis_iu6_i1_t3_v, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t3_a, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_t3_p, + output [0:2] frn_fdis_iu6_i1_t3_t, + output frn_fdis_iu6_i1_s1_v, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s1_a, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s1_p, + output [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i1_s1_itag, + output [0:2] frn_fdis_iu6_i1_s1_t, + output frn_fdis_iu6_i1_s1_dep_hit, + output frn_fdis_iu6_i1_s2_v, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s2_a, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s2_p, + output [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i1_s2_itag, + output [0:2] frn_fdis_iu6_i1_s2_t, + output frn_fdis_iu6_i1_s2_dep_hit, + output frn_fdis_iu6_i1_s3_v, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s3_a, + output [0:`GPR_POOL_ENC-1] frn_fdis_iu6_i1_s3_p, + output [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_i1_s3_itag, + output [0:2] frn_fdis_iu6_i1_s3_t, + output frn_fdis_iu6_i1_s3_dep_hit + + ); + + // Ibuffer to decode + wire ib_id_iu4_0_valid; + wire [62-`EFF_IFAR_WIDTH:61] ib_id_iu4_0_ifar; + wire [62-`EFF_IFAR_WIDTH:61] ib_id_iu4_0_bta; + wire [0:69] ib_id_iu4_0_instr; + wire [0:2] ib_id_iu4_0_ucode; + wire [0:3] ib_id_iu4_0_ucode_ext; + wire ib_id_iu4_0_isram; + wire ib_id_iu4_0_fuse_val; + wire [0:31] ib_id_iu4_0_fuse_data; + wire ib_id_iu4_1_valid; + wire [62-`EFF_IFAR_WIDTH:61] ib_id_iu4_1_ifar; + wire [62-`EFF_IFAR_WIDTH:61] ib_id_iu4_1_bta; + wire [0:69] ib_id_iu4_1_instr; + wire [0:2] ib_id_iu4_1_ucode; + wire [0:3] ib_id_iu4_1_ucode_ext; + wire ib_id_iu4_1_isram; + wire ib_id_iu4_1_fuse_val; + wire [0:31] ib_id_iu4_1_fuse_data; + wire id_ib_iu4_stall; + + // Decoded instruction to send to rename + wire fdec_frn_iu5_i0_vld; + wire [0:2] fdec_frn_iu5_i0_ucode; + wire fdec_frn_iu5_i0_2ucode; + wire fdec_frn_iu5_i0_fuse_nop; + wire fdec_frn_iu5_i0_rte_lq; + wire fdec_frn_iu5_i0_rte_sq; + wire fdec_frn_iu5_i0_rte_fx0; + wire fdec_frn_iu5_i0_rte_fx1; + wire fdec_frn_iu5_i0_rte_axu0; + wire fdec_frn_iu5_i0_rte_axu1; + wire fdec_frn_iu5_i0_valop; + wire fdec_frn_iu5_i0_ord; + wire fdec_frn_iu5_i0_cord; + wire [0:2] fdec_frn_iu5_i0_error; + wire [0:19] fdec_frn_iu5_i0_fusion; + wire fdec_frn_iu5_i0_spec; + wire fdec_frn_iu5_i0_type_fp; + wire fdec_frn_iu5_i0_type_ap; + wire fdec_frn_iu5_i0_type_spv; + wire fdec_frn_iu5_i0_type_st; + wire fdec_frn_iu5_i0_async_block; + wire fdec_frn_iu5_i0_np1_flush; + wire fdec_frn_iu5_i0_core_block; + wire fdec_frn_iu5_i0_isram; + wire fdec_frn_iu5_i0_isload; + wire fdec_frn_iu5_i0_isstore; + wire [0:31] fdec_frn_iu5_i0_instr; + wire [62-`EFF_IFAR_WIDTH:61] fdec_frn_iu5_i0_ifar; + wire [62-`EFF_IFAR_WIDTH:61] fdec_frn_iu5_i0_bta; + wire [0:3] fdec_frn_iu5_i0_ilat; + wire fdec_frn_iu5_i0_t1_v; + wire [0:2] fdec_frn_iu5_i0_t1_t; + wire [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i0_t1_a; + wire fdec_frn_iu5_i0_t2_v; + wire [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i0_t2_a; + wire [0:2] fdec_frn_iu5_i0_t2_t; + wire fdec_frn_iu5_i0_t3_v; + wire [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i0_t3_a; + wire [0:2] fdec_frn_iu5_i0_t3_t; + wire fdec_frn_iu5_i0_s1_v; + wire [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i0_s1_a; + wire [0:2] fdec_frn_iu5_i0_s1_t; + wire fdec_frn_iu5_i0_s2_v; + wire [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i0_s2_a; + wire [0:2] fdec_frn_iu5_i0_s2_t; + wire fdec_frn_iu5_i0_s3_v; + wire [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i0_s3_a; + wire [0:2] fdec_frn_iu5_i0_s3_t; + wire fdec_frn_iu5_i0_br_pred; + wire fdec_frn_iu5_i0_bh_update; + wire [0:1] fdec_frn_iu5_i0_bh0_hist; + wire [0:1] fdec_frn_iu5_i0_bh1_hist; + wire [0:1] fdec_frn_iu5_i0_bh2_hist; + wire [0:17] fdec_frn_iu5_i0_gshare; + wire [0:2] fdec_frn_iu5_i0_ls_ptr; + wire fdec_frn_iu5_i0_match; + wire fdec_frn_iu5_i0_btb_entry; + wire [0:1] fdec_frn_iu5_i0_btb_hist; + wire fdec_frn_iu5_i0_bta_val; + wire fdec_frn_iu5_i1_vld; + wire [0:2] fdec_frn_iu5_i1_ucode; + wire fdec_frn_iu5_i1_fuse_nop; + wire fdec_frn_iu5_i1_rte_lq; + wire fdec_frn_iu5_i1_rte_sq; + wire fdec_frn_iu5_i1_rte_fx0; + wire fdec_frn_iu5_i1_rte_fx1; + wire fdec_frn_iu5_i1_rte_axu0; + wire fdec_frn_iu5_i1_rte_axu1; + wire fdec_frn_iu5_i1_valop; + wire fdec_frn_iu5_i1_ord; + wire fdec_frn_iu5_i1_cord; + wire [0:2] fdec_frn_iu5_i1_error; + wire [0:19] fdec_frn_iu5_i1_fusion; + wire fdec_frn_iu5_i1_spec; + wire fdec_frn_iu5_i1_type_fp; + wire fdec_frn_iu5_i1_type_ap; + wire fdec_frn_iu5_i1_type_spv; + wire fdec_frn_iu5_i1_type_st; + wire fdec_frn_iu5_i1_async_block; + wire fdec_frn_iu5_i1_np1_flush; + wire fdec_frn_iu5_i1_core_block; + wire fdec_frn_iu5_i1_isram; + wire fdec_frn_iu5_i1_isload; + wire fdec_frn_iu5_i1_isstore; + wire [0:31] fdec_frn_iu5_i1_instr; + wire [62-`EFF_IFAR_WIDTH:61] fdec_frn_iu5_i1_ifar; + wire [62-`EFF_IFAR_WIDTH:61] fdec_frn_iu5_i1_bta; + wire [0:3] fdec_frn_iu5_i1_ilat; + wire fdec_frn_iu5_i1_t1_v; + wire [0:2] fdec_frn_iu5_i1_t1_t; + wire [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i1_t1_a; + wire fdec_frn_iu5_i1_t2_v; + wire [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i1_t2_a; + wire [0:2] fdec_frn_iu5_i1_t2_t; + wire fdec_frn_iu5_i1_t3_v; + wire [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i1_t3_a; + wire [0:2] fdec_frn_iu5_i1_t3_t; + wire fdec_frn_iu5_i1_s1_v; + wire [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i1_s1_a; + wire [0:2] fdec_frn_iu5_i1_s1_t; + wire fdec_frn_iu5_i1_s2_v; + wire [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i1_s2_a; + wire [0:2] fdec_frn_iu5_i1_s2_t; + wire fdec_frn_iu5_i1_s3_v; + wire [0:`GPR_POOL_ENC-1] fdec_frn_iu5_i1_s3_a; + wire [0:2] fdec_frn_iu5_i1_s3_t; + wire fdec_frn_iu5_i1_br_pred; + wire fdec_frn_iu5_i1_bh_update; + wire [0:1] fdec_frn_iu5_i1_bh0_hist; + wire [0:1] fdec_frn_iu5_i1_bh1_hist; + wire [0:1] fdec_frn_iu5_i1_bh2_hist; + wire [0:17] fdec_frn_iu5_i1_gshare; + wire [0:2] fdec_frn_iu5_i1_ls_ptr; + wire fdec_frn_iu5_i1_match; + wire fdec_frn_iu5_i1_btb_entry; + wire [0:1] fdec_frn_iu5_i1_btb_hist; + wire fdec_frn_iu5_i1_bta_val; + + wire frn_fdec_iu5_stall; + + + //`IBUFF_IFAR_WIDTH => `IBUFF_IFAR_WIDTH, + iuq_ibuf iuq_ibuf0( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .pc_iu_sg_2(pc_iu_sg_2), + .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), + .clkoff_b(clkoff_b), + .act_dis(act_dis), + .tc_ac_ccflush_dc(tc_ac_ccflush_dc), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scan_in(scan_in[6]), + .scan_out(scan_out[6]), + .ib_rm_rdy(ib_rm_rdy), + .rm_ib_iu3_val(rm_ib_iu3_val), + .rm_ib_iu3_instr(rm_ib_iu3_instr), + .uc_ib_iu3_invalid(uc_ib_iu3_invalid), + .cp_iu_iu3_flush(iu_flush), + .cp_flush_into_uc(cp_flush_into_uc), + .br_iu_redirect(br_iu_redirect), + .uc_ib_iu3_flush_all(uc_ib_iu3_flush_all), + .id_ib_iu4_stall(id_ib_iu4_stall), + .ib_ic_need_fetch(ib_ic_need_fetch), + .bp_ib_iu3_ifar(bp_ib_iu3_ifar), + .bp_ib_iu3_val(bp_ib_iu3_val), + .bp_ib_iu3_0_instr(bp_ib_iu3_0_instr), + .bp_ib_iu3_1_instr(bp_ib_iu3_1_instr), + .bp_ib_iu3_2_instr(bp_ib_iu3_2_instr), + .bp_ib_iu3_3_instr(bp_ib_iu3_3_instr), + .bp_ib_iu3_bta(bp_ib_iu3_bta), + .ib_uc_rdy(ib_uc_rdy), + .uc_ib_val(uc_ib_val), + .uc_ib_done(uc_ib_done), + .uc_ib_instr0(uc_ib_instr0), + .uc_ib_instr1(uc_ib_instr1), + .uc_ib_ifar0(uc_ib_ifar0), + .uc_ib_ifar1(uc_ib_ifar1), + .uc_ib_ext0(uc_ib_ext0), + .uc_ib_ext1(uc_ib_ext1), + .ib_id_iu4_0_valid(ib_id_iu4_0_valid), + .ib_id_iu4_0_ifar(ib_id_iu4_0_ifar), + .ib_id_iu4_0_bta(ib_id_iu4_0_bta), + .ib_id_iu4_0_instr(ib_id_iu4_0_instr), + .ib_id_iu4_0_ucode(ib_id_iu4_0_ucode), + .ib_id_iu4_0_ucode_ext(ib_id_iu4_0_ucode_ext), + .ib_id_iu4_0_isram(ib_id_iu4_0_isram), + .ib_id_iu4_0_fuse_data(ib_id_iu4_0_fuse_data), + .ib_id_iu4_0_fuse_val(ib_id_iu4_0_fuse_val), + .ib_id_iu4_1_valid(ib_id_iu4_1_valid), + .ib_id_iu4_1_ifar(ib_id_iu4_1_ifar), + .ib_id_iu4_1_bta(ib_id_iu4_1_bta), + .ib_id_iu4_1_instr(ib_id_iu4_1_instr), + .ib_id_iu4_1_ucode(ib_id_iu4_1_ucode), + .ib_id_iu4_1_ucode_ext(ib_id_iu4_1_ucode_ext), + .ib_id_iu4_1_isram(ib_id_iu4_1_isram), + .ib_id_iu4_1_fuse_data(ib_id_iu4_1_fuse_data), + .ib_id_iu4_1_fuse_val(ib_id_iu4_1_fuse_val) + ); + + + iuq_dec_top dec_top0( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .pc_iu_sg_2(pc_iu_sg_2), + .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), + .clkoff_b(clkoff_b), + .act_dis(act_dis), + .tc_ac_ccflush_dc(tc_ac_ccflush_dc), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scan_in(scan_in[0:3]), + .scan_out(scan_out[0:3]), + + .xu_iu_epcr_dgtmi(xu_iu_epcr_dgtmi), + .xu_iu_msrp_uclep(tc_ac_ccflush_dc), + .xu_iu_msr_pr(xu_iu_msr_pr), + .xu_iu_msr_gs(xu_iu_msr_gs), + .xu_iu_msr_ucle(xu_iu_msr_ucle), + .xu_iu_ccr2_ucode_dis(xu_iu_ccr2_ucode_dis), + + .spr_dec_mask(spr_dec_mask), + .spr_dec_match(spr_dec_match), + .iu_au_config_iucr(iu_au_config_iucr), + .mm_iu_tlbwe_binv(mm_iu_tlbwe_binv), + + .cp_iu_iu4_flush(cp_iu_iu4_flush), + .uc_ib_iu3_flush_all(uc_ib_iu3_flush_all), + .br_iu_redirect(br_iu_redirect), + + .ib_id_iu4_0_valid(ib_id_iu4_0_valid), + .ib_id_iu4_0_ifar(ib_id_iu4_0_ifar), + .ib_id_iu4_0_bta(ib_id_iu4_0_bta), + .ib_id_iu4_0_instr(ib_id_iu4_0_instr), + .ib_id_iu4_0_ucode(ib_id_iu4_0_ucode), + .ib_id_iu4_0_ucode_ext(ib_id_iu4_0_ucode_ext), + .ib_id_iu4_0_isram(ib_id_iu4_0_isram), + .ib_id_iu4_0_fuse_data(ib_id_iu4_0_fuse_data), + .ib_id_iu4_0_fuse_val(ib_id_iu4_0_fuse_val), + + .ib_id_iu4_1_valid(ib_id_iu4_1_valid), + .ib_id_iu4_1_ifar(ib_id_iu4_1_ifar), + .ib_id_iu4_1_bta(ib_id_iu4_1_bta), + .ib_id_iu4_1_instr(ib_id_iu4_1_instr), + .ib_id_iu4_1_ucode(ib_id_iu4_1_ucode), + .ib_id_iu4_1_ucode_ext(ib_id_iu4_1_ucode_ext), + .ib_id_iu4_1_isram(ib_id_iu4_1_isram), + .ib_id_iu4_1_fuse_data(ib_id_iu4_1_fuse_data), + .ib_id_iu4_1_fuse_val(ib_id_iu4_1_fuse_val), + + .id_ib_iu4_stall(id_ib_iu4_stall), + + // Decoded instruction to send to rename + .fdec_frn_iu5_i0_vld(fdec_frn_iu5_i0_vld), + .fdec_frn_iu5_i0_ucode(fdec_frn_iu5_i0_ucode), + .fdec_frn_iu5_i0_2ucode(fdec_frn_iu5_i0_2ucode), + .fdec_frn_iu5_i0_fuse_nop(fdec_frn_iu5_i0_fuse_nop), + .fdec_frn_iu5_i0_rte_lq(fdec_frn_iu5_i0_rte_lq), + .fdec_frn_iu5_i0_rte_sq(fdec_frn_iu5_i0_rte_sq), + .fdec_frn_iu5_i0_rte_fx0(fdec_frn_iu5_i0_rte_fx0), + .fdec_frn_iu5_i0_rte_fx1(fdec_frn_iu5_i0_rte_fx1), + .fdec_frn_iu5_i0_rte_axu0(fdec_frn_iu5_i0_rte_axu0), + .fdec_frn_iu5_i0_rte_axu1(fdec_frn_iu5_i0_rte_axu1), + .fdec_frn_iu5_i0_valop(fdec_frn_iu5_i0_valop), + .fdec_frn_iu5_i0_ord(fdec_frn_iu5_i0_ord), + .fdec_frn_iu5_i0_cord(fdec_frn_iu5_i0_cord), + .fdec_frn_iu5_i0_error(fdec_frn_iu5_i0_error), + .fdec_frn_iu5_i0_fusion(fdec_frn_iu5_i0_fusion), + .fdec_frn_iu5_i0_spec(fdec_frn_iu5_i0_spec), + .fdec_frn_iu5_i0_type_fp(fdec_frn_iu5_i0_type_fp), + .fdec_frn_iu5_i0_type_ap(fdec_frn_iu5_i0_type_ap), + .fdec_frn_iu5_i0_type_spv(fdec_frn_iu5_i0_type_spv), + .fdec_frn_iu5_i0_type_st(fdec_frn_iu5_i0_type_st), + .fdec_frn_iu5_i0_async_block(fdec_frn_iu5_i0_async_block), + .fdec_frn_iu5_i0_np1_flush(fdec_frn_iu5_i0_np1_flush), + .fdec_frn_iu5_i0_core_block(fdec_frn_iu5_i0_core_block), + .fdec_frn_iu5_i0_isram(fdec_frn_iu5_i0_isram), + .fdec_frn_iu5_i0_isload(fdec_frn_iu5_i0_isload), + .fdec_frn_iu5_i0_isstore(fdec_frn_iu5_i0_isstore), + .fdec_frn_iu5_i0_instr(fdec_frn_iu5_i0_instr), + .fdec_frn_iu5_i0_ifar(fdec_frn_iu5_i0_ifar), + .fdec_frn_iu5_i0_bta(fdec_frn_iu5_i0_bta), + .fdec_frn_iu5_i0_ilat(fdec_frn_iu5_i0_ilat), + .fdec_frn_iu5_i0_t1_v(fdec_frn_iu5_i0_t1_v), + .fdec_frn_iu5_i0_t1_t(fdec_frn_iu5_i0_t1_t), + .fdec_frn_iu5_i0_t1_a(fdec_frn_iu5_i0_t1_a), + .fdec_frn_iu5_i0_t2_v(fdec_frn_iu5_i0_t2_v), + .fdec_frn_iu5_i0_t2_a(fdec_frn_iu5_i0_t2_a), + .fdec_frn_iu5_i0_t2_t(fdec_frn_iu5_i0_t2_t), + .fdec_frn_iu5_i0_t3_v(fdec_frn_iu5_i0_t3_v), + .fdec_frn_iu5_i0_t3_a(fdec_frn_iu5_i0_t3_a), + .fdec_frn_iu5_i0_t3_t(fdec_frn_iu5_i0_t3_t), + .fdec_frn_iu5_i0_s1_v(fdec_frn_iu5_i0_s1_v), + .fdec_frn_iu5_i0_s1_a(fdec_frn_iu5_i0_s1_a), + .fdec_frn_iu5_i0_s1_t(fdec_frn_iu5_i0_s1_t), + .fdec_frn_iu5_i0_s2_v(fdec_frn_iu5_i0_s2_v), + .fdec_frn_iu5_i0_s2_a(fdec_frn_iu5_i0_s2_a), + .fdec_frn_iu5_i0_s2_t(fdec_frn_iu5_i0_s2_t), + .fdec_frn_iu5_i0_s3_v(fdec_frn_iu5_i0_s3_v), + .fdec_frn_iu5_i0_s3_a(fdec_frn_iu5_i0_s3_a), + .fdec_frn_iu5_i0_s3_t(fdec_frn_iu5_i0_s3_t), + .fdec_frn_iu5_i0_br_pred(fdec_frn_iu5_i0_br_pred), + .fdec_frn_iu5_i0_bh_update(fdec_frn_iu5_i0_bh_update), + .fdec_frn_iu5_i0_bh0_hist(fdec_frn_iu5_i0_bh0_hist), + .fdec_frn_iu5_i0_bh1_hist(fdec_frn_iu5_i0_bh1_hist), + .fdec_frn_iu5_i0_bh2_hist(fdec_frn_iu5_i0_bh2_hist), + .fdec_frn_iu5_i0_gshare(fdec_frn_iu5_i0_gshare), + .fdec_frn_iu5_i0_ls_ptr(fdec_frn_iu5_i0_ls_ptr), + .fdec_frn_iu5_i0_match(fdec_frn_iu5_i0_match), + .fdec_frn_iu5_i0_btb_entry(fdec_frn_iu5_i0_btb_entry), + .fdec_frn_iu5_i0_btb_hist(fdec_frn_iu5_i0_btb_hist), + .fdec_frn_iu5_i0_bta_val(fdec_frn_iu5_i0_bta_val), + + .fdec_frn_iu5_i1_vld(fdec_frn_iu5_i1_vld), + .fdec_frn_iu5_i1_ucode(fdec_frn_iu5_i1_ucode), + .fdec_frn_iu5_i1_fuse_nop(fdec_frn_iu5_i1_fuse_nop), + .fdec_frn_iu5_i1_rte_lq(fdec_frn_iu5_i1_rte_lq), + .fdec_frn_iu5_i1_rte_sq(fdec_frn_iu5_i1_rte_sq), + .fdec_frn_iu5_i1_rte_fx0(fdec_frn_iu5_i1_rte_fx0), + .fdec_frn_iu5_i1_rte_fx1(fdec_frn_iu5_i1_rte_fx1), + .fdec_frn_iu5_i1_rte_axu0(fdec_frn_iu5_i1_rte_axu0), + .fdec_frn_iu5_i1_rte_axu1(fdec_frn_iu5_i1_rte_axu1), + .fdec_frn_iu5_i1_valop(fdec_frn_iu5_i1_valop), + .fdec_frn_iu5_i1_ord(fdec_frn_iu5_i1_ord), + .fdec_frn_iu5_i1_cord(fdec_frn_iu5_i1_cord), + .fdec_frn_iu5_i1_error(fdec_frn_iu5_i1_error), + .fdec_frn_iu5_i1_fusion(fdec_frn_iu5_i1_fusion), + .fdec_frn_iu5_i1_spec(fdec_frn_iu5_i1_spec), + .fdec_frn_iu5_i1_type_fp(fdec_frn_iu5_i1_type_fp), + .fdec_frn_iu5_i1_type_ap(fdec_frn_iu5_i1_type_ap), + .fdec_frn_iu5_i1_type_spv(fdec_frn_iu5_i1_type_spv), + .fdec_frn_iu5_i1_type_st(fdec_frn_iu5_i1_type_st), + .fdec_frn_iu5_i1_async_block(fdec_frn_iu5_i1_async_block), + .fdec_frn_iu5_i1_np1_flush(fdec_frn_iu5_i1_np1_flush), + .fdec_frn_iu5_i1_core_block(fdec_frn_iu5_i1_core_block), + .fdec_frn_iu5_i1_isram(fdec_frn_iu5_i1_isram), + .fdec_frn_iu5_i1_isload(fdec_frn_iu5_i1_isload), + .fdec_frn_iu5_i1_isstore(fdec_frn_iu5_i1_isstore), + .fdec_frn_iu5_i1_instr(fdec_frn_iu5_i1_instr), + .fdec_frn_iu5_i1_ifar(fdec_frn_iu5_i1_ifar), + .fdec_frn_iu5_i1_bta(fdec_frn_iu5_i1_bta), + .fdec_frn_iu5_i1_ilat(fdec_frn_iu5_i1_ilat), + .fdec_frn_iu5_i1_t1_v(fdec_frn_iu5_i1_t1_v), + .fdec_frn_iu5_i1_t1_t(fdec_frn_iu5_i1_t1_t), + .fdec_frn_iu5_i1_t1_a(fdec_frn_iu5_i1_t1_a), + .fdec_frn_iu5_i1_t2_v(fdec_frn_iu5_i1_t2_v), + .fdec_frn_iu5_i1_t2_a(fdec_frn_iu5_i1_t2_a), + .fdec_frn_iu5_i1_t2_t(fdec_frn_iu5_i1_t2_t), + .fdec_frn_iu5_i1_t3_v(fdec_frn_iu5_i1_t3_v), + .fdec_frn_iu5_i1_t3_a(fdec_frn_iu5_i1_t3_a), + .fdec_frn_iu5_i1_t3_t(fdec_frn_iu5_i1_t3_t), + .fdec_frn_iu5_i1_s1_v(fdec_frn_iu5_i1_s1_v), + .fdec_frn_iu5_i1_s1_a(fdec_frn_iu5_i1_s1_a), + .fdec_frn_iu5_i1_s1_t(fdec_frn_iu5_i1_s1_t), + .fdec_frn_iu5_i1_s2_v(fdec_frn_iu5_i1_s2_v), + .fdec_frn_iu5_i1_s2_a(fdec_frn_iu5_i1_s2_a), + .fdec_frn_iu5_i1_s2_t(fdec_frn_iu5_i1_s2_t), + .fdec_frn_iu5_i1_s3_v(fdec_frn_iu5_i1_s3_v), + .fdec_frn_iu5_i1_s3_a(fdec_frn_iu5_i1_s3_a), + .fdec_frn_iu5_i1_s3_t(fdec_frn_iu5_i1_s3_t), + .fdec_frn_iu5_i1_br_pred(fdec_frn_iu5_i1_br_pred), + .fdec_frn_iu5_i1_bh_update(fdec_frn_iu5_i1_bh_update), + .fdec_frn_iu5_i1_bh0_hist(fdec_frn_iu5_i1_bh0_hist), + .fdec_frn_iu5_i1_bh1_hist(fdec_frn_iu5_i1_bh1_hist), + .fdec_frn_iu5_i1_bh2_hist(fdec_frn_iu5_i1_bh2_hist), + .fdec_frn_iu5_i1_gshare(fdec_frn_iu5_i1_gshare), + .fdec_frn_iu5_i1_ls_ptr(fdec_frn_iu5_i1_ls_ptr), + .fdec_frn_iu5_i1_match(fdec_frn_iu5_i1_match), + .fdec_frn_iu5_i1_btb_entry(fdec_frn_iu5_i1_btb_entry), + .fdec_frn_iu5_i1_btb_hist(fdec_frn_iu5_i1_btb_hist), + .fdec_frn_iu5_i1_bta_val(fdec_frn_iu5_i1_bta_val), + + .frn_fdec_iu5_stall(frn_fdec_iu5_stall) + ); + + + iuq_rn_top rn_top0( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), + .pc_iu_sg_2(pc_iu_sg_2), + .clkoff_b(clkoff_b), + .act_dis(act_dis), + .tc_ac_ccflush_dc(tc_ac_ccflush_dc), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .func_scan_in(scan_in[4:5]), + .func_scan_out(scan_out[4:5]), + + //------------------------------- + // Performance interface with I$ + //------------------------------- + .pc_iu_event_bus_enable(pc_iu_event_bus_enable), + .perf_iu5_stall(perf_iu5_stall), + .perf_iu5_cpl_credit_stall(perf_iu5_cpl_credit_stall), + .perf_iu5_gpr_credit_stall(perf_iu5_gpr_credit_stall), + .perf_iu5_cr_credit_stall(perf_iu5_cr_credit_stall), + .perf_iu5_lr_credit_stall(perf_iu5_lr_credit_stall), + .perf_iu5_ctr_credit_stall(perf_iu5_ctr_credit_stall), + .perf_iu5_xer_credit_stall(perf_iu5_xer_credit_stall), + .perf_iu5_br_hold_stall(perf_iu5_br_hold_stall), + .perf_iu5_axu_hold_stall(perf_iu5_axu_hold_stall), + + //----------------------------- + // Inputs to rename from decode + //----------------------------- + .fdec_frn_iu5_i0_vld(fdec_frn_iu5_i0_vld), + .fdec_frn_iu5_i0_ucode(fdec_frn_iu5_i0_ucode), + .fdec_frn_iu5_i0_2ucode(fdec_frn_iu5_i0_2ucode), + .fdec_frn_iu5_i0_fuse_nop(fdec_frn_iu5_i0_fuse_nop), + .fdec_frn_iu5_i0_rte_lq(fdec_frn_iu5_i0_rte_lq), + .fdec_frn_iu5_i0_rte_sq(fdec_frn_iu5_i0_rte_sq), + .fdec_frn_iu5_i0_rte_fx0(fdec_frn_iu5_i0_rte_fx0), + .fdec_frn_iu5_i0_rte_fx1(fdec_frn_iu5_i0_rte_fx1), + .fdec_frn_iu5_i0_rte_axu0(fdec_frn_iu5_i0_rte_axu0), + .fdec_frn_iu5_i0_rte_axu1(fdec_frn_iu5_i0_rte_axu1), + .fdec_frn_iu5_i0_valop(fdec_frn_iu5_i0_valop), + .fdec_frn_iu5_i0_ord(fdec_frn_iu5_i0_ord), + .fdec_frn_iu5_i0_cord(fdec_frn_iu5_i0_cord), + .fdec_frn_iu5_i0_error(fdec_frn_iu5_i0_error), + .fdec_frn_iu5_i0_fusion(fdec_frn_iu5_i0_fusion), + .fdec_frn_iu5_i0_spec(fdec_frn_iu5_i0_spec), + .fdec_frn_iu5_i0_type_fp(fdec_frn_iu5_i0_type_fp), + .fdec_frn_iu5_i0_type_ap(fdec_frn_iu5_i0_type_ap), + .fdec_frn_iu5_i0_type_spv(fdec_frn_iu5_i0_type_spv), + .fdec_frn_iu5_i0_type_st(fdec_frn_iu5_i0_type_st), + .fdec_frn_iu5_i0_async_block(fdec_frn_iu5_i0_async_block), + .fdec_frn_iu5_i0_np1_flush(fdec_frn_iu5_i0_np1_flush), + .fdec_frn_iu5_i0_core_block(fdec_frn_iu5_i0_core_block), + .fdec_frn_iu5_i0_isram(fdec_frn_iu5_i0_isram), + .fdec_frn_iu5_i0_isload(fdec_frn_iu5_i0_isload), + .fdec_frn_iu5_i0_isstore(fdec_frn_iu5_i0_isstore), + .fdec_frn_iu5_i0_instr(fdec_frn_iu5_i0_instr), + .fdec_frn_iu5_i0_ifar(fdec_frn_iu5_i0_ifar), + .fdec_frn_iu5_i0_bta(fdec_frn_iu5_i0_bta), + .fdec_frn_iu5_i0_br_pred(fdec_frn_iu5_i0_br_pred), + .fdec_frn_iu5_i0_bh_update(fdec_frn_iu5_i0_bh_update), + .fdec_frn_iu5_i0_bh0_hist(fdec_frn_iu5_i0_bh0_hist), + .fdec_frn_iu5_i0_bh1_hist(fdec_frn_iu5_i0_bh1_hist), + .fdec_frn_iu5_i0_bh2_hist(fdec_frn_iu5_i0_bh2_hist), + .fdec_frn_iu5_i0_gshare(fdec_frn_iu5_i0_gshare), + .fdec_frn_iu5_i0_ls_ptr(fdec_frn_iu5_i0_ls_ptr), + .fdec_frn_iu5_i0_match(fdec_frn_iu5_i0_match), + .fdec_frn_iu5_i0_btb_entry(fdec_frn_iu5_i0_btb_entry), + .fdec_frn_iu5_i0_btb_hist(fdec_frn_iu5_i0_btb_hist), + .fdec_frn_iu5_i0_bta_val(fdec_frn_iu5_i0_bta_val), + .fdec_frn_iu5_i0_ilat(fdec_frn_iu5_i0_ilat), + .fdec_frn_iu5_i0_t1_v(fdec_frn_iu5_i0_t1_v), + .fdec_frn_iu5_i0_t1_t(fdec_frn_iu5_i0_t1_t), + .fdec_frn_iu5_i0_t1_a(fdec_frn_iu5_i0_t1_a), + .fdec_frn_iu5_i0_t2_v(fdec_frn_iu5_i0_t2_v), + .fdec_frn_iu5_i0_t2_a(fdec_frn_iu5_i0_t2_a), + .fdec_frn_iu5_i0_t2_t(fdec_frn_iu5_i0_t2_t), + .fdec_frn_iu5_i0_t3_v(fdec_frn_iu5_i0_t3_v), + .fdec_frn_iu5_i0_t3_a(fdec_frn_iu5_i0_t3_a), + .fdec_frn_iu5_i0_t3_t(fdec_frn_iu5_i0_t3_t), + .fdec_frn_iu5_i0_s1_v(fdec_frn_iu5_i0_s1_v), + .fdec_frn_iu5_i0_s1_a(fdec_frn_iu5_i0_s1_a), + .fdec_frn_iu5_i0_s1_t(fdec_frn_iu5_i0_s1_t), + .fdec_frn_iu5_i0_s2_v(fdec_frn_iu5_i0_s2_v), + .fdec_frn_iu5_i0_s2_a(fdec_frn_iu5_i0_s2_a), + .fdec_frn_iu5_i0_s2_t(fdec_frn_iu5_i0_s2_t), + .fdec_frn_iu5_i0_s3_v(fdec_frn_iu5_i0_s3_v), + .fdec_frn_iu5_i0_s3_a(fdec_frn_iu5_i0_s3_a), + .fdec_frn_iu5_i0_s3_t(fdec_frn_iu5_i0_s3_t), + + .fdec_frn_iu5_i1_vld(fdec_frn_iu5_i1_vld), + .fdec_frn_iu5_i1_ucode(fdec_frn_iu5_i1_ucode), + .fdec_frn_iu5_i1_fuse_nop(fdec_frn_iu5_i1_fuse_nop), + .fdec_frn_iu5_i1_rte_lq(fdec_frn_iu5_i1_rte_lq), + .fdec_frn_iu5_i1_rte_sq(fdec_frn_iu5_i1_rte_sq), + .fdec_frn_iu5_i1_rte_fx0(fdec_frn_iu5_i1_rte_fx0), + .fdec_frn_iu5_i1_rte_fx1(fdec_frn_iu5_i1_rte_fx1), + .fdec_frn_iu5_i1_rte_axu0(fdec_frn_iu5_i1_rte_axu0), + .fdec_frn_iu5_i1_rte_axu1(fdec_frn_iu5_i1_rte_axu1), + .fdec_frn_iu5_i1_valop(fdec_frn_iu5_i1_valop), + .fdec_frn_iu5_i1_ord(fdec_frn_iu5_i1_ord), + .fdec_frn_iu5_i1_cord(fdec_frn_iu5_i1_cord), + .fdec_frn_iu5_i1_error(fdec_frn_iu5_i1_error), + .fdec_frn_iu5_i1_fusion(fdec_frn_iu5_i1_fusion), + .fdec_frn_iu5_i1_spec(fdec_frn_iu5_i1_spec), + .fdec_frn_iu5_i1_type_fp(fdec_frn_iu5_i1_type_fp), + .fdec_frn_iu5_i1_type_ap(fdec_frn_iu5_i1_type_ap), + .fdec_frn_iu5_i1_type_spv(fdec_frn_iu5_i1_type_spv), + .fdec_frn_iu5_i1_type_st(fdec_frn_iu5_i1_type_st), + .fdec_frn_iu5_i1_async_block(fdec_frn_iu5_i1_async_block), + .fdec_frn_iu5_i1_np1_flush(fdec_frn_iu5_i1_np1_flush), + .fdec_frn_iu5_i1_core_block(fdec_frn_iu5_i1_core_block), + .fdec_frn_iu5_i1_isram(fdec_frn_iu5_i1_isram), + .fdec_frn_iu5_i1_isload(fdec_frn_iu5_i1_isload), + .fdec_frn_iu5_i1_isstore(fdec_frn_iu5_i1_isstore), + .fdec_frn_iu5_i1_instr(fdec_frn_iu5_i1_instr), + .fdec_frn_iu5_i1_ifar(fdec_frn_iu5_i1_ifar), + .fdec_frn_iu5_i1_bta(fdec_frn_iu5_i1_bta), + .fdec_frn_iu5_i1_br_pred(fdec_frn_iu5_i1_br_pred), + .fdec_frn_iu5_i1_bh_update(fdec_frn_iu5_i1_bh_update), + .fdec_frn_iu5_i1_bh0_hist(fdec_frn_iu5_i1_bh0_hist), + .fdec_frn_iu5_i1_bh1_hist(fdec_frn_iu5_i1_bh1_hist), + .fdec_frn_iu5_i1_bh2_hist(fdec_frn_iu5_i1_bh2_hist), + .fdec_frn_iu5_i1_gshare(fdec_frn_iu5_i1_gshare), + .fdec_frn_iu5_i1_ls_ptr(fdec_frn_iu5_i1_ls_ptr), + .fdec_frn_iu5_i1_match(fdec_frn_iu5_i1_match), + .fdec_frn_iu5_i1_btb_entry(fdec_frn_iu5_i1_btb_entry), + .fdec_frn_iu5_i1_btb_hist(fdec_frn_iu5_i1_btb_hist), + .fdec_frn_iu5_i1_bta_val(fdec_frn_iu5_i1_bta_val), + .fdec_frn_iu5_i1_ilat(fdec_frn_iu5_i1_ilat), + .fdec_frn_iu5_i1_t1_v(fdec_frn_iu5_i1_t1_v), + .fdec_frn_iu5_i1_t1_t(fdec_frn_iu5_i1_t1_t), + .fdec_frn_iu5_i1_t1_a(fdec_frn_iu5_i1_t1_a), + .fdec_frn_iu5_i1_t2_v(fdec_frn_iu5_i1_t2_v), + .fdec_frn_iu5_i1_t2_a(fdec_frn_iu5_i1_t2_a), + .fdec_frn_iu5_i1_t2_t(fdec_frn_iu5_i1_t2_t), + .fdec_frn_iu5_i1_t3_v(fdec_frn_iu5_i1_t3_v), + .fdec_frn_iu5_i1_t3_a(fdec_frn_iu5_i1_t3_a), + .fdec_frn_iu5_i1_t3_t(fdec_frn_iu5_i1_t3_t), + .fdec_frn_iu5_i1_s1_v(fdec_frn_iu5_i1_s1_v), + .fdec_frn_iu5_i1_s1_a(fdec_frn_iu5_i1_s1_a), + .fdec_frn_iu5_i1_s1_t(fdec_frn_iu5_i1_s1_t), + .fdec_frn_iu5_i1_s2_v(fdec_frn_iu5_i1_s2_v), + .fdec_frn_iu5_i1_s2_a(fdec_frn_iu5_i1_s2_a), + .fdec_frn_iu5_i1_s2_t(fdec_frn_iu5_i1_s2_t), + .fdec_frn_iu5_i1_s3_v(fdec_frn_iu5_i1_s3_v), + .fdec_frn_iu5_i1_s3_a(fdec_frn_iu5_i1_s3_a), + .fdec_frn_iu5_i1_s3_t(fdec_frn_iu5_i1_s3_t), + + //----------------------------- + // SPR values + //----------------------------- + .spr_high_pri_mask(spr_high_pri_mask), + .spr_cpcr_we(spr_cpcr_we), + .spr_cpcr3_cp_cnt(spr_cpcr3_cp_cnt), + .spr_cpcr5_cp_cnt(spr_cpcr5_cp_cnt), + .spr_single_issue(spr_single_issue), + + //----------------------------- + // Stall to decode + //----------------------------- + .frn_fdec_iu5_stall(frn_fdec_iu5_stall), + + //----------------------------- + // Stall from dispatch + //----------------------------- + .fdis_frn_iu6_stall(fdis_frn_iu6_stall), + + //---------------------------- + // Completion Interface + //---------------------------- + .cp_rn_i0_axu_exception_val(cp_rn_i0_axu_exception_val), + .cp_rn_i0_axu_exception(cp_rn_i0_axu_exception), + .cp_rn_i1_axu_exception_val(cp_rn_i1_axu_exception_val), + .cp_rn_i1_axu_exception(cp_rn_i1_axu_exception), + .cp_rn_empty(cp_rn_empty), + .cp_rn_i0_v(cp_rn_i0_v), + .cp_rn_i0_itag(cp_rn_i0_itag), + .cp_rn_i0_t1_v(cp_rn_i0_t1_v), + .cp_rn_i0_t1_t(cp_rn_i0_t1_t), + .cp_rn_i0_t1_p(cp_rn_i0_t1_p), + .cp_rn_i0_t1_a(cp_rn_i0_t1_a), + .cp_rn_i0_t2_v(cp_rn_i0_t2_v), + .cp_rn_i0_t2_t(cp_rn_i0_t2_t), + .cp_rn_i0_t2_p(cp_rn_i0_t2_p), + .cp_rn_i0_t2_a(cp_rn_i0_t2_a), + .cp_rn_i0_t3_v(cp_rn_i0_t3_v), + .cp_rn_i0_t3_t(cp_rn_i0_t3_t), + .cp_rn_i0_t3_p(cp_rn_i0_t3_p), + .cp_rn_i0_t3_a(cp_rn_i0_t3_a), + + .cp_rn_i1_v(cp_rn_i1_v), + .cp_rn_i1_itag(cp_rn_i1_itag), + .cp_rn_i1_t1_v(cp_rn_i1_t1_v), + .cp_rn_i1_t1_t(cp_rn_i1_t1_t), + .cp_rn_i1_t1_p(cp_rn_i1_t1_p), + .cp_rn_i1_t1_a(cp_rn_i1_t1_a), + .cp_rn_i1_t2_v(cp_rn_i1_t2_v), + .cp_rn_i1_t2_t(cp_rn_i1_t2_t), + .cp_rn_i1_t2_p(cp_rn_i1_t2_p), + .cp_rn_i1_t2_a(cp_rn_i1_t2_a), + .cp_rn_i1_t3_v(cp_rn_i1_t3_v), + .cp_rn_i1_t3_t(cp_rn_i1_t3_t), + .cp_rn_i1_t3_p(cp_rn_i1_t3_p), + .cp_rn_i1_t3_a(cp_rn_i1_t3_a), + + .cp_flush(cp_flush), + .cp_flush_into_uc(cp_flush_into_uc), + .br_iu_redirect(br_iu_redirect), + .cp_rn_uc_credit_free(cp_rn_uc_credit_free), + + //---------------------------------------------------------------- + // Interface to reservation station - Completion is snooping also + //---------------------------------------------------------------- + .frn_fdis_iu6_i0_vld(frn_fdis_iu6_i0_vld), + .frn_fdis_iu6_i0_itag(frn_fdis_iu6_i0_itag), + .frn_fdis_iu6_i0_ucode(frn_fdis_iu6_i0_ucode), + .frn_fdis_iu6_i0_ucode_cnt(frn_fdis_iu6_i0_ucode_cnt), + .frn_fdis_iu6_i0_2ucode(frn_fdis_iu6_i0_2ucode), + .frn_fdis_iu6_i0_fuse_nop(frn_fdis_iu6_i0_fuse_nop), + .frn_fdis_iu6_i0_rte_lq(frn_fdis_iu6_i0_rte_lq), + .frn_fdis_iu6_i0_rte_sq(frn_fdis_iu6_i0_rte_sq), + .frn_fdis_iu6_i0_rte_fx0(frn_fdis_iu6_i0_rte_fx0), + .frn_fdis_iu6_i0_rte_fx1(frn_fdis_iu6_i0_rte_fx1), + .frn_fdis_iu6_i0_rte_axu0(frn_fdis_iu6_i0_rte_axu0), + .frn_fdis_iu6_i0_rte_axu1(frn_fdis_iu6_i0_rte_axu1), + .frn_fdis_iu6_i0_valop(frn_fdis_iu6_i0_valop), + .frn_fdis_iu6_i0_ord(frn_fdis_iu6_i0_ord), + .frn_fdis_iu6_i0_cord(frn_fdis_iu6_i0_cord), + .frn_fdis_iu6_i0_error(frn_fdis_iu6_i0_error), + .frn_fdis_iu6_i0_fusion(frn_fdis_iu6_i0_fusion), + .frn_fdis_iu6_i0_spec(frn_fdis_iu6_i0_spec), + .frn_fdis_iu6_i0_type_fp(frn_fdis_iu6_i0_type_fp), + .frn_fdis_iu6_i0_type_ap(frn_fdis_iu6_i0_type_ap), + .frn_fdis_iu6_i0_type_spv(frn_fdis_iu6_i0_type_spv), + .frn_fdis_iu6_i0_type_st(frn_fdis_iu6_i0_type_st), + .frn_fdis_iu6_i0_async_block(frn_fdis_iu6_i0_async_block), + .frn_fdis_iu6_i0_np1_flush(frn_fdis_iu6_i0_np1_flush), + .frn_fdis_iu6_i0_core_block(frn_fdis_iu6_i0_core_block), + .frn_fdis_iu6_i0_isram(frn_fdis_iu6_i0_isram), + .frn_fdis_iu6_i0_isload(frn_fdis_iu6_i0_isload), + .frn_fdis_iu6_i0_isstore(frn_fdis_iu6_i0_isstore), + .frn_fdis_iu6_i0_instr(frn_fdis_iu6_i0_instr), + .frn_fdis_iu6_i0_ifar(frn_fdis_iu6_i0_ifar), + .frn_fdis_iu6_i0_bta(frn_fdis_iu6_i0_bta), + .frn_fdis_iu6_i0_br_pred(frn_fdis_iu6_i0_br_pred), + .frn_fdis_iu6_i0_bh_update(frn_fdis_iu6_i0_bh_update), + .frn_fdis_iu6_i0_bh0_hist(frn_fdis_iu6_i0_bh0_hist), + .frn_fdis_iu6_i0_bh1_hist(frn_fdis_iu6_i0_bh1_hist), + .frn_fdis_iu6_i0_bh2_hist(frn_fdis_iu6_i0_bh2_hist), + .frn_fdis_iu6_i0_gshare(frn_fdis_iu6_i0_gshare), + .frn_fdis_iu6_i0_ls_ptr(frn_fdis_iu6_i0_ls_ptr), + .frn_fdis_iu6_i0_match(frn_fdis_iu6_i0_match), + .frn_fdis_iu6_i0_btb_entry(frn_fdis_iu6_i0_btb_entry), + .frn_fdis_iu6_i0_btb_hist(frn_fdis_iu6_i0_btb_hist), + .frn_fdis_iu6_i0_bta_val(frn_fdis_iu6_i0_bta_val), + .frn_fdis_iu6_i0_ilat(frn_fdis_iu6_i0_ilat), + .frn_fdis_iu6_i0_t1_v(frn_fdis_iu6_i0_t1_v), + .frn_fdis_iu6_i0_t1_t(frn_fdis_iu6_i0_t1_t), + .frn_fdis_iu6_i0_t1_a(frn_fdis_iu6_i0_t1_a), + .frn_fdis_iu6_i0_t1_p(frn_fdis_iu6_i0_t1_p), + .frn_fdis_iu6_i0_t2_v(frn_fdis_iu6_i0_t2_v), + .frn_fdis_iu6_i0_t2_a(frn_fdis_iu6_i0_t2_a), + .frn_fdis_iu6_i0_t2_p(frn_fdis_iu6_i0_t2_p), + .frn_fdis_iu6_i0_t2_t(frn_fdis_iu6_i0_t2_t), + .frn_fdis_iu6_i0_t3_v(frn_fdis_iu6_i0_t3_v), + .frn_fdis_iu6_i0_t3_a(frn_fdis_iu6_i0_t3_a), + .frn_fdis_iu6_i0_t3_p(frn_fdis_iu6_i0_t3_p), + .frn_fdis_iu6_i0_t3_t(frn_fdis_iu6_i0_t3_t), + .frn_fdis_iu6_i0_s1_v(frn_fdis_iu6_i0_s1_v), + .frn_fdis_iu6_i0_s1_a(frn_fdis_iu6_i0_s1_a), + .frn_fdis_iu6_i0_s1_p(frn_fdis_iu6_i0_s1_p), + .frn_fdis_iu6_i0_s1_itag(frn_fdis_iu6_i0_s1_itag), + .frn_fdis_iu6_i0_s1_t(frn_fdis_iu6_i0_s1_t), + .frn_fdis_iu6_i0_s2_v(frn_fdis_iu6_i0_s2_v), + .frn_fdis_iu6_i0_s2_a(frn_fdis_iu6_i0_s2_a), + .frn_fdis_iu6_i0_s2_p(frn_fdis_iu6_i0_s2_p), + .frn_fdis_iu6_i0_s2_itag(frn_fdis_iu6_i0_s2_itag), + .frn_fdis_iu6_i0_s2_t(frn_fdis_iu6_i0_s2_t), + .frn_fdis_iu6_i0_s3_v(frn_fdis_iu6_i0_s3_v), + .frn_fdis_iu6_i0_s3_a(frn_fdis_iu6_i0_s3_a), + .frn_fdis_iu6_i0_s3_p(frn_fdis_iu6_i0_s3_p), + .frn_fdis_iu6_i0_s3_itag(frn_fdis_iu6_i0_s3_itag), + .frn_fdis_iu6_i0_s3_t(frn_fdis_iu6_i0_s3_t), + + .frn_fdis_iu6_i1_vld(frn_fdis_iu6_i1_vld), + .frn_fdis_iu6_i1_itag(frn_fdis_iu6_i1_itag), + .frn_fdis_iu6_i1_ucode(frn_fdis_iu6_i1_ucode), + .frn_fdis_iu6_i1_ucode_cnt(frn_fdis_iu6_i1_ucode_cnt), + .frn_fdis_iu6_i1_fuse_nop(frn_fdis_iu6_i1_fuse_nop), + .frn_fdis_iu6_i1_rte_lq(frn_fdis_iu6_i1_rte_lq), + .frn_fdis_iu6_i1_rte_sq(frn_fdis_iu6_i1_rte_sq), + .frn_fdis_iu6_i1_rte_fx0(frn_fdis_iu6_i1_rte_fx0), + .frn_fdis_iu6_i1_rte_fx1(frn_fdis_iu6_i1_rte_fx1), + .frn_fdis_iu6_i1_rte_axu0(frn_fdis_iu6_i1_rte_axu0), + .frn_fdis_iu6_i1_rte_axu1(frn_fdis_iu6_i1_rte_axu1), + .frn_fdis_iu6_i1_valop(frn_fdis_iu6_i1_valop), + .frn_fdis_iu6_i1_ord(frn_fdis_iu6_i1_ord), + .frn_fdis_iu6_i1_cord(frn_fdis_iu6_i1_cord), + .frn_fdis_iu6_i1_error(frn_fdis_iu6_i1_error), + .frn_fdis_iu6_i1_fusion(frn_fdis_iu6_i1_fusion), + .frn_fdis_iu6_i1_spec(frn_fdis_iu6_i1_spec), + .frn_fdis_iu6_i1_type_fp(frn_fdis_iu6_i1_type_fp), + .frn_fdis_iu6_i1_type_ap(frn_fdis_iu6_i1_type_ap), + .frn_fdis_iu6_i1_type_spv(frn_fdis_iu6_i1_type_spv), + .frn_fdis_iu6_i1_type_st(frn_fdis_iu6_i1_type_st), + .frn_fdis_iu6_i1_async_block(frn_fdis_iu6_i1_async_block), + .frn_fdis_iu6_i1_np1_flush(frn_fdis_iu6_i1_np1_flush), + .frn_fdis_iu6_i1_core_block(frn_fdis_iu6_i1_core_block), + .frn_fdis_iu6_i1_isram(frn_fdis_iu6_i1_isram), + .frn_fdis_iu6_i1_isload(frn_fdis_iu6_i1_isload), + .frn_fdis_iu6_i1_isstore(frn_fdis_iu6_i1_isstore), + .frn_fdis_iu6_i1_instr(frn_fdis_iu6_i1_instr), + .frn_fdis_iu6_i1_ifar(frn_fdis_iu6_i1_ifar), + .frn_fdis_iu6_i1_bta(frn_fdis_iu6_i1_bta), + .frn_fdis_iu6_i1_br_pred(frn_fdis_iu6_i1_br_pred), + .frn_fdis_iu6_i1_bh_update(frn_fdis_iu6_i1_bh_update), + .frn_fdis_iu6_i1_bh0_hist(frn_fdis_iu6_i1_bh0_hist), + .frn_fdis_iu6_i1_bh1_hist(frn_fdis_iu6_i1_bh1_hist), + .frn_fdis_iu6_i1_bh2_hist(frn_fdis_iu6_i1_bh2_hist), + .frn_fdis_iu6_i1_gshare(frn_fdis_iu6_i1_gshare), + .frn_fdis_iu6_i1_ls_ptr(frn_fdis_iu6_i1_ls_ptr), + .frn_fdis_iu6_i1_match(frn_fdis_iu6_i1_match), + .frn_fdis_iu6_i1_btb_entry(frn_fdis_iu6_i1_btb_entry), + .frn_fdis_iu6_i1_btb_hist(frn_fdis_iu6_i1_btb_hist), + .frn_fdis_iu6_i1_bta_val(frn_fdis_iu6_i1_bta_val), + .frn_fdis_iu6_i1_ilat(frn_fdis_iu6_i1_ilat), + .frn_fdis_iu6_i1_t1_v(frn_fdis_iu6_i1_t1_v), + .frn_fdis_iu6_i1_t1_t(frn_fdis_iu6_i1_t1_t), + .frn_fdis_iu6_i1_t1_a(frn_fdis_iu6_i1_t1_a), + .frn_fdis_iu6_i1_t1_p(frn_fdis_iu6_i1_t1_p), + .frn_fdis_iu6_i1_t2_v(frn_fdis_iu6_i1_t2_v), + .frn_fdis_iu6_i1_t2_a(frn_fdis_iu6_i1_t2_a), + .frn_fdis_iu6_i1_t2_p(frn_fdis_iu6_i1_t2_p), + .frn_fdis_iu6_i1_t2_t(frn_fdis_iu6_i1_t2_t), + .frn_fdis_iu6_i1_t3_v(frn_fdis_iu6_i1_t3_v), + .frn_fdis_iu6_i1_t3_a(frn_fdis_iu6_i1_t3_a), + .frn_fdis_iu6_i1_t3_p(frn_fdis_iu6_i1_t3_p), + .frn_fdis_iu6_i1_t3_t(frn_fdis_iu6_i1_t3_t), + .frn_fdis_iu6_i1_s1_v(frn_fdis_iu6_i1_s1_v), + .frn_fdis_iu6_i1_s1_a(frn_fdis_iu6_i1_s1_a), + .frn_fdis_iu6_i1_s1_p(frn_fdis_iu6_i1_s1_p), + .frn_fdis_iu6_i1_s1_itag(frn_fdis_iu6_i1_s1_itag), + .frn_fdis_iu6_i1_s1_t(frn_fdis_iu6_i1_s1_t), + .frn_fdis_iu6_i1_s1_dep_hit(frn_fdis_iu6_i1_s1_dep_hit), + .frn_fdis_iu6_i1_s2_v(frn_fdis_iu6_i1_s2_v), + .frn_fdis_iu6_i1_s2_a(frn_fdis_iu6_i1_s2_a), + .frn_fdis_iu6_i1_s2_p(frn_fdis_iu6_i1_s2_p), + .frn_fdis_iu6_i1_s2_itag(frn_fdis_iu6_i1_s2_itag), + .frn_fdis_iu6_i1_s2_t(frn_fdis_iu6_i1_s2_t), + .frn_fdis_iu6_i1_s2_dep_hit(frn_fdis_iu6_i1_s2_dep_hit), + .frn_fdis_iu6_i1_s3_v(frn_fdis_iu6_i1_s3_v), + .frn_fdis_iu6_i1_s3_a(frn_fdis_iu6_i1_s3_a), + .frn_fdis_iu6_i1_s3_p(frn_fdis_iu6_i1_s3_p), + .frn_fdis_iu6_i1_s3_itag(frn_fdis_iu6_i1_s3_itag), + .frn_fdis_iu6_i1_s3_t(frn_fdis_iu6_i1_s3_t), + .frn_fdis_iu6_i1_s3_dep_hit(frn_fdis_iu6_i1_s3_dep_hit) + ); + + +endmodule diff --git a/dev/verilog/work/iuq_slice_top.v b/dev/verilog/work/iuq_slice_top.v new file mode 100755 index 0000000..bf7c958 --- /dev/null +++ b/dev/verilog/work/iuq_slice_top.v @@ -0,0 +1,2228 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//******************************************************************** +//* +//* TITLE: +//* +//* NAME: iuq_slice_top.vhdl +//********************************************************************* +`include "tri_a2o.vh" + + +module iuq_slice_top( + (* pin_data="PIN_FUNCTION=/G_CLK/" *) + input [0:`NCLK_WIDTH-1] nclk, + input pc_iu_sg_2, + input pc_iu_func_sl_thold_2, + input pc_iu_func_slp_sl_thold_2, + input clkoff_b, + input act_dis, + input tc_ac_ccflush_dc, + input d_mode, + input delay_lclkr, + input mpw1_b, + input mpw2_b, + input [0:`THREADS*7] scan_in, + output [0:`THREADS*7] scan_out, + + output [0:`THREADS-1] iu_pc_fx0_credit_ok, + output [0:`THREADS-1] iu_pc_fx1_credit_ok, + output [0:`THREADS-1] iu_pc_axu0_credit_ok, + output [0:`THREADS-1] iu_pc_axu1_credit_ok, + output [0:`THREADS-1] iu_pc_lq_credit_ok, + output [0:`THREADS-1] iu_pc_sq_credit_ok, + + + //------------------------------- + // Performance interface with I$ + //------------------------------- + input pc_iu_event_bus_enable, + output [0:20] slice_ic_t0_perf_events, + `ifndef THREADS1 + output [0:20] slice_ic_t1_perf_events, + `endif + + input [0:31] spr_dec_mask, + input [0:31] spr_dec_match, + + input xu_iu_ccr2_ucode_dis, + input mm_iu_tlbwe_binv, + input [0:35] rm_ib_iu3_instr, + + input [62-`EFF_IFAR_WIDTH:61] bp_ib_iu3_t0_ifar, + input [0:`IBUFF_INSTR_WIDTH-1] bp_ib_iu3_t0_0_instr, + input [0:`IBUFF_INSTR_WIDTH-1] bp_ib_iu3_t0_1_instr, + input [0:`IBUFF_INSTR_WIDTH-1] bp_ib_iu3_t0_2_instr, + input [0:`IBUFF_INSTR_WIDTH-1] bp_ib_iu3_t0_3_instr, + input [62-`EFF_IFAR_WIDTH:61] bp_ib_iu3_t0_bta, + `ifndef THREADS1 + input [62-`EFF_IFAR_WIDTH:61] bp_ib_iu3_t1_ifar, + input [0:`IBUFF_INSTR_WIDTH-1] bp_ib_iu3_t1_0_instr, + input [0:`IBUFF_INSTR_WIDTH-1] bp_ib_iu3_t1_1_instr, + input [0:`IBUFF_INSTR_WIDTH-1] bp_ib_iu3_t1_2_instr, + input [0:`IBUFF_INSTR_WIDTH-1] bp_ib_iu3_t1_3_instr, + input [62-`EFF_IFAR_WIDTH:61] bp_ib_iu3_t1_bta, + `endif + + input [0:`THREADS-1] cp_iu_iu4_flush, + input [0:`THREADS-1] cp_flush_into_uc, + + input [0:`THREADS-1] xu_iu_epcr_dgtmi, + input [0:`THREADS-1] xu_iu_msrp_uclep, + input [0:`THREADS-1] xu_iu_msr_pr, + input [0:`THREADS-1] xu_iu_msr_gs, + input [0:`THREADS-1] xu_iu_msr_ucle, + input [0:`THREADS-1] spr_single_issue, + + // Input to dispatch to block due to ivax + input [0:`THREADS-1] cp_dis_ivax, + + //----------------------------- + // MMU Connections + //----------------------------- + + input [0:`THREADS-1] mm_iu_flush_req, + output [0:`THREADS-1] dp_cp_hold_req, + input [0:`THREADS-1] mm_iu_hold_done, + input [0:`THREADS-1] mm_iu_bus_snoop_hold_req, + output [0:`THREADS-1] dp_cp_bus_snoop_hold_req, + input [0:`THREADS-1] mm_iu_bus_snoop_hold_done, + input [0:`THREADS-1] mm_iu_tlbi_complete, + //---------------------------- + // Credit Interface with IU + //---------------------------- + input [0:`THREADS-1] rv_iu_fx0_credit_free, + input [0:`THREADS-1] rv_iu_fx1_credit_free, // Need to add 2nd unit someday + input [0:`THREADS-1] lq_iu_credit_free, + input [0:`THREADS-1] sq_iu_credit_free, + input [0:`THREADS-1] axu0_iu_credit_free, // credit free from axu reservation station + input [0:`THREADS-1] axu1_iu_credit_free, // credit free from axu reservation station + + + output [0:`THREADS-1] ib_rm_rdy, + input [0:`THREADS-1] rm_ib_iu3_val, + output [0:`THREADS-1] ib_uc_rdy, + input [0:`THREADS-1] uc_ib_done, + + + input [0:`THREADS-1] iu_flush, + input [0:`THREADS-1] cp_flush, + input [0:`THREADS-1] br_iu_redirect, + input [0:`THREADS-1] uc_ib_iu3_flush_all, + input [0:`THREADS-1] cp_rn_uc_credit_free, + input [0:`THREADS-1] xu_iu_run_thread, + + output iu_xu_credits_returned, + + +//threaded + + //----------------------------- + // SPR connections + //----------------------------- + input [0:`THREADS-1] spr_cpcr_we, + input [0:4] spr_t0_cpcr2_fx0_cnt, + input [0:4] spr_t0_cpcr2_fx1_cnt, + input [0:4] spr_t0_cpcr2_lq_cnt, + input [0:4] spr_t0_cpcr2_sq_cnt, + input [0:4] spr_t0_cpcr3_fu0_cnt, + input [0:4] spr_t0_cpcr3_fu1_cnt, + input [0:6] spr_t0_cpcr3_cp_cnt, + input [0:4] spr_t0_cpcr4_fx0_cnt, + input [0:4] spr_t0_cpcr4_fx1_cnt, + input [0:4] spr_t0_cpcr4_lq_cnt, + input [0:4] spr_t0_cpcr4_sq_cnt, + input [0:4] spr_t0_cpcr5_fu0_cnt, + input [0:4] spr_t0_cpcr5_fu1_cnt, + input [0:6] spr_t0_cpcr5_cp_cnt, +`ifndef THREADS1 + input [0:4] spr_t1_cpcr2_fx0_cnt, + input [0:4] spr_t1_cpcr2_fx1_cnt, + input [0:4] spr_t1_cpcr2_lq_cnt, + input [0:4] spr_t1_cpcr2_sq_cnt, + input [0:4] spr_t1_cpcr3_fu0_cnt, + input [0:4] spr_t1_cpcr3_fu1_cnt, + input [0:6] spr_t1_cpcr3_cp_cnt, + input [0:4] spr_t1_cpcr4_fx0_cnt, + input [0:4] spr_t1_cpcr4_fx1_cnt, + input [0:4] spr_t1_cpcr4_lq_cnt, + input [0:4] spr_t1_cpcr4_sq_cnt, + input [0:4] spr_t1_cpcr5_fu0_cnt, + input [0:4] spr_t1_cpcr5_fu1_cnt, + input [0:6] spr_t1_cpcr5_cp_cnt, +`endif + input [0:4] spr_cpcr0_fx0_cnt, + input [0:4] spr_cpcr0_fx1_cnt, + input [0:4] spr_cpcr0_lq_cnt, + input [0:4] spr_cpcr0_sq_cnt, + input [0:4] spr_cpcr1_fu0_cnt, + input [0:4] spr_cpcr1_fu1_cnt, + + input [0:`THREADS-1] spr_high_pri_mask, + input [0:`THREADS-1] spr_med_pri_mask, + input [0:5] spr_t0_low_pri_count, +`ifndef THREADS1 + input [0:5] spr_t1_low_pri_count, +`endif + + //----------------------------- + // SPR values + //----------------------------- + input [0:7] iu_au_t0_config_iucr, + + //---------------------------- + // Ucode interface with IB + //---------------------------- + input [0:3] uc_ib_iu3_t0_invalid, + input [0:1] uc_ib_t0_val, + input [0:31] uc_ib_t0_instr0, + input [0:31] uc_ib_t0_instr1, + input [62-`EFF_IFAR_WIDTH:61] uc_ib_t0_ifar0, + input [62-`EFF_IFAR_WIDTH:61] uc_ib_t0_ifar1, + input [0:3] uc_ib_t0_ext0, + input [0:3] uc_ib_t0_ext1, + + //---------------------------- + // Completion Interface + //---------------------------- + input [0:`THREADS-1] cp_rn_empty, + input cp_rn_t0_i0_axu_exception_val, + input [0:3] cp_rn_t0_i0_axu_exception, + input cp_rn_t0_i1_axu_exception_val, + input [0:3] cp_rn_t0_i1_axu_exception, + input cp_rn_t0_i0_v, + input [0:`ITAG_SIZE_ENC-1] cp_rn_t0_i0_itag, + input cp_rn_t0_i0_t1_v, + input [0:2] cp_rn_t0_i0_t1_t, + input [0:`GPR_POOL_ENC-1] cp_rn_t0_i0_t1_p, + input [0:`GPR_POOL_ENC-1] cp_rn_t0_i0_t1_a, + input cp_rn_t0_i0_t2_v, + input [0:2] cp_rn_t0_i0_t2_t, + input [0:`GPR_POOL_ENC-1] cp_rn_t0_i0_t2_p, + input [0:`GPR_POOL_ENC-1] cp_rn_t0_i0_t2_a, + input cp_rn_t0_i0_t3_v, + input [0:2] cp_rn_t0_i0_t3_t, + input [0:`GPR_POOL_ENC-1] cp_rn_t0_i0_t3_p, + input [0:`GPR_POOL_ENC-1] cp_rn_t0_i0_t3_a, + + input cp_rn_t0_i1_v, + input [0:`ITAG_SIZE_ENC-1] cp_rn_t0_i1_itag, + input cp_rn_t0_i1_t1_v, + input [0:2] cp_rn_t0_i1_t1_t, + input [0:`GPR_POOL_ENC-1] cp_rn_t0_i1_t1_p, + input [0:`GPR_POOL_ENC-1] cp_rn_t0_i1_t1_a, + input cp_rn_t0_i1_t2_v, + input [0:2] cp_rn_t0_i1_t2_t, + input [0:`GPR_POOL_ENC-1] cp_rn_t0_i1_t2_p, + input [0:`GPR_POOL_ENC-1] cp_rn_t0_i1_t2_a, + input cp_rn_t0_i1_t3_v, + input [0:2] cp_rn_t0_i1_t3_t, + input [0:`GPR_POOL_ENC-1] cp_rn_t0_i1_t3_p, + input [0:`GPR_POOL_ENC-1] cp_rn_t0_i1_t3_a, + + //---------------------------------------------------------------- + // Interface to reservation station - Completion is snooping also + //---------------------------------------------------------------- + output iu_rv_iu6_t0_i0_vld, + output iu_rv_iu6_t0_i0_act, + output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i0_itag, + output [0:2] iu_rv_iu6_t0_i0_ucode, + output [0:`UCODE_ENTRIES_ENC-1] iu_rv_iu6_t0_i0_ucode_cnt, + output iu_rv_iu6_t0_i0_2ucode, + output iu_rv_iu6_t0_i0_fuse_nop, + output iu_rv_iu6_t0_i0_rte_lq, + output iu_rv_iu6_t0_i0_rte_sq, + output iu_rv_iu6_t0_i0_rte_fx0, + output iu_rv_iu6_t0_i0_rte_fx1, + output iu_rv_iu6_t0_i0_rte_axu0, + output iu_rv_iu6_t0_i0_rte_axu1, + output iu_rv_iu6_t0_i0_valop, + output iu_rv_iu6_t0_i0_ord, + output iu_rv_iu6_t0_i0_cord, + output [0:2] iu_rv_iu6_t0_i0_error, + output iu_rv_iu6_t0_i0_btb_entry, + output [0:1] iu_rv_iu6_t0_i0_btb_hist, + output iu_rv_iu6_t0_i0_bta_val, + output [0:19] iu_rv_iu6_t0_i0_fusion, + output iu_rv_iu6_t0_i0_spec, + output iu_rv_iu6_t0_i0_type_fp, + output iu_rv_iu6_t0_i0_type_ap, + output iu_rv_iu6_t0_i0_type_spv, + output iu_rv_iu6_t0_i0_type_st, + output iu_rv_iu6_t0_i0_async_block, + output iu_rv_iu6_t0_i0_np1_flush, + output iu_rv_iu6_t0_i0_isram, + output iu_rv_iu6_t0_i0_isload, + output iu_rv_iu6_t0_i0_isstore, + output [0:31] iu_rv_iu6_t0_i0_instr, + output [62-`EFF_IFAR_WIDTH:61] iu_rv_iu6_t0_i0_ifar, + output [62-`EFF_IFAR_WIDTH:61] iu_rv_iu6_t0_i0_bta, + output iu_rv_iu6_t0_i0_br_pred, + output iu_rv_iu6_t0_i0_bh_update, + output [0:1] iu_rv_iu6_t0_i0_bh0_hist, + output [0:1] iu_rv_iu6_t0_i0_bh1_hist, + output [0:1] iu_rv_iu6_t0_i0_bh2_hist, + output [0:17] iu_rv_iu6_t0_i0_gshare, + output [0:2] iu_rv_iu6_t0_i0_ls_ptr, + output iu_rv_iu6_t0_i0_match, + output [0:3] iu_rv_iu6_t0_i0_ilat, + output iu_rv_iu6_t0_i0_t1_v, + output [0:2] iu_rv_iu6_t0_i0_t1_t, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_t1_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_t1_p, + output iu_rv_iu6_t0_i0_t2_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_t2_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_t2_p, + output [0:2] iu_rv_iu6_t0_i0_t2_t, + output iu_rv_iu6_t0_i0_t3_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_t3_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_t3_p, + output [0:2] iu_rv_iu6_t0_i0_t3_t, + output iu_rv_iu6_t0_i0_s1_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_s1_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_s1_p, + output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i0_s1_itag, + output [0:2] iu_rv_iu6_t0_i0_s1_t, + output iu_rv_iu6_t0_i0_s2_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_s2_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_s2_p, + output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i0_s2_itag, + output [0:2] iu_rv_iu6_t0_i0_s2_t, + output iu_rv_iu6_t0_i0_s3_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_s3_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_s3_p, + output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i0_s3_itag, + output [0:2] iu_rv_iu6_t0_i0_s3_t, + + output iu_rv_iu6_t0_i1_vld, + output iu_rv_iu6_t0_i1_act, + output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i1_itag, + output [0:2] iu_rv_iu6_t0_i1_ucode, + output [0:`UCODE_ENTRIES_ENC-1] iu_rv_iu6_t0_i1_ucode_cnt, + output iu_rv_iu6_t0_i1_fuse_nop, + output iu_rv_iu6_t0_i1_rte_lq, + output iu_rv_iu6_t0_i1_rte_sq, + output iu_rv_iu6_t0_i1_rte_fx0, + output iu_rv_iu6_t0_i1_rte_fx1, + output iu_rv_iu6_t0_i1_rte_axu0, + output iu_rv_iu6_t0_i1_rte_axu1, + output iu_rv_iu6_t0_i1_valop, + output iu_rv_iu6_t0_i1_ord, + output iu_rv_iu6_t0_i1_cord, + output [0:2] iu_rv_iu6_t0_i1_error, + output iu_rv_iu6_t0_i1_btb_entry, + output [0:1] iu_rv_iu6_t0_i1_btb_hist, + output iu_rv_iu6_t0_i1_bta_val, + output [0:19] iu_rv_iu6_t0_i1_fusion, + output iu_rv_iu6_t0_i1_spec, + output iu_rv_iu6_t0_i1_type_fp, + output iu_rv_iu6_t0_i1_type_ap, + output iu_rv_iu6_t0_i1_type_spv, + output iu_rv_iu6_t0_i1_type_st, + output iu_rv_iu6_t0_i1_async_block, + output iu_rv_iu6_t0_i1_np1_flush, + output iu_rv_iu6_t0_i1_isram, + output iu_rv_iu6_t0_i1_isload, + output iu_rv_iu6_t0_i1_isstore, + output [0:31] iu_rv_iu6_t0_i1_instr, + output [62-`EFF_IFAR_WIDTH:61] iu_rv_iu6_t0_i1_ifar, + output [62-`EFF_IFAR_WIDTH:61] iu_rv_iu6_t0_i1_bta, + output iu_rv_iu6_t0_i1_br_pred, + output iu_rv_iu6_t0_i1_bh_update, + output [0:1] iu_rv_iu6_t0_i1_bh0_hist, + output [0:1] iu_rv_iu6_t0_i1_bh1_hist, + output [0:1] iu_rv_iu6_t0_i1_bh2_hist, + output [0:17] iu_rv_iu6_t0_i1_gshare, + output [0:2] iu_rv_iu6_t0_i1_ls_ptr, + output iu_rv_iu6_t0_i1_match, + output [0:3] iu_rv_iu6_t0_i1_ilat, + output iu_rv_iu6_t0_i1_t1_v, + output [0:2] iu_rv_iu6_t0_i1_t1_t, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_t1_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_t1_p, + output iu_rv_iu6_t0_i1_t2_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_t2_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_t2_p, + output [0:2] iu_rv_iu6_t0_i1_t2_t, + output iu_rv_iu6_t0_i1_t3_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_t3_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_t3_p, + output [0:2] iu_rv_iu6_t0_i1_t3_t, + output iu_rv_iu6_t0_i1_s1_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_s1_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_s1_p, + output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i1_s1_itag, + output [0:2] iu_rv_iu6_t0_i1_s1_t, + output iu_rv_iu6_t0_i1_s1_dep_hit, + output iu_rv_iu6_t0_i1_s2_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_s2_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_s2_p, + output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i1_s2_itag, + output [0:2] iu_rv_iu6_t0_i1_s2_t, + output iu_rv_iu6_t0_i1_s2_dep_hit, + output iu_rv_iu6_t0_i1_s3_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_s3_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_s3_p, + output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i1_s3_itag, + output [0:2] iu_rv_iu6_t0_i1_s3_t, + output iu_rv_iu6_t0_i1_s3_dep_hit, + +`ifndef THREADS1 + //----------------------------- + // SPR values + //----------------------------- + input [0:7] iu_au_t1_config_iucr, + + + //---------------------------- + // Ifetch with slice + //---------------------------- + output [0:(`IBUFF_DEPTH/4)-1] ib_ic_t1_need_fetch, + input [0:3] bp_ib_iu3_t1_val, + + //---------------------------- + // Ucode interface with IB + //---------------------------- + input [0:3] uc_ib_iu3_t1_invalid, + input [0:1] uc_ib_t1_val, + input [0:31] uc_ib_t1_instr0, + input [0:31] uc_ib_t1_instr1, + input [62-`EFF_IFAR_WIDTH:61] uc_ib_t1_ifar0, + input [62-`EFF_IFAR_WIDTH:61] uc_ib_t1_ifar1, + input [0:3] uc_ib_t1_ext0, + input [0:3] uc_ib_t1_ext1, + + //---------------------------- + // Completion Interface + //---------------------------- + input cp_rn_t1_i0_axu_exception_val, + input [0:3] cp_rn_t1_i0_axu_exception, + input cp_rn_t1_i1_axu_exception_val, + input [0:3] cp_rn_t1_i1_axu_exception, + input cp_rn_t1_i0_v, + input [0:`ITAG_SIZE_ENC-1] cp_rn_t1_i0_itag, + input cp_rn_t1_i0_t1_v, + input [0:2] cp_rn_t1_i0_t1_t, + input [0:`GPR_POOL_ENC-1] cp_rn_t1_i0_t1_p, + input [0:`GPR_POOL_ENC-1] cp_rn_t1_i0_t1_a, + input cp_rn_t1_i0_t2_v, + input [0:2] cp_rn_t1_i0_t2_t, + input [0:`GPR_POOL_ENC-1] cp_rn_t1_i0_t2_p, + input [0:`GPR_POOL_ENC-1] cp_rn_t1_i0_t2_a, + input cp_rn_t1_i0_t3_v, + input [0:2] cp_rn_t1_i0_t3_t, + input [0:`GPR_POOL_ENC-1] cp_rn_t1_i0_t3_p, + input [0:`GPR_POOL_ENC-1] cp_rn_t1_i0_t3_a, + + input cp_rn_t1_i1_v, + input [0:`ITAG_SIZE_ENC-1] cp_rn_t1_i1_itag, + input cp_rn_t1_i1_t1_v, + input [0:2] cp_rn_t1_i1_t1_t, + input [0:`GPR_POOL_ENC-1] cp_rn_t1_i1_t1_p, + input [0:`GPR_POOL_ENC-1] cp_rn_t1_i1_t1_a, + input cp_rn_t1_i1_t2_v, + input [0:2] cp_rn_t1_i1_t2_t, + input [0:`GPR_POOL_ENC-1] cp_rn_t1_i1_t2_p, + input [0:`GPR_POOL_ENC-1] cp_rn_t1_i1_t2_a, + input cp_rn_t1_i1_t3_v, + input [0:2] cp_rn_t1_i1_t3_t, + input [0:`GPR_POOL_ENC-1] cp_rn_t1_i1_t3_p, + input [0:`GPR_POOL_ENC-1] cp_rn_t1_i1_t3_a, + + + //---------------------------------------------------------------- + // Interface to reservation station - Completion is snooping also + //---------------------------------------------------------------- + output iu_rv_iu6_t1_i0_vld, + output iu_rv_iu6_t1_i0_act, + output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i0_itag, + output [0:2] iu_rv_iu6_t1_i0_ucode, + output [0:`UCODE_ENTRIES_ENC-1] iu_rv_iu6_t1_i0_ucode_cnt, + output iu_rv_iu6_t1_i0_2ucode, + output iu_rv_iu6_t1_i0_fuse_nop, + output iu_rv_iu6_t1_i0_rte_lq, + output iu_rv_iu6_t1_i0_rte_sq, + output iu_rv_iu6_t1_i0_rte_fx0, + output iu_rv_iu6_t1_i0_rte_fx1, + output iu_rv_iu6_t1_i0_rte_axu0, + output iu_rv_iu6_t1_i0_rte_axu1, + output iu_rv_iu6_t1_i0_valop, + output iu_rv_iu6_t1_i0_ord, + output iu_rv_iu6_t1_i0_cord, + output [0:2] iu_rv_iu6_t1_i0_error, + output iu_rv_iu6_t1_i0_btb_entry, + output [0:1] iu_rv_iu6_t1_i0_btb_hist, + output iu_rv_iu6_t1_i0_bta_val, + output [0:19] iu_rv_iu6_t1_i0_fusion, + output iu_rv_iu6_t1_i0_spec, + output iu_rv_iu6_t1_i0_type_fp, + output iu_rv_iu6_t1_i0_type_ap, + output iu_rv_iu6_t1_i0_type_spv, + output iu_rv_iu6_t1_i0_type_st, + output iu_rv_iu6_t1_i0_async_block, + output iu_rv_iu6_t1_i0_np1_flush, + output iu_rv_iu6_t1_i0_isram, + output iu_rv_iu6_t1_i0_isload, + output iu_rv_iu6_t1_i0_isstore, + output [0:31] iu_rv_iu6_t1_i0_instr, + output [62-`EFF_IFAR_WIDTH:61] iu_rv_iu6_t1_i0_ifar, + output [62-`EFF_IFAR_WIDTH:61] iu_rv_iu6_t1_i0_bta, + output iu_rv_iu6_t1_i0_br_pred, + output iu_rv_iu6_t1_i0_bh_update, + output [0:1] iu_rv_iu6_t1_i0_bh0_hist, + output [0:1] iu_rv_iu6_t1_i0_bh1_hist, + output [0:1] iu_rv_iu6_t1_i0_bh2_hist, + output [0:17] iu_rv_iu6_t1_i0_gshare, + output [0:2] iu_rv_iu6_t1_i0_ls_ptr, + output iu_rv_iu6_t1_i0_match, + output [0:3] iu_rv_iu6_t1_i0_ilat, + output iu_rv_iu6_t1_i0_t1_v, + output [0:2] iu_rv_iu6_t1_i0_t1_t, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_t1_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_t1_p, + output iu_rv_iu6_t1_i0_t2_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_t2_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_t2_p, + output [0:2] iu_rv_iu6_t1_i0_t2_t, + output iu_rv_iu6_t1_i0_t3_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_t3_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_t3_p, + output [0:2] iu_rv_iu6_t1_i0_t3_t, + output iu_rv_iu6_t1_i0_s1_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_s1_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_s1_p, + output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i0_s1_itag, + output [0:2] iu_rv_iu6_t1_i0_s1_t, + output iu_rv_iu6_t1_i0_s2_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_s2_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_s2_p, + output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i0_s2_itag, + output [0:2] iu_rv_iu6_t1_i0_s2_t, + output iu_rv_iu6_t1_i0_s3_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_s3_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_s3_p, + output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i0_s3_itag, + output [0:2] iu_rv_iu6_t1_i0_s3_t, + + output iu_rv_iu6_t1_i1_vld, + output iu_rv_iu6_t1_i1_act, + output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i1_itag, + output [0:2] iu_rv_iu6_t1_i1_ucode, + output [0:`UCODE_ENTRIES_ENC-1] iu_rv_iu6_t1_i1_ucode_cnt, + output iu_rv_iu6_t1_i1_fuse_nop, + output iu_rv_iu6_t1_i1_rte_lq, + output iu_rv_iu6_t1_i1_rte_sq, + output iu_rv_iu6_t1_i1_rte_fx0, + output iu_rv_iu6_t1_i1_rte_fx1, + output iu_rv_iu6_t1_i1_rte_axu0, + output iu_rv_iu6_t1_i1_rte_axu1, + output iu_rv_iu6_t1_i1_valop, + output iu_rv_iu6_t1_i1_ord, + output iu_rv_iu6_t1_i1_cord, + output [0:2] iu_rv_iu6_t1_i1_error, + output iu_rv_iu6_t1_i1_btb_entry, + output [0:1] iu_rv_iu6_t1_i1_btb_hist, + output iu_rv_iu6_t1_i1_bta_val, + output [0:19] iu_rv_iu6_t1_i1_fusion, + output iu_rv_iu6_t1_i1_spec, + output iu_rv_iu6_t1_i1_type_fp, + output iu_rv_iu6_t1_i1_type_ap, + output iu_rv_iu6_t1_i1_type_spv, + output iu_rv_iu6_t1_i1_type_st, + output iu_rv_iu6_t1_i1_async_block, + output iu_rv_iu6_t1_i1_np1_flush, + output iu_rv_iu6_t1_i1_isram, + output iu_rv_iu6_t1_i1_isload, + output iu_rv_iu6_t1_i1_isstore, + output [0:31] iu_rv_iu6_t1_i1_instr, + output [62-`EFF_IFAR_WIDTH:61] iu_rv_iu6_t1_i1_ifar, + output [62-`EFF_IFAR_WIDTH:61] iu_rv_iu6_t1_i1_bta, + output iu_rv_iu6_t1_i1_br_pred, + output iu_rv_iu6_t1_i1_bh_update, + output [0:1] iu_rv_iu6_t1_i1_bh0_hist, + output [0:1] iu_rv_iu6_t1_i1_bh1_hist, + output [0:1] iu_rv_iu6_t1_i1_bh2_hist, + output [0:17] iu_rv_iu6_t1_i1_gshare, + output [0:2] iu_rv_iu6_t1_i1_ls_ptr, + output iu_rv_iu6_t1_i1_match, + output [0:3] iu_rv_iu6_t1_i1_ilat, + output iu_rv_iu6_t1_i1_t1_v, + output [0:2] iu_rv_iu6_t1_i1_t1_t, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_t1_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_t1_p, + output iu_rv_iu6_t1_i1_t2_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_t2_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_t2_p, + output [0:2] iu_rv_iu6_t1_i1_t2_t, + output iu_rv_iu6_t1_i1_t3_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_t3_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_t3_p, + output [0:2] iu_rv_iu6_t1_i1_t3_t, + output iu_rv_iu6_t1_i1_s1_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_s1_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_s1_p, + output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i1_s1_itag, + output [0:2] iu_rv_iu6_t1_i1_s1_t, + output iu_rv_iu6_t1_i1_s1_dep_hit, + output iu_rv_iu6_t1_i1_s2_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_s2_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_s2_p, + output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i1_s2_itag, + output [0:2] iu_rv_iu6_t1_i1_s2_t, + output iu_rv_iu6_t1_i1_s2_dep_hit, + output iu_rv_iu6_t1_i1_s3_v, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_s3_a, + output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_s3_p, + output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i1_s3_itag, + output [0:2] iu_rv_iu6_t1_i1_s3_t, + output iu_rv_iu6_t1_i1_s3_dep_hit, +`endif + + //---------------------------- + // Ifetch with slice + //---------------------------- + output [0:(`IBUFF_DEPTH/4)-1] ib_ic_t0_need_fetch, + input [0:3] bp_ib_iu3_t0_val + + ); + + //---------------------------------------------------------------- + // Interface with rename + //---------------------------------------------------------------- + wire frn_fdis_iu6_t0_i0_vld; + wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_t0_i0_itag; + wire [0:2] frn_fdis_iu6_t0_i0_ucode; + wire [0:`UCODE_ENTRIES_ENC-1] frn_fdis_iu6_t0_i0_ucode_cnt; + wire frn_fdis_iu6_t0_i0_2ucode; + wire frn_fdis_iu6_t0_i0_fuse_nop; + wire frn_fdis_iu6_t0_i0_rte_lq; + wire frn_fdis_iu6_t0_i0_rte_sq; + wire frn_fdis_iu6_t0_i0_rte_fx0; + wire frn_fdis_iu6_t0_i0_rte_fx1; + wire frn_fdis_iu6_t0_i0_rte_axu0; + wire frn_fdis_iu6_t0_i0_rte_axu1; + wire frn_fdis_iu6_t0_i0_valop; + wire frn_fdis_iu6_t0_i0_ord; + wire frn_fdis_iu6_t0_i0_cord; + wire [0:2] frn_fdis_iu6_t0_i0_error; + wire frn_fdis_iu6_t0_i0_btb_entry; + wire [0:1] frn_fdis_iu6_t0_i0_btb_hist; + wire frn_fdis_iu6_t0_i0_bta_val; + wire [0:19] frn_fdis_iu6_t0_i0_fusion; + wire frn_fdis_iu6_t0_i0_spec; + wire frn_fdis_iu6_t0_i0_type_fp; + wire frn_fdis_iu6_t0_i0_type_ap; + wire frn_fdis_iu6_t0_i0_type_spv; + wire frn_fdis_iu6_t0_i0_type_st; + wire frn_fdis_iu6_t0_i0_async_block; + wire frn_fdis_iu6_t0_i0_np1_flush; + wire frn_fdis_iu6_t0_i0_core_block; + wire frn_fdis_iu6_t0_i0_isram; + wire frn_fdis_iu6_t0_i0_isload; + wire frn_fdis_iu6_t0_i0_isstore; + wire [0:31] frn_fdis_iu6_t0_i0_instr; + wire [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_t0_i0_ifar; + wire [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_t0_i0_bta; + wire frn_fdis_iu6_t0_i0_br_pred; + wire frn_fdis_iu6_t0_i0_bh_update; + wire [0:1] frn_fdis_iu6_t0_i0_bh0_hist; + wire [0:1] frn_fdis_iu6_t0_i0_bh1_hist; + wire [0:1] frn_fdis_iu6_t0_i0_bh2_hist; + wire [0:17] frn_fdis_iu6_t0_i0_gshare; + wire [0:2] frn_fdis_iu6_t0_i0_ls_ptr; + wire frn_fdis_iu6_t0_i0_match; + wire [0:3] frn_fdis_iu6_t0_i0_ilat; + wire frn_fdis_iu6_t0_i0_t1_v; + wire [0:2] frn_fdis_iu6_t0_i0_t1_t; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t0_i0_t1_a; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t0_i0_t1_p; + wire frn_fdis_iu6_t0_i0_t2_v; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t0_i0_t2_a; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t0_i0_t2_p; + wire [0:2] frn_fdis_iu6_t0_i0_t2_t; + wire frn_fdis_iu6_t0_i0_t3_v; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t0_i0_t3_a; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t0_i0_t3_p; + wire [0:2] frn_fdis_iu6_t0_i0_t3_t; + wire frn_fdis_iu6_t0_i0_s1_v; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t0_i0_s1_a; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t0_i0_s1_p; + wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_t0_i0_s1_itag; + wire [0:2] frn_fdis_iu6_t0_i0_s1_t; + wire frn_fdis_iu6_t0_i0_s2_v; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t0_i0_s2_a; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t0_i0_s2_p; + wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_t0_i0_s2_itag; + wire [0:2] frn_fdis_iu6_t0_i0_s2_t; + wire frn_fdis_iu6_t0_i0_s3_v; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t0_i0_s3_a; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t0_i0_s3_p; + wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_t0_i0_s3_itag; + wire [0:2] frn_fdis_iu6_t0_i0_s3_t; + + wire frn_fdis_iu6_t0_i1_vld; + wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_t0_i1_itag; + wire [0:2] frn_fdis_iu6_t0_i1_ucode; + wire [0:`UCODE_ENTRIES_ENC-1] frn_fdis_iu6_t0_i1_ucode_cnt; + wire frn_fdis_iu6_t0_i1_fuse_nop; + wire frn_fdis_iu6_t0_i1_rte_lq; + wire frn_fdis_iu6_t0_i1_rte_sq; + wire frn_fdis_iu6_t0_i1_rte_fx0; + wire frn_fdis_iu6_t0_i1_rte_fx1; + wire frn_fdis_iu6_t0_i1_rte_axu0; + wire frn_fdis_iu6_t0_i1_rte_axu1; + wire frn_fdis_iu6_t0_i1_valop; + wire frn_fdis_iu6_t0_i1_ord; + wire frn_fdis_iu6_t0_i1_cord; + wire [0:2] frn_fdis_iu6_t0_i1_error; + wire frn_fdis_iu6_t0_i1_btb_entry; + wire [0:1] frn_fdis_iu6_t0_i1_btb_hist; + wire frn_fdis_iu6_t0_i1_bta_val; + wire [0:19] frn_fdis_iu6_t0_i1_fusion; + wire frn_fdis_iu6_t0_i1_spec; + wire frn_fdis_iu6_t0_i1_type_fp; + wire frn_fdis_iu6_t0_i1_type_ap; + wire frn_fdis_iu6_t0_i1_type_spv; + wire frn_fdis_iu6_t0_i1_type_st; + wire frn_fdis_iu6_t0_i1_async_block; + wire frn_fdis_iu6_t0_i1_np1_flush; + wire frn_fdis_iu6_t0_i1_core_block; + wire frn_fdis_iu6_t0_i1_isram; + wire frn_fdis_iu6_t0_i1_isload; + wire frn_fdis_iu6_t0_i1_isstore; + wire [0:31] frn_fdis_iu6_t0_i1_instr; + wire [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_t0_i1_ifar; + wire [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_t0_i1_bta; + wire frn_fdis_iu6_t0_i1_br_pred; + wire frn_fdis_iu6_t0_i1_bh_update; + wire [0:1] frn_fdis_iu6_t0_i1_bh0_hist; + wire [0:1] frn_fdis_iu6_t0_i1_bh1_hist; + wire [0:1] frn_fdis_iu6_t0_i1_bh2_hist; + wire [0:17] frn_fdis_iu6_t0_i1_gshare; + wire [0:2] frn_fdis_iu6_t0_i1_ls_ptr; + wire frn_fdis_iu6_t0_i1_match; + wire [0:3] frn_fdis_iu6_t0_i1_ilat; + wire frn_fdis_iu6_t0_i1_t1_v; + wire [0:2] frn_fdis_iu6_t0_i1_t1_t; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t0_i1_t1_a; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t0_i1_t1_p; + wire frn_fdis_iu6_t0_i1_t2_v; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t0_i1_t2_a; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t0_i1_t2_p; + wire [0:2] frn_fdis_iu6_t0_i1_t2_t; + wire frn_fdis_iu6_t0_i1_t3_v; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t0_i1_t3_a; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t0_i1_t3_p; + wire [0:2] frn_fdis_iu6_t0_i1_t3_t; + wire frn_fdis_iu6_t0_i1_s1_v; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t0_i1_s1_a; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t0_i1_s1_p; + wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_t0_i1_s1_itag; + wire [0:2] frn_fdis_iu6_t0_i1_s1_t; + wire frn_fdis_iu6_t0_i1_s1_dep_hit; + wire frn_fdis_iu6_t0_i1_s2_v; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t0_i1_s2_a; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t0_i1_s2_p; + wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_t0_i1_s2_itag; + wire [0:2] frn_fdis_iu6_t0_i1_s2_t; + wire frn_fdis_iu6_t0_i1_s2_dep_hit; + wire frn_fdis_iu6_t0_i1_s3_v; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t0_i1_s3_a; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t0_i1_s3_p; + wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_t0_i1_s3_itag; + wire [0:2] frn_fdis_iu6_t0_i1_s3_t; + wire frn_fdis_iu6_t0_i1_s3_dep_hit; + +`ifndef THREADS1 + //---------------------------------------------------------------- + // Interface with rename + //---------------------------------------------------------------- + wire frn_fdis_iu6_t1_i0_vld; + wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_t1_i0_itag; + wire [0:2] frn_fdis_iu6_t1_i0_ucode; + wire [0:`UCODE_ENTRIES_ENC-1] frn_fdis_iu6_t1_i0_ucode_cnt; + wire frn_fdis_iu6_t1_i0_2ucode; + wire frn_fdis_iu6_t1_i0_fuse_nop; + wire frn_fdis_iu6_t1_i0_rte_lq; + wire frn_fdis_iu6_t1_i0_rte_sq; + wire frn_fdis_iu6_t1_i0_rte_fx0; + wire frn_fdis_iu6_t1_i0_rte_fx1; + wire frn_fdis_iu6_t1_i0_rte_axu0; + wire frn_fdis_iu6_t1_i0_rte_axu1; + wire frn_fdis_iu6_t1_i0_valop; + wire frn_fdis_iu6_t1_i0_ord; + wire frn_fdis_iu6_t1_i0_cord; + wire [0:2] frn_fdis_iu6_t1_i0_error; + wire frn_fdis_iu6_t1_i0_btb_entry; + wire [0:1] frn_fdis_iu6_t1_i0_btb_hist; + wire frn_fdis_iu6_t1_i0_bta_val; + wire [0:19] frn_fdis_iu6_t1_i0_fusion; + wire frn_fdis_iu6_t1_i0_spec; + wire frn_fdis_iu6_t1_i0_type_fp; + wire frn_fdis_iu6_t1_i0_type_ap; + wire frn_fdis_iu6_t1_i0_type_spv; + wire frn_fdis_iu6_t1_i0_type_st; + wire frn_fdis_iu6_t1_i0_async_block; + wire frn_fdis_iu6_t1_i0_np1_flush; + wire frn_fdis_iu6_t1_i0_core_block; + wire frn_fdis_iu6_t1_i0_isram; + wire frn_fdis_iu6_t1_i0_isload; + wire frn_fdis_iu6_t1_i0_isstore; + wire [0:31] frn_fdis_iu6_t1_i0_instr; + wire [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_t1_i0_ifar; + wire [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_t1_i0_bta; + wire frn_fdis_iu6_t1_i0_br_pred; + wire frn_fdis_iu6_t1_i0_bh_update; + wire [0:1] frn_fdis_iu6_t1_i0_bh0_hist; + wire [0:1] frn_fdis_iu6_t1_i0_bh1_hist; + wire [0:1] frn_fdis_iu6_t1_i0_bh2_hist; + wire [0:17] frn_fdis_iu6_t1_i0_gshare; + wire [0:2] frn_fdis_iu6_t1_i0_ls_ptr; + wire frn_fdis_iu6_t1_i0_match; + wire [0:3] frn_fdis_iu6_t1_i0_ilat; + wire frn_fdis_iu6_t1_i0_t1_v; + wire [0:2] frn_fdis_iu6_t1_i0_t1_t; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t1_i0_t1_a; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t1_i0_t1_p; + wire frn_fdis_iu6_t1_i0_t2_v; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t1_i0_t2_a; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t1_i0_t2_p; + wire [0:2] frn_fdis_iu6_t1_i0_t2_t; + wire frn_fdis_iu6_t1_i0_t3_v; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t1_i0_t3_a; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t1_i0_t3_p; + wire [0:2] frn_fdis_iu6_t1_i0_t3_t; + wire frn_fdis_iu6_t1_i0_s1_v; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t1_i0_s1_a; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t1_i0_s1_p; + wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_t1_i0_s1_itag; + wire [0:2] frn_fdis_iu6_t1_i0_s1_t; + wire frn_fdis_iu6_t1_i0_s2_v; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t1_i0_s2_a; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t1_i0_s2_p; + wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_t1_i0_s2_itag; + wire [0:2] frn_fdis_iu6_t1_i0_s2_t; + wire frn_fdis_iu6_t1_i0_s3_v; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t1_i0_s3_a; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t1_i0_s3_p; + wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_t1_i0_s3_itag; + wire [0:2] frn_fdis_iu6_t1_i0_s3_t; + + wire frn_fdis_iu6_t1_i1_vld; + wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_t1_i1_itag; + wire [0:2] frn_fdis_iu6_t1_i1_ucode; + wire [0:`UCODE_ENTRIES_ENC-1] frn_fdis_iu6_t1_i1_ucode_cnt; + wire frn_fdis_iu6_t1_i1_fuse_nop; + wire frn_fdis_iu6_t1_i1_rte_lq; + wire frn_fdis_iu6_t1_i1_rte_sq; + wire frn_fdis_iu6_t1_i1_rte_fx0; + wire frn_fdis_iu6_t1_i1_rte_fx1; + wire frn_fdis_iu6_t1_i1_rte_axu0; + wire frn_fdis_iu6_t1_i1_rte_axu1; + wire frn_fdis_iu6_t1_i1_valop; + wire frn_fdis_iu6_t1_i1_ord; + wire frn_fdis_iu6_t1_i1_cord; + wire [0:2] frn_fdis_iu6_t1_i1_error; + wire frn_fdis_iu6_t1_i1_btb_entry; + wire [0:1] frn_fdis_iu6_t1_i1_btb_hist; + wire frn_fdis_iu6_t1_i1_bta_val; + wire [0:19] frn_fdis_iu6_t1_i1_fusion; + wire frn_fdis_iu6_t1_i1_spec; + wire frn_fdis_iu6_t1_i1_type_fp; + wire frn_fdis_iu6_t1_i1_type_ap; + wire frn_fdis_iu6_t1_i1_type_spv; + wire frn_fdis_iu6_t1_i1_type_st; + wire frn_fdis_iu6_t1_i1_async_block; + wire frn_fdis_iu6_t1_i1_np1_flush; + wire frn_fdis_iu6_t1_i1_core_block; + wire frn_fdis_iu6_t1_i1_isram; + wire frn_fdis_iu6_t1_i1_isload; + wire frn_fdis_iu6_t1_i1_isstore; + wire [0:31] frn_fdis_iu6_t1_i1_instr; + wire [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_t1_i1_ifar; + wire [62-`EFF_IFAR_WIDTH:61] frn_fdis_iu6_t1_i1_bta; + wire frn_fdis_iu6_t1_i1_br_pred; + wire frn_fdis_iu6_t1_i1_bh_update; + wire [0:1] frn_fdis_iu6_t1_i1_bh0_hist; + wire [0:1] frn_fdis_iu6_t1_i1_bh1_hist; + wire [0:1] frn_fdis_iu6_t1_i1_bh2_hist; + wire [0:17] frn_fdis_iu6_t1_i1_gshare; + wire [0:2] frn_fdis_iu6_t1_i1_ls_ptr; + wire frn_fdis_iu6_t1_i1_match; + wire [0:3] frn_fdis_iu6_t1_i1_ilat; + wire frn_fdis_iu6_t1_i1_t1_v; + wire [0:2] frn_fdis_iu6_t1_i1_t1_t; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t1_i1_t1_a; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t1_i1_t1_p; + wire frn_fdis_iu6_t1_i1_t2_v; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t1_i1_t2_a; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t1_i1_t2_p; + wire [0:2] frn_fdis_iu6_t1_i1_t2_t; + wire frn_fdis_iu6_t1_i1_t3_v; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t1_i1_t3_a; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t1_i1_t3_p; + wire [0:2] frn_fdis_iu6_t1_i1_t3_t; + wire frn_fdis_iu6_t1_i1_s1_v; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t1_i1_s1_a; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t1_i1_s1_p; + wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_t1_i1_s1_itag; + wire [0:2] frn_fdis_iu6_t1_i1_s1_t; + wire frn_fdis_iu6_t1_i1_s1_dep_hit; + wire frn_fdis_iu6_t1_i1_s2_v; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t1_i1_s2_a; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t1_i1_s2_p; + wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_t1_i1_s2_itag; + wire [0:2] frn_fdis_iu6_t1_i1_s2_t; + wire frn_fdis_iu6_t1_i1_s2_dep_hit; + wire frn_fdis_iu6_t1_i1_s3_v; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t1_i1_s3_a; + wire [0:`GPR_POOL_ENC-1] frn_fdis_iu6_t1_i1_s3_p; + wire [0:`ITAG_SIZE_ENC-1] frn_fdis_iu6_t1_i1_s3_itag; + wire [0:2] frn_fdis_iu6_t1_i1_s3_t; + wire frn_fdis_iu6_t1_i1_s3_dep_hit; +`endif + + wire [0:`THREADS-1] fdis_frn_iu6_stall; + + //------------------------------- + // Performance interface with I$ + //------------------------------- + wire [0:`THREADS-1] perf_iu5_stall; + wire [0:`THREADS-1] perf_iu5_cpl_credit_stall; + wire [0:`THREADS-1] perf_iu5_gpr_credit_stall; + wire [0:`THREADS-1] perf_iu5_cr_credit_stall; + wire [0:`THREADS-1] perf_iu5_lr_credit_stall; + wire [0:`THREADS-1] perf_iu5_ctr_credit_stall; + wire [0:`THREADS-1] perf_iu5_xer_credit_stall; + wire [0:`THREADS-1] perf_iu5_br_hold_stall; + wire [0:`THREADS-1] perf_iu5_axu_hold_stall; + wire [0:`THREADS-1] perf_iu6_stall; + wire [0:`THREADS-1] perf_iu6_dispatch_fx0; + wire [0:`THREADS-1] perf_iu6_dispatch_fx1; + wire [0:`THREADS-1] perf_iu6_dispatch_lq; + wire [0:`THREADS-1] perf_iu6_dispatch_axu0; + wire [0:`THREADS-1] perf_iu6_dispatch_axu1; + wire [0:`THREADS-1] perf_iu6_fx0_credit_stall; + wire [0:`THREADS-1] perf_iu6_fx1_credit_stall; + wire [0:`THREADS-1] perf_iu6_lq_credit_stall; + wire [0:`THREADS-1] perf_iu6_sq_credit_stall; + wire [0:`THREADS-1] perf_iu6_axu0_credit_stall; + wire [0:`THREADS-1] perf_iu6_axu1_credit_stall; + + wire vdd; + wire gnd; + assign vdd = 1'b1; + assign gnd = 1'b0; + + assign slice_ic_t0_perf_events = {perf_iu5_stall[0], perf_iu5_cpl_credit_stall[0], perf_iu5_gpr_credit_stall[0], perf_iu5_cr_credit_stall[0], + perf_iu5_lr_credit_stall[0], perf_iu5_ctr_credit_stall[0], perf_iu5_xer_credit_stall[0], perf_iu5_br_hold_stall[0], + perf_iu5_axu_hold_stall[0], perf_iu6_stall[0], perf_iu6_dispatch_fx0[0], perf_iu6_dispatch_fx1[0], perf_iu6_dispatch_lq[0], + perf_iu6_dispatch_axu0[0], perf_iu6_dispatch_axu1[0], perf_iu6_fx0_credit_stall[0], perf_iu6_fx1_credit_stall[0], + perf_iu6_lq_credit_stall[0], perf_iu6_sq_credit_stall[0], perf_iu6_axu0_credit_stall[0], perf_iu6_axu1_credit_stall[0]}; +`ifndef THREADS1 + assign slice_ic_t1_perf_events = {perf_iu5_stall[1], perf_iu5_cpl_credit_stall[1], perf_iu5_gpr_credit_stall[1], perf_iu5_cr_credit_stall[1], + perf_iu5_lr_credit_stall[1], perf_iu5_ctr_credit_stall[1], perf_iu5_xer_credit_stall[1], perf_iu5_br_hold_stall[1], + perf_iu5_axu_hold_stall[1], perf_iu6_stall[1], perf_iu6_dispatch_fx0[1], perf_iu6_dispatch_fx1[1], perf_iu6_dispatch_lq[1], + perf_iu6_dispatch_axu0[1], perf_iu6_dispatch_axu1[1], perf_iu6_fx0_credit_stall[1], perf_iu6_fx1_credit_stall[1], + perf_iu6_lq_credit_stall[1], perf_iu6_sq_credit_stall[1], perf_iu6_axu0_credit_stall[1], perf_iu6_axu1_credit_stall[1]}; +`endif + + + iuq_slice slice0( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .pc_iu_sg_2(pc_iu_sg_2), + .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), + .clkoff_b(clkoff_b), + .act_dis(act_dis), + .tc_ac_ccflush_dc(tc_ac_ccflush_dc), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scan_in(scan_in[1:7]), + .scan_out(scan_out[1:7]), + + //------------------------------- + // Performance interface with I$ + //------------------------------- + .pc_iu_event_bus_enable(pc_iu_event_bus_enable), + .perf_iu5_stall(perf_iu5_stall[0]), + .perf_iu5_cpl_credit_stall(perf_iu5_cpl_credit_stall[0]), + .perf_iu5_gpr_credit_stall(perf_iu5_gpr_credit_stall[0]), + .perf_iu5_cr_credit_stall(perf_iu5_cr_credit_stall[0]), + .perf_iu5_lr_credit_stall(perf_iu5_lr_credit_stall[0]), + .perf_iu5_ctr_credit_stall(perf_iu5_ctr_credit_stall[0]), + .perf_iu5_xer_credit_stall(perf_iu5_xer_credit_stall[0]), + .perf_iu5_br_hold_stall(perf_iu5_br_hold_stall[0]), + .perf_iu5_axu_hold_stall(perf_iu5_axu_hold_stall[0]), + + .cp_iu_iu4_flush(cp_iu_iu4_flush[0]), + .cp_flush_into_uc(cp_flush_into_uc[0]), + + .xu_iu_epcr_dgtmi(xu_iu_epcr_dgtmi[0]), + .xu_iu_msrp_uclep(xu_iu_msrp_uclep[0]), + .xu_iu_msr_pr(xu_iu_msr_pr[0]), + .xu_iu_msr_gs(xu_iu_msr_gs[0]), + .xu_iu_msr_ucle(xu_iu_msr_ucle[0]), + .xu_iu_ccr2_ucode_dis(xu_iu_ccr2_ucode_dis), + + //----------------------------- + // SPR values + //----------------------------- + .spr_high_pri_mask(spr_high_pri_mask[0]), + .spr_cpcr_we(spr_cpcr_we[0]), + .spr_cpcr3_cp_cnt(spr_t0_cpcr3_cp_cnt), + .spr_cpcr5_cp_cnt(spr_t0_cpcr5_cp_cnt), + .spr_single_issue(spr_single_issue[0]), + .spr_dec_mask(spr_dec_mask), + .spr_dec_match(spr_dec_match), + .iu_au_config_iucr(iu_au_t0_config_iucr), + .mm_iu_tlbwe_binv(mm_iu_tlbwe_binv), + + //---------------------------- + // Ifetch with slice + //---------------------------- + .ib_rm_rdy(ib_rm_rdy[0]), + .rm_ib_iu3_val(rm_ib_iu3_val[0]), + .rm_ib_iu3_instr(rm_ib_iu3_instr), + + .uc_ib_iu3_invalid(uc_ib_iu3_t0_invalid), + + .ib_ic_need_fetch(ib_ic_t0_need_fetch), + + .bp_ib_iu3_ifar(bp_ib_iu3_t0_ifar), + .bp_ib_iu3_val(bp_ib_iu3_t0_val), + .bp_ib_iu3_0_instr(bp_ib_iu3_t0_0_instr), + .bp_ib_iu3_1_instr(bp_ib_iu3_t0_1_instr), + .bp_ib_iu3_2_instr(bp_ib_iu3_t0_2_instr), + .bp_ib_iu3_3_instr(bp_ib_iu3_t0_3_instr), + .bp_ib_iu3_bta(bp_ib_iu3_t0_bta), + + //---------------------------- + // Ucode interface with IB + //---------------------------- + .ib_uc_rdy(ib_uc_rdy[0]), + .uc_ib_val(uc_ib_t0_val), + .uc_ib_done(uc_ib_done[0]), + .uc_ib_instr0(uc_ib_t0_instr0), + .uc_ib_instr1(uc_ib_t0_instr1), + .uc_ib_ifar0(uc_ib_t0_ifar0), + .uc_ib_ifar1(uc_ib_t0_ifar1), + .uc_ib_ext0(uc_ib_t0_ext0), + .uc_ib_ext1(uc_ib_t0_ext1), + + //---------------------------- + // Completion Interface + //---------------------------- + .cp_rn_i0_axu_exception_val(cp_rn_t0_i0_axu_exception_val), + .cp_rn_i0_axu_exception(cp_rn_t0_i0_axu_exception), + .cp_rn_i1_axu_exception_val(cp_rn_t0_i1_axu_exception_val), + .cp_rn_i1_axu_exception(cp_rn_t0_i1_axu_exception), + .cp_rn_empty(cp_rn_empty[0]), + .cp_rn_i0_v(cp_rn_t0_i0_v), + .cp_rn_i0_itag(cp_rn_t0_i0_itag), + .cp_rn_i0_t1_v(cp_rn_t0_i0_t1_v), + .cp_rn_i0_t1_t(cp_rn_t0_i0_t1_t), + .cp_rn_i0_t1_p(cp_rn_t0_i0_t1_p), + .cp_rn_i0_t1_a(cp_rn_t0_i0_t1_a), + .cp_rn_i0_t2_v(cp_rn_t0_i0_t2_v), + .cp_rn_i0_t2_t(cp_rn_t0_i0_t2_t), + .cp_rn_i0_t2_p(cp_rn_t0_i0_t2_p), + .cp_rn_i0_t2_a(cp_rn_t0_i0_t2_a), + .cp_rn_i0_t3_v(cp_rn_t0_i0_t3_v), + .cp_rn_i0_t3_t(cp_rn_t0_i0_t3_t), + .cp_rn_i0_t3_p(cp_rn_t0_i0_t3_p), + .cp_rn_i0_t3_a(cp_rn_t0_i0_t3_a), + + .cp_rn_i1_v(cp_rn_t0_i1_v), + .cp_rn_i1_itag(cp_rn_t0_i1_itag), + .cp_rn_i1_t1_v(cp_rn_t0_i1_t1_v), + .cp_rn_i1_t1_t(cp_rn_t0_i1_t1_t), + .cp_rn_i1_t1_p(cp_rn_t0_i1_t1_p), + .cp_rn_i1_t1_a(cp_rn_t0_i1_t1_a), + .cp_rn_i1_t2_v(cp_rn_t0_i1_t2_v), + .cp_rn_i1_t2_t(cp_rn_t0_i1_t2_t), + .cp_rn_i1_t2_p(cp_rn_t0_i1_t2_p), + .cp_rn_i1_t2_a(cp_rn_t0_i1_t2_a), + .cp_rn_i1_t3_v(cp_rn_t0_i1_t3_v), + .cp_rn_i1_t3_t(cp_rn_t0_i1_t3_t), + .cp_rn_i1_t3_p(cp_rn_t0_i1_t3_p), + .cp_rn_i1_t3_a(cp_rn_t0_i1_t3_a), + + .iu_flush(iu_flush[0]), + .cp_flush(cp_flush[0]), + .br_iu_redirect(br_iu_redirect[0]), + .uc_ib_iu3_flush_all(uc_ib_iu3_flush_all[0]), + .cp_rn_uc_credit_free(cp_rn_uc_credit_free[0]), + + //----------------------------- + // Stall from dispatch + //----------------------------- + .fdis_frn_iu6_stall(fdis_frn_iu6_stall[0]), + + //---------------------------------------------------------------- + // Interface to reservation station - Completion is snooping also + //---------------------------------------------------------------- + .frn_fdis_iu6_i0_vld(frn_fdis_iu6_t0_i0_vld), + .frn_fdis_iu6_i0_itag(frn_fdis_iu6_t0_i0_itag), + .frn_fdis_iu6_i0_ucode(frn_fdis_iu6_t0_i0_ucode), + .frn_fdis_iu6_i0_ucode_cnt(frn_fdis_iu6_t0_i0_ucode_cnt), + .frn_fdis_iu6_i0_2ucode(frn_fdis_iu6_t0_i0_2ucode), + .frn_fdis_iu6_i0_fuse_nop(frn_fdis_iu6_t0_i0_fuse_nop), + .frn_fdis_iu6_i0_rte_lq(frn_fdis_iu6_t0_i0_rte_lq), + .frn_fdis_iu6_i0_rte_sq(frn_fdis_iu6_t0_i0_rte_sq), + .frn_fdis_iu6_i0_rte_fx0(frn_fdis_iu6_t0_i0_rte_fx0), + .frn_fdis_iu6_i0_rte_fx1(frn_fdis_iu6_t0_i0_rte_fx1), + .frn_fdis_iu6_i0_rte_axu0(frn_fdis_iu6_t0_i0_rte_axu0), + .frn_fdis_iu6_i0_rte_axu1(frn_fdis_iu6_t0_i0_rte_axu1), + .frn_fdis_iu6_i0_valop(frn_fdis_iu6_t0_i0_valop), + .frn_fdis_iu6_i0_ord(frn_fdis_iu6_t0_i0_ord), + .frn_fdis_iu6_i0_cord(frn_fdis_iu6_t0_i0_cord), + .frn_fdis_iu6_i0_error(frn_fdis_iu6_t0_i0_error), + .frn_fdis_iu6_i0_fusion(frn_fdis_iu6_t0_i0_fusion), + .frn_fdis_iu6_i0_spec(frn_fdis_iu6_t0_i0_spec), + .frn_fdis_iu6_i0_type_fp(frn_fdis_iu6_t0_i0_type_fp), + .frn_fdis_iu6_i0_type_ap(frn_fdis_iu6_t0_i0_type_ap), + .frn_fdis_iu6_i0_type_spv(frn_fdis_iu6_t0_i0_type_spv), + .frn_fdis_iu6_i0_type_st(frn_fdis_iu6_t0_i0_type_st), + .frn_fdis_iu6_i0_async_block(frn_fdis_iu6_t0_i0_async_block), + .frn_fdis_iu6_i0_np1_flush(frn_fdis_iu6_t0_i0_np1_flush), + .frn_fdis_iu6_i0_core_block(frn_fdis_iu6_t0_i0_core_block), + .frn_fdis_iu6_i0_isram(frn_fdis_iu6_t0_i0_isram), + .frn_fdis_iu6_i0_isload(frn_fdis_iu6_t0_i0_isload), + .frn_fdis_iu6_i0_isstore(frn_fdis_iu6_t0_i0_isstore), + .frn_fdis_iu6_i0_instr(frn_fdis_iu6_t0_i0_instr), + .frn_fdis_iu6_i0_ifar(frn_fdis_iu6_t0_i0_ifar), + .frn_fdis_iu6_i0_bta(frn_fdis_iu6_t0_i0_bta), + .frn_fdis_iu6_i0_br_pred(frn_fdis_iu6_t0_i0_br_pred), + .frn_fdis_iu6_i0_bh_update(frn_fdis_iu6_t0_i0_bh_update), + .frn_fdis_iu6_i0_bh0_hist(frn_fdis_iu6_t0_i0_bh0_hist), + .frn_fdis_iu6_i0_bh1_hist(frn_fdis_iu6_t0_i0_bh1_hist), + .frn_fdis_iu6_i0_bh2_hist(frn_fdis_iu6_t0_i0_bh2_hist), + .frn_fdis_iu6_i0_gshare(frn_fdis_iu6_t0_i0_gshare), + .frn_fdis_iu6_i0_ls_ptr(frn_fdis_iu6_t0_i0_ls_ptr), + .frn_fdis_iu6_i0_match(frn_fdis_iu6_t0_i0_match), + .frn_fdis_iu6_i0_btb_entry(frn_fdis_iu6_t0_i0_btb_entry), + .frn_fdis_iu6_i0_btb_hist(frn_fdis_iu6_t0_i0_btb_hist), + .frn_fdis_iu6_i0_bta_val(frn_fdis_iu6_t0_i0_bta_val), + .frn_fdis_iu6_i0_ilat(frn_fdis_iu6_t0_i0_ilat), + .frn_fdis_iu6_i0_t1_v(frn_fdis_iu6_t0_i0_t1_v), + .frn_fdis_iu6_i0_t1_t(frn_fdis_iu6_t0_i0_t1_t), + .frn_fdis_iu6_i0_t1_a(frn_fdis_iu6_t0_i0_t1_a), + .frn_fdis_iu6_i0_t1_p(frn_fdis_iu6_t0_i0_t1_p), + .frn_fdis_iu6_i0_t2_v(frn_fdis_iu6_t0_i0_t2_v), + .frn_fdis_iu6_i0_t2_a(frn_fdis_iu6_t0_i0_t2_a), + .frn_fdis_iu6_i0_t2_p(frn_fdis_iu6_t0_i0_t2_p), + .frn_fdis_iu6_i0_t2_t(frn_fdis_iu6_t0_i0_t2_t), + .frn_fdis_iu6_i0_t3_v(frn_fdis_iu6_t0_i0_t3_v), + .frn_fdis_iu6_i0_t3_a(frn_fdis_iu6_t0_i0_t3_a), + .frn_fdis_iu6_i0_t3_p(frn_fdis_iu6_t0_i0_t3_p), + .frn_fdis_iu6_i0_t3_t(frn_fdis_iu6_t0_i0_t3_t), + .frn_fdis_iu6_i0_s1_v(frn_fdis_iu6_t0_i0_s1_v), + .frn_fdis_iu6_i0_s1_a(frn_fdis_iu6_t0_i0_s1_a), + .frn_fdis_iu6_i0_s1_p(frn_fdis_iu6_t0_i0_s1_p), + .frn_fdis_iu6_i0_s1_itag(frn_fdis_iu6_t0_i0_s1_itag), + .frn_fdis_iu6_i0_s1_t(frn_fdis_iu6_t0_i0_s1_t), + .frn_fdis_iu6_i0_s2_v(frn_fdis_iu6_t0_i0_s2_v), + .frn_fdis_iu6_i0_s2_a(frn_fdis_iu6_t0_i0_s2_a), + .frn_fdis_iu6_i0_s2_p(frn_fdis_iu6_t0_i0_s2_p), + .frn_fdis_iu6_i0_s2_itag(frn_fdis_iu6_t0_i0_s2_itag), + .frn_fdis_iu6_i0_s2_t(frn_fdis_iu6_t0_i0_s2_t), + .frn_fdis_iu6_i0_s3_v(frn_fdis_iu6_t0_i0_s3_v), + .frn_fdis_iu6_i0_s3_a(frn_fdis_iu6_t0_i0_s3_a), + .frn_fdis_iu6_i0_s3_p(frn_fdis_iu6_t0_i0_s3_p), + .frn_fdis_iu6_i0_s3_itag(frn_fdis_iu6_t0_i0_s3_itag), + .frn_fdis_iu6_i0_s3_t(frn_fdis_iu6_t0_i0_s3_t), + + .frn_fdis_iu6_i1_vld(frn_fdis_iu6_t0_i1_vld), + .frn_fdis_iu6_i1_itag(frn_fdis_iu6_t0_i1_itag), + .frn_fdis_iu6_i1_ucode(frn_fdis_iu6_t0_i1_ucode), + .frn_fdis_iu6_i1_ucode_cnt(frn_fdis_iu6_t0_i1_ucode_cnt), + .frn_fdis_iu6_i1_fuse_nop(frn_fdis_iu6_t0_i1_fuse_nop), + .frn_fdis_iu6_i1_rte_lq(frn_fdis_iu6_t0_i1_rte_lq), + .frn_fdis_iu6_i1_rte_sq(frn_fdis_iu6_t0_i1_rte_sq), + .frn_fdis_iu6_i1_rte_fx0(frn_fdis_iu6_t0_i1_rte_fx0), + .frn_fdis_iu6_i1_rte_fx1(frn_fdis_iu6_t0_i1_rte_fx1), + .frn_fdis_iu6_i1_rte_axu0(frn_fdis_iu6_t0_i1_rte_axu0), + .frn_fdis_iu6_i1_rte_axu1(frn_fdis_iu6_t0_i1_rte_axu1), + .frn_fdis_iu6_i1_valop(frn_fdis_iu6_t0_i1_valop), + .frn_fdis_iu6_i1_ord(frn_fdis_iu6_t0_i1_ord), + .frn_fdis_iu6_i1_cord(frn_fdis_iu6_t0_i1_cord), + .frn_fdis_iu6_i1_error(frn_fdis_iu6_t0_i1_error), + .frn_fdis_iu6_i1_fusion(frn_fdis_iu6_t0_i1_fusion), + .frn_fdis_iu6_i1_spec(frn_fdis_iu6_t0_i1_spec), + .frn_fdis_iu6_i1_type_fp(frn_fdis_iu6_t0_i1_type_fp), + .frn_fdis_iu6_i1_type_ap(frn_fdis_iu6_t0_i1_type_ap), + .frn_fdis_iu6_i1_type_spv(frn_fdis_iu6_t0_i1_type_spv), + .frn_fdis_iu6_i1_type_st(frn_fdis_iu6_t0_i1_type_st), + .frn_fdis_iu6_i1_async_block(frn_fdis_iu6_t0_i1_async_block), + .frn_fdis_iu6_i1_np1_flush(frn_fdis_iu6_t0_i1_np1_flush), + .frn_fdis_iu6_i1_core_block(frn_fdis_iu6_t0_i1_core_block), + .frn_fdis_iu6_i1_isram(frn_fdis_iu6_t0_i1_isram), + .frn_fdis_iu6_i1_isload(frn_fdis_iu6_t0_i1_isload), + .frn_fdis_iu6_i1_isstore(frn_fdis_iu6_t0_i1_isstore), + .frn_fdis_iu6_i1_instr(frn_fdis_iu6_t0_i1_instr), + .frn_fdis_iu6_i1_ifar(frn_fdis_iu6_t0_i1_ifar), + .frn_fdis_iu6_i1_bta(frn_fdis_iu6_t0_i1_bta), + .frn_fdis_iu6_i1_br_pred(frn_fdis_iu6_t0_i1_br_pred), + .frn_fdis_iu6_i1_bh_update(frn_fdis_iu6_t0_i1_bh_update), + .frn_fdis_iu6_i1_bh0_hist(frn_fdis_iu6_t0_i1_bh0_hist), + .frn_fdis_iu6_i1_bh1_hist(frn_fdis_iu6_t0_i1_bh1_hist), + .frn_fdis_iu6_i1_bh2_hist(frn_fdis_iu6_t0_i1_bh2_hist), + .frn_fdis_iu6_i1_gshare(frn_fdis_iu6_t0_i1_gshare), + .frn_fdis_iu6_i1_ls_ptr(frn_fdis_iu6_t0_i1_ls_ptr), + .frn_fdis_iu6_i1_match(frn_fdis_iu6_t0_i1_match), + .frn_fdis_iu6_i1_btb_entry(frn_fdis_iu6_t0_i1_btb_entry), + .frn_fdis_iu6_i1_btb_hist(frn_fdis_iu6_t0_i1_btb_hist), + .frn_fdis_iu6_i1_bta_val(frn_fdis_iu6_t0_i1_bta_val), + .frn_fdis_iu6_i1_ilat(frn_fdis_iu6_t0_i1_ilat), + .frn_fdis_iu6_i1_t1_v(frn_fdis_iu6_t0_i1_t1_v), + .frn_fdis_iu6_i1_t1_t(frn_fdis_iu6_t0_i1_t1_t), + .frn_fdis_iu6_i1_t1_a(frn_fdis_iu6_t0_i1_t1_a), + .frn_fdis_iu6_i1_t1_p(frn_fdis_iu6_t0_i1_t1_p), + .frn_fdis_iu6_i1_t2_v(frn_fdis_iu6_t0_i1_t2_v), + .frn_fdis_iu6_i1_t2_a(frn_fdis_iu6_t0_i1_t2_a), + .frn_fdis_iu6_i1_t2_p(frn_fdis_iu6_t0_i1_t2_p), + .frn_fdis_iu6_i1_t2_t(frn_fdis_iu6_t0_i1_t2_t), + .frn_fdis_iu6_i1_t3_v(frn_fdis_iu6_t0_i1_t3_v), + .frn_fdis_iu6_i1_t3_a(frn_fdis_iu6_t0_i1_t3_a), + .frn_fdis_iu6_i1_t3_p(frn_fdis_iu6_t0_i1_t3_p), + .frn_fdis_iu6_i1_t3_t(frn_fdis_iu6_t0_i1_t3_t), + .frn_fdis_iu6_i1_s1_v(frn_fdis_iu6_t0_i1_s1_v), + .frn_fdis_iu6_i1_s1_a(frn_fdis_iu6_t0_i1_s1_a), + .frn_fdis_iu6_i1_s1_p(frn_fdis_iu6_t0_i1_s1_p), + .frn_fdis_iu6_i1_s1_itag(frn_fdis_iu6_t0_i1_s1_itag), + .frn_fdis_iu6_i1_s1_t(frn_fdis_iu6_t0_i1_s1_t), + .frn_fdis_iu6_i1_s1_dep_hit(frn_fdis_iu6_t0_i1_s1_dep_hit), + .frn_fdis_iu6_i1_s2_v(frn_fdis_iu6_t0_i1_s2_v), + .frn_fdis_iu6_i1_s2_a(frn_fdis_iu6_t0_i1_s2_a), + .frn_fdis_iu6_i1_s2_p(frn_fdis_iu6_t0_i1_s2_p), + .frn_fdis_iu6_i1_s2_itag(frn_fdis_iu6_t0_i1_s2_itag), + .frn_fdis_iu6_i1_s2_t(frn_fdis_iu6_t0_i1_s2_t), + .frn_fdis_iu6_i1_s2_dep_hit(frn_fdis_iu6_t0_i1_s2_dep_hit), + .frn_fdis_iu6_i1_s3_v(frn_fdis_iu6_t0_i1_s3_v), + .frn_fdis_iu6_i1_s3_a(frn_fdis_iu6_t0_i1_s3_a), + .frn_fdis_iu6_i1_s3_p(frn_fdis_iu6_t0_i1_s3_p), + .frn_fdis_iu6_i1_s3_itag(frn_fdis_iu6_t0_i1_s3_itag), + .frn_fdis_iu6_i1_s3_t(frn_fdis_iu6_t0_i1_s3_t), + .frn_fdis_iu6_i1_s3_dep_hit(frn_fdis_iu6_t0_i1_s3_dep_hit) + ); + +`ifndef THREADS1 + iuq_slice slice1( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .pc_iu_sg_2(pc_iu_sg_2), + .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), + .clkoff_b(clkoff_b), + .act_dis(act_dis), + .tc_ac_ccflush_dc(tc_ac_ccflush_dc), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scan_in(scan_in[8:14]), + .scan_out(scan_out[8:14]), + + //------------------------------- + // Performance interface with I$ + //------------------------------- + .pc_iu_event_bus_enable(pc_iu_event_bus_enable), + .perf_iu5_stall(perf_iu5_stall[1]), + .perf_iu5_cpl_credit_stall(perf_iu5_cpl_credit_stall[1]), + .perf_iu5_gpr_credit_stall(perf_iu5_gpr_credit_stall[1]), + .perf_iu5_cr_credit_stall(perf_iu5_cr_credit_stall[1]), + .perf_iu5_lr_credit_stall(perf_iu5_lr_credit_stall[1]), + .perf_iu5_ctr_credit_stall(perf_iu5_ctr_credit_stall[1]), + .perf_iu5_xer_credit_stall(perf_iu5_xer_credit_stall[1]), + .perf_iu5_br_hold_stall(perf_iu5_br_hold_stall[1]), + .perf_iu5_axu_hold_stall(perf_iu5_axu_hold_stall[1]), + + .cp_iu_iu4_flush(cp_iu_iu4_flush[1]), + .cp_flush_into_uc(cp_flush_into_uc[1]), + + .xu_iu_epcr_dgtmi(xu_iu_epcr_dgtmi[1]), + .xu_iu_msrp_uclep(xu_iu_msrp_uclep[1]), + .xu_iu_msr_pr(xu_iu_msr_pr[1]), + .xu_iu_msr_gs(xu_iu_msr_gs[1]), + .xu_iu_msr_ucle(xu_iu_msr_ucle[1]), + .xu_iu_ccr2_ucode_dis(xu_iu_ccr2_ucode_dis), + + //----------------------------- + // SPR values + //----------------------------- + .spr_high_pri_mask(spr_high_pri_mask[1]), + .spr_cpcr_we(spr_cpcr_we[1]), + .spr_cpcr3_cp_cnt(spr_t1_cpcr3_cp_cnt), + .spr_cpcr5_cp_cnt(spr_t1_cpcr5_cp_cnt), + .spr_single_issue(spr_single_issue[1]), + .spr_dec_mask(spr_dec_mask), + .spr_dec_match(spr_dec_match), + .iu_au_config_iucr(iu_au_t1_config_iucr), + .mm_iu_tlbwe_binv(mm_iu_tlbwe_binv), + + //---------------------------- + // Ifetch with slice + //---------------------------- + .ib_rm_rdy(ib_rm_rdy[1]), + .rm_ib_iu3_val(rm_ib_iu3_val[1]), + .rm_ib_iu3_instr(rm_ib_iu3_instr), + + .uc_ib_iu3_invalid(uc_ib_iu3_t1_invalid), + + .ib_ic_need_fetch(ib_ic_t1_need_fetch), + + .bp_ib_iu3_val(bp_ib_iu3_t1_val), + .bp_ib_iu3_ifar(bp_ib_iu3_t1_ifar), + .bp_ib_iu3_0_instr(bp_ib_iu3_t1_0_instr), + .bp_ib_iu3_1_instr(bp_ib_iu3_t1_1_instr), + .bp_ib_iu3_2_instr(bp_ib_iu3_t1_2_instr), + .bp_ib_iu3_3_instr(bp_ib_iu3_t1_3_instr), + .bp_ib_iu3_bta(bp_ib_iu3_t1_bta), + + //---------------------------- + // Ucode interface with IB + //---------------------------- + .ib_uc_rdy(ib_uc_rdy[1]), + .uc_ib_val(uc_ib_t1_val), + .uc_ib_done(uc_ib_done[1]), + .uc_ib_instr0(uc_ib_t1_instr0), + .uc_ib_instr1(uc_ib_t1_instr1), + .uc_ib_ifar0(uc_ib_t1_ifar0), + .uc_ib_ifar1(uc_ib_t1_ifar1), + .uc_ib_ext0(uc_ib_t1_ext0), + .uc_ib_ext1(uc_ib_t1_ext1), + + //---------------------------- + // Completion Interface + //---------------------------- + .cp_rn_i0_axu_exception_val(cp_rn_t1_i0_axu_exception_val), + .cp_rn_i0_axu_exception(cp_rn_t1_i0_axu_exception), + .cp_rn_i1_axu_exception_val(cp_rn_t1_i1_axu_exception_val), + .cp_rn_i1_axu_exception(cp_rn_t1_i1_axu_exception), + .cp_rn_empty(cp_rn_empty[1]), + .cp_rn_i0_v(cp_rn_t1_i0_v), + .cp_rn_i0_itag(cp_rn_t1_i0_itag), + .cp_rn_i0_t1_v(cp_rn_t1_i0_t1_v), + .cp_rn_i0_t1_t(cp_rn_t1_i0_t1_t), + .cp_rn_i0_t1_p(cp_rn_t1_i0_t1_p), + .cp_rn_i0_t1_a(cp_rn_t1_i0_t1_a), + .cp_rn_i0_t2_v(cp_rn_t1_i0_t2_v), + .cp_rn_i0_t2_t(cp_rn_t1_i0_t2_t), + .cp_rn_i0_t2_p(cp_rn_t1_i0_t2_p), + .cp_rn_i0_t2_a(cp_rn_t1_i0_t2_a), + .cp_rn_i0_t3_v(cp_rn_t1_i0_t3_v), + .cp_rn_i0_t3_t(cp_rn_t1_i0_t3_t), + .cp_rn_i0_t3_p(cp_rn_t1_i0_t3_p), + .cp_rn_i0_t3_a(cp_rn_t1_i0_t3_a), + + .cp_rn_i1_v(cp_rn_t1_i1_v), + .cp_rn_i1_itag(cp_rn_t1_i1_itag), + .cp_rn_i1_t1_v(cp_rn_t1_i1_t1_v), + .cp_rn_i1_t1_t(cp_rn_t1_i1_t1_t), + .cp_rn_i1_t1_p(cp_rn_t1_i1_t1_p), + .cp_rn_i1_t1_a(cp_rn_t1_i1_t1_a), + .cp_rn_i1_t2_v(cp_rn_t1_i1_t2_v), + .cp_rn_i1_t2_t(cp_rn_t1_i1_t2_t), + .cp_rn_i1_t2_p(cp_rn_t1_i1_t2_p), + .cp_rn_i1_t2_a(cp_rn_t1_i1_t2_a), + .cp_rn_i1_t3_v(cp_rn_t1_i1_t3_v), + .cp_rn_i1_t3_t(cp_rn_t1_i1_t3_t), + .cp_rn_i1_t3_p(cp_rn_t1_i1_t3_p), + .cp_rn_i1_t3_a(cp_rn_t1_i1_t3_a), + + .iu_flush(iu_flush[1]), + .cp_flush(cp_flush[1]), + .br_iu_redirect(br_iu_redirect[1]), + .uc_ib_iu3_flush_all(uc_ib_iu3_flush_all[1]), + .cp_rn_uc_credit_free(cp_rn_uc_credit_free[1]), + + //----------------------------- + // Stall from dispatch + //----------------------------- + .fdis_frn_iu6_stall(fdis_frn_iu6_stall[1]), + + //---------------------------------------------------------------- + // Interface to reservation station - Completion is snooping also + //---------------------------------------------------------------- + .frn_fdis_iu6_i0_vld(frn_fdis_iu6_t1_i0_vld), + .frn_fdis_iu6_i0_itag(frn_fdis_iu6_t1_i0_itag), + .frn_fdis_iu6_i0_ucode(frn_fdis_iu6_t1_i0_ucode), + .frn_fdis_iu6_i0_ucode_cnt(frn_fdis_iu6_t1_i0_ucode_cnt), + .frn_fdis_iu6_i0_2ucode(frn_fdis_iu6_t1_i0_2ucode), + .frn_fdis_iu6_i0_fuse_nop(frn_fdis_iu6_t1_i0_fuse_nop), + .frn_fdis_iu6_i0_rte_lq(frn_fdis_iu6_t1_i0_rte_lq), + .frn_fdis_iu6_i0_rte_sq(frn_fdis_iu6_t1_i0_rte_sq), + .frn_fdis_iu6_i0_rte_fx0(frn_fdis_iu6_t1_i0_rte_fx0), + .frn_fdis_iu6_i0_rte_fx1(frn_fdis_iu6_t1_i0_rte_fx1), + .frn_fdis_iu6_i0_rte_axu0(frn_fdis_iu6_t1_i0_rte_axu0), + .frn_fdis_iu6_i0_rte_axu1(frn_fdis_iu6_t1_i0_rte_axu1), + .frn_fdis_iu6_i0_valop(frn_fdis_iu6_t1_i0_valop), + .frn_fdis_iu6_i0_ord(frn_fdis_iu6_t1_i0_ord), + .frn_fdis_iu6_i0_cord(frn_fdis_iu6_t1_i0_cord), + .frn_fdis_iu6_i0_error(frn_fdis_iu6_t1_i0_error), + .frn_fdis_iu6_i0_fusion(frn_fdis_iu6_t1_i0_fusion), + .frn_fdis_iu6_i0_spec(frn_fdis_iu6_t1_i0_spec), + .frn_fdis_iu6_i0_type_fp(frn_fdis_iu6_t1_i0_type_fp), + .frn_fdis_iu6_i0_type_ap(frn_fdis_iu6_t1_i0_type_ap), + .frn_fdis_iu6_i0_type_spv(frn_fdis_iu6_t1_i0_type_spv), + .frn_fdis_iu6_i0_type_st(frn_fdis_iu6_t1_i0_type_st), + .frn_fdis_iu6_i0_async_block(frn_fdis_iu6_t1_i0_async_block), + .frn_fdis_iu6_i0_np1_flush(frn_fdis_iu6_t1_i0_np1_flush), + .frn_fdis_iu6_i0_core_block(frn_fdis_iu6_t1_i0_core_block), + .frn_fdis_iu6_i0_isram(frn_fdis_iu6_t1_i0_isram), + .frn_fdis_iu6_i0_isload(frn_fdis_iu6_t1_i0_isload), + .frn_fdis_iu6_i0_isstore(frn_fdis_iu6_t1_i0_isstore), + .frn_fdis_iu6_i0_instr(frn_fdis_iu6_t1_i0_instr), + .frn_fdis_iu6_i0_ifar(frn_fdis_iu6_t1_i0_ifar), + .frn_fdis_iu6_i0_bta(frn_fdis_iu6_t1_i0_bta), + .frn_fdis_iu6_i0_br_pred(frn_fdis_iu6_t1_i0_br_pred), + .frn_fdis_iu6_i0_bh_update(frn_fdis_iu6_t1_i0_bh_update), + .frn_fdis_iu6_i0_bh0_hist(frn_fdis_iu6_t1_i0_bh0_hist), + .frn_fdis_iu6_i0_bh1_hist(frn_fdis_iu6_t1_i0_bh1_hist), + .frn_fdis_iu6_i0_bh2_hist(frn_fdis_iu6_t1_i0_bh2_hist), + .frn_fdis_iu6_i0_gshare(frn_fdis_iu6_t1_i0_gshare), + .frn_fdis_iu6_i0_ls_ptr(frn_fdis_iu6_t1_i0_ls_ptr), + .frn_fdis_iu6_i0_match(frn_fdis_iu6_t1_i0_match), + .frn_fdis_iu6_i0_btb_entry(frn_fdis_iu6_t1_i0_btb_entry), + .frn_fdis_iu6_i0_btb_hist(frn_fdis_iu6_t1_i0_btb_hist), + .frn_fdis_iu6_i0_bta_val(frn_fdis_iu6_t1_i0_bta_val), + .frn_fdis_iu6_i0_ilat(frn_fdis_iu6_t1_i0_ilat), + .frn_fdis_iu6_i0_t1_v(frn_fdis_iu6_t1_i0_t1_v), + .frn_fdis_iu6_i0_t1_t(frn_fdis_iu6_t1_i0_t1_t), + .frn_fdis_iu6_i0_t1_a(frn_fdis_iu6_t1_i0_t1_a), + .frn_fdis_iu6_i0_t1_p(frn_fdis_iu6_t1_i0_t1_p), + .frn_fdis_iu6_i0_t2_v(frn_fdis_iu6_t1_i0_t2_v), + .frn_fdis_iu6_i0_t2_a(frn_fdis_iu6_t1_i0_t2_a), + .frn_fdis_iu6_i0_t2_p(frn_fdis_iu6_t1_i0_t2_p), + .frn_fdis_iu6_i0_t2_t(frn_fdis_iu6_t1_i0_t2_t), + .frn_fdis_iu6_i0_t3_v(frn_fdis_iu6_t1_i0_t3_v), + .frn_fdis_iu6_i0_t3_a(frn_fdis_iu6_t1_i0_t3_a), + .frn_fdis_iu6_i0_t3_p(frn_fdis_iu6_t1_i0_t3_p), + .frn_fdis_iu6_i0_t3_t(frn_fdis_iu6_t1_i0_t3_t), + .frn_fdis_iu6_i0_s1_v(frn_fdis_iu6_t1_i0_s1_v), + .frn_fdis_iu6_i0_s1_a(frn_fdis_iu6_t1_i0_s1_a), + .frn_fdis_iu6_i0_s1_p(frn_fdis_iu6_t1_i0_s1_p), + .frn_fdis_iu6_i0_s1_itag(frn_fdis_iu6_t1_i0_s1_itag), + .frn_fdis_iu6_i0_s1_t(frn_fdis_iu6_t1_i0_s1_t), + .frn_fdis_iu6_i0_s2_v(frn_fdis_iu6_t1_i0_s2_v), + .frn_fdis_iu6_i0_s2_a(frn_fdis_iu6_t1_i0_s2_a), + .frn_fdis_iu6_i0_s2_p(frn_fdis_iu6_t1_i0_s2_p), + .frn_fdis_iu6_i0_s2_itag(frn_fdis_iu6_t1_i0_s2_itag), + .frn_fdis_iu6_i0_s2_t(frn_fdis_iu6_t1_i0_s2_t), + .frn_fdis_iu6_i0_s3_v(frn_fdis_iu6_t1_i0_s3_v), + .frn_fdis_iu6_i0_s3_a(frn_fdis_iu6_t1_i0_s3_a), + .frn_fdis_iu6_i0_s3_p(frn_fdis_iu6_t1_i0_s3_p), + .frn_fdis_iu6_i0_s3_itag(frn_fdis_iu6_t1_i0_s3_itag), + .frn_fdis_iu6_i0_s3_t(frn_fdis_iu6_t1_i0_s3_t), + + .frn_fdis_iu6_i1_vld(frn_fdis_iu6_t1_i1_vld), + .frn_fdis_iu6_i1_itag(frn_fdis_iu6_t1_i1_itag), + .frn_fdis_iu6_i1_ucode(frn_fdis_iu6_t1_i1_ucode), + .frn_fdis_iu6_i1_ucode_cnt(frn_fdis_iu6_t1_i1_ucode_cnt), + .frn_fdis_iu6_i1_fuse_nop(frn_fdis_iu6_t1_i1_fuse_nop), + .frn_fdis_iu6_i1_rte_lq(frn_fdis_iu6_t1_i1_rte_lq), + .frn_fdis_iu6_i1_rte_sq(frn_fdis_iu6_t1_i1_rte_sq), + .frn_fdis_iu6_i1_rte_fx0(frn_fdis_iu6_t1_i1_rte_fx0), + .frn_fdis_iu6_i1_rte_fx1(frn_fdis_iu6_t1_i1_rte_fx1), + .frn_fdis_iu6_i1_rte_axu0(frn_fdis_iu6_t1_i1_rte_axu0), + .frn_fdis_iu6_i1_rte_axu1(frn_fdis_iu6_t1_i1_rte_axu1), + .frn_fdis_iu6_i1_valop(frn_fdis_iu6_t1_i1_valop), + .frn_fdis_iu6_i1_ord(frn_fdis_iu6_t1_i1_ord), + .frn_fdis_iu6_i1_cord(frn_fdis_iu6_t1_i1_cord), + .frn_fdis_iu6_i1_error(frn_fdis_iu6_t1_i1_error), + .frn_fdis_iu6_i1_fusion(frn_fdis_iu6_t1_i1_fusion), + .frn_fdis_iu6_i1_spec(frn_fdis_iu6_t1_i1_spec), + .frn_fdis_iu6_i1_type_fp(frn_fdis_iu6_t1_i1_type_fp), + .frn_fdis_iu6_i1_type_ap(frn_fdis_iu6_t1_i1_type_ap), + .frn_fdis_iu6_i1_type_spv(frn_fdis_iu6_t1_i1_type_spv), + .frn_fdis_iu6_i1_type_st(frn_fdis_iu6_t1_i1_type_st), + .frn_fdis_iu6_i1_async_block(frn_fdis_iu6_t1_i1_async_block), + .frn_fdis_iu6_i1_np1_flush(frn_fdis_iu6_t1_i1_np1_flush), + .frn_fdis_iu6_i1_core_block(frn_fdis_iu6_t1_i1_core_block), + .frn_fdis_iu6_i1_isram(frn_fdis_iu6_t1_i1_isram), + .frn_fdis_iu6_i1_isload(frn_fdis_iu6_t1_i1_isload), + .frn_fdis_iu6_i1_isstore(frn_fdis_iu6_t1_i1_isstore), + .frn_fdis_iu6_i1_instr(frn_fdis_iu6_t1_i1_instr), + .frn_fdis_iu6_i1_ifar(frn_fdis_iu6_t1_i1_ifar), + .frn_fdis_iu6_i1_bta(frn_fdis_iu6_t1_i1_bta), + .frn_fdis_iu6_i1_br_pred(frn_fdis_iu6_t1_i1_br_pred), + .frn_fdis_iu6_i1_bh_update(frn_fdis_iu6_t1_i1_bh_update), + .frn_fdis_iu6_i1_bh0_hist(frn_fdis_iu6_t1_i1_bh0_hist), + .frn_fdis_iu6_i1_bh1_hist(frn_fdis_iu6_t1_i1_bh1_hist), + .frn_fdis_iu6_i1_bh2_hist(frn_fdis_iu6_t1_i1_bh2_hist), + .frn_fdis_iu6_i1_gshare(frn_fdis_iu6_t1_i1_gshare), + .frn_fdis_iu6_i1_ls_ptr(frn_fdis_iu6_t1_i1_ls_ptr), + .frn_fdis_iu6_i1_match(frn_fdis_iu6_t1_i1_match), + .frn_fdis_iu6_i1_btb_entry(frn_fdis_iu6_t1_i1_btb_entry), + .frn_fdis_iu6_i1_btb_hist(frn_fdis_iu6_t1_i1_btb_hist), + .frn_fdis_iu6_i1_bta_val(frn_fdis_iu6_t1_i1_bta_val), + .frn_fdis_iu6_i1_ilat(frn_fdis_iu6_t1_i1_ilat), + .frn_fdis_iu6_i1_t1_v(frn_fdis_iu6_t1_i1_t1_v), + .frn_fdis_iu6_i1_t1_t(frn_fdis_iu6_t1_i1_t1_t), + .frn_fdis_iu6_i1_t1_a(frn_fdis_iu6_t1_i1_t1_a), + .frn_fdis_iu6_i1_t1_p(frn_fdis_iu6_t1_i1_t1_p), + .frn_fdis_iu6_i1_t2_v(frn_fdis_iu6_t1_i1_t2_v), + .frn_fdis_iu6_i1_t2_a(frn_fdis_iu6_t1_i1_t2_a), + .frn_fdis_iu6_i1_t2_p(frn_fdis_iu6_t1_i1_t2_p), + .frn_fdis_iu6_i1_t2_t(frn_fdis_iu6_t1_i1_t2_t), + .frn_fdis_iu6_i1_t3_v(frn_fdis_iu6_t1_i1_t3_v), + .frn_fdis_iu6_i1_t3_a(frn_fdis_iu6_t1_i1_t3_a), + .frn_fdis_iu6_i1_t3_p(frn_fdis_iu6_t1_i1_t3_p), + .frn_fdis_iu6_i1_t3_t(frn_fdis_iu6_t1_i1_t3_t), + .frn_fdis_iu6_i1_s1_v(frn_fdis_iu6_t1_i1_s1_v), + .frn_fdis_iu6_i1_s1_a(frn_fdis_iu6_t1_i1_s1_a), + .frn_fdis_iu6_i1_s1_p(frn_fdis_iu6_t1_i1_s1_p), + .frn_fdis_iu6_i1_s1_itag(frn_fdis_iu6_t1_i1_s1_itag), + .frn_fdis_iu6_i1_s1_t(frn_fdis_iu6_t1_i1_s1_t), + .frn_fdis_iu6_i1_s1_dep_hit(frn_fdis_iu6_t1_i1_s1_dep_hit), + .frn_fdis_iu6_i1_s2_v(frn_fdis_iu6_t1_i1_s2_v), + .frn_fdis_iu6_i1_s2_a(frn_fdis_iu6_t1_i1_s2_a), + .frn_fdis_iu6_i1_s2_p(frn_fdis_iu6_t1_i1_s2_p), + .frn_fdis_iu6_i1_s2_itag(frn_fdis_iu6_t1_i1_s2_itag), + .frn_fdis_iu6_i1_s2_t(frn_fdis_iu6_t1_i1_s2_t), + .frn_fdis_iu6_i1_s2_dep_hit(frn_fdis_iu6_t1_i1_s2_dep_hit), + .frn_fdis_iu6_i1_s3_v(frn_fdis_iu6_t1_i1_s3_v), + .frn_fdis_iu6_i1_s3_a(frn_fdis_iu6_t1_i1_s3_a), + .frn_fdis_iu6_i1_s3_p(frn_fdis_iu6_t1_i1_s3_p), + .frn_fdis_iu6_i1_s3_itag(frn_fdis_iu6_t1_i1_s3_itag), + .frn_fdis_iu6_i1_s3_t(frn_fdis_iu6_t1_i1_s3_t), + .frn_fdis_iu6_i1_s3_dep_hit(frn_fdis_iu6_t1_i1_s3_dep_hit) + ); +`endif + + iuq_dispatch dispatch( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), + .pc_iu_func_slp_sl_thold_2(pc_iu_func_slp_sl_thold_2), + .pc_iu_sg_2(pc_iu_sg_2), + .clkoff_b(clkoff_b), + .act_dis(act_dis), + .tc_ac_ccflush_dc(tc_ac_ccflush_dc), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scan_in(scan_in[0]), + .scan_out(scan_out[0]), + + //----------------------------- + // SPR connections + //----------------------------- + .spr_cpcr_we(spr_cpcr_we), + .spr_t0_cpcr2_fx0_cnt(spr_t0_cpcr2_fx0_cnt), + .spr_t0_cpcr2_fx1_cnt(spr_t0_cpcr2_fx1_cnt), + .spr_t0_cpcr2_lq_cnt(spr_t0_cpcr2_lq_cnt), + .spr_t0_cpcr2_sq_cnt(spr_t0_cpcr2_sq_cnt), + .spr_t0_cpcr3_fu0_cnt(spr_t0_cpcr3_fu0_cnt), + .spr_t0_cpcr3_fu1_cnt(spr_t0_cpcr3_fu1_cnt), + .spr_t0_cpcr4_fx0_cnt(spr_t0_cpcr4_fx0_cnt), + .spr_t0_cpcr4_fx1_cnt(spr_t0_cpcr4_fx1_cnt), + .spr_t0_cpcr4_lq_cnt(spr_t0_cpcr4_lq_cnt), + .spr_t0_cpcr4_sq_cnt(spr_t0_cpcr4_sq_cnt), + .spr_t0_cpcr5_fu0_cnt(spr_t0_cpcr5_fu0_cnt), + .spr_t0_cpcr5_fu1_cnt(spr_t0_cpcr5_fu1_cnt), +`ifndef THREADS1 + .spr_t1_cpcr2_fx0_cnt(spr_t1_cpcr2_fx0_cnt), + .spr_t1_cpcr2_fx1_cnt(spr_t1_cpcr2_fx1_cnt), + .spr_t1_cpcr2_lq_cnt(spr_t1_cpcr2_lq_cnt), + .spr_t1_cpcr2_sq_cnt(spr_t1_cpcr2_sq_cnt), + .spr_t1_cpcr3_fu0_cnt(spr_t1_cpcr3_fu0_cnt), + .spr_t1_cpcr3_fu1_cnt(spr_t1_cpcr3_fu1_cnt), + .spr_t1_cpcr4_fx0_cnt(spr_t1_cpcr4_fx0_cnt), + .spr_t1_cpcr4_fx1_cnt(spr_t1_cpcr4_fx1_cnt), + .spr_t1_cpcr4_lq_cnt(spr_t1_cpcr4_lq_cnt), + .spr_t1_cpcr4_sq_cnt(spr_t1_cpcr4_sq_cnt), + .spr_t1_cpcr5_fu0_cnt(spr_t1_cpcr5_fu0_cnt), + .spr_t1_cpcr5_fu1_cnt(spr_t1_cpcr5_fu1_cnt), +`endif + .spr_cpcr0_fx0_cnt(spr_cpcr0_fx0_cnt), + .spr_cpcr0_fx1_cnt(spr_cpcr0_fx1_cnt), + .spr_cpcr0_lq_cnt(spr_cpcr0_lq_cnt), + .spr_cpcr0_sq_cnt(spr_cpcr0_sq_cnt), + .spr_cpcr1_fu0_cnt(spr_cpcr1_fu0_cnt), + .spr_cpcr1_fu1_cnt(spr_cpcr1_fu1_cnt), + .spr_high_pri_mask(spr_high_pri_mask), + .spr_med_pri_mask(spr_med_pri_mask), + .spr_t0_low_pri_count(spr_t0_low_pri_count), +`ifndef THREADS1 + .spr_t1_low_pri_count(spr_t1_low_pri_count), +`endif + + //------------------------------- + // Performance interface with I$ + //------------------------------- + .pc_iu_event_bus_enable(pc_iu_event_bus_enable), + .perf_iu6_stall(perf_iu6_stall), + .perf_iu6_dispatch_fx0(perf_iu6_dispatch_fx0), + .perf_iu6_dispatch_fx1(perf_iu6_dispatch_fx1), + .perf_iu6_dispatch_lq(perf_iu6_dispatch_lq), + .perf_iu6_dispatch_axu0(perf_iu6_dispatch_axu0), + .perf_iu6_dispatch_axu1(perf_iu6_dispatch_axu1), + .perf_iu6_fx0_credit_stall(perf_iu6_fx0_credit_stall), + .perf_iu6_fx1_credit_stall(perf_iu6_fx1_credit_stall), + .perf_iu6_lq_credit_stall(perf_iu6_lq_credit_stall), + .perf_iu6_sq_credit_stall(perf_iu6_sq_credit_stall), + .perf_iu6_axu0_credit_stall(perf_iu6_axu0_credit_stall), + .perf_iu6_axu1_credit_stall(perf_iu6_axu1_credit_stall), + + .iu_pc_fx0_credit_ok(iu_pc_fx0_credit_ok), + .iu_pc_fx1_credit_ok(iu_pc_fx1_credit_ok), + .iu_pc_lq_credit_ok(iu_pc_lq_credit_ok), + .iu_pc_sq_credit_ok(iu_pc_sq_credit_ok), + .iu_pc_axu0_credit_ok(iu_pc_axu0_credit_ok), + .iu_pc_axu1_credit_ok(iu_pc_axu1_credit_ok), + + //---------------------------- + // Credit Interface with IU + //---------------------------- + .rv_iu_fx0_credit_free(rv_iu_fx0_credit_free), + .rv_iu_fx1_credit_free(rv_iu_fx1_credit_free), // Need to add 2nd unit someday + .lq_iu_credit_free(lq_iu_credit_free), + .sq_iu_credit_free(sq_iu_credit_free), + .axu0_iu_credit_free(axu0_iu_credit_free), // credit free from axu reservation station + .axu1_iu_credit_free(axu1_iu_credit_free), // credit free from axu reservation station + + .cp_flush(cp_flush), + .xu_iu_run_thread(xu_iu_run_thread), + .iu_xu_credits_returned(iu_xu_credits_returned), + + //---------------------------------------------------------------- + // Interface with rename + //---------------------------------------------------------------- + .frn_fdis_iu6_t0_i0_vld(frn_fdis_iu6_t0_i0_vld), + .frn_fdis_iu6_t0_i0_itag(frn_fdis_iu6_t0_i0_itag), + .frn_fdis_iu6_t0_i0_ucode(frn_fdis_iu6_t0_i0_ucode), + .frn_fdis_iu6_t0_i0_ucode_cnt(frn_fdis_iu6_t0_i0_ucode_cnt), + .frn_fdis_iu6_t0_i0_2ucode(frn_fdis_iu6_t0_i0_2ucode), + .frn_fdis_iu6_t0_i0_fuse_nop(frn_fdis_iu6_t0_i0_fuse_nop), + .frn_fdis_iu6_t0_i0_rte_lq(frn_fdis_iu6_t0_i0_rte_lq), + .frn_fdis_iu6_t0_i0_rte_sq(frn_fdis_iu6_t0_i0_rte_sq), + .frn_fdis_iu6_t0_i0_rte_fx0(frn_fdis_iu6_t0_i0_rte_fx0), + .frn_fdis_iu6_t0_i0_rte_fx1(frn_fdis_iu6_t0_i0_rte_fx1), + .frn_fdis_iu6_t0_i0_rte_axu0(frn_fdis_iu6_t0_i0_rte_axu0), + .frn_fdis_iu6_t0_i0_rte_axu1(frn_fdis_iu6_t0_i0_rte_axu1), + .frn_fdis_iu6_t0_i0_valop(frn_fdis_iu6_t0_i0_valop), + .frn_fdis_iu6_t0_i0_ord(frn_fdis_iu6_t0_i0_ord), + .frn_fdis_iu6_t0_i0_cord(frn_fdis_iu6_t0_i0_cord), + .frn_fdis_iu6_t0_i0_error(frn_fdis_iu6_t0_i0_error), + .frn_fdis_iu6_t0_i0_btb_entry(frn_fdis_iu6_t0_i0_btb_entry), + .frn_fdis_iu6_t0_i0_btb_hist(frn_fdis_iu6_t0_i0_btb_hist), + .frn_fdis_iu6_t0_i0_bta_val(frn_fdis_iu6_t0_i0_bta_val), + .frn_fdis_iu6_t0_i0_fusion(frn_fdis_iu6_t0_i0_fusion), + .frn_fdis_iu6_t0_i0_spec(frn_fdis_iu6_t0_i0_spec), + .frn_fdis_iu6_t0_i0_type_fp(frn_fdis_iu6_t0_i0_type_fp), + .frn_fdis_iu6_t0_i0_type_ap(frn_fdis_iu6_t0_i0_type_ap), + .frn_fdis_iu6_t0_i0_type_spv(frn_fdis_iu6_t0_i0_type_spv), + .frn_fdis_iu6_t0_i0_type_st(frn_fdis_iu6_t0_i0_type_st), + .frn_fdis_iu6_t0_i0_async_block(frn_fdis_iu6_t0_i0_async_block), + .frn_fdis_iu6_t0_i0_np1_flush(frn_fdis_iu6_t0_i0_np1_flush), + .frn_fdis_iu6_t0_i0_core_block(frn_fdis_iu6_t0_i0_core_block), + .frn_fdis_iu6_t0_i0_isram(frn_fdis_iu6_t0_i0_isram), + .frn_fdis_iu6_t0_i0_isload(frn_fdis_iu6_t0_i0_isload), + .frn_fdis_iu6_t0_i0_isstore(frn_fdis_iu6_t0_i0_isstore), + .frn_fdis_iu6_t0_i0_instr(frn_fdis_iu6_t0_i0_instr), + .frn_fdis_iu6_t0_i0_ifar(frn_fdis_iu6_t0_i0_ifar), + .frn_fdis_iu6_t0_i0_bta(frn_fdis_iu6_t0_i0_bta), + .frn_fdis_iu6_t0_i0_br_pred(frn_fdis_iu6_t0_i0_br_pred), + .frn_fdis_iu6_t0_i0_bh_update(frn_fdis_iu6_t0_i0_bh_update), + .frn_fdis_iu6_t0_i0_bh0_hist(frn_fdis_iu6_t0_i0_bh0_hist), + .frn_fdis_iu6_t0_i0_bh1_hist(frn_fdis_iu6_t0_i0_bh1_hist), + .frn_fdis_iu6_t0_i0_bh2_hist(frn_fdis_iu6_t0_i0_bh2_hist), + .frn_fdis_iu6_t0_i0_gshare(frn_fdis_iu6_t0_i0_gshare), + .frn_fdis_iu6_t0_i0_ls_ptr(frn_fdis_iu6_t0_i0_ls_ptr), + .frn_fdis_iu6_t0_i0_match(frn_fdis_iu6_t0_i0_match), + .frn_fdis_iu6_t0_i0_ilat(frn_fdis_iu6_t0_i0_ilat), + .frn_fdis_iu6_t0_i0_t1_v(frn_fdis_iu6_t0_i0_t1_v), + .frn_fdis_iu6_t0_i0_t1_t(frn_fdis_iu6_t0_i0_t1_t), + .frn_fdis_iu6_t0_i0_t1_a(frn_fdis_iu6_t0_i0_t1_a), + .frn_fdis_iu6_t0_i0_t1_p(frn_fdis_iu6_t0_i0_t1_p), + .frn_fdis_iu6_t0_i0_t2_v(frn_fdis_iu6_t0_i0_t2_v), + .frn_fdis_iu6_t0_i0_t2_a(frn_fdis_iu6_t0_i0_t2_a), + .frn_fdis_iu6_t0_i0_t2_p(frn_fdis_iu6_t0_i0_t2_p), + .frn_fdis_iu6_t0_i0_t2_t(frn_fdis_iu6_t0_i0_t2_t), + .frn_fdis_iu6_t0_i0_t3_v(frn_fdis_iu6_t0_i0_t3_v), + .frn_fdis_iu6_t0_i0_t3_a(frn_fdis_iu6_t0_i0_t3_a), + .frn_fdis_iu6_t0_i0_t3_p(frn_fdis_iu6_t0_i0_t3_p), + .frn_fdis_iu6_t0_i0_t3_t(frn_fdis_iu6_t0_i0_t3_t), + .frn_fdis_iu6_t0_i0_s1_v(frn_fdis_iu6_t0_i0_s1_v), + .frn_fdis_iu6_t0_i0_s1_a(frn_fdis_iu6_t0_i0_s1_a), + .frn_fdis_iu6_t0_i0_s1_p(frn_fdis_iu6_t0_i0_s1_p), + .frn_fdis_iu6_t0_i0_s1_itag(frn_fdis_iu6_t0_i0_s1_itag), + .frn_fdis_iu6_t0_i0_s1_t(frn_fdis_iu6_t0_i0_s1_t), + .frn_fdis_iu6_t0_i0_s2_v(frn_fdis_iu6_t0_i0_s2_v), + .frn_fdis_iu6_t0_i0_s2_a(frn_fdis_iu6_t0_i0_s2_a), + .frn_fdis_iu6_t0_i0_s2_p(frn_fdis_iu6_t0_i0_s2_p), + .frn_fdis_iu6_t0_i0_s2_itag(frn_fdis_iu6_t0_i0_s2_itag), + .frn_fdis_iu6_t0_i0_s2_t(frn_fdis_iu6_t0_i0_s2_t), + .frn_fdis_iu6_t0_i0_s3_v(frn_fdis_iu6_t0_i0_s3_v), + .frn_fdis_iu6_t0_i0_s3_a(frn_fdis_iu6_t0_i0_s3_a), + .frn_fdis_iu6_t0_i0_s3_p(frn_fdis_iu6_t0_i0_s3_p), + .frn_fdis_iu6_t0_i0_s3_itag(frn_fdis_iu6_t0_i0_s3_itag), + .frn_fdis_iu6_t0_i0_s3_t(frn_fdis_iu6_t0_i0_s3_t), + + .frn_fdis_iu6_t0_i1_vld(frn_fdis_iu6_t0_i1_vld), + .frn_fdis_iu6_t0_i1_itag(frn_fdis_iu6_t0_i1_itag), + .frn_fdis_iu6_t0_i1_ucode(frn_fdis_iu6_t0_i1_ucode), + .frn_fdis_iu6_t0_i1_ucode_cnt(frn_fdis_iu6_t0_i1_ucode_cnt), + .frn_fdis_iu6_t0_i1_fuse_nop(frn_fdis_iu6_t0_i1_fuse_nop), + .frn_fdis_iu6_t0_i1_rte_lq(frn_fdis_iu6_t0_i1_rte_lq), + .frn_fdis_iu6_t0_i1_rte_sq(frn_fdis_iu6_t0_i1_rte_sq), + .frn_fdis_iu6_t0_i1_rte_fx0(frn_fdis_iu6_t0_i1_rte_fx0), + .frn_fdis_iu6_t0_i1_rte_fx1(frn_fdis_iu6_t0_i1_rte_fx1), + .frn_fdis_iu6_t0_i1_rte_axu0(frn_fdis_iu6_t0_i1_rte_axu0), + .frn_fdis_iu6_t0_i1_rte_axu1(frn_fdis_iu6_t0_i1_rte_axu1), + .frn_fdis_iu6_t0_i1_valop(frn_fdis_iu6_t0_i1_valop), + .frn_fdis_iu6_t0_i1_ord(frn_fdis_iu6_t0_i1_ord), + .frn_fdis_iu6_t0_i1_cord(frn_fdis_iu6_t0_i1_cord), + .frn_fdis_iu6_t0_i1_error(frn_fdis_iu6_t0_i1_error), + .frn_fdis_iu6_t0_i1_btb_entry(frn_fdis_iu6_t0_i1_btb_entry), + .frn_fdis_iu6_t0_i1_btb_hist(frn_fdis_iu6_t0_i1_btb_hist), + .frn_fdis_iu6_t0_i1_bta_val(frn_fdis_iu6_t0_i1_bta_val), + .frn_fdis_iu6_t0_i1_fusion(frn_fdis_iu6_t0_i1_fusion), + .frn_fdis_iu6_t0_i1_spec(frn_fdis_iu6_t0_i1_spec), + .frn_fdis_iu6_t0_i1_type_fp(frn_fdis_iu6_t0_i1_type_fp), + .frn_fdis_iu6_t0_i1_type_ap(frn_fdis_iu6_t0_i1_type_ap), + .frn_fdis_iu6_t0_i1_type_spv(frn_fdis_iu6_t0_i1_type_spv), + .frn_fdis_iu6_t0_i1_type_st(frn_fdis_iu6_t0_i1_type_st), + .frn_fdis_iu6_t0_i1_async_block(frn_fdis_iu6_t0_i1_async_block), + .frn_fdis_iu6_t0_i1_np1_flush(frn_fdis_iu6_t0_i1_np1_flush), + .frn_fdis_iu6_t0_i1_core_block(frn_fdis_iu6_t0_i1_core_block), + .frn_fdis_iu6_t0_i1_isram(frn_fdis_iu6_t0_i1_isram), + .frn_fdis_iu6_t0_i1_isload(frn_fdis_iu6_t0_i1_isload), + .frn_fdis_iu6_t0_i1_isstore(frn_fdis_iu6_t0_i1_isstore), + .frn_fdis_iu6_t0_i1_instr(frn_fdis_iu6_t0_i1_instr), + .frn_fdis_iu6_t0_i1_ifar(frn_fdis_iu6_t0_i1_ifar), + .frn_fdis_iu6_t0_i1_bta(frn_fdis_iu6_t0_i1_bta), + .frn_fdis_iu6_t0_i1_br_pred(frn_fdis_iu6_t0_i1_br_pred), + .frn_fdis_iu6_t0_i1_bh_update(frn_fdis_iu6_t0_i1_bh_update), + .frn_fdis_iu6_t0_i1_bh0_hist(frn_fdis_iu6_t0_i1_bh0_hist), + .frn_fdis_iu6_t0_i1_bh1_hist(frn_fdis_iu6_t0_i1_bh1_hist), + .frn_fdis_iu6_t0_i1_bh2_hist(frn_fdis_iu6_t0_i1_bh2_hist), + .frn_fdis_iu6_t0_i1_gshare(frn_fdis_iu6_t0_i1_gshare), + .frn_fdis_iu6_t0_i1_ls_ptr(frn_fdis_iu6_t0_i1_ls_ptr), + .frn_fdis_iu6_t0_i1_match(frn_fdis_iu6_t0_i1_match), + .frn_fdis_iu6_t0_i1_ilat(frn_fdis_iu6_t0_i1_ilat), + .frn_fdis_iu6_t0_i1_t1_v(frn_fdis_iu6_t0_i1_t1_v), + .frn_fdis_iu6_t0_i1_t1_t(frn_fdis_iu6_t0_i1_t1_t), + .frn_fdis_iu6_t0_i1_t1_a(frn_fdis_iu6_t0_i1_t1_a), + .frn_fdis_iu6_t0_i1_t1_p(frn_fdis_iu6_t0_i1_t1_p), + .frn_fdis_iu6_t0_i1_t2_v(frn_fdis_iu6_t0_i1_t2_v), + .frn_fdis_iu6_t0_i1_t2_a(frn_fdis_iu6_t0_i1_t2_a), + .frn_fdis_iu6_t0_i1_t2_p(frn_fdis_iu6_t0_i1_t2_p), + .frn_fdis_iu6_t0_i1_t2_t(frn_fdis_iu6_t0_i1_t2_t), + .frn_fdis_iu6_t0_i1_t3_v(frn_fdis_iu6_t0_i1_t3_v), + .frn_fdis_iu6_t0_i1_t3_a(frn_fdis_iu6_t0_i1_t3_a), + .frn_fdis_iu6_t0_i1_t3_p(frn_fdis_iu6_t0_i1_t3_p), + .frn_fdis_iu6_t0_i1_t3_t(frn_fdis_iu6_t0_i1_t3_t), + .frn_fdis_iu6_t0_i1_s1_v(frn_fdis_iu6_t0_i1_s1_v), + .frn_fdis_iu6_t0_i1_s1_a(frn_fdis_iu6_t0_i1_s1_a), + .frn_fdis_iu6_t0_i1_s1_p(frn_fdis_iu6_t0_i1_s1_p), + .frn_fdis_iu6_t0_i1_s1_itag(frn_fdis_iu6_t0_i1_s1_itag), + .frn_fdis_iu6_t0_i1_s1_t(frn_fdis_iu6_t0_i1_s1_t), + .frn_fdis_iu6_t0_i1_s1_dep_hit(frn_fdis_iu6_t0_i1_s1_dep_hit), + .frn_fdis_iu6_t0_i1_s2_v(frn_fdis_iu6_t0_i1_s2_v), + .frn_fdis_iu6_t0_i1_s2_a(frn_fdis_iu6_t0_i1_s2_a), + .frn_fdis_iu6_t0_i1_s2_p(frn_fdis_iu6_t0_i1_s2_p), + .frn_fdis_iu6_t0_i1_s2_itag(frn_fdis_iu6_t0_i1_s2_itag), + .frn_fdis_iu6_t0_i1_s2_t(frn_fdis_iu6_t0_i1_s2_t), + .frn_fdis_iu6_t0_i1_s2_dep_hit(frn_fdis_iu6_t0_i1_s2_dep_hit), + .frn_fdis_iu6_t0_i1_s3_v(frn_fdis_iu6_t0_i1_s3_v), + .frn_fdis_iu6_t0_i1_s3_a(frn_fdis_iu6_t0_i1_s3_a), + .frn_fdis_iu6_t0_i1_s3_p(frn_fdis_iu6_t0_i1_s3_p), + .frn_fdis_iu6_t0_i1_s3_itag(frn_fdis_iu6_t0_i1_s3_itag), + .frn_fdis_iu6_t0_i1_s3_t(frn_fdis_iu6_t0_i1_s3_t), + .frn_fdis_iu6_t0_i1_s3_dep_hit(frn_fdis_iu6_t0_i1_s3_dep_hit), +`ifndef THREADS1 + .frn_fdis_iu6_t1_i0_vld(frn_fdis_iu6_t1_i0_vld), + .frn_fdis_iu6_t1_i0_itag(frn_fdis_iu6_t1_i0_itag), + .frn_fdis_iu6_t1_i0_ucode(frn_fdis_iu6_t1_i0_ucode), + .frn_fdis_iu6_t1_i0_ucode_cnt(frn_fdis_iu6_t1_i0_ucode_cnt), + .frn_fdis_iu6_t1_i0_2ucode(frn_fdis_iu6_t1_i0_2ucode), + .frn_fdis_iu6_t1_i0_fuse_nop(frn_fdis_iu6_t1_i0_fuse_nop), + .frn_fdis_iu6_t1_i0_rte_lq(frn_fdis_iu6_t1_i0_rte_lq), + .frn_fdis_iu6_t1_i0_rte_sq(frn_fdis_iu6_t1_i0_rte_sq), + .frn_fdis_iu6_t1_i0_rte_fx0(frn_fdis_iu6_t1_i0_rte_fx0), + .frn_fdis_iu6_t1_i0_rte_fx1(frn_fdis_iu6_t1_i0_rte_fx1), + .frn_fdis_iu6_t1_i0_rte_axu0(frn_fdis_iu6_t1_i0_rte_axu0), + .frn_fdis_iu6_t1_i0_rte_axu1(frn_fdis_iu6_t1_i0_rte_axu1), + .frn_fdis_iu6_t1_i0_valop(frn_fdis_iu6_t1_i0_valop), + .frn_fdis_iu6_t1_i0_ord(frn_fdis_iu6_t1_i0_ord), + .frn_fdis_iu6_t1_i0_cord(frn_fdis_iu6_t1_i0_cord), + .frn_fdis_iu6_t1_i0_error(frn_fdis_iu6_t1_i0_error), + .frn_fdis_iu6_t1_i0_btb_entry(frn_fdis_iu6_t1_i0_btb_entry), + .frn_fdis_iu6_t1_i0_btb_hist(frn_fdis_iu6_t1_i0_btb_hist), + .frn_fdis_iu6_t1_i0_bta_val(frn_fdis_iu6_t1_i0_bta_val), + .frn_fdis_iu6_t1_i0_fusion(frn_fdis_iu6_t1_i0_fusion), + .frn_fdis_iu6_t1_i0_spec(frn_fdis_iu6_t1_i0_spec), + .frn_fdis_iu6_t1_i0_type_fp(frn_fdis_iu6_t1_i0_type_fp), + .frn_fdis_iu6_t1_i0_type_ap(frn_fdis_iu6_t1_i0_type_ap), + .frn_fdis_iu6_t1_i0_type_spv(frn_fdis_iu6_t1_i0_type_spv), + .frn_fdis_iu6_t1_i0_type_st(frn_fdis_iu6_t1_i0_type_st), + .frn_fdis_iu6_t1_i0_async_block(frn_fdis_iu6_t1_i0_async_block), + .frn_fdis_iu6_t1_i0_np1_flush(frn_fdis_iu6_t1_i0_np1_flush), + .frn_fdis_iu6_t1_i0_core_block(frn_fdis_iu6_t1_i0_core_block), + .frn_fdis_iu6_t1_i0_isram(frn_fdis_iu6_t1_i0_isram), + .frn_fdis_iu6_t1_i0_isload(frn_fdis_iu6_t1_i0_isload), + .frn_fdis_iu6_t1_i0_isstore(frn_fdis_iu6_t1_i0_isstore), + .frn_fdis_iu6_t1_i0_instr(frn_fdis_iu6_t1_i0_instr), + .frn_fdis_iu6_t1_i0_ifar(frn_fdis_iu6_t1_i0_ifar), + .frn_fdis_iu6_t1_i0_bta(frn_fdis_iu6_t1_i0_bta), + .frn_fdis_iu6_t1_i0_br_pred(frn_fdis_iu6_t1_i0_br_pred), + .frn_fdis_iu6_t1_i0_bh_update(frn_fdis_iu6_t1_i0_bh_update), + .frn_fdis_iu6_t1_i0_bh0_hist(frn_fdis_iu6_t1_i0_bh0_hist), + .frn_fdis_iu6_t1_i0_bh1_hist(frn_fdis_iu6_t1_i0_bh1_hist), + .frn_fdis_iu6_t1_i0_bh2_hist(frn_fdis_iu6_t1_i0_bh2_hist), + .frn_fdis_iu6_t1_i0_gshare(frn_fdis_iu6_t1_i0_gshare), + .frn_fdis_iu6_t1_i0_ls_ptr(frn_fdis_iu6_t1_i0_ls_ptr), + .frn_fdis_iu6_t1_i0_match(frn_fdis_iu6_t1_i0_match), + .frn_fdis_iu6_t1_i0_ilat(frn_fdis_iu6_t1_i0_ilat), + .frn_fdis_iu6_t1_i0_t1_v(frn_fdis_iu6_t1_i0_t1_v), + .frn_fdis_iu6_t1_i0_t1_t(frn_fdis_iu6_t1_i0_t1_t), + .frn_fdis_iu6_t1_i0_t1_a(frn_fdis_iu6_t1_i0_t1_a), + .frn_fdis_iu6_t1_i0_t1_p(frn_fdis_iu6_t1_i0_t1_p), + .frn_fdis_iu6_t1_i0_t2_v(frn_fdis_iu6_t1_i0_t2_v), + .frn_fdis_iu6_t1_i0_t2_a(frn_fdis_iu6_t1_i0_t2_a), + .frn_fdis_iu6_t1_i0_t2_p(frn_fdis_iu6_t1_i0_t2_p), + .frn_fdis_iu6_t1_i0_t2_t(frn_fdis_iu6_t1_i0_t2_t), + .frn_fdis_iu6_t1_i0_t3_v(frn_fdis_iu6_t1_i0_t3_v), + .frn_fdis_iu6_t1_i0_t3_a(frn_fdis_iu6_t1_i0_t3_a), + .frn_fdis_iu6_t1_i0_t3_p(frn_fdis_iu6_t1_i0_t3_p), + .frn_fdis_iu6_t1_i0_t3_t(frn_fdis_iu6_t1_i0_t3_t), + .frn_fdis_iu6_t1_i0_s1_v(frn_fdis_iu6_t1_i0_s1_v), + .frn_fdis_iu6_t1_i0_s1_a(frn_fdis_iu6_t1_i0_s1_a), + .frn_fdis_iu6_t1_i0_s1_p(frn_fdis_iu6_t1_i0_s1_p), + .frn_fdis_iu6_t1_i0_s1_itag(frn_fdis_iu6_t1_i0_s1_itag), + .frn_fdis_iu6_t1_i0_s1_t(frn_fdis_iu6_t1_i0_s1_t), + .frn_fdis_iu6_t1_i0_s2_v(frn_fdis_iu6_t1_i0_s2_v), + .frn_fdis_iu6_t1_i0_s2_a(frn_fdis_iu6_t1_i0_s2_a), + .frn_fdis_iu6_t1_i0_s2_p(frn_fdis_iu6_t1_i0_s2_p), + .frn_fdis_iu6_t1_i0_s2_itag(frn_fdis_iu6_t1_i0_s2_itag), + .frn_fdis_iu6_t1_i0_s2_t(frn_fdis_iu6_t1_i0_s2_t), + .frn_fdis_iu6_t1_i0_s3_v(frn_fdis_iu6_t1_i0_s3_v), + .frn_fdis_iu6_t1_i0_s3_a(frn_fdis_iu6_t1_i0_s3_a), + .frn_fdis_iu6_t1_i0_s3_p(frn_fdis_iu6_t1_i0_s3_p), + .frn_fdis_iu6_t1_i0_s3_itag(frn_fdis_iu6_t1_i0_s3_itag), + .frn_fdis_iu6_t1_i0_s3_t(frn_fdis_iu6_t1_i0_s3_t), + + .frn_fdis_iu6_t1_i1_vld(frn_fdis_iu6_t1_i1_vld), + .frn_fdis_iu6_t1_i1_itag(frn_fdis_iu6_t1_i1_itag), + .frn_fdis_iu6_t1_i1_ucode(frn_fdis_iu6_t1_i1_ucode), + .frn_fdis_iu6_t1_i1_ucode_cnt(frn_fdis_iu6_t1_i1_ucode_cnt), + .frn_fdis_iu6_t1_i1_fuse_nop(frn_fdis_iu6_t1_i1_fuse_nop), + .frn_fdis_iu6_t1_i1_rte_lq(frn_fdis_iu6_t1_i1_rte_lq), + .frn_fdis_iu6_t1_i1_rte_sq(frn_fdis_iu6_t1_i1_rte_sq), + .frn_fdis_iu6_t1_i1_rte_fx0(frn_fdis_iu6_t1_i1_rte_fx0), + .frn_fdis_iu6_t1_i1_rte_fx1(frn_fdis_iu6_t1_i1_rte_fx1), + .frn_fdis_iu6_t1_i1_rte_axu0(frn_fdis_iu6_t1_i1_rte_axu0), + .frn_fdis_iu6_t1_i1_rte_axu1(frn_fdis_iu6_t1_i1_rte_axu1), + .frn_fdis_iu6_t1_i1_valop(frn_fdis_iu6_t1_i1_valop), + .frn_fdis_iu6_t1_i1_ord(frn_fdis_iu6_t1_i1_ord), + .frn_fdis_iu6_t1_i1_cord(frn_fdis_iu6_t1_i1_cord), + .frn_fdis_iu6_t1_i1_error(frn_fdis_iu6_t1_i1_error), + .frn_fdis_iu6_t1_i1_btb_entry(frn_fdis_iu6_t1_i1_btb_entry), + .frn_fdis_iu6_t1_i1_btb_hist(frn_fdis_iu6_t1_i1_btb_hist), + .frn_fdis_iu6_t1_i1_bta_val(frn_fdis_iu6_t1_i1_bta_val), + .frn_fdis_iu6_t1_i1_fusion(frn_fdis_iu6_t1_i1_fusion), + .frn_fdis_iu6_t1_i1_spec(frn_fdis_iu6_t1_i1_spec), + .frn_fdis_iu6_t1_i1_type_fp(frn_fdis_iu6_t1_i1_type_fp), + .frn_fdis_iu6_t1_i1_type_ap(frn_fdis_iu6_t1_i1_type_ap), + .frn_fdis_iu6_t1_i1_type_spv(frn_fdis_iu6_t1_i1_type_spv), + .frn_fdis_iu6_t1_i1_type_st(frn_fdis_iu6_t1_i1_type_st), + .frn_fdis_iu6_t1_i1_async_block(frn_fdis_iu6_t1_i1_async_block), + .frn_fdis_iu6_t1_i1_np1_flush(frn_fdis_iu6_t1_i1_np1_flush), + .frn_fdis_iu6_t1_i1_core_block(frn_fdis_iu6_t1_i1_core_block), + .frn_fdis_iu6_t1_i1_isram(frn_fdis_iu6_t1_i1_isram), + .frn_fdis_iu6_t1_i1_isload(frn_fdis_iu6_t1_i1_isload), + .frn_fdis_iu6_t1_i1_isstore(frn_fdis_iu6_t1_i1_isstore), + .frn_fdis_iu6_t1_i1_instr(frn_fdis_iu6_t1_i1_instr), + .frn_fdis_iu6_t1_i1_ifar(frn_fdis_iu6_t1_i1_ifar), + .frn_fdis_iu6_t1_i1_bta(frn_fdis_iu6_t1_i1_bta), + .frn_fdis_iu6_t1_i1_br_pred(frn_fdis_iu6_t1_i1_br_pred), + .frn_fdis_iu6_t1_i1_bh_update(frn_fdis_iu6_t1_i1_bh_update), + .frn_fdis_iu6_t1_i1_bh0_hist(frn_fdis_iu6_t1_i1_bh0_hist), + .frn_fdis_iu6_t1_i1_bh1_hist(frn_fdis_iu6_t1_i1_bh1_hist), + .frn_fdis_iu6_t1_i1_bh2_hist(frn_fdis_iu6_t1_i1_bh2_hist), + .frn_fdis_iu6_t1_i1_gshare(frn_fdis_iu6_t1_i1_gshare), + .frn_fdis_iu6_t1_i1_ls_ptr(frn_fdis_iu6_t1_i1_ls_ptr), + .frn_fdis_iu6_t1_i1_match(frn_fdis_iu6_t1_i1_match), + .frn_fdis_iu6_t1_i1_ilat(frn_fdis_iu6_t1_i1_ilat), + .frn_fdis_iu6_t1_i1_t1_v(frn_fdis_iu6_t1_i1_t1_v), + .frn_fdis_iu6_t1_i1_t1_t(frn_fdis_iu6_t1_i1_t1_t), + .frn_fdis_iu6_t1_i1_t1_a(frn_fdis_iu6_t1_i1_t1_a), + .frn_fdis_iu6_t1_i1_t1_p(frn_fdis_iu6_t1_i1_t1_p), + .frn_fdis_iu6_t1_i1_t2_v(frn_fdis_iu6_t1_i1_t2_v), + .frn_fdis_iu6_t1_i1_t2_a(frn_fdis_iu6_t1_i1_t2_a), + .frn_fdis_iu6_t1_i1_t2_p(frn_fdis_iu6_t1_i1_t2_p), + .frn_fdis_iu6_t1_i1_t2_t(frn_fdis_iu6_t1_i1_t2_t), + .frn_fdis_iu6_t1_i1_t3_v(frn_fdis_iu6_t1_i1_t3_v), + .frn_fdis_iu6_t1_i1_t3_a(frn_fdis_iu6_t1_i1_t3_a), + .frn_fdis_iu6_t1_i1_t3_p(frn_fdis_iu6_t1_i1_t3_p), + .frn_fdis_iu6_t1_i1_t3_t(frn_fdis_iu6_t1_i1_t3_t), + .frn_fdis_iu6_t1_i1_s1_v(frn_fdis_iu6_t1_i1_s1_v), + .frn_fdis_iu6_t1_i1_s1_a(frn_fdis_iu6_t1_i1_s1_a), + .frn_fdis_iu6_t1_i1_s1_p(frn_fdis_iu6_t1_i1_s1_p), + .frn_fdis_iu6_t1_i1_s1_itag(frn_fdis_iu6_t1_i1_s1_itag), + .frn_fdis_iu6_t1_i1_s1_t(frn_fdis_iu6_t1_i1_s1_t), + .frn_fdis_iu6_t1_i1_s1_dep_hit(frn_fdis_iu6_t1_i1_s1_dep_hit), + .frn_fdis_iu6_t1_i1_s2_v(frn_fdis_iu6_t1_i1_s2_v), + .frn_fdis_iu6_t1_i1_s2_a(frn_fdis_iu6_t1_i1_s2_a), + .frn_fdis_iu6_t1_i1_s2_p(frn_fdis_iu6_t1_i1_s2_p), + .frn_fdis_iu6_t1_i1_s2_itag(frn_fdis_iu6_t1_i1_s2_itag), + .frn_fdis_iu6_t1_i1_s2_t(frn_fdis_iu6_t1_i1_s2_t), + .frn_fdis_iu6_t1_i1_s2_dep_hit(frn_fdis_iu6_t1_i1_s2_dep_hit), + .frn_fdis_iu6_t1_i1_s3_v(frn_fdis_iu6_t1_i1_s3_v), + .frn_fdis_iu6_t1_i1_s3_a(frn_fdis_iu6_t1_i1_s3_a), + .frn_fdis_iu6_t1_i1_s3_p(frn_fdis_iu6_t1_i1_s3_p), + .frn_fdis_iu6_t1_i1_s3_itag(frn_fdis_iu6_t1_i1_s3_itag), + .frn_fdis_iu6_t1_i1_s3_t(frn_fdis_iu6_t1_i1_s3_t), + .frn_fdis_iu6_t1_i1_s3_dep_hit(frn_fdis_iu6_t1_i1_s3_dep_hit), +`endif + + //----------------------------- + // Stall from dispatch + //----------------------------- + .fdis_frn_iu6_stall(fdis_frn_iu6_stall), + + //---------------------------------------------------------------- + // Interface to reservation station - Completion is snooping also + //---------------------------------------------------------------- + .iu_rv_iu6_t0_i0_vld(iu_rv_iu6_t0_i0_vld), + .iu_rv_iu6_t0_i0_act(iu_rv_iu6_t0_i0_act), + .iu_rv_iu6_t0_i0_itag(iu_rv_iu6_t0_i0_itag), + .iu_rv_iu6_t0_i0_ucode(iu_rv_iu6_t0_i0_ucode), + .iu_rv_iu6_t0_i0_ucode_cnt(iu_rv_iu6_t0_i0_ucode_cnt), + .iu_rv_iu6_t0_i0_2ucode(iu_rv_iu6_t0_i0_2ucode), + .iu_rv_iu6_t0_i0_fuse_nop(iu_rv_iu6_t0_i0_fuse_nop), + .iu_rv_iu6_t0_i0_rte_lq(iu_rv_iu6_t0_i0_rte_lq), + .iu_rv_iu6_t0_i0_rte_sq(iu_rv_iu6_t0_i0_rte_sq), + .iu_rv_iu6_t0_i0_rte_fx0(iu_rv_iu6_t0_i0_rte_fx0), + .iu_rv_iu6_t0_i0_rte_fx1(iu_rv_iu6_t0_i0_rte_fx1), + .iu_rv_iu6_t0_i0_rte_axu0(iu_rv_iu6_t0_i0_rte_axu0), + .iu_rv_iu6_t0_i0_rte_axu1(iu_rv_iu6_t0_i0_rte_axu1), + .iu_rv_iu6_t0_i0_valop(iu_rv_iu6_t0_i0_valop), + .iu_rv_iu6_t0_i0_ord(iu_rv_iu6_t0_i0_ord), + .iu_rv_iu6_t0_i0_cord(iu_rv_iu6_t0_i0_cord), + .iu_rv_iu6_t0_i0_error(iu_rv_iu6_t0_i0_error), + .iu_rv_iu6_t0_i0_btb_entry(iu_rv_iu6_t0_i0_btb_entry), + .iu_rv_iu6_t0_i0_btb_hist(iu_rv_iu6_t0_i0_btb_hist), + .iu_rv_iu6_t0_i0_bta_val(iu_rv_iu6_t0_i0_bta_val), + .iu_rv_iu6_t0_i0_fusion(iu_rv_iu6_t0_i0_fusion), + .iu_rv_iu6_t0_i0_spec(iu_rv_iu6_t0_i0_spec), + .iu_rv_iu6_t0_i0_type_fp(iu_rv_iu6_t0_i0_type_fp), + .iu_rv_iu6_t0_i0_type_ap(iu_rv_iu6_t0_i0_type_ap), + .iu_rv_iu6_t0_i0_type_spv(iu_rv_iu6_t0_i0_type_spv), + .iu_rv_iu6_t0_i0_type_st(iu_rv_iu6_t0_i0_type_st), + .iu_rv_iu6_t0_i0_async_block(iu_rv_iu6_t0_i0_async_block), + .iu_rv_iu6_t0_i0_np1_flush(iu_rv_iu6_t0_i0_np1_flush), + .iu_rv_iu6_t0_i0_isram(iu_rv_iu6_t0_i0_isram), + .iu_rv_iu6_t0_i0_isload(iu_rv_iu6_t0_i0_isload), + .iu_rv_iu6_t0_i0_isstore(iu_rv_iu6_t0_i0_isstore), + .iu_rv_iu6_t0_i0_instr(iu_rv_iu6_t0_i0_instr), + .iu_rv_iu6_t0_i0_ifar(iu_rv_iu6_t0_i0_ifar), + .iu_rv_iu6_t0_i0_bta(iu_rv_iu6_t0_i0_bta), + .iu_rv_iu6_t0_i0_br_pred(iu_rv_iu6_t0_i0_br_pred), + .iu_rv_iu6_t0_i0_bh_update(iu_rv_iu6_t0_i0_bh_update), + .iu_rv_iu6_t0_i0_bh0_hist(iu_rv_iu6_t0_i0_bh0_hist), + .iu_rv_iu6_t0_i0_bh1_hist(iu_rv_iu6_t0_i0_bh1_hist), + .iu_rv_iu6_t0_i0_bh2_hist(iu_rv_iu6_t0_i0_bh2_hist), + .iu_rv_iu6_t0_i0_gshare(iu_rv_iu6_t0_i0_gshare), + .iu_rv_iu6_t0_i0_ls_ptr(iu_rv_iu6_t0_i0_ls_ptr), + .iu_rv_iu6_t0_i0_match(iu_rv_iu6_t0_i0_match), + .iu_rv_iu6_t0_i0_ilat(iu_rv_iu6_t0_i0_ilat), + .iu_rv_iu6_t0_i0_t1_v(iu_rv_iu6_t0_i0_t1_v), + .iu_rv_iu6_t0_i0_t1_t(iu_rv_iu6_t0_i0_t1_t), + .iu_rv_iu6_t0_i0_t1_a(iu_rv_iu6_t0_i0_t1_a), + .iu_rv_iu6_t0_i0_t1_p(iu_rv_iu6_t0_i0_t1_p), + .iu_rv_iu6_t0_i0_t2_v(iu_rv_iu6_t0_i0_t2_v), + .iu_rv_iu6_t0_i0_t2_a(iu_rv_iu6_t0_i0_t2_a), + .iu_rv_iu6_t0_i0_t2_p(iu_rv_iu6_t0_i0_t2_p), + .iu_rv_iu6_t0_i0_t2_t(iu_rv_iu6_t0_i0_t2_t), + .iu_rv_iu6_t0_i0_t3_v(iu_rv_iu6_t0_i0_t3_v), + .iu_rv_iu6_t0_i0_t3_a(iu_rv_iu6_t0_i0_t3_a), + .iu_rv_iu6_t0_i0_t3_p(iu_rv_iu6_t0_i0_t3_p), + .iu_rv_iu6_t0_i0_t3_t(iu_rv_iu6_t0_i0_t3_t), + .iu_rv_iu6_t0_i0_s1_v(iu_rv_iu6_t0_i0_s1_v), + .iu_rv_iu6_t0_i0_s1_a(iu_rv_iu6_t0_i0_s1_a), + .iu_rv_iu6_t0_i0_s1_p(iu_rv_iu6_t0_i0_s1_p), + .iu_rv_iu6_t0_i0_s1_itag(iu_rv_iu6_t0_i0_s1_itag), + .iu_rv_iu6_t0_i0_s1_t(iu_rv_iu6_t0_i0_s1_t), + .iu_rv_iu6_t0_i0_s2_v(iu_rv_iu6_t0_i0_s2_v), + .iu_rv_iu6_t0_i0_s2_a(iu_rv_iu6_t0_i0_s2_a), + .iu_rv_iu6_t0_i0_s2_p(iu_rv_iu6_t0_i0_s2_p), + .iu_rv_iu6_t0_i0_s2_itag(iu_rv_iu6_t0_i0_s2_itag), + .iu_rv_iu6_t0_i0_s2_t(iu_rv_iu6_t0_i0_s2_t), + .iu_rv_iu6_t0_i0_s3_v(iu_rv_iu6_t0_i0_s3_v), + .iu_rv_iu6_t0_i0_s3_a(iu_rv_iu6_t0_i0_s3_a), + .iu_rv_iu6_t0_i0_s3_p(iu_rv_iu6_t0_i0_s3_p), + .iu_rv_iu6_t0_i0_s3_itag(iu_rv_iu6_t0_i0_s3_itag), + .iu_rv_iu6_t0_i0_s3_t(iu_rv_iu6_t0_i0_s3_t), + + .iu_rv_iu6_t0_i1_vld(iu_rv_iu6_t0_i1_vld), + .iu_rv_iu6_t0_i1_act(iu_rv_iu6_t0_i1_act), + .iu_rv_iu6_t0_i1_itag(iu_rv_iu6_t0_i1_itag), + .iu_rv_iu6_t0_i1_ucode(iu_rv_iu6_t0_i1_ucode), + .iu_rv_iu6_t0_i1_ucode_cnt(iu_rv_iu6_t0_i1_ucode_cnt), + .iu_rv_iu6_t0_i1_fuse_nop(iu_rv_iu6_t0_i1_fuse_nop), + .iu_rv_iu6_t0_i1_rte_lq(iu_rv_iu6_t0_i1_rte_lq), + .iu_rv_iu6_t0_i1_rte_sq(iu_rv_iu6_t0_i1_rte_sq), + .iu_rv_iu6_t0_i1_rte_fx0(iu_rv_iu6_t0_i1_rte_fx0), + .iu_rv_iu6_t0_i1_rte_fx1(iu_rv_iu6_t0_i1_rte_fx1), + .iu_rv_iu6_t0_i1_rte_axu0(iu_rv_iu6_t0_i1_rte_axu0), + .iu_rv_iu6_t0_i1_rte_axu1(iu_rv_iu6_t0_i1_rte_axu1), + .iu_rv_iu6_t0_i1_valop(iu_rv_iu6_t0_i1_valop), + .iu_rv_iu6_t0_i1_ord(iu_rv_iu6_t0_i1_ord), + .iu_rv_iu6_t0_i1_cord(iu_rv_iu6_t0_i1_cord), + .iu_rv_iu6_t0_i1_error(iu_rv_iu6_t0_i1_error), + .iu_rv_iu6_t0_i1_btb_entry(iu_rv_iu6_t0_i1_btb_entry), + .iu_rv_iu6_t0_i1_btb_hist(iu_rv_iu6_t0_i1_btb_hist), + .iu_rv_iu6_t0_i1_bta_val(iu_rv_iu6_t0_i1_bta_val), + .iu_rv_iu6_t0_i1_fusion(iu_rv_iu6_t0_i1_fusion), + .iu_rv_iu6_t0_i1_spec(iu_rv_iu6_t0_i1_spec), + .iu_rv_iu6_t0_i1_type_fp(iu_rv_iu6_t0_i1_type_fp), + .iu_rv_iu6_t0_i1_type_ap(iu_rv_iu6_t0_i1_type_ap), + .iu_rv_iu6_t0_i1_type_spv(iu_rv_iu6_t0_i1_type_spv), + .iu_rv_iu6_t0_i1_type_st(iu_rv_iu6_t0_i1_type_st), + .iu_rv_iu6_t0_i1_async_block(iu_rv_iu6_t0_i1_async_block), + .iu_rv_iu6_t0_i1_np1_flush(iu_rv_iu6_t0_i1_np1_flush), + .iu_rv_iu6_t0_i1_isram(iu_rv_iu6_t0_i1_isram), + .iu_rv_iu6_t0_i1_isload(iu_rv_iu6_t0_i1_isload), + .iu_rv_iu6_t0_i1_isstore(iu_rv_iu6_t0_i1_isstore), + .iu_rv_iu6_t0_i1_instr(iu_rv_iu6_t0_i1_instr), + .iu_rv_iu6_t0_i1_ifar(iu_rv_iu6_t0_i1_ifar), + .iu_rv_iu6_t0_i1_bta(iu_rv_iu6_t0_i1_bta), + .iu_rv_iu6_t0_i1_br_pred(iu_rv_iu6_t0_i1_br_pred), + .iu_rv_iu6_t0_i1_bh_update(iu_rv_iu6_t0_i1_bh_update), + .iu_rv_iu6_t0_i1_bh0_hist(iu_rv_iu6_t0_i1_bh0_hist), + .iu_rv_iu6_t0_i1_bh1_hist(iu_rv_iu6_t0_i1_bh1_hist), + .iu_rv_iu6_t0_i1_bh2_hist(iu_rv_iu6_t0_i1_bh2_hist), + .iu_rv_iu6_t0_i1_gshare(iu_rv_iu6_t0_i1_gshare), + .iu_rv_iu6_t0_i1_ls_ptr(iu_rv_iu6_t0_i1_ls_ptr), + .iu_rv_iu6_t0_i1_match(iu_rv_iu6_t0_i1_match), + .iu_rv_iu6_t0_i1_ilat(iu_rv_iu6_t0_i1_ilat), + .iu_rv_iu6_t0_i1_t1_v(iu_rv_iu6_t0_i1_t1_v), + .iu_rv_iu6_t0_i1_t1_t(iu_rv_iu6_t0_i1_t1_t), + .iu_rv_iu6_t0_i1_t1_a(iu_rv_iu6_t0_i1_t1_a), + .iu_rv_iu6_t0_i1_t1_p(iu_rv_iu6_t0_i1_t1_p), + .iu_rv_iu6_t0_i1_t2_v(iu_rv_iu6_t0_i1_t2_v), + .iu_rv_iu6_t0_i1_t2_a(iu_rv_iu6_t0_i1_t2_a), + .iu_rv_iu6_t0_i1_t2_p(iu_rv_iu6_t0_i1_t2_p), + .iu_rv_iu6_t0_i1_t2_t(iu_rv_iu6_t0_i1_t2_t), + .iu_rv_iu6_t0_i1_t3_v(iu_rv_iu6_t0_i1_t3_v), + .iu_rv_iu6_t0_i1_t3_a(iu_rv_iu6_t0_i1_t3_a), + .iu_rv_iu6_t0_i1_t3_p(iu_rv_iu6_t0_i1_t3_p), + .iu_rv_iu6_t0_i1_t3_t(iu_rv_iu6_t0_i1_t3_t), + .iu_rv_iu6_t0_i1_s1_v(iu_rv_iu6_t0_i1_s1_v), + .iu_rv_iu6_t0_i1_s1_a(iu_rv_iu6_t0_i1_s1_a), + .iu_rv_iu6_t0_i1_s1_p(iu_rv_iu6_t0_i1_s1_p), + .iu_rv_iu6_t0_i1_s1_itag(iu_rv_iu6_t0_i1_s1_itag), + .iu_rv_iu6_t0_i1_s1_t(iu_rv_iu6_t0_i1_s1_t), + .iu_rv_iu6_t0_i1_s1_dep_hit(iu_rv_iu6_t0_i1_s1_dep_hit), + .iu_rv_iu6_t0_i1_s2_v(iu_rv_iu6_t0_i1_s2_v), + .iu_rv_iu6_t0_i1_s2_a(iu_rv_iu6_t0_i1_s2_a), + .iu_rv_iu6_t0_i1_s2_p(iu_rv_iu6_t0_i1_s2_p), + .iu_rv_iu6_t0_i1_s2_itag(iu_rv_iu6_t0_i1_s2_itag), + .iu_rv_iu6_t0_i1_s2_t(iu_rv_iu6_t0_i1_s2_t), + .iu_rv_iu6_t0_i1_s2_dep_hit(iu_rv_iu6_t0_i1_s2_dep_hit), + .iu_rv_iu6_t0_i1_s3_v(iu_rv_iu6_t0_i1_s3_v), + .iu_rv_iu6_t0_i1_s3_a(iu_rv_iu6_t0_i1_s3_a), + .iu_rv_iu6_t0_i1_s3_p(iu_rv_iu6_t0_i1_s3_p), + .iu_rv_iu6_t0_i1_s3_itag(iu_rv_iu6_t0_i1_s3_itag), + .iu_rv_iu6_t0_i1_s3_t(iu_rv_iu6_t0_i1_s3_t), + .iu_rv_iu6_t0_i1_s3_dep_hit(iu_rv_iu6_t0_i1_s3_dep_hit), +`ifndef THREADS1 + .iu_rv_iu6_t1_i0_vld(iu_rv_iu6_t1_i0_vld), + .iu_rv_iu6_t1_i0_act(iu_rv_iu6_t1_i0_act), + .iu_rv_iu6_t1_i0_itag(iu_rv_iu6_t1_i0_itag), + .iu_rv_iu6_t1_i0_ucode(iu_rv_iu6_t1_i0_ucode), + .iu_rv_iu6_t1_i0_ucode_cnt(iu_rv_iu6_t1_i0_ucode_cnt), + .iu_rv_iu6_t1_i0_2ucode(iu_rv_iu6_t1_i0_2ucode), + .iu_rv_iu6_t1_i0_fuse_nop(iu_rv_iu6_t1_i0_fuse_nop), + .iu_rv_iu6_t1_i0_rte_lq(iu_rv_iu6_t1_i0_rte_lq), + .iu_rv_iu6_t1_i0_rte_sq(iu_rv_iu6_t1_i0_rte_sq), + .iu_rv_iu6_t1_i0_rte_fx0(iu_rv_iu6_t1_i0_rte_fx0), + .iu_rv_iu6_t1_i0_rte_fx1(iu_rv_iu6_t1_i0_rte_fx1), + .iu_rv_iu6_t1_i0_rte_axu0(iu_rv_iu6_t1_i0_rte_axu0), + .iu_rv_iu6_t1_i0_rte_axu1(iu_rv_iu6_t1_i0_rte_axu1), + .iu_rv_iu6_t1_i0_valop(iu_rv_iu6_t1_i0_valop), + .iu_rv_iu6_t1_i0_ord(iu_rv_iu6_t1_i0_ord), + .iu_rv_iu6_t1_i0_cord(iu_rv_iu6_t1_i0_cord), + .iu_rv_iu6_t1_i0_error(iu_rv_iu6_t1_i0_error), + .iu_rv_iu6_t1_i0_btb_entry(iu_rv_iu6_t1_i0_btb_entry), + .iu_rv_iu6_t1_i0_btb_hist(iu_rv_iu6_t1_i0_btb_hist), + .iu_rv_iu6_t1_i0_bta_val(iu_rv_iu6_t1_i0_bta_val), + .iu_rv_iu6_t1_i0_fusion(iu_rv_iu6_t1_i0_fusion), + .iu_rv_iu6_t1_i0_spec(iu_rv_iu6_t1_i0_spec), + .iu_rv_iu6_t1_i0_type_fp(iu_rv_iu6_t1_i0_type_fp), + .iu_rv_iu6_t1_i0_type_ap(iu_rv_iu6_t1_i0_type_ap), + .iu_rv_iu6_t1_i0_type_spv(iu_rv_iu6_t1_i0_type_spv), + .iu_rv_iu6_t1_i0_type_st(iu_rv_iu6_t1_i0_type_st), + .iu_rv_iu6_t1_i0_async_block(iu_rv_iu6_t1_i0_async_block), + .iu_rv_iu6_t1_i0_np1_flush(iu_rv_iu6_t1_i0_np1_flush), + .iu_rv_iu6_t1_i0_isram(iu_rv_iu6_t1_i0_isram), + .iu_rv_iu6_t1_i0_isload(iu_rv_iu6_t1_i0_isload), + .iu_rv_iu6_t1_i0_isstore(iu_rv_iu6_t1_i0_isstore), + .iu_rv_iu6_t1_i0_instr(iu_rv_iu6_t1_i0_instr), + .iu_rv_iu6_t1_i0_ifar(iu_rv_iu6_t1_i0_ifar), + .iu_rv_iu6_t1_i0_bta(iu_rv_iu6_t1_i0_bta), + .iu_rv_iu6_t1_i0_br_pred(iu_rv_iu6_t1_i0_br_pred), + .iu_rv_iu6_t1_i0_bh_update(iu_rv_iu6_t1_i0_bh_update), + .iu_rv_iu6_t1_i0_bh0_hist(iu_rv_iu6_t1_i0_bh0_hist), + .iu_rv_iu6_t1_i0_bh1_hist(iu_rv_iu6_t1_i0_bh1_hist), + .iu_rv_iu6_t1_i0_bh2_hist(iu_rv_iu6_t1_i0_bh2_hist), + .iu_rv_iu6_t1_i0_gshare(iu_rv_iu6_t1_i0_gshare), + .iu_rv_iu6_t1_i0_ls_ptr(iu_rv_iu6_t1_i0_ls_ptr), + .iu_rv_iu6_t1_i0_match(iu_rv_iu6_t1_i0_match), + .iu_rv_iu6_t1_i0_ilat(iu_rv_iu6_t1_i0_ilat), + .iu_rv_iu6_t1_i0_t1_v(iu_rv_iu6_t1_i0_t1_v), + .iu_rv_iu6_t1_i0_t1_t(iu_rv_iu6_t1_i0_t1_t), + .iu_rv_iu6_t1_i0_t1_a(iu_rv_iu6_t1_i0_t1_a), + .iu_rv_iu6_t1_i0_t1_p(iu_rv_iu6_t1_i0_t1_p), + .iu_rv_iu6_t1_i0_t2_v(iu_rv_iu6_t1_i0_t2_v), + .iu_rv_iu6_t1_i0_t2_a(iu_rv_iu6_t1_i0_t2_a), + .iu_rv_iu6_t1_i0_t2_p(iu_rv_iu6_t1_i0_t2_p), + .iu_rv_iu6_t1_i0_t2_t(iu_rv_iu6_t1_i0_t2_t), + .iu_rv_iu6_t1_i0_t3_v(iu_rv_iu6_t1_i0_t3_v), + .iu_rv_iu6_t1_i0_t3_a(iu_rv_iu6_t1_i0_t3_a), + .iu_rv_iu6_t1_i0_t3_p(iu_rv_iu6_t1_i0_t3_p), + .iu_rv_iu6_t1_i0_t3_t(iu_rv_iu6_t1_i0_t3_t), + .iu_rv_iu6_t1_i0_s1_v(iu_rv_iu6_t1_i0_s1_v), + .iu_rv_iu6_t1_i0_s1_a(iu_rv_iu6_t1_i0_s1_a), + .iu_rv_iu6_t1_i0_s1_p(iu_rv_iu6_t1_i0_s1_p), + .iu_rv_iu6_t1_i0_s1_itag(iu_rv_iu6_t1_i0_s1_itag), + .iu_rv_iu6_t1_i0_s1_t(iu_rv_iu6_t1_i0_s1_t), + .iu_rv_iu6_t1_i0_s2_v(iu_rv_iu6_t1_i0_s2_v), + .iu_rv_iu6_t1_i0_s2_a(iu_rv_iu6_t1_i0_s2_a), + .iu_rv_iu6_t1_i0_s2_p(iu_rv_iu6_t1_i0_s2_p), + .iu_rv_iu6_t1_i0_s2_itag(iu_rv_iu6_t1_i0_s2_itag), + .iu_rv_iu6_t1_i0_s2_t(iu_rv_iu6_t1_i0_s2_t), + .iu_rv_iu6_t1_i0_s3_v(iu_rv_iu6_t1_i0_s3_v), + .iu_rv_iu6_t1_i0_s3_a(iu_rv_iu6_t1_i0_s3_a), + .iu_rv_iu6_t1_i0_s3_p(iu_rv_iu6_t1_i0_s3_p), + .iu_rv_iu6_t1_i0_s3_itag(iu_rv_iu6_t1_i0_s3_itag), + .iu_rv_iu6_t1_i0_s3_t(iu_rv_iu6_t1_i0_s3_t), + + .iu_rv_iu6_t1_i1_vld(iu_rv_iu6_t1_i1_vld), + .iu_rv_iu6_t1_i1_act(iu_rv_iu6_t1_i1_act), + .iu_rv_iu6_t1_i1_itag(iu_rv_iu6_t1_i1_itag), + .iu_rv_iu6_t1_i1_ucode(iu_rv_iu6_t1_i1_ucode), + .iu_rv_iu6_t1_i1_ucode_cnt(iu_rv_iu6_t1_i1_ucode_cnt), + .iu_rv_iu6_t1_i1_fuse_nop(iu_rv_iu6_t1_i1_fuse_nop), + .iu_rv_iu6_t1_i1_rte_lq(iu_rv_iu6_t1_i1_rte_lq), + .iu_rv_iu6_t1_i1_rte_sq(iu_rv_iu6_t1_i1_rte_sq), + .iu_rv_iu6_t1_i1_rte_fx0(iu_rv_iu6_t1_i1_rte_fx0), + .iu_rv_iu6_t1_i1_rte_fx1(iu_rv_iu6_t1_i1_rte_fx1), + .iu_rv_iu6_t1_i1_rte_axu0(iu_rv_iu6_t1_i1_rte_axu0), + .iu_rv_iu6_t1_i1_rte_axu1(iu_rv_iu6_t1_i1_rte_axu1), + .iu_rv_iu6_t1_i1_valop(iu_rv_iu6_t1_i1_valop), + .iu_rv_iu6_t1_i1_ord(iu_rv_iu6_t1_i1_ord), + .iu_rv_iu6_t1_i1_cord(iu_rv_iu6_t1_i1_cord), + .iu_rv_iu6_t1_i1_error(iu_rv_iu6_t1_i1_error), + .iu_rv_iu6_t1_i1_btb_entry(iu_rv_iu6_t1_i1_btb_entry), + .iu_rv_iu6_t1_i1_btb_hist(iu_rv_iu6_t1_i1_btb_hist), + .iu_rv_iu6_t1_i1_bta_val(iu_rv_iu6_t1_i1_bta_val), + .iu_rv_iu6_t1_i1_fusion(iu_rv_iu6_t1_i1_fusion), + .iu_rv_iu6_t1_i1_spec(iu_rv_iu6_t1_i1_spec), + .iu_rv_iu6_t1_i1_type_fp(iu_rv_iu6_t1_i1_type_fp), + .iu_rv_iu6_t1_i1_type_ap(iu_rv_iu6_t1_i1_type_ap), + .iu_rv_iu6_t1_i1_type_spv(iu_rv_iu6_t1_i1_type_spv), + .iu_rv_iu6_t1_i1_type_st(iu_rv_iu6_t1_i1_type_st), + .iu_rv_iu6_t1_i1_async_block(iu_rv_iu6_t1_i1_async_block), + .iu_rv_iu6_t1_i1_np1_flush(iu_rv_iu6_t1_i1_np1_flush), + .iu_rv_iu6_t1_i1_isram(iu_rv_iu6_t1_i1_isram), + .iu_rv_iu6_t1_i1_isload(iu_rv_iu6_t1_i1_isload), + .iu_rv_iu6_t1_i1_isstore(iu_rv_iu6_t1_i1_isstore), + .iu_rv_iu6_t1_i1_instr(iu_rv_iu6_t1_i1_instr), + .iu_rv_iu6_t1_i1_ifar(iu_rv_iu6_t1_i1_ifar), + .iu_rv_iu6_t1_i1_bta(iu_rv_iu6_t1_i1_bta), + .iu_rv_iu6_t1_i1_br_pred(iu_rv_iu6_t1_i1_br_pred), + .iu_rv_iu6_t1_i1_bh_update(iu_rv_iu6_t1_i1_bh_update), + .iu_rv_iu6_t1_i1_bh0_hist(iu_rv_iu6_t1_i1_bh0_hist), + .iu_rv_iu6_t1_i1_bh1_hist(iu_rv_iu6_t1_i1_bh1_hist), + .iu_rv_iu6_t1_i1_bh2_hist(iu_rv_iu6_t1_i1_bh2_hist), + .iu_rv_iu6_t1_i1_gshare(iu_rv_iu6_t1_i1_gshare), + .iu_rv_iu6_t1_i1_ls_ptr(iu_rv_iu6_t1_i1_ls_ptr), + .iu_rv_iu6_t1_i1_match(iu_rv_iu6_t1_i1_match), + .iu_rv_iu6_t1_i1_ilat(iu_rv_iu6_t1_i1_ilat), + .iu_rv_iu6_t1_i1_t1_v(iu_rv_iu6_t1_i1_t1_v), + .iu_rv_iu6_t1_i1_t1_t(iu_rv_iu6_t1_i1_t1_t), + .iu_rv_iu6_t1_i1_t1_a(iu_rv_iu6_t1_i1_t1_a), + .iu_rv_iu6_t1_i1_t1_p(iu_rv_iu6_t1_i1_t1_p), + .iu_rv_iu6_t1_i1_t2_v(iu_rv_iu6_t1_i1_t2_v), + .iu_rv_iu6_t1_i1_t2_a(iu_rv_iu6_t1_i1_t2_a), + .iu_rv_iu6_t1_i1_t2_p(iu_rv_iu6_t1_i1_t2_p), + .iu_rv_iu6_t1_i1_t2_t(iu_rv_iu6_t1_i1_t2_t), + .iu_rv_iu6_t1_i1_t3_v(iu_rv_iu6_t1_i1_t3_v), + .iu_rv_iu6_t1_i1_t3_a(iu_rv_iu6_t1_i1_t3_a), + .iu_rv_iu6_t1_i1_t3_p(iu_rv_iu6_t1_i1_t3_p), + .iu_rv_iu6_t1_i1_t3_t(iu_rv_iu6_t1_i1_t3_t), + .iu_rv_iu6_t1_i1_s1_v(iu_rv_iu6_t1_i1_s1_v), + .iu_rv_iu6_t1_i1_s1_a(iu_rv_iu6_t1_i1_s1_a), + .iu_rv_iu6_t1_i1_s1_p(iu_rv_iu6_t1_i1_s1_p), + .iu_rv_iu6_t1_i1_s1_itag(iu_rv_iu6_t1_i1_s1_itag), + .iu_rv_iu6_t1_i1_s1_t(iu_rv_iu6_t1_i1_s1_t), + .iu_rv_iu6_t1_i1_s1_dep_hit(iu_rv_iu6_t1_i1_s1_dep_hit), + .iu_rv_iu6_t1_i1_s2_v(iu_rv_iu6_t1_i1_s2_v), + .iu_rv_iu6_t1_i1_s2_a(iu_rv_iu6_t1_i1_s2_a), + .iu_rv_iu6_t1_i1_s2_p(iu_rv_iu6_t1_i1_s2_p), + .iu_rv_iu6_t1_i1_s2_itag(iu_rv_iu6_t1_i1_s2_itag), + .iu_rv_iu6_t1_i1_s2_t(iu_rv_iu6_t1_i1_s2_t), + .iu_rv_iu6_t1_i1_s2_dep_hit(iu_rv_iu6_t1_i1_s2_dep_hit), + .iu_rv_iu6_t1_i1_s3_v(iu_rv_iu6_t1_i1_s3_v), + .iu_rv_iu6_t1_i1_s3_a(iu_rv_iu6_t1_i1_s3_a), + .iu_rv_iu6_t1_i1_s3_p(iu_rv_iu6_t1_i1_s3_p), + .iu_rv_iu6_t1_i1_s3_itag(iu_rv_iu6_t1_i1_s3_itag), + .iu_rv_iu6_t1_i1_s3_t(iu_rv_iu6_t1_i1_s3_t), + .iu_rv_iu6_t1_i1_s3_dep_hit(iu_rv_iu6_t1_i1_s3_dep_hit), +`endif + + // Input to dispatch to block due to ivax + .cp_dis_ivax(cp_dis_ivax), + + //----------------------------- + // Stall from MMU + //----------------------------- + + .mm_iu_flush_req(mm_iu_flush_req), + .dp_cp_hold_req(dp_cp_hold_req), + .mm_iu_hold_done(mm_iu_hold_done), + .mm_iu_bus_snoop_hold_req(mm_iu_bus_snoop_hold_req), + .dp_cp_bus_snoop_hold_req(dp_cp_bus_snoop_hold_req), + .mm_iu_bus_snoop_hold_done(mm_iu_bus_snoop_hold_done), + .mm_iu_tlbi_complete(mm_iu_tlbi_complete) + ); + +endmodule diff --git a/dev/verilog/work/iuq_spr.v b/dev/verilog/work/iuq_spr.v new file mode 100755 index 0000000..b835e94 --- /dev/null +++ b/dev/verilog/work/iuq_spr.v @@ -0,0 +1,1745 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// ********************************************************************* +// +// This is the ENTITY for iuq_spr +// +// +// ********************************************************************* + +`include "tri_a2o.vh" + +module iuq_spr( + // inputs for power and gnd + inout vdd, + inout gnd, + + // inputs from xx + input iu_slowspr_val_in, + input iu_slowspr_rw_in, + input [0:1] iu_slowspr_etid_in, + input [0:9] iu_slowspr_addr_in, + input [64-`GPR_WIDTH:63] iu_slowspr_data_in, + input iu_slowspr_done_in, + + // outputs to xx + output iu_slowspr_val_out, + output iu_slowspr_rw_out, + output [0:1] iu_slowspr_etid_out, + output [0:9] iu_slowspr_addr_out, + output [64-`GPR_WIDTH:63] iu_slowspr_data_out, + output iu_slowspr_done_out, + + // Need to flush any read instructions coming around the ring + input [0:`THREADS-1] cp_flush, + + // Signals for branch prediction enable + output [0:3] spr_ic_bp_config, + output [0:5] spr_bp_config, + + output [0:1] spr_bp_size, + + // decoder match/mask + output [0:31] spr_dec_mask, + output [0:31] spr_dec_match, + output [0:`THREADS-1] spr_single_issue, + //axu config + output [0:7] iu_au_t0_config_iucr, +`ifndef THREADS1 + output [0:7] iu_au_t1_config_iucr, +`endif + + // XU issue priority + output [0:`THREADS-1] spr_high_pri_mask, + output [0:`THREADS-1] spr_med_pri_mask, + output [0:5] spr_t0_low_pri_count, +`ifndef THREADS1 + output [0:5] spr_t1_low_pri_count, +`endif + input [0:`THREADS-1] xu_iu_raise_iss_pri, + + input [0:`THREADS-1] xu_iu_pri_val, + input [0:2] xu_iu_pri, + + input [0:`THREADS-1] spr_msr_gs, + input [0:`THREADS-1] spr_msr_pr, + + output [64-`GPR_WIDTH:51] spr_ivpr, + output [64-`GPR_WIDTH:51] spr_givpr, + + output [62-`EFF_IFAR_ARCH:61] spr_iac1, + output [62-`EFF_IFAR_ARCH:61] spr_iac2, + output [62-`EFF_IFAR_ARCH:61] spr_iac3, + output [62-`EFF_IFAR_ARCH:61] spr_iac4, + + output [0:`THREADS-1] spr_cpcr_we, + output [0:4] spr_t0_cpcr2_fx0_cnt, + output [0:4] spr_t0_cpcr2_fx1_cnt, + output [0:4] spr_t0_cpcr2_lq_cnt, + output [0:4] spr_t0_cpcr2_sq_cnt, + output [0:4] spr_t0_cpcr3_fu0_cnt, + output [0:4] spr_t0_cpcr3_fu1_cnt, + output [0:6] spr_t0_cpcr3_cp_cnt, + output [0:4] spr_t0_cpcr4_fx0_cnt, + output [0:4] spr_t0_cpcr4_fx1_cnt, + output [0:4] spr_t0_cpcr4_lq_cnt, + output [0:4] spr_t0_cpcr4_sq_cnt, + output [0:4] spr_t0_cpcr5_fu0_cnt, + output [0:4] spr_t0_cpcr5_fu1_cnt, + output [0:6] spr_t0_cpcr5_cp_cnt, +`ifndef THREADS1 + output [0:4] spr_t1_cpcr2_fx0_cnt, + output [0:4] spr_t1_cpcr2_fx1_cnt, + output [0:4] spr_t1_cpcr2_lq_cnt, + output [0:4] spr_t1_cpcr2_sq_cnt, + output [0:4] spr_t1_cpcr3_fu0_cnt, + output [0:4] spr_t1_cpcr3_fu1_cnt, + output [0:6] spr_t1_cpcr3_cp_cnt, + output [0:4] spr_t1_cpcr4_fx0_cnt, + output [0:4] spr_t1_cpcr4_fx1_cnt, + output [0:4] spr_t1_cpcr4_lq_cnt, + output [0:4] spr_t1_cpcr4_sq_cnt, + output [0:4] spr_t1_cpcr5_fu0_cnt, + output [0:4] spr_t1_cpcr5_fu1_cnt, + output [0:6] spr_t1_cpcr5_cp_cnt, +`endif + output [0:4] spr_cpcr0_fx0_cnt, + output [0:4] spr_cpcr0_fx1_cnt, + output [0:4] spr_cpcr0_lq_cnt, + output [0:4] spr_cpcr0_sq_cnt, + output [0:4] spr_cpcr1_fu0_cnt, + output [0:4] spr_cpcr1_fu1_cnt, + + input [0:`THREADS-1] iu_spr_eheir_update, + input [0:31] iu_spr_t0_eheir, +`ifndef THREADS1 + input [0:31] iu_spr_t1_eheir, +`endif + + output spr_ic_idir_read, + output [0:1] spr_ic_idir_way, + output [51:57] spr_ic_idir_row, + input ic_spr_idir_done, + input [0:2] ic_spr_idir_lru, + input [0:3] ic_spr_idir_parity, + input ic_spr_idir_endian, + input ic_spr_idir_valid, + input [0:28] ic_spr_idir_tag, + + output spr_ic_icbi_ack_en, + output spr_ic_cls, + output spr_ic_clockgate_dis, + output spr_ic_prefetch_dis, + + output [0:47] spr_perf_event_mux_ctrls, + output [0:31] spr_cp_perf_event_mux_ctrls, + + //pervasive + (* pin_data="PIN_FUNCTION=/G_CLK/" *) + input [0:`NCLK_WIDTH-1] nclk, + input pc_iu_sg_2, + input pc_iu_func_sl_thold_2, + input clkoff_b, + input act_dis, + input tc_ac_ccflush_dc, + input d_mode, + input delay_lclkr, + input mpw1_b, + input mpw2_b, + input scan_in, + output scan_out); + + //scan chain + parameter slowspr_val_offset = 0; + parameter slowspr_rw_offset = slowspr_val_offset + 1; + parameter slowspr_etid_offset = slowspr_rw_offset + 1; + parameter slowspr_addr_offset = slowspr_etid_offset + 2; + parameter slowspr_data_offset = slowspr_addr_offset + 10; + parameter slowspr_done_offset = slowspr_data_offset + `GPR_WIDTH; + parameter ivpr_offset = slowspr_done_offset + 1; + parameter givpr_offset = ivpr_offset + 52 - (64 - `GPR_WIDTH); + parameter immr0_offset = givpr_offset + 52 - (64 - `GPR_WIDTH); + parameter imr0_offset = immr0_offset + 32; + parameter iucr0_offset = imr0_offset + 32; + parameter eheir_offset = iucr0_offset + 16; + parameter iucr1_offset = eheir_offset + 32 * `THREADS; + parameter iucr2_offset = iucr1_offset + 14 * `THREADS; + parameter ppr32_offset = iucr2_offset + 8 * `THREADS; + parameter iac1_offset = ppr32_offset + 3 * `THREADS; + parameter iac2_offset = iac1_offset + `EFF_IFAR_ARCH; + parameter iac3_offset = iac2_offset + `EFF_IFAR_ARCH; + parameter iac4_offset = iac3_offset + `EFF_IFAR_ARCH; + parameter cpcr_we_offset = iac4_offset + `EFF_IFAR_ARCH; + parameter cpcr0_offset = cpcr_we_offset + `THREADS; + parameter cpcr1_offset = cpcr0_offset + 32; + parameter cpcr2_offset = cpcr1_offset + 32; + parameter cpcr3_offset = cpcr2_offset + 32 * `THREADS; + parameter cpcr4_offset = cpcr3_offset + 32 * `THREADS; + parameter cpcr5_offset = cpcr4_offset + 32 * `THREADS; + parameter iulfsr_offset = cpcr5_offset + 32 * `THREADS; + parameter iudbg0_offset = iulfsr_offset + 32; + parameter iudbg1_offset = iudbg0_offset + 9; + parameter iudbg2_offset = iudbg1_offset + 11; + parameter iudbg0_exec_offset = iudbg2_offset + 29; + parameter iudbg0_done_offset = iudbg0_exec_offset + 1; + parameter iullcr_offset = iudbg0_done_offset + 1; + parameter cp_flush_offset = iullcr_offset + 18; + parameter spr_msr_gs_offset = cp_flush_offset + `THREADS; + parameter spr_msr_pr_offset = spr_msr_gs_offset + `THREADS; + parameter xu_iu_pri_offset = spr_msr_pr_offset + `THREADS; + parameter xu_iu_pri_val_offset = xu_iu_pri_offset + 3; + parameter iesr3_offset = xu_iu_pri_val_offset + `THREADS; + parameter iesr1_offset = iesr3_offset + 32; + parameter iesr2_offset = iesr1_offset + 24; + parameter raise_iss_pri_offset = iesr2_offset + 24; + parameter scan_right = raise_iss_pri_offset + `THREADS - 1; + + parameter [32:63] IMMR0_MASK = 32'b11111111111111111111111111111111; + parameter [32:63] IMR0_MASK = 32'b11111111111111111111111111111111; + parameter [32:63] IULFSR_MASK = 32'b11111111111111111111111111111111; + parameter [32:63] IUDBG0_MASK = 32'b00000000000000000111111111000011; + parameter [32:63] IUDBG1_MASK = 32'b00000000000000000000011111111001; + parameter [32:63] IUDBG2_MASK = 32'b00011111111111111111111111111111; + parameter [32:63] IULLCR_MASK = 32'b00000000000000111100001111110001; + parameter [32:63] IUCR0_MASK = 32'b00000000000000001111001111111111; + parameter [32:63] IUCR1_MASK = 32'b00000000000000000011000000111111; + parameter [32:63] IUCR2_MASK = 32'b11111111000000000000000000000000; + parameter [32:63] PPR32_MASK = 32'b00000000000111000000000000000000; + parameter [32:63] EVENTMUX_128_MASK = 32'b11111111111111111111111100000000; + + //-------------------------- + // signals + //-------------------------- + wire slowspr_val_act; + + wire slowspr_val_d; + wire slowspr_val_l2; + wire slowspr_rw_d; + wire slowspr_rw_l2; + wire [0:1] slowspr_etid_d; + wire [0:1] slowspr_etid_l2; + wire [0:9] slowspr_addr_d; + wire [0:9] slowspr_addr_l2; + wire [64-`GPR_WIDTH:63] slowspr_data_d; + wire [64-`GPR_WIDTH:63] slowspr_data_l2; + wire slowspr_done_d; + wire slowspr_done_l2; + + wire iu_slowspr_done; + wire [64-`GPR_WIDTH:63] iu_slowspr_data; + + wire ivpr_sel; + wire ivpr_wren; + wire ivpr_rden; + wire [64-`GPR_WIDTH:51] ivpr_d; + wire [64-`GPR_WIDTH:51] ivpr_l2; + + wire givpr_sel; + wire givpr_wren; + wire givpr_rden; + wire [64-`GPR_WIDTH:51] givpr_d; + wire [64-`GPR_WIDTH:51] givpr_l2; + + wire immr0_sel; + wire immr0_wren; + wire immr0_rden; + wire [32:63] immr0_d; + wire [32:63] immr0_l2; + + wire imr0_sel; + wire imr0_wren; + wire imr0_rden; + wire [32:63] imr0_d; + wire [32:63] imr0_l2; + + wire iulfsr_sel; + wire iulfsr_wren; + wire iulfsr_rden; + wire [32:63] iulfsr_d; + wire [32:63] iulfsr_l2; + wire [1:28] iulfsr; + wire iulfsr_act; + + wire iudbg0_sel; + wire iudbg0_wren; + wire iudbg0_rden; + wire [49:57] iudbg0_d; + wire [49:57] iudbg0_l2; + wire [32:63] iudbg0; + + wire iudbg0_exec_wren; + wire iudbg0_exec_d; + wire iudbg0_exec_l2; + wire iudbg0_done_wren; + wire iudbg0_done_d; + wire iudbg0_done_l2; + + wire iudbg1_sel; + wire iudbg1_wren; + wire iudbg1_rden; + wire [53:63] iudbg1_d; + wire [53:63] iudbg1_l2; + wire [32:63] iudbg1; + + wire iudbg2_sel; + wire iudbg2_wren; + wire iudbg2_rden; + wire [35:63] iudbg2_d; + wire [35:63] iudbg2_l2; + wire [32:63] iudbg2; + + wire iullcr_sel; + wire iullcr_wren; + wire iullcr_rden; + wire [46:63] iullcr_d; + wire [46:63] iullcr_l2; + wire [32:63] iullcr; + + wire iucr0_sel; + wire iucr0_wren; + wire iucr0_rden; + wire [48:63] iucr0_d; + wire [48:63] iucr0_l2; + wire [32:63] iucr0; + + wire [0:`THREADS-1] eheir_sel; + wire [0:`THREADS-1] eheir_wren; + wire [0:`THREADS-1] eheir_rden; + wire [32:63] eheir_d[0:`THREADS-1]; + wire [32:63] eheir_l2[0:`THREADS-1]; + wire [32:63] eheir[0:`THREADS-1]; + + wire [0:`THREADS-1] iucr1_sel; + wire [0:`THREADS-1] iucr1_wren; + wire [0:`THREADS-1] iucr1_rden; + wire [50:63] iucr1_d[0:`THREADS-1]; + wire [50:63] iucr1_l2[0:`THREADS-1]; + wire [32:63] iucr1[0:`THREADS-1]; + + wire [0:`THREADS-1] iucr2_sel; + wire [0:`THREADS-1] iucr2_wren; + wire [0:`THREADS-1] iucr2_rden; + wire [0:7] iucr2_d[0:`THREADS-1]; + wire [0:7] iucr2_l2[0:`THREADS-1]; + wire [32:63] iucr2[0:`THREADS-1]; + + wire [0:`THREADS-1] ppr32_sel; + wire [0:`THREADS-1] ppr32_wren; + wire [0:`THREADS-1] ppr32_rden; + wire [43:45] ppr32_d[0:`THREADS-1]; + wire [43:45] ppr32_l2[0:`THREADS-1]; + wire [32:63] ppr32[0:`THREADS-1]; + + wire iac1_sel; + wire iac1_wren; + wire iac1_rden; + wire [62-`EFF_IFAR_ARCH:61] iac1_d; + wire [62-`EFF_IFAR_ARCH:61] iac1_l2; + wire [0:63] iac1; + + wire iac2_sel; + wire iac2_wren; + wire iac2_rden; + wire [62-`EFF_IFAR_ARCH:61] iac2_d; + wire [62-`EFF_IFAR_ARCH:61] iac2_l2; + wire [0:63] iac2; + + wire iac3_sel; + wire iac3_wren; + wire iac3_rden; + wire [62-`EFF_IFAR_ARCH:61] iac3_d; + wire [62-`EFF_IFAR_ARCH:61] iac3_l2; + wire [0:63] iac3; + + wire iac4_sel; + wire iac4_wren; + wire iac4_rden; + wire [62-`EFF_IFAR_ARCH:61] iac4_d; + wire [62-`EFF_IFAR_ARCH:61] iac4_l2; + wire [0:63] iac4; + + wire [0:`THREADS-1] spr_cpcr_we_d; + wire [0:`THREADS-1] spr_cpcr_we_l2; + + wire cpcr0_sel; + wire cpcr0_wren; + wire cpcr0_rden; + wire [32:63] cpcr0_d; + wire [32:63] cpcr0_l2; + wire [32:63] cpcr0; + + wire cpcr1_sel; + wire cpcr1_wren; + wire cpcr1_rden; + wire [32:63] cpcr1_d; + wire [32:63] cpcr1_l2; + wire [32:63] cpcr1; + + wire [0:`THREADS-1] cpcr2_sel; + wire [0:`THREADS-1] cpcr2_wren; + wire [0:`THREADS-1] cpcr2_rden; + wire [32:63] cpcr2_d[0:`THREADS-1]; + wire [32:63] cpcr2_l2[0:`THREADS-1]; + wire [32:63] cpcr2[0:`THREADS-1]; + + wire [0:`THREADS-1] cpcr3_sel; + wire [0:`THREADS-1] cpcr3_wren; + wire [0:`THREADS-1] cpcr3_rden; + wire [32:63] cpcr3_d[0:`THREADS-1]; + wire [32:63] cpcr3_l2[0:`THREADS-1]; + wire [32:63] cpcr3[0:`THREADS-1]; + + wire [0:`THREADS-1] cpcr4_sel; + wire [0:`THREADS-1] cpcr4_wren; + wire [0:`THREADS-1] cpcr4_rden; + wire [32:63] cpcr4_d[0:`THREADS-1]; + wire [32:63] cpcr4_l2[0:`THREADS-1]; + wire [32:63] cpcr4[0:`THREADS-1]; + + wire [0:`THREADS-1] cpcr5_sel; + wire [0:`THREADS-1] cpcr5_wren; + wire [0:`THREADS-1] cpcr5_rden; + wire [32:63] cpcr5_d[0:`THREADS-1]; + wire [32:63] cpcr5_l2[0:`THREADS-1]; + wire [32:63] cpcr5[0:`THREADS-1]; + + wire [0:`THREADS-1] hi_pri; + wire [0:`THREADS-1] lo_pri; + + wire [0:`THREADS-1] priv_mode; + wire [0:`THREADS-1] hypv_mode; + + wire [0:`THREADS-1] cp_flush_l2; + + wire [0:`THREADS-1] spr_msr_gs_l2; + wire [0:`THREADS-1] spr_msr_pr_l2; + + wire [0:`THREADS-1] xu_iu_pri_val_l2; + wire [0:2] xu_iu_pri_l2; + + wire iesr3_sel; + wire iesr3_wren; + wire iesr3_rden; + wire [32:63] iesr3_d; + wire [32:63] iesr3_l2; + + wire iesr1_sel; + wire iesr1_wren; + wire iesr1_rden; + wire [32:55] iesr1_d; + wire [32:55] iesr1_l2; + + wire iesr2_sel; + wire iesr2_wren; + wire iesr2_rden; + wire [32:55] iesr2_d; + wire [32:55] iesr2_l2; + + wire [0:`THREADS-1] xu_iu_raise_iss_pri_l2; + + // pervasive signals + wire tiup; + + wire pc_iu_func_sl_thold_1; + wire pc_iu_func_sl_thold_0; + wire pc_iu_func_sl_thold_0_b; + wire pc_iu_sg_1; + wire pc_iu_sg_0; + wire force_t; + + wire [0:scan_right] siv; + wire [0:scan_right] sov; + + wire [0:3] slowspr_tid; + + assign tiup = 1'b1; + //assign tidn = 1'b0; + + //----------------------------------------------- + // latches + //----------------------------------------------- + tri_rlmlatch_p #(.INIT(0)) slowspr_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(slowspr_val_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[slowspr_val_offset]), + .scout(sov[slowspr_val_offset]), + .din(slowspr_val_d), + .dout(slowspr_val_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) slowspr_rw_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(slowspr_val_d), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[slowspr_rw_offset]), + .scout(sov[slowspr_rw_offset]), + .din(slowspr_rw_d), + .dout(slowspr_rw_l2) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) slowspr_etid_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(slowspr_val_d), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[slowspr_etid_offset:slowspr_etid_offset + 2 - 1]), + .scout(sov[slowspr_etid_offset:slowspr_etid_offset + 2 - 1]), + .din(slowspr_etid_d), + .dout(slowspr_etid_l2) + ); + + tri_rlmreg_p #(.WIDTH(10), .INIT(0)) slowspr_addr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(slowspr_val_d), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[slowspr_addr_offset:slowspr_addr_offset + 10 - 1]), + .scout(sov[slowspr_addr_offset:slowspr_addr_offset + 10 - 1]), + .din(slowspr_addr_d), + .dout(slowspr_addr_l2) + ); + + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .INIT(0)) slowspr_data_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(slowspr_val_d), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[slowspr_data_offset:slowspr_data_offset + `GPR_WIDTH - 1]), + .scout(sov[slowspr_data_offset:slowspr_data_offset + `GPR_WIDTH - 1]), + .din(slowspr_data_d), + .dout(slowspr_data_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) slowspr_done_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(slowspr_val_d), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[slowspr_done_offset]), + .scout(sov[slowspr_done_offset]), + .din(slowspr_done_d), + .dout(slowspr_done_l2) + ); + + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH-12), .INIT(0)) ivpr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ivpr_wren), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[ivpr_offset:ivpr_offset + (`GPR_WIDTH-12) - 1]), + .scout(sov[ivpr_offset:ivpr_offset + (`GPR_WIDTH-12) - 1]), + .din(ivpr_d), + .dout(ivpr_l2) + ); + + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH-12), .INIT(0)) givpr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(givpr_wren), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[givpr_offset:givpr_offset + (`GPR_WIDTH-12) - 1]), + .scout(sov[givpr_offset:givpr_offset + (`GPR_WIDTH-12) - 1]), + .din(givpr_d), + .dout(givpr_l2) + ); + + tri_rlmreg_p #(.WIDTH(16), .INIT(65535)) immr0a_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(immr0_wren), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[immr0_offset:immr0_offset + 16 - 1]), + .scout(sov[immr0_offset:immr0_offset + 16 - 1]), + .din(immr0_d[32:47]), + .dout(immr0_l2[32:47]) + ); + + tri_rlmreg_p #(.WIDTH(16), .INIT(65535)) immr0b_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(immr0_wren), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[immr0_offset + 16:immr0_offset + 32 - 1]), + .scout(sov[immr0_offset + 16:immr0_offset + 32 - 1]), + .din(immr0_d[48:63]), + .dout(immr0_l2[48:63]) + ); + + tri_rlmreg_p #(.WIDTH(32), .INIT(0)) imr0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(imr0_wren), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[imr0_offset:imr0_offset + 32 - 1]), + .scout(sov[imr0_offset:imr0_offset + 32 - 1]), + .din(imr0_d), + .dout(imr0_l2) + ); + + //init 0x000000F9 + tri_rlmreg_p #(.WIDTH(16), .INIT(`INIT_IUCR0)) iucr0_reg( + // generic map (width => iucr0_l2'length, init => 249, `EXPAND_TYPE => `EXPAND_TYPE) + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iucr0_wren), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iucr0_offset:iucr0_offset + 16 - 1]), + .scout(sov[iucr0_offset:iucr0_offset + 16 - 1]), + .din(iucr0_d), + .dout(iucr0_l2) + ); + + generate + begin : xhdl1 + genvar i; + for (i = 0; i <= `THREADS - 1; i = i + 1) + begin : thread_regs + + //init 0x00001000 + tri_rlmreg_p #(.WIDTH(32), .INIT(0)) eheir_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(eheir_wren[i]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[eheir_offset + i * 32:eheir_offset + (i + 1) * 32 - 1]), + .scout(sov[eheir_offset + i * 32:eheir_offset + (i + 1) * 32 - 1]), + .din(eheir_d[i]), + .dout(eheir_l2[i]) + ); + + //init 0x00001000 + tri_rlmreg_p #(.WIDTH(14), .INIT(4096)) iucr1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iucr1_wren[i]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iucr1_offset + i * 14:iucr1_offset + (i + 1) * 14 - 1]), + .scout(sov[iucr1_offset + i * 14:iucr1_offset + (i + 1) * 14 - 1]), + .din(iucr1_d[i]), + .dout(iucr1_l2[i]) + ); + + //init 0x00000000 + tri_rlmreg_p #(.WIDTH(8), .INIT(0)) iucr2_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iucr2_wren[i]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iucr2_offset + i * 8:iucr2_offset + (i + 1) * 8 - 1]), + .scout(sov[iucr2_offset + i * 8:iucr2_offset + (i + 1) * 8 - 1]), + .din(iucr2_d[i]), + .dout(iucr2_l2[i]) + ); + + //init 0x000c0000 + tri_rlmreg_p #(.WIDTH(3), .INIT(3)) ppr32_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ppr32_wren[i]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[ppr32_offset + i * 3:ppr32_offset + (i + 1) * 3 - 1]), + .scout(sov[ppr32_offset + i * 3:ppr32_offset + (i + 1) * 3 - 1]), + .din(ppr32_d[i]), + .dout(ppr32_l2[i]) + ); + + // hex 0A0A0E0A = 168431114 + tri_rlmreg_p #(.WIDTH(32), .INIT(168431114)) cpcr2_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cpcr2_wren[i]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[cpcr2_offset + i * 32:cpcr2_offset + (i + 1) * 32 - 1]), + .scout(sov[cpcr2_offset + i * 32:cpcr2_offset + (i + 1) * 32 - 1]), + .din(cpcr2_d[i]), + .dout(cpcr2_l2[i]) + ); + + // hex 000A0020 = 655392 + tri_rlmreg_p #(.WIDTH(32), .INIT(655392)) cpcr3_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cpcr3_wren[i]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[cpcr3_offset + i * 32:cpcr3_offset + (i + 1) * 32 - 1]), + .scout(sov[cpcr3_offset + i * 32:cpcr3_offset + (i + 1) * 32 - 1]), + .din(cpcr3_d[i]), + .dout(cpcr3_l2[i]) + ); + + // hex 06060806 = 101058566 + tri_rlmreg_p #(.WIDTH(32), .INIT(101058566)) cpcr4_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cpcr4_wren[i]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[cpcr4_offset + i * 32:cpcr4_offset + (i + 1) * 32 - 1]), + .scout(sov[cpcr4_offset + i * 32:cpcr4_offset + (i + 1) * 32 - 1]), + .din(cpcr4_d[i]), + .dout(cpcr4_l2[i]) + ); + + // hex 00060010 = 393232 + tri_rlmreg_p #(.WIDTH(32), .INIT(393232)) cpcr5_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cpcr5_wren[i]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[cpcr5_offset + i * 32:cpcr5_offset + (i + 1) * 32 - 1]), + .scout(sov[cpcr5_offset + i * 32:cpcr5_offset + (i + 1) * 32 - 1]), + .din(cpcr5_d[i]), + .dout(cpcr5_l2[i]) + ); + end + end + endgenerate + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) cpcr_we_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[cpcr_we_offset:cpcr_we_offset + `THREADS-1]), + .scout(sov[cpcr_we_offset:cpcr_we_offset + `THREADS-1]), + .din(spr_cpcr_we_d), + .dout(spr_cpcr_we_l2) + ); + + // hex 0C0C100C = 202117132 + tri_rlmreg_p #(.WIDTH(32), .INIT(`INIT_CPCR0)) cpcr0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cpcr0_wren), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[cpcr0_offset:cpcr0_offset + 32-1]), + .scout(sov[cpcr0_offset:cpcr0_offset + 32-1]), + .din(cpcr0_d), + .dout(cpcr0_l2) + ); + + // hex 000C0C00 = 789504 + tri_rlmreg_p #(.WIDTH(32), .INIT(`INIT_CPCR1)) cpcr1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cpcr1_wren), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[cpcr1_offset:cpcr1_offset + 32-1]), + .scout(sov[cpcr1_offset:cpcr1_offset + 32-1]), + .din(cpcr1_d), + .dout(cpcr1_l2) + ); + + //init 0x00000000 + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0)) iac1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iac1_wren), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iac1_offset:iac1_offset + `EFF_IFAR_ARCH - 1]), + .scout(sov[iac1_offset:iac1_offset + `EFF_IFAR_ARCH - 1]), + .din(iac1_d), + .dout(iac1_l2) + ); + + //init 0x00000000 + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0)) iac2_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iac2_wren), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iac2_offset:iac2_offset + `EFF_IFAR_ARCH - 1]), + .scout(sov[iac2_offset:iac2_offset + `EFF_IFAR_ARCH - 1]), + .din(iac2_d), + .dout(iac2_l2) + ); + + //init 0x00000000 + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0)) iac3_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iac3_wren), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iac3_offset:iac3_offset + `EFF_IFAR_ARCH - 1]), + .scout(sov[iac3_offset:iac3_offset + `EFF_IFAR_ARCH - 1]), + .din(iac3_d), + .dout(iac3_l2) + ); + + //init 0x00000000 + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0)) iac4_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iac4_wren), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iac4_offset:iac4_offset + `EFF_IFAR_ARCH - 1]), + .scout(sov[iac4_offset:iac4_offset + `EFF_IFAR_ARCH - 1]), + .din(iac4_d), + .dout(iac4_l2) + ); + + tri_ser_rlmreg_p #(.WIDTH(32), .INIT(26)) iulfsr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iulfsr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iulfsr_offset:iulfsr_offset + 32 - 1]), + .scout(sov[iulfsr_offset:iulfsr_offset + 32 - 1]), + .din(iulfsr_d), + .dout(iulfsr_l2) + ); + + tri_ser_rlmreg_p #(.WIDTH(9), .INIT(0)) iudbg0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iudbg0_wren), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iudbg0_offset:iudbg0_offset + 9 - 1]), + .scout(sov[iudbg0_offset:iudbg0_offset + 9 - 1]), + .din(iudbg0_d), + .dout(iudbg0_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) iudbg0_done_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iudbg0_done_wren), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iudbg0_done_offset]), + .scout(sov[iudbg0_done_offset]), + .din(iudbg0_done_d), + .dout(iudbg0_done_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) iudbg0_exec_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iudbg0_exec_wren), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iudbg0_exec_offset]), + .scout(sov[iudbg0_exec_offset]), + .din(iudbg0_exec_d), + .dout(iudbg0_exec_l2) + ); + + tri_ser_rlmreg_p #(.WIDTH(11), .INIT(0)) iudbg1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iudbg1_wren), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iudbg1_offset:iudbg1_offset + 11 - 1]), + .scout(sov[iudbg1_offset:iudbg1_offset + 11 - 1]), + .din(iudbg1_d), + .dout(iudbg1_l2) + ); + + tri_ser_rlmreg_p #(.WIDTH(29), .INIT(0)) iudbg2_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iudbg2_wren), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iudbg2_offset:iudbg2_offset + 29 - 1]), + .scout(sov[iudbg2_offset:iudbg2_offset + 29 - 1]), + .din(iudbg2_d), + .dout(iudbg2_l2) + ); + + //init 0x00020040 + tri_ser_rlmreg_p #(.WIDTH(18), .INIT(131136)) iullcr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iullcr_wren), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iullcr_offset:iullcr_offset + 18 - 1]), + .scout(sov[iullcr_offset:iullcr_offset + 18 - 1]), + .din(iullcr_d), + .dout(iullcr_l2) + ); + + tri_ser_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) cp_flush_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[cp_flush_offset:cp_flush_offset + `THREADS - 1]), + .scout(sov[cp_flush_offset:cp_flush_offset + `THREADS - 1]), + .din(cp_flush), + .dout(cp_flush_l2) + ); + + tri_ser_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) spr_msr_gs_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[spr_msr_gs_offset:spr_msr_gs_offset + `THREADS - 1]), + .scout(sov[spr_msr_gs_offset:spr_msr_gs_offset + `THREADS - 1]), + .din(spr_msr_gs), + .dout(spr_msr_gs_l2) + ); + + tri_ser_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) spr_msr_pr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[spr_msr_pr_offset:spr_msr_pr_offset + `THREADS - 1]), + .scout(sov[spr_msr_pr_offset:spr_msr_pr_offset + `THREADS - 1]), + .din(spr_msr_pr), + .dout(spr_msr_pr_l2) + ); + + tri_ser_rlmreg_p #(.WIDTH(3), .INIT(0)) xu_iu_pri_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[xu_iu_pri_offset:xu_iu_pri_offset + 3 - 1]), + .scout(sov[xu_iu_pri_offset:xu_iu_pri_offset + 3 - 1]), + .din(xu_iu_pri), + .dout(xu_iu_pri_l2) + ); + + tri_ser_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) xu_iu_pri_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[xu_iu_pri_val_offset:xu_iu_pri_val_offset + `THREADS - 1]), + .scout(sov[xu_iu_pri_val_offset:xu_iu_pri_val_offset + `THREADS - 1]), + .din(xu_iu_pri_val), + .dout(xu_iu_pri_val_l2) + ); + + tri_ser_rlmreg_p #(.WIDTH(32), .INIT(0)) iesr3_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iesr3_wren), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iesr3_offset:iesr3_offset + 32 - 1]), + .scout(sov[iesr3_offset:iesr3_offset + 32 - 1]), + .din(iesr3_d), + .dout(iesr3_l2) + ); + + tri_ser_rlmreg_p #(.WIDTH(24), .INIT(0)) iesr1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iesr1_wren), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iesr1_offset:iesr1_offset + 24 - 1]), + .scout(sov[iesr1_offset:iesr1_offset + 24 - 1]), + .din(iesr1_d), + .dout(iesr1_l2) + ); + + tri_ser_rlmreg_p #(.WIDTH(24), .INIT(0)) iesr2_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iesr2_wren), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iesr2_offset:iesr2_offset + 24 - 1]), + .scout(sov[iesr2_offset:iesr2_offset + 24 - 1]), + .din(iesr2_d), + .dout(iesr2_l2) + ); + + tri_ser_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) raise_iss_pri_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[raise_iss_pri_offset:raise_iss_pri_offset + `THREADS - 1]), + .scout(sov[raise_iss_pri_offset:raise_iss_pri_offset + `THREADS - 1]), + .din(xu_iu_raise_iss_pri), + .dout(xu_iu_raise_iss_pri_l2) + ); + + //----------------------------------------------- + // inputs + //----------------------------------------------- + assign slowspr_val_d = iu_slowspr_val_in & ~|(slowspr_tid[0:`THREADS - 1] & cp_flush_l2); + assign slowspr_rw_d = iu_slowspr_rw_in; + assign slowspr_etid_d = iu_slowspr_etid_in; + assign slowspr_addr_d = iu_slowspr_addr_in; + assign slowspr_data_d = iu_slowspr_data_in; + assign slowspr_done_d = iu_slowspr_done_in; + + //----------------------------------------------- + // outputs + //----------------------------------------------- + assign slowspr_tid = (iu_slowspr_etid_in == 2'b00) ? 4'b1000 : + (iu_slowspr_etid_in == 2'b01) ? 4'b0100 : + (iu_slowspr_etid_in == 2'b10) ? 4'b0010 : + (iu_slowspr_etid_in == 2'b11) ? 4'b0001 : + 4'b0000; + assign iu_slowspr_val_out = slowspr_val_l2; + assign iu_slowspr_rw_out = slowspr_rw_l2; + assign iu_slowspr_etid_out = slowspr_etid_l2; + assign iu_slowspr_addr_out = slowspr_addr_l2; + assign iu_slowspr_data_out = slowspr_data_l2 | iu_slowspr_data; + assign iu_slowspr_done_out = slowspr_done_l2 | iu_slowspr_done; + + assign spr_dec_mask[0:31] = immr0_l2[32:63]; + assign spr_dec_match[0:31] = imr0_l2[32:63]; + + assign spr_ic_clockgate_dis = iucr0_l2[48]; + assign spr_ic_prefetch_dis = iucr0_l2[49]; + assign spr_ic_cls = iucr0_l2[50]; + assign spr_ic_icbi_ack_en = iucr0_l2[51]; + + assign spr_ic_bp_config = iucr0_l2[56:59]; + assign spr_bp_config = {iucr0_l2[60:63], iucr0_l2[54:55]}; + assign spr_single_issue = {`THREADS{1'b0}}; + assign iu_au_t0_config_iucr = iucr2_l2[0]; +`ifndef THREADS1 + assign iu_au_t1_config_iucr = iucr2_l2[1]; +`endif + assign spr_ivpr = ivpr_l2; + assign spr_givpr = givpr_l2; + + assign spr_iac1 = iac1_l2; + assign spr_iac2 = iac2_l2; + assign spr_iac3 = iac3_l2; + assign spr_iac4 = iac4_l2; + + assign spr_cpcr_we = spr_cpcr_we_l2; + + assign spr_t0_cpcr2_fx0_cnt = cpcr2_l2[0][35:39]; + assign spr_t0_cpcr2_fx1_cnt = cpcr2_l2[0][43:47]; + assign spr_t0_cpcr2_lq_cnt = cpcr2_l2[0][51:55]; + assign spr_t0_cpcr2_sq_cnt = cpcr2_l2[0][59:63]; + assign spr_t0_cpcr3_fu0_cnt = cpcr3_l2[0][43:47]; + assign spr_t0_cpcr3_fu1_cnt = cpcr3_l2[0][51:55]; + assign spr_t0_cpcr3_cp_cnt = cpcr3_l2[0][57:63]; + assign spr_t0_cpcr4_fx0_cnt = cpcr4_l2[0][35:39]; + assign spr_t0_cpcr4_fx1_cnt = cpcr4_l2[0][43:47]; + assign spr_t0_cpcr4_lq_cnt = cpcr4_l2[0][51:55]; + assign spr_t0_cpcr4_sq_cnt = cpcr4_l2[0][59:63]; + assign spr_t0_cpcr5_fu0_cnt = cpcr5_l2[0][43:47]; + assign spr_t0_cpcr5_fu1_cnt = cpcr5_l2[0][51:55]; + assign spr_t0_cpcr5_cp_cnt = cpcr5_l2[0][57:63]; +`ifndef THREADS1 + assign spr_t1_cpcr2_fx0_cnt = cpcr2_l2[1][35:39]; + assign spr_t1_cpcr2_fx1_cnt = cpcr2_l2[1][43:47]; + assign spr_t1_cpcr2_lq_cnt = cpcr2_l2[1][51:55]; + assign spr_t1_cpcr2_sq_cnt = cpcr2_l2[1][59:63]; + assign spr_t1_cpcr3_fu0_cnt = cpcr3_l2[1][43:47]; + assign spr_t1_cpcr3_fu1_cnt = cpcr3_l2[1][51:55]; + assign spr_t1_cpcr3_cp_cnt = cpcr3_l2[1][57:63]; + assign spr_t1_cpcr4_fx0_cnt = cpcr4_l2[1][35:39]; + assign spr_t1_cpcr4_fx1_cnt = cpcr4_l2[1][43:47]; + assign spr_t1_cpcr4_lq_cnt = cpcr4_l2[1][51:55]; + assign spr_t1_cpcr4_sq_cnt = cpcr4_l2[1][59:63]; + assign spr_t1_cpcr5_fu0_cnt = cpcr5_l2[1][43:47]; + assign spr_t1_cpcr5_fu1_cnt = cpcr5_l2[1][51:55]; + assign spr_t1_cpcr5_cp_cnt = cpcr5_l2[1][57:63]; +`endif + assign spr_cpcr0_fx0_cnt = cpcr0_l2[35:39]; + assign spr_cpcr0_fx1_cnt = cpcr0_l2[43:47]; + assign spr_cpcr0_lq_cnt = cpcr0_l2[51:55]; + assign spr_cpcr0_sq_cnt = cpcr0_l2[59:63]; + assign spr_cpcr1_fu0_cnt = cpcr1_l2[43:47]; + assign spr_cpcr1_fu1_cnt = cpcr1_l2[51:55]; + + assign spr_t0_low_pri_count = iucr1_l2[0][58:63]; +`ifndef THREADS1 + assign spr_t1_low_pri_count = iucr1_l2[1][58:63]; +`endif + + assign spr_bp_size = 2'b0; + + assign spr_ic_idir_read = iudbg0_exec_l2; + assign spr_ic_idir_way = iudbg0_l2[49:50]; + assign spr_ic_idir_row = iudbg0_l2[51:57]; + + assign spr_perf_event_mux_ctrls = {iesr1_l2[32:55], iesr2_l2[32:55]}; + assign spr_cp_perf_event_mux_ctrls = iesr3_l2[32:63]; + + //----------------------------------------------- + // register select + //----------------------------------------------- + assign slowspr_val_act = slowspr_val_d | slowspr_val_l2; + + assign ivpr_sel = slowspr_val_l2 & slowspr_addr_l2 == 10'b0000111111; //63 + assign givpr_sel = slowspr_val_l2 & slowspr_addr_l2 == 10'b0110111111; //447 + assign immr0_sel = slowspr_val_l2 & slowspr_addr_l2 == 10'b1101110001; //881 + assign imr0_sel = slowspr_val_l2 & slowspr_addr_l2 == 10'b1101110000; //880 + assign iulfsr_sel = slowspr_val_l2 & slowspr_addr_l2 == 10'b1101111011; //891 + assign iudbg0_sel = slowspr_val_l2 & slowspr_addr_l2 == 10'b1101111000; //888 + assign iudbg1_sel = slowspr_val_l2 & slowspr_addr_l2 == 10'b1101111001; //889 + assign iudbg2_sel = slowspr_val_l2 & slowspr_addr_l2 == 10'b1101111010; //890 + assign iullcr_sel = slowspr_val_l2 & slowspr_addr_l2 == 10'b1101111100; //892 + assign iucr0_sel = slowspr_val_l2 & slowspr_addr_l2 == 10'b1111110011; //1011 + assign cpcr0_sel = slowspr_val_l2 & slowspr_addr_l2 == 10'b1100110000; //816 + assign cpcr1_sel = slowspr_val_l2 & slowspr_addr_l2 == 10'b1100110001; //817 + assign eheir_sel[0] = slowspr_val_l2 & (slowspr_addr_l2 == 10'b0000110100) & slowspr_etid_l2 === 2'b00; //52 + assign iucr1_sel[0] = slowspr_val_l2 & (slowspr_addr_l2 == 10'b1101110011) & slowspr_etid_l2 === 2'b00; //883,ti + assign iucr2_sel[0] = slowspr_val_l2 & (slowspr_addr_l2 == 10'b1101110100) & slowspr_etid_l2 === 2'b00; //884,ti + assign ppr32_sel[0] = slowspr_val_l2 & (slowspr_addr_l2 == 10'b1110000010) & slowspr_etid_l2 === 2'b00; //898,ti + assign cpcr2_sel[0] = slowspr_val_l2 & (slowspr_addr_l2 == 10'b1100110010) & slowspr_etid_l2 === 2'b00; //818 + assign cpcr3_sel[0] = slowspr_val_l2 & (slowspr_addr_l2 == 10'b1100110100) & slowspr_etid_l2 === 2'b00; //820 + assign cpcr4_sel[0] = slowspr_val_l2 & (slowspr_addr_l2 == 10'b1100110101) & slowspr_etid_l2 === 2'b00; //821 + assign cpcr5_sel[0] = slowspr_val_l2 & (slowspr_addr_l2 == 10'b1100110110) & slowspr_etid_l2 === 2'b00; //822 + +`ifndef THREADS1 + assign eheir_sel[1] = slowspr_val_l2 & (slowspr_addr_l2 == 10'b0000110100) & slowspr_etid_l2 === 2'b01; //52 + assign iucr1_sel[1] = slowspr_val_l2 & (slowspr_addr_l2 == 10'b1101110011) & slowspr_etid_l2 === 2'b01; //883,ti + assign iucr2_sel[1] = slowspr_val_l2 & (slowspr_addr_l2 == 10'b1101110100) & slowspr_etid_l2 === 2'b01; //884,ti + assign ppr32_sel[1] = slowspr_val_l2 & (slowspr_addr_l2 == 10'b1110000010) & slowspr_etid_l2 === 2'b01; //898,ti + assign cpcr2_sel[1] = slowspr_val_l2 & (slowspr_addr_l2 == 10'b1100110010) & slowspr_etid_l2 === 2'b01; //818 + assign cpcr3_sel[1] = slowspr_val_l2 & (slowspr_addr_l2 == 10'b1100110100) & slowspr_etid_l2 === 2'b01; //820 + assign cpcr4_sel[1] = slowspr_val_l2 & (slowspr_addr_l2 == 10'b1100110101) & slowspr_etid_l2 === 2'b01; //821 + assign cpcr5_sel[1] = slowspr_val_l2 & (slowspr_addr_l2 == 10'b1100110110) & slowspr_etid_l2 === 2'b01; //822 +`endif + + assign iac1_sel = slowspr_val_l2 & slowspr_addr_l2 == 10'b0100111000; //312 + assign iac2_sel = slowspr_val_l2 & slowspr_addr_l2 == 10'b0100111001; //313 + assign iac3_sel = slowspr_val_l2 & slowspr_addr_l2 == 10'b0100111010; //314 + assign iac4_sel = slowspr_val_l2 & slowspr_addr_l2 == 10'b0100111011; //315 + assign iesr3_sel = slowspr_val_l2 & slowspr_addr_l2 == 10'b1110011100; //924 + assign iesr1_sel = slowspr_val_l2 & slowspr_addr_l2 == 10'b1110010010; //914 + assign iesr2_sel = slowspr_val_l2 & slowspr_addr_l2 == 10'b1110010011; //915 + + assign iu_slowspr_done = (ivpr_sel | givpr_sel | immr0_sel | imr0_sel | iulfsr_sel | iullcr_sel | iucr0_sel | iudbg0_sel | iudbg1_sel | iudbg2_sel) | + (|eheir_sel) | (|iucr1_sel) | (|iucr2_sel) | (|ppr32_sel) | iac1_sel | iac2_sel | iac3_sel | iac4_sel | cpcr0_sel | + cpcr1_sel | (|cpcr2_sel) | (|cpcr3_sel) | (|cpcr4_sel) | (|cpcr5_sel) |iesr3_sel | iesr1_sel | iesr2_sel; + + //----------------------------------------------- + // set priority levels + //----------------------------------------------- + assign priv_mode = (~spr_msr_pr_l2); + assign hypv_mode = (~spr_msr_pr_l2) & (~spr_msr_gs_l2); + + generate + begin : priset + genvar i; + for (i = 0; i <= `THREADS - 1; i = i + 1) + begin : pricalc + assign lo_pri[i] = ~xu_iu_raise_iss_pri_l2[i] & + (ppr32_l2[i][43:45] == 3'b000 | + ppr32_l2[i][43:45] == 3'b001 | + ppr32_l2[i][43:45] == 3'b010); + + assign hi_pri[i] =(ppr32_l2[i][43:45] == 3'b100 & iucr1_l2[i][50:51] == 2'b00) | + (ppr32_l2[i][43:45] == 3'b101 & (iucr1_l2[i][50:51] == 2'b00 | iucr1_l2[i][50:51] == 2'b01)) | + (ppr32_l2[i][43:45] == 3'b110 & (iucr1_l2[i][50:51] == 2'b00 | iucr1_l2[i][50:51] == 2'b01 | iucr1_l2[i][50:51] == 2'b10)) | + ppr32_l2[i][43:45] == 3'b111; + + assign spr_high_pri_mask[i] = hi_pri[i]; + assign spr_med_pri_mask[i] = ~hi_pri[i] & ~lo_pri[i]; + end + end + endgenerate + + + //----------------------------------------------- + // register write + //----------------------------------------------- + assign iudbg0_exec_wren = iudbg0_wren | iudbg0_exec_l2; + assign iudbg0_done_wren = iudbg0_wren | ic_spr_idir_done; + + assign iudbg1_wren = ic_spr_idir_done; + assign iudbg2_wren = ic_spr_idir_done; + + assign ivpr_wren = ivpr_sel & slowspr_rw_l2 == 1'b0; + assign givpr_wren = givpr_sel & slowspr_rw_l2 == 1'b0; + assign immr0_wren = immr0_sel & slowspr_rw_l2 == 1'b0; + assign imr0_wren = imr0_sel & slowspr_rw_l2 == 1'b0; + assign iulfsr_wren = iulfsr_sel & slowspr_rw_l2 == 1'b0; + assign iudbg0_wren = iudbg0_sel & slowspr_rw_l2 == 1'b0; + assign iullcr_wren = iullcr_sel & slowspr_rw_l2 == 1'b0; + assign iucr0_wren = iucr0_sel & slowspr_rw_l2 == 1'b0; + assign eheir_wren[0] = ((slowspr_rw_l2 == 1'b0) & eheir_sel[0]) | iu_spr_eheir_update[0]; +`ifndef THREADS1 + assign eheir_wren[1] = ((slowspr_rw_l2 == 1'b0) & eheir_sel[1]) | iu_spr_eheir_update[1]; +`endif + assign iucr1_wren = ({`THREADS{slowspr_rw_l2 == 1'b0}} & iucr1_sel); + assign iucr2_wren = ({`THREADS{slowspr_rw_l2 == 1'b0}} & iucr2_sel); + assign iac1_wren = iac1_sel & slowspr_rw_l2 == 1'b0; + assign iac2_wren = iac2_sel & slowspr_rw_l2 == 1'b0; + assign iac3_wren = iac3_sel & slowspr_rw_l2 == 1'b0; + assign iac4_wren = iac4_sel & slowspr_rw_l2 == 1'b0; + assign cpcr0_wren = cpcr0_sel & slowspr_rw_l2 == 1'b0; + assign cpcr1_wren = cpcr1_sel & slowspr_rw_l2 == 1'b0; + assign cpcr2_wren = ({`THREADS{slowspr_rw_l2 == 1'b0}} & cpcr2_sel); + assign cpcr3_wren = ({`THREADS{slowspr_rw_l2 == 1'b0}} & cpcr3_sel); + assign cpcr4_wren = ({`THREADS{slowspr_rw_l2 == 1'b0}} & cpcr4_sel); + assign cpcr5_wren = ({`THREADS{slowspr_rw_l2 == 1'b0}} & cpcr5_sel); + assign iesr3_wren = iesr3_sel & slowspr_rw_l2 == 1'b0; + assign iesr1_wren = iesr1_sel & slowspr_rw_l2 == 1'b0; + assign iesr2_wren = iesr2_sel & slowspr_rw_l2 == 1'b0; + + assign ppr32_wren[0] = ((ppr32_sel[0] & slowspr_rw_l2 == 1'b0) | xu_iu_pri_val_l2[0]) & + ((ppr32_d[0] == 3'b001 & priv_mode[0]) | (ppr32_d[0] == 3'b010) | (ppr32_d[0] == 3'b011) | + (ppr32_d[0] == 3'b100) | (ppr32_d[0] == 3'b101 & priv_mode[0]) | (ppr32_d[0] == 3'b110 & priv_mode[0]) | + (ppr32_d[0] == 3'b111 & hypv_mode[0])); + +`ifndef THREADS1 + assign ppr32_wren[1] = ((ppr32_sel[1] & slowspr_rw_l2 == 1'b0) | xu_iu_pri_val_l2[1]) & + ((ppr32_d[1] == 3'b001 & priv_mode[1]) | (ppr32_d[1] == 3'b010) | (ppr32_d[1] == 3'b011) | + (ppr32_d[1] == 3'b100) | (ppr32_d[1] == 3'b101 & priv_mode[1]) | (ppr32_d[1] == 3'b110 & priv_mode[1]) | + (ppr32_d[1] == 3'b111 & hypv_mode[1])); +`endif + + assign ivpr_d = slowspr_data_l2[64 - `GPR_WIDTH:51]; + assign givpr_d = slowspr_data_l2[64 - `GPR_WIDTH:51]; + + assign immr0_d = IMMR0_MASK & slowspr_data_l2[32:63]; + assign imr0_d = IMR0_MASK & slowspr_data_l2[32:63]; + + assign iulfsr[1:28] = iulfsr_l2[32:59]; + assign iulfsr_d = (iulfsr_wren == 1'b1) ? IULFSR_MASK & slowspr_data_l2[32:63] : + {(iulfsr[28] ^ iulfsr[27] ^ iulfsr[26] ^ iulfsr[25] ^ iulfsr[24] ^ iulfsr[8]), iulfsr[1:27], iulfsr_l2[60:63]}; + assign iulfsr_act = iulfsr_wren; + + assign iudbg0_d = IUDBG0_MASK[49:57] & slowspr_data_l2[49:57]; + assign iudbg0_exec_d = (iudbg0_wren == 1'b1) ? IUDBG0_MASK[62] & slowspr_data_l2[62] : + 1'b0; + assign iudbg0_done_d = (iudbg0_wren == 1'b1) ? IUDBG0_MASK[63] & slowspr_data_l2[63] : + ic_spr_idir_done; + + assign iudbg1_d = IUDBG1_MASK[53:63] & ({ic_spr_idir_lru[0:2], ic_spr_idir_parity[0:3], ic_spr_idir_endian, 2'b00, ic_spr_idir_valid}); + assign iudbg2_d = IUDBG2_MASK[35:63] & ic_spr_idir_tag[0:28]; + + assign iullcr_d = IULLCR_MASK[46:63] & slowspr_data_l2[46:63]; + + assign iucr0_d = IUCR0_MASK[48:63] & ({slowspr_data_l2[48:49], iucr0_l2[50], slowspr_data_l2[51:63]}); + + assign eheir_d[0] = (iu_spr_eheir_update[0] == 1'b1) ? iu_spr_t0_eheir : slowspr_data_l2[32:63]; + assign iucr1_d[0] = IUCR1_MASK[50:63] & slowspr_data_l2[50:63]; + assign iucr2_d[0] = IUCR2_MASK[32:39] & slowspr_data_l2[32:39]; + assign ppr32_d[0] = (xu_iu_pri_val_l2[0] == 1'b1) ? PPR32_MASK[43:45] & xu_iu_pri_l2[0:2] : PPR32_MASK[43:45] & slowspr_data_l2[43:45]; + assign spr_cpcr_we_d[0] = (~slowspr_etid_l2[1] & cpcr0_wren) | (~slowspr_etid_l2[1] & cpcr1_wren) | cpcr2_wren[0] | cpcr3_wren[0] | cpcr4_wren[0] | cpcr5_wren[0]; + assign cpcr0_d = {3'b0, slowspr_data_l2[35:39], 3'b0, slowspr_data_l2[43:47], 3'b0, slowspr_data_l2[51:55], 3'b0, slowspr_data_l2[59:63]}; + assign cpcr1_d = {11'b0, slowspr_data_l2[43:47], 3'b0, slowspr_data_l2[51:55], 8'b0}; + assign cpcr2_d[0] = {3'b0, slowspr_data_l2[35:39], 3'b0, slowspr_data_l2[43:47], 3'b0, slowspr_data_l2[51:55], 3'b0, slowspr_data_l2[59:63]}; + assign cpcr3_d[0] = {11'b0, slowspr_data_l2[43:47], 3'b0, slowspr_data_l2[51:55], 1'b0, slowspr_data_l2[57:63]}; + assign cpcr4_d[0] = {3'b0, slowspr_data_l2[35:39], 3'b0, slowspr_data_l2[43:47], 3'b0, slowspr_data_l2[51:55], 3'b0, slowspr_data_l2[59:63]}; + assign cpcr5_d[0] = {11'b0, slowspr_data_l2[43:47], 3'b0, slowspr_data_l2[51:55], 1'b0, slowspr_data_l2[57:63]}; + +`ifndef THREADS1 + assign eheir_d[1] = (iu_spr_eheir_update[1] == 1'b1) ? iu_spr_t1_eheir : slowspr_data_l2[32:63]; + assign iucr1_d[1] = IUCR1_MASK[50:63] & slowspr_data_l2[50:63]; + assign iucr2_d[1] = IUCR2_MASK[32:39] & slowspr_data_l2[32:39]; + assign ppr32_d[1] = (xu_iu_pri_val_l2[1] == 1'b1) ? PPR32_MASK[43:45] & xu_iu_pri_l2[0:2] : PPR32_MASK[43:45] & slowspr_data_l2[43:45]; + assign spr_cpcr_we_d[1] = (slowspr_etid_l2[1] & cpcr0_wren) | (slowspr_etid_l2[1] & cpcr1_wren) | cpcr2_wren[1] | cpcr3_wren[1] | cpcr4_wren[1] | cpcr5_wren[1]; + assign cpcr2_d[1] = {3'b0, slowspr_data_l2[35:39], 3'b0, slowspr_data_l2[43:47], 3'b0, slowspr_data_l2[51:55], 3'b0, slowspr_data_l2[59:63]}; + assign cpcr3_d[1] = {11'b0, slowspr_data_l2[43:47], 3'b0, slowspr_data_l2[51:55], 1'b0, slowspr_data_l2[57:63]}; + assign cpcr4_d[1] = {3'b0, slowspr_data_l2[35:39], 3'b0, slowspr_data_l2[43:47], 3'b0, slowspr_data_l2[51:55], 3'b0, slowspr_data_l2[59:63]}; + assign cpcr5_d[1] = {11'b0, slowspr_data_l2[43:47], 3'b0, slowspr_data_l2[51:55], 1'b0, slowspr_data_l2[57:63]}; + `endif + + assign iac1_d = slowspr_data_l2[62 - (`EFF_IFAR_ARCH):61]; + assign iac2_d = slowspr_data_l2[62 - (`EFF_IFAR_ARCH):61]; + assign iac3_d = slowspr_data_l2[62 - (`EFF_IFAR_ARCH):61]; + assign iac4_d = slowspr_data_l2[62 - (`EFF_IFAR_ARCH):61]; + + assign iesr3_d = slowspr_data_l2[32:63]; + assign iesr1_d = EVENTMUX_128_MASK[32:55] & slowspr_data_l2[32:55]; + assign iesr2_d = EVENTMUX_128_MASK[32:55] & slowspr_data_l2[32:55]; + + //----------------------------------------------- + // register read + //----------------------------------------------- + assign ivpr_rden = ivpr_sel & slowspr_rw_l2 == 1'b1; + assign givpr_rden = givpr_sel & slowspr_rw_l2 == 1'b1; + assign immr0_rden = immr0_sel & slowspr_rw_l2 == 1'b1; + assign imr0_rden = imr0_sel & slowspr_rw_l2 == 1'b1; + assign iulfsr_rden = iulfsr_sel & slowspr_rw_l2 == 1'b1; + assign iudbg0_rden = iudbg0_sel & slowspr_rw_l2 == 1'b1; + assign iudbg1_rden = iudbg1_sel & slowspr_rw_l2 == 1'b1; + assign iudbg2_rden = iudbg2_sel & slowspr_rw_l2 == 1'b1; + assign iullcr_rden = iullcr_sel & slowspr_rw_l2 == 1'b1; + assign iucr0_rden = iucr0_sel & slowspr_rw_l2 == 1'b1; + assign eheir_rden = {`THREADS{slowspr_rw_l2 == 1'b1}} & eheir_sel; + assign iucr1_rden = {`THREADS{slowspr_rw_l2 == 1'b1}} & iucr1_sel; + assign iucr2_rden = {`THREADS{slowspr_rw_l2 == 1'b1}} & iucr2_sel; + assign ppr32_rden = {`THREADS{slowspr_rw_l2 == 1'b1}} & ppr32_sel; + assign iac1_rden = iac1_sel & slowspr_rw_l2 == 1'b1; + assign iac2_rden = iac2_sel & slowspr_rw_l2 == 1'b1; + assign iac3_rden = iac3_sel & slowspr_rw_l2 == 1'b1; + assign iac4_rden = iac4_sel & slowspr_rw_l2 == 1'b1; + assign cpcr0_rden = cpcr0_sel & slowspr_rw_l2 == 1'b1; + assign cpcr1_rden = cpcr1_sel & slowspr_rw_l2 == 1'b1; + assign cpcr2_rden = {`THREADS{slowspr_rw_l2 == 1'b1}} & cpcr2_sel; + assign cpcr3_rden = {`THREADS{slowspr_rw_l2 == 1'b1}} & cpcr3_sel; + assign cpcr4_rden = {`THREADS{slowspr_rw_l2 == 1'b1}} & cpcr4_sel; + assign cpcr5_rden = {`THREADS{slowspr_rw_l2 == 1'b1}} & cpcr5_sel; + assign iesr3_rden = iesr3_sel & slowspr_rw_l2 == 1'b1; + assign iesr1_rden = iesr1_sel & slowspr_rw_l2 == 1'b1; + assign iesr2_rden = iesr2_sel & slowspr_rw_l2 == 1'b1; + + generate + if (`GPR_WIDTH == 64) + begin : r64 + assign iu_slowspr_data[0:31] = (ivpr_rden == 1'b1) ? ivpr_l2[0:31] : + (givpr_rden == 1'b1) ? givpr_l2[0:31] : + (iac1_rden == 1'b1) ? iac1[0:31] : + (iac2_rden == 1'b1) ? iac2[0:31] : + (iac3_rden == 1'b1) ? iac3[0:31] : + (iac4_rden == 1'b1) ? iac4[0:31] : + {32{1'b0}}; + end + endgenerate + assign iu_slowspr_data[32:63] = (ivpr_rden == 1'b1) ? {ivpr_l2[32:51], 12'b000000000000} : + (givpr_rden == 1'b1) ? {givpr_l2[32:51], 12'b000000000000} : + (immr0_rden == 1'b1) ? immr0_l2 : + (imr0_rden == 1'b1) ? imr0_l2 : + (iulfsr_rden == 1'b1) ? iulfsr_l2 : + (iudbg0_rden == 1'b1) ? iudbg0 : + (iudbg1_rden == 1'b1) ? iudbg1 : + (iudbg2_rden == 1'b1) ? iudbg2 : + (iullcr_rden == 1'b1) ? iullcr : + (iucr0_rden == 1'b1) ? iucr0 : + (eheir_rden[0] == 1'b1) ? eheir[0] : + (iucr1_rden[0] == 1'b1) ? iucr1[0] : + (iucr2_rden[0] == 1'b1) ? iucr2[0] : + (ppr32_rden[0] == 1'b1) ? ppr32[0] : + (cpcr0_rden == 1'b1) ? cpcr0 : + (cpcr1_rden == 1'b1) ? cpcr1 : + (cpcr2_rden[0] == 1'b1) ? cpcr2[0] : + (cpcr3_rden[0] == 1'b1) ? cpcr3[0] : + (cpcr4_rden[0] == 1'b1) ? cpcr4[0] : + (cpcr5_rden[0] == 1'b1) ? cpcr5[0] : +`ifndef THREADS1 + (eheir_rden[1] == 1'b1) ? eheir[1] : + (iucr1_rden[1] == 1'b1) ? iucr1[1] : + (iucr2_rden[1] == 1'b1) ? iucr2[1] : + (ppr32_rden[1] == 1'b1) ? ppr32[1] : + (cpcr2_rden[1] == 1'b1) ? cpcr2[1] : + (cpcr3_rden[1] == 1'b1) ? cpcr3[1] : + (cpcr4_rden[1] == 1'b1) ? cpcr4[1] : + (cpcr5_rden[1] == 1'b1) ? cpcr5[1] : +`endif + (iac1_rden == 1'b1) ? iac1[32:63] : + (iac2_rden == 1'b1) ? iac2[32:63] : + (iac3_rden == 1'b1) ? iac3[32:63] : + (iac4_rden == 1'b1) ? iac4[32:63] : + (iesr3_rden == 1'b1) ? iesr3_l2[32:63] : + (iesr1_rden == 1'b1) ? {iesr1_l2[32:55], 8'h00} : + (iesr2_rden == 1'b1) ? {iesr2_l2[32:55], 8'h00} : + {32{1'b0}}; + + assign iudbg0[32:63] = {IUDBG0_MASK[32:48], iudbg0_l2[49:57], IUDBG0_MASK[58:61], iudbg0_exec_l2, iudbg0_done_l2}; + assign iudbg1[32:63] = {IUDBG1_MASK[32:52], iudbg1_l2[53:63]}; + assign iudbg2[32:63] = {IUDBG2_MASK[32:34], iudbg2_l2[35:63]}; + + assign iullcr[32:63] = {IULLCR_MASK[32:45], iullcr_l2[46:63]}; + + assign iucr0[32:63] = {IUCR0_MASK[32:47], iucr0_l2[48:63]}; + assign eheir[0] = {32{eheir_rden[0]}} & eheir_l2[0]; + assign iucr1[0] = {32{iucr1_rden[0]}} & {IUCR1_MASK[32:49], iucr1_l2[0]}; + assign iucr2[0] = {32{iucr2_rden[0]}} & {iucr2_l2[0], IUCR2_MASK[40:63]}; + assign ppr32[0] = {32{ppr32_rden[0]}} & {PPR32_MASK[32:42], ppr32_l2[0], PPR32_MASK[46:63]}; + assign cpcr0 = {32{cpcr0_rden}} & {3'b0, cpcr0_l2[35:39], 3'b0, cpcr0_l2[43:47], 3'b0, cpcr0_l2[51:55], 3'b0, cpcr0_l2[59:63]}; + assign cpcr1 = {32{cpcr1_rden}} & {11'b0, cpcr1_l2[43:47], 3'b0, cpcr1_l2[51:55], 8'b0}; + assign cpcr2[0] = {32{cpcr2_rden[0]}} & {3'b0, cpcr2_l2[0][35:39], 3'b0, cpcr2_l2[0][43:47], 3'b0, cpcr2_l2[0][51:55], 3'b0, cpcr2_l2[0][59:63]}; + assign cpcr3[0] = {32{cpcr3_rden[0]}} & {11'b0, cpcr3_l2[0][43:47], 3'b0, cpcr3_l2[0][51:55], 1'b0, cpcr3_l2[0][57:63]}; + assign cpcr4[0] = {32{cpcr4_rden[0]}} & {3'b0, cpcr4_l2[0][35:39], 3'b0, cpcr4_l2[0][43:47], 3'b0, cpcr4_l2[0][51:55], 3'b0, cpcr4_l2[0][59:63]}; + assign cpcr5[0] = {32{cpcr5_rden[0]}} & {11'b0, cpcr5_l2[0][43:47], 3'b0, cpcr5_l2[0][51:55], 1'b0, cpcr5_l2[0][57:63]}; +`ifndef THREADS1 + assign eheir[1] = {32{eheir_rden[1]}} & eheir_l2[1]; + assign iucr1[1] = {32{iucr1_rden[1]}} & {IUCR1_MASK[32:49], iucr1_l2[1]}; + assign iucr2[1] = {32{iucr2_rden[1]}} & {iucr2_l2[1], IUCR2_MASK[40:63]}; + assign ppr32[1] = {32{ppr32_rden[1]}} & {PPR32_MASK[32:42], ppr32_l2[1], PPR32_MASK[46:63]}; + assign cpcr2[1] = {32{cpcr2_rden[1]}} & {3'b0, cpcr2_l2[1][35:39], 3'b0, cpcr2_l2[1][43:47], 3'b0, cpcr2_l2[1][51:55], 3'b0, cpcr2_l2[1][59:63]}; + assign cpcr3[1] = {32{cpcr3_rden[1]}} & {11'b0, cpcr3_l2[1][43:47], 3'b0, cpcr3_l2[1][51:55], 1'b0, cpcr3_l2[1][57:63]}; + assign cpcr4[1] = {32{cpcr4_rden[1]}} & {3'b0, cpcr4_l2[1][35:39], 3'b0, cpcr4_l2[1][43:47], 3'b0, cpcr4_l2[1][51:55], 3'b0, cpcr4_l2[1][59:63]}; + assign cpcr5[1] = {32{cpcr5_rden[1]}} & {11'b0, cpcr5_l2[1][43:47], 3'b0, cpcr5_l2[1][51:55], 1'b0, cpcr5_l2[1][57:63]}; +`endif + + generate + begin : xhdl7 + genvar i; + for (i = 0; i <= 61; i = i + 1) + begin : iac_width + if (`EFF_IFAR_ARCH > i) + begin : R0 + assign iac1[61 - i] = iac1_l2[61 - i]; + assign iac2[61 - i] = iac2_l2[61 - i]; + assign iac3[61 - i] = iac3_l2[61 - i]; + assign iac4[61 - i] = iac4_l2[61 - i]; + end + if (`EFF_IFAR_ARCH <= i) + begin : R1 + assign iac1[61 - i] = 1'b0; + assign iac2[61 - i] = 1'b0; + assign iac3[61 - i] = 1'b0; + assign iac4[61 - i] = 1'b0; + end + end + end + endgenerate + assign iac1[62:63] = 2'b00; + assign iac2[62:63] = 2'b00; + assign iac3[62:63] = 2'b00; + assign iac4[62:63] = 2'b00; + + //----------------------------------------------- + // pervasive + //----------------------------------------------- + tri_plat #(.WIDTH(2)) perv_2to1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + .din({pc_iu_func_sl_thold_2, pc_iu_sg_2}), + .q({pc_iu_func_sl_thold_1, pc_iu_sg_1}) + ); + + tri_plat #(.WIDTH(2)) perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + .din({pc_iu_func_sl_thold_1, pc_iu_sg_1}), + .q({pc_iu_func_sl_thold_0, pc_iu_sg_0}) + ); + + tri_lcbor perv_lcbor( + .clkoff_b(clkoff_b), + .thold(pc_iu_func_sl_thold_0), + .sg(pc_iu_sg_0), + .act_dis(act_dis), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b) + ); + + //----------------------------------------------- + // scan + //----------------------------------------------- + assign siv[0:scan_right] = {scan_in, sov[0:scan_right - 1]}; + assign scan_out = sov[scan_right]; +endmodule diff --git a/dev/verilog/work/iuq_uc.v b/dev/verilog/work/iuq_uc.v new file mode 100755 index 0000000..0085457 --- /dev/null +++ b/dev/verilog/work/iuq_uc.v @@ -0,0 +1,2126 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//******************************************************************** +//* +//* TITLE: IU Microcode +//* +//* NAME: iuq_uc.v +//* +//********************************************************************* + +`include "tri_a2o.vh" + + +module iuq_uc( + vdd, + gnd, + nclk, + pc_iu_func_sl_thold_2, + pc_iu_sg_2, + tc_ac_ccflush_dc, + clkoff_b, + act_dis, + d_mode, + delay_lclkr, + mpw1_b, + mpw2_b, + scan_in, + scan_out, + iu_pc_err_ucode_illegal, + xu_iu_ucode_xer_val, + xu_iu_ucode_xer, + iu_flush, + br_iu_redirect, + cp_flush_into_uc, + cp_uc_np1_flush, + cp_uc_flush_ifar, + cp_uc_credit_free, + cp_flush, + uc_ic_hold, + uc_iu4_flush, + uc_iu4_flush_ifar, + ic_bp_iu2_val, + ic_bp_iu2_ifar, + ic_bp_iu2_2ucode, + ic_bp_iu2_2ucode_type, + ic_bp_iu2_error, + ic_bp_iu2_flush, + ic_bp_iu3_flush, + ic_bp_iu3_ecc_err, + ic_bp_iu2_0_instr, + ic_bp_iu2_1_instr, + ic_bp_iu2_2_instr, + ic_bp_iu2_3_instr, + bp_ib_iu3_val, + ib_uc_rdy, + uc_ib_iu3_invalid, + uc_ib_iu3_flush_all, + uc_ib_val, + uc_ib_done, + uc_ib_instr0, + uc_ib_instr1, + uc_ib_ifar0, + uc_ib_ifar1, + uc_ib_ext0, + uc_ib_ext1 +); + + + inout vdd; + + inout gnd; + + (* pin_data="PIN_FUNCTION=/G_CLK/" *) + input [0:`NCLK_WIDTH-1] nclk; + input pc_iu_func_sl_thold_2; + input pc_iu_sg_2; + input tc_ac_ccflush_dc; + input clkoff_b; + input act_dis; + input d_mode; + input delay_lclkr; + input mpw1_b; + input mpw2_b; + + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + input scan_in; + + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + output scan_out; + + output iu_pc_err_ucode_illegal; + + input xu_iu_ucode_xer_val; + input [57:63] xu_iu_ucode_xer; + + input iu_flush; + input br_iu_redirect; + input cp_flush_into_uc; + input cp_uc_np1_flush; + input [43:61] cp_uc_flush_ifar; + input cp_uc_credit_free; + input cp_flush; + + output uc_ic_hold; + + output uc_iu4_flush; + output [62-`EFF_IFAR_WIDTH:61] uc_iu4_flush_ifar; + + input [0:3] ic_bp_iu2_val; + input [62-`EFF_IFAR_WIDTH:61] ic_bp_iu2_ifar; + input ic_bp_iu2_2ucode; + input ic_bp_iu2_2ucode_type; + input ic_bp_iu2_error; + input ic_bp_iu2_flush; + input ic_bp_iu3_flush; + input ic_bp_iu3_ecc_err; + + // iu2 instruction(0:31) + predecode(32:35); (32:33) = "01" when uCode + input [0:33] ic_bp_iu2_0_instr; + input [0:33] ic_bp_iu2_1_instr; + input [0:33] ic_bp_iu2_2_instr; + input [0:33] ic_bp_iu2_3_instr; + + input [0:3] bp_ib_iu3_val; + + input ib_uc_rdy; + + output [0:3] uc_ib_iu3_invalid; + output uc_ib_iu3_flush_all; + output reg [0:1] uc_ib_val; + output reg uc_ib_done; + output reg [0:31] uc_ib_instr0; + output reg [0:31] uc_ib_instr1; + output reg [62-`EFF_IFAR_WIDTH:61] uc_ib_ifar0; + output reg [62-`EFF_IFAR_WIDTH:61] uc_ib_ifar1; + output reg [0:3] uc_ib_ext0; //RT, S1, S2, S3 + output reg [0:3] uc_ib_ext1; //RT, S1, S2, S3 + + //@@ Signal Declarations + wire [1:78] get_address_pt; + wire force_ep; + wire fxm_type; + wire late_end; + wire [0:9] start_addr; + wire uc_legal; + wire xer_type; + + parameter ucode_width = 72; + parameter uc_ifar = 20; + + parameter iu3_val_offset = 0; + parameter iu3_ifar_offset = iu3_val_offset + 4; + parameter iu3_2ucode_offset = iu3_ifar_offset + `EFF_IFAR_WIDTH; + parameter iu3_2ucode_type_offset = iu3_2ucode_offset + 1; + parameter iu3_instr_offset = iu3_2ucode_type_offset + 1; + parameter iu_flush_offset = iu3_instr_offset + 136; + parameter br_hold_offset = iu_flush_offset + 1; + parameter flush_into_uc_offset = br_hold_offset + 1; + parameter np1_flush_offset = flush_into_uc_offset + 1; + parameter flush_ifar_offset = np1_flush_offset + 1; + parameter cp_flush_offset = flush_ifar_offset + 19; + parameter br_iu_redirect_offset = cp_flush_offset + 1; + parameter iu_pc_err_ucode_illegal_offset = br_iu_redirect_offset + 1; + parameter advance_buffers_offset = iu_pc_err_ucode_illegal_offset + 1; + parameter romvalid_offset = advance_buffers_offset + 1; + parameter rom_data_even_late_offset = romvalid_offset + 1; + parameter rom_data_odd_late_offset = rom_data_even_late_offset + 32; + parameter iu4_valid_offset = rom_data_odd_late_offset + 32; + parameter iu4_ifar_offset = iu4_valid_offset + 2; + parameter iu4_ext0_offset = iu4_ifar_offset + uc_ifar; + parameter iu4_ext1_offset = iu4_ext0_offset + 4; + parameter iu4_done_offset = iu4_ext1_offset + 4; + parameter iu4_ov_valid_offset = iu4_done_offset + 1; + parameter iu4_ov_ifar_offset = iu4_ov_valid_offset + 2; + parameter iu4_ov_instr0_offset = iu4_ov_ifar_offset + uc_ifar; + parameter iu4_ov_instr1_offset = iu4_ov_instr0_offset + 32; + parameter iu4_ov_ext0_offset = iu4_ov_instr1_offset + 32; + parameter iu4_ov_ext1_offset = iu4_ov_ext0_offset + 4; + parameter iu4_ov_done_offset = iu4_ov_ext1_offset + 4; + parameter scan_right = iu4_ov_done_offset + 1 - 1; + + // Latches + wire [0:3] iu3_val_d; + wire [62-`EFF_IFAR_WIDTH:61] iu3_ifar_d; + wire iu3_2ucode_d; + wire iu3_2ucode_type_d; + wire [0:33] iu3_0_instr_d; + wire [0:33] iu3_1_instr_d; + wire [0:33] iu3_2_instr_d; + wire [0:33] iu3_3_instr_d; + wire [0:3] iu3_val_l2; + wire [62-`EFF_IFAR_WIDTH:61] iu3_ifar_l2; + wire iu3_2ucode_l2; + wire iu3_2ucode_type_l2; + wire [0:33] iu3_0_instr_l2; + wire [0:33] iu3_1_instr_l2; + wire [0:33] iu3_2_instr_l2; + wire [0:33] iu3_3_instr_l2; + + wire iu_pc_err_ucode_illegal_d; + wire iu_pc_err_ucode_illegal_l2; + wire cp_flush_d; + wire cp_flush_l2; + wire br_iu_redirect_d; + wire br_iu_redirect_l2; + wire advance_buffers_d; + wire advance_buffers_l2; + wire romvalid_d; + wire romvalid_l2; + wire iu_flush_d; + wire iu_flush_l2; + wire br_hold_d; + wire br_hold_l2; + wire flush_into_uc_d; + wire flush_into_uc_l2; + wire np1_flush_d; + wire np1_flush_l2; + wire [43:61] flush_ifar_d; + wire [43:61] flush_ifar_l2; + + reg [0:1] iu4_valid_d; + wire [62-uc_ifar:61] iu4_ifar_d; + wire [0:3] iu4_ext0_d; //RT, S1, S2, S3 + wire [0:3] iu4_ext1_d; + wire iu4_done_d; + wire [0:1] iu4_valid_l2; + wire [62-uc_ifar:61] iu4_ifar_l2; + wire [0:31] iu4_instr0_l2; + wire [0:31] iu4_instr1_l2; + wire [0:3] iu4_ext0_l2; + wire [0:3] iu4_ext1_l2; + wire iu4_done_l2; + + reg [0:1] iu4_ov_valid_d; + wire [62-uc_ifar:61] iu4_ov_ifar_d; + wire [0:31] iu4_ov_instr0_d; + wire [0:31] iu4_ov_instr1_d; + wire [0:3] iu4_ov_ext0_d; + wire [0:3] iu4_ov_ext1_d; + wire iu4_ov_done_d; + wire [0:1] iu4_ov_valid_l2; + wire [62-uc_ifar:61] iu4_ov_ifar_l2; + wire [0:31] iu4_ov_instr0_l2; + wire [0:31] iu4_ov_instr1_l2; + wire [0:3] iu4_ov_ext0_l2; + wire [0:3] iu4_ov_ext1_l2; + wire iu4_ov_done_l2; + + wire uc_val; + wire uc_end; + wire cplbuffer_full; + wire clear_ill_flush_2ucode; + wire next_valid; + wire [0:31] next_instr; + wire iu2_flush; + wire flush_next; + wire flush_next_control; + wire flush_current; + wire uc_iu4_flush_int; + + wire uc_default_act; + wire uc_stall; + wire new_command; + wire msr_64bit; + wire early_end; + wire new_cond; + + wire [0:8] rom_ra; + wire [62-uc_ifar:61] ucode_ifar; + wire [0:31] ucode_instr_even; + wire [0:31] ucode_instr_odd; + wire [0:3] ucode_ext_even; + wire [0:3] ucode_ext_odd; + wire [0:1] ucode_valid; + + wire rom_act; + wire [0:9] rom_addr_even; + wire [0:9] rom_addr_odd; + wire iu4_stall; + wire data_valid; + wire [0:ucode_width-1] rom_data_even; + wire [0:ucode_width-1] rom_data_odd; + + wire [0:31] rom_data_even_late_d; + wire [0:31] rom_data_even_late_l2; + wire [0:31] rom_data_odd_late_d; + wire [0:31] rom_data_odd_late_l2; + + wire ra_valid; + + wire iu4_stage_act; + wire iu4_ov_stage_act; + reg [62-uc_ifar:61] iu4_ifar_out; + + wire pc_iu_func_sl_thold_1; + wire pc_iu_func_sl_thold_0; + wire pc_iu_func_sl_thold_0_b; + wire pc_iu_sg_1; + wire pc_iu_sg_0; + wire force_t; + + wire xu_iu_flush; + + wire [0:scan_right+4] siv; + wire [0:scan_right+4] sov; + + wire tidn; + wire tiup; + + assign tidn = 1'b0; + assign tiup = 1'b1; + + //--------------------------------------------------------------------- + // latch inputs + //--------------------------------------------------------------------- + assign iu3_val_d = {4{(~iu2_flush) & (~xu_iu_flush) & (~ic_bp_iu2_error)}} & ic_bp_iu2_val; + assign iu3_ifar_d = ic_bp_iu2_ifar; + assign iu3_2ucode_d = ic_bp_iu2_2ucode & ic_bp_iu2_val[0]; + assign iu3_2ucode_type_d = ic_bp_iu2_2ucode_type & ic_bp_iu2_val[0]; + assign iu3_0_instr_d = ic_bp_iu2_0_instr; + assign iu3_1_instr_d = ic_bp_iu2_1_instr; + assign iu3_2_instr_d = ic_bp_iu2_2_instr; + assign iu3_3_instr_d = ic_bp_iu2_3_instr; + + //--------------------------------------------------------------------- + // buffers + //--------------------------------------------------------------------- + + iuq_uc_buffer iuq_uc_buffer0( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .pc_iu_func_sl_thold_0_b(pc_iu_func_sl_thold_0_b), + .pc_iu_sg_0(pc_iu_sg_0), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scan_in(siv[scan_right + 4]), + .scan_out(sov[scan_right + 4]), + .iu3_val_l2(iu3_val_l2), + .iu3_ifar_l2(iu3_ifar_l2), + .iu3_2ucode_l2(iu3_2ucode_l2), + .iu3_0_instr_l2(iu3_0_instr_l2), + .iu3_1_instr_l2(iu3_1_instr_l2), + .iu3_2_instr_l2(iu3_2_instr_l2), + .iu3_3_instr_l2(iu3_3_instr_l2), + .ic_bp_iu2_flush(ic_bp_iu2_flush), + .ic_bp_iu3_flush(ic_bp_iu3_flush), + .ic_bp_iu3_ecc_err(ic_bp_iu3_ecc_err), + .bp_ib_iu3_val(bp_ib_iu3_val), + .uc_ib_iu3_invalid(uc_ib_iu3_invalid), + .uc_ib_iu3_flush_all(uc_ib_iu3_flush_all), + .uc_ic_hold(uc_ic_hold), + .uc_iu4_flush(uc_iu4_flush_int), + .uc_iu4_flush_ifar(uc_iu4_flush_ifar), + .xu_iu_flush(xu_iu_flush), + .uc_val(uc_val), + .advance_buffers(advance_buffers_l2), + .br_hold_l2(br_hold_l2), + .cplbuffer_full(cplbuffer_full), + .clear_ill_flush_2ucode(clear_ill_flush_2ucode), + .next_valid(next_valid), + .next_instr(next_instr), + .iu2_flush(iu2_flush), + .flush_next(flush_next), + .flush_current(flush_current) + ); + + assign uc_iu4_flush = uc_iu4_flush_int; + + //--------------------------------------------------------------------- + // new command + //--------------------------------------------------------------------- + assign uc_default_act = flush_into_uc_l2 | next_valid | uc_val | iu4_valid_l2[0] | iu4_ov_valid_l2[0]; + + // stall if same command in buffer0 next cycle + assign uc_stall = (uc_val & (~uc_end)) | + br_hold_l2 | cplbuffer_full; // we need this line if we use new_command to increment cplbuffer (br_hold_l2 prevents underwrap, cplbuffer_full prevents overflow) + + + assign new_command = next_valid & (~uc_stall); // Check that it can receive next command + + assign advance_buffers_d = new_command & uc_val; + + assign msr_64bit = tidn; // Unused + + // output + assign early_end = (~late_end); + + // If '1', will skip lines with skip_cond bit set + assign new_cond = (~iu3_2ucode_type_l2); + + //--------------------------------------------------------------------- + // look up address + //--------------------------------------------------------------------- + +/* +//table_start +?TABLE get_address LISTING(final) OPTIMIZE PARMS(ON-SET, DC-SET); +*INPUTS*============================================*OUTPUTS*====================* +| | | +| next_instr | start_addr | +| | next_instr | | | +| | | iu3_2ucode_l2 | | xer_type | +| | | | iu3_2ucode_type_l2 | | | late_end | # For update form, etc. +| | | | | msr_64bit | | | | force_ep | +| | | | | | | | | | | fxm_type | +| | | | | | | | | | | | uc_legal| +| | 22222222233 | | | | | | | | | | | +| 012345 12345678901 | | | | 0123456789 | | | | | | +*TYPE*==============================================+============================+ +| PPPPPP PPPPPPPPPPP P P P | SSSSSSSSSS S S S S S | +*TERMS*=============================================+============================+ +| 101000 ........... . . . | 0000000000 0 0 0 0 1 | lhz # Flushed 2ucode +| 011111 0100010111. . . . | 0000010000 0 0 0 0 1 | lhzx +| 011111 0100011111. . . . | 0000010000 0 0 1 0 1 | lhepx +| 101010 ........... . . . | 0000100000 0 0 0 0 1 | lha +| 011111 0101010111. . . . | 0000110000 0 0 0 0 1 | lhax +| 100000 ........... . . . | 0001000000 0 0 0 0 1 | lwz +| 011111 0000010111. . . . | 0001010000 0 0 0 0 1 | lwzx +| 011111 0000011111. . . . | 0001010000 0 0 1 0 1 | lwepx +| 111010 .........10 . . . | 0001100000 0 1 0 0 1 | lwa +| 011111 0101010101. . . . | 0001110000 0 0 0 0 1 | lwax +| 111010 .........00 . . . | 0010000000 0 0 0 0 1 | ld +| 011111 0000010101. . . . | 0010010000 0 0 0 0 1 | ldx +| 011111 0000011101. . . . | 0010010000 0 0 1 0 1 | ldepx + +| 101100 ........... . . . | 0100000000 0 0 0 0 1 | sth +| 011111 0110010111. . . . | 0100010000 0 0 0 0 1 | sthx +| 011111 0110011111. . . . | 0100010000 0 0 1 0 1 | sthepx +| 101101 ........... . . . | 0100000000 0 1 0 0 1 | sthu +| 011111 0110110111. . . . | 0100010000 0 1 0 0 1 | sthux +| 100100 ........... . . . | 0101000000 0 0 0 0 1 | stw +| 011111 0010010111. . . . | 0101010000 0 0 0 0 1 | stwx +| 011111 0010011111. . . . | 0101010000 0 0 1 0 1 | stwepx +| 100101 ........... . . . | 0101000000 0 1 0 0 1 | stwu +| 011111 0010110111. . . . | 0101010000 0 1 0 0 1 | stwux +| 111110 .........00 . . . | 0110000000 0 0 0 0 1 | std +| 011111 0010010101. . . . | 0110010000 0 0 0 0 1 | stdx +| 011111 0010011101. . . . | 0110010000 0 0 1 0 1 | stdepx +| 111110 .........01 . . . | 0110000000 0 1 0 0 1 | stdu +| 011111 0010110101. . . . | 0110010000 0 1 0 0 1 | stdux +| 011111 1100010110. . . . | 0000010000 0 0 0 0 1 | lhbrx +| 011111 1000010110. . . . | 0001010000 0 0 0 0 1 | lwbrx +| 011111 1000010100. . . . | 0010010000 0 0 0 0 1 | ldbrx +| 011111 1110010110. . . . | 0100010000 0 0 0 0 1 | sthbrx +| 011111 1010010110. . . . | 0101010000 0 0 0 0 1 | stwbrx +| 011111 1010010100. . . . | 0110010000 0 0 0 0 1 | stdbrx +| | | +| 011111 1000000000. . . . | 0101100000 0 1 0 0 1 | mcrxr +| 011111 0000010011. . . . | 0101110000 0 1 0 0 1 | mfcr +| 011111 0010010000. . . . | 0111110000 0 1 0 1 1 | mtcrf +| 011111 0010010000. . . . | 0111110000 0 1 0 1 1 | mtocrf # Flushed 2ucode +| | | +| 101001 ........... 1 . . | 0000000000 0 1 0 0 1 | lhzu # Flushed 2ucode +| 011111 0100110111. 1 . . | 0000010000 0 1 0 0 1 | lhzux +| 101011 ........... 1 . . | 0000100000 0 1 0 0 1 | lhau +| 011111 0101110111. 1 . . | 0000110000 0 1 0 0 1 | lhaux +| 100001 ........... 1 . . | 0001000000 0 1 0 0 1 | lwzu +| 011111 0000110111. 1 . . | 0001010000 0 1 0 0 1 | lwzux +| 011111 0101110101. 1 . . | 0001110000 0 1 0 0 1 | lwaux +| 111010 .........01 1 . . | 0010000000 0 1 0 0 1 | ldu +| 011111 0000110101. 1 . . | 0010010000 0 1 0 0 1 | ldux +| | | +| 100011 ........... . . . | 1010100000 0 1 0 0 1 | lbzu # Aligned +| 011111 0001110111. . . . | 1010101000 0 1 0 0 1 | lbzux +| 101001 ........... 0 . . | 1010110000 0 1 0 0 1 | lhzu +| 011111 0100110111. 0 . . | 1010111000 0 1 0 0 1 | lhzux +| 101011 ........... 0 . . | 1011100000 0 1 0 0 1 | lhau +| 011111 0101110111. 0 . . | 1011101000 0 1 0 0 1 | lhaux +| 100001 ........... 0 . . | 1011000000 0 1 0 0 1 | lwzu +| 011111 0000110111. 0 . . | 1011001000 0 1 0 0 1 | lwzux +| 011111 0101110101. 0 . . | 1011111000 0 1 0 0 1 | lwaux +| 111010 .........01 0 . . | 1011010000 0 1 0 0 1 | ldu +| 011111 0000110101. 0 . . | 1011011000 0 1 0 0 1 | ldux +| 101110 ........... . . . | 0010100000 0 1 0 0 1 | lmw +| 011111 1001010101. . . . | 0010110000 0 1 0 0 1 | lswi +| 011111 1000010101. . . . | 0011010000 1 1 0 0 1 | lswx +| 101111 ........... . . . | 0110100000 0 1 0 0 1 | stmw +| 011111 1011010101. . . . | 0110110000 0 1 0 0 1 | stswi +| 011111 1010010101. . . . | 0111010000 1 1 0 0 1 | stswx +| | | +| 110001 ........... 0 . . | 1111000000 0 1 0 0 1 | lfsu # Aligned +| 011111 1000110111. 0 . . | 1111001000 0 1 0 0 1 | lfsux +| 110011 ........... 0 . . | 1111010000 0 1 0 0 1 | lfdu +| 011111 1001110111. 0 . . | 1111011000 0 1 0 0 1 | lfdux +| | | +| 011111 1101010111. . . . | 1000110000 0 1 0 0 1 | lfiwax # Flushed 2ucode +| 011111 1101110111. . . . | 1001110000 0 1 0 0 1 | lfiwzx +| 110000 ........... . . . | 1001000000 0 0 0 0 1 | lfs +| 011111 1000010111. . . . | 1001010000 0 0 0 0 1 | lfsx +| 110001 ........... 1 . . | 1001000000 0 1 0 0 1 | lfsu +| 011111 1000110111. 1 . . | 1001010000 0 1 0 0 1 | lfsux +| 110010 ........... . . . | 1010000000 0 0 0 0 1 | lfd +| 011111 1001010111. . . . | 1010010000 0 0 0 0 1 | lfdx +| 011111 1001011111. . . . | 1010010000 0 0 1 0 1 | lfdepx +| 110011 ........... 1 . . | 1010000000 0 1 0 0 1 | lfdu +| 011111 1001110111. 1 . . | 1010010000 0 1 0 0 1 | lfdux +| | | +| 011111 1111010111. . . . | 1100110000 0 1 0 0 1 | stfiwx +| 110100 ........... . . . | 1101000000 0 0 0 0 1 | stfs +| 011111 1010010111. . . . | 1101010000 0 0 0 0 1 | stfsx +| 110101 ........... . . . | 1101000000 0 1 0 0 1 | stfsu +| 011111 1010110111. . . . | 1101010000 0 1 0 0 1 | stfsux +| 110110 ........... . . . | 1110000000 0 0 0 0 1 | stfd +| 011111 1011010111. . . . | 1110010000 0 0 0 0 1 | stfdx +| 011111 1011011111. . . . | 1110010000 0 0 1 0 1 | stfdepx +| 110111 ........... . . . | 1110000000 0 1 0 0 1 | stfdu +| 011111 1011110111. . . . | 1110010000 0 1 0 0 1 | stfdux +| | | +| 000100 .....10101. . . . | 1100000000 0 1 0 0 1 | qvfadd +| 000000 .....10101. . . . | 1100000000 0 1 0 0 1 | qvfadds +| 000100 .....10100. . . . | 1100000000 0 1 0 0 1 | qvfsub +| 000000 .....10100. . . . | 1100000000 0 1 0 0 1 | qvfsubs +| 000100 .....11000. . . . | 1100000000 0 1 0 0 1 | qvfre +| 000000 .....11000. . . . | 1100000000 0 1 0 0 1 | qvfres +| 000100 .....11010. . . . | 1100000000 0 1 0 0 1 | frsqrte +| 000000 .....11010. . . . | 1100000000 0 1 0 0 1 | frsqrtes +| 000100 .....11101. . . . | 1100000000 0 1 0 0 1 | qvfmadd +| 000000 .....11101. . . . | 1100000000 0 1 0 0 1 | qvfmadds +| 000100 .....11100. . . . | 1100000000 0 1 0 0 1 | qvfmsub +| 000000 .....11100. . . . | 1100000000 0 1 0 0 1 | qvfmsubs +| 000100 .....11111. . . . | 1100000000 0 1 0 0 1 | qvfnmadd +| 000000 .....11111. . . . | 1100000000 0 1 0 0 1 | qvfnmadds +| 000100 .....11110. . . . | 1100000000 0 1 0 0 1 | qvfnmsub +| 000000 .....11110. . . . | 1100000000 0 1 0 0 1 | qvfnmsubs +| 000100 .....01001. . . . | 1100000000 0 1 0 0 1 | qvfxmadd +| 000000 .....01001. . . . | 1100000000 0 1 0 0 1 | qvfxmadds +| 000100 .....01011. . . . | 1100000000 0 1 0 0 1 | qvfxxnpmadd +| 000000 .....01011. . . . | 1100000000 0 1 0 0 1 | qvfxxnpmadds +| 000100 .....00011. . . . | 1100000000 0 1 0 0 1 | qvfxxcpnmadd +| 000000 .....00011. . . . | 1100000000 0 1 0 0 1 | qvfxxcpnmadds +| 000100 .....00001. . . . | 1100000000 0 1 0 0 1 | qvfxxmadd +| 000000 .....00001. . . . | 1100000000 0 1 0 0 1 | qvfxxmadds +| 000100 1101001110. . . . | 1100010000 0 1 0 0 1 | qvfcfid - SP prenorm only +| | | +| 111111 .....10101. . . . | 1100000000 0 1 0 0 1 | fadd +| 111011 .....10101. . . . | 1100000000 0 1 0 0 1 | fadds +| 111111 0000100000. . . . | 1100000000 0 1 0 0 1 | fcmpo +| 111111 0000000000. . . . | 1100000000 0 1 0 0 1 | fcmpu +| 111111 .....10010. . . . | 1100001000 0 1 0 0 1 | fdiv +| 111011 .....10010. . . . | 1100001000 0 1 0 0 1 | fdivs +| 111111 .....11101. . . . | 1100000000 0 1 0 0 1 | fmadd +| 111011 .....11101. . . . | 1100000000 0 1 0 0 1 | fmadds +| 111111 .....11100. . . . | 1100000000 0 1 0 0 1 | fmsub +| 111011 .....11100. . . . | 1100000000 0 1 0 0 1 | fmsubs +| 111111 .....11111. . . . | 1100000000 0 1 0 0 1 | fnmadd +| 111011 .....11111. . . . | 1100000000 0 1 0 0 1 | fnmadds +| 111111 .....11110. . . . | 1100000000 0 1 0 0 1 | fnmsub +| 111011 .....11110. . . . | 1100000000 0 1 0 0 1 | fnmsubs +| 111111 .....11000. . . . | 1100000000 0 1 0 0 1 | fre +| 111011 .....11000. . . . | 1100000000 0 1 0 0 1 | fres +| 111111 1101001110. . . . | 1100000000 0 1 0 0 1 | fcfid +| 111111 1111001110. . . . | 1100000000 0 1 0 0 1 | fcfidu +| 111011 1101001110. . . . | 1100000000 0 1 0 0 1 | fcfids +| 111011 1111001110. . . . | 1100000000 0 1 0 0 1 | fcfidus +| 111111 .....11010. . . . | 1100000000 0 1 0 0 1 | frsqrte +| 111011 .....11010. . . . | 1100000000 0 1 0 0 1 | frsqrtes +| 111111 .....10100. . . . | 1100000000 0 1 0 0 1 | fsub +| 111011 .....10100. . . . | 1100000000 0 1 0 0 1 | fsubs +| 111111 .....10110. . . . | 1100000000 0 1 0 0 1 | fsqrt +| 111011 .....10110. . . . | 1100000000 0 1 0 0 1 | fsqrts +| 111111 0010000000. . . . | 1100001000 0 1 0 0 1 | ftdiv +| 111111 0010100000. . . . | 1100000000 0 1 0 0 1 | ftsqrt +| 111111 1011000111. . . . | 1100000000 0 1 0 0 1 | mtfsf +*END*===============================================+============================+ +?TABLE END get_address ; +//table_end +*/ + +//assign_start + +assign get_address_pt[1] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] , next_instr[5] , + next_instr[21] , next_instr[22] , + next_instr[23] , next_instr[24] , + next_instr[25] , next_instr[26] , + next_instr[27] , next_instr[28] , + next_instr[29] , next_instr[30] + }) === 16'b0001001101001110); +assign get_address_pt[2] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] , next_instr[5] , + next_instr[21] , next_instr[22] , + next_instr[23] , next_instr[24] , + next_instr[25] , next_instr[26] , + next_instr[27] , next_instr[28] , + next_instr[29] , next_instr[30] + }) === 16'b1111110010000000); +assign get_address_pt[3] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] , next_instr[5] , + next_instr[21] , next_instr[22] , + next_instr[23] , next_instr[24] , + next_instr[25] , next_instr[26] , + next_instr[27] , next_instr[28] , + next_instr[29] , next_instr[30] + }) === 16'b0111111000000000); +assign get_address_pt[4] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] , next_instr[5] , + next_instr[21] , next_instr[22] , + next_instr[24] , next_instr[25] , + next_instr[26] , next_instr[27] , + next_instr[28] , next_instr[29] , + next_instr[30] }) === 15'b011111101011111); +assign get_address_pt[5] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] , next_instr[5] , + next_instr[21] , next_instr[22] , + next_instr[23] , next_instr[24] , + next_instr[25] , next_instr[26] , + next_instr[27] , next_instr[28] , + next_instr[30] , iu3_2ucode_l2 + }) === 16'b0111110000110110); +assign get_address_pt[6] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] , next_instr[5] , + next_instr[21] , next_instr[22] , + next_instr[23] , next_instr[25] , + next_instr[26] , next_instr[27] , + next_instr[28] , next_instr[29] , + next_instr[30] , iu3_2ucode_l2 + }) === 16'b0111111001101110); +assign get_address_pt[7] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] , next_instr[5] , + next_instr[21] , next_instr[22] , + next_instr[23] , next_instr[24] , + next_instr[25] , next_instr[26] , + next_instr[27] , next_instr[28] , + next_instr[30] , iu3_2ucode_l2 + }) === 16'b0111110101110111); +assign get_address_pt[8] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] , next_instr[5] , + next_instr[21] , next_instr[22] , + next_instr[23] , next_instr[24] , + next_instr[26] , next_instr[27] , + next_instr[28] , next_instr[29] , + next_instr[30] }) === 15'b011111010110101); +assign get_address_pt[9] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] , next_instr[5] , + next_instr[21] , next_instr[22] , + next_instr[23] , next_instr[24] , + next_instr[25] , next_instr[26] , + next_instr[27] , next_instr[28] , + next_instr[29] , next_instr[30] , + iu3_2ucode_l2 }) === 17'b01111101001101110); +assign get_address_pt[10] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] , next_instr[5] , + next_instr[21] , next_instr[22] , + next_instr[23] , next_instr[24] , + next_instr[25] , next_instr[26] , + next_instr[28] , next_instr[29] , + next_instr[30] }) === 15'b011111101101111); +assign get_address_pt[11] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] , next_instr[5] , + next_instr[21] , next_instr[23] , + next_instr[24] , next_instr[25] , + next_instr[26] , next_instr[27] , + next_instr[28] , next_instr[29] , + next_instr[30] }) === 15'b011111111010111); +assign get_address_pt[12] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] , next_instr[5] , + next_instr[21] , next_instr[24] , + next_instr[25] , next_instr[26] , + next_instr[27] , next_instr[28] , + next_instr[29] , next_instr[30] + }) === 14'b01111100011111); +assign get_address_pt[13] = + (({ next_instr[0] , next_instr[1] , + next_instr[3] , next_instr[4] , + next_instr[5] , next_instr[21] , + next_instr[22] , next_instr[23] , + next_instr[24] , next_instr[25] , + next_instr[26] , next_instr[27] , + next_instr[28] , next_instr[29] , + next_instr[30] }) === 15'b111111011000111); +assign get_address_pt[14] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] , next_instr[5] , + next_instr[21] , next_instr[22] , + next_instr[24] , next_instr[25] , + next_instr[26] , next_instr[27] , + next_instr[28] , next_instr[30] + }) === 14'b01111100001111); +assign get_address_pt[15] = + (({ next_instr[1] , next_instr[2] , + next_instr[3] , next_instr[4] , + next_instr[5] , next_instr[21] , + next_instr[23] , next_instr[24] , + next_instr[25] , next_instr[26] , + next_instr[27] , next_instr[28] , + next_instr[29] , next_instr[30] + }) === 14'b11111110010110); +assign get_address_pt[16] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] , next_instr[5] , + next_instr[21] , next_instr[22] , + next_instr[23] , next_instr[24] , + next_instr[25] , next_instr[26] , + next_instr[27] , next_instr[28] , + next_instr[30] , iu3_2ucode_l2 + }) === 16'b0111110101110110); +assign get_address_pt[17] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] , next_instr[5] , + next_instr[21] , next_instr[22] , + next_instr[23] , next_instr[24] , + next_instr[25] , next_instr[26] , + next_instr[27] , next_instr[28] , + next_instr[30] }) === 15'b011111010101011); +assign get_address_pt[18] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] , next_instr[5] , + next_instr[21] , next_instr[22] , + next_instr[24] , next_instr[25] , + next_instr[26] , next_instr[27] , + next_instr[28] , next_instr[29] , + next_instr[30] }) === 15'b011111100010101); +assign get_address_pt[19] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] , next_instr[5] , + next_instr[21] , next_instr[22] , + next_instr[23] , next_instr[24] , + next_instr[25] , next_instr[26] , + next_instr[27] , next_instr[28] , + next_instr[29] , next_instr[30] + }) === 16'b0111110010010000); +assign get_address_pt[20] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] , next_instr[5] , + next_instr[21] , next_instr[22] , + next_instr[23] , next_instr[24] , + next_instr[25] , next_instr[26] , + next_instr[27] , next_instr[28] , + next_instr[29] , next_instr[30] + }) === 16'b0111111101110111); +assign get_address_pt[21] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] , next_instr[5] , + next_instr[21] , next_instr[22] , + next_instr[23] , next_instr[24] , + next_instr[25] , next_instr[26] , + next_instr[27] , next_instr[28] , + next_instr[29] , next_instr[30] + }) === 16'b0111110001110111); +assign get_address_pt[22] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] , next_instr[5] , + next_instr[21] , next_instr[22] , + next_instr[24] , next_instr[25] , + next_instr[26] , next_instr[27] , + next_instr[28] , next_instr[29] , + next_instr[30] }) === 15'b011111101110111); +assign get_address_pt[23] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] , next_instr[5] , + next_instr[22] , next_instr[24] , + next_instr[26] , next_instr[27] , + next_instr[28] , next_instr[29] , + next_instr[30] , iu3_2ucode_l2 + }) === 14'b01111100101111); +assign get_address_pt[24] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] , next_instr[5] , + next_instr[21] , next_instr[22] , + next_instr[23] , next_instr[24] , + next_instr[25] , next_instr[26] , + next_instr[27] , next_instr[28] + }) === 14'b01111110100101); +assign get_address_pt[25] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] , next_instr[5] , + next_instr[21] , next_instr[23] , + next_instr[24] , next_instr[25] , + next_instr[26] , next_instr[28] , + next_instr[29] , next_instr[30] + }) === 14'b01111101001111); +assign get_address_pt[26] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] , next_instr[5] , + next_instr[21] , next_instr[24] , + next_instr[25] , next_instr[26] , + next_instr[27] , next_instr[28] , + next_instr[29] , next_instr[30] , + iu3_2ucode_l2 }) === 15'b011111001101111); +assign get_address_pt[27] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] , next_instr[5] , + next_instr[21] , next_instr[22] , + next_instr[23] , next_instr[24] , + next_instr[25] , next_instr[26] , + next_instr[28] , next_instr[30] + }) === 14'b01111100100111); +assign get_address_pt[28] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] , next_instr[5] , + next_instr[21] , next_instr[22] , + next_instr[24] , next_instr[25] , + next_instr[26] , next_instr[28] , + next_instr[29] , next_instr[30] + }) === 14'b01111100001111); +assign get_address_pt[29] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] , next_instr[5] , + next_instr[21] , next_instr[22] , + next_instr[23] , next_instr[24] , + next_instr[25] , next_instr[26] , + next_instr[27] , next_instr[28] , + next_instr[29] , next_instr[30] + }) === 16'b0111110000010011); +assign get_address_pt[30] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] , next_instr[5] , + next_instr[21] , next_instr[22] , + next_instr[23] , next_instr[24] , + next_instr[26] , next_instr[27] , + next_instr[28] , next_instr[30] + }) === 14'b01111100101011); +assign get_address_pt[31] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] , next_instr[5] , + next_instr[21] , next_instr[22] , + next_instr[23] , next_instr[25] , + next_instr[26] , next_instr[27] , + next_instr[28] , next_instr[30] + }) === 14'b01111110101011); +assign get_address_pt[32] = + (({ next_instr[0] , next_instr[1] , + next_instr[3] , next_instr[4] , + next_instr[5] , next_instr[21] , + next_instr[22] , next_instr[24] , + next_instr[26] , next_instr[27] , + next_instr[28] , next_instr[29] , + next_instr[30] }) === 13'b1111100000000); +assign get_address_pt[33] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] , next_instr[5] , + next_instr[21] , next_instr[22] , + next_instr[24] , next_instr[25] , + next_instr[26] , next_instr[27] , + next_instr[28] , next_instr[29] + }) === 14'b01111110001011); +assign get_address_pt[34] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] , next_instr[5] , + next_instr[21] , next_instr[22] , + next_instr[24] , next_instr[25] , + next_instr[26] , next_instr[27] , + next_instr[28] , next_instr[29] , + next_instr[30] }) === 15'b011111000110101); +assign get_address_pt[35] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] , next_instr[5] , + next_instr[21] , next_instr[24] , + next_instr[25] , next_instr[26] , + next_instr[27] , next_instr[28] , + next_instr[29] , next_instr[30] + }) === 14'b01111110010110); +assign get_address_pt[36] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] , next_instr[5] , + next_instr[21] , next_instr[22] , + next_instr[23] , next_instr[26] , + next_instr[27] , next_instr[28] , + next_instr[29] , next_instr[30] + }) === 14'b01111110110111); +assign get_address_pt[37] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] , next_instr[5] , + next_instr[21] , next_instr[23] , + next_instr[24] , next_instr[25] , + next_instr[26] , next_instr[27] , + next_instr[28] , next_instr[29] , + next_instr[30] }) === 15'b011111010110111); +assign get_address_pt[38] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[4] , + next_instr[5] , next_instr[21] , + next_instr[22] , next_instr[24] , + next_instr[25] , next_instr[27] , + next_instr[28] , next_instr[29] , + next_instr[30] }) === 13'b1111111101110); +assign get_address_pt[39] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] , next_instr[5] , + next_instr[21] , next_instr[22] , + next_instr[24] , next_instr[25] , + next_instr[26] , next_instr[27] , + next_instr[28] , next_instr[29] + }) === 14'b01111110001010); +assign get_address_pt[40] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] , next_instr[5] , + next_instr[21] , next_instr[22] , + next_instr[24] , next_instr[25] , + next_instr[26] , next_instr[27] , + next_instr[28] , next_instr[29] , + next_instr[30] }) === 15'b011111101010101); +assign get_address_pt[41] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] , next_instr[5] , + next_instr[21] , next_instr[22] , + next_instr[24] , next_instr[25] , + next_instr[26] , next_instr[28] , + next_instr[29] , next_instr[30] + }) === 14'b01111100001101); +assign get_address_pt[42] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] , next_instr[5] , + next_instr[21] , next_instr[22] , + next_instr[24] , next_instr[25] , + next_instr[26] , next_instr[27] , + next_instr[28] , next_instr[29] , + next_instr[30] }) === 15'b011111111010111); +assign get_address_pt[43] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] , next_instr[5] , + next_instr[22] , next_instr[24] , + next_instr[25] , next_instr[26] , + next_instr[27] , next_instr[28] , + next_instr[29] , next_instr[30] + }) === 14'b01111100110111); +assign get_address_pt[44] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] , next_instr[5] , + next_instr[21] , next_instr[22] , + next_instr[24] , next_instr[25] , + next_instr[26] , next_instr[28] , + next_instr[29] , next_instr[30] + }) === 14'b01111110101111); +assign get_address_pt[45] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] , next_instr[5] , + next_instr[21] , next_instr[24] , + next_instr[25] , next_instr[26] , + next_instr[28] , next_instr[29] , + next_instr[30] }) === 13'b0111110001111); +assign get_address_pt[46] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] , next_instr[5] , + next_instr[30] , next_instr[31] , + iu3_2ucode_l2 }) === 9'b111010010); +assign get_address_pt[47] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] , next_instr[5] , + next_instr[21] , next_instr[22] , + next_instr[26] , next_instr[27] , + next_instr[28] , next_instr[29] , + next_instr[30] }) === 13'b0111111010111); +assign get_address_pt[48] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[4] , + next_instr[5] , next_instr[26] , + next_instr[28] , next_instr[30] + }) === 8'b00000001); +assign get_address_pt[49] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[4] , + next_instr[5] , next_instr[26] , + next_instr[27] , next_instr[30] + }) === 8'b00000110); +assign get_address_pt[50] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[4] , + next_instr[5] , next_instr[26] , + next_instr[27] , next_instr[28] + }) === 8'b00000111); +assign get_address_pt[51] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[4] , + next_instr[5] , next_instr[26] , + next_instr[28] , next_instr[29] + }) === 8'b00000110); +assign get_address_pt[52] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] , next_instr[5] , + iu3_2ucode_l2 }) === 7'b1100110); +assign get_address_pt[53] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[4] , + next_instr[5] , next_instr[30] , + next_instr[31] }) === 7'b1111001); +assign get_address_pt[54] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] , next_instr[5] , + iu3_2ucode_l2 }) === 7'b1010010); +assign get_address_pt[55] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] , next_instr[5] , + next_instr[30] , next_instr[31] + }) === 8'b11101010); +assign get_address_pt[56] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] , next_instr[5] , + iu3_2ucode_l2 }) === 7'b1010110); +assign get_address_pt[57] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[4] , + next_instr[5] , next_instr[26] , + next_instr[27] , next_instr[28] , + next_instr[29] , next_instr[30] + }) === 10'b1111110010); +assign get_address_pt[58] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[5] , iu3_2ucode_l2 + }) === 6'b110010); +assign get_address_pt[59] = + (({ next_instr[0] , next_instr[2] , + next_instr[3] , next_instr[5] , + iu3_2ucode_l2 }) === 5'b10010); +assign get_address_pt[60] = + (({ next_instr[0] , next_instr[1] , + next_instr[3] , next_instr[4] , + next_instr[5] , next_instr[30] + }) === 6'b111100); +assign get_address_pt[61] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] , next_instr[5] + }) === 6'b100011); +assign get_address_pt[62] = + (({ next_instr[0] , next_instr[1] , + next_instr[3] , next_instr[4] + }) === 4'b1010); +assign get_address_pt[63] = + (({ next_instr[0] , next_instr[1] , + next_instr[3] , next_instr[5] + }) === 4'b1001); +assign get_address_pt[64] = + (({ next_instr[0] , next_instr[2] , + next_instr[4] , next_instr[5] + }) === 4'b1001); +assign get_address_pt[65] = + (({ next_instr[0] , next_instr[1] , + next_instr[4] , next_instr[5] , + next_instr[30] }) === 5'b11100); +assign get_address_pt[66] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[4] , + next_instr[5] , next_instr[26] , + next_instr[27] , next_instr[30] + }) === 8'b11111110); +assign get_address_pt[67] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[4] + }) === 4'b1011); +assign get_address_pt[68] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] + }) === 4'b1101); +assign get_address_pt[69] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[4] }) === 5'b10111); +assign get_address_pt[70] = + (({ next_instr[0] , next_instr[2] , + next_instr[4] }) === 3'b100); +assign get_address_pt[71] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[4] , + next_instr[5] , next_instr[26] , + next_instr[27] , next_instr[28] + }) === 8'b11111111); +assign get_address_pt[72] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[4] , + next_instr[5] , next_instr[26] , + next_instr[28] , next_instr[29] + }) === 8'b11111110); +assign get_address_pt[73] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[3] , + next_instr[5] }) === 5'b10111); +assign get_address_pt[74] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[5] + }) === 4'b1101); +assign get_address_pt[75] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[4] , + next_instr[5] , next_instr[26] , + next_instr[28] , next_instr[30] + }) === 8'b11111110); +assign get_address_pt[76] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] }) === 3'b110); +assign get_address_pt[77] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] }) === 3'b101); +assign get_address_pt[78] = + (({ next_instr[0] , next_instr[1] , + next_instr[2] , next_instr[4] + }) === 4'b1101); +assign start_addr[0] = + (get_address_pt[1] | get_address_pt[5] + | get_address_pt[9] | get_address_pt[13] + | get_address_pt[16] | get_address_pt[20] + | get_address_pt[21] | get_address_pt[32] + | get_address_pt[38] | get_address_pt[42] + | get_address_pt[44] | get_address_pt[46] + | get_address_pt[47] | get_address_pt[48] + | get_address_pt[49] | get_address_pt[50] + | get_address_pt[51] | get_address_pt[54] + | get_address_pt[56] | get_address_pt[57] + | get_address_pt[59] | get_address_pt[61] + | get_address_pt[66] | get_address_pt[71] + | get_address_pt[72] | get_address_pt[75] + | get_address_pt[76]); +assign start_addr[1] = + (get_address_pt[1] | get_address_pt[3] + | get_address_pt[6] | get_address_pt[10] + | get_address_pt[11] | get_address_pt[13] + | get_address_pt[15] | get_address_pt[19] + | get_address_pt[24] | get_address_pt[25] + | get_address_pt[27] | get_address_pt[29] + | get_address_pt[30] | get_address_pt[31] + | get_address_pt[32] | get_address_pt[36] + | get_address_pt[37] | get_address_pt[38] + | get_address_pt[48] | get_address_pt[49] + | get_address_pt[50] | get_address_pt[51] + | get_address_pt[57] | get_address_pt[58] + | get_address_pt[60] | get_address_pt[62] + | get_address_pt[66] | get_address_pt[68] + | get_address_pt[71] | get_address_pt[72] + | get_address_pt[73] | get_address_pt[75] + ); +assign start_addr[2] = + (get_address_pt[5] | get_address_pt[6] + | get_address_pt[9] | get_address_pt[16] + | get_address_pt[19] | get_address_pt[21] + | get_address_pt[22] | get_address_pt[34] + | get_address_pt[39] | get_address_pt[40] + | get_address_pt[41] | get_address_pt[44] + | get_address_pt[54] | get_address_pt[56] + | get_address_pt[59] | get_address_pt[61] + | get_address_pt[65] | get_address_pt[69] + | get_address_pt[78]); +assign start_addr[3] = + (get_address_pt[3] | get_address_pt[5] + | get_address_pt[6] | get_address_pt[8] + | get_address_pt[16] | get_address_pt[18] + | get_address_pt[19] | get_address_pt[20] + | get_address_pt[28] | get_address_pt[29] + | get_address_pt[33] | get_address_pt[43] + | get_address_pt[46] | get_address_pt[55] + | get_address_pt[56] | get_address_pt[58] + | get_address_pt[70]); +assign start_addr[4] = + (get_address_pt[3] | get_address_pt[7] + | get_address_pt[9] | get_address_pt[16] + | get_address_pt[17] | get_address_pt[19] + | get_address_pt[20] | get_address_pt[21] + | get_address_pt[29] | get_address_pt[40] + | get_address_pt[42] | get_address_pt[54] + | get_address_pt[55] | get_address_pt[61] + | get_address_pt[67]); +assign start_addr[5] = + (get_address_pt[1] | get_address_pt[7] + | get_address_pt[8] | get_address_pt[9] + | get_address_pt[17] | get_address_pt[19] + | get_address_pt[20] | get_address_pt[22] + | get_address_pt[23] | get_address_pt[26] + | get_address_pt[29] | get_address_pt[33] + | get_address_pt[34] | get_address_pt[35] + | get_address_pt[36] | get_address_pt[37] + | get_address_pt[39] | get_address_pt[40] + | get_address_pt[41] | get_address_pt[42] + | get_address_pt[44] | get_address_pt[45] + | get_address_pt[46] | get_address_pt[52] + | get_address_pt[54]); +assign start_addr[6] = + (get_address_pt[2] | get_address_pt[5] + | get_address_pt[6] | get_address_pt[9] + | get_address_pt[16] | get_address_pt[21] + | get_address_pt[57]); +assign start_addr[7] = + 1'b0; +assign start_addr[8] = + 1'b0; +assign start_addr[9] = + 1'b0; +assign xer_type = + (get_address_pt[18]); +assign late_end = + (get_address_pt[1] | get_address_pt[3] + | get_address_pt[7] | get_address_pt[9] + | get_address_pt[13] | get_address_pt[16] + | get_address_pt[18] | get_address_pt[19] + | get_address_pt[20] | get_address_pt[21] + | get_address_pt[22] | get_address_pt[26] + | get_address_pt[29] | get_address_pt[32] + | get_address_pt[34] | get_address_pt[37] + | get_address_pt[38] | get_address_pt[40] + | get_address_pt[42] | get_address_pt[43] + | get_address_pt[48] | get_address_pt[49] + | get_address_pt[50] | get_address_pt[51] + | get_address_pt[53] | get_address_pt[55] + | get_address_pt[57] | get_address_pt[63] + | get_address_pt[64] | get_address_pt[66] + | get_address_pt[69] | get_address_pt[71] + | get_address_pt[72] | get_address_pt[73] + | get_address_pt[74] | get_address_pt[75] + ); +assign force_ep = + (get_address_pt[4] | get_address_pt[12] + | get_address_pt[14]); +assign fxm_type = + (get_address_pt[19]); +assign uc_legal = + (get_address_pt[1] | get_address_pt[3] + | get_address_pt[7] | get_address_pt[9] + | get_address_pt[13] | get_address_pt[16] + | get_address_pt[17] | get_address_pt[19] + | get_address_pt[20] | get_address_pt[21] + | get_address_pt[26] | get_address_pt[29] + | get_address_pt[32] | get_address_pt[34] + | get_address_pt[35] | get_address_pt[37] + | get_address_pt[38] | get_address_pt[39] + | get_address_pt[40] | get_address_pt[41] + | get_address_pt[42] | get_address_pt[43] + | get_address_pt[44] | get_address_pt[45] + | get_address_pt[47] | get_address_pt[48] + | get_address_pt[49] | get_address_pt[50] + | get_address_pt[51] | get_address_pt[55] + | get_address_pt[57] | get_address_pt[61] + | get_address_pt[65] | get_address_pt[66] + | get_address_pt[70] | get_address_pt[71] + | get_address_pt[72] | get_address_pt[75] + | get_address_pt[77] | get_address_pt[78] + ); + +//assign_end + + //--------------------------------------------------------------------- + // illegal op + //--------------------------------------------------------------------- + + // Need to handle the cmodx case where load/store gets flushed to uCode, + // then that instruction is changed to some non-uCode instruction. + // Solution: Any time an instruction was flushed_2ucode and doesn't hit + // in table, flush instruction to clear flush_2ucode bit. Instruction + // will then re-fetch as regular instruction. + assign clear_ill_flush_2ucode = new_command & (~uc_legal) & iu3_2ucode_l2; + + assign flush_next_control = flush_next | clear_ill_flush_2ucode; + + assign iu_pc_err_ucode_illegal_d = new_command & (~uc_legal) & (~iu3_2ucode_l2) & (~flush_next); + + tri_direct_err_rpt #(.WIDTH(1)) err_ucode_illegal( + .vd(vdd), + .gd(gnd), + .err_in(iu_pc_err_ucode_illegal_l2), + .err_out(iu_pc_err_ucode_illegal) + ); + + //--------------------------------------------------------------------- + // create instruction + //--------------------------------------------------------------------- + assign xu_iu_flush = iu_flush_l2 | br_iu_redirect_l2; + assign iu_flush_d = iu_flush; + assign cp_flush_d = cp_flush; + assign br_iu_redirect_d = br_iu_redirect & (~(cp_flush_l2 | iu_flush_l2)); + + // When br_iu_redirect happens, hold off uCode commands until cp_flush + // otherwise weird things happen + assign br_hold_d = (cp_flush_l2 == 1'b1) ? 1'b0 : + (br_iu_redirect_l2 == 1'b1) ? 1'b1 : + br_hold_l2; + + assign flush_into_uc_d = iu_flush & cp_flush_into_uc; + assign np1_flush_d = cp_uc_np1_flush; + assign flush_ifar_d = cp_uc_flush_ifar; + + iuq_uc_control uc_control( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .pc_iu_func_sl_thold_0_b(pc_iu_func_sl_thold_0_b), + .pc_iu_sg_0(pc_iu_sg_0), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scan_in(siv[scan_right + 1]), + .scan_out(sov[scan_right + 1]), + .xu_iu_ucode_xer_val(xu_iu_ucode_xer_val), + .xu_iu_ucode_xer(xu_iu_ucode_xer), + .br_hold(br_hold_l2), + .flush_next(flush_next_control), + .flush(flush_current), + .flush_into_uc(flush_into_uc_l2), + .np1_flush(np1_flush_l2), + .flush_ifar(flush_ifar_l2), + .cp_uc_credit_free(cp_uc_credit_free), + .cp_flush(cp_flush_l2), + .uc_default_act(uc_default_act), + .next_valid(next_valid), + .new_command(new_command), + .new_instr(next_instr), + .start_addr(start_addr[0:8]), // bit (9) is unused - always even + .xer_type(xer_type), + .early_end(early_end), + .force_ep(force_ep), + .fxm_type(fxm_type), + .new_cond(new_cond), + .ra_valid(ra_valid), + .rom_ra(rom_ra), + .rom_act(rom_act), + .data_valid(data_valid), + .rom_data_even(rom_data_even[32:ucode_width - 1]), + .rom_data_odd(rom_data_odd[32:ucode_width - 1]), + .rom_data_even_late(rom_data_even_late_l2), + .rom_data_odd_late(rom_data_odd_late_l2), + .uc_val(uc_val), + .uc_end(uc_end), + .cplbuffer_full(cplbuffer_full), + .ucode_valid(ucode_valid), + .ucode_ifar_even(ucode_ifar), + .ucode_instr_even(ucode_instr_even), + .ucode_instr_odd(ucode_instr_odd), + .ucode_ext_even(ucode_ext_even), + .ucode_ext_odd(ucode_ext_odd) + ); + + //--------------------------------------------------------------------- + // ROM + //--------------------------------------------------------------------- + + assign romvalid_d = ra_valid; + + assign rom_addr_even = {rom_ra[0:8], 1'b0}; + assign rom_addr_odd = {rom_ra[0:8], 1'b1}; + + assign iu4_stall = iu4_valid_l2[0] & iu4_ov_valid_l2[0]; // ??? Need to check vector if ever switch to only i1 being valid + + assign data_valid = romvalid_l2 & (~iu4_stall); + + //--------------------------------------------------------------------- + // ROM Lookup + //--------------------------------------------------------------------- + + iuq_uc_rom_even uc_rom_even( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .pc_iu_func_sl_thold_0_b(pc_iu_func_sl_thold_0_b), + .pc_iu_sg_0(pc_iu_sg_0), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scan_in(siv[scan_right + 2]), + .scan_out(sov[scan_right + 2]), + .rom_act(rom_act), + .rom_addr(rom_addr_even), + .rom_data(rom_data_even) + ); + assign rom_data_even_late_d = rom_data_even[0:31]; + + iuq_uc_rom_odd uc_rom_odd( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .pc_iu_func_sl_thold_0_b(pc_iu_func_sl_thold_0_b), + .pc_iu_sg_0(pc_iu_sg_0), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scan_in(siv[scan_right + 3]), + .scan_out(sov[scan_right + 3]), + .rom_act(rom_act), + .rom_addr(rom_addr_odd), + .rom_data(rom_data_odd) + ); + assign rom_data_odd_late_d = rom_data_odd[0:31]; + + //--------------------------------------------------------------------- + // Staging latches + //--------------------------------------------------------------------- + assign iu4_stage_act = data_valid; // ??? Removed "not flush and not skip" from act. Do we want to add in some form of skip check? + + generate + begin : xhdl1 + genvar i; + for (i = 0; i <= 1; i = i + 1) + begin : gen_iu4_val + always @(*) iu4_valid_d[i] = ((ucode_valid[i] & (~iu4_stall)) | + (iu4_valid_l2[i] & iu4_stall)) & + (~(iu_flush_l2 | br_iu_redirect_l2)); // clear on flush + end + end + endgenerate + + assign iu4_ifar_d = ucode_ifar; + assign iu4_ext0_d = ucode_ext_even; + assign iu4_ext1_d = ucode_ext_odd; + + //late data + assign iu4_instr0_l2 = ucode_instr_even; + assign iu4_instr1_l2 = ucode_instr_odd; + + assign iu4_done_d = uc_end; + + // Overflow latches + assign iu4_ov_stage_act = iu4_valid_l2[0] & (~iu4_ov_valid_l2[0]); + generate + begin : xhdl2 + genvar i; + for (i = 0; i <= 1; i = i + 1) + begin : gen_ov_valid + always @(*) iu4_ov_valid_d[i] = (iu4_ov_valid_l2[i] | (iu4_valid_l2[i] & (~iu4_ov_valid_l2[0]))) & (~ib_uc_rdy) & (~(iu_flush_l2 | br_iu_redirect_l2)); + end + end + endgenerate + + assign iu4_ov_ifar_d = iu4_ifar_l2; + assign iu4_ov_ext0_d = iu4_ext0_l2; + assign iu4_ov_ext1_d = iu4_ext1_l2; + assign iu4_ov_instr0_d = iu4_instr0_l2; + assign iu4_ov_instr1_d = iu4_instr1_l2; + assign iu4_ov_done_d = iu4_done_l2; + + // If uc_ifar > `EFF_IFAR_WIDTH, we + // need to change uc_control so uc_ifar is not bigger than EFF_IFAR_WIDTH + // so that we don't lose part of ifar on flush + + generate + begin + if (uc_ifar >= `EFF_IFAR_WIDTH) + begin : ifara + always @(*) uc_ib_ifar0 = iu4_ifar_out[62 - `EFF_IFAR_WIDTH:61]; + always @(*) uc_ib_ifar1 = {iu4_ifar_out[62 - `EFF_IFAR_WIDTH:60], 1'b1}; + end + if (uc_ifar < `EFF_IFAR_WIDTH) + begin : ifarb + always @(*) + begin + uc_ib_ifar0[62 - `EFF_IFAR_WIDTH:62 - uc_ifar - 1] = {`EFF_IFAR_WIDTH-uc_ifar{1'b0}}; + uc_ib_ifar1[62 - `EFF_IFAR_WIDTH:62 - uc_ifar - 1] = {`EFF_IFAR_WIDTH-uc_ifar{1'b0}}; + + uc_ib_ifar0[62 - uc_ifar:61] = iu4_ifar_out; + uc_ib_ifar1[62 - uc_ifar:61] = {iu4_ifar_out[62 - uc_ifar:60], 1'b1}; + end + end + end + endgenerate + + always @(iu4_ov_valid_l2 or iu4_ifar_l2 or iu4_instr0_l2 or iu4_instr1_l2 or iu4_valid_l2 or iu4_ext0_l2 or iu4_ext1_l2 or iu4_done_l2 or iu4_ov_ifar_l2 or iu4_ov_instr0_l2 or iu4_ov_instr1_l2 or iu4_ov_ext0_l2 or iu4_ov_ext1_l2 or iu4_ov_done_l2) + begin: ib_proc + uc_ib_val = iu4_valid_l2; + iu4_ifar_out = iu4_ifar_l2; + uc_ib_instr0 = iu4_instr0_l2; + uc_ib_instr1 = iu4_instr1_l2; + uc_ib_ext0 = iu4_ext0_l2; + uc_ib_ext1 = iu4_ext1_l2; + uc_ib_done = iu4_done_l2; + + if (iu4_ov_valid_l2[0] == 1'b1) + begin + uc_ib_val = iu4_ov_valid_l2; + iu4_ifar_out = iu4_ov_ifar_l2; + uc_ib_instr0 = iu4_ov_instr0_l2; + uc_ib_instr1 = iu4_ov_instr1_l2; + uc_ib_ext0 = iu4_ov_ext0_l2; + uc_ib_ext1 = iu4_ov_ext1_l2; + uc_ib_done = iu4_ov_done_l2; + end + end + + //--------------------------------------------------------------------- + // Latches + //--------------------------------------------------------------------- + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) iu3_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu3_val_offset:iu3_val_offset + 4 - 1]), + .scout(sov[iu3_val_offset:iu3_val_offset + 4 - 1]), + .din(iu3_val_d), + .dout(iu3_val_l2) + ); + + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0), .NEEDS_SRESET(0)) iu3_ifar_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ic_bp_iu2_val[0]), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu3_ifar_offset:iu3_ifar_offset + `EFF_IFAR_WIDTH - 1]), + .scout(sov[iu3_ifar_offset:iu3_ifar_offset + `EFF_IFAR_WIDTH - 1]), + .din(iu3_ifar_d), + .dout(iu3_ifar_l2) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(0)) iu3_2ucode_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu3_2ucode_offset]), + .scout(sov[iu3_2ucode_offset]), + .din(iu3_2ucode_d), + .dout(iu3_2ucode_l2) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(0)) iu3_2ucode_type_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu3_2ucode_type_offset]), + .scout(sov[iu3_2ucode_type_offset]), + .din(iu3_2ucode_type_d), + .dout(iu3_2ucode_type_l2) + ); + + tri_rlmreg_p #(.WIDTH(34 * 4), .INIT(0), .NEEDS_SRESET(0)) iu3_instr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ic_bp_iu2_val[0]), // ??? Could create act for 0:31 when buffers full? + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu3_instr_offset:iu3_instr_offset + (34 * 4) - 1]), + .scout(sov[iu3_instr_offset:iu3_instr_offset + (34 * 4) - 1]), + .din({iu3_0_instr_d, iu3_1_instr_d, iu3_2_instr_d, iu3_3_instr_d}), + .dout({iu3_0_instr_l2, iu3_1_instr_l2, iu3_2_instr_l2, iu3_3_instr_l2}) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(0)) iu_pc_err_ucode_illegal_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu_pc_err_ucode_illegal_offset]), + .scout(sov[iu_pc_err_ucode_illegal_offset]), + .din(iu_pc_err_ucode_illegal_d), + .dout(iu_pc_err_ucode_illegal_l2) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(0)) iu_flush_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu_flush_offset]), + .scout(sov[iu_flush_offset]), + .din(iu_flush_d), + .dout(iu_flush_l2) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) br_hold_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[br_hold_offset]), + .scout(sov[br_hold_offset]), + .din(br_hold_d), + .dout(br_hold_l2) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) flush_into_uc_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[flush_into_uc_offset]), + .scout(sov[flush_into_uc_offset]), + .din(flush_into_uc_d), + .dout(flush_into_uc_l2) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) np1_flush_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cp_flush_into_uc), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[np1_flush_offset]), + .scout(sov[np1_flush_offset]), + .din(np1_flush_d), + .dout(np1_flush_l2) + ); + + tri_rlmreg_p #(.WIDTH(19), .INIT(0), .NEEDS_SRESET(0)) flush_ifar_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cp_flush_into_uc), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[flush_ifar_offset:flush_ifar_offset + 19 - 1]), + .scout(sov[flush_ifar_offset:flush_ifar_offset + 19 - 1]), + .din(flush_ifar_d), + .dout(flush_ifar_l2) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp_flush_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[cp_flush_offset]), + .scout(sov[cp_flush_offset]), + .din(cp_flush_d), + .dout(cp_flush_l2) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) br_iu_redirect_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[br_iu_redirect_offset]), + .scout(sov[br_iu_redirect_offset]), + .din(br_iu_redirect_d), + .dout(br_iu_redirect_l2) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) advance_buffers_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[advance_buffers_offset]), + .scout(sov[advance_buffers_offset]), + .din(advance_buffers_d), + .dout(advance_buffers_l2) + ); + + // ROM + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) romvalid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(uc_default_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[romvalid_offset]), + .scout(sov[romvalid_offset]), + .din(romvalid_d), + .dout(romvalid_l2) + ); + + tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(0)) rom_data_even_late_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu4_stage_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rom_data_even_late_offset:rom_data_even_late_offset + 32 - 1]), + .scout(sov[rom_data_even_late_offset:rom_data_even_late_offset + 32 - 1]), + .din(rom_data_even_late_d), + .dout(rom_data_even_late_l2) + ); + + tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(0)) rom_data_odd_late_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu4_stage_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rom_data_odd_late_offset:rom_data_odd_late_offset + 32 - 1]), + .scout(sov[rom_data_odd_late_offset:rom_data_odd_late_offset + 32 - 1]), + .din(rom_data_odd_late_d), + .dout(rom_data_odd_late_l2) + ); + + // Staging latches + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) iu4_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(uc_default_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu4_valid_offset:iu4_valid_offset + 2 - 1]), + .scout(sov[iu4_valid_offset:iu4_valid_offset + 2 - 1]), + .din(iu4_valid_d), + .dout(iu4_valid_l2) + ); + + tri_rlmreg_p #(.WIDTH(uc_ifar), .INIT(0), .NEEDS_SRESET(0)) iu4_ifar_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu4_stage_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu4_ifar_offset:iu4_ifar_offset + uc_ifar - 1]), + .scout(sov[iu4_ifar_offset:iu4_ifar_offset + uc_ifar - 1]), + .din(iu4_ifar_d), + .dout(iu4_ifar_l2) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(0)) iu4_ext0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu4_stage_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu4_ext0_offset:iu4_ext0_offset + 4 - 1]), + .scout(sov[iu4_ext0_offset:iu4_ext0_offset + 4 - 1]), + .din(iu4_ext0_d), + .dout(iu4_ext0_l2) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(0)) iu4_ext1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu4_stage_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu4_ext1_offset:iu4_ext1_offset + 4 - 1]), + .scout(sov[iu4_ext1_offset:iu4_ext1_offset + 4 - 1]), + .din(iu4_ext1_d), + .dout(iu4_ext1_l2) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(0)) iu4_done_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu4_stage_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu4_done_offset]), + .scout(sov[iu4_done_offset]), + .din(iu4_done_d), + .dout(iu4_done_l2) + ); + + // Overflow Staging latches + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) iu4_ov_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(uc_default_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu4_ov_valid_offset:iu4_ov_valid_offset + 2 - 1]), + .scout(sov[iu4_ov_valid_offset:iu4_ov_valid_offset + 2 - 1]), + .din(iu4_ov_valid_d), + .dout(iu4_ov_valid_l2) + ); + + tri_rlmreg_p #(.WIDTH(uc_ifar), .INIT(0), .NEEDS_SRESET(0)) iu4_ov_ifar_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu4_ov_stage_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu4_ov_ifar_offset:iu4_ov_ifar_offset + uc_ifar - 1]), + .scout(sov[iu4_ov_ifar_offset:iu4_ov_ifar_offset + uc_ifar - 1]), + .din(iu4_ov_ifar_d), + .dout(iu4_ov_ifar_l2) + ); + + tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(0)) iu4_ov_instr0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu4_ov_stage_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu4_ov_instr0_offset:iu4_ov_instr0_offset + 32 - 1]), + .scout(sov[iu4_ov_instr0_offset:iu4_ov_instr0_offset + 32 - 1]), + .din(iu4_ov_instr0_d), + .dout(iu4_ov_instr0_l2) + ); + + tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(0)) iu4_ov_instr1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu4_ov_stage_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu4_ov_instr1_offset:iu4_ov_instr1_offset + 32 - 1]), + .scout(sov[iu4_ov_instr1_offset:iu4_ov_instr1_offset + 32 - 1]), + .din(iu4_ov_instr1_d), + .dout(iu4_ov_instr1_l2) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(0)) u4_ov_ext0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu4_ov_stage_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu4_ov_ext0_offset:iu4_ov_ext0_offset + 4 - 1]), + .scout(sov[iu4_ov_ext0_offset:iu4_ov_ext0_offset + 4 - 1]), + .din(iu4_ov_ext0_d), + .dout(iu4_ov_ext0_l2) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(0)) iu4_ov_ext1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu4_ov_stage_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu4_ov_ext1_offset:iu4_ov_ext1_offset + 4 - 1]), + .scout(sov[iu4_ov_ext1_offset:iu4_ov_ext1_offset + 4 - 1]), + .din(iu4_ov_ext1_d), + .dout(iu4_ov_ext1_l2) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(0)) iu4_ov_done_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu4_ov_stage_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[iu4_ov_done_offset]), + .scout(sov[iu4_ov_done_offset]), + .din(iu4_ov_done_d), + .dout(iu4_ov_done_l2) + ); + + //--------------------------------------------------------------------- + // pervasive thold/sg latches + //--------------------------------------------------------------------- + + tri_plat #(.WIDTH(2)) perv_2to1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + .din({pc_iu_func_sl_thold_2, pc_iu_sg_2}), + .q( {pc_iu_func_sl_thold_1, pc_iu_sg_1}) + ); + + tri_plat #(.WIDTH(2)) perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + .din({pc_iu_func_sl_thold_1, pc_iu_sg_1}), + .q( {pc_iu_func_sl_thold_0, pc_iu_sg_0}) + ); + + tri_lcbor perv_lcbor( + .clkoff_b(clkoff_b), + .thold(pc_iu_func_sl_thold_0), + .sg(pc_iu_sg_0), + .act_dis(act_dis), + .force_t(force_t), + .thold_b(pc_iu_func_sl_thold_0_b) + ); + + //--------------------------------------------------------------------- + // Scan + //--------------------------------------------------------------------- + assign siv[0:scan_right + 4] = {sov[1:scan_right + 4], scan_in}; + assign scan_out = sov[0]; + +endmodule diff --git a/dev/verilog/work/iuq_uc_buffer.v b/dev/verilog/work/iuq_uc_buffer.v new file mode 100755 index 0000000..a7778e0 --- /dev/null +++ b/dev/verilog/work/iuq_uc_buffer.v @@ -0,0 +1,624 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//******************************************************************** +//* +//* TITLE: IU Microcode Buffers +//* +//* NAME: iuq_uc_buffer.v +//* +//********************************************************************* + +`include "tri_a2o.vh" + + +module iuq_uc_buffer( + vdd, + gnd, + nclk, + pc_iu_func_sl_thold_0_b, + pc_iu_sg_0, + force_t, + d_mode, + delay_lclkr, + mpw1_b, + mpw2_b, + scan_in, + scan_out, + iu3_val_l2, + iu3_ifar_l2, + iu3_2ucode_l2, + iu3_0_instr_l2, + iu3_1_instr_l2, + iu3_2_instr_l2, + iu3_3_instr_l2, + ic_bp_iu2_flush, + ic_bp_iu3_flush, + ic_bp_iu3_ecc_err, + bp_ib_iu3_val, + uc_ib_iu3_invalid, + uc_ib_iu3_flush_all, + uc_ic_hold, + uc_iu4_flush, + uc_iu4_flush_ifar, + xu_iu_flush, + uc_val, + advance_buffers, + br_hold_l2, + cplbuffer_full, + clear_ill_flush_2ucode, + next_valid, + next_instr, + iu2_flush, + flush_next, + flush_current +); + + + inout vdd; + + inout gnd; + + + (* pin_data ="PIN_FUNCTION=/G_CLK/" *) + input [0:`NCLK_WIDTH-1] nclk; + input pc_iu_func_sl_thold_0_b; + input pc_iu_sg_0; + input force_t; + input d_mode; + input delay_lclkr; + input mpw1_b; + input mpw2_b; + + (* pin_data ="PIN_FUNCTION=/SCAN_IN/" *) + input scan_in; + + (* pin_data ="PIN_FUNCTION=/SCAN_OUT/" *) + output scan_out; + + input [0:3] iu3_val_l2; + input [62-`EFF_IFAR_WIDTH:61] iu3_ifar_l2; + input iu3_2ucode_l2; // Only iu3_0_instr0 can ever be 2ucode because xu_iu_flush clears everything before it. + + input [0:33] iu3_0_instr_l2; + input [0:33] iu3_1_instr_l2; + input [0:33] iu3_2_instr_l2; + input [0:33] iu3_3_instr_l2; + + input ic_bp_iu2_flush; + input ic_bp_iu3_flush; + input ic_bp_iu3_ecc_err; + + input [0:3] bp_ib_iu3_val; + + output [0:3] uc_ib_iu3_invalid; // IB uses this to mask off the valids + + output uc_ib_iu3_flush_all; // IB uses this to clear buffer (because not enough time to get into iu3_invalid) + + output uc_ic_hold; + + output uc_iu4_flush; + output [62-`EFF_IFAR_WIDTH:61] uc_iu4_flush_ifar; + + input xu_iu_flush; + + // Internal to microcode + input uc_val; + input advance_buffers; + input br_hold_l2; + input cplbuffer_full; + input clear_ill_flush_2ucode; + + output next_valid; // Does not include flush + output [0:31] next_instr; + + output iu2_flush; // Does not include XU flush + output flush_next; // Includes XU flush + output flush_current; // Includes XU flush + + parameter uc_ic_hold_offset = 0; + parameter uc_iu4_flush_offset = uc_ic_hold_offset + 1; + parameter uc_iu4_flush_ifar_offset = uc_iu4_flush_offset + 1; + parameter buffer_valid_offset = uc_iu4_flush_ifar_offset + `EFF_IFAR_WIDTH; + parameter buffer1_offset = buffer_valid_offset + 4; //buffer0_offset + 2; + parameter buffer2_offset = buffer1_offset + 32; + parameter buffer3_offset = buffer2_offset + 32; + parameter buffer4_offset = buffer3_offset + 32; + parameter scan_right = buffer4_offset + 32 - 1; //buffer_stg_iu4_offset + 5 - 1; + + // Latches + wire uc_ic_hold_d; + wire uc_iu4_flush_d; + wire [62-`EFF_IFAR_WIDTH:61] uc_iu4_flush_ifar_d; + + wire [1:4] buffer_valid_d; + wire [0:31] buffer1_d; + wire [0:31] buffer2_d; + wire [0:31] buffer3_d; + wire [0:31] buffer4_d; + + wire uc_ic_hold_l2; + wire uc_iu4_flush_l2; + wire [62-`EFF_IFAR_WIDTH:61] uc_iu4_flush_ifar_l2; + + wire [1:4] buffer_valid_l2; + wire [0:31] buffer1_l2; + wire [0:31] buffer2_l2; + wire [0:31] buffer3_l2; + wire [0:31] buffer4_l2; + + wire [0:3] new_ucode_in; + wire uc_buffer_act; + wire uc_stall; + + // Left shift incoming microcode instructions + wire [0:3] ucode_and_bp_in; + wire [0:3] valid_in; + wire [0:3] early_val_in; + wire [0:31] instr0_in; + wire [0:31] instr1_in; + wire [0:31] instr2_in; + wire [0:31] instr3_in; + wire [60:61] ic_ifar0; + wire [60:61] ic_ifar1; + wire [60:61] ic_ifar2; + wire [60:61] ic_ifar3; + wire [60:61] ifar0_in; + wire [60:61] ifar1_in; + wire [60:61] ifar2_in; + wire [60:61] ifar3_in; + + // Flushes + wire iu3_flush; + + wire [0:3] early_need_flush_instr_in; + wire [0:3] need_flush_instr_in; + wire [60:61] overflow_flush_ifar; + + wire [0:3] imask0_in; + wire [0:3] imask1_in; + wire [0:3] imask2_in; + wire [0:3] imask3_in; + wire [0:3] uc_iu3_flush_imask; + + // Buffer + wire bp_flush_next; + + wire [0:scan_right] siv; + wire [0:scan_right] sov; + + //tidn <= '0'; + //tiup <= '1'; + + assign new_ucode_in[0] = iu3_val_l2[0] & ((iu3_0_instr_l2[32:33] == 2'b01) | iu3_2ucode_l2); + assign new_ucode_in[1] = iu3_val_l2[1] & (iu3_1_instr_l2[32:33] == 2'b01); + assign new_ucode_in[2] = iu3_val_l2[2] & (iu3_2_instr_l2[32:33] == 2'b01); + assign new_ucode_in[3] = iu3_val_l2[3] & (iu3_3_instr_l2[32:33] == 2'b01); + + // default act signal + assign uc_buffer_act = uc_val | buffer_valid_l2[1] | (|(new_ucode_in)) | uc_iu4_flush_l2; + + // stall if processing command in buffer0 or commands are being held off. When current command finishes, + // buffer0 takes next command when uc_end, but Buffers need to latch info + // and advance next cycle because we cannot make timing (ib_uc_rdy comes late) + // This means buffer0 can have same command as buffer1 for a cycle + assign uc_stall = (uc_val | br_hold_l2 | cplbuffer_full) & (~advance_buffers); + + //--------------------------------------------------------------------- + // left shift incoming microcode instructions + //--------------------------------------------------------------------- + //Detect if redirected by BP + assign ucode_and_bp_in = new_ucode_in & bp_ib_iu3_val; + + assign valid_in[0] = |(ucode_and_bp_in); + assign valid_in[1] = (~(( ucode_and_bp_in[0:2] == 3'b000) | + (({ucode_and_bp_in[0:1], ucode_and_bp_in[3]}) == 3'b000) | + (({ucode_and_bp_in[0], ucode_and_bp_in[2:3]}) == 3'b000) | + ( ucode_and_bp_in[1:3] == 3'b000))); // not 0000,0001,0010,0100,1000 + + assign valid_in[2] = ( ucode_and_bp_in[0:2] == 3'b111) | + ({ucode_and_bp_in[0:1], ucode_and_bp_in[3]} == 3'b111) | + ({ucode_and_bp_in[0], ucode_and_bp_in[2:3]} == 3'b111) | + ( ucode_and_bp_in[1:3] == 3'b111); // 1111,1110,1101,1011,0111 + + assign valid_in[3] = ucode_and_bp_in == 4'b1111; + + // This early signal does not include BP val, and is used for IB invalidate + assign early_val_in[0] = |(new_ucode_in); + assign early_val_in[1] = (~(( new_ucode_in[0:2] == 3'b000) | + ({new_ucode_in[0:1], new_ucode_in[3]} == 3'b000) | + ({new_ucode_in[0], new_ucode_in[2:3]} == 3'b000) | + ( new_ucode_in[1:3] == 3'b000))); // not 0000,0001,0010,0100,1000 + + assign early_val_in[2] = ( new_ucode_in[0:2] == 3'b111) | + ({new_ucode_in[0:1], new_ucode_in[3]} == 3'b111) | + ({new_ucode_in[0], new_ucode_in[2:3]} == 3'b111) | + ( new_ucode_in[1:3] == 3'b111); // 1111,1110,1101,1011,0111 + + assign early_val_in[3] = new_ucode_in == 4'b1111; + + assign instr0_in = (new_ucode_in[0] == 1'b1) ? iu3_0_instr_l2[0:31] : // 1--- + (new_ucode_in[1] == 1'b1) ? iu3_1_instr_l2[0:31] : // 01-- + (new_ucode_in[2] == 1'b1) ? iu3_2_instr_l2[0:31] : // 001- + iu3_3_instr_l2[0:31]; + + assign instr1_in = (new_ucode_in[0:1] == 2'b11) ? iu3_1_instr_l2[0:31] : // 11-- + (((new_ucode_in[0:2] == 3'b011) | // 011- + (new_ucode_in[0:2] == 3'b101))) ? iu3_2_instr_l2[0:31] : // 101- + iu3_3_instr_l2[0:31]; + + assign instr2_in = (new_ucode_in[0:2] == 3'b111) ? iu3_2_instr_l2[0:31] : // 111- + iu3_3_instr_l2[0:31]; + + assign instr3_in = iu3_3_instr_l2[0:31]; + + assign ic_ifar0 = iu3_ifar_l2[60:61]; + + assign ic_ifar1 = (iu3_ifar_l2[60:61] == 2'b00) ? 2'b01 : + (iu3_ifar_l2[60:61] == 2'b01) ? 2'b10 : + 2'b11; + + assign ic_ifar2 = {(~iu3_ifar_l2[60]), iu3_ifar_l2[61]}; + assign ic_ifar3 = 2'b11; + + assign ifar0_in = (new_ucode_in[0] == 1'b1) ? ic_ifar0 : // 1--- + (new_ucode_in[1] == 1'b1) ? ic_ifar1 : // 01-- + (new_ucode_in[2] == 1'b1) ? ic_ifar2 : // 001- + ic_ifar3; + + assign ifar1_in = (new_ucode_in[0:1] == 2'b11) ? ic_ifar1 : // 11-- + (((new_ucode_in[0:2] == 3'b011) | // 011- + (new_ucode_in[0:2] == 3'b101))) ? ic_ifar2 : // 101- + ic_ifar3; + + assign ifar2_in = (new_ucode_in[0:2] == 3'b111) ? ic_ifar2 : // 111- + ic_ifar3; + + assign ifar3_in = ic_ifar3; + + //--------------------------------------------------------------------- + // Flushes + //--------------------------------------------------------------------- + // Does not include xu_iu_flush (for timing) + assign iu3_flush = ic_bp_iu3_flush | uc_iu4_flush_l2 | ic_bp_iu3_ecc_err; + assign iu2_flush = ic_bp_iu3_flush | uc_iu4_flush_l2 | (|(need_flush_instr_in)) | ic_bp_iu2_flush; + + // Need UC flush if overflowing buffer + // early signal does not check BP val + assign early_need_flush_instr_in = ((early_val_in[0] & buffer_valid_l2[4] & uc_stall) == 1'b1) ? 4'b1000 : + ((early_val_in[1] & ((buffer_valid_l2[3] & uc_stall) | (buffer_valid_l2[4] & (~uc_stall)))) == 1'b1) ? 4'b0100 : + ((early_val_in[2] & ((buffer_valid_l2[2] & uc_stall) | (buffer_valid_l2[3] & (~uc_stall)))) == 1'b1) ? 4'b0010 : + ((early_val_in[3] & ((buffer_valid_l2[1] & uc_stall) | (buffer_valid_l2[2] & (~uc_stall)))) == 1'b1) ? 4'b0001 : + 4'b0000; + + assign need_flush_instr_in = early_need_flush_instr_in & valid_in; + + assign overflow_flush_ifar[60:61] = (ifar0_in & {2{need_flush_instr_in[0]}}) | + (ifar1_in & {2{need_flush_instr_in[1]}}) | + (ifar2_in & {2{need_flush_instr_in[2]}}) | + (ifar3_in & {2{need_flush_instr_in[3]}}); + + assign uc_iu4_flush_ifar_d[62 - `EFF_IFAR_WIDTH:59] = iu3_ifar_l2[62 - `EFF_IFAR_WIDTH:59]; + assign uc_iu4_flush_ifar_d[60:61] = clear_ill_flush_2ucode ? ifar0_in : + overflow_flush_ifar; + + // Which of the 4 instructions was flushed + assign imask0_in = (new_ucode_in[0] == 1'b1) ? 4'b1111 : // 1--- + (new_ucode_in[1] == 1'b1) ? 4'b0111 : // 01-- + (new_ucode_in[2] == 1'b1) ? 4'b0011 : // 001- + 4'b0001; + + assign imask1_in = (new_ucode_in[0:1] == 2'b11) ? 4'b0111 : // 11-- + (((new_ucode_in[0:2] == 3'b011) | // 011- + (new_ucode_in[0:2] == 3'b101))) ? 4'b0011 : // 101- + 4'b0001; + + assign imask2_in = (new_ucode_in[0:2] == 3'b111) ? 4'b0011 : // 111- + 4'b0001; + + assign imask3_in = 4'b0001; + + assign uc_iu3_flush_imask = (imask0_in & {4{early_need_flush_instr_in[0]}}) | + (imask1_in & {4{early_need_flush_instr_in[1]}}) | + (imask2_in & {4{early_need_flush_instr_in[2]}}) | + (imask3_in & {4{early_need_flush_instr_in[3]}}); + + assign uc_ib_iu3_invalid = uc_iu3_flush_imask | {4{uc_iu4_flush_l2}}; + + assign uc_iu4_flush_d = (|(need_flush_instr_in) | clear_ill_flush_2ucode) & (~iu3_flush) & (~xu_iu_flush); + + assign uc_ib_iu3_flush_all = clear_ill_flush_2ucode & (~iu3_flush); + + // Detect IB flush + + // Simpler to wait until IU4 because BP flush is IU3 & IU4 + // (old)IB flush should take precedence over UC flush in IC because we invalidated UC flushes in IU3 + // UC flush should take precedence over BP flush in IC because we checked BP valids in IU3 + assign uc_iu4_flush = uc_iu4_flush_l2; + assign uc_iu4_flush_ifar = uc_iu4_flush_ifar_l2; + + assign uc_ic_hold_d = (buffer_valid_d[4] == 1'b0) ? 1'b0 : + (uc_iu4_flush_l2 == 1'b1) ? 1'b1 : + uc_ic_hold_l2; + + assign uc_ic_hold = uc_ic_hold_l2; + + //--------------------------------------------------------------------- + // Buffers + //--------------------------------------------------------------------- + // Buffer0 is the instruction that UC is currently working on + assign next_instr = (buffer_valid_l2[2] == 1'b1 & advance_buffers == 1'b1) ? buffer2_l2[0:31] : + (buffer_valid_l2[1] == 1'b1 & advance_buffers == 1'b0) ? buffer1_l2[0:31] : + instr0_in; + + // Note: buffer0 could be taking buffer2 info next cycle, but we never can get an ib_flush on buffer0 + // in that scenario + + // ??? Do I want to switch ordering so bufferX_l2 is default case? (save power/toggling) + assign buffer1_d = (uc_stall == 1'b1 & buffer_valid_l2[1] == 1'b1) ? buffer1_l2 : + (uc_stall == 1'b0 & buffer_valid_l2[2] == 1'b1) ? buffer2_l2 : + (uc_stall == 1'b0 & buffer_valid_l2[1] == 1'b0) ? instr1_in : + instr0_in; + + assign buffer2_d = (uc_stall == 1'b1 & buffer_valid_l2[2] == 1'b1) ? buffer2_l2 : + (uc_stall == 1'b0 & buffer_valid_l2[3] == 1'b1) ? buffer3_l2 : + (uc_stall == 1'b0 & buffer_valid_l2[1] == 1'b0) ? instr2_in : + (uc_stall == 1'b1 & buffer_valid_l2[1] == 1'b0) ? instr1_in : + (uc_stall == 1'b0 & buffer_valid_l2[2] == 1'b0) ? instr1_in : + instr0_in; + + assign buffer3_d = (uc_stall == 1'b1 & buffer_valid_l2[3] == 1'b1) ? buffer3_l2 : + (uc_stall == 1'b0 & buffer_valid_l2[4] == 1'b1) ? buffer4_l2 : + (uc_stall == 1'b0 & buffer_valid_l2[1] == 1'b0) ? instr3_in : + (uc_stall == 1'b1 & buffer_valid_l2[1] == 1'b0) ? instr2_in : + (uc_stall == 1'b0 & buffer_valid_l2[2] == 1'b0) ? instr2_in : + (uc_stall == 1'b1 & buffer_valid_l2[2] == 1'b0) ? instr1_in : + (uc_stall == 1'b0 & buffer_valid_l2[3] == 1'b0) ? instr1_in : + instr0_in; + + assign buffer4_d = (uc_stall == 1'b1 & buffer_valid_l2[4] == 1'b1) ? buffer4_l2 : + (uc_stall == 1'b1 & buffer_valid_l2[1] == 1'b0) ? instr3_in : + (uc_stall == 1'b0 & buffer_valid_l2[2] == 1'b0) ? instr3_in : + (uc_stall == 1'b1 & buffer_valid_l2[2] == 1'b0) ? instr2_in : + (uc_stall == 1'b0 & buffer_valid_l2[3] == 1'b0) ? instr2_in : + (uc_stall == 1'b1 & buffer_valid_l2[3] == 1'b0) ? instr1_in : + (uc_stall == 1'b0 & buffer_valid_l2[4] == 1'b0) ? instr1_in : + instr0_in; + + // Output is never in IU4 now that we latch incoming IU2 signals + + assign bp_flush_next = (|(new_ucode_in)) & (~valid_in[0]); + + assign flush_current = xu_iu_flush; // Current instruction flushed + assign flush_next = ((~((buffer_valid_l2[2] & advance_buffers) | (buffer_valid_l2[1] & (~advance_buffers)))) & (iu3_flush | bp_flush_next)) | xu_iu_flush; + + assign next_valid = (buffer_valid_l2[2] & advance_buffers) | + (buffer_valid_l2[1] & (~advance_buffers)) | + (|(new_ucode_in)); // Does not include flush + + assign buffer_valid_d[1] = ((buffer_valid_l2[1] & uc_stall) | + buffer_valid_l2[2] | + (((valid_in[1]) | + (valid_in[0] & buffer_valid_l2[1]) | + (uc_stall & valid_in[0])) & (~iu3_flush))) + & (~xu_iu_flush); + + assign buffer_valid_d[2] = ((buffer_valid_l2[2] & uc_stall) | + buffer_valid_l2[3] | + (((valid_in[2]) | + (valid_in[1] & buffer_valid_l2[1]) | + (valid_in[0] & buffer_valid_l2[2]) | + (uc_stall & (valid_in[1] | + (valid_in[0] & buffer_valid_l2[1])))) & (~iu3_flush))) + & (~xu_iu_flush); + + assign buffer_valid_d[3] = ((buffer_valid_l2[3] & uc_stall) | + buffer_valid_l2[4] | + (((valid_in[3]) | + (valid_in[2] & buffer_valid_l2[1]) | + (valid_in[1] & buffer_valid_l2[2]) | + (valid_in[0] & buffer_valid_l2[3]) | + (uc_stall & (valid_in[2] | + (valid_in[1] & buffer_valid_l2[1]) | + (valid_in[0] & buffer_valid_l2[2])))) & (~iu3_flush))) + & (~xu_iu_flush); + + assign buffer_valid_d[4] = ((buffer_valid_l2[4] & uc_stall) | + (((valid_in[3] & buffer_valid_l2[1]) | + (valid_in[2] & buffer_valid_l2[2]) | + (valid_in[1] & buffer_valid_l2[3]) | + (valid_in[0] & buffer_valid_l2[4]) | + (uc_stall & (valid_in[3] | + (valid_in[2] & buffer_valid_l2[1]) | + (valid_in[1] & buffer_valid_l2[2]) | + (valid_in[0] & buffer_valid_l2[3])))) & (~iu3_flush))) + & (~xu_iu_flush); + + //--------------------------------------------------------------------- + // Latches + //--------------------------------------------------------------------- + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) uc_ic_hold_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(uc_buffer_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[uc_ic_hold_offset]), + .scout(sov[uc_ic_hold_offset]), + .din(uc_ic_hold_d), + .dout(uc_ic_hold_l2) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) uc_iu4_flush_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(uc_buffer_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[uc_iu4_flush_offset]), + .scout(sov[uc_iu4_flush_offset]), + .din(uc_iu4_flush_d), + .dout(uc_iu4_flush_l2) + ); + + + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0), .NEEDS_SRESET(0)) uc_iu4_flush_ifar_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(uc_iu4_flush_d), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[uc_iu4_flush_ifar_offset:uc_iu4_flush_ifar_offset + `EFF_IFAR_WIDTH - 1]), + .scout(sov[uc_iu4_flush_ifar_offset:uc_iu4_flush_ifar_offset + `EFF_IFAR_WIDTH - 1]), + .din(uc_iu4_flush_ifar_d), + .dout(uc_iu4_flush_ifar_l2) + ); + + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) buffer_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(uc_buffer_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[buffer_valid_offset:buffer_valid_offset + 4 - 1]), + .scout(sov[buffer_valid_offset:buffer_valid_offset + 4 - 1]), + .din(buffer_valid_d), + .dout(buffer_valid_l2) + ); + + tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(0)) buffer1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(uc_buffer_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[buffer1_offset:buffer1_offset + 32 - 1]), + .scout(sov[buffer1_offset:buffer1_offset + 32 - 1]), + .din(buffer1_d), + .dout(buffer1_l2) + ); + + + tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(0)) buffer2_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(uc_buffer_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[buffer2_offset:buffer2_offset + 32 - 1]), + .scout(sov[buffer2_offset:buffer2_offset + 32 - 1]), + .din(buffer2_d), + .dout(buffer2_l2) + ); + + + tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(0)) buffer3_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(uc_buffer_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[buffer3_offset:buffer3_offset + 32 - 1]), + .scout(sov[buffer3_offset:buffer3_offset + 32 - 1]), + .din(buffer3_d), + .dout(buffer3_l2) + ); + + + tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(0)) buffer4_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(uc_buffer_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[buffer4_offset:buffer4_offset + 32 - 1]), + .scout(sov[buffer4_offset:buffer4_offset + 32 - 1]), + .din(buffer4_d), + .dout(buffer4_l2) + ); + + //--------------------------------------------------------------------- + // Scan + //--------------------------------------------------------------------- + assign siv[0:scan_right] = {sov[1:scan_right], scan_in}; + assign scan_out = sov[0]; + +endmodule diff --git a/dev/verilog/work/iuq_uc_control.v b/dev/verilog/work/iuq_uc_control.v new file mode 100755 index 0000000..eaeee51 --- /dev/null +++ b/dev/verilog/work/iuq_uc_control.v @@ -0,0 +1,1214 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//******************************************************************** +//* +//* TITLE: Microcode Control +//* +//* NAME: iuq_uc_control.v +//* +//********************************************************************* + +`include "tri_a2o.vh" + + +module iuq_uc_control( + vdd, + gnd, + nclk, + pc_iu_func_sl_thold_0_b, + pc_iu_sg_0, + force_t, + d_mode, + delay_lclkr, + mpw1_b, + mpw2_b, + scan_in, + scan_out, + xu_iu_ucode_xer_val, + xu_iu_ucode_xer, + br_hold, + flush_next, + flush, + flush_into_uc, + np1_flush, + flush_ifar, + cp_uc_credit_free, + cp_flush, + uc_default_act, + next_valid, + new_command, + new_instr, + start_addr, + xer_type, + early_end, + force_ep, + fxm_type, + new_cond, + ra_valid, + rom_ra, + rom_act, + data_valid, + rom_data_even, + rom_data_odd, + rom_data_even_late, + rom_data_odd_late, + uc_val, + uc_end, + cplbuffer_full, + ucode_valid, + ucode_ifar_even, + ucode_instr_even, + ucode_instr_odd, + ucode_ext_even, + ucode_ext_odd +); + //parameter ucode_width = 72; + + + inout vdd; + + inout gnd; + + (* pin_data ="PIN_FUNCTION=/G_CLK/" *) + input [0:`NCLK_WIDTH-1] nclk; + input pc_iu_func_sl_thold_0_b; + input pc_iu_sg_0; + input force_t; + input d_mode; + input delay_lclkr; + input mpw1_b; + input mpw2_b; + + (* pin_data ="PIN_FUNCTION=/SCAN_IN/" *) + input scan_in; + + (* pin_data ="PIN_FUNCTION=/SCAN_OUT/" *) + output scan_out; + + input xu_iu_ucode_xer_val; + input [57:63] xu_iu_ucode_xer; + input br_hold; // br_redirect requires hold on xer_type's + input flush_next; // Flush new instruction + input flush; // Flush current instruction + input flush_into_uc; // Flush back into the middle of uCode sequence + input np1_flush; // Skip flushed instruction and go to next + input [43:61] flush_ifar; // ucode-style address & state to flush to + input cp_uc_credit_free; + input cp_flush; + input uc_default_act; + input next_valid; // early signal for act + input new_command; + input [0:31] new_instr; + input [0:8] start_addr; // bit (9) is unused - always '0' + input xer_type; // instruction uses XER: need to wait until XER guaranteed valid + input early_end; + input force_ep; + input fxm_type; + input new_cond; // If '1', will skip lines with skip_cond bit set + + output ra_valid; + output [0:8] rom_ra; // read address + output rom_act; + + input data_valid; + input [32:71] rom_data_even; + input [32:71] rom_data_odd; + input [0:31] rom_data_even_late; + input [0:31] rom_data_odd_late; + + output uc_val; // to uc_buffer + output uc_end; // to uc_buffer + output cplbuffer_full; // to uc_buffer + + output [0:1] ucode_valid; + output [42:61] ucode_ifar_even; // old: EFF_IFAR + output [0:31] ucode_instr_even; + output [0:31] ucode_instr_odd; + output [0:3] ucode_ext_even; // RT, S1, S2, S3 + output [0:3] ucode_ext_odd; // RT, S1, S2, S3 + + parameter xu_iu_ucode_xer_offset = 0; + parameter xu_iu_ucode_xer_val_offset = xu_iu_ucode_xer_offset + 7; + parameter wait_for_xer_offset = xu_iu_ucode_xer_val_offset + 1; + parameter xer_val_occurred_offset = wait_for_xer_offset + 1; + parameter valid_offset = xer_val_occurred_offset + 1; + parameter instr_offset = valid_offset + 1; + parameter instr_even_late_offset = instr_offset + 32; + parameter instr_odd_late_offset = instr_even_late_offset + 32; + parameter sel_even_late_offset = instr_odd_late_offset + 32; + parameter sel_odd_late_offset = sel_even_late_offset + 12; + parameter early_end_offset = sel_odd_late_offset + 11; + parameter cond_offset = early_end_offset + 1; + parameter rom_addr_offset = cond_offset + 1; + parameter flush_to_odd_offset = rom_addr_offset + 9; + parameter inloop_offset = flush_to_odd_offset + 1; + parameter count_offset = inloop_offset + 1; + parameter skip_zero_offset = count_offset + 5; + parameter skip_to_np1_offset = skip_zero_offset + 1; + parameter force_ep_offset = skip_to_np1_offset + 1; + parameter fxm_type_offset = force_ep_offset + 1; + parameter ep_force_even_late_offset = fxm_type_offset + 1; + parameter ep_force_odd_late_offset = ep_force_even_late_offset + 1; + parameter scan_right = ep_force_odd_late_offset + 1 - 1; + + // Latches + wire [57:63] xu_iu_ucode_xer_d; + wire xu_iu_ucode_xer_val_d; + wire wait_for_xer_d; + wire xer_val_occurred_d; + wire valid_d; + wire [0:31] instr_d; + wire early_end_d; + wire cond_d; + wire [0:8] rom_addr_d; + wire flush_to_odd_d; + wire inLoop_d; + wire [0:4] count_d; + wire skip_zero_d; + wire skip_to_np1_d; + + wire [57:63] xu_iu_ucode_xer_l2; + wire xu_iu_ucode_xer_val_l2; + wire wait_for_xer_l2; + wire xer_val_occurred_l2; + wire valid_l2; + wire [0:31] instr_l2; + wire early_end_l2; + wire cond_l2; + wire [0:8] rom_addr_l2; + wire flush_to_odd_l2; + wire inLoop_l2; + wire [0:4] count_l2; + wire skip_zero_l2; + wire skip_to_np1_l2; + + wire force_ep_d; + wire force_ep_l2; + wire fxm_type_d; + wire fxm_type_l2; + + wire shift_fxm; + + // + // Even + wire [0:31] template_code_even; + wire uc_end_even; + wire uc_end_early_even; + wire loop_begin_even; + wire loop_end_even; + wire [0:2] count_src_even; + wire [0:3] ext_even; + wire sel0_5_even; + wire [0:1] sel6_10_even; + wire [0:1] sel11_15_even; + wire [0:1] sel16_20_even; + wire [0:1] sel21_25_even; + wire sel26_30_even; + wire sel31_even; + wire cr_bf2fxm_even; // for mtocrf + wire skip_cond_even; + wire skip_zero_even; + wire skip_nop_even; + wire [0:9] loop_addr_even; + wire [0:2] loop_init_even; + wire ep_instr_even; + + wire ucode_end_even; + wire [0:7] fxm; + wire [0:31] nop; + wire [0:3] nop_ext; + wire use_nop_even; + wire [0:31] uc_instruction_even; + + //timing fixes + wire sel0_5_even_late; + wire [0:1] sel6_10_even_late; + wire [0:1] sel11_15_even_late; + wire [0:1] sel16_20_even_late; + wire [0:1] sel21_25_even_late; + wire sel26_30_even_late; + wire sel31_even_late; + wire use_nop_even_late; + + wire [0:11] sel_even_late_d; + wire [0:11] sel_even_late_l2; + wire ep_force_even_late_d; + wire ep_force_even_late_l2; + wire [0:31] instr_even_late_d; + wire [0:31] instr_even_late_l2; + + // + // Odd + wire [0:31] template_code_odd; + wire uc_end_odd; + wire uc_end_early_odd; + wire loop_begin_odd; + wire loop_end_odd; + wire [0:2] count_src_odd; + wire [0:3] ext_odd; + wire sel0_5_odd; + wire [0:1] sel6_10_odd; + wire [0:1] sel11_15_odd; + wire [0:1] sel16_20_odd; + wire [0:1] sel21_25_odd; + wire sel26_30_odd; + wire sel31_odd; + wire cr_bf2fxm_odd; // for mtocrf + wire skip_cond_odd; + wire skip_zero_odd; + wire skip_nop_odd; + wire [0:9] loop_addr_odd; + wire [0:2] loop_init_odd; + wire ep_instr_odd; + + wire ucode_end_odd; + wire [0:31] uc_instruction_odd; + + //timing fixes + wire sel0_5_odd_late; + wire [0:1] sel6_10_odd_late; + wire [0:1] sel11_15_odd_late; + wire [0:1] sel16_20_odd_late; + wire [0:1] sel21_25_odd_late; + wire sel26_30_odd_late; + wire sel31_odd_late; + + wire [0:10] sel_odd_late_d; + wire [0:10] sel_odd_late_l2; + wire ep_force_odd_late_d; + wire ep_force_odd_late_l2; + wire [0:31] instr_odd_late_d; + wire [0:31] instr_odd_late_l2; + + // + // Combined + wire loop_begin; + wire loop_end; + wire [0:2] count_src; + wire skip_zero; + wire [0:8] loop_addr; // bit (9) is unused (always '0') + wire [0:2] loop_init; + + wire ucode_end; + + // control + wire last_loop; + wire last_loop_fast; + wire loopback; + wire inc_RT; + + wire xer_act; + wire [0:4] NB_dec; + wire [0:1] NB_comp; + wire [0:6] XER_dec_z; + wire [0:2] XER_low; + wire [0:1] XER_comp; + wire [0:4] count_init; + wire skip_even; + wire skip_odd; + + wire [0:31] buff_instr_in; + wire cplbuffer_xer_act; + wire cplbuffer_full_int; + wire [0:31] oldest_instr; + wire [57:63] oldest_xer; + + wire uc_control_act; + + wire tiup; + + wire [0:scan_right] siv; + wire [0:scan_right] sov; + wire buff_scan_in; + wire buff_scan_out; + + + (* analysis_not_referenced="true" *) + + wire [0:16] unused; + + //tidn <= '0'; + assign tiup = 1'b1; + + //--------------------------------------------------------------------- + // load new command + //--------------------------------------------------------------------- + + //???? Add act once new_command timing is ok (everything except xu_iu_ucode_xer_val) + //???? uc_act <= new_command or valid_l2; + assign uc_control_act = flush_into_uc | next_valid | data_valid; + assign rom_act = uc_control_act; + + // Wait for 1 cycle after getting new command to allow IU to flush + + assign valid_d = ((new_command & (~flush_next)) | (valid_l2 & (~(ucode_end & data_valid)) & (~flush))) | flush_into_uc; + + assign uc_val = valid_l2; + + // Don't need br_hold anymore because new_command checks this + assign wait_for_xer_d = (flush == 1'b1) ? 1'b0 : //flush_into_uc = '1' + (new_command == 1'b1) ? (xer_type & (~(xu_iu_ucode_xer_val_l2 | xer_val_occurred_l2)) ) : + ((xu_iu_ucode_xer_val_l2 | xer_val_occurred_l2) == 1'b1) ? 1'b0 : + wait_for_xer_l2; + + // Set if xer_val comes before wait_for_xer (preissue sent, but valid is held off in uc_buffer) + // Clear when new_command (and don't set wait_for_xer hold), or clear on flush or br_hold + assign xer_val_occurred_d = (xu_iu_ucode_xer_val_l2 | xer_val_occurred_l2) & (~wait_for_xer_l2) & (~new_command) & (~flush) & (~br_hold); + + assign instr_d[0:5] = (flush_into_uc == 1'b1) ? oldest_instr[0:5] : + (new_command == 1'b1) ? new_instr[0:5] : + instr_l2[0:5]; + + assign instr_d[6:10] = (flush_into_uc == 1'b1) ? flush_ifar[49:53] : + (new_command == 1'b1) ? new_instr[6:10] : + (inc_RT == 1'b1) ? instr_l2[6:10] + 5'b00001 : + instr_l2[6:10]; + + assign instr_d[11] = (flush_into_uc == 1'b1) ? oldest_instr[11] : + (new_command == 1'b1) ? new_instr[11] : + instr_l2[11]; + + // Note: we must never flush_into_uc for a fxm_type instruction because we don't keep that info + assign instr_d[12:19] = (flush_into_uc == 1'b1) ? oldest_instr[12:19] : + (new_command == 1'b1) ? new_instr[12:19] : + (shift_fxm == 1'b1) ? {instr_l2[14:19], instr_l2[12:13]} : + instr_l2[12:19]; + + assign instr_d[20:31] = (flush_into_uc == 1'b1) ? oldest_instr[20:31] : + (new_command == 1'b1) ? new_instr[20:31] : + instr_l2[20:31]; + + assign early_end_d = (flush_into_uc == 1'b1) ? oldest_instr[6] : + (new_command == 1'b1) ? early_end : + early_end_l2; + + assign cond_d = (flush_into_uc == 1'b1) ? oldest_instr[7] : + (new_command == 1'b1) ? new_cond : + cond_l2; + + assign force_ep_d = (flush_into_uc == 1'b1) ? oldest_instr[8] : + (new_command == 1'b1) ? force_ep : + force_ep_l2; + + // Note: we must never flush_into_uc for a fxm_type instruction because we don't keep latest instr(12:19) + assign fxm_type_d = (flush_into_uc == 1'b1) ? 1'b0 : + (new_command == 1'b1) ? fxm_type : // for mtcrf + fxm_type_l2; + + assign shift_fxm = fxm_type_l2 & data_valid; + + // uCode sequence cannot cross 256-instr address boundary + // Read 2 instructions at a time, so only need 9 bits + assign rom_addr_d = (flush_into_uc == 1'b1) ? {oldest_instr[9:10], flush_ifar[54:60]} : + (new_command == 1'b1) ? start_addr : + (loopback == 1'b1) ? loop_addr : + (data_valid == 1'b1) ? (rom_addr_l2[0:8] + 9'b000000001) : + rom_addr_l2; + + assign rom_ra = rom_addr_d; + + assign ra_valid = valid_d & (~wait_for_xer_d) & (~br_hold) & (~cplbuffer_full_int); // ???? should I change to just check next cycle, or leave as is in case we add other threads? + + // If flushing to second half of pair, throw no-op into first position to keep things balanced. + assign flush_to_odd_d = (flush_into_uc == 1'b1) ? flush_ifar[61] : + (new_command == 1'b1) ? 1'b0 : + (data_valid == 1'b1) ? 1'b0 : + flush_to_odd_l2; + + //--------------------------------------------------------------------- + // create output instruction - even + //--------------------------------------------------------------------- + assign uc_end_even = rom_data_even[32]; + assign uc_end_early_even = rom_data_even[33]; + assign loop_begin_even = rom_data_even[34]; + assign loop_end_even = rom_data_even[35] & (inLoop_l2 | loop_begin_even); + assign count_src_even = rom_data_even[36:38]; // 00: NB(3:4), 01: "000" & 2's comp NB(3:4), 10: mult of 4 & XER(62:63), 11: 2's comp XER(62:63), 100: RT(inverted), 101: NB(0:2) - word mode, 110: XER(57:61) - word mode, 111: loop_init + assign ext_even[0] = rom_data_even[39]; // RT -- ??? Can we incorporate into mux selects? + assign ext_even[1] = rom_data_even[40]; // S1 + assign ext_even[2] = rom_data_even[41]; // S2 + assign ext_even[3] = rom_data_even[42]; // S3 + assign sel0_5_even = rom_data_even[43]; + assign sel6_10_even = rom_data_even[44:45]; + assign sel11_15_even = rom_data_even[46:47]; + assign sel16_20_even = rom_data_even[48:49]; + assign sel21_25_even = rom_data_even[50:51]; + assign sel26_30_even = rom_data_even[52]; + assign sel31_even = rom_data_even[53]; + assign cr_bf2fxm_even = rom_data_even[54]; + assign skip_cond_even = rom_data_even[55]; + assign skip_zero_even = rom_data_even[56]; // For when XER = 0 & to help with NB coding + assign skip_nop_even = rom_data_even[57]; + assign loop_addr_even = rom_data_even[58:67]; // ??? In product, can latch loop_begin address instead of keeping in ROM + assign loop_init_even = rom_data_even[68:70]; + assign ep_instr_even = rom_data_even[71]; + + assign template_code_even[0:26] = rom_data_even_late[0:26]; + assign template_code_even[27] = rom_data_even_late[27] | ep_force_even_late_l2; + assign template_code_even[28:31] = rom_data_even_late[28:31]; + + assign sel_even_late_d[0] = sel0_5_even; + assign sel_even_late_d[1:2] = sel6_10_even; + assign sel_even_late_d[3:4] = sel11_15_even; + assign sel_even_late_d[5:6] = sel16_20_even; + assign sel_even_late_d[7:8] = sel21_25_even; + assign sel_even_late_d[9] = sel26_30_even; + assign sel_even_late_d[10] = sel31_even; + assign sel_even_late_d[11] = use_nop_even; + + assign sel0_5_even_late = sel_even_late_l2[0]; + assign sel6_10_even_late = sel_even_late_l2[1:2]; + assign sel11_15_even_late = sel_even_late_l2[3:4]; + assign sel16_20_even_late = sel_even_late_l2[5:6]; + assign sel21_25_even_late = sel_even_late_l2[7:8]; + assign sel26_30_even_late = sel_even_late_l2[9]; + assign sel31_even_late = sel_even_late_l2[10]; + assign use_nop_even_late = sel_even_late_l2[11]; + + assign ep_force_even_late_d = ep_instr_even & force_ep_l2; + + assign ucode_end_even = (uc_end_even | (uc_end_early_even & early_end_l2)) & (~(loop_end_even & (~last_loop_fast))); + + assign fxm = (instr_l2[6:8] == 3'b000) ? 8'b10000000 : + (instr_l2[6:8] == 3'b001) ? 8'b01000000 : + (instr_l2[6:8] == 3'b010) ? 8'b00100000 : + (instr_l2[6:8] == 3'b011) ? 8'b00010000 : + (instr_l2[6:8] == 3'b100) ? 8'b00001000 : + (instr_l2[6:8] == 3'b101) ? 8'b00000100 : + (instr_l2[6:8] == 3'b110) ? 8'b00000010 : + 8'b00000001; + + assign instr_even_late_d[0:10] = instr_l2[0:10]; + assign instr_even_late_d[11:20] = (cr_bf2fxm_even == 1'b0) ? instr_l2[11:20] : + {1'b1, fxm[0:7], 1'b0}; + assign instr_even_late_d[21:31] = instr_l2[21:31]; + + assign uc_instruction_even[0:5] = (sel0_5_even_late == 1'b0) ? template_code_even[0:5] : + instr_even_late_l2[0:5]; + + assign uc_instruction_even[6:10] = (sel6_10_even_late == 2'b00) ? template_code_even[6:10] : + (sel6_10_even_late == 2'b01) ? instr_even_late_l2[6:10] : + (sel6_10_even_late == 2'b10) ? instr_even_late_l2[11:15] : + instr_even_late_l2[16:20]; + + assign uc_instruction_even[11:15] = (sel11_15_even_late == 2'b00) ? template_code_even[11:15] : + (sel11_15_even_late == 2'b01) ? instr_even_late_l2[11:15] : + (sel11_15_even_late == 2'b10) ? instr_even_late_l2[16:20] : + instr_even_late_l2[6:10]; + + assign uc_instruction_even[16:20] = (sel16_20_even_late == 2'b00) ? template_code_even[16:20] : + (sel16_20_even_late == 2'b01) ? instr_even_late_l2[16:20] : + (sel16_20_even_late == 2'b10) ? instr_even_late_l2[6:10] : + instr_even_late_l2[11:15]; + + assign uc_instruction_even[21:25] = (sel21_25_even_late == 2'b00) ? template_code_even[21:25] : + (sel21_25_even_late == 2'b01) ? instr_even_late_l2[21:25] : + instr_even_late_l2[16:20]; + + assign uc_instruction_even[26:30] = (sel26_30_even_late == 1'b0) ? template_code_even[26:30] : + instr_even_late_l2[26:30]; + + assign uc_instruction_even[31] = (sel31_even_late == 1'b0) ? template_code_even[31] : + instr_even_late_l2[31]; + + assign nop = 32'b01100000000000000000000000000000; + assign nop_ext = 4'b0000; + + assign use_nop_even = skip_even; + + assign ucode_instr_even = (use_nop_even_late == 1'b1) ? nop : + uc_instruction_even; + + assign ucode_ext_even = (use_nop_even == 1'b1) ? nop_ext : + ext_even; + + assign ucode_valid[0] = data_valid & (~flush) & (~(skip_even & skip_odd & (~ucode_end))); + // Removed ucode_end_odd term from skip_odd. When we skip on ucode_end_odd (e.g. mtcrf,FXM(7)=0), we still end up with a nop or something on even side. Since uc_ib_done is only 1 bit, it assumes even side was the end. + assign ucode_valid[1] = data_valid & (~flush) & (~skip_odd) & (~ucode_end_even) & (~(loop_end_even & (~last_loop))); // Handles loops with odd # of lines + + assign ucode_ifar_even[42:61] = {rom_addr_l2[1], count_l2, inLoop_l2, instr_l2[6:10], rom_addr_l2[2:8], 1'b0}; + + assign unused[0] = skip_nop_even; + assign unused[1:10] = loop_addr_even; + + //--------------------------------------------------------------------- + // create output instruction - odd + //--------------------------------------------------------------------- + assign uc_end_odd = rom_data_odd[32]; + assign uc_end_early_odd = rom_data_odd[33]; + assign loop_begin_odd = rom_data_odd[34]; + assign loop_end_odd = rom_data_odd[35] & (inLoop_l2 | loop_begin_even); + assign count_src_odd = rom_data_odd[36:38]; // 00: NB(3:4), 01: "000" & 2's comp NB(3:4), 10: mult of 4 & XER(62:63), 11: 2's comp XER(62:63), 100: RT(inverted), 101: NB(0:2) - word mode, 110: XER(57:61) - word mode, 111: loop_init + assign ext_odd[0] = rom_data_odd[39]; // RT -- ??? Can we incorporate into mux selects? + assign ext_odd[1] = rom_data_odd[40]; // S1 + assign ext_odd[2] = rom_data_odd[41]; // S2 + assign ext_odd[3] = rom_data_odd[42]; // S3 + assign sel0_5_odd = rom_data_odd[43]; + assign sel6_10_odd = rom_data_odd[44:45]; + assign sel11_15_odd = rom_data_odd[46:47]; + assign sel16_20_odd = rom_data_odd[48:49]; + assign sel21_25_odd = rom_data_odd[50:51]; + assign sel26_30_odd = rom_data_odd[52]; + assign sel31_odd = rom_data_odd[53]; + assign cr_bf2fxm_odd = rom_data_odd[54]; + assign skip_cond_odd = rom_data_odd[55]; + assign skip_zero_odd = rom_data_odd[56]; // For when XER = 0 & to help with NB coding + assign skip_nop_odd = rom_data_odd[57]; + assign loop_addr_odd = rom_data_odd[58:67]; // ??? In product, can latch loop_begin address instead of keeping in ROM + assign loop_init_odd = rom_data_odd[68:70]; + assign ep_instr_odd = rom_data_odd[71]; + + assign template_code_odd[0:26] = rom_data_odd_late[0:26]; + assign template_code_odd[27] = rom_data_odd_late[27] | ep_force_odd_late_l2; + assign template_code_odd[28:31] = rom_data_odd_late[28:31]; + + assign sel_odd_late_d[0] = sel0_5_odd; + assign sel_odd_late_d[1:2] = sel6_10_odd; + assign sel_odd_late_d[3:4] = sel11_15_odd; + assign sel_odd_late_d[5:6] = sel16_20_odd; + assign sel_odd_late_d[7:8] = sel21_25_odd; + assign sel_odd_late_d[9] = sel26_30_odd; + assign sel_odd_late_d[10] = sel31_odd; + + assign sel0_5_odd_late = sel_odd_late_l2[0]; + assign sel6_10_odd_late = sel_odd_late_l2[1:2]; + assign sel11_15_odd_late = sel_odd_late_l2[3:4]; + assign sel16_20_odd_late = sel_odd_late_l2[5:6]; + assign sel21_25_odd_late = sel_odd_late_l2[7:8]; + assign sel26_30_odd_late = sel_odd_late_l2[9]; + assign sel31_odd_late = sel_odd_late_l2[10]; + + assign ep_force_odd_late_d = ep_instr_odd & force_ep_l2; + + assign ucode_end_odd = (uc_end_odd | (uc_end_early_odd & early_end_l2)) & + (~((loop_end_odd | loop_end_even) & (~last_loop_fast))); + + assign instr_odd_late_d[0:10] = instr_l2[0:10]; + assign instr_odd_late_d[11:20] = (cr_bf2fxm_odd == 1'b0) ? instr_l2[11:20] : + {1'b1, fxm[0:7], 1'b0}; + assign instr_odd_late_d[21:31] = instr_l2[21:31]; + + assign uc_instruction_odd[0:5] = (sel0_5_odd_late == 1'b0) ? template_code_odd[0:5] : + instr_odd_late_l2[0:5]; + + assign uc_instruction_odd[6:10] = (sel6_10_odd_late == 2'b00) ? template_code_odd[6:10] : + (sel6_10_odd_late == 2'b01) ? instr_odd_late_l2[6:10] : + (sel6_10_odd_late == 2'b10) ? instr_odd_late_l2[11:15] : + instr_odd_late_l2[16:20]; + + assign uc_instruction_odd[11:15] = (sel11_15_odd_late == 2'b00) ? template_code_odd[11:15] : + (sel11_15_odd_late == 2'b01) ? instr_odd_late_l2[11:15] : + (sel11_15_odd_late == 2'b10) ? instr_odd_late_l2[16:20] : + instr_odd_late_l2[6:10]; + + assign uc_instruction_odd[16:20] = (sel16_20_odd_late == 2'b00) ? template_code_odd[16:20] : + (sel16_20_odd_late == 2'b01) ? instr_odd_late_l2[16:20] : + (sel16_20_odd_late == 2'b10) ? instr_odd_late_l2[6:10] : + instr_odd_late_l2[11:15]; + + assign uc_instruction_odd[21:25] = (sel21_25_odd_late == 2'b00) ? template_code_odd[21:25] : + (sel21_25_odd_late == 2'b01) ? instr_odd_late_l2[21:25] : + instr_odd_late_l2[16:20]; + + assign uc_instruction_odd[26:30] = (sel26_30_odd_late == 1'b0) ? template_code_odd[26:30] : + instr_odd_late_l2[26:30]; + + assign uc_instruction_odd[31] = (sel31_odd_late == 1'b0) ? template_code_odd[31] : + instr_odd_late_l2[31]; + + assign ucode_instr_odd = uc_instruction_odd; + + assign ucode_ext_odd = ext_odd; + + assign unused[11] = loop_begin_odd; + assign unused[12] = skip_zero_odd; + assign unused[13:15] = loop_init_odd; + assign unused[16] = loop_addr_odd[9]; + + //--------------------------------------------------------------------- + // combine even & odd info + //--------------------------------------------------------------------- + assign loop_begin = loop_begin_even; + assign loop_end = loop_end_odd | loop_end_even; + assign count_src = (inLoop_l2 == 1'b1) ? count_src_odd : + count_src_even; + assign skip_zero = skip_zero_even; + assign loop_addr = loop_addr_odd[0:8]; + assign loop_init = loop_init_even; + + assign ucode_end = ucode_end_even | ucode_end_odd; + assign uc_end = ucode_end & data_valid; + + //--------------------------------------------------------------------- + // control, state machines + //--------------------------------------------------------------------- + // Old Assumptions: + // ??? No Nested Loops + // ??? All Loops must have at least 2 instructions?? + // ??? New ucode instructions will be held off until XU flushes IU (to next instruction) on this thread + // ??? If loop_end is skip_c, the instruction before loop_end must also be skip_c + // + // New Assumptions: + // ??? No Nested Loops + // ??? Loops can have only 1 instruction + // ??? uCode cannot end in the same row as loop_begin + // ??? If loop_end is skip_c, the instruction before loop_end must also be skip_c + // ??? Loops must begin on an even address + // ??? Loops can end on an even address, but loop_address must be written in the odd side (loop_address_odd) + // ??? We can skip nop lines. They must be in the odd side, and marked skip_nop + assign inLoop_d = (flush_into_uc == 1'b1) ? flush_ifar[48] : + (new_command == 1'b1) ? 1'b0 : // clear when beginning + (((data_valid & loop_begin) | inLoop_l2) & (~((data_valid & loop_end) & last_loop)) & valid_l2); + + assign last_loop = (count_l2 == 5'b00000 & inLoop_l2) | + (loop_begin & count_init == 5'b00000) | + (skip_zero & loop_begin & count_init == 5'b00001) | + (skip_zero_l2 & count_l2 == 5'b00001) | + (skip_cond_odd & loop_end_odd & cond_l2) | + (skip_cond_even & loop_end_even & cond_l2); // ??? Could remove this line if timing bad + + // only for uc_end: never have loop_begin & uc_end in same rom line + assign last_loop_fast = (count_l2 == 5'b00000 & inLoop_l2) | + (skip_zero_l2 & count_l2 == 5'b00001) | + (skip_cond_odd & loop_end_odd & cond_l2) | + (skip_cond_even & loop_end_even & cond_l2); + + assign loopback = data_valid & loop_end & (~last_loop); + + assign inc_RT = data_valid & loop_end & (~(skip_zero_l2 & count_l2 == 5'b00000 & (~loop_begin))) & + (~(skip_zero & loop_begin & count_init == 5'b00000)) & + count_src[0] & (~(count_src == 3'b111)); // load/store multiple & string op word loops + + assign NB_dec = instr_l2[16:20] - 5'b00001; + // when NB(3:4) = 00 -> 00, 01 -> 11, 10 -> 10, 11 -> 01 + assign NB_comp[0] = instr_l2[19] ^ instr_l2[20]; + assign NB_comp[1] = instr_l2[20]; + + assign xer_act = flush_into_uc | xu_iu_ucode_xer_val; + assign xu_iu_ucode_xer_d = (flush_into_uc == 1'b1) ? oldest_xer : + xu_iu_ucode_xer; + assign xu_iu_ucode_xer_val_d = xu_iu_ucode_xer_val & (~flush) & (~br_hold); // flush term avoids problems with cplbuffer + + assign XER_dec_z = (xu_iu_ucode_xer_l2[57:63] == 7'b0) ? 7'b0000000 : + xu_iu_ucode_xer_l2[57:63] - 7'b0000001; + assign XER_low = (XER_dec_z[5:6] == 2'b11) ? 3'b100 : + {1'b0, xu_iu_ucode_xer_l2[62:63]}; + assign XER_comp[0] = xu_iu_ucode_xer_l2[62] ^ xu_iu_ucode_xer_l2[63]; + assign XER_comp[1] = xu_iu_ucode_xer_l2[63]; + + assign count_init = (count_src == 3'b000) ? {3'b000, NB_dec[3:4]} : + (count_src == 3'b001) ? {3'b000, NB_comp[0:1]} : + (count_src == 3'b010) ? {2'b00, XER_low} : + (count_src == 3'b011) ? {3'b000, XER_comp[0:1]} : + (count_src == 3'b100) ? (~(instr_l2[6:10])) : // RT + (count_src == 3'b101) ? {2'b00, NB_dec[0:2]} : + (count_src == 3'b110) ? XER_dec_z[0:4] : + {2'b00, loop_init}; + + assign count_d = (flush_into_uc == 1'b1) ? flush_ifar[43:47] : + ((data_valid & loop_begin & (~inLoop_l2) & loop_end) == 1'b1) ? count_init - 5'b00001 : + ((data_valid & loop_begin & (~inLoop_l2)) == 1'b1) ? count_init : + ((data_valid & loop_end) == 1'b1) ? count_l2 - 5'b00001 : + count_l2; + + assign skip_zero_d = (((data_valid & loop_end & last_loop) | new_command | flush_into_uc) == 1'b1) ? 1'b0 : // added last_loop to handle 2 instruction loops in lswi,lswx + ((data_valid & loop_begin) == 1'b1) ? skip_zero : + skip_zero_l2; + + // ??? If we always read each cycle, could we just do: skip_to_np1_d <- flush_into_uc and np1_flush? + assign skip_to_np1_d = (flush == 1'b1) ? flush_into_uc & np1_flush : + (data_valid == 1'b1) ? 1'b0 : + skip_to_np1_l2; + + assign skip_even = (((skip_zero & loop_begin) | skip_zero_l2) & (count_l2 == 5'b00000) & inLoop_l2) | + ( (skip_zero & loop_begin) & count_init == 5'b00000 & (~inLoop_l2)) | + (skip_cond_even & cond_l2) | + (fxm_type_l2 & instr_l2[12] == 1'b0) | + flush_to_odd_l2 | + skip_to_np1_l2; + + assign skip_odd = (((skip_zero & loop_begin) | skip_zero_l2) & (count_l2 == 5'b00000) & inLoop_l2) | + ( (skip_zero & loop_begin) & count_init == 5'b00000 & (~inLoop_l2)) | + (skip_cond_odd & cond_l2) | + (fxm_type_l2 & instr_l2[13] == 1'b0) | + skip_nop_odd | + (flush_to_odd_l2 & skip_to_np1_l2); + + //--------------------------------------------------------------------- + // Buffer old instructions until they complete + //--------------------------------------------------------------------- + assign buff_instr_in = {instr_l2[0:5], early_end_l2, cond_l2, force_ep_l2, rom_addr_l2[0:1], instr_l2[11:31]}; + + assign cplbuffer_xer_act = ( wait_for_xer_l2 & xu_iu_ucode_xer_val_l2) | + ((~wait_for_xer_l2) & new_command & xer_type & (xer_val_occurred_l2 | xu_iu_ucode_xer_val_l2)); + + // Flush_into_uc requirements: + // -- signal active for only 1 cycle + // -- flush_into_uc can only occur if we have a non-completed uCode instruction + // -- flush_into_uc must not occur on fxm_type instr (we don't keep around instr_l2(12:19) in ifar) + iuq_uc_cplbuffer iuq_uc_cplbuffer0( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .pc_iu_func_sl_thold_0_b(pc_iu_func_sl_thold_0_b), + .pc_iu_sg_0(pc_iu_sg_0), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scan_in(buff_scan_in), + .scan_out(buff_scan_out), + .cp_uc_credit_free(cp_uc_credit_free), + .flush(cp_flush), + .flush_into_uc(flush_into_uc), + .new_command(new_command), + .flush_next(flush_next), + .valid_l2(valid_l2), + .flush_current(flush), + .buff_instr_in(buff_instr_in), + .cplbuffer_xer_act(cplbuffer_xer_act), + .wait_for_xer_l2(wait_for_xer_l2), + .xu_iu_ucode_xer_l2(xu_iu_ucode_xer_l2), + .cplbuffer_full(cplbuffer_full_int), + .oldest_instr(oldest_instr), + .oldest_xer(oldest_xer) + ); + + assign cplbuffer_full = cplbuffer_full_int; + + //--------------------------------------------------------------------- + // Latches + //--------------------------------------------------------------------- + + tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(0)) xu_iu_ucode_xer_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xer_act), // ??? If change, make sure xer bugspray is still accurate + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[xu_iu_ucode_xer_offset:xu_iu_ucode_xer_offset + 7 - 1]), + .scout(sov[xu_iu_ucode_xer_offset:xu_iu_ucode_xer_offset + 7 - 1]), + .din(xu_iu_ucode_xer_d), + .dout(xu_iu_ucode_xer_l2) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(0)) xu_iu_ucode_xer_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(uc_default_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[xu_iu_ucode_xer_val_offset]), + .scout(sov[xu_iu_ucode_xer_val_offset]), + .din(xu_iu_ucode_xer_val_d), + .dout(xu_iu_ucode_xer_val_l2) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(0)) wait_for_xer_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(uc_default_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[wait_for_xer_offset]), + .scout(sov[wait_for_xer_offset]), + .din(wait_for_xer_d), + .dout(wait_for_xer_l2) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(0)) xer_val_occurred_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[xer_val_occurred_offset]), + .scout(sov[xer_val_occurred_offset]), + .din(xer_val_occurred_d), + .dout(xer_val_occurred_l2) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(uc_default_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[valid_offset]), + .scout(sov[valid_offset]), + .din(valid_d), + .dout(valid_l2) + ); + + tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(0)) instr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(uc_control_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[instr_offset:instr_offset + 32 - 1]), + .scout(sov[instr_offset:instr_offset + 32 - 1]), + .din(instr_d), + .dout(instr_l2) + ); + + tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(0)) instr_even_late_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(data_valid), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[instr_even_late_offset:instr_even_late_offset + 32 - 1]), + .scout(sov[instr_even_late_offset:instr_even_late_offset + 32 - 1]), + .din(instr_even_late_d), + .dout(instr_even_late_l2) + ); + + tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(0)) instr_odd_late_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(data_valid), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[instr_odd_late_offset:instr_odd_late_offset + 32 - 1]), + .scout(sov[instr_odd_late_offset:instr_odd_late_offset + 32 - 1]), + .din(instr_odd_late_d), + .dout(instr_odd_late_l2) + ); + + tri_rlmreg_p #(.WIDTH(12), .INIT(0), .NEEDS_SRESET(0)) sel_even_late_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(data_valid), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[sel_even_late_offset:sel_even_late_offset + 12 - 1]), + .scout(sov[sel_even_late_offset:sel_even_late_offset + 12 - 1]), + .din(sel_even_late_d), + .dout(sel_even_late_l2) + ); + + tri_rlmreg_p #(.WIDTH(11), .INIT(0), .NEEDS_SRESET(0)) sel_odd_late_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(data_valid), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[sel_odd_late_offset:sel_odd_late_offset + 11 - 1]), + .scout(sov[sel_odd_late_offset:sel_odd_late_offset + 11 - 1]), + .din(sel_odd_late_d), + .dout(sel_odd_late_l2) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) early_end_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(uc_control_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[early_end_offset]), + .scout(sov[early_end_offset]), + .din(early_end_d), + .dout(early_end_l2) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cond_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(uc_control_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[cond_offset]), + .scout(sov[cond_offset]), + .din(cond_d), + .dout(cond_l2) + ); + + tri_rlmreg_p #(.WIDTH(9), .INIT(0), .NEEDS_SRESET(0)) rom_addr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(uc_control_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rom_addr_offset:rom_addr_offset + 9 - 1]), + .scout(sov[rom_addr_offset:rom_addr_offset + 9 - 1]), + .din(rom_addr_d), + .dout(rom_addr_l2) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) flush_to_odd_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(uc_control_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[flush_to_odd_offset]), + .scout(sov[flush_to_odd_offset]), + .din(flush_to_odd_d), + .dout(flush_to_odd_l2) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(0)) count_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(uc_control_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[count_offset:count_offset + 5 - 1]), + .scout(sov[count_offset:count_offset + 5 - 1]), + .din(count_d), + .dout(count_l2) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) inloop_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(uc_control_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[inloop_offset]), + .scout(sov[inloop_offset]), + .din(inLoop_d), + .dout(inLoop_l2) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) skip_zero_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(uc_control_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[skip_zero_offset]), + .scout(sov[skip_zero_offset]), + .din(skip_zero_d), + .dout(skip_zero_l2) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) skip_to_np1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(uc_control_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[skip_to_np1_offset]), + .scout(sov[skip_to_np1_offset]), + .din(skip_to_np1_d), + .dout(skip_to_np1_l2) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) force_ep_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(uc_control_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[force_ep_offset]), + .scout(sov[force_ep_offset]), + .din(force_ep_d), + .dout(force_ep_l2) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) fxm_type_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(uc_control_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[fxm_type_offset]), + .scout(sov[fxm_type_offset]), + .din(fxm_type_d), + .dout(fxm_type_l2) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ep_force_even_late_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(data_valid), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[ep_force_even_late_offset]), + .scout(sov[ep_force_even_late_offset]), + .din(ep_force_even_late_d), + .dout(ep_force_even_late_l2) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ep_force_odd_late_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(data_valid), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[ep_force_odd_late_offset]), + .scout(sov[ep_force_odd_late_offset]), + .din(ep_force_odd_late_d), + .dout(ep_force_odd_late_l2) + ); + + //--------------------------------------------------------------------- + // Scan + //--------------------------------------------------------------------- + assign siv[0:scan_right] = {sov[1:scan_right], scan_in}; + assign buff_scan_in = sov[0]; + assign scan_out = buff_scan_out; + +endmodule diff --git a/dev/verilog/work/iuq_uc_cplbuffer.v b/dev/verilog/work/iuq_uc_cplbuffer.v new file mode 100755 index 0000000..e70790b --- /dev/null +++ b/dev/verilog/work/iuq_uc_cplbuffer.v @@ -0,0 +1,345 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//******************************************************************** +//* +//* TITLE: Microcode Completion Buffer +//* +//* NAME: iuq_uc_cplbuffer.v +//* +//********************************************************************* + +`include "tri_a2o.vh" + + +module iuq_uc_cplbuffer( + vdd, + gnd, + nclk, + pc_iu_func_sl_thold_0_b, + pc_iu_sg_0, + force_t, + d_mode, + delay_lclkr, + mpw1_b, + mpw2_b, + scan_in, + scan_out, + cp_uc_credit_free, + flush, + flush_into_uc, + new_command, + flush_next, + valid_l2, + flush_current, + buff_instr_in, + cplbuffer_xer_act, + wait_for_xer_l2, + xu_iu_ucode_xer_l2, + cplbuffer_full, + oldest_instr, + oldest_xer +); + + + inout vdd; + + inout gnd; + + (* pin_data="PIN_FUNCTION=/G_CLK/" *) + input [0:`NCLK_WIDTH-1] nclk; + input pc_iu_func_sl_thold_0_b; + input pc_iu_sg_0; + input force_t; + input d_mode; + input delay_lclkr; + input mpw1_b; + input mpw2_b; + + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + input scan_in; + + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + output scan_out; + + input cp_uc_credit_free; + input flush; + input flush_into_uc; + input new_command; + input flush_next; + input valid_l2; + input flush_current; + input [0:31] buff_instr_in; + input cplbuffer_xer_act; + input wait_for_xer_l2; + input [57:63] xu_iu_ucode_xer_l2; + + output cplbuffer_full; + output reg [0:31] oldest_instr; + output reg [57:63] oldest_xer; + + // iuq_uc_cplbuffer + + localparam [0:31] value_1 = 32'h00000001; + localparam [0:31] value_2 = 32'h00000002; + + parameter buffer_width = 32; + parameter buffer_depth = 8; // NOTE: If this changes, change cplbuffer_full logic + parameter buffer_depth_log = 3; + parameter xer_width = 7; + + parameter buffer_count_offset = 0; + parameter buffer_offset = buffer_count_offset + buffer_depth_log + 1; + parameter xer_offset = buffer_offset + buffer_depth * buffer_width; + parameter read_ptr_offset = xer_offset + buffer_depth * xer_width; + parameter write_ptr_offset = read_ptr_offset + buffer_depth_log; + parameter new_command_offset = write_ptr_offset + buffer_depth_log; + parameter scan_right = new_command_offset + 1 - 1; + + + wire [0:buffer_depth_log] buffer_count_d; + wire [0:buffer_depth_log] buffer_count_l2; + reg [0:buffer_width-1] buffer_d[0:buffer_depth-1]; + wire [0:buffer_width-1] buffer_l2[0:buffer_depth-1]; + reg [57:63] xer_d[0:buffer_depth-1]; + wire [57:63] xer_l2[0:buffer_depth-1]; + wire [0:buffer_depth_log-1] read_ptr_d; + wire [0:buffer_depth_log-1] read_ptr_l2; + wire [0:buffer_depth_log-1] write_ptr_d; + wire [0:buffer_depth_log-1] write_ptr_l2; + wire new_command_d; + wire new_command_l2; + + wire [0:buffer_depth_log-1] xer_write_ptr; + wire [0:1] buffer_act; + wire ptr_act; + wire cplbuffer_full_int; + + wire tiup; + + // scan + wire [0:scan_right] siv; + wire [0:scan_right] sov; + + assign tiup = 1'b1; + assign new_command_d = new_command & (~(flush_next)); + + assign buffer_count_d = (flush_into_uc == 1'b1) ? value_1[31-buffer_depth_log:31] : + (flush == 1'b1) ? {(buffer_depth_log+1){1'b0}} : //cp_flush + (new_command_l2 == 1'b0 & (flush_current & valid_l2) == 1'b1 & cp_uc_credit_free == 1'b1) ? buffer_count_l2 - value_2[31-buffer_depth_log:31] : + (new_command_l2 == 1'b0 & (flush_current & valid_l2) == 1'b1 & cp_uc_credit_free == 1'b0) ? buffer_count_l2 - value_1[31-buffer_depth_log:31] : + (new_command_l2 == 1'b0 & (flush_current & valid_l2) == 1'b0 & cp_uc_credit_free == 1'b1) ? buffer_count_l2 - value_1[31-buffer_depth_log:31] : + (new_command_l2 == 1'b1 & (flush_current & valid_l2) == 1'b1 & cp_uc_credit_free == 1'b1) ? buffer_count_l2 - value_1[31-buffer_depth_log:31] : + (new_command_l2 == 1'b1 & (flush_current & valid_l2) == 1'b0 & cp_uc_credit_free == 1'b0) ? buffer_count_l2 + value_1[31-buffer_depth_log:31] : + buffer_count_l2; + + assign read_ptr_d = (cp_uc_credit_free == 1'b1) ? read_ptr_l2 + value_1[32-buffer_depth_log:31] : + read_ptr_l2; + + assign write_ptr_d = (flush_into_uc == 1'b1) ? read_ptr_l2 + value_1[32-buffer_depth_log:31] : + (flush == 1'b1) ? read_ptr_l2 : + (new_command_l2 == 1'b1 & ((flush_current & valid_l2) == 1'b0)) ? write_ptr_l2 + value_1[32-buffer_depth_log:31] : + (new_command_l2 == 1'b0 & ((flush_current & valid_l2) == 1'b1)) ? write_ptr_l2 - value_1[32-buffer_depth_log:31] : + write_ptr_l2; + + generate + begin : gen_buff + genvar i; + for (i = 0; i < buffer_depth; i = i + 1) + begin : buff_loop + wire [0:buffer_depth_log-1] index=i; + always @ (write_ptr_l2 or index or buff_instr_in or buffer_l2[i] or + xer_write_ptr or xu_iu_ucode_xer_l2 or xer_l2[i]) + begin + buffer_d[i] = (write_ptr_l2 == index) ? buff_instr_in : + buffer_l2[i]; + xer_d[i] = (xer_write_ptr == index) ? xu_iu_ucode_xer_l2 : + xer_l2[i]; + end + end + end + endgenerate + + always @ (*) + begin : read_mux + + //(* analysis_not_referenced="true" *) + + integer i; + oldest_instr = 32'b0; + oldest_xer = 7'b0; + for (i = 0; i < buffer_depth; i = i + 1) + begin : read_mux_loop + if (read_ptr_l2 == i[buffer_depth_log-1:0]) + begin + oldest_instr = buffer_l2[i]; + oldest_xer = xer_l2[i]; + end + end + end + + assign xer_write_ptr = (wait_for_xer_l2 == 1'b1) ? write_ptr_l2 - value_1[32-buffer_depth_log:31] : // when xer comes after new_command + write_ptr_l2; // when xer valid with new_command + + assign cplbuffer_full_int = (buffer_count_l2[1:2] == 2'b11); + assign cplbuffer_full = cplbuffer_full_int; + + assign buffer_act[0] = new_command_l2 & (~write_ptr_l2[0]); + assign buffer_act[1] = new_command_l2 & write_ptr_l2[0]; + + assign ptr_act = flush_into_uc | flush | new_command_l2 | cp_uc_credit_free | flush_current; + + //--------------------------------------------------------------------- + // Latches + //--------------------------------------------------------------------- + + tri_rlmreg_p #(.WIDTH(buffer_depth_log+1), .INIT(0)) buffer_count_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ptr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[buffer_count_offset:buffer_count_offset + (buffer_depth_log+1) - 1]), + .scout(sov[buffer_count_offset:buffer_count_offset + (buffer_depth_log+1) - 1]), + .din(buffer_count_d), + .dout(buffer_count_l2) + ); + + generate + begin + genvar i; + for (i = 0; i < buffer_depth; i = i + 1) + begin : gen_b + tri_rlmreg_p #(.WIDTH(buffer_width), .INIT(0)) buffer_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(buffer_act[i/(buffer_depth/2)]), // only clock half of buffers at a time + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[buffer_offset + i * buffer_width:buffer_offset + (i + 1) * buffer_width - 1]), + .scout(sov[buffer_offset + i * buffer_width:buffer_offset + (i + 1) * buffer_width - 1]), + .din(buffer_d[i]), + .dout(buffer_l2[i]) + ); + + tri_rlmreg_p #(.WIDTH(xer_width), .INIT(0)) xer_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cplbuffer_xer_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[xer_offset + i * xer_width:xer_offset + (i + 1) * xer_width - 1]), + .scout(sov[xer_offset + i * xer_width:xer_offset + (i + 1) * xer_width - 1]), + .din(xer_d[i]), + .dout(xer_l2[i]) + ); + end + end + endgenerate + + tri_rlmreg_p #(.WIDTH(buffer_depth_log), .INIT(0)) read_ptr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ptr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[read_ptr_offset:read_ptr_offset + buffer_depth_log - 1]), + .scout(sov[read_ptr_offset:read_ptr_offset + buffer_depth_log - 1]), + .din(read_ptr_d), + .dout(read_ptr_l2) + ); + + tri_rlmreg_p #(.WIDTH(buffer_depth_log), .INIT(0)) write_ptr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ptr_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[write_ptr_offset:write_ptr_offset + buffer_depth_log - 1]), + .scout(sov[write_ptr_offset:write_ptr_offset + buffer_depth_log - 1]), + .din(write_ptr_d), + .dout(write_ptr_l2) + ); + + tri_rlmlatch_p #(.INIT(0)) new_command_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[new_command_offset]), + .scout(sov[new_command_offset]), + .din(new_command_d), + .dout(new_command_l2) + ); + + //--------------------------------------------------------------------- + // Scan + //--------------------------------------------------------------------- + assign siv[0:scan_right] = {sov[1:scan_right], scan_in}; + assign scan_out = sov[0]; + +endmodule diff --git a/dev/verilog/work/iuq_uc_rom_even.v b/dev/verilog/work/iuq_uc_rom_even.v new file mode 100755 index 0000000..0e77bdd --- /dev/null +++ b/dev/verilog/work/iuq_uc_rom_even.v @@ -0,0 +1,2231 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//******************************************************************** +//* +//* TITLE: IU Microcode Code +//* +//* NAME: iuq_uc_rom_even.v +//* +//********************************************************************* + +`include "tri_a2o.vh" + + +module iuq_uc_rom_even( + vdd, + gnd, + nclk, + pc_iu_func_sl_thold_0_b, + pc_iu_sg_0, + force_t, + d_mode, + delay_lclkr, + mpw1_b, + mpw2_b, + scan_in, + scan_out, + rom_act, + rom_addr, + rom_data +); + //parameter ucode_width = 72; + + + inout vdd; + + inout gnd; + + (* pin_data ="PIN_FUNCTION=/G_CLK/" *) + input [0:`NCLK_WIDTH-1] nclk; + input pc_iu_func_sl_thold_0_b; + input pc_iu_sg_0; + input force_t; + input d_mode; + input delay_lclkr; + input mpw1_b; + input mpw2_b; + input scan_in; + output scan_out; + + input rom_act; + input [0:9] rom_addr; + output [0:71] rom_data; + + //@@ Signal Declarations + wire [1:225] rom_instr_pt; + wire [0:2] count_src; + wire cr_bf2fxm; + wire ep; + wire ext_rt; + wire ext_s1; + wire ext_s2; + wire ext_s3; + wire [0:9] loop_addr; + wire loop_begin; + wire loop_end; + wire [0:2] loop_init; + wire sel0_5; + wire [0:1] sel11_15; + wire [0:1] sel16_20; + wire [0:1] sel21_25; + wire sel26_30; + wire sel31; + wire [0:1] sel6_10; + wire skip_cond; + wire skip_nop; + wire skip_zero; + wire [0:31] template; + wire ucode_end; + wire ucode_end_early; + + parameter rom_addr_offset = 0; + parameter scan_right = rom_addr_offset + 10 - 1; + + // Latches + wire [0:9] rom_addr_d; + wire [0:9] rom_addr_l2; + wire [0:scan_right] siv; + wire [0:scan_right] sov; + +//64-bit core +//c64: if (regmode = 6) generate begin + +/* +//table_start +?TABLE rom_instr LISTING(final) OPTIMIZE PARMS(ON-SET, OFF-SET); +*INPUTS*========*OUTPUTS*===============================================================================================* +| | | +| rom_addr_l2 | template ucode_end | +| | | | | ucode_end_early | +| | | | | | loop_begin | +| | | | | | | loop_end | +| | | | | | | | count_src | -- Can DC if not (loop_begin or loop_end) +| | | | | | | | | | +| | | | | | | | | ext_rt | +| | | | | | | | | | ext_s1 | +| | | | | | | | | | | ext_s2 | +| | | | | | | | | | | | ext_s3 | +| | | | | | | | | | | | | | +| | | | | | | | | | | | | sel0_5 | +| | | | | | | | | | | | | | sel6_10 | +| | | | | | | | | | | | | | | sel11_15 | +| | | | | | | | | | | | | | | | sel16_20 | +| | | | | | | | | | | | | | | | | sel21_25 | +| | | | | | | | | | | | | | | | | | sel26_30 | +| | | | | | | | | | | | | | | | | | | sel31 | +| | | | | | | | | | | | | | | | | | | | | +| | | | | | | | | | | | | | | | | | | | cr_bf2fxm | +| | | | | | | | | | | | | | | | | | | | | skip_cond | +| | | | | | | | | | | | | | | | | | | | | | skip_zero | -- Can DC if loop_begin not set +| | | | | | | | | | | | | | | | | | | | | | | skip_nop | -- Optimize to only be in odd side +| | | | | | | | | | | | | | | | | | | | | | | | loop_addr | -- Can DC if loop_end not set; always odd side +| | | | | | | | | | | | | | | | | | | | | | | | | loop_init| -- 1 less than # of times to loop; Can DC if not loop_begin or not count_src=111 +| | | | | | | | | | | | | | | | | | | | | | | | | | ep | +| | | | 1111111111222222222233 | | | | | | | | | | | | | | | | | | | | | | | | +| 0123456789 | 01234567890123456789012345678901 | | | | 012 | | | | | 01 01 01 01 | | | | | | 0123456789 012 | | +*TYPE*==========+=======================================================================================================+ +| PPPPPPPPPP | SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS S S S S SSS S S S S S SS SS SS SS S S S S S S SSSSSSSSSS SSS S | +*OPTIMIZE*----->| AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA B B B B CCC X X X X X XX XX XX XX X X X X X X XXXXXXXXXX XYX X | +*TERMS*=========+=======================================================================================================+ +| 0000000000 | 00111000000--------------------- 0 0 0 - --- 1 0 - - 0 00 01 01 01 1 1 0 0 - 0 ---------- --- - | # addi s0,RA,D -lhz,lhzu +| 0000000010 | 10001000010000000000000000000001 0 0 0 - --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # lbz s2,1(s0) +| 0000000100 | 01010100010000100100010000101110 0 0 0 - --- 1 1 - - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- - | # rlwinm s2,s2,8,16,23 -skip_c +| 0000000110 | 01101000010-----0000000000000000 0 1 0 - --- 0 1 - - 0 00 11 00 00 0 0 0 0 - 0 ---------- --- - | # xori RT,s2,0 -end for non-update + +| 0000010000 | 011111-----00000-----00000111000 0 0 0 - --- 1 0 0 - 0 11 00 01 00 0 0 0 0 - 0 ---------- --- 0 | # and s0,RB,RB -lhzx,lhzux,lhbrx +| 0000010010 | 00111000011000000000000000000001 0 0 0 - --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- 0 | # addi s3,s0,1 +| 0000010100 | 01010000001000100100010000101110 0 0 0 - --- 1 1 1 - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- 0 | # rlwimi s2,s1,8,16,23 +| 0000010110 | 01111100010000100000101101111000 0 0 0 - --- 1 1 1 - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- 0 | # or s2,s2,s1 -skip_c +| 0000011000 | 011111----------0000001000010100 1 - 0 - --- 0 0 1 - 0 10 01 00 00 0 0 0 0 - 0 ---------- --- 0 | # add RA,RA,s0 + +| 0000100000 | 00111000000--------------------- 0 0 0 - --- 1 0 - - 0 00 01 01 01 1 1 0 0 - 0 ---------- --- - | # addi s0,RA,D -lha,lhau +| 0000100010 | 10001000010000000000000000000001 0 0 0 - --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # lbz s2,1(s0) +| 0000100100 | 01010100010000100100010000101110 0 0 0 - --- 1 1 - - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- - | # rlwinm s2,s2,8,16,23 -skip_c +| 0000100110 | 01111100010----------11100110100 0 1 0 - --- 0 1 - - 0 00 11 -- 00 0 0 0 0 - 0 ---------- --- - | # extsh RT,s2 -end for non-update + +| 0000110000 | 00111000000-----0000000000000000 0 0 0 - --- 1 0 - - 0 00 01 00 00 0 0 0 0 - 0 ---------- --- - | # addi s0,RA,0 -lhax,lhaux +| 0000110010 | 10001000001000000000000000000000 0 0 0 - --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # lbz s1,0(s0) +| 0000110100 | 01010000001000100100010000101110 0 0 0 - --- 1 1 1 - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # rlwimi s2,s1,8,16,23 +| 0000110110 | 01111100010000100000101101111000 0 0 0 - --- 1 1 1 - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- - | # or s2,s2,s1 -skip_c +| 0000111000 | 01101000000-----0000000000000000 1 - 0 - --- 0 1 - - 0 00 01 00 00 0 0 0 0 - 0 ---------- --- - | # xori RA,s0,0 + +| 0001000000 | 00111000000--------------------- 0 0 0 - --- 1 0 - - 0 00 01 01 01 1 1 0 0 - 0 ---------- --- - | # addi s0,RA,D -lwz,lwzu +| 0001000010 | 00111000000000000000000000000001 0 0 1 0 111 1 1 - - 0 00 00 00 00 0 0 0 0 0 0 ---------- 010 - | # addi s0,s0,1 -loop_begin,cnt=3 +| 0001000100 | 10001000001000000000000000000000 0 0 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # lbz s1,0(s0) +| 0001000110 | 01010100010000100100000000111110 0 0 0 - --- 1 1 - - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- - | # rlwinm s2,s2,8,0,31 -skip_c +| 0001001000 | 01010000001000101100000000001110 0 0 0 - --- 1 1 1 - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- - | # rlwimi s2,s1,24,0,7 -skip_c +| 0001001010 | 001110-------------------------- 1 - 0 - --- 0 0 - - 0 10 01 01 01 1 1 0 0 - 0 ---------- --- - | # addi RA,RA,D + +| 0001010000 | 011111-----00000-----00000111000 0 0 0 - --- 1 0 0 - 0 11 00 01 00 0 0 0 0 - 0 ---------- --- 0 | # and s0,RB,RB -lwzx,lwzux,lwbrx +| 0001010010 | 00111000000000000000000000000001 0 0 1 0 111 1 1 - - 0 00 00 00 00 0 0 0 0 0 0 ---------- 010 0 | # addi s0,s0,1 -loop_begin,cnt=3 +| 0001010100 | 01111100001-----000000001010111- 0 0 0 0 --- 1 0 1 - 0 00 01 00 00 0 - 0 0 - 0 ---------- --- 1 | # lbzx s1,RA,s0 +| 0001010110 | 01010100010000100100000000111110 0 0 0 - --- 1 1 - - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- 0 | # rlwinm s2,s2,8,0,31 -skip_c +| 0001011000 | 01010000001000101100000000001110 0 0 0 - --- 1 1 1 - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- 0 | # rlwimi s2,s1,24,0,7 -skip_c +| 0001011010 | 00111000001-----1111111111111101 0 - 0 - --- 1 0 - - 0 00 01 00 00 0 0 0 0 - 0 ---------- --- 0 | # addi s1,RA,-3 + +| 0001100000 | 00111000000-----1111111111111110 0 - 0 - --- 1 0 - - 0 00 01 00 00 0 0 0 0 - 0 ---------- --- - | # addi s0,RA,-2 -lwa +| 0001100010 | 00111000000000000000000000000001 0 - 1 0 111 1 1 - - 0 00 00 00 00 0 0 0 0 0 0 ---------- 010 - | # addi s0,s0,1 -loop_begin,cnt=3 +| 0001100100 | 1000100000100000---------------- 0 - 0 0 --- 1 1 - - 0 00 00 01 01 1 1 0 0 - 0 ---------- --- - | # lbz s1,D(s0) +| 0001100110 | 01010100010000100100000000111110 0 - 0 - --- 1 1 - - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- - | # rlwinm s2,s2,8,0,31 -skip_c +| 0001101000 | 01010000001000101100000000001110 0 - 0 - --- 1 1 1 - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- - | # rlwimi s2,s1,24,0,7 -skip_c + +| 0001110000 | 011111-----00000-----00000111000 0 0 0 - --- 1 0 0 - 0 11 00 01 00 0 0 0 0 - 0 ---------- --- - | # and s0,RB,RB -lwax,lwaux +| 0001110010 | 00111000000000000000000000000001 0 0 1 0 111 1 1 - - 0 00 00 00 00 0 0 0 0 0 0 ---------- 010 - | # addi s0,s0,1 -loop_begin,cnt=3 +| 0001110100 | 01111100001-----000000001010111- 0 0 0 0 --- 1 0 1 - 0 00 01 00 00 0 - 0 0 - 0 ---------- --- - | # lbzx s1,RA,s0 +| 0001110110 | 01010100010000100100000000111110 0 0 0 - --- 1 1 - - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- - | # rlwinm s2,s2,8,0,31 -skip_c +| 0001111000 | 01010000001000101100000000001110 0 0 0 - --- 1 1 1 - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- - | # rlwimi s2,s1,24,0,7 -skip_c +| 0001111010 | 00111000001-----1111111111111101 0 - 0 - --- 1 0 - - 0 00 01 00 00 0 0 0 0 - 0 ---------- --- - | # addi s1,RA,-3 + +| 0010000000 | 00111000000--------------------0 0 0 0 - --- 1 0 - - 0 00 01 01 01 1 0 0 0 - 0 ---------- --- - | # addi s0,RA,DS -ld,ldu +| 0010000010 | 00111000000000000000000000000001 0 0 1 0 111 1 1 - - 0 00 00 00 00 0 0 0 0 0 0 ---------- 110 - | # addi s0,s0,1 -loop_begin,cnt=7 +| 0010000100 | 10001000001000000000000000000000 0 0 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # lbz s1,0(s0) +| 0010000110 | 01111000010000101100000000000010 0 0 1 0 111 1 1 - - 0 00 00 00 00 0 0 0 1 0 0 ---------- 110 - | # rldicl s2,s2,56,0 -skip_c,loop_begin,cnt=7 +| 0010001000 | 01010000010000010000011000111110 0 0 0 1 --- 1 1 1 - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- - | # rlwimi s1,s2,0,24,31 -skip_c,loop_end +| 0010001010 | 01101000010-----0000000000000000 0 1 0 - --- 0 1 - - 0 00 11 00 00 0 0 0 0 - 0 ---------- --- - | # xori RT,s2,0 -end for non-update + +| 0010010000 | 011111-----00000-----00000111000 0 0 0 - --- 1 0 0 - 0 11 00 01 00 0 0 0 0 - 0 ---------- --- 0 | # and s0,RB,RB -ldx,ldux,ldbrx +| 0010010010 | 00111000000000000000000000000001 0 0 1 0 111 1 1 - - 0 00 00 00 00 0 0 0 0 0 0 ---------- 110 0 | # addi s0,s0,1 -loop_begin,cnt=7 +| 0010010100 | 01111100001-----000000001010111- 0 0 0 0 --- 1 0 1 - 0 00 01 00 00 0 - 0 0 - 0 ---------- --- 1 | # lbzx s1,RA,s0 +| 0010010110 | 01111000010000101100000000000010 0 0 1 0 111 1 1 - - 0 00 00 00 00 0 0 0 1 0 0 ---------- 110 0 | # rldicl s2,s2,56,0 -skip_c,loop_begin,cnt=7 +| 0010011000 | 01010000010000010000011000111110 0 0 0 1 --- 1 1 1 - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- 0 | # rlwimi s1,s2,0,24,31 -skip_c,loop_end +| 0010011010 | 01101000010-----0000000000000000 0 1 0 - --- 0 1 - - 0 00 11 00 00 0 0 0 0 - 0 ---------- --- 0 | # xori RT,s2,0 -end for non-update +| 0010011100 | 011111-----000010000001000010100 1 - 0 - --- 0 1 1 - 0 10 00 00 00 0 0 0 0 - 0 ---------- --- 0 | # add RA,s1,s0 + +| 0010100000 | 00111000000--------------------- 0 - 0 - --- 1 0 - - 0 00 01 01 01 1 1 0 0 - 0 ---------- --- - | # addi s0,RA,D -lmw +| 0010100010 | 100000-----000000000000000000000 0 - 1 0 100 0 1 - - 0 01 00 00 00 0 0 0 0 1 0 ---------- --- - | # lwz RT,0(s0) -loop_begin,skip_zero +| 0010100100 | 100000-----000000000000000000000 1 - 0 - --- 0 1 - - 0 01 00 00 00 0 0 0 0 - 0 ---------- --- - | # lwz RT,0(s0) + +| 0010110000 | 00111000000-----0000000000000000 0 - 0 - --- 1 0 - - 0 00 01 00 00 0 0 0 0 - 0 ---------- --- - | # addi s0,RA,0 -lswi +| 0010110010 | 10001000010000000000000000000000 0 - 1 0 101 1 1 - - 0 00 00 00 00 0 0 0 0 1 0 ---------- --- - | # lbz s2,0(s0) -loop_begin,skip_zero +| 0010110100 | 10001000001000000000000000000001 0 - 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # lbz s1,1(s0) +| 0010110110 | 10001000001000000000000000000010 0 - 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # lbz s1,2(s0) +| 0010111000 | 10001000001000000000000000000011 0 - 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # lbz s1,3(s0) +| 0010111010 | 01111100010-----0000101101111000 0 - 0 1 --- 0 1 1 - 0 00 11 00 00 0 0 0 0 - 0 ---------- --- - | # or RT,s2,s1 -loop_end +| 0010111100 | 10001000001000000000000000000000 0 - 1 0 000 1 1 - - 0 00 00 00 00 0 0 0 0 0 0 ---------- --- - | # lbz s1,0(s0) -loop_begin +| 0010111110 | 00111000000000000000000000000001 0 - 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # addi s0,s0,1 +| 0011000000 | 01010100010000100100000000101110 0 - 1 0 001 1 1 - - 0 00 00 00 00 0 0 0 0 1 0 ---------- --- - | # rlwinm s2,s2,8,0,23 -loop_begin,skip_zero +| 0011000010 | 01101000010-----0000000000000000 1 - 0 - --- 0 1 - - 0 00 11 00 00 0 0 0 0 - 0 ---------- --- - | # xori RT,s2,0 + +| 0011010000 | 00111000010000000000000000000000 0 - 0 - --- 1 0 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # addi s2,R0,0 -lswx +| 0011010010 | 0111110001000000-----0001010111- 0 - 1 0 110 1 1 0 - 0 00 00 01 00 0 - 0 0 1 0 ---------- --- - | # lbzx s2,s0,RB -loop_begin,skip_zero +| 0011010100 | 01010100010000101100000000111110 0 - 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # rlwinm s2,s2,24,0,31 +| 0011010110 | 00111000000000000000000000000001 0 - 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # addi s0,s0,1 +| 0011011000 | 0111110000100000-----0001010111- 0 - 0 0 --- 1 1 0 - 0 00 00 01 00 0 - 0 0 - 0 ---------- --- - | # lbzx s1,s0,RB +| 0011011010 | 01010000001000100100010000101110 0 - 0 0 --- 1 1 1 - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # rlwimi s2,s1,8,16,23 +| 0011011100 | 00111000000000000000000000000001 0 - 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # addi s0,s0,1 +| 0011011110 | 0111110000100000-----0001010111- 0 - 1 0 010 1 1 0 - 0 00 00 01 00 0 - 0 0 1 0 ---------- --- - | # lbzx s1,s0,RB -loop_begin,skip_zero +| 0011100000 | 00111000000000000000000000000001 0 - 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # addi s0,s0,1 +| 0011100010 | 01010100010000100100000000101110 0 - 1 0 011 1 1 - - 0 00 00 00 00 0 0 0 0 1 0 ---------- --- - | # rlwinm s2,s2,8,0,23 -loop_begin,skip_zero +| 0011100100 | 01101000010-----0000000000000000 1 - 0 - --- 0 1 - - 0 00 11 00 00 0 0 0 0 - 0 ---------- --- - | # xori RT,s2,0 + + +| 0100000000 | 010101-----000101100000000111110 0 0 0 - --- 1 0 - - 0 01 00 00 00 0 0 0 0 - 0 ---------- --- - | # rlwinm s2,RS,24,0,31 -sth,sthu +| 0100000010 | 010101-----000101000000000001110 0 0 0 - --- 1 0 - - 0 01 00 00 00 0 0 0 1 - 0 ---------- --- - | # rlwinm s2,RS,16,0,7 -skip_c +| 0100000100 | 10011000010000000000000000000000 0 0 0 - --- - 1 - 1 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # stb s2,0(s0) +| 0100000110 | 10011000010000000000000000000001 0 1 0 - --- - 1 - 1 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # stb s2,1(s0) -end for non-update + +| 0100010000 | 010101-----000101100000000111110 0 0 0 - --- 1 0 - - 0 01 00 00 00 0 0 0 0 - 0 ---------- --- 0 | # rlwinm s2,RS,24,0,31 -sthx,sthux,sthbrx +| 0100010010 | 010101-----000101000000000001110 0 0 0 - --- 1 0 - - 0 01 00 00 00 0 0 0 1 - 0 ---------- --- 0 | # rlwinm s2,RS,16,0,7 -skip_c +| 0100010100 | 01111100010----------0011010111- 0 0 0 - --- - 0 0 1 0 00 01 01 00 0 - 0 0 - 0 ---------- --- 1 | # stbx s2,RA,RB +| 0100010110 | 0111110001000000-----0011010111- 0 1 0 - --- - 1 0 1 0 00 00 01 00 0 - 0 0 - 0 ---------- --- 1 | # stbx s2,s0,RB -end for non-update +| 0100011000 | 011111-----00000-----01000010100 1 - 0 - --- 0 1 0 - 0 10 00 01 00 0 0 0 0 - 0 ---------- --- 0 | # add RA,s0,RB + +| 0101000000 | 010101-----000100100000000111110 0 0 0 - --- 1 0 - - 0 01 00 00 00 0 0 0 0 - 0 ---------- --- - | # rlwinm s2,RS,8,0,31 -stw,stwu +| 0101000010 | 01010000010000101000010000101110 0 0 0 - --- 1 1 1 - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- - | # rlwimi s2,s2,16,16,23 -skip_c +| 0101000100 | 00111000000--------------------- 0 0 0 - --- 1 0 - - 0 00 01 01 01 1 1 0 0 - 0 ---------- --- - | # addi s0,RA,D +| 0101000110 | 00111000000000000000000000000001 0 0 1 0 111 1 1 - - 0 00 00 00 00 0 0 0 0 0 0 ---------- 010 - | # addi s0,s0,1 -loop_begin,cnt=3 +| 0101001000 | 10011000010000000000000000000000 0 1 0 1 --- - 1 - 1 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # stb s2,0(s0) -loop_end,end for non-update + +| 0101010000 | 010101-----000100100000000111110 0 0 0 - --- 1 0 - - 0 01 00 00 00 0 0 0 0 - 0 ---------- --- 0 | # rlwinm s2,RS,8,0,31 -stwx,stwux,stwbrx +| 0101010010 | 01010000010000101000010000101110 0 0 0 - --- 1 1 1 - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- 0 | # rlwimi s2,s2,16,16,23 -skip_c +| 0101010100 | 00111000000-----0000000000000000 0 0 0 - --- 1 0 - - 0 00 01 00 00 0 0 0 0 - 0 ---------- --- 0 | # addi s0,RA,0 +| 0101010110 | 00111000000000000000000000000001 0 0 1 0 111 1 1 - - 0 00 00 00 00 0 0 0 0 0 0 ---------- 010 0 | # addi s0,s0,1 -loop_begin,cnt=3 +| 0101011000 | 0111110001000000-----0011010111- 0 1 0 1 --- - 1 0 1 0 00 00 01 00 0 - 0 0 - 0 ---------- --- 1 | # stbx s2,s0,RB -loop_end,end for non-update + +| 0110000000 | 011110-----000100100000000000000 0 0 0 - --- 1 0 - - 0 01 00 00 00 0 0 0 0 - 0 ---------- --- - | # rldicl s2,RS,8,0 -std,stdu +| 0110000010 | 01111000010000101100000000000010 0 0 1 0 111 1 1 - - 0 00 00 00 00 0 0 0 1 0 0 ---------- 111 - | # rldicl s2,s2,56,0 -skip_c,loop_begin,cnt=8 +| 0110000100 | 01010000010000010000011000111110 0 0 0 1 --- 1 1 1 - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- - | # rlwimi s1,s2,0,24,31 -skip_c,loop_end +| 0110000110 | 1001100001000000---------------0 0 0 1 0 111 - 1 - 1 0 00 00 01 01 1 0 0 0 0 0 ---------- 110 - | # stb s2,DS(s0) -loop_begin,cnt=7 +| 0110001000 | 01111000010000100100000000000000 0 0 0 1 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # rldicl s2,s2,8,0 -loop_end +| 0110001010 | 001110-------------------------0 1 - 0 - --- 0 0 - - 0 10 01 01 01 1 0 0 0 - 0 ---------- --- - | # addi RA,RA,DS + +| 0110010000 | 011110-----000100100000000000000 0 0 0 - --- 1 0 - - 0 01 00 00 00 0 0 0 0 - 0 ---------- --- 0 | # rldicl s2,RS,8,0 -stdx,stdux,stdbrx +| 0110010010 | 01111000010000101100000000000010 0 0 1 0 111 1 1 - - 0 00 00 00 00 0 0 0 1 0 0 ---------- 111 0 | # rldicl s2,s2,56,0 -skip_c,loop_begin,cnt=8 +| 0110010100 | 01010000010000010000011000111110 0 0 0 1 --- 1 1 1 - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- 0 | # rlwimi s1,s2,0,24,31 -skip_c,loop_end +| 0110010110 | 0111110001000000-----0011010111- 0 0 1 0 111 - 1 0 1 0 00 00 01 00 0 - 0 0 0 0 ---------- 110 1 | # stbx s2,s0,RB -loop_begin,cnt=7 +| 0110011000 | 01111000010000100100000000000000 0 0 0 1 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- 0 | # rldicl s2,s2,8,0 -loop_end +| 0110011010 | 011111---------------01000010100 1 - 0 - --- 0 0 0 - 0 10 01 01 00 0 0 0 0 - 0 ---------- --- 0 | # add RA,RA,RB + + +| 0110100000 | 00111000000--------------------- 0 - 0 - --- 1 0 - - 0 00 01 01 01 1 1 0 0 - 0 ---------- --- - | # addi s0,RA,D -stmw +| 0110100010 | 100100-----000000000000000000000 0 - 1 0 100 - 1 - 0 0 01 00 00 00 0 0 0 0 1 0 ---------- --- - | # stw RS,0(s0) -loop_begin,skip_zero +| 0110100100 | 100100-----000000000000000000000 1 - 0 - --- - 1 - 0 0 01 00 00 00 0 0 0 0 - 0 ---------- --- - | # stw RS,0(s0) + +| 0110110000 | 00111000000-----0000000000000000 0 - 0 - --- 1 0 - - 0 00 01 00 00 0 0 0 0 - 0 ---------- --- - | # addi s0,RA,0 -stswi +| 0110110010 | 010101-----000100100000000111110 0 - 1 0 101 1 0 - - 0 01 00 00 00 0 0 0 0 1 0 ---------- --- - | # rlwinm s2,RS,8,0,31 -loop_begin,skip_zero +| 0110110100 | 01010100010000100100000000111110 0 - 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # rlwinm s2,s2,8,0,31 +| 0110110110 | 01010100010000100100000000111110 0 - 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # rlwinm s2,s2,8,0,31 +| 0110111000 | 01010100010000100100000000111110 0 - 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # rlwinm s2,s2,8,0,31 +| 0110111010 | 00111000000000000000000000000100 0 - 0 1 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # addi s0,s0,4 -loop_end +| 0110111100 | 010101-----000100100000000111110 0 - 0 - --- 1 0 - - 0 01 00 00 00 0 0 0 0 - 0 ---------- --- - | # rlwinm s2,RS,8,0,31 +| 0110111110 | 10011000010000000000000000000000 0 - 1 0 000 - 1 - 1 0 00 00 00 00 0 0 0 0 0 0 ---------- --- - | # stb s2,0(s0) -loop_begin +| 0111000000 | 01010100010000100100000000111110 1 - 0 1 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # rlwinm s2,s2,8,0,31 -loop_end + +| 0111010000 | 00111000000-----0000000000000000 0 - 0 - --- 1 0 - - 0 00 01 00 00 0 0 0 0 - 0 ---------- --- - | # addi s0,RA,0 -stswx +| 0111010010 | 010101-----000100100000000111110 0 - 1 0 110 1 0 - - 0 01 00 00 00 0 0 0 0 1 0 ---------- --- - | # rlwinm s2,RS,8,0,31 -loop_begin,skip_zero +| 0111010100 | 00111000000000000000000000000001 0 - 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # addi s0,s0,1 +| 0111010110 | 0111110001000000-----0011010111- 0 - 0 0 --- - 1 0 1 0 00 00 01 00 0 - 0 0 - 0 ---------- --- - | # stbx s2,s0,RB +| 0111011000 | 01010100010000100100000000111110 0 - 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # rlwinm s2,s2,8,0,31 +| 0111011010 | 00111000000000000000000000000001 0 - 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # addi s0,s0,1 +| 0111011100 | 0111110001000000-----0011010111- 0 - 0 0 --- - 1 0 1 0 00 00 01 00 0 - 0 0 - 0 ---------- --- - | # stbx s2,s0,RB +| 0111011110 | 010101-----000100100000000111110 0 - 0 - --- 1 0 - - 0 01 00 00 00 0 0 0 0 - 0 ---------- --- - | # rlwinm s2,RS,8,0,31 +| 0111100000 | 0111110001000000-----0011010111- 0 - 1 0 010 - 1 0 1 0 00 00 01 00 0 - 0 0 1 0 ---------- --- - | # stbx s2,s0,RB -loop_begin,skip_zero +| 0111100010 | 01010100010000100100000000111110 0 - 0 1 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # rlwinm s2,s2,8,0,31 -loop_end + + +| 0101100000 | 0111110000000001000000101010011- 0 - 0 - --- 1 - - - 0 00 00 00 00 0 - 0 0 - 0 ---------- --- - | # mfxer s0 -mcrxr +| 0101100010 | 01111100000000100000101001111000 0 - 0 - --- 1 1 1 - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # xor s2,s0,s1 +| 0101100100 | 01111100000000010000101101111000 0 - 0 - --- 1 1 1 - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # or s1,s0,s1 +| 0101100110 | 01111100000000010000101101111000 0 - 0 - --- 1 1 1 - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # or s1,s0,s1 +| 0101101000 | 01111100000000010000101101111000 0 - 0 - --- 1 1 1 - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # or s1,s0,s1 +| 0101101010 | 0111110001000001000000111010011- 1 - 0 - --- - 1 - - 0 00 00 00 00 0 - 0 0 - 0 ---------- --- - | # mtxer s2 + +| 0101110000 | 011111-----110000000-0000010011- 0 - 0 - --- 0 - - - 0 01 00 00 00 0 - 0 0 - 0 ---------- --- - | # mfocrf RT,0x80 -mfcr +| 0101110010 | 011111----------0000001101111000 0 - 0 - --- 0 0 1 - 0 01 11 00 00 0 0 0 0 - 0 ---------- --- - | # or RT,RT,s0 +| 0101110100 | 011111----------0000001101111000 0 - 0 - --- 0 0 1 - 0 01 11 00 00 0 0 0 0 - 0 ---------- --- - | # or RT,RT,s0 +| 0101110110 | 011111----------0000001101111000 0 - 0 - --- 0 0 1 - 0 01 11 00 00 0 0 0 0 - 0 ---------- --- - | # or RT,RT,s0 +| 0101111000 | 011111----------0000001101111000 0 - 0 - --- 0 0 1 - 0 01 11 00 00 0 0 0 0 - 0 ---------- --- - | # or RT,RT,s0 +| 0101111010 | 011111----------0000001101111000 0 - 0 - --- 0 0 1 - 0 01 11 00 00 0 0 0 0 - 0 ---------- --- - | # or RT,RT,s0 +| 0101111100 | 011111----------0000001101111000 0 - 0 - --- 0 0 1 - 0 01 11 00 00 0 0 0 0 - 0 ---------- --- - | # or RT,RT,s0 +| 0101111110 | 011111----------0000001101111000 1 - 0 - --- 0 0 1 - 0 01 11 00 00 0 0 0 0 - 0 ---------- --- - | # or RT,RT,s0 + + +| 0111110000 | 011111-----110000000-0010010000- 0 - 0 - --- - 0 - - 0 01 00 00 00 0 - 0 0 - 0 ---------- --- - | # mtocrf 0x80,RS -mtcrf +| 0111110010 | 011111-----100100000-0010010000- 0 - 0 - --- - 0 - - 0 01 00 00 00 0 - 0 0 - 0 ---------- --- - | # mtocrf 0x20,RS +| 0111110100 | 011111-----100001000-0010010000- 0 - 0 - --- - 0 - - 0 01 00 00 00 0 - 0 0 - 0 ---------- --- - | # mtocrf 0x08,RS +| 0111110110 | 011111-----100000010-0010010000- 0 - 0 - --- - 0 - - 0 01 00 00 00 0 - 0 0 - 0 ---------- --- - | # mtocrf 0x02,RS + + + +| 1010100000 | 100010-------------------------- 0 - 0 - --- 0 0 - - 0 01 01 01 01 1 1 0 0 - 0 ---------- --- - | # lbz RT,D(RA) -lbzu + +| 1010101000 | 01111100000----------01000010100 0 - 0 - --- 1 0 0 - 0 00 01 01 00 0 0 0 0 - 0 ---------- --- - | # add s0,RA,RB -lbzux +| 1010101010 | 01101000000-----0000000000000000 1 - 0 - --- 0 1 - - 0 00 01 00 00 0 0 0 0 - 0 ---------- --- - | # xori RA,s0,0 + +| 1010110000 | 101000-------------------------- 0 - 0 - --- 0 0 - - 0 01 01 01 01 1 1 0 0 - 0 ---------- --- - | # lhz RT,D(RA) -lhzu + +| 1010111000 | 01111100000----------01000010100 0 - 0 - --- 1 0 0 - 0 00 01 01 00 0 0 0 0 - 0 ---------- --- - | # add s0,RA,RB -lhzux +| 1010111010 | 01101000000-----0000000000000000 1 - 0 - --- 0 1 - - 0 00 01 00 00 0 0 0 0 - 0 ---------- --- - | # xori RA,s0,0 + +| 1011000000 | 100000-------------------------- 0 - 0 - --- 0 0 - - 0 01 01 01 01 1 1 0 0 - 0 ---------- --- - | # lwz RT,D(RA) -lwzu + +| 1011001000 | 01111100000----------01000010100 0 - 0 - --- 1 0 0 - 0 00 01 01 00 0 0 0 0 - 0 ---------- --- - | # add s0,RA,RB -lwzux +| 1011001010 | 01101000000-----0000000000000000 1 - 0 - --- 0 1 - - 0 00 01 00 00 0 0 0 0 - 0 ---------- --- - | # xori RA,s0,0 + +| 1011010000 | 111010-------------------------0 0 - 0 - --- 0 0 - - 0 01 01 01 01 1 0 0 0 - 0 ---------- --- - | # ld RT,DS(RA) -ldu + +| 1011011000 | 01111100000----------01000010100 0 - 0 - --- 1 0 0 - 0 00 01 01 00 0 0 0 0 - 0 ---------- --- - | # add s0,RA,RB -ldux +| 1011011010 | 01101000000-----0000000000000000 1 - 0 - --- 0 1 - - 0 00 01 00 00 0 0 0 0 - 0 ---------- --- - | # xori RA,s0,0 + +| 1011100000 | 101010-------------------------- 0 - 0 - --- 0 0 - - 0 01 01 01 01 1 1 0 0 - 0 ---------- --- - | # lha RT,D(RA) -lhau + +| 1011101000 | 01111100000----------01000010100 0 - 0 - --- 1 0 0 - 0 00 01 01 00 0 0 0 0 - 0 ---------- --- - | # add s0,RA,RB -lhaux +| 1011101010 | 01101000000-----0000000000000000 1 - 0 - --- 0 1 - - 0 00 01 00 00 0 0 0 0 - 0 ---------- --- - | # xori RA,s0,0 + +| 1011111000 | 01111100000----------01000010100 0 - 0 - --- 1 0 0 - 0 00 01 01 00 0 0 0 0 - 0 ---------- --- - | # add s0,RA,RB -lwaux +| 1011111010 | 01101000000-----0000000000000000 1 - 0 - --- 0 1 - - 0 00 01 00 00 0 0 0 0 - 0 ---------- --- - | # xori RA,s0,0 + + + +| 1000110000 | 011111-----00000-----00000111000 0 - 0 - --- 1 0 0 - 0 11 00 01 00 0 0 0 0 - 0 ---------- --- - | # and s0,RB,RB -lfiwax +| 1000110010 | 00111000000000000000000000000001 0 - 1 0 111 1 1 - - 0 00 00 00 00 0 0 0 0 0 0 ---------- 010 - | # addi s0,s0,1 -loop_begin,cnt=3 +| 1000110100 | 01111100001-----000000001010111- 0 - 0 0 --- 1 0 1 - 0 00 01 00 00 0 - 0 0 - 0 ---------- --- - | # lbzx s1,RA,s0 +| 1000110110 | 01010100010000100100000000111110 0 - 0 - --- 1 1 - - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- - | # rlwinm s2,s2,8,0,31 -skip_c +| 1000111000 | 01010000001000101100000000001110 0 - 0 - --- 1 1 1 - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- - | # rlwimi s2,s1,24,0,7 -skip_c + +| 1001110000 | 011111-----00000-----00000111000 0 - 0 - --- 1 0 0 - 0 11 00 01 00 0 0 0 0 - 0 ---------- --- - | # and s0,RB,RB -lfiwzx +| 1001110010 | 00111000000000000000000000000001 0 - 1 0 111 1 1 - - 0 00 00 00 00 0 0 0 0 0 0 ---------- 010 - | # addi s0,s0,1 -loop_begin,cnt=3 +| 1001110100 | 01111100001-----000000001010111- 0 - 0 0 --- 1 0 1 - 0 00 01 00 00 0 - 0 0 - 0 ---------- --- - | # lbzx s1,RA,s0 +| 1001110110 | 01010100010000100100000000111110 0 - 0 - --- 1 1 - - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- - | # rlwinm s2,s2,8,0,31 -skip_c +| 1001111000 | 01010000001000101100000000001110 0 - 0 - --- 1 1 1 - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- - | # rlwimi s2,s1,24,0,7 -skip_c + +| 1001000000 | 00111000000--------------------- 0 0 0 - --- 1 0 - - 0 00 01 01 01 1 1 0 0 - 0 ---------- --- - | # addi s0,RA,D -lfs,lfsu +| 1001000010 | 00111000000000000000000000000001 0 0 1 0 111 1 1 - - 0 00 00 00 00 0 0 0 0 0 0 ---------- 010 - | # addi s0,s0,1 -loop_begin,cnt=3 +| 1001000100 | 10001000001000000000000000000000 0 0 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # lbz s1,0(s0) +| 1001000110 | 01010100010000100100000000111110 0 0 0 - --- 1 1 - - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- - | # rlwinm s2,s2,8,0,31 -skip_c +| 1001001000 | 01010000001000101100000000001110 0 0 0 - --- 1 1 1 - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- - | # rlwimi s2,s1,24,0,7 -skip_c +| 1001001010 | 001110-------------------------- 1 - 0 - --- 0 0 - - 0 10 01 01 01 1 1 0 0 - 0 ---------- --- - | # addi RA,RA,D + +| 1001010000 | 011111-----00000-----00000111000 0 0 0 - --- 1 0 0 - 0 11 00 01 00 0 0 0 0 - 0 ---------- --- - | # and s0,RB,RB -lfsx,lfsux +| 1001010010 | 00111000000000000000000000000001 0 0 1 0 111 1 1 - - 0 00 00 00 00 0 0 0 0 0 0 ---------- 010 - | # addi s0,s0,1 -loop_begin,cnt=3 +| 1001010100 | 01111100001-----000000001010111- 0 0 0 0 --- 1 0 1 - 0 00 01 00 00 0 - 0 0 - 0 ---------- --- - | # lbzx s1,RA,s0 +| 1001010110 | 01010100010000100100000000111110 0 0 0 - --- 1 1 - - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- - | # rlwinm s2,s2,8,0,31 -skip_c +| 1001011000 | 01010000001000101100000000001110 0 0 0 - --- 1 1 1 - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- - | # rlwimi s2,s1,24,0,7 -skip_c +| 1001011010 | 00111000001-----1111111111111101 0 - 0 - --- 1 0 - - 0 00 01 00 00 0 0 0 0 - 0 ---------- --- - | # addi s1,RA,-3 + +| 1010000000 | 00111000000--------------------- 0 0 0 - --- 1 0 - - 0 00 01 01 01 1 1 0 0 - 0 ---------- --- - | # addi s0,RA,D -lfd,lfdu +| 1010000010 | 00111000000000000000000000000001 0 0 1 0 111 1 1 - - 0 00 00 00 00 0 0 0 0 0 0 ---------- 110 - | # addi s0,s0,1 -loop_begin,cnt=7 +| 1010000100 | 10001000001000000000000000000000 0 0 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # lbz s1,0(s0) +| 1010000110 | 01111000010000101100000000000010 0 0 1 0 111 1 1 - - 0 00 00 00 00 0 0 0 1 0 0 ---------- 110 - | # rldicl s2,s2,56,0 -skip_c,loop_begin,cnt=7 +| 1010001000 | 01010000010000010000011000111110 0 0 0 1 --- 1 1 1 - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- - | # rlwimi s1,s2,0,24,31 -skip_c,loop_end +| 1010001010 | 01111100000000000001010011111110 0 1 0 - --- 0 - 1 - 0 01 00 00 00 0 0 0 0 - 0 ---------- --- - | # mffgpr RT,s2,0 -end for non-update + +| 1010010000 | 011111-----00000-----00000111000 0 0 0 - --- 1 0 0 - 0 11 00 01 00 0 0 0 0 - 0 ---------- --- 0 | # and s0,RB,RB -lfdx,lfdux,lfdepx +| 1010010010 | 00111000000000000000000000000001 0 0 1 0 111 1 1 - - 0 00 00 00 00 0 0 0 0 0 0 ---------- 110 0 | # addi s0,s0,1 -loop_begin,cnt=7 +| 1010010100 | 01111100001-----000000001010111- 0 0 0 0 --- 1 0 1 - 0 00 01 00 00 0 - 0 0 - 0 ---------- --- 1 | # lbzx s1,RA,s0 +| 1010010110 | 01111000010000101100000000000010 0 0 1 0 111 1 1 - - 0 00 00 00 00 0 0 0 1 0 0 ---------- 110 0 | # rldicl s2,s2,56,0 -skip_c,loop_begin,cnt=7 +| 1010011000 | 01010000010000010000011000111110 0 0 0 1 --- 1 1 1 - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- 0 | # rlwimi s1,s2,0,24,31 -skip_c,loop_end +| 1010011010 | 011111-----000000001010011111110 0 1 0 - --- 0 - 1 - 0 01 00 00 00 0 0 0 0 - 0 ---------- --- 0 | # mffgpr RT,s2,0 -end for non-update +| 1010011100 | 011111-----000010000001000010100 1 - 0 - --- 0 1 1 - 0 10 00 00 00 0 0 0 0 - 0 ---------- --- 0 | # add RA,s1,s0 + +| 1100110000 | 0111110000100000-----10110111010 0 - 0 - --- 1 - 0 - 0 00 00 10 00 0 0 0 0 - 0 ---------- --- - | # mfitgpr s1,FRS -stfiwx +| 1100110010 | 01010100001000100100000000111110 0 - 0 - --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # rlwinm s2,s1,8,0,31 +| 1100110100 | 01010000010000101000010000101110 0 - 0 - --- 1 1 1 - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- - | # rlwimi s2,s2,16,16,23 -skip_c +| 1100110110 | 0111110001000000-----0011010111- 0 - 1 0 111 - 1 0 1 0 00 00 01 00 0 - 0 0 0 0 ---------- 010 - | # stbx s2,s0,RB -loop_begin,cnt=3 +| 1100111000 | 01010100010000100100000000111110 0 - 0 1 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # rlwinm s2,s2,8,0,31 -loop_end + +| 1101000000 | 0111110000100000-----10111111100 0 0 0 - --- 1 - 0 - 0 00 00 10 00 0 0 0 0 - 0 ---------- --- - | # mfstgpr s1,FRS -stfs,stfsu +| 1101000010 | 01010100001000100100000000111110 0 0 0 - --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # rlwinm s2,s1,8,0,31 +| 1101000100 | 01010000010000101000010000101110 0 0 0 - --- 1 1 1 - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- - | # rlwimi s2,s2,16,16,23 -skip_c +| 1101000110 | 10011000010000000000000000000000 0 0 1 0 111 - 1 - 1 0 00 00 00 00 0 0 0 0 0 0 ---------- 010 - | # stb s2,0(s0) -loop_begin,cnt=3 +| 1101001000 | 01010100010000100100000000111110 0 0 0 1 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # rlwinm s2,s2,8,0,31 -loop_end +| 1101001010 | 001110-------------------------- 1 - 0 - --- 0 0 - - 0 10 01 01 01 1 1 0 0 - 0 ---------- --- - | # addi RA,RA,D + +| 1101010000 | 0111110000100000-----10111111100 0 0 0 - --- 1 - 0 - 0 00 00 10 00 0 0 0 0 - 0 ---------- --- - | # mfstgpr s1,FRS -stfsx,stfsux +| 1101010010 | 01010100001000100100000000111110 0 0 0 - --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # rlwinm s2,s1,8,0,31 +| 1101010100 | 01010000010000101000010000101110 0 0 0 - --- 1 1 1 - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- - | # rlwimi s2,s2,16,16,23 -skip_c +| 1101010110 | 0111110001000000-----0011010111- 0 0 1 0 111 - 1 0 1 0 00 00 01 00 0 - 0 0 0 0 ---------- 010 - | # stbx s2,s0,RB -loop_begin,cnt=3 +| 1101011000 | 01010100010000100100000000111110 0 0 0 1 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # rlwinm s2,s2,8,0,31 -loop_end +| 1101011010 | 011111---------------01000010100 1 - 0 - --- 0 0 0 - 0 10 01 01 00 0 0 0 0 - 0 ---------- --- - | # add RA,RA,RB + +| 1110000000 | 0111110000100000-----10111111110 0 0 0 - --- 1 - 0 - 0 00 00 10 00 0 0 0 0 - 0 ---------- --- - | # mftgpr s1,FRS -stfd,stfdu +| 1110000010 | 01111000010000101100000000000010 0 0 1 0 111 1 1 - - 0 00 00 00 00 0 0 0 1 0 0 ---------- 111 - | # rldicl s2,s2,56,0 -skip_c,loop_begin,cnt=8 +| 1110000100 | 01010000010000010000011000111110 0 0 0 1 --- 1 1 1 - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- - | # rlwimi s1,s2,0,24,31 -skip_c,loop_end +| 1110000110 | 00111000000-----0000000000000000 0 0 0 - --- 1 0 - - 0 00 01 00 00 0 0 0 0 - 0 ---------- --- - | # addi s0,RA,0 +| 1110001000 | 00111000000000000000000000000001 0 0 1 0 111 1 1 - - 0 00 00 00 00 0 0 0 0 0 0 ---------- 110 - | # addi s0,s0,1 -loop_begin,cnt=7 +| 1110001010 | 1001100001000000---------------- 0 1 0 1 --- - 1 - 1 0 00 00 01 01 1 1 0 0 - 0 ---------- --- - | # stb s2,D(s0) -loop_end,end for non-update + +| 1110010000 | 0111110000100000-----10111111110 0 0 0 - --- 1 - 0 - 0 00 00 10 00 0 0 0 0 - 0 ---------- --- 0 | # mftgpr s1,FRS -stfdx,stfdux,stfdepx +| 1110010010 | 01111000010000101100000000000010 0 0 1 0 111 1 1 - - 0 00 00 00 00 0 0 0 1 0 0 ---------- 111 0 | # rldicl s2,s2,56,0 -skip_c,loop_begin,cnt=8 +| 1110010100 | 01010000010000010000011000111110 0 0 0 1 --- 1 1 1 - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- 0 | # rlwimi s1,s2,0,24,31 -skip_c,loop_end +| 1110010110 | 00111000000-----0000000000000000 0 0 0 - --- 1 0 - - 0 00 01 00 00 0 0 0 0 - 0 ---------- --- 0 | # addi s0,RA,0 +| 1110011000 | 00111000000000000000000000000001 0 0 1 0 111 1 1 - - 0 00 00 00 00 0 0 0 0 0 0 ---------- 110 0 | # addi s0,s0,1 -loop_begin,cnt=7 +| 1110011010 | 0111110001000000-----0011010111- 0 1 0 1 --- - 1 0 1 0 00 00 01 00 0 - 0 0 - 0 ---------- --- 1 | # stbx s2,s0,RB -loop_end,end for non-update + + + +| 1111000000 | 110000-------------------------- 0 - 0 - --- 0 0 - - 0 01 01 01 01 1 1 0 0 - 0 ---------- --- - | # lfs FRT,DS(RA) -lfsu + +| 1111001000 | 01111100000----------01000010100 0 - 0 - --- 1 0 0 - 0 00 01 01 00 0 0 0 0 - 0 ---------- --- - | # add s0,RA,RB -lfsux +| 1111001010 | 01101000000-----0000000000000000 1 - 0 - --- 0 1 - - 0 00 01 00 00 0 0 0 0 - 0 ---------- --- - | # xori RA,s0,0 + +| 1111010000 | 110010-------------------------- 0 - 0 - --- 0 0 - - 0 01 01 01 01 1 1 0 0 - 0 ---------- --- - | # lfd FRT,DS(RA) -lfdu + +| 1111011000 | 01111100000----------01000010100 0 - 0 - --- 1 0 0 - 0 00 01 01 00 0 0 0 0 - 0 ---------- --- - | # add s0,RA,RB -lfdux +| 1111011010 | 01101000000-----0000000000000000 1 - 0 - --- 0 1 - - 0 00 01 00 00 0 0 0 0 - 0 ---------- --- - | # xori RA,s0,0 + + +| 1100000000 | 11111100001---------------100000 0 - 0 - --- 1 - 0 - 0 00 -- 01 -- 0 0 0 0 - 0 ---------- --- - | # prenrm s1,FB - prenorm both DP, SP + +| 1100001000 | 11111100001---------------100000 0 - 0 - --- 1 - 0 - 0 00 -- 01 -- 0 0 0 0 - 0 ---------- --- - | # prenrm s1,FB - prenorm both DP, SP +| 1100001010 | -----------0001000001----------- 1 - 0 - --- 0 1 1 0 1 01 00 00 01 1 1 0 0 - 0 ---------- --- - | # vvvvv FT,s2,FC,s1 - Original qpx op except B + +| 1100010000 | 11101100001---------------100000 0 - 0 - --- 1 - 0 - 0 00 -- 01 -- 0 0 0 0 - 0 ---------- --- - | # prenrm s1,FB - prenorm SP only +*END*===========+=======================================================================================================+ +?TABLE END rom_instr; +//table_end +*/ + +//assign_start + +assign rom_instr_pt[1] = + (({ rom_addr_l2[1] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[5] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0000000); +assign rom_instr_pt[2] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[4] , rom_addr_l2[5] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0000000); +assign rom_instr_pt[3] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[4] , rom_addr_l2[5] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b1010000); +assign rom_instr_pt[4] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[5] , rom_addr_l2[6] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b000000); +assign rom_instr_pt[5] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[5] , rom_addr_l2[6] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b100000); +assign rom_instr_pt[6] = + (({ rom_addr_l2[1] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[5] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0001000); +assign rom_instr_pt[7] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[6] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 8'b11101000); +assign rom_instr_pt[8] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[6] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 8'b10111000); +assign rom_instr_pt[9] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[5] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0011000); +assign rom_instr_pt[10] = + (({ rom_addr_l2[0] , rom_addr_l2[2] , + rom_addr_l2[5] , rom_addr_l2[6] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b011000); +assign rom_instr_pt[11] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0100000); +assign rom_instr_pt[12] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[4] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0100000); +assign rom_instr_pt[13] = + (({ rom_addr_l2[0] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[6] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b001000); +assign rom_instr_pt[14] = + (({ rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[6] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b111000); +assign rom_instr_pt[15] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[4] , rom_addr_l2[6] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b101000); +assign rom_instr_pt[16] = + (({ rom_addr_l2[0] , rom_addr_l2[2] , + rom_addr_l2[4] , rom_addr_l2[6] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b101000); +assign rom_instr_pt[17] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[4] , rom_addr_l2[6] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b111000); +assign rom_instr_pt[18] = + (({ rom_addr_l2[0] , rom_addr_l2[4] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b01000); +assign rom_instr_pt[19] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b1000000); +assign rom_instr_pt[20] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b1110000); +assign rom_instr_pt[21] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b1101000); +assign rom_instr_pt[22] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b11000); +assign rom_instr_pt[23] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0100100); +assign rom_instr_pt[24] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[4] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0011100); +assign rom_instr_pt[25] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0011100); +assign rom_instr_pt[26] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[6] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b011100); +assign rom_instr_pt[27] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0111100); +assign rom_instr_pt[28] = + (({ rom_addr_l2[0] , rom_addr_l2[2] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b01100); +assign rom_instr_pt[29] = + (({ rom_addr_l2[0] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[5] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b001000); +assign rom_instr_pt[30] = + (({ rom_addr_l2[0] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0111100); +assign rom_instr_pt[31] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0110000); +assign rom_instr_pt[32] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[6] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 8'b01001010); +assign rom_instr_pt[33] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[4] , rom_addr_l2[5] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0111010); +assign rom_instr_pt[34] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0110010); +assign rom_instr_pt[35] = + (({ rom_addr_l2[1] , rom_addr_l2[4] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b10110); +assign rom_instr_pt[36] = + (({ rom_addr_l2[1] , rom_addr_l2[4] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b01110); +assign rom_instr_pt[37] = + (({ rom_addr_l2[1] , rom_addr_l2[3] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b10110); +assign rom_instr_pt[38] = + (({ rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b11110); +assign rom_instr_pt[39] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0110010); +assign rom_instr_pt[40] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[4] , rom_addr_l2[5] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b010010); +assign rom_instr_pt[41] = + (({ rom_addr_l2[1] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b00010); +assign rom_instr_pt[42] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0011010); +assign rom_instr_pt[43] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[5] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b000010); +assign rom_instr_pt[44] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[5] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b001010); +assign rom_instr_pt[45] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[5] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0000110); +assign rom_instr_pt[46] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[5] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0100110); +assign rom_instr_pt[47] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[5] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b001110); +assign rom_instr_pt[48] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b110010); +assign rom_instr_pt[49] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0101010); +assign rom_instr_pt[50] = + (({ rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b11010); +assign rom_instr_pt[51] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b111110); +assign rom_instr_pt[52] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[4] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b10110); +assign rom_instr_pt[53] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b11010); +assign rom_instr_pt[54] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 4'b1110); +assign rom_instr_pt[55] = + (({ rom_addr_l2[1] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[6] , + rom_addr_l2[8] }) === 5'b10000); +assign rom_instr_pt[56] = + (({ rom_addr_l2[1] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[6] , + rom_addr_l2[8] }) === 5'b11010); +assign rom_instr_pt[57] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[6] , rom_addr_l2[8] + }) === 6'b100010); +assign rom_instr_pt[58] = + (({ rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[6] , + rom_addr_l2[8] }) === 5'b01010); +assign rom_instr_pt[59] = + (({ rom_addr_l2[1] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[6] , + rom_addr_l2[8] }) === 5'b10110); +assign rom_instr_pt[60] = + (({ rom_addr_l2[1] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[6] , + rom_addr_l2[8] }) === 5'b11110); +assign rom_instr_pt[61] = + (({ rom_addr_l2[0] , rom_addr_l2[2] , + rom_addr_l2[4] , rom_addr_l2[6] , + rom_addr_l2[8] }) === 5'b11110); +assign rom_instr_pt[62] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[6] , rom_addr_l2[8] + }) === 6'b111010); +assign rom_instr_pt[63] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[6] , + rom_addr_l2[8] }) === 5'b00110); +assign rom_instr_pt[64] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[6] , rom_addr_l2[8] + }) === 6'b110110); +assign rom_instr_pt[65] = + (({ rom_addr_l2[0] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[6] , + rom_addr_l2[8] }) === 5'b11110); +assign rom_instr_pt[66] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[5] , + rom_addr_l2[8] }) === 7'b0011000); +assign rom_instr_pt[67] = + (({ rom_addr_l2[0] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[8] + }) === 6'b011000); +assign rom_instr_pt[68] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[8] + }) === 6'b111100); +assign rom_instr_pt[69] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[3] , rom_addr_l2[8] + }) === 4'b1100); +assign rom_instr_pt[70] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[4] , rom_addr_l2[5] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b1010001); +assign rom_instr_pt[71] = + (({ rom_addr_l2[2] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[6] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b101001); +assign rom_instr_pt[72] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[4] , rom_addr_l2[5] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0111001); +assign rom_instr_pt[73] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[4] , rom_addr_l2[5] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b1111001); +assign rom_instr_pt[74] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[5] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0111001); +assign rom_instr_pt[75] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b1100001); +assign rom_instr_pt[76] = + (({ rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[6] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b100001); +assign rom_instr_pt[77] = + (({ rom_addr_l2[1] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[6] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b000001); +assign rom_instr_pt[78] = + (({ rom_addr_l2[1] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[6] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b100001); +assign rom_instr_pt[79] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b1110001); +assign rom_instr_pt[80] = + (({ rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b10001); +assign rom_instr_pt[81] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[6] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b001001); +assign rom_instr_pt[82] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b00001); +assign rom_instr_pt[83] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[6] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b110001); +assign rom_instr_pt[84] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[4] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0011101); +assign rom_instr_pt[85] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[3] , rom_addr_l2[6] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b000101); +assign rom_instr_pt[86] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[3] , rom_addr_l2[6] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b010101); +assign rom_instr_pt[87] = + (({ rom_addr_l2[3] , rom_addr_l2[6] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 4'b0101); +assign rom_instr_pt[88] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0011101); +assign rom_instr_pt[89] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0111101); +assign rom_instr_pt[90] = + (({ rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b11101); +assign rom_instr_pt[91] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[5] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b000001); +assign rom_instr_pt[92] = + (({ rom_addr_l2[0] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0001101); +assign rom_instr_pt[93] = + (({ rom_addr_l2[0] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0111101); +assign rom_instr_pt[94] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0101001); +assign rom_instr_pt[95] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[4] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b010001); +assign rom_instr_pt[96] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[4] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b100101); +assign rom_instr_pt[97] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b010001); +assign rom_instr_pt[98] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b00101); +assign rom_instr_pt[99] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b10001); +assign rom_instr_pt[100] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[6] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 8'b01101011); +assign rom_instr_pt[101] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b1110011); +assign rom_instr_pt[102] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[4] , rom_addr_l2[6] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b011011); +assign rom_instr_pt[103] = + (({ rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b11011); +assign rom_instr_pt[104] = + (({ rom_addr_l2[1] , rom_addr_l2[4] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b10111); +assign rom_instr_pt[105] = + (({ rom_addr_l2[1] , rom_addr_l2[3] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b10111); +assign rom_instr_pt[106] = + (({ rom_addr_l2[1] , rom_addr_l2[3] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b01111); +assign rom_instr_pt[107] = + (({ rom_addr_l2[2] , rom_addr_l2[6] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 4'b0111); +assign rom_instr_pt[108] = + (({ rom_addr_l2[1] , rom_addr_l2[6] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 4'b0111); +assign rom_instr_pt[109] = + (({ rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b01011); +assign rom_instr_pt[110] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[5] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b000011); +assign rom_instr_pt[111] = + (({ rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[5] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b00011); +assign rom_instr_pt[112] = + (({ rom_addr_l2[1] , rom_addr_l2[3] , + rom_addr_l2[5] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b00011); +assign rom_instr_pt[113] = + (({ rom_addr_l2[1] , rom_addr_l2[3] , + rom_addr_l2[5] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b01011); +assign rom_instr_pt[114] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[5] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b110011); +assign rom_instr_pt[115] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[5] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b011011); +assign rom_instr_pt[116] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0100111); +assign rom_instr_pt[117] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[5] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0000111); +assign rom_instr_pt[118] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[5] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b00111); +assign rom_instr_pt[119] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[5] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b110111); +assign rom_instr_pt[120] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b010011); +assign rom_instr_pt[121] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b101011); +assign rom_instr_pt[122] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[4] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b010011); +assign rom_instr_pt[123] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b100111); +assign rom_instr_pt[124] = + (({ rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b11111); +assign rom_instr_pt[125] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b10011); +assign rom_instr_pt[126] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b00111); +assign rom_instr_pt[127] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b10011); +assign rom_instr_pt[128] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b11111); +assign rom_instr_pt[129] = + (({ rom_addr_l2[0] , rom_addr_l2[2] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 4'b1111); +assign rom_instr_pt[130] = + (({ rom_addr_l2[1] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[5] , + rom_addr_l2[6] , rom_addr_l2[8] + }) === 6'b111001); +assign rom_instr_pt[131] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[6] , + rom_addr_l2[8] }) === 7'b0101101); +assign rom_instr_pt[132] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[6] , rom_addr_l2[8] + }) === 6'b010001); +assign rom_instr_pt[133] = + (({ rom_addr_l2[0] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[6] , rom_addr_l2[8] + }) === 6'b010001); +assign rom_instr_pt[134] = + (({ rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[6] , + rom_addr_l2[8] }) === 5'b01001); +assign rom_instr_pt[135] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[6] , rom_addr_l2[8] + }) === 6'b011101); +assign rom_instr_pt[136] = + (({ rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[5] , + rom_addr_l2[6] , rom_addr_l2[8] + }) === 6'b010011); +assign rom_instr_pt[137] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[3] , rom_addr_l2[5] , + rom_addr_l2[6] , rom_addr_l2[8] + }) === 6'b110011); +assign rom_instr_pt[138] = + (({ rom_addr_l2[1] , rom_addr_l2[3] , + rom_addr_l2[5] , rom_addr_l2[6] , + rom_addr_l2[8] }) === 5'b10011); +assign rom_instr_pt[139] = + (({ rom_addr_l2[2] , rom_addr_l2[5] , + rom_addr_l2[6] , rom_addr_l2[8] + }) === 4'b0011); +assign rom_instr_pt[140] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[6] , + rom_addr_l2[8] }) === 7'b0100111); +assign rom_instr_pt[141] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[3] , rom_addr_l2[5] , + rom_addr_l2[6] , rom_addr_l2[8] + }) === 6'b110111); +assign rom_instr_pt[142] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[5] , rom_addr_l2[6] , + rom_addr_l2[8] }) === 5'b00111); +assign rom_instr_pt[143] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[5] , + rom_addr_l2[6] , rom_addr_l2[8] + }) === 6'b110111); +assign rom_instr_pt[144] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[6] , rom_addr_l2[8] + }) === 6'b000011); +assign rom_instr_pt[145] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[6] , rom_addr_l2[8] + }) === 6'b100011); +assign rom_instr_pt[146] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[6] , rom_addr_l2[8] + }) === 6'b010011); +assign rom_instr_pt[147] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[4] , rom_addr_l2[6] , + rom_addr_l2[8] }) === 5'b11111); +assign rom_instr_pt[148] = + (({ rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[6] , rom_addr_l2[8] + }) === 4'b0011); +assign rom_instr_pt[149] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[6] , rom_addr_l2[8] + }) === 6'b111011); +assign rom_instr_pt[150] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[6] , rom_addr_l2[8] + }) === 6'b110111); +assign rom_instr_pt[151] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[6] , rom_addr_l2[8] + }) === 4'b0011); +assign rom_instr_pt[152] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[6] , + rom_addr_l2[8] }) === 5'b11011); +assign rom_instr_pt[153] = + (({ rom_addr_l2[0] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[8] + }) === 6'b011001); +assign rom_instr_pt[154] = + (({ rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[5] , + rom_addr_l2[8] }) === 5'b11001); +assign rom_instr_pt[155] = + (({ rom_addr_l2[0] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[8] + }) === 6'b010101); +assign rom_instr_pt[156] = + (({ rom_addr_l2[0] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[8] + }) === 6'b011101); +assign rom_instr_pt[157] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[8] + }) === 6'b010111); +assign rom_instr_pt[158] = + (({ rom_addr_l2[1] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[8] + }) === 4'b1111); +assign rom_instr_pt[159] = + (({ rom_addr_l2[0] , rom_addr_l2[2] , + rom_addr_l2[4] , rom_addr_l2[8] + }) === 4'b1111); +assign rom_instr_pt[160] = + (({ rom_addr_l2[0] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[8] + }) === 4'b1111); +assign rom_instr_pt[161] = + (({ rom_addr_l2[3] , rom_addr_l2[8] + }) === 2'b11); +assign rom_instr_pt[162] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[8] }) === 3'b011); +assign rom_instr_pt[163] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[5] , + rom_addr_l2[6] , rom_addr_l2[7] + }) === 6'b011100); +assign rom_instr_pt[164] = + (({ rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[6] , + rom_addr_l2[7] }) === 5'b10000); +assign rom_instr_pt[165] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[6] , rom_addr_l2[7] + }) === 6'b010000); +assign rom_instr_pt[166] = + (({ rom_addr_l2[0] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[7] + }) === 6'b011100); +assign rom_instr_pt[167] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[7] + }) === 6'b000010); +assign rom_instr_pt[168] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[6] , + rom_addr_l2[7] }) === 7'b0101101); +assign rom_instr_pt[169] = + (({ rom_addr_l2[0] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[6] , + rom_addr_l2[7] }) === 5'b00101); +assign rom_instr_pt[170] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[6] , + rom_addr_l2[7] }) === 5'b11101); +assign rom_instr_pt[171] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[3] , rom_addr_l2[6] , + rom_addr_l2[7] }) === 5'b01101); +assign rom_instr_pt[172] = + (({ rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[6] , rom_addr_l2[7] + }) === 4'b0011); +assign rom_instr_pt[173] = + (({ rom_addr_l2[1] , rom_addr_l2[4] , + rom_addr_l2[6] , rom_addr_l2[7] + }) === 4'b0111); +assign rom_instr_pt[174] = + (({ rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[5] , + rom_addr_l2[7] }) === 5'b10101); +assign rom_instr_pt[175] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[4] , rom_addr_l2[5] , + rom_addr_l2[7] }) === 5'b10101); +assign rom_instr_pt[176] = + (({ rom_addr_l2[2] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[7] + }) === 4'b1101); +assign rom_instr_pt[177] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[5] , + rom_addr_l2[7] }) === 5'b10001); +assign rom_instr_pt[178] = + (({ rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[5] , rom_addr_l2[7] + }) === 4'b0001); +assign rom_instr_pt[179] = + (({ rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[5] , rom_addr_l2[7] + }) === 4'b1101); +assign rom_instr_pt[180] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[7] + }) === 6'b010111); +assign rom_instr_pt[181] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[5] , rom_addr_l2[7] + }) === 6'b000011); +assign rom_instr_pt[182] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[5] , rom_addr_l2[7] + }) === 6'b010011); +assign rom_instr_pt[183] = + (({ rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[7] + }) === 4'b1111); +assign rom_instr_pt[184] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[4] , + rom_addr_l2[7] }) === 5'b01011); +assign rom_instr_pt[185] = + (({ rom_addr_l2[0] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[6] + }) === 4'b1100); +assign rom_instr_pt[186] = + (({ rom_addr_l2[0] , rom_addr_l2[2] , + rom_addr_l2[4] , rom_addr_l2[5] , + rom_addr_l2[6] }) === 5'b01110); +assign rom_instr_pt[187] = + (({ rom_addr_l2[0] , rom_addr_l2[2] , + rom_addr_l2[4] , rom_addr_l2[5] , + rom_addr_l2[6] }) === 5'b11110); +assign rom_instr_pt[188] = + (({ rom_addr_l2[3] , rom_addr_l2[5] , + rom_addr_l2[6] }) === 3'b010); +assign rom_instr_pt[189] = + (({ rom_addr_l2[5] , rom_addr_l2[6] + }) === 2'b10); +assign rom_instr_pt[190] = + (({ rom_addr_l2[0] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[6] }) === 5'b10000); +assign rom_instr_pt[191] = + (({ rom_addr_l2[0] , rom_addr_l2[2] , + rom_addr_l2[4] , rom_addr_l2[6] + }) === 4'b1110); +assign rom_instr_pt[192] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[6] }) === 5'b11110); +assign rom_instr_pt[193] = + (({ rom_addr_l2[0] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[6] + }) === 4'b1110); +assign rom_instr_pt[194] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[6] + }) === 6'b010001); +assign rom_instr_pt[195] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[5] , + rom_addr_l2[6] }) === 7'b0101011); +assign rom_instr_pt[196] = + (({ rom_addr_l2[1] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[5] , + rom_addr_l2[6] }) === 5'b11111); +assign rom_instr_pt[197] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[6] }) === 5'b00001); +assign rom_instr_pt[198] = + (({ rom_addr_l2[0] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[6] }) === 5'b00001); +assign rom_instr_pt[199] = + (({ rom_addr_l2[1] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[6] + }) === 4'b0001); +assign rom_instr_pt[200] = + (({ rom_addr_l2[0] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[6] + }) === 4'b0001); +assign rom_instr_pt[201] = + (({ rom_addr_l2[0] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[6] }) === 5'b00011); +assign rom_instr_pt[202] = + (({ rom_addr_l2[1] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[6] + }) === 4'b1111); +assign rom_instr_pt[203] = + (({ rom_addr_l2[0] , rom_addr_l2[2] , + rom_addr_l2[4] , rom_addr_l2[6] + }) === 4'b1111); +assign rom_instr_pt[204] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[6] }) === 5'b10001); +assign rom_instr_pt[205] = + (({ rom_addr_l2[0] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[6] + }) === 4'b0001); +assign rom_instr_pt[206] = + (({ rom_addr_l2[0] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[6] + }) === 4'b1111); +assign rom_instr_pt[207] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[3] , rom_addr_l2[6] + }) === 4'b0111); +assign rom_instr_pt[208] = + (({ rom_addr_l2[2] , rom_addr_l2[6] + }) === 2'b01); +assign rom_instr_pt[209] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[5] + }) === 6'b011100); +assign rom_instr_pt[210] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[4] , rom_addr_l2[5] + }) === 4'b1010); +assign rom_instr_pt[211] = + (({ rom_addr_l2[0] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[5] + }) === 4'b1000); +assign rom_instr_pt[212] = + (({ rom_addr_l2[3] , rom_addr_l2[5] + }) === 2'b00); +assign rom_instr_pt[213] = + (({ rom_addr_l2[1] , rom_addr_l2[3] , + rom_addr_l2[5] }) === 3'b010); +assign rom_instr_pt[214] = + (({ rom_addr_l2[1] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[5] + }) === 4'b1111); +assign rom_instr_pt[215] = + (({ rom_addr_l2[0] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[5] + }) === 4'b0111); +assign rom_instr_pt[216] = + (({ rom_addr_l2[0] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[5] + }) === 4'b1111); +assign rom_instr_pt[217] = + (({ rom_addr_l2[0] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] + }) === 4'b1000); +assign rom_instr_pt[218] = + (({ rom_addr_l2[3] , rom_addr_l2[4] + }) === 2'b00); +assign rom_instr_pt[219] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] + }) === 4'b1001); +assign rom_instr_pt[220] = + (({ rom_addr_l2[3] , rom_addr_l2[4] + }) === 2'b11); +assign rom_instr_pt[221] = + (({ rom_addr_l2[0] , rom_addr_l2[2] , + rom_addr_l2[4] }) === 3'b111); +assign rom_instr_pt[222] = + (({ rom_addr_l2[1] , rom_addr_l2[4] + }) === 2'b11); +assign rom_instr_pt[223] = + (({ rom_addr_l2[0] , rom_addr_l2[2] , + rom_addr_l2[3] }) === 3'b111); +assign rom_instr_pt[224] = + (({ rom_addr_l2[2] }) === 1'b0); +assign rom_instr_pt[225] = + 1'b1; +assign template[0] = + (rom_instr_pt[24] | rom_instr_pt[33] + | rom_instr_pt[36] | rom_instr_pt[40] + | rom_instr_pt[44] | rom_instr_pt[72] + | rom_instr_pt[91] | rom_instr_pt[92] + | rom_instr_pt[102] | rom_instr_pt[105] + | rom_instr_pt[114] | rom_instr_pt[115] + | rom_instr_pt[137] | rom_instr_pt[155] + | rom_instr_pt[174] | rom_instr_pt[177] + | rom_instr_pt[185] | rom_instr_pt[187] + | rom_instr_pt[193] | rom_instr_pt[194] + | rom_instr_pt[217]); +assign template[1] = + (rom_instr_pt[3] | rom_instr_pt[6] + | rom_instr_pt[8] | rom_instr_pt[9] + | rom_instr_pt[12] | rom_instr_pt[16] + | rom_instr_pt[22] | rom_instr_pt[23] + | rom_instr_pt[25] | rom_instr_pt[27] + | rom_instr_pt[30] | rom_instr_pt[31] + | rom_instr_pt[32] | rom_instr_pt[34] + | rom_instr_pt[35] | rom_instr_pt[43] + | rom_instr_pt[45] | rom_instr_pt[47] + | rom_instr_pt[48] | rom_instr_pt[52] + | rom_instr_pt[53] | rom_instr_pt[59] + | rom_instr_pt[63] | rom_instr_pt[64] + | rom_instr_pt[67] | rom_instr_pt[68] + | rom_instr_pt[70] | rom_instr_pt[74] + | rom_instr_pt[75] | rom_instr_pt[79] + | rom_instr_pt[83] | rom_instr_pt[84] + | rom_instr_pt[88] | rom_instr_pt[93] + | rom_instr_pt[94] | rom_instr_pt[100] + | rom_instr_pt[104] | rom_instr_pt[106] + | rom_instr_pt[112] | rom_instr_pt[117] + | rom_instr_pt[119] | rom_instr_pt[120] + | rom_instr_pt[126] | rom_instr_pt[127] + | rom_instr_pt[131] | rom_instr_pt[140] + | rom_instr_pt[141] | rom_instr_pt[143] + | rom_instr_pt[144] | rom_instr_pt[145] + | rom_instr_pt[153] | rom_instr_pt[156] + | rom_instr_pt[157] | rom_instr_pt[165] + | rom_instr_pt[168] | rom_instr_pt[172] + | rom_instr_pt[182] | rom_instr_pt[183] + | rom_instr_pt[184] | rom_instr_pt[195] + | rom_instr_pt[202] | rom_instr_pt[203] + | rom_instr_pt[204] | rom_instr_pt[205] + | rom_instr_pt[206] | rom_instr_pt[211] + | rom_instr_pt[216]); +assign template[2] = + (rom_instr_pt[4] | rom_instr_pt[9] + | rom_instr_pt[10] | rom_instr_pt[14] + | rom_instr_pt[16] | rom_instr_pt[18] + | rom_instr_pt[21] | rom_instr_pt[25] + | rom_instr_pt[31] | rom_instr_pt[32] + | rom_instr_pt[38] | rom_instr_pt[47] + | rom_instr_pt[52] | rom_instr_pt[60] + | rom_instr_pt[62] | rom_instr_pt[70] + | rom_instr_pt[84] | rom_instr_pt[86] + | rom_instr_pt[89] | rom_instr_pt[93] + | rom_instr_pt[98] | rom_instr_pt[99] + | rom_instr_pt[100] | rom_instr_pt[103] + | rom_instr_pt[108] | rom_instr_pt[112] + | rom_instr_pt[117] | rom_instr_pt[119] + | rom_instr_pt[120] | rom_instr_pt[129] + | rom_instr_pt[139] | rom_instr_pt[141] + | rom_instr_pt[143] | rom_instr_pt[144] + | rom_instr_pt[145] | rom_instr_pt[153] + | rom_instr_pt[157] | rom_instr_pt[163] + | rom_instr_pt[164] | rom_instr_pt[167] + | rom_instr_pt[171] | rom_instr_pt[172] + | rom_instr_pt[182] | rom_instr_pt[183] + | rom_instr_pt[187] | rom_instr_pt[195] + | rom_instr_pt[203] | rom_instr_pt[205] + | rom_instr_pt[206] | rom_instr_pt[217] + ); +assign template[3] = + (rom_instr_pt[4] | rom_instr_pt[9] + | rom_instr_pt[10] | rom_instr_pt[12] + | rom_instr_pt[16] | rom_instr_pt[18] + | rom_instr_pt[21] | rom_instr_pt[23] + | rom_instr_pt[25] | rom_instr_pt[27] + | rom_instr_pt[31] | rom_instr_pt[32] + | rom_instr_pt[34] | rom_instr_pt[38] + | rom_instr_pt[43] | rom_instr_pt[45] + | rom_instr_pt[47] | rom_instr_pt[48] + | rom_instr_pt[52] | rom_instr_pt[53] + | rom_instr_pt[61] | rom_instr_pt[62] + | rom_instr_pt[63] | rom_instr_pt[64] + | rom_instr_pt[65] | rom_instr_pt[67] + | rom_instr_pt[74] | rom_instr_pt[79] + | rom_instr_pt[83] | rom_instr_pt[84] + | rom_instr_pt[86] | rom_instr_pt[88] + | rom_instr_pt[89] | rom_instr_pt[94] + | rom_instr_pt[98] | rom_instr_pt[99] + | rom_instr_pt[100] | rom_instr_pt[103] + | rom_instr_pt[104] | rom_instr_pt[108] + | rom_instr_pt[109] | rom_instr_pt[114] + | rom_instr_pt[115] | rom_instr_pt[117] + | rom_instr_pt[119] | rom_instr_pt[120] + | rom_instr_pt[126] | rom_instr_pt[127] + | rom_instr_pt[129] | rom_instr_pt[137] + | rom_instr_pt[139] | rom_instr_pt[141] + | rom_instr_pt[143] | rom_instr_pt[145] + | rom_instr_pt[156] | rom_instr_pt[164] + | rom_instr_pt[165] | rom_instr_pt[167] + | rom_instr_pt[171] | rom_instr_pt[172] + | rom_instr_pt[177] | rom_instr_pt[182] + | rom_instr_pt[194] | rom_instr_pt[195] + | rom_instr_pt[198] | rom_instr_pt[204] + | rom_instr_pt[211] | rom_instr_pt[222] + ); +assign template[4] = + (rom_instr_pt[4] | rom_instr_pt[9] + | rom_instr_pt[10] | rom_instr_pt[16] + | rom_instr_pt[18] | rom_instr_pt[21] + | rom_instr_pt[24] | rom_instr_pt[25] + | rom_instr_pt[31] | rom_instr_pt[32] + | rom_instr_pt[33] | rom_instr_pt[36] + | rom_instr_pt[38] | rom_instr_pt[40] + | rom_instr_pt[44] | rom_instr_pt[47] + | rom_instr_pt[52] | rom_instr_pt[60] + | rom_instr_pt[62] | rom_instr_pt[70] + | rom_instr_pt[72] | rom_instr_pt[84] + | rom_instr_pt[86] | rom_instr_pt[89] + | rom_instr_pt[91] | rom_instr_pt[92] + | rom_instr_pt[93] | rom_instr_pt[98] + | rom_instr_pt[99] | rom_instr_pt[100] + | rom_instr_pt[102] | rom_instr_pt[103] + | rom_instr_pt[105] | rom_instr_pt[108] + | rom_instr_pt[112] | rom_instr_pt[114] + | rom_instr_pt[115] | rom_instr_pt[117] + | rom_instr_pt[119] | rom_instr_pt[120] + | rom_instr_pt[129] | rom_instr_pt[137] + | rom_instr_pt[139] | rom_instr_pt[141] + | rom_instr_pt[143] | rom_instr_pt[144] + | rom_instr_pt[145] | rom_instr_pt[153] + | rom_instr_pt[157] | rom_instr_pt[163] + | rom_instr_pt[164] | rom_instr_pt[167] + | rom_instr_pt[171] | rom_instr_pt[172] + | rom_instr_pt[177] | rom_instr_pt[182] + | rom_instr_pt[183] | rom_instr_pt[185] + | rom_instr_pt[194] | rom_instr_pt[195] + | rom_instr_pt[203] | rom_instr_pt[205] + | rom_instr_pt[206] | rom_instr_pt[216] + | rom_instr_pt[217]); +assign template[5] = + (rom_instr_pt[3] | rom_instr_pt[6] + | rom_instr_pt[8] | rom_instr_pt[9] + | rom_instr_pt[12] | rom_instr_pt[16] + | rom_instr_pt[20] | rom_instr_pt[21] + | rom_instr_pt[25] | rom_instr_pt[27] + | rom_instr_pt[30] | rom_instr_pt[32] + | rom_instr_pt[34] | rom_instr_pt[35] + | rom_instr_pt[43] | rom_instr_pt[47] + | rom_instr_pt[51] | rom_instr_pt[52] + | rom_instr_pt[59] | rom_instr_pt[61] + | rom_instr_pt[64] | rom_instr_pt[65] + | rom_instr_pt[67] | rom_instr_pt[68] + | rom_instr_pt[70] | rom_instr_pt[74] + | rom_instr_pt[79] | rom_instr_pt[83] + | rom_instr_pt[84] | rom_instr_pt[93] + | rom_instr_pt[100] | rom_instr_pt[104] + | rom_instr_pt[106] | rom_instr_pt[109] + | rom_instr_pt[117] | rom_instr_pt[119] + | rom_instr_pt[124] | rom_instr_pt[126] + | rom_instr_pt[127] | rom_instr_pt[131] + | rom_instr_pt[140] | rom_instr_pt[141] + | rom_instr_pt[143] | rom_instr_pt[145] + | rom_instr_pt[156] | rom_instr_pt[157] + | rom_instr_pt[165] | rom_instr_pt[168] + | rom_instr_pt[172] | rom_instr_pt[182] + | rom_instr_pt[184] | rom_instr_pt[195] + | rom_instr_pt[198] | rom_instr_pt[202] + | rom_instr_pt[217]); +assign template[6] = + 1'b0; +assign template[7] = + 1'b0; +assign template[8] = + 1'b0; +assign template[9] = + (rom_instr_pt[23] | rom_instr_pt[27] + | rom_instr_pt[31] | rom_instr_pt[34] + | rom_instr_pt[35] | rom_instr_pt[43] + | rom_instr_pt[48] | rom_instr_pt[53] + | rom_instr_pt[59] | rom_instr_pt[64] + | rom_instr_pt[67] | rom_instr_pt[68] + | rom_instr_pt[72] | rom_instr_pt[75] + | rom_instr_pt[84] | rom_instr_pt[91] + | rom_instr_pt[94] | rom_instr_pt[100] + | rom_instr_pt[105] | rom_instr_pt[112] + | rom_instr_pt[114] | rom_instr_pt[115] + | rom_instr_pt[117] | rom_instr_pt[119] + | rom_instr_pt[120] | rom_instr_pt[126] + | rom_instr_pt[127] | rom_instr_pt[137] + | rom_instr_pt[139] | rom_instr_pt[141] + | rom_instr_pt[144] | rom_instr_pt[153] + | rom_instr_pt[156] | rom_instr_pt[163] + | rom_instr_pt[167] | rom_instr_pt[168] + | rom_instr_pt[177] | rom_instr_pt[182] + | rom_instr_pt[183] | rom_instr_pt[194] + | rom_instr_pt[195]); +assign template[10] = + (rom_instr_pt[22] | rom_instr_pt[24] + | rom_instr_pt[25] | rom_instr_pt[32] + | rom_instr_pt[33] | rom_instr_pt[36] + | rom_instr_pt[40] | rom_instr_pt[44] + | rom_instr_pt[45] | rom_instr_pt[47] + | rom_instr_pt[52] | rom_instr_pt[63] + | rom_instr_pt[83] | rom_instr_pt[88] + | rom_instr_pt[92] | rom_instr_pt[102] + | rom_instr_pt[106] | rom_instr_pt[151] + | rom_instr_pt[167] | rom_instr_pt[204] + | rom_instr_pt[211]); +assign template[11] = + (rom_instr_pt[8] | rom_instr_pt[30] + | rom_instr_pt[93] | rom_instr_pt[183] + ); +assign template[12] = + (rom_instr_pt[8] | rom_instr_pt[30] + ); +assign template[13] = + 1'b0; +assign template[14] = + (rom_instr_pt[12] | rom_instr_pt[27] + | rom_instr_pt[31] | rom_instr_pt[34] + | rom_instr_pt[43] | rom_instr_pt[45] + | rom_instr_pt[53] | rom_instr_pt[59] + | rom_instr_pt[63] | rom_instr_pt[64] + | rom_instr_pt[67] | rom_instr_pt[70] + | rom_instr_pt[75] | rom_instr_pt[79] + | rom_instr_pt[83] | rom_instr_pt[88] + | rom_instr_pt[93] | rom_instr_pt[94] + | rom_instr_pt[104] | rom_instr_pt[117] + | rom_instr_pt[120] | rom_instr_pt[126] + | rom_instr_pt[127] | rom_instr_pt[131] + | rom_instr_pt[156] | rom_instr_pt[165] + | rom_instr_pt[168] | rom_instr_pt[204] + | rom_instr_pt[211]); +assign template[15] = + (rom_instr_pt[3] | rom_instr_pt[23] + | rom_instr_pt[48] | rom_instr_pt[172] + | rom_instr_pt[175] | rom_instr_pt[202] + ); +assign template[16] = + (rom_instr_pt[4] | rom_instr_pt[34] + | rom_instr_pt[51] | rom_instr_pt[53] + | rom_instr_pt[63] | rom_instr_pt[75] + | rom_instr_pt[94] | rom_instr_pt[120] + | rom_instr_pt[151] | rom_instr_pt[165] + | rom_instr_pt[204]); +assign template[17] = + (rom_instr_pt[4] | rom_instr_pt[12] + | rom_instr_pt[27] | rom_instr_pt[31] + | rom_instr_pt[34] | rom_instr_pt[43] + | rom_instr_pt[45] | rom_instr_pt[59] + | rom_instr_pt[63] | rom_instr_pt[64] + | rom_instr_pt[67] | rom_instr_pt[75] + | rom_instr_pt[79] | rom_instr_pt[83] + | rom_instr_pt[88] | rom_instr_pt[104] + | rom_instr_pt[120] | rom_instr_pt[126] + | rom_instr_pt[127] | rom_instr_pt[131] + | rom_instr_pt[151] | rom_instr_pt[156] + | rom_instr_pt[168] | rom_instr_pt[204] + ); +assign template[18] = + (rom_instr_pt[4] | rom_instr_pt[124] + | rom_instr_pt[151]); +assign template[19] = + (rom_instr_pt[4] | rom_instr_pt[145] + | rom_instr_pt[151]); +assign template[20] = + (rom_instr_pt[4] | rom_instr_pt[56] + | rom_instr_pt[70] | rom_instr_pt[84] + | rom_instr_pt[117] | rom_instr_pt[137] + | rom_instr_pt[151] | rom_instr_pt[175] + ); +assign template[21] = + (rom_instr_pt[4] | rom_instr_pt[22] + | rom_instr_pt[23] | rom_instr_pt[43] + | rom_instr_pt[45] | rom_instr_pt[48] + | rom_instr_pt[53] | rom_instr_pt[88] + | rom_instr_pt[94] | rom_instr_pt[109] + | rom_instr_pt[145] | rom_instr_pt[151] + ); +assign template[22] = + (rom_instr_pt[3] | rom_instr_pt[4] + | rom_instr_pt[23] | rom_instr_pt[48] + | rom_instr_pt[61] | rom_instr_pt[65] + | rom_instr_pt[70] | rom_instr_pt[84] + | rom_instr_pt[109] | rom_instr_pt[117] + | rom_instr_pt[140] | rom_instr_pt[143] + | rom_instr_pt[151] | rom_instr_pt[157] + | rom_instr_pt[172] | rom_instr_pt[184] + | rom_instr_pt[198] | rom_instr_pt[202] + ); +assign template[23] = + (rom_instr_pt[4] | rom_instr_pt[22] + | rom_instr_pt[30] | rom_instr_pt[35] + | rom_instr_pt[51] | rom_instr_pt[68] + | rom_instr_pt[84] | rom_instr_pt[93] + | rom_instr_pt[100] | rom_instr_pt[109] + | rom_instr_pt[117] | rom_instr_pt[119] + | rom_instr_pt[124] | rom_instr_pt[141] + | rom_instr_pt[151] | rom_instr_pt[157] + | rom_instr_pt[182] | rom_instr_pt[184] + | rom_instr_pt[195] | rom_instr_pt[202] + ); +assign template[24] = + (rom_instr_pt[3] | rom_instr_pt[4] + | rom_instr_pt[22] | rom_instr_pt[25] + | rom_instr_pt[32] | rom_instr_pt[35] + | rom_instr_pt[47] | rom_instr_pt[52] + | rom_instr_pt[68] | rom_instr_pt[74] + | rom_instr_pt[100] | rom_instr_pt[106] + | rom_instr_pt[119] | rom_instr_pt[139] + | rom_instr_pt[141] | rom_instr_pt[145] + | rom_instr_pt[151] | rom_instr_pt[182] + | rom_instr_pt[195]); +assign template[25] = + (rom_instr_pt[4] | rom_instr_pt[20] + | rom_instr_pt[21] | rom_instr_pt[60] + | rom_instr_pt[70] | rom_instr_pt[84] + | rom_instr_pt[117] | rom_instr_pt[145] + | rom_instr_pt[151] | rom_instr_pt[157] + | rom_instr_pt[184]); +assign template[26] = + (rom_instr_pt[3] | rom_instr_pt[4] + | rom_instr_pt[6] | rom_instr_pt[8] + | rom_instr_pt[9] | rom_instr_pt[12] + | rom_instr_pt[16] | rom_instr_pt[22] + | rom_instr_pt[23] | rom_instr_pt[25] + | rom_instr_pt[27] | rom_instr_pt[30] + | rom_instr_pt[32] | rom_instr_pt[34] + | rom_instr_pt[35] | rom_instr_pt[43] + | rom_instr_pt[45] | rom_instr_pt[47] + | rom_instr_pt[48] | rom_instr_pt[51] + | rom_instr_pt[52] | rom_instr_pt[53] + | rom_instr_pt[59] | rom_instr_pt[64] + | rom_instr_pt[67] | rom_instr_pt[68] + | rom_instr_pt[70] | rom_instr_pt[74] + | rom_instr_pt[79] | rom_instr_pt[83] + | rom_instr_pt[84] | rom_instr_pt[88] + | rom_instr_pt[93] | rom_instr_pt[94] + | rom_instr_pt[100] | rom_instr_pt[104] + | rom_instr_pt[106] | rom_instr_pt[109] + | rom_instr_pt[117] | rom_instr_pt[119] + | rom_instr_pt[124] | rom_instr_pt[126] + | rom_instr_pt[127] | rom_instr_pt[131] + | rom_instr_pt[141] | rom_instr_pt[145] + | rom_instr_pt[151] | rom_instr_pt[156] + | rom_instr_pt[157] | rom_instr_pt[168] + | rom_instr_pt[182] | rom_instr_pt[184] + | rom_instr_pt[195] | rom_instr_pt[202] + | rom_instr_pt[211]); +assign template[27] = + (rom_instr_pt[4] | rom_instr_pt[6] + | rom_instr_pt[9] | rom_instr_pt[12] + | rom_instr_pt[16] | rom_instr_pt[20] + | rom_instr_pt[21] | rom_instr_pt[23] + | rom_instr_pt[27] | rom_instr_pt[34] + | rom_instr_pt[48] | rom_instr_pt[59] + | rom_instr_pt[60] | rom_instr_pt[61] + | rom_instr_pt[64] | rom_instr_pt[65] + | rom_instr_pt[79] | rom_instr_pt[83] + | rom_instr_pt[84] | rom_instr_pt[104] + | rom_instr_pt[109] | rom_instr_pt[117] + | rom_instr_pt[126] | rom_instr_pt[127] + | rom_instr_pt[130] | rom_instr_pt[131] + | rom_instr_pt[140] | rom_instr_pt[143] + | rom_instr_pt[145] | rom_instr_pt[151] + | rom_instr_pt[157] | rom_instr_pt[168] + | rom_instr_pt[172] | rom_instr_pt[184] + | rom_instr_pt[198] | rom_instr_pt[209] + ); +assign template[28] = + (rom_instr_pt[4] | rom_instr_pt[6] + | rom_instr_pt[9] | rom_instr_pt[12] + | rom_instr_pt[16] | rom_instr_pt[20] + | rom_instr_pt[21] | rom_instr_pt[23] + | rom_instr_pt[25] | rom_instr_pt[27] + | rom_instr_pt[32] | rom_instr_pt[34] + | rom_instr_pt[35] | rom_instr_pt[43] + | rom_instr_pt[45] | rom_instr_pt[47] + | rom_instr_pt[48] | rom_instr_pt[52] + | rom_instr_pt[53] | rom_instr_pt[59] + | rom_instr_pt[60] | rom_instr_pt[63] + | rom_instr_pt[64] | rom_instr_pt[67] + | rom_instr_pt[68] | rom_instr_pt[70] + | rom_instr_pt[74] | rom_instr_pt[79] + | rom_instr_pt[83] | rom_instr_pt[84] + | rom_instr_pt[88] | rom_instr_pt[94] + | rom_instr_pt[100] | rom_instr_pt[104] + | rom_instr_pt[106] | rom_instr_pt[117] + | rom_instr_pt[119] | rom_instr_pt[126] + | rom_instr_pt[127] | rom_instr_pt[131] + | rom_instr_pt[141] | rom_instr_pt[145] + | rom_instr_pt[151] | rom_instr_pt[156] + | rom_instr_pt[157] | rom_instr_pt[165] + | rom_instr_pt[168] | rom_instr_pt[182] + | rom_instr_pt[184] | rom_instr_pt[195] + | rom_instr_pt[204]); +assign template[29] = + (rom_instr_pt[3] | rom_instr_pt[4] + | rom_instr_pt[8] | rom_instr_pt[12] + | rom_instr_pt[20] | rom_instr_pt[21] + | rom_instr_pt[23] | rom_instr_pt[25] + | rom_instr_pt[27] | rom_instr_pt[32] + | rom_instr_pt[34] | rom_instr_pt[35] + | rom_instr_pt[43] | rom_instr_pt[45] + | rom_instr_pt[47] | rom_instr_pt[48] + | rom_instr_pt[52] | rom_instr_pt[53] + | rom_instr_pt[59] | rom_instr_pt[61] + | rom_instr_pt[63] | rom_instr_pt[64] + | rom_instr_pt[65] | rom_instr_pt[67] + | rom_instr_pt[68] | rom_instr_pt[74] + | rom_instr_pt[79] | rom_instr_pt[83] + | rom_instr_pt[86] | rom_instr_pt[88] + | rom_instr_pt[94] | rom_instr_pt[100] + | rom_instr_pt[104] | rom_instr_pt[106] + | rom_instr_pt[109] | rom_instr_pt[119] + | rom_instr_pt[126] | rom_instr_pt[127] + | rom_instr_pt[131] | rom_instr_pt[139] + | rom_instr_pt[141] | rom_instr_pt[143] + | rom_instr_pt[145] | rom_instr_pt[151] + | rom_instr_pt[156] | rom_instr_pt[165] + | rom_instr_pt[168] | rom_instr_pt[172] + | rom_instr_pt[182] | rom_instr_pt[195] + | rom_instr_pt[198] | rom_instr_pt[204] + ); +assign template[30] = + (rom_instr_pt[4] | rom_instr_pt[12] + | rom_instr_pt[15] | rom_instr_pt[20] + | rom_instr_pt[23] | rom_instr_pt[24] + | rom_instr_pt[25] | rom_instr_pt[27] + | rom_instr_pt[32] | rom_instr_pt[34] + | rom_instr_pt[35] | rom_instr_pt[43] + | rom_instr_pt[45] | rom_instr_pt[47] + | rom_instr_pt[48] | rom_instr_pt[52] + | rom_instr_pt[53] | rom_instr_pt[59] + | rom_instr_pt[63] | rom_instr_pt[64] + | rom_instr_pt[67] | rom_instr_pt[68] + | rom_instr_pt[74] | rom_instr_pt[75] + | rom_instr_pt[79] | rom_instr_pt[83] + | rom_instr_pt[88] | rom_instr_pt[94] + | rom_instr_pt[100] | rom_instr_pt[102] + | rom_instr_pt[104] | rom_instr_pt[106] + | rom_instr_pt[119] | rom_instr_pt[120] + | rom_instr_pt[126] | rom_instr_pt[127] + | rom_instr_pt[131] | rom_instr_pt[139] + | rom_instr_pt[141] | rom_instr_pt[145] + | rom_instr_pt[156] | rom_instr_pt[165] + | rom_instr_pt[168] | rom_instr_pt[182] + | rom_instr_pt[195] | rom_instr_pt[204] + ); +assign template[31] = + (rom_instr_pt[14] | rom_instr_pt[24] + | rom_instr_pt[33] | rom_instr_pt[38] + | rom_instr_pt[62] | rom_instr_pt[77] + | rom_instr_pt[89] | rom_instr_pt[91] + | rom_instr_pt[98] | rom_instr_pt[99] + | rom_instr_pt[103] | rom_instr_pt[108] + | rom_instr_pt[122] | rom_instr_pt[170] + ); +assign ucode_end = + (rom_instr_pt[107] | rom_instr_pt[139] + | rom_instr_pt[146] | rom_instr_pt[152] + | rom_instr_pt[154] | rom_instr_pt[159] + | rom_instr_pt[160] | rom_instr_pt[172] + | rom_instr_pt[176] | rom_instr_pt[205] + | rom_instr_pt[209]); +assign ucode_end_early = + (rom_instr_pt[87] | rom_instr_pt[111] + | rom_instr_pt[125] | rom_instr_pt[207] + ); +assign loop_begin = + (rom_instr_pt[36] | rom_instr_pt[62] + | rom_instr_pt[66] | rom_instr_pt[68] + | rom_instr_pt[71] | rom_instr_pt[80] + | rom_instr_pt[81] | rom_instr_pt[96] + | rom_instr_pt[105] | rom_instr_pt[106] + | rom_instr_pt[121] | rom_instr_pt[123] + | rom_instr_pt[132] | rom_instr_pt[133] + | rom_instr_pt[135]); +assign loop_end = + (rom_instr_pt[55] | rom_instr_pt[87] + | rom_instr_pt[158] | rom_instr_pt[199] + | rom_instr_pt[200] | rom_instr_pt[208] + | rom_instr_pt[209]); +assign count_src[0] = + (rom_instr_pt[189] | rom_instr_pt[212] + | rom_instr_pt[218] | rom_instr_pt[224] + ); +assign count_src[1] = + (rom_instr_pt[161] | rom_instr_pt[218] + | rom_instr_pt[220] | rom_instr_pt[224] + ); +assign count_src[2] = + (rom_instr_pt[188] | rom_instr_pt[213] + | rom_instr_pt[218] | rom_instr_pt[224] + ); +assign ext_rt = + (rom_instr_pt[1] | rom_instr_pt[4] + | rom_instr_pt[6] | rom_instr_pt[9] + | rom_instr_pt[11] | rom_instr_pt[12] + | rom_instr_pt[13] | rom_instr_pt[19] + | rom_instr_pt[21] | rom_instr_pt[23] + | rom_instr_pt[28] | rom_instr_pt[32] + | rom_instr_pt[37] | rom_instr_pt[41] + | rom_instr_pt[42] | rom_instr_pt[43] + | rom_instr_pt[47] | rom_instr_pt[48] + | rom_instr_pt[49] | rom_instr_pt[52] + | rom_instr_pt[54] | rom_instr_pt[58] + | rom_instr_pt[61] | rom_instr_pt[63] + | rom_instr_pt[65] | rom_instr_pt[67] + | rom_instr_pt[69] | rom_instr_pt[76] + | rom_instr_pt[82] | rom_instr_pt[97] + | rom_instr_pt[113] | rom_instr_pt[118] + | rom_instr_pt[120] | rom_instr_pt[128] + | rom_instr_pt[134] | rom_instr_pt[142] + | rom_instr_pt[147] | rom_instr_pt[166] + | rom_instr_pt[173] | rom_instr_pt[181] + | rom_instr_pt[186] | rom_instr_pt[204] + | rom_instr_pt[210] | rom_instr_pt[215] + | rom_instr_pt[219]); +assign ext_s1 = + (rom_instr_pt[23] | rom_instr_pt[28] + | rom_instr_pt[41] | rom_instr_pt[42] + | rom_instr_pt[48] | rom_instr_pt[50] + | rom_instr_pt[54] | rom_instr_pt[57] + | rom_instr_pt[58] | rom_instr_pt[63] + | rom_instr_pt[67] | rom_instr_pt[69] + | rom_instr_pt[76] | rom_instr_pt[82] + | rom_instr_pt[90] | rom_instr_pt[101] + | rom_instr_pt[113] | rom_instr_pt[115] + | rom_instr_pt[116] | rom_instr_pt[118] + | rom_instr_pt[134] | rom_instr_pt[147] + | rom_instr_pt[148] | rom_instr_pt[149] + | rom_instr_pt[155] | rom_instr_pt[162] + | rom_instr_pt[166] | rom_instr_pt[169] + | rom_instr_pt[172] | rom_instr_pt[173] + | rom_instr_pt[178] | rom_instr_pt[179] + | rom_instr_pt[181] | rom_instr_pt[201] + | rom_instr_pt[204] | rom_instr_pt[210] + | rom_instr_pt[219]); +assign ext_s2 = + (rom_instr_pt[23] | rom_instr_pt[32] + | rom_instr_pt[47] | rom_instr_pt[48] + | rom_instr_pt[52] | rom_instr_pt[54] + | rom_instr_pt[63] | rom_instr_pt[85] + | rom_instr_pt[90] | rom_instr_pt[95] + | rom_instr_pt[145] | rom_instr_pt[148] + | rom_instr_pt[172] | rom_instr_pt[181] + | rom_instr_pt[197] | rom_instr_pt[204] + | rom_instr_pt[210] | rom_instr_pt[214] + ); +assign ext_s3 = + (rom_instr_pt[46] | rom_instr_pt[58] + | rom_instr_pt[68] | rom_instr_pt[115] + | rom_instr_pt[116] | rom_instr_pt[119] + | rom_instr_pt[134] | rom_instr_pt[147] + | rom_instr_pt[149] | rom_instr_pt[178] + | rom_instr_pt[215]); +assign sel0_5 = + (rom_instr_pt[148]); +assign sel6_10[0] = + (rom_instr_pt[6] | rom_instr_pt[9] + | rom_instr_pt[19] | rom_instr_pt[136] + | rom_instr_pt[146] | rom_instr_pt[150] + | rom_instr_pt[172] | rom_instr_pt[198] + ); +assign sel6_10[1] = + (rom_instr_pt[6] | rom_instr_pt[9] + | rom_instr_pt[11] | rom_instr_pt[12] + | rom_instr_pt[19] | rom_instr_pt[37] + | rom_instr_pt[73] | rom_instr_pt[79] + | rom_instr_pt[97] | rom_instr_pt[104] + | rom_instr_pt[145] | rom_instr_pt[148] + | rom_instr_pt[155] | rom_instr_pt[174] + | rom_instr_pt[191] | rom_instr_pt[193] + | rom_instr_pt[214]); +assign sel11_15[0] = + (rom_instr_pt[85] | rom_instr_pt[110] + | rom_instr_pt[153] | rom_instr_pt[157] + | rom_instr_pt[179] | rom_instr_pt[180] + | rom_instr_pt[196]); +assign sel11_15[1] = + (rom_instr_pt[1] | rom_instr_pt[4] + | rom_instr_pt[7] | rom_instr_pt[13] + | rom_instr_pt[32] | rom_instr_pt[46] + | rom_instr_pt[47] | rom_instr_pt[49] + | rom_instr_pt[52] | rom_instr_pt[85] + | rom_instr_pt[110] | rom_instr_pt[128] + | rom_instr_pt[136] | rom_instr_pt[142] + | rom_instr_pt[146] | rom_instr_pt[150] + | rom_instr_pt[153] | rom_instr_pt[157] + | rom_instr_pt[179] | rom_instr_pt[180] + | rom_instr_pt[196] | rom_instr_pt[197] + | rom_instr_pt[201] | rom_instr_pt[221] + | rom_instr_pt[223]); +assign sel16_20[0] = + (rom_instr_pt[17] | rom_instr_pt[20] + | rom_instr_pt[21]); +assign sel16_20[1] = + (rom_instr_pt[1] | rom_instr_pt[2] + | rom_instr_pt[6] | rom_instr_pt[9] + | rom_instr_pt[19] | rom_instr_pt[26] + | rom_instr_pt[29] | rom_instr_pt[35] + | rom_instr_pt[39] | rom_instr_pt[42] + | rom_instr_pt[46] | rom_instr_pt[57] + | rom_instr_pt[61] | rom_instr_pt[65] + | rom_instr_pt[68] | rom_instr_pt[74] + | rom_instr_pt[101] | rom_instr_pt[106] + | rom_instr_pt[115] | rom_instr_pt[116] + | rom_instr_pt[119] | rom_instr_pt[136] + | rom_instr_pt[146] | rom_instr_pt[149] + | rom_instr_pt[150] | rom_instr_pt[190] + | rom_instr_pt[191] | rom_instr_pt[193] + | rom_instr_pt[195]); +assign sel21_25[0] = + 1'b0; +assign sel21_25[1] = + (rom_instr_pt[1] | rom_instr_pt[2] + | rom_instr_pt[29] | rom_instr_pt[39] + | rom_instr_pt[42] | rom_instr_pt[115] + | rom_instr_pt[136] | rom_instr_pt[138] + | rom_instr_pt[191] | rom_instr_pt[193] + ); +assign sel26_30 = + (rom_instr_pt[1] | rom_instr_pt[2] + | rom_instr_pt[29] | rom_instr_pt[39] + | rom_instr_pt[42] | rom_instr_pt[115] + | rom_instr_pt[136] | rom_instr_pt[138] + | rom_instr_pt[191] | rom_instr_pt[193] + ); +assign sel31 = + (rom_instr_pt[2] | rom_instr_pt[5] + | rom_instr_pt[29] | rom_instr_pt[39] + | rom_instr_pt[42] | rom_instr_pt[136] + | rom_instr_pt[148] | rom_instr_pt[149] + | rom_instr_pt[191] | rom_instr_pt[192] + ); +assign cr_bf2fxm = + 1'b0; +assign skip_cond = + (rom_instr_pt[23] | rom_instr_pt[43] + | rom_instr_pt[48] | rom_instr_pt[54] + | rom_instr_pt[63] | rom_instr_pt[78] + | rom_instr_pt[95] | rom_instr_pt[113] + | rom_instr_pt[118] | rom_instr_pt[120] + | rom_instr_pt[204]); +assign skip_zero = + (rom_instr_pt[67] | rom_instr_pt[155] + | rom_instr_pt[166] | rom_instr_pt[186] + | rom_instr_pt[215]); +assign skip_nop = + 1'b0; +assign loop_addr[0] = + 1'b0; +assign loop_addr[1] = + 1'b0; +assign loop_addr[2] = + 1'b0; +assign loop_addr[3] = + 1'b0; +assign loop_addr[4] = + 1'b0; +assign loop_addr[5] = + 1'b0; +assign loop_addr[6] = + 1'b0; +assign loop_addr[7] = + 1'b0; +assign loop_addr[8] = + 1'b0; +assign loop_addr[9] = + 1'b0; +assign loop_init[0] = + (rom_instr_pt[69] | rom_instr_pt[76] + | rom_instr_pt[115] | rom_instr_pt[116] + | rom_instr_pt[120]); +assign loop_init[1] = + (rom_instr_pt[225]); +assign loop_init[2] = + (rom_instr_pt[78]); +assign ep = + (rom_instr_pt[32] | rom_instr_pt[46] + | rom_instr_pt[47] | rom_instr_pt[116] + | rom_instr_pt[149] | rom_instr_pt[195] + ); + +//assign_end + + // Old FDIV/FSQRT + //end generate; + //| 1111000000 | 11111100000000000000100000110000 0 - 0 - --- 1 0 1 0 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # fre s0, s1 #FDIV + //| 1111000010 | 11111100010-----0000000000110010 0 - 0 - --- 1 0 0 1 0 00 01 00 00 0 0 0 0 - 0 ---------- --- - | # fmul s2,FA,s0 + //| 1111000100 | 11111100001000000000000001111010 0 - 0 - --- 1 1 1 1 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # fmadd s1,s0,s1,s0 + //| 1111000110 | 11111100011000110001100011111010 0 - 0 - --- 1 1 1 1 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # fmadd s3,s3,s3,s3 + //| 1111001000 | 11111100001000000001000011111010 0 - 0 - --- 1 1 1 1 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # fmadd s1,s0,s3,s2 + //| 1111001010 | 11111100000----------00001111100 0 - 0 - --- 1 0 0 1 0 00 10 11 00 0 0 0 0 - 0 ---------- --- - | # fnmsub s0,FB,s1,FA + //| 1111001100 | 11111100000----------00001111100 0 - 0 - --- 1 0 0 1 0 00 10 11 00 0 0 0 0 - 0 ---------- --- - | # fnmsub s0,FB,s1,FA + //| 1111010000 | 11111100000000000000100000110000 0 - 0 - --- 1 0 1 0 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # fre s0, s1 #FDIVS + //| 1111010010 | 11111100000-----0000000000110010 0 - 0 - --- 1 0 0 1 0 00 01 00 00 0 0 0 0 - 0 ---------- --- - | # fmul s0,FA,s0 + //| 1111010100 | 11101100011000000000000011111010 0 - 0 - --- 1 1 1 1 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # fmadds s3,s0,s3,s0 + //| 1111010110 | 11101100010----------00011111100 0 - 0 - --- 1 0 0 1 0 00 10 11 00 0 0 0 0 - 0 ---------- --- - | # fnmsub s2,FB,s3,FA + //| 1111011000 | 111011-----00001000000000010001- 1 - 0 - --- 0 1 1 1 0 01 00 00 00 0 1 0 0 - 0 ---------- --- - | # fmuls_uc FT,s1,s0,s0 include s0 in 16-20 + //| 1111100000 | 11111100000000000000100000110100 0 - 0 - --- 1 0 1 0 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # frsqrte s0, , ,s1 #FSQRT + //| 1111100010 | 111111000100000000000-----110010 0 - 0 - --- 1 1 0 0 0 00 00 00 1- 0 0 0 0 - 0 ---------- --- - | # fmul s2,s0,FB, + //| 1111100100 | 11111100011000100001000000111010 0 - 0 - --- 1 1 1 1 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # fmadd s3,s2,s0,s2 + //| 1111100110 | 1111110000000011-----00011111100 0 - 0 - --- 1 1 0 1 0 00 00 01 00 0 0 0 0 - 0 ---------- --- - | # fnmsub s0,s3,s3,FB + //| 1111101000 | 11111100011000000001100010111010 0 - 0 - --- 1 1 1 1 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # fmadd s3,s0,s2,s3 + //| 1111101010 | 1111110001000011-----00011111100 0 - 0 - --- 1 1 0 1 0 00 00 01 00 0 0 0 0 - 0 ---------- --- - | # fnmsub s2,s3,s3,FB + //| 1111101100 | 111111-----00001000000000010001- 1 - 0 - --- 0 1 1 1 0 01 00 00 00 0 1 0 0 - 0 ---------- --- - | # fmul_uc FT,s1,s0,s0 include s0 in 16-20 + //| 1111110000 | 11111100000000000000100000110100 0 - 0 - --- 1 0 1 0 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # frsqrte s0, , ,s1 #FSQRTS + //| 1111110010 | 111111000110000000000-----110010 0 - 0 - --- 1 1 0 0 0 00 00 00 1- 0 0 0 0 - 0 ---------- --- - | # fmul s2,s0,FB, + //| 1111110100 | 11101100001000000001100010111010 0 - 0 - --- 1 1 1 1 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # fmadds s1,s0,s1,s2 + //| 1111110110 | 1110110000000001-----00001111100 0 - 0 - --- 1 1 0 1 0 00 00 01 00 0 0 0 0 - 0 ---------- --- - | # fnmsubs s0,s1,s1,FB + //| 1111111000 | 1110110000000001-----00011111100 0 - 0 - --- 1 1 0 1 0 00 00 01 00 0 0 0 0 - 0 ---------- --- - | # fnmsubs s0,s1,s3,FB + //32-bit core + //c32: if (regmode = 5) generate begin + //end generate; + + + // ??? Do I want to optimize any terms? + // ??? Which is better: on-off, or on-dc? + // ??? Do we want to DC template fields not being used? + + assign rom_addr_d = rom_addr; + + assign rom_data = {template, ucode_end, ucode_end_early, loop_begin, loop_end, count_src, ext_rt, ext_s1, ext_s2, ext_s3, sel0_5, sel6_10, sel11_15, sel16_20, sel21_25, sel26_30, sel31, cr_bf2fxm, skip_cond, skip_zero, skip_nop, loop_addr, loop_init, ep}; + + //--------------------------------------------------------------------- + // Latches + //--------------------------------------------------------------------- + + tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(0)) rom_addr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rom_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rom_addr_offset:rom_addr_offset + 10 - 1]), + .scout(sov[rom_addr_offset:rom_addr_offset + 10 - 1]), + .din(rom_addr_d), + .dout(rom_addr_l2) + ); + + //--------------------------------------------------------------------- + // Scan + //--------------------------------------------------------------------- + assign siv[0:scan_right] = {sov[1:scan_right], scan_in}; + assign scan_out = sov[0]; + +endmodule diff --git a/dev/verilog/work/iuq_uc_rom_odd.v b/dev/verilog/work/iuq_uc_rom_odd.v new file mode 100755 index 0000000..6eb1fab --- /dev/null +++ b/dev/verilog/work/iuq_uc_rom_odd.v @@ -0,0 +1,2039 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//******************************************************************** +//* +//* TITLE: IU Microcode Code +//* +//* NAME: iuq_uc_rom_odd.v +//* +//********************************************************************* + +`include "tri_a2o.vh" + + +module iuq_uc_rom_odd( + vdd, + gnd, + nclk, + pc_iu_func_sl_thold_0_b, + pc_iu_sg_0, + force_t, + d_mode, + delay_lclkr, + mpw1_b, + mpw2_b, + scan_in, + scan_out, + rom_act, + rom_addr, + rom_data +); + //parameter ucode_width = 72; + + + inout vdd; + + inout gnd; + + (* pin_data ="PIN_FUNCTION=/G_CLK/" *) + input [0:`NCLK_WIDTH-1] nclk; + input pc_iu_func_sl_thold_0_b; + input pc_iu_sg_0; + input force_t; + input d_mode; + input delay_lclkr; + input mpw1_b; + input mpw2_b; + input scan_in; + output scan_out; + + input rom_act; + input [0:9] rom_addr; + output [0:71] rom_data; + + //@@ Signal Declarations + wire [1:200] rom_instr_pt; + wire [0:2] count_src; + wire cr_bf2fxm; + wire ep; + wire ext_rt; + wire ext_s1; + wire ext_s2; + wire ext_s3; + wire [0:9] loop_addr; + wire loop_begin; + wire loop_end; + wire [0:2] loop_init; + wire sel0_5; + wire [0:1] sel11_15; + wire [0:1] sel16_20; + wire [0:1] sel21_25; + wire sel26_30; + wire sel31; + wire [0:1] sel6_10; + wire skip_cond; + wire skip_nop; + wire skip_zero; + wire [0:31] template; + wire ucode_end; + wire ucode_end_early; + + parameter rom_addr_offset = 0; + parameter scan_right = rom_addr_offset + 10 - 1; + + // Latches + wire [0:9] rom_addr_d; + wire [0:9] rom_addr_l2; + wire [0:scan_right] siv; + wire [0:scan_right] sov; + +//64-bit core +//c64: if (regmode = 6) generate begin + +/* +//table_start +?TABLE rom_instr LISTING(final) OPTIMIZE PARMS(ON-SET, OFF-SET); +*INPUTS*========*OUTPUTS*===============================================================================================* +| | | +| rom_addr_l2 | template ucode_end | +| | | | | ucode_end_early | +| | | | | | loop_begin | +| | | | | | | loop_end | +| | | | | | | | count_src | -- Can DC if not (loop_begin or loop_end) +| | | | | | | | | | +| | | | | | | | | ext_rt | +| | | | | | | | | | ext_s1 | +| | | | | | | | | | | ext_s2 | +| | | | | | | | | | | | ext_s3 | +| | | | | | | | | | | | | | +| | | | | | | | | | | | | sel0_5 | +| | | | | | | | | | | | | | sel6_10 | +| | | | | | | | | | | | | | | sel11_15 | +| | | | | | | | | | | | | | | | sel16_20 | +| | | | | | | | | | | | | | | | | sel21_25 | +| | | | | | | | | | | | | | | | | | sel26_30 | +| | | | | | | | | | | | | | | | | | | sel31 | +| | | | | | | | | | | | | | | | | | | | | +| | | | | | | | | | | | | | | | | | | | cr_bf2fxm | +| | | | | | | | | | | | | | | | | | | | | skip_cond | +| | | | | | | | | | | | | | | | | | | | | | skip_zero | -- Can DC if loop_begin not set +| | | | | | | | | | | | | | | | | | | | | | | skip_nop | -- Optimize to only be in odd side +| | | | | | | | | | | | | | | | | | | | | | | | loop_addr | -- Can DC if loop_end not set; always odd side +| | | | | | | | | | | | | | | | | | | | | | | | | loop_init| -- 1 less than # of times to loop; Can DC if not loop_begin or not count_src=111 +| | | | | | | | | | | | | | | | | | | | | | | | | | ep | +| | | | 1111111111222222222233 | | | | | | | | | | | | | | | | | | | | | | | | +| 0123456789 | 01234567890123456789012345678901 | | | | 012 | | | | | 01 01 01 01 | | | | | | 0123456789 012 | | +*TYPE*==========+=======================================================================================================+ +| PPPPPPPPPP | SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS S S S S SSS S S S S S SS SS SS SS S S S S S S SSSSSSSSSS SSS S | +*OPTIMIZE*----->| AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA B B B B CCC X X X X X XX XX XX XX X X X X X X XXXXXXXXXX XYX X | +*TERMS*=========+=======================================================================================================+ +| 0000000001 | 10001000001000000000000000000000 0 0 0 - --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # lbz s1,0(s0) +| 0000000011 | 01010000001000100100010000101110 0 0 0 - --- 1 1 1 - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # rlwimi s2,s1,8,16,23 +| 0000000101 | 01111100010000100000101101111000 0 0 0 - --- 1 1 1 - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- - | # or s2,s2,s1 -skip_c +| 0000000111 | 01101000000-----0000000000000000 1 - 0 - --- 0 1 - - 0 00 01 00 00 0 0 0 0 - 0 ---------- --- - | # xori RA,s0,0 + +| 0000010001 | 01111100001-----000000001010111- 0 0 0 - --- 1 0 1 - 0 00 01 00 00 0 - 0 0 - 0 ---------- --- 1 | # lbzx s1,RA,s0 +| 0000010011 | 01111100010-----000110001010111- 0 0 0 - --- 1 0 1 - 0 00 01 00 00 0 - 0 0 - 0 ---------- --- 1 | # lbzx s2,RA,s3 +| 0000010101 | 01010100010000100100010000101110 0 0 0 - --- 1 1 - - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- 0 | # rlwinm s2,s2,8,16,23 -skip_c +| 0000010111 | 01101000010-----0000000000000000 0 1 0 - --- 0 1 - - 0 00 11 00 00 0 0 0 0 - 0 ---------- --- 0 | # xori RT,s2,0 -end for non-update + +| 0000100001 | 10001000001000000000000000000000 0 0 0 - --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # lbz s1,0(s0) +| 0000100011 | 01010000001000100100010000101110 0 0 0 - --- 1 1 1 - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # rlwimi s2,s1,8,16,23 +| 0000100101 | 01111100010000100000101101111000 0 0 0 - --- 1 1 1 - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- - | # or s2,s2,s1 -skip_c +| 0000100111 | 01101000000-----0000000000000000 1 - 0 - --- 0 1 - - 0 00 01 00 00 0 0 0 0 - 0 ---------- --- - | # xori RA,s0,0 + +| 0000110001 | 0111110000000000-----01000010100 0 0 0 - --- 1 1 0 - 0 00 00 01 00 0 0 0 0 - 0 ---------- --- - | # add s0,s0,RB +| 0000110011 | 10001000010000000000000000000001 0 0 0 - --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # lbz s2,1(s0) +| 0000110101 | 01010100010000100100010000101110 0 0 0 - --- 1 1 - - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- - | # rlwinm s2,s2,8,16,23 -skip_c +| 0000110111 | 01111100010----------11100110100 0 1 0 - --- 0 1 - - 0 00 11 -- 00 0 0 0 0 - 0 ---------- --- - | # extsh RT,s2 -end for non-update + +| 0001000001 | 10001000010000000000000000000000 0 0 0 - --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # lbz s2,0(s0) +| 0001000011 | 01010100010000100100000000111110 0 0 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # rlwinm s2,s2,8,0,31 +| 0001000101 | 01111100010000100000101101111000 0 0 0 1 111 1 1 1 - 0 00 00 00 00 0 0 0 0 - 0 0001000010 --- - | # or s2,s2,s1 -loop_end +| 0001000111 | 01010000010000101000010000101110 0 0 0 - --- 1 1 1 - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- - | # rlwimi s2,s2,16,16,23 -skip_c +| 0001001001 | 01101000010-----0000000000000000 0 1 0 - --- 0 1 - - 0 00 11 00 00 0 0 0 0 - 0 ---------- --- - | # xori RT,s2,0 -end for non-update + +| 0001010001 | 01111100010-----000000001010111- 0 0 0 - --- 1 0 1 - 0 00 01 00 00 0 - 0 0 - 0 ---------- --- 1 | # lbzx s2,RA,s0 +| 0001010011 | 01010100010000100100000000111110 0 0 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- 0 | # rlwinm s2,s2,8,0,31 +| 0001010101 | 01111100010000100000101101111000 0 0 0 1 111 1 1 1 - 0 00 00 00 00 0 0 0 0 - 0 0001010010 --- 0 | # or s2,s2,s1 -loop_end +| 0001010111 | 01010000010000101000010000101110 0 0 0 - --- 1 1 1 - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- 0 | # rlwimi s2,s2,16,16,23 -skip_c +| 0001011001 | 01101000010-----0000000000000000 0 1 0 - --- 0 1 - - 0 00 11 00 00 0 0 0 0 - 0 ---------- --- 0 | # xori RT,s2,0 -end for non-update +| 0001011011 | 011111-----000010000001000010100 1 - 0 - --- 0 1 1 - 0 10 00 00 00 0 0 0 0 - 0 ---------- --- 0 | # add RA,s1,s0 + +| 0001100001 | 1000100001000000---------------- 0 - 0 - --- 1 1 - - 0 00 00 01 01 1 1 0 0 - 0 ---------- --- - | # lbz s2,D(s0) +| 0001100011 | 01010100010000100100000000111110 0 - 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # rlwinm s2,s2,8,0,31 +| 0001100101 | 01111100010000100000101101111000 0 - 0 1 111 1 1 1 - 0 00 00 00 00 0 0 0 0 - 0 0001100010 --- - | # or s2,s2,s1 -loop_end +| 0001100111 | 01010000010000101000010000101110 0 - 0 - --- 1 1 1 - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- - | # rlwimi s2,s2,16,16,23 -skip_c +| 0001101001 | 01111100010----------11110110100 1 - 0 - --- 0 1 - - 0 00 11 -- 00 0 0 0 0 - 0 ---------- --- - | # extsw RT,s2 + +| 0001110001 | 01111100010-----000000001010111- 0 0 0 - --- 1 0 1 - 0 00 01 00 00 0 - 0 0 - 0 ---------- --- - | # lbzx s2,RA,s0 +| 0001110011 | 01010100010000100100000000111110 0 0 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # rlwinm s2,s2,8,0,31 +| 0001110101 | 01111100010000100000101101111000 0 0 0 1 111 1 1 1 - 0 00 00 00 00 0 0 0 0 - 0 0001110010 --- - | # or s2,s2,s1 -loop_end +| 0001110111 | 01010000010000101000010000101110 0 0 0 - --- 1 1 1 - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- - | # rlwimi s2,s2,16,16,23 -skip_c +| 0001111001 | 01111100010----------11110110100 0 1 0 - --- 0 1 - - 0 00 11 -- 00 0 0 0 0 - 0 ---------- --- - | # extsw RT,s2 -end for non-update +| 0001111011 | 011111-----000010000001000010100 1 - 0 - --- 0 1 1 - 0 10 00 00 00 0 0 0 0 - 0 ---------- --- - | # add RA,s1,s0 + +| 0010000001 | 10001000010000000000000000000000 0 0 0 - --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # lbz s2,0(s0) +| 0010000011 | 01111000010000100100010111100100 0 0 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # rldicr s2,s2,8,55 +| 0010000101 | 01111100010000100000101101111000 0 0 0 1 111 1 1 1 - 0 00 00 00 00 0 0 0 0 - 0 0010000010 --- - | # or s2,s2,s1 -loop_end +| 0010000111 | 01111000001000010100000000000000 0 0 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- - | # rldicl s1,s1,8,0 -skip_c +| 0010001001 | 00111000010000010000000000000000 0 0 0 - 111 1 1 - - 0 00 00 00 00 0 0 0 1 - 0 0010000110 --- - | # addi s2,s1,0 -skip_c +| 0010001011 | 001110-------------------------0 1 - 0 - --- 0 0 - - 0 10 01 01 01 1 0 0 0 - 0 ---------- --- - | # addi RA,RA,DS + +| 0010010001 | 01111100010-----000000001010111- 0 0 0 - --- 1 0 1 - 0 00 01 00 00 0 - 0 0 - 0 ---------- --- 1 | # lbzx s2,RA,s0 +| 0010010011 | 01111000010000100100010111100100 0 0 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- 0 | # rldicr s2,s2,8,55 +| 0010010101 | 01111100010000100000101101111000 0 0 0 1 111 1 1 1 - 0 00 00 00 00 0 0 0 0 - 0 0010010010 --- 0 | # or s2,s2,s1 -loop_end +| 0010010111 | 01111000001000010100000000000000 0 0 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- 0 | # rldicl s1,s1,8,0 -skip_c +| 0010011001 | 00111000010000010000000000000000 0 0 0 - 111 1 1 - - 0 00 00 00 00 0 0 0 1 - 0 0010010110 --- 0 | # addi s2,s1,0 -skip_c +| 0010011011 | 00111000001-----1111111111111001 0 - 0 - --- 1 0 - - 0 00 01 00 00 0 0 0 0 - 0 ---------- --- 0 | # addi s1,RA,-7 + +| 0010100001 | -------------------------------- 0 - 0 - --- - - - - - -- -- -- -- - - 0 - - 1 ---------- --- - | # nop +| 0010100011 | 00111000000000000000000000000100 0 - 0 1 100 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 0010100010 --- - | # addi s0,s0,4 -loop_end + +| 0010110001 | -------------------------------- 0 - 0 - --- - - - - - -- -- -- -- - - 0 - - 1 ---------- --- - | # nop +| 0010110011 | 01010100010000101100000000111110 0 - 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # rlwinm s2,s2,24,0,31 +| 0010110101 | 01010000001000101000001000011110 0 - 0 0 --- 1 1 1 - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # rlwimi s2,s1,16,8,15 +| 0010110111 | 01010000001000100100010000101110 0 - 0 0 --- 1 1 1 - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # rlwimi s2,s1,8,16,23 +| 0010111001 | 00111000000000000000000000000100 0 - 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # addi s0,s0,4 +| 0010111011 | -------------------------------- 0 - 0 - 101 - - - - - -- -- -- -- - - 0 - - 1 0010110010 --- - | # nop +| 0010111101 | 01010100010000100100000000101110 0 - 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # rlwinm s2,s2,8,0,23 +| 0010111111 | 01111100010000100000101101111000 0 - 0 1 000 1 1 1 - 0 00 00 00 00 0 0 0 0 - 0 0010111100 --- - | # or s2,s2,s1 -loop_end +| 0011000001 | -------------------------------- 0 - 0 1 001 - - - - - -- -- -- -- - - 0 - - 1 0011000000 --- - | # nop -loop_end + +| 0011010001 | 00111000000-----0000000000000000 0 - 0 - --- 1 0 - - 0 00 01 00 00 0 0 0 0 - 0 ---------- --- - | # addi s0,RA,0 +| 0011010011 | 00111000000000000000000000000001 0 - 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # addi s0,s0,1 +| 0011010101 | 0111110000100000-----0001010111- 0 - 0 0 --- 1 1 0 - 0 00 00 01 00 0 - 0 0 - 0 ---------- --- - | # lbzx s1,s0,RB +| 0011010111 | 01010000001000101000001000011110 0 - 0 0 --- 1 1 1 - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # rlwimi s2,s1,16,8,15 +| 0011011001 | 00111000000000000000000000000001 0 - 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # addi s0,s0,1 +| 0011011011 | 0111110000100000-----0001010111- 0 - 0 0 --- 1 1 0 - 0 00 00 01 00 0 - 0 0 - 0 ---------- --- - | # lbzx s1,s0,RB +| 0011011101 | 01111100010-----0000101101111000 0 - 0 1 110 0 1 1 - 0 00 11 00 00 0 0 0 0 - 0 0011010010 --- - | # or RT,s2,s1 -loop_end +| 0011011111 | 01010100010000100100000000101110 0 - 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # rlwinm s2,s2,8,0,23 +| 0011100001 | 01111100010000100000101101111000 0 - 0 1 010 1 1 1 - 0 00 00 00 00 0 0 0 0 - 0 0011011110 --- - | # or s2,s2,s1 -loop_end +| 0011100011 | -------------------------------- 0 - 0 1 011 - - - - - -- -- -- -- - - 0 - - 1 0011100010 --- - | # nop -loop_end + + +| 0100000001 | 00111000000--------------------- 0 0 0 - --- 1 0 - - 0 00 01 01 01 1 1 0 0 - 0 ---------- --- - | # addi s0,RA,D +| 0100000011 | 010100-----000100000011000111110 0 0 0 - --- 1 0 1 - 0 01 00 00 00 0 0 0 1 - 0 ---------- --- - | # rlwimi s2,RS,0,24,31 -skip_c +| 0100000101 | 01010100010000100100000000111110 0 0 0 - --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # rlwinm s2,s2,8,0,31 +| 0100000111 | 001110-------------------------- 1 - 0 - --- 0 0 - - 0 10 01 01 01 1 1 0 0 - 0 ---------- --- - | # addi RA,RA,D + +| 0100010001 | 00111000000-----0000000000000001 0 0 0 - --- 1 0 - - 0 00 01 00 00 0 0 0 0 - 0 ---------- --- 0 | # addi s0,RA,1 +| 0100010011 | 010100-----000100000011000111110 0 0 0 - --- 1 0 1 - 0 01 00 00 00 0 0 0 1 - 0 ---------- --- 0 | # rlwimi s2,RS,0,24,31 -skip_c +| 0100010101 | 01010100010000100100000000111110 0 0 0 - --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- 0 | # rlwinm s2,s2,8,0,31 +| 0100010111 | 00111000000-----0000000000000000 0 - 0 - --- 1 0 - - 0 00 01 00 00 0 0 0 0 - 0 ---------- --- 0 | # addi s0,RA,0 + +| 0101000001 | 010101-----000100000000000111110 0 0 0 - --- 1 0 - - 0 01 00 00 00 0 0 0 1 - 0 ---------- --- - | # rlwinm s2,RS,0,0,31 -skip_c +| 0101000011 | 010100-----000101000000000001110 0 0 0 - --- 1 0 1 - 0 01 00 00 00 0 0 0 1 - 0 ---------- --- - | # rlwimi s2,RS,16,0,7 -skip_c +| 0101000101 | 10011000010000000000000000000000 0 0 0 - --- - 1 - 1 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # stb s2,0(s0) +| 0101000111 | 01010100010000100100000000111110 0 0 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # rlwinm s2,s2,8,0,31 +| 0101001001 | 001110-------------------------- 1 - 0 - 111 0 0 - - 0 10 01 01 01 1 1 0 0 - 0 0101000110 --- - | # addi RA,RA,D + +| 0101010001 | 010101-----000100000000000111110 0 0 0 - --- 1 0 - - 0 01 00 00 00 0 0 0 1 - 0 ---------- --- 0 | # rlwinm s2,RS,0,0,31 -skip_c +| 0101010011 | 010100-----000101000000000001110 0 0 0 - --- 1 0 1 - 0 01 00 00 00 0 0 0 1 - 0 ---------- --- 0 | # rlwimi s2,RS,16,0,7 -skip_c +| 0101010101 | 0111110001000000-----0011010111- 0 0 0 - --- - 1 0 1 0 00 00 01 00 0 - 0 0 - 0 ---------- --- 1 | # stbx s2,s0,RB +| 0101010111 | 01010100010000100100000000111110 0 0 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- 0 | # rlwinm s2,s2,8,0,31 +| 0101011001 | 011111---------------01000010100 1 - 0 - 111 0 0 0 - 0 10 01 01 00 0 0 0 0 - 0 0101010110 --- 0 | # add RA,RA,RB + +| 0110000001 | 00111000000-----0000000000000000 0 0 0 - --- 1 0 - - 0 00 01 00 00 0 0 0 0 - 0 ---------- --- - | # addi s0,RA,0 +| 0110000011 | 01111000001000010100000000000000 0 0 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- - | # rldicl s1,s1,8,0 -skip_c +| 0110000101 | 01111000001000100100000000000000 0 0 0 - 111 1 1 - - 0 00 00 00 00 0 0 0 1 - 0 0110000010 --- - | # rldicl s2,s1,8,0 -skip_c +| 0110000111 | 00111000000000000000000000000001 0 0 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # addi s0,s0,1 +| 0110001001 | 1001100001000000---------------0 0 1 0 - 111 - 1 - 1 0 00 00 01 01 1 0 0 0 - 0 0110000110 --- - | # stb s2,DS(s0) -end for non-update + +| 0110010001 | 00111000000-----0000000000000000 0 0 0 - --- 1 0 - - 0 00 01 00 00 0 0 0 0 - 0 ---------- --- 0 | # addi s0,RA,0 +| 0110010011 | 01111000001000010100000000000000 0 0 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- 0 | # rldicl s1,s1,8,0 -skip_c +| 0110010101 | 01111000001000100100000000000000 0 0 0 - 111 1 1 - - 0 00 00 00 00 0 0 0 1 - 0 0110010010 --- 0 | # rldicl s2,s1,8,0 -skip_c +| 0110010111 | 00111000000000000000000000000001 0 0 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- 0 | # addi s0,s0,1 +| 0110011001 | 0111110001000000-----0011010111- 0 1 0 - 111 - 1 0 1 0 00 00 01 00 0 - 0 0 - 0 0110010110 --- 1 | # stbx s2,s0,RB -end for non-update + + +| 0110100001 | -------------------------------- 0 - 0 - --- - - - - - -- -- -- -- - - 0 - - 1 ---------- --- - | # nop +| 0110100011 | 00111000000000000000000000000100 0 - 0 1 100 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 0110100010 --- - | # addi s0,s0,4 -loop_end + +| 0110110001 | -------------------------------- 0 - 0 - --- - - - - - -- -- -- -- - - 0 - - 1 ---------- --- - | # nop +| 0110110011 | 10011000010000000000000000000000 0 - 0 0 --- - 1 - 1 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # stb s2,0(s0) +| 0110110101 | 10011000010000000000000000000001 0 - 0 0 --- - 1 - 1 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # stb s2,1(s0) +| 0110110111 | 10011000010000000000000000000010 0 - 0 0 --- - 1 - 1 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # stb s2,2(s0) +| 0110111001 | 10011000010000000000000000000011 0 - 0 0 --- - 1 - 1 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # stb s2,3(s0) +| 0110111011 | -------------------------------- 0 - 0 - 101 - - - - - -- -- -- -- - - 0 - - 1 0110110010 --- - | # nop +| 0110111101 | -------------------------------- 0 - 0 - --- - - - - - -- -- -- -- - - 0 - - 1 ---------- --- - | # nop +| 0110111111 | 00111000000000000000000000000001 0 - 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # addi s0,s0,1 +| 0111000001 | -------------------------------- - - 0 - 000 - - - - - -- -- -- -- - - 0 - - - 0110111110 --- - | # nop + +| 0111010001 | -------------------------------- 0 - 0 - --- - - - - - -- -- -- -- - - 0 - - 1 ---------- --- - | # nop +| 0111010011 | 0111110001000000-----0011010111- 0 - 0 0 --- - 1 0 1 0 00 00 01 00 0 - 0 0 - 0 ---------- --- - | # stbx s2,s0,RB +| 0111010101 | 01010100010000100100000000111110 0 - 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # rlwinm s2,s2,8,0,31 +| 0111010111 | 00111000000000000000000000000001 0 - 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # addi s0,s0,1 +| 0111011001 | 0111110001000000-----0011010111- 0 - 0 0 --- - 1 0 1 0 00 00 01 00 0 - 0 0 - 0 ---------- --- - | # stbx s2,s0,RB +| 0111011011 | 01010100010000100100000000111110 0 - 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # rlwinm s2,s2,8,0,31 +| 0111011101 | 00111000000000000000000000000001 0 - 0 1 110 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 0111010010 --- - | # addi s0,s0,1 -loop_end +| 0111011111 | -------------------------------- 0 - 0 - --- - - - - - -- -- -- -- - - 0 - - 1 ---------- --- - | # nop +| 0111100001 | 00111000000000000000000000000001 0 - 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # addi s0,s0,1 +| 0111100011 | 01100000000000000000000000000000 1 - 0 - 010 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 0111100000 --- - | # ori 0,0,0 (nop) + + +| 0101100001 | 01010100000000010000000000000110 0 - 0 - --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # rlwinm s1,s0,0,0,3 +| 0101100011 | 01010100001000001110000100111110 0 - 0 - --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # srwi s0,s1,4 +| 0101100101 | 01010100001000001100001000111110 0 - 0 - --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # srwi s0,s1,8 +| 0101100111 | 01010100001000001000010000111110 0 - 0 - --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # srwi s0,s1,16 +| 0101101001 | 01111100001----------0010010000- 0 - 0 - --- - 1 - - 0 00 01 01 00 0 - 1 0 - 0 ---------- --- - | # mtocrf BF,s1 + +| 0101110001 | 01111100000101000000-0000010011- 0 - 0 - --- 1 - - - 0 00 00 00 00 0 - 0 0 - 0 ---------- --- - | # mfocrf s0,0x40 +| 0101110011 | 01111100000100100000-0000010011- 0 - 0 - --- 1 - - - 0 00 00 00 00 0 - 0 0 - 0 ---------- --- - | # mfocrf s0,0x20 +| 0101110101 | 01111100000100010000-0000010011- 0 - 0 - --- 1 - - - 0 00 00 00 00 0 - 0 0 - 0 ---------- --- - | # mfocrf s0,0x10 +| 0101110111 | 01111100000100001000-0000010011- 0 - 0 - --- 1 - - - 0 00 00 00 00 0 - 0 0 - 0 ---------- --- - | # mfocrf s0,0x08 +| 0101111001 | 01111100000100000100-0000010011- 0 - 0 - --- 1 - - - 0 00 00 00 00 0 - 0 0 - 0 ---------- --- - | # mfocrf s0,0x04 +| 0101111011 | 01111100000100000010-0000010011- 0 - 0 - --- 1 - - - 0 00 00 00 00 0 - 0 0 - 0 ---------- --- - | # mfocrf s0,0x02 +| 0101111101 | 01111100000100000001-0000010011- 0 - 0 - --- 1 - - - 0 00 00 00 00 0 - 0 0 - 0 ---------- --- - | # mfocrf s0,0x01 + + +| 0111110001 | 011111-----101000000-0010010000- 0 - 0 - --- - 0 - - 0 01 00 00 00 0 - 0 0 - 0 ---------- --- - | # mtocrf 0x40,RS +| 0111110011 | 011111-----100010000-0010010000- 0 - 0 - --- - 0 - - 0 01 00 00 00 0 - 0 0 - 0 ---------- --- - | # mtocrf 0x10,RS +| 0111110101 | 011111-----100000100-0010010000- 0 - 0 - --- - 0 - - 0 01 00 00 00 0 - 0 0 - 0 ---------- --- - | # mtocrf 0x04,RS +| 0111110111 | 011111-----100000001-0010010000- 1 - 0 - --- - 0 - - 0 01 00 00 00 0 - 0 0 - 0 ---------- --- - | # mtocrf 0x01,RS + + + +| 1010100001 | 001110-------------------------- 1 - 0 - --- 0 0 - - 0 10 01 01 01 1 1 0 0 - 0 ---------- --- - | # addi RA,RA,D + +| 1010101001 | 100010-----000000000000000000000 0 - 0 - --- 0 1 - - 0 01 00 00 00 0 0 0 0 - 0 ---------- --- - | # lbz RT,0(s0) + +| 1010110001 | 001110-------------------------- 1 - 0 - --- 0 0 - - 0 10 01 01 01 1 1 0 0 - 0 ---------- --- - | # addi RA,RA,D + +| 1010111001 | 101000-----000000000000000000000 0 - 0 - --- 0 1 - - 0 01 00 00 00 0 0 0 0 - 0 ---------- --- - | # lhz RT,0(s0) + +| 1011000001 | 001110-------------------------- 1 - 0 - --- 0 0 - - 0 10 01 01 01 1 1 0 0 - 0 ---------- --- - | # addi RA,RA,D + +| 1011001001 | 100000-----000000000000000000000 0 - 0 - --- 0 1 - - 0 01 00 00 00 0 0 0 0 - 0 ---------- --- - | # lwz RT,0(s0) + +| 1011010001 | 001110-------------------------0 1 - 0 - --- 0 0 - - 0 10 01 01 01 1 0 0 0 - 0 ---------- --- - | # addi RA,RA,DS + +| 1011011001 | 111010-----000000000000000000000 0 - 0 - --- 0 1 - - 0 01 00 00 00 0 0 0 0 - 0 ---------- --- - | # ld RT,0(s0) + +| 1011100001 | 001110-------------------------- 1 - 0 - --- 0 0 - - 0 10 01 01 01 1 1 0 0 - 0 ---------- --- - | # addi RA,RA,D + +| 1011101001 | 101010-----000000000000000000000 0 - 0 - --- 0 1 - - 0 01 00 00 00 0 0 0 0 - 0 ---------- --- - | # lha RT,0(s0) + +| 1011111001 | 111010-----000000000000000000010 0 - 0 - --- 0 1 - - 0 01 00 00 00 0 0 0 0 - 0 ---------- --- - | # lwa RT,0(s0) + + + +| 1000110001 | 01111100010-----000000001010111- 0 - 0 - --- 1 0 1 - 0 00 01 00 00 0 - 0 0 - 0 ---------- --- - | # lbzx s2,RA,s0 +| 1000110011 | 01010100010000100100000000111110 0 - 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # rlwinm s2,s2,8,0,31 +| 1000110101 | 01111100010000100000101101111000 0 - 0 1 111 1 1 1 - 0 00 00 00 00 0 0 0 0 - 0 1000110010 --- - | # or s2,s2,s1 -loop_end +| 1000110111 | 01010000010000101000010000101110 0 - 0 - --- 1 1 1 - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- - | # rlwimi s2,s2,16,16,23 -skip_c +| 1000111001 | 011111-----000000001010011111000 1 - 0 - --- 0 - 1 - 0 01 00 00 00 0 0 0 0 - 0 ---------- --- - | # mfifgpr RT,s2,0 -end + +| 1001110001 | 01111100010-----000000001010111- 0 - 0 - --- 1 0 1 - 0 00 01 00 00 0 - 0 0 - 0 ---------- --- - | # lbzx s2,RA,s0 +| 1001110011 | 01010100010000100100000000111110 0 - 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # rlwinm s2,s2,8,0,31 +| 1001110101 | 01111100010000100000101101111000 0 - 0 1 111 1 1 1 - 0 00 00 00 00 0 0 0 0 - 0 1001110010 --- - | # or s2,s2,s1 -loop_end +| 1001110111 | 01010000010000101000010000101110 0 - 0 - --- 1 1 1 - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- - | # rlwimi s2,s2,16,16,23 -skip_c +| 1001111001 | 011111-----000000001010011111010 1 - 0 - --- 0 - 1 - 0 01 00 00 00 0 0 0 0 - 0 ---------- --- - | # mfixfgpr RT,s2,0 -end + +| 1001000001 | 10001000010000000000000000000000 0 0 0 - --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # lbz s2,0(s0) +| 1001000011 | 01010100010000100100000000111110 0 0 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # rlwinm s2,s2,8,0,31 +| 1001000101 | 01111100010000100000101101111000 0 0 0 1 111 1 1 1 - 0 00 00 00 00 0 0 0 0 - 0 1001000010 --- - | # or s2,s2,s1 -loop_end +| 1001000111 | 01010000010000101000010000101110 0 0 0 - --- 1 1 1 - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- - | # rlwimi s2,s2,16,16,23 -skip_c +| 1001001001 | 01111100000000000001010011111100 0 1 0 - --- 0 - 1 - 0 01 00 00 00 0 0 0 0 - 0 ---------- --- - | # mfsfgpr RT,s2,0 -end for non-update + +| 1001010001 | 01111100010-----000000001010111- 0 0 0 - --- 1 0 1 - 0 00 01 00 00 0 - 0 0 - 0 ---------- --- - | # lbzx s2,RA,s0 +| 1001010011 | 01010100010000100100000000111110 0 0 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # rlwinm s2,s2,8,0,31 +| 1001010101 | 01111100010000100000101101111000 0 0 0 1 111 1 1 1 - 0 00 00 00 00 0 0 0 0 - 0 1001010010 --- - | # or s2,s2,s1 -loop_end +| 1001010111 | 01010000010000101000010000101110 0 0 0 - --- 1 1 1 - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- - | # rlwimi s2,s2,16,16,23 -skip_c +| 1001011001 | 011111-----000000001010011111100 0 1 0 - --- 0 - 1 - 0 01 00 00 00 0 0 0 0 - 0 ---------- --- - | # mfsfgpr RT,s2,0 -end for non-update +| 1001011011 | 011111-----000010000001000010100 1 - 0 - --- 0 1 1 - 0 10 00 00 00 0 0 0 0 - 0 ---------- --- - | # add RA,s1,s0 + +| 1010000001 | 10001000010000000000000000000000 0 0 0 - --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # lbz s2,0(s0) +| 1010000011 | 01111000010000100100010111100100 0 0 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # rldicr s2,s2,8,55 +| 1010000101 | 01111100010000100000101101111000 0 0 0 1 111 1 1 1 - 0 00 00 00 00 0 0 0 0 - 0 1010000010 --- - | # or s2,s2,s1 -loop_end +| 1010000111 | 01111000001000010100000000000000 0 0 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- - | # rldicl s1,s1,8,0 -skip_c +| 1010001001 | 01101000001000100000000000000000 0 0 0 - 111 1 1 - - 0 00 00 00 00 0 0 0 1 - 0 1010000110 --- - | # xori s2,s1,0 -skip_c +| 1010001011 | 001110-------------------------- 1 - 0 - --- 0 0 - - 0 10 01 01 01 1 1 0 0 - 0 ---------- --- - | # addi RA,RA,D + +| 1010010001 | 01111100010-----000000001010111- 0 0 0 - --- 1 0 1 - 0 00 01 00 00 0 - 0 0 - 0 ---------- --- 1 | # lbzx s2,RA,s0 +| 1010010011 | 01111000010000100100010111100100 0 0 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- 0 | # rldicr s2,s2,8,55 +| 1010010101 | 01111100010000100000101101111000 0 0 0 1 111 1 1 1 - 0 00 00 00 00 0 0 0 0 - 0 1010010010 --- 0 | # or s2,s2,s1 -loop_end +| 1010010111 | 01111000001000010100000000000000 0 0 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- 0 | # rldicl s1,s1,8,0 -skip_c +| 1010011001 | 01101000001000100000000000000000 0 0 0 - 111 1 1 - - 0 00 00 00 00 0 0 0 1 - 0 1010010110 --- 0 | # xori s2,s1,0 -skip_c +| 1010011011 | 00111000001-----1111111111111001 0 - 0 - --- 1 0 - - 0 00 01 00 00 0 0 0 0 - 0 ---------- --- 0 | # addi s1,RA,-7 + +| 1100110001 | 00111000000-----0000000000000000 0 - 0 - --- 1 0 - - 0 00 01 00 00 0 0 0 0 - 0 ---------- --- - | # addi s0,RA,0 +| 1100110011 | 01010100001000100000000000111110 0 - 0 - --- 1 1 - - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- - | # rlwinm s2,s1,0,0,31 -skip_c +| 1100110101 | 01010000001000101000000000001110 0 - 0 - --- 1 1 1 - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- - | # rlwimi s2,s1,16,0,7 -skip_c +| 1100110111 | 00111000000000000000000000000001 0 - 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # addi s0,s0,1 +| 1100111001 | 0111110001000000-----0011010111- 1 - 0 - 111 - 1 0 1 0 00 00 01 00 0 - 0 0 - 0 1100110110 --- - | # stbx s2,s0,RB + +| 1101000001 | 00111000000--------------------- 0 0 0 - --- 1 0 - - 0 00 01 01 01 1 1 0 0 - 0 ---------- --- - | # addi s0,RA,D +| 1101000011 | 01010100001000100000000000111110 0 0 0 - --- 1 1 - - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- - | # rlwinm s2,s1,0,0,31 -skip_c +| 1101000101 | 01010000001000101000000000001110 0 0 0 - --- 1 1 1 - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- - | # rlwimi s2,s1,16,0,7 -skip_c +| 1101000111 | 00111000000000000000000000000001 0 0 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # addi s0,s0,1 +| 1101001001 | 10011000010000000000000000000000 0 1 0 - 111 - 1 - 1 0 00 00 00 00 0 0 0 0 - 0 1101000110 --- - | # stb s2,0(s0) -end for non-update + +| 1101010001 | 00111000000-----0000000000000000 0 0 0 - --- 1 0 - - 0 00 01 00 00 0 0 0 0 - 0 ---------- --- - | # addi s0,RA,0 +| 1101010011 | 01010100001000100000000000111110 0 0 0 - --- 1 1 - - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- - | # rlwinm s2,s1,0,0,31 -skip_c +| 1101010101 | 01010000001000101000000000001110 0 0 0 - --- 1 1 1 - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- - | # rlwimi s2,s1,16,0,7 -skip_c +| 1101010111 | 00111000000000000000000000000001 0 0 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # addi s0,s0,1 +| 1101011001 | 0111110001000000-----0011010111- 0 1 0 - 111 - 1 0 1 0 00 00 01 00 0 - 0 0 - 0 1101010110 --- - | # stbx s2,s0,RB -end for non-update + +| 1110000001 | 01111000001000100100000000000000 0 0 0 - --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # rldicl s2,s1,8,0 +| 1110000011 | 01111000001000010100000000000000 0 0 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- - | # rldicl s1,s1,8,0 -skip_c +| 1110000101 | 01111000001000100100000000000000 0 0 0 - 111 1 1 - - 0 00 00 00 00 0 0 0 1 - 0 1110000010 --- - | # rldicl s2,s1,8,0 -skip_c +| 1110000111 | 1001100001000000---------------- 0 0 0 - --- - 1 - 1 0 00 00 01 01 1 1 0 0 - 0 ---------- --- - | # stb s2,D(s0) +| 1110001001 | 01111000010000100100000000000000 0 0 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # rldicl s2,s2,8,0 +| 1110001011 | 001110-------------------------- 1 - 0 - 111 0 0 - - 0 10 01 01 01 1 1 0 0 - 0 1110001000 --- - | # addi RA,RA,D + +| 1110010001 | 01111000001000100100000000000000 0 0 0 - --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- 0 | # rldicl s2,s1,8,0 +| 1110010011 | 01111000001000010100000000000000 0 0 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 1 - 0 ---------- --- 0 | # rldicl s1,s1,8,0 -skip_c +| 1110010101 | 01111000001000100100000000000000 0 0 0 - 111 1 1 - - 0 00 00 00 00 0 0 0 1 - 0 1110010010 --- 0 | # rldicl s2,s1,8,0 -skip_c +| 1110010111 | 0111110001000000-----0011010111- 0 0 0 - --- - 1 0 1 0 00 00 01 00 0 - 0 0 - 0 ---------- --- 1 | # stbx s2,s0,RB +| 1110011001 | 01111000010000100100000000000000 0 0 0 0 --- 1 1 - - 0 00 00 00 00 0 0 0 0 - 0 ---------- --- 0 | # rldicl s2,s2,8,0 +| 1110011011 | 011111---------------01000010100 1 - 0 - 111 0 0 0 - 0 10 01 01 00 0 0 0 0 - 0 1110011000 --- 0 | # add RA,RA,RB + + + +| 1111000001 | 001110-------------------------- 1 - 0 - --- 0 0 - - 0 10 01 01 01 1 1 0 0 - 0 ---------- --- - | # addi RA,RA,DS + +| 1111001001 | 110000-----000000000000000000000 0 - 0 - --- 0 1 - - 0 01 00 00 00 0 0 0 0 - 0 ---------- --- - | # lfs FRT,0(s0) + +| 1111010001 | 001110-------------------------- 1 - 0 - --- 0 0 - - 0 10 01 01 01 1 1 0 0 - 0 ---------- --- - | # addi RA,RA,DS + +| 1111011001 | 110010-----000000000000000000000 0 - 0 - --- 0 1 - - 0 01 00 00 00 0 0 0 0 - 0 ---------- --- - | # lfd FRT,0(s0) + + +| 1100000001 | ----------------00001----------- 1 - 0 - --- 0 0 1 0 1 01 01 00 01 1 1 0 0 - 0 ---------- --- - | # vvvvv FT,FA,FC,s1 - Original qpx op except B + +| 1100001001 | 11111100010---------------100000 0 - 0 - --- 1 0 0 0 0 00 -- 11 -- 0 0 0 0 - 0 ---------- --- - | # prenrm s2,FA - prenorm both DP, SP + +| 1100010001 | ----------------00001----------- 1 - 0 - --- 0 0 1 0 1 01 01 00 01 1 1 0 0 - 0 ---------- --- - | # vvvvv FT,FA,FC,s1 - Original qpx op except B +*END*===========+=======================================================================================================+ +?TABLE END rom_instr; +//table_end +*/ + +//assign_start + +assign rom_instr_pt[1] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[6] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 8'b01000000); +assign rom_instr_pt[2] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[6] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 8'b00110000); +assign rom_instr_pt[3] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[4] , rom_addr_l2[5] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b1010000); +assign rom_instr_pt[4] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[5] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0010000); +assign rom_instr_pt[5] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[3] , rom_addr_l2[5] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b1110000); +assign rom_instr_pt[6] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[6] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 8'b01001000); +assign rom_instr_pt[7] = + (({ rom_addr_l2[1] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[6] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b001000); +assign rom_instr_pt[8] = + (({ rom_addr_l2[2] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[6] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b111000); +assign rom_instr_pt[9] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[4] , rom_addr_l2[5] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0111000); +assign rom_instr_pt[10] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[5] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0011000); +assign rom_instr_pt[11] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[3] , rom_addr_l2[5] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0011000); +assign rom_instr_pt[12] = + (({ rom_addr_l2[0] , rom_addr_l2[2] , + rom_addr_l2[5] , rom_addr_l2[6] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b101000); +assign rom_instr_pt[13] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[6] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 8'b01110000); +assign rom_instr_pt[14] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0110000); +assign rom_instr_pt[15] = + (({ rom_addr_l2[0] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0101000); +assign rom_instr_pt[16] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[4] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0011000); +assign rom_instr_pt[17] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b1000000); +assign rom_instr_pt[18] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[3] , rom_addr_l2[6] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b010000); +assign rom_instr_pt[19] = + (({ rom_addr_l2[1] , rom_addr_l2[3] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b10000); +assign rom_instr_pt[20] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[6] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b111000); +assign rom_instr_pt[21] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b11000); +assign rom_instr_pt[22] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[6] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 8'b01101100); +assign rom_instr_pt[23] = + (({ rom_addr_l2[1] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[6] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b101100); +assign rom_instr_pt[24] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[6] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b010100); +assign rom_instr_pt[25] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[5] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b000000); +assign rom_instr_pt[26] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[5] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0100000); +assign rom_instr_pt[27] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0000100); +assign rom_instr_pt[28] = + (({ rom_addr_l2[0] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0001100); +assign rom_instr_pt[29] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b010100); +assign rom_instr_pt[30] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b010000); +assign rom_instr_pt[31] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[6] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 8'b01011010); +assign rom_instr_pt[32] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[4] , rom_addr_l2[6] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b011010); +assign rom_instr_pt[33] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[6] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b011010); +assign rom_instr_pt[34] = + (({ rom_addr_l2[1] , rom_addr_l2[3] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b10110); +assign rom_instr_pt[35] = + (({ rom_addr_l2[3] , rom_addr_l2[6] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 4'b0110); +assign rom_instr_pt[36] = + (({ rom_addr_l2[1] , rom_addr_l2[3] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b01110); +assign rom_instr_pt[37] = + (({ rom_addr_l2[3] , rom_addr_l2[6] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 4'b1110); +assign rom_instr_pt[38] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0110010); +assign rom_instr_pt[39] = + (({ rom_addr_l2[1] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b11010); +assign rom_instr_pt[40] = + (({ rom_addr_l2[1] , rom_addr_l2[5] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 4'b0010); +assign rom_instr_pt[41] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[5] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 8'b01010110); +assign rom_instr_pt[42] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[5] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0000110); +assign rom_instr_pt[43] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b010010); +assign rom_instr_pt[44] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b110010); +assign rom_instr_pt[45] = + (({ rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 4'b0010); +assign rom_instr_pt[46] = + (({ rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b11110); +assign rom_instr_pt[47] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b000010); +assign rom_instr_pt[48] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b010010); +assign rom_instr_pt[49] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b00110); +assign rom_instr_pt[50] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b11010); +assign rom_instr_pt[51] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 4'b1010); +assign rom_instr_pt[52] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 4'b1110); +assign rom_instr_pt[53] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[6] , + rom_addr_l2[8] }) === 7'b0111000); +assign rom_instr_pt[54] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[6] , rom_addr_l2[8] + }) === 6'b111000); +assign rom_instr_pt[55] = + (({ rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[6] , + rom_addr_l2[8] }) === 5'b10010); +assign rom_instr_pt[56] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[6] , rom_addr_l2[8] + }) === 6'b000010); +assign rom_instr_pt[57] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[6] , rom_addr_l2[8] + }) === 6'b100010); +assign rom_instr_pt[58] = + (({ rom_addr_l2[1] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[6] , + rom_addr_l2[8] }) === 5'b00010); +assign rom_instr_pt[59] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[4] , + rom_addr_l2[6] , rom_addr_l2[8] + }) === 6'b100010); +assign rom_instr_pt[60] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[4] , + rom_addr_l2[6] , rom_addr_l2[8] + }) === 6'b000110); +assign rom_instr_pt[61] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[6] , rom_addr_l2[8] + }) === 6'b111010); +assign rom_instr_pt[62] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[3] , rom_addr_l2[6] , + rom_addr_l2[8] }) === 5'b10110); +assign rom_instr_pt[63] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[6] , + rom_addr_l2[8] }) === 5'b00010); +assign rom_instr_pt[64] = + (({ rom_addr_l2[1] , rom_addr_l2[5] , + rom_addr_l2[8] }) === 3'b000); +assign rom_instr_pt[65] = + (({ rom_addr_l2[1] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[8] + }) === 4'b0000); +assign rom_instr_pt[66] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[8] }) === 5'b01010); +assign rom_instr_pt[67] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[4] , + rom_addr_l2[8] }) === 5'b00110); +assign rom_instr_pt[68] = + (({ rom_addr_l2[3] , rom_addr_l2[8] + }) === 2'b00); +assign rom_instr_pt[69] = + (({ rom_addr_l2[2] , rom_addr_l2[8] + }) === 2'b00); +assign rom_instr_pt[70] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[5] , rom_addr_l2[6] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b101001); +assign rom_instr_pt[71] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0100001); +assign rom_instr_pt[72] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b1100001); +assign rom_instr_pt[73] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[6] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b001001); +assign rom_instr_pt[74] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b11001); +assign rom_instr_pt[75] = + (({ rom_addr_l2[2] , rom_addr_l2[4] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b11101); +assign rom_instr_pt[76] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[6] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b011101); +assign rom_instr_pt[77] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[4] , rom_addr_l2[5] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b101001); +assign rom_instr_pt[78] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[5] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b000001); +assign rom_instr_pt[79] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0000101); +assign rom_instr_pt[80] = + (({ rom_addr_l2[0] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0001101); +assign rom_instr_pt[81] = + (({ rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[5] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b111101); +assign rom_instr_pt[82] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[4] , rom_addr_l2[5] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b011101); +assign rom_instr_pt[83] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b010001); +assign rom_instr_pt[84] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0101001); +assign rom_instr_pt[85] = + (({ rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 4'b0101); +assign rom_instr_pt[86] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[4] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b10101); +assign rom_instr_pt[87] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b010001); +assign rom_instr_pt[88] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b01101); +assign rom_instr_pt[89] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b11001); +assign rom_instr_pt[90] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0101011); +assign rom_instr_pt[91] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[4] , rom_addr_l2[6] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b011011); +assign rom_instr_pt[92] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[6] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b011011); +assign rom_instr_pt[93] = + (({ rom_addr_l2[1] , rom_addr_l2[3] , + rom_addr_l2[6] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b11111); +assign rom_instr_pt[94] = + (({ rom_addr_l2[3] , rom_addr_l2[6] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 4'b1111); +assign rom_instr_pt[95] = + (({ rom_addr_l2[1] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b11011); +assign rom_instr_pt[96] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[5] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b000011); +assign rom_instr_pt[97] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[5] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b100011); +assign rom_instr_pt[98] = + (({ rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[5] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b00011); +assign rom_instr_pt[99] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[5] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b111011); +assign rom_instr_pt[100] = + (({ rom_addr_l2[0] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0001111); +assign rom_instr_pt[101] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[5] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0000111); +assign rom_instr_pt[102] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[5] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0100111); +assign rom_instr_pt[103] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[5] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b111111); +assign rom_instr_pt[104] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b010011); +assign rom_instr_pt[105] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 7'b0101011); +assign rom_instr_pt[106] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[4] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b011011); +assign rom_instr_pt[107] = + (({ rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b11111); +assign rom_instr_pt[108] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[4] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b010111); +assign rom_instr_pt[109] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 6'b000011); +assign rom_instr_pt[110] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b10011); +assign rom_instr_pt[111] = + (({ rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 4'b0011); +assign rom_instr_pt[112] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b00111); +assign rom_instr_pt[113] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b10011); +assign rom_instr_pt[114] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b11011); +assign rom_instr_pt[115] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 4'b0111); +assign rom_instr_pt[116] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[7] , + rom_addr_l2[8] }) === 5'b11111); +assign rom_instr_pt[117] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[7] , rom_addr_l2[8] + }) === 4'b1011); +assign rom_instr_pt[118] = + (({ rom_addr_l2[2] , rom_addr_l2[4] , + rom_addr_l2[6] , rom_addr_l2[8] + }) === 4'b1001); +assign rom_instr_pt[119] = + (({ rom_addr_l2[0] , rom_addr_l2[5] , + rom_addr_l2[6] , rom_addr_l2[8] + }) === 4'b1011); +assign rom_instr_pt[120] = + (({ rom_addr_l2[5] , rom_addr_l2[6] , + rom_addr_l2[8] }) === 3'b011); +assign rom_instr_pt[121] = + (({ rom_addr_l2[1] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[5] , + rom_addr_l2[6] , rom_addr_l2[8] + }) === 6'b000111); +assign rom_instr_pt[122] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[5] , rom_addr_l2[6] , + rom_addr_l2[8] }) === 5'b11111); +assign rom_instr_pt[123] = + (({ rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[6] , rom_addr_l2[8] + }) === 4'b0011); +assign rom_instr_pt[124] = + (({ rom_addr_l2[1] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[6] , + rom_addr_l2[8] }) === 5'b11111); +assign rom_instr_pt[125] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[4] , rom_addr_l2[6] , + rom_addr_l2[8] }) === 5'b01111); +assign rom_instr_pt[126] = + (({ rom_addr_l2[1] , rom_addr_l2[3] , + rom_addr_l2[6] , rom_addr_l2[8] + }) === 4'b0011); +assign rom_instr_pt[127] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[6] , + rom_addr_l2[8] }) === 5'b11111); +assign rom_instr_pt[128] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[6] , rom_addr_l2[8] + }) === 4'b0011); +assign rom_instr_pt[129] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[6] , rom_addr_l2[8] + }) === 4'b1111); +assign rom_instr_pt[130] = + (({ rom_addr_l2[2] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[8] + }) === 4'b1101); +assign rom_instr_pt[131] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[5] , + rom_addr_l2[8] }) === 5'b11101); +assign rom_instr_pt[132] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[8] + }) === 6'b000011); +assign rom_instr_pt[133] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[8] }) === 5'b01111); +assign rom_instr_pt[134] = + (({ rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[8] }) === 3'b111); +assign rom_instr_pt[135] = + (({ rom_addr_l2[1] , rom_addr_l2[3] , + rom_addr_l2[8] }) === 3'b011); +assign rom_instr_pt[136] = + (({ rom_addr_l2[1] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[5] , + rom_addr_l2[6] , rom_addr_l2[7] + }) === 6'b000000); +assign rom_instr_pt[137] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[5] , rom_addr_l2[6] , + rom_addr_l2[7] }) === 5'b00000); +assign rom_instr_pt[138] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[6] , + rom_addr_l2[7] }) === 7'b0101000); +assign rom_instr_pt[139] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[6] , + rom_addr_l2[7] }) === 7'b0111000); +assign rom_instr_pt[140] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[6] , rom_addr_l2[7] + }) === 6'b111000); +assign rom_instr_pt[141] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[6] , + rom_addr_l2[7] }) === 5'b01100); +assign rom_instr_pt[142] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[4] , rom_addr_l2[6] , + rom_addr_l2[7] }) === 5'b00110); +assign rom_instr_pt[143] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[6] , rom_addr_l2[7] + }) === 6'b001110); +assign rom_instr_pt[144] = + (({ rom_addr_l2[0] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[6] , + rom_addr_l2[7] }) === 5'b01110); +assign rom_instr_pt[145] = + (({ rom_addr_l2[6] , rom_addr_l2[7] + }) === 2'b10); +assign rom_instr_pt[146] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[7] + }) === 6'b000010); +assign rom_instr_pt[147] = + (({ rom_addr_l2[3] , rom_addr_l2[7] + }) === 2'b00); +assign rom_instr_pt[148] = + (({ rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[6] , rom_addr_l2[7] + }) === 4'b1111); +assign rom_instr_pt[149] = + (({ rom_addr_l2[1] , rom_addr_l2[6] , + rom_addr_l2[7] }) === 3'b111); +assign rom_instr_pt[150] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[4] , rom_addr_l2[5] , + rom_addr_l2[7] }) === 5'b11011); +assign rom_instr_pt[151] = + (({ rom_addr_l2[2] , rom_addr_l2[4] , + rom_addr_l2[7] }) === 3'b011); +assign rom_instr_pt[152] = + (({ rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[7] }) === 3'b011); +assign rom_instr_pt[153] = + (({ rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[5] , + rom_addr_l2[6] }) === 5'b10100); +assign rom_instr_pt[154] = + (({ rom_addr_l2[0] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[5] , + rom_addr_l2[6] }) === 5'b11100); +assign rom_instr_pt[155] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[6] + }) === 6'b010110); +assign rom_instr_pt[156] = + (({ rom_addr_l2[0] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[6] }) === 5'b10000); +assign rom_instr_pt[157] = + (({ rom_addr_l2[0] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[6] + }) === 4'b0010); +assign rom_instr_pt[158] = + (({ rom_addr_l2[0] , rom_addr_l2[2] , + rom_addr_l2[4] , rom_addr_l2[6] + }) === 4'b1010); +assign rom_instr_pt[159] = + (({ rom_addr_l2[0] , rom_addr_l2[2] , + rom_addr_l2[4] , rom_addr_l2[6] + }) === 4'b1110); +assign rom_instr_pt[160] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[6] }) === 5'b11100); +assign rom_instr_pt[161] = + (({ rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[6] }) === 3'b010); +assign rom_instr_pt[162] = + (({ rom_addr_l2[0] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[6] + }) === 4'b1110); +assign rom_instr_pt[163] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[6] + }) === 6'b010001); +assign rom_instr_pt[164] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[4] , rom_addr_l2[5] , + rom_addr_l2[6] }) === 5'b00101); +assign rom_instr_pt[165] = + (({ rom_addr_l2[1] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[6] + }) === 4'b1101); +assign rom_instr_pt[166] = + (({ rom_addr_l2[0] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[6] + }) === 4'b1101); +assign rom_instr_pt[167] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[5] , + rom_addr_l2[6] }) === 5'b11001); +assign rom_instr_pt[168] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[5] , + rom_addr_l2[6] }) === 5'b01101); +assign rom_instr_pt[169] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[4] , + rom_addr_l2[5] , rom_addr_l2[6] + }) === 6'b010011); +assign rom_instr_pt[170] = + (({ rom_addr_l2[0] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[5] , + rom_addr_l2[6] }) === 5'b11111); +assign rom_instr_pt[171] = + (({ rom_addr_l2[0] , rom_addr_l2[2] , + rom_addr_l2[4] , rom_addr_l2[5] , + rom_addr_l2[6] }) === 5'b11111); +assign rom_instr_pt[172] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[3] , rom_addr_l2[5] , + rom_addr_l2[6] }) === 5'b10111); +assign rom_instr_pt[173] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[5] , + rom_addr_l2[6] }) === 5'b11011); +assign rom_instr_pt[174] = + (({ rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[6] + }) === 4'b0001); +assign rom_instr_pt[175] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[4] , + rom_addr_l2[6] }) === 5'b01001); +assign rom_instr_pt[176] = + (({ rom_addr_l2[4] , rom_addr_l2[6] + }) === 2'b01); +assign rom_instr_pt[177] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[4] , + rom_addr_l2[6] }) === 5'b10011); +assign rom_instr_pt[178] = + (({ rom_addr_l2[0] , rom_addr_l2[2] , + rom_addr_l2[4] , rom_addr_l2[6] + }) === 4'b1011); +assign rom_instr_pt[179] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[4] , rom_addr_l2[6] + }) === 4'b1011); +assign rom_instr_pt[180] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[6] }) === 5'b11111); +assign rom_instr_pt[181] = + (({ rom_addr_l2[0] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[6] + }) === 4'b1111); +assign rom_instr_pt[182] = + (({ rom_addr_l2[0] , rom_addr_l2[3] , + rom_addr_l2[6] }) === 3'b111); +assign rom_instr_pt[183] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[6] + }) === 4'b0001); +assign rom_instr_pt[184] = + (({ rom_addr_l2[2] , rom_addr_l2[6] + }) === 2'b01); +assign rom_instr_pt[185] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[6] + }) === 4'b0111); +assign rom_instr_pt[186] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[6] }) === 3'b011); +assign rom_instr_pt[187] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[5] + }) === 6'b001100); +assign rom_instr_pt[188] = + (({ rom_addr_l2[1] , rom_addr_l2[4] , + rom_addr_l2[5] }) === 3'b000); +assign rom_instr_pt[189] = + (({ rom_addr_l2[1] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[5] + }) === 4'b1110); +assign rom_instr_pt[190] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] , + rom_addr_l2[5] }) === 5'b01001); +assign rom_instr_pt[191] = + (({ rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[4] , rom_addr_l2[5] + }) === 4'b1111); +assign rom_instr_pt[192] = + (({ rom_addr_l2[0] , rom_addr_l2[1] , + rom_addr_l2[2] , rom_addr_l2[4] , + rom_addr_l2[5] }) === 5'b01011); +assign rom_instr_pt[193] = + (({ rom_addr_l2[3] , rom_addr_l2[5] + }) === 2'b11); +assign rom_instr_pt[194] = + (({ rom_addr_l2[0] , rom_addr_l2[2] , + rom_addr_l2[3] , rom_addr_l2[4] + }) === 4'b1000); +assign rom_instr_pt[195] = + (({ rom_addr_l2[2] , rom_addr_l2[3] , + rom_addr_l2[4] }) === 3'b111); +assign rom_instr_pt[196] = + (({ rom_addr_l2[3] , rom_addr_l2[4] + }) === 2'b11); +assign rom_instr_pt[197] = + (({ rom_addr_l2[1] , rom_addr_l2[4] + }) === 2'b11); +assign rom_instr_pt[198] = + (({ rom_addr_l2[1] , rom_addr_l2[2] , + rom_addr_l2[3] }) === 3'b001); +assign rom_instr_pt[199] = + (({ rom_addr_l2[2] }) === 1'b0); +assign rom_instr_pt[200] = + (({ rom_addr_l2[0] }) === 1'b1); +assign template[0] = + (rom_instr_pt[1] | rom_instr_pt[4] + | rom_instr_pt[25] | rom_instr_pt[29] + | rom_instr_pt[38] | rom_instr_pt[80] + | rom_instr_pt[99] | rom_instr_pt[155] + | rom_instr_pt[166] | rom_instr_pt[167] + | rom_instr_pt[168] | rom_instr_pt[171] + | rom_instr_pt[181]); +assign template[1] = + (rom_instr_pt[3] | rom_instr_pt[6] + | rom_instr_pt[9] | rom_instr_pt[10] + | rom_instr_pt[14] | rom_instr_pt[16] + | rom_instr_pt[17] | rom_instr_pt[23] + | rom_instr_pt[27] | rom_instr_pt[28] + | rom_instr_pt[32] | rom_instr_pt[33] + | rom_instr_pt[35] | rom_instr_pt[36] + | rom_instr_pt[39] | rom_instr_pt[40] + | rom_instr_pt[41] | rom_instr_pt[42] + | rom_instr_pt[43] | rom_instr_pt[44] + | rom_instr_pt[46] | rom_instr_pt[48] + | rom_instr_pt[49] | rom_instr_pt[50] + | rom_instr_pt[51] | rom_instr_pt[53] + | rom_instr_pt[54] | rom_instr_pt[57] + | rom_instr_pt[59] | rom_instr_pt[61] + | rom_instr_pt[71] | rom_instr_pt[72] + | rom_instr_pt[73] | rom_instr_pt[76] + | rom_instr_pt[78] | rom_instr_pt[82] + | rom_instr_pt[84] | rom_instr_pt[86] + | rom_instr_pt[87] | rom_instr_pt[89] + | rom_instr_pt[91] | rom_instr_pt[92] + | rom_instr_pt[94] | rom_instr_pt[103] + | rom_instr_pt[104] | rom_instr_pt[105] + | rom_instr_pt[109] | rom_instr_pt[112] + | rom_instr_pt[113] | rom_instr_pt[122] + | rom_instr_pt[125] | rom_instr_pt[127] + | rom_instr_pt[132] | rom_instr_pt[134] + | rom_instr_pt[139] | rom_instr_pt[165] + | rom_instr_pt[172] | rom_instr_pt[173] + | rom_instr_pt[177] | rom_instr_pt[180] + | rom_instr_pt[183] | rom_instr_pt[192] + | rom_instr_pt[194]); +assign template[2] = + (rom_instr_pt[6] | rom_instr_pt[8] + | rom_instr_pt[10] | rom_instr_pt[17] + | rom_instr_pt[19] | rom_instr_pt[21] + | rom_instr_pt[22] | rom_instr_pt[24] + | rom_instr_pt[27] | rom_instr_pt[28] + | rom_instr_pt[33] | rom_instr_pt[36] + | rom_instr_pt[40] | rom_instr_pt[41] + | rom_instr_pt[43] | rom_instr_pt[44] + | rom_instr_pt[49] | rom_instr_pt[51] + | rom_instr_pt[56] | rom_instr_pt[57] + | rom_instr_pt[59] | rom_instr_pt[61] + | rom_instr_pt[71] | rom_instr_pt[72] + | rom_instr_pt[103] | rom_instr_pt[104] + | rom_instr_pt[106] | rom_instr_pt[109] + | rom_instr_pt[110] | rom_instr_pt[114] + | rom_instr_pt[123] | rom_instr_pt[125] + | rom_instr_pt[132] | rom_instr_pt[139] + | rom_instr_pt[141] | rom_instr_pt[142] + | rom_instr_pt[143] | rom_instr_pt[149] + | rom_instr_pt[153] | rom_instr_pt[171] + | rom_instr_pt[172] | rom_instr_pt[173] + | rom_instr_pt[177] | rom_instr_pt[183] + | rom_instr_pt[192] | rom_instr_pt[194] + | rom_instr_pt[195]); +assign template[3] = + (rom_instr_pt[3] | rom_instr_pt[6] + | rom_instr_pt[8] | rom_instr_pt[10] + | rom_instr_pt[14] | rom_instr_pt[17] + | rom_instr_pt[19] | rom_instr_pt[20] + | rom_instr_pt[21] | rom_instr_pt[22] + | rom_instr_pt[24] | rom_instr_pt[27] + | rom_instr_pt[28] | rom_instr_pt[29] + | rom_instr_pt[32] | rom_instr_pt[33] + | rom_instr_pt[35] | rom_instr_pt[36] + | rom_instr_pt[38] | rom_instr_pt[39] + | rom_instr_pt[40] | rom_instr_pt[41] + | rom_instr_pt[42] | rom_instr_pt[43] + | rom_instr_pt[44] | rom_instr_pt[46] + | rom_instr_pt[48] | rom_instr_pt[49] + | rom_instr_pt[50] | rom_instr_pt[51] + | rom_instr_pt[53] | rom_instr_pt[56] + | rom_instr_pt[59] | rom_instr_pt[61] + | rom_instr_pt[71] | rom_instr_pt[72] + | rom_instr_pt[73] | rom_instr_pt[77] + | rom_instr_pt[78] | rom_instr_pt[79] + | rom_instr_pt[81] | rom_instr_pt[82] + | rom_instr_pt[84] | rom_instr_pt[86] + | rom_instr_pt[87] | rom_instr_pt[89] + | rom_instr_pt[91] | rom_instr_pt[92] + | rom_instr_pt[94] | rom_instr_pt[95] + | rom_instr_pt[99] | rom_instr_pt[100] + | rom_instr_pt[103] | rom_instr_pt[104] + | rom_instr_pt[105] | rom_instr_pt[106] + | rom_instr_pt[107] | rom_instr_pt[110] + | rom_instr_pt[112] | rom_instr_pt[113] + | rom_instr_pt[114] | rom_instr_pt[123] + | rom_instr_pt[125] | rom_instr_pt[127] + | rom_instr_pt[128] | rom_instr_pt[139] + | rom_instr_pt[141] | rom_instr_pt[142] + | rom_instr_pt[143] | rom_instr_pt[149] + | rom_instr_pt[153] | rom_instr_pt[155] + | rom_instr_pt[167] | rom_instr_pt[168] + | rom_instr_pt[173] | rom_instr_pt[177] + | rom_instr_pt[192]); +assign template[4] = + (rom_instr_pt[1] | rom_instr_pt[4] + | rom_instr_pt[6] | rom_instr_pt[8] + | rom_instr_pt[10] | rom_instr_pt[17] + | rom_instr_pt[19] | rom_instr_pt[20] + | rom_instr_pt[21] | rom_instr_pt[23] + | rom_instr_pt[24] | rom_instr_pt[25] + | rom_instr_pt[27] | rom_instr_pt[28] + | rom_instr_pt[29] | rom_instr_pt[33] + | rom_instr_pt[36] | rom_instr_pt[38] + | rom_instr_pt[40] | rom_instr_pt[41] + | rom_instr_pt[43] | rom_instr_pt[44] + | rom_instr_pt[46] | rom_instr_pt[49] + | rom_instr_pt[51] | rom_instr_pt[56] + | rom_instr_pt[57] | rom_instr_pt[59] + | rom_instr_pt[61] | rom_instr_pt[71] + | rom_instr_pt[72] | rom_instr_pt[80] + | rom_instr_pt[81] | rom_instr_pt[99] + | rom_instr_pt[103] | rom_instr_pt[104] + | rom_instr_pt[106] | rom_instr_pt[107] + | rom_instr_pt[109] | rom_instr_pt[110] + | rom_instr_pt[114] | rom_instr_pt[123] + | rom_instr_pt[125] | rom_instr_pt[132] + | rom_instr_pt[139] | rom_instr_pt[141] + | rom_instr_pt[142] | rom_instr_pt[143] + | rom_instr_pt[149] | rom_instr_pt[153] + | rom_instr_pt[155] | rom_instr_pt[166] + | rom_instr_pt[167] | rom_instr_pt[168] + | rom_instr_pt[172] | rom_instr_pt[173] + | rom_instr_pt[177] | rom_instr_pt[183] + | rom_instr_pt[192]); +assign template[5] = + (rom_instr_pt[3] | rom_instr_pt[6] + | rom_instr_pt[9] | rom_instr_pt[10] + | rom_instr_pt[14] | rom_instr_pt[16] + | rom_instr_pt[17] | rom_instr_pt[22] + | rom_instr_pt[27] | rom_instr_pt[28] + | rom_instr_pt[33] | rom_instr_pt[35] + | rom_instr_pt[36] | rom_instr_pt[39] + | rom_instr_pt[40] | rom_instr_pt[41] + | rom_instr_pt[42] | rom_instr_pt[43] + | rom_instr_pt[46] | rom_instr_pt[48] + | rom_instr_pt[49] | rom_instr_pt[51] + | rom_instr_pt[53] | rom_instr_pt[59] + | rom_instr_pt[60] | rom_instr_pt[73] + | rom_instr_pt[76] | rom_instr_pt[77] + | rom_instr_pt[79] | rom_instr_pt[81] + | rom_instr_pt[82] | rom_instr_pt[86] + | rom_instr_pt[89] | rom_instr_pt[94] + | rom_instr_pt[95] | rom_instr_pt[100] + | rom_instr_pt[103] | rom_instr_pt[105] + | rom_instr_pt[107] | rom_instr_pt[122] + | rom_instr_pt[125] | rom_instr_pt[127] + | rom_instr_pt[128] | rom_instr_pt[139] + | rom_instr_pt[165] | rom_instr_pt[169] + | rom_instr_pt[173] | rom_instr_pt[177] + | rom_instr_pt[192] | rom_instr_pt[194] + ); +assign template[6] = + 1'b0; +assign template[7] = + 1'b0; +assign template[8] = + 1'b0; +assign template[9] = + (rom_instr_pt[1] | rom_instr_pt[4] + | rom_instr_pt[6] | rom_instr_pt[10] + | rom_instr_pt[16] | rom_instr_pt[17] + | rom_instr_pt[23] | rom_instr_pt[29] + | rom_instr_pt[35] | rom_instr_pt[36] + | rom_instr_pt[38] | rom_instr_pt[40] + | rom_instr_pt[41] | rom_instr_pt[42] + | rom_instr_pt[43] | rom_instr_pt[48] + | rom_instr_pt[49] | rom_instr_pt[51] + | rom_instr_pt[53] | rom_instr_pt[56] + | rom_instr_pt[61] | rom_instr_pt[71] + | rom_instr_pt[73] | rom_instr_pt[80] + | rom_instr_pt[82] | rom_instr_pt[86] + | rom_instr_pt[94] | rom_instr_pt[99] + | rom_instr_pt[100] | rom_instr_pt[103] + | rom_instr_pt[105] | rom_instr_pt[112] + | rom_instr_pt[113] | rom_instr_pt[125] + | rom_instr_pt[127] | rom_instr_pt[132] + | rom_instr_pt[139] | rom_instr_pt[155] + | rom_instr_pt[167] | rom_instr_pt[168] + | rom_instr_pt[173] | rom_instr_pt[183] + ); +assign template[10] = + (rom_instr_pt[25] | rom_instr_pt[27] + | rom_instr_pt[32] | rom_instr_pt[33] + | rom_instr_pt[39] | rom_instr_pt[44] + | rom_instr_pt[50] | rom_instr_pt[54] + | rom_instr_pt[57] | rom_instr_pt[72] + | rom_instr_pt[76] | rom_instr_pt[77] + | rom_instr_pt[78] | rom_instr_pt[89] + | rom_instr_pt[91] | rom_instr_pt[92] + | rom_instr_pt[95] | rom_instr_pt[104] + | rom_instr_pt[121] | rom_instr_pt[165] + ); +assign template[11] = + (rom_instr_pt[9] | rom_instr_pt[46] + | rom_instr_pt[81] | rom_instr_pt[107] + | rom_instr_pt[192]); +assign template[12] = + 1'b0; +assign template[13] = + (rom_instr_pt[9]); +assign template[14] = + (rom_instr_pt[14] | rom_instr_pt[16] + | rom_instr_pt[32] | rom_instr_pt[35] + | rom_instr_pt[40] | rom_instr_pt[42] + | rom_instr_pt[43] | rom_instr_pt[44] + | rom_instr_pt[48] | rom_instr_pt[49] + | rom_instr_pt[50] | rom_instr_pt[51] + | rom_instr_pt[53] | rom_instr_pt[54] + | rom_instr_pt[57] | rom_instr_pt[61] + | rom_instr_pt[70] | rom_instr_pt[71] + | rom_instr_pt[73] | rom_instr_pt[78] + | rom_instr_pt[82] | rom_instr_pt[84] + | rom_instr_pt[86] | rom_instr_pt[87] + | rom_instr_pt[89] | rom_instr_pt[91] + | rom_instr_pt[92] | rom_instr_pt[94] + | rom_instr_pt[105] | rom_instr_pt[112] + | rom_instr_pt[113] | rom_instr_pt[125] + | rom_instr_pt[127]); +assign template[15] = + (rom_instr_pt[3] | rom_instr_pt[31] + | rom_instr_pt[56] | rom_instr_pt[72] + | rom_instr_pt[81] | rom_instr_pt[104] + | rom_instr_pt[128]); +assign template[16] = + (rom_instr_pt[32] | rom_instr_pt[39] + | rom_instr_pt[50] | rom_instr_pt[77] + | rom_instr_pt[82] | rom_instr_pt[84] + | rom_instr_pt[92] | rom_instr_pt[108] + | rom_instr_pt[112] | rom_instr_pt[113] + | rom_instr_pt[121]); +assign template[17] = + (rom_instr_pt[24] | rom_instr_pt[35] + | rom_instr_pt[39] | rom_instr_pt[42] + | rom_instr_pt[44] | rom_instr_pt[46] + | rom_instr_pt[48] | rom_instr_pt[53] + | rom_instr_pt[54] | rom_instr_pt[61] + | rom_instr_pt[71] | rom_instr_pt[72] + | rom_instr_pt[73] | rom_instr_pt[77] + | rom_instr_pt[78] | rom_instr_pt[82] + | rom_instr_pt[86] | rom_instr_pt[91] + | rom_instr_pt[94] | rom_instr_pt[104] + | rom_instr_pt[105] | rom_instr_pt[121] + | rom_instr_pt[127]); +assign template[18] = + (rom_instr_pt[77] | rom_instr_pt[121] + | rom_instr_pt[124]); +assign template[19] = + (rom_instr_pt[59] | rom_instr_pt[79] + | rom_instr_pt[107] | rom_instr_pt[121] + | rom_instr_pt[148] | rom_instr_pt[177] + ); +assign template[20] = + (rom_instr_pt[16] | rom_instr_pt[36] + | rom_instr_pt[40] | rom_instr_pt[43] + | rom_instr_pt[49] | rom_instr_pt[51] + | rom_instr_pt[79] | rom_instr_pt[121] + | rom_instr_pt[125] | rom_instr_pt[194] + ); +assign template[21] = + (rom_instr_pt[42] | rom_instr_pt[59] + | rom_instr_pt[60] | rom_instr_pt[71] + | rom_instr_pt[78] | rom_instr_pt[87] + | rom_instr_pt[91] | rom_instr_pt[95] + | rom_instr_pt[100] | rom_instr_pt[112] + | rom_instr_pt[113] | rom_instr_pt[121] + | rom_instr_pt[177]); +assign template[22] = + (rom_instr_pt[16] | rom_instr_pt[28] + | rom_instr_pt[32] | rom_instr_pt[36] + | rom_instr_pt[39] | rom_instr_pt[40] + | rom_instr_pt[43] | rom_instr_pt[49] + | rom_instr_pt[51] | rom_instr_pt[60] + | rom_instr_pt[87] | rom_instr_pt[92] + | rom_instr_pt[100] | rom_instr_pt[123] + | rom_instr_pt[125] | rom_instr_pt[128] + | rom_instr_pt[169]); +assign template[23] = + (rom_instr_pt[8] | rom_instr_pt[16] + | rom_instr_pt[22] | rom_instr_pt[36] + | rom_instr_pt[40] | rom_instr_pt[41] + | rom_instr_pt[43] | rom_instr_pt[46] + | rom_instr_pt[49] | rom_instr_pt[51] + | rom_instr_pt[60] | rom_instr_pt[71] + | rom_instr_pt[77] | rom_instr_pt[81] + | rom_instr_pt[100] | rom_instr_pt[103] + | rom_instr_pt[107] | rom_instr_pt[121] + | rom_instr_pt[125] | rom_instr_pt[139] + | rom_instr_pt[165] | rom_instr_pt[173] + ); +assign template[24] = + (rom_instr_pt[6] | rom_instr_pt[10] + | rom_instr_pt[17] | rom_instr_pt[22] + | rom_instr_pt[27] | rom_instr_pt[33] + | rom_instr_pt[41] | rom_instr_pt[59] + | rom_instr_pt[60] | rom_instr_pt[71] + | rom_instr_pt[76] | rom_instr_pt[79] + | rom_instr_pt[103] | rom_instr_pt[121] + | rom_instr_pt[139] | rom_instr_pt[173] + | rom_instr_pt[177]); +assign template[25] = + (rom_instr_pt[16] | rom_instr_pt[36] + | rom_instr_pt[40] | rom_instr_pt[43] + | rom_instr_pt[49] | rom_instr_pt[51] + | rom_instr_pt[59] | rom_instr_pt[71] + | rom_instr_pt[121] | rom_instr_pt[125] + | rom_instr_pt[177]); +assign template[26] = + (rom_instr_pt[6] | rom_instr_pt[9] + | rom_instr_pt[10] | rom_instr_pt[14] + | rom_instr_pt[16] | rom_instr_pt[17] + | rom_instr_pt[22] | rom_instr_pt[27] + | rom_instr_pt[33] | rom_instr_pt[35] + | rom_instr_pt[36] | rom_instr_pt[39] + | rom_instr_pt[40] | rom_instr_pt[41] + | rom_instr_pt[42] | rom_instr_pt[43] + | rom_instr_pt[46] | rom_instr_pt[48] + | rom_instr_pt[49] | rom_instr_pt[51] + | rom_instr_pt[53] | rom_instr_pt[59] + | rom_instr_pt[60] | rom_instr_pt[71] + | rom_instr_pt[73] | rom_instr_pt[76] + | rom_instr_pt[77] | rom_instr_pt[78] + | rom_instr_pt[79] | rom_instr_pt[81] + | rom_instr_pt[82] | rom_instr_pt[86] + | rom_instr_pt[87] | rom_instr_pt[89] + | rom_instr_pt[91] | rom_instr_pt[94] + | rom_instr_pt[95] | rom_instr_pt[100] + | rom_instr_pt[103] | rom_instr_pt[105] + | rom_instr_pt[107] | rom_instr_pt[112] + | rom_instr_pt[113] | rom_instr_pt[121] + | rom_instr_pt[125] | rom_instr_pt[127] + | rom_instr_pt[139] | rom_instr_pt[165] + | rom_instr_pt[173] | rom_instr_pt[177] + | rom_instr_pt[192] | rom_instr_pt[194] + ); +assign template[27] = + (rom_instr_pt[14] | rom_instr_pt[16] + | rom_instr_pt[28] | rom_instr_pt[32] + | rom_instr_pt[36] | rom_instr_pt[39] + | rom_instr_pt[40] | rom_instr_pt[43] + | rom_instr_pt[48] | rom_instr_pt[49] + | rom_instr_pt[51] | rom_instr_pt[53] + | rom_instr_pt[59] | rom_instr_pt[60] + | rom_instr_pt[73] | rom_instr_pt[77] + | rom_instr_pt[82] | rom_instr_pt[86] + | rom_instr_pt[87] | rom_instr_pt[89] + | rom_instr_pt[92] | rom_instr_pt[95] + | rom_instr_pt[100] | rom_instr_pt[105] + | rom_instr_pt[123] | rom_instr_pt[125] + | rom_instr_pt[127] | rom_instr_pt[128] + | rom_instr_pt[169] | rom_instr_pt[177] + ); +assign template[28] = + (rom_instr_pt[6] | rom_instr_pt[10] + | rom_instr_pt[14] | rom_instr_pt[16] + | rom_instr_pt[17] | rom_instr_pt[22] + | rom_instr_pt[27] | rom_instr_pt[32] + | rom_instr_pt[33] | rom_instr_pt[35] + | rom_instr_pt[36] | rom_instr_pt[39] + | rom_instr_pt[40] | rom_instr_pt[41] + | rom_instr_pt[42] | rom_instr_pt[43] + | rom_instr_pt[48] | rom_instr_pt[49] + | rom_instr_pt[50] | rom_instr_pt[51] + | rom_instr_pt[53] | rom_instr_pt[59] + | rom_instr_pt[73] | rom_instr_pt[76] + | rom_instr_pt[77] | rom_instr_pt[78] + | rom_instr_pt[79] | rom_instr_pt[82] + | rom_instr_pt[84] | rom_instr_pt[86] + | rom_instr_pt[87] | rom_instr_pt[89] + | rom_instr_pt[91] | rom_instr_pt[92] + | rom_instr_pt[94] | rom_instr_pt[95] + | rom_instr_pt[103] | rom_instr_pt[105] + | rom_instr_pt[112] | rom_instr_pt[113] + | rom_instr_pt[121] | rom_instr_pt[125] + | rom_instr_pt[127] | rom_instr_pt[139] + | rom_instr_pt[173] | rom_instr_pt[177] + ); +assign template[29] = + (rom_instr_pt[3] | rom_instr_pt[6] + | rom_instr_pt[10] | rom_instr_pt[14] + | rom_instr_pt[17] | rom_instr_pt[22] + | rom_instr_pt[27] | rom_instr_pt[28] + | rom_instr_pt[32] | rom_instr_pt[33] + | rom_instr_pt[35] | rom_instr_pt[39] + | rom_instr_pt[41] | rom_instr_pt[42] + | rom_instr_pt[48] | rom_instr_pt[50] + | rom_instr_pt[53] | rom_instr_pt[59] + | rom_instr_pt[71] | rom_instr_pt[73] + | rom_instr_pt[76] | rom_instr_pt[77] + | rom_instr_pt[78] | rom_instr_pt[79] + | rom_instr_pt[82] | rom_instr_pt[84] + | rom_instr_pt[86] | rom_instr_pt[87] + | rom_instr_pt[89] | rom_instr_pt[91] + | rom_instr_pt[92] | rom_instr_pt[94] + | rom_instr_pt[95] | rom_instr_pt[100] + | rom_instr_pt[103] | rom_instr_pt[105] + | rom_instr_pt[112] | rom_instr_pt[113] + | rom_instr_pt[122] | rom_instr_pt[127] + | rom_instr_pt[128] | rom_instr_pt[139] + | rom_instr_pt[142] | rom_instr_pt[153] + | rom_instr_pt[169] | rom_instr_pt[173] + | rom_instr_pt[192]); +assign template[30] = + (rom_instr_pt[3] | rom_instr_pt[6] + | rom_instr_pt[10] | rom_instr_pt[14] + | rom_instr_pt[17] | rom_instr_pt[22] + | rom_instr_pt[27] | rom_instr_pt[29] + | rom_instr_pt[32] | rom_instr_pt[33] + | rom_instr_pt[35] | rom_instr_pt[39] + | rom_instr_pt[41] | rom_instr_pt[42] + | rom_instr_pt[48] | rom_instr_pt[50] + | rom_instr_pt[53] | rom_instr_pt[73] + | rom_instr_pt[76] | rom_instr_pt[77] + | rom_instr_pt[78] | rom_instr_pt[79] + | rom_instr_pt[82] | rom_instr_pt[84] + | rom_instr_pt[86] | rom_instr_pt[87] + | rom_instr_pt[89] | rom_instr_pt[90] + | rom_instr_pt[91] | rom_instr_pt[92] + | rom_instr_pt[94] | rom_instr_pt[95] + | rom_instr_pt[103] | rom_instr_pt[105] + | rom_instr_pt[112] | rom_instr_pt[113] + | rom_instr_pt[127] | rom_instr_pt[139] + | rom_instr_pt[170] | rom_instr_pt[173] + | rom_instr_pt[192]); +assign template[31] = + (rom_instr_pt[20] | rom_instr_pt[30] + | rom_instr_pt[66] | rom_instr_pt[80] + | rom_instr_pt[88] | rom_instr_pt[106] + | rom_instr_pt[114] | rom_instr_pt[121] + | rom_instr_pt[143] | rom_instr_pt[149] + ); +assign ucode_end = + (rom_instr_pt[98] | rom_instr_pt[107] + | rom_instr_pt[120] | rom_instr_pt[128] + | rom_instr_pt[129] | rom_instr_pt[131] + | rom_instr_pt[156] | rom_instr_pt[159] + | rom_instr_pt[162] | rom_instr_pt[164] + | rom_instr_pt[175] | rom_instr_pt[178] + ); +assign ucode_end_early = + (rom_instr_pt[111] | rom_instr_pt[184] + | rom_instr_pt[186]); +assign loop_begin = + 1'b0; +assign loop_end = + (rom_instr_pt[37] | rom_instr_pt[64] + | rom_instr_pt[65] | rom_instr_pt[69] + | rom_instr_pt[126] | rom_instr_pt[130] + ); +assign count_src[0] = + (rom_instr_pt[68] | rom_instr_pt[147] + | rom_instr_pt[176] | rom_instr_pt[199] + ); +assign count_src[1] = + (rom_instr_pt[68] | rom_instr_pt[176] + | rom_instr_pt[196] | rom_instr_pt[199] + ); +assign count_src[2] = + (rom_instr_pt[68] | rom_instr_pt[135] + | rom_instr_pt[145] | rom_instr_pt[188] + | rom_instr_pt[199]); +assign ext_rt = + (rom_instr_pt[11] | rom_instr_pt[18] + | rom_instr_pt[28] | rom_instr_pt[33] + | rom_instr_pt[45] | rom_instr_pt[47] + | rom_instr_pt[55] | rom_instr_pt[67] + | rom_instr_pt[85] | rom_instr_pt[87] + | rom_instr_pt[102] | rom_instr_pt[115] + | rom_instr_pt[118] | rom_instr_pt[136] + | rom_instr_pt[137] | rom_instr_pt[144] + | rom_instr_pt[146] | rom_instr_pt[150] + | rom_instr_pt[158] | rom_instr_pt[160] + | rom_instr_pt[161] | rom_instr_pt[174] + | rom_instr_pt[190] | rom_instr_pt[197] + ); +assign ext_s1 = + (rom_instr_pt[33] | rom_instr_pt[36] + | rom_instr_pt[45] | rom_instr_pt[55] + | rom_instr_pt[63] | rom_instr_pt[67] + | rom_instr_pt[74] | rom_instr_pt[85] + | rom_instr_pt[96] | rom_instr_pt[101] + | rom_instr_pt[115] | rom_instr_pt[118] + | rom_instr_pt[135] | rom_instr_pt[136] + | rom_instr_pt[137] | rom_instr_pt[144] + | rom_instr_pt[150] | rom_instr_pt[151] + | rom_instr_pt[152] | rom_instr_pt[157] + | rom_instr_pt[160] | rom_instr_pt[173] + | rom_instr_pt[179] | rom_instr_pt[182] + | rom_instr_pt[185] | rom_instr_pt[189] + ); +assign ext_s2 = + (rom_instr_pt[7] | rom_instr_pt[36] + | rom_instr_pt[45] | rom_instr_pt[47] + | rom_instr_pt[52] | rom_instr_pt[67] + | rom_instr_pt[87] | rom_instr_pt[115] + | rom_instr_pt[137] | rom_instr_pt[138] + | rom_instr_pt[146] | rom_instr_pt[156] + | rom_instr_pt[158] | rom_instr_pt[179] + | rom_instr_pt[198]); +assign ext_s3 = + (rom_instr_pt[22] | rom_instr_pt[116] + | rom_instr_pt[161] | rom_instr_pt[168] + | rom_instr_pt[182] | rom_instr_pt[193] + | rom_instr_pt[197]); +assign sel0_5 = + (rom_instr_pt[156]); +assign sel6_10[0] = + (rom_instr_pt[97] | rom_instr_pt[120] + | rom_instr_pt[122] | rom_instr_pt[128] + | rom_instr_pt[159] | rom_instr_pt[162] + | rom_instr_pt[175]); +assign sel6_10[1] = + (rom_instr_pt[62] | rom_instr_pt[87] + | rom_instr_pt[138] | rom_instr_pt[156] + | rom_instr_pt[179] | rom_instr_pt[181] + | rom_instr_pt[191]); +assign sel11_15[0] = + (rom_instr_pt[36] | rom_instr_pt[63] + | rom_instr_pt[101]); +assign sel11_15[1] = + (rom_instr_pt[5] | rom_instr_pt[7] + | rom_instr_pt[11] | rom_instr_pt[12] + | rom_instr_pt[18] | rom_instr_pt[36] + | rom_instr_pt[63] | rom_instr_pt[96] + | rom_instr_pt[97] | rom_instr_pt[101] + | rom_instr_pt[102] | rom_instr_pt[123] + | rom_instr_pt[146] | rom_instr_pt[156] + | rom_instr_pt[159] | rom_instr_pt[162] + | rom_instr_pt[165] | rom_instr_pt[175] + ); +assign sel16_20[0] = + (rom_instr_pt[174]); +assign sel16_20[1] = + (rom_instr_pt[2] | rom_instr_pt[5] + | rom_instr_pt[22] | rom_instr_pt[26] + | rom_instr_pt[28] | rom_instr_pt[33] + | rom_instr_pt[41] | rom_instr_pt[76] + | rom_instr_pt[97] | rom_instr_pt[116] + | rom_instr_pt[120] | rom_instr_pt[122] + | rom_instr_pt[140] | rom_instr_pt[159] + | rom_instr_pt[162] | rom_instr_pt[165] + | rom_instr_pt[168] | rom_instr_pt[173] + | rom_instr_pt[174] | rom_instr_pt[175] + ); +assign sel21_25[0] = + 1'b0; +assign sel21_25[1] = + (rom_instr_pt[2] | rom_instr_pt[5] + | rom_instr_pt[26] | rom_instr_pt[97] + | rom_instr_pt[99] | rom_instr_pt[120] + | rom_instr_pt[156] | rom_instr_pt[159] + | rom_instr_pt[162] | rom_instr_pt[163] + | rom_instr_pt[168]); +assign sel26_30 = + (rom_instr_pt[2] | rom_instr_pt[5] + | rom_instr_pt[26] | rom_instr_pt[97] + | rom_instr_pt[99] | rom_instr_pt[120] + | rom_instr_pt[156] | rom_instr_pt[159] + | rom_instr_pt[162] | rom_instr_pt[163] + | rom_instr_pt[168]); +assign sel31 = + (rom_instr_pt[2] | rom_instr_pt[5] + | rom_instr_pt[26] | rom_instr_pt[97] + | rom_instr_pt[99] | rom_instr_pt[119] + | rom_instr_pt[140] | rom_instr_pt[154] + | rom_instr_pt[156] | rom_instr_pt[159] + | rom_instr_pt[163]); +assign cr_bf2fxm = + (rom_instr_pt[165]); +assign skip_cond = + (rom_instr_pt[44] | rom_instr_pt[47] + | rom_instr_pt[52] | rom_instr_pt[58] + | rom_instr_pt[74] | rom_instr_pt[83] + | rom_instr_pt[104] | rom_instr_pt[112] + | rom_instr_pt[117] | rom_instr_pt[138] + ); +assign skip_zero = + 1'b0; +assign skip_nop = + (rom_instr_pt[13] | rom_instr_pt[15] + | rom_instr_pt[34] | rom_instr_pt[75] + | rom_instr_pt[93] | rom_instr_pt[133] + | rom_instr_pt[187]); +assign loop_addr[0] = + (rom_instr_pt[200]); +assign loop_addr[1] = + (rom_instr_pt[44] | rom_instr_pt[119] + | rom_instr_pt[122] | rom_instr_pt[140] + | rom_instr_pt[175] | rom_instr_pt[182] + | rom_instr_pt[185] | rom_instr_pt[197] + ); +assign loop_addr[2] = + (rom_instr_pt[36] | rom_instr_pt[45] + | rom_instr_pt[58] | rom_instr_pt[67] + | rom_instr_pt[75] | rom_instr_pt[115] + | rom_instr_pt[119] | rom_instr_pt[122] + | rom_instr_pt[133] | rom_instr_pt[140] + | rom_instr_pt[157] | rom_instr_pt[185] + | rom_instr_pt[187] | rom_instr_pt[189] + ); +assign loop_addr[3] = + (rom_instr_pt[67] | rom_instr_pt[133] + | rom_instr_pt[163] | rom_instr_pt[182] + | rom_instr_pt[187] | rom_instr_pt[189] + | rom_instr_pt[193] | rom_instr_pt[198] + ); +assign loop_addr[4] = + (rom_instr_pt[75] | rom_instr_pt[115] + | rom_instr_pt[133] | rom_instr_pt[140] + | rom_instr_pt[151] | rom_instr_pt[157] + | rom_instr_pt[197]); +assign loop_addr[5] = + (rom_instr_pt[22] | rom_instr_pt[67] + | rom_instr_pt[75] | rom_instr_pt[115] + | rom_instr_pt[122] | rom_instr_pt[140] + | rom_instr_pt[150] | rom_instr_pt[158] + | rom_instr_pt[173] | rom_instr_pt[190] + | rom_instr_pt[193]); +assign loop_addr[6] = + (rom_instr_pt[67] | rom_instr_pt[115] + | rom_instr_pt[119] | rom_instr_pt[122] + | rom_instr_pt[140]); +assign loop_addr[7] = + (rom_instr_pt[22] | rom_instr_pt[58] + | rom_instr_pt[67] | rom_instr_pt[115] + | rom_instr_pt[140] | rom_instr_pt[168] + | rom_instr_pt[173] | rom_instr_pt[175] + | rom_instr_pt[182]); +assign loop_addr[8] = + (rom_instr_pt[22] | rom_instr_pt[45] + | rom_instr_pt[58] | rom_instr_pt[67] + | rom_instr_pt[75] | rom_instr_pt[133] + | rom_instr_pt[140] | rom_instr_pt[157] + | rom_instr_pt[158] | rom_instr_pt[163] + | rom_instr_pt[168] | rom_instr_pt[173] + | rom_instr_pt[182] | rom_instr_pt[193] + | rom_instr_pt[198]); +assign loop_addr[9] = + 1'b0; +assign loop_init[0] = + 1'b0; +assign loop_init[1] = + 1'b0; +assign loop_init[2] = + 1'b0; +assign ep = + (rom_instr_pt[7] | rom_instr_pt[22] + | rom_instr_pt[41] | rom_instr_pt[116] + | rom_instr_pt[146]); + +//assign_end + + // Old FDIV/FSQRT + //end generate; + //| 1111000001 | 11111100001-----0000000000111100 0 - 0 - --- 1 0 1 1 0 00 10 00 00 0 0 0 0 - 0 ---------- --- - | # fnmsub s1,FB,s0,s0 + //| 1111000011 | 11111100011000010000100001111010 0 - 0 - --- 1 1 1 1 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # fmadd s3,s1,s1,s1 + //| 1111000101 | 11111100000----------00010111100 0 - 0 - --- 1 0 0 1 0 00 10 11 00 0 0 0 0 - 0 ---------- --- - | # fnmsub s0,FB,s2,FA + //| 1111000111 | 11111100000000010000000000110010 0 - 0 - --- 1 1 0 1 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # fmul s0,s1,s0 + //| 1111001001 | 11111100011000000001000011111010 0 - 0 - --- 1 1 1 1 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # fmadd s3,s0,s3,s2 + //| 1111001011 | 11111100010----------00011111100 0 - 0 - --- 1 0 0 1 0 00 10 11 00 0 0 0 0 - 0 ---------- --- - | # fnmsub s2,FB,s3,FA + //| 1111001101 | 111111-----00001000000000010001- 1 - 0 - --- 0 1 1 1 0 01 00 00 00 0 1 0 0 - 0 ---------- --- - | # fmul_uc FT,s1,s0,s0 include s0 in 16-20 + //| 1111010001 | 11111100011-----0000000000111100 0 - 0 - --- 1 0 1 1 0 00 10 00 00 0 0 0 0 - 0 ---------- --- - | # fnmsub s3,FB,s0,s0 + //| 1111010011 | 11101100001000000000000011111010 0 - 0 - --- 1 1 1 1 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # fmadds s1,s0,s3,s0 + //| 1111010101 | 11101100000----------00001111100 0 - 0 - --- 1 0 0 1 0 00 10 11 00 0 0 0 0 - 0 ---------- --- - | # fnmsub s0,FB,s1,FA + //| 1111010111 | 11101100000----------00001111100 0 - 0 - --- 1 0 0 1 0 00 10 11 00 0 0 0 0 - 0 ---------- --- - | # fnmsub s0,FB,s1,FA + //| 1111100001 | 11111100001000000000000000110010 0 - 0 - --- 1 1 0 1 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # fmul s1,s0,s0, + //| 1111100011 | 11111100000000010000100010111100 0 - 0 - --- 1 1 1 1 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # fnmsub s0,s1,s2,s1 + //| 1111100101 | 11111100010000010000100000111010 0 - 0 - --- 1 1 1 1 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # fmadd s2,s1,s0,s1 + //| 1111100111 | 11111100001000000001100010111010 0 - 0 - --- 1 1 1 1 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # fmadd s1,s0,s2,s3 + //| 1111101001 | 1111110000000001-----00001111100 0 - 0 - --- 1 1 0 1 0 00 00 01 00 0 0 0 0 - 0 ---------- --- - | # fnmsub s0,s1,s1,FB + //| 1111101011 | 1111110000000001-----00011111100 0 - 0 - --- 1 1 0 1 0 00 00 01 00 0 0 0 0 - 0 ---------- --- - | # fnmsub s0,s1,s3,FB + //| 1111110001 | 11111100010000000000000000110010 0 - 0 - --- 1 1 0 1 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # fmul s1,s0,s0, + //| 1111110011 | 1111110000000011-----00011111100 0 - 0 - --- 1 1 0 1 0 00 00 01 00 0 0 0 0 - 0 ---------- --- - | # fnmsub s0,s2,s2,FB + //| 1111110101 | 11101100011000000001100010111010 0 - 0 - --- 1 1 1 1 0 00 00 00 00 0 0 0 0 - 0 ---------- --- - | # fmadds s3,s0,s1,s2 + //| 1111110111 | 1110110001000011-----00011111100 0 - 0 - --- 1 1 0 1 0 00 00 01 00 0 0 0 0 - 0 ---------- --- - | # fnmsubs s2,s3,s3,FB + //| 1111111001 | 111011-----00001000000000010001- 1 - 0 - --- 0 1 1 1 0 01 00 00 00 0 1 0 0 - 0 ---------- --- - | # fmuls_uc FT,s1,s0,s0 include s0 in 16-20 + //32-bit core + //c32: if (regmode = 5) generate begin + //end generate; + + + // ??? Do I want to optimize any terms? + // ??? Which is better: on-off, or on-dc? + // ??? Do we want to DC template fields not being used? + + assign rom_addr_d = rom_addr; + + assign rom_data = {template, ucode_end, ucode_end_early, loop_begin, loop_end, count_src, ext_rt, ext_s1, ext_s2, ext_s3, sel0_5, sel6_10, sel11_15, sel16_20, sel21_25, sel26_30, sel31, cr_bf2fxm, skip_cond, skip_zero, skip_nop, loop_addr, loop_init, ep}; + + //--------------------------------------------------------------------- + // Latches + //--------------------------------------------------------------------- + + tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(0)) rom_addr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rom_act), + .thold_b(pc_iu_func_sl_thold_0_b), + .sg(pc_iu_sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rom_addr_offset:rom_addr_offset + 10 - 1]), + .scout(sov[rom_addr_offset:rom_addr_offset + 10 - 1]), + .din(rom_addr_d), + .dout(rom_addr_l2) + ); + + //--------------------------------------------------------------------- + // Scan + //--------------------------------------------------------------------- + assign siv[0:scan_right] = {sov[1:scan_right], scan_in}; + assign scan_out = sov[0]; + +endmodule diff --git a/dev/verilog/work/lq.v b/dev/verilog/work/lq.v new file mode 100755 index 0000000..8ed07c5 --- /dev/null +++ b/dev/verilog/work/lq.v @@ -0,0 +1,2655 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: lq Top +// +//***************************************************************************** + +`include "tri_a2o.vh" + +(* recursive_synthesis="0" *) + +module lq( + xu_lq_spr_ccr2_en_trace, + xu_lq_spr_ccr2_en_pc, + xu_lq_spr_ccr2_en_ditc, + xu_lq_spr_ccr2_en_icswx, + xu_lq_spr_ccr2_dfrat, + xu_lq_spr_ccr2_dfratsc, + xu_lq_spr_ccr2_ap, + xu_lq_spr_ccr2_ucode_dis, + xu_lq_spr_ccr2_notlb, + xu_lq_spr_xucr4_mmu_mchk, + xu_lq_spr_xucr4_mddmh, + xu_lq_spr_xucr0_clkg_ctl, + xu_lq_spr_xucr0_wlk, + xu_lq_spr_xucr0_mbar_ack, + xu_lq_spr_xucr0_tlbsync, + xu_lq_spr_xucr0_dcdis, + xu_lq_spr_xucr0_aflsta, + xu_lq_spr_xucr0_flsta, + xu_lq_spr_xucr0_clfc, + xu_lq_spr_xucr0_cls, + xu_lq_spr_xucr0_trace_um, + xu_lq_spr_xucr0_cred, + xu_lq_spr_xucr0_mddp, + xu_lq_spr_xucr0_mdcp, + xu_lq_spr_dbcr0_dac1, + xu_lq_spr_dbcr0_dac2, + xu_lq_spr_dbcr0_dac3, + xu_lq_spr_dbcr0_dac4, + xu_lq_spr_dbcr0_idm, + xu_lq_spr_epcr_duvd, + xu_lq_spr_msr_cm, + xu_lq_spr_msr_fp, + xu_lq_spr_msr_spv, + xu_lq_spr_msr_gs, + xu_lq_spr_msr_pr, + xu_lq_spr_msr_ds, + xu_lq_spr_msr_de, + xu_lq_spr_msr_ucle, + xu_lq_spr_msrp_uclep, + iu_lq_spr_iucr0_icbi_ack, + lq_xu_spr_xucr0_cul, + lq_xu_spr_xucr0_cslc_xuop, + lq_xu_spr_xucr0_cslc_binv, + lq_xu_spr_xucr0_clo, + lq_iu_spr_dbcr3_ivc, + slowspr_val_in, + slowspr_rw_in, + slowspr_etid_in, + slowspr_addr_in, + slowspr_data_in, + slowspr_done_in, + slowspr_val_out, + slowspr_rw_out, + slowspr_etid_out, + slowspr_addr_out, + slowspr_data_out, + slowspr_done_out, + iu_lq_cp_flush, + iu_lq_recirc_val, + iu_lq_cp_next_itag_t0, + `ifndef THREADS1 + iu_lq_cp_next_itag_t1, + `endif + iu_lq_isync, + iu_lq_csync, + lq0_iu_execute_vld, + lq0_iu_recirc_val, + lq0_iu_itag, + lq0_iu_flush2ucode, + lq0_iu_flush2ucode_type, + lq0_iu_exception_val, + lq0_iu_exception, + lq0_iu_dear_val, + lq0_iu_n_flush, + lq0_iu_np1_flush, + lq0_iu_dacr_type, + lq0_iu_dacrw, + lq0_iu_instr, + lq0_iu_eff_addr, + lq1_iu_execute_vld, + lq1_iu_itag, + lq1_iu_exception_val, + lq1_iu_exception, + lq1_iu_n_flush, + lq1_iu_np1_flush, + lq1_iu_dacr_type, + lq1_iu_dacrw, + lq1_iu_perf_events, + lq_iu_credit_free, + sq_iu_credit_free, + iu_lq_i0_completed, + iu_lq_i0_completed_itag_t0, + `ifndef THREADS1 + iu_lq_i0_completed_itag_t1, + `endif + iu_lq_i1_completed, + iu_lq_i1_completed_itag_t0, + `ifndef THREADS1 + iu_lq_i1_completed_itag_t1, + `endif + iu_lq_request, + iu_lq_cTag, + iu_lq_ra, + iu_lq_wimge, + iu_lq_userdef, + lq_iu_icbi_val, + lq_iu_icbi_addr, + iu_lq_icbi_complete, + lq_iu_ici_val, + xu_lq_act, + xu_lq_val, + xu_lq_is_eratre, + xu_lq_is_eratwe, + xu_lq_is_eratsx, + xu_lq_is_eratilx, + xu_lq_ws, + xu_lq_ra_entry, + xu_lq_rs_data, + xu_lq_hold_req, + lq_xu_ex5_data, + lq_xu_ord_par_err, + lq_xu_ord_read_done, + lq_xu_ord_write_done, + lq_xu_dbell_val, + lq_xu_dbell_type, + lq_xu_dbell_brdcast, + lq_xu_dbell_lpid_match, + lq_xu_dbell_pirtag, + rv_lq_rv1_i0_vld, + rv_lq_rv1_i0_ucode_preissue, + rv_lq_rv1_i0_2ucode, + rv_lq_rv1_i0_ucode_cnt, + rv_lq_rv1_i0_s3_t, + rv_lq_rv1_i0_isLoad, + rv_lq_rv1_i0_isStore, + rv_lq_rv1_i0_itag, + rv_lq_rv1_i0_rte_lq, + rv_lq_rv1_i0_rte_sq, + rv_lq_rv1_i0_ifar, + rv_lq_rv1_i1_vld, + rv_lq_rv1_i1_ucode_preissue, + rv_lq_rv1_i1_2ucode, + rv_lq_rv1_i1_ucode_cnt, + rv_lq_rv1_i1_s3_t, + rv_lq_rv1_i1_isLoad, + rv_lq_rv1_i1_isStore, + rv_lq_rv1_i1_itag, + rv_lq_rv1_i1_rte_lq, + rv_lq_rv1_i1_rte_sq, + rv_lq_rv1_i1_ifar, + rv_lq_rvs_empty, + rv_lq_vld, + rv_lq_isLoad, + rv_lq_ex0_itag, + rv_lq_ex0_instr, + rv_lq_ex0_ucode, + rv_lq_ex0_ucode_cnt, + rv_lq_ex0_t1_v, + rv_lq_ex0_t1_p, + rv_lq_ex0_t3_p, + rv_lq_ex0_s1_v, + rv_lq_ex0_s2_v, + lq_rv_itag0_vld, + lq_rv_itag0, + lq_rv_itag0_abort, + lq_rv_ex2_s1_abort, + lq_rv_ex2_s2_abort, + lq_rv_hold_all, + lq_rv_itag1_vld, + lq_rv_itag1, + lq_rv_itag1_restart, + lq_rv_itag1_abort, + lq_rv_itag1_hold, + lq_rv_itag1_cord, + lq_rv_itag2_vld, + lq_rv_itag2, + lq_rv_clr_hold, + rv_lq_ex0_s1_xu0_sel, + rv_lq_ex0_s2_xu0_sel, + rv_lq_ex0_s1_xu1_sel, + rv_lq_ex0_s2_xu1_sel, + rv_lq_ex0_s1_lq_sel, + rv_lq_ex0_s2_lq_sel, + rv_lq_ex0_s1_rel_sel, + rv_lq_ex0_s2_rel_sel, + xu_lq_xer_cp_rd, + rv_lq_gpr_ex1_r0d, + rv_lq_gpr_ex1_r1d, + lq_rv_gpr_ex6_we, + lq_rv_gpr_ex6_wa, + lq_rv_gpr_ex6_wd, + lq_xu_gpr_ex5_we, + lq_xu_gpr_ex5_wa, + lq_rv_gpr_rel_we, + lq_xu_gpr_rel_we, + lq_xu_axu_rel_we, + lq_xu_axu_rel_le, + lq_rv_gpr_rel_wa, + lq_xu_gpr_rel_wa, + lq_rv_gpr_rel_wd, + lq_xu_gpr_rel_wd, + lq_xu_cr_l2_we, + lq_xu_cr_l2_wa, + lq_xu_cr_l2_wd, + lq_xu_cr_ex5_we, + lq_xu_cr_ex5_wa, + lq_xu_ex5_abort, + xu0_lq_ex3_act, + xu0_lq_ex3_abort, + xu0_lq_ex3_rt, + xu0_lq_ex4_rt, + xu0_lq_ex6_act, + xu0_lq_ex6_rt, + lq_xu_ex5_act, + lq_xu_ex5_cr, + lq_xu_ex5_rt, + xu1_lq_ex3_act, + xu1_lq_ex3_abort, + xu1_lq_ex3_rt, + xu1_lq_ex2_stq_val, + xu1_lq_ex2_stq_itag, + xu1_lq_ex2_stq_size, + xu1_lq_ex2_stq_dvc1_cmp, + xu1_lq_ex2_stq_dvc2_cmp, + xu1_lq_ex3_illeg_lswx, + xu1_lq_ex3_strg_noop, + xu_lq_axu_ex_stq_val, + xu_lq_axu_ex_stq_itag, + xu_lq_axu_exp1_stq_data, + lq_xu_axu_ex4_addr, + lq_xu_axu_ex5_we, + lq_xu_axu_ex5_le, + mm_lq_lsu_req, + mm_lq_lsu_ttype, + mm_lq_lsu_wimge, + mm_lq_lsu_u, + mm_lq_lsu_addr, + mm_lq_lsu_lpid, + mm_lq_lsu_gs, + mm_lq_lsu_ind, + mm_lq_lsu_lbit, + mm_lq_lsu_lpidr, + lq_mm_lsu_token, + mm_lq_hold_req, + mm_lq_hold_done, + mm_lq_pid_t0, + mm_lq_mmucr0_t0, + `ifndef THREADS1 + mm_lq_pid_t1, + mm_lq_mmucr0_t1, + `endif + mm_lq_mmucr1, + mm_lq_rel_val, + mm_lq_rel_data, + mm_lq_rel_emq, + mm_lq_itag, + mm_lq_tlb_miss, + mm_lq_tlb_inelig, + mm_lq_pt_fault, + mm_lq_lrat_miss, + mm_lq_tlb_multihit, + mm_lq_tlb_par_err, + mm_lq_lru_par_err, + mm_lq_snoop_coming, + mm_lq_snoop_val, + mm_lq_snoop_attr, + mm_lq_snoop_vpn, + lq_mm_snoop_ack, + lq_mm_req, + lq_mm_req_nonspec, + lq_mm_req_itag, + lq_mm_req_epn, + lq_mm_thdid, + lq_mm_req_emq, + lq_mm_ttype, + lq_mm_state, + lq_mm_lpid, + lq_mm_tid, + lq_mm_mmucr0_we, + lq_mm_mmucr0, + lq_mm_mmucr1_we, + lq_mm_mmucr1, + lq_mm_lmq_stq_empty, + lq_mm_perf_dtlb, + lq_xu_quiesce, + lq_pc_ldq_quiesce, + lq_pc_stq_quiesce, + lq_pc_pfetch_quiesce, + pc_lq_inj_dcachedir_ldp_parity, + pc_lq_inj_dcachedir_ldp_multihit, + pc_lq_inj_dcachedir_stp_parity, + pc_lq_inj_dcachedir_stp_multihit, + pc_lq_inj_dcache_parity, + pc_lq_inj_prefetcher_parity, + pc_lq_inj_relq_parity, + lq_pc_err_derat_parity, + lq_pc_err_dir_ldp_parity, + lq_pc_err_dir_stp_parity, + lq_pc_err_relq_parity, + lq_pc_err_dcache_parity, + lq_pc_err_derat_multihit, + lq_pc_err_dir_ldp_multihit, + lq_pc_err_dir_stp_multihit, + lq_pc_err_invld_reld, + lq_pc_err_l2intrf_ecc, + lq_pc_err_l2intrf_ue, + lq_pc_err_l2credit_overrun, + pc_lq_ram_active, + lq_pc_ram_data_val, + lq_pc_ram_data, + lq_pc_err_prefetcher_parity, + pc_lq_trace_bus_enable, + pc_lq_debug_mux1_ctrls, + pc_lq_debug_mux2_ctrls, + pc_lq_instr_trace_mode, + pc_lq_instr_trace_tid, + debug_bus_in, + coretrace_ctrls_in, + debug_bus_out, + coretrace_ctrls_out, + pc_lq_event_bus_enable, + pc_lq_event_count_mode, + event_bus_in, + event_bus_out, + an_ac_coreid, + an_ac_sync_ack, + an_ac_stcx_complete, + an_ac_stcx_pass, + an_ac_icbi_ack, + an_ac_icbi_ack_thread, + an_ac_back_inv, + an_ac_back_inv_addr, + an_ac_back_inv_target_bit1, + an_ac_back_inv_target_bit3, + an_ac_back_inv_target_bit4, + an_ac_flh2l2_gate, + an_ac_req_ld_pop, + an_ac_req_st_pop, + an_ac_req_st_gather, + an_ac_reld_data_vld, + an_ac_reld_core_tag, + an_ac_reld_data, + an_ac_reld_qw, + an_ac_reld_ecc_err, + an_ac_reld_ecc_err_ue, + an_ac_reld_data_coming, + an_ac_reld_ditc, + an_ac_reld_crit_qw, + an_ac_reld_l1_dump, + an_ac_req_spare_ctrl_a1, + ac_an_req_pwr_token, + ac_an_req, + ac_an_req_ra, + ac_an_req_ttype, + ac_an_req_thread, + ac_an_req_wimg_w, + ac_an_req_wimg_i, + ac_an_req_wimg_m, + ac_an_req_wimg_g, + ac_an_req_user_defined, + ac_an_req_spare_ctrl_a0, + ac_an_req_ld_core_tag, + ac_an_req_ld_xfr_len, + ac_an_st_byte_enbl, + ac_an_st_data, + ac_an_req_endian, + ac_an_st_data_pwr_token, +// vcs, +// vdd, +// gnd, + nclk, + pc_lq_init_reset, + pc_lq_ccflush_dc, + pc_lq_gptr_sl_thold_3, + pc_lq_time_sl_thold_3, + pc_lq_repr_sl_thold_3, + pc_lq_bolt_sl_thold_3, + pc_lq_abst_sl_thold_3, + pc_lq_abst_slp_sl_thold_3, + pc_lq_func_sl_thold_3, + pc_lq_func_slp_sl_thold_3, + pc_lq_cfg_sl_thold_3, + pc_lq_cfg_slp_sl_thold_3, + pc_lq_regf_slp_sl_thold_3, + pc_lq_func_nsl_thold_3, + pc_lq_func_slp_nsl_thold_3, + pc_lq_ary_nsl_thold_3, + pc_lq_ary_slp_nsl_thold_3, + pc_lq_sg_3, + pc_lq_fce_3, + pc_lq_abist_wl64_comp_ena, + pc_lq_abist_g8t_wenb, + pc_lq_abist_g8t1p_renb_0, + pc_lq_abist_g8t_dcomp, + pc_lq_abist_g8t_bw_1, + pc_lq_abist_g8t_bw_0, + pc_lq_abist_di_0, + pc_lq_abist_waddr_0, + pc_lq_abist_ena_dc, + pc_lq_abist_raw_dc_b, + pc_lq_abist_g6t_bw, + pc_lq_abist_di_g6t_2r, + pc_lq_abist_wl256_comp_ena, + pc_lq_abist_dcomp_g6t_2r, + pc_lq_abist_raddr_0, + pc_lq_abist_g6t_r_wb, + pc_lq_bo_enable_3, + pc_lq_bo_unload, + pc_lq_bo_repair, + pc_lq_bo_reset, + pc_lq_bo_shdata, + pc_lq_bo_select, + lq_pc_bo_fail, + lq_pc_bo_diagout, + an_ac_lbist_ary_wrt_thru_dc, + an_ac_scan_dis_dc_b, + an_ac_scan_diag_dc, + an_ac_lbist_en_dc, + an_ac_atpg_en_dc, + an_ac_grffence_en_dc, + gptr_scan_in, + gptr_scan_out, + abst_scan_in, + abst_scan_out, + time_scan_in, + time_scan_out, + repr_scan_in, + repr_scan_out, + regf_scan_in, + regf_scan_out, + ccfg_scan_in, + ccfg_scan_out, + func_scan_in, + func_scan_out +); + +// Parameters used from tri_a2o.vh +// parameter `THREADS = 2; +// parameter THREAD_POOL_ENC = 1; +// parameter EFF_IFAR_WIDTH = 20; +// parameter EFF_IFAR = 62; +// parameter ITAG_SIZE_ENC = 7; +// parameter GPR_WIDTH = 64; +// parameter GPR_WIDTH_ENC = 6; +// parameter GPR_POOL_ENC = 6; +// parameter AXU_SPARE_ENC = 3; +// parameter XER_WIDTH = 10; +// parameter XER_POOL_ENC = 4; +// parameter CR_WIDTH = 4; +// parameter CR_POOL_ENC = 5; +// parameter XU0_PIPE_START = 2; +// parameter XU0_PIPE_END = 8; +// parameter XU1_PIPE_START = 2; +// parameter XU1_PIPE_END = 5; +// parameter LQ_LOAD_PIPE_START = 4; +// parameter LQ_LOAD_PIPE_END = 8; +// parameter LQ_REL_PIPE_START = 2; +// parameter LQ_REL_PIPE_END = 4; +// parameter EMQ_ENTRIES = 4; +// parameter LMQ_ENTRIES = 8; +// parameter LMQ_ENTRIES_ENC = 3; +// parameter LGQ_ENTRIES = 8; // Load Gather Queue Size +// parameter STQ_ENTRIES = 12; +// parameter STQ_FWD_ENTRIES = 4; +// parameter STQ_ENTRIES_ENC = 4; +// parameter STQ_DATA_SIZE = 64; // 64 or 128 Bit store data sizes supported +// parameter LDSTQ_ENTRIES = 16; +// parameter LDSTQ_ENTRIES_ENC = 4; +// parameter IUQ_ENTRIES = 4; +// parameter MMQ_ENTRIES = 1; +// parameter REAL_IFAR_WIDTH = 42; +// parameter L_ENDIAN_M = 1; +// parameter DC_SIZE = 15; +// parameter CL_SIZE = 6; +// parameter LOAD_CREDITS = 8; +// parameter STORE_CREDITS = 32; +// parameter UCODE_ENTRIES_ENC = 3; +// parameter BUILD_PFETCH = 1; // 1=> include pfetch in the build, 0=> build without pfetch +// parameter PF_IFAR_WIDTH = 12; // number of IAR bits used by prefetch +// parameter PFETCH_INITIAL_DEPTH = 0; // the initial value for the SPR that determines how many lines to prefetch +// parameter PFETCH_Q_SIZE_ENC = 3; // number of bits to address queue size (3 => 8 entries, 4 => 16 entries) +// parameter PFETCH_Q_SIZE = 8; // number of entries in prefetch queue +parameter XU0_PIPE_START = `FXU0_PIPE_START+1; +parameter XU0_PIPE_END = `FXU0_PIPE_END; +parameter XU1_PIPE_START = `FXU1_PIPE_START+1; +parameter XU1_PIPE_END = `FXU1_PIPE_END; + +//-------------------------------------------------------------- +// SPR Interface +//-------------------------------------------------------------- +input xu_lq_spr_ccr2_en_trace; // MTSPR Trace is Enabled +input xu_lq_spr_ccr2_en_pc; // MSGSND is Enabled +input xu_lq_spr_ccr2_en_ditc; // DITC is Enabled +input xu_lq_spr_ccr2_en_icswx; // ICSWX is Enabled +input xu_lq_spr_ccr2_dfrat; // Force Real Address Translation +input [0:8] xu_lq_spr_ccr2_dfratsc; // 0:4: wimge, 5:8: u0:3 +input xu_lq_spr_ccr2_ap; // AP Available +input xu_lq_spr_ccr2_ucode_dis; // Ucode Disabled +input xu_lq_spr_ccr2_notlb; // MMU is disabled +input xu_lq_spr_xucr4_mmu_mchk; // Machine Check on a Data ERAT Parity or Multihit Error +input xu_lq_spr_xucr4_mddmh; // Machine Check on Data Cache Directory Multihit Error +input xu_lq_spr_xucr0_clkg_ctl; // Clock Gating Override +input xu_lq_spr_xucr0_wlk; // Data Cache Way Locking Enable +input xu_lq_spr_xucr0_mbar_ack; // L2 ACK of membar and lwsync +input xu_lq_spr_xucr0_tlbsync; // L2 ACK of tlbsync +input xu_lq_spr_xucr0_dcdis; // Data Cache Disable +input xu_lq_spr_xucr0_aflsta; // AXU Force Load/Store Alignment interrupt +input xu_lq_spr_xucr0_flsta; // FX Force Load/Store Alignment interrupt +input xu_lq_spr_xucr0_clfc; // Cache Directory Lock Flash Clear +input xu_lq_spr_xucr0_cls; // Cacheline Size = 1 => 128Byte size, 0 => 64Byte size +input [0:`THREADS-1] xu_lq_spr_xucr0_trace_um; // TRACE SPR is Enabled in user mode +input xu_lq_spr_xucr0_cred; // L2 Credit Control +input xu_lq_spr_xucr0_mddp; // Machine Check on Data Cache Directory Parity Error +input xu_lq_spr_xucr0_mdcp; // Machine Check on Data Cache Parity Error + + // JK Multidimmensional port +input [0:(`THREADS*2)-1] xu_lq_spr_dbcr0_dac1; // Data Address Compare 1 Debug Event Enable +input [0:(`THREADS*2)-1] xu_lq_spr_dbcr0_dac2; // Data Address Compare 2 Debug Event Enable +input [0:(`THREADS*2)-1] xu_lq_spr_dbcr0_dac3; // Data Address Compare 3 Debug Event Enable +input [0:(`THREADS*2)-1] xu_lq_spr_dbcr0_dac4; // Data Address Compare 4 Debug Event Enable + + +input [0:`THREADS-1] xu_lq_spr_dbcr0_idm; // Internal Debug Mode Enable +input [0:`THREADS-1] xu_lq_spr_epcr_duvd; // Disable Hypervisor Debug +input [0:`THREADS-1] xu_lq_spr_msr_cm; // 64bit mode enable +input [0:`THREADS-1] xu_lq_spr_msr_fp; // FP Available +input [0:`THREADS-1] xu_lq_spr_msr_spv; // VEC Available +input [0:`THREADS-1] xu_lq_spr_msr_gs; // Guest State +input [0:`THREADS-1] xu_lq_spr_msr_pr; // Problem State +input [0:`THREADS-1] xu_lq_spr_msr_ds; // Data Address Space +input [0:`THREADS-1] xu_lq_spr_msr_de; // Debug Interrupt Enable +input [0:`THREADS-1] xu_lq_spr_msr_ucle; // User Cache Locking Enable +input [0:`THREADS-1] xu_lq_spr_msrp_uclep; // User Cache Locking Enable Protect +input iu_lq_spr_iucr0_icbi_ack; // L2 ICBI ACK Enable +output lq_xu_spr_xucr0_cul; // Cache Lock unable to lock +output lq_xu_spr_xucr0_cslc_xuop; // Invalidate type instruction invalidated lock +output lq_xu_spr_xucr0_cslc_binv; // Back-Invalidate invalidated lock +output lq_xu_spr_xucr0_clo; // Cache Lock instruction caused an overlock +output [0:`THREADS-1] lq_iu_spr_dbcr3_ivc; // Instruction Value Compare Enabled +input slowspr_val_in; +input slowspr_rw_in; +input [0:1] slowspr_etid_in; +input [0:9] slowspr_addr_in; +input [64-(2**`GPR_WIDTH_ENC):63] slowspr_data_in; +input slowspr_done_in; +output slowspr_val_out; +output slowspr_rw_out; +output [0:1] slowspr_etid_out; +output [0:9] slowspr_addr_out; +output [64-(2**`GPR_WIDTH_ENC):63] slowspr_data_out; +output slowspr_done_out; + +//-------------------------------------------------------------- +// CP Interface +//-------------------------------------------------------------- +input [0:`THREADS-1] iu_lq_cp_flush; +input [0:`THREADS-1] iu_lq_recirc_val; + // JK Multidimmensional port +input [0:`ITAG_SIZE_ENC-1] iu_lq_cp_next_itag_t0; +`ifndef THREADS1 + input [0:`ITAG_SIZE_ENC-1] iu_lq_cp_next_itag_t1; +`endif + +input iu_lq_isync; +input iu_lq_csync; +output [0:`THREADS-1] lq0_iu_execute_vld; +output [0:`THREADS-1] lq0_iu_recirc_val; +output [0:`ITAG_SIZE_ENC-1] lq0_iu_itag; +output lq0_iu_flush2ucode; +output lq0_iu_flush2ucode_type; +output lq0_iu_exception_val; +output [0:5] lq0_iu_exception; +output [0:`THREADS-1] lq0_iu_dear_val; +output lq0_iu_n_flush; +output lq0_iu_np1_flush; +output lq0_iu_dacr_type; +output [0:3] lq0_iu_dacrw; +output [0:31] lq0_iu_instr; +output [64-(2**`GPR_WIDTH_ENC):63] lq0_iu_eff_addr; +output [0:`THREADS-1] lq1_iu_execute_vld; +output [0:`ITAG_SIZE_ENC-1] lq1_iu_itag; +output lq1_iu_exception_val; +output [0:5] lq1_iu_exception; +output lq1_iu_n_flush; +output lq1_iu_np1_flush; +output lq1_iu_dacr_type; +output [0:3] lq1_iu_dacrw; +output [0:3] lq1_iu_perf_events; +output [0:`THREADS-1] lq_iu_credit_free; +output [0:`THREADS-1] sq_iu_credit_free; + +input [0:`THREADS-1] iu_lq_i0_completed; + // JK Multidimmensional port +input [0:`ITAG_SIZE_ENC-1] iu_lq_i0_completed_itag_t0; +`ifndef THREADS1 + input [0:`ITAG_SIZE_ENC-1] iu_lq_i0_completed_itag_t1; +`endif +input [0:`THREADS-1] iu_lq_i1_completed; + // JK Multidimmensional port +input [0:`ITAG_SIZE_ENC-1] iu_lq_i1_completed_itag_t0; +`ifndef THREADS1 + input [0:`ITAG_SIZE_ENC-1] iu_lq_i1_completed_itag_t1; +`endif +input [0:`THREADS-1] iu_lq_request; +input [0:1] iu_lq_cTag; +input [64-`REAL_IFAR_WIDTH:59] iu_lq_ra; +input [0:4] iu_lq_wimge; +input [0:3] iu_lq_userdef; +output [0:`THREADS-1] lq_iu_icbi_val; +output [64-`REAL_IFAR_WIDTH:57] lq_iu_icbi_addr; +input [0:`THREADS-1] iu_lq_icbi_complete; +output lq_iu_ici_val; + +//-------------------------------------------------------------- +// Interface with XU DERAT +//-------------------------------------------------------------- +input xu_lq_act; +input [0:`THREADS-1] xu_lq_val; +input xu_lq_is_eratre; +input xu_lq_is_eratwe; +input xu_lq_is_eratsx; +input xu_lq_is_eratilx; +input [0:1] xu_lq_ws; +input [0:4] xu_lq_ra_entry; +input [64-(2**`GPR_WIDTH_ENC):63] xu_lq_rs_data; +input xu_lq_hold_req; +output [64-(2**`GPR_WIDTH_ENC):63] lq_xu_ex5_data; +output lq_xu_ord_par_err; +output lq_xu_ord_read_done; +output lq_xu_ord_write_done; + +//-------------------------------------------------------------- +// Doorbell Interface with XU +//-------------------------------------------------------------- +output lq_xu_dbell_val; +output [0:4] lq_xu_dbell_type; +output lq_xu_dbell_brdcast; +output lq_xu_dbell_lpid_match; +output [50:63] lq_xu_dbell_pirtag; + +//-------------------------------------------------------------- +// Interface with RV +//-------------------------------------------------------------- +input [0:`THREADS-1] rv_lq_rv1_i0_vld; +input rv_lq_rv1_i0_ucode_preissue; +input rv_lq_rv1_i0_2ucode; +input [0:`UCODE_ENTRIES_ENC-1] rv_lq_rv1_i0_ucode_cnt; +input [0:2] rv_lq_rv1_i0_s3_t; +input rv_lq_rv1_i0_isLoad; +input rv_lq_rv1_i0_isStore; +input [0:`ITAG_SIZE_ENC-1] rv_lq_rv1_i0_itag; +input rv_lq_rv1_i0_rte_lq; +input rv_lq_rv1_i0_rte_sq; +input [61-`PF_IFAR_WIDTH+1:61] rv_lq_rv1_i0_ifar; +input [0:`THREADS-1] rv_lq_rv1_i1_vld; +input rv_lq_rv1_i1_ucode_preissue; +input rv_lq_rv1_i1_2ucode; +input [0:`UCODE_ENTRIES_ENC-1] rv_lq_rv1_i1_ucode_cnt; +input [0:2] rv_lq_rv1_i1_s3_t; +input rv_lq_rv1_i1_isLoad; +input rv_lq_rv1_i1_isStore; +input [0:`ITAG_SIZE_ENC-1] rv_lq_rv1_i1_itag; +input rv_lq_rv1_i1_rte_lq; +input rv_lq_rv1_i1_rte_sq; +input [61-`PF_IFAR_WIDTH+1:61] rv_lq_rv1_i1_ifar; + +input [0:`THREADS-1] rv_lq_rvs_empty; +input [0:`THREADS-1] rv_lq_vld; +input rv_lq_isLoad; +input [0:`ITAG_SIZE_ENC-1] rv_lq_ex0_itag; +input [0:31] rv_lq_ex0_instr; +input [0:1] rv_lq_ex0_ucode; +input [0:`UCODE_ENTRIES_ENC-1] rv_lq_ex0_ucode_cnt; +input rv_lq_ex0_t1_v; +input [0:`GPR_POOL_ENC-1] rv_lq_ex0_t1_p; +input [0:`GPR_POOL_ENC-1] rv_lq_ex0_t3_p; +input rv_lq_ex0_s1_v; +input rv_lq_ex0_s2_v; + +output [0:`THREADS-1] lq_rv_itag0_vld; +output [0:`ITAG_SIZE_ENC-1] lq_rv_itag0; +output lq_rv_itag0_abort; +output lq_rv_ex2_s1_abort; +output lq_rv_ex2_s2_abort; +output lq_rv_hold_all; +output [0:`THREADS-1] lq_rv_itag1_vld; +output [0:`ITAG_SIZE_ENC-1] lq_rv_itag1; +output lq_rv_itag1_restart; +output lq_rv_itag1_abort; +output lq_rv_itag1_hold; +output lq_rv_itag1_cord; +output [0:`THREADS-1] lq_rv_itag2_vld; +output [0:`ITAG_SIZE_ENC-1] lq_rv_itag2; +output [0:`THREADS-1] lq_rv_clr_hold; + +//------------------------------------------------------------------- +// Interface with Bypass Controller +//------------------------------------------------------------------- +input [2:12] rv_lq_ex0_s1_xu0_sel; +input [2:12] rv_lq_ex0_s2_xu0_sel; +input [2:7] rv_lq_ex0_s1_xu1_sel; +input [2:7] rv_lq_ex0_s2_xu1_sel; +input [4:8] rv_lq_ex0_s1_lq_sel; +input [4:8] rv_lq_ex0_s2_lq_sel; +input [2:3] rv_lq_ex0_s1_rel_sel; +input [2:3] rv_lq_ex0_s2_rel_sel; + +//-------------------------------------------------------------- +// Interface with Regfiles +//-------------------------------------------------------------- +input [0:`THREADS-1] xu_lq_xer_cp_rd; +input [64-(2**`GPR_WIDTH_ENC):63] rv_lq_gpr_ex1_r0d; +input [64-(2**`GPR_WIDTH_ENC):63] rv_lq_gpr_ex1_r1d; +output lq_rv_gpr_ex6_we; +output [0:`GPR_POOL_ENC+`THREAD_POOL_ENC-1] lq_rv_gpr_ex6_wa; +output [64-(2**`GPR_WIDTH_ENC):64+(((2**`GPR_WIDTH_ENC)-1)/8)] lq_rv_gpr_ex6_wd; +output lq_xu_gpr_ex5_we; +output [0:`AXU_SPARE_ENC+`GPR_POOL_ENC+`THREAD_POOL_ENC-1] lq_xu_gpr_ex5_wa; +output lq_rv_gpr_rel_we; +output lq_xu_gpr_rel_we; +output lq_xu_axu_rel_we; +output lq_xu_axu_rel_le; +output [0:`GPR_POOL_ENC+`THREAD_POOL_ENC-1] lq_rv_gpr_rel_wa; +output [0:`AXU_SPARE_ENC+`GPR_POOL_ENC+`THREAD_POOL_ENC-1] lq_xu_gpr_rel_wa; +output [64-(2**`GPR_WIDTH_ENC):64+(((2**`GPR_WIDTH_ENC)-1)/8)] lq_rv_gpr_rel_wd; +output [(128-`STQ_DATA_SIZE):128+((`STQ_DATA_SIZE-1)/8)] lq_xu_gpr_rel_wd; +output lq_xu_cr_l2_we; +output [0:`CR_POOL_ENC+`THREAD_POOL_ENC-1] lq_xu_cr_l2_wa; +output [0:`CR_WIDTH-1] lq_xu_cr_l2_wd; +output lq_xu_cr_ex5_we; +output [0:`CR_POOL_ENC+`THREAD_POOL_ENC-1] lq_xu_cr_ex5_wa; +output lq_xu_ex5_abort; + +//------------------------------------------------------------------- +// Interface with XU0 +//------------------------------------------------------------------- +input xu0_lq_ex3_act; +input xu0_lq_ex3_abort; +input [64-(2**`GPR_WIDTH_ENC):63] xu0_lq_ex3_rt; +input [64-(2**`GPR_WIDTH_ENC):63] xu0_lq_ex4_rt; +input xu0_lq_ex6_act; +input [64-(2**`GPR_WIDTH_ENC):63] xu0_lq_ex6_rt; +output lq_xu_ex5_act; +output [0:`CR_WIDTH-1] lq_xu_ex5_cr; +output [(128-`STQ_DATA_SIZE):127] lq_xu_ex5_rt; + +//------------------------------------------------------------------- +// Interface with XU1 +//------------------------------------------------------------------- +input xu1_lq_ex3_act; +input xu1_lq_ex3_abort; +input [64-(2**`GPR_WIDTH_ENC):63] xu1_lq_ex3_rt; +input [0:`THREADS-1] xu1_lq_ex2_stq_val; +input [0:`ITAG_SIZE_ENC-1] xu1_lq_ex2_stq_itag; +input [1:4] xu1_lq_ex2_stq_size; +input [(64-(2**`GPR_WIDTH_ENC))/8:7] xu1_lq_ex2_stq_dvc1_cmp; +input [(64-(2**`GPR_WIDTH_ENC))/8:7] xu1_lq_ex2_stq_dvc2_cmp; +input xu1_lq_ex3_illeg_lswx; +input xu1_lq_ex3_strg_noop; + +//------------------------------------------------------------------- +// Interface with AXU PassThru with XU +//------------------------------------------------------------------- +input [0:`THREADS-1] xu_lq_axu_ex_stq_val; +input [0:`ITAG_SIZE_ENC-1] xu_lq_axu_ex_stq_itag; +input [(128-`STQ_DATA_SIZE):127] xu_lq_axu_exp1_stq_data; +output [59:63] lq_xu_axu_ex4_addr; +output lq_xu_axu_ex5_we; +output lq_xu_axu_ex5_le; + +//-------------------------------------------------------------- +// Interface with MMU +//-------------------------------------------------------------- +input [0:`THREADS-1] mm_lq_lsu_req; +input [0:1] mm_lq_lsu_ttype; +input [0:4] mm_lq_lsu_wimge; +input [0:3] mm_lq_lsu_u; +input [64-`REAL_IFAR_WIDTH:63] mm_lq_lsu_addr; +input [0:7] mm_lq_lsu_lpid; +input mm_lq_lsu_gs; +input mm_lq_lsu_ind; +input mm_lq_lsu_lbit; +input [0:7] mm_lq_lsu_lpidr; +output lq_mm_lsu_token; +input mm_lq_hold_req; +input mm_lq_hold_done; + // JK Multidimmensional port +input [0:13] mm_lq_pid_t0; +input [0:19] mm_lq_mmucr0_t0; +`ifndef THREADS1 + input [0:13] mm_lq_pid_t1; + input [0:19] mm_lq_mmucr0_t1; +`endif + +input [0:9] mm_lq_mmucr1; +input [0:4] mm_lq_rel_val; +input [0:131] mm_lq_rel_data; +input [0:`EMQ_ENTRIES-1] mm_lq_rel_emq; +input [0:`ITAG_SIZE_ENC-1] mm_lq_itag; +input [0:`THREADS-1] mm_lq_tlb_miss; // Request got a TLB Miss +input [0:`THREADS-1] mm_lq_tlb_inelig; // Request got a TLB Ineligible +input [0:`THREADS-1] mm_lq_pt_fault; // Request got a PT Fault +input [0:`THREADS-1] mm_lq_lrat_miss; // Request got an LRAT Miss +input [0:`THREADS-1] mm_lq_tlb_multihit; // Request got a TLB Multihit Error +input [0:`THREADS-1] mm_lq_tlb_par_err; // Request got a TLB Parity Error +input [0:`THREADS-1] mm_lq_lru_par_err; // Request got a LRU Parity Error +input mm_lq_snoop_coming; +input mm_lq_snoop_val; +input [0:25] mm_lq_snoop_attr; +input [0:51] mm_lq_snoop_vpn; +output lq_mm_snoop_ack; +output lq_mm_req; +output lq_mm_req_nonspec; +output [0:`ITAG_SIZE_ENC-1] lq_mm_req_itag; +output [64-(2**`GPR_WIDTH_ENC):51] lq_mm_req_epn; +output [0:`THREADS-1] lq_mm_thdid; +output [0:`EMQ_ENTRIES-1] lq_mm_req_emq; +output [0:1] lq_mm_ttype; +output [0:3] lq_mm_state; +output [0:7] lq_mm_lpid; +output [0:13] lq_mm_tid; +output [0:`THREADS-1] lq_mm_mmucr0_we; +output [0:17] lq_mm_mmucr0; +output [0:`THREADS-1] lq_mm_mmucr1_we; +output [0:4] lq_mm_mmucr1; +output [0:`THREADS-1] lq_xu_quiesce; // Load and Store Queue is empty +output [0:`THREADS-1] lq_pc_ldq_quiesce; +output [0:`THREADS-1] lq_pc_stq_quiesce; +output [0:`THREADS-1] lq_pc_pfetch_quiesce; +output lq_mm_lmq_stq_empty; +output [0:`THREADS-1] lq_mm_perf_dtlb; + +//-------------------------------------------------------------- +// Interface with PC +//-------------------------------------------------------------- +input pc_lq_inj_dcachedir_ldp_parity; +input pc_lq_inj_dcachedir_ldp_multihit; +input pc_lq_inj_dcachedir_stp_parity; +input pc_lq_inj_dcachedir_stp_multihit; +input pc_lq_inj_dcache_parity; +input pc_lq_inj_prefetcher_parity; +input pc_lq_inj_relq_parity; +output lq_pc_err_derat_parity; +output lq_pc_err_dir_ldp_parity; +output lq_pc_err_dir_stp_parity; +output lq_pc_err_relq_parity; +output lq_pc_err_dcache_parity; +output lq_pc_err_derat_multihit; +output lq_pc_err_dir_ldp_multihit; +output lq_pc_err_dir_stp_multihit; +output lq_pc_err_invld_reld; // Reload detected without Loadmiss waiting for reload or got extra beats for cacheable request +output lq_pc_err_l2intrf_ecc; // Reload detected with an ECC error +output lq_pc_err_l2intrf_ue; // Reload detected with an uncorrectable ECC error +output lq_pc_err_l2credit_overrun; // L2 Credits were Overrun +input [0:`THREADS-1] pc_lq_ram_active; // Thread is in RAM mode +output lq_pc_ram_data_val; +output [64-(2**`GPR_WIDTH_ENC):63] lq_pc_ram_data; +output lq_pc_err_prefetcher_parity; + +//-------------------------------------------------------------- +// Debug Bus Control +//-------------------------------------------------------------- +// Pervasive Debug Control +input pc_lq_trace_bus_enable; +input [0:10] pc_lq_debug_mux1_ctrls; +input [0:10] pc_lq_debug_mux2_ctrls; +input pc_lq_instr_trace_mode; +input [0:`THREADS-1] pc_lq_instr_trace_tid; + +// Pass Thru Debug Trace Bus +input [0:31] debug_bus_in; +input [0:3] coretrace_ctrls_in; + +output [0:31] debug_bus_out; +output [0:3] coretrace_ctrls_out; + +//-------------------------------------------------------------- +// Performance Event Control +//-------------------------------------------------------------- +input pc_lq_event_bus_enable; +input [0:2] pc_lq_event_count_mode; +input [0:(4*`THREADS)-1] event_bus_in; +output [0:(4*`THREADS)-1] event_bus_out; + +//-------------------------------------------------------------- +// Interface with L2 +//-------------------------------------------------------------- +input [6:7] an_ac_coreid; +input [0:`THREADS-1] an_ac_sync_ack; +input [0:`THREADS-1] an_ac_stcx_complete; +input [0:`THREADS-1] an_ac_stcx_pass; +input an_ac_icbi_ack; +input [0:1] an_ac_icbi_ack_thread; +input an_ac_back_inv; +input [64-`REAL_IFAR_WIDTH:63] an_ac_back_inv_addr; +input an_ac_back_inv_target_bit1; +input an_ac_back_inv_target_bit3; +input an_ac_back_inv_target_bit4; +input an_ac_flh2l2_gate; +input an_ac_req_ld_pop; +input an_ac_req_st_pop; +input an_ac_req_st_gather; +input an_ac_reld_data_vld; +input [0:4] an_ac_reld_core_tag; +input [0:127] an_ac_reld_data; +input [58:59] an_ac_reld_qw; +input an_ac_reld_ecc_err; +input an_ac_reld_ecc_err_ue; +input an_ac_reld_data_coming; +input an_ac_reld_ditc; +input an_ac_reld_crit_qw; +input an_ac_reld_l1_dump; +input [0:3] an_ac_req_spare_ctrl_a1; +output ac_an_req_pwr_token; +output ac_an_req; +output [64-`REAL_IFAR_WIDTH:63] ac_an_req_ra; +output [0:5] ac_an_req_ttype; +output [0:2] ac_an_req_thread; +output ac_an_req_wimg_w; +output ac_an_req_wimg_i; +output ac_an_req_wimg_m; +output ac_an_req_wimg_g; +output [0:3] ac_an_req_user_defined; +output [0:3] ac_an_req_spare_ctrl_a0; +output [0:4] ac_an_req_ld_core_tag; +output [0:2] ac_an_req_ld_xfr_len; +output [0:31] ac_an_st_byte_enbl; +output [0:255] ac_an_st_data; +output ac_an_req_endian; +output ac_an_st_data_pwr_token; + +// Pervasive + +(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) +input [0:`NCLK_WIDTH-1] nclk; + +// Thold inputs +input pc_lq_init_reset; +input pc_lq_ccflush_dc; +input pc_lq_gptr_sl_thold_3; +input pc_lq_time_sl_thold_3; +input pc_lq_repr_sl_thold_3; +input pc_lq_bolt_sl_thold_3; +input pc_lq_abst_sl_thold_3; +input pc_lq_abst_slp_sl_thold_3; +input pc_lq_func_sl_thold_3; +input pc_lq_func_slp_sl_thold_3; +input pc_lq_cfg_sl_thold_3; +input pc_lq_cfg_slp_sl_thold_3; +input pc_lq_regf_slp_sl_thold_3; +input pc_lq_func_nsl_thold_3; +input pc_lq_func_slp_nsl_thold_3; +input pc_lq_ary_nsl_thold_3; +input pc_lq_ary_slp_nsl_thold_3; +input pc_lq_sg_3; +input pc_lq_fce_3; + +// G8T ABIST Control +input pc_lq_abist_wl64_comp_ena; +input pc_lq_abist_g8t_wenb; +input pc_lq_abist_g8t1p_renb_0; +input [0:3] pc_lq_abist_g8t_dcomp; +input pc_lq_abist_g8t_bw_1; +input pc_lq_abist_g8t_bw_0; +input [0:3] pc_lq_abist_di_0; +input [2:9] pc_lq_abist_waddr_0; + +// G6T ABIST Control +input pc_lq_abist_ena_dc; +input pc_lq_abist_raw_dc_b; +input [0:1] pc_lq_abist_g6t_bw; +input [0:3] pc_lq_abist_di_g6t_2r; +input pc_lq_abist_wl256_comp_ena; +input [0:3] pc_lq_abist_dcomp_g6t_2r; +input [1:8] pc_lq_abist_raddr_0; +input pc_lq_abist_g6t_r_wb; + +input pc_lq_bo_enable_3; +input pc_lq_bo_unload; +input pc_lq_bo_repair; +input pc_lq_bo_reset; +input pc_lq_bo_shdata; +input [0:13] pc_lq_bo_select; +output [0:13] lq_pc_bo_fail; +output [0:13] lq_pc_bo_diagout; + +// Core Level Signals +input an_ac_lbist_ary_wrt_thru_dc; +input an_ac_scan_dis_dc_b; +input an_ac_scan_diag_dc; +input an_ac_lbist_en_dc; +input an_ac_atpg_en_dc; +input an_ac_grffence_en_dc; + +// SCAN + +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + +input gptr_scan_in; + +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + +output gptr_scan_out; + +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + +input [0:5] abst_scan_in; + +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + +output [0:5] abst_scan_out; + +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + +input time_scan_in; + +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + +output time_scan_out; + +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + +input repr_scan_in; + +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + +output repr_scan_out; + +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + +input [0:6] regf_scan_in; + +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + +output [0:6] regf_scan_out; + +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + +input ccfg_scan_in; + +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + +output ccfg_scan_out; + +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + +input [0:24] func_scan_in; + +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + +output [0:24] func_scan_out; + + +parameter tiup = 1'b1; +parameter tidn = 1'b0; +parameter UPRTAGBIT = 64 - `REAL_IFAR_WIDTH; +parameter LWRTAGBIT = 63 - (`DC_SIZE - 3); +parameter TAGSIZE = LWRTAGBIT - UPRTAGBIT + 1; +parameter PAREXTCALC = 8 - (TAGSIZE % 8); +parameter PARBITS = (TAGSIZE + PAREXTCALC)/8; +parameter WAYDATASIZE = TAGSIZE + PARBITS; +parameter AXU_TARGET_ENC = `AXU_SPARE_ENC + `GPR_POOL_ENC + `THREAD_POOL_ENC; + +wire lsq_ctl_stq1_stg_act; +wire [0:`THREADS-1] lsq_ctl_oldest_tid; +wire [0:`ITAG_SIZE_ENC-1] lsq_ctl_oldest_itag; +wire lsq_ctl_rv0_back_inv; +wire [64-`REAL_IFAR_WIDTH:63-`CL_SIZE] lsq_ctl_rv1_back_inv_addr; +wire lsq_ctl_stq_release_itag_vld; +wire [0:`ITAG_SIZE_ENC-1] lsq_ctl_stq_release_itag; +wire [0:`THREADS-1] lsq_ctl_stq_release_tid; +wire lsq_ctl_ex5_ldq_restart; +wire lsq_ctl_ex5_stq_restart; +wire lsq_ctl_ex5_stq_restart_miss; +wire lsq_ctl_ex5_fwd_val; +wire [(128-`STQ_DATA_SIZE):127] lsq_ctl_ex5_fwd_data; +wire lsq_ctl_rv_hold_all; +wire lsq_ctl_rv_set_hold; +wire [0:`THREADS-1] lsq_ctl_rv_clr_hold; +wire lsq_ctl_stq1_val; +wire [0:`ITAG_SIZE_ENC-1] lsq_ctl_stq5_itag; +wire [0:AXU_TARGET_ENC-1] lsq_ctl_stq5_tgpr; +wire lsq_ctl_stq1_mftgpr_val; +wire lsq_ctl_stq1_mfdpf_val; +wire lsq_ctl_stq1_mfdpa_val; +wire [0:`THREADS-1] lsq_ctl_stq1_thrd_id; +wire [0:`THREADS-1] lsq_ctl_rel1_thrd_id; +wire lsq_ctl_stq1_resv; +wire lsq_ctl_stq1_ci; +wire lsq_ctl_stq1_axu_val; +wire lsq_ctl_stq1_epid_val; +wire lsq_ctl_stq1_store_val; +wire lsq_ctl_stq1_lock_clr; +wire lsq_ctl_stq1_watch_clr; +wire [0:1] lsq_ctl_stq1_l_fld; +wire lsq_ctl_stq1_inval; +wire lsq_ctl_stq1_dci_val; +wire [64-`REAL_IFAR_WIDTH:63-`CL_SIZE] lsq_ctl_stq1_addr; +wire lsq_ctl_stq4_xucr0_cul; +wire lsq_ctl_rel1_gpr_val; +wire [0:AXU_TARGET_ENC-1] lsq_ctl_rel1_ta_gpr; +wire lsq_ctl_rel1_upd_gpr; +wire lsq_ctl_rel1_clr_val; +wire lsq_ctl_rel1_set_val; +wire lsq_ctl_rel1_data_val; +wire lsq_ctl_rel1_back_inv; +wire [0:3] lsq_ctl_rel1_tag; +wire [0:1] lsq_ctl_rel1_classid; +wire lsq_ctl_rel1_lock_set; +wire lsq_ctl_rel1_watch_set; +wire lsq_ctl_rel2_blk_req; +wire lsq_ctl_stq2_blk_req; +wire lsq_ctl_rel2_upd_val; +wire [0:127] lsq_ctl_rel2_data; +wire lsq_ctl_rel3_l1dump_val; +wire lsq_ctl_rel3_clr_relq; +wire ctl_lsq_stq4_perr_reject; +wire [0:7] ctl_dat_stq5_way_perr_inval; +wire lsq_ctl_ex3_strg_val; +wire lsq_ctl_ex3_strg_noop; +wire lsq_ctl_ex3_illeg_lswx; +wire lsq_ctl_ex3_ct_val; +wire [0:5] lsq_ctl_ex3_be_ct; +wire [0:5] lsq_ctl_ex3_le_ct; +wire lsq_ctl_stq_cpl_ready; +wire [0:`ITAG_SIZE_ENC-1] lsq_ctl_stq_cpl_ready_itag; +wire [0:`THREADS-1] lsq_ctl_stq_cpl_ready_tid; +wire lsq_ctl_stq_n_flush; +wire lsq_ctl_stq_np1_flush; +wire lsq_ctl_stq_exception_val; +wire [0:5] lsq_ctl_stq_exception; +wire [0:3] lsq_ctl_stq_dacrw; +wire lsq_ctl_sync_in_stq; +wire lsq_ctl_sync_done; +wire ctl_lsq_stq_cpl_blk; +wire ctl_lsq_ex_pipe_full; +wire [0:`THREADS-1] ctl_lsq_ex2_streq_val; +wire [0:`ITAG_SIZE_ENC-1] ctl_lsq_ex2_itag; +wire [0:`THREADS-1] ctl_lsq_ex2_thrd_id; +wire [0:`THREADS-1] ctl_lsq_ex3_ldreq_val; +wire [0:`THREADS-1] ctl_lsq_ex3_wchkall_val; +wire ctl_lsq_ex3_pfetch_val; +wire [0:15] ctl_lsq_ex3_byte_en; +wire [58:63] ctl_lsq_ex3_p_addr; +wire [0:`THREADS-1] ctl_lsq_ex3_thrd_id; +wire ctl_lsq_ex3_algebraic; +wire [0:2] ctl_lsq_ex3_opsize; +wire ctl_lsq_ex4_ldreq_val; +wire ctl_lsq_ex4_binvreq_val; +wire ctl_lsq_ex4_streq_val; +wire ctl_lsq_ex4_othreq_val; +wire [64-`REAL_IFAR_WIDTH:57] ctl_lsq_ex4_p_addr; +wire ctl_lsq_ex4_dReq_val; +wire ctl_lsq_ex4_gath_load; +wire ctl_lsq_ex4_send_l2; +wire ctl_lsq_ex4_has_data; +wire ctl_lsq_ex4_cline_chk; +wire [0:4] ctl_lsq_ex4_wimge; +wire ctl_lsq_ex4_byte_swap; +wire ctl_lsq_ex4_is_sync; +wire ctl_lsq_ex4_all_thrd_chk; +wire ctl_lsq_ex4_is_store; +wire ctl_lsq_ex4_is_resv; +wire ctl_lsq_ex4_is_mfgpr; +wire ctl_lsq_ex4_is_icswxr; +wire ctl_lsq_ex4_is_icbi; +wire ctl_lsq_ex4_watch_clr; +wire ctl_lsq_ex4_watch_clr_all; +wire ctl_lsq_ex4_mtspr_trace; +wire ctl_lsq_ex4_is_inval_op; +wire ctl_lsq_ex4_is_cinval; +wire ctl_lsq_ex5_lock_clr; +wire ctl_lsq_ex5_lock_set; +wire ctl_lsq_ex5_watch_set; +wire [0:AXU_TARGET_ENC-1] ctl_lsq_ex5_tgpr; +wire ctl_lsq_ex5_axu_val; +wire ctl_lsq_ex5_is_epid; +wire [0:3] ctl_lsq_ex5_usr_def; +wire ctl_lsq_ex5_drop_rel; +wire ctl_lsq_ex5_flush_req; +wire ctl_lsq_ex5_flush_pfetch; +wire [0:10] ctl_lsq_ex5_cmmt_events; +wire ctl_lsq_ex5_perf_val0; +wire [0:3] ctl_lsq_ex5_perf_sel0; +wire ctl_lsq_ex5_perf_val1; +wire [0:3] ctl_lsq_ex5_perf_sel1; +wire ctl_lsq_ex5_perf_val2; +wire [0:3] ctl_lsq_ex5_perf_sel2; +wire ctl_lsq_ex5_perf_val3; +wire [0:3] ctl_lsq_ex5_perf_sel3; +wire ctl_lsq_ex5_not_touch; +wire [0:1] ctl_lsq_ex5_class_id; +wire [0:1] ctl_lsq_ex5_dvc; +wire [0:3] ctl_lsq_ex5_dacrw; +wire [0:5] ctl_lsq_ex5_ttype; +wire [0:1] ctl_lsq_ex5_l_fld; +wire ctl_lsq_ex5_load_hit; +wire [0:3] lsq_ctl_ex6_ldq_events; +wire [0:1] lsq_ctl_ex6_stq_events; +wire [0:`THREADS-1] lsq_perv_ex7_events; +wire [0:(2*`THREADS)+3] lsq_perv_ldq_events; +wire [0:(3*`THREADS)+2] lsq_perv_stq_events; +wire [0:4+`THREADS-1] lsq_perv_odq_events; +wire [0:3] ctl_lsq_ex6_ldh_dacrw; +wire [0:26] ctl_lsq_stq3_icswx_data; +wire [0:`THREADS-1] ctl_lsq_dbg_int_en; +wire [0:`THREADS-1] ctl_lsq_ldp_idle; +wire ctl_lsq_spr_lsucr0_b2b; +wire ctl_lsq_spr_lsucr0_lge; +wire [0:2] ctl_lsq_spr_lsucr0_lca; +wire [0:2] ctl_lsq_spr_lsucr0_sca; +wire ctl_lsq_spr_lsucr0_dfwd; +wire ctl_lsq_rv1_dir_rd_val; +wire ctl_lsq_spr_lsucr0_ford; +wire [64-(2**`GPR_WIDTH_ENC):63] ctl_lsq_ex4_xu1_data; +wire [0:`THREADS-1] ctl_lsq_pf_empty; + +wire [0:3] dir_arr_wr_enable; +wire [0:7] dir_arr_wr_way; +wire [64-(`DC_SIZE-3):63-`CL_SIZE] dir_arr_wr_addr; +wire [64-`REAL_IFAR_WIDTH:64-`REAL_IFAR_WIDTH+WAYDATASIZE-1] dir_arr_wr_data; +wire [0:(8*WAYDATASIZE)-1] dir_arr_rd_data1; +wire ctl_dat_ex1_data_act; +wire [52:59] ctl_dat_ex2_eff_addr; +wire [0:4] ctl_dat_ex3_opsize; +wire ctl_dat_ex3_le_mode; +wire [0:3] ctl_dat_ex3_le_ld_rotsel; +wire [0:3] ctl_dat_ex3_be_ld_rotsel; +wire ctl_dat_ex3_algebraic; +wire [0:3] ctl_dat_ex3_le_alg_rotsel; +wire [64-(2**`GPR_WIDTH_ENC):63] ctl_spr_dvc1_dbg; +wire [64-(2**`GPR_WIDTH_ENC):63] ctl_spr_dvc2_dbg; + + // JK Multidimmensional wire +wire [0:(`THREADS*8)-1] ctl_spr_dbcr2_dvc1be; +wire [0:(`THREADS*8)-1] ctl_spr_dbcr2_dvc2be; +wire [0:(`THREADS*2)-1] ctl_spr_dbcr2_dvc1m; +wire [0:(`THREADS*2)-1] ctl_spr_dbcr2_dvc2m; + +// LQ Pervasive +wire [0:18+`THREADS-1] ctl_perv_ex6_perf_events; +wire [0:6+`THREADS-1] ctl_perv_stq4_perf_events; +wire [0:(`THREADS*3)+1] ctl_perv_dir_perf_events; + +wire [0:7] ctl_dat_ex4_way_hit; +wire [0:7] dat_ctl_dcarr_perr_way; +wire [(128-`STQ_DATA_SIZE):127] dat_ctl_ex5_load_data; +wire [(128-`STQ_DATA_SIZE):127] dat_ctl_stq6_axu_data; +wire stq4_dcarr_wren; +wire [0:7] stq4_dcarr_way_en; +wire lsq_dat_stq1_stg_act; +wire lsq_dat_stq1_val; +wire lsq_dat_stq1_mftgpr_val; +wire lsq_dat_stq1_store_val; +wire [0:15] lsq_dat_stq1_byte_en; +wire [0:2] lsq_dat_stq1_op_size; +wire lsq_dat_stq1_le_mode; +wire [52:63] lsq_dat_stq1_addr; +wire lsq_dat_stq2_blk_req; +wire [0:143] lsq_dat_stq2_store_data; +wire lsq_dat_rel1_data_val; +wire [57:59] lsq_dat_rel1_qw; +wire [0:127] dat_lsq_stq4_128data; +wire [0:`THREADS-1] odq_pf_report_tid; +wire [0:`ITAG_SIZE_ENC-1] odq_pf_report_itag; +wire odq_pf_resolved; + +wire bo_enable_2; +wire sg_2; +wire func_sl_thold_2; +wire func_nsl_thold_2; +wire func_slp_sl_thold_2; +wire func_slp_nsl_thold_2; +wire ary_nsl_thold_2; +wire ary_slp_nsl_thold_2; +wire time_sl_thold_2; +wire abst_sl_thold_2; +wire abst_slp_sl_thold_2; +wire repr_sl_thold_2; +wire bolt_sl_thold_2; +wire cfg_sl_thold_2; +wire cfg_slp_sl_thold_2; +wire regf_slp_sl_thold_2; +wire fce_2; +wire clkoff_dc_b; +wire d_mode_dc; +wire [0:9] delay_lclkr_dc; +wire [0:9] mpw1_dc_b; +wire mpw2_dc_b; +wire g6t_clkoff_dc_b; +wire g6t_d_mode_dc; +wire [0:4] g6t_delay_lclkr_dc; +wire [0:4] g6t_mpw1_dc_b; +wire g6t_mpw2_dc_b; +wire g8t_clkoff_dc_b; +wire g8t_d_mode_dc; +wire [0:4] g8t_delay_lclkr_dc; +wire [0:4] g8t_mpw1_dc_b; +wire g8t_mpw2_dc_b; +wire cam_clkoff_dc_b; +wire cam_d_mode_dc; +wire [0:4] cam_delay_lclkr_dc; +wire cam_act_dis_dc; +wire [0:4] cam_mpw1_dc_b; +wire cam_mpw2_dc_b; +wire ctl_time_scan_out; +wire dat_time_scan_out; +wire ctl_repr_scan_out; +wire dat_repr_scan_out; + +wire [0:(`THREADS*`ITAG_SIZE_ENC)-1] iu_lq_cp_next_itag; +wire [0:(`THREADS*`ITAG_SIZE_ENC)-1] iu_lq_i0_completed_itag; +wire [0:(`THREADS*`ITAG_SIZE_ENC)-1] iu_lq_i1_completed_itag; +wire [0:(`THREADS*14)-1] mm_lq_pid; +wire [0:(`THREADS*20)-1] mm_lq_mmucr0; +wire [18:24] lsq_func_scan_out; +wire perv_func_scan_in; +wire perv_func_scan_out; +wire [0:23] ctl_perv_spr_lesr1; +wire [0:23] ctl_perv_spr_lesr2; +wire [0:31] lq_debug_bus0; +wire vdd; +wire gnd; + +`ifdef THREADS1 + assign iu_lq_cp_next_itag = iu_lq_cp_next_itag_t0; + assign iu_lq_i0_completed_itag = iu_lq_i0_completed_itag_t0; + assign iu_lq_i1_completed_itag = iu_lq_i1_completed_itag_t0; + assign mm_lq_pid = mm_lq_pid_t0; + assign mm_lq_mmucr0 = mm_lq_mmucr0_t0; +`endif +`ifndef THREADS1 + assign iu_lq_cp_next_itag = {iu_lq_cp_next_itag_t0, iu_lq_cp_next_itag_t1}; + assign iu_lq_i0_completed_itag = {iu_lq_i0_completed_itag_t0, iu_lq_i0_completed_itag_t1}; + assign iu_lq_i1_completed_itag = {iu_lq_i1_completed_itag_t0, iu_lq_i1_completed_itag_t1}; + assign mm_lq_pid = {mm_lq_pid_t0, mm_lq_pid_t1}; + assign mm_lq_mmucr0 = {mm_lq_mmucr0_t0, mm_lq_mmucr0_t1}; +`endif + +assign vdd = 1'b1; +//assign vcs = 1'b1; +assign gnd = 1'b0; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// LQ CONTROL +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +// Order Queue Size +lq_ctl #(.XU0_PIPE_START(XU0_PIPE_START), .XU0_PIPE_END(XU0_PIPE_END), .XU1_PIPE_START(XU1_PIPE_START), .XU1_PIPE_END(XU1_PIPE_END), .WAYDATASIZE(WAYDATASIZE)) ctl( + + //-------------------------------------------------------------- + // SPR Interface + //-------------------------------------------------------------- + .xu_lq_spr_ccr2_en_trace(xu_lq_spr_ccr2_en_trace), + .xu_lq_spr_ccr2_en_pc(xu_lq_spr_ccr2_en_pc), + .xu_lq_spr_ccr2_en_ditc(xu_lq_spr_ccr2_en_ditc), + .xu_lq_spr_ccr2_en_icswx(xu_lq_spr_ccr2_en_icswx), + .xu_lq_spr_ccr2_dfrat(xu_lq_spr_ccr2_dfrat), + .xu_lq_spr_ccr2_dfratsc(xu_lq_spr_ccr2_dfratsc), + .xu_lq_spr_ccr2_ap(xu_lq_spr_ccr2_ap), + .xu_lq_spr_ccr2_ucode_dis(xu_lq_spr_ccr2_ucode_dis), + .xu_lq_spr_ccr2_notlb(xu_lq_spr_ccr2_notlb), + .xu_lq_spr_xucr0_clkg_ctl(xu_lq_spr_xucr0_clkg_ctl), + .xu_lq_spr_xucr0_wlk(xu_lq_spr_xucr0_wlk), + .xu_lq_spr_xucr0_mbar_ack(xu_lq_spr_xucr0_mbar_ack), + .xu_lq_spr_xucr0_tlbsync(xu_lq_spr_xucr0_tlbsync), + .xu_lq_spr_xucr0_dcdis(xu_lq_spr_xucr0_dcdis), + .xu_lq_spr_xucr0_aflsta(xu_lq_spr_xucr0_aflsta), + .xu_lq_spr_xucr0_flsta(xu_lq_spr_xucr0_flsta), + .xu_lq_spr_xucr0_clfc(xu_lq_spr_xucr0_clfc), + .xu_lq_spr_xucr0_cls(xu_lq_spr_xucr0_cls), + .xu_lq_spr_xucr0_trace_um(xu_lq_spr_xucr0_trace_um), + .xu_lq_spr_xucr0_mddp(xu_lq_spr_xucr0_mddp), + .xu_lq_spr_xucr0_mdcp(xu_lq_spr_xucr0_mdcp), + .xu_lq_spr_xucr4_mmu_mchk(xu_lq_spr_xucr4_mmu_mchk), + .xu_lq_spr_xucr4_mddmh(xu_lq_spr_xucr4_mddmh), + .xu_lq_spr_msr_cm(xu_lq_spr_msr_cm), + .xu_lq_spr_msr_fp(xu_lq_spr_msr_fp), + .xu_lq_spr_msr_spv(xu_lq_spr_msr_spv), + .xu_lq_spr_msr_gs(xu_lq_spr_msr_gs), + .xu_lq_spr_msr_pr(xu_lq_spr_msr_pr), + .xu_lq_spr_msr_ds(xu_lq_spr_msr_ds), + .xu_lq_spr_msr_de(xu_lq_spr_msr_de), + .xu_lq_spr_msr_ucle(xu_lq_spr_msr_ucle), + .xu_lq_spr_msrp_uclep(xu_lq_spr_msrp_uclep), + .xu_lq_spr_dbcr0_dac1(xu_lq_spr_dbcr0_dac1), + .xu_lq_spr_dbcr0_dac2(xu_lq_spr_dbcr0_dac2), + .xu_lq_spr_dbcr0_dac3(xu_lq_spr_dbcr0_dac3), + .xu_lq_spr_dbcr0_dac4(xu_lq_spr_dbcr0_dac4), + .xu_lq_spr_dbcr0_idm(xu_lq_spr_dbcr0_idm), + .xu_lq_spr_epcr_duvd(xu_lq_spr_epcr_duvd), + .lq_xu_spr_xucr0_cul(lq_xu_spr_xucr0_cul), + .lq_xu_spr_xucr0_cslc_xuop(lq_xu_spr_xucr0_cslc_xuop), + .lq_xu_spr_xucr0_cslc_binv(lq_xu_spr_xucr0_cslc_binv), + .lq_xu_spr_xucr0_clo(lq_xu_spr_xucr0_clo), + .lq_iu_spr_dbcr3_ivc(lq_iu_spr_dbcr3_ivc), + .slowspr_val_in(slowspr_val_in), + .slowspr_rw_in(slowspr_rw_in), + .slowspr_etid_in(slowspr_etid_in), + .slowspr_addr_in(slowspr_addr_in), + .slowspr_data_in(slowspr_data_in), + .slowspr_done_in(slowspr_done_in), + .slowspr_val_out(slowspr_val_out), + .slowspr_rw_out(slowspr_rw_out), + .slowspr_etid_out(slowspr_etid_out), + .slowspr_addr_out(slowspr_addr_out), + .slowspr_data_out(slowspr_data_out), + .slowspr_done_out(slowspr_done_out), + + //-------------------------------------------------------------- + // Interface with IU + //-------------------------------------------------------------- + .iu_lq_cp_flush(iu_lq_cp_flush), + .iu_lq_recirc_val(iu_lq_recirc_val), + .iu_lq_cp_next_itag(iu_lq_cp_next_itag), + .iu_lq_isync(iu_lq_isync), + .iu_lq_csync(iu_lq_csync), + .lq0_iu_execute_vld(lq0_iu_execute_vld), + .lq0_iu_recirc_val(lq0_iu_recirc_val), + .lq0_iu_itag(lq0_iu_itag), + .lq0_iu_flush2ucode(lq0_iu_flush2ucode), + .lq0_iu_flush2ucode_type(lq0_iu_flush2ucode_type), + .lq0_iu_exception_val(lq0_iu_exception_val), + .lq0_iu_exception(lq0_iu_exception), + .lq0_iu_dear_val(lq0_iu_dear_val), + .lq0_iu_n_flush(lq0_iu_n_flush), + .lq0_iu_np1_flush(lq0_iu_np1_flush), + .lq0_iu_dacr_type(lq0_iu_dacr_type), + .lq0_iu_dacrw(lq0_iu_dacrw), + .lq0_iu_instr(lq0_iu_instr), + .lq0_iu_eff_addr(lq0_iu_eff_addr), + + // IU interface to RV for pfetch predictor table0 + // port 0 + .rv_lq_rv1_i0_vld(rv_lq_rv1_i0_vld), + .rv_lq_rv1_i0_ucode_preissue(rv_lq_rv1_i0_ucode_preissue), + .rv_lq_rv1_i0_2ucode(rv_lq_rv1_i0_2ucode), + .rv_lq_rv1_i0_ucode_cnt(rv_lq_rv1_i0_ucode_cnt), + .rv_lq_rv1_i0_isLoad(rv_lq_rv1_i0_isLoad), + .rv_lq_rv1_i0_itag(rv_lq_rv1_i0_itag), + .rv_lq_rv1_i0_rte_lq(rv_lq_rv1_i0_rte_lq), + .rv_lq_rv1_i0_ifar(rv_lq_rv1_i0_ifar), + + // port 1 + .rv_lq_rv1_i1_vld(rv_lq_rv1_i1_vld), + .rv_lq_rv1_i1_ucode_preissue(rv_lq_rv1_i1_ucode_preissue), + .rv_lq_rv1_i1_2ucode(rv_lq_rv1_i1_2ucode), + .rv_lq_rv1_i1_ucode_cnt(rv_lq_rv1_i1_ucode_cnt), + .rv_lq_rv1_i1_isLoad(rv_lq_rv1_i1_isLoad), + .rv_lq_rv1_i1_itag(rv_lq_rv1_i1_itag), + .rv_lq_rv1_i1_rte_lq(rv_lq_rv1_i1_rte_lq), + .rv_lq_rv1_i1_ifar(rv_lq_rv1_i1_ifar), + + // release itag to pfetch + .odq_pf_report_tid(odq_pf_report_tid), + .odq_pf_report_itag(odq_pf_report_itag), + .odq_pf_resolved(odq_pf_resolved), + + //-------------------------------------------------------------- + // Interface with XU DERAT + //-------------------------------------------------------------- + .xu_lq_act(xu_lq_act), + .xu_lq_val(xu_lq_val), + .xu_lq_is_eratre(xu_lq_is_eratre), + .xu_lq_is_eratwe(xu_lq_is_eratwe), + .xu_lq_is_eratsx(xu_lq_is_eratsx), + .xu_lq_is_eratilx(xu_lq_is_eratilx), + .xu_lq_ws(xu_lq_ws), + .xu_lq_ra_entry(xu_lq_ra_entry), + .xu_lq_rs_data(xu_lq_rs_data), + .xu_lq_hold_req(xu_lq_hold_req), + .lq_xu_ex5_data(lq_xu_ex5_data), + .lq_xu_ord_par_err(lq_xu_ord_par_err), + .lq_xu_ord_read_done(lq_xu_ord_read_done), + .lq_xu_ord_write_done(lq_xu_ord_write_done), + + //-------------------------------------------------------------- + // Interface with RV + //-------------------------------------------------------------- + .rv_lq_vld(rv_lq_vld), + .rv_lq_ex0_itag(rv_lq_ex0_itag), + .rv_lq_ex0_instr(rv_lq_ex0_instr), + .rv_lq_ex0_ucode(rv_lq_ex0_ucode), + .rv_lq_ex0_ucode_cnt(rv_lq_ex0_ucode_cnt), + .rv_lq_ex0_t1_v(rv_lq_ex0_t1_v), + .rv_lq_ex0_t1_p(rv_lq_ex0_t1_p), + .rv_lq_ex0_t3_p(rv_lq_ex0_t3_p), + .rv_lq_ex0_s1_v(rv_lq_ex0_s1_v), + .rv_lq_ex0_s2_v(rv_lq_ex0_s2_v), + + .lq_rv_itag0(lq_rv_itag0), + .lq_rv_itag0_vld(lq_rv_itag0_vld), + .lq_rv_itag0_abort(lq_rv_itag0_abort), + .lq_rv_ex2_s1_abort(lq_rv_ex2_s1_abort), + .lq_rv_ex2_s2_abort(lq_rv_ex2_s2_abort), + .lq_rv_hold_all(lq_rv_hold_all), + .lq_rv_itag1_vld(lq_rv_itag1_vld), + .lq_rv_itag1(lq_rv_itag1), + .lq_rv_itag1_restart(lq_rv_itag1_restart), + .lq_rv_itag1_abort(lq_rv_itag1_abort), + .lq_rv_itag1_hold(lq_rv_itag1_hold), + .lq_rv_itag1_cord(lq_rv_itag1_cord), + .lq_rv_clr_hold(lq_rv_clr_hold), + + //------------------------------------------------------------------- + // Interface with Bypass Controller + //------------------------------------------------------------------- + .rv_lq_ex0_s1_xu0_sel(rv_lq_ex0_s1_xu0_sel), + .rv_lq_ex0_s2_xu0_sel(rv_lq_ex0_s2_xu0_sel), + .rv_lq_ex0_s1_xu1_sel(rv_lq_ex0_s1_xu1_sel), + .rv_lq_ex0_s2_xu1_sel(rv_lq_ex0_s2_xu1_sel), + .rv_lq_ex0_s1_lq_sel(rv_lq_ex0_s1_lq_sel), + .rv_lq_ex0_s2_lq_sel(rv_lq_ex0_s2_lq_sel), + .rv_lq_ex0_s1_rel_sel(rv_lq_ex0_s1_rel_sel), + .rv_lq_ex0_s2_rel_sel(rv_lq_ex0_s2_rel_sel), + + //-------------------------------------------------------------- + // Interface with Regfiles + //-------------------------------------------------------------- + .xu_lq_xer_cp_rd(xu_lq_xer_cp_rd), + .rv_lq_gpr_ex1_r0d(rv_lq_gpr_ex1_r0d), + .rv_lq_gpr_ex1_r1d(rv_lq_gpr_ex1_r1d), + .lq_rv_gpr_ex6_we(lq_rv_gpr_ex6_we), + .lq_rv_gpr_ex6_wa(lq_rv_gpr_ex6_wa), + .lq_rv_gpr_ex6_wd(lq_rv_gpr_ex6_wd), + .lq_xu_gpr_ex5_we(lq_xu_gpr_ex5_we), + .lq_xu_gpr_ex5_wa(lq_xu_gpr_ex5_wa), + .lq_rv_gpr_rel_we(lq_rv_gpr_rel_we), + .lq_xu_gpr_rel_we(lq_xu_gpr_rel_we), + .lq_xu_axu_rel_we(lq_xu_axu_rel_we), + .lq_rv_gpr_rel_wa(lq_rv_gpr_rel_wa), + .lq_xu_gpr_rel_wa(lq_xu_gpr_rel_wa), + .lq_rv_gpr_rel_wd(lq_rv_gpr_rel_wd), + .lq_xu_gpr_rel_wd(lq_xu_gpr_rel_wd), + .lq_xu_cr_ex5_we(lq_xu_cr_ex5_we), + .lq_xu_cr_ex5_wa(lq_xu_cr_ex5_wa), + + //------------------------------------------------------------------- + // Interface with XU0 + //------------------------------------------------------------------- + .xu0_lq_ex3_act(xu0_lq_ex3_act), + .xu0_lq_ex3_abort(xu0_lq_ex3_abort), + .xu0_lq_ex3_rt(xu0_lq_ex3_rt), + .xu0_lq_ex4_rt(xu0_lq_ex4_rt), + .xu0_lq_ex6_act(xu0_lq_ex6_act), + .xu0_lq_ex6_rt(xu0_lq_ex6_rt), + .lq_xu_ex5_act(lq_xu_ex5_act), + .lq_xu_ex5_cr(lq_xu_ex5_cr), + .lq_xu_ex5_rt(lq_xu_ex5_rt), + .lq_xu_ex5_abort(lq_xu_ex5_abort), + + //------------------------------------------------------------------- + // Interface with XU1 + //------------------------------------------------------------------- + .xu1_lq_ex3_act(xu1_lq_ex3_act), + .xu1_lq_ex3_abort(xu1_lq_ex3_abort), + .xu1_lq_ex3_rt(xu1_lq_ex3_rt), + + //------------------------------------------------------------------- + // Interface with AXU PassThru with XU + //------------------------------------------------------------------- + .lq_xu_axu_ex4_addr(lq_xu_axu_ex4_addr), + .lq_xu_axu_ex5_we(lq_xu_axu_ex5_we), + .lq_xu_axu_ex5_le(lq_xu_axu_ex5_le), + + //-------------------------------------------------------------- + // Interface with MMU + //-------------------------------------------------------------- + .mm_lq_hold_req(mm_lq_hold_req), + .mm_lq_hold_done(mm_lq_hold_done), + .mm_lq_pid(mm_lq_pid), + .mm_lq_lsu_lpidr(mm_lq_lsu_lpidr), + .mm_lq_mmucr0(mm_lq_mmucr0), + .mm_lq_mmucr1(mm_lq_mmucr1), + .mm_lq_rel_val(mm_lq_rel_val), + .mm_lq_rel_data(mm_lq_rel_data), + .mm_lq_rel_emq(mm_lq_rel_emq), + .mm_lq_itag(mm_lq_itag), + .mm_lq_tlb_miss(mm_lq_tlb_miss), + .mm_lq_tlb_inelig(mm_lq_tlb_inelig), + .mm_lq_pt_fault(mm_lq_pt_fault), + .mm_lq_lrat_miss(mm_lq_lrat_miss), + .mm_lq_tlb_multihit(mm_lq_tlb_multihit), + .mm_lq_tlb_par_err(mm_lq_tlb_par_err), + .mm_lq_lru_par_err(mm_lq_lru_par_err), + .mm_lq_snoop_coming(mm_lq_snoop_coming), + .mm_lq_snoop_val(mm_lq_snoop_val), + .mm_lq_snoop_attr(mm_lq_snoop_attr), + .mm_lq_snoop_vpn(mm_lq_snoop_vpn), + .lq_mm_snoop_ack(lq_mm_snoop_ack), + .lq_mm_req(lq_mm_req), + .lq_mm_req_nonspec(lq_mm_req_nonspec), + .lq_mm_req_itag(lq_mm_req_itag), + .lq_mm_req_epn(lq_mm_req_epn), + .lq_mm_thdid(lq_mm_thdid), + .lq_mm_req_emq(lq_mm_req_emq), + .lq_mm_ttype(lq_mm_ttype), + .lq_mm_state(lq_mm_state), + .lq_mm_lpid(lq_mm_lpid), + .lq_mm_tid(lq_mm_tid), + .lq_mm_mmucr0_we(lq_mm_mmucr0_we), + .lq_mm_mmucr0(lq_mm_mmucr0), + .lq_mm_mmucr1_we(lq_mm_mmucr1_we), + .lq_mm_mmucr1(lq_mm_mmucr1), + .lq_mm_perf_dtlb(lq_mm_perf_dtlb), + + //-------------------------------------------------------------- + // Interface with PC + //-------------------------------------------------------------- + .pc_lq_inj_dcachedir_ldp_parity(pc_lq_inj_dcachedir_ldp_parity), + .pc_lq_inj_dcachedir_ldp_multihit(pc_lq_inj_dcachedir_ldp_multihit), + .pc_lq_inj_dcachedir_stp_parity(pc_lq_inj_dcachedir_stp_parity), + .pc_lq_inj_dcachedir_stp_multihit(pc_lq_inj_dcachedir_stp_multihit), + + //-------------------------------------------------------------- + // Interface with Load/Store Queses + //-------------------------------------------------------------- + .lsq_ctl_oldest_tid(lsq_ctl_oldest_tid), + .lsq_ctl_oldest_itag(lsq_ctl_oldest_itag), + .lsq_ctl_stq1_stg_act(lsq_ctl_stq1_stg_act), + .lsq_ctl_rv0_back_inv(lsq_ctl_rv0_back_inv), + .lsq_ctl_rv1_back_inv_addr(lsq_ctl_rv1_back_inv_addr), + .lsq_ctl_stq_release_itag_vld(lsq_ctl_stq_release_itag_vld), + .lsq_ctl_stq_release_itag(lsq_ctl_stq_release_itag), + .lsq_ctl_stq_release_tid(lsq_ctl_stq_release_tid), + .lsq_ctl_ex5_ldq_restart(lsq_ctl_ex5_ldq_restart), + .lsq_ctl_ex5_stq_restart(lsq_ctl_ex5_stq_restart), + .lsq_ctl_ex5_stq_restart_miss(lsq_ctl_ex5_stq_restart_miss), + .lsq_ctl_ex5_fwd_val(lsq_ctl_ex5_fwd_val), + .lsq_ctl_ex5_fwd_data(lsq_ctl_ex5_fwd_data), + .lsq_ctl_rv_hold_all(lsq_ctl_rv_hold_all), + .lsq_ctl_rv_set_hold(lsq_ctl_rv_set_hold), + .lsq_ctl_rv_clr_hold(lsq_ctl_rv_clr_hold), + .lsq_ctl_stq1_val(lsq_ctl_stq1_val), + .lsq_ctl_stq1_mftgpr_val(lsq_ctl_stq1_mftgpr_val), + .lsq_ctl_stq1_mfdpf_val(lsq_ctl_stq1_mfdpf_val), + .lsq_ctl_stq1_mfdpa_val(lsq_ctl_stq1_mfdpa_val), + .lsq_ctl_stq2_blk_req(lsq_ctl_stq2_blk_req), + .lsq_ctl_stq5_itag(lsq_ctl_stq5_itag), + .lsq_ctl_stq5_tgpr(lsq_ctl_stq5_tgpr), + .lsq_ctl_stq1_thrd_id(lsq_ctl_stq1_thrd_id), + .lsq_ctl_rel1_thrd_id(lsq_ctl_rel1_thrd_id), + .lsq_ctl_stq1_resv(lsq_ctl_stq1_resv), + .lsq_ctl_stq1_ci(lsq_ctl_stq1_ci), + .lsq_ctl_stq1_axu_val(lsq_ctl_stq1_axu_val), + .lsq_ctl_stq1_epid_val(lsq_ctl_stq1_epid_val), + .lsq_ctl_stq1_store_val(lsq_ctl_stq1_store_val), + .lsq_ctl_stq1_lock_clr(lsq_ctl_stq1_lock_clr), + .lsq_ctl_stq1_watch_clr(lsq_ctl_stq1_watch_clr), + .lsq_ctl_stq1_l_fld(lsq_ctl_stq1_l_fld), + .lsq_ctl_stq1_inval(lsq_ctl_stq1_inval), + .lsq_ctl_stq1_dci_val(lsq_ctl_stq1_dci_val), + .lsq_ctl_stq1_addr(lsq_ctl_stq1_addr), + .lsq_ctl_stq4_xucr0_cul(lsq_ctl_stq4_xucr0_cul), + .lsq_ctl_rel1_gpr_val(lsq_ctl_rel1_gpr_val), + .lsq_ctl_rel1_ta_gpr(lsq_ctl_rel1_ta_gpr), + .lsq_ctl_rel1_upd_gpr(lsq_ctl_rel1_upd_gpr), + .lsq_ctl_rel1_clr_val(lsq_ctl_rel1_clr_val), + .lsq_ctl_rel1_set_val(lsq_ctl_rel1_set_val), + .lsq_ctl_rel1_data_val(lsq_ctl_rel1_data_val), + .lsq_ctl_rel1_back_inv(lsq_ctl_rel1_back_inv), + .lsq_ctl_rel2_blk_req(lsq_ctl_rel2_blk_req), + .lsq_ctl_rel1_tag(lsq_ctl_rel1_tag), + .lsq_ctl_rel1_classid(lsq_ctl_rel1_classid), + .lsq_ctl_rel1_lock_set(lsq_ctl_rel1_lock_set), + .lsq_ctl_rel1_watch_set(lsq_ctl_rel1_watch_set), + .lsq_ctl_rel2_upd_val(lsq_ctl_rel2_upd_val), + .lsq_ctl_rel2_data(lsq_ctl_rel2_data), + .lsq_ctl_rel3_l1dump_val(lsq_ctl_rel3_l1dump_val), + .lsq_ctl_rel3_clr_relq(lsq_ctl_rel3_clr_relq), + .ctl_lsq_stq4_perr_reject(ctl_lsq_stq4_perr_reject), + .ctl_dat_stq5_way_perr_inval(ctl_dat_stq5_way_perr_inval), + .lsq_ctl_ex3_strg_val(lsq_ctl_ex3_strg_val), + .lsq_ctl_ex3_strg_noop(lsq_ctl_ex3_strg_noop), + .lsq_ctl_ex3_illeg_lswx(lsq_ctl_ex3_illeg_lswx), + .lsq_ctl_ex3_ct_val(lsq_ctl_ex3_ct_val), + .lsq_ctl_ex3_be_ct(lsq_ctl_ex3_be_ct), + .lsq_ctl_ex3_le_ct(lsq_ctl_ex3_le_ct), + .lsq_ctl_stq_cpl_ready(lsq_ctl_stq_cpl_ready), + .lsq_ctl_stq_cpl_ready_itag(lsq_ctl_stq_cpl_ready_itag), + .lsq_ctl_stq_cpl_ready_tid(lsq_ctl_stq_cpl_ready_tid), + .lsq_ctl_stq_n_flush(lsq_ctl_stq_n_flush), + .lsq_ctl_stq_np1_flush(lsq_ctl_stq_np1_flush), + .lsq_ctl_stq_exception_val(lsq_ctl_stq_exception_val), + .lsq_ctl_stq_exception(lsq_ctl_stq_exception), + .lsq_ctl_stq_dacrw(lsq_ctl_stq_dacrw), + .lsq_ctl_sync_in_stq(lsq_ctl_sync_in_stq), + .lsq_ctl_sync_done(lsq_ctl_sync_done), + .ctl_lsq_stq_cpl_blk(ctl_lsq_stq_cpl_blk), + .ctl_lsq_ex_pipe_full(ctl_lsq_ex_pipe_full), + .ctl_lsq_ex2_streq_val(ctl_lsq_ex2_streq_val), + .ctl_lsq_ex2_itag(ctl_lsq_ex2_itag), + .ctl_lsq_ex2_thrd_id(ctl_lsq_ex2_thrd_id), + .ctl_lsq_ex3_ldreq_val(ctl_lsq_ex3_ldreq_val), + .ctl_lsq_ex3_wchkall_val(ctl_lsq_ex3_wchkall_val), + .ctl_lsq_ex3_pfetch_val(ctl_lsq_ex3_pfetch_val), + .ctl_lsq_ex3_byte_en(ctl_lsq_ex3_byte_en), + .ctl_lsq_ex3_p_addr(ctl_lsq_ex3_p_addr), + .ctl_lsq_ex3_thrd_id(ctl_lsq_ex3_thrd_id), + .ctl_lsq_ex3_algebraic(ctl_lsq_ex3_algebraic), + .ctl_lsq_ex3_opsize(ctl_lsq_ex3_opsize), + .ctl_lsq_ex4_ldreq_val(ctl_lsq_ex4_ldreq_val), + .ctl_lsq_ex4_binvreq_val(ctl_lsq_ex4_binvreq_val), + .ctl_lsq_ex4_streq_val(ctl_lsq_ex4_streq_val), + .ctl_lsq_ex4_othreq_val(ctl_lsq_ex4_othreq_val), + .ctl_lsq_ex4_p_addr(ctl_lsq_ex4_p_addr), + .ctl_lsq_ex4_dReq_val(ctl_lsq_ex4_dReq_val), + .ctl_lsq_ex4_gath_load(ctl_lsq_ex4_gath_load), + .ctl_lsq_ex4_send_l2(ctl_lsq_ex4_send_l2), + .ctl_lsq_ex4_has_data(ctl_lsq_ex4_has_data), + .ctl_lsq_ex4_cline_chk(ctl_lsq_ex4_cline_chk), + .ctl_lsq_ex4_wimge(ctl_lsq_ex4_wimge), + .ctl_lsq_ex4_byte_swap(ctl_lsq_ex4_byte_swap), + .ctl_lsq_ex4_is_sync(ctl_lsq_ex4_is_sync), + .ctl_lsq_ex4_all_thrd_chk(ctl_lsq_ex4_all_thrd_chk), + .ctl_lsq_ex4_is_store(ctl_lsq_ex4_is_store), + .ctl_lsq_ex4_is_resv(ctl_lsq_ex4_is_resv), + .ctl_lsq_ex4_is_mfgpr(ctl_lsq_ex4_is_mfgpr), + .ctl_lsq_ex4_is_icswxr(ctl_lsq_ex4_is_icswxr), + .ctl_lsq_ex4_is_icbi(ctl_lsq_ex4_is_icbi), + .ctl_lsq_ex4_watch_clr(ctl_lsq_ex4_watch_clr), + .ctl_lsq_ex4_watch_clr_all(ctl_lsq_ex4_watch_clr_all), + .ctl_lsq_ex4_mtspr_trace(ctl_lsq_ex4_mtspr_trace), + .ctl_lsq_ex4_is_inval_op(ctl_lsq_ex4_is_inval_op), + .ctl_lsq_ex4_is_cinval(ctl_lsq_ex4_is_cinval), + .ctl_lsq_ex5_lock_clr(ctl_lsq_ex5_lock_clr), + .ctl_lsq_ex5_lock_set(ctl_lsq_ex5_lock_set), + .ctl_lsq_ex5_watch_set(ctl_lsq_ex5_watch_set), + .ctl_lsq_ex5_tgpr(ctl_lsq_ex5_tgpr), + .ctl_lsq_ex5_axu_val(ctl_lsq_ex5_axu_val), + .ctl_lsq_ex5_is_epid(ctl_lsq_ex5_is_epid), + .ctl_lsq_ex5_usr_def(ctl_lsq_ex5_usr_def), + .ctl_lsq_ex5_drop_rel(ctl_lsq_ex5_drop_rel), + .ctl_lsq_ex5_flush_req(ctl_lsq_ex5_flush_req), + .ctl_lsq_ex5_flush_pfetch(ctl_lsq_ex5_flush_pfetch), + .ctl_lsq_ex5_cmmt_events(ctl_lsq_ex5_cmmt_events), + .ctl_lsq_ex5_perf_val0(ctl_lsq_ex5_perf_val0), + .ctl_lsq_ex5_perf_sel0(ctl_lsq_ex5_perf_sel0), + .ctl_lsq_ex5_perf_val1(ctl_lsq_ex5_perf_val1), + .ctl_lsq_ex5_perf_sel1(ctl_lsq_ex5_perf_sel1), + .ctl_lsq_ex5_perf_val2(ctl_lsq_ex5_perf_val2), + .ctl_lsq_ex5_perf_sel2(ctl_lsq_ex5_perf_sel2), + .ctl_lsq_ex5_perf_val3(ctl_lsq_ex5_perf_val3), + .ctl_lsq_ex5_perf_sel3(ctl_lsq_ex5_perf_sel3), + .ctl_lsq_ex5_not_touch(ctl_lsq_ex5_not_touch), + .ctl_lsq_ex5_class_id(ctl_lsq_ex5_class_id), + .ctl_lsq_ex5_dvc(ctl_lsq_ex5_dvc), + .ctl_lsq_ex5_dacrw(ctl_lsq_ex5_dacrw), + .ctl_lsq_ex5_ttype(ctl_lsq_ex5_ttype), + .ctl_lsq_ex5_l_fld(ctl_lsq_ex5_l_fld), + .ctl_lsq_ex5_load_hit(ctl_lsq_ex5_load_hit), + .lsq_ctl_ex6_ldq_events(lsq_ctl_ex6_ldq_events), + .lsq_ctl_ex6_stq_events(lsq_ctl_ex6_stq_events), + .ctl_lsq_ex6_ldh_dacrw(ctl_lsq_ex6_ldh_dacrw), + .ctl_lsq_stq3_icswx_data(ctl_lsq_stq3_icswx_data), + .ctl_lsq_dbg_int_en(ctl_lsq_dbg_int_en), + .ctl_lsq_ldp_idle(ctl_lsq_ldp_idle), + .ctl_lsq_rv1_dir_rd_val(ctl_lsq_rv1_dir_rd_val), + .ctl_lsq_spr_lsucr0_ford(ctl_lsq_spr_lsucr0_ford), + .ctl_lsq_spr_lsucr0_b2b(ctl_lsq_spr_lsucr0_b2b), + .ctl_lsq_spr_lsucr0_lge(ctl_lsq_spr_lsucr0_lge), + .ctl_lsq_spr_lsucr0_lca(ctl_lsq_spr_lsucr0_lca), + .ctl_lsq_spr_lsucr0_sca(ctl_lsq_spr_lsucr0_sca), + .ctl_lsq_spr_lsucr0_dfwd(ctl_lsq_spr_lsucr0_dfwd), + .ctl_lsq_ex4_xu1_data(ctl_lsq_ex4_xu1_data), + + .ctl_lsq_pf_empty(ctl_lsq_pf_empty), + + //-------------------------------------------------------------- + // Interface with Commit Pipe Directories + //-------------------------------------------------------------- + .dir_arr_wr_enable(dir_arr_wr_enable), + .dir_arr_wr_way(dir_arr_wr_way), + .dir_arr_wr_addr(dir_arr_wr_addr), + .dir_arr_wr_data(dir_arr_wr_data), + .dir_arr_rd_data1(dir_arr_rd_data1), + + //-------------------------------------------------------------- + // Interface with DATA + //-------------------------------------------------------------- + .ctl_dat_ex1_data_act(ctl_dat_ex1_data_act), + .ctl_dat_ex2_eff_addr(ctl_dat_ex2_eff_addr), + .ctl_dat_ex3_opsize(ctl_dat_ex3_opsize), + .ctl_dat_ex3_le_mode(ctl_dat_ex3_le_mode), + .ctl_dat_ex3_le_ld_rotsel(ctl_dat_ex3_le_ld_rotsel), + .ctl_dat_ex3_be_ld_rotsel(ctl_dat_ex3_be_ld_rotsel), + .ctl_dat_ex3_algebraic(ctl_dat_ex3_algebraic), + .ctl_dat_ex3_le_alg_rotsel(ctl_dat_ex3_le_alg_rotsel), + .ctl_dat_ex4_way_hit(ctl_dat_ex4_way_hit), + .dat_ctl_dcarr_perr_way(dat_ctl_dcarr_perr_way), + .dat_ctl_ex5_load_data(dat_ctl_ex5_load_data), + .dat_ctl_stq6_axu_data(dat_ctl_stq6_axu_data), + + .stq4_dcarr_wren(stq4_dcarr_wren), + .stq4_dcarr_way_en(stq4_dcarr_way_en), + + //-------------------------------------------------------------- + // Common Interface + //-------------------------------------------------------------- + .ctl_spr_dvc1_dbg(ctl_spr_dvc1_dbg), + .ctl_spr_dvc2_dbg(ctl_spr_dvc2_dbg), + .ctl_perv_spr_lesr1(ctl_perv_spr_lesr1), + .ctl_perv_spr_lesr2(ctl_perv_spr_lesr2), + .ctl_spr_dbcr2_dvc1be(ctl_spr_dbcr2_dvc1be), + .ctl_spr_dbcr2_dvc2be(ctl_spr_dbcr2_dvc2be), + .ctl_spr_dbcr2_dvc1m(ctl_spr_dbcr2_dvc1m), + .ctl_spr_dbcr2_dvc2m(ctl_spr_dbcr2_dvc2m), + + // LQ Pervasive + .ctl_perv_ex6_perf_events(ctl_perv_ex6_perf_events), + .ctl_perv_stq4_perf_events(ctl_perv_stq4_perf_events), + .ctl_perv_dir_perf_events(ctl_perv_dir_perf_events), + + // Error Reporting + .lq_pc_err_derat_parity(lq_pc_err_derat_parity), + .lq_pc_err_dir_ldp_parity(lq_pc_err_dir_ldp_parity), + .lq_pc_err_dir_stp_parity(lq_pc_err_dir_stp_parity), + .lq_pc_err_dcache_parity(lq_pc_err_dcache_parity), + .lq_pc_err_derat_multihit(lq_pc_err_derat_multihit), + .lq_pc_err_dir_ldp_multihit(lq_pc_err_dir_ldp_multihit), + .lq_pc_err_dir_stp_multihit(lq_pc_err_dir_stp_multihit), + .pc_lq_inj_prefetcher_parity(pc_lq_inj_prefetcher_parity), + .lq_pc_err_prefetcher_parity(lq_pc_err_prefetcher_parity), + + // Pervasive + .vcs(vdd), + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .sg_2(sg_2), + .fce_2(fce_2), + .func_sl_thold_2(func_sl_thold_2), + .func_nsl_thold_2(func_nsl_thold_2), + .func_slp_sl_thold_2(func_slp_sl_thold_2), + .func_slp_nsl_thold_2(func_slp_nsl_thold_2), + .pc_lq_init_reset(pc_lq_init_reset), + .pc_lq_ccflush_dc(pc_lq_ccflush_dc), + .clkoff_dc_b(clkoff_dc_b), + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc[5:9]), + .mpw1_dc_b(mpw1_dc_b[5:9]), + .mpw2_dc_b(mpw2_dc_b), + .g8t_clkoff_dc_b(g8t_clkoff_dc_b), + .g8t_d_mode_dc(g8t_d_mode_dc), + .g8t_delay_lclkr_dc(g8t_delay_lclkr_dc), + .g8t_mpw1_dc_b(g8t_mpw1_dc_b), + .g8t_mpw2_dc_b(g8t_mpw2_dc_b), + .cfg_slp_sl_thold_2(cfg_slp_sl_thold_2), + .cfg_sl_thold_2(cfg_sl_thold_2), + .regf_slp_sl_thold_2(regf_slp_sl_thold_2), + .abst_sl_thold_2(abst_sl_thold_2), + .abst_slp_sl_thold_2(abst_slp_sl_thold_2), + .time_sl_thold_2(time_sl_thold_2), + .ary_nsl_thold_2(ary_nsl_thold_2), + .ary_slp_nsl_thold_2(ary_slp_nsl_thold_2), + .repr_sl_thold_2(repr_sl_thold_2), + .bolt_sl_thold_2(bolt_sl_thold_2), + .bo_enable_2(bo_enable_2), + .an_ac_scan_dis_dc_b(an_ac_scan_dis_dc_b), + .an_ac_scan_diag_dc(an_ac_scan_diag_dc), + .an_ac_lbist_en_dc(an_ac_lbist_en_dc), + .an_ac_atpg_en_dc(an_ac_atpg_en_dc), + .an_ac_grffence_en_dc(an_ac_grffence_en_dc), + .an_ac_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc), + .pc_lq_abist_ena_dc(pc_lq_abist_ena_dc), + .pc_lq_abist_raw_dc_b(pc_lq_abist_raw_dc_b), + .pc_lq_bo_unload(pc_lq_bo_unload), + .pc_lq_bo_repair(pc_lq_bo_repair), + .pc_lq_bo_reset(pc_lq_bo_reset), + .pc_lq_bo_shdata(pc_lq_bo_shdata), + .pc_lq_bo_select(pc_lq_bo_select[4:7]), + .lq_pc_bo_fail(lq_pc_bo_fail[4:7]), + .lq_pc_bo_diagout(lq_pc_bo_diagout[4:7]), + + // RAM Control + .pc_lq_ram_active(pc_lq_ram_active), + .lq_pc_ram_data_val(lq_pc_ram_data_val), + .lq_pc_ram_data(lq_pc_ram_data), + + // G8T ABIST Control + .pc_lq_abist_wl64_comp_ena(pc_lq_abist_wl64_comp_ena), + .pc_lq_abist_g8t_wenb(pc_lq_abist_g8t_wenb), + .pc_lq_abist_g8t1p_renb_0(pc_lq_abist_g8t1p_renb_0), + .pc_lq_abist_g8t_dcomp(pc_lq_abist_g8t_dcomp), + .pc_lq_abist_g8t_bw_1(pc_lq_abist_g8t_bw_1), + .pc_lq_abist_g8t_bw_0(pc_lq_abist_g8t_bw_0), + .pc_lq_abist_di_0(pc_lq_abist_di_0), + .pc_lq_abist_waddr_0(pc_lq_abist_waddr_0[4:9]), + .pc_lq_abist_raddr_0(pc_lq_abist_raddr_0[3:8]), + + // D-ERAT CAM ABIST Control + .cam_clkoff_dc_b(cam_clkoff_dc_b), + .cam_d_mode_dc(cam_d_mode_dc), + .cam_act_dis_dc(cam_act_dis_dc), + .cam_delay_lclkr_dc(cam_delay_lclkr_dc), + .cam_mpw1_dc_b(cam_mpw1_dc_b), + .cam_mpw2_dc_b(cam_mpw2_dc_b), + + // SCAN Ports + .abst_scan_in(abst_scan_in[4]), + .time_scan_in(time_scan_in), + .repr_scan_in(repr_scan_in), + .func_scan_in(func_scan_in[0:10]), + .regf_scan_in(regf_scan_in), + .ccfg_scan_in(ccfg_scan_in), + .abst_scan_out(abst_scan_out[4]), + .time_scan_out(ctl_time_scan_out), + .repr_scan_out(ctl_repr_scan_out), + .func_scan_out(func_scan_out[0:10]), + .regf_scan_out(regf_scan_out), + .ccfg_scan_out(ccfg_scan_out) +); + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// DATA +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +lq_data dat( + + // Execution Pipe + .ctl_dat_ex1_data_act(ctl_dat_ex1_data_act), + .ctl_dat_ex2_eff_addr(ctl_dat_ex2_eff_addr), + .ctl_dat_ex3_opsize(ctl_dat_ex3_opsize), + .ctl_dat_ex3_le_ld_rotsel(ctl_dat_ex3_le_ld_rotsel), + .ctl_dat_ex3_be_ld_rotsel(ctl_dat_ex3_be_ld_rotsel), + .ctl_dat_ex3_algebraic(ctl_dat_ex3_algebraic), + .ctl_dat_ex3_le_alg_rotsel(ctl_dat_ex3_le_alg_rotsel), + .ctl_dat_ex3_le_mode(ctl_dat_ex3_le_mode), + .ctl_dat_ex4_way_hit(ctl_dat_ex4_way_hit), + + // Config Bits + .xu_lq_spr_xucr0_dcdis(xu_lq_spr_xucr0_dcdis), + + // RELOAD/STORE PIPE + .lsq_dat_stq1_stg_act(lsq_dat_stq1_stg_act), + .lsq_dat_stq1_val(lsq_dat_stq1_val), + .lsq_dat_stq1_mftgpr_val(lsq_dat_stq1_mftgpr_val), + .lsq_dat_stq1_store_val(lsq_dat_stq1_store_val), + .lsq_dat_stq1_byte_en(lsq_dat_stq1_byte_en), + .lsq_dat_stq1_op_size(lsq_dat_stq1_op_size), + .lsq_dat_stq1_le_mode(lsq_dat_stq1_le_mode), + .lsq_dat_stq1_addr(lsq_dat_stq1_addr), + .lsq_dat_stq2_blk_req(lsq_dat_stq2_blk_req), + .lsq_dat_stq2_store_data(lsq_dat_stq2_store_data), + .lsq_dat_rel1_data_val(lsq_dat_rel1_data_val), + .lsq_dat_rel1_qw(lsq_dat_rel1_qw), + + // L1 D$ update Enable + .stq4_dcarr_wren(stq4_dcarr_wren), + .stq4_dcarr_way_en(stq4_dcarr_way_en), + .ctl_dat_stq5_way_perr_inval(ctl_dat_stq5_way_perr_inval), + + // Execution Pipe Outputs + .dat_ctl_dcarr_perr_way(dat_ctl_dcarr_perr_way), + + //Rotated Data + .dat_ctl_ex5_load_data(dat_ctl_ex5_load_data), + .dat_ctl_stq6_axu_data(dat_ctl_stq6_axu_data), + + // Debug Data Compare + .dat_lsq_stq4_128data(dat_lsq_stq4_128data), + + // Error Inject + .pc_lq_inj_dcache_parity(pc_lq_inj_dcache_parity), + + //pervasive + .vdd(vdd), + .gnd(gnd), + .vcs(vdd), + .nclk(nclk), + .pc_lq_ccflush_dc(pc_lq_ccflush_dc), + .sg_2(sg_2), + .fce_2(fce_2), + .func_sl_thold_2(func_sl_thold_2), + .func_nsl_thold_2(func_nsl_thold_2), + .clkoff_dc_b(clkoff_dc_b), + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc[0]), + .mpw1_dc_b(mpw1_dc_b[0]), + .mpw2_dc_b(mpw2_dc_b), + .g8t_clkoff_dc_b(g8t_clkoff_dc_b), + .g8t_d_mode_dc(g8t_d_mode_dc), + .g8t_delay_lclkr_dc(g8t_delay_lclkr_dc), + .g8t_mpw1_dc_b(g8t_mpw1_dc_b), + .g8t_mpw2_dc_b(g8t_mpw2_dc_b), + .abst_sl_thold_2(abst_sl_thold_2), + .time_sl_thold_2(time_sl_thold_2), + .ary_nsl_thold_2(ary_nsl_thold_2), + .repr_sl_thold_2(repr_sl_thold_2), + .bolt_sl_thold_2(bolt_sl_thold_2), + .bo_enable_2(bo_enable_2), + .an_ac_scan_dis_dc_b(an_ac_scan_dis_dc_b), + .an_ac_scan_diag_dc(an_ac_scan_diag_dc), + + // G6T ABIST Control + .an_ac_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc), + .pc_lq_abist_ena_dc(pc_lq_abist_ena_dc), + .pc_lq_abist_raw_dc_b(pc_lq_abist_raw_dc_b), + .pc_lq_abist_wl256_comp_ena(pc_lq_abist_wl256_comp_ena), + .pc_lq_abist_g8t_wenb(pc_lq_abist_g8t_wenb), + .pc_lq_abist_g8t1p_renb_0(pc_lq_abist_g8t1p_renb_0), + .pc_lq_abist_g8t_dcomp(pc_lq_abist_g8t_dcomp), + .pc_lq_abist_g8t_bw_1(pc_lq_abist_g8t_bw_1), + .pc_lq_abist_g8t_bw_0(pc_lq_abist_g8t_bw_0), + .pc_lq_abist_di_0(pc_lq_abist_di_0), + .pc_lq_abist_waddr_0(pc_lq_abist_waddr_0), + .pc_lq_abist_raddr_0(pc_lq_abist_raddr_0), + .pc_lq_bo_unload(pc_lq_bo_unload), + .pc_lq_bo_repair(pc_lq_bo_repair), + .pc_lq_bo_reset(pc_lq_bo_reset), + .pc_lq_bo_shdata(pc_lq_bo_shdata), + .pc_lq_bo_select(pc_lq_bo_select[0:3]), + .lq_pc_bo_fail(lq_pc_bo_fail[0:3]), + .lq_pc_bo_diagout(lq_pc_bo_diagout[0:3]), + + // SCAN Ports + .abst_scan_in(abst_scan_in[0:3]), + .time_scan_in(ctl_time_scan_out), + .repr_scan_in(ctl_repr_scan_out), + .func_scan_in(func_scan_in[11:17]), + .abst_scan_out(abst_scan_out[0:3]), + .time_scan_out(dat_time_scan_out), + .repr_scan_out(dat_repr_scan_out), + .func_scan_out(func_scan_out[11:17]) +); + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// LOADMISS/STORE QUEUES +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +lq_lsq lsq( + + // IU interface to RV for instruction insertion + // port 0 + .rv_lq_rv1_i0_vld(rv_lq_rv1_i0_vld), + .rv_lq_rv1_i0_ucode_preissue(rv_lq_rv1_i0_ucode_preissue), + .rv_lq_rv1_i0_s3_t(rv_lq_rv1_i0_s3_t), + .rv_lq_rv1_i0_isLoad(rv_lq_rv1_i0_isLoad), + .rv_lq_rv1_i0_isStore(rv_lq_rv1_i0_isStore), + .rv_lq_rv1_i0_itag(rv_lq_rv1_i0_itag), + .rv_lq_rv1_i0_rte_lq(rv_lq_rv1_i0_rte_lq), + .rv_lq_rv1_i0_rte_sq(rv_lq_rv1_i0_rte_sq), + + // port 1 + .rv_lq_rv1_i1_vld(rv_lq_rv1_i1_vld), + .rv_lq_rv1_i1_ucode_preissue(rv_lq_rv1_i1_ucode_preissue), + .rv_lq_rv1_i1_s3_t(rv_lq_rv1_i1_s3_t), + .rv_lq_rv1_i1_isLoad(rv_lq_rv1_i1_isLoad), + .rv_lq_rv1_i1_isStore(rv_lq_rv1_i1_isStore), + .rv_lq_rv1_i1_itag(rv_lq_rv1_i1_itag), + .rv_lq_rv1_i1_rte_lq(rv_lq_rv1_i1_rte_lq), + .rv_lq_rv1_i1_rte_sq(rv_lq_rv1_i1_rte_sq), + + // FXU0 Data interface + .xu1_lq_ex2_stq_val(xu1_lq_ex2_stq_val), + .xu1_lq_ex2_stq_itag(xu1_lq_ex2_stq_itag), + // xu1_lq_ex2_stq_size => xu1_lq_ex2_stq_size, + .xu1_lq_ex2_stq_dvc1_cmp(xu1_lq_ex2_stq_dvc1_cmp), + .xu1_lq_ex2_stq_dvc2_cmp(xu1_lq_ex2_stq_dvc2_cmp), + .ctl_lsq_ex4_xu1_data(ctl_lsq_ex4_xu1_data), + .xu1_lq_ex3_illeg_lswx(xu1_lq_ex3_illeg_lswx), + .xu1_lq_ex3_strg_noop(xu1_lq_ex3_strg_noop), + + // AXU Data interface + .xu_lq_axu_ex_stq_val(xu_lq_axu_ex_stq_val), + .xu_lq_axu_ex_stq_itag(xu_lq_axu_ex_stq_itag), + .xu_lq_axu_exp1_stq_data(xu_lq_axu_exp1_stq_data), + + // RV1 RV Issue Valid + .rv_lq_vld(rv_lq_vld), + .rv_lq_isLoad(rv_lq_isLoad), + + // RV is empty indicator + .rv_lq_rvs_empty(rv_lq_rvs_empty), + + // SPR Directory Read Valid + .ctl_lsq_rv1_dir_rd_val(ctl_lsq_rv1_dir_rd_val), + + // Execution Pipe Outputs + .ctl_lsq_ex2_streq_val(ctl_lsq_ex2_streq_val), + .ctl_lsq_ex2_itag(ctl_lsq_ex2_itag), + .ctl_lsq_ex2_thrd_id(ctl_lsq_ex2_thrd_id), + .ctl_lsq_ex3_ldreq_val(ctl_lsq_ex3_ldreq_val), + .ctl_lsq_ex3_wchkall_val(ctl_lsq_ex3_wchkall_val), + .ctl_lsq_ex3_pfetch_val(ctl_lsq_ex3_pfetch_val), + .ctl_lsq_ex3_byte_en(ctl_lsq_ex3_byte_en), + .ctl_lsq_ex3_p_addr(ctl_lsq_ex3_p_addr), + .ctl_lsq_ex3_thrd_id(ctl_lsq_ex3_thrd_id), + .ctl_lsq_ex3_algebraic(ctl_lsq_ex3_algebraic), + .ctl_lsq_ex3_opsize(ctl_lsq_ex3_opsize), + .ctl_lsq_ex4_ldreq_val(ctl_lsq_ex4_ldreq_val), + .ctl_lsq_ex4_binvreq_val(ctl_lsq_ex4_binvreq_val), + .ctl_lsq_ex4_streq_val(ctl_lsq_ex4_streq_val), + .ctl_lsq_ex4_othreq_val(ctl_lsq_ex4_othreq_val), + .ctl_lsq_ex4_p_addr(ctl_lsq_ex4_p_addr), + .ctl_lsq_ex4_dReq_val(ctl_lsq_ex4_dReq_val), + .ctl_lsq_ex4_gath_load(ctl_lsq_ex4_gath_load), + .ctl_lsq_ex4_send_l2(ctl_lsq_ex4_send_l2), + .ctl_lsq_ex4_has_data(ctl_lsq_ex4_has_data), + .ctl_lsq_ex4_cline_chk(ctl_lsq_ex4_cline_chk), + .ctl_lsq_ex4_wimge(ctl_lsq_ex4_wimge), + .ctl_lsq_ex4_byte_swap(ctl_lsq_ex4_byte_swap), + .ctl_lsq_ex4_is_sync(ctl_lsq_ex4_is_sync), + .ctl_lsq_ex4_all_thrd_chk(ctl_lsq_ex4_all_thrd_chk), + .ctl_lsq_ex4_is_store(ctl_lsq_ex4_is_store), + .ctl_lsq_ex4_is_resv(ctl_lsq_ex4_is_resv), + .ctl_lsq_ex4_is_mfgpr(ctl_lsq_ex4_is_mfgpr), + .ctl_lsq_ex4_is_icswxr(ctl_lsq_ex4_is_icswxr), + .ctl_lsq_ex4_is_icbi(ctl_lsq_ex4_is_icbi), + .ctl_lsq_ex4_watch_clr(ctl_lsq_ex4_watch_clr), + .ctl_lsq_ex4_watch_clr_all(ctl_lsq_ex4_watch_clr_all), + .ctl_lsq_ex4_mtspr_trace(ctl_lsq_ex4_mtspr_trace), + .ctl_lsq_ex4_is_inval_op(ctl_lsq_ex4_is_inval_op), + .ctl_lsq_ex4_is_cinval(ctl_lsq_ex4_is_cinval), + .ctl_lsq_ex5_lock_clr(ctl_lsq_ex5_lock_clr), + .ctl_lsq_ex5_lock_set(ctl_lsq_ex5_lock_set), + .ctl_lsq_ex5_watch_set(ctl_lsq_ex5_watch_set), + .ctl_lsq_ex5_tgpr(ctl_lsq_ex5_tgpr), + .ctl_lsq_ex5_axu_val(ctl_lsq_ex5_axu_val), + .ctl_lsq_ex5_is_epid(ctl_lsq_ex5_is_epid), + .ctl_lsq_ex5_usr_def(ctl_lsq_ex5_usr_def), + .ctl_lsq_ex5_drop_rel(ctl_lsq_ex5_drop_rel), + .ctl_lsq_ex5_flush_req(ctl_lsq_ex5_flush_req), + .ctl_lsq_ex5_flush_pfetch(ctl_lsq_ex5_flush_pfetch), + .ctl_lsq_ex5_cmmt_events(ctl_lsq_ex5_cmmt_events), + .ctl_lsq_ex5_perf_val0(ctl_lsq_ex5_perf_val0), + .ctl_lsq_ex5_perf_sel0(ctl_lsq_ex5_perf_sel0), + .ctl_lsq_ex5_perf_val1(ctl_lsq_ex5_perf_val1), + .ctl_lsq_ex5_perf_sel1(ctl_lsq_ex5_perf_sel1), + .ctl_lsq_ex5_perf_val2(ctl_lsq_ex5_perf_val2), + .ctl_lsq_ex5_perf_sel2(ctl_lsq_ex5_perf_sel2), + .ctl_lsq_ex5_perf_val3(ctl_lsq_ex5_perf_val3), + .ctl_lsq_ex5_perf_sel3(ctl_lsq_ex5_perf_sel3), + .ctl_lsq_ex5_not_touch(ctl_lsq_ex5_not_touch), + .ctl_lsq_ex5_class_id(ctl_lsq_ex5_class_id), + .ctl_lsq_ex5_dvc(ctl_lsq_ex5_dvc), + .ctl_lsq_ex5_dacrw(ctl_lsq_ex5_dacrw), + .ctl_lsq_ex5_ttype(ctl_lsq_ex5_ttype), + .ctl_lsq_ex5_l_fld(ctl_lsq_ex5_l_fld), + .ctl_lsq_ex5_load_hit(ctl_lsq_ex5_load_hit), + .lsq_ctl_ex6_ldq_events(lsq_ctl_ex6_ldq_events), + .lsq_ctl_ex6_stq_events(lsq_ctl_ex6_stq_events), + .lsq_perv_ex7_events(lsq_perv_ex7_events), + .lsq_perv_ldq_events(lsq_perv_ldq_events), + .lsq_perv_stq_events(lsq_perv_stq_events), + .lsq_perv_odq_events(lsq_perv_odq_events), + .ctl_lsq_ex6_ldh_dacrw(ctl_lsq_ex6_ldh_dacrw), + .ctl_lsq_dbg_int_en(ctl_lsq_dbg_int_en), + .ctl_lsq_ldp_idle(ctl_lsq_ldp_idle), + + // ICSWX Data to be sent to the L2 + .ctl_lsq_stq3_icswx_data(ctl_lsq_stq3_icswx_data), + + // Interface with Local SPR's + .ctl_lsq_spr_dvc1_dbg(ctl_spr_dvc1_dbg), + .ctl_lsq_spr_dvc2_dbg(ctl_spr_dvc2_dbg), + .ctl_lsq_spr_dbcr2_dvc1m(ctl_spr_dbcr2_dvc1m), + .ctl_lsq_spr_dbcr2_dvc1be(ctl_spr_dbcr2_dvc1be), + .ctl_lsq_spr_dbcr2_dvc2m(ctl_spr_dbcr2_dvc2m), + .ctl_lsq_spr_dbcr2_dvc2be(ctl_spr_dbcr2_dvc2be), + .ctl_lsq_spr_lsucr0_b2b(ctl_lsq_spr_lsucr0_b2b), + .ctl_lsq_spr_lsucr0_lge(ctl_lsq_spr_lsucr0_lge), + .ctl_lsq_spr_lsucr0_lca(ctl_lsq_spr_lsucr0_lca), + .ctl_lsq_spr_lsucr0_sca(ctl_lsq_spr_lsucr0_sca), + .ctl_lsq_spr_lsucr0_dfwd(ctl_lsq_spr_lsucr0_dfwd), + + .ctl_lsq_pf_empty(ctl_lsq_pf_empty), + + //-------------------------------------------------------------- + // Interface with Commit Pipe Directories + //-------------------------------------------------------------- + .dir_arr_wr_enable(dir_arr_wr_enable), + .dir_arr_wr_way(dir_arr_wr_way), + .dir_arr_wr_addr(dir_arr_wr_addr), + .dir_arr_wr_data(dir_arr_wr_data), + .dir_arr_rd_data1(dir_arr_rd_data1), + + // Data Cache Config + .xu_lq_spr_xucr0_cls(xu_lq_spr_xucr0_cls), + .xu_lq_spr_xucr0_cred(xu_lq_spr_xucr0_cred), + + // ICBI ACK Enable + .iu_lq_spr_iucr0_icbi_ack(iu_lq_spr_iucr0_icbi_ack), + + // STQ4 Data for L2 write + .dat_lsq_stq4_128data(dat_lsq_stq4_128data), + + // Instruction Fetches + .iu_lq_request(iu_lq_request), + .iu_lq_cTag(iu_lq_cTag), + .iu_lq_ra(iu_lq_ra), + .iu_lq_wimge(iu_lq_wimge), + .iu_lq_userdef(iu_lq_userdef), + + // ICBI Interface to IU + .lq_iu_icbi_val(lq_iu_icbi_val), + .lq_iu_icbi_addr(lq_iu_icbi_addr), + .iu_lq_icbi_complete(iu_lq_icbi_complete), + + // ICI Interace + .lq_iu_ici_val(lq_iu_ici_val), + + // MMU instruction interface + .mm_lq_lsu_req(mm_lq_lsu_req), + .mm_lq_lsu_ttype(mm_lq_lsu_ttype), + .mm_lq_lsu_wimge(mm_lq_lsu_wimge), + .mm_lq_lsu_u(mm_lq_lsu_u), + .mm_lq_lsu_addr(mm_lq_lsu_addr), + + // TLBI_COMPLETE is address-less + .mm_lq_lsu_lpid(mm_lq_lsu_lpid), + .mm_lq_lsu_gs(mm_lq_lsu_gs), + .mm_lq_lsu_ind(mm_lq_lsu_ind), + .mm_lq_lsu_lbit(mm_lq_lsu_lbit), + .mm_lq_lsu_lpidr(mm_lq_lsu_lpidr), + .lq_mm_lsu_token(lq_mm_lsu_token), + .lq_xu_quiesce(lq_xu_quiesce), + .lq_pc_ldq_quiesce(lq_pc_ldq_quiesce), + .lq_pc_stq_quiesce(lq_pc_stq_quiesce), + .lq_pc_pfetch_quiesce(lq_pc_pfetch_quiesce), + .lq_mm_lmq_stq_empty(lq_mm_lmq_stq_empty), + + // Zap Machine + .iu_lq_cp_flush(iu_lq_cp_flush), + + // Next Itag Completion + .iu_lq_recirc_val(iu_lq_recirc_val), + .iu_lq_cp_next_itag(iu_lq_cp_next_itag), + + // Complete iTag + .iu_lq_i0_completed(iu_lq_i0_completed), + .iu_lq_i0_completed_itag(iu_lq_i0_completed_itag), + .iu_lq_i1_completed(iu_lq_i1_completed), + .iu_lq_i1_completed_itag(iu_lq_i1_completed_itag), + + // XER Read for long latency CP_NEXT ops stcx./icswx. + .xu_lq_xer_cp_rd(xu_lq_xer_cp_rd), + + // Sync Ack + .an_ac_sync_ack(an_ac_sync_ack), + + // Stcx Complete + .an_ac_stcx_complete(an_ac_stcx_complete), + .an_ac_stcx_pass(an_ac_stcx_pass), + + // ICBI ACK + .an_ac_icbi_ack(an_ac_icbi_ack), + .an_ac_icbi_ack_thread(an_ac_icbi_ack_thread), + + // Core ID + .an_ac_coreid(an_ac_coreid), + + // L2 Interface Credit Control + .an_ac_req_ld_pop(an_ac_req_ld_pop), + .an_ac_req_st_pop(an_ac_req_st_pop), + .an_ac_req_st_gather(an_ac_req_st_gather), + + // L2 Interface Reload + .an_ac_reld_data_vld(an_ac_reld_data_vld), + .an_ac_reld_core_tag(an_ac_reld_core_tag), + .an_ac_reld_qw(an_ac_reld_qw), + .an_ac_reld_data(an_ac_reld_data), + .an_ac_reld_data_coming(an_ac_reld_data_coming), + .an_ac_reld_ditc(an_ac_reld_ditc), + .an_ac_reld_crit_qw(an_ac_reld_crit_qw), + .an_ac_reld_l1_dump(an_ac_reld_l1_dump), + .an_ac_reld_ecc_err(an_ac_reld_ecc_err), + .an_ac_reld_ecc_err_ue(an_ac_reld_ecc_err_ue), + + // L2 Interface Back Invalidate + .an_ac_back_inv(an_ac_back_inv), + .an_ac_back_inv_addr(an_ac_back_inv_addr), + .an_ac_back_inv_target_bit1(an_ac_back_inv_target_bit1), + .an_ac_back_inv_target_bit3(an_ac_back_inv_target_bit3), + .an_ac_back_inv_target_bit4(an_ac_back_inv_target_bit4), + .an_ac_req_spare_ctrl_a1(an_ac_req_spare_ctrl_a1), + + // Credit Release to IU + .lq_iu_credit_free(lq_iu_credit_free), + .sq_iu_credit_free(sq_iu_credit_free), + + // Reservation Station Hold indicator + .lsq_ctl_rv_hold_all(lsq_ctl_rv_hold_all), + + // Reservation station set barrier indicator + .lsq_ctl_rv_set_hold(lsq_ctl_rv_set_hold), + .lsq_ctl_rv_clr_hold(lsq_ctl_rv_clr_hold), + + // Reload Itag Complete + .lsq_ctl_stq_release_itag_vld(lsq_ctl_stq_release_itag_vld), + .lsq_ctl_stq_release_itag(lsq_ctl_stq_release_itag), + .lsq_ctl_stq_release_tid(lsq_ctl_stq_release_tid), + + // Store Queue Completion Report + .lsq_ctl_stq_cpl_ready(lsq_ctl_stq_cpl_ready), + .lsq_ctl_stq_cpl_ready_itag(lsq_ctl_stq_cpl_ready_itag), + .lsq_ctl_stq_cpl_ready_tid(lsq_ctl_stq_cpl_ready_tid), + .lsq_ctl_stq_n_flush(lsq_ctl_stq_n_flush), + .lsq_ctl_stq_np1_flush(lsq_ctl_stq_np1_flush), + .lsq_ctl_stq_exception_val(lsq_ctl_stq_exception_val), + .lsq_ctl_stq_exception(lsq_ctl_stq_exception), + .lsq_ctl_stq_dacrw(lsq_ctl_stq_dacrw), + .ctl_lsq_stq_cpl_blk(ctl_lsq_stq_cpl_blk), + .ctl_lsq_ex_pipe_full(ctl_lsq_ex_pipe_full), + + // LOADMISS Queue RESTART indicator + .lsq_ctl_ex5_ldq_restart(lsq_ctl_ex5_ldq_restart), + + // Store Data Forward + .lsq_ctl_ex5_fwd_val(lsq_ctl_ex5_fwd_val), + .lsq_ctl_ex5_fwd_data(lsq_ctl_ex5_fwd_data), + + .lsq_ctl_sync_in_stq(lsq_ctl_sync_in_stq), + .lsq_ctl_sync_done(lsq_ctl_sync_done), + + // Store Queue RESTART indicator + .lsq_ctl_ex5_stq_restart(lsq_ctl_ex5_stq_restart), + .lsq_ctl_ex5_stq_restart_miss(lsq_ctl_ex5_stq_restart_miss), + + // Interface to completion + .lq1_iu_execute_vld(lq1_iu_execute_vld), + .lq1_iu_itag(lq1_iu_itag), + .lq1_iu_exception_val(lq1_iu_exception_val), + .lq1_iu_exception(lq1_iu_exception), + .lq1_iu_n_flush(lq1_iu_n_flush), + .lq1_iu_np1_flush(lq1_iu_np1_flush), + .lq1_iu_dacr_type(lq1_iu_dacr_type), + .lq1_iu_dacrw(lq1_iu_dacrw), + .lq1_iu_perf_events(lq1_iu_perf_events), + + // RELOAD/COMMIT Data Control + .lsq_dat_stq1_stg_act(lsq_dat_stq1_stg_act), + .lsq_dat_rel1_data_val(lsq_dat_rel1_data_val), + .lsq_dat_rel1_qw(lsq_dat_rel1_qw), + .lsq_dat_stq1_val(lsq_dat_stq1_val), + .lsq_dat_stq1_mftgpr_val(lsq_dat_stq1_mftgpr_val), + .lsq_dat_stq1_store_val(lsq_dat_stq1_store_val), + .lsq_dat_stq1_byte_en(lsq_dat_stq1_byte_en), + .lsq_dat_stq1_op_size(lsq_dat_stq1_op_size), + .lsq_dat_stq1_addr(lsq_dat_stq1_addr), + .lsq_dat_stq1_le_mode(lsq_dat_stq1_le_mode), + .lsq_dat_stq2_blk_req(lsq_dat_stq2_blk_req), + .lsq_dat_stq2_store_data(lsq_dat_stq2_store_data), + + // RELOAD/COMMIT Directory Control + .lsq_ctl_stq1_stg_act(lsq_ctl_stq1_stg_act), + .lsq_ctl_oldest_tid(lsq_ctl_oldest_tid), + .lsq_ctl_oldest_itag(lsq_ctl_oldest_itag), + .lsq_ctl_rel1_clr_val(lsq_ctl_rel1_clr_val), + .lsq_ctl_rel1_set_val(lsq_ctl_rel1_set_val), + .lsq_ctl_rel1_data_val(lsq_ctl_rel1_data_val), + .lsq_ctl_rel1_back_inv(lsq_ctl_rel1_back_inv), + .lsq_ctl_rel1_tag(lsq_ctl_rel1_tag), + .lsq_ctl_rel1_classid(lsq_ctl_rel1_classid), + .lsq_ctl_rel1_lock_set(lsq_ctl_rel1_lock_set), + .lsq_ctl_rel1_watch_set(lsq_ctl_rel1_watch_set), + .lsq_ctl_rel2_blk_req(lsq_ctl_rel2_blk_req), + .lsq_ctl_stq2_blk_req(lsq_ctl_stq2_blk_req), + .lsq_ctl_rel2_upd_val(lsq_ctl_rel2_upd_val), + .lsq_ctl_rel2_data(lsq_ctl_rel2_data), + .lsq_ctl_rel3_l1dump_val(lsq_ctl_rel3_l1dump_val), + .lsq_ctl_rel3_clr_relq(lsq_ctl_rel3_clr_relq), + .ctl_lsq_stq4_perr_reject(ctl_lsq_stq4_perr_reject), + .lsq_ctl_stq1_val(lsq_ctl_stq1_val), + .lsq_ctl_stq1_mftgpr_val(lsq_ctl_stq1_mftgpr_val), + .lsq_ctl_stq1_mfdpf_val(lsq_ctl_stq1_mfdpf_val), + .lsq_ctl_stq1_mfdpa_val(lsq_ctl_stq1_mfdpa_val), + .lsq_ctl_stq1_thrd_id(lsq_ctl_stq1_thrd_id), + .lsq_ctl_rel1_thrd_id(lsq_ctl_rel1_thrd_id), + .lsq_ctl_stq1_store_val(lsq_ctl_stq1_store_val), + .lsq_ctl_stq1_lock_clr(lsq_ctl_stq1_lock_clr), + .lsq_ctl_stq1_watch_clr(lsq_ctl_stq1_watch_clr), + .lsq_ctl_stq1_l_fld(lsq_ctl_stq1_l_fld), + .lsq_ctl_stq1_inval(lsq_ctl_stq1_inval), + .lsq_ctl_stq1_dci_val(lsq_ctl_stq1_dci_val), + .lsq_ctl_stq1_addr(lsq_ctl_stq1_addr), + .lsq_ctl_stq1_ci(lsq_ctl_stq1_ci), + .lsq_ctl_stq1_axu_val(lsq_ctl_stq1_axu_val), + .lsq_ctl_stq1_epid_val(lsq_ctl_stq1_epid_val), + .lsq_ctl_stq4_xucr0_cul(lsq_ctl_stq4_xucr0_cul), + .lsq_ctl_stq5_itag(lsq_ctl_stq5_itag), + .lsq_ctl_stq5_tgpr(lsq_ctl_stq5_tgpr), + + // RELOAD Register Control + .lsq_ctl_rel1_gpr_val(lsq_ctl_rel1_gpr_val), + .lsq_ctl_rel1_ta_gpr(lsq_ctl_rel1_ta_gpr), + .lsq_ctl_rel1_upd_gpr(lsq_ctl_rel1_upd_gpr), + .lsq_ctl_stq1_resv(lsq_ctl_stq1_resv), + + // Illegal LSWX has been determined + .lsq_ctl_ex3_strg_val(lsq_ctl_ex3_strg_val), + .lsq_ctl_ex3_strg_noop(lsq_ctl_ex3_strg_noop), + .lsq_ctl_ex3_illeg_lswx(lsq_ctl_ex3_illeg_lswx), + .lsq_ctl_ex3_ct_val(lsq_ctl_ex3_ct_val), + .lsq_ctl_ex3_be_ct(lsq_ctl_ex3_be_ct), + .lsq_ctl_ex3_le_ct(lsq_ctl_ex3_le_ct), + + // release itag to pfetch + .odq_pf_report_tid(odq_pf_report_tid), + .odq_pf_report_itag(odq_pf_report_itag), + .odq_pf_resolved(odq_pf_resolved), + + // STCX Update + .lq_xu_cr_l2_we(lq_xu_cr_l2_we), + .lq_xu_cr_l2_wa(lq_xu_cr_l2_wa), + .lq_xu_cr_l2_wd(lq_xu_cr_l2_wd), + + // PRF update for reloads + .lq_xu_axu_rel_le(lq_xu_axu_rel_le), + + // Back-Invalidate + .lsq_ctl_rv0_back_inv(lsq_ctl_rv0_back_inv), + .lsq_ctl_rv1_back_inv_addr(lsq_ctl_rv1_back_inv_addr), + + // RV Reload Release Dependent ITAGs + .lq_rv_itag2_vld(lq_rv_itag2_vld), + .lq_rv_itag2(lq_rv_itag2), + + // Doorbell Interface + .lq_xu_dbell_val(lq_xu_dbell_val), + .lq_xu_dbell_type(lq_xu_dbell_type), + .lq_xu_dbell_brdcast(lq_xu_dbell_brdcast), + .lq_xu_dbell_lpid_match(lq_xu_dbell_lpid_match), + .lq_xu_dbell_pirtag(lq_xu_dbell_pirtag), + + // L2 Interface Outputs + .ac_an_req_pwr_token(ac_an_req_pwr_token), + .ac_an_req(ac_an_req), + .ac_an_req_ra(ac_an_req_ra), + .ac_an_req_ttype(ac_an_req_ttype), + .ac_an_req_thread(ac_an_req_thread), + .ac_an_req_wimg_w(ac_an_req_wimg_w), + .ac_an_req_wimg_i(ac_an_req_wimg_i), + .ac_an_req_wimg_m(ac_an_req_wimg_m), + .ac_an_req_wimg_g(ac_an_req_wimg_g), + .ac_an_req_endian(ac_an_req_endian), + .ac_an_req_user_defined(ac_an_req_user_defined), + .ac_an_req_spare_ctrl_a0(ac_an_req_spare_ctrl_a0), + .ac_an_req_ld_core_tag(ac_an_req_ld_core_tag), + .ac_an_req_ld_xfr_len(ac_an_req_ld_xfr_len), + .ac_an_st_byte_enbl(ac_an_st_byte_enbl), + .ac_an_st_data(ac_an_st_data), + .ac_an_st_data_pwr_token(ac_an_st_data_pwr_token), + + // Interface to Pervasive Unit + .pc_lq_inj_relq_parity(pc_lq_inj_relq_parity), + .lq_pc_err_relq_parity(lq_pc_err_relq_parity), + .lq_pc_err_invld_reld(lq_pc_err_invld_reld), + .lq_pc_err_l2intrf_ecc(lq_pc_err_l2intrf_ecc), + .lq_pc_err_l2intrf_ue(lq_pc_err_l2intrf_ue), + .lq_pc_err_l2credit_overrun(lq_pc_err_l2credit_overrun), + + // Pervasive + .vcs(vdd), + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .pc_lq_ccflush_dc(pc_lq_ccflush_dc), + .sg_2(sg_2), + .fce_2(fce_2), + .func_sl_thold_2(func_sl_thold_2), + .func_nsl_thold_2(func_nsl_thold_2), + .func_slp_sl_thold_2(func_slp_sl_thold_2), + .clkoff_dc_b(clkoff_dc_b), + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc[0]), + .mpw1_dc_b(mpw1_dc_b[0]), + .mpw2_dc_b(mpw2_dc_b), + .g8t_clkoff_dc_b(g8t_clkoff_dc_b), + .g8t_d_mode_dc(g8t_d_mode_dc), + .g8t_delay_lclkr_dc(g8t_delay_lclkr_dc), + .g8t_mpw1_dc_b(g8t_mpw1_dc_b), + .g8t_mpw2_dc_b(g8t_mpw2_dc_b), + .abst_sl_thold_2(abst_sl_thold_2), + .time_sl_thold_2(time_sl_thold_2), + .ary_nsl_thold_2(ary_nsl_thold_2), + .repr_sl_thold_2(repr_sl_thold_2), + .bolt_sl_thold_2(bolt_sl_thold_2), + .bo_enable_2(bo_enable_2), + .an_ac_scan_dis_dc_b(an_ac_scan_dis_dc_b), + .an_ac_scan_diag_dc(an_ac_scan_diag_dc), + .an_ac_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc), + .pc_lq_abist_ena_dc(pc_lq_abist_ena_dc), + .pc_lq_abist_raw_dc_b(pc_lq_abist_raw_dc_b), + .pc_lq_bo_unload(pc_lq_bo_unload), + .pc_lq_bo_repair(pc_lq_bo_repair), + .pc_lq_bo_reset(pc_lq_bo_reset), + .pc_lq_bo_shdata(pc_lq_bo_shdata), + .pc_lq_bo_select(pc_lq_bo_select[8:13]), + .lq_pc_bo_fail(lq_pc_bo_fail[8:13]), + .lq_pc_bo_diagout(lq_pc_bo_diagout[8:13]), + + // G8T ABIST Control + .pc_lq_abist_wl64_comp_ena(pc_lq_abist_wl64_comp_ena), + .pc_lq_abist_g8t_wenb(pc_lq_abist_g8t_wenb), + .pc_lq_abist_g8t1p_renb_0(pc_lq_abist_g8t1p_renb_0), + .pc_lq_abist_g8t_dcomp(pc_lq_abist_g8t_dcomp), + .pc_lq_abist_g8t_bw_1(pc_lq_abist_g8t_bw_1), + .pc_lq_abist_g8t_bw_0(pc_lq_abist_g8t_bw_0), + .pc_lq_abist_di_0(pc_lq_abist_di_0), + .pc_lq_abist_waddr_0(pc_lq_abist_waddr_0[4:9]), + .pc_lq_abist_raddr_0(pc_lq_abist_raddr_0[3:8]), + + // SCAN Ports + .abst_scan_in(abst_scan_in[5]), + .time_scan_in(dat_time_scan_out), + .repr_scan_in(dat_repr_scan_out), + .func_scan_in(func_scan_in[18:24]), + .abst_scan_out(abst_scan_out[5]), + .time_scan_out(time_scan_out), + .repr_scan_out(repr_scan_out), + .func_scan_out(lsq_func_scan_out[18:24]) +); + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// LOCAL PERVASIVE +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +assign perv_func_scan_in = lsq_func_scan_out[24]; +assign lq_debug_bus0 = 32'h00000000; + +lq_perv lq_perv( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .pc_lq_trace_bus_enable(pc_lq_trace_bus_enable), + .pc_lq_debug_mux1_ctrls(pc_lq_debug_mux1_ctrls), + .pc_lq_debug_mux2_ctrls(pc_lq_debug_mux2_ctrls), + .pc_lq_instr_trace_mode(pc_lq_instr_trace_mode), + .pc_lq_instr_trace_tid(pc_lq_instr_trace_tid), + .debug_bus_in(debug_bus_in), + .coretrace_ctrls_in(coretrace_ctrls_in), + .lq_debug_bus0(lq_debug_bus0), + .debug_bus_out(debug_bus_out), + .coretrace_ctrls_out(coretrace_ctrls_out), + .pc_lq_event_bus_enable(pc_lq_event_bus_enable), + .pc_lq_event_count_mode(pc_lq_event_count_mode), + .ctl_perv_spr_lesr1(ctl_perv_spr_lesr1), + .ctl_perv_spr_lesr2(ctl_perv_spr_lesr2), + .ctl_perv_ex6_perf_events(ctl_perv_ex6_perf_events), + .ctl_perv_stq4_perf_events(ctl_perv_stq4_perf_events), + .ctl_perv_dir_perf_events(ctl_perv_dir_perf_events), + .lsq_perv_ex7_events(lsq_perv_ex7_events), + .lsq_perv_ldq_events(lsq_perv_ldq_events), + .lsq_perv_stq_events(lsq_perv_stq_events), + .lsq_perv_odq_events(lsq_perv_odq_events), + .xu_lq_spr_msr_pr(xu_lq_spr_msr_pr), + .xu_lq_spr_msr_gs(xu_lq_spr_msr_gs), + .event_bus_in(event_bus_in), + .event_bus_out(event_bus_out), + .pc_lq_sg_3(pc_lq_sg_3), + .pc_lq_func_sl_thold_3(pc_lq_func_sl_thold_3), + .pc_lq_func_slp_sl_thold_3(pc_lq_func_slp_sl_thold_3), + .pc_lq_gptr_sl_thold_3(pc_lq_gptr_sl_thold_3), + .pc_lq_func_nsl_thold_3(pc_lq_func_nsl_thold_3), + .pc_lq_func_slp_nsl_thold_3(pc_lq_func_slp_nsl_thold_3), + .pc_lq_abst_sl_thold_3(pc_lq_abst_sl_thold_3), + .pc_lq_abst_slp_sl_thold_3(pc_lq_abst_slp_sl_thold_3), + .pc_lq_time_sl_thold_3(pc_lq_time_sl_thold_3), + .pc_lq_repr_sl_thold_3(pc_lq_repr_sl_thold_3), + .pc_lq_bolt_sl_thold_3(pc_lq_bolt_sl_thold_3), + .pc_lq_cfg_slp_sl_thold_3(pc_lq_cfg_slp_sl_thold_3), + .pc_lq_regf_slp_sl_thold_3(pc_lq_regf_slp_sl_thold_3), + .pc_lq_ary_nsl_thold_3(pc_lq_ary_nsl_thold_3), + .pc_lq_ary_slp_nsl_thold_3(pc_lq_ary_slp_nsl_thold_3), + .pc_lq_cfg_sl_thold_3(pc_lq_cfg_sl_thold_3), + .pc_lq_fce_3(pc_lq_fce_3), + .pc_lq_ccflush_dc(pc_lq_ccflush_dc), + .pc_lq_bo_enable_3(pc_lq_bo_enable_3), + .an_ac_scan_diag_dc(an_ac_scan_diag_dc), + .bo_enable_2(bo_enable_2), + .sg_2(sg_2), + .func_sl_thold_2(func_sl_thold_2), + .func_slp_sl_thold_2(func_slp_sl_thold_2), + .func_nsl_thold_2(func_nsl_thold_2), + .func_slp_nsl_thold_2(func_slp_nsl_thold_2), + .ary_nsl_thold_2(ary_nsl_thold_2), + .ary_slp_nsl_thold_2(ary_slp_nsl_thold_2), + .time_sl_thold_2(time_sl_thold_2), + .repr_sl_thold_2(repr_sl_thold_2), + .bolt_sl_thold_2(bolt_sl_thold_2), + .cfg_slp_sl_thold_2(cfg_slp_sl_thold_2), + .regf_slp_sl_thold_2(regf_slp_sl_thold_2), + .abst_sl_thold_2(abst_sl_thold_2), + .abst_slp_sl_thold_2(abst_slp_sl_thold_2), + .cfg_sl_thold_2(cfg_sl_thold_2), + .fce_2(fce_2), + .clkoff_dc_b(clkoff_dc_b), + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .g6t_clkoff_dc_b(g6t_clkoff_dc_b), + .g6t_d_mode_dc(g6t_d_mode_dc), + .g6t_delay_lclkr_dc(g6t_delay_lclkr_dc), + .g6t_mpw1_dc_b(g6t_mpw1_dc_b), + .g6t_mpw2_dc_b(g6t_mpw2_dc_b), + .g8t_clkoff_dc_b(g8t_clkoff_dc_b), + .g8t_d_mode_dc(g8t_d_mode_dc), + .g8t_delay_lclkr_dc(g8t_delay_lclkr_dc), + .g8t_mpw1_dc_b(g8t_mpw1_dc_b), + .g8t_mpw2_dc_b(g8t_mpw2_dc_b), + .cam_clkoff_dc_b(cam_clkoff_dc_b), + .cam_d_mode_dc(cam_d_mode_dc), + .cam_act_dis_dc(cam_act_dis_dc), + .cam_delay_lclkr_dc(cam_delay_lclkr_dc), + .cam_mpw1_dc_b(cam_mpw1_dc_b), + .cam_mpw2_dc_b(cam_mpw2_dc_b), + .gptr_scan_in(gptr_scan_in), + .gptr_scan_out(gptr_scan_out), + .func_scan_in(perv_func_scan_in), + .func_scan_out(perv_func_scan_out) +); + +assign func_scan_out[18:24] = {lsq_func_scan_out[18:23], perv_func_scan_out}; + +endmodule diff --git a/dev/verilog/work/lq_agen.v b/dev/verilog/work/lq_agen.v new file mode 100755 index 0000000..536bfaf --- /dev/null +++ b/dev/verilog/work/lq_agen.v @@ -0,0 +1,341 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" + +module lq_agen( + x, + y, + mode64, + dir_ig_57_b, + sum_non_erat, + sum, + sum_arr_dir01, + sum_arr_dir23, + sum_arr_dir45, + sum_arr_dir67, + way, + rel4_dir_wr_val, + ary_write_act_01, + ary_write_act_23, + ary_write_act_45, + ary_write_act_67 +); + +//------------------------------------------------------------------- +// Generics +//------------------------------------------------------------------- +//parameter expand_type = 2; // 2 - ibm tech, 1 - other + +input [0:63] x; +input [0:63] y; +input mode64; // 1 per byte [0:31] +input dir_ig_57_b; // when this is low , bit 57 becomes "1" . + +output [0:63] sum_non_erat; // for compares and uses other than array address +output [0:51] sum; // 0:51 for erat + +output [52:57] sum_arr_dir01; + +output [52:57] sum_arr_dir23; + +output [52:57] sum_arr_dir45; + +output [52:57] sum_arr_dir67; + +input [0:7] way; // 8 bit vector use to be in array model +input rel4_dir_wr_val; +output ary_write_act_01; +output ary_write_act_23; +output ary_write_act_45; +output ary_write_act_67; + +parameter tiup = 1'b1; +parameter tidn = 1'b0; + +wire [0:51] sum_int; +wire [0:51] sum_non_erat_b; +wire [0:51] sum_erat; +wire [0:51] sum_erat_b; +wire [0:51] sum_0; +wire [0:51] sum_1; +wire [1:7] g08; +wire [1:6] t08; +wire [1:7] c64_b; +wire addr_sel_64; + +wire [0:63] x_b; + +wire [0:63] y_b; + +wire [52:57] sum_arr; + +wire [52:57] sum_arr_lv1_0_b; + +wire [52:57] sum_arr_lv1_1_b; + +assign addr_sel_64 = mode64; + +// assume pins come in the top +// start global carry along the top . +// byte groups (0 near top) stretch out along the macro. + +//assign x_b[0:63] = (~(x[0:63])); // receiving inverter near pin +tri_inv #(.WIDTH(64)) x_b_0 (.y(x_b[0:63]), .a(x[0:63])); + +//assign y_b[0:63] = (~(y[0:63])); // receiving inverter near pin +tri_inv #(.WIDTH(64)) y_b_0 (.y(y_b[0:63]), .a(y[0:63])); + +//################################################## +//## local part of byte group +//################################################## + +lq_agen_loca loc_0( + .x_b(x_b[0:7]), //i-- + .y_b(y_b[0:7]), //i-- + .sum_0(sum_0[0:7]), //o-- + .sum_1(sum_1[0:7]) //o-- +); + +lq_agen_loca loc_1( + .x_b(x_b[8:15]), //i-- + .y_b(y_b[8:15]), //i-- + .sum_0(sum_0[8:15]), //o-- + .sum_1(sum_1[8:15]) //o-- +); + +lq_agen_loca loc_2( + .x_b(x_b[16:23]), //i-- + .y_b(y_b[16:23]), //i-- + .sum_0(sum_0[16:23]), //o-- + .sum_1(sum_1[16:23]) //o-- +); + +lq_agen_loca loc_3( + .x_b(x_b[24:31]), //i-- + .y_b(y_b[24:31]), //i-- + .sum_0(sum_0[24:31]), //o-- + .sum_1(sum_1[24:31]) //o-- +); + +lq_agen_loca loc_4( + .x_b(x_b[32:39]), //i-- + .y_b(y_b[32:39]), //i-- + .sum_0(sum_0[32:39]), //o-- + .sum_1(sum_1[32:39]) //o-- +); + +lq_agen_loca loc_5( + .x_b(x_b[40:47]), //i-- + .y_b(y_b[40:47]), //i-- + .sum_0(sum_0[40:47]), //o-- + .sum_1(sum_1[40:47]) //o-- +); + +lq_agen_locae loc_6( + .x_b(x_b[48:55]), //i-- + .y_b(y_b[48:55]), //i-- + .sum_0(sum_0[48:51]), //o-- + .sum_1(sum_1[48:51]) //o-- +); + +//################################################## +//## local part of global carry +//################################################## + +lq_agen_glbloc gclc_1( + .x_b(x_b[8:15]), //i-- + .y_b(y_b[8:15]), //i-- + .g08(g08[1]), //o-- + .t08(t08[1]) //o-- +); + +lq_agen_glbloc gclc_2( + .x_b(x_b[16:23]), //i-- + .y_b(y_b[16:23]), //i-- + .g08(g08[2]), //o-- + .t08(t08[2]) //o-- +); + +lq_agen_glbloc gclc_3( + .x_b(x_b[24:31]), //i-- + .y_b(y_b[24:31]), //i-- + .g08(g08[3]), //o-- + .t08(t08[3]) //o-- +); + +lq_agen_glbloc gclc_4( + .x_b(x_b[32:39]), //i-- + .y_b(y_b[32:39]), //i-- + .g08(g08[4]), //o-- + .t08(t08[4]) //o-- +); + +lq_agen_glbloc gclc_5( + .x_b(x_b[40:47]), //i-- + .y_b(y_b[40:47]), //i-- + .g08(g08[5]), //o-- + .t08(t08[5]) //o-- +); + +lq_agen_glbloc gclc_6( + .x_b(x_b[48:55]), //i-- + .y_b(y_b[48:55]), //i-- + .g08(g08[6]), //o-- + .t08(t08[6]) //o-- +); + +lq_agen_glbloc_lsb gclc_7( + .x_b(x_b[56:63]), //i-- + .y_b(y_b[56:63]), //i-- + .g08(g08[7]) //o-- +); + +//################################################## +//## global part of global carry {replicate ending of global carry vertical) +//################################################## + +lq_agen_glbglb gc( + .g08(g08[1:7]), //i-- + .t08(t08[1:6]), //i-- + .c64_b(c64_b[1:7]) //o-- +); + +//################################################## +//## final mux (vertical) +//################################################## + +lq_agen_csmux fm_0( + .ci_b(c64_b[1]), //i-- + .sum_0(sum_0[0:7]), //i-- + .sum_1(sum_1[0:7]), //i-- + .sum(sum_int[0:7]) //o-- +); + +lq_agen_csmux fm_1( + .ci_b(c64_b[2]), //i-- + .sum_0(sum_0[8:15]), //i-- + .sum_1(sum_1[8:15]), //i-- + .sum(sum_int[8:15]) //o-- +); + +lq_agen_csmux fm_2( + .ci_b(c64_b[3]), //i-- + .sum_0(sum_0[16:23]), //i-- + .sum_1(sum_1[16:23]), //i-- + .sum(sum_int[16:23]) //o-- +); + +lq_agen_csmux fm_3( + .ci_b(c64_b[4]), //i-- + .sum_0(sum_0[24:31]), //i-- + .sum_1(sum_1[24:31]), //i-- + .sum(sum_int[24:31]) //o-- +); + +lq_agen_csmux fm_4( + .ci_b(c64_b[5]), //i-- + .sum_0(sum_0[32:39]), //i-- + .sum_1(sum_1[32:39]), //i-- + .sum(sum_int[32:39]) //o-- +); + +lq_agen_csmux fm_5( + .ci_b(c64_b[6]), //i-- + .sum_0(sum_0[40:47]), //i-- + .sum_1(sum_1[40:47]), //i-- + .sum(sum_int[40:47]) //o-- +); + // just the 4 msb of the byte go to erat +lq_agen_csmuxe fm_6( + .ci_b(c64_b[7]), //i-- + .sum_0(sum_0[48:51]), //i-- + .sum_1(sum_1[48:51]), //i-- + .sum(sum_int[48:51]) //o-- +); + + // 12 lsbs are for the DIRECTORY +lq_agen_lo kog( + .dir_ig_57_b(dir_ig_57_b), //i--lq_agen_lo(kog) force dir addr 57 to "1" + .x_b(x_b[52:63]), //i--lq_agen_lo(kog) + .y_b(y_b[52:63]), //i--lq_agen_lo(kog) + .sum(sum_non_erat[52:63]), //o--lq_agen_lo(kog) for the compares etc + .sum_arr(sum_arr[52:57]) //o--lq_agen_lo(kog) for the array address +); + +//assign sum_non_erat_b[0:51] = (~(sum_int[0:51])); +tri_inv #(.WIDTH(52)) sum_non_erat_b_0 (.y(sum_non_erat_b[0:51]), .a(sum_int[0:51])); + +//assign sum_non_erat[0:51] = (~(sum_non_erat_b[0:51])); +tri_inv #(.WIDTH(52)) sum_non_erat_0 (.y(sum_non_erat[0:51]), .a(sum_non_erat_b[0:51])); + +//assign sum_erat_b[0:31] = (~(sum_int[0:31] & {32{addr_sel_64}})); +tri_nand2 #(.WIDTH(32)) sum_erat_b_0 (.y(sum_erat_b[0:31]), .a(sum_int[0:31]), .b({32{addr_sel_64}})); + +//assign sum_erat_b[32:51] = (~(sum_int[32:51])); +tri_inv #(.WIDTH(20)) sum_erat_b_32 (.y(sum_erat_b[32:51]), .a(sum_int[32:51])); + +//assign sum_erat = (~(sum_erat_b)); +tri_inv #(.WIDTH(52)) sum_erat_0 (.y(sum_erat[0:51]), .a(sum_erat_b[0:51])); + +assign sum = sum_erat; //rename-- to ERAT only + +// ################################### +// # repower network for directoru +// ################################### + +//assign sum_arr_lv1_1_b[52:57] = (~(sum_arr[52:57])); // 4x +tri_inv #(.WIDTH(6)) sum_arr_lv1_1_b_52 (.y(sum_arr_lv1_1_b[52:57]), .a(sum_arr[52:57])); + +//assign sum_arr_dir01[52:57] = (~(sum_arr_lv1_1_b[52:57])); // 4x --output-- +tri_inv #(.WIDTH(6)) sum_arr_dir01_52 (.y(sum_arr_dir01[52:57]), .a(sum_arr_lv1_1_b[52:57])); + +//assign sum_arr_dir45[52:57] = (~(sum_arr_lv1_1_b[52:57])); // 4x --output-- +tri_inv #(.WIDTH(6)) sum_arr_dir45_52 (.y(sum_arr_dir45[52:57]), .a(sum_arr_lv1_1_b[52:57])); + +//assign sum_arr_lv1_0_b[52:57] = (~(sum_arr[52:57])); // 6x +tri_inv #(.WIDTH(6)) sum_arr_lv1_0_b_52 (.y(sum_arr_lv1_0_b[52:57]), .a(sum_arr[52:57])); + +//assign sum_arr_dir23[52:57] = (~(sum_arr_lv1_0_b[52:57])); // 4x --output-- +tri_inv #(.WIDTH(6)) sum_arr_dir23_52 (.y(sum_arr_dir23[52:57]), .a(sum_arr_lv1_0_b[52:57])); + +//assign sum_arr_dir67[52:57] = (~(sum_arr_lv1_0_b[52:57])); // 4x --output-- +tri_inv #(.WIDTH(6)) sum_arr_dir67_52 (.y(sum_arr_dir67[52:57]), .a(sum_arr_lv1_0_b[52:57])); + +// ###################################################################### +// ## this experimental piece is for directory read/write collisions +// ###################################################################### + +assign ary_write_act_01 = rel4_dir_wr_val & (way[0] | way[1]); +assign ary_write_act_23 = rel4_dir_wr_val & (way[2] | way[3]); +assign ary_write_act_45 = rel4_dir_wr_val & (way[4] | way[5]); +assign ary_write_act_67 = rel4_dir_wr_val & (way[6] | way[7]); + +endmodule diff --git a/dev/verilog/work/lq_agen_csmux.v b/dev/verilog/work/lq_agen_csmux.v new file mode 100755 index 0000000..da44894 --- /dev/null +++ b/dev/verilog/work/lq_agen_csmux.v @@ -0,0 +1,78 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +// input phase is importent +// (change X (B) by switching xor/xnor ) + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" + +module lq_agen_csmux( + sum_0, + sum_1, + ci_b, + sum +); + +input [0:7] sum_0; // after xor +input [0:7] sum_1; +input ci_b; + +output [0:7] sum; + +wire [0:7] sum0_b; + +wire [0:7] sum1_b; + +wire int_ci; + +wire int_ci_t; + +wire int_ci_b; + +//assign int_ci = (~ci_b); +tri_inv int_ci_0 (.y(int_ci), .a(ci_b)); + +//assign int_ci_t = (~ci_b); +tri_inv int_ci_t_0 (.y(int_ci_t), .a(ci_b)); + +//assign int_ci_b = (~int_ci_t); +tri_inv int_ci_b_0 (.y(int_ci_b), .a(int_ci_t)); + +//assign sum0_b[0] = (~(sum_0[0] & int_ci_b)); +tri_nand2 #(.WIDTH(8)) sum0_b_0 (.y(sum0_b[0:7]), .a(sum_0[0:7]), .b({8{int_ci_b}})); + +//assign sum1_b[0] = (~(sum_1[0] & int_ci)); +tri_nand2 #(.WIDTH(8)) sum1_b_0 (.y(sum1_b[0:7]), .a(sum_1[0:7]), .b({8{int_ci}})); + +//assign sum[0] = (~(sum0_b[0] & sum1_b[0])); +tri_nand2 #(.WIDTH(8)) sum0 (.y(sum[0:7]), .a(sum0_b[0:7]), .b(sum1_b[0:7])); + + +endmodule diff --git a/dev/verilog/work/lq_agen_csmuxe.v b/dev/verilog/work/lq_agen_csmuxe.v new file mode 100755 index 0000000..7f05adb --- /dev/null +++ b/dev/verilog/work/lq_agen_csmuxe.v @@ -0,0 +1,77 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +// input phase is importent +// (change X (B) by switching xor/xnor ) + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" + +module lq_agen_csmuxe( + sum_0, + sum_1, + ci_b, + sum +); + +input [0:3] sum_0; // after xor +input [0:3] sum_1; +input ci_b; + +output [0:3] sum; + +wire [0:3] sum0_b; + +wire [0:3] sum1_b; + +wire int_ci; + +wire int_ci_t; + +wire int_ci_b; + +//assign int_ci = (~ci_b); +tri_inv int_ci_0 (.y(int_ci), .a(ci_b)); + +//assign int_ci_t = (~ci_b); +tri_inv int_ci_t_0 (.y(int_ci_t), .a(ci_b)); + +//assign int_ci_b = (~int_ci_t); +tri_inv int_ci_b_0 (.y(int_ci_b), .a(int_ci_t)); + +//assign sum0_b[0] = (~(sum_0[0] & int_ci_b)); +tri_nand2 #(.WIDTH(4)) sum0_b_0 (.y(sum0_b[0:3]), .a(sum_0[0:3]), .b({4{int_ci_b}})); + +//assign sum1_b[0] = (~(sum_1[0] & int_ci)); +tri_nand2 #(.WIDTH(4)) sum1_b_0 (.y(sum1_b[0:3]), .a(sum_1[0:3]), .b({4{int_ci}})); + +//assign sum[0] = (~(sum0_b[0] & sum1_b[0])); +tri_nand2 #(.WIDTH(4)) sum0 (.y(sum[0:3]), .a(sum0_b[0:3]), .b(sum1_b[0:3])); + +endmodule diff --git a/dev/verilog/work/lq_agen_glbglb.v b/dev/verilog/work/lq_agen_glbglb.v new file mode 100755 index 0000000..faa138b --- /dev/null +++ b/dev/verilog/work/lq_agen_glbglb.v @@ -0,0 +1,268 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +// input phase is importent +// (change X (B) by switching xor/xnor ) + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" + +module lq_agen_glbglb( + g08, + t08, + c64_b +); +input [1:7] g08; +input [1:6] t08; + +output [1:7] c64_b; + +wire [0:3] b1_g16_b; + +wire [0:2] b1_t16_b; + +wire [0:1] b1_g32; + +wire [0:0] b1_t32; + +wire [0:3] b2_g16_b; + +wire [0:2] b2_t16_b; + +wire [0:1] b2_g32; + +wire [0:0] b2_t32; + +wire [0:3] b3_g16_b; + +wire [0:2] b3_t16_b; + +wire [0:1] b3_g32; + +wire [0:0] b3_t32; + +wire [0:3] b4_g16_b; + +wire [0:2] b4_t16_b; + +wire [0:1] b4_g32; + +wire [0:0] b4_t32; + +wire [0:2] b5_g16_b; + +wire [0:1] b5_t16_b; + +wire [0:1] b5_g32; + +wire [0:0] b5_t32; + +wire [0:1] b6_g16_b; + +wire [0:0] b6_t16_b; + +wire [0:0] b6_g32; + +wire [0:0] b7_g16_b; + +wire [0:0] b7_g32; + +////############################# +////## byte 1 +////############################# + +//assign b1_g16_b[0] = (~(g08[1] | (t08[1] & g08[2]))); +tri_aoi21 b1_g16_b_0 (.y(b1_g16_b[0]), .a0(t08[1]), .a1(g08[2]), .b0(g08[1])); + +//assign b1_g16_b[1] = (~(g08[3] | (t08[3] & g08[4]))); +tri_aoi21 b1_g16_b_1 (.y(b1_g16_b[1]), .a0(t08[3]), .a1(g08[4]), .b0(g08[3])); + +//assign b1_g16_b[2] = (~(g08[5] | (t08[5] & g08[6]))); +tri_aoi21 b1_g16_b_2 (.y(b1_g16_b[2]), .a0(t08[5]), .a1(g08[6]), .b0(g08[5])); + +//assign b1_g16_b[3] = (~(g08[7])); +tri_inv b1_g16_b_3 (.y(b1_g16_b[3]), .a(g08[7])); + +//assign b1_t16_b[0] = (~(t08[1] & t08[2])); +tri_nand2 b1_t16_b_0 (.y(b1_t16_b[0]), .a(t08[1]), .b(t08[2])); + +//assign b1_t16_b[1] = (~(t08[3] & t08[4])); +tri_nand2 b1_t16_b_1 (.y(b1_t16_b[1]), .a(t08[3]), .b(t08[4])); + +//assign b1_t16_b[2] = (~(t08[5] & t08[6])); +tri_nand2 b1_t16_b_2 (.y(b1_t16_b[2]), .a(t08[5]), .b(t08[6])); + +//assign b1_g32[0] = (~(b1_g16_b[0] & (b1_t16_b[0] | b1_g16_b[1]))); +tri_oai21 b1_g32_0 (.y(b1_g32[0]), .a0(b1_t16_b[0]), .a1(b1_g16_b[1]), .b0(b1_g16_b[0])); + +//assign b1_g32[1] = (~(b1_g16_b[2] & (b1_t16_b[2] | b1_g16_b[3]))); +tri_oai21 b1_g32_1 (.y(b1_g32[1]), .a0(b1_t16_b[2]), .a1(b1_g16_b[3]), .b0(b1_g16_b[2])); + +//assign b1_t32[0] = (~(b1_t16_b[0] | b1_t16_b[1])); +tri_nor2 b1_t32_0 (.y(b1_t32[0]), .a(b1_t16_b[0]), .b(b1_t16_b[1])); + +//assign c64_b[1] = (~(b1_g32[0] | (b1_t32[0] & b1_g32[1]))); //output-- +tri_aoi21 c64_b_1 (.y(c64_b[1]), .a0(b1_t32[0]), .a1(b1_g32[1]), .b0(b1_g32[0])); + +////############################# +////## byte 2 +////############################# + +//assign b2_g16_b[0] = (~(g08[2] | (t08[2] & g08[3]))); +tri_aoi21 b2_g16_b_0 (.y(b2_g16_b[0]), .a0(t08[2]), .a1(g08[3]), .b0(g08[2])); + +//assign b2_g16_b[1] = (~(g08[4] | (t08[4] & g08[5]))); +tri_aoi21 b2_g16_b_1 (.y(b2_g16_b[1]), .a0(t08[4]), .a1(g08[5]), .b0(g08[4])); + +//assign b2_g16_b[2] = (~(g08[6])); +tri_inv #(.WIDTH(2)) b2_g16_b_2 (.y(b2_g16_b[2:3]), .a(g08[6:7])); + +//assign b2_t16_b[0] = (~(t08[2] & t08[3])); +tri_nand2 b2_t16_b_0 (.y(b2_t16_b[0]), .a(t08[2]), .b(t08[3])); + +//assign b2_t16_b[1] = (~(t08[4] & t08[5])); +tri_nand2 b2_t16_b_1 (.y(b2_t16_b[1]), .a(t08[4]), .b(t08[5])); + +//assign b2_t16_b[2] = (~(t08[6])); +tri_inv b2_t16_b_2 (.y(b2_t16_b[2]), .a(t08[6])); + +//assign b2_g32[0] = (~(b2_g16_b[0] & (b2_t16_b[0] | b2_g16_b[1]))); +tri_oai21 b2_g32_0 (.y(b2_g32[0]), .a0(b2_t16_b[0]), .a1(b2_g16_b[1]), .b0(b2_g16_b[0])); + +//assign b2_g32[1] = (~(b2_g16_b[2] & (b2_t16_b[2] | b2_g16_b[3]))); +tri_oai21 b2_g32_1 (.y(b2_g32[1]), .a0(b2_t16_b[2]), .a1(b2_g16_b[3]), .b0(b2_g16_b[2])); + +//assign b2_t32[0] = (~(b2_t16_b[0] | b2_t16_b[1])); +tri_nor2 b2_t32_0 (.y(b2_t32[0]), .a(b2_t16_b[0]), .b(b2_t16_b[1])); + +//assign c64_b[2] = (~(b2_g32[0] | (b2_t32[0] & b2_g32[1]))); //output-- +tri_aoi21 c64_b_2 (.y(c64_b[2]), .a0(b2_t32[0]), .a1(b2_g32[1]), .b0(b2_g32[0])); + +////############################# +////## byte 3 +////############################# + +//assign b3_g16_b[0] = (~(g08[3] | (t08[3] & g08[4]))); +tri_aoi21 b3_g16_b_0 (.y(b3_g16_b[0]), .a0(t08[3]), .a1(g08[4]), .b0(g08[3])); + +//assign b3_g16_b[1] = (~(g08[5])); +tri_inv #(.WIDTH(3)) b3_g16_b_3 (.y(b3_g16_b[1:3]), .a(g08[5:7])); + +//assign b3_t16_b[0] = (~(t08[3] & t08[4])); +tri_nand2 b3_t16_b_0 (.y(b3_t16_b[0]), .a(t08[3]), .b(t08[4])); + +//assign b3_t16_b[1] = (~(t08[5])); +tri_inv #(.WIDTH(2)) b3_t16_b_1 (.y(b3_t16_b[1:2]), .a(t08[5:6])); + +//assign b3_g32[0] = (~(b3_g16_b[0] & (b3_t16_b[0] | b3_g16_b[1]))); +tri_oai21 b3_g32_0 (.y(b3_g32[0]), .a0(b3_t16_b[0]), .a1(b3_g16_b[1]), .b0(b3_g16_b[0])); + +//assign b3_g32[1] = (~(b3_g16_b[2] & (b3_t16_b[2] | b3_g16_b[3]))); +tri_oai21 b3_g32_1 (.y(b3_g32[1]), .a0(b3_t16_b[2]), .a1(b3_g16_b[3]), .b0(b3_g16_b[2])); + +//assign b3_t32[0] = (~(b3_t16_b[0] | b3_t16_b[1])); +tri_nor2 b3_t32_0 (.y(b3_t32[0]), .a(b3_t16_b[0]), .b(b3_t16_b[1])); + +//assign c64_b[3] = (~(b3_g32[0] | (b3_t32[0] & b3_g32[1]))); //output-- +tri_aoi21 c64_b_3 (.y(c64_b[3]), .a0(b3_t32[0]), .a1(b3_g32[1]), .b0(b3_g32[0])); + +////############################# +////## byte 4 +////############################# + +//assign b4_g16_b[0] = (~(g08[4])); +tri_inv #(.WIDTH(4)) b4_g16_b_0 (.y(b4_g16_b[0:3]), .a(g08[4:7])); + +//assign b4_t16_b[0] = (~(t08[4])); +tri_inv #(.WIDTH(3)) b4_t16_b_0 (.y(b4_t16_b[0:2]), .a(t08[4:6])); + +//assign b4_g32[0] = (~(b4_g16_b[0] & (b4_t16_b[0] | b4_g16_b[1]))); +tri_oai21 b4_g32_0 (.y(b4_g32[0]), .a0(b4_t16_b[0]), .a1(b4_g16_b[1]), .b0(b4_g16_b[0])); + +//assign b4_g32[1] = (~(b4_g16_b[2] & (b4_t16_b[2] | b4_g16_b[3]))); +tri_oai21 b4_g32_1 (.y(b4_g32[1]), .a0(b4_t16_b[2]), .a1(b4_g16_b[3]), .b0(b4_g16_b[2])); + +//assign b4_t32[0] = (~(b4_t16_b[0] | b4_t16_b[1])); +tri_nor2 b4_t32_0 (.y(b4_t32[0]), .a(b4_t16_b[0]), .b(b4_t16_b[1])); + +//assign c64_b[4] = (~(b4_g32[0] | (b4_t32[0] & b4_g32[1]))); //output-- +tri_aoi21 c64_b_4 (.y(c64_b[4]), .a0(b4_t32[0]), .a1(b4_g32[1]), .b0(b4_g32[0])); + +////############################# +////## byte 5 +////############################# + +//assign b5_g16_b[0] = (~(g08[5])); +tri_inv #(.WIDTH(3)) b5_g16_b_0 (.y(b5_g16_b[0:2]), .a(g08[5:7])); + +//assign b5_t16_b[0] = (~(t08[5])); +tri_inv #(.WIDTH(2)) b5_t16_b_0 (.y(b5_t16_b[0:1]), .a(t08[5:6])); + +//assign b5_g32[0] = (~(b5_g16_b[0] & (b5_t16_b[0] | b5_g16_b[1]))); +tri_oai21 b5_g32_0 (.y(b5_g32[0]), .a0(b5_t16_b[0]), .a1(b5_g16_b[1]), .b0(b5_g16_b[0])); + +//assign b5_g32[1] = (~(b5_g16_b[2])); +tri_inv b5_g32_1 (.y(b5_g32[1]), .a(b5_g16_b[2])); + +//assign b5_t32[0] = (~(b5_t16_b[0] | b5_t16_b[1])); +tri_nor2 b5_t32_0 (.y(b5_t32[0]), .a(b5_t16_b[0]), .b(b5_t16_b[1])); + +//assign c64_b[5] = (~(b5_g32[0] | (b5_t32[0] & b5_g32[1]))); //output-- +tri_aoi21 c64_b_5 (.y(c64_b[5]), .a0(b5_t32[0]), .a1(b5_g32[1]), .b0(b5_g32[0])); + +////############################# +////## byte 6 +////############################# + +//assign b6_g16_b[0] = (~(g08[6])); +tri_inv #(.WIDTH(2)) b6_g16_b_0 (.y(b6_g16_b[0:1]), .a(g08[6:7])); + +//assign b6_t16_b[0] = (~(t08[6])); +tri_inv b6_t16_b_0 (.y(b6_t16_b[0]), .a(t08[6])); + +//assign b6_g32[0] = (~(b6_g16_b[0] & (b6_t16_b[0] | b6_g16_b[1]))); +tri_oai21 b6_g32_0 (.y(b6_g32[0]), .a0(b6_t16_b[0]), .a1(b6_g16_b[1]), .b0(b6_g16_b[0])); + +//assign c64_b[6] = (~(b6_g32[0])); //output-- +tri_inv c64_b_6 (.y(c64_b[6]), .a(b6_g32[0])); + +////############################# +////## byte 7 +////############################# + +//assign b7_g16_b[0] = (~(g08[7])); +tri_inv b7_g16_b_0 (.y(b7_g16_b[0]), .a(g08[7])); + +//assign b7_g32[0] = (~(b7_g16_b[0])); +tri_inv b7_g32_0 (.y(b7_g32[0]), .a(b7_g16_b[0])); + +//assign c64_b[7] = (~(b7_g32[0])); //output-- +tri_inv c64_b_7 (.y(c64_b[7]), .a(b7_g32[0])); + +endmodule diff --git a/dev/verilog/work/lq_agen_glbloc.v b/dev/verilog/work/lq_agen_glbloc.v new file mode 100755 index 0000000..de4bf63 --- /dev/null +++ b/dev/verilog/work/lq_agen_glbloc.v @@ -0,0 +1,117 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" + +module lq_agen_glbloc( + x_b, + y_b, + g08, + t08 +); + +input [0:7] x_b; +input [0:7] y_b; + +output g08; + +output t08; + +wire [0:7] g01; + +wire [0:7] t01; + +wire [0:3] g02_b; + +wire [0:3] t02_b; + +wire [0:1] g04; + +wire [0:1] t04; + +wire g08_b; + +wire t08_b; + +//assign g01[0] = (~(x_b[0] | y_b[0])); +tri_nor2 #(.WIDTH(8)) g01_0 (.y(g01[0:7]), .a(x_b[0:7]), .b(y_b[0:7])); + +//assign t01[0] = (~(x_b[0] & y_b[0])); +tri_nand2 #(.WIDTH(8)) t01_0 (.y(t01[0:7]), .a(x_b[0:7]), .b(y_b[0:7])); + +//assign g02_b[0] = (~(g01[0] | (t01[0] & g01[1]))); +tri_aoi21 g02_b_0 (.y(g02_b[0]), .a0(t01[0]), .a1(g01[1]), .b0(g01[0])); + +//assign g02_b[1] = (~(g01[2] | (t01[2] & g01[3]))); +tri_aoi21 g02_b_1 (.y(g02_b[1]), .a0(t01[2]), .a1(g01[3]), .b0(g01[2])); + +//assign g02_b[2] = (~(g01[4] | (t01[4] & g01[5]))); +tri_aoi21 g02_b_2 (.y(g02_b[2]), .a0(t01[4]), .a1(g01[5]), .b0(g01[4])); + +//assign g02_b[3] = (~(g01[6] | (t01[6] & g01[7]))); +tri_aoi21 g02_b_3 (.y(g02_b[3]), .a0(t01[6]), .a1(g01[7]), .b0(g01[6])); + +//assign t02_b[0] = (~(t01[0] & t01[1])); +tri_nand2 t02_b_0 (.y(t02_b[0]), .a(t01[0]), .b(t01[1])); + +//assign t02_b[1] = (~(t01[2] & t01[3])); +tri_nand2 t02_b_1 (.y(t02_b[1]), .a(t01[2]), .b(t01[3])); + +//assign t02_b[2] = (~(t01[4] & t01[5])); +tri_nand2 t02_b_2 (.y(t02_b[2]), .a(t01[4]), .b(t01[5])); + +//assign t02_b[3] = (~(t01[6] & t01[7])); +tri_nand2 t02_b_3 (.y(t02_b[3]), .a(t01[6]), .b(t01[7])); + +//assign g04[0] = (~(g02_b[0] & (t02_b[0] | g02_b[1]))); +tri_oai21 g04_0 (.y(g04[0]), .a0(t02_b[0]), .a1(g02_b[1]), .b0(g02_b[0])); + +//assign g04[1] = (~(g02_b[2] & (t02_b[2] | g02_b[3]))); +tri_oai21 g04_1 (.y(g04[1]), .a0(t02_b[2]), .a1(g02_b[3]), .b0(g02_b[2])); + +//assign t04[0] = (~(t02_b[0] | t02_b[1])); +tri_nor2 t04_0 (.y(t04[0]), .a(t02_b[0]), .b(t02_b[1])); + +//assign t04[1] = (~(t02_b[2] | t02_b[3])); +tri_nor2 t04_1 (.y(t04[1]), .a(t02_b[2]), .b(t02_b[3])); + +//assign g08_b = (~(g04[0] | (t04[0] & g04[1]))); +tri_aoi21 g08_b_0 (.y(g08_b), .a0(t04[0]), .a1(g04[1]), .b0(g04[0])); + +//assign t08_b = (~((t04[0] & t04[1]))); +tri_nand2 t08_b_0 (.y(t08_b), .a(t04[0]), .b(t04[1])); + +//assign g08 = (~(g08_b)); // output +tri_inv g08_0 (.y(g08), .a(g08_b)); + +//assign t08 = (~(t08_b)); // output +tri_inv t08_0 (.y(t08), .a(t08_b)); + +endmodule diff --git a/dev/verilog/work/lq_agen_glbloc_lsb.v b/dev/verilog/work/lq_agen_glbloc_lsb.v new file mode 100755 index 0000000..8a5a2ac --- /dev/null +++ b/dev/verilog/work/lq_agen_glbloc_lsb.v @@ -0,0 +1,99 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" + +module lq_agen_glbloc_lsb( + x_b, + y_b, + g08 +); +input [0:7] x_b; +input [0:7] y_b; + +output g08; + +wire [0:7] g01; + +wire [0:6] t01; + +wire [0:3] g02_b; + +wire [0:2] t02_b; + +wire [0:1] g04; + +wire [0:0] t04; + +wire g08_b; + +//assign g01[0] = (~(x_b[0] | y_b[0])); +tri_nor2 #(.WIDTH(8)) g01_0 (.y(g01[0:7]), .a(x_b[0:7]), .b(y_b[0:7])); + +//assign t01[0] = (~(x_b[0] & y_b[0])); +tri_nand2 #(.WIDTH(7)) t01_0 (.y(t01[0:6]), .a(x_b[0:6]), .b(y_b[0:6])); + +//assign g02_b[0] = (~(g01[0] | (t01[0] & g01[1]))); +tri_aoi21 g02_b_0 (.y(g02_b[0]), .a0(t01[0]), .a1(g01[1]), .b0(g01[0])); + +//assign g02_b[1] = (~(g01[2] | (t01[2] & g01[3]))); +tri_aoi21 g02_b_1 (.y(g02_b[1]), .a0(t01[2]), .a1(g01[3]), .b0(g01[2])); + +//assign g02_b[2] = (~(g01[4] | (t01[4] & g01[5]))); +tri_aoi21 g02_b_2 (.y(g02_b[2]), .a0(t01[4]), .a1(g01[5]), .b0(g01[4])); + +//assign g02_b[3] = (~(g01[6] | (t01[6] & g01[7]))); +tri_aoi21 g02_b_3 (.y(g02_b[3]), .a0(t01[6]), .a1(g01[7]), .b0(g01[6])); + +//assign t02_b[0] = (~(t01[0] & t01[1])); +tri_nand2 t02_b_0 (.y(t02_b[0]), .a(t01[0]), .b(t01[1])); + +//assign t02_b[1] = (~(t01[2] & t01[3])); +tri_nand2 t02_b_1 (.y(t02_b[1]), .a(t01[2]), .b(t01[3])); + +//assign t02_b[2] = (~(t01[4] & t01[5])); +tri_nand2 t02_b_2 (.y(t02_b[2]), .a(t01[4]), .b(t01[5])); + +//assign g04[0] = (~(g02_b[0] & (t02_b[0] | g02_b[1]))); +tri_oai21 g04_0 (.y(g04[0]), .a0(t02_b[0]), .a1(g02_b[1]), .b0(g02_b[0])); + +//assign g04[1] = (~(g02_b[2] & (t02_b[2] | g02_b[3]))); +tri_oai21 g04_1 (.y(g04[1]), .a0(t02_b[2]), .a1(g02_b[3]), .b0(g02_b[2])); + +//assign t04[0] = (~(t02_b[0] | t02_b[1])); +tri_nor2 t04_0 (.y(t04[0]), .a(t02_b[0]), .b(t02_b[1])); + +//assign g08_b = (~(g04[0] | (t04[0] & g04[1]))); +tri_aoi21 g08_b_0 (.y(g08_b), .a0(t04[0]), .a1(g04[1]), .b0(g04[0])); + +//assign g08 = (~(g08_b)); // output +tri_inv g08_0 (.y(g08), .a(g08_b)); + +endmodule diff --git a/dev/verilog/work/lq_agen_lo.v b/dev/verilog/work/lq_agen_lo.v new file mode 100755 index 0000000..4a9dea1 --- /dev/null +++ b/dev/verilog/work/lq_agen_lo.v @@ -0,0 +1,244 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +// input phase is importent +// (change X (B) by switching xor/xnor ) + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" + +module lq_agen_lo( + x_b, + y_b, + sum, + sum_arr, + dir_ig_57_b +); + +input [0:11] x_b; // after xor +input [0:11] y_b; +input dir_ig_57_b; // when this is low , bit 57 becomes "1" . + +output [0:11] sum; + +output [0:5] sum_arr; + +wire [0:11] p01_b; + +wire [0:11] p01; + +wire [1:11] g01; + +wire [1:10] t01; + +wire [0:11] sum_x; + +wire [0:11] sum_b; + +wire sum_x_11_b; + +wire [1:11] g12_x_b; + +wire [1:11] g02_b; + +wire [1:11] g04; + +wire [1:11] c; + +wire [1:7] g12_y_b; + +wire [1:3] g12_z_b; + +wire [1:9] t02_b; + +wire [1:7] t04; + +//#################################################################### +//# propagate, generate, transmit +//#################################################################### + +//assign g01[1:11] = (~(x_b[1:11] | y_b[1:11])); +tri_nor2 #(.WIDTH(11)) g01_1 (.y(g01[1:11]), .a(x_b[1:11]), .b(y_b[1:11])); + +//assign t01[1:10] = (~(x_b[1:10] & y_b[1:10])); +tri_nand2 #(.WIDTH(10)) t01_1 (.y(t01[1:10]), .a(x_b[1:10]), .b(y_b[1:10])); + +//assign p01_b[0:11] = (~(x_b[0:11] ^ y_b[0:11])); +tri_xnor2 #(.WIDTH(12)) p01_b_1 (.y(p01_b[0:11]), .a(x_b[0:11]), .b(y_b[0:11])); + +//assign p01[0:11] = (~(p01_b[0:11])); +tri_inv #(.WIDTH(12)) p01_0 (.y(p01[0:11]), .a(p01_b[0:11])); + +//#################################################################### +//# final sum and drive +//#################################################################### + +//assign sum_x[0:10] = p01[0:10] ^ c[1:11]; +tri_xor2 #(.WIDTH(11)) sum_x_0 (.y(sum_x[0:10]), .a(p01[0:10]), .b(c[1:11])); + +//assign sum_x_11_b = (~(p01[11])); +tri_inv sum_x_11_b_11 (.y(sum_x_11_b), .a(p01[11])); + +//assign sum_x[11] = (~(sum_x_11_b)); +tri_inv sum_x_11 (.y(sum_x[11]), .a(sum_x_11_b)); + +// 00 01 02 03 04 05 06 07 08 09 10 11 +// 52 53 54 55 56 57 58 59 60 61 62 63 + +//assign sum_b[0:11] = (~(sum_x[0:11])); +tri_inv #(.WIDTH(12)) sum_b_0 (.y(sum_b[0:11]), .a(sum_x[0:11])); + +//assign sum[0:11] = (~(sum_b[0:11])); +tri_inv #(.WIDTH(12)) sum_0 (.y(sum[0:11]), .a(sum_b[0:11])); + +//assign sum_arr[0] = (~(sum_b[0])); +tri_inv #(.WIDTH(5)) sum_arr_0 (.y(sum_arr[0:4]), .a(sum_b[0:4])); + +//assign sum_arr[5] = (~(sum_b[5] & dir_ig_57_b)); // OR with negative inputs +tri_nand2 sum_arr_5 (.y(sum_arr[5]), .a(sum_b[5]), .b(dir_ig_57_b)); + +//#################################################################### +//# carry path is cogge-stone +//#################################################################### + +//assign g02_b[1] = (~(g01[1] | (t01[1] & g01[2]))); +tri_aoi21 #(.WIDTH(10)) g02_b_1 (.y(g02_b[1:10]), .a0(t01[1:10]), .a1(g01[2:11]), .b0(g01[1:10])); + +//assign g02_b[11] = (~(g01[11])); +tri_inv g02_b_11 (.y(g02_b[11]), .a(g01[11])); + +//assign t02_b[1] = (~(t01[1] & t01[2])); +tri_nand2 #(.WIDTH(9)) t02_b_1 (.y(t02_b[1:9]), .a(t01[1:9]), .b(t01[2:10])); + +//assign g04[1] = (~(g02_b[1] & (t02_b[1] | g02_b[3]))); +tri_oai21 #(.WIDTH(9)) g04_1 (.y(g04[1:9]), .a0(t02_b[1:9]), .a1(g02_b[3:11]), .b0(g02_b[1:9])); + +//assign g04[10] = (~(g02_b[10])); +tri_inv #(.WIDTH(2)) g04_10 (.y(g04[10:11]), .a(g02_b[10:11])); + +//assign t04[1] = (~(t02_b[1] | t02_b[3])); +tri_nor2 #(.WIDTH(7)) t04_1 (.y(t04[1:7]), .a(t02_b[1:7]), .b(t02_b[3:9])); + +//assign g12_x_b[1] = (~(g04[1])); +tri_inv g12_x_b_1 (.y(g12_x_b[1]), .a(g04[1])); + +//assign g12_y_b[1] = (~(t04[1] & g04[5])); +tri_nand2 g12_y_b_1 (.y(g12_y_b[1]), .a(t04[1]), .b(g04[5])); + +//assign g12_z_b[1] = (~(t04[1] & t04[5] & g04[9])); +tri_nand3 g12_z_b_1 (.y(g12_z_b[1]), .a(t04[1]), .b(t04[5]), .c(g04[9])); + +//assign c[1] = (~(g12_x_b[1] & g12_y_b[1] & g12_z_b[1])); +tri_nand3 c_1 (.y(c[1]), .a(g12_x_b[1]), .b(g12_y_b[1]), .c(g12_z_b[1])); + +//assign g12_x_b[2] = (~(g04[2])); +tri_inv g12_x_b_2 (.y(g12_x_b[2]), .a(g04[2])); + +//assign g12_y_b[2] = (~(t04[2] & g04[6])); +tri_nand2 g12_y_b_2 (.y(g12_y_b[2]), .a(t04[2]), .b(g04[6])); + +//assign g12_z_b[2] = (~(t04[2] & t04[6] & g04[10])); +tri_nand3 g12_z_b_2 (.y(g12_z_b[2]), .a(t04[2]), .b(t04[6]), .c(g04[10])); + +//assign c[2] = (~(g12_x_b[2] & g12_y_b[2] & g12_z_b[2])); +tri_nand3 c_2 (.y(c[2]), .a(g12_x_b[2]), .b(g12_y_b[2]), .c(g12_z_b[2])); + +//assign g12_x_b[3] = (~(g04[3])); +tri_inv g12_x_b_3 (.y(g12_x_b[3]), .a(g04[3])); + +//assign g12_y_b[3] = (~(t04[3] & g04[7])); +tri_nand2 g12_y_b_3 (.y(g12_y_b[3]), .a(t04[3]), .b(g04[7])); + +//assign g12_z_b[3] = (~(t04[3] & t04[7] & g04[11])); +tri_nand3 g12_z_b_3 (.y(g12_z_b[3]), .a(t04[3]), .b(t04[7]), .c(g04[11])); + +//assign c[3] = (~(g12_x_b[3] & g12_y_b[3] & g12_z_b[3])); +tri_nand3 c_3 (.y(c[3]), .a(g12_x_b[3]), .b(g12_y_b[3]), .c(g12_z_b[3])); + +//assign g12_x_b[4] = (~(g04[4])); +tri_inv g12_x_b_4 (.y(g12_x_b[4]), .a(g04[4])); + +//assign g12_y_b[4] = (~(t04[4] & g04[8])); +tri_nand2 g12_y_b_4 (.y(g12_y_b[4]), .a(t04[4]), .b(g04[8])); + +//assign c[4] = (~(g12_x_b[4] & g12_y_b[4])); +tri_nand2 c_4 (.y(c[4]), .a(g12_x_b[4]), .b(g12_y_b[4])); + +//assign g12_x_b[5] = (~(g04[5])); +tri_inv g12_x_b_5 (.y(g12_x_b[5]), .a(g04[5])); + +//assign g12_y_b[5] = (~(t04[5] & g04[9])); +tri_nand2 g12_y_b_5 (.y(g12_y_b[5]), .a(t04[5]), .b(g04[9])); + +//assign c[5] = (~(g12_x_b[5] & g12_y_b[5])); +tri_nand2 c_5 (.y(c[5]), .a(g12_x_b[5]), .b(g12_y_b[5])); + +//assign g12_x_b[6] = (~(g04[6])); +tri_inv g12_x_b_6 (.y(g12_x_b[6]), .a(g04[6])); + +//assign g12_y_b[6] = (~(t04[6] & g04[10])); +tri_nand2 g12_y_b_6 (.y(g12_y_b[6]), .a(t04[6]), .b(g04[10])); + +//assign c[6] = (~(g12_x_b[6] & g12_y_b[6])); +tri_nand2 c_6 (.y(c[6]), .a(g12_x_b[6]), .b(g12_y_b[6])); + +//assign g12_x_b[7] = (~(g04[7])); +tri_inv g12_x_b_7 (.y(g12_x_b[7]), .a(g04[7])); + +//assign g12_y_b[7] = (~(t04[7] & g04[11])); +tri_nand2 g12_y_b_7 (.y(g12_y_b[7]), .a(t04[7]), .b(g04[11])); + +//assign c[7] = (~(g12_x_b[7] & g12_y_b[7])); +tri_nand2 c_7 (.y(c[7]), .a(g12_x_b[7]), .b(g12_y_b[7])); + +//assign g12_x_b[8] = (~(g04[8])); +tri_inv g12_x_b_8 (.y(g12_x_b[8]), .a(g04[8])); + +//assign c[8] = (~(g12_x_b[8])); +tri_inv c_8 (.y(c[8]), .a(g12_x_b[8])); + +//assign g12_x_b[9] = (~(g04[9])); +tri_inv g12_x_b_9 (.y(g12_x_b[9]), .a(g04[9])); + +//assign c[9] = (~(g12_x_b[9])); +tri_inv c_9 (.y(c[9]), .a(g12_x_b[9])); + +//assign g12_x_b[10] = (~(g04[10])); +tri_inv g12_x_b_10 (.y(g12_x_b[10]), .a(g04[10])); + +//assign c[10] = (~(g12_x_b[10])); +tri_inv c_10 (.y(c[10]), .a(g12_x_b[10])); + +//assign g12_x_b[11] = (~(g04[11])); +tri_inv g12_x_b_11 (.y(g12_x_b[11]), .a(g04[11])); + +//assign c[11] = (~(g12_x_b[11])); +tri_inv c_11 (.y(c[11]), .a(g12_x_b[11])); + +endmodule diff --git a/dev/verilog/work/lq_agen_loca.v b/dev/verilog/work/lq_agen_loca.v new file mode 100755 index 0000000..cd8e083 --- /dev/null +++ b/dev/verilog/work/lq_agen_loca.v @@ -0,0 +1,181 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +// input phase is importent +// (change X (B) by switching xor/xnor ) + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" + +module lq_agen_loca( + x_b, + y_b, + sum_0, + sum_1 +); +input [0:7] x_b; // after xor +input [0:7] y_b; + +output [0:7] sum_0; + +output [0:7] sum_1; + +wire [0:7] h01; + +wire [0:7] h01_b; + +wire [0:7] x; + +wire [0:7] y; + +wire [1:7] g01_b; + +wire [1:7] t01_b; + +wire [0:7] p01; + +wire [0:7] p01_b; + +wire [1:7] g08_b; + +wire [1:7] g08; + +wire [1:7] g04_b; + +wire [1:7] g02; + +wire [1:7] t02; + +wire [1:7] t04_b; + +wire [1:7] t08; + +wire [1:7] t08_b; + +//#################################################################### +//# inverter at top to drive to bit location +//#################################################################### + +//assign x[0:7] = (~x_b[0:7]); // maybe should be fat wire +tri_inv #(.WIDTH(8)) x_0 (.y(x[0:7]), .a(x_b[0:7])); + +//assign y[0:7] = (~y_b[0:7]); // maybe should be fat wire +tri_inv #(.WIDTH(8)) y_0 (.y(y[0:7]), .a(y_b[0:7])); + +//#################################################################### +//# funny way to make xor +//#################################################################### + +//assign g01_b[1:7] = (~(x[1:7] & y[1:7])); +tri_nand2 #(.WIDTH(7)) g01_b_1 (.y(g01_b[1:7]), .a(x[1:7]), .b(y[1:7])); + +//assign t01_b[1:7] = (~(x[1:7] | y[1:7])); +tri_nor2 #(.WIDTH(7)) t01_b_1 (.y(t01_b[1:7]), .a(x[1:7]), .b(y[1:7])); + +//assign p01_b[0:7] = (~(x[0:7] ^ y[0:7])); +tri_xnor2 #(.WIDTH(8)) p01_b_0 (.y(p01_b[0:7]), .a(x[0:7]), .b(y[0:7])); + +//assign p01[0:7] = (~(p01_b[0:7])); +tri_inv #(.WIDTH(8)) p01_0 (.y(p01[0:7]), .a(p01_b[0:7])); + +//assign h01[0:7] = (~p01_b[0:7]); +tri_inv #(.WIDTH(8)) h01_0 (.y(h01[0:7]), .a(p01_b[0:7])); + +//assign h01_b[0:7] = (~p01[0:7]); +tri_inv #(.WIDTH(8)) h01_b_0 (.y(h01_b[0:7]), .a(p01[0:7])); + +//#################################################################### +//# local carry +//#################################################################### + +//assign g02[1] = (~(g01_b[1] & (t01_b[1] | g01_b[2]))); +tri_oai21 #(.WIDTH(6)) g02_1 (.y(g02[1:6]), .a0(t01_b[1:6]), .a1(g01_b[2:7]), .b0(g01_b[1:6])); + +//assign g02[7] = (~(g01_b[7])); +tri_inv g02_7 (.y(g02[7]), .a(g01_b[7])); + +//assign t02[1] = (~(t01_b[1] | t01_b[2])); +tri_nor2 #(.WIDTH(5)) t02_1 (.y(t02[1:5]), .a(t01_b[1:5]), .b(t01_b[2:6])); + +//assign t02[6] = (~(g01_b[6] & (t01_b[6] | t01_b[7]))); //final-- +tri_oai21 t02_6 (.y(t02[6]), .a0(t01_b[6]), .a1(t01_b[7]), .b0(g01_b[6])); + +//assign t02[7] = (~(t01_b[7])); +tri_inv t02_7 (.y(t02[7]), .a(t01_b[7])); + +//assign g04_b[1] = (~(g02[1] | (t02[1] & g02[3]))); +tri_aoi21 #(.WIDTH(5)) g04_b_1 (.y(g04_b[1:5]), .a0(t02[1:5]), .a1(g02[3:7]), .b0(g02[1:5])); + +//assign g04_b[6] = (~(g02[6])); +tri_inv #(.WIDTH(2)) g04_b_6 (.y(g04_b[6:7]), .a(g02[6:7])); + +//assign t04_b[1] = (~(t02[1] & t02[3])); +tri_nand2 #(.WIDTH(3)) t04_b_1 (.y(t04_b[1:3]), .a(t02[1:3]), .b(t02[3:5])); + +//assign t04_b[4] = (~(g02[4] | (t02[4] & t02[6]))); //final-- +tri_aoi21 #(.WIDTH(2)) t04_b_4 (.y(t04_b[4:5]), .a0(t02[4:5]), .a1(t02[6:7]), .b0(g02[4:5])); + +//assign t04_b[6] = (~(t02[6])); +tri_inv #(.WIDTH(2)) t04_b_6 (.y(t04_b[6:7]), .a(t02[6:7])); + +//assign g08[1] = (~(g04_b[1] & (t04_b[1] | g04_b[5]))); //final-- +tri_oai21 #(.WIDTH(3)) g08_1 (.y(g08[1:3]), .a0(t04_b[1:3]), .a1(g04_b[5:7]), .b0(g04_b[1:3])); + +//assign g08[4] = (~(g04_b[4])); +tri_inv #(.WIDTH(4)) g08_4 (.y(g08[4:7]), .a(g04_b[4:7])); + +//assign t08[1] = (~(g04_b[1] & (t04_b[1] | t04_b[5]))); //final-- +tri_oai21 #(.WIDTH(3)) t08_1 (.y(t08[1:3]), .a0(t04_b[1:3]), .a1(t04_b[5:7]), .b0(g04_b[1:3])); + +//assign t08[4] = (~(t04_b[4])); +tri_inv #(.WIDTH(4)) t08_4 (.y(t08[4:7]), .a(t04_b[4:7])); + +//#################################################################### +//# conditional sums // may need to make NON-xor implementation +//#################################################################### + +//assign g08_b[1] = (~g08[1]); +tri_inv #(.WIDTH(7)) g08_b_1 (.y(g08_b[1:7]), .a(g08[1:7])); + +//assign t08_b[1] = (~t08[1]); +tri_inv #(.WIDTH(7)) t08_b_1 (.y(t08_b[1:7]), .a(t08[1:7])); + +//assign sum_0[0] = (~((h01[0] & g08[1]) | (h01_b[0] & g08_b[1]))); //output-- +tri_aoi22 #(.WIDTH(7)) sum_0_0 (.y(sum_0[0:6]), .a0(h01[0:6]), .a1(g08[1:7]), .b0(h01_b[0:6]), .b1(g08_b[1:7])); + +//assign sum_0[7] = (~(h01_b[7])); //output-- +tri_inv sum_0_7 (.y(sum_0[7]), .a(h01_b[7])); + +//assign sum_1[0] = (~((h01[0] & t08[1]) | (h01_b[0] & t08_b[1]))); //output-- +tri_aoi22 #(.WIDTH(7)) sum_1_0 (.y(sum_1[0:6]), .a0(h01[0:6]), .a1(t08[1:7]), .b0(h01_b[0:6]), .b1(t08_b[1:7])); + +//assign sum_1[7] = (~(h01[7])); //output-- +tri_inv sum_1_7 (.y(sum_1[7]), .a(h01[7])); + +endmodule diff --git a/dev/verilog/work/lq_agen_locae.v b/dev/verilog/work/lq_agen_locae.v new file mode 100755 index 0000000..8116234 --- /dev/null +++ b/dev/verilog/work/lq_agen_locae.v @@ -0,0 +1,175 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +// this is used in the agen ... for this byte (half the bits go to ERAT through this macro, others go to DIR from different macro + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" + +module lq_agen_locae( + x_b, + y_b, + sum_0, + sum_1 +); + +input [0:7] x_b; // after xor +input [0:7] y_b; + +output [0:3] sum_0; + +output [0:3] sum_1; + +wire [0:7] x; + +wire [0:7] y; + +wire [1:7] g01_b; + +wire [1:7] t01_b; + +wire [0:3] p01; + +wire [0:3] p01_b; + +wire [1:4] g08_b; + +wire [1:4] g08; + +wire [1:7] g04_b; + +wire [1:7] g02; + +wire [1:7] t02; + +wire [1:7] t04_b; + +wire [1:4] t08; + +wire [1:4] t08_b; + +wire [0:3] h01; + +wire [0:3] h01_b; + +//#################################################################### +//# inverter at top to drive to bit location +//#################################################################### + +//assign x[0:7] = (~x_b[0:7]); // maybe should be fat wire +tri_inv #(.WIDTH(8)) x_0 (.y(x[0:7]), .a(x_b[0:7])); + +//assign y[0:7] = (~y_b[0:7]); // maybe should be fat wire +tri_inv #(.WIDTH(8)) y_0 (.y(y[0:7]), .a(y_b[0:7])); + +//#################################################################### +//# pgt +//#################################################################### + +//assign g01_b[1:7] = (~(x[1:7] & y[1:7])); +tri_nand2 #(.WIDTH(7)) g01_b_1 (.y(g01_b[1:7]), .a(x[1:7]), .b(y[1:7])); + +//assign t01_b[1:7] = (~(x[1:7] | y[1:7])); +tri_nor2 #(.WIDTH(7)) t01_b_1 (.y(t01_b[1:7]), .a(x[1:7]), .b(y[1:7])); + +//assign p01_b[0:3] = (~(x[0:3] ^ y[0:3])); +tri_xnor2 #(.WIDTH(4)) p01_b_0 (.y(p01_b[0:3]), .a(x[0:3]), .b(y[0:3])); + +//assign p01[0:3] = (~(p01_b[0:3])); +tri_inv #(.WIDTH(4)) p01_0 (.y(p01[0:3]), .a(p01_b[0:3])); + +//#################################################################### +//# local carry +//#################################################################### + +//assign g02[1] = (~(g01_b[1] & (t01_b[1] | g01_b[2]))); +tri_oai21 #(.WIDTH(6)) g02_1 (.y(g02[1:6]), .a0(t01_b[1:6]), .a1(g01_b[2:7]), .b0(g01_b[1:6])); + +//assign g02[7] = (~(g01_b[7])); +tri_inv g02_7 (.y(g02[7]), .a(g01_b[7])); + +//assign t02[1] = (~(t01_b[1] | t01_b[2])); +tri_nor2 #(.WIDTH(5)) t02_1 (.y(t02[1:5]), .a(t01_b[1:5]), .b(t01_b[2:6])); + +//assign t02[6] = (~(g01_b[6] & (t01_b[6] | t01_b[7]))); //final-- +tri_oai21 t02_6 (.y(t02[6]), .a0(t01_b[6]), .a1(t01_b[7]), .b0(g01_b[6])); + +//assign t02[7] = (~(t01_b[7])); +tri_inv t02_7 (.y(t02[7]), .a(t01_b[7])); + +//assign g04_b[1] = (~(g02[1] | (t02[1] & g02[3]))); +tri_aoi21 #(.WIDTH(5)) g04_b_1 (.y(g04_b[1:5]), .a0(t02[1:5]), .a1(g02[3:7]), .b0(g02[1:5])); + +//assign g04_b[6] = (~(g02[6])); +tri_inv #(.WIDTH(2)) g04_b_6 (.y(g04_b[6:7]), .a(g02[6:7])); + +//assign t04_b[1] = (~(t02[1] & t02[3])); +tri_nand2 #(.WIDTH(3)) t04_b_1 (.y(t04_b[1:3]), .a(t02[1:3]), .b(t02[3:5])); + +//assign t04_b[4] = (~(g02[4] | (t02[4] & t02[6]))); //final-- +tri_aoi21 #(.WIDTH(2)) t04_b_4 (.y(t04_b[4:5]), .a0(t02[4:5]), .a1(t02[6:7]), .b0(g02[4:5])); + +//assign t04_b[6] = (~(t02[6])); +tri_inv #(.WIDTH(2)) t04_b_6 (.y(t04_b[6:7]), .a(t02[6:7])); + +//assign g08[1] = (~(g04_b[1] & (t04_b[1] | g04_b[5]))); //final-- +tri_oai21 #(.WIDTH(3)) g08_1 (.y(g08[1:3]), .a0(t04_b[1:3]), .a1(g04_b[5:7]), .b0(g04_b[1:3])); + +//assign g08[4] = (~(g04_b[4])); +tri_inv g08_4 (.y(g08[4]), .a(g04_b[4])); + +//assign t08[1] = (~(g04_b[1] & (t04_b[1] | t04_b[5]))); //final-- +tri_oai21 #(.WIDTH(3)) t08_1 (.y(t08[1:3]), .a0(t04_b[1:3]), .a1(t04_b[5:7]), .b0(g04_b[1:3])); + +//assign t08[4] = (~(t04_b[4])); +tri_inv t08_4 (.y(t08[4]), .a(t04_b[4])); + +//#################################################################### +//# conditional sums // may need to make NON-xor implementation +//#################################################################### + +//assign g08_b[1] = (~g08[1]); +tri_inv #(.WIDTH(4)) g08_b_1 (.y(g08_b[1:4]), .a(g08[1:4])); + +//assign t08_b[1] = (~t08[1]); +tri_inv #(.WIDTH(4)) t08_b_1 (.y(t08_b[1:4]), .a(t08[1:4])); + +//assign h01[0:3] = (~p01_b[0:3]); +tri_inv #(.WIDTH(4)) h01_0 (.y(h01[0:3]), .a(p01_b[0:3])); + +//assign h01_b[0:3] = (~p01[0:3]); +tri_inv #(.WIDTH(4)) h01_b_0 (.y(h01_b[0:3]), .a(p01[0:3])); + +//assign sum_0[0] = (~((h01[0] & g08[1]) | (h01_b[0] & g08_b[1]))); //output-- +tri_aoi22 #(.WIDTH(4)) sum0 (.y(sum_0[0:3]), .a0(h01[0:3]), .a1(g08[1:4]), .b0(h01_b[0:3]), .b1(g08_b[1:4])); + +//assign sum_1[0] = (~((h01[0] & t08[1]) | (h01_b[0] & t08_b[1]))); //output-- +tri_aoi22 #(.WIDTH(4)) sum1 (.y(sum_1[0:3]), .a0(h01[0:3]), .a1(t08[1:4]), .b0(h01_b[0:3]), .b1(t08_b[1:4])); + +endmodule diff --git a/dev/verilog/work/lq_arb.v b/dev/verilog/work/lq_arb.v new file mode 100755 index 0000000..3954926 --- /dev/null +++ b/dev/verilog/work/lq_arb.v @@ -0,0 +1,1415 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +// Description: XU LSU Store Data Rotator Wrapper +// +//***************************************************************************** + +// ########################################################################################## +// VHDL Contents +// 1) Load Queue +// 2) Store Queue +// 3) Load/Store Queue Control +// ########################################################################################## + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" + +// parameter EXPAND_TYPE = 2; // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) +// `define LOAD_CREDITS 16 +// `define STORE_CREDITS 32 +// parameter ITAG_SIZE_ENC = 7; +// parameter CL_SIZE = 6; // 6 => 64B CLINE, 7 => 128B CLINE +// parameter THREADS = 2; // Number of Threads in the system +// parameter STQ_DATA_SIZE = 64; // 64 or 128 Bit store data sizes supported +// parameter REAL_IFAR_WIDTH = 42; // real addressing bits + +module lq_arb( + imq_arb_iuq_ld_req_avail, + imq_arb_iuq_tid, + imq_arb_iuq_usr_def, + imq_arb_iuq_wimge, + imq_arb_iuq_p_addr, + imq_arb_iuq_ttype, + imq_arb_iuq_opSize, + imq_arb_iuq_cTag, + imq_arb_mmq_ld_req_avail, + imq_arb_mmq_st_req_avail, + imq_arb_mmq_tid, + imq_arb_mmq_usr_def, + imq_arb_mmq_wimge, + imq_arb_mmq_p_addr, + imq_arb_mmq_ttype, + imq_arb_mmq_opSize, + imq_arb_mmq_cTag, + imq_arb_mmq_st_data, + ldq_arb_ld_req_pwrToken, + ldq_arb_ld_req_avail, + ldq_arb_tid, + ldq_arb_usr_def, + ldq_arb_wimge, + ldq_arb_p_addr, + ldq_arb_ttype, + ldq_arb_opSize, + ldq_arb_cTag, + stq_arb_stq1_stg_act, + stq_arb_st_req_avail, + stq_arb_stq3_cmmt_val, + stq_arb_stq3_cmmt_reject, + stq_arb_stq3_req_val, + stq_arb_stq3_tid, + stq_arb_stq3_usrDef, + stq_arb_stq3_wimge, + stq_arb_stq3_p_addr, + stq_arb_stq3_ttype, + stq_arb_stq3_opSize, + stq_arb_stq3_byteEn, + stq_arb_stq3_cTag, + dat_lsq_stq4_128data, + ldq_arb_rel1_stg_act, + ldq_arb_rel1_data_sel, + ldq_arb_rel1_data, + ldq_arb_rel1_blk_store, + ldq_arb_rel1_axu_val, + ldq_arb_rel1_op_size, + ldq_arb_rel1_addr, + ldq_arb_rel1_ci, + ldq_arb_rel1_byte_swap, + ldq_arb_rel1_thrd_id, + ldq_arb_rel2_rdat_sel, + stq_arb_stq1_axu_val, + stq_arb_stq1_epid_val, + stq_arb_stq1_opSize, + stq_arb_stq1_p_addr, + stq_arb_stq1_wimge_i, + stq_arb_stq1_store_data, + stq_arb_stq1_byte_swap, + stq_arb_stq1_thrd_id, + stq_arb_release_itag_vld, + stq_arb_release_itag, + stq_arb_release_tid, + l2_lsq_req_ld_pop, + l2_lsq_req_st_pop, + l2_lsq_req_st_gather, + ctl_lsq_stq3_icswx_data, + ldq_arb_rel2_rd_data, + arb_ldq_rel2_wrt_data, + arb_stq_cred_avail, + arb_ldq_ldq_unit_sel, + arb_imq_iuq_unit_sel, + arb_imq_mmq_unit_sel, + lsq_ctl_stq1_axu_val, + lsq_ctl_stq1_epid_val, + lsq_dat_stq1_le_mode, + lsq_dat_stq1_op_size, + lsq_dat_stq1_addr, + lsq_dat_stq2_store_data, + lsq_ctl_stq1_addr, + lsq_ctl_stq1_ci, + lsq_ctl_stq1_thrd_id, + lsq_ctl_stq_release_itag_vld, + lsq_ctl_stq_release_itag, + lsq_ctl_stq_release_tid, + lsq_l2_pwrToken, + lsq_l2_valid, + lsq_l2_tid, + lsq_l2_p_addr, + lsq_l2_wimge, + lsq_l2_usrDef, + lsq_l2_byteEn, + lsq_l2_ttype, + lsq_l2_opSize, + lsq_l2_coreTag, + lsq_l2_dataToken, + lsq_l2_st_data, + ctl_lsq_spr_lsucr0_b2b, + xu_lq_spr_xucr0_cred, + xu_lq_spr_xucr0_cls, + lq_pc_err_l2credit_overrun, + vdd, + gnd, + nclk, + sg_0, + func_sl_thold_0_b, + func_sl_force, + func_slp_sl_thold_0_b, + func_slp_sl_force, + d_mode_dc, + delay_lclkr_dc, + mpw1_dc_b, + mpw2_dc_b, + scan_in, + scan_out +); + + // IUQ Request to the L2 + input imq_arb_iuq_ld_req_avail; + input [0:1] imq_arb_iuq_tid; + input [0:3] imq_arb_iuq_usr_def; + input [0:4] imq_arb_iuq_wimge; + input [64-`REAL_IFAR_WIDTH:63] imq_arb_iuq_p_addr; + input [0:5] imq_arb_iuq_ttype; + input [0:2] imq_arb_iuq_opSize; + input [0:4] imq_arb_iuq_cTag; + + // MMQ Request to the L2 + input imq_arb_mmq_ld_req_avail; + input imq_arb_mmq_st_req_avail; + input [0:1] imq_arb_mmq_tid; + input [0:3] imq_arb_mmq_usr_def; + input [0:4] imq_arb_mmq_wimge; + input [64-`REAL_IFAR_WIDTH:63] imq_arb_mmq_p_addr; + input [0:5] imq_arb_mmq_ttype; + input [0:2] imq_arb_mmq_opSize; + input [0:4] imq_arb_mmq_cTag; + input [0:15] imq_arb_mmq_st_data; + + // LDQ Request to the L2 + input ldq_arb_ld_req_pwrToken; + input ldq_arb_ld_req_avail; + input [0:1] ldq_arb_tid; + input [0:3] ldq_arb_usr_def; + input [0:4] ldq_arb_wimge; + input [64-`REAL_IFAR_WIDTH:63] ldq_arb_p_addr; + input [0:5] ldq_arb_ttype; + input [0:2] ldq_arb_opSize; + input [0:4] ldq_arb_cTag; + + // Store Type Request to L2 + input stq_arb_stq1_stg_act; + input stq_arb_st_req_avail; + input stq_arb_stq3_cmmt_val; + input stq_arb_stq3_cmmt_reject; + input stq_arb_stq3_req_val; + input [0:1] stq_arb_stq3_tid; + input [0:3] stq_arb_stq3_usrDef; + input [0:4] stq_arb_stq3_wimge; + input [64-`REAL_IFAR_WIDTH:63] stq_arb_stq3_p_addr; + input [0:5] stq_arb_stq3_ttype; + input [0:2] stq_arb_stq3_opSize; + input [0:15] stq_arb_stq3_byteEn; + input [0:4] stq_arb_stq3_cTag; + input [0:127] dat_lsq_stq4_128data; + + // Common Between LDQ and STQ + input ldq_arb_rel1_stg_act; + input ldq_arb_rel1_data_sel; + input [0:127] ldq_arb_rel1_data; + input ldq_arb_rel1_blk_store; + input ldq_arb_rel1_axu_val; + input [0:2] ldq_arb_rel1_op_size; + input [64-`REAL_IFAR_WIDTH:63] ldq_arb_rel1_addr; + input ldq_arb_rel1_ci; + input ldq_arb_rel1_byte_swap; + input [0:`THREADS-1] ldq_arb_rel1_thrd_id; + input ldq_arb_rel2_rdat_sel; + input stq_arb_stq1_axu_val; + input stq_arb_stq1_epid_val; + input [0:2] stq_arb_stq1_opSize; + input [64-`REAL_IFAR_WIDTH:63] stq_arb_stq1_p_addr; + input stq_arb_stq1_wimge_i; + input [(128-`STQ_DATA_SIZE):127] stq_arb_stq1_store_data; + input stq_arb_stq1_byte_swap; + input [0:`THREADS-1] stq_arb_stq1_thrd_id; + input stq_arb_release_itag_vld; + input [0:`ITAG_SIZE_ENC-1] stq_arb_release_itag; + input [0:`THREADS-1] stq_arb_release_tid; + + // L2 Credit Control + input l2_lsq_req_ld_pop; + input l2_lsq_req_st_pop; + input l2_lsq_req_st_gather; + + // ICSWX Data to be sent to the L2 + input [0:26] ctl_lsq_stq3_icswx_data; + + // Interface with Reload Data Queue + input [0:143] ldq_arb_rel2_rd_data; + output [0:143] arb_ldq_rel2_wrt_data; + + // L2 Credits Available + output arb_stq_cred_avail; + + // Unit Selected to Send Request to the L2 + output arb_ldq_ldq_unit_sel; + output arb_imq_iuq_unit_sel; + output arb_imq_mmq_unit_sel; + + // Common Between LDQ and STQ + output lsq_ctl_stq1_axu_val; + output lsq_ctl_stq1_epid_val; + output lsq_dat_stq1_le_mode; + output [0:2] lsq_dat_stq1_op_size; + output [52:63] lsq_dat_stq1_addr; + output [0:143] lsq_dat_stq2_store_data; + output [64-`REAL_IFAR_WIDTH:63-`CL_SIZE] lsq_ctl_stq1_addr; + output lsq_ctl_stq1_ci; + output [0:`THREADS-1] lsq_ctl_stq1_thrd_id; + + // STCX/ICSWX Itag Complete + output lsq_ctl_stq_release_itag_vld; + output [0:`ITAG_SIZE_ENC-1] lsq_ctl_stq_release_itag; + output [0:`THREADS-1] lsq_ctl_stq_release_tid; + + // L2 Request Signals + output lsq_l2_pwrToken; + output lsq_l2_valid; + output [0:1] lsq_l2_tid; + output [64-`REAL_IFAR_WIDTH:63] lsq_l2_p_addr; + output [0:4] lsq_l2_wimge; + output [0:3] lsq_l2_usrDef; + output [0:15] lsq_l2_byteEn; + output [0:5] lsq_l2_ttype; + output [0:2] lsq_l2_opSize; + output [0:4] lsq_l2_coreTag; + output lsq_l2_dataToken; + output [0:127] lsq_l2_st_data; + + // SPR Bits + input ctl_lsq_spr_lsucr0_b2b; // LSUCR0[B2B] Mode enabled + input xu_lq_spr_xucr0_cred; // XUCR0[CRED] Mode enabled + input xu_lq_spr_xucr0_cls; // XUCR0[CLS] Mode enabled + + // Pervasive Error Report + output lq_pc_err_l2credit_overrun; + + // Pervasive + + + inout vdd; + + + inout gnd; + + (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) + + input [0:`NCLK_WIDTH-1] nclk; + input sg_0; + input func_sl_thold_0_b; + input func_sl_force; + input func_slp_sl_thold_0_b; + input func_slp_sl_force; + input d_mode_dc; + input delay_lclkr_dc; + input mpw1_dc_b; + input mpw2_dc_b; + + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + + input scan_in; + + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + + output scan_out; + + //-------------------------- + // signals + //-------------------------- + + wire [0:2] lsq_dat_stq1_op_size_int; + wire [52:63] ldq_dat_stq1_addr_int; + wire [0:`THREADS-1] ldq_stq1_thrd_id; + wire [64-`REAL_IFAR_WIDTH:63] ldq_stq_stq1_addr; + wire ldq_stq_stq1_le_mode; + wire req_l2_val_d; + wire req_l2_val_q; + wire req_l2_ld_sent_d; + wire req_l2_ld_sent_q; + wire [0:3] req_sel_usrDef_d; + wire [0:3] req_sel_usrDef_q; + wire [0:15] req_sel_byteEn_d; + wire [0:15] req_sel_byteEn_q; + wire [0:4] req_sel_wimge_d; + wire [0:4] req_sel_wimge_q; + wire [64-`REAL_IFAR_WIDTH:63] req_sel_p_addr_d; + wire [64-`REAL_IFAR_WIDTH:63] req_sel_p_addr_q; + wire [0:5] req_sel_ttype_d; + wire [0:5] req_sel_ttype_q; + wire [0:1] req_sel_tid_d; + wire [0:1] req_sel_tid_q; + wire [0:2] req_sel_opSize_d; + wire [0:2] req_sel_opSize_q; + wire [0:4] req_sel_cTag_d; + wire [0:4] req_sel_cTag_q; + wire [0:3] unit_req_sel_usrDef; + wire [0:4] unit_req_sel_wimge; + wire [64-`REAL_IFAR_WIDTH:63] unit_req_sel_p_addr; + wire [0:5] unit_req_sel_ttype; + wire [0:1] unit_req_sel_tid; + wire [0:2] unit_req_sel_opSize; + wire [0:4] unit_req_sel_cTag; + wire [0:3] unit_req_val; + wire [0:3] unit_last_sel_d; + wire [0:3] unit_last_sel_q; + wire [0:3] queue_unit_sel; + wire req_l2_sent; + wire req_l2_ld_pwrToken; + wire req_l2_ld_val; + wire req_l2_st_val; + wire req_l2_act; + wire ld_type_credAvail; + wire st_type_credAvail; + wire st_req_noCreds; + wire st_req_2inpipe; + wire st_req_1inpipe; + wire st_req_0Creds; + wire st2_req_val; + wire st3_req_val; + wire mmq1_req_val; + wire mmq2_req_val_d; + wire mmq2_req_val_q; + wire mmq3_req_val_d; + wire mmq3_req_val_q; + wire stq4_data_override_d; + wire stq4_data_override_q; + wire stq2_req_val_d; + wire stq2_req_val_q; + wire stq3_icswx_val; + wire [64-`REAL_IFAR_WIDTH:63] req_l2_st_p_addr; + wire [0:4] req_l2_st_wimge; + wire [0:3] req_l2_st_usrDef; + wire [0:5] req_l2_st_ttype; + wire [0:1] req_l2_st_tid; + wire [0:2] req_l2_st_opSize; + wire ld_st_noCred_flp_d; + wire ld_st_noCred_flp_q; + wire stq3_store_type_cmmt; + wire stq3_store_type_rej; + wire st_rej_hold_cred_d; + wire st_rej_hold_cred_q; + wire ld_noCred_hold_d; + wire ld_noCred_hold_q; + wire ld_noCred_release; + wire ld_pop_rcvd_d; + wire ld_pop_rcvd_q; + wire ld_cred_blk_rst; + wire ld_cred_blk_run; + wire ld_cred_blk_zero; + wire [0:3] ld_cred_blk_decr; + wire [0:3] ld_cred_blk_init; + wire [0:3] ld_cred_blk_cnt_d; + wire [0:3] ld_cred_blk_cnt_q; + wire load_req_sent; + wire [0:4] load_cred_incr; + wire [0:4] load_cred_decr; + wire [0:1] load_cred_sel; + wire [0:4] load_cred_cnt_d; + wire [0:4] load_cred_cnt_q; + wire ld_cred_err_d; + wire ld_cred_err_q; + wire ld_req_0Creds; + wire ld_req_noCreds; + wire store_req_sent; + wire [0:5] store_cred_incr; + wire [0:5] store_cred_incr2; + wire [0:5] store_cred_decr; + wire [0:2] store_cred_sel; + wire [0:5] store_cred_cnt_d; + wire [0:5] store_cred_cnt_q; + wire st_cred_err_d; + wire st_cred_err_q; + wire [0:26] stq4_req_st_data_d; + wire [0:26] stq4_req_st_data_q; + wire [0:127] req_l2_st_data; + wire [0:143] stq2_store_data; + wire [0:127] stq2_store_data_d; + wire [0:127] stq2_store_data_q; + wire [0:15] stq2_store_parity; + wire [0:143] rel2_wrt_data; + wire spr_lsucr0_b2b_d; + wire spr_lsucr0_b2b_q; + wire spr_xucr0_cred_d; + wire spr_xucr0_cred_q; + wire spr_xucr0_cls_d; + wire spr_xucr0_cls_q; + wire st_b2b_st_dis; + wire ld_b2b_ld_dis; + wire stq1_stg_act; + wire lsq_l2credit_overrun; + wire [0:4] ld_cred_max; + wire [0:5] st_cred_max; + + //-------------------------- + // constants + //-------------------------- + + parameter req_l2_val_offset = 0; + parameter req_l2_ld_sent_offset = req_l2_val_offset + 1; + parameter req_sel_usrDef_offset = req_l2_ld_sent_offset + 1; + parameter req_sel_byteEn_offset = req_sel_usrDef_offset + 4; + parameter req_sel_wimge_offset = req_sel_byteEn_offset + 16; + parameter req_sel_p_addr_offset = req_sel_wimge_offset + 5; + parameter req_sel_ttype_offset = req_sel_p_addr_offset + `REAL_IFAR_WIDTH; + parameter req_sel_tid_offset = req_sel_ttype_offset + 6; + parameter req_sel_opSize_offset = req_sel_tid_offset + 2; + parameter req_sel_cTag_offset = req_sel_opSize_offset + 3; + parameter unit_last_sel_offset = req_sel_cTag_offset + 5; + parameter load_cred_cnt_offset = unit_last_sel_offset + 4; + parameter ld_cred_err_offset = load_cred_cnt_offset + 5; + parameter ld_st_noCred_flp_offset = ld_cred_err_offset + 1; + parameter st_rej_hold_cred_offset = ld_st_noCred_flp_offset + 1; + parameter ld_noCred_hold_offset = st_rej_hold_cred_offset + 1; + parameter ld_pop_rcvd_offset = ld_noCred_hold_offset + 1; + parameter ld_cred_blk_cnt_offset = ld_pop_rcvd_offset + 1; + parameter store_cred_cnt_offset = ld_cred_blk_cnt_offset + 4; + parameter st_cred_err_offset = store_cred_cnt_offset + 6; + parameter spr_lsucr0_b2b_offset = st_cred_err_offset + 1; + parameter spr_xucr0_cred_offset = spr_lsucr0_b2b_offset + 1; + parameter spr_xucr0_cls_offset = spr_xucr0_cred_offset + 1; + parameter stq2_req_val_offset = spr_xucr0_cls_offset + 1; + parameter mmq2_req_val_offset = stq2_req_val_offset + 1; + parameter mmq3_req_val_offset = mmq2_req_val_offset + 1; + parameter stq4_data_override_offset = mmq3_req_val_offset + 1; + parameter stq4_req_st_data_offset = stq4_data_override_offset + 1; + parameter stq2_store_data_offset = stq4_req_st_data_offset + 27; + parameter scan_right = stq2_store_data_offset + 128 - 1; + + wire tiup; + wire [0:scan_right] siv; + wire [0:scan_right] sov; + + assign tiup = 1'b1; + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // LSU Config Bits + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + + // LSUCR0[B2B] Back-2-Back allowed for same type of L2 request + // 1 => Back-2-Back allowed + // 0 => Back-2-Back not allowed, LSI Mode + assign spr_lsucr0_b2b_d = ctl_lsq_spr_lsucr0_b2b; + + // XUCR0[CRED] L2 Credit Control + // 1 => Can only send one load or store when there is 1 store credit and 1 load credit + // 0 => No restrictions when there is 1 store credit and 1 load credit + assign spr_xucr0_cred_d = xu_lq_spr_xucr0_cred; + + // XUCR0[CLS] 128 Byte Cacheline Enabled + // 1 => 128 Byte Cacheline + // 0 => 64 Byte Cacheline + assign spr_xucr0_cls_d = xu_lq_spr_xucr0_cls; + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // Select Between LDQ and STQ Common + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // Reloads have higher priority than Commit Pipe + + assign lsq_ctl_stq1_axu_val = (ldq_arb_rel1_blk_store == 1'b1) ? ldq_arb_rel1_axu_val : + stq_arb_stq1_axu_val; + + assign lsq_ctl_stq1_epid_val = stq_arb_stq1_epid_val & (~ldq_arb_rel1_blk_store); + + assign lsq_dat_stq1_op_size_int = (ldq_arb_rel1_blk_store == 1'b1) ? ldq_arb_rel1_op_size : + stq_arb_stq1_opSize; + + assign ldq_stq_stq1_addr = (ldq_arb_rel1_blk_store == 1'b1) ? ldq_arb_rel1_addr : + stq_arb_stq1_p_addr; + + assign lsq_ctl_stq1_ci = (ldq_arb_rel1_blk_store == 1'b1) ? ldq_arb_rel1_ci : + stq_arb_stq1_wimge_i; + + assign ldq_stq_stq1_le_mode = (ldq_arb_rel1_blk_store == 1'b1) ? ldq_arb_rel1_byte_swap : + stq_arb_stq1_byte_swap; + + assign ldq_stq1_thrd_id = (ldq_arb_rel1_blk_store == 1'b1) ? ldq_arb_rel1_thrd_id : + stq_arb_stq1_thrd_id; + + assign ldq_dat_stq1_addr_int = ldq_stq_stq1_addr[52:63]; + + assign lsq_dat_stq1_op_size = lsq_dat_stq1_op_size_int; + assign lsq_dat_stq1_addr = ldq_dat_stq1_addr_int[52:63]; + assign lsq_ctl_stq1_thrd_id = ldq_stq1_thrd_id; + assign lsq_ctl_stq1_addr = ldq_stq_stq1_addr[64 - `REAL_IFAR_WIDTH:63 - `CL_SIZE]; + assign lsq_dat_stq1_le_mode = ldq_stq_stq1_le_mode; + assign stq1_stg_act = ldq_arb_rel1_stg_act | stq_arb_stq1_stg_act; + + assign lsq_ctl_stq_release_itag_vld = stq_arb_release_itag_vld; + assign lsq_ctl_stq_release_itag = stq_arb_release_itag; + assign lsq_ctl_stq_release_tid = stq_arb_release_tid; + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // Store Data Muxing + // Data that needs to be rotated or written to the cache + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + + generate + if (`STQ_DATA_SIZE == 128) begin : stqDat128 + // Select between L2 reload Data and Store Data + assign stq2_store_data_d = (ldq_arb_rel1_data_sel == 1'b1) ? ldq_arb_rel1_data : + stq_arb_stq1_store_data; + end + endgenerate + + generate + if (`STQ_DATA_SIZE == 64) begin : stqDat64 + assign stq2_store_data_d[0:63] = ldq_arb_rel1_data[0:63]; + + // Select between L2 reload Data and Store Data + assign stq2_store_data_d[64:127] = (ldq_arb_rel1_data_sel == 1'b1) ? ldq_arb_rel1_data[64:127] : + stq_arb_stq1_store_data[64:127]; + end + endgenerate + + generate begin : parGen + genvar t; + for (t = 0; t <= 15; t = t + 1) begin : parGen + assign stq2_store_parity[t] = ^(stq2_store_data_q[t * 8:(t * 8) + 7]); + end + end + endgenerate + + assign rel2_wrt_data = {stq2_store_data_q, stq2_store_parity}; + + // Select betweeen L2/Store and Reload Queue Data + assign stq2_store_data = (ldq_arb_rel2_rdat_sel == 1'b1) ? ldq_arb_rel2_rd_data : + rel2_wrt_data; + + assign lsq_dat_stq2_store_data = stq2_store_data; + assign arb_ldq_rel2_wrt_data = rel2_wrt_data; + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // L2 Credit Control + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + + // Need to flip the no credit available to ldq and stq when running in XUCR0[CRED] mode and there are no load credits or store credits + // Cant send both load and store requests out, need to pick one, so will ping pong between load and store + // Want to hold flp to point to load if the store was rejected and didnt commit to the L1/L2 + // 1 => Load Queue has no Credit + // 0 => Store Queue has no Credit + assign ld_st_noCred_flp_d = spr_xucr0_cred_q & (~ld_st_noCred_flp_q | ld_noCred_hold_q); + assign stq3_store_type_cmmt = stq_arb_stq3_cmmt_val | mmq3_req_val_q; + assign stq3_store_type_rej = stq_arb_stq3_cmmt_reject & ~mmq3_req_val_q; + assign st_rej_hold_cred_d = spr_xucr0_cred_q & (stq3_store_type_rej | (st_rej_hold_cred_q & ~stq_arb_stq3_cmmt_val)); + assign ld_noCred_hold_d = spr_xucr0_cred_q & (load_req_sent | (ld_noCred_hold_q & ~ld_noCred_release)); + assign ld_noCred_release = ld_pop_rcvd_q & ~|(ld_cred_blk_cnt_q) & ~st_rej_hold_cred_q; + assign ld_pop_rcvd_d = l2_lsq_req_ld_pop | (ld_pop_rcvd_q & ~load_req_sent); + + assign ld_cred_blk_rst = spr_xucr0_cred_q & l2_lsq_req_ld_pop; + assign ld_cred_blk_run = |(ld_cred_blk_cnt_q); + assign ld_cred_blk_zero = stq3_store_type_cmmt | stq3_store_type_rej; + assign ld_cred_blk_decr = ld_cred_blk_cnt_q - 4'b0001; + assign ld_cred_blk_init = {1'b1, spr_xucr0_cls_q, 2'b00}; + assign ld_cred_blk_cnt_d = ld_cred_blk_rst ? ld_cred_blk_init : + ld_cred_blk_zero ? 4'b0000 : + ld_cred_blk_run ? ld_cred_blk_decr : + ld_cred_blk_cnt_q; + + // Load Credit Control + assign load_req_sent = |(unit_req_val); + assign load_cred_incr = load_cred_cnt_q + 5'b00001; + assign load_cred_decr = load_cred_cnt_q - 5'b00001; + assign load_cred_sel = {l2_lsq_req_ld_pop, load_req_sent}; + + assign load_cred_cnt_d = (load_cred_sel == 2'b10) ? load_cred_incr : + (load_cred_sel == 2'b01) ? load_cred_decr : + load_cred_cnt_q; + + assign ld_req_0Creds = (load_cred_cnt_q == 5'b00000); + assign ld_req_noCreds = ld_req_0Creds | (spr_xucr0_cred_q & (st_req_0Creds | st_req_1inpipe | st_req_2inpipe | ld_st_noCred_flp_q)); + assign ld_type_credAvail = ~(ld_req_noCreds | ld_b2b_ld_dis); + assign ld_cred_max = 5'd`LOAD_CREDITS; + assign ld_cred_err_d = (load_cred_cnt_q > ld_cred_max); + assign ld_b2b_ld_dis = req_l2_ld_sent_q & (~spr_lsucr0_b2b_q); + + // Store Credit Control + assign store_req_sent = stq_arb_stq3_req_val | mmq3_req_val_q; + assign store_cred_incr = store_cred_cnt_q + 6'b00001; + assign store_cred_incr2 = store_cred_cnt_q + 6'b00010; + assign store_cred_decr = store_cred_cnt_q - 6'b00001; + assign store_cred_sel = {l2_lsq_req_st_pop, l2_lsq_req_st_gather, store_req_sent}; + + //000 store_cred_cnt_q + //001 store_cred_decr + //010 store_cred_incr + //011 store_cred_cnt_q + //100 store_cred_incr + //101 store_cred_cnt_q + //110 store_cred_incr2 + //111 store_cred_incr + + assign store_cred_cnt_d = (store_cred_sel == 3'b001) ? store_cred_decr : + (store_cred_sel == 3'b110) ? store_cred_incr2 : + (store_cred_sel == 3'b000) ? store_cred_cnt_q : + (store_cred_sel == 3'b011) ? store_cred_cnt_q : + (store_cred_sel == 3'b101) ? store_cred_cnt_q : + store_cred_incr; + + assign st_cred_max = 6'd`STORE_CREDITS; + assign st_cred_err_d = (store_cred_cnt_q > st_cred_max); + assign st_req_2inpipe = (store_cred_cnt_q == 6'b000010) & st2_req_val & st3_req_val; + assign st_req_1inpipe = (store_cred_cnt_q == 6'b000001) & (st2_req_val ^ st3_req_val); + assign st_req_0Creds = (store_cred_cnt_q == 6'b000000); + assign st_req_noCreds = st_req_0Creds | st_req_1inpipe | st_req_2inpipe | (spr_xucr0_cred_q & (ld_req_0Creds | ~ld_st_noCred_flp_q)); + assign st_type_credAvail = ~(st_req_noCreds | st_b2b_st_dis); + assign st2_req_val = mmq2_req_val_q | stq2_req_val_q; + assign st3_req_val = (mmq3_req_val_q | stq_arb_stq3_req_val); + assign stq2_req_val_d = stq_arb_st_req_avail & (~mmq1_req_val); + assign stq3_icswx_val = (stq_arb_stq3_ttype[0:4] == 5'b10011); + assign st_b2b_st_dis = st2_req_val & (~spr_lsucr0_b2b_q); + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // L2 Request Arbiter + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + + // Need to block off request when store request is about to be sent to L2 + assign unit_req_val[0] = ldq_arb_ld_req_avail & ld_type_credAvail & (~req_l2_st_val); + assign unit_req_val[1] = imq_arb_iuq_ld_req_avail & ld_type_credAvail & (~req_l2_st_val); + assign unit_req_val[2] = imq_arb_mmq_ld_req_avail & ld_type_credAvail & (~req_l2_st_val); + assign unit_req_val[3] = 1'b0; + + assign queue_unit_sel[0] = (unit_last_sel_q[0] & (~(|(unit_req_val[1:3]))) & unit_req_val[0]) | + (unit_last_sel_q[1] & (~(|(unit_req_val[2:3]))) & unit_req_val[0]) | + (unit_last_sel_q[2] & (~unit_req_val[3]) & unit_req_val[0]) | + (unit_last_sel_q[3] & unit_req_val[0]); + + assign queue_unit_sel[1] = (unit_last_sel_q[0] & unit_req_val[1]) | + (unit_last_sel_q[1] & (~(|(({unit_req_val[0], unit_req_val[2:3]})))) & unit_req_val[1]) | + (unit_last_sel_q[2] & (~(|(({unit_req_val[0], unit_req_val[3]})))) & unit_req_val[1]) | + (unit_last_sel_q[3] & (~unit_req_val[0]) & unit_req_val[1]); + + assign queue_unit_sel[2] = (unit_last_sel_q[0] & (~unit_req_val[1]) & unit_req_val[2]) | + (unit_last_sel_q[1] & unit_req_val[2]) | + (unit_last_sel_q[2] & (~(|(({unit_req_val[0:1], unit_req_val[3]})))) & unit_req_val[2]) | + (unit_last_sel_q[3] & (~(|(unit_req_val[0:1]))) & unit_req_val[2]); + + assign queue_unit_sel[3] = (unit_last_sel_q[0] & (~(|(unit_req_val[1:2]))) & unit_req_val[3]) | + (unit_last_sel_q[1] & (~unit_req_val[2]) & unit_req_val[3]) | + (unit_last_sel_q[2] & unit_req_val[3]) | + (unit_last_sel_q[3] & (~(|(unit_req_val[0:2]))) & unit_req_val[3]); + + assign unit_last_sel_d = (req_l2_sent == 1'b1) ? queue_unit_sel : + unit_last_sel_q; + + // Unit Select + assign unit_req_sel_usrDef = (ldq_arb_usr_def & {4{queue_unit_sel[0]}}) | + (imq_arb_iuq_usr_def & {4{queue_unit_sel[1]}}) | + (imq_arb_mmq_usr_def & {4{queue_unit_sel[2]}}); + + assign unit_req_sel_wimge = (ldq_arb_wimge & {5{queue_unit_sel[0]}}) | + (imq_arb_iuq_wimge & {5{queue_unit_sel[1]}}) | + (imq_arb_mmq_wimge & {5{queue_unit_sel[2]}}); + + assign unit_req_sel_p_addr = (ldq_arb_p_addr & {`REAL_IFAR_WIDTH{queue_unit_sel[0]}}) | + (imq_arb_iuq_p_addr & {`REAL_IFAR_WIDTH{queue_unit_sel[1]}}) | + (imq_arb_mmq_p_addr & {`REAL_IFAR_WIDTH{queue_unit_sel[2]}}); + + assign unit_req_sel_ttype = (ldq_arb_ttype & {6{queue_unit_sel[0]}}) | + (imq_arb_iuq_ttype & {6{queue_unit_sel[1]}}) | + (imq_arb_mmq_ttype & {6{queue_unit_sel[2]}}); + + assign unit_req_sel_tid = (ldq_arb_tid & {2{queue_unit_sel[0]}}) | + (imq_arb_iuq_tid & {2{queue_unit_sel[1]}}) | + (imq_arb_mmq_tid & {2{queue_unit_sel[2]}}); + + assign unit_req_sel_opSize = (ldq_arb_opSize & {3{queue_unit_sel[0]}}) | + (imq_arb_iuq_opSize & {3{queue_unit_sel[1]}}) | + (imq_arb_mmq_opSize & {3{queue_unit_sel[2]}}); + + assign unit_req_sel_cTag = (ldq_arb_cTag & {5{queue_unit_sel[0]}}) | + (imq_arb_iuq_cTag & {5{queue_unit_sel[1]}}) | + (imq_arb_mmq_cTag & {5{queue_unit_sel[2]}}); + + assign req_l2_sent = |(queue_unit_sel); + assign req_l2_ld_pwrToken = (ldq_arb_ld_req_pwrToken | imq_arb_iuq_ld_req_avail | imq_arb_mmq_ld_req_avail) & ld_type_credAvail; + assign req_l2_ld_val = (ldq_arb_ld_req_avail | imq_arb_iuq_ld_req_avail | imq_arb_mmq_ld_req_avail) & ld_type_credAvail; + assign req_l2_ld_sent_d = req_l2_ld_val; + assign req_l2_st_val = (stq_arb_stq3_req_val | mmq3_req_val_q); + assign req_l2_val_d = req_l2_ld_val | stq_arb_stq3_req_val | mmq3_req_val_q; + assign req_l2_act = ldq_arb_ld_req_pwrToken | imq_arb_iuq_ld_req_avail | imq_arb_mmq_ld_req_avail | stq_arb_stq3_req_val | mmq3_req_val_q; + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // MMQ Store Type Request Delay + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + + assign mmq1_req_val = imq_arb_mmq_st_req_avail & st_type_credAvail & (~(mmq2_req_val_q | mmq3_req_val_q)); + assign mmq2_req_val_d = mmq1_req_val; + assign mmq3_req_val_d = mmq2_req_val_q; + assign stq4_data_override_d = mmq3_req_val_q | stq3_icswx_val; + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // Mux Between Store and other requests + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + + assign req_l2_st_p_addr = (mmq3_req_val_q == 1'b0) ? stq_arb_stq3_p_addr : + imq_arb_mmq_p_addr; + + assign req_l2_st_wimge = (mmq3_req_val_q == 1'b0) ? stq_arb_stq3_wimge : + imq_arb_mmq_wimge; + + assign req_l2_st_usrDef = (mmq3_req_val_q == 1'b0) ? stq_arb_stq3_usrDef : + imq_arb_mmq_usr_def; + + assign req_sel_byteEn_d = stq_arb_stq3_byteEn & {16{(~mmq3_req_val_q)}}; + + assign req_l2_st_ttype = (mmq3_req_val_q == 1'b0) ? stq_arb_stq3_ttype : + imq_arb_mmq_ttype; + + assign req_l2_st_tid = (mmq3_req_val_q == 1'b0) ? stq_arb_stq3_tid : + imq_arb_mmq_tid; + + assign req_l2_st_opSize = stq_arb_stq3_opSize & {3{(~mmq3_req_val_q)}}; + + assign req_sel_p_addr_d = (req_l2_st_val == 1'b1) ? req_l2_st_p_addr : + unit_req_sel_p_addr; + + assign req_sel_wimge_d = (req_l2_st_val == 1'b1) ? req_l2_st_wimge : + unit_req_sel_wimge; + + assign req_sel_usrDef_d = (req_l2_st_val == 1'b1) ? req_l2_st_usrDef : + unit_req_sel_usrDef; + + assign req_sel_ttype_d = (req_l2_st_val == 1'b1) ? req_l2_st_ttype : + unit_req_sel_ttype; + + assign req_sel_tid_d = (req_l2_st_val == 1'b1) ? req_l2_st_tid : + unit_req_sel_tid; + + assign req_sel_opSize_d = (req_l2_st_val == 1'b1) ? req_l2_st_opSize : + unit_req_sel_opSize; + + assign req_sel_cTag_d = (req_l2_st_val == 1'b1) ? stq_arb_stq3_cTag : + unit_req_sel_cTag; + + // Select between icswx and mmu request + // ICSWX Store Data Format + // (0:2) => ~GS,PR,DS + // (3:9) => "0000000" + // (10:31) => RS(10:31) + // (32:39) => LPID + // (40:41) => "00" + // (42:55) => PID + // TLBIVAX Store Data Format + // (0:31) => unusedBits + // (32:39) => LPAR_ID + // (40:44) => Reserved + // (45:47) => IND,GS,L + // (48:55) => unusedBits + assign stq4_req_st_data_d[3:18] = (mmq3_req_val_q == 1'b1) ? imq_arb_mmq_st_data[0:15] : + ctl_lsq_stq3_icswx_data[3:18]; + + assign stq4_req_st_data_d[0:2] = ctl_lsq_stq3_icswx_data[0:2]; + assign stq4_req_st_data_d[19:26] = ctl_lsq_stq3_icswx_data[19:26]; + + assign req_l2_st_data[32:55] = (stq4_data_override_q == 1'b0) ? dat_lsq_stq4_128data[32:55] : + stq4_req_st_data_q[3:26]; + + assign req_l2_st_data[0:2] = (stq4_data_override_q == 1'b0) ? dat_lsq_stq4_128data[0:2] : + stq4_req_st_data_q[0:2]; + + assign req_l2_st_data[3:9] = dat_lsq_stq4_128data[3:9] & {7{(~stq4_data_override_q)}}; + assign req_l2_st_data[10:31] = dat_lsq_stq4_128data[10:31]; + assign req_l2_st_data[56:127] = dat_lsq_stq4_128data[56:127]; + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // Outputs + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + assign lsq_l2credit_overrun = ld_cred_err_q | st_cred_err_q; + + tri_direct_err_rpt #(.WIDTH(1)) err_rpt( + .vd(vdd), + .gd(gnd), + .err_in(lsq_l2credit_overrun), + .err_out(lq_pc_err_l2credit_overrun) + ); + + // Credits Available + assign arb_stq_cred_avail = st_type_credAvail & (~imq_arb_mmq_st_req_avail); + + // Unit Selected to Send request to L2 + assign arb_ldq_ldq_unit_sel = queue_unit_sel[0]; + assign arb_imq_iuq_unit_sel = queue_unit_sel[1]; + assign arb_imq_mmq_unit_sel = queue_unit_sel[2] | mmq3_req_val_q; + + // L2 Request + assign lsq_l2_pwrToken = req_l2_ld_pwrToken | stq_arb_stq3_req_val | mmq3_req_val_q; + assign lsq_l2_valid = req_l2_val_q; + assign lsq_l2_tid = req_sel_tid_q; + assign lsq_l2_p_addr = req_sel_p_addr_q; + assign lsq_l2_wimge = req_sel_wimge_q; + assign lsq_l2_usrDef = req_sel_usrDef_q; + assign lsq_l2_byteEn = req_sel_byteEn_q; + assign lsq_l2_ttype = req_sel_ttype_q; + assign lsq_l2_opSize = req_sel_opSize_q; + assign lsq_l2_coreTag = req_sel_cTag_q; + assign lsq_l2_dataToken = stq_arb_stq3_req_val | mmq3_req_val_q; + assign lsq_l2_st_data = req_l2_st_data; + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // REGISTERS + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) req_l2_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[req_l2_val_offset]), + .scout(sov[req_l2_val_offset]), + .din(req_l2_val_d), + .dout(req_l2_val_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) req_l2_ld_sent_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[req_l2_ld_sent_offset]), + .scout(sov[req_l2_ld_sent_offset]), + .din(req_l2_ld_sent_d), + .dout(req_l2_ld_sent_q) + ); + + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) req_sel_usrDef_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(req_l2_act), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[req_sel_usrDef_offset:req_sel_usrDef_offset + 4 - 1]), + .scout(sov[req_sel_usrDef_offset:req_sel_usrDef_offset + 4 - 1]), + .din(req_sel_usrDef_d), + .dout(req_sel_usrDef_q) + ); + + + tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) req_sel_byteEn_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(req_l2_act), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[req_sel_byteEn_offset:req_sel_byteEn_offset + 16 - 1]), + .scout(sov[req_sel_byteEn_offset:req_sel_byteEn_offset + 16 - 1]), + .din(req_sel_byteEn_d), + .dout(req_sel_byteEn_q) + ); + + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) req_sel_wimge_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(req_l2_act), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[req_sel_wimge_offset:req_sel_wimge_offset + 5 - 1]), + .scout(sov[req_sel_wimge_offset:req_sel_wimge_offset + 5 - 1]), + .din(req_sel_wimge_d), + .dout(req_sel_wimge_q) + ); + + + tri_rlmreg_p #(.WIDTH(`REAL_IFAR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) req_sel_p_addr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(req_l2_act), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[req_sel_p_addr_offset:req_sel_p_addr_offset + `REAL_IFAR_WIDTH - 1]), + .scout(sov[req_sel_p_addr_offset:req_sel_p_addr_offset + `REAL_IFAR_WIDTH - 1]), + .din(req_sel_p_addr_d), + .dout(req_sel_p_addr_q) + ); + + + tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) req_sel_ttype_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(req_l2_act), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[req_sel_ttype_offset:req_sel_ttype_offset + 6 - 1]), + .scout(sov[req_sel_ttype_offset:req_sel_ttype_offset + 6 - 1]), + .din(req_sel_ttype_d), + .dout(req_sel_ttype_q) + ); + + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) req_sel_tid_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(req_l2_act), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[req_sel_tid_offset:req_sel_tid_offset + 2 - 1]), + .scout(sov[req_sel_tid_offset:req_sel_tid_offset + 2 - 1]), + .din(req_sel_tid_d), + .dout(req_sel_tid_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) req_sel_opSize_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(req_l2_act), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[req_sel_opSize_offset:req_sel_opSize_offset + 3 - 1]), + .scout(sov[req_sel_opSize_offset:req_sel_opSize_offset + 3 - 1]), + .din(req_sel_opSize_d), + .dout(req_sel_opSize_q) + ); + + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) req_sel_cTag_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(req_l2_act), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[req_sel_cTag_offset:req_sel_cTag_offset + 5 - 1]), + .scout(sov[req_sel_cTag_offset:req_sel_cTag_offset + 5 - 1]), + .din(req_sel_cTag_d), + .dout(req_sel_cTag_q) + ); + + + tri_rlmreg_p #(.WIDTH(4), .INIT(1), .NEEDS_SRESET(1)) unit_last_sel_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[unit_last_sel_offset:unit_last_sel_offset + 4 - 1]), + .scout(sov[unit_last_sel_offset:unit_last_sel_offset + 4 - 1]), + .din(unit_last_sel_d), + .dout(unit_last_sel_q) + ); + + + tri_rlmreg_p #(.WIDTH(5), .INIT(`LOAD_CREDITS), .NEEDS_SRESET(1)) load_cred_cnt_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[load_cred_cnt_offset:load_cred_cnt_offset + 5 - 1]), + .scout(sov[load_cred_cnt_offset:load_cred_cnt_offset + 5 - 1]), + .din(load_cred_cnt_d), + .dout(load_cred_cnt_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ld_cred_err_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ld_cred_err_offset]), + .scout(sov[ld_cred_err_offset]), + .din(ld_cred_err_d), + .dout(ld_cred_err_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ld_st_noCred_flp_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ld_st_noCred_flp_offset]), + .scout(sov[ld_st_noCred_flp_offset]), + .din(ld_st_noCred_flp_d), + .dout(ld_st_noCred_flp_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) st_rej_hold_cred_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[st_rej_hold_cred_offset]), + .scout(sov[st_rej_hold_cred_offset]), + .din(st_rej_hold_cred_d), + .dout(st_rej_hold_cred_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ld_noCred_hold_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ld_noCred_hold_offset]), + .scout(sov[ld_noCred_hold_offset]), + .din(ld_noCred_hold_d), + .dout(ld_noCred_hold_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ld_pop_rcvd_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ld_pop_rcvd_offset]), + .scout(sov[ld_pop_rcvd_offset]), + .din(ld_pop_rcvd_d), + .dout(ld_pop_rcvd_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ld_cred_blk_cnt_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ld_cred_blk_cnt_offset:ld_cred_blk_cnt_offset + 4 - 1]), + .scout(sov[ld_cred_blk_cnt_offset:ld_cred_blk_cnt_offset + 4 - 1]), + .din(ld_cred_blk_cnt_d), + .dout(ld_cred_blk_cnt_q) + ); + + tri_rlmreg_p #(.WIDTH(6), .INIT(`STORE_CREDITS), .NEEDS_SRESET(1)) store_cred_cnt_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[store_cred_cnt_offset:store_cred_cnt_offset + 6 - 1]), + .scout(sov[store_cred_cnt_offset:store_cred_cnt_offset + 6 - 1]), + .din(store_cred_cnt_d), + .dout(store_cred_cnt_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) st_cred_err_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[st_cred_err_offset]), + .scout(sov[st_cred_err_offset]), + .din(st_cred_err_d), + .dout(st_cred_err_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_lsucr0_b2b_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_lsucr0_b2b_offset]), + .scout(sov[spr_lsucr0_b2b_offset]), + .din(spr_lsucr0_b2b_d), + .dout(spr_lsucr0_b2b_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr0_cred_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_xucr0_cred_offset]), + .scout(sov[spr_xucr0_cred_offset]), + .din(spr_xucr0_cred_d), + .dout(spr_xucr0_cred_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr0_cls_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_xucr0_cls_offset]), + .scout(sov[spr_xucr0_cls_offset]), + .din(spr_xucr0_cls_d), + .dout(spr_xucr0_cls_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_req_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq2_req_val_offset]), + .scout(sov[stq2_req_val_offset]), + .din(stq2_req_val_d), + .dout(stq2_req_val_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mmq2_req_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[mmq2_req_val_offset]), + .scout(sov[mmq2_req_val_offset]), + .din(mmq2_req_val_d), + .dout(mmq2_req_val_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mmq3_req_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[mmq3_req_val_offset]), + .scout(sov[mmq3_req_val_offset]), + .din(mmq3_req_val_d), + .dout(mmq3_req_val_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_data_override_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq4_data_override_offset]), + .scout(sov[stq4_data_override_offset]), + .din(stq4_data_override_d), + .dout(stq4_data_override_q) + ); + + + tri_rlmreg_p #(.WIDTH(27), .INIT(0), .NEEDS_SRESET(1)) stq4_req_st_data_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(req_l2_act), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq4_req_st_data_offset:stq4_req_st_data_offset + 27 - 1]), + .scout(sov[stq4_req_st_data_offset:stq4_req_st_data_offset + 27 - 1]), + .din(stq4_req_st_data_d), + .dout(stq4_req_st_data_q) + ); + + + tri_rlmreg_p #(.WIDTH(128), .INIT(0), .NEEDS_SRESET(1)) stq2_store_data_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq1_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq2_store_data_offset:stq2_store_data_offset + 128 - 1]), + .scout(sov[stq2_store_data_offset:stq2_store_data_offset + 128 - 1]), + .din(stq2_store_data_d), + .dout(stq2_store_data_q) + ); + + assign siv[0:scan_right] = {sov[1:scan_right], scan_in}; + assign scan_out = sov[0]; + +endmodule diff --git a/dev/verilog/work/lq_axu_dec.v b/dev/verilog/work/lq_axu_dec.v new file mode 100755 index 0000000..5743331 --- /dev/null +++ b/dev/verilog/work/lq_axu_dec.v @@ -0,0 +1,592 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +// Description: LQ AXU Decode +// +//***************************************************************************** + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" + +module lq_axu_dec( + lq_au_ex0_instr, + lq_au_ex1_vld, + lq_au_ex1_tid, + lq_au_ex1_instr, + lq_au_ex1_t3_p, + au_lq_ex0_extload, + au_lq_ex0_extstore, + au_lq_ex0_mftgpr, + au_lq_ex1_ldst_v, + au_lq_ex1_st_v, + au_lq_ex1_ldst_size, + au_lq_ex1_ldst_update, + au_lq_ex1_mftgpr, + au_lq_ex1_mffgpr, + au_lq_ex1_movedp, + au_lq_ex1_ldst_tag, + au_lq_ex1_ldst_dimm, + au_lq_ex1_ldst_indexed, + au_lq_ex1_ldst_forcealign, + au_lq_ex1_ldst_forceexcept, + au_lq_ex1_ldst_priv, + au_lq_ex1_instr_type +); + +//------------------------------------------------------------------- +// Generics +//------------------------------------------------------------------- +//parameter `GPR_POOL_ENC = 6; +//parameter `THREADS = 2; +//parameter `THREADS_POOL_ENC = 1; +//parameter `AXU_SPARE_ENC = 3; + +//------------------------------------------------------------------- +// Input Instruction +//------------------------------------------------------------------- +input [0:31] lq_au_ex0_instr; +input lq_au_ex1_vld; +input [0:`THREADS-1] lq_au_ex1_tid; +input [0:31] lq_au_ex1_instr; +input [0:`GPR_POOL_ENC-1] lq_au_ex1_t3_p; + +//------------------------------------------------------------------- +// Output +//------------------------------------------------------------------- +output au_lq_ex0_extload; +output au_lq_ex0_extstore; +output au_lq_ex0_mftgpr; +output au_lq_ex1_ldst_v; +output au_lq_ex1_st_v; +output [0:5] au_lq_ex1_ldst_size; +output au_lq_ex1_ldst_update; +output au_lq_ex1_mftgpr; +output au_lq_ex1_mffgpr; +output au_lq_ex1_movedp; +output [0:`GPR_POOL_ENC+`THREADS_POOL_ENC+`AXU_SPARE_ENC-1] au_lq_ex1_ldst_tag; +output [0:15] au_lq_ex1_ldst_dimm; +output au_lq_ex1_ldst_indexed; +output au_lq_ex1_ldst_forcealign; +output au_lq_ex1_ldst_forceexcept; +output au_lq_ex1_ldst_priv; +output [0:2] au_lq_ex1_instr_type; + +wire tiup; +wire tidn; +wire [0:5] pri_ex1; +wire [20:31] sec_ex1; +wire isfu_dec_ex1; +wire tv; +wire av; +wire bv; +wire cv; +wire bubble3; +wire prebubble1; +wire ld_st_ex1; +wire st_ex1; +wire indexed; +wire update_form; +wire forcealign; +wire single_precision_ldst; +wire int_word_ldst; +wire sign_ext_ldst; +wire ldst_extpid; +wire io_port; +wire io_port_ext; +wire [0:5] size; +wire cr_writer; +wire mffgpr; +wire mftgpr; +wire fdiv_ex1; +wire fsqrt_ex1; +wire only_from_ucode; +wire final_fmul_uc; +wire only_graphics_mode; +wire ex0_movedp_instr; +wire ex0_mftgpr_instr; + +wire [0:2] iu_au_ex1_ucode_ext; +wire [0:4] ldst_tag_addr; +wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC+`AXU_SPARE_ENC-1] ldst_tag; + + +(* analysis_not_referenced="true" *) + +wire unused; + +assign tiup = 1'b1; +assign tidn = 1'b0; + +// EX0 +// External PID instructions need to be decoded in EX0 +// 011111 - 1001011111 - 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 00 001000 0 00 00 0 0 0 # lfdepx +// 011111 - 1011011111 - 1 0 1 0 0 0 0 1 1 1 0 0 0 0 0 1 00 001000 0 00 00 0 0 0 # stfdepx +assign au_lq_ex0_extload = (lq_au_ex0_instr[0:5] == 6'b011111) & (lq_au_ex0_instr[21:30] == 10'b1001011111); +assign au_lq_ex0_extstore = (lq_au_ex0_instr[0:5] == 6'b011111) & (lq_au_ex0_instr[21:30] == 10'b1011011111); + +// MFTGPR instructions need to be decoded in EX0 +// 011111 1 0001000011 0 1 0 1 0 0 0 0 1 1 1 0 0 0 1 0 0 11 000000 0 01 00 0 0 0 # mtdpx (DITC from FPR) +// 011111 1 0001000011 1 1 0 1 0 0 0 0 1 1 1 0 0 0 1 0 0 11 000000 1 01 00 0 0 0 # mtdpx. (DITC from FPR) +// 011111 1 0001100011 0 1 0 1 0 0 0 0 1 1 0 0 0 0 1 0 0 10 000000 0 01 00 0 0 0 # mtdp (DITC from FPR) +// 011111 1 0001100011 1 1 0 1 0 0 0 0 1 1 0 0 0 0 1 0 0 10 000000 1 01 00 0 0 0 # mtdp. (DITC from FPR) +// 011111 - 1011011101 - 1 0 0 1 0 0 0 1 1 0 0 0 0 1 0 0 00 000000 0 01 00 1 0 1 # mfitgpr (mftgpr for stfiwx integer word) +// 011111 - 1011111110 - 1 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0 00 000000 0 01 00 1 0 1 # mfstgpr (mftgpr single) +// 011111 - 1011111111 - 1 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 00 000000 0 01 00 1 0 1 # mftgpr (mftgpr double) +assign ex0_movedp_instr = lq_au_ex0_instr[20] & (lq_au_ex0_instr[21:24] == 4'b0001) & (lq_au_ex0_instr[26:30] == 5'b00011); +assign ex0_mftgpr_instr = (lq_au_ex0_instr[21:29] == 9'b101111111) | (lq_au_ex0_instr[21:30] == 10'b1011011101); +assign au_lq_ex0_mftgpr = (lq_au_ex0_instr[0:5] == 6'b011111) & (ex0_movedp_instr | ex0_mftgpr_instr); + +// EX1 +assign pri_ex1[0:5] = lq_au_ex1_instr[0:5]; +assign sec_ex1[20:31] = lq_au_ex1_instr[20:31]; + +// update # of inputs and outputs .i xx .o xx +// run "espvhdlexpand iuq_axu_fu_dec.vhdl > iuq_axu_fu_dec_new.vhdl" to regenerate logic below table +// + +//@@ ESPRESSO TABLE START @@ +// ################################################################################################## +// .i 18 +// .o 32 +// .ilb pri_ex1(0) pri_ex1(1) pri_ex1(2) pri_ex1(3) pri_ex1(4) pri_ex1(5) +// sec_ex1(20) sec_ex1(21) sec_ex1(22) sec_ex1(23) sec_ex1(24) sec_ex1(25) sec_ex1(26) sec_ex1(27) sec_ex1(28) sec_ex1(29) sec_ex1(30) sec_ex1(31) +// .ob isfu_dec_ex1 tv av bv cv +// bubble3 prebubble1 +// ld_st_ex1 st_ex1 indexed update_form forcealign single_precision_ldst int_word_ldst sign_ext_ldst ldst_extpid io_port io_port_ext +// size(0) size(1) size(2) size(3) size(4) size(5) +// cr_writer mffgpr mftgpr fdiv_ex1 +// fsqrt_ex1 only_from_ucode final_fmul_uc only_graphics_mode +// .type fd +//# +//# +// ################################################################################################################### +//# s +//# i +//# n +//# g o +//# l n +//# e l +//# | o y +//# p n | +//# r i s l f g +//# e n i y i r +//# u c t g l i | n a +//# p p f i | n d o f a p +//# r d o s w | s | c r l h +//# e l a r i o e t p LD/ST r o | i +//# b b d i t c o r x | io size m f c +//# u u n e e n d t e or in w mm | m s +//# b b o s d a | | | x |t bytes r ff f u u | +//#pri_ex1 sec_ex1 i b b r t e f l l l l t p| 1to16 i ft fs c l m +//# s l l o x o i d d d p oe pwrs t gg dq o | o +//#000000 2 2222222223 3 F T A B C e e s r e r g s s s i rx oftwo e pp ir d u d +//#012345 0 1234567890 1 U V V V V 3 1 t e d m n t t t d tt 012345 r rr vt e c e +// ######### ############################################################################################################### + +// 011111 1 0000000011 0 1 1 0 0 0 0 0 1 0 1 0 0 0 1 0 0 11 000000 0 10 00 0 0 0 # mfdpx (DITC to FPR) +// 011111 1 0000000011 1 1 1 0 0 0 0 0 1 0 1 0 0 0 1 0 0 11 000000 1 10 00 0 0 0 # mfdpx. (DITC to FPR) + +// 011111 1 0000100011 0 1 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 10 000000 0 10 00 0 0 0 # mfdp (DITC to FPR) +// 011111 1 0000100011 1 1 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 10 000000 1 10 00 0 0 0 # mfdp. (DITC to FPR) + +// 011111 1 0001000011 0 1 0 1 0 0 0 0 1 1 1 0 0 0 1 0 0 11 000000 0 01 00 0 0 0 # mtdpx (DITC from FPR) +// 011111 1 0001000011 1 1 0 1 0 0 0 0 1 1 1 0 0 0 1 0 0 11 000000 1 01 00 0 0 0 # mtdpx. (DITC from FPR) + +// 011111 1 0001100011 0 1 0 1 0 0 0 0 1 1 0 0 0 0 1 0 0 10 000000 0 01 00 0 0 0 # mtdp (DITC from FPR) +// 011111 1 0001100011 1 1 0 1 0 0 0 0 1 1 0 0 0 0 1 0 0 10 000000 1 01 00 0 0 0 # mtdp. (DITC from FPR) + +// 011111 - 01-------- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 100000---- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 10000100-- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 100001010- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 1000010110 - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 1000010111 - 1 1 0 0 0 0 0 1 0 1 0 0 1 0 0 0 00 000100 0 00 00 0 0 0 # lfsx +// 011111 - 1000011--- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// +// 011111 - 100010---- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 10001100-- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 100011010- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 1000110110 - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 1000110111 - 1 1 0 0 0 0 0 1 0 1 1 0 1 0 0 0 00 000100 0 00 00 0 0 0 # lfsux +// 011111 - 1000111--- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 100100---- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 10010100-- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 100101010- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 1001010110 - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 1001010111 - 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 00 001000 0 00 00 0 0 0 # lfdx + +// 011111 - 10010110-- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 100101110- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 1001011110 - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 1001011111 - 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 1 00 001000 0 00 00 0 0 0 # lfdepx +// 011111 - 100110---- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 10011100-- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 100111010- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 1001110110 - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 1001110111 - 1 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 00 001000 0 00 00 0 0 0 # lfdux + +// 011111 - 1001111100 - 1 1 0 0 0 0 0 1 0 1 0 0 0 1 1 0 00 000000 0 10 00 1 0 1 # mfifgpr (mffgpr for lfiwax) +// 011111 - 1001111101 - 1 1 0 0 0 0 0 1 0 1 0 0 0 1 0 0 00 000000 0 10 00 1 0 1 # mfixfgpr (mffgpr for lfiwzx) + +// 011111 - 1001111110 - 1 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 00 000000 0 10 00 1 0 1 # mfsfgpr (mffgpr for lfs, lfsu single) +// 011111 - 1001111111 - 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 00 000000 0 10 00 1 0 1 # mffgpr (mffgpr for lfd, lfdu double) + +// 011111 - 101000---- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 10100100-- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 101001010- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 1010010110 - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 1010010111 - 1 0 1 0 0 0 0 1 1 1 0 0 1 0 0 0 00 000100 0 00 00 0 0 0 # stfsx +// 011111 - 1010011--- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// +// 011111 - 101010---- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 10101100-- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 101011010- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 1010110110 - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 1010110111 - 1 0 1 0 0 0 0 1 1 1 1 0 1 0 0 0 00 000100 0 00 00 0 0 0 # stfsux +// 011111 - 1010111--- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// +// 011111 - 101100---- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 10110100-- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 101101010- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 1011010110 - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 1011010111 - 1 0 1 0 0 0 0 1 1 1 0 0 0 0 0 0 00 001000 0 00 00 0 0 0 # stfdx +// 011111 - 10110110-- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 1011011100 - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 1011011101 - 1 0 0 1 0 0 0 1 1 0 0 0 0 1 0 0 00 000000 0 01 00 1 0 1 # mfitgpr (mftgpr for stfiwx integer word) +// 011111 - 1011011110 - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 1011011111 - 1 0 1 0 0 0 0 1 1 1 0 0 0 0 0 1 00 001000 0 00 00 0 0 0 # stfdepx + +// 011111 - 101110---- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 10111100-- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 101111010- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 1011110110 - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 1011110111 - 1 0 1 0 0 0 0 1 1 1 1 0 0 0 0 0 00 001000 0 00 00 0 0 0 # stfdux + +// 011111 - 1011111110 - 1 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0 00 000000 0 01 00 1 0 1 # mfstgpr (mftgpr single) +// 011111 - 1011111111 - 1 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 00 000000 0 01 00 1 0 1 # mftgpr (mftgpr double) + +// 011111 - 110000---- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 11000100-- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 110001010- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 1100010110 - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +//#011111 - 1100010111 - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 # lfdpx (ucoded) +// 011111 - 1100011--- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 11001----- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + +// 011111 - 110100---- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 11010100-- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 110101010- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 1101010110 - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 1101010111 - 1 1 0 0 0 0 0 1 0 1 0 0 0 1 1 0 00 000100 0 00 00 0 0 0 # lfiwax +// 011111 - 1101011--- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 1101110111 - 1 1 0 0 0 0 0 1 0 1 0 0 0 1 0 0 00 000100 0 00 00 0 0 0 # lfiwzx + +// 011111 - 111000---- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 11100100-- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 111001010- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 1110010110 - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +//#011111 - 1110010111 - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 # stfdpx (ucoded) +// 011111 - 1110011--- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 11101----- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 111100---- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 11110100-- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 111101010- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 1111010110 - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 1111010111 - 1 0 1 0 0 0 0 1 1 1 0 0 0 1 0 0 00 000100 0 00 00 0 0 0 # stfiwx +// 011111 - 1111011--- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 +// 011111 - 11111----- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + +// 10---- - ---------- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + +// 110000 - ---------- - 1 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 00 000100 0 00 00 0 0 0 # lfs + +// 110001 - ---------- - 1 1 0 0 0 0 0 1 0 0 1 0 1 0 0 0 00 000100 0 00 00 0 0 0 # lfsu + +// 110010 - ---------- - 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 00 001000 0 00 00 0 0 0 # lfd +// 110011 - ---------- - 1 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 00 001000 0 00 00 0 0 0 # lfdu +// 110100 - ---------- - 1 0 1 0 0 0 0 1 1 0 0 0 1 0 0 0 00 000100 0 00 00 0 0 0 # stfs + +// 110101 - ---------- - 1 0 1 0 0 0 0 1 1 0 1 0 1 0 0 0 00 000100 0 00 00 0 0 0 # stfsu +// +// 110110 - ---------- - 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 00 001000 0 00 00 0 0 0 # stfd +// +// 110111 - ---------- - 1 0 1 0 0 0 0 1 1 0 1 0 0 0 0 0 00 001000 0 00 00 0 0 0 # stfdu +// +// 111000 - ---------- - 0 - - - - - - 0 0 - 0 - - - - 0 00 ------ - 00 00 0 0 0 + +// ####################################################################### +// .e +//@@ ESPRESSO TABLE END @@ + +//@@ ESPRESSO LOGIC START @@ +// logic generated on: Mon Mar 16 09:28:21 2009 +assign isfu_dec_ex1 = ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & + pri_ex1[4] & pri_ex1[5] & sec_ex1[20] & (~sec_ex1[21]) & + (~sec_ex1[22]) & (~sec_ex1[23]) & (~sec_ex1[26]) & (~sec_ex1[27]) & + (~sec_ex1[28]) & sec_ex1[29] & sec_ex1[30]) | ((~pri_ex1[0]) & + pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & + sec_ex1[21] & (~sec_ex1[22]) & (~sec_ex1[23]) & sec_ex1[24] & sec_ex1[25] & + sec_ex1[26] & sec_ex1[27] & sec_ex1[28]) | ((~pri_ex1[0]) & pri_ex1[1] & + pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[21] & (~sec_ex1[22]) & + sec_ex1[23] & sec_ex1[24] & (~sec_ex1[25]) & sec_ex1[26] & sec_ex1[27] & + sec_ex1[28] & sec_ex1[30]) | ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & + pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[21] & (~sec_ex1[22]) & + sec_ex1[24] & sec_ex1[25] & sec_ex1[26] & sec_ex1[27] & sec_ex1[28] & sec_ex1[29]) | + ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & + sec_ex1[21] & sec_ex1[24] & (~sec_ex1[25]) & sec_ex1[26] & (~sec_ex1[27]) & sec_ex1[28] & + sec_ex1[29] & sec_ex1[30]) | ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & + pri_ex1[4] & pri_ex1[5] & sec_ex1[21] & (~sec_ex1[22]) & sec_ex1[26] & (~sec_ex1[27]) & + sec_ex1[28] & sec_ex1[29] & sec_ex1[30]) | ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & + pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[21] & (~sec_ex1[23]) & sec_ex1[24] & + sec_ex1[26] & (~sec_ex1[27]) & sec_ex1[28] & sec_ex1[29] & sec_ex1[30]) | ((~pri_ex1[0]) & + pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[21] & (~sec_ex1[22]) & + sec_ex1[24] & sec_ex1[26] & sec_ex1[28] & sec_ex1[29] & sec_ex1[30]) | (pri_ex1[0] & pri_ex1[1] & (~pri_ex1[2])); + +assign tv = ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & + sec_ex1[22] & (~sec_ex1[23]) & sec_ex1[24] & sec_ex1[26] & (~sec_ex1[27]) & sec_ex1[28] & + sec_ex1[29] & sec_ex1[30]) | ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & + pri_ex1[5] & sec_ex1[20] & (~sec_ex1[23]) & (~sec_ex1[24]) & (~sec_ex1[26]) & (~sec_ex1[27]) & + (~sec_ex1[28]) & sec_ex1[29] & sec_ex1[30]) | ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & + pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[21] & (~sec_ex1[22]) & (~sec_ex1[23]) & sec_ex1[28]) | + (pri_ex1[0] & (~pri_ex1[2]) & (~pri_ex1[3])); + +assign av = ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[20] & + (~sec_ex1[22]) & (~sec_ex1[23]) & sec_ex1[24] & (~sec_ex1[26]) & (~sec_ex1[27]) & (~sec_ex1[28]) & + sec_ex1[29] & sec_ex1[30]) | ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & + pri_ex1[4] & pri_ex1[5] & sec_ex1[21] & sec_ex1[23] & sec_ex1[24] & (~sec_ex1[25]) & sec_ex1[29]) | + ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[21] & + (~sec_ex1[22]) & sec_ex1[23] & (~sec_ex1[27])) | (pri_ex1[0] & (~pri_ex1[2]) & pri_ex1[3]); + +assign bv = ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[21] & + (~sec_ex1[25]) & (~sec_ex1[29])) | ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & + pri_ex1[4] & pri_ex1[5] & sec_ex1[21] & sec_ex1[23] & sec_ex1[25] & sec_ex1[27] & sec_ex1[28] & sec_ex1[29]); + +assign cv = 1'b0; + +assign bubble3 = 1'b0; + +assign prebubble1 = 1'b0; + +assign ld_st_ex1 = ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[20] & + (~sec_ex1[21]) & (~sec_ex1[22]) & (~sec_ex1[23]) & (~sec_ex1[26]) & (~sec_ex1[27]) & + (~sec_ex1[28]) & sec_ex1[29] & sec_ex1[30]) | ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & + pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[21] & (~sec_ex1[22]) & (~sec_ex1[23]) & + sec_ex1[24] & sec_ex1[25] & sec_ex1[26] & sec_ex1[27] & sec_ex1[28]) | ((~pri_ex1[0]) & + pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[21] & + (~sec_ex1[22]) & sec_ex1[23] & sec_ex1[24] & (~sec_ex1[25]) & sec_ex1[26] & sec_ex1[27] & + sec_ex1[28] & sec_ex1[30]) | ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & + pri_ex1[4] & pri_ex1[5] & sec_ex1[21] & (~sec_ex1[22]) & sec_ex1[24] & sec_ex1[25] & sec_ex1[26] & + sec_ex1[27] & sec_ex1[28] & sec_ex1[29]) | ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & + pri_ex1[4] & pri_ex1[5] & sec_ex1[21] & sec_ex1[24] & (~sec_ex1[25]) & sec_ex1[26] & (~sec_ex1[27]) & + sec_ex1[28] & sec_ex1[29] & sec_ex1[30]) | ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & + pri_ex1[4] & pri_ex1[5] & sec_ex1[21] & (~sec_ex1[22]) & sec_ex1[26] & (~sec_ex1[27]) & sec_ex1[28] & + sec_ex1[29] & sec_ex1[30]) | ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & + pri_ex1[5] & sec_ex1[21] & (~sec_ex1[23]) & sec_ex1[24] & sec_ex1[26] & (~sec_ex1[27]) & sec_ex1[28] & + sec_ex1[29] & sec_ex1[30]) | ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & + pri_ex1[5] & sec_ex1[21] & (~sec_ex1[22]) & sec_ex1[24] & sec_ex1[26] & sec_ex1[28] & sec_ex1[29] & + sec_ex1[30]) | (pri_ex1[0] & pri_ex1[1] & (~pri_ex1[2])); + +assign st_ex1 = ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[20] & + (~sec_ex1[21]) & (~sec_ex1[22]) & (~sec_ex1[23]) & sec_ex1[24] & (~sec_ex1[26]) & (~sec_ex1[27]) & + (~sec_ex1[28]) & sec_ex1[29] & sec_ex1[30]) | ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & + pri_ex1[4] & pri_ex1[5] & sec_ex1[21] & (~sec_ex1[22]) & sec_ex1[23] & sec_ex1[24] & sec_ex1[25] & + sec_ex1[26] & sec_ex1[27] & sec_ex1[28] & sec_ex1[29]) | ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & + pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[21] & (~sec_ex1[22]) & sec_ex1[23] & sec_ex1[24] & + (~sec_ex1[25]) & sec_ex1[26] & sec_ex1[27] & sec_ex1[28] & sec_ex1[30]) | ((~pri_ex1[0]) & pri_ex1[1] & + pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[21] & sec_ex1[23] & sec_ex1[24] & + (~sec_ex1[25]) & sec_ex1[26] & (~sec_ex1[27]) & sec_ex1[28] & sec_ex1[29] & sec_ex1[30]) | ((~pri_ex1[0]) & + pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[21] & (~sec_ex1[22]) & + sec_ex1[23] & sec_ex1[26] & (~sec_ex1[27]) & sec_ex1[28] & sec_ex1[29] & sec_ex1[30]) | (pri_ex1[0] & + pri_ex1[1] & (~pri_ex1[2]) & pri_ex1[3]); + +assign indexed = ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[21] & + (~sec_ex1[25]) & sec_ex1[27] & sec_ex1[29]) | ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & + pri_ex1[4] & pri_ex1[5] & sec_ex1[21] & (~sec_ex1[22]) & (~sec_ex1[27])) | ((~pri_ex1[0]) & pri_ex1[1] & + pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[21] & sec_ex1[24] & sec_ex1[26] & + (~sec_ex1[27]) & sec_ex1[28] & sec_ex1[29] & sec_ex1[30]) | ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & + pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[20] & (~sec_ex1[23]) & (~sec_ex1[25]) & (~sec_ex1[26]) & + (~sec_ex1[27]) & (~sec_ex1[28]) & sec_ex1[29] & sec_ex1[30]) | ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & + pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[21] & (~sec_ex1[22]) & (~sec_ex1[23]) & sec_ex1[28] & (~sec_ex1[29])); + +assign update_form = ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[21] & + (~sec_ex1[22]) & sec_ex1[25] & sec_ex1[26] & (~sec_ex1[27]) & sec_ex1[28] & sec_ex1[29] & + sec_ex1[30]) | (pri_ex1[0] & pri_ex1[1] & (~pri_ex1[2]) & pri_ex1[5]); + +assign forcealign = 1'b0; + +assign single_precision_ldst = ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[21] & + (~sec_ex1[22]) & sec_ex1[28] & sec_ex1[29] & (~sec_ex1[30])) | ((~pri_ex1[0]) & pri_ex1[1] & + pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[21] & (~sec_ex1[22]) & + (~sec_ex1[24])) | (pri_ex1[0] & (~pri_ex1[2]) & (~pri_ex1[4])); + +assign int_word_ldst = ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[20] & + (~sec_ex1[22]) & (~sec_ex1[23]) & (~sec_ex1[26]) & (~sec_ex1[27]) & (~sec_ex1[28]) & sec_ex1[29] & + sec_ex1[30]) | ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & + sec_ex1[22] & sec_ex1[24] & sec_ex1[26] & (~sec_ex1[27]) & sec_ex1[28] & sec_ex1[29] & sec_ex1[30]) | + ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[21] & + (~sec_ex1[22]) & (~sec_ex1[23]) & sec_ex1[28] & (~sec_ex1[29])) | ((~pri_ex1[0]) & pri_ex1[1] & + pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[21] & (~sec_ex1[25]) & (~sec_ex1[29])); + +assign sign_ext_ldst = ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[21] & + (~sec_ex1[22]) & (~sec_ex1[23]) & sec_ex1[28] & (~sec_ex1[29]) & (~sec_ex1[30])) | + ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[22] & + (~sec_ex1[23]) & sec_ex1[24] & (~sec_ex1[25])); + +assign ldst_extpid = ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[21] & + (~sec_ex1[22]) & sec_ex1[24] & (~sec_ex1[25]) & sec_ex1[26] & sec_ex1[27] & sec_ex1[28] & + sec_ex1[29] & sec_ex1[30]); + +assign io_port = ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[20] & + (~sec_ex1[21]) & (~sec_ex1[22]) & (~sec_ex1[23]) & (~sec_ex1[26]) & (~sec_ex1[27]) & + (~sec_ex1[28]) & sec_ex1[29] & sec_ex1[30]); + +assign io_port_ext = ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[20] & + (~sec_ex1[21]) & (~sec_ex1[22]) & (~sec_ex1[23]) & (~sec_ex1[25]) & (~sec_ex1[26]) & + (~sec_ex1[27]) & (~sec_ex1[28]) & sec_ex1[29] & sec_ex1[30]); + +assign size[0] = 1'b0; + +assign size[1] = 1'b0; + +assign size[2] = ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[21] & + (~sec_ex1[25]) & sec_ex1[27] & sec_ex1[29]) | ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & + pri_ex1[4] & pri_ex1[5] & sec_ex1[21] & (~sec_ex1[22]) & sec_ex1[24] & (~sec_ex1[27])) | + (pri_ex1[0] & (~pri_ex1[2]) & pri_ex1[4]); + +assign size[3] = ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[22] & + sec_ex1[24] & sec_ex1[26] & (~sec_ex1[27]) & sec_ex1[28] & sec_ex1[29] & sec_ex1[30]) | ((~pri_ex1[0]) & + pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[21] & (~sec_ex1[22]) & + (~sec_ex1[24])) | (pri_ex1[0] & (~pri_ex1[2]) & (~pri_ex1[4])); + +assign size[4] = 1'b0; + +assign size[5] = 1'b0; + +assign cr_writer = ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[20] & + (~sec_ex1[22]) & (~sec_ex1[23]) & (~sec_ex1[26]) & (~sec_ex1[27]) & (~sec_ex1[28]) & sec_ex1[29] & + sec_ex1[30] & sec_ex1[31]); + +assign mffgpr = ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[20] & (~sec_ex1[21]) & + (~sec_ex1[22]) & (~sec_ex1[23]) & (~sec_ex1[24]) & (~sec_ex1[26]) & (~sec_ex1[27]) & (~sec_ex1[28]) & + sec_ex1[29] & sec_ex1[30]) | ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & + pri_ex1[5] & sec_ex1[21] & (~sec_ex1[22]) & (~sec_ex1[23]) & sec_ex1[24] & sec_ex1[25] & sec_ex1[26] & + sec_ex1[27] & sec_ex1[28]); + +assign mftgpr = ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[21] & + (~sec_ex1[22]) & sec_ex1[23] & sec_ex1[24] & (~sec_ex1[25]) & sec_ex1[26] & sec_ex1[27] & sec_ex1[28] & + (~sec_ex1[29]) & sec_ex1[30]) | ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & + pri_ex1[5] & sec_ex1[21] & (~sec_ex1[22]) & sec_ex1[23] & sec_ex1[24] & sec_ex1[25] & sec_ex1[26] & + sec_ex1[27] & sec_ex1[28] & sec_ex1[29]) | ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & + pri_ex1[4] & pri_ex1[5] & sec_ex1[20] & (~sec_ex1[21]) & (~sec_ex1[22]) & (~sec_ex1[23]) & sec_ex1[24] & + (~sec_ex1[26]) & (~sec_ex1[27]) & (~sec_ex1[28]) & sec_ex1[29] & sec_ex1[30]); + +assign fdiv_ex1 = 1'b0; + +assign fsqrt_ex1 = 1'b0; + +assign only_from_ucode = ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[21] & + (~sec_ex1[22]) & sec_ex1[23] & sec_ex1[24] & (~sec_ex1[25]) & sec_ex1[26] & sec_ex1[27] & sec_ex1[28] & + (~sec_ex1[29]) & sec_ex1[30]) | ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & + pri_ex1[5] & sec_ex1[21] & (~sec_ex1[22]) & (~sec_ex1[23]) & sec_ex1[24] & sec_ex1[25] & sec_ex1[26] & + sec_ex1[27] & sec_ex1[28]) | ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & + sec_ex1[21] & (~sec_ex1[22]) & sec_ex1[24] & sec_ex1[25] & sec_ex1[26] & sec_ex1[27] & sec_ex1[28] & sec_ex1[29]); + +assign final_fmul_uc = 1'b0; + +assign only_graphics_mode = ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & sec_ex1[21] & + (~sec_ex1[22]) & sec_ex1[23] & sec_ex1[24] & (~sec_ex1[25]) & sec_ex1[26] & sec_ex1[27] & sec_ex1[28] & + (~sec_ex1[29]) & sec_ex1[30]) | ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & + pri_ex1[5] & sec_ex1[21] & (~sec_ex1[22]) & (~sec_ex1[23]) & sec_ex1[24] & sec_ex1[25] & sec_ex1[26] & + sec_ex1[27] & sec_ex1[28]) | ((~pri_ex1[0]) & pri_ex1[1] & pri_ex1[2] & pri_ex1[3] & pri_ex1[4] & pri_ex1[5] & + sec_ex1[21] & (~sec_ex1[22]) & sec_ex1[24] & sec_ex1[25] & sec_ex1[26] & sec_ex1[27] & sec_ex1[28] & sec_ex1[29]); + +//@@ ESPRESSO LOGIC END @@ + +generate + if (`THREADS_POOL_ENC == 0) begin : tid1 + wire [0:`THREADS_POOL_ENC] tid_enc; + + assign tid_enc = tidn; + assign ldst_tag = {single_precision_ldst, int_word_ldst, sign_ext_ldst, lq_au_ex1_t3_p}; // for lfiwax + assign unused = tiup | |lq_au_ex0_instr[6:19] | lq_au_ex0_instr[31] | |lq_au_ex1_instr[11:15] | isfu_dec_ex1 | + tv | av | bv | cv | bubble3 | prebubble1 | io_port_ext | cr_writer | fdiv_ex1 | fsqrt_ex1 | + only_from_ucode | final_fmul_uc | only_graphics_mode | |iu_au_ex1_ucode_ext | |ldst_tag_addr | + |tid_enc | |lq_au_ex1_tid; + end +endgenerate + +generate + if (`THREADS_POOL_ENC > 0) begin : tidMulti + reg [0:`THREADS_POOL_ENC] tid_enc; + always @(*) begin: tidEnc + reg [0:`THREADS_POOL_ENC-1] enc; + + //(* analysis_not_referenced="true" *) + + reg [0:31] tidVar; + enc = {`THREADS_POOL_ENC{1'b0}}; + tid_enc[`THREADS_POOL_ENC:`THREADS_POOL_ENC] = tidn; + for (tidVar=0; tidVar<`THREADS; tidVar=tidVar+1) begin + enc = (tidVar[32-`THREADS_POOL_ENC:31] & {`THREADS_POOL_ENC{lq_au_ex1_tid[tidVar]}}) | enc; + end + tid_enc[0:`THREADS_POOL_ENC-1] <= enc; + end + assign ldst_tag = {single_precision_ldst, int_word_ldst, sign_ext_ldst, lq_au_ex1_t3_p, tid_enc[0:`THREADS_POOL_ENC - 1]}; // for lfiwax + assign unused = tiup | |lq_au_ex0_instr[6:19] | lq_au_ex0_instr[31] | |lq_au_ex1_instr[11:15] | isfu_dec_ex1 | + tv | av | bv | cv | bubble3 | prebubble1 | io_port_ext | cr_writer | fdiv_ex1 | fsqrt_ex1 | + only_from_ucode | final_fmul_uc | only_graphics_mode | |iu_au_ex1_ucode_ext | |ldst_tag_addr | + tid_enc[`THREADS_POOL_ENC:`THREADS_POOL_ENC] | lq_au_ex1_tid[0]; + end +endgenerate + +assign iu_au_ex1_ucode_ext[0:2] = {3{1'b0}}; + +assign ldst_tag_addr = ~mftgpr ? lq_au_ex1_instr[06:10] : lq_au_ex1_instr[16:20]; + +assign au_lq_ex1_ldst_v = ld_st_ex1 & lq_au_ex1_vld; +assign au_lq_ex1_st_v = st_ex1; + +assign au_lq_ex1_instr_type = 3'b001; // 0=AP,1=Vec,2=FP + +assign au_lq_ex1_mffgpr = mffgpr; // and ld_st_ex1; -- This is for LVSL, and also misaligned loads +assign au_lq_ex1_mftgpr = mftgpr; // and ld_st_ex1; -- This is for misaligned stores + +assign au_lq_ex1_movedp = io_port & ld_st_ex1; + +assign au_lq_ex1_ldst_size = size[0:5]; +assign au_lq_ex1_ldst_tag = ldst_tag; +assign au_lq_ex1_ldst_dimm = lq_au_ex1_instr[16:31]; +assign au_lq_ex1_ldst_indexed = indexed; +assign au_lq_ex1_ldst_update = update_form; // and ld_st_ex1; +assign au_lq_ex1_ldst_forcealign = forcealign; +assign au_lq_ex1_ldst_forceexcept = 1'b0; + +assign au_lq_ex1_ldst_priv = ldst_extpid; + +endmodule diff --git a/dev/verilog/work/lq_byp.v b/dev/verilog/work/lq_byp.v new file mode 100755 index 0000000..ba097f5 --- /dev/null +++ b/dev/verilog/work/lq_byp.v @@ -0,0 +1,1903 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: LQ SFX Bypass Unit +// +//***************************************************************************** + +`include "tri_a2o.vh" + + + +module lq_byp( + nclk, + vdd, + gnd, + d_mode_dc, + delay_lclkr_dc, + mpw1_dc_b, + mpw2_dc_b, + func_sl_force, + func_sl_thold_0_b, + func_slp_sl_force, + func_slp_sl_thold_0_b, + sg_0, + scan_in, + scan_out, + xu0_lq_ex3_act, + xu0_lq_ex3_abort, + xu0_lq_ex3_rt, + xu0_lq_ex4_rt, + xu0_lq_ex6_act, + xu0_lq_ex6_rt, + xu1_lq_ex3_act, + xu1_lq_ex3_abort, + xu1_lq_ex3_rt, + lq_xu_ex5_rt, + dec_byp_ex0_stg_act, + dec_byp_ex1_stg_act, + dec_byp_ex5_stg_act, + dec_byp_ex6_stg_act, + dec_byp_ex7_stg_act, + dec_byp_ex1_s1_vld, + dec_byp_ex1_s2_vld, + dec_byp_ex1_use_imm, + dec_byp_ex1_imm, + dec_byp_ex1_rs1_zero, + byp_ex2_req_aborted, + byp_dec_ex1_s1_abort, + byp_dec_ex1_s2_abort, + ctl_lsq_ex4_xu1_data, + ctl_lsq_ex6_ldh_dacrw, + lsq_ctl_ex5_fwd_val, + lsq_ctl_ex5_fwd_data, + lsq_ctl_rel2_data, + dcc_byp_rel2_stg_act, + dcc_byp_rel3_stg_act, + dcc_byp_ram_act, + dcc_byp_ex4_moveOp_val, + dcc_byp_stq6_moveOp_val, + dcc_byp_ex4_move_data, + dcc_byp_ex5_lq_req_abort, + dcc_byp_ex5_byte_mask, + dcc_byp_ex6_thrd_id, + dcc_byp_ex6_dvc1_en, + dcc_byp_ex6_dvc2_en, + dcc_byp_ex6_dacr_cmpr, + dat_ctl_ex5_load_data, + dat_ctl_stq6_axu_data, + dcc_byp_ram_sel, + byp_dir_ex2_rs1, + byp_dir_ex2_rs2, + spr_byp_spr_dvc1_dbg, + spr_byp_spr_dvc2_dbg, + spr_byp_spr_dbcr2_dvc1m, + spr_byp_spr_dbcr2_dvc1be, + spr_byp_spr_dbcr2_dvc2m, + spr_byp_spr_dbcr2_dvc2be, + rv_lq_ex0_s1_xu0_sel, + rv_lq_ex0_s2_xu0_sel, + rv_lq_ex0_s1_xu1_sel, + rv_lq_ex0_s2_xu1_sel, + rv_lq_ex0_s1_lq_sel, + rv_lq_ex0_s2_lq_sel, + rv_lq_ex0_s1_rel_sel, + rv_lq_ex0_s2_rel_sel, + lq_pc_ram_data, + rv_lq_gpr_ex1_r0d, + rv_lq_gpr_ex1_r1d, + lq_rv_gpr_ex6_wd, + lq_rv_gpr_rel_wd, + lq_xu_gpr_rel_wd, + lq_rv_ex2_s1_abort, + lq_rv_ex2_s2_abort +); + +//------------------------------------------------------------------- +// Generics +//------------------------------------------------------------------- +//parameter EXPAND_TYPE = 2; +//parameter THREADS = 2; +//parameter `GPR_WIDTH_ENC = 6; +//parameter `STQ_DATA_SIZE = 64; // 64 or 128 Bit store data sizes supported +//parameter `LQ_LOAD_PIPE_START = 4; +//parameter `LQ_LOAD_PIPE_END = 8; +//parameter `LQ_REL_PIPE_START = 2; +//parameter `LQ_REL_PIPE_END = 4; +//parameter XU0_PIPE_START = 2; +//parameter XU0_PIPE_END = 12; +//parameter XU1_PIPE_START = 2; +//parameter XU1_PIPE_END = 7; + +//------------------------------------------------------------------- +// Clocks & Power +//------------------------------------------------------------------- + + +inout vdd; + + +inout gnd; + +(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) + +input [0:`NCLK_WIDTH-1] nclk; + +//------------------------------------------------------------------- +// Pervasive +//------------------------------------------------------------------- +input d_mode_dc; +input delay_lclkr_dc; +input mpw1_dc_b; +input mpw2_dc_b; +input func_sl_force; +input func_sl_thold_0_b; +input func_slp_sl_force; +input func_slp_sl_thold_0_b; +input sg_0; + +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + +input scan_in; + +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + +output scan_out; + +//------------------------------------------------------------------- +// Interface with XU +//------------------------------------------------------------------- +input xu0_lq_ex3_act; +input xu0_lq_ex3_abort; +input [64-(2**`GPR_WIDTH_ENC):63] xu0_lq_ex3_rt; +input [64-(2**`GPR_WIDTH_ENC):63] xu0_lq_ex4_rt; +input xu0_lq_ex6_act; +input [64-(2**`GPR_WIDTH_ENC):63] xu0_lq_ex6_rt; +input xu1_lq_ex3_act; +input xu1_lq_ex3_abort; +input [64-(2**`GPR_WIDTH_ENC):63] xu1_lq_ex3_rt; +output [(128-`STQ_DATA_SIZE):127] lq_xu_ex5_rt; + +//------------------------------------------------------------------- +// Interface with DEC +//------------------------------------------------------------------- +input dec_byp_ex0_stg_act; +input dec_byp_ex1_stg_act; +input dec_byp_ex5_stg_act; +input dec_byp_ex6_stg_act; +input dec_byp_ex7_stg_act; +input dec_byp_ex1_s1_vld; +input dec_byp_ex1_s2_vld; +input dec_byp_ex1_use_imm; +input [64-(2**`GPR_WIDTH_ENC):63] dec_byp_ex1_imm; +input dec_byp_ex1_rs1_zero; +output byp_ex2_req_aborted; +output byp_dec_ex1_s1_abort; +output byp_dec_ex1_s2_abort; + +//------------------------------------------------------------------- +// Interface with LQ Pipe +//------------------------------------------------------------------- +// Load Pipe +output [64-(2**`GPR_WIDTH_ENC):63] ctl_lsq_ex4_xu1_data; +output [0:3] ctl_lsq_ex6_ldh_dacrw; +input lsq_ctl_ex5_fwd_val; +input [(128-`STQ_DATA_SIZE):127] lsq_ctl_ex5_fwd_data; +input [0:127] lsq_ctl_rel2_data; +input dcc_byp_rel2_stg_act; +input dcc_byp_rel3_stg_act; +input dcc_byp_ram_act; +input dcc_byp_ex4_moveOp_val; +input dcc_byp_stq6_moveOp_val; +input [64-(2**`GPR_WIDTH_ENC):63] dcc_byp_ex4_move_data; +input dcc_byp_ex5_lq_req_abort; +input [0:((2**`GPR_WIDTH_ENC)/8)-1] dcc_byp_ex5_byte_mask; +input [0:`THREADS-1] dcc_byp_ex6_thrd_id; +input dcc_byp_ex6_dvc1_en; +input dcc_byp_ex6_dvc2_en; +input [0:3] dcc_byp_ex6_dacr_cmpr; +input [(128-`STQ_DATA_SIZE):127] dat_ctl_ex5_load_data; +input [(128-`STQ_DATA_SIZE):127] dat_ctl_stq6_axu_data; +input dcc_byp_ram_sel; + +output [64-(2**`GPR_WIDTH_ENC):63] byp_dir_ex2_rs1; +output [64-(2**`GPR_WIDTH_ENC):63] byp_dir_ex2_rs2; + +//------------------------------------------------------------------- +// Interface with SPR's +//------------------------------------------------------------------- +input [64-(2**`GPR_WIDTH_ENC):63] spr_byp_spr_dvc1_dbg; +input [64-(2**`GPR_WIDTH_ENC):63] spr_byp_spr_dvc2_dbg; +input [0:(`THREADS*2)-1] spr_byp_spr_dbcr2_dvc1m; +input [0:(`THREADS*8)-1] spr_byp_spr_dbcr2_dvc1be; +input [0:(`THREADS*2)-1] spr_byp_spr_dbcr2_dvc2m; +input [0:(`THREADS*8)-1] spr_byp_spr_dbcr2_dvc2be; + +//------------------------------------------------------------------- +// Interface with Bypass Controller +//------------------------------------------------------------------- +input [2:12] rv_lq_ex0_s1_xu0_sel; +input [2:12] rv_lq_ex0_s2_xu0_sel; +input [2:7] rv_lq_ex0_s1_xu1_sel; +input [2:7] rv_lq_ex0_s2_xu1_sel; +input [4:8] rv_lq_ex0_s1_lq_sel; +input [4:8] rv_lq_ex0_s2_lq_sel; +input [2:3] rv_lq_ex0_s1_rel_sel; +input [2:3] rv_lq_ex0_s2_rel_sel; + +//------------------------------------------------------------------- +// Interface with PERVASIVE +//------------------------------------------------------------------- +output [64-(2**`GPR_WIDTH_ENC):63] lq_pc_ram_data; + +//------------------------------------------------------------------- +// Interface with GPR +//------------------------------------------------------------------- +input [64-(2**`GPR_WIDTH_ENC):63] rv_lq_gpr_ex1_r0d; +input [64-(2**`GPR_WIDTH_ENC):63] rv_lq_gpr_ex1_r1d; +output [64-(2**`GPR_WIDTH_ENC):64+(((2**`GPR_WIDTH_ENC)-1)/8)] lq_rv_gpr_ex6_wd; +output [64-(2**`GPR_WIDTH_ENC):64+(((2**`GPR_WIDTH_ENC)-1)/8)] lq_rv_gpr_rel_wd; +output [(128-`STQ_DATA_SIZE):128+((`STQ_DATA_SIZE-1)/8)] lq_xu_gpr_rel_wd; + +//------------------------------------------------------------------- +// Interface with RV +//------------------------------------------------------------------- +output lq_rv_ex2_s1_abort; +output lq_rv_ex2_s2_abort; + +//------------------------------------------------------------------- +// Signals +//------------------------------------------------------------------- +wire tiup; +wire tidn; +wire [0:4] ex1_rs1_byp_sel; +wire [1:3] ex1_rs1_abort_byp_sel; +wire [0:4] ex1_rs2_byp_sel; +wire [1:3] ex1_rs2_abort_byp_sel; +wire [64-(2**`GPR_WIDTH_ENC):63] ex3_xu0_rt; +wire [64-(2**`GPR_WIDTH_ENC):63] ex4_xu0_rt; +wire [64-(2**`GPR_WIDTH_ENC):63] ex5_xu0_rt; +wire [64-(2**`GPR_WIDTH_ENC):63] ex6_xu0_rt; +wire [64-(2**`GPR_WIDTH_ENC):63] ex7_xu0_rt; +wire [64-(2**`GPR_WIDTH_ENC):63] ex8_xu0_rt; +wire [64-(2**`GPR_WIDTH_ENC):63] ex3_xu1_rt; +wire [64-(2**`GPR_WIDTH_ENC):63] ex4_xu1_rt; +wire [64-(2**`GPR_WIDTH_ENC):63] ex5_xu1_rt; +wire [64-(2**`GPR_WIDTH_ENC):63] rel2_rel_rt; +wire ex1_s1_load_byp_val; +wire ex1_s1_load_abort_byp_val; +wire [64-(2**`GPR_WIDTH_ENC):63] ex1_s1_load_data; +wire ex1_s2_load_byp_val; +wire ex1_s2_load_abort_byp_val; +wire [64-(2**`GPR_WIDTH_ENC):63] ex1_s2_load_data; +wire ex1_s1_reload_byp_val; +wire [64-(2**`GPR_WIDTH_ENC):63] ex1_s1_reload_data; +wire ex1_s2_reload_byp_val; +wire [64-(2**`GPR_WIDTH_ENC):63] ex1_s2_reload_data; +wire ex1_s1_xu0_byp_val; +wire ex1_s1_xu0_abort_byp_val; +wire [64-(2**`GPR_WIDTH_ENC):63] ex1_s1_xu0_data; +wire ex1_s2_xu0_byp_val; +wire ex1_s2_xu0_abort_byp_val; +wire [64-(2**`GPR_WIDTH_ENC):63] ex1_s2_xu0_data; +wire ex1_s1_xu1_byp_val; +wire ex1_s1_xu1_abort_byp_val; +wire [64-(2**`GPR_WIDTH_ENC):63] ex1_s1_xu1_data; +wire ex1_s2_xu1_byp_val; +wire ex1_s2_xu1_abort_byp_val; +wire [64-(2**`GPR_WIDTH_ENC):63] ex1_s2_xu1_data; +wire ex3_xu0_stg_act; +wire ex3_xu1_stg_act; +wire ex4_move_data_sel; +wire [(128-`STQ_DATA_SIZE):127] ex5_load_move_data; +wire [(128-`STQ_DATA_SIZE):127] ex5_load_data; +wire [64-(2**`GPR_WIDTH_ENC):63] ex5_fx_ld_data; +wire [0:((2**`GPR_WIDTH_ENC)-1)/8] ex5_fx_ld_data_par; +reg [0:1] spr_dbcr2_dvc1m; +reg [0:1] spr_dbcr2_dvc2m; +reg [8-(2**`GPR_WIDTH_ENC)/8:7] spr_dbcr2_dvc1be; +reg [8-(2**`GPR_WIDTH_ENC)/8:7] spr_dbcr2_dvc2be; +wire [0:((2**`GPR_WIDTH_ENC)/8)-1] ex6_dvc1_cmp_d; +wire [0:((2**`GPR_WIDTH_ENC)/8)-1] ex6_dvc1_cmp_q; +wire [0:((2**`GPR_WIDTH_ENC)/8)-1] ex6_dvc2_cmp_d; +wire [0:((2**`GPR_WIDTH_ENC)/8)-1] ex6_dvc2_cmp_q; +wire ex6_dvc1r_cmpr; +wire ex6_dvc2r_cmpr; +wire [0:3] ex6_dacrw; +wire [0:(`STQ_DATA_SIZE-1)/8] rel2_data_par; +wire [64-(2**`GPR_WIDTH_ENC):64+(((2**`GPR_WIDTH_ENC)-1)/8)] rel2_rv_rel_data; +wire [(128-`STQ_DATA_SIZE):128+((`STQ_DATA_SIZE-1)/8)] rel2_xu_rel_data; +wire [0:1] spr_dbcr2_dvc1m_tid[0:`THREADS-1]; +wire [0:7] spr_dbcr2_dvc1be_tid[0:`THREADS-1]; +wire [0:1] spr_dbcr2_dvc2m_tid[0:`THREADS-1]; +wire [0:7] spr_dbcr2_dvc2be_tid[0:`THREADS-1]; +wire ex5_lq_req_abort; +wire ex3_xu0_req_abort; +wire ex3_xu1_req_abort; +wire ex1_s1_load_abort; +wire ex1_s2_load_abort; +wire ex1_s1_xu0_abort; +wire ex1_s2_xu0_abort; +wire ex1_s1_xu1_abort; +wire ex1_s2_xu1_abort; +wire ex2_req_aborted; + +//------------------------------------------------------------------- +// Latches +//------------------------------------------------------------------- +wire [64-(2**`GPR_WIDTH_ENC):63] ex2_rs1_d; +wire [64-(2**`GPR_WIDTH_ENC):63] ex2_rs1_q; +wire [64-(2**`GPR_WIDTH_ENC):63] ex2_rs2_d; +wire [64-(2**`GPR_WIDTH_ENC):63] ex2_rs2_q; +wire ex1_s1_abort; +wire ex2_s1_abort_d; +wire ex2_s1_abort_q; +wire ex1_s2_abort; +wire ex2_s2_abort_d; +wire ex2_s2_abort_q; +wire [2:12] ex1_s1_xu0_sel_q; +wire [2:12] ex1_s2_xu0_sel_q; +wire [2:7] ex1_s1_xu1_sel_q; +wire [2:7] ex1_s2_xu1_sel_q; +wire [4:8] ex1_s1_lq_sel_q; +wire [4:8] ex1_s2_lq_sel_q; +wire [2:3] ex1_s1_rel_sel_q; +wire [2:3] ex1_s2_rel_sel_q; +wire [64-(2**`GPR_WIDTH_ENC):63] ex5_xu0_rt_q; +wire [64-(2**`GPR_WIDTH_ENC):63] ex6_xu0_rt_q; +wire [64-(2**`GPR_WIDTH_ENC):63] ex7_xu0_rt_d; +wire [64-(2**`GPR_WIDTH_ENC):63] ex7_xu0_rt_q; +wire [64-(2**`GPR_WIDTH_ENC):63] ex8_xu0_rt_q; +wire ex4_xu0_req_abort_d; +wire ex4_xu0_req_abort_q; +wire ex5_xu0_req_abort_d; +wire ex5_xu0_req_abort_q; +wire ex6_xu0_req_abort_d; +wire ex6_xu0_req_abort_q; +wire ex7_xu0_req_abort_d; +wire ex7_xu0_req_abort_q; +wire ex8_xu0_req_abort_d; +wire ex8_xu0_req_abort_q; +wire ex9_xu0_req_abort_d; +wire ex9_xu0_req_abort_q; +wire ex10_xu0_req_abort_d; +wire ex10_xu0_req_abort_q; +wire ex11_xu0_req_abort_d; +wire ex11_xu0_req_abort_q; +wire ex12_xu0_req_abort_d; +wire ex12_xu0_req_abort_q; +wire ex13_xu0_req_abort_d; +wire ex13_xu0_req_abort_q; +wire [64-(2**`GPR_WIDTH_ENC):63] ex4_xu1_rt_q; +wire [64-(2**`GPR_WIDTH_ENC):63] ex5_xu1_rt_q; +wire ex4_xu1_req_abort_d; +wire ex4_xu1_req_abort_q; +wire ex5_xu1_req_abort_d; +wire ex5_xu1_req_abort_q; +wire ex6_xu1_req_abort_d; +wire ex6_xu1_req_abort_q; +wire ex7_xu1_req_abort_d; +wire ex7_xu1_req_abort_q; +wire ex8_xu1_req_abort_d; +wire ex8_xu1_req_abort_q; +wire [64-(2**`GPR_WIDTH_ENC):63] rel3_rel_rt_d; +wire [64-(2**`GPR_WIDTH_ENC):63] rel3_rel_rt_q; +wire [64-(2**`GPR_WIDTH_ENC):63] rel4_rel_rt_d; +wire [64-(2**`GPR_WIDTH_ENC):63] rel4_rel_rt_q; +wire [64-(2**`GPR_WIDTH_ENC):63] ex6_fx_ld_data_d; +wire [64-(2**`GPR_WIDTH_ENC):63] ex6_fx_ld_data_q; +wire [64-(2**`GPR_WIDTH_ENC):63] ex7_fx_ld_data_d; +wire [64-(2**`GPR_WIDTH_ENC):63] ex7_fx_ld_data_q; +wire [64-(2**`GPR_WIDTH_ENC):63] ex8_fx_ld_data_d; +wire [64-(2**`GPR_WIDTH_ENC):63] ex8_fx_ld_data_q; +wire ex3_req_aborted_d; +wire ex3_req_aborted_q; +wire ex4_req_aborted_d; +wire ex4_req_aborted_q; +wire ex5_req_aborted_d; +wire ex5_req_aborted_q; +wire ex6_lq_req_abort_d; +wire ex6_lq_req_abort_q; +wire ex7_lq_req_abort_d; +wire ex7_lq_req_abort_q; +wire ex8_lq_req_abort_d; +wire ex8_lq_req_abort_q; +wire ex9_lq_req_abort_d; +wire ex9_lq_req_abort_q; +wire ex4_xu0_stg_act_d; +wire ex4_xu0_stg_act_q; +wire ex5_xu0_stg_act_d; +wire ex5_xu0_stg_act_q; +wire ex6_xu0_stg_act; +wire ex6_xu0_stg_act_d; +wire ex6_xu0_stg_act_q; +wire ex7_xu0_stg_act_d; +wire ex7_xu0_stg_act_q; +wire ex4_xu1_stg_act_d; +wire ex4_xu1_stg_act_q; +wire [64-(2**`GPR_WIDTH_ENC):64+(((2**`GPR_WIDTH_ENC)-1)/8)] ex6_gpr_wd0_d; +wire [64-(2**`GPR_WIDTH_ENC):64+(((2**`GPR_WIDTH_ENC)-1)/8)] ex6_gpr_wd0_q; +wire ex5_move_data_sel_d; +wire ex5_move_data_sel_q; +wire [(128-`STQ_DATA_SIZE):127] ex5_mv_rel_data_d; +wire [(128-`STQ_DATA_SIZE):127] ex5_mv_rel_data_q; +wire [64-(2**`GPR_WIDTH_ENC):63] lq_pc_ram_data_d; +wire [64-(2**`GPR_WIDTH_ENC):63] lq_pc_ram_data_q; + +//------------------------------------------------------------------- +// Scanchain +//------------------------------------------------------------------- +parameter ex2_rs1_offset = 0; +parameter ex2_rs2_offset = ex2_rs1_offset + 2**`GPR_WIDTH_ENC; +parameter ex2_s1_abort_offset = ex2_rs2_offset + 2**`GPR_WIDTH_ENC; +parameter ex2_s2_abort_offset = ex2_s1_abort_offset + 1; +parameter ex1_s1_xu0_sel_offset = ex2_s2_abort_offset + 1; +parameter ex1_s2_xu0_sel_offset = ex1_s1_xu0_sel_offset + 11; +parameter ex1_s1_xu1_sel_offset = ex1_s2_xu0_sel_offset + 11; +parameter ex1_s2_xu1_sel_offset = ex1_s1_xu1_sel_offset + 6; +parameter ex1_s1_lq_sel_offset = ex1_s2_xu1_sel_offset + 6; +parameter ex1_s2_lq_sel_offset = ex1_s1_lq_sel_offset + 5; +parameter ex1_s1_rel_sel_offset = ex1_s2_lq_sel_offset + 5; +parameter ex1_s2_rel_sel_offset = ex1_s1_rel_sel_offset + 2; +parameter ex5_xu0_rt_offset = ex1_s2_rel_sel_offset + 2; +parameter ex6_xu0_rt_offset = ex5_xu0_rt_offset + 2**`GPR_WIDTH_ENC; +parameter ex7_xu0_rt_offset = ex6_xu0_rt_offset + 2**`GPR_WIDTH_ENC; +parameter ex8_xu0_rt_offset = ex7_xu0_rt_offset + 2**`GPR_WIDTH_ENC; +parameter ex4_xu0_req_abort_offset = ex8_xu0_rt_offset + 2**`GPR_WIDTH_ENC; +parameter ex5_xu0_req_abort_offset = ex4_xu0_req_abort_offset + 1; +parameter ex6_xu0_req_abort_offset = ex5_xu0_req_abort_offset + 1; +parameter ex7_xu0_req_abort_offset = ex6_xu0_req_abort_offset + 1; +parameter ex8_xu0_req_abort_offset = ex7_xu0_req_abort_offset + 1; +parameter ex9_xu0_req_abort_offset = ex8_xu0_req_abort_offset + 1; +parameter ex10_xu0_req_abort_offset = ex9_xu0_req_abort_offset + 1; +parameter ex11_xu0_req_abort_offset = ex10_xu0_req_abort_offset + 1; +parameter ex12_xu0_req_abort_offset = ex11_xu0_req_abort_offset + 1; +parameter ex13_xu0_req_abort_offset = ex12_xu0_req_abort_offset + 1; +parameter ex4_xu1_rt_offset = ex13_xu0_req_abort_offset + 1; +parameter ex5_xu1_rt_offset = ex4_xu1_rt_offset + 2**`GPR_WIDTH_ENC; +parameter ex4_xu1_req_abort_offset = ex5_xu1_rt_offset + 2**`GPR_WIDTH_ENC; +parameter ex5_xu1_req_abort_offset = ex4_xu1_req_abort_offset + 1; +parameter ex6_xu1_req_abort_offset = ex5_xu1_req_abort_offset + 1; +parameter ex7_xu1_req_abort_offset = ex6_xu1_req_abort_offset + 1; +parameter ex8_xu1_req_abort_offset = ex7_xu1_req_abort_offset + 1; +parameter rel3_rel_rt_offset = ex8_xu1_req_abort_offset + 1; +parameter rel4_rel_rt_offset = rel3_rel_rt_offset + 2**`GPR_WIDTH_ENC; +parameter ex6_fx_ld_data_offset = rel4_rel_rt_offset + 2**`GPR_WIDTH_ENC; +parameter ex7_fx_ld_data_offset = ex6_fx_ld_data_offset + 2**`GPR_WIDTH_ENC; +parameter ex8_fx_ld_data_offset = ex7_fx_ld_data_offset + 2**`GPR_WIDTH_ENC; +parameter ex3_req_aborted_offset = ex8_fx_ld_data_offset + 2**`GPR_WIDTH_ENC; +parameter ex4_req_aborted_offset = ex3_req_aborted_offset + 1; +parameter ex5_req_aborted_offset = ex4_req_aborted_offset + 1; +parameter ex6_lq_req_abort_offset = ex5_req_aborted_offset + 1; +parameter ex7_lq_req_abort_offset = ex6_lq_req_abort_offset + 1; +parameter ex8_lq_req_abort_offset = ex7_lq_req_abort_offset + 1; +parameter ex9_lq_req_abort_offset = ex8_lq_req_abort_offset + 1; +parameter ex6_gpr_wd0_offset = ex9_lq_req_abort_offset + 1; +parameter ex5_move_data_sel_offset = ex6_gpr_wd0_offset + 2**`GPR_WIDTH_ENC + (2**`GPR_WIDTH_ENC)/8; +parameter ex5_mv_rel_data_offset = ex5_move_data_sel_offset + 1; +parameter ex6_dvc1_cmp_offset = ex5_mv_rel_data_offset + `STQ_DATA_SIZE; +parameter ex6_dvc2_cmp_offset = ex6_dvc1_cmp_offset + (2**`GPR_WIDTH_ENC)/8; +parameter lq_pc_ram_data_offset = ex6_dvc2_cmp_offset + (2**`GPR_WIDTH_ENC)/8; +parameter ex4_xu0_stg_act_offset = lq_pc_ram_data_offset + 2**`GPR_WIDTH_ENC; +parameter ex5_xu0_stg_act_offset = ex4_xu0_stg_act_offset + 1; +parameter ex6_xu0_stg_act_offset = ex5_xu0_stg_act_offset + 1; +parameter ex7_xu0_stg_act_offset = ex6_xu0_stg_act_offset + 1; +parameter ex4_xu1_stg_act_offset = ex7_xu0_stg_act_offset + 1; +parameter scan_right = ex4_xu1_stg_act_offset + 1; +wire [0:scan_right-1] siv; +wire [0:scan_right-1] sov; + +(* analysis_not_referenced="true" *) + +wire unused; + +//---------------------------------------------------------------------------------------------------------------------------------------- +// Misc Assignments +//---------------------------------------------------------------------------------------------------------------------------------------- +assign tiup = 1'b1; +assign tidn = 1'b0; +assign ex3_xu0_rt = xu0_lq_ex3_rt; +assign ex4_xu0_rt = xu0_lq_ex4_rt; +assign ex5_xu0_rt = ex5_xu0_rt_q; +assign ex6_xu0_rt = ex6_xu0_rt_q; +assign ex7_xu0_rt_d = xu0_lq_ex6_rt; +assign ex7_xu0_rt = ex7_xu0_rt_q; +assign ex8_xu0_rt = ex8_xu0_rt_q; +assign ex3_xu0_req_abort = xu0_lq_ex3_abort; +assign ex4_xu0_req_abort_d = ex3_xu0_req_abort; +assign ex5_xu0_req_abort_d = ex4_xu0_req_abort_q; +assign ex6_xu0_req_abort_d = ex5_xu0_req_abort_q; +assign ex7_xu0_req_abort_d = ex6_xu0_req_abort_q; +assign ex8_xu0_req_abort_d = ex7_xu0_req_abort_q; +assign ex9_xu0_req_abort_d = ex8_xu0_req_abort_q; +assign ex10_xu0_req_abort_d = ex9_xu0_req_abort_q; +assign ex11_xu0_req_abort_d = ex10_xu0_req_abort_q; +assign ex12_xu0_req_abort_d = ex11_xu0_req_abort_q; +assign ex13_xu0_req_abort_d = ex12_xu0_req_abort_q; + +assign ex3_xu1_rt = xu1_lq_ex3_rt; +assign ex4_xu1_rt = ex4_xu1_rt_q; +assign ex5_xu1_rt = ex5_xu1_rt_q; +assign ex3_xu1_req_abort = xu1_lq_ex3_abort; +assign ex4_xu1_req_abort_d = ex3_xu1_req_abort; +assign ex5_xu1_req_abort_d = ex4_xu1_req_abort_q; +assign ex6_xu1_req_abort_d = ex5_xu1_req_abort_q; +assign ex7_xu1_req_abort_d = ex6_xu1_req_abort_q; +assign ex8_xu1_req_abort_d = ex7_xu1_req_abort_q; + +assign rel2_rel_rt = lsq_ctl_rel2_data[128-(2**`GPR_WIDTH_ENC):127]; +assign rel3_rel_rt_d = rel2_rel_rt; +assign rel4_rel_rt_d = rel3_rel_rt_q; + +assign ex3_xu0_stg_act = xu0_lq_ex3_act; +assign ex4_xu0_stg_act_d = ex3_xu0_stg_act; +assign ex5_xu0_stg_act_d = ex4_xu0_stg_act_q; +assign ex6_xu0_stg_act_d = ex5_xu0_stg_act_q; +assign ex6_xu0_stg_act = xu0_lq_ex6_act | ex6_xu0_stg_act_q; +assign ex7_xu0_stg_act_d = ex6_xu0_stg_act; + +assign ex3_xu1_stg_act = xu1_lq_ex3_act; +assign ex4_xu1_stg_act_d = ex3_xu1_stg_act; + +//---------------------------------------------------------------------------------------------------------------------------------------- +// Load Data Muxing Update +//---------------------------------------------------------------------------------------------------------------------------------------- +// Move Data contains mffgpr,mftgpr,ditc and store_updates_forms +// dcc_byp_ex4_moveOp_val is valid for the following instructions coming down the LQ Pipeline mffgpr or store_update_forms +// dcc_byp_stq6_moveOp_val is valid for the following instructions coming down the COMMIT Pipeline mftgpr, mfdpf, or mfdpa +generate + if (`STQ_DATA_SIZE == 128) begin : stqDat128 + assign ex5_mv_rel_data_d[(128-`STQ_DATA_SIZE):127-(2**`GPR_WIDTH_ENC)] = dat_ctl_stq6_axu_data[(128-`STQ_DATA_SIZE):127-(2**`GPR_WIDTH_ENC)]; + assign ex5_mv_rel_data_d[128-(2**`GPR_WIDTH_ENC):127] = (dat_ctl_stq6_axu_data[128-(2**`GPR_WIDTH_ENC):127] & {(2**`GPR_WIDTH_ENC){dcc_byp_stq6_moveOp_val}}) | + ( dcc_byp_ex4_move_data & {(2**`GPR_WIDTH_ENC){dcc_byp_ex4_moveOp_val}}); + assign unused = tidn; + end +endgenerate + +generate + if (`STQ_DATA_SIZE == 64) begin : stqDat64 + if ((2 ** `GPR_WIDTH_ENC) == 64) begin : gpr64 + assign ex5_mv_rel_data_d[128 - (2 ** `GPR_WIDTH_ENC):127] = (dat_ctl_stq6_axu_data[128-(2**`GPR_WIDTH_ENC):127] & {(2**`GPR_WIDTH_ENC){dcc_byp_stq6_moveOp_val}}) | + ( dcc_byp_ex4_move_data & {(2**`GPR_WIDTH_ENC){dcc_byp_ex4_moveOp_val}}); + end + + if ((2 ** `GPR_WIDTH_ENC) == 32) begin : gpr32 + assign ex5_mv_rel_data_d[(128-`STQ_DATA_SIZE):127-(2**`GPR_WIDTH_ENC)] = dat_ctl_stq6_axu_data[(128-`STQ_DATA_SIZE):127-(2**`GPR_WIDTH_ENC)]; + assign ex5_mv_rel_data_d[128-(2**`GPR_WIDTH_ENC):127] = (dat_ctl_stq6_axu_data[128-(2**`GPR_WIDTH_ENC):127] & {(2**`GPR_WIDTH_ENC){dcc_byp_stq6_moveOp_val}}) | + ( dcc_byp_ex4_move_data & {(2**`GPR_WIDTH_ENC){dcc_byp_ex4_moveOp_val}}); + end + assign unused = tidn | |lsq_ctl_rel2_data[0:`STQ_DATA_SIZE-1]; + end +endgenerate + +assign ex4_move_data_sel = dcc_byp_ex4_moveOp_val | dcc_byp_stq6_moveOp_val; +assign ex5_move_data_sel_d = ex4_move_data_sel; + +// FX Load Hit Data +// Mux Between load hit and Move Data +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Mux Between move data and load hit +assign ex5_load_move_data = (ex5_mv_rel_data_q & {(`STQ_DATA_SIZE){ ex5_move_data_sel_q}}) | + (dat_ctl_ex5_load_data & {(`STQ_DATA_SIZE){~ex5_move_data_sel_q}}); +// Mux Between load hit/Move Data and Data Forward +assign ex5_load_data = (lsq_ctl_ex5_fwd_data & {(`STQ_DATA_SIZE){ lsq_ctl_ex5_fwd_val}}) | + (ex5_load_move_data & {(`STQ_DATA_SIZE){~lsq_ctl_ex5_fwd_val}}); + +// Fixed Point Data For bypass +assign lq_xu_ex5_rt = ex5_load_data; +assign ex5_fx_ld_data = ex5_load_data[128 - (2 ** `GPR_WIDTH_ENC):127]; +assign ex6_fx_ld_data_d = ex5_fx_ld_data; +assign ex7_fx_ld_data_d = ex6_fx_ld_data_q; +assign ex8_fx_ld_data_d = ex7_fx_ld_data_q; +assign ex5_lq_req_abort = dcc_byp_ex5_lq_req_abort | ex5_req_aborted_q; +assign ex6_lq_req_abort_d = ex5_lq_req_abort; +assign ex7_lq_req_abort_d = ex6_lq_req_abort_q; +assign ex8_lq_req_abort_d = ex7_lq_req_abort_q; +assign ex9_lq_req_abort_d = ex8_lq_req_abort_q; +assign ex2_req_aborted = ex2_s1_abort_q | ex2_s2_abort_q; +assign ex3_req_aborted_d = ex2_req_aborted; +assign ex4_req_aborted_d = ex3_req_aborted_q; +assign ex5_req_aborted_d = ex4_req_aborted_q; + +generate begin : ex5ParGen + genvar b; + for (b=0; b<=((2**`GPR_WIDTH_ENC)-1)/8; b=b+1) begin : ex5ParGen + assign ex5_fx_ld_data_par[b] = ^(ex5_fx_ld_data[(64-(2**`GPR_WIDTH_ENC))+(b*8):(64-(2**`GPR_WIDTH_ENC))+(b*8)+7]); + end + end +endgenerate + +assign ex6_gpr_wd0_d = {ex5_fx_ld_data, ex5_fx_ld_data_par}; + +//---------------------------------------------------------------------------------------------------------------------------------------- +// Internal Load LQ Muxing +//---------------------------------------------------------------------------------------------------------------------------------------- +// Source 1 Bypass Control +assign ex1_s1_load_byp_val = |(ex1_s1_lq_sel_q[4:7]); + +assign ex1_s1_load_data = (ex5_fx_ld_data & {(2**`GPR_WIDTH_ENC){ex1_s1_lq_sel_q[4]}}) | + (ex6_fx_ld_data_q & {(2**`GPR_WIDTH_ENC){ex1_s1_lq_sel_q[5]}}) | + (ex7_fx_ld_data_q & {(2**`GPR_WIDTH_ENC){ex1_s1_lq_sel_q[6]}}) | + (ex8_fx_ld_data_q & {(2**`GPR_WIDTH_ENC){ex1_s1_lq_sel_q[7]}}); + +assign ex1_s1_load_abort_byp_val = |(ex1_s1_lq_sel_q); + +assign ex1_s1_load_abort = (ex5_lq_req_abort & ex1_s1_lq_sel_q[4]) | + (ex6_lq_req_abort_q & ex1_s1_lq_sel_q[5]) | + (ex7_lq_req_abort_q & ex1_s1_lq_sel_q[6]) | + (ex8_lq_req_abort_q & ex1_s1_lq_sel_q[7]) | + (ex9_lq_req_abort_q & ex1_s1_lq_sel_q[8]); + +// Source 2 Bypass Control +assign ex1_s2_load_byp_val = |(ex1_s2_lq_sel_q[4:7]); + +assign ex1_s2_load_data = (ex5_fx_ld_data & {(2**`GPR_WIDTH_ENC){ex1_s2_lq_sel_q[4]}}) | + (ex6_fx_ld_data_q & {(2**`GPR_WIDTH_ENC){ex1_s2_lq_sel_q[5]}}) | + (ex7_fx_ld_data_q & {(2**`GPR_WIDTH_ENC){ex1_s2_lq_sel_q[6]}}) | + (ex8_fx_ld_data_q & {(2**`GPR_WIDTH_ENC){ex1_s2_lq_sel_q[7]}}); + +assign ex1_s2_load_abort_byp_val = |(ex1_s2_lq_sel_q); + +assign ex1_s2_load_abort = (ex5_lq_req_abort & ex1_s2_lq_sel_q[4]) | + (ex6_lq_req_abort_q & ex1_s2_lq_sel_q[5]) | + (ex7_lq_req_abort_q & ex1_s2_lq_sel_q[6]) | + (ex8_lq_req_abort_q & ex1_s2_lq_sel_q[7]) | + (ex9_lq_req_abort_q & ex1_s2_lq_sel_q[8]); + +//---------------------------------------------------------------------------------------------------------------------------------------- +// Internal Reload LQ Muxing +//---------------------------------------------------------------------------------------------------------------------------------------- +// Source 1 Bypass Control +assign ex1_s1_reload_byp_val = |(ex1_s1_rel_sel_q); + +assign ex1_s1_reload_data = (rel3_rel_rt_q & {(2**`GPR_WIDTH_ENC){ex1_s1_rel_sel_q[2]}}) | + (rel4_rel_rt_q & {(2**`GPR_WIDTH_ENC){ex1_s1_rel_sel_q[3]}}); + +// Source 2 Bypass Control +assign ex1_s2_reload_byp_val = |(ex1_s2_rel_sel_q); + +assign ex1_s2_reload_data = (rel3_rel_rt_q & {(2**`GPR_WIDTH_ENC){ex1_s2_rel_sel_q[2]}}) | + (rel4_rel_rt_q & {(2**`GPR_WIDTH_ENC){ex1_s2_rel_sel_q[3]}}); + +//---------------------------------------------------------------------------------------------------------------------------------------- +// xu0 Muxing +//---------------------------------------------------------------------------------------------------------------------------------------- +// Source 1 Bypass Control +assign ex1_s1_xu0_byp_val = |(ex1_s1_xu0_sel_q[2:7]); + +assign ex1_s1_xu0_data = (ex3_xu0_rt & {(2**`GPR_WIDTH_ENC){ex1_s1_xu0_sel_q[2]}}) | + (ex4_xu0_rt & {(2**`GPR_WIDTH_ENC){ex1_s1_xu0_sel_q[3]}}) | + (ex5_xu0_rt & {(2**`GPR_WIDTH_ENC){ex1_s1_xu0_sel_q[4]}}) | + (ex6_xu0_rt & {(2**`GPR_WIDTH_ENC){ex1_s1_xu0_sel_q[5]}}) | + (ex7_xu0_rt & {(2**`GPR_WIDTH_ENC){ex1_s1_xu0_sel_q[6]}}) | + (ex8_xu0_rt & {(2**`GPR_WIDTH_ENC){ex1_s1_xu0_sel_q[7]}}); + +assign ex1_s1_xu0_abort_byp_val = |(ex1_s1_xu0_sel_q); + +assign ex1_s1_xu0_abort = (ex3_xu0_req_abort & ex1_s1_xu0_sel_q[2]) | + (ex4_xu0_req_abort_q & ex1_s1_xu0_sel_q[3]) | + (ex5_xu0_req_abort_q & ex1_s1_xu0_sel_q[4]) | + (ex6_xu0_req_abort_q & ex1_s1_xu0_sel_q[5]) | + (ex7_xu0_req_abort_q & ex1_s1_xu0_sel_q[6]) | + (ex8_xu0_req_abort_q & ex1_s1_xu0_sel_q[7]) | + (ex9_xu0_req_abort_q & ex1_s1_xu0_sel_q[8]) | + (ex10_xu0_req_abort_q & ex1_s1_xu0_sel_q[9]) | + (ex11_xu0_req_abort_q & ex1_s1_xu0_sel_q[10]) | + (ex12_xu0_req_abort_q & ex1_s1_xu0_sel_q[11]) | + (ex13_xu0_req_abort_q & ex1_s1_xu0_sel_q[12]); + +// Source 2 Bypass Control +assign ex1_s2_xu0_byp_val = |(ex1_s2_xu0_sel_q[2:7]); + +assign ex1_s2_xu0_data = (ex3_xu0_rt & {(2**`GPR_WIDTH_ENC){ex1_s2_xu0_sel_q[2]}}) | + (ex4_xu0_rt & {(2**`GPR_WIDTH_ENC){ex1_s2_xu0_sel_q[3]}}) | + (ex5_xu0_rt & {(2**`GPR_WIDTH_ENC){ex1_s2_xu0_sel_q[4]}}) | + (ex6_xu0_rt & {(2**`GPR_WIDTH_ENC){ex1_s2_xu0_sel_q[5]}}) | + (ex7_xu0_rt & {(2**`GPR_WIDTH_ENC){ex1_s2_xu0_sel_q[6]}}) | + (ex8_xu0_rt & {(2**`GPR_WIDTH_ENC){ex1_s2_xu0_sel_q[7]}}); + +assign ex1_s2_xu0_abort_byp_val = |(ex1_s2_xu0_sel_q); + +assign ex1_s2_xu0_abort = (ex3_xu0_req_abort & ex1_s2_xu0_sel_q[2]) | + (ex4_xu0_req_abort_q & ex1_s2_xu0_sel_q[3]) | + (ex5_xu0_req_abort_q & ex1_s2_xu0_sel_q[4]) | + (ex6_xu0_req_abort_q & ex1_s2_xu0_sel_q[5]) | + (ex7_xu0_req_abort_q & ex1_s2_xu0_sel_q[6]) | + (ex8_xu0_req_abort_q & ex1_s2_xu0_sel_q[7]) | + (ex9_xu0_req_abort_q & ex1_s2_xu0_sel_q[8]) | + (ex10_xu0_req_abort_q & ex1_s2_xu0_sel_q[9]) | + (ex11_xu0_req_abort_q & ex1_s2_xu0_sel_q[10]) | + (ex12_xu0_req_abort_q & ex1_s2_xu0_sel_q[11]) | + (ex13_xu0_req_abort_q & ex1_s2_xu0_sel_q[12]); + +//---------------------------------------------------------------------------------------------------------------------------------------- +// xu1 Muxing +//---------------------------------------------------------------------------------------------------------------------------------------- +// Source 1 Bypass Control +assign ex1_s1_xu1_byp_val = |(ex1_s1_xu1_sel_q[2:4]); + +assign ex1_s1_xu1_data = (ex3_xu1_rt & {(2**`GPR_WIDTH_ENC){ex1_s1_xu1_sel_q[2]}}) | + (ex4_xu1_rt & {(2**`GPR_WIDTH_ENC){ex1_s1_xu1_sel_q[3]}}) | + (ex5_xu1_rt & {(2**`GPR_WIDTH_ENC){ex1_s1_xu1_sel_q[4]}}); + +assign ex1_s1_xu1_abort_byp_val = |(ex1_s1_xu1_sel_q); + +assign ex1_s1_xu1_abort = (ex3_xu1_req_abort & ex1_s1_xu1_sel_q[2]) | + (ex4_xu1_req_abort_q & ex1_s1_xu1_sel_q[3]) | + (ex5_xu1_req_abort_q & ex1_s1_xu1_sel_q[4]) | + (ex6_xu1_req_abort_q & ex1_s1_xu1_sel_q[5]) | + (ex7_xu1_req_abort_q & ex1_s1_xu1_sel_q[6]) | + (ex8_xu1_req_abort_q & ex1_s1_xu1_sel_q[7]); + +// Source 2 Bypass Control +assign ex1_s2_xu1_byp_val = |(ex1_s2_xu1_sel_q[2:4]); + +assign ex1_s2_xu1_data = (ex3_xu1_rt & {(2**`GPR_WIDTH_ENC){ex1_s2_xu1_sel_q[2]}}) | + (ex4_xu1_rt & {(2**`GPR_WIDTH_ENC){ex1_s2_xu1_sel_q[3]}}) | + (ex5_xu1_rt & {(2**`GPR_WIDTH_ENC){ex1_s2_xu1_sel_q[4]}}); + +assign ex1_s2_xu1_abort_byp_val = |(ex1_s2_xu1_sel_q); + +assign ex1_s2_xu1_abort = (ex3_xu1_req_abort & ex1_s2_xu1_sel_q[2]) | + (ex4_xu1_req_abort_q & ex1_s2_xu1_sel_q[3]) | + (ex5_xu1_req_abort_q & ex1_s2_xu1_sel_q[4]) | + (ex6_xu1_req_abort_q & ex1_s2_xu1_sel_q[5]) | + (ex7_xu1_req_abort_q & ex1_s2_xu1_sel_q[6]) | + (ex8_xu1_req_abort_q & ex1_s2_xu1_sel_q[7]); + +//---------------------------------------------------------------------------------------------------------------------------------------- +// Source 1 Mux Selects +//---------------------------------------------------------------------------------------------------------------------------------------- +// GPR Source 1 +assign ex1_rs1_byp_sel[0] = (~(|{ex1_s1_xu0_byp_val, ex1_s1_xu1_byp_val, ex1_s1_load_byp_val, ex1_s1_reload_byp_val})) & (~dec_byp_ex1_rs1_zero); // Use Array or use ZERO +assign ex1_rs1_byp_sel[1] = ex1_s1_xu0_byp_val & (~dec_byp_ex1_rs1_zero); // Use xu0 or use ZERO +assign ex1_rs1_byp_sel[2] = ex1_s1_xu1_byp_val & (~dec_byp_ex1_rs1_zero); // Use xu1 or use ZERO +assign ex1_rs1_byp_sel[3] = ex1_s1_load_byp_val & (~dec_byp_ex1_rs1_zero); // Use LQ LOAD or use ZERO +assign ex1_rs1_byp_sel[4] = ex1_s1_reload_byp_val & (~dec_byp_ex1_rs1_zero); // Use LQ RELOAD or use ZERO + +assign ex2_rs1_d = (rv_lq_gpr_ex1_r0d & {(2**`GPR_WIDTH_ENC){ex1_rs1_byp_sel[0]}}) | + (ex1_s1_xu0_data & {(2**`GPR_WIDTH_ENC){ex1_rs1_byp_sel[1]}}) | + (ex1_s1_xu1_data & {(2**`GPR_WIDTH_ENC){ex1_rs1_byp_sel[2]}}) | + (ex1_s1_load_data & {(2**`GPR_WIDTH_ENC){ex1_rs1_byp_sel[3]}}) | + (ex1_s1_reload_data & {(2**`GPR_WIDTH_ENC){ex1_rs1_byp_sel[4]}}); + +// Abort Bypass for Source 1 +assign ex1_rs1_abort_byp_sel[1] = ex1_s1_xu0_abort_byp_val & (~dec_byp_ex1_rs1_zero); // Use xu0 or use ZERO +assign ex1_rs1_abort_byp_sel[2] = ex1_s1_xu1_abort_byp_val & (~dec_byp_ex1_rs1_zero); // Use xu1 or use ZERO +assign ex1_rs1_abort_byp_sel[3] = ex1_s1_load_abort_byp_val & (~dec_byp_ex1_rs1_zero); // Use LQ LOAD or use ZERO + +assign ex1_s1_abort = ((ex1_s1_xu0_abort & ex1_rs1_abort_byp_sel[1]) | + (ex1_s1_xu1_abort & ex1_rs1_abort_byp_sel[2]) | + (ex1_s1_load_abort & ex1_rs1_abort_byp_sel[3])) & dec_byp_ex1_s1_vld; + +assign ex2_s1_abort_d = ex1_s1_abort; + +//---------------------------------------------------------------------------------------------------------------------------------------- +// Source 2 Mux Selects +//---------------------------------------------------------------------------------------------------------------------------------------- +// GPR Source 2 +assign ex1_rs2_byp_sel[0] = (~(|{ex1_s2_xu0_byp_val, ex1_s2_xu1_byp_val, ex1_s2_load_byp_val, ex1_s2_reload_byp_val})) & (~dec_byp_ex1_use_imm); // Use Array or use IMMEDIATE +assign ex1_rs2_byp_sel[1] = ex1_s2_xu0_byp_val & (~dec_byp_ex1_use_imm); // Use xu0 or use IMMEDIATE +assign ex1_rs2_byp_sel[2] = ex1_s2_xu1_byp_val & (~dec_byp_ex1_use_imm); // Use xu1 or use IMMEDIATE +assign ex1_rs2_byp_sel[3] = ex1_s2_load_byp_val & (~dec_byp_ex1_use_imm); // Use LQ LOAD or use IMMEDIATE +assign ex1_rs2_byp_sel[4] = ex1_s2_reload_byp_val & (~dec_byp_ex1_use_imm); // Use LQ RELOAD or use IMMEDIATE + +assign ex2_rs2_d = (rv_lq_gpr_ex1_r1d & {(2**`GPR_WIDTH_ENC){ex1_rs2_byp_sel[0]}}) | + (ex1_s2_xu0_data & {(2**`GPR_WIDTH_ENC){ex1_rs2_byp_sel[1]}}) | + (ex1_s2_xu1_data & {(2**`GPR_WIDTH_ENC){ex1_rs2_byp_sel[2]}}) | + (ex1_s2_load_data & {(2**`GPR_WIDTH_ENC){ex1_rs2_byp_sel[3]}}) | + (ex1_s2_reload_data & {(2**`GPR_WIDTH_ENC){ex1_rs2_byp_sel[4]}}) | + (dec_byp_ex1_imm & {(2**`GPR_WIDTH_ENC){dec_byp_ex1_use_imm}}); + +// Abort Bypass for Source 2 +assign ex1_rs2_abort_byp_sel[1] = ex1_s2_xu0_abort_byp_val & (~dec_byp_ex1_use_imm); // Use xu0 or use IMMEDIATE +assign ex1_rs2_abort_byp_sel[2] = ex1_s2_xu1_abort_byp_val & (~dec_byp_ex1_use_imm); // Use xu1 or use IMMEDIATE +assign ex1_rs2_abort_byp_sel[3] = ex1_s2_load_abort_byp_val & (~dec_byp_ex1_use_imm); // Use LQ LOAD or use IMMEDIATE + +assign ex1_s2_abort = ((ex1_s2_xu0_abort & ex1_rs2_abort_byp_sel[1]) | + (ex1_s2_xu1_abort & ex1_rs2_abort_byp_sel[2]) | + (ex1_s2_load_abort & ex1_rs2_abort_byp_sel[3])) & dec_byp_ex1_s2_vld; + +assign ex2_s2_abort_d = ex1_s2_abort; + +//---------------------------------------------------------------------------------------------------------------------------------------- +// Load Hit Debug Data Compare +//---------------------------------------------------------------------------------------------------------------------------------------- + +// Load Hit Data Compare +generate begin : dvcCmpLH + genvar t; + for (t = 0; t <= ((2 ** `GPR_WIDTH_ENC)/8) - 1; t = t + 1) begin : dvcCmpLH + assign ex6_dvc1_cmp_d[t] = ( ex5_fx_ld_data[(64-(2**`GPR_WIDTH_ENC))+t*8:(64-(2**`GPR_WIDTH_ENC))+((t*8)+7)] == + spr_byp_spr_dvc1_dbg[(64-(2**`GPR_WIDTH_ENC))+t*8:(64-(2**`GPR_WIDTH_ENC))+((t*8)+7)]) & dcc_byp_ex5_byte_mask[t]; + assign ex6_dvc2_cmp_d[t] = ( ex5_fx_ld_data[(64-(2**`GPR_WIDTH_ENC))+t*8:(64-(2**`GPR_WIDTH_ENC))+((t*8)+7)] == + spr_byp_spr_dvc2_dbg[(64-(2**`GPR_WIDTH_ENC))+t*8:(64-(2**`GPR_WIDTH_ENC))+((t*8)+7)]) & dcc_byp_ex5_byte_mask[t]; + end +end +endgenerate + +// Thread Select +generate begin : sprTid + genvar tid; + for (tid=0; tid<`THREADS; tid=tid+1) begin : sprTid + assign spr_dbcr2_dvc1m_tid[tid] = spr_byp_spr_dbcr2_dvc1m[(tid*2):((tid*2)+1)]; + assign spr_dbcr2_dvc1be_tid[tid] = spr_byp_spr_dbcr2_dvc1be[tid*8:(tid*8)+7]; + assign spr_dbcr2_dvc2m_tid[tid] = spr_byp_spr_dbcr2_dvc2m[tid*2:(tid*2)+1]; + assign spr_dbcr2_dvc2be_tid[tid] = spr_byp_spr_dbcr2_dvc2be[tid*8:(tid*8)+7]; + end +end +endgenerate + +always @(*) begin: ldhTid + reg [0:1] dvc1m; + reg [0:1] dvc2m; + reg [8-(2**`GPR_WIDTH_ENC)/8:7] dvc1be; + reg [8-(2**`GPR_WIDTH_ENC)/8:7] dvc2be; + + //(* analysis_not_referenced="true" *) + + integer tid; + dvc1m = {2{1'b0}}; + dvc2m = {2{1'b0}}; + dvc1be = {((2**`GPR_WIDTH_ENC)/8){1'b0}}; + dvc2be = {((2**`GPR_WIDTH_ENC)/8){1'b0}}; + for (tid=0; tid<`THREADS; tid=tid+1) begin + dvc1m = (spr_dbcr2_dvc1m_tid[tid] & {2{dcc_byp_ex6_thrd_id[tid]}}) | dvc1m; + dvc2m = (spr_dbcr2_dvc2m_tid[tid] & {2{dcc_byp_ex6_thrd_id[tid]}}) | dvc2m; + dvc1be = (spr_dbcr2_dvc1be_tid[tid][8-((2**`GPR_WIDTH_ENC)/8):7] & {((2**`GPR_WIDTH_ENC)/8){dcc_byp_ex6_thrd_id[tid]}}) | dvc1be; + dvc2be = (spr_dbcr2_dvc2be_tid[tid][8-((2**`GPR_WIDTH_ENC)/8):7] & {((2**`GPR_WIDTH_ENC)/8){dcc_byp_ex6_thrd_id[tid]}}) | dvc2be; + end + spr_dbcr2_dvc1m = dvc1m; + spr_dbcr2_dvc2m = dvc2m; + spr_dbcr2_dvc1be = dvc1be; + spr_dbcr2_dvc2be = dvc2be; +end + +lq_spr_dvccmp #(.REGSIZE(2**`GPR_WIDTH_ENC)) dvc1Ldh( + .en(dcc_byp_ex6_dvc1_en), + .en00(dcc_byp_ex6_dacr_cmpr[0]), + .cmp(ex6_dvc1_cmp_q), + .dvcm(spr_dbcr2_dvc1m), + .dvcbe(spr_dbcr2_dvc1be), + .dvc_cmpr(ex6_dvc1r_cmpr)); + +lq_spr_dvccmp #(.REGSIZE(2**`GPR_WIDTH_ENC)) dvc2Ldh( + .en(dcc_byp_ex6_dvc2_en), + .en00(dcc_byp_ex6_dacr_cmpr[1]), + .cmp(ex6_dvc2_cmp_q), + .dvcm(spr_dbcr2_dvc2m), + .dvcbe(spr_dbcr2_dvc2be), + .dvc_cmpr(ex6_dvc2r_cmpr)); + +assign ex6_dacrw = {ex6_dvc1r_cmpr, ex6_dvc2r_cmpr, dcc_byp_ex6_dacr_cmpr[2:3]}; + +//---------------------------------------------------------------------------------------------------------------------------------------- +// RAM Data Muxing +//---------------------------------------------------------------------------------------------------------------------------------------- +// RAM Data Update + +assign lq_pc_ram_data_d = dcc_byp_ram_sel ? lsq_ctl_rel2_data[128-(2**`GPR_WIDTH_ENC):127] : ex6_gpr_wd0_q[64-(2**`GPR_WIDTH_ENC):63]; +assign lq_pc_ram_data = lq_pc_ram_data_q; + +//---------------------------------------------------------------------------------------------------------------------------------------- +// Reload Data Parity Generation +//---------------------------------------------------------------------------------------------------------------------------------------- +generate begin : relParGen + genvar b; + for (b = 0; b <= (`STQ_DATA_SIZE- 1)/8; b=b+1) begin : relParGen + assign rel2_data_par[b] = ^(lsq_ctl_rel2_data[(128-`STQ_DATA_SIZE) + b*8:((128-`STQ_DATA_SIZE))+(b*8)+7]); + end +end +endgenerate + +assign rel2_rv_rel_data = {lsq_ctl_rel2_data[128-(2**`GPR_WIDTH_ENC):127], + rel2_data_par[((`STQ_DATA_SIZE-1)/8)-(((2**`GPR_WIDTH_ENC)-1)/8):(`STQ_DATA_SIZE-1)/8]}; +assign rel2_xu_rel_data = {lsq_ctl_rel2_data[(128-`STQ_DATA_SIZE):127], rel2_data_par}; + +//---------------------------------------------------------------------------------------------------------------------------------------- +// Assign targets +//---------------------------------------------------------------------------------------------------------------------------------------- +assign byp_dir_ex2_rs1 = ex2_rs1_q; +assign byp_dir_ex2_rs2 = ex2_rs2_q; +assign byp_ex2_req_aborted = ex2_req_aborted; +assign lq_rv_gpr_ex6_wd = ex6_gpr_wd0_q; +assign lq_rv_gpr_rel_wd = rel2_rv_rel_data; +assign lq_xu_gpr_rel_wd = rel2_xu_rel_data; +assign ctl_lsq_ex4_xu1_data = ex4_xu1_rt_q; +assign ctl_lsq_ex6_ldh_dacrw = ex6_dacrw; +assign lq_rv_ex2_s1_abort = ex2_s1_abort_q; +assign lq_rv_ex2_s2_abort = ex2_s2_abort_q; +assign byp_dec_ex1_s1_abort = ex1_s1_abort; +assign byp_dec_ex1_s2_abort = ex1_s2_abort; + +//---------------------------------------------------------------------------------------------------------------------------------------- +// Latches +//---------------------------------------------------------------------------------------------------------------------------------------- + +tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) ex2_rs1_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(dec_byp_ex1_stg_act), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_rs1_offset:ex2_rs1_offset + 2**`GPR_WIDTH_ENC - 1]), + .scout(sov[ex2_rs1_offset:ex2_rs1_offset + 2**`GPR_WIDTH_ENC - 1]), + .din(ex2_rs1_d), + .dout(ex2_rs1_q)); + +tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) ex2_rs2_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(dec_byp_ex1_stg_act), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_rs2_offset:ex2_rs2_offset + 2**`GPR_WIDTH_ENC - 1]), + .scout(sov[ex2_rs2_offset:ex2_rs2_offset + 2**`GPR_WIDTH_ENC - 1]), + .din(ex2_rs2_d), + .dout(ex2_rs2_q)); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_s1_abort_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_s1_abort_offset]), + .scout(sov[ex2_s1_abort_offset]), + .din(ex2_s1_abort_d), + .dout(ex2_s1_abort_q)); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_s2_abort_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_s2_abort_offset]), + .scout(sov[ex2_s2_abort_offset]), + .din(ex2_s2_abort_d), + .dout(ex2_s2_abort_q)); + +tri_rlmreg_p #(.WIDTH(11), .INIT(0), .NEEDS_SRESET(1)) ex1_s1_xu0_sel_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(dec_byp_ex0_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_s1_xu0_sel_offset:ex1_s1_xu0_sel_offset + (11) - 1]), + .scout(sov[ex1_s1_xu0_sel_offset:ex1_s1_xu0_sel_offset + (11) - 1]), + .din(rv_lq_ex0_s1_xu0_sel), + .dout(ex1_s1_xu0_sel_q)); + +tri_rlmreg_p #(.WIDTH(11), .INIT(0), .NEEDS_SRESET(1)) ex1_s2_xu0_sel_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(dec_byp_ex0_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_s2_xu0_sel_offset:ex1_s2_xu0_sel_offset + (11) - 1]), + .scout(sov[ex1_s2_xu0_sel_offset:ex1_s2_xu0_sel_offset + (11) - 1]), + .din(rv_lq_ex0_s2_xu0_sel), + .dout(ex1_s2_xu0_sel_q)); + +tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) ex1_s1_xu1_sel_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(dec_byp_ex0_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_s1_xu1_sel_offset:ex1_s1_xu1_sel_offset + (6) - 1]), + .scout(sov[ex1_s1_xu1_sel_offset:ex1_s1_xu1_sel_offset + (6) - 1]), + .din(rv_lq_ex0_s1_xu1_sel), + .dout(ex1_s1_xu1_sel_q)); + +tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) ex1_s2_xu1_sel_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(dec_byp_ex0_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_s2_xu1_sel_offset:ex1_s2_xu1_sel_offset + (6) - 1]), + .scout(sov[ex1_s2_xu1_sel_offset:ex1_s2_xu1_sel_offset + (6) - 1]), + .din(rv_lq_ex0_s2_xu1_sel), + .dout(ex1_s2_xu1_sel_q)); + +tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) ex1_s1_lq_sel_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(dec_byp_ex0_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_s1_lq_sel_offset:ex1_s1_lq_sel_offset + (5) - 1]), + .scout(sov[ex1_s1_lq_sel_offset:ex1_s1_lq_sel_offset + (5) - 1]), + .din(rv_lq_ex0_s1_lq_sel), + .dout(ex1_s1_lq_sel_q)); + +tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) ex1_s2_lq_sel_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(dec_byp_ex0_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_s2_lq_sel_offset:ex1_s2_lq_sel_offset + (5) - 1]), + .scout(sov[ex1_s2_lq_sel_offset:ex1_s2_lq_sel_offset + (5) - 1]), + .din(rv_lq_ex0_s2_lq_sel), + .dout(ex1_s2_lq_sel_q)); + +tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex1_s1_rel_sel_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(dec_byp_ex0_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_s1_rel_sel_offset:ex1_s1_rel_sel_offset + (2) - 1]), + .scout(sov[ex1_s1_rel_sel_offset:ex1_s1_rel_sel_offset + (2) - 1]), + .din(rv_lq_ex0_s1_rel_sel), + .dout(ex1_s1_rel_sel_q)); + +tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex1_s2_rel_sel_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(dec_byp_ex0_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_s2_rel_sel_offset:ex1_s2_rel_sel_offset + (2) - 1]), + .scout(sov[ex1_s2_rel_sel_offset:ex1_s2_rel_sel_offset + (2) - 1]), + .din(rv_lq_ex0_s2_rel_sel), + .dout(ex1_s2_rel_sel_q)); + +tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) ex5_xu0_rt_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex4_xu0_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_xu0_rt_offset:ex5_xu0_rt_offset + 2**`GPR_WIDTH_ENC - 1]), + .scout(sov[ex5_xu0_rt_offset:ex5_xu0_rt_offset + 2**`GPR_WIDTH_ENC - 1]), + .din(ex4_xu0_rt), + .dout(ex5_xu0_rt_q)); + +tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) ex6_xu0_rt_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex5_xu0_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_xu0_rt_offset:ex6_xu0_rt_offset + 2**`GPR_WIDTH_ENC - 1]), + .scout(sov[ex6_xu0_rt_offset:ex6_xu0_rt_offset + 2**`GPR_WIDTH_ENC - 1]), + .din(ex5_xu0_rt_q), + .dout(ex6_xu0_rt_q)); + +tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) ex7_xu0_rt_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex6_xu0_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex7_xu0_rt_offset:ex7_xu0_rt_offset + 2**`GPR_WIDTH_ENC - 1]), + .scout(sov[ex7_xu0_rt_offset:ex7_xu0_rt_offset + 2**`GPR_WIDTH_ENC - 1]), + .din(ex7_xu0_rt_d), + .dout(ex7_xu0_rt_q)); + +tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) ex8_xu0_rt_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex7_xu0_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex8_xu0_rt_offset:ex8_xu0_rt_offset + 2**`GPR_WIDTH_ENC - 1]), + .scout(sov[ex8_xu0_rt_offset:ex8_xu0_rt_offset + 2**`GPR_WIDTH_ENC - 1]), + .din(ex7_xu0_rt_q), + .dout(ex8_xu0_rt_q)); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_xu0_req_abort_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_xu0_req_abort_offset]), + .scout(sov[ex4_xu0_req_abort_offset]), + .din(ex4_xu0_req_abort_d), + .dout(ex4_xu0_req_abort_q)); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_xu0_req_abort_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_xu0_req_abort_offset]), + .scout(sov[ex5_xu0_req_abort_offset]), + .din(ex5_xu0_req_abort_d), + .dout(ex5_xu0_req_abort_q)); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_xu0_req_abort_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_xu0_req_abort_offset]), + .scout(sov[ex6_xu0_req_abort_offset]), + .din(ex6_xu0_req_abort_d), + .dout(ex6_xu0_req_abort_q)); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex7_xu0_req_abort_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex7_xu0_req_abort_offset]), + .scout(sov[ex7_xu0_req_abort_offset]), + .din(ex7_xu0_req_abort_d), + .dout(ex7_xu0_req_abort_q)); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex8_xu0_req_abort_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex8_xu0_req_abort_offset]), + .scout(sov[ex8_xu0_req_abort_offset]), + .din(ex8_xu0_req_abort_d), + .dout(ex8_xu0_req_abort_q)); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex9_xu0_req_abort_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex9_xu0_req_abort_offset]), + .scout(sov[ex9_xu0_req_abort_offset]), + .din(ex9_xu0_req_abort_d), + .dout(ex9_xu0_req_abort_q)); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex10_xu0_req_abort_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex10_xu0_req_abort_offset]), + .scout(sov[ex10_xu0_req_abort_offset]), + .din(ex10_xu0_req_abort_d), + .dout(ex10_xu0_req_abort_q)); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex11_xu0_req_abort_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex11_xu0_req_abort_offset]), + .scout(sov[ex11_xu0_req_abort_offset]), + .din(ex11_xu0_req_abort_d), + .dout(ex11_xu0_req_abort_q)); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex12_xu0_req_abort_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex12_xu0_req_abort_offset]), + .scout(sov[ex12_xu0_req_abort_offset]), + .din(ex12_xu0_req_abort_d), + .dout(ex12_xu0_req_abort_q)); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex13_xu0_req_abort_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex13_xu0_req_abort_offset]), + .scout(sov[ex13_xu0_req_abort_offset]), + .din(ex13_xu0_req_abort_d), + .dout(ex13_xu0_req_abort_q)); + +tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) ex4_xu1_rt_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_xu1_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_xu1_rt_offset:ex4_xu1_rt_offset + 2**`GPR_WIDTH_ENC - 1]), + .scout(sov[ex4_xu1_rt_offset:ex4_xu1_rt_offset + 2**`GPR_WIDTH_ENC - 1]), + .din(xu1_lq_ex3_rt), + .dout(ex4_xu1_rt_q)); + +tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) ex5_xu1_rt_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex4_xu1_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_xu1_rt_offset:ex5_xu1_rt_offset + 2**`GPR_WIDTH_ENC - 1]), + .scout(sov[ex5_xu1_rt_offset:ex5_xu1_rt_offset + 2**`GPR_WIDTH_ENC - 1]), + .din(ex4_xu1_rt_q), + .dout(ex5_xu1_rt_q)); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_xu1_req_abort_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_xu1_req_abort_offset]), + .scout(sov[ex4_xu1_req_abort_offset]), + .din(ex4_xu1_req_abort_d), + .dout(ex4_xu1_req_abort_q)); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_xu1_req_abort_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_xu1_req_abort_offset]), + .scout(sov[ex5_xu1_req_abort_offset]), + .din(ex5_xu1_req_abort_d), + .dout(ex5_xu1_req_abort_q)); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_xu1_req_abort_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_xu1_req_abort_offset]), + .scout(sov[ex6_xu1_req_abort_offset]), + .din(ex6_xu1_req_abort_d), + .dout(ex6_xu1_req_abort_q)); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex7_xu1_req_abort_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex7_xu1_req_abort_offset]), + .scout(sov[ex7_xu1_req_abort_offset]), + .din(ex7_xu1_req_abort_d), + .dout(ex7_xu1_req_abort_q)); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex8_xu1_req_abort_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex8_xu1_req_abort_offset]), + .scout(sov[ex8_xu1_req_abort_offset]), + .din(ex8_xu1_req_abort_d), + .dout(ex8_xu1_req_abort_q)); + +tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) rel3_rel_rt_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(dcc_byp_rel2_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rel3_rel_rt_offset:rel3_rel_rt_offset + 2**`GPR_WIDTH_ENC - 1]), + .scout(sov[rel3_rel_rt_offset:rel3_rel_rt_offset + 2**`GPR_WIDTH_ENC - 1]), + .din(rel3_rel_rt_d), + .dout(rel3_rel_rt_q)); + +tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) rel4_rel_rt_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(dcc_byp_rel3_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rel4_rel_rt_offset:rel4_rel_rt_offset + 2**`GPR_WIDTH_ENC - 1]), + .scout(sov[rel4_rel_rt_offset:rel4_rel_rt_offset + 2**`GPR_WIDTH_ENC - 1]), + .din(rel4_rel_rt_d), + .dout(rel4_rel_rt_q)); + +tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) ex6_fx_ld_data_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(dec_byp_ex5_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_fx_ld_data_offset:ex6_fx_ld_data_offset + 2**`GPR_WIDTH_ENC - 1]), + .scout(sov[ex6_fx_ld_data_offset:ex6_fx_ld_data_offset + 2**`GPR_WIDTH_ENC - 1]), + .din(ex6_fx_ld_data_d), + .dout(ex6_fx_ld_data_q)); + +tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) ex7_fx_ld_data_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(dec_byp_ex6_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex7_fx_ld_data_offset:ex7_fx_ld_data_offset + 2**`GPR_WIDTH_ENC - 1]), + .scout(sov[ex7_fx_ld_data_offset:ex7_fx_ld_data_offset + 2**`GPR_WIDTH_ENC - 1]), + .din(ex7_fx_ld_data_d), + .dout(ex7_fx_ld_data_q)); + +tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) ex8_fx_ld_data_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(dec_byp_ex7_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex8_fx_ld_data_offset:ex8_fx_ld_data_offset + 2**`GPR_WIDTH_ENC - 1]), + .scout(sov[ex8_fx_ld_data_offset:ex8_fx_ld_data_offset + 2**`GPR_WIDTH_ENC - 1]), + .din(ex8_fx_ld_data_d), + .dout(ex8_fx_ld_data_q)); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_req_aborted_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_req_aborted_offset]), + .scout(sov[ex3_req_aborted_offset]), + .din(ex3_req_aborted_d), + .dout(ex3_req_aborted_q)); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_req_aborted_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_req_aborted_offset]), + .scout(sov[ex4_req_aborted_offset]), + .din(ex4_req_aborted_d), + .dout(ex4_req_aborted_q)); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_req_aborted_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_req_aborted_offset]), + .scout(sov[ex5_req_aborted_offset]), + .din(ex5_req_aborted_d), + .dout(ex5_req_aborted_q)); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_lq_req_abort_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_lq_req_abort_offset]), + .scout(sov[ex6_lq_req_abort_offset]), + .din(ex6_lq_req_abort_d), + .dout(ex6_lq_req_abort_q)); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex7_lq_req_abort_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex7_lq_req_abort_offset]), + .scout(sov[ex7_lq_req_abort_offset]), + .din(ex7_lq_req_abort_d), + .dout(ex7_lq_req_abort_q)); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex8_lq_req_abort_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex8_lq_req_abort_offset]), + .scout(sov[ex8_lq_req_abort_offset]), + .din(ex8_lq_req_abort_d), + .dout(ex8_lq_req_abort_q)); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex9_lq_req_abort_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex9_lq_req_abort_offset]), + .scout(sov[ex9_lq_req_abort_offset]), + .din(ex9_lq_req_abort_d), + .dout(ex9_lq_req_abort_q)); + +tri_rlmreg_p #(.WIDTH((2**`GPR_WIDTH_ENC)+(2**`GPR_WIDTH_ENC)/8), .INIT(0), .NEEDS_SRESET(1)) ex6_gpr_wd0_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(dec_byp_ex5_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_gpr_wd0_offset:ex6_gpr_wd0_offset + (2**`GPR_WIDTH_ENC)+(2**`GPR_WIDTH_ENC)/8 - 1]), + .scout(sov[ex6_gpr_wd0_offset:ex6_gpr_wd0_offset + (2**`GPR_WIDTH_ENC)+(2**`GPR_WIDTH_ENC)/8 - 1]), + .din(ex6_gpr_wd0_d), + .dout(ex6_gpr_wd0_q)); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_move_data_sel_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_move_data_sel_offset]), + .scout(sov[ex5_move_data_sel_offset]), + .din(ex5_move_data_sel_d), + .dout(ex5_move_data_sel_q)); + +tri_rlmreg_p #(.WIDTH(`STQ_DATA_SIZE), .INIT(0), .NEEDS_SRESET(1)) ex5_mv_rel_data_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex4_move_data_sel), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_mv_rel_data_offset:ex5_mv_rel_data_offset + `STQ_DATA_SIZE - 1]), + .scout(sov[ex5_mv_rel_data_offset:ex5_mv_rel_data_offset + `STQ_DATA_SIZE - 1]), + .din(ex5_mv_rel_data_d), + .dout(ex5_mv_rel_data_q)); + +tri_rlmreg_p #(.WIDTH((2**`GPR_WIDTH_ENC)/8), .INIT(0), .NEEDS_SRESET(1)) ex6_dvc1_cmp_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(dec_byp_ex5_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_dvc1_cmp_offset:ex6_dvc1_cmp_offset + (2**`GPR_WIDTH_ENC)/8 - 1]), + .scout(sov[ex6_dvc1_cmp_offset:ex6_dvc1_cmp_offset + (2**`GPR_WIDTH_ENC)/8 - 1]), + .din(ex6_dvc1_cmp_d), + .dout(ex6_dvc1_cmp_q)); + +tri_rlmreg_p #(.WIDTH((2**`GPR_WIDTH_ENC)/8), .INIT(0), .NEEDS_SRESET(1)) ex6_dvc2_cmp_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(dec_byp_ex5_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_dvc2_cmp_offset:ex6_dvc2_cmp_offset + (2**`GPR_WIDTH_ENC)/8 - 1]), + .scout(sov[ex6_dvc2_cmp_offset:ex6_dvc2_cmp_offset + (2**`GPR_WIDTH_ENC)/8 - 1]), + .din(ex6_dvc2_cmp_d), + .dout(ex6_dvc2_cmp_q)); + +tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) lq_pc_ram_data_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(dcc_byp_ram_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lq_pc_ram_data_offset:lq_pc_ram_data_offset + 2**`GPR_WIDTH_ENC - 1]), + .scout(sov[lq_pc_ram_data_offset:lq_pc_ram_data_offset + 2**`GPR_WIDTH_ENC - 1]), + .din(lq_pc_ram_data_d), + .dout(lq_pc_ram_data_q)); + +//------------------------------------ +// ACTs +//------------------------------------ + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_xu0_stg_act_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_xu0_stg_act_offset]), + .scout(sov[ex4_xu0_stg_act_offset]), + .din(ex4_xu0_stg_act_d), + .dout(ex4_xu0_stg_act_q)); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_xu0_stg_act_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_xu0_stg_act_offset]), + .scout(sov[ex5_xu0_stg_act_offset]), + .din(ex5_xu0_stg_act_d), + .dout(ex5_xu0_stg_act_q)); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_xu0_stg_act_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_xu0_stg_act_offset]), + .scout(sov[ex6_xu0_stg_act_offset]), + .din(ex6_xu0_stg_act_d), + .dout(ex6_xu0_stg_act_q)); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex7_xu0_stg_act_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex7_xu0_stg_act_offset]), + .scout(sov[ex7_xu0_stg_act_offset]), + .din(ex7_xu0_stg_act_d), + .dout(ex7_xu0_stg_act_q)); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_xu1_stg_act_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_xu1_stg_act_offset]), + .scout(sov[ex4_xu1_stg_act_offset]), + .din(ex4_xu1_stg_act_d), + .dout(ex4_xu1_stg_act_q)); + +assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in}; +assign scan_out = sov[0]; + +endmodule diff --git a/dev/verilog/work/lq_ctl.v b/dev/verilog/work/lq_ctl.v new file mode 100755 index 0000000..b533fbd --- /dev/null +++ b/dev/verilog/work/lq_ctl.v @@ -0,0 +1,3727 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +// Description: XU LSU Control +// +//***************************************************************************** + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" + +module lq_ctl( + xu_lq_spr_ccr2_en_trace, + xu_lq_spr_ccr2_en_pc, + xu_lq_spr_ccr2_en_ditc, + xu_lq_spr_ccr2_en_icswx, + xu_lq_spr_ccr2_dfrat, + xu_lq_spr_ccr2_dfratsc, + xu_lq_spr_ccr2_ap, + xu_lq_spr_ccr2_ucode_dis, + xu_lq_spr_ccr2_notlb, + xu_lq_spr_xucr0_clkg_ctl, + xu_lq_spr_xucr0_wlk, + xu_lq_spr_xucr0_mbar_ack, + xu_lq_spr_xucr0_tlbsync, + xu_lq_spr_xucr0_dcdis, + xu_lq_spr_xucr0_aflsta, + xu_lq_spr_xucr0_flsta, + xu_lq_spr_xucr0_clfc, + xu_lq_spr_xucr0_cls, + xu_lq_spr_xucr0_trace_um, + xu_lq_spr_xucr0_mddp, + xu_lq_spr_xucr0_mdcp, + xu_lq_spr_xucr4_mmu_mchk, + xu_lq_spr_xucr4_mddmh, + xu_lq_spr_msr_cm, + xu_lq_spr_msr_ds, + xu_lq_spr_msr_fp, + xu_lq_spr_msr_spv, + xu_lq_spr_msr_gs, + xu_lq_spr_msr_pr, + xu_lq_spr_msr_de, + xu_lq_spr_msr_ucle, + xu_lq_spr_msrp_uclep, + xu_lq_spr_dbcr0_dac1, + xu_lq_spr_dbcr0_dac2, + xu_lq_spr_dbcr0_dac3, + xu_lq_spr_dbcr0_dac4, + xu_lq_spr_dbcr0_idm, + xu_lq_spr_epcr_duvd, + lq_xu_spr_xucr0_cul, + lq_xu_spr_xucr0_cslc_xuop, + lq_xu_spr_xucr0_cslc_binv, + lq_xu_spr_xucr0_clo, + lq_iu_spr_dbcr3_ivc, + slowspr_val_in, + slowspr_rw_in, + slowspr_etid_in, + slowspr_addr_in, + slowspr_data_in, + slowspr_done_in, + slowspr_val_out, + slowspr_rw_out, + slowspr_etid_out, + slowspr_addr_out, + slowspr_data_out, + slowspr_done_out, + iu_lq_cp_flush, + iu_lq_recirc_val, + iu_lq_cp_next_itag, + iu_lq_isync, + iu_lq_csync, + lq0_iu_execute_vld, + lq0_iu_recirc_val, + lq0_iu_itag, + lq0_iu_flush2ucode, + lq0_iu_flush2ucode_type, + lq0_iu_exception_val, + lq0_iu_exception, + lq0_iu_dear_val, + lq0_iu_n_flush, + lq0_iu_np1_flush, + lq0_iu_dacr_type, + lq0_iu_dacrw, + lq0_iu_instr, + lq0_iu_eff_addr, + rv_lq_rv1_i0_vld, + rv_lq_rv1_i0_ucode_preissue, + rv_lq_rv1_i0_2ucode, + rv_lq_rv1_i0_ucode_cnt, + rv_lq_rv1_i0_rte_lq, + rv_lq_rv1_i0_isLoad, + rv_lq_rv1_i0_ifar, + rv_lq_rv1_i0_itag, + rv_lq_rv1_i1_vld, + rv_lq_rv1_i1_ucode_preissue, + rv_lq_rv1_i1_2ucode, + rv_lq_rv1_i1_ucode_cnt, + rv_lq_rv1_i1_rte_lq, + rv_lq_rv1_i1_isLoad, + rv_lq_rv1_i1_ifar, + rv_lq_rv1_i1_itag, + odq_pf_report_tid, + odq_pf_report_itag, + odq_pf_resolved, + xu_lq_act, + xu_lq_val, + xu_lq_is_eratre, + xu_lq_is_eratwe, + xu_lq_is_eratsx, + xu_lq_is_eratilx, + xu_lq_ws, + xu_lq_ra_entry, + xu_lq_rs_data, + xu_lq_hold_req, + lq_xu_ex5_data, + lq_xu_ord_par_err, + lq_xu_ord_read_done, + lq_xu_ord_write_done, + rv_lq_vld, + rv_lq_ex0_itag, + rv_lq_ex0_instr, + rv_lq_ex0_ucode, + rv_lq_ex0_ucode_cnt, + rv_lq_ex0_t1_v, + rv_lq_ex0_t1_p, + rv_lq_ex0_t3_p, + rv_lq_ex0_s1_v, + rv_lq_ex0_s2_v, + lq_rv_itag0, + lq_rv_itag0_vld, + lq_rv_itag0_abort, + lq_rv_ex2_s1_abort, + lq_rv_ex2_s2_abort, + lq_rv_hold_all, + lq_rv_itag1_vld, + lq_rv_itag1, + lq_rv_itag1_restart, + lq_rv_itag1_abort, + lq_rv_itag1_hold, + lq_rv_itag1_cord, + lq_rv_clr_hold, + rv_lq_ex0_s1_xu0_sel, + rv_lq_ex0_s2_xu0_sel, + rv_lq_ex0_s1_xu1_sel, + rv_lq_ex0_s2_xu1_sel, + rv_lq_ex0_s1_lq_sel, + rv_lq_ex0_s2_lq_sel, + rv_lq_ex0_s1_rel_sel, + rv_lq_ex0_s2_rel_sel, + xu_lq_xer_cp_rd, + rv_lq_gpr_ex1_r0d, + rv_lq_gpr_ex1_r1d, + lq_rv_gpr_ex6_we, + lq_rv_gpr_ex6_wa, + lq_rv_gpr_ex6_wd, + lq_xu_gpr_ex5_we, + lq_xu_gpr_ex5_wa, + lq_rv_gpr_rel_we, + lq_xu_gpr_rel_we, + lq_xu_axu_rel_we, + lq_rv_gpr_rel_wa, + lq_xu_gpr_rel_wa, + lq_rv_gpr_rel_wd, + lq_xu_gpr_rel_wd, + lq_xu_cr_ex5_we, + lq_xu_cr_ex5_wa, + xu0_lq_ex3_act, + xu0_lq_ex3_abort, + xu0_lq_ex3_rt, + xu0_lq_ex4_rt, + xu0_lq_ex6_act, + xu0_lq_ex6_rt, + lq_xu_ex5_act, + lq_xu_ex5_cr, + lq_xu_ex5_rt, + lq_xu_ex5_abort, + xu1_lq_ex3_act, + xu1_lq_ex3_abort, + xu1_lq_ex3_rt, + lq_xu_axu_ex4_addr, + lq_xu_axu_ex5_we, + lq_xu_axu_ex5_le, + mm_lq_hold_req, + mm_lq_hold_done, + mm_lq_pid, + mm_lq_lsu_lpidr, + mm_lq_mmucr0, + mm_lq_mmucr1, + mm_lq_rel_val, + mm_lq_rel_data, + mm_lq_rel_emq, + mm_lq_itag, + mm_lq_tlb_miss, + mm_lq_tlb_inelig, + mm_lq_pt_fault, + mm_lq_lrat_miss, + mm_lq_tlb_multihit, + mm_lq_tlb_par_err, + mm_lq_lru_par_err, + mm_lq_snoop_coming, + mm_lq_snoop_val, + mm_lq_snoop_attr, + mm_lq_snoop_vpn, + lq_mm_snoop_ack, + lq_mm_req, + lq_mm_req_nonspec, + lq_mm_req_itag, + lq_mm_req_epn, + lq_mm_thdid, + lq_mm_req_emq, + lq_mm_ttype, + lq_mm_state, + lq_mm_lpid, + lq_mm_tid, + lq_mm_mmucr0_we, + lq_mm_mmucr0, + lq_mm_mmucr1_we, + lq_mm_mmucr1, + lq_mm_perf_dtlb, + pc_lq_inj_dcachedir_ldp_parity, + pc_lq_inj_dcachedir_ldp_multihit, + pc_lq_inj_dcachedir_stp_parity, + pc_lq_inj_dcachedir_stp_multihit, + pc_lq_inj_prefetcher_parity, + lsq_ctl_oldest_tid, + lsq_ctl_oldest_itag, + lsq_ctl_stq1_stg_act, + lsq_ctl_rv0_back_inv, + lsq_ctl_rv1_back_inv_addr, + lsq_ctl_stq_release_itag_vld, + lsq_ctl_stq_release_itag, + lsq_ctl_stq_release_tid, + lsq_ctl_ex5_ldq_restart, + lsq_ctl_ex5_stq_restart, + lsq_ctl_ex5_stq_restart_miss, + lsq_ctl_ex5_fwd_val, + lsq_ctl_ex5_fwd_data, + lsq_ctl_rv_hold_all, + lsq_ctl_rv_set_hold, + lsq_ctl_rv_clr_hold, + lsq_ctl_stq1_val, + lsq_ctl_stq1_mftgpr_val, + lsq_ctl_stq1_mfdpf_val, + lsq_ctl_stq1_mfdpa_val, + lsq_ctl_stq1_thrd_id, + lsq_ctl_rel1_thrd_id, + lsq_ctl_stq1_resv, + lsq_ctl_stq1_ci, + lsq_ctl_stq1_axu_val, + lsq_ctl_stq1_epid_val, + lsq_ctl_stq1_store_val, + lsq_ctl_stq1_lock_clr, + lsq_ctl_stq1_watch_clr, + lsq_ctl_stq1_l_fld, + lsq_ctl_stq1_inval, + lsq_ctl_stq1_dci_val, + lsq_ctl_stq1_addr, + lsq_ctl_stq4_xucr0_cul, + lsq_ctl_rel1_gpr_val, + lsq_ctl_rel1_ta_gpr, + lsq_ctl_rel1_upd_gpr, + lsq_ctl_rel1_clr_val, + lsq_ctl_rel1_set_val, + lsq_ctl_rel1_data_val, + lsq_ctl_rel1_back_inv, + lsq_ctl_rel1_tag, + lsq_ctl_rel1_classid, + lsq_ctl_rel1_lock_set, + lsq_ctl_rel1_watch_set, + lsq_ctl_rel2_blk_req, + lsq_ctl_rel2_data, + lsq_ctl_stq2_blk_req, + lsq_ctl_stq5_itag, + lsq_ctl_stq5_tgpr, + lsq_ctl_rel2_upd_val, + lsq_ctl_rel3_l1dump_val, + lsq_ctl_rel3_clr_relq, + ctl_lsq_stq4_perr_reject, + ctl_dat_stq5_way_perr_inval, + lsq_ctl_ex3_strg_val, + lsq_ctl_ex3_strg_noop, + lsq_ctl_ex3_illeg_lswx, + lsq_ctl_ex3_ct_val, + lsq_ctl_ex3_be_ct, + lsq_ctl_ex3_le_ct, + lsq_ctl_stq_cpl_ready, + lsq_ctl_stq_cpl_ready_itag, + lsq_ctl_stq_cpl_ready_tid, + lsq_ctl_stq_n_flush, + lsq_ctl_stq_np1_flush, + lsq_ctl_stq_exception_val, + lsq_ctl_stq_exception, + lsq_ctl_stq_dacrw, + lsq_ctl_sync_in_stq, + lsq_ctl_sync_done, + ctl_lsq_stq_cpl_blk, + ctl_lsq_ex_pipe_full, + ctl_lsq_ex2_streq_val, + ctl_lsq_ex2_itag, + ctl_lsq_ex2_thrd_id, + ctl_lsq_ex3_ldreq_val, + ctl_lsq_ex3_wchkall_val, + ctl_lsq_ex3_pfetch_val, + ctl_lsq_ex3_byte_en, + ctl_lsq_ex3_p_addr, + ctl_lsq_ex3_thrd_id, + ctl_lsq_ex3_algebraic, + ctl_lsq_ex3_opsize, + ctl_lsq_ex4_ldreq_val, + ctl_lsq_ex4_binvreq_val, + ctl_lsq_ex4_streq_val, + ctl_lsq_ex4_othreq_val, + ctl_lsq_ex4_p_addr, + ctl_lsq_ex4_dReq_val, + ctl_lsq_ex4_gath_load, + ctl_lsq_ex4_send_l2, + ctl_lsq_ex4_has_data, + ctl_lsq_ex4_cline_chk, + ctl_lsq_ex4_wimge, + ctl_lsq_ex4_byte_swap, + ctl_lsq_ex4_is_sync, + ctl_lsq_ex4_all_thrd_chk, + ctl_lsq_ex4_is_store, + ctl_lsq_ex4_is_resv, + ctl_lsq_ex4_is_mfgpr, + ctl_lsq_ex4_is_icswxr, + ctl_lsq_ex4_is_icbi, + ctl_lsq_ex4_watch_clr, + ctl_lsq_ex4_watch_clr_all, + ctl_lsq_ex4_mtspr_trace, + ctl_lsq_ex4_is_inval_op, + ctl_lsq_ex4_is_cinval, + ctl_lsq_ex5_lock_clr, + ctl_lsq_ex5_lock_set, + ctl_lsq_ex5_watch_set, + ctl_lsq_ex5_tgpr, + ctl_lsq_ex5_axu_val, + ctl_lsq_ex5_is_epid, + ctl_lsq_ex5_usr_def, + ctl_lsq_ex5_drop_rel, + ctl_lsq_ex5_flush_req, + ctl_lsq_ex5_flush_pfetch, + ctl_lsq_ex5_cmmt_events, + ctl_lsq_ex5_perf_val0, + ctl_lsq_ex5_perf_sel0, + ctl_lsq_ex5_perf_val1, + ctl_lsq_ex5_perf_sel1, + ctl_lsq_ex5_perf_val2, + ctl_lsq_ex5_perf_sel2, + ctl_lsq_ex5_perf_val3, + ctl_lsq_ex5_perf_sel3, + ctl_lsq_ex5_not_touch, + ctl_lsq_ex5_class_id, + ctl_lsq_ex5_dvc, + ctl_lsq_ex5_dacrw, + ctl_lsq_ex5_ttype, + ctl_lsq_ex5_l_fld, + ctl_lsq_ex5_load_hit, + lsq_ctl_ex6_ldq_events, + lsq_ctl_ex6_stq_events, + ctl_lsq_ex6_ldh_dacrw, + ctl_lsq_stq3_icswx_data, + ctl_lsq_dbg_int_en, + ctl_lsq_ldp_idle, + ctl_lsq_rv1_dir_rd_val, + ctl_lsq_spr_lsucr0_ford, + ctl_lsq_spr_lsucr0_b2b, + ctl_lsq_spr_lsucr0_lge, + ctl_lsq_spr_lsucr0_lca, + ctl_lsq_spr_lsucr0_sca, + ctl_lsq_spr_lsucr0_dfwd, + ctl_lsq_ex4_xu1_data, + ctl_lsq_pf_empty, + dir_arr_wr_enable, + dir_arr_wr_way, + dir_arr_wr_addr, + dir_arr_wr_data, + dir_arr_rd_data1, + ctl_dat_ex1_data_act, + ctl_dat_ex2_eff_addr, + ctl_dat_ex3_opsize, + ctl_dat_ex3_le_mode, + ctl_dat_ex3_le_ld_rotsel, + ctl_dat_ex3_be_ld_rotsel, + ctl_dat_ex3_algebraic, + ctl_dat_ex3_le_alg_rotsel, + ctl_dat_ex4_way_hit, + dat_ctl_dcarr_perr_way, + dat_ctl_ex5_load_data, + dat_ctl_stq6_axu_data, + stq4_dcarr_wren, + stq4_dcarr_way_en, + ctl_spr_dvc1_dbg, + ctl_spr_dvc2_dbg, + ctl_perv_spr_lesr1, + ctl_perv_spr_lesr2, + ctl_spr_dbcr2_dvc1be, + ctl_spr_dbcr2_dvc2be, + ctl_spr_dbcr2_dvc1m, + ctl_spr_dbcr2_dvc2m, + ctl_perv_ex6_perf_events, + ctl_perv_stq4_perf_events, + ctl_perv_dir_perf_events, + lq_pc_err_derat_parity, + lq_pc_err_dir_ldp_parity, + lq_pc_err_dir_stp_parity, + lq_pc_err_dcache_parity, + lq_pc_err_derat_multihit, + lq_pc_err_dir_ldp_multihit, + lq_pc_err_dir_stp_multihit, + lq_pc_err_prefetcher_parity, + vcs, + vdd, + gnd, + nclk, + sg_2, + fce_2, + func_sl_thold_2, + func_nsl_thold_2, + func_slp_sl_thold_2, + func_slp_nsl_thold_2, + pc_lq_init_reset, + pc_lq_ccflush_dc, + clkoff_dc_b, + d_mode_dc, + delay_lclkr_dc, + mpw1_dc_b, + mpw2_dc_b, + g8t_clkoff_dc_b, + g8t_d_mode_dc, + g8t_delay_lclkr_dc, + g8t_mpw1_dc_b, + g8t_mpw2_dc_b, + cfg_slp_sl_thold_2, + cfg_sl_thold_2, + regf_slp_sl_thold_2, + abst_sl_thold_2, + abst_slp_sl_thold_2, + time_sl_thold_2, + ary_nsl_thold_2, + ary_slp_nsl_thold_2, + repr_sl_thold_2, + bolt_sl_thold_2, + bo_enable_2, + an_ac_scan_dis_dc_b, + an_ac_scan_diag_dc, + an_ac_lbist_en_dc, + an_ac_atpg_en_dc, + an_ac_grffence_en_dc, + an_ac_lbist_ary_wrt_thru_dc, + pc_lq_abist_ena_dc, + pc_lq_abist_raw_dc_b, + pc_lq_bo_unload, + pc_lq_bo_repair, + pc_lq_bo_reset, + pc_lq_bo_shdata, + pc_lq_bo_select, + lq_pc_bo_fail, + lq_pc_bo_diagout, + pc_lq_ram_active, + lq_pc_ram_data_val, + lq_pc_ram_data, + pc_lq_abist_wl64_comp_ena, + pc_lq_abist_g8t_wenb, + pc_lq_abist_g8t1p_renb_0, + pc_lq_abist_g8t_dcomp, + pc_lq_abist_g8t_bw_1, + pc_lq_abist_g8t_bw_0, + pc_lq_abist_di_0, + pc_lq_abist_waddr_0, + pc_lq_abist_raddr_0, + cam_clkoff_dc_b, + cam_d_mode_dc, + cam_act_dis_dc, + cam_delay_lclkr_dc, + cam_mpw1_dc_b, + cam_mpw2_dc_b, + abst_scan_in, + time_scan_in, + repr_scan_in, + func_scan_in, + regf_scan_in, + ccfg_scan_in, + abst_scan_out, + time_scan_out, + repr_scan_out, + func_scan_out, + regf_scan_out, + ccfg_scan_out +); + +//------------------------------------------------------------------- +// Generics +//------------------------------------------------------------------- +//parameter EXPAND_TYPE = 2; +//parameter `GPR_WIDTH_ENC = 6; +//parameter `XER_POOL_ENC = 4; +//parameter `CR_POOL_ENC = 5; +//parameter `GPR_POOL_ENC = 6; +//parameter `AXU_SPARE_ENC = 3; +//parameter `THREADS_POOL_ENC = 1; +//parameter `ITAG_SIZE_ENC = 7; // Instruction Tag Size +//parameter `CR_WIDTH = 4; +//parameter `UCODE_ENTRIES_ENC = 3; +//parameter `STQ_DATA_SIZE = 64; // 64 or 128 Bit store data sizes supported +//parameter ``FXU0_PIPE_START = 2; +//parameter `XU0_PIPE_END = 8; +//parameter ``FXU1_PIPE_START = 2; +//parameter `XU1_PIPE_END = 5; +//parameter `LQ_LOAD_PIPE_START = 4; +//parameter `LQ_LOAD_PIPE_END = 8; +//parameter `LQ_REL_PIPE_START = 2; +//parameter `LQ_REL_PIPE_END = 4; +//parameter `THREADS = 2; +//parameter `DC_SIZE = 15; // 14 => 16K L1D$, 15 => 32K L1D$ +//parameter `CL_SIZE = 6; +//parameter `LMQ_ENTRIES = 8; +//parameter `EMQ_ENTRIES = 4; +//parameter `REAL_IFAR_WIDTH = 42; // 42 bit real address +//parameter `LDSTQ_ENTRIES = 16; // Order Queue Size +//parameter `PF_IFAR_WIDTH = 12; // number of IAR bits used by prefetch +//parameter `BUILD_PFETCH = 1; // 1=> include pfetch in the build, 0=> build without pfetch +//parameter `PFETCH_INITIAL_DEPTH = 0; // the initial value for the SPR that determines how many lines to prefetch +//parameter ``PFETCH_Q_SIZE_ENC = 3; // number of bits to address queue size (3 => 8 entries, 4 => 16 entries) +//parameter `PFETCH_Q_SIZE = 8; // number of entries in prefetch queue +parameter WAYDATASIZE = 34; // TagSize + Parity Bits +parameter XU0_PIPE_START = `FXU0_PIPE_START+1; +parameter XU0_PIPE_END = `FXU0_PIPE_END; +parameter XU1_PIPE_START = `FXU1_PIPE_START+1; +parameter XU1_PIPE_END = `FXU1_PIPE_END; + +//-------------------------------------------------------------- +// SPR Interface +//-------------------------------------------------------------- +input xu_lq_spr_ccr2_en_trace; // MTSPR Trace is Enabled +input xu_lq_spr_ccr2_en_pc; // MSGSND is Enabled +input xu_lq_spr_ccr2_en_ditc; // DITC is Enabled +input xu_lq_spr_ccr2_en_icswx; // ICSWX is Enabled +input xu_lq_spr_ccr2_dfrat; // Force Real Address Translation +input [0:8] xu_lq_spr_ccr2_dfratsc; // 0:4: wimge, 5:8: u0:3 +input xu_lq_spr_ccr2_ap; // AP Available +input xu_lq_spr_ccr2_ucode_dis; // Ucode Disabled +input xu_lq_spr_ccr2_notlb; // MMU is disabled +input xu_lq_spr_xucr0_clkg_ctl; // Clock Gating Override +input xu_lq_spr_xucr0_wlk; // Data Cache Way Locking Enable +input xu_lq_spr_xucr0_mbar_ack; // L2 ACK of membar and lwsync +input xu_lq_spr_xucr0_tlbsync; // L2 ACK of tlbsync +input xu_lq_spr_xucr0_dcdis; // Data Cache Disable +input xu_lq_spr_xucr0_aflsta; // AXU Force Load/Store Alignment interrupt +input xu_lq_spr_xucr0_flsta; // FX Force Load/Store Alignment interrupt +input xu_lq_spr_xucr0_clfc; // Cache Directory Lock Flash Clear +input xu_lq_spr_xucr0_cls; // Cacheline Size = 1 => 128Byte size, 0 => 64Byte size +input [0:`THREADS-1] xu_lq_spr_xucr0_trace_um; // TRACE SPR is Enabled in user mode +input xu_lq_spr_xucr0_mddp; // Machine Check on Data Cache Directory Parity Error +input xu_lq_spr_xucr0_mdcp; // Machine Check on Data Cache Parity Error +input xu_lq_spr_xucr4_mmu_mchk; // Machine Check on a Data ERAT Parity or Multihit Error +input xu_lq_spr_xucr4_mddmh; // Machine Check on Data Cache Directory Multihit Error +input [0:`THREADS-1] xu_lq_spr_msr_cm; // 64bit mode enable +input [0:`THREADS-1] xu_lq_spr_msr_ds; // Data Address Space +input [0:`THREADS-1] xu_lq_spr_msr_fp; // FP Available +input [0:`THREADS-1] xu_lq_spr_msr_spv; // VEC Available +input [0:`THREADS-1] xu_lq_spr_msr_gs; // Guest State +input [0:`THREADS-1] xu_lq_spr_msr_pr; // Problem State +input [0:`THREADS-1] xu_lq_spr_msr_de; // Debug Interrupt Enable +input [0:`THREADS-1] xu_lq_spr_msr_ucle; // User Cache Locking Enable +input [0:`THREADS-1] xu_lq_spr_msrp_uclep; // User Cache Locking Enable Protect +input [0:2*`THREADS-1] xu_lq_spr_dbcr0_dac1; // Data Address Compare 1 Debug Event Enable +input [0:2*`THREADS-1] xu_lq_spr_dbcr0_dac2; // Data Address Compare 2 Debug Event Enable +input [0:2*`THREADS-1] xu_lq_spr_dbcr0_dac3; // Data Address Compare 3 Debug Event Enable +input [0:2*`THREADS-1] xu_lq_spr_dbcr0_dac4; // Data Address Compare 4 Debug Event Enable +input [0:`THREADS-1] xu_lq_spr_dbcr0_idm; // Internal Debug Mode Enable +input [0:`THREADS-1] xu_lq_spr_epcr_duvd; // Disable Hypervisor Debug +output lq_xu_spr_xucr0_cul; // Cache Lock unable to lock +output lq_xu_spr_xucr0_cslc_xuop; // Invalidate type instruction invalidated lock +output lq_xu_spr_xucr0_cslc_binv; // Back-Invalidate invalidated lock +output lq_xu_spr_xucr0_clo; // Cache Lock instruction caused an overlock +output [0:`THREADS-1] lq_iu_spr_dbcr3_ivc; // Instruction Value Compare Enabled +input slowspr_val_in; +input slowspr_rw_in; +input [0:1] slowspr_etid_in; +input [0:9] slowspr_addr_in; +input [64-(2**`GPR_WIDTH_ENC):63] slowspr_data_in; +input slowspr_done_in; +output slowspr_val_out; +output slowspr_rw_out; +output [0:1] slowspr_etid_out; +output [0:9] slowspr_addr_out; +output [64-(2**`GPR_WIDTH_ENC):63] slowspr_data_out; +output slowspr_done_out; + +//-------------------------------------------------------------- +// CP Interface +//-------------------------------------------------------------- +input [0:`THREADS-1] iu_lq_cp_flush; +input [0:`THREADS-1] iu_lq_recirc_val; +input [0:`ITAG_SIZE_ENC*`THREADS-1] iu_lq_cp_next_itag; +input iu_lq_isync; +input iu_lq_csync; +output [0:`THREADS-1] lq0_iu_execute_vld; +output [0:`THREADS-1] lq0_iu_recirc_val; +output [0:`ITAG_SIZE_ENC-1] lq0_iu_itag; +output lq0_iu_flush2ucode; +output lq0_iu_flush2ucode_type; +output lq0_iu_exception_val; +output [0:5] lq0_iu_exception; +output [0:`THREADS-1] lq0_iu_dear_val; +output lq0_iu_n_flush; +output lq0_iu_np1_flush; +output lq0_iu_dacr_type; +output [0:3] lq0_iu_dacrw; +output [0:31] lq0_iu_instr; +output [64-(2**`GPR_WIDTH_ENC):63] lq0_iu_eff_addr; + +// IU interface to RV for pfetch predictor table0 +// port 0 +input [0:`THREADS-1] rv_lq_rv1_i0_vld; +input rv_lq_rv1_i0_ucode_preissue; +input rv_lq_rv1_i0_2ucode; +input [0:`UCODE_ENTRIES_ENC-1] rv_lq_rv1_i0_ucode_cnt; +input rv_lq_rv1_i0_rte_lq; +input rv_lq_rv1_i0_isLoad; +input [61-`PF_IFAR_WIDTH+1:61] rv_lq_rv1_i0_ifar; +input [0:`ITAG_SIZE_ENC-1] rv_lq_rv1_i0_itag; + +// port 1 +input [0:`THREADS-1] rv_lq_rv1_i1_vld; +input rv_lq_rv1_i1_ucode_preissue; +input rv_lq_rv1_i1_2ucode; +input [0:`UCODE_ENTRIES_ENC-1] rv_lq_rv1_i1_ucode_cnt; +input rv_lq_rv1_i1_rte_lq; +input rv_lq_rv1_i1_isLoad; +input [61-`PF_IFAR_WIDTH+1:61] rv_lq_rv1_i1_ifar; +input [0:`ITAG_SIZE_ENC-1] rv_lq_rv1_i1_itag; + +// release itag to pfetch +input [0:`THREADS-1] odq_pf_report_tid; +input [0:`ITAG_SIZE_ENC-1] odq_pf_report_itag; +input odq_pf_resolved; + +//-------------------------------------------------------------- +// Interface with XU DERAT +//-------------------------------------------------------------- +input xu_lq_act; +input [0:`THREADS-1] xu_lq_val; +input xu_lq_is_eratre; +input xu_lq_is_eratwe; +input xu_lq_is_eratsx; +input xu_lq_is_eratilx; +input [0:1] xu_lq_ws; +input [0:4] xu_lq_ra_entry; +input [64-(2**`GPR_WIDTH_ENC):63] xu_lq_rs_data; +input xu_lq_hold_req; +output [64-(2**`GPR_WIDTH_ENC):63] lq_xu_ex5_data; +output lq_xu_ord_par_err; +output lq_xu_ord_read_done; +output lq_xu_ord_write_done; + +//-------------------------------------------------------------- +// Interface with RV +//-------------------------------------------------------------- +input [0:`THREADS-1] rv_lq_vld; +input [0:`ITAG_SIZE_ENC-1] rv_lq_ex0_itag; +input [0:31] rv_lq_ex0_instr; +input [0:1] rv_lq_ex0_ucode; +input [0:`UCODE_ENTRIES_ENC-1] rv_lq_ex0_ucode_cnt; +input rv_lq_ex0_t1_v; +input [0:`GPR_POOL_ENC-1] rv_lq_ex0_t1_p; +input [0:`GPR_POOL_ENC-1] rv_lq_ex0_t3_p; +input rv_lq_ex0_s1_v; +input rv_lq_ex0_s2_v; + +output [0:`ITAG_SIZE_ENC-1] lq_rv_itag0; +output [0:`THREADS-1] lq_rv_itag0_vld; +output lq_rv_itag0_abort; +output lq_rv_ex2_s1_abort; +output lq_rv_ex2_s2_abort; +output lq_rv_hold_all; +output [0:`THREADS-1] lq_rv_itag1_vld; +output [0:`ITAG_SIZE_ENC-1] lq_rv_itag1; +output lq_rv_itag1_restart; +output lq_rv_itag1_abort; +output lq_rv_itag1_hold; +output lq_rv_itag1_cord; +output [0:`THREADS-1] lq_rv_clr_hold; + +//------------------------------------------------------------------- +// Interface with Bypass Controller +//------------------------------------------------------------------- +input [2:12] rv_lq_ex0_s1_xu0_sel; +input [2:12] rv_lq_ex0_s2_xu0_sel; +input [2:7] rv_lq_ex0_s1_xu1_sel; +input [2:7] rv_lq_ex0_s2_xu1_sel; +input [4:8] rv_lq_ex0_s1_lq_sel; +input [4:8] rv_lq_ex0_s2_lq_sel; +input [2:3] rv_lq_ex0_s1_rel_sel; +input [2:3] rv_lq_ex0_s2_rel_sel; + +//-------------------------------------------------------------- +// Interface with Regfiles +//-------------------------------------------------------------- +input [0:`THREADS-1] xu_lq_xer_cp_rd; +input [64-(2**`GPR_WIDTH_ENC):63] rv_lq_gpr_ex1_r0d; +input [64-(2**`GPR_WIDTH_ENC):63] rv_lq_gpr_ex1_r1d; +output lq_rv_gpr_ex6_we; +output [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] lq_rv_gpr_ex6_wa; +output [64-(2**`GPR_WIDTH_ENC):64+(((2**`GPR_WIDTH_ENC)-1)/8)] lq_rv_gpr_ex6_wd; +output lq_xu_gpr_ex5_we; +output [0:`AXU_SPARE_ENC+`GPR_POOL_ENC+`THREADS_POOL_ENC-1] lq_xu_gpr_ex5_wa; +output lq_rv_gpr_rel_we; +output lq_xu_gpr_rel_we; +output lq_xu_axu_rel_we; +output [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] lq_rv_gpr_rel_wa; +output [0:`AXU_SPARE_ENC+`GPR_POOL_ENC+`THREADS_POOL_ENC-1] lq_xu_gpr_rel_wa; +output [64-(2**`GPR_WIDTH_ENC):64+(((2**`GPR_WIDTH_ENC)-1)/8)] lq_rv_gpr_rel_wd; +output [(128-`STQ_DATA_SIZE):128+((`STQ_DATA_SIZE-1)/8)] lq_xu_gpr_rel_wd; +output lq_xu_cr_ex5_we; +output [0:`CR_POOL_ENC+`THREADS_POOL_ENC-1] lq_xu_cr_ex5_wa; + +//------------------------------------------------------------------- +// Interface with XU0 +//------------------------------------------------------------------- +input xu0_lq_ex3_act; +input xu0_lq_ex3_abort; +input [64-(2**`GPR_WIDTH_ENC):63] xu0_lq_ex3_rt; +input [64-(2**`GPR_WIDTH_ENC):63] xu0_lq_ex4_rt; +input xu0_lq_ex6_act; +input [64-(2**`GPR_WIDTH_ENC):63] xu0_lq_ex6_rt; +output lq_xu_ex5_act; +output [0:`CR_WIDTH-1] lq_xu_ex5_cr; +output [(128-`STQ_DATA_SIZE):127] lq_xu_ex5_rt; +output lq_xu_ex5_abort; + +//------------------------------------------------------------------- +// Interface with XU1 +//------------------------------------------------------------------- +input xu1_lq_ex3_act; +input xu1_lq_ex3_abort; +input [64-(2**`GPR_WIDTH_ENC):63] xu1_lq_ex3_rt; + +//------------------------------------------------------------------- +// Interface with AXU PassThru with XU +//------------------------------------------------------------------- +output [59:63] lq_xu_axu_ex4_addr; +output lq_xu_axu_ex5_we; +output lq_xu_axu_ex5_le; + +//-------------------------------------------------------------- +// Interface with MMU +//-------------------------------------------------------------- +input mm_lq_hold_req; +input mm_lq_hold_done; +input [0:`THREADS*14-1] mm_lq_pid; +input [0:7] mm_lq_lsu_lpidr; // the LPIDR register +input [0:`THREADS*20-1] mm_lq_mmucr0; +input [0:9] mm_lq_mmucr1; +input [0:4] mm_lq_rel_val; +input [0:131] mm_lq_rel_data; +input [0:`EMQ_ENTRIES-1] mm_lq_rel_emq; +input [0:`ITAG_SIZE_ENC-1] mm_lq_itag; +input [0:`THREADS-1] mm_lq_tlb_miss; // Request got a TLB Miss +input [0:`THREADS-1] mm_lq_tlb_inelig; // Request got a TLB Ineligible +input [0:`THREADS-1] mm_lq_pt_fault; // Request got a PT Fault +input [0:`THREADS-1] mm_lq_lrat_miss; // Request got an LRAT Miss +input [0:`THREADS-1] mm_lq_tlb_multihit; // Request got a TLB Multihit Error +input [0:`THREADS-1] mm_lq_tlb_par_err; // Request got a TLB Parity Error +input [0:`THREADS-1] mm_lq_lru_par_err; // Request got a LRU Parity Error +input mm_lq_snoop_coming; +input mm_lq_snoop_val; +input [0:25] mm_lq_snoop_attr; +input [0:51] mm_lq_snoop_vpn; +output lq_mm_snoop_ack; +output lq_mm_req; +output lq_mm_req_nonspec; +output [0:`ITAG_SIZE_ENC-1] lq_mm_req_itag; +output [64-(2**`GPR_WIDTH_ENC):51] lq_mm_req_epn; +output [0:`THREADS-1] lq_mm_thdid; +output [0:`EMQ_ENTRIES-1] lq_mm_req_emq; +output [0:1] lq_mm_ttype; +output [0:3] lq_mm_state; +output [0:7] lq_mm_lpid; +output [0:13] lq_mm_tid; +output [0:`THREADS-1] lq_mm_mmucr0_we; +output [0:17] lq_mm_mmucr0; +output [0:`THREADS-1] lq_mm_mmucr1_we; +output [0:4] lq_mm_mmucr1; +output [0:`THREADS-1] lq_mm_perf_dtlb; + +//-------------------------------------------------------------- +// Interface with PC +//-------------------------------------------------------------- +input pc_lq_inj_dcachedir_ldp_parity; +input pc_lq_inj_dcachedir_ldp_multihit; +input pc_lq_inj_dcachedir_stp_parity; +input pc_lq_inj_dcachedir_stp_multihit; +input pc_lq_inj_prefetcher_parity; + +//-------------------------------------------------------------- +// Interface with Load/Store Queses +//-------------------------------------------------------------- +input [0:`THREADS-1] lsq_ctl_oldest_tid; +input [0:`ITAG_SIZE_ENC-1] lsq_ctl_oldest_itag; +input lsq_ctl_stq1_stg_act; +input lsq_ctl_rv0_back_inv; +input [64-`REAL_IFAR_WIDTH:63-`CL_SIZE] lsq_ctl_rv1_back_inv_addr; +input lsq_ctl_stq_release_itag_vld; +input [0:`ITAG_SIZE_ENC-1] lsq_ctl_stq_release_itag; +input [0:`THREADS-1] lsq_ctl_stq_release_tid; +input lsq_ctl_ex5_ldq_restart; +input lsq_ctl_ex5_stq_restart; +input lsq_ctl_ex5_stq_restart_miss; +input lsq_ctl_ex5_fwd_val; +input [(128-`STQ_DATA_SIZE):127] lsq_ctl_ex5_fwd_data; +input lsq_ctl_rv_hold_all; +input lsq_ctl_rv_set_hold; +input [0:`THREADS-1] lsq_ctl_rv_clr_hold; +input lsq_ctl_stq1_val; +input lsq_ctl_stq1_mftgpr_val; +input lsq_ctl_stq1_mfdpf_val; +input lsq_ctl_stq1_mfdpa_val; +input [0:`THREADS-1] lsq_ctl_stq1_thrd_id; +input [0:`THREADS-1] lsq_ctl_rel1_thrd_id; +input lsq_ctl_stq1_resv; +input lsq_ctl_stq1_ci; +input lsq_ctl_stq1_axu_val; +input lsq_ctl_stq1_epid_val; +input lsq_ctl_stq1_store_val; +input lsq_ctl_stq1_lock_clr; +input lsq_ctl_stq1_watch_clr; +input [0:1] lsq_ctl_stq1_l_fld; +input lsq_ctl_stq1_inval; +input lsq_ctl_stq1_dci_val; +input [64-`REAL_IFAR_WIDTH:63-`CL_SIZE] lsq_ctl_stq1_addr; +input lsq_ctl_stq4_xucr0_cul; +input lsq_ctl_rel1_gpr_val; +input [0:`AXU_SPARE_ENC+`GPR_POOL_ENC+`THREADS_POOL_ENC-1] lsq_ctl_rel1_ta_gpr; +input lsq_ctl_rel1_upd_gpr; +input lsq_ctl_rel1_clr_val; +input lsq_ctl_rel1_set_val; +input lsq_ctl_rel1_data_val; +input lsq_ctl_rel1_back_inv; +input [0:3] lsq_ctl_rel1_tag; +input [0:1] lsq_ctl_rel1_classid; +input lsq_ctl_rel1_lock_set; +input lsq_ctl_rel1_watch_set; +input lsq_ctl_rel2_blk_req; // Block Reload due to RV issue or Back-Invalidate +input [0:127] lsq_ctl_rel2_data; // Reload PRF Update Data +input lsq_ctl_stq2_blk_req; // Block Store due to RV issue +input [0:`ITAG_SIZE_ENC-1] lsq_ctl_stq5_itag; +input [0:`AXU_SPARE_ENC+`GPR_POOL_ENC+`THREADS_POOL_ENC-1] lsq_ctl_stq5_tgpr; +input lsq_ctl_rel2_upd_val; +input lsq_ctl_rel3_l1dump_val; // Reload Complete for an L1_DUMP reload +input lsq_ctl_rel3_clr_relq; // Reload Complete due to an ECC error +output ctl_lsq_stq4_perr_reject; // STQ4 parity error detect, reject STQ2 Commit +output [0:7] ctl_dat_stq5_way_perr_inval; +input lsq_ctl_ex3_strg_val; +input lsq_ctl_ex3_strg_noop; +input lsq_ctl_ex3_illeg_lswx; +input lsq_ctl_ex3_ct_val; // ICSWX Data is valid +input [0:5] lsq_ctl_ex3_be_ct; // Big Endian Coprocessor Type Select +input [0:5] lsq_ctl_ex3_le_ct; // Little Endian Coprocessor Type Select +input lsq_ctl_stq_cpl_ready; +input [0:`ITAG_SIZE_ENC-1] lsq_ctl_stq_cpl_ready_itag; +input [0:`THREADS-1] lsq_ctl_stq_cpl_ready_tid; +input lsq_ctl_stq_n_flush; +input lsq_ctl_stq_np1_flush; +input lsq_ctl_stq_exception_val; +input [0:5] lsq_ctl_stq_exception; +input [0:3] lsq_ctl_stq_dacrw; +input lsq_ctl_sync_in_stq; +input lsq_ctl_sync_done; +output ctl_lsq_stq_cpl_blk; +output ctl_lsq_ex_pipe_full; +output [0:`THREADS-1] ctl_lsq_ex2_streq_val; +output [0:`ITAG_SIZE_ENC-1] ctl_lsq_ex2_itag; +output [0:`THREADS-1] ctl_lsq_ex2_thrd_id; +output [0:`THREADS-1] ctl_lsq_ex3_ldreq_val; +output [0:`THREADS-1] ctl_lsq_ex3_wchkall_val; +output ctl_lsq_ex3_pfetch_val; +output [0:15] ctl_lsq_ex3_byte_en; +output [58:63] ctl_lsq_ex3_p_addr; +output [0:`THREADS-1] ctl_lsq_ex3_thrd_id; +output ctl_lsq_ex3_algebraic; +output [0:2] ctl_lsq_ex3_opsize; +output ctl_lsq_ex4_ldreq_val; +output ctl_lsq_ex4_binvreq_val; +output ctl_lsq_ex4_streq_val; +output ctl_lsq_ex4_othreq_val; +output [64-`REAL_IFAR_WIDTH:57] ctl_lsq_ex4_p_addr; +output ctl_lsq_ex4_dReq_val; +output ctl_lsq_ex4_gath_load; +output ctl_lsq_ex4_send_l2; +output ctl_lsq_ex4_has_data; +output ctl_lsq_ex4_cline_chk; +output [0:4] ctl_lsq_ex4_wimge; +output ctl_lsq_ex4_byte_swap; +output ctl_lsq_ex4_is_sync; +output ctl_lsq_ex4_all_thrd_chk; +output ctl_lsq_ex4_is_store; +output ctl_lsq_ex4_is_resv; +output ctl_lsq_ex4_is_mfgpr; +output ctl_lsq_ex4_is_icswxr; +output ctl_lsq_ex4_is_icbi; +output ctl_lsq_ex4_watch_clr; +output ctl_lsq_ex4_watch_clr_all; +output ctl_lsq_ex4_mtspr_trace; +output ctl_lsq_ex4_is_inval_op; +output ctl_lsq_ex4_is_cinval; +output ctl_lsq_ex5_lock_clr; +output ctl_lsq_ex5_lock_set; +output ctl_lsq_ex5_watch_set; +output [0:`AXU_SPARE_ENC+`GPR_POOL_ENC+`THREADS_POOL_ENC-1] ctl_lsq_ex5_tgpr; +output ctl_lsq_ex5_axu_val; // XU,AXU type operation +output ctl_lsq_ex5_is_epid; +output [0:3] ctl_lsq_ex5_usr_def; +output ctl_lsq_ex5_drop_rel; // L2 only instructions +output ctl_lsq_ex5_flush_req; // Flush request from LDQ/STQ +output ctl_lsq_ex5_flush_pfetch; // Flush Prefetch in EX5 +output [0:10] ctl_lsq_ex5_cmmt_events; +output ctl_lsq_ex5_perf_val0; +output [0:3] ctl_lsq_ex5_perf_sel0; +output ctl_lsq_ex5_perf_val1; +output [0:3] ctl_lsq_ex5_perf_sel1; +output ctl_lsq_ex5_perf_val2; +output [0:3] ctl_lsq_ex5_perf_sel2; +output ctl_lsq_ex5_perf_val3; +output [0:3] ctl_lsq_ex5_perf_sel3; +output ctl_lsq_ex5_not_touch; +output [0:1] ctl_lsq_ex5_class_id; +output [0:1] ctl_lsq_ex5_dvc; +output [0:3] ctl_lsq_ex5_dacrw; +output [0:5] ctl_lsq_ex5_ttype; +output [0:1] ctl_lsq_ex5_l_fld; +output ctl_lsq_ex5_load_hit; +input [0:3] lsq_ctl_ex6_ldq_events; // LDQ Pipeline Performance Events +input [0:1] lsq_ctl_ex6_stq_events; // LDQ Pipeline Performance Events +output [0:3] ctl_lsq_ex6_ldh_dacrw; +output [0:26] ctl_lsq_stq3_icswx_data; +output [0:`THREADS-1] ctl_lsq_dbg_int_en; +output [0:`THREADS-1] ctl_lsq_ldp_idle; +output ctl_lsq_rv1_dir_rd_val; +output ctl_lsq_spr_lsucr0_ford; +output ctl_lsq_spr_lsucr0_b2b; // LSUCR0[B2B] Mode enabled +output ctl_lsq_spr_lsucr0_lge; +output [0:2] ctl_lsq_spr_lsucr0_lca; +output [0:2] ctl_lsq_spr_lsucr0_sca; +output ctl_lsq_spr_lsucr0_dfwd; +output [64-(2**`GPR_WIDTH_ENC):63] ctl_lsq_ex4_xu1_data; +output [0:`THREADS-1] ctl_lsq_pf_empty; + +//-------------------------------------------------------------- +// Interface with Commit Pipe Directories +//-------------------------------------------------------------- +output [0:3] dir_arr_wr_enable; +output [0:7] dir_arr_wr_way; +output [64-(`DC_SIZE-3):63-`CL_SIZE] dir_arr_wr_addr; +output [64-`REAL_IFAR_WIDTH:64-`REAL_IFAR_WIDTH+WAYDATASIZE-1] dir_arr_wr_data; +input [0:(8*WAYDATASIZE)-1] dir_arr_rd_data1; + +//-------------------------------------------------------------- +// Interface with DATA +//-------------------------------------------------------------- +output ctl_dat_ex1_data_act; +output [52:59] ctl_dat_ex2_eff_addr; +output [0:4] ctl_dat_ex3_opsize; +output ctl_dat_ex3_le_mode; +output [0:3] ctl_dat_ex3_le_ld_rotsel; +output [0:3] ctl_dat_ex3_be_ld_rotsel; +output ctl_dat_ex3_algebraic; +output [0:3] ctl_dat_ex3_le_alg_rotsel; +output [0:7] ctl_dat_ex4_way_hit; +input [0:7] dat_ctl_dcarr_perr_way; +input [(128-`STQ_DATA_SIZE):127] dat_ctl_ex5_load_data; +input [(128-`STQ_DATA_SIZE):127] dat_ctl_stq6_axu_data; + +output stq4_dcarr_wren; +output [0:7] stq4_dcarr_way_en; + +//-------------------------------------------------------------- +// Common Interface +//-------------------------------------------------------------- +output [64-(2**`GPR_WIDTH_ENC):63] ctl_spr_dvc1_dbg; +output [64-(2**`GPR_WIDTH_ENC):63] ctl_spr_dvc2_dbg; +output [0:23] ctl_perv_spr_lesr1; +output [0:23] ctl_perv_spr_lesr2; +output [0:8*`THREADS-1] ctl_spr_dbcr2_dvc1be; +output [0:8*`THREADS-1] ctl_spr_dbcr2_dvc2be; +output [0:2*`THREADS-1] ctl_spr_dbcr2_dvc1m; +output [0:2*`THREADS-1] ctl_spr_dbcr2_dvc2m; + +// LQ Pervasive +output [0:18+`THREADS-1] ctl_perv_ex6_perf_events; +output [0:6+`THREADS-1] ctl_perv_stq4_perf_events; +output [0:(`THREADS*3)+1] ctl_perv_dir_perf_events; + +// Error Reporting +output lq_pc_err_derat_parity; +output lq_pc_err_dir_ldp_parity; +output lq_pc_err_dir_stp_parity; +output lq_pc_err_dcache_parity; +output lq_pc_err_derat_multihit; +output lq_pc_err_dir_ldp_multihit; +output lq_pc_err_dir_stp_multihit; +output lq_pc_err_prefetcher_parity; + +// Pervasive + + +inout vcs; + + +inout vdd; + + +inout gnd; + +(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) + +input [0:`NCLK_WIDTH-1] nclk; +input sg_2; +input fce_2; +input func_sl_thold_2; +input func_nsl_thold_2; +input func_slp_sl_thold_2; +input func_slp_nsl_thold_2; +input pc_lq_init_reset; +input pc_lq_ccflush_dc; +input clkoff_dc_b; +input d_mode_dc; +input [5:9] delay_lclkr_dc; +input [5:9] mpw1_dc_b; +input mpw2_dc_b; +input g8t_clkoff_dc_b; +input g8t_d_mode_dc; +input [0:4] g8t_delay_lclkr_dc; +input [0:4] g8t_mpw1_dc_b; +input g8t_mpw2_dc_b; +input cfg_slp_sl_thold_2; +input cfg_sl_thold_2; +input regf_slp_sl_thold_2; +input abst_sl_thold_2; +input abst_slp_sl_thold_2; +input time_sl_thold_2; +input ary_nsl_thold_2; +input ary_slp_nsl_thold_2; +input repr_sl_thold_2; +input bolt_sl_thold_2; +input bo_enable_2; +input an_ac_scan_dis_dc_b; +input an_ac_scan_diag_dc; +input an_ac_lbist_en_dc; +input an_ac_atpg_en_dc; +input an_ac_grffence_en_dc; +input an_ac_lbist_ary_wrt_thru_dc; +input pc_lq_abist_ena_dc; +input pc_lq_abist_raw_dc_b; +input pc_lq_bo_unload; +input pc_lq_bo_repair; +input pc_lq_bo_reset; +input pc_lq_bo_shdata; +input [4:7] pc_lq_bo_select; +output [4:7] lq_pc_bo_fail; +output [4:7] lq_pc_bo_diagout; + +// RAM Control +input [0:`THREADS-1] pc_lq_ram_active; +output lq_pc_ram_data_val; +output [64-(2**`GPR_WIDTH_ENC):63] lq_pc_ram_data; + +// G8T ABIST Control +input pc_lq_abist_wl64_comp_ena; +input pc_lq_abist_g8t_wenb; +input pc_lq_abist_g8t1p_renb_0; +input [0:3] pc_lq_abist_g8t_dcomp; +input pc_lq_abist_g8t_bw_1; +input pc_lq_abist_g8t_bw_0; +input [0:3] pc_lq_abist_di_0; +input [4:9] pc_lq_abist_waddr_0; +input [3:8] pc_lq_abist_raddr_0; + +// D-ERAT CAM ABIST Control +input cam_clkoff_dc_b; +input cam_d_mode_dc; +input cam_act_dis_dc; +input [0:4] cam_delay_lclkr_dc; +input [0:4] cam_mpw1_dc_b; +input cam_mpw2_dc_b; + +// SCAN Ports + +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + +input abst_scan_in; + +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + +input time_scan_in; + +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + +input repr_scan_in; + +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + +input [0:10] func_scan_in; + +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + +input [0:6] regf_scan_in; + +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + +input ccfg_scan_in; + +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + +output abst_scan_out; + +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + +output time_scan_out; + +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + +output repr_scan_out; + +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + +output [0:10] func_scan_out; + +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + +output [0:6] regf_scan_out; + +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + +output ccfg_scan_out; + +//-------------------------- +// components +//-------------------------- + +//-------------------------- +// constants +//-------------------------- +parameter UPRTAGBIT = 64 - `REAL_IFAR_WIDTH; +parameter LWRTAGBIT = 63 - (`DC_SIZE - 3); +parameter TAGSIZE = LWRTAGBIT - UPRTAGBIT + 1; +parameter PAREXTCALC = 8 - (TAGSIZE % 8); +parameter PARBITS = (TAGSIZE + PAREXTCALC)/8; +parameter AXU_TARGET_ENC = `AXU_SPARE_ENC + `GPR_POOL_ENC + `THREADS_POOL_ENC; + +//-------------------------- +// signals +//-------------------------- +wire dcc_dec_hold_all; +wire dec_byp_ex1_s1_vld; +wire dec_byp_ex1_s2_vld; +wire dec_byp_ex1_use_imm; +wire [64-(2**`GPR_WIDTH_ENC):63] dec_byp_ex1_imm; +wire dec_byp_ex1_rs1_zero; +wire byp_ex2_req_aborted; +wire dcc_dec_arr_rd_rv1_val; +wire [0:5] dcc_dec_arr_rd_congr_cl; +wire dcc_dec_stq3_mftgpr_val; +wire dcc_dec_stq5_mftgpr_val; +wire [0:51] derat_dec_rv1_snoop_addr; +wire derat_dec_hole_all; +wire dcc_byp_ram_sel; +wire dcc_dec_ex5_wren; +wire dec_dcc_ex1_cmd_act; +wire dec_derat_ex1_derat_act; +wire dec_dir_ex2_dir_rd_act; +wire [0:`THREADS-1] dec_derat_ex1_pfetch_val; +wire [0:`THREADS-1] dec_spr_ex1_valid; +wire dec_dcc_ex1_ucode_val; +wire [0:`UCODE_ENTRIES_ENC-1] dec_dcc_ex1_ucode_cnt; +wire dec_dcc_ex1_ucode_op; +wire dec_dcc_ex1_sfx_val; +wire dec_dcc_ex1_axu_op_val; +wire dec_dcc_ex1_axu_falign; +wire dec_dcc_ex1_axu_fexcpt; +wire [0:2] dec_dcc_ex1_axu_instr_type; +wire dec_dcc_ex1_cache_acc; +wire [0:`THREADS-1] dec_dcc_ex1_thrd_id; +wire [0:31] dec_dcc_ex1_instr; +wire dec_dcc_ex1_optype1; +wire dec_dcc_ex1_optype2; +wire dec_dcc_ex1_optype4; +wire dec_dcc_ex1_optype8; +wire dec_dcc_ex1_optype16; +wire dec_dcc_ex1_optype32; +wire [0:AXU_TARGET_ENC-1] dec_dcc_ex1_target_gpr; +wire dec_dcc_ex1_mtspr_trace; +wire dec_dcc_ex1_load_instr; +wire dec_dcc_ex1_store_instr; +wire dec_dcc_ex1_dcbf_instr; +wire dec_dcc_ex1_sync_instr; +wire [0:1] dec_dcc_ex1_l_fld; +wire dec_dcc_ex1_dcbi_instr; +wire dec_dcc_ex1_dcbz_instr; +wire dec_dcc_ex1_dcbt_instr; +wire dec_dcc_ex1_pfetch_val; +wire dec_dcc_ex1_dcbtst_instr; +wire [0:4] dec_dcc_ex1_th_fld; +wire dec_dcc_ex1_dcbtls_instr; +wire dec_dcc_ex1_dcbtstls_instr; +wire dec_dcc_ex1_dcblc_instr; +wire dec_dcc_ex1_dcbst_instr; +wire dec_dcc_ex1_icbi_instr; +wire dec_dcc_ex1_icblc_instr; +wire dec_dcc_ex1_icbt_instr; +wire dec_dcc_ex1_icbtls_instr; +wire dec_dcc_ex1_icswx_instr; +wire dec_dcc_ex1_icswxdot_instr; +wire dec_dcc_ex1_icswx_epid; +wire dec_dcc_ex1_tlbsync_instr; +wire dec_dcc_ex1_ldawx_instr; +wire dec_dcc_ex1_wclr_instr; +wire dec_dcc_ex1_wchk_instr; +wire dec_dcc_ex1_resv_instr; +wire dec_dcc_ex1_mutex_hint; +wire dec_dcc_ex1_mbar_instr; +wire dec_dcc_ex1_makeitso_instr; +wire dec_dcc_ex1_is_msgsnd; +wire dec_derat_ex1_is_load; +wire dec_derat_ex1_is_store; +wire [0:`THREADS-1] dec_derat_ex0_val; +wire dec_derat_ex0_is_extload; +wire dec_derat_ex0_is_extstore; +wire dec_derat_ex1_ra_eq_ea; +wire dec_derat_ex1_is_touch; +wire dec_dcc_ex1_dci_instr; +wire dec_dcc_ex1_ici_instr; +wire dec_dcc_ex1_mword_instr; +wire dec_dcc_ex1_algebraic; +wire dec_derat_ex1_byte_rev; +wire dec_dcc_ex1_strg_index; +wire dec_dcc_ex1_src_gpr; +wire dec_dcc_ex1_src_axu; +wire dec_dcc_ex1_src_dp; +wire dec_dcc_ex1_targ_gpr; +wire dec_dcc_ex1_targ_axu; +wire dec_dcc_ex1_targ_dp; +wire dec_dcc_ex1_upd_form; +wire [0:`ITAG_SIZE_ENC-1] dec_dcc_ex1_itag; +wire [0:4] dec_dcc_ex2_rotsel_ovrd; +wire dec_dcc_ex3_mtdp_val; +wire dec_dcc_ex3_mfdp_val; +wire [0:4] dec_dcc_ex3_ipc_ba; +wire [0:1] dec_dcc_ex3_ipc_sz; +wire dec_dcc_ex5_req_abort_rpt; +wire dec_dcc_ex5_axu_abort_rpt; +wire dec_ex2_is_any_load_dac; +wire dec_ex2_is_any_store_dac; +wire [0:`CR_POOL_ENC-1] dec_dcc_ex1_cr_fld; +wire dec_dcc_ex1_expt_det; +wire dec_dcc_ex1_priv_prog; +wire dec_dcc_ex1_hypv_prog; +wire dec_dcc_ex1_illeg_prog; +wire dec_dcc_ex1_dlock_excp; +wire dec_dcc_ex1_ilock_excp; +wire dec_dcc_ex1_ehpriv_excp; +wire [64-(2**`GPR_WIDTH_ENC):63] dir_dcc_ex2_eff_addr; +wire [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] dir_dcc_ex4_way_tag_a; +wire [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] dir_dcc_ex4_way_tag_b; +wire [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] dir_dcc_ex4_way_tag_c; +wire [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] dir_dcc_ex4_way_tag_d; +wire [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] dir_dcc_ex4_way_tag_e; +wire [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] dir_dcc_ex4_way_tag_f; +wire [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] dir_dcc_ex4_way_tag_g; +wire [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] dir_dcc_ex4_way_tag_h; +wire [0:PARBITS-1] dir_dcc_ex4_way_par_a; +wire [0:PARBITS-1] dir_dcc_ex4_way_par_b; +wire [0:PARBITS-1] dir_dcc_ex4_way_par_c; +wire [0:PARBITS-1] dir_dcc_ex4_way_par_d; +wire [0:PARBITS-1] dir_dcc_ex4_way_par_e; +wire [0:PARBITS-1] dir_dcc_ex4_way_par_f; +wire [0:PARBITS-1] dir_dcc_ex4_way_par_g; +wire [0:PARBITS-1] dir_dcc_ex4_way_par_h; +wire [0:1+`THREADS] dir_dcc_ex5_way_a_dir; +wire [0:1+`THREADS] dir_dcc_ex5_way_b_dir; +wire [0:1+`THREADS] dir_dcc_ex5_way_c_dir; +wire [0:1+`THREADS] dir_dcc_ex5_way_d_dir; +wire [0:1+`THREADS] dir_dcc_ex5_way_e_dir; +wire [0:1+`THREADS] dir_dcc_ex5_way_f_dir; +wire [0:1+`THREADS] dir_dcc_ex5_way_g_dir; +wire [0:1+`THREADS] dir_dcc_ex5_way_h_dir; +wire [0:6] dir_dcc_ex5_dir_lru; +wire derat_dcc_ex3_wimge_e; +wire derat_dcc_ex3_itagHit; +wire [0:4] derat_dcc_ex4_wimge; +wire [0:3] derat_dcc_ex4_usr_bits; +wire [0:1] derat_dcc_ex4_wlc; +wire [22:51] derat_dcc_ex4_p_addr; +wire derat_dcc_ex4_noop_touch; +wire derat_dcc_ex4_miss; +wire derat_dcc_ex4_tlb_err; +wire derat_dcc_ex4_dsi; +wire derat_dcc_ex4_vf; +wire derat_dcc_ex4_multihit_err_det; +wire derat_dcc_ex4_multihit_err_flush; +wire derat_dcc_ex4_par_err_det; +wire derat_dcc_ex4_par_err_flush; +wire derat_dcc_ex4_tlb_inelig; +wire derat_dcc_ex4_pt_fault; +wire derat_dcc_ex4_lrat_miss; +wire derat_dcc_ex4_tlb_multihit; +wire derat_dcc_ex4_tlb_par_err; +wire derat_dcc_ex4_lru_par_err; +wire derat_dcc_ex4_restart; +wire derat_dcc_ex4_setHold; +wire [0:`THREADS-1] derat_dcc_clr_hold; +wire [0:`THREADS-1] derat_dcc_emq_idle; +wire derat_fir_par_err; +wire derat_fir_multihit; +wire dir_dcc_ex4_hit; +wire dir_dcc_ex4_miss; +wire dir_dcc_ex4_set_rel_coll; +wire dir_dcc_ex4_byp_restart; +wire dir_dcc_ex5_dir_perr_det; +wire dir_dcc_ex5_dc_perr_det; +wire dir_dcc_ex5_dir_perr_flush; +wire dir_dcc_ex5_dc_perr_flush; +wire dir_dcc_ex5_multihit_det; +wire dir_dcc_ex5_multihit_flush; +wire dir_dcc_stq4_dir_perr_det; +wire dir_dcc_stq4_multihit_det; +wire dir_dcc_ex5_stp_flush; +wire fgen_ex1_stg_flush; +wire fgen_ex2_stg_flush; +wire fgen_ex3_stg_flush; +wire fgen_ex4_cp_flush; +wire fgen_ex4_stg_flush; +wire fgen_ex5_stg_flush; +wire dir_dcc_rel3_dcarr_upd; +wire dir_dec_rel3_dir_wr_val; +wire [64-(`DC_SIZE-3):63-`CL_SIZE] dir_dec_rel3_dir_wr_addr; +wire dir_dcc_stq3_hit; +wire dir_dcc_ex5_cr_rslt; +wire dcc_dir_ex2_frc_align2; +wire dcc_dir_ex2_frc_align4; +wire dcc_dir_ex2_frc_align8; +wire dcc_dir_ex2_frc_align16; +wire dcc_dir_ex2_64bit_agen; +wire [0:`THREADS-1] dcc_dir_ex2_thrd_id; +wire dcc_dir_ex3_lru_upd; +wire dcc_dir_ex3_cache_acc; +wire dcc_derat_ex3_strg_noop; +wire dcc_derat_ex5_blk_tlb_req; +wire [0:`THREADS-1] dcc_derat_ex6_cplt; +wire [0:`ITAG_SIZE_ENC-1] dcc_derat_ex6_cplt_itag; +wire dcc_dir_ex3_pfetch_val; +wire dcc_dir_ex3_lock_set; +wire dcc_dir_ex3_th_c; +wire dcc_dir_ex3_watch_set; +wire dcc_dir_ex3_larx_val; +wire dcc_dir_ex3_watch_chk; +wire dcc_dir_ex3_ddir_acc; +wire dcc_dir_ex4_load_val; +wire dcc_spr_ex3_data_val; +wire [64-(2**`GPR_WIDTH_ENC):63] dcc_spr_ex3_eff_addr; +wire dcc_byp_rel2_stg_act; +wire dcc_byp_rel3_stg_act; +wire dcc_byp_ram_act; +wire dcc_byp_ex4_moveOp_val; +wire dcc_byp_stq6_moveOp_val; +wire [64-(2**`GPR_WIDTH_ENC):63] dcc_byp_ex4_move_data; +wire dcc_byp_ex5_lq_req_abort; +wire [0:((2**`GPR_WIDTH_ENC)/8)-1] dcc_byp_ex5_byte_mask; +wire [0:`THREADS-1] dcc_byp_ex6_thrd_id; +wire dcc_byp_ex6_dvc1_en; +wire dcc_byp_ex6_dvc2_en; +wire [0:3] dcc_byp_ex6_dacr_cmpr; +wire [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] dcc_dir_ex4_p_addr; +wire dcc_dir_stq6_store_val; +wire [0:31] dcc_dir_spr_xucr2_rmt; +wire dcc_dir_ex2_binv_val; +wire derat_rv1_snoop_val; +wire [0:`THREADS-1] spr_derat_epsc_wr; +wire [0:`THREADS-1] spr_derat_eplc_wr; +wire [0:`THREADS-1] spr_derat_eplc_epr; +wire [0:`THREADS-1] spr_derat_eplc_eas; +wire [0:`THREADS-1] spr_derat_eplc_egs; +wire [0:(8*`THREADS)-1] spr_derat_eplc_elpid; +wire [0:(14*`THREADS)-1] spr_derat_eplc_epid; +wire [0:`THREADS-1] spr_derat_epsc_epr; +wire [0:`THREADS-1] spr_derat_epsc_eas; +wire [0:`THREADS-1] spr_derat_epsc_egs; +wire [0:(8*`THREADS)-1] spr_derat_epsc_elpid; +wire [0:(14*`THREADS)-1] spr_derat_epsc_epid; +wire [64-(`DC_SIZE-3):63-`CL_SIZE] dir_arr_rd_addr0_01; +wire [64-(`DC_SIZE-3):63-`CL_SIZE] dir_arr_rd_addr0_23; +wire [64-(`DC_SIZE-3):63-`CL_SIZE] dir_arr_rd_addr0_45; +wire [64-(`DC_SIZE-3):63-`CL_SIZE] dir_arr_rd_addr0_67; +wire [0:(8*WAYDATASIZE)-1] dir_arr_rd_data0; +wire [0:3] dir_arr_wr_enable_int; +wire [0:7] dir_arr_wr_way_int; +wire [64-(`DC_SIZE-3):63-`CL_SIZE] dir_arr_wr_addr_int; +wire [64-`REAL_IFAR_WIDTH:64-`REAL_IFAR_WIDTH+WAYDATASIZE-1] dir_arr_wr_data_int; +wire [0:51] dir_derat_ex2_eff_addr; +wire dec_byp_ex0_stg_act; +wire dec_byp_ex1_stg_act; +wire dec_byp_ex5_stg_act; +wire dec_byp_ex6_stg_act; +wire dec_byp_ex7_stg_act; +wire [64-(2**`GPR_WIDTH_ENC):59] dcc_pf_ex5_eff_addr; +wire dcc_pf_ex5_req_val_4pf; +wire dcc_pf_ex5_act; +wire dcc_pf_ex5_loadmiss; +wire [0:`ITAG_SIZE_ENC-1] dcc_pf_ex5_itag; +wire [64-(2**`GPR_WIDTH_ENC):63-`CL_SIZE] pf_dec_req_addr; +wire [0:`THREADS-1] pf_dec_req_thrd; +wire [0:`THREADS-1] dcc_pf_ex5_thrd_id; +wire pf_dec_req_val; +wire dec_pf_ack; +wire ctl_pf_clear_queue; +wire [64-(2**`GPR_WIDTH_ENC):63] byp_dir_ex2_rs1; +wire [64-(2**`GPR_WIDTH_ENC):63] byp_dir_ex2_rs2; +wire [0:87] derat_xu_debug_group0; +wire [0:87] derat_xu_debug_group1; +wire [0:87] derat_xu_debug_group2; +wire [0:87] derat_xu_debug_group3; +wire spr_dcc_ex4_dvc1_en; +wire spr_dcc_ex4_dvc2_en; +wire spr_dcc_ex4_dacrw1_cmpr; +wire spr_dcc_ex4_dacrw2_cmpr; +wire spr_dcc_ex4_dacrw3_cmpr; +wire spr_dcc_ex4_dacrw4_cmpr; +wire spr_dcc_spr_xudbg0_exec; +wire [0:`THREADS-1] spr_dcc_spr_xudbg0_tid; +wire dcc_spr_spr_xudbg0_done; +wire [0:2] spr_dcc_spr_xudbg0_way; +wire [0:5] spr_dcc_spr_xudbg0_row; +wire dcc_spr_spr_xudbg1_valid; +wire [0:3] dcc_spr_spr_xudbg1_watch; +wire [0:3] dcc_spr_spr_xudbg1_parity; +wire [0:6] dcc_spr_spr_xudbg1_lru; +wire dcc_spr_spr_xudbg1_lock; +wire [33:63] dcc_spr_spr_xudbg2_tag; +wire [32:63] spr_dcc_spr_xucr2_rmt; +wire spr_dcc_spr_lsucr0_clchk; +wire [0:(32*`THREADS)-1] spr_dcc_spr_acop_ct; +wire [0:(32*`THREADS)-1] spr_dcc_spr_hacop_ct; +wire [0:`THREADS-1] spr_pf_spr_dscr_lsd; +wire [0:`THREADS-1] spr_pf_spr_dscr_snse; +wire [0:`THREADS-1] spr_pf_spr_dscr_sse; +wire [0:3*`THREADS-1] spr_pf_spr_dscr_dpfd; +wire [0:8*`THREADS-1] spr_dbcr2_dvc1be; +wire [0:8*`THREADS-1] spr_dbcr2_dvc2be; +wire [0:2*`THREADS-1] spr_dbcr2_dvc1m; +wire [0:2*`THREADS-1] spr_dbcr2_dvc2m; +wire [64-(2**`GPR_WIDTH_ENC):63] spr_dvc1_dbg; +wire [64-(2**`GPR_WIDTH_ENC):63] spr_dvc2_dbg; +wire [0:31] spr_pf_spr_pesr; +wire dcc_dir_ex2_stg_act; +wire dcc_dir_ex3_stg_act; +wire dcc_dir_ex4_stg_act; +wire dcc_dir_ex5_stg_act; +wire dcc_dir_stq1_stg_act; +wire dcc_dir_stq2_stg_act; +wire dcc_dir_stq3_stg_act; +wire dcc_dir_stq4_stg_act; +wire dcc_dir_stq5_stg_act; +wire dcc_dir_binv2_ex2_stg_act; +wire dcc_dir_binv3_ex3_stg_act; +wire dcc_dir_binv4_ex4_stg_act; +wire dcc_dir_binv5_ex5_stg_act; +wire dcc_dir_binv6_ex6_stg_act; +wire [0:23] spr_lesr1; +wire [0:5] spr_lesr1_muxseleb0; +wire [0:5] spr_lesr1_muxseleb1; +wire [0:5] spr_lesr1_muxseleb2; +wire [0:5] spr_lesr1_muxseleb3; +wire [0:23] spr_lesr2; +wire [0:5] spr_lesr2_muxseleb4; +wire [0:5] spr_lesr2_muxseleb5; +wire [0:5] spr_lesr2_muxseleb6; +wire [0:5] spr_lesr2_muxseleb7; +wire [0:47] spr_dcc_spr_lesr; +wire func_nsl_thold_1; +wire func_sl_thold_1; +wire func_slp_sl_thold_1; +wire func_slp_nsl_thold_1; +wire regf_slp_sl_thold_1; +wire sg_1; +wire fce_1; +wire func_nsl_thold_0; +wire func_sl_thold_0; +wire func_slp_sl_thold_0; +wire func_slp_nsl_thold_0; +wire regf_slp_sl_thold_0; +wire sg_0; +wire fce_0; +wire func_nsl_thold_0_b; +wire func_sl_thold_0_b; +wire func_slp_sl_thold_0_b; +wire func_slp_nsl_thold_0_b; +wire func_nsl_force; +wire func_sl_force; +wire func_slp_sl_force; +wire func_slp_nsl_force; +wire tiup; +wire tidn; +wire abst_scan_in_q; +wire [0:3] abst_scan_out_int; +wire [0:2] abst_scan_out_q; +wire [0:2] time_scan_in_q; +wire [0:2] time_scan_out_int; +wire time_scan_out_q; +wire [0:1] repr_scan_in_q; +wire [0:1] repr_scan_out_int; +wire repr_scan_out_q; +wire [0:10] func_scan_in_q; +wire [0:10] func_scan_out_int; +wire [0:10] func_scan_out_q; +wire [3:7] dir_func_scan_in; +wire arr_func_scan_out; +wire [0:6] regf_scan_in_q; +wire [0:6] regf_scan_out_int; +wire [0:6] regf_scan_out_q; +wire spr_derat_cfg_scan; +wire spr_pf_func_scan; +wire ccfg_scan_out_int; +wire [0:24] abist_siv; +wire [0:24] abist_sov; +wire abst_sl_thold_1; +wire abst_slp_sl_thold_1; +wire time_sl_thold_1; +wire ary_nsl_thold_1; +wire ary_slp_nsl_thold_1; +wire repr_sl_thold_1; +wire bolt_sl_thold_1; +wire cfg_sl_thold_1; +wire abst_sl_thold_0; +wire abst_slp_sl_thold_0; +wire time_sl_thold_0; +wire ary_nsl_thold_0; +wire ary_slp_nsl_thold_0; +wire repr_sl_thold_0; +wire bolt_sl_thold_0; +wire cfg_sl_thold_0; +wire abst_sl_thold_0_b; +wire abst_sl_force; +wire cfg_sl_thold_0_b; +wire cfg_sl_force; +wire pc_lq_abist_wl64_comp_ena_q; +wire [3:8] pc_lq_abist_raddr_0_q; +wire pc_lq_abist_g8t_wenb_q; +wire pc_lq_abist_g8t1p_renb_0_q; +wire [0:3] pc_lq_abist_g8t_dcomp_q; +wire pc_lq_abist_g8t_bw_1_q; +wire pc_lq_abist_g8t_bw_0_q; +wire [0:3] pc_lq_abist_di_0_q; +wire [4:9] pc_lq_abist_waddr_0_q; +wire slat_force; +wire abst_slat_thold_b; +wire abst_slat_d2clk; +wire [0:`NCLK_WIDTH-1] abst_slat_lclk; +wire time_slat_thold_b; +wire time_slat_d2clk; +wire [0:`NCLK_WIDTH-1] time_slat_lclk; +wire repr_slat_thold_b; +wire repr_slat_d2clk; +wire [0:`NCLK_WIDTH-1] repr_slat_lclk; +wire func_slat_thold_b; +wire func_slat_d2clk; +wire [0:`NCLK_WIDTH-1] func_slat_lclk; +wire regf_slat_thold_b; +wire regf_slat_d2clk; +wire [0:`NCLK_WIDTH-1] regf_slat_lclk; +wire [0:3] abst_scan_q; +wire [0:3] abst_scan_q_b; +wire [0:3] time_scan_q; +wire [0:3] time_scan_q_b; +wire [0:2] repr_scan_q; +wire [0:2] repr_scan_q_b; +wire [0:21] func_scan_q; +wire [0:21] func_scan_q_b; +wire [0:13] regf_scan_q; +wire [0:13] regf_scan_q_b; +wire byp_dec_ex1_s1_abort; +wire byp_dec_ex1_s2_abort; + +(* analysis_not_referenced="true" *) +wire unused; + +assign tiup = 1'b1; +assign tidn = 1'b0; +assign unused = |abst_scan_q | |abst_scan_q_b | |time_scan_q | |time_scan_q_b | + |repr_scan_q | |repr_scan_q_b | |func_scan_q | |func_scan_q_b | + |regf_scan_q | |regf_scan_q_b; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// DECODE +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +lq_dec dec( + //-------------------------------------------------------------- + // Clocks & Power + //-------------------------------------------------------------- + .nclk(nclk), + .vdd(vdd), + .gnd(gnd), + + //-------------------------------------------------------------- + // Pervasive + //-------------------------------------------------------------- + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc[5]), + .mpw1_dc_b(mpw1_dc_b[5]), + .mpw2_dc_b(mpw2_dc_b), + .func_sl_force(func_sl_force), + .func_sl_thold_0_b(func_sl_thold_0_b), + .func_slp_sl_force(func_slp_sl_force), + .func_slp_sl_thold_0_b(func_slp_sl_thold_0_b), + .sg_0(sg_0), + .scan_in(func_scan_in_q[0]), + .scan_out(func_scan_out_int[0]), + + //-------------------------------------------------------------- + // SPR Interface + //-------------------------------------------------------------- + .xu_lq_spr_msr_gs(xu_lq_spr_msr_gs), + .xu_lq_spr_msr_pr(xu_lq_spr_msr_pr), + .xu_lq_spr_msr_ucle(xu_lq_spr_msr_ucle), + .xu_lq_spr_msrp_uclep(xu_lq_spr_msrp_uclep), + .xu_lq_spr_ccr2_en_pc(xu_lq_spr_ccr2_en_pc), + .xu_lq_spr_ccr2_en_ditc(xu_lq_spr_ccr2_en_ditc), + .xu_lq_spr_ccr2_en_icswx(xu_lq_spr_ccr2_en_icswx), + + //-------------------------------------------------------------- + // CP Interface + //-------------------------------------------------------------- + .iu_lq_cp_flush(iu_lq_cp_flush), + + //----------------------------------------------------- + // Interface with RV + //----------------------------------------------------- + .rv_lq_vld(rv_lq_vld), + .rv_lq_ex0_itag(rv_lq_ex0_itag), + .rv_lq_ex0_instr(rv_lq_ex0_instr), + .rv_lq_ex0_ucode(rv_lq_ex0_ucode), + .rv_lq_ex0_ucode_cnt(rv_lq_ex0_ucode_cnt), + .rv_lq_ex0_t1_v(rv_lq_ex0_t1_v), + .rv_lq_ex0_t1_p(rv_lq_ex0_t1_p), + .rv_lq_ex0_t3_p(rv_lq_ex0_t3_p), + .rv_lq_ex0_s1_v(rv_lq_ex0_s1_v), + .rv_lq_ex0_s2_v(rv_lq_ex0_s2_v), + + .dcc_dec_hold_all(dcc_dec_hold_all), + + .xu_lq_hold_req(xu_lq_hold_req), + .mm_lq_hold_req(mm_lq_hold_req), + .mm_lq_hold_done(mm_lq_hold_done), + + .lq_rv_itag0(lq_rv_itag0), + .lq_rv_itag0_vld(lq_rv_itag0_vld), + .lq_rv_itag0_abort(lq_rv_itag0_abort), + .lq_rv_hold_all(lq_rv_hold_all), + + //-------------------------------------------------------------- + // Interface with Regfiles + //-------------------------------------------------------------- + .lq_rv_gpr_ex6_we(lq_rv_gpr_ex6_we), + .lq_xu_gpr_ex5_we(lq_xu_gpr_ex5_we), + + //------------------------------------------------------------------- + // Interface with XU + //------------------------------------------------------------------- + .lq_xu_ex5_act(lq_xu_ex5_act), + + //-------------------------------------------------------------- + // Interface with BYP + //-------------------------------------------------------------- + .dec_byp_ex1_s1_vld(dec_byp_ex1_s1_vld), + .dec_byp_ex1_s2_vld(dec_byp_ex1_s2_vld), + .dec_byp_ex1_use_imm(dec_byp_ex1_use_imm), + .dec_byp_ex1_imm(dec_byp_ex1_imm), + .dec_byp_ex1_rs1_zero(dec_byp_ex1_rs1_zero), + .dec_byp_ex0_stg_act(dec_byp_ex0_stg_act), + .dec_byp_ex1_stg_act(dec_byp_ex1_stg_act), + .dec_byp_ex5_stg_act(dec_byp_ex5_stg_act), + .dec_byp_ex6_stg_act(dec_byp_ex6_stg_act), + .dec_byp_ex7_stg_act(dec_byp_ex7_stg_act), + .byp_dec_ex2_req_aborted(byp_ex2_req_aborted), + .byp_dec_ex1_s1_abort(byp_dec_ex1_s1_abort), + .byp_dec_ex1_s2_abort(byp_dec_ex1_s2_abort), + + //------------------------------------------------------------------- + // Interface with PreFetch + //------------------------------------------------------------------- + .pf_dec_req_addr(pf_dec_req_addr), + .pf_dec_req_thrd(pf_dec_req_thrd), + .pf_dec_req_val(pf_dec_req_val), + .dec_pf_ack(dec_pf_ack), + + .lsq_ctl_sync_in_stq(lsq_ctl_sync_in_stq), + + //-------------------------------------------------------------- + // Reload Itag Complete + //-------------------------------------------------------------- + .lsq_ctl_stq_release_itag_vld(lsq_ctl_stq_release_itag_vld), + .lsq_ctl_stq_release_itag(lsq_ctl_stq_release_itag), + .lsq_ctl_stq_release_tid(lsq_ctl_stq_release_tid), + + //-------------------------------------------------------------- + // LSU Back-Invalidate + //-------------------------------------------------------------- + // Back-Invalidate Interface + .lsq_ctl_rv0_back_inv(lsq_ctl_rv0_back_inv), + .lsq_ctl_rv1_back_inv_addr(lsq_ctl_rv1_back_inv_addr), + + //-------------------------------------------------------------- + // LSU L1 Directory Read Instruction + //-------------------------------------------------------------- + // Directory Read interface + .dcc_dec_arr_rd_rv1_val(dcc_dec_arr_rd_rv1_val), + .dcc_dec_arr_rd_congr_cl(dcc_dec_arr_rd_congr_cl), + + //-------------------------------------------------------------- + // LSU L1 Directory Reload Write + //-------------------------------------------------------------- + .dir_dec_rel3_dir_wr_val(dir_dec_rel3_dir_wr_val), + .dir_dec_rel3_dir_wr_addr(dir_dec_rel3_dir_wr_addr), + + //-------------------------------------------------------------- + // MFTGPR Instruction + //-------------------------------------------------------------- + .dcc_dec_stq3_mftgpr_val(dcc_dec_stq3_mftgpr_val), + .dcc_dec_stq5_mftgpr_val(dcc_dec_stq5_mftgpr_val), + + //-------------------------------------------------------------- + // DERAT Snoop-Invalidate + //-------------------------------------------------------------- + // Back-Invalidate Interface + .derat_rv1_snoop_val(derat_rv1_snoop_val), + .derat_dec_rv1_snoop_addr(derat_dec_rv1_snoop_addr), + .derat_dec_hole_all(derat_dec_hole_all), + + //-------------------------------------------------------------- + // LSU Control + //-------------------------------------------------------------- + .dec_dcc_ex1_cmd_act(dec_dcc_ex1_cmd_act), + .ctl_dat_ex1_data_act(ctl_dat_ex1_data_act), + .dec_derat_ex1_derat_act(dec_derat_ex1_derat_act), + .dec_dir_ex2_dir_rd_act(dec_dir_ex2_dir_rd_act), + .dec_derat_ex1_pfetch_val(dec_derat_ex1_pfetch_val), + .dec_spr_ex1_valid(dec_spr_ex1_valid), + .dec_dcc_ex1_expt_det(dec_dcc_ex1_expt_det), + .dec_dcc_ex1_priv_prog(dec_dcc_ex1_priv_prog), + .dec_dcc_ex1_hypv_prog(dec_dcc_ex1_hypv_prog), + .dec_dcc_ex1_illeg_prog(dec_dcc_ex1_illeg_prog), + .dec_dcc_ex1_dlock_excp(dec_dcc_ex1_dlock_excp), + .dec_dcc_ex1_ilock_excp(dec_dcc_ex1_ilock_excp), + .dec_dcc_ex1_ehpriv_excp(dec_dcc_ex1_ehpriv_excp), + .dec_dcc_ex1_ucode_val(dec_dcc_ex1_ucode_val), + .dec_dcc_ex1_ucode_cnt(dec_dcc_ex1_ucode_cnt), + .dec_dcc_ex1_ucode_op(dec_dcc_ex1_ucode_op), + .dec_dcc_ex1_sfx_val(dec_dcc_ex1_sfx_val), + .dec_dcc_ex1_cache_acc(dec_dcc_ex1_cache_acc), + .dec_dcc_ex1_thrd_id(dec_dcc_ex1_thrd_id), + .dec_dcc_ex1_instr(dec_dcc_ex1_instr), + .dec_dcc_ex1_optype1(dec_dcc_ex1_optype1), + .dec_dcc_ex1_optype2(dec_dcc_ex1_optype2), + .dec_dcc_ex1_optype4(dec_dcc_ex1_optype4), + .dec_dcc_ex1_optype8(dec_dcc_ex1_optype8), + .dec_dcc_ex1_optype16(dec_dcc_ex1_optype16), + .dec_dcc_ex1_optype32(dec_dcc_ex1_optype32), + .dec_dcc_ex1_target_gpr(dec_dcc_ex1_target_gpr), + .dec_dcc_ex1_load_instr(dec_dcc_ex1_load_instr), + .dec_dcc_ex1_store_instr(dec_dcc_ex1_store_instr), + .dec_dcc_ex1_dcbf_instr(dec_dcc_ex1_dcbf_instr), + .dec_dcc_ex1_sync_instr(dec_dcc_ex1_sync_instr), + .dec_dcc_ex1_mbar_instr(dec_dcc_ex1_mbar_instr), + .dec_dcc_ex1_makeitso_instr(dec_dcc_ex1_makeitso_instr), + .dec_dcc_ex1_l_fld(dec_dcc_ex1_l_fld), + .dec_dcc_ex1_dcbi_instr(dec_dcc_ex1_dcbi_instr), + .dec_dcc_ex1_dcbz_instr(dec_dcc_ex1_dcbz_instr), + .dec_dcc_ex1_dcbt_instr(dec_dcc_ex1_dcbt_instr), + .dec_dcc_ex1_pfetch_val(dec_dcc_ex1_pfetch_val), + .dec_dcc_ex1_dcbtst_instr(dec_dcc_ex1_dcbtst_instr), + .dec_dcc_ex1_th_fld(dec_dcc_ex1_th_fld), + .dec_dcc_ex1_dcbtls_instr(dec_dcc_ex1_dcbtls_instr), + .dec_dcc_ex1_dcbtstls_instr(dec_dcc_ex1_dcbtstls_instr), + .dec_dcc_ex1_dcblc_instr(dec_dcc_ex1_dcblc_instr), + .dec_dcc_ex1_dci_instr(dec_dcc_ex1_dci_instr), + .dec_dcc_ex1_dcbst_instr(dec_dcc_ex1_dcbst_instr), + .dec_dcc_ex1_icbi_instr(dec_dcc_ex1_icbi_instr), + .dec_dcc_ex1_ici_instr(dec_dcc_ex1_ici_instr), + .dec_dcc_ex1_icblc_instr(dec_dcc_ex1_icblc_instr), + .dec_dcc_ex1_icbt_instr(dec_dcc_ex1_icbt_instr), + .dec_dcc_ex1_icbtls_instr(dec_dcc_ex1_icbtls_instr), + .dec_dcc_ex1_tlbsync_instr(dec_dcc_ex1_tlbsync_instr), + .dec_dcc_ex1_resv_instr(dec_dcc_ex1_resv_instr), + .dec_dcc_ex1_cr_fld(dec_dcc_ex1_cr_fld), + .dec_dcc_ex1_mutex_hint(dec_dcc_ex1_mutex_hint), + .dec_dcc_ex1_axu_op_val(dec_dcc_ex1_axu_op_val), + .dec_dcc_ex1_axu_falign(dec_dcc_ex1_axu_falign), + .dec_dcc_ex1_axu_fexcpt(dec_dcc_ex1_axu_fexcpt), + .dec_dcc_ex1_axu_instr_type(dec_dcc_ex1_axu_instr_type), + .dec_dcc_ex1_upd_form(dec_dcc_ex1_upd_form), + .dec_dcc_ex1_algebraic(dec_dcc_ex1_algebraic), + .dec_dcc_ex1_strg_index(dec_dcc_ex1_strg_index), + .dec_dcc_ex1_src_gpr(dec_dcc_ex1_src_gpr), + .dec_dcc_ex1_src_axu(dec_dcc_ex1_src_axu), + .dec_dcc_ex1_src_dp(dec_dcc_ex1_src_dp), + .dec_dcc_ex1_targ_gpr(dec_dcc_ex1_targ_gpr), + .dec_dcc_ex1_targ_axu(dec_dcc_ex1_targ_axu), + .dec_dcc_ex1_targ_dp(dec_dcc_ex1_targ_dp), + .dec_derat_ex1_is_load(dec_derat_ex1_is_load), + .dec_derat_ex1_is_store(dec_derat_ex1_is_store), + .dec_derat_ex0_val(dec_derat_ex0_val), + .dec_derat_ex0_is_extload(dec_derat_ex0_is_extload), + .dec_derat_ex0_is_extstore(dec_derat_ex0_is_extstore), + .dec_derat_ex1_ra_eq_ea(dec_derat_ex1_ra_eq_ea), + .dec_derat_ex1_byte_rev(dec_derat_ex1_byte_rev), + .dec_derat_ex1_is_touch(dec_derat_ex1_is_touch), + .dec_dcc_ex1_is_msgsnd(dec_dcc_ex1_is_msgsnd), + .dec_dcc_ex1_mtspr_trace(dec_dcc_ex1_mtspr_trace), + .dec_dcc_ex1_mword_instr(dec_dcc_ex1_mword_instr), + .dec_dcc_ex1_icswx_instr(dec_dcc_ex1_icswx_instr), + .dec_dcc_ex1_icswxdot_instr(dec_dcc_ex1_icswxdot_instr), + .dec_dcc_ex1_icswx_epid(dec_dcc_ex1_icswx_epid), + .dec_dcc_ex1_ldawx_instr(dec_dcc_ex1_ldawx_instr), + .dec_dcc_ex1_wclr_instr(dec_dcc_ex1_wclr_instr), + .dec_dcc_ex1_wchk_instr(dec_dcc_ex1_wchk_instr), + .dec_dcc_ex1_itag(dec_dcc_ex1_itag), + .dec_dcc_ex2_rotsel_ovrd(dec_dcc_ex2_rotsel_ovrd), + .dec_dcc_ex3_mtdp_val(dec_dcc_ex3_mtdp_val), + .dec_dcc_ex3_mfdp_val(dec_dcc_ex3_mfdp_val), + .dec_dcc_ex3_ipc_ba(dec_dcc_ex3_ipc_ba), + .dec_dcc_ex3_ipc_sz(dec_dcc_ex3_ipc_sz), + .dec_dcc_ex5_req_abort_rpt(dec_dcc_ex5_req_abort_rpt), + .dec_dcc_ex5_axu_abort_rpt(dec_dcc_ex5_axu_abort_rpt), + .dec_ex2_is_any_load_dac(dec_ex2_is_any_load_dac), + .dec_ex2_is_any_store_dac(dec_ex2_is_any_store_dac), + .ctl_lsq_ex_pipe_full(ctl_lsq_ex_pipe_full), + + // FXU Load Hit Store is Valid in ex5 + .dcc_dec_ex5_wren(dcc_dec_ex5_wren) +); + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// BYPASS +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +lq_byp byp( + //------------------------------------------------------------------- + // Clocks & Power + //------------------------------------------------------------------- + .nclk(nclk), + .vdd(vdd), + .gnd(gnd), + + //------------------------------------------------------------------- + // Pervasive + //------------------------------------------------------------------- + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc[5]), + .mpw1_dc_b(mpw1_dc_b[5]), + .mpw2_dc_b(mpw2_dc_b), + .func_sl_force(func_sl_force), + .func_sl_thold_0_b(func_sl_thold_0_b), + .func_slp_sl_force(func_slp_sl_force), + .func_slp_sl_thold_0_b(func_slp_sl_thold_0_b), + .sg_0(sg_0), + .scan_in(func_scan_in_q[1]), + .scan_out(func_scan_out_int[1]), + + //------------------------------------------------------------------- + // Interface with XU + //------------------------------------------------------------------- + .xu0_lq_ex3_act(xu0_lq_ex3_act), + .xu0_lq_ex3_abort(xu0_lq_ex3_abort), + .xu0_lq_ex3_rt(xu0_lq_ex3_rt), + .xu0_lq_ex4_rt(xu0_lq_ex4_rt), + .xu0_lq_ex6_act(xu0_lq_ex6_act), + .xu0_lq_ex6_rt(xu0_lq_ex6_rt), + .lq_xu_ex5_rt(lq_xu_ex5_rt), + .xu1_lq_ex3_act(xu1_lq_ex3_act), + .xu1_lq_ex3_abort(xu1_lq_ex3_abort), + .xu1_lq_ex3_rt(xu1_lq_ex3_rt), + + //------------------------------------------------------------------- + // Interface with DEC + //------------------------------------------------------------------- + .dec_byp_ex0_stg_act(dec_byp_ex0_stg_act), + .dec_byp_ex1_stg_act(dec_byp_ex1_stg_act), + .dec_byp_ex5_stg_act(dec_byp_ex5_stg_act), + .dec_byp_ex6_stg_act(dec_byp_ex6_stg_act), + .dec_byp_ex7_stg_act(dec_byp_ex7_stg_act), + .dec_byp_ex1_s1_vld(dec_byp_ex1_s1_vld), + .dec_byp_ex1_s2_vld(dec_byp_ex1_s2_vld), + .dec_byp_ex1_use_imm(dec_byp_ex1_use_imm), + .dec_byp_ex1_imm(dec_byp_ex1_imm), + .dec_byp_ex1_rs1_zero(dec_byp_ex1_rs1_zero), + .byp_ex2_req_aborted(byp_ex2_req_aborted), + .byp_dec_ex1_s1_abort(byp_dec_ex1_s1_abort), + .byp_dec_ex1_s2_abort(byp_dec_ex1_s2_abort), + + //------------------------------------------------------------------- + // Interface with LQ Pipe + //------------------------------------------------------------------- + // Load Pipe + .ctl_lsq_ex4_xu1_data(ctl_lsq_ex4_xu1_data), + .ctl_lsq_ex6_ldh_dacrw(ctl_lsq_ex6_ldh_dacrw), + .lsq_ctl_ex5_fwd_val(lsq_ctl_ex5_fwd_val), + .lsq_ctl_ex5_fwd_data(lsq_ctl_ex5_fwd_data), + .lsq_ctl_rel2_data(lsq_ctl_rel2_data), + .dcc_byp_rel2_stg_act(dcc_byp_rel2_stg_act), + .dcc_byp_rel3_stg_act(dcc_byp_rel3_stg_act), + .dcc_byp_ram_act(dcc_byp_ram_act), + .dcc_byp_ex4_moveOp_val(dcc_byp_ex4_moveOp_val), + .dcc_byp_stq6_moveOp_val(dcc_byp_stq6_moveOp_val), + .dcc_byp_ex4_move_data(dcc_byp_ex4_move_data), + .dcc_byp_ex5_lq_req_abort(dcc_byp_ex5_lq_req_abort), + .dcc_byp_ex5_byte_mask(dcc_byp_ex5_byte_mask), + .dcc_byp_ex6_thrd_id(dcc_byp_ex6_thrd_id), + .dcc_byp_ex6_dvc1_en(dcc_byp_ex6_dvc1_en), + .dcc_byp_ex6_dvc2_en(dcc_byp_ex6_dvc2_en), + .dcc_byp_ex6_dacr_cmpr(dcc_byp_ex6_dacr_cmpr), + .dat_ctl_ex5_load_data(dat_ctl_ex5_load_data), + .dat_ctl_stq6_axu_data(dat_ctl_stq6_axu_data), + .dcc_byp_ram_sel(dcc_byp_ram_sel), + + .byp_dir_ex2_rs1(byp_dir_ex2_rs1), + .byp_dir_ex2_rs2(byp_dir_ex2_rs2), + + //------------------------------------------------------------------- + // Interface with SPR's + //------------------------------------------------------------------- + .spr_byp_spr_dvc1_dbg(spr_dvc1_dbg), + .spr_byp_spr_dvc2_dbg(spr_dvc2_dbg), + .spr_byp_spr_dbcr2_dvc1m(spr_dbcr2_dvc1m), + .spr_byp_spr_dbcr2_dvc1be(spr_dbcr2_dvc1be), + .spr_byp_spr_dbcr2_dvc2m(spr_dbcr2_dvc2m), + .spr_byp_spr_dbcr2_dvc2be(spr_dbcr2_dvc2be), + + //------------------------------------------------------------------- + // Interface with Bypass Controller + //------------------------------------------------------------------- + .rv_lq_ex0_s1_xu0_sel(rv_lq_ex0_s1_xu0_sel), + .rv_lq_ex0_s2_xu0_sel(rv_lq_ex0_s2_xu0_sel), + .rv_lq_ex0_s1_xu1_sel(rv_lq_ex0_s1_xu1_sel), + .rv_lq_ex0_s2_xu1_sel(rv_lq_ex0_s2_xu1_sel), + .rv_lq_ex0_s1_lq_sel(rv_lq_ex0_s1_lq_sel), + .rv_lq_ex0_s2_lq_sel(rv_lq_ex0_s2_lq_sel), + .rv_lq_ex0_s1_rel_sel(rv_lq_ex0_s1_rel_sel), + .rv_lq_ex0_s2_rel_sel(rv_lq_ex0_s2_rel_sel), + + //------------------------------------------------------------------- + // Interface with PERVASIVE + //------------------------------------------------------------------- + .lq_pc_ram_data(lq_pc_ram_data), + + //------------------------------------------------------------------- + // Interface with GPR + //------------------------------------------------------------------- + .rv_lq_gpr_ex1_r0d(rv_lq_gpr_ex1_r0d), + .rv_lq_gpr_ex1_r1d(rv_lq_gpr_ex1_r1d), + .lq_rv_gpr_ex6_wd(lq_rv_gpr_ex6_wd), + .lq_rv_gpr_rel_wd(lq_rv_gpr_rel_wd), + .lq_xu_gpr_rel_wd(lq_xu_gpr_rel_wd), + + //------------------------------------------------------------------- + // Interface with RV + //------------------------------------------------------------------- + .lq_rv_ex2_s1_abort(lq_rv_ex2_s1_abort), + .lq_rv_ex2_s2_abort(lq_rv_ex2_s2_abort) +); + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// DATA CACHE CONTROL +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +lq_dcc #(.PARBITS(PARBITS)) dcc( + + // IU Dispatch + .rv_lq_rv1_i0_vld(rv_lq_rv1_i0_vld), + .rv_lq_rv1_i0_ucode_preissue(rv_lq_rv1_i0_ucode_preissue), + .rv_lq_rv1_i0_2ucode(rv_lq_rv1_i0_2ucode), + .rv_lq_rv1_i0_ucode_cnt(rv_lq_rv1_i0_ucode_cnt), + .rv_lq_rv1_i1_vld(rv_lq_rv1_i1_vld), + .rv_lq_rv1_i1_ucode_preissue(rv_lq_rv1_i1_ucode_preissue), + .rv_lq_rv1_i1_2ucode(rv_lq_rv1_i1_2ucode), + .rv_lq_rv1_i1_ucode_cnt(rv_lq_rv1_i1_ucode_cnt), + + // Execution Pipe Inputs + .dec_dcc_ex0_act(dec_byp_ex0_stg_act), + .dec_dcc_ex1_cmd_act(dec_dcc_ex1_cmd_act), + .dec_dcc_ex1_ucode_val(dec_dcc_ex1_ucode_val), + .dec_dcc_ex1_ucode_cnt(dec_dcc_ex1_ucode_cnt), + .dec_dcc_ex1_ucode_op(dec_dcc_ex1_ucode_op), + .dec_dcc_ex1_sfx_val(dec_dcc_ex1_sfx_val), + .dec_dcc_ex1_axu_op_val(dec_dcc_ex1_axu_op_val), + .dec_dcc_ex1_axu_falign(dec_dcc_ex1_axu_falign), + .dec_dcc_ex1_axu_fexcpt(dec_dcc_ex1_axu_fexcpt), + .dec_dcc_ex1_axu_instr_type(dec_dcc_ex1_axu_instr_type), + .dec_dcc_ex1_cache_acc(dec_dcc_ex1_cache_acc), + .dec_dcc_ex1_thrd_id(dec_dcc_ex1_thrd_id), + .dec_dcc_ex1_instr(dec_dcc_ex1_instr), + .dec_dcc_ex1_optype1(dec_dcc_ex1_optype1), + .dec_dcc_ex1_optype2(dec_dcc_ex1_optype2), + .dec_dcc_ex1_optype4(dec_dcc_ex1_optype4), + .dec_dcc_ex1_optype8(dec_dcc_ex1_optype8), + .dec_dcc_ex1_optype16(dec_dcc_ex1_optype16), + .dec_dcc_ex1_target_gpr(dec_dcc_ex1_target_gpr), + .dec_dcc_ex1_mtspr_trace(dec_dcc_ex1_mtspr_trace), + .dec_dcc_ex1_load_instr(dec_dcc_ex1_load_instr), + .dec_dcc_ex1_store_instr(dec_dcc_ex1_store_instr), + .dec_dcc_ex1_dcbf_instr(dec_dcc_ex1_dcbf_instr), + .dec_dcc_ex1_sync_instr(dec_dcc_ex1_sync_instr), + .dec_dcc_ex1_l_fld(dec_dcc_ex1_l_fld), + .dec_dcc_ex1_dcbi_instr(dec_dcc_ex1_dcbi_instr), + .dec_dcc_ex1_dcbz_instr(dec_dcc_ex1_dcbz_instr), + .dec_dcc_ex1_dcbt_instr(dec_dcc_ex1_dcbt_instr), + .dec_dcc_ex1_pfetch_val(dec_dcc_ex1_pfetch_val), + .dec_dcc_ex1_dcbtst_instr(dec_dcc_ex1_dcbtst_instr), + .dec_dcc_ex1_th_fld(dec_dcc_ex1_th_fld), + .dec_dcc_ex1_dcbtls_instr(dec_dcc_ex1_dcbtls_instr), + .dec_dcc_ex1_dcbtstls_instr(dec_dcc_ex1_dcbtstls_instr), + .dec_dcc_ex1_dcblc_instr(dec_dcc_ex1_dcblc_instr), + .dec_dcc_ex1_dcbst_instr(dec_dcc_ex1_dcbst_instr), + .dec_dcc_ex1_icbi_instr(dec_dcc_ex1_icbi_instr), + .dec_dcc_ex1_icblc_instr(dec_dcc_ex1_icblc_instr), + .dec_dcc_ex1_icbt_instr(dec_dcc_ex1_icbt_instr), + .dec_dcc_ex1_icbtls_instr(dec_dcc_ex1_icbtls_instr), + .dec_dcc_ex1_icswx_instr(dec_dcc_ex1_icswx_instr), + .dec_dcc_ex1_icswxdot_instr(dec_dcc_ex1_icswxdot_instr), + .dec_dcc_ex1_icswx_epid(dec_dcc_ex1_icswx_epid), + .dec_dcc_ex1_tlbsync_instr(dec_dcc_ex1_tlbsync_instr), + .dec_dcc_ex1_ldawx_instr(dec_dcc_ex1_ldawx_instr), + .dec_dcc_ex1_wclr_instr(dec_dcc_ex1_wclr_instr), + .dec_dcc_ex1_wchk_instr(dec_dcc_ex1_wchk_instr), + .dec_dcc_ex1_resv_instr(dec_dcc_ex1_resv_instr), + .dec_dcc_ex1_mutex_hint(dec_dcc_ex1_mutex_hint), + .dec_dcc_ex1_mbar_instr(dec_dcc_ex1_mbar_instr), + .dec_dcc_ex1_makeitso_instr(dec_dcc_ex1_makeitso_instr), + .dec_dcc_ex1_is_msgsnd(dec_dcc_ex1_is_msgsnd), + .dec_dcc_ex1_dci_instr(dec_dcc_ex1_dci_instr), + .dec_dcc_ex1_ici_instr(dec_dcc_ex1_ici_instr), + .dec_dcc_ex1_mword_instr(dec_dcc_ex1_mword_instr), + .dec_dcc_ex1_algebraic(dec_dcc_ex1_algebraic), + .dec_dcc_ex1_strg_index(dec_dcc_ex1_strg_index), + .dec_dcc_ex1_src_gpr(dec_dcc_ex1_src_gpr), + .dec_dcc_ex1_src_axu(dec_dcc_ex1_src_axu), + .dec_dcc_ex1_src_dp(dec_dcc_ex1_src_dp), + .dec_dcc_ex1_targ_gpr(dec_dcc_ex1_targ_gpr), + .dec_dcc_ex1_targ_axu(dec_dcc_ex1_targ_axu), + .dec_dcc_ex1_targ_dp(dec_dcc_ex1_targ_dp), + .dec_dcc_ex1_upd_form(dec_dcc_ex1_upd_form), + .dec_dcc_ex1_itag(dec_dcc_ex1_itag), + .dec_dcc_ex1_cr_fld(dec_dcc_ex1_cr_fld), + .dec_dcc_ex1_expt_det(dec_dcc_ex1_expt_det), + .dec_dcc_ex1_priv_prog(dec_dcc_ex1_priv_prog), + .dec_dcc_ex1_hypv_prog(dec_dcc_ex1_hypv_prog), + .dec_dcc_ex1_illeg_prog(dec_dcc_ex1_illeg_prog), + .dec_dcc_ex1_dlock_excp(dec_dcc_ex1_dlock_excp), + .dec_dcc_ex1_ilock_excp(dec_dcc_ex1_ilock_excp), + .dec_dcc_ex1_ehpriv_excp(dec_dcc_ex1_ehpriv_excp), + .dec_dcc_ex2_is_any_load_dac(dec_ex2_is_any_load_dac), + .dec_dcc_ex5_req_abort_rpt(dec_dcc_ex5_req_abort_rpt), + .dec_dcc_ex5_axu_abort_rpt(dec_dcc_ex5_axu_abort_rpt), + .dir_dcc_ex2_eff_addr(dir_dcc_ex2_eff_addr), + + // Directory Back-Invalidate + .lsq_ctl_rv0_back_inv(lsq_ctl_rv0_back_inv), + + // Derat Snoop-Invalidate + .derat_rv1_snoop_val(derat_rv1_snoop_val), + + // Directory Read Operation + .dir_dcc_ex4_way_tag_a(dir_dcc_ex4_way_tag_a), + .dir_dcc_ex4_way_tag_b(dir_dcc_ex4_way_tag_b), + .dir_dcc_ex4_way_tag_c(dir_dcc_ex4_way_tag_c), + .dir_dcc_ex4_way_tag_d(dir_dcc_ex4_way_tag_d), + .dir_dcc_ex4_way_tag_e(dir_dcc_ex4_way_tag_e), + .dir_dcc_ex4_way_tag_f(dir_dcc_ex4_way_tag_f), + .dir_dcc_ex4_way_tag_g(dir_dcc_ex4_way_tag_g), + .dir_dcc_ex4_way_tag_h(dir_dcc_ex4_way_tag_h), + .dir_dcc_ex4_way_par_a(dir_dcc_ex4_way_par_a), + .dir_dcc_ex4_way_par_b(dir_dcc_ex4_way_par_b), + .dir_dcc_ex4_way_par_c(dir_dcc_ex4_way_par_c), + .dir_dcc_ex4_way_par_d(dir_dcc_ex4_way_par_d), + .dir_dcc_ex4_way_par_e(dir_dcc_ex4_way_par_e), + .dir_dcc_ex4_way_par_f(dir_dcc_ex4_way_par_f), + .dir_dcc_ex4_way_par_g(dir_dcc_ex4_way_par_g), + .dir_dcc_ex4_way_par_h(dir_dcc_ex4_way_par_h), + .dir_dcc_ex5_way_a_dir(dir_dcc_ex5_way_a_dir), + .dir_dcc_ex5_way_b_dir(dir_dcc_ex5_way_b_dir), + .dir_dcc_ex5_way_c_dir(dir_dcc_ex5_way_c_dir), + .dir_dcc_ex5_way_d_dir(dir_dcc_ex5_way_d_dir), + .dir_dcc_ex5_way_e_dir(dir_dcc_ex5_way_e_dir), + .dir_dcc_ex5_way_f_dir(dir_dcc_ex5_way_f_dir), + .dir_dcc_ex5_way_g_dir(dir_dcc_ex5_way_g_dir), + .dir_dcc_ex5_way_h_dir(dir_dcc_ex5_way_h_dir), + .dir_dcc_ex5_dir_lru(dir_dcc_ex5_dir_lru), + + .derat_dcc_ex3_wimge_e(derat_dcc_ex3_wimge_e), + .derat_dcc_ex3_itagHit(derat_dcc_ex3_itagHit), + .derat_dcc_ex4_wimge(derat_dcc_ex4_wimge), + .derat_dcc_ex4_usr_bits(derat_dcc_ex4_usr_bits), + .derat_dcc_ex4_wlc(derat_dcc_ex4_wlc), + .derat_dcc_ex4_p_addr(derat_dcc_ex4_p_addr[64 - `REAL_IFAR_WIDTH:51]), + .derat_dcc_ex4_noop_touch(derat_dcc_ex4_noop_touch), + .derat_dcc_ex4_miss(derat_dcc_ex4_miss), + .derat_dcc_ex4_tlb_err(derat_dcc_ex4_tlb_err), + .derat_dcc_ex4_dsi(derat_dcc_ex4_dsi), + .derat_dcc_ex4_vf(derat_dcc_ex4_vf), + .derat_dcc_ex4_multihit_err_det(derat_dcc_ex4_multihit_err_det), + .derat_dcc_ex4_multihit_err_flush(derat_dcc_ex4_multihit_err_flush), + .derat_dcc_ex4_par_err_det(derat_dcc_ex4_par_err_det), + .derat_dcc_ex4_par_err_flush(derat_dcc_ex4_par_err_flush), + .derat_dcc_ex4_tlb_inelig(derat_dcc_ex4_tlb_inelig), + .derat_dcc_ex4_pt_fault(derat_dcc_ex4_pt_fault), + .derat_dcc_ex4_lrat_miss(derat_dcc_ex4_lrat_miss), + .derat_dcc_ex4_tlb_multihit(derat_dcc_ex4_tlb_multihit), + .derat_dcc_ex4_tlb_par_err(derat_dcc_ex4_tlb_par_err), + .derat_dcc_ex4_lru_par_err(derat_dcc_ex4_lru_par_err), + .derat_dcc_ex4_restart(derat_dcc_ex4_restart), + .derat_fir_par_err(derat_fir_par_err), + .derat_fir_multihit(derat_fir_multihit), + + // SetHold and ClrHold for itag + .derat_dcc_ex4_setHold(derat_dcc_ex4_setHold), + .derat_dcc_clr_hold(derat_dcc_clr_hold), + .derat_dcc_emq_idle(derat_dcc_emq_idle), + + .spr_dcc_ex4_dvc1_en(spr_dcc_ex4_dvc1_en), + .spr_dcc_ex4_dvc2_en(spr_dcc_ex4_dvc2_en), + .spr_dcc_ex4_dacrw1_cmpr(spr_dcc_ex4_dacrw1_cmpr), + .spr_dcc_ex4_dacrw2_cmpr(spr_dcc_ex4_dacrw2_cmpr), + .spr_dcc_ex4_dacrw3_cmpr(spr_dcc_ex4_dacrw3_cmpr), + .spr_dcc_ex4_dacrw4_cmpr(spr_dcc_ex4_dacrw4_cmpr), + .spr_dcc_spr_lesr(spr_dcc_spr_lesr), + + .dir_dcc_ex4_hit(dir_dcc_ex4_hit), + .dir_dcc_ex4_miss(dir_dcc_ex4_miss), + .dir_dcc_ex4_set_rel_coll(dir_dcc_ex4_set_rel_coll), + .dir_dcc_ex4_byp_restart(dir_dcc_ex4_byp_restart), + .dir_dcc_ex5_dir_perr_det(dir_dcc_ex5_dir_perr_det), + .dir_dcc_ex5_dc_perr_det(dir_dcc_ex5_dc_perr_det), + .dir_dcc_ex5_dir_perr_flush(dir_dcc_ex5_dir_perr_flush), + .dir_dcc_ex5_dc_perr_flush(dir_dcc_ex5_dc_perr_flush), + .dir_dcc_ex5_multihit_det(dir_dcc_ex5_multihit_det), + .dir_dcc_ex5_multihit_flush(dir_dcc_ex5_multihit_flush), + .dir_dcc_stq4_dir_perr_det(dir_dcc_stq4_dir_perr_det), + .dir_dcc_stq4_multihit_det(dir_dcc_stq4_multihit_det), + .dir_dcc_ex5_stp_flush(dir_dcc_ex5_stp_flush), + + // Completion Inputs + .iu_lq_cp_flush(iu_lq_cp_flush), + .iu_lq_recirc_val(iu_lq_recirc_val), + .iu_lq_cp_next_itag(iu_lq_cp_next_itag), + + // XER[SO] Read for CP_NEXT instructions (stcx./icswx./ldawx.) + .xu_lq_xer_cp_rd(xu_lq_xer_cp_rd), + + // Stage Flush + .fgen_ex1_stg_flush(fgen_ex1_stg_flush), + .fgen_ex2_stg_flush(fgen_ex2_stg_flush), + .fgen_ex3_stg_flush(fgen_ex3_stg_flush), + .fgen_ex4_cp_flush(fgen_ex4_cp_flush), + .fgen_ex4_stg_flush(fgen_ex4_stg_flush), + .fgen_ex5_stg_flush(fgen_ex5_stg_flush), + + .dir_dcc_rel3_dcarr_upd(dir_dcc_rel3_dcarr_upd), + + // Data Cache Config + .xu_lq_spr_ccr2_en_trace(xu_lq_spr_ccr2_en_trace), + .xu_lq_spr_ccr2_dfrat(xu_lq_spr_ccr2_dfrat), + .xu_lq_spr_ccr2_ap(xu_lq_spr_ccr2_ap), + .xu_lq_spr_ccr2_ucode_dis(xu_lq_spr_ccr2_ucode_dis), + .xu_lq_spr_ccr2_notlb(xu_lq_spr_ccr2_notlb), + .xu_lq_spr_xucr0_clkg_ctl(xu_lq_spr_xucr0_clkg_ctl), + .xu_lq_spr_xucr0_wlk(xu_lq_spr_xucr0_wlk), + .xu_lq_spr_xucr0_mbar_ack(xu_lq_spr_xucr0_mbar_ack), + .xu_lq_spr_xucr0_tlbsync(xu_lq_spr_xucr0_tlbsync), + .xu_lq_spr_xucr0_dcdis(xu_lq_spr_xucr0_dcdis), + .xu_lq_spr_xucr0_aflsta(xu_lq_spr_xucr0_aflsta), + .xu_lq_spr_xucr0_flsta(xu_lq_spr_xucr0_flsta), + .xu_lq_spr_xucr0_trace_um(xu_lq_spr_xucr0_trace_um), + .xu_lq_spr_xucr0_mddp(xu_lq_spr_xucr0_mddp), + .xu_lq_spr_xucr0_mdcp(xu_lq_spr_xucr0_mdcp), + .xu_lq_spr_xucr4_mmu_mchk(xu_lq_spr_xucr4_mmu_mchk), + .xu_lq_spr_xucr4_mddmh(xu_lq_spr_xucr4_mddmh), + .xu_lq_spr_msr_cm(xu_lq_spr_msr_cm), + .xu_lq_spr_msr_fp(xu_lq_spr_msr_fp), + .xu_lq_spr_msr_spv(xu_lq_spr_msr_spv), + .xu_lq_spr_msr_de(xu_lq_spr_msr_de), + .xu_lq_spr_dbcr0_idm(xu_lq_spr_dbcr0_idm), + .xu_lq_spr_epcr_duvd(xu_lq_spr_epcr_duvd), + + // MSR[GS,PR] bits, indicates which state we are running in + .xu_lq_spr_msr_gs(xu_lq_spr_msr_gs), + .xu_lq_spr_msr_pr(xu_lq_spr_msr_pr), + .xu_lq_spr_msr_ds(xu_lq_spr_msr_ds), + .mm_lq_lsu_lpidr(mm_lq_lsu_lpidr), + .mm_lq_pid(mm_lq_pid), + + // RESTART indicator + .lsq_ctl_ex5_ldq_restart(lsq_ctl_ex5_ldq_restart), + .lsq_ctl_ex5_stq_restart(lsq_ctl_ex5_stq_restart), + .lsq_ctl_ex5_stq_restart_miss(lsq_ctl_ex5_stq_restart_miss), + + // Store Data Forward + .lsq_ctl_ex5_fwd_val(lsq_ctl_ex5_fwd_val), + + .lsq_ctl_sync_in_stq(lsq_ctl_sync_in_stq), + + // Hold RV Indicator + .lsq_ctl_rv_hold_all(lsq_ctl_rv_hold_all), + + // Reservation station set barrier indicator + .lsq_ctl_rv_set_hold(lsq_ctl_rv_set_hold), + .lsq_ctl_rv_clr_hold(lsq_ctl_rv_clr_hold), + + // Reload/Commit Pipe + .lsq_ctl_stq1_stg_act(lsq_ctl_stq1_stg_act), + .lsq_ctl_stq1_val(lsq_ctl_stq1_val), + .lsq_ctl_stq1_thrd_id(lsq_ctl_stq1_thrd_id), + .lsq_ctl_stq1_mftgpr_val(lsq_ctl_stq1_mftgpr_val), + .lsq_ctl_stq1_mfdpf_val(lsq_ctl_stq1_mfdpf_val), + .lsq_ctl_stq1_mfdpa_val(lsq_ctl_stq1_mfdpa_val), + .lsq_ctl_stq1_store_val(lsq_ctl_stq1_store_val), + .lsq_ctl_stq1_watch_clr(lsq_ctl_stq1_watch_clr), + .lsq_ctl_stq1_l_fld(lsq_ctl_stq1_l_fld), + .lsq_ctl_stq1_resv(lsq_ctl_stq1_resv), + .lsq_ctl_stq1_ci(lsq_ctl_stq1_ci), + .lsq_ctl_stq1_axu_val(lsq_ctl_stq1_axu_val), + .lsq_ctl_stq1_epid_val(lsq_ctl_stq1_epid_val), + .lsq_ctl_stq2_blk_req(lsq_ctl_stq2_blk_req), + .lsq_ctl_stq4_xucr0_cul(lsq_ctl_stq4_xucr0_cul), + .lsq_ctl_stq5_itag(lsq_ctl_stq5_itag), + .lsq_ctl_stq5_tgpr(lsq_ctl_stq5_tgpr), + .lsq_ctl_rel1_gpr_val(lsq_ctl_rel1_gpr_val), + .lsq_ctl_rel1_ta_gpr(lsq_ctl_rel1_ta_gpr), + .lsq_ctl_rel1_upd_gpr(lsq_ctl_rel1_upd_gpr), + + // Store Queue Completion Report + .lsq_ctl_stq_cpl_ready(lsq_ctl_stq_cpl_ready), + .lsq_ctl_stq_cpl_ready_itag(lsq_ctl_stq_cpl_ready_itag), + .lsq_ctl_stq_cpl_ready_tid(lsq_ctl_stq_cpl_ready_tid), + .lsq_ctl_stq_n_flush(lsq_ctl_stq_n_flush), + .lsq_ctl_stq_np1_flush(lsq_ctl_stq_np1_flush), + .lsq_ctl_stq_exception_val(lsq_ctl_stq_exception_val), + .lsq_ctl_stq_exception(lsq_ctl_stq_exception), + .lsq_ctl_stq_dacrw(lsq_ctl_stq_dacrw), + .ctl_lsq_stq_cpl_blk(ctl_lsq_stq_cpl_blk), + + // Illegal LSWX has been determined + .lsq_ctl_ex3_strg_val(lsq_ctl_ex3_strg_val), + .lsq_ctl_ex3_strg_noop(lsq_ctl_ex3_strg_noop), + .lsq_ctl_ex3_illeg_lswx(lsq_ctl_ex3_illeg_lswx), + .lsq_ctl_ex3_ct_val(lsq_ctl_ex3_ct_val), + .lsq_ctl_ex3_be_ct(lsq_ctl_ex3_be_ct), + .lsq_ctl_ex3_le_ct(lsq_ctl_ex3_le_ct), + + // Directory Results Input + .dir_dcc_stq3_hit(dir_dcc_stq3_hit), + .dir_dcc_ex5_cr_rslt(dir_dcc_ex5_cr_rslt), + + // EX2 Execution Pipe Outputs + .dcc_dir_ex2_frc_align2(dcc_dir_ex2_frc_align2), + .dcc_dir_ex2_frc_align4(dcc_dir_ex2_frc_align4), + .dcc_dir_ex2_frc_align8(dcc_dir_ex2_frc_align8), + .dcc_dir_ex2_frc_align16(dcc_dir_ex2_frc_align16), + .dcc_dir_ex2_64bit_agen(dcc_dir_ex2_64bit_agen), + .dcc_dir_ex2_thrd_id(dcc_dir_ex2_thrd_id), + .dcc_derat_ex3_strg_noop(dcc_derat_ex3_strg_noop), + .dcc_derat_ex5_blk_tlb_req(dcc_derat_ex5_blk_tlb_req), + .dcc_derat_ex6_cplt(dcc_derat_ex6_cplt), + .dcc_derat_ex6_cplt_itag(dcc_derat_ex6_cplt_itag), + + // EX3 Execution Pipe Outputs + .dcc_dir_ex3_lru_upd(dcc_dir_ex3_lru_upd), + .dcc_dir_ex3_cache_acc(dcc_dir_ex3_cache_acc), + .dcc_dir_ex3_pfetch_val(dcc_dir_ex3_pfetch_val), + .dcc_dir_ex3_lock_set(dcc_dir_ex3_lock_set), + .dcc_dir_ex3_th_c(dcc_dir_ex3_th_c), + .dcc_dir_ex3_watch_set(dcc_dir_ex3_watch_set), + .dcc_dir_ex3_larx_val(dcc_dir_ex3_larx_val), + .dcc_dir_ex3_watch_chk(dcc_dir_ex3_watch_chk), + .dcc_dir_ex3_ddir_acc(dcc_dir_ex3_ddir_acc), + .dcc_dir_ex4_load_val(dcc_dir_ex4_load_val), + .dcc_spr_ex3_data_val(dcc_spr_ex3_data_val), + .dcc_spr_ex3_eff_addr(dcc_spr_ex3_eff_addr), + + .ctl_dat_ex3_opsize(ctl_dat_ex3_opsize), + .ctl_dat_ex3_le_mode(ctl_dat_ex3_le_mode), + .ctl_dat_ex3_le_ld_rotsel(ctl_dat_ex3_le_ld_rotsel), + .ctl_dat_ex3_be_ld_rotsel(ctl_dat_ex3_be_ld_rotsel), + .ctl_dat_ex3_algebraic(ctl_dat_ex3_algebraic), + .ctl_dat_ex3_le_alg_rotsel(ctl_dat_ex3_le_alg_rotsel), + + // EX4 Execution Pipe Outputs + .dcc_byp_rel2_stg_act(dcc_byp_rel2_stg_act), + .dcc_byp_rel3_stg_act(dcc_byp_rel3_stg_act), + .dcc_byp_ram_act(dcc_byp_ram_act), + .byp_dcc_ex2_req_aborted(byp_ex2_req_aborted), + .dcc_byp_ex4_moveOp_val(dcc_byp_ex4_moveOp_val), + .dcc_byp_stq6_moveOp_val(dcc_byp_stq6_moveOp_val), + .dcc_byp_ex4_move_data(dcc_byp_ex4_move_data), + .dcc_byp_ex5_lq_req_abort(dcc_byp_ex5_lq_req_abort), + .dcc_byp_ex5_byte_mask(dcc_byp_ex5_byte_mask), + .dcc_byp_ex6_thrd_id(dcc_byp_ex6_thrd_id), + .dcc_byp_ex6_dvc1_en(dcc_byp_ex6_dvc1_en), + .dcc_byp_ex6_dvc2_en(dcc_byp_ex6_dvc2_en), + .dcc_byp_ex6_dacr_cmpr(dcc_byp_ex6_dacr_cmpr), + .dcc_dir_ex4_p_addr(dcc_dir_ex4_p_addr), + .dcc_dir_stq6_store_val(dcc_dir_stq6_store_val), + + // Execution Pipe Outputs + .ctl_lsq_ex2_streq_val(ctl_lsq_ex2_streq_val), + .ctl_lsq_ex2_itag(ctl_lsq_ex2_itag), + .ctl_lsq_ex2_thrd_id(ctl_lsq_ex2_thrd_id), + .ctl_lsq_ex3_ldreq_val(ctl_lsq_ex3_ldreq_val), + .ctl_lsq_ex3_wchkall_val(ctl_lsq_ex3_wchkall_val), + .ctl_lsq_ex3_pfetch_val(ctl_lsq_ex3_pfetch_val), + .ctl_lsq_ex3_byte_en(ctl_lsq_ex3_byte_en), + .ctl_lsq_ex3_p_addr(ctl_lsq_ex3_p_addr), + .ctl_lsq_ex3_thrd_id(ctl_lsq_ex3_thrd_id), + .ctl_lsq_ex3_algebraic(ctl_lsq_ex3_algebraic), + .ctl_lsq_ex3_opsize(ctl_lsq_ex3_opsize), + .ctl_lsq_ex4_ldreq_val(ctl_lsq_ex4_ldreq_val), + .ctl_lsq_ex4_binvreq_val(ctl_lsq_ex4_binvreq_val), + .ctl_lsq_ex4_streq_val(ctl_lsq_ex4_streq_val), + .ctl_lsq_ex4_othreq_val(ctl_lsq_ex4_othreq_val), + .ctl_lsq_ex4_p_addr(ctl_lsq_ex4_p_addr), + .ctl_lsq_ex4_dReq_val(ctl_lsq_ex4_dReq_val), + .ctl_lsq_ex4_gath_load(ctl_lsq_ex4_gath_load), + .ctl_lsq_ex4_send_l2(ctl_lsq_ex4_send_l2), + .ctl_lsq_ex4_has_data(ctl_lsq_ex4_has_data), + .ctl_lsq_ex4_cline_chk(ctl_lsq_ex4_cline_chk), + .ctl_lsq_ex4_wimge(ctl_lsq_ex4_wimge), + .ctl_lsq_ex4_byte_swap(ctl_lsq_ex4_byte_swap), + .ctl_lsq_ex4_is_sync(ctl_lsq_ex4_is_sync), + .ctl_lsq_ex4_all_thrd_chk(ctl_lsq_ex4_all_thrd_chk), + .ctl_lsq_ex4_is_store(ctl_lsq_ex4_is_store), + .ctl_lsq_ex4_is_resv(ctl_lsq_ex4_is_resv), + .ctl_lsq_ex4_is_mfgpr(ctl_lsq_ex4_is_mfgpr), + .ctl_lsq_ex4_is_icswxr(ctl_lsq_ex4_is_icswxr), + .ctl_lsq_ex4_is_icbi(ctl_lsq_ex4_is_icbi), + .ctl_lsq_ex4_watch_clr(ctl_lsq_ex4_watch_clr), + .ctl_lsq_ex4_watch_clr_all(ctl_lsq_ex4_watch_clr_all), + .ctl_lsq_ex4_mtspr_trace(ctl_lsq_ex4_mtspr_trace), + .ctl_lsq_ex4_is_inval_op(ctl_lsq_ex4_is_inval_op), + .ctl_lsq_ex4_is_cinval(ctl_lsq_ex4_is_cinval), + .ctl_lsq_ex5_lock_clr(ctl_lsq_ex5_lock_clr), + .ctl_lsq_ex5_lock_set(ctl_lsq_ex5_lock_set), + .ctl_lsq_ex5_watch_set(ctl_lsq_ex5_watch_set), + .ctl_lsq_ex5_tgpr(ctl_lsq_ex5_tgpr), + .ctl_lsq_ex5_axu_val(ctl_lsq_ex5_axu_val), + .ctl_lsq_ex5_is_epid(ctl_lsq_ex5_is_epid), + .ctl_lsq_ex5_usr_def(ctl_lsq_ex5_usr_def), + .ctl_lsq_ex5_drop_rel(ctl_lsq_ex5_drop_rel), + .ctl_lsq_ex5_flush_req(ctl_lsq_ex5_flush_req), + .ctl_lsq_ex5_flush_pfetch(ctl_lsq_ex5_flush_pfetch), + .ctl_lsq_ex5_cmmt_events(ctl_lsq_ex5_cmmt_events), + .ctl_lsq_ex5_perf_val0(ctl_lsq_ex5_perf_val0), + .ctl_lsq_ex5_perf_sel0(ctl_lsq_ex5_perf_sel0), + .ctl_lsq_ex5_perf_val1(ctl_lsq_ex5_perf_val1), + .ctl_lsq_ex5_perf_sel1(ctl_lsq_ex5_perf_sel1), + .ctl_lsq_ex5_perf_val2(ctl_lsq_ex5_perf_val2), + .ctl_lsq_ex5_perf_sel2(ctl_lsq_ex5_perf_sel2), + .ctl_lsq_ex5_perf_val3(ctl_lsq_ex5_perf_val3), + .ctl_lsq_ex5_perf_sel3(ctl_lsq_ex5_perf_sel3), + .ctl_lsq_ex5_not_touch(ctl_lsq_ex5_not_touch), + .ctl_lsq_ex5_class_id(ctl_lsq_ex5_class_id), + .ctl_lsq_ex5_dvc(ctl_lsq_ex5_dvc), + .ctl_lsq_ex5_dacrw(ctl_lsq_ex5_dacrw), + .ctl_lsq_ex5_ttype(ctl_lsq_ex5_ttype), + .ctl_lsq_ex5_l_fld(ctl_lsq_ex5_l_fld), + .ctl_lsq_ex5_load_hit(ctl_lsq_ex5_load_hit), + .lsq_ctl_ex6_ldq_events(lsq_ctl_ex6_ldq_events), + .lsq_ctl_ex6_stq_events(lsq_ctl_ex6_stq_events), + .ctl_lsq_stq3_icswx_data(ctl_lsq_stq3_icswx_data), + .ctl_lsq_dbg_int_en(ctl_lsq_dbg_int_en), + .ctl_lsq_ldp_idle(ctl_lsq_ldp_idle), + + // SPR Directory Read Valid + .ctl_lsq_rv1_dir_rd_val(ctl_lsq_rv1_dir_rd_val), + + // Directory Read interface + .dcc_dec_arr_rd_rv1_val(dcc_dec_arr_rd_rv1_val), + .dcc_dec_arr_rd_congr_cl(dcc_dec_arr_rd_congr_cl), + + // MFTGPR instruction + .dcc_dec_stq3_mftgpr_val(dcc_dec_stq3_mftgpr_val), + .dcc_dec_stq5_mftgpr_val(dcc_dec_stq5_mftgpr_val), + + // SPR status + .lq_xu_spr_xucr0_cul(lq_xu_spr_xucr0_cul), + .dcc_dir_spr_xucr2_rmt(dcc_dir_spr_xucr2_rmt), + .spr_dcc_spr_xudbg0_exec(spr_dcc_spr_xudbg0_exec), + .spr_dcc_spr_xudbg0_tid(spr_dcc_spr_xudbg0_tid), + .spr_dcc_spr_xudbg0_way(spr_dcc_spr_xudbg0_way), + .spr_dcc_spr_xudbg0_row(spr_dcc_spr_xudbg0_row), + .dcc_spr_spr_xudbg0_done(dcc_spr_spr_xudbg0_done), + .dcc_spr_spr_xudbg1_valid(dcc_spr_spr_xudbg1_valid), + .dcc_spr_spr_xudbg1_watch(dcc_spr_spr_xudbg1_watch), + .dcc_spr_spr_xudbg1_parity(dcc_spr_spr_xudbg1_parity), + .dcc_spr_spr_xudbg1_lru(dcc_spr_spr_xudbg1_lru), + .dcc_spr_spr_xudbg1_lock(dcc_spr_spr_xudbg1_lock), + .dcc_spr_spr_xudbg2_tag(dcc_spr_spr_xudbg2_tag), + .spr_dcc_spr_xucr2_rmt(spr_dcc_spr_xucr2_rmt), + .spr_dcc_spr_lsucr0_clchk(spr_dcc_spr_lsucr0_clchk), + .spr_dcc_spr_acop_ct(spr_dcc_spr_acop_ct), + .spr_dcc_spr_hacop_ct(spr_dcc_spr_hacop_ct), + .spr_dcc_epsc_epr(spr_derat_epsc_epr), + .spr_dcc_epsc_eas(spr_derat_epsc_eas), + .spr_dcc_epsc_egs(spr_derat_epsc_egs), + .spr_dcc_epsc_elpid(spr_derat_epsc_elpid), + .spr_dcc_epsc_epid(spr_derat_epsc_epid), + + // Back-invalidate + .dcc_dir_ex2_binv_val(dcc_dir_ex2_binv_val), + + // Update Data Array Valid + .stq4_dcarr_wren(stq4_dcarr_wren), + + .dcc_byp_ram_sel(dcc_byp_ram_sel), + .dcc_dec_ex5_wren(dcc_dec_ex5_wren), + .lq_xu_gpr_ex5_wa(lq_xu_gpr_ex5_wa), + .lq_rv_gpr_ex6_wa(lq_rv_gpr_ex6_wa), + .lq_rv_gpr_rel_we(lq_rv_gpr_rel_we), + .lq_xu_gpr_rel_we(lq_xu_gpr_rel_we), + .lq_xu_axu_rel_we(lq_xu_axu_rel_we), + .lq_rv_gpr_rel_wa(lq_rv_gpr_rel_wa), + .lq_xu_gpr_rel_wa(lq_xu_gpr_rel_wa), + .lq_xu_ex5_abort(lq_xu_ex5_abort), + + .lq_xu_cr_ex5_we(lq_xu_cr_ex5_we), + .lq_xu_cr_ex5_wa(lq_xu_cr_ex5_wa), + .lq_xu_ex5_cr(lq_xu_ex5_cr), + + // Interface with AXU PassThru with XU + .lq_xu_axu_ex4_addr(lq_xu_axu_ex4_addr), + .lq_xu_axu_ex5_we(lq_xu_axu_ex5_we), + .lq_xu_axu_ex5_le(lq_xu_axu_ex5_le), + + // Outputs to Reservation Station + .lq_rv_itag1_vld(lq_rv_itag1_vld), + .lq_rv_itag1(lq_rv_itag1), + .lq_rv_itag1_restart(lq_rv_itag1_restart), + .lq_rv_itag1_abort(lq_rv_itag1_abort), + .lq_rv_itag1_hold(lq_rv_itag1_hold), + .lq_rv_itag1_cord(lq_rv_itag1_cord), + .lq_rv_clr_hold(lq_rv_clr_hold), + .dcc_dec_hold_all(dcc_dec_hold_all), + + // Completion Report + .lq0_iu_execute_vld(lq0_iu_execute_vld), + .lq0_iu_recirc_val(lq0_iu_recirc_val), + .lq0_iu_itag(lq0_iu_itag), + .lq0_iu_flush2ucode(lq0_iu_flush2ucode), + .lq0_iu_flush2ucode_type(lq0_iu_flush2ucode_type), + .lq0_iu_exception_val(lq0_iu_exception_val), + .lq0_iu_exception(lq0_iu_exception), + .lq0_iu_dear_val(lq0_iu_dear_val), + .lq0_iu_n_flush(lq0_iu_n_flush), + .lq0_iu_np1_flush(lq0_iu_np1_flush), + .lq0_iu_dacr_type(lq0_iu_dacr_type), + .lq0_iu_dacrw(lq0_iu_dacrw), + .lq0_iu_instr(lq0_iu_instr), + .lq0_iu_eff_addr(lq0_iu_eff_addr), + + // outputs to prefetch + .dcc_pf_ex5_eff_addr(dcc_pf_ex5_eff_addr), + .dcc_pf_ex5_req_val_4pf(dcc_pf_ex5_req_val_4pf), + .dcc_pf_ex5_act(dcc_pf_ex5_act), + .dcc_pf_ex5_thrd_id(dcc_pf_ex5_thrd_id), + .dcc_pf_ex5_loadmiss(dcc_pf_ex5_loadmiss), + .dcc_pf_ex5_itag(dcc_pf_ex5_itag), + + // Error Reporting + .lq_pc_err_derat_parity(lq_pc_err_derat_parity), + .lq_pc_err_dir_ldp_parity(lq_pc_err_dir_ldp_parity), + .lq_pc_err_dir_stp_parity(lq_pc_err_dir_stp_parity), + .lq_pc_err_dcache_parity(lq_pc_err_dcache_parity), + .lq_pc_err_derat_multihit(lq_pc_err_derat_multihit), + .lq_pc_err_dir_ldp_multihit(lq_pc_err_dir_ldp_multihit), + .lq_pc_err_dir_stp_multihit(lq_pc_err_dir_stp_multihit), + + // Ram Mode Control + .pc_lq_ram_active(pc_lq_ram_active), + .lq_pc_ram_data_val(lq_pc_ram_data_val), + + // LQ Pervasive + .ctl_perv_ex6_perf_events(ctl_perv_ex6_perf_events), + .ctl_perv_stq4_perf_events(ctl_perv_stq4_perf_events), + + + // ACT's + .dcc_dir_ex2_stg_act(dcc_dir_ex2_stg_act), + .dcc_dir_ex3_stg_act(dcc_dir_ex3_stg_act), + .dcc_dir_ex4_stg_act(dcc_dir_ex4_stg_act), + .dcc_dir_ex5_stg_act(dcc_dir_ex5_stg_act), + .dcc_dir_stq1_stg_act(dcc_dir_stq1_stg_act), + .dcc_dir_stq2_stg_act(dcc_dir_stq2_stg_act), + .dcc_dir_stq3_stg_act(dcc_dir_stq3_stg_act), + .dcc_dir_stq4_stg_act(dcc_dir_stq4_stg_act), + .dcc_dir_stq5_stg_act(dcc_dir_stq5_stg_act), + .dcc_dir_binv2_ex2_stg_act(dcc_dir_binv2_ex2_stg_act), + .dcc_dir_binv3_ex3_stg_act(dcc_dir_binv3_ex3_stg_act), + .dcc_dir_binv4_ex4_stg_act(dcc_dir_binv4_ex4_stg_act), + .dcc_dir_binv5_ex5_stg_act(dcc_dir_binv5_ex5_stg_act), + .dcc_dir_binv6_ex6_stg_act(dcc_dir_binv6_ex6_stg_act), + + // Pervasive + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .sg_0(sg_0), + .func_sl_thold_0_b(func_sl_thold_0_b), + .func_sl_force(func_sl_force), + .func_nsl_thold_0_b(func_nsl_thold_0_b), + .func_nsl_force(func_nsl_force), + .func_slp_sl_thold_0_b(func_slp_sl_thold_0_b), + .func_slp_sl_force(func_slp_sl_force), + .func_slp_nsl_thold_0_b(func_slp_nsl_thold_0_b), + .func_slp_nsl_force(func_slp_nsl_force), + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc[5]), + .mpw1_dc_b(mpw1_dc_b[5]), + .mpw2_dc_b(mpw2_dc_b), + .scan_in(func_scan_in_q[2]), + .scan_out(func_scan_out_int[2]) +); + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// LQ SPR control +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +lq_spr spr( + .nclk(nclk), + + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc[5]), + .mpw1_dc_b(mpw1_dc_b[5]), + .mpw2_dc_b(mpw2_dc_b), + + .ccfg_sl_force(cfg_sl_force), + .ccfg_sl_thold_0_b(cfg_sl_thold_0_b), + .func_sl_force(func_sl_force), + .func_sl_thold_0_b(func_sl_thold_0_b), + .func_nsl_force(func_nsl_force), + .func_nsl_thold_0_b(func_nsl_thold_0_b), + .sg_0(sg_0), + .scan_in(func_scan_in_q[10]), + .scan_out(spr_pf_func_scan), + .ccfg_scan_in(ccfg_scan_in), + .ccfg_scan_out(spr_derat_cfg_scan), + + .flush(iu_lq_cp_flush), + .ex1_valid(dec_spr_ex1_valid), + .ex3_data_val(dcc_spr_ex3_data_val), + .ex3_eff_addr(dcc_spr_ex3_eff_addr), + + // SlowSPR Interface + .slowspr_val_in(slowspr_val_in), + .slowspr_rw_in(slowspr_rw_in), + .slowspr_etid_in(slowspr_etid_in), + .slowspr_addr_in(slowspr_addr_in), + .slowspr_data_in(slowspr_data_in), + .slowspr_done_in(slowspr_done_in), + + .slowspr_val_out(slowspr_val_out), + .slowspr_rw_out(slowspr_rw_out), + .slowspr_etid_out(slowspr_etid_out), + .slowspr_addr_out(slowspr_addr_out), + .slowspr_data_out(slowspr_data_out), + .slowspr_done_out(slowspr_done_out), + + // DAC + .ex2_is_any_load_dac(dec_ex2_is_any_load_dac), + .ex2_is_any_store_dac(dec_ex2_is_any_store_dac), + + .spr_dcc_ex4_dvc1_en(spr_dcc_ex4_dvc1_en), + .spr_dcc_ex4_dvc2_en(spr_dcc_ex4_dvc2_en), + .spr_dcc_ex4_dacrw1_cmpr(spr_dcc_ex4_dacrw1_cmpr), + .spr_dcc_ex4_dacrw2_cmpr(spr_dcc_ex4_dacrw2_cmpr), + .spr_dcc_ex4_dacrw3_cmpr(spr_dcc_ex4_dacrw3_cmpr), + .spr_dcc_ex4_dacrw4_cmpr(spr_dcc_ex4_dacrw4_cmpr), + + // SPRs + .spr_msr_pr(xu_lq_spr_msr_pr), + .spr_msr_gs(xu_lq_spr_msr_gs), + .spr_msr_ds(xu_lq_spr_msr_ds), + .spr_dbcr0_dac1(xu_lq_spr_dbcr0_dac1), + .spr_dbcr0_dac2(xu_lq_spr_dbcr0_dac2), + .spr_dbcr0_dac3(xu_lq_spr_dbcr0_dac3), + .spr_dbcr0_dac4(xu_lq_spr_dbcr0_dac4), + + .spr_xudbg0_exec(spr_dcc_spr_xudbg0_exec), + .spr_xudbg0_tid(spr_dcc_spr_xudbg0_tid), + .spr_xudbg0_done(dcc_spr_spr_xudbg0_done), + .spr_xudbg0_way(spr_dcc_spr_xudbg0_way), + .spr_xudbg0_row(spr_dcc_spr_xudbg0_row), + .spr_xudbg1_valid(dcc_spr_spr_xudbg1_valid), + .spr_xudbg1_watch(dcc_spr_spr_xudbg1_watch), + .spr_xudbg1_parity(dcc_spr_spr_xudbg1_parity), + .spr_xudbg1_lru(dcc_spr_spr_xudbg1_lru), + .spr_xudbg1_lock(dcc_spr_spr_xudbg1_lock), + .spr_xudbg2_tag(dcc_spr_spr_xudbg2_tag), + .spr_dbcr2_dvc1be(spr_dbcr2_dvc1be), + .spr_dbcr2_dvc2be(spr_dbcr2_dvc2be), + .spr_dbcr2_dvc1m(spr_dbcr2_dvc1m), + .spr_dbcr2_dvc2m(spr_dbcr2_dvc2m), + + .spr_dvc1(spr_dvc1_dbg), + .spr_dvc2(spr_dvc2_dbg), + .spr_pesr(spr_pf_spr_pesr), + .spr_lesr1_muxseleb0(spr_lesr1_muxseleb0), + .spr_lesr1_muxseleb1(spr_lesr1_muxseleb1), + .spr_lesr1_muxseleb2(spr_lesr1_muxseleb2), + .spr_lesr1_muxseleb3(spr_lesr1_muxseleb3), + .spr_lesr2_muxseleb4(spr_lesr2_muxseleb4), + .spr_lesr2_muxseleb5(spr_lesr2_muxseleb5), + .spr_lesr2_muxseleb6(spr_lesr2_muxseleb6), + .spr_lesr2_muxseleb7(spr_lesr2_muxseleb7), + .spr_lsucr0_lca(ctl_lsq_spr_lsucr0_lca), + .spr_lsucr0_sca(ctl_lsq_spr_lsucr0_sca), + .spr_lsucr0_lge(ctl_lsq_spr_lsucr0_lge), + .spr_lsucr0_b2b(ctl_lsq_spr_lsucr0_b2b), + .spr_lsucr0_dfwd(ctl_lsq_spr_lsucr0_dfwd), + .spr_lsucr0_clchk(spr_dcc_spr_lsucr0_clchk), + .spr_lsucr0_ford(ctl_lsq_spr_lsucr0_ford), + .spr_xucr2_rmt3(spr_dcc_spr_xucr2_rmt[32:39]), + .spr_xucr2_rmt2(spr_dcc_spr_xucr2_rmt[40:47]), + .spr_xucr2_rmt1(spr_dcc_spr_xucr2_rmt[48:55]), + .spr_xucr2_rmt0(spr_dcc_spr_xucr2_rmt[56:63]), + .spr_acop_ct(spr_dcc_spr_acop_ct), + .spr_dbcr3_ivc(lq_iu_spr_dbcr3_ivc), + .spr_dscr_lsd(spr_pf_spr_dscr_lsd), + .spr_dscr_snse(spr_pf_spr_dscr_snse), + .spr_dscr_sse(spr_pf_spr_dscr_sse), + .spr_dscr_dpfd(spr_pf_spr_dscr_dpfd), + .spr_eplc_wr(spr_derat_eplc_wr), + .spr_epsc_wr(spr_derat_epsc_wr), + .spr_eplc_epr(spr_derat_eplc_epr), + .spr_eplc_eas(spr_derat_eplc_eas), + .spr_eplc_egs(spr_derat_eplc_egs), + .spr_eplc_elpid(spr_derat_eplc_elpid), + .spr_eplc_epid(spr_derat_eplc_epid), + .spr_epsc_epr(spr_derat_epsc_epr), + .spr_epsc_eas(spr_derat_epsc_eas), + .spr_epsc_egs(spr_derat_epsc_egs), + .spr_epsc_elpid(spr_derat_epsc_elpid), + .spr_epsc_epid(spr_derat_epsc_epid), + .spr_hacop_ct(spr_dcc_spr_hacop_ct), + + // Power + .vdd(vdd), + .gnd(gnd) +); + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// DIRECTORY +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +lq_dir #(.WAYDATASIZE(WAYDATASIZE), .PARBITS(PARBITS)) dir( + + // ACT's + .dcc_dir_ex2_stg_act(dcc_dir_ex2_stg_act), + .dcc_dir_ex3_stg_act(dcc_dir_ex3_stg_act), + .dcc_dir_ex4_stg_act(dcc_dir_ex4_stg_act), + .dcc_dir_ex5_stg_act(dcc_dir_ex5_stg_act), + .dcc_dir_stq1_stg_act(dcc_dir_stq1_stg_act), + .dcc_dir_stq2_stg_act(dcc_dir_stq2_stg_act), + .dcc_dir_stq3_stg_act(dcc_dir_stq3_stg_act), + .dcc_dir_stq4_stg_act(dcc_dir_stq4_stg_act), + .dcc_dir_stq5_stg_act(dcc_dir_stq5_stg_act), + .dcc_dir_binv2_ex2_stg_act(dcc_dir_binv2_ex2_stg_act), + .dcc_dir_binv3_ex3_stg_act(dcc_dir_binv3_ex3_stg_act), + .dcc_dir_binv4_ex4_stg_act(dcc_dir_binv4_ex4_stg_act), + .dcc_dir_binv5_ex5_stg_act(dcc_dir_binv5_ex5_stg_act), + .dcc_dir_binv6_ex6_stg_act(dcc_dir_binv6_ex6_stg_act), + + // AGEN Sources + .byp_dir_ex2_rs1(byp_dir_ex2_rs1), + .byp_dir_ex2_rs2(byp_dir_ex2_rs2), + .dcc_dir_ex2_64bit_agen(dcc_dir_ex2_64bit_agen), + + // Error Inject + .pc_lq_inj_dcachedir_ldp_parity(pc_lq_inj_dcachedir_ldp_parity), + .pc_lq_inj_dcachedir_ldp_multihit(pc_lq_inj_dcachedir_ldp_multihit), + .pc_lq_inj_dcachedir_stp_parity(pc_lq_inj_dcachedir_stp_parity), + .pc_lq_inj_dcachedir_stp_multihit(pc_lq_inj_dcachedir_stp_multihit), + + .dcc_dir_ex2_binv_val(dcc_dir_ex2_binv_val), + .dcc_dir_ex2_thrd_id(dcc_dir_ex2_thrd_id), + .dcc_dir_ex3_cache_acc(dcc_dir_ex3_cache_acc), + .dcc_dir_ex3_pfetch_val(dcc_dir_ex3_pfetch_val), + .dcc_dir_ex3_lru_upd(dcc_dir_ex3_lru_upd), + .dcc_dir_ex3_lock_set(dcc_dir_ex3_lock_set), + .dcc_dir_ex3_th_c(dcc_dir_ex3_th_c), + .dcc_dir_ex3_watch_set(dcc_dir_ex3_watch_set), + .dcc_dir_ex3_larx_val(dcc_dir_ex3_larx_val), + .dcc_dir_ex3_watch_chk(dcc_dir_ex3_watch_chk), + .dcc_dir_ex3_ddir_acc(dcc_dir_ex3_ddir_acc), + .dcc_dir_ex4_load_val(dcc_dir_ex4_load_val), + .dcc_dir_ex4_p_addr(dcc_dir_ex4_p_addr), + .derat_dir_ex4_wimge_i(derat_dcc_ex4_wimge[1]), + .dcc_dir_stq6_store_val(dcc_dir_stq6_store_val), + + .dat_ctl_dcarr_perr_way(dat_ctl_dcarr_perr_way), + + .xu_lq_spr_xucr0_wlk(xu_lq_spr_xucr0_wlk), + .xu_lq_spr_xucr0_dcdis(xu_lq_spr_xucr0_dcdis), + .xu_lq_spr_xucr0_clfc(xu_lq_spr_xucr0_clfc), + .xu_lq_spr_xucr0_cls(xu_lq_spr_xucr0_cls), + .dcc_dir_spr_xucr2_rmt(dcc_dir_spr_xucr2_rmt), + .dcc_dir_ex2_frc_align16(dcc_dir_ex2_frc_align16), + .dcc_dir_ex2_frc_align8(dcc_dir_ex2_frc_align8), + .dcc_dir_ex2_frc_align4(dcc_dir_ex2_frc_align4), + .dcc_dir_ex2_frc_align2(dcc_dir_ex2_frc_align2), + + // RELOAD/COMMIT Control + .lsq_ctl_stq1_val(lsq_ctl_stq1_val), + .lsq_ctl_stq2_blk_req(lsq_ctl_stq2_blk_req), + .lsq_ctl_stq1_thrd_id(lsq_ctl_stq1_thrd_id), + .lsq_ctl_rel1_thrd_id(lsq_ctl_rel1_thrd_id), + .lsq_ctl_stq1_store_val(lsq_ctl_stq1_store_val), + .lsq_ctl_stq1_ci(lsq_ctl_stq1_ci), + .lsq_ctl_stq1_lock_clr(lsq_ctl_stq1_lock_clr), + .lsq_ctl_stq1_watch_clr(lsq_ctl_stq1_watch_clr), + .lsq_ctl_stq1_l_fld(lsq_ctl_stq1_l_fld), + .lsq_ctl_stq1_inval(lsq_ctl_stq1_inval), + .lsq_ctl_stq1_dci_val(lsq_ctl_stq1_dci_val), + .lsq_ctl_stq1_addr(lsq_ctl_stq1_addr), + .lsq_ctl_rel1_clr_val(lsq_ctl_rel1_clr_val), + .lsq_ctl_rel1_set_val(lsq_ctl_rel1_set_val), + .lsq_ctl_rel1_data_val(lsq_ctl_rel1_data_val), + .lsq_ctl_rel1_back_inv(lsq_ctl_rel1_back_inv), + .lsq_ctl_rel1_tag(lsq_ctl_rel1_tag), + .lsq_ctl_rel1_classid(lsq_ctl_rel1_classid), + .lsq_ctl_rel1_lock_set(lsq_ctl_rel1_lock_set), + .lsq_ctl_rel1_watch_set(lsq_ctl_rel1_watch_set), + .lsq_ctl_rel2_blk_req(lsq_ctl_rel2_blk_req), + .lsq_ctl_rel2_upd_val(lsq_ctl_rel2_upd_val), + .lsq_ctl_rel3_l1dump_val(lsq_ctl_rel3_l1dump_val), + .lsq_ctl_rel3_clr_relq(lsq_ctl_rel3_clr_relq), + .ctl_lsq_stq4_perr_reject(ctl_lsq_stq4_perr_reject), + .ctl_dat_stq5_way_perr_inval(ctl_dat_stq5_way_perr_inval), + + // Instruction Flush + .fgen_ex3_stg_flush(fgen_ex3_stg_flush), + .fgen_ex4_cp_flush(fgen_ex4_cp_flush), + .fgen_ex4_stg_flush(fgen_ex4_stg_flush), + .fgen_ex5_stg_flush(fgen_ex5_stg_flush), + + // Directory Read Interface + .dir_arr_rd_addr0_01(dir_arr_rd_addr0_01), + .dir_arr_rd_addr0_23(dir_arr_rd_addr0_23), + .dir_arr_rd_addr0_45(dir_arr_rd_addr0_45), + .dir_arr_rd_addr0_67(dir_arr_rd_addr0_67), + .dir_arr_rd_data0(dir_arr_rd_data0), + .dir_arr_rd_data1(dir_arr_rd_data1), + + // Directory Write Interface + .dir_arr_wr_enable(dir_arr_wr_enable_int), + .dir_arr_wr_way(dir_arr_wr_way_int), + .dir_arr_wr_addr(dir_arr_wr_addr_int), + .dir_arr_wr_data(dir_arr_wr_data_int), + + // LQ Pipe Outputs + .dir_dcc_ex2_eff_addr(dir_dcc_ex2_eff_addr), + .dir_derat_ex2_eff_addr(dir_derat_ex2_eff_addr), + .dir_dcc_ex4_hit(dir_dcc_ex4_hit), + .dir_dcc_ex4_miss(dir_dcc_ex4_miss), + .ctl_dat_ex4_way_hit(ctl_dat_ex4_way_hit), + + // COMMIT Pipe Hit indicator + .dir_dcc_stq3_hit(dir_dcc_stq3_hit), + + // CR results + .dir_dcc_ex5_cr_rslt(dir_dcc_ex5_cr_rslt), + + // Performance Events + .ctl_perv_dir_perf_events(ctl_perv_dir_perf_events), + + // Data Array Controls + .dir_dcc_rel3_dcarr_upd(dir_dcc_rel3_dcarr_upd), + .dir_dec_rel3_dir_wr_val(dir_dec_rel3_dir_wr_val), + .dir_dec_rel3_dir_wr_addr(dir_dec_rel3_dir_wr_addr), + + .stq4_dcarr_way_en(stq4_dcarr_way_en), + + // SPR status + .lq_xu_spr_xucr0_cslc_xuop(lq_xu_spr_xucr0_cslc_xuop), + .lq_xu_spr_xucr0_cslc_binv(lq_xu_spr_xucr0_cslc_binv), + .lq_xu_spr_xucr0_clo(lq_xu_spr_xucr0_clo), + + // L1 Directory Contents + .dir_dcc_ex4_way_tag_a(dir_dcc_ex4_way_tag_a), + .dir_dcc_ex4_way_tag_b(dir_dcc_ex4_way_tag_b), + .dir_dcc_ex4_way_tag_c(dir_dcc_ex4_way_tag_c), + .dir_dcc_ex4_way_tag_d(dir_dcc_ex4_way_tag_d), + .dir_dcc_ex4_way_tag_e(dir_dcc_ex4_way_tag_e), + .dir_dcc_ex4_way_tag_f(dir_dcc_ex4_way_tag_f), + .dir_dcc_ex4_way_tag_g(dir_dcc_ex4_way_tag_g), + .dir_dcc_ex4_way_tag_h(dir_dcc_ex4_way_tag_h), + .dir_dcc_ex4_way_par_a(dir_dcc_ex4_way_par_a), + .dir_dcc_ex4_way_par_b(dir_dcc_ex4_way_par_b), + .dir_dcc_ex4_way_par_c(dir_dcc_ex4_way_par_c), + .dir_dcc_ex4_way_par_d(dir_dcc_ex4_way_par_d), + .dir_dcc_ex4_way_par_e(dir_dcc_ex4_way_par_e), + .dir_dcc_ex4_way_par_f(dir_dcc_ex4_way_par_f), + .dir_dcc_ex4_way_par_g(dir_dcc_ex4_way_par_g), + .dir_dcc_ex4_way_par_h(dir_dcc_ex4_way_par_h), + .dir_dcc_ex5_way_a_dir(dir_dcc_ex5_way_a_dir), + .dir_dcc_ex5_way_b_dir(dir_dcc_ex5_way_b_dir), + .dir_dcc_ex5_way_c_dir(dir_dcc_ex5_way_c_dir), + .dir_dcc_ex5_way_d_dir(dir_dcc_ex5_way_d_dir), + .dir_dcc_ex5_way_e_dir(dir_dcc_ex5_way_e_dir), + .dir_dcc_ex5_way_f_dir(dir_dcc_ex5_way_f_dir), + .dir_dcc_ex5_way_g_dir(dir_dcc_ex5_way_g_dir), + .dir_dcc_ex5_way_h_dir(dir_dcc_ex5_way_h_dir), + .dir_dcc_ex5_dir_lru(dir_dcc_ex5_dir_lru), + + // Reject Cases + .dir_dcc_ex4_set_rel_coll(dir_dcc_ex4_set_rel_coll), + .dir_dcc_ex4_byp_restart(dir_dcc_ex4_byp_restart), + .dir_dcc_ex5_dir_perr_det(dir_dcc_ex5_dir_perr_det), + .dir_dcc_ex5_dc_perr_det(dir_dcc_ex5_dc_perr_det), + .dir_dcc_ex5_dir_perr_flush(dir_dcc_ex5_dir_perr_flush), + .dir_dcc_ex5_dc_perr_flush(dir_dcc_ex5_dc_perr_flush), + .dir_dcc_ex5_multihit_det(dir_dcc_ex5_multihit_det), + .dir_dcc_ex5_multihit_flush(dir_dcc_ex5_multihit_flush), + .dir_dcc_stq4_dir_perr_det(dir_dcc_stq4_dir_perr_det), + .dir_dcc_stq4_multihit_det(dir_dcc_stq4_multihit_det), + .dir_dcc_ex5_stp_flush(dir_dcc_ex5_stp_flush), + + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .sg_0(sg_0), + .func_sl_thold_0_b(func_sl_thold_0_b), + .func_sl_force(func_sl_force), + .func_slp_sl_thold_0_b(func_slp_sl_thold_0_b), + .func_slp_sl_force(func_slp_sl_force), + .func_nsl_thold_0_b(func_nsl_thold_0_b), + .func_nsl_force(func_nsl_force), + .func_slp_nsl_thold_0_b(func_slp_nsl_thold_0_b), + .func_slp_nsl_force(func_slp_nsl_force), + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc[5]), + .mpw1_dc_b(mpw1_dc_b[5]), + .mpw2_dc_b(mpw2_dc_b), + .scan_in(dir_func_scan_in), + .scan_out(func_scan_out_int[3:7]) +); +assign dir_func_scan_in[3:7] = {func_scan_in_q[3:6],arr_func_scan_out}; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// DIRECTORY ARRAYS +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +generate + if (`DC_SIZE == 15 & `CL_SIZE == 6) + begin : dc32Kdir64B + + // number of addressable register in this array + // width of the bus to address all ports (2^portadrbus_width >= addressable_ports) + // bitwidth of ports + // number of ways + tri_64x34_8w_1r1w #(.addressable_ports(64), .addressbus_width(6), .port_bitwidth(WAYDATASIZE), .ways(8)) arr( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) + // POWER PINS + .vcs(vdd), + .vdd(vdd), + .gnd(gnd), + + // CLOCK AND CLOCKCONTROL PORTS + .nclk(nclk), + .rd_act(dec_dir_ex2_dir_rd_act), + .wr_act(tiup), + .sg_0(sg_0), + .abst_sl_thold_0(abst_slp_sl_thold_0), // Need to use Sleep THOLDS, This copy is active while in sleep mode + .ary_nsl_thold_0(ary_slp_nsl_thold_0), // Need to use Sleep THOLDS, This copy is active while in sleep mode + .time_sl_thold_0(time_sl_thold_0), + .repr_sl_thold_0(repr_sl_thold_0), + .func_sl_force(func_slp_sl_force), // Need to use Sleep THOLDS, This copy is active while in sleep mode + .func_sl_thold_0_b(func_slp_sl_thold_0_b), // Need to use Sleep THOLDS, This copy is active while in sleep mode + .g8t_clkoff_dc_b(g8t_clkoff_dc_b), + .ccflush_dc(pc_lq_ccflush_dc), + .scan_dis_dc_b(an_ac_scan_dis_dc_b), + .scan_diag_dc(an_ac_scan_diag_dc), + .g8t_d_mode_dc(g8t_d_mode_dc), + .g8t_mpw1_dc_b(g8t_mpw1_dc_b), + .g8t_mpw2_dc_b(g8t_mpw2_dc_b), + .g8t_delay_lclkr_dc(g8t_delay_lclkr_dc), + .d_mode_dc(d_mode_dc), + .mpw1_dc_b(mpw1_dc_b[5]), + .mpw2_dc_b(mpw2_dc_b), + .delay_lclkr_dc(delay_lclkr_dc[5]), + + // ABIST + .wr_abst_act(pc_lq_abist_g8t_wenb_q), + .rd0_abst_act(pc_lq_abist_g8t1p_renb_0_q), + .abist_di(pc_lq_abist_di_0_q), + .abist_bw_odd(pc_lq_abist_g8t_bw_1_q), + .abist_bw_even(pc_lq_abist_g8t_bw_0_q), + .abist_wr_adr(pc_lq_abist_waddr_0_q), + .abist_rd0_adr(pc_lq_abist_raddr_0_q[3:8]), + .tc_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc), + .abist_ena_1(pc_lq_abist_ena_dc), + .abist_g8t_rd0_comp_ena(pc_lq_abist_wl64_comp_ena_q), + .abist_raw_dc_b(pc_lq_abist_raw_dc_b), + .obs0_abist_cmp(pc_lq_abist_g8t_dcomp_q), + + // SCAN PORTS + .abst_scan_in(abst_scan_in_q), + .time_scan_in(time_scan_in_q[0]), + .repr_scan_in(repr_scan_in_q[0]), + .func_scan_in(func_scan_in_q[7]), + .abst_scan_out(abst_scan_out_int[0]), + .time_scan_out(time_scan_out_int[0]), + .repr_scan_out(repr_scan_out_int[0]), + .func_scan_out(arr_func_scan_out), + + // BOLT-ON + .lcb_bolt_sl_thold_0(bolt_sl_thold_0), + .pc_bo_enable_2(bo_enable_2), + .pc_bo_reset(pc_lq_bo_reset), + .pc_bo_unload(pc_lq_bo_unload), + .pc_bo_repair(pc_lq_bo_repair), + .pc_bo_shdata(pc_lq_bo_shdata), + .pc_bo_select(pc_lq_bo_select), + .bo_pc_failout(lq_pc_bo_fail), + .bo_pc_diagloop(lq_pc_bo_diagout), + .tri_lcb_mpw1_dc_b(mpw1_dc_b[5]), + .tri_lcb_mpw2_dc_b(mpw2_dc_b), + .tri_lcb_delay_lclkr_dc(delay_lclkr_dc[5]), + .tri_lcb_clkoff_dc_b(clkoff_dc_b), + .tri_lcb_act_dis_dc(tidn), + + // Write Ports + .write_enable(dir_arr_wr_enable_int), + .way(dir_arr_wr_way_int), + .addr_wr(dir_arr_wr_addr_int), + .data_in(dir_arr_wr_data_int), + + // Read Ports + .addr_rd_01(dir_arr_rd_addr0_01), + .addr_rd_23(dir_arr_rd_addr0_23), + .addr_rd_45(dir_arr_rd_addr0_45), + .addr_rd_67(dir_arr_rd_addr0_67), + .data_out(dir_arr_rd_data0) + ); + end +endgenerate + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// D-ERATS +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +lq_derat derat( + // POWER PINS + .gnd(gnd), + .vdd(vdd), + .vcs(vdd), + + // CLOCK and CLOCK CONTROL ports + .nclk(nclk), + .pc_xu_init_reset(pc_lq_init_reset), + .pc_xu_ccflush_dc(pc_lq_ccflush_dc), + .tc_scan_dis_dc_b(an_ac_scan_dis_dc_b), + .tc_scan_diag_dc(an_ac_scan_diag_dc), + .tc_lbist_en_dc(an_ac_lbist_en_dc), + .an_ac_atpg_en_dc(an_ac_atpg_en_dc), + .an_ac_grffence_en_dc(an_ac_grffence_en_dc), + + .lcb_d_mode_dc(d_mode_dc), + .lcb_clkoff_dc_b(clkoff_dc_b), + .lcb_act_dis_dc(tidn), + .lcb_mpw1_dc_b(mpw1_dc_b), + .lcb_mpw2_dc_b(mpw2_dc_b), + .lcb_delay_lclkr_dc(delay_lclkr_dc), + + .pc_func_sl_thold_2(func_sl_thold_2), + .pc_func_slp_sl_thold_2(func_slp_sl_thold_2), + .pc_func_slp_nsl_thold_2(func_slp_nsl_thold_2), + .pc_cfg_slp_sl_thold_2(cfg_slp_sl_thold_2), + .pc_regf_slp_sl_thold_2(regf_slp_sl_thold_2), + .pc_time_sl_thold_2(time_sl_thold_2), + .pc_sg_2(sg_2), + .pc_fce_2(fce_2), + + .cam_clkoff_dc_b(cam_clkoff_dc_b), + .cam_act_dis_dc(cam_act_dis_dc), + .cam_d_mode_dc(cam_d_mode_dc), + .cam_delay_lclkr_dc(cam_delay_lclkr_dc), + .cam_mpw1_dc_b(cam_mpw1_dc_b), + .cam_mpw2_dc_b(cam_mpw2_dc_b), + + .ac_func_scan_in(func_scan_in_q[8:9]), + .ac_func_scan_out(func_scan_out_int[8:9]), + .ac_ccfg_scan_in(spr_derat_cfg_scan), + .ac_ccfg_scan_out(ccfg_scan_out_int), + .time_scan_in(time_scan_in_q[1]), + .time_scan_out(time_scan_out_int[1]), + .regf_scan_in(regf_scan_in_q), + .regf_scan_out(regf_scan_out_int), + + // Functional ports + // lsu pipelined instructions + .dec_derat_ex1_derat_act(dec_derat_ex1_derat_act), + // ttypes + .dec_derat_ex0_val(dec_derat_ex0_val), + .dec_derat_ex0_is_extload(dec_derat_ex0_is_extload), + .dec_derat_ex0_is_extstore(dec_derat_ex0_is_extstore), + .dec_derat_ex1_pfetch_val(dec_derat_ex1_pfetch_val), + .dec_derat_ex1_is_load(dec_derat_ex1_is_load), + .dec_derat_ex1_is_store(dec_derat_ex1_is_store), + .dec_derat_ex1_is_touch(dec_derat_ex1_is_touch), + .dec_derat_ex1_icbtls_instr(dec_dcc_ex1_icbtls_instr), + .dec_derat_ex1_icblc_instr(dec_dcc_ex1_icblc_instr), + .dec_derat_ex1_ra_eq_ea(dec_derat_ex1_ra_eq_ea), + .dec_derat_ex1_byte_rev(dec_derat_ex1_byte_rev), + .byp_derat_ex2_req_aborted(byp_ex2_req_aborted), + .dcc_derat_ex3_strg_noop(dcc_derat_ex3_strg_noop), + .dcc_derat_ex5_blk_tlb_req(dcc_derat_ex5_blk_tlb_req), + .dcc_derat_ex6_cplt(dcc_derat_ex6_cplt), + .dcc_derat_ex6_cplt_itag(dcc_derat_ex6_cplt_itag), + + .dir_derat_ex2_epn_arr(dir_derat_ex2_eff_addr[64 - (2 ** `GPR_WIDTH_ENC):51]), + .dir_derat_ex2_epn_nonarr(dir_dcc_ex2_eff_addr[64 - (2 ** `GPR_WIDTH_ENC):51]), + .iu_lq_recirc_val(iu_lq_recirc_val), + .iu_lq_cp_next_itag(iu_lq_cp_next_itag), + .lsq_ctl_oldest_tid(lsq_ctl_oldest_tid), + .lsq_ctl_oldest_itag(lsq_ctl_oldest_itag), + .dec_derat_ex1_itag(dec_dcc_ex1_itag), + .derat_dcc_ex4_restart(derat_dcc_ex4_restart), + + // SetHold and ClrHold for itag + .derat_dcc_ex4_setHold(derat_dcc_ex4_setHold), + .derat_dcc_clr_hold(derat_dcc_clr_hold), + .derat_dcc_emq_idle(derat_dcc_emq_idle), + + // ordered instructions + .xu_lq_act(xu_lq_act), + .xu_lq_val(xu_lq_val), + .xu_lq_is_eratre(xu_lq_is_eratre), + .xu_lq_is_eratwe(xu_lq_is_eratwe), + .xu_lq_is_eratsx(xu_lq_is_eratsx), + .xu_lq_is_eratilx(xu_lq_is_eratilx), + .xu_lq_ws(xu_lq_ws), + .xu_lq_ra_entry(xu_lq_ra_entry), + .xu_lq_rs_data(xu_lq_rs_data), + .lq_xu_ex5_data(lq_xu_ex5_data), + .lq_xu_ord_par_err(lq_xu_ord_par_err), + .lq_xu_ord_read_done(lq_xu_ord_read_done), + .lq_xu_ord_write_done(lq_xu_ord_write_done), + + // context synchronizing event + .iu_lq_isync(iu_lq_isync), + .iu_lq_csync(iu_lq_csync), + + // reload from mmu + .mm_derat_rel_val(mm_lq_rel_val), + .mm_derat_rel_data(mm_lq_rel_data), + .mm_derat_rel_emq(mm_lq_rel_emq), + .mm_lq_itag(mm_lq_itag), + .mm_lq_tlb_miss(mm_lq_tlb_miss), + .mm_lq_tlb_inelig(mm_lq_tlb_inelig), + .mm_lq_pt_fault(mm_lq_pt_fault), + .mm_lq_lrat_miss(mm_lq_lrat_miss), + .mm_lq_tlb_multihit(mm_lq_tlb_multihit), + .mm_lq_tlb_par_err(mm_lq_tlb_par_err), + .mm_lq_lru_par_err(mm_lq_lru_par_err), + + // D$ snoop + .lsq_ctl_rv0_binv_val(lsq_ctl_rv0_back_inv), + + // tlbivax or tlbilx snoop + .mm_lq_snoop_coming(mm_lq_snoop_coming), + .mm_lq_snoop_val(mm_lq_snoop_val), + .mm_lq_snoop_attr(mm_lq_snoop_attr), + .mm_lq_snoop_vpn(mm_lq_snoop_vpn), + .lq_mm_snoop_ack(lq_mm_snoop_ack), + .derat_dec_rv1_snoop_addr(derat_dec_rv1_snoop_addr), + .derat_rv1_snoop_val(derat_rv1_snoop_val), + + // pipeline controls + .iu_lq_cp_flush(iu_lq_cp_flush), + .derat_dec_hole_all(derat_dec_hole_all), + + // cam _np1 ports + .derat_dcc_ex3_e(derat_dcc_ex3_wimge_e), + .derat_dcc_ex3_itagHit(derat_dcc_ex3_itagHit), + + // cam _np2 ports + .derat_dcc_ex4_rpn(derat_dcc_ex4_p_addr), + .derat_dcc_ex4_wimge(derat_dcc_ex4_wimge), + .derat_dcc_ex4_u(derat_dcc_ex4_usr_bits), + .derat_dcc_ex4_wlc(derat_dcc_ex4_wlc), + .derat_dcc_ex4_attr(), + .derat_dcc_ex4_vf(derat_dcc_ex4_vf), + .derat_dcc_ex4_miss(derat_dcc_ex4_miss), + .derat_dcc_ex4_tlb_err(derat_dcc_ex4_tlb_err), + .derat_dcc_ex4_dsi(derat_dcc_ex4_dsi), + .derat_dcc_ex4_par_err_det(derat_dcc_ex4_par_err_det), + .derat_dcc_ex4_par_err_flush(derat_dcc_ex4_par_err_flush), + .derat_dcc_ex4_multihit_err_det(derat_dcc_ex4_multihit_err_det), + .derat_dcc_ex4_multihit_err_flush(derat_dcc_ex4_multihit_err_flush), + .derat_dcc_ex4_noop_touch(derat_dcc_ex4_noop_touch), + .derat_dcc_ex4_tlb_inelig(derat_dcc_ex4_tlb_inelig), + .derat_dcc_ex4_pt_fault(derat_dcc_ex4_pt_fault), + .derat_dcc_ex4_lrat_miss(derat_dcc_ex4_lrat_miss), + .derat_dcc_ex4_tlb_multihit(derat_dcc_ex4_tlb_multihit), + .derat_dcc_ex4_tlb_par_err(derat_dcc_ex4_tlb_par_err), + .derat_dcc_ex4_lru_par_err(derat_dcc_ex4_lru_par_err), + + .derat_fir_par_err(derat_fir_par_err), + .derat_fir_multihit(derat_fir_multihit), + + // erat reload request to mmu + .lq_mm_req(lq_mm_req), + .lq_mm_req_nonspec(lq_mm_req_nonspec), + .lq_mm_req_itag(lq_mm_req_itag), + .lq_mm_req_epn(lq_mm_req_epn), + .lq_mm_thdid(lq_mm_thdid), + .lq_mm_req_emq(lq_mm_req_emq), + .lq_mm_ttype(lq_mm_ttype), + .lq_mm_state(lq_mm_state), + .lq_mm_lpid(lq_mm_lpid), + .lq_mm_tid(lq_mm_tid), + .lq_mm_perf_dtlb(lq_mm_perf_dtlb), + + // write interface to mmucr0,1 + .lq_mm_mmucr0_we(lq_mm_mmucr0_we), + .lq_mm_mmucr0(lq_mm_mmucr0), + .lq_mm_mmucr1_we(lq_mm_mmucr1_we), + .lq_mm_mmucr1(lq_mm_mmucr1), + + // spr's + .spr_xucr0_clkg_ctl_b1(xu_lq_spr_xucr0_clkg_ctl), + + .xu_lq_spr_msr_hv(xu_lq_spr_msr_gs), + .xu_lq_spr_msr_pr(xu_lq_spr_msr_pr), + .xu_lq_spr_msr_ds(xu_lq_spr_msr_ds), + .xu_lq_spr_msr_cm(xu_lq_spr_msr_cm), + .xu_lq_spr_ccr2_notlb(xu_lq_spr_ccr2_notlb), + .xu_lq_spr_ccr2_dfrat(xu_lq_spr_ccr2_dfrat), + .xu_lq_spr_ccr2_dfratsc(xu_lq_spr_ccr2_dfratsc), + .xu_lq_spr_xucr4_mmu_mchk(xu_lq_spr_xucr4_mmu_mchk), + + .spr_derat_eplc_wr(spr_derat_eplc_wr), + .spr_derat_eplc_epr(spr_derat_eplc_epr), + .spr_derat_eplc_eas(spr_derat_eplc_eas), + .spr_derat_eplc_egs(spr_derat_eplc_egs), + .spr_derat_eplc_elpid(spr_derat_eplc_elpid), + .spr_derat_eplc_epid(spr_derat_eplc_epid), + + .spr_derat_epsc_wr(spr_derat_epsc_wr), + .spr_derat_epsc_epr(spr_derat_epsc_epr), + .spr_derat_epsc_eas(spr_derat_epsc_eas), + .spr_derat_epsc_egs(spr_derat_epsc_egs), + .spr_derat_epsc_elpid(spr_derat_epsc_elpid), + .spr_derat_epsc_epid(spr_derat_epsc_epid), + + .mm_lq_pid(mm_lq_pid), + .mm_lq_mmucr0(mm_lq_mmucr0), + .mm_lq_mmucr1(mm_lq_mmucr1), + + // debug + .derat_xu_debug_group0(derat_xu_debug_group0), + .derat_xu_debug_group1(derat_xu_debug_group1), + .derat_xu_debug_group2(derat_xu_debug_group2), + .derat_xu_debug_group3(derat_xu_debug_group3) +); + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// PreFetch +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +assign ctl_pf_clear_queue = lsq_ctl_sync_done; + +generate + if (`BUILD_PFETCH == 1) + begin : pf + + // Order Queue Size + lq_pfetch pfetch( // number of IAR bits used by prefetch + + // IU interface to RV for pfetch predictor table0 + // port 0 + .rv_lq_rv1_i0_vld(rv_lq_rv1_i0_vld), + .rv_lq_rv1_i0_isLoad(rv_lq_rv1_i0_isLoad), + .rv_lq_rv1_i0_itag(rv_lq_rv1_i0_itag), + .rv_lq_rv1_i0_rte_lq(rv_lq_rv1_i0_rte_lq), + .rv_lq_rv1_i0_ifar(rv_lq_rv1_i0_ifar), + + // port 1 + .rv_lq_rv1_i1_vld(rv_lq_rv1_i1_vld), + .rv_lq_rv1_i1_isLoad(rv_lq_rv1_i1_isLoad), + .rv_lq_rv1_i1_itag(rv_lq_rv1_i1_itag), + .rv_lq_rv1_i1_rte_lq(rv_lq_rv1_i1_rte_lq), + .rv_lq_rv1_i1_ifar(rv_lq_rv1_i1_ifar), + + // Zap Machine + .iu_lq_cp_flush(iu_lq_cp_flush), + + .ctl_pf_clear_queue(ctl_pf_clear_queue), + + // release itag to pfetch + .odq_pf_report_tid(odq_pf_report_tid), + .odq_pf_report_itag(odq_pf_report_itag), + .odq_pf_resolved(odq_pf_resolved), + + // EA of load miss that is valid for pre-fetching + .dcc_pf_ex5_eff_addr(dcc_pf_ex5_eff_addr), + .dcc_pf_ex5_req_val_4pf(dcc_pf_ex5_req_val_4pf), + .dcc_pf_ex5_act(dcc_pf_ex5_act), + .dcc_pf_ex5_thrd_id(dcc_pf_ex5_thrd_id), + .dcc_pf_ex5_loadmiss(dcc_pf_ex5_loadmiss), + .dcc_pf_ex5_itag(dcc_pf_ex5_itag), + + .spr_pf_spr_dscr_lsd(spr_pf_spr_dscr_lsd), + .spr_pf_spr_dscr_snse(spr_pf_spr_dscr_snse), + .spr_pf_spr_dscr_sse(spr_pf_spr_dscr_sse), + .spr_pf_spr_dscr_dpfd(spr_pf_spr_dscr_dpfd), + .spr_pf_spr_pesr(spr_pf_spr_pesr), + + // EA of prefetch request + .pf_dec_req_addr(pf_dec_req_addr), + .pf_dec_req_thrd(pf_dec_req_thrd), + .pf_dec_req_val(pf_dec_req_val), + .dec_pf_ack(dec_pf_ack), + + .pf_empty(ctl_lsq_pf_empty), + + // EA of prefetch request + .pc_lq_inj_prefetcher_parity(pc_lq_inj_prefetcher_parity), + .lq_pc_err_prefetcher_parity(lq_pc_err_prefetcher_parity), + + // Pervasive + .vcs(vdd), + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .sg_0(sg_0), + .func_sl_thold_0_b(func_sl_thold_0_b), + .func_sl_force(func_sl_force), + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc[5]), + .clkoff_dc_b(clkoff_dc_b), + .mpw1_dc_b(mpw1_dc_b[5]), + .mpw2_dc_b(mpw2_dc_b), + .scan_in(spr_pf_func_scan), + .scan_out(func_scan_out_int[10]), + + // array pervasive + .abst_sl_thold_0(abst_sl_thold_0), + .ary_nsl_thold_0(ary_nsl_thold_0), + .time_sl_thold_0(time_sl_thold_0), + .repr_sl_thold_0(repr_sl_thold_0), + .g8t_clkoff_dc_b(g8t_clkoff_dc_b), + .pc_lq_ccflush_dc(pc_lq_ccflush_dc), + .an_ac_scan_dis_dc_b(an_ac_scan_dis_dc_b), + .an_ac_scan_diag_dc(an_ac_scan_diag_dc), + .g8t_d_mode_dc(g8t_d_mode_dc), + .g8t_mpw1_dc_b(g8t_mpw1_dc_b), + .g8t_mpw2_dc_b(g8t_mpw2_dc_b), + .g8t_delay_lclkr_dc(g8t_delay_lclkr_dc), + // ABIST + .pc_xu_abist_g8t_wenb_q(pc_lq_abist_g8t_wenb_q), + .pc_xu_abist_g8t1p_renb_0_q(pc_lq_abist_g8t1p_renb_0_q), + .pc_xu_abist_di_0_q(pc_lq_abist_di_0_q), + .pc_xu_abist_g8t_bw_1_q(pc_lq_abist_g8t_bw_1_q), + .pc_xu_abist_g8t_bw_0_q(pc_lq_abist_g8t_bw_0_q), + .pc_xu_abist_waddr_0_q(5'b00000), + .pc_xu_abist_raddr_0_q(5'b00000), + .an_ac_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc), + .pc_xu_abist_ena_dc(pc_lq_abist_ena_dc), + .pc_xu_abist_wl64_comp_ena_q(pc_lq_abist_wl64_comp_ena_q), + .pc_xu_abist_raw_dc_b(pc_lq_abist_raw_dc_b), + .pc_xu_abist_g8t_dcomp_q(pc_lq_abist_g8t_dcomp_q), + // Scan + .abst_scan_in({abst_scan_out_q[1], abst_scan_out_int[2]}), + .time_scan_in(time_scan_in_q[2]), + .repr_scan_in(repr_scan_in_q[1]), + .abst_scan_out({abst_scan_out_int[2], abst_scan_out_int[3]}), + .time_scan_out(time_scan_out_int[2]), + .repr_scan_out(repr_scan_out_int[1]), + // BOLT-ON + .bolt_sl_thold_0(bolt_sl_thold_0), + .pc_bo_enable_2(bo_enable_2), // general bolt-on enable + .pc_xu_bo_reset(pc_lq_bo_reset), // reset + .pc_xu_bo_unload(pc_lq_bo_unload), // unload sticky bits + .pc_xu_bo_repair(pc_lq_bo_repair), // execute sticky bit decode + .pc_xu_bo_shdata(pc_lq_bo_shdata), // shift data for timing write and diag loop + .pc_xu_bo_select(2'b00), // select for mask and hier writes + .xu_pc_bo_fail(), // fail/no-fix reg + .xu_pc_bo_diagout() + ); + end +endgenerate + +generate + if (`BUILD_PFETCH == 0) begin : nopf + assign pf_dec_req_addr = {(63 - `CL_SIZE-64 - (2 ** `GPR_WIDTH_ENC))+1{1'b0}}; + assign pf_dec_req_thrd = {`THREADS{1'b0}}; + assign pf_dec_req_val = 1'b0; + assign func_scan_out_int[10] = spr_pf_func_scan; + assign abst_scan_out_int[2] = abst_scan_out_q[1]; + assign abst_scan_out_int[3] = abst_scan_out_int[2]; + assign time_scan_out_int[2] = time_scan_in_q[2]; + assign repr_scan_out_int[1] = repr_scan_in_q[1]; + end +endgenerate + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// OUTPUTS +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +assign ctl_dat_ex2_eff_addr = dir_dcc_ex2_eff_addr[52:59]; +assign dir_arr_wr_enable = dir_arr_wr_enable_int; +assign dir_arr_wr_way = dir_arr_wr_way_int; +assign dir_arr_wr_addr = dir_arr_wr_addr_int; +assign dir_arr_wr_data = dir_arr_wr_data_int; +assign ctl_spr_dbcr2_dvc1be = spr_dbcr2_dvc1be; +assign ctl_spr_dbcr2_dvc2be = spr_dbcr2_dvc2be; +assign ctl_spr_dbcr2_dvc1m = spr_dbcr2_dvc1m; +assign ctl_spr_dbcr2_dvc2m = spr_dbcr2_dvc2m; +assign ctl_spr_dvc1_dbg = spr_dvc1_dbg; +assign ctl_spr_dvc2_dbg = spr_dvc2_dbg; +assign spr_lesr1 = {spr_lesr1_muxseleb0, spr_lesr1_muxseleb1, spr_lesr1_muxseleb2, spr_lesr1_muxseleb3}; +assign spr_lesr2 = {spr_lesr2_muxseleb4, spr_lesr2_muxseleb5, spr_lesr2_muxseleb6, spr_lesr2_muxseleb7}; + +assign spr_dcc_spr_lesr = {spr_lesr1, spr_lesr2}; +assign ctl_perv_spr_lesr1 = spr_lesr1; +assign ctl_perv_spr_lesr2 = spr_lesr2; + +// SCAN OUT Gate +assign abst_scan_out = abst_scan_out_q[2] & an_ac_scan_dis_dc_b; +assign time_scan_out = time_scan_out_q & an_ac_scan_dis_dc_b; +assign repr_scan_out = repr_scan_out_q & an_ac_scan_dis_dc_b; +assign func_scan_out = func_scan_out_q & {11{an_ac_scan_dis_dc_b}}; +assign regf_scan_out = regf_scan_out_q & {7{an_ac_scan_dis_dc_b}}; +assign ccfg_scan_out = ccfg_scan_out_int & an_ac_scan_dis_dc_b; + +//--------------------------------------------------------------------- +// abist latches +//--------------------------------------------------------------------- + +tri_rlmreg_p #(.INIT(0), .WIDTH(25), .NEEDS_SRESET(1)) abist_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pc_lq_abist_ena_dc), + .thold_b(abst_sl_thold_0_b), + .sg(sg_0), + .force_t(abst_sl_force), + .delay_lclkr(delay_lclkr_dc[5]), + .mpw1_b(mpw1_dc_b[5]), + .mpw2_b(mpw2_dc_b), + .d_mode(d_mode_dc), + .scin(abist_siv[0:24]), + .scout(abist_sov[0:24]), + .din({pc_lq_abist_wl64_comp_ena, + pc_lq_abist_g8t_wenb, + pc_lq_abist_g8t1p_renb_0, + pc_lq_abist_di_0, + pc_lq_abist_g8t_dcomp, + pc_lq_abist_g8t_bw_1, + pc_lq_abist_g8t_bw_0, + pc_lq_abist_raddr_0, + pc_lq_abist_waddr_0}), + .dout({pc_lq_abist_wl64_comp_ena_q, + pc_lq_abist_g8t_wenb_q, + pc_lq_abist_g8t1p_renb_0_q, + pc_lq_abist_di_0_q, + pc_lq_abist_g8t_dcomp_q, + pc_lq_abist_g8t_bw_1_q, + pc_lq_abist_g8t_bw_0_q, + pc_lq_abist_raddr_0_q, + pc_lq_abist_waddr_0_q}) +); + +//----------------------------------------------- +// Pervasive +//----------------------------------------------- + +tri_plat #(.WIDTH(15)) perv_2to1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(pc_lq_ccflush_dc), + .din({func_nsl_thold_2, + func_sl_thold_2, + func_slp_sl_thold_2, + func_slp_nsl_thold_2, + regf_slp_sl_thold_2, + ary_nsl_thold_2, + ary_slp_nsl_thold_2, + abst_sl_thold_2, + abst_slp_sl_thold_2, + time_sl_thold_2, + repr_sl_thold_2, + bolt_sl_thold_2, + sg_2, + fce_2, + cfg_sl_thold_2}), + .q({func_nsl_thold_1, + func_sl_thold_1, + func_slp_sl_thold_1, + func_slp_nsl_thold_1, + regf_slp_sl_thold_1, + ary_nsl_thold_1, + ary_slp_nsl_thold_1, + abst_sl_thold_1, + abst_slp_sl_thold_1, + time_sl_thold_1, + repr_sl_thold_1, + bolt_sl_thold_1, + sg_1, + fce_1, + cfg_sl_thold_1}) +); + +tri_plat #(.WIDTH(15)) perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(pc_lq_ccflush_dc), + .din({func_nsl_thold_1, + func_sl_thold_1, + func_slp_sl_thold_1, + func_slp_nsl_thold_1, + regf_slp_sl_thold_1, + ary_nsl_thold_1, + ary_slp_nsl_thold_1, + abst_sl_thold_1, + abst_slp_sl_thold_1, + time_sl_thold_1, + repr_sl_thold_1, + bolt_sl_thold_1, + sg_1, + fce_1, + cfg_sl_thold_1}), + .q({func_nsl_thold_0, + func_sl_thold_0, + func_slp_sl_thold_0, + func_slp_nsl_thold_0, + regf_slp_sl_thold_0, + ary_nsl_thold_0, + ary_slp_nsl_thold_0, + abst_sl_thold_0, + abst_slp_sl_thold_0, + time_sl_thold_0, + repr_sl_thold_0, + bolt_sl_thold_0, + sg_0, + fce_0, + cfg_sl_thold_0}) +); + + +tri_lcbor perv_lcbor_func_sl( + .clkoff_b(clkoff_dc_b), + .thold(func_sl_thold_0), + .sg(sg_0), + .act_dis(tidn), + .force_t(func_sl_force), + .thold_b(func_sl_thold_0_b) +); + + +tri_lcbor perv_lcbor_func_slp_sl( + .clkoff_b(clkoff_dc_b), + .thold(func_slp_sl_thold_0), + .sg(sg_0), + .act_dis(tidn), + .force_t(func_slp_sl_force), + .thold_b(func_slp_sl_thold_0_b) +); + + +tri_lcbor perv_lcbor_func_nsl( + .clkoff_b(clkoff_dc_b), + .thold(func_nsl_thold_0), + .sg(fce_0), + .act_dis(tidn), + .force_t(func_nsl_force), + .thold_b(func_nsl_thold_0_b) +); + + +tri_lcbor perv_lcbor_func_slp_nsl( + .clkoff_b(clkoff_dc_b), + .thold(func_slp_nsl_thold_0), + .sg(fce_0), + .act_dis(tidn), + .force_t(func_slp_nsl_force), + .thold_b(func_slp_nsl_thold_0_b) +); + + +tri_lcbor perv_lcbor_abst_sl( + .clkoff_b(clkoff_dc_b), + .thold(abst_sl_thold_0), + .sg(sg_0), + .act_dis(tidn), + .force_t(abst_sl_force), + .thold_b(abst_sl_thold_0_b) +); + + +tri_lcbor perv_lcbor_cfg_sl( + .clkoff_b(clkoff_dc_b), + .thold(cfg_sl_thold_0), + .sg(sg_0), + .act_dis(tidn), + .force_t(cfg_sl_force), + .thold_b(cfg_sl_thold_0_b) +); + +// LCBs for scan only staging latches +assign slat_force = sg_0; +assign abst_slat_thold_b = (~abst_sl_thold_0); +assign time_slat_thold_b = (~time_sl_thold_0); +assign repr_slat_thold_b = (~repr_sl_thold_0); +assign func_slat_thold_b = (~func_sl_thold_0); +assign regf_slat_thold_b = (~regf_slp_sl_thold_0); + + +tri_lcbs perv_lcbs_abst( + .vd(vdd), + .gd(gnd), + .delay_lclkr(delay_lclkr_dc[5]), + .nclk(nclk), + .force_t(slat_force), + .thold_b(abst_slat_thold_b), + .dclk(abst_slat_d2clk), + .lclk(abst_slat_lclk) +); + +tri_slat_scan #(.WIDTH(4), .INIT(4'b0000)) perv_abst_stg( + .vd(vdd), + .gd(gnd), + .dclk(abst_slat_d2clk), + .lclk(abst_slat_lclk), + .scan_in({abst_scan_in, + abst_scan_out_int[0], + abst_scan_out_int[1], + abst_scan_out_int[3]}), + .scan_out({abst_scan_in_q, + abst_scan_out_q[0], + abst_scan_out_q[1], + abst_scan_out_q[2]}), + .q(abst_scan_q), + .q_b(abst_scan_q_b) +); + +tri_lcbs perv_lcbs_time( + .vd(vdd), + .gd(gnd), + .delay_lclkr(delay_lclkr_dc[5]), + .nclk(nclk), + .force_t(slat_force), + .thold_b(time_slat_thold_b), + .dclk(time_slat_d2clk), + .lclk(time_slat_lclk) +); + + +tri_slat_scan #(.WIDTH(4), .INIT(4'b0000)) perv_time_stg( + .vd(vdd), + .gd(gnd), + .dclk(time_slat_d2clk), + .lclk(time_slat_lclk), + .scan_in({time_scan_in, + time_scan_out_int[0], + time_scan_out_int[1], + time_scan_out_int[2]}), + .scan_out({time_scan_in_q[0], + time_scan_in_q[1], + time_scan_in_q[2], + time_scan_out_q}), + .q(time_scan_q), + .q_b(time_scan_q_b) +); + +tri_lcbs perv_lcbs_repr( + .vd(vdd), + .gd(gnd), + .delay_lclkr(delay_lclkr_dc[5]), + .nclk(nclk), + .force_t(slat_force), + .thold_b(repr_slat_thold_b), + .dclk(repr_slat_d2clk), + .lclk(repr_slat_lclk) +); + + +tri_slat_scan #(.WIDTH(3), .INIT(3'b000)) perv_repr_stg( + .vd(vdd), + .gd(gnd), + .dclk(repr_slat_d2clk), + .lclk(repr_slat_lclk), + .scan_in({repr_scan_in, + repr_scan_out_int[0], + repr_scan_out_int[1]}), + .scan_out({repr_scan_in_q[0], + repr_scan_in_q[1], + repr_scan_out_q}), + .q(repr_scan_q), + .q_b(repr_scan_q_b) +); + +tri_lcbs perv_lcbs_func( + .vd(vdd), + .gd(gnd), + .delay_lclkr(delay_lclkr_dc[5]), + .nclk(nclk), + .force_t(slat_force), + .thold_b(func_slat_thold_b), + .dclk(func_slat_d2clk), + .lclk(func_slat_lclk) +); + +tri_slat_scan #(.WIDTH(22), .INIT(22'b0000000000000000000000)) perv_func_stg( + .vd(vdd), + .gd(gnd), + .dclk(func_slat_d2clk), + .lclk(func_slat_lclk), + .scan_in({func_scan_in[0], + func_scan_in[1], + func_scan_in[2], + func_scan_in[3], + func_scan_in[4], + func_scan_in[5], + func_scan_in[6], + func_scan_in[7], + func_scan_in[8], + func_scan_in[9], + func_scan_in[10], + func_scan_out_int[0], + func_scan_out_int[1], + func_scan_out_int[2], + func_scan_out_int[3], + func_scan_out_int[4], + func_scan_out_int[5], + func_scan_out_int[6], + func_scan_out_int[7], + func_scan_out_int[8], + func_scan_out_int[9], + func_scan_out_int[10]}), + .scan_out({func_scan_in_q[0], + func_scan_in_q[1], + func_scan_in_q[2], + func_scan_in_q[3], + func_scan_in_q[4], + func_scan_in_q[5], + func_scan_in_q[6], + func_scan_in_q[7], + func_scan_in_q[8], + func_scan_in_q[9], + func_scan_in_q[10], + func_scan_out_q[0], + func_scan_out_q[1], + func_scan_out_q[2], + func_scan_out_q[3], + func_scan_out_q[4], + func_scan_out_q[5], + func_scan_out_q[6], + func_scan_out_q[7], + func_scan_out_q[8], + func_scan_out_q[9], + func_scan_out_q[10]}), + .q(func_scan_q), + .q_b(func_scan_q_b) +); + +tri_lcbs perv_lcbs_regf( + .vd(vdd), + .gd(gnd), + .delay_lclkr(delay_lclkr_dc[5]), + .nclk(nclk), + .force_t(slat_force), + .thold_b(regf_slat_thold_b), + .dclk(regf_slat_d2clk), + .lclk(regf_slat_lclk) +); + + +tri_slat_scan #(.WIDTH(14), .INIT(14'b00000000000000)) perv_regf_stg( + .vd(vdd), + .gd(gnd), + .dclk(regf_slat_d2clk), + .lclk(regf_slat_lclk), + .scan_in({regf_scan_out_int, regf_scan_in}), + .scan_out({regf_scan_out_q, regf_scan_in_q}), + .q(regf_scan_q), + .q_b(regf_scan_q_b) +); + +assign abist_siv = {abist_sov[1:24], abst_scan_out_q[0]}; +assign abst_scan_out_int[1] = abist_sov[0]; + +endmodule diff --git a/dev/verilog/work/lq_data.v b/dev/verilog/work/lq_data.v new file mode 100755 index 0000000..ad91d56 --- /dev/null +++ b/dev/verilog/work/lq_data.v @@ -0,0 +1,1164 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +// Description: XU LSU Data Rotator +// +//***************************************************************************** + +// ########################################################################################## +// VHDL Contents +// 1) 16 Byte Reload Rotator +// 2) 16 Byte Unaligned Rotator +// 3) Little Endian Support for 2,4,8,16 Byte Operations +// 4) Execution Pipe Store data rotation +// 5) Byte Enable Generation +// ########################################################################################## + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" + +module lq_data( + ctl_dat_ex1_data_act, + ctl_dat_ex2_eff_addr, + ctl_dat_ex3_opsize, + ctl_dat_ex3_le_ld_rotsel, + ctl_dat_ex3_be_ld_rotsel, + ctl_dat_ex3_algebraic, + ctl_dat_ex3_le_alg_rotsel, + ctl_dat_ex3_le_mode, + ctl_dat_ex4_way_hit, + xu_lq_spr_xucr0_dcdis, + lsq_dat_stq1_stg_act, + lsq_dat_stq1_val, + lsq_dat_stq1_mftgpr_val, + lsq_dat_stq1_store_val, + lsq_dat_stq1_byte_en, + lsq_dat_stq1_op_size, + lsq_dat_stq1_le_mode, + lsq_dat_stq1_addr, + lsq_dat_stq2_blk_req, + lsq_dat_stq2_store_data, + lsq_dat_rel1_data_val, + lsq_dat_rel1_qw, + stq4_dcarr_wren, + stq4_dcarr_way_en, + ctl_dat_stq5_way_perr_inval, + dat_ctl_dcarr_perr_way, + dat_ctl_ex5_load_data, + dat_ctl_stq6_axu_data, + dat_lsq_stq4_128data, + pc_lq_inj_dcache_parity, + vdd, + gnd, + vcs, + nclk, + pc_lq_ccflush_dc, + sg_2, + fce_2, + func_sl_thold_2, + func_nsl_thold_2, + clkoff_dc_b, + d_mode_dc, + delay_lclkr_dc, + mpw1_dc_b, + mpw2_dc_b, + g8t_clkoff_dc_b, + g8t_d_mode_dc, + g8t_delay_lclkr_dc, + g8t_mpw1_dc_b, + g8t_mpw2_dc_b, + abst_sl_thold_2, + time_sl_thold_2, + ary_nsl_thold_2, + repr_sl_thold_2, + bolt_sl_thold_2, + bo_enable_2, + an_ac_scan_dis_dc_b, + an_ac_scan_diag_dc, + an_ac_lbist_ary_wrt_thru_dc, + pc_lq_abist_ena_dc, + pc_lq_abist_raw_dc_b, + pc_lq_bo_unload, + pc_lq_bo_repair, + pc_lq_bo_reset, + pc_lq_bo_shdata, + pc_lq_bo_select, + lq_pc_bo_fail, + lq_pc_bo_diagout, + pc_lq_abist_wl256_comp_ena, + pc_lq_abist_g8t_wenb, + pc_lq_abist_g8t1p_renb_0, + pc_lq_abist_g8t_dcomp, + pc_lq_abist_g8t_bw_1, + pc_lq_abist_g8t_bw_0, + pc_lq_abist_di_0, + pc_lq_abist_waddr_0, + pc_lq_abist_raddr_0, + abst_scan_in, + time_scan_in, + repr_scan_in, + func_scan_in, + abst_scan_out, + time_scan_out, + repr_scan_out, + func_scan_out +); + +//------------------------------------------------------------------- +// Generics +//------------------------------------------------------------------- +//parameter EXPAND_TYPE = 2; // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) +//parameter GPR_WIDTH_ENC = 6; // Register Mode 5 = 32bit, 6 = 64bit +//parameter DC_SIZE = 15; // 2^15 = 32768 Bytes L1 D$ + +// Execution Pipe +input ctl_dat_ex1_data_act; +input [52:59] ctl_dat_ex2_eff_addr; +input [0:4] ctl_dat_ex3_opsize; +input [0:3] ctl_dat_ex3_le_ld_rotsel; +input [0:3] ctl_dat_ex3_be_ld_rotsel; +input ctl_dat_ex3_algebraic; +input [0:3] ctl_dat_ex3_le_alg_rotsel; +input ctl_dat_ex3_le_mode; +input [0:7] ctl_dat_ex4_way_hit; // Way Hit + +// Config Bits +input xu_lq_spr_xucr0_dcdis; + +// RELOAD/STORE PIPE +input lsq_dat_stq1_stg_act; +input lsq_dat_stq1_val; +input lsq_dat_stq1_mftgpr_val; +input lsq_dat_stq1_store_val; +input [0:15] lsq_dat_stq1_byte_en; +input [0:2] lsq_dat_stq1_op_size; +input lsq_dat_stq1_le_mode; +input [52:63] lsq_dat_stq1_addr; +input lsq_dat_stq2_blk_req; +input [0:143] lsq_dat_stq2_store_data; +input lsq_dat_rel1_data_val; +input [57:59] lsq_dat_rel1_qw; + +// L1 D$ update Enable +input stq4_dcarr_wren; +input [0:7] stq4_dcarr_way_en; +input [0:7] ctl_dat_stq5_way_perr_inval; + +// Execution/Store Commit Pipe Outputs +output [0:7] dat_ctl_dcarr_perr_way; // Load Data Way Parity Error + +//Rotated Data +output [(128-`STQ_DATA_SIZE):127] dat_ctl_ex5_load_data; +output [(128-`STQ_DATA_SIZE):127] dat_ctl_stq6_axu_data; + +// Debug Data Compare +output [0:127] dat_lsq_stq4_128data; + +// Error Inject +input pc_lq_inj_dcache_parity; + +//pervasive +inout vcs; +inout vdd; +inout gnd; +(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) +input [0:`NCLK_WIDTH-1] nclk; +input pc_lq_ccflush_dc; +input sg_2; +input fce_2; +input func_sl_thold_2; +input func_nsl_thold_2; +input clkoff_dc_b; +input d_mode_dc; +input delay_lclkr_dc; +input mpw1_dc_b; +input mpw2_dc_b; +input g8t_clkoff_dc_b; +input g8t_d_mode_dc; +input [0:4] g8t_delay_lclkr_dc; +input [0:4] g8t_mpw1_dc_b; +input g8t_mpw2_dc_b; +input abst_sl_thold_2; +input time_sl_thold_2; +input ary_nsl_thold_2; +input repr_sl_thold_2; +input bolt_sl_thold_2; +input bo_enable_2; +input an_ac_scan_dis_dc_b; +input an_ac_scan_diag_dc; +input an_ac_lbist_ary_wrt_thru_dc; +input pc_lq_abist_ena_dc; +input pc_lq_abist_raw_dc_b; +input pc_lq_bo_unload; +input pc_lq_bo_repair; +input pc_lq_bo_reset; +input pc_lq_bo_shdata; +input [0:3] pc_lq_bo_select; +output [0:3] lq_pc_bo_fail; +output [0:3] lq_pc_bo_diagout; + +// G8T ABIST Control +input pc_lq_abist_wl256_comp_ena; +input pc_lq_abist_g8t_wenb; +input pc_lq_abist_g8t1p_renb_0; +input [0:3] pc_lq_abist_g8t_dcomp; +input pc_lq_abist_g8t_bw_1; +input pc_lq_abist_g8t_bw_0; +input [0:3] pc_lq_abist_di_0; +input [2:9] pc_lq_abist_waddr_0; +input [1:8] pc_lq_abist_raddr_0; + +// SCAN Ports +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) +input [0:3] abst_scan_in; +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) +input time_scan_in; +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) +input repr_scan_in; +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) +input [0:6] func_scan_in; +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) +output [0:3] abst_scan_out; +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) +output time_scan_out; +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) +output repr_scan_out; +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) +output [0:6] func_scan_out; + +//-------------------------- +// constants +//-------------------------- +parameter inj_dcache_parity_offset = 0; +parameter spr_xucr0_dcdis_offset = inj_dcache_parity_offset + 1; +parameter stq6_rot_data_offset = spr_xucr0_dcdis_offset + 1; +parameter ex2_stg_act_offset = stq6_rot_data_offset + `STQ_DATA_SIZE; +parameter ex3_stg_act_offset = ex2_stg_act_offset + 1; +parameter ex4_stg_act_offset = ex3_stg_act_offset + 1; +parameter stq2_stg_act_offset = ex4_stg_act_offset + 1; +parameter stq3_stg_act_offset = stq2_stg_act_offset + 1; +parameter stq4_stg_act_offset = stq3_stg_act_offset + 1; +parameter stq5_stg_act_offset = stq4_stg_act_offset + 1; +parameter stq5_rot_data_reg_offset = stq5_stg_act_offset + 1; +parameter scan_right = stq5_rot_data_reg_offset + `STQ_DATA_SIZE - 1; + +//-------------------------- +// signals +//-------------------------- +wire [(128-`STQ_DATA_SIZE):127] ex5_ld_hit_data; +wire spr_xucr0_dcdis_d; +wire spr_xucr0_dcdis_q; +wire [0:143] stq6_rd_data_wa; +wire [0:143] stq6_rd_data_wb; +wire [0:143] stq6_rd_data_wc; +wire [0:143] stq6_rd_data_wd; +wire [0:143] stq6_rd_data_we; +wire [0:143] stq6_rd_data_wf; +wire [0:143] stq6_rd_data_wg; +wire [0:143] stq6_rd_data_wh; +wire [0:3] stq7_byp_val_wabcd; +wire [0:3] stq7_byp_val_wefgh; +wire [0:143] stq7_byp_data_wabcd; +wire [0:143] stq7_byp_data_wefgh; +wire [0:143] stq8_byp_data_wabcd; +wire [0:143] stq8_byp_data_wefgh; +wire [0:3] stq_byp_val_wabcd; +wire [0:3] stq_byp_val_wefgh; +wire [(128-`STQ_DATA_SIZE):127] stq4_rot_data; +wire [(128-`STQ_DATA_SIZE):127] stq5_rot_data_d; +wire [(128-`STQ_DATA_SIZE):127] stq5_rot_data_q; +wire [(128-`STQ_DATA_SIZE):127] stq6_rot_data_d; +wire [(128-`STQ_DATA_SIZE):127] stq6_rot_data_q; +wire [52:59] dcarr_rd_addr; +wire [0:1151] dcarr_rd_data; +wire [0:7] dcarr_wr_way; +wire [52:59] dcarr_wr_addr; +wire [0:143] dcarr_wr_data_wabcd; +wire [0:143] dcarr_wr_data_wefgh; +wire inj_dcache_parity_d; +wire inj_dcache_parity_q; +wire [0:7] dcarr_data_perr_way; + +wire [0:7] dcarr_rd_stg_act; +wire [0:7] dcarr_wr_stg_act; +wire ex2_stg_act_d; +wire ex2_stg_act_q; +wire ex3_stg_act_d; +wire ex3_stg_act_q; +wire ex4_stg_act_d; +wire ex4_stg_act_q; +wire stq1_stg_act; +wire stq2_stg_act_d; +wire stq2_stg_act_q; +wire stq3_stg_act_d; +wire stq3_stg_act_q; +wire stq4_stg_act_d; +wire stq4_stg_act_q; +wire stq5_stg_act_d; +wire stq5_stg_act_q; +wire [0:3] abst_scan_in_q; +wire [0:3] abst_scan_out_int; +wire [0:3] abst_scan_out_q; +wire time_scan_in_q; +wire time_scan_out_int; +wire time_scan_out_q; +wire repr_scan_in_q; +wire repr_scan_out_int; +wire repr_scan_out_q; +wire [0:6] func_scan_in_q; +wire [0:6] func_scan_out_int; +wire [0:6] func_scan_out_q; +wire tiup; +wire tidn; +wire func_nsl_thold_1; +wire func_sl_thold_1; +wire sg_1; +wire fce_1; +wire func_nsl_thold_0; +wire func_sl_thold_0; +wire sg_0; +wire fce_0; +wire func_sl_force; +wire func_sl_thold_0_b; +wire func_nsl_force; +wire func_nsl_thold_0_b; +wire [0:scan_right] siv; +wire [0:scan_right] sov; +wire [0:29] abist_siv; +wire [0:29] abist_sov; +wire abst_sl_thold_1; +wire time_sl_thold_1; +wire ary_nsl_thold_1; +wire repr_sl_thold_1; +wire bolt_sl_thold_1; +wire abst_sl_thold_0; +wire time_sl_thold_0; +wire ary_nsl_thold_0; +wire repr_sl_thold_0; +wire bolt_sl_thold_0; +wire abst_sl_thold_0_b; +wire abst_sl_force; +wire pc_lq_abist_g8t_bw_0_q; +wire pc_lq_abist_g8t_bw_1_q; +wire [0:3] pc_lq_abist_di_0_q; +wire pc_lq_abist_wl256_comp_ena_q; +wire [0:3] pc_lq_abist_g8t_dcomp_q; +wire [2:9] pc_lq_abist_waddr_0_q; +wire [1:8] pc_lq_abist_raddr_0_q; +wire pc_lq_abist_g8t_wenb_q; +wire pc_lq_abist_g8t1p_renb_0_q; +wire slat_force; +wire abst_slat_thold_b; +wire abst_slat_d2clk; +wire [0:`NCLK_WIDTH-1] abst_slat_lclk; +wire time_slat_thold_b; +wire time_slat_d2clk; +wire [0:`NCLK_WIDTH-1] time_slat_lclk; +wire repr_slat_thold_b; +wire repr_slat_d2clk; +wire [0:`NCLK_WIDTH-1] repr_slat_lclk; +wire func_slat_thold_b; +wire func_slat_d2clk; +wire [0:`NCLK_WIDTH-1] func_slat_lclk; +wire [0:7] abst_scan_q; +wire [0:7] abst_scan_q_b; +wire [0:1] time_scan_q; +wire [0:1] time_scan_q_b; +wire [0:1] repr_scan_q; +wire [0:1] repr_scan_q_b; +wire [0:13] func_scan_q; +wire [0:13] func_scan_q_b; +wire [1:4] dat_scan_out_int; + +(* analysis_not_referenced="true" *) +wire unused; + +assign tiup = 1'b1; +assign tidn = 1'b0; +assign unused = |abst_scan_q | |abst_scan_q_b | |time_scan_q | |time_scan_q_b | + |repr_scan_q | |repr_scan_q_b | |func_scan_q | |func_scan_q_b; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// ACT's +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +assign ex2_stg_act_d = ctl_dat_ex1_data_act; +assign ex3_stg_act_d = ex2_stg_act_q; +assign ex4_stg_act_d = ex3_stg_act_q; + +assign stq1_stg_act = lsq_dat_stq1_stg_act; +assign stq2_stg_act_d = stq1_stg_act; +assign stq3_stg_act_d = stq2_stg_act_q & ~lsq_dat_stq2_blk_req; +assign stq4_stg_act_d = stq3_stg_act_q; +assign stq5_stg_act_d = stq4_stg_act_q; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Inputs +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +assign spr_xucr0_dcdis_d = xu_lq_spr_xucr0_dcdis; +assign inj_dcache_parity_d = pc_lq_inj_dcache_parity; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Reload/Store Data Rotator +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +lq_data_st l1dcst( + + // Load Address + .ex2_stg_act(ex2_stg_act_q), + .ctl_dat_ex2_eff_addr(ctl_dat_ex2_eff_addr), + + // SPR + .spr_xucr0_dcdis(spr_xucr0_dcdis_q), + + //Store/Reload path + .lsq_dat_stq1_stg_act(lsq_dat_stq1_stg_act), + .lsq_dat_stq1_val(lsq_dat_stq1_val), + .lsq_dat_stq1_mftgpr_val(lsq_dat_stq1_mftgpr_val), + .lsq_dat_stq1_store_val(lsq_dat_stq1_store_val), + .lsq_dat_stq1_byte_en(lsq_dat_stq1_byte_en), + .lsq_dat_stq1_op_size(lsq_dat_stq1_op_size), + .lsq_dat_stq1_le_mode(lsq_dat_stq1_le_mode), + .lsq_dat_stq1_addr(lsq_dat_stq1_addr), + .lsq_dat_stq2_blk_req(lsq_dat_stq2_blk_req), + .lsq_dat_rel1_data_val(lsq_dat_rel1_data_val), + .lsq_dat_rel1_qw(lsq_dat_rel1_qw), + .lsq_dat_stq2_store_data(lsq_dat_stq2_store_data), + + // Read-Modify-Write Path Read data + .stq6_rd_data_wa(stq6_rd_data_wa), + .stq6_rd_data_wb(stq6_rd_data_wb), + .stq6_rd_data_wc(stq6_rd_data_wc), + .stq6_rd_data_wd(stq6_rd_data_wd), + .stq6_rd_data_we(stq6_rd_data_we), + .stq6_rd_data_wf(stq6_rd_data_wf), + .stq6_rd_data_wg(stq6_rd_data_wg), + .stq6_rd_data_wh(stq6_rd_data_wh), + + // Rotated Data + .stq4_rot_data(stq4_rot_data), + + // L2 Store Data + .dat_lsq_stq4_128data(dat_lsq_stq4_128data), + + // EX4 Load Bypass Data for Read/Write Collision detected in EX2 + .stq7_byp_val_wabcd(stq7_byp_val_wabcd), + .stq7_byp_val_wefgh(stq7_byp_val_wefgh), + .stq7_byp_data_wabcd(stq7_byp_data_wabcd), + .stq7_byp_data_wefgh(stq7_byp_data_wefgh), + .stq8_byp_data_wabcd(stq8_byp_data_wabcd), + .stq8_byp_data_wefgh(stq8_byp_data_wefgh), + .stq_byp_val_wabcd(stq_byp_val_wabcd), + .stq_byp_val_wefgh(stq_byp_val_wefgh), + + // D$ Array Write Control + .stq4_dcarr_wren(stq4_dcarr_wren), + .stq4_dcarr_way_en(stq4_dcarr_way_en), + .ctl_dat_stq5_way_perr_inval(ctl_dat_stq5_way_perr_inval), + + // D$ Array + .dcarr_rd_stg_act(dcarr_rd_stg_act), + .dcarr_rd_addr(dcarr_rd_addr), + .dcarr_wr_stg_act(dcarr_wr_stg_act), + .dcarr_wr_way(dcarr_wr_way), + .dcarr_wr_addr(dcarr_wr_addr), + .dcarr_wr_data_wabcd(dcarr_wr_data_wabcd), + .dcarr_wr_data_wefgh(dcarr_wr_data_wefgh), + + // Pervasive + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .sg_0(sg_0), + .func_sl_thold_0_b(func_sl_thold_0_b), + .func_sl_force(func_sl_force), + .func_nsl_thold_0_b(func_nsl_thold_0_b), + .func_nsl_force(func_nsl_force), + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .scan_in(func_scan_in_q[6]), + .scan_out(func_scan_out_int[6]) +); + +assign stq5_rot_data_d = stq4_rot_data; +assign stq6_rot_data_d = stq5_rot_data_q; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// L1 D-Cache Array +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +generate if ((2 ** `DC_SIZE) == 32768) begin : dc32K + // number of addressable register in this array + // width of the bus to address all ports (2^addressbus_width >= addressable_ports) + // bitwidth of ports (per way) + // gives the number of bits that shares one write-enable; must divide evenly into array + // number of ways + tri_256x144_8w_1r1w #(.addressable_ports(256), .addressbus_width(8), .port_bitwidth(144), .bit_write_type(9), .ways(8)) tridcarr( + // POWER PINS + .vcs(vcs), + .vdd(vdd), + .gnd(gnd), + + // CLOCK AND CLOCKCONTROL PORTS + .nclk(nclk), + .wr_act(dcarr_wr_stg_act), + .rd_act(dcarr_rd_stg_act), + .sg_0(sg_0), + .ary_nsl_thold_0(ary_nsl_thold_0), + .abst_sl_thold_0(abst_sl_thold_0), + .time_sl_thold_0(time_sl_thold_0), + .repr_sl_thold_0(repr_sl_thold_0), + .func_sl_force(func_sl_force), + .func_sl_thold_0_b(func_sl_thold_0_b), + .g8t_clkoff_dc_b(g8t_clkoff_dc_b), + .ccflush_dc(pc_lq_ccflush_dc), + .scan_dis_dc_b(an_ac_scan_dis_dc_b), + .scan_diag_dc(an_ac_scan_diag_dc), + .g8t_d_mode_dc(g8t_d_mode_dc), + .g8t_mpw1_dc_b(g8t_mpw1_dc_b), + .g8t_mpw2_dc_b(g8t_mpw2_dc_b), + .g8t_delay_lclkr_dc(g8t_delay_lclkr_dc), + .d_mode_dc(d_mode_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .delay_lclkr_dc(delay_lclkr_dc), + + // ABIST + .wr_abst_act(pc_lq_abist_g8t_wenb_q), + .rd0_abst_act(pc_lq_abist_g8t1p_renb_0_q), + .abist_di(pc_lq_abist_di_0_q), + .abist_bw_odd(pc_lq_abist_g8t_bw_1_q), + .abist_bw_even(pc_lq_abist_g8t_bw_0_q), + .abist_wr_adr(pc_lq_abist_waddr_0_q), + .abist_rd0_adr(pc_lq_abist_raddr_0_q), + .tc_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc), + .abist_ena_1(pc_lq_abist_ena_dc), + .abist_g8t_rd0_comp_ena(pc_lq_abist_wl256_comp_ena_q), + .abist_raw_dc_b(pc_lq_abist_raw_dc_b), + .obs0_abist_cmp(pc_lq_abist_g8t_dcomp_q), + + // SCAN PORTS + .abst_scan_in({abist_siv[0], abst_scan_in_q[1], abst_scan_in_q[2], abst_scan_in_q[3]}), + .time_scan_in(time_scan_in_q), + .repr_scan_in(repr_scan_in_q), + .func_scan_in(func_scan_in_q[1:4]), + .abst_scan_out({abist_sov[0], abst_scan_out_int[1], abst_scan_out_int[2], abst_scan_out_int[3]}), + .time_scan_out(time_scan_out_int), + .repr_scan_out(repr_scan_out_int), + .func_scan_out(dat_scan_out_int[1:4]), + + // BOLT-ON + .lcb_bolt_sl_thold_0(bolt_sl_thold_0), + .pc_bo_enable_2(bo_enable_2), + .pc_bo_reset(pc_lq_bo_reset), + .pc_bo_unload(pc_lq_bo_unload), + .pc_bo_repair(pc_lq_bo_repair), + .pc_bo_shdata(pc_lq_bo_shdata), + .pc_bo_select(pc_lq_bo_select), + .bo_pc_failout(lq_pc_bo_fail), + .bo_pc_diagloop(lq_pc_bo_diagout), + .tri_lcb_mpw1_dc_b(mpw1_dc_b), + .tri_lcb_mpw2_dc_b(mpw2_dc_b), + .tri_lcb_delay_lclkr_dc(delay_lclkr_dc), + .tri_lcb_clkoff_dc_b(clkoff_dc_b), + .tri_lcb_act_dis_dc(tidn), + + // FUNCTIONAL PORTS + .wr_way(dcarr_wr_way), + .wr_addr(dcarr_wr_addr), + .data_in0(dcarr_wr_data_wabcd), + .data_in1(dcarr_wr_data_wefgh), + .rd_addr(dcarr_rd_addr), + .data_out(dcarr_rd_data) + ); +end +endgenerate + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Load Rotator +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +lq_data_ld l1dcld( + + // ACT + .ex3_stg_act(ex3_stg_act_q), + .ex4_stg_act(ex4_stg_act_q), + + // Execution Pipe Load Data Rotator Controls + .ctl_dat_ex3_opsize(ctl_dat_ex3_opsize), + .ctl_dat_ex3_le_ld_rotsel(ctl_dat_ex3_le_ld_rotsel), + .ctl_dat_ex3_be_ld_rotsel(ctl_dat_ex3_be_ld_rotsel), + .ctl_dat_ex3_algebraic(ctl_dat_ex3_algebraic), + .ctl_dat_ex3_le_alg_rotsel(ctl_dat_ex3_le_alg_rotsel), + .ctl_dat_ex3_le_mode(ctl_dat_ex3_le_mode), + + // D$ Array Read Data + .dcarr_rd_data(dcarr_rd_data), + + // EX4 Load Bypass Data for Read/Write Collision detected in EX2 + .stq7_byp_val_wabcd(stq7_byp_val_wabcd), + .stq7_byp_val_wefgh(stq7_byp_val_wefgh), + .stq7_byp_data_wabcd(stq7_byp_data_wabcd), + .stq7_byp_data_wefgh(stq7_byp_data_wefgh), + .stq8_byp_data_wabcd(stq8_byp_data_wabcd), + .stq8_byp_data_wefgh(stq8_byp_data_wefgh), + .stq_byp_val_wabcd(stq_byp_val_wabcd), + .stq_byp_val_wefgh(stq_byp_val_wefgh), + + // Load Control + .ctl_dat_ex4_way_hit(ctl_dat_ex4_way_hit), + + // Parity Error Inject + .inj_dcache_parity(inj_dcache_parity_q), + + // Data Cache Array Parity Error Detected + .dcarr_data_perr_way(dcarr_data_perr_way), + + // Rotated Data + .ex5_ld_hit_data(ex5_ld_hit_data), + + // Read-Modify-Write Path Read data + .stq6_rd_data_wa(stq6_rd_data_wa), + .stq6_rd_data_wb(stq6_rd_data_wb), + .stq6_rd_data_wc(stq6_rd_data_wc), + .stq6_rd_data_wd(stq6_rd_data_wd), + .stq6_rd_data_we(stq6_rd_data_we), + .stq6_rd_data_wf(stq6_rd_data_wf), + .stq6_rd_data_wg(stq6_rd_data_wg), + .stq6_rd_data_wh(stq6_rd_data_wh), + + // Pervasive + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .sg_0(sg_0), + .func_sl_thold_0_b(func_sl_thold_0_b), + .func_sl_force(func_sl_force), + .func_nsl_thold_0_b(func_nsl_thold_0_b), + .func_nsl_force(func_nsl_force), + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .scan_in({func_scan_in_q[0],dat_scan_out_int[1:4]}), + .scan_out(func_scan_out_int[0:4]) +); + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Outputs +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +// D$ Parity Error Detected +assign dat_ctl_dcarr_perr_way = dcarr_data_perr_way; + +// XU data +assign dat_ctl_ex5_load_data = ex5_ld_hit_data; + +// AXU Reload data +assign dat_ctl_stq6_axu_data = stq6_rot_data_q; + +// SCAN OUT Gate +assign abst_scan_out = abst_scan_out_q & {4{an_ac_scan_dis_dc_b}}; +assign time_scan_out = time_scan_out_q & an_ac_scan_dis_dc_b; +assign repr_scan_out = repr_scan_out_q & an_ac_scan_dis_dc_b; +assign func_scan_out = func_scan_out_q & {7{an_ac_scan_dis_dc_b}}; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Registers +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) inj_dcache_parity_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[inj_dcache_parity_offset]), + .scout(sov[inj_dcache_parity_offset]), + .din(inj_dcache_parity_d), + .dout(inj_dcache_parity_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr0_dcdis_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_xucr0_dcdis_offset]), + .scout(sov[spr_xucr0_dcdis_offset]), + .din(spr_xucr0_dcdis_d), + .dout(spr_xucr0_dcdis_q) +); + +tri_regk #(.WIDTH(`STQ_DATA_SIZE), .INIT(0), .NEEDS_SRESET(1)) stq5_rot_data_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq4_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[stq5_rot_data_reg_offset:stq5_rot_data_reg_offset + `STQ_DATA_SIZE - 1]), + .scout(sov[stq5_rot_data_reg_offset:stq5_rot_data_reg_offset + `STQ_DATA_SIZE - 1]), + .din(stq5_rot_data_d), + .dout(stq5_rot_data_q) +); + + +tri_rlmreg_p #(.WIDTH(`STQ_DATA_SIZE), .INIT(0), .NEEDS_SRESET(1)) stq6_rot_data_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq5_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq6_rot_data_offset:stq6_rot_data_offset + `STQ_DATA_SIZE - 1]), + .scout(sov[stq6_rot_data_offset:stq6_rot_data_offset + `STQ_DATA_SIZE - 1]), + .din(stq6_rot_data_d), + .dout(stq6_rot_data_q) +); + +//--------------------------------------------------------------------- +// ACT's +//--------------------------------------------------------------------- + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_stg_act_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_stg_act_offset]), + .scout(sov[ex2_stg_act_offset]), + .din(ex2_stg_act_d), + .dout(ex2_stg_act_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_stg_act_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_stg_act_offset]), + .scout(sov[ex3_stg_act_offset]), + .din(ex3_stg_act_d), + .dout(ex3_stg_act_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_stg_act_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_stg_act_offset]), + .scout(sov[ex4_stg_act_offset]), + .din(ex4_stg_act_d), + .dout(ex4_stg_act_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_stg_act_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq2_stg_act_offset]), + .scout(sov[stq2_stg_act_offset]), + .din(stq2_stg_act_d), + .dout(stq2_stg_act_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq3_stg_act_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq3_stg_act_offset]), + .scout(sov[stq3_stg_act_offset]), + .din(stq3_stg_act_d), + .dout(stq3_stg_act_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_stg_act_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq4_stg_act_offset]), + .scout(sov[stq4_stg_act_offset]), + .din(stq4_stg_act_d), + .dout(stq4_stg_act_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq5_stg_act_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq5_stg_act_offset]), + .scout(sov[stq5_stg_act_offset]), + .din(stq5_stg_act_d), + .dout(stq5_stg_act_q) +); + +//--------------------------------------------------------------------- +// abist latches +//--------------------------------------------------------------------- +tri_rlmreg_p #(.INIT(0), .WIDTH(29), .NEEDS_SRESET(1)) abist0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pc_lq_abist_ena_dc), + .thold_b(abst_sl_thold_0_b), + .sg(sg_0), + .force_t(abst_sl_force), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .d_mode(d_mode_dc), + .scin(abist_siv[1:29]), + .scout(abist_sov[1:29]), + .din({pc_lq_abist_g8t_bw_0, + pc_lq_abist_g8t_bw_1, + pc_lq_abist_di_0, + pc_lq_abist_wl256_comp_ena, + pc_lq_abist_g8t_dcomp, + pc_lq_abist_raddr_0, + pc_lq_abist_waddr_0, + pc_lq_abist_g8t_wenb, + pc_lq_abist_g8t1p_renb_0}), + .dout({pc_lq_abist_g8t_bw_0_q, + pc_lq_abist_g8t_bw_1_q, + pc_lq_abist_di_0_q, + pc_lq_abist_wl256_comp_ena_q, + pc_lq_abist_g8t_dcomp_q, + pc_lq_abist_raddr_0_q, + pc_lq_abist_waddr_0_q, + pc_lq_abist_g8t_wenb_q, + pc_lq_abist_g8t1p_renb_0_q}) +); + +//----------------------------------------------- +// Pervasive +//----------------------------------------------- + +tri_plat #(.WIDTH(9)) perv_2to1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(pc_lq_ccflush_dc), + .din({func_nsl_thold_2, + func_sl_thold_2, + ary_nsl_thold_2, + abst_sl_thold_2, + time_sl_thold_2, + repr_sl_thold_2, + bolt_sl_thold_2, + sg_2, + fce_2}), + .q({func_nsl_thold_1, + func_sl_thold_1, + ary_nsl_thold_1, + abst_sl_thold_1, + time_sl_thold_1, + repr_sl_thold_1, + bolt_sl_thold_1, + sg_1, + fce_1}) +); + + +tri_plat #(.WIDTH(9)) perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(pc_lq_ccflush_dc), + .din({func_nsl_thold_1, + func_sl_thold_1, + ary_nsl_thold_1, + abst_sl_thold_1, + time_sl_thold_1, + repr_sl_thold_1, + bolt_sl_thold_1, + sg_1, + fce_1}), + .q({func_nsl_thold_0, + func_sl_thold_0, + ary_nsl_thold_0, + abst_sl_thold_0, + time_sl_thold_0, + repr_sl_thold_0, + bolt_sl_thold_0, + sg_0, + fce_0}) +); + + +tri_lcbor perv_lcbor_func_sl( + .clkoff_b(clkoff_dc_b), + .thold(func_sl_thold_0), + .sg(sg_0), + .act_dis(tidn), + .force_t(func_sl_force), + .thold_b(func_sl_thold_0_b) +); + + +tri_lcbor perv_lcbor_func_nsl( + .clkoff_b(clkoff_dc_b), + .thold(func_nsl_thold_0), + .sg(fce_0), + .act_dis(tidn), + .force_t(func_nsl_force), + .thold_b(func_nsl_thold_0_b) +); + + +tri_lcbor perv_lcbor_abst_sl( + .clkoff_b(clkoff_dc_b), + .thold(abst_sl_thold_0), + .sg(sg_0), + .act_dis(tidn), + .force_t(abst_sl_force), + .thold_b(abst_sl_thold_0_b) +); + +// LCBs for scan only staging latches +assign slat_force = sg_0; +assign abst_slat_thold_b = (~abst_sl_thold_0); +assign time_slat_thold_b = (~time_sl_thold_0); +assign repr_slat_thold_b = (~repr_sl_thold_0); +assign func_slat_thold_b = (~func_sl_thold_0); + + +tri_lcbs perv_lcbs_abst( + .vd(vdd), + .gd(gnd), + .delay_lclkr(delay_lclkr_dc), + .nclk(nclk), + .force_t(slat_force), + .thold_b(abst_slat_thold_b), + .dclk(abst_slat_d2clk), + .lclk(abst_slat_lclk) +); + + +tri_slat_scan #(.WIDTH(8), .INIT(8'b00000000)) perv_abst_stg( + .vd(vdd), + .gd(gnd), + .dclk(abst_slat_d2clk), + .lclk(abst_slat_lclk), + .scan_in({abst_scan_in, abst_scan_out_int}), + .scan_out({abst_scan_in_q, abst_scan_out_q}), + .q(abst_scan_q), + .q_b(abst_scan_q_b) +); + + +tri_lcbs perv_lcbs_time( + .vd(vdd), + .gd(gnd), + .delay_lclkr(delay_lclkr_dc), + .nclk(nclk), + .force_t(slat_force), + .thold_b(time_slat_thold_b), + .dclk(time_slat_d2clk), + .lclk(time_slat_lclk) +); + + +tri_slat_scan #(.WIDTH(2), .INIT(2'b00)) perv_time_stg( + .vd(vdd), + .gd(gnd), + .dclk(time_slat_d2clk), + .lclk(time_slat_lclk), + .scan_in({time_scan_in, time_scan_out_int}), + .scan_out({time_scan_in_q, time_scan_out_q}), + .q(time_scan_q), + .q_b(time_scan_q_b) +); + + +tri_lcbs perv_lcbs_repr( + .vd(vdd), + .gd(gnd), + .delay_lclkr(delay_lclkr_dc), + .nclk(nclk), + .force_t(slat_force), + .thold_b(repr_slat_thold_b), + .dclk(repr_slat_d2clk), + .lclk(repr_slat_lclk) +); + + +tri_slat_scan #(.WIDTH(2), .INIT(2'b00)) perv_repr_stg( + .vd(vdd), + .gd(gnd), + .dclk(repr_slat_d2clk), + .lclk(repr_slat_lclk), + .scan_in({repr_scan_in, repr_scan_out_int}), + .scan_out({repr_scan_in_q, repr_scan_out_q}), + .q(repr_scan_q), + .q_b(repr_scan_q_b) +); + + +tri_lcbs perv_lcbs_func( + .vd(vdd), + .gd(gnd), + .delay_lclkr(delay_lclkr_dc), + .nclk(nclk), + .force_t(slat_force), + .thold_b(func_slat_thold_b), + .dclk(func_slat_d2clk), + .lclk(func_slat_lclk) +); + + +tri_slat_scan #(.WIDTH(14), .INIT(14'b00000000000000)) perv_func_stg( + .vd(vdd), + .gd(gnd), + .dclk(func_slat_d2clk), + .lclk(func_slat_lclk), + .scan_in({func_scan_in[0], + func_scan_in[1], + func_scan_in[2], + func_scan_in[3], + func_scan_in[4], + func_scan_in[5], + func_scan_in[6], + func_scan_out_int[0], + func_scan_out_int[1], + func_scan_out_int[2], + func_scan_out_int[3], + func_scan_out_int[4], + func_scan_out_int[5], + func_scan_out_int[6]}), + .scan_out({func_scan_in_q[0], + func_scan_in_q[1], + func_scan_in_q[2], + func_scan_in_q[3], + func_scan_in_q[4], + func_scan_in_q[5], + func_scan_in_q[6], + func_scan_out_q[0], + func_scan_out_q[1], + func_scan_out_q[2], + func_scan_out_q[3], + func_scan_out_q[4], + func_scan_out_q[5], + func_scan_out_q[6]}), + .q(func_scan_q), + .q_b(func_scan_q_b) +); + +assign siv[0:scan_right] = {sov[1:scan_right], func_scan_in_q[5]}; +assign func_scan_out_int[5] = sov[0]; + +assign abist_siv = {abist_sov[1:29], abst_scan_in_q[0]}; +assign abst_scan_out_int[0] = abist_sov[0]; + +endmodule diff --git a/dev/verilog/work/lq_data_ld.v b/dev/verilog/work/lq_data_ld.v new file mode 100755 index 0000000..4951734 --- /dev/null +++ b/dev/verilog/work/lq_data_ld.v @@ -0,0 +1,1163 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +// Description: XU LSU Load Data Rotator Wrapper +// +//***************************************************************************** + +// ########################################################################################## +// VHDL Contents +// 1) 8 16 Byte Unaligned Rotator +// 2) Little Endian Support for 2,4,8,16 Byte Operations +// 3) Contains Algebraic Sign Extension +// 4) Contains 8 Way Select +// 5) Contains Fixed Point Unit (FXU) 8 Byte Load Path +// 6) Contains Auxilary Unit (AXU) 16 Byte Load Path +// ########################################################################################## + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" + +module lq_data_ld( + ex3_stg_act, + ex4_stg_act, + ctl_dat_ex3_opsize, + ctl_dat_ex3_le_ld_rotsel, + ctl_dat_ex3_be_ld_rotsel, + ctl_dat_ex3_algebraic, + ctl_dat_ex3_le_alg_rotsel, + ctl_dat_ex3_le_mode, + dcarr_rd_data, + stq7_byp_val_wabcd, + stq7_byp_val_wefgh, + stq7_byp_data_wabcd, + stq7_byp_data_wefgh, + stq8_byp_data_wabcd, + stq8_byp_data_wefgh, + stq_byp_val_wabcd, + stq_byp_val_wefgh, + ctl_dat_ex4_way_hit, + inj_dcache_parity, + dcarr_data_perr_way, + ex5_ld_hit_data, + stq6_rd_data_wa, + stq6_rd_data_wb, + stq6_rd_data_wc, + stq6_rd_data_wd, + stq6_rd_data_we, + stq6_rd_data_wf, + stq6_rd_data_wg, + stq6_rd_data_wh, + vdd, + gnd, + nclk, + sg_0, + func_sl_thold_0_b, + func_sl_force, + func_nsl_thold_0_b, + func_nsl_force, + d_mode_dc, + delay_lclkr_dc, + mpw1_dc_b, + mpw2_dc_b, + scan_in, + scan_out +); + +//------------------------------------------------------------------- +// Generics +//------------------------------------------------------------------- +//parameter EXPAND_TYPE = 2; // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) + +// ACT +input ex3_stg_act; +input ex4_stg_act; + +// Execution Pipe Load Data Rotator Controls +input [0:4] ctl_dat_ex3_opsize; +input [0:3] ctl_dat_ex3_le_ld_rotsel; +input [0:3] ctl_dat_ex3_be_ld_rotsel; +input ctl_dat_ex3_algebraic; +input [0:3] ctl_dat_ex3_le_alg_rotsel; +input ctl_dat_ex3_le_mode; + +// D$ Array Read Data +input [0:1151] dcarr_rd_data; + +// EX4 Load Bypass Data for Read/Write Collision detected in EX2 +input [0:3] stq7_byp_val_wabcd; +input [0:3] stq7_byp_val_wefgh; +input [0:143] stq7_byp_data_wabcd; +input [0:143] stq7_byp_data_wefgh; +input [0:143] stq8_byp_data_wabcd; +input [0:143] stq8_byp_data_wefgh; +input [0:3] stq_byp_val_wabcd; +input [0:3] stq_byp_val_wefgh; + +// Load Control +input [0:7] ctl_dat_ex4_way_hit; + +// Parity Error Inject +input inj_dcache_parity; + +// Data Cache Array Parity Error Detected +output [0:7] dcarr_data_perr_way; + +// Rotated Data +output [(128-`STQ_DATA_SIZE):127] ex5_ld_hit_data; + +// Read-Modify-Write Path Read data +output [0:143] stq6_rd_data_wa; +output [0:143] stq6_rd_data_wb; +output [0:143] stq6_rd_data_wc; +output [0:143] stq6_rd_data_wd; +output [0:143] stq6_rd_data_we; +output [0:143] stq6_rd_data_wf; +output [0:143] stq6_rd_data_wg; +output [0:143] stq6_rd_data_wh; + +// Pervasive +inout vdd; +inout gnd; +(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) +input [0:`NCLK_WIDTH-1] nclk; +input sg_0; +input func_sl_thold_0_b; +input func_sl_force; +input func_nsl_thold_0_b; +input func_nsl_force; +input d_mode_dc; +input delay_lclkr_dc; +input mpw1_dc_b; +input mpw2_dc_b; +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) +input [0:4] scan_in; +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) +output [0:4] scan_out; + +//-------------------------- +// constants +//-------------------------- +parameter ex5_ld_hit_data_reg_offset = 0; +parameter scan_right = ex5_ld_hit_data_reg_offset + `STQ_DATA_SIZE - 1; + +//-------------------------- +// signals +//-------------------------- +wire inj_dcache_parity_b; +wire arr_rd_data32_b; +wire stickbit32; +wire [0:127] dcarr_rd_data_wa; +wire [0:127] dcarr_rd_data_wb; +wire [0:127] dcarr_rd_data_wc; +wire [0:127] dcarr_rd_data_wd; +wire [0:127] dcarr_rd_data_we; +wire [0:127] dcarr_rd_data_wf; +wire [0:127] dcarr_rd_data_wg; +wire [0:127] dcarr_rd_data_wh; +wire [0:15] dcarr_rd_parity_wa; +wire [0:15] dcarr_rd_parity_wb; +wire [0:15] dcarr_rd_parity_wc; +wire [0:15] dcarr_rd_parity_wd; +wire [0:15] dcarr_rd_parity_we; +wire [0:15] dcarr_rd_parity_wf; +wire [0:15] dcarr_rd_parity_wg; +wire [0:15] dcarr_rd_parity_wh; +wire [0:127] dcarr_buf_data_wa; +wire [0:127] dcarr_buf_data_wb; +wire [0:127] dcarr_buf_data_wc; +wire [0:127] dcarr_buf_data_wd; +wire [0:127] dcarr_buf_data_we; +wire [0:127] dcarr_buf_data_wf; +wire [0:127] dcarr_buf_data_wg; +wire [0:127] dcarr_buf_data_wh; +wire [0:127] ex4_ld_data_rot_wa; +wire [0:127] ex4_ld_data_rot_wb; +wire [0:127] ex4_ld_data_rot_wc; +wire [0:127] ex4_ld_data_rot_wd; +wire [0:127] ex4_ld_data_rot_we; +wire [0:127] ex4_ld_data_rot_wf; +wire [0:127] ex4_ld_data_rot_wg; +wire [0:127] ex4_ld_data_rot_wh; +wire [0:5] ex4_ld_alg_bit_wa; +wire [0:5] ex4_ld_alg_bit_wb; +wire [0:5] ex4_ld_alg_bit_wc; +wire [0:5] ex4_ld_alg_bit_wd; +wire [0:5] ex4_ld_alg_bit_we; +wire [0:5] ex4_ld_alg_bit_wf; +wire [0:5] ex4_ld_alg_bit_wg; +wire [0:5] ex4_ld_alg_bit_wh; +wire [0:127] ex4_ld_data_swzl_wa; +wire [0:127] ex4_ld_data_swzl_wb; +wire [0:127] ex4_ld_data_swzl_wc; +wire [0:127] ex4_ld_data_swzl_wd; +wire [0:127] ex4_ld_data_swzl_we; +wire [0:127] ex4_ld_data_swzl_wf; +wire [0:127] ex4_ld_data_swzl_wg; +wire [0:127] ex4_ld_data_swzl_wh; +wire [0:128] ex4_ld_data_wa; +wire [0:128] ex4_ld_data_wb; +wire [0:128] ex4_ld_data_wc; +wire [0:128] ex4_ld_data_wd; +wire [0:128] ex4_ld_data_we; +wire [0:128] ex4_ld_data_wf; +wire [0:128] ex4_ld_data_wg; +wire [0:128] ex4_ld_data_wh; +wire [0:15] dcarr_perr_byte_wa; +wire [0:15] dcarr_perr_byte_wb; +wire [0:15] dcarr_perr_byte_wc; +wire [0:15] dcarr_perr_byte_wd; +wire [0:15] dcarr_perr_byte_we; +wire [0:15] dcarr_perr_byte_wf; +wire [0:15] dcarr_perr_byte_wg; +wire [0:15] dcarr_perr_byte_wh; +wire dcarr_perr_det_wa; +wire dcarr_perr_det_wb; +wire dcarr_perr_det_wc; +wire dcarr_perr_det_wd; +wire dcarr_perr_det_we; +wire dcarr_perr_det_wf; +wire dcarr_perr_det_wg; +wire dcarr_perr_det_wh; +wire [(128-`STQ_DATA_SIZE):127] ex5_ld_hit_data_d; +wire [(128-`STQ_DATA_SIZE):127] ex5_ld_hit_data_q; +wire [0:7] rot_wa_scan_in; +wire [0:7] rot_wa_scan_out; +wire [0:7] rot_wb_scan_in; +wire [0:7] rot_wb_scan_out; +wire [0:7] rot_wc_scan_in; +wire [0:7] rot_wc_scan_out; +wire [0:7] rot_wd_scan_in; +wire [0:7] rot_wd_scan_out; +wire [0:7] rot_we_scan_in; +wire [0:7] rot_we_scan_out; +wire [0:7] rot_wf_scan_in; +wire [0:7] rot_wf_scan_out; +wire [0:7] rot_wg_scan_in; +wire [0:7] rot_wg_scan_out; +wire [0:7] rot_wh_scan_in; +wire [0:7] rot_wh_scan_out; + +wire tiup; +wire [0:scan_right] siv; +wire [0:scan_right] sov; + +(* analysis_not_referenced="true" *) +wire unused; + +assign tiup = 1'b1; +assign unused = (|(ex4_ld_data_wa[0:128-`STQ_DATA_SIZE])) | (|(ex4_ld_data_wb[0:128-`STQ_DATA_SIZE])) | + (|(ex4_ld_data_wc[0:128-`STQ_DATA_SIZE])) | (|(ex4_ld_data_wd[0:128-`STQ_DATA_SIZE])) | + (|(ex4_ld_data_we[0:128-`STQ_DATA_SIZE])) | (|(ex4_ld_data_wf[0:128-`STQ_DATA_SIZE])) | + (|(ex4_ld_data_wg[0:128-`STQ_DATA_SIZE])) | (|(ex4_ld_data_wh[0:128-`STQ_DATA_SIZE])); +// ############################################################################################# + +// ############################################################################################# +// Inject Data Cache Error +// ############################################################################################# + +// Sticking bit32 of the array when Data Cache Parity Error Inject is on +// Bit32 will be stuck to 1 +// Bit32 refers to bit2 of byte0 of WayA +assign inj_dcache_parity_b = (~inj_dcache_parity); +assign arr_rd_data32_b = (~dcarr_rd_data[32]); +assign stickbit32 = (~(arr_rd_data32_b & inj_dcache_parity_b)); +// ############################################################################################# + +// ############################################################################################# +// Separate Data +// ############################################################################################# +// Data Bits +assign dcarr_rd_data_wa = {dcarr_rd_data[0:31], stickbit32, dcarr_rd_data[33:127]}; +assign dcarr_rd_data_wb = dcarr_rd_data[144:271]; +assign dcarr_rd_data_wc = dcarr_rd_data[288:415]; +assign dcarr_rd_data_wd = dcarr_rd_data[432:559]; +assign dcarr_rd_data_we = dcarr_rd_data[576:703]; +assign dcarr_rd_data_wf = dcarr_rd_data[720:847]; +assign dcarr_rd_data_wg = dcarr_rd_data[864:991]; +assign dcarr_rd_data_wh = dcarr_rd_data[1008:1135]; + +// Parity Bits +assign dcarr_rd_parity_wa = dcarr_rd_data[128:143]; +assign dcarr_rd_parity_wb = dcarr_rd_data[272:287]; +assign dcarr_rd_parity_wc = dcarr_rd_data[416:431]; +assign dcarr_rd_parity_wd = dcarr_rd_data[560:575]; +assign dcarr_rd_parity_we = dcarr_rd_data[704:719]; +assign dcarr_rd_parity_wf = dcarr_rd_data[848:863]; +assign dcarr_rd_parity_wg = dcarr_rd_data[992:1007]; +assign dcarr_rd_parity_wh = dcarr_rd_data[1136:1151]; +// ############################################################################################# + +// ############################################################################################# +// Way A 16 Byte Rotator +// ############################################################################################# +generate begin : l1dcrotrWA + genvar b; + for (b = 0; b <= 7; b = b + 1) begin : l1dcrotrWA + if (b == 0) begin : sgrp + tri_rot16s_ru bits( + .opsize(ctl_dat_ex3_opsize), + .le(ctl_dat_ex3_le_mode), + .le_rotate_sel(ctl_dat_ex3_le_ld_rotsel), + .be_rotate_sel(ctl_dat_ex3_be_ld_rotsel), + .algebraic(ctl_dat_ex3_algebraic), + .le_algebraic_sel(ctl_dat_ex3_le_alg_rotsel), + .be_algebraic_sel(ctl_dat_ex3_le_ld_rotsel), + + .arr_data(dcarr_rd_data_wa[b * 16:(b * 16) + 15]), + .stq7_byp_val(stq7_byp_val_wabcd[0]), + .stq_byp_val(stq_byp_val_wabcd[0]), + .stq7_rmw_data(stq7_byp_data_wabcd[b * 16:(b * 16) + 15]), + .stq8_rmw_data(stq8_byp_data_wabcd[b * 16:(b * 16) + 15]), + .data_latched(dcarr_buf_data_wa[b * 16:(b * 16) + 15]), + .data_rot(ex4_ld_data_rot_wa[b * 16:(b * 16) + 15]), + .algebraic_bit(ex4_ld_alg_bit_wa), + + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .act(ex3_stg_act), + .func_sl_force(func_sl_force), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .func_sl_thold_0_b(func_sl_thold_0_b), + .sg_0(sg_0), + .scan_in(rot_wa_scan_in[b]), + .scan_out(rot_wa_scan_out[b]) + ); + end + if (b != 0) begin : grp + tri_rot16_ru bits( + .opsize(ctl_dat_ex3_opsize), + .le(ctl_dat_ex3_le_mode), + .le_rotate_sel(ctl_dat_ex3_le_ld_rotsel), + .be_rotate_sel(ctl_dat_ex3_be_ld_rotsel), + + .arr_data(dcarr_rd_data_wa[b * 16:(b * 16) + 15]), + .stq7_byp_val(stq7_byp_val_wabcd[0]), + .stq_byp_val(stq_byp_val_wabcd[0]), + .stq7_rmw_data(stq7_byp_data_wabcd[b * 16:(b * 16) + 15]), + .stq8_rmw_data(stq8_byp_data_wabcd[b * 16:(b * 16) + 15]), + .data_latched(dcarr_buf_data_wa[b * 16:(b * 16) + 15]), + .data_rot(ex4_ld_data_rot_wa[b * 16:(b * 16) + 15]), + + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .act(ex3_stg_act), + .func_sl_force(func_sl_force), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .func_sl_thold_0_b(func_sl_thold_0_b), + .sg_0(sg_0), + .scan_in(rot_wa_scan_in[b]), + .scan_out(rot_wa_scan_out[b]) + ); + end + end +end +endgenerate +// ############################################################################################# + +// ############################################################################################# +// Way B 16 Byte Rotator +// ############################################################################################# +generate begin : l1dcrotrWB + genvar b; + for (b = 0; b <= 7; b = b + 1) begin : l1dcrotrWB + if (b == 0) begin : sgrp + tri_rot16s_ru bits( + .opsize(ctl_dat_ex3_opsize), + .le(ctl_dat_ex3_le_mode), + .le_rotate_sel(ctl_dat_ex3_le_ld_rotsel), + .be_rotate_sel(ctl_dat_ex3_be_ld_rotsel), + .algebraic(ctl_dat_ex3_algebraic), + .le_algebraic_sel(ctl_dat_ex3_le_alg_rotsel), + .be_algebraic_sel(ctl_dat_ex3_le_ld_rotsel), + + .arr_data(dcarr_rd_data_wb[b * 16:(b * 16) + 15]), + .stq7_byp_val(stq7_byp_val_wabcd[1]), + .stq_byp_val(stq_byp_val_wabcd[1]), + .stq7_rmw_data(stq7_byp_data_wabcd[b * 16:(b * 16) + 15]), + .stq8_rmw_data(stq8_byp_data_wabcd[b * 16:(b * 16) + 15]), + .data_latched(dcarr_buf_data_wb[b * 16:(b * 16) + 15]), + .data_rot(ex4_ld_data_rot_wb[b * 16:(b * 16) + 15]), + .algebraic_bit(ex4_ld_alg_bit_wb), + + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .act(ex3_stg_act), + .func_sl_force(func_sl_force), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .func_sl_thold_0_b(func_sl_thold_0_b), + .sg_0(sg_0), + .scan_in(rot_wb_scan_in[b]), + .scan_out(rot_wb_scan_out[b]) + ); + end + if (b != 0) begin : grp + tri_rot16_ru bits( + .opsize(ctl_dat_ex3_opsize), + .le(ctl_dat_ex3_le_mode), + .le_rotate_sel(ctl_dat_ex3_le_ld_rotsel), + .be_rotate_sel(ctl_dat_ex3_be_ld_rotsel), + + .arr_data(dcarr_rd_data_wb[b * 16:(b * 16) + 15]), + .stq7_byp_val(stq7_byp_val_wabcd[1]), + .stq_byp_val(stq_byp_val_wabcd[1]), + .stq7_rmw_data(stq7_byp_data_wabcd[b * 16:(b * 16) + 15]), + .stq8_rmw_data(stq8_byp_data_wabcd[b * 16:(b * 16) + 15]), + .data_latched(dcarr_buf_data_wb[b * 16:(b * 16) + 15]), + .data_rot(ex4_ld_data_rot_wb[b * 16:(b * 16) + 15]), + + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .act(ex3_stg_act), + .func_sl_force(func_sl_force), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .func_sl_thold_0_b(func_sl_thold_0_b), + .sg_0(sg_0), + .scan_in(rot_wb_scan_in[b]), + .scan_out(rot_wb_scan_out[b]) + ); + end + end +end +endgenerate +// ############################################################################################# + +// ############################################################################################# +// Way C 16 Byte Rotator +// ############################################################################################# +generate begin : l1dcrotrWC + genvar b; + for (b = 0; b <= 7; b = b + 1) begin : l1dcrotrWC + if (b == 0) begin : sgrp + tri_rot16s_ru bits( + .opsize(ctl_dat_ex3_opsize), + .le(ctl_dat_ex3_le_mode), + .le_rotate_sel(ctl_dat_ex3_le_ld_rotsel), + .be_rotate_sel(ctl_dat_ex3_be_ld_rotsel), + .algebraic(ctl_dat_ex3_algebraic), + .le_algebraic_sel(ctl_dat_ex3_le_alg_rotsel), + .be_algebraic_sel(ctl_dat_ex3_le_ld_rotsel), + + .arr_data(dcarr_rd_data_wc[b * 16:(b * 16) + 15]), + .stq7_byp_val(stq7_byp_val_wabcd[2]), + .stq_byp_val(stq_byp_val_wabcd[2]), + .stq7_rmw_data(stq7_byp_data_wabcd[b * 16:(b * 16) + 15]), + .stq8_rmw_data(stq8_byp_data_wabcd[b * 16:(b * 16) + 15]), + .data_latched(dcarr_buf_data_wc[b * 16:(b * 16) + 15]), + .data_rot(ex4_ld_data_rot_wc[b * 16:(b * 16) + 15]), + .algebraic_bit(ex4_ld_alg_bit_wc), + + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .act(ex3_stg_act), + .func_sl_force(func_sl_force), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .func_sl_thold_0_b(func_sl_thold_0_b), + .sg_0(sg_0), + .scan_in(rot_wc_scan_in[b]), + .scan_out(rot_wc_scan_out[b]) + ); + end + if (b != 0) begin : grp + tri_rot16_ru bits( + .opsize(ctl_dat_ex3_opsize), + .le(ctl_dat_ex3_le_mode), + .le_rotate_sel(ctl_dat_ex3_le_ld_rotsel), + .be_rotate_sel(ctl_dat_ex3_be_ld_rotsel), + + .arr_data(dcarr_rd_data_wc[b * 16:(b * 16) + 15]), + .stq7_byp_val(stq7_byp_val_wabcd[2]), + .stq_byp_val(stq_byp_val_wabcd[2]), + .stq7_rmw_data(stq7_byp_data_wabcd[b * 16:(b * 16) + 15]), + .stq8_rmw_data(stq8_byp_data_wabcd[b * 16:(b * 16) + 15]), + .data_latched(dcarr_buf_data_wc[b * 16:(b * 16) + 15]), + .data_rot(ex4_ld_data_rot_wc[b * 16:(b * 16) + 15]), + + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .act(ex3_stg_act), + .func_sl_force(func_sl_force), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .func_sl_thold_0_b(func_sl_thold_0_b), + .sg_0(sg_0), + .scan_in(rot_wc_scan_in[b]), + .scan_out(rot_wc_scan_out[b]) + ); + end + end +end +endgenerate +// ############################################################################################# + +// ############################################################################################# +// Way D 16 Byte Rotator +// ############################################################################################# +generate begin : l1dcrotrWD + genvar b; + for (b = 0; b <= 7; b = b + 1) begin : l1dcrotrWD + if (b == 0) begin : sgrp + tri_rot16s_ru bits( + .opsize(ctl_dat_ex3_opsize), + .le(ctl_dat_ex3_le_mode), + .le_rotate_sel(ctl_dat_ex3_le_ld_rotsel), + .be_rotate_sel(ctl_dat_ex3_be_ld_rotsel), + .algebraic(ctl_dat_ex3_algebraic), + .le_algebraic_sel(ctl_dat_ex3_le_alg_rotsel), + .be_algebraic_sel(ctl_dat_ex3_le_ld_rotsel), + + .arr_data(dcarr_rd_data_wd[b * 16:(b * 16) + 15]), + .stq7_byp_val(stq7_byp_val_wabcd[3]), + .stq_byp_val(stq_byp_val_wabcd[3]), + .stq7_rmw_data(stq7_byp_data_wabcd[b * 16:(b * 16) + 15]), + .stq8_rmw_data(stq8_byp_data_wabcd[b * 16:(b * 16) + 15]), + .data_latched(dcarr_buf_data_wd[b * 16:(b * 16) + 15]), + .data_rot(ex4_ld_data_rot_wd[b * 16:(b * 16) + 15]), + .algebraic_bit(ex4_ld_alg_bit_wd), + + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .act(ex3_stg_act), + .func_sl_force(func_sl_force), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .func_sl_thold_0_b(func_sl_thold_0_b), + .sg_0(sg_0), + .scan_in(rot_wd_scan_in[b]), + .scan_out(rot_wd_scan_out[b]) + ); + end + if (b != 0) begin : grp + tri_rot16_ru bits( + .opsize(ctl_dat_ex3_opsize), + .le(ctl_dat_ex3_le_mode), + .le_rotate_sel(ctl_dat_ex3_le_ld_rotsel), + .be_rotate_sel(ctl_dat_ex3_be_ld_rotsel), + + .arr_data(dcarr_rd_data_wd[b * 16:(b * 16) + 15]), + .stq7_byp_val(stq7_byp_val_wabcd[3]), + .stq_byp_val(stq_byp_val_wabcd[3]), + .stq7_rmw_data(stq7_byp_data_wabcd[b * 16:(b * 16) + 15]), + .stq8_rmw_data(stq8_byp_data_wabcd[b * 16:(b * 16) + 15]), + .data_latched(dcarr_buf_data_wd[b * 16:(b * 16) + 15]), + .data_rot(ex4_ld_data_rot_wd[b * 16:(b * 16) + 15]), + + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .act(ex3_stg_act), + .func_sl_force(func_sl_force), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .func_sl_thold_0_b(func_sl_thold_0_b), + .sg_0(sg_0), + .scan_in(rot_wd_scan_in[b]), + .scan_out(rot_wd_scan_out[b]) + ); + end + end +end +endgenerate +// ############################################################################################# + +// ############################################################################################# +// Way E 16 Byte Rotator +// ############################################################################################# +generate begin : l1dcrotrWE + genvar b; + for (b = 0; b <= 7; b = b + 1) begin : l1dcrotrWE + if (b == 0) begin : sgrp + tri_rot16s_ru bits( + .opsize(ctl_dat_ex3_opsize), + .le(ctl_dat_ex3_le_mode), + .le_rotate_sel(ctl_dat_ex3_le_ld_rotsel), + .be_rotate_sel(ctl_dat_ex3_be_ld_rotsel), + .algebraic(ctl_dat_ex3_algebraic), + .le_algebraic_sel(ctl_dat_ex3_le_alg_rotsel), + .be_algebraic_sel(ctl_dat_ex3_le_ld_rotsel), + + .arr_data(dcarr_rd_data_we[b * 16:(b * 16) + 15]), + .stq7_byp_val(stq7_byp_val_wefgh[0]), + .stq_byp_val(stq_byp_val_wefgh[0]), + .stq7_rmw_data(stq7_byp_data_wefgh[b * 16:(b * 16) + 15]), + .stq8_rmw_data(stq8_byp_data_wefgh[b * 16:(b * 16) + 15]), + .data_latched(dcarr_buf_data_we[b * 16:(b * 16) + 15]), + .data_rot(ex4_ld_data_rot_we[b * 16:(b * 16) + 15]), + .algebraic_bit(ex4_ld_alg_bit_we), + + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .act(ex3_stg_act), + .func_sl_force(func_sl_force), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .func_sl_thold_0_b(func_sl_thold_0_b), + .sg_0(sg_0), + .scan_in(rot_we_scan_in[b]), + .scan_out(rot_we_scan_out[b]) + ); + end + if (b != 0) begin : grp + tri_rot16_ru bits( + .opsize(ctl_dat_ex3_opsize), + .le(ctl_dat_ex3_le_mode), + .le_rotate_sel(ctl_dat_ex3_le_ld_rotsel), + .be_rotate_sel(ctl_dat_ex3_be_ld_rotsel), + + .arr_data(dcarr_rd_data_we[b * 16:(b * 16) + 15]), + .stq7_byp_val(stq7_byp_val_wefgh[0]), + .stq_byp_val(stq_byp_val_wefgh[0]), + .stq7_rmw_data(stq7_byp_data_wefgh[b * 16:(b * 16) + 15]), + .stq8_rmw_data(stq8_byp_data_wefgh[b * 16:(b * 16) + 15]), + .data_latched(dcarr_buf_data_we[b * 16:(b * 16) + 15]), + .data_rot(ex4_ld_data_rot_we[b * 16:(b * 16) + 15]), + + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .act(ex3_stg_act), + .func_sl_force(func_sl_force), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .func_sl_thold_0_b(func_sl_thold_0_b), + .sg_0(sg_0), + .scan_in(rot_we_scan_in[b]), + .scan_out(rot_we_scan_out[b]) + ); + end + end +end +endgenerate +// ############################################################################################# + +// ############################################################################################# +// Way F 16 Byte Rotator +// ############################################################################################# +generate begin : l1dcrotrWF + genvar b; + for (b = 0; b <= 7; b = b + 1) begin : l1dcrotrWF + if (b == 0) begin : sgrp + tri_rot16s_ru bits( + .opsize(ctl_dat_ex3_opsize), + .le(ctl_dat_ex3_le_mode), + .le_rotate_sel(ctl_dat_ex3_le_ld_rotsel), + .be_rotate_sel(ctl_dat_ex3_be_ld_rotsel), + .algebraic(ctl_dat_ex3_algebraic), + .le_algebraic_sel(ctl_dat_ex3_le_alg_rotsel), + .be_algebraic_sel(ctl_dat_ex3_le_ld_rotsel), + + .arr_data(dcarr_rd_data_wf[b * 16:(b * 16) + 15]), + .stq7_byp_val(stq7_byp_val_wefgh[1]), + .stq_byp_val(stq_byp_val_wefgh[1]), + .stq7_rmw_data(stq7_byp_data_wefgh[b * 16:(b * 16) + 15]), + .stq8_rmw_data(stq8_byp_data_wefgh[b * 16:(b * 16) + 15]), + .data_latched(dcarr_buf_data_wf[b * 16:(b * 16) + 15]), + .data_rot(ex4_ld_data_rot_wf[b * 16:(b * 16) + 15]), + .algebraic_bit(ex4_ld_alg_bit_wf), + + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .act(ex3_stg_act), + .func_sl_force(func_sl_force), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .func_sl_thold_0_b(func_sl_thold_0_b), + .sg_0(sg_0), + .scan_in(rot_wf_scan_in[b]), + .scan_out(rot_wf_scan_out[b]) + ); + end + if (b != 0) begin : grp + tri_rot16_ru bits( + .opsize(ctl_dat_ex3_opsize), + .le(ctl_dat_ex3_le_mode), + .le_rotate_sel(ctl_dat_ex3_le_ld_rotsel), + .be_rotate_sel(ctl_dat_ex3_be_ld_rotsel), + + .arr_data(dcarr_rd_data_wf[b * 16:(b * 16) + 15]), + .stq7_byp_val(stq7_byp_val_wefgh[1]), + .stq_byp_val(stq_byp_val_wefgh[1]), + .stq7_rmw_data(stq7_byp_data_wefgh[b * 16:(b * 16) + 15]), + .stq8_rmw_data(stq8_byp_data_wefgh[b * 16:(b * 16) + 15]), + .data_latched(dcarr_buf_data_wf[b * 16:(b * 16) + 15]), + .data_rot(ex4_ld_data_rot_wf[b * 16:(b * 16) + 15]), + + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .act(ex3_stg_act), + .func_sl_force(func_sl_force), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .func_sl_thold_0_b(func_sl_thold_0_b), + .sg_0(sg_0), + .scan_in(rot_wf_scan_in[b]), + .scan_out(rot_wf_scan_out[b]) + ); + end + end +end +endgenerate +// ############################################################################################# + +// ############################################################################################# +// Way G 16 Byte Rotator +// ############################################################################################# +generate begin : l1dcrotrWG + genvar b; + for (b = 0; b <= 7; b = b + 1) begin : l1dcrotrWG + if (b == 0) begin : sgrp + tri_rot16s_ru bits( + .opsize(ctl_dat_ex3_opsize), + .le(ctl_dat_ex3_le_mode), + .le_rotate_sel(ctl_dat_ex3_le_ld_rotsel), + .be_rotate_sel(ctl_dat_ex3_be_ld_rotsel), + .algebraic(ctl_dat_ex3_algebraic), + .le_algebraic_sel(ctl_dat_ex3_le_alg_rotsel), + .be_algebraic_sel(ctl_dat_ex3_le_ld_rotsel), + + .arr_data(dcarr_rd_data_wg[b * 16:(b * 16) + 15]), + .stq7_byp_val(stq7_byp_val_wefgh[2]), + .stq_byp_val(stq_byp_val_wefgh[2]), + .stq7_rmw_data(stq7_byp_data_wefgh[b * 16:(b * 16) + 15]), + .stq8_rmw_data(stq8_byp_data_wefgh[b * 16:(b * 16) + 15]), + .data_latched(dcarr_buf_data_wg[b * 16:(b * 16) + 15]), + .data_rot(ex4_ld_data_rot_wg[b * 16:(b * 16) + 15]), + .algebraic_bit(ex4_ld_alg_bit_wg), + + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .act(ex3_stg_act), + .func_sl_force(func_sl_force), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .func_sl_thold_0_b(func_sl_thold_0_b), + .sg_0(sg_0), + .scan_in(rot_wg_scan_in[b]), + .scan_out(rot_wg_scan_out[b]) + ); + end + if (b != 0) begin : grp + tri_rot16_ru bits( + .opsize(ctl_dat_ex3_opsize), + .le(ctl_dat_ex3_le_mode), + .le_rotate_sel(ctl_dat_ex3_le_ld_rotsel), + .be_rotate_sel(ctl_dat_ex3_be_ld_rotsel), + + .arr_data(dcarr_rd_data_wg[b * 16:(b * 16) + 15]), + .stq7_byp_val(stq7_byp_val_wefgh[2]), + .stq_byp_val(stq_byp_val_wefgh[2]), + .stq7_rmw_data(stq7_byp_data_wefgh[b * 16:(b * 16) + 15]), + .stq8_rmw_data(stq8_byp_data_wefgh[b * 16:(b * 16) + 15]), + .data_latched(dcarr_buf_data_wg[b * 16:(b * 16) + 15]), + .data_rot(ex4_ld_data_rot_wg[b * 16:(b * 16) + 15]), + + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .act(ex3_stg_act), + .func_sl_force(func_sl_force), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .func_sl_thold_0_b(func_sl_thold_0_b), + .sg_0(sg_0), + .scan_in(rot_wg_scan_in[b]), + .scan_out(rot_wg_scan_out[b]) + ); + end + end +end +endgenerate +// ############################################################################################# + +// ############################################################################################# +// Way H 16 Byte Rotator +// ############################################################################################# +generate begin : l1dcrotrWH + genvar b; + for (b = 0; b <= 7; b = b + 1) begin : l1dcrotrWH + if (b == 0) begin : sgrp + tri_rot16s_ru bits( + .opsize(ctl_dat_ex3_opsize), + .le(ctl_dat_ex3_le_mode), + .le_rotate_sel(ctl_dat_ex3_le_ld_rotsel), + .be_rotate_sel(ctl_dat_ex3_be_ld_rotsel), + .algebraic(ctl_dat_ex3_algebraic), + .le_algebraic_sel(ctl_dat_ex3_le_alg_rotsel), + .be_algebraic_sel(ctl_dat_ex3_le_ld_rotsel), + + .arr_data(dcarr_rd_data_wh[b * 16:(b * 16) + 15]), + .stq7_byp_val(stq7_byp_val_wefgh[3]), + .stq_byp_val(stq_byp_val_wefgh[3]), + .stq7_rmw_data(stq7_byp_data_wefgh[b * 16:(b * 16) + 15]), + .stq8_rmw_data(stq8_byp_data_wefgh[b * 16:(b * 16) + 15]), + .data_latched(dcarr_buf_data_wh[b * 16:(b * 16) + 15]), + .data_rot(ex4_ld_data_rot_wh[b * 16:(b * 16) + 15]), + .algebraic_bit(ex4_ld_alg_bit_wh), + + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .act(ex3_stg_act), + .func_sl_force(func_sl_force), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .func_sl_thold_0_b(func_sl_thold_0_b), + .sg_0(sg_0), + .scan_in(rot_wh_scan_in[b]), + .scan_out(rot_wh_scan_out[b]) + ); + end + if (b != 0) begin : grp + tri_rot16_ru bits( + .opsize(ctl_dat_ex3_opsize), + .le(ctl_dat_ex3_le_mode), + .le_rotate_sel(ctl_dat_ex3_le_ld_rotsel), + .be_rotate_sel(ctl_dat_ex3_be_ld_rotsel), + + .arr_data(dcarr_rd_data_wh[b * 16:(b * 16) + 15]), + .stq7_byp_val(stq7_byp_val_wefgh[3]), + .stq_byp_val(stq_byp_val_wefgh[3]), + .stq7_rmw_data(stq7_byp_data_wefgh[b * 16:(b * 16) + 15]), + .stq8_rmw_data(stq8_byp_data_wefgh[b * 16:(b * 16) + 15]), + .data_latched(dcarr_buf_data_wh[b * 16:(b * 16) + 15]), + .data_rot(ex4_ld_data_rot_wh[b * 16:(b * 16) + 15]), + + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .act(ex3_stg_act), + .func_sl_force(func_sl_force), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .func_sl_thold_0_b(func_sl_thold_0_b), + .sg_0(sg_0), + .scan_in(rot_wh_scan_in[b]), + .scan_out(rot_wh_scan_out[b]) + ); + end + end +end +endgenerate +// ############################################################################################# + +// ############################################################################################# +// Parity Check +// ############################################################################################# +generate begin : parBdet + genvar b; + for (b = 0; b <= 15; b = b + 1) begin : parBdet + assign dcarr_perr_byte_wa[b] = dcarr_buf_data_wa[b + 0] ^ dcarr_buf_data_wa[b + 16] ^ + dcarr_buf_data_wa[b + 32] ^ dcarr_buf_data_wa[b + 48] ^ + dcarr_buf_data_wa[b + 64] ^ dcarr_buf_data_wa[b + 80] ^ + dcarr_buf_data_wa[b + 96] ^ dcarr_buf_data_wa[b + 112] ^ + dcarr_rd_parity_wa[b]; + + assign dcarr_perr_byte_wb[b] = dcarr_buf_data_wb[b + 0] ^ dcarr_buf_data_wb[b + 16] ^ + dcarr_buf_data_wb[b + 32] ^ dcarr_buf_data_wb[b + 48] ^ + dcarr_buf_data_wb[b + 64] ^ dcarr_buf_data_wb[b + 80] ^ + dcarr_buf_data_wb[b + 96] ^ dcarr_buf_data_wb[b + 112] ^ + dcarr_rd_parity_wb[b]; + + assign dcarr_perr_byte_wc[b] = dcarr_buf_data_wc[b + 0] ^ dcarr_buf_data_wc[b + 16] ^ + dcarr_buf_data_wc[b + 32] ^ dcarr_buf_data_wc[b + 48] ^ + dcarr_buf_data_wc[b + 64] ^ dcarr_buf_data_wc[b + 80] ^ + dcarr_buf_data_wc[b + 96] ^ dcarr_buf_data_wc[b + 112] ^ + dcarr_rd_parity_wc[b]; + + assign dcarr_perr_byte_wd[b] = dcarr_buf_data_wd[b + 0] ^ dcarr_buf_data_wd[b + 16] ^ + dcarr_buf_data_wd[b + 32] ^ dcarr_buf_data_wd[b + 48] ^ + dcarr_buf_data_wd[b + 64] ^ dcarr_buf_data_wd[b + 80] ^ + dcarr_buf_data_wd[b + 96] ^ dcarr_buf_data_wd[b + 112] ^ + dcarr_rd_parity_wd[b]; + + assign dcarr_perr_byte_we[b] = dcarr_buf_data_we[b + 0] ^ dcarr_buf_data_we[b + 16] ^ + dcarr_buf_data_we[b + 32] ^ dcarr_buf_data_we[b + 48] ^ + dcarr_buf_data_we[b + 64] ^ dcarr_buf_data_we[b + 80] ^ + dcarr_buf_data_we[b + 96] ^ dcarr_buf_data_we[b + 112] ^ + dcarr_rd_parity_we[b]; + + assign dcarr_perr_byte_wf[b] = dcarr_buf_data_wf[b + 0] ^ dcarr_buf_data_wf[b + 16] ^ + dcarr_buf_data_wf[b + 32] ^ dcarr_buf_data_wf[b + 48] ^ + dcarr_buf_data_wf[b + 64] ^ dcarr_buf_data_wf[b + 80] ^ + dcarr_buf_data_wf[b + 96] ^ dcarr_buf_data_wf[b + 112] ^ + dcarr_rd_parity_wf[b]; + + assign dcarr_perr_byte_wg[b] = dcarr_buf_data_wg[b + 0] ^ dcarr_buf_data_wg[b + 16] ^ + dcarr_buf_data_wg[b + 32] ^ dcarr_buf_data_wg[b + 48] ^ + dcarr_buf_data_wg[b + 64] ^ dcarr_buf_data_wg[b + 80] ^ + dcarr_buf_data_wg[b + 96] ^ dcarr_buf_data_wg[b + 112] ^ + dcarr_rd_parity_wg[b]; + + assign dcarr_perr_byte_wh[b] = dcarr_buf_data_wh[b + 0] ^ dcarr_buf_data_wh[b + 16] ^ + dcarr_buf_data_wh[b + 32] ^ dcarr_buf_data_wh[b + 48] ^ + dcarr_buf_data_wh[b + 64] ^ dcarr_buf_data_wh[b + 80] ^ + dcarr_buf_data_wh[b + 96] ^ dcarr_buf_data_wh[b + 112] ^ + dcarr_rd_parity_wh[b]; + end +end +endgenerate + +// Report a Parity error if the data is not being bypassed due to a store to the same address +assign dcarr_perr_det_wa = |(dcarr_perr_byte_wa) & ~stq_byp_val_wabcd[0]; +assign dcarr_perr_det_wb = |(dcarr_perr_byte_wb) & ~stq_byp_val_wabcd[1]; +assign dcarr_perr_det_wc = |(dcarr_perr_byte_wc) & ~stq_byp_val_wabcd[2]; +assign dcarr_perr_det_wd = |(dcarr_perr_byte_wd) & ~stq_byp_val_wabcd[3]; +assign dcarr_perr_det_we = |(dcarr_perr_byte_we) & ~stq_byp_val_wefgh[0]; +assign dcarr_perr_det_wf = |(dcarr_perr_byte_wf) & ~stq_byp_val_wefgh[1]; +assign dcarr_perr_det_wg = |(dcarr_perr_byte_wg) & ~stq_byp_val_wefgh[2]; +assign dcarr_perr_det_wh = |(dcarr_perr_byte_wh) & ~stq_byp_val_wefgh[3]; + +// EX4/STQ6 Data Cache Array Parity Error Detected +assign dcarr_data_perr_way = {dcarr_perr_det_wa, dcarr_perr_det_wb, dcarr_perr_det_wc, dcarr_perr_det_wd, + dcarr_perr_det_we, dcarr_perr_det_wf, dcarr_perr_det_wg, dcarr_perr_det_wh}; + +// ############################################################################################# + +// ############################################################################################# +// Algebraic Sign Extension +// ############################################################################################# + +// Data Fixup +generate begin : ldData + genvar bb; + for (bb = 0; bb <= 15; bb = bb + 1) begin : ldData + assign ex4_ld_data_swzl_wa[bb * 8:(bb * 8) + 7] = {ex4_ld_data_rot_wa[bb + 0], + ex4_ld_data_rot_wa[bb + 16], + ex4_ld_data_rot_wa[bb + 32], + ex4_ld_data_rot_wa[bb + 48], + ex4_ld_data_rot_wa[bb + 64], + ex4_ld_data_rot_wa[bb + 80], + ex4_ld_data_rot_wa[bb + 96], + ex4_ld_data_rot_wa[bb + 112]}; + + assign ex4_ld_data_swzl_wb[bb * 8:(bb * 8) + 7] = {ex4_ld_data_rot_wb[bb + 0], + ex4_ld_data_rot_wb[bb + 16], + ex4_ld_data_rot_wb[bb + 32], + ex4_ld_data_rot_wb[bb + 48], + ex4_ld_data_rot_wb[bb + 64], + ex4_ld_data_rot_wb[bb + 80], + ex4_ld_data_rot_wb[bb + 96], + ex4_ld_data_rot_wb[bb + 112]}; + + assign ex4_ld_data_swzl_wc[bb * 8:(bb * 8) + 7] = {ex4_ld_data_rot_wc[bb + 0], + ex4_ld_data_rot_wc[bb + 16], + ex4_ld_data_rot_wc[bb + 32], + ex4_ld_data_rot_wc[bb + 48], + ex4_ld_data_rot_wc[bb + 64], + ex4_ld_data_rot_wc[bb + 80], + ex4_ld_data_rot_wc[bb + 96], + ex4_ld_data_rot_wc[bb + 112]}; + + assign ex4_ld_data_swzl_wd[bb * 8:(bb * 8) + 7] = {ex4_ld_data_rot_wd[bb + 0], + ex4_ld_data_rot_wd[bb + 16], + ex4_ld_data_rot_wd[bb + 32], + ex4_ld_data_rot_wd[bb + 48], + ex4_ld_data_rot_wd[bb + 64], + ex4_ld_data_rot_wd[bb + 80], + ex4_ld_data_rot_wd[bb + 96], + ex4_ld_data_rot_wd[bb + 112]}; + + assign ex4_ld_data_swzl_we[bb * 8:(bb * 8) + 7] = {ex4_ld_data_rot_we[bb + 0], + ex4_ld_data_rot_we[bb + 16], + ex4_ld_data_rot_we[bb + 32], + ex4_ld_data_rot_we[bb + 48], + ex4_ld_data_rot_we[bb + 64], + ex4_ld_data_rot_we[bb + 80], + ex4_ld_data_rot_we[bb + 96], + ex4_ld_data_rot_we[bb + 112]}; + + assign ex4_ld_data_swzl_wf[bb * 8:(bb * 8) + 7] = {ex4_ld_data_rot_wf[bb + 0], + ex4_ld_data_rot_wf[bb + 16], + ex4_ld_data_rot_wf[bb + 32], + ex4_ld_data_rot_wf[bb + 48], + ex4_ld_data_rot_wf[bb + 64], + ex4_ld_data_rot_wf[bb + 80], + ex4_ld_data_rot_wf[bb + 96], + ex4_ld_data_rot_wf[bb + 112]}; + + assign ex4_ld_data_swzl_wg[bb * 8:(bb * 8) + 7] = {ex4_ld_data_rot_wg[bb + 0], + ex4_ld_data_rot_wg[bb + 16], + ex4_ld_data_rot_wg[bb + 32], + ex4_ld_data_rot_wg[bb + 48], + ex4_ld_data_rot_wg[bb + 64], + ex4_ld_data_rot_wg[bb + 80], + ex4_ld_data_rot_wg[bb + 96], + ex4_ld_data_rot_wg[bb + 112]}; + + assign ex4_ld_data_swzl_wh[bb * 8:(bb * 8) + 7] = {ex4_ld_data_rot_wh[bb + 0], + ex4_ld_data_rot_wh[bb + 16], + ex4_ld_data_rot_wh[bb + 32], + ex4_ld_data_rot_wh[bb + 48], + ex4_ld_data_rot_wh[bb + 64], + ex4_ld_data_rot_wh[bb + 80], + ex4_ld_data_rot_wh[bb + 96], + ex4_ld_data_rot_wh[bb + 112]}; + end +end +endgenerate + +// Non-Sign Extension +assign ex4_ld_data_wa[0:64] = {1'b0, ex4_ld_data_swzl_wa[0:63]}; +assign ex4_ld_data_wb[0:64] = {1'b0, ex4_ld_data_swzl_wb[0:63]}; +assign ex4_ld_data_wc[0:64] = {1'b0, ex4_ld_data_swzl_wc[0:63]}; +assign ex4_ld_data_wd[0:64] = {1'b0, ex4_ld_data_swzl_wd[0:63]}; +assign ex4_ld_data_we[0:64] = {1'b0, ex4_ld_data_swzl_we[0:63]}; +assign ex4_ld_data_wf[0:64] = {1'b0, ex4_ld_data_swzl_wf[0:63]}; +assign ex4_ld_data_wg[0:64] = {1'b0, ex4_ld_data_swzl_wg[0:63]}; +assign ex4_ld_data_wh[0:64] = {1'b0, ex4_ld_data_swzl_wh[0:63]}; +assign ex4_ld_data_wa[113:128] = ex4_ld_data_swzl_wa[112:127]; +assign ex4_ld_data_wb[113:128] = ex4_ld_data_swzl_wb[112:127]; +assign ex4_ld_data_wc[113:128] = ex4_ld_data_swzl_wc[112:127]; +assign ex4_ld_data_wd[113:128] = ex4_ld_data_swzl_wd[112:127]; +assign ex4_ld_data_we[113:128] = ex4_ld_data_swzl_we[112:127]; +assign ex4_ld_data_wf[113:128] = ex4_ld_data_swzl_wf[112:127]; +assign ex4_ld_data_wg[113:128] = ex4_ld_data_swzl_wg[112:127]; +assign ex4_ld_data_wh[113:128] = ex4_ld_data_swzl_wh[112:127]; + +// Sign Extension +generate begin : algExt + genvar b; + for (b = 0; b <= 47; b = b + 1) begin : algExt + assign ex4_ld_data_wa[65 + b] = ex4_ld_data_swzl_wa[64 + b] | ex4_ld_alg_bit_wa[b/8]; + assign ex4_ld_data_wb[65 + b] = ex4_ld_data_swzl_wb[64 + b] | ex4_ld_alg_bit_wb[b/8]; + assign ex4_ld_data_wc[65 + b] = ex4_ld_data_swzl_wc[64 + b] | ex4_ld_alg_bit_wc[b/8]; + assign ex4_ld_data_wd[65 + b] = ex4_ld_data_swzl_wd[64 + b] | ex4_ld_alg_bit_wd[b/8]; + assign ex4_ld_data_we[65 + b] = ex4_ld_data_swzl_we[64 + b] | ex4_ld_alg_bit_we[b/8]; + assign ex4_ld_data_wf[65 + b] = ex4_ld_data_swzl_wf[64 + b] | ex4_ld_alg_bit_wf[b/8]; + assign ex4_ld_data_wg[65 + b] = ex4_ld_data_swzl_wg[64 + b] | ex4_ld_alg_bit_wg[b/8]; + assign ex4_ld_data_wh[65 + b] = ex4_ld_data_swzl_wh[64 + b] | ex4_ld_alg_bit_wh[b/8]; + end +end +endgenerate +// ############################################################################################# + +// ############################################################################################# +// 8 Way Mux Select +// ############################################################################################# +assign ex5_ld_hit_data_d = (ex4_ld_data_wa[(129 - `STQ_DATA_SIZE):128] & {`STQ_DATA_SIZE{ctl_dat_ex4_way_hit[0]}}) | + (ex4_ld_data_wb[(129 - `STQ_DATA_SIZE):128] & {`STQ_DATA_SIZE{ctl_dat_ex4_way_hit[1]}}) | + (ex4_ld_data_wc[(129 - `STQ_DATA_SIZE):128] & {`STQ_DATA_SIZE{ctl_dat_ex4_way_hit[2]}}) | + (ex4_ld_data_wd[(129 - `STQ_DATA_SIZE):128] & {`STQ_DATA_SIZE{ctl_dat_ex4_way_hit[3]}}) | + (ex4_ld_data_we[(129 - `STQ_DATA_SIZE):128] & {`STQ_DATA_SIZE{ctl_dat_ex4_way_hit[4]}}) | + (ex4_ld_data_wf[(129 - `STQ_DATA_SIZE):128] & {`STQ_DATA_SIZE{ctl_dat_ex4_way_hit[5]}}) | + (ex4_ld_data_wg[(129 - `STQ_DATA_SIZE):128] & {`STQ_DATA_SIZE{ctl_dat_ex4_way_hit[6]}}) | + (ex4_ld_data_wh[(129 - `STQ_DATA_SIZE):128] & {`STQ_DATA_SIZE{ctl_dat_ex4_way_hit[7]}}); +// ############################################################################################# + +// ############################################################################################# +// Outputs +// ############################################################################################# +assign ex5_ld_hit_data = ex5_ld_hit_data_q; + +// Read-Modify-Write Path +assign stq6_rd_data_wa = {dcarr_rd_data_wa, dcarr_rd_parity_wa}; +assign stq6_rd_data_wb = {dcarr_rd_data_wb, dcarr_rd_parity_wb}; +assign stq6_rd_data_wc = {dcarr_rd_data_wc, dcarr_rd_parity_wc}; +assign stq6_rd_data_wd = {dcarr_rd_data_wd, dcarr_rd_parity_wd}; +assign stq6_rd_data_we = {dcarr_rd_data_we, dcarr_rd_parity_we}; +assign stq6_rd_data_wf = {dcarr_rd_data_wf, dcarr_rd_parity_wf}; +assign stq6_rd_data_wg = {dcarr_rd_data_wg, dcarr_rd_parity_wg}; +assign stq6_rd_data_wh = {dcarr_rd_data_wh, dcarr_rd_parity_wh}; + +// ############################################################################################# + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Registers +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +tri_regk #(.WIDTH(`STQ_DATA_SIZE), .INIT(0), .NEEDS_SRESET(1)) ex5_ld_hit_data_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_ld_hit_data_reg_offset:ex5_ld_hit_data_reg_offset + `STQ_DATA_SIZE - 1]), + .scout(sov[ex5_ld_hit_data_reg_offset:ex5_ld_hit_data_reg_offset + `STQ_DATA_SIZE - 1]), + .din(ex5_ld_hit_data_d), + .dout(ex5_ld_hit_data_q) +); + +assign siv[0:scan_right] = {sov[1:scan_right], scan_in[0]}; +assign scan_out[0] = sov[0]; + +assign rot_wa_scan_in[0:7] = {rot_wa_scan_out[1:7], scan_in[1]}; +assign rot_wb_scan_in[0:7] = {rot_wb_scan_out[1:7], rot_wa_scan_out[0]}; +assign scan_out[1] = rot_wb_scan_out[0]; + +assign rot_wc_scan_in[0:7] = {rot_wc_scan_out[1:7], scan_in[2]}; +assign rot_wd_scan_in[0:7] = {rot_wd_scan_out[1:7], rot_wc_scan_out[0]}; +assign scan_out[2] = rot_wd_scan_out[0]; + +assign rot_we_scan_in[0:7] = {rot_we_scan_out[1:7], scan_in[3]}; +assign rot_wf_scan_in[0:7] = {rot_wf_scan_out[1:7], rot_we_scan_out[0]}; +assign scan_out[3] = rot_wf_scan_out[0]; + +assign rot_wg_scan_in[0:7] = {rot_wg_scan_out[1:7], scan_in[4]}; +assign rot_wh_scan_in[0:7] = {rot_wh_scan_out[1:7], rot_wg_scan_out[0]}; +assign scan_out[4] = rot_wh_scan_out[0]; + +endmodule diff --git a/dev/verilog/work/lq_data_st.v b/dev/verilog/work/lq_data_st.v new file mode 100755 index 0000000..f00c69f --- /dev/null +++ b/dev/verilog/work/lq_data_st.v @@ -0,0 +1,1228 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +// Description: XU LSU Store Data Rotator Wrapper +// +//***************************************************************************** + +// ########################################################################################## +// VHDL Contents +// 1) 16 Byte Unaligned Rotator +// 2) Little Endian Support for 2,4,8,16 Byte Operations +// 3) Byte Enable Generation +// ########################################################################################## + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" + +module lq_data_st( + ex2_stg_act, + ctl_dat_ex2_eff_addr, + spr_xucr0_dcdis, + lsq_dat_stq1_stg_act, + lsq_dat_stq1_val, + lsq_dat_stq1_mftgpr_val, + lsq_dat_stq1_store_val, + lsq_dat_stq1_byte_en, + lsq_dat_stq1_op_size, + lsq_dat_stq1_le_mode, + lsq_dat_stq1_addr, + lsq_dat_stq2_blk_req, + lsq_dat_rel1_data_val, + lsq_dat_rel1_qw, + lsq_dat_stq2_store_data, + stq6_rd_data_wa, + stq6_rd_data_wb, + stq6_rd_data_wc, + stq6_rd_data_wd, + stq6_rd_data_we, + stq6_rd_data_wf, + stq6_rd_data_wg, + stq6_rd_data_wh, + stq4_rot_data, + dat_lsq_stq4_128data, + stq7_byp_val_wabcd, + stq7_byp_val_wefgh, + stq7_byp_data_wabcd, + stq7_byp_data_wefgh, + stq8_byp_data_wabcd, + stq8_byp_data_wefgh, + stq_byp_val_wabcd, + stq_byp_val_wefgh, + stq4_dcarr_wren, + stq4_dcarr_way_en, + ctl_dat_stq5_way_perr_inval, + dcarr_rd_stg_act, + dcarr_rd_addr, + dcarr_wr_stg_act, + dcarr_wr_way, + dcarr_wr_addr, + dcarr_wr_data_wabcd, + dcarr_wr_data_wefgh, + vdd, + gnd, + nclk, + sg_0, + func_sl_thold_0_b, + func_sl_force, + func_nsl_thold_0_b, + func_nsl_force, + d_mode_dc, + delay_lclkr_dc, + mpw1_dc_b, + mpw2_dc_b, + scan_in, + scan_out +); + +//------------------------------------------------------------------- +// Generics +//------------------------------------------------------------------- +//parameter EXPAND_TYPE = 2; // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) +//parameter GPR_WIDTH_ENC = 6; // Register Mode 5 = 32bit, 6 = 64bit + +// Load Address +input ex2_stg_act; +input [52:59] ctl_dat_ex2_eff_addr; + +// SPR +input spr_xucr0_dcdis; + +//Store/Reload path +input lsq_dat_stq1_stg_act; +input lsq_dat_stq1_val; +input lsq_dat_stq1_mftgpr_val; +input lsq_dat_stq1_store_val; +input [0:15] lsq_dat_stq1_byte_en; +input [0:2] lsq_dat_stq1_op_size; +input lsq_dat_stq1_le_mode; +input [52:63] lsq_dat_stq1_addr; +input lsq_dat_stq2_blk_req; +input lsq_dat_rel1_data_val; +input [57:59] lsq_dat_rel1_qw; +input [0:143] lsq_dat_stq2_store_data; + +// Read-Modify-Write Path Read data +input [0:143] stq6_rd_data_wa; +input [0:143] stq6_rd_data_wb; +input [0:143] stq6_rd_data_wc; +input [0:143] stq6_rd_data_wd; +input [0:143] stq6_rd_data_we; +input [0:143] stq6_rd_data_wf; +input [0:143] stq6_rd_data_wg; +input [0:143] stq6_rd_data_wh; + +// Rotated Data +output [(128-`STQ_DATA_SIZE):127] stq4_rot_data; + +// L2 Store Data +output [0:127] dat_lsq_stq4_128data; + +// EX4 Load Bypass Data for Read/Write Collision detected in EX2 +output [0:3] stq7_byp_val_wabcd; +output [0:3] stq7_byp_val_wefgh; +output [0:143] stq7_byp_data_wabcd; +output [0:143] stq7_byp_data_wefgh; +output [0:143] stq8_byp_data_wabcd; +output [0:143] stq8_byp_data_wefgh; +output [0:3] stq_byp_val_wabcd; +output [0:3] stq_byp_val_wefgh; + +// D$ Array Write Control +input stq4_dcarr_wren; // D$ Array Write Enable +input [0:7] stq4_dcarr_way_en; // D$ Array Way Enable +input [0:7] ctl_dat_stq5_way_perr_inval; + +// D$ Array +output [0:7] dcarr_rd_stg_act; // D$ Array Read ACT +output [52:59] dcarr_rd_addr; // D$ Array Read Address +output [0:7] dcarr_wr_stg_act; // D$ Array Write ACT +output [0:7] dcarr_wr_way; // D$ Array Write Way Write Enable +output [52:59] dcarr_wr_addr; // D$ Array Write Address +output [0:143] dcarr_wr_data_wabcd; // D$ Array Write Data for Way A,B,C,D +output [0:143] dcarr_wr_data_wefgh; // D$ Array Write Data for Way E,F,G,H + +// Pervasive +inout vdd; +inout gnd; +(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) +input [0:`NCLK_WIDTH-1] nclk; +input sg_0; +input func_sl_thold_0_b; +input func_sl_force; +input func_nsl_thold_0_b; +input func_nsl_force; +input d_mode_dc; +input delay_lclkr_dc; +input mpw1_dc_b; +input mpw2_dc_b; +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) +input scan_in; +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) +output scan_out; + +//-------------------------- +// constants +//-------------------------- +parameter stq2_opsize_offset = 0; +parameter stq3_opsize_offset = stq2_opsize_offset + 5; +parameter stq4_rot_data_offset = stq3_opsize_offset + 5; +parameter stq2_le_mode_offset = stq4_rot_data_offset + `STQ_DATA_SIZE; +parameter stq2_mftgpr_val_offset = stq2_le_mode_offset + 1; +parameter stq2_upd_val_offset = stq2_mftgpr_val_offset + 1; +parameter stq3_upd_val_offset = stq2_upd_val_offset + 1; +parameter stq4_upd_val_offset = stq3_upd_val_offset + 1; +parameter stq5_arr_wren_offset = stq4_upd_val_offset + 1; +parameter stq3_blk_req_offset = stq5_arr_wren_offset + 1; +parameter stq2_rot_addr_offset = stq3_blk_req_offset + 1; +parameter stq2_addr_offset = stq2_rot_addr_offset + 5; +parameter stq4_addr_offset = stq2_addr_offset + 8; +parameter rel2_data_val_offset = stq4_addr_offset + 8; +parameter stq4_dcarr_data_offset = rel2_data_val_offset + 1; +parameter stq4_dcarr_par_offset = stq4_dcarr_data_offset + 128; +parameter stq2_byte_en_offset = stq4_dcarr_par_offset + 16; +parameter stq4_byte_en_offset = stq2_byte_en_offset + 16; +parameter stq2_stg_act_offset = stq4_byte_en_offset + 16; +parameter stq3_stg_act_offset = stq2_stg_act_offset + 1; +parameter stq4_stg_act_offset = stq3_stg_act_offset + 1; +parameter stq5_stg_act_offset = stq4_stg_act_offset + 1; + +// start non-scan +parameter stq5_arr_way_en_offset = stq5_stg_act_offset + 1; +parameter stq3_rot_sel1_offset = stq5_arr_way_en_offset + 8; +parameter stq3_rot_sel2_offset = stq3_rot_sel1_offset + 8; +parameter stq3_rot_sel3_offset = stq3_rot_sel2_offset + 8; +parameter stq3_addr_offset = stq3_rot_sel3_offset + 8; +parameter stq5_addr_offset = stq3_addr_offset + 8; +parameter stq5_dcarr_wrt_data_offset = stq5_addr_offset + 8; +parameter stq3_store_rel_data_offset = stq5_dcarr_wrt_data_offset + 144; +parameter stq3_store_rel_par_offset = stq3_store_rel_data_offset + 128; +parameter stq3_byte_en_offset = stq3_store_rel_par_offset + 16; +parameter stq5_byte_en_offset = stq3_byte_en_offset + 16; +parameter scan_right = stq5_byte_en_offset + 16 - 1; + +parameter [0:4] rot_max_size = 5'b10000; + +//-------------------------- +// signals +//-------------------------- +wire [0:127] stq3_rot_data; +wire [0:4] stq2_opsize_d; +wire [0:4] stq2_opsize_q; +wire [0:4] stq3_opsize_d; +wire [0:4] stq3_opsize_q; +wire [0:127] stq3_optype_mask; +wire [0:127] stq3_msk_data; +wire [0:127] stq3_swzl_data; +wire [0:1] rotate_sel1; +wire [0:3] rotate_sel2; +wire [0:3] rotate_sel3; +wire [0:7] stq3_rot_sel1_d; +wire [0:7] stq3_rot_sel1_q; +wire [0:7] stq3_rot_sel2_d; +wire [0:7] stq3_rot_sel2_q; +wire [0:7] stq3_rot_sel3_d; +wire [0:7] stq3_rot_sel3_q; +wire lvl1_sel; +wire [0:1] lvl2_sel; +wire [0:1] lvl3_sel; +wire [52:59] ex2_stq4_rd_addr; +wire ex2_stq4_rd_stg_act; +wire [59:63] stq2_rot_addr_d; +wire [59:63] stq2_rot_addr_q; +wire [52:59] stq2_addr_d; +wire [52:59] stq2_addr_q; +wire [52:59] stq3_addr_d; +wire [52:59] stq3_addr_q; +wire [52:59] stq4_addr_d; +wire [52:59] stq4_addr_q; +wire [52:59] stq5_addr_d; +wire [52:59] stq5_addr_q; +wire [(128-`STQ_DATA_SIZE):127] stq4_rot_data_d; +wire [(128-`STQ_DATA_SIZE):127] stq4_rot_data_q; +wire [0:4] rot_size; +wire [0:4] rot_max_size_le; +wire [0:4] rot_sel_le; +wire [0:4] rot_sel_non_le; +wire [0:3] st_rot_sel; +wire rel2_data_val_d; +wire rel2_data_val_q; +wire [0:4] stq1_op_size; +wire [0:15] stq3_rot_parity; +wire [0:127] stq4_dcarr_data_d; +wire [0:127] stq4_dcarr_data_q; +wire [0:15] stq4_dcarr_par_d; +wire [0:15] stq4_dcarr_par_q; +wire [0:143] stq4_dcarr_wrt_data; +wire [0:143] stq5_dcarr_wrt_data_d; +wire [0:143] stq5_dcarr_wrt_data_q; +wire [0:127] stq4_128data; +wire stq2_le_mode_d; +wire stq2_le_mode_q; +wire stq2_mftgpr_val_d; +wire stq2_mftgpr_val_q; +wire stq2_upd_val_d; +wire stq2_upd_val_q; +wire stq3_upd_val_d; +wire stq3_upd_val_q; +wire stq4_upd_val_d; +wire stq4_upd_val_q; +wire stq5_arr_wren_d; +wire stq5_arr_wren_q; +wire [0:7] stq5_arr_way_en; +wire [0:7] stq5_arr_way_en_d; +wire [0:7] stq5_arr_way_en_q; +wire stq3_blk_req_d; +wire stq3_blk_req_q; +wire [0:127] stq3_store_rel_data_d; +wire [0:127] stq3_store_rel_data_q; +wire [0:15] stq3_store_rel_par_d; +wire [0:15] stq3_store_rel_par_q; +wire [0:15] stq2_byte_en_d; +wire [0:15] stq2_byte_en_q; +wire [0:15] stq3_byte_en_d; +wire [0:15] stq3_byte_en_q; +wire [0:15] stq4_byte_en_d; +wire [0:15] stq4_byte_en_q; +wire [0:15] stq5_byte_en_d; +wire [0:15] stq5_byte_en_q; +wire [0:15] bittype_mask; +wire stq1_stg_act; +wire stq2_stg_act_d; +wire stq2_stg_act_q; +wire stq3_stg_act_d; +wire stq3_stg_act_q; +wire stq4_stg_act_d; +wire stq4_stg_act_q; +wire stq5_stg_act_d; +wire stq5_stg_act_q; +wire rmw_scan_in; +wire rmw_scan_out; + +wire tiup; +wire [0:scan_right] siv; +wire [0:scan_right] sov; +(* analysis_not_referenced="true" *) +wire unused; + +assign unused = rot_sel_le[0] | rot_sel_non_le[0] | |stq3_swzl_data[0:63]; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// ACT's +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +assign stq1_stg_act = lsq_dat_stq1_stg_act; +assign stq2_stg_act_d = stq1_stg_act; +assign stq3_stg_act_d = stq2_stg_act_q; +assign stq4_stg_act_d = stq3_stg_act_q; +assign stq5_stg_act_d = stq4_stg_act_q; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Inputs +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +assign tiup = 1'b1; + +// This signals are not muxed latched, need to latch them only +assign stq1_op_size = (lsq_dat_stq1_op_size == 3'b110) ? 5'b10000 : // 16Bytes + (lsq_dat_stq1_op_size == 3'b101) ? 5'b01000 : // 8Bytes + (lsq_dat_stq1_op_size == 3'b100) ? 5'b00100 : // 4Bytes + (lsq_dat_stq1_op_size == 3'b010) ? 5'b00010 : // 2Bytes + (lsq_dat_stq1_op_size == 3'b001) ? 5'b00001 : // 1Bytes + 5'b00000; + +assign stq2_opsize_d = stq1_op_size; +assign stq3_opsize_d = stq2_opsize_q; +assign stq2_addr_d[52:56] = lsq_dat_stq1_addr[52:56]; + +assign stq2_addr_d[57:59] = (lsq_dat_rel1_data_val == 1'b1) ? lsq_dat_rel1_qw : lsq_dat_stq1_addr[57:59]; + +assign stq2_rot_addr_d = lsq_dat_stq1_addr[59:63]; +assign stq3_addr_d = stq2_addr_q; +assign stq4_addr_d = stq3_addr_q; +assign stq5_addr_d = stq4_addr_q; +assign stq2_le_mode_d = lsq_dat_stq1_le_mode; +assign stq2_mftgpr_val_d = lsq_dat_stq1_mftgpr_val & lsq_dat_stq1_val; +assign stq2_upd_val_d = (lsq_dat_stq1_store_val & lsq_dat_stq1_val); +assign stq3_upd_val_d = stq2_upd_val_q; +assign stq4_upd_val_d = stq3_upd_val_q & (~stq3_blk_req_q); +assign stq5_arr_wren_d = stq4_dcarr_wren & ~spr_xucr0_dcdis; +assign stq5_arr_way_en_d = stq4_dcarr_way_en; +assign stq5_arr_way_en = stq5_arr_way_en_q & ~ctl_dat_stq5_way_perr_inval; +assign stq2_byte_en_d = lsq_dat_stq1_byte_en; +assign stq3_byte_en_d = stq2_byte_en_q | {16{rel2_data_val_q}}; +assign stq4_byte_en_d = stq3_byte_en_q; +assign stq5_byte_en_d = stq4_byte_en_q; +assign stq3_blk_req_d = lsq_dat_stq2_blk_req; +assign rel2_data_val_d = lsq_dat_rel1_data_val; + +// ############################################################################################# +// Select between different Operations +// ############################################################################################# +assign ex2_stq4_rd_addr = ~stq4_upd_val_q ? ctl_dat_ex2_eff_addr : stq4_addr_q; +assign ex2_stq4_rd_stg_act = (ex2_stg_act | stq4_upd_val_q) & ~spr_xucr0_dcdis; + +// ############################################################################################# +// Create Rotate Select +// ############################################################################################# + +// Store/Reload Pipe Rotator Control Calculations +assign rot_size = stq2_rot_addr_q + stq2_opsize_q; +assign rot_max_size_le = rot_max_size | stq2_opsize_q; +assign rot_sel_le = rot_max_size_le - rot_size; +assign rot_sel_non_le = rot_max_size - rot_size; + +// STORE PATH LITTLE ENDIAN ROTATOR SELECT CALCULATION +// st_rot_size = rot_addr + op_size +// st_rot_sel = (rot_max_size or le_op_size) - rot_size + +// Little Endian Support Store Data Rotate Select +assign st_rot_sel = (stq2_le_mode_q == 1'b1) ? rot_sel_le[1:4] : + rot_sel_non_le[1:4]; + +// ############################################################################################# +// 1-hot Rotate Select +// ############################################################################################# + +assign lvl1_sel = stq2_le_mode_q & (~(stq2_mftgpr_val_q | rel2_data_val_q)); +assign lvl2_sel = st_rot_sel[0:1] & {2{~(stq2_mftgpr_val_q | rel2_data_val_q)}}; +assign lvl3_sel = st_rot_sel[2:3] & {2{~(stq2_mftgpr_val_q | rel2_data_val_q)}}; + +assign rotate_sel1 = (lvl1_sel == 1'b0) ? 2'b10 : + 2'b01; + +assign rotate_sel2 = (lvl2_sel == 2'b00) ? 4'b1000 : + (lvl2_sel == 2'b01) ? 4'b0100 : + (lvl2_sel == 2'b10) ? 4'b0010 : + 4'b0001; + +assign rotate_sel3 = (lvl3_sel == 2'b00) ? 4'b1000 : + (lvl3_sel == 2'b01) ? 4'b0100 : + (lvl3_sel == 2'b10) ? 4'b0010 : + 4'b0001; + +assign stq3_rot_sel1_d = {rotate_sel1, rotate_sel1, rotate_sel1, rotate_sel1}; +assign stq3_rot_sel2_d = {rotate_sel2, rotate_sel2}; +assign stq3_rot_sel3_d = {rotate_sel3, rotate_sel3}; + +// ############################################################################################# +// Select Between Reload Critical Quadword and Store Data Path +// ############################################################################################# + +// Parity Bits +assign stq3_store_rel_par_d = lsq_dat_stq2_store_data[128:143]; + +// Swizzle Rotate Data +generate begin : swzlSTData + genvar t; + for (t = 0; t <= 7; t = t + 1) begin : swzlSTData + assign stq3_store_rel_data_d[t * 16:(t * 16) + 15] = {lsq_dat_stq2_store_data[t + 0], + lsq_dat_stq2_store_data[t + 8], + lsq_dat_stq2_store_data[t + 16], + lsq_dat_stq2_store_data[t + 24], + lsq_dat_stq2_store_data[t + 32], + lsq_dat_stq2_store_data[t + 40], + lsq_dat_stq2_store_data[t + 48], + lsq_dat_stq2_store_data[t + 56], + lsq_dat_stq2_store_data[t + 64], + lsq_dat_stq2_store_data[t + 72], + lsq_dat_stq2_store_data[t + 80], + lsq_dat_stq2_store_data[t + 88], + lsq_dat_stq2_store_data[t + 96], + lsq_dat_stq2_store_data[t + 104], + lsq_dat_stq2_store_data[t + 112], + lsq_dat_stq2_store_data[t + 120]}; + end +end +endgenerate + +// ############################################################################################# +// 16 Byte Store Rotator +// ############################################################################################# + +// Store Data Rotate +generate begin : l1dcrotl + genvar b; + for (b = 0; b <= 7; b = b + 1) begin : l1dcrotl + tri_rot16_lu drotl( + + // Rotator Controls and Data + .rot_sel1(stq3_rot_sel1_q), + .rot_sel2(stq3_rot_sel2_q), + .rot_sel3(stq3_rot_sel3_q), + .rot_data(stq3_store_rel_data_q[b * 16:(b * 16) + 15]), + + // Rotated Data + .data_rot(stq3_rot_data[b * 16:(b * 16) + 15]), + + // Pervasive + .vdd(vdd), + .gnd(gnd) + ); + end +end +endgenerate + +// Parity Rotate + +tri_rot16_lu protl( + + // Rotator Controls and Data + .rot_sel1(stq3_rot_sel1_q), + .rot_sel2(stq3_rot_sel2_q), + .rot_sel3(stq3_rot_sel3_q), + .rot_data(stq3_store_rel_par_q), + + // Rotated Data + .data_rot(stq3_rot_parity), + + // Pervasive + .vdd(vdd), + .gnd(gnd) +); + +// Mux removed since we are gating the rotator controls when operation is a reload +// this causes the data to be passed through +// Data written to D$ Array +assign stq4_dcarr_data_d = stq3_rot_data; +assign stq4_dcarr_par_d = stq3_rot_parity; +assign stq4_dcarr_wrt_data = {stq4_dcarr_data_q, stq4_dcarr_par_q}; +assign stq5_dcarr_wrt_data_d = stq4_dcarr_wrt_data; + +// ############################################################################################# +// Read Modify Write +// ############################################################################################# +tri_lq_rmw rmw( + .ex2_stq4_rd_stg_act(ex2_stq4_rd_stg_act), + .ex2_stq4_rd_addr(ex2_stq4_rd_addr), + .stq6_rd_data_wa(stq6_rd_data_wa), + .stq6_rd_data_wb(stq6_rd_data_wb), + .stq6_rd_data_wc(stq6_rd_data_wc), + .stq6_rd_data_wd(stq6_rd_data_wd), + .stq6_rd_data_we(stq6_rd_data_we), + .stq6_rd_data_wf(stq6_rd_data_wf), + .stq6_rd_data_wg(stq6_rd_data_wg), + .stq6_rd_data_wh(stq6_rd_data_wh), + .stq5_stg_act(stq5_stg_act_q), + .stq5_arr_wren(stq5_arr_wren_q), + .stq5_arr_wr_way(stq5_arr_way_en), + .stq5_arr_wr_addr(stq5_addr_q), + .stq5_arr_wr_bytew(stq5_byte_en_q), + .stq5_arr_wr_data(stq5_dcarr_wrt_data_q), + .stq7_byp_val_wabcd(stq7_byp_val_wabcd), + .stq7_byp_val_wefgh(stq7_byp_val_wefgh), + .stq7_byp_data_wabcd(stq7_byp_data_wabcd), + .stq7_byp_data_wefgh(stq7_byp_data_wefgh), + .stq8_byp_data_wabcd(stq8_byp_data_wabcd), + .stq8_byp_data_wefgh(stq8_byp_data_wefgh), + .stq_byp_val_wabcd(stq_byp_val_wabcd), + .stq_byp_val_wefgh(stq_byp_val_wefgh), + .dcarr_rd_stg_act(dcarr_rd_stg_act), + .dcarr_wr_stg_act(dcarr_wr_stg_act), + .dcarr_wr_way(dcarr_wr_way), + .dcarr_wr_addr(dcarr_wr_addr), + .dcarr_wr_data_wabcd(dcarr_wr_data_wabcd), + .dcarr_wr_data_wefgh(dcarr_wr_data_wefgh), + .nclk(nclk), + .vdd(vdd), + .gnd(gnd), + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .func_sl_force(func_sl_force), + .func_sl_thold_0_b(func_sl_thold_0_b), + .sg_0(sg_0), + .scan_in(rmw_scan_in), + .scan_out(rmw_scan_out) +); + +// ############################################################################################# +// Op Size Mask Generation for Reloads +// ############################################################################################# + +// STQ Bit Mask Generation +assign bittype_mask = (16'h0001 & {16{stq3_opsize_q[4]}}) | (16'h0003 & {16{stq3_opsize_q[3]}}) | + (16'h000F & {16{stq3_opsize_q[2]}}) | (16'h00FF & {16{stq3_opsize_q[1]}}) | + (16'hFFFF & {16{stq3_opsize_q[0]}}); + +generate begin : maskGen + genvar b; + for (b = 0; b <= 7; b = b + 1) + begin : maskGen + assign stq3_optype_mask[b * 16:(b * 16) + 15] = bittype_mask; + end +end +endgenerate + +assign stq3_msk_data = stq3_rot_data & stq3_optype_mask; + +// Swizzle Data to a proper format +generate begin : swzlData + genvar t; + for (t = 0; t <= 15; t = t + 1) + begin : swzlData + assign stq3_swzl_data[t * 8:(t * 8) + 7] = {stq3_msk_data[t], + stq3_msk_data[t + 16], + stq3_msk_data[t + 32], + stq3_msk_data[t + 48], + stq3_msk_data[t + 64], + stq3_msk_data[t + 80], + stq3_msk_data[t + 96], + stq3_msk_data[t + 112]}; + + assign stq4_128data[t * 8:(t * 8) + 7] = {stq4_dcarr_data_q[t], + stq4_dcarr_data_q[t + 16], + stq4_dcarr_data_q[t + 32], + stq4_dcarr_data_q[t + 48], + stq4_dcarr_data_q[t + 64], + stq4_dcarr_data_q[t + 80], + stq4_dcarr_data_q[t + 96], + stq4_dcarr_data_q[t + 112]}; + end +end +endgenerate + +assign stq4_rot_data_d = stq3_swzl_data[(128 - `STQ_DATA_SIZE):127]; + +// ############################################################################################# +// Outputs +// ############################################################################################# + +assign dcarr_rd_addr = ex2_stq4_rd_addr; +assign dat_lsq_stq4_128data = stq4_128data; +assign stq4_rot_data = stq4_rot_data_q; + +// ############################################################################################# +// Registers +// ############################################################################################# +tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) stq2_opsize_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq1_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq2_opsize_offset:stq2_opsize_offset + 5 - 1]), + .scout(sov[stq2_opsize_offset:stq2_opsize_offset + 5 - 1]), + .din(stq2_opsize_d), + .dout(stq2_opsize_q) +); + +tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) stq3_opsize_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq2_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq3_opsize_offset:stq3_opsize_offset + 5 - 1]), + .scout(sov[stq3_opsize_offset:stq3_opsize_offset + 5 - 1]), + .din(stq3_opsize_d), + .dout(stq3_opsize_q) +); + +tri_rlmreg_p #(.WIDTH(`STQ_DATA_SIZE), .INIT(0), .NEEDS_SRESET(1)) stq4_rot_data_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq4_rot_data_offset:stq4_rot_data_offset + `STQ_DATA_SIZE - 1]), + .scout(sov[stq4_rot_data_offset:stq4_rot_data_offset + `STQ_DATA_SIZE - 1]), + .din(stq4_rot_data_d), + .dout(stq4_rot_data_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_le_mode_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq1_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq2_le_mode_offset]), + .scout(sov[stq2_le_mode_offset]), + .din(stq2_le_mode_d), + .dout(stq2_le_mode_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_mftgpr_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq2_mftgpr_val_offset]), + .scout(sov[stq2_mftgpr_val_offset]), + .din(stq2_mftgpr_val_d), + .dout(stq2_mftgpr_val_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_upd_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq2_upd_val_offset]), + .scout(sov[stq2_upd_val_offset]), + .din(stq2_upd_val_d), + .dout(stq2_upd_val_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq3_upd_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq3_upd_val_offset]), + .scout(sov[stq3_upd_val_offset]), + .din(stq3_upd_val_d), + .dout(stq3_upd_val_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_upd_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq4_upd_val_offset]), + .scout(sov[stq4_upd_val_offset]), + .din(stq4_upd_val_d), + .dout(stq4_upd_val_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq5_arr_wren_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq5_arr_wren_offset]), + .scout(sov[stq5_arr_wren_offset]), + .din(stq5_arr_wren_d), + .dout(stq5_arr_wren_q) +); + +tri_regk #(.WIDTH(8), .INIT(170), .NEEDS_SRESET(1)) stq5_arr_way_en_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq4_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[stq5_arr_way_en_offset:stq5_arr_way_en_offset+8-1]), + .scout(sov[stq5_arr_way_en_offset:stq5_arr_way_en_offset+8-1]), + .din(stq5_arr_way_en_d), + .dout(stq5_arr_way_en_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq3_blk_req_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq3_blk_req_offset]), + .scout(sov[stq3_blk_req_offset]), + .din(stq3_blk_req_d), + .dout(stq3_blk_req_q) +); + +tri_regk #(.WIDTH(8), .INIT(170), .NEEDS_SRESET(1)) stq3_rot_sel1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[stq3_rot_sel1_offset:stq3_rot_sel1_offset+8-1]), + .scout(sov[stq3_rot_sel1_offset:stq3_rot_sel1_offset+8-1]), + .din(stq3_rot_sel1_d), + .dout(stq3_rot_sel1_q) +); + +tri_regk #(.WIDTH(8), .INIT(136), .NEEDS_SRESET(1)) stq3_rot_sel2_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[stq3_rot_sel2_offset:stq3_rot_sel2_offset+8-1]), + .scout(sov[stq3_rot_sel2_offset:stq3_rot_sel2_offset+8-1]), + .din(stq3_rot_sel2_d), + .dout(stq3_rot_sel2_q) +); + +tri_regk #(.WIDTH(8), .INIT(136), .NEEDS_SRESET(1)) stq3_rot_sel3_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[stq3_rot_sel3_offset:stq3_rot_sel3_offset+8-1]), + .scout(sov[stq3_rot_sel3_offset:stq3_rot_sel3_offset+8-1]), + .din(stq3_rot_sel3_d), + .dout(stq3_rot_sel3_q) +); + +tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) stq2_rot_addr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq1_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq2_rot_addr_offset:stq2_rot_addr_offset + 5 - 1]), + .scout(sov[stq2_rot_addr_offset:stq2_rot_addr_offset + 5 - 1]), + .din(stq2_rot_addr_d), + .dout(stq2_rot_addr_q) +); + +tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) stq2_addr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq1_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq2_addr_offset:stq2_addr_offset + 8 - 1]), + .scout(sov[stq2_addr_offset:stq2_addr_offset + 8 - 1]), + .din(stq2_addr_d), + .dout(stq2_addr_q) +); + +tri_regk #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) stq3_addr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[stq3_addr_offset:stq3_addr_offset+8-1]), + .scout(sov[stq3_addr_offset:stq3_addr_offset+8-1]), + .din(stq3_addr_d), + .dout(stq3_addr_q) +); + +tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) stq4_addr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq4_addr_offset:stq4_addr_offset + 8 - 1]), + .scout(sov[stq4_addr_offset:stq4_addr_offset + 8 - 1]), + .din(stq4_addr_d), + .dout(stq4_addr_q) +); + +tri_regk #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) stq5_addr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq4_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[stq5_addr_offset:stq5_addr_offset+8-1]), + .scout(sov[stq5_addr_offset:stq5_addr_offset+8-1]), + .din(stq5_addr_d), + .dout(stq5_addr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel2_data_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rel2_data_val_offset]), + .scout(sov[rel2_data_val_offset]), + .din(rel2_data_val_d), + .dout(rel2_data_val_q) +); + +tri_rlmreg_p #(.WIDTH(128), .INIT(0), .NEEDS_SRESET(1)) stq4_dcarr_data_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq4_dcarr_data_offset:stq4_dcarr_data_offset + 128 - 1]), + .scout(sov[stq4_dcarr_data_offset:stq4_dcarr_data_offset + 128 - 1]), + .din(stq4_dcarr_data_d), + .dout(stq4_dcarr_data_q) +); + +tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) stq4_dcarr_par_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq4_dcarr_par_offset:stq4_dcarr_par_offset + 16 - 1]), + .scout(sov[stq4_dcarr_par_offset:stq4_dcarr_par_offset + 16 - 1]), + .din(stq4_dcarr_par_d), + .dout(stq4_dcarr_par_q) +); + +tri_regk #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq5_dcarr_wrt_data_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq4_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[stq5_dcarr_wrt_data_offset:stq5_dcarr_wrt_data_offset+144-1]), + .scout(sov[stq5_dcarr_wrt_data_offset:stq5_dcarr_wrt_data_offset+144-1]), + .din(stq5_dcarr_wrt_data_d), + .dout(stq5_dcarr_wrt_data_q) +); + +tri_regk #(.WIDTH(128), .INIT(0), .NEEDS_SRESET(1)) stq3_store_rel_data_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[stq3_store_rel_data_offset:stq3_store_rel_data_offset+128-1]), + .scout(sov[stq3_store_rel_data_offset:stq3_store_rel_data_offset+128-1]), + .din(stq3_store_rel_data_d), + .dout(stq3_store_rel_data_q) +); + +tri_regk #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) stq3_store_rel_par_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[stq3_store_rel_par_offset:stq3_store_rel_par_offset+16-1]), + .scout(sov[stq3_store_rel_par_offset:stq3_store_rel_par_offset+16-1]), + .din(stq3_store_rel_par_d), + .dout(stq3_store_rel_par_q) +); + +tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) stq2_byte_en_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq1_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq2_byte_en_offset:stq2_byte_en_offset + 16 - 1]), + .scout(sov[stq2_byte_en_offset:stq2_byte_en_offset + 16 - 1]), + .din(stq2_byte_en_d), + .dout(stq2_byte_en_q) +); + +tri_regk #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) stq3_byte_en_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[stq3_byte_en_offset:stq3_byte_en_offset+16-1]), + .scout(sov[stq3_byte_en_offset:stq3_byte_en_offset+16-1]), + .din(stq3_byte_en_d), + .dout(stq3_byte_en_q) +); + +tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) stq4_byte_en_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq4_byte_en_offset:stq4_byte_en_offset + 16 - 1]), + .scout(sov[stq4_byte_en_offset:stq4_byte_en_offset + 16 - 1]), + .din(stq4_byte_en_d), + .dout(stq4_byte_en_q) +); + +tri_regk #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) stq5_byte_en_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq4_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[stq5_byte_en_offset:stq5_byte_en_offset+16-1]), + .scout(sov[stq5_byte_en_offset:stq5_byte_en_offset+16-1]), + .din(stq5_byte_en_d), + .dout(stq5_byte_en_q) +); + +//------------------------------------ +// ACTs +//------------------------------------ + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_stg_act_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq2_stg_act_offset]), + .scout(sov[stq2_stg_act_offset]), + .din(stq2_stg_act_d), + .dout(stq2_stg_act_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq3_stg_act_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq3_stg_act_offset]), + .scout(sov[stq3_stg_act_offset]), + .din(stq3_stg_act_d), + .dout(stq3_stg_act_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_stg_act_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq4_stg_act_offset]), + .scout(sov[stq4_stg_act_offset]), + .din(stq4_stg_act_d), + .dout(stq4_stg_act_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq5_stg_act_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq5_stg_act_offset]), + .scout(sov[stq5_stg_act_offset]), + .din(stq5_stg_act_d), + .dout(stq5_stg_act_q) +); + +assign rmw_scan_in = scan_in; +assign siv[0:scan_right] = {sov[1:scan_right], rmw_scan_out}; +assign scan_out = sov[0]; + +endmodule diff --git a/dev/verilog/work/lq_dcc.v b/dev/verilog/work/lq_dcc.v new file mode 100755 index 0000000..a342067 --- /dev/null +++ b/dev/verilog/work/lq_dcc.v @@ -0,0 +1,12475 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +// Description: XU LSU L1 Data Cache Control +// +//***************************************************************************** + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" + +module lq_dcc( + rv_lq_rv1_i0_vld, + rv_lq_rv1_i0_ucode_preissue, + rv_lq_rv1_i0_2ucode, + rv_lq_rv1_i0_ucode_cnt, + rv_lq_rv1_i1_vld, + rv_lq_rv1_i1_ucode_preissue, + rv_lq_rv1_i1_2ucode, + rv_lq_rv1_i1_ucode_cnt, + dec_dcc_ex0_act, + dec_dcc_ex1_cmd_act, + dec_dcc_ex1_ucode_val, + dec_dcc_ex1_ucode_cnt, + dec_dcc_ex1_ucode_op, + dec_dcc_ex1_sfx_val, + dec_dcc_ex1_axu_op_val, + dec_dcc_ex1_axu_falign, + dec_dcc_ex1_axu_fexcpt, + dec_dcc_ex1_axu_instr_type, + dec_dcc_ex1_cache_acc, + dec_dcc_ex1_thrd_id, + dec_dcc_ex1_instr, + dec_dcc_ex1_optype1, + dec_dcc_ex1_optype2, + dec_dcc_ex1_optype4, + dec_dcc_ex1_optype8, + dec_dcc_ex1_optype16, + dec_dcc_ex1_target_gpr, + dec_dcc_ex1_mtspr_trace, + dec_dcc_ex1_load_instr, + dec_dcc_ex1_store_instr, + dec_dcc_ex1_dcbf_instr, + dec_dcc_ex1_sync_instr, + dec_dcc_ex1_l_fld, + dec_dcc_ex1_dcbi_instr, + dec_dcc_ex1_dcbz_instr, + dec_dcc_ex1_dcbt_instr, + dec_dcc_ex1_pfetch_val, + dec_dcc_ex1_dcbtst_instr, + dec_dcc_ex1_th_fld, + dec_dcc_ex1_dcbtls_instr, + dec_dcc_ex1_dcbtstls_instr, + dec_dcc_ex1_dcblc_instr, + dec_dcc_ex1_dcbst_instr, + dec_dcc_ex1_icbi_instr, + dec_dcc_ex1_icblc_instr, + dec_dcc_ex1_icbt_instr, + dec_dcc_ex1_icbtls_instr, + dec_dcc_ex1_icswx_instr, + dec_dcc_ex1_icswxdot_instr, + dec_dcc_ex1_icswx_epid, + dec_dcc_ex1_tlbsync_instr, + dec_dcc_ex1_ldawx_instr, + dec_dcc_ex1_wclr_instr, + dec_dcc_ex1_wchk_instr, + dec_dcc_ex1_resv_instr, + dec_dcc_ex1_mutex_hint, + dec_dcc_ex1_mbar_instr, + dec_dcc_ex1_makeitso_instr, + dec_dcc_ex1_is_msgsnd, + dec_dcc_ex1_dci_instr, + dec_dcc_ex1_ici_instr, + dec_dcc_ex1_mword_instr, + dec_dcc_ex1_algebraic, + dec_dcc_ex1_strg_index, + dec_dcc_ex1_src_gpr, + dec_dcc_ex1_src_axu, + dec_dcc_ex1_src_dp, + dec_dcc_ex1_targ_gpr, + dec_dcc_ex1_targ_axu, + dec_dcc_ex1_targ_dp, + dec_dcc_ex1_upd_form, + dec_dcc_ex1_itag, + dec_dcc_ex1_cr_fld, + dec_dcc_ex1_expt_det, + dec_dcc_ex1_priv_prog, + dec_dcc_ex1_hypv_prog, + dec_dcc_ex1_illeg_prog, + dec_dcc_ex1_dlock_excp, + dec_dcc_ex1_ilock_excp, + dec_dcc_ex1_ehpriv_excp, + dec_dcc_ex2_is_any_load_dac, + dec_dcc_ex5_req_abort_rpt, + dec_dcc_ex5_axu_abort_rpt, + dir_dcc_ex2_eff_addr, + lsq_ctl_rv0_back_inv, + derat_rv1_snoop_val, + dir_dcc_ex4_way_tag_a, + dir_dcc_ex4_way_tag_b, + dir_dcc_ex4_way_tag_c, + dir_dcc_ex4_way_tag_d, + dir_dcc_ex4_way_tag_e, + dir_dcc_ex4_way_tag_f, + dir_dcc_ex4_way_tag_g, + dir_dcc_ex4_way_tag_h, + dir_dcc_ex4_way_par_a, + dir_dcc_ex4_way_par_b, + dir_dcc_ex4_way_par_c, + dir_dcc_ex4_way_par_d, + dir_dcc_ex4_way_par_e, + dir_dcc_ex4_way_par_f, + dir_dcc_ex4_way_par_g, + dir_dcc_ex4_way_par_h, + dir_dcc_ex5_way_a_dir, + dir_dcc_ex5_way_b_dir, + dir_dcc_ex5_way_c_dir, + dir_dcc_ex5_way_d_dir, + dir_dcc_ex5_way_e_dir, + dir_dcc_ex5_way_f_dir, + dir_dcc_ex5_way_g_dir, + dir_dcc_ex5_way_h_dir, + dir_dcc_ex5_dir_lru, + derat_dcc_ex3_wimge_e, + derat_dcc_ex3_itagHit, + derat_dcc_ex4_wimge, + derat_dcc_ex4_usr_bits, + derat_dcc_ex4_wlc, + derat_dcc_ex4_p_addr, + derat_dcc_ex4_noop_touch, + derat_dcc_ex4_miss, + derat_dcc_ex4_tlb_err, + derat_dcc_ex4_dsi, + derat_dcc_ex4_vf, + derat_dcc_ex4_multihit_err_det, + derat_dcc_ex4_par_err_det, + derat_dcc_ex4_multihit_err_flush, + derat_dcc_ex4_par_err_flush, + derat_dcc_ex4_tlb_inelig, + derat_dcc_ex4_pt_fault, + derat_dcc_ex4_lrat_miss, + derat_dcc_ex4_tlb_multihit, + derat_dcc_ex4_tlb_par_err, + derat_dcc_ex4_lru_par_err, + derat_fir_par_err, + derat_fir_multihit, + derat_dcc_ex4_restart, + derat_dcc_ex4_setHold, + derat_dcc_clr_hold, + derat_dcc_emq_idle, + spr_dcc_ex4_dvc1_en, + spr_dcc_ex4_dvc2_en, + spr_dcc_ex4_dacrw1_cmpr, + spr_dcc_ex4_dacrw2_cmpr, + spr_dcc_ex4_dacrw3_cmpr, + spr_dcc_ex4_dacrw4_cmpr, + spr_dcc_spr_lesr, + dir_dcc_ex4_hit, + dir_dcc_ex4_miss, + dir_dcc_ex4_set_rel_coll, + dir_dcc_ex4_byp_restart, + dir_dcc_ex5_dir_perr_det, + dir_dcc_ex5_dc_perr_det, + dir_dcc_ex5_dir_perr_flush, + dir_dcc_ex5_dc_perr_flush, + dir_dcc_ex5_multihit_det, + dir_dcc_ex5_multihit_flush, + dir_dcc_stq4_dir_perr_det, + dir_dcc_stq4_multihit_det, + dir_dcc_ex5_stp_flush, + iu_lq_cp_flush, + iu_lq_recirc_val, + iu_lq_cp_next_itag, + xu_lq_xer_cp_rd, + fgen_ex1_stg_flush, + fgen_ex2_stg_flush, + fgen_ex3_stg_flush, + fgen_ex4_cp_flush, + fgen_ex4_stg_flush, + fgen_ex5_stg_flush, + dir_dcc_rel3_dcarr_upd, + xu_lq_spr_ccr2_en_trace, + xu_lq_spr_ccr2_dfrat, + xu_lq_spr_ccr2_ap, + xu_lq_spr_ccr2_ucode_dis, + xu_lq_spr_ccr2_notlb, + xu_lq_spr_xucr0_clkg_ctl, + xu_lq_spr_xucr0_wlk, + xu_lq_spr_xucr0_mbar_ack, + xu_lq_spr_xucr0_tlbsync, + xu_lq_spr_xucr0_dcdis, + xu_lq_spr_xucr0_aflsta, + xu_lq_spr_xucr0_flsta, + xu_lq_spr_xucr0_trace_um, + xu_lq_spr_xucr0_mddp, + xu_lq_spr_xucr0_mdcp, + xu_lq_spr_xucr4_mmu_mchk, + xu_lq_spr_xucr4_mddmh, + xu_lq_spr_msr_cm, + xu_lq_spr_msr_fp, + xu_lq_spr_msr_spv, + xu_lq_spr_msr_de, + xu_lq_spr_dbcr0_idm, + xu_lq_spr_epcr_duvd, + xu_lq_spr_msr_gs, + xu_lq_spr_msr_pr, + xu_lq_spr_msr_ds, + mm_lq_lsu_lpidr, + mm_lq_pid, + lsq_ctl_ex5_ldq_restart, + lsq_ctl_ex5_stq_restart, + lsq_ctl_ex5_stq_restart_miss, + lsq_ctl_ex5_fwd_val, + lsq_ctl_sync_in_stq, + lsq_ctl_rv_hold_all, + lsq_ctl_rv_set_hold, + lsq_ctl_rv_clr_hold, + lsq_ctl_stq1_stg_act, + lsq_ctl_stq1_val, + lsq_ctl_stq1_thrd_id, + lsq_ctl_stq1_store_val, + lsq_ctl_stq1_watch_clr, + lsq_ctl_stq1_l_fld, + lsq_ctl_stq1_resv, + lsq_ctl_stq1_ci, + lsq_ctl_stq1_axu_val, + lsq_ctl_stq1_epid_val, + lsq_ctl_stq1_mftgpr_val, + lsq_ctl_stq1_mfdpf_val, + lsq_ctl_stq1_mfdpa_val, + lsq_ctl_stq2_blk_req, + lsq_ctl_stq4_xucr0_cul, + lsq_ctl_stq5_itag, + lsq_ctl_stq5_tgpr, + lsq_ctl_rel1_gpr_val, + lsq_ctl_rel1_ta_gpr, + lsq_ctl_rel1_upd_gpr, + lsq_ctl_stq_cpl_ready, + lsq_ctl_stq_cpl_ready_itag, + lsq_ctl_stq_cpl_ready_tid, + lsq_ctl_stq_n_flush, + lsq_ctl_stq_np1_flush, + lsq_ctl_stq_exception_val, + lsq_ctl_stq_exception, + lsq_ctl_stq_dacrw, + ctl_lsq_stq_cpl_blk, + lsq_ctl_ex3_strg_val, + lsq_ctl_ex3_strg_noop, + lsq_ctl_ex3_illeg_lswx, + lsq_ctl_ex3_ct_val, + lsq_ctl_ex3_be_ct, + lsq_ctl_ex3_le_ct, + dir_dcc_stq3_hit, + dir_dcc_ex5_cr_rslt, + dcc_dir_ex2_frc_align2, + dcc_dir_ex2_frc_align4, + dcc_dir_ex2_frc_align8, + dcc_dir_ex2_frc_align16, + dcc_dir_ex2_64bit_agen, + dcc_dir_ex2_thrd_id, + dcc_derat_ex3_strg_noop, + dcc_derat_ex5_blk_tlb_req, + dcc_derat_ex6_cplt, + dcc_derat_ex6_cplt_itag, + dcc_dir_ex3_lru_upd, + dcc_dir_ex3_cache_acc, + dcc_dir_ex3_pfetch_val, + dcc_dir_ex3_lock_set, + dcc_dir_ex3_th_c, + dcc_dir_ex3_watch_set, + dcc_dir_ex3_larx_val, + dcc_dir_ex3_watch_chk, + dcc_dir_ex3_ddir_acc, + dcc_dir_ex4_load_val, + dcc_spr_ex3_data_val, + dcc_spr_ex3_eff_addr, + ctl_dat_ex3_opsize, + ctl_dat_ex3_le_mode, + ctl_dat_ex3_le_ld_rotsel, + ctl_dat_ex3_be_ld_rotsel, + ctl_dat_ex3_algebraic, + ctl_dat_ex3_le_alg_rotsel, + dcc_byp_rel2_stg_act, + dcc_byp_rel3_stg_act, + dcc_byp_ram_act, + byp_dcc_ex2_req_aborted, + dcc_byp_ex4_moveOp_val, + dcc_byp_stq6_moveOp_val, + dcc_byp_ex4_move_data, + dcc_byp_ex5_lq_req_abort, + dcc_byp_ex5_byte_mask, + dcc_byp_ex6_thrd_id, + dcc_byp_ex6_dvc1_en, + dcc_byp_ex6_dvc2_en, + dcc_byp_ex6_dacr_cmpr, + dcc_dir_ex4_p_addr, + dcc_dir_stq6_store_val, + ctl_lsq_ex2_streq_val, + ctl_lsq_ex2_itag, + ctl_lsq_ex2_thrd_id, + ctl_lsq_ex3_ldreq_val, + ctl_lsq_ex3_wchkall_val, + ctl_lsq_ex3_pfetch_val, + ctl_lsq_ex3_byte_en, + ctl_lsq_ex3_p_addr, + ctl_lsq_ex3_thrd_id, + ctl_lsq_ex3_algebraic, + ctl_lsq_ex3_opsize, + ctl_lsq_ex4_ldreq_val, + ctl_lsq_ex4_binvreq_val, + ctl_lsq_ex4_streq_val, + ctl_lsq_ex4_othreq_val, + ctl_lsq_ex4_p_addr, + ctl_lsq_ex4_dReq_val, + ctl_lsq_ex4_gath_load, + ctl_lsq_ex4_send_l2, + ctl_lsq_ex4_has_data, + ctl_lsq_ex4_cline_chk, + ctl_lsq_ex4_wimge, + ctl_lsq_ex4_byte_swap, + ctl_lsq_ex4_is_sync, + ctl_lsq_ex4_all_thrd_chk, + ctl_lsq_ex4_is_store, + ctl_lsq_ex4_is_resv, + ctl_lsq_ex4_is_mfgpr, + ctl_lsq_ex4_is_icswxr, + ctl_lsq_ex4_is_icbi, + ctl_lsq_ex4_watch_clr, + ctl_lsq_ex4_watch_clr_all, + ctl_lsq_ex4_mtspr_trace, + ctl_lsq_ex4_is_inval_op, + ctl_lsq_ex4_is_cinval, + ctl_lsq_ex5_lock_clr, + ctl_lsq_ex5_lock_set, + ctl_lsq_ex5_watch_set, + ctl_lsq_ex5_tgpr, + ctl_lsq_ex5_axu_val, + ctl_lsq_ex5_is_epid, + ctl_lsq_ex5_usr_def, + ctl_lsq_ex5_drop_rel, + ctl_lsq_ex5_flush_req, + ctl_lsq_ex5_flush_pfetch, + ctl_lsq_ex5_cmmt_events, + ctl_lsq_ex5_perf_val0, + ctl_lsq_ex5_perf_sel0, + ctl_lsq_ex5_perf_val1, + ctl_lsq_ex5_perf_sel1, + ctl_lsq_ex5_perf_val2, + ctl_lsq_ex5_perf_sel2, + ctl_lsq_ex5_perf_val3, + ctl_lsq_ex5_perf_sel3, + ctl_lsq_ex5_not_touch, + ctl_lsq_ex5_class_id, + ctl_lsq_ex5_dvc, + ctl_lsq_ex5_dacrw, + ctl_lsq_ex5_ttype, + ctl_lsq_ex5_l_fld, + ctl_lsq_ex5_load_hit, + lsq_ctl_ex6_ldq_events, + lsq_ctl_ex6_stq_events, + ctl_lsq_stq3_icswx_data, + ctl_lsq_dbg_int_en, + ctl_lsq_ldp_idle, + ctl_lsq_rv1_dir_rd_val, + dcc_dec_arr_rd_rv1_val, + dcc_dec_arr_rd_congr_cl, + dcc_dec_stq3_mftgpr_val, + dcc_dec_stq5_mftgpr_val, + lq_xu_spr_xucr0_cul, + dcc_dir_spr_xucr2_rmt, + spr_dcc_spr_xudbg0_exec, + spr_dcc_spr_xudbg0_tid, + spr_dcc_spr_xudbg0_way, + spr_dcc_spr_xudbg0_row, + dcc_spr_spr_xudbg0_done, + dcc_spr_spr_xudbg1_valid, + dcc_spr_spr_xudbg1_watch, + dcc_spr_spr_xudbg1_parity, + dcc_spr_spr_xudbg1_lru, + dcc_spr_spr_xudbg1_lock, + dcc_spr_spr_xudbg2_tag, + spr_dcc_spr_xucr2_rmt, + spr_dcc_spr_lsucr0_clchk, + spr_dcc_spr_acop_ct, + spr_dcc_spr_hacop_ct, + spr_dcc_epsc_epr, + spr_dcc_epsc_eas, + spr_dcc_epsc_egs, + spr_dcc_epsc_elpid, + spr_dcc_epsc_epid, + dcc_dir_ex2_binv_val, + stq4_dcarr_wren, + dcc_byp_ram_sel, + dcc_dec_ex5_wren, + lq_xu_ex5_abort, + lq_xu_gpr_ex5_wa, + lq_rv_gpr_ex6_wa, + lq_xu_axu_rel_we, + lq_xu_gpr_rel_we, + lq_xu_gpr_rel_wa, + lq_rv_gpr_rel_we, + lq_rv_gpr_rel_wa, + lq_xu_cr_ex5_we, + lq_xu_cr_ex5_wa, + lq_xu_ex5_cr, + lq_xu_axu_ex4_addr, + lq_xu_axu_ex5_we, + lq_xu_axu_ex5_le, + lq_rv_itag1_vld, + lq_rv_itag1, + lq_rv_itag1_restart, + lq_rv_itag1_abort, + lq_rv_itag1_hold, + lq_rv_itag1_cord, + lq_rv_clr_hold, + dcc_dec_hold_all, + lq0_iu_execute_vld, + lq0_iu_recirc_val, + lq0_iu_itag, + lq0_iu_flush2ucode, + lq0_iu_flush2ucode_type, + lq0_iu_exception_val, + lq0_iu_exception, + lq0_iu_dear_val, + lq0_iu_n_flush, + lq0_iu_np1_flush, + lq0_iu_dacr_type, + lq0_iu_dacrw, + lq0_iu_instr, + lq0_iu_eff_addr, + dcc_pf_ex5_eff_addr, + dcc_pf_ex5_req_val_4pf, + dcc_pf_ex5_act, + dcc_pf_ex5_thrd_id, + dcc_pf_ex5_loadmiss, + dcc_pf_ex5_itag, + lq_pc_err_derat_parity, + lq_pc_err_dir_ldp_parity, + lq_pc_err_dir_stp_parity, + lq_pc_err_dcache_parity, + lq_pc_err_derat_multihit, + lq_pc_err_dir_ldp_multihit, + lq_pc_err_dir_stp_multihit, + pc_lq_ram_active, + lq_pc_ram_data_val, + ctl_perv_ex6_perf_events, + ctl_perv_stq4_perf_events, + dcc_dir_ex2_stg_act, + dcc_dir_ex3_stg_act, + dcc_dir_ex4_stg_act, + dcc_dir_ex5_stg_act, + dcc_dir_stq1_stg_act, + dcc_dir_stq2_stg_act, + dcc_dir_stq3_stg_act, + dcc_dir_stq4_stg_act, + dcc_dir_stq5_stg_act, + dcc_dir_binv2_ex2_stg_act, + dcc_dir_binv3_ex3_stg_act, + dcc_dir_binv4_ex4_stg_act, + dcc_dir_binv5_ex5_stg_act, + dcc_dir_binv6_ex6_stg_act, + vdd, + gnd, + nclk, + sg_0, + func_sl_thold_0_b, + func_sl_force, + func_nsl_thold_0_b, + func_nsl_force, + func_slp_sl_thold_0_b, + func_slp_sl_force, + func_slp_nsl_thold_0_b, + func_slp_nsl_force, + d_mode_dc, + delay_lclkr_dc, + mpw1_dc_b, + mpw2_dc_b, + scan_in, + scan_out +); + +//------------------------------------------------------------------- +// Generics +//------------------------------------------------------------------- +//parameter ITAG_SIZE_ENC = 7; // Instruction Tag Size +//parameter CR_POOL_ENC = 5; // Encode of CR rename pool size +//parameter GPR_POOL_ENC = 6; +//parameter THREADS_POOL_ENC = 1; +//parameter UCODE_ENTRIES_ENC = 3; +//parameter REAL_IFAR_WIDTH = 42; // 42 bit real address +//parameter DC_SIZE = 15; // 2^15 = 32768 Bytes L1 D$ +//parameter AXU_SPARE_ENC = 3; +//parameter GPR_WIDTH_ENC = 6; // 5 = 32bit mode, 6 = 64bit mode +//parameter `CR_WIDTH = 4; +parameter PARBITS = 4; // Number of Parity Bits + +// IU Dispatch +input [0:`THREADS-1] rv_lq_rv1_i0_vld; +input rv_lq_rv1_i0_ucode_preissue; +input rv_lq_rv1_i0_2ucode; +input [0:`UCODE_ENTRIES_ENC-1] rv_lq_rv1_i0_ucode_cnt; +input [0:`THREADS-1] rv_lq_rv1_i1_vld; +input rv_lq_rv1_i1_ucode_preissue; +input rv_lq_rv1_i1_2ucode; +input [0:`UCODE_ENTRIES_ENC-1] rv_lq_rv1_i1_ucode_cnt; + +// Execution Pipe Inputs +input dec_dcc_ex0_act; // ACT +input dec_dcc_ex1_cmd_act; // ACT +input dec_dcc_ex1_ucode_val; // PreIssue of Ucode operation is valid +input [0:`UCODE_ENTRIES_ENC-1] dec_dcc_ex1_ucode_cnt; +input dec_dcc_ex1_ucode_op; +input dec_dcc_ex1_sfx_val; // Simple FXU operation is valid +input dec_dcc_ex1_axu_op_val; // Operation is from the AXU +input dec_dcc_ex1_axu_falign; // AXU force alignment indicator +input dec_dcc_ex1_axu_fexcpt; // AXU force alignment exception on misaligned access +input [0:2] dec_dcc_ex1_axu_instr_type; +input dec_dcc_ex1_cache_acc; // Cache Access is Valid, Op that touches directory +input [0:`THREADS-1] dec_dcc_ex1_thrd_id; +input [0:31] dec_dcc_ex1_instr; +input dec_dcc_ex1_optype1; // 1 Byte Load/Store +input dec_dcc_ex1_optype2; // 2 Byte Load/Store +input dec_dcc_ex1_optype4; // 4 Byte Load/Store +input dec_dcc_ex1_optype8; // 8 Byte Load/Store +input dec_dcc_ex1_optype16; // 16 Byte Load/Store +input [0:`AXU_SPARE_ENC+`GPR_POOL_ENC+`THREADS_POOL_ENC-1] dec_dcc_ex1_target_gpr; // Target GPR, needed for reloads +input dec_dcc_ex1_mtspr_trace; // Operation is a mtspr trace instruction +input dec_dcc_ex1_load_instr; // Operation is a Load instruction +input dec_dcc_ex1_store_instr; // Operation is a Store instruction +input dec_dcc_ex1_dcbf_instr; // Operation is a DCBF instruction +input dec_dcc_ex1_sync_instr; // Operation is a SYNC instruction +input [0:1] dec_dcc_ex1_l_fld; // DCBF/SYNC L Field +input dec_dcc_ex1_dcbi_instr; // Operation is a DCBI instruction +input dec_dcc_ex1_dcbz_instr; // Operation is a DCBZ instruction +input dec_dcc_ex1_dcbt_instr; // Operation is a DCBT instruction +input dec_dcc_ex1_pfetch_val; // Operation is a prefetch +input dec_dcc_ex1_dcbtst_instr; // Operation is a DCBTST instruction +input [0:4] dec_dcc_ex1_th_fld; // TH/CT Field for Cache Management instructions +input dec_dcc_ex1_dcbtls_instr; +input dec_dcc_ex1_dcbtstls_instr; +input dec_dcc_ex1_dcblc_instr; +input dec_dcc_ex1_dcbst_instr; +input dec_dcc_ex1_icbi_instr; +input dec_dcc_ex1_icblc_instr; +input dec_dcc_ex1_icbt_instr; +input dec_dcc_ex1_icbtls_instr; +input dec_dcc_ex1_icswx_instr; +input dec_dcc_ex1_icswxdot_instr; +input dec_dcc_ex1_icswx_epid; +input dec_dcc_ex1_tlbsync_instr; +input dec_dcc_ex1_ldawx_instr; +input dec_dcc_ex1_wclr_instr; +input dec_dcc_ex1_wchk_instr; +input dec_dcc_ex1_resv_instr; // Operation is a resv instruction +input dec_dcc_ex1_mutex_hint; // Mutex Hint For larx instructions +input dec_dcc_ex1_mbar_instr; // Operation is an MBAR instruction +input dec_dcc_ex1_makeitso_instr; +input dec_dcc_ex1_is_msgsnd; +input dec_dcc_ex1_dci_instr; +input dec_dcc_ex1_ici_instr; +input dec_dcc_ex1_mword_instr; // load/store multiple word instruction +input dec_dcc_ex1_algebraic; // Operation is an Algebraic Load instruction +input dec_dcc_ex1_strg_index; // String Indexed Form +input dec_dcc_ex1_src_gpr; // Source is the GPR's for mfloat and mDCR ops +input dec_dcc_ex1_src_axu; // Source is the AXU's for mfloat and mDCR ops +input dec_dcc_ex1_src_dp; // Source is the BOX's for mfloat and mDCR ops +input dec_dcc_ex1_targ_gpr; // Target is the GPR's for mfloat and mDCR ops +input dec_dcc_ex1_targ_axu; // Target is the AXU's for mfloat and mDCR ops +input dec_dcc_ex1_targ_dp; // Target is the BOX's for mfloat and mDCR ops +input dec_dcc_ex1_upd_form; +input [0:`ITAG_SIZE_ENC-1] dec_dcc_ex1_itag; +input [0:`CR_POOL_ENC-1] dec_dcc_ex1_cr_fld; +input dec_dcc_ex1_expt_det; +input dec_dcc_ex1_priv_prog; +input dec_dcc_ex1_hypv_prog; +input dec_dcc_ex1_illeg_prog; +input dec_dcc_ex1_dlock_excp; +input dec_dcc_ex1_ilock_excp; +input dec_dcc_ex1_ehpriv_excp; +input dec_dcc_ex2_is_any_load_dac; +input dec_dcc_ex5_req_abort_rpt; +input dec_dcc_ex5_axu_abort_rpt; +input [64-(2**`GPR_WIDTH_ENC):63] dir_dcc_ex2_eff_addr; + +// Directory Back-Invalidate +input lsq_ctl_rv0_back_inv; // L2 Back-Invalidate is Valid + +// Derat Snoop-Invalidate +input derat_rv1_snoop_val; + +// Directory Read Operation +input [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] dir_dcc_ex4_way_tag_a; +input [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] dir_dcc_ex4_way_tag_b; +input [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] dir_dcc_ex4_way_tag_c; +input [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] dir_dcc_ex4_way_tag_d; +input [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] dir_dcc_ex4_way_tag_e; +input [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] dir_dcc_ex4_way_tag_f; +input [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] dir_dcc_ex4_way_tag_g; +input [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] dir_dcc_ex4_way_tag_h; +input [0:PARBITS-1] dir_dcc_ex4_way_par_a; +input [0:PARBITS-1] dir_dcc_ex4_way_par_b; +input [0:PARBITS-1] dir_dcc_ex4_way_par_c; +input [0:PARBITS-1] dir_dcc_ex4_way_par_d; +input [0:PARBITS-1] dir_dcc_ex4_way_par_e; +input [0:PARBITS-1] dir_dcc_ex4_way_par_f; +input [0:PARBITS-1] dir_dcc_ex4_way_par_g; +input [0:PARBITS-1] dir_dcc_ex4_way_par_h; +input [0:1+`THREADS] dir_dcc_ex5_way_a_dir; +input [0:1+`THREADS] dir_dcc_ex5_way_b_dir; +input [0:1+`THREADS] dir_dcc_ex5_way_c_dir; +input [0:1+`THREADS] dir_dcc_ex5_way_d_dir; +input [0:1+`THREADS] dir_dcc_ex5_way_e_dir; +input [0:1+`THREADS] dir_dcc_ex5_way_f_dir; +input [0:1+`THREADS] dir_dcc_ex5_way_g_dir; +input [0:1+`THREADS] dir_dcc_ex5_way_h_dir; +input [0:6] dir_dcc_ex5_dir_lru; + +input derat_dcc_ex3_wimge_e; +input derat_dcc_ex3_itagHit; +input [0:4] derat_dcc_ex4_wimge; // Memory Attribute I Bit from ERAT +input [0:3] derat_dcc_ex4_usr_bits; // User Defined Bits from ERAT +input [0:1] derat_dcc_ex4_wlc; // ClassID +input [64-`REAL_IFAR_WIDTH:51] derat_dcc_ex4_p_addr; +input derat_dcc_ex4_noop_touch; +input derat_dcc_ex4_miss; +input derat_dcc_ex4_tlb_err; +input derat_dcc_ex4_dsi; +input derat_dcc_ex4_vf; +input derat_dcc_ex4_multihit_err_det; +input derat_dcc_ex4_par_err_det; +input derat_dcc_ex4_multihit_err_flush; +input derat_dcc_ex4_par_err_flush; +input derat_dcc_ex4_tlb_inelig; +input derat_dcc_ex4_pt_fault; +input derat_dcc_ex4_lrat_miss; +input derat_dcc_ex4_tlb_multihit; +input derat_dcc_ex4_tlb_par_err; +input derat_dcc_ex4_lru_par_err; +input derat_dcc_ex4_restart; +input derat_fir_par_err; +input derat_fir_multihit; + +// SetHold and ClrHold for itag +input derat_dcc_ex4_setHold; +input [0:`THREADS-1] derat_dcc_clr_hold; + +// EMQ Idle indicator +input [0:`THREADS-1] derat_dcc_emq_idle; + +// DEBUG Address Compare Exception +input spr_dcc_ex4_dvc1_en; +input spr_dcc_ex4_dvc2_en; +input spr_dcc_ex4_dacrw1_cmpr; +input spr_dcc_ex4_dacrw2_cmpr; +input spr_dcc_ex4_dacrw3_cmpr; +input spr_dcc_ex4_dacrw4_cmpr; +input [0:47] spr_dcc_spr_lesr; + +input dir_dcc_ex4_hit; // ex4 Load/Store Hit +input dir_dcc_ex4_miss; // ex4 Load/Store Miss +input dir_dcc_ex4_set_rel_coll; // Resource Conflict, should cause a reject +input dir_dcc_ex4_byp_restart; // Directory Bypassed stage that was restarted +input dir_dcc_ex5_dir_perr_det; // Data Directory Parity Error Detected +input dir_dcc_ex5_dc_perr_det; // Data Cache Parity Error Detected +input dir_dcc_ex5_dir_perr_flush; // Data Directory Parity Error Flush +input dir_dcc_ex5_dc_perr_flush; // Data Cache Parity Error Flush +input dir_dcc_ex5_multihit_det; // Directory Multihit Detected +input dir_dcc_ex5_multihit_flush; // Directory Multihit Flush +input dir_dcc_stq4_dir_perr_det; // Data Cache Parity Error Detected on the STQ Commit Pipeline +input dir_dcc_stq4_multihit_det; // Directory Multihit Detected on the STQ Commit Pipeline +input dir_dcc_ex5_stp_flush; // Directory Error detected on the STQ Commit Pipeline with EX5 LDP valid + +// Completion Inputs +input [0:`THREADS-1] iu_lq_cp_flush; // Completion Flush Report +input [0:`THREADS-1] iu_lq_recirc_val; // Next Itag Completion Report +input [0:`THREADS*`ITAG_SIZE_ENC-1] iu_lq_cp_next_itag; // Next Itag Completion Itag + +// XER[SO] Read for CP_NEXT instructions (stcx./icswx./ldawx.) +input [0:`THREADS-1] xu_lq_xer_cp_rd; + +// Stage Flush +output fgen_ex1_stg_flush; // ex1 Stage Flush +output fgen_ex2_stg_flush; // ex2 Stage Flush +output fgen_ex3_stg_flush; // ex3 Stage Flush +output fgen_ex4_cp_flush; // ex4 CP Flush +output fgen_ex4_stg_flush; // ex4 Stage Flush +output fgen_ex5_stg_flush; // ex5 Stage Flush + +input dir_dcc_rel3_dcarr_upd; // Reload Data Array Update Valid + +// Data Cache Config +input xu_lq_spr_ccr2_en_trace; // MTSPR Trace is Enabled +input xu_lq_spr_ccr2_dfrat; // Force Real Address Translation +input xu_lq_spr_ccr2_ap; // AP Available +input xu_lq_spr_ccr2_ucode_dis; // Ucode Disabled +input xu_lq_spr_ccr2_notlb; // MMU is disabled +input xu_lq_spr_xucr0_clkg_ctl; // Clock Gating Override +input xu_lq_spr_xucr0_wlk; // Data Cache Way Locking Enable +input xu_lq_spr_xucr0_mbar_ack; // L2 ACK of membar and lwsync +input xu_lq_spr_xucr0_tlbsync; // L2 ACK of tlbsync +input xu_lq_spr_xucr0_dcdis; // Data Cache Disable +input xu_lq_spr_xucr0_aflsta; // AXU Force Load/Store Alignment interrupt +input xu_lq_spr_xucr0_flsta; // FX Force Load/Store Alignment interrupt +input [0:`THREADS-1] xu_lq_spr_xucr0_trace_um; // TRACE SPR is Enabled in user mode +input xu_lq_spr_xucr0_mddp; // Machine Check on Data Cache Directory Parity Error +input xu_lq_spr_xucr0_mdcp; // Machine Check on Data Cache Parity Error +input xu_lq_spr_xucr4_mmu_mchk; // Machine Check on a Data ERAT Parity or Multihit Error +input xu_lq_spr_xucr4_mddmh; // Machine Check on Data Cache Directory Multihit Error + +input [0:`THREADS-1] xu_lq_spr_msr_cm; // 64bit mode enable +input [0:`THREADS-1] xu_lq_spr_msr_fp; // FP Available +input [0:`THREADS-1] xu_lq_spr_msr_spv; // VEC Available +input [0:`THREADS-1] xu_lq_spr_msr_de; // Debug Interrupt Enable +input [0:`THREADS-1] xu_lq_spr_dbcr0_idm; // Internal Debug Mode Enable +input [0:`THREADS-1] xu_lq_spr_epcr_duvd; // Disable Hypervisor Debug + +// MSR[GS,PR] bits, indicates which state we are running in +input [0:`THREADS-1] xu_lq_spr_msr_gs; // (MSR.GS) +input [0:`THREADS-1] xu_lq_spr_msr_pr; // Problem State (MSR.PR) +input [0:`THREADS-1] xu_lq_spr_msr_ds; // Data Address Space (MSR.DS) +input [0:7] mm_lq_lsu_lpidr; // the LPIDR register +input [0:14*`THREADS-1] mm_lq_pid; + +// RESTART indicator +input lsq_ctl_ex5_ldq_restart; // Loadmiss Queue Report +input lsq_ctl_ex5_stq_restart; // Store Queue Report +input lsq_ctl_ex5_stq_restart_miss; + +// Store Data Forward +input lsq_ctl_ex5_fwd_val; + +input lsq_ctl_sync_in_stq; + +// Hold RV Indicator +input lsq_ctl_rv_hold_all; + +// Reservation station set barrier indicator +input lsq_ctl_rv_set_hold; +input [0:`THREADS-1] lsq_ctl_rv_clr_hold; + +// Reload/Commit Pipe +input lsq_ctl_stq1_stg_act; +input lsq_ctl_stq1_val; +input [0:`THREADS-1] lsq_ctl_stq1_thrd_id; +input lsq_ctl_stq1_store_val; // Store Commit instruction +input lsq_ctl_stq1_watch_clr; // Recirc Watch Clear instruction +input [0:1] lsq_ctl_stq1_l_fld; // Recirc Watch Clear L-Field +input lsq_ctl_stq1_resv; +input lsq_ctl_stq1_ci; +input lsq_ctl_stq1_axu_val; // Reload is for a Vector Register +input lsq_ctl_stq1_epid_val; +input lsq_ctl_stq1_mftgpr_val; // MFTGPR instruction Valid +input lsq_ctl_stq1_mfdpf_val; // MFDP to the Fixed Point Unit instruction Valid +input lsq_ctl_stq1_mfdpa_val; // MFDP to the Auxilary Unit instruction Valid +input lsq_ctl_stq2_blk_req; // Block Store due to RV issue +input lsq_ctl_stq4_xucr0_cul; +input [0:`ITAG_SIZE_ENC-1] lsq_ctl_stq5_itag; +input [0:`AXU_SPARE_ENC+`GPR_POOL_ENC+`THREADS_POOL_ENC-1] lsq_ctl_stq5_tgpr; +input lsq_ctl_rel1_gpr_val; +input [0:`AXU_SPARE_ENC+`GPR_POOL_ENC+`THREADS_POOL_ENC-1] lsq_ctl_rel1_ta_gpr; +input lsq_ctl_rel1_upd_gpr; // Reload data should be written to GPR (DCB ops don't write to GPRs) + +// Store Queue Completion Report +input lsq_ctl_stq_cpl_ready; +input [0:`ITAG_SIZE_ENC-1] lsq_ctl_stq_cpl_ready_itag; +input [0:`THREADS-1] lsq_ctl_stq_cpl_ready_tid; +input lsq_ctl_stq_n_flush; +input lsq_ctl_stq_np1_flush; +input lsq_ctl_stq_exception_val; +input [0:5] lsq_ctl_stq_exception; +input [0:3] lsq_ctl_stq_dacrw; +output ctl_lsq_stq_cpl_blk; + +// Illegal LSWX has been determined +input lsq_ctl_ex3_strg_val; // STQ has checked XER valid +input lsq_ctl_ex3_strg_noop; // STQ detected a noop of LSWX/STSWX +input lsq_ctl_ex3_illeg_lswx; // STQ detected illegal form of LSWX +input lsq_ctl_ex3_ct_val; // ICSWX Data is valid +input [0:5] lsq_ctl_ex3_be_ct; // Big Endian Coprocessor Type Select +input [0:5] lsq_ctl_ex3_le_ct; // Little Endian Coprocessor Type Select + +// Directory Results Input +input dir_dcc_stq3_hit; +input dir_dcc_ex5_cr_rslt; + +// EX2 Execution Pipe Outputs +output dcc_dir_ex2_frc_align2; +output dcc_dir_ex2_frc_align4; +output dcc_dir_ex2_frc_align8; +output dcc_dir_ex2_frc_align16; +output dcc_dir_ex2_64bit_agen; +output [0:`THREADS-1] dcc_dir_ex2_thrd_id; +output dcc_derat_ex3_strg_noop; +output dcc_derat_ex5_blk_tlb_req; // Higher Priority Interrupt detected, block ERAT miss request from going to MMU +output [0:`THREADS-1] dcc_derat_ex6_cplt; // Completion report was sent for EMQ detected interrupts, EMQ entry can be freed +output [0:`ITAG_SIZE_ENC-1] dcc_derat_ex6_cplt_itag; // Completion report ITAG for EMQ detected interrupt + +// EX3 Execution Pipe Outputs +output dcc_dir_ex3_lru_upd; +output dcc_dir_ex3_cache_acc; // Cache Access is Valid +output dcc_dir_ex3_pfetch_val; +output dcc_dir_ex3_lock_set; // DCBT[ST]LS Operation is valid +output dcc_dir_ex3_th_c; // DCBT[ST]LS Operation is targeting the L1 Data Cache +output dcc_dir_ex3_watch_set; // LDAWX Operation is valid +output dcc_dir_ex3_larx_val; // LARX Operation is valid, the directory should be invalidated if hit +output dcc_dir_ex3_watch_chk; // WCHK Operation is valid +output dcc_dir_ex3_ddir_acc; +output dcc_dir_ex4_load_val; +output dcc_spr_ex3_data_val; +output [64-(2**`GPR_WIDTH_ENC):63] dcc_spr_ex3_eff_addr; + +output [0:4] ctl_dat_ex3_opsize; +output ctl_dat_ex3_le_mode; +output [0:3] ctl_dat_ex3_le_ld_rotsel; +output [0:3] ctl_dat_ex3_be_ld_rotsel; +output ctl_dat_ex3_algebraic; +output [0:3] ctl_dat_ex3_le_alg_rotsel; + +// EX4 Execution Pipe Outputs +output dcc_byp_rel2_stg_act; +output dcc_byp_rel3_stg_act; +output dcc_byp_ram_act; +input byp_dcc_ex2_req_aborted; +output dcc_byp_ex4_moveOp_val; +output dcc_byp_stq6_moveOp_val; +output [64-(2**`GPR_WIDTH_ENC):63] dcc_byp_ex4_move_data; +output dcc_byp_ex5_lq_req_abort; +output [0:((2**`GPR_WIDTH_ENC)/8)-1] dcc_byp_ex5_byte_mask; +output [0:`THREADS-1] dcc_byp_ex6_thrd_id; +output dcc_byp_ex6_dvc1_en; +output dcc_byp_ex6_dvc2_en; +output [0:3] dcc_byp_ex6_dacr_cmpr; +output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] dcc_dir_ex4_p_addr; +output dcc_dir_stq6_store_val; + +// Execution Pipe Outputs +output [0:`THREADS-1] ctl_lsq_ex2_streq_val; +output [0:`ITAG_SIZE_ENC-1] ctl_lsq_ex2_itag; +output [0:`THREADS-1] ctl_lsq_ex2_thrd_id; +output [0:`THREADS-1] ctl_lsq_ex3_ldreq_val; +output [0:`THREADS-1] ctl_lsq_ex3_wchkall_val; +output ctl_lsq_ex3_pfetch_val; +output [0:15] ctl_lsq_ex3_byte_en; +output [58:63] ctl_lsq_ex3_p_addr; +output [0:`THREADS-1] ctl_lsq_ex3_thrd_id; +output ctl_lsq_ex3_algebraic; +output [0:2] ctl_lsq_ex3_opsize; +output ctl_lsq_ex4_ldreq_val; +output ctl_lsq_ex4_binvreq_val; +output ctl_lsq_ex4_streq_val; +output ctl_lsq_ex4_othreq_val; +output [64-`REAL_IFAR_WIDTH:57] ctl_lsq_ex4_p_addr; +output ctl_lsq_ex4_dReq_val; +output ctl_lsq_ex4_gath_load; +output ctl_lsq_ex4_send_l2; +output ctl_lsq_ex4_has_data; +output ctl_lsq_ex4_cline_chk; +output [0:4] ctl_lsq_ex4_wimge; +output ctl_lsq_ex4_byte_swap; +output ctl_lsq_ex4_is_sync; +output ctl_lsq_ex4_all_thrd_chk; +output ctl_lsq_ex4_is_store; +output ctl_lsq_ex4_is_resv; +output ctl_lsq_ex4_is_mfgpr; +output ctl_lsq_ex4_is_icswxr; +output ctl_lsq_ex4_is_icbi; +output ctl_lsq_ex4_watch_clr; +output ctl_lsq_ex4_watch_clr_all; +output ctl_lsq_ex4_mtspr_trace; +output ctl_lsq_ex4_is_inval_op; +output ctl_lsq_ex4_is_cinval; +output ctl_lsq_ex5_lock_clr; +output ctl_lsq_ex5_lock_set; +output ctl_lsq_ex5_watch_set; +output [0:`AXU_SPARE_ENC+`GPR_POOL_ENC+`THREADS_POOL_ENC-1] ctl_lsq_ex5_tgpr; +output ctl_lsq_ex5_axu_val; // XU,AXU type operation +output ctl_lsq_ex5_is_epid; +output [0:3] ctl_lsq_ex5_usr_def; +output ctl_lsq_ex5_drop_rel; // L2 only instructions +output ctl_lsq_ex5_flush_req; // Flush request from LDQ/STQ +output ctl_lsq_ex5_flush_pfetch; // Flush Prefetch in EX5 +output [0:10] ctl_lsq_ex5_cmmt_events; +output ctl_lsq_ex5_perf_val0; +output [0:3] ctl_lsq_ex5_perf_sel0; +output ctl_lsq_ex5_perf_val1; +output [0:3] ctl_lsq_ex5_perf_sel1; +output ctl_lsq_ex5_perf_val2; +output [0:3] ctl_lsq_ex5_perf_sel2; +output ctl_lsq_ex5_perf_val3; +output [0:3] ctl_lsq_ex5_perf_sel3; +output ctl_lsq_ex5_not_touch; +output [0:1] ctl_lsq_ex5_class_id; +output [0:1] ctl_lsq_ex5_dvc; +output [0:3] ctl_lsq_ex5_dacrw; +output [0:5] ctl_lsq_ex5_ttype; +output [0:1] ctl_lsq_ex5_l_fld; +output ctl_lsq_ex5_load_hit; +input [0:3] lsq_ctl_ex6_ldq_events; // LDQ Pipeline Performance Events +input [0:1] lsq_ctl_ex6_stq_events; // LDQ Pipeline Performance Events +output [0:26] ctl_lsq_stq3_icswx_data; +output [0:`THREADS-1] ctl_lsq_dbg_int_en; +output [0:`THREADS-1] ctl_lsq_ldp_idle; + +// SPR Directory Read Valid +output ctl_lsq_rv1_dir_rd_val; + +// Directory Read interface +output dcc_dec_arr_rd_rv1_val; +output [0:5] dcc_dec_arr_rd_congr_cl; + +// MFTGPR instruction +output dcc_dec_stq3_mftgpr_val; +output dcc_dec_stq5_mftgpr_val; + +// SPR status +output lq_xu_spr_xucr0_cul; // Cache Lock unable to lock +output [0:31] dcc_dir_spr_xucr2_rmt; +input spr_dcc_spr_xudbg0_exec; // Execute Directory Read +input [0:`THREADS-1] spr_dcc_spr_xudbg0_tid; // Directory Read Initiated by Thread +input [0:2] spr_dcc_spr_xudbg0_way; // Directory Read Way +input [0:5] spr_dcc_spr_xudbg0_row; // Directory Read Congruence Class +output dcc_spr_spr_xudbg0_done; // Directory Read Done +output dcc_spr_spr_xudbg1_valid; // Directory Valid State +output [0:3] dcc_spr_spr_xudbg1_watch; // Directory Watch State +output [0:3] dcc_spr_spr_xudbg1_parity; // Directory Parity +output [0:6] dcc_spr_spr_xudbg1_lru; // Directory LRU +output dcc_spr_spr_xudbg1_lock; // Directory Lock State +output [33:63] dcc_spr_spr_xudbg2_tag; // Directory Tag +input [32:63] spr_dcc_spr_xucr2_rmt; // RMT Table +input spr_dcc_spr_lsucr0_clchk; // Cacheline Check Enabled +input [0:(32*`THREADS)-1] spr_dcc_spr_acop_ct; // ACOP register for icswx +input [0:(32*`THREADS)-1] spr_dcc_spr_hacop_ct; // HACOP register for icswx +input [0:`THREADS-1] spr_dcc_epsc_epr; +input [0:`THREADS-1] spr_dcc_epsc_eas; +input [0:`THREADS-1] spr_dcc_epsc_egs; +input [0:(8*`THREADS)-1] spr_dcc_epsc_elpid; +input [0:(14*`THREADS)-1] spr_dcc_epsc_epid; + +// Back-invalidate +output dcc_dir_ex2_binv_val; + +// Update Data Array Valid +output stq4_dcarr_wren; + +output dcc_byp_ram_sel; +output dcc_dec_ex5_wren; +output lq_xu_ex5_abort; +output [0:`AXU_SPARE_ENC+`GPR_POOL_ENC+`THREADS_POOL_ENC-1] lq_xu_gpr_ex5_wa; +output [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] lq_rv_gpr_ex6_wa; +output lq_xu_axu_rel_we; +output lq_xu_gpr_rel_we; +output [0:`AXU_SPARE_ENC+`GPR_POOL_ENC+`THREADS_POOL_ENC-1] lq_xu_gpr_rel_wa; +output lq_rv_gpr_rel_we; +output [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] lq_rv_gpr_rel_wa; + +output lq_xu_cr_ex5_we; +output [0:`CR_POOL_ENC+`THREADS_POOL_ENC-1] lq_xu_cr_ex5_wa; +output [0:`CR_WIDTH-1] lq_xu_ex5_cr; + +// Interface with AXU PassThru with XU +output [59:63] lq_xu_axu_ex4_addr; +output lq_xu_axu_ex5_we; +output lq_xu_axu_ex5_le; + +// Outputs to Reservation Station +output [0:`THREADS-1] lq_rv_itag1_vld; +output [0:`ITAG_SIZE_ENC-1] lq_rv_itag1; +output lq_rv_itag1_restart; +output lq_rv_itag1_abort; +output lq_rv_itag1_hold; +output lq_rv_itag1_cord; +output [0:`THREADS-1] lq_rv_clr_hold; +output dcc_dec_hold_all; + +// Completion Report +output [0:`THREADS-1] lq0_iu_execute_vld; +output [0:`THREADS-1] lq0_iu_recirc_val; +output [0:`ITAG_SIZE_ENC-1] lq0_iu_itag; +output lq0_iu_flush2ucode; +output lq0_iu_flush2ucode_type; +output lq0_iu_exception_val; +output [0:5] lq0_iu_exception; +output [0:`THREADS-1] lq0_iu_dear_val; +output lq0_iu_n_flush; +output lq0_iu_np1_flush; +output lq0_iu_dacr_type; +output [0:3] lq0_iu_dacrw; +output [0:31] lq0_iu_instr; +output [64-(2**`GPR_WIDTH_ENC):63] lq0_iu_eff_addr; + +// outputs to prefetch +output [64-(2**`GPR_WIDTH_ENC):59] dcc_pf_ex5_eff_addr; +output dcc_pf_ex5_req_val_4pf; +output dcc_pf_ex5_act; +output [0:`THREADS-1] dcc_pf_ex5_thrd_id; +output dcc_pf_ex5_loadmiss; +output [0:`ITAG_SIZE_ENC-1] dcc_pf_ex5_itag; + +// Error Reporting +output lq_pc_err_derat_parity; +output lq_pc_err_dir_ldp_parity; +output lq_pc_err_dir_stp_parity; +output lq_pc_err_dcache_parity; +output lq_pc_err_derat_multihit; +output lq_pc_err_dir_ldp_multihit; +output lq_pc_err_dir_stp_multihit; + +// Ram Mode Control +input [0:`THREADS-1] pc_lq_ram_active; +output lq_pc_ram_data_val; + +// LQ Pervasive +output [0:18+`THREADS-1] ctl_perv_ex6_perf_events; +output [0:6+`THREADS-1] ctl_perv_stq4_perf_events; + +// ACT's +output dcc_dir_ex2_stg_act; +output dcc_dir_ex3_stg_act; +output dcc_dir_ex4_stg_act; +output dcc_dir_ex5_stg_act; +output dcc_dir_stq1_stg_act; +output dcc_dir_stq2_stg_act; +output dcc_dir_stq3_stg_act; +output dcc_dir_stq4_stg_act; +output dcc_dir_stq5_stg_act; +output dcc_dir_binv2_ex2_stg_act; +output dcc_dir_binv3_ex3_stg_act; +output dcc_dir_binv4_ex4_stg_act; +output dcc_dir_binv5_ex5_stg_act; +output dcc_dir_binv6_ex6_stg_act; + +// Pervasive + + +inout vdd; + + +inout gnd; + +(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) + +input [0:`NCLK_WIDTH-1] nclk; +input sg_0; +input func_sl_thold_0_b; +input func_sl_force; +input func_nsl_thold_0_b; +input func_nsl_force; +input func_slp_sl_thold_0_b; +input func_slp_sl_force; +input func_slp_nsl_thold_0_b; +input func_slp_nsl_force; +input d_mode_dc; +input delay_lclkr_dc; +input mpw1_dc_b; +input mpw2_dc_b; + +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + +input scan_in; + +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + +output scan_out; + +//-------------------------- +// constants +//-------------------------- +parameter TAGSIZE = ((63-(`DC_SIZE-3))-(64-`REAL_IFAR_WIDTH))+1; +parameter AXU_TARGET_ENC = `AXU_SPARE_ENC+`GPR_POOL_ENC+`THREADS_POOL_ENC; + +//-------------------------- +// components +//-------------------------- + +parameter [0:4] rot_max_size = 5'b10000; + +//-------------------------- +// signals +//-------------------------- +wire [0:`THREADS-1] iu_lq_recirc_val_d; +wire [0:`THREADS-1] iu_lq_recirc_val_q; +wire [0:`ITAG_SIZE_ENC-1] iu_lq_cp_next_itag_q[0:`THREADS-1]; +wire [0:`THREADS-1] iu_lq_cp_flush_d; +wire [0:`THREADS-1] iu_lq_cp_flush_q; +wire [0:`THREADS-1] ex0_i0_vld_d; +wire [0:`THREADS-1] ex0_i0_vld_q; +wire ex0_i0_ucode_preissue_d; +wire ex0_i0_ucode_preissue_q; +wire ex0_i0_2ucode_d; +wire ex0_i0_2ucode_q; +wire [0:`UCODE_ENTRIES_ENC-1] ex0_i0_ucode_cnt_d; +wire [0:`UCODE_ENTRIES_ENC-1] ex0_i0_ucode_cnt_q; +wire [0:`THREADS-1] ex0_i1_vld_d; +wire [0:`THREADS-1] ex0_i1_vld_q; +wire ex0_i1_ucode_preissue_d; +wire ex0_i1_ucode_preissue_q; +wire ex0_i1_2ucode_d; +wire ex0_i1_2ucode_q; +wire [0:`UCODE_ENTRIES_ENC-1] ex0_i1_ucode_cnt_d; +wire [0:`UCODE_ENTRIES_ENC-1] ex0_i1_ucode_cnt_q; +wire [0:`THREADS-1] xer_lq_cp_rd_so_d; +wire [0:`THREADS-1] xer_lq_cp_rd_so_q; +wire ex2_optype1_d; +wire ex2_optype1_q; +wire ex3_optype1_d; +wire ex3_optype1_q; +wire ex2_optype2_d; +wire ex2_optype2_q; +wire ex3_optype2_d; +wire ex3_optype2_q; +wire ex2_optype4_d; +wire ex2_optype4_q; +wire ex3_optype4_d; +wire ex3_optype4_q; +wire ex2_optype8_d; +wire ex2_optype8_q; +wire ex3_optype8_d; +wire ex3_optype8_q; +wire ex2_optype16_d; +wire ex2_optype16_q; +wire ex3_optype16_d; +wire ex3_optype16_q; +wire ex3_dacr_type_d; +wire ex3_dacr_type_q; +wire ex4_dacr_type_d; +wire ex4_dacr_type_q; +wire ex5_dacr_type_d; +wire ex5_dacr_type_q; +wire ex2_cache_acc_d; +wire ex2_cache_acc_q; +wire ex3_cache_acc_d; +wire ex3_cache_acc_q; +wire ex4_cache_acc_d; +wire ex4_cache_acc_q; +wire ex5_cache_acc_d; +wire ex5_cache_acc_q; +wire ex6_cache_acc_d; +wire ex6_cache_acc_q; +wire [0:`THREADS-1] ex2_thrd_id_d; +wire [0:`THREADS-1] ex2_thrd_id_q; +wire [0:`THREADS-1] ex3_thrd_id_d; +wire [0:`THREADS-1] ex3_thrd_id_q; +wire [0:`THREADS-1] ex4_thrd_id_d; +wire [0:`THREADS-1] ex4_thrd_id_q; +wire [0:`THREADS-1] ex5_thrd_id_d; +wire [0:`THREADS-1] ex5_thrd_id_q; +wire [0:`THREADS-1] ex6_thrd_id_d; +wire [0:`THREADS-1] ex6_thrd_id_q; +wire [0:31] ex2_instr_d; +wire [0:31] ex2_instr_q; +wire [0:31] ex3_instr_d; +wire [0:31] ex3_instr_q; +wire [0:31] ex4_instr_d; +wire [0:31] ex4_instr_q; +wire [0:31] ex5_instr_d; +wire [0:31] ex5_instr_q; +wire [0:AXU_TARGET_ENC-1] ex2_target_gpr_d; +wire [0:AXU_TARGET_ENC-1] ex2_target_gpr_q; +wire [0:AXU_TARGET_ENC-1] ex3_target_gpr_d; +wire [0:AXU_TARGET_ENC-1] ex3_target_gpr_q; +wire [0:AXU_TARGET_ENC-1] ex4_target_gpr_d; +wire [0:AXU_TARGET_ENC-1] ex4_target_gpr_q; +wire [0:AXU_TARGET_ENC-1] ex5_target_gpr_d; +wire [0:AXU_TARGET_ENC-1] ex5_target_gpr_q; +wire ex2_dcbt_instr_d; +wire ex2_dcbt_instr_q; +wire ex3_dcbt_instr_d; +wire ex3_dcbt_instr_q; +wire ex4_dcbt_instr_d; +wire ex4_dcbt_instr_q; +wire ex2_pfetch_val_d; +wire ex2_pfetch_val_q; +wire ex3_pfetch_val_d; +wire ex3_pfetch_val_q; +wire ex4_pfetch_val_d; +wire ex4_pfetch_val_q; +wire ex5_pfetch_val_d; +wire ex5_pfetch_val_q; +wire ex6_pfetch_val_d; +wire ex6_pfetch_val_q; +wire [0:`THREADS-1] ldp_pfetch_inPipe; +wire ex2_dcbtst_instr_d; +wire ex2_dcbtst_instr_q; +wire ex3_dcbtst_instr_d; +wire ex3_dcbtst_instr_q; +wire ex4_dcbtst_instr_d; +wire ex4_dcbtst_instr_q; +wire ex2_store_instr_d; +wire ex2_store_instr_q; +wire ex2_wchk_instr_d; +wire ex2_wchk_instr_q; +wire ex3_wchk_instr_d; +wire ex3_wchk_instr_q; +wire ex4_wchk_instr_d; +wire ex4_wchk_instr_q; +wire ex2_dcbst_instr_d; +wire ex2_dcbst_instr_q; +wire ex3_dcbst_instr_d; +wire ex3_dcbst_instr_q; +wire ex4_dcbst_instr_d; +wire ex4_dcbst_instr_q; +wire ex2_dcbf_instr_d; +wire ex2_dcbf_instr_q; +wire ex3_dcbf_instr_d; +wire ex3_dcbf_instr_q; +wire ex4_dcbf_instr_d; +wire ex4_dcbf_instr_q; +wire ex2_mtspr_trace_d; +wire ex2_mtspr_trace_q; +wire ex3_mtspr_trace_d; +wire ex3_mtspr_trace_q; +wire ex4_mtspr_trace_d; +wire ex4_mtspr_trace_q; +wire ex2_sync_instr_d; +wire ex2_sync_instr_q; +wire ex3_sync_instr_d; +wire ex3_sync_instr_q; +wire ex4_sync_instr_d; +wire ex4_sync_instr_q; +wire [0:1] ex2_l_fld_d; +wire [0:1] ex2_l_fld_q; +wire [0:1] ex3_l_fld_d; +wire [0:1] ex3_l_fld_q; +wire [0:1] ex4_l_fld_d; +wire [0:1] ex4_l_fld_q; +wire [0:1] ex5_l_fld_d; +wire [0:1] ex5_l_fld_q; +wire [0:3] ex3_l_fld_sel; +wire [0:1] ex3_l_fld_mbar; +wire [0:1] ex3_l_fld_sync; +wire [0:1] ex3_l_fld_tlbsync; +wire [0:1] ex3_l_fld_makeitso; +wire [0:1] ex3_l_fld; +wire ex2_dcbi_instr_d; +wire ex2_dcbi_instr_q; +wire ex3_dcbi_instr_d; +wire ex3_dcbi_instr_q; +wire ex4_dcbi_instr_d; +wire ex4_dcbi_instr_q; +wire ex2_dcbz_instr_d; +wire ex2_dcbz_instr_q; +wire ex3_dcbz_instr_d; +wire ex3_dcbz_instr_q; +wire ex4_dcbz_instr_d; +wire ex4_dcbz_instr_q; +wire ex2_icbi_instr_d; +wire ex2_icbi_instr_q; +wire ex3_icbi_instr_d; +wire ex3_icbi_instr_q; +wire ex4_icbi_instr_d; +wire ex4_icbi_instr_q; +wire ex2_mbar_instr_d; +wire ex2_mbar_instr_q; +wire ex3_mbar_instr_d; +wire ex3_mbar_instr_q; +wire ex4_mbar_instr_d; +wire ex4_mbar_instr_q; +wire ex2_makeitso_instr_d; +wire ex2_makeitso_instr_q; +wire ex3_makeitso_instr_d; +wire ex3_makeitso_instr_q; +wire ex4_makeitso_instr_d; +wire ex4_makeitso_instr_q; +wire ex2_dci_instr_d; +wire ex2_dci_instr_q; +wire ex3_dci_instr_d; +wire ex3_dci_instr_q; +wire ex4_dci_instr_d; +wire ex4_dci_instr_q; +wire ex4_dci_l2_val; +wire ex4_is_cinval; +wire ex4_is_cinval_drop; +wire ex2_ici_instr_d; +wire ex2_ici_instr_q; +wire ex3_ici_instr_d; +wire ex3_ici_instr_q; +wire ex4_ici_instr_d; +wire ex4_ici_instr_q; +wire ex4_ici_l2_val; +wire ex2_resv_instr_d; +wire ex2_resv_instr_q; +wire ex3_resv_instr_d; +wire ex3_resv_instr_q; +wire ex4_resv_instr_d; +wire ex4_resv_instr_q; +wire ex2_load_instr_d; +wire ex2_load_instr_q; +wire ex3_load_instr_d; +wire ex3_load_instr_q; +wire ex4_load_instr_d; +wire ex4_load_instr_q; +wire ex3_load_type; +wire ex4_load_type_d; +wire ex4_load_type_q; +wire ex4_gath_load_d; +wire ex4_gath_load_q; +wire ex3_store_instr_d; +wire ex3_store_instr_q; +wire ex4_store_instr_d; +wire ex4_store_instr_q; +wire ex3_le_mode; +wire ex4_le_mode_d; +wire ex4_le_mode_q; +wire ex5_wimge_i_bits_d; +wire ex5_wimge_i_bits_q; +wire [0:3] ex5_usr_bits_d; +wire [0:3] ex5_usr_bits_q; +wire [0:1] ex5_classid_d; +wire [0:1] ex5_classid_q; +wire ex5_derat_setHold_d; +wire ex5_derat_setHold_q; +wire ex3_icswx_type; +wire ex4_icswx_type; +wire ex4_stx_instr; +wire ex4_larx_instr; +wire is_mem_bar_op; +wire is_inval_op; +wire ex3_l1_lock_set; +wire is_lock_clr; +wire ex3_lru_upd; +wire stq6_tgpr_val; +wire [0:AXU_TARGET_ENC-1] reg_upd_ta_gpr; +wire lq_wren; +wire ex5_lq_wren; +wire ex5_lq_wren_d; +wire ex5_lq_wren_q; +wire ex6_lq_wren_d; +wire ex6_lq_wren_q; +wire axu_wren; +wire rel2_axu_wren_d; +wire rel2_axu_wren_q; +wire stq2_axu_val_d; +wire stq2_axu_val_q; +wire stq3_axu_val_d; +wire stq3_axu_val_q; +wire stq4_axu_val_d; +wire stq4_axu_val_q; +wire stq3_store_hit; +wire stq3_store_miss; +wire stq4_store_hit_d; +wire stq4_store_hit_q; +wire stq5_store_hit_d; +wire stq5_store_hit_q; +wire stq6_store_hit_d; +wire stq6_store_hit_q; +wire ex4_load_hit; +wire ex4_load_miss; +wire ex5_load_miss_d; +wire ex5_load_miss_q; +wire ex5_load_hit_d; +wire ex5_load_hit_q; +wire ex6_load_hit_d; +wire ex6_load_hit_q; +wire ex2_axu_op_val_d; +wire ex2_axu_op_val_q; +wire ex3_axu_op_val_d; +wire ex3_axu_op_val_q; +wire ex4_axu_op_val_d; +wire ex4_axu_op_val_q; +wire ex5_axu_op_val_d; +wire ex5_axu_op_val_q; +wire ex2_upd_form_d; +wire ex2_upd_form_q; +wire ex3_upd_form_d; +wire ex3_upd_form_q; +wire [0:2] ex2_axu_instr_type_d; +wire [0:2] ex2_axu_instr_type_q; +wire [0:2] ex3_axu_instr_type_d; +wire [0:2] ex3_axu_instr_type_q; +wire ex5_axu_wren_d; +wire ex5_axu_wren_q; +wire ex6_axu_wren_d; +wire ex6_axu_wren_q; +wire [0:AXU_TARGET_ENC-1] ex5_lq_ta_gpr_d; +wire [0:AXU_TARGET_ENC-1] ex5_lq_ta_gpr_q; +wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] ex6_lq_ta_gpr_d; +wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] ex6_lq_ta_gpr_q; +wire ex5_load_le_d; +wire ex5_load_le_q; +wire ex2_algebraic_d; +wire ex2_algebraic_q; +wire ex3_algebraic_d; +wire ex3_algebraic_q; +wire ex2_strg_index_d; +wire ex2_strg_index_q; +wire ex3_strg_index_d; +wire ex3_strg_index_q; +wire ex4_strg_index_d; +wire ex4_strg_index_q; +wire ex4_nogpr_upd; +wire ex1_th_b0; +wire ex2_th_fld_c_d; +wire ex2_th_fld_c_q; +wire ex3_th_fld_c_d; +wire ex3_th_fld_c_q; +wire ex4_th_fld_c_d; +wire ex4_th_fld_c_q; +wire ex2_th_fld_l2_d; +wire ex2_th_fld_l2_q; +wire ex3_th_fld_l2_d; +wire ex3_th_fld_l2_q; +wire ex4_th_fld_l2_d; +wire ex4_th_fld_l2_q; +wire ex2_undef_touch; +wire ex3_undef_touch_d; +wire ex3_undef_touch_q; +wire ex4_undef_touch_d; +wire ex4_undef_touch_q; +wire ex2_dcbtls_instr_d; +wire ex2_dcbtls_instr_q; +wire ex3_dcbtls_instr_d; +wire ex3_dcbtls_instr_q; +wire ex4_dcbtls_instr_d; +wire ex4_dcbtls_instr_q; +wire ex2_dcbtstls_instr_d; +wire ex2_dcbtstls_instr_q; +wire ex3_dcbtstls_instr_d; +wire ex3_dcbtstls_instr_q; +wire ex4_dcbtstls_instr_d; +wire ex4_dcbtstls_instr_q; +wire ex2_dcblc_instr_d; +wire ex2_dcblc_instr_q; +wire ex3_dcblc_instr_d; +wire ex3_dcblc_instr_q; +wire ex4_dcblc_instr_d; +wire ex4_dcblc_instr_q; +wire ex2_icblc_l2_instr_d; +wire ex2_icblc_l2_instr_q; +wire ex3_icblc_l2_instr_d; +wire ex3_icblc_l2_instr_q; +wire ex4_icblc_l2_instr_d; +wire ex4_icblc_l2_instr_q; +wire ex2_icbt_l2_instr_d; +wire ex2_icbt_l2_instr_q; +wire ex3_icbt_l2_instr_d; +wire ex3_icbt_l2_instr_q; +wire ex4_icbt_l2_instr_d; +wire ex4_icbt_l2_instr_q; +wire ex2_icbtls_l2_instr_d; +wire ex2_icbtls_l2_instr_q; +wire ex3_icbtls_l2_instr_d; +wire ex3_icbtls_l2_instr_q; +wire ex4_icbtls_l2_instr_d; +wire ex4_icbtls_l2_instr_q; +wire ex2_tlbsync_instr_d; +wire ex2_tlbsync_instr_q; +wire ex3_tlbsync_instr_d; +wire ex3_tlbsync_instr_q; +wire ex4_tlbsync_instr_d; +wire ex4_tlbsync_instr_q; +wire ex2_ldst_falign_d; +wire ex2_ldst_falign_q; +wire ex2_ldst_fexcpt_d; +wire ex2_ldst_fexcpt_q; +wire ex3_ldst_fexcpt_d; +wire ex3_ldst_fexcpt_q; +wire [0:8+`THREADS] xudbg1_dir_reg_d; +wire [0:8+`THREADS] xudbg1_dir_reg_q; +wire [0:PARBITS-1] xudbg1_parity_reg_d; +wire [0:PARBITS-1] xudbg1_parity_reg_q; +wire [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] xudbg2_tag_d; +wire [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] xudbg2_tag_q; +wire [0:24] epsc_t_reg[0:`THREADS-1]; +wire [0:23] lesr_t_reg[0:`THREADS-1]; +wire [0:31] way_lck_rmt; +wire spr_ccr2_ap_d; +wire spr_ccr2_ap_q; +wire spr_ccr2_en_trace_d; +wire spr_ccr2_en_trace_q; +wire spr_ccr2_ucode_dis_d; +wire spr_ccr2_ucode_dis_q; +wire spr_ccr2_notlb_d; +wire spr_ccr2_notlb_q; +wire clkg_ctl_override_d; +wire clkg_ctl_override_q; +wire spr_xucr0_wlk_d; +wire spr_xucr0_wlk_q; +wire spr_xucr0_mbar_ack_d; +wire spr_xucr0_mbar_ack_q; +wire spr_xucr0_tlbsync_d; +wire spr_xucr0_tlbsync_q; +wire spr_xucr0_dcdis_d; +wire spr_xucr0_dcdis_q; +wire spr_xucr0_aflsta_d; +wire spr_xucr0_aflsta_q; +wire spr_xucr0_flsta_d; +wire spr_xucr0_flsta_q; +wire spr_xucr0_mddp_d; +wire spr_xucr0_mddp_q; +wire spr_xucr0_mdcp_d; +wire spr_xucr0_mdcp_q; +wire spr_xucr4_mmu_mchk_d; +wire spr_xucr4_mmu_mchk_q; +wire spr_xucr4_mddmh_d; +wire spr_xucr4_mddmh_q; +wire [0:`THREADS-1] spr_xucr0_en_trace_um_d; +wire [0:`THREADS-1] spr_xucr0_en_trace_um_q; +wire ex4_mtspr_trace_tid_en; +wire ex4_mtspr_trace_en; +wire ex4_mtspr_trace_dis; +wire ex1_lsu_64bit_mode; +wire [0:`THREADS-1] ex1_lsu_64bit_mode_d; +wire [0:`THREADS-1] ex1_lsu_64bit_mode_q; +wire ex2_lsu_64bit_agen_d; +wire ex2_lsu_64bit_agen_q; +wire ex3_lsu_64bit_agen_d; +wire ex3_lsu_64bit_agen_q; +wire ex4_lsu_64bit_agen_d; +wire ex4_lsu_64bit_agen_q; +wire stq4_dcarr_wren_d; +wire stq4_dcarr_wren_q; +wire ex2_sgpr_instr_d; +wire ex2_sgpr_instr_q; +wire ex2_saxu_instr_d; +wire ex2_saxu_instr_q; +wire ex2_sdp_instr_d; +wire ex2_sdp_instr_q; +wire ex2_tgpr_instr_d; +wire ex2_tgpr_instr_q; +wire ex2_taxu_instr_d; +wire ex2_taxu_instr_q; +wire ex2_tdp_instr_d; +wire ex2_tdp_instr_q; +wire ex3_sgpr_instr_d; +wire ex3_sgpr_instr_q; +wire ex3_saxu_instr_d; +wire ex3_saxu_instr_q; +wire ex3_sdp_instr_d; +wire ex3_sdp_instr_q; +wire ex3_tgpr_instr_d; +wire ex3_tgpr_instr_q; +wire ex3_taxu_instr_d; +wire ex3_taxu_instr_q; +wire ex3_tdp_instr_d; +wire ex3_tdp_instr_q; +wire ex4_sgpr_instr_d; +wire ex4_sgpr_instr_q; +wire ex4_saxu_instr_d; +wire ex4_saxu_instr_q; +wire ex4_sdp_instr_d; +wire ex4_sdp_instr_q; +wire ex4_tgpr_instr_d; +wire ex4_tgpr_instr_q; +wire ex4_taxu_instr_d; +wire ex4_taxu_instr_q; +wire ex4_tdp_instr_d; +wire ex4_tdp_instr_q; +wire ex4_mfdpa_val; +wire ex4_mfdpf_val; +wire ex4_ditc_val; +wire ex3_mffgpr_val; +wire ex4_mffgpr_val; +wire ex4_mftgpr_val; +wire ex5_mftgpr_val_d; +wire ex5_mftgpr_val_q; +wire ex2_mftgpr_val; +wire ex3_mftgpr_val; +wire ex3_mfgpr_val; +wire ex4_moveOp_val_d; +wire ex4_moveOp_val_q; +wire stq6_moveOp_val_d; +wire stq6_moveOp_val_q; +wire data_touch_op; +wire inst_touch_op; +wire all_touch_op; +wire ddir_acc_instr; +wire ex4_c_dcbtls; +wire ex4_c_dcbtstls; +wire ex4_c_icbtls; +wire ex4_l2_dcbtls; +wire ex4_l2_dcbtstls; +wire ex4_l2_icbtls; +wire ex4_l2_icblc; +wire ex4_l2_dcblc; +wire ex4_blkable_touch_d; +wire ex4_blkable_touch_q; +wire ex5_blk_touch_d; +wire ex5_blk_touch_q; +wire ex6_blk_touch_d; +wire ex6_blk_touch_q; +wire ex4_excp_touch; +wire ex4_cinh_touch; +wire ex4_blk_touch; +wire ex4_blk_touch_instr; +wire ex3_local_dcbf; +wire ex2_mutex_hint_d; +wire ex2_mutex_hint_q; +wire ex3_mutex_hint_d; +wire ex3_mutex_hint_q; +wire ex4_mutex_hint_d; +wire ex4_mutex_hint_q; +wire [64-`REAL_IFAR_WIDTH:63] ex4_p_addr; +wire [64-(2**`GPR_WIDTH_ENC):63] ex3_eff_addr_d; +wire [64-(2**`GPR_WIDTH_ENC):63] ex3_eff_addr_q; +wire [64-(2**`GPR_WIDTH_ENC):63] ex4_eff_addr_d; +wire [64-(2**`GPR_WIDTH_ENC):63] ex4_eff_addr_q; +wire [64-(2**`GPR_WIDTH_ENC):63] ex5_eff_addr_d; +wire [64-(2**`GPR_WIDTH_ENC):63] ex5_eff_addr_q; +wire ex2_lockset_instr; +wire ex3_undef_lockset_d; +wire ex3_undef_lockset_q; +wire ex4_undef_lockset_d; +wire ex4_undef_lockset_q; +wire ex4_cinh_lockset; +wire ex4_l1dc_dis_lockset; +wire ex4_l1dc_dis_lockclr; +wire ex4_noop_lockset; +wire ex5_unable_2lock_d; +wire ex5_unable_2lock_q; +wire ex6_stq5_unable_2lock_d; +wire ex6_stq5_unable_2lock_q; +wire ex2_stq_val_cacc; +wire ex2_stq_nval_cacc; +wire ex2_stq_val_req; +wire ex3_stq_val_req_d; +wire ex3_stq_val_req_q; +wire ex4_stq_val_req_d; +wire ex4_stq_val_req_q; +wire ex5_load_instr_d; +wire ex5_load_instr_q; +wire ex2_mword_instr_d; +wire ex2_mword_instr_q; +wire ex3_mword_instr_d; +wire ex3_mword_instr_q; +wire stq4_store_miss_d; +wire stq4_store_miss_q; +wire ex5_perf_dcbt_d; +wire ex5_perf_dcbt_q; +reg [0:23] ex5_spr_lesr; +wire perf_stq_stores; +wire perf_stq_store_miss; +wire perf_stq_stcx_exec; +wire perf_stq_axu_store; +wire perf_stq_wclr; +wire perf_stq_wclr_set; +wire perf_com_loadmiss; +wire perf_com_cinh_loads; +wire perf_com_loads; +wire perf_com_dcbt_sent; +wire perf_com_dcbt_hit; +wire perf_com_axu_load; +wire perf_com_load_fwd; +wire perf_ex6_pfetch_iss; +wire perf_ex6_pfetch_hit; +wire perf_ex6_pfetch_emiss; +wire perf_ex6_align_flush; +wire perf_ex6_dir_restart; +wire perf_ex6_dec_restart; +wire perf_ex6_wNComp_restart; +wire perf_ex6_pfetch_ldq_full; +wire perf_ex6_pfetch_ldq_hit; +wire perf_ex6_pfetch_stq; +wire perf_ex6_ldq_full; +wire perf_ex6_ldq_hit; +wire perf_ex6_lgq_full; +wire perf_ex6_lgq_hit; +wire perf_ex6_stq_sametid; +wire perf_ex6_stq_difftid; +wire perf_ex6_derat_attmpts; +wire [0:10] ex5_cmmt_events; +wire [0:6+`THREADS-1] stq_perf_events; +wire [0:18+`THREADS-1] ex6_dcc_perf_events; +wire perf_com_watch_set; +wire perf_com_watch_dup; +wire perf_com_wchkall; +wire perf_com_wchkall_succ; +wire ex3_watch_clr_entry; +wire ex3_watch_clr_all; +wire ex4_local_dcbf_d; +wire ex4_local_dcbf_q; +wire ex2_msgsnd_instr_d; +wire ex2_msgsnd_instr_q; +wire ex3_msgsnd_instr_d; +wire ex3_msgsnd_instr_q; +wire ex4_msgsnd_instr_d; +wire ex4_msgsnd_instr_q; +wire ex4_l2load_type_d; +wire ex4_l2load_type_q; +wire ex2_ldawx_instr_d; +wire ex2_ldawx_instr_q; +wire ex3_ldawx_instr_d; +wire ex3_ldawx_instr_q; +wire ex4_ldawx_instr_d; +wire ex4_ldawx_instr_q; +wire ex5_ldawx_instr_d; +wire ex5_ldawx_instr_q; +wire ex2_wclr_instr_d; +wire ex2_wclr_instr_q; +wire ex3_wclr_instr_d; +wire ex3_wclr_instr_q; +wire ex4_wclr_instr_d; +wire ex4_wclr_instr_q; +wire ex4_wclr_all_val; +wire [0:4] ex3_opsize; +wire [0:2] ex3_opsize_enc; +wire [0:2] ex4_opsize_enc_d; +wire [0:2] ex4_opsize_enc_q; +wire [0:2] ex5_opsize_enc_d; +wire [0:2] ex5_opsize_enc_q; +wire [1:4] ex5_opsize; +wire [0:7] ex5_byte_mask; +wire [0:4] ex3_rot_size; +wire [0:4] ex3_rot_sel_non_le; +wire [0:4] ex3_alg_bit_le_sel; +wire [0:`ITAG_SIZE_ENC-1] ex2_itag_d; +wire [0:`ITAG_SIZE_ENC-1] ex2_itag_q; +wire [0:`ITAG_SIZE_ENC-1] ex3_itag_d; +wire [0:`ITAG_SIZE_ENC-1] ex3_itag_q; +wire [0:`ITAG_SIZE_ENC-1] ex4_itag_d; +wire [0:`ITAG_SIZE_ENC-1] ex4_itag_q; +wire [0:`ITAG_SIZE_ENC-1] ex5_itag_d; +wire [0:`ITAG_SIZE_ENC-1] ex5_itag_q; +wire [0:`ITAG_SIZE_ENC-1] ex6_itag_d; +wire [0:`ITAG_SIZE_ENC-1] ex6_itag_q; +wire ex5_drop_rel_d; +wire ex5_drop_rel_q; +wire ex2_icswx_instr_d; +wire ex2_icswx_instr_q; +wire ex3_icswx_instr_d; +wire ex3_icswx_instr_q; +wire ex4_icswx_instr_d; +wire ex4_icswx_instr_q; +wire ex2_icswxdot_instr_d; +wire ex2_icswxdot_instr_q; +wire ex3_icswxdot_instr_d; +wire ex3_icswxdot_instr_q; +wire ex4_icswxdot_instr_d; +wire ex4_icswxdot_instr_q; +wire ex2_icswx_epid_d; +wire ex2_icswx_epid_q; +wire ex3_icswx_epid_d; +wire ex3_icswx_epid_q; +wire ex4_icswx_epid_d; +wire ex4_icswx_epid_q; +wire ex5_icswx_epid_d; +wire ex5_icswx_epid_q; +wire ex4_c_inh_drop_op_d; +wire ex4_c_inh_drop_op_q; +wire ex4_cache_enabled; +wire ex4_cache_inhibited; +wire [0:8] ex4_mem_attr; +wire [0:AXU_TARGET_ENC-1] rel2_ta_gpr_d; +wire [0:AXU_TARGET_ENC-1] rel2_ta_gpr_q; +wire rv1_binv_val_d; +wire rv1_binv_val_q; +wire ex0_binv_val_d; +wire ex0_binv_val_q; +wire ex1_binv_val_d; +wire ex1_binv_val_q; +wire ex2_binv_val_d; +wire ex2_binv_val_q; +wire ex3_binv_val_d; +wire ex3_binv_val_q; +wire ex4_binv_val_d; +wire ex4_binv_val_q; +wire ex0_derat_snoop_val_d; +wire ex0_derat_snoop_val_q; +wire ex1_derat_snoop_val_d; +wire ex1_derat_snoop_val_q; +wire spr_msr_fp; +wire [0:`THREADS-1] spr_msr_fp_d; +wire [0:`THREADS-1] spr_msr_fp_q; +wire spr_msr_spv; +wire [0:`THREADS-1] spr_msr_spv_d; +wire [0:`THREADS-1] spr_msr_spv_q; +wire [0:`THREADS-1] spr_msr_gs_d; +wire [0:`THREADS-1] spr_msr_gs_q; +wire [0:`THREADS-1] spr_msr_pr_d; +wire [0:`THREADS-1] spr_msr_pr_q; +wire [0:`THREADS-1] spr_msr_ds_d; +wire [0:`THREADS-1] spr_msr_ds_q; +wire [0:`THREADS-1] spr_msr_de_d; +wire [0:`THREADS-1] spr_msr_de_q; +wire [0:`THREADS-1] spr_dbcr0_idm_d; +wire [0:`THREADS-1] spr_dbcr0_idm_q; +wire [0:`THREADS-1] spr_epcr_duvd_d; +wire [0:`THREADS-1] spr_epcr_duvd_q; +wire [0:7] spr_lpidr_d; +wire [0:7] spr_lpidr_q; +wire [0:13] spr_pid_d[0:`THREADS-1]; +wire [0:13] spr_pid_q[0:`THREADS-1]; +wire [0:31] spr_acop_ct[0:`THREADS-1]; +wire [0:31] spr_hacop_ct[0:`THREADS-1]; +wire ex2_epsc_egs; +wire ex2_epsc_epr; +wire ex2_msr_gs; +wire ex2_msr_pr; +wire ex3_icswx_gs_d; +wire ex3_icswx_gs_q; +wire ex3_icswx_pr_d; +wire ex3_icswx_pr_q; +wire ex4_icswx_ct_val_d; +wire ex4_icswx_ct_val_q; +reg [32:63] ex3_acop_ct; +reg [32:63] ex3_hacop_ct; +wire [32:63] ex3_acop_ct_npr; +wire [32:63] ex3_cop_ct; +wire [0:1] ex3_icswx_ct; +wire [0:1] ex4_icswx_ct_d; +wire [0:1] ex4_icswx_ct_q; +wire ex4_icswx_ct; +wire ex4_icswx_dsi; +wire [0:`THREADS-1] dbg_int_en_d; +wire [0:`THREADS-1] dbg_int_en_q; +reg [0:13] stq2_pid; +reg [0:24] stq2_epsc; +wire [0:24] stq2_icswx_epid; +wire [0:24] stq2_icswx_nepid; +wire [0:24] stq3_icswx_data_d; +wire [0:24] stq3_icswx_data_q; +wire ex4_spr_msr_pr; +wire [0:`THREADS-1] hypervisor_state; +wire ex4_load_val; +wire [0:5] ex5_ttype_d; +wire [0:5] ex5_ttype_q; +wire ex4_store_val; +wire ex4_othreq_val; +wire ex3_illeg_lswx; +wire ex3_strg_index_noop; +wire ex4_strg_gate_d; +wire ex4_strg_gate_q; +wire ex3_wNComp; +wire [0:`THREADS-1] ex3_wNComp_tid; +wire ex3_wNComp_rcvd; +wire ex4_wNComp_rcvd_d; +wire ex4_wNComp_rcvd_q; +wire ex4_wNComp_d; +wire ex4_wNComp_q; +wire ex5_wNComp_d; +wire ex5_wNComp_q; +wire ex5_wNComp_cr_upd_d; +wire ex5_wNComp_cr_upd_q; +wire ex4_wNComp_excp_restart; +wire ex4_2younger_restart; +wire ex5_flush_req; +wire ex5_blk_tlb_req; +wire ex5_flush_pfetch; +wire [0:1] ex5_dvc_en_d; +wire [0:1] ex5_dvc_en_q; +wire [0:1] ex6_dvc_en_d; +wire [0:1] ex6_dvc_en_q; +wire ex4_is_inval_op_d; +wire ex4_is_inval_op_q; +wire [0:15] op_sel; +wire [0:15] beC840_en; +wire [0:15] be3210_en; +wire [0:15] byte_en; +wire [0:15] ex3_byte_en; +wire ex2_sfx_val_d; +wire ex2_sfx_val_q; +wire ex3_sfx_val_d; +wire ex3_sfx_val_q; +wire ex4_sfx_val_d; +wire ex4_sfx_val_q; +wire ex2_ucode_val_d; +wire ex2_ucode_val_q; +wire ex3_ucode_val_d; +wire ex3_ucode_val_q; +wire ex4_ucode_val_d; +wire ex4_ucode_val_q; +wire ex6_lq_comp_rpt_d; +wire ex6_lq_comp_rpt_q; +wire [0:`THREADS-1] lq0_iu_execute_vld_d; +wire [0:`THREADS-1] lq0_iu_execute_vld_q; +wire [0:`ITAG_SIZE_ENC-1] lq0_iu_itag_d; +wire [0:`ITAG_SIZE_ENC-1] lq0_iu_itag_q; +wire lq0_iu_flush2ucode_type_d; +wire lq0_iu_flush2ucode_type_q; +wire [0:`THREADS-1] lq0_iu_recirc_val_d; +wire [0:`THREADS-1] lq0_iu_recirc_val_q; +wire lq0_iu_flush2ucode_d; +wire lq0_iu_flush2ucode_q; +wire [0:`THREADS-1] lq0_iu_dear_val_d; +wire [0:`THREADS-1] lq0_iu_dear_val_q; +wire [64-(2**`GPR_WIDTH_ENC):63] lq0_iu_eff_addr_d; +wire [64-(2**`GPR_WIDTH_ENC):63] lq0_iu_eff_addr_q; +wire lq0_iu_n_flush_d; +wire lq0_iu_n_flush_q; +wire lq0_iu_np1_flush_d; +wire lq0_iu_np1_flush_q; +wire lq0_iu_exception_val_d; +wire lq0_iu_exception_val_q; +wire [0:5] lq0_iu_exception_d; +wire [0:5] lq0_iu_exception_q; +wire lq0_iu_dacr_type_d; +wire lq0_iu_dacr_type_q; +wire [0:3] lq0_iu_dacrw_d; +wire [0:3] lq0_iu_dacrw_q; +wire [0:31] lq0_iu_instr_d; +wire [0:31] lq0_iu_instr_q; +wire ex4_spec_load_miss; +wire ex5_spec_load_miss_d; +wire ex5_spec_load_miss_q; +wire ex5_spec_itag_vld_d; +wire ex5_spec_itag_vld_q; +wire [0:`ITAG_SIZE_ENC-1] ex4_spec_itag; +wire [0:`THREADS-1] ex4_spec_thrd_id; +wire [0:`ITAG_SIZE_ENC-1] ex5_spec_itag_d; +wire [0:`ITAG_SIZE_ENC-1] ex5_spec_itag_q; +wire [0:`THREADS-1] ex5_spec_tid_d; +wire [0:`THREADS-1] ex5_spec_tid_q; +wire ex4_guarded_load; +wire ex5_blk_pf_load_d; +wire ex5_blk_pf_load_q; +wire ex4_lq_wNComp_req; +wire ex4_wNcomp_oth; +wire ex4_wNComp_req; +wire ex5_lq_wNComp_val_d; +wire ex5_lq_wNComp_val_q; +wire ex6_lq_wNComp_val_d; +wire ex6_lq_wNComp_val_q; +wire ex5_wNComp_ord_d; +wire ex5_wNComp_ord_q; +wire ex3_lswx_restart; +wire ex4_lswx_restart_d; +wire ex4_lswx_restart_q; +wire ex3_icswx_restart; +wire ex4_icswx_restart_d; +wire ex4_icswx_restart_q; +wire ex4_restart_val; +wire ex5_restart_val_d; +wire ex5_restart_val_q; +wire ex5_derat_restart_d; +wire ex5_derat_restart_q; +wire ex6_derat_restart_d; +wire ex6_derat_restart_q; +wire ex5_dir_restart_d; +wire ex5_dir_restart_q; +wire ex6_dir_restart_d; +wire ex6_dir_restart_q; +wire ex5_dec_restart_d; +wire ex5_dec_restart_q; +wire ex6_dec_restart_d; +wire ex6_dec_restart_q; +wire ex4_derat_itagHit_d; +wire ex4_derat_itagHit_q; +wire ex6_stq_restart_val_d; +wire ex6_stq_restart_val_q; +wire ex6_restart_val_d; +wire ex6_restart_val_q; +wire ex5_execute_vld; +wire ex5_execute_vld_d; +wire ex5_execute_vld_q; +wire ex5_flush2ucode_type_d; +wire ex5_flush2ucode_type_q; +wire ex5_recirc_val; +wire ex5_recirc_val_d; +wire ex5_recirc_val_q; +wire [0:`THREADS-1] lq0_rpt_thrd_id; +wire ex5_wchkall_cplt; +wire ex5_wchkall_cplt_d; +wire ex5_wchkall_cplt_q; +wire ex6_misalign_flush_d; +wire ex6_misalign_flush_q; +wire [0:`THREADS-1] ldq_idle_d; +wire [0:`THREADS-1] ldq_idle_q; +wire ex5_lq_comp_rpt_val; +wire ex5_restart_val; +wire ex5_lq_req_abort; +wire ex5_ldq_restart_val; +wire ex5_stq_restart_miss; +wire ex5_stq_restart_val; +wire ex4_is_sync_d; +wire ex4_is_sync_q; +wire ex4_l1_lock_set_d; +wire ex4_l1_lock_set_q; +wire ex5_l1_lock_set_d; +wire ex5_l1_lock_set_q; +wire ex4_lock_clr_d; +wire ex4_lock_clr_q; +wire ex5_lock_clr_d; +wire ex5_lock_clr_q; +wire rel2_xu_wren_d; +wire rel2_xu_wren_q; +wire stq2_store_val_d; +wire stq2_store_val_q; +wire stq3_store_val_d; +wire stq3_store_val_q; +wire stq4_store_val_d; +wire stq4_store_val_q; +wire stq2_ci_d; +wire stq2_ci_q; +wire stq3_ci_d; +wire stq3_ci_q; +wire stq2_resv_d; +wire stq2_resv_q; +wire stq3_resv_d; +wire stq3_resv_q; +wire stq2_wclr_val_d; +wire stq2_wclr_val_q; +wire stq3_wclr_val_d; +wire stq3_wclr_val_q; +wire stq4_wclr_val_d; +wire stq4_wclr_val_q; +wire stq2_wclr_all_set_d; +wire stq2_wclr_all_set_q; +wire stq3_wclr_all_set_d; +wire stq3_wclr_all_set_q; +wire stq4_wclr_all_set_d; +wire stq4_wclr_all_set_q; +wire stq4_rec_stcx_d; +wire stq4_rec_stcx_q; +wire [0:`ITAG_SIZE_ENC-1] stq6_itag_d; +wire [0:`ITAG_SIZE_ENC-1] stq6_itag_q; +wire [0:AXU_TARGET_ENC-1] stq6_tgpr_d; +wire [0:AXU_TARGET_ENC-1] stq6_tgpr_q; +wire [0:`THREADS-1] stq2_thrd_id_d; +wire [0:`THREADS-1] stq2_thrd_id_q; +wire [0:`THREADS-1] stq3_thrd_id_d; +wire [0:`THREADS-1] stq3_thrd_id_q; +wire [0:`THREADS-1] stq4_thrd_id_d; +wire [0:`THREADS-1] stq4_thrd_id_q; +wire [0:`THREADS-1] stq5_thrd_id_d; +wire [0:`THREADS-1] stq5_thrd_id_q; +wire [0:`THREADS-1] stq6_thrd_id_d; +wire [0:`THREADS-1] stq6_thrd_id_q; +wire [0:`THREADS-1] stq7_thrd_id_d; +wire [0:`THREADS-1] stq7_thrd_id_q; +wire [0:`THREADS-1] stq8_thrd_id_d; +wire [0:`THREADS-1] stq8_thrd_id_q; +wire stq2_epid_val_d; +wire stq2_epid_val_q; +wire stq2_mftgpr_val_d; +wire stq2_mftgpr_val_q; +wire stq3_mftgpr_val_d; +wire stq3_mftgpr_val_q; +wire stq4_mftgpr_val_d; +wire stq4_mftgpr_val_q; +wire stq5_mftgpr_val_d; +wire stq5_mftgpr_val_q; +wire stq6_mftgpr_val_d; +wire stq6_mftgpr_val_q; +wire stq7_mftgpr_val_d; +wire stq7_mftgpr_val_q; +wire stq8_mftgpr_val_d; +wire stq8_mftgpr_val_q; +wire stq2_mfdpf_val_d; +wire stq2_mfdpf_val_q; +wire stq3_mfdpf_val_d; +wire stq3_mfdpf_val_q; +wire stq4_mfdpf_val_d; +wire stq4_mfdpf_val_q; +wire stq5_mfdpf_val_d; +wire stq5_mfdpf_val_q; +wire stq2_mfdpa_val_d; +wire stq2_mfdpa_val_q; +wire stq3_mfdpa_val_d; +wire stq3_mfdpa_val_q; +wire stq4_mfdpa_val_d; +wire stq4_mfdpa_val_q; +wire stq5_mfdpa_val_d; +wire stq5_mfdpa_val_q; +wire stq6_mfdpa_val_d; +wire stq6_mfdpa_val_q; +wire [0:`CR_POOL_ENC-1] ex2_cr_fld_d; +wire [0:`CR_POOL_ENC-1] ex2_cr_fld_q; +wire [0:`CR_POOL_ENC-1] ex3_cr_fld_d; +wire [0:`CR_POOL_ENC-1] ex3_cr_fld_q; +wire [0:`CR_POOL_ENC-1] ex4_cr_fld_d; +wire [0:`CR_POOL_ENC-1] ex4_cr_fld_q; +wire [0:`CR_POOL_ENC+`THREADS_POOL_ENC-1] ex5_cr_fld_d; +wire [0:`CR_POOL_ENC+`THREADS_POOL_ENC-1] ex5_cr_fld_q; +wire ex4_cr_sel; +wire [0:AXU_TARGET_ENC-1] ex4_cr_fld; +wire [0:`CR_WIDTH-1] ex5_cr_wd; +wire [0:`UCODE_ENTRIES_ENC-1] ex2_ucode_cnt_d; +wire [0:`UCODE_ENTRIES_ENC-1] ex2_ucode_cnt_q; +wire [0:`UCODE_ENTRIES_ENC-1] ex3_ucode_cnt_d; +wire [0:`UCODE_ENTRIES_ENC-1] ex3_ucode_cnt_q; +wire ex2_ucode_op_d; +wire ex2_ucode_op_q; +wire ex3_ucode_op_d; +wire ex3_ucode_op_q; +wire ex4_ucode_op_d; +wire ex4_ucode_op_q; +wire ex4_cline_chk; +wire ex4_send_l2; +wire ex4_has_data; +wire ex4_dReq_val; +wire ex4_excp_rpt_val; +wire ex4_ucode_rpt; +wire ex4_ucode_rpt_val; +wire ex4_mffgpr_rpt_val; +wire ex4_ucode_restart; +wire ex4_sfx_excpt_det; +wire ex4_excp_det; +wire ex4_wNComp_excp; +wire dir_arr_rd_rv1_done; +wire [0:1] dir_arr_rd_cntrl; +wire dir_arr_rd_val_d; +wire dir_arr_rd_val_q; +wire [0:`THREADS-1] dir_arr_rd_tid_d; +wire [0:`THREADS-1] dir_arr_rd_tid_q; +wire dir_arr_rd_rv1_val_d; +wire dir_arr_rd_rv1_val_q; +wire dir_arr_rd_ex0_done_d; +wire dir_arr_rd_ex0_done_q; +wire dir_arr_rd_ex1_done_d; +wire dir_arr_rd_ex1_done_q; +wire dir_arr_rd_ex2_done_d; +wire dir_arr_rd_ex2_done_q; +wire dir_arr_rd_ex3_done_d; +wire dir_arr_rd_ex3_done_q; +wire dir_arr_rd_ex4_done_d; +wire dir_arr_rd_ex4_done_q; +wire dir_arr_rd_ex5_done_d; +wire dir_arr_rd_ex5_done_q; +wire dir_arr_rd_ex6_done_d; +wire dir_arr_rd_ex6_done_q; +wire dir_arr_rd_busy; +wire [0:`THREADS-1] dir_arr_rd_tid_busy; +wire [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] dir_arr_rd_tag; +wire [0:1+`THREADS] dir_arr_rd_directory; +wire [0:PARBITS-1] dir_arr_rd_parity; +wire [0:6] dir_arr_rd_lru; +wire ex4_dacrw1_cmpr; +wire ex4_dacrw2_cmpr; +wire ex4_dacrw3_cmpr; +wire ex4_dacrw4_cmpr; +wire ex5_dacrw_rpt_val; +wire [0:3] ex5_dacrw_cmpr; +wire [0:3] ex5_dacrw_cmpr_d; +wire [0:3] ex5_dacrw_cmpr_q; +wire [0:3] ex6_dacrw_cmpr_d; +wire [0:3] ex6_dacrw_cmpr_q; +wire ex4_dac_int_det; +wire ex4_dbg_int_en; +wire ex5_flush2ucode; +wire ex5_n_flush; +wire ex5_np1_flush; +wire ex5_exception_val; +wire [0:5] ex5_exception; +wire [0:`THREADS-1] ex5_dear_val; +wire ex5_misalign_flush; +wire [0:`THREADS-1] lq_ram_data_val; +wire [0:`THREADS-1] ex6_ram_thrd; +wire [0:`THREADS-1] ex6_ram_active_thrd; +wire [0:`THREADS-1] stq8_ram_thrd; +wire [0:`THREADS-1] stq8_ram_active_thrd; +wire [0:`THREADS-1] rel2_ram_thrd; +wire [0:`THREADS-1] rel2_ram_active_thrd; +wire [0:`THREADS-1] pc_lq_ram_active_d; +wire [0:`THREADS-1] pc_lq_ram_active_q; +wire lq_pc_ram_data_val_d; +wire lq_pc_ram_data_val_q; +wire ex1_instr_act; +wire ex1_stg_act; +wire ex1_stg_act_d; +wire ex1_stg_act_q; +wire ex2_stg_act_d; +wire ex2_stg_act_q; +wire ex3_stg_act_d; +wire ex3_stg_act_q; +wire ex4_stg_act_d; +wire ex4_stg_act_q; +wire ex5_stg_act_d; +wire ex5_stg_act_q; +wire ex6_stg_act_d; +wire ex6_stg_act_q; +wire binv1_stg_act; +wire binv2_stg_act_d; +wire binv2_stg_act_q; +wire binv3_stg_act_d; +wire binv3_stg_act_q; +wire binv4_stg_act_d; +wire binv4_stg_act_q; +wire binv5_stg_act_d; +wire binv5_stg_act_q; +wire binv6_stg_act_d; +wire binv6_stg_act_q; +wire ex2_binv2_stg_act; +wire ex3_binv3_stg_act; +wire ex4_binv4_stg_act; +wire ex5_binv5_stg_act; +wire ex6_binv6_stg_act; +wire ex4_darr_rd_act; +wire ex5_darr_rd_act; +wire lq0_iu_act; +wire stq1_stg_act; +wire stq2_stg_act_d; +wire stq2_stg_act_q; +wire stq3_stg_act_d; +wire stq3_stg_act_q; +wire stq4_stg_act_d; +wire stq4_stg_act_q; +wire stq5_stg_act_d; +wire stq5_stg_act_q; + +wire fgen_ex1_stg_flush_int; +wire fgen_ex2_stg_flush_int; +wire fgen_ex3_stg_flush_int; +wire fgen_ex4_stg_flush_int; +wire fgen_ex5_stg_flush_int; +wire fgen_ex4_cp_flush_int; +wire fgen_ex5_cp_flush; +wire fgen_scan_in; +wire fgen_scan_out; + +wire perf_ex6_derat_restarts; + +//-------------------------- +// register constants +//-------------------------- +parameter iu_lq_recirc_val_offset = 0; +parameter iu_lq_cp_next_itag_offset = iu_lq_recirc_val_offset + `THREADS; +parameter iu_lq_cp_flush_offset = iu_lq_cp_next_itag_offset + (`THREADS*`ITAG_SIZE_ENC); +parameter xer_lq_cp_rd_so_offset = iu_lq_cp_flush_offset + `THREADS; +parameter ex0_i0_vld_offset = xer_lq_cp_rd_so_offset + `THREADS; +parameter ex0_i0_ucode_preissue_offset = ex0_i0_vld_offset + `THREADS; +parameter ex0_i0_2ucode_offset = ex0_i0_ucode_preissue_offset + 1; +parameter ex0_i0_ucode_cnt_offset = ex0_i0_2ucode_offset + 1; +parameter ex0_i1_vld_offset = ex0_i0_ucode_cnt_offset + `UCODE_ENTRIES_ENC; +parameter ex0_i1_ucode_preissue_offset = ex0_i1_vld_offset + `THREADS; +parameter ex0_i1_2ucode_offset = ex0_i1_ucode_preissue_offset + 1; +parameter ex0_i1_ucode_cnt_offset = ex0_i1_2ucode_offset + 1; +parameter ex2_optype1_offset = ex0_i1_ucode_cnt_offset + `UCODE_ENTRIES_ENC; +parameter ex2_optype2_offset = ex2_optype1_offset + 1; +parameter ex2_optype4_offset = ex2_optype2_offset + 1; +parameter ex2_optype8_offset = ex2_optype4_offset + 1; +parameter ex2_optype16_offset = ex2_optype8_offset + 1; +parameter ex3_optype1_offset = ex2_optype16_offset + 1; +parameter ex3_optype2_offset = ex3_optype1_offset + 1; +parameter ex3_optype4_offset = ex3_optype2_offset + 1; +parameter ex3_optype8_offset = ex3_optype4_offset + 1; +parameter ex3_optype16_offset = ex3_optype8_offset + 1; +parameter ex3_dacr_type_offset = ex3_optype16_offset + 1; +parameter ex4_dacr_type_offset = ex3_dacr_type_offset + 1; +parameter ex5_dacr_type_offset = ex4_dacr_type_offset + 1; +parameter ex2_cache_acc_offset = ex5_dacr_type_offset + 1; +parameter ex3_cache_acc_offset = ex2_cache_acc_offset + 1; +parameter ex4_cache_acc_offset = ex3_cache_acc_offset + 1; +parameter ex5_cache_acc_offset = ex4_cache_acc_offset + 1; +parameter ex6_cache_acc_offset = ex5_cache_acc_offset + 1; +parameter ex2_thrd_id_offset = ex6_cache_acc_offset + 1; +parameter ex3_thrd_id_offset = ex2_thrd_id_offset + `THREADS; +parameter ex4_thrd_id_offset = ex3_thrd_id_offset + `THREADS; +parameter ex5_thrd_id_offset = ex4_thrd_id_offset + `THREADS; +parameter ex6_thrd_id_offset = ex5_thrd_id_offset + `THREADS; +parameter ex2_instr_offset = ex6_thrd_id_offset + `THREADS; +parameter ex3_instr_offset = ex2_instr_offset + 32; +parameter ex4_instr_offset = ex3_instr_offset + 32; +parameter ex5_instr_offset = ex4_instr_offset + 32; +parameter ex2_target_gpr_offset = ex5_instr_offset + 32; +parameter ex3_target_gpr_offset = ex2_target_gpr_offset + AXU_TARGET_ENC; +parameter ex4_target_gpr_offset = ex3_target_gpr_offset + AXU_TARGET_ENC; +parameter ex5_target_gpr_offset = ex4_target_gpr_offset + AXU_TARGET_ENC; +parameter ex2_dcbt_instr_offset = ex5_target_gpr_offset + AXU_TARGET_ENC; +parameter ex3_dcbt_instr_offset = ex2_dcbt_instr_offset + 1; +parameter ex4_dcbt_instr_offset = ex3_dcbt_instr_offset + 1; +parameter ex2_pfetch_val_offset = ex4_dcbt_instr_offset + 1; +parameter ex3_pfetch_val_offset = ex2_pfetch_val_offset + 1; +parameter ex4_pfetch_val_offset = ex3_pfetch_val_offset + 1; +parameter ex5_pfetch_val_offset = ex4_pfetch_val_offset + 1; +parameter ex6_pfetch_val_offset = ex5_pfetch_val_offset + 1; +parameter ex2_dcbtst_instr_offset = ex6_pfetch_val_offset + 1; +parameter ex3_dcbtst_instr_offset = ex2_dcbtst_instr_offset + 1; +parameter ex4_dcbtst_instr_offset = ex3_dcbtst_instr_offset + 1; +parameter ex2_wchk_instr_offset = ex4_dcbtst_instr_offset + 1; +parameter ex3_wchk_instr_offset = ex2_wchk_instr_offset + 1; +parameter ex4_wchk_instr_offset = ex3_wchk_instr_offset + 1; +parameter ex2_dcbst_instr_offset = ex4_wchk_instr_offset + 1; +parameter ex3_dcbst_instr_offset = ex2_dcbst_instr_offset + 1; +parameter ex4_dcbst_instr_offset = ex3_dcbst_instr_offset + 1; +parameter ex2_dcbf_instr_offset = ex4_dcbst_instr_offset + 1; +parameter ex3_dcbf_instr_offset = ex2_dcbf_instr_offset + 1; +parameter ex4_dcbf_instr_offset = ex3_dcbf_instr_offset + 1; +parameter ex2_mtspr_trace_offset = ex4_dcbf_instr_offset + 1; +parameter ex3_mtspr_trace_offset = ex2_mtspr_trace_offset + 1; +parameter ex4_mtspr_trace_offset = ex3_mtspr_trace_offset + 1; +parameter ex2_sync_instr_offset = ex4_mtspr_trace_offset + 1; +parameter ex3_sync_instr_offset = ex2_sync_instr_offset + 1; +parameter ex4_sync_instr_offset = ex3_sync_instr_offset + 1; +parameter ex2_l_fld_offset = ex4_sync_instr_offset + 1; +parameter ex3_l_fld_offset = ex2_l_fld_offset + 2; +parameter ex4_l_fld_offset = ex3_l_fld_offset + 2; +parameter ex5_l_fld_offset = ex4_l_fld_offset + 2; +parameter ex2_dcbi_instr_offset = ex5_l_fld_offset + 2; +parameter ex3_dcbi_instr_offset = ex2_dcbi_instr_offset + 1; +parameter ex4_dcbi_instr_offset = ex3_dcbi_instr_offset + 1; +parameter ex2_dcbz_instr_offset = ex4_dcbi_instr_offset + 1; +parameter ex3_dcbz_instr_offset = ex2_dcbz_instr_offset + 1; +parameter ex4_dcbz_instr_offset = ex3_dcbz_instr_offset + 1; +parameter ex2_icbi_instr_offset = ex4_dcbz_instr_offset + 1; +parameter ex3_icbi_instr_offset = ex2_icbi_instr_offset + 1; +parameter ex4_icbi_instr_offset = ex3_icbi_instr_offset + 1; +parameter ex2_mbar_instr_offset = ex4_icbi_instr_offset + 1; +parameter ex3_mbar_instr_offset = ex2_mbar_instr_offset + 1; +parameter ex4_mbar_instr_offset = ex3_mbar_instr_offset + 1; +parameter ex2_makeitso_instr_offset = ex4_mbar_instr_offset + 1; +parameter ex3_makeitso_instr_offset = ex2_makeitso_instr_offset + 1; +parameter ex4_makeitso_instr_offset = ex3_makeitso_instr_offset + 1; +parameter ex2_dci_instr_offset = ex4_makeitso_instr_offset + 1; +parameter ex3_dci_instr_offset = ex2_dci_instr_offset + 1; +parameter ex4_dci_instr_offset = ex3_dci_instr_offset + 1; +parameter ex2_ici_instr_offset = ex4_dci_instr_offset + 1; +parameter ex3_ici_instr_offset = ex2_ici_instr_offset + 1; +parameter ex4_ici_instr_offset = ex3_ici_instr_offset + 1; +parameter ex2_algebraic_offset = ex4_ici_instr_offset + 1; +parameter ex3_algebraic_offset = ex2_algebraic_offset + 1; +parameter ex2_strg_index_offset = ex3_algebraic_offset + 1; +parameter ex3_strg_index_offset = ex2_strg_index_offset + 1; +parameter ex4_strg_index_offset = ex3_strg_index_offset + 1; +parameter ex2_resv_instr_offset = ex4_strg_index_offset + 1; +parameter ex3_resv_instr_offset = ex2_resv_instr_offset + 1; +parameter ex4_resv_instr_offset = ex3_resv_instr_offset + 1; +parameter ex2_mutex_hint_offset = ex4_resv_instr_offset + 1; +parameter ex3_mutex_hint_offset = ex2_mutex_hint_offset + 1; +parameter ex4_mutex_hint_offset = ex3_mutex_hint_offset + 1; +parameter ex2_load_instr_offset = ex4_mutex_hint_offset + 1; +parameter ex3_load_instr_offset = ex2_load_instr_offset + 1; +parameter ex4_load_instr_offset = ex3_load_instr_offset + 1; +parameter ex2_store_instr_offset = ex4_load_instr_offset + 1; +parameter ex3_store_instr_offset = ex2_store_instr_offset + 1; +parameter ex4_store_instr_offset = ex3_store_instr_offset + 1; +parameter ex4_le_mode_offset = ex4_store_instr_offset + 1; +parameter ex5_wimge_i_bits_offset = ex4_le_mode_offset + 1; +parameter ex2_axu_op_val_offset = ex5_wimge_i_bits_offset + 1; +parameter ex3_axu_op_val_offset = ex2_axu_op_val_offset + 1; +parameter ex4_axu_op_val_offset = ex3_axu_op_val_offset + 1; +parameter ex5_axu_op_val_offset = ex4_axu_op_val_offset + 1; +parameter ex2_upd_form_offset = ex5_axu_op_val_offset + 1; +parameter ex3_upd_form_offset = ex2_upd_form_offset + 1; +parameter ex2_axu_instr_type_offset = ex3_upd_form_offset + 1; +parameter ex3_axu_instr_type_offset = ex2_axu_instr_type_offset + 3; +parameter ex5_load_hit_offset = ex3_axu_instr_type_offset + 3; +parameter ex6_load_hit_offset = ex5_load_hit_offset + 1; +parameter ex5_usr_bits_offset = ex6_load_hit_offset + 1; +parameter ex5_classid_offset = ex5_usr_bits_offset + 4; +parameter ex5_derat_setHold_offset = ex5_classid_offset + 2; +parameter ex5_axu_wren_offset = ex5_derat_setHold_offset + 1; +parameter ex6_axu_wren_offset = ex5_axu_wren_offset + 1; +parameter ex5_lq_ta_gpr_offset = ex6_axu_wren_offset + 1; +parameter ex6_lq_ta_gpr_offset = ex5_lq_ta_gpr_offset + AXU_TARGET_ENC; +parameter ex5_load_le_offset = ex6_lq_ta_gpr_offset + (`GPR_POOL_ENC+`THREADS_POOL_ENC); +parameter ex2_th_fld_c_offset = ex5_load_le_offset + 1; +parameter ex3_th_fld_c_offset = ex2_th_fld_c_offset + 1; +parameter ex4_th_fld_c_offset = ex3_th_fld_c_offset + 1; +parameter ex2_th_fld_l2_offset = ex4_th_fld_c_offset + 1; +parameter ex3_th_fld_l2_offset = ex2_th_fld_l2_offset + 1; +parameter ex4_th_fld_l2_offset = ex3_th_fld_l2_offset + 1; +parameter ex2_dcbtls_instr_offset = ex4_th_fld_l2_offset + 1; +parameter ex3_dcbtls_instr_offset = ex2_dcbtls_instr_offset + 1; +parameter ex4_dcbtls_instr_offset = ex3_dcbtls_instr_offset + 1; +parameter ex2_dcbtstls_instr_offset = ex4_dcbtls_instr_offset + 1; +parameter ex3_dcbtstls_instr_offset = ex2_dcbtstls_instr_offset + 1; +parameter ex4_dcbtstls_instr_offset = ex3_dcbtstls_instr_offset + 1; +parameter ex2_dcblc_instr_offset = ex4_dcbtstls_instr_offset + 1; +parameter ex3_dcblc_instr_offset = ex2_dcblc_instr_offset + 1; +parameter ex4_dcblc_instr_offset = ex3_dcblc_instr_offset + 1; +parameter ex2_icblc_l2_instr_offset = ex4_dcblc_instr_offset + 1; +parameter ex3_icblc_l2_instr_offset = ex2_icblc_l2_instr_offset + 1; +parameter ex4_icblc_l2_instr_offset = ex3_icblc_l2_instr_offset + 1; +parameter ex2_icbt_l2_instr_offset = ex4_icblc_l2_instr_offset + 1; +parameter ex3_icbt_l2_instr_offset = ex2_icbt_l2_instr_offset + 1; +parameter ex4_icbt_l2_instr_offset = ex3_icbt_l2_instr_offset + 1; +parameter ex2_icbtls_l2_instr_offset = ex4_icbt_l2_instr_offset + 1; +parameter ex3_icbtls_l2_instr_offset = ex2_icbtls_l2_instr_offset + 1; +parameter ex4_icbtls_l2_instr_offset = ex3_icbtls_l2_instr_offset + 1; +parameter ex2_tlbsync_instr_offset = ex4_icbtls_l2_instr_offset + 1; +parameter ex3_tlbsync_instr_offset = ex2_tlbsync_instr_offset + 1; +parameter ex4_tlbsync_instr_offset = ex3_tlbsync_instr_offset + 1; +parameter ex2_ldst_falign_offset = ex4_tlbsync_instr_offset + 1; +parameter ex2_ldst_fexcpt_offset = ex2_ldst_falign_offset + 1; +parameter ex3_ldst_fexcpt_offset = ex2_ldst_fexcpt_offset + 1; +parameter ex5_load_miss_offset = ex3_ldst_fexcpt_offset + 1; +parameter xudbg1_dir_reg_offset = ex5_load_miss_offset + 1; +parameter xudbg1_parity_reg_offset = xudbg1_dir_reg_offset + (9+`THREADS); +parameter xudbg2_tag_offset = xudbg1_parity_reg_offset + PARBITS; +parameter stq4_dcarr_wren_offset = xudbg2_tag_offset + TAGSIZE; +parameter ex2_sgpr_instr_offset = stq4_dcarr_wren_offset + 1; +parameter ex2_saxu_instr_offset = ex2_sgpr_instr_offset + 1; +parameter ex2_sdp_instr_offset = ex2_saxu_instr_offset + 1; +parameter ex2_tgpr_instr_offset = ex2_sdp_instr_offset + 1; +parameter ex2_taxu_instr_offset = ex2_tgpr_instr_offset + 1; +parameter ex2_tdp_instr_offset = ex2_taxu_instr_offset + 1; +parameter ex3_sgpr_instr_offset = ex2_tdp_instr_offset + 1; +parameter ex3_saxu_instr_offset = ex3_sgpr_instr_offset + 1; +parameter ex3_sdp_instr_offset = ex3_saxu_instr_offset + 1; +parameter ex3_tgpr_instr_offset = ex3_sdp_instr_offset + 1; +parameter ex3_taxu_instr_offset = ex3_tgpr_instr_offset + 1; +parameter ex3_tdp_instr_offset = ex3_taxu_instr_offset + 1; +parameter ex4_sgpr_instr_offset = ex3_tdp_instr_offset + 1; +parameter ex4_saxu_instr_offset = ex4_sgpr_instr_offset + 1; +parameter ex4_sdp_instr_offset = ex4_saxu_instr_offset + 1; +parameter ex4_tgpr_instr_offset = ex4_sdp_instr_offset + 1; +parameter ex4_taxu_instr_offset = ex4_tgpr_instr_offset + 1; +parameter ex4_tdp_instr_offset = ex4_taxu_instr_offset + 1; +parameter ex5_mftgpr_val_offset = ex4_tdp_instr_offset + 1; +parameter ex4_moveOp_val_offset = ex5_mftgpr_val_offset + 1; +parameter stq6_moveOp_val_offset = ex4_moveOp_val_offset + 1; +parameter ex3_undef_touch_offset = stq6_moveOp_val_offset + 1; +parameter ex4_undef_touch_offset = ex3_undef_touch_offset + 1; +parameter ex4_blkable_touch_offset = ex4_undef_touch_offset + 1; +parameter ex5_blk_touch_offset = ex4_blkable_touch_offset + 1; +parameter ex6_blk_touch_offset = ex5_blk_touch_offset + 1; +parameter ex3_eff_addr_offset = ex6_blk_touch_offset + 1; +parameter ex4_eff_addr_offset = ex3_eff_addr_offset + (2**`GPR_WIDTH_ENC); +parameter ex5_eff_addr_offset = ex4_eff_addr_offset + (2**`GPR_WIDTH_ENC); +parameter ex3_undef_lockset_offset = ex5_eff_addr_offset + (2**`GPR_WIDTH_ENC); +parameter ex4_undef_lockset_offset = ex3_undef_lockset_offset + 1; +parameter ex5_unable_2lock_offset = ex4_undef_lockset_offset + 1; +parameter ex6_stq5_unable_2lock_offset = ex5_unable_2lock_offset + 1; +parameter ex5_dacrw_cmpr_offset = ex6_stq5_unable_2lock_offset + 1; +parameter ex6_dacrw_cmpr_offset = ex5_dacrw_cmpr_offset + 4; +parameter ex3_stq_val_req_offset = ex6_dacrw_cmpr_offset + 4; +parameter ex4_stq_val_req_offset = ex3_stq_val_req_offset + 1; +parameter ex5_load_instr_offset = ex4_stq_val_req_offset + 1; +parameter ex2_mword_instr_offset = ex5_load_instr_offset + 1; +parameter ex3_mword_instr_offset = ex2_mword_instr_offset + 1; +parameter stq4_store_miss_offset = ex3_mword_instr_offset + 1; +parameter ex5_perf_dcbt_offset = stq4_store_miss_offset + 1; +parameter spr_ccr2_ap_offset = ex5_perf_dcbt_offset + 1; +parameter spr_ccr2_en_trace_offset = spr_ccr2_ap_offset + 1; +parameter spr_ccr2_ucode_dis_offset = spr_ccr2_en_trace_offset + 1; +parameter spr_ccr2_notlb_offset = spr_ccr2_ucode_dis_offset + 1; +parameter clkg_ctl_override_offset = spr_ccr2_notlb_offset + 1; +parameter spr_xucr0_wlk_offset = clkg_ctl_override_offset + 1; +parameter spr_xucr0_mbar_ack_offset = spr_xucr0_wlk_offset + 1; +parameter spr_xucr0_tlbsync_offset = spr_xucr0_mbar_ack_offset + 1; +parameter spr_xucr0_dcdis_offset = spr_xucr0_tlbsync_offset + 1; +parameter spr_xucr0_aflsta_offset = spr_xucr0_dcdis_offset + 1; +parameter spr_xucr0_flsta_offset = spr_xucr0_aflsta_offset + 1; +parameter spr_xucr0_mddp_offset = spr_xucr0_flsta_offset + 1; +parameter spr_xucr0_mdcp_offset = spr_xucr0_mddp_offset + 1; +parameter spr_xucr4_mmu_mchk_offset = spr_xucr0_mdcp_offset + 1; +parameter spr_xucr4_mddmh_offset = spr_xucr4_mmu_mchk_offset + 1; +parameter spr_xucr0_en_trace_um_offset = spr_xucr4_mddmh_offset + 1; +parameter ex1_lsu_64bit_mode_offset = spr_xucr0_en_trace_um_offset + `THREADS; +parameter ex2_lsu_64bit_agen_offset = ex1_lsu_64bit_mode_offset + `THREADS; +parameter ex3_lsu_64bit_agen_offset = ex2_lsu_64bit_agen_offset + 1; +parameter ex4_lsu_64bit_agen_offset = ex3_lsu_64bit_agen_offset + 1; +parameter ex4_local_dcbf_offset = ex4_lsu_64bit_agen_offset + 1; +parameter ex2_msgsnd_instr_offset = ex4_local_dcbf_offset + 1; +parameter ex3_msgsnd_instr_offset = ex2_msgsnd_instr_offset + 1; +parameter ex4_msgsnd_instr_offset = ex3_msgsnd_instr_offset + 1; +parameter ex4_load_type_offset = ex4_msgsnd_instr_offset + 1; +parameter ex4_gath_load_offset = ex4_load_type_offset + 1; +parameter ex4_l2load_type_offset = ex4_gath_load_offset + 1; +parameter ex5_lq_wren_offset = ex4_l2load_type_offset + 1; +parameter ex6_lq_wren_offset = ex5_lq_wren_offset + 1; +parameter ex2_ldawx_instr_offset = ex6_lq_wren_offset + 1; +parameter ex3_ldawx_instr_offset = ex2_ldawx_instr_offset + 1; +parameter ex4_ldawx_instr_offset = ex3_ldawx_instr_offset + 1; +parameter ex5_ldawx_instr_offset = ex4_ldawx_instr_offset + 1; +parameter ex2_wclr_instr_offset = ex5_ldawx_instr_offset + 1; +parameter ex3_wclr_instr_offset = ex2_wclr_instr_offset + 1; +parameter ex4_wclr_instr_offset = ex3_wclr_instr_offset + 1; +parameter ex4_opsize_enc_offset = ex4_wclr_instr_offset + 1; +parameter ex5_opsize_enc_offset = ex4_opsize_enc_offset + 3; +parameter ex2_itag_offset = ex5_opsize_enc_offset + 3; +parameter ex3_itag_offset = ex2_itag_offset + `ITAG_SIZE_ENC; +parameter ex4_itag_offset = ex3_itag_offset + `ITAG_SIZE_ENC; +parameter ex5_itag_offset = ex4_itag_offset + `ITAG_SIZE_ENC; +parameter ex6_itag_offset = ex5_itag_offset + `ITAG_SIZE_ENC; +parameter ex5_drop_rel_offset = ex6_itag_offset + `ITAG_SIZE_ENC; +parameter ex2_icswx_instr_offset = ex5_drop_rel_offset + 1; +parameter ex3_icswx_instr_offset = ex2_icswx_instr_offset + 1; +parameter ex4_icswx_instr_offset = ex3_icswx_instr_offset + 1; +parameter ex2_icswxdot_instr_offset = ex4_icswx_instr_offset + 1; +parameter ex3_icswxdot_instr_offset = ex2_icswxdot_instr_offset + 1; +parameter ex4_icswxdot_instr_offset = ex3_icswxdot_instr_offset + 1; +parameter ex2_icswx_epid_offset = ex4_icswxdot_instr_offset + 1; +parameter ex3_icswx_epid_offset = ex2_icswx_epid_offset + 1; +parameter ex4_icswx_epid_offset = ex3_icswx_epid_offset + 1; +parameter ex5_icswx_epid_offset = ex4_icswx_epid_offset + 1; +parameter ex4_c_inh_drop_op_offset = ex5_icswx_epid_offset + 1; +parameter rel2_axu_wren_offset = ex4_c_inh_drop_op_offset + 1; +parameter stq2_axu_val_offset = rel2_axu_wren_offset + 1; +parameter stq3_axu_val_offset = stq2_axu_val_offset + 1; +parameter stq4_axu_val_offset = stq3_axu_val_offset + 1; +parameter stq4_store_hit_offset = stq4_axu_val_offset + 1; +parameter stq5_store_hit_offset = stq4_store_hit_offset + 1; +parameter stq6_store_hit_offset = stq5_store_hit_offset + 1; +parameter rel2_ta_gpr_offset = stq6_store_hit_offset + 1; +parameter rv1_binv_val_offset = rel2_ta_gpr_offset + AXU_TARGET_ENC; +parameter ex0_binv_val_offset = rv1_binv_val_offset + 1; +parameter ex1_binv_val_offset = ex0_binv_val_offset + 1; +parameter ex2_binv_val_offset = ex1_binv_val_offset + 1; +parameter ex3_binv_val_offset = ex2_binv_val_offset + 1; +parameter ex4_binv_val_offset = ex3_binv_val_offset + 1; +parameter ex0_derat_snoop_val_offset = ex4_binv_val_offset + 1; +parameter ex1_derat_snoop_val_offset = ex0_derat_snoop_val_offset + 1; +parameter spr_msr_fp_offset = ex1_derat_snoop_val_offset + 1; +parameter spr_msr_spv_offset = spr_msr_fp_offset + `THREADS; +parameter spr_msr_gs_offset = spr_msr_spv_offset + `THREADS; +parameter spr_msr_pr_offset = spr_msr_gs_offset + `THREADS; +parameter spr_msr_ds_offset = spr_msr_pr_offset + `THREADS; +parameter spr_msr_de_offset = spr_msr_ds_offset + `THREADS; +parameter spr_dbcr0_idm_offset = spr_msr_de_offset + `THREADS; +parameter spr_epcr_duvd_offset = spr_dbcr0_idm_offset + `THREADS; +parameter spr_lpidr_offset = spr_epcr_duvd_offset + `THREADS; +parameter spr_pid_offset = spr_lpidr_offset + 8; +parameter ex3_icswx_gs_offset = spr_pid_offset + (`THREADS*14); +parameter ex3_icswx_pr_offset = ex3_icswx_gs_offset + 1; +parameter ex4_icswx_ct_offset = ex3_icswx_pr_offset + 1; +parameter ex4_icswx_ct_val_offset = ex4_icswx_ct_offset + 2; +parameter dbg_int_en_offset = ex4_icswx_ct_val_offset + 1; +parameter ex5_ttype_offset = dbg_int_en_offset + `THREADS; +parameter ex4_wNComp_rcvd_offset = ex5_ttype_offset + 6; +parameter ex4_wNComp_offset = ex4_wNComp_rcvd_offset + 1; +parameter ex5_wNComp_offset = ex4_wNComp_offset + 1; +parameter ex5_wNComp_cr_upd_offset = ex5_wNComp_offset + 1; +parameter ex5_dvc_en_offset = ex5_wNComp_cr_upd_offset + 1; +parameter ex6_dvc_en_offset = ex5_dvc_en_offset + 2; +parameter ex4_is_inval_op_offset = ex6_dvc_en_offset + 2; +parameter ex4_l1_lock_set_offset = ex4_is_inval_op_offset + 1; +parameter ex5_l1_lock_set_offset = ex4_l1_lock_set_offset + 1; +parameter ex4_lock_clr_offset = ex5_l1_lock_set_offset + 1; +parameter ex5_lock_clr_offset = ex4_lock_clr_offset + 1; +parameter ex2_sfx_val_offset = ex5_lock_clr_offset + 1; +parameter ex3_sfx_val_offset = ex2_sfx_val_offset + 1; +parameter ex4_sfx_val_offset = ex3_sfx_val_offset + 1; +parameter ex2_ucode_val_offset = ex4_sfx_val_offset + 1; +parameter ex3_ucode_val_offset = ex2_ucode_val_offset + 1; +parameter ex4_ucode_val_offset = ex3_ucode_val_offset + 1; +parameter ex2_ucode_cnt_offset = ex4_ucode_val_offset + 1; +parameter ex3_ucode_cnt_offset = ex2_ucode_cnt_offset + `UCODE_ENTRIES_ENC; +parameter ex2_ucode_op_offset = ex3_ucode_cnt_offset + `UCODE_ENTRIES_ENC; +parameter ex3_ucode_op_offset = ex2_ucode_op_offset + 1; +parameter ex4_ucode_op_offset = ex3_ucode_op_offset + 1; +parameter ex6_lq_comp_rpt_offset = ex4_ucode_op_offset + 1; +parameter lq0_iu_execute_vld_offset = ex6_lq_comp_rpt_offset + 1; +parameter lq0_iu_itag_offset = lq0_iu_execute_vld_offset + `THREADS; +parameter lq0_iu_flush2ucode_type_offset = lq0_iu_itag_offset + `ITAG_SIZE_ENC; +parameter lq0_iu_recirc_val_offset = lq0_iu_flush2ucode_type_offset + 1; +parameter lq0_iu_flush2ucode_offset = lq0_iu_recirc_val_offset + `THREADS; +parameter lq0_iu_dear_val_offset = lq0_iu_flush2ucode_offset + 1; +parameter lq0_iu_eff_addr_offset = lq0_iu_dear_val_offset + `THREADS; +parameter lq0_iu_n_flush_offset = lq0_iu_eff_addr_offset + (2**`GPR_WIDTH_ENC); +parameter lq0_iu_np1_flush_offset = lq0_iu_n_flush_offset + 1; +parameter lq0_iu_exception_val_offset = lq0_iu_np1_flush_offset + 1; +parameter lq0_iu_exception_offset = lq0_iu_exception_val_offset + 1; +parameter lq0_iu_dacr_type_offset = lq0_iu_exception_offset + 6; +parameter lq0_iu_dacrw_offset = lq0_iu_dacr_type_offset + 1; +parameter lq0_iu_instr_offset = lq0_iu_dacrw_offset + 4; +parameter ex5_spec_load_miss_offset = lq0_iu_instr_offset + 32; +parameter ex5_spec_itag_vld_offset = ex5_spec_load_miss_offset + 1; +parameter ex5_spec_itag_offset = ex5_spec_itag_vld_offset + 1; +parameter ex5_spec_tid_offset = ex5_spec_itag_offset + `ITAG_SIZE_ENC; +parameter ex5_blk_pf_load_offset = ex5_spec_tid_offset + `THREADS; +parameter ex5_lq_wNComp_val_offset = ex5_blk_pf_load_offset + 1; +parameter ex6_lq_wNComp_val_offset = ex5_lq_wNComp_val_offset + 1; +parameter ex5_wNComp_ord_offset = ex6_lq_wNComp_val_offset + 1; +parameter ex5_restart_val_offset = ex5_wNComp_ord_offset + 1; +parameter ex5_derat_restart_offset = ex5_restart_val_offset + 1; +parameter ex6_derat_restart_offset = ex5_derat_restart_offset + 1; +parameter ex5_dir_restart_offset = ex6_derat_restart_offset + 1; +parameter ex6_dir_restart_offset = ex5_dir_restart_offset + 1; +parameter ex5_dec_restart_offset = ex6_dir_restart_offset + 1; +parameter ex6_dec_restart_offset = ex5_dec_restart_offset + 1; +parameter ex4_derat_itagHit_offset = ex6_dec_restart_offset + 1; +parameter ex6_stq_restart_val_offset = ex4_derat_itagHit_offset + 1; +parameter ex6_restart_val_offset = ex6_stq_restart_val_offset + 1; +parameter ex5_execute_vld_offset = ex6_restart_val_offset + 1; +parameter ex5_flush2ucode_type_offset = ex5_execute_vld_offset + 1; +parameter ex5_recirc_val_offset = ex5_flush2ucode_type_offset + 1; +parameter ex5_wchkall_cplt_offset = ex5_recirc_val_offset + 1; +parameter ex6_misalign_flush_offset = ex5_wchkall_cplt_offset + 1; +parameter ldq_idle_offset = ex6_misalign_flush_offset + 1; +parameter ex4_strg_gate_offset = ldq_idle_offset + `THREADS; +parameter ex4_lswx_restart_offset = ex4_strg_gate_offset + 1; +parameter ex4_icswx_restart_offset = ex4_lswx_restart_offset + 1; +parameter ex4_is_sync_offset = ex4_icswx_restart_offset + 1; +parameter rel2_xu_wren_offset = ex4_is_sync_offset + 1; +parameter stq2_store_val_offset = rel2_xu_wren_offset + 1; +parameter stq3_store_val_offset = stq2_store_val_offset + 1; +parameter stq4_store_val_offset = stq3_store_val_offset + 1; +parameter stq6_itag_offset = stq4_store_val_offset + 1; +parameter stq6_tgpr_offset = stq6_itag_offset + `ITAG_SIZE_ENC; +parameter stq2_thrd_id_offset = stq6_tgpr_offset + AXU_TARGET_ENC; +parameter stq3_thrd_id_offset = stq2_thrd_id_offset + `THREADS; +parameter stq4_thrd_id_offset = stq3_thrd_id_offset + `THREADS; +parameter stq5_thrd_id_offset = stq4_thrd_id_offset + `THREADS; +parameter stq6_thrd_id_offset = stq5_thrd_id_offset + `THREADS; +parameter stq7_thrd_id_offset = stq6_thrd_id_offset + `THREADS; +parameter stq8_thrd_id_offset = stq7_thrd_id_offset + `THREADS; +parameter stq2_mftgpr_val_offset = stq8_thrd_id_offset + `THREADS; +parameter stq3_mftgpr_val_offset = stq2_mftgpr_val_offset + 1; +parameter stq4_mftgpr_val_offset = stq3_mftgpr_val_offset + 1; +parameter stq5_mftgpr_val_offset = stq4_mftgpr_val_offset + 1; +parameter stq6_mftgpr_val_offset = stq5_mftgpr_val_offset + 1; +parameter stq7_mftgpr_val_offset = stq6_mftgpr_val_offset + 1; +parameter stq8_mftgpr_val_offset = stq7_mftgpr_val_offset + 1; +parameter stq2_mfdpf_val_offset = stq8_mftgpr_val_offset + 1; +parameter stq3_mfdpf_val_offset = stq2_mfdpf_val_offset + 1; +parameter stq4_mfdpf_val_offset = stq3_mfdpf_val_offset + 1; +parameter stq5_mfdpf_val_offset = stq4_mfdpf_val_offset + 1; +parameter stq2_mfdpa_val_offset = stq5_mfdpf_val_offset + 1; +parameter stq3_mfdpa_val_offset = stq2_mfdpa_val_offset + 1; +parameter stq4_mfdpa_val_offset = stq3_mfdpa_val_offset + 1; +parameter stq5_mfdpa_val_offset = stq4_mfdpa_val_offset + 1; +parameter stq6_mfdpa_val_offset = stq5_mfdpa_val_offset + 1; +parameter stq2_ci_offset = stq6_mfdpa_val_offset + 1; +parameter stq3_ci_offset = stq2_ci_offset + 1; +parameter stq2_resv_offset = stq3_ci_offset + 1; +parameter stq3_resv_offset = stq2_resv_offset + 1; +parameter stq2_wclr_val_offset = stq3_resv_offset + 1; +parameter stq3_wclr_val_offset = stq2_wclr_val_offset + 1; +parameter stq4_wclr_val_offset = stq3_wclr_val_offset + 1; +parameter stq2_wclr_all_set_offset = stq4_wclr_val_offset + 1; +parameter stq3_wclr_all_set_offset = stq2_wclr_all_set_offset + 1; +parameter stq4_wclr_all_set_offset = stq3_wclr_all_set_offset + 1; +parameter stq2_epid_val_offset = stq4_wclr_all_set_offset + 1; +parameter stq4_rec_stcx_offset = stq2_epid_val_offset + 1; +parameter stq3_icswx_data_offset = stq4_rec_stcx_offset + 1; +parameter ex2_cr_fld_offset = stq3_icswx_data_offset + 25; +parameter ex3_cr_fld_offset = ex2_cr_fld_offset + `CR_POOL_ENC; +parameter ex4_cr_fld_offset = ex3_cr_fld_offset + `CR_POOL_ENC; +parameter ex5_cr_fld_offset = ex4_cr_fld_offset + `CR_POOL_ENC; +parameter dir_arr_rd_val_offset = ex5_cr_fld_offset + `CR_POOL_ENC+`THREADS_POOL_ENC; +parameter dir_arr_rd_tid_offset = dir_arr_rd_val_offset + 1; +parameter dir_arr_rd_rv1_val_offset = dir_arr_rd_tid_offset + `THREADS; +parameter dir_arr_rd_ex0_done_offset = dir_arr_rd_rv1_val_offset + 1; +parameter dir_arr_rd_ex1_done_offset = dir_arr_rd_ex0_done_offset + 1; +parameter dir_arr_rd_ex2_done_offset = dir_arr_rd_ex1_done_offset + 1; +parameter dir_arr_rd_ex3_done_offset = dir_arr_rd_ex2_done_offset + 1; +parameter dir_arr_rd_ex4_done_offset = dir_arr_rd_ex3_done_offset + 1; +parameter dir_arr_rd_ex5_done_offset = dir_arr_rd_ex4_done_offset + 1; +parameter dir_arr_rd_ex6_done_offset = dir_arr_rd_ex5_done_offset + 1; +parameter pc_lq_ram_active_offset = dir_arr_rd_ex6_done_offset + 1; +parameter lq_pc_ram_data_val_offset = pc_lq_ram_active_offset + `THREADS; +parameter ex1_stg_act_offset = lq_pc_ram_data_val_offset + 1; +parameter ex2_stg_act_offset = ex1_stg_act_offset + 1; +parameter ex3_stg_act_offset = ex2_stg_act_offset + 1; +parameter ex4_stg_act_offset = ex3_stg_act_offset + 1; +parameter ex5_stg_act_offset = ex4_stg_act_offset + 1; +parameter ex6_stg_act_offset = ex5_stg_act_offset + 1; +parameter binv2_stg_act_offset = ex6_stg_act_offset + 1; +parameter binv3_stg_act_offset = binv2_stg_act_offset + 1; +parameter binv4_stg_act_offset = binv3_stg_act_offset + 1; +parameter binv5_stg_act_offset = binv4_stg_act_offset + 1; +parameter binv6_stg_act_offset = binv5_stg_act_offset + 1; +parameter stq2_stg_act_offset = binv6_stg_act_offset + 1; +parameter stq3_stg_act_offset = stq2_stg_act_offset + 1; +parameter stq4_stg_act_offset = stq3_stg_act_offset + 1; +parameter stq5_stg_act_offset = stq4_stg_act_offset + 1; +parameter scan_right = stq5_stg_act_offset + 1 - 1; + +wire tiup; +wire tidn; +wire [0:scan_right] siv; +wire [0:scan_right] sov; + + +(* analysis_not_referenced="true" *) +wire unused; + +assign tiup = 1; +assign tidn = 0; +assign unused = ex3_rot_sel_non_le[0] | ex3_alg_bit_le_sel[0] | (|hypervisor_state) | (|ex4_p_addr[58:63]) | tidn | (|spr_dcc_spr_lesr); + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Act Signals going to all Latches +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +// Execution Pipe ACT +assign ex1_stg_act_d = dec_dcc_ex0_act | clkg_ctl_override_q; +assign ex1_stg_act = dec_dcc_ex1_cmd_act | clkg_ctl_override_q; +assign ex2_stg_act_d = ex1_stg_act; +assign ex3_stg_act_d = ex2_stg_act_q; +assign ex4_stg_act_d = ex3_stg_act_q; +assign ex5_stg_act_d = ex4_stg_act_q; +assign ex6_stg_act_d = ex5_stg_act_q; +assign ex1_instr_act = ex1_stg_act_q | dec_dcc_ex1_pfetch_val; + +// Back-Invalidate PIPE ACT +assign binv1_stg_act = ex1_binv_val_q | clkg_ctl_override_q; +assign binv2_stg_act_d = binv1_stg_act; +assign binv3_stg_act_d = binv2_stg_act_q; +assign binv4_stg_act_d = binv3_stg_act_q; +assign binv5_stg_act_d = binv4_stg_act_q; +assign binv6_stg_act_d = binv5_stg_act_q; +assign ex2_binv2_stg_act = ex2_stg_act_q | binv2_stg_act_q; +assign ex3_binv3_stg_act = ex3_stg_act_q | binv3_stg_act_q; +assign ex4_binv4_stg_act = ex4_stg_act_q | binv4_stg_act_q; +assign ex5_binv5_stg_act = ex5_stg_act_q | binv5_stg_act_q; +assign ex6_binv6_stg_act = ex6_stg_act_q | binv6_stg_act_q; + +// XUDBG PIPE ACT +assign ex4_darr_rd_act = dir_arr_rd_ex4_done_q; +assign ex5_darr_rd_act = dir_arr_rd_ex5_done_q; + +// LQ0 Interface Report ACT +assign lq0_iu_act = ex5_stg_act_q | lsq_ctl_stq_cpl_ready; + +// REL/STQ Pipe ACT +assign stq1_stg_act = lsq_ctl_stq1_stg_act | clkg_ctl_override_q; +assign stq2_stg_act_d = stq1_stg_act; +assign stq3_stg_act_d = stq2_stg_act_q; +assign stq4_stg_act_d = stq3_stg_act_q; +assign stq5_stg_act_d = stq4_stg_act_q; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Completion Inputs +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +assign iu_lq_recirc_val_d = iu_lq_recirc_val; +assign iu_lq_cp_flush_d = iu_lq_cp_flush; + +// XER[SO] bit for CP_NEXT CR update instructions (stcx./icswx./ldawx.) +assign xer_lq_cp_rd_so_d = xu_lq_xer_cp_rd; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// IU Dispatch Inputs +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +assign ex0_i0_vld_d = rv_lq_rv1_i0_vld; +assign ex0_i0_ucode_preissue_d = rv_lq_rv1_i0_ucode_preissue; +assign ex0_i0_2ucode_d = rv_lq_rv1_i0_2ucode; +assign ex0_i0_ucode_cnt_d = rv_lq_rv1_i0_ucode_cnt; +assign ex0_i1_vld_d = rv_lq_rv1_i1_vld; +assign ex0_i1_ucode_preissue_d = rv_lq_rv1_i1_ucode_preissue; +assign ex0_i1_2ucode_d = rv_lq_rv1_i1_2ucode; +assign ex0_i1_ucode_cnt_d = rv_lq_rv1_i1_ucode_cnt; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// LSU Config Bits +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +// CCR2[AP] Auxilary Processor Available +// 1 => Auxilary Processor Available +// 0 => Auxilary Processor Unavailable +assign spr_ccr2_ap_d = xu_lq_spr_ccr2_ap; + +// CCR2[EN_TRACE] MTSPR TRACE Enabled +// 1 => MTSPR Trace is enabled +// 0 => MTSPR Trace is disabled +assign spr_ccr2_en_trace_d = xu_lq_spr_ccr2_en_trace; + +// CCR2[UCODE_DIS] Ucode Disabled +// 1 => Ucode Disabled +// 0 => Ucode Enabled +assign spr_ccr2_ucode_dis_d = xu_lq_spr_ccr2_ucode_dis; + +// CCR2[NOTLB] MMU Disabled +// 1 => MMU Disabled +// 0 => MMU Enabled +assign spr_ccr2_notlb_d = xu_lq_spr_ccr2_notlb; + +// XUCR0[TRACE_UM] Enable MTSPR TRACE in user mode +// 1 => Enable MTSPR TRACE in user mode +// 0 => Disable MTSPR TRACE in user mode +assign spr_xucr0_en_trace_um_d = xu_lq_spr_xucr0_trace_um; +assign ex4_mtspr_trace_tid_en = |(spr_xucr0_en_trace_um_q & ex4_thrd_id_q); +assign ex4_mtspr_trace_en = ex4_mtspr_trace_q & spr_ccr2_en_trace_q & (ex4_mtspr_trace_tid_en | ~ex4_spr_msr_pr); +assign ex4_mtspr_trace_dis = ex4_mtspr_trace_q & ~(spr_ccr2_en_trace_q & (ex4_mtspr_trace_tid_en | ~ex4_spr_msr_pr)); + +// XUCR0[CLKG] Clock Gating Override +// 1 => Override Clock ACT's controls +// 0 => Use Clock Gating controls +assign clkg_ctl_override_d = xu_lq_spr_xucr0_clkg_ctl; + +// XUCR0[WLK] Way Locking Enabled +// 1 => Way Locking Enabled +// 0 => Way Locking Disabled +assign spr_xucr0_wlk_d = xu_lq_spr_xucr0_wlk & ~xu_lq_spr_ccr2_dfrat; + +assign way_lck_rmt = ~spr_xucr0_wlk_q ? 32'hFFFFFFFF : spr_dcc_spr_xucr2_rmt; + +// XUCR0[MBAR_ACK] +// 1 => Wait for L2 Ack of mbar and lwsync +// 0 => Dont wait for L2 Ack of mbar and lwsync +assign spr_xucr0_mbar_ack_d = xu_lq_spr_xucr0_mbar_ack; + +// XUCR0[TLBSYNC] +// 1 => Wait for L2 Ack of tlbsync +// 0 => Dont wait for L2 Ack of tlbsync +assign spr_xucr0_tlbsync_d = xu_lq_spr_xucr0_tlbsync; + +// XUCR0[DC_DIS] Data Cache Disabled +// 1 => L1 Data Cache Disabled +// 0 => L1 Data Cache Enabled +assign spr_xucr0_dcdis_d = xu_lq_spr_xucr0_dcdis; + +// XUCR0[AFLSTA] AXU Force Load/Store Alignment Interrupt +// 1 => Force alingment interrupt if misaligned access +// 0 => Dont force alingment interrupt if misaligned access +assign spr_xucr0_aflsta_d = xu_lq_spr_xucr0_aflsta; + +// XUCR0[FLSTA] FX Force Load/Store Alignment Interrupt +// 1 => Force alingment interrupt if misaligned access +// 0 => Dont force alingment interrupt if misaligned access +assign spr_xucr0_flsta_d = xu_lq_spr_xucr0_flsta; + +// XUCR0[MDDP] Machine Check on Data Cache Directory Parity Error +// 1 => Cause a machine check on data cache directory parity error +// 0 => Dont cause a machine check on data cache directory parity error, generate an N-Flush +assign spr_xucr0_mddp_d = xu_lq_spr_xucr0_mddp; + +// XUCR0[MDCP] Machine Check on Data Cache Parity Error +// 1 => Cause a machine check on data cache parity error +// 0 => Dont cause a machine check on data cache parity error, generate an N-Flush +assign spr_xucr0_mdcp_d = xu_lq_spr_xucr0_mdcp; + +// XUCR4[MMU_MCHK] Machine Check on Data ERAT Parity or Multihit Error +// 1 => Cause a machine check on data ERAT parity or multihit error +// 0 => Dont cause a machine check on data ERAT parity or multihit error, generate an N-Flush +assign spr_xucr4_mmu_mchk_d = xu_lq_spr_xucr4_mmu_mchk; + +// XUCR4[MDDMH] Machine Check on Data Cache Directory Multihit Error +// 1 => Cause a machine check on data cache directory multihit error +// 0 => Dont cause a machine check on data cache directory multihit error, generate an N-Flush +assign spr_xucr4_mddmh_d = xu_lq_spr_xucr4_mddmh; + +// MSR[FP] Floating Point Processor Available +// 1 => Floating Point Processor Available +// 0 => Floating Point Processor Unavailable +assign spr_msr_fp_d = xu_lq_spr_msr_fp; +assign spr_msr_fp = |(spr_msr_fp_q & ex3_thrd_id_q); + +// MSR[SPV] Vector Processor Available +// 1 => Vector Processor Available +// 0 => Vector Processor Unavailable +assign spr_msr_spv_d = xu_lq_spr_msr_spv; +assign spr_msr_spv = |(spr_msr_spv_q & ex3_thrd_id_q); + +// MSR[GS] Guest State +// 1 => Processor is in Guest State +// 0 => Processor is in Hypervisor State +assign spr_msr_gs_d = xu_lq_spr_msr_gs; + +// MSR[PR] Problem State +// 1 => Processor is in User Mode +// 0 => Processor is in Supervisor Mode +assign spr_msr_pr_d = xu_lq_spr_msr_pr; +assign ex4_spr_msr_pr = |(spr_msr_pr_q & ex4_thrd_id_q); + +// MSR[DS] Data Address Space +// 1 => Processor directs all data storage accesses to address space 1 +// 0 => Processor directs all data storage accesses to address space 0 +assign spr_msr_ds_d = xu_lq_spr_msr_ds; + +// MSR[DE] Debug Interrupt Enable +// 1 => Processor is allowed to take a debug interrupt +// 0 => Processor is not allowed to take a debug interrupt +assign spr_msr_de_d = xu_lq_spr_msr_de; + +// DBCR0[IDM] Internal Debug Mode Enable +// 1 => Enable internal debug mode +// 0 => Disable internal debug mode +assign spr_dbcr0_idm_d = xu_lq_spr_dbcr0_idm; + +// EPCR[DUVD] Disable Hypervisor Debug +// 1 => Debug events are suppressed in the hypervisor state +// 0 => Debug events can occur in the hypervisor state +assign spr_epcr_duvd_d = xu_lq_spr_epcr_duvd; + +// Logical Partition ID +assign spr_lpidr_d = mm_lq_lsu_lpidr; + +// Threaded Registers +generate begin : tidPid + genvar tid; + for (tid=0; tid<`THREADS; tid=tid+1) begin : tidPid + assign spr_pid_d[tid] = mm_lq_pid[14*tid:(14*tid)+13]; + assign spr_acop_ct[tid] = spr_dcc_spr_acop_ct[32*tid:(32*tid)+31]; + assign spr_hacop_ct[tid] = spr_dcc_spr_hacop_ct[32*tid:(32*tid)+31]; + end + end +endgenerate + +// Determine threads in hypervisor state +// MSR[GS] | MSR[PR] | Mode +//------------------------------------------------ +// 0 | 0 | Hypervisor +// 0 | 1 | User +// 1 | 0 | Guest Supervisor +// 1 | 1 | Guest User +assign hypervisor_state = ~(spr_msr_gs_q | spr_msr_pr_q); + +// Determine if a Debug Interrupt Should Occur +assign dbg_int_en_d = spr_msr_de_q & spr_dbcr0_idm_q & ~(spr_epcr_duvd_q & ~spr_msr_gs_q & ~spr_msr_pr_q); + +// 64Bit mode Select +assign ex1_lsu_64bit_mode_d = xu_lq_spr_msr_cm; +assign ex1_lsu_64bit_mode = |(ex1_lsu_64bit_mode_q & dec_dcc_ex1_thrd_id); +assign ex2_lsu_64bit_agen_d = ex1_lsu_64bit_mode | ex1_binv_val_q | ex1_derat_snoop_val_q; +assign ex3_lsu_64bit_agen_d = ex2_lsu_64bit_agen_q; +assign ex4_lsu_64bit_agen_d = ex3_lsu_64bit_agen_q; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Back-Invalidate Pipe +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +// Back-Invalidate Address comes from ALU +// it is provided in rv1 and muxed into bypass in ex1 +// it is then added with 0 and bypasses the erat translation +assign rv1_binv_val_d = lsq_ctl_rv0_back_inv; +assign ex0_binv_val_d = rv1_binv_val_q; +assign ex1_binv_val_d = ex0_binv_val_q; +assign ex2_binv_val_d = ex1_binv_val_q; +assign ex3_binv_val_d = ex2_binv_val_q; +assign ex4_binv_val_d = ex3_binv_val_q; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Snoop-Invalidate Pipe +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +// Snoop-Invalidate Address comes from ALU +// it is provided in rv1 and muxed into bypass in ex1 +// it is then added with 0 and goes directly to the erat +assign ex0_derat_snoop_val_d = derat_rv1_snoop_val; +assign ex1_derat_snoop_val_d = ex0_derat_snoop_val_q; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Execution Instruction Decode Staging +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +assign ex2_itag_d = dec_dcc_ex1_itag; +assign ex3_itag_d = ex2_itag_q; +assign ex4_itag_d = ex3_itag_q; +assign ex5_itag_d = ex4_itag_q; +assign ex6_itag_d = ex5_itag_q; + +assign ex2_optype1_d = dec_dcc_ex1_optype1; +assign ex3_optype1_d = ex2_optype1_q; + +assign ex2_optype2_d = dec_dcc_ex1_optype2; +assign ex3_optype2_d = ex2_optype2_q; + +assign ex2_optype4_d = dec_dcc_ex1_optype4; +assign ex3_optype4_d = ex2_optype4_q; + +assign ex2_optype8_d = dec_dcc_ex1_optype8; +assign ex3_optype8_d = ex2_optype8_q; + +assign ex2_optype16_d = dec_dcc_ex1_optype16; +assign ex3_optype16_d = ex2_optype16_q; + +assign ex3_dacr_type_d = dec_dcc_ex2_is_any_load_dac; +assign ex4_dacr_type_d = ex3_dacr_type_q; +assign ex5_dacr_type_d = ex4_dacr_type_q; + +assign ex3_eff_addr_d = dir_dcc_ex2_eff_addr; +assign ex4_eff_addr_d = ex3_eff_addr_q; + +generate + if (`GPR_WIDTH_ENC == 5) begin : Mode32b + assign ex5_eff_addr_d = ex4_eff_addr_q; + end +endgenerate + +generate + if (`GPR_WIDTH_ENC == 6) begin : Mode64b + assign ex5_eff_addr_d[0:31] = ex4_eff_addr_q[0:31] & {32{ex4_lsu_64bit_agen_q}}; + assign ex5_eff_addr_d[32:63] = ex4_eff_addr_q[32:63]; + end +endgenerate + +assign ex4_p_addr = {derat_dcc_ex4_p_addr, ex4_eff_addr_q[52:63]}; + +assign ex2_cache_acc_d = dec_dcc_ex1_cache_acc & ~fgen_ex1_stg_flush_int; +assign ex3_cache_acc_d = ex2_cache_acc_q & ~fgen_ex2_stg_flush_int; +assign ex4_cache_acc_d = ex3_cache_acc_q & ~fgen_ex3_stg_flush_int; +assign ex5_cache_acc_d = ex4_cache_acc_q & ~fgen_ex4_stg_flush_int; +assign ex6_cache_acc_d = ex5_cache_acc_q & ~fgen_ex5_cp_flush; // Different because it only goes to performance event + +assign ex2_thrd_id_d = dec_dcc_ex1_thrd_id; +assign ex3_thrd_id_d = ex2_thrd_id_q; +assign ex4_thrd_id_d = ex3_thrd_id_q; +assign ex5_thrd_id_d = ex4_thrd_id_q; +assign ex6_thrd_id_d = ex5_thrd_id_q; + +assign ex2_instr_d = dec_dcc_ex1_instr; +assign ex3_instr_d = ex2_instr_q; +assign ex4_instr_d = ex3_instr_q; +assign ex5_instr_d = ex4_instr_q; + +assign ex2_target_gpr_d = dec_dcc_ex1_target_gpr; +assign ex3_target_gpr_d = ex2_target_gpr_q; +assign ex4_target_gpr_d = ex3_target_gpr_q; + +assign ex4_cr_sel = ex4_icswxdot_instr_q | ex4_stx_instr; + +generate + if (`THREADS_POOL_ENC == 0) begin : threads1 + assign ex4_cr_fld = {({AXU_TARGET_ENC-`CR_POOL_ENC{1'b0}}), ex4_cr_fld_q}; + end +endgenerate + +generate + if (`THREADS_POOL_ENC != 0) begin : threadMulti + assign ex4_cr_fld = {({AXU_TARGET_ENC-`CR_POOL_ENC-1{1'b0}}), ex4_cr_fld_q, ex4_target_gpr_q[AXU_TARGET_ENC-`THREADS_POOL_ENC:AXU_TARGET_ENC-1]}; + end +endgenerate + +assign ex5_target_gpr_d = ex4_cr_sel ? ex4_cr_fld : ex4_target_gpr_q; + +assign ex2_dcbt_instr_d = dec_dcc_ex1_dcbt_instr; +assign ex3_dcbt_instr_d = ex2_dcbt_instr_q; +assign ex4_dcbt_instr_d = ex3_dcbt_instr_q; + +assign ex2_pfetch_val_d = dec_dcc_ex1_pfetch_val; +assign ex3_pfetch_val_d = ex2_pfetch_val_q; +assign ex4_pfetch_val_d = ex3_pfetch_val_q; +// For the case that an instruction got a Bad Machine Path Error, +// Need to drop prefetch in the pipeline in case it would have +// bypassed a bad state bit +assign ex5_pfetch_val_d = ex4_pfetch_val_q & ~ex4_wNComp_excp_restart; +assign ex6_pfetch_val_d = ex5_pfetch_val_q; +assign ldp_pfetch_inPipe = (dec_dcc_ex1_thrd_id & {`THREADS{dec_dcc_ex1_pfetch_val}}) | + (ex2_thrd_id_q & {`THREADS{ex2_pfetch_val_q}}) | + (ex3_thrd_id_q & {`THREADS{ex3_pfetch_val_q}}) | + (ex4_thrd_id_q & {`THREADS{ex4_pfetch_val_q}}) | + (ex5_thrd_id_q & {`THREADS{ex5_pfetch_val_q}}); + +assign ex2_dcbtst_instr_d = dec_dcc_ex1_dcbtst_instr; +assign ex3_dcbtst_instr_d = ex2_dcbtst_instr_q; +assign ex4_dcbtst_instr_d = ex3_dcbtst_instr_q; + +assign ex5_perf_dcbt_d = ex4_th_fld_c_q & (ex4_dcbtst_instr_q | ex4_dcbt_instr_q | ex4_dcbtstls_instr_q | ex4_dcbtls_instr_q); + +assign ex1_th_b0 = dec_dcc_ex1_th_fld[0] & (dec_dcc_ex1_dcbt_instr | dec_dcc_ex1_dcbtst_instr); +assign ex2_th_fld_c_d = ~ex1_th_b0 & ~(|dec_dcc_ex1_th_fld[1:4]); +assign ex3_th_fld_c_d = ex2_th_fld_c_q; +assign ex4_th_fld_c_d = ex3_th_fld_c_q; + +assign ex2_th_fld_l2_d = ~ex1_th_b0 & (dec_dcc_ex1_th_fld[1:4] == 4'b0010); +assign ex3_th_fld_l2_d = ex2_th_fld_l2_q; +assign ex4_th_fld_l2_d = ex3_th_fld_l2_q; + +// Need to check the L1 and send to the L2 when th=00000 +// Need to not check the L1 and send to the L2 when th=00010 +assign ex2_dcbtls_instr_d = dec_dcc_ex1_dcbtls_instr; +assign ex3_dcbtls_instr_d = ex2_dcbtls_instr_q; +assign ex4_dcbtls_instr_d = ex3_dcbtls_instr_q; + +// Need to check the L1 and send to the L2 when th=00000 +// Need to not check the L1 and send to the L2 when th=00010 +assign ex2_dcbtstls_instr_d = dec_dcc_ex1_dcbtstls_instr; +assign ex3_dcbtstls_instr_d = ex2_dcbtstls_instr_q; +assign ex4_dcbtstls_instr_d = ex3_dcbtstls_instr_q; + +// Need to check the L1 and not send to the L2 when th=00000 +// Need to not check the L1 and send to the L2 when th=00010 +assign ex2_dcblc_instr_d = dec_dcc_ex1_dcblc_instr; +assign ex3_dcblc_instr_d = ex2_dcblc_instr_q; +assign ex4_dcblc_instr_d = ex3_dcblc_instr_q; + +// Need to not check the L1 and not send to the L2 when th=00000 +// Need to not check the L1 and send to the L2 when th=00010 +assign ex2_icblc_l2_instr_d = dec_dcc_ex1_icblc_instr; +assign ex3_icblc_l2_instr_d = ex2_icblc_l2_instr_q; +assign ex4_icblc_l2_instr_d = ex3_icblc_l2_instr_q; + +// Need to not check the L1 and send to the L2 +assign ex2_icbt_l2_instr_d = dec_dcc_ex1_icbt_instr; +assign ex3_icbt_l2_instr_d = ex2_icbt_l2_instr_q; +assign ex4_icbt_l2_instr_d = ex3_icbt_l2_instr_q; + +// Need to not check the L1 and send to the L2 +assign ex2_icbtls_l2_instr_d = dec_dcc_ex1_icbtls_instr; +assign ex3_icbtls_l2_instr_d = ex2_icbtls_l2_instr_q; +assign ex4_icbtls_l2_instr_d = ex3_icbtls_l2_instr_q; + +assign ex2_tlbsync_instr_d = dec_dcc_ex1_tlbsync_instr & ~fgen_ex1_stg_flush_int; +assign ex3_tlbsync_instr_d = ex2_tlbsync_instr_q & ~fgen_ex2_stg_flush_int; +assign ex4_tlbsync_instr_d = ex3_tlbsync_instr_q & ~fgen_ex3_stg_flush_int; + +// Load Double and Set Watch Bit +assign ex2_ldawx_instr_d = dec_dcc_ex1_ldawx_instr; +assign ex3_ldawx_instr_d = ex2_ldawx_instr_q; +assign ex4_ldawx_instr_d = ex3_ldawx_instr_q; +assign ex5_ldawx_instr_d = ex4_ldawx_instr_q; + +// ICSWX Non-Record Form Instruction +assign ex2_icswx_instr_d = dec_dcc_ex1_icswx_instr; +assign ex3_icswx_instr_d = ex2_icswx_instr_q; +assign ex4_icswx_instr_d = ex3_icswx_instr_q; + +// ICSWX Record Form Instruction +assign ex2_icswxdot_instr_d = dec_dcc_ex1_icswxdot_instr; +assign ex3_icswxdot_instr_d = ex2_icswxdot_instr_q; +assign ex4_icswxdot_instr_d = ex3_icswxdot_instr_q; + +// ICSWX External PID Form Instruction +assign ex2_icswx_epid_d = dec_dcc_ex1_icswx_epid; +assign ex3_icswx_epid_d = ex2_icswx_epid_q; +assign ex4_icswx_epid_d = ex3_icswx_epid_q; +assign ex5_icswx_epid_d = ex4_icswx_epid_q; + +// Watch Clear +assign ex2_wclr_instr_d = dec_dcc_ex1_wclr_instr; +assign ex3_wclr_instr_d = ex2_wclr_instr_q; +assign ex4_wclr_instr_d = ex3_wclr_instr_q; +assign ex4_wclr_all_val = ex4_wclr_instr_q & ~ex4_l_fld_q[0]; + +// Watch Check +assign ex2_wchk_instr_d = dec_dcc_ex1_wchk_instr & ~fgen_ex1_stg_flush_int; +assign ex3_wchk_instr_d = ex2_wchk_instr_q & ~fgen_ex2_stg_flush_int; +assign ex4_wchk_instr_d = ex3_wchk_instr_q & ~fgen_ex3_stg_flush_int; + +assign ex2_dcbst_instr_d = dec_dcc_ex1_dcbst_instr; +assign ex3_dcbst_instr_d = ex2_dcbst_instr_q; +assign ex4_dcbst_instr_d = ex3_dcbst_instr_q; + +assign ex2_dcbf_instr_d = dec_dcc_ex1_dcbf_instr; +assign ex3_dcbf_instr_d = ex2_dcbf_instr_q; +assign ex3_local_dcbf = ex3_dcbf_instr_q & (ex3_l_fld_q == 2'b11); +assign ex4_dcbf_instr_d = ex3_dcbf_instr_q; + +assign ex2_mtspr_trace_d = dec_dcc_ex1_mtspr_trace & ~fgen_ex1_stg_flush_int; +assign ex3_mtspr_trace_d = ex2_mtspr_trace_q & ~fgen_ex2_stg_flush_int; +assign ex4_mtspr_trace_d = ex3_mtspr_trace_q & ~fgen_ex3_stg_flush_int; + +assign ex2_sync_instr_d = dec_dcc_ex1_sync_instr & ~fgen_ex1_stg_flush_int; +assign ex3_sync_instr_d = ex2_sync_instr_q & ~fgen_ex2_stg_flush_int; +assign ex4_sync_instr_d = ex3_sync_instr_q & ~fgen_ex3_stg_flush_int; + +assign ex2_l_fld_d = dec_dcc_ex1_l_fld; +assign ex3_l_fld_d = ex2_l_fld_q; +assign ex3_l_fld_sel = {ex3_sync_instr_q, ex3_mbar_instr_q, ex3_tlbsync_instr_q, ex3_makeitso_instr_q}; +assign ex3_l_fld_mbar = {1'b0, ~spr_xucr0_mbar_ack_q}; +assign ex3_l_fld_sync = {1'b0, (ex3_l_fld_q[1] & ~(ex3_l_fld_q[0] | spr_xucr0_mbar_ack_q))}; +assign ex3_l_fld_makeitso = 2'b01; + +assign ex3_l_fld_tlbsync = (spr_xucr0_tlbsync_q == 1'b0) ? 2'b01 : 2'b00; + +assign ex3_l_fld = (ex3_l_fld_sel == 4'b0001) ? ex3_l_fld_makeitso : + (ex3_l_fld_sel == 4'b0010) ? ex3_l_fld_tlbsync : + (ex3_l_fld_sel == 4'b0100) ? ex3_l_fld_mbar : + (ex3_l_fld_sel == 4'b1000) ? ex3_l_fld_sync : + ex3_l_fld_q; + +assign ex4_l_fld_d = ex3_l_fld; +assign ex5_l_fld_d = ex4_l_fld_q; + +assign ex2_dcbi_instr_d = dec_dcc_ex1_dcbi_instr; +assign ex3_dcbi_instr_d = ex2_dcbi_instr_q; +assign ex4_dcbi_instr_d = ex3_dcbi_instr_q; + +assign ex2_dcbz_instr_d = dec_dcc_ex1_dcbz_instr; +assign ex3_dcbz_instr_d = ex2_dcbz_instr_q; +assign ex4_dcbz_instr_d = ex3_dcbz_instr_q; + +assign ex2_icbi_instr_d = dec_dcc_ex1_icbi_instr; +assign ex3_icbi_instr_d = ex2_icbi_instr_q; +assign ex4_icbi_instr_d = ex3_icbi_instr_q; + +assign ex2_mbar_instr_d = dec_dcc_ex1_mbar_instr & ~fgen_ex1_stg_flush_int; +assign ex3_mbar_instr_d = ex2_mbar_instr_q & ~fgen_ex2_stg_flush_int; +assign ex4_mbar_instr_d = ex3_mbar_instr_q & ~fgen_ex3_stg_flush_int; + +assign ex2_makeitso_instr_d = dec_dcc_ex1_makeitso_instr & ~fgen_ex1_stg_flush_int; +assign ex3_makeitso_instr_d = ex2_makeitso_instr_q & ~fgen_ex2_stg_flush_int; +assign ex4_makeitso_instr_d = ex3_makeitso_instr_q & ~fgen_ex3_stg_flush_int; + +assign ex2_msgsnd_instr_d = dec_dcc_ex1_is_msgsnd & ~fgen_ex1_stg_flush_int; +assign ex3_msgsnd_instr_d = ex2_msgsnd_instr_q & ~fgen_ex2_stg_flush_int; +assign ex4_msgsnd_instr_d = ex3_msgsnd_instr_q & ~fgen_ex3_stg_flush_int; + +// DCI with CT=0 -> invalidate L1 only +// DCI with CT=2 -> invalidate L1 and send to L2 +// DCI with CT!=0,2 -> No-Op +assign ex2_dci_instr_d = dec_dcc_ex1_dci_instr & ~fgen_ex1_stg_flush_int; +assign ex3_dci_instr_d = ex2_dci_instr_q & ~fgen_ex2_stg_flush_int; +assign ex4_dci_instr_d = ex3_dci_instr_q & ~fgen_ex3_stg_flush_int; +assign ex4_dci_l2_val = ex4_dci_instr_q & ex4_th_fld_l2_q; +assign ex4_is_cinval = (ex4_dci_instr_q | ex4_ici_instr_q) & (ex4_th_fld_l2_q | ex4_th_fld_c_q); +assign ex4_is_cinval_drop = (ex4_dci_instr_q | ex4_ici_instr_q) & ~(ex4_th_fld_l2_q | ex4_th_fld_c_q); + +// ICI with CT=0 -> invalidate L1 only +// ICI with CT=2 -> invalidate L1 and send to L2 +// ICI with CT!=0,2 -> No-Op +assign ex2_ici_instr_d = dec_dcc_ex1_ici_instr & ~fgen_ex1_stg_flush_int; +assign ex3_ici_instr_d = ex2_ici_instr_q & ~fgen_ex2_stg_flush_int; +assign ex4_ici_instr_d = ex3_ici_instr_q & ~fgen_ex3_stg_flush_int; +assign ex4_ici_l2_val = ex4_ici_instr_q & ex4_th_fld_l2_q; + +assign ex2_algebraic_d = dec_dcc_ex1_algebraic; +assign ex3_algebraic_d = ex2_algebraic_q; + +assign ex2_strg_index_d = dec_dcc_ex1_strg_index; +assign ex3_strg_index_d = ex2_strg_index_q; +assign ex4_strg_index_d = ex3_strg_index_q; + +assign ex2_resv_instr_d = dec_dcc_ex1_resv_instr; +assign ex3_resv_instr_d = ex2_resv_instr_q; +assign ex4_resv_instr_d = ex3_resv_instr_q; + +assign ex2_mutex_hint_d = dec_dcc_ex1_mutex_hint; +assign ex3_mutex_hint_d = ex2_mutex_hint_q; +assign ex4_mutex_hint_d = ex3_mutex_hint_q; + +assign ex2_cr_fld_d = dec_dcc_ex1_cr_fld; +assign ex3_cr_fld_d = ex2_cr_fld_q; +assign ex4_cr_fld_d = ex3_cr_fld_q; +assign ex5_cr_fld_d = ex4_cr_fld[AXU_TARGET_ENC - (`CR_POOL_ENC + `THREADS_POOL_ENC):AXU_TARGET_ENC - 1]; + +assign ex2_load_instr_d = dec_dcc_ex1_load_instr; +assign ex3_load_instr_d = ex2_load_instr_q; +assign ex4_load_instr_d = ex3_load_instr_q; +assign ex5_load_instr_d = ex4_load_instr_q; +assign ex3_load_type = ex3_load_instr_q | ex3_dcbt_instr_q | ex3_dcbtst_instr_q | ex3_dcbtls_instr_q | ex3_dcbtstls_instr_q; +assign ex4_load_type_d = ex3_load_type; +assign ex4_gath_load_d = ex3_load_instr_q & ~(ex3_resv_instr_q | ex3_ldawx_instr_q); +assign ex4_l2load_type_d = ex3_load_type | ex3_icbt_l2_instr_q | ex3_icbtls_l2_instr_q; + +assign ex2_store_instr_d = dec_dcc_ex1_store_instr; +assign ex3_store_instr_d = ex2_store_instr_q; +assign ex4_store_instr_d = ex3_store_instr_q; + +assign ex2_axu_op_val_d = dec_dcc_ex1_axu_op_val; +assign ex3_axu_op_val_d = ex2_axu_op_val_q; +assign ex4_axu_op_val_d = ex3_axu_op_val_q; +assign ex5_axu_op_val_d = ex4_axu_op_val_q; + +assign ex2_sgpr_instr_d = dec_dcc_ex1_src_gpr & ~fgen_ex1_stg_flush_int; +assign ex2_saxu_instr_d = dec_dcc_ex1_src_axu & ~fgen_ex1_stg_flush_int; +assign ex2_sdp_instr_d = dec_dcc_ex1_src_dp & ~fgen_ex1_stg_flush_int; +assign ex2_tgpr_instr_d = dec_dcc_ex1_targ_gpr & ~fgen_ex1_stg_flush_int; +assign ex2_taxu_instr_d = dec_dcc_ex1_targ_axu & ~fgen_ex1_stg_flush_int; +assign ex2_tdp_instr_d = dec_dcc_ex1_targ_dp & ~fgen_ex1_stg_flush_int; + +assign ex3_sgpr_instr_d = ex2_sgpr_instr_q; +assign ex3_saxu_instr_d = ex2_saxu_instr_q; +assign ex3_sdp_instr_d = ex2_sdp_instr_q; +assign ex4_sgpr_instr_d = ex3_sgpr_instr_q; +assign ex4_saxu_instr_d = ex3_saxu_instr_q; +assign ex4_sdp_instr_d = ex3_sdp_instr_q; + +assign ex3_tgpr_instr_d = ex2_tgpr_instr_q & ~fgen_ex2_stg_flush_int; +assign ex3_taxu_instr_d = ex2_taxu_instr_q & ~fgen_ex2_stg_flush_int; +assign ex3_tdp_instr_d = ex2_tdp_instr_q & ~fgen_ex2_stg_flush_int; + +assign ex4_tgpr_instr_d = ex3_tgpr_instr_q & ~fgen_ex3_stg_flush_int; +assign ex4_taxu_instr_d = ex3_taxu_instr_q & ~fgen_ex3_stg_flush_int; +assign ex4_tdp_instr_d = ex3_tdp_instr_q & ~fgen_ex3_stg_flush_int; + +// ditc instructions +assign ex4_mfdpa_val = ex4_sdp_instr_q & ex4_taxu_instr_q; +assign ex4_mfdpf_val = ex4_sdp_instr_q & ex4_tgpr_instr_q; +assign ex4_ditc_val = ex4_tdp_instr_q | (ex4_sdp_instr_q & (ex4_taxu_instr_q | ex4_tgpr_instr_q)); + +// All the mf[f,t]gpr instructions +assign ex2_mftgpr_val = ex2_saxu_instr_q & ex2_tgpr_instr_q; +assign ex3_mftgpr_val = ex3_saxu_instr_q & ex3_tgpr_instr_q; +assign ex4_mftgpr_val = ex4_saxu_instr_q & ex4_tgpr_instr_q; +assign ex5_mftgpr_val_d = ex4_mftgpr_val & ~fgen_ex4_stg_flush_int; +assign ex3_mffgpr_val = ex3_sgpr_instr_q & ex3_taxu_instr_q; +assign ex4_mffgpr_val = ex4_sgpr_instr_q & ex4_taxu_instr_q; +assign ex3_mfgpr_val = ex3_tgpr_instr_q | ex3_taxu_instr_q | ex3_tdp_instr_q; + +assign ex2_ldst_falign_d = dec_dcc_ex1_axu_falign; +assign ex2_ldst_fexcpt_d = dec_dcc_ex1_axu_fexcpt; +assign ex3_ldst_fexcpt_d = ex2_ldst_fexcpt_q; + +assign ex2_mword_instr_d = dec_dcc_ex1_mword_instr; +assign ex3_mword_instr_d = ex2_mword_instr_q; + +assign ex2_sfx_val_d = dec_dcc_ex1_sfx_val & ~fgen_ex1_stg_flush_int; +assign ex3_sfx_val_d = ex2_sfx_val_q & ~fgen_ex2_stg_flush_int; +assign ex4_sfx_val_d = ex3_sfx_val_q & ~fgen_ex3_stg_flush_int; + +assign ex2_ucode_val_d = dec_dcc_ex1_ucode_val & ~fgen_ex1_stg_flush_int; +assign ex3_ucode_val_d = ex2_ucode_val_q & ~fgen_ex2_stg_flush_int; +assign ex4_ucode_val_d = ex3_ucode_val_q & ~fgen_ex3_stg_flush_int; + +assign ex2_ucode_cnt_d = dec_dcc_ex1_ucode_cnt; +assign ex3_ucode_cnt_d = ex2_ucode_cnt_q; + +assign ex2_ucode_op_d = dec_dcc_ex1_ucode_op; +assign ex3_ucode_op_d = ex2_ucode_op_q; +assign ex4_ucode_op_d = ex3_ucode_op_q; + +assign ex2_upd_form_d = dec_dcc_ex1_upd_form; +assign ex3_upd_form_d = ex2_upd_form_q; + +assign ex2_axu_instr_type_d = dec_dcc_ex1_axu_instr_type; +assign ex3_axu_instr_type_d = ex2_axu_instr_type_q; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Commit Execution Pipe +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +assign stq2_store_val_d = lsq_ctl_stq1_store_val & lsq_ctl_stq1_val; +assign stq3_store_val_d = stq2_store_val_q & ~lsq_ctl_stq2_blk_req; +assign stq4_store_val_d = stq3_store_val_q; +assign stq2_ci_d = lsq_ctl_stq1_ci; +assign stq3_ci_d = stq2_ci_q; +assign stq2_resv_d = lsq_ctl_stq1_resv; +assign stq3_resv_d = stq2_resv_q; +assign stq4_rec_stcx_d = stq3_resv_q & stq3_store_val_q; +assign stq2_wclr_val_d = lsq_ctl_stq1_val & lsq_ctl_stq1_watch_clr; +assign stq3_wclr_val_d = stq2_wclr_val_q & ~lsq_ctl_stq2_blk_req; +assign stq4_wclr_val_d = stq3_wclr_val_q; +assign stq2_wclr_all_set_d = lsq_ctl_stq1_watch_clr & ~lsq_ctl_stq1_l_fld[0] & lsq_ctl_stq1_l_fld[1]; +assign stq3_wclr_all_set_d = stq2_wclr_all_set_q; +assign stq4_wclr_all_set_d = stq3_wclr_all_set_q; +assign stq6_itag_d = lsq_ctl_stq5_itag; +assign stq6_tgpr_d = lsq_ctl_stq5_tgpr; +assign stq2_epid_val_d = lsq_ctl_stq1_epid_val; +assign stq2_thrd_id_d = lsq_ctl_stq1_thrd_id; +assign stq3_thrd_id_d = stq2_thrd_id_q; +assign stq4_thrd_id_d = stq3_thrd_id_q; +assign stq5_thrd_id_d = stq4_thrd_id_q; +assign stq6_thrd_id_d = stq5_thrd_id_q; +assign stq7_thrd_id_d = stq6_thrd_id_q; +assign stq8_thrd_id_d = stq7_thrd_id_q; + +assign stq2_mftgpr_val_d = lsq_ctl_stq1_mftgpr_val & lsq_ctl_stq1_val; +assign stq3_mftgpr_val_d = stq2_mftgpr_val_q & ~lsq_ctl_stq2_blk_req; +assign stq4_mftgpr_val_d = stq3_mftgpr_val_q; +assign stq5_mftgpr_val_d = stq4_mftgpr_val_q; +assign stq6_mftgpr_val_d = stq5_mftgpr_val_q; +assign stq7_mftgpr_val_d = stq6_mftgpr_val_q; +assign stq8_mftgpr_val_d = stq7_mftgpr_val_q; + +assign stq2_mfdpf_val_d = lsq_ctl_stq1_mfdpf_val & lsq_ctl_stq1_val; +assign stq3_mfdpf_val_d = stq2_mfdpf_val_q & ~lsq_ctl_stq2_blk_req; +assign stq4_mfdpf_val_d = stq3_mfdpf_val_q; +assign stq5_mfdpf_val_d = stq4_mfdpf_val_q; + +assign stq2_mfdpa_val_d = lsq_ctl_stq1_mfdpa_val & lsq_ctl_stq1_val; +assign stq3_mfdpa_val_d = stq2_mfdpa_val_q & ~lsq_ctl_stq2_blk_req; +assign stq4_mfdpa_val_d = stq3_mfdpa_val_q; +assign stq5_mfdpa_val_d = stq4_mfdpa_val_q; +assign stq6_mfdpa_val_d = stq5_mfdpa_val_q; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// ICSWX LOGIC +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +// ICSWX +assign ex2_epsc_egs = |(spr_dcc_epsc_egs & ex2_thrd_id_q); +assign ex2_epsc_epr = |(spr_dcc_epsc_epr & ex2_thrd_id_q); +assign ex2_msr_gs = |(spr_msr_gs_q & ex2_thrd_id_q); +assign ex2_msr_pr = |(spr_msr_pr_q & ex2_thrd_id_q); +assign ex3_icswx_gs_d = ex2_icswx_epid_q ? ex2_epsc_egs : ex2_msr_gs; +assign ex3_icswx_pr_d = ex2_icswx_epid_q ? ex2_epsc_epr : ex2_msr_pr; +assign ex4_icswx_ct_val_d = lsq_ctl_ex3_ct_val; + +// Only Check ACOP in problem state (PR=1) +assign ex3_acop_ct_npr = ex3_acop_ct | {32{~ex3_icswx_pr_q}}; +assign ex3_cop_ct = ex3_hacop_ct & ex3_acop_ct_npr; + +// Only Check ACOP/HACOP if not in Hypervisor +assign ex4_icswx_ct_d[0] = ex3_icswx_ct[0] | (~ex3_icswx_pr_q & ~ex3_icswx_gs_q); // Big Endian +assign ex4_icswx_ct_d[1] = ex3_icswx_ct[1] | (~ex3_icswx_pr_q & ~ex3_icswx_gs_q); // Little Endian + +// ICSWX DSI Generation +assign ex4_icswx_ct = (ex4_icswx_ct_q[0] & ~derat_dcc_ex4_wimge[4]) | // Big Endian + (ex4_icswx_ct_q[1] & derat_dcc_ex4_wimge[4]); // Little Endian +assign ex4_icswx_dsi = ex4_cache_acc_q & ex4_icswx_type & ex4_icswx_ct_val_q & ~ex4_icswx_ct; + +// Big Endian CT Select +assign ex3_icswx_ct[0] = (lsq_ctl_ex3_be_ct == 6'b100000) ? ex3_cop_ct[32] : + (lsq_ctl_ex3_be_ct == 6'b100001) ? ex3_cop_ct[33] : + (lsq_ctl_ex3_be_ct == 6'b100010) ? ex3_cop_ct[34] : + (lsq_ctl_ex3_be_ct == 6'b100011) ? ex3_cop_ct[35] : + (lsq_ctl_ex3_be_ct == 6'b100100) ? ex3_cop_ct[36] : + (lsq_ctl_ex3_be_ct == 6'b100101) ? ex3_cop_ct[37] : + (lsq_ctl_ex3_be_ct == 6'b100110) ? ex3_cop_ct[38] : + (lsq_ctl_ex3_be_ct == 6'b100111) ? ex3_cop_ct[39] : + (lsq_ctl_ex3_be_ct == 6'b101000) ? ex3_cop_ct[40] : + (lsq_ctl_ex3_be_ct == 6'b101001) ? ex3_cop_ct[41] : + (lsq_ctl_ex3_be_ct == 6'b101010) ? ex3_cop_ct[42] : + (lsq_ctl_ex3_be_ct == 6'b101011) ? ex3_cop_ct[43] : + (lsq_ctl_ex3_be_ct == 6'b101100) ? ex3_cop_ct[44] : + (lsq_ctl_ex3_be_ct == 6'b101101) ? ex3_cop_ct[45] : + (lsq_ctl_ex3_be_ct == 6'b101110) ? ex3_cop_ct[46] : + (lsq_ctl_ex3_be_ct == 6'b101111) ? ex3_cop_ct[47] : + (lsq_ctl_ex3_be_ct == 6'b110000) ? ex3_cop_ct[48] : + (lsq_ctl_ex3_be_ct == 6'b110001) ? ex3_cop_ct[49] : + (lsq_ctl_ex3_be_ct == 6'b110010) ? ex3_cop_ct[50] : + (lsq_ctl_ex3_be_ct == 6'b110011) ? ex3_cop_ct[51] : + (lsq_ctl_ex3_be_ct == 6'b110100) ? ex3_cop_ct[52] : + (lsq_ctl_ex3_be_ct == 6'b110101) ? ex3_cop_ct[53] : + (lsq_ctl_ex3_be_ct == 6'b110110) ? ex3_cop_ct[54] : + (lsq_ctl_ex3_be_ct == 6'b110111) ? ex3_cop_ct[55] : + (lsq_ctl_ex3_be_ct == 6'b111000) ? ex3_cop_ct[56] : + (lsq_ctl_ex3_be_ct == 6'b111001) ? ex3_cop_ct[57] : + (lsq_ctl_ex3_be_ct == 6'b111010) ? ex3_cop_ct[58] : + (lsq_ctl_ex3_be_ct == 6'b111011) ? ex3_cop_ct[59] : + (lsq_ctl_ex3_be_ct == 6'b111100) ? ex3_cop_ct[60] : + (lsq_ctl_ex3_be_ct == 6'b111101) ? ex3_cop_ct[61] : + (lsq_ctl_ex3_be_ct == 6'b111110) ? ex3_cop_ct[62] : + (lsq_ctl_ex3_be_ct == 6'b111111) ? ex3_cop_ct[63] : + 1'b0; + +// Little Endian CT Select +assign ex3_icswx_ct[1] = (lsq_ctl_ex3_le_ct == 6'b100000) ? ex3_cop_ct[32] : + (lsq_ctl_ex3_le_ct == 6'b100001) ? ex3_cop_ct[33] : + (lsq_ctl_ex3_le_ct == 6'b100010) ? ex3_cop_ct[34] : + (lsq_ctl_ex3_le_ct == 6'b100011) ? ex3_cop_ct[35] : + (lsq_ctl_ex3_le_ct == 6'b100100) ? ex3_cop_ct[36] : + (lsq_ctl_ex3_le_ct == 6'b100101) ? ex3_cop_ct[37] : + (lsq_ctl_ex3_le_ct == 6'b100110) ? ex3_cop_ct[38] : + (lsq_ctl_ex3_le_ct == 6'b100111) ? ex3_cop_ct[39] : + (lsq_ctl_ex3_le_ct == 6'b101000) ? ex3_cop_ct[40] : + (lsq_ctl_ex3_le_ct == 6'b101001) ? ex3_cop_ct[41] : + (lsq_ctl_ex3_le_ct == 6'b101010) ? ex3_cop_ct[42] : + (lsq_ctl_ex3_le_ct == 6'b101011) ? ex3_cop_ct[43] : + (lsq_ctl_ex3_le_ct == 6'b101100) ? ex3_cop_ct[44] : + (lsq_ctl_ex3_le_ct == 6'b101101) ? ex3_cop_ct[45] : + (lsq_ctl_ex3_le_ct == 6'b101110) ? ex3_cop_ct[46] : + (lsq_ctl_ex3_le_ct == 6'b101111) ? ex3_cop_ct[47] : + (lsq_ctl_ex3_le_ct == 6'b110000) ? ex3_cop_ct[48] : + (lsq_ctl_ex3_le_ct == 6'b110001) ? ex3_cop_ct[49] : + (lsq_ctl_ex3_le_ct == 6'b110010) ? ex3_cop_ct[50] : + (lsq_ctl_ex3_le_ct == 6'b110011) ? ex3_cop_ct[51] : + (lsq_ctl_ex3_le_ct == 6'b110100) ? ex3_cop_ct[52] : + (lsq_ctl_ex3_le_ct == 6'b110101) ? ex3_cop_ct[53] : + (lsq_ctl_ex3_le_ct == 6'b110110) ? ex3_cop_ct[54] : + (lsq_ctl_ex3_le_ct == 6'b110111) ? ex3_cop_ct[55] : + (lsq_ctl_ex3_le_ct == 6'b111000) ? ex3_cop_ct[56] : + (lsq_ctl_ex3_le_ct == 6'b111001) ? ex3_cop_ct[57] : + (lsq_ctl_ex3_le_ct == 6'b111010) ? ex3_cop_ct[58] : + (lsq_ctl_ex3_le_ct == 6'b111011) ? ex3_cop_ct[59] : + (lsq_ctl_ex3_le_ct == 6'b111100) ? ex3_cop_ct[60] : + (lsq_ctl_ex3_le_ct == 6'b111101) ? ex3_cop_ct[61] : + (lsq_ctl_ex3_le_ct == 6'b111110) ? ex3_cop_ct[62] : + (lsq_ctl_ex3_le_ct == 6'b111111) ? ex3_cop_ct[63] : + 1'b0; + +generate begin : regConc + genvar tid; + for (tid=0; tid<`THREADS; tid=tid+1) begin : regConc + // Concatenate Appropriate EPSC fields + assign epsc_t_reg[tid] = {spr_dcc_epsc_epr[tid], spr_dcc_epsc_eas[tid], spr_dcc_epsc_egs[tid], + spr_dcc_epsc_elpid[tid*8:tid*8+7], spr_dcc_epsc_epid[tid*14:tid*14+13]}; + // Concatenate Appropriate LESR fields + assign lesr_t_reg[tid] = spr_dcc_spr_lesr[tid*24:(tid*24)+23]; + end + end +endgenerate + +// Thread Register Selection +always @(*) +begin: tidIcswx + reg [0:13] pid; + reg [0:24] epsc; + reg [0:31] acop; + reg [0:31] hcop; + reg [0:23] lesr; + //(* analysis_not_referenced="true" *) + integer tid; + + pid = {14{1'b0}}; + epsc = {25{1'b0}}; + acop = {32{1'b0}}; + hcop = {32{1'b0}}; + lesr = {24{1'b0}}; + for (tid=0; tid<`THREADS; tid=tid+1) + begin + pid = (spr_pid_q[tid] & {14{stq2_thrd_id_q[tid]}}) | pid; + epsc = (epsc_t_reg[tid] & {25{stq2_thrd_id_q[tid]}}) | epsc; + acop = (spr_acop_ct[tid] & {32{ex3_thrd_id_q[tid]}}) | acop; + hcop = (spr_hacop_ct[tid] & {32{ex3_thrd_id_q[tid]}}) | hcop; + lesr = (lesr_t_reg[tid] & {24{ex5_thrd_id_q[tid]}}) | lesr; + end + stq2_pid = pid; + stq2_epsc = epsc; + ex3_acop_ct = acop; + ex3_hacop_ct = hcop; + ex5_spr_lesr = lesr; +end + +// ICSWX Store Data +assign stq2_icswx_epid[0:2] = {~stq2_epsc[2], stq2_epsc[0], stq2_epsc[1]}; +assign stq2_icswx_epid[3:24] = stq2_epsc[3:24]; +assign stq2_icswx_nepid[0:2] = {~(|(spr_msr_gs_q & stq2_thrd_id_q)), |(spr_msr_pr_q & stq2_thrd_id_q), |(spr_msr_ds_q & stq2_thrd_id_q)}; +assign stq2_icswx_nepid[3:24] = {spr_lpidr_q, stq2_pid}; + +// Select between External Pid and non-External Pid ICSWX +assign stq3_icswx_data_d = stq2_epid_val_q ? stq2_icswx_epid : stq2_icswx_nepid; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// CR Update Logic +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +// CR Setter +generate begin : crData + genvar cr; + for (cr=0; cr<`CR_WIDTH; cr=cr+1) begin : crData + if (cr == 2) begin : crSet0 + assign ex5_cr_wd[cr] = dir_dcc_ex5_cr_rslt; + end + if (cr == 3) begin : crSet1 + assign ex5_cr_wd[cr] = |(xer_lq_cp_rd_so_q & ex5_thrd_id_q); + end + if (cr < 2 | cr >= 4) begin : crOff0 + assign ex5_cr_wd[cr] = 1'b0; + end + end + end +endgenerate + +//ldawx. --> 00 || b2 || XER[SO] +//icswx. --> b0b1b2 || 0 +//stcx. --> 00 || b2 || XER[SO] +//wchkall ==> 00 || b2 || XER[SO] + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Byte Enable Generation +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Need to generate byte enables for the type of operation +// size1 => 0x8000 +// size2 => 0xC000 +// size4 => 0xF000 +// size8 => 0xFF00 +// size16 => 0xFFFF +assign op_sel[0] = ex3_opsize[1] | ex3_opsize[2] | ex3_opsize[3] | ex3_opsize[4]; +assign op_sel[1] = ex3_opsize[1] | ex3_opsize[2] | ex3_opsize[3]; +assign op_sel[2] = ex3_opsize[1] | ex3_opsize[2]; +assign op_sel[3] = ex3_opsize[1] | ex3_opsize[2]; +assign op_sel[4] = ex3_opsize[1]; +assign op_sel[5] = ex3_opsize[1]; +assign op_sel[6] = ex3_opsize[1]; +assign op_sel[7] = ex3_opsize[1]; +assign op_sel[8:15] = {8{1'b0}}; + +// 16 Bit Rotator +// Selects between Data rotated by 0, 4, 8, or 12 bits +assign beC840_en = (ex3_eff_addr_q[60:61] == 2'b00) ? op_sel[0:15] : + (ex3_eff_addr_q[60:61] == 2'b01) ? {4'h0, op_sel[0:11]} : + (ex3_eff_addr_q[60:61] == 2'b10) ? {8'h00, op_sel[0:7]} : + {12'h000, op_sel[0:3]}; + +// Selects between Data rotated by 0, 1, 2, or 3 bits +assign be3210_en = (ex3_eff_addr_q[62:63] == 2'b00) ? beC840_en[0:15] : + (ex3_eff_addr_q[62:63] == 2'b01) ? {1'b0, beC840_en[0:14]} : + (ex3_eff_addr_q[62:63] == 2'b10) ? {2'b00, beC840_en[0:13]} : + {3'b000, beC840_en[0:12]}; + +// Byte Enables Generated using the opsize and physical_addr(60 to 63) +generate begin : ben_gen + genvar t; + for (t=0; t<16; t=t+1) begin : ben_gen + assign byte_en[t] = ex3_opsize[0] | be3210_en[t]; + end + end +endgenerate + +// Gate off Byte Enables for instructions that have no address checking in the Order Queue +assign ex3_byte_en = byte_en & {16{~(ex3_mfgpr_val | ex3_msgsnd_instr_q)}}; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Load Rotate Control Generation +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +// Table of op_size, Should be 1-hot enabled +// op_size(0) => size16 +// op_size(1) => size8 +// op_size(2) => size4 +// op_size(3) => size2 +// op_size(4) => size1 +assign ex3_opsize = ex3_mftgpr_val ? 5'b10000 : ({ex3_optype16_q, ex3_optype8_q, ex3_optype4_q, ex3_optype2_q, ex3_optype1_q}); + +assign ex3_opsize_enc = (ex3_opsize == 5'b10000) ? 3'b110 : + (ex3_opsize == 5'b01000) ? 3'b101 : + (ex3_opsize == 5'b00100) ? 3'b100 : + (ex3_opsize == 5'b00010) ? 3'b010 : + (ex3_opsize == 5'b00001) ? 3'b001 : + 3'b000; + +assign ex4_opsize_enc_d = ex3_opsize_enc; +assign ex5_opsize_enc_d = ex4_opsize_enc_q; + +assign ex5_opsize = (ex5_opsize_enc_q == 3'b101) ? 4'b1000 : + (ex5_opsize_enc_q == 3'b100) ? 4'b0100 : + (ex5_opsize_enc_q == 3'b010) ? 4'b0010 : + (ex5_opsize_enc_q == 3'b001) ? 4'b0001 : + 4'b0000; + +// Loadhit DVC Compare Byte Valid Generation +assign ex5_byte_mask = (8'h01 /*'*/ & {8{ex5_opsize[4]}}) | (8'h03 & {8{ex5_opsize[3]}}) | (8'h0F /*'*/& {8{ex5_opsize[2]}}) | (8'hFF /*'*/ & {8{ex5_opsize[1]}}); + +// LOAD PATH LITTLE ENDIAN ROTATOR SELECT CALCULATION +// ld_rot_size = rot_addr + op_size +// ld_rot_sel_le = rot_addr +// ld_rot_sel = rot_max_size - ld_rot_size +// ld_rot_sel = ld_rot_sel_le => le_mode = 1 +// = ld_rot_sel => le_mode = 0 + +// Execution Pipe Rotator Control Calculations +assign ex3_rot_size = ex3_eff_addr_q[59:63] + ex3_opsize; +assign ex3_rot_sel_non_le = rot_max_size - ex3_rot_size; +assign ex3_alg_bit_le_sel = ex3_rot_size - 5'b00001; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// RV Release Control +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +// Instruction Report to RV +// Removed SYNC/MBAR/MAKEITSO/TLBSYNC since they are non speculative and they are reported and removed on the LQ_RV_ITAG0 bus +// Work Around for DITC +assign ex5_spec_itag_vld_d = ((ex4_cache_acc_q | ex4_mffgpr_val | ex4_mftgpr_val | ex4_wchk_instr_q | ex4_ditc_val) & ~fgen_ex4_stg_flush_int) | + ((ex4_wNComp_excp | ex4_ucode_val_q) & ~fgen_ex4_cp_flush_int) | + stq6_mftgpr_val_q; + +assign ex4_spec_itag = stq6_mftgpr_val_q ? stq6_itag_q : ex4_itag_q; +assign ex4_spec_thrd_id = stq6_mftgpr_val_q ? stq6_thrd_id_q : ex4_thrd_id_q; +assign ex5_spec_itag_d = ex4_spec_itag; +assign ex5_spec_tid_d = ex4_spec_thrd_id; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// RESTART Control +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +// RESTART_SPEC Indicators +assign ex4_spec_load_miss = (dir_dcc_ex4_miss | derat_dcc_ex4_wimge[1] | spr_xucr0_dcdis_q) & ex4_load_instr_q & ~ex4_blk_touch; +// either a loadmiss, a cache-inhibited load, larx, stcx, or icswx. instructions +assign ex5_spec_load_miss_d = (ex4_spec_load_miss | ex4_resv_instr_q | ex4_icswxdot_instr_q) & ex4_cache_acc_q & ~(fgen_ex4_stg_flush_int | stq6_mftgpr_val_q); + +// RESTART Indicators +// 1) STQ => LSWX that hasn't gotten the XER source +// 2) DIR => DCBTLS/DCBTSTLS/LDAWX instruction in EX3/EX4 and a reload targetting the same congruence class +// 3) DIR => Instruction Bypassed Directory results that were restarted +// 4) CTRL => Request is a CP_NEXT instruction and CP_NEXT_VAL isnt on +// 5) CTRL => Request is a CP_NEXT exception and CP_NEXT_VAL isnt on +// 6) DERAT => ERATM State machines are all busy +// 7) DERAT => ERATM State machine 0 is busy and oldest itag missed +// 8) DERAT => ERATM State machines 1 to EMQ_ENTRIES are busy and +// this request is not the oldest +// 9) DERAT => Current Requests ITAG is already using a state machine +// 10) DERAT => Current Requests EPN down to a 4KB page is already using a state machine +// 11) DERAT => Current Requests is sending the NonSpeculative Request to the TLB +// 12) LDQ => Load hit outstanding LARX for my thread +// 13) LDQ => New Loadmiss Request to Cache line already in LoadMiss Queue +// 14) LDQ => New LoadMiss Request and the Queue is full +// 15) LDQ => New Loadmiss Request and 1 LoadMiss StateMachine available and not the oldest load request +// 16) LDQ => Load was gathered to a cTag and reload to that cTag started the same cycle +// 17) STQ => Younger Guarded Load Request collided against an older guarded Store +// 18) STQ => Younger Load Request hit against an older CP_NEXT store instruction (i.e icbi, sync, stcx, icswx., mftgpr, mfdp) +// 19) STQ => Younger Load Request Address hit multiple older entries +// 20) STQ => Younger Load Request Address hit against an older store but endianness differs +// 21) STQ => Younger Guarded Load Request Address hit against an older store +// 22) STQ => Younger Load Request Address hit against an older store type with no data associated +// 23) STQ => Younger Loadmiss Request Cacheline Address hit against older store type +// 24) STQ => ICSWX that hasn't gotten RS2 data from the FX units +// 25) CTRL => CP_NEXT instruction needs to be redirected, the 2 younger instructions behind it need a +// restart since they will bypass from bad instruction +// 26) CTRL => Ucode PreIssue has not updated the memory attribute bits + +assign ex3_lswx_restart = ex3_ucode_val_q & ex3_load_instr_q & ex3_strg_index_q & ~lsq_ctl_ex3_strg_val; +assign ex4_lswx_restart_d = ex3_lswx_restart; +assign ex3_icswx_restart = ex3_cache_acc_q & ex3_icswx_type & ~lsq_ctl_ex3_ct_val; +assign ex4_icswx_restart_d = ex3_icswx_restart; +assign ex4_2younger_restart = ex4_wNComp_excp_restart & (ex4_cache_acc_q | ex4_ucode_val_q | ex4_wchk_instr_q); +assign ex4_restart_val = dir_dcc_ex4_set_rel_coll | dir_dcc_ex4_byp_restart | derat_dcc_ex4_restart | ex4_lswx_restart_q | ex4_icswx_restart_q | ex4_2younger_restart | ex4_ucode_restart; +assign ex5_restart_val_d = ex4_restart_val; +assign ex5_ldq_restart_val = lsq_ctl_ex5_ldq_restart; +assign ex5_derat_restart_d = derat_dcc_ex4_restart; +assign ex6_derat_restart_d = ex5_derat_restart_q; +assign ex5_dir_restart_d = dir_dcc_ex4_set_rel_coll | dir_dcc_ex4_byp_restart; +assign ex6_dir_restart_d = ex5_dir_restart_q; +assign ex5_dec_restart_d = ex4_lswx_restart_q | ex4_icswx_restart_q | ex4_ucode_restart; +assign ex6_dec_restart_d = ex5_dec_restart_q; +assign ex4_derat_itagHit_d = derat_dcc_ex3_itagHit; + +// Want to restart if loadmiss and didnt forward +assign ex5_stq_restart_miss = lsq_ctl_ex5_stq_restart_miss & ex5_load_miss_q; +assign ex5_stq_restart_val = lsq_ctl_ex5_stq_restart | ex5_stq_restart_miss; +assign ex6_stq_restart_val_d = ex5_stq_restart_val; +assign ex5_restart_val = (ex5_ldq_restart_val | ex5_stq_restart_val | ex5_lq_wNComp_val_q | ex5_restart_val_q) & ex5_spec_itag_vld_q & ~(stq7_mftgpr_val_q | ex5_flush_req); +assign ex6_restart_val_d = ex5_restart_val; +assign ex5_lq_req_abort = ((ex5_spec_load_miss_q & ~lsq_ctl_ex5_fwd_val) | ex5_restart_val | ex5_mftgpr_val_q) & ex5_spec_itag_vld_q; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Completion Control +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// All instructions that report completion when coming down the pipe +// sfx_val <= src_gpr or src_axu or src_dp or targ_gpr or targ_axu or targ_dp or mtdp or mtdpx or mtdp_dc or mtdpx_dc or mfdp or +// mfdpx or mfdp_dc or mfdpx_dc or mbar or msgsnd or sync or tlbsync or wchkall or dci or ici or mtspr_trace or makeitso +assign ex4_excp_rpt_val = (ex4_cache_acc_q | ex4_sfx_val_q | ex4_sfx_excpt_det) & ex4_excp_det; +assign ex4_ucode_rpt = (~ex4_strg_index_q & ~ex4_wNComp_excp & ~(derat_dcc_ex4_restart | ex4_2younger_restart)) | (ex4_excp_det & ~ex4_lswx_restart_q); +assign ex4_ucode_rpt_val = ex4_ucode_val_q & ex4_ucode_rpt; +// I dont think ex4_wNComp_excp_restart needs to be in the equation since mffgpr doesnt use the directory, dataCache, or erats +assign ex4_mffgpr_rpt_val = ex4_mffgpr_val; +assign ex5_execute_vld_d = (ex4_ucode_rpt_val | // Ucode_PreIssue + ex4_mffgpr_rpt_val | // mffgpr + ex4_excp_rpt_val) & // Exception Detected on a Cache Access + ~fgen_ex4_cp_flush_int; + +assign ex5_flush2ucode_type_d = ex4_le_mode_q; +assign ex5_recirc_val_d = (ex4_wNComp_req & ~(ex4_wNComp_rcvd_q | fgen_ex4_stg_flush_int)) | + (ex4_wNComp_excp & ~(ex4_wNComp_rcvd_q | fgen_ex4_cp_flush_int)); + +// Mux between Store Queue Completion Report and Load Pipeline Completion Report +// Load Pipeline has higher priority +assign ex5_lq_comp_rpt_val = ( ex5_execute_vld_q | ex5_wchkall_cplt | ex5_flush_req | ex5_recirc_val_q) & ~fgen_ex5_cp_flush; +assign ex6_lq_comp_rpt_d = ( ex5_execute_vld_q | ex5_wchkall_cplt | ex5_flush_req) & ~fgen_ex5_cp_flush; +assign ex5_execute_vld = ((ex5_execute_vld_q | ex5_wchkall_cplt | ex5_flush_req) & ~fgen_ex5_cp_flush) | + (lsq_ctl_stq_cpl_ready & ~ex5_lq_comp_rpt_val); +assign ex5_recirc_val = ex5_recirc_val_q & ~(fgen_ex5_cp_flush | ex5_flush_req); +assign lq0_rpt_thrd_id = ( ex5_thrd_id_q & {`THREADS{ ex5_lq_comp_rpt_val}}) | + (lsq_ctl_stq_cpl_ready_tid & {`THREADS{~ex5_lq_comp_rpt_val}}); +assign lq0_iu_execute_vld_d = lq0_rpt_thrd_id & {`THREADS{ex5_execute_vld}}; +assign lq0_iu_itag_d = ( ex5_itag_q & {`ITAG_SIZE_ENC{ ex5_lq_comp_rpt_val}}) | + (lsq_ctl_stq_cpl_ready_itag & {`ITAG_SIZE_ENC{~ex5_lq_comp_rpt_val}}); +assign lq0_iu_recirc_val_d = ex5_thrd_id_q & {`THREADS{ex5_recirc_val}}; +assign lq0_iu_flush2ucode_d = ex5_flush2ucode & ex5_lq_comp_rpt_val; +assign lq0_iu_flush2ucode_type_d = ex5_flush2ucode_type_q; +assign lq0_iu_dear_val_d = ex5_dear_val & {`THREADS{ex5_lq_comp_rpt_val}}; +assign lq0_iu_eff_addr_d = ex5_eff_addr_q; +assign lq0_iu_n_flush_d = ( ex5_n_flush & ex5_lq_comp_rpt_val) | ( lsq_ctl_stq_n_flush & ~ex5_lq_comp_rpt_val); +assign lq0_iu_np1_flush_d = ( ex5_np1_flush & ex5_lq_comp_rpt_val) | ( lsq_ctl_stq_np1_flush & ~ex5_lq_comp_rpt_val); +assign lq0_iu_exception_val_d = (ex5_exception_val & ex5_lq_comp_rpt_val) | (lsq_ctl_stq_exception_val & ~ex5_lq_comp_rpt_val); +assign lq0_iu_exception_d = ( ex5_exception & {6{ ex5_lq_comp_rpt_val}}) | + (lsq_ctl_stq_exception & {6{~ex5_lq_comp_rpt_val}}); +assign lq0_iu_dacr_type_d = (ex5_dacr_type_q & ex5_lq_comp_rpt_val); +assign lq0_iu_dacrw_d = ( ex5_dacrw_cmpr & {4{ ex5_lq_comp_rpt_val}}) | + (lsq_ctl_stq_dacrw & {4{~ex5_lq_comp_rpt_val}}); +assign lq0_iu_instr_d = ex5_instr_q; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// DEBUG ADDRESS COMPARE only report +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +// Data Address Compare Only Interrupt is detected and reported on LQ0 Completion bus +// Store Pipe Data Value Compare Interrupts are reported on LQ0 Completion bus +// Load Pipe Data Value Compare Interrupts are reported on LQ1 Completion bus +// All Debug Interrupts are PRECISE +assign ex4_dbg_int_en = |(dbg_int_en_q & ex4_thrd_id_q); +assign ex4_dacrw1_cmpr = spr_dcc_ex4_dacrw1_cmpr & ~ex4_blk_touch_instr; +assign ex4_dacrw2_cmpr = spr_dcc_ex4_dacrw2_cmpr & ~ex4_blk_touch_instr; +assign ex4_dacrw3_cmpr = spr_dcc_ex4_dacrw3_cmpr & ~ex4_blk_touch_instr; +assign ex4_dacrw4_cmpr = spr_dcc_ex4_dacrw4_cmpr & ~ex4_blk_touch_instr; +assign ex5_dacrw_cmpr_d = {ex4_dacrw1_cmpr, ex4_dacrw2_cmpr, ex4_dacrw3_cmpr, ex4_dacrw4_cmpr}; +assign ex5_dacrw_rpt_val = ~(ex5_flush_req | ex5_flush2ucode); +assign ex5_dacrw_cmpr = ex5_dacrw_cmpr_q & {4{ex5_dacrw_rpt_val}}; +assign ex6_dacrw_cmpr_d = ex5_dacrw_cmpr; +assign ex5_dvc_en_d = {spr_dcc_ex4_dvc1_en, spr_dcc_ex4_dvc2_en}; +assign ex6_dvc_en_d = ex5_dvc_en_q & {2{ex5_load_hit_q}}; + +// Debug Address Compare Interrupt detected, Data Value Compare is disabled +// Flushing instructions early +assign ex4_dac_int_det = (ex4_dacrw1_cmpr | ex4_dacrw2_cmpr | ex4_dacrw3_cmpr | ex4_dacrw4_cmpr) & + ~(spr_dcc_ex4_dvc1_en | spr_dcc_ex4_dvc2_en) & ex4_dbg_int_en; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// L1 D-Cache Control Logic +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +// Touch Type Instructions +// ################################################################ + +// Touch Ops with unsupported TH fields are no-ops +assign ex2_undef_touch = (ex2_dcbt_instr_q | ex2_dcblc_instr_q | ex2_dcbtls_instr_q | ex2_dcbtstls_instr_q | ex2_dcbtst_instr_q | + ex2_icbt_l2_instr_q | ex2_icblc_l2_instr_q | ex2_icbtls_l2_instr_q) & ~(ex2_th_fld_c_q | ex2_th_fld_l2_q); + +assign ex3_undef_touch_d = ex2_undef_touch; +assign ex4_undef_touch_d = ex3_undef_touch_q; + +// Cache Unable to Lock Detection +// icblc/dcblc are taken care of by ex4_blk_touch and ex4_l1dc_dis_lockclr +assign ex2_lockset_instr = ex2_dcbtls_instr_q | ex2_dcbtstls_instr_q | ex2_icbtls_l2_instr_q; +assign ex3_undef_lockset_d = ex2_lockset_instr & ~(ex2_th_fld_c_q | ex2_th_fld_l2_q); +assign ex4_undef_lockset_d = ex3_undef_lockset_q; +assign ex4_cinh_lockset = (ex4_dcbtls_instr_q | ex4_dcbtstls_instr_q | ex4_icbtls_l2_instr_q) & derat_dcc_ex4_wimge[1]; +assign ex4_l1dc_dis_lockset = (ex4_dcbtls_instr_q | ex4_dcbtstls_instr_q) & ex4_th_fld_c_q & spr_xucr0_dcdis_q; +assign ex4_l1dc_dis_lockclr = ex4_dcblc_instr_q & ex4_th_fld_c_q & spr_xucr0_dcdis_q; +assign ex4_noop_lockset = (ex4_dcbtls_instr_q | ex4_dcbtstls_instr_q | ex4_icbtls_l2_instr_q) & derat_dcc_ex4_noop_touch; +assign ex5_unable_2lock_d = (ex4_undef_lockset_q | ex4_cinh_lockset | ex4_l1dc_dis_lockset | ex4_noop_lockset) & ex4_wNComp_rcvd_q & ex4_cache_acc_q & ~fgen_ex4_stg_flush_int; +assign ex6_stq5_unable_2lock_d = (ex5_unable_2lock_q & ~fgen_ex5_stg_flush_int) | lsq_ctl_stq4_xucr0_cul; + +// ex3 Data touch ops, DCBT/DCBTST/DCBTLS/DCBTSTLS +assign data_touch_op = ex3_dcbt_instr_q | ex3_dcbtst_instr_q | ex3_dcbtls_instr_q | ex3_dcbtstls_instr_q; +// ex3 Instruction touch ops, ICBT/ICBTLS +assign inst_touch_op = ex3_icbt_l2_instr_q | ex3_icbtls_l2_instr_q; + +// Ops that should not execute if translated to cache-inh +assign all_touch_op = data_touch_op | inst_touch_op; + +// ex3 DCBTLS/DCBTSTLS instruction that should set the Lock bit for the cacheline +assign ex3_l1_lock_set = (ex3_dcbtstls_instr_q | ex3_dcbtls_instr_q) & ex3_th_fld_c_q; +assign ex4_l1_lock_set_d = ex3_l1_lock_set; +assign ex5_l1_lock_set_d = ex4_l1_lock_set_q; +assign ex4_c_dcbtls = ex4_dcbtls_instr_q & ex4_th_fld_c_q; +assign ex4_c_dcbtstls = ex4_dcbtstls_instr_q & ex4_th_fld_c_q; +assign ex4_c_icbtls = ex4_icbtls_l2_instr_q & ex4_th_fld_c_q; +assign ex4_l2_dcbtls = ex4_dcbtls_instr_q & ex4_th_fld_l2_q; +assign ex4_l2_dcbtstls = ex4_dcbtstls_instr_q & ex4_th_fld_l2_q; +assign ex4_l2_icbtls = ex4_icbtls_l2_instr_q & ex4_th_fld_l2_q; +assign ex4_l2_icblc = ex4_icblc_l2_instr_q & ex4_th_fld_l2_q; +assign ex4_l2_dcblc = ex4_dcblc_instr_q & ex4_th_fld_l2_q; + +// ex3 DCBLC/DCBF/DCBI/LWARX/STWCX/DCBZ instruction that should clear the Lock bit for the cacheline +assign is_lock_clr = (ex3_dcblc_instr_q & ex3_th_fld_c_q) | is_inval_op; +assign ex4_lock_clr_d = is_lock_clr; +assign ex5_lock_clr_d = ex4_lock_clr_q; + +// Blockable Touches +assign ex4_c_inh_drop_op_d = (all_touch_op | ex3_icblc_l2_instr_q | ex3_dcblc_instr_q) & ((ex3_cache_acc_q & ~fgen_ex3_stg_flush_int) | ex3_pfetch_val_q); +assign ex4_blkable_touch_d = ex3_dcbt_instr_q | ex3_dcbtst_instr_q | ex3_icbt_l2_instr_q | ex3_undef_touch_q; +assign ex4_excp_touch = ex4_blkable_touch_q & derat_dcc_ex4_noop_touch; +assign ex4_cinh_touch = ex4_cache_inhibited & ex4_c_inh_drop_op_q; +assign ex4_blk_touch = ex4_excp_touch | ex4_cinh_touch | ex4_undef_touch_q | (ex4_pfetch_val_q & (derat_dcc_ex4_wimge[3] | lsq_ctl_sync_in_stq)); +assign ex4_blk_touch_instr = ex4_undef_touch_q; +assign ex5_blk_touch_d = ex4_blk_touch; +assign ex6_blk_touch_d = ex5_blk_touch_q; + +// Sync Type Instructions +// ################################################################ + +// ex3 HSYNC/LWSYNC/MBAR/TLBSYNC/MAKEITSO +assign is_mem_bar_op = ex3_sync_instr_q | ex3_mbar_instr_q | ex3_tlbsync_instr_q | ex3_makeitso_instr_q; +assign ex4_is_sync_d = is_mem_bar_op & ~fgen_ex3_stg_flush_int; + +// Line Invalidating Type Instructions +// ################################################################ + +// ex3 DCBF/DCBI/LWARX/STWCX/DCBZ/ICSWX instruction that should invalidate the L1 Directory if there is a Hit +assign ex3_icswx_type = ex3_icswx_instr_q | ex3_icswxdot_instr_q | ex3_icswx_epid_q; +assign ex4_icswx_type = ex4_icswx_instr_q | ex4_icswxdot_instr_q | ex4_icswx_epid_q; +assign is_inval_op = ex3_dcbf_instr_q | ex3_dcbi_instr_q | ex3_resv_instr_q | ex3_dcbz_instr_q | ex3_icswx_type; +assign ex4_is_inval_op_d = is_inval_op; + +// Hit/Miss Calculation +// ################################################################ + +// Type of Hit +assign stq3_store_hit = dir_dcc_stq3_hit & stq3_store_val_q & ~(stq3_ci_q | stq3_resv_q); +assign stq4_store_hit_d = stq3_store_hit; +assign stq5_store_hit_d = stq4_store_hit_q; +assign stq6_store_hit_d = stq5_store_hit_q; +assign ex4_load_hit = dir_dcc_ex4_hit & ex4_load_type_q & ex4_cache_enabled & ~(fgen_ex4_stg_flush_int | spr_xucr0_dcdis_q | ex4_nogpr_upd); +assign ex5_load_hit_d = dir_dcc_ex4_hit & ex4_load_type_q & ex4_cache_enabled & ~(spr_xucr0_dcdis_q | ex4_resv_instr_q | ex4_l2_dcbtls | ex4_l2_dcbtstls); +assign ex6_load_hit_d = ex5_load_hit_q; +assign stq4_dcarr_wren_d = dir_dcc_rel3_dcarr_upd | stq3_store_hit; + +// Type of Miss +assign stq3_store_miss = ~dir_dcc_stq3_hit & (stq3_store_val_q | stq3_resv_q) & ~stq3_ci_q; +assign stq4_store_miss_d = stq3_store_miss; +assign ex4_load_miss = (dir_dcc_ex4_miss | spr_xucr0_dcdis_q) & ex4_load_type_q & ex4_cache_enabled; +assign ex5_load_miss_d = ex4_load_miss; +assign ex5_drop_rel_d = (dir_dcc_ex4_hit & (ex4_dcbtls_instr_q | ex4_dcbtstls_instr_q)) | (ex4_th_fld_l2_q & (ex4_dcbt_instr_q | ex4_dcbtst_instr_q | ex4_dcbtls_instr_q | ex4_dcbtstls_instr_q)) | + (ex4_icbt_l2_instr_q | ex4_icbtls_l2_instr_q); + +// WIMGE and USR_DEF +// ################################################################ + +// Cacheline State Bits +assign ex3_le_mode = derat_dcc_ex3_wimge_e; +assign ex4_le_mode_d = ex3_le_mode; +assign ex5_wimge_i_bits_d = derat_dcc_ex4_wimge[1]; +assign ex5_usr_bits_d = derat_dcc_ex4_usr_bits; +assign ex5_classid_d = derat_dcc_ex4_wlc; +assign ex4_cache_enabled = (ex4_cache_acc_q | ex4_pfetch_val_q) & ~derat_dcc_ex4_wimge[1]; +assign ex4_cache_inhibited = (ex4_cache_acc_q | ex4_pfetch_val_q) & derat_dcc_ex4_wimge[1]; +assign ex4_mem_attr = {derat_dcc_ex4_usr_bits, derat_dcc_ex4_wimge}; +assign ex5_derat_setHold_d = derat_dcc_ex4_setHold; + +// Misc. Control +// ################################################################ + +// LQ Pipe Directory Access Instructions +assign ddir_acc_instr = ex3_load_instr_q | ex3_ldawx_instr_q | data_touch_op; + +// Ops that should not update the LRU if a miss or hit +assign ex3_lru_upd = (ex3_load_instr_q & ~ex3_resv_instr_q) | (ex3_ldawx_instr_q & ex3_wNComp_rcvd); + +// These instructions should not update the register file but are treated as loads +assign ex4_nogpr_upd = ex4_dcbt_instr_q | ex4_dcbtst_instr_q | ex4_resv_instr_q | ex4_dcbtls_instr_q | ex4_dcbtstls_instr_q; + +// Watch Clear if real address matches +assign ex3_watch_clr_entry = ex3_wclr_instr_q & ex3_l_fld_q[0]; +assign ex3_watch_clr_all = ex3_wclr_instr_q & ~ex3_l_fld_q[0]; + +// Move Register Type Instructions +assign ex4_moveOp_val_d = ex3_mffgpr_val | (ex3_upd_form_q & ex3_cache_acc_q); +assign stq6_moveOp_val_d = stq5_mftgpr_val_q | stq5_mfdpf_val_q | stq5_mfdpa_val_q; + +// ex4 local dcbf is special, need to check against loadmiss queue, +// but dont want to send request to the L2, since this signal does not set +// ex4_l_s_q_val, need to do an OR statement for setbarr_tid and ex4_n_flush_req +// in case it hits against the loadmiss queue +assign ex4_local_dcbf_d = (ex3_local_dcbf | ex3_watch_clr_entry) & ex3_cache_acc_q & ~fgen_ex3_stg_flush_int; + +// Instructions that need to wait for completion +assign ex4_stx_instr = ex4_store_instr_q & ex4_resv_instr_q; +assign ex4_larx_instr = ex4_load_instr_q & ex4_resv_instr_q; + +// misc. instructions +assign ex4_load_val = ex4_load_instr_q & ~ex4_resv_instr_q; +assign ex4_store_val = ex4_store_instr_q & ~ex4_resv_instr_q; +assign ex3_illeg_lswx = ex3_ucode_val_q & ex3_load_instr_q & ex3_strg_index_q & lsq_ctl_ex3_strg_val & lsq_ctl_ex3_illeg_lswx; +assign ex3_strg_index_noop = ex3_ucode_val_q & ex3_strg_index_q & lsq_ctl_ex3_strg_val & lsq_ctl_ex3_strg_noop; +assign ex4_strg_gate_d = ex3_lswx_restart | ex3_strg_index_noop; + +// Other requests that need to be reported to the ORDERQ +// Work Around for DITC +assign ex4_othreq_val = ex4_mffgpr_val | (ex4_wchk_instr_q & ex4_wNComp_rcvd_q) | ex4_ucode_val_q | + ex4_ditc_val; + +// wchkall instruction will complete if not flushed or restarted +assign ex5_wchkall_cplt_d = ex4_wchk_instr_q & ex4_wNComp_rcvd_q & ~ex4_restart_val; +assign ex5_wchkall_cplt = ex5_wchkall_cplt_q & ~lsq_ctl_ex5_stq_restart; + +// LoadPipeline is IDLE +assign ldq_idle_d = ~ldp_pfetch_inPipe & ~dir_arr_rd_tid_busy & derat_dcc_emq_idle; + +// Performance Event +assign ex6_misalign_flush_d = ex5_cache_acc_q & ex5_misalign_flush & ~fgen_ex5_cp_flush; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// LSQ Control Logic +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +// Ops that flow down the Store Queue and require CACHE_ACC to be valid +assign ex2_stq_val_cacc = (ex2_store_instr_q | ex2_dcbf_instr_q | ex2_dcbi_instr_q | ex2_dcbz_instr_q | ex2_wclr_instr_q | + ex2_dcbst_instr_q | ex2_icbi_instr_q | ex2_icswx_instr_q | ex2_icswxdot_instr_q | ex2_icswx_epid_q | + ex2_dcblc_instr_q | ex2_icblc_l2_instr_q) & ex2_cache_acc_q; + +// Ops that flow down the Store Queue and do not require CACHE_ACC to be valid +// Removing DITC +assign ex2_stq_nval_cacc = ex2_msgsnd_instr_q | ex2_mtspr_trace_q | ex2_dci_instr_q | ex2_ici_instr_q | ex2_sync_instr_q | + ex2_mbar_instr_q | ex2_tlbsync_instr_q | ex2_mftgpr_val | ex2_makeitso_instr_q; + +assign ex2_stq_val_req = ex2_stq_val_cacc | ex2_stq_nval_cacc | (ex2_strg_index_q & ex2_ucode_val_q); +assign ex3_stq_val_req_d = ex2_stq_val_req & ~fgen_ex2_stg_flush_int; +assign ex4_stq_val_req_d = ex3_stq_val_req_q & ~fgen_ex3_stg_flush_int; + +// Wait for Next Completion Indicator Instructions +generate begin : cpNextItag + genvar tid; + for (tid=0; tid<`THREADS; tid=tid+1) begin : cpNextItag + assign ex3_wNComp_tid[tid] = ex3_thrd_id_q[tid] & iu_lq_recirc_val_q[tid] & (ex3_itag_q == iu_lq_cp_next_itag_q[tid]); + end + end +endgenerate + +assign ex3_wNComp_rcvd = |(ex3_wNComp_tid); +assign ex4_wNComp_rcvd_d = ex3_wNComp_rcvd; +assign ex3_wNComp = ex3_resv_instr_q | ex3_icbi_instr_q | ex3_ldawx_instr_q | ex3_icswx_instr_q | + ex3_icswxdot_instr_q | ex3_icswx_epid_q | ex3_dcbtls_instr_q | ex3_dcbtstls_instr_q | + ex3_icbtls_l2_instr_q | ex3_watch_clr_all; +assign ex4_wNComp_d = ex3_wNComp; +assign ex5_wNComp_d = ex4_wNComp_q & ~ex4_wNComp_rcvd_q; +assign ex4_guarded_load = derat_dcc_ex4_wimge[3] & ex4_l2load_type_q; +assign ex5_blk_pf_load_d = (derat_dcc_ex4_wimge[1] | derat_dcc_ex4_wimge[3]) & ex4_l2load_type_q; + +// These instructions update a temporary but need to wait for all ops ahead to be completed +// ex4_wchk_instr_q +// These instructions update a temporary and are handled by the load pipe but use the store queue +// ex4_mftgpr_val +// These instructions update a temporary and update a status register +// ex4_mfdpa_val, ex4_mfdpf_val +assign ex4_wNcomp_oth = ex4_wchk_instr_q | ex4_is_sync_q | ex4_mftgpr_val | ex4_mfdpa_val | ex4_mfdpf_val | ex4_is_cinval; +assign ex4_wNComp_req = (((ex4_wNComp_q | ex4_guarded_load) & ex4_cache_acc_q) | ex4_wNcomp_oth); + +// Wait for Next Completion Requests that are handled by the LQ Pipe +// These requests are restarted to RV +assign ex4_lq_wNComp_req = ex4_larx_instr | ex4_ldawx_instr_q | ex4_guarded_load | ex4_wchk_instr_q | + ex4_dcbtls_instr_q | ex4_dcbtstls_instr_q | ex4_icbtls_l2_instr_q; +assign ex5_lq_wNComp_val_d = (ex4_wNComp_req & ex4_lq_wNComp_req & ~(ex4_wNComp_rcvd_q | fgen_ex4_stg_flush_int)) | + (ex4_wNComp_excp & ~(ex4_wNComp_rcvd_q | fgen_ex4_cp_flush_int)); +assign ex6_lq_wNComp_val_d = ex5_lq_wNComp_val_q; + +// Want to report to RV to hold until CP_NEXT_ITAG matches, then release +// dont want these scenarios to keep recirculating +assign ex5_wNComp_ord_d = ex4_wNComp_req & ex4_lq_wNComp_req & ~(ex4_wNComp_rcvd_q | fgen_ex4_stg_flush_int); + +// CR Update is Valid +assign ex5_wNComp_cr_upd_d = ((ex4_ldawx_instr_q & ex4_cache_acc_q) | ex4_wchk_instr_q) & ex4_wNComp_rcvd_q; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// LSQ Entry Data +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +assign ex4_cline_chk = (spr_dcc_spr_lsucr0_clchk | ex4_dcbt_instr_q | ex4_larx_instr | ex4_dcbtls_instr_q | ex4_dcbtst_instr_q | + ex4_dcbtstls_instr_q | ex4_icbt_l2_instr_q | ex4_icbtls_l2_instr_q | ex4_stx_instr | + ex4_icbi_instr_q | ex4_dcbf_instr_q | ex4_dcbi_instr_q | ex4_dcbz_instr_q | + ex4_dcbst_instr_q | ex4_icblc_l2_instr_q | ex4_dcblc_instr_q | derat_dcc_ex4_wimge[1] | + ex4_wclr_instr_q | ex4_ldawx_instr_q | ex4_icswx_instr_q | ex4_icswxdot_instr_q | ex4_icswx_epid_q) & + ~(ex4_tgpr_instr_q | ex4_taxu_instr_q | ex4_tdp_instr_q | ex4_msgsnd_instr_q); + +// All Store instructions that need to go to the L2 +assign ex4_send_l2 = ex4_store_val | ex4_stx_instr | (ex4_dcbf_instr_q & (~ex4_local_dcbf_q)) | ex4_dcbi_instr_q | ex4_dcbz_instr_q | ex4_dcbst_instr_q | + ex4_sync_instr_q | ex4_mbar_instr_q | ex4_tlbsync_instr_q | ex4_l2_icblc | ex4_l2_dcblc | ex4_dci_l2_val | ex4_ici_l2_val | + ex4_msgsnd_instr_q | ex4_icbi_instr_q | ex4_icswx_instr_q | ex4_icswxdot_instr_q | ex4_icswx_epid_q | ex4_mtspr_trace_en | ex4_makeitso_instr_q; + +// All requests that should be dropped +assign ex4_dReq_val = ex4_blk_touch | ex4_ucode_val_q | ex4_mtspr_trace_dis | ex4_is_cinval_drop | ex4_l1dc_dis_lockclr; + +// All Store instructions that have data +// Removing DITC +assign ex4_has_data = ex4_store_val | ex4_stx_instr | ex4_icswx_instr_q | ex4_icswxdot_instr_q | ex4_icswx_epid_q | ex4_mftgpr_val | ex4_strg_index_q; + +// TTYPE Select +assign ex5_ttype_d = ({6{ex4_load_val}} & 6'b001000) | + ({6{ex4_larx_instr}} & ({4'b0010, ex4_mutex_hint_q, 1'b1})) | + ({6{((ex4_dcbt_instr_q & ex4_th_fld_c_q) | ex4_c_dcbtls)}} & 6'b001111) | + ({6{(ex4_dcbt_instr_q & ex4_th_fld_l2_q)}} & 6'b000111) | + ({6{ex4_l2_dcbtls}} & 6'b010111) | + ({6{((ex4_dcbtst_instr_q & ex4_th_fld_c_q) | ex4_c_dcbtstls)}} & 6'b001101) | + ({6{(ex4_dcbtst_instr_q & ex4_th_fld_l2_q)}} & 6'b000101) | + ({6{ex4_l2_dcbtstls}} & 6'b010101) | + ({6{(ex4_icbt_l2_instr_q | ex4_c_icbtls)}} & 6'b000100) | + ({6{ex4_l2_icbtls}} & 6'b010100) | + ({6{ex4_store_val}} & 6'b100000) | + ({6{ex4_stx_instr}} & 6'b101001) | + ({6{ex4_icbi_instr_q}} & 6'b111110) | + ({6{(ex4_dcbf_instr_q & (ex4_l_fld_q == 2'b01))}} & 6'b110110) | + ({6{(ex4_dcbf_instr_q & ~(ex4_l_fld_q == 2'b01))}} & 6'b110111) | + ({6{ex4_dcbi_instr_q}} & 6'b111111) | + ({6{ex4_dcbz_instr_q}} & 6'b100001) | + ({6{ex4_dcbst_instr_q}} & 6'b110101) | + ({6{(ex4_sync_instr_q & ((ex4_l_fld_q != 2'b01)))}} & 6'b101011) | + ({6{(ex4_mbar_instr_q & spr_xucr0_mbar_ack_q)}} & 6'b101011) | //' HWSYNC MODE ENABLED for MBAR + ({6{(ex4_mbar_instr_q & ~spr_xucr0_mbar_ack_q)}} & 6'b110010) | //' HWSYNC MODE DISABLED for MBAR + ({6{(ex4_sync_instr_q & (ex4_l_fld_q == 2'b01))}} & 6'b101010) | + ({6{ex4_makeitso_instr_q}} & 6'b100011) | + ({6{ex4_tlbsync_instr_q}} & 6'b111010) | + ({6{ex4_icblc_l2_instr_q}} & 6'b100100) | + ({6{ex4_dcblc_instr_q}} & 6'b100101) | + ({6{ex4_dci_instr_q}} & 6'b101111) | + ({6{ex4_ici_instr_q}} & 6'b101110) | + ({6{ex4_msgsnd_instr_q}} & 6'b101101) | + ({6{ex4_icswx_instr_q}} & 6'b100110) | + ({6{ex4_icswxdot_instr_q}} & 6'b100111) | + ({6{ex4_mtspr_trace_q}} & 6'b101100) | + ({6{ex4_mfdpf_val}} & 6'b011000) | + ({6{ex4_mfdpa_val}} & 6'b010000) | + ({6{ex4_tdp_instr_q}} & 6'b110000) | + ({6{ex4_mftgpr_val}} & 6'b111000); + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Directory Read Control +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +assign dir_arr_rd_cntrl = {spr_dcc_spr_xudbg0_exec, dir_arr_rd_rv1_done}; + +assign dir_arr_rd_val_d = (dir_arr_rd_cntrl == 2'b10) ? spr_dcc_spr_xudbg0_exec : + (dir_arr_rd_cntrl == 2'b01) ? 1'b0 : + dir_arr_rd_val_q; + +assign dir_arr_rd_tid_d = dir_arr_rd_cntrl[0] ? spr_dcc_spr_xudbg0_tid : + dir_arr_rd_tid_q; + +// Piping Down Directory Read indicator to match up with need hole request +assign dir_arr_rd_rv1_val_d = dir_arr_rd_val_q; + +// Directory Read is done when there isnt a back-invalidate in same stage +// Creating a Pulse, dont want to set done indicator for multiple cycles +assign dir_arr_rd_rv1_done = dir_arr_rd_rv1_val_q & ~(rv1_binv_val_q | dir_arr_rd_ex0_done_q | dir_arr_rd_ex1_done_q | dir_arr_rd_ex2_done_q); + +// Piping Down Done indicator to capture directory contents +assign dir_arr_rd_ex0_done_d = dir_arr_rd_rv1_done; +assign dir_arr_rd_ex1_done_d = dir_arr_rd_ex0_done_q; +assign dir_arr_rd_ex2_done_d = dir_arr_rd_ex1_done_q; +assign dir_arr_rd_ex3_done_d = dir_arr_rd_ex2_done_q; +assign dir_arr_rd_ex4_done_d = dir_arr_rd_ex3_done_q; +assign dir_arr_rd_ex5_done_d = dir_arr_rd_ex4_done_q; +assign dir_arr_rd_ex6_done_d = dir_arr_rd_ex5_done_q; + +// Directory Read In Progress +assign dir_arr_rd_busy = dir_arr_rd_rv1_val_q | dir_arr_rd_ex0_done_q | dir_arr_rd_ex1_done_q | dir_arr_rd_ex2_done_q | + dir_arr_rd_ex3_done_q | dir_arr_rd_ex4_done_q | dir_arr_rd_ex5_done_q | dir_arr_rd_ex6_done_q; + +assign dir_arr_rd_tid_busy = dir_arr_rd_tid_q & {`THREADS{dir_arr_rd_busy}}; + +// Select Tag +assign dir_arr_rd_tag = (spr_dcc_spr_xudbg0_way == 3'b000) ? dir_dcc_ex4_way_tag_a : + (spr_dcc_spr_xudbg0_way == 3'b001) ? dir_dcc_ex4_way_tag_b : + (spr_dcc_spr_xudbg0_way == 3'b010) ? dir_dcc_ex4_way_tag_c : + (spr_dcc_spr_xudbg0_way == 3'b011) ? dir_dcc_ex4_way_tag_d : + (spr_dcc_spr_xudbg0_way == 3'b100) ? dir_dcc_ex4_way_tag_e : + (spr_dcc_spr_xudbg0_way == 3'b101) ? dir_dcc_ex4_way_tag_f : + (spr_dcc_spr_xudbg0_way == 3'b110) ? dir_dcc_ex4_way_tag_g : + dir_dcc_ex4_way_tag_h; + +// Select Directory Contents +assign dir_arr_rd_directory = (spr_dcc_spr_xudbg0_way == 3'b000) ? dir_dcc_ex5_way_a_dir : + (spr_dcc_spr_xudbg0_way == 3'b001) ? dir_dcc_ex5_way_b_dir : + (spr_dcc_spr_xudbg0_way == 3'b010) ? dir_dcc_ex5_way_c_dir : + (spr_dcc_spr_xudbg0_way == 3'b011) ? dir_dcc_ex5_way_d_dir : + (spr_dcc_spr_xudbg0_way == 3'b100) ? dir_dcc_ex5_way_e_dir : + (spr_dcc_spr_xudbg0_way == 3'b101) ? dir_dcc_ex5_way_f_dir : + (spr_dcc_spr_xudbg0_way == 3'b110) ? dir_dcc_ex5_way_g_dir : + dir_dcc_ex5_way_h_dir; + +// Select Directory Tag Parity +assign dir_arr_rd_parity = (spr_dcc_spr_xudbg0_way == 3'b000) ? dir_dcc_ex4_way_par_a : + (spr_dcc_spr_xudbg0_way == 3'b001) ? dir_dcc_ex4_way_par_b : + (spr_dcc_spr_xudbg0_way == 3'b010) ? dir_dcc_ex4_way_par_c : + (spr_dcc_spr_xudbg0_way == 3'b011) ? dir_dcc_ex4_way_par_d : + (spr_dcc_spr_xudbg0_way == 3'b100) ? dir_dcc_ex4_way_par_e : + (spr_dcc_spr_xudbg0_way == 3'b101) ? dir_dcc_ex4_way_par_f : + (spr_dcc_spr_xudbg0_way == 3'b110) ? dir_dcc_ex4_way_par_g : + dir_dcc_ex4_way_par_h; + +assign dir_arr_rd_lru = dir_dcc_ex5_dir_lru; + +// XUDBG0 Register +assign dcc_spr_spr_xudbg0_done = dir_arr_rd_ex5_done_q; + +// XUDBG1 Register +assign xudbg1_dir_reg_d = {dir_arr_rd_directory, dir_arr_rd_lru}; +assign xudbg1_parity_reg_d = dir_arr_rd_parity; + +generate begin : xudbg1Watch + genvar tid; + for (tid=0; tid<4; tid=tid+1) begin : xudbg1Watch + if (tid < `THREADS) begin : tidVal + assign dcc_spr_spr_xudbg1_watch[tid] = xudbg1_dir_reg_q[2+tid]; + end + if (tid >= `THREADS) begin : tidIVal + assign dcc_spr_spr_xudbg1_watch[tid] = 1'b0; + end + end + end +endgenerate + +generate + if (PARBITS == 4) begin : parityFull + assign dcc_spr_spr_xudbg1_parity = xudbg1_parity_reg_q; + end +endgenerate + +generate + if (PARBITS != 4) begin : parityFill + assign dcc_spr_spr_xudbg1_parity[0:3 - PARBITS] = {4-PARBITS{1'b0}}; + assign dcc_spr_spr_xudbg1_parity[4 - PARBITS:3] = xudbg1_parity_reg_q; + end +endgenerate + +assign dcc_spr_spr_xudbg1_lock = xudbg1_dir_reg_q[1]; +assign dcc_spr_spr_xudbg1_valid = xudbg1_dir_reg_q[0]; +assign dcc_spr_spr_xudbg1_lru = xudbg1_dir_reg_q[2+`THREADS:2+`THREADS+6]; + +// XUDBG2 Register +assign xudbg2_tag_d = dir_arr_rd_tag; + +generate + if (TAGSIZE == 31) begin : tagFull + assign dcc_spr_spr_xudbg2_tag = xudbg2_tag_q; + end +endgenerate +generate + if (TAGSIZE != 31) begin : tagFill + assign dcc_spr_spr_xudbg2_tag[33:33+(30-TAGSIZE)] = {31-TAGSIZE{1'b0}}; + assign dcc_spr_spr_xudbg2_tag[33+(31-TAGSIZE):63] = xudbg2_tag_q; + end +endgenerate + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Register File updates +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +// Staging out Update of AXU on a Reload +assign rel2_axu_wren_d = lsq_ctl_rel1_gpr_val & lsq_ctl_rel1_upd_gpr & lsq_ctl_stq1_axu_val; +assign stq2_axu_val_d = lsq_ctl_stq1_axu_val; +assign stq3_axu_val_d = stq2_axu_val_q; +assign stq4_axu_val_d = stq3_axu_val_q; + +assign rel2_ta_gpr_d = lsq_ctl_rel1_ta_gpr; +assign rel2_xu_wren_d = lsq_ctl_rel1_gpr_val & lsq_ctl_rel1_upd_gpr & (~lsq_ctl_stq1_axu_val); + +// Move From DITC to AXU request +// Move Float To GPR request +assign stq6_tgpr_val = stq6_mfdpa_val_q | stq6_mftgpr_val_q; +assign reg_upd_ta_gpr = stq6_tgpr_val ? stq6_tgpr_q : ex4_target_gpr_q; + +assign lq_wren = ex4_load_hit & ~ex4_axu_op_val_q; +assign axu_wren = (ex4_load_hit & ex4_axu_op_val_q) | ex4_mffgpr_val | stq6_mfdpa_val_q; + +assign ex5_lq_wren_d = lq_wren; +assign ex5_lq_wren = ex5_lq_wren_q | (lsq_ctl_ex5_fwd_val & ~ex5_axu_op_val_q); +assign ex6_lq_wren_d = ex5_lq_wren; +assign ex5_axu_wren_d = axu_wren; +assign ex6_axu_wren_d = ex5_axu_wren_q; +assign ex5_lq_ta_gpr_d = reg_upd_ta_gpr; +assign ex6_lq_ta_gpr_d = ex5_lq_ta_gpr_q[AXU_TARGET_ENC-(`GPR_POOL_ENC+`THREADS_POOL_ENC):AXU_TARGET_ENC-1]; +assign ex5_load_le_d = derat_dcc_ex4_wimge[4]; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// RAM Control +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// RAM Active Thread +assign pc_lq_ram_active_d = pc_lq_ram_active; + +// Active Thread for a pipeline instruction +assign ex6_ram_thrd = pc_lq_ram_active_q & ex6_thrd_id_q; +assign ex6_ram_active_thrd = ex6_ram_thrd & {`THREADS{(ex6_lq_wren_q | ex6_axu_wren_q)}}; + +// Active Thread for a MFTGPR instruction +assign stq8_ram_thrd = pc_lq_ram_active_q & stq8_thrd_id_q; +assign stq8_ram_active_thrd = stq8_ram_thrd & {`THREADS{stq8_mftgpr_val_q}}; + +// Active Thread for a reload +assign rel2_ram_thrd = pc_lq_ram_active_q & stq2_thrd_id_q; +assign rel2_ram_active_thrd = rel2_ram_thrd & {`THREADS{(rel2_xu_wren_q | rel2_axu_wren_q)}}; + +// RAM Data Valid +assign lq_ram_data_val = ex6_ram_active_thrd | stq8_ram_active_thrd | rel2_ram_active_thrd; +assign lq_pc_ram_data_val_d = |(lq_ram_data_val); + +// RAM Data ACT +assign dcc_byp_ram_act = |(lq_ram_data_val); + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Performance Events +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Events that need to be reported to Completion +assign perf_com_loadmiss = ex5_cache_acc_q & ex5_load_instr_q & ex5_load_miss_q & ~lsq_ctl_ex5_fwd_val; +assign perf_com_loads = ex5_cache_acc_q & ex5_load_instr_q & ~ex5_wimge_i_bits_q; +assign perf_com_cinh_loads = ex5_cache_acc_q & ex5_load_instr_q & ex5_wimge_i_bits_q; +assign perf_com_dcbt_hit = ex5_cache_acc_q & ex5_perf_dcbt_q & ex5_load_hit_q; +assign perf_com_dcbt_sent = ex5_cache_acc_q & ex5_perf_dcbt_q & ex5_load_miss_q; +assign perf_com_axu_load = ex5_cache_acc_q & ex5_axu_op_val_q & ex5_load_instr_q; +assign perf_com_load_fwd = ex5_cache_acc_q & ex5_load_instr_q & lsq_ctl_ex5_fwd_val; +assign perf_com_watch_set = ex5_cache_acc_q & ex5_ldawx_instr_q; +assign perf_com_watch_dup = ex5_cache_acc_q & ex5_ldawx_instr_q & dir_dcc_ex5_cr_rslt; +assign perf_com_wchkall = ex5_wchkall_cplt; +assign perf_com_wchkall_succ = ex5_wchkall_cplt & ~dir_dcc_ex5_cr_rslt; +assign ex5_cmmt_events = {perf_com_loads, perf_com_loadmiss, perf_com_cinh_loads, perf_com_load_fwd, + perf_com_axu_load, perf_com_dcbt_sent, perf_com_dcbt_hit, perf_com_watch_set, + perf_com_watch_dup, perf_com_wchkall, perf_com_wchkall_succ}; + +// STQ Pipeline Events that do not need to be reported to Completion +assign perf_stq_stores = stq4_store_val_q; +assign perf_stq_store_miss = stq4_store_miss_q; +assign perf_stq_stcx_exec = stq4_rec_stcx_q; +assign perf_stq_axu_store = stq4_store_val_q & stq4_axu_val_q; +assign perf_stq_wclr = stq4_wclr_val_q; +assign perf_stq_wclr_set = stq4_wclr_val_q & stq4_wclr_all_set_q; +assign stq_perf_events = {perf_stq_stores, perf_stq_store_miss, perf_stq_stcx_exec, + perf_stq_axu_store, perf_stq_wclr, perf_stq_wclr_set, stq4_thrd_id_q}; + +// LDQ Pipeline Events +assign perf_ex6_derat_attmpts = 1'b0; +assign perf_ex6_derat_restarts = ex6_cache_acc_q & ex6_restart_val_q & ex6_derat_restart_q; +assign perf_ex6_pfetch_iss = ex6_pfetch_val_q; +assign perf_ex6_pfetch_hit = ex6_pfetch_val_q & ex6_load_hit_q; +assign perf_ex6_pfetch_emiss = ex6_pfetch_val_q & ex6_blk_touch_q; +assign perf_ex6_pfetch_ldq_full = ex6_pfetch_val_q & lsq_ctl_ex6_ldq_events[0]; +assign perf_ex6_pfetch_ldq_hit = ex6_pfetch_val_q & lsq_ctl_ex6_ldq_events[1]; +assign perf_ex6_pfetch_stq = ex6_pfetch_val_q & ex6_stq_restart_val_q; +assign perf_ex6_align_flush = ex6_cache_acc_q & ex6_misalign_flush_q; +assign perf_ex6_dir_restart = ex6_cache_acc_q & ex6_restart_val_q & ex6_dir_restart_q; +assign perf_ex6_dec_restart = ex6_cache_acc_q & ex6_restart_val_q & ex6_dec_restart_q; +assign perf_ex6_wNComp_restart = ex6_cache_acc_q & ex6_restart_val_q & ex6_lq_wNComp_val_q; +assign perf_ex6_ldq_full = ex6_cache_acc_q & ex6_restart_val_q & lsq_ctl_ex6_ldq_events[0]; +assign perf_ex6_ldq_hit = ex6_cache_acc_q & ex6_restart_val_q & lsq_ctl_ex6_ldq_events[1]; +assign perf_ex6_lgq_full = ex6_cache_acc_q & ex6_restart_val_q & lsq_ctl_ex6_ldq_events[2]; +assign perf_ex6_lgq_hit = ex6_cache_acc_q & ex6_restart_val_q & lsq_ctl_ex6_ldq_events[3]; +assign perf_ex6_stq_sametid = ex6_cache_acc_q & ex6_restart_val_q & lsq_ctl_ex6_stq_events[0]; +assign perf_ex6_stq_difftid = ex6_cache_acc_q & ex6_restart_val_q & lsq_ctl_ex6_stq_events[1]; + +assign ex6_dcc_perf_events = {perf_ex6_derat_attmpts, perf_ex6_derat_restarts, perf_ex6_pfetch_iss, + perf_ex6_pfetch_hit, perf_ex6_pfetch_emiss, perf_ex6_pfetch_ldq_full, + perf_ex6_pfetch_ldq_hit, perf_ex6_pfetch_stq, perf_ex6_dir_restart, + perf_ex6_dec_restart, perf_ex6_wNComp_restart, perf_ex6_ldq_full, + perf_ex6_ldq_hit, perf_ex6_lgq_full, perf_ex6_lgq_hit, + perf_ex6_stq_sametid, perf_ex6_stq_difftid, perf_ex6_align_flush, ex6_thrd_id_q}; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Flush Generation +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +lq_fgen fgen( + + // IU Dispatch to RV0 + .ex0_i0_vld(ex0_i0_vld_q), + .ex0_i0_ucode_preissue(ex0_i0_ucode_preissue_q), + .ex0_i0_2ucode(ex0_i0_2ucode_q), + .ex0_i0_ucode_cnt(ex0_i0_ucode_cnt_q), + .ex0_i1_vld(ex0_i1_vld_q), + .ex0_i1_ucode_preissue(ex0_i1_ucode_preissue_q), + .ex0_i1_2ucode(ex0_i1_2ucode_q), + .ex0_i1_ucode_cnt(ex0_i1_ucode_cnt_q), + + // Execution Pipe + .dec_dcc_ex1_expt_det(dec_dcc_ex1_expt_det), + .dec_dcc_ex1_priv_prog(dec_dcc_ex1_priv_prog), + .dec_dcc_ex1_hypv_prog(dec_dcc_ex1_hypv_prog), + .dec_dcc_ex1_illeg_prog(dec_dcc_ex1_illeg_prog), + .dec_dcc_ex1_dlock_excp(dec_dcc_ex1_dlock_excp), + .dec_dcc_ex1_ilock_excp(dec_dcc_ex1_ilock_excp), + .dec_dcc_ex1_ehpriv_excp(dec_dcc_ex1_ehpriv_excp), + .byp_dcc_ex2_req_aborted(byp_dcc_ex2_req_aborted), + + // Control + .ex3_stg_act(ex3_stg_act_q), + .ex4_stg_act(ex4_stg_act_q), + .ex1_thrd_id(dec_dcc_ex1_thrd_id), + .ex2_thrd_id(ex2_thrd_id_q), + .ex3_thrd_id(ex3_thrd_id_q), + .ex4_thrd_id(ex4_thrd_id_q), + .ex5_thrd_id(ex5_thrd_id_q), + .ex3_cache_acc(ex3_cache_acc_q), + .ex3_ucode_val(ex3_ucode_val_q), + .ex3_ucode_cnt(ex3_ucode_cnt_q), + .ex4_ucode_op(ex4_ucode_op_q), + .ex4_mem_attr(ex4_mem_attr), + .ex4_blkable_touch(ex4_blkable_touch_q), + .ex3_ldst_fexcpt(ex3_ldst_fexcpt_q), + .ex3_axu_op_val(ex3_axu_op_val_q), + .ex3_axu_instr_type(ex3_axu_instr_type_q), + .ex3_optype16(ex3_optype16_q), + .ex3_optype8(ex3_optype8_q), + .ex3_optype4(ex3_optype4_q), + .ex3_optype2(ex3_optype2_q), + .ex3_eff_addr(ex3_eff_addr_q[57:63]), + .ex3_icswx_type(ex3_icswx_type), + .ex3_dcbz_instr(ex3_dcbz_instr_q), + .ex3_resv_instr(ex3_resv_instr_q), + .ex3_mword_instr(ex3_mword_instr_q), + .ex3_ldawx_instr(ex3_ldawx_instr_q), + .ex3_illeg_lswx(ex3_illeg_lswx), + .ex4_icswx_dsi(ex4_icswx_dsi), + .ex4_wclr_all_val(ex4_wclr_all_val), + .ex4_wNComp_rcvd(ex4_wNComp_rcvd_q), + .ex4_dac_int_det(ex4_dac_int_det), + .ex4_strg_gate(ex4_strg_gate_q), + .ex4_restart_val(ex4_restart_val), + .ex5_restart_val(ex5_restart_val), + + // SPR Bits + .spr_ccr2_ucode_dis(spr_ccr2_ucode_dis_q), + .spr_ccr2_notlb(spr_ccr2_notlb_q), + .spr_xucr0_mddp(spr_xucr0_mddp_q), + .spr_xucr0_mdcp(spr_xucr0_mdcp_q), + .spr_xucr4_mmu_mchk(spr_xucr4_mmu_mchk_q), + .spr_xucr4_mddmh(spr_xucr4_mddmh_q), + + // ERAT Interface + .derat_dcc_ex4_restart(derat_dcc_ex4_restart), + .derat_dcc_ex4_wimge_w(derat_dcc_ex4_wimge[0]), + .derat_dcc_ex4_wimge_i(derat_dcc_ex4_wimge[1]), + .derat_dcc_ex4_miss(derat_dcc_ex4_miss), + .derat_dcc_ex4_tlb_err(derat_dcc_ex4_tlb_err), + .derat_dcc_ex4_dsi(derat_dcc_ex4_dsi), + .derat_dcc_ex4_vf(derat_dcc_ex4_vf), + .derat_dcc_ex4_multihit_err_det(derat_dcc_ex4_multihit_err_det), + .derat_dcc_ex4_multihit_err_flush(derat_dcc_ex4_multihit_err_flush), + .derat_dcc_ex4_tlb_inelig(derat_dcc_ex4_tlb_inelig), + .derat_dcc_ex4_pt_fault(derat_dcc_ex4_pt_fault), + .derat_dcc_ex4_lrat_miss(derat_dcc_ex4_lrat_miss), + .derat_dcc_ex4_tlb_multihit(derat_dcc_ex4_tlb_multihit), + .derat_dcc_ex4_tlb_par_err(derat_dcc_ex4_tlb_par_err), + .derat_dcc_ex4_lru_par_err(derat_dcc_ex4_lru_par_err), + .derat_dcc_ex4_par_err_det(derat_dcc_ex4_par_err_det), + .derat_dcc_ex4_par_err_flush(derat_dcc_ex4_par_err_flush), + .derat_fir_par_err(derat_fir_par_err), + .derat_fir_multihit(derat_fir_multihit), + + // D$ Parity Error Detected + .dir_dcc_ex5_dir_perr_det(dir_dcc_ex5_dir_perr_det), + .dir_dcc_ex5_dc_perr_det(dir_dcc_ex5_dc_perr_det), + .dir_dcc_ex5_dir_perr_flush(dir_dcc_ex5_dir_perr_flush), + .dir_dcc_ex5_dc_perr_flush(dir_dcc_ex5_dc_perr_flush), + .dir_dcc_ex5_multihit_det(dir_dcc_ex5_multihit_det), + .dir_dcc_ex5_multihit_flush(dir_dcc_ex5_multihit_flush), + .dir_dcc_stq4_dir_perr_det(dir_dcc_stq4_dir_perr_det), + .dir_dcc_stq4_multihit_det(dir_dcc_stq4_multihit_det), + .dir_dcc_ex5_stp_flush(dir_dcc_ex5_stp_flush), + + // SPR's + .spr_xucr0_aflsta(spr_xucr0_aflsta_q), + .spr_xucr0_flsta(spr_xucr0_flsta_q), + .spr_ccr2_ap(spr_ccr2_ap_q), + .spr_msr_fp(spr_msr_fp), + .spr_msr_spv(spr_msr_spv), + + // Instruction Flush + .iu_lq_cp_flush(iu_lq_cp_flush_q), + + // Flush Pipe Outputs + .ex4_ucode_restart(ex4_ucode_restart), + .ex4_sfx_excpt_det(ex4_sfx_excpt_det), + .ex4_excp_det(ex4_excp_det), + .ex4_wNComp_excp(ex4_wNComp_excp), + .ex4_wNComp_excp_restart(ex4_wNComp_excp_restart), + .ex5_flush_req(ex5_flush_req), + .ex5_blk_tlb_req(ex5_blk_tlb_req), + .ex5_flush_pfetch(ex5_flush_pfetch), + .fgen_ex4_cp_flush(fgen_ex4_cp_flush_int), + .fgen_ex5_cp_flush(fgen_ex5_cp_flush), + .fgen_ex1_stg_flush(fgen_ex1_stg_flush_int), + .fgen_ex2_stg_flush(fgen_ex2_stg_flush_int), + .fgen_ex3_stg_flush(fgen_ex3_stg_flush_int), + .fgen_ex4_stg_flush(fgen_ex4_stg_flush_int), + .fgen_ex5_stg_flush(fgen_ex5_stg_flush_int), + + // Completion Indicators + .ex5_flush2ucode(ex5_flush2ucode), + .ex5_n_flush(ex5_n_flush), + .ex5_np1_flush(ex5_np1_flush), + .ex5_exception_val(ex5_exception_val), + .ex5_exception(ex5_exception), + .ex5_dear_val(ex5_dear_val), + + // Performance Events + .ex5_misalign_flush(ex5_misalign_flush), + + // Error Reporting + .lq_pc_err_derat_parity(lq_pc_err_derat_parity), + .lq_pc_err_dir_ldp_parity(lq_pc_err_dir_ldp_parity), + .lq_pc_err_dir_stp_parity(lq_pc_err_dir_stp_parity), + .lq_pc_err_dcache_parity(lq_pc_err_dcache_parity), + .lq_pc_err_derat_multihit(lq_pc_err_derat_multihit), + .lq_pc_err_dir_ldp_multihit(lq_pc_err_dir_ldp_multihit), + .lq_pc_err_dir_stp_multihit(lq_pc_err_dir_stp_multihit), + + //pervasive + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .sg_0(sg_0), + .func_sl_thold_0_b(func_sl_thold_0_b), + .func_sl_force(func_sl_force), + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .scan_in(fgen_scan_in), + .scan_out(fgen_scan_out) +); + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Execution Pipe Outputs +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +assign dcc_dir_ex2_frc_align2 = ex2_ldst_falign_q & ex2_optype2_q; +assign dcc_dir_ex2_frc_align4 = ex2_ldst_falign_q & ex2_optype4_q; +assign dcc_dir_ex2_frc_align8 = ex2_ldst_falign_q & ex2_optype8_q; +assign dcc_dir_ex2_frc_align16 = ex2_ldst_falign_q & ex2_optype16_q; +assign dcc_dir_spr_xucr2_rmt = way_lck_rmt; +assign dcc_dir_ex2_64bit_agen = ex2_lsu_64bit_agen_q; +assign dcc_dir_ex4_p_addr = ex4_p_addr[64-`REAL_IFAR_WIDTH:63-(`DC_SIZE- 3)]; + +assign ctl_dat_ex3_opsize = ex3_opsize; +assign ctl_dat_ex3_le_mode = ex3_le_mode; +assign ctl_dat_ex3_le_ld_rotsel = ex3_eff_addr_q[60:63]; +assign ctl_dat_ex3_be_ld_rotsel = ex3_rot_sel_non_le[1:4]; +assign ctl_dat_ex3_algebraic = ex3_algebraic_q; +assign ctl_dat_ex3_le_alg_rotsel = ex3_alg_bit_le_sel[1:4]; +assign dcc_byp_ex4_moveOp_val = ex4_moveOp_val_q; +assign dcc_byp_stq6_moveOp_val = stq6_moveOp_val_q; +assign dcc_byp_ex4_move_data = ex4_eff_addr_q; +assign dcc_byp_ex5_lq_req_abort = ex5_lq_req_abort; +assign dcc_byp_ex5_byte_mask = ex5_byte_mask[(8-((2 ** `GPR_WIDTH_ENC)/8)):7]; +assign dcc_byp_ex6_thrd_id = ex6_thrd_id_q; +assign dcc_byp_ex6_dvc1_en = ex6_dvc_en_q[0]; +assign dcc_byp_ex6_dvc2_en = ex6_dvc_en_q[1]; +assign dcc_byp_ex6_dacr_cmpr = ex6_dacrw_cmpr_q; +assign dcc_dec_arr_rd_rv1_val = dir_arr_rd_rv1_done; +assign dcc_dec_arr_rd_congr_cl = spr_dcc_spr_xudbg0_row; +assign dcc_dec_stq3_mftgpr_val = stq3_mftgpr_val_q; +assign dcc_dec_stq5_mftgpr_val = stq5_mftgpr_val_q; +assign ctl_lsq_ex2_streq_val = ex2_thrd_id_q & {`THREADS{ex2_stq_val_req}}; +assign ctl_lsq_ex2_itag = ex2_itag_q; +assign ctl_lsq_ex2_thrd_id = ex2_thrd_id_q; +assign ctl_lsq_ex3_ldreq_val = ex3_thrd_id_q & {`THREADS{(ex3_cache_acc_q & ex4_l2load_type_d)}}; +assign ctl_lsq_ex3_wchkall_val = ex3_thrd_id_q & {`THREADS{ex3_wchk_instr_q}}; +assign ctl_lsq_ex3_pfetch_val = ex3_pfetch_val_q; +assign ctl_lsq_ex3_byte_en = ex3_byte_en; +assign ctl_lsq_ex3_p_addr = ex3_eff_addr_q[58:63]; +assign ctl_lsq_ex3_thrd_id = ex3_thrd_id_q; +assign ctl_lsq_ex3_algebraic = ex3_algebraic_q; +assign ctl_lsq_ex3_opsize = ex3_opsize_enc; + +// these should be 1-hot (ex4_ldreq_val & ex4_binvreq_val & ex4_streq_val & ex4_othreq_val) +assign ctl_lsq_ex4_ldreq_val = ex4_cache_acc_q & ex4_l2load_type_q & (~ex4_wNComp_req | ex4_wNComp_rcvd_q) & ~(fgen_ex4_stg_flush_int | ex4_restart_val); +assign ctl_lsq_ex4_binvreq_val = ex4_binv_val_q; +assign ctl_lsq_ex4_streq_val = ex4_stq_val_req_q & ~(fgen_ex4_stg_flush_int | ex4_restart_val); +assign ctl_lsq_ex4_othreq_val = ex4_othreq_val & ~(fgen_ex4_stg_flush_int | ex4_restart_val); +assign ctl_lsq_ex4_p_addr = ex4_p_addr[64-`REAL_IFAR_WIDTH:57]; +assign ctl_lsq_ex4_dReq_val = ex4_dReq_val; +assign ctl_lsq_ex4_gath_load = ex4_gath_load_q; +assign ctl_lsq_ex4_send_l2 = ex4_send_l2; +assign ctl_lsq_ex4_has_data = ex4_has_data; +assign ctl_lsq_ex4_cline_chk = ex4_cline_chk; +assign ctl_lsq_ex4_wimge = derat_dcc_ex4_wimge; +assign ctl_lsq_ex4_byte_swap = ex4_le_mode_q; +assign ctl_lsq_ex4_is_sync = ex4_is_sync_q; +assign ctl_lsq_ex4_all_thrd_chk = ex4_dci_instr_q & (ex4_th_fld_l2_q | ex4_th_fld_c_q); +assign ctl_lsq_ex4_is_store = ex4_store_val; +assign ctl_lsq_ex4_is_resv = ex4_resv_instr_q; +assign ctl_lsq_ex4_is_mfgpr = ex4_mftgpr_val | ex4_mfdpf_val | ex4_mfdpa_val; +assign ctl_lsq_ex4_is_icswxr = ex4_icswx_instr_q | ex4_icswxdot_instr_q | ex4_icswx_epid_q; +assign ctl_lsq_ex4_is_icbi = ex4_icbi_instr_q; +assign ctl_lsq_ex4_watch_clr = ex4_wclr_instr_q; +assign ctl_lsq_ex4_watch_clr_all = ex4_wclr_all_val; +assign ctl_lsq_ex4_mtspr_trace = ex4_mtspr_trace_q; +assign ctl_lsq_ex4_is_inval_op = ex4_is_inval_op_q; +assign ctl_lsq_ex4_is_cinval = ex4_is_cinval; +assign ctl_lsq_ex5_lock_clr = ex5_lock_clr_q; +assign ctl_lsq_ex5_lock_set = ex5_l1_lock_set_q; +assign ctl_lsq_ex5_watch_set = ex5_ldawx_instr_q; +assign ctl_lsq_ex5_tgpr = ex5_target_gpr_q; +assign ctl_lsq_ex5_axu_val = ex5_axu_op_val_q; +assign ctl_lsq_ex5_is_epid = ex5_icswx_epid_q; +assign ctl_lsq_ex5_usr_def = ex5_usr_bits_q; +assign ctl_lsq_ex5_not_touch = ex5_load_instr_q; +assign ctl_lsq_ex5_class_id = ex5_classid_q; +assign ctl_lsq_ex5_dvc = ex5_dvc_en_q; +assign ctl_lsq_ex5_dacrw = ex5_dacrw_cmpr_q; +assign ctl_lsq_ex5_ttype = ex5_ttype_q; +assign ctl_lsq_ex5_l_fld = ex5_l_fld_q; +assign ctl_lsq_ex5_load_hit = ex5_load_hit_q; +assign ctl_lsq_ex5_drop_rel = ex5_drop_rel_q; +assign ctl_lsq_ex5_flush_req = ex5_flush_req; +assign ctl_lsq_ex5_flush_pfetch = ex5_flush_pfetch | ex5_restart_val_q; +assign ctl_lsq_ex5_cmmt_events = ex5_cmmt_events; +assign ctl_lsq_ex5_perf_val0 = &(ex5_spr_lesr[0:1]); +assign ctl_lsq_ex5_perf_sel0 = ex5_spr_lesr[2:5]; +assign ctl_lsq_ex5_perf_val1 = &(ex5_spr_lesr[6:7]); +assign ctl_lsq_ex5_perf_sel1 = ex5_spr_lesr[8:11]; +assign ctl_lsq_ex5_perf_val2 = &(ex5_spr_lesr[12:13]); +assign ctl_lsq_ex5_perf_sel2 = ex5_spr_lesr[14:17]; +assign ctl_lsq_ex5_perf_val3 = &(ex5_spr_lesr[18:19]); +assign ctl_lsq_ex5_perf_sel3 = ex5_spr_lesr[20:23]; +assign ctl_lsq_stq3_icswx_data = {stq3_icswx_data_q[0:10], 2'b00, stq3_icswx_data_q[11:24]}; +assign ctl_lsq_stq_cpl_blk = ex5_lq_comp_rpt_val; +assign ctl_lsq_rv1_dir_rd_val = dir_arr_rd_rv1_done; +assign ctl_lsq_dbg_int_en = dbg_int_en_q; +assign ctl_lsq_ldp_idle = ldq_idle_q; +assign stq4_dcarr_wren = stq4_dcarr_wren_q; +assign dcc_byp_ram_sel = |(rel2_ram_active_thrd); +assign dcc_dec_ex5_wren = ex5_lq_wren; +assign dcc_byp_rel2_stg_act = stq2_stg_act_q; +assign dcc_byp_rel3_stg_act = stq3_stg_act_q; +assign lq_xu_ex5_abort = ex5_lq_req_abort | dec_dcc_ex5_req_abort_rpt; +assign lq_xu_gpr_ex5_wa = ex5_lq_ta_gpr_q; +assign lq_rv_gpr_ex6_wa = ex6_lq_ta_gpr_q; +assign lq_xu_axu_rel_we = rel2_axu_wren_q; +assign lq_xu_gpr_rel_we = rel2_xu_wren_q; +assign lq_xu_gpr_rel_wa = rel2_ta_gpr_q; +assign lq_rv_gpr_rel_we = rel2_xu_wren_q; +assign lq_rv_gpr_rel_wa = rel2_ta_gpr_q[AXU_TARGET_ENC-(`GPR_POOL_ENC+`THREADS_POOL_ENC):AXU_TARGET_ENC-1]; +assign lq_xu_cr_ex5_we = ex5_wNComp_cr_upd_q; +assign lq_xu_cr_ex5_wa = ex5_cr_fld_q; +assign lq_xu_ex5_cr = ex5_cr_wd; +assign dcc_dir_ex2_binv_val = ex2_binv_val_q; +assign dcc_dir_ex2_thrd_id = ex2_thrd_id_q; +assign dcc_dir_ex3_lru_upd = ex3_lru_upd; +assign dcc_dir_ex3_cache_acc = ex3_cache_acc_q & ex3_load_type; +assign dcc_dir_ex3_pfetch_val = ex3_pfetch_val_q; +assign dcc_derat_ex3_strg_noop = ex3_lswx_restart | ex3_strg_index_noop; +assign dcc_derat_ex5_blk_tlb_req = ex5_blk_tlb_req; +assign dcc_derat_ex6_cplt = ex6_thrd_id_q & {`THREADS{ex6_lq_comp_rpt_q}}; +assign dcc_derat_ex6_cplt_itag = ex6_itag_q; +assign dcc_dir_ex3_lock_set = (ex3_dcbtstls_instr_q | ex3_dcbtls_instr_q) & ex3_cache_acc_q & ex3_wNComp_rcvd; +assign dcc_dir_ex3_th_c = ex3_th_fld_c_q; +assign dcc_dir_ex3_watch_set = ex3_ldawx_instr_q & ex3_cache_acc_q & ex3_wNComp_rcvd; +assign dcc_dir_ex3_larx_val = ex3_load_instr_q & ex3_resv_instr_q & ex3_cache_acc_q & ex3_wNComp_rcvd; +assign dcc_dir_ex3_watch_chk = ex3_wchk_instr_q & ex3_wNComp_rcvd; +assign dcc_dir_ex3_ddir_acc = ddir_acc_instr & ((ex3_cache_acc_q & ~(derat_dcc_ex3_itagHit | fgen_ex3_stg_flush_int)) | ex3_pfetch_val_q); +assign dcc_dir_ex4_load_val = ex4_load_val & ex4_cache_enabled & ~(spr_xucr0_dcdis_q | ex4_derat_itagHit_q); // Want to gate off parity detection if dcdis=1 or DERAT Itag Hit +assign dcc_spr_ex3_data_val = (ex3_load_instr_q | ex3_store_instr_q) & ~ex3_axu_op_val_q; +assign dcc_spr_ex3_eff_addr = ex3_eff_addr_q; +assign dcc_dir_stq6_store_val = stq6_store_hit_q; +assign lq_pc_ram_data_val = lq_pc_ram_data_val_q; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Outputs to LQ Pervasive +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +assign ctl_perv_ex6_perf_events = ex6_dcc_perf_events; +assign ctl_perv_stq4_perf_events = stq_perf_events; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Outputs to Reservation Station +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +assign lq_rv_itag1_vld = ex5_spec_tid_q & {`THREADS{ex5_spec_itag_vld_q}}; +assign lq_rv_itag1 = ex5_spec_itag_q; +assign lq_rv_itag1_restart = ex5_restart_val; +assign lq_rv_itag1_abort = ex5_lq_req_abort; +assign lq_rv_itag1_hold = (lsq_ctl_rv_set_hold | ex5_derat_setHold_q) & ex5_restart_val; +assign lq_rv_itag1_cord = ex5_wNComp_ord_q & ~ex5_flush_req; +assign lq_rv_clr_hold = lsq_ctl_rv_clr_hold | derat_dcc_clr_hold; +assign dcc_dec_hold_all = dir_arr_rd_val_q | lsq_ctl_rv_hold_all; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Outputs to Completion +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +assign lq0_iu_execute_vld = lq0_iu_execute_vld_q; +assign lq0_iu_flush2ucode_type = lq0_iu_flush2ucode_type_q; +assign lq0_iu_recirc_val = lq0_iu_recirc_val_q; +assign lq0_iu_itag = lq0_iu_itag_q; +assign lq0_iu_flush2ucode = lq0_iu_flush2ucode_q; +assign lq0_iu_n_flush = lq0_iu_n_flush_q; +assign lq0_iu_np1_flush = lq0_iu_np1_flush_q; +assign lq0_iu_exception_val = lq0_iu_exception_val_q; +assign lq0_iu_exception = lq0_iu_exception_q; +assign lq0_iu_dear_val = lq0_iu_dear_val_q; +assign lq0_iu_eff_addr = lq0_iu_eff_addr_q; +assign lq0_iu_dacr_type = lq0_iu_dacr_type_q; +assign lq0_iu_dacrw = lq0_iu_dacrw_q; +assign lq0_iu_instr = lq0_iu_instr_q; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Outputs to Prefetch +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +assign dcc_pf_ex5_eff_addr = ex5_eff_addr_q[64-(2 ** `GPR_WIDTH_ENC):59]; +assign dcc_pf_ex5_req_val_4pf = ex5_cache_acc_q & ex5_load_instr_q & ~ex5_wNComp_q & ~ex5_lq_wNComp_val_q & ~spr_xucr0_dcdis_q & ~ex5_blk_pf_load_q & ~fgen_ex5_stg_flush_int; +assign dcc_pf_ex5_act = ex5_cache_acc_q & ex5_load_instr_q & ~ex5_wNComp_q & ~ex5_lq_wNComp_val_q & ~spr_xucr0_dcdis_q; +assign dcc_pf_ex5_thrd_id = ex5_thrd_id_q; +assign dcc_pf_ex5_loadmiss = ex5_load_miss_q; +assign dcc_pf_ex5_itag = ex5_itag_q; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Stage Flush Outputs +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +assign fgen_ex1_stg_flush = fgen_ex1_stg_flush_int; +assign fgen_ex2_stg_flush = fgen_ex2_stg_flush_int; +assign fgen_ex3_stg_flush = fgen_ex3_stg_flush_int; +assign fgen_ex4_cp_flush = fgen_ex4_cp_flush_int; +assign fgen_ex4_stg_flush = fgen_ex4_stg_flush_int; +assign fgen_ex5_stg_flush = fgen_ex5_stg_flush_int; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// SPR Outputs +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +assign lq_xu_spr_xucr0_cul = ex6_stq5_unable_2lock_q; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// AXU Outputs +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +assign lq_xu_axu_ex4_addr = ex4_eff_addr_q[59:63]; +assign lq_xu_axu_ex5_we = ex5_axu_wren_q | (lsq_ctl_ex5_fwd_val & ex5_axu_op_val_q) | dec_dcc_ex5_axu_abort_rpt; +assign lq_xu_axu_ex5_le = ex5_load_le_q; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// DIRECTORY ACT Controls +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +assign dcc_dir_ex2_stg_act = ex2_stg_act_q; +assign dcc_dir_ex3_stg_act = ex3_stg_act_q; +assign dcc_dir_ex4_stg_act = ex4_stg_act_q; +assign dcc_dir_ex5_stg_act = ex5_stg_act_q; +assign dcc_dir_stq1_stg_act = stq1_stg_act; +assign dcc_dir_stq2_stg_act = stq2_stg_act_q; +assign dcc_dir_stq3_stg_act = stq3_stg_act_q; +assign dcc_dir_stq4_stg_act = stq4_stg_act_q; +assign dcc_dir_stq5_stg_act = stq5_stg_act_q; +assign dcc_dir_binv2_ex2_stg_act = ex2_binv2_stg_act; +assign dcc_dir_binv3_ex3_stg_act = ex3_binv3_stg_act; +assign dcc_dir_binv4_ex4_stg_act = ex4_binv4_stg_act; +assign dcc_dir_binv5_ex5_stg_act = ex5_binv5_stg_act; +assign dcc_dir_binv6_ex6_stg_act = ex6_binv6_stg_act; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Registers +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) iu_lq_recirc_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[iu_lq_recirc_val_offset:iu_lq_recirc_val_offset + `THREADS - 1]), + .scout(sov[iu_lq_recirc_val_offset:iu_lq_recirc_val_offset + `THREADS - 1]), + .din(iu_lq_recirc_val_d), + .dout(iu_lq_recirc_val_q) +); + +generate begin : iu_lq_cp_next_itag_tid + genvar tid; + for (tid=0; tid<`THREADS; tid=tid+1) begin : iu_lq_cp_next_itag_tid + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) iu_lq_cp_next_itag_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[iu_lq_cp_next_itag_offset + `ITAG_SIZE_ENC * tid:iu_lq_cp_next_itag_offset + `ITAG_SIZE_ENC * (tid + 1) - 1]), + .scout(sov[iu_lq_cp_next_itag_offset + `ITAG_SIZE_ENC * tid:iu_lq_cp_next_itag_offset + `ITAG_SIZE_ENC * (tid + 1) - 1]), + .din(iu_lq_cp_next_itag[tid*`ITAG_SIZE_ENC:tid*`ITAG_SIZE_ENC+(`ITAG_SIZE_ENC-1)]), + .dout(iu_lq_cp_next_itag_q[tid]) + ); + end + end +endgenerate + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) iu_lq_cp_flush_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[iu_lq_cp_flush_offset:iu_lq_cp_flush_offset + `THREADS - 1]), + .scout(sov[iu_lq_cp_flush_offset:iu_lq_cp_flush_offset + `THREADS - 1]), + .din(iu_lq_cp_flush_d), + .dout(iu_lq_cp_flush_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) xer_lq_cp_rd_so_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[xer_lq_cp_rd_so_offset:xer_lq_cp_rd_so_offset + `THREADS - 1]), + .scout(sov[xer_lq_cp_rd_so_offset:xer_lq_cp_rd_so_offset + `THREADS - 1]), + .din(xer_lq_cp_rd_so_d), + .dout(xer_lq_cp_rd_so_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex0_i0_vld_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_i0_vld_offset:ex0_i0_vld_offset + `THREADS - 1]), + .scout(sov[ex0_i0_vld_offset:ex0_i0_vld_offset + `THREADS - 1]), + .din(ex0_i0_vld_d), + .dout(ex0_i0_vld_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_i0_ucode_preissue_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_i0_ucode_preissue_offset]), + .scout(sov[ex0_i0_ucode_preissue_offset]), + .din(ex0_i0_ucode_preissue_d), + .dout(ex0_i0_ucode_preissue_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_i0_2ucode_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_i0_2ucode_offset]), + .scout(sov[ex0_i0_2ucode_offset]), + .din(ex0_i0_2ucode_d), + .dout(ex0_i0_2ucode_q) +); + +tri_rlmreg_p #(.WIDTH(`UCODE_ENTRIES_ENC), .INIT(0), .NEEDS_SRESET(1)) ex0_i0_ucode_cnt_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_i0_ucode_cnt_offset:ex0_i0_ucode_cnt_offset + `UCODE_ENTRIES_ENC - 1]), + .scout(sov[ex0_i0_ucode_cnt_offset:ex0_i0_ucode_cnt_offset + `UCODE_ENTRIES_ENC - 1]), + .din(ex0_i0_ucode_cnt_d), + .dout(ex0_i0_ucode_cnt_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex0_i1_vld_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_i1_vld_offset:ex0_i1_vld_offset + `THREADS - 1]), + .scout(sov[ex0_i1_vld_offset:ex0_i1_vld_offset + `THREADS - 1]), + .din(ex0_i1_vld_d), + .dout(ex0_i1_vld_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_i1_ucode_preissue_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_i1_ucode_preissue_offset]), + .scout(sov[ex0_i1_ucode_preissue_offset]), + .din(ex0_i1_ucode_preissue_d), + .dout(ex0_i1_ucode_preissue_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_i1_2ucode_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_i1_2ucode_offset]), + .scout(sov[ex0_i1_2ucode_offset]), + .din(ex0_i1_2ucode_d), + .dout(ex0_i1_2ucode_q) +); + +tri_rlmreg_p #(.WIDTH(`UCODE_ENTRIES_ENC), .INIT(0), .NEEDS_SRESET(1)) ex0_i1_ucode_cnt_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_i1_ucode_cnt_offset:ex0_i1_ucode_cnt_offset + `UCODE_ENTRIES_ENC - 1]), + .scout(sov[ex0_i1_ucode_cnt_offset:ex0_i1_ucode_cnt_offset + `UCODE_ENTRIES_ENC - 1]), + .din(ex0_i1_ucode_cnt_d), + .dout(ex0_i1_ucode_cnt_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_optype1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_instr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_optype1_offset]), + .scout(sov[ex2_optype1_offset]), + .din(ex2_optype1_d), + .dout(ex2_optype1_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_optype2_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_instr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_optype2_offset]), + .scout(sov[ex2_optype2_offset]), + .din(ex2_optype2_d), + .dout(ex2_optype2_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_optype4_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_instr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_optype4_offset]), + .scout(sov[ex2_optype4_offset]), + .din(ex2_optype4_d), + .dout(ex2_optype4_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_optype8_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_instr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_optype8_offset]), + .scout(sov[ex2_optype8_offset]), + .din(ex2_optype8_d), + .dout(ex2_optype8_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_optype16_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_instr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_optype16_offset]), + .scout(sov[ex2_optype16_offset]), + .din(ex2_optype16_d), + .dout(ex2_optype16_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_optype1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_optype1_offset]), + .scout(sov[ex3_optype1_offset]), + .din(ex3_optype1_d), + .dout(ex3_optype1_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_optype2_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_optype2_offset]), + .scout(sov[ex3_optype2_offset]), + .din(ex3_optype2_d), + .dout(ex3_optype2_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_optype4_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_optype4_offset]), + .scout(sov[ex3_optype4_offset]), + .din(ex3_optype4_d), + .dout(ex3_optype4_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_optype8_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_optype8_offset]), + .scout(sov[ex3_optype8_offset]), + .din(ex3_optype8_d), + .dout(ex3_optype8_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_optype16_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_optype16_offset]), + .scout(sov[ex3_optype16_offset]), + .din(ex3_optype16_d), + .dout(ex3_optype16_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_dacr_type_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_dacr_type_offset]), + .scout(sov[ex3_dacr_type_offset]), + .din(ex3_dacr_type_d), + .dout(ex3_dacr_type_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_dacr_type_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_dacr_type_offset]), + .scout(sov[ex4_dacr_type_offset]), + .din(ex4_dacr_type_d), + .dout(ex4_dacr_type_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_dacr_type_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_dacr_type_offset]), + .scout(sov[ex5_dacr_type_offset]), + .din(ex5_dacr_type_d), + .dout(ex5_dacr_type_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_cache_acc_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_cache_acc_offset]), + .scout(sov[ex2_cache_acc_offset]), + .din(ex2_cache_acc_d), + .dout(ex2_cache_acc_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_cache_acc_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_cache_acc_offset]), + .scout(sov[ex3_cache_acc_offset]), + .din(ex3_cache_acc_d), + .dout(ex3_cache_acc_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_cache_acc_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_cache_acc_offset]), + .scout(sov[ex4_cache_acc_offset]), + .din(ex4_cache_acc_d), + .dout(ex4_cache_acc_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_cache_acc_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_cache_acc_offset]), + .scout(sov[ex5_cache_acc_offset]), + .din(ex5_cache_acc_d), + .dout(ex5_cache_acc_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_cache_acc_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_cache_acc_offset]), + .scout(sov[ex6_cache_acc_offset]), + .din(ex6_cache_acc_d), + .dout(ex6_cache_acc_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex2_thrd_id_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_instr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_thrd_id_offset:ex2_thrd_id_offset + `THREADS - 1]), + .scout(sov[ex2_thrd_id_offset:ex2_thrd_id_offset + `THREADS - 1]), + .din(ex2_thrd_id_d), + .dout(ex2_thrd_id_q) +); + +tri_regk #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex3_thrd_id_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_thrd_id_offset:ex3_thrd_id_offset + `THREADS - 1]), + .scout(sov[ex3_thrd_id_offset:ex3_thrd_id_offset + `THREADS - 1]), + .din(ex3_thrd_id_d), + .dout(ex3_thrd_id_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex4_thrd_id_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_thrd_id_offset:ex4_thrd_id_offset + `THREADS - 1]), + .scout(sov[ex4_thrd_id_offset:ex4_thrd_id_offset + `THREADS - 1]), + .din(ex4_thrd_id_d), + .dout(ex4_thrd_id_q) +); + +tri_regk #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex5_thrd_id_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_thrd_id_offset:ex5_thrd_id_offset + `THREADS - 1]), + .scout(sov[ex5_thrd_id_offset:ex5_thrd_id_offset + `THREADS - 1]), + .din(ex5_thrd_id_d), + .dout(ex5_thrd_id_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex6_thrd_id_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_thrd_id_offset:ex6_thrd_id_offset + `THREADS - 1]), + .scout(sov[ex6_thrd_id_offset:ex6_thrd_id_offset + `THREADS - 1]), + .din(ex6_thrd_id_d), + .dout(ex6_thrd_id_q) +); + +tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) ex2_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_instr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_instr_offset:ex2_instr_offset + 32 - 1]), + .scout(sov[ex2_instr_offset:ex2_instr_offset + 32 - 1]), + .din(ex2_instr_d), + .dout(ex2_instr_q) +); + +tri_regk #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) ex3_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_instr_offset:ex3_instr_offset + 32 - 1]), + .scout(sov[ex3_instr_offset:ex3_instr_offset + 32 - 1]), + .din(ex3_instr_d), + .dout(ex3_instr_q) +); + +tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) ex4_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_instr_offset:ex4_instr_offset + 32 - 1]), + .scout(sov[ex4_instr_offset:ex4_instr_offset + 32 - 1]), + .din(ex4_instr_d), + .dout(ex4_instr_q) +); + +tri_regk #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) ex5_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_instr_offset:ex5_instr_offset + 32 - 1]), + .scout(sov[ex5_instr_offset:ex5_instr_offset + 32 - 1]), + .din(ex5_instr_d), + .dout(ex5_instr_q) +); + +tri_rlmreg_p #(.WIDTH(AXU_TARGET_ENC), .INIT(0), .NEEDS_SRESET(1)) ex2_target_gpr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_instr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_target_gpr_offset:ex2_target_gpr_offset + AXU_TARGET_ENC - 1]), + .scout(sov[ex2_target_gpr_offset:ex2_target_gpr_offset + AXU_TARGET_ENC - 1]), + .din(ex2_target_gpr_d), + .dout(ex2_target_gpr_q) +); + +tri_regk #(.WIDTH(AXU_TARGET_ENC), .INIT(0), .NEEDS_SRESET(1)) ex3_target_gpr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_target_gpr_offset:ex3_target_gpr_offset + AXU_TARGET_ENC - 1]), + .scout(sov[ex3_target_gpr_offset:ex3_target_gpr_offset + AXU_TARGET_ENC - 1]), + .din(ex3_target_gpr_d), + .dout(ex3_target_gpr_q) +); + +tri_rlmreg_p #(.WIDTH(AXU_TARGET_ENC), .INIT(0), .NEEDS_SRESET(1)) ex4_target_gpr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_target_gpr_offset:ex4_target_gpr_offset + AXU_TARGET_ENC - 1]), + .scout(sov[ex4_target_gpr_offset:ex4_target_gpr_offset + AXU_TARGET_ENC - 1]), + .din(ex4_target_gpr_d), + .dout(ex4_target_gpr_q) +); + +tri_regk #(.WIDTH(AXU_TARGET_ENC), .INIT(0), .NEEDS_SRESET(1)) ex5_target_gpr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_target_gpr_offset:ex5_target_gpr_offset + AXU_TARGET_ENC - 1]), + .scout(sov[ex5_target_gpr_offset:ex5_target_gpr_offset + AXU_TARGET_ENC - 1]), + .din(ex5_target_gpr_d), + .dout(ex5_target_gpr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_dcbt_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_instr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_dcbt_instr_offset]), + .scout(sov[ex2_dcbt_instr_offset]), + .din(ex2_dcbt_instr_d), + .dout(ex2_dcbt_instr_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_dcbt_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_dcbt_instr_offset]), + .scout(sov[ex3_dcbt_instr_offset]), + .din(ex3_dcbt_instr_d), + .dout(ex3_dcbt_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_dcbt_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_dcbt_instr_offset]), + .scout(sov[ex4_dcbt_instr_offset]), + .din(ex4_dcbt_instr_d), + .dout(ex4_dcbt_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_pfetch_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_pfetch_val_offset]), + .scout(sov[ex2_pfetch_val_offset]), + .din(ex2_pfetch_val_d), + .dout(ex2_pfetch_val_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_pfetch_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_pfetch_val_offset]), + .scout(sov[ex3_pfetch_val_offset]), + .din(ex3_pfetch_val_d), + .dout(ex3_pfetch_val_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_pfetch_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_pfetch_val_offset]), + .scout(sov[ex4_pfetch_val_offset]), + .din(ex4_pfetch_val_d), + .dout(ex4_pfetch_val_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_pfetch_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_pfetch_val_offset]), + .scout(sov[ex5_pfetch_val_offset]), + .din(ex5_pfetch_val_d), + .dout(ex5_pfetch_val_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_pfetch_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_pfetch_val_offset]), + .scout(sov[ex6_pfetch_val_offset]), + .din(ex6_pfetch_val_d), + .dout(ex6_pfetch_val_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_dcbtst_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_instr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_dcbtst_instr_offset]), + .scout(sov[ex2_dcbtst_instr_offset]), + .din(ex2_dcbtst_instr_d), + .dout(ex2_dcbtst_instr_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_dcbtst_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_dcbtst_instr_offset]), + .scout(sov[ex3_dcbtst_instr_offset]), + .din(ex3_dcbtst_instr_d), + .dout(ex3_dcbtst_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_dcbtst_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_dcbtst_instr_offset]), + .scout(sov[ex4_dcbtst_instr_offset]), + .din(ex4_dcbtst_instr_d), + .dout(ex4_dcbtst_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_wchk_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_wchk_instr_offset]), + .scout(sov[ex2_wchk_instr_offset]), + .din(ex2_wchk_instr_d), + .dout(ex2_wchk_instr_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_wchk_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_wchk_instr_offset]), + .scout(sov[ex3_wchk_instr_offset]), + .din(ex3_wchk_instr_d), + .dout(ex3_wchk_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_wchk_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_wchk_instr_offset]), + .scout(sov[ex4_wchk_instr_offset]), + .din(ex4_wchk_instr_d), + .dout(ex4_wchk_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_dcbst_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_instr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_dcbst_instr_offset]), + .scout(sov[ex2_dcbst_instr_offset]), + .din(ex2_dcbst_instr_d), + .dout(ex2_dcbst_instr_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_dcbst_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_dcbst_instr_offset]), + .scout(sov[ex3_dcbst_instr_offset]), + .din(ex3_dcbst_instr_d), + .dout(ex3_dcbst_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_dcbst_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_dcbst_instr_offset]), + .scout(sov[ex4_dcbst_instr_offset]), + .din(ex4_dcbst_instr_d), + .dout(ex4_dcbst_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_dcbf_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_instr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_dcbf_instr_offset]), + .scout(sov[ex2_dcbf_instr_offset]), + .din(ex2_dcbf_instr_d), + .dout(ex2_dcbf_instr_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_dcbf_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_dcbf_instr_offset]), + .scout(sov[ex3_dcbf_instr_offset]), + .din(ex3_dcbf_instr_d), + .dout(ex3_dcbf_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_dcbf_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_dcbf_instr_offset]), + .scout(sov[ex4_dcbf_instr_offset]), + .din(ex4_dcbf_instr_d), + .dout(ex4_dcbf_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_mtspr_trace_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_mtspr_trace_offset]), + .scout(sov[ex2_mtspr_trace_offset]), + .din(ex2_mtspr_trace_d), + .dout(ex2_mtspr_trace_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_mtspr_trace_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_mtspr_trace_offset]), + .scout(sov[ex3_mtspr_trace_offset]), + .din(ex3_mtspr_trace_d), + .dout(ex3_mtspr_trace_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_mtspr_trace_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_mtspr_trace_offset]), + .scout(sov[ex4_mtspr_trace_offset]), + .din(ex4_mtspr_trace_d), + .dout(ex4_mtspr_trace_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sync_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_sync_instr_offset]), + .scout(sov[ex2_sync_instr_offset]), + .din(ex2_sync_instr_d), + .dout(ex2_sync_instr_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_sync_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_sync_instr_offset]), + .scout(sov[ex3_sync_instr_offset]), + .din(ex3_sync_instr_d), + .dout(ex3_sync_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_sync_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_sync_instr_offset]), + .scout(sov[ex4_sync_instr_offset]), + .din(ex4_sync_instr_d), + .dout(ex4_sync_instr_q) +); + +tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex2_l_fld_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_instr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_l_fld_offset:ex2_l_fld_offset + 2 - 1]), + .scout(sov[ex2_l_fld_offset:ex2_l_fld_offset + 2 - 1]), + .din(ex2_l_fld_d), + .dout(ex2_l_fld_q) +); + +tri_regk #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex3_l_fld_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_l_fld_offset:ex3_l_fld_offset + 2 - 1]), + .scout(sov[ex3_l_fld_offset:ex3_l_fld_offset + 2 - 1]), + .din(ex3_l_fld_d), + .dout(ex3_l_fld_q) +); + +tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex4_l_fld_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_l_fld_offset:ex4_l_fld_offset + 2 - 1]), + .scout(sov[ex4_l_fld_offset:ex4_l_fld_offset + 2 - 1]), + .din(ex4_l_fld_d), + .dout(ex4_l_fld_q) +); + +tri_regk #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex5_l_fld_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_l_fld_offset:ex5_l_fld_offset + 2 - 1]), + .scout(sov[ex5_l_fld_offset:ex5_l_fld_offset + 2 - 1]), + .din(ex5_l_fld_d), + .dout(ex5_l_fld_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_dcbi_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_instr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_dcbi_instr_offset]), + .scout(sov[ex2_dcbi_instr_offset]), + .din(ex2_dcbi_instr_d), + .dout(ex2_dcbi_instr_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_dcbi_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_dcbi_instr_offset]), + .scout(sov[ex3_dcbi_instr_offset]), + .din(ex3_dcbi_instr_d), + .dout(ex3_dcbi_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_dcbi_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_dcbi_instr_offset]), + .scout(sov[ex4_dcbi_instr_offset]), + .din(ex4_dcbi_instr_d), + .dout(ex4_dcbi_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_dcbz_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_instr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_dcbz_instr_offset]), + .scout(sov[ex2_dcbz_instr_offset]), + .din(ex2_dcbz_instr_d), + .dout(ex2_dcbz_instr_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_dcbz_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_dcbz_instr_offset]), + .scout(sov[ex3_dcbz_instr_offset]), + .din(ex3_dcbz_instr_d), + .dout(ex3_dcbz_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_dcbz_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_dcbz_instr_offset]), + .scout(sov[ex4_dcbz_instr_offset]), + .din(ex4_dcbz_instr_d), + .dout(ex4_dcbz_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_icbi_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_instr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_icbi_instr_offset]), + .scout(sov[ex2_icbi_instr_offset]), + .din(ex2_icbi_instr_d), + .dout(ex2_icbi_instr_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_icbi_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_icbi_instr_offset]), + .scout(sov[ex3_icbi_instr_offset]), + .din(ex3_icbi_instr_d), + .dout(ex3_icbi_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_icbi_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_icbi_instr_offset]), + .scout(sov[ex4_icbi_instr_offset]), + .din(ex4_icbi_instr_d), + .dout(ex4_icbi_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_mbar_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_mbar_instr_offset]), + .scout(sov[ex2_mbar_instr_offset]), + .din(ex2_mbar_instr_d), + .dout(ex2_mbar_instr_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_mbar_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_mbar_instr_offset]), + .scout(sov[ex3_mbar_instr_offset]), + .din(ex3_mbar_instr_d), + .dout(ex3_mbar_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_mbar_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_mbar_instr_offset]), + .scout(sov[ex4_mbar_instr_offset]), + .din(ex4_mbar_instr_d), + .dout(ex4_mbar_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_makeitso_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_makeitso_instr_offset]), + .scout(sov[ex2_makeitso_instr_offset]), + .din(ex2_makeitso_instr_d), + .dout(ex2_makeitso_instr_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_makeitso_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_makeitso_instr_offset]), + .scout(sov[ex3_makeitso_instr_offset]), + .din(ex3_makeitso_instr_d), + .dout(ex3_makeitso_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_makeitso_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_makeitso_instr_offset]), + .scout(sov[ex4_makeitso_instr_offset]), + .din(ex4_makeitso_instr_d), + .dout(ex4_makeitso_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_dci_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_dci_instr_offset]), + .scout(sov[ex2_dci_instr_offset]), + .din(ex2_dci_instr_d), + .dout(ex2_dci_instr_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_dci_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_dci_instr_offset]), + .scout(sov[ex3_dci_instr_offset]), + .din(ex3_dci_instr_d), + .dout(ex3_dci_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_dci_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_dci_instr_offset]), + .scout(sov[ex4_dci_instr_offset]), + .din(ex4_dci_instr_d), + .dout(ex4_dci_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ici_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_ici_instr_offset]), + .scout(sov[ex2_ici_instr_offset]), + .din(ex2_ici_instr_d), + .dout(ex2_ici_instr_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_ici_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_ici_instr_offset]), + .scout(sov[ex3_ici_instr_offset]), + .din(ex3_ici_instr_d), + .dout(ex3_ici_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_ici_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_ici_instr_offset]), + .scout(sov[ex4_ici_instr_offset]), + .din(ex4_ici_instr_d), + .dout(ex4_ici_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_algebraic_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_instr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_algebraic_offset]), + .scout(sov[ex2_algebraic_offset]), + .din(ex2_algebraic_d), + .dout(ex2_algebraic_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_algebraic_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_algebraic_offset]), + .scout(sov[ex3_algebraic_offset]), + .din(ex3_algebraic_d), + .dout(ex3_algebraic_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_strg_index_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_instr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_strg_index_offset]), + .scout(sov[ex2_strg_index_offset]), + .din(ex2_strg_index_d), + .dout(ex2_strg_index_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_strg_index_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_strg_index_offset]), + .scout(sov[ex3_strg_index_offset]), + .din(ex3_strg_index_d), + .dout(ex3_strg_index_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_strg_index_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_strg_index_offset]), + .scout(sov[ex4_strg_index_offset]), + .din(ex4_strg_index_d), + .dout(ex4_strg_index_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_resv_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_instr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_resv_instr_offset]), + .scout(sov[ex2_resv_instr_offset]), + .din(ex2_resv_instr_d), + .dout(ex2_resv_instr_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_resv_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_resv_instr_offset]), + .scout(sov[ex3_resv_instr_offset]), + .din(ex3_resv_instr_d), + .dout(ex3_resv_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_resv_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_resv_instr_offset]), + .scout(sov[ex4_resv_instr_offset]), + .din(ex4_resv_instr_d), + .dout(ex4_resv_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_mutex_hint_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_instr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_mutex_hint_offset]), + .scout(sov[ex2_mutex_hint_offset]), + .din(ex2_mutex_hint_d), + .dout(ex2_mutex_hint_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_mutex_hint_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_mutex_hint_offset]), + .scout(sov[ex3_mutex_hint_offset]), + .din(ex3_mutex_hint_d), + .dout(ex3_mutex_hint_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_mutex_hint_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_mutex_hint_offset]), + .scout(sov[ex4_mutex_hint_offset]), + .din(ex4_mutex_hint_d), + .dout(ex4_mutex_hint_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_load_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_instr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_load_instr_offset]), + .scout(sov[ex2_load_instr_offset]), + .din(ex2_load_instr_d), + .dout(ex2_load_instr_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_load_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_load_instr_offset]), + .scout(sov[ex3_load_instr_offset]), + .din(ex3_load_instr_d), + .dout(ex3_load_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_load_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_load_instr_offset]), + .scout(sov[ex4_load_instr_offset]), + .din(ex4_load_instr_d), + .dout(ex4_load_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_store_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_instr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_store_instr_offset]), + .scout(sov[ex2_store_instr_offset]), + .din(ex2_store_instr_d), + .dout(ex2_store_instr_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_store_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_store_instr_offset]), + .scout(sov[ex3_store_instr_offset]), + .din(ex3_store_instr_d), + .dout(ex3_store_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_store_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_store_instr_offset]), + .scout(sov[ex4_store_instr_offset]), + .din(ex4_store_instr_d), + .dout(ex4_store_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_le_mode_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_le_mode_offset]), + .scout(sov[ex4_le_mode_offset]), + .din(ex4_le_mode_d), + .dout(ex4_le_mode_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_wimge_i_bits_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_wimge_i_bits_offset]), + .scout(sov[ex5_wimge_i_bits_offset]), + .din(ex5_wimge_i_bits_d), + .dout(ex5_wimge_i_bits_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_axu_op_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_instr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_axu_op_val_offset]), + .scout(sov[ex2_axu_op_val_offset]), + .din(ex2_axu_op_val_d), + .dout(ex2_axu_op_val_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_axu_op_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_axu_op_val_offset]), + .scout(sov[ex3_axu_op_val_offset]), + .din(ex3_axu_op_val_d), + .dout(ex3_axu_op_val_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_axu_op_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_axu_op_val_offset]), + .scout(sov[ex4_axu_op_val_offset]), + .din(ex4_axu_op_val_d), + .dout(ex4_axu_op_val_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_axu_op_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_axu_op_val_offset]), + .scout(sov[ex5_axu_op_val_offset]), + .din(ex5_axu_op_val_d), + .dout(ex5_axu_op_val_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_upd_form_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_instr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_upd_form_offset]), + .scout(sov[ex2_upd_form_offset]), + .din(ex2_upd_form_d), + .dout(ex2_upd_form_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_upd_form_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_upd_form_offset]), + .scout(sov[ex3_upd_form_offset]), + .din(ex3_upd_form_d), + .dout(ex3_upd_form_q) +); + +tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex2_axu_instr_type_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_instr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_axu_instr_type_offset:ex2_axu_instr_type_offset + 3 - 1]), + .scout(sov[ex2_axu_instr_type_offset:ex2_axu_instr_type_offset + 3 - 1]), + .din(ex2_axu_instr_type_d), + .dout(ex2_axu_instr_type_q) +); + +tri_regk #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex3_axu_instr_type_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_axu_instr_type_offset:ex3_axu_instr_type_offset + 3 - 1]), + .scout(sov[ex3_axu_instr_type_offset:ex3_axu_instr_type_offset + 3 - 1]), + .din(ex3_axu_instr_type_d), + .dout(ex3_axu_instr_type_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_load_hit_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_load_hit_offset]), + .scout(sov[ex5_load_hit_offset]), + .din(ex5_load_hit_d), + .dout(ex5_load_hit_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_load_hit_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_load_hit_offset]), + .scout(sov[ex6_load_hit_offset]), + .din(ex6_load_hit_d), + .dout(ex6_load_hit_q) +); + +tri_regk #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ex5_usr_bits_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_usr_bits_offset:ex5_usr_bits_offset + 4 - 1]), + .scout(sov[ex5_usr_bits_offset:ex5_usr_bits_offset + 4 - 1]), + .din(ex5_usr_bits_d), + .dout(ex5_usr_bits_q) +); + +tri_regk #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex5_classid_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_classid_offset:ex5_classid_offset + 2 - 1]), + .scout(sov[ex5_classid_offset:ex5_classid_offset + 2 - 1]), + .din(ex5_classid_d), + .dout(ex5_classid_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_derat_setHold_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_derat_setHold_offset]), + .scout(sov[ex5_derat_setHold_offset]), + .din(ex5_derat_setHold_d), + .dout(ex5_derat_setHold_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_axu_wren_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_axu_wren_offset]), + .scout(sov[ex5_axu_wren_offset]), + .din(ex5_axu_wren_d), + .dout(ex5_axu_wren_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_axu_wren_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_axu_wren_offset]), + .scout(sov[ex6_axu_wren_offset]), + .din(ex6_axu_wren_d), + .dout(ex6_axu_wren_q) +); + +tri_regk #(.WIDTH(AXU_TARGET_ENC), .INIT(0), .NEEDS_SRESET(1)) ex5_lq_ta_gpr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_lq_ta_gpr_offset:ex5_lq_ta_gpr_offset + AXU_TARGET_ENC - 1]), + .scout(sov[ex5_lq_ta_gpr_offset:ex5_lq_ta_gpr_offset + AXU_TARGET_ENC - 1]), + .din(ex5_lq_ta_gpr_d), + .dout(ex5_lq_ta_gpr_q) +); + +tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) ex6_lq_ta_gpr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_lq_ta_gpr_offset:ex6_lq_ta_gpr_offset + (`GPR_POOL_ENC+`THREADS_POOL_ENC) - 1]), + .scout(sov[ex6_lq_ta_gpr_offset:ex6_lq_ta_gpr_offset + (`GPR_POOL_ENC+`THREADS_POOL_ENC) - 1]), + .din(ex6_lq_ta_gpr_d), + .dout(ex6_lq_ta_gpr_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_load_le_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_load_le_offset]), + .scout(sov[ex5_load_le_offset]), + .din(ex5_load_le_d), + .dout(ex5_load_le_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_th_fld_c_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_instr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_th_fld_c_offset]), + .scout(sov[ex2_th_fld_c_offset]), + .din(ex2_th_fld_c_d), + .dout(ex2_th_fld_c_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_th_fld_c_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_th_fld_c_offset]), + .scout(sov[ex3_th_fld_c_offset]), + .din(ex3_th_fld_c_d), + .dout(ex3_th_fld_c_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_th_fld_c_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_th_fld_c_offset]), + .scout(sov[ex4_th_fld_c_offset]), + .din(ex4_th_fld_c_d), + .dout(ex4_th_fld_c_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_th_fld_l2_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_instr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_th_fld_l2_offset]), + .scout(sov[ex2_th_fld_l2_offset]), + .din(ex2_th_fld_l2_d), + .dout(ex2_th_fld_l2_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_th_fld_l2_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_th_fld_l2_offset]), + .scout(sov[ex3_th_fld_l2_offset]), + .din(ex3_th_fld_l2_d), + .dout(ex3_th_fld_l2_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_th_fld_l2_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_th_fld_l2_offset]), + .scout(sov[ex4_th_fld_l2_offset]), + .din(ex4_th_fld_l2_d), + .dout(ex4_th_fld_l2_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_dcbtls_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_instr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_dcbtls_instr_offset]), + .scout(sov[ex2_dcbtls_instr_offset]), + .din(ex2_dcbtls_instr_d), + .dout(ex2_dcbtls_instr_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_dcbtls_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_dcbtls_instr_offset]), + .scout(sov[ex3_dcbtls_instr_offset]), + .din(ex3_dcbtls_instr_d), + .dout(ex3_dcbtls_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_dcbtls_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_dcbtls_instr_offset]), + .scout(sov[ex4_dcbtls_instr_offset]), + .din(ex4_dcbtls_instr_d), + .dout(ex4_dcbtls_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_dcbtstls_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_instr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_dcbtstls_instr_offset]), + .scout(sov[ex2_dcbtstls_instr_offset]), + .din(ex2_dcbtstls_instr_d), + .dout(ex2_dcbtstls_instr_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_dcbtstls_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_dcbtstls_instr_offset]), + .scout(sov[ex3_dcbtstls_instr_offset]), + .din(ex3_dcbtstls_instr_d), + .dout(ex3_dcbtstls_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_dcbtstls_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_dcbtstls_instr_offset]), + .scout(sov[ex4_dcbtstls_instr_offset]), + .din(ex4_dcbtstls_instr_d), + .dout(ex4_dcbtstls_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_dcblc_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_instr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_dcblc_instr_offset]), + .scout(sov[ex2_dcblc_instr_offset]), + .din(ex2_dcblc_instr_d), + .dout(ex2_dcblc_instr_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_dcblc_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_dcblc_instr_offset]), + .scout(sov[ex3_dcblc_instr_offset]), + .din(ex3_dcblc_instr_d), + .dout(ex3_dcblc_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_dcblc_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_dcblc_instr_offset]), + .scout(sov[ex4_dcblc_instr_offset]), + .din(ex4_dcblc_instr_d), + .dout(ex4_dcblc_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_icblc_l2_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_instr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_icblc_l2_instr_offset]), + .scout(sov[ex2_icblc_l2_instr_offset]), + .din(ex2_icblc_l2_instr_d), + .dout(ex2_icblc_l2_instr_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_icblc_l2_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_icblc_l2_instr_offset]), + .scout(sov[ex3_icblc_l2_instr_offset]), + .din(ex3_icblc_l2_instr_d), + .dout(ex3_icblc_l2_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_icblc_l2_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_icblc_l2_instr_offset]), + .scout(sov[ex4_icblc_l2_instr_offset]), + .din(ex4_icblc_l2_instr_d), + .dout(ex4_icblc_l2_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_icbt_l2_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_instr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_icbt_l2_instr_offset]), + .scout(sov[ex2_icbt_l2_instr_offset]), + .din(ex2_icbt_l2_instr_d), + .dout(ex2_icbt_l2_instr_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_icbt_l2_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_icbt_l2_instr_offset]), + .scout(sov[ex3_icbt_l2_instr_offset]), + .din(ex3_icbt_l2_instr_d), + .dout(ex3_icbt_l2_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_icbt_l2_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_icbt_l2_instr_offset]), + .scout(sov[ex4_icbt_l2_instr_offset]), + .din(ex4_icbt_l2_instr_d), + .dout(ex4_icbt_l2_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_icbtls_l2_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_instr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_icbtls_l2_instr_offset]), + .scout(sov[ex2_icbtls_l2_instr_offset]), + .din(ex2_icbtls_l2_instr_d), + .dout(ex2_icbtls_l2_instr_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_icbtls_l2_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_icbtls_l2_instr_offset]), + .scout(sov[ex3_icbtls_l2_instr_offset]), + .din(ex3_icbtls_l2_instr_d), + .dout(ex3_icbtls_l2_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_icbtls_l2_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_icbtls_l2_instr_offset]), + .scout(sov[ex4_icbtls_l2_instr_offset]), + .din(ex4_icbtls_l2_instr_d), + .dout(ex4_icbtls_l2_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_tlbsync_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_tlbsync_instr_offset]), + .scout(sov[ex2_tlbsync_instr_offset]), + .din(ex2_tlbsync_instr_d), + .dout(ex2_tlbsync_instr_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_tlbsync_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_tlbsync_instr_offset]), + .scout(sov[ex3_tlbsync_instr_offset]), + .din(ex3_tlbsync_instr_d), + .dout(ex3_tlbsync_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_tlbsync_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_tlbsync_instr_offset]), + .scout(sov[ex4_tlbsync_instr_offset]), + .din(ex4_tlbsync_instr_d), + .dout(ex4_tlbsync_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ldst_falign_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_instr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_ldst_falign_offset]), + .scout(sov[ex2_ldst_falign_offset]), + .din(ex2_ldst_falign_d), + .dout(ex2_ldst_falign_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ldst_fexcpt_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_instr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_ldst_fexcpt_offset]), + .scout(sov[ex2_ldst_fexcpt_offset]), + .din(ex2_ldst_fexcpt_d), + .dout(ex2_ldst_fexcpt_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_ldst_fexcpt_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_ldst_fexcpt_offset]), + .scout(sov[ex3_ldst_fexcpt_offset]), + .din(ex3_ldst_fexcpt_d), + .dout(ex3_ldst_fexcpt_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_load_miss_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_load_miss_offset]), + .scout(sov[ex5_load_miss_offset]), + .din(ex5_load_miss_d), + .dout(ex5_load_miss_q) +); + +tri_ser_rlmreg_p #(.WIDTH((8+`THREADS+1)), .INIT(0), .NEEDS_SRESET(1)) xudbg1_dir_reg_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_darr_rd_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[xudbg1_dir_reg_offset:xudbg1_dir_reg_offset + (8+`THREADS+1) - 1]), + .scout(sov[xudbg1_dir_reg_offset:xudbg1_dir_reg_offset + (8+`THREADS+1) - 1]), + .din(xudbg1_dir_reg_d), + .dout(xudbg1_dir_reg_q) +); + +tri_ser_rlmreg_p #(.WIDTH(PARBITS), .INIT(0), .NEEDS_SRESET(1)) xudbg1_parity_reg_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_darr_rd_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[xudbg1_parity_reg_offset:xudbg1_parity_reg_offset + PARBITS - 1]), + .scout(sov[xudbg1_parity_reg_offset:xudbg1_parity_reg_offset + PARBITS - 1]), + .din(xudbg1_parity_reg_d), + .dout(xudbg1_parity_reg_q) +); + +tri_ser_rlmreg_p #(.WIDTH((63-(`DC_SIZE-3))-(64-`REAL_IFAR_WIDTH)+1), .INIT(0), .NEEDS_SRESET(1)) xudbg2_tag_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_darr_rd_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[xudbg2_tag_offset:xudbg2_tag_offset + (63-(`DC_SIZE-3))-(64-`REAL_IFAR_WIDTH)+1 - 1]), + .scout(sov[xudbg2_tag_offset:xudbg2_tag_offset + (63-(`DC_SIZE-3))-(64-`REAL_IFAR_WIDTH)+1 - 1]), + .din(xudbg2_tag_d), + .dout(xudbg2_tag_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_dcarr_wren_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq4_dcarr_wren_offset]), + .scout(sov[stq4_dcarr_wren_offset]), + .din(stq4_dcarr_wren_d), + .dout(stq4_dcarr_wren_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sgpr_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_sgpr_instr_offset]), + .scout(sov[ex2_sgpr_instr_offset]), + .din(ex2_sgpr_instr_d), + .dout(ex2_sgpr_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_saxu_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_saxu_instr_offset]), + .scout(sov[ex2_saxu_instr_offset]), + .din(ex2_saxu_instr_d), + .dout(ex2_saxu_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sdp_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_sdp_instr_offset]), + .scout(sov[ex2_sdp_instr_offset]), + .din(ex2_sdp_instr_d), + .dout(ex2_sdp_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_tgpr_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_tgpr_instr_offset]), + .scout(sov[ex2_tgpr_instr_offset]), + .din(ex2_tgpr_instr_d), + .dout(ex2_tgpr_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_taxu_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_taxu_instr_offset]), + .scout(sov[ex2_taxu_instr_offset]), + .din(ex2_taxu_instr_d), + .dout(ex2_taxu_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_tdp_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_tdp_instr_offset]), + .scout(sov[ex2_tdp_instr_offset]), + .din(ex2_tdp_instr_d), + .dout(ex2_tdp_instr_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_sgpr_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_sgpr_instr_offset]), + .scout(sov[ex3_sgpr_instr_offset]), + .din(ex3_sgpr_instr_d), + .dout(ex3_sgpr_instr_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_saxu_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_saxu_instr_offset]), + .scout(sov[ex3_saxu_instr_offset]), + .din(ex3_saxu_instr_d), + .dout(ex3_saxu_instr_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_sdp_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_sdp_instr_offset]), + .scout(sov[ex3_sdp_instr_offset]), + .din(ex3_sdp_instr_d), + .dout(ex3_sdp_instr_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_tgpr_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_tgpr_instr_offset]), + .scout(sov[ex3_tgpr_instr_offset]), + .din(ex3_tgpr_instr_d), + .dout(ex3_tgpr_instr_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_taxu_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_taxu_instr_offset]), + .scout(sov[ex3_taxu_instr_offset]), + .din(ex3_taxu_instr_d), + .dout(ex3_taxu_instr_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_tdp_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_tdp_instr_offset]), + .scout(sov[ex3_tdp_instr_offset]), + .din(ex3_tdp_instr_d), + .dout(ex3_tdp_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_sgpr_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_sgpr_instr_offset]), + .scout(sov[ex4_sgpr_instr_offset]), + .din(ex4_sgpr_instr_d), + .dout(ex4_sgpr_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_saxu_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_saxu_instr_offset]), + .scout(sov[ex4_saxu_instr_offset]), + .din(ex4_saxu_instr_d), + .dout(ex4_saxu_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_sdp_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_sdp_instr_offset]), + .scout(sov[ex4_sdp_instr_offset]), + .din(ex4_sdp_instr_d), + .dout(ex4_sdp_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_tgpr_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_tgpr_instr_offset]), + .scout(sov[ex4_tgpr_instr_offset]), + .din(ex4_tgpr_instr_d), + .dout(ex4_tgpr_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_taxu_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_taxu_instr_offset]), + .scout(sov[ex4_taxu_instr_offset]), + .din(ex4_taxu_instr_d), + .dout(ex4_taxu_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_tdp_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_tdp_instr_offset]), + .scout(sov[ex4_tdp_instr_offset]), + .din(ex4_tdp_instr_d), + .dout(ex4_tdp_instr_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_mftgpr_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_mftgpr_val_offset]), + .scout(sov[ex5_mftgpr_val_offset]), + .din(ex5_mftgpr_val_d), + .dout(ex5_mftgpr_val_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_moveOp_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_moveOp_val_offset]), + .scout(sov[ex4_moveOp_val_offset]), + .din(ex4_moveOp_val_d), + .dout(ex4_moveOp_val_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq6_moveOp_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq6_moveOp_val_offset]), + .scout(sov[stq6_moveOp_val_offset]), + .din(stq6_moveOp_val_d), + .dout(stq6_moveOp_val_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_undef_touch_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_undef_touch_offset]), + .scout(sov[ex3_undef_touch_offset]), + .din(ex3_undef_touch_d), + .dout(ex3_undef_touch_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_undef_touch_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_undef_touch_offset]), + .scout(sov[ex4_undef_touch_offset]), + .din(ex4_undef_touch_d), + .dout(ex4_undef_touch_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_blkable_touch_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_blkable_touch_offset]), + .scout(sov[ex4_blkable_touch_offset]), + .din(ex4_blkable_touch_d), + .dout(ex4_blkable_touch_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_blk_touch_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_blk_touch_offset]), + .scout(sov[ex5_blk_touch_offset]), + .din(ex5_blk_touch_d), + .dout(ex5_blk_touch_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_blk_touch_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_blk_touch_offset]), + .scout(sov[ex6_blk_touch_offset]), + .din(ex6_blk_touch_d), + .dout(ex6_blk_touch_q) +); + +tri_regk #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) ex3_eff_addr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_binv2_stg_act), + .force_t(func_slp_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_eff_addr_offset:ex3_eff_addr_offset + (2**`GPR_WIDTH_ENC) - 1]), + .scout(sov[ex3_eff_addr_offset:ex3_eff_addr_offset + (2**`GPR_WIDTH_ENC) - 1]), + .din(ex3_eff_addr_d), + .dout(ex3_eff_addr_q) +); + +tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) ex4_eff_addr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_binv3_stg_act), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_eff_addr_offset:ex4_eff_addr_offset + (2**`GPR_WIDTH_ENC) - 1]), + .scout(sov[ex4_eff_addr_offset:ex4_eff_addr_offset + (2**`GPR_WIDTH_ENC) - 1]), + .din(ex4_eff_addr_d), + .dout(ex4_eff_addr_q) +); + +tri_regk #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) ex5_eff_addr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_eff_addr_offset:ex5_eff_addr_offset + (2**`GPR_WIDTH_ENC) - 1]), + .scout(sov[ex5_eff_addr_offset:ex5_eff_addr_offset + (2**`GPR_WIDTH_ENC) - 1]), + .din(ex5_eff_addr_d), + .dout(ex5_eff_addr_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_undef_lockset_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_undef_lockset_offset]), + .scout(sov[ex3_undef_lockset_offset]), + .din(ex3_undef_lockset_d), + .dout(ex3_undef_lockset_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_undef_lockset_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_undef_lockset_offset]), + .scout(sov[ex4_undef_lockset_offset]), + .din(ex4_undef_lockset_d), + .dout(ex4_undef_lockset_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_unable_2lock_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_unable_2lock_offset]), + .scout(sov[ex5_unable_2lock_offset]), + .din(ex5_unable_2lock_d), + .dout(ex5_unable_2lock_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_stq5_unable_2lock_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_stq5_unable_2lock_offset]), + .scout(sov[ex6_stq5_unable_2lock_offset]), + .din(ex6_stq5_unable_2lock_d), + .dout(ex6_stq5_unable_2lock_q) +); + +tri_regk #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ex5_dacrw_cmpr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_dacrw_cmpr_offset:ex5_dacrw_cmpr_offset + 4 - 1]), + .scout(sov[ex5_dacrw_cmpr_offset:ex5_dacrw_cmpr_offset + 4 - 1]), + .din(ex5_dacrw_cmpr_d), + .dout(ex5_dacrw_cmpr_q) +); + +tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ex6_dacrw_cmpr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_dacrw_cmpr_offset:ex6_dacrw_cmpr_offset + 4 - 1]), + .scout(sov[ex6_dacrw_cmpr_offset:ex6_dacrw_cmpr_offset + 4 - 1]), + .din(ex6_dacrw_cmpr_d), + .dout(ex6_dacrw_cmpr_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_stq_val_req_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_stq_val_req_offset]), + .scout(sov[ex3_stq_val_req_offset]), + .din(ex3_stq_val_req_d), + .dout(ex3_stq_val_req_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_stq_val_req_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_stq_val_req_offset]), + .scout(sov[ex4_stq_val_req_offset]), + .din(ex4_stq_val_req_d), + .dout(ex4_stq_val_req_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_load_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_load_instr_offset]), + .scout(sov[ex5_load_instr_offset]), + .din(ex5_load_instr_d), + .dout(ex5_load_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_mword_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_instr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_mword_instr_offset]), + .scout(sov[ex2_mword_instr_offset]), + .din(ex2_mword_instr_d), + .dout(ex2_mword_instr_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_mword_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_mword_instr_offset]), + .scout(sov[ex3_mword_instr_offset]), + .din(ex3_mword_instr_d), + .dout(ex3_mword_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_store_miss_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq4_store_miss_offset]), + .scout(sov[stq4_store_miss_offset]), + .din(stq4_store_miss_d), + .dout(stq4_store_miss_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_perf_dcbt_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_perf_dcbt_offset]), + .scout(sov[ex5_perf_dcbt_offset]), + .din(ex5_perf_dcbt_d), + .dout(ex5_perf_dcbt_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_ccr2_ap_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_ccr2_ap_offset]), + .scout(sov[spr_ccr2_ap_offset]), + .din(spr_ccr2_ap_d), + .dout(spr_ccr2_ap_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_ccr2_en_trace_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_ccr2_en_trace_offset]), + .scout(sov[spr_ccr2_en_trace_offset]), + .din(spr_ccr2_en_trace_d), + .dout(spr_ccr2_en_trace_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_ccr2_ucode_dis_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_ccr2_ucode_dis_offset]), + .scout(sov[spr_ccr2_ucode_dis_offset]), + .din(spr_ccr2_ucode_dis_d), + .dout(spr_ccr2_ucode_dis_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_ccr2_notlb_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_ccr2_notlb_offset]), + .scout(sov[spr_ccr2_notlb_offset]), + .din(spr_ccr2_notlb_d), + .dout(spr_ccr2_notlb_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) clkg_ctl_override_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[clkg_ctl_override_offset]), + .scout(sov[clkg_ctl_override_offset]), + .din(clkg_ctl_override_d), + .dout(clkg_ctl_override_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr0_wlk_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_xucr0_wlk_offset]), + .scout(sov[spr_xucr0_wlk_offset]), + .din(spr_xucr0_wlk_d), + .dout(spr_xucr0_wlk_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr0_mbar_ack_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_xucr0_mbar_ack_offset]), + .scout(sov[spr_xucr0_mbar_ack_offset]), + .din(spr_xucr0_mbar_ack_d), + .dout(spr_xucr0_mbar_ack_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr0_tlbsync_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_xucr0_tlbsync_offset]), + .scout(sov[spr_xucr0_tlbsync_offset]), + .din(spr_xucr0_tlbsync_d), + .dout(spr_xucr0_tlbsync_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr0_dcdis_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_xucr0_dcdis_offset]), + .scout(sov[spr_xucr0_dcdis_offset]), + .din(spr_xucr0_dcdis_d), + .dout(spr_xucr0_dcdis_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr0_aflsta_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_xucr0_aflsta_offset]), + .scout(sov[spr_xucr0_aflsta_offset]), + .din(spr_xucr0_aflsta_d), + .dout(spr_xucr0_aflsta_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr0_flsta_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_xucr0_flsta_offset]), + .scout(sov[spr_xucr0_flsta_offset]), + .din(spr_xucr0_flsta_d), + .dout(spr_xucr0_flsta_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr0_mddp_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_xucr0_mddp_offset]), + .scout(sov[spr_xucr0_mddp_offset]), + .din(spr_xucr0_mddp_d), + .dout(spr_xucr0_mddp_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr0_mdcp_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_xucr0_mdcp_offset]), + .scout(sov[spr_xucr0_mdcp_offset]), + .din(spr_xucr0_mdcp_d), + .dout(spr_xucr0_mdcp_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr4_mmu_mchk_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_xucr4_mmu_mchk_offset]), + .scout(sov[spr_xucr4_mmu_mchk_offset]), + .din(spr_xucr4_mmu_mchk_d), + .dout(spr_xucr4_mmu_mchk_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr4_mddmh_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_xucr4_mddmh_offset]), + .scout(sov[spr_xucr4_mddmh_offset]), + .din(spr_xucr4_mddmh_d), + .dout(spr_xucr4_mddmh_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_xucr0_en_trace_um_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_xucr0_en_trace_um_offset:spr_xucr0_en_trace_um_offset + `THREADS - 1]), + .scout(sov[spr_xucr0_en_trace_um_offset:spr_xucr0_en_trace_um_offset + `THREADS - 1]), + .din(spr_xucr0_en_trace_um_d), + .dout(spr_xucr0_en_trace_um_q) +); + +tri_regk #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex1_lsu_64bit_mode_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_lsu_64bit_mode_offset:ex1_lsu_64bit_mode_offset + `THREADS - 1]), + .scout(sov[ex1_lsu_64bit_mode_offset:ex1_lsu_64bit_mode_offset + `THREADS - 1]), + .din(ex1_lsu_64bit_mode_d), + .dout(ex1_lsu_64bit_mode_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_lsu_64bit_agen_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_lsu_64bit_agen_offset]), + .scout(sov[ex2_lsu_64bit_agen_offset]), + .din(ex2_lsu_64bit_agen_d), + .dout(ex2_lsu_64bit_agen_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_lsu_64bit_agen_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_lsu_64bit_agen_offset]), + .scout(sov[ex3_lsu_64bit_agen_offset]), + .din(ex3_lsu_64bit_agen_d), + .dout(ex3_lsu_64bit_agen_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_lsu_64bit_agen_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_lsu_64bit_agen_offset]), + .scout(sov[ex4_lsu_64bit_agen_offset]), + .din(ex4_lsu_64bit_agen_d), + .dout(ex4_lsu_64bit_agen_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_local_dcbf_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_local_dcbf_offset]), + .scout(sov[ex4_local_dcbf_offset]), + .din(ex4_local_dcbf_d), + .dout(ex4_local_dcbf_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_msgsnd_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_msgsnd_instr_offset]), + .scout(sov[ex2_msgsnd_instr_offset]), + .din(ex2_msgsnd_instr_d), + .dout(ex2_msgsnd_instr_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_msgsnd_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_msgsnd_instr_offset]), + .scout(sov[ex3_msgsnd_instr_offset]), + .din(ex3_msgsnd_instr_d), + .dout(ex3_msgsnd_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_msgsnd_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_msgsnd_instr_offset]), + .scout(sov[ex4_msgsnd_instr_offset]), + .din(ex4_msgsnd_instr_d), + .dout(ex4_msgsnd_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_load_type_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_load_type_offset]), + .scout(sov[ex4_load_type_offset]), + .din(ex4_load_type_d), + .dout(ex4_load_type_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_gath_load_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_gath_load_offset]), + .scout(sov[ex4_gath_load_offset]), + .din(ex4_gath_load_d), + .dout(ex4_gath_load_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_l2load_type_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_l2load_type_offset]), + .scout(sov[ex4_l2load_type_offset]), + .din(ex4_l2load_type_d), + .dout(ex4_l2load_type_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_lq_wren_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_lq_wren_offset]), + .scout(sov[ex5_lq_wren_offset]), + .din(ex5_lq_wren_d), + .dout(ex5_lq_wren_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_lq_wren_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_lq_wren_offset]), + .scout(sov[ex6_lq_wren_offset]), + .din(ex6_lq_wren_d), + .dout(ex6_lq_wren_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ldawx_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_instr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_ldawx_instr_offset]), + .scout(sov[ex2_ldawx_instr_offset]), + .din(ex2_ldawx_instr_d), + .dout(ex2_ldawx_instr_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_ldawx_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_ldawx_instr_offset]), + .scout(sov[ex3_ldawx_instr_offset]), + .din(ex3_ldawx_instr_d), + .dout(ex3_ldawx_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_ldawx_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_ldawx_instr_offset]), + .scout(sov[ex4_ldawx_instr_offset]), + .din(ex4_ldawx_instr_d), + .dout(ex4_ldawx_instr_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_ldawx_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_ldawx_instr_offset]), + .scout(sov[ex5_ldawx_instr_offset]), + .din(ex5_ldawx_instr_d), + .dout(ex5_ldawx_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_wclr_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_instr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_wclr_instr_offset]), + .scout(sov[ex2_wclr_instr_offset]), + .din(ex2_wclr_instr_d), + .dout(ex2_wclr_instr_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_wclr_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_wclr_instr_offset]), + .scout(sov[ex3_wclr_instr_offset]), + .din(ex3_wclr_instr_d), + .dout(ex3_wclr_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_wclr_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_wclr_instr_offset]), + .scout(sov[ex4_wclr_instr_offset]), + .din(ex4_wclr_instr_d), + .dout(ex4_wclr_instr_q) +); + +tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex4_opsize_enc_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_opsize_enc_offset:ex4_opsize_enc_offset + 3 - 1]), + .scout(sov[ex4_opsize_enc_offset:ex4_opsize_enc_offset + 3 - 1]), + .din(ex4_opsize_enc_d), + .dout(ex4_opsize_enc_q) +); + +tri_regk #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex5_opsize_enc_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_opsize_enc_offset:ex5_opsize_enc_offset + 3 - 1]), + .scout(sov[ex5_opsize_enc_offset:ex5_opsize_enc_offset + 3 - 1]), + .din(ex5_opsize_enc_d), + .dout(ex5_opsize_enc_q) +); + +tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex2_itag_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_instr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_itag_offset:ex2_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[ex2_itag_offset:ex2_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(ex2_itag_d), + .dout(ex2_itag_q) +); + +tri_regk #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex3_itag_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_itag_offset:ex3_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[ex3_itag_offset:ex3_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(ex3_itag_d), + .dout(ex3_itag_q) +); + +tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex4_itag_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_itag_offset:ex4_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[ex4_itag_offset:ex4_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(ex4_itag_d), + .dout(ex4_itag_q) +); + +tri_regk #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex5_itag_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_itag_offset:ex5_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[ex5_itag_offset:ex5_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(ex5_itag_d), + .dout(ex5_itag_q) +); + +tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex6_itag_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_itag_offset:ex6_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[ex6_itag_offset:ex6_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(ex6_itag_d), + .dout(ex6_itag_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_drop_rel_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_drop_rel_offset]), + .scout(sov[ex5_drop_rel_offset]), + .din(ex5_drop_rel_d), + .dout(ex5_drop_rel_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_icswx_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_instr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_icswx_instr_offset]), + .scout(sov[ex2_icswx_instr_offset]), + .din(ex2_icswx_instr_d), + .dout(ex2_icswx_instr_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_icswx_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_icswx_instr_offset]), + .scout(sov[ex3_icswx_instr_offset]), + .din(ex3_icswx_instr_d), + .dout(ex3_icswx_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_icswx_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_icswx_instr_offset]), + .scout(sov[ex4_icswx_instr_offset]), + .din(ex4_icswx_instr_d), + .dout(ex4_icswx_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_icswxdot_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_instr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_icswxdot_instr_offset]), + .scout(sov[ex2_icswxdot_instr_offset]), + .din(ex2_icswxdot_instr_d), + .dout(ex2_icswxdot_instr_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_icswxdot_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_icswxdot_instr_offset]), + .scout(sov[ex3_icswxdot_instr_offset]), + .din(ex3_icswxdot_instr_d), + .dout(ex3_icswxdot_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_icswxdot_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_icswxdot_instr_offset]), + .scout(sov[ex4_icswxdot_instr_offset]), + .din(ex4_icswxdot_instr_d), + .dout(ex4_icswxdot_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_icswx_epid_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_instr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_icswx_epid_offset]), + .scout(sov[ex2_icswx_epid_offset]), + .din(ex2_icswx_epid_d), + .dout(ex2_icswx_epid_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_icswx_epid_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_icswx_epid_offset]), + .scout(sov[ex3_icswx_epid_offset]), + .din(ex3_icswx_epid_d), + .dout(ex3_icswx_epid_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_icswx_epid_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_icswx_epid_offset]), + .scout(sov[ex4_icswx_epid_offset]), + .din(ex4_icswx_epid_d), + .dout(ex4_icswx_epid_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_icswx_epid_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_icswx_epid_offset]), + .scout(sov[ex5_icswx_epid_offset]), + .din(ex5_icswx_epid_d), + .dout(ex5_icswx_epid_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_c_inh_drop_op_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_c_inh_drop_op_offset]), + .scout(sov[ex4_c_inh_drop_op_offset]), + .din(ex4_c_inh_drop_op_d), + .dout(ex4_c_inh_drop_op_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel2_axu_wren_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rel2_axu_wren_offset]), + .scout(sov[rel2_axu_wren_offset]), + .din(rel2_axu_wren_d), + .dout(rel2_axu_wren_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_axu_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq1_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq2_axu_val_offset]), + .scout(sov[stq2_axu_val_offset]), + .din(stq2_axu_val_d), + .dout(stq2_axu_val_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stq3_axu_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[stq3_axu_val_offset]), + .scout(sov[stq3_axu_val_offset]), + .din(stq3_axu_val_d), + .dout(stq3_axu_val_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_axu_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq4_axu_val_offset]), + .scout(sov[stq4_axu_val_offset]), + .din(stq4_axu_val_d), + .dout(stq4_axu_val_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_store_hit_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq4_store_hit_offset]), + .scout(sov[stq4_store_hit_offset]), + .din(stq4_store_hit_d), + .dout(stq4_store_hit_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq5_store_hit_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq5_store_hit_offset]), + .scout(sov[stq5_store_hit_offset]), + .din(stq5_store_hit_d), + .dout(stq5_store_hit_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq6_store_hit_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq6_store_hit_offset]), + .scout(sov[stq6_store_hit_offset]), + .din(stq6_store_hit_d), + .dout(stq6_store_hit_q) +); + +tri_rlmreg_p #(.WIDTH(AXU_TARGET_ENC), .INIT(0), .NEEDS_SRESET(1)) rel2_ta_gpr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq1_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rel2_ta_gpr_offset:rel2_ta_gpr_offset + AXU_TARGET_ENC - 1]), + .scout(sov[rel2_ta_gpr_offset:rel2_ta_gpr_offset + AXU_TARGET_ENC - 1]), + .din(rel2_ta_gpr_d), + .dout(rel2_ta_gpr_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) rv1_binv_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_slp_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[rv1_binv_val_offset]), + .scout(sov[rv1_binv_val_offset]), + .din(rv1_binv_val_d), + .dout(rv1_binv_val_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_binv_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_binv_val_offset]), + .scout(sov[ex0_binv_val_offset]), + .din(ex0_binv_val_d), + .dout(ex0_binv_val_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex1_binv_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_slp_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_binv_val_offset]), + .scout(sov[ex1_binv_val_offset]), + .din(ex1_binv_val_d), + .dout(ex1_binv_val_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_binv_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_binv_val_offset]), + .scout(sov[ex2_binv_val_offset]), + .din(ex2_binv_val_d), + .dout(ex2_binv_val_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_binv_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_slp_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_binv_val_offset]), + .scout(sov[ex3_binv_val_offset]), + .din(ex3_binv_val_d), + .dout(ex3_binv_val_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_binv_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_binv_val_offset]), + .scout(sov[ex4_binv_val_offset]), + .din(ex4_binv_val_d), + .dout(ex4_binv_val_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_derat_snoop_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_derat_snoop_val_offset]), + .scout(sov[ex0_derat_snoop_val_offset]), + .din(ex0_derat_snoop_val_d), + .dout(ex0_derat_snoop_val_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex1_derat_snoop_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_derat_snoop_val_offset]), + .scout(sov[ex1_derat_snoop_val_offset]), + .din(ex1_derat_snoop_val_d), + .dout(ex1_derat_snoop_val_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_msr_fp_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_msr_fp_offset:spr_msr_fp_offset + `THREADS - 1]), + .scout(sov[spr_msr_fp_offset:spr_msr_fp_offset + `THREADS - 1]), + .din(spr_msr_fp_d), + .dout(spr_msr_fp_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_msr_spv_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_msr_spv_offset:spr_msr_spv_offset + `THREADS - 1]), + .scout(sov[spr_msr_spv_offset:spr_msr_spv_offset + `THREADS - 1]), + .din(spr_msr_spv_d), + .dout(spr_msr_spv_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_msr_gs_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_msr_gs_offset:spr_msr_gs_offset + `THREADS - 1]), + .scout(sov[spr_msr_gs_offset:spr_msr_gs_offset + `THREADS - 1]), + .din(spr_msr_gs_d), + .dout(spr_msr_gs_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_msr_pr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_msr_pr_offset:spr_msr_pr_offset + `THREADS - 1]), + .scout(sov[spr_msr_pr_offset:spr_msr_pr_offset + `THREADS - 1]), + .din(spr_msr_pr_d), + .dout(spr_msr_pr_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_msr_ds_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_msr_ds_offset:spr_msr_ds_offset + `THREADS - 1]), + .scout(sov[spr_msr_ds_offset:spr_msr_ds_offset + `THREADS - 1]), + .din(spr_msr_ds_d), + .dout(spr_msr_ds_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_msr_de_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_msr_de_offset:spr_msr_de_offset + `THREADS - 1]), + .scout(sov[spr_msr_de_offset:spr_msr_de_offset + `THREADS - 1]), + .din(spr_msr_de_d), + .dout(spr_msr_de_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_dbcr0_idm_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_dbcr0_idm_offset:spr_dbcr0_idm_offset + `THREADS - 1]), + .scout(sov[spr_dbcr0_idm_offset:spr_dbcr0_idm_offset + `THREADS - 1]), + .din(spr_dbcr0_idm_d), + .dout(spr_dbcr0_idm_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_epcr_duvd_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_epcr_duvd_offset:spr_epcr_duvd_offset + `THREADS - 1]), + .scout(sov[spr_epcr_duvd_offset:spr_epcr_duvd_offset + `THREADS - 1]), + .din(spr_epcr_duvd_d), + .dout(spr_epcr_duvd_q) +); + +tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) spr_lpidr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_lpidr_offset:spr_lpidr_offset + 8 - 1]), + .scout(sov[spr_lpidr_offset:spr_lpidr_offset + 8 - 1]), + .din(spr_lpidr_d), + .dout(spr_lpidr_q) +); + +generate begin : spr_pid_reg + genvar tid; + for (tid=0; tid<`THREADS; tid=tid+1) begin : spr_pid_reg + tri_ser_rlmreg_p #(.WIDTH(14), .INIT(0), .NEEDS_SRESET(1)) spr_pid_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_pid_offset + 14 * tid:spr_pid_offset + 14 * (tid + 1) - 1]), + .scout(sov[spr_pid_offset + 14 * tid:spr_pid_offset + 14 * (tid + 1) - 1]), + .din(spr_pid_d[tid]), + .dout(spr_pid_q[tid]) + ); + end + end +endgenerate + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_icswx_gs_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_icswx_gs_offset]), + .scout(sov[ex3_icswx_gs_offset]), + .din(ex3_icswx_gs_d), + .dout(ex3_icswx_gs_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_icswx_pr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_icswx_pr_offset]), + .scout(sov[ex3_icswx_pr_offset]), + .din(ex3_icswx_pr_d), + .dout(ex3_icswx_pr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_icswx_ct_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_icswx_ct_val_offset]), + .scout(sov[ex4_icswx_ct_val_offset]), + .din(ex4_icswx_ct_val_d), + .dout(ex4_icswx_ct_val_q) +); + +tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex4_icswx_ct_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_icswx_ct_offset:ex4_icswx_ct_offset + 2 - 1]), + .scout(sov[ex4_icswx_ct_offset:ex4_icswx_ct_offset + 2 - 1]), + .din(ex4_icswx_ct_d), + .dout(ex4_icswx_ct_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) dbg_int_en_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[dbg_int_en_offset:dbg_int_en_offset + `THREADS - 1]), + .scout(sov[dbg_int_en_offset:dbg_int_en_offset + `THREADS - 1]), + .din(dbg_int_en_d), + .dout(dbg_int_en_q) +); + +tri_regk #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) ex5_ttype_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_ttype_offset:ex5_ttype_offset + 6 - 1]), + .scout(sov[ex5_ttype_offset:ex5_ttype_offset + 6 - 1]), + .din(ex5_ttype_d), + .dout(ex5_ttype_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_wNComp_rcvd_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_wNComp_rcvd_offset]), + .scout(sov[ex4_wNComp_rcvd_offset]), + .din(ex4_wNComp_rcvd_d), + .dout(ex4_wNComp_rcvd_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_wNComp_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_wNComp_offset]), + .scout(sov[ex4_wNComp_offset]), + .din(ex4_wNComp_d), + .dout(ex4_wNComp_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_wNComp_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_wNComp_offset]), + .scout(sov[ex5_wNComp_offset]), + .din(ex5_wNComp_d), + .dout(ex5_wNComp_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_wNComp_cr_upd_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_wNComp_cr_upd_offset]), + .scout(sov[ex5_wNComp_cr_upd_offset]), + .din(ex5_wNComp_cr_upd_d), + .dout(ex5_wNComp_cr_upd_q) +); + +tri_regk #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex5_dvc_en_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_dvc_en_offset:ex5_dvc_en_offset + 2 - 1]), + .scout(sov[ex5_dvc_en_offset:ex5_dvc_en_offset + 2 - 1]), + .din(ex5_dvc_en_d), + .dout(ex5_dvc_en_q) +); + +tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex6_dvc_en_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_dvc_en_offset:ex6_dvc_en_offset + 2 - 1]), + .scout(sov[ex6_dvc_en_offset:ex6_dvc_en_offset + 2 - 1]), + .din(ex6_dvc_en_d), + .dout(ex6_dvc_en_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_is_inval_op_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_is_inval_op_offset]), + .scout(sov[ex4_is_inval_op_offset]), + .din(ex4_is_inval_op_d), + .dout(ex4_is_inval_op_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_l1_lock_set_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_l1_lock_set_offset]), + .scout(sov[ex4_l1_lock_set_offset]), + .din(ex4_l1_lock_set_d), + .dout(ex4_l1_lock_set_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_l1_lock_set_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_l1_lock_set_offset]), + .scout(sov[ex5_l1_lock_set_offset]), + .din(ex5_l1_lock_set_d), + .dout(ex5_l1_lock_set_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_lock_clr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_lock_clr_offset]), + .scout(sov[ex4_lock_clr_offset]), + .din(ex4_lock_clr_d), + .dout(ex4_lock_clr_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_lock_clr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_lock_clr_offset]), + .scout(sov[ex5_lock_clr_offset]), + .din(ex5_lock_clr_d), + .dout(ex5_lock_clr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sfx_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_sfx_val_offset]), + .scout(sov[ex2_sfx_val_offset]), + .din(ex2_sfx_val_d), + .dout(ex2_sfx_val_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_sfx_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_sfx_val_offset]), + .scout(sov[ex3_sfx_val_offset]), + .din(ex3_sfx_val_d), + .dout(ex3_sfx_val_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_sfx_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_sfx_val_offset]), + .scout(sov[ex4_sfx_val_offset]), + .din(ex4_sfx_val_d), + .dout(ex4_sfx_val_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ucode_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_ucode_val_offset]), + .scout(sov[ex2_ucode_val_offset]), + .din(ex2_ucode_val_d), + .dout(ex2_ucode_val_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_ucode_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_ucode_val_offset]), + .scout(sov[ex3_ucode_val_offset]), + .din(ex3_ucode_val_d), + .dout(ex3_ucode_val_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_ucode_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_ucode_val_offset]), + .scout(sov[ex4_ucode_val_offset]), + .din(ex4_ucode_val_d), + .dout(ex4_ucode_val_q) +); + +tri_rlmreg_p #(.WIDTH(`UCODE_ENTRIES_ENC), .INIT(0), .NEEDS_SRESET(1)) ex2_ucode_cnt_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_instr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_ucode_cnt_offset:ex2_ucode_cnt_offset + `UCODE_ENTRIES_ENC - 1]), + .scout(sov[ex2_ucode_cnt_offset:ex2_ucode_cnt_offset + `UCODE_ENTRIES_ENC - 1]), + .din(ex2_ucode_cnt_d), + .dout(ex2_ucode_cnt_q) +); + +tri_regk #(.WIDTH(`UCODE_ENTRIES_ENC), .INIT(0), .NEEDS_SRESET(1)) ex3_ucode_cnt_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_ucode_cnt_offset:ex3_ucode_cnt_offset + `UCODE_ENTRIES_ENC - 1]), + .scout(sov[ex3_ucode_cnt_offset:ex3_ucode_cnt_offset + `UCODE_ENTRIES_ENC - 1]), + .din(ex3_ucode_cnt_d), + .dout(ex3_ucode_cnt_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ucode_op_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_instr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_ucode_op_offset]), + .scout(sov[ex2_ucode_op_offset]), + .din(ex2_ucode_op_d), + .dout(ex2_ucode_op_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_ucode_op_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_ucode_op_offset]), + .scout(sov[ex3_ucode_op_offset]), + .din(ex3_ucode_op_d), + .dout(ex3_ucode_op_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_ucode_op_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_ucode_op_offset]), + .scout(sov[ex4_ucode_op_offset]), + .din(ex4_ucode_op_d), + .dout(ex4_ucode_op_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_lq_comp_rpt_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_lq_comp_rpt_offset]), + .scout(sov[ex6_lq_comp_rpt_offset]), + .din(ex6_lq_comp_rpt_d), + .dout(ex6_lq_comp_rpt_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) lq0_iu_execute_vld_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lq0_iu_execute_vld_offset:lq0_iu_execute_vld_offset + `THREADS - 1]), + .scout(sov[lq0_iu_execute_vld_offset:lq0_iu_execute_vld_offset + `THREADS - 1]), + .din(lq0_iu_execute_vld_d), + .dout(lq0_iu_execute_vld_q) +); + +tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) lq0_iu_itag_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lq0_iu_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lq0_iu_itag_offset:lq0_iu_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[lq0_iu_itag_offset:lq0_iu_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(lq0_iu_itag_d), + .dout(lq0_iu_itag_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq0_iu_flush2ucode_type_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lq0_iu_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lq0_iu_flush2ucode_type_offset]), + .scout(sov[lq0_iu_flush2ucode_type_offset]), + .din(lq0_iu_flush2ucode_type_d), + .dout(lq0_iu_flush2ucode_type_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) lq0_iu_recirc_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lq0_iu_recirc_val_offset:lq0_iu_recirc_val_offset + `THREADS - 1]), + .scout(sov[lq0_iu_recirc_val_offset:lq0_iu_recirc_val_offset + `THREADS - 1]), + .din(lq0_iu_recirc_val_d), + .dout(lq0_iu_recirc_val_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq0_iu_flush2ucode_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lq0_iu_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lq0_iu_flush2ucode_offset]), + .scout(sov[lq0_iu_flush2ucode_offset]), + .din(lq0_iu_flush2ucode_d), + .dout(lq0_iu_flush2ucode_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) lq0_iu_dear_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lq0_iu_dear_val_offset:lq0_iu_dear_val_offset + `THREADS - 1]), + .scout(sov[lq0_iu_dear_val_offset:lq0_iu_dear_val_offset + `THREADS - 1]), + .din(lq0_iu_dear_val_d), + .dout(lq0_iu_dear_val_q) +); + +tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) lq0_iu_eff_addr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lq0_iu_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lq0_iu_eff_addr_offset:lq0_iu_eff_addr_offset + (2**`GPR_WIDTH_ENC) - 1]), + .scout(sov[lq0_iu_eff_addr_offset:lq0_iu_eff_addr_offset + (2**`GPR_WIDTH_ENC) - 1]), + .din(lq0_iu_eff_addr_d), + .dout(lq0_iu_eff_addr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq0_iu_n_flush_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lq0_iu_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lq0_iu_n_flush_offset]), + .scout(sov[lq0_iu_n_flush_offset]), + .din(lq0_iu_n_flush_d), + .dout(lq0_iu_n_flush_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq0_iu_np1_flush_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lq0_iu_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lq0_iu_np1_flush_offset]), + .scout(sov[lq0_iu_np1_flush_offset]), + .din(lq0_iu_np1_flush_d), + .dout(lq0_iu_np1_flush_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq0_iu_exception_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lq0_iu_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lq0_iu_exception_val_offset]), + .scout(sov[lq0_iu_exception_val_offset]), + .din(lq0_iu_exception_val_d), + .dout(lq0_iu_exception_val_q) +); + +tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) lq0_iu_exception_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lq0_iu_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lq0_iu_exception_offset:lq0_iu_exception_offset + 6 - 1]), + .scout(sov[lq0_iu_exception_offset:lq0_iu_exception_offset + 6 - 1]), + .din(lq0_iu_exception_d), + .dout(lq0_iu_exception_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq0_iu_dacr_type_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lq0_iu_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lq0_iu_dacr_type_offset]), + .scout(sov[lq0_iu_dacr_type_offset]), + .din(lq0_iu_dacr_type_d), + .dout(lq0_iu_dacr_type_q) +); + +tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lq0_iu_dacrw_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lq0_iu_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lq0_iu_dacrw_offset:lq0_iu_dacrw_offset + 4 - 1]), + .scout(sov[lq0_iu_dacrw_offset:lq0_iu_dacrw_offset + 4 - 1]), + .din(lq0_iu_dacrw_d), + .dout(lq0_iu_dacrw_q) +); + +tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) lq0_iu_instr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lq0_iu_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lq0_iu_instr_offset:lq0_iu_instr_offset + 32 - 1]), + .scout(sov[lq0_iu_instr_offset:lq0_iu_instr_offset + 32 - 1]), + .din(lq0_iu_instr_d), + .dout(lq0_iu_instr_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_spec_load_miss_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_spec_load_miss_offset]), + .scout(sov[ex5_spec_load_miss_offset]), + .din(ex5_spec_load_miss_d), + .dout(ex5_spec_load_miss_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_spec_itag_vld_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_spec_itag_vld_offset]), + .scout(sov[ex5_spec_itag_vld_offset]), + .din(ex5_spec_itag_vld_d), + .dout(ex5_spec_itag_vld_q) +); + +tri_regk #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex5_spec_itag_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_spec_itag_offset:ex5_spec_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[ex5_spec_itag_offset:ex5_spec_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(ex5_spec_itag_d), + .dout(ex5_spec_itag_q) +); + +tri_regk #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex5_spec_tid_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_spec_tid_offset:ex5_spec_tid_offset + `THREADS - 1]), + .scout(sov[ex5_spec_tid_offset:ex5_spec_tid_offset + `THREADS - 1]), + .din(ex5_spec_tid_d), + .dout(ex5_spec_tid_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_blk_pf_load_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_blk_pf_load_offset]), + .scout(sov[ex5_blk_pf_load_offset]), + .din(ex5_blk_pf_load_d), + .dout(ex5_blk_pf_load_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_lq_wNComp_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_lq_wNComp_val_offset]), + .scout(sov[ex5_lq_wNComp_val_offset]), + .din(ex5_lq_wNComp_val_d), + .dout(ex5_lq_wNComp_val_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_lq_wNComp_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_lq_wNComp_val_offset]), + .scout(sov[ex6_lq_wNComp_val_offset]), + .din(ex6_lq_wNComp_val_d), + .dout(ex6_lq_wNComp_val_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_wNComp_ord_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_wNComp_ord_offset]), + .scout(sov[ex5_wNComp_ord_offset]), + .din(ex5_wNComp_ord_d), + .dout(ex5_wNComp_ord_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_restart_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_restart_val_offset]), + .scout(sov[ex5_restart_val_offset]), + .din(ex5_restart_val_d), + .dout(ex5_restart_val_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_derat_restart_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_derat_restart_offset]), + .scout(sov[ex5_derat_restart_offset]), + .din(ex5_derat_restart_d), + .dout(ex5_derat_restart_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_derat_restart_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_derat_restart_offset]), + .scout(sov[ex6_derat_restart_offset]), + .din(ex6_derat_restart_d), + .dout(ex6_derat_restart_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_dir_restart_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_dir_restart_offset]), + .scout(sov[ex5_dir_restart_offset]), + .din(ex5_dir_restart_d), + .dout(ex5_dir_restart_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_dir_restart_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_dir_restart_offset]), + .scout(sov[ex6_dir_restart_offset]), + .din(ex6_dir_restart_d), + .dout(ex6_dir_restart_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_dec_restart_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_dec_restart_offset]), + .scout(sov[ex5_dec_restart_offset]), + .din(ex5_dec_restart_d), + .dout(ex5_dec_restart_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_dec_restart_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_dec_restart_offset]), + .scout(sov[ex6_dec_restart_offset]), + .din(ex6_dec_restart_d), + .dout(ex6_dec_restart_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_derat_itagHit_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_derat_itagHit_offset]), + .scout(sov[ex4_derat_itagHit_offset]), + .din(ex4_derat_itagHit_d), + .dout(ex4_derat_itagHit_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_stq_restart_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_stq_restart_val_offset]), + .scout(sov[ex6_stq_restart_val_offset]), + .din(ex6_stq_restart_val_d), + .dout(ex6_stq_restart_val_q) +); +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_restart_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_restart_val_offset]), + .scout(sov[ex6_restart_val_offset]), + .din(ex6_restart_val_d), + .dout(ex6_restart_val_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_execute_vld_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_execute_vld_offset]), + .scout(sov[ex5_execute_vld_offset]), + .din(ex5_execute_vld_d), + .dout(ex5_execute_vld_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_flush2ucode_type_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_flush2ucode_type_offset]), + .scout(sov[ex5_flush2ucode_type_offset]), + .din(ex5_flush2ucode_type_d), + .dout(ex5_flush2ucode_type_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_recirc_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_recirc_val_offset]), + .scout(sov[ex5_recirc_val_offset]), + .din(ex5_recirc_val_d), + .dout(ex5_recirc_val_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_wchkall_cplt_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_wchkall_cplt_offset]), + .scout(sov[ex5_wchkall_cplt_offset]), + .din(ex5_wchkall_cplt_d), + .dout(ex5_wchkall_cplt_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_misalign_flush_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_misalign_flush_offset]), + .scout(sov[ex6_misalign_flush_offset]), + .din(ex6_misalign_flush_d), + .dout(ex6_misalign_flush_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ldq_idle_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_idle_offset:ldq_idle_offset + `THREADS - 1]), + .scout(sov[ldq_idle_offset:ldq_idle_offset + `THREADS - 1]), + .din(ldq_idle_d), + .dout(ldq_idle_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_strg_gate_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_strg_gate_offset]), + .scout(sov[ex4_strg_gate_offset]), + .din(ex4_strg_gate_d), + .dout(ex4_strg_gate_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_lswx_restart_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_lswx_restart_offset]), + .scout(sov[ex4_lswx_restart_offset]), + .din(ex4_lswx_restart_d), + .dout(ex4_lswx_restart_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_icswx_restart_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_icswx_restart_offset]), + .scout(sov[ex4_icswx_restart_offset]), + .din(ex4_icswx_restart_d), + .dout(ex4_icswx_restart_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_is_sync_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_is_sync_offset]), + .scout(sov[ex4_is_sync_offset]), + .din(ex4_is_sync_d), + .dout(ex4_is_sync_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel2_xu_wren_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rel2_xu_wren_offset]), + .scout(sov[rel2_xu_wren_offset]), + .din(rel2_xu_wren_d), + .dout(rel2_xu_wren_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_store_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq2_store_val_offset]), + .scout(sov[stq2_store_val_offset]), + .din(stq2_store_val_d), + .dout(stq2_store_val_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stq3_store_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[stq3_store_val_offset]), + .scout(sov[stq3_store_val_offset]), + .din(stq3_store_val_d), + .dout(stq3_store_val_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_store_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq4_store_val_offset]), + .scout(sov[stq4_store_val_offset]), + .din(stq4_store_val_d), + .dout(stq4_store_val_q) +); + +tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) stq6_itag_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq5_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq6_itag_offset:stq6_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[stq6_itag_offset:stq6_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(stq6_itag_d), + .dout(stq6_itag_q) +); + +tri_rlmreg_p #(.WIDTH(AXU_TARGET_ENC), .INIT(0), .NEEDS_SRESET(1)) stq6_tgpr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq5_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq6_tgpr_offset:stq6_tgpr_offset + AXU_TARGET_ENC - 1]), + .scout(sov[stq6_tgpr_offset:stq6_tgpr_offset + AXU_TARGET_ENC - 1]), + .din(stq6_tgpr_d), + .dout(stq6_tgpr_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) stq2_thrd_id_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq1_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq2_thrd_id_offset:stq2_thrd_id_offset + `THREADS - 1]), + .scout(sov[stq2_thrd_id_offset:stq2_thrd_id_offset + `THREADS - 1]), + .din(stq2_thrd_id_d), + .dout(stq2_thrd_id_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) stq3_thrd_id_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq2_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq3_thrd_id_offset:stq3_thrd_id_offset + `THREADS - 1]), + .scout(sov[stq3_thrd_id_offset:stq3_thrd_id_offset + `THREADS - 1]), + .din(stq3_thrd_id_d), + .dout(stq3_thrd_id_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) stq4_thrd_id_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq4_thrd_id_offset:stq4_thrd_id_offset + `THREADS - 1]), + .scout(sov[stq4_thrd_id_offset:stq4_thrd_id_offset + `THREADS - 1]), + .din(stq4_thrd_id_d), + .dout(stq4_thrd_id_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) stq5_thrd_id_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq4_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq5_thrd_id_offset:stq5_thrd_id_offset + `THREADS - 1]), + .scout(sov[stq5_thrd_id_offset:stq5_thrd_id_offset + `THREADS - 1]), + .din(stq5_thrd_id_d), + .dout(stq5_thrd_id_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) stq6_thrd_id_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq5_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq6_thrd_id_offset:stq6_thrd_id_offset + `THREADS - 1]), + .scout(sov[stq6_thrd_id_offset:stq6_thrd_id_offset + `THREADS - 1]), + .din(stq6_thrd_id_d), + .dout(stq6_thrd_id_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) stq7_thrd_id_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq7_thrd_id_offset:stq7_thrd_id_offset + `THREADS - 1]), + .scout(sov[stq7_thrd_id_offset:stq7_thrd_id_offset + `THREADS - 1]), + .din(stq7_thrd_id_d), + .dout(stq7_thrd_id_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) stq8_thrd_id_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq8_thrd_id_offset:stq8_thrd_id_offset + `THREADS - 1]), + .scout(sov[stq8_thrd_id_offset:stq8_thrd_id_offset + `THREADS - 1]), + .din(stq8_thrd_id_d), + .dout(stq8_thrd_id_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_mftgpr_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq2_mftgpr_val_offset]), + .scout(sov[stq2_mftgpr_val_offset]), + .din(stq2_mftgpr_val_d), + .dout(stq2_mftgpr_val_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stq3_mftgpr_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[stq3_mftgpr_val_offset]), + .scout(sov[stq3_mftgpr_val_offset]), + .din(stq3_mftgpr_val_d), + .dout(stq3_mftgpr_val_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_mftgpr_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq4_mftgpr_val_offset]), + .scout(sov[stq4_mftgpr_val_offset]), + .din(stq4_mftgpr_val_d), + .dout(stq4_mftgpr_val_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stq5_mftgpr_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[stq5_mftgpr_val_offset]), + .scout(sov[stq5_mftgpr_val_offset]), + .din(stq5_mftgpr_val_d), + .dout(stq5_mftgpr_val_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq6_mftgpr_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq6_mftgpr_val_offset]), + .scout(sov[stq6_mftgpr_val_offset]), + .din(stq6_mftgpr_val_d), + .dout(stq6_mftgpr_val_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stq7_mftgpr_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[stq7_mftgpr_val_offset]), + .scout(sov[stq7_mftgpr_val_offset]), + .din(stq7_mftgpr_val_d), + .dout(stq7_mftgpr_val_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq8_mftgpr_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq8_mftgpr_val_offset]), + .scout(sov[stq8_mftgpr_val_offset]), + .din(stq8_mftgpr_val_d), + .dout(stq8_mftgpr_val_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_mfdpf_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq2_mfdpf_val_offset]), + .scout(sov[stq2_mfdpf_val_offset]), + .din(stq2_mfdpf_val_d), + .dout(stq2_mfdpf_val_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stq3_mfdpf_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[stq3_mfdpf_val_offset]), + .scout(sov[stq3_mfdpf_val_offset]), + .din(stq3_mfdpf_val_d), + .dout(stq3_mfdpf_val_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_mfdpf_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq4_mfdpf_val_offset]), + .scout(sov[stq4_mfdpf_val_offset]), + .din(stq4_mfdpf_val_d), + .dout(stq4_mfdpf_val_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stq5_mfdpf_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[stq5_mfdpf_val_offset]), + .scout(sov[stq5_mfdpf_val_offset]), + .din(stq5_mfdpf_val_d), + .dout(stq5_mfdpf_val_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_mfdpa_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq2_mfdpa_val_offset]), + .scout(sov[stq2_mfdpa_val_offset]), + .din(stq2_mfdpa_val_d), + .dout(stq2_mfdpa_val_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stq3_mfdpa_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[stq3_mfdpa_val_offset]), + .scout(sov[stq3_mfdpa_val_offset]), + .din(stq3_mfdpa_val_d), + .dout(stq3_mfdpa_val_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_mfdpa_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq4_mfdpa_val_offset]), + .scout(sov[stq4_mfdpa_val_offset]), + .din(stq4_mfdpa_val_d), + .dout(stq4_mfdpa_val_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stq5_mfdpa_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[stq5_mfdpa_val_offset]), + .scout(sov[stq5_mfdpa_val_offset]), + .din(stq5_mfdpa_val_d), + .dout(stq5_mfdpa_val_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq6_mfdpa_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq6_mfdpa_val_offset]), + .scout(sov[stq6_mfdpa_val_offset]), + .din(stq6_mfdpa_val_d), + .dout(stq6_mfdpa_val_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_ci_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq1_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq2_ci_offset]), + .scout(sov[stq2_ci_offset]), + .din(stq2_ci_d), + .dout(stq2_ci_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stq3_ci_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[stq3_ci_offset]), + .scout(sov[stq3_ci_offset]), + .din(stq3_ci_d), + .dout(stq3_ci_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_resv_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq1_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq2_resv_offset]), + .scout(sov[stq2_resv_offset]), + .din(stq2_resv_d), + .dout(stq2_resv_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stq3_resv_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[stq3_resv_offset]), + .scout(sov[stq3_resv_offset]), + .din(stq3_resv_d), + .dout(stq3_resv_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_wclr_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq2_wclr_val_offset]), + .scout(sov[stq2_wclr_val_offset]), + .din(stq2_wclr_val_d), + .dout(stq2_wclr_val_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq3_wclr_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq3_wclr_val_offset]), + .scout(sov[stq3_wclr_val_offset]), + .din(stq3_wclr_val_d), + .dout(stq3_wclr_val_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_wclr_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq4_wclr_val_offset]), + .scout(sov[stq4_wclr_val_offset]), + .din(stq4_wclr_val_d), + .dout(stq4_wclr_val_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_wclr_all_set_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq1_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq2_wclr_all_set_offset]), + .scout(sov[stq2_wclr_all_set_offset]), + .din(stq2_wclr_all_set_d), + .dout(stq2_wclr_all_set_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stq3_wclr_all_set_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[stq3_wclr_all_set_offset]), + .scout(sov[stq3_wclr_all_set_offset]), + .din(stq3_wclr_all_set_d), + .dout(stq3_wclr_all_set_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_wclr_all_set_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq4_wclr_all_set_offset]), + .scout(sov[stq4_wclr_all_set_offset]), + .din(stq4_wclr_all_set_d), + .dout(stq4_wclr_all_set_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_epid_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq1_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq2_epid_val_offset]), + .scout(sov[stq2_epid_val_offset]), + .din(stq2_epid_val_d), + .dout(stq2_epid_val_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_rec_stcx_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq4_rec_stcx_offset]), + .scout(sov[stq4_rec_stcx_offset]), + .din(stq4_rec_stcx_d), + .dout(stq4_rec_stcx_q) +); + +tri_regk #(.WIDTH(25), .INIT(0), .NEEDS_SRESET(1)) stq3_icswx_data_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(stq2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[stq3_icswx_data_offset:stq3_icswx_data_offset + 25 - 1]), + .scout(sov[stq3_icswx_data_offset:stq3_icswx_data_offset + 25 - 1]), + .din(stq3_icswx_data_d), + .dout(stq3_icswx_data_q) +); + +tri_rlmreg_p #(.WIDTH(`CR_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) ex2_cr_fld_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_instr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_cr_fld_offset:ex2_cr_fld_offset + `CR_POOL_ENC - 1]), + .scout(sov[ex2_cr_fld_offset:ex2_cr_fld_offset + `CR_POOL_ENC - 1]), + .din(ex2_cr_fld_d), + .dout(ex2_cr_fld_q) +); + +tri_regk #(.WIDTH(`CR_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) ex3_cr_fld_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_cr_fld_offset:ex3_cr_fld_offset + `CR_POOL_ENC - 1]), + .scout(sov[ex3_cr_fld_offset:ex3_cr_fld_offset + `CR_POOL_ENC - 1]), + .din(ex3_cr_fld_d), + .dout(ex3_cr_fld_q) +); + +tri_rlmreg_p #(.WIDTH(`CR_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) ex4_cr_fld_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_cr_fld_offset:ex4_cr_fld_offset + `CR_POOL_ENC - 1]), + .scout(sov[ex4_cr_fld_offset:ex4_cr_fld_offset + `CR_POOL_ENC - 1]), + .din(ex4_cr_fld_d), + .dout(ex4_cr_fld_q) +); + +tri_regk #(.WIDTH(`CR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) ex5_cr_fld_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_cr_fld_offset:ex5_cr_fld_offset + (`CR_POOL_ENC+`THREADS_POOL_ENC) - 1]), + .scout(sov[ex5_cr_fld_offset:ex5_cr_fld_offset + (`CR_POOL_ENC+`THREADS_POOL_ENC) - 1]), + .din(ex5_cr_fld_d), + .dout(ex5_cr_fld_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dir_arr_rd_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[dir_arr_rd_val_offset]), + .scout(sov[dir_arr_rd_val_offset]), + .din(dir_arr_rd_val_d), + .dout(dir_arr_rd_val_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) dir_arr_rd_tid_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[dir_arr_rd_tid_offset:dir_arr_rd_tid_offset + `THREADS - 1]), + .scout(sov[dir_arr_rd_tid_offset:dir_arr_rd_tid_offset + `THREADS - 1]), + .din(dir_arr_rd_tid_d), + .dout(dir_arr_rd_tid_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dir_arr_rd_rv1_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[dir_arr_rd_rv1_val_offset]), + .scout(sov[dir_arr_rd_rv1_val_offset]), + .din(dir_arr_rd_rv1_val_d), + .dout(dir_arr_rd_rv1_val_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dir_arr_rd_ex0_done_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[dir_arr_rd_ex0_done_offset]), + .scout(sov[dir_arr_rd_ex0_done_offset]), + .din(dir_arr_rd_ex0_done_d), + .dout(dir_arr_rd_ex0_done_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) dir_arr_rd_ex1_done_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[dir_arr_rd_ex1_done_offset]), + .scout(sov[dir_arr_rd_ex1_done_offset]), + .din(dir_arr_rd_ex1_done_d), + .dout(dir_arr_rd_ex1_done_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dir_arr_rd_ex2_done_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[dir_arr_rd_ex2_done_offset]), + .scout(sov[dir_arr_rd_ex2_done_offset]), + .din(dir_arr_rd_ex2_done_d), + .dout(dir_arr_rd_ex2_done_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) dir_arr_rd_ex3_done_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[dir_arr_rd_ex3_done_offset]), + .scout(sov[dir_arr_rd_ex3_done_offset]), + .din(dir_arr_rd_ex3_done_d), + .dout(dir_arr_rd_ex3_done_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dir_arr_rd_ex4_done_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[dir_arr_rd_ex4_done_offset]), + .scout(sov[dir_arr_rd_ex4_done_offset]), + .din(dir_arr_rd_ex4_done_d), + .dout(dir_arr_rd_ex4_done_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) dir_arr_rd_ex5_done_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[dir_arr_rd_ex5_done_offset]), + .scout(sov[dir_arr_rd_ex5_done_offset]), + .din(dir_arr_rd_ex5_done_d), + .dout(dir_arr_rd_ex5_done_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dir_arr_rd_ex6_done_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[dir_arr_rd_ex6_done_offset]), + .scout(sov[dir_arr_rd_ex6_done_offset]), + .din(dir_arr_rd_ex6_done_d), + .dout(dir_arr_rd_ex6_done_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) pc_lq_ram_active_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[pc_lq_ram_active_offset:pc_lq_ram_active_offset + `THREADS - 1]), + .scout(sov[pc_lq_ram_active_offset:pc_lq_ram_active_offset + `THREADS - 1]), + .din(pc_lq_ram_active_d), + .dout(pc_lq_ram_active_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq_pc_ram_data_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lq_pc_ram_data_val_offset]), + .scout(sov[lq_pc_ram_data_val_offset]), + .din(lq_pc_ram_data_val_d), + .dout(lq_pc_ram_data_val_q) +); + +//--------------------------------------------------------------------- +// ACT's +//--------------------------------------------------------------------- +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_stg_act_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_stg_act_offset]), + .scout(sov[ex1_stg_act_offset]), + .din(ex1_stg_act_d), + .dout(ex1_stg_act_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_stg_act_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_stg_act_offset]), + .scout(sov[ex2_stg_act_offset]), + .din(ex2_stg_act_d), + .dout(ex2_stg_act_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_stg_act_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_stg_act_offset]), + .scout(sov[ex3_stg_act_offset]), + .din(ex3_stg_act_d), + .dout(ex3_stg_act_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_stg_act_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_stg_act_offset]), + .scout(sov[ex4_stg_act_offset]), + .din(ex4_stg_act_d), + .dout(ex4_stg_act_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_stg_act_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_stg_act_offset]), + .scout(sov[ex5_stg_act_offset]), + .din(ex5_stg_act_d), + .dout(ex5_stg_act_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_stg_act_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_stg_act_offset]), + .scout(sov[ex6_stg_act_offset]), + .din(ex6_stg_act_d), + .dout(ex6_stg_act_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) binv2_stg_act_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[binv2_stg_act_offset]), + .scout(sov[binv2_stg_act_offset]), + .din(binv2_stg_act_d), + .dout(binv2_stg_act_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) binv3_stg_act_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[binv3_stg_act_offset]), + .scout(sov[binv3_stg_act_offset]), + .din(binv3_stg_act_d), + .dout(binv3_stg_act_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) binv4_stg_act_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[binv4_stg_act_offset]), + .scout(sov[binv4_stg_act_offset]), + .din(binv4_stg_act_d), + .dout(binv4_stg_act_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) binv5_stg_act_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[binv5_stg_act_offset]), + .scout(sov[binv5_stg_act_offset]), + .din(binv5_stg_act_d), + .dout(binv5_stg_act_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) binv6_stg_act_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[binv6_stg_act_offset]), + .scout(sov[binv6_stg_act_offset]), + .din(binv6_stg_act_d), + .dout(binv6_stg_act_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_stg_act_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq2_stg_act_offset]), + .scout(sov[stq2_stg_act_offset]), + .din(stq2_stg_act_d), + .dout(stq2_stg_act_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq3_stg_act_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq3_stg_act_offset]), + .scout(sov[stq3_stg_act_offset]), + .din(stq3_stg_act_d), + .dout(stq3_stg_act_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_stg_act_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq4_stg_act_offset]), + .scout(sov[stq4_stg_act_offset]), + .din(stq4_stg_act_d), + .dout(stq4_stg_act_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq5_stg_act_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq5_stg_act_offset]), + .scout(sov[stq5_stg_act_offset]), + .din(stq5_stg_act_d), + .dout(stq5_stg_act_q) +); + +assign siv[0:scan_right] = {sov[1:scan_right], scan_in}; +assign fgen_scan_in = sov[0]; +assign scan_out = fgen_scan_out; + +endmodule diff --git a/dev/verilog/work/lq_dec.v b/dev/verilog/work/lq_dec.v new file mode 100755 index 0000000..37c831d --- /dev/null +++ b/dev/verilog/work/lq_dec.v @@ -0,0 +1,3750 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: LQ SFX Decode +//***************************************************************************** + +`include "tri_a2o.vh" + + + +module lq_dec( + nclk, + vdd, + gnd, + d_mode_dc, + delay_lclkr_dc, + mpw1_dc_b, + mpw2_dc_b, + func_sl_force, + func_sl_thold_0_b, + func_slp_sl_force, + func_slp_sl_thold_0_b, + sg_0, + scan_in, + scan_out, + xu_lq_spr_msr_gs, + xu_lq_spr_msr_pr, + xu_lq_spr_msr_ucle, + xu_lq_spr_msrp_uclep, + xu_lq_spr_ccr2_en_pc, + xu_lq_spr_ccr2_en_ditc, + xu_lq_spr_ccr2_en_icswx, + iu_lq_cp_flush, + rv_lq_vld, + rv_lq_ex0_itag, + rv_lq_ex0_instr, + rv_lq_ex0_ucode, + rv_lq_ex0_ucode_cnt, + rv_lq_ex0_t1_v, + rv_lq_ex0_t1_p, + rv_lq_ex0_t3_p, + rv_lq_ex0_s1_v, + rv_lq_ex0_s2_v, + dcc_dec_hold_all, + xu_lq_hold_req, + mm_lq_hold_req, + mm_lq_hold_done, + lq_rv_itag0_vld, + lq_rv_itag0, + lq_rv_itag0_abort, + lq_rv_hold_all, + lq_rv_gpr_ex6_we, + lq_xu_gpr_ex5_we, + lq_xu_ex5_act, + dec_byp_ex1_s1_vld, + dec_byp_ex1_s2_vld, + dec_byp_ex1_use_imm, + dec_byp_ex1_imm, + dec_byp_ex1_rs1_zero, + dec_byp_ex0_stg_act, + dec_byp_ex1_stg_act, + dec_byp_ex5_stg_act, + dec_byp_ex6_stg_act, + dec_byp_ex7_stg_act, + byp_dec_ex2_req_aborted, + byp_dec_ex1_s1_abort, + byp_dec_ex1_s2_abort, + pf_dec_req_addr, + pf_dec_req_thrd, + pf_dec_req_val, + dec_pf_ack, + lsq_ctl_sync_in_stq, + lsq_ctl_stq_release_itag_vld, + lsq_ctl_stq_release_itag, + lsq_ctl_stq_release_tid, + lsq_ctl_rv0_back_inv, + lsq_ctl_rv1_back_inv_addr, + dcc_dec_arr_rd_rv1_val, + dcc_dec_arr_rd_congr_cl, + dir_dec_rel3_dir_wr_val, + dir_dec_rel3_dir_wr_addr, + dcc_dec_stq3_mftgpr_val, + dcc_dec_stq5_mftgpr_val, + derat_rv1_snoop_val, + derat_dec_rv1_snoop_addr, + derat_dec_hole_all, + dec_dcc_ex1_cmd_act, + ctl_dat_ex1_data_act, + dec_derat_ex1_derat_act, + dec_dir_ex2_dir_rd_act, + dec_derat_ex1_pfetch_val, + dec_spr_ex1_valid, + dec_dcc_ex1_expt_det, + dec_dcc_ex1_priv_prog, + dec_dcc_ex1_hypv_prog, + dec_dcc_ex1_illeg_prog, + dec_dcc_ex1_dlock_excp, + dec_dcc_ex1_ilock_excp, + dec_dcc_ex1_ehpriv_excp, + dec_dcc_ex1_ucode_val, + dec_dcc_ex1_ucode_cnt, + dec_dcc_ex1_ucode_op, + dec_dcc_ex1_sfx_val, + dec_dcc_ex1_cache_acc, + dec_dcc_ex1_thrd_id, + dec_dcc_ex1_instr, + dec_dcc_ex1_optype1, + dec_dcc_ex1_optype2, + dec_dcc_ex1_optype4, + dec_dcc_ex1_optype8, + dec_dcc_ex1_optype16, + dec_dcc_ex1_optype32, + dec_dcc_ex1_target_gpr, + dec_dcc_ex1_load_instr, + dec_dcc_ex1_store_instr, + dec_dcc_ex1_dcbf_instr, + dec_dcc_ex1_sync_instr, + dec_dcc_ex1_mbar_instr, + dec_dcc_ex1_makeitso_instr, + dec_dcc_ex1_l_fld, + dec_dcc_ex1_dcbi_instr, + dec_dcc_ex1_dcbz_instr, + dec_dcc_ex1_dcbt_instr, + dec_dcc_ex1_pfetch_val, + dec_dcc_ex1_dcbtst_instr, + dec_dcc_ex1_th_fld, + dec_dcc_ex1_dcbtls_instr, + dec_dcc_ex1_dcbtstls_instr, + dec_dcc_ex1_dcblc_instr, + dec_dcc_ex1_dci_instr, + dec_dcc_ex1_dcbst_instr, + dec_dcc_ex1_icbi_instr, + dec_dcc_ex1_ici_instr, + dec_dcc_ex1_icblc_instr, + dec_dcc_ex1_icbt_instr, + dec_dcc_ex1_icbtls_instr, + dec_dcc_ex1_tlbsync_instr, + dec_dcc_ex1_resv_instr, + dec_dcc_ex1_cr_fld, + dec_dcc_ex1_mutex_hint, + dec_dcc_ex1_axu_op_val, + dec_dcc_ex1_axu_falign, + dec_dcc_ex1_axu_fexcpt, + dec_dcc_ex1_axu_instr_type, + dec_dcc_ex1_upd_form, + dec_dcc_ex1_algebraic, + dec_dcc_ex1_strg_index, + dec_dcc_ex1_src_gpr, + dec_dcc_ex1_src_axu, + dec_dcc_ex1_src_dp, + dec_dcc_ex1_targ_gpr, + dec_dcc_ex1_targ_axu, + dec_dcc_ex1_targ_dp, + dec_derat_ex1_is_load, + dec_derat_ex1_is_store, + dec_derat_ex0_val, + dec_derat_ex0_is_extload, + dec_derat_ex0_is_extstore, + dec_derat_ex1_ra_eq_ea, + dec_derat_ex1_byte_rev, + dec_derat_ex1_is_touch, + dec_dcc_ex1_is_msgsnd, + dec_dcc_ex1_mtspr_trace, + dec_dcc_ex1_mword_instr, + dec_dcc_ex1_icswx_instr, + dec_dcc_ex1_icswxdot_instr, + dec_dcc_ex1_icswx_epid, + dec_dcc_ex1_ldawx_instr, + dec_dcc_ex1_wclr_instr, + dec_dcc_ex1_wchk_instr, + dec_dcc_ex1_itag, + dec_dcc_ex2_rotsel_ovrd, + dec_dcc_ex3_mtdp_val, + dec_dcc_ex3_mfdp_val, + dec_dcc_ex3_ipc_ba, + dec_dcc_ex3_ipc_sz, + dec_ex2_is_any_load_dac, + dec_ex2_is_any_store_dac, + dec_dcc_ex5_req_abort_rpt, + dec_dcc_ex5_axu_abort_rpt, + ctl_lsq_ex_pipe_full, + dcc_dec_ex5_wren +); + +//------------------------------------------------------------------- +// Generics +//------------------------------------------------------------------- +//parameter EXPAND_TYPE = 2; +//parameter `GPR_WIDTH_ENC = 6; +//parameter `XER_POOL_ENC = 4; +//parameter `CR_POOL_ENC = 5; +//parameter `GPR_POOL_ENC = 6; +//parameter `AXU_SPARE_ENC = 3; +//parameter `CL_SIZE = 6; +//parameter `REAL_IFAR_WIDTH = 42; +//parameter `UCODE_ENTRIES_ENC = 3; +//parameter `THREADS = 2; +//parameter `THREADS_POOL_ENC = 1; +//parameter `ITAG_SIZE_ENC = 7; + + + +inout vdd; + + +inout gnd; + +(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) + +input [0:`NCLK_WIDTH-1] nclk; + +input d_mode_dc; +input delay_lclkr_dc; +input mpw1_dc_b; +input mpw2_dc_b; +input func_sl_force; +input func_sl_thold_0_b; +input func_slp_sl_force; +input func_slp_sl_thold_0_b; +input sg_0; + +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + +input scan_in; + +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + +output scan_out; + +input [0:`THREADS-1] xu_lq_spr_msr_gs; +input [0:`THREADS-1] xu_lq_spr_msr_pr; +input [0:`THREADS-1] xu_lq_spr_msr_ucle; +input [0:`THREADS-1] xu_lq_spr_msrp_uclep; +input xu_lq_spr_ccr2_en_pc; +input xu_lq_spr_ccr2_en_ditc; +input xu_lq_spr_ccr2_en_icswx; + +input [0:`THREADS-1] iu_lq_cp_flush; + +input [0:`THREADS-1] rv_lq_vld; +input [0:`ITAG_SIZE_ENC-1] rv_lq_ex0_itag; +input [0:31] rv_lq_ex0_instr; +input [0:1] rv_lq_ex0_ucode; +input [0:`UCODE_ENTRIES_ENC-1] rv_lq_ex0_ucode_cnt; +input rv_lq_ex0_t1_v; +input [0:`GPR_POOL_ENC-1] rv_lq_ex0_t1_p; +input [0:`GPR_POOL_ENC-1] rv_lq_ex0_t3_p; +input rv_lq_ex0_s1_v; +input rv_lq_ex0_s2_v; + +input dcc_dec_hold_all; + +input xu_lq_hold_req; +input mm_lq_hold_req; +input mm_lq_hold_done; + +output [0:`THREADS-1] lq_rv_itag0_vld; +output [0:`ITAG_SIZE_ENC-1] lq_rv_itag0; +output lq_rv_itag0_abort; +output lq_rv_hold_all; + +output lq_rv_gpr_ex6_we; +output lq_xu_gpr_ex5_we; + +output lq_xu_ex5_act; +output dec_byp_ex1_s1_vld; +output dec_byp_ex1_s2_vld; +output dec_byp_ex1_use_imm; +output [64-(2**`GPR_WIDTH_ENC):63] dec_byp_ex1_imm; +output dec_byp_ex1_rs1_zero; +output dec_byp_ex0_stg_act; +output dec_byp_ex1_stg_act; +output dec_byp_ex5_stg_act; +output dec_byp_ex6_stg_act; +output dec_byp_ex7_stg_act; +input byp_dec_ex2_req_aborted; +input byp_dec_ex1_s1_abort; +input byp_dec_ex1_s2_abort; +input [64-(2**`GPR_WIDTH_ENC):63-`CL_SIZE] pf_dec_req_addr; +input [0:`THREADS-1] pf_dec_req_thrd; +input pf_dec_req_val; +output dec_pf_ack; + +input lsq_ctl_sync_in_stq; + +input lsq_ctl_stq_release_itag_vld; +input [0:`ITAG_SIZE_ENC-1] lsq_ctl_stq_release_itag; +input [0:`THREADS-1] lsq_ctl_stq_release_tid; + +input lsq_ctl_rv0_back_inv; +input [64-`REAL_IFAR_WIDTH:63-`CL_SIZE] lsq_ctl_rv1_back_inv_addr; + +input dcc_dec_arr_rd_rv1_val; +input [0:5] dcc_dec_arr_rd_congr_cl; +input dir_dec_rel3_dir_wr_val; // Reload Directory Write Stage is valid +input [64-(`DC_SIZE-3):63-`CL_SIZE] dir_dec_rel3_dir_wr_addr; // Reload Directory Write Address +input dcc_dec_stq3_mftgpr_val; +input dcc_dec_stq5_mftgpr_val; + +input derat_rv1_snoop_val; +input [0:51] derat_dec_rv1_snoop_addr; +input derat_dec_hole_all; + +output dec_dcc_ex1_cmd_act; +output ctl_dat_ex1_data_act; +output dec_derat_ex1_derat_act; +output dec_dir_ex2_dir_rd_act; +output [0:`THREADS-1] dec_derat_ex1_pfetch_val; +output [0:`THREADS-1] dec_spr_ex1_valid; +output dec_dcc_ex1_expt_det; +output dec_dcc_ex1_priv_prog; +output dec_dcc_ex1_hypv_prog; +output dec_dcc_ex1_illeg_prog; +output dec_dcc_ex1_dlock_excp; +output dec_dcc_ex1_ilock_excp; +output dec_dcc_ex1_ehpriv_excp; +output dec_dcc_ex1_ucode_val; +output [0:`UCODE_ENTRIES_ENC-1] dec_dcc_ex1_ucode_cnt; +output dec_dcc_ex1_ucode_op; +output dec_dcc_ex1_sfx_val; +output dec_dcc_ex1_cache_acc; +output [0:`THREADS-1] dec_dcc_ex1_thrd_id; +output [0:31] dec_dcc_ex1_instr; +output dec_dcc_ex1_optype1; +output dec_dcc_ex1_optype2; +output dec_dcc_ex1_optype4; +output dec_dcc_ex1_optype8; +output dec_dcc_ex1_optype16; +output dec_dcc_ex1_optype32; +output [0:`GPR_POOL_ENC+`THREADS_POOL_ENC+`AXU_SPARE_ENC-1] dec_dcc_ex1_target_gpr; +output dec_dcc_ex1_load_instr; +output dec_dcc_ex1_store_instr; +output dec_dcc_ex1_dcbf_instr; +output dec_dcc_ex1_sync_instr; +output dec_dcc_ex1_mbar_instr; +output dec_dcc_ex1_makeitso_instr; +output [0:1] dec_dcc_ex1_l_fld; +output dec_dcc_ex1_dcbi_instr; +output dec_dcc_ex1_dcbz_instr; +output dec_dcc_ex1_dcbt_instr; +output dec_dcc_ex1_pfetch_val; +output dec_dcc_ex1_dcbtst_instr; +output [0:4] dec_dcc_ex1_th_fld; +output dec_dcc_ex1_dcbtls_instr; +output dec_dcc_ex1_dcbtstls_instr; +output dec_dcc_ex1_dcblc_instr; +output dec_dcc_ex1_dci_instr; +output dec_dcc_ex1_dcbst_instr; +output dec_dcc_ex1_icbi_instr; +output dec_dcc_ex1_ici_instr; +output dec_dcc_ex1_icblc_instr; +output dec_dcc_ex1_icbt_instr; +output dec_dcc_ex1_icbtls_instr; +output dec_dcc_ex1_tlbsync_instr; +output dec_dcc_ex1_resv_instr; +output [0:`CR_POOL_ENC-1] dec_dcc_ex1_cr_fld; +output dec_dcc_ex1_mutex_hint; +output dec_dcc_ex1_axu_op_val; +output dec_dcc_ex1_axu_falign; +output dec_dcc_ex1_axu_fexcpt; +output [0:2] dec_dcc_ex1_axu_instr_type; +output dec_dcc_ex1_upd_form; +output dec_dcc_ex1_algebraic; +output dec_dcc_ex1_strg_index; +output dec_dcc_ex1_src_gpr; +output dec_dcc_ex1_src_axu; +output dec_dcc_ex1_src_dp; +output dec_dcc_ex1_targ_gpr; +output dec_dcc_ex1_targ_axu; +output dec_dcc_ex1_targ_dp; +output dec_derat_ex1_is_load; +output dec_derat_ex1_is_store; +output [0:`THREADS-1] dec_derat_ex0_val; +output dec_derat_ex0_is_extload; +output dec_derat_ex0_is_extstore; +output dec_derat_ex1_ra_eq_ea; +output dec_derat_ex1_byte_rev; +output dec_derat_ex1_is_touch; +output dec_dcc_ex1_is_msgsnd; +output dec_dcc_ex1_mtspr_trace; +output dec_dcc_ex1_mword_instr; +output dec_dcc_ex1_icswx_instr; +output dec_dcc_ex1_icswxdot_instr; +output dec_dcc_ex1_icswx_epid; +output dec_dcc_ex1_ldawx_instr; +output dec_dcc_ex1_wclr_instr; +output dec_dcc_ex1_wchk_instr; +output [0:`ITAG_SIZE_ENC-1] dec_dcc_ex1_itag; +output [0:4] dec_dcc_ex2_rotsel_ovrd; +output dec_dcc_ex3_mtdp_val; +output dec_dcc_ex3_mfdp_val; +output [0:4] dec_dcc_ex3_ipc_ba; +output [0:1] dec_dcc_ex3_ipc_sz; +output dec_ex2_is_any_load_dac; +output dec_ex2_is_any_store_dac; +output dec_dcc_ex5_req_abort_rpt; +output dec_dcc_ex5_axu_abort_rpt; +output ctl_lsq_ex_pipe_full; + +input dcc_dec_ex5_wren; +//@@ Signal Declarations +wire [1:79] TBL_LD_ST_DEC_PT; +wire [1:50] TBL_VAL_STG_GATE_PT; +wire tiup; +wire tidn; +parameter AXU_TARGET_ENC = `GPR_POOL_ENC + `THREADS_POOL_ENC + `AXU_SPARE_ENC; +//------------------------------------------------------------------- +// Immediate Logic +//------------------------------------------------------------------- +wire ex1_zero_imm; +wire ex1_use_imm; +wire ex1_imm_size; +wire ex1_imm_signext; +wire [0:15] ex1_16b_imm; +wire [0:63] ex1_64b_imm; +wire [0:63] ex1_imm_sign_ext; +wire ex1_pfetch_rel_collision; +wire ex1_use_pfetch; +//------------------------------------------------------------------- +// Instruction Decode +//------------------------------------------------------------------- +wire ex1_opcode_is_62; +wire ex1_opcode_is_58; +wire ex1_opcode_is_31; +wire ex1_is_dcbf; +wire ex1_is_dcbi; +wire ex1_is_dcbst; +wire ex1_is_dcblc; +wire ex1_is_dcbt; +wire ex1_is_dcbtls; +wire ex1_is_dcbtst; +wire ex1_is_dcbtstls; +wire ex1_is_dcbz; +wire ex1_is_dci; +wire ex1_is_ici; +wire ex1_is_icbi; +wire ex1_is_icblc; +wire ex1_is_icbt; +wire ex1_is_icbtls; +wire ex1_is_lbz; +wire ex1_is_lbzu; +wire ex1_is_lbzux; +wire ex1_is_ld; +wire ex1_is_ldbrx; +wire ex1_is_ldu; +wire ex1_is_ldux; +wire ex1_is_lha; +wire ex1_is_lhau; +wire ex1_is_lhaux; +wire ex1_is_lhbrx; +wire ex1_is_lhzux; +wire ex1_is_lhz; +wire ex1_is_lhzu; +wire ex1_is_lmw; +wire ex1_is_lswi; +wire ex1_is_lwa; +wire ex1_is_lwaux; +wire ex1_is_lwz; +wire ex1_is_lwzu; +wire ex1_is_lwzux; +wire ex1_is_lwbrx; +wire ex1_derat_is_load; +wire ex1_derat_is_store; +wire ex1_is_ditc; +wire ex1_is_mfdp; +wire ex1_is_mfdpx; +wire ex1_is_mtdp; +wire ex1_is_mtdpx; +wire ex1_is_stb; +wire ex1_is_stbu; +wire ex1_is_stbux; +wire ex1_is_std; +wire ex1_is_stdbrx; +wire ex1_is_stdu; +wire ex1_is_stdux; +wire ex1_is_sth; +wire ex1_is_sthu; +wire ex1_is_sthux; +wire ex1_is_sthbrx; +wire ex1_is_stmw; +wire ex1_is_stswi; +wire ex1_is_stw; +wire ex1_is_stwbrx; +wire ex1_is_stwu; +wire ex1_is_stwux; +wire ex1_is_tlbsync; +wire ex1_is_lbepx; +wire ex1_is_lhepx; +wire ex1_is_lwepx; +wire ex1_is_ldepx; +wire ex1_is_stbepx; +wire ex1_is_sthepx; +wire ex1_is_stwepx; +wire ex1_is_stdepx; +wire ex1_is_dcbstep; +wire ex1_is_dcbtep; +wire ex1_is_dcbfep; +wire ex1_is_dcbtstep; +wire ex1_is_icbiep; +wire ex1_is_dcbzep; +wire ex1_is_msgsnd; +wire ex1_is_icswx; +wire ex1_is_icswepx; +wire ex1_is_wclr; +wire ex1_mtspr_trace; +wire ex0_is_lbepx; +wire ex0_is_lhepx; +wire ex0_is_lwepx; +wire ex0_is_ldepx; +wire ex0_is_dcbfep; +wire ex0_is_dcbtep; +wire ex0_is_dcbtstep; +wire ex0_is_dcbstep; +wire ex0_is_icbiep; +wire ex0_is_dcbzep; +wire ex0_is_stbepx; +wire ex0_is_sthepx; +wire ex0_is_stwepx; +wire ex0_is_stdepx; +wire ex0_is_icswepx; +wire ex0_is_larx; +wire ex0_is_stcx; +wire ex0_is_ldawx; +wire ex0_is_icswxdot; +wire ex0_cpNext_instr; +wire ex1_fxu_ld_update; +wire ex1_axu_ld_update; +wire ex1_ld_w_update; +wire ex1_fxu_st_update; +wire ex1_axu_st_update; +wire ex1_st_w_update; +wire ex1_gpr0_zero; +wire ex1_gpr0_zero_reg_op; +wire ex1_gpr0_zero_axu_op; +wire ex1_gpr0_zero_other; +wire ex5_t1_we; +wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] ex1_t1_wa; +wire ex1_needs_release; +wire ex1_stq3_needs_release; +wire ex1_stq3_sched_release; +wire ex0_release_vld; +wire ex0_needs_release; +wire stq2_needs_release; +wire ex1_cache_acc; +wire ex1_wclr_one_val; +wire ex1_cmd_act; +wire ex1_derat_act; +wire ex1_dir_rd_act; +wire ex1_dcm_instr; +wire ex1_is_any_load_dac; +wire ex1_is_any_store_dac; +wire ex1_resv_instr; +wire ex1_load_instr; +wire ex0_derat_is_extload; +wire ex0_derat_is_extstore; +wire ex1_th_fld_b6; +wire ex1_th_fld_c; +wire ex1_th_fld_l2; +wire [0:`ITAG_SIZE_ENC-1] ex0_iss_stq2_itag; +wire [0:`THREADS-1] ex0_iss_stq2_tid; +wire ex1_instr_priv; +wire ex1_instr_hypv; +wire ex1_dlk_dstor_cond0; +wire ex1_dlk_dstor_cond1; +wire ex1_dlk_dstor_cond2; +wire ex1_dlock_dstor; +wire ex1_ilock_dstor; +wire ex1_instr_ehpriv; +wire ex1_illeg_msgsnd; +wire ex1_illeg_ditc; +wire ex1_illeg_icswx; +wire ex1_illeg_instr; +wire ex1_illeg_lswi; +wire ex1_illeg_lmw; +wire ex1_priv_prog_excp; +wire ex1_hypv_prog_excp; +wire ex1_ra_eq_zero; +wire ex1_ra_eq_rt; +wire ex1_illeg_upd_form; +wire [0:7] ex1_num_bytes; +wire [0:7] ex1_num_bytes_plus3; +wire [0:5] ex1_num_regs; +wire [0:5] ex1_lower_bnd; +wire [0:5] ex1_upper_bnd; +wire [0:5] ex1_upper_bnd_wrap; +wire ex1_range_wrap; +wire ex1_ra_in_rng_lmw; +wire ex1_ra_in_rng_nowrap; +wire ex1_ra_in_rng_wrap; +wire ex1_ra_in_rng; +wire ex1_illeg_prog_excp; +wire ex1_dlock_dstor_excp; +wire ex1_ilock_dstor_excp; +wire ex1_ehpriv_excp; +wire ex1_axu_sel_target; +wire au_lq_ex0_extload; +wire au_lq_ex0_extstore; +wire au_lq_ex0_mftgpr; +wire au_lq_ex1_ldst_v; +wire au_lq_ex1_st_v; +wire [0:5] au_lq_ex1_ldst_size; +wire au_lq_ex1_ldst_update; +wire au_lq_ex1_mftgpr; +wire au_lq_ex1_mffgpr; +wire au_lq_ex1_movedp; +wire [0:AXU_TARGET_ENC-1] au_lq_ex1_ldst_tag; +wire [0:15] au_lq_ex1_ldst_dimm; +wire au_lq_ex1_ldst_indexed; +wire au_lq_ex1_ldst_forcealign; +wire au_lq_ex1_ldst_forceexcept; +wire au_lq_ex1_ldst_priv; +wire [0:2] au_lq_ex1_instr_type; +wire rv1_vld; +wire rv0_hold_taken; +wire ex2_abort_sel_val; +wire lq_rel_itag0_val; +wire lq_rel_itag0_abort; +wire [0:`ITAG_SIZE_ENC-1] lq_rel_itag0_itag; +wire [0:`THREADS-1] lq_rel_itag0_tid; +//------------------------------------------------------------------- +// Latches +//------------------------------------------------------------------- +wire ex0_vld_q; +wire ex0_vld_d; +wire ex1_vld_q; +wire ex1_vld_d; +wire ex2_vld_q; +wire ex2_vld_d; +wire ex3_vld_q; +wire ex3_vld_d; +wire ex4_vld_q; +wire ex4_vld_d; +wire ex5_vld_q; +wire ex5_vld_d; +wire ex0_stg_act_d; +wire ex0_stg_act_q; +wire ex1_stg_act_d; +wire ex1_stg_act_q; +wire ex2_stg_act_d; +wire ex2_stg_act_q; +wire ex3_stg_act_d; +wire ex3_stg_act_q; +wire ex4_stg_act_d; +wire ex4_stg_act_q; +wire ex5_stg_act_d; +wire ex5_stg_act_q; +wire ex6_stg_act_d; +wire ex6_stg_act_q; +wire ex7_stg_act_d; +wire ex7_stg_act_q; +wire ex5_stg_act; +wire ex0_stq2_stg_act; +wire ex1_stq3_stg_act; +wire [0:31] ex1_instr_d; +wire [0:31] ex1_instr_q; +wire ex2_is_any_load_dac_d; +wire ex2_is_any_load_dac_q; +wire ex2_is_any_store_dac_d; +wire ex2_is_any_store_dac_q; +wire ex2_dir_rd_act_d; +wire ex2_dir_rd_act_q; +wire [0:`THREADS-1] ex0_tid_q; +wire [0:`THREADS-1] ex1_tid_q; +wire [0:`THREADS-1] ex1_tid; +wire [0:`THREADS-1] ex2_tid_q; +wire [0:`THREADS-1] ex3_tid_q; +wire [0:`THREADS-1] ex4_tid_q; +wire ex1_s1_vld_q; +wire ex1_s2_vld_q; +wire ex1_t1_we_q; +wire ex1_t1_we_d; +wire ex2_t1_we_q; +wire ex2_t1_we_d; +wire ex3_t1_we_q; +wire ex3_t1_we_d; +wire ex4_t1_we_q; +wire ex4_t1_we_d; +wire ex5_t1_we_q; +wire ex5_t1_we_d; +wire ex6_t1_we_q; +wire ex6_t1_we_d; +wire lq_xu_ex5_act_q; +wire lq_xu_ex5_act_d; +wire [0:`GPR_POOL_ENC-1] ex1_t1_wa_q; +wire [0:`GPR_POOL_ENC-1] ex1_t3_wa_q; +wire [0:`ITAG_SIZE_ENC-1] ex1_itag_q; +wire [0:`ITAG_SIZE_ENC-1] ex1_itag; +wire [0:`ITAG_SIZE_ENC-1] ex2_itag_q; +wire [0:`ITAG_SIZE_ENC-1] release_itag_q; +wire [0:`ITAG_SIZE_ENC-1] release_itag_d; +wire release_itag_vld_q; +wire release_itag_vld_d; +wire [0:`THREADS-1] release_tid_q; +wire [0:`THREADS-1] release_tid_d; +wire ex0_needs_release_q; +wire ex0_needs_release_d; +wire ex1_needs_release_q; +wire ex1_needs_release_d; +wire ex2_needs_release_q; +wire ex2_needs_release_d; +wire ex2_needs_release; +wire ex1_release_attmp; +wire ex1_release_attmp_q; +wire ex1_release_attmp_d; +wire stq3_release_attmp_q; +wire stq3_release_attmp_d; +wire stq3_needs_release_q; +wire stq3_needs_release_d; +wire ex2_physical_upd_d; +wire ex2_physical_upd_q; +wire ex2_req_abort_rpt; +wire ex3_req_abort_rpt_d; +wire ex3_req_abort_rpt_q; +wire ex4_req_abort_rpt_d; +wire ex4_req_abort_rpt_q; +wire ex5_req_abort_rpt_d; +wire ex5_req_abort_rpt_q; +wire ex2_axu_physical_upd_d; +wire ex2_axu_physical_upd_q; +wire ex2_axu_abort_rpt; +wire ex3_axu_abort_rpt_d; +wire ex3_axu_abort_rpt_q; +wire ex4_axu_abort_rpt_d; +wire ex4_axu_abort_rpt_q; +wire ex5_axu_abort_rpt_d; +wire ex5_axu_abort_rpt_q; +wire [0:1] ex1_ucode_d; +wire [0:1] ex1_ucode_q; +wire [0:`UCODE_ENTRIES_ENC-1] ex1_ucode_cnt_d; +wire [0:`UCODE_ENTRIES_ENC-1] ex1_ucode_cnt_q; +wire stq1_release_vld; +wire stq2_release_vld_d; +wire stq2_release_vld_q; +wire stq3_release_vld_d; +wire stq3_release_vld_q; +wire stq4_release_vld_d; +wire stq4_release_vld_q; +wire stq5_release_vld_d; +wire stq5_release_vld_q; +wire stq6_release_vld_d; +wire stq6_release_vld_q; +wire stq7_release_vld_d; +wire stq7_release_vld_q; +wire spr_msr_gs; +wire [0:`THREADS-1] spr_msr_gs_d; +wire [0:`THREADS-1] spr_msr_gs_q; +wire spr_msr_pr; +wire [0:`THREADS-1] spr_msr_pr_d; +wire [0:`THREADS-1] spr_msr_pr_q; +wire spr_msr_ucle; +wire [0:`THREADS-1] spr_msr_ucle_d; +wire [0:`THREADS-1] spr_msr_ucle_q; +wire spr_msrp_uclep; +wire [0:`THREADS-1] spr_msrp_uclep_d; +wire [0:`THREADS-1] spr_msrp_uclep_q; +wire spr_ccr2_en_pc_d; +wire spr_ccr2_en_pc_q; +wire mm_hold_req_d; +wire mm_hold_req_q; +wire mm_hold_done_d; +wire mm_hold_done_q; +wire spr_ccr2_en_ditc_d; +wire spr_ccr2_en_ditc_q; +wire spr_ccr2_en_icswx_d; +wire spr_ccr2_en_icswx_q; +wire xu_lq_hold_req_d; +wire xu_lq_hold_req_q; +wire rv1_hold_taken_d; +wire rv1_hold_taken_q; +wire ex0_hold_taken_d; +wire ex0_hold_taken_q; +wire ex1_hold_taken_d; +wire ex1_hold_taken_q; +wire rv1_back_inv_d; +wire rv1_back_inv_q; +wire ex0_back_inv_d; +wire ex0_back_inv_q; +wire [64-`REAL_IFAR_WIDTH:63-`CL_SIZE] ex0_back_inv_addr_d; +wire [64-`REAL_IFAR_WIDTH:63-`CL_SIZE] ex0_back_inv_addr_q; +wire ex0_arr_rd_val_d; +wire ex0_arr_rd_val_q; +wire [0:5] ex0_arr_rd_congr_cl_d; +wire [0:5] ex0_arr_rd_congr_cl_q; +wire ex0_derat_snoop_val_d; +wire ex0_derat_snoop_val_q; +wire [0:51] ex0_derat_snoop_addr_d; +wire [0:51] ex0_derat_snoop_addr_q; +wire [0:63-`CL_SIZE] ex0_non_back_inv_addr; +wire ex0_selimm_addr_val; +wire ex1_selimm_addr_val_d; +wire ex1_selimm_addr_val_q; +wire [0:63-`CL_SIZE] ex1_selimm_addr_d; +wire [0:63-`CL_SIZE] ex1_selimm_addr_q; +wire [0:`THREADS-1] iu_lq_cp_flush_d; +wire [0:`THREADS-1] iu_lq_cp_flush_q; +wire stq6_mftgpr_val_d; +wire stq6_mftgpr_val_q; +wire stq7_mftgpr_val_d; +wire stq7_mftgpr_val_q; +wire [0:`ITAG_SIZE_ENC-1] stq2_release_itag_d; +wire [0:`ITAG_SIZE_ENC-1] stq2_release_itag_q; +wire [0:`THREADS-1] stq2_release_tid_d; +wire [0:`THREADS-1] stq2_release_tid_q; +wire rv1_stg_flush; +wire ex0_stg_flush; +wire ex1_stg_flush; +wire ex2_stg_flush; +wire ex3_stg_flush; +wire ex4_stg_flush; +//------------------------------------------------------------------- +// Scan Chain +//------------------------------------------------------------------- +parameter spr_msr_gs_offset = 0; +parameter spr_msr_pr_offset = spr_msr_gs_offset + `THREADS; +parameter spr_msr_ucle_offset = spr_msr_pr_offset + `THREADS; +parameter spr_msrp_uclep_offset = spr_msr_ucle_offset + `THREADS; +parameter spr_ccr2_en_pc_offset = spr_msrp_uclep_offset + `THREADS; +parameter spr_ccr2_en_ditc_offset = spr_ccr2_en_pc_offset + 1; +parameter spr_ccr2_en_icswx_offset = spr_ccr2_en_ditc_offset + 1; +parameter ex0_vld_offset = spr_ccr2_en_icswx_offset + 1; +parameter ex1_vld_offset = ex0_vld_offset + 1; +parameter ex2_vld_offset = ex1_vld_offset + 1; +parameter ex3_vld_offset = ex2_vld_offset + 1; +parameter ex4_vld_offset = ex3_vld_offset + 1; +parameter ex5_vld_offset = ex4_vld_offset + 1; +parameter ex0_stg_act_offset = ex5_vld_offset + 1; +parameter ex1_stg_act_offset = ex0_stg_act_offset + 1; +parameter ex2_stg_act_offset = ex1_stg_act_offset + 1; +parameter ex3_stg_act_offset = ex2_stg_act_offset + 1; +parameter ex4_stg_act_offset = ex3_stg_act_offset + 1; +parameter ex5_stg_act_offset = ex4_stg_act_offset + 1; +parameter ex6_stg_act_offset = ex5_stg_act_offset + 1; +parameter ex7_stg_act_offset = ex6_stg_act_offset + 1; +parameter ex1_ucode_offset = ex7_stg_act_offset + 1; +parameter ex1_ucode_cnt_offset = ex1_ucode_offset + 2; +parameter ex1_instr_offset = ex1_ucode_cnt_offset + `UCODE_ENTRIES_ENC; +parameter ex2_is_any_load_dac_offset = ex1_instr_offset + 32; +parameter ex2_is_any_store_dac_offset = ex2_is_any_load_dac_offset + 1; +parameter ex2_dir_rd_act_offset = ex2_is_any_store_dac_offset + 1; +parameter ex0_tid_offset = ex2_dir_rd_act_offset + 1; +parameter ex1_tid_offset = ex0_tid_offset + `THREADS; +parameter ex2_tid_offset = ex1_tid_offset + `THREADS; +parameter ex3_tid_offset = ex2_tid_offset + `THREADS; +parameter ex4_tid_offset = ex3_tid_offset + `THREADS; +parameter ex1_s1_vld_offset = ex4_tid_offset + `THREADS; +parameter ex1_s2_vld_offset = ex1_s1_vld_offset + 1; +parameter ex1_t1_we_offset = ex1_s2_vld_offset + 1; +parameter ex2_t1_we_offset = ex1_t1_we_offset + 1; +parameter ex3_t1_we_offset = ex2_t1_we_offset + 1; +parameter ex4_t1_we_offset = ex3_t1_we_offset + 1; +parameter ex5_t1_we_offset = ex4_t1_we_offset + 1; +parameter ex6_t1_we_offset = ex5_t1_we_offset + 1; +parameter lq_xu_ex5_act_offset = ex6_t1_we_offset + 1; +parameter ex1_t1_wa_offset = lq_xu_ex5_act_offset + 1; +parameter ex1_t3_wa_offset = ex1_t1_wa_offset + `GPR_POOL_ENC; +parameter ex1_itag_offset = ex1_t3_wa_offset + `GPR_POOL_ENC; +parameter ex2_itag_offset = ex1_itag_offset + `ITAG_SIZE_ENC; +parameter release_itag_offset = ex2_itag_offset + `ITAG_SIZE_ENC; +parameter release_tid_offset = release_itag_offset + `ITAG_SIZE_ENC; +parameter release_itag_vld_offset = release_tid_offset + `THREADS; +parameter ex0_needs_release_offset = release_itag_vld_offset + 1; +parameter ex1_needs_release_offset = ex0_needs_release_offset + 1; +parameter ex2_needs_release_offset = ex1_needs_release_offset + 1; +parameter ex2_physical_upd_offset = ex2_needs_release_offset + 1; +parameter ex3_req_abort_rpt_offset = ex2_physical_upd_offset + 1; +parameter ex4_req_abort_rpt_offset = ex3_req_abort_rpt_offset + 1; +parameter ex5_req_abort_rpt_offset = ex4_req_abort_rpt_offset + 1; +parameter ex2_axu_physical_upd_offset = ex5_req_abort_rpt_offset + 1; +parameter ex3_axu_abort_rpt_offset = ex2_axu_physical_upd_offset + 1; +parameter ex4_axu_abort_rpt_offset = ex3_axu_abort_rpt_offset + 1; +parameter ex5_axu_abort_rpt_offset = ex4_axu_abort_rpt_offset + 1; +parameter ex1_release_attmp_offset = ex5_axu_abort_rpt_offset + 1; +parameter stq3_release_attmp_offset = ex1_release_attmp_offset + 1; +parameter stq3_needs_release_offset = stq3_release_attmp_offset + 1; +parameter stq2_release_vld_offset = stq3_needs_release_offset + 1; +parameter stq3_release_vld_offset = stq2_release_vld_offset + 1; +parameter stq4_release_vld_offset = stq3_release_vld_offset + 1; +parameter stq5_release_vld_offset = stq4_release_vld_offset + 1; +parameter stq6_release_vld_offset = stq5_release_vld_offset + 1; +parameter stq7_release_vld_offset = stq6_release_vld_offset + 1; +parameter xu_lq_hold_req_offset = stq7_release_vld_offset + 1; +parameter mm_hold_req_offset = xu_lq_hold_req_offset + 1; +parameter mm_hold_done_offset = mm_hold_req_offset + 1; +parameter rv1_hold_taken_offset = mm_hold_done_offset + 1; +parameter ex0_hold_taken_offset = rv1_hold_taken_offset + 1; +parameter ex1_hold_taken_offset = ex0_hold_taken_offset + 1; +parameter rv1_back_inv_offset = ex1_hold_taken_offset + 1; +parameter ex0_back_inv_offset = rv1_back_inv_offset + 1; +parameter ex0_back_inv_addr_offset = ex0_back_inv_offset + 1; +parameter ex1_selimm_addr_val_offset = ex0_back_inv_addr_offset + (`REAL_IFAR_WIDTH-`CL_SIZE); +parameter ex1_selimm_addr_offset = ex1_selimm_addr_val_offset + 1; +parameter ex0_arr_rd_val_offset = ex1_selimm_addr_offset + (64-`CL_SIZE); +parameter ex0_arr_rd_congr_cl_offset = ex0_arr_rd_val_offset + 1; +parameter ex0_derat_snoop_val_offset = ex0_arr_rd_congr_cl_offset + 6; +parameter ex0_derat_snoop_addr_offset = ex0_derat_snoop_val_offset + 1; +parameter iu_lq_cp_flush_offset = ex0_derat_snoop_addr_offset + 52; +parameter stq6_mftgpr_val_offset = iu_lq_cp_flush_offset + `THREADS; +parameter stq7_mftgpr_val_offset = stq6_mftgpr_val_offset + 1; +parameter stq2_release_itag_offset = stq7_mftgpr_val_offset + 1; +parameter stq2_release_tid_offset = stq2_release_itag_offset + `ITAG_SIZE_ENC; +parameter scan_right = stq2_release_tid_offset + `THREADS; + +wire [0:scan_right-1] siv; +wire [0:scan_right-1] sov; + + +(* analysis_not_referenced="true" *) +wire unused; + +assign tiup = 1'b1; +assign tidn = 1'b0; + +assign spr_msr_gs_d = xu_lq_spr_msr_gs; +assign spr_msr_gs = |(spr_msr_gs_q & ex1_tid_q); +assign spr_msr_pr_d = xu_lq_spr_msr_pr; +assign spr_msr_pr = |(spr_msr_pr_q & ex1_tid_q); +assign spr_msr_ucle_d = xu_lq_spr_msr_ucle; +assign spr_msr_ucle = |(spr_msr_ucle_q & ex1_tid_q); +assign spr_msrp_uclep_d = xu_lq_spr_msrp_uclep; +assign spr_msrp_uclep = |(spr_msrp_uclep_q & ex1_tid_q); +assign spr_ccr2_en_pc_d = xu_lq_spr_ccr2_en_pc; +assign spr_ccr2_en_ditc_d = xu_lq_spr_ccr2_en_ditc; +assign spr_ccr2_en_icswx_d = xu_lq_spr_ccr2_en_icswx; +assign stq6_mftgpr_val_d = dcc_dec_stq5_mftgpr_val; +assign stq7_mftgpr_val_d = stq6_mftgpr_val_q; + +// Added logic for Erat invalidates +assign xu_lq_hold_req_d = xu_lq_hold_req; +assign mm_hold_req_d = mm_lq_hold_req | (mm_hold_req_q & (~(mm_hold_done_q))); +assign mm_hold_done_d = mm_lq_hold_done; +assign rv0_hold_taken = dcc_dec_hold_all | derat_dec_hole_all | xu_lq_hold_req_q; +assign rv1_hold_taken_d = rv0_hold_taken; +assign lq_rv_hold_all = rv0_hold_taken; +assign ex0_hold_taken_d = rv1_hold_taken_q; +assign ex1_hold_taken_d = ex0_hold_taken_q; +assign rv1_back_inv_d = lsq_ctl_rv0_back_inv; +assign ex0_back_inv_d = rv1_back_inv_q; +assign ex0_back_inv_addr_d = lsq_ctl_rv1_back_inv_addr; +assign ex0_arr_rd_val_d = dcc_dec_arr_rd_rv1_val; +assign ex0_arr_rd_congr_cl_d = dcc_dec_arr_rd_congr_cl; +assign ex0_derat_snoop_val_d = derat_rv1_snoop_val; +assign ex0_derat_snoop_addr_d = derat_dec_rv1_snoop_addr; +assign ex0_non_back_inv_addr = {ex0_derat_snoop_addr_q, ex0_arr_rd_congr_cl_q}; +assign ex0_selimm_addr_val = ex0_back_inv_q | ex0_arr_rd_val_q | ex0_derat_snoop_val_q; +assign ex1_selimm_addr_val_d = ex0_selimm_addr_val; +assign ex1_selimm_addr_d[64-`REAL_IFAR_WIDTH:63-`CL_SIZE] = ex0_back_inv_q ? ex0_back_inv_addr_q : ex0_non_back_inv_addr[64-`REAL_IFAR_WIDTH:63-`CL_SIZE]; +assign ex1_selimm_addr_d[0:64-`REAL_IFAR_WIDTH-1] = ex0_non_back_inv_addr[0:64-`REAL_IFAR_WIDTH-1]; +//---------------------------------------------------------------------------------------------------------------------------------------- +// CP Flush of the Pipeline +//---------------------------------------------------------------------------------------------------------------------------------------- +assign iu_lq_cp_flush_d = iu_lq_cp_flush; +assign rv1_stg_flush = |(rv_lq_vld & iu_lq_cp_flush_q); +assign ex0_stg_flush = |(ex0_tid_q & iu_lq_cp_flush_q); +assign ex1_stg_flush = |(ex1_tid_q & iu_lq_cp_flush_q); +assign ex2_stg_flush = |(ex2_tid_q & iu_lq_cp_flush_q) | byp_dec_ex2_req_aborted; +assign ex3_stg_flush = |(ex3_tid_q & iu_lq_cp_flush_q); +assign ex4_stg_flush = |(ex4_tid_q & iu_lq_cp_flush_q); +//---------------------------------------------------------------------------------------------------------------------------------------- +// Valid/ACT Pipeline +//---------------------------------------------------------------------------------------------------------------------------------------- +assign rv1_vld = |(rv_lq_vld); +assign ex0_vld_d = rv1_vld & ~rv1_stg_flush; +assign ex1_vld_d = ex0_vld_q & ~ex0_stg_flush; +assign ex2_vld_d = ex1_vld_q & ~ex1_stg_flush; +assign ex3_vld_d = ex2_vld_q & ~ex2_stg_flush; +assign ex4_vld_d = ex3_vld_q & ~ex3_stg_flush; +assign ex5_vld_d = ex4_vld_q & ~ex4_stg_flush; +assign ctl_lsq_ex_pipe_full = ex0_vld_q & ex1_vld_q & ex2_vld_q & ex3_vld_q & ex4_vld_q; + +// Execution Pipe ACT Generation +assign ex0_stg_act_d = rv1_vld; +assign ex1_stg_act_d = ex0_stg_act_q; +assign ex2_stg_act_d = ex1_stg_act_q | ex1_use_pfetch; +assign ex3_stg_act_d = ex2_stg_act_q; +assign ex4_stg_act_d = ex3_stg_act_q; +assign ex5_stg_act_d = ex4_stg_act_q; +assign ex5_stg_act = ex5_stg_act_q | stq7_mftgpr_val_q; +assign ex6_stg_act_d = ex5_stg_act; +assign ex7_stg_act_d = ex6_stg_act_q; +assign dec_byp_ex0_stg_act = ex0_stg_act_q; +assign dec_byp_ex1_stg_act = ex1_stg_act_q | ex1_selimm_addr_val_q | ex1_use_pfetch; +assign dec_byp_ex5_stg_act = ex5_stg_act; +assign dec_byp_ex6_stg_act = ex6_stg_act_q; +assign dec_byp_ex7_stg_act = ex7_stg_act_q; + +// Execution Pipe and LSQ Pipe ACT Generation +assign ex0_stq2_stg_act = ex0_stg_act_q | stq2_release_vld_q; +assign ex1_stq3_stg_act = ex1_stg_act_q | stq3_release_vld_q | ex1_use_pfetch; +//---------------------------------------------------------------------------------------------------------------------------------------- +// uCode Pipeline +//---------------------------------------------------------------------------------------------------------------------------------------- +assign ex1_ucode_d = rv_lq_ex0_ucode; +assign ex1_ucode_cnt_d = rv_lq_ex0_ucode_cnt; +//---------------------------------------------------------------------------------------------------------------------------------------- +// Target we/wa controls +//---------------------------------------------------------------------------------------------------------------------------------------- +// Target 1 write enable pipe +assign ex1_t1_we_d = rv_lq_ex0_t1_v & ex1_vld_d; +assign ex2_t1_we_d = ex1_t1_we_q & ex2_vld_d & (au_lq_ex1_ldst_update | (~(ex1_load_instr | ex1_dcm_instr | ex1_is_ditc))); +assign ex3_t1_we_d = ex2_t1_we_q & ex3_vld_d; +assign ex4_t1_we_d = ex3_t1_we_q & ex4_vld_d; +assign ex5_t1_we_d = ex4_t1_we_q & ex5_vld_d; +assign ex5_t1_we = ((ex5_t1_we_q | dcc_dec_ex5_wren) & ex5_vld_q) | stq7_mftgpr_val_q; +assign ex6_t1_we_d = ex5_t1_we; + +// Target 1 controls +generate + if (`THREADS_POOL_ENC == 0) begin : tid1 + assign ex1_t1_wa = ex1_t1_wa_q; + assign unused = |ex1_num_bytes_plus3[6:7] | |au_lq_ex1_ldst_dimm | byp_dec_ex1_s1_abort | byp_dec_ex1_s2_abort; + end +endgenerate + +generate + if (`THREADS_POOL_ENC > 0) begin : tidMulti + reg [0:`THREADS_POOL_ENC] ex1_enc_tid; + always @(*) begin: tidEnc + reg [0:`THREADS_POOL_ENC-1] encEx1; + + //(* analysis_not_referenced="true" *) + + reg [0:31] tid; + encEx1 = {`THREADS_POOL_ENC{1'b0}}; + ex1_enc_tid[`THREADS_POOL_ENC:`THREADS_POOL_ENC] = 1'b0; + for (tid=0; tid<`THREADS; tid=tid+1) begin + encEx1 = (tid[32-`THREADS_POOL_ENC:31] & {`THREADS_POOL_ENC{ex1_tid_q[tid]}}) | encEx1; + end + ex1_enc_tid[0:`THREADS_POOL_ENC - 1] <= encEx1; + end + assign ex1_t1_wa = {ex1_t1_wa_q, ex1_enc_tid[0:`THREADS_POOL_ENC - 1]}; + assign unused = ex1_enc_tid[`THREADS_POOL_ENC:`THREADS_POOL_ENC] | |ex1_num_bytes_plus3[6:7] | |au_lq_ex1_ldst_dimm | + byp_dec_ex1_s1_abort | byp_dec_ex1_s2_abort; + end +endgenerate +assign lq_xu_ex5_act_d = ex4_vld_q | stq6_mftgpr_val_q; +assign lq_xu_ex5_act = lq_xu_ex5_act_q; +assign lq_xu_gpr_ex5_we = ex5_t1_we; +assign lq_rv_gpr_ex6_we = ex6_t1_we_q; + +//---------------------------------------------------------------------------------------------------------------------------------------- +// Dependent op release +//---------------------------------------------------------------------------------------------------------------------------------------- +// LSQ Release ITAG Staging +assign stq1_release_vld = lsq_ctl_stq_release_itag_vld; +assign stq2_release_vld_d = stq1_release_vld; +assign stq3_release_vld_d = stq2_release_vld_q; +assign stq4_release_vld_d = stq3_release_vld_q; +assign stq5_release_vld_d = stq4_release_vld_q; +assign stq6_release_vld_d = stq5_release_vld_q; +assign stq7_release_vld_d = stq6_release_vld_q; + +// Mux in between LSQ Complete and EX0 Instruction, +// There shouldnt be an instruction in EX0 since HOLD_REQ +// was requested by LSQ +assign stq2_release_itag_d = lsq_ctl_stq_release_itag; +assign stq2_release_tid_d = lsq_ctl_stq_release_tid; +assign ex0_iss_stq2_itag = (rv_lq_ex0_itag & {`ITAG_SIZE_ENC{~stq2_release_vld_q}}) | (stq2_release_itag_q & {`ITAG_SIZE_ENC{stq2_release_vld_q}}); +assign ex0_iss_stq2_tid = (ex0_tid_q & {`THREADS{~stq2_release_vld_q}}) | (stq2_release_tid_q & {`THREADS{stq2_release_vld_q}}); + +// Intructions are in correct pipeline stage to allow dependent op release, and they have not been released yet +// adding ex2_needs_release to handle the case where an ABORT was reported instead of instruction in EX1_STQ3 +assign ex1_stq3_sched_release = ex1_needs_release | stq3_needs_release_q | ex1_stq3_needs_release; + +// Pipeline to keep track of instructions that have not been released yet +assign ex0_cpNext_instr = ex0_is_ldawx | ex0_is_larx | ex0_is_stcx | ex0_is_icswxdot | au_lq_ex0_mftgpr; +assign ex0_needs_release_d = rv1_vld & ~rv1_stg_flush; +assign ex0_release_vld = ex0_needs_release_q & ~(ex0_stg_flush | ex0_cpNext_instr); +assign ex0_needs_release = ex0_needs_release_q & ~(ex0_stg_flush | ex0_cpNext_instr) & ex1_stq3_sched_release; +assign ex1_release_attmp_d = ex0_release_vld & ~ex1_stq3_sched_release; +assign ex1_release_attmp = ex1_release_attmp_q & ~ex1_stg_flush; +assign ex1_needs_release_d = ex0_needs_release; +assign ex1_needs_release = ex1_needs_release_q & ~ex1_stg_flush; +assign ex2_needs_release_d = ex1_needs_release; +assign ex2_needs_release = ex2_abort_sel_val & ~(|(ex2_tid_q & iu_lq_cp_flush_q)); +assign stq2_needs_release = stq2_release_vld_q & ex1_stq3_sched_release; +assign stq3_release_attmp_d = stq2_release_vld_q & ~ex1_stq3_sched_release; +assign stq3_needs_release_d = stq2_needs_release; +assign ex1_stq3_needs_release = (stq3_release_attmp_q | ex1_needs_release | ex1_release_attmp) & ex2_needs_release; + +// Use prioritized schedule to determine which stage to release itag/vld out of (Will be latched) +assign release_itag_d = (ex0_iss_stq2_itag & {`ITAG_SIZE_ENC{~ex1_stq3_sched_release}}) | (ex1_itag_q & {`ITAG_SIZE_ENC{ex1_stq3_sched_release}}); +assign release_itag_vld_d = ((ex0_release_vld | stq2_release_vld_q) & (~ex1_stq3_sched_release)) | ex1_stq3_sched_release; +assign release_tid_d = (ex0_iss_stq2_tid & {`THREADS{~ex1_stq3_sched_release}}) | (ex1_tid_q & {`THREADS{ex1_stq3_sched_release}}); + +// Abort Pipeline Request that updates a physical speculatively, +// Needs to have a separate ex2_stg_flush to remove the ex2_req_abort from the flush gen +// LARX is removed from the equation because it doesnt release +// a dependent instruction speculativevly +assign ex2_physical_upd_d = (ex1_load_instr & ~ex1_resv_instr) | (au_lq_ex1_mffgpr & ~au_lq_ex1_movedp) | ex1_st_w_update; +assign ex2_req_abort_rpt = byp_dec_ex2_req_aborted & ex2_vld_q & ex2_physical_upd_q; +assign ex3_req_abort_rpt_d = ex2_req_abort_rpt & ~(|(ex2_tid_q & iu_lq_cp_flush_q)); +assign ex4_req_abort_rpt_d = ex3_req_abort_rpt_q & ~ex3_stg_flush; +assign ex5_req_abort_rpt_d = ex4_req_abort_rpt_q & ~ex4_stg_flush; + +// Abort AXU Pipeline Request that updates an AXU physical speculatively, +// Needs to have a separate ex2_stg_flush to remove the ex2_req_abort from the flush gen +// Dont want to set if the instruction is a preIssue of an AXU instruction +assign ex2_axu_physical_upd_d = ((au_lq_ex1_ldst_v & ex1_load_instr) | (au_lq_ex1_mffgpr & ~au_lq_ex1_movedp)) & ~ex1_ucode_q[1]; +assign ex2_axu_abort_rpt = ex2_vld_q & ex2_axu_physical_upd_q; +assign ex3_axu_abort_rpt_d = ex2_axu_abort_rpt & ~(|(ex2_tid_q & iu_lq_cp_flush_q)); +assign ex4_axu_abort_rpt_d = ex3_axu_abort_rpt_q & ~ex3_stg_flush; +assign ex5_axu_abort_rpt_d = ex4_axu_abort_rpt_q & ~ex4_stg_flush; + +//---------------------------------------------------------------------------------------------------------------------------------------- +// RV Completion +//---------------------------------------------------------------------------------------------------------------------------------------- +assign ex2_abort_sel_val = byp_dec_ex2_req_aborted & ex2_vld_q & ~ex2_needs_release_q; +assign lq_rel_itag0_val = release_itag_vld_q | ex2_abort_sel_val; +assign lq_rel_itag0_itag = (release_itag_q & {`ITAG_SIZE_ENC{~ex2_abort_sel_val}}) | (ex2_itag_q & {`ITAG_SIZE_ENC{ex2_abort_sel_val}}); +assign lq_rel_itag0_tid = (release_tid_q & { `THREADS{~ex2_abort_sel_val}}) | (ex2_tid_q & { `THREADS{ex2_abort_sel_val}}); +assign lq_rel_itag0_abort = byp_dec_ex2_req_aborted & ex2_vld_q; +assign lq_rv_itag0_vld = lq_rel_itag0_tid & {`THREADS{lq_rel_itag0_val}}; +assign lq_rv_itag0 = lq_rel_itag0_itag; +assign lq_rv_itag0_abort = lq_rel_itag0_abort; + +//---------------------------------------------------------------------------------------------------------------------------------------- +// IU Completion +//---------------------------------------------------------------------------------------------------------------------------------------- +//---------------------------------------------------------------------------------------------------------------------------------------- +// GPR Source 0 +//---------------------------------------------------------------------------------------------------------------------------------------- +// Regular XU ops +assign ex1_gpr0_zero_reg_op = (~ex1_s1_vld_q); + +// AXU and Not Indexed Op +assign ex1_gpr0_zero_axu_op = au_lq_ex1_ldst_v & (~(ex1_s1_vld_q | au_lq_ex1_mftgpr | au_lq_ex1_mffgpr)); + +// Other ops that need this zeroed +assign ex1_gpr0_zero_other = ex1_is_msgsnd; +assign ex1_gpr0_zero = ex1_gpr0_zero_reg_op | ex1_gpr0_zero_axu_op | ex1_gpr0_zero_other | ex1_selimm_addr_val_q | ex1_use_pfetch; +assign dec_byp_ex1_rs1_zero = ex1_gpr0_zero; + +//---------------------------------------------------------------------------------------------------------------------------------------- +// Immediate Logic +//---------------------------------------------------------------------------------------------------------------------------------------- +// Determine what ops use immediate: +// Branches, Arith/Logical/Other Immediate forms, Loads/Stores, SPR Instructions +assign ex1_use_imm = ex1_is_lbz | ex1_is_ld | ex1_is_lha | ex1_is_lhz | ex1_is_lwa | ex1_is_lwz | + ex1_is_lhzu | ex1_is_lhau | ex1_is_lwzu | ex1_is_lbzu | ex1_is_lmw | + ex1_is_stb | ex1_is_std | ex1_is_sth | ex1_is_stw | ex1_is_stbu | ex1_is_sthu | + ex1_is_stwu | ex1_is_stdu | ex1_is_stmw | ex1_is_ldu | ex1_is_stswi | ex1_is_lswi | + ex1_mtspr_trace | + (au_lq_ex1_ldst_v & (~(au_lq_ex1_ldst_indexed | au_lq_ex1_mftgpr | au_lq_ex1_mffgpr))); + +// Determine ops that use 15 bit immediate +assign ex1_imm_size = ex1_is_lbz | ex1_is_lbzu | ex1_is_lhz | ex1_is_lhzu | ex1_is_lha | ex1_is_lhau | + ex1_is_lwz | ex1_is_lwzu | ex1_is_lwa | ex1_is_ld | ex1_is_ldu | ex1_is_lmw | + ex1_is_stb | ex1_is_sth | ex1_is_stw | ex1_is_stbu | ex1_is_sthu | ex1_is_stwu | + ex1_is_stdu | ex1_is_std | ex1_is_stmw | + (au_lq_ex1_ldst_v & (~au_lq_ex1_ldst_indexed)); + +// Determine ops that use sign-extended immediate +assign ex1_imm_signext = ex1_is_lbz | ex1_is_lbzu | ex1_is_lhz | ex1_is_lhzu | ex1_is_lha | ex1_is_lhau | + ex1_is_lwz | ex1_is_lwzu | ex1_is_lwa | ex1_is_ld | ex1_is_ldu | ex1_is_lmw | + ex1_is_stb | ex1_is_sth | ex1_is_stw | ex1_is_stbu | ex1_is_sthu | ex1_is_stwu | + ex1_is_stdu | ex1_is_std | ex1_is_stmw | + (au_lq_ex1_ldst_v & (~au_lq_ex1_ldst_indexed)); + +// Immediate should be zeroed +assign ex1_zero_imm = ex1_is_stswi | ex1_is_lswi | ex1_mtspr_trace; + +// Some ops need lower two bits of immediate tied down +assign ex1_16b_imm = ~(ex1_is_std | ex1_is_stdu | ex1_is_lwa | ex1_is_ld | ex1_is_ldu) ? ex1_instr_q[16:31] : {ex1_instr_q[16:29], {2{tidn}}}; +assign ex1_64b_imm = ex1_selimm_addr_val_q ? {ex1_selimm_addr_q, {`CL_SIZE{1'b0}}} : {{38{1'b0}}, ex1_instr_q[6:31]}; +assign ex1_imm_sign_ext = ({(ex1_imm_size & (~ex1_selimm_addr_val_q)), ex1_imm_signext} == 2'b11) ? {{48{ex1_16b_imm[0]}}, ex1_16b_imm} : + ({(ex1_imm_size & (~ex1_selimm_addr_val_q)), ex1_imm_signext} == 2'b10) ? {{48{ 1'b0}}, ex1_16b_imm} : + ex1_64b_imm; +// prefetch +// removed mm_hold_req_q because it would lead to a deadlock +// the pfetch will not be quiesced because we block all pfetches +// while the mmu requests a hold, but the mmu waits for quiesce +// before executing +assign ex1_pfetch_rel_collision = dir_dec_rel3_dir_wr_val & (dir_dec_rel3_dir_wr_addr == pf_dec_req_addr[64-(`DC_SIZE-3):63-`CL_SIZE]); +assign ex1_use_pfetch = pf_dec_req_val & ~ex1_vld_q & ~ex1_selimm_addr_val_q & ~lsq_ctl_sync_in_stq & ~ex1_hold_taken_q & ~ex1_pfetch_rel_collision & ~dcc_dec_stq3_mftgpr_val; +assign dec_pf_ack = ex1_use_pfetch; + +assign dec_byp_ex1_imm = ~ex1_use_pfetch ? (ex1_imm_sign_ext[64-(2**`GPR_WIDTH_ENC):63] & {2**`GPR_WIDTH_ENC{~ex1_zero_imm}}) : + {pf_dec_req_addr, {`CL_SIZE{1'b0}}}; +assign dec_byp_ex1_use_imm = ex1_use_imm | ex1_selimm_addr_val_q | ex1_use_pfetch; +assign dec_byp_ex1_s1_vld = ex1_s1_vld_q & ex1_vld_q; +assign dec_byp_ex1_s2_vld = ex1_s2_vld_q & ex1_vld_q; +assign ex1_tid = ~ex1_use_pfetch ? ex1_tid_q : pf_dec_req_thrd; +//------------------------------------------------------------------- +// DITC Control Logic +//------------------------------------------------------------------- +//------------------------------------------------------------------- +// LSU Control Logic +//------------------------------------------------------------------- +assign ex1_priv_prog_excp = ex1_instr_priv & ex1_vld_q & spr_msr_pr; +assign ex1_hypv_prog_excp = ex1_instr_hypv & ex1_vld_q & (spr_msr_pr | spr_msr_gs); +assign ex1_illeg_prog_excp = ex1_vld_q & ex1_illeg_instr; +assign ex1_dlock_dstor_excp = ex1_vld_q & ex1_dlock_dstor; +assign ex1_ilock_dstor_excp = ex1_vld_q & ex1_ilock_dstor; +assign ex1_ehpriv_excp = ex1_vld_q & ex1_instr_ehpriv; +assign dec_spr_ex1_valid = ex1_tid_q & {`THREADS{ex1_vld_q}}; +assign dec_dcc_ex1_expt_det = ex1_priv_prog_excp | ex1_hypv_prog_excp | ex1_illeg_prog_excp | ex1_dlock_dstor_excp | ex1_ilock_dstor_excp | ex1_ehpriv_excp; +assign dec_dcc_ex1_priv_prog = ex1_priv_prog_excp; +assign dec_dcc_ex1_hypv_prog = ex1_hypv_prog_excp; +assign dec_dcc_ex1_illeg_prog = ex1_illeg_prog_excp; +assign dec_dcc_ex1_dlock_excp = ex1_dlock_dstor_excp; +assign dec_dcc_ex1_ilock_excp = ex1_ilock_dstor_excp; +assign dec_dcc_ex1_ehpriv_excp = ex1_ehpriv_excp; +assign dec_dcc_ex1_ucode_val = ex1_vld_q & ex1_ucode_q[1]; +assign dec_dcc_ex1_ucode_cnt = ex1_ucode_cnt_q; +assign dec_dcc_ex1_ucode_op = ex1_ucode_q[0]; +assign dec_dcc_ex1_sfx_val = ex1_vld_q & (~(ex1_cache_acc | ex1_ucode_q[1])); +assign dec_dcc_ex1_cache_acc = ex1_cache_acc & (~(ex1_ucode_q[1] | ex1_illeg_icswx)); +assign dec_dcc_ex1_thrd_id = ex1_tid; +assign dec_dcc_ex1_instr = ex1_instr_q; + +assign ex1_axu_sel_target = (au_lq_ex1_ldst_v | au_lq_ex1_mffgpr) & (~(au_lq_ex1_mftgpr | ex1_axu_st_update)); +assign dec_dcc_ex1_target_gpr[AXU_TARGET_ENC-(`GPR_POOL_ENC+`THREADS_POOL_ENC):AXU_TARGET_ENC-1] = ex1_axu_sel_target ? au_lq_ex1_ldst_tag[AXU_TARGET_ENC-(`GPR_POOL_ENC+`THREADS_POOL_ENC):AXU_TARGET_ENC-1] : ex1_t1_wa; + +generate + if (`AXU_SPARE_ENC > 0) begin : axuSpare + assign dec_dcc_ex1_target_gpr[0:AXU_TARGET_ENC-(`GPR_POOL_ENC+`THREADS_POOL_ENC)-1] = au_lq_ex1_ldst_tag[0:AXU_TARGET_ENC-(`GPR_POOL_ENC+`THREADS_POOL_ENC)-1]; + end +endgenerate + +assign dec_dcc_ex1_cmd_act = ex1_cmd_act | (ex1_vld_q & ex1_ucode_q[1]) | ex1_use_pfetch | ex1_selimm_addr_val_q; +assign dec_dcc_ex1_upd_form = (au_lq_ex1_ldst_v & au_lq_ex1_ldst_update) | ((~au_lq_ex1_ldst_v) & ex1_fxu_st_update); +assign dec_dcc_ex1_mtspr_trace = ex1_mtspr_trace; +assign dec_dcc_ex1_is_msgsnd = ex1_is_msgsnd & spr_ccr2_en_pc_q; +assign dec_dcc_ex1_load_instr = ex1_load_instr; +assign dec_dcc_ex1_dcbf_instr = (ex1_is_dcbf | ex1_is_dcbfep); +assign dec_dcc_ex1_l_fld = ex1_instr_q[9:10]; +assign dec_dcc_ex1_dcbi_instr = ex1_is_dcbi; +assign dec_dcc_ex1_dcbz_instr = (ex1_is_dcbz | ex1_is_dcbzep); +assign dec_dcc_ex1_dcbt_instr = (ex1_is_dcbt | ex1_is_dcbtep); +assign dec_dcc_ex1_pfetch_val = ex1_use_pfetch; +assign dec_dcc_ex1_dcbtst_instr = (ex1_is_dcbtst | ex1_is_dcbtstep); +assign dec_dcc_ex1_th_fld = ~ex1_use_pfetch ? {ex1_th_fld_b6, ex1_instr_q[7:10]} : 5'b00000; +assign dec_dcc_ex1_dcbtls_instr = ex1_is_dcbtls; +assign dec_dcc_ex1_dcbtstls_instr = ex1_is_dcbtstls; +assign dec_dcc_ex1_dcblc_instr = ex1_is_dcblc; +assign dec_dcc_ex1_dci_instr = ex1_is_dci & ex1_vld_q; +assign dec_dcc_ex1_dcbst_instr = (ex1_is_dcbst | ex1_is_dcbstep); +assign dec_dcc_ex1_icbi_instr = (ex1_is_icbi | ex1_is_icbiep); +assign dec_dcc_ex1_ici_instr = ex1_is_ici & ex1_vld_q; +assign dec_dcc_ex1_icblc_instr = ex1_is_icblc; +assign dec_dcc_ex1_icbt_instr = ex1_is_icbt; +assign dec_dcc_ex1_icbtls_instr = ex1_is_icbtls; +assign dec_dcc_ex1_resv_instr = ex1_resv_instr; +assign dec_dcc_ex1_cr_fld = ex1_t3_wa_q[`GPR_POOL_ENC - `CR_POOL_ENC:`GPR_POOL_ENC - 1]; +assign dec_dcc_ex1_mutex_hint = ex1_instr_q[31]; +assign dec_dcc_ex1_axu_op_val = au_lq_ex1_ldst_v; +assign dec_dcc_ex1_axu_falign = au_lq_ex1_ldst_forcealign; +assign dec_dcc_ex1_axu_fexcpt = au_lq_ex1_ldst_forceexcept; +assign dec_dcc_ex1_axu_instr_type = au_lq_ex1_instr_type; +assign dec_derat_ex1_byte_rev = ex1_is_lhbrx | ex1_is_lwbrx | ex1_is_ldbrx | ex1_is_sthbrx | ex1_is_stwbrx | ex1_is_stdbrx; +assign dec_derat_ex1_ra_eq_ea = ex1_selimm_addr_val_q | ex1_is_msgsnd | ex1_mtspr_trace; +assign dec_derat_ex1_derat_act = ex1_derat_act | (ex1_vld_q & ex1_ucode_q[1]) | ex1_wclr_one_val | ex1_use_pfetch; +assign dec_derat_ex1_pfetch_val = ex1_tid & {`THREADS{ex1_use_pfetch}}; +assign dec_dcc_ex5_req_abort_rpt = ex5_req_abort_rpt_q; +assign dec_dcc_ex5_axu_abort_rpt = ex5_axu_abort_rpt_q; + +assign dec_dir_ex2_dir_rd_act = ex2_dir_rd_act_q; +assign ex0_derat_is_extload = ex0_is_lbepx | ex0_is_lhepx | ex0_is_lwepx | ex0_is_ldepx | ex0_is_dcbfep | ex0_is_dcbtep | ex0_is_dcbstep | ex0_is_icbiep | au_lq_ex0_extload; +assign dec_derat_ex0_is_extload = ex0_derat_is_extload; +assign dec_derat_ex0_val = ex0_tid_q & {`THREADS{ex0_vld_q}}; +assign ex0_derat_is_extstore = ex0_is_dcbzep | ex0_is_stbepx | ex0_is_sthepx | ex0_is_stwepx | ex0_is_stdepx | ex0_is_dcbtstep | ex0_is_icswepx | au_lq_ex0_extstore; +assign dec_derat_ex0_is_extstore = ex0_derat_is_extstore; + +assign ex1_th_fld_b6 = ex1_instr_q[6] & (ex1_is_dcbt | ex1_is_dcbtep | ex1_is_dcbtst | ex1_is_dcbtstep); +assign ex1_th_fld_c = ~ex1_th_fld_b6 & (ex1_instr_q[7:10] == 4'b0000); +assign ex1_th_fld_l2 = ~ex1_th_fld_b6 & (ex1_instr_q[7:10] == 4'b0010); +assign dec_derat_ex1_is_touch = ex1_is_dcbt | ex1_is_dcbtep | ex1_is_dcbtst | ex1_is_dcbtstep | ex1_is_icbt | + ((ex1_is_dcbtls | ex1_is_dcbtstls | ex1_is_dcblc) & (~(ex1_th_fld_c | ex1_th_fld_l2))) | + ((ex1_is_icbtls | ex1_is_icblc) & (~(ex1_th_fld_c | ex1_th_fld_l2))); + +assign dec_dcc_ex1_mword_instr = ex1_is_lmw | ex1_is_stmw; +assign dec_dcc_ex1_icswx_instr = ex1_is_icswx | ex1_is_icswepx; +assign dec_dcc_ex1_icswxdot_instr = (ex1_is_icswx | ex1_is_icswepx) & ex1_instr_q[31]; +assign dec_dcc_ex1_icswx_epid = ex1_is_icswepx; +assign dec_dcc_ex1_itag = ex1_itag; +assign dec_dcc_ex2_rotsel_ovrd = au_lq_ex1_ldst_size[1:5]; +assign dec_dcc_ex3_mtdp_val = tidn; +assign dec_dcc_ex3_mfdp_val = tidn; +assign dec_dcc_ex3_ipc_ba = {5{1'b0}}; +assign dec_dcc_ex3_ipc_sz = {2{1'b0}}; + +assign ex1_itag = ex1_use_pfetch ? 7'b0111111 : ex1_itag_q; + +assign ex2_is_any_load_dac_d = ex1_is_any_load_dac; +assign ex2_is_any_store_dac_d = ex1_is_any_store_dac; +assign dec_ex2_is_any_load_dac = ex2_is_any_load_dac_q; +assign dec_ex2_is_any_store_dac = ex2_is_any_store_dac_q; +assign ex2_dir_rd_act_d = ex1_dir_rd_act | ex1_use_pfetch | ex1_selimm_addr_val_q; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Instruction Decode +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +assign ex1_instr_d = ex1_vld_d ? rv_lq_ex0_instr : 32'h7C00022C; + +//---------------------------------------------------------------------------------------------------------------------------------------- +// AXU Load/Store Instruction Decode +//---------------------------------------------------------------------------------------------------------------------------------------- + +lq_axu_dec axu( + .lq_au_ex0_instr(rv_lq_ex0_instr), + .lq_au_ex1_vld(ex1_vld_q), + .lq_au_ex1_tid(ex1_tid_q), + .lq_au_ex1_instr(ex1_instr_q), + .lq_au_ex1_t3_p(ex1_t3_wa_q), + .au_lq_ex0_extload(au_lq_ex0_extload), + .au_lq_ex0_extstore(au_lq_ex0_extstore), + .au_lq_ex0_mftgpr(au_lq_ex0_mftgpr), + .au_lq_ex1_ldst_v(au_lq_ex1_ldst_v), + .au_lq_ex1_st_v(au_lq_ex1_st_v), + .au_lq_ex1_ldst_size(au_lq_ex1_ldst_size), + .au_lq_ex1_ldst_update(au_lq_ex1_ldst_update), + .au_lq_ex1_mftgpr(au_lq_ex1_mftgpr), + .au_lq_ex1_mffgpr(au_lq_ex1_mffgpr), + .au_lq_ex1_movedp(au_lq_ex1_movedp), + .au_lq_ex1_ldst_tag(au_lq_ex1_ldst_tag), + .au_lq_ex1_ldst_dimm(au_lq_ex1_ldst_dimm), + .au_lq_ex1_ldst_indexed(au_lq_ex1_ldst_indexed), + .au_lq_ex1_ldst_forcealign(au_lq_ex1_ldst_forcealign), + .au_lq_ex1_ldst_forceexcept(au_lq_ex1_ldst_forceexcept), + .au_lq_ex1_ldst_priv(au_lq_ex1_ldst_priv), + .au_lq_ex1_instr_type(au_lq_ex1_instr_type) +); + +//---------------------------------------------------------------------------------------------------------------------------------------- +// Illegal ops +//---------------------------------------------------------------------------------------------------------------------------------------- +assign ex1_instr_priv = ex1_is_dcbfep | ex1_is_dcbi | ex1_is_dcbstep | ex1_is_dcbtep | ex1_is_dcbtstep | ex1_is_dcbzep | ex1_is_dci | ex1_is_icbiep | + ex1_is_ici | ex1_is_icswepx | ex1_is_lbepx | ex1_is_ldepx | ex1_is_lhepx | ex1_is_lwepx | ex1_is_mfdp | ex1_is_mfdpx | + ex1_is_msgsnd | ex1_is_mtdp | ex1_is_mtdpx | ex1_is_stbepx | ex1_is_stdepx | ex1_is_sthepx | ex1_is_stwepx | ex1_is_tlbsync | au_lq_ex1_ldst_priv; +assign ex1_instr_hypv = ex1_is_msgsnd | ex1_is_tlbsync; +assign ex1_dlk_dstor_cond0 = spr_msrp_uclep & spr_msr_gs & spr_msr_pr; +assign ex1_dlk_dstor_cond1 = (~spr_msr_ucle) & (~spr_msrp_uclep) & spr_msr_pr; +assign ex1_dlk_dstor_cond2 = (~spr_msr_ucle) & (~spr_msr_gs) & spr_msr_pr; +assign ex1_dlock_dstor = (ex1_is_dcbtls | ex1_is_dcbtstls | ex1_is_dcblc) & (ex1_dlk_dstor_cond0 | ex1_dlk_dstor_cond1 | ex1_dlk_dstor_cond2); +assign ex1_ilock_dstor = (ex1_is_icbtls | ex1_is_icblc) & (ex1_dlk_dstor_cond0 | ex1_dlk_dstor_cond1 | ex1_dlk_dstor_cond2); +assign ex1_instr_ehpriv = (ex1_is_dcbtls | ex1_is_dcbtstls | ex1_is_dcblc | ex1_is_icbtls | ex1_is_icblc) & spr_msrp_uclep & spr_msr_gs & (~spr_msr_pr); +assign ex1_illeg_msgsnd = ex1_is_msgsnd & (~spr_ccr2_en_pc_q); +assign ex1_illeg_ditc = ex1_is_ditc & (~spr_ccr2_en_ditc_q); +assign ex1_illeg_icswx = (ex1_is_icswx | ex1_is_icswepx) & (~spr_ccr2_en_icswx_q); +assign ex1_illeg_instr = ex1_illeg_msgsnd | ex1_illeg_ditc | ex1_illeg_icswx | ex1_illeg_lswi | ex1_illeg_lmw | ex1_illeg_upd_form; + +// Load/Store Update Form Instruction Decode +// Load with Update Valid +assign ex1_fxu_ld_update = ex1_is_lbzu | ex1_is_lbzux | ex1_is_ldu | ex1_is_ldux | ex1_is_lhau | ex1_is_lhaux | + ex1_is_lhzu | ex1_is_lhzux | ex1_is_lwaux | ex1_is_lwzu | ex1_is_lwzux; +assign ex1_axu_ld_update = (~au_lq_ex1_st_v) & au_lq_ex1_ldst_update; +assign ex1_ld_w_update = au_lq_ex1_ldst_v ? ex1_axu_ld_update : ex1_fxu_ld_update; + +// Store with Update Valid +assign ex1_fxu_st_update = ex1_is_stbu | ex1_is_stbux | ex1_is_stdu | ex1_is_stdux | ex1_is_sthu | ex1_is_sthux | + ex1_is_stwu | ex1_is_stwux; +assign ex1_axu_st_update = au_lq_ex1_st_v & au_lq_ex1_ldst_update; +assign ex1_st_w_update = au_lq_ex1_ldst_v ? ex1_axu_st_update : ex1_fxu_st_update; +assign ex1_ra_eq_zero = (ex1_instr_q[11:15] == 5'b00000); +assign ex1_ra_eq_rt = (ex1_instr_q[11:15] == ex1_instr_q[6:10]) & (~au_lq_ex1_ldst_v); +assign ex1_illeg_upd_form = (ex1_ld_w_update & (ex1_ra_eq_zero | ex1_ra_eq_rt)) | (ex1_st_w_update & ex1_ra_eq_zero); + +// Illegal forms of LSWI and LMW +assign ex1_num_bytes = {2'b00, (~(|ex1_instr_q[16:20])), ex1_instr_q[16:20]}; +assign ex1_num_bytes_plus3 = ex1_num_bytes + 8'b00000011; +assign ex1_num_regs = ex1_num_bytes_plus3[0:5]; +assign ex1_lower_bnd = {1'b0, ex1_instr_q[6:10]}; +assign ex1_upper_bnd = ex1_lower_bnd + ex1_num_regs; +assign ex1_upper_bnd_wrap = {1'b0, ex1_upper_bnd[1:5]}; +assign ex1_range_wrap = ex1_upper_bnd[0]; +assign ex1_ra_in_rng_lmw = ({1'b0, ex1_instr_q[11:15]}) >= ex1_lower_bnd; + +// RA in range +assign ex1_ra_in_rng_nowrap = (({1'b0, ex1_instr_q[11:15]}) >= ex1_lower_bnd) & + (({1'b0, ex1_instr_q[11:15]}) < ex1_upper_bnd); +assign ex1_ra_in_rng_wrap = (({1'b0, ex1_instr_q[11:15]}) < ex1_upper_bnd_wrap); +assign ex1_ra_in_rng = (ex1_ra_in_rng_nowrap) | (ex1_ra_in_rng_wrap & ex1_range_wrap); +assign ex1_illeg_lswi = ex1_is_lswi & ex1_ra_in_rng; +assign ex1_illeg_lmw = ex1_is_lmw & ex1_ra_in_rng_lmw; + +//---------------------------------------------------------------------------------------------------------------------------------------- +// FXU Instruction Decode +//---------------------------------------------------------------------------------------------------------------------------------------- +// +// Final Table Listing +// *INPUTS*==================================================*OUTPUTS*============================================* +// | | | +// | ex1_instr_q | ex1_cache_acc | +// | | ex1_instr_q | | ex1_is_msgsnd | +// | | | ex1_instr_q | | | dec_dcc_ex1_mbar_instr | +// | | | | ex1_instr_q | | | | dec_dcc_ex1_sync_instr | +// | | | | | au_lq_ex1_ldst_v | | | | | dec_dcc_ex1_makeitso_instr | +// | | | | | | au_lq_ex1_mftgpr | | | | | | dec_dcc_ex1_tlbsync_instr | +// | | | | | | | au_lq_ex1_mffgpr | | | | | | | dec_dcc_ex1_wclr_instr | +// | | | | | | | | au_lq_ex1_movedp | | | | | | | | dec_dcc_ex1_wchk_instr | +// | | | | | | | | | ex1_vld_q | | | | | | | | | dec_dcc_ex1_src_gpr | +// | | | | | | | | | | | | | | | | | | | | dec_dcc_ex1_src_axu | +// | | | | | | | | | | | | | | | | | | | | | dec_dcc_ex1_src_dp | +// | | | | | | | | | | | | | | | | | | | | | | dec_dcc_ex1_targ_gpr | +// | | | | | | | | | | | | | | | | | | | | | | | dec_dcc_ex1_targ_axu | +// | | | | | | | | | | | | | | | | | | | | | | | | dec_dcc_ex1_targ_dp | +// | | | | | | | | | | | | | | | | | | | | | | | | | ex1_cmd_act | +// | | | | | | | | | | | | | | | | | | | | | | | | | | ctl_dat_ex1_data_act | +// | | | | | | | | | | | | | | | | | | | | | | | | | | | ex1_mtspr_trace | +// | | | | | | | | | | | | | | | | | | | | | | | | | | | | ex1_derat_act | +// | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ex1_dir_rd_act | +// | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | +// | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | +// | 000000 1111111112 2222222223 33 | | | | | | | | | | | | | | | | | | | | | | | | | | +// | 012345 1234567890 1234567890 01 | | | | | | | | | | | | | | | | | | | | | | | | | | +// *TYPE*====================================================+====================================================+ +// | PPPPPP PPPPPPPPPP PPPPPPPPPP PP P P P P P | P P P P P P P P P P P P P P P P P P P | +// *POLARITY*----------------------------------------------->| + + + + + + + + + + + + + + + + + + + | +// *PHASE*-------------------------------------------------->| T T T T T T T T T T T T T T T T T T T | +// *TERMS*===================================================+====================================================+ +// 1 | 011111 0111011111 0111010011 -- - - - - 1 | . . . . . . . . . . . . . . 1 . 1 . . | +// 2 | 011111 ---------- 0000-00011 -- - - - 0 1 | . . . . . . . . . . . 1 . . . . . . . | +// 3 | 011111 ---------- 1110000110 -- - - - - 1 | . . . . . . . 1 . . . . . . . . . . . | +// 4 | 011111 ---------- 0011111111 -- - - - - 1 | . . . . . . . . . . . . . . . . . . 1 | +// 5 | 011111 ---------- 0011001110 -- - - - - 1 | . 1 . . . . . . . . . . . . 1 . . . . | +// 6 | 011111 ---------- 0000110010 -- - - - - 1 | . . . . 1 . . . . . . . . . 1 . . . . | +// 7 | 011111 ---------- 1101010110 -- - - - - 1 | . . 1 . . . . . . . . . . . 1 . . . . | +// 8 | 011111 ---------- 1110100110 -- - - - - 1 | 1 . . . . . 1 . . . . . . . 1 . . . . | +// 9 | 011111 ---------- 1000110110 -- - - - - 1 | . . . . . 1 . . . . . . . . 1 . . . . | +// 10 | 011111 ---------- 1001010110 -- - - - - 1 | . . . 1 . . . . . . . . . . 1 . . . . | +// 11 | 011111 ---------- 0001-00011 -- - - - - 1 | . . . . . . . . 1 . . . . 1 1 1 . . . | +// 12 | 011111 ---------- 0000-00011 -- - - - - 1 | . . . . . . . . . . 1 . . . 1 1 . . . | +// 13 | 011111 ---------- 10000101-0 -- - - - - 1 | . . . . . . . . . . . . . . . 1 . . 1 | +// 14 | 011111 ---------- 0-0001-111 -- - - - - 1 | . . . . . . . . . . . . . . . 1 . . . | +// 15 | 011111 ---------- 000001-1-1 -- - - - - 1 | . . . . . . . . . . . . . . . 1 . . 1 | +// 16 | 011111 ---------- 1111-11111 -- - - - - 1 | 1 . . . . . . . . . . . . . 1 . . 1 . | +// 17 | 011111 ---------- 000-01-111 -- - - - - 1 | . . . . . . . . . . . . . . . 1 . . 1 | +// 18 | 011111 ---------- 0-11100110 -- - - - - 1 | 1 . . . . . . . . . . . . . 1 . . 1 . | +// 19 | 011111 ---------- 0011110110 -- - - - - 1 | 1 . . . . . . . . . . . . . 1 . . 1 1 | +// 20 | 011111 ---------- -11-0-0110 -- - - - - 1 | . . . . . . . . . . . . . . 1 . . . . | +// 21 | 011111 ---------- 0-100-0110 -- - - - - 1 | 1 . . . . . . . . . . . . . . . . 1 . | +// 22 | 011111 ---------- 0100-11111 -- - - - - 1 | 1 . . . . . . . . . . . . . 1 . . 1 1 | +// 23 | 011111 ---------- 0010-00110 -- - - - - 1 | 1 . . . . . . . . . . . . . 1 . . 1 1 | +// 24 | 011111 ---------- 00-1010100 -- - - - - 1 | 1 . . . . . . . . . . . . . 1 1 . 1 1 | +// 25 | 011111 ---------- 01010101-1 -- - - - - 1 | 1 . . . . . . . . . . . . . 1 1 . 1 1 | +// 26 | 011111 ---------- 111--10110 -- - - - - 1 | 1 . . . . . . . . . . . . . 1 . . 1 . | +// 27 | 011111 ---------- 000--11111 -- - - - - 1 | 1 . . . . . . . . . . . . . 1 . . 1 . | +// 28 | 011111 ---------- 010001011- -- - - - - 1 | 1 . . . . . . . . . . . . . 1 . . 1 1 | +// 29 | 011111 ---------- 10-00101-0 -- - - - - 1 | 1 . . . . . . . . . . . . . 1 . . 1 . | +// 30 | 011111 ---------- 0011-1-111 -- - - - - 1 | 1 . . . . . . . . . . . . . 1 . . 1 . | +// 31 | 011111 ---------- 1-00010110 -- - - - - 1 | 1 . . . . . . . . . . . . . 1 1 . 1 1 | +// 32 | 011111 ---------- 1-10-10110 -- - - - - 1 | 1 . . . . . . . . . . . . . 1 . . 1 . | +// 33 | 011111 ---------- 0010-101-1 -- - - - - 1 | 1 . . . . . . . . . . . . . 1 . . 1 . | +// 34 | 011111 ---------- 0000-101-0 -- - - - - 1 | 1 . . . . . . . . . . . . . 1 . . 1 . | +// 35 | 011111 ---------- 0-10-10111 -- - - - - 1 | 1 . . . . . . . . . . . . . 1 . . 1 . | +// 36 | 011111 ---------- 000--10100 -- - - - - 1 | 1 . . . . . . . . . . . . . 1 1 . 1 1 | +// 37 | 011111 ---------- 00-001-1-1 -- - - - - 1 | 1 . . . . . . . . . . . . . 1 . . 1 . | +// 38 | 011111 ---------- 0--001-111 -- - - - - 1 | 1 . . . . . . . . . . . . . 1 . . 1 . | +// 39 | 011111 ---------- --1-010110 -- - - - - 1 | 1 . . . . . . . . . . . . . 1 . . 1 . | +// 40 | 011111 ---------- 00--01011- -- - - - - 1 | 1 . . . . . . . . . . . . . 1 . . 1 . | +// 41 | 1-1010 ---------- ---------- -0 - - - - 1 | 1 . . . . . . . . . . . . . 1 1 . 1 1 | +// 42 | 111110 ---------- ---------- 0- - - - - 1 | 1 . . . . . . . . . . . . . 1 . . 1 . | +// 43 | ------ ---------- ---------- -- 1 0 0 0 1 | 1 . . . . . . . . . . . . . 1 1 . 1 1 | +// 44 | 10-0-0 ---------- ---------- -- - - - - 1 | 1 . . . . . . . . . . . . . 1 1 . 1 1 | +// 45 | ------ ---------- ---------- -- - - 1 1 1 | . . . . . . . . . . 1 . 1 . 1 . . . . | +// 46 | ------ ---------- ---------- -- - 1 - 1 1 | . . . . . . . . . 1 . . . 1 1 . . . . | +// 47 | ------ ---------- ---------- -- - 1 - 0 1 | . . . . . . . . . 1 . 1 . . 1 . . . . | +// 48 | ------ ---------- ---------- -- - - 1 0 1 | . . . . . . . . 1 . . . 1 . 1 . . . . | +// 49 | 10-10- ---------- ---------- -- - - - - 1 | 1 . . . . . . . . . . . . . 1 . . 1 . | +// 50 | 1001-- ---------- ---------- -- - - - - 1 | 1 . . . . . . . . . . . . . 1 . . 1 . | +// *==============================================================================================================* +// +// Table TBL_VAL_STG_GATE Signal Assignments for Product Terms +assign TBL_VAL_STG_GATE_PT[1] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[11], + ex1_instr_q[12], ex1_instr_q[13], ex1_instr_q[14], ex1_instr_q[15], ex1_instr_q[16], ex1_instr_q[17], ex1_instr_q[18], + ex1_instr_q[19], ex1_instr_q[20], ex1_instr_q[21], ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], + ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], ex1_instr_q[29], ex1_instr_q[30], ex1_vld_q}) == 27'b011111011101111101110100111; +assign TBL_VAL_STG_GATE_PT[2] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], ex1_instr_q[29], + ex1_instr_q[30], au_lq_ex1_movedp, ex1_vld_q}) == 17'b01111100000001101; +assign TBL_VAL_STG_GATE_PT[3] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], + ex1_instr_q[29], ex1_instr_q[30], ex1_vld_q}) == 17'b01111111100001101; +assign TBL_VAL_STG_GATE_PT[4] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], + ex1_instr_q[29], ex1_instr_q[30], ex1_vld_q}) == 17'b01111100111111111; +assign TBL_VAL_STG_GATE_PT[5] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], + ex1_instr_q[29], ex1_instr_q[30], ex1_vld_q}) == 17'b01111100110011101; +assign TBL_VAL_STG_GATE_PT[6] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], + ex1_instr_q[29], ex1_instr_q[30], ex1_vld_q}) == 17'b01111100001100101; +assign TBL_VAL_STG_GATE_PT[7] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], + ex1_instr_q[29], ex1_instr_q[30], ex1_vld_q}) == 17'b01111111010101101; +assign TBL_VAL_STG_GATE_PT[8] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], + ex1_instr_q[29], ex1_instr_q[30], ex1_vld_q}) == 17'b01111111101001101; +assign TBL_VAL_STG_GATE_PT[9] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], + ex1_instr_q[29], ex1_instr_q[30], ex1_vld_q}) == 17'b01111110001101101; +assign TBL_VAL_STG_GATE_PT[10] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], + ex1_instr_q[29], ex1_instr_q[30], ex1_vld_q}) == 17'b01111110010101101; +assign TBL_VAL_STG_GATE_PT[11] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], ex1_instr_q[29], + ex1_instr_q[30], ex1_vld_q}) == 16'b0111110001000111; +assign TBL_VAL_STG_GATE_PT[12] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], ex1_instr_q[29], + ex1_instr_q[30], ex1_vld_q}) == 16'b0111110000000111; +assign TBL_VAL_STG_GATE_PT[13] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], + ex1_instr_q[30], ex1_vld_q}) == 16'b0111111000010101; +assign TBL_VAL_STG_GATE_PT[14] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[28], ex1_instr_q[29], ex1_instr_q[30], + ex1_vld_q}) == 15'b011111000011111; +assign TBL_VAL_STG_GATE_PT[15] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[28], ex1_instr_q[30], + ex1_vld_q}) == 15'b011111000001111; +assign TBL_VAL_STG_GATE_PT[16] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], ex1_instr_q[29], + ex1_instr_q[30], ex1_vld_q}) == 16'b0111111111111111; +assign TBL_VAL_STG_GATE_PT[17] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[28], ex1_instr_q[29], ex1_instr_q[30], + ex1_vld_q}) == 15'b011111000011111; +assign TBL_VAL_STG_GATE_PT[18] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], ex1_instr_q[29], + ex1_instr_q[30], ex1_vld_q}) == 16'b0111110111001101; +assign TBL_VAL_STG_GATE_PT[19] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], + ex1_instr_q[29], ex1_instr_q[30], ex1_vld_q}) == 17'b01111100111101101; +assign TBL_VAL_STG_GATE_PT[20] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[22], + ex1_instr_q[23], ex1_instr_q[25], ex1_instr_q[27], ex1_instr_q[28], ex1_instr_q[29], ex1_instr_q[30], + ex1_vld_q}) == 14'b01111111001101; +assign TBL_VAL_STG_GATE_PT[21] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[27], ex1_instr_q[28], ex1_instr_q[29], ex1_instr_q[30], + ex1_vld_q}) == 15'b011111010001101; +assign TBL_VAL_STG_GATE_PT[22] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], ex1_instr_q[29], + ex1_instr_q[30], ex1_vld_q}) == 16'b0111110100111111; +assign TBL_VAL_STG_GATE_PT[23] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], ex1_instr_q[29], + ex1_instr_q[30], ex1_vld_q}) == 16'b0111110010001101; +assign TBL_VAL_STG_GATE_PT[24] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], ex1_instr_q[29], + ex1_instr_q[30], ex1_vld_q}) == 16'b0111110010101001; +assign TBL_VAL_STG_GATE_PT[25] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], + ex1_instr_q[30], ex1_vld_q}) == 16'b0111110101010111; +assign TBL_VAL_STG_GATE_PT[26] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], ex1_instr_q[29], ex1_instr_q[30], + ex1_vld_q}) == 15'b011111111101101; +assign TBL_VAL_STG_GATE_PT[27] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], ex1_instr_q[29], ex1_instr_q[30], + ex1_vld_q}) == 15'b011111000111111; +assign TBL_VAL_STG_GATE_PT[28] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], + ex1_instr_q[29], ex1_vld_q}) == 16'b0111110100010111; +assign TBL_VAL_STG_GATE_PT[29] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], ex1_instr_q[30], + ex1_vld_q}) == 15'b011111100010101; +assign TBL_VAL_STG_GATE_PT[30] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[26], ex1_instr_q[28], ex1_instr_q[29], ex1_instr_q[30], + ex1_vld_q}) == 15'b011111001111111; +assign TBL_VAL_STG_GATE_PT[31] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], ex1_instr_q[29], + ex1_instr_q[30], ex1_vld_q}) == 16'b0111111000101101; +assign TBL_VAL_STG_GATE_PT[32] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], ex1_instr_q[29], ex1_instr_q[30], + ex1_vld_q}) == 15'b011111110101101; +assign TBL_VAL_STG_GATE_PT[33] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], ex1_instr_q[30], + ex1_vld_q}) == 15'b011111001010111; +assign TBL_VAL_STG_GATE_PT[34] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], ex1_instr_q[30], + ex1_vld_q}) == 15'b011111000010101; +assign TBL_VAL_STG_GATE_PT[35] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], ex1_instr_q[29], ex1_instr_q[30], + ex1_vld_q}) == 15'b011111010101111; +assign TBL_VAL_STG_GATE_PT[36] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], ex1_instr_q[29], ex1_instr_q[30], + ex1_vld_q}) == 15'b011111000101001; +assign TBL_VAL_STG_GATE_PT[37] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[28], ex1_instr_q[30], + ex1_vld_q}) == 14'b01111100001111; +assign TBL_VAL_STG_GATE_PT[38] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], + ex1_instr_q[21], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[28], ex1_instr_q[29], + ex1_instr_q[30], ex1_vld_q}) == 14'b01111100011111; +assign TBL_VAL_STG_GATE_PT[39] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], + ex1_instr_q[23], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], ex1_instr_q[29], + ex1_instr_q[30], ex1_vld_q}) == 14'b01111110101101; +assign TBL_VAL_STG_GATE_PT[40] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], + ex1_instr_q[21], ex1_instr_q[22], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], + ex1_instr_q[29], ex1_vld_q}) == 14'b01111100010111; +assign TBL_VAL_STG_GATE_PT[41] = ({ex1_instr_q[00], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[31], + ex1_vld_q}) == 7'b1101001; +assign TBL_VAL_STG_GATE_PT[42] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], + ex1_instr_q[30], ex1_vld_q}) == 8'b11111001; +assign TBL_VAL_STG_GATE_PT[43] = ({au_lq_ex1_ldst_v, au_lq_ex1_mftgpr, au_lq_ex1_mffgpr, au_lq_ex1_movedp, ex1_vld_q}) == 5'b10001; +assign TBL_VAL_STG_GATE_PT[44] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[03], ex1_instr_q[05], ex1_vld_q}) == 5'b10001; +assign TBL_VAL_STG_GATE_PT[45] = ({au_lq_ex1_mffgpr, au_lq_ex1_movedp, ex1_vld_q}) == 3'b111; +assign TBL_VAL_STG_GATE_PT[46] = ({au_lq_ex1_mftgpr, au_lq_ex1_movedp, ex1_vld_q}) == 3'b111; +assign TBL_VAL_STG_GATE_PT[47] = ({au_lq_ex1_mftgpr, au_lq_ex1_movedp, ex1_vld_q}) == 3'b101; +assign TBL_VAL_STG_GATE_PT[48] = ({au_lq_ex1_mffgpr, au_lq_ex1_movedp, ex1_vld_q}) == 3'b101; +assign TBL_VAL_STG_GATE_PT[49] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[03], ex1_instr_q[04], ex1_vld_q}) == 5'b10101; +assign TBL_VAL_STG_GATE_PT[50] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_vld_q}) == 5'b10011; +// Table TBL_VAL_STG_GATE Signal Assignments for Outputs +assign ex1_cache_acc = (TBL_VAL_STG_GATE_PT[8] | TBL_VAL_STG_GATE_PT[16] | TBL_VAL_STG_GATE_PT[18] | TBL_VAL_STG_GATE_PT[19] | + TBL_VAL_STG_GATE_PT[21] | TBL_VAL_STG_GATE_PT[22] | TBL_VAL_STG_GATE_PT[23] | TBL_VAL_STG_GATE_PT[24] | + TBL_VAL_STG_GATE_PT[25] | TBL_VAL_STG_GATE_PT[26] | TBL_VAL_STG_GATE_PT[27] | TBL_VAL_STG_GATE_PT[28] | + TBL_VAL_STG_GATE_PT[29] | TBL_VAL_STG_GATE_PT[30] | TBL_VAL_STG_GATE_PT[31] | TBL_VAL_STG_GATE_PT[32] | + TBL_VAL_STG_GATE_PT[33] | TBL_VAL_STG_GATE_PT[34] | TBL_VAL_STG_GATE_PT[35] | TBL_VAL_STG_GATE_PT[36] | + TBL_VAL_STG_GATE_PT[37] | TBL_VAL_STG_GATE_PT[38] | TBL_VAL_STG_GATE_PT[39] | TBL_VAL_STG_GATE_PT[40] | + TBL_VAL_STG_GATE_PT[41] | TBL_VAL_STG_GATE_PT[42] | TBL_VAL_STG_GATE_PT[43] | TBL_VAL_STG_GATE_PT[44] | + TBL_VAL_STG_GATE_PT[49] | TBL_VAL_STG_GATE_PT[50]); +assign ex1_is_msgsnd = (TBL_VAL_STG_GATE_PT[5]); +assign dec_dcc_ex1_mbar_instr = (TBL_VAL_STG_GATE_PT[7]); +assign dec_dcc_ex1_sync_instr = (TBL_VAL_STG_GATE_PT[10]); +assign dec_dcc_ex1_makeitso_instr = (TBL_VAL_STG_GATE_PT[6]); +assign dec_dcc_ex1_tlbsync_instr = (TBL_VAL_STG_GATE_PT[9]); +assign dec_dcc_ex1_wclr_instr = (TBL_VAL_STG_GATE_PT[8]); +assign dec_dcc_ex1_wchk_instr = (TBL_VAL_STG_GATE_PT[3]); +assign dec_dcc_ex1_src_gpr = (TBL_VAL_STG_GATE_PT[11] | TBL_VAL_STG_GATE_PT[48]); +assign dec_dcc_ex1_src_axu = (TBL_VAL_STG_GATE_PT[46] | TBL_VAL_STG_GATE_PT[47]); +assign dec_dcc_ex1_src_dp = (TBL_VAL_STG_GATE_PT[12] | TBL_VAL_STG_GATE_PT[45]); +assign dec_dcc_ex1_targ_gpr = (TBL_VAL_STG_GATE_PT[2] | TBL_VAL_STG_GATE_PT[47]); +assign dec_dcc_ex1_targ_axu = (TBL_VAL_STG_GATE_PT[45] | TBL_VAL_STG_GATE_PT[48]); +assign dec_dcc_ex1_targ_dp = (TBL_VAL_STG_GATE_PT[11] | TBL_VAL_STG_GATE_PT[46]); + +assign ex1_cmd_act = (TBL_VAL_STG_GATE_PT[1] | TBL_VAL_STG_GATE_PT[5] | TBL_VAL_STG_GATE_PT[6] | TBL_VAL_STG_GATE_PT[7] | + TBL_VAL_STG_GATE_PT[8] | TBL_VAL_STG_GATE_PT[9] | TBL_VAL_STG_GATE_PT[10] | TBL_VAL_STG_GATE_PT[11] | + TBL_VAL_STG_GATE_PT[12] | TBL_VAL_STG_GATE_PT[16] | TBL_VAL_STG_GATE_PT[18] | TBL_VAL_STG_GATE_PT[19] | + TBL_VAL_STG_GATE_PT[20] | TBL_VAL_STG_GATE_PT[22] | TBL_VAL_STG_GATE_PT[23] | TBL_VAL_STG_GATE_PT[24] | + TBL_VAL_STG_GATE_PT[25] | TBL_VAL_STG_GATE_PT[26] | TBL_VAL_STG_GATE_PT[27] | TBL_VAL_STG_GATE_PT[28] | + TBL_VAL_STG_GATE_PT[29] | TBL_VAL_STG_GATE_PT[30] | TBL_VAL_STG_GATE_PT[31] | TBL_VAL_STG_GATE_PT[32] | + TBL_VAL_STG_GATE_PT[33] | TBL_VAL_STG_GATE_PT[34] | TBL_VAL_STG_GATE_PT[35] | TBL_VAL_STG_GATE_PT[36] | + TBL_VAL_STG_GATE_PT[37] | TBL_VAL_STG_GATE_PT[38] | TBL_VAL_STG_GATE_PT[39] | TBL_VAL_STG_GATE_PT[40] | + TBL_VAL_STG_GATE_PT[41] | TBL_VAL_STG_GATE_PT[42] | TBL_VAL_STG_GATE_PT[43] | TBL_VAL_STG_GATE_PT[44] | + TBL_VAL_STG_GATE_PT[45] | TBL_VAL_STG_GATE_PT[46] | TBL_VAL_STG_GATE_PT[47] | TBL_VAL_STG_GATE_PT[48] | + TBL_VAL_STG_GATE_PT[49] | TBL_VAL_STG_GATE_PT[50]); +assign ctl_dat_ex1_data_act = (TBL_VAL_STG_GATE_PT[11] | TBL_VAL_STG_GATE_PT[12] | TBL_VAL_STG_GATE_PT[13] | TBL_VAL_STG_GATE_PT[14] | + TBL_VAL_STG_GATE_PT[15] | TBL_VAL_STG_GATE_PT[17] | TBL_VAL_STG_GATE_PT[24] | TBL_VAL_STG_GATE_PT[25] | + TBL_VAL_STG_GATE_PT[31] | TBL_VAL_STG_GATE_PT[36] | TBL_VAL_STG_GATE_PT[41] | TBL_VAL_STG_GATE_PT[43] | + TBL_VAL_STG_GATE_PT[44]); +assign ex1_mtspr_trace = (TBL_VAL_STG_GATE_PT[1]); +assign ex1_derat_act = (TBL_VAL_STG_GATE_PT[16] | TBL_VAL_STG_GATE_PT[18] | TBL_VAL_STG_GATE_PT[19] | TBL_VAL_STG_GATE_PT[21] | + TBL_VAL_STG_GATE_PT[22] | TBL_VAL_STG_GATE_PT[23] | TBL_VAL_STG_GATE_PT[24] | TBL_VAL_STG_GATE_PT[25] | + TBL_VAL_STG_GATE_PT[26] | TBL_VAL_STG_GATE_PT[27] | TBL_VAL_STG_GATE_PT[28] | TBL_VAL_STG_GATE_PT[29] | + TBL_VAL_STG_GATE_PT[30] | TBL_VAL_STG_GATE_PT[31] | TBL_VAL_STG_GATE_PT[32] | TBL_VAL_STG_GATE_PT[33] | + TBL_VAL_STG_GATE_PT[34] | TBL_VAL_STG_GATE_PT[35] | TBL_VAL_STG_GATE_PT[36] | TBL_VAL_STG_GATE_PT[37] | + TBL_VAL_STG_GATE_PT[38] | TBL_VAL_STG_GATE_PT[39] | TBL_VAL_STG_GATE_PT[40] | TBL_VAL_STG_GATE_PT[41] | + TBL_VAL_STG_GATE_PT[42] | TBL_VAL_STG_GATE_PT[43] | TBL_VAL_STG_GATE_PT[44] | TBL_VAL_STG_GATE_PT[49] | + TBL_VAL_STG_GATE_PT[50]); +assign ex1_dir_rd_act = (TBL_VAL_STG_GATE_PT[4] | TBL_VAL_STG_GATE_PT[13] | TBL_VAL_STG_GATE_PT[15] | TBL_VAL_STG_GATE_PT[17] | + TBL_VAL_STG_GATE_PT[19] | TBL_VAL_STG_GATE_PT[22] | TBL_VAL_STG_GATE_PT[23] | TBL_VAL_STG_GATE_PT[24] | + TBL_VAL_STG_GATE_PT[25] | TBL_VAL_STG_GATE_PT[28] | TBL_VAL_STG_GATE_PT[31] | TBL_VAL_STG_GATE_PT[36] | + TBL_VAL_STG_GATE_PT[41] | TBL_VAL_STG_GATE_PT[43] | TBL_VAL_STG_GATE_PT[44]); + +// +// Final Table Listing +// *INPUTS*===================================================*OUTPUTS*============================================* +// | | | +// | ex1_instr_q | | +// | | ex1_instr_q | | +// | | | ex1_instr_q | ex1_derat_is_load | +// | | | | ex1_instr_q | | ex1_derat_is_store | +// | | | | | au_lq_ex1_ldst_v | | | ex1_load_instr | +// | | | | | | au_lq_ex1_ldst_size | | | | dec_dcc_ex1_store_instr | +// | | | | | | | au_lq_ex1_mftgpr | | | | | dec_dcc_ex1_algebraic | +// | | | | | | | | au_lq_ex1_mffgpr | | | | | | dec_dcc_ex1_ldawx_instr | +// | | | | | | | | | au_lq_ex1_movedp | | | | | | | dec_dcc_ex1_optype1 | +// | | | | | | | | | | au_lq_ex1_st_v | | | | | | | | dec_dcc_ex1_optype16 | +// | | | | | | | | | | | | | | | | | | | | dec_dcc_ex1_optype2 | +// | | | | | | | | | | | | | | | | | | | | | dec_dcc_ex1_optype32 | +// | | | | | | | | | | | | | | | | | | | | | | dec_dcc_ex1_optype4 | +// | | | | | | | | | | | | | | | | | | | | | | | dec_dcc_ex1_optype8 | +// | | | | | | | | | | | | | | | | | | | | | | | | ex1_dcm_instr | +// | | | | | | | | | | | | | | | | | | | | | | | | | dec_dcc_ex1_strg_index | +// | | | | | | | | | | | | | | | | | | | | | | | | | | ex1_is_any_load_dac | +// | | | | | | | | | | | | | | | | | | | | | | | | | | | ex1_is_any_store_dac | +// | | | | | | | | | | | | | | | | | | | | | | | | | | | | ex1_resv_instr | +// | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | +// | 000000 0 2222222223 33 | 000000 | | | | | | | | | | | | | | | | | | | | | | | +// | 012345 9 1234567890 01 | 012345 | | | | | | | | | | | | | | | | | | | | | | | +// *TYPE*=====================================================+====================================================+ +// | PPPPPP P PPPPPPPPPP PP P PPPPPP P P P P | P P P P P P P P P P P P P P P P P | +// *POLARITY*------------------------------------------------>| + + + + + + + + + + + + + + + + + | +// *PHASE*--------------------------------------------------->| T T T T T T T T T T T T T T T T T | +// *TERMS*====================================================+====================================================+ +// 1 | 011111 1 1110100110 -- - ------ - - - - | 1 . . . . . . . . . . . . . 1 . . | +// 2 | 011111 - 1110100110 -- - ------ - - - - | . . . . . . . . . . . . 1 . . . . | +// 3 | 011111 - 1111111111 -- - ------ - - - - | . 1 . . . . . . . . . . 1 . . 1 . | +// 4 | 011111 - 1110110110 -- - ------ - - - - | . 1 . . . . . . . . 1 . . . . . . | +// 5 | 011111 - 1111011111 -- - ------ - - - - | 1 . . . . . . . . . . . 1 . 1 . . | +// 6 | 011111 - 0100111111 -- - ------ - - - - | 1 . . . . . . . . . . . 1 . 1 . . | +// 7 | 011111 - 10-0010101 -- - ------ - - - - | . . . . . . . . . . . . . 1 . . . | +// 8 | 011111 - 0011111111 -- - ------ - - - - | . 1 . . . . . . . . . . 1 . . 1 . | +// 9 | 011111 - 1111110110 -- - ------ - - - - | . 1 . . . . . . . . . . 1 . . 1 . | +// 10 | 011111 - 01010101-1 -- - ------ - - - - | . . 1 . 1 . . . . . . . . . . . . | +// 11 | 011111 - 0110000110 -- - ------ - - - - | 1 . . . . . . . . . . . 1 . 1 . . | +// 12 | 011111 - 1000010100 -- - ------ - - - - | 1 . . . . . . . . . . 1 . . 1 . . | +// 13 | 011111 - 0010000110 -- - ------ - - - - | . 1 . . . . . . . . . . 1 . . 1 . | +// 14 | 011111 - 1111010110 -- - ------ - - - - | 1 . . . . . . . . . . . 1 . 1 . . | +// 15 | 011111 - 0001110100 -- - ------ - - - - | 1 . 1 . . . . . 1 . . . . . 1 . 1 | +// 16 | 011111 - 1010010100 -- - ------ - - - - | . 1 . 1 . . . . . . . 1 . . . 1 . | +// 17 | 011111 - 0111010110 -- - ------ - - - - | . 1 . . . . . . . . . . 1 . . 1 . | +// 18 | 011111 - 0011110110 -- - ------ - - - - | . 1 . . . . . . . . . . 1 . . 1 . | +// 19 | 011111 - 1100010110 -- - ------ - - - - | 1 . 1 . . . . . 1 . . . . . 1 . . | +// 20 | 011111 - 1110010110 -- - ------ - - - - | . 1 . 1 . . . . 1 . . . . . . 1 . | +// 21 | 011111 - 0000110100 -- - ------ - - - - | 1 . 1 . . . 1 . . . . . . . 1 . 1 | +// 22 | 011111 - 1010110110 -- - ------ - - - - | . 1 . 1 . . 1 . . . . . . . . 1 1 | +// 23 | 011111 - 0-11100110 -- - ------ - - - - | 1 . . . . . . . . . . . 1 . 1 . . | +// 24 | 011111 - 0000110110 -- - ------ - - - - | 1 . . . . . . . . . . . 1 . . 1 . | +// 25 | 011111 - 001-010110 -- - ------ - - - - | . . . . . . . . . . . . . . . . 1 | +// 26 | 011111 - 101-010101 -- - ------ - - - - | . 1 . . . . . . . . . . . . . 1 . | +// 27 | 011111 - 0000010100 -- - ------ - - - - | 1 . . . . . . . . . 1 . . . 1 . 1 | +// 28 | 011111 - 0001010100 -- - ------ - - - - | 1 . 1 . . . . . . . . 1 . . 1 . 1 | +// 29 | 011111 - 100-010101 -- - ------ - - - - | 1 . . . . . . . . . . . . . 1 . . | +// 30 | 011111 - 0011010100 -- - ------ - - - - | 1 . 1 . . 1 . . . . . 1 . . 1 . . | +// 31 | 011111 - 000-111111 -- - ------ - - - - | 1 . . . . . . . . . . . 1 . . 1 . | +// 32 | 011111 - 1011010110 -- - ------ - - - - | . 1 . 1 . . . . 1 . . . . . . 1 1 | +// 33 | 011111 - 0001010110 -- - ------ - - - - | 1 . . . . . . . . . . . 1 . . 1 . | +// 34 | 011111 - 0101-10101 -- - ------ - - - - | 1 . . . . . . . . . 1 . . . 1 . . | +// 35 | 011111 - 1000010110 -- - ------ - - - - | 1 . 1 . . . . . . . 1 . . . 1 . . | +// 36 | 011111 - 001-100110 -- - ------ - - - - | 1 . . . . . . . . . . . 1 . 1 . . | +// 37 | 011111 - -00001010- -- - ------ - - - - | . . 1 . . . . . . . . . . . . . . | +// 38 | 011111 - 0011010110 -- - ------ - - - - | . 1 . 1 . . . . . . . 1 . . . 1 . | +// 39 | 011111 - 00-0-10101 -- - ------ - - - - | . . . . . . . . . . . 1 . . . . . | +// 40 | 011111 - 0-10010110 -- - ------ - - - - | . 1 . . . . . . . . 1 . . . . . . | +// 41 | 011111 - 000001-101 -- - ------ - - - - | 1 . 1 . . . . . . . . 1 . . 1 . . | +// 42 | 011111 - 001001-101 -- - ------ - - - - | . 1 . 1 . . . . . . . 1 . . . 1 . | +// 43 | 011111 - 010001-111 -- - ------ - - - - | 1 . 1 . . . . . 1 . . . . . 1 . . | +// 44 | 011111 - 0001-10111 -- - ------ - - - - | 1 . . . . . 1 . . . . . . . 1 . . | +// 45 | 011111 - 011001-111 -- - ------ - - - - | . 1 . 1 . . . . 1 . . . . . . 1 . | +// 46 | 011111 - 000101-111 -- - ------ - - - - | 1 . 1 . . . 1 . . . . . . . 1 . . | +// 47 | 011111 - 001101-111 -- - ------ - - - - | . 1 . 1 . . 1 . . . . . . . . 1 . | +// 48 | 011111 - 00-0-10111 -- - ------ - - - - | . . . . . . . . . . 1 . . . . . . | +// 49 | 011111 - 0110-10111 -- - ------ - - - - | . 1 . 1 . . . . 1 . . . . . . 1 . | +// 50 | 011111 - 0011-10111 -- - ------ - - - - | . 1 . 1 . . 1 . . . . . . . . 1 . | +// 51 | 011111 - 0-00010110 -- - ------ - - - - | 1 . . . . . . . . . . . 1 . 1 . . | +// 52 | 011111 - 000001-111 -- - ------ - - - - | 1 . 1 . . . . . . . 1 . . . 1 . . | +// 53 | 011111 - 001001-111 -- - ------ - - - - | . 1 . 1 . . . . . . 1 . . . . 1 . | +// 54 | 011111 - -010010110 -- - ------ - - - - | . 1 . 1 . . . . . . 1 . . . . 1 . | +// 55 | 011111 - 0000-101-1 -- - ------ - - - - | 1 . . . . . . . . . . . . . 1 . . | +// 56 | 011111 - 010--10111 -- - ------ - - - - | 1 . . . . . . . 1 . . . . . 1 . . | +// 57 | 011111 - 0010-101-1 -- - ------ - - - - | . 1 . 1 . . . . . . . . . . . 1 . | +// 58 | 111010 - ---------- 10 - ------ - - - - | 1 . . . 1 . . . . . 1 . . . 1 . . | +// 59 | ------ - ---------- -- 1 ------ 0 0 0 1 | . 1 . 1 . . . . . . . . . . . 1 . | +// 60 | 101010 - ---------- -- - ------ - - - - | . . . . 1 . . . . . . . . . . . . | +// 61 | ------ - ---------- -- 1 ------ 0 0 0 0 | 1 . 1 . . . . . . . . . . . 1 . . | +// 62 | 1-1010 - ---------- -0 - ------ - - - - | . . 1 . . . . . . . . . . . . . . | +// 63 | 10000- - ---------- -- - ------ - - - - | 1 . . . . . . . . . 1 . . . 1 . . | +// 64 | 10-0-0 - ---------- -- - ------ - - - - | . . 1 . . . . . . . . . . . . . . | +// 65 | 111010 - ---------- 0- - ------ - - - - | 1 . . . . . . . . . . 1 . . 1 . . | +// 66 | 10001- - ---------- -- - ------ - - - - | 1 . . . . . 1 . . . . . . . 1 . . | +// 67 | 10010- - ---------- -- - ------ - - - - | . 1 . 1 . . . . . . 1 . . . . 1 . | +// 68 | 111110 - ---------- 0- - ------ - - - - | . 1 . 1 . . . . . . . 1 . . . 1 . | +// 69 | 101110 - ---------- -- - ------ - - - - | 1 . . . . . . . . . 1 . . . 1 . . | +// 70 | 10011- - ---------- -- - ------ - - - - | . 1 . 1 . . 1 . . . . . . . . 1 . | +// 71 | 10110- - ---------- -- - ------ - - - - | . 1 . 1 . . . . 1 . . . . . . 1 . | +// 72 | ------ - ---------- -- 1 -1---- - - - - | . . . . . . . 1 . . . . . . . . . | +// 73 | ------ - ---------- -- 1 1----- - - - - | . . . . . . . . . 1 . . . . . . . | +// 74 | ------ - ---------- -- 1 -----1 - - - - | . . . . . . 1 . . . . . . . . . . | +// 75 | 1010-- - ---------- -- - ------ - - - - | 1 . . . . . . . 1 . . . . . 1 . . | +// 76 | ------ - ---------- -- 1 ----1- - - - - | . . . . . . . . 1 . . . . . . . . | +// 77 | ------ - ---------- -- 1 --1--- - - - - | . . . . . . . . . . . 1 . . . . . | +// 78 | ------ - ---------- -- 1 ---1-- - - - - | . . . . . . . . . . 1 . . . . . . | +// 79 | 101111 - ---------- -- - ------ - - - - | . 1 . . . . . . . . 1 . . . . 1 . | +// *===============================================================================================================* +// +// Table TBL_LD_ST_DEC Signal Assignments for Product Terms +assign TBL_LD_ST_DEC_PT[1] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[09], + ex1_instr_q[21], ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], + ex1_instr_q[28], ex1_instr_q[29], ex1_instr_q[30]}) == 17'b01111111110100110; +assign TBL_LD_ST_DEC_PT[2] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], + ex1_instr_q[29], ex1_instr_q[30]}) == 16'b0111111110100110; +assign TBL_LD_ST_DEC_PT[3] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], + ex1_instr_q[29], ex1_instr_q[30]}) == 16'b0111111111111111; +assign TBL_LD_ST_DEC_PT[4] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], + ex1_instr_q[29], ex1_instr_q[30]}) == 16'b0111111110110110; +assign TBL_LD_ST_DEC_PT[5] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], + ex1_instr_q[29], ex1_instr_q[30]}) == 16'b0111111111011111; +assign TBL_LD_ST_DEC_PT[6] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], + ex1_instr_q[29], ex1_instr_q[30]}) == 16'b0111110100111111; +assign TBL_LD_ST_DEC_PT[7] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], ex1_instr_q[29], + ex1_instr_q[30]}) == 15'b011111100010101; +assign TBL_LD_ST_DEC_PT[8] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], + ex1_instr_q[29], ex1_instr_q[30]}) == 16'b0111110011111111; +assign TBL_LD_ST_DEC_PT[9] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], + ex1_instr_q[29], ex1_instr_q[30]}) == 16'b0111111111110110; +assign TBL_LD_ST_DEC_PT[10] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], + ex1_instr_q[30]}) == 15'b011111010101011; +assign TBL_LD_ST_DEC_PT[11] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], + ex1_instr_q[29], ex1_instr_q[30]}) == 16'b0111110110000110; +assign TBL_LD_ST_DEC_PT[12] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], + ex1_instr_q[29], ex1_instr_q[30]}) == 16'b0111111000010100; +assign TBL_LD_ST_DEC_PT[13] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], + ex1_instr_q[29], ex1_instr_q[30]}) == 16'b0111110010000110; +assign TBL_LD_ST_DEC_PT[14] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], + ex1_instr_q[29], ex1_instr_q[30]}) == 16'b0111111111010110; +assign TBL_LD_ST_DEC_PT[15] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], + ex1_instr_q[29], ex1_instr_q[30]}) == 16'b0111110001110100; +assign TBL_LD_ST_DEC_PT[16] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], + ex1_instr_q[29], ex1_instr_q[30]}) == 16'b0111111010010100; +assign TBL_LD_ST_DEC_PT[17] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], + ex1_instr_q[29], ex1_instr_q[30]}) == 16'b0111110111010110; +assign TBL_LD_ST_DEC_PT[18] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], + ex1_instr_q[29], ex1_instr_q[30]}) == 16'b0111110011110110; +assign TBL_LD_ST_DEC_PT[19] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], + ex1_instr_q[29], ex1_instr_q[30]}) == 16'b0111111100010110; +assign TBL_LD_ST_DEC_PT[20] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], + ex1_instr_q[29], ex1_instr_q[30]}) == 16'b0111111110010110; +assign TBL_LD_ST_DEC_PT[21] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], + ex1_instr_q[29], ex1_instr_q[30]}) == 16'b0111110000110100; +assign TBL_LD_ST_DEC_PT[22] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], + ex1_instr_q[29], ex1_instr_q[30]}) == 16'b0111111010110110; +assign TBL_LD_ST_DEC_PT[23] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], ex1_instr_q[29], + ex1_instr_q[30]}) == 15'b011111011100110; +assign TBL_LD_ST_DEC_PT[24] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], + ex1_instr_q[29], ex1_instr_q[30]}) == 16'b0111110000110110; +assign TBL_LD_ST_DEC_PT[25] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], ex1_instr_q[29], + ex1_instr_q[30]}) == 15'b011111001010110; +assign TBL_LD_ST_DEC_PT[26] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], ex1_instr_q[29], + ex1_instr_q[30]}) == 15'b011111101010101; +assign TBL_LD_ST_DEC_PT[27] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], + ex1_instr_q[29], ex1_instr_q[30]}) == 16'b0111110000010100; +assign TBL_LD_ST_DEC_PT[28] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], + ex1_instr_q[29], ex1_instr_q[30]}) == 16'b0111110001010100; +assign TBL_LD_ST_DEC_PT[29] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], ex1_instr_q[29], + ex1_instr_q[30]}) == 15'b011111100010101; +assign TBL_LD_ST_DEC_PT[30] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], + ex1_instr_q[29], ex1_instr_q[30]}) == 16'b0111110011010100; +assign TBL_LD_ST_DEC_PT[31] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], ex1_instr_q[29], + ex1_instr_q[30]}) == 15'b011111000111111; +assign TBL_LD_ST_DEC_PT[32] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], + ex1_instr_q[29], ex1_instr_q[30]}) == 16'b0111111011010110; +assign TBL_LD_ST_DEC_PT[33] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], + ex1_instr_q[29], ex1_instr_q[30]}) == 16'b0111110001010110; +assign TBL_LD_ST_DEC_PT[34] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], ex1_instr_q[29], + ex1_instr_q[30]}) == 15'b011111010110101; +assign TBL_LD_ST_DEC_PT[35] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], + ex1_instr_q[29], ex1_instr_q[30]}) == 16'b0111111000010110; +assign TBL_LD_ST_DEC_PT[36] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], ex1_instr_q[29], + ex1_instr_q[30]}) == 15'b011111001100110; +assign TBL_LD_ST_DEC_PT[37] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[22], + ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], + ex1_instr_q[29]}) == 14'b01111100001010; +assign TBL_LD_ST_DEC_PT[38] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], + ex1_instr_q[29], ex1_instr_q[30]}) == 16'b0111110011010110; +assign TBL_LD_ST_DEC_PT[39] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[24], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], ex1_instr_q[29], + ex1_instr_q[30]}) == 14'b01111100010101; +assign TBL_LD_ST_DEC_PT[40] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], ex1_instr_q[29], + ex1_instr_q[30]}) == 15'b011111010010110; +assign TBL_LD_ST_DEC_PT[41] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[28], ex1_instr_q[29], + ex1_instr_q[30]}) == 15'b011111000001101; +assign TBL_LD_ST_DEC_PT[42] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[28], ex1_instr_q[29], + ex1_instr_q[30]}) == 15'b011111001001101; +assign TBL_LD_ST_DEC_PT[43] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[28], ex1_instr_q[29], + ex1_instr_q[30]}) == 15'b011111010001111; +assign TBL_LD_ST_DEC_PT[44] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], ex1_instr_q[29], + ex1_instr_q[30]}) == 15'b011111000110111; +assign TBL_LD_ST_DEC_PT[45] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[28], ex1_instr_q[29], + ex1_instr_q[30]}) == 15'b011111011001111; +assign TBL_LD_ST_DEC_PT[46] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[28], ex1_instr_q[29], + ex1_instr_q[30]}) == 15'b011111000101111; +assign TBL_LD_ST_DEC_PT[47] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[28], ex1_instr_q[29], + ex1_instr_q[30]}) == 15'b011111001101111; +assign TBL_LD_ST_DEC_PT[48] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[24], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], ex1_instr_q[29], + ex1_instr_q[30]}) == 14'b01111100010111; +assign TBL_LD_ST_DEC_PT[49] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], ex1_instr_q[29], + ex1_instr_q[30]}) == 15'b011111011010111; +assign TBL_LD_ST_DEC_PT[50] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], ex1_instr_q[29], + ex1_instr_q[30]}) == 15'b011111001110111; +assign TBL_LD_ST_DEC_PT[51] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], ex1_instr_q[29], + ex1_instr_q[30]}) == 15'b011111000010110; +assign TBL_LD_ST_DEC_PT[52] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[28], ex1_instr_q[29], + ex1_instr_q[30]}) == 15'b011111000001111; +assign TBL_LD_ST_DEC_PT[53] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[28], ex1_instr_q[29], + ex1_instr_q[30]}) == 15'b011111001001111; +assign TBL_LD_ST_DEC_PT[54] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[22], + ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[25], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], ex1_instr_q[29], + ex1_instr_q[30]}) == 15'b011111010010110; +assign TBL_LD_ST_DEC_PT[55] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], + ex1_instr_q[30]}) == 14'b01111100001011; +assign TBL_LD_ST_DEC_PT[56] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], ex1_instr_q[29], + ex1_instr_q[30]}) == 14'b01111101010111; +assign TBL_LD_ST_DEC_PT[57] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[21], + ex1_instr_q[22], ex1_instr_q[23], ex1_instr_q[24], ex1_instr_q[26], ex1_instr_q[27], ex1_instr_q[28], + ex1_instr_q[30]}) == 14'b01111100101011; +assign TBL_LD_ST_DEC_PT[58] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[30], + ex1_instr_q[31]}) == 8'b11101010; +assign TBL_LD_ST_DEC_PT[59] = ({au_lq_ex1_ldst_v, au_lq_ex1_mftgpr, au_lq_ex1_mffgpr, au_lq_ex1_movedp, au_lq_ex1_st_v}) == 5'b10001; +assign TBL_LD_ST_DEC_PT[60] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05]}) == 6'b101010; +assign TBL_LD_ST_DEC_PT[61] = ({au_lq_ex1_ldst_v, au_lq_ex1_mftgpr, au_lq_ex1_mffgpr, au_lq_ex1_movedp, au_lq_ex1_st_v}) == 5'b10000; +assign TBL_LD_ST_DEC_PT[62] = ({ex1_instr_q[00], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[31]}) == 6'b110100; +assign TBL_LD_ST_DEC_PT[63] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04]}) == 5'b10000; +assign TBL_LD_ST_DEC_PT[64] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[03], ex1_instr_q[05]}) == 4'b1000; +assign TBL_LD_ST_DEC_PT[65] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[30]}) == 7'b1110100; +assign TBL_LD_ST_DEC_PT[66] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04]}) == 5'b10001; +assign TBL_LD_ST_DEC_PT[67] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04]}) == 5'b10010; +assign TBL_LD_ST_DEC_PT[68] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05], ex1_instr_q[30]}) == 7'b1111100; +assign TBL_LD_ST_DEC_PT[69] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05]}) == 6'b101110; +assign TBL_LD_ST_DEC_PT[70] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04]}) == 5'b10011; +assign TBL_LD_ST_DEC_PT[71] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04]}) == 5'b10110; +assign TBL_LD_ST_DEC_PT[72] = ({au_lq_ex1_ldst_v, au_lq_ex1_ldst_size[01]}) == 2'b11; +assign TBL_LD_ST_DEC_PT[73] = ({au_lq_ex1_ldst_v, au_lq_ex1_ldst_size[00]}) == 2'b11; +assign TBL_LD_ST_DEC_PT[74] = ({au_lq_ex1_ldst_v, au_lq_ex1_ldst_size[05]}) == 2'b11; +assign TBL_LD_ST_DEC_PT[75] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03]}) == 4'b1010; +assign TBL_LD_ST_DEC_PT[76] = ({au_lq_ex1_ldst_v, au_lq_ex1_ldst_size[04]}) == 2'b11; +assign TBL_LD_ST_DEC_PT[77] = ({au_lq_ex1_ldst_v, au_lq_ex1_ldst_size[02]}) == 2'b11; +assign TBL_LD_ST_DEC_PT[78] = ({au_lq_ex1_ldst_v, au_lq_ex1_ldst_size[03]}) == 2'b11; +assign TBL_LD_ST_DEC_PT[79] = ({ex1_instr_q[00], ex1_instr_q[01], ex1_instr_q[02], ex1_instr_q[03], ex1_instr_q[04], ex1_instr_q[05]}) == 6'b101111; + +// Table TBL_LD_ST_DEC Signal Assignments for Outputs +assign ex1_derat_is_load = (TBL_LD_ST_DEC_PT[1] | TBL_LD_ST_DEC_PT[5] | TBL_LD_ST_DEC_PT[6] | TBL_LD_ST_DEC_PT[11] | + TBL_LD_ST_DEC_PT[12] | TBL_LD_ST_DEC_PT[14] | TBL_LD_ST_DEC_PT[15] | TBL_LD_ST_DEC_PT[19] | + TBL_LD_ST_DEC_PT[21] | TBL_LD_ST_DEC_PT[23] | TBL_LD_ST_DEC_PT[24] | TBL_LD_ST_DEC_PT[27] | + TBL_LD_ST_DEC_PT[28] | TBL_LD_ST_DEC_PT[29] | TBL_LD_ST_DEC_PT[30] | TBL_LD_ST_DEC_PT[31] | + TBL_LD_ST_DEC_PT[33] | TBL_LD_ST_DEC_PT[34] | TBL_LD_ST_DEC_PT[35] | TBL_LD_ST_DEC_PT[36] | + TBL_LD_ST_DEC_PT[41] | TBL_LD_ST_DEC_PT[43] | TBL_LD_ST_DEC_PT[44] | TBL_LD_ST_DEC_PT[46] | + TBL_LD_ST_DEC_PT[51] | TBL_LD_ST_DEC_PT[52] | TBL_LD_ST_DEC_PT[55] | TBL_LD_ST_DEC_PT[56] | + TBL_LD_ST_DEC_PT[58] | TBL_LD_ST_DEC_PT[61] | TBL_LD_ST_DEC_PT[63] | TBL_LD_ST_DEC_PT[65] | + TBL_LD_ST_DEC_PT[66] | TBL_LD_ST_DEC_PT[69] | TBL_LD_ST_DEC_PT[75]); +assign ex1_derat_is_store = (TBL_LD_ST_DEC_PT[3] | TBL_LD_ST_DEC_PT[4] | TBL_LD_ST_DEC_PT[8] | TBL_LD_ST_DEC_PT[9] | + TBL_LD_ST_DEC_PT[13] | TBL_LD_ST_DEC_PT[16] | TBL_LD_ST_DEC_PT[17] | TBL_LD_ST_DEC_PT[18] | + TBL_LD_ST_DEC_PT[20] | TBL_LD_ST_DEC_PT[22] | TBL_LD_ST_DEC_PT[26] | TBL_LD_ST_DEC_PT[32] | + TBL_LD_ST_DEC_PT[38] | TBL_LD_ST_DEC_PT[40] | TBL_LD_ST_DEC_PT[42] | TBL_LD_ST_DEC_PT[45] | + TBL_LD_ST_DEC_PT[47] | TBL_LD_ST_DEC_PT[49] | TBL_LD_ST_DEC_PT[50] | TBL_LD_ST_DEC_PT[53] | + TBL_LD_ST_DEC_PT[54] | TBL_LD_ST_DEC_PT[57] | TBL_LD_ST_DEC_PT[59] | TBL_LD_ST_DEC_PT[67] | + TBL_LD_ST_DEC_PT[68] | TBL_LD_ST_DEC_PT[70] | TBL_LD_ST_DEC_PT[71] | TBL_LD_ST_DEC_PT[79]); +assign ex1_load_instr = (TBL_LD_ST_DEC_PT[10] | TBL_LD_ST_DEC_PT[15] | TBL_LD_ST_DEC_PT[19] | TBL_LD_ST_DEC_PT[21] | + TBL_LD_ST_DEC_PT[28] | TBL_LD_ST_DEC_PT[30] | TBL_LD_ST_DEC_PT[35] | TBL_LD_ST_DEC_PT[37] | + TBL_LD_ST_DEC_PT[41] | TBL_LD_ST_DEC_PT[43] | TBL_LD_ST_DEC_PT[46] | TBL_LD_ST_DEC_PT[52] | + TBL_LD_ST_DEC_PT[61] | TBL_LD_ST_DEC_PT[62] | TBL_LD_ST_DEC_PT[64]); +assign dec_dcc_ex1_store_instr = (TBL_LD_ST_DEC_PT[16] | TBL_LD_ST_DEC_PT[20] | TBL_LD_ST_DEC_PT[22] | TBL_LD_ST_DEC_PT[32] | + TBL_LD_ST_DEC_PT[38] | TBL_LD_ST_DEC_PT[42] | TBL_LD_ST_DEC_PT[45] | TBL_LD_ST_DEC_PT[47] | + TBL_LD_ST_DEC_PT[49] | TBL_LD_ST_DEC_PT[50] | TBL_LD_ST_DEC_PT[53] | TBL_LD_ST_DEC_PT[54] | + TBL_LD_ST_DEC_PT[57] | TBL_LD_ST_DEC_PT[59] | TBL_LD_ST_DEC_PT[67] | TBL_LD_ST_DEC_PT[68] | + TBL_LD_ST_DEC_PT[70] | TBL_LD_ST_DEC_PT[71]); +assign dec_dcc_ex1_algebraic = (TBL_LD_ST_DEC_PT[10] | TBL_LD_ST_DEC_PT[58] | TBL_LD_ST_DEC_PT[60]); +assign dec_dcc_ex1_ldawx_instr = (TBL_LD_ST_DEC_PT[30]); +assign dec_dcc_ex1_optype1 = (TBL_LD_ST_DEC_PT[21] | TBL_LD_ST_DEC_PT[22] | TBL_LD_ST_DEC_PT[44] | TBL_LD_ST_DEC_PT[46] | + TBL_LD_ST_DEC_PT[47] | TBL_LD_ST_DEC_PT[50] | TBL_LD_ST_DEC_PT[66] | TBL_LD_ST_DEC_PT[70] | + TBL_LD_ST_DEC_PT[74]); +assign dec_dcc_ex1_optype16 = (TBL_LD_ST_DEC_PT[72]); +assign dec_dcc_ex1_optype2 = (TBL_LD_ST_DEC_PT[15] | TBL_LD_ST_DEC_PT[19] | TBL_LD_ST_DEC_PT[20] | TBL_LD_ST_DEC_PT[32] | + TBL_LD_ST_DEC_PT[43] | TBL_LD_ST_DEC_PT[45] | TBL_LD_ST_DEC_PT[49] | TBL_LD_ST_DEC_PT[56] | + TBL_LD_ST_DEC_PT[71] | TBL_LD_ST_DEC_PT[75] | TBL_LD_ST_DEC_PT[76]); +assign dec_dcc_ex1_optype32 = (TBL_LD_ST_DEC_PT[73]); +assign dec_dcc_ex1_optype4 = (TBL_LD_ST_DEC_PT[4] | TBL_LD_ST_DEC_PT[27] | TBL_LD_ST_DEC_PT[34] | TBL_LD_ST_DEC_PT[35] | + TBL_LD_ST_DEC_PT[40] | TBL_LD_ST_DEC_PT[48] | TBL_LD_ST_DEC_PT[52] | TBL_LD_ST_DEC_PT[53] | + TBL_LD_ST_DEC_PT[54] | TBL_LD_ST_DEC_PT[58] | TBL_LD_ST_DEC_PT[63] | TBL_LD_ST_DEC_PT[67] | + TBL_LD_ST_DEC_PT[69] | TBL_LD_ST_DEC_PT[78] | TBL_LD_ST_DEC_PT[79]); +assign dec_dcc_ex1_optype8 = (TBL_LD_ST_DEC_PT[12] | TBL_LD_ST_DEC_PT[16] | TBL_LD_ST_DEC_PT[28] | TBL_LD_ST_DEC_PT[30] | + TBL_LD_ST_DEC_PT[38] | TBL_LD_ST_DEC_PT[39] | TBL_LD_ST_DEC_PT[41] | TBL_LD_ST_DEC_PT[42] | + TBL_LD_ST_DEC_PT[65] | TBL_LD_ST_DEC_PT[68] | TBL_LD_ST_DEC_PT[77]); +assign ex1_dcm_instr = (TBL_LD_ST_DEC_PT[2] | TBL_LD_ST_DEC_PT[3] | TBL_LD_ST_DEC_PT[5] | TBL_LD_ST_DEC_PT[6] | + TBL_LD_ST_DEC_PT[8] | TBL_LD_ST_DEC_PT[9] | TBL_LD_ST_DEC_PT[11] | TBL_LD_ST_DEC_PT[13] | + TBL_LD_ST_DEC_PT[14] | TBL_LD_ST_DEC_PT[17] | TBL_LD_ST_DEC_PT[18] | TBL_LD_ST_DEC_PT[23] | + TBL_LD_ST_DEC_PT[24] | TBL_LD_ST_DEC_PT[31] | TBL_LD_ST_DEC_PT[33] | TBL_LD_ST_DEC_PT[36] | + TBL_LD_ST_DEC_PT[51]); +assign dec_dcc_ex1_strg_index = (TBL_LD_ST_DEC_PT[7]); +assign ex1_is_any_load_dac = (TBL_LD_ST_DEC_PT[1] | TBL_LD_ST_DEC_PT[5] | TBL_LD_ST_DEC_PT[6] | TBL_LD_ST_DEC_PT[11] | + TBL_LD_ST_DEC_PT[12] | TBL_LD_ST_DEC_PT[14] | TBL_LD_ST_DEC_PT[15] | TBL_LD_ST_DEC_PT[19] | + TBL_LD_ST_DEC_PT[21] | TBL_LD_ST_DEC_PT[23] | TBL_LD_ST_DEC_PT[27] | TBL_LD_ST_DEC_PT[28] | + TBL_LD_ST_DEC_PT[29] | TBL_LD_ST_DEC_PT[30] | TBL_LD_ST_DEC_PT[34] | TBL_LD_ST_DEC_PT[35] | + TBL_LD_ST_DEC_PT[36] | TBL_LD_ST_DEC_PT[41] | TBL_LD_ST_DEC_PT[43] | TBL_LD_ST_DEC_PT[44] | + TBL_LD_ST_DEC_PT[46] | TBL_LD_ST_DEC_PT[51] | TBL_LD_ST_DEC_PT[52] | TBL_LD_ST_DEC_PT[55] | + TBL_LD_ST_DEC_PT[56] | TBL_LD_ST_DEC_PT[58] | TBL_LD_ST_DEC_PT[61] | TBL_LD_ST_DEC_PT[63] | + TBL_LD_ST_DEC_PT[65] | TBL_LD_ST_DEC_PT[66] | TBL_LD_ST_DEC_PT[69] | TBL_LD_ST_DEC_PT[75]); +assign ex1_is_any_store_dac = (TBL_LD_ST_DEC_PT[3] | TBL_LD_ST_DEC_PT[8] | TBL_LD_ST_DEC_PT[9] | TBL_LD_ST_DEC_PT[13] | + TBL_LD_ST_DEC_PT[16] | TBL_LD_ST_DEC_PT[17] | TBL_LD_ST_DEC_PT[18] | TBL_LD_ST_DEC_PT[20] | + TBL_LD_ST_DEC_PT[22] | TBL_LD_ST_DEC_PT[24] | TBL_LD_ST_DEC_PT[26] | TBL_LD_ST_DEC_PT[31] | + TBL_LD_ST_DEC_PT[32] | TBL_LD_ST_DEC_PT[33] | TBL_LD_ST_DEC_PT[38] | TBL_LD_ST_DEC_PT[42] | + TBL_LD_ST_DEC_PT[45] | TBL_LD_ST_DEC_PT[47] | TBL_LD_ST_DEC_PT[49] | TBL_LD_ST_DEC_PT[50] | + TBL_LD_ST_DEC_PT[53] | TBL_LD_ST_DEC_PT[54] | TBL_LD_ST_DEC_PT[57] | TBL_LD_ST_DEC_PT[59] | + TBL_LD_ST_DEC_PT[67] | TBL_LD_ST_DEC_PT[68] | TBL_LD_ST_DEC_PT[70] | TBL_LD_ST_DEC_PT[71] | + TBL_LD_ST_DEC_PT[79]); +assign ex1_resv_instr = (TBL_LD_ST_DEC_PT[15] | TBL_LD_ST_DEC_PT[21] | TBL_LD_ST_DEC_PT[22] | TBL_LD_ST_DEC_PT[25] | + TBL_LD_ST_DEC_PT[27] | TBL_LD_ST_DEC_PT[28] | TBL_LD_ST_DEC_PT[32]); + +assign dec_derat_ex1_is_load = ex1_derat_is_load; +assign dec_derat_ex1_is_store = ex1_derat_is_store; +assign ex1_is_ditc = ex1_is_mtdpx | ex1_is_mtdp | ex1_is_mfdpx | ex1_is_mfdp; + +// Need to decode these ops in ex0 +assign ex1_opcode_is_62 = ex1_instr_q[0:5] == 6'b111110; +assign ex1_opcode_is_58 = ex1_instr_q[0:5] == 6'b111010; +assign ex1_opcode_is_31 = ex1_instr_q[0:5] == 6'b011111; +assign ex1_is_dcbf = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0001010110); +assign ex1_is_dcbi = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0111010110); +assign ex1_is_dcbst = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0000110110); +assign ex1_is_dcblc = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0110000110); +assign ex1_is_dcbt = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0100010110); +assign ex1_is_dcbtls = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0010100110); +assign ex1_is_dcbtst = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0011110110); +assign ex1_is_dcbtstls = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0010000110); +assign ex1_is_dcbz = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b1111110110); +assign ex1_is_dci = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0111000110); +assign ex1_is_ici = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b1111000110); +assign ex1_is_icbi = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b1111010110); +assign ex1_is_icblc = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0011100110); +assign ex1_is_icbt = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0000010110); +assign ex1_is_icbtls = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0111100110); +assign ex1_is_lbz = (ex1_instr_q[0:5] == 6'b100010); +assign ex1_is_lbzu = (ex1_instr_q[0:5] == 6'b100011); +assign ex1_is_lbzux = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0001110111); +assign ex1_is_ld = (ex1_opcode_is_58 & ex1_instr_q[30:31] == 2'b00); +assign ex1_is_ldbrx = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b1000010100); +assign ex1_is_ldu = (ex1_opcode_is_58 & ex1_instr_q[30:31] == 2'b01); +assign ex1_is_ldux = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0000110101); +assign ex1_is_lha = (ex1_instr_q[0:5] == 6'b101010); +assign ex1_is_lhau = (ex1_instr_q[0:5] == 6'b101011); +assign ex1_is_lhaux = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0101110111); +assign ex1_is_lhbrx = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b1100010110); +assign ex1_is_lhzux = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0100110111); +assign ex1_is_lhz = (ex1_instr_q[0:5] == 6'b101000); +assign ex1_is_lhzu = (ex1_instr_q[0:5] == 6'b101001); +assign ex1_is_lmw = (ex1_instr_q[0:5] == 6'b101110); +assign ex1_is_lswi = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b1001010101); +assign ex1_is_lwa = (ex1_opcode_is_58 & ex1_instr_q[30:31] == 2'b10); +assign ex1_is_lwaux = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0101110101); +assign ex1_is_lwz = (ex1_instr_q[0:5] == 6'b100000); +assign ex1_is_lwzu = (ex1_instr_q[0:5] == 6'b100001); +assign ex1_is_lwzux = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0000110111); +assign ex1_is_lwbrx = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b1000010110); +assign ex1_is_mfdp = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0000100011); +assign ex1_is_mfdpx = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0000000011); +assign ex1_is_mtdp = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0001100011); +assign ex1_is_mtdpx = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0001000011); +assign ex1_is_stb = (ex1_instr_q[0:5] == 6'b100110); +assign ex1_is_stbu = (ex1_instr_q[0:5] == 6'b100111); +assign ex1_is_stbux = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0011110111); +assign ex1_is_std = (ex1_opcode_is_62 & ex1_instr_q[30:31] == 2'b00); +assign ex1_is_stdbrx = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b1010010100); +assign ex1_is_stdu = (ex1_opcode_is_62 & ex1_instr_q[30:31] == 2'b01); +assign ex1_is_stdux = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0010110101); +assign ex1_is_sth = (ex1_instr_q[0:5] == 6'b101100); +assign ex1_is_sthu = (ex1_instr_q[0:5] == 6'b101101); +assign ex1_is_sthux = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0110110111); +assign ex1_is_sthbrx = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b1110010110); +assign ex1_is_stmw = (ex1_instr_q[0:5] == 6'b101111); +assign ex1_is_stswi = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b1011010101); +assign ex1_is_stw = (ex1_instr_q[0:5] == 6'b100100); +assign ex1_is_stwu = (ex1_instr_q[0:5] == 6'b100101); +assign ex1_is_stwux = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0010110111); +assign ex1_is_stwbrx = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b1010010110); +assign ex1_is_tlbsync = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b1000110110); +assign ex1_is_dcbstep = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0000111111); +assign ex1_is_dcbtep = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0100111111); +assign ex1_is_dcbfep = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0001111111); +assign ex1_is_dcbtstep = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0011111111); +assign ex1_is_icbiep = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b1111011111); +assign ex1_is_dcbzep = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b1111111111); +assign ex1_is_icswx = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0110010110); +assign ex1_is_icswepx = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b1110110110); +assign ex1_is_wclr = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b1110100110); +assign ex1_wclr_one_val = ex1_vld_q & ex1_is_wclr & ex1_instr_q[9]; +assign ex1_is_lbepx = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0001011111); +assign ex1_is_ldepx = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0000011101); +assign ex1_is_lhepx = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0100011111); +assign ex1_is_lwepx = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0000011111); +assign ex1_is_stbepx = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0011011111); +assign ex1_is_stdepx = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0010011101); +assign ex1_is_sthepx = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0110011111); +assign ex1_is_stwepx = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0010011111); +assign ex0_is_lbepx = (rv_lq_ex0_instr[0:5] == 6'b011111 & rv_lq_ex0_instr[21:30] == 10'b0001011111); +assign ex0_is_lhepx = (rv_lq_ex0_instr[0:5] == 6'b011111 & rv_lq_ex0_instr[21:30] == 10'b0100011111); +assign ex0_is_lwepx = (rv_lq_ex0_instr[0:5] == 6'b011111 & rv_lq_ex0_instr[21:30] == 10'b0000011111); +assign ex0_is_ldepx = (rv_lq_ex0_instr[0:5] == 6'b011111 & rv_lq_ex0_instr[21:30] == 10'b0000011101); +assign ex0_is_dcbfep = (rv_lq_ex0_instr[0:5] == 6'b011111 & rv_lq_ex0_instr[21:30] == 10'b0001111111); +assign ex0_is_dcbtep = (rv_lq_ex0_instr[0:5] == 6'b011111 & rv_lq_ex0_instr[21:30] == 10'b0100111111); +assign ex0_is_dcbtstep = (rv_lq_ex0_instr[0:5] == 6'b011111 & rv_lq_ex0_instr[21:30] == 10'b0011111111); +assign ex0_is_dcbstep = (rv_lq_ex0_instr[0:5] == 6'b011111 & rv_lq_ex0_instr[21:30] == 10'b0000111111); +assign ex0_is_icbiep = (rv_lq_ex0_instr[0:5] == 6'b011111 & rv_lq_ex0_instr[21:30] == 10'b1111011111); +assign ex0_is_dcbzep = (rv_lq_ex0_instr[0:5] == 6'b011111 & rv_lq_ex0_instr[21:30] == 10'b1111111111); +assign ex0_is_stbepx = (rv_lq_ex0_instr[0:5] == 6'b011111 & rv_lq_ex0_instr[21:30] == 10'b0011011111); +assign ex0_is_sthepx = (rv_lq_ex0_instr[0:5] == 6'b011111 & rv_lq_ex0_instr[21:30] == 10'b0110011111); +assign ex0_is_stwepx = (rv_lq_ex0_instr[0:5] == 6'b011111 & rv_lq_ex0_instr[21:30] == 10'b0010011111); +assign ex0_is_stdepx = (rv_lq_ex0_instr[0:5] == 6'b011111 & rv_lq_ex0_instr[21:30] == 10'b0010011101); +assign ex0_is_icswepx = (rv_lq_ex0_instr[0:5] == 6'b011111 & rv_lq_ex0_instr[21:30] == 10'b1110110110); +assign ex0_is_larx = (rv_lq_ex0_instr[0:5] == 6'b011111) & (rv_lq_ex0_instr[21:23] == 3'b000) & (rv_lq_ex0_instr[26:30] == 5'b10100); +assign ex0_is_stcx = (rv_lq_ex0_instr[0:5] == 6'b011111) & (rv_lq_ex0_instr[26:30] == 5'b10110) & + ((rv_lq_ex0_instr[21:25] == 5'b10101) | (rv_lq_ex0_instr[21:25] == 5'b10110) | + (rv_lq_ex0_instr[21:25] == 5'b00100) | (rv_lq_ex0_instr[21:25] == 5'b00110)) ; +assign ex0_is_ldawx = (rv_lq_ex0_instr[0:5] == 6'b011111) & (rv_lq_ex0_instr[21:30] == 10'b0011010100); +assign ex0_is_icswxdot = (rv_lq_ex0_instr[0:5] == 6'b011111) & (rv_lq_ex0_instr[22:24] == 3'b110) & (rv_lq_ex0_instr[26:31] == 6'b101101); + +//---------------------------------------------------------------------------------------------------------------------------------------- +// Latch Instances +//---------------------------------------------------------------------------------------------------------------------------------------- + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_msr_gs_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_msr_gs_offset:spr_msr_gs_offset + `THREADS - 1]), + .scout(sov[spr_msr_gs_offset:spr_msr_gs_offset + `THREADS - 1]), + .din(spr_msr_gs_d), + .dout(spr_msr_gs_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_msr_pr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_msr_pr_offset:spr_msr_pr_offset + `THREADS - 1]), + .scout(sov[spr_msr_pr_offset:spr_msr_pr_offset + `THREADS - 1]), + .din(spr_msr_pr_d), + .dout(spr_msr_pr_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_msr_ucle_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_msr_ucle_offset:spr_msr_ucle_offset + `THREADS - 1]), + .scout(sov[spr_msr_ucle_offset:spr_msr_ucle_offset + `THREADS - 1]), + .din(spr_msr_ucle_d), + .dout(spr_msr_ucle_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_msrp_uclep_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_msrp_uclep_offset:spr_msrp_uclep_offset + `THREADS - 1]), + .scout(sov[spr_msrp_uclep_offset:spr_msrp_uclep_offset + `THREADS - 1]), + .din(spr_msrp_uclep_d), + .dout(spr_msrp_uclep_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_ccr2_en_pc_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_ccr2_en_pc_offset]), + .scout(sov[spr_ccr2_en_pc_offset]), + .din(spr_ccr2_en_pc_d), + .dout(spr_ccr2_en_pc_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_ccr2_en_ditc_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_ccr2_en_ditc_offset]), + .scout(sov[spr_ccr2_en_ditc_offset]), + .din(spr_ccr2_en_ditc_d), + .dout(spr_ccr2_en_ditc_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_ccr2_en_icswx_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_ccr2_en_icswx_offset]), + .scout(sov[spr_ccr2_en_icswx_offset]), + .din(spr_ccr2_en_icswx_d), + .dout(spr_ccr2_en_icswx_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_vld_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_vld_offset]), + .scout(sov[ex0_vld_offset]), + .din(ex0_vld_d), + .dout(ex0_vld_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_vld_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_vld_offset]), + .scout(sov[ex1_vld_offset]), + .din(ex1_vld_d), + .dout(ex1_vld_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_vld_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_vld_offset]), + .scout(sov[ex2_vld_offset]), + .din(ex2_vld_d), + .dout(ex2_vld_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_vld_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_vld_offset]), + .scout(sov[ex3_vld_offset]), + .din(ex3_vld_d), + .dout(ex3_vld_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_vld_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_vld_offset]), + .scout(sov[ex4_vld_offset]), + .din(ex4_vld_d), + .dout(ex4_vld_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_vld_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_vld_offset]), + .scout(sov[ex5_vld_offset]), + .din(ex5_vld_d), + .dout(ex5_vld_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_stg_act_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_stg_act_offset]), + .scout(sov[ex0_stg_act_offset]), + .din(ex0_stg_act_d), + .dout(ex0_stg_act_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_stg_act_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_stg_act_offset]), + .scout(sov[ex1_stg_act_offset]), + .din(ex1_stg_act_d), + .dout(ex1_stg_act_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_stg_act_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_stg_act_offset]), + .scout(sov[ex2_stg_act_offset]), + .din(ex2_stg_act_d), + .dout(ex2_stg_act_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_stg_act_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_stg_act_offset]), + .scout(sov[ex3_stg_act_offset]), + .din(ex3_stg_act_d), + .dout(ex3_stg_act_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_stg_act_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_stg_act_offset]), + .scout(sov[ex4_stg_act_offset]), + .din(ex4_stg_act_d), + .dout(ex4_stg_act_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_stg_act_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_stg_act_offset]), + .scout(sov[ex5_stg_act_offset]), + .din(ex5_stg_act_d), + .dout(ex5_stg_act_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_stg_act_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_stg_act_offset]), + .scout(sov[ex6_stg_act_offset]), + .din(ex6_stg_act_d), + .dout(ex6_stg_act_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex7_stg_act_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex7_stg_act_offset]), + .scout(sov[ex7_stg_act_offset]), + .din(ex7_stg_act_d), + .dout(ex7_stg_act_q) +); + +tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex1_ucode_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex0_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_ucode_offset:ex1_ucode_offset + 2 - 1]), + .scout(sov[ex1_ucode_offset:ex1_ucode_offset + 2 - 1]), + .din(ex1_ucode_d), + .dout(ex1_ucode_q) +); + +tri_rlmreg_p #(.WIDTH(`UCODE_ENTRIES_ENC), .INIT(0), .NEEDS_SRESET(1)) ex1_ucode_cnt_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex0_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_ucode_cnt_offset:ex1_ucode_cnt_offset + `UCODE_ENTRIES_ENC - 1]), + .scout(sov[ex1_ucode_cnt_offset:ex1_ucode_cnt_offset + `UCODE_ENTRIES_ENC - 1]), + .din(ex1_ucode_cnt_d), + .dout(ex1_ucode_cnt_q) +); + +tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) ex1_instr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_instr_offset:ex1_instr_offset + 32 - 1]), + .scout(sov[ex1_instr_offset:ex1_instr_offset + 32 - 1]), + .din(ex1_instr_d), + .dout(ex1_instr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_is_any_load_dac_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_is_any_load_dac_offset]), + .scout(sov[ex2_is_any_load_dac_offset]), + .din(ex2_is_any_load_dac_d), + .dout(ex2_is_any_load_dac_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_is_any_store_dac_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_is_any_store_dac_offset]), + .scout(sov[ex2_is_any_store_dac_offset]), + .din(ex2_is_any_store_dac_d), + .dout(ex2_is_any_store_dac_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_dir_rd_act_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_dir_rd_act_offset]), + .scout(sov[ex2_dir_rd_act_offset]), + .din(ex2_dir_rd_act_d), + .dout(ex2_dir_rd_act_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex0_tid_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_tid_offset:ex0_tid_offset + `THREADS - 1]), + .scout(sov[ex0_tid_offset:ex0_tid_offset + `THREADS - 1]), + .din(rv_lq_vld), + .dout(ex0_tid_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex1_tid_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex0_stq2_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_tid_offset:ex1_tid_offset + `THREADS - 1]), + .scout(sov[ex1_tid_offset:ex1_tid_offset + `THREADS - 1]), + .din(ex0_iss_stq2_tid), + .dout(ex1_tid_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex2_tid_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_stg_act_d), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_tid_offset:ex2_tid_offset + `THREADS - 1]), + .scout(sov[ex2_tid_offset:ex2_tid_offset + `THREADS - 1]), + .din(ex1_tid), + .dout(ex2_tid_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex3_tid_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_tid_offset:ex3_tid_offset + `THREADS - 1]), + .scout(sov[ex3_tid_offset:ex3_tid_offset + `THREADS - 1]), + .din(ex2_tid_q), + .dout(ex3_tid_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex4_tid_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_tid_offset:ex4_tid_offset + `THREADS - 1]), + .scout(sov[ex4_tid_offset:ex4_tid_offset + `THREADS - 1]), + .din(ex3_tid_q), + .dout(ex4_tid_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_s1_vld_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex0_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_s1_vld_offset]), + .scout(sov[ex1_s1_vld_offset]), + .din(rv_lq_ex0_s1_v), + .dout(ex1_s1_vld_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_s2_vld_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex0_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_s2_vld_offset]), + .scout(sov[ex1_s2_vld_offset]), + .din(rv_lq_ex0_s2_v), + .dout(ex1_s2_vld_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_t1_we_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_t1_we_offset]), + .scout(sov[ex1_t1_we_offset]), + .din(ex1_t1_we_d), + .dout(ex1_t1_we_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_t1_we_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_t1_we_offset]), + .scout(sov[ex2_t1_we_offset]), + .din(ex2_t1_we_d), + .dout(ex2_t1_we_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_t1_we_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_t1_we_offset]), + .scout(sov[ex3_t1_we_offset]), + .din(ex3_t1_we_d), + .dout(ex3_t1_we_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_t1_we_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_t1_we_offset]), + .scout(sov[ex4_t1_we_offset]), + .din(ex4_t1_we_d), + .dout(ex4_t1_we_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_t1_we_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_t1_we_offset]), + .scout(sov[ex5_t1_we_offset]), + .din(ex5_t1_we_d), + .dout(ex5_t1_we_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_t1_we_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_t1_we_offset]), + .scout(sov[ex6_t1_we_offset]), + .din(ex6_t1_we_d), + .dout(ex6_t1_we_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq_xu_ex5_act_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lq_xu_ex5_act_offset]), + .scout(sov[lq_xu_ex5_act_offset]), + .din(lq_xu_ex5_act_d), + .dout(lq_xu_ex5_act_q) +); + +tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) ex1_t1_wa_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex0_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_t1_wa_offset:ex1_t1_wa_offset + `GPR_POOL_ENC - 1]), + .scout(sov[ex1_t1_wa_offset:ex1_t1_wa_offset + `GPR_POOL_ENC - 1]), + .din(rv_lq_ex0_t1_p), + .dout(ex1_t1_wa_q) +); + +tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) ex1_t3_wa_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex0_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_t3_wa_offset:ex1_t3_wa_offset + `GPR_POOL_ENC - 1]), + .scout(sov[ex1_t3_wa_offset:ex1_t3_wa_offset + `GPR_POOL_ENC - 1]), + .din(rv_lq_ex0_t3_p), + .dout(ex1_t3_wa_q) +); + +tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex1_itag_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex0_stq2_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_itag_offset:ex1_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[ex1_itag_offset:ex1_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(ex0_iss_stq2_itag), + .dout(ex1_itag_q) +); + +tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex2_itag_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_stq3_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_itag_offset:ex2_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[ex2_itag_offset:ex2_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(ex1_itag), + .dout(ex2_itag_q) +); + +tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) release_itag_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[release_itag_offset:release_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[release_itag_offset:release_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(release_itag_d), + .dout(release_itag_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) release_tid_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[release_tid_offset:release_tid_offset + `THREADS - 1]), + .scout(sov[release_tid_offset:release_tid_offset + `THREADS - 1]), + .din(release_tid_d), + .dout(release_tid_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) release_itag_vld_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[release_itag_vld_offset]), + .scout(sov[release_itag_vld_offset]), + .din(release_itag_vld_d), + .dout(release_itag_vld_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_needs_release_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_needs_release_offset]), + .scout(sov[ex0_needs_release_offset]), + .din(ex0_needs_release_d), + .dout(ex0_needs_release_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_needs_release_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_needs_release_offset]), + .scout(sov[ex1_needs_release_offset]), + .din(ex1_needs_release_d), + .dout(ex1_needs_release_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_needs_release_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_needs_release_offset]), + .scout(sov[ex2_needs_release_offset]), + .din(ex2_needs_release_d), + .dout(ex2_needs_release_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_physical_upd_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_physical_upd_offset]), + .scout(sov[ex2_physical_upd_offset]), + .din(ex2_physical_upd_d), + .dout(ex2_physical_upd_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_req_abort_rpt_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_req_abort_rpt_offset]), + .scout(sov[ex3_req_abort_rpt_offset]), + .din(ex3_req_abort_rpt_d), + .dout(ex3_req_abort_rpt_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_req_abort_rpt_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_req_abort_rpt_offset]), + .scout(sov[ex4_req_abort_rpt_offset]), + .din(ex4_req_abort_rpt_d), + .dout(ex4_req_abort_rpt_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_req_abort_rpt_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_req_abort_rpt_offset]), + .scout(sov[ex5_req_abort_rpt_offset]), + .din(ex5_req_abort_rpt_d), + .dout(ex5_req_abort_rpt_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_axu_physical_upd_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_axu_physical_upd_offset]), + .scout(sov[ex2_axu_physical_upd_offset]), + .din(ex2_axu_physical_upd_d), + .dout(ex2_axu_physical_upd_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_axu_abort_rpt_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_axu_abort_rpt_offset]), + .scout(sov[ex3_axu_abort_rpt_offset]), + .din(ex3_axu_abort_rpt_d), + .dout(ex3_axu_abort_rpt_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_axu_abort_rpt_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_axu_abort_rpt_offset]), + .scout(sov[ex4_axu_abort_rpt_offset]), + .din(ex4_axu_abort_rpt_d), + .dout(ex4_axu_abort_rpt_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_axu_abort_rpt_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_axu_abort_rpt_offset]), + .scout(sov[ex5_axu_abort_rpt_offset]), + .din(ex5_axu_abort_rpt_d), + .dout(ex5_axu_abort_rpt_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_release_attmp_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_release_attmp_offset]), + .scout(sov[ex1_release_attmp_offset]), + .din(ex1_release_attmp_d), + .dout(ex1_release_attmp_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq3_release_attmp_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq3_release_attmp_offset]), + .scout(sov[stq3_release_attmp_offset]), + .din(stq3_release_attmp_d), + .dout(stq3_release_attmp_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq3_needs_release_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq3_needs_release_offset]), + .scout(sov[stq3_needs_release_offset]), + .din(stq3_needs_release_d), + .dout(stq3_needs_release_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_release_vld_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq2_release_vld_offset]), + .scout(sov[stq2_release_vld_offset]), + .din(stq2_release_vld_d), + .dout(stq2_release_vld_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq3_release_vld_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq3_release_vld_offset]), + .scout(sov[stq3_release_vld_offset]), + .din(stq3_release_vld_d), + .dout(stq3_release_vld_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_release_vld_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq4_release_vld_offset]), + .scout(sov[stq4_release_vld_offset]), + .din(stq4_release_vld_d), + .dout(stq4_release_vld_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq5_release_vld_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq5_release_vld_offset]), + .scout(sov[stq5_release_vld_offset]), + .din(stq5_release_vld_d), + .dout(stq5_release_vld_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq6_release_vld_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq6_release_vld_offset]), + .scout(sov[stq6_release_vld_offset]), + .din(stq6_release_vld_d), + .dout(stq6_release_vld_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq7_release_vld_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq7_release_vld_offset]), + .scout(sov[stq7_release_vld_offset]), + .din(stq7_release_vld_d), + .dout(stq7_release_vld_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_lq_hold_req_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[xu_lq_hold_req_offset]), + .scout(sov[xu_lq_hold_req_offset]), + .din(xu_lq_hold_req_d), + .dout(xu_lq_hold_req_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mm_hold_req_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[mm_hold_req_offset]), + .scout(sov[mm_hold_req_offset]), + .din(mm_hold_req_d), + .dout(mm_hold_req_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mm_hold_done_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[mm_hold_done_offset]), + .scout(sov[mm_hold_done_offset]), + .din(mm_hold_done_d), + .dout(mm_hold_done_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rv1_hold_taken_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rv1_hold_taken_offset]), + .scout(sov[rv1_hold_taken_offset]), + .din(rv1_hold_taken_d), + .dout(rv1_hold_taken_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_hold_taken_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_hold_taken_offset]), + .scout(sov[ex0_hold_taken_offset]), + .din(ex0_hold_taken_d), + .dout(ex0_hold_taken_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_hold_taken_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_hold_taken_offset]), + .scout(sov[ex1_hold_taken_offset]), + .din(ex1_hold_taken_d), + .dout(ex1_hold_taken_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rv1_back_inv_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rv1_back_inv_offset]), + .scout(sov[rv1_back_inv_offset]), + .din(rv1_back_inv_d), + .dout(rv1_back_inv_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_back_inv_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_back_inv_offset]), + .scout(sov[ex0_back_inv_offset]), + .din(ex0_back_inv_d), + .dout(ex0_back_inv_q) +); + +tri_rlmreg_p #(.WIDTH(`REAL_IFAR_WIDTH-`CL_SIZE), .INIT(0), .NEEDS_SRESET(1)) ex0_back_inv_addr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rv1_back_inv_q), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_back_inv_addr_offset:ex0_back_inv_addr_offset + (`REAL_IFAR_WIDTH-`CL_SIZE) - 1]), + .scout(sov[ex0_back_inv_addr_offset:ex0_back_inv_addr_offset + (`REAL_IFAR_WIDTH-`CL_SIZE) - 1]), + .din(ex0_back_inv_addr_d), + .dout(ex0_back_inv_addr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_selimm_addr_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_selimm_addr_val_offset]), + .scout(sov[ex1_selimm_addr_val_offset]), + .din(ex1_selimm_addr_val_d), + .dout(ex1_selimm_addr_val_q) +); + +tri_rlmreg_p #(.WIDTH((64-`CL_SIZE)), .INIT(0), .NEEDS_SRESET(1)) ex1_selimm_addr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex0_selimm_addr_val), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_selimm_addr_offset:ex1_selimm_addr_offset + (64-`CL_SIZE) - 1]), + .scout(sov[ex1_selimm_addr_offset:ex1_selimm_addr_offset + (64-`CL_SIZE) - 1]), + .din(ex1_selimm_addr_d), + .dout(ex1_selimm_addr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_arr_rd_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_arr_rd_val_offset]), + .scout(sov[ex0_arr_rd_val_offset]), + .din(ex0_arr_rd_val_d), + .dout(ex0_arr_rd_val_q) +); + +tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) ex0_arr_rd_congr_cl_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_arr_rd_congr_cl_offset:ex0_arr_rd_congr_cl_offset + 6 - 1]), + .scout(sov[ex0_arr_rd_congr_cl_offset:ex0_arr_rd_congr_cl_offset + 6 - 1]), + .din(ex0_arr_rd_congr_cl_d), + .dout(ex0_arr_rd_congr_cl_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_derat_snoop_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_derat_snoop_val_offset]), + .scout(sov[ex0_derat_snoop_val_offset]), + .din(ex0_derat_snoop_val_d), + .dout(ex0_derat_snoop_val_q) +); + +tri_rlmreg_p #(.WIDTH(52), .INIT(0), .NEEDS_SRESET(1)) ex0_derat_snoop_addr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(derat_rv1_snoop_val), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_derat_snoop_addr_offset:ex0_derat_snoop_addr_offset + 52 - 1]), + .scout(sov[ex0_derat_snoop_addr_offset:ex0_derat_snoop_addr_offset + 52 - 1]), + .din(ex0_derat_snoop_addr_d), + .dout(ex0_derat_snoop_addr_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) iu_lq_cp_flush_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[iu_lq_cp_flush_offset:iu_lq_cp_flush_offset + `THREADS - 1]), + .scout(sov[iu_lq_cp_flush_offset:iu_lq_cp_flush_offset + `THREADS - 1]), + .din(iu_lq_cp_flush_d), + .dout(iu_lq_cp_flush_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq6_mftgpr_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq6_mftgpr_val_offset]), + .scout(sov[stq6_mftgpr_val_offset]), + .din(stq6_mftgpr_val_d), + .dout(stq6_mftgpr_val_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq7_mftgpr_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq7_mftgpr_val_offset]), + .scout(sov[stq7_mftgpr_val_offset]), + .din(stq7_mftgpr_val_d), + .dout(stq7_mftgpr_val_q) +); + +tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) stq2_release_itag_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq2_release_itag_offset:stq2_release_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[stq2_release_itag_offset:stq2_release_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(stq2_release_itag_d), + .dout(stq2_release_itag_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) stq2_release_tid_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq2_release_tid_offset:stq2_release_tid_offset + `THREADS - 1]), + .scout(sov[stq2_release_tid_offset:stq2_release_tid_offset + `THREADS - 1]), + .din(stq2_release_tid_d), + .dout(stq2_release_tid_q) +); + +assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in}; +assign scan_out = sov[0]; + +endmodule diff --git a/dev/verilog/work/lq_derat.v b/dev/verilog/work/lq_derat.v new file mode 100755 index 0000000..61ba5e2 --- /dev/null +++ b/dev/verilog/work/lq_derat.v @@ -0,0 +1,10099 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//****************************************************************************** +//* TITLE: Data Side Effective to Real Address Translation +//* NAME: lq_derat.vhdl +//****************************************************************************** + +`include "tri_a2o.vh" + + + + + +module lq_derat( + gnd, + vdd, + vcs, + nclk, + pc_xu_init_reset, + pc_xu_ccflush_dc, + tc_scan_dis_dc_b, + tc_scan_diag_dc, + tc_lbist_en_dc, + an_ac_atpg_en_dc, + an_ac_grffence_en_dc, + lcb_d_mode_dc, + lcb_clkoff_dc_b, + lcb_act_dis_dc, + lcb_mpw1_dc_b, + lcb_mpw2_dc_b, + lcb_delay_lclkr_dc, + pc_func_sl_thold_2, + pc_func_slp_sl_thold_2, + pc_func_slp_nsl_thold_2, + pc_cfg_slp_sl_thold_2, + pc_regf_slp_sl_thold_2, + pc_time_sl_thold_2, + pc_sg_2, + pc_fce_2, + cam_clkoff_dc_b, + cam_act_dis_dc, + cam_d_mode_dc, + cam_delay_lclkr_dc, + cam_mpw1_dc_b, + cam_mpw2_dc_b, + ac_func_scan_in, + ac_func_scan_out, + ac_ccfg_scan_in, + ac_ccfg_scan_out, + time_scan_in, + time_scan_out, + regf_scan_in, + regf_scan_out, + dec_derat_ex1_derat_act, + dec_derat_ex0_val, + dec_derat_ex0_is_extload, + dec_derat_ex0_is_extstore, + dec_derat_ex1_itag, + dec_derat_ex1_pfetch_val, + dec_derat_ex1_is_load, + dec_derat_ex1_is_store, + dec_derat_ex1_is_touch, + dec_derat_ex1_icbtls_instr, + dec_derat_ex1_icblc_instr, + dec_derat_ex1_ra_eq_ea, + dec_derat_ex1_byte_rev, + byp_derat_ex2_req_aborted, + dcc_derat_ex3_strg_noop, + dcc_derat_ex5_blk_tlb_req, + dcc_derat_ex6_cplt, + dcc_derat_ex6_cplt_itag, + dir_derat_ex2_epn_arr, + dir_derat_ex2_epn_nonarr, + iu_lq_recirc_val, + iu_lq_cp_next_itag, + lsq_ctl_oldest_tid, + lsq_ctl_oldest_itag, + derat_dcc_ex4_restart, + derat_dcc_ex4_setHold, + derat_dcc_clr_hold, + derat_dcc_emq_idle, + xu_lq_act, + xu_lq_val, + xu_lq_is_eratre, + xu_lq_is_eratwe, + xu_lq_is_eratsx, + xu_lq_is_eratilx, + xu_lq_ws, + xu_lq_ra_entry, + xu_lq_rs_data, + lq_xu_ex5_data, + lq_xu_ord_par_err, + lq_xu_ord_read_done, + lq_xu_ord_write_done, + iu_lq_isync, + iu_lq_csync, + mm_derat_rel_val, + mm_derat_rel_data, + mm_derat_rel_emq, + mm_lq_itag, + mm_lq_tlb_miss, + mm_lq_tlb_inelig, + mm_lq_pt_fault, + mm_lq_lrat_miss, + mm_lq_tlb_multihit, + mm_lq_tlb_par_err, + mm_lq_lru_par_err, + lsq_ctl_rv0_binv_val, + mm_lq_snoop_coming, + mm_lq_snoop_val, + mm_lq_snoop_attr, + mm_lq_snoop_vpn, + lq_mm_snoop_ack, + derat_dec_rv1_snoop_addr, + derat_rv1_snoop_val, + iu_lq_cp_flush, + derat_dec_hole_all, + derat_dcc_ex3_e, + derat_dcc_ex3_itagHit, + derat_dcc_ex4_rpn, + derat_dcc_ex4_wimge, + derat_dcc_ex4_u, + derat_dcc_ex4_wlc, + derat_dcc_ex4_attr, + derat_dcc_ex4_vf, + derat_dcc_ex4_miss, + derat_dcc_ex4_tlb_err, + derat_dcc_ex4_dsi, + derat_dcc_ex4_par_err_flush, + derat_dcc_ex4_multihit_err_flush, + derat_dcc_ex4_par_err_det, + derat_dcc_ex4_multihit_err_det, + derat_dcc_ex4_noop_touch, + derat_dcc_ex4_tlb_inelig, + derat_dcc_ex4_pt_fault, + derat_dcc_ex4_lrat_miss, + derat_dcc_ex4_tlb_multihit, + derat_dcc_ex4_tlb_par_err, + derat_dcc_ex4_lru_par_err, + derat_fir_par_err, + derat_fir_multihit, + lq_mm_req, + lq_mm_req_nonspec, + lq_mm_req_itag, + lq_mm_req_epn, + lq_mm_thdid, + lq_mm_req_emq, + lq_mm_ttype, + lq_mm_state, + lq_mm_lpid, + lq_mm_tid, + lq_mm_perf_dtlb, + lq_mm_mmucr0_we, + lq_mm_mmucr0, + lq_mm_mmucr1_we, + lq_mm_mmucr1, + spr_xucr0_clkg_ctl_b1, + xu_lq_spr_msr_hv, + xu_lq_spr_msr_pr, + xu_lq_spr_msr_ds, + xu_lq_spr_msr_cm, + xu_lq_spr_ccr2_notlb, + xu_lq_spr_ccr2_dfrat, + xu_lq_spr_ccr2_dfratsc, + xu_lq_spr_xucr4_mmu_mchk, + spr_derat_eplc_wr, + spr_derat_eplc_epr, + spr_derat_eplc_eas, + spr_derat_eplc_egs, + spr_derat_eplc_elpid, + spr_derat_eplc_epid, + spr_derat_epsc_wr, + spr_derat_epsc_epr, + spr_derat_epsc_eas, + spr_derat_epsc_egs, + spr_derat_epsc_elpid, + spr_derat_epsc_epid, + mm_lq_pid, + mm_lq_mmucr0, + mm_lq_mmucr1, + derat_xu_debug_group0, + derat_xu_debug_group1, + derat_xu_debug_group2, + derat_xu_debug_group3 +); + + // Parameters used from tri_a2o.vh + + // parameter EXPAND_TYPE = 1; + // parameter GPR_WIDTH_ENC = 6; + // parameter ITAG_SIZE_ENC = 7; + // parameter EMQ_ENTRIES = 4; + // parameter THREADS = 2; + + + + + + inout gnd; + + + inout vdd; + + + inout vcs; + + + (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) + + input [0:`NCLK_WIDTH-1] nclk; + input pc_xu_init_reset; + input pc_xu_ccflush_dc; + input tc_scan_dis_dc_b; + input tc_scan_diag_dc; + input tc_lbist_en_dc; + input an_ac_atpg_en_dc; + input an_ac_grffence_en_dc; + + input lcb_d_mode_dc; + input lcb_clkoff_dc_b; + input lcb_act_dis_dc; + input [0:4] lcb_mpw1_dc_b; + input lcb_mpw2_dc_b; + input [0:4] lcb_delay_lclkr_dc; + + input pc_func_sl_thold_2; + input pc_func_slp_sl_thold_2; + input pc_func_slp_nsl_thold_2; + input pc_cfg_slp_sl_thold_2; + input pc_regf_slp_sl_thold_2; + input pc_time_sl_thold_2; + input pc_sg_2; + input pc_fce_2; + input cam_clkoff_dc_b; + input cam_act_dis_dc; + input cam_d_mode_dc; + input [0:4] cam_delay_lclkr_dc; + input [0:4] cam_mpw1_dc_b; + input cam_mpw2_dc_b; + + + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + + input [0:1] ac_func_scan_in; + + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + + output [0:1] ac_func_scan_out; + + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + + input ac_ccfg_scan_in; + + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + + output ac_ccfg_scan_out; + + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + + input time_scan_in; + + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + + output time_scan_out; + + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + + input [0:6] regf_scan_in; + + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + + output [0:6] regf_scan_out; + + input dec_derat_ex1_derat_act; + input [0:`THREADS-1] dec_derat_ex0_val; + input dec_derat_ex0_is_extload; + input dec_derat_ex0_is_extstore; + input [0:`ITAG_SIZE_ENC-1] dec_derat_ex1_itag; + input [0:`THREADS-1] dec_derat_ex1_pfetch_val; + input dec_derat_ex1_is_load; + input dec_derat_ex1_is_store; + input dec_derat_ex1_is_touch; + input dec_derat_ex1_icbtls_instr; + input dec_derat_ex1_icblc_instr; + input dec_derat_ex1_ra_eq_ea; + input dec_derat_ex1_byte_rev; + input byp_derat_ex2_req_aborted; + input dcc_derat_ex3_strg_noop; + input dcc_derat_ex5_blk_tlb_req; + input [0:`THREADS-1] dcc_derat_ex6_cplt; + input [0:`ITAG_SIZE_ENC-1] dcc_derat_ex6_cplt_itag; + + input [64-(2**`GPR_WIDTH_ENC):51] dir_derat_ex2_epn_arr; + input [64-(2**`GPR_WIDTH_ENC):51] dir_derat_ex2_epn_nonarr; + input [0:`THREADS-1] iu_lq_recirc_val; + input [0:(`THREADS*`ITAG_SIZE_ENC)-1] iu_lq_cp_next_itag; + + input [0:`THREADS-1] lsq_ctl_oldest_tid; + input [0:`ITAG_SIZE_ENC-1] lsq_ctl_oldest_itag; + + output derat_dcc_ex4_restart; + + output derat_dcc_ex4_setHold; + output [0:`THREADS-1] derat_dcc_clr_hold; + output [0:`THREADS-1] derat_dcc_emq_idle; + input xu_lq_act; + input [0:`THREADS-1] xu_lq_val; + input xu_lq_is_eratre; + input xu_lq_is_eratwe; + input xu_lq_is_eratsx; + input xu_lq_is_eratilx; + input [0:1] xu_lq_ws; + input [0:4] xu_lq_ra_entry; + input [64-(2**`GPR_WIDTH_ENC):63] xu_lq_rs_data; + output [64-(2**`GPR_WIDTH_ENC):63] lq_xu_ex5_data; + output lq_xu_ord_par_err; + output lq_xu_ord_read_done; + output lq_xu_ord_write_done; + + input iu_lq_isync; + input iu_lq_csync; + + input [0:4] mm_derat_rel_val; + input [0:131] mm_derat_rel_data; + input [0:`EMQ_ENTRIES-1] mm_derat_rel_emq; + input [0:`ITAG_SIZE_ENC-1] mm_lq_itag; + input [0:`THREADS-1] mm_lq_tlb_miss; + input [0:`THREADS-1] mm_lq_tlb_inelig; + input [0:`THREADS-1] mm_lq_pt_fault; + input [0:`THREADS-1] mm_lq_lrat_miss; + input [0:`THREADS-1] mm_lq_tlb_multihit; + input [0:`THREADS-1] mm_lq_tlb_par_err; + input [0:`THREADS-1] mm_lq_lru_par_err; + + input lsq_ctl_rv0_binv_val; + input mm_lq_snoop_coming; + input mm_lq_snoop_val; + input [0:25] mm_lq_snoop_attr; + input [0:51] mm_lq_snoop_vpn; + output lq_mm_snoop_ack; + output [0:51] derat_dec_rv1_snoop_addr; + output derat_rv1_snoop_val; + input [0:`THREADS-1] iu_lq_cp_flush; + output derat_dec_hole_all; + output derat_dcc_ex3_e; + output derat_dcc_ex3_itagHit; + + output [22:51] derat_dcc_ex4_rpn; + output [0:4] derat_dcc_ex4_wimge; + output [0:3] derat_dcc_ex4_u; + output [0:1] derat_dcc_ex4_wlc; + output [0:5] derat_dcc_ex4_attr; + output derat_dcc_ex4_vf; + output derat_dcc_ex4_miss; + output derat_dcc_ex4_tlb_err; + output derat_dcc_ex4_dsi; + output derat_dcc_ex4_par_err_flush; + output derat_dcc_ex4_multihit_err_flush; + output derat_dcc_ex4_par_err_det; + output derat_dcc_ex4_multihit_err_det; + output derat_dcc_ex4_noop_touch; + output derat_dcc_ex4_tlb_inelig; + output derat_dcc_ex4_pt_fault; + output derat_dcc_ex4_lrat_miss; + output derat_dcc_ex4_tlb_multihit; + output derat_dcc_ex4_tlb_par_err; + output derat_dcc_ex4_lru_par_err; + + output derat_fir_par_err; + output derat_fir_multihit; + + output lq_mm_req; + output lq_mm_req_nonspec; + output [0:`ITAG_SIZE_ENC-1] lq_mm_req_itag; + output [64-(2**`GPR_WIDTH_ENC):51] lq_mm_req_epn; + output [0:`THREADS-1] lq_mm_thdid; + output [0:`EMQ_ENTRIES-1] lq_mm_req_emq; + output [0:1] lq_mm_ttype; + output [0:3] lq_mm_state; + output [0:7] lq_mm_lpid; + output [0:13] lq_mm_tid; + output [0:`THREADS-1] lq_mm_mmucr0_we; + output [0:17] lq_mm_mmucr0; + output [0:`THREADS-1] lq_mm_mmucr1_we; + output [0:4] lq_mm_mmucr1; + output [0:`THREADS-1] lq_mm_perf_dtlb; + input spr_xucr0_clkg_ctl_b1; + + input [0:`THREADS-1] xu_lq_spr_msr_hv; + input [0:`THREADS-1] xu_lq_spr_msr_pr; + input [0:`THREADS-1] xu_lq_spr_msr_ds; + input [0:`THREADS-1] xu_lq_spr_msr_cm; + input xu_lq_spr_ccr2_notlb; + input xu_lq_spr_ccr2_dfrat; + input [0:8] xu_lq_spr_ccr2_dfratsc; + input xu_lq_spr_xucr4_mmu_mchk; + + input [0:`THREADS-1] spr_derat_eplc_wr; + input [0:`THREADS-1] spr_derat_eplc_epr; + input [0:`THREADS-1] spr_derat_eplc_eas; + input [0:`THREADS-1] spr_derat_eplc_egs; + input [0:(8*`THREADS)-1] spr_derat_eplc_elpid; + input [0:(14*`THREADS)-1] spr_derat_eplc_epid; + + input [0:`THREADS-1] spr_derat_epsc_wr; + input [0:`THREADS-1] spr_derat_epsc_epr; + input [0:`THREADS-1] spr_derat_epsc_eas; + input [0:`THREADS-1] spr_derat_epsc_egs; + input [0:(8*`THREADS)-1] spr_derat_epsc_elpid; + input [0:(14*`THREADS)-1] spr_derat_epsc_epid; + + input [0:(`THREADS*14)-1] mm_lq_pid; + input [0:(`THREADS*20)-1] mm_lq_mmucr0; + input [0:9] mm_lq_mmucr1; + output [0:87] derat_xu_debug_group0; + output [0:87] derat_xu_debug_group1; + output [0:87] derat_xu_debug_group2; + output [0:87] derat_xu_debug_group3; + + //@@ Signal Declarations + wire [1:19] CAM_MASK_BITS_PT; + wire [1:31] EX3_FIRST_HIT_ENTRY_PT; + wire [1:32] EX3_MULTIHIT_B_PT; + wire [1:32] LRU_RMT_VEC_D_PT; + wire [1:161] LRU_SET_RESET_VEC_PT; + wire [1:31] LRU_WAY_ENCODE_PT; + //-------------------------- + // components + //-------------------------- + + //-------------------------- + // constants + //-------------------------- + parameter GPR_WIDTH = 2 ** `GPR_WIDTH_ENC; + parameter [0:2] EMQ_IDLE = 3'b100; + parameter [0:2] EMQ_RPEN = 3'b010; + parameter [0:2] EMQ_REXCP = 3'b001; + // Field/Signal sizes + parameter ttype_width = 12; + parameter state_width = 4; + parameter lpid_width = 8; + parameter pid_width = 14; + parameter pid_width_erat = 8; + parameter extclass_width = 2; + parameter tlbsel_width = 2; + parameter epn_width = 52; + parameter vpn_width = 61; + parameter rpn_width = 30; + parameter ws_width = 2; + parameter rs_is_width = 9; + parameter error_width = 3; + parameter cam_data_width = 84; + parameter array_data_width = 68; + parameter num_entry = 32; + parameter num_entry_log2 = 5; + parameter por_seq_width = 3; + parameter watermark_width = 5; + parameter eptr_width = 5; + parameter lru_width = 31; + parameter bcfg_width = 123; + parameter ex3_epn_width = 30; + // Generate flags + parameter check_parity = 1; + parameter MMU_Mode_Value = 1'b0; + parameter [0:1] TlbSel_Tlb = 2'b00; + parameter [0:1] TlbSel_IErat = 2'b10; + parameter [0:1] TlbSel_DErat = 2'b11; + parameter [0:2] CAM_PgSize_1GB = 3'b110; + parameter [0:2] CAM_PgSize_16MB = 3'b111; + parameter [0:2] CAM_PgSize_1MB = 3'b101; + parameter [0:2] CAM_PgSize_64KB = 3'b011; + parameter [0:2] CAM_PgSize_4KB = 3'b001; + parameter [0:3] WS0_PgSize_1GB = 4'b1010; + parameter [0:3] WS0_PgSize_16MB = 4'b0111; + parameter [0:3] WS0_PgSize_1MB = 4'b0101; + parameter [0:3] WS0_PgSize_64KB = 4'b0011; + parameter [0:3] WS0_PgSize_4KB = 4'b0001; + parameter eratpos_epn = 0; + parameter eratpos_x = 52; + parameter eratpos_size = 53; + parameter eratpos_v = 56; + parameter eratpos_thdid = 57; + parameter eratpos_class = 61; + parameter eratpos_extclass = 63; + parameter eratpos_wren = 65; + parameter eratpos_rpnrsvd = 66; + parameter eratpos_rpn = 70; + parameter eratpos_r = 100; + parameter eratpos_c = 101; + parameter eratpos_relsoon = 102; + parameter eratpos_wlc = 103; + parameter eratpos_resvattr = 105; + parameter eratpos_vf = 106; + parameter eratpos_ubits = 107; + parameter eratpos_wimge = 111; + parameter eratpos_usxwr = 116; + parameter eratpos_gs = 122; + parameter eratpos_ts = 123; + parameter eratpos_tid = 124; + parameter [0:2] PorSeq_Idle = 3'b000; + parameter [0:2] PorSeq_Stg1 = 3'b001; + parameter [0:2] PorSeq_Stg2 = 3'b011; + parameter [0:2] PorSeq_Stg3 = 3'b010; + parameter [0:2] PorSeq_Stg4 = 3'b110; + parameter [0:2] PorSeq_Stg5 = 3'b100; + parameter [0:2] PorSeq_Stg6 = 3'b101; + parameter [0:2] PorSeq_Stg7 = 3'b111; + parameter [0:num_entry_log2-1] Por_Wr_Entry_Num1 = 5'b11110; + parameter [0:num_entry_log2-1] Por_Wr_Entry_Num2 = 5'b11111; + // wr_cam_data ----------------------------------------------------------------- + // 0:51 - EPN + // 52 - X + // 53:55 - SIZE + // 56 - V + // 57:60 - ThdID + // 61:62 - Class + // 63:64 - ExtClass | TID_NZ + // 65 - TGS + // 66 - TS + // 67:74 - TID + // 75:78 - epn_cmpmasks: 34_39, 40_43, 44_47, 48_51 + // 79:82 - xbit_cmpmasks: 34_51, 40_51, 44_51, 48_51 + // 83 - parity for 75:82 + parameter [0:83] Por_Wr_Cam_Data1 = {52'b0000000000000000000000000000000011111111111111111111, 1'b0, 3'b001, 1'b1, 4'b1111, 2'b00, 2'b00, 2'b00, 8'b00000000, 8'b11110000, 1'b0}; + parameter [0:83] Por_Wr_Cam_Data2 = {52'b0000000000000000000000000000000000000000000000000000, 1'b0, 3'b001, 1'b1, 4'b1111, 2'b00, 2'b10, 2'b00, 8'b00000000, 8'b11110000, 1'b0}; + // 16x143 version, 42b RA + // wr_array_data + // 0:29 - RPN + // 30:31 - R,C + // 32:35 - ResvAttr + // 36:39 - U0-U3 + // 40:44 - WIMGE + // 45:46 - UX,SX + // 47:48 - UW,SW + // 49:50 - UR,SR + // 51:60 - CAM parity + // 61:67 - Array parity + parameter [0:67] Por_Wr_Array_Data1 = {30'b111111111111111111111111111111, 2'b00, 4'b0000, 4'b0000, 5'b01010, 2'b01, 2'b00, 2'b01, 10'b0000001000, 7'b0000000}; + parameter [0:67] Por_Wr_Array_Data2 = {30'b000000000000000000000000000000, 2'b00, 4'b0000, 4'b0000, 5'b01010, 2'b01, 2'b00, 2'b01, 10'b0000001010, 7'b0000000}; + + + parameter spr_msr_hv_offset = 0; + parameter spr_msr_pr_offset = spr_msr_hv_offset + `THREADS; + parameter spr_msr_ds_offset = spr_msr_pr_offset + `THREADS; + parameter spr_msr_cm_offset = spr_msr_ds_offset + `THREADS; + parameter spr_ccr2_notlb_offset = spr_msr_cm_offset + `THREADS; + parameter xucr4_mmu_mchk_offset = spr_ccr2_notlb_offset + 1; + parameter mchk_flash_inv_offset = xucr4_mmu_mchk_offset + 1; + parameter cp_next_val_offset = mchk_flash_inv_offset + 4; + parameter cp_next_itag_offset = cp_next_val_offset + `THREADS; + parameter ex2_byte_rev_offset = cp_next_itag_offset + `THREADS * `ITAG_SIZE_ENC; + parameter ex3_byte_rev_offset = ex2_byte_rev_offset + 1; + parameter ex1_valid_offset = ex3_byte_rev_offset + 1; + parameter ex1_ttype_offset = ex1_valid_offset + `THREADS; + parameter ex2_valid_offset = ex1_ttype_offset + 2; + parameter ex2_pfetch_val_offset = ex2_valid_offset + `THREADS; + parameter ex2_itag_offset = ex2_pfetch_val_offset + `THREADS; + parameter ex2_ttype_offset = ex2_itag_offset + `ITAG_SIZE_ENC; + parameter ex2_ws_offset = ex2_ttype_offset + ttype_width; + parameter ex2_rs_is_offset = ex2_ws_offset + ws_width; + parameter ex2_ra_entry_offset = ex2_rs_is_offset + rs_is_width; + parameter ex2_state_offset = ex2_ra_entry_offset + 5; + parameter ex2_pid_offset = ex2_state_offset + state_width; + parameter ex2_extclass_offset = ex2_pid_offset + pid_width; + parameter ex2_tlbsel_offset = ex2_extclass_offset + extclass_width; + parameter ex2_data_in_offset = ex2_tlbsel_offset + tlbsel_width; + parameter ex3_valid_offset = ex2_data_in_offset + GPR_WIDTH; + parameter ex3_pfetch_val_offset = ex3_valid_offset + `THREADS; + parameter ex3_itag_offset = ex3_pfetch_val_offset + `THREADS; + parameter ex3_ttype_offset = ex3_itag_offset + `ITAG_SIZE_ENC; + parameter ex3_ws_offset = ex3_ttype_offset + ttype_width; + parameter ex3_rs_is_offset = ex3_ws_offset + ws_width; + parameter ex3_ra_entry_offset = ex3_rs_is_offset + rs_is_width; + parameter ex3_state_offset = ex3_ra_entry_offset + 5; + parameter ex3_pid_offset = ex3_state_offset + state_width; + parameter ex3_extclass_offset = ex3_pid_offset + pid_width; + parameter ex3_tlbsel_offset = ex3_extclass_offset + extclass_width; + parameter ex4_valid_offset = ex3_tlbsel_offset + tlbsel_width; + parameter ex4_pfetch_val_offset = ex4_valid_offset + `THREADS; + parameter ex4_itag_offset = ex4_pfetch_val_offset + `THREADS; + parameter ex4_ttype_offset = ex4_itag_offset + `ITAG_SIZE_ENC; + parameter ex4_ws_offset = ex4_ttype_offset + ttype_width; + parameter ex4_rs_is_offset = ex4_ws_offset + ws_width; + parameter ex4_ra_entry_offset = ex4_rs_is_offset + rs_is_width; + parameter ex4_state_offset = ex4_ra_entry_offset + 5; + parameter ex4_pid_offset = ex4_state_offset + state_width; + parameter ex4_lpid_offset = ex4_pid_offset + pid_width; + parameter ex4_extclass_offset = ex4_lpid_offset + lpid_width; + parameter ex4_tlbsel_offset = ex4_extclass_offset + extclass_width; + parameter ex5_valid_offset = ex4_tlbsel_offset + tlbsel_width; + parameter ex5_pfetch_val_offset = ex5_valid_offset + `THREADS; + parameter ex5_itag_offset = ex5_pfetch_val_offset + `THREADS; + parameter ex5_ttype_offset = ex5_itag_offset + `ITAG_SIZE_ENC; + parameter ex5_ws_offset = ex5_ttype_offset + ttype_width; + parameter ex5_rs_is_offset = ex5_ws_offset + ws_width; + parameter ex5_ra_entry_offset = ex5_rs_is_offset + rs_is_width; + parameter ex5_state_offset = ex5_ra_entry_offset + 5; + parameter ex5_pid_offset = ex5_state_offset + state_width; + parameter ex5_lpid_offset = ex5_pid_offset + pid_width; + parameter ex5_extclass_offset = ex5_lpid_offset + lpid_width; + parameter ex5_tlbsel_offset = ex5_extclass_offset + extclass_width; + parameter ex6_valid_offset = ex5_tlbsel_offset + tlbsel_width; + parameter ex6_pfetch_val_offset = ex6_valid_offset + `THREADS; + parameter ex6_itag_offset = ex6_pfetch_val_offset + `THREADS; + parameter ex6_ttype_offset = ex6_itag_offset + `ITAG_SIZE_ENC; + parameter ex6_ws_offset = ex6_ttype_offset + ttype_width; + parameter ex6_rs_is_offset = ex6_ws_offset + ws_width; + parameter ex6_ra_entry_offset = ex6_rs_is_offset + rs_is_width; + parameter ex6_state_offset = ex6_ra_entry_offset + 5; + parameter ex6_pid_offset = ex6_state_offset + state_width; + parameter ex6_extclass_offset = ex6_pid_offset + pid_width; + parameter ex6_tlbsel_offset = ex6_extclass_offset + extclass_width; + parameter ex7_valid_offset = ex6_tlbsel_offset + tlbsel_width; + parameter ex7_pfetch_val_offset = ex7_valid_offset + `THREADS; + parameter ex7_ttype_offset = ex7_pfetch_val_offset + `THREADS; + parameter ex7_ws_offset = ex7_ttype_offset + ttype_width; + parameter ex7_rs_is_offset = ex7_ws_offset + ws_width; + parameter ex7_ra_entry_offset = ex7_rs_is_offset + rs_is_width; + parameter ex7_state_offset = ex7_ra_entry_offset + 5; + parameter ex7_pid_offset = ex7_state_offset + state_width; + parameter ex7_extclass_offset = ex7_pid_offset + pid_width; + parameter ex7_tlbsel_offset = ex7_extclass_offset + extclass_width; + parameter ex8_valid_offset = ex7_tlbsel_offset + tlbsel_width; + parameter ex8_pfetch_val_offset = ex8_valid_offset + `THREADS; + parameter ex8_ttype_offset = ex8_pfetch_val_offset + `THREADS; + parameter ex8_tlbsel_offset = ex8_ttype_offset + ttype_width; + parameter ex5_data_out_offset = ex8_tlbsel_offset + tlbsel_width; + parameter tlb_req_inprogress_offset = ex5_data_out_offset + GPR_WIDTH; + parameter ex3_dsi_offset = tlb_req_inprogress_offset + 1; + parameter ex3_noop_touch_offset = ex3_dsi_offset + 8 + 2 * `THREADS; + parameter ex4_miss_offset = ex3_noop_touch_offset + 8 + 2 * `THREADS; + parameter ex4_dsi_offset = ex4_miss_offset + `THREADS; + parameter ex4_noop_touch_offset = ex4_dsi_offset + 8 + 2 * `THREADS; + parameter ex4_multihit_offset = ex4_noop_touch_offset + 8 + 2 * `THREADS; + parameter ex4_multihit_b_pt_offset = ex4_multihit_offset + `THREADS; + parameter ex4_first_hit_entry_pt_offset = ex4_multihit_b_pt_offset + num_entry; + parameter ex4_parerr_offset = ex4_first_hit_entry_pt_offset + num_entry - 1; + parameter ex4_attr_offset = ex4_parerr_offset + `THREADS + 2; + parameter ex4_hit_offset = ex4_attr_offset + 6; + parameter ex4_cam_hit_offset = ex4_hit_offset + 1; + parameter ex3_debug_offset = ex4_cam_hit_offset + 1; + parameter ex4_debug_offset = ex3_debug_offset + 11; + parameter rw_entry_offset = ex4_debug_offset + 17; + parameter rw_entry_val_offset = rw_entry_offset + 5; + parameter rw_entry_le_offset = rw_entry_val_offset + 1; + parameter cam_entry_le_offset = rw_entry_le_offset + 1; + parameter spare_a_offset = cam_entry_le_offset + 32; + parameter scan_right_0 = spare_a_offset + 16 - 1; + + // parerr macro is commented out below + parameter ex3_comp_addr_offset = 0; + parameter ex4_rpn_offset = ex3_comp_addr_offset + 30; + parameter ex4_wimge_offset = ex4_rpn_offset + 30; + parameter ex4_cam_cmp_data_offset = ex4_wimge_offset + 5; + parameter ex4_array_cmp_data_offset = ex4_cam_cmp_data_offset + cam_data_width; + parameter ex4_rd_cam_data_offset = ex4_array_cmp_data_offset + array_data_width; + parameter ex4_rd_array_data_offset = ex4_rd_cam_data_offset + cam_data_width; + parameter ex5_parerr_offset = ex4_rd_array_data_offset + array_data_width; + parameter ex5_fir_parerr_offset = ex5_parerr_offset + `THREADS + 5; + parameter ex5_fir_multihit_offset = ex5_fir_parerr_offset + `THREADS + 3; + parameter ex5_deen_offset = ex5_fir_multihit_offset + `THREADS; + parameter ex5_hit_offset = ex5_deen_offset + num_entry_log2 + `THREADS; + parameter ex6_deen_offset = ex5_hit_offset + 1; + parameter ex6_hit_offset = ex6_deen_offset + num_entry_log2 + `THREADS; + parameter ex7_deen_offset = ex6_hit_offset + 1; + parameter ex7_hit_offset = ex7_deen_offset + num_entry_log2 + `THREADS; + parameter barrier_done_offset = ex7_hit_offset + 1; + parameter mmucr1_offset = barrier_done_offset + `THREADS; + parameter rpn_holdreg_offset = mmucr1_offset + 10; + parameter entry_valid_offset = rpn_holdreg_offset + 64 * `THREADS; + parameter entry_match_offset = entry_valid_offset + 32; + parameter watermark_offset = entry_match_offset + 32; + parameter mmucr1_b0_cpy_offset = watermark_offset + watermark_width; + parameter lru_rmt_vec_offset = mmucr1_b0_cpy_offset + 1; + parameter eptr_offset = lru_rmt_vec_offset + lru_width + 1; + parameter lru_offset = eptr_offset + eptr_width; + parameter lru_update_event_offset = lru_offset + lru_width; + parameter lru_debug_offset = lru_update_event_offset + 10; + parameter snoop_val_offset = lru_debug_offset + 41; + parameter snoop_attr_offset = snoop_val_offset + 3; + parameter snoop_addr_offset = snoop_attr_offset + 26; + parameter ex3_epn_offset = snoop_addr_offset + epn_width; + parameter ex4_epn_offset = ex3_epn_offset + (2 ** `GPR_WIDTH_ENC) - 12; + parameter ex5_epn_offset = ex4_epn_offset + (2 ** `GPR_WIDTH_ENC) - 12; + parameter por_seq_offset = ex5_epn_offset + (2 ** `GPR_WIDTH_ENC) - 12; + parameter pc_xu_init_reset_offset = por_seq_offset + 3; + parameter tlb_rel_val_offset = pc_xu_init_reset_offset + 1; + parameter tlb_rel_data_offset = tlb_rel_val_offset + 5; + parameter tlb_rel_emq_offset = tlb_rel_data_offset + 132; + parameter eplc_wr_offset = tlb_rel_emq_offset + `EMQ_ENTRIES; + parameter epsc_wr_offset = eplc_wr_offset + 2 * `THREADS + 1; + parameter ccr2_frat_paranoia_offset = epsc_wr_offset + 2 * `THREADS + 1; + parameter clkg_ctl_override_offset = ccr2_frat_paranoia_offset + 12; + parameter ex1_stg_act_offset = clkg_ctl_override_offset + 1; + parameter ex2_stg_act_offset = ex1_stg_act_offset + 1; + parameter ex3_stg_act_offset = ex2_stg_act_offset + 1; + parameter ex4_stg_act_offset = ex3_stg_act_offset + 1; + parameter ex5_stg_act_offset = ex4_stg_act_offset + 1; + parameter ex6_stg_act_offset = ex5_stg_act_offset + 1; + parameter tlb_rel_act_offset = ex6_stg_act_offset + 1; + parameter snoopp_act_offset = tlb_rel_act_offset + 1; + parameter an_ac_grffence_en_dc_offset = snoopp_act_offset + 1; + parameter spare_b_offset = an_ac_grffence_en_dc_offset + 1; + parameter csync_val_offset = spare_b_offset + 16; + parameter isync_val_offset = csync_val_offset + 2; + parameter rel_val_offset = isync_val_offset + 2; + parameter rel_hit_offset = rel_val_offset + 4; + parameter rel_data_offset = rel_hit_offset + 1; + parameter rel_emq_offset = rel_data_offset + 132; + parameter rel_int_upd_val_offset = rel_emq_offset + `EMQ_ENTRIES; + parameter epsc_wr_val_offset = rel_int_upd_val_offset + `EMQ_ENTRIES; + parameter eplc_wr_val_offset = epsc_wr_val_offset + `THREADS; + parameter rv1_binv_val_offset = eplc_wr_val_offset + `THREADS; + parameter snoopp_val_offset = rv1_binv_val_offset + 1; + parameter snoopp_attr_offset = snoopp_val_offset + 1; + parameter snoopp_vpn_offset = snoopp_attr_offset + 26; + parameter ttype_val_offset = snoopp_vpn_offset + epn_width; + parameter ttype_offset = ttype_val_offset + `THREADS; + parameter ws_offset = ttype_offset + 4; + parameter ra_entry_offset = ws_offset + ws_width; + parameter rs_data_offset = ra_entry_offset + 5; + parameter eratre_hole_offset = rs_data_offset + GPR_WIDTH; + parameter eratwe_hole_offset = eratre_hole_offset + 4; + parameter rv1_csync_val_offset = eratwe_hole_offset + 4; + parameter ex0_csync_val_offset = rv1_csync_val_offset + 1; + parameter rv1_isync_val_offset = ex0_csync_val_offset + 1; + parameter ex0_isync_val_offset = rv1_isync_val_offset + 1; + parameter rv1_rel_val_offset = ex0_isync_val_offset + 1; + parameter ex0_rel_val_offset = rv1_rel_val_offset + 4; + parameter ex1_rel_val_offset = ex0_rel_val_offset + 4; + parameter rv1_epsc_wr_val_offset = ex1_rel_val_offset + 4; + parameter ex0_epsc_wr_val_offset = rv1_epsc_wr_val_offset + `THREADS; + parameter rv1_eplc_wr_val_offset = ex0_epsc_wr_val_offset + `THREADS; + parameter ex0_eplc_wr_val_offset = rv1_eplc_wr_val_offset + `THREADS; + parameter ex0_binv_val_offset = ex0_eplc_wr_val_offset + `THREADS; + parameter ex1_binv_val_offset = ex0_binv_val_offset + 1; + parameter rv1_snoop_val_offset = ex1_binv_val_offset + 1; + parameter ex0_snoop_val_offset = rv1_snoop_val_offset + 1; + parameter ex1_snoop_val_offset = ex0_snoop_val_offset + 1; + parameter rv1_ttype_val_offset = ex1_snoop_val_offset + 1; + parameter ex0_ttype_val_offset = rv1_ttype_val_offset + `THREADS; + parameter rv1_ttype_offset = ex0_ttype_val_offset + `THREADS; + parameter ex0_ttype_offset = rv1_ttype_offset + 4; + parameter ex1_ttype03_offset = ex0_ttype_offset + 4; + parameter ex1_ttype67_offset = ex1_ttype03_offset + 4; + parameter ex1_valid_op_offset = ex1_ttype67_offset + 2; + parameter ex2_valid_op_offset = ex1_valid_op_offset + `THREADS; + parameter ex3_valid_op_offset = ex2_valid_op_offset + `THREADS; + parameter ex4_valid_op_offset = ex3_valid_op_offset + `THREADS; + parameter ex5_valid_op_offset = ex4_valid_op_offset + `THREADS; + parameter ex6_valid_op_offset = ex5_valid_op_offset + `THREADS; + parameter ex7_valid_op_offset = ex6_valid_op_offset + `THREADS; + parameter ex8_valid_op_offset = ex7_valid_op_offset + `THREADS; + parameter lq_xu_ord_write_done_offset = ex8_valid_op_offset + `THREADS; + parameter lq_xu_ord_read_done_offset = lq_xu_ord_write_done_offset + 1; + parameter xu_lq_act_offset = lq_xu_ord_read_done_offset + 1; + parameter xu_lq_val_offset = xu_lq_act_offset + 1; + parameter xu_lq_is_eratre_offset = xu_lq_val_offset + `THREADS; + parameter xu_lq_is_eratwe_offset = xu_lq_is_eratre_offset + 1; + parameter xu_lq_is_eratsx_offset = xu_lq_is_eratwe_offset + 1; + parameter xu_lq_is_eratilx_offset = xu_lq_is_eratsx_offset + 1; + parameter xu_lq_ws_offset = xu_lq_is_eratilx_offset + 1; + parameter xu_lq_ra_entry_offset = xu_lq_ws_offset + 2; + parameter xu_lq_rs_data_offset = xu_lq_ra_entry_offset + 5; + parameter cp_flush_offset = xu_lq_rs_data_offset + GPR_WIDTH; + parameter ex4_oldest_itag_offset = cp_flush_offset + `THREADS; + parameter ex4_nonspec_val_offset = ex4_oldest_itag_offset + 1; + parameter ex4_tlbmiss_offset = ex4_nonspec_val_offset + 1; + parameter ex4_tlbinelig_offset = ex4_tlbmiss_offset + 1; + parameter ex4_ptfault_offset = ex4_tlbinelig_offset + 1; + parameter ex4_lratmiss_offset = ex4_ptfault_offset + 1; + parameter ex4_tlb_multihit_offset = ex4_lratmiss_offset + 1; + parameter ex4_tlb_par_err_offset = ex4_tlb_multihit_offset + 1; + parameter ex4_lru_par_err_offset = ex4_tlb_par_err_offset + 1; + parameter ex4_tlb_excp_det_offset = ex4_lru_par_err_offset + 1; + parameter ex3_eratm_itag_hit_offset = ex4_tlb_excp_det_offset + 1; + parameter ex4_emq_excp_rpt_offset = ex3_eratm_itag_hit_offset + `EMQ_ENTRIES; + parameter ex5_emq_excp_rpt_offset = ex4_emq_excp_rpt_offset + `EMQ_ENTRIES; + parameter ex6_emq_excp_rpt_offset = ex5_emq_excp_rpt_offset + `EMQ_ENTRIES; + parameter ex5_tlb_excp_val_offset = ex6_emq_excp_rpt_offset + `EMQ_ENTRIES; + parameter ex6_tlb_excp_val_offset = ex5_tlb_excp_val_offset + `THREADS; + parameter ex4_gate_miss_offset = ex6_tlb_excp_val_offset + `THREADS; + parameter ex4_full_restart_offset = ex4_gate_miss_offset + 1; + parameter ex4_itag_hit_restart_offset = ex4_full_restart_offset + 1; + parameter ex4_epn_hit_restart_offset = ex4_itag_hit_restart_offset + 1; + parameter ex4_setHold_offset = ex4_epn_hit_restart_offset + 1; + parameter ex5_tlbreq_val_offset = ex4_setHold_offset + 1; + parameter ex5_tlbreq_nonspec_offset = ex5_tlbreq_val_offset + 1; + parameter ex5_thdid_offset = ex5_tlbreq_nonspec_offset + 1; + parameter ex5_emq_offset = ex5_thdid_offset + `THREADS; + parameter ex5_tlbreq_ttype_offset = ex5_emq_offset + `EMQ_ENTRIES; + parameter ex5_perf_dtlb_offset = ex5_tlbreq_ttype_offset + 2; + parameter derat_dcc_clr_hold_offset = ex5_perf_dtlb_offset + `THREADS; + parameter eratm_entry_state_offset = derat_dcc_clr_hold_offset + `THREADS; + parameter eratm_entry_itag_offset = eratm_entry_state_offset + 3 * `EMQ_ENTRIES; + parameter eratm_entry_tid_offset = eratm_entry_itag_offset + `ITAG_SIZE_ENC * `EMQ_ENTRIES; + parameter eratm_entry_epn_offset = eratm_entry_tid_offset + `THREADS * `EMQ_ENTRIES; + parameter eratm_entry_nonspec_val_offset = eratm_entry_epn_offset + ((2 ** `GPR_WIDTH_ENC) - 12) * `EMQ_ENTRIES; + parameter eratm_entry_mkill_offset = eratm_entry_nonspec_val_offset + `EMQ_ENTRIES; + parameter eratm_hold_tid_offset = eratm_entry_mkill_offset + `EMQ_ENTRIES; + parameter mm_int_rpt_itag_offset = eratm_hold_tid_offset + `THREADS; + parameter mm_int_rpt_tlbmiss_offset = mm_int_rpt_itag_offset + `ITAG_SIZE_ENC; + parameter mm_int_rpt_tlbinelig_offset = mm_int_rpt_tlbmiss_offset + 1; + parameter mm_int_rpt_ptfault_offset = mm_int_rpt_tlbinelig_offset + 1; + parameter mm_int_rpt_lratmiss_offset = mm_int_rpt_ptfault_offset + 1; + parameter mm_int_rpt_tlb_multihit_offset = mm_int_rpt_lratmiss_offset + 1; + parameter mm_int_rpt_tlb_par_err_offset = mm_int_rpt_tlb_multihit_offset + 1; + parameter mm_int_rpt_lru_par_err_offset = mm_int_rpt_tlb_par_err_offset + 1; + parameter eratm_entry_tlbmiss_offset = mm_int_rpt_lru_par_err_offset + 1; + parameter eratm_entry_tlbinelig_offset = eratm_entry_tlbmiss_offset + `EMQ_ENTRIES; + parameter eratm_entry_ptfault_offset = eratm_entry_tlbinelig_offset + `EMQ_ENTRIES; + parameter eratm_entry_lratmiss_offset = eratm_entry_ptfault_offset + `EMQ_ENTRIES; + parameter eratm_entry_tlb_multihit_offset = eratm_entry_lratmiss_offset + `EMQ_ENTRIES; + parameter eratm_entry_tlb_par_err_offset = eratm_entry_tlb_multihit_offset + `EMQ_ENTRIES; + parameter eratm_entry_lru_par_err_offset = eratm_entry_tlb_par_err_offset + `EMQ_ENTRIES; + parameter scan_right_1 = eratm_entry_lru_par_err_offset + `EMQ_ENTRIES - 1; + + parameter bcfg_offset = 0; + parameter boot_scan_right = bcfg_offset + bcfg_width - 1; + + //-------------------------- + // signals + //-------------------------- + // Latch signals + wire [0:`THREADS-1] ex1_valid_d; + wire [0:`THREADS-1] ex1_valid_q; + wire [10:11] ex1_ttype_d; + wire [10:11] ex1_ttype_q; + wire [0:`THREADS-1] ex2_valid_d; + wire [0:`THREADS-1] ex2_valid_q; + wire [0:`THREADS-1] ex2_pfetch_val_d; + wire [0:`THREADS-1] ex2_pfetch_val_q; + wire [0:`ITAG_SIZE_ENC-1] ex2_itag_d; + wire [0:`ITAG_SIZE_ENC-1] ex2_itag_q; + wire [0:ttype_width-1] ex2_ttype_d; + wire [0:ttype_width-1] ex2_ttype_q; + wire [0:ws_width-1] ex2_ws_d; + wire [0:ws_width-1] ex2_ws_q; + wire [0:rs_is_width-1] ex2_rs_is_d; + wire [0:rs_is_width-1] ex2_rs_is_q; + wire [0:4] ex2_ra_entry_d; + wire [0:4] ex2_ra_entry_q; + wire [0:state_width-1] ex2_state_d; + wire [0:state_width-1] ex2_state_q; + wire [0:pid_width-1] ex2_pid_d; + wire [0:pid_width-1] ex2_pid_q; + reg [0:extclass_width-1] ex2_extclass_d; + wire [0:extclass_width-1] ex2_extclass_q; + reg [0:tlbsel_width-1] ex2_tlbsel_d; + wire [0:tlbsel_width-1] ex2_tlbsel_q; + wire [0:`THREADS-1] ex3_valid_d; + wire [0:`THREADS-1] ex3_valid_q; + wire [0:`ITAG_SIZE_ENC-1] ex3_itag_d; + wire [0:`ITAG_SIZE_ENC-1] ex3_itag_q; + wire [0:`THREADS-1] ex3_pfetch_val_d; + wire [0:`THREADS-1] ex3_pfetch_val_q; + wire [0:ttype_width-1] ex3_ttype_d; + wire [0:ttype_width-1] ex3_ttype_q; + wire [0:ws_width-1] ex3_ws_d; + wire [0:ws_width-1] ex3_ws_q; + wire [0:rs_is_width-1] ex3_rs_is_d; + wire [0:rs_is_width-1] ex3_rs_is_q; + wire [0:4] ex3_ra_entry_d; + wire [0:4] ex3_ra_entry_q; + wire [0:state_width-1] ex3_state_d; + wire [0:state_width-1] ex3_state_q; + wire [0:pid_width-1] ex3_pid_d; + wire [0:pid_width-1] ex3_pid_q; + wire [0:extclass_width-1] ex3_extclass_d; + wire [0:extclass_width-1] ex3_extclass_q; + wire [0:tlbsel_width-1] ex3_tlbsel_d; + wire [0:tlbsel_width-1] ex3_tlbsel_q; + wire [0:`THREADS-1] ex4_valid_d; + wire [0:`THREADS-1] ex4_valid_q; + wire [0:`THREADS-1] ex4_pfetch_val_d; + wire [0:`THREADS-1] ex4_pfetch_val_q; + wire [0:`ITAG_SIZE_ENC-1] ex4_itag_d; + wire [0:`ITAG_SIZE_ENC-1] ex4_itag_q; + wire [0:ttype_width-1] ex4_ttype_d; + wire [0:ttype_width-1] ex4_ttype_q; + wire [0:ws_width-1] ex4_ws_d; + wire [0:ws_width-1] ex4_ws_q; + wire [0:rs_is_width-1] ex4_rs_is_d; + wire [0:rs_is_width-1] ex4_rs_is_q; + wire [0:4] ex4_ra_entry_d; + wire [0:4] ex4_ra_entry_q; + wire [0:state_width-1] ex4_state_d; + wire [0:state_width-1] ex4_state_q; + wire [0:pid_width-1] ex4_pid_d; + wire [0:pid_width-1] ex4_pid_q; + wire [0:lpid_width-1] ex4_lpid_d; + wire [0:lpid_width-1] ex4_lpid_q; + wire [0:extclass_width-1] ex4_extclass_d; + wire [0:extclass_width-1] ex4_extclass_q; + wire [0:tlbsel_width-1] ex4_tlbsel_d; + wire [0:tlbsel_width-1] ex4_tlbsel_q; + wire [0:`THREADS-1] ex5_valid_d; + wire [0:`THREADS-1] ex5_valid_q; + wire [0:`THREADS-1] ex5_pfetch_val_d; + wire [0:`THREADS-1] ex5_pfetch_val_q; + wire [0:`ITAG_SIZE_ENC-1] ex5_itag_d; + wire [0:`ITAG_SIZE_ENC-1] ex5_itag_q; + wire [0:ttype_width-1] ex5_ttype_d; + wire [0:ttype_width-1] ex5_ttype_q; + wire [0:ws_width-1] ex5_ws_d; + wire [0:ws_width-1] ex5_ws_q; + wire [0:rs_is_width-1] ex5_rs_is_d; + wire [0:rs_is_width-1] ex5_rs_is_q; + wire [0:4] ex5_ra_entry_d; + wire [0:4] ex5_ra_entry_q; + wire [0:state_width-1] ex5_state_d; + wire [0:state_width-1] ex5_state_q; + wire [0:pid_width-1] ex5_pid_d; + wire [0:pid_width-1] ex5_pid_q; + wire [0:lpid_width-1] ex5_lpid_d; + wire [0:lpid_width-1] ex5_lpid_q; + wire [0:extclass_width-1] ex5_extclass_d; + wire [0:extclass_width-1] ex5_extclass_q; + wire [0:tlbsel_width-1] ex5_tlbsel_d; + wire [0:tlbsel_width-1] ex5_tlbsel_q; + wire [0:`THREADS-1] ex6_valid_d; + wire [0:`THREADS-1] ex6_valid_q; + wire [0:`THREADS-1] ex6_pfetch_val_d; + wire [0:`THREADS-1] ex6_pfetch_val_q; + wire [0:`ITAG_SIZE_ENC-1] ex6_itag_d; + wire [0:`ITAG_SIZE_ENC-1] ex6_itag_q; + wire [0:ttype_width-1] ex6_ttype_d; + wire [0:ttype_width-1] ex6_ttype_q; + wire [0:ws_width-1] ex6_ws_d; + wire [0:ws_width-1] ex6_ws_q; + wire [0:rs_is_width-1] ex6_rs_is_d; + wire [0:rs_is_width-1] ex6_rs_is_q; + wire [0:4] ex6_ra_entry_d; + wire [0:4] ex6_ra_entry_q; + wire [0:state_width-1] ex6_state_d; + wire [0:state_width-1] ex6_state_q; + wire [0:pid_width-1] ex6_pid_d; + wire [0:pid_width-1] ex6_pid_q; + wire [0:extclass_width-1] ex6_extclass_d; + wire [0:extclass_width-1] ex6_extclass_q; + wire [0:tlbsel_width-1] ex6_tlbsel_d; + wire [0:tlbsel_width-1] ex6_tlbsel_q; + wire [0:`THREADS-1] ex7_valid_d; + wire [0:`THREADS-1] ex7_valid_q; + wire [0:`THREADS-1] ex7_pfetch_val_d; + wire [0:`THREADS-1] ex7_pfetch_val_q; + wire [0:ttype_width-1] ex7_ttype_d; + wire [0:ttype_width-1] ex7_ttype_q; + wire [0:ws_width-1] ex7_ws_d; + wire [0:ws_width-1] ex7_ws_q; + wire [0:rs_is_width-1] ex7_rs_is_d; + wire [0:rs_is_width-1] ex7_rs_is_q; + wire [0:4] ex7_ra_entry_d; + wire [0:4] ex7_ra_entry_q; + wire [0:state_width-1] ex7_state_d; + wire [0:state_width-1] ex7_state_q; + wire [0:pid_width-1] ex7_pid_d; + wire [0:pid_width-1] ex7_pid_q; + wire [0:extclass_width-1] ex7_extclass_d; + wire [0:extclass_width-1] ex7_extclass_q; + wire [0:tlbsel_width-1] ex7_tlbsel_d; + wire [0:tlbsel_width-1] ex7_tlbsel_q; + wire [0:`THREADS-1] ex8_valid_d; + wire [0:`THREADS-1] ex8_valid_q; + wire [0:`THREADS-1] ex8_pfetch_val_d; + wire [0:`THREADS-1] ex8_pfetch_val_q; + wire [0:ttype_width-1] ex8_ttype_d; + wire [0:ttype_width-1] ex8_ttype_q; + wire [0:tlbsel_width-1] ex8_tlbsel_d; + wire [0:tlbsel_width-1] ex8_tlbsel_q; + wire [64-GPR_WIDTH:63] ex2_data_in_d; + wire [64-GPR_WIDTH:63] ex2_data_in_q; + wire [64-GPR_WIDTH:63] ex5_data_out_d; + wire [64-GPR_WIDTH:63] ex5_data_out_q; + wire tlb_req_inprogress_d; + wire tlb_req_inprogress_q; + wire ex2_deratre; + wire ex2_deratwe; + wire ex2_deratsx; + wire ex2_deratwe_ws3; + wire [0:7+2*`THREADS] ex3_dsi_d; + wire [0:7+2*`THREADS] ex3_dsi_q; + wire [0:7+2*`THREADS] ex3_noop_touch_d; + wire [0:7+2*`THREADS] ex3_noop_touch_q; + wire [0:`THREADS-1] ex4_miss_d; + wire [0:`THREADS-1] ex4_miss_q; + wire [0:7+2*`THREADS] ex4_dsi_d; + wire [0:7+2*`THREADS] ex4_dsi_q; + wire [0:7+2*`THREADS] ex4_noop_touch_d; + wire [0:7+2*`THREADS] ex4_noop_touch_q; + wire [0:`THREADS-1] ex4_multihit_d; + wire [0:`THREADS-1] ex4_multihit_q; + wire [1:num_entry] ex4_multihit_b_pt_d; + wire [1:num_entry] ex4_multihit_b_pt_q; + wire [1:num_entry-1] ex4_first_hit_entry_pt_d; + wire [1:num_entry-1] ex4_first_hit_entry_pt_q; + wire [0:`THREADS+1] ex4_parerr_d; + wire [0:`THREADS+1] ex4_parerr_q; + wire [0:5] ex4_attr_d; + wire [0:5] ex4_attr_q; + wire ex4_hit_d; + wire ex4_hit_q; + wire ex4_cam_hit_q; + wire [0:10] ex3_debug_d; + wire [0:10] ex3_debug_q; + wire [0:16] ex4_debug_d; + wire [0:16] ex4_debug_q; + wire [0:cam_data_width-1] ex4_cam_cmp_data_d; + wire [0:cam_data_width-1] ex4_cam_cmp_data_q; + wire [0:array_data_width-1] ex4_array_cmp_data_d; + wire [0:array_data_width-1] ex4_array_cmp_data_q; + wire [0:array_data_width-1] ex4_rd_array_data_d; + wire [0:array_data_width-1] ex4_rd_array_data_q; + wire [0:cam_data_width-1] ex4_rd_cam_data_d; + wire [0:cam_data_width-1] ex4_rd_cam_data_q; + wire [0:`THREADS+4] ex5_parerr_d; + wire [0:`THREADS+4] ex5_parerr_q; + wire [0:`THREADS+2] ex5_fir_parerr_d; + wire [0:`THREADS+2] ex5_fir_parerr_q; + wire [0:`THREADS-1] ex5_fir_multihit_d; + wire [0:`THREADS-1] ex5_fir_multihit_q; + wire [0:`THREADS+num_entry_log2-1] ex5_deen_d; + wire [0:`THREADS+num_entry_log2-1] ex5_deen_q; + wire ex5_hit_d; + wire ex5_hit_q; + wire [0:`THREADS+num_entry_log2-1] ex6_deen_d; + wire [0:`THREADS+num_entry_log2-1] ex6_deen_q; + wire ex6_hit_d; + wire ex6_hit_q; + wire [0:`THREADS+num_entry_log2-1] ex7_deen_d; + wire [0:`THREADS+num_entry_log2-1] ex7_deen_q; + wire ex7_hit_d; + wire ex7_hit_q; + wire ex4_deratwe; + wire ex5_deratwe; + wire ex6_deratwe; + wire ex7_deratwe; + wire ex8_deratwe; + wire [0:`THREADS-1] barrier_done_d; + wire [0:`THREADS-1] barrier_done_q; + wire [0:9] mmucr1_d; + wire [0:9] mmucr1_q; + wire [22:51] ex3_comp_addr_d; + wire [22:51] ex3_comp_addr_q; + wire [22:51] ex4_rpn_d; + wire [22:51] ex4_rpn_q; + wire [0:4] ex4_wimge_d; + wire [0:4] ex4_wimge_q; + wire mmucr1_b0_cpy_d; + wire mmucr1_b0_cpy_q; + wire [0:lru_width] lru_rmt_vec_d; + wire [0:lru_width] lru_rmt_vec_q; + wire [0:7] ex4_dsi; + wire [3:7] ex4_noop_touch; + reg [0:2] por_seq_d; + wire [0:2] por_seq_q; + wire [0:63] rpn_holdreg_d[0:`THREADS-1]; + wire [0:63] rpn_holdreg_q[0:`THREADS-1]; + reg [0:63] ex2_rpn_holdreg; + wire [0:watermark_width-1] watermark_d; + wire [0:watermark_width-1] watermark_q; + wire [0:eptr_width-1] eptr_d; + wire [0:eptr_width-1] eptr_q; + wire [1:lru_width] lru_d; + wire [1:lru_width] lru_q; + wire [0:9] lru_update_event_d; + wire [0:9] lru_update_event_q; + wire [0:40] lru_debug_d; + wire [0:40] lru_debug_q; + wire [0:2] snoop_val_d; + wire [0:2] snoop_val_q; + wire [0:25] snoop_attr_d; + wire [0:25] snoop_attr_q; + wire [52-epn_width:51] snoop_addr_d; + wire [52-epn_width:51] snoop_addr_q; + wire [64-(2**`GPR_WIDTH_ENC):51] ex3_epn_d; + wire [64-(2**`GPR_WIDTH_ENC):51] ex3_epn_q; + wire [64-(2**`GPR_WIDTH_ENC):51] ex4_epn_q; + wire [64-(2**`GPR_WIDTH_ENC):51] ex5_epn_q; + wire pc_xu_init_reset_q; + wire [0:4] tlb_rel_val_d; + wire [0:4] tlb_rel_val_q; + wire [0:131] tlb_rel_data_d; + wire [0:131] tlb_rel_data_q; + wire [0:`EMQ_ENTRIES-1] tlb_rel_emq_d; + wire [0:`EMQ_ENTRIES-1] tlb_rel_emq_q; + wire [0:2*`THREADS] eplc_wr_d; + wire [0:2*`THREADS] eplc_wr_q; + wire [0:2*`THREADS] epsc_wr_d; + wire [0:2*`THREADS] epsc_wr_q; + wire [0:11] ccr2_frat_paranoia_d; + wire [0:11] ccr2_frat_paranoia_q; + wire ex2_byte_rev_d; + wire ex2_byte_rev_q; + wire ex3_byte_rev_d; + wire ex3_byte_rev_q; + wire [0:bcfg_width-1] bcfg_q; + wire [0:bcfg_width-1] bcfg_q_b; + // logic signals + reg [0:1] por_wr_cam_val; + reg [0:1] por_wr_array_val; + reg [0:cam_data_width-1] por_wr_cam_data; + reg [0:array_data_width-1] por_wr_array_data; + reg [0:num_entry_log2-1] por_wr_entry; + reg [0:`THREADS-1] por_hold_req; + wire ex3_multihit; + wire ex3_multihit_b; + wire [0:num_entry_log2-1] ex3_first_hit_entry; + wire [0:num_entry_log2-1] ex4_first_hit_entry; + wire ex4_dsi_enab; + wire ex4_noop_touch_enab; + wire ex4_multihit_enab; + wire [0:1] ex4_parerr_enab; + + + wire [0:2+num_entry_log2-1] ex4_eratsx_data; + wire [0:num_entry_log2-1] lru_way_encode; + wire [0:lru_width] lru_rmt_vec; + wire [1:lru_width] lru_reset_vec; + wire [1:lru_width] lru_set_vec; + wire [1:lru_width] lru_op_vec; + wire [1:lru_width] lru_vp_vec; + wire [1:lru_width] lru_eff; + wire [0:lru_width] lru_watermark_mask; + wire [0:lru_width] entry_valid_watermarked; + //signal lru_update_event : std_ulogic; + wire [0:eptr_width-1] eptr_p1; + //signal ex4_valid_32b : std_ulogic; + wire ex1_is_icbtlslc; + wire [50:67] ex4_cmp_data_calc_par; + wire ex4_cmp_data_parerr_epn_mac; + wire ex4_cmp_data_parerr_rpn_mac; + wire ex4_cmp_data_parerr_epn; + wire ex4_cmp_data_parerr_rpn; + wire [50:67] ex4_rd_data_calc_par; + wire ex4_rd_data_parerr_epn; + wire ex4_rd_data_parerr_rpn; + + + wire ex5_parerr_enab; + wire ex5_fir_parerr_enab; + wire ex1_mmucr0_gs; + wire ex1_mmucr0_ts; + wire ex1_eplc_epr; + wire ex1_epsc_epr; + wire ex1_eplc_egs; + wire ex1_epsc_egs; + wire ex1_eplc_eas; + wire ex1_epsc_eas; + reg [0:pid_width-1] ex1_pid; + reg [0:pid_width-1] ex1_mmucr0_pid; + reg [0:pid_width-1] ex1_eplc_epid; + reg [0:pid_width-1] ex1_epsc_epid; + wire [0:3] tlb_rel_cmpmask; + wire [0:3] tlb_rel_xbitmask; + wire tlb_rel_maskpar; + wire [0:3] ex2_data_cmpmask; + wire [0:3] ex2_data_xbitmask; + wire ex2_data_maskpar; + wire [0:`THREADS-1] cp_flush_d; + wire [0:`THREADS-1] cp_flush_q; + // CAM/Array signals + // Read Port + wire rd_val; + wire [0:4] rw_entry; + // Write Port + wire [51:67] wr_array_par; + wire [0:array_data_width-1-10-7] wr_array_data_nopar; + wire [0:array_data_width-1] wr_array_data; + wire [0:cam_data_width-1] wr_cam_data; + wire [0:1] wr_array_val; + wire [0:1] wr_cam_val; + wire wr_val_early; + // CAM Port + wire comp_request; + wire [0:51] comp_addr; + wire [0:1] addr_enable; + wire [0:2] comp_pgsize; + wire pgsize_enable; + wire [0:1] comp_class; + wire [0:2] class_enable; + wire [0:1] comp_extclass; + wire [0:1] extclass_enable; + wire [0:1] comp_state; + wire [0:1] state_enable; + wire [0:3] comp_thdid; + wire [0:1] thdid_enable; + wire [0:7] comp_pid; + wire pid_enable; + wire comp_invalidate; + wire flash_invalidate; + // Array Outputs + wire [0:array_data_width-1] array_cmp_data; + wire [0:array_data_width-1] rd_array_data; + // CAM Outputs + wire [0:cam_data_width-1] cam_cmp_data; + wire cam_hit; + wire [0:4] cam_hit_entry; + wire [0:31] entry_match; + wire [0:31] entry_match_q; + wire [0:31] entry_valid; + wire [0:31] entry_valid_q; + wire [0:cam_data_width-1] rd_cam_data; + + + wire [0:2] cam_pgsize; + wire [0:3] ws0_pgsize; + // new cam _np2 signals + wire bypass_mux_enab_np1; + wire [0:20] bypass_attr_np1; + wire [0:20] attr_np2; + wire [22:51] rpn_np2; + // Pervasive + wire pc_sg_1; + wire pc_sg_0; + wire pc_func_sl_thold_1; + wire pc_func_sl_thold_0; + wire pc_func_sl_thold_0_b; + wire pc_func_slp_sl_thold_1; + wire pc_func_slp_sl_thold_0; + wire pc_func_slp_sl_thold_0_b; + wire pc_func_sl_force; + wire pc_func_slp_sl_force; + wire pc_cfg_slp_sl_thold_1; + wire pc_cfg_slp_sl_thold_0; + wire pc_cfg_slp_sl_thold_0_b; + wire pc_cfg_slp_sl_force; + wire lcb_dclk; + wire [0:`NCLK_WIDTH-1] lcb_lclk; + wire init_alias; + // Clock Gating + wire clkg_ctl_override_d; + wire clkg_ctl_override_q; + wire ex1_stg_act_d; + wire ex1_stg_act_q; + wire ex2_stg_act_d; + wire ex2_stg_act_q; + wire ex3_stg_act_d; + wire ex3_stg_act_q; + wire ex4_stg_act_d; + wire ex4_stg_act_q; + wire ex5_stg_act_d; + wire ex5_stg_act_q; + wire ex6_stg_act_d; + wire ex6_stg_act_q; + wire an_ac_grffence_en_dc_q; + wire ex3_cmp_data_act; + wire ex3_rd_data_act; + wire entry_valid_act; + wire entry_match_act; + wire snoopp_act_q; + wire snoopp_act; + wire snoop_act; + wire tlb_rel_act_d; + wire tlb_rel_act_q; + wire tlb_rel_act; + wire mchk_flash_inv_act; + wire [0:15] spare_a_q; + wire [0:15] spare_b_q; + wire [0:39] unused_dc; + + + //- new latches and signals for A20 -------------------------------------------- + wire [0:1] csync_val_d; + wire [0:1] csync_val_q; + wire [0:1] isync_val_d; + wire [0:1] isync_val_q; + wire [0:3] rel_val_d; + wire [0:3] rel_val_q; + wire rel_hit_d; + wire rel_hit_q; + wire [0:131] rel_data_d; + wire [0:131] rel_data_q; + wire [0:`EMQ_ENTRIES-1] rel_emq_d; + wire [0:`EMQ_ENTRIES-1] rel_emq_q; + wire [0:`EMQ_ENTRIES-1] rel_int_upd_val_d; + wire [0:`EMQ_ENTRIES-1] rel_int_upd_val_q; + wire [0:`THREADS-1] epsc_wr_val_d; + wire [0:`THREADS-1] epsc_wr_val_q; + wire [0:`THREADS-1] eplc_wr_val_d; + wire [0:`THREADS-1] eplc_wr_val_q; + wire snoopp_val_d; + wire snoopp_val_q; + wire [0:25] snoopp_attr_d; + wire [0:25] snoopp_attr_q; + wire [52-epn_width:51] snoopp_vpn_d; + wire [52-epn_width:51] snoopp_vpn_q; + wire [0:`THREADS-1] ttype_val_d; + wire [0:`THREADS-1] ttype_val_q; + wire [0:3] ttype_d; + wire [0:3] ttype_q; + wire [0:ws_width-1] ws_d; + wire [0:ws_width-1] ws_q; + wire [0:4] ra_entry_d; + wire [0:4] ra_entry_q; + wire [64-GPR_WIDTH:63] rs_data_d; + wire [64-GPR_WIDTH:63] rs_data_q; + wire [0:3] eratre_hole_d; + wire [0:3] eratre_hole_q; + wire [0:3] eratwe_hole_d; + wire [0:3] eratwe_hole_q; + wire rv1_csync_val_d; + wire rv1_csync_val_q; + wire ex0_csync_val_d; + wire ex0_csync_val_q; + wire rv1_isync_val_d; + wire rv1_isync_val_q; + wire ex0_isync_val_d; + wire ex0_isync_val_q; + wire [0:3] rv1_rel_val_d; + wire [0:3] rv1_rel_val_q; + wire [0:3] ex0_rel_val_d; + wire [0:3] ex0_rel_val_q; + wire [0:3] ex1_rel_val_d; + wire [0:3] ex1_rel_val_q; + wire [0:`THREADS-1] rv1_epsc_wr_val_d; + wire [0:`THREADS-1] rv1_epsc_wr_val_q; + wire [0:`THREADS-1] ex0_epsc_wr_val_d; + wire [0:`THREADS-1] ex0_epsc_wr_val_q; + wire [0:`THREADS-1] rv1_eplc_wr_val_d; + wire [0:`THREADS-1] rv1_eplc_wr_val_q; + wire [0:`THREADS-1] ex0_eplc_wr_val_d; + wire [0:`THREADS-1] ex0_eplc_wr_val_q; + wire rv1_binv_val_d; + wire rv1_binv_val_q; + wire ex0_binv_val_d; + wire ex0_binv_val_q; + wire ex1_binv_val_d; + wire ex1_binv_val_q; + wire rv1_snoop_val_d; + wire rv1_snoop_val_q; + wire ex0_snoop_val_d; + wire ex0_snoop_val_q; + wire ex1_snoop_val_d; + wire ex1_snoop_val_q; + wire [0:`THREADS-1] rv1_ttype_val_d; + wire [0:`THREADS-1] rv1_ttype_val_q; + wire [0:`THREADS-1] ex0_ttype_val_d; + wire [0:`THREADS-1] ex0_ttype_val_q; + wire [0:3] rv1_ttype_d; + wire [0:3] rv1_ttype_q; + wire [0:3] ex0_ttype_d; + wire [0:3] ex0_ttype_q; + wire [0:3] ex1_ttype03_d; + wire [0:3] ex1_ttype03_q; + wire [0:1] ex1_ttype67_d; + wire [0:1] ex1_ttype67_q; + wire [0:`THREADS-1] ex1_valid_op_d; + wire [0:`THREADS-1] ex1_valid_op_q; + wire [0:`THREADS-1] ex2_valid_op_d; + wire [0:`THREADS-1] ex2_valid_op_q; + wire [0:`THREADS-1] ex3_valid_op_d; + wire [0:`THREADS-1] ex3_valid_op_q; + wire [0:`THREADS-1] ex4_valid_op_d; + wire [0:`THREADS-1] ex4_valid_op_q; + wire [0:`THREADS-1] ex5_valid_op_d; + wire [0:`THREADS-1] ex5_valid_op_q; + wire [0:`THREADS-1] ex6_valid_op_d; + wire [0:`THREADS-1] ex6_valid_op_q; + wire [0:`THREADS-1] ex7_valid_op_d; + wire [0:`THREADS-1] ex7_valid_op_q; + wire [0:`THREADS-1] ex8_valid_op_d; + wire [0:`THREADS-1] ex8_valid_op_q; + wire [0:`THREADS-1] ex1_valid; + wire [0:`THREADS-1] ex2_valid; + wire [0:`THREADS-1] ex3_valid; + wire [0:`THREADS-1] ex3_valid_req; + wire [0:`THREADS-1] ex4_valid; + wire [0:`THREADS-1] ex5_valid; + wire [0:`THREADS-1] ex6_valid; + wire [0:`THREADS-1] ex7_valid; + wire [0:`THREADS-1] ex8_valid; + + wire [0:4] arb_pri; + wire eratrw_hole; + wire rel_hole; + wire csync_next; + wire rel_next; + wire epsc_next; + wire eplc_next; + wire snoop_next; + wire eratre_next; + wire eratwe_next; + wire eratsx_next; + wire [0:19] derat_mmucr0[0:`THREADS-1]; + wire [0:`THREADS-1] derat_mmucr0_gs; + wire [0:`THREADS-1] derat_mmucr0_ts; + wire [0:7] derat_eplc_elpid[0:`THREADS-1]; + wire [0:13] derat_eplc_epid[0:`THREADS-1]; + wire [0:7] derat_epsc_elpid[0:`THREADS-1]; + wire [0:13] derat_epsc_epid[0:`THREADS-1]; + wire [0:13] derat_pid[0:`THREADS-1]; + reg [0:7] ex3_eplc_elpid; + reg [0:7] ex3_epsc_elpid; + wire [0:`THREADS-1] spr_msr_hv_d; + wire [0:`THREADS-1] spr_msr_hv_q; + wire [0:`THREADS-1] spr_msr_pr_d; + wire [0:`THREADS-1] spr_msr_pr_q; + wire [0:`THREADS-1] spr_msr_ds_d; + wire [0:`THREADS-1] spr_msr_ds_q; + wire [0:`THREADS-1] spr_msr_cm_d; + wire [0:`THREADS-1] spr_msr_cm_q; + wire spr_ccr2_notlb_d; + wire spr_ccr2_notlb_q; + wire xucr4_mmu_mchk_q; + wire [0:3] mchk_flash_inv_d; + wire [0:3] mchk_flash_inv_q; + wire mchk_flash_inv_enab; + wire [0:`THREADS-1] cp_next_val_d; + wire [0:`THREADS-1] cp_next_val_q; + wire [0:`ITAG_SIZE_ENC-1] cp_next_itag_q[0:`THREADS-1]; + wire ex4_eratm_val; + wire [0:`EMQ_ENTRIES-1] ex4_entry_wrt_val; + wire eratm_por_reset; + wire ex3_oldest_itag; + wire ex4_oldest_itag_d; + wire ex4_oldest_itag_q; + wire ex3_eratm_chk_val; + wire ex3_eratm_epn_m; + wire [0:`EMQ_ENTRIES-1] ex3_eratm_epn_hit; + wire [0:`EMQ_ENTRIES-1] ex3_eratm_epn_hit_restart; + wire [0:`EMQ_ENTRIES-1] ex2_eratm_itag_hit; + wire [0:`EMQ_ENTRIES-1] ex3_eratm_itag_hit; + wire [0:`EMQ_ENTRIES-1] ex3_eratm_itag_hit_d; + wire [0:`EMQ_ENTRIES-1] ex3_eratm_itag_hit_q; + wire [0:`EMQ_ENTRIES-1] ex3_eratm_itag_hit_restart; + wire [0:`EMQ_ENTRIES-1] ex3_eratm_itag_hit_setHold; + wire [0:`EMQ_ENTRIES-1] ex3_eratm_hit_restart; + wire [0:`EMQ_ENTRIES-1] ex3_eratm_hit_setHold; + wire [0:`EMQ_ENTRIES-1] ex3_eratm_hit_report; + wire ex3_eratm_full; + wire [0:`EMQ_ENTRIES-1] ex3_emq_tlbmiss; + wire [0:`EMQ_ENTRIES-1] ex3_emq_tlbinelig; + wire [0:`EMQ_ENTRIES-1] ex3_emq_ptfault; + wire [0:`EMQ_ENTRIES-1] ex3_emq_lratmiss; + wire [0:`EMQ_ENTRIES-1] ex3_emq_multihit; + wire [0:`EMQ_ENTRIES-1] ex3_emq_tlb_par; + wire [0:`EMQ_ENTRIES-1] ex3_emq_lru_par; + wire [0:`EMQ_ENTRIES-1] ex4_emq_excp_rpt_d; + wire [0:`EMQ_ENTRIES-1] ex4_emq_excp_rpt_q; + wire [0:`EMQ_ENTRIES-1] ex5_emq_excp_rpt_d; + wire [0:`EMQ_ENTRIES-1] ex5_emq_excp_rpt_q; + wire [0:`EMQ_ENTRIES-1] ex6_emq_excp_rpt_d; + wire [0:`EMQ_ENTRIES-1] ex6_emq_excp_rpt_q; + wire [0:`THREADS-1] ex5_tlb_excp_val_d; + wire [0:`THREADS-1] ex5_tlb_excp_val_q; + wire [0:`THREADS-1] ex6_tlb_excp_val_d; + wire [0:`THREADS-1] ex6_tlb_excp_val_q; + wire ex6_tlb_cplt_val; + wire [0:`EMQ_ENTRIES-1] ex6_emq_excp_rpt; + wire ex3_tlbmiss; + wire ex4_tlbmiss_d; + wire ex4_tlbmiss_q; + wire ex3_tlbinelig; + wire ex4_tlbinelig_d; + wire ex4_tlbinelig_q; + wire ex3_ptfault; + wire ex4_ptfault_d; + wire ex4_ptfault_q; + wire ex3_lratmiss; + wire ex4_lratmiss_d; + wire ex4_lratmiss_q; + wire ex3_tlb_multihit; + wire ex4_tlb_multihit_d; + wire ex4_tlb_multihit_q; + wire ex3_tlb_par_err; + wire ex4_tlb_par_err_d; + wire ex4_tlb_par_err_q; + wire ex3_lru_par_err; + wire ex4_lru_par_err_d; + wire ex4_lru_par_err_q; + wire ex4_tlb_excp_det_d; + wire ex4_tlb_excp_det_q; + wire [0:`THREADS-1] ex3_cp_next_tid; + reg [0:`THREADS-1] emq_tid_idle; + wire ex3_nonspec_val; + wire ex4_nonspec_val_d; + wire ex4_nonspec_val_q; + wire ex4_gate_miss_d; + wire ex4_gate_miss_q; + wire ex4_full_restart; + wire ex4_full_restart_d; + wire ex4_full_restart_q; + wire ex4_hit_restart; + wire ex4_itag_hit_restart_d; + wire ex4_itag_hit_restart_q; + wire ex4_epn_hit_restart_d; + wire ex4_epn_hit_restart_q; + wire ex4_setHold; + wire [0:`THREADS-1] ex4_setHold_tid; + wire ex4_setHold_d; + wire ex4_setHold_q; + wire [0:`THREADS-1] derat_dcc_clr_hold_d; + wire [0:`THREADS-1] derat_dcc_clr_hold_q; + wire ex4_derat_restart; + wire ex4_tlbreq_val; + wire ex5_tlbreq_val_d; + wire ex5_tlbreq_val_q; + wire ex5_tlbreq_val; + wire ex5_tlbreq_nonspec_d; + wire ex5_tlbreq_nonspec_q; + wire [0:`THREADS-1] ex5_thdid_d; + wire [0:`THREADS-1] ex5_thdid_q; + wire [0:`EMQ_ENTRIES-1] ex5_emq_d; + wire [0:`EMQ_ENTRIES-1] ex5_emq_q; + wire [0:1] ex5_tlbreq_ttype_d; + wire [0:1] ex5_tlbreq_ttype_q; + wire ex5_tlbreq_blk; + wire [0:`EMQ_ENTRIES-1] ex5_emq_tlbreq_blk; + wire [0:`THREADS-1] ex5_perf_dtlb_d, ex5_perf_dtlb_q; + wire ex4_miss_w_tlb; + wire ex4_miss_wo_tlb; + wire [0:`EMQ_ENTRIES-1] eratm_tlb_rel_val; + wire [0:`EMQ_ENTRIES-1] eratm_wrt_ptr; + wire [0:`EMQ_ENTRIES-1] eratm_entry_available; + wire [0:`EMQ_ENTRIES-1] eratm_entry_cpl; + reg [0:2] eratm_entry_nxt_state[0:`EMQ_ENTRIES-1]; + wire [0:2] eratm_entry_state_d[0:`EMQ_ENTRIES-1]; + wire [0:2] eratm_entry_state_q[0:`EMQ_ENTRIES-1]; + wire [0:`ITAG_SIZE_ENC-1] eratm_entry_itag_d[0:`EMQ_ENTRIES-1]; + wire [0:`ITAG_SIZE_ENC-1] eratm_entry_itag_q[0:`EMQ_ENTRIES-1]; + wire [0:`THREADS-1] eratm_entry_tid_d[0:`EMQ_ENTRIES-1]; + wire [0:`THREADS-1] eratm_entry_tid_q[0:`EMQ_ENTRIES-1]; + wire [0:`THREADS-1] eratm_entry_tid_inuse[0:`EMQ_ENTRIES-1]; + wire [64-(2**`GPR_WIDTH_ENC):51] eratm_entry_epn_d[0:`EMQ_ENTRIES-1]; + wire [64-(2**`GPR_WIDTH_ENC):51] eratm_entry_epn_q[0:`EMQ_ENTRIES-1]; + reg [0:`EMQ_ENTRIES-1] eratm_entry_nonspec_val_d; + wire [0:`EMQ_ENTRIES-1] eratm_entry_nonspec_val_q; + wire [0:`EMQ_ENTRIES-1] eratm_entry_mkill; + wire [0:`EMQ_ENTRIES-1] eratm_entry_mkill_d; + wire [0:`EMQ_ENTRIES-1] eratm_entry_mkill_q; + wire [0:`EMQ_ENTRIES-1] eratm_entry_kill; + wire [0:`EMQ_ENTRIES-1] eratm_entry_inuse; + wire [0:`EMQ_ENTRIES-1] eratm_entry_relPend; + reg [0:`EMQ_ENTRIES-1] eratm_entry_clr_hold; + wire eratm_clrHold; + wire [0:`THREADS-1] eratm_clrHold_tid; + wire [0:1] eratm_setHold_tid_ctrl[0:`THREADS-1]; + wire [0:`THREADS-1] eratm_hold_tid_d; + wire [0:`THREADS-1] eratm_hold_tid_q; + wire [0:`ITAG_SIZE_ENC-1] mm_int_rpt_itag_d; + wire [0:`ITAG_SIZE_ENC-1] mm_int_rpt_itag_q; + wire mm_int_rpt_tlbmiss_d; + wire mm_int_rpt_tlbmiss_q; + wire mm_int_rpt_tlbinelig_d; + wire mm_int_rpt_tlbinelig_q; + wire mm_int_rpt_ptfault_d; + wire mm_int_rpt_ptfault_q; + wire mm_int_rpt_lratmiss_d; + wire mm_int_rpt_lratmiss_q; + wire mm_int_rpt_tlb_multihit_d; + wire mm_int_rpt_tlb_multihit_q; + wire mm_int_rpt_tlb_par_err_d; + wire mm_int_rpt_tlb_par_err_q; + wire mm_int_rpt_lru_par_err_d; + wire mm_int_rpt_lru_par_err_q; + wire [0:`EMQ_ENTRIES-1] mm_int_rpt_tlbmiss_val; + wire [0:`EMQ_ENTRIES-1] mm_int_rpt_tlbinelig_val; + wire [0:`EMQ_ENTRIES-1] mm_int_rpt_ptfault_val; + wire [0:`EMQ_ENTRIES-1] mm_int_rpt_lratmiss_val; + wire [0:`EMQ_ENTRIES-1] mm_int_rpt_tlb_multihit_val; + wire [0:`EMQ_ENTRIES-1] mm_int_rpt_tlb_par_err_val; + wire [0:`EMQ_ENTRIES-1] mm_int_rpt_lru_par_err_val; + wire [0:`EMQ_ENTRIES-1] eratm_entry_tlbmiss_d; + wire [0:`EMQ_ENTRIES-1] eratm_entry_tlbmiss_q; + wire [0:`EMQ_ENTRIES-1] eratm_entry_tlbinelig_d; + wire [0:`EMQ_ENTRIES-1] eratm_entry_tlbinelig_q; + wire [0:`EMQ_ENTRIES-1] eratm_entry_ptfault_d; + wire [0:`EMQ_ENTRIES-1] eratm_entry_ptfault_q; + wire [0:`EMQ_ENTRIES-1] eratm_entry_lratmiss_d; + wire [0:`EMQ_ENTRIES-1] eratm_entry_lratmiss_q; + wire [0:`EMQ_ENTRIES-1] eratm_entry_tlb_multihit_d; + wire [0:`EMQ_ENTRIES-1] eratm_entry_tlb_multihit_q; + wire [0:`EMQ_ENTRIES-1] eratm_entry_tlb_par_err_d; + wire [0:`EMQ_ENTRIES-1] eratm_entry_tlb_par_err_q; + wire [0:`EMQ_ENTRIES-1] eratm_entry_lru_par_err_d; + wire [0:`EMQ_ENTRIES-1] eratm_entry_lru_par_err_q; + wire [0:`EMQ_ENTRIES-1] eratm_entry_int_det; + wire [0:4] rw_entry_d; + wire [0:4] rw_entry_q; + wire rw_entry_val_d; + wire rw_entry_val_q; + wire rw_entry_le_d; + wire rw_entry_le_q; + wire [0:31] cam_entry_le_wr; + wire [0:31] cam_entry_le; + wire [0:31] cam_entry_le_d; + wire [0:31] cam_entry_le_q; + wire [0:31] ex3_cam_byte_rev; + wire [0:31] ex3_cam_entry_le; + wire ex3_cam_hit_le; + wire [0:`THREADS-1] ex3_strg_noop; + wire lq_xu_ord_write_done_d; + wire lq_xu_ord_write_done_q; + wire lq_xu_ord_read_done_d; + wire lq_xu_ord_read_done_q; + wire xu_lq_act_d; + wire xu_lq_act_q; + wire [0:`THREADS-1] xu_lq_val_d; + wire [0:`THREADS-1] xu_lq_val_q; + wire xu_lq_is_eratre_d; + wire xu_lq_is_eratre_q; + wire xu_lq_is_eratwe_d; + wire xu_lq_is_eratwe_q; + wire xu_lq_is_eratsx_d; + wire xu_lq_is_eratsx_q; + wire xu_lq_is_eratilx_d; + wire xu_lq_is_eratilx_q; + wire [0:1] xu_lq_ws_d; + wire [0:1] xu_lq_ws_q; + wire [0:4] xu_lq_ra_entry_d; + wire [0:4] xu_lq_ra_entry_q; + wire [64-(2**`GPR_WIDTH_ENC):63] xu_lq_rs_data_d; + wire [64-(2**`GPR_WIDTH_ENC):63] xu_lq_rs_data_q; + wire csinv_complete; + wire [0:scan_right_0] siv_0; + wire [0:scan_right_0] sov_0; + wire [0:scan_right_1] siv_1; + wire [0:scan_right_1] sov_1; + wire [0:boot_scan_right] bsiv; + wire [0:boot_scan_right] bsov; + // cam component scan chains + wire func_si_cam_int; + wire func_so_cam_int; + //signal tidn : std_ulogic; + wire tiup; + //begin + //@@ START OF EXECUTABLE CODE FOR LQ_DERAT + + //## figtree_source: lq_derat.fig; + //--------------------------------------------------------------------- + // ACT Generation + //--------------------------------------------------------------------- + assign clkg_ctl_override_d = spr_xucr0_clkg_ctl_b1; + assign ex1_stg_act_d = ((|(dec_derat_ex0_val)) | clkg_ctl_override_q | (|(ex0_ttype_val_q))); + assign ex2_stg_act_d = ((dec_derat_ex1_derat_act | dec_derat_ex1_ra_eq_ea | clkg_ctl_override_q) | (|(ex1_valid_op_q)) | |(dec_derat_ex1_pfetch_val)); + assign ex3_stg_act_d = ex2_stg_act_q; + assign ex4_stg_act_d = ex3_stg_act_q; + assign ex5_stg_act_d = ex4_stg_act_q; + assign ex6_stg_act_d = ex5_stg_act_q; + assign ex3_cmp_data_act = ex3_stg_act_q & (~(an_ac_grffence_en_dc_q)); + assign ex3_rd_data_act = ex3_stg_act_q & (~(an_ac_grffence_en_dc_q)); + assign entry_valid_act = (~an_ac_grffence_en_dc_q); + assign entry_match_act = (~an_ac_grffence_en_dc_q); + assign mchk_flash_inv_act = (~an_ac_grffence_en_dc_q); + assign tlb_rel_act_d = mm_derat_rel_data[eratpos_relsoon]; + assign tlb_rel_act = (tlb_rel_act_q & (~(spr_ccr2_notlb_q))) | clkg_ctl_override_q; + assign snoopp_act = snoopp_act_q | clkg_ctl_override_q; + assign snoop_act = snoop_next | ex1_snoop_val_q | clkg_ctl_override_q; + assign cp_flush_d = iu_lq_cp_flush; + //--------------------------------------------------------------------- + // SPR + //--------------------------------------------------------------------- + assign spr_msr_hv_d = xu_lq_spr_msr_hv; + assign spr_msr_pr_d = xu_lq_spr_msr_pr; + assign spr_msr_ds_d = xu_lq_spr_msr_ds; + assign spr_msr_cm_d = xu_lq_spr_msr_cm; + assign spr_ccr2_notlb_d = xu_lq_spr_ccr2_notlb; + //--------------------------------------------------------------------- + // Inputs from Completion + //--------------------------------------------------------------------- + assign cp_next_val_d = iu_lq_recirc_val; + //--------------------------------------------------------------------- + // ERAT Operation Bus + //--------------------------------------------------------------------- + assign xu_lq_act_d = xu_lq_act; + assign xu_lq_val_d = xu_lq_val & (~cp_flush_q); + assign xu_lq_is_eratre_d = xu_lq_is_eratre; + assign xu_lq_is_eratwe_d = xu_lq_is_eratwe; + assign xu_lq_is_eratsx_d = xu_lq_is_eratsx; + assign xu_lq_is_eratilx_d = xu_lq_is_eratilx; + assign xu_lq_ws_d = xu_lq_ws; + assign xu_lq_ra_entry_d = xu_lq_ra_entry; + // RS Data contains the following + // either RB Data for eratsx or RS Data for eratwe + assign xu_lq_rs_data_d = xu_lq_rs_data; + //--------------------------------------------------------------------- + // Logic + //--------------------------------------------------------------------- + assign tiup = 1'b1; + assign init_alias = pc_xu_init_reset_q; + assign mmucr1_d = mm_lq_mmucr1; + assign ex2_byte_rev_d = dec_derat_ex1_byte_rev; + assign ex3_byte_rev_d = ex2_byte_rev_q; + + // timing latches for the ifrat delusional paranoia real mode + assign ccr2_frat_paranoia_d[0:3] = xu_lq_spr_ccr2_dfratsc[0:3]; + assign ccr2_frat_paranoia_d[4] = xu_lq_spr_ccr2_dfratsc[4]; + assign ccr2_frat_paranoia_d[5:8] = xu_lq_spr_ccr2_dfratsc[5:8]; + assign ccr2_frat_paranoia_d[9] = xu_lq_spr_ccr2_dfrat; + assign ccr2_frat_paranoia_d[10] = dec_derat_ex1_ra_eq_ea; + assign ccr2_frat_paranoia_d[11] = ccr2_frat_paranoia_q[10]; + //- latch incoming valid and data -------------------------------------------- + // mmucr1: 0-DRRE, 1-REE, 2-CEE, + // 3-Disable any context sync inst from invalidating extclass=0 erat entries, + // 4-Disable isync inst from invalidating extclass=0 erat entries, + // 5:6-PEI, 7:8-DCTID|DTTID, 9-DCCD + // ttype <= 0-eratre & 1-eratwe & 2-eratsx & 3-eratilx & 4-load & 5-store & + // 6-csync & 7-isync & 8-icbtlslc & 9-touch & 10-extload & 11-extstore; + // context synch operation + assign csync_val_d[0] = iu_lq_csync; + assign isync_val_d[0] = iu_lq_isync; + assign csync_val_d[1] = ((csync_val_q[0] == 1'b1 & mmucr1_q[3] == 1'b0 & spr_ccr2_notlb_q == MMU_Mode_Value)) ? 1'b1 : + (csync_next == 1'b1) ? 1'b0 : + csync_val_q[1]; + assign isync_val_d[1] = ((isync_val_q[0] == 1'b1 & mmucr1_q[4] == 1'b0 & spr_ccr2_notlb_q == MMU_Mode_Value)) ? 1'b1 : + (csync_next == 1'b1) ? 1'b0 : + isync_val_q[1]; + // tlb reload -- one hot val, 4 reloads + assign rel_val_d = (|(mm_derat_rel_val) == 1'b1) ? mm_derat_rel_val[0:3] : + (rel_next == 1'b1) ? {4{1'b0}} : + rel_val_q; + assign rel_hit_d = (|(mm_derat_rel_val) == 1'b1) ? mm_derat_rel_val[4] : + rel_hit_q; + assign rel_data_d = (|(mm_derat_rel_val) == 1'b1) ? mm_derat_rel_data : + rel_data_q; + assign rel_emq_d = (|(mm_derat_rel_val) == 1'b1) ? mm_derat_rel_emq : + rel_emq_q; + // Need to update Interrupt Status for each EMQ when the reload is valid + assign rel_int_upd_val_d = (mm_derat_rel_emq & {`EMQ_ENTRIES{(|(mm_derat_rel_val))}}); + // write External PID Lo + assign epsc_wr_val_d = (|(spr_derat_epsc_wr) == 1'b1) ? spr_derat_epsc_wr : + (epsc_next == 1'b1) ? {`THREADS{1'b0}} : + epsc_wr_val_q; + assign eplc_wr_val_d = (|(spr_derat_eplc_wr) == 1'b1) ? spr_derat_eplc_wr : + (eplc_next == 1'b1) ? {`THREADS{1'b0}} : + eplc_wr_val_q; + // D$ snoop + assign rv1_binv_val_d = lsq_ctl_rv0_binv_val; + // tlbivax or tlbilx sno + assign snoopp_val_d = (mm_lq_snoop_val == 1'b1) ? 1'b1 : + (snoop_next == 1'b1) ? 1'b0 : + snoopp_val_q; + assign snoopp_attr_d = (mm_lq_snoop_val == 1'b1) ? mm_lq_snoop_attr : + snoopp_attr_q; + assign snoopp_vpn_d = (mm_lq_snoop_val == 1'b1) ? mm_lq_snoop_vpn : + snoopp_vpn_q; + // ordered ttype = 0-eratre 1-eratwe 2-eratsx 3-eratilx + // ttype_val_d, ttype_d, -- fix (is ilx is not needed) check with Jon + assign ttype_val_d = (|(xu_lq_val_q) == 1'b1) ? (xu_lq_val_q & (~cp_flush_q)) : + ((eratre_next | eratwe_next | eratsx_next) == 1'b1) ? {`THREADS{1'b0}} : + (ttype_val_q & (~cp_flush_q)); + assign ttype_d = (|(xu_lq_val_q) == 1'b1) ? {xu_lq_is_eratre_q, xu_lq_is_eratwe_q, xu_lq_is_eratsx_q, 1'b0} : + ((eratre_next | eratwe_next | eratsx_next) == 1'b1) ? 4'b0000 : + ttype_q; + assign ws_d = (|(xu_lq_val_q) == 1'b1) ? xu_lq_ws_q : + ws_q; + assign ra_entry_d = (|(xu_lq_val_q) == 1'b1) ? xu_lq_ra_entry_q : + ra_entry_q; + assign rs_data_d = (|(xu_lq_val_q) == 1'b1) ? xu_lq_rs_data_q : + rs_data_q; + // generate pipeline hole for non-ld/st ops ------------------------------------ + // eratre op extended hole + assign eratre_hole_d[3] = (~(|(eratre_hole_q))) & eratre_next; + assign eratre_hole_d[2] = eratre_hole_q[3]; + assign eratre_hole_d[1] = eratre_hole_q[2]; + assign eratre_hole_d[0] = eratre_hole_q[1]; + assign eratwe_hole_d[3] = (~(|(eratwe_hole_q))) & eratwe_next; + assign eratwe_hole_d[2] = eratwe_hole_q[3]; + assign eratwe_hole_d[1] = eratwe_hole_q[2]; + assign eratwe_hole_d[0] = eratwe_hole_q[1]; + assign eratrw_hole = |({eratre_hole_q, eratwe_hole_q}); + + assign rel_hole = tlb_rel_act_q | lru_update_event_q[0] | |(rel_val_q | rv1_rel_val_q | ex0_rel_val_q | ex1_rel_val_q | tlb_rel_val_q[0:3]); + + assign derat_dec_hole_all = |({csync_val_q[1], isync_val_q[1], rel_hole, epsc_wr_val_q, eplc_wr_val_q, + snoopp_val_q, ttype_val_q, eratrw_hole, por_hold_req}); + + //- arb Priorities ------------------------------------------------------------- + assign arb_pri[0] = ~(eratrw_hole); + assign arb_pri[1] = ~(csync_val_q[1] | isync_val_q[1] | eratrw_hole); + assign arb_pri[2] = ~(csync_val_q[1] | isync_val_q[1] | |(rel_val_q[0:3]) | eratrw_hole); + assign arb_pri[3] = ~(csync_val_q[1] | isync_val_q[1] | |(rel_val_q[0:3]) | |(epsc_wr_val_q) | |(eplc_wr_val_q) | eratrw_hole | lsq_ctl_rv0_binv_val); + assign arb_pri[4] = ~(csync_val_q[1] | isync_val_q[1] | |(rel_val_q[0:3]) | |(epsc_wr_val_q) | |(eplc_wr_val_q) | snoopp_val_q | lsq_ctl_rv0_binv_val); + + assign csync_next = (csync_val_q[1] | isync_val_q[1]) & arb_pri[0]; + assign rel_next = (|(rel_val_q[0:3])) & arb_pri[1]; + assign epsc_next = (|(epsc_wr_val_q)) & arb_pri[2]; + assign eplc_next = (|(eplc_wr_val_q)) & arb_pri[2]; + assign snoop_next = snoopp_val_q & arb_pri[3]; + assign eratre_next = (|((ttype_val_q) & (~cp_flush_q))) & ttype_q[0] & arb_pri[4]; + assign eratwe_next = (|((ttype_val_q) & (~cp_flush_q))) & ttype_q[1] & arb_pri[4]; + assign eratsx_next = (|((ttype_val_q) & (~cp_flush_q))) & ttype_q[2] & arb_pri[4]; + + // last priority lsu op (load, store, etc) + + //- pipe valids to the old interface ------------------------------------------- + assign rv1_ttype_val_d = ((eratre_next | eratwe_next | eratsx_next) == 1'b1) ? (ttype_val_q & (~cp_flush_q)) : + {`THREADS{1'b0}}; + assign rv1_ttype_d = ttype_q; + assign rv1_csync_val_d = csync_val_q[1] & csync_next; + assign rv1_isync_val_d = isync_val_q[1] & csync_next; + assign rv1_rel_val_d = (rel_next == 1'b1) ? rel_val_q : + {4{1'b0}}; + assign rv1_epsc_wr_val_d = (epsc_next == 1'b1) ? epsc_wr_val_q : + {`THREADS{1'b0}}; + assign rv1_eplc_wr_val_d = (eplc_next == 1'b1) ? eplc_wr_val_q : + {`THREADS{1'b0}}; + assign rv1_snoop_val_d = snoop_next; + assign ex0_ttype_val_d = rv1_ttype_val_q & (~cp_flush_q); + assign ex0_ttype_d = rv1_ttype_q; + assign ex0_isync_val_d = rv1_isync_val_q; + assign ex0_csync_val_d = rv1_csync_val_q; + assign ex0_rel_val_d = rv1_rel_val_q; + assign ex0_epsc_wr_val_d = rv1_epsc_wr_val_q; + assign ex0_eplc_wr_val_d = rv1_eplc_wr_val_q; + assign ex0_snoop_val_d = rv1_snoop_val_q; + assign ex0_binv_val_d = rv1_binv_val_q; + assign ex1_binv_val_d = ex0_binv_val_q; + assign ex1_rel_val_d = ex0_rel_val_q; + assign ex1_snoop_val_d = ex0_snoop_val_q; + assign ex1_ttype03_d = (ex0_ttype_q & {4{(|(ex0_ttype_val_q))}}); + assign ex1_ttype67_d = {ex0_csync_val_q, ex0_isync_val_q}; + + // old logic ------------------------------------------------------------------- + // reloads + assign tlb_rel_val_d = {ex1_rel_val_q, (rel_hit_q & (|(ex1_rel_val_q)))}; + assign tlb_rel_data_d = rel_data_q; + assign tlb_rel_emq_d = rel_emq_q; + // ex0 ------------------------------------------------------------------------- + // Need to separate ex0_csync_val and ex0_isync_val because they should not be blocked by byp_derat_ex2_req_aborted + assign ex1_valid_d = (dec_derat_ex0_val & (~cp_flush_q)); + assign ex1_ttype_d = (({dec_derat_ex0_is_extload, dec_derat_ex0_is_extstore}) & {2{(|(dec_derat_ex0_val))}}); + assign ex1_valid_op_d = ex0_ttype_val_q & (~cp_flush_q); + // ex1 ------------------------------------------------------------------------- + assign ex1_valid = ((ex1_valid_q | ex1_valid_op_q) & (~cp_flush_q)) | dec_derat_ex1_pfetch_val; + assign ex1_is_icbtlslc = dec_derat_ex1_icbtls_instr | dec_derat_ex1_icblc_instr; + assign ex1_eplc_epr = |(spr_derat_eplc_epr & ex1_valid); + assign ex1_eplc_egs = |(spr_derat_eplc_egs & ex1_valid); + assign ex1_eplc_eas = |(spr_derat_eplc_eas & ex1_valid); + assign ex1_epsc_epr = |(spr_derat_epsc_epr & ex1_valid); + assign ex1_epsc_egs = |(spr_derat_epsc_egs & ex1_valid); + assign ex1_epsc_eas = |(spr_derat_epsc_eas & ex1_valid); + assign ex1_mmucr0_gs = |(derat_mmucr0_gs & ex1_valid); + assign ex1_mmucr0_ts = |(derat_mmucr0_ts & ex1_valid); + // ttype <= 0-eratre 1-eratwe 2-eratsx 3-eratilx 4-load 5-store + // 6-csync 7-isync 8-icbtlslc 9-touch 10-extload 11-extstore + assign ex2_valid_d = ex1_valid_q & (~cp_flush_q); + assign ex2_itag_d = dec_derat_ex1_itag; + assign ex2_pfetch_val_d = dec_derat_ex1_pfetch_val; + assign ex2_valid_op_d = ex1_valid_op_q & (~cp_flush_q); + assign ex2_valid = (((ex2_valid_q & {`THREADS{~byp_derat_ex2_req_aborted}}) | ex2_valid_op_q) & (~cp_flush_q)) | ex2_pfetch_val_q; + assign ex2_ttype_d = {ex1_ttype03_q, + (({dec_derat_ex1_is_load, dec_derat_ex1_is_store}) & {2{(~(|(ex1_ttype03_q)))}}), + ex1_ttype67_q, + (({ex1_is_icbtlslc, dec_derat_ex1_is_touch, ex1_ttype_q[10], ex1_ttype_q[11]}) & {4{(~(|(ex1_ttype03_q)))}})}; + + assign ex2_ws_d = ws_q; + assign ex2_rs_is_d = {rs_is_width{1'b0}}; + assign ex2_ra_entry_d = ra_entry_q; + assign csinv_complete = |(ex2_ttype_q[6:7]); + + generate + begin : sprThrd + genvar tid; + for (tid = 0; tid <= `THREADS - 1; tid = tid + 1) + begin : sprThrd + assign derat_mmucr0[tid] = mm_lq_mmucr0[tid*20:(tid*20)+20-1]; + assign derat_mmucr0_gs[tid] = mm_lq_mmucr0[(tid*20)+2]; + assign derat_mmucr0_ts[tid] = mm_lq_mmucr0[(tid*20)+3]; + assign derat_eplc_elpid[tid] = spr_derat_eplc_elpid[8 * tid:(8 * tid) + 7]; + assign derat_eplc_epid[tid] = spr_derat_eplc_epid[14 * tid:(14 * tid) + 13]; + assign derat_epsc_elpid[tid] = spr_derat_epsc_elpid[8 * tid:(8 * tid) + 7]; + assign derat_epsc_epid[tid] = spr_derat_epsc_epid[14 * tid:(14 * tid) + 13]; + assign derat_pid[tid] = mm_lq_pid[tid*14:(tid*14)+14-1]; + end + end + endgenerate + + //always @(derat_eplc_epid or derat_epsc_epid or derat_mmucr0 or derat_pid or derat_eplc_elpid or derat_epsc_elpid or ex3_ttype_q[10:11] or rpn_holdreg_q or ex1_valid or ex2_valid or ex3_valid_req) + always @(*) + begin: tidSpr + reg [0:13] eplc_epid; + reg [0:13] epsc_epid; + reg [0:13] mmucr0_pid; + reg [0:13] pid; + reg [0:7] eplc_elpid; + reg [0:7] epsc_elpid; + reg [0:1] extclass; + reg [0:1] tlbsel; + reg [0:63] rpnHold; + //(* analysis_not_referenced="true" *) + integer tid; + + eplc_epid = {14{1'b0}}; + epsc_epid = {14{1'b0}}; + mmucr0_pid = {14{1'b0}}; + pid = {14{1'b0}}; + eplc_elpid = {8{1'b0}}; + epsc_elpid = {8{1'b0}}; + extclass = {2{1'b0}}; + tlbsel = {2{1'b0}}; + rpnHold = {64{1'b0}}; + + for (tid = 0; tid <= `THREADS - 1; tid = tid + 1) + begin + eplc_epid = (derat_eplc_epid[tid] & {14{ex1_valid[tid]}}) | eplc_epid; + epsc_epid = (derat_epsc_epid[tid] & {14{ex1_valid[tid]}}) | epsc_epid; + mmucr0_pid = (derat_mmucr0[tid][6:19] & {14{ex1_valid[tid]}}) | mmucr0_pid; + pid = (derat_pid[tid] & {14{ex1_valid[tid]}}) | pid; + eplc_elpid = (derat_eplc_elpid[tid] & {8{(ex3_valid_req[tid] & ex3_ttype_q[10])}}) | eplc_elpid; + epsc_elpid = (derat_epsc_elpid[tid] & {8{(ex3_valid_req[tid] & ex3_ttype_q[11])}}) | epsc_elpid; + extclass = (derat_mmucr0[tid][0:1] & {2{ex1_valid[tid]}}) | extclass; + tlbsel = (derat_mmucr0[tid][4:5] & {2{ex1_valid[tid]}}) | tlbsel; + rpnHold = (rpn_holdreg_q[tid] & {64{ex2_valid[tid]}}) | rpnHold; + end + ex1_eplc_epid = eplc_epid; + ex1_epsc_epid = epsc_epid; + ex1_mmucr0_pid = mmucr0_pid; + ex1_pid = pid; + ex3_eplc_elpid = eplc_elpid; + ex3_epsc_elpid = epsc_elpid; + ex2_extclass_d = extclass; + ex2_tlbsel_d = tlbsel; + ex2_rpn_holdreg = rpnHold; + end + assign ex2_state_d[0] = (ex1_ttype_q[10] == 1'b1) ? ex1_eplc_epr : + (ex1_ttype_q[11] == 1'b1) ? ex1_epsc_epr : + |(spr_msr_pr_q & ex1_valid); + assign ex2_state_d[1] = (ex1_ttype_q[10] == 1'b1) ? ex1_eplc_egs : + (ex1_ttype_q[11] == 1'b1) ? ex1_epsc_egs : + ((ex1_ttype03_q[1] == 1'b1 | ex1_ttype03_q[2] == 1'b1)) ? ex1_mmucr0_gs : + |(spr_msr_hv_q & ex1_valid); + assign ex2_state_d[2] = (ex1_ttype_q[10] == 1'b1) ? ex1_eplc_eas : + (ex1_ttype_q[11] == 1'b1) ? ex1_epsc_eas : + ((ex1_ttype03_q[1] == 1'b1 | ex1_ttype03_q[2] == 1'b1)) ? ex1_mmucr0_ts : + |(spr_msr_ds_q & ex1_valid); + assign ex2_state_d[3] = |(spr_msr_cm_q & ex1_valid); + assign ex2_pid_d = (ex1_ttype_q[10] == 1'b1) ? ex1_eplc_epid : + (ex1_ttype_q[11] == 1'b1) ? ex1_epsc_epid : + ((ex1_ttype03_q[1] == 1'b1 | ex1_ttype03_q[2] == 1'b1)) ? ex1_mmucr0_pid : + ex1_pid; + assign ex2_data_in_d = rs_data_q; + // ex2 ------------------------------------------------------------------------- + assign ex2_deratre = (|(ex2_valid_op_q)) & ex2_ttype_q[0] & ex2_tlbsel_q[0] & ex2_tlbsel_q[1]; + assign ex2_deratwe = (|(ex2_valid_op_q)) & ex2_ttype_q[1] & ex2_tlbsel_q[0] & ex2_tlbsel_q[1]; + assign ex2_deratsx = (|(ex2_valid_op_q)) & ex2_ttype_q[2] & ex2_tlbsel_q[0] & ex2_tlbsel_q[1]; + assign ex3_valid_d = (ex2_valid_q & {`THREADS{~byp_derat_ex2_req_aborted}}) & ~cp_flush_q; + assign ex3_itag_d = ex2_itag_q; + assign ex3_pfetch_val_d = ex2_pfetch_val_q; + assign ex3_valid_op_d = ex2_valid_op_q & (~cp_flush_q); + assign ex3_strg_noop = {`THREADS{dcc_derat_ex3_strg_noop}}; + assign ex3_valid = (((ex3_valid_q & (~ex3_strg_noop)) | ex3_valid_op_q) & (~(cp_flush_q))) | ex3_pfetch_val_q; + assign ex3_valid_req = ex3_valid_q | ex3_valid_op_q | ex3_pfetch_val_q; + assign ex3_ttype_d = ex2_ttype_q; + assign ex3_ws_d = ex2_ws_q; + assign ex3_rs_is_d = ex2_rs_is_d; + assign ex3_ra_entry_d = ex2_ra_entry_d; + assign ex3_state_d = ex2_state_q; + assign ex3_extclass_d = ex2_extclass_q; + assign ex3_tlbsel_d = ex2_tlbsel_q; + assign ex3_pid_d = ex2_pid_q; + // ex3 ------------------------------------------------------------------------- + assign ex4_valid_d = ex3_valid_q & (~(cp_flush_q | ex3_strg_noop)); + assign ex4_itag_d = ex3_itag_q; + assign ex4_pfetch_val_d = ex3_pfetch_val_q; + assign ex4_valid_op_d = ex3_valid_op_q & (~cp_flush_q); + assign ex4_ttype_d = ex3_ttype_q; + assign ex4_ws_d = ex3_ws_q; + assign ex4_rs_is_d = ex3_rs_is_q; + assign ex4_ra_entry_d = ex3_ra_entry_q; + // state: 0:pr 1:gs 2:ds 3:cm + assign ex4_state_d = ex3_state_q; + assign ex4_extclass_d = ex3_extclass_q; + assign ex4_tlbsel_d = ex3_tlbsel_q; + assign ex4_pid_d = ex3_pid_q; + assign ex4_lpid_d[0:lpid_width - 1] = ex3_eplc_elpid | ex3_epsc_elpid; + // ex4 ------------------------------------------------------------------------- + // ttype <= 0-eratre 1-eratwe 2-eratsx 3-eratilx 4-load 5-store + // 6-csync 7-isync 8-icbtlslc 9-touch 10-extload 11-extstore + assign ex4_valid = ((ex4_valid_q | ex4_valid_op_q) & (~cp_flush_q)) | ex4_pfetch_val_q; + assign ex4_deratwe = (|(ex4_valid)) & ex4_ttype_q[1] & ex4_tlbsel_q[0] & ex4_tlbsel_q[1]; + assign ex4_rd_array_data_d = rd_array_data; + assign ex4_rd_cam_data_d = rd_cam_data; + assign ex5_valid_d = ex4_valid_q & (~(cp_flush_q)) & (~(ex4_miss_q)); + assign ex5_itag_d = ex4_itag_q; + assign ex5_pfetch_val_d = ex4_pfetch_val_q; + assign ex5_valid_op_d = ex4_valid_op_q & (~cp_flush_q); + assign ex5_ttype_d = ex4_ttype_q; + assign ex5_ws_d = ex4_ws_q; + assign ex5_rs_is_d = ex4_rs_is_q; + // ra_entry becomes hit_entry for search, inval, load, or store + assign ex5_ra_entry_d = (ex4_ttype_q[2:5] != 4'b0000) ? ex4_first_hit_entry : + ex4_ra_entry_q; + assign ex5_tlbsel_d = ex4_tlbsel_q; + // muxes for tlbre and sending mmucr0 ExtClass,State,TID + assign ex5_extclass_d = ((|(ex4_valid) == 1'b1 & ex4_ttype_q[0] == 1'b1 & ex4_ws_q == 2'b00)) ? ex4_rd_cam_data_q[63:64] : + ex4_extclass_q; + assign ex5_state_d = ((|(ex4_valid) == 1'b1 & ex4_ttype_q[0] == 1'b1 & ex4_ws_q == 2'b00)) ? {ex4_state_q[0], ex4_rd_cam_data_q[65:66], ex4_state_q[3]} : + ex4_state_q; + assign ex5_pid_d = ((|(ex4_valid) == 1'b1 & ex4_ttype_q[0] == 1'b1 & ex4_ws_q == 2'b00)) ? {ex4_rd_cam_data_q[61:62], ex4_rd_cam_data_q[57:60], ex4_rd_cam_data_q[67:74]} : + ex4_pid_q; + assign ex5_lpid_d = ex4_lpid_q; + // ex5 ------------------------------------------------------------------------- + assign ex5_valid = ((ex5_valid_q | ex5_valid_op_q) & (~cp_flush_q)) | ex5_pfetch_val_q; + assign ex5_deratwe = (|(ex5_valid)) & ex5_ttype_q[1] & ex5_tlbsel_q[0] & ex5_tlbsel_q[1]; + assign ex6_valid_d = ex5_valid_q & (~(cp_flush_q)); + assign ex6_itag_d = ex5_itag_q; + assign ex6_valid_op_d = ex5_valid_op_q & (~cp_flush_q); + assign ex6_pfetch_val_d = ex5_pfetch_val_q; + assign ex6_ws_d = ex5_ws_q; + assign ex6_rs_is_d = ex5_rs_is_q; + assign ex6_ra_entry_d = ex5_ra_entry_q; + assign ex6_ttype_d = ex5_ttype_q; + assign ex6_extclass_d = ex5_extclass_q; + // state: 0:pr 1:gs 2:ds 3:cm + assign ex6_state_d = ex5_state_q; + assign ex6_pid_d = ex5_pid_q; + assign ex6_tlbsel_d = ex5_tlbsel_q; + // ex6 ------------------------------------------------------------------------- + assign ex6_valid = ((ex6_valid_q | ex6_valid_op_q) & (~cp_flush_q)) | ex6_pfetch_val_q; + assign ex6_deratwe = (|(ex6_valid)) & ex6_ttype_q[1] & ex6_tlbsel_q[0] & ex6_tlbsel_q[1]; + assign ex7_valid_d = ex6_valid_q & (~(cp_flush_q)); + assign ex7_valid_op_d = ex6_valid_op_q & (~cp_flush_q); + assign ex7_pfetch_val_d = ex6_pfetch_val_q; + assign ex7_ws_d = ex6_ws_q; + assign ex7_rs_is_d = ex6_rs_is_q; + assign ex7_ra_entry_d = ex6_ra_entry_q; + assign ex7_extclass_d = ex6_extclass_q; + assign ex7_tlbsel_d = ex6_tlbsel_q; + assign ex7_pid_d = ex6_pid_q; + assign ex7_state_d = ex6_state_q; + assign ex7_ttype_d = ex6_ttype_q; + // mmucr1: 0-DRRE, 1-REE, 2-CEE, + // 3-Disable any context sync inst from invalidating extclass=0 erat entries, + // 4-Disable isync inst from invalidating extclass=0 erat entries, + // 5:6-PEI, 7:8-DCTID|DTTID, 9-DCCD + // ttype <= 0-eratre & 1-eratwe & 2-eratsx & 3-eratilx & 4-load & 5-store & + // 6-csync & 7-isync & 8-icbtlslc & 9-touch & 10-extload & 11-extstore; + // ex7 ------------------------------------------------------------------------- + assign ex7_valid = ((ex7_valid_q | ex7_valid_op_q) & (~cp_flush_q)) | ex7_pfetch_val_q; + assign ex7_deratwe = (|(ex7_valid)) & ex7_ttype_q[1] & ex7_tlbsel_q[0] & ex7_tlbsel_q[1]; + // for flushing + assign ex8_valid_d = ex7_valid_q; + assign ex8_valid_op_d = ex7_valid_op_q & (~cp_flush_q); + assign ex8_pfetch_val_d = ex7_pfetch_val_q; + assign ex8_ttype_d = ex7_ttype_q; + assign ex8_tlbsel_d = ex7_tlbsel_q; + // ex8 ------------------------------------------------------------------------- + assign ex8_valid = ((ex8_valid_q | ex8_valid_op_q) & (~cp_flush_q)) | ex8_pfetch_val_q; + assign ex8_deratwe = (|(ex8_valid)) & ex8_ttype_q[1] & ex8_tlbsel_q[0] & ex8_tlbsel_q[1]; + // formation of ex3 phase multihit complement signal + // + // Final Table Listing + // *INPUTS*==============================*OUTPUTS*==========* + // | | | + // | entry_match | ex3_multihit_b | + // | | | | | + // | | | | | + // | | | | | + // | | 1111111111222222222233 | | | + // | 01234567890123456789012345678901 | | | + // *TYPE*================================+==================+ + // | PPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPP | P | + // *POLARITY*--------------------------->| + | + // *PHASE*------------------------------>| T | + // *OPTIMIZE*--------------------------->| A | + // *TERMS*===============================+==================+ + // 1 | -0000000000000000000000000000000 | 1 | + // 2 | 0-000000000000000000000000000000 | 1 | + // 3 | 00-00000000000000000000000000000 | 1 | + // 4 | 000-0000000000000000000000000000 | 1 | + // 5 | 0000-000000000000000000000000000 | 1 | + // 6 | 00000-00000000000000000000000000 | 1 | + // 7 | 000000-0000000000000000000000000 | 1 | + // 8 | 0000000-000000000000000000000000 | 1 | + // 9 | 00000000-00000000000000000000000 | 1 | + // 10 | 000000000-0000000000000000000000 | 1 | + // 11 | 0000000000-000000000000000000000 | 1 | + // 12 | 00000000000-00000000000000000000 | 1 | + // 13 | 000000000000-0000000000000000000 | 1 | + // 14 | 0000000000000-000000000000000000 | 1 | + // 15 | 00000000000000-00000000000000000 | 1 | + // 16 | 000000000000000-0000000000000000 | 1 | + // 17 | 0000000000000000-000000000000000 | 1 | + // 18 | 00000000000000000-00000000000000 | 1 | + // 19 | 000000000000000000-0000000000000 | 1 | + // 20 | 0000000000000000000-000000000000 | 1 | + // 21 | 00000000000000000000-00000000000 | 1 | + // 22 | 000000000000000000000-0000000000 | 1 | + // 23 | 0000000000000000000000-000000000 | 1 | + // 24 | 00000000000000000000000-00000000 | 1 | + // 25 | 000000000000000000000000-0000000 | 1 | + // 26 | 0000000000000000000000000-000000 | 1 | + // 27 | 00000000000000000000000000-00000 | 1 | + // 28 | 000000000000000000000000000-0000 | 1 | + // 29 | 0000000000000000000000000000-000 | 1 | + // 30 | 00000000000000000000000000000-00 | 1 | + // 31 | 000000000000000000000000000000-0 | 1 | + // 32 | 0000000000000000000000000000000- | 1 | + // *========================================================* + // + // Table EX3_MULTIHIT_B Signal Assignments for Product Terms + assign EX3_MULTIHIT_B_PT[1] = (({entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000); + assign EX3_MULTIHIT_B_PT[2] = (({entry_match[0], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000); + assign EX3_MULTIHIT_B_PT[3] = (({entry_match[0], entry_match[1], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000); + assign EX3_MULTIHIT_B_PT[4] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000); + assign EX3_MULTIHIT_B_PT[5] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000); + assign EX3_MULTIHIT_B_PT[6] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000); + assign EX3_MULTIHIT_B_PT[7] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000); + assign EX3_MULTIHIT_B_PT[8] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000); + assign EX3_MULTIHIT_B_PT[9] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000); + assign EX3_MULTIHIT_B_PT[10] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000); + assign EX3_MULTIHIT_B_PT[11] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000); + assign EX3_MULTIHIT_B_PT[12] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000); + assign EX3_MULTIHIT_B_PT[13] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000); + assign EX3_MULTIHIT_B_PT[14] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000); + assign EX3_MULTIHIT_B_PT[15] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000); + assign EX3_MULTIHIT_B_PT[16] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000); + assign EX3_MULTIHIT_B_PT[17] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000); + assign EX3_MULTIHIT_B_PT[18] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000); + assign EX3_MULTIHIT_B_PT[19] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000); + assign EX3_MULTIHIT_B_PT[20] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000); + assign EX3_MULTIHIT_B_PT[21] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000); + assign EX3_MULTIHIT_B_PT[22] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000); + assign EX3_MULTIHIT_B_PT[23] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000); + assign EX3_MULTIHIT_B_PT[24] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000); + assign EX3_MULTIHIT_B_PT[25] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000); + assign EX3_MULTIHIT_B_PT[26] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000); + assign EX3_MULTIHIT_B_PT[27] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[27], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000); + assign EX3_MULTIHIT_B_PT[28] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000); + assign EX3_MULTIHIT_B_PT[29] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[29], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000); + assign EX3_MULTIHIT_B_PT[30] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[30], entry_match[31]}) == 31'b0000000000000000000000000000000); + assign EX3_MULTIHIT_B_PT[31] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[31]}) == 31'b0000000000000000000000000000000); + assign EX3_MULTIHIT_B_PT[32] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30]}) == 31'b0000000000000000000000000000000); + // Table EX3_MULTIHIT_B Signal Assignments for Outputs + assign ex3_multihit_b = (EX3_MULTIHIT_B_PT[1] | EX3_MULTIHIT_B_PT[2] | EX3_MULTIHIT_B_PT[3] | EX3_MULTIHIT_B_PT[4] | EX3_MULTIHIT_B_PT[5] | EX3_MULTIHIT_B_PT[6] | EX3_MULTIHIT_B_PT[7] | EX3_MULTIHIT_B_PT[8] | EX3_MULTIHIT_B_PT[9] | EX3_MULTIHIT_B_PT[10] | EX3_MULTIHIT_B_PT[11] | EX3_MULTIHIT_B_PT[12] | EX3_MULTIHIT_B_PT[13] | EX3_MULTIHIT_B_PT[14] | EX3_MULTIHIT_B_PT[15] | EX3_MULTIHIT_B_PT[16] | EX3_MULTIHIT_B_PT[17] | EX3_MULTIHIT_B_PT[18] | EX3_MULTIHIT_B_PT[19] | EX3_MULTIHIT_B_PT[20] | EX3_MULTIHIT_B_PT[21] | EX3_MULTIHIT_B_PT[22] | EX3_MULTIHIT_B_PT[23] | EX3_MULTIHIT_B_PT[24] | EX3_MULTIHIT_B_PT[25] | EX3_MULTIHIT_B_PT[26] | EX3_MULTIHIT_B_PT[27] | EX3_MULTIHIT_B_PT[28] | EX3_MULTIHIT_B_PT[29] | EX3_MULTIHIT_B_PT[30] | EX3_MULTIHIT_B_PT[31] | EX3_MULTIHIT_B_PT[32]); + + assign ex3_multihit = (~ex3_multihit_b); + assign ex4_multihit_b_pt_d = EX3_MULTIHIT_B_PT; + assign ex4_multihit_enab = (~(|(ex4_multihit_b_pt_q))); + // Encoder for the ex3 phase first hit entry number + // + // Final Table Listing + // *INPUTS*==============================*OUTPUTS*==============* + // | | | + // | entry_match | ex3_first_hit_entry | + // | | | | | + // | | | | | + // | | | | | + // | | 1111111111222222222233 | | | + // | 01234567890123456789012345678901 | 01234 | + // *TYPE*================================+======================+ + // | PPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPP | PPPPP | + // *POLARITY*--------------------------->| +++++ | + // *PHASE*------------------------------>| TTTTT | + // *OPTIMIZE*--------------------------->| AAAAA | + // *TERMS*===============================+======================+ + // 1 | 00000000000000000000000000000001 | 11111 | + // 2 | 0000000000000000000000000000001- | 1111. | + // 3 | 000000000000000000000000000001-- | 111.1 | + // 4 | 00000000000000000000000000001--- | 111.. | + // 5 | 0000000000000000000000000001---- | 11.11 | + // 6 | 000000000000000000000000001----- | 11.1. | + // 7 | 00000000000000000000000001------ | 11..1 | + // 8 | 0000000000000000000000001------- | 11... | + // 9 | 000000000000000000000001-------- | 1.111 | + // 10 | 00000000000000000000001--------- | 1.11. | + // 11 | 0000000000000000000001---------- | 1.1.1 | + // 12 | 000000000000000000001----------- | 1.1.. | + // 13 | 00000000000000000001------------ | 1..11 | + // 14 | 0000000000000000001------------- | 1..1. | + // 15 | 000000000000000001-------------- | 1...1 | + // 16 | 00000000000000001--------------- | 1.... | + // 17 | 0000000000000001---------------- | .1111 | + // 18 | 000000000000001----------------- | .111. | + // 19 | 00000000000001------------------ | .11.1 | + // 20 | 0000000000001------------------- | .11.. | + // 21 | 000000000001-------------------- | .1.11 | + // 22 | 00000000001--------------------- | .1.1. | + // 23 | 0000000001---------------------- | .1..1 | + // 24 | 000000001----------------------- | .1... | + // 25 | 00000001------------------------ | ..111 | + // 26 | 0000001------------------------- | ..11. | + // 27 | 000001-------------------------- | ..1.1 | + // 28 | 00001--------------------------- | ..1.. | + // 29 | 0001---------------------------- | ...11 | + // 30 | 001----------------------------- | ...1. | + // 31 | 01------------------------------ | ....1 | + // *============================================================* + // + // Table EX3_FIRST_HIT_ENTRY Signal Assignments for Product Terms + assign EX3_FIRST_HIT_ENTRY_PT[1] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30], entry_match[31]}) == 32'b00000000000000000000000000000001); + assign EX3_FIRST_HIT_ENTRY_PT[2] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29], entry_match[30]}) == 31'b0000000000000000000000000000001); + assign EX3_FIRST_HIT_ENTRY_PT[3] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28], entry_match[29]}) == 30'b000000000000000000000000000001); + assign EX3_FIRST_HIT_ENTRY_PT[4] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27], entry_match[28]}) == 29'b00000000000000000000000000001); + assign EX3_FIRST_HIT_ENTRY_PT[5] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26], entry_match[27]}) == 28'b0000000000000000000000000001); + assign EX3_FIRST_HIT_ENTRY_PT[6] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25], entry_match[26]}) == 27'b000000000000000000000000001); + assign EX3_FIRST_HIT_ENTRY_PT[7] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24], entry_match[25]}) == 26'b00000000000000000000000001); + assign EX3_FIRST_HIT_ENTRY_PT[8] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23], entry_match[24]}) == 25'b0000000000000000000000001); + assign EX3_FIRST_HIT_ENTRY_PT[9] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22], entry_match[23]}) == 24'b000000000000000000000001); + assign EX3_FIRST_HIT_ENTRY_PT[10] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21], entry_match[22]}) == 23'b00000000000000000000001); + assign EX3_FIRST_HIT_ENTRY_PT[11] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20], entry_match[21]}) == 22'b0000000000000000000001); + assign EX3_FIRST_HIT_ENTRY_PT[12] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19], entry_match[20]}) == 21'b000000000000000000001); + assign EX3_FIRST_HIT_ENTRY_PT[13] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18], entry_match[19]}) == 20'b00000000000000000001); + assign EX3_FIRST_HIT_ENTRY_PT[14] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17], entry_match[18]}) == 19'b0000000000000000001); + assign EX3_FIRST_HIT_ENTRY_PT[15] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16], entry_match[17]}) == 18'b000000000000000001); + assign EX3_FIRST_HIT_ENTRY_PT[16] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15], entry_match[16]}) == 17'b00000000000000001); + assign EX3_FIRST_HIT_ENTRY_PT[17] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14], entry_match[15]}) == 16'b0000000000000001); + assign EX3_FIRST_HIT_ENTRY_PT[18] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13], entry_match[14]}) == 15'b000000000000001); + assign EX3_FIRST_HIT_ENTRY_PT[19] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12], entry_match[13]}) == 14'b00000000000001); + assign EX3_FIRST_HIT_ENTRY_PT[20] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11], entry_match[12]}) == 13'b0000000000001); + assign EX3_FIRST_HIT_ENTRY_PT[21] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10], entry_match[11]}) == 12'b000000000001); + assign EX3_FIRST_HIT_ENTRY_PT[22] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9], entry_match[10]}) == 11'b00000000001); + assign EX3_FIRST_HIT_ENTRY_PT[23] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8], entry_match[9]}) == 10'b0000000001); + assign EX3_FIRST_HIT_ENTRY_PT[24] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7], entry_match[8]}) == 9'b000000001); + assign EX3_FIRST_HIT_ENTRY_PT[25] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6], entry_match[7]}) == 8'b00000001); + assign EX3_FIRST_HIT_ENTRY_PT[26] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5], entry_match[6]}) == 7'b0000001); + assign EX3_FIRST_HIT_ENTRY_PT[27] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4], entry_match[5]}) == 6'b000001); + assign EX3_FIRST_HIT_ENTRY_PT[28] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3], entry_match[4]}) == 5'b00001); + assign EX3_FIRST_HIT_ENTRY_PT[29] = (({entry_match[0], entry_match[1], entry_match[2], entry_match[3]}) == 4'b0001); + assign EX3_FIRST_HIT_ENTRY_PT[30] = (({entry_match[0], entry_match[1], entry_match[2]}) == 3'b001); + assign EX3_FIRST_HIT_ENTRY_PT[31] = (({entry_match[0], entry_match[1]}) == 2'b01); + // Table EX3_FIRST_HIT_ENTRY Signal Assignments for Outputs + assign ex3_first_hit_entry[0] = (EX3_FIRST_HIT_ENTRY_PT[1] | EX3_FIRST_HIT_ENTRY_PT[2] | EX3_FIRST_HIT_ENTRY_PT[3] | EX3_FIRST_HIT_ENTRY_PT[4] | EX3_FIRST_HIT_ENTRY_PT[5] | EX3_FIRST_HIT_ENTRY_PT[6] | EX3_FIRST_HIT_ENTRY_PT[7] | EX3_FIRST_HIT_ENTRY_PT[8] | EX3_FIRST_HIT_ENTRY_PT[9] | EX3_FIRST_HIT_ENTRY_PT[10] | EX3_FIRST_HIT_ENTRY_PT[11] | EX3_FIRST_HIT_ENTRY_PT[12] | EX3_FIRST_HIT_ENTRY_PT[13] | EX3_FIRST_HIT_ENTRY_PT[14] | EX3_FIRST_HIT_ENTRY_PT[15] | EX3_FIRST_HIT_ENTRY_PT[16]); + assign ex3_first_hit_entry[1] = (EX3_FIRST_HIT_ENTRY_PT[1] | EX3_FIRST_HIT_ENTRY_PT[2] | EX3_FIRST_HIT_ENTRY_PT[3] | EX3_FIRST_HIT_ENTRY_PT[4] | EX3_FIRST_HIT_ENTRY_PT[5] | EX3_FIRST_HIT_ENTRY_PT[6] | EX3_FIRST_HIT_ENTRY_PT[7] | EX3_FIRST_HIT_ENTRY_PT[8] | EX3_FIRST_HIT_ENTRY_PT[17] | EX3_FIRST_HIT_ENTRY_PT[18] | EX3_FIRST_HIT_ENTRY_PT[19] | EX3_FIRST_HIT_ENTRY_PT[20] | EX3_FIRST_HIT_ENTRY_PT[21] | EX3_FIRST_HIT_ENTRY_PT[22] | EX3_FIRST_HIT_ENTRY_PT[23] | EX3_FIRST_HIT_ENTRY_PT[24]); + assign ex3_first_hit_entry[2] = (EX3_FIRST_HIT_ENTRY_PT[1] | EX3_FIRST_HIT_ENTRY_PT[2] | EX3_FIRST_HIT_ENTRY_PT[3] | EX3_FIRST_HIT_ENTRY_PT[4] | EX3_FIRST_HIT_ENTRY_PT[9] | EX3_FIRST_HIT_ENTRY_PT[10] | EX3_FIRST_HIT_ENTRY_PT[11] | EX3_FIRST_HIT_ENTRY_PT[12] | EX3_FIRST_HIT_ENTRY_PT[17] | EX3_FIRST_HIT_ENTRY_PT[18] | EX3_FIRST_HIT_ENTRY_PT[19] | EX3_FIRST_HIT_ENTRY_PT[20] | EX3_FIRST_HIT_ENTRY_PT[25] | EX3_FIRST_HIT_ENTRY_PT[26] | EX3_FIRST_HIT_ENTRY_PT[27] | EX3_FIRST_HIT_ENTRY_PT[28]); + assign ex3_first_hit_entry[3] = (EX3_FIRST_HIT_ENTRY_PT[1] | EX3_FIRST_HIT_ENTRY_PT[2] | EX3_FIRST_HIT_ENTRY_PT[5] | EX3_FIRST_HIT_ENTRY_PT[6] | EX3_FIRST_HIT_ENTRY_PT[9] | EX3_FIRST_HIT_ENTRY_PT[10] | EX3_FIRST_HIT_ENTRY_PT[13] | EX3_FIRST_HIT_ENTRY_PT[14] | EX3_FIRST_HIT_ENTRY_PT[17] | EX3_FIRST_HIT_ENTRY_PT[18] | EX3_FIRST_HIT_ENTRY_PT[21] | EX3_FIRST_HIT_ENTRY_PT[22] | EX3_FIRST_HIT_ENTRY_PT[25] | EX3_FIRST_HIT_ENTRY_PT[26] | EX3_FIRST_HIT_ENTRY_PT[29] | EX3_FIRST_HIT_ENTRY_PT[30]); + assign ex3_first_hit_entry[4] = (EX3_FIRST_HIT_ENTRY_PT[1] | EX3_FIRST_HIT_ENTRY_PT[3] | EX3_FIRST_HIT_ENTRY_PT[5] | EX3_FIRST_HIT_ENTRY_PT[7] | EX3_FIRST_HIT_ENTRY_PT[9] | EX3_FIRST_HIT_ENTRY_PT[11] | EX3_FIRST_HIT_ENTRY_PT[13] | EX3_FIRST_HIT_ENTRY_PT[15] | EX3_FIRST_HIT_ENTRY_PT[17] | EX3_FIRST_HIT_ENTRY_PT[19] | EX3_FIRST_HIT_ENTRY_PT[21] | EX3_FIRST_HIT_ENTRY_PT[23] | EX3_FIRST_HIT_ENTRY_PT[25] | EX3_FIRST_HIT_ENTRY_PT[27] | EX3_FIRST_HIT_ENTRY_PT[29] | EX3_FIRST_HIT_ENTRY_PT[31]); + + assign ex4_first_hit_entry_pt_d = EX3_FIRST_HIT_ENTRY_PT; + assign ex4_first_hit_entry[0] = (ex4_first_hit_entry_pt_q[1] | ex4_first_hit_entry_pt_q[2] | ex4_first_hit_entry_pt_q[3] | ex4_first_hit_entry_pt_q[4] | ex4_first_hit_entry_pt_q[5] | ex4_first_hit_entry_pt_q[6] | ex4_first_hit_entry_pt_q[7] | ex4_first_hit_entry_pt_q[8] | ex4_first_hit_entry_pt_q[9] | ex4_first_hit_entry_pt_q[10] | ex4_first_hit_entry_pt_q[11] | ex4_first_hit_entry_pt_q[12] | ex4_first_hit_entry_pt_q[13] | ex4_first_hit_entry_pt_q[14] | ex4_first_hit_entry_pt_q[15] | ex4_first_hit_entry_pt_q[16]); + assign ex4_first_hit_entry[1] = (ex4_first_hit_entry_pt_q[1] | ex4_first_hit_entry_pt_q[2] | ex4_first_hit_entry_pt_q[3] | ex4_first_hit_entry_pt_q[4] | ex4_first_hit_entry_pt_q[5] | ex4_first_hit_entry_pt_q[6] | ex4_first_hit_entry_pt_q[7] | ex4_first_hit_entry_pt_q[8] | ex4_first_hit_entry_pt_q[17] | ex4_first_hit_entry_pt_q[18] | ex4_first_hit_entry_pt_q[19] | ex4_first_hit_entry_pt_q[20] | ex4_first_hit_entry_pt_q[21] | ex4_first_hit_entry_pt_q[22] | ex4_first_hit_entry_pt_q[23] | ex4_first_hit_entry_pt_q[24]); + assign ex4_first_hit_entry[2] = (ex4_first_hit_entry_pt_q[1] | ex4_first_hit_entry_pt_q[2] | ex4_first_hit_entry_pt_q[3] | ex4_first_hit_entry_pt_q[4] | ex4_first_hit_entry_pt_q[9] | ex4_first_hit_entry_pt_q[10] | ex4_first_hit_entry_pt_q[11] | ex4_first_hit_entry_pt_q[12] | ex4_first_hit_entry_pt_q[17] | ex4_first_hit_entry_pt_q[18] | ex4_first_hit_entry_pt_q[19] | ex4_first_hit_entry_pt_q[20] | ex4_first_hit_entry_pt_q[25] | ex4_first_hit_entry_pt_q[26] | ex4_first_hit_entry_pt_q[27] | ex4_first_hit_entry_pt_q[28]); + assign ex4_first_hit_entry[3] = (ex4_first_hit_entry_pt_q[1] | ex4_first_hit_entry_pt_q[2] | ex4_first_hit_entry_pt_q[5] | ex4_first_hit_entry_pt_q[6] | ex4_first_hit_entry_pt_q[9] | ex4_first_hit_entry_pt_q[10] | ex4_first_hit_entry_pt_q[13] | ex4_first_hit_entry_pt_q[14] | ex4_first_hit_entry_pt_q[17] | ex4_first_hit_entry_pt_q[18] | ex4_first_hit_entry_pt_q[21] | ex4_first_hit_entry_pt_q[22] | ex4_first_hit_entry_pt_q[25] | ex4_first_hit_entry_pt_q[26] | ex4_first_hit_entry_pt_q[29] | ex4_first_hit_entry_pt_q[30]); + assign ex4_first_hit_entry[4] = (ex4_first_hit_entry_pt_q[1] | ex4_first_hit_entry_pt_q[3] | ex4_first_hit_entry_pt_q[5] | ex4_first_hit_entry_pt_q[7] | ex4_first_hit_entry_pt_q[9] | ex4_first_hit_entry_pt_q[11] | ex4_first_hit_entry_pt_q[13] | ex4_first_hit_entry_pt_q[15] | ex4_first_hit_entry_pt_q[17] | ex4_first_hit_entry_pt_q[19] | ex4_first_hit_entry_pt_q[21] | ex4_first_hit_entry_pt_q[23] | ex4_first_hit_entry_pt_q[25] | ex4_first_hit_entry_pt_q[27] | ex4_first_hit_entry_pt_q[29] | ex4_first_hit_entry_pt_q[31]); + + // ttype <= 0-eratre 1-eratwe 2-eratsx 3-eratilx 4-load 5-store 6-csync 7-isync 8-icbtlslc 9-touch 10-extload 11-extstore + + assign ex4_miss_d = ((cam_hit == 1'b0 & ex3_ttype_q[4:5] != 2'b00 & ex3_ttype_q[9] == 1'b0 & ccr2_frat_paranoia_q[9] == 1'b0 & ccr2_frat_paranoia_q[11] == 1'b0)) ? (ex3_valid) : + {`THREADS{1'b0}}; + assign ex4_hit_d = ((cam_hit == 1'b1 & ex3_ttype_q[2:5] != 4'b0000)) ? (|(ex3_valid)) : + 1'b0; + assign ex4_eratsx_data = {ex4_multihit_enab, ex4_hit_q, ex4_first_hit_entry}; + + //------------------------------------------------------------------------------ + assign tlb_req_inprogress_d = |(eratm_entry_relPend & (~tlb_rel_val_q[0:`EMQ_ENTRIES - 1])) & (~(ccr2_frat_paranoia_q[9] | (|(por_hold_req)) | spr_ccr2_notlb_q)); + + //ttype: 0-eratre, 1-eratwe, 2-eratsx, 3-eratilx, + // 4-load, 5-store, 6-csync, 7-isync, + // 8-icbtlslc, 9-touch, 10-extload, 11-extstore + + //-- these ex4 versions are for lsu translation sources of parity errors being sent derat -> dcc + assign ex4_parerr_d[0:`THREADS - 1] = (ex3_valid); + + //assign ex4_parerr_d[`THREADS] = (cam_hit & (ex3_ttype_q[4] | ex3_ttype_q[5]) & (~ex3_ttype_q[9]) & (~ccr2_frat_paranoia_q[9])); // term0, load/store either word + assign ex4_parerr_d[`THREADS] = (cam_hit & (ex3_ttype_q[4] | ex3_ttype_q[5]) & (~ccr2_frat_paranoia_q[9])); // term0, load/store either word + + assign ex4_parerr_d[`THREADS + 1] = (cam_hit & ex3_ttype_q[2] & ex3_tlbsel_q[0] & ex3_tlbsel_q[1] & + (~(ex4_deratwe | ex5_deratwe | ex6_deratwe | ex7_deratwe | ex8_deratwe))); // term1, eratsx epn word (and no eratwe in front of it) + + assign ex4_parerr_enab[0] = (ex4_parerr_q[`THREADS] & ~ex4_multihit_enab & (ex4_cmp_data_parerr_epn | ex4_cmp_data_parerr_rpn)); // load/store + assign ex4_parerr_enab[1] = (ex4_parerr_q[`THREADS + 1] & ~ex4_multihit_enab & ex4_cmp_data_parerr_epn); // eratsx + + // This function is controlled by XUCR4.MMU_MCHK and CCR2.NOTLB bits. + assign mchk_flash_inv_d[0] = ex4_parerr_q[`THREADS] & (ex4_cmp_data_parerr_epn | ex4_cmp_data_parerr_rpn); // parerr on load/store (not touch) and cam hit + assign mchk_flash_inv_d[1] = ex4_parerr_q[`THREADS] & ex4_multihit_enab; // multihit on load/store (not touch) and cam hit + assign mchk_flash_inv_d[2] = (mchk_flash_inv_q[0] | mchk_flash_inv_q[1]) & (|(ex5_parerr_q[0:`THREADS - 1] & ~cp_flush_q)); // ex5 phase + assign mchk_flash_inv_d[3] = mchk_flash_inv_enab; // ex6 phase, needed since flash in cyc n results in entry_valid=0 in cyc n+2 + + assign mchk_flash_inv_enab = mchk_flash_inv_q[2] & (~(spr_ccr2_notlb_q)) & (~(xucr4_mmu_mchk_q)); // ex6 phase, parerr/multihit on load/store and tlb mode and mmu_mchk disabled + + //-- these ex5 versions are for ordered erat op sources of parity errors being sent lq -> xu with ordered done handshake + assign ex5_parerr_d[0:`THREADS - 1] = ex4_valid; + assign ex5_parerr_d[`THREADS] = (ex4_ttype_q[0] & (~ex4_ws_q[0]) & (~ex4_ws_q[1]) & ex4_tlbsel_q[0] & ex4_tlbsel_q[1] & + (~(ex5_deratwe | ex6_deratwe | ex7_deratwe))); // eratre, epn ws=0 (and no eratwe in front of it) + assign ex5_parerr_d[`THREADS + 1] = (ex4_ttype_q[0] & (^(ex4_ws_q)) & ex4_tlbsel_q[0] & ex4_tlbsel_q[1] & + (~(ex5_deratwe | ex6_deratwe | ex7_deratwe))); // eratre, rpn ws=1 or 2 (and no eratwe in front of it) + assign ex5_parerr_d[`THREADS + 2] = ex4_rd_data_parerr_epn; + assign ex5_parerr_d[`THREADS + 3] = ex4_rd_data_parerr_rpn; + assign ex5_parerr_d[`THREADS + 4] = ex4_parerr_enab[1]; + + // this is for derat to xu ord op reporting + assign ex5_parerr_enab = (ex5_parerr_q[`THREADS] & ex5_parerr_q[`THREADS + 2]) | // eratre + (ex5_parerr_q[`THREADS + 1] & ex5_parerr_q[`THREADS + 3]) | // eratre + ex5_parerr_q[`THREADS + 4]; // eratsx + + assign lq_xu_ord_par_err = |(ex5_parerr_q[0:`THREADS - 1]) & ex5_parerr_enab; + + //-- these fir versions are catch-all for any source of parity errors + assign ex5_fir_parerr_d[0:`THREADS - 1] = ex4_valid; + assign ex5_fir_parerr_d[`THREADS] = (ex4_ttype_q[0] & (~ex4_ws_q[0]) & (~ex4_ws_q[1]) & ex4_tlbsel_q[0] & ex4_tlbsel_q[1] & + (~(ex5_deratwe | ex6_deratwe | ex7_deratwe))); // eratre, epn ws=0 + assign ex5_fir_parerr_d[`THREADS + 1] = (ex4_ttype_q[0] & (^(ex4_ws_q)) & ex4_tlbsel_q[0] & ex4_tlbsel_q[1] & + (~(ex5_deratwe | ex6_deratwe | ex7_deratwe))); // eratre, rpn ws=1 or 2 + assign ex5_fir_parerr_d[`THREADS + 2] = |(ex4_parerr_enab[0:1]); // load/store, or eratsx + + assign ex5_fir_parerr_enab = (ex5_fir_parerr_q[`THREADS] & ex5_parerr_q[`THREADS + 2]) | // eratre, epn ws=0 + (ex5_fir_parerr_q[`THREADS + 1] & ex5_parerr_q[`THREADS + 3]) | // eratre, rpn ws=1 or 2 + ex5_fir_parerr_q[`THREADS + 2]; // load/store, or eratsx epn + + // ttype <= 0-eratre 1-eratwe 2-eratsx 3-eratilx 4-load 5-store 6-csync 7-isync 8-icbtlslc 9-touch 10-extload 11-extstore + + // ### multihit error generation for translation types (eratsx mhit doesn't generate error, rather gives rt status bit) + assign ex4_multihit_d = ((cam_hit == 1'b1 & ex3_ttype_q[4:5] != 2'b00 & ccr2_frat_paranoia_q[9] == 1'b0)) ? (ex3_valid) : + {`THREADS{1'b0}}; + assign ex5_fir_multihit_d = ((ex4_ttype_q[4:5] != 2'b00 & ex4_multihit_enab == 1'b1)) ? (ex4_multihit_q & ex4_valid) : + {`THREADS{1'b0}}; + assign ex5_deen_d[0:`THREADS - 1] = (((ex4_ttype_q[4] == 1'b1 | ex4_ttype_q[5] == 1'b1) & ex4_multihit_enab == 1'b1)) ? (ex4_multihit_q & ex4_valid) : + {`THREADS{1'b0}}; + assign ex5_deen_d[`THREADS:`THREADS + num_entry_log2 - 1] = (ex4_ttype_q[2] == 1'b1 | ex4_ttype_q[4] == 1'b1 | ex4_ttype_q[5] == 1'b1) ? ex4_eratsx_data[2:2 + num_entry_log2 - 1] : + ((ex4_ttype_q[0] == 1'b1 & (ex4_ws_q == 2'b00 | ex4_ws_q == 2'b01 | ex4_ws_q == 2'b10) & ex4_tlbsel_q == TlbSel_DErat)) ? ex4_ra_entry_q : + {num_entry_log2{1'b0}}; + assign ex5_hit_d = (|(ex4_valid) == 1'b1) ? ex4_hit_q : + 1'b0; + assign ex6_deen_d[0:`THREADS - 1] = (ex5_deen_q[0:`THREADS - 1] & (~(cp_flush_q))) | (ex5_fir_parerr_q[0:`THREADS - 1] & (~(cp_flush_q)) & {`THREADS{ex5_fir_parerr_enab}}); + assign ex6_deen_d[`THREADS:`THREADS + num_entry_log2 - 1] = ex5_deen_q[`THREADS:`THREADS + num_entry_log2 - 1]; + assign ex6_hit_d = (|(ex5_valid & (~(cp_flush_q))) == 1'b1) ? ex5_hit_q : + 1'b0; + + assign ex7_deen_d = {( ex6_deen_q[0:`THREADS - 1] & (~(cp_flush_q)) & {`THREADS{~mchk_flash_inv_enab}} ), ex6_deen_q[`THREADS:`THREADS + num_entry_log2 - 1]}; + assign ex7_hit_d = (|(ex6_valid & (~(cp_flush_q))) == 1'b1) ? ex6_hit_q : + 1'b0; + assign barrier_done_d = ((ex7_ttype_q[0] == 1'b1)) ? ex7_valid : + {`THREADS{1'b0}}; + + // 16x143 version, 42b RA + // wr_array_data + // 0:29 - RPN + // 30:31 - R,C + // 32:35 - ResvAttr + // 36:39 - U0-U3 + // 40:44 - WIMGE + // 45:46 - UX,SX + // 47:48 - UW,SW + // 49:50 - UR,SR + // 51:60 - CAM parity + // 61:67 - Array parity + + // ttype <= 0-eratre 1-eratwe 2-eratsx 3-eratilx 4-load 5-store 6-csync 7-isync 8-icbtlslc 9-touch 10-extload 11-extstore + // state: 0:pr 1:gs 2:ds 3:cm + + // ttype[8] is defined as: (icbtls | icblc) + // ttype[9]=is_touch is defined in lq_dec.v as: (dcbt | dcbtep | dcbtst | dcbtstep | icbt) | + // ((dcbtls | dcbtstls | dcblc) & CT /= 0 or 2) | + // ((icbtls | icblc) & CT /= 0 or 2); + + assign ex3_dsi_d[0] = (ex2_ttype_q[5] & (~ex2_ttype_q[8]) & (~ex2_ttype_q[9]) & ex2_state_q[0] & (~ccr2_frat_paranoia_q[9])); // store, not touch + assign ex3_dsi_d[1] = (ex2_ttype_q[4] & (~ex2_ttype_q[8]) & (~ex2_ttype_q[9]) & ex2_state_q[0] & (~ccr2_frat_paranoia_q[9])); // load, not touch + assign ex3_dsi_d[2] = (ex2_ttype_q[4] & ex2_ttype_q[8] & (~ex2_ttype_q[9]) & ex2_state_q[0] & (~ccr2_frat_paranoia_q[9])); // load, icbtls/icblc, touch=0 means TC=0 or 2 goodness + assign ex3_dsi_d[3] = (ex2_ttype_q[5] & (~ex2_ttype_q[8]) & (~ex2_ttype_q[9]) & (~ex2_state_q[0]) & (~ccr2_frat_paranoia_q[9])); // store, not touch + assign ex3_dsi_d[4] = (ex2_ttype_q[4] & (~ex2_ttype_q[8]) & (~ex2_ttype_q[9]) & (~ex2_state_q[0]) & (~ccr2_frat_paranoia_q[9])); // load, not touch + assign ex3_dsi_d[5] = (ex2_ttype_q[4] & ex2_ttype_q[8] & (~ex2_ttype_q[9]) & (~ex2_state_q[0]) & (~ccr2_frat_paranoia_q[9])); // load, icbtls/icblc, touch=0 means TC=0 or 2 goodness + assign ex3_dsi_d[6] = (ex2_ttype_q[5] & (~ex2_ttype_q[8]) & (~ex2_ttype_q[9]) & mmucr1_q[2] & (~ccr2_frat_paranoia_q[9])); // store (and not touch) with change exception enabled + assign ex3_dsi_d[7] = (ex2_ttype_q[4] & (~ex2_ttype_q[8]) & (~ex2_ttype_q[9]) & mmucr1_q[1] & (~ccr2_frat_paranoia_q[9])); // load (and not touch) with reference exception enabled + assign ex3_dsi_d[8:7 + (2 * `THREADS)] = {ex2_valid, ex2_valid}; + assign ex4_dsi_d[0:7] = ex3_dsi_q[0:7]; + assign ex4_dsi_d[8:7 + (2 * `THREADS)] = ex3_dsi_q[8:7 + 2 * `THREADS] & (~(({cp_flush_q, cp_flush_q}) | ({ex3_strg_noop, ex3_strg_noop}))); + assign ex4_dsi[0] = ex4_dsi_q[0] & (~ex4_array_cmp_data_q[47]); // store, not touch, not user writeable + assign ex4_dsi[1] = ex4_dsi_q[1] & (~ex4_array_cmp_data_q[49]); // load, not touch, not user readable + assign ex4_dsi[2] = ex4_dsi_q[2] & (~ex4_array_cmp_data_q[45]) & (~ex4_array_cmp_data_q[49]); // load, icbtls/icblc, not user readable and not executable; touch=0 means TC=0 or 2 goodness + assign ex4_dsi[3] = ex4_dsi_q[3] & (~ex4_array_cmp_data_q[48]); // store, not touch, not supervisor writeable + assign ex4_dsi[4] = ex4_dsi_q[4] & (~ex4_array_cmp_data_q[50]); // load, not touch, not supervisor readable + assign ex4_dsi[5] = ex4_dsi_q[5] & (~ex4_array_cmp_data_q[46]) & (~ex4_array_cmp_data_q[50]); // load, icbtls/icblc, not supervisor readable and not executable; touch=0 means TC=0 or 2 goodness + assign ex4_dsi[6] = ex4_dsi_q[6] & (~ex4_array_cmp_data_q[31]); // store (and not touch) and C=0 with change exception enabled + assign ex4_dsi[7] = ex4_dsi_q[7] & (~ex4_array_cmp_data_q[30]); // load (and not touch) and R=0 with reference exception enabled + assign ex4_dsi_enab = (|(ex4_dsi)) & (~(|(ex4_miss_q))); + + // ttype <= 0-eratre 1-eratwe 2-eratsx 3-eratilx 4-load 5-store 6-csync 7-isync 8-icbtlslc 9-touch 10-extload 11-extstore + // state: 0:pr 1:gs 2:ds 3:cm + + // ttype[8] is defined as: (icbtls | icblc) + // ttype[9]=is_touch is defined in lq_dec.v as: (dcbt | dcbtep | dcbtst | dcbtstep | icbt) | + // ((dcbtls | dcbtstls | dcblc) & CT /= 0 or 2) | + // ((icbtls | icblc) & CT /= 0 or 2); + // i.e. either it's one of the 5 touch instructions + // (in which case ISA says in event of access or miss exception, no-op the touch and do not generate the interrupt), or + // it's a lock set/clear op with a reserved/bad cache type field CT /= 0 or 2 + // (in which case the instruction is treated as a no-op, and we no-op the it's side-affects here) + + // touch that would have caused exception needs to be no-op + assign ex3_noop_touch_d[0] = ((ex2_ttype_q[4] | ex2_ttype_q[5]) & ex2_ttype_q[9]); + assign ex3_noop_touch_d[1] = ((ex2_ttype_q[4] | ex2_ttype_q[5]) & ex2_ttype_q[9]); + assign ex3_noop_touch_d[2] = ((ex2_ttype_q[4] | ex2_ttype_q[5]) & ex2_ttype_q[9]); + assign ex3_noop_touch_d[3] = (ex2_ttype_q[4] & (~ex2_ttype_q[8]) & ex2_ttype_q[9] & ex2_state_q[0]); // User load, is_touch but not icbtls/lc + assign ex3_noop_touch_d[4] = (ex2_ttype_q[4] & (~ex2_ttype_q[8]) & ex2_ttype_q[9] & (~ex2_state_q[0])); // Sup load, is_touch but not icbtls/lc + assign ex3_noop_touch_d[5] = (ex2_ttype_q[5] & (~ex2_ttype_q[8]) & ex2_ttype_q[9] & ex2_state_q[0]); // User store, is_touch but not icbtls/lc + assign ex3_noop_touch_d[6] = (ex2_ttype_q[5] & (~ex2_ttype_q[8]) & ex2_ttype_q[9] & (~ex2_state_q[0])); // Sup store, is_touch but not icbtls/lc + assign ex3_noop_touch_d[7] = (ex2_ttype_q[4] & ex2_ttype_q[8] & ex2_ttype_q[9]); // Load, icbtls or icbtlc, and CT /= 0 or 2 + assign ex3_noop_touch_d[8:7 + (2 * `THREADS)] = {ex2_valid, ex2_valid}; + assign ex4_noop_touch_d[0] = ex3_noop_touch_q[0] & (~cam_hit); + assign ex4_noop_touch_d[1:7] = ex3_noop_touch_q[1:7]; + assign ex4_noop_touch[3] = ex4_noop_touch_q[3] & (~ex4_array_cmp_data_q[49]); // User load, is_touch, not readable access error + assign ex4_noop_touch[4] = ex4_noop_touch_q[4] & (~ex4_array_cmp_data_q[50]); // Sup load, is_touch, not readable access error + assign ex4_noop_touch[5] = ex4_noop_touch_q[5] & (~ex4_array_cmp_data_q[47]); // User store, is_touch, not writeable access error + assign ex4_noop_touch[6] = ex4_noop_touch_q[6] & (~ex4_array_cmp_data_q[48]); // Sup store, is_touch, not writeable access error + assign ex4_noop_touch[7] = ex4_noop_touch_q[7]; // Load, icbtls or icbtlc, and CT /= 0 or 2 + assign ex4_noop_touch_d[8:7 + (2 * `THREADS)] = ex3_noop_touch_q[8:7 + (2 * `THREADS)] & (~(({cp_flush_q, cp_flush_q}) | ({ex3_strg_noop, ex3_strg_noop}))); + assign ex4_noop_touch_enab = ex4_noop_touch_q[0] | (|(ex4_noop_touch[3:7])); + + // mmucr1_q: 0-DRRE, 1-REE, 2-CEE, 3-csync, 4-isync, 5:6-DPEI, 7:8-DCTID/DTTID, 9-DCCD + //ttype: 0-eratre, 1-eratwe, 2-eratsx, 3-eratilx, + // 4-load, 5-store, 6-csync, 7-isync, + // 8-icbtlslc, 9-touch, 10-extload, 11-extstore + assign ex4_attr_d = array_cmp_data[45:50] | ({6{ccr2_frat_paranoia_q[9]}}); + assign snoop_val_d[0] = (snoop_val_q[0] == 1'b0) ? ex1_snoop_val_q : + ((tlb_rel_val_q[4] == 1'b0 & epsc_wr_q[2 * `THREADS] == 1'b0 & eplc_wr_q[2 * `THREADS] == 1'b0 & snoop_val_q[1] == 1'b1)) ? 1'b0 : + snoop_val_q[0]; + assign snoop_val_d[1] = (~ex1_binv_val_q); + assign snoop_val_d[2] = ((tlb_rel_val_q[4] == 1'b1 | epsc_wr_q[2 * `THREADS] == 1'b1 | eplc_wr_q[2 * `THREADS] == 1'b1 | snoop_val_q[1] == 1'b0)) ? 1'b0 : + snoop_val_q[0]; + assign snoop_attr_d = (snoop_val_q[0] == 1'b0) ? snoopp_attr_q : + snoop_attr_q; + assign snoop_addr_d = (snoop_val_q[0] == 1'b0) ? snoopp_vpn_q : + snoop_addr_q; + assign lq_mm_snoop_ack = snoop_val_q[2]; + + generate begin : rpnTid + genvar tid; + for (tid = 0; tid <= `THREADS - 1; tid = tid + 1) begin : rpnTid + if (GPR_WIDTH == 64) begin : gen64_holdreg + assign rpn_holdreg_d[tid][0:19] = ((ex2_valid_op_q[tid] == 1'b1 & ex2_ttype_q[1] == 1'b1 & ex2_ws_q == 2'b01 & ex2_tlbsel_q == TlbSel_DErat & ex2_state_q[3] == 1'b1)) ? ex2_data_in_q[0:19] : + ((ex2_valid_op_q[tid] == 1'b1 & ex2_ttype_q[1] == 1'b1 & ex2_ws_q == 2'b10 & ex2_tlbsel_q == TlbSel_DErat & ex2_state_q[3] == 1'b0)) ? ex2_data_in_q[32:51] : + rpn_holdreg_q[tid][0:19]; + assign rpn_holdreg_d[tid][20:31] = ((ex2_valid_op_q[tid] == 1'b1 & ex2_ttype_q[1] == 1'b1 & ex2_ws_q == 2'b01 & ex2_tlbsel_q == TlbSel_DErat & ex2_state_q[3] == 1'b1)) ? ex2_data_in_q[20:31] : + ((ex2_valid_op_q[tid] == 1'b1 & ex2_ttype_q[1] == 1'b1 & ex2_ws_q == 2'b01 & ex2_tlbsel_q == TlbSel_DErat & ex2_state_q[3] == 1'b0)) ? ex2_data_in_q[52:63] : + rpn_holdreg_q[tid][20:31]; + assign rpn_holdreg_d[tid][32:51] = ((ex2_valid_op_q[tid] == 1'b1 & ex2_ttype_q[1] == 1'b1 & ex2_ws_q == 2'b01 & ex2_tlbsel_q == TlbSel_DErat & ex2_state_q[3] == 1'b1)) ? ex2_data_in_q[32:51] : + ((ex2_valid_op_q[tid] == 1'b1 & ex2_ttype_q[1] == 1'b1 & ex2_ws_q == 2'b01 & ex2_tlbsel_q == TlbSel_DErat & ex2_state_q[3] == 1'b0)) ? ex2_data_in_q[32:51] : + rpn_holdreg_q[tid][32:51]; + assign rpn_holdreg_d[tid][52:63] = ((ex2_valid_op_q[tid] == 1'b1 & ex2_ttype_q[1] == 1'b1 & ex2_ws_q == 2'b01 & ex2_tlbsel_q == TlbSel_DErat & ex2_state_q[3] == 1'b1)) ? ex2_data_in_q[52:63] : + ((ex2_valid_op_q[tid] == 1'b1 & ex2_ttype_q[1] == 1'b1 & ex2_ws_q == 2'b10 & ex2_tlbsel_q == TlbSel_DErat & ex2_state_q[3] == 1'b0)) ? ex2_data_in_q[52:63] : + rpn_holdreg_q[tid][52:63]; + end + if (GPR_WIDTH == 32) begin : gen32_holdreg + assign rpn_holdreg_d[tid][32:51] = ((ex2_valid_op_q[tid] == 1'b1 & ex2_ttype_q[1] == 1'b1 & ex2_ws_q == 2'b01 & ex2_tlbsel_q == TlbSel_DErat)) ? ex2_data_in_q[32:51] : + rpn_holdreg_q[tid][32:51]; + assign rpn_holdreg_d[tid][20:31] = ((ex2_valid_op_q[tid] == 1'b1 & ex2_ttype_q[1] == 1'b1 & ex2_ws_q == 2'b01 & ex2_tlbsel_q == TlbSel_DErat)) ? ex2_data_in_q[52:63] : + rpn_holdreg_q[tid][20:31]; + assign rpn_holdreg_d[tid][52:63] = ((ex2_valid_op_q[tid] == 1'b1 & ex2_ttype_q[1] == 1'b1 & ex2_ws_q == 2'b10 & ex2_tlbsel_q == TlbSel_DErat)) ? ex2_data_in_q[52:63] : + rpn_holdreg_q[tid][52:63]; + assign rpn_holdreg_d[tid][0:19] = ((ex2_valid_op_q[tid] == 1'b1 & ex2_ttype_q[1] == 1'b1 & ex2_ws_q == 2'b10 & ex2_tlbsel_q == TlbSel_DErat)) ? ex2_data_in_q[32:51] : + rpn_holdreg_q[tid][0:19]; + end + end + end + endgenerate + + assign ex2_deratwe_ws3 = (|(ex2_valid_op_q)) & ex2_ttype_q[1] & (ex2_ws_q == 2'b11) & (ex2_tlbsel_q == TlbSel_DErat); + assign watermark_d = (ex2_deratwe_ws3 == 1'b1) ? ex2_data_in_q[64 - watermark_width:63] : + watermark_q; + + // entry pointer for round-robin mode + assign eptr_d = ((ex2_deratwe_ws3 == 1'b1 | csinv_complete == 1'b1) & mmucr1_q[0] == 1'b1) ? {eptr_width{1'b0}} : + (eptr_q == 5'b11111 & ((|(ex2_valid_op_q) == 1'b1 & ex2_ttype_q[1] == 1'b1 & ex2_ws_q == 2'b00 & ex2_tlbsel_q == TlbSel_DErat & mmucr1_q[0] == 1'b1) | (tlb_rel_val_q[0:3] != 4'b0000 & tlb_rel_val_q[4] == 1'b1 & tlb_rel_data_q[eratpos_wren] == 1'b1 & mmucr1_q[0] == 1'b1))) ? {eptr_width{1'b0}} : + (eptr_q == watermark_q & ((|(ex2_valid_op_q) == 1'b1 & ex2_ttype_q[1] == 1'b1 & ex2_ws_q == 2'b00 & ex2_tlbsel_q == TlbSel_DErat & mmucr1_q[0] == 1'b1) | (tlb_rel_val_q[0:3] != 4'b0000 & tlb_rel_val_q[4] == 1'b1 & tlb_rel_data_q[eratpos_wren] == 1'b1 & mmucr1_q[0] == 1'b1))) ? {eptr_width{1'b0}} : + (((|(ex2_valid_op_q) == 1'b1 & ex2_ttype_q[1] == 1'b1 & ex2_ws_q == 2'b00 & ex2_tlbsel_q == TlbSel_DErat & mmucr1_q[0] == 1'b1) | (tlb_rel_val_q[0:3] != 4'b0000 & tlb_rel_val_q[4] == 1'b1 & tlb_rel_data_q[eratpos_wren] == 1'b1 & mmucr1_q[0] == 1'b1))) ? eptr_p1 : + eptr_q; + assign eptr_p1 = (eptr_q == 5'b00000) ? 5'b00001 : + (eptr_q == 5'b00001) ? 5'b00010 : + (eptr_q == 5'b00010) ? 5'b00011 : + (eptr_q == 5'b00011) ? 5'b00100 : + (eptr_q == 5'b00100) ? 5'b00101 : + (eptr_q == 5'b00101) ? 5'b00110 : + (eptr_q == 5'b00110) ? 5'b00111 : + (eptr_q == 5'b00111) ? 5'b01000 : + (eptr_q == 5'b01000) ? 5'b01001 : + (eptr_q == 5'b01001) ? 5'b01010 : + (eptr_q == 5'b01010) ? 5'b01011 : + (eptr_q == 5'b01011) ? 5'b01100 : + (eptr_q == 5'b01100) ? 5'b01101 : + (eptr_q == 5'b01101) ? 5'b01110 : + (eptr_q == 5'b01110) ? 5'b01111 : + (eptr_q == 5'b01111) ? 5'b10000 : + (eptr_q == 5'b10000) ? 5'b10001 : + (eptr_q == 5'b10001) ? 5'b10010 : + (eptr_q == 5'b10010) ? 5'b10011 : + (eptr_q == 5'b10011) ? 5'b10100 : + (eptr_q == 5'b10100) ? 5'b10101 : + (eptr_q == 5'b10101) ? 5'b10110 : + (eptr_q == 5'b10110) ? 5'b10111 : + (eptr_q == 5'b10111) ? 5'b11000 : + (eptr_q == 5'b11000) ? 5'b11001 : + (eptr_q == 5'b11001) ? 5'b11010 : + (eptr_q == 5'b11010) ? 5'b11011 : + (eptr_q == 5'b11011) ? 5'b11100 : + (eptr_q == 5'b11100) ? 5'b11101 : + (eptr_q == 5'b11101) ? 5'b11110 : + (eptr_q == 5'b11110) ? 5'b11111 : + 5'b00000; + generate begin : epn_mask + genvar i; + for (i = (64 - (2 ** `GPR_WIDTH_ENC)); i <= 51; i = i + 1) begin : epn_mask + if (i < 32) begin : R0 + assign ex3_epn_d[i] = (ex2_state_q[3] & dir_derat_ex2_epn_nonarr[i]); + end + if (i >= 32) begin : R1 + assign ex3_epn_d[i] = dir_derat_ex2_epn_nonarr[i]; + end + end + end + endgenerate + + // lru_update_event + // 0: tlb reload + // 1: invalidate snoop + // 2: csync or isync enabled + // 3: eratwe WS=0 + // 4: load or store hit + // 5: ex4 cam write type events + // 6: ex4 cam invalidate type events + // 7: ex4 cam translation type events + // 8: superset, ex3 + // 9: superset, delayed to ex4 + assign lru_update_event_d[0] = (tlb_rel_data_q[eratpos_wren] & (|(tlb_rel_val_q[0:3])) & tlb_rel_val_q[4]); + assign lru_update_event_d[1] = (snoop_val_q[0] & snoop_val_q[1]); + assign lru_update_event_d[2] = csinv_complete; + assign lru_update_event_d[3] = (|(ex2_valid_op_q) & ex2_ttype_q[1] & (ex2_ws_q == 2'b00) & (ex2_tlbsel_q == TlbSel_DErat) & (lru_way_encode == ex2_ra_entry_q)); + assign lru_update_event_d[4] = (|(ex2_valid) & |(ex2_ttype_q[4:5])); + assign lru_update_event_d[5] = lru_update_event_q[0] | lru_update_event_q[3]; + assign lru_update_event_d[6] = lru_update_event_q[1] | lru_update_event_q[2]; + assign lru_update_event_d[7] = lru_update_event_q[4] & cam_hit; + assign lru_update_event_d[8] = (tlb_rel_data_q[eratpos_wren] & (|(tlb_rel_val_q[0:3])) & tlb_rel_val_q[4]) | (snoop_val_q[0] & snoop_val_q[1]) | (csinv_complete) | (|(ex2_valid_op_q) & ex2_ttype_q[1] & (ex2_ws_q == 2'b00) & (ex2_tlbsel_q == TlbSel_DErat) & (lru_way_encode == ex2_ra_entry_q)); + assign lru_update_event_d[9] = lru_update_event_q[8] | (lru_update_event_q[4] & cam_hit); + //?generate begin n(1 to 31); + //lru_d() <= '1' when lru_set_vec()='1' and lru_op_vec()='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + // else '0' when lru_reset_vec()='1' and lru_op_vec()='0' and lru_update_event_q(9)='1' and mmucr1_q(0)='0' + // else lru_q(); + //lru_eff() <= (lru_vp_vec() and lru_op_vec()) or (lru_q() and not lru_op_vec()); + //?generate end; + assign lru_d[1] = (((ex2_deratwe_ws3 == 1'b1 & mmucr1_q[0] == 1'b0) | flash_invalidate == 1'b1)) ? 1'b0 : + (lru_reset_vec[1] == 1'b1 & lru_op_vec[1] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b0 : + (lru_set_vec[1] == 1'b1 & lru_op_vec[1] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b1 : + lru_q[1]; + assign lru_eff[1] = (lru_vp_vec[1] & lru_op_vec[1]) | (lru_q[1] & (~lru_op_vec[1])); + assign lru_d[2] = (((ex2_deratwe_ws3 == 1'b1 & mmucr1_q[0] == 1'b0) | flash_invalidate == 1'b1)) ? 1'b0 : + (lru_reset_vec[2] == 1'b1 & lru_op_vec[2] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b0 : + (lru_set_vec[2] == 1'b1 & lru_op_vec[2] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b1 : + lru_q[2]; + assign lru_eff[2] = (lru_vp_vec[2] & lru_op_vec[2]) | (lru_q[2] & (~lru_op_vec[2])); + assign lru_d[3] = (((ex2_deratwe_ws3 == 1'b1 & mmucr1_q[0] == 1'b0) | flash_invalidate == 1'b1)) ? 1'b0 : + (lru_reset_vec[3] == 1'b1 & lru_op_vec[3] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b0 : + (lru_set_vec[3] == 1'b1 & lru_op_vec[3] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b1 : + lru_q[3]; + assign lru_eff[3] = (lru_vp_vec[3] & lru_op_vec[3]) | (lru_q[3] & (~lru_op_vec[3])); + assign lru_d[4] = (((ex2_deratwe_ws3 == 1'b1 & mmucr1_q[0] == 1'b0) | flash_invalidate == 1'b1)) ? 1'b0 : + (lru_reset_vec[4] == 1'b1 & lru_op_vec[4] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b0 : + (lru_set_vec[4] == 1'b1 & lru_op_vec[4] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b1 : + lru_q[4]; + assign lru_eff[4] = (lru_vp_vec[4] & lru_op_vec[4]) | (lru_q[4] & (~lru_op_vec[4])); + assign lru_d[5] = (((ex2_deratwe_ws3 == 1'b1 & mmucr1_q[0] == 1'b0) | flash_invalidate == 1'b1)) ? 1'b0 : + (lru_reset_vec[5] == 1'b1 & lru_op_vec[5] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b0 : + (lru_set_vec[5] == 1'b1 & lru_op_vec[5] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b1 : + lru_q[5]; + assign lru_eff[5] = (lru_vp_vec[5] & lru_op_vec[5]) | (lru_q[5] & (~lru_op_vec[5])); + assign lru_d[6] = (((ex2_deratwe_ws3 == 1'b1 & mmucr1_q[0] == 1'b0) | flash_invalidate == 1'b1)) ? 1'b0 : + (lru_reset_vec[6] == 1'b1 & lru_op_vec[6] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b0 : + (lru_set_vec[6] == 1'b1 & lru_op_vec[6] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b1 : + lru_q[6]; + assign lru_eff[6] = (lru_vp_vec[6] & lru_op_vec[6]) | (lru_q[6] & (~lru_op_vec[6])); + assign lru_d[7] = (((ex2_deratwe_ws3 == 1'b1 & mmucr1_q[0] == 1'b0) | flash_invalidate == 1'b1)) ? 1'b0 : + (lru_reset_vec[7] == 1'b1 & lru_op_vec[7] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b0 : + (lru_set_vec[7] == 1'b1 & lru_op_vec[7] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b1 : + lru_q[7]; + assign lru_eff[7] = (lru_vp_vec[7] & lru_op_vec[7]) | (lru_q[7] & (~lru_op_vec[7])); + assign lru_d[8] = (((ex2_deratwe_ws3 == 1'b1 & mmucr1_q[0] == 1'b0) | flash_invalidate == 1'b1)) ? 1'b0 : + (lru_reset_vec[8] == 1'b1 & lru_op_vec[8] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b0 : + (lru_set_vec[8] == 1'b1 & lru_op_vec[8] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b1 : + lru_q[8]; + assign lru_eff[8] = (lru_vp_vec[8] & lru_op_vec[8]) | (lru_q[8] & (~lru_op_vec[8])); + assign lru_d[9] = (((ex2_deratwe_ws3 == 1'b1 & mmucr1_q[0] == 1'b0) | flash_invalidate == 1'b1)) ? 1'b0 : + (lru_reset_vec[9] == 1'b1 & lru_op_vec[9] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b0 : + (lru_set_vec[9] == 1'b1 & lru_op_vec[9] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b1 : + lru_q[9]; + assign lru_eff[9] = (lru_vp_vec[9] & lru_op_vec[9]) | (lru_q[9] & (~lru_op_vec[9])); + assign lru_d[10] = (((ex2_deratwe_ws3 == 1'b1 & mmucr1_q[0] == 1'b0) | flash_invalidate == 1'b1)) ? 1'b0 : + (lru_reset_vec[10] == 1'b1 & lru_op_vec[10] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b0 : + (lru_set_vec[10] == 1'b1 & lru_op_vec[10] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b1 : + lru_q[10]; + assign lru_eff[10] = (lru_vp_vec[10] & lru_op_vec[10]) | (lru_q[10] & (~lru_op_vec[10])); + assign lru_d[11] = (((ex2_deratwe_ws3 == 1'b1 & mmucr1_q[0] == 1'b0) | flash_invalidate == 1'b1)) ? 1'b0 : + (lru_reset_vec[11] == 1'b1 & lru_op_vec[11] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b0 : + (lru_set_vec[11] == 1'b1 & lru_op_vec[11] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b1 : + lru_q[11]; + assign lru_eff[11] = (lru_vp_vec[11] & lru_op_vec[11]) | (lru_q[11] & (~lru_op_vec[11])); + assign lru_d[12] = (((ex2_deratwe_ws3 == 1'b1 & mmucr1_q[0] == 1'b0) | flash_invalidate == 1'b1)) ? 1'b0 : + (lru_reset_vec[12] == 1'b1 & lru_op_vec[12] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b0 : + (lru_set_vec[12] == 1'b1 & lru_op_vec[12] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b1 : + lru_q[12]; + assign lru_eff[12] = (lru_vp_vec[12] & lru_op_vec[12]) | (lru_q[12] & (~lru_op_vec[12])); + assign lru_d[13] = (((ex2_deratwe_ws3 == 1'b1 & mmucr1_q[0] == 1'b0) | flash_invalidate == 1'b1)) ? 1'b0 : + (lru_reset_vec[13] == 1'b1 & lru_op_vec[13] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b0 : + (lru_set_vec[13] == 1'b1 & lru_op_vec[13] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b1 : + lru_q[13]; + assign lru_eff[13] = (lru_vp_vec[13] & lru_op_vec[13]) | (lru_q[13] & (~lru_op_vec[13])); + assign lru_d[14] = (((ex2_deratwe_ws3 == 1'b1 & mmucr1_q[0] == 1'b0) | flash_invalidate == 1'b1)) ? 1'b0 : + (lru_reset_vec[14] == 1'b1 & lru_op_vec[14] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b0 : + (lru_set_vec[14] == 1'b1 & lru_op_vec[14] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b1 : + lru_q[14]; + assign lru_eff[14] = (lru_vp_vec[14] & lru_op_vec[14]) | (lru_q[14] & (~lru_op_vec[14])); + assign lru_d[15] = (((ex2_deratwe_ws3 == 1'b1 & mmucr1_q[0] == 1'b0) | flash_invalidate == 1'b1)) ? 1'b0 : + (lru_reset_vec[15] == 1'b1 & lru_op_vec[15] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b0 : + (lru_set_vec[15] == 1'b1 & lru_op_vec[15] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b1 : + lru_q[15]; + assign lru_eff[15] = (lru_vp_vec[15] & lru_op_vec[15]) | (lru_q[15] & (~lru_op_vec[15])); + assign lru_d[16] = (((ex2_deratwe_ws3 == 1'b1 & mmucr1_q[0] == 1'b0) | flash_invalidate == 1'b1)) ? 1'b0 : + (lru_reset_vec[16] == 1'b1 & lru_op_vec[16] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b0 : + (lru_set_vec[16] == 1'b1 & lru_op_vec[16] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b1 : + lru_q[16]; + assign lru_eff[16] = (lru_vp_vec[16] & lru_op_vec[16]) | (lru_q[16] & (~lru_op_vec[16])); + assign lru_d[17] = (((ex2_deratwe_ws3 == 1'b1 & mmucr1_q[0] == 1'b0) | flash_invalidate == 1'b1)) ? 1'b0 : + (lru_reset_vec[17] == 1'b1 & lru_op_vec[17] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b0 : + (lru_set_vec[17] == 1'b1 & lru_op_vec[17] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b1 : + lru_q[17]; + assign lru_eff[17] = (lru_vp_vec[17] & lru_op_vec[17]) | (lru_q[17] & (~lru_op_vec[17])); + assign lru_d[18] = (((ex2_deratwe_ws3 == 1'b1 & mmucr1_q[0] == 1'b0) | flash_invalidate == 1'b1)) ? 1'b0 : + (lru_reset_vec[18] == 1'b1 & lru_op_vec[18] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b0 : + (lru_set_vec[18] == 1'b1 & lru_op_vec[18] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b1 : + lru_q[18]; + assign lru_eff[18] = (lru_vp_vec[18] & lru_op_vec[18]) | (lru_q[18] & (~lru_op_vec[18])); + assign lru_d[19] = (((ex2_deratwe_ws3 == 1'b1 & mmucr1_q[0] == 1'b0) | flash_invalidate == 1'b1)) ? 1'b0 : + (lru_reset_vec[19] == 1'b1 & lru_op_vec[19] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b0 : + (lru_set_vec[19] == 1'b1 & lru_op_vec[19] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b1 : + lru_q[19]; + assign lru_eff[19] = (lru_vp_vec[19] & lru_op_vec[19]) | (lru_q[19] & (~lru_op_vec[19])); + assign lru_d[20] = (((ex2_deratwe_ws3 == 1'b1 & mmucr1_q[0] == 1'b0) | flash_invalidate == 1'b1)) ? 1'b0 : + (lru_reset_vec[20] == 1'b1 & lru_op_vec[20] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b0 : + (lru_set_vec[20] == 1'b1 & lru_op_vec[20] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b1 : + lru_q[20]; + assign lru_eff[20] = (lru_vp_vec[20] & lru_op_vec[20]) | (lru_q[20] & (~lru_op_vec[20])); + assign lru_d[21] = (((ex2_deratwe_ws3 == 1'b1 & mmucr1_q[0] == 1'b0) | flash_invalidate == 1'b1)) ? 1'b0 : + (lru_reset_vec[21] == 1'b1 & lru_op_vec[21] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b0 : + (lru_set_vec[21] == 1'b1 & lru_op_vec[21] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b1 : + lru_q[21]; + assign lru_eff[21] = (lru_vp_vec[21] & lru_op_vec[21]) | (lru_q[21] & (~lru_op_vec[21])); + assign lru_d[22] = (((ex2_deratwe_ws3 == 1'b1 & mmucr1_q[0] == 1'b0) | flash_invalidate == 1'b1)) ? 1'b0 : + (lru_reset_vec[22] == 1'b1 & lru_op_vec[22] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b0 : + (lru_set_vec[22] == 1'b1 & lru_op_vec[22] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b1 : + lru_q[22]; + assign lru_eff[22] = (lru_vp_vec[22] & lru_op_vec[22]) | (lru_q[22] & (~lru_op_vec[22])); + assign lru_d[23] = (((ex2_deratwe_ws3 == 1'b1 & mmucr1_q[0] == 1'b0) | flash_invalidate == 1'b1)) ? 1'b0 : + (lru_reset_vec[23] == 1'b1 & lru_op_vec[23] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b0 : + (lru_set_vec[23] == 1'b1 & lru_op_vec[23] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b1 : + lru_q[23]; + assign lru_eff[23] = (lru_vp_vec[23] & lru_op_vec[23]) | (lru_q[23] & (~lru_op_vec[23])); + assign lru_d[24] = (((ex2_deratwe_ws3 == 1'b1 & mmucr1_q[0] == 1'b0) | flash_invalidate == 1'b1)) ? 1'b0 : + (lru_reset_vec[24] == 1'b1 & lru_op_vec[24] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b0 : + (lru_set_vec[24] == 1'b1 & lru_op_vec[24] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b1 : + lru_q[24]; + assign lru_eff[24] = (lru_vp_vec[24] & lru_op_vec[24]) | (lru_q[24] & (~lru_op_vec[24])); + assign lru_d[25] = (((ex2_deratwe_ws3 == 1'b1 & mmucr1_q[0] == 1'b0) | flash_invalidate == 1'b1)) ? 1'b0 : + (lru_reset_vec[25] == 1'b1 & lru_op_vec[25] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b0 : + (lru_set_vec[25] == 1'b1 & lru_op_vec[25] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b1 : + lru_q[25]; + assign lru_eff[25] = (lru_vp_vec[25] & lru_op_vec[25]) | (lru_q[25] & (~lru_op_vec[25])); + assign lru_d[26] = (((ex2_deratwe_ws3 == 1'b1 & mmucr1_q[0] == 1'b0) | flash_invalidate == 1'b1)) ? 1'b0 : + (lru_reset_vec[26] == 1'b1 & lru_op_vec[26] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b0 : + (lru_set_vec[26] == 1'b1 & lru_op_vec[26] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b1 : + lru_q[26]; + assign lru_eff[26] = (lru_vp_vec[26] & lru_op_vec[26]) | (lru_q[26] & (~lru_op_vec[26])); + assign lru_d[27] = (((ex2_deratwe_ws3 == 1'b1 & mmucr1_q[0] == 1'b0) | flash_invalidate == 1'b1)) ? 1'b0 : + (lru_reset_vec[27] == 1'b1 & lru_op_vec[27] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b0 : + (lru_set_vec[27] == 1'b1 & lru_op_vec[27] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b1 : + lru_q[27]; + assign lru_eff[27] = (lru_vp_vec[27] & lru_op_vec[27]) | (lru_q[27] & (~lru_op_vec[27])); + assign lru_d[28] = (((ex2_deratwe_ws3 == 1'b1 & mmucr1_q[0] == 1'b0) | flash_invalidate == 1'b1)) ? 1'b0 : + (lru_reset_vec[28] == 1'b1 & lru_op_vec[28] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b0 : + (lru_set_vec[28] == 1'b1 & lru_op_vec[28] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b1 : + lru_q[28]; + assign lru_eff[28] = (lru_vp_vec[28] & lru_op_vec[28]) | (lru_q[28] & (~lru_op_vec[28])); + assign lru_d[29] = (((ex2_deratwe_ws3 == 1'b1 & mmucr1_q[0] == 1'b0) | flash_invalidate == 1'b1)) ? 1'b0 : + (lru_reset_vec[29] == 1'b1 & lru_op_vec[29] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b0 : + (lru_set_vec[29] == 1'b1 & lru_op_vec[29] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b1 : + lru_q[29]; + assign lru_eff[29] = (lru_vp_vec[29] & lru_op_vec[29]) | (lru_q[29] & (~lru_op_vec[29])); + assign lru_d[30] = (((ex2_deratwe_ws3 == 1'b1 & mmucr1_q[0] == 1'b0) | flash_invalidate == 1'b1)) ? 1'b0 : + (lru_reset_vec[30] == 1'b1 & lru_op_vec[30] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b0 : + (lru_set_vec[30] == 1'b1 & lru_op_vec[30] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b1 : + lru_q[30]; + assign lru_eff[30] = (lru_vp_vec[30] & lru_op_vec[30]) | (lru_q[30] & (~lru_op_vec[30])); + assign lru_d[31] = (((ex2_deratwe_ws3 == 1'b1 & mmucr1_q[0] == 1'b0) | flash_invalidate == 1'b1)) ? 1'b0 : + (lru_reset_vec[31] == 1'b1 & lru_op_vec[31] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b0 : + (lru_set_vec[31] == 1'b1 & lru_op_vec[31] == 1'b0 & lru_update_event_q[9] == 1'b1 & mmucr1_q[0] == 1'b0) ? 1'b1 : + lru_q[31]; + assign lru_eff[31] = (lru_vp_vec[31] & lru_op_vec[31]) | (lru_q[31] & (~lru_op_vec[31])); + // RMT override enable: Op= OR(all RMT entries below and left of p) XOR OR(all RMT entries below and right of p) + assign lru_op_vec[1] = (lru_rmt_vec[0] | lru_rmt_vec[1] | lru_rmt_vec[2] | lru_rmt_vec[3] | lru_rmt_vec[4] | lru_rmt_vec[5] | lru_rmt_vec[6] | lru_rmt_vec[7] | lru_rmt_vec[8] | lru_rmt_vec[9] | lru_rmt_vec[10] | lru_rmt_vec[11] | lru_rmt_vec[12] | lru_rmt_vec[13] | lru_rmt_vec[14] | lru_rmt_vec[15]) ^ (lru_rmt_vec[16] | lru_rmt_vec[17] | lru_rmt_vec[18] | lru_rmt_vec[19] | lru_rmt_vec[20] | lru_rmt_vec[21] | lru_rmt_vec[22] | lru_rmt_vec[23] | lru_rmt_vec[24] | lru_rmt_vec[25] | lru_rmt_vec[26] | lru_rmt_vec[27] | lru_rmt_vec[28] | lru_rmt_vec[29] | lru_rmt_vec[30] | lru_rmt_vec[31]); + assign lru_op_vec[2] = (lru_rmt_vec[0] | lru_rmt_vec[1] | lru_rmt_vec[2] | lru_rmt_vec[3] | lru_rmt_vec[4] | lru_rmt_vec[5] | lru_rmt_vec[6] | lru_rmt_vec[7]) ^ (lru_rmt_vec[8] | lru_rmt_vec[9] | lru_rmt_vec[10] | lru_rmt_vec[11] | lru_rmt_vec[12] | lru_rmt_vec[13] | lru_rmt_vec[14] | lru_rmt_vec[15]); + assign lru_op_vec[3] = (lru_rmt_vec[16] | lru_rmt_vec[17] | lru_rmt_vec[18] | lru_rmt_vec[19] | lru_rmt_vec[20] | lru_rmt_vec[21] | lru_rmt_vec[22] | lru_rmt_vec[23]) ^ (lru_rmt_vec[24] | lru_rmt_vec[25] | lru_rmt_vec[26] | lru_rmt_vec[27] | lru_rmt_vec[28] | lru_rmt_vec[29] | lru_rmt_vec[30] | lru_rmt_vec[31]); + assign lru_op_vec[4] = (lru_rmt_vec[0] | lru_rmt_vec[1] | lru_rmt_vec[2] | lru_rmt_vec[3]) ^ (lru_rmt_vec[4] | lru_rmt_vec[5] | lru_rmt_vec[6] | lru_rmt_vec[7]); + assign lru_op_vec[5] = (lru_rmt_vec[8] | lru_rmt_vec[9] | lru_rmt_vec[10] | lru_rmt_vec[11]) ^ (lru_rmt_vec[12] | lru_rmt_vec[13] | lru_rmt_vec[14] | lru_rmt_vec[15]); + assign lru_op_vec[6] = (lru_rmt_vec[16] | lru_rmt_vec[17] | lru_rmt_vec[18] | lru_rmt_vec[19]) ^ (lru_rmt_vec[20] | lru_rmt_vec[21] | lru_rmt_vec[22] | lru_rmt_vec[23]); + assign lru_op_vec[7] = (lru_rmt_vec[24] | lru_rmt_vec[25] | lru_rmt_vec[26] | lru_rmt_vec[27]) ^ (lru_rmt_vec[28] | lru_rmt_vec[29] | lru_rmt_vec[30] | lru_rmt_vec[31]); + assign lru_op_vec[8] = (lru_rmt_vec[0] | lru_rmt_vec[1]) ^ (lru_rmt_vec[2] | lru_rmt_vec[3]); + assign lru_op_vec[9] = (lru_rmt_vec[4] | lru_rmt_vec[5]) ^ (lru_rmt_vec[6] | lru_rmt_vec[7]); + assign lru_op_vec[10] = (lru_rmt_vec[8] | lru_rmt_vec[9]) ^ (lru_rmt_vec[10] | lru_rmt_vec[11]); + assign lru_op_vec[11] = (lru_rmt_vec[12] | lru_rmt_vec[13]) ^ (lru_rmt_vec[14] | lru_rmt_vec[15]); + assign lru_op_vec[12] = (lru_rmt_vec[16] | lru_rmt_vec[17]) ^ (lru_rmt_vec[18] | lru_rmt_vec[19]); + assign lru_op_vec[13] = (lru_rmt_vec[20] | lru_rmt_vec[21]) ^ (lru_rmt_vec[22] | lru_rmt_vec[23]); + assign lru_op_vec[14] = (lru_rmt_vec[24] | lru_rmt_vec[25]) ^ (lru_rmt_vec[26] | lru_rmt_vec[27]); + assign lru_op_vec[15] = (lru_rmt_vec[28] | lru_rmt_vec[29]) ^ (lru_rmt_vec[30] | lru_rmt_vec[31]); + assign lru_op_vec[16] = lru_rmt_vec[0] ^ lru_rmt_vec[1]; + assign lru_op_vec[17] = lru_rmt_vec[2] ^ lru_rmt_vec[3]; + assign lru_op_vec[18] = lru_rmt_vec[4] ^ lru_rmt_vec[5]; + assign lru_op_vec[19] = lru_rmt_vec[6] ^ lru_rmt_vec[7]; + assign lru_op_vec[20] = lru_rmt_vec[8] ^ lru_rmt_vec[9]; + assign lru_op_vec[21] = lru_rmt_vec[10] ^ lru_rmt_vec[11]; + assign lru_op_vec[22] = lru_rmt_vec[12] ^ lru_rmt_vec[13]; + assign lru_op_vec[23] = lru_rmt_vec[14] ^ lru_rmt_vec[15]; + assign lru_op_vec[24] = lru_rmt_vec[16] ^ lru_rmt_vec[17]; + assign lru_op_vec[25] = lru_rmt_vec[18] ^ lru_rmt_vec[19]; + assign lru_op_vec[26] = lru_rmt_vec[20] ^ lru_rmt_vec[21]; + assign lru_op_vec[27] = lru_rmt_vec[22] ^ lru_rmt_vec[23]; + assign lru_op_vec[28] = lru_rmt_vec[24] ^ lru_rmt_vec[25]; + assign lru_op_vec[29] = lru_rmt_vec[26] ^ lru_rmt_vec[27]; + assign lru_op_vec[30] = lru_rmt_vec[28] ^ lru_rmt_vec[29]; + assign lru_op_vec[31] = lru_rmt_vec[30] ^ lru_rmt_vec[31]; + // RMT override value: Vp= OR(all RMT entries below and right of p) + assign lru_vp_vec[1] = (lru_rmt_vec[16] | lru_rmt_vec[17] | lru_rmt_vec[18] | lru_rmt_vec[19] | lru_rmt_vec[20] | lru_rmt_vec[21] | lru_rmt_vec[22] | lru_rmt_vec[23] | lru_rmt_vec[24] | lru_rmt_vec[25] | lru_rmt_vec[26] | lru_rmt_vec[27] | lru_rmt_vec[28] | lru_rmt_vec[29] | lru_rmt_vec[30] | lru_rmt_vec[31]); + assign lru_vp_vec[2] = (lru_rmt_vec[8] | lru_rmt_vec[9] | lru_rmt_vec[10] | lru_rmt_vec[11] | lru_rmt_vec[12] | lru_rmt_vec[13] | lru_rmt_vec[14] | lru_rmt_vec[15]); + assign lru_vp_vec[3] = (lru_rmt_vec[24] | lru_rmt_vec[25] | lru_rmt_vec[26] | lru_rmt_vec[27] | lru_rmt_vec[28] | lru_rmt_vec[29] | lru_rmt_vec[30] | lru_rmt_vec[31]); + assign lru_vp_vec[4] = (lru_rmt_vec[4] | lru_rmt_vec[5] | lru_rmt_vec[6] | lru_rmt_vec[7]); + assign lru_vp_vec[5] = (lru_rmt_vec[12] | lru_rmt_vec[13] | lru_rmt_vec[14] | lru_rmt_vec[15]); + assign lru_vp_vec[6] = (lru_rmt_vec[20] | lru_rmt_vec[21] | lru_rmt_vec[22] | lru_rmt_vec[23]); + assign lru_vp_vec[7] = (lru_rmt_vec[28] | lru_rmt_vec[29] | lru_rmt_vec[30] | lru_rmt_vec[31]); + assign lru_vp_vec[8] = (lru_rmt_vec[2] | lru_rmt_vec[3]); + assign lru_vp_vec[9] = (lru_rmt_vec[6] | lru_rmt_vec[7]); + assign lru_vp_vec[10] = (lru_rmt_vec[10] | lru_rmt_vec[11]); + assign lru_vp_vec[11] = (lru_rmt_vec[14] | lru_rmt_vec[15]); + assign lru_vp_vec[12] = (lru_rmt_vec[18] | lru_rmt_vec[19]); + assign lru_vp_vec[13] = (lru_rmt_vec[22] | lru_rmt_vec[23]); + assign lru_vp_vec[14] = (lru_rmt_vec[26] | lru_rmt_vec[27]); + assign lru_vp_vec[15] = (lru_rmt_vec[30] | lru_rmt_vec[31]); + assign lru_vp_vec[16] = lru_rmt_vec[1]; + assign lru_vp_vec[17] = lru_rmt_vec[3]; + assign lru_vp_vec[18] = lru_rmt_vec[5]; + assign lru_vp_vec[19] = lru_rmt_vec[7]; + assign lru_vp_vec[20] = lru_rmt_vec[9]; + assign lru_vp_vec[21] = lru_rmt_vec[11]; + assign lru_vp_vec[22] = lru_rmt_vec[13]; + assign lru_vp_vec[23] = lru_rmt_vec[15]; + assign lru_vp_vec[24] = lru_rmt_vec[17]; + assign lru_vp_vec[25] = lru_rmt_vec[19]; + assign lru_vp_vec[26] = lru_rmt_vec[21]; + assign lru_vp_vec[27] = lru_rmt_vec[23]; + assign lru_vp_vec[28] = lru_rmt_vec[25]; + assign lru_vp_vec[29] = lru_rmt_vec[27]; + assign lru_vp_vec[30] = lru_rmt_vec[29]; + assign lru_vp_vec[31] = lru_rmt_vec[31]; + // mmucr1_q: 0-DRRE, 1-REE, 2-CEE, 3-csync, 4-isync, 5:6-DPEI, 7:8-DCTID/DTTID, 9-DCCD + // + // Final Table Listing + // *INPUTS*=========*OUTPUTS*============================* + // | | | + // | | lru_rmt_vec_d | + // | watermark_d | | | + // | | | | | + // | | | | | + // | | | | 1111111111222222222233 | + // | 01234 | 01234567890123456789012345678901 | + // *TYPE*===========+====================================+ + // | PPPPP | PPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPP | + // *POLARITY*------>| ++++++++++++++++++++++++++++++++ | + // *PHASE*--------->| TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT | + // *OPTIMIZE*------>| AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA | + // *TERMS*==========+====================================+ + // 1 | 11111 | ...............................1 | + // 2 | -1111 | ...............1................ | + // 3 | 1-111 | .......................1........ | + // 4 | --111 | .......1........................ | + // 5 | 11-11 | ...........................1.... | + // 6 | -1-11 | ...........1.................... | + // 7 | 1--11 | ...................1............ | + // 8 | ---11 | ...1............................ | + // 9 | 111-1 | .............................1.. | + // 10 | -11-1 | .............1.................. | + // 11 | 1-1-1 | .....................1.......... | + // 12 | --1-1 | .....1.......................... | + // 13 | 11--1 | .........................1...... | + // 14 | -1--1 | .........1...................... | + // 15 | 1---1 | .................1.............. | + // 16 | ----1 | .1.............................. | + // 17 | 1111- | .............................11. | + // 18 | -111- | .............11................. | + // 19 | 1-11- | .....................11......... | + // 20 | --11- | .....11......................... | + // 21 | 11-1- | .........................11..... | + // 22 | -1-1- | .........11..................... | + // 23 | 1--1- | .................11............. | + // 24 | ---1- | .11............................. | + // 25 | 111-- | .........................1111... | + // 26 | -11-- | .........1111................... | + // 27 | 1-1-- | .................1111........... | + // 28 | --1-- | .1111........................... | + // 29 | 11--- | .................11111111....... | + // 30 | -1--- | .11111111....................... | + // 31 | 1---- | .1111111111111111............... | + // 32 | ----- | 1............................... | + // *=====================================================* + // + // Table LRU_RMT_VEC_D Signal Assignments for Product Terms + assign LRU_RMT_VEC_D_PT[1] = (({watermark_d[0], watermark_d[1], watermark_d[2], watermark_d[3], watermark_d[4]}) == 5'b11111); + assign LRU_RMT_VEC_D_PT[2] = (({watermark_d[1], watermark_d[2], watermark_d[3], watermark_d[4]}) == 4'b1111); + assign LRU_RMT_VEC_D_PT[3] = (({watermark_d[0], watermark_d[2], watermark_d[3], watermark_d[4]}) == 4'b1111); + assign LRU_RMT_VEC_D_PT[4] = (({watermark_d[2], watermark_d[3], watermark_d[4]}) == 3'b111); + assign LRU_RMT_VEC_D_PT[5] = (({watermark_d[0], watermark_d[1], watermark_d[3], watermark_d[4]}) == 4'b1111); + assign LRU_RMT_VEC_D_PT[6] = (({watermark_d[1], watermark_d[3], watermark_d[4]}) == 3'b111); + assign LRU_RMT_VEC_D_PT[7] = (({watermark_d[0], watermark_d[3], watermark_d[4]}) == 3'b111); + assign LRU_RMT_VEC_D_PT[8] = (({watermark_d[3], watermark_d[4]}) == 2'b11); + assign LRU_RMT_VEC_D_PT[9] = (({watermark_d[0], watermark_d[1], watermark_d[2], watermark_d[4]}) == 4'b1111); + assign LRU_RMT_VEC_D_PT[10] = (({watermark_d[1], watermark_d[2], watermark_d[4]}) == 3'b111); + assign LRU_RMT_VEC_D_PT[11] = (({watermark_d[0], watermark_d[2], watermark_d[4]}) == 3'b111); + assign LRU_RMT_VEC_D_PT[12] = (({watermark_d[2], watermark_d[4]}) == 2'b11); + assign LRU_RMT_VEC_D_PT[13] = (({watermark_d[0], watermark_d[1], watermark_d[4]}) == 3'b111); + assign LRU_RMT_VEC_D_PT[14] = (({watermark_d[1], watermark_d[4]}) == 2'b11); + assign LRU_RMT_VEC_D_PT[15] = (({watermark_d[0], watermark_d[4]}) == 2'b11); + assign LRU_RMT_VEC_D_PT[16] = ((watermark_d[4]) == 1'b1); + assign LRU_RMT_VEC_D_PT[17] = (({watermark_d[0], watermark_d[1], watermark_d[2], watermark_d[3]}) == 4'b1111); + assign LRU_RMT_VEC_D_PT[18] = (({watermark_d[1], watermark_d[2], watermark_d[3]}) == 3'b111); + assign LRU_RMT_VEC_D_PT[19] = (({watermark_d[0], watermark_d[2], watermark_d[3]}) == 3'b111); + assign LRU_RMT_VEC_D_PT[20] = (({watermark_d[2], watermark_d[3]}) == 2'b11); + assign LRU_RMT_VEC_D_PT[21] = (({watermark_d[0], watermark_d[1], watermark_d[3]}) == 3'b111); + assign LRU_RMT_VEC_D_PT[22] = (({watermark_d[1], watermark_d[3]}) == 2'b11); + assign LRU_RMT_VEC_D_PT[23] = (({watermark_d[0], watermark_d[3]}) == 2'b11); + assign LRU_RMT_VEC_D_PT[24] = ((watermark_d[3]) == 1'b1); + assign LRU_RMT_VEC_D_PT[25] = (({watermark_d[0], watermark_d[1], watermark_d[2]}) == 3'b111); + assign LRU_RMT_VEC_D_PT[26] = (({watermark_d[1], watermark_d[2]}) == 2'b11); + assign LRU_RMT_VEC_D_PT[27] = (({watermark_d[0], watermark_d[2]}) == 2'b11); + assign LRU_RMT_VEC_D_PT[28] = ((watermark_d[2]) == 1'b1); + assign LRU_RMT_VEC_D_PT[29] = (({watermark_d[0], watermark_d[1]}) == 2'b11); + assign LRU_RMT_VEC_D_PT[30] = ((watermark_d[1]) == 1'b1); + assign LRU_RMT_VEC_D_PT[31] = ((watermark_d[0]) == 1'b1); + assign LRU_RMT_VEC_D_PT[32] = 1'b1; + // Table LRU_RMT_VEC_D Signal Assignments for Outputs + assign lru_rmt_vec_d[0] = (LRU_RMT_VEC_D_PT[32]); + assign lru_rmt_vec_d[1] = (LRU_RMT_VEC_D_PT[16] | LRU_RMT_VEC_D_PT[24] | LRU_RMT_VEC_D_PT[28] | LRU_RMT_VEC_D_PT[30] | LRU_RMT_VEC_D_PT[31]); + assign lru_rmt_vec_d[2] = (LRU_RMT_VEC_D_PT[24] | LRU_RMT_VEC_D_PT[28] | LRU_RMT_VEC_D_PT[30] | LRU_RMT_VEC_D_PT[31]); + assign lru_rmt_vec_d[3] = (LRU_RMT_VEC_D_PT[8] | LRU_RMT_VEC_D_PT[28] | LRU_RMT_VEC_D_PT[30] | LRU_RMT_VEC_D_PT[31]); + assign lru_rmt_vec_d[4] = (LRU_RMT_VEC_D_PT[28] | LRU_RMT_VEC_D_PT[30] | LRU_RMT_VEC_D_PT[31]); + assign lru_rmt_vec_d[5] = (LRU_RMT_VEC_D_PT[12] | LRU_RMT_VEC_D_PT[20] | LRU_RMT_VEC_D_PT[30] | LRU_RMT_VEC_D_PT[31]); + assign lru_rmt_vec_d[6] = (LRU_RMT_VEC_D_PT[20] | LRU_RMT_VEC_D_PT[30] | LRU_RMT_VEC_D_PT[31]); + assign lru_rmt_vec_d[7] = (LRU_RMT_VEC_D_PT[4] | LRU_RMT_VEC_D_PT[30] | LRU_RMT_VEC_D_PT[31]); + assign lru_rmt_vec_d[8] = (LRU_RMT_VEC_D_PT[30] | LRU_RMT_VEC_D_PT[31]); + assign lru_rmt_vec_d[9] = (LRU_RMT_VEC_D_PT[14] | LRU_RMT_VEC_D_PT[22] | LRU_RMT_VEC_D_PT[26] | LRU_RMT_VEC_D_PT[31]); + assign lru_rmt_vec_d[10] = (LRU_RMT_VEC_D_PT[22] | LRU_RMT_VEC_D_PT[26] | LRU_RMT_VEC_D_PT[31]); + assign lru_rmt_vec_d[11] = (LRU_RMT_VEC_D_PT[6] | LRU_RMT_VEC_D_PT[26] | LRU_RMT_VEC_D_PT[31]); + assign lru_rmt_vec_d[12] = (LRU_RMT_VEC_D_PT[26] | LRU_RMT_VEC_D_PT[31]); + assign lru_rmt_vec_d[13] = (LRU_RMT_VEC_D_PT[10] | LRU_RMT_VEC_D_PT[18] | LRU_RMT_VEC_D_PT[31]); + assign lru_rmt_vec_d[14] = (LRU_RMT_VEC_D_PT[18] | LRU_RMT_VEC_D_PT[31]); + assign lru_rmt_vec_d[15] = (LRU_RMT_VEC_D_PT[2] | LRU_RMT_VEC_D_PT[31]); + assign lru_rmt_vec_d[16] = (LRU_RMT_VEC_D_PT[31]); + assign lru_rmt_vec_d[17] = (LRU_RMT_VEC_D_PT[15] | LRU_RMT_VEC_D_PT[23] | LRU_RMT_VEC_D_PT[27] | LRU_RMT_VEC_D_PT[29]); + assign lru_rmt_vec_d[18] = (LRU_RMT_VEC_D_PT[23] | LRU_RMT_VEC_D_PT[27] | LRU_RMT_VEC_D_PT[29]); + assign lru_rmt_vec_d[19] = (LRU_RMT_VEC_D_PT[7] | LRU_RMT_VEC_D_PT[27] | LRU_RMT_VEC_D_PT[29]); + assign lru_rmt_vec_d[20] = (LRU_RMT_VEC_D_PT[27] | LRU_RMT_VEC_D_PT[29]); + assign lru_rmt_vec_d[21] = (LRU_RMT_VEC_D_PT[11] | LRU_RMT_VEC_D_PT[19] | LRU_RMT_VEC_D_PT[29]); + assign lru_rmt_vec_d[22] = (LRU_RMT_VEC_D_PT[19] | LRU_RMT_VEC_D_PT[29]); + assign lru_rmt_vec_d[23] = (LRU_RMT_VEC_D_PT[3] | LRU_RMT_VEC_D_PT[29]); + assign lru_rmt_vec_d[24] = (LRU_RMT_VEC_D_PT[29]); + assign lru_rmt_vec_d[25] = (LRU_RMT_VEC_D_PT[13] | LRU_RMT_VEC_D_PT[21] | LRU_RMT_VEC_D_PT[25]); + assign lru_rmt_vec_d[26] = (LRU_RMT_VEC_D_PT[21] | LRU_RMT_VEC_D_PT[25]); + assign lru_rmt_vec_d[27] = (LRU_RMT_VEC_D_PT[5] | LRU_RMT_VEC_D_PT[25]); + assign lru_rmt_vec_d[28] = (LRU_RMT_VEC_D_PT[25]); + assign lru_rmt_vec_d[29] = (LRU_RMT_VEC_D_PT[9] | LRU_RMT_VEC_D_PT[17]); + assign lru_rmt_vec_d[30] = (LRU_RMT_VEC_D_PT[17]); + assign lru_rmt_vec_d[31] = (LRU_RMT_VEC_D_PT[1]); + + assign mmucr1_b0_cpy_d = mmucr1_d[0]; + assign lru_rmt_vec = lru_rmt_vec_q; + assign lru_watermark_mask = (~lru_rmt_vec_q); + assign entry_valid_watermarked = entry_valid_q | lru_watermark_mask; + // lru_update_event + // 0: tlb reload + // 1: invalidate snoop + // 2: csync or isync enabled + // 3: eratwe WS=0 + // 4: load or store hit + // 5: cam write type events + // 6: cam invalidate type events + // 7: cam translation type events + // 8: superset, ex3 + // 9: superset, delayed to ex4 + // logic for the LRU reset and set bit vectors + // ?TABLE lru_set_reset_vec LISTING(final) OPTIMIZE PARMS(ON-SET, OFF-SET); + // + // Final Table Listing + // *INPUTS*========================================================================================================*OUTPUTS*=============================================================* + // | | | + // | lru_update_event_q | lru_reset_vec | + // | | entry_valid_watermarked | | lru_set_vec | + // | | | lru_q | | | | + // | | | | entry_match_q | | | | + // | | | | | | | | | + // | | | | | | | | | + // | | | 1111111111222222222233 | 1111111111222222222233 | 1111111111222222222233 | | 1111111111222222222233 | 1111111111222222222233 | + // | 012345678 01234567890123456789012345678901 1234567890123456789012345678901 01234567890123456789012345678901 | 1234567890123456789012345678901 1234567890123456789012345678901 | + // *TYPE*==========================================================================================================+=====================================================================+ + // | PPPPPPPPP PPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPP PPPPPPPPPPPPPPPPPPPPPPPPPPPPPPP PPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPP | PPPPPPPPPPPPPPPPPPPPPPPPPPPPPPP PPPPPPPPPPPPPPPPPPPPPPPPPPPPPPP | + // *POLARITY*----------------------------------------------------------------------------------------------------->| +++++++++++++++++++++++++++++++ +++++++++++++++++++++++++++++++ | + // *PHASE*-------------------------------------------------------------------------------------------------------->| TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT TTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT | + // *OPTIMIZE*----------------------------------------------------------------------------------------------------->| AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB | + // *TERMS*=========================================================================================================+=====================================================================+ + // 1 | -----001- 11111111111111111111111111111111 ------------------------------- 00000000000000000000000000000001 | 1.1...1.......1...............1 ............................... | + // 2 | -----001- 11111111111111111111111111111111 ------------------------------- 0000000000000000000000000000001- | 1.1...1.......1................ ............................... | + // 3 | -----001- 1111111111111111111111111111111- ------------------------------- 0000000000000000000000000000001- | ............................... ..............................1 | + // 4 | -----001- 11111111111111111111111111111111 ------------------------------- 000000000000000000000000000001-- | 1.1...1......................1. ............................... | + // 5 | -----001- 111111111111111111111111111111-- ------------------------------- 0000000000000000000000000000-1-- | ............................... ..............1................ | + // 6 | -----001- 11111111111111111111111111111111 ------------------------------- 00000000000000000000000000001--- | 1.1...1........................ ..............1..............1. | + // 7 | -----001- 11111111111111111111111111111111 ------------------------------- 0000000000000000000000000001---- | 1.1..........1..............1.. ............................... | + // 8 | -----001- 1111111111111111111111111111---- ------------------------------- 000000000000000000000000---1---- | ............................... ......1........................ | + // 9 | -----001- 11111111111111111111111111111111 ------------------------------- 000000000000000000000000001----- | 1.1..........1................. ......1.....................1.. | + // 10 | -----001- 11111111111111111111111111111111 ------------------------------- 00000000000000000000000001------ | 1.1........................1... ............................... | + // 11 | -----001- 11111111111111111111111111111111 ------------------------------- 000000000000000000000000-1------ | ............................... ......1......1................. | + // 12 | -----001- 11111111111111111111111111111111 ------------------------------- 0000000000000000000000001------- | 1.1............................ ......1......1.............1... | + // 13 | -----001- 11111111111111111111111111111111 ------------------------------- 000000000000000000000001-------- | 1....1......1.............1.... ............................... | + // 14 | -----001- 111111111111111111111111-------- ------------------------------- 0000000000000000-------1-------- | ............................... ..1............................ | + // 15 | -----001- 11111111111111111111111111111111 ------------------------------- 00000000000000000000001--------- | 1....1......1.................. ..1.......................1.... | + // 16 | -----001- 11111111111111111111111111111111 ------------------------------- 0000000000000000000001---------- | 1....1...................1..... ............................... | + // 17 | -----001- 11111111111111111111111111111111 ------------------------------- 00000000000000000000-1---------- | ............................... ..1.........1.................. | + // 18 | -----001- 11111111111111111111111111111111 ------------------------------- 000000000000000000001----------- | 1....1......................... ..1.........1............1..... | + // 19 | -----001- 11111111111111111111111111111111 ------------------------------- 00000000000000000001------------ | 1..........1............1...... ............................... | + // 20 | -----001- 11111111111111111111111111111111 ------------------------------- 0000000000000000---1------------ | ............................... ..1..1......................... | + // 21 | -----001- 11111111111111111111111111111111 ------------------------------- 0000000000000000001------------- | 1..........1................... ..1..1..................1...... | + // 22 | -----001- 11111111111111111111111111111111 ------------------------------- 000000000000000001-------------- | 1......................1....... ............................... | + // 23 | -----001- 11111111111111111111111111111111 ------------------------------- 0000000000000000-1-------------- | ............................... ..1..1.....1................... | + // 24 | -----001- 11111111111111111111111111111111 ------------------------------- 00000000000000001--------------- | ............................... ..1..1.....1...........1....... | + // 25 | -----001- ----------------1111111111111111 ------------------------------- 00000000000000001--------------- | 1.............................. ............................... | + // 26 | -----001- 11111111111111111111111111111111 ------------------------------- 0000000000000001---------------- | .1..1.....1...........1........ ............................... | + // 27 | -----001- 1111111111111111---------------- ------------------------------- ---------------1---------------- | ............................... 1.............................. | + // 28 | -----001- 11111111111111111111111111111111 ------------------------------- 000000000000001----------------- | .1..1.....1.................... 1.....................1........ | + // 29 | -----001- 11111111111111111111111111111111 ------------------------------- 00000000000001------------------ | .1..1................1......... ............................... | + // 30 | -----001- 11111111111111111111111111111111 ------------------------------- 000000000000-1------------------ | ............................... 1.........1.................... | + // 31 | -----001- 11111111111111111111111111111111 ------------------------------- 0000000000001------------------- | .1..1.......................... 1.........1..........1......... | + // 32 | -----001- 11111111111111111111111111111111 ------------------------------- 000000000001-------------------- | .1.......1..........1.......... ............................... | + // 33 | -----001- 11111111111111111111111111111111 ------------------------------- 00000000---1-------------------- | ............................... 1...1.......................... | + // 34 | -----001- 11111111111111111111111111111111 ------------------------------- 00000000001--------------------- | .1.......1..................... 1...1...............1.......... | + // 35 | -----001- 11111111111111111111111111111111 ------------------------------- 0000000001---------------------- | .1.................1........... ............................... | + // 36 | -----001- 11111111111111111111111111111111 ------------------------------- 00000000-1---------------------- | ............................... 1...1....1..................... | + // 37 | -----001- 11111111111111111111111111111111 ------------------------------- 000000001----------------------- | ............................... 1...1....1.........1........... | + // 38 | -----001- --------111111111111111111111111 ------------------------------- 000000001----------------------- | .1............................. ............................... | + // 39 | -----001- 11111111111111111111111111111111 ------------------------------- 00000001------------------------ | ...1....1.........1............ ............................... | + // 40 | -----001- 11111111111111111111111111111111 ------------------------------- -------1------------------------ | ............................... 11............................. | + // 41 | -----001- 11111111111111111111111111111111 ------------------------------- 0000001------------------------- | ...1....1...................... 11................1............ | + // 42 | -----001- 11111111111111111111111111111111 ------------------------------- 000001-------------------------- | ...1.............1............. ............................... | + // 43 | -----001- 11111111111111111111111111111111 ------------------------------- 0000-1-------------------------- | ............................... 11......1...................... | + // 44 | -----001- 11111111111111111111111111111111 ------------------------------- 00001--------------------------- | ............................... 11......1........1............. | + // 45 | -----001- ----1111111111111111111111111111 ------------------------------- 00001--------------------------- | ...1........................... ............................... | + // 46 | -----001- 11111111111111111111111111111111 ------------------------------- 0001---------------------------- | .......1........1.............. ............................... | + // 47 | -----001- 11111111111111111111111111111111 ------------------------------- ---1---------------------------- | ............................... 11.1........................... | + // 48 | -----001- 11111111111111111111111111111111 ------------------------------- 001----------------------------- | ............................... 11.1............1.............. | + // 49 | -----001- --111111111111111111111111111111 ------------------------------- 001----------------------------- | .......1....................... ............................... | + // 50 | -----001- -1111111111111111111111111111111 ------------------------------- 01------------------------------ | ...............1............... ............................... | + // 51 | -----001- 11111111111111111111111111111111 ------------------------------- -1------------------------------ | ............................... 11.1...1....................... | + // 52 | -----001- 11111111111111111111111111111111 ------------------------------- 1------------------------------- | ............................... 11.1...1.......1............... | + // 53 | -----1--- 1111111111111111111111111111111- 1-1---1-------1---------------0 -------------------------------- | ............................... ..............................1 | + // 54 | -----1--- 111111111111111111111111111111-1 1-1---1-------1---------------1 -------------------------------- | ..............................1 ............................... | + // 55 | -----1--- 11111111111111111111111111111-11 1-1---1-------0--------------0- -------------------------------- | ............................... .............................1. | + // 56 | -----1--- 1111111111111111111111111111-111 1-1---1-------0--------------1- -------------------------------- | .............................1. ............................... | + // 57 | -----1--- 111111111111111111111111111-1111 1-1---0------1--------------0-- -------------------------------- | ............................... ............................1.. | + // 58 | -----1--- 11111111111111111111111111-11111 1-1---0------1--------------1-- -------------------------------- | ............................1.. ............................... | + // 59 | -----1--- 1111111111111111111111111-111111 1-1---0------0-------------0--- -------------------------------- | ............................... ...........................1... | + // 60 | -----1--- 111111111111111111111111-1111111 1-1---0------0-------------1--- -------------------------------- | ...........................1... ............................... | + // 61 | -----1--- 11111111111111111111111-11111111 1-0--1------1-------------0---- -------------------------------- | ............................... ..........................1.... | + // 62 | -----1--- 1111111111111111111111-111111111 1-0--1------1-------------1---- -------------------------------- | ..........................1.... ............................... | + // 63 | -----1--- 111111111111111111111-1111111111 1-0--1------0------------0----- -------------------------------- | ............................... .........................1..... | + // 64 | -----1--- 11111111111111111111-11111111111 1-0--1------0------------1----- -------------------------------- | .........................1..... ............................... | + // 65 | -----1--- 1111111111111111111-111111111111 1-0--0-----1------------0------ -------------------------------- | ............................... ........................1...... | + // 66 | -----1--- 111111111111111111-1111111111111 1-0--0-----1------------1------ -------------------------------- | ........................1...... ............................... | + // 67 | -----1--- 11111111111111111-11111111111111 1-0--0-----0-----------0------- -------------------------------- | ............................... .......................1....... | + // 68 | -----1--- 1111111111111111-111111111111111 1-0--0-----0-----------1------- -------------------------------- | .......................1....... ............................... | + // 69 | -----1--- 111111111111111-1111111111111111 01--1-----1-----------0-------- -------------------------------- | ............................... ......................1........ | + // 70 | -----1--- 11111111111111-11111111111111111 01--1-----1-----------1-------- -------------------------------- | ......................1........ ............................... | + // 71 | -----1--- 1111111111111-111111111111111111 01--1-----0----------0--------- -------------------------------- | ............................... .....................1......... | + // 72 | -----1--- 111111111111-1111111111111111111 01--1-----0----------1--------- -------------------------------- | .....................1......... ............................... | + // 73 | -----1--- 11111111111-11111111111111111111 01--0----1----------0---------- -------------------------------- | ............................... ....................1.......... | + // 74 | -----1--- 1111111111-111111111111111111111 01--0----1----------1---------- -------------------------------- | ....................1.......... ............................... | + // 75 | -----1--- 111111111-1111111111111111111111 01--0----0---------0----------- -------------------------------- | ............................... ...................1........... | + // 76 | -----1--- 11111111-11111111111111111111111 01--0----0---------1----------- -------------------------------- | ...................1........... ............................... | + // 77 | -----1--- 1111111-111111111111111111111111 00-1----1---------0------------ -------------------------------- | ............................... ..................1............ | + // 78 | -----1--- 111111-1111111111111111111111111 00-1----1---------1------------ -------------------------------- | ..................1............ ............................... | + // 79 | -----1--- 11111-11111111111111111111111111 00-1----0--------0------------- -------------------------------- | ............................... .................1............. | + // 80 | -----1--- 1111-111111111111111111111111111 00-1----0--------1------------- -------------------------------- | .................1............. ............................... | + // 81 | -----1--- 111-1111111111111111111111111111 00-0---1--------0-------------- -------------------------------- | ............................... ................1.............. | + // 82 | -----1--- 11-11111111111111111111111111111 00-0---1--------1-------------- -------------------------------- | ................1.............. ............................... | + // 83 | -----1--- 1-111111111111111111111111111111 00-0---0-------0--------------- -------------------------------- | ............................... ...............1............... | + // 84 | -----1--- -1111111111111111111111111111111 00-0---0-------1--------------- -------------------------------- | ...............1............... ............................... | + // 85 | -----1--- 111111111111111111111111111111-- 1-1---1-------0---------------- -------------------------------- | ............................... ..............1................ | + // 86 | -----1--- 1111111111111111111111111111--11 1-1---1-------1---------------- -------------------------------- | ..............1................ ............................... | + // 87 | -----1--- 11111111111111111111111111--1111 1-1---0------0----------------- -------------------------------- | ............................... .............1................. | + // 88 | -----1--- 111111111111111111111111--111111 1-1---0------1----------------- -------------------------------- | .............1................. ............................... | + // 89 | -----1--- 1111111111111111111111--11111111 1-0--1------0------------------ -------------------------------- | ............................... ............1.................. | + // 90 | -----1--- 11111111111111111111--1111111111 1-0--1------1------------------ -------------------------------- | ............1.................. ............................... | + // 91 | -----1--- 111111111111111111--111111111111 1-0--0-----0------------------- -------------------------------- | ............................... ...........1................... | + // 92 | -----1--- 1111111111111111--11111111111111 1-0--0-----1------------------- -------------------------------- | ...........1................... ............................... | + // 93 | -----1--- 11111111111111--1111111111111111 01--1-----0-------------------- -------------------------------- | ............................... ..........1.................... | + // 94 | -----1--- 111111111111--111111111111111111 01--1-----1-------------------- -------------------------------- | ..........1.................... ............................... | + // 95 | -----1--- 1111111111--11111111111111111111 01--0----0--------------------- -------------------------------- | ............................... .........1..................... | + // 96 | -----1--- 11111111--1111111111111111111111 01--0----1--------------------- -------------------------------- | .........1..................... ............................... | + // 97 | -----1--- 111111--111111111111111111111111 00-1----0---------------------- -------------------------------- | ............................... ........1...................... | + // 98 | -----1--- 1111--11111111111111111111111111 00-1----1---------------------- -------------------------------- | ........1...................... ............................... | + // 99 | -----1--- 11--1111111111111111111111111111 00-0---0----------------------- -------------------------------- | ............................... .......1....................... | + // 100 | -----1--- --111111111111111111111111111111 00-0---1----------------------- -------------------------------- | .......1....................... ............................... | + // 101 | -----1--- 1111111111111111111111111111---- 1-1---0------------------------ -------------------------------- | ............................... ......1........................ | + // 102 | -----1--- 111111111111111111111111----1111 1-1---1------------------------ -------------------------------- | ......1........................ ............................... | + // 103 | -----1--- 11111111111111111111----11111111 1-0--0------------------------- -------------------------------- | ............................... .....1......................... | + // 104 | -----1--- 1111111111111111----111111111111 1-0--1------------------------- -------------------------------- | .....1......................... ............................... | + // 105 | -----1--- 111111111111----1111111111111111 01--0-------------------------- -------------------------------- | ............................... ....1.......................... | + // 106 | -----1--- 11111111----11111111111111111111 01--1-------------------------- -------------------------------- | ....1.......................... ............................... | + // 107 | -----1--- 1111----111111111111111111111111 00-0--------------------------- -------------------------------- | ............................... ...1........................... | + // 108 | -----1--- ----1111111111111111111111111111 00-1--------------------------- -------------------------------- | ...1........................... ............................... | + // 109 | -----1--- 111111111111111111111111-------- 1-0---------------------------- -------------------------------- | ............................... ..1............................ | + // 110 | -----1--- 1111111111111111--------11111111 1-1---------------------------- -------------------------------- | ..1............................ ............................... | + // 111 | -----1--- 11111111--------1111111111111111 00----------------------------- -------------------------------- | ............................... .1............................. | + // 112 | -----1--- --------111111111111111111111111 01----------------------------- -------------------------------- | .1............................. ............................... | + // 113 | -----1--- 1111111111111111---------------- 0------------------------------ -------------------------------- | ............................... 1.............................. | + // 114 | -----1--- ----------------1111111111111111 1------------------------------ -------------------------------- | 1.............................. ............................... | + // 115 | --------- 11111111111111111111111111111110 ------------------------------- -------------------------------- | ............................... 1.1...1.......1...............1 | + // 116 | --------- 1111111111111111111111111111110- ------------------------------- -------------------------------- | ..............................1 1.1...1.......1................ | + // 117 | --------- 111111111111111111111111111110-- ------------------------------- -------------------------------- | ............................... 1.1...1......................1. | + // 118 | --------- 1111111111111111111111111111-0-- ------------------------------- -------------------------------- | ..............1................ ............................... | + // 119 | --------- 11111111111111111111111111110--- ------------------------------- -------------------------------- | ..............1..............1. 1.1...1........................ | + // 120 | --------- 1111111111111111111111111110---- ------------------------------- -------------------------------- | ............................... 1.1..........1..............1.. | + // 121 | --------- 111111111111111111111111---0---- ------------------------------- -------------------------------- | ......1........................ ............................... | + // 122 | --------- 111111111111111111111111110----- ------------------------------- -------------------------------- | ......1.....................1.. 1.1..........1................. | + // 123 | --------- 11111111111111111111111110------ ------------------------------- -------------------------------- | ............................... 1.1........................1... | + // 124 | --------- 111111111111111111111111-0------ ------------------------------- -------------------------------- | ......1......1................. ............................... | + // 125 | --------- 1111111111111111111111110------- ------------------------------- -------------------------------- | ......1......1.............1... 1.1............................ | + // 126 | --------- 111111111111111111111110-------- ------------------------------- -------------------------------- | ............................... 1....1......1.............1.... | + // 127 | --------- 1111111111111111-------0-------- ------------------------------- -------------------------------- | ..1............................ ............................... | + // 128 | --------- 11111111111111111111110--------- ------------------------------- -------------------------------- | ..1.......................1.... 1....1......1.................. | + // 129 | --------- 1111111111111111111110---------- ------------------------------- -------------------------------- | ............................... 1....1...................1..... | + // 130 | --------- 11111111111111111111-0---------- ------------------------------- -------------------------------- | ..1.........1.................. ............................... | + // 131 | --------- 111111111111111111110----------- ------------------------------- -------------------------------- | ..1.........1............1..... 1....1......................... | + // 132 | --------- 11111111111111111110------------ ------------------------------- -------------------------------- | ............................... 1..........1............1...... | + // 133 | --------- 1111111111111111---0------------ ------------------------------- -------------------------------- | ..1..1......................... ............................... | + // 134 | --------- 1111111111111111110------------- ------------------------------- -------------------------------- | ..1..1..................1...... 1..........1................... | + // 135 | --------- 111111111111111110-------------- ------------------------------- -------------------------------- | ............................... 1......................1....... | + // 136 | --------- 1111111111111111-0-------------- ------------------------------- -------------------------------- | ..1..1.....1................... ............................... | + // 137 | --------- 11111111111111110--------------- ------------------------------- -------------------------------- | ..1..1.....1...........1....... 1.............................. | + // 138 | --------- 1111111111111110---------------- ------------------------------- -------------------------------- | ............................... .1..1.....1...........1........ | + // 139 | --------- ---------------0---------------- ------------------------------- -------------------------------- | 1.............................. ............................... | + // 140 | --------- 111111111111110----------------- ------------------------------- -------------------------------- | 1.....................1........ .1..1.....1.................... | + // 141 | --------- 11111111111110------------------ ------------------------------- -------------------------------- | ............................... .1..1................1......... | + // 142 | --------- 111111111111-0------------------ ------------------------------- -------------------------------- | 1.........1.................... ............................... | + // 143 | --------- 1111111111110------------------- ------------------------------- -------------------------------- | 1.........1..........1......... .1..1.......................... | + // 144 | --------- 111111111110-------------------- ------------------------------- -------------------------------- | ............................... .1.......1..........1.......... | + // 145 | --------- 11111111---0-------------------- ------------------------------- -------------------------------- | 1...1.......................... ............................... | + // 146 | --------- 11111111110--------------------- ------------------------------- -------------------------------- | 1...1...............1.......... .1.......1..................... | + // 147 | --------- 1111111110---------------------- ------------------------------- -------------------------------- | ............................... .1.................1........... | + // 148 | --------- 11111111-0---------------------- ------------------------------- -------------------------------- | 1...1....1..................... ............................... | + // 149 | --------- 111111110----------------------- ------------------------------- -------------------------------- | 1...1....1.........1........... .1............................. | + // 150 | --------- 11111110------------------------ ------------------------------- -------------------------------- | ............................... ...1....1.........1............ | + // 151 | --------- -------0------------------------ ------------------------------- -------------------------------- | 11............................. ............................... | + // 152 | --------- 1111110------------------------- ------------------------------- -------------------------------- | 11................1............ ...1....1...................... | + // 153 | --------- 111110-------------------------- ------------------------------- -------------------------------- | ............................... ...1.............1............. | + // 154 | --------- 1111-0-------------------------- ------------------------------- -------------------------------- | 11......1...................... ............................... | + // 155 | --------- 11110--------------------------- ------------------------------- -------------------------------- | 11......1........1............. ...1........................... | + // 156 | --------- 1110---------------------------- ------------------------------- -------------------------------- | ............................... .......1........1.............. | + // 157 | --------- ---0---------------------------- ------------------------------- -------------------------------- | 11.1........................... ............................... | + // 158 | --------- 110----------------------------- ------------------------------- -------------------------------- | 11.1............1.............. .......1....................... | + // 159 | --------- 10------------------------------ ------------------------------- -------------------------------- | ............................... ...............1............... | + // 160 | --------- -0------------------------------ ------------------------------- -------------------------------- | 11.1...1....................... ............................... | + // 161 | --------- 0------------------------------- ------------------------------- -------------------------------- | 11.1...1.......1............... ............................... | + // *=====================================================================================================================================================================================* + // + // Table LRU_SET_RESET_VEC Signal Assignments for Product Terms + assign LRU_SET_RESET_VEC_PT[1] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], entry_match_q[0], entry_match_q[1], entry_match_q[2], entry_match_q[3], entry_match_q[4], entry_match_q[5], entry_match_q[6], entry_match_q[7], entry_match_q[8], entry_match_q[9], entry_match_q[10], entry_match_q[11], entry_match_q[12], entry_match_q[13], entry_match_q[14], entry_match_q[15], entry_match_q[16], entry_match_q[17], entry_match_q[18], entry_match_q[19], entry_match_q[20], entry_match_q[21], entry_match_q[22], entry_match_q[23], entry_match_q[24], entry_match_q[25], entry_match_q[26], entry_match_q[27], entry_match_q[28], entry_match_q[29], entry_match_q[30], entry_match_q[31]}) == {55'b0011111111111111111111111111111111100000000000000000000, 12'b000000000001}); + assign LRU_SET_RESET_VEC_PT[2] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], entry_match_q[0], entry_match_q[1], entry_match_q[2], entry_match_q[3], entry_match_q[4], entry_match_q[5], entry_match_q[6], entry_match_q[7], entry_match_q[8], entry_match_q[9], entry_match_q[10], entry_match_q[11], entry_match_q[12], entry_match_q[13], entry_match_q[14], entry_match_q[15], entry_match_q[16], entry_match_q[17], entry_match_q[18], entry_match_q[19], entry_match_q[20], entry_match_q[21], entry_match_q[22], entry_match_q[23], entry_match_q[24], entry_match_q[25], entry_match_q[26], entry_match_q[27], entry_match_q[28], entry_match_q[29], entry_match_q[30]}) == 66'b001111111111111111111111111111111110000000000000000000000000000001); + assign LRU_SET_RESET_VEC_PT[3] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_match_q[0], entry_match_q[1], entry_match_q[2], entry_match_q[3], entry_match_q[4], entry_match_q[5], entry_match_q[6], entry_match_q[7], entry_match_q[8], entry_match_q[9], entry_match_q[10], entry_match_q[11], entry_match_q[12], entry_match_q[13], entry_match_q[14], entry_match_q[15], entry_match_q[16], entry_match_q[17], entry_match_q[18], entry_match_q[19], entry_match_q[20], entry_match_q[21], entry_match_q[22], entry_match_q[23], entry_match_q[24], entry_match_q[25], entry_match_q[26], entry_match_q[27], entry_match_q[28], entry_match_q[29], entry_match_q[30]}) == {55'b0011111111111111111111111111111111000000000000000000000, 10'b0000000001}); + assign LRU_SET_RESET_VEC_PT[4] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], entry_match_q[0], entry_match_q[1], entry_match_q[2], entry_match_q[3], entry_match_q[4], entry_match_q[5], entry_match_q[6], entry_match_q[7], entry_match_q[8], entry_match_q[9], entry_match_q[10], entry_match_q[11], entry_match_q[12], entry_match_q[13], entry_match_q[14], entry_match_q[15], entry_match_q[16], entry_match_q[17], entry_match_q[18], entry_match_q[19], entry_match_q[20], entry_match_q[21], entry_match_q[22], entry_match_q[23], entry_match_q[24], entry_match_q[25], entry_match_q[26], entry_match_q[27], entry_match_q[28], entry_match_q[29]}) == {55'b0011111111111111111111111111111111100000000000000000000, 10'b0000000001}); + assign LRU_SET_RESET_VEC_PT[5] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_match_q[0], entry_match_q[1], entry_match_q[2], entry_match_q[3], entry_match_q[4], entry_match_q[5], entry_match_q[6], entry_match_q[7], entry_match_q[8], entry_match_q[9], entry_match_q[10], entry_match_q[11], entry_match_q[12], entry_match_q[13], entry_match_q[14], entry_match_q[15], entry_match_q[16], entry_match_q[17], entry_match_q[18], entry_match_q[19], entry_match_q[20], entry_match_q[21], entry_match_q[22], entry_match_q[23], entry_match_q[24], entry_match_q[25], entry_match_q[26], entry_match_q[27], entry_match_q[29]}) == 62'b00111111111111111111111111111111100000000000000000000000000001); + assign LRU_SET_RESET_VEC_PT[6] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], entry_match_q[0], entry_match_q[1], entry_match_q[2], entry_match_q[3], entry_match_q[4], entry_match_q[5], entry_match_q[6], entry_match_q[7], entry_match_q[8], entry_match_q[9], entry_match_q[10], entry_match_q[11], entry_match_q[12], entry_match_q[13], entry_match_q[14], entry_match_q[15], entry_match_q[16], entry_match_q[17], entry_match_q[18], entry_match_q[19], entry_match_q[20], entry_match_q[21], entry_match_q[22], entry_match_q[23], entry_match_q[24], entry_match_q[25], entry_match_q[26], entry_match_q[27], entry_match_q[28]}) == 64'b0011111111111111111111111111111111100000000000000000000000000001); + assign LRU_SET_RESET_VEC_PT[7] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], entry_match_q[0], entry_match_q[1], entry_match_q[2], entry_match_q[3], entry_match_q[4], entry_match_q[5], entry_match_q[6], entry_match_q[7], entry_match_q[8], entry_match_q[9], entry_match_q[10], entry_match_q[11], entry_match_q[12], entry_match_q[13], entry_match_q[14], entry_match_q[15], entry_match_q[16], entry_match_q[17], entry_match_q[18], entry_match_q[19], entry_match_q[20], entry_match_q[21], entry_match_q[22], entry_match_q[23], entry_match_q[24], entry_match_q[25], entry_match_q[26], entry_match_q[27]}) == {55'b0011111111111111111111111111111111100000000000000000000, 8'b00000001}); + assign LRU_SET_RESET_VEC_PT[8] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_match_q[0], entry_match_q[1], entry_match_q[2], entry_match_q[3], entry_match_q[4], entry_match_q[5], entry_match_q[6], entry_match_q[7], entry_match_q[8], entry_match_q[9], entry_match_q[10], entry_match_q[11], entry_match_q[12], entry_match_q[13], entry_match_q[14], entry_match_q[15], entry_match_q[16], entry_match_q[17], entry_match_q[18], entry_match_q[19], entry_match_q[20], entry_match_q[21], entry_match_q[22], entry_match_q[23], entry_match_q[27]}) == 56'b00111111111111111111111111111110000000000000000000000001); + assign LRU_SET_RESET_VEC_PT[9] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], entry_match_q[0], entry_match_q[1], entry_match_q[2], entry_match_q[3], entry_match_q[4], entry_match_q[5], entry_match_q[6], entry_match_q[7], entry_match_q[8], entry_match_q[9], entry_match_q[10], entry_match_q[11], entry_match_q[12], entry_match_q[13], entry_match_q[14], entry_match_q[15], entry_match_q[16], entry_match_q[17], entry_match_q[18], entry_match_q[19], entry_match_q[20], entry_match_q[21], entry_match_q[22], entry_match_q[23], entry_match_q[24], entry_match_q[25], entry_match_q[26]}) == 62'b00111111111111111111111111111111111000000000000000000000000001); + assign LRU_SET_RESET_VEC_PT[10] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], entry_match_q[0], entry_match_q[1], entry_match_q[2], entry_match_q[3], entry_match_q[4], entry_match_q[5], entry_match_q[6], entry_match_q[7], entry_match_q[8], entry_match_q[9], entry_match_q[10], entry_match_q[11], entry_match_q[12], entry_match_q[13], entry_match_q[14], entry_match_q[15], entry_match_q[16], entry_match_q[17], entry_match_q[18], entry_match_q[19], entry_match_q[20], entry_match_q[21], entry_match_q[22], entry_match_q[23], entry_match_q[24], entry_match_q[25]}) == {55'b0011111111111111111111111111111111100000000000000000000, 6'b000001}); + assign LRU_SET_RESET_VEC_PT[11] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], entry_match_q[0], entry_match_q[1], entry_match_q[2], entry_match_q[3], entry_match_q[4], entry_match_q[5], entry_match_q[6], entry_match_q[7], entry_match_q[8], entry_match_q[9], entry_match_q[10], entry_match_q[11], entry_match_q[12], entry_match_q[13], entry_match_q[14], entry_match_q[15], entry_match_q[16], entry_match_q[17], entry_match_q[18], entry_match_q[19], entry_match_q[20], entry_match_q[21], entry_match_q[22], entry_match_q[23], entry_match_q[25]}) == 60'b001111111111111111111111111111111110000000000000000000000001); + assign LRU_SET_RESET_VEC_PT[12] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], entry_match_q[0], entry_match_q[1], entry_match_q[2], entry_match_q[3], entry_match_q[4], entry_match_q[5], entry_match_q[6], entry_match_q[7], entry_match_q[8], entry_match_q[9], entry_match_q[10], entry_match_q[11], entry_match_q[12], entry_match_q[13], entry_match_q[14], entry_match_q[15], entry_match_q[16], entry_match_q[17], entry_match_q[18], entry_match_q[19], entry_match_q[20], entry_match_q[21], entry_match_q[22], entry_match_q[23], entry_match_q[24]}) == 60'b001111111111111111111111111111111110000000000000000000000001); + assign LRU_SET_RESET_VEC_PT[13] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], entry_match_q[0], entry_match_q[1], entry_match_q[2], entry_match_q[3], entry_match_q[4], entry_match_q[5], entry_match_q[6], entry_match_q[7], entry_match_q[8], entry_match_q[9], entry_match_q[10], entry_match_q[11], entry_match_q[12], entry_match_q[13], entry_match_q[14], entry_match_q[15], entry_match_q[16], entry_match_q[17], entry_match_q[18], entry_match_q[19], entry_match_q[20], entry_match_q[21], entry_match_q[22], entry_match_q[23]}) == {55'b0011111111111111111111111111111111100000000000000000000, 4'b0001}); + assign LRU_SET_RESET_VEC_PT[14] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_match_q[0], entry_match_q[1], entry_match_q[2], entry_match_q[3], entry_match_q[4], entry_match_q[5], entry_match_q[6], entry_match_q[7], entry_match_q[8], entry_match_q[9], entry_match_q[10], entry_match_q[11], entry_match_q[12], entry_match_q[13], entry_match_q[14], entry_match_q[15], entry_match_q[23]}) == 44'b00111111111111111111111111100000000000000001); + assign LRU_SET_RESET_VEC_PT[15] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], entry_match_q[0], entry_match_q[1], entry_match_q[2], entry_match_q[3], entry_match_q[4], entry_match_q[5], entry_match_q[6], entry_match_q[7], entry_match_q[8], entry_match_q[9], entry_match_q[10], entry_match_q[11], entry_match_q[12], entry_match_q[13], entry_match_q[14], entry_match_q[15], entry_match_q[16], entry_match_q[17], entry_match_q[18], entry_match_q[19], entry_match_q[20], entry_match_q[21], entry_match_q[22]}) == 58'b0011111111111111111111111111111111100000000000000000000001); + assign LRU_SET_RESET_VEC_PT[16] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], entry_match_q[0], entry_match_q[1], entry_match_q[2], entry_match_q[3], entry_match_q[4], entry_match_q[5], entry_match_q[6], entry_match_q[7], entry_match_q[8], entry_match_q[9], entry_match_q[10], entry_match_q[11], entry_match_q[12], entry_match_q[13], entry_match_q[14], entry_match_q[15], entry_match_q[16], entry_match_q[17], entry_match_q[18], entry_match_q[19], entry_match_q[20], entry_match_q[21]}) == {55'b0011111111111111111111111111111111100000000000000000000, 2'b01}); + assign LRU_SET_RESET_VEC_PT[17] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], entry_match_q[0], entry_match_q[1], entry_match_q[2], entry_match_q[3], entry_match_q[4], entry_match_q[5], entry_match_q[6], entry_match_q[7], entry_match_q[8], entry_match_q[9], entry_match_q[10], entry_match_q[11], entry_match_q[12], entry_match_q[13], entry_match_q[14], entry_match_q[15], entry_match_q[16], entry_match_q[17], entry_match_q[18], entry_match_q[19], entry_match_q[21]}) == 56'b00111111111111111111111111111111111000000000000000000001); + assign LRU_SET_RESET_VEC_PT[18] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], entry_match_q[0], entry_match_q[1], entry_match_q[2], entry_match_q[3], entry_match_q[4], entry_match_q[5], entry_match_q[6], entry_match_q[7], entry_match_q[8], entry_match_q[9], entry_match_q[10], entry_match_q[11], entry_match_q[12], entry_match_q[13], entry_match_q[14], entry_match_q[15], entry_match_q[16], entry_match_q[17], entry_match_q[18], entry_match_q[19], entry_match_q[20]}) == 56'b00111111111111111111111111111111111000000000000000000001); + assign LRU_SET_RESET_VEC_PT[19] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], entry_match_q[0], entry_match_q[1], entry_match_q[2], entry_match_q[3], entry_match_q[4], entry_match_q[5], entry_match_q[6], entry_match_q[7], entry_match_q[8], entry_match_q[9], entry_match_q[10], entry_match_q[11], entry_match_q[12], entry_match_q[13], entry_match_q[14], entry_match_q[15], entry_match_q[16], entry_match_q[17], entry_match_q[18], entry_match_q[19]}) == 55'b0011111111111111111111111111111111100000000000000000001); + assign LRU_SET_RESET_VEC_PT[20] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], entry_match_q[0], entry_match_q[1], entry_match_q[2], entry_match_q[3], entry_match_q[4], entry_match_q[5], entry_match_q[6], entry_match_q[7], entry_match_q[8], entry_match_q[9], entry_match_q[10], entry_match_q[11], entry_match_q[12], entry_match_q[13], entry_match_q[14], entry_match_q[15], entry_match_q[19]}) == 52'b0011111111111111111111111111111111100000000000000001); + assign LRU_SET_RESET_VEC_PT[21] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], entry_match_q[0], entry_match_q[1], entry_match_q[2], entry_match_q[3], entry_match_q[4], entry_match_q[5], entry_match_q[6], entry_match_q[7], entry_match_q[8], entry_match_q[9], entry_match_q[10], entry_match_q[11], entry_match_q[12], entry_match_q[13], entry_match_q[14], entry_match_q[15], entry_match_q[16], entry_match_q[17], entry_match_q[18]}) == 54'b001111111111111111111111111111111110000000000000000001); + assign LRU_SET_RESET_VEC_PT[22] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], entry_match_q[0], entry_match_q[1], entry_match_q[2], entry_match_q[3], entry_match_q[4], entry_match_q[5], entry_match_q[6], entry_match_q[7], entry_match_q[8], entry_match_q[9], entry_match_q[10], entry_match_q[11], entry_match_q[12], entry_match_q[13], entry_match_q[14], entry_match_q[15], entry_match_q[16], entry_match_q[17]}) == 53'b00111111111111111111111111111111111000000000000000001); + assign LRU_SET_RESET_VEC_PT[23] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], entry_match_q[0], entry_match_q[1], entry_match_q[2], entry_match_q[3], entry_match_q[4], entry_match_q[5], entry_match_q[6], entry_match_q[7], entry_match_q[8], entry_match_q[9], entry_match_q[10], entry_match_q[11], entry_match_q[12], entry_match_q[13], entry_match_q[14], entry_match_q[15], entry_match_q[17]}) == 52'b0011111111111111111111111111111111100000000000000001); + assign LRU_SET_RESET_VEC_PT[24] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], entry_match_q[0], entry_match_q[1], entry_match_q[2], entry_match_q[3], entry_match_q[4], entry_match_q[5], entry_match_q[6], entry_match_q[7], entry_match_q[8], entry_match_q[9], entry_match_q[10], entry_match_q[11], entry_match_q[12], entry_match_q[13], entry_match_q[14], entry_match_q[15], entry_match_q[16]}) == 52'b0011111111111111111111111111111111100000000000000001); + assign LRU_SET_RESET_VEC_PT[25] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], entry_match_q[0], entry_match_q[1], entry_match_q[2], entry_match_q[3], entry_match_q[4], entry_match_q[5], entry_match_q[6], entry_match_q[7], entry_match_q[8], entry_match_q[9], entry_match_q[10], entry_match_q[11], entry_match_q[12], entry_match_q[13], entry_match_q[14], entry_match_q[15], entry_match_q[16]}) == 36'b001111111111111111100000000000000001); + assign LRU_SET_RESET_VEC_PT[26] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], entry_match_q[0], entry_match_q[1], entry_match_q[2], entry_match_q[3], entry_match_q[4], entry_match_q[5], entry_match_q[6], entry_match_q[7], entry_match_q[8], entry_match_q[9], entry_match_q[10], entry_match_q[11], entry_match_q[12], entry_match_q[13], entry_match_q[14], entry_match_q[15]}) == 51'b001111111111111111111111111111111110000000000000001); + assign LRU_SET_RESET_VEC_PT[27] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_match_q[15]}) == 20'b00111111111111111111); + assign LRU_SET_RESET_VEC_PT[28] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], entry_match_q[0], entry_match_q[1], entry_match_q[2], entry_match_q[3], entry_match_q[4], entry_match_q[5], entry_match_q[6], entry_match_q[7], entry_match_q[8], entry_match_q[9], entry_match_q[10], entry_match_q[11], entry_match_q[12], entry_match_q[13], entry_match_q[14]}) == 50'b00111111111111111111111111111111111000000000000001); + assign LRU_SET_RESET_VEC_PT[29] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], entry_match_q[0], entry_match_q[1], entry_match_q[2], entry_match_q[3], entry_match_q[4], entry_match_q[5], entry_match_q[6], entry_match_q[7], entry_match_q[8], entry_match_q[9], entry_match_q[10], entry_match_q[11], entry_match_q[12], entry_match_q[13]}) == 49'b0011111111111111111111111111111111100000000000001); + assign LRU_SET_RESET_VEC_PT[30] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], entry_match_q[0], entry_match_q[1], entry_match_q[2], entry_match_q[3], entry_match_q[4], entry_match_q[5], entry_match_q[6], entry_match_q[7], entry_match_q[8], entry_match_q[9], entry_match_q[10], entry_match_q[11], entry_match_q[13]}) == 48'b001111111111111111111111111111111110000000000001); + assign LRU_SET_RESET_VEC_PT[31] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], entry_match_q[0], entry_match_q[1], entry_match_q[2], entry_match_q[3], entry_match_q[4], entry_match_q[5], entry_match_q[6], entry_match_q[7], entry_match_q[8], entry_match_q[9], entry_match_q[10], entry_match_q[11], entry_match_q[12]}) == 48'b001111111111111111111111111111111110000000000001); + assign LRU_SET_RESET_VEC_PT[32] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], entry_match_q[0], entry_match_q[1], entry_match_q[2], entry_match_q[3], entry_match_q[4], entry_match_q[5], entry_match_q[6], entry_match_q[7], entry_match_q[8], entry_match_q[9], entry_match_q[10], entry_match_q[11]}) == 47'b00111111111111111111111111111111111000000000001); + assign LRU_SET_RESET_VEC_PT[33] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], entry_match_q[0], entry_match_q[1], entry_match_q[2], entry_match_q[3], entry_match_q[4], entry_match_q[5], entry_match_q[6], entry_match_q[7], entry_match_q[11]}) == 44'b00111111111111111111111111111111111000000001); + assign LRU_SET_RESET_VEC_PT[34] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], entry_match_q[0], entry_match_q[1], entry_match_q[2], entry_match_q[3], entry_match_q[4], entry_match_q[5], entry_match_q[6], entry_match_q[7], entry_match_q[8], entry_match_q[9], entry_match_q[10]}) == 46'b0011111111111111111111111111111111100000000001); + assign LRU_SET_RESET_VEC_PT[35] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], entry_match_q[0], entry_match_q[1], entry_match_q[2], entry_match_q[3], entry_match_q[4], entry_match_q[5], entry_match_q[6], entry_match_q[7], entry_match_q[8], entry_match_q[9]}) == 45'b001111111111111111111111111111111110000000001); + assign LRU_SET_RESET_VEC_PT[36] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], entry_match_q[0], entry_match_q[1], entry_match_q[2], entry_match_q[3], entry_match_q[4], entry_match_q[5], entry_match_q[6], entry_match_q[7], entry_match_q[9]}) == 44'b00111111111111111111111111111111111000000001); + assign LRU_SET_RESET_VEC_PT[37] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], entry_match_q[0], entry_match_q[1], entry_match_q[2], entry_match_q[3], entry_match_q[4], entry_match_q[5], entry_match_q[6], entry_match_q[7], entry_match_q[8]}) == 44'b00111111111111111111111111111111111000000001); + assign LRU_SET_RESET_VEC_PT[38] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], entry_match_q[0], entry_match_q[1], entry_match_q[2], entry_match_q[3], entry_match_q[4], entry_match_q[5], entry_match_q[6], entry_match_q[7], entry_match_q[8]}) == 36'b001111111111111111111111111000000001); + assign LRU_SET_RESET_VEC_PT[39] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], entry_match_q[0], entry_match_q[1], entry_match_q[2], entry_match_q[3], entry_match_q[4], entry_match_q[5], entry_match_q[6], entry_match_q[7]}) == 43'b0011111111111111111111111111111111100000001); + assign LRU_SET_RESET_VEC_PT[40] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], entry_match_q[7]}) == 36'b001111111111111111111111111111111111); + assign LRU_SET_RESET_VEC_PT[41] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], entry_match_q[0], entry_match_q[1], entry_match_q[2], entry_match_q[3], entry_match_q[4], entry_match_q[5], entry_match_q[6]}) == 42'b001111111111111111111111111111111110000001); + assign LRU_SET_RESET_VEC_PT[42] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], entry_match_q[0], entry_match_q[1], entry_match_q[2], entry_match_q[3], entry_match_q[4], entry_match_q[5]}) == 41'b00111111111111111111111111111111111000001); + assign LRU_SET_RESET_VEC_PT[43] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], entry_match_q[0], entry_match_q[1], entry_match_q[2], entry_match_q[3], entry_match_q[5]}) == 40'b0011111111111111111111111111111111100001); + assign LRU_SET_RESET_VEC_PT[44] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], entry_match_q[0], entry_match_q[1], entry_match_q[2], entry_match_q[3], entry_match_q[4]}) == 40'b0011111111111111111111111111111111100001); + assign LRU_SET_RESET_VEC_PT[45] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], entry_match_q[0], entry_match_q[1], entry_match_q[2], entry_match_q[3], entry_match_q[4]}) == 36'b001111111111111111111111111111100001); + assign LRU_SET_RESET_VEC_PT[46] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], entry_match_q[0], entry_match_q[1], entry_match_q[2], entry_match_q[3]}) == 39'b001111111111111111111111111111111110001); + assign LRU_SET_RESET_VEC_PT[47] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], entry_match_q[3]}) == 36'b001111111111111111111111111111111111); + assign LRU_SET_RESET_VEC_PT[48] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], entry_match_q[0], entry_match_q[1], entry_match_q[2]}) == 38'b00111111111111111111111111111111111001); + assign LRU_SET_RESET_VEC_PT[49] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], entry_match_q[0], entry_match_q[1], entry_match_q[2]}) == 36'b001111111111111111111111111111111001); + assign LRU_SET_RESET_VEC_PT[50] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], entry_match_q[0], entry_match_q[1]}) == 36'b001111111111111111111111111111111101); + assign LRU_SET_RESET_VEC_PT[51] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], entry_match_q[1]}) == 36'b001111111111111111111111111111111111); + assign LRU_SET_RESET_VEC_PT[52] = (({lru_update_event_q[5], lru_update_event_q[6], lru_update_event_q[7], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], entry_match_q[0]}) == 36'b001111111111111111111111111111111111); + assign LRU_SET_RESET_VEC_PT[53] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], lru_q[1], lru_q[3], lru_q[7], lru_q[15], lru_q[31]}) == 37'b1111111111111111111111111111111111110); + assign LRU_SET_RESET_VEC_PT[54] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[31], lru_q[1], lru_q[3], lru_q[7], lru_q[15], lru_q[31]}) == 37'b1111111111111111111111111111111111111); + assign LRU_SET_RESET_VEC_PT[55] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[3], lru_q[7], lru_q[15], lru_q[30]}) == 37'b1111111111111111111111111111111111100); + assign LRU_SET_RESET_VEC_PT[56] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[3], lru_q[7], lru_q[15], lru_q[30]}) == 37'b1111111111111111111111111111111111101); + assign LRU_SET_RESET_VEC_PT[57] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[3], lru_q[7], lru_q[14], lru_q[29]}) == 37'b1111111111111111111111111111111111010); + assign LRU_SET_RESET_VEC_PT[58] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[3], lru_q[7], lru_q[14], lru_q[29]}) == 37'b1111111111111111111111111111111111011); + assign LRU_SET_RESET_VEC_PT[59] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[3], lru_q[7], lru_q[14], lru_q[28]}) == 37'b1111111111111111111111111111111111000); + assign LRU_SET_RESET_VEC_PT[60] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[3], lru_q[7], lru_q[14], lru_q[28]}) == 37'b1111111111111111111111111111111111001); + assign LRU_SET_RESET_VEC_PT[61] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[3], lru_q[6], lru_q[13], lru_q[27]}) == 37'b1111111111111111111111111111111110110); + assign LRU_SET_RESET_VEC_PT[62] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[3], lru_q[6], lru_q[13], lru_q[27]}) == 37'b1111111111111111111111111111111110111); + assign LRU_SET_RESET_VEC_PT[63] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[3], lru_q[6], lru_q[13], lru_q[26]}) == 37'b1111111111111111111111111111111110100); + assign LRU_SET_RESET_VEC_PT[64] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[3], lru_q[6], lru_q[13], lru_q[26]}) == 37'b1111111111111111111111111111111110101); + assign LRU_SET_RESET_VEC_PT[65] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[3], lru_q[6], lru_q[12], lru_q[25]}) == 37'b1111111111111111111111111111111110010); + assign LRU_SET_RESET_VEC_PT[66] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[3], lru_q[6], lru_q[12], lru_q[25]}) == 37'b1111111111111111111111111111111110011); + assign LRU_SET_RESET_VEC_PT[67] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[3], lru_q[6], lru_q[12], lru_q[24]}) == 37'b1111111111111111111111111111111110000); + assign LRU_SET_RESET_VEC_PT[68] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[3], lru_q[6], lru_q[12], lru_q[24]}) == 37'b1111111111111111111111111111111110001); + assign LRU_SET_RESET_VEC_PT[69] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[2], lru_q[5], lru_q[11], lru_q[23]}) == 37'b1111111111111111111111111111111101110); + assign LRU_SET_RESET_VEC_PT[70] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[2], lru_q[5], lru_q[11], lru_q[23]}) == 37'b1111111111111111111111111111111101111); + assign LRU_SET_RESET_VEC_PT[71] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[2], lru_q[5], lru_q[11], lru_q[22]}) == 37'b1111111111111111111111111111111101100); + assign LRU_SET_RESET_VEC_PT[72] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[2], lru_q[5], lru_q[11], lru_q[22]}) == 37'b1111111111111111111111111111111101101); + assign LRU_SET_RESET_VEC_PT[73] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[2], lru_q[5], lru_q[10], lru_q[21]}) == 37'b1111111111111111111111111111111101010); + assign LRU_SET_RESET_VEC_PT[74] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[2], lru_q[5], lru_q[10], lru_q[21]}) == 37'b1111111111111111111111111111111101011); + assign LRU_SET_RESET_VEC_PT[75] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[2], lru_q[5], lru_q[10], lru_q[20]}) == 37'b1111111111111111111111111111111101000); + assign LRU_SET_RESET_VEC_PT[76] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[2], lru_q[5], lru_q[10], lru_q[20]}) == 37'b1111111111111111111111111111111101001); + assign LRU_SET_RESET_VEC_PT[77] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[2], lru_q[4], lru_q[9], lru_q[19]}) == 37'b1111111111111111111111111111111100110); + assign LRU_SET_RESET_VEC_PT[78] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[2], lru_q[4], lru_q[9], lru_q[19]}) == 37'b1111111111111111111111111111111100111); + assign LRU_SET_RESET_VEC_PT[79] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[2], lru_q[4], lru_q[9], lru_q[18]}) == 37'b1111111111111111111111111111111100100); + assign LRU_SET_RESET_VEC_PT[80] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[2], lru_q[4], lru_q[9], lru_q[18]}) == 37'b1111111111111111111111111111111100101); + assign LRU_SET_RESET_VEC_PT[81] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[2], lru_q[4], lru_q[8], lru_q[17]}) == 37'b1111111111111111111111111111111100010); + assign LRU_SET_RESET_VEC_PT[82] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[2], lru_q[4], lru_q[8], lru_q[17]}) == 37'b1111111111111111111111111111111100011); + assign LRU_SET_RESET_VEC_PT[83] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[2], lru_q[4], lru_q[8], lru_q[16]}) == 37'b1111111111111111111111111111111100000); + assign LRU_SET_RESET_VEC_PT[84] = (({lru_update_event_q[5], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[2], lru_q[4], lru_q[8], lru_q[16]}) == 37'b1111111111111111111111111111111100001); + assign LRU_SET_RESET_VEC_PT[85] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], lru_q[1], lru_q[3], lru_q[7], lru_q[15]}) == 35'b11111111111111111111111111111111110); + assign LRU_SET_RESET_VEC_PT[86] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[3], lru_q[7], lru_q[15]}) == 35'b11111111111111111111111111111111111); + assign LRU_SET_RESET_VEC_PT[87] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[3], lru_q[7], lru_q[14]}) == 35'b11111111111111111111111111111111100); + assign LRU_SET_RESET_VEC_PT[88] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[3], lru_q[7], lru_q[14]}) == 35'b11111111111111111111111111111111101); + assign LRU_SET_RESET_VEC_PT[89] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[3], lru_q[6], lru_q[13]}) == 35'b11111111111111111111111111111111010); + assign LRU_SET_RESET_VEC_PT[90] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[3], lru_q[6], lru_q[13]}) == 35'b11111111111111111111111111111111011); + assign LRU_SET_RESET_VEC_PT[91] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[3], lru_q[6], lru_q[12]}) == 35'b11111111111111111111111111111111000); + assign LRU_SET_RESET_VEC_PT[92] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[3], lru_q[6], lru_q[12]}) == 35'b11111111111111111111111111111111001); + assign LRU_SET_RESET_VEC_PT[93] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[2], lru_q[5], lru_q[11]}) == 35'b11111111111111111111111111111110110); + assign LRU_SET_RESET_VEC_PT[94] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[2], lru_q[5], lru_q[11]}) == 35'b11111111111111111111111111111110111); + assign LRU_SET_RESET_VEC_PT[95] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[2], lru_q[5], lru_q[10]}) == 35'b11111111111111111111111111111110100); + assign LRU_SET_RESET_VEC_PT[96] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[2], lru_q[5], lru_q[10]}) == 35'b11111111111111111111111111111110101); + assign LRU_SET_RESET_VEC_PT[97] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[2], lru_q[4], lru_q[9]}) == 35'b11111111111111111111111111111110010); + assign LRU_SET_RESET_VEC_PT[98] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[2], lru_q[4], lru_q[9]}) == 35'b11111111111111111111111111111110011); + assign LRU_SET_RESET_VEC_PT[99] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[2], lru_q[4], lru_q[8]}) == 35'b11111111111111111111111111111110000); + assign LRU_SET_RESET_VEC_PT[100] = (({lru_update_event_q[5], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[2], lru_q[4], lru_q[8]}) == 35'b11111111111111111111111111111110001); + assign LRU_SET_RESET_VEC_PT[101] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], lru_q[1], lru_q[3], lru_q[7]}) == 32'b11111111111111111111111111111110); + assign LRU_SET_RESET_VEC_PT[102] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[3], lru_q[7]}) == 32'b11111111111111111111111111111111); + assign LRU_SET_RESET_VEC_PT[103] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[3], lru_q[6]}) == 32'b11111111111111111111111111111100); + assign LRU_SET_RESET_VEC_PT[104] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[3], lru_q[6]}) == 32'b11111111111111111111111111111101); + assign LRU_SET_RESET_VEC_PT[105] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[2], lru_q[5]}) == 32'b11111111111111111111111111111010); + assign LRU_SET_RESET_VEC_PT[106] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[2], lru_q[5]}) == 32'b11111111111111111111111111111011); + assign LRU_SET_RESET_VEC_PT[107] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[2], lru_q[4]}) == 32'b11111111111111111111111111111000); + assign LRU_SET_RESET_VEC_PT[108] = (({lru_update_event_q[5], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[2], lru_q[4]}) == 32'b11111111111111111111111111111001); + assign LRU_SET_RESET_VEC_PT[109] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], lru_q[1], lru_q[3]}) == 27'b111111111111111111111111110); + assign LRU_SET_RESET_VEC_PT[110] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[3]}) == 27'b111111111111111111111111111); + assign LRU_SET_RESET_VEC_PT[111] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[2]}) == 27'b111111111111111111111111100); + assign LRU_SET_RESET_VEC_PT[112] = (({lru_update_event_q[5], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1], lru_q[2]}) == 27'b111111111111111111111111101); + assign LRU_SET_RESET_VEC_PT[113] = (({lru_update_event_q[5], entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], lru_q[1]}) == 18'b111111111111111110); + assign LRU_SET_RESET_VEC_PT[114] = (({lru_update_event_q[5], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31], lru_q[1]}) == 18'b111111111111111111); + assign LRU_SET_RESET_VEC_PT[115] = (({entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30], entry_valid_watermarked[31]}) == 32'b11111111111111111111111111111110); + assign LRU_SET_RESET_VEC_PT[116] = (({entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29], entry_valid_watermarked[30]}) == 31'b1111111111111111111111111111110); + assign LRU_SET_RESET_VEC_PT[117] = (({entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28], entry_valid_watermarked[29]}) == 30'b111111111111111111111111111110); + assign LRU_SET_RESET_VEC_PT[118] = (({entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[29]}) == 29'b11111111111111111111111111110); + assign LRU_SET_RESET_VEC_PT[119] = (({entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27], entry_valid_watermarked[28]}) == 29'b11111111111111111111111111110); + assign LRU_SET_RESET_VEC_PT[120] = (({entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26], entry_valid_watermarked[27]}) == 28'b1111111111111111111111111110); + assign LRU_SET_RESET_VEC_PT[121] = (({entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[27]}) == 25'b1111111111111111111111110); + assign LRU_SET_RESET_VEC_PT[122] = (({entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25], entry_valid_watermarked[26]}) == 27'b111111111111111111111111110); + assign LRU_SET_RESET_VEC_PT[123] = (({entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24], entry_valid_watermarked[25]}) == 26'b11111111111111111111111110); + assign LRU_SET_RESET_VEC_PT[124] = (({entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[25]}) == 25'b1111111111111111111111110); + assign LRU_SET_RESET_VEC_PT[125] = (({entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23], entry_valid_watermarked[24]}) == 25'b1111111111111111111111110); + assign LRU_SET_RESET_VEC_PT[126] = (({entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22], entry_valid_watermarked[23]}) == 24'b111111111111111111111110); + assign LRU_SET_RESET_VEC_PT[127] = (({entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[23]}) == 17'b11111111111111110); + assign LRU_SET_RESET_VEC_PT[128] = (({entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21], entry_valid_watermarked[22]}) == 23'b11111111111111111111110); + assign LRU_SET_RESET_VEC_PT[129] = (({entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20], entry_valid_watermarked[21]}) == 22'b1111111111111111111110); + assign LRU_SET_RESET_VEC_PT[130] = (({entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[21]}) == 21'b111111111111111111110); + assign LRU_SET_RESET_VEC_PT[131] = (({entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19], entry_valid_watermarked[20]}) == 21'b111111111111111111110); + assign LRU_SET_RESET_VEC_PT[132] = (({entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18], entry_valid_watermarked[19]}) == 20'b11111111111111111110); + assign LRU_SET_RESET_VEC_PT[133] = (({entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[19]}) == 17'b11111111111111110); + assign LRU_SET_RESET_VEC_PT[134] = (({entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17], entry_valid_watermarked[18]}) == 19'b1111111111111111110); + assign LRU_SET_RESET_VEC_PT[135] = (({entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16], entry_valid_watermarked[17]}) == 18'b111111111111111110); + assign LRU_SET_RESET_VEC_PT[136] = (({entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[17]}) == 17'b11111111111111110); + assign LRU_SET_RESET_VEC_PT[137] = (({entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15], entry_valid_watermarked[16]}) == 17'b11111111111111110); + assign LRU_SET_RESET_VEC_PT[138] = (({entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14], entry_valid_watermarked[15]}) == 16'b1111111111111110); + assign LRU_SET_RESET_VEC_PT[139] = ((entry_valid_watermarked[15]) == 1'b0); + assign LRU_SET_RESET_VEC_PT[140] = (({entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13], entry_valid_watermarked[14]}) == 15'b111111111111110); + assign LRU_SET_RESET_VEC_PT[141] = (({entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12], entry_valid_watermarked[13]}) == 14'b11111111111110); + assign LRU_SET_RESET_VEC_PT[142] = (({entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[13]}) == 13'b1111111111110); + assign LRU_SET_RESET_VEC_PT[143] = (({entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11], entry_valid_watermarked[12]}) == 13'b1111111111110); + assign LRU_SET_RESET_VEC_PT[144] = (({entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10], entry_valid_watermarked[11]}) == 12'b111111111110); + assign LRU_SET_RESET_VEC_PT[145] = (({entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[11]}) == 9'b111111110); + assign LRU_SET_RESET_VEC_PT[146] = (({entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9], entry_valid_watermarked[10]}) == 11'b11111111110); + assign LRU_SET_RESET_VEC_PT[147] = (({entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8], entry_valid_watermarked[9]}) == 10'b1111111110); + assign LRU_SET_RESET_VEC_PT[148] = (({entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[9]}) == 9'b111111110); + assign LRU_SET_RESET_VEC_PT[149] = (({entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7], entry_valid_watermarked[8]}) == 9'b111111110); + assign LRU_SET_RESET_VEC_PT[150] = (({entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6], entry_valid_watermarked[7]}) == 8'b11111110); + assign LRU_SET_RESET_VEC_PT[151] = ((entry_valid_watermarked[7]) == 1'b0); + assign LRU_SET_RESET_VEC_PT[152] = (({entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5], entry_valid_watermarked[6]}) == 7'b1111110); + assign LRU_SET_RESET_VEC_PT[153] = (({entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4], entry_valid_watermarked[5]}) == 6'b111110); + assign LRU_SET_RESET_VEC_PT[154] = (({entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[5]}) == 5'b11110); + assign LRU_SET_RESET_VEC_PT[155] = (({entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3], entry_valid_watermarked[4]}) == 5'b11110); + assign LRU_SET_RESET_VEC_PT[156] = (({entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2], entry_valid_watermarked[3]}) == 4'b1110); + assign LRU_SET_RESET_VEC_PT[157] = ((entry_valid_watermarked[3]) == 1'b0); + assign LRU_SET_RESET_VEC_PT[158] = (({entry_valid_watermarked[0], entry_valid_watermarked[1], entry_valid_watermarked[2]}) == 3'b110); + assign LRU_SET_RESET_VEC_PT[159] = (({entry_valid_watermarked[0], entry_valid_watermarked[1]}) == 2'b10); + assign LRU_SET_RESET_VEC_PT[160] = ((entry_valid_watermarked[1]) == 1'b0); + assign LRU_SET_RESET_VEC_PT[161] = ((entry_valid_watermarked[0]) == 1'b0); + // Table LRU_SET_RESET_VEC Signal Assignments for Outputs + assign lru_reset_vec[1] = (LRU_SET_RESET_VEC_PT[1] | LRU_SET_RESET_VEC_PT[2] | LRU_SET_RESET_VEC_PT[4] | LRU_SET_RESET_VEC_PT[6] | LRU_SET_RESET_VEC_PT[7] | LRU_SET_RESET_VEC_PT[9] | LRU_SET_RESET_VEC_PT[10] | LRU_SET_RESET_VEC_PT[12] | LRU_SET_RESET_VEC_PT[13] | LRU_SET_RESET_VEC_PT[15] | LRU_SET_RESET_VEC_PT[16] | LRU_SET_RESET_VEC_PT[18] | LRU_SET_RESET_VEC_PT[19] | LRU_SET_RESET_VEC_PT[21] | LRU_SET_RESET_VEC_PT[22] | LRU_SET_RESET_VEC_PT[25] | LRU_SET_RESET_VEC_PT[114] | LRU_SET_RESET_VEC_PT[139] | LRU_SET_RESET_VEC_PT[140] | LRU_SET_RESET_VEC_PT[142] | LRU_SET_RESET_VEC_PT[143] | LRU_SET_RESET_VEC_PT[145] | LRU_SET_RESET_VEC_PT[146] | LRU_SET_RESET_VEC_PT[148] | LRU_SET_RESET_VEC_PT[149] | LRU_SET_RESET_VEC_PT[151] | LRU_SET_RESET_VEC_PT[152] | LRU_SET_RESET_VEC_PT[154] | LRU_SET_RESET_VEC_PT[155] | LRU_SET_RESET_VEC_PT[157] | LRU_SET_RESET_VEC_PT[158] | LRU_SET_RESET_VEC_PT[160] | LRU_SET_RESET_VEC_PT[161]); + assign lru_reset_vec[2] = (LRU_SET_RESET_VEC_PT[26] | LRU_SET_RESET_VEC_PT[28] | LRU_SET_RESET_VEC_PT[29] | LRU_SET_RESET_VEC_PT[31] | LRU_SET_RESET_VEC_PT[32] | LRU_SET_RESET_VEC_PT[34] | LRU_SET_RESET_VEC_PT[35] | LRU_SET_RESET_VEC_PT[38] | LRU_SET_RESET_VEC_PT[112] | LRU_SET_RESET_VEC_PT[151] | LRU_SET_RESET_VEC_PT[152] | LRU_SET_RESET_VEC_PT[154] | LRU_SET_RESET_VEC_PT[155] | LRU_SET_RESET_VEC_PT[157] | LRU_SET_RESET_VEC_PT[158] | LRU_SET_RESET_VEC_PT[160] | LRU_SET_RESET_VEC_PT[161]); + assign lru_reset_vec[3] = (LRU_SET_RESET_VEC_PT[1] | LRU_SET_RESET_VEC_PT[2] | LRU_SET_RESET_VEC_PT[4] | LRU_SET_RESET_VEC_PT[6] | LRU_SET_RESET_VEC_PT[7] | LRU_SET_RESET_VEC_PT[9] | LRU_SET_RESET_VEC_PT[10] | LRU_SET_RESET_VEC_PT[12] | LRU_SET_RESET_VEC_PT[110] | LRU_SET_RESET_VEC_PT[127] | LRU_SET_RESET_VEC_PT[128] | LRU_SET_RESET_VEC_PT[130] | LRU_SET_RESET_VEC_PT[131] | LRU_SET_RESET_VEC_PT[133] | LRU_SET_RESET_VEC_PT[134] | LRU_SET_RESET_VEC_PT[136] | LRU_SET_RESET_VEC_PT[137]); + assign lru_reset_vec[4] = (LRU_SET_RESET_VEC_PT[39] | LRU_SET_RESET_VEC_PT[41] | LRU_SET_RESET_VEC_PT[42] | LRU_SET_RESET_VEC_PT[45] | LRU_SET_RESET_VEC_PT[108] | LRU_SET_RESET_VEC_PT[157] | LRU_SET_RESET_VEC_PT[158] | LRU_SET_RESET_VEC_PT[160] | LRU_SET_RESET_VEC_PT[161]); + assign lru_reset_vec[5] = (LRU_SET_RESET_VEC_PT[26] | LRU_SET_RESET_VEC_PT[28] | LRU_SET_RESET_VEC_PT[29] | LRU_SET_RESET_VEC_PT[31] | LRU_SET_RESET_VEC_PT[106] | LRU_SET_RESET_VEC_PT[145] | LRU_SET_RESET_VEC_PT[146] | LRU_SET_RESET_VEC_PT[148] | LRU_SET_RESET_VEC_PT[149]); + assign lru_reset_vec[6] = (LRU_SET_RESET_VEC_PT[13] | LRU_SET_RESET_VEC_PT[15] | LRU_SET_RESET_VEC_PT[16] | LRU_SET_RESET_VEC_PT[18] | LRU_SET_RESET_VEC_PT[104] | LRU_SET_RESET_VEC_PT[133] | LRU_SET_RESET_VEC_PT[134] | LRU_SET_RESET_VEC_PT[136] | LRU_SET_RESET_VEC_PT[137]); + assign lru_reset_vec[7] = (LRU_SET_RESET_VEC_PT[1] | LRU_SET_RESET_VEC_PT[2] | LRU_SET_RESET_VEC_PT[4] | LRU_SET_RESET_VEC_PT[6] | LRU_SET_RESET_VEC_PT[102] | LRU_SET_RESET_VEC_PT[121] | LRU_SET_RESET_VEC_PT[122] | LRU_SET_RESET_VEC_PT[124] | LRU_SET_RESET_VEC_PT[125]); + assign lru_reset_vec[8] = (LRU_SET_RESET_VEC_PT[46] | LRU_SET_RESET_VEC_PT[49] | LRU_SET_RESET_VEC_PT[100] | LRU_SET_RESET_VEC_PT[160] | LRU_SET_RESET_VEC_PT[161]); + assign lru_reset_vec[9] = (LRU_SET_RESET_VEC_PT[39] | LRU_SET_RESET_VEC_PT[41] | LRU_SET_RESET_VEC_PT[98] | LRU_SET_RESET_VEC_PT[154] | LRU_SET_RESET_VEC_PT[155]); + assign lru_reset_vec[10] = (LRU_SET_RESET_VEC_PT[32] | LRU_SET_RESET_VEC_PT[34] | LRU_SET_RESET_VEC_PT[96] | LRU_SET_RESET_VEC_PT[148] | LRU_SET_RESET_VEC_PT[149]); + assign lru_reset_vec[11] = (LRU_SET_RESET_VEC_PT[26] | LRU_SET_RESET_VEC_PT[28] | LRU_SET_RESET_VEC_PT[94] | LRU_SET_RESET_VEC_PT[142] | LRU_SET_RESET_VEC_PT[143]); + assign lru_reset_vec[12] = (LRU_SET_RESET_VEC_PT[19] | LRU_SET_RESET_VEC_PT[21] | LRU_SET_RESET_VEC_PT[92] | LRU_SET_RESET_VEC_PT[136] | LRU_SET_RESET_VEC_PT[137]); + assign lru_reset_vec[13] = (LRU_SET_RESET_VEC_PT[13] | LRU_SET_RESET_VEC_PT[15] | LRU_SET_RESET_VEC_PT[90] | LRU_SET_RESET_VEC_PT[130] | LRU_SET_RESET_VEC_PT[131]); + assign lru_reset_vec[14] = (LRU_SET_RESET_VEC_PT[7] | LRU_SET_RESET_VEC_PT[9] | LRU_SET_RESET_VEC_PT[88] | LRU_SET_RESET_VEC_PT[124] | LRU_SET_RESET_VEC_PT[125]); + assign lru_reset_vec[15] = (LRU_SET_RESET_VEC_PT[1] | LRU_SET_RESET_VEC_PT[2] | LRU_SET_RESET_VEC_PT[86] | LRU_SET_RESET_VEC_PT[118] | LRU_SET_RESET_VEC_PT[119]); + assign lru_reset_vec[16] = (LRU_SET_RESET_VEC_PT[50] | LRU_SET_RESET_VEC_PT[84] | LRU_SET_RESET_VEC_PT[161]); + assign lru_reset_vec[17] = (LRU_SET_RESET_VEC_PT[46] | LRU_SET_RESET_VEC_PT[82] | LRU_SET_RESET_VEC_PT[158]); + assign lru_reset_vec[18] = (LRU_SET_RESET_VEC_PT[42] | LRU_SET_RESET_VEC_PT[80] | LRU_SET_RESET_VEC_PT[155]); + assign lru_reset_vec[19] = (LRU_SET_RESET_VEC_PT[39] | LRU_SET_RESET_VEC_PT[78] | LRU_SET_RESET_VEC_PT[152]); + assign lru_reset_vec[20] = (LRU_SET_RESET_VEC_PT[35] | LRU_SET_RESET_VEC_PT[76] | LRU_SET_RESET_VEC_PT[149]); + assign lru_reset_vec[21] = (LRU_SET_RESET_VEC_PT[32] | LRU_SET_RESET_VEC_PT[74] | LRU_SET_RESET_VEC_PT[146]); + assign lru_reset_vec[22] = (LRU_SET_RESET_VEC_PT[29] | LRU_SET_RESET_VEC_PT[72] | LRU_SET_RESET_VEC_PT[143]); + assign lru_reset_vec[23] = (LRU_SET_RESET_VEC_PT[26] | LRU_SET_RESET_VEC_PT[70] | LRU_SET_RESET_VEC_PT[140]); + assign lru_reset_vec[24] = (LRU_SET_RESET_VEC_PT[22] | LRU_SET_RESET_VEC_PT[68] | LRU_SET_RESET_VEC_PT[137]); + assign lru_reset_vec[25] = (LRU_SET_RESET_VEC_PT[19] | LRU_SET_RESET_VEC_PT[66] | LRU_SET_RESET_VEC_PT[134]); + assign lru_reset_vec[26] = (LRU_SET_RESET_VEC_PT[16] | LRU_SET_RESET_VEC_PT[64] | LRU_SET_RESET_VEC_PT[131]); + assign lru_reset_vec[27] = (LRU_SET_RESET_VEC_PT[13] | LRU_SET_RESET_VEC_PT[62] | LRU_SET_RESET_VEC_PT[128]); + assign lru_reset_vec[28] = (LRU_SET_RESET_VEC_PT[10] | LRU_SET_RESET_VEC_PT[60] | LRU_SET_RESET_VEC_PT[125]); + assign lru_reset_vec[29] = (LRU_SET_RESET_VEC_PT[7] | LRU_SET_RESET_VEC_PT[58] | LRU_SET_RESET_VEC_PT[122]); + assign lru_reset_vec[30] = (LRU_SET_RESET_VEC_PT[4] | LRU_SET_RESET_VEC_PT[56] | LRU_SET_RESET_VEC_PT[119]); + assign lru_reset_vec[31] = (LRU_SET_RESET_VEC_PT[1] | LRU_SET_RESET_VEC_PT[54] | LRU_SET_RESET_VEC_PT[116]); + assign lru_set_vec[1] = (LRU_SET_RESET_VEC_PT[27] | LRU_SET_RESET_VEC_PT[28] | LRU_SET_RESET_VEC_PT[30] | LRU_SET_RESET_VEC_PT[31] | LRU_SET_RESET_VEC_PT[33] | LRU_SET_RESET_VEC_PT[34] | LRU_SET_RESET_VEC_PT[36] | LRU_SET_RESET_VEC_PT[37] | LRU_SET_RESET_VEC_PT[40] | LRU_SET_RESET_VEC_PT[41] | LRU_SET_RESET_VEC_PT[43] | LRU_SET_RESET_VEC_PT[44] | LRU_SET_RESET_VEC_PT[47] | LRU_SET_RESET_VEC_PT[48] | LRU_SET_RESET_VEC_PT[51] | LRU_SET_RESET_VEC_PT[52] | LRU_SET_RESET_VEC_PT[113] | LRU_SET_RESET_VEC_PT[115] | LRU_SET_RESET_VEC_PT[116] | LRU_SET_RESET_VEC_PT[117] | LRU_SET_RESET_VEC_PT[119] | LRU_SET_RESET_VEC_PT[120] | LRU_SET_RESET_VEC_PT[122] | LRU_SET_RESET_VEC_PT[123] | LRU_SET_RESET_VEC_PT[125] | LRU_SET_RESET_VEC_PT[126] | LRU_SET_RESET_VEC_PT[128] | LRU_SET_RESET_VEC_PT[129] | LRU_SET_RESET_VEC_PT[131] | LRU_SET_RESET_VEC_PT[132] | LRU_SET_RESET_VEC_PT[134] | LRU_SET_RESET_VEC_PT[135] | LRU_SET_RESET_VEC_PT[137]); + assign lru_set_vec[2] = (LRU_SET_RESET_VEC_PT[40] | LRU_SET_RESET_VEC_PT[41] | LRU_SET_RESET_VEC_PT[43] | LRU_SET_RESET_VEC_PT[44] | LRU_SET_RESET_VEC_PT[47] | LRU_SET_RESET_VEC_PT[48] | LRU_SET_RESET_VEC_PT[51] | LRU_SET_RESET_VEC_PT[52] | LRU_SET_RESET_VEC_PT[111] | LRU_SET_RESET_VEC_PT[138] | LRU_SET_RESET_VEC_PT[140] | LRU_SET_RESET_VEC_PT[141] | LRU_SET_RESET_VEC_PT[143] | LRU_SET_RESET_VEC_PT[144] | LRU_SET_RESET_VEC_PT[146] | LRU_SET_RESET_VEC_PT[147] | LRU_SET_RESET_VEC_PT[149]); + assign lru_set_vec[3] = (LRU_SET_RESET_VEC_PT[14] | LRU_SET_RESET_VEC_PT[15] | LRU_SET_RESET_VEC_PT[17] | LRU_SET_RESET_VEC_PT[18] | LRU_SET_RESET_VEC_PT[20] | LRU_SET_RESET_VEC_PT[21] | LRU_SET_RESET_VEC_PT[23] | LRU_SET_RESET_VEC_PT[24] | LRU_SET_RESET_VEC_PT[109] | LRU_SET_RESET_VEC_PT[115] | LRU_SET_RESET_VEC_PT[116] | LRU_SET_RESET_VEC_PT[117] | LRU_SET_RESET_VEC_PT[119] | LRU_SET_RESET_VEC_PT[120] | LRU_SET_RESET_VEC_PT[122] | LRU_SET_RESET_VEC_PT[123] | LRU_SET_RESET_VEC_PT[125]); + assign lru_set_vec[4] = (LRU_SET_RESET_VEC_PT[47] | LRU_SET_RESET_VEC_PT[48] | LRU_SET_RESET_VEC_PT[51] | LRU_SET_RESET_VEC_PT[52] | LRU_SET_RESET_VEC_PT[107] | LRU_SET_RESET_VEC_PT[150] | LRU_SET_RESET_VEC_PT[152] | LRU_SET_RESET_VEC_PT[153] | LRU_SET_RESET_VEC_PT[155]); + assign lru_set_vec[5] = (LRU_SET_RESET_VEC_PT[33] | LRU_SET_RESET_VEC_PT[34] | LRU_SET_RESET_VEC_PT[36] | LRU_SET_RESET_VEC_PT[37] | LRU_SET_RESET_VEC_PT[105] | LRU_SET_RESET_VEC_PT[138] | LRU_SET_RESET_VEC_PT[140] | LRU_SET_RESET_VEC_PT[141] | LRU_SET_RESET_VEC_PT[143]); + assign lru_set_vec[6] = (LRU_SET_RESET_VEC_PT[20] | LRU_SET_RESET_VEC_PT[21] | LRU_SET_RESET_VEC_PT[23] | LRU_SET_RESET_VEC_PT[24] | LRU_SET_RESET_VEC_PT[103] | LRU_SET_RESET_VEC_PT[126] | LRU_SET_RESET_VEC_PT[128] | LRU_SET_RESET_VEC_PT[129] | LRU_SET_RESET_VEC_PT[131]); + assign lru_set_vec[7] = (LRU_SET_RESET_VEC_PT[8] | LRU_SET_RESET_VEC_PT[9] | LRU_SET_RESET_VEC_PT[11] | LRU_SET_RESET_VEC_PT[12] | LRU_SET_RESET_VEC_PT[101] | LRU_SET_RESET_VEC_PT[115] | LRU_SET_RESET_VEC_PT[116] | LRU_SET_RESET_VEC_PT[117] | LRU_SET_RESET_VEC_PT[119]); + assign lru_set_vec[8] = (LRU_SET_RESET_VEC_PT[51] | LRU_SET_RESET_VEC_PT[52] | LRU_SET_RESET_VEC_PT[99] | LRU_SET_RESET_VEC_PT[156] | LRU_SET_RESET_VEC_PT[158]); + assign lru_set_vec[9] = (LRU_SET_RESET_VEC_PT[43] | LRU_SET_RESET_VEC_PT[44] | LRU_SET_RESET_VEC_PT[97] | LRU_SET_RESET_VEC_PT[150] | LRU_SET_RESET_VEC_PT[152]); + assign lru_set_vec[10] = (LRU_SET_RESET_VEC_PT[36] | LRU_SET_RESET_VEC_PT[37] | LRU_SET_RESET_VEC_PT[95] | LRU_SET_RESET_VEC_PT[144] | LRU_SET_RESET_VEC_PT[146]); + assign lru_set_vec[11] = (LRU_SET_RESET_VEC_PT[30] | LRU_SET_RESET_VEC_PT[31] | LRU_SET_RESET_VEC_PT[93] | LRU_SET_RESET_VEC_PT[138] | LRU_SET_RESET_VEC_PT[140]); + assign lru_set_vec[12] = (LRU_SET_RESET_VEC_PT[23] | LRU_SET_RESET_VEC_PT[24] | LRU_SET_RESET_VEC_PT[91] | LRU_SET_RESET_VEC_PT[132] | LRU_SET_RESET_VEC_PT[134]); + assign lru_set_vec[13] = (LRU_SET_RESET_VEC_PT[17] | LRU_SET_RESET_VEC_PT[18] | LRU_SET_RESET_VEC_PT[89] | LRU_SET_RESET_VEC_PT[126] | LRU_SET_RESET_VEC_PT[128]); + assign lru_set_vec[14] = (LRU_SET_RESET_VEC_PT[11] | LRU_SET_RESET_VEC_PT[12] | LRU_SET_RESET_VEC_PT[87] | LRU_SET_RESET_VEC_PT[120] | LRU_SET_RESET_VEC_PT[122]); + assign lru_set_vec[15] = (LRU_SET_RESET_VEC_PT[5] | LRU_SET_RESET_VEC_PT[6] | LRU_SET_RESET_VEC_PT[85] | LRU_SET_RESET_VEC_PT[115] | LRU_SET_RESET_VEC_PT[116]); + assign lru_set_vec[16] = (LRU_SET_RESET_VEC_PT[52] | LRU_SET_RESET_VEC_PT[83] | LRU_SET_RESET_VEC_PT[159]); + assign lru_set_vec[17] = (LRU_SET_RESET_VEC_PT[48] | LRU_SET_RESET_VEC_PT[81] | LRU_SET_RESET_VEC_PT[156]); + assign lru_set_vec[18] = (LRU_SET_RESET_VEC_PT[44] | LRU_SET_RESET_VEC_PT[79] | LRU_SET_RESET_VEC_PT[153]); + assign lru_set_vec[19] = (LRU_SET_RESET_VEC_PT[41] | LRU_SET_RESET_VEC_PT[77] | LRU_SET_RESET_VEC_PT[150]); + assign lru_set_vec[20] = (LRU_SET_RESET_VEC_PT[37] | LRU_SET_RESET_VEC_PT[75] | LRU_SET_RESET_VEC_PT[147]); + assign lru_set_vec[21] = (LRU_SET_RESET_VEC_PT[34] | LRU_SET_RESET_VEC_PT[73] | LRU_SET_RESET_VEC_PT[144]); + assign lru_set_vec[22] = (LRU_SET_RESET_VEC_PT[31] | LRU_SET_RESET_VEC_PT[71] | LRU_SET_RESET_VEC_PT[141]); + assign lru_set_vec[23] = (LRU_SET_RESET_VEC_PT[28] | LRU_SET_RESET_VEC_PT[69] | LRU_SET_RESET_VEC_PT[138]); + assign lru_set_vec[24] = (LRU_SET_RESET_VEC_PT[24] | LRU_SET_RESET_VEC_PT[67] | LRU_SET_RESET_VEC_PT[135]); + assign lru_set_vec[25] = (LRU_SET_RESET_VEC_PT[21] | LRU_SET_RESET_VEC_PT[65] | LRU_SET_RESET_VEC_PT[132]); + assign lru_set_vec[26] = (LRU_SET_RESET_VEC_PT[18] | LRU_SET_RESET_VEC_PT[63] | LRU_SET_RESET_VEC_PT[129]); + assign lru_set_vec[27] = (LRU_SET_RESET_VEC_PT[15] | LRU_SET_RESET_VEC_PT[61] | LRU_SET_RESET_VEC_PT[126]); + assign lru_set_vec[28] = (LRU_SET_RESET_VEC_PT[12] | LRU_SET_RESET_VEC_PT[59] | LRU_SET_RESET_VEC_PT[123]); + assign lru_set_vec[29] = (LRU_SET_RESET_VEC_PT[9] | LRU_SET_RESET_VEC_PT[57] | LRU_SET_RESET_VEC_PT[120]); + assign lru_set_vec[30] = (LRU_SET_RESET_VEC_PT[6] | LRU_SET_RESET_VEC_PT[55] | LRU_SET_RESET_VEC_PT[117]); + assign lru_set_vec[31] = (LRU_SET_RESET_VEC_PT[3] | LRU_SET_RESET_VEC_PT[53] | LRU_SET_RESET_VEC_PT[115]); + + // Encoder for the LRU selected entry + // + // Final Table Listing + // *INPUTS*=======================================*OUTPUTS*==========* + // | | | + // | mmucr1_q | lru_way_encode | + // | | lru_eff | | | + // | | | | | | + // | | | | | | + // | | | 1111111111222222222233 | | | + // | 012345678 1234567890123456789012345678901 | 01234 | + // *TYPE*=========================================+==================+ + // | PPPPPPPPP PPPPPPPPPPPPPPPPPPPPPPPPPPPPPPP | PPPPP | + // *POLARITY*------------------------------------>| +++++ | + // *PHASE*--------------------------------------->| TTTTT | + // *OPTIMIZE*------------------------------------>| AAAAA | + // *TERMS*========================================+==================+ + // 1 | --------- 1-1---1-------1---------------1 | ....1 | + // 2 | --------- 1-1---1-------0--------------1- | ....1 | + // 3 | --------- 1-1---0------1--------------1-- | ....1 | + // 4 | --------- 1-1---0------0-------------1--- | ....1 | + // 5 | --------- 1-0--1------1-------------1---- | ....1 | + // 6 | --------- 1-0--1------0------------1----- | ....1 | + // 7 | --------- 1-0--0-----1------------1------ | ....1 | + // 8 | --------- 1-0--0-----0-----------1------- | ....1 | + // 9 | --------- 01--1-----1-----------1-------- | ....1 | + // 10 | --------- 01--1-----0----------1--------- | ....1 | + // 11 | --------- 01--0----1----------1---------- | ....1 | + // 12 | --------- 01--0----0---------1----------- | ....1 | + // 13 | --------- 00-1----1---------1------------ | ....1 | + // 14 | --------- 00-1----0--------1------------- | ....1 | + // 15 | --------- 00-0---1--------1-------------- | ....1 | + // 16 | --------- 00-0---0-------1--------------- | ....1 | + // 17 | --------- 1-1---1-------1---------------- | ...1. | + // 18 | --------- 1-1---0------1----------------- | ...1. | + // 19 | --------- 1-0--1------1------------------ | ...1. | + // 20 | --------- 1-0--0-----1------------------- | ...1. | + // 21 | --------- 01--1-----1-------------------- | ...1. | + // 22 | --------- 01--0----1--------------------- | ...1. | + // 23 | --------- 00-1----1---------------------- | ...1. | + // 24 | --------- 00-0---1----------------------- | ...1. | + // 25 | --------- 1-1---1------------------------ | ..1.. | + // 26 | --------- 1-0--1------------------------- | ..1.. | + // 27 | --------- 01--1-------------------------- | ..1.. | + // 28 | --------- 00-1--------------------------- | ..1.. | + // 29 | --------- 1-1---------------------------- | .1... | + // 30 | --------- 01----------------------------- | .1... | + // 31 | --------- 1------------------------------ | 1.... | + // *=================================================================* + // + // Table LRU_WAY_ENCODE Signal Assignments for Product Terms + assign LRU_WAY_ENCODE_PT[1] = (({lru_eff[1], lru_eff[3], lru_eff[7], lru_eff[15], lru_eff[31]}) == 5'b11111); + assign LRU_WAY_ENCODE_PT[2] = (({lru_eff[1], lru_eff[3], lru_eff[7], lru_eff[15], lru_eff[30]}) == 5'b11101); + assign LRU_WAY_ENCODE_PT[3] = (({lru_eff[1], lru_eff[3], lru_eff[7], lru_eff[14], lru_eff[29]}) == 5'b11011); + assign LRU_WAY_ENCODE_PT[4] = (({lru_eff[1], lru_eff[3], lru_eff[7], lru_eff[14], lru_eff[28]}) == 5'b11001); + assign LRU_WAY_ENCODE_PT[5] = (({lru_eff[1], lru_eff[3], lru_eff[6], lru_eff[13], lru_eff[27]}) == 5'b10111); + assign LRU_WAY_ENCODE_PT[6] = (({lru_eff[1], lru_eff[3], lru_eff[6], lru_eff[13], lru_eff[26]}) == 5'b10101); + assign LRU_WAY_ENCODE_PT[7] = (({lru_eff[1], lru_eff[3], lru_eff[6], lru_eff[12], lru_eff[25]}) == 5'b10011); + assign LRU_WAY_ENCODE_PT[8] = (({lru_eff[1], lru_eff[3], lru_eff[6], lru_eff[12], lru_eff[24]}) == 5'b10001); + assign LRU_WAY_ENCODE_PT[9] = (({lru_eff[1], lru_eff[2], lru_eff[5], lru_eff[11], lru_eff[23]}) == 5'b01111); + assign LRU_WAY_ENCODE_PT[10] = (({lru_eff[1], lru_eff[2], lru_eff[5], lru_eff[11], lru_eff[22]}) == 5'b01101); + assign LRU_WAY_ENCODE_PT[11] = (({lru_eff[1], lru_eff[2], lru_eff[5], lru_eff[10], lru_eff[21]}) == 5'b01011); + assign LRU_WAY_ENCODE_PT[12] = (({lru_eff[1], lru_eff[2], lru_eff[5], lru_eff[10], lru_eff[20]}) == 5'b01001); + assign LRU_WAY_ENCODE_PT[13] = (({lru_eff[1], lru_eff[2], lru_eff[4], lru_eff[9], lru_eff[19]}) == 5'b00111); + assign LRU_WAY_ENCODE_PT[14] = (({lru_eff[1], lru_eff[2], lru_eff[4], lru_eff[9], lru_eff[18]}) == 5'b00101); + assign LRU_WAY_ENCODE_PT[15] = (({lru_eff[1], lru_eff[2], lru_eff[4], lru_eff[8], lru_eff[17]}) == 5'b00011); + assign LRU_WAY_ENCODE_PT[16] = (({lru_eff[1], lru_eff[2], lru_eff[4], lru_eff[8], lru_eff[16]}) == 5'b00001); + assign LRU_WAY_ENCODE_PT[17] = (({lru_eff[1], lru_eff[3], lru_eff[7], lru_eff[15]}) == 4'b1111); + assign LRU_WAY_ENCODE_PT[18] = (({lru_eff[1], lru_eff[3], lru_eff[7], lru_eff[14]}) == 4'b1101); + assign LRU_WAY_ENCODE_PT[19] = (({lru_eff[1], lru_eff[3], lru_eff[6], lru_eff[13]}) == 4'b1011); + assign LRU_WAY_ENCODE_PT[20] = (({lru_eff[1], lru_eff[3], lru_eff[6], lru_eff[12]}) == 4'b1001); + assign LRU_WAY_ENCODE_PT[21] = (({lru_eff[1], lru_eff[2], lru_eff[5], lru_eff[11]}) == 4'b0111); + assign LRU_WAY_ENCODE_PT[22] = (({lru_eff[1], lru_eff[2], lru_eff[5], lru_eff[10]}) == 4'b0101); + assign LRU_WAY_ENCODE_PT[23] = (({lru_eff[1], lru_eff[2], lru_eff[4], lru_eff[9]}) == 4'b0011); + assign LRU_WAY_ENCODE_PT[24] = (({lru_eff[1], lru_eff[2], lru_eff[4], lru_eff[8]}) == 4'b0001); + assign LRU_WAY_ENCODE_PT[25] = (({lru_eff[1], lru_eff[3], lru_eff[7]}) == 3'b111); + assign LRU_WAY_ENCODE_PT[26] = (({lru_eff[1], lru_eff[3], lru_eff[6]}) == 3'b101); + assign LRU_WAY_ENCODE_PT[27] = (({lru_eff[1], lru_eff[2], lru_eff[5]}) == 3'b011); + assign LRU_WAY_ENCODE_PT[28] = (({lru_eff[1], lru_eff[2], lru_eff[4]}) == 3'b001); + assign LRU_WAY_ENCODE_PT[29] = (({lru_eff[1], lru_eff[3]}) == 2'b11); + assign LRU_WAY_ENCODE_PT[30] = (({lru_eff[1], lru_eff[2]}) == 2'b01); + assign LRU_WAY_ENCODE_PT[31] = ((lru_eff[1]) == 1'b1); + // Table LRU_WAY_ENCODE Signal Assignments for Outputs + assign lru_way_encode[0] = (LRU_WAY_ENCODE_PT[31]); + assign lru_way_encode[1] = (LRU_WAY_ENCODE_PT[29] | LRU_WAY_ENCODE_PT[30]); + assign lru_way_encode[2] = (LRU_WAY_ENCODE_PT[25] | LRU_WAY_ENCODE_PT[26] | LRU_WAY_ENCODE_PT[27] | LRU_WAY_ENCODE_PT[28]); + assign lru_way_encode[3] = (LRU_WAY_ENCODE_PT[17] | LRU_WAY_ENCODE_PT[18] | LRU_WAY_ENCODE_PT[19] | LRU_WAY_ENCODE_PT[20] | LRU_WAY_ENCODE_PT[21] | LRU_WAY_ENCODE_PT[22] | LRU_WAY_ENCODE_PT[23] | LRU_WAY_ENCODE_PT[24]); + assign lru_way_encode[4] = (LRU_WAY_ENCODE_PT[1] | LRU_WAY_ENCODE_PT[2] | LRU_WAY_ENCODE_PT[3] | LRU_WAY_ENCODE_PT[4] | LRU_WAY_ENCODE_PT[5] | LRU_WAY_ENCODE_PT[6] | LRU_WAY_ENCODE_PT[7] | LRU_WAY_ENCODE_PT[8] | LRU_WAY_ENCODE_PT[9] | LRU_WAY_ENCODE_PT[10] | LRU_WAY_ENCODE_PT[11] | LRU_WAY_ENCODE_PT[12] | LRU_WAY_ENCODE_PT[13] | LRU_WAY_ENCODE_PT[14] | LRU_WAY_ENCODE_PT[15] | LRU_WAY_ENCODE_PT[16]); + + // power-on reset sequencer to load initial erat entries + + always @(por_seq_q or init_alias or bcfg_q[0:106]) + begin: Por_Sequencer + por_wr_cam_val = {2{1'b0}}; + por_wr_array_val = {2{1'b0}}; + por_wr_cam_data = {cam_data_width{1'b0}}; + por_wr_array_data = {array_data_width{1'b0}}; + por_wr_entry = {num_entry_log2{1'b0}}; + case (por_seq_q) + PorSeq_Idle : + begin + por_wr_cam_val = {2{1'b0}}; + por_wr_array_val = {2{1'b0}}; + por_hold_req = {`THREADS{init_alias}}; + + if (init_alias == 1'b1) + por_seq_d = PorSeq_Stg1; + else + por_seq_d = PorSeq_Idle; + end + PorSeq_Stg1 : + begin + por_wr_cam_val = {2{1'b0}}; + por_wr_array_val = {2{1'b0}}; + por_seq_d = PorSeq_Stg2; + por_hold_req = {`THREADS{1'b1}}; + end + + PorSeq_Stg2 : + begin + por_wr_cam_val = {2{1'b1}}; + por_wr_array_val = {2{1'b1}}; + por_wr_entry = Por_Wr_Entry_Num1; + por_wr_cam_data = {bcfg_q[0:51], Por_Wr_Cam_Data1[52:83]}; + // 16x143 version, 42b RA + // wr_array_data + // 0:29 - RPN + // 30:31 - R,C + // 32:35 - ResvAttr + // 36:39 - U0-U3 + // 40:44 - WIMGE + // 45:46 - UX,SX + // 47:48 - UW,SW + // 49:50 - UR,SR + // 51:60 - CAM parity + // 61:67 - Array parity + por_wr_array_data = {bcfg_q[52:81], Por_Wr_Array_Data1[30:35], bcfg_q[82:85], Por_Wr_Array_Data1[40:43], bcfg_q[86], Por_Wr_Array_Data1[45:67]}; + por_hold_req = {`THREADS{1'b1}}; + por_seq_d = PorSeq_Stg3; + end + + PorSeq_Stg3 : + begin + por_wr_cam_val = {2{1'b0}}; + por_wr_array_val = {2{1'b0}}; + por_hold_req = {`THREADS{1'b1}}; + por_seq_d = PorSeq_Stg4; + end + + PorSeq_Stg4 : + begin + por_wr_cam_val = {2{1'b1}}; + por_wr_array_val = {2{1'b1}}; + por_wr_entry = Por_Wr_Entry_Num2; + por_wr_cam_data = Por_Wr_Cam_Data2; + por_wr_array_data = {bcfg_q[52:61], bcfg_q[87:106], Por_Wr_Array_Data2[30:35], bcfg_q[82:85], Por_Wr_Array_Data2[40:43], bcfg_q[86], Por_Wr_Array_Data2[45:67]}; + por_hold_req = {`THREADS{1'b1}}; + por_seq_d = PorSeq_Stg5; + end + + PorSeq_Stg5 : + begin + por_wr_cam_val = {2{1'b0}}; + por_wr_array_val = {2{1'b0}}; + por_hold_req = {`THREADS{1'b1}}; + por_seq_d = PorSeq_Stg6; + end + + PorSeq_Stg6 : + begin + por_wr_cam_val = {2{1'b0}}; + por_wr_array_val = {2{1'b0}}; + por_hold_req = {`THREADS{1'b0}}; + por_seq_d = PorSeq_Stg7; + end + + PorSeq_Stg7 : + begin + por_wr_cam_val = {2{1'b0}}; + por_wr_array_val = {2{1'b0}}; + por_hold_req = {`THREADS{1'b0}}; + if (init_alias == 1'b0) + por_seq_d = PorSeq_Idle; + else + por_seq_d = PorSeq_Stg7; + end + + default : + por_seq_d = PorSeq_Idle; + endcase + end + // page size 4b to 3b swizzles for cam write + assign cam_pgsize[0:2] = (CAM_PgSize_1GB & ({3{(ex2_data_in_q[56:59] == WS0_PgSize_1GB)}})) | + (CAM_PgSize_16MB & ({3{(ex2_data_in_q[56:59] == WS0_PgSize_16MB)}})) | + (CAM_PgSize_1MB & ({3{(ex2_data_in_q[56:59] == WS0_PgSize_1MB)}})) | + (CAM_PgSize_64KB & ({3{(ex2_data_in_q[56:59] == WS0_PgSize_64KB)}})) | + (CAM_PgSize_4KB & ({3{(~((ex2_data_in_q[56:59] == WS0_PgSize_1GB) | + (ex2_data_in_q[56:59] == WS0_PgSize_16MB) | + (ex2_data_in_q[56:59] == WS0_PgSize_1MB) | + (ex2_data_in_q[56:59] == WS0_PgSize_64KB)))}})); + // page size 3b to 4b swizzles for cam read + assign ws0_pgsize[0:3] = (WS0_PgSize_1GB & ({4{(ex4_rd_cam_data_q[53:55] == CAM_PgSize_1GB)}})) | + (WS0_PgSize_16MB & ({4{(ex4_rd_cam_data_q[53:55] == CAM_PgSize_16MB)}})) | + (WS0_PgSize_1MB & ({4{(ex4_rd_cam_data_q[53:55] == CAM_PgSize_1MB)}})) | + (WS0_PgSize_64KB & ({4{(ex4_rd_cam_data_q[53:55] == CAM_PgSize_64KB)}})) | + (WS0_PgSize_4KB & ({4{(ex4_rd_cam_data_q[53:55] == CAM_PgSize_4KB)}})); + // CAM control signal assignments + assign rd_val = (|(ex2_valid_op_q & (~cp_flush_q))) & ex2_ttype_q[0] & (ex2_tlbsel_q == TlbSel_DErat); + assign rw_entry = (por_wr_entry & ({5{(|(por_seq_q))}})) | + (eptr_q & ({5{(|(tlb_rel_val_q[0:3]) & tlb_rel_val_q[4] & mmucr1_q[0])}})) | + (lru_way_encode & ({5{(|(tlb_rel_val_q[0:3]) & tlb_rel_val_q[4] & (~mmucr1_q[0]))}})) | + (eptr_q & ({5{(|(ex2_valid_op_q) & ex2_ttype_q[1] & (ex2_tlbsel_q == TlbSel_DErat) & (~tlb_rel_val_q[4]) & mmucr1_q[0])}})) | + (ex2_ra_entry_q & ({5{(|(ex2_valid_op_q) & ex2_ttype_q[1] & (ex2_tlbsel_q == TlbSel_DErat) & (~tlb_rel_val_q[4]) & (~mmucr1_q[0]))}})) | + (ex2_ra_entry_q & ({5{(|(ex2_valid_op_q) & ex2_ttype_q[0] & (~tlb_rel_val_q[4]))}})); + // Write Port + assign wr_cam_val = (por_seq_q != PorSeq_Idle) ? por_wr_cam_val : + ((csinv_complete == 1'b1)) ? {2{1'b0}} : + ((tlb_rel_val_q[0:3] != 4'b0000 & tlb_rel_val_q[4] == 1'b1)) ? {2{tlb_rel_data_q[eratpos_wren]}} : + ((|(ex2_valid_op_q) == 1'b1 & ex2_ttype_q[1] == 1'b1 & ex2_ws_q == 2'b00 & ex2_tlbsel_q == TlbSel_DErat)) ? {2{1'b1}} : + {2{1'b0}}; + // write port act pin + assign wr_val_early = (|(por_seq_q)) | tlb_req_inprogress_q | (|(ex1_valid_op_q) & ex1_ttype03_q[1]) | (|(ex2_valid_op_q) & ex2_ttype_q[1]); + // state <= PR & GS or mmucr0(8) & IS or mmucr0(9) & CM + // tlb_low_data + // 0:51 - EPN + // 52:55 - SIZE (4b) + // 56:59 - ThdID + // 60:61 - Class + // 62 - ExtClass + // 63 - TID_NZ + // 64:65 - reserved (2b) + // 66:73 - 8b for LPID + // 74:83 - parity 10bits + // wr_ws0_data (LO) + // 0:51 - EPN + // 52:53 - Class + // 54 - V + // 55 - X + // 56:59 - SIZE + // 60:63 - ThdID + // wr_cam_data + // 0:51 - EPN + // 52 - X + // 53:55 - SIZE + // 56 - V + // 57:60 - ThdID + // 61:62 - Class + // 63:64 - ExtClass | TID_NZ + // 65 - TGS + // 66 - TS + // 67:74 - TID + // 75:78 - epn_cmpmasks: 34_39, 40_43, 44_47, 48_51 + // 79:82 - xbit_cmpmasks: 34_51, 40_51, 44_51, 48_51 + // 83 - parity for 75:82 + //--------- this is what the erat expects on reload bus + // 0:51 - EPN + // 52 - X + // 53:55 - SIZE + // 56 - V + // 57:60 - ThdID + // 61:62 - Class + // 63:64 - ExtClass | TID_NZ + // 65 - write enable + // 0:3 66:69 - reserved RPN + // 4:33 70:99 - RPN + // 34:35 100:101 - R,C + // 36 102 - reserved + // 37:38 103:104 - WLC + // 39 105 - ResvAttr + // 40 106 - VF + // 41:44 107:110 - U0-U3 + // 45:49 111:115 - WIMGE + // 50:51 116:117 - UX,SX + // 52:53 118:119 - UW,SW + // 54:55 120:121 - UR,SR + // 56 122 - GS + // 57 123 - TS + // 58:65 124:131 - TID lsbs + + generate + if (GPR_WIDTH == 64) + begin : gen64_wr_cam_data + assign wr_cam_data = (por_wr_cam_data & {84{(por_seq_q[0] | por_seq_q[1] | por_seq_q[2])}}) | + (({tlb_rel_data_q[0:64], tlb_rel_data_q[122:131], tlb_rel_cmpmask[0:3], tlb_rel_xbitmask[0:3], tlb_rel_maskpar}) & + ({84{((tlb_rel_val_q[0] | tlb_rel_val_q[1] | tlb_rel_val_q[2] | tlb_rel_val_q[3]) & tlb_rel_val_q[4])}})) | + (({(ex2_data_in_q[0:31] & ({32{ex2_state_q[3]}})), ex2_data_in_q[32:51], + ex2_data_in_q[55], cam_pgsize[0:2], ex2_data_in_q[54], + (({ex2_data_in_q[60:61], 2'b00} & {4{~(mmucr1_q[8])}}) | (ex2_pid_q[pid_width-12 : pid_width-9] & {4{mmucr1_q[8]}})), + (( ex2_data_in_q[52:53] & {2{~(mmucr1_q[7])}}) | (ex2_pid_q[pid_width-14 : pid_width-13] & {2{mmucr1_q[7]}})), + ex2_extclass_q, ex2_state_q[1:2], ex2_pid_q[pid_width - 8:pid_width - 1], + ex2_data_cmpmask[0:3], ex2_data_xbitmask[0:3], ex2_data_maskpar}) & + ({84{(|(ex2_valid_op_q) & ex2_ttype_q[1] & (~ex2_ws_q[0]) & (~ex2_ws_q[1]) & (~tlb_rel_val_q[4]))}})); + end + endgenerate + + generate + if (GPR_WIDTH == 32) + begin : gen32_wr_cam_data + assign wr_cam_data = (por_wr_cam_data & ({84{(por_seq_q[0] | por_seq_q[1] | por_seq_q[2])}})) | + (({tlb_rel_data_q[0:64], tlb_rel_data_q[122:131], tlb_rel_cmpmask[0:3], tlb_rel_xbitmask[0:3], tlb_rel_maskpar}) & + ({84{((tlb_rel_val_q[0] | tlb_rel_val_q[1] | tlb_rel_val_q[2] | tlb_rel_val_q[3]) & tlb_rel_val_q[4])}})) | + (({({32{1'b0}}), ex2_data_in_q[32:51], ex2_data_in_q[55], cam_pgsize[0:2], ex2_data_in_q[54], + (({ex2_data_in_q[60:61], 2'b00} & {4{~(mmucr1_q[8])}}) | (ex2_pid_q[pid_width-12 : pid_width-9] & {4{(mmucr1_q[8])}})), + (( ex2_data_in_q[52:53] & {2{~(mmucr1_q[7])}}) | (ex2_pid_q[pid_width-14 : pid_width-13] & {2{(mmucr1_q[7])}})), + ex2_extclass_q, ex2_state_q[1:2], ex2_pid_q[pid_width - 8:pid_width - 1], ex2_data_cmpmask[0:3], ex2_data_xbitmask[0:3], ex2_data_maskpar}) & + ({84{(|(ex2_valid_op_q) & ex2_ttype_q[1] & (~ex2_ws_q[0]) & (~ex2_ws_q[1]) & (~tlb_rel_val_q[4]))}})); + end + endgenerate + + // wr_cam_data(75) (76) (77) (78) (79) (80) (81) (82) + // cmpmask(0) (1) (2) (3) xbitmask(0) (1) (2) (3) + // xbit pgsize 34_39 40_43 44_47 48_51 34_39 40_43 44_47 48_51 size + // 0 001 1 1 1 1 0 0 0 0 4K + // 0 011 1 1 1 0 0 0 0 0 64K + // 0 101 1 1 0 0 0 0 0 0 1M + // 0 111 1 0 0 0 0 0 0 0 16M + // 0 110 0 0 0 0 0 0 0 0 1G + // 1 001 1 1 1 1 0 0 0 0 4K + // 1 011 1 1 1 0 0 0 0 1 64K + // 1 101 1 1 0 0 0 0 1 0 1M + // 1 111 1 0 0 0 0 1 0 0 16M + // 1 110 0 0 0 0 1 0 0 0 1G + // Encoder for the cam compare mask bits write data + // + // Final Table Listing + // *INPUTS*==================*OUTPUTS*===================================* + // | | | + // | tlb_rel_data_q | tlb_rel_cmpmask | + // | | ex2_data_in_q | | tlb_rel_xbitmask | + // | | | | | | tlb_rel_maskpar | + // | | | | | | | ex2_data_cmpmask | + // | | | | | | | | ex2_data_xbitmask | + // | | | | | | | | | ex2_data_maskpar | + // | | | | | | | | | | | + // | 5555 55555 | | | | | | | | + // | 2345 56789 | 0123 0123 | 0123 0123 | | + // *TYPE*====================+===========================================+ + // | PPPP PPPPP | PPPP PPPP P PPPP PPPP P | + // *POLARITY*--------------->| ++++ ++++ + ++++ ++++ + | + // *PHASE*------------------>| TTTT TTTT T TTTT TTTT T | + // *OPTIMIZE*--------------->| AAAA AAAA A AAAA AAAA A | + // *TERMS*===================+===========================================+ + // 1 | ---- 11010 | .... .... . .... 1... 1 | + // 2 | ---- -0--0 | .... .... . 1111 .... . | + // 3 | ---- 10101 | .... .... . .... ..1. 1 | + // 4 | ---- 10011 | .... .... . 1... ...1 . | + // 5 | ---- 10111 | .... .... . 1... .1.. . | + // 6 | ---- 00-11 | .... .... . 1... .... 1 | + // 7 | ---- -1--1 | .... .... . 1111 .... . | + // 8 | ---- --00- | .... .... . ..11 .... . | + // 9 | ---- ---0- | .... .... . 11.. .... . | + // 10 | ---- -00-- | .... .... . .11. .... . | + // 11 | ---- -11-- | .... .... . 1111 .... . | + // 12 | 1--0 ----- | .... 1... 1 .... .... . | + // 13 | 1111 ----- | 1... .1.. . .... .... . | + // 14 | 0-11 ----- | 1... .... 1 .... .... . | + // 15 | -00- ----- | ...1 .... . .... .... . | + // 16 | 110- ----- | .... ..1. 1 .... .... . | + // 17 | --0- ----- | 11.. .... . .... .... . | + // 18 | 101- ----- | 1... ...1 . .... .... . | + // 19 | -0-- ----- | .11. .... . .... .... . | + // *=====================================================================* + // + // Table CAM_MASK_BITS Signal Assignments for Product Terms + assign CAM_MASK_BITS_PT[1] = (({ex2_data_in_q[55], ex2_data_in_q[56], ex2_data_in_q[57], ex2_data_in_q[58], ex2_data_in_q[59]}) == 5'b11010); + assign CAM_MASK_BITS_PT[2] = (({ex2_data_in_q[56], ex2_data_in_q[59]}) == 2'b00); + assign CAM_MASK_BITS_PT[3] = (({ex2_data_in_q[55], ex2_data_in_q[56], ex2_data_in_q[57], ex2_data_in_q[58], ex2_data_in_q[59]}) == 5'b10101); + assign CAM_MASK_BITS_PT[4] = (({ex2_data_in_q[55], ex2_data_in_q[56], ex2_data_in_q[57], ex2_data_in_q[58], ex2_data_in_q[59]}) == 5'b10011); + assign CAM_MASK_BITS_PT[5] = (({ex2_data_in_q[55], ex2_data_in_q[56], ex2_data_in_q[57], ex2_data_in_q[58], ex2_data_in_q[59]}) == 5'b10111); + assign CAM_MASK_BITS_PT[6] = (({ex2_data_in_q[55], ex2_data_in_q[56], ex2_data_in_q[58], ex2_data_in_q[59]}) == 4'b0011); + assign CAM_MASK_BITS_PT[7] = (({ex2_data_in_q[56], ex2_data_in_q[59]}) == 2'b11); + assign CAM_MASK_BITS_PT[8] = (({ex2_data_in_q[57], ex2_data_in_q[58]}) == 2'b00); + assign CAM_MASK_BITS_PT[9] = ((ex2_data_in_q[58]) == 1'b0); + assign CAM_MASK_BITS_PT[10] = (({ex2_data_in_q[56], ex2_data_in_q[57]}) == 2'b00); + assign CAM_MASK_BITS_PT[11] = (({ex2_data_in_q[56], ex2_data_in_q[57]}) == 2'b11); + assign CAM_MASK_BITS_PT[12] = (({tlb_rel_data_q[52], tlb_rel_data_q[55]}) == 2'b10); + assign CAM_MASK_BITS_PT[13] = (({tlb_rel_data_q[52], tlb_rel_data_q[53], tlb_rel_data_q[54], tlb_rel_data_q[55]}) == 4'b1111); + assign CAM_MASK_BITS_PT[14] = (({tlb_rel_data_q[52], tlb_rel_data_q[54], tlb_rel_data_q[55]}) == 3'b011); + assign CAM_MASK_BITS_PT[15] = (({tlb_rel_data_q[53], tlb_rel_data_q[54]}) == 2'b00); + assign CAM_MASK_BITS_PT[16] = (({tlb_rel_data_q[52], tlb_rel_data_q[53], tlb_rel_data_q[54]}) == 3'b110); + assign CAM_MASK_BITS_PT[17] = ((tlb_rel_data_q[54]) == 1'b0); + assign CAM_MASK_BITS_PT[18] = (({tlb_rel_data_q[52], tlb_rel_data_q[53], tlb_rel_data_q[54]}) == 3'b101); + assign CAM_MASK_BITS_PT[19] = ((tlb_rel_data_q[53]) == 1'b0); + // Table CAM_MASK_BITS Signal Assignments for Outputs + assign tlb_rel_cmpmask[0] = (CAM_MASK_BITS_PT[13] | CAM_MASK_BITS_PT[14] | CAM_MASK_BITS_PT[17] | CAM_MASK_BITS_PT[18]); + assign tlb_rel_cmpmask[1] = (CAM_MASK_BITS_PT[17] | CAM_MASK_BITS_PT[19]); + assign tlb_rel_cmpmask[2] = (CAM_MASK_BITS_PT[19]); + assign tlb_rel_cmpmask[3] = (CAM_MASK_BITS_PT[15]); + assign tlb_rel_xbitmask[0] = (CAM_MASK_BITS_PT[12]); + assign tlb_rel_xbitmask[1] = (CAM_MASK_BITS_PT[13]); + assign tlb_rel_xbitmask[2] = (CAM_MASK_BITS_PT[16]); + assign tlb_rel_xbitmask[3] = (CAM_MASK_BITS_PT[18]); + assign tlb_rel_maskpar = (CAM_MASK_BITS_PT[12] | CAM_MASK_BITS_PT[14] | CAM_MASK_BITS_PT[16]); + assign ex2_data_cmpmask[0] = (CAM_MASK_BITS_PT[2] | CAM_MASK_BITS_PT[4] | CAM_MASK_BITS_PT[5] | CAM_MASK_BITS_PT[6] | CAM_MASK_BITS_PT[7] | CAM_MASK_BITS_PT[9] | CAM_MASK_BITS_PT[11]); + assign ex2_data_cmpmask[1] = (CAM_MASK_BITS_PT[2] | CAM_MASK_BITS_PT[7] | CAM_MASK_BITS_PT[9] | CAM_MASK_BITS_PT[10] | CAM_MASK_BITS_PT[11]); + assign ex2_data_cmpmask[2] = (CAM_MASK_BITS_PT[2] | CAM_MASK_BITS_PT[7] | CAM_MASK_BITS_PT[8] | CAM_MASK_BITS_PT[10] | CAM_MASK_BITS_PT[11]); + assign ex2_data_cmpmask[3] = (CAM_MASK_BITS_PT[2] | CAM_MASK_BITS_PT[7] | CAM_MASK_BITS_PT[8] | CAM_MASK_BITS_PT[11]); + assign ex2_data_xbitmask[0] = (CAM_MASK_BITS_PT[1]); + assign ex2_data_xbitmask[1] = (CAM_MASK_BITS_PT[5]); + assign ex2_data_xbitmask[2] = (CAM_MASK_BITS_PT[3]); + assign ex2_data_xbitmask[3] = (CAM_MASK_BITS_PT[4]); + assign ex2_data_maskpar = (CAM_MASK_BITS_PT[1] | CAM_MASK_BITS_PT[3] | CAM_MASK_BITS_PT[6]); + + assign wr_array_val = (por_seq_q != PorSeq_Idle) ? por_wr_array_val : + ((csinv_complete == 1'b1)) ? 2'b00 : + ((tlb_rel_val_q[0:3] != 4'b0000 & tlb_rel_val_q[4] == 1'b1)) ? {2{tlb_rel_data_q[eratpos_wren]}} : + ((((|(ex2_valid_op_q)) == 1'b1) & ex2_ttype_q[1] == 1'b1 & ex2_ws_q == 2'b00 & ex2_tlbsel_q == TlbSel_DErat)) ? 2'b11 : + 2'b00; + + // tlb_high_data + // 84 - 0 - X-bit + // 85:87 - 1:3 - reserved (3b) + // 88:117 - 4:33 - RPN (30b) + // 118:119 - 34:35 - R,C + // 120:121 - 36:37 - WLC (2b) + // 122 - 38 - ResvAttr + // 123 - 39 - VF + // 124 - 40 - IND + // 125:128 - 41:44 - U0-U3 + // 129:133 - 45:49 - WIMGE + // 134:136 - 50:52 - UX,UW,UR + // 137:139 - 53:55 - SX,SW,SR + // 140 - 56 - GS + // 141 - 57 - TS + // 142:143 - 58:59 - reserved (2b) + // 144:149 - 60:65 - 6b TID msbs + // 150:157 - 66:73 - 8b TID lsbs + // 158:167 - 74:83 - parity 10bits + // 16x143 version, 42b RA + // wr_array_data + // 0:29 - RPN + // 30:31 - R,C + // 32:35 - ResvAttr + // 36:39 - U0-U3 + // 40:44 - WIMGE + // 45:46 - UX,SX + // 47:48 - UW,SW + // 49:50 - UR,SR + // 51:60 - CAM parity + // 61:67 - Array parity + // wr_ws1_data (HI) + // 0:7 - unused + // 8:9 - WLC + // 10 - ResvAttr + // 11 - unused + // 12:15 - U0-U3 + // 16:17 - R,C + // 18:21 - unused + // 22:51 - RPN + // 52:56 - WIMGE + // 57 - VF + // 58:59 - UX,SX + // 60:61 - UW,SW + // 62:63 - UR,SR + assign wr_array_data_nopar = (por_wr_array_data[0:50] & ({51{(por_seq_q[0] | por_seq_q[1] | por_seq_q[2])}})) | + (({tlb_rel_data_q[70:101], tlb_rel_data_q[103:121]}) & ({51{((tlb_rel_val_q[0] | tlb_rel_val_q[1] | tlb_rel_val_q[2] | tlb_rel_val_q[3]) & tlb_rel_val_q[4])}})) | + (({ex2_rpn_holdreg[22:51], ex2_rpn_holdreg[16:17], ex2_rpn_holdreg[8:10], ex2_rpn_holdreg[57], ex2_rpn_holdreg[12:15], ex2_rpn_holdreg[52:56], ex2_rpn_holdreg[58:63]}) & + ({51{(|(ex2_valid_op_q) & ex2_ttype_q[1] & (~ex2_ws_q[0]) & (~ex2_ws_q[1]) & (~tlb_rel_val_q[4]))}})); + // wr_cam_val(0) -> epn(0:51), xbit, size(0:2), V, ThdID(0:3), class(0:1), array_dat(51:58) + // epn(0:7) - wr_cam_data 0:7 - wr_array_par(51) + // epn(8:15) - wr_cam_data 8:15 - wr_array_par(52) + // epn(16:23) - wr_cam_data 16:23 - wr_array_par(53) + // epn(24:31) - wr_cam_data 24:31 - wr_array_par(54) + // epn(32:39) - wr_cam_data 32:39 - wr_array_par(55) + // epn(40:47) - wr_cam_data 40:47 - wr_array_par(56) + // epn(48:51),xbit,size(0:2) - wr_cam_data 48:55 - wr_array_par(57) + // V,ThdID(0:3),class(0:1) - wr_cam_data 56:62 - wr_array_par(58) + assign wr_array_par[51] = ^(wr_cam_data[0:7]); + assign wr_array_par[52] = ^(wr_cam_data[8:15]); + assign wr_array_par[53] = ^(wr_cam_data[16:23]); + assign wr_array_par[54] = ^(wr_cam_data[24:31]); + assign wr_array_par[55] = ^(wr_cam_data[32:39]); + assign wr_array_par[56] = ^(wr_cam_data[40:47]); + assign wr_array_par[57] = ^(wr_cam_data[48:55]); + assign wr_array_par[58] = ^(wr_cam_data[57:62]); + // wr_cam_val(1) -> extclass, tid_nz, gs, as, tid(6:13), array_dat(59:60) + // extclass,tid_nz,gs,as - wr_cam_data 63:66 - wr_array_par(59) + // tid(6:13) - wr_cam_data 67:74 - wr_array_par(60) + assign wr_array_par[59] = ^(wr_cam_data[63:66]); + assign wr_array_par[60] = ^(wr_cam_data[67:74]); + // wr_array_val(0) -> rpn(22:51), array_dat(61:64) + // rpn(22:27) - wr_array_data 0:5 - wr_array_par(61) + // rpn(28:35) - wr_array_data 6:13 - wr_array_par(62) + // rpn(36:43) - wr_array_data 14:21 - wr_array_par(63) + // rpn(44:51) - wr_array_data 22:29 - wr_array_par(64) + assign wr_array_par[61] = ^(wr_array_data_nopar[0:5]); + assign wr_array_par[62] = ^(wr_array_data_nopar[6:13]); + assign wr_array_par[63] = ^(wr_array_data_nopar[14:21]); + assign wr_array_par[64] = ^(wr_array_data_nopar[22:29]); + // wr_array_val(1) -> R,C, WLC(0:1), resvattr, VF, ubits(0:3), wimge(0:4), UX,SX,UW,SW,UR,SR, array_dat(65:67) + // R,C,WLC(0:1),resvattr,VF,ubits(0:1) - wr_array_data 30:37 - wr_array_par(65) + // ubits(2:3),WIMGE(0:4) - wr_array_data 38:44 - wr_array_par(66) + // UX,SX,UW,SW,UR,SR - wr_array_data 45:50 - wr_array_par(67) + assign wr_array_par[65] = ^(wr_array_data_nopar[30:37]); + assign wr_array_par[66] = ^(wr_array_data_nopar[38:44]); + assign wr_array_par[67] = ^(wr_array_data_nopar[45:50]); + assign wr_array_data[0:50] = wr_array_data_nopar; + assign wr_array_data[51:67] = (((tlb_rel_val_q[0:3] != 4'b0000 & tlb_rel_val_q[4] == 1'b1) | por_seq_q != PorSeq_Idle)) ? ({wr_array_par[51:60], wr_array_par[61:67]}) : + ((|(ex2_valid_op_q) == 1'b1 & ex2_ttype_q[1] == 1'b1 & ex2_ws_q == 2'b00)) ? ({(wr_array_par[51] ^ mmucr1_q[5]), wr_array_par[52:60], (wr_array_par[61] ^ mmucr1_q[6]), wr_array_par[62:67]}) : + {17{1'b0}}; + // Parity Checking + assign ex4_rd_data_calc_par[50] = ^(ex4_rd_cam_data_q[75:82]); + assign ex4_rd_data_calc_par[51] = ^(ex4_rd_cam_data_q[0:7]); + assign ex4_rd_data_calc_par[52] = ^(ex4_rd_cam_data_q[8:15]); + assign ex4_rd_data_calc_par[53] = ^(ex4_rd_cam_data_q[16:23]); + assign ex4_rd_data_calc_par[54] = ^(ex4_rd_cam_data_q[24:31]); + assign ex4_rd_data_calc_par[55] = ^(ex4_rd_cam_data_q[32:39]); + assign ex4_rd_data_calc_par[56] = ^(ex4_rd_cam_data_q[40:47]); + assign ex4_rd_data_calc_par[57] = ^(ex4_rd_cam_data_q[48:55]); + assign ex4_rd_data_calc_par[58] = ^(ex4_rd_cam_data_q[57:62]); + assign ex4_rd_data_calc_par[59] = ^(ex4_rd_cam_data_q[63:66]); + assign ex4_rd_data_calc_par[60] = ^(ex4_rd_cam_data_q[67:74]); + assign ex4_rd_data_calc_par[61] = ^(ex4_rd_array_data_q[0:5]); + assign ex4_rd_data_calc_par[62] = ^(ex4_rd_array_data_q[6:13]); + assign ex4_rd_data_calc_par[63] = ^(ex4_rd_array_data_q[14:21]); + assign ex4_rd_data_calc_par[64] = ^(ex4_rd_array_data_q[22:29]); + assign ex4_rd_data_calc_par[65] = ^(ex4_rd_array_data_q[30:37]); + assign ex4_rd_data_calc_par[66] = ^(ex4_rd_array_data_q[38:44]); + assign ex4_rd_data_calc_par[67] = ^(ex4_rd_array_data_q[45:50]); + generate + if (check_parity == 0) + begin : parerr_gen0 + assign ex4_cmp_data_parerr_epn = 1'b0; + assign ex4_cmp_data_parerr_rpn = 1'b0; + end + endgenerate + generate + if (check_parity == 1) + begin : parerr_gen1 + assign ex4_cmp_data_parerr_epn = ex4_cmp_data_parerr_epn_mac; + assign ex4_cmp_data_parerr_rpn = ex4_cmp_data_parerr_rpn_mac; + end + endgenerate + generate + if (check_parity == 0) + begin : parerr_gen2 + assign ex4_rd_data_parerr_epn = 1'b0; + assign ex4_rd_data_parerr_rpn = 1'b0; + end + endgenerate + generate + if (check_parity == 1) + begin : parerr_gen3 + assign ex4_rd_data_parerr_epn = |(ex4_rd_data_calc_par[50:60] ^ ({ex4_rd_cam_data_q[83], ex4_rd_array_data_q[51:60]})); + assign ex4_rd_data_parerr_rpn = |(ex4_rd_data_calc_par[61:67] ^ ex4_rd_array_data_q[61:67]); + end + endgenerate + // Adding Little Endian capture latches for timing + assign rw_entry_d = rw_entry; + assign rw_entry_val_d = &(wr_array_val); + assign rw_entry_le_d = wr_array_data[44]; + assign cam_entry_le_wr[0] = (rw_entry_q == 5'b00000) & rw_entry_val_q; + assign cam_entry_le[0] = (cam_entry_le_wr[0] == 1'b1) ? rw_entry_le_q : + cam_entry_le_q[0]; + assign cam_entry_le_d[0] = cam_entry_le[0]; + assign cam_entry_le_wr[1] = (rw_entry_q == 5'b00001) & rw_entry_val_q; + assign cam_entry_le[1] = (cam_entry_le_wr[1] == 1'b1) ? rw_entry_le_q : + cam_entry_le_q[1]; + assign cam_entry_le_d[1] = cam_entry_le[1]; + assign cam_entry_le_wr[2] = (rw_entry_q == 5'b00010) & rw_entry_val_q; + assign cam_entry_le[2] = (cam_entry_le_wr[2] == 1'b1) ? rw_entry_le_q : + cam_entry_le_q[2]; + assign cam_entry_le_d[2] = cam_entry_le[2]; + assign cam_entry_le_wr[3] = (rw_entry_q == 5'b00011) & rw_entry_val_q; + assign cam_entry_le[3] = (cam_entry_le_wr[3] == 1'b1) ? rw_entry_le_q : + cam_entry_le_q[3]; + assign cam_entry_le_d[3] = cam_entry_le[3]; + assign cam_entry_le_wr[4] = (rw_entry_q == 5'b00100) & rw_entry_val_q; + assign cam_entry_le[4] = (cam_entry_le_wr[4] == 1'b1) ? rw_entry_le_q : + cam_entry_le_q[4]; + assign cam_entry_le_d[4] = cam_entry_le[4]; + assign cam_entry_le_wr[5] = (rw_entry_q == 5'b00101) & rw_entry_val_q; + assign cam_entry_le[5] = (cam_entry_le_wr[5] == 1'b1) ? rw_entry_le_q : + cam_entry_le_q[5]; + assign cam_entry_le_d[5] = cam_entry_le[5]; + assign cam_entry_le_wr[6] = (rw_entry_q == 5'b00110) & rw_entry_val_q; + assign cam_entry_le[6] = (cam_entry_le_wr[6] == 1'b1) ? rw_entry_le_q : + cam_entry_le_q[6]; + assign cam_entry_le_d[6] = cam_entry_le[6]; + assign cam_entry_le_wr[7] = (rw_entry_q == 5'b00111) & rw_entry_val_q; + assign cam_entry_le[7] = (cam_entry_le_wr[7] == 1'b1) ? rw_entry_le_q : + cam_entry_le_q[7]; + assign cam_entry_le_d[7] = cam_entry_le[7]; + assign cam_entry_le_wr[8] = (rw_entry_q == 5'b01000) & rw_entry_val_q; + assign cam_entry_le[8] = (cam_entry_le_wr[8] == 1'b1) ? rw_entry_le_q : + cam_entry_le_q[8]; + assign cam_entry_le_d[8] = cam_entry_le[8]; + assign cam_entry_le_wr[9] = (rw_entry_q == 5'b01001) & rw_entry_val_q; + assign cam_entry_le[9] = (cam_entry_le_wr[9] == 1'b1) ? rw_entry_le_q : + cam_entry_le_q[9]; + assign cam_entry_le_d[9] = cam_entry_le[9]; + assign cam_entry_le_wr[10] = (rw_entry_q == 5'b01010) & rw_entry_val_q; + assign cam_entry_le[10] = (cam_entry_le_wr[10] == 1'b1) ? rw_entry_le_q : + cam_entry_le_q[10]; + assign cam_entry_le_d[10] = cam_entry_le[10]; + assign cam_entry_le_wr[11] = (rw_entry_q == 5'b01011) & rw_entry_val_q; + assign cam_entry_le[11] = (cam_entry_le_wr[11] == 1'b1) ? rw_entry_le_q : + cam_entry_le_q[11]; + assign cam_entry_le_d[11] = cam_entry_le[11]; + assign cam_entry_le_wr[12] = (rw_entry_q == 5'b01100) & rw_entry_val_q; + assign cam_entry_le[12] = (cam_entry_le_wr[12] == 1'b1) ? rw_entry_le_q : + cam_entry_le_q[12]; + assign cam_entry_le_d[12] = cam_entry_le[12]; + assign cam_entry_le_wr[13] = (rw_entry_q == 5'b01101) & rw_entry_val_q; + assign cam_entry_le[13] = (cam_entry_le_wr[13] == 1'b1) ? rw_entry_le_q : + cam_entry_le_q[13]; + assign cam_entry_le_d[13] = cam_entry_le[13]; + assign cam_entry_le_wr[14] = (rw_entry_q == 5'b01110) & rw_entry_val_q; + assign cam_entry_le[14] = (cam_entry_le_wr[14] == 1'b1) ? rw_entry_le_q : + cam_entry_le_q[14]; + assign cam_entry_le_d[14] = cam_entry_le[14]; + assign cam_entry_le_wr[15] = (rw_entry_q == 5'b01111) & rw_entry_val_q; + assign cam_entry_le[15] = (cam_entry_le_wr[15] == 1'b1) ? rw_entry_le_q : + cam_entry_le_q[15]; + assign cam_entry_le_d[15] = cam_entry_le[15]; + assign cam_entry_le_wr[16] = (rw_entry_q == 5'b10000) & rw_entry_val_q; + assign cam_entry_le[16] = (cam_entry_le_wr[16] == 1'b1) ? rw_entry_le_q : + cam_entry_le_q[16]; + assign cam_entry_le_d[16] = cam_entry_le[16]; + assign cam_entry_le_wr[17] = (rw_entry_q == 5'b10001) & rw_entry_val_q; + assign cam_entry_le[17] = (cam_entry_le_wr[17] == 1'b1) ? rw_entry_le_q : + cam_entry_le_q[17]; + assign cam_entry_le_d[17] = cam_entry_le[17]; + assign cam_entry_le_wr[18] = (rw_entry_q == 5'b10010) & rw_entry_val_q; + assign cam_entry_le[18] = (cam_entry_le_wr[18] == 1'b1) ? rw_entry_le_q : + cam_entry_le_q[18]; + assign cam_entry_le_d[18] = cam_entry_le[18]; + assign cam_entry_le_wr[19] = (rw_entry_q == 5'b10011) & rw_entry_val_q; + assign cam_entry_le[19] = (cam_entry_le_wr[19] == 1'b1) ? rw_entry_le_q : + cam_entry_le_q[19]; + assign cam_entry_le_d[19] = cam_entry_le[19]; + assign cam_entry_le_wr[20] = (rw_entry_q == 5'b10100) & rw_entry_val_q; + assign cam_entry_le[20] = (cam_entry_le_wr[20] == 1'b1) ? rw_entry_le_q : + cam_entry_le_q[20]; + assign cam_entry_le_d[20] = cam_entry_le[20]; + assign cam_entry_le_wr[21] = (rw_entry_q == 5'b10101) & rw_entry_val_q; + assign cam_entry_le[21] = (cam_entry_le_wr[21] == 1'b1) ? rw_entry_le_q : + cam_entry_le_q[21]; + assign cam_entry_le_d[21] = cam_entry_le[21]; + assign cam_entry_le_wr[22] = (rw_entry_q == 5'b10110) & rw_entry_val_q; + assign cam_entry_le[22] = (cam_entry_le_wr[22] == 1'b1) ? rw_entry_le_q : + cam_entry_le_q[22]; + assign cam_entry_le_d[22] = cam_entry_le[22]; + assign cam_entry_le_wr[23] = (rw_entry_q == 5'b10111) & rw_entry_val_q; + assign cam_entry_le[23] = (cam_entry_le_wr[23] == 1'b1) ? rw_entry_le_q : + cam_entry_le_q[23]; + assign cam_entry_le_d[23] = cam_entry_le[23]; + assign cam_entry_le_wr[24] = (rw_entry_q == 5'b11000) & rw_entry_val_q; + assign cam_entry_le[24] = (cam_entry_le_wr[24] == 1'b1) ? rw_entry_le_q : + cam_entry_le_q[24]; + assign cam_entry_le_d[24] = cam_entry_le[24]; + assign cam_entry_le_wr[25] = (rw_entry_q == 5'b11001) & rw_entry_val_q; + assign cam_entry_le[25] = (cam_entry_le_wr[25] == 1'b1) ? rw_entry_le_q : + cam_entry_le_q[25]; + assign cam_entry_le_d[25] = cam_entry_le[25]; + assign cam_entry_le_wr[26] = (rw_entry_q == 5'b11010) & rw_entry_val_q; + assign cam_entry_le[26] = (cam_entry_le_wr[26] == 1'b1) ? rw_entry_le_q : + cam_entry_le_q[26]; + assign cam_entry_le_d[26] = cam_entry_le[26]; + assign cam_entry_le_wr[27] = (rw_entry_q == 5'b11011) & rw_entry_val_q; + assign cam_entry_le[27] = (cam_entry_le_wr[27] == 1'b1) ? rw_entry_le_q : + cam_entry_le_q[27]; + assign cam_entry_le_d[27] = cam_entry_le[27]; + assign cam_entry_le_wr[28] = (rw_entry_q == 5'b11100) & rw_entry_val_q; + assign cam_entry_le[28] = (cam_entry_le_wr[28] == 1'b1) ? rw_entry_le_q : + cam_entry_le_q[28]; + assign cam_entry_le_d[28] = cam_entry_le[28]; + assign cam_entry_le_wr[29] = (rw_entry_q == 5'b11101) & rw_entry_val_q; + assign cam_entry_le[29] = (cam_entry_le_wr[29] == 1'b1) ? rw_entry_le_q : + cam_entry_le_q[29]; + assign cam_entry_le_d[29] = cam_entry_le[29]; + assign cam_entry_le_wr[30] = (rw_entry_q == 5'b11110) & rw_entry_val_q; + assign cam_entry_le[30] = (cam_entry_le_wr[30] == 1'b1) ? rw_entry_le_q : + cam_entry_le_q[30]; + assign cam_entry_le_d[30] = cam_entry_le[30]; + assign cam_entry_le_wr[31] = (rw_entry_q == 5'b11111) & rw_entry_val_q; + assign cam_entry_le[31] = (cam_entry_le_wr[31] == 1'b1) ? rw_entry_le_q : + cam_entry_le_q[31]; + assign cam_entry_le_d[31] = cam_entry_le[31]; + assign ex3_cam_byte_rev = (cam_entry_le ^ ({32{ex3_byte_rev_q}})); + assign ex3_cam_entry_le = (ex3_cam_byte_rev & {32{(~ccr2_frat_paranoia_q[9])}}); + assign ex3_cam_hit_le = |((ex3_cam_entry_le & entry_match)); + // ttype <= 0-eratre 1-eratwe 2-eratsx 3-eratilx 4-load 5-store 6-csync 7-isync 8-icbtlslc 9-touch 10-extload 11-extstore + // end of parity checking ------------------------------------------------------ + // epsc waits for tlb_reloads + assign epsc_wr_d[0:`THREADS - 1] = ex0_epsc_wr_val_q; + assign epsc_wr_d[`THREADS:(2 * `THREADS) - 1] = (|(tlb_rel_val_q[0:4]) == 1'b1) ? (epsc_wr_q[0:`THREADS - 1] | epsc_wr_q[`THREADS:(2 * `THREADS) - 1]) : + epsc_wr_q[0:`THREADS - 1]; + assign epsc_wr_d[2 * `THREADS] = (|(tlb_rel_val_q[0:4]) == 1'b1) ? (|(epsc_wr_q[0:`THREADS - 1]) | epsc_wr_q[2 * `THREADS]) : + |(epsc_wr_q[0:`THREADS - 1]); + // eplc waits for tlb_reloads and epsc accesses + assign eplc_wr_d[0:`THREADS - 1] = ex0_eplc_wr_val_q; + assign eplc_wr_d[`THREADS:2 * `THREADS - 1] = ((|(tlb_rel_val_q[0:4]) == 1'b1 | epsc_wr_q[2 * `THREADS] == 1'b1)) ? (eplc_wr_q[0:`THREADS - 1] | eplc_wr_q[`THREADS:(2 * `THREADS) - 1]) : + eplc_wr_q[0:`THREADS - 1]; + assign eplc_wr_d[2 * `THREADS] = ((|(tlb_rel_val_q[0:4]) == 1'b1 | epsc_wr_q[2 * `THREADS] == 1'b1)) ? (|(eplc_wr_q[0:`THREADS - 1]) | eplc_wr_q[2 * `THREADS]) : + |(eplc_wr_q[0:`THREADS - 1]); + // CAM Port + assign flash_invalidate = (por_seq_q == PorSeq_Stg1) | mchk_flash_inv_enab; + assign comp_invalidate = ((csinv_complete == 1'b1)) ? 1'b1 : + ((tlb_rel_val_q[0:3] != 4'b0000 & tlb_rel_val_q[4] == 1'b1)) ? 1'b0 : + (((eplc_wr_q[2 * `THREADS] == 1'b1 | epsc_wr_q[2 * `THREADS] == 1'b1) & tlb_rel_val_q[4] == 1'b0 & mmucr1_q[7] == 1'b0)) ? 1'b1 : + (snoop_val_q[0:1] == 2'b11) ? 1'b1 : + 1'b0; + assign comp_request = (((csinv_complete == 1'b1) | ((eplc_wr_q[2 * `THREADS] == 1'b1 | epsc_wr_q[2 * `THREADS] == 1'b1) & tlb_rel_val_q[4] == 1'b0 & mmucr1_q[7] == 1'b0) | + (snoop_val_q[0:1] == 2'b11 & tlb_rel_val_q[0:3] == 4'b0000) | ((|(ex2_valid_op_q)) == 1'b1 & ex2_ttype_q[2] == 1'b1 & ex2_tlbsel_q == TlbSel_DErat) | + ((|(ex2_valid)) == 1'b1 & ex2_ttype_q[4:5] != 2'b00) | ((|(ex2_pfetch_val_q)) == 1'b1))) ? 1'b1 : + 1'b0; + generate + if (GPR_WIDTH == 64) + begin : gen64_comp_addr + assign comp_addr = dir_derat_ex2_epn_arr; + assign derat_dec_rv1_snoop_addr = ((|(rv1_ttype_val_q)) == 1'b0) ? snoop_addr_q : + rs_data_q[0:51]; + assign derat_rv1_snoop_val = (rv1_snoop_val_q) | (|(rv1_ttype_val_q) & rv1_ttype_q[2]); + end + endgenerate + generate + if (GPR_WIDTH == 32) + begin : gen32_comp_addr + assign comp_addr = {{32{1'b0}}, dir_derat_ex2_epn_arr[32:51]}; + assign derat_dec_rv1_snoop_addr = ((|(rv1_ttype_val_q)) == 1'b0) ? {{32{1'b0}}, snoop_addr_q[32:51]} : + {{32{1'b0}}, rs_data_q[32:51]}; + assign derat_rv1_snoop_val = (rv1_snoop_val_q) | (|(rv1_ttype_val_q) & rv1_ttype_q[2]); + end + endgenerate + assign ex3_comp_addr_d = comp_addr[22:51]; + // ex2_rs_is(0 to 9) from erativax instr. + // RS(55) -> ex2_rs_is(0) -> snoop_attr(0) -> Local + // RS(56:57) -> ex2_rs_is(1:2) -> snoop_attr(0:1) -> IS + // RS(58:59) -> ex2_rs_is(3:4) -> snoop_attr(2:3) -> Class + // n/a -> n/a -> snoop_attr(4:5) -> State + // n/a -> n/a -> snoop_attr(6:13) -> TID(6:13) + // RS(60:63) -> ex2_rs_is(5:8) -> snoop_attr(14:17) -> Size + // n/a -> n/a -> snoop_attr(20:25) -> TID(0:5) + // snoop_attr: + // 0 -> Local + // 1:3 -> IS/Class: 0=all, 1=tid, 2=gs, 3=epn, 4=class0, 5=class1, 6=class2, 7=class3 + // 4:5 -> GS/TS + // 6:13 -> TID(6:13) + // 14:17 -> Size + // 18 -> reserved for tlb, extclass_enable(0) for erats + // 19 -> mmucsr0.tlb0fi for tlb, or TID_NZ for erats + // 20:25 -> TID(0:5) + // ttype <= 0-eratre 1-eratwe 2-eratsx 3-eratilx 4-load 5-store 6-csync 7-isync 8-icbtlslc 9-touch 10-extload 11-extstore + assign addr_enable = (((csinv_complete == 1'b1) | (epsc_wr_q[2 * `THREADS] == 1'b1 | eplc_wr_q[2 * `THREADS] == 1'b1) | (snoop_val_q[0:1] == 2'b11 & snoop_attr_q[1:3] != 3'b011))) ? 2'b00 : + ((snoop_val_q[0:1] == 2'b11 & snoop_attr_q[0:3] == 4'b0011)) ? 2'b10 : + ((snoop_val_q[0:1] == 2'b11 & snoop_attr_q[0:3] == 4'b1011)) ? 2'b11 : + ((((|(ex2_valid_op_q)) == 1'b1 & ex2_ttype_q[2] == 1'b1 & ex2_tlbsel_q == TlbSel_DErat) | + ((|(ex2_valid)) == 1'b1 & ex2_ttype_q[4:5] != 2'b00) | + ((|(ex2_pfetch_val_q)) == 1'b1))) ? 2'b11 : + 2'b00; + assign comp_pgsize = (snoop_attr_q[14:17] == WS0_PgSize_1GB) ? CAM_PgSize_1GB : + (snoop_attr_q[14:17] == WS0_PgSize_16MB) ? CAM_PgSize_16MB : + (snoop_attr_q[14:17] == WS0_PgSize_1MB) ? CAM_PgSize_1MB : + (snoop_attr_q[14:17] == WS0_PgSize_64KB) ? CAM_PgSize_64KB : + CAM_PgSize_4KB; + assign pgsize_enable = ((csinv_complete == 1'b1)) ? 1'b0 : + ((epsc_wr_q[2 * `THREADS] == 1'b1 | eplc_wr_q[2 * `THREADS] == 1'b1)) ? 1'b0 : + ((snoop_val_q[0:1] == 2'b11 & snoop_attr_q[0:3] == 4'b0011)) ? 1'b1 : + 1'b0; + // ttype <= 0-eratre 1-eratwe 2-eratsx 3-eratilx 4-load 5-store 6-csync 7-isync 8-icbtlslc 9-touch 10-extload 11-extstore + // mmucr1_q: 0-DRRE, 1-REE, 2-CEE, 3-csync, 4-isync, 5:6-DPEI, 7:8-DCTID/DTTID, 9:DCCD + assign comp_class = ((epsc_wr_q[2 * `THREADS] == 1'b1 & mmucr1_q[7] == 1'b0)) ? 2'b11 : + ((epsc_wr_q[2 * `THREADS] == 1'b0 & eplc_wr_q[2 * `THREADS] == 1'b1 & mmucr1_q[7] == 1'b0)) ? 2'b10 : + ((snoop_val_q[0:1] == 2'b11 & mmucr1_q[7] == 1'b1)) ? snoop_attr_q[20:21] : + ((snoop_val_q[0:1] == 2'b11)) ? snoop_attr_q[2:3] : + (mmucr1_q[7] == 1'b1) ? ex2_pid_q[pid_width - 14:pid_width - 13] : + ({(ex2_ttype_q[10] | ex2_ttype_q[11]), ex2_ttype_q[11]}); + assign class_enable[0] = (((mmucr1_q[7] == 1'b1) | (csinv_complete == 1'b1))) ? 1'b0 : + ((((eplc_wr_q[2 * `THREADS] == 1'b1 | epsc_wr_q[2 * `THREADS] == 1'b1) & tlb_rel_val_q[4] == 1'b0 & mmucr1_q[7] == 1'b0) | + (snoop_val_q[0:1] == 2'b11 & snoop_attr_q[1] == 1'b1) | ((|(ex2_valid)) == 1'b1 & ex2_ttype_q[10:11] != 2'b00 & mmucr1_q[9] == 1'b0) | + ((|(ex2_valid)) == 1'b1 & ex2_ttype_q[4:5] != 2'b00 & mmucr1_q[9] == 1'b0) | + ((|(ex2_pfetch_val_q)) == 1'b1 & mmucr1_q[9] == 1'b0))) ? 1'b1 : + 1'b0; + assign class_enable[1] = (((mmucr1_q[7] == 1'b1) | (csinv_complete == 1'b1))) ? 1'b0 : + ((((eplc_wr_q[2 * `THREADS] == 1'b1 | epsc_wr_q[2 * `THREADS] == 1'b1) & tlb_rel_val_q[4] == 1'b0 & mmucr1_q[7] == 1'b0) | + (snoop_val_q[0:1] == 2'b11 & snoop_attr_q[1] == 1'b1) | ((|(ex2_valid)) == 1'b1 & ex2_ttype_q[10:11] != 2'b00 & mmucr1_q[9] == 1'b0))) ? 1'b1 : + 1'b0; + assign class_enable[2] = pid_enable & mmucr1_q[7]; + // snoop_attr: + // 0 -> Local + // 1:3 -> IS/Class: 0=all, 1=tid, 2=gs, 3=epn, 4=class0, 5=class1, 6=class2, 7=class3 + // 4:5 -> GS/TS + // 6:13 -> TID(6:13) + // 14:17 -> Size + // 18 -> reserved for tlb, extclass_enable(0) for erats + // 19 -> mmucsr0.tlb0fi for tlb, or TID_NZ for erats + // 20:25 -> TID(0:5) + assign comp_extclass[0] = 1'b0; + assign comp_extclass[1] = snoop_attr_q[19]; + assign extclass_enable[0] = (csinv_complete == 1'b1) | ((eplc_wr_q[2 * `THREADS] | epsc_wr_q[2 * `THREADS]) & (~mmucr1_q[7])) | (snoop_val_q[0] & snoop_attr_q[18]); + assign extclass_enable[1] = (~csinv_complete) & (snoop_val_q[0] & (~snoop_attr_q[1]) & snoop_attr_q[3]); + // state: 0:pr 1:gs 2:ds 3:cm + // cam state bits are 0:GS, 1:TS + assign comp_state = ((snoop_val_q[0:1] == 2'b11 & snoop_attr_q[1:2] == 2'b01)) ? snoop_attr_q[4:5] : + ex2_state_q[1:2]; + assign state_enable = (((csinv_complete == 1'b1) | (epsc_wr_q[2 * `THREADS] == 1'b1 | eplc_wr_q[2 * `THREADS] == 1'b1) | (snoop_val_q[0:1] == 2'b11 & snoop_attr_q[1:2] != 2'b01))) ? 2'b00 : + ((snoop_val_q[0:1] == 2'b11 & snoop_attr_q[1:3] == 3'b010)) ? 2'b10 : + ((snoop_val_q[0:1] == 2'b11 & snoop_attr_q[1:3] == 3'b011)) ? 2'b11 : + ((((|(ex2_valid_op_q)) == 1'b1 & ex2_ttype_q[2] == 1'b1 & ex2_tlbsel_q == TlbSel_DErat) | + ((|(ex2_valid)) == 1'b1 & ex2_ttype_q[4:5] != 2'b00) | + ((|(ex2_pfetch_val_q)) == 1'b1))) ? 2'b11 : + 2'b00; + // mmucr1_q: 0-DRRE, 1-REE, 2-CEE, 3-csync, 4-isync, 5:6-DPEI, 7:8-DCTID/DTTID, 9-DCCD + generate begin : compTids + genvar tid; + for (tid = 0; tid <= 3; tid = tid + 1) begin : compTids + if (tid < `THREADS) begin : validTid + assign comp_thdid[tid] = ((snoop_val_q[0:1] == 2'b11 & mmucr1_q[8] == 1'b1)) ? snoop_attr_q[22 + tid] : + ((mmucr1_q[8] == 1'b1)) ? ex2_pid_q[(pid_width - 12) + tid] : + ((epsc_wr_q[2 * `THREADS] == 1'b1 & mmucr1_q[8] == 1'b0)) ? epsc_wr_q[`THREADS + tid] : + ((epsc_wr_q[2 * `THREADS] == 1'b0 & eplc_wr_q[2 * `THREADS] == 1'b1 & mmucr1_q[8] == 1'b0)) ? eplc_wr_q[`THREADS + tid] : + ((snoop_val_q[0:1] == 2'b11 & mmucr1_q[8] == 1'b0)) ? 1'b1 : + ((ex2_pfetch_val_q[tid]) == 1'b1) ? 1'b1 : + ex2_valid[tid]; + end + if (tid >= `THREADS) begin : nonValidTid + assign comp_thdid[tid] = ((snoop_val_q[0:1] == 2'b11 & mmucr1_q[8] == 1'b1)) ? snoop_attr_q[22 + tid] : + ((mmucr1_q[8] == 1'b1)) ? ex2_pid_q[(pid_width - 12) + tid] : + ((epsc_wr_q[2 * `THREADS] == 1'b1 & mmucr1_q[8] == 1'b0)) ? 1'b0 : + ((epsc_wr_q[2 * `THREADS] == 1'b0 & eplc_wr_q[2 * `THREADS] == 1'b1 & mmucr1_q[8] == 1'b0)) ? 1'b0 : + ((snoop_val_q[0:1] == 2'b11 & mmucr1_q[8] == 1'b0)) ? 1'b1 : + 1'b0; + end + end + end + endgenerate + assign thdid_enable[0] = (((mmucr1_q[8] == 1'b1) | (csinv_complete == 1'b1))) ? 1'b0 : + (((epsc_wr_q[2 * `THREADS] == 1'b1 & tlb_rel_val_q[4] == 1'b0 & mmucr1_q[8] == 1'b0) | (epsc_wr_q[2 * `THREADS] == 1'b0 & eplc_wr_q[2 * `THREADS] == 1'b1 & tlb_rel_val_q[4] == 1'b0 & mmucr1_q[8] == 1'b0))) ? 1'b1 : + ((snoop_val_q[0:1] == 2'b11)) ? 1'b0 : + ((((|(ex2_valid_op_q)) == 1'b1 & ex2_ttype_q[2] == 1'b1 & ex2_tlbsel_q == TlbSel_DErat) | ((|(ex2_valid)) == 1'b1 & (|(ex2_ttype_q[4:5])) == 1'b1) | ((|(ex2_pfetch_val_q)) == 1'b1))) ? 1'b1 : + 1'b0; + assign thdid_enable[1] = pid_enable & mmucr1_q[8]; + assign comp_pid = ((snoop_val_q[0:1] == 2'b11)) ? snoop_attr_q[6:13] : + ex2_pid_q[pid_width - 8:pid_width - 1]; + assign pid_enable = (((csinv_complete == 1'b1) | (epsc_wr_q[2 * `THREADS] == 1'b1 | eplc_wr_q[2 * `THREADS] == 1'b1) | (snoop_val_q[0:1] == 2'b11 & snoop_attr_q[1] == 1'b1) | (snoop_val_q[0:1] == 2'b11 & snoop_attr_q[3] == 1'b0))) ? 1'b0 : + (((snoop_val_q[0:1] == 2'b11 & snoop_attr_q[1:3] == 3'b001) | (snoop_val_q[0:1] == 2'b11 & snoop_attr_q[1:3] == 3'b011) | ((|(ex2_valid_op_q) == 1'b1) & ex2_ttype_q[2] == 1'b1 & ex2_tlbsel_q == TlbSel_DErat) | ((|(ex2_valid)) == 1'b1 & ex2_ttype_q[4:5] != 2'b00) | ((|(ex2_pfetch_val_q)) == 1'b1))) ? 1'b1 : + 1'b0; + // wr_cam_data + // 0:51 - EPN + // 52 - X + // 53:55 - SIZE + // 56 - V + // 57:60 - ThdID + // 61:62 - Class + // 63:64 - ExtClass | TID_NZ + // 65 - TGS + // 66 - TS + // 67:74 - TID + // 75:78 - epn_cmpmasks: 34_39, 40_43, 44_47, 48_51 + // 79:82 - xbit_cmpmasks: 34_51, 40_51, 44_51, 48_51 + // 83 - parity for 75:82 + // 16x143 version, 42b RA + // wr_array_data + // 0:29 - RPN + // 30:31 - R,C + // 32:35 - ResvAttr + // 36:39 - U0-U3 + // 40:44 - WIMGE + // 45:46 - UX,SX + // 47:48 - UW,SW + // 49:50 - UR,SR + // 51:60 - CAM parity + // 61:67 - Array parity + // wr_ws0_data (LO) + // 0:51 - EPN + // 52:53 - Class + // 54 - V + // 55 - X + // 56:59 - SIZE + // 60:63 - ThdID + // CAM.ExtClass - MMUCR ExtClass + // CAM.TS - MMUCR TS + // CAM.TID - MMUCR TID + // wr_ws1_data (HI) + // 0:7 - unused + // 8:9 - WLC + // 10 - ResvAttr + // 11 - unused + // 12:15 - U0-U3 + // 16:17 - R,C + // 18:21 - unused + // 22:51 - RPN + // 52:56 - WIMGE + // 57 - VF + // 58:59 - UX,SX + // 60:61 - UW,SW + // 62:63 - UR,SR + // state: 0:pr 1:gs 2:ds 3:cm + // ttype <= 0-eratre 1-eratwe 2-eratsx 3-eratilx 4-load 5-store 6-csync 7-isync 8-icbtlslc 9-touch 10-extload 11-extstore + // EPN Class V + // X SIZE ThdID + // Unused ResvAttr U0-U3 R,C + // RPN WIMGE Unused UX,SW,UW,SW,UR,SR + + generate + if (`GPR_WIDTH == 64) + begin : gen64_data_out + assign ex5_data_out_d = (({({32{1'b0}}), ex4_rd_cam_data_q[32:51], + (ex4_rd_cam_data_q[61:62] & {2{~(mmucr1_q[7])}}), + ex4_rd_cam_data_q[56], ex4_rd_cam_data_q[52], ws0_pgsize[0:3], + (ex4_rd_cam_data_q[57:58] | {2{mmucr1_q[8]}}), 2'b0}) & + ({`GPR_WIDTH{(|(ex4_valid) & ex4_ttype_q[0] & (~ex4_ws_q[0]) & (~ex4_ws_q[1]) & (~ex4_state_q[3]))}})) | + (({({32{1'b0}}), ex4_rd_array_data_q[10:29], 2'b00, ex4_rd_array_data_q[0:9]}) & + ({`GPR_WIDTH{(|(ex4_valid) & ex4_ttype_q[0] & (~ex4_ws_q[0]) & ex4_ws_q[1] & (~ex4_state_q[3]))}})) | + (({({32{1'b0}}), 8'b00000000, ex4_rd_array_data_q[32:34], 1'b0, ex4_rd_array_data_q[36:39], ex4_rd_array_data_q[30:31], 2'b00, ex4_rd_array_data_q[40:44], ex4_rd_array_data_q[35], ex4_rd_array_data_q[45:50]}) & + ({`GPR_WIDTH{(|(ex4_valid) & ex4_ttype_q[0] & ex4_ws_q[0] & (~ex4_ws_q[1]) & (~ex4_state_q[3]))}})) | + (({ex4_rd_cam_data_q[0:51], + (ex4_rd_cam_data_q[61:62] & {2{~(mmucr1_q[7])}}), + ex4_rd_cam_data_q[56], ex4_rd_cam_data_q[52], ws0_pgsize[0:3], + (ex4_rd_cam_data_q[57:58] | {2{mmucr1_q[8]}}), 2'b0}) & + ({`GPR_WIDTH{(|(ex4_valid) & ex4_ttype_q[0] & (~ex4_ws_q[0]) & (~ex4_ws_q[1]) & ex4_state_q[3])}})) | + (({8'b00000000, ex4_rd_array_data_q[32:34], 1'b0, ex4_rd_array_data_q[36:39], ex4_rd_array_data_q[30:31], 4'b0000, ex4_rd_array_data_q[0:29], ex4_rd_array_data_q[40:44], ex4_rd_array_data_q[35], ex4_rd_array_data_q[45:50]}) & + ({`GPR_WIDTH{(|(ex4_valid) & ex4_ttype_q[0] & (~ex4_ws_q[0]) & ex4_ws_q[1] & ex4_state_q[3])}})) | + (({({59{1'b0}}), eptr_q}) & + ({`GPR_WIDTH{(|(ex4_valid) & ex4_ttype_q[0] & ex4_ws_q[0] & ex4_ws_q[1] & mmucr1_q[0])}})) | + (({({59{1'b0}}), lru_way_encode}) & + ({`GPR_WIDTH{(|(ex4_valid) & ex4_ttype_q[0] & ex4_ws_q[0] & ex4_ws_q[1] & (~mmucr1_q[0]))}})) | + (({({50{1'b0}}), ex4_eratsx_data[0:1], ({7{1'b0}}), ex4_eratsx_data[2:2 + num_entry_log2 - 1]}) & + ({`GPR_WIDTH{(|(ex4_valid) & ex4_ttype_q[2])}})); + end + endgenerate + + generate + if (`GPR_WIDTH == 32) + begin : gen32_data_out + assign ex5_data_out_d = (({ex4_rd_cam_data_q[32:51], + (ex4_rd_cam_data_q[61:62] & {2{~(mmucr1_q[7])}}), + ex4_rd_cam_data_q[56], ex4_rd_cam_data_q[52], ws0_pgsize[0:3], + (ex4_rd_cam_data_q[57:58] | {2{mmucr1_q[8]}}), 2'b0}) & + ({`GPR_WIDTH{(|(ex4_valid) & ex4_ttype_q[0] & (~ex4_ws_q[0]) & (~ex4_ws_q[1]))}})) | + (({ex4_rd_array_data_q[10:29], 2'b00, ex4_rd_array_data_q[0:9]}) & + ({`GPR_WIDTH{(|(ex4_valid) & ex4_ttype_q[0] & (~ex4_ws_q[0]) & ex4_ws_q[1])}})) | + (({8'b00000000, ex4_rd_array_data_q[32:34], 1'b0, ex4_rd_array_data_q[36:39], ex4_rd_array_data_q[30:31], 2'b00, ex4_rd_array_data_q[40:44], ex4_rd_array_data_q[35], ex4_rd_array_data_q[45:50]}) & + ({`GPR_WIDTH{(|(ex4_valid) & ex4_ttype_q[0] & ex4_ws_q[0] & (~ex4_ws_q[1]))}})) | + (({({27{1'b0}}), eptr_q}) & + ({`GPR_WIDTH{(|(ex4_valid) & ex4_ttype_q[0] & ex4_ws_q[0] & ex4_ws_q[1] & mmucr1_q[0])}})) | + (({({27{1'b0}}), lru_way_encode}) & + ({`GPR_WIDTH{(|(ex4_valid) & ex4_ttype_q[0] & ex4_ws_q[0] & ex4_ws_q[1] & (~mmucr1_q[0]))}})) | + (({({18{1'b0}}), ex4_eratsx_data[0:1], ({7{1'b0}}), ex4_eratsx_data[2:2 + num_entry_log2 - 1]}) & + ({`GPR_WIDTH{(|(ex4_valid) & ex4_ttype_q[2])}})); + end + endgenerate + + //ex4_valid_32b <= or_reduce(ex4_valid_q and not(spr_msr_cm_q)); + // ERAT outputs + // 16x143 version + // pass thru epn offset bits depending on page size from cam entry + // adding frat paranoia bypass bit 9 for ra=ea... bit 10 also bypass ra=ea for other xu reasons + // bit 10 affects only rpn, not the attr/prot bits + // wr_cam_data(75) (76) (77) (78) (79) (80) (81) (82) + // cmpmask(0) (1) (2) (3) xbitmask(0) (1) (2) (3) + // xbit pgsize 34_39 40_43 44_47 48_51 34_39 40_43 44_47 48_51 size + // 0 001 1 1 1 1 0 0 0 0 4K + // 0 011 1 1 1 0 0 0 0 0 64K + // 0 101 1 1 0 0 0 0 0 0 1M + // 0 111 1 0 0 0 0 0 0 0 16M + // 0 110 0 0 0 0 0 0 0 0 1G + generate + if (ex3_epn_width == rpn_width) + begin : gen_mcompar_breaks_timing_1 + assign derat_dcc_ex3_e = ((ccr2_frat_paranoia_q[4] ^ ex3_byte_rev_q) & ccr2_frat_paranoia_q[9]) | ex3_cam_hit_le; + end + endgenerate + //gen_no_frat_1: if ex3_epn_width = 18 generate + // derat_dcc_ex3_e <= ex3_cam_hit_le; + //end generate gen_no_frat_1; + // new cam _np2 bypass attributes (bit numbering per array) + // 30:31 - R,C + // 32:33 - WLC + // 34 - ResvAttr + // 35 - VF + // 36:39 - U0-U3 + // 40:44 - WIMGE + // 45:46 - UX,SX + // 47:48 - UW,SW + // 49:50 - UR,SR + assign bypass_mux_enab_np1 = (ccr2_frat_paranoia_q[9] | ccr2_frat_paranoia_q[11]); + assign bypass_attr_np1[0:5] = {6{1'b0}}; + assign bypass_attr_np1[6:9] = ccr2_frat_paranoia_q[5:8]; + assign bypass_attr_np1[10:14] = ccr2_frat_paranoia_q[0:4]; + assign bypass_attr_np1[15:20] = 6'b111111; + // Had to remove ex4_gate_miss from equation, was causing a livelock scenario since the oldest itag was not + // able to report a recirc valid to IU, the gate_miss was gating that report + assign ex4_miss_w_tlb = (|(ex4_miss_q) & (~(spr_ccr2_notlb_q | ex4_nonspec_val_q))) | ex4_tlbmiss_q; + assign ex4_miss_wo_tlb = |(ex4_miss_q) & spr_ccr2_notlb_q; + assign derat_dcc_ex4_tlb_err = ex4_miss_w_tlb | ex4_miss_wo_tlb; + assign derat_dcc_ex4_miss = |(ex4_miss_q); + assign derat_dcc_ex4_dsi = |(ex4_dsi_q[8 + `THREADS:7 + 2 * `THREADS]) & ex4_dsi_enab; + assign derat_dcc_ex4_noop_touch = |(ex4_noop_touch_q[8 + `THREADS:7 + 2 * `THREADS]) & ex4_noop_touch_enab; + + assign derat_dcc_ex4_multihit_err_flush = |(ex4_multihit_q[0:`THREADS-1] & ~ex4_pfetch_val_q) & ex4_multihit_enab; // load/store, not eratsx and not prefetch + assign derat_dcc_ex4_par_err_flush = |(ex4_parerr_q[0:`THREADS-1] & ~ex4_pfetch_val_q) & ex4_parerr_enab[0]; // load/store, not eratsx and not prefetch + assign derat_dcc_ex4_multihit_err_det = |(ex4_multihit_q[0:`THREADS-1]) & ex4_multihit_enab; // load/store, not eratsx + assign derat_dcc_ex4_par_err_det = |(ex4_parerr_q[0:`THREADS-1]) & ex4_parerr_enab[0]; // load/store, not eratsx + + // TLB reporting due to derat miss + assign derat_dcc_ex4_tlb_inelig = ex4_tlbinelig_q; + assign derat_dcc_ex4_pt_fault = ex4_ptfault_q; + assign derat_dcc_ex4_lrat_miss = ex4_lratmiss_q; + assign derat_dcc_ex4_tlb_multihit = ex4_tlb_multihit_q; + assign derat_dcc_ex4_tlb_par_err = ex4_tlb_par_err_q; + assign derat_dcc_ex4_lru_par_err = ex4_lru_par_err_q; + + // Reporting to fir regs, err_rpt buffer macro is over in lq_fgen.v + assign derat_fir_par_err = |(ex5_fir_parerr_q[0:`THREADS - 1]) & ex5_fir_parerr_enab; // any source of parerr + assign derat_fir_multihit = |(ex5_fir_multihit_q[0:`THREADS - 1]); // any source of multihit + + assign lq_xu_ex5_data = ex5_data_out_q; + + // Derat Miss Request to the MMU + assign lq_mm_req = ex5_tlbreq_val; + assign lq_mm_req_nonspec = ex5_tlbreq_nonspec_q; + assign lq_mm_req_itag = ex5_itag_q; + assign lq_mm_req_epn = ex5_epn_q; + assign lq_mm_thdid = ex5_thdid_q; + assign lq_mm_req_emq = ex5_emq_q; + assign lq_mm_state = ex5_state_q; + assign lq_mm_ttype = ex5_tlbreq_ttype_q; + assign lq_mm_tid = ex5_pid_q; + assign lq_mm_lpid = ex5_lpid_q; + assign lq_mm_mmucr0 = {ex7_extclass_q, ex7_state_q[1:2], ex7_pid_q}; + assign lq_mm_mmucr0_we = ((ex7_ttype_q[0] == 1'b1 & ex7_ws_q == 2'b00 & ex7_tlbsel_q == TlbSel_DErat)) ? ex7_valid : + {`THREADS{1'b0}}; + assign lq_mm_mmucr1 = ex7_deen_q[`THREADS:`THREADS+num_entry_log2-1]; + assign lq_mm_mmucr1_we = ex7_deen_q[0:`THREADS-1]; + + assign lq_mm_perf_dtlb = ex5_perf_dtlb_q; + + //--------------------------------------------------------------------- + // CAM Instantiation + //--------------------------------------------------------------------- + //derat_cam: entity work.tri_cam_32x143_1r1w1c + + tri_cam_32x143_1r1w1c derat_cam( + .gnd(gnd), + .vdd(vdd), + .vcs(vcs), + .nclk(nclk), + + .tc_ccflush_dc(pc_xu_ccflush_dc), + .tc_scan_dis_dc_b(tc_scan_dis_dc_b), + .tc_scan_diag_dc(tc_scan_diag_dc), + .tc_lbist_en_dc(tc_lbist_en_dc), + .an_ac_atpg_en_dc(an_ac_atpg_en_dc), + + .lcb_d_mode_dc(cam_d_mode_dc), + .lcb_clkoff_dc_b(cam_clkoff_dc_b), + .lcb_act_dis_dc(cam_act_dis_dc), + .lcb_mpw1_dc_b(cam_mpw1_dc_b[0:3]), + .lcb_mpw2_dc_b(cam_mpw2_dc_b), + .lcb_delay_lclkr_dc(cam_delay_lclkr_dc[0:3]), + + .pc_sg_2(pc_sg_2), + .pc_func_slp_sl_thold_2(pc_func_slp_sl_thold_2), + .pc_func_slp_nsl_thold_2(pc_func_slp_nsl_thold_2), + .pc_regf_slp_sl_thold_2(pc_regf_slp_sl_thold_2), + .pc_time_sl_thold_2(pc_time_sl_thold_2), + .pc_fce_2(pc_fce_2), + + .func_scan_in(func_si_cam_int), + .func_scan_out(func_so_cam_int), + .regfile_scan_in(regf_scan_in), + .regfile_scan_out(regf_scan_out), + .time_scan_in(time_scan_in), + .time_scan_out(time_scan_out), + + .rd_val(rd_val), + .rd_val_late(tiup), + .rw_entry(rw_entry), + .wr_array_data(wr_array_data), + .wr_cam_data(wr_cam_data), + .wr_array_val(wr_array_val), + .wr_cam_val(wr_cam_val), + .wr_val_early(wr_val_early), + .comp_request(comp_request), + .comp_addr(comp_addr), + .addr_enable(addr_enable), + .comp_pgsize(comp_pgsize), + .pgsize_enable(pgsize_enable), + .comp_class(comp_class), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .extclass_enable(extclass_enable), + .comp_state(comp_state), + .state_enable(state_enable), + .comp_thdid(comp_thdid), + .thdid_enable(thdid_enable), + .comp_pid(comp_pid), + .pid_enable(pid_enable), + .comp_invalidate(comp_invalidate), + .flash_invalidate(flash_invalidate), + + .array_cmp_data(array_cmp_data), + .rd_array_data(rd_array_data), + .cam_cmp_data(cam_cmp_data), + .cam_hit(cam_hit), + .cam_hit_entry(cam_hit_entry), + .entry_match(entry_match), + .entry_valid(entry_valid), + .rd_cam_data(rd_cam_data), + + //--- new ports for IO plus ----------------------- + .bypass_mux_enab_np1(bypass_mux_enab_np1), + .bypass_attr_np1(bypass_attr_np1), + .attr_np2(attr_np2), + .rpn_np2(rpn_np2) + ); + + // Parity Calculation + assign ex4_cam_cmp_data_d = cam_cmp_data; + assign ex4_array_cmp_data_d = array_cmp_data; + assign ex4_cmp_data_calc_par[50] = ^(ex4_cam_cmp_data_q[75:82]); + assign ex4_cmp_data_calc_par[51] = ^(ex4_cam_cmp_data_q[0:7]); + assign ex4_cmp_data_calc_par[52] = ^(ex4_cam_cmp_data_q[8:15]); + assign ex4_cmp_data_calc_par[53] = ^(ex4_cam_cmp_data_q[16:23]); + assign ex4_cmp_data_calc_par[54] = ^(ex4_cam_cmp_data_q[24:31]); + assign ex4_cmp_data_calc_par[55] = ^(ex4_cam_cmp_data_q[32:39]); + assign ex4_cmp_data_calc_par[56] = ^(ex4_cam_cmp_data_q[40:47]); + assign ex4_cmp_data_calc_par[57] = ^(ex4_cam_cmp_data_q[48:55]); + assign ex4_cmp_data_calc_par[58] = ^(ex4_cam_cmp_data_q[57:62]); + assign ex4_cmp_data_calc_par[59] = ^(ex4_cam_cmp_data_q[63:66]); + assign ex4_cmp_data_calc_par[60] = ^(ex4_cam_cmp_data_q[67:74]); + assign ex4_cmp_data_calc_par[61] = ^(ex4_array_cmp_data_q[0:5]); + assign ex4_cmp_data_calc_par[62] = ^(ex4_array_cmp_data_q[6:13]); + assign ex4_cmp_data_calc_par[63] = ^(ex4_array_cmp_data_q[14:21]); + assign ex4_cmp_data_calc_par[64] = ^(ex4_array_cmp_data_q[22:29]); + assign ex4_cmp_data_calc_par[65] = ^(ex4_array_cmp_data_q[30:37]); + assign ex4_cmp_data_calc_par[66] = ^(ex4_array_cmp_data_q[38:44]); + assign ex4_cmp_data_calc_par[67] = ^(ex4_array_cmp_data_q[45:50]); + assign ex4_cmp_data_parerr_epn_mac = |(ex4_cmp_data_calc_par[50:60] ^ ({ex4_cam_cmp_data_q[83], ex4_array_cmp_data_q[51:60]})); + assign ex4_cmp_data_parerr_rpn_mac = |(ex4_cmp_data_calc_par[61:67] ^ ex4_array_cmp_data_q[61:67]); + + //--------------------------------------------------------------------- + // ERAT MISS Queue + //--------------------------------------------------------------------- + // MMU Interrupt Report Logic + assign mm_int_rpt_itag_d = mm_lq_itag; + assign mm_int_rpt_tlbmiss_d = |(mm_lq_tlb_miss); + assign mm_int_rpt_tlbinelig_d = |(mm_lq_tlb_inelig); + assign mm_int_rpt_ptfault_d = |(mm_lq_pt_fault); + assign mm_int_rpt_lratmiss_d = |(mm_lq_lrat_miss); + assign mm_int_rpt_tlb_multihit_d = |(mm_lq_tlb_multihit); + assign mm_int_rpt_tlb_par_err_d = |(mm_lq_tlb_par_err); + assign mm_int_rpt_lru_par_err_d = |(mm_lq_lru_par_err); + // ERATM Entry WRT pointer Logic + // Look for first IDLE state machine from ERATMISSQ(0) -> ERATMISSQ(`EMQ_ENTRIES-1) + assign eratm_wrt_ptr[0] = eratm_entry_available[0]; + + generate begin : EMPriWrt + genvar emq; + for (emq = 1; emq <= `EMQ_ENTRIES - 1; emq = emq + 1) begin : EMPriWrt + assign eratm_wrt_ptr[emq] = &((~eratm_entry_available[0:emq - 1])) & eratm_entry_available[emq]; + end + end + endgenerate + + // ERATMISS Queue Update Valid + assign ex4_eratm_val = |(ex4_miss_q & (~cp_flush_q)) & (~(spr_ccr2_notlb_q | ex4_gate_miss_q)); + assign ex4_entry_wrt_val = (eratm_wrt_ptr & {`EMQ_ENTRIES{ex4_eratm_val}}); + assign eratm_por_reset = |(por_hold_req); + // Instruction check against the ERATMISS Queue is valid + assign ex3_eratm_chk_val = |(ex3_valid_q & (~cp_flush_q)) & |(ex3_ttype_q[4:5]) & (~ex3_ttype_q[9]); + + // Compare against ex4_epn that will be updating the ERATMISS Queue with the ex3_epn + // The ERATMISS Queue epn is valid in ex5, so this covers the back-2-back case + assign ex3_eratm_epn_m = ex3_eratm_chk_val & ex4_eratm_val & (ex4_epn_q == ex3_epn_q) & (~ex3_oldest_itag); + + generate begin : ERATMQ + genvar emq; + for (emq = 0; emq <= `EMQ_ENTRIES - 1; emq = emq + 1) begin : ERATMQ + + assign eratm_tlb_rel_val[emq] = |(tlb_rel_val_q[0:3]) & tlb_rel_emq_q[emq]; + + always @(*) begin: emqState + eratm_entry_nxt_state[emq] = EMQ_IDLE; + eratm_entry_nonspec_val_d[emq] = eratm_entry_nonspec_val_q[emq]; + eratm_entry_clr_hold[emq] = 1'b0; + case (eratm_entry_state_q[emq]) + + EMQ_IDLE : + if (ex4_entry_wrt_val[emq] == 1'b1) + begin + eratm_entry_nxt_state[emq] = EMQ_RPEN; + eratm_entry_nonspec_val_d[emq] = ex4_nonspec_val_q; + end + else + begin + eratm_entry_nxt_state[emq] = EMQ_IDLE; + eratm_entry_nonspec_val_d[emq] = 1'b0; + end + + EMQ_RPEN : + if ((eratm_por_reset == 1'b1) | (ex5_emq_tlbreq_blk[emq] == 1'b1) | (eratm_tlb_rel_val[emq] == 1'b1 & (eratm_entry_int_det[emq] == 1'b0 | eratm_entry_nonspec_val_q[emq] == 1'b0))) + begin + eratm_entry_nxt_state[emq] = EMQ_IDLE; + eratm_entry_clr_hold[emq] = 1'b1; + eratm_entry_nonspec_val_d[emq] = 1'b0; + end + else if (eratm_tlb_rel_val[emq] == 1'b1 & eratm_entry_int_det[emq] == 1'b1 & eratm_entry_nonspec_val_q[emq] == 1'b1) + begin + eratm_entry_nxt_state[emq] = EMQ_REXCP; + eratm_entry_clr_hold[emq] = 1'b1; + end + else + eratm_entry_nxt_state[emq] = EMQ_RPEN; + + EMQ_REXCP : + if (eratm_entry_cpl[emq] == 1'b1) + begin + eratm_entry_nxt_state[emq] = EMQ_IDLE; + eratm_entry_clr_hold[emq] = 1'b1; + eratm_entry_nonspec_val_d[emq] = 1'b0; + end + else + eratm_entry_nxt_state[emq] = EMQ_REXCP; + + default : + begin + eratm_entry_nxt_state[emq] = EMQ_IDLE; + eratm_entry_nonspec_val_d[emq] = eratm_entry_nonspec_val_q[emq]; + eratm_entry_clr_hold[emq] = 1'b0; + end + endcase + end + + assign eratm_entry_state_d[emq] = eratm_entry_nxt_state[emq]; + + if (emq == 0) begin : entryZero + assign eratm_entry_available[emq] = eratm_entry_state_q[emq][0] & ex4_oldest_itag_q; + end + + if (emq != 0) begin : entryNZero + assign eratm_entry_available[emq] = eratm_entry_state_q[emq][0] & (~ex4_oldest_itag_q); + end + + assign eratm_entry_cpl[emq] = ex6_emq_excp_rpt[emq] | (|(por_hold_req)) | eratm_entry_kill[emq]; + assign eratm_entry_itag_d[emq] = (ex4_entry_wrt_val[emq] == 1'b1) ? ex4_itag_q : + eratm_entry_itag_q[emq]; + assign eratm_entry_tid_d[emq] = (ex4_entry_wrt_val[emq] == 1'b1) ? ex4_valid_q : + eratm_entry_tid_q[emq]; + assign eratm_entry_epn_d[emq] = (ex4_entry_wrt_val[emq] == 1'b1) ? ex4_epn_q : + eratm_entry_epn_q[emq]; + assign eratm_entry_mkill[emq] = (~eratm_entry_state_q[emq][0]) & (|(eratm_entry_tid_q[emq] & cp_flush_q)); + assign eratm_entry_kill[emq] = eratm_entry_mkill[emq] | eratm_entry_mkill_q[emq]; + assign eratm_entry_mkill_d[emq] = ({ex4_entry_wrt_val[emq], eratm_entry_mkill[emq]} == 2'b00) ? eratm_entry_mkill_q[emq] : + ({ex4_entry_wrt_val[emq], eratm_entry_mkill[emq]} == 2'b01) ? 1'b1 : + 1'b0; + assign eratm_entry_tid_inuse[emq] = eratm_entry_tid_q[emq] & {`THREADS{~eratm_entry_state_q[emq][0]}}; + assign eratm_entry_inuse[emq] = (~(eratm_entry_state_q[emq][0])) | (ex4_entry_wrt_val[emq]); + assign eratm_entry_relPend[emq] = eratm_entry_state_q[emq][1]; + assign ex3_eratm_epn_hit[emq] = ex3_eratm_chk_val & (eratm_entry_epn_q[emq] == ex3_epn_q); + assign ex3_eratm_epn_hit_restart[emq] = ex3_eratm_epn_hit[emq] & eratm_entry_state_q[emq][1] & (~ex3_oldest_itag); + + assign ex2_eratm_itag_hit[emq] = (eratm_entry_itag_q[emq] == ex2_itag_q) & (|(ex2_valid_q & eratm_entry_tid_q[emq])) & + ~(eratm_entry_kill[emq] | eratm_entry_state_q[emq][0]); + assign ex3_eratm_itag_hit_d[emq] = ex2_eratm_itag_hit[emq]; + assign ex3_eratm_itag_hit[emq] = ex3_eratm_itag_hit_q[emq] & |(ex3_valid_q & ~cp_flush_q); // Gate Cache Access to Data and Dir if ITAG hit + assign ex3_eratm_itag_hit_restart[emq] = ex3_eratm_itag_hit[emq] & ~eratm_entry_state_q[emq][2]; // Restart if it wasnt IDLE in EX2 and not currently in REXCP state + assign ex3_eratm_itag_hit_setHold[emq] = ex3_eratm_itag_hit[emq] & eratm_entry_state_q[emq][1]; // SetHold only if Reload is Pending + assign ex3_eratm_hit_report[emq] = ex3_eratm_itag_hit[emq] & eratm_entry_state_q[emq][2]; // Report Exception only if in REXCP state + assign ex3_eratm_hit_restart[emq] = ex3_eratm_itag_hit_restart[emq] | ex3_eratm_epn_hit_restart[emq]; + assign ex3_eratm_hit_setHold[emq] = (ex3_eratm_itag_hit_setHold[emq] | ex3_eratm_epn_hit_restart[emq]) & ~eratm_entry_clr_hold[emq]; + assign mm_int_rpt_tlbmiss_val[emq] = eratm_entry_state_q[emq][1] & mm_int_rpt_tlbmiss_q & rel_int_upd_val_q[emq]; + assign eratm_entry_tlbmiss_d[emq] = ({ex4_entry_wrt_val[emq], mm_int_rpt_tlbmiss_val[emq]} == 2'b00) ? eratm_entry_tlbmiss_q[emq] : + ({ex4_entry_wrt_val[emq], mm_int_rpt_tlbmiss_val[emq]} == 2'b01) ? mm_int_rpt_tlbmiss_q : + 1'b0; + assign mm_int_rpt_tlbinelig_val[emq] = eratm_entry_state_q[emq][1] & mm_int_rpt_tlbinelig_q & rel_int_upd_val_q[emq]; + assign eratm_entry_tlbinelig_d[emq] = ({ex4_entry_wrt_val[emq], mm_int_rpt_tlbinelig_val[emq]} == 2'b00) ? eratm_entry_tlbinelig_q[emq] : + ({ex4_entry_wrt_val[emq], mm_int_rpt_tlbinelig_val[emq]} == 2'b01) ? mm_int_rpt_tlbinelig_q : + 1'b0; + assign mm_int_rpt_ptfault_val[emq] = eratm_entry_state_q[emq][1] & mm_int_rpt_ptfault_q & rel_int_upd_val_q[emq]; + assign eratm_entry_ptfault_d[emq] = ({ex4_entry_wrt_val[emq], mm_int_rpt_ptfault_val[emq]} == 2'b00) ? eratm_entry_ptfault_q[emq] : + ({ex4_entry_wrt_val[emq], mm_int_rpt_ptfault_val[emq]} == 2'b01) ? mm_int_rpt_ptfault_q : + 1'b0; + assign mm_int_rpt_lratmiss_val[emq] = eratm_entry_state_q[emq][1] & mm_int_rpt_lratmiss_q & rel_int_upd_val_q[emq]; + assign eratm_entry_lratmiss_d[emq] = ({ex4_entry_wrt_val[emq], mm_int_rpt_lratmiss_val[emq]} == 2'b00) ? eratm_entry_lratmiss_q[emq] : + ({ex4_entry_wrt_val[emq], mm_int_rpt_lratmiss_val[emq]} == 2'b01) ? mm_int_rpt_lratmiss_q : + 1'b0; + assign mm_int_rpt_tlb_multihit_val[emq]= eratm_entry_state_q[emq][1] & mm_int_rpt_tlb_multihit_q & rel_int_upd_val_q[emq]; + assign eratm_entry_tlb_multihit_d[emq] = ({ex4_entry_wrt_val[emq], mm_int_rpt_tlb_multihit_val[emq]} == 2'b00) ? eratm_entry_tlb_multihit_q[emq] : + ({ex4_entry_wrt_val[emq], mm_int_rpt_tlb_multihit_val[emq]} == 2'b01) ? mm_int_rpt_tlb_multihit_q : + 1'b0; + assign mm_int_rpt_tlb_par_err_val[emq] = eratm_entry_state_q[emq][1] & mm_int_rpt_tlb_par_err_q & rel_int_upd_val_q[emq]; + assign eratm_entry_tlb_par_err_d[emq] = ({ex4_entry_wrt_val[emq], mm_int_rpt_tlb_par_err_val[emq]} == 2'b00) ? eratm_entry_tlb_par_err_q[emq] : + ({ex4_entry_wrt_val[emq], mm_int_rpt_tlb_par_err_val[emq]} == 2'b01) ? mm_int_rpt_tlb_par_err_q : + 1'b0; + assign mm_int_rpt_lru_par_err_val[emq] = eratm_entry_state_q[emq][1] & mm_int_rpt_lru_par_err_q & rel_int_upd_val_q[emq]; + assign eratm_entry_lru_par_err_d[emq] = ({ex4_entry_wrt_val[emq], mm_int_rpt_lru_par_err_val[emq]} == 2'b00) ? eratm_entry_lru_par_err_q[emq] : + ({ex4_entry_wrt_val[emq], mm_int_rpt_lru_par_err_val[emq]} == 2'b01) ? mm_int_rpt_lru_par_err_q : + 1'b0; + assign eratm_entry_int_det[emq] = eratm_entry_tlbmiss_q[emq] | eratm_entry_tlbinelig_q[emq] | eratm_entry_ptfault_q[emq] | eratm_entry_lratmiss_q[emq] | eratm_entry_tlb_multihit_q[emq] | eratm_entry_tlb_par_err_q[emq] | eratm_entry_lru_par_err_q[emq]; + end + end + endgenerate + + // Request is the oldest ITAG + assign ex3_oldest_itag = (lsq_ctl_oldest_itag == ex3_itag_q) & (|(lsq_ctl_oldest_tid & ex3_valid_q)); + assign ex4_oldest_itag_d = ex3_oldest_itag; + + generate begin : cpNextItag + genvar tid; + for (tid = 0; tid <= `THREADS - 1; tid = tid + 1) begin : cpNextItag + assign ex3_cp_next_tid[tid] = ex3_valid_q[tid] & cp_next_val_q[tid] & (ex3_itag_q == cp_next_itag_q[tid]); + end + end + endgenerate + + // Thread Quiesced OR reduce + always @(*) begin: tidQuiesce + reg [0:`THREADS-1] tidQ; + + //(* analysis_not_referenced="true" *) + + integer emq; + tidQ = {`THREADS{1'b0}}; + for (emq=0; emq<`EMQ_ENTRIES; emq=emq+1) begin + tidQ = (eratm_entry_tid_inuse[emq]) | tidQ; + end + emq_tid_idle = ~tidQ; + end + + assign ex3_nonspec_val = |(ex3_cp_next_tid); + assign ex4_nonspec_val_d = ex3_nonspec_val; + assign ex3_emq_tlbmiss = ex3_eratm_hit_report & eratm_entry_tlbmiss_q; + assign ex3_emq_tlbinelig = ex3_eratm_hit_report & eratm_entry_tlbinelig_q; + assign ex3_emq_ptfault = ex3_eratm_hit_report & eratm_entry_ptfault_q; + assign ex3_emq_lratmiss = ex3_eratm_hit_report & eratm_entry_lratmiss_q; + assign ex3_emq_multihit = ex3_eratm_hit_report & eratm_entry_tlb_multihit_q; + assign ex3_emq_tlb_par = ex3_eratm_hit_report & eratm_entry_tlb_par_err_q; + assign ex3_emq_lru_par = ex3_eratm_hit_report & eratm_entry_lru_par_err_q; + assign ex3_tlbmiss = |(ex3_emq_tlbmiss); + assign ex4_tlbmiss_d = ex3_tlbmiss; + assign ex3_tlbinelig = |(ex3_emq_tlbinelig); + assign ex4_tlbinelig_d = ex3_tlbinelig; + assign ex3_ptfault = |(ex3_emq_ptfault); + assign ex4_ptfault_d = ex3_ptfault; + assign ex3_lratmiss = |(ex3_emq_lratmiss); + assign ex4_lratmiss_d = ex3_lratmiss; + assign ex3_tlb_multihit = |(ex3_emq_multihit); + assign ex4_tlb_multihit_d = ex3_tlb_multihit; + assign ex3_tlb_par_err = |(ex3_emq_tlb_par); + assign ex4_tlb_par_err_d = ex3_tlb_par_err; + assign ex3_lru_par_err = |(ex3_emq_lru_par); + assign ex4_lru_par_err_d = ex3_lru_par_err; + assign ex4_tlb_excp_det_d = ex3_tlbmiss | ex3_tlbinelig | ex3_ptfault | ex3_lratmiss | ex3_tlb_multihit | ex3_tlb_par_err | ex3_lru_par_err; + assign ex4_emq_excp_rpt_d = ex3_emq_tlbmiss | ex3_emq_tlbinelig | ex3_emq_ptfault | ex3_emq_lratmiss | ex3_emq_multihit | ex3_emq_tlb_par | ex3_emq_lru_par; + assign ex5_emq_excp_rpt_d = ex4_emq_excp_rpt_q; + assign ex6_emq_excp_rpt_d = ex5_emq_excp_rpt_q; + assign ex5_tlb_excp_val_d = (ex4_valid_q & {`THREADS{ex4_tlb_excp_det_q}}) & (~cp_flush_q); + assign ex6_tlb_excp_val_d = ex5_tlb_excp_val_q & (~cp_flush_q); + assign ex6_tlb_cplt_val = |(ex6_tlb_excp_val_q & dcc_derat_ex6_cplt) & (ex6_itag_q == dcc_derat_ex6_cplt_itag); + assign ex6_emq_excp_rpt = (ex6_emq_excp_rpt_q & {`EMQ_ENTRIES{ex6_tlb_cplt_val}}); + // ERATM State Machines are all busy + // ERAT FULL Cases + // 1) All entries are in use + // 2) Oldest ITAG and entry 0 is in use (entry 0 is reserved for oldest, but oldest could have been flushed so new oldest cant use it) + // 3) Not the oldest ITAG and all entries except 0 are in use + assign ex3_eratm_full = &(eratm_entry_inuse) | (ex3_oldest_itag & eratm_entry_inuse[0]) | ((~ex3_oldest_itag) & (&(eratm_entry_inuse[1:`EMQ_ENTRIES - 1]))); + // Request needs to restart + assign ex4_gate_miss_d = (|(ex3_eratm_hit_restart)) | ex3_eratm_epn_m | ex3_eratm_full | (|(ex3_eratm_hit_report)); + assign ex4_full_restart_d = ex3_eratm_full; + assign ex4_epn_hit_restart_d = |(ex3_eratm_epn_hit_restart) | ex3_eratm_epn_m; + assign ex4_itag_hit_restart_d = |(ex3_eratm_itag_hit_restart); + assign ex4_setHold_d = |(ex3_eratm_hit_setHold) | ex3_eratm_epn_m | (ex3_eratm_full & (~(|(eratm_entry_clr_hold)))); + // Request to the MMU Valid + assign ex4_tlbreq_val = |((ex4_miss_q & (~cp_flush_q))) & (~(spr_ccr2_notlb_q | ex4_gate_miss_q)); + assign ex5_tlbreq_val_d = ex4_tlbreq_val; + assign ex5_tlbreq_val = ex5_tlbreq_val_q & (~dcc_derat_ex5_blk_tlb_req); + assign ex5_tlbreq_nonspec_d = ex4_nonspec_val_q; + assign ex5_thdid_d = ex4_valid_q; + assign ex5_emq_d = eratm_wrt_ptr; + assign ex5_tlbreq_ttype_d = (ex4_ttype_q[11] == 1'b1) ? 2'b11 : + (ex4_ttype_q[10] == 1'b1) ? 2'b10 : + (ex4_ttype_q[5] == 1'b1) ? 2'b01 : + 2'b00; + assign ex5_perf_dtlb_d = {`THREADS{((ex4_miss_w_tlb | ex4_miss_wo_tlb) & ~ex4_gate_miss_q)}} & ex4_valid_q & ~cp_flush_q; + + // Request to the MMU was blocked due to a higher priority interrupt + assign ex5_tlbreq_blk = ex5_tlbreq_val_q & dcc_derat_ex5_blk_tlb_req; + assign ex5_emq_tlbreq_blk = (ex5_emq_q & {`EMQ_ENTRIES{ex5_tlbreq_blk}}); + // Need to restart the request for the following reasons + // 1) ERATM State machines are all busy + // 2) ERATM State machines 1 to `EMQ_ENTRIES are busy and + // this request is not the oldest + // 3) Current Requests ITAG is already using a state machine + // 4) Current Requests derat misses EPN hit an outstanding MMU requests EPN + // 5) Current Requests is sending the NonSpeculative Request to the TLB + // Dont want to restart if current request is sending DERAT MISS indicator or TLB Exception detected + assign ex4_full_restart = |(ex4_miss_q) & (ex4_full_restart_q | ex4_nonspec_val_q); + assign ex4_hit_restart = ex4_itag_hit_restart_q | (|(ex4_miss_q) & ex4_epn_hit_restart_q); + assign ex4_derat_restart = (ex4_full_restart | ex4_hit_restart) & (~(spr_ccr2_notlb_q | ex4_tlb_excp_det_q)); + assign ex4_setHold = ex4_eratm_val | (ex4_derat_restart & ex4_setHold_q); + assign ex4_setHold_tid = (ex4_valid_q & {`THREADS{ex4_setHold}}); + assign eratm_clrHold = |(eratm_entry_clr_hold); + assign eratm_clrHold_tid = {`THREADS{eratm_clrHold}}; + + generate begin : holdTid + genvar tid; + for (tid = 0; tid <= `THREADS - 1; tid = tid + 1) begin : holdTid + assign eratm_setHold_tid_ctrl[tid] = {ex4_setHold_tid[tid], eratm_clrHold_tid[tid]}; + assign eratm_hold_tid_d[tid] = (eratm_setHold_tid_ctrl[tid] == 2'b00) ? eratm_hold_tid_q[tid] : + (eratm_setHold_tid_ctrl[tid] == 2'b10) ? ex4_setHold_tid[tid] : + 1'b0; + end + end + endgenerate + + assign derat_dcc_ex3_itagHit = |ex3_eratm_itag_hit; + assign derat_dcc_ex4_restart = ex4_derat_restart; + assign derat_dcc_ex4_setHold = ex4_setHold; + assign derat_dcc_clr_hold_d = eratm_clrHold_tid; + assign derat_dcc_clr_hold = derat_dcc_clr_hold_q; + assign derat_dcc_emq_idle = emq_tid_idle; + //--------------------------------------------------------------------- + // Effective Address equals Real Address Muxing + assign ex4_rpn_d[22:33] = (ex3_comp_addr_q[22:33] & ({12{bypass_mux_enab_np1}})) | (array_cmp_data[0:11] & ({12{(~bypass_mux_enab_np1)}})); + assign ex4_rpn_d[34:39] = (ex3_comp_addr_q[34:39] & ({6{(((~cam_cmp_data[75])) | bypass_mux_enab_np1)}})) | (array_cmp_data[12:17] & ({6{(cam_cmp_data[75] & (~bypass_mux_enab_np1))}})); + assign ex4_rpn_d[40:43] = (ex3_comp_addr_q[40:43] & ({4{(((~cam_cmp_data[76])) | bypass_mux_enab_np1)}})) | (array_cmp_data[18:21] & ({4{(cam_cmp_data[76] & (~bypass_mux_enab_np1))}})); + assign ex4_rpn_d[44:47] = (ex3_comp_addr_q[44:47] & ({4{(((~cam_cmp_data[77])) | bypass_mux_enab_np1)}})) | (array_cmp_data[22:25] & ({4{(cam_cmp_data[77] & (~bypass_mux_enab_np1))}})); + assign ex4_rpn_d[48:51] = (ex3_comp_addr_q[48:51] & ({4{(((~cam_cmp_data[78])) | bypass_mux_enab_np1)}})) | (array_cmp_data[26:29] & ({4{(cam_cmp_data[78] & (~bypass_mux_enab_np1))}})); + assign ex4_wimge_d = (array_cmp_data[40:44] & {5{(~bypass_mux_enab_np1)}}) | (bypass_attr_np1[10:14] & {5{bypass_mux_enab_np1}}); + + // bypass attributes (bit numbering per array) + // 30:31 - R,C + // 32:33 - WLC + // 34 - ResvAttr + // 35 - VF + // 36:39 - U0-U3 + // 40:44 - WIMGE + // 45:46 - UX,SX + // 47:48 - UW,SW + // 49:50 - UR,SR + assign derat_dcc_ex4_rpn = ex4_rpn_q; + assign derat_dcc_ex4_wimge = ex4_wimge_q; + assign derat_dcc_ex4_u = attr_np2[6:9]; + assign derat_dcc_ex4_wlc = attr_np2[2:3]; + assign derat_dcc_ex4_attr = attr_np2[15:20]; + assign derat_dcc_ex4_vf = attr_np2[5] & (~(|(ex4_miss_q))); + + // ERAT Operation is Complete + assign lq_xu_ord_write_done_d = |(ex4_valid) & (ex4_ttype_q[0] | ex4_ttype_q[2]); + assign lq_xu_ord_read_done_d = |(ex4_valid) & ex4_ttype_q[1]; + assign lq_xu_ord_write_done = lq_xu_ord_write_done_q; + assign lq_xu_ord_read_done = lq_xu_ord_read_done_q; + + // debug bus outputs + assign ex3_debug_d[0] = comp_request; + assign ex3_debug_d[1] = comp_invalidate; + assign ex3_debug_d[2] = (csinv_complete); + assign ex3_debug_d[3] = ((eplc_wr_q[2 * `THREADS] | epsc_wr_q[2 * `THREADS]) & (~(tlb_rel_val_q[4])) & (~(mmucr1_q[7]))); + assign ex3_debug_d[4] = (snoop_val_q[0] & snoop_val_q[1] & (~(|(tlb_rel_val_q[0:3])))); + assign ex3_debug_d[5] = (|(ex2_valid_op_q) & ex2_ttype_q[2] & (ex2_tlbsel_q == TlbSel_DErat)); + assign ex3_debug_d[6] = (|(ex2_valid) & (|(ex2_ttype_q[4:5]))); + assign ex3_debug_d[7] = (|(tlb_rel_val_q[0:3]) & tlb_rel_val_q[4]); + assign ex3_debug_d[8] = (|(tlb_rel_val_q[0:3])); + assign ex3_debug_d[9] = (snoop_val_q[0] & snoop_val_q[1]); + assign ex3_debug_d[10] = (eplc_wr_q[2 * `THREADS] | epsc_wr_q[2 * `THREADS]); + assign ex4_debug_d[0:10] = ex3_debug_q[0:10]; + assign ex4_debug_d[11:15] = ex4_first_hit_entry; + assign ex4_debug_d[16] = ex3_multihit; + assign lru_debug_d[0] = lru_update_event_q[0]; + assign lru_debug_d[1] = lru_update_event_q[1]; + assign lru_debug_d[2] = lru_update_event_q[2]; + assign lru_debug_d[3] = lru_update_event_q[3]; + assign lru_debug_d[4] = lru_update_event_q[4] & cam_hit; + assign lru_debug_d[5:35] = lru_eff; + assign lru_debug_d[36:40] = lru_way_encode; + // debug groups: out std_ulogic_vector(0 to 87); + assign derat_xu_debug_group0[0:83] = ex4_cam_cmp_data_q[0:83]; + assign derat_xu_debug_group0[84] = ex4_cam_hit_q; + assign derat_xu_debug_group0[85] = ex4_debug_q[0]; + assign derat_xu_debug_group0[86] = ex4_debug_q[1]; + assign derat_xu_debug_group0[87] = ex4_debug_q[9]; + assign derat_xu_debug_group1[0:67] = ex4_array_cmp_data_q[0:67]; + assign derat_xu_debug_group1[68] = ex4_cam_hit_q; + assign derat_xu_debug_group1[69] = ex4_debug_q[16]; + assign derat_xu_debug_group1[70:74] = ex4_debug_q[11:15]; + assign derat_xu_debug_group1[75] = ex4_debug_q[0]; + assign derat_xu_debug_group1[76] = ex4_debug_q[1]; + assign derat_xu_debug_group1[77] = ex4_debug_q[2]; + assign derat_xu_debug_group1[78] = ex4_debug_q[3]; + assign derat_xu_debug_group1[79] = ex4_debug_q[4]; + assign derat_xu_debug_group1[80] = ex4_debug_q[5]; + assign derat_xu_debug_group1[81] = ex4_debug_q[6]; + assign derat_xu_debug_group1[82] = ex4_debug_q[7]; + assign derat_xu_debug_group1[83] = ex4_debug_q[8]; + assign derat_xu_debug_group1[84] = ex4_debug_q[9]; + assign derat_xu_debug_group1[85] = ex4_debug_q[10]; + assign derat_xu_debug_group1[86] = ex4_ttype_q[8]; + assign derat_xu_debug_group1[87] = ex4_ttype_q[9]; + assign derat_xu_debug_group2[0:31] = entry_valid_q[0:31]; + assign derat_xu_debug_group2[32:63] = entry_match_q[0:31]; + assign derat_xu_debug_group2[64:73] = lru_update_event_q[0:9]; + assign derat_xu_debug_group2[74:78] = lru_debug_q[36:40]; + assign derat_xu_debug_group2[79:83] = watermark_q[0:4]; + assign derat_xu_debug_group2[84] = ex4_cam_hit_q; + assign derat_xu_debug_group2[85] = ex4_debug_q[0]; + assign derat_xu_debug_group2[86] = ex4_debug_q[1]; + assign derat_xu_debug_group2[87] = ex4_debug_q[9]; + assign derat_xu_debug_group3[0] = ex4_cam_hit_q; + assign derat_xu_debug_group3[1] = ex4_debug_q[0]; + assign derat_xu_debug_group3[2] = ex4_debug_q[1]; + assign derat_xu_debug_group3[3] = ex4_debug_q[9]; + assign derat_xu_debug_group3[4:8] = ex4_debug_q[11:15]; + assign derat_xu_debug_group3[9] = lru_update_event_q[9]; + assign derat_xu_debug_group3[10:14] = lru_debug_q[0:4]; + assign derat_xu_debug_group3[15:19] = watermark_q[0:4]; + assign derat_xu_debug_group3[20] = 1'b0; + assign derat_xu_debug_group3[21:51] = lru_q[1:31]; + assign derat_xu_debug_group3[52:82] = lru_debug_q[5:35]; + assign derat_xu_debug_group3[83:87] = lru_debug_q[36:40]; + // unused spare signal assignments + assign unused_dc[0] = |(lcb_delay_lclkr_dc[1:4]); + assign unused_dc[1] = |(lcb_mpw1_dc_b[1:4]); + assign unused_dc[2] = mchk_flash_inv_q[3]; + assign unused_dc[3] = 1'b0; + assign unused_dc[4] = pc_func_sl_force; + assign unused_dc[5] = pc_func_sl_thold_0_b; + assign unused_dc[6] = 1'b0; + assign unused_dc[7] = |(ex2_rs_is_q); + assign unused_dc[8] = |(ex2_ra_entry_q); + assign unused_dc[9] = |(cam_hit_entry); + assign unused_dc[10] = |(ex3_first_hit_entry); + assign unused_dc[11] = |(ex4_dsi_q[8:8 + `THREADS - 1]); + assign unused_dc[12] = |(ex4_noop_touch_q[1:2]); + assign unused_dc[13] = |(ex4_noop_touch_q[8:8 + `THREADS - 1]); + assign unused_dc[14] = |(ex4_attr_q); + assign unused_dc[15] = ex4_rd_cam_data_q[56]; + assign unused_dc[16] = |(ex7_rs_is_q); + assign unused_dc[17] = ex7_state_q[0]; + assign unused_dc[18] = ex8_ttype_q[0]; + assign unused_dc[19] = |(ex8_ttype_q[2:11]); + assign unused_dc[20] = |(tlb_rel_data_q[eratpos_rpnrsvd:eratpos_rpnrsvd + 3]); + assign unused_dc[21] = 1'b0; + assign unused_dc[22] = 1'b0; + assign unused_dc[23] = 1'b0; + assign unused_dc[24] = |(attr_np2[0:1]); + assign unused_dc[25] = attr_np2[4]; + assign unused_dc[26] = mmucr1_b0_cpy_q; + assign unused_dc[27] = |(bcfg_q_b[0:15]); + assign unused_dc[28] = |(bcfg_q_b[16:31]); + assign unused_dc[29] = |(bcfg_q_b[32:47]); + assign unused_dc[30] = |(bcfg_q_b[48:51]); + assign unused_dc[31] = |(bcfg_q_b[52:61]); + assign unused_dc[32] = |(bcfg_q_b[62:77]); + assign unused_dc[33] = |(bcfg_q_b[78:81]); + assign unused_dc[34] = |(bcfg_q_b[82:86]); + assign unused_dc[35] = |(por_wr_array_data[51:67]); + assign unused_dc[36] = |(bcfg_q_b[87:102]); + assign unused_dc[37] = |(bcfg_q_b[103:106]); + assign unused_dc[38] = |(bcfg_q[107:122]); + assign unused_dc[39] = |(bcfg_q_b[107:122]); + //--------------------------------------------------------------------- + // Latches + //--------------------------------------------------------------------- + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_msr_hv_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_msr_hv_offset:spr_msr_hv_offset + `THREADS - 1]), + .scout(sov_0[spr_msr_hv_offset:spr_msr_hv_offset + `THREADS - 1]), + .din(spr_msr_hv_d), + .dout(spr_msr_hv_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_msr_pr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_msr_pr_offset:spr_msr_pr_offset + `THREADS - 1]), + .scout(sov_0[spr_msr_pr_offset:spr_msr_pr_offset + `THREADS - 1]), + .din(spr_msr_pr_d), + .dout(spr_msr_pr_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_msr_ds_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_msr_ds_offset:spr_msr_ds_offset + `THREADS - 1]), + .scout(sov_0[spr_msr_ds_offset:spr_msr_ds_offset + `THREADS - 1]), + .din(spr_msr_ds_d), + .dout(spr_msr_ds_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_msr_cm_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_msr_cm_offset:spr_msr_cm_offset + `THREADS - 1]), + .scout(sov_0[spr_msr_cm_offset:spr_msr_cm_offset + `THREADS - 1]), + .din(spr_msr_cm_d), + .dout(spr_msr_cm_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_ccr2_notlb_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_ccr2_notlb_offset]), + .scout(sov_0[spr_ccr2_notlb_offset]), + .din(spr_ccr2_notlb_d), + .dout(spr_ccr2_notlb_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) mchk_flash_inv_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mchk_flash_inv_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[mchk_flash_inv_offset:mchk_flash_inv_offset + 4 - 1]), + .scout(sov_0[mchk_flash_inv_offset:mchk_flash_inv_offset + 4 - 1]), + .din(mchk_flash_inv_d), + .dout(mchk_flash_inv_q) + ); + + tri_rlmlatch_p #(.INIT(1), .NEEDS_SRESET(1)) xucr4_mmu_mchk_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[xucr4_mmu_mchk_offset]), + .scout(sov_0[xucr4_mmu_mchk_offset]), + .din(xu_lq_spr_xucr4_mmu_mchk), + .dout(xucr4_mmu_mchk_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) cp_next_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[cp_next_val_offset:cp_next_val_offset + `THREADS - 1]), + .scout(sov_0[cp_next_val_offset:cp_next_val_offset + `THREADS - 1]), + .din(cp_next_val_d), + .dout(cp_next_val_q) + ); + generate + + genvar tid; + + for (tid = 0; tid <= `THREADS - 1; tid = tid + 1) + begin : cp_next_itag + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) cp_next_itag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[cp_next_itag_offset + `ITAG_SIZE_ENC * tid:cp_next_itag_offset + `ITAG_SIZE_ENC * (tid + 1) - 1]), + .scout(sov_0[cp_next_itag_offset + `ITAG_SIZE_ENC * tid:cp_next_itag_offset + `ITAG_SIZE_ENC * (tid + 1) - 1]), + .din(iu_lq_cp_next_itag[tid*`ITAG_SIZE_ENC:(tid*`ITAG_SIZE_ENC)+`ITAG_SIZE_ENC-1]), + .dout(cp_next_itag_q[tid]) + ); + end + + for (tid = 0; tid <= `THREADS - 1; tid = tid + 1) + begin : rpn_holdreg + + tri_rlmreg_p #(.WIDTH(64), .INIT(0), .NEEDS_SRESET(1)) rpn_holdreg_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[rpn_holdreg_offset + (64 * tid):rpn_holdreg_offset + (64 * (tid + 1)) - 1]), + .scout(sov_1[rpn_holdreg_offset + (64 * tid):rpn_holdreg_offset + (64 * (tid + 1)) - 1]), + .din(rpn_holdreg_d[tid][0:63]), + .dout(rpn_holdreg_q[tid][0:63]) + ); + end + + endgenerate + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_byte_rev_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex2_byte_rev_offset]), + .scout(sov_0[ex2_byte_rev_offset]), + .din(ex2_byte_rev_d), + .dout(ex2_byte_rev_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_byte_rev_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex3_byte_rev_offset]), + .scout(sov_0[ex3_byte_rev_offset]), + .din(ex3_byte_rev_d), + .dout(ex3_byte_rev_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex1_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex1_valid_offset:ex1_valid_offset + `THREADS - 1]), + .scout(sov_0[ex1_valid_offset:ex1_valid_offset + `THREADS - 1]), + .din(ex1_valid_d[0:`THREADS - 1]), + .dout(ex1_valid_q[0:`THREADS - 1]) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex1_ttype_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex1_ttype_offset:ex1_ttype_offset + 2 - 1]), + .scout(sov_0[ex1_ttype_offset:ex1_ttype_offset + 2 - 1]), + .din(ex1_ttype_d), + .dout(ex1_ttype_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex2_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex2_valid_offset:ex2_valid_offset + `THREADS - 1]), + .scout(sov_0[ex2_valid_offset:ex2_valid_offset + `THREADS - 1]), + .din(ex2_valid_d[0:`THREADS - 1]), + .dout(ex2_valid_q[0:`THREADS - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex2_pfetch_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex2_pfetch_val_offset:ex2_pfetch_val_offset + `THREADS - 1]), + .scout(sov_0[ex2_pfetch_val_offset:ex2_pfetch_val_offset + `THREADS - 1]), + .din(ex2_pfetch_val_d[0:`THREADS - 1]), + .dout(ex2_pfetch_val_q[0:`THREADS - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex2_itag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex2_itag_offset:ex2_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov_0[ex2_itag_offset:ex2_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(ex2_itag_d[0:`ITAG_SIZE_ENC - 1]), + .dout(ex2_itag_q[0:`ITAG_SIZE_ENC - 1]) + ); + + tri_rlmreg_p #(.WIDTH(ttype_width), .INIT(0), .NEEDS_SRESET(1)) ex2_ttype_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex2_ttype_offset:ex2_ttype_offset + ttype_width - 1]), + .scout(sov_0[ex2_ttype_offset:ex2_ttype_offset + ttype_width - 1]), + .din(ex2_ttype_d), + .dout(ex2_ttype_q) + ); + + tri_rlmreg_p #(.WIDTH(ws_width), .INIT(0), .NEEDS_SRESET(1)) ex2_ws_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex2_ws_offset:ex2_ws_offset + ws_width - 1]), + .scout(sov_0[ex2_ws_offset:ex2_ws_offset + ws_width - 1]), + .din(ex2_ws_d[0:ws_width - 1]), + .dout(ex2_ws_q[0:ws_width - 1]) + ); + // next 2 latches should not be needed + + tri_rlmreg_p #(.WIDTH(rs_is_width), .INIT(0), .NEEDS_SRESET(1)) ex2_rs_is_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex2_rs_is_offset:ex2_rs_is_offset + rs_is_width - 1]), + .scout(sov_0[ex2_rs_is_offset:ex2_rs_is_offset + rs_is_width - 1]), + .din(ex2_rs_is_d[0:rs_is_width - 1]), + .dout(ex2_rs_is_q[0:rs_is_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) ex2_ra_entry_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex2_ra_entry_offset:ex2_ra_entry_offset + 5 - 1]), + .scout(sov_0[ex2_ra_entry_offset:ex2_ra_entry_offset + 5 - 1]), + .din(ex2_ra_entry_d), + .dout(ex2_ra_entry_q) + ); + + tri_rlmreg_p #(.WIDTH(state_width), .INIT(0), .NEEDS_SRESET(1)) ex2_state_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex2_state_offset:ex2_state_offset + state_width - 1]), + .scout(sov_0[ex2_state_offset:ex2_state_offset + state_width - 1]), + .din(ex2_state_d[0:state_width - 1]), + .dout(ex2_state_q[0:state_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(pid_width), .INIT(0), .NEEDS_SRESET(1)) ex2_pid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex2_pid_offset:ex2_pid_offset + pid_width - 1]), + .scout(sov_0[ex2_pid_offset:ex2_pid_offset + pid_width - 1]), + .din(ex2_pid_d), + .dout(ex2_pid_q) + ); + + tri_rlmreg_p #(.WIDTH(extclass_width), .INIT(0), .NEEDS_SRESET(1)) ex2_extclass_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex2_extclass_offset:ex2_extclass_offset + extclass_width - 1]), + .scout(sov_0[ex2_extclass_offset:ex2_extclass_offset + extclass_width - 1]), + .din(ex2_extclass_d[0:extclass_width - 1]), + .dout(ex2_extclass_q[0:extclass_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(tlbsel_width), .INIT(0), .NEEDS_SRESET(1)) ex2_tlbsel_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex2_tlbsel_offset:ex2_tlbsel_offset + tlbsel_width - 1]), + .scout(sov_0[ex2_tlbsel_offset:ex2_tlbsel_offset + tlbsel_width - 1]), + .din(ex2_tlbsel_d[0:tlbsel_width - 1]), + .dout(ex2_tlbsel_q[0:tlbsel_width - 1]) + ); + //------------------------------------------------ + + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex2_data_in_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex1_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex2_data_in_offset:ex2_data_in_offset + (`GPR_WIDTH) - 1]), + .scout(sov_0[ex2_data_in_offset:ex2_data_in_offset + (`GPR_WIDTH) - 1]), + .din(ex2_data_in_d[64 - `GPR_WIDTH:63]), + .dout(ex2_data_in_q[64 - `GPR_WIDTH:63]) + ); + //----------------------------------------------------------------------------- + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex3_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex3_valid_offset:ex3_valid_offset + `THREADS - 1]), + .scout(sov_0[ex3_valid_offset:ex3_valid_offset + `THREADS - 1]), + .din(ex3_valid_d[0:`THREADS - 1]), + .dout(ex3_valid_q[0:`THREADS - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex3_pfetch_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex3_pfetch_val_offset:ex3_pfetch_val_offset + `THREADS - 1]), + .scout(sov_0[ex3_pfetch_val_offset:ex3_pfetch_val_offset + `THREADS - 1]), + .din(ex3_pfetch_val_d[0:`THREADS - 1]), + .dout(ex3_pfetch_val_q[0:`THREADS - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex3_itag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex3_itag_offset:ex3_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov_0[ex3_itag_offset:ex3_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(ex3_itag_d[0:`ITAG_SIZE_ENC - 1]), + .dout(ex3_itag_q[0:`ITAG_SIZE_ENC - 1]) + ); + + tri_rlmreg_p #(.WIDTH(ttype_width), .INIT(0), .NEEDS_SRESET(1)) ex3_ttype_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex3_ttype_offset:ex3_ttype_offset + ttype_width - 1]), + .scout(sov_0[ex3_ttype_offset:ex3_ttype_offset + ttype_width - 1]), + .din(ex3_ttype_d[0:ttype_width - 1]), + .dout(ex3_ttype_q[0:ttype_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(ws_width), .INIT(0), .NEEDS_SRESET(1)) ex3_ws_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex3_ws_offset:ex3_ws_offset + ws_width - 1]), + .scout(sov_0[ex3_ws_offset:ex3_ws_offset + ws_width - 1]), + .din(ex3_ws_d[0:ws_width - 1]), + .dout(ex3_ws_q[0:ws_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(rs_is_width), .INIT(0), .NEEDS_SRESET(1)) ex3_rs_is_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex3_rs_is_offset:ex3_rs_is_offset + rs_is_width - 1]), + .scout(sov_0[ex3_rs_is_offset:ex3_rs_is_offset + rs_is_width - 1]), + .din(ex3_rs_is_d[0:rs_is_width - 1]), + .dout(ex3_rs_is_q[0:rs_is_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) ex3_ra_entry_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex3_ra_entry_offset:ex3_ra_entry_offset + 5 - 1]), + .scout(sov_0[ex3_ra_entry_offset:ex3_ra_entry_offset + 5 - 1]), + .din(ex3_ra_entry_d), + .dout(ex3_ra_entry_q) + ); + + tri_rlmreg_p #(.WIDTH(state_width), .INIT(0), .NEEDS_SRESET(1)) ex3_state_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex3_state_offset:ex3_state_offset + state_width - 1]), + .scout(sov_0[ex3_state_offset:ex3_state_offset + state_width - 1]), + .din(ex3_state_d[0:state_width - 1]), + .dout(ex3_state_q[0:state_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(pid_width), .INIT(0), .NEEDS_SRESET(1)) ex3_pid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex3_pid_offset:ex3_pid_offset + pid_width - 1]), + .scout(sov_0[ex3_pid_offset:ex3_pid_offset + pid_width - 1]), + .din(ex3_pid_d), + .dout(ex3_pid_q) + ); + + tri_rlmreg_p #(.WIDTH(extclass_width), .INIT(0), .NEEDS_SRESET(1)) ex3_extclass_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex3_extclass_offset:ex3_extclass_offset + extclass_width - 1]), + .scout(sov_0[ex3_extclass_offset:ex3_extclass_offset + extclass_width - 1]), + .din(ex3_extclass_d[0:extclass_width - 1]), + .dout(ex3_extclass_q[0:extclass_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(tlbsel_width), .INIT(0), .NEEDS_SRESET(1)) ex3_tlbsel_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex3_tlbsel_offset:ex3_tlbsel_offset + tlbsel_width - 1]), + .scout(sov_0[ex3_tlbsel_offset:ex3_tlbsel_offset + tlbsel_width - 1]), + .din(ex3_tlbsel_d[0:tlbsel_width - 1]), + .dout(ex3_tlbsel_q[0:tlbsel_width - 1]) + ); + //----------------------------------------------------------------------------- + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex4_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex4_valid_offset:ex4_valid_offset + `THREADS - 1]), + .scout(sov_0[ex4_valid_offset:ex4_valid_offset + `THREADS - 1]), + .din(ex4_valid_d[0:`THREADS - 1]), + .dout(ex4_valid_q[0:`THREADS - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex4_pfetch_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex4_pfetch_val_offset:ex4_pfetch_val_offset + `THREADS - 1]), + .scout(sov_0[ex4_pfetch_val_offset:ex4_pfetch_val_offset + `THREADS - 1]), + .din(ex4_pfetch_val_d[0:`THREADS - 1]), + .dout(ex4_pfetch_val_q[0:`THREADS - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex4_itag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex4_itag_offset:ex4_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov_0[ex4_itag_offset:ex4_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(ex4_itag_d[0:`ITAG_SIZE_ENC - 1]), + .dout(ex4_itag_q[0:`ITAG_SIZE_ENC - 1]) + ); + + tri_rlmreg_p #(.WIDTH(ttype_width), .INIT(0), .NEEDS_SRESET(1)) ex4_ttype_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex4_ttype_offset:ex4_ttype_offset + ttype_width - 1]), + .scout(sov_0[ex4_ttype_offset:ex4_ttype_offset + ttype_width - 1]), + .din(ex4_ttype_d[0:ttype_width - 1]), + .dout(ex4_ttype_q[0:ttype_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(ws_width), .INIT(0), .NEEDS_SRESET(1)) ex4_ws_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex4_ws_offset:ex4_ws_offset + ws_width - 1]), + .scout(sov_0[ex4_ws_offset:ex4_ws_offset + ws_width - 1]), + .din(ex4_ws_d[0:ws_width - 1]), + .dout(ex4_ws_q[0:ws_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(rs_is_width), .INIT(0), .NEEDS_SRESET(1)) ex4_rs_is_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex4_rs_is_offset:ex4_rs_is_offset + rs_is_width - 1]), + .scout(sov_0[ex4_rs_is_offset:ex4_rs_is_offset + rs_is_width - 1]), + .din(ex4_rs_is_d[0:rs_is_width - 1]), + .dout(ex4_rs_is_q[0:rs_is_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) ex4_ra_entry_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex4_ra_entry_offset:ex4_ra_entry_offset + 5 - 1]), + .scout(sov_0[ex4_ra_entry_offset:ex4_ra_entry_offset + 5 - 1]), + .din(ex4_ra_entry_d), + .dout(ex4_ra_entry_q) + ); + + tri_rlmreg_p #(.WIDTH(state_width), .INIT(0), .NEEDS_SRESET(1)) ex4_state_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex4_state_offset:ex4_state_offset + state_width - 1]), + .scout(sov_0[ex4_state_offset:ex4_state_offset + state_width - 1]), + .din(ex4_state_d[0:state_width - 1]), + .dout(ex4_state_q[0:state_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(pid_width), .INIT(0), .NEEDS_SRESET(1)) ex4_pid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex4_pid_offset:ex4_pid_offset + pid_width - 1]), + .scout(sov_0[ex4_pid_offset:ex4_pid_offset + pid_width - 1]), + .din(ex4_pid_d), + .dout(ex4_pid_q) + ); + + tri_rlmreg_p #(.WIDTH(lpid_width), .INIT(0), .NEEDS_SRESET(1)) ex4_lpid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex4_lpid_offset:ex4_lpid_offset + lpid_width - 1]), + .scout(sov_0[ex4_lpid_offset:ex4_lpid_offset + lpid_width - 1]), + .din(ex4_lpid_d), + .dout(ex4_lpid_q) + ); + + tri_rlmreg_p #(.WIDTH(extclass_width), .INIT(0), .NEEDS_SRESET(1)) ex4_extclass_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex4_extclass_offset:ex4_extclass_offset + extclass_width - 1]), + .scout(sov_0[ex4_extclass_offset:ex4_extclass_offset + extclass_width - 1]), + .din(ex4_extclass_d[0:extclass_width - 1]), + .dout(ex4_extclass_q[0:extclass_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(tlbsel_width), .INIT(0), .NEEDS_SRESET(1)) ex4_tlbsel_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex4_tlbsel_offset:ex4_tlbsel_offset + tlbsel_width - 1]), + .scout(sov_0[ex4_tlbsel_offset:ex4_tlbsel_offset + tlbsel_width - 1]), + .din(ex4_tlbsel_d[0:tlbsel_width - 1]), + .dout(ex4_tlbsel_q[0:tlbsel_width - 1]) + ); + //----------------------------------------------------------------------------- + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex5_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex5_valid_offset:ex5_valid_offset + `THREADS - 1]), + .scout(sov_0[ex5_valid_offset:ex5_valid_offset + `THREADS - 1]), + .din(ex5_valid_d[0:`THREADS - 1]), + .dout(ex5_valid_q[0:`THREADS - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex5_pfetch_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex5_pfetch_val_offset:ex5_pfetch_val_offset + `THREADS - 1]), + .scout(sov_0[ex5_pfetch_val_offset:ex5_pfetch_val_offset + `THREADS - 1]), + .din(ex5_pfetch_val_d[0:`THREADS - 1]), + .dout(ex5_pfetch_val_q[0:`THREADS - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex5_itag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex5_itag_offset:ex5_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov_0[ex5_itag_offset:ex5_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(ex5_itag_d[0:`ITAG_SIZE_ENC - 1]), + .dout(ex5_itag_q[0:`ITAG_SIZE_ENC - 1]) + ); + + tri_rlmreg_p #(.WIDTH(ttype_width), .INIT(0), .NEEDS_SRESET(1)) ex5_ttype_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex5_ttype_offset:ex5_ttype_offset + ttype_width - 1]), + .scout(sov_0[ex5_ttype_offset:ex5_ttype_offset + ttype_width - 1]), + .din(ex5_ttype_d[0:ttype_width - 1]), + .dout(ex5_ttype_q[0:ttype_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(ws_width), .INIT(0), .NEEDS_SRESET(1)) ex5_ws_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex5_ws_offset:ex5_ws_offset + ws_width - 1]), + .scout(sov_0[ex5_ws_offset:ex5_ws_offset + ws_width - 1]), + .din(ex5_ws_d[0:ws_width - 1]), + .dout(ex5_ws_q[0:ws_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(rs_is_width), .INIT(0), .NEEDS_SRESET(1)) ex5_rs_is_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex5_rs_is_offset:ex5_rs_is_offset + rs_is_width - 1]), + .scout(sov_0[ex5_rs_is_offset:ex5_rs_is_offset + rs_is_width - 1]), + .din(ex5_rs_is_d[0:rs_is_width - 1]), + .dout(ex5_rs_is_q[0:rs_is_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) ex5_ra_entry_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex5_ra_entry_offset:ex5_ra_entry_offset + 5 - 1]), + .scout(sov_0[ex5_ra_entry_offset:ex5_ra_entry_offset + 5 - 1]), + .din(ex5_ra_entry_d), + .dout(ex5_ra_entry_q) + ); + + tri_rlmreg_p #(.WIDTH(state_width), .INIT(0), .NEEDS_SRESET(1)) ex5_state_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex5_state_offset:ex5_state_offset + state_width - 1]), + .scout(sov_0[ex5_state_offset:ex5_state_offset + state_width - 1]), + .din(ex5_state_d[0:state_width - 1]), + .dout(ex5_state_q[0:state_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(pid_width), .INIT(0), .NEEDS_SRESET(1)) ex5_pid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex5_pid_offset:ex5_pid_offset + pid_width - 1]), + .scout(sov_0[ex5_pid_offset:ex5_pid_offset + pid_width - 1]), + .din(ex5_pid_d), + .dout(ex5_pid_q) + ); + + tri_rlmreg_p #(.WIDTH(lpid_width), .INIT(0), .NEEDS_SRESET(1)) ex5_lpid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex5_lpid_offset:ex5_lpid_offset + lpid_width - 1]), + .scout(sov_0[ex5_lpid_offset:ex5_lpid_offset + lpid_width - 1]), + .din(ex5_lpid_d), + .dout(ex5_lpid_q) + ); + + tri_rlmreg_p #(.WIDTH(extclass_width), .INIT(0), .NEEDS_SRESET(1)) ex5_extclass_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex5_extclass_offset:ex5_extclass_offset + extclass_width - 1]), + .scout(sov_0[ex5_extclass_offset:ex5_extclass_offset + extclass_width - 1]), + .din(ex5_extclass_d[0:extclass_width - 1]), + .dout(ex5_extclass_q[0:extclass_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(tlbsel_width), .INIT(0), .NEEDS_SRESET(1)) ex5_tlbsel_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex5_tlbsel_offset:ex5_tlbsel_offset + tlbsel_width - 1]), + .scout(sov_0[ex5_tlbsel_offset:ex5_tlbsel_offset + tlbsel_width - 1]), + .din(ex5_tlbsel_d[0:tlbsel_width - 1]), + .dout(ex5_tlbsel_q[0:tlbsel_width - 1]) + ); + //----------------------------------------------------------------------------- + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex6_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex6_valid_offset:ex6_valid_offset + `THREADS - 1]), + .scout(sov_0[ex6_valid_offset:ex6_valid_offset + `THREADS - 1]), + .din(ex6_valid_d[0:`THREADS - 1]), + .dout(ex6_valid_q[0:`THREADS - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex6_pfetch_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex6_pfetch_val_offset:ex6_pfetch_val_offset + `THREADS - 1]), + .scout(sov_0[ex6_pfetch_val_offset:ex6_pfetch_val_offset + `THREADS - 1]), + .din(ex6_pfetch_val_d[0:`THREADS - 1]), + .dout(ex6_pfetch_val_q[0:`THREADS - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex6_itag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex6_itag_offset:ex6_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov_0[ex6_itag_offset:ex6_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(ex6_itag_d[0:`ITAG_SIZE_ENC - 1]), + .dout(ex6_itag_q[0:`ITAG_SIZE_ENC - 1]) + ); + + tri_rlmreg_p #(.WIDTH(ttype_width), .INIT(0), .NEEDS_SRESET(1)) ex6_ttype_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex6_ttype_offset:ex6_ttype_offset + ttype_width - 1]), + .scout(sov_0[ex6_ttype_offset:ex6_ttype_offset + ttype_width - 1]), + .din(ex6_ttype_d[0:ttype_width - 1]), + .dout(ex6_ttype_q[0:ttype_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(ws_width), .INIT(0), .NEEDS_SRESET(1)) ex6_ws_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex6_ws_offset:ex6_ws_offset + ws_width - 1]), + .scout(sov_0[ex6_ws_offset:ex6_ws_offset + ws_width - 1]), + .din(ex6_ws_d[0:ws_width - 1]), + .dout(ex6_ws_q[0:ws_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(rs_is_width), .INIT(0), .NEEDS_SRESET(1)) ex6_rs_is_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex6_rs_is_offset:ex6_rs_is_offset + rs_is_width - 1]), + .scout(sov_0[ex6_rs_is_offset:ex6_rs_is_offset + rs_is_width - 1]), + .din(ex6_rs_is_d[0:rs_is_width - 1]), + .dout(ex6_rs_is_q[0:rs_is_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) ex6_ra_entry_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex6_ra_entry_offset:ex6_ra_entry_offset + 5 - 1]), + .scout(sov_0[ex6_ra_entry_offset:ex6_ra_entry_offset + 5 - 1]), + .din(ex6_ra_entry_d), + .dout(ex6_ra_entry_q) + ); + + tri_rlmreg_p #(.WIDTH(state_width), .INIT(0), .NEEDS_SRESET(1)) ex6_state_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex6_state_offset:ex6_state_offset + state_width - 1]), + .scout(sov_0[ex6_state_offset:ex6_state_offset + state_width - 1]), + .din(ex6_state_d[0:state_width - 1]), + .dout(ex6_state_q[0:state_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(pid_width), .INIT(0), .NEEDS_SRESET(1)) ex6_pid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex6_pid_offset:ex6_pid_offset + pid_width - 1]), + .scout(sov_0[ex6_pid_offset:ex6_pid_offset + pid_width - 1]), + .din(ex6_pid_d), + .dout(ex6_pid_q) + ); + + tri_rlmreg_p #(.WIDTH(extclass_width), .INIT(0), .NEEDS_SRESET(1)) ex6_extclass_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex6_extclass_offset:ex6_extclass_offset + extclass_width - 1]), + .scout(sov_0[ex6_extclass_offset:ex6_extclass_offset + extclass_width - 1]), + .din(ex6_extclass_d[0:extclass_width - 1]), + .dout(ex6_extclass_q[0:extclass_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(tlbsel_width), .INIT(0), .NEEDS_SRESET(1)) ex6_tlbsel_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex6_tlbsel_offset:ex6_tlbsel_offset + tlbsel_width - 1]), + .scout(sov_0[ex6_tlbsel_offset:ex6_tlbsel_offset + tlbsel_width - 1]), + .din(ex6_tlbsel_d[0:tlbsel_width - 1]), + .dout(ex6_tlbsel_q[0:tlbsel_width - 1]) + ); + //----------------------------------------------------------------------------- + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex7_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex7_valid_offset:ex7_valid_offset + `THREADS - 1]), + .scout(sov_0[ex7_valid_offset:ex7_valid_offset + `THREADS - 1]), + .din(ex7_valid_d[0:`THREADS - 1]), + .dout(ex7_valid_q[0:`THREADS - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex7_pfetch_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex7_pfetch_val_offset:ex7_pfetch_val_offset + `THREADS - 1]), + .scout(sov_0[ex7_pfetch_val_offset:ex7_pfetch_val_offset + `THREADS - 1]), + .din(ex7_pfetch_val_d[0:`THREADS - 1]), + .dout(ex7_pfetch_val_q[0:`THREADS - 1]) + ); + + tri_rlmreg_p #(.WIDTH(ttype_width), .INIT(0), .NEEDS_SRESET(1)) ex7_ttype_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex7_ttype_offset:ex7_ttype_offset + ttype_width - 1]), + .scout(sov_0[ex7_ttype_offset:ex7_ttype_offset + ttype_width - 1]), + .din(ex7_ttype_d[0:ttype_width - 1]), + .dout(ex7_ttype_q[0:ttype_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(ws_width), .INIT(0), .NEEDS_SRESET(1)) ex7_ws_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex6_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex7_ws_offset:ex7_ws_offset + ws_width - 1]), + .scout(sov_0[ex7_ws_offset:ex7_ws_offset + ws_width - 1]), + .din(ex7_ws_d[0:ws_width - 1]), + .dout(ex7_ws_q[0:ws_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(rs_is_width), .INIT(0), .NEEDS_SRESET(1)) ex7_rs_is_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex6_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex7_rs_is_offset:ex7_rs_is_offset + rs_is_width - 1]), + .scout(sov_0[ex7_rs_is_offset:ex7_rs_is_offset + rs_is_width - 1]), + .din(ex7_rs_is_d[0:rs_is_width - 1]), + .dout(ex7_rs_is_q[0:rs_is_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) ex7_ra_entry_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex6_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex7_ra_entry_offset:ex7_ra_entry_offset + 5 - 1]), + .scout(sov_0[ex7_ra_entry_offset:ex7_ra_entry_offset + 5 - 1]), + .din(ex7_ra_entry_d), + .dout(ex7_ra_entry_q) + ); + + tri_rlmreg_p #(.WIDTH(state_width), .INIT(0), .NEEDS_SRESET(1)) ex7_state_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex6_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex7_state_offset:ex7_state_offset + state_width - 1]), + .scout(sov_0[ex7_state_offset:ex7_state_offset + state_width - 1]), + .din(ex7_state_d[0:state_width - 1]), + .dout(ex7_state_q[0:state_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(pid_width), .INIT(0), .NEEDS_SRESET(1)) ex7_pid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex6_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex7_pid_offset:ex7_pid_offset + pid_width - 1]), + .scout(sov_0[ex7_pid_offset:ex7_pid_offset + pid_width - 1]), + .din(ex7_pid_d), + .dout(ex7_pid_q) + ); + + tri_rlmreg_p #(.WIDTH(extclass_width), .INIT(0), .NEEDS_SRESET(1)) ex7_extclass_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex6_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex7_extclass_offset:ex7_extclass_offset + extclass_width - 1]), + .scout(sov_0[ex7_extclass_offset:ex7_extclass_offset + extclass_width - 1]), + .din(ex7_extclass_d[0:extclass_width - 1]), + .dout(ex7_extclass_q[0:extclass_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(tlbsel_width), .INIT(0), .NEEDS_SRESET(1)) ex7_tlbsel_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex6_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex7_tlbsel_offset:ex7_tlbsel_offset + tlbsel_width - 1]), + .scout(sov_0[ex7_tlbsel_offset:ex7_tlbsel_offset + tlbsel_width - 1]), + .din(ex7_tlbsel_d[0:tlbsel_width - 1]), + .dout(ex7_tlbsel_q[0:tlbsel_width - 1]) + ); + //----------------------------------------------------------------------------- + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex8_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex8_valid_offset:ex8_valid_offset + `THREADS - 1]), + .scout(sov_0[ex8_valid_offset:ex8_valid_offset + `THREADS - 1]), + .din(ex8_valid_d[0:`THREADS - 1]), + .dout(ex8_valid_q[0:`THREADS - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex8_pfetch_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex8_pfetch_val_offset:ex8_pfetch_val_offset + `THREADS - 1]), + .scout(sov_0[ex8_pfetch_val_offset:ex8_pfetch_val_offset + `THREADS - 1]), + .din(ex8_pfetch_val_d[0:`THREADS - 1]), + .dout(ex8_pfetch_val_q[0:`THREADS - 1]) + ); + + tri_rlmreg_p #(.WIDTH(ttype_width), .INIT(0), .NEEDS_SRESET(1)) ex8_ttype_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex8_ttype_offset:ex8_ttype_offset + ttype_width - 1]), + .scout(sov_0[ex8_ttype_offset:ex8_ttype_offset + ttype_width - 1]), + .din(ex8_ttype_d[0:ttype_width - 1]), + .dout(ex8_ttype_q[0:ttype_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(tlbsel_width), .INIT(0), .NEEDS_SRESET(1)) ex8_tlbsel_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex8_tlbsel_offset:ex8_tlbsel_offset + tlbsel_width - 1]), + .scout(sov_0[ex8_tlbsel_offset:ex8_tlbsel_offset + tlbsel_width - 1]), + .din(ex8_tlbsel_d[0:tlbsel_width - 1]), + .dout(ex8_tlbsel_q[0:tlbsel_width - 1]) + ); + //------------------------------------------------ + + tri_rlmreg_p #(.WIDTH(GPR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex5_data_out_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex5_data_out_offset:ex5_data_out_offset + GPR_WIDTH - 1]), + .scout(sov_0[ex5_data_out_offset:ex5_data_out_offset + GPR_WIDTH - 1]), + .din(ex5_data_out_d[64 - GPR_WIDTH:63]), + .dout(ex5_data_out_q[64 - GPR_WIDTH:63]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_req_inprogress_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_req_inprogress_offset]), + .scout(sov_0[tlb_req_inprogress_offset]), + .din(tlb_req_inprogress_d), + .dout(tlb_req_inprogress_q) + ); + + tri_rlmreg_p #(.WIDTH((7+(2*`THREADS)+1)), .INIT(0), .NEEDS_SRESET(1)) ex3_dsi_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex3_dsi_offset:ex3_dsi_offset + (7+(2*`THREADS)+1) - 1]), + .scout(sov_0[ex3_dsi_offset:ex3_dsi_offset + (7+(2*`THREADS)+1) - 1]), + .din(ex3_dsi_d), + .dout(ex3_dsi_q) + ); + + tri_rlmreg_p #(.WIDTH((7+(2*`THREADS)+1)), .INIT(0), .NEEDS_SRESET(1)) ex3_noop_touch_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex3_noop_touch_offset:ex3_noop_touch_offset + (7+(2*`THREADS)+1) - 1]), + .scout(sov_0[ex3_noop_touch_offset:ex3_noop_touch_offset + (7+(2*`THREADS)+1) - 1]), + .din(ex3_noop_touch_d), + .dout(ex3_noop_touch_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex4_miss_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex4_miss_offset:ex4_miss_offset + `THREADS - 1]), + .scout(sov_0[ex4_miss_offset:ex4_miss_offset + `THREADS - 1]), + .din(ex4_miss_d[0:`THREADS - 1]), + .dout(ex4_miss_q[0:`THREADS - 1]) + ); + + tri_rlmreg_p #(.WIDTH((7+(2*`THREADS)+1)), .INIT(0), .NEEDS_SRESET(1)) ex4_dsi_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex4_dsi_offset:ex4_dsi_offset + (7+(2*`THREADS)+1) - 1]), + .scout(sov_0[ex4_dsi_offset:ex4_dsi_offset + (7+(2*`THREADS)+1) - 1]), + .din(ex4_dsi_d), + .dout(ex4_dsi_q) + ); + + tri_rlmreg_p #(.WIDTH((7+(2*`THREADS)+1)), .INIT(0), .NEEDS_SRESET(1)) ex4_noop_touch_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex4_noop_touch_offset:ex4_noop_touch_offset + (7+(2*`THREADS)+1) - 1]), + .scout(sov_0[ex4_noop_touch_offset:ex4_noop_touch_offset + (7+(2*`THREADS)+1) - 1]), + .din(ex4_noop_touch_d), + .dout(ex4_noop_touch_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex4_multihit_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex4_multihit_offset:ex4_multihit_offset + `THREADS - 1]), + .scout(sov_0[ex4_multihit_offset:ex4_multihit_offset + `THREADS - 1]), + .din(ex4_multihit_d[0:`THREADS - 1]), + .dout(ex4_multihit_q[0:`THREADS - 1]) + ); + + tri_rlmreg_p #(.WIDTH(num_entry), .INIT(0), .NEEDS_SRESET(1)) ex4_multihit_b_pt_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex4_multihit_b_pt_offset:ex4_multihit_b_pt_offset + num_entry - 1]), + .scout(sov_0[ex4_multihit_b_pt_offset:ex4_multihit_b_pt_offset + num_entry - 1]), + .din(ex4_multihit_b_pt_d), + .dout(ex4_multihit_b_pt_q) + ); + + tri_rlmreg_p #(.WIDTH((num_entry-1)), .INIT(0), .NEEDS_SRESET(1)) ex4_first_hit_entry_pt_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex4_first_hit_entry_pt_offset:ex4_first_hit_entry_pt_offset + (num_entry-1) - 1]), + .scout(sov_0[ex4_first_hit_entry_pt_offset:ex4_first_hit_entry_pt_offset + (num_entry-1) - 1]), + .din(ex4_first_hit_entry_pt_d), + .dout(ex4_first_hit_entry_pt_q) + ); + + tri_rlmreg_p #(.WIDTH((`THREADS+2)), .INIT(0), .NEEDS_SRESET(1)) ex4_parerr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex4_parerr_offset:ex4_parerr_offset + (`THREADS+2) - 1]), + .scout(sov_0[ex4_parerr_offset:ex4_parerr_offset + (`THREADS+2) - 1]), + .din(ex4_parerr_d), + .dout(ex4_parerr_q) + ); + + tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) ex4_attr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex4_attr_offset:ex4_attr_offset + 6 - 1]), + .scout(sov_0[ex4_attr_offset:ex4_attr_offset + 6 - 1]), + .din(ex4_attr_d[0:5]), + .dout(ex4_attr_q[0:5]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_cam_hit_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex4_cam_hit_offset]), + .scout(sov_0[ex4_cam_hit_offset]), + .din(cam_hit), + .dout(ex4_cam_hit_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_hit_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex4_hit_offset]), + .scout(sov_0[ex4_hit_offset]), + .din(ex4_hit_d), + .dout(ex4_hit_q) + ); + + tri_rlmreg_p #(.WIDTH(11), .INIT(0), .NEEDS_SRESET(1)) ex3_debug_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex3_debug_offset:ex3_debug_offset + 11 - 1]), + .scout(sov_0[ex3_debug_offset:ex3_debug_offset + 11 - 1]), + .din(ex3_debug_d), + .dout(ex3_debug_q) + ); + + tri_rlmreg_p #(.WIDTH(17), .INIT(0), .NEEDS_SRESET(1)) ex4_debug_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ex4_debug_offset:ex4_debug_offset + 17 - 1]), + .scout(sov_0[ex4_debug_offset:ex4_debug_offset + 17 - 1]), + .din(ex4_debug_d), + .dout(ex4_debug_q) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) rw_entry_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[rw_entry_offset:rw_entry_offset + 5 - 1]), + .scout(sov_0[rw_entry_offset:rw_entry_offset + 5 - 1]), + .din(rw_entry_d), + .dout(rw_entry_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rw_entry_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[rw_entry_val_offset]), + .scout(sov_0[rw_entry_val_offset]), + .din(rw_entry_val_d), + .dout(rw_entry_val_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rw_entry_le_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[rw_entry_le_offset]), + .scout(sov_0[rw_entry_le_offset]), + .din(rw_entry_le_d), + .dout(rw_entry_le_q) + ); + + tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) cam_entry_le_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rw_entry_val_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[cam_entry_le_offset:cam_entry_le_offset + 32 - 1]), + .scout(sov_0[cam_entry_le_offset:cam_entry_le_offset + 32 - 1]), + .din(cam_entry_le_d), + .dout(cam_entry_le_q) + ); + + tri_rlmreg_p #(.WIDTH(30), .INIT(0), .NEEDS_SRESET(1)) ex3_comp_addr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex3_comp_addr_offset:ex3_comp_addr_offset + 30 - 1]), + .scout(sov_1[ex3_comp_addr_offset:ex3_comp_addr_offset + 30 - 1]), + .din(ex3_comp_addr_d), + .dout(ex3_comp_addr_q) + ); + + tri_rlmreg_p #(.WIDTH(30), .INIT(0), .NEEDS_SRESET(1)) ex4_rpn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex4_rpn_offset:ex4_rpn_offset + 30 - 1]), + .scout(sov_1[ex4_rpn_offset:ex4_rpn_offset + 30 - 1]), + .din(ex4_rpn_d), + .dout(ex4_rpn_q) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) ex4_wimge_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex4_wimge_offset:ex4_wimge_offset + 5 - 1]), + .scout(sov_1[ex4_wimge_offset:ex4_wimge_offset + 5 - 1]), + .din(ex4_wimge_d), + .dout(ex4_wimge_q) + ); + + tri_rlmreg_p #(.WIDTH(cam_data_width), .INIT(0), .NEEDS_SRESET(1)) ex4_cam_cmp_data_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_cmp_data_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex4_cam_cmp_data_offset:ex4_cam_cmp_data_offset + cam_data_width - 1]), + .scout(sov_1[ex4_cam_cmp_data_offset:ex4_cam_cmp_data_offset + cam_data_width - 1]), + .din(ex4_cam_cmp_data_d), + .dout(ex4_cam_cmp_data_q) + ); + + tri_rlmreg_p #(.WIDTH(array_data_width), .INIT(0), .NEEDS_SRESET(1)) ex4_array_cmp_data_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_cmp_data_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex4_array_cmp_data_offset:ex4_array_cmp_data_offset + array_data_width - 1]), + .scout(sov_1[ex4_array_cmp_data_offset:ex4_array_cmp_data_offset + array_data_width - 1]), + .din(ex4_array_cmp_data_d), + .dout(ex4_array_cmp_data_q) + ); + + tri_rlmreg_p #(.WIDTH(array_data_width), .INIT(0), .NEEDS_SRESET(1)) ex4_rd_array_data_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_rd_data_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex4_rd_array_data_offset:ex4_rd_array_data_offset + array_data_width - 1]), + .scout(sov_1[ex4_rd_array_data_offset:ex4_rd_array_data_offset + array_data_width - 1]), + .din(ex4_rd_array_data_d[0:array_data_width - 1]), + .dout(ex4_rd_array_data_q[0:array_data_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(cam_data_width), .INIT(0), .NEEDS_SRESET(1)) ex4_rd_cam_data_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_rd_data_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex4_rd_cam_data_offset:ex4_rd_cam_data_offset + cam_data_width - 1]), + .scout(sov_1[ex4_rd_cam_data_offset:ex4_rd_cam_data_offset + cam_data_width - 1]), + .din(ex4_rd_cam_data_d[0:cam_data_width - 1]), + .dout(ex4_rd_cam_data_q[0:cam_data_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH((`THREADS+5)), .INIT(0), .NEEDS_SRESET(1)) ex5_parerr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex5_parerr_offset:ex5_parerr_offset + (`THREADS+5) - 1]), + .scout(sov_1[ex5_parerr_offset:ex5_parerr_offset + (`THREADS+5) - 1]), + .din(ex5_parerr_d), + .dout(ex5_parerr_q) + ); + + tri_rlmreg_p #(.WIDTH((`THREADS+3)), .INIT(0), .NEEDS_SRESET(1)) ex5_fir_parerr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex5_fir_parerr_offset:ex5_fir_parerr_offset + (`THREADS+3) - 1]), + .scout(sov_1[ex5_fir_parerr_offset:ex5_fir_parerr_offset + (`THREADS+3) - 1]), + .din(ex5_fir_parerr_d), + .dout(ex5_fir_parerr_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex5_fir_multihit_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex5_fir_multihit_offset:ex5_fir_multihit_offset + `THREADS - 1]), + .scout(sov_1[ex5_fir_multihit_offset:ex5_fir_multihit_offset + `THREADS - 1]), + .din(ex5_fir_multihit_d[0:`THREADS - 1]), + .dout(ex5_fir_multihit_q[0:`THREADS - 1]) + ); + + tri_rlmreg_p #(.WIDTH((`THREADS+num_entry_log2-1+1)), .INIT(0), .NEEDS_SRESET(1)) ex5_deen_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex5_deen_offset:ex5_deen_offset + (`THREADS+num_entry_log2-1+1) - 1]), + .scout(sov_1[ex5_deen_offset:ex5_deen_offset + (`THREADS+num_entry_log2-1+1) - 1]), + .din(ex5_deen_d[0:(`THREADS+num_entry_log2-1+1) - 1]), + .dout(ex5_deen_q[0:(`THREADS+num_entry_log2-1+1) - 1]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_hit_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex5_hit_offset]), + .scout(sov_1[ex5_hit_offset]), + .din(ex5_hit_d), + .dout(ex5_hit_q) + ); + + tri_rlmreg_p #(.WIDTH((`THREADS+num_entry_log2)), .INIT(0), .NEEDS_SRESET(1)) ex6_deen_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex6_deen_offset:ex6_deen_offset + (`THREADS+num_entry_log2) - 1]), + .scout(sov_1[ex6_deen_offset:ex6_deen_offset + (`THREADS+num_entry_log2) - 1]), + .din(ex6_deen_d[0:`THREADS+num_entry_log2 - 1]), + .dout(ex6_deen_q[0:`THREADS+num_entry_log2 - 1]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_hit_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex6_hit_offset]), + .scout(sov_1[ex6_hit_offset]), + .din(ex6_hit_d), + .dout(ex6_hit_q) + ); + + tri_rlmreg_p #(.WIDTH((`THREADS+num_entry_log2)), .INIT(0), .NEEDS_SRESET(1)) ex7_deen_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex7_deen_offset:ex7_deen_offset + (`THREADS+num_entry_log2) - 1]), + .scout(sov_1[ex7_deen_offset:ex7_deen_offset + (`THREADS+num_entry_log2) - 1]), + .din(ex7_deen_d[0:`THREADS+num_entry_log2 - 1]), + .dout(ex7_deen_q[0:`THREADS+num_entry_log2 - 1]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex7_hit_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex7_hit_offset]), + .scout(sov_1[ex7_hit_offset]), + .din(ex7_hit_d), + .dout(ex7_hit_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) barrier_done_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[barrier_done_offset:barrier_done_offset + `THREADS - 1]), + .scout(sov_1[barrier_done_offset:barrier_done_offset + `THREADS - 1]), + .din(barrier_done_d[0:`THREADS - 1]), + .dout(barrier_done_q[0:`THREADS - 1]) + ); + + tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) mmucr1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mmucr1_offset:mmucr1_offset + 10 - 1]), + .scout(sov_1[mmucr1_offset:mmucr1_offset + 10 - 1]), + .din(mmucr1_d), + .dout(mmucr1_q) + ); +/* + generate + begin : rpn_holdreg + genvar tid; + for (tid = 0; tid <= `THREADS - 1; tid = tid + 1) + begin : rpn_holdreg + + tri_rlmreg_p #(.WIDTH(64), .INIT(0), .NEEDS_SRESET(1)) rpn_holdreg_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[rpn_holdreg_offset + (64 * tid):rpn_holdreg_offset + (64 * (tid + 1)) - 1]), + .scout(sov_1[rpn_holdreg_offset + (64 * tid):rpn_holdreg_offset + (64 * (tid + 1)) - 1]), + .din(rpn_holdreg_d[tid][0:63]), + .dout(rpn_holdreg_q[tid][0:63]) + ); + end + end + endgenerate +*/ + + tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) entry_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(entry_valid_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[entry_valid_offset:entry_valid_offset + 32 - 1]), + .scout(sov_1[entry_valid_offset:entry_valid_offset + 32 - 1]), + .din(entry_valid), + .dout(entry_valid_q) + ); + + tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) entry_match_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(entry_match_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[entry_match_offset:entry_match_offset + 32 - 1]), + .scout(sov_1[entry_match_offset:entry_match_offset + 32 - 1]), + .din(entry_match), + .dout(entry_match_q) + ); + + tri_rlmreg_p #(.WIDTH(watermark_width), .INIT(29), .NEEDS_SRESET(1)) watermark_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[watermark_offset:watermark_offset + watermark_width - 1]), + .scout(sov_1[watermark_offset:watermark_offset + watermark_width - 1]), + .din(watermark_d[0:watermark_width - 1]), + .dout(watermark_q[0:watermark_width - 1]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mmucr1_b0_cpy_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mmucr1_b0_cpy_offset]), + .scout(sov_1[mmucr1_b0_cpy_offset]), + .din(mmucr1_b0_cpy_d), + .dout(mmucr1_b0_cpy_q) + ); + + tri_rlmreg_p #(.WIDTH((lru_width+1)), .INIT(0), .NEEDS_SRESET(1)) lru_rmt_vec_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[lru_rmt_vec_offset:lru_rmt_vec_offset + (lru_width+1) - 1]), + .scout(sov_1[lru_rmt_vec_offset:lru_rmt_vec_offset + (lru_width+1) - 1]), + .din(lru_rmt_vec_d), + .dout(lru_rmt_vec_q) + ); + + tri_rlmreg_p #(.WIDTH(eptr_width), .INIT(0), .NEEDS_SRESET(1)) eptr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[eptr_offset:eptr_offset + eptr_width - 1]), + .scout(sov_1[eptr_offset:eptr_offset + eptr_width - 1]), + .din(eptr_d[0:eptr_width - 1]), + .dout(eptr_q[0:eptr_width - 1]) + ); + + tri_rlmreg_p #(.WIDTH(lru_width), .INIT(0), .NEEDS_SRESET(1)) lru_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[lru_offset:lru_offset + lru_width - 1]), + .scout(sov_1[lru_offset:lru_offset + lru_width - 1]), + .din(lru_d[1:lru_width]), + .dout(lru_q[1:lru_width]) + ); + + tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) lru_update_event_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[lru_update_event_offset:lru_update_event_offset + 10 - 1]), + .scout(sov_1[lru_update_event_offset:lru_update_event_offset + 10 - 1]), + .din(lru_update_event_d), + .dout(lru_update_event_q) + ); + + + tri_rlmreg_p #(.WIDTH(41), .INIT(0), .NEEDS_SRESET(1)) lru_debug_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[lru_debug_offset:lru_debug_offset + 41 - 1]), + .scout(sov_1[lru_debug_offset:lru_debug_offset + 41 - 1]), + .din(lru_debug_d), + .dout(lru_debug_q) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) snoop_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[snoop_val_offset:snoop_val_offset + 3 - 1]), + .scout(sov_1[snoop_val_offset:snoop_val_offset + 3 - 1]), + .din(snoop_val_d), + .dout(snoop_val_q) + ); + + tri_rlmreg_p #(.WIDTH(26), .INIT(0), .NEEDS_SRESET(1)) snoop_attr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(snoop_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[snoop_attr_offset:snoop_attr_offset + 26 - 1]), + .scout(sov_1[snoop_attr_offset:snoop_attr_offset + 26 - 1]), + .din(snoop_attr_d), + .dout(snoop_attr_q) + ); + + tri_rlmreg_p #(.WIDTH((epn_width)), .INIT(0), .NEEDS_SRESET(1)) snoop_addr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(snoop_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[snoop_addr_offset:snoop_addr_offset + epn_width - 1]), + .scout(sov_1[snoop_addr_offset:snoop_addr_offset + epn_width - 1]), + .din(snoop_addr_d[52 - epn_width:51]), + .dout(snoop_addr_q[52 - epn_width:51]) + ); + + tri_rlmreg_p #(.WIDTH((51-(64-(2**`GPR_WIDTH_ENC))+1)), .INIT(0), .NEEDS_SRESET(1)) ex3_epn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex2_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex3_epn_offset:ex3_epn_offset + (51-(64-(2**`GPR_WIDTH_ENC))+1) - 1]), + .scout(sov_1[ex3_epn_offset:ex3_epn_offset + (51-(64-(2**`GPR_WIDTH_ENC))+1) - 1]), + .din(ex3_epn_d), + .dout(ex3_epn_q) + ); + + tri_rlmreg_p #(.WIDTH((51-(64-(2**`GPR_WIDTH_ENC))+1)), .INIT(0), .NEEDS_SRESET(1)) ex4_epn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex4_epn_offset:ex4_epn_offset + (51-(64-(2**`GPR_WIDTH_ENC))+1) - 1]), + .scout(sov_1[ex4_epn_offset:ex4_epn_offset + (51-(64-(2**`GPR_WIDTH_ENC))+1) - 1]), + .din(ex3_epn_q), + .dout(ex4_epn_q) + ); + + tri_rlmreg_p #(.WIDTH((51-(64-(2**`GPR_WIDTH_ENC))+1)), .INIT(0), .NEEDS_SRESET(1)) ex5_epn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex5_epn_offset:ex5_epn_offset + (51-(64-(2**`GPR_WIDTH_ENC))+1) - 1]), + .scout(sov_1[ex5_epn_offset:ex5_epn_offset + (51-(64-(2**`GPR_WIDTH_ENC))+1) - 1]), + .din(ex4_epn_q), + .dout(ex5_epn_q) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) por_seq_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[por_seq_offset:por_seq_offset + 3 - 1]), + .scout(sov_1[por_seq_offset:por_seq_offset + 3 - 1]), + .din(por_seq_d[0:por_seq_width - 1]), + .dout(por_seq_q[0:por_seq_width - 1]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pc_xu_init_reset_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[pc_xu_init_reset_offset]), + .scout(sov_1[pc_xu_init_reset_offset]), + .din(pc_xu_init_reset), + .dout(pc_xu_init_reset_q) + ); + // timing latches for reloads + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) tlb_rel_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[tlb_rel_val_offset:tlb_rel_val_offset + 5 - 1]), + .scout(sov_1[tlb_rel_val_offset:tlb_rel_val_offset + 5 - 1]), + .din(tlb_rel_val_d), + .dout(tlb_rel_val_q) + ); + + tri_rlmreg_p #(.WIDTH(132), .INIT(0), .NEEDS_SRESET(1)) tlb_rel_data_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_rel_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[tlb_rel_data_offset:tlb_rel_data_offset + 132 - 1]), + .scout(sov_1[tlb_rel_data_offset:tlb_rel_data_offset + 132 - 1]), + .din(tlb_rel_data_d), + .dout(tlb_rel_data_q) + ); + + tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) tlb_rel_emq_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_rel_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[tlb_rel_emq_offset:tlb_rel_emq_offset + `EMQ_ENTRIES - 1]), + .scout(sov_1[tlb_rel_emq_offset:tlb_rel_emq_offset + `EMQ_ENTRIES - 1]), + .din(tlb_rel_emq_d), + .dout(tlb_rel_emq_q) + ); + + tri_rlmreg_p #(.WIDTH((2*`THREADS+1)), .INIT(0), .NEEDS_SRESET(1)) eplc_wr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[eplc_wr_offset:eplc_wr_offset + (2*`THREADS+1) - 1]), + .scout(sov_1[eplc_wr_offset:eplc_wr_offset + (2*`THREADS+1) - 1]), + .din(eplc_wr_d), + .dout(eplc_wr_q) + ); + + tri_rlmreg_p #(.WIDTH((2*`THREADS+1)), .INIT(0), .NEEDS_SRESET(1)) epsc_wr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[epsc_wr_offset:epsc_wr_offset + (2*`THREADS+1) - 1]), + .scout(sov_1[epsc_wr_offset:epsc_wr_offset + (2*`THREADS+1) - 1]), + .din(epsc_wr_d), + .dout(epsc_wr_q) + ); + + tri_rlmreg_p #(.WIDTH(12), .INIT(0), .NEEDS_SRESET(1)) ccr2_frat_paranoia_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ccr2_frat_paranoia_offset:ccr2_frat_paranoia_offset + 12 - 1]), + .scout(sov_1[ccr2_frat_paranoia_offset:ccr2_frat_paranoia_offset + 12 - 1]), + .din(ccr2_frat_paranoia_d), + .dout(ccr2_frat_paranoia_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) clkg_ctl_override_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[clkg_ctl_override_offset]), + .scout(sov_1[clkg_ctl_override_offset]), + .din(clkg_ctl_override_d), + .dout(clkg_ctl_override_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_stg_act_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex1_stg_act_offset]), + .scout(sov_1[ex1_stg_act_offset]), + .din(ex1_stg_act_d), + .dout(ex1_stg_act_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_stg_act_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex2_stg_act_offset]), + .scout(sov_1[ex2_stg_act_offset]), + .din(ex2_stg_act_d), + .dout(ex2_stg_act_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_stg_act_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex3_stg_act_offset]), + .scout(sov_1[ex3_stg_act_offset]), + .din(ex3_stg_act_d), + .dout(ex3_stg_act_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_stg_act_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex4_stg_act_offset]), + .scout(sov_1[ex4_stg_act_offset]), + .din(ex4_stg_act_d), + .dout(ex4_stg_act_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_stg_act_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex5_stg_act_offset]), + .scout(sov_1[ex5_stg_act_offset]), + .din(ex5_stg_act_d), + .dout(ex5_stg_act_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_stg_act_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex6_stg_act_offset]), + .scout(sov_1[ex6_stg_act_offset]), + .din(ex6_stg_act_d), + .dout(ex6_stg_act_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_rel_act_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[tlb_rel_act_offset]), + .scout(sov_1[tlb_rel_act_offset]), + .din(tlb_rel_act_d), + .dout(tlb_rel_act_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) snoopp_act_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[snoopp_act_offset]), + .scout(sov_1[snoopp_act_offset]), + .din(mm_lq_snoop_coming), + .dout(snoopp_act_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) an_ac_grffence_en_dc_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[an_ac_grffence_en_dc_offset]), + .scout(sov_1[an_ac_grffence_en_dc_offset]), + .din(an_ac_grffence_en_dc), + .dout(an_ac_grffence_en_dc_q) + ); + + tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) spare_a_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spare_a_offset:spare_a_offset + 16 - 1]), + .scout(sov_0[spare_a_offset:spare_a_offset + 16 - 1]), + .din(spare_a_q), + .dout(spare_a_q) + ); + + tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) spare_b_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spare_b_offset:spare_b_offset + 16 - 1]), + .scout(sov_1[spare_b_offset:spare_b_offset + 16 - 1]), + .din(spare_b_q), + .dout(spare_b_q) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) csync_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[csync_val_offset:csync_val_offset + 2 - 1]), + .scout(sov_1[csync_val_offset:csync_val_offset + 2 - 1]), + .din(csync_val_d), + .dout(csync_val_q) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) isync_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[isync_val_offset:isync_val_offset + 2 - 1]), + .scout(sov_1[isync_val_offset:isync_val_offset + 2 - 1]), + .din(isync_val_d), + .dout(isync_val_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) rel_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[rel_val_offset:rel_val_offset + 4 - 1]), + .scout(sov_1[rel_val_offset:rel_val_offset + 4 - 1]), + .din(rel_val_d), + .dout(rel_val_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel_hit_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[rel_hit_offset]), + .scout(sov_1[rel_hit_offset]), + .din(rel_hit_d), + .dout(rel_hit_q) + ); + + tri_rlmreg_p #(.WIDTH(132), .INIT(0), .NEEDS_SRESET(1)) rel_data_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_rel_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[rel_data_offset:rel_data_offset + 132 - 1]), + .scout(sov_1[rel_data_offset:rel_data_offset + 132 - 1]), + .din(rel_data_d), + .dout(rel_data_q) + ); + + tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) rel_emq_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_rel_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[rel_emq_offset:rel_emq_offset + `EMQ_ENTRIES - 1]), + .scout(sov_1[rel_emq_offset:rel_emq_offset + `EMQ_ENTRIES - 1]), + .din(rel_emq_d), + .dout(rel_emq_q) + ); + + tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) rel_int_upd_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_rel_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[rel_int_upd_val_offset:rel_int_upd_val_offset + `EMQ_ENTRIES - 1]), + .scout(sov_1[rel_int_upd_val_offset:rel_int_upd_val_offset + `EMQ_ENTRIES - 1]), + .din(rel_int_upd_val_d), + .dout(rel_int_upd_val_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) epsc_wr_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[epsc_wr_val_offset:epsc_wr_val_offset + `THREADS - 1]), + .scout(sov_1[epsc_wr_val_offset:epsc_wr_val_offset + `THREADS - 1]), + .din(epsc_wr_val_d), + .dout(epsc_wr_val_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) eplc_wr_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[eplc_wr_val_offset:eplc_wr_val_offset + `THREADS - 1]), + .scout(sov_1[eplc_wr_val_offset:eplc_wr_val_offset + `THREADS - 1]), + .din(eplc_wr_val_d), + .dout(eplc_wr_val_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rv1_binv_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[rv1_binv_val_offset]), + .scout(sov_1[rv1_binv_val_offset]), + .din(rv1_binv_val_d), + .dout(rv1_binv_val_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) snoopp_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[snoopp_val_offset]), + .scout(sov_1[snoopp_val_offset]), + .din(snoopp_val_d), + .dout(snoopp_val_q) + ); + + tri_rlmreg_p #(.WIDTH(26), .INIT(0), .NEEDS_SRESET(1)) snoopp_attr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(snoopp_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[snoopp_attr_offset:snoopp_attr_offset + 26 - 1]), + .scout(sov_1[snoopp_attr_offset:snoopp_attr_offset + 26 - 1]), + .din(snoopp_attr_d), + .dout(snoopp_attr_q) + ); + + tri_rlmreg_p #(.WIDTH((epn_width)), .INIT(0), .NEEDS_SRESET(1)) snoopp_vpn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(snoopp_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[snoopp_vpn_offset:snoopp_vpn_offset + epn_width - 1]), + .scout(sov_1[snoopp_vpn_offset:snoopp_vpn_offset + epn_width - 1]), + .din(snoopp_vpn_d), + .dout(snoopp_vpn_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ttype_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ttype_val_offset:ttype_val_offset + `THREADS - 1]), + .scout(sov_1[ttype_val_offset:ttype_val_offset + `THREADS - 1]), + .din(ttype_val_d), + .dout(ttype_val_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ttype_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ttype_offset:ttype_offset + 4 - 1]), + .scout(sov_1[ttype_offset:ttype_offset + 4 - 1]), + .din(ttype_d), + .dout(ttype_q) + ); + + tri_rlmreg_p #(.WIDTH(ws_width), .INIT(0), .NEEDS_SRESET(1)) ws_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ws_offset:ws_offset + ws_width - 1]), + .scout(sov_1[ws_offset:ws_offset + ws_width - 1]), + .din(ws_d), + .dout(ws_q) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) ra_entry_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ra_entry_offset:ra_entry_offset + 5 - 1]), + .scout(sov_1[ra_entry_offset:ra_entry_offset + 5 - 1]), + .din(ra_entry_d), + .dout(ra_entry_q) + ); + + tri_rlmreg_p #(.WIDTH(GPR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) rs_data_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[rs_data_offset:rs_data_offset + GPR_WIDTH - 1]), + .scout(sov_1[rs_data_offset:rs_data_offset + GPR_WIDTH - 1]), + .din(rs_data_d), + .dout(rs_data_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) eratre_hole_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[eratre_hole_offset:eratre_hole_offset + 4 - 1]), + .scout(sov_1[eratre_hole_offset:eratre_hole_offset + 4 - 1]), + .din(eratre_hole_d), + .dout(eratre_hole_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) eratwe_hole_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[eratwe_hole_offset:eratwe_hole_offset + 4 - 1]), + .scout(sov_1[eratwe_hole_offset:eratwe_hole_offset + 4 - 1]), + .din(eratwe_hole_d), + .dout(eratwe_hole_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rv1_csync_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[rv1_csync_val_offset]), + .scout(sov_1[rv1_csync_val_offset]), + .din(rv1_csync_val_d), + .dout(rv1_csync_val_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_csync_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex0_csync_val_offset]), + .scout(sov_1[ex0_csync_val_offset]), + .din(ex0_csync_val_d), + .dout(ex0_csync_val_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rv1_isync_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[rv1_isync_val_offset]), + .scout(sov_1[rv1_isync_val_offset]), + .din(rv1_isync_val_d), + .dout(rv1_isync_val_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_isync_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex0_isync_val_offset]), + .scout(sov_1[ex0_isync_val_offset]), + .din(ex0_isync_val_d), + .dout(ex0_isync_val_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) rv1_rel_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[rv1_rel_val_offset:rv1_rel_val_offset + 4 - 1]), + .scout(sov_1[rv1_rel_val_offset:rv1_rel_val_offset + 4 - 1]), + .din(rv1_rel_val_d), + .dout(rv1_rel_val_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ex0_rel_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex0_rel_val_offset:ex0_rel_val_offset + 4 - 1]), + .scout(sov_1[ex0_rel_val_offset:ex0_rel_val_offset + 4 - 1]), + .din(ex0_rel_val_d), + .dout(ex0_rel_val_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ex1_rel_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex1_rel_val_offset:ex1_rel_val_offset + 4 - 1]), + .scout(sov_1[ex1_rel_val_offset:ex1_rel_val_offset + 4 - 1]), + .din(ex1_rel_val_d), + .dout(ex1_rel_val_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) rv1_epsc_wr_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[rv1_epsc_wr_val_offset:rv1_epsc_wr_val_offset + `THREADS - 1]), + .scout(sov_1[rv1_epsc_wr_val_offset:rv1_epsc_wr_val_offset + `THREADS - 1]), + .din(rv1_epsc_wr_val_d), + .dout(rv1_epsc_wr_val_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex0_epsc_wr_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex0_epsc_wr_val_offset:ex0_epsc_wr_val_offset + `THREADS - 1]), + .scout(sov_1[ex0_epsc_wr_val_offset:ex0_epsc_wr_val_offset + `THREADS - 1]), + .din(ex0_epsc_wr_val_d), + .dout(ex0_epsc_wr_val_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) rv1_eplc_wr_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[rv1_eplc_wr_val_offset:rv1_eplc_wr_val_offset + `THREADS - 1]), + .scout(sov_1[rv1_eplc_wr_val_offset:rv1_eplc_wr_val_offset + `THREADS - 1]), + .din(rv1_eplc_wr_val_d), + .dout(rv1_eplc_wr_val_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex0_eplc_wr_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex0_eplc_wr_val_offset:ex0_eplc_wr_val_offset + `THREADS - 1]), + .scout(sov_1[ex0_eplc_wr_val_offset:ex0_eplc_wr_val_offset + `THREADS - 1]), + .din(ex0_eplc_wr_val_d), + .dout(ex0_eplc_wr_val_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_binv_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex0_binv_val_offset]), + .scout(sov_1[ex0_binv_val_offset]), + .din(ex0_binv_val_d), + .dout(ex0_binv_val_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_binv_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex1_binv_val_offset]), + .scout(sov_1[ex1_binv_val_offset]), + .din(ex1_binv_val_d), + .dout(ex1_binv_val_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rv1_snoop_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[rv1_snoop_val_offset]), + .scout(sov_1[rv1_snoop_val_offset]), + .din(rv1_snoop_val_d), + .dout(rv1_snoop_val_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_snoop_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex0_snoop_val_offset]), + .scout(sov_1[ex0_snoop_val_offset]), + .din(ex0_snoop_val_d), + .dout(ex0_snoop_val_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_snoop_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex1_snoop_val_offset]), + .scout(sov_1[ex1_snoop_val_offset]), + .din(ex1_snoop_val_d), + .dout(ex1_snoop_val_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) rv1_ttype_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[rv1_ttype_val_offset:rv1_ttype_val_offset + `THREADS - 1]), + .scout(sov_1[rv1_ttype_val_offset:rv1_ttype_val_offset + `THREADS - 1]), + .din(rv1_ttype_val_d), + .dout(rv1_ttype_val_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex0_ttype_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex0_ttype_val_offset:ex0_ttype_val_offset + `THREADS - 1]), + .scout(sov_1[ex0_ttype_val_offset:ex0_ttype_val_offset + `THREADS - 1]), + .din(ex0_ttype_val_d), + .dout(ex0_ttype_val_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) rv1_ttype_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[rv1_ttype_offset:rv1_ttype_offset + 4 - 1]), + .scout(sov_1[rv1_ttype_offset:rv1_ttype_offset + 4 - 1]), + .din(rv1_ttype_d), + .dout(rv1_ttype_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ex0_ttype_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex0_ttype_offset:ex0_ttype_offset + 4 - 1]), + .scout(sov_1[ex0_ttype_offset:ex0_ttype_offset + 4 - 1]), + .din(ex0_ttype_d), + .dout(ex0_ttype_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ex1_ttype03_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex1_ttype03_offset:ex1_ttype03_offset + 4 - 1]), + .scout(sov_1[ex1_ttype03_offset:ex1_ttype03_offset + 4 - 1]), + .din(ex1_ttype03_d), + .dout(ex1_ttype03_q) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex1_ttype67_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex1_ttype67_offset:ex1_ttype67_offset + 2 - 1]), + .scout(sov_1[ex1_ttype67_offset:ex1_ttype67_offset + 2 - 1]), + .din(ex1_ttype67_d), + .dout(ex1_ttype67_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex1_valid_op_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex1_valid_op_offset:ex1_valid_op_offset + `THREADS - 1]), + .scout(sov_1[ex1_valid_op_offset:ex1_valid_op_offset + `THREADS - 1]), + .din(ex1_valid_op_d), + .dout(ex1_valid_op_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex2_valid_op_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex2_valid_op_offset:ex2_valid_op_offset + `THREADS - 1]), + .scout(sov_1[ex2_valid_op_offset:ex2_valid_op_offset + `THREADS - 1]), + .din(ex2_valid_op_d), + .dout(ex2_valid_op_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex3_valid_op_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex3_valid_op_offset:ex3_valid_op_offset + `THREADS - 1]), + .scout(sov_1[ex3_valid_op_offset:ex3_valid_op_offset + `THREADS - 1]), + .din(ex3_valid_op_d), + .dout(ex3_valid_op_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex4_valid_op_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex4_valid_op_offset:ex4_valid_op_offset + `THREADS - 1]), + .scout(sov_1[ex4_valid_op_offset:ex4_valid_op_offset + `THREADS - 1]), + .din(ex4_valid_op_d), + .dout(ex4_valid_op_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex5_valid_op_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex5_valid_op_offset:ex5_valid_op_offset + `THREADS - 1]), + .scout(sov_1[ex5_valid_op_offset:ex5_valid_op_offset + `THREADS - 1]), + .din(ex5_valid_op_d), + .dout(ex5_valid_op_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex6_valid_op_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex6_valid_op_offset:ex6_valid_op_offset + `THREADS - 1]), + .scout(sov_1[ex6_valid_op_offset:ex6_valid_op_offset + `THREADS - 1]), + .din(ex6_valid_op_d), + .dout(ex6_valid_op_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex7_valid_op_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex7_valid_op_offset:ex7_valid_op_offset + `THREADS - 1]), + .scout(sov_1[ex7_valid_op_offset:ex7_valid_op_offset + `THREADS - 1]), + .din(ex7_valid_op_d), + .dout(ex7_valid_op_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex8_valid_op_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex8_valid_op_offset:ex8_valid_op_offset + `THREADS - 1]), + .scout(sov_1[ex8_valid_op_offset:ex8_valid_op_offset + `THREADS - 1]), + .din(ex8_valid_op_d), + .dout(ex8_valid_op_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq_xu_ord_write_done_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[lq_xu_ord_write_done_offset]), + .scout(sov_1[lq_xu_ord_write_done_offset]), + .din(lq_xu_ord_write_done_d), + .dout(lq_xu_ord_write_done_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq_xu_ord_read_done_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[lq_xu_ord_read_done_offset]), + .scout(sov_1[lq_xu_ord_read_done_offset]), + .din(lq_xu_ord_read_done_d), + .dout(lq_xu_ord_read_done_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_lq_act_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[xu_lq_act_offset]), + .scout(sov_1[xu_lq_act_offset]), + .din(xu_lq_act_d), + .dout(xu_lq_act_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) xu_lq_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[xu_lq_val_offset:xu_lq_val_offset + `THREADS - 1]), + .scout(sov_1[xu_lq_val_offset:xu_lq_val_offset + `THREADS - 1]), + .din(xu_lq_val_d), + .dout(xu_lq_val_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_lq_is_eratre_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_lq_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[xu_lq_is_eratre_offset]), + .scout(sov_1[xu_lq_is_eratre_offset]), + .din(xu_lq_is_eratre_d), + .dout(xu_lq_is_eratre_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_lq_is_eratwe_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_lq_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[xu_lq_is_eratwe_offset]), + .scout(sov_1[xu_lq_is_eratwe_offset]), + .din(xu_lq_is_eratwe_d), + .dout(xu_lq_is_eratwe_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_lq_is_eratsx_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_lq_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[xu_lq_is_eratsx_offset]), + .scout(sov_1[xu_lq_is_eratsx_offset]), + .din(xu_lq_is_eratsx_d), + .dout(xu_lq_is_eratsx_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_lq_is_eratilx_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_lq_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[xu_lq_is_eratilx_offset]), + .scout(sov_1[xu_lq_is_eratilx_offset]), + .din(xu_lq_is_eratilx_d), + .dout(xu_lq_is_eratilx_q) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) xu_lq_ws_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_lq_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[xu_lq_ws_offset:xu_lq_ws_offset + 2 - 1]), + .scout(sov_1[xu_lq_ws_offset:xu_lq_ws_offset + 2 - 1]), + .din(xu_lq_ws_d), + .dout(xu_lq_ws_q) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) xu_lq_ra_entry_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_lq_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[xu_lq_ra_entry_offset:xu_lq_ra_entry_offset + 5 - 1]), + .scout(sov_1[xu_lq_ra_entry_offset:xu_lq_ra_entry_offset + 5 - 1]), + .din(xu_lq_ra_entry_d), + .dout(xu_lq_ra_entry_q) + ); + + tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) xu_lq_rs_data_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_lq_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[xu_lq_rs_data_offset:xu_lq_rs_data_offset + (2**`GPR_WIDTH_ENC) - 1]), + .scout(sov_1[xu_lq_rs_data_offset:xu_lq_rs_data_offset + (2**`GPR_WIDTH_ENC) - 1]), + .din(xu_lq_rs_data_d), + .dout(xu_lq_rs_data_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) cp_flush_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[cp_flush_offset:cp_flush_offset + `THREADS - 1]), + .scout(sov_1[cp_flush_offset:cp_flush_offset + `THREADS - 1]), + .din(cp_flush_d), + .dout(cp_flush_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_oldest_itag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex4_oldest_itag_offset]), + .scout(sov_1[ex4_oldest_itag_offset]), + .din(ex4_oldest_itag_d), + .dout(ex4_oldest_itag_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_nonspec_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex4_nonspec_val_offset]), + .scout(sov_1[ex4_nonspec_val_offset]), + .din(ex4_nonspec_val_d), + .dout(ex4_nonspec_val_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_tlbmiss_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex4_tlbmiss_offset]), + .scout(sov_1[ex4_tlbmiss_offset]), + .din(ex4_tlbmiss_d), + .dout(ex4_tlbmiss_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_tlbinelig_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex4_tlbinelig_offset]), + .scout(sov_1[ex4_tlbinelig_offset]), + .din(ex4_tlbinelig_d), + .dout(ex4_tlbinelig_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_ptfault_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex4_ptfault_offset]), + .scout(sov_1[ex4_ptfault_offset]), + .din(ex4_ptfault_d), + .dout(ex4_ptfault_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_lratmiss_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex4_lratmiss_offset]), + .scout(sov_1[ex4_lratmiss_offset]), + .din(ex4_lratmiss_d), + .dout(ex4_lratmiss_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_tlb_multihit_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex4_tlb_multihit_offset]), + .scout(sov_1[ex4_tlb_multihit_offset]), + .din(ex4_tlb_multihit_d), + .dout(ex4_tlb_multihit_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_tlb_par_err_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex4_tlb_par_err_offset]), + .scout(sov_1[ex4_tlb_par_err_offset]), + .din(ex4_tlb_par_err_d), + .dout(ex4_tlb_par_err_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_lru_par_err_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex4_lru_par_err_offset]), + .scout(sov_1[ex4_lru_par_err_offset]), + .din(ex4_lru_par_err_d), + .dout(ex4_lru_par_err_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_tlb_excp_det_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex4_tlb_excp_det_offset]), + .scout(sov_1[ex4_tlb_excp_det_offset]), + .din(ex4_tlb_excp_det_d), + .dout(ex4_tlb_excp_det_q) + ); + + tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex3_eratm_itag_hit_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex3_eratm_itag_hit_offset:ex3_eratm_itag_hit_offset + `EMQ_ENTRIES - 1]), + .scout(sov_1[ex3_eratm_itag_hit_offset:ex3_eratm_itag_hit_offset + `EMQ_ENTRIES - 1]), + .din(ex3_eratm_itag_hit_d), + .dout(ex3_eratm_itag_hit_q) + ); + + tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex4_emq_excp_rpt_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex4_emq_excp_rpt_offset:ex4_emq_excp_rpt_offset + `EMQ_ENTRIES - 1]), + .scout(sov_1[ex4_emq_excp_rpt_offset:ex4_emq_excp_rpt_offset + `EMQ_ENTRIES - 1]), + .din(ex4_emq_excp_rpt_d), + .dout(ex4_emq_excp_rpt_q) + ); + + tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex5_emq_excp_rpt_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex5_emq_excp_rpt_offset:ex5_emq_excp_rpt_offset + `EMQ_ENTRIES - 1]), + .scout(sov_1[ex5_emq_excp_rpt_offset:ex5_emq_excp_rpt_offset + `EMQ_ENTRIES - 1]), + .din(ex5_emq_excp_rpt_d), + .dout(ex5_emq_excp_rpt_q) + ); + + tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex6_emq_excp_rpt_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex6_emq_excp_rpt_offset:ex6_emq_excp_rpt_offset + `EMQ_ENTRIES - 1]), + .scout(sov_1[ex6_emq_excp_rpt_offset:ex6_emq_excp_rpt_offset + `EMQ_ENTRIES - 1]), + .din(ex6_emq_excp_rpt_d), + .dout(ex6_emq_excp_rpt_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex5_tlb_excp_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex5_tlb_excp_val_offset:ex5_tlb_excp_val_offset + `THREADS - 1]), + .scout(sov_1[ex5_tlb_excp_val_offset:ex5_tlb_excp_val_offset + `THREADS - 1]), + .din(ex5_tlb_excp_val_d), + .dout(ex5_tlb_excp_val_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex6_tlb_excp_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex6_tlb_excp_val_offset:ex6_tlb_excp_val_offset + `THREADS - 1]), + .scout(sov_1[ex6_tlb_excp_val_offset:ex6_tlb_excp_val_offset + `THREADS - 1]), + .din(ex6_tlb_excp_val_d), + .dout(ex6_tlb_excp_val_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_gate_miss_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex4_gate_miss_offset]), + .scout(sov_1[ex4_gate_miss_offset]), + .din(ex4_gate_miss_d), + .dout(ex4_gate_miss_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_full_restart_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex4_full_restart_offset]), + .scout(sov_1[ex4_full_restart_offset]), + .din(ex4_full_restart_d), + .dout(ex4_full_restart_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_itag_hit_restart_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex4_itag_hit_restart_offset]), + .scout(sov_1[ex4_itag_hit_restart_offset]), + .din(ex4_itag_hit_restart_d), + .dout(ex4_itag_hit_restart_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_epn_hit_restart_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex4_epn_hit_restart_offset]), + .scout(sov_1[ex4_epn_hit_restart_offset]), + .din(ex4_epn_hit_restart_d), + .dout(ex4_epn_hit_restart_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_setHold_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex4_setHold_offset]), + .scout(sov_1[ex4_setHold_offset]), + .din(ex4_setHold_d), + .dout(ex4_setHold_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_tlbreq_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex5_tlbreq_val_offset]), + .scout(sov_1[ex5_tlbreq_val_offset]), + .din(ex5_tlbreq_val_d), + .dout(ex5_tlbreq_val_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_tlbreq_nonspec_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex5_tlbreq_nonspec_offset]), + .scout(sov_1[ex5_tlbreq_nonspec_offset]), + .din(ex5_tlbreq_nonspec_d), + .dout(ex5_tlbreq_nonspec_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex5_thdid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex5_thdid_offset:ex5_thdid_offset + `THREADS - 1]), + .scout(sov_1[ex5_thdid_offset:ex5_thdid_offset + `THREADS - 1]), + .din(ex5_thdid_d), + .dout(ex5_thdid_q) + ); + + tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex5_emq_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex5_emq_offset:ex5_emq_offset + `EMQ_ENTRIES - 1]), + .scout(sov_1[ex5_emq_offset:ex5_emq_offset + `EMQ_ENTRIES - 1]), + .din(ex5_emq_d), + .dout(ex5_emq_q) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex5_tlbreq_ttype_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex5_tlbreq_ttype_offset:ex5_tlbreq_ttype_offset + 2 - 1]), + .scout(sov_1[ex5_tlbreq_ttype_offset:ex5_tlbreq_ttype_offset + 2 - 1]), + .din(ex5_tlbreq_ttype_d), + .dout(ex5_tlbreq_ttype_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex5_perf_dtlb_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ex5_perf_dtlb_offset:ex5_perf_dtlb_offset + `THREADS - 1]), + .scout(sov_1[ex5_perf_dtlb_offset:ex5_perf_dtlb_offset + `THREADS - 1]), + .din(ex5_perf_dtlb_d), + .dout(ex5_perf_dtlb_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) derat_dcc_clr_hold_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[derat_dcc_clr_hold_offset:derat_dcc_clr_hold_offset + `THREADS - 1]), + .scout(sov_1[derat_dcc_clr_hold_offset:derat_dcc_clr_hold_offset + `THREADS - 1]), + .din(derat_dcc_clr_hold_d), + .dout(derat_dcc_clr_hold_q) + ); + + generate + + genvar emq; + + for (emq = 0; emq <= `EMQ_ENTRIES - 1; emq = emq + 1) + begin : eratm_entry_state + + tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) eratm_entry_state_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[eratm_entry_state_offset + (3 * emq):eratm_entry_state_offset + (3 * (emq + 1)) - 1]), + .scout(sov_1[eratm_entry_state_offset + (3 * emq):eratm_entry_state_offset + (3 * (emq + 1)) - 1]), + .din(eratm_entry_state_d[emq]), + .dout(eratm_entry_state_q[emq]) + ); + end + + for (emq = 0; emq <= `EMQ_ENTRIES - 1; emq = emq + 1) + begin : eratm_entry_itag + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) eratm_entry_itag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_entry_wrt_val[emq]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[eratm_entry_itag_offset + (`ITAG_SIZE_ENC * emq):eratm_entry_itag_offset + (`ITAG_SIZE_ENC * (emq + 1)) - 1]), + .scout(sov_1[eratm_entry_itag_offset + (`ITAG_SIZE_ENC * emq):eratm_entry_itag_offset + (`ITAG_SIZE_ENC * (emq + 1)) - 1]), + .din(eratm_entry_itag_d[emq]), + .dout(eratm_entry_itag_q[emq]) + ); + end + + for (emq = 0; emq <= `EMQ_ENTRIES - 1; emq = emq + 1) + begin : eratm_entry_tid + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) eratm_entry_tid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_entry_wrt_val[emq]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[eratm_entry_tid_offset + (`THREADS * emq):eratm_entry_tid_offset + (`THREADS * (emq + 1)) - 1]), + .scout(sov_1[eratm_entry_tid_offset + (`THREADS * emq):eratm_entry_tid_offset + (`THREADS * (emq + 1)) - 1]), + .din(eratm_entry_tid_d[emq]), + .dout(eratm_entry_tid_q[emq]) + ); + end + + for (emq = 0; emq <= `EMQ_ENTRIES - 1; emq = emq + 1) + begin : eratm_entry_epn + + tri_rlmreg_p #(.WIDTH((51-(64-(2**`GPR_WIDTH_ENC))+1)), .INIT(0), .NEEDS_SRESET(1)) eratm_entry_epn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_entry_wrt_val[emq]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[eratm_entry_epn_offset + ((51-(64-(2**`GPR_WIDTH_ENC))+1) * emq):eratm_entry_epn_offset + ((51-(64-(2**`GPR_WIDTH_ENC))+1) * (emq + 1)) - 1]), + .scout(sov_1[eratm_entry_epn_offset + ((51-(64-(2**`GPR_WIDTH_ENC))+1) * emq):eratm_entry_epn_offset + ((51-(64-(2**`GPR_WIDTH_ENC))+1) * (emq + 1)) - 1]), + .din(eratm_entry_epn_d[emq]), + .dout(eratm_entry_epn_q[emq]) + ); + end + + endgenerate +/* + generate + begin : eratm_entry_itag + genvar emq; + for (emq = 0; emq <= `EMQ_ENTRIES - 1; emq = emq + 1) + begin : eratm_entry_itag + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) eratm_entry_itag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_entry_wrt_val[emq]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[eratm_entry_itag_offset + (`ITAG_SIZE_ENC * emq):eratm_entry_itag_offset + (`ITAG_SIZE_ENC * (emq + 1)) - 1]), + .scout(sov_1[eratm_entry_itag_offset + (`ITAG_SIZE_ENC * emq):eratm_entry_itag_offset + (`ITAG_SIZE_ENC * (emq + 1)) - 1]), + .din(eratm_entry_itag_d[emq]), + .dout(eratm_entry_itag_q[emq]) + ); + end + end + endgenerate +*/ +/* + generate + begin : eratm_entry_tid + genvar emq; + for (emq = 0; emq <= `EMQ_ENTRIES - 1; emq = emq + 1) + begin : eratm_entry_tid + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) eratm_entry_tid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_entry_wrt_val[emq]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[eratm_entry_tid_offset + (`THREADS * emq):eratm_entry_tid_offset + (`THREADS * (emq + 1)) - 1]), + .scout(sov_1[eratm_entry_tid_offset + (`THREADS * emq):eratm_entry_tid_offset + (`THREADS * (emq + 1)) - 1]), + .din(eratm_entry_tid_d[emq]), + .dout(eratm_entry_tid_q[emq]) + ); + end + end + endgenerate +*/ +/* + generate + begin : eratm_entry_epn + genvar emq; + for (emq = 0; emq <= `EMQ_ENTRIES - 1; emq = emq + 1) + begin : eratm_entry_epn + + tri_rlmreg_p #(.WIDTH((51-(64-(2**GPR_WIDTH_ENC))+1)), .INIT(0), .NEEDS_SRESET(1)) eratm_entry_epn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_entry_wrt_val[emq]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[eratm_entry_epn_offset + ((51-(64-(2**GPR_WIDTH_ENC))+1) * emq):eratm_entry_epn_offset + ((51-(64-(2**GPR_WIDTH_ENC))+1) * (emq + 1)) - 1]), + .scout(sov_1[eratm_entry_epn_offset + ((51-(64-(2**GPR_WIDTH_ENC))+1) * emq):eratm_entry_epn_offset + ((51-(64-(2**GPR_WIDTH_ENC))+1) * (emq + 1)) - 1]), + .din(eratm_entry_epn_d[emq]), + .dout(eratm_entry_epn_q[emq]) + ); + end + end + endgenerate +*/ + + tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) eratm_entry_nonspec_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[eratm_entry_nonspec_val_offset:eratm_entry_nonspec_val_offset + `EMQ_ENTRIES - 1]), + .scout(sov_1[eratm_entry_nonspec_val_offset:eratm_entry_nonspec_val_offset + `EMQ_ENTRIES - 1]), + .din(eratm_entry_nonspec_val_d), + .dout(eratm_entry_nonspec_val_q) + ); + + tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) eratm_entry_mkill_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[eratm_entry_mkill_offset:eratm_entry_mkill_offset + `EMQ_ENTRIES - 1]), + .scout(sov_1[eratm_entry_mkill_offset:eratm_entry_mkill_offset + `EMQ_ENTRIES - 1]), + .din(eratm_entry_mkill_d), + .dout(eratm_entry_mkill_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) eratm_hold_tid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[eratm_hold_tid_offset:eratm_hold_tid_offset + `THREADS - 1]), + .scout(sov_1[eratm_hold_tid_offset:eratm_hold_tid_offset + `THREADS - 1]), + .din(eratm_hold_tid_d), + .dout(eratm_hold_tid_q) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) mm_int_rpt_itag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mm_int_rpt_itag_offset:mm_int_rpt_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov_1[mm_int_rpt_itag_offset:mm_int_rpt_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(mm_int_rpt_itag_d), + .dout(mm_int_rpt_itag_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mm_int_rpt_tlbmiss_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mm_int_rpt_tlbmiss_offset]), + .scout(sov_1[mm_int_rpt_tlbmiss_offset]), + .din(mm_int_rpt_tlbmiss_d), + .dout(mm_int_rpt_tlbmiss_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mm_int_rpt_tlbinelig_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mm_int_rpt_tlbinelig_offset]), + .scout(sov_1[mm_int_rpt_tlbinelig_offset]), + .din(mm_int_rpt_tlbinelig_d), + .dout(mm_int_rpt_tlbinelig_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mm_int_rpt_ptfault_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mm_int_rpt_ptfault_offset]), + .scout(sov_1[mm_int_rpt_ptfault_offset]), + .din(mm_int_rpt_ptfault_d), + .dout(mm_int_rpt_ptfault_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mm_int_rpt_lratmiss_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mm_int_rpt_lratmiss_offset]), + .scout(sov_1[mm_int_rpt_lratmiss_offset]), + .din(mm_int_rpt_lratmiss_d), + .dout(mm_int_rpt_lratmiss_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mm_int_rpt_tlb_multihit_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mm_int_rpt_tlb_multihit_offset]), + .scout(sov_1[mm_int_rpt_tlb_multihit_offset]), + .din(mm_int_rpt_tlb_multihit_d), + .dout(mm_int_rpt_tlb_multihit_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mm_int_rpt_tlb_par_err_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mm_int_rpt_tlb_par_err_offset]), + .scout(sov_1[mm_int_rpt_tlb_par_err_offset]), + .din(mm_int_rpt_tlb_par_err_d), + .dout(mm_int_rpt_tlb_par_err_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mm_int_rpt_lru_par_err_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mm_int_rpt_lru_par_err_offset]), + .scout(sov_1[mm_int_rpt_lru_par_err_offset]), + .din(mm_int_rpt_lru_par_err_d), + .dout(mm_int_rpt_lru_par_err_q) + ); + + tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) eratm_entry_tlbmiss_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[eratm_entry_tlbmiss_offset:eratm_entry_tlbmiss_offset + `EMQ_ENTRIES - 1]), + .scout(sov_1[eratm_entry_tlbmiss_offset:eratm_entry_tlbmiss_offset + `EMQ_ENTRIES - 1]), + .din(eratm_entry_tlbmiss_d), + .dout(eratm_entry_tlbmiss_q) + ); + + tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) eratm_entry_tlbinelig_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[eratm_entry_tlbinelig_offset:eratm_entry_tlbinelig_offset + `EMQ_ENTRIES - 1]), + .scout(sov_1[eratm_entry_tlbinelig_offset:eratm_entry_tlbinelig_offset + `EMQ_ENTRIES - 1]), + .din(eratm_entry_tlbinelig_d), + .dout(eratm_entry_tlbinelig_q) + ); + + tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) eratm_entry_ptfault_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[eratm_entry_ptfault_offset:eratm_entry_ptfault_offset + `EMQ_ENTRIES - 1]), + .scout(sov_1[eratm_entry_ptfault_offset:eratm_entry_ptfault_offset + `EMQ_ENTRIES - 1]), + .din(eratm_entry_ptfault_d), + .dout(eratm_entry_ptfault_q) + ); + + tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) eratm_entry_lratmiss_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[eratm_entry_lratmiss_offset:eratm_entry_lratmiss_offset + `EMQ_ENTRIES - 1]), + .scout(sov_1[eratm_entry_lratmiss_offset:eratm_entry_lratmiss_offset + `EMQ_ENTRIES - 1]), + .din(eratm_entry_lratmiss_d), + .dout(eratm_entry_lratmiss_q) + ); + + tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) eratm_entry_tlb_multihit_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[eratm_entry_tlb_multihit_offset:eratm_entry_tlb_multihit_offset + `EMQ_ENTRIES - 1]), + .scout(sov_1[eratm_entry_tlb_multihit_offset:eratm_entry_tlb_multihit_offset + `EMQ_ENTRIES - 1]), + .din(eratm_entry_tlb_multihit_d), + .dout(eratm_entry_tlb_multihit_q) + ); + + tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) eratm_entry_tlb_par_err_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[eratm_entry_tlb_par_err_offset:eratm_entry_tlb_par_err_offset + `EMQ_ENTRIES - 1]), + .scout(sov_1[eratm_entry_tlb_par_err_offset:eratm_entry_tlb_par_err_offset + `EMQ_ENTRIES - 1]), + .din(eratm_entry_tlb_par_err_d), + .dout(eratm_entry_tlb_par_err_q) + ); + + tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) eratm_entry_lru_par_err_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[eratm_entry_lru_par_err_offset:eratm_entry_lru_par_err_offset + `EMQ_ENTRIES - 1]), + .scout(sov_1[eratm_entry_lru_par_err_offset:eratm_entry_lru_par_err_offset + `EMQ_ENTRIES - 1]), + .din(eratm_entry_lru_par_err_d), + .dout(eratm_entry_lru_par_err_q) + ); + + + //------------------------------------------------ + // scan only latches for boot config + //------------------------------------------------ + + tri_slat_scan #(.WIDTH(16), .INIT(`DERAT_BCFG_EPN_0TO15), .RESET_INVERTS_SCAN(1'b1)) bcfg_epn_0to15_latch( + .vd(vdd), + .gd(gnd), + .dclk(lcb_dclk), + .lclk(lcb_lclk), + .scan_in(bsiv[bcfg_offset:bcfg_offset + 15]), + .scan_out(bsov[bcfg_offset:bcfg_offset + 15]), + .q(bcfg_q[0:15]), + .q_b(bcfg_q_b[0:15]) + ); + + tri_slat_scan #(.WIDTH(16), .INIT(`DERAT_BCFG_EPN_16TO31), .RESET_INVERTS_SCAN(1'b1)) bcfg_epn_16to31_latch( + .vd(vdd), + .gd(gnd), + .dclk(lcb_dclk), + .lclk(lcb_lclk), + .scan_in(bsiv[bcfg_offset + 16:bcfg_offset + 31]), + .scan_out(bsov[bcfg_offset + 16:bcfg_offset + 31]), + .q(bcfg_q[16:31]), + .q_b(bcfg_q_b[16:31]) + ); + + tri_slat_scan #(.WIDTH(16), .INIT(`DERAT_BCFG_EPN_32TO47), .RESET_INVERTS_SCAN(1'b1)) bcfg_epn_32to47_latch( + .vd(vdd), + .gd(gnd), + .dclk(lcb_dclk), + .lclk(lcb_lclk), + .scan_in(bsiv[bcfg_offset + 32:bcfg_offset + 47]), + .scan_out(bsov[bcfg_offset + 32:bcfg_offset + 47]), + .q(bcfg_q[32:47]), + .q_b(bcfg_q_b[32:47]) + ); + + tri_slat_scan #(.WIDTH(4), .INIT(`DERAT_BCFG_EPN_48TO51), .RESET_INVERTS_SCAN(1'b1)) bcfg_epn_48to51_latch( + .vd(vdd), + .gd(gnd), + .dclk(lcb_dclk), + .lclk(lcb_lclk), + .scan_in(bsiv[bcfg_offset + 48:bcfg_offset + 51]), + .scan_out(bsov[bcfg_offset + 48:bcfg_offset + 51]), + .q(bcfg_q[48:51]), + .q_b(bcfg_q_b[48:51]) + ); + + tri_slat_scan #(.WIDTH(10), .INIT(`DERAT_BCFG_RPN_22TO31), .RESET_INVERTS_SCAN(1'b1)) bcfg_rpn_22to31_latch( + .vd(vdd), + .gd(gnd), + .dclk(lcb_dclk), + .lclk(lcb_lclk), + .scan_in(bsiv[bcfg_offset + 52:bcfg_offset + 61]), + .scan_out(bsov[bcfg_offset + 52:bcfg_offset + 61]), + .q(bcfg_q[52:61]), + .q_b(bcfg_q_b[52:61]) + ); + + tri_slat_scan #(.WIDTH(16), .INIT(`DERAT_BCFG_RPN_32TO47), .RESET_INVERTS_SCAN(1'b1)) bcfg_rpn_32to47_latch( + .vd(vdd), + .gd(gnd), + .dclk(lcb_dclk), + .lclk(lcb_lclk), + .scan_in(bsiv[bcfg_offset + 62:bcfg_offset + 77]), + .scan_out(bsov[bcfg_offset + 62:bcfg_offset + 77]), + .q(bcfg_q[62:77]), + .q_b(bcfg_q_b[62:77]) + ); + + tri_slat_scan #(.WIDTH(4), .INIT(`DERAT_BCFG_RPN_48TO51), .RESET_INVERTS_SCAN(1'b1)) bcfg_rpn_48to51_latch( + .vd(vdd), + .gd(gnd), + .dclk(lcb_dclk), + .lclk(lcb_lclk), + .scan_in(bsiv[bcfg_offset + 78:bcfg_offset + 81]), + .scan_out(bsov[bcfg_offset + 78:bcfg_offset + 81]), + .q(bcfg_q[78:81]), + .q_b(bcfg_q_b[78:81]) + ); + + tri_slat_scan #(.WIDTH(5), .INIT(`DERAT_BCFG_ATTR), .RESET_INVERTS_SCAN(1'b1)) bcfg_attr_latch( + .vd(vdd), + .gd(gnd), + .dclk(lcb_dclk), + .lclk(lcb_lclk), + .scan_in(bsiv[bcfg_offset + 82:bcfg_offset + 86]), + .scan_out(bsov[bcfg_offset + 82:bcfg_offset + 86]), + .q(bcfg_q[82:86]), + .q_b(bcfg_q_b[82:86]) + ); + + tri_slat_scan #(.WIDTH(16), .INIT(`DERAT_BCFG_RPN2_32TO47), .RESET_INVERTS_SCAN(1'b1)) bcfg_rpn2_32to47_latch( + .vd(vdd), + .gd(gnd), + .dclk(lcb_dclk), + .lclk(lcb_lclk), + .scan_in(bsiv[bcfg_offset + 87:bcfg_offset + 102]), + .scan_out(bsov[bcfg_offset + 87:bcfg_offset + 102]), + .q(bcfg_q[87:102]), + .q_b(bcfg_q_b[87:102]) + ); + + tri_slat_scan #(.WIDTH(4), .INIT(`DERAT_BCFG_RPN2_48TO51), .RESET_INVERTS_SCAN(1'b1)) bcfg_rpn2_48to51_latch( + .vd(vdd), + .gd(gnd), + .dclk(lcb_dclk), + .lclk(lcb_lclk), + .scan_in(bsiv[bcfg_offset + 103:bcfg_offset + 106]), + .scan_out(bsov[bcfg_offset + 103:bcfg_offset + 106]), + .q(bcfg_q[103:106]), + .q_b(bcfg_q_b[103:106]) + ); + + tri_slat_scan #(.WIDTH(16), .INIT(0), .RESET_INVERTS_SCAN(1'b1)) bcfg_spare_latch( + .vd(vdd), + .gd(gnd), + .dclk(lcb_dclk), + .lclk(lcb_lclk), + .scan_in(bsiv[bcfg_offset + 107:bcfg_offset + 122]), + .scan_out(bsov[bcfg_offset + 107:bcfg_offset + 122]), + .q(bcfg_q[107:122]), + .q_b(bcfg_q_b[107:122]) + ); + + //------------------------------------------------ + // thold/sg latches + //------------------------------------------------ + + tri_plat #(.WIDTH(4)) perv_2to1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(pc_xu_ccflush_dc), + .din({pc_func_sl_thold_2, pc_func_slp_sl_thold_2, pc_cfg_slp_sl_thold_2, pc_sg_2}), + .q({pc_func_sl_thold_1, pc_func_slp_sl_thold_1, pc_cfg_slp_sl_thold_1, pc_sg_1}) + ); + + tri_plat #(.WIDTH(4)) perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(pc_xu_ccflush_dc), + .din({pc_func_sl_thold_1, pc_func_slp_sl_thold_1, pc_cfg_slp_sl_thold_1, pc_sg_1}), + .q({pc_func_sl_thold_0, pc_func_slp_sl_thold_0, pc_cfg_slp_sl_thold_0, pc_sg_0}) + ); + + tri_lcbor perv_lcbor_func_sl( + .clkoff_b(lcb_clkoff_dc_b), + .thold(pc_func_sl_thold_0), + .sg(pc_sg_0), + .act_dis(lcb_act_dis_dc), + .force_t(pc_func_sl_force), + .thold_b(pc_func_sl_thold_0_b) + ); + + tri_lcbor perv_lcbor_func_slp_sl( + .clkoff_b(lcb_clkoff_dc_b), + .thold(pc_func_slp_sl_thold_0), + .sg(pc_sg_0), + .act_dis(lcb_act_dis_dc), + .force_t(pc_func_slp_sl_force), + .thold_b(pc_func_slp_sl_thold_0_b) + ); + + //------------------------------------------------ + // local clock buffer for boot config + //------------------------------------------------ + + tri_lcbs bcfg_lcb( + .vd(vdd), + .gd(gnd), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .nclk(nclk), + .force_t(pc_cfg_slp_sl_force), + .thold_b(pc_cfg_slp_sl_thold_0_b), + .dclk(lcb_dclk), + .lclk(lcb_lclk) + ); + // these terms in the absence of another lcbor component + // that drives the thold_b and force into the bcfg_lcb for slat's + assign pc_cfg_slp_sl_thold_0_b = (~pc_cfg_slp_sl_thold_0); + assign pc_cfg_slp_sl_force = pc_sg_0; + + //--------------------------------------------------------------------- + // Scan + //--------------------------------------------------------------------- + assign siv_0[0:scan_right_0] = {sov_0[1:scan_right_0], ac_func_scan_in[0]}; + assign func_si_cam_int = sov_0[0]; + assign ac_func_scan_out[0] = func_so_cam_int; + assign siv_1[0:scan_right_1] = {sov_1[1:scan_right_1], ac_func_scan_in[1]}; + assign ac_func_scan_out[1] = sov_1[0]; + assign bsiv[0:boot_scan_right] = {bsov[1:boot_scan_right], ac_ccfg_scan_in}; + assign ac_ccfg_scan_out = bsov[0]; + +endmodule diff --git a/dev/verilog/work/lq_dir.v b/dev/verilog/work/lq_dir.v new file mode 100755 index 0000000..fd1d9e7 --- /dev/null +++ b/dev/verilog/work/lq_dir.v @@ -0,0 +1,1181 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +// Description: XU LSU L1 Data Directory Wrapper +//***************************************************************************** + +// ########################################################################################## +// VHDL Contents +// 1) L1 D$ Directory Array +// 2) Valid Register Array +// 3) LRU Register Array +// 4) Data Cache Control +// 5) Flush Generation +// 6) 8 way tag compare +// 7) Parity Check +// 8) Reload Update +// ########################################################################################## + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" + +module lq_dir( + dcc_dir_ex2_stg_act, + dcc_dir_ex3_stg_act, + dcc_dir_ex4_stg_act, + dcc_dir_ex5_stg_act, + dcc_dir_stq1_stg_act, + dcc_dir_stq2_stg_act, + dcc_dir_stq3_stg_act, + dcc_dir_stq4_stg_act, + dcc_dir_stq5_stg_act, + dcc_dir_binv2_ex2_stg_act, + dcc_dir_binv3_ex3_stg_act, + dcc_dir_binv4_ex4_stg_act, + dcc_dir_binv5_ex5_stg_act, + dcc_dir_binv6_ex6_stg_act, + byp_dir_ex2_rs1, + byp_dir_ex2_rs2, + dcc_dir_ex2_64bit_agen, + pc_lq_inj_dcachedir_ldp_parity, + pc_lq_inj_dcachedir_ldp_multihit, + pc_lq_inj_dcachedir_stp_parity, + pc_lq_inj_dcachedir_stp_multihit, + dcc_dir_ex2_binv_val, + dcc_dir_ex2_thrd_id, + dcc_dir_ex3_cache_acc, + dcc_dir_ex3_pfetch_val, + dcc_dir_ex3_lru_upd, + dcc_dir_ex3_lock_set, + dcc_dir_ex3_th_c, + dcc_dir_ex3_watch_set, + dcc_dir_ex3_larx_val, + dcc_dir_ex3_watch_chk, + dcc_dir_ex3_ddir_acc, + dcc_dir_ex4_load_val, + dcc_dir_ex4_p_addr, + derat_dir_ex4_wimge_i, + dcc_dir_stq6_store_val, + dat_ctl_dcarr_perr_way, + xu_lq_spr_xucr0_wlk, + xu_lq_spr_xucr0_dcdis, + xu_lq_spr_xucr0_clfc, + xu_lq_spr_xucr0_cls, + dcc_dir_spr_xucr2_rmt, + dcc_dir_ex2_frc_align16, + dcc_dir_ex2_frc_align8, + dcc_dir_ex2_frc_align4, + dcc_dir_ex2_frc_align2, + lsq_ctl_stq1_val, + lsq_ctl_stq2_blk_req, + lsq_ctl_stq1_thrd_id, + lsq_ctl_rel1_thrd_id, + lsq_ctl_stq1_store_val, + lsq_ctl_stq1_ci, + lsq_ctl_stq1_lock_clr, + lsq_ctl_stq1_watch_clr, + lsq_ctl_stq1_l_fld, + lsq_ctl_stq1_inval, + lsq_ctl_stq1_dci_val, + lsq_ctl_stq1_addr, + lsq_ctl_rel1_clr_val, + lsq_ctl_rel1_set_val, + lsq_ctl_rel1_data_val, + lsq_ctl_rel1_back_inv, + lsq_ctl_rel2_blk_req, + lsq_ctl_rel1_tag, + lsq_ctl_rel1_classid, + lsq_ctl_rel1_lock_set, + lsq_ctl_rel1_watch_set, + lsq_ctl_rel2_upd_val, + lsq_ctl_rel3_l1dump_val, + lsq_ctl_rel3_clr_relq, + ctl_lsq_stq4_perr_reject, + ctl_dat_stq5_way_perr_inval, + fgen_ex3_stg_flush, + fgen_ex4_cp_flush, + fgen_ex4_stg_flush, + fgen_ex5_stg_flush, + dir_arr_rd_addr0_01, + dir_arr_rd_addr0_23, + dir_arr_rd_addr0_45, + dir_arr_rd_addr0_67, + dir_arr_rd_data0, + dir_arr_rd_data1, + dir_arr_wr_enable, + dir_arr_wr_way, + dir_arr_wr_addr, + dir_arr_wr_data, + dir_dcc_ex2_eff_addr, + dir_derat_ex2_eff_addr, + dir_dcc_ex4_hit, + dir_dcc_ex4_miss, + ctl_dat_ex4_way_hit, + dir_dcc_stq3_hit, + dir_dcc_ex5_cr_rslt, + ctl_perv_dir_perf_events, + dir_dcc_rel3_dcarr_upd, + dir_dec_rel3_dir_wr_val, + dir_dec_rel3_dir_wr_addr, + stq4_dcarr_way_en, + lq_xu_spr_xucr0_cslc_xuop, + lq_xu_spr_xucr0_cslc_binv, + lq_xu_spr_xucr0_clo, + dir_dcc_ex4_way_tag_a, + dir_dcc_ex4_way_tag_b, + dir_dcc_ex4_way_tag_c, + dir_dcc_ex4_way_tag_d, + dir_dcc_ex4_way_tag_e, + dir_dcc_ex4_way_tag_f, + dir_dcc_ex4_way_tag_g, + dir_dcc_ex4_way_tag_h, + dir_dcc_ex4_way_par_a, + dir_dcc_ex4_way_par_b, + dir_dcc_ex4_way_par_c, + dir_dcc_ex4_way_par_d, + dir_dcc_ex4_way_par_e, + dir_dcc_ex4_way_par_f, + dir_dcc_ex4_way_par_g, + dir_dcc_ex4_way_par_h, + dir_dcc_ex5_way_a_dir, + dir_dcc_ex5_way_b_dir, + dir_dcc_ex5_way_c_dir, + dir_dcc_ex5_way_d_dir, + dir_dcc_ex5_way_e_dir, + dir_dcc_ex5_way_f_dir, + dir_dcc_ex5_way_g_dir, + dir_dcc_ex5_way_h_dir, + dir_dcc_ex5_dir_lru, + dir_dcc_ex4_set_rel_coll, + dir_dcc_ex4_byp_restart, + dir_dcc_ex5_dir_perr_det, + dir_dcc_ex5_dc_perr_det, + dir_dcc_ex5_dir_perr_flush, + dir_dcc_ex5_dc_perr_flush, + dir_dcc_ex5_multihit_det, + dir_dcc_ex5_multihit_flush, + dir_dcc_stq4_dir_perr_det, + dir_dcc_stq4_multihit_det, + dir_dcc_ex5_stp_flush, + vdd, + gnd, + nclk, + sg_0, + func_sl_thold_0_b, + func_sl_force, + func_slp_sl_thold_0_b, + func_slp_sl_force, + func_nsl_thold_0_b, + func_nsl_force, + func_slp_nsl_thold_0_b, + func_slp_nsl_force, + d_mode_dc, + delay_lclkr_dc, + mpw1_dc_b, + mpw2_dc_b, + scan_in, + scan_out +); + +//------------------------------------------------------------------- +// Generics +//------------------------------------------------------------------- +//parameter EXPAND_TYPE = 2; +//parameter THREADS = 2; +//parameter ITAG_SIZE_ENC = 7; +//parameter DC_SIZE = 15; // 14 => 16K L1D$, 15 => 32K L1D$ +//parameter CL_SIZE = 6; // 6 => 64B CLINE, 7 => 128B CLINE +//parameter LMQ_ENTRIES = 8; +//parameter CR_POOL_ENC = 5; +//parameter UCODE_ENTRIES_ENC = 3; +//parameter REAL_IFAR_WIDTH = 42; +//parameter `GPR_WIDTH_ENC = 6; +parameter WAYDATASIZE = 34; // TagSize + Parity Bits +parameter PARBITS = 4; + +// ACT's +input dcc_dir_ex2_stg_act; +input dcc_dir_ex3_stg_act; +input dcc_dir_ex4_stg_act; +input dcc_dir_ex5_stg_act; +input dcc_dir_stq1_stg_act; +input dcc_dir_stq2_stg_act; +input dcc_dir_stq3_stg_act; +input dcc_dir_stq4_stg_act; +input dcc_dir_stq5_stg_act; +input dcc_dir_binv2_ex2_stg_act; +input dcc_dir_binv3_ex3_stg_act; +input dcc_dir_binv4_ex4_stg_act; +input dcc_dir_binv5_ex5_stg_act; +input dcc_dir_binv6_ex6_stg_act; + +// AGEN Sources +input [64-(2**`GPR_WIDTH_ENC):63] byp_dir_ex2_rs1; +input [64-(2**`GPR_WIDTH_ENC):63] byp_dir_ex2_rs2; +input dcc_dir_ex2_64bit_agen; + +// Error Inject +input pc_lq_inj_dcachedir_ldp_parity; +input pc_lq_inj_dcachedir_ldp_multihit; +input pc_lq_inj_dcachedir_stp_parity; +input pc_lq_inj_dcachedir_stp_multihit; + +input dcc_dir_ex2_binv_val; // Back-Invalidate is Valid +input [0:`THREADS-1] dcc_dir_ex2_thrd_id; // Thread ID +input dcc_dir_ex3_cache_acc; // Cache Access is Valid +input dcc_dir_ex3_pfetch_val; +input dcc_dir_ex3_lru_upd; // Dont update LRU indicator +input dcc_dir_ex3_lock_set; // DCBT[ST]LS Operation is valid +input dcc_dir_ex3_th_c; // DCBT[ST]LS Operation is targeting the L1 Data Cache +input dcc_dir_ex3_watch_set; // LDAWX Operation is valid +input dcc_dir_ex3_larx_val; // LARX Operation is valid, the directory should be invalidated if hit +input dcc_dir_ex3_watch_chk; // WCHK Operation is valid +input dcc_dir_ex3_ddir_acc; // Directory Access is valid +input dcc_dir_ex4_load_val; +input [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] dcc_dir_ex4_p_addr; +input derat_dir_ex4_wimge_i; // Cache-Inhibited Request +input dcc_dir_stq6_store_val; + +input [0:7] dat_ctl_dcarr_perr_way; // Data Cache Parity on a Way + +input xu_lq_spr_xucr0_wlk; +input xu_lq_spr_xucr0_dcdis; +input xu_lq_spr_xucr0_clfc; +input xu_lq_spr_xucr0_cls; // Cacheline Size = 1 => 128Byte size, 0 => 64Byte size +input [0:31] dcc_dir_spr_xucr2_rmt; +input dcc_dir_ex2_frc_align16; +input dcc_dir_ex2_frc_align8; +input dcc_dir_ex2_frc_align4; +input dcc_dir_ex2_frc_align2; + +// RELOAD/RECIRC Control +input lsq_ctl_stq1_val; +input lsq_ctl_stq2_blk_req; // Block Store due to RV issue +input [0:`THREADS-1] lsq_ctl_stq1_thrd_id; +input [0:`THREADS-1] lsq_ctl_rel1_thrd_id; +input lsq_ctl_stq1_store_val; // Recir Store instruction +input lsq_ctl_stq1_ci; +input lsq_ctl_stq1_lock_clr; // Recirc Lock Clear instruction +input lsq_ctl_stq1_watch_clr; // Recirc Watch Clear instruction +input [0:1] lsq_ctl_stq1_l_fld; // Recirc Watch Clear L-Field +input lsq_ctl_stq1_inval; // Recirc Invalidate instruction +input lsq_ctl_stq1_dci_val; // Recirc DCI instruction +input [64-`REAL_IFAR_WIDTH:63-`CL_SIZE] lsq_ctl_stq1_addr; +input lsq_ctl_rel1_clr_val; // Reload data is valid for 1st beat +input lsq_ctl_rel1_set_val; // Reload data is valid for last beat +input lsq_ctl_rel1_data_val; // Reload data is valid +input lsq_ctl_rel1_back_inv; // Reload was Back-Invalidated +input lsq_ctl_rel2_blk_req; // Block Reload due to RV issue or Back-Invalidate +input [0:3] lsq_ctl_rel1_tag; // Reload Tag +input [0:1] lsq_ctl_rel1_classid; +input lsq_ctl_rel1_lock_set; // Reload/Recirc Lock Set instruction +input lsq_ctl_rel1_watch_set; // Reload/Recirc Watch Set instruction +input lsq_ctl_rel2_upd_val; // No ECC Errors were detected +input lsq_ctl_rel3_l1dump_val; // Reload Complete for an L1_DUMP reload +input lsq_ctl_rel3_clr_relq; // Reload Complete due to an ECC error +output ctl_lsq_stq4_perr_reject; // STQ4 parity error detected, reject STQ2 Commit +output [0:7] ctl_dat_stq5_way_perr_inval; + +// Instruction Flush +input fgen_ex3_stg_flush; +input fgen_ex4_cp_flush; +input fgen_ex4_stg_flush; +input fgen_ex5_stg_flush; + +// Directory Read Interface +output [64-(`DC_SIZE-3):63-`CL_SIZE] dir_arr_rd_addr0_01; +output [64-(`DC_SIZE-3):63-`CL_SIZE] dir_arr_rd_addr0_23; +output [64-(`DC_SIZE-3):63-`CL_SIZE] dir_arr_rd_addr0_45; +output [64-(`DC_SIZE-3):63-`CL_SIZE] dir_arr_rd_addr0_67; +input [0:(8*WAYDATASIZE)-1] dir_arr_rd_data0; +input [0:(8*WAYDATASIZE)-1] dir_arr_rd_data1; + +// Directory Write Interface +output [0:3] dir_arr_wr_enable; +output [0:7] dir_arr_wr_way; +output [64-(`DC_SIZE-3):63-`CL_SIZE] dir_arr_wr_addr; +output [64-`REAL_IFAR_WIDTH:64-`REAL_IFAR_WIDTH+WAYDATASIZE-1] dir_arr_wr_data; + +// LQ Pipe Outputs +output [64-(2**`GPR_WIDTH_ENC):63] dir_dcc_ex2_eff_addr; +output [0:51] dir_derat_ex2_eff_addr; +output dir_dcc_ex4_hit; +output dir_dcc_ex4_miss; +output [0:7] ctl_dat_ex4_way_hit; // Way Hit + +// COMMIT Pipe Hit indicator +output dir_dcc_stq3_hit; + +// CR results +output dir_dcc_ex5_cr_rslt; // Condition Register Results from Watch instructions + +// Performance Events +output [0:(`THREADS*3)+1] ctl_perv_dir_perf_events; + +// Data Array Controls +output dir_dcc_rel3_dcarr_upd; // Reload Data Array Update Valid +output dir_dec_rel3_dir_wr_val; // Reload Directory Write Stage is valid +output [64-(`DC_SIZE-3):63-`CL_SIZE] dir_dec_rel3_dir_wr_addr; // Reload Directory Write Address +output [0:7] stq4_dcarr_way_en; + +// SPR status +output lq_xu_spr_xucr0_cslc_xuop; // Invalidate type instruction invalidated lock +output lq_xu_spr_xucr0_cslc_binv; // Back-Invalidate invalidated lock +output lq_xu_spr_xucr0_clo; // Cache Lock instruction caused an overlock + +// L1 Directory Contents +output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] dir_dcc_ex4_way_tag_a; +output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] dir_dcc_ex4_way_tag_b; +output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] dir_dcc_ex4_way_tag_c; +output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] dir_dcc_ex4_way_tag_d; +output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] dir_dcc_ex4_way_tag_e; +output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] dir_dcc_ex4_way_tag_f; +output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] dir_dcc_ex4_way_tag_g; +output [64-`REAL_IFAR_WIDTH:63-(`DC_SIZE-3)] dir_dcc_ex4_way_tag_h; +output [0:PARBITS-1] dir_dcc_ex4_way_par_a; +output [0:PARBITS-1] dir_dcc_ex4_way_par_b; +output [0:PARBITS-1] dir_dcc_ex4_way_par_c; +output [0:PARBITS-1] dir_dcc_ex4_way_par_d; +output [0:PARBITS-1] dir_dcc_ex4_way_par_e; +output [0:PARBITS-1] dir_dcc_ex4_way_par_f; +output [0:PARBITS-1] dir_dcc_ex4_way_par_g; +output [0:PARBITS-1] dir_dcc_ex4_way_par_h; +output [0:1+`THREADS] dir_dcc_ex5_way_a_dir; +output [0:1+`THREADS] dir_dcc_ex5_way_b_dir; +output [0:1+`THREADS] dir_dcc_ex5_way_c_dir; +output [0:1+`THREADS] dir_dcc_ex5_way_d_dir; +output [0:1+`THREADS] dir_dcc_ex5_way_e_dir; +output [0:1+`THREADS] dir_dcc_ex5_way_f_dir; +output [0:1+`THREADS] dir_dcc_ex5_way_g_dir; +output [0:1+`THREADS] dir_dcc_ex5_way_h_dir; +output [0:6] dir_dcc_ex5_dir_lru; + +// Reject Cases +output dir_dcc_ex4_set_rel_coll; // Resource Conflict, should cause a reject +output dir_dcc_ex4_byp_restart; // Directory Bypassed stage that was restarted +output dir_dcc_ex5_dir_perr_det; // Parity Error Detected +output dir_dcc_ex5_dc_perr_det; // Data Cache Parity Error Detected +output dir_dcc_ex5_dir_perr_flush; // Data Directory Parity Error Flush +output dir_dcc_ex5_dc_perr_flush; // Data Cache Parity Error Flush +output dir_dcc_ex5_multihit_det; // Directory Multihit Detected +output dir_dcc_ex5_multihit_flush; // Directory Multihit Flush +output dir_dcc_stq4_dir_perr_det; // Data Cache Parity Error Detected on the STQ Commit Pipeline +output dir_dcc_stq4_multihit_det; // Directory Multihit Detected on the STQ Commit Pipeline +output dir_dcc_ex5_stp_flush; // Directory Error detected on the STQ Commit Pipeline with EX5 LDP valid + + +inout vdd; + + +inout gnd; + +(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) + +input [0:`NCLK_WIDTH-1] nclk; +input sg_0; +input func_sl_thold_0_b; +input func_sl_force; +input func_slp_sl_thold_0_b; +input func_slp_sl_force; +input func_nsl_thold_0_b; +input func_nsl_force; +input func_slp_nsl_thold_0_b; +input func_slp_nsl_force; +input d_mode_dc; +input delay_lclkr_dc; +input mpw1_dc_b; +input mpw2_dc_b; + +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + +input [0:4] scan_in; + +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + +output [0:4] scan_out; + +//-------------------------- +// components +//-------------------------- + +//-------------------------- +// signals +//-------------------------- +wire [64-(2**`GPR_WIDTH_ENC):63] ex2_eff_addr; +wire [60:63] ex2_lwr_p_addr; +wire rel4_dir_wr_val_d; +wire rel4_dir_wr_val_q; +wire rel_way_val_a; +wire rel_way_val_b; +wire rel_way_val_c; +wire rel_way_val_d; +wire rel_way_val_e; +wire rel_way_val_f; +wire rel_way_val_g; +wire rel_way_val_h; +wire rel_way_lock_a; +wire rel_way_lock_b; +wire rel_way_lock_c; +wire rel_way_lock_d; +wire rel_way_lock_e; +wire rel_way_lock_f; +wire rel_way_lock_g; +wire rel_way_lock_h; +wire rel_way_clr_a; +wire rel_way_clr_b; +wire rel_way_clr_c; +wire rel_way_clr_d; +wire rel_way_clr_e; +wire rel_way_clr_f; +wire rel_way_clr_g; +wire rel_way_clr_h; +wire rel_way_wen_a; +wire rel_way_wen_b; +wire rel_way_wen_c; +wire rel_way_wen_d; +wire rel_way_wen_e; +wire rel_way_wen_f; +wire rel_way_wen_g; +wire rel_way_wen_h; +wire rel_way_upd_a; +wire rel_way_upd_b; +wire rel_way_upd_c; +wire rel_way_upd_d; +wire rel_way_upd_e; +wire rel_way_upd_f; +wire rel_way_upd_g; +wire rel_way_upd_h; +wire rel3_dir_wr_val; +wire [64-(`DC_SIZE-3):63-`CL_SIZE] rel3_dir_wr_addr; +wire ex4_l1hit; +wire ex4_l1miss; +wire ex4_way_cmp_a; +wire ex4_way_cmp_b; +wire ex4_way_cmp_c; +wire ex4_way_cmp_d; +wire ex4_way_cmp_e; +wire ex4_way_cmp_f; +wire ex4_way_cmp_g; +wire ex4_way_cmp_h; +wire ex4_way_hit_a; +wire ex4_way_hit_b; +wire ex4_way_hit_c; +wire ex4_way_hit_d; +wire ex4_way_hit_e; +wire ex4_way_hit_f; +wire ex4_way_hit_g; +wire ex4_way_hit_h; +wire [0:7] ex4_tag_perr_way; +wire spr_xucr0_dcdis_d; +wire spr_xucr0_dcdis_q; +wire spr_xucr0_cls_b; +wire spr_xucr0_cls_d; +wire spr_xucr0_cls_q; +wire stq3_way_cmp_a; +wire stq3_way_cmp_b; +wire stq3_way_cmp_c; +wire stq3_way_cmp_d; +wire stq3_way_cmp_e; +wire stq3_way_cmp_f; +wire stq3_way_cmp_g; +wire stq3_way_cmp_h; +wire [0:7] stq3_tag_way_perr; +wire stq3_way_hit_a; +wire stq3_way_hit_b; +wire stq3_way_hit_c; +wire stq3_way_hit_d; +wire stq3_way_hit_e; +wire stq3_way_hit_f; +wire stq3_way_hit_g; +wire stq3_way_hit_h; +wire stq3_miss; +wire stq3_hit; +wire stq1_lru_upd; +wire stq2_ddir_acc; +wire [0:7] dir_arr_wr_way_int; +wire [64-(`DC_SIZE-3):63-`CL_SIZE] dir_arr_wr_addr_int; +wire dir_tag_scanout; + +//-------------------------- +// constants +//-------------------------- +parameter rel4_dir_wr_val_offset = 0; +parameter spr_xucr0_dcdis_offset = rel4_dir_wr_val_offset + 1; +parameter spr_xucr0_cls_offset = spr_xucr0_dcdis_offset + 1; +parameter scan_right = spr_xucr0_cls_offset + 1 - 1; + +wire tiup; +wire [0:scan_right] siv; +wire [0:scan_right] sov; + + +(* analysis_not_referenced="true" *) + +wire unused; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Inputs +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +assign tiup = 1'b1; +assign unused = stq3_miss; + +// Force Alignment +assign ex2_lwr_p_addr[60] = ex2_eff_addr[60] & (~dcc_dir_ex2_frc_align16); +assign ex2_lwr_p_addr[61] = ex2_eff_addr[61] & (~(dcc_dir_ex2_frc_align16 | dcc_dir_ex2_frc_align8)); +assign ex2_lwr_p_addr[62] = ex2_eff_addr[62] & (~(dcc_dir_ex2_frc_align16 | dcc_dir_ex2_frc_align8 | dcc_dir_ex2_frc_align4)); +assign ex2_lwr_p_addr[63] = ex2_eff_addr[63] & (~(dcc_dir_ex2_frc_align16 | dcc_dir_ex2_frc_align8 | dcc_dir_ex2_frc_align4 | dcc_dir_ex2_frc_align2)); + +assign rel4_dir_wr_val_d = rel3_dir_wr_val; +assign stq1_lru_upd = lsq_ctl_stq1_store_val & (~lsq_ctl_stq1_inval); +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// XU Config Bits +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +// XUCR0[DC_DIS] Data Cache Disabled +// 1 => L1 Data Cache Disabled +// 0 => L1 Data Cache Enabled +assign spr_xucr0_dcdis_d = xu_lq_spr_xucr0_dcdis; + +// XUCR0[CLS] 128 Byte Cacheline Enabled +// 1 => 128 Byte Cacheline +// 0 => 64 Byte Cacheline +assign spr_xucr0_cls_d = xu_lq_spr_xucr0_cls; +assign spr_xucr0_cls_b = (~spr_xucr0_cls_q); + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// AGEN Adder +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +generate + if (`GPR_WIDTH_ENC == 5) begin : Mode32b + assign ex2_eff_addr = byp_dir_ex2_rs1 + byp_dir_ex2_rs2; + assign dir_arr_rd_addr0_01[64-(`DC_SIZE-3):63-`CL_SIZE-1] = ex2_eff_addr[64-(`DC_SIZE-3):63-`CL_SIZE-1]; + assign dir_arr_rd_addr0_01[63-`CL_SIZE] = ex2_eff_addr[63-`CL_SIZE] | spr_xucr0_cls_q; + assign dir_arr_rd_addr0_23[64-(`DC_SIZE-3):63-`CL_SIZE-1] = ex2_eff_addr[64-(`DC_SIZE-3):63-`CL_SIZE-1]; + assign dir_arr_rd_addr0_23[63-`CL_SIZE] = ex2_eff_addr[63-`CL_SIZE] | spr_xucr0_cls_q; + assign dir_arr_rd_addr0_45[64-(`DC_SIZE-3):63-`CL_SIZE-1] = ex2_eff_addr[64-(`DC_SIZE-3):63-`CL_SIZE-1]; + assign dir_arr_rd_addr0_45[63-`CL_SIZE] = ex2_eff_addr[63-`CL_SIZE] | spr_xucr0_cls_q; + assign dir_arr_rd_addr0_67[64-(`DC_SIZE-3):63-`CL_SIZE-1] = ex2_eff_addr[64-(`DC_SIZE-3):63-`CL_SIZE-1]; + assign dir_arr_rd_addr0_67[63-`CL_SIZE] = ex2_eff_addr[63-`CL_SIZE] | spr_xucr0_cls_q; + assign dir_derat_ex2_eff_addr[0:31] = {32{1'b0}}; + assign dir_derat_ex2_eff_addr[32:51] = ex2_eff_addr[32:51]; + assign dir_arr_wr_enable[0] = rel4_dir_wr_val_q & (dir_arr_wr_way_int[0] | dir_arr_wr_way_int[1]); + assign dir_arr_wr_enable[1] = rel4_dir_wr_val_q & (dir_arr_wr_way_int[2] | dir_arr_wr_way_int[3]); + assign dir_arr_wr_enable[2] = rel4_dir_wr_val_q & (dir_arr_wr_way_int[4] | dir_arr_wr_way_int[5]); + assign dir_arr_wr_enable[3] = rel4_dir_wr_val_q & (dir_arr_wr_way_int[6] | dir_arr_wr_way_int[7]); + end +endgenerate + +generate + if (`GPR_WIDTH_ENC == 6) begin : Mode64b + lq_agen agen( + .x(byp_dir_ex2_rs1), + .y(byp_dir_ex2_rs2), + .mode64(dcc_dir_ex2_64bit_agen), + .dir_ig_57_b(spr_xucr0_cls_b), + + .sum_non_erat(ex2_eff_addr), + .sum(dir_derat_ex2_eff_addr), + .sum_arr_dir01(dir_arr_rd_addr0_01), + .sum_arr_dir23(dir_arr_rd_addr0_23), + .sum_arr_dir45(dir_arr_rd_addr0_45), + .sum_arr_dir67(dir_arr_rd_addr0_67), + + .way(dir_arr_wr_way_int), + .rel4_dir_wr_val(rel4_dir_wr_val_q), + .ary_write_act_01(dir_arr_wr_enable[0]), + .ary_write_act_23(dir_arr_wr_enable[1]), + .ary_write_act_45(dir_arr_wr_enable[2]), + .ary_write_act_67(dir_arr_wr_enable[3]) + ); + end +endgenerate + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Directory Valids Array +// 1) Contains an Array of Valids +// 2) Updates Valid bits on Reloads +// 3) Invalidates Valid bits for Flush type commands and Back Invalidates +// 4) Outputs Valids for Congruence Class +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +lq_dir_val l1dcdv( + + // ACT's + .dcc_dir_ex2_stg_act(dcc_dir_ex2_stg_act), + .dcc_dir_ex3_stg_act(dcc_dir_ex3_stg_act), + .dcc_dir_ex4_stg_act(dcc_dir_ex4_stg_act), + .dcc_dir_stq1_stg_act(dcc_dir_stq1_stg_act), + .dcc_dir_stq2_stg_act(dcc_dir_stq2_stg_act), + .dcc_dir_stq3_stg_act(dcc_dir_stq3_stg_act), + .dcc_dir_stq4_stg_act(dcc_dir_stq4_stg_act), + .dcc_dir_stq5_stg_act(dcc_dir_stq5_stg_act), + .dcc_dir_binv2_ex2_stg_act(dcc_dir_binv2_ex2_stg_act), + .dcc_dir_binv3_ex3_stg_act(dcc_dir_binv3_ex3_stg_act), + .dcc_dir_binv4_ex4_stg_act(dcc_dir_binv4_ex4_stg_act), + .dcc_dir_binv5_ex5_stg_act(dcc_dir_binv5_ex5_stg_act), + .dcc_dir_binv6_ex6_stg_act(dcc_dir_binv6_ex6_stg_act), + + // Reload and Store Commit Pipe + .lsq_ctl_stq1_val(lsq_ctl_stq1_val), + .lsq_ctl_stq2_blk_req(lsq_ctl_stq2_blk_req), + .lsq_ctl_stq1_thrd_id(lsq_ctl_stq1_thrd_id), + .lsq_ctl_rel1_thrd_id(lsq_ctl_rel1_thrd_id), + .lsq_ctl_stq1_ci(lsq_ctl_stq1_ci), + .lsq_ctl_stq1_lock_clr(lsq_ctl_stq1_lock_clr), + .lsq_ctl_stq1_watch_clr(lsq_ctl_stq1_watch_clr), + .lsq_ctl_stq1_store_val(lsq_ctl_stq1_store_val), + .lsq_ctl_stq1_inval(lsq_ctl_stq1_inval), + .lsq_ctl_stq1_dci_val(lsq_ctl_stq1_dci_val), + .lsq_ctl_stq1_l_fld(lsq_ctl_stq1_l_fld), + .lsq_ctl_stq1_addr(lsq_ctl_stq1_addr[64 - (`DC_SIZE - 3):63 - `CL_SIZE]), + .lsq_ctl_rel1_clr_val(lsq_ctl_rel1_clr_val), + .lsq_ctl_rel1_set_val(lsq_ctl_rel1_set_val), + .lsq_ctl_rel1_back_inv(lsq_ctl_rel1_back_inv), + .lsq_ctl_rel2_blk_req(lsq_ctl_rel2_blk_req), + .lsq_ctl_rel2_upd_val(lsq_ctl_rel2_upd_val), + .lsq_ctl_rel3_l1dump_val(lsq_ctl_rel3_l1dump_val), + .lsq_ctl_rel1_lock_set(lsq_ctl_rel1_lock_set), + .lsq_ctl_rel1_watch_set(lsq_ctl_rel1_watch_set), + .dcc_dir_stq6_store_val(dcc_dir_stq6_store_val), + + .rel_way_clr_a(rel_way_clr_a), + .rel_way_clr_b(rel_way_clr_b), + .rel_way_clr_c(rel_way_clr_c), + .rel_way_clr_d(rel_way_clr_d), + .rel_way_clr_e(rel_way_clr_e), + .rel_way_clr_f(rel_way_clr_f), + .rel_way_clr_g(rel_way_clr_g), + .rel_way_clr_h(rel_way_clr_h), + + .rel_way_wen_a(rel_way_wen_a), + .rel_way_wen_b(rel_way_wen_b), + .rel_way_wen_c(rel_way_wen_c), + .rel_way_wen_d(rel_way_wen_d), + .rel_way_wen_e(rel_way_wen_e), + .rel_way_wen_f(rel_way_wen_f), + .rel_way_wen_g(rel_way_wen_g), + .rel_way_wen_h(rel_way_wen_h), + + .xu_lq_spr_xucr0_clfc(xu_lq_spr_xucr0_clfc), + .spr_xucr0_dcdis(spr_xucr0_dcdis_q), + .spr_xucr0_cls(spr_xucr0_cls_q), + + // Execution Pipe + .dcc_dir_ex2_binv_val(dcc_dir_ex2_binv_val), + .dcc_dir_ex2_thrd_id(dcc_dir_ex2_thrd_id), + .ex2_eff_addr(ex2_eff_addr[64 - (`DC_SIZE - 3):63 - `CL_SIZE]), + .dcc_dir_ex3_cache_acc(dcc_dir_ex3_cache_acc), + .dcc_dir_ex3_pfetch_val(dcc_dir_ex3_pfetch_val), + .dcc_dir_ex3_lock_set(dcc_dir_ex3_lock_set), + .dcc_dir_ex3_th_c(dcc_dir_ex3_th_c), + .dcc_dir_ex3_watch_set(dcc_dir_ex3_watch_set), + .dcc_dir_ex3_larx_val(dcc_dir_ex3_larx_val), + .dcc_dir_ex3_watch_chk(dcc_dir_ex3_watch_chk), + .dcc_dir_ex4_load_val(dcc_dir_ex4_load_val), + .derat_dir_ex4_wimge_i(derat_dir_ex4_wimge_i), + + // Execution Pipe Flush + .fgen_ex3_stg_flush(fgen_ex3_stg_flush), + .fgen_ex4_cp_flush(fgen_ex4_cp_flush), + .fgen_ex4_stg_flush(fgen_ex4_stg_flush), + .fgen_ex5_stg_flush(fgen_ex5_stg_flush), + + // Directory Parity Error for Execution Pipe + .ex4_tag_perr_way(ex4_tag_perr_way), + .dat_ctl_dcarr_perr_way(dat_ctl_dcarr_perr_way), + + // Tag Compares + .ex4_way_cmp_a(ex4_way_cmp_a), + .ex4_way_cmp_b(ex4_way_cmp_b), + .ex4_way_cmp_c(ex4_way_cmp_c), + .ex4_way_cmp_d(ex4_way_cmp_d), + .ex4_way_cmp_e(ex4_way_cmp_e), + .ex4_way_cmp_f(ex4_way_cmp_f), + .ex4_way_cmp_g(ex4_way_cmp_g), + .ex4_way_cmp_h(ex4_way_cmp_h), + + // Commit Pipe + .stq3_way_cmp_a(stq3_way_cmp_a), + .stq3_way_cmp_b(stq3_way_cmp_b), + .stq3_way_cmp_c(stq3_way_cmp_c), + .stq3_way_cmp_d(stq3_way_cmp_d), + .stq3_way_cmp_e(stq3_way_cmp_e), + .stq3_way_cmp_f(stq3_way_cmp_f), + .stq3_way_cmp_g(stq3_way_cmp_g), + .stq3_way_cmp_h(stq3_way_cmp_h), + + // Directory Parity Error for Store Commit Pipe + .stq3_tag_way_perr(stq3_tag_way_perr), + + // Multihit Error Inject + .pc_lq_inj_dcachedir_ldp_multihit(pc_lq_inj_dcachedir_ldp_multihit), + .pc_lq_inj_dcachedir_stp_multihit(pc_lq_inj_dcachedir_stp_multihit), + + // L1 Directory Contents + .dir_dcc_ex5_way_a_dir(dir_dcc_ex5_way_a_dir), + .dir_dcc_ex5_way_b_dir(dir_dcc_ex5_way_b_dir), + .dir_dcc_ex5_way_c_dir(dir_dcc_ex5_way_c_dir), + .dir_dcc_ex5_way_d_dir(dir_dcc_ex5_way_d_dir), + .dir_dcc_ex5_way_e_dir(dir_dcc_ex5_way_e_dir), + .dir_dcc_ex5_way_f_dir(dir_dcc_ex5_way_f_dir), + .dir_dcc_ex5_way_g_dir(dir_dcc_ex5_way_g_dir), + .dir_dcc_ex5_way_h_dir(dir_dcc_ex5_way_h_dir), + + // L1 Directory Hits + .ex4_way_hit_a(ex4_way_hit_a), + .ex4_way_hit_b(ex4_way_hit_b), + .ex4_way_hit_c(ex4_way_hit_c), + .ex4_way_hit_d(ex4_way_hit_d), + .ex4_way_hit_e(ex4_way_hit_e), + .ex4_way_hit_f(ex4_way_hit_f), + .ex4_way_hit_g(ex4_way_hit_g), + .ex4_way_hit_h(ex4_way_hit_h), + + // ex4 Execution Pipe Command Outputs + .ex4_miss(ex4_l1miss), + .ex4_hit(ex4_l1hit), + .dir_dcc_ex4_set_rel_coll(dir_dcc_ex4_set_rel_coll), + .dir_dcc_ex4_byp_restart(dir_dcc_ex4_byp_restart), + .dir_dcc_ex5_dir_perr_det(dir_dcc_ex5_dir_perr_det), + .dir_dcc_ex5_dc_perr_det(dir_dcc_ex5_dc_perr_det), + .dir_dcc_ex5_dir_perr_flush(dir_dcc_ex5_dir_perr_flush), + .dir_dcc_ex5_dc_perr_flush(dir_dcc_ex5_dc_perr_flush), + .dir_dcc_ex5_multihit_det(dir_dcc_ex5_multihit_det), + .dir_dcc_ex5_multihit_flush(dir_dcc_ex5_multihit_flush), + .dir_dcc_stq4_dir_perr_det(dir_dcc_stq4_dir_perr_det), + .dir_dcc_stq4_multihit_det(dir_dcc_stq4_multihit_det), + .dir_dcc_ex5_stp_flush(dir_dcc_ex5_stp_flush), + + // Performance Events + .ctl_perv_dir_perf_events(ctl_perv_dir_perf_events), + + // SPR status + .lq_xu_spr_xucr0_cslc_xuop(lq_xu_spr_xucr0_cslc_xuop), + .lq_xu_spr_xucr0_cslc_binv(lq_xu_spr_xucr0_cslc_binv), + + // ex5 Execution Pipe Command Outputs + .dir_dcc_ex5_cr_rslt(dir_dcc_ex5_cr_rslt), + + // stq4 Commit Pipe Command Outputs + .stq2_ddir_acc(stq2_ddir_acc), + .stq3_way_hit_a(stq3_way_hit_a), + .stq3_way_hit_b(stq3_way_hit_b), + .stq3_way_hit_c(stq3_way_hit_c), + .stq3_way_hit_d(stq3_way_hit_d), + .stq3_way_hit_e(stq3_way_hit_e), + .stq3_way_hit_f(stq3_way_hit_f), + .stq3_way_hit_g(stq3_way_hit_g), + .stq3_way_hit_h(stq3_way_hit_h), + .stq3_miss(stq3_miss), + .stq3_hit(stq3_hit), + .ctl_lsq_stq4_perr_reject(ctl_lsq_stq4_perr_reject), + .ctl_dat_stq5_way_perr_inval(ctl_dat_stq5_way_perr_inval), + + // Way Valids for Replacement Algorithm + .rel_way_val_a(rel_way_val_a), + .rel_way_val_b(rel_way_val_b), + .rel_way_val_c(rel_way_val_c), + .rel_way_val_d(rel_way_val_d), + .rel_way_val_e(rel_way_val_e), + .rel_way_val_f(rel_way_val_f), + .rel_way_val_g(rel_way_val_g), + .rel_way_val_h(rel_way_val_h), + + // Congruence Class Line Lock + .rel_way_lock_a(rel_way_lock_a), + .rel_way_lock_b(rel_way_lock_b), + .rel_way_lock_c(rel_way_lock_c), + .rel_way_lock_d(rel_way_lock_d), + .rel_way_lock_e(rel_way_lock_e), + .rel_way_lock_f(rel_way_lock_f), + .rel_way_lock_g(rel_way_lock_g), + .rel_way_lock_h(rel_way_lock_h), + + //pervasive + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .sg_0(sg_0), + .func_sl_thold_0_b(func_sl_thold_0_b), + .func_sl_force(func_sl_force), + .func_slp_sl_thold_0_b(func_slp_sl_thold_0_b), + .func_slp_sl_force(func_slp_sl_force), + .func_nsl_thold_0_b(func_nsl_thold_0_b), + .func_nsl_force(func_nsl_force), + .func_slp_nsl_thold_0_b(func_slp_nsl_thold_0_b), + .func_slp_nsl_force(func_slp_nsl_force), + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .scan_in(scan_in[0:2]), + .scan_out(scan_out[0:2]) +); + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// LRU Register Array +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +lq_dir_lru l1dcdl( + + // ACT's + .dcc_dir_ex2_stg_act(dcc_dir_ex2_stg_act), + .dcc_dir_ex3_stg_act(dcc_dir_ex3_stg_act), + .dcc_dir_ex4_stg_act(dcc_dir_ex4_stg_act), + .dcc_dir_ex5_stg_act(dcc_dir_ex5_stg_act), + .dcc_dir_stq1_stg_act(dcc_dir_stq1_stg_act), + .dcc_dir_stq2_stg_act(dcc_dir_stq2_stg_act), + .dcc_dir_stq3_stg_act(dcc_dir_stq3_stg_act), + + // Inputs + //Reload path + .lsq_ctl_stq1_val(lsq_ctl_stq1_val), + .lsq_ctl_stq2_blk_req(lsq_ctl_stq2_blk_req), + .lsq_ctl_stq1_ci(lsq_ctl_stq1_ci), + .lsq_ctl_stq1_addr(lsq_ctl_stq1_addr[64 - (`DC_SIZE - 3):63 - `CL_SIZE]), + .lsq_ctl_rel1_clr_val(lsq_ctl_rel1_clr_val), + .lsq_ctl_rel1_set_val(lsq_ctl_rel1_set_val), + .lsq_ctl_rel1_data_val(lsq_ctl_rel1_data_val), + .lsq_ctl_rel2_blk_req(lsq_ctl_rel2_blk_req), + .lsq_ctl_rel1_lock_set(lsq_ctl_rel1_lock_set), + .lsq_ctl_rel1_classid(lsq_ctl_rel1_classid), + .lsq_ctl_rel1_tag(lsq_ctl_rel1_tag), + .lsq_ctl_rel3_clr_relq(lsq_ctl_rel3_clr_relq), + .stq1_lru_upd(stq1_lru_upd), + + // stq3 Commit Pipe Command Inputs + .stq3_way_hit_a(stq3_way_hit_a), + .stq3_way_hit_b(stq3_way_hit_b), + .stq3_way_hit_c(stq3_way_hit_c), + .stq3_way_hit_d(stq3_way_hit_d), + .stq3_way_hit_e(stq3_way_hit_e), + .stq3_way_hit_f(stq3_way_hit_f), + .stq3_way_hit_g(stq3_way_hit_g), + .stq3_way_hit_h(stq3_way_hit_h), + .stq3_hit(stq3_hit), + + // Way Valids for Replacement Algorithm + .rel_way_val_a(rel_way_val_a), + .rel_way_val_b(rel_way_val_b), + .rel_way_val_c(rel_way_val_c), + .rel_way_val_d(rel_way_val_d), + .rel_way_val_e(rel_way_val_e), + .rel_way_val_f(rel_way_val_f), + .rel_way_val_g(rel_way_val_g), + .rel_way_val_h(rel_way_val_h), + + // Congruence Class Line Lock + .rel_way_lock_a(rel_way_lock_a), + .rel_way_lock_b(rel_way_lock_b), + .rel_way_lock_c(rel_way_lock_c), + .rel_way_lock_d(rel_way_lock_d), + .rel_way_lock_e(rel_way_lock_e), + .rel_way_lock_f(rel_way_lock_f), + .rel_way_lock_g(rel_way_lock_g), + .rel_way_lock_h(rel_way_lock_h), + + //Execution path + .ex2_eff_addr(ex2_eff_addr[64 - (`DC_SIZE - 3):63 - `CL_SIZE]), + .dcc_dir_ex3_cache_acc(dcc_dir_ex3_cache_acc), + .dcc_dir_ex3_lru_upd(dcc_dir_ex3_lru_upd), + .derat_dir_ex4_wimge_i(derat_dir_ex4_wimge_i), + + // Way Hit for Execution Pipe + .ex4_way_hit_a(ex4_way_hit_a), + .ex4_way_hit_b(ex4_way_hit_b), + .ex4_way_hit_c(ex4_way_hit_c), + .ex4_way_hit_d(ex4_way_hit_d), + .ex4_way_hit_e(ex4_way_hit_e), + .ex4_way_hit_f(ex4_way_hit_f), + .ex4_way_hit_g(ex4_way_hit_g), + .ex4_way_hit_h(ex4_way_hit_h), + .ex4_hit(ex4_l1hit), + + // SPR's + .dcc_dir_spr_xucr2_rmt(dcc_dir_spr_xucr2_rmt), + .spr_xucr0_dcdis(spr_xucr0_dcdis_q), + .xu_lq_spr_xucr0_wlk(xu_lq_spr_xucr0_wlk), + .spr_xucr0_cls(spr_xucr0_cls_q), + + // Flush Signals + .fgen_ex3_stg_flush(fgen_ex3_stg_flush), + .fgen_ex4_stg_flush(fgen_ex4_stg_flush), + .fgen_ex5_stg_flush(fgen_ex5_stg_flush), + + // Outputs + // Way Data Cache Write Enables on a Reload + .rel_way_wen_a(rel_way_wen_a), + .rel_way_wen_b(rel_way_wen_b), + .rel_way_wen_c(rel_way_wen_c), + .rel_way_wen_d(rel_way_wen_d), + .rel_way_wen_e(rel_way_wen_e), + .rel_way_wen_f(rel_way_wen_f), + .rel_way_wen_g(rel_way_wen_g), + .rel_way_wen_h(rel_way_wen_h), + + // Way Directory Write Enables on a Reload + .rel_way_upd_a(rel_way_upd_a), + .rel_way_upd_b(rel_way_upd_b), + .rel_way_upd_c(rel_way_upd_c), + .rel_way_upd_d(rel_way_upd_d), + .rel_way_upd_e(rel_way_upd_e), + .rel_way_upd_f(rel_way_upd_f), + .rel_way_upd_g(rel_way_upd_g), + .rel_way_upd_h(rel_way_upd_h), + + // Way Invalidate on a Reload + .rel_way_clr_a(rel_way_clr_a), + .rel_way_clr_b(rel_way_clr_b), + .rel_way_clr_c(rel_way_clr_c), + .rel_way_clr_d(rel_way_clr_d), + .rel_way_clr_e(rel_way_clr_e), + .rel_way_clr_f(rel_way_clr_f), + .rel_way_clr_g(rel_way_clr_g), + .rel_way_clr_h(rel_way_clr_h), + .rel3_dir_wr_val(rel3_dir_wr_val), + .rel3_dir_wr_addr(rel3_dir_wr_addr), + .dir_dcc_rel3_dcarr_upd(dir_dcc_rel3_dcarr_upd), + + // Way Write Enable on a Reload for Data + .stq4_dcarr_way_en(stq4_dcarr_way_en), + + // Directory LRU in EX5 + .dir_dcc_ex5_dir_lru(dir_dcc_ex5_dir_lru), + + // SPR Status + .lq_xu_spr_xucr0_clo(lq_xu_spr_xucr0_clo), + + //pervasive + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .sg_0(sg_0), + .func_sl_thold_0_b(func_sl_thold_0_b), + .func_sl_force(func_sl_force), + .func_nsl_thold_0_b(func_nsl_thold_0_b), + .func_nsl_force(func_nsl_force), + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .scan_in(scan_in[3]), + .scan_out(scan_out[3]) +); + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Directory Tag Array +// 1) Contains an Array of Tags +// 2) Updates Tag on Reload +// 3) Contains Hit Logic +// 4) Outputs Way Hit indicators +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +lq_dir_tag #(.WAYDATASIZE(WAYDATASIZE), .PARBITS(PARBITS)) l1dcdt( + + // Stage ACT Signals + .dcc_dir_binv3_ex3_stg_act(dcc_dir_binv3_ex3_stg_act), + .dcc_dir_stq1_stg_act(dcc_dir_stq1_stg_act), + .dcc_dir_stq2_stg_act(dcc_dir_stq2_stg_act), + .dcc_dir_stq3_stg_act(dcc_dir_stq3_stg_act), + + // Reload Update Directory + .rel_way_upd_a(rel_way_upd_a), + .rel_way_upd_b(rel_way_upd_b), + .rel_way_upd_c(rel_way_upd_c), + .rel_way_upd_d(rel_way_upd_d), + .rel_way_upd_e(rel_way_upd_e), + .rel_way_upd_f(rel_way_upd_f), + .rel_way_upd_g(rel_way_upd_g), + .rel_way_upd_h(rel_way_upd_h), + + // Back-Invalidate + .dcc_dir_ex2_binv_val(dcc_dir_ex2_binv_val), + + // SPR Bits + .spr_xucr0_dcdis(spr_xucr0_dcdis_q), + + // LQ Pipe + .dcc_dir_ex4_p_addr(dcc_dir_ex4_p_addr), + .dcc_dir_ex3_ddir_acc(dcc_dir_ex3_ddir_acc), + + // Commit Pipe + .lsq_ctl_stq1_addr(lsq_ctl_stq1_addr), + .stq2_ddir_acc(stq2_ddir_acc), + + // Error Inject + .pc_lq_inj_dcachedir_ldp_parity(pc_lq_inj_dcachedir_ldp_parity), + .pc_lq_inj_dcachedir_stp_parity(pc_lq_inj_dcachedir_stp_parity), + + // L1 Directory Read Interface + .dir_arr_rd_data0(dir_arr_rd_data0), + .dir_arr_rd_data1(dir_arr_rd_data1), + + // L1 Directory Write Interface + .dir_arr_wr_way(dir_arr_wr_way_int), + .dir_arr_wr_addr(dir_arr_wr_addr_int), + .dir_arr_wr_data(dir_arr_wr_data), + + // LQ Pipe + .ex4_way_cmp_a(ex4_way_cmp_a), + .ex4_way_cmp_b(ex4_way_cmp_b), + .ex4_way_cmp_c(ex4_way_cmp_c), + .ex4_way_cmp_d(ex4_way_cmp_d), + .ex4_way_cmp_e(ex4_way_cmp_e), + .ex4_way_cmp_f(ex4_way_cmp_f), + .ex4_way_cmp_g(ex4_way_cmp_g), + .ex4_way_cmp_h(ex4_way_cmp_h), + .ex4_tag_perr_way(ex4_tag_perr_way), + + // L1 Directory Contents + .dir_dcc_ex4_way_tag_a(dir_dcc_ex4_way_tag_a), + .dir_dcc_ex4_way_tag_b(dir_dcc_ex4_way_tag_b), + .dir_dcc_ex4_way_tag_c(dir_dcc_ex4_way_tag_c), + .dir_dcc_ex4_way_tag_d(dir_dcc_ex4_way_tag_d), + .dir_dcc_ex4_way_tag_e(dir_dcc_ex4_way_tag_e), + .dir_dcc_ex4_way_tag_f(dir_dcc_ex4_way_tag_f), + .dir_dcc_ex4_way_tag_g(dir_dcc_ex4_way_tag_g), + .dir_dcc_ex4_way_tag_h(dir_dcc_ex4_way_tag_h), + .dir_dcc_ex4_way_par_a(dir_dcc_ex4_way_par_a), + .dir_dcc_ex4_way_par_b(dir_dcc_ex4_way_par_b), + .dir_dcc_ex4_way_par_c(dir_dcc_ex4_way_par_c), + .dir_dcc_ex4_way_par_d(dir_dcc_ex4_way_par_d), + .dir_dcc_ex4_way_par_e(dir_dcc_ex4_way_par_e), + .dir_dcc_ex4_way_par_f(dir_dcc_ex4_way_par_f), + .dir_dcc_ex4_way_par_g(dir_dcc_ex4_way_par_g), + .dir_dcc_ex4_way_par_h(dir_dcc_ex4_way_par_h), + + // Commit Pipe + .stq3_way_cmp_a(stq3_way_cmp_a), + .stq3_way_cmp_b(stq3_way_cmp_b), + .stq3_way_cmp_c(stq3_way_cmp_c), + .stq3_way_cmp_d(stq3_way_cmp_d), + .stq3_way_cmp_e(stq3_way_cmp_e), + .stq3_way_cmp_f(stq3_way_cmp_f), + .stq3_way_cmp_g(stq3_way_cmp_g), + .stq3_way_cmp_h(stq3_way_cmp_h), + .stq3_tag_way_perr(stq3_tag_way_perr), + + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .sg_0(sg_0), + .func_sl_thold_0_b(func_sl_thold_0_b), + .func_sl_force(func_sl_force), + .func_slp_sl_thold_0_b(func_slp_sl_thold_0_b), + .func_slp_sl_force(func_slp_sl_force), + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .scan_in(scan_in[4]), + .scan_out(dir_tag_scanout) +); +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Outputs +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +assign ctl_dat_ex4_way_hit = {ex4_way_hit_a, ex4_way_hit_b, ex4_way_hit_c, ex4_way_hit_d, + ex4_way_hit_e, ex4_way_hit_f, ex4_way_hit_g, ex4_way_hit_h}; + +assign dir_arr_wr_way = dir_arr_wr_way_int; +assign dir_arr_wr_addr = dir_arr_wr_addr_int; + +assign dir_dcc_ex2_eff_addr = {ex2_eff_addr[(64 - (2 ** `GPR_WIDTH_ENC)):59], ex2_lwr_p_addr}; +assign dir_dcc_stq3_hit = stq3_hit; +assign dir_dcc_ex4_hit = ex4_l1hit; +assign dir_dcc_ex4_miss = ex4_l1miss; + +assign dir_dec_rel3_dir_wr_val = rel3_dir_wr_val; +assign dir_dec_rel3_dir_wr_addr = rel3_dir_wr_addr; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Registers +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel4_dir_wr_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rel4_dir_wr_val_offset]), + .scout(sov[rel4_dir_wr_val_offset]), + .din(rel4_dir_wr_val_d), + .dout(rel4_dir_wr_val_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr0_dcdis_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_xucr0_dcdis_offset]), + .scout(sov[spr_xucr0_dcdis_offset]), + .din(spr_xucr0_dcdis_d), + .dout(spr_xucr0_dcdis_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr0_cls_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_xucr0_cls_offset]), + .scout(sov[spr_xucr0_cls_offset]), + .din(spr_xucr0_cls_d), + .dout(spr_xucr0_cls_q) +); + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +assign siv[0:scan_right] = {sov[1:scan_right], dir_tag_scanout}; +assign scan_out[4] = sov[0]; + +endmodule diff --git a/dev/verilog/work/lq_dir_lru.v b/dev/verilog/work/lq_dir_lru.v new file mode 100755 index 0000000..d2d44cb --- /dev/null +++ b/dev/verilog/work/lq_dir_lru.v @@ -0,0 +1,2272 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +// +// Description: XU LSU L1 Data Directory LRU Register Array +// +//***************************************************************************** + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" + +module lq_dir_lru( + dcc_dir_ex2_stg_act, + dcc_dir_ex3_stg_act, + dcc_dir_ex4_stg_act, + dcc_dir_ex5_stg_act, + dcc_dir_stq1_stg_act, + dcc_dir_stq2_stg_act, + dcc_dir_stq3_stg_act, + lsq_ctl_stq1_val, + lsq_ctl_stq2_blk_req, + lsq_ctl_stq1_ci, + lsq_ctl_stq1_addr, + lsq_ctl_rel1_clr_val, + lsq_ctl_rel1_set_val, + lsq_ctl_rel1_data_val, + lsq_ctl_rel2_blk_req, + lsq_ctl_rel1_lock_set, + lsq_ctl_rel1_classid, + lsq_ctl_rel1_tag, + lsq_ctl_rel3_clr_relq, + stq1_lru_upd, + stq3_way_hit_a, + stq3_way_hit_b, + stq3_way_hit_c, + stq3_way_hit_d, + stq3_way_hit_e, + stq3_way_hit_f, + stq3_way_hit_g, + stq3_way_hit_h, + stq3_hit, + rel_way_val_a, + rel_way_val_b, + rel_way_val_c, + rel_way_val_d, + rel_way_val_e, + rel_way_val_f, + rel_way_val_g, + rel_way_val_h, + rel_way_lock_a, + rel_way_lock_b, + rel_way_lock_c, + rel_way_lock_d, + rel_way_lock_e, + rel_way_lock_f, + rel_way_lock_g, + rel_way_lock_h, + ex2_eff_addr, + dcc_dir_ex3_cache_acc, + dcc_dir_ex3_lru_upd, + derat_dir_ex4_wimge_i, + ex4_way_hit_a, + ex4_way_hit_b, + ex4_way_hit_c, + ex4_way_hit_d, + ex4_way_hit_e, + ex4_way_hit_f, + ex4_way_hit_g, + ex4_way_hit_h, + ex4_hit, + dcc_dir_spr_xucr2_rmt, + spr_xucr0_dcdis, + xu_lq_spr_xucr0_wlk, + spr_xucr0_cls, + fgen_ex3_stg_flush, + fgen_ex4_stg_flush, + fgen_ex5_stg_flush, + rel_way_wen_a, + rel_way_wen_b, + rel_way_wen_c, + rel_way_wen_d, + rel_way_wen_e, + rel_way_wen_f, + rel_way_wen_g, + rel_way_wen_h, + rel_way_upd_a, + rel_way_upd_b, + rel_way_upd_c, + rel_way_upd_d, + rel_way_upd_e, + rel_way_upd_f, + rel_way_upd_g, + rel_way_upd_h, + rel_way_clr_a, + rel_way_clr_b, + rel_way_clr_c, + rel_way_clr_d, + rel_way_clr_e, + rel_way_clr_f, + rel_way_clr_g, + rel_way_clr_h, + rel3_dir_wr_val, + rel3_dir_wr_addr, + dir_dcc_rel3_dcarr_upd, + stq4_dcarr_way_en, + dir_dcc_ex5_dir_lru, + lq_xu_spr_xucr0_clo, + vdd, + gnd, + nclk, + sg_0, + func_sl_thold_0_b, + func_sl_force, + func_nsl_thold_0_b, + func_nsl_force, + d_mode_dc, + delay_lclkr_dc, + mpw1_dc_b, + mpw2_dc_b, + scan_in, + scan_out +); + +//------------------------------------------------------------------- +// Generics +//------------------------------------------------------------------- +//parameter EXPAND_TYPE = 2; // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) +//parameter LMQ_ENTRIES = 8; // Number of Loadmiss Queue Entries +//parameter DC_SIZE = 15; // 14 => 16K L1D$, 15 => 32K L1D$ +//parameter CL_SIZE = 6; // 6 => 64B CLINE, 7 => 128B CLINE + +// ACT's +input dcc_dir_ex2_stg_act; +input dcc_dir_ex3_stg_act; +input dcc_dir_ex4_stg_act; +input dcc_dir_ex5_stg_act; +input dcc_dir_stq1_stg_act; +input dcc_dir_stq2_stg_act; +input dcc_dir_stq3_stg_act; + +// Inputs +//Reload path +input lsq_ctl_stq1_val; // Recirculation Operation is Valid +input lsq_ctl_stq2_blk_req; // Block Store due to RV issue +input lsq_ctl_stq1_ci; // Recirculation is Cache-Inhibited +input [64-(`DC_SIZE-3):63-`CL_SIZE] lsq_ctl_stq1_addr; // Reload Congruence Class +input lsq_ctl_rel1_clr_val; // Reload data is valid for 1st beat +input lsq_ctl_rel1_set_val; // Reload data is valid for last beat +input lsq_ctl_rel1_data_val; // Reload data is valid for middle beats +input lsq_ctl_rel2_blk_req; // Block Reload due to RV issue or Back-Invalidate +input lsq_ctl_rel1_lock_set; // Reload For a DCBTLS/DCBTSTLS +input [0:1] lsq_ctl_rel1_classid; // Way locking ClassID +input [0:3] lsq_ctl_rel1_tag; // Reload Tag +input lsq_ctl_rel3_clr_relq; // Reload Complete due to an ECC error +input stq1_lru_upd; // Cache Access does not update the LRU (i.e. dcbt, dcbtst, dcbf, etc) + +// stq3 Recirculation Pipe Command Inputs +input stq3_way_hit_a; // Way A Hit +input stq3_way_hit_b; // Way B Hit +input stq3_way_hit_c; // Way C Hit +input stq3_way_hit_d; // Way D Hit +input stq3_way_hit_e; // Way E Hit +input stq3_way_hit_f; // Way F Hit +input stq3_way_hit_g; // Way G Hit +input stq3_way_hit_h; // Way H Hit +input stq3_hit; // Recirculation Pipe operation hit in L1 D$ + +// Way Valids for Replacement Algorithm +input rel_way_val_a; // Way A Valid for Replacement algorithm +input rel_way_val_b; // Way B Valid for Replacement algorithm +input rel_way_val_c; // Way C Valid for Replacement algorithm +input rel_way_val_d; // Way D Valid for Replacement algorithm +input rel_way_val_e; // Way E Valid for Replacement algorithm +input rel_way_val_f; // Way F Valid for Replacement algorithm +input rel_way_val_g; // Way G Valid for Replacement algorithm +input rel_way_val_h; // Way H Valid for Replacement algorithm + +// Congruence Class Line Lock +input rel_way_lock_a; // Way A Locked Line for Replacement algorithm +input rel_way_lock_b; // Way B Locked Line for Replacement algorithm +input rel_way_lock_c; // Way C Locked Line for Replacement algorithm +input rel_way_lock_d; // Way D Locked Line for Replacement algorithm +input rel_way_lock_e; // Way E Locked Line for Replacement algorithm +input rel_way_lock_f; // Way F Locked Line for Replacement algorithm +input rel_way_lock_g; // Way G Locked Line for Replacement algorithm +input rel_way_lock_h; // Way H Locked Line for Replacement algorithm + +//Execution path +input [64-(`DC_SIZE-3):63-`CL_SIZE] ex2_eff_addr; +input dcc_dir_ex3_cache_acc; // Cache Access is Valid +input dcc_dir_ex3_lru_upd; // Cache Access does not update the LRU (i.e. dcbt and dcbtst) +input derat_dir_ex4_wimge_i; // Cache-Inhibited Request + +// Way Hit for Execution Pipe +input ex4_way_hit_a; // ex3 Way A hit +input ex4_way_hit_b; // ex3 Way B hit +input ex4_way_hit_c; // ex3 Way C hit +input ex4_way_hit_d; // ex3 Way D hit +input ex4_way_hit_e; // ex3 Way E hit +input ex4_way_hit_f; // ex3 Way F hit +input ex4_way_hit_g; // ex3 Way G hit +input ex4_way_hit_h; // ex3 Way H hit +input ex4_hit; // ex4 hit + +// SPR's +input [0:31] dcc_dir_spr_xucr2_rmt; // XUCR2 RMT bits +input spr_xucr0_dcdis; // Data Cache Disable +input xu_lq_spr_xucr0_wlk; // XUCR0 Way locking enabled +input spr_xucr0_cls; // 128Byte Cacheline Mode + +// Flush Signals +input fgen_ex3_stg_flush; // ex3 Flush Stage +input fgen_ex4_stg_flush; // ex4 Flush Stage +input fgen_ex5_stg_flush; // ex5 Flush Stage + +// Outputs +// Way Data Cache Write Enables on a Reload +output rel_way_wen_a; // Reload Way A Write Enable +output rel_way_wen_b; // Reload Way B Write Enable +output rel_way_wen_c; // Reload Way C Write Enable +output rel_way_wen_d; // Reload Way D Write Enable +output rel_way_wen_e; // Reload Way E Write Enable +output rel_way_wen_f; // Reload Way F Write Enable +output rel_way_wen_g; // Reload Way G Write Enable +output rel_way_wen_h; // Reload Way H Write Enable + +// Way Directory Write Enables on a Reload +output rel_way_upd_a; // Reload Way A Write Enable +output rel_way_upd_b; // Reload Way B Write Enable +output rel_way_upd_c; // Reload Way C Write Enable +output rel_way_upd_d; // Reload Way D Write Enable +output rel_way_upd_e; // Reload Way E Write Enable +output rel_way_upd_f; // Reload Way F Write Enable +output rel_way_upd_g; // Reload Way G Write Enable +output rel_way_upd_h; // Reload Way H Write Enable + +// Way Invalidate on a Reload +output rel_way_clr_a; // Reload Way A Write Enable +output rel_way_clr_b; // Reload Way B Write Enable +output rel_way_clr_c; // Reload Way C Write Enable +output rel_way_clr_d; // Reload Way D Write Enable +output rel_way_clr_e; // Reload Way E Write Enable +output rel_way_clr_f; // Reload Way F Write Enable +output rel_way_clr_g; // Reload Way G Write Enable +output rel_way_clr_h; // Reload Way H Write Enable +output rel3_dir_wr_val; // Reload Directory Write Stage is valid +output [64-(`DC_SIZE-3):63-`CL_SIZE] rel3_dir_wr_addr; // Reload Directory Write Address +output dir_dcc_rel3_dcarr_upd; // Reload Data Array Update Valid + +// Way Write Enable on a Reload for Data +output [0:7] stq4_dcarr_way_en; // Reload upper Address + +// Directory LRU in EX5 +output [0:6] dir_dcc_ex5_dir_lru; + +// SPR Status +output lq_xu_spr_xucr0_clo; // Cache Lock instruction caused an overlock + +//pervasive + + +inout vdd; + + +inout gnd; + +(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) + +input [0:`NCLK_WIDTH-1] nclk; +input sg_0; +input func_sl_thold_0_b; +input func_sl_force; +input func_nsl_thold_0_b; +input func_nsl_force; +input d_mode_dc; +input delay_lclkr_dc; +input mpw1_dc_b; +input mpw2_dc_b; + +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + +input scan_in; + +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + +output scan_out; + +//-------------------------- +// components +//-------------------------- + +//-------------------------- +// signals +//-------------------------- +parameter uprCClassBit = 64 - (`DC_SIZE - 3); +parameter lwrCClassBit = 63 - `CL_SIZE; +parameter numCClass = ((2 ** `DC_SIZE)/(2 ** `CL_SIZE))/8; +parameter numCClassWidth = lwrCClassBit-uprCClassBit+1; +parameter numWays = 8; +parameter lruState = numWays - 1; + +wire [0:lruState-1] congr_cl_lru_d[0:numCClass-1]; +wire [0:lruState-1] congr_cl_lru_q[0:numCClass-1]; +wire [0:numCClass-1] congr_cl_lru_wen; +wire [0:numCClass-1] lq_op_cl_lru_wen; +wire [0:numCClass-1] rel_cl_lru_wen; +wire [0:lruState-1] rel_ldst_cl_lru[0:numCClass-1]; +wire [uprCClassBit:lwrCClassBit] ex2_congr_cl; +wire [uprCClassBit:lwrCClassBit] ex3_congr_cl_d; +wire [uprCClassBit:lwrCClassBit] ex3_congr_cl_q; +wire [uprCClassBit:lwrCClassBit] ex4_congr_cl_d; +wire [uprCClassBit:lwrCClassBit] ex4_congr_cl_q; +wire [0:numCClass-1] ex4_congr_cl_1hot; +wire [uprCClassBit:lwrCClassBit] ex5_congr_cl_d; +wire [uprCClassBit:lwrCClassBit] ex5_congr_cl_q; +wire [uprCClassBit:lwrCClassBit] ex6_congr_cl_d; +wire [uprCClassBit:lwrCClassBit] ex6_congr_cl_q; +wire [uprCClassBit:lwrCClassBit] stq1_congr_cl; +wire [uprCClassBit:lwrCClassBit] stq2_congr_cl_d; +wire [uprCClassBit:lwrCClassBit] stq2_congr_cl_q; +wire [0:numCClass-1] stq2_congr_cl_1hot; +wire [uprCClassBit:lwrCClassBit] stq3_congr_cl_d; +wire [uprCClassBit:lwrCClassBit] stq3_congr_cl_q; +wire [uprCClassBit:lwrCClassBit] stq4_congr_cl_d; +wire [uprCClassBit:lwrCClassBit] stq4_congr_cl_q; +wire rel2_clr_stg_val_d; +wire rel2_clr_stg_val_q; +wire rel3_clr_stg_val_d; +wire rel3_clr_stg_val_q; +wire rel2_data_stg_val_d; +wire rel2_data_stg_val_q; +wire rel3_data_stg_val_d; +wire rel3_data_stg_val_q; +wire stq3_val_wen; +wire stq4_val_wen_d; +wire stq4_val_wen_q; +wire [0:lruState-1] lq_congr_cl_lru_d; +wire [0:lruState-1] lq_congr_cl_lru_q; +wire rel_wayA_clr; +wire rel_wayB_clr; +wire rel_wayC_clr; +wire rel_wayD_clr; +wire rel_wayE_clr; +wire rel_wayF_clr; +wire rel_wayG_clr; +wire rel_wayH_clr; +wire stq_wayA_hit; +wire stq_wayB_hit; +wire stq_wayC_hit; +wire stq_wayD_hit; +wire stq_wayE_hit; +wire stq_wayF_hit; +wire stq_wayG_hit; +wire stq_wayH_hit; +wire [0:numWays-1] rel_clr_vec; +wire [0:numWays-1] rel_hit_vec; +wire [0:lruState-1] hit_wayA_upd; +wire [0:lruState-1] hit_wayB_upd; +wire [0:lruState-1] hit_wayC_upd; +wire [0:lruState-1] hit_wayD_upd; +wire [0:lruState-1] hit_wayE_upd; +wire [0:lruState-1] hit_wayF_upd; +wire [0:lruState-1] hit_wayG_upd; +wire [0:lruState-1] hit_wayh_upd; +wire [0:lruState-1] rel_hit_wayA_upd; +wire [0:lruState-1] rel_hit_wayB_upd; +wire [0:lruState-1] rel_hit_wayC_upd; +wire [0:lruState-1] rel_hit_wayD_upd; +wire [0:lruState-1] rel_hit_wayE_upd; +wire [0:lruState-1] rel_hit_wayF_upd; +wire [0:lruState-1] rel_hit_wayG_upd; +wire [0:lruState-1] rel_hit_wayh_upd; +wire [0:lruState-1] ex5_lru_upd; +wire [0:lruState-1] stq3_lru_upd; +wire [0:lruState-1] stq4_lru_upd_d; +wire [0:lruState-1] stq4_lru_upd_q; +wire [0:lruState-1] ex6_lru_upd_d; +wire [0:lruState-1] ex6_lru_upd_q; +wire ex4_c_acc_d; +wire ex4_c_acc_q; +wire ex5_c_acc_d; +wire ex5_c_acc_q; +wire ex6_c_acc_d; +wire ex6_c_acc_q; +wire [0:lruState-1] lq_op_lru; +wire [0:lruState-1] rel_op_lru; +wire [0:numWays-1] ldst_hit_vector_d; +wire [0:numWays-1] ldst_hit_vector_q; +reg [0:lruState-1] p0_arr_lru_rd; +reg [0:lruState-1] p1_arr_lru_rd; +wire [0:lruState-1] rel_congr_cl_lru_d; +wire [0:lruState-1] rel_congr_cl_lru_q; +wire ex4_lru_upd_d; +wire ex4_lru_upd_q; +wire congr_cl_full; +wire [0:numWays-1] empty_way; +wire [0:numWays-1] full_way; +wire [0:numWays-1] rel_hit; +wire [0:3] congr_cl_ex4_byp; +wire [0:3] congr_cl_ex4_sel; +wire ex4_lru_arr_sel; +wire congr_cl_ex4_ex5_cmp_d; +wire congr_cl_ex4_ex5_cmp_q; +wire congr_cl_ex4_ex6_cmp_d; +wire congr_cl_ex4_ex6_cmp_q; +wire congr_cl_ex4_stq3_cmp_d; +wire congr_cl_ex4_stq3_cmp_q; +wire congr_cl_ex4_stq4_cmp_d; +wire congr_cl_ex4_stq4_cmp_q; +wire congr_cl_ex4_ex5_m; +wire congr_cl_ex4_stq3_m; +wire congr_cl_ex4_ex6_m; +wire congr_cl_ex4_stq4_m; +wire congr_cl_stq2_ex5_cmp_d; +wire congr_cl_stq2_ex5_cmp_q; +wire congr_cl_stq2_ex6_cmp_d; +wire congr_cl_stq2_ex6_cmp_q; +wire congr_cl_stq2_stq3_cmp_d; +wire congr_cl_stq2_stq3_cmp_q; +wire congr_cl_stq2_stq4_cmp_d; +wire congr_cl_stq2_stq4_cmp_q; +wire congr_cl_stq2_ex5_m; +wire congr_cl_stq2_ex6_m; +wire congr_cl_stq2_stq3_m; +wire congr_cl_stq2_stq4_m; +wire [0:3] congr_cl_stq2_byp; +wire [0:3] congr_cl_stq2_sel; +wire stq2_lru_arr_sel; +reg [0:numWays-1] rel_way_qsel_d; +wire [0:numWays-1] rel_way_qsel_q; +reg [0:numWays-1] rel_way_mid_qsel; +wire rel_val_mid_qsel; +wire [0:3] rel2_rel_tag_d; +wire [0:3] rel2_rel_tag_q; +wire [0:3] rel3_rel_tag_d; +wire [0:3] rel3_rel_tag_q; +wire rel2_set_stg_val_d; +wire rel2_set_stg_val_q; +wire rel3_set_stg_val_d; +wire rel3_set_stg_val_q; +wire rel_wayA_mid; +wire rel_wayB_mid; +wire rel_wayC_mid; +wire rel_wayD_mid; +wire rel_wayE_mid; +wire rel_wayF_mid; +wire rel_wayG_mid; +wire rel_wayH_mid; +wire rel_wayA_set; +wire rel_wayB_set; +wire rel_wayC_set; +wire rel_wayD_set; +wire rel_wayE_set; +wire rel_wayF_set; +wire rel_wayG_set; +wire rel_wayH_set; +wire [0:numWays-1] rel4_dir_way_upd_d; +wire [0:numWays-1] rel4_dir_way_upd_q; +wire [0:numWays-1] rel3_wlock_d; +wire [0:numWays-1] rel3_wlock_q; +wire [0:numWays-1] rel_lock_line; +wire [0:lruState-1] stq3_op_lru; +wire [0:lruState-1] rel_ovrd_lru; +wire [0:1] rel_ovrd_wayAB; +wire [0:1] rel_ovrd_wayCD; +wire [0:1] rel_ovrd_wayEF; +wire [0:1] rel_ovrd_wayGH; +wire [0:1] rel_ovrd_wayABCD; +wire [0:1] rel_ovrd_wayEFGH; +wire [0:1] rel_ovrd_wayABCDEFGH; +wire ovr_lock_det; +wire ovr_lock_det_wlkon; +wire ovr_lock_det_wlkoff; +wire wayA_not_empty; +wire wayB_not_empty; +wire wayC_not_empty; +wire wayD_not_empty; +wire wayE_not_empty; +wire wayF_not_empty; +wire wayG_not_empty; +wire wayH_not_empty; +wire [0:`LMQ_ENTRIES-1] reld_q_chk_val; +wire [0:numWays-1] reld_q_chk_way[0:`LMQ_ENTRIES-1]; +wire [0:`LMQ_ENTRIES-1] reld_q_way_m; +wire [0:`LMQ_ENTRIES-1] reld_q_set; +wire [0:`LMQ_ENTRIES-1] reld_q_inval; +wire [0:1] reld_q_val_sel[0:`LMQ_ENTRIES-1]; +wire [uprCClassBit:lwrCClassBit] reld_q_congr_cl_d[0:`LMQ_ENTRIES-1]; +wire [uprCClassBit:lwrCClassBit] reld_q_congr_cl_q[0:`LMQ_ENTRIES-1]; +wire [0:numWays-1] reld_q_way_d[0:`LMQ_ENTRIES-1]; +wire [0:numWays-1] reld_q_way_q[0:`LMQ_ENTRIES-1]; +wire [0:`LMQ_ENTRIES-1] reld_q_val_d; +wire [0:`LMQ_ENTRIES-1] reld_q_val_q; +wire [0:`LMQ_ENTRIES-1] reld_q_lock_d; +wire [0:`LMQ_ENTRIES-1] reld_q_lock_q; +wire [0:numWays-1] reld_q_way_lock[0:`LMQ_ENTRIES-1]; +wire [0:`LMQ_ENTRIES-1] rel_m_q; +wire [0:`LMQ_ENTRIES-1] reld_match; +wire [0:`LMQ_ENTRIES-1] reld_q_sel_d; +wire [0:`LMQ_ENTRIES-1] reld_q_sel_q; +wire [0:`LMQ_ENTRIES-1] reld_q_set_val; +wire [0:`LMQ_ENTRIES-1] reld_q_mid_val; +wire rel_val_qsel_d; +wire rel_val_qsel_q; +wire [0:numWays-1] rel2_wlock_rmt; +wire [0:31] rel2_xucr2_rmt_d; +wire [0:31] rel2_xucr2_rmt_q; +wire spr_xucr0_wlk_d; +wire spr_xucr0_wlk_q; +wire [0:1] stq2_class_id_d; +wire [0:1] stq2_class_id_q; +wire rel_m_q_upd; +wire [0:numWays-1] rel_m_q_upd_way; +wire [0:numWays-1] rel_m_q_upd_lock_way; +reg [0:numWays-1] rel_m_q_way_val; +reg [0:numWays-1] rel_m_q_lock_way; +wire [0:numWays-1] rel3_m_q_way_d; +wire [0:numWays-1] rel3_m_q_way_q; +wire rel2_lock_en_d; +wire rel2_lock_en_q; +wire rel3_lock_en_d; +wire rel3_lock_en_q; +wire xucr0_clo_d; +wire xucr0_clo_q; +wire [0:numWays-1] rel_way_dwen; +wire [0:numWays-1] stq4_dcarr_way_en_d; +wire [0:numWays-1] stq4_dcarr_way_en_q; +wire stq3_new_lru_sel; +wire [0:lruState-1] rel_hit_lru_upd; +wire [0:lruState-1] ldst_hit_lru_upd; +wire stq2_val_d; +wire stq2_val_q; +wire stq3_val_d; +wire stq3_val_q; +wire congr_cl_act_d; +wire congr_cl_act_q; + +//-------------------------- +// constants +//-------------------------- +parameter congr_cl_lru_offset = 0; +parameter rel2_xucr2_rmt_offset = congr_cl_lru_offset + numCClass*lruState; +parameter spr_xucr0_wlk_offset = rel2_xucr2_rmt_offset + 32; +parameter lq_congr_cl_lru_offset = spr_xucr0_wlk_offset + 1; +parameter ldst_hit_vector_offset = lq_congr_cl_lru_offset + lruState; +parameter rel_congr_cl_lru_offset = ldst_hit_vector_offset + numWays; +parameter ex3_congr_cl_offset = rel_congr_cl_lru_offset + lruState; +parameter ex4_congr_cl_offset = ex3_congr_cl_offset + numCClassWidth; +parameter ex5_congr_cl_offset = ex4_congr_cl_offset + numCClassWidth; +parameter ex6_congr_cl_offset = ex5_congr_cl_offset + numCClassWidth; +parameter stq2_congr_cl_offset = ex6_congr_cl_offset + numCClassWidth; +parameter stq3_congr_cl_offset = stq2_congr_cl_offset + numCClassWidth; +parameter stq4_congr_cl_offset = stq3_congr_cl_offset + numCClassWidth; +parameter congr_cl_stq2_ex5_cmp_offset = stq4_congr_cl_offset + numCClassWidth; +parameter congr_cl_stq2_ex6_cmp_offset = congr_cl_stq2_ex5_cmp_offset + 1; +parameter congr_cl_stq2_stq3_cmp_offset = congr_cl_stq2_ex6_cmp_offset + 1; +parameter congr_cl_stq2_stq4_cmp_offset = congr_cl_stq2_stq3_cmp_offset + 1; +parameter congr_cl_ex4_ex5_cmp_offset = congr_cl_stq2_stq4_cmp_offset + 1; +parameter congr_cl_ex4_ex6_cmp_offset = congr_cl_ex4_ex5_cmp_offset + 1; +parameter congr_cl_ex4_stq3_cmp_offset = congr_cl_ex4_ex6_cmp_offset + 1; +parameter congr_cl_ex4_stq4_cmp_offset = congr_cl_ex4_stq3_cmp_offset + 1; +parameter ex6_lru_upd_offset = congr_cl_ex4_stq4_cmp_offset + 1; +parameter rel2_clr_stg_val_offset = ex6_lru_upd_offset + lruState; +parameter rel3_clr_stg_val_offset = rel2_clr_stg_val_offset + 1; +parameter rel2_data_stg_val_offset = rel3_clr_stg_val_offset + 1; +parameter rel3_data_stg_val_offset = rel2_data_stg_val_offset + 1; +parameter ex4_c_acc_offset = rel3_data_stg_val_offset + 1; +parameter ex5_c_acc_offset = ex4_c_acc_offset + 1; +parameter ex6_c_acc_offset = ex5_c_acc_offset + 1; +parameter stq4_val_wen_offset = ex6_c_acc_offset + 1; +parameter stq4_lru_upd_offset = stq4_val_wen_offset + 1; +parameter rel2_rel_tag_offset = stq4_lru_upd_offset + lruState; +parameter rel3_rel_tag_offset = rel2_rel_tag_offset + 4; +parameter rel2_set_stg_val_offset = rel3_rel_tag_offset + 4; +parameter rel3_set_stg_val_offset = rel2_set_stg_val_offset + 1; +parameter rel3_wlock_offset = rel3_set_stg_val_offset + 1; +parameter reld_q_sel_offset = rel3_wlock_offset + numWays; +parameter rel_way_qsel_offset = reld_q_sel_offset + `LMQ_ENTRIES; +parameter rel_val_qsel_offset = rel_way_qsel_offset + numWays; +parameter rel4_dir_way_upd_offset = rel_val_qsel_offset + 1; +parameter reld_q_congr_cl_offset = rel4_dir_way_upd_offset + numWays; +parameter reld_q_way_offset = reld_q_congr_cl_offset + `LMQ_ENTRIES*numCClassWidth; +parameter reld_q_val_offset = reld_q_way_offset + `LMQ_ENTRIES *numWays; +parameter reld_q_lock_offset = reld_q_val_offset + `LMQ_ENTRIES; +parameter rel3_m_q_way_offset = reld_q_lock_offset + `LMQ_ENTRIES; +parameter ex4_lru_upd_offset = rel3_m_q_way_offset + numWays; +parameter rel2_lock_en_offset = ex4_lru_upd_offset + 1; +parameter rel3_lock_en_offset = rel2_lock_en_offset + 1; +parameter xucr0_clo_offset = rel3_lock_en_offset + 1; +parameter stq4_dcarr_way_en_offset = xucr0_clo_offset + 1; +parameter stq2_class_id_offset = stq4_dcarr_way_en_offset + numWays; +parameter stq2_val_offset = stq2_class_id_offset + 2; +parameter stq3_val_offset = stq2_val_offset + 1; +parameter congr_cl_act_offset = stq3_val_offset + 1; +parameter scan_right = congr_cl_act_offset + 1 - 1; + +wire tiup; +wire [0:scan_right] siv; +wire [0:scan_right] sov; + + +(* analysis_not_referenced="true" *) + +wire unused; + +// #################################################### +// Inputs +// #################################################### + +assign rel2_xucr2_rmt_d = dcc_dir_spr_xucr2_rmt; +assign spr_xucr0_wlk_d = xu_lq_spr_xucr0_wlk; +assign tiup = 1'b1; +assign unused = stq3_op_lru[0]; + +// #################################################### +// Reload Pipe Control +// Port1 => Reload or Recirculation +// #################################################### + +// Reload/Recirc Pipe Staging +assign stq2_val_d = lsq_ctl_stq1_val & stq1_lru_upd & (~(spr_xucr0_dcdis | lsq_ctl_stq1_ci)); +assign stq3_val_d = stq2_val_q & (~lsq_ctl_stq2_blk_req); +assign rel2_clr_stg_val_d = lsq_ctl_rel1_clr_val & (~spr_xucr0_dcdis); +assign rel3_clr_stg_val_d = rel2_clr_stg_val_q & (~lsq_ctl_rel2_blk_req); +assign rel2_data_stg_val_d = lsq_ctl_rel1_data_val & (~spr_xucr0_dcdis); +assign rel3_data_stg_val_d = rel2_data_stg_val_q; +assign rel2_set_stg_val_d = lsq_ctl_rel1_set_val & (~spr_xucr0_dcdis); +assign rel3_set_stg_val_d = rel2_set_stg_val_q & (~lsq_ctl_rel2_blk_req); +assign rel2_rel_tag_d = lsq_ctl_rel1_tag; +assign rel3_rel_tag_d = rel2_rel_tag_q; +assign stq2_class_id_d = lsq_ctl_rel1_classid; +assign rel2_lock_en_d = lsq_ctl_rel1_lock_set & lsq_ctl_rel1_clr_val; +assign rel3_lock_en_d = rel2_lock_en_q & (~lsq_ctl_rel2_blk_req); +assign stq3_val_wen = (rel3_clr_stg_val_q & (~ovr_lock_det)) | (stq3_val_q & stq3_hit); +assign stq4_val_wen_d = stq3_val_wen; + +generate + if (`CL_SIZE == 6) begin : cl64size + assign stq1_congr_cl[uprCClassBit:lwrCClassBit - 1] = lsq_ctl_stq1_addr[uprCClassBit:lwrCClassBit - 1]; + assign stq1_congr_cl[lwrCClassBit] = lsq_ctl_stq1_addr[lwrCClassBit] | spr_xucr0_cls; + end +endgenerate + +generate + if (`CL_SIZE == 7) begin : cl128size + assign stq1_congr_cl = lsq_ctl_stq1_addr; + end +endgenerate + +assign stq2_congr_cl_d = stq1_congr_cl; +assign stq3_congr_cl_d = stq2_congr_cl_q; +assign stq4_congr_cl_d = stq3_congr_cl_q; + +// #################################################### +// Reload Pipe Directory Read +// #################################################### +// 1-hot Congruence Class Select +generate begin : stpCClass + genvar cclass; + for (cclass=0; cclass Bypass out of reload Queue +// Need to merge outstanding reloads to same congruence class + +// Select which RMT table to use +assign rel2_wlock_rmt = (stq2_class_id_q == 2'b11) ? (~rel2_xucr2_rmt_q[0:7]) : + (stq2_class_id_q == 2'b10) ? (~rel2_xucr2_rmt_q[8:15]) : + (stq2_class_id_q == 2'b01) ? (~rel2_xucr2_rmt_q[16:23]) : + (~rel2_xucr2_rmt_q[24:31]); + +// Reload updating a way +assign rel_m_q_upd = (stq2_congr_cl_q == stq3_congr_cl_q) & rel3_clr_stg_val_q; +assign rel_m_q_upd_way = rel_clr_vec & {numWays{rel_m_q_upd}}; +assign rel_m_q_upd_lock_way = rel_clr_vec & {numWays{(rel_m_q_upd & rel3_lock_en_q)}}; + +// Reload Matching Reload Queue Entry +generate begin : relqByp + genvar lmq; + for (lmq=0; lmq<`LMQ_ENTRIES; lmq=lmq+1) begin : relqByp + assign rel_m_q[lmq] = (stq2_congr_cl_q == reld_q_congr_cl_q[lmq]) & reld_q_val_q[lmq]; + assign reld_q_way_lock[lmq] = reld_q_way_q[lmq] & {numWays{reld_q_lock_q[lmq]}}; + end + end +endgenerate + +// Reload Matching Reload Queue State Muxing + +always @(*) begin: relqBypState + reg [0:numWays-1] qVal; + reg [0:numWays-1] qLock; + + //(* analysis_not_referenced="true" *) + + integer lmq; + qVal = {numWays{1'b0}}; + qLock = {numWays{1'b0}}; + for (lmq=0; lmq<`LMQ_ENTRIES; lmq=lmq+1) begin + qVal = (reld_q_way_q[lmq] & {numWays{rel_m_q[lmq]}}) | qVal; + qLock = (reld_q_way_lock[lmq] & {numWays{rel_m_q[lmq]}}) | qLock; + end + rel_m_q_way_val = qVal; + rel_m_q_lock_way = qLock; +end + +// Reload Queue Ways in Use for congruence class +assign rel3_m_q_way_d = rel_m_q_way_val | rel_m_q_upd_way; + +// Reload Queue Locked Ways +assign rel3_wlock_d = rel_m_q_lock_way | rel_m_q_upd_lock_way | rel2_wlock_rmt; + +// #################################################### +// Reload/Recirc Pipe Bypass +// #################################################### +// STQ2 Stage --> Bypass Logic +assign congr_cl_stq2_stq3_cmp_d = (stq1_congr_cl == stq2_congr_cl_q); +assign congr_cl_stq2_stq4_cmp_d = (stq1_congr_cl == stq3_congr_cl_q); +assign congr_cl_stq2_ex5_cmp_d = (stq1_congr_cl == ex4_congr_cl_q); +assign congr_cl_stq2_ex6_cmp_d = (stq1_congr_cl == ex5_congr_cl_q); + +assign congr_cl_stq2_stq3_m = congr_cl_stq2_stq3_cmp_q & stq3_val_wen; +assign congr_cl_stq2_stq4_m = congr_cl_stq2_stq4_cmp_q & stq4_val_wen_q; +assign congr_cl_stq2_ex5_m = congr_cl_stq2_ex5_cmp_q & ex5_c_acc_q; +assign congr_cl_stq2_ex6_m = congr_cl_stq2_ex6_cmp_q & ex6_c_acc_q; + +// Bypass STQ2 select +assign congr_cl_stq2_byp[0] = congr_cl_stq2_ex5_m; // 1st priority +assign congr_cl_stq2_byp[1] = congr_cl_stq2_stq3_m; // 2nd priority <-- slowest of all of them +assign congr_cl_stq2_byp[2] = congr_cl_stq2_ex6_m; // 3rd priority +assign congr_cl_stq2_byp[3] = congr_cl_stq2_stq4_m; // 4th priority + +assign congr_cl_stq2_sel[0] = congr_cl_stq2_byp[0]; +assign congr_cl_stq2_sel[1] = congr_cl_stq2_byp[1] & (~congr_cl_stq2_byp[0]); +assign congr_cl_stq2_sel[2] = congr_cl_stq2_byp[2] & ~(|congr_cl_stq2_byp[0:1]); +assign congr_cl_stq2_sel[3] = congr_cl_stq2_byp[3] & ~(|congr_cl_stq2_byp[0:2]); + +assign stq2_lru_arr_sel = ~(|congr_cl_stq2_byp); + +assign rel_congr_cl_lru_d = (ex5_lru_upd & {lruState{congr_cl_stq2_sel[0]}}) | + (stq3_lru_upd & {lruState{congr_cl_stq2_sel[1]}}) | + (ex6_lru_upd_q & {lruState{congr_cl_stq2_sel[2]}}) | + (stq4_lru_upd_q & {lruState{congr_cl_stq2_sel[3]}}) | + (p1_arr_lru_rd & {lruState{stq2_lru_arr_sel}}); + +// Bypassed LRU for Reloads +assign rel_op_lru = rel_congr_cl_lru_q; + +// #################################################### +// Reload Path +// #################################################### + +// Determine which way is locked +assign rel_lock_line[0] = rel_way_lock_a | rel3_wlock_q[0]; +assign rel_lock_line[1] = rel_way_lock_b | rel3_wlock_q[1]; +assign rel_lock_line[2] = rel_way_lock_c | rel3_wlock_q[2]; +assign rel_lock_line[3] = rel_way_lock_d | rel3_wlock_q[3]; +assign rel_lock_line[4] = rel_way_lock_e | rel3_wlock_q[4]; +assign rel_lock_line[5] = rel_way_lock_f | rel3_wlock_q[5]; +assign rel_lock_line[6] = rel_way_lock_g | rel3_wlock_q[6]; +assign rel_lock_line[7] = rel_way_lock_h | rel3_wlock_q[7]; + +// Override LRU, removing locked ways from replacement +// Overlocking Detected, do not update Cache +assign ovr_lock_det = rel_lock_line[0] & rel_lock_line[1] & rel_lock_line[2] & rel_lock_line[3] & + rel_lock_line[4] & rel_lock_line[5] & rel_lock_line[6] & rel_lock_line[7]; + +assign ovr_lock_det_wlkon = ovr_lock_det & rel3_clr_stg_val_q; +assign ovr_lock_det_wlkoff = ovr_lock_det & rel3_lock_en_q & rel3_clr_stg_val_q; + +assign xucr0_clo_d = spr_xucr0_wlk_q ? ovr_lock_det_wlkon : ovr_lock_det_wlkoff; + +// LRU(0) +assign rel_ovrd_wayABCDEFGH = {(rel_lock_line[0] & rel_lock_line[1] & rel_lock_line[2] & rel_lock_line[3]), + (rel_lock_line[4] & rel_lock_line[5] & rel_lock_line[6] & rel_lock_line[7])}; +assign rel_ovrd_lru[0] = (rel_op_lru[0] & (~rel_ovrd_wayABCDEFGH[1])) | rel_ovrd_wayABCDEFGH[0]; + +// LRU(1) +assign rel_ovrd_wayABCD = {(rel_lock_line[0] & rel_lock_line[1]), (rel_lock_line[2] & rel_lock_line[3])}; +assign rel_ovrd_lru[1] = (rel_op_lru[1] & (~rel_ovrd_wayABCD[1])) | rel_ovrd_wayABCD[0]; + +// LRU(2) +assign rel_ovrd_wayEFGH = {(rel_lock_line[4] & rel_lock_line[5]), (rel_lock_line[6] & rel_lock_line[7])}; +assign rel_ovrd_lru[2] = (rel_op_lru[2] & (~rel_ovrd_wayEFGH[1])) | rel_ovrd_wayEFGH[0]; + +// LRU(3) +assign rel_ovrd_wayAB = rel_lock_line[0:1]; +assign rel_ovrd_lru[3] = (rel_op_lru[3] & (~rel_ovrd_wayAB[1])) | rel_ovrd_wayAB[0]; + +// LRU(4) +assign rel_ovrd_wayCD = rel_lock_line[2:3]; +assign rel_ovrd_lru[4] = (rel_op_lru[4] & (~rel_ovrd_wayCD[1])) | rel_ovrd_wayCD[0]; + +// LRU(5) +assign rel_ovrd_wayEF = rel_lock_line[4:5]; +assign rel_ovrd_lru[5] = (rel_op_lru[5] & (~rel_ovrd_wayEF[1])) | rel_ovrd_wayEF[0]; + +// LRU(6) +assign rel_ovrd_wayGH = rel_lock_line[6:7]; +assign rel_ovrd_lru[6] = (rel_op_lru[6] & (~rel_ovrd_wayGH[1])) | rel_ovrd_wayGH[0]; + +// Locking Enabled +// Not Empty way is a valid Way or locked way or reload way in queue +assign wayA_not_empty = rel_way_val_a | rel3_wlock_q[0] | rel3_m_q_way_q[0]; +assign wayB_not_empty = rel_way_val_b | rel3_wlock_q[1] | rel3_m_q_way_q[1]; +assign wayC_not_empty = rel_way_val_c | rel3_wlock_q[2] | rel3_m_q_way_q[2]; +assign wayD_not_empty = rel_way_val_d | rel3_wlock_q[3] | rel3_m_q_way_q[3]; +assign wayE_not_empty = rel_way_val_e | rel3_wlock_q[4] | rel3_m_q_way_q[4]; +assign wayF_not_empty = rel_way_val_f | rel3_wlock_q[5] | rel3_m_q_way_q[5]; +assign wayG_not_empty = rel_way_val_g | rel3_wlock_q[6] | rel3_m_q_way_q[6]; +assign wayH_not_empty = rel_way_val_h | rel3_wlock_q[7] | rel3_m_q_way_q[7]; + +// Pseudo LRU needs to be used if all ways contain valid data on a reload or its a recirculation +assign congr_cl_full = (wayA_not_empty & wayB_not_empty & wayC_not_empty & wayD_not_empty & + wayE_not_empty & wayF_not_empty & wayG_not_empty & wayH_not_empty) | stq3_val_q; + +// Need to select which non-valid way needs updating, Using leftmost empty Way +assign empty_way[0] = ~wayA_not_empty; +assign empty_way[1] = (wayA_not_empty & ~wayB_not_empty); +assign empty_way[2] = (wayA_not_empty & wayB_not_empty & ~wayC_not_empty); +assign empty_way[3] = (wayA_not_empty & wayB_not_empty & wayC_not_empty & ~wayD_not_empty); +assign empty_way[4] = (wayA_not_empty & wayB_not_empty & wayC_not_empty & wayD_not_empty & ~wayE_not_empty); +assign empty_way[5] = (wayA_not_empty & wayB_not_empty & wayC_not_empty & wayD_not_empty & wayE_not_empty & ~wayF_not_empty); +assign empty_way[6] = (wayA_not_empty & wayB_not_empty & wayC_not_empty & wayD_not_empty & wayE_not_empty & wayF_not_empty & ~wayG_not_empty); +assign empty_way[7] = (wayA_not_empty & wayB_not_empty & wayC_not_empty & wayD_not_empty & wayE_not_empty & wayF_not_empty & wayG_not_empty); + +// Locking Enabled +// Using LRU to determine which way will be updated +assign full_way[0] = ~rel_ovrd_lru[0] & ~rel_ovrd_lru[1] & ~rel_ovrd_lru[3]; +assign full_way[1] = ~rel_ovrd_lru[0] & ~rel_ovrd_lru[1] & rel_ovrd_lru[3]; +assign full_way[2] = ~rel_ovrd_lru[0] & rel_ovrd_lru[1] & ~rel_ovrd_lru[4]; +assign full_way[3] = ~rel_ovrd_lru[0] & rel_ovrd_lru[1] & rel_ovrd_lru[4]; +assign full_way[4] = rel_ovrd_lru[0] & ~rel_ovrd_lru[2] & ~rel_ovrd_lru[5]; +assign full_way[5] = rel_ovrd_lru[0] & ~rel_ovrd_lru[2] & rel_ovrd_lru[5]; +assign full_way[6] = rel_ovrd_lru[0] & rel_ovrd_lru[2] & ~rel_ovrd_lru[6]; +assign full_way[7] = rel_ovrd_lru[0] & rel_ovrd_lru[2] & rel_ovrd_lru[6]; + +// Selecting between using LRU or Fill in the Empty Ways +assign rel_hit = (empty_way & {numWays{~congr_cl_full}}) | (full_way & {numWays{congr_cl_full}}); + +// Way that will be updating is determined by the current LRU +// Dont want to update the directory or the D$ if we have all ways locked in the same congruence class +assign rel_wayA_clr = rel_hit[0] & rel3_clr_stg_val_q & ~ovr_lock_det; +assign rel_wayB_clr = rel_hit[1] & rel3_clr_stg_val_q & ~ovr_lock_det; +assign rel_wayC_clr = rel_hit[2] & rel3_clr_stg_val_q & ~ovr_lock_det; +assign rel_wayD_clr = rel_hit[3] & rel3_clr_stg_val_q & ~ovr_lock_det; +assign rel_wayE_clr = rel_hit[4] & rel3_clr_stg_val_q & ~ovr_lock_det; +assign rel_wayF_clr = rel_hit[5] & rel3_clr_stg_val_q & ~ovr_lock_det; +assign rel_wayG_clr = rel_hit[6] & rel3_clr_stg_val_q & ~ovr_lock_det; +assign rel_wayH_clr = rel_hit[7] & rel3_clr_stg_val_q & ~ovr_lock_det; + +assign rel_clr_vec = {rel_wayA_clr, rel_wayB_clr, rel_wayC_clr, rel_wayD_clr, + rel_wayE_clr, rel_wayF_clr, rel_wayG_clr, rel_wayH_clr}; + +assign stq_wayA_hit = stq3_way_hit_a & stq3_val_q; +assign stq_wayB_hit = stq3_way_hit_b & stq3_val_q; +assign stq_wayC_hit = stq3_way_hit_c & stq3_val_q; +assign stq_wayD_hit = stq3_way_hit_d & stq3_val_q; +assign stq_wayE_hit = stq3_way_hit_e & stq3_val_q; +assign stq_wayF_hit = stq3_way_hit_f & stq3_val_q; +assign stq_wayG_hit = stq3_way_hit_g & stq3_val_q; +assign stq_wayH_hit = stq3_way_hit_h & stq3_val_q; + +assign rel_hit_vec = {(rel_wayA_clr | stq_wayA_hit), (rel_wayB_clr | stq_wayB_hit), + (rel_wayC_clr | stq_wayC_hit), (rel_wayD_clr | stq_wayD_hit), + (rel_wayE_clr | stq_wayE_hit), (rel_wayF_clr | stq_wayF_hit), + (rel_wayG_clr | stq_wayG_hit), (rel_wayH_clr | stq_wayH_hit)}; + +// #################################################### +// LRU update calculation due to a Reload/Recirculation +// #################################################### +// Select between Reload or Recirculation Operation +assign stq3_op_lru = ~rel3_clr_stg_val_q ? rel_op_lru : rel_ovrd_lru; + +// Updating the LRU using the Way that is being reloaded or the Way hit +assign rel_hit_wayA_upd = {2'b11, stq3_op_lru[2], 1'b1, stq3_op_lru[4:6]}; +assign rel_hit_wayB_upd = {2'b11, stq3_op_lru[2], 1'b0, stq3_op_lru[4:6]}; +assign rel_hit_wayC_upd = {2'b10, stq3_op_lru[2:3], 1'b1, stq3_op_lru[5:6]}; +assign rel_hit_wayD_upd = {2'b10, stq3_op_lru[2:3], 1'b0, stq3_op_lru[5:6]}; +assign rel_hit_wayE_upd = {1'b0, stq3_op_lru[1], 1'b1, stq3_op_lru[3:4], 1'b1, stq3_op_lru[6]}; +assign rel_hit_wayF_upd = {1'b0, stq3_op_lru[1], 1'b1, stq3_op_lru[3:4], 1'b0, stq3_op_lru[6]}; +assign rel_hit_wayG_upd = {1'b0, stq3_op_lru[1], 1'b0, stq3_op_lru[3:5], 1'b1}; +assign rel_hit_wayh_upd = {1'b0, stq3_op_lru[1], 1'b0, stq3_op_lru[3:5], 1'b0}; + +// #################################################### +// Selecting which calculated LRU to update with +// #################################################### +// Selecting Way Hit Updated LRU +assign rel_hit_lru_upd = (rel_hit_wayA_upd & {lruState{rel_hit_vec[0]}}) | (rel_hit_wayB_upd & {lruState{rel_hit_vec[1]}}) | + (rel_hit_wayC_upd & {lruState{rel_hit_vec[2]}}) | (rel_hit_wayD_upd & {lruState{rel_hit_vec[3]}}) | + (rel_hit_wayE_upd & {lruState{rel_hit_vec[4]}}) | (rel_hit_wayF_upd & {lruState{rel_hit_vec[5]}}) | + (rel_hit_wayG_upd & {lruState{rel_hit_vec[6]}}) | (rel_hit_wayh_upd & {lruState{rel_hit_vec[7]}}); + +// LRU update is valid +assign stq3_new_lru_sel = |(rel_clr_vec) | stq3_hit; +assign stq3_lru_upd = ~stq3_new_lru_sel ? rel_op_lru : rel_hit_lru_upd; +assign stq4_lru_upd_d = stq3_lru_upd; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Small Reload Way Enable Queue to Handle Beats with Gaps +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +generate begin : reldQ + genvar lmq; + for (lmq=0; lmq<`LMQ_ENTRIES; lmq=lmq+1) begin : reldQ + wire [0:3] lmqDummy = lmq; + + // Write Enable Logic for Reload Queue + assign reld_q_chk_val[lmq] = (reld_q_congr_cl_q[lmq] == stq3_congr_cl_q) & reld_q_val_q[lmq] & rel3_clr_stg_val_q & (~ovr_lock_det); + assign reld_q_chk_way[lmq] = reld_q_way_q[lmq] & {numWays{reld_q_chk_val[lmq]}}; + assign reld_q_way_m[lmq] = |(reld_q_chk_way[lmq] & rel_hit); + assign reld_match[lmq] = reld_q_way_m[lmq]; + assign reld_q_set[lmq] = rel3_clr_stg_val_q & (rel3_rel_tag_q == lmqDummy); + assign reld_q_inval[lmq] = ((rel3_set_stg_val_q | lsq_ctl_rel3_clr_relq) & reld_q_sel_q[lmq]) | reld_match[lmq]; + assign reld_q_val_sel[lmq] = {reld_q_set[lmq], reld_q_inval[lmq]}; + + // Congruence Class + assign reld_q_congr_cl_d[lmq] = reld_q_set[lmq] ? stq3_congr_cl_q : reld_q_congr_cl_q[lmq]; + + // Reload Way + assign reld_q_way_d[lmq] = reld_q_set[lmq] ? rel_hit_vec : reld_q_way_q[lmq]; + + // Valid + assign reld_q_val_d[lmq] = (reld_q_val_sel[lmq] == 2'b10) ? 1'b1 : + (reld_q_val_sel[lmq] == 2'b00) ? reld_q_val_q[lmq] : + 1'b0; + + // Lock Bit + assign reld_q_lock_d[lmq] = (reld_q_val_sel[lmq] == 2'b10) ? rel3_lock_en_q : + (reld_q_val_sel[lmq] == 2'b00) ? reld_q_lock_q[lmq] : + 1'b0; + + // Reload Queue Select + assign reld_q_sel_d[lmq] = (rel2_rel_tag_q == lmqDummy); + + // Reload Queue Set Stage Valid + assign reld_q_set_val[lmq] = reld_q_val_q[lmq] & reld_q_sel_d[lmq] & ~reld_match[lmq]; + + // Reload Queue Mid Stage Valid + assign reld_q_mid_val[lmq] = reld_q_val_q[lmq] & reld_q_sel_q[lmq]; + end + end +endgenerate + +// Reload Queue Way Muxing +always @(*) begin: reldQSel + reg [0:numWays-1] qWay; + reg [0:numWays-1] qWayM; + + //(* analysis_not_referenced="true" *) + + integer lmq; + qWay = {numWays{1'b0}}; + qWayM = {numWays{1'b0}}; + for (lmq=0; lmq<`LMQ_ENTRIES; lmq=lmq+1) begin + qWay = (reld_q_way_q[lmq] & {numWays{reld_q_sel_d[lmq]}}) | qWay; + qWayM = (reld_q_way_q[lmq] & {numWays{reld_q_sel_q[lmq]}}) | qWayM; + end + // Select Way for Set Data Beat + rel_way_qsel_d = qWay; + + // Select Way for Middle Data Beats + rel_way_mid_qsel = qWayM; +end + +// Select Valid for Set Data Beat +assign rel_val_qsel_d = |(reld_q_set_val); + +// Select Valid for Middle Data Beats +assign rel_val_mid_qsel = |(reld_q_mid_val); + +// Reload Way Middle Data Beats +assign rel_wayA_mid = rel_way_mid_qsel[0] & rel3_data_stg_val_q & rel_val_mid_qsel; +assign rel_wayB_mid = rel_way_mid_qsel[1] & rel3_data_stg_val_q & rel_val_mid_qsel; +assign rel_wayC_mid = rel_way_mid_qsel[2] & rel3_data_stg_val_q & rel_val_mid_qsel; +assign rel_wayD_mid = rel_way_mid_qsel[3] & rel3_data_stg_val_q & rel_val_mid_qsel; +assign rel_wayE_mid = rel_way_mid_qsel[4] & rel3_data_stg_val_q & rel_val_mid_qsel; +assign rel_wayF_mid = rel_way_mid_qsel[5] & rel3_data_stg_val_q & rel_val_mid_qsel; +assign rel_wayG_mid = rel_way_mid_qsel[6] & rel3_data_stg_val_q & rel_val_mid_qsel; +assign rel_wayH_mid = rel_way_mid_qsel[7] & rel3_data_stg_val_q & rel_val_mid_qsel; + +// Reload Way Set +assign rel_wayA_set = rel_way_qsel_q[0] & rel3_set_stg_val_q & rel_val_qsel_q; +assign rel_wayB_set = rel_way_qsel_q[1] & rel3_set_stg_val_q & rel_val_qsel_q; +assign rel_wayC_set = rel_way_qsel_q[2] & rel3_set_stg_val_q & rel_val_qsel_q; +assign rel_wayD_set = rel_way_qsel_q[3] & rel3_set_stg_val_q & rel_val_qsel_q; +assign rel_wayE_set = rel_way_qsel_q[4] & rel3_set_stg_val_q & rel_val_qsel_q; +assign rel_wayF_set = rel_way_qsel_q[5] & rel3_set_stg_val_q & rel_val_qsel_q; +assign rel_wayG_set = rel_way_qsel_q[6] & rel3_set_stg_val_q & rel_val_qsel_q; +assign rel_wayH_set = rel_way_qsel_q[7] & rel3_set_stg_val_q & rel_val_qsel_q; + +assign rel4_dir_way_upd_d = {rel_wayA_set, rel_wayB_set, rel_wayC_set, rel_wayD_set, + rel_wayE_set, rel_wayF_set, rel_wayG_set, rel_wayH_set}; + +// #################################################### +// Execution Pipe Control +// Port0 => Execution Pipe +// #################################################### + +// access is valid if its a cache_enabled op and not flushed or not a dcbt/dcbf type instruction +assign ex4_c_acc_d = dcc_dir_ex3_cache_acc & (~(fgen_ex3_stg_flush | spr_xucr0_dcdis)); +assign ex5_c_acc_d = ex4_c_acc_q & (~derat_dir_ex4_wimge_i) & ex4_hit & ex4_lru_upd_q & (~fgen_ex4_stg_flush); +assign ex6_c_acc_d = ex5_c_acc_q & (~fgen_ex5_stg_flush); +assign ex2_congr_cl = ex2_eff_addr; +assign ex3_congr_cl_d = ex2_congr_cl; +assign ex4_congr_cl_d = ex3_congr_cl_q; +assign ex5_congr_cl_d = ex4_congr_cl_q; +assign ex6_congr_cl_d = ex5_congr_cl_q; +assign ex4_lru_upd_d = dcc_dir_ex3_lru_upd; + +// #################################################### +// Execution Pipe Directory Read +// #################################################### +// 1-hot Congruence Class Select +generate begin : ldpCClass + genvar cclass; + for (cclass=0; cclass Bypass Logic +// ex4 congruence class matches valid ex5,ex6 or reload congruence class + +assign congr_cl_ex4_ex5_cmp_d = (ex3_congr_cl_q == ex4_congr_cl_q); +assign congr_cl_ex4_ex6_cmp_d = (ex3_congr_cl_q == ex5_congr_cl_q); +assign congr_cl_ex4_stq3_cmp_d = (ex3_congr_cl_q == stq2_congr_cl_q); +assign congr_cl_ex4_stq4_cmp_d = (ex3_congr_cl_q == stq3_congr_cl_q); + +assign congr_cl_ex4_ex5_m = congr_cl_ex4_ex5_cmp_q & ex5_c_acc_q; +assign congr_cl_ex4_ex6_m = congr_cl_ex4_ex6_cmp_q & ex6_c_acc_q; +assign congr_cl_ex4_stq3_m = congr_cl_ex4_stq3_cmp_q & stq3_val_wen; +assign congr_cl_ex4_stq4_m = congr_cl_ex4_stq4_cmp_q & stq4_val_wen_q; + +// Bypass ex3 select +assign congr_cl_ex4_byp[0] = congr_cl_ex4_ex5_m; // 1st priority +assign congr_cl_ex4_byp[1] = congr_cl_ex4_stq3_m; // 2nd priority <-- slowest of all of them +assign congr_cl_ex4_byp[2] = congr_cl_ex4_ex6_m; // 3rd priority +assign congr_cl_ex4_byp[3] = congr_cl_ex4_stq4_m; // 4th priority + +assign congr_cl_ex4_sel[0] = congr_cl_ex4_byp[0]; +assign congr_cl_ex4_sel[1] = congr_cl_ex4_byp[1] & (~congr_cl_ex4_byp[0]); +assign congr_cl_ex4_sel[2] = congr_cl_ex4_byp[2] & ~(|congr_cl_ex4_byp[0:1]); +assign congr_cl_ex4_sel[3] = congr_cl_ex4_byp[3] & ~(|congr_cl_ex4_byp[0:2]); + +assign ex4_lru_arr_sel = ~(|congr_cl_ex4_byp); + +assign lq_congr_cl_lru_d = (ex5_lru_upd & {lruState{congr_cl_ex4_sel[0]}}) | + (stq3_lru_upd & {lruState{congr_cl_ex4_sel[1]}}) | + (ex6_lru_upd_q & {lruState{congr_cl_ex4_sel[2]}}) | + (stq4_lru_upd_q & {lruState{congr_cl_ex4_sel[3]}}) | + (p0_arr_lru_rd & {lruState{ex4_lru_arr_sel}}); + +// Bypassed LRU for Execution Pipe +assign lq_op_lru = lq_congr_cl_lru_q; + +// #################################################### +// LRU update calculation due to an XU op +// #################################################### +// Updating the LRU using the Way that is being reloaded as the Way hit +assign hit_wayA_upd = {2'b11, lq_op_lru[2], 1'b1, lq_op_lru[4:6]}; +assign hit_wayB_upd = {2'b11, lq_op_lru[2], 1'b0, lq_op_lru[4:6]}; +assign hit_wayC_upd = {2'b10, lq_op_lru[2:3], 1'b1, lq_op_lru[5:6]}; +assign hit_wayD_upd = {2'b10, lq_op_lru[2:3], 1'b0, lq_op_lru[5:6]}; +assign hit_wayE_upd = {1'b0, lq_op_lru[1], 1'b1, lq_op_lru[3:4], 1'b1, lq_op_lru[6]}; +assign hit_wayF_upd = {1'b0, lq_op_lru[1], 1'b1, lq_op_lru[3:4], 1'b0, lq_op_lru[6]}; +assign hit_wayG_upd = {1'b0, lq_op_lru[1], 1'b0, lq_op_lru[3:5], 1'b1}; +assign hit_wayh_upd = {1'b0, lq_op_lru[1], 1'b0, lq_op_lru[3:5], 1'b0}; + +// #################################################### +// Selecting between Execution Pipe +// #################################################### +// Selecting Way Hit Updated LRU +assign ldst_hit_vector_d = {ex4_way_hit_a, ex4_way_hit_b, ex4_way_hit_c, ex4_way_hit_d, + ex4_way_hit_e, ex4_way_hit_f, ex4_way_hit_g, ex4_way_hit_h}; +assign ldst_hit_lru_upd = (hit_wayA_upd & {lruState{ldst_hit_vector_q[0]}}) | (hit_wayB_upd & {lruState{ldst_hit_vector_q[1]}}) | + (hit_wayC_upd & {lruState{ldst_hit_vector_q[2]}}) | (hit_wayD_upd & {lruState{ldst_hit_vector_q[3]}}) | + (hit_wayE_upd & {lruState{ldst_hit_vector_q[4]}}) | (hit_wayF_upd & {lruState{ldst_hit_vector_q[5]}}) | + (hit_wayG_upd & {lruState{ldst_hit_vector_q[6]}}) | (hit_wayh_upd & {lruState{ldst_hit_vector_q[7]}}); + +assign ex5_lru_upd = ex5_c_acc_q ? ldst_hit_lru_upd : lq_op_lru; +assign ex6_lru_upd_d = ex5_lru_upd; + +// #################################################### +// Upper Address Caculation +// #################################################### +// Reload Address Calculation +assign rel_way_dwen = {(rel_wayA_clr | rel_wayA_mid | stq_wayA_hit), (rel_wayB_clr | rel_wayB_mid | stq_wayB_hit), + (rel_wayC_clr | rel_wayC_mid | stq_wayC_hit), (rel_wayD_clr | rel_wayD_mid | stq_wayD_hit), + (rel_wayE_clr | rel_wayE_mid | stq_wayE_hit), (rel_wayF_clr | rel_wayF_mid | stq_wayF_hit), + (rel_wayG_clr | rel_wayG_mid | stq_wayG_hit), (rel_wayH_clr | rel_wayH_mid | stq_wayH_hit)}; + +assign dir_dcc_rel3_dcarr_upd = rel3_clr_stg_val_q | rel3_data_stg_val_q; +assign stq4_dcarr_way_en_d = rel_way_dwen; +// #################################################### +// Directory LRU write enable generations +// #################################################### + +// Congruence Class Update Act +assign congr_cl_act_d = ex5_c_acc_q | stq3_val_wen; + +// Update LRU due to a Reload or an EX6 Execution operation +generate begin : lruUpd + genvar cclass; + for (cclass=0; cclass= (tagSize % 8)) begin : R1 + assign extra_byte_par[t] = 1'b0; + end + end + end +endgenerate + +generate begin : par_gen + genvar i; + for (i = 0; i <= (tagSize/8) - 1; i = i + 1) begin : par_gen + assign arr_parity[i] = ^(wr_data[8*i+uprTagBit:8*i+uprTagBit+7]); + end + end +endgenerate + +generate + if ((tagSize % 8) != 0) begin : par_gen_x + assign arr_parity[tagSize/8] = ^(extra_byte_par); + end +endgenerate + +assign arr_wr_data = {wr_data, arr_parity}; + +// #################################################### +// Tag Array Read +// #################################################### + +generate begin : tagRead + genvar way; + for (way=0; way= (tagSize % 8)) begin : R1 + assign p0_extra_tag_par[way][t] = 1'b0; + assign p1_extra_tag_par[way][t] = 1'b0; + end + end + end + end +endgenerate + +generate begin : rdParGen + genvar way; + for (way=0; way 16K L1D$, 15 => 32K L1D$ +//parameter CL_SIZE = 6; // 6 => 64B CLINE, 7 => 128B CLINE + +// ACT's +input dcc_dir_ex2_stg_act; +input dcc_dir_ex3_stg_act; +input dcc_dir_ex4_stg_act; +input dcc_dir_stq1_stg_act; +input dcc_dir_stq2_stg_act; +input dcc_dir_stq3_stg_act; +input dcc_dir_stq4_stg_act; +input dcc_dir_stq5_stg_act; +input dcc_dir_binv2_ex2_stg_act; +input dcc_dir_binv3_ex3_stg_act; +input dcc_dir_binv4_ex4_stg_act; +input dcc_dir_binv5_ex5_stg_act; +input dcc_dir_binv6_ex6_stg_act; + +// Reload and Store Commit Pipe +input lsq_ctl_stq1_val; // Commit Operation is Valid +input lsq_ctl_stq2_blk_req; // Block Store due to RV issue +input [0:`THREADS-1] lsq_ctl_stq1_thrd_id; +input [0:`THREADS-1] lsq_ctl_rel1_thrd_id; +input lsq_ctl_stq1_ci; // Reload/Commit is Cache-Inhibited +input lsq_ctl_stq1_lock_clr; +input lsq_ctl_stq1_watch_clr; +input lsq_ctl_stq1_store_val; +input lsq_ctl_stq1_inval; +input lsq_ctl_stq1_dci_val; +input [0:1] lsq_ctl_stq1_l_fld; +input [64-(`DC_SIZE-3):63-`CL_SIZE] lsq_ctl_stq1_addr; +input lsq_ctl_rel1_clr_val; // Reload data is valid for 1st beat +input lsq_ctl_rel1_set_val; // Reload data is valid for last beat +input lsq_ctl_rel1_back_inv; // Reload was Back-Invalidated +input lsq_ctl_rel2_blk_req; // Block Reload due to RV issue or Back-Invalidate +input lsq_ctl_rel1_lock_set; +input lsq_ctl_rel1_watch_set; +input lsq_ctl_rel2_upd_val; // all 8 data beats have transferred without error, set valid in dir +input lsq_ctl_rel3_l1dump_val; // Reload Complete for an L1_DUMP reload +input dcc_dir_stq6_store_val; + +input rel_way_clr_a; // Reload Stage2 Way A clear existing Valid +input rel_way_clr_b; // Reload Stage2 Way B clear existing Valid +input rel_way_clr_c; // Reload Stage2 Way C clear existing Valid +input rel_way_clr_d; // Reload Stage2 Way D clear existing Valid +input rel_way_clr_e; // Reload Stage2 Way E clear existing Valid +input rel_way_clr_f; // Reload Stage2 Way F clear existing Valid +input rel_way_clr_g; // Reload Stage2 Way G clear existing Valid +input rel_way_clr_h; // Reload Stage2 Way H clear existing Valid + +input rel_way_wen_a; // Reload Stage4 Way A Write Enable +input rel_way_wen_b; // Reload Stage4 Way B Write Enable +input rel_way_wen_c; // Reload Stage4 Way C Write Enable +input rel_way_wen_d; // Reload Stage4 Way D Write Enable +input rel_way_wen_e; // Reload Stage4 Way E Write Enable +input rel_way_wen_f; // Reload Stage4 Way F Write Enable +input rel_way_wen_g; // Reload Stage4 Way G Write Enable +input rel_way_wen_h; // Reload Stage4 Way H Write Enable + +input xu_lq_spr_xucr0_clfc; // Cache Lock Bits Flash Clear +input spr_xucr0_dcdis; // Data Cache Disable +input spr_xucr0_cls; // 128Byte Cacheline Mode + +// Execution Pipe +input dcc_dir_ex2_binv_val; // Back-Invalidate is Valid +input [0:`THREADS-1] dcc_dir_ex2_thrd_id; // Thread ID +input [64-(`DC_SIZE-3):63-`CL_SIZE] ex2_eff_addr; +input dcc_dir_ex3_cache_acc; // Cache Access is Valid +input dcc_dir_ex3_pfetch_val; // Prefetch is Valid +input dcc_dir_ex3_lock_set; // DCBT[ST]LS Operation is valid +input dcc_dir_ex3_th_c; // DCBT[ST]LS Operation is targeting the L1 Data Cache +input dcc_dir_ex3_watch_set; // LDAWX Operation is valid +input dcc_dir_ex3_larx_val; // LARX Operation is valid, the directory should be invalidated if hit +input dcc_dir_ex3_watch_chk; // WCHK Operation is valid +input dcc_dir_ex4_load_val; +input derat_dir_ex4_wimge_i; // Cache-Inhibited Request + +// Execution Pipe Flush +input fgen_ex3_stg_flush; // ex3 Stage Flush +input fgen_ex4_cp_flush; // ex4 CP Flush +input fgen_ex4_stg_flush; // ex4 Stage Flush +input fgen_ex5_stg_flush; // ex5 Stage Flush + +// Directory Parity Error for Execution Pipe +input [0:7] ex4_tag_perr_way; // Directory Way with Parity Error +input [0:7] dat_ctl_dcarr_perr_way; // Data Cache Parity on a Way + +// Tag Compares +input ex4_way_cmp_a; // Way A Compared +input ex4_way_cmp_b; // Way B Compared +input ex4_way_cmp_c; // Way C Compared +input ex4_way_cmp_d; // Way D Compared +input ex4_way_cmp_e; // Way E Compared +input ex4_way_cmp_f; // Way F Compared +input ex4_way_cmp_g; // Way G Compared +input ex4_way_cmp_h; // Way H Compared + +// Commit Pipe +input stq3_way_cmp_a; // Way A Compared +input stq3_way_cmp_b; // Way B Compared +input stq3_way_cmp_c; // Way C Compared +input stq3_way_cmp_d; // Way D Compared +input stq3_way_cmp_e; // Way E Compared +input stq3_way_cmp_f; // Way F Compared +input stq3_way_cmp_g; // Way G Compared +input stq3_way_cmp_h; // Way H Compared + +// Directory Parity Error for Store Commit Pipe +input [0:7] stq3_tag_way_perr; + +// Multihit Error Inject +input pc_lq_inj_dcachedir_ldp_multihit; // Load Pipe Multihit Error Inject from PC +input pc_lq_inj_dcachedir_stp_multihit; // Store Pipe Multihit Error Inject from PC + +// L1 Directory Contents +output [0:1+`THREADS] dir_dcc_ex5_way_a_dir; +output [0:1+`THREADS] dir_dcc_ex5_way_b_dir; +output [0:1+`THREADS] dir_dcc_ex5_way_c_dir; +output [0:1+`THREADS] dir_dcc_ex5_way_d_dir; +output [0:1+`THREADS] dir_dcc_ex5_way_e_dir; +output [0:1+`THREADS] dir_dcc_ex5_way_f_dir; +output [0:1+`THREADS] dir_dcc_ex5_way_g_dir; +output [0:1+`THREADS] dir_dcc_ex5_way_h_dir; + +// L1 Directory Hits +output ex4_way_hit_a; // Way A Hit +output ex4_way_hit_b; // Way B Hit +output ex4_way_hit_c; // Way C Hit +output ex4_way_hit_d; // Way D Hit +output ex4_way_hit_e; // Way E Hit +output ex4_way_hit_f; // Way F Hit +output ex4_way_hit_g; // Way G Hit +output ex4_way_hit_h; // Way H Hit + +// ex4 Execution Pipe Command Outputs +output ex4_miss; // Execution Pipe operation missed in D$ +output ex4_hit; // Execution Pipe operation hit in D$ +output dir_dcc_ex4_set_rel_coll; // Resource Conflict, should cause a reject +output dir_dcc_ex4_byp_restart; // Directory Bypassed stage that was restarted +output dir_dcc_ex5_dir_perr_det; // Data Directory Parity Error Detected on the LDQ Pipeline +output dir_dcc_ex5_dc_perr_det; // Data Cache Parity Error Detected on the LDQ Pipeline +output dir_dcc_ex5_dir_perr_flush; // Data Directory Parity Error Flush on the LDQ Pipeline +output dir_dcc_ex5_dc_perr_flush; // Data Cache Parity Error Flush on the LDQ Pipeline +output dir_dcc_ex5_multihit_det; // Directory Multihit Detected on the LDQ Pipeline +output dir_dcc_ex5_multihit_flush; // Directory Multihit Flush on the LDQ Pipeline +output dir_dcc_stq4_dir_perr_det; // Data Cache Parity Error Detected on the STQ Commit Pipeline +output dir_dcc_stq4_multihit_det; // Directory Multihit Detected on the STQ Commit Pipeline +output dir_dcc_ex5_stp_flush; // Directory Error detected on the STQ Commit Pipeline with EX5 LDP valid + +// Performance Events +output [0:(`THREADS*3)+1] ctl_perv_dir_perf_events; // Performance Events + +// SPR status +output lq_xu_spr_xucr0_cslc_xuop; // Invalidate type instruction invalidated lock +output lq_xu_spr_xucr0_cslc_binv; // Back-Invalidate invalidated lock + +// ex5 Execution Pipe Command Outputs +output dir_dcc_ex5_cr_rslt; // Condition Register Results from Watch instructions + +// stq4 Recirculation Pipe Command Outputs +output stq2_ddir_acc; // Directory Array Access is valid +output stq3_way_hit_a; // Way A Hit +output stq3_way_hit_b; // Way B Hit +output stq3_way_hit_c; // Way C Hit +output stq3_way_hit_d; // Way D Hit +output stq3_way_hit_e; // Way E Hit +output stq3_way_hit_f; // Way F Hit +output stq3_way_hit_g; // Way G Hit +output stq3_way_hit_h; // Way H Hit +output stq3_miss; // Recirculation Pipe operation missed in L1 D$ +output stq3_hit; // Recirculation Pipe operation hit in L1 D$ +output ctl_lsq_stq4_perr_reject; // STQ4 detected a parity error, need to reject STQ2 Commit +output [0:7] ctl_dat_stq5_way_perr_inval; // STQ5 Gate Data Cache Write due to Directory Error + +// Way Valids for Replacement Algorithm +output rel_way_val_a; // Way A Valid for Replacement algorithm +output rel_way_val_b; // Way B Valid for Replacement algorithm +output rel_way_val_c; // Way C Valid for Replacement algorithm +output rel_way_val_d; // Way D Valid for Replacement algorithm +output rel_way_val_e; // Way E Valid for Replacement algorithm +output rel_way_val_f; // Way F Valid for Replacement algorithm +output rel_way_val_g; // Way G Valid for Replacement algorithm +output rel_way_val_h; // Way H Valid for Replacement algorithm + +// Congruence Class Line Lock +output rel_way_lock_a; // Way A Locked Line for Replacement algorithm +output rel_way_lock_b; // Way B Locked Line for Replacement algorithm +output rel_way_lock_c; // Way C Locked Line for Replacement algorithm +output rel_way_lock_d; // Way D Locked Line for Replacement algorithm +output rel_way_lock_e; // Way E Locked Line for Replacement algorithm +output rel_way_lock_f; // Way F Locked Line for Replacement algorithm +output rel_way_lock_g; // Way G Locked Line for Replacement algorithm +output rel_way_lock_h; // Way H Locked Line for Replacement algorithm + +//pervasive + + +inout vdd; + + +inout gnd; + +(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) + +input [0:`NCLK_WIDTH-1] nclk; +input sg_0; +input func_sl_thold_0_b; +input func_sl_force; +input func_slp_sl_thold_0_b; +input func_slp_sl_force; +input func_nsl_thold_0_b; +input func_nsl_force; +input func_slp_nsl_thold_0_b; +input func_slp_nsl_force; +input d_mode_dc; +input delay_lclkr_dc; +input mpw1_dc_b; +input mpw2_dc_b; + +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + +input [0:2] scan_in; + +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + +output [0:2] scan_out; + +//-------------------------- +// components +//-------------------------- + +//-------------------------- +// signals +//-------------------------- +parameter uprCClassBit = 64 - (`DC_SIZE - 3); +parameter lwrCClassBit = 63 - `CL_SIZE; +parameter numCClass = ((2 ** `DC_SIZE)/(2 ** `CL_SIZE))/8; +parameter dirState = 2 + `THREADS; +parameter numWays = 8; + + +wire [0:dirState-1] congr_cl_wA_d[0:numCClass-1]; +wire [0:dirState-1] congr_cl_wA_q[0:numCClass-1]; +wire [0:dirState-1] congr_cl_wB_d[0:numCClass-1]; +wire [0:dirState-1] congr_cl_wB_q[0:numCClass-1]; +wire [0:dirState-1] congr_cl_wC_d[0:numCClass-1]; +wire [0:dirState-1] congr_cl_wC_q[0:numCClass-1]; +wire [0:dirState-1] congr_cl_wD_d[0:numCClass-1]; +wire [0:dirState-1] congr_cl_wD_q[0:numCClass-1]; +wire [0:dirState-1] congr_cl_wE_d[0:numCClass-1]; +wire [0:dirState-1] congr_cl_wE_q[0:numCClass-1]; +wire [0:dirState-1] congr_cl_wF_d[0:numCClass-1]; +wire [0:dirState-1] congr_cl_wF_q[0:numCClass-1]; +wire [0:dirState-1] congr_cl_wG_d[0:numCClass-1]; +wire [0:dirState-1] congr_cl_wG_q[0:numCClass-1]; +wire [0:dirState-1] congr_cl_wH_d[0:numCClass-1]; +wire [0:dirState-1] congr_cl_wH_q[0:numCClass-1]; +wire [0:1] rel_bixu_wayA_upd[0:numCClass-1]; +wire [0:1] rel_bixu_wayB_upd[0:numCClass-1]; +wire [0:1] rel_bixu_wayC_upd[0:numCClass-1]; +wire [0:1] rel_bixu_wayD_upd[0:numCClass-1]; +wire [0:1] rel_bixu_wayE_upd[0:numCClass-1]; +wire [0:1] rel_bixu_wayF_upd[0:numCClass-1]; +wire [0:1] rel_bixu_wayG_upd[0:numCClass-1]; +wire [0:1] rel_bixu_wayH_upd[0:numCClass-1]; +wire [0:numWays-1] p0_way_data_upd_way[0:numCClass-1]; +wire [0:numWays-1] p1_way_data_upd_way[0:numCClass-1]; +wire [0:numCClass-1] p0_congr_cl_m; +wire [0:numCClass-1] p1_congr_cl_m; +wire [0:numCClass-1] p0_congr_cl_act_d; +wire [0:numCClass-1] p0_congr_cl_act_q; +wire [0:numCClass-1] p1_congr_cl_act_d; +wire [0:numCClass-1] p1_congr_cl_act_q; +wire [0:numCClass-1] congr_cl_act; +wire [0:numWays-1] rel_way_clr; +wire [0:numWays-1] rel_way_set; +reg [0:dirState-1] p0_arr_way_rd[0:numWays-1]; +reg [0:dirState-1] p1_arr_way_rd[0:numWays-1]; +wire [0:numWays-1] ex4_way_hit; +wire [0:numWays-1] ex4_way_cmp; +wire [0:4] congr_cl_ex3_way_byp[0:numWays-1]; +wire [1:4] congr_cl_ex3_way_sel[0:numWays-1]; +wire [0:numWays-1] ex3_way_arr_sel; +wire [0:dirState-1] ex3_way_stg_pri[0:numWays-1]; +wire [0:dirState-1] ex4_way_val_d[0:numWays-1]; +wire [0:dirState-1] ex4_way_val_q[0:numWays-1]; +wire [0:dirState-1] ex5_way_val_d[0:numWays-1]; +wire [0:dirState-1] ex5_way_val_q[0:numWays-1]; +wire [0:numWays-1] ex5_clr_lck_way_d; +wire [0:numWays-1] ex5_clr_lck_way_q; +wire [0:`THREADS-1] ex5_lost_way[0:numWays-1]; +wire [0:numWays-1] ex5_way_upd; +wire [0:numWays-1] ex5_way_upd_d; +wire [0:numWays-1] ex5_way_upd_q; +wire [0:numWays-1] ex6_way_upd_d; +wire [0:numWays-1] ex6_way_upd_q; +wire [0:numWays-1] ex7_way_upd_d; +wire [0:numWays-1] ex7_way_upd_q; +wire [0:dirState-1] ex4_dir_way[0:numWays-1]; +wire [0:dirState-1] ex5_dir_way_err[0:numWays-1]; +wire [0:dirState-1] ex5_dir_way_d[0:numWays-1]; +wire [0:dirState-1] ex5_dir_way_q[0:numWays-1]; +wire [0:dirState-1] ex6_dir_way_d[0:numWays-1]; +wire [0:dirState-1] ex6_dir_way_q[0:numWays-1]; +wire [2:dirState-1] ex7_dir_way_d[0:numWays-1]; +wire [2:dirState-1] ex7_dir_way_q[0:numWays-1]; +wire [0:numWays-1] ex4_way_watch; +wire [0:numWays-1] ex4_way_lock; +wire [0:`THREADS-1] ex4_err_way_watchlost[0:numWays-1]; +wire [0:4] congr_cl_stq2_way_byp[0:numWays-1]; +wire [1:4] congr_cl_stq2_way_sel[0:numWays-1]; +wire [0:numWays-1] stq2_way_arr_sel; +wire [0:dirState-1] stq2_way_stg_pri[0:numWays-1]; +wire [0:dirState-1] stq3_way_val_d[0:numWays-1]; +wire [0:dirState-1] stq3_way_val_q[0:numWays-1]; +wire [2:dirState-1] stq4_way_val_d[0:numWays-1]; +wire [2:dirState-1] stq4_way_val_q[0:numWays-1]; +wire [0:numWays-1] stq3_way_hit; +wire [0:numWays-1] stq3_way_cmp; +wire [0:dirState-1] stq3_dir_way[0:numWays-1]; +wire [0:dirState-1] stq4_dir_way_d[0:numWays-1]; +wire [0:dirState-1] stq4_dir_way_q[0:numWays-1]; +wire [0:dirState-1] stq4_dir_way_err[0:numWays-1]; +wire [0:dirState-1] stq5_dir_way_d[0:numWays-1]; +wire [0:dirState-1] stq5_dir_way_q[0:numWays-1]; +wire [0:numWays-1] stq2_ex5_ldp_err; +wire [0:numWays-1] stq3_ex6_ldp_err_d; +wire [0:numWays-1] stq3_ex6_ldp_err_q; +wire [0:numWays-1] stq4_ex7_ldp_err_d; +wire [0:numWays-1] stq4_ex7_ldp_err_q; +wire [0:numWays-1] stq3_ex5_ldp_err; +wire [0:numWays-1] stq4_ex6_ldp_err_d; +wire [0:numWays-1] stq4_ex6_ldp_err_q; +wire [0:numWays-1] stq4_ex5_ldp_err; +wire [0:numWays-1] stq4_ex_ldp_err_det; + + +wire [0:numWays-1] stq2_stq4_stp_err; +wire [0:numWays-1] stq3_stq5_stp_err_d; +wire [0:numWays-1] stq3_stq5_stp_err_q; +wire [0:numWays-1] stq4_stq6_stp_err_d; +wire [0:numWays-1] stq4_stq6_stp_err_q; +wire [0:numWays-1] stq3_stq4_stp_err; +wire [0:numWays-1] stq4_stq5_stp_err_d; +wire [0:numWays-1] stq4_stq5_stp_err_q; +wire [0:numWays-1] stq4_stq_stp_err_det; + + +wire [0:numWays-1] stq3_way_lock; +wire [0:numWays-1] stq4_clr_lck_way_d; +wire [0:numWays-1] stq4_clr_lck_way_q; +wire [0:numWays-1] stq4_lose_watch_way; +wire [0:`THREADS-1] stq4_lost_way[0:numWays-1]; +wire [0:`THREADS-1] rel_lost_watch_way_evict[0:numWays-1]; +wire [0:`THREADS-1] ex7_lost_watch_way_evict[0:numWays-1]; +wire [0:numWays-1] stq3_way_upd; +wire [0:numWays-1] stq4_way_upd; +wire [0:numWays-1] stq4_way_upd_d; +wire [0:numWays-1] stq4_way_upd_q; +wire [0:numWays-1] stq5_way_upd_d; +wire [0:numWays-1] stq5_way_upd_q; +wire [0:numWays-1] stq6_way_upd_d; +wire [0:numWays-1] stq6_way_upd_q; +wire [0:numWays-1] stq7_way_upd_d; +wire [0:numWays-1] stq7_way_upd_q; +wire [0:numWays-1] stq4_rel_way_clr_d; +wire [0:numWays-1] stq4_rel_way_clr_q; +wire [0:dirState-1] stq4_dir_way_rel[0:numWays-1]; +wire [0:`THREADS-1] stq3_err_way_watchlost[0:numWays-1]; +wire ex4_cache_acc_d; +wire ex4_cache_acc_q; +wire ex5_cache_acc_d; +wire ex5_cache_acc_q; +wire ex5_mhit_cacc_d; +wire ex5_mhit_cacc_q; +wire ex4_pfetch_val_d; +wire ex4_pfetch_val_q; +wire ex4_cache_en_val; +wire ex3_binv_val_d; +wire ex3_binv_val_q; +wire ex4_binv_val_d; +wire ex4_binv_val_q; +wire ex5_binv_val_d; +wire ex5_binv_val_q; +wire [0:`THREADS-1] ex2_thrd_id; +wire [0:`THREADS-1] ex3_thrd_id_d; +wire [0:`THREADS-1] ex3_thrd_id_q; +wire [0:`THREADS-1] ex4_thrd_id_d; +wire [0:`THREADS-1] ex4_thrd_id_q; +wire [0:`THREADS-1] ex5_thrd_id_d; +wire [0:`THREADS-1] ex5_thrd_id_q; +wire ex3_lock_set; +wire ex4_lock_set_d; +wire ex4_lock_set_q; +wire ex5_lock_set_d; +wire ex5_lock_set_q; +wire ex4_watch_set_d; +wire ex4_watch_set_q; +wire ex5_watch_set_d; +wire ex5_watch_set_q; +wire ex6_watch_set_d; +wire ex6_watch_set_q; +wire ex4_larx_val_d; +wire ex4_larx_val_q; +wire ex7_watch_set_inval_d; +wire ex7_watch_set_inval_q; +wire ex4_clr_watch; +wire [0:`THREADS-1] ex4_set_watch; +wire ex5_lose_watch_d; +wire ex5_lose_watch_q; +wire ex4_clr_val_way; +wire ex4_xuop_upd_val; +wire ex4_xuop_upd_val_d; +wire ex4_xuop_upd_val_q; +wire ex5_xuop_upd_val; +wire ex5_xuop_upd_val_d; +wire ex5_xuop_upd_val_q; +wire binv4_ex4_xuop_upd; +wire binv4_ex4_dir_val; +wire binv5_ex5_dir_val_d; +wire binv5_ex5_dir_val_q; +wire [0:numWays-1] ex5_way_hit_d; +wire [0:numWays-1] ex5_way_hit_q; +wire [uprCClassBit:lwrCClassBit] ex2_congr_cl; +wire [uprCClassBit:lwrCClassBit] ex3_congr_cl_d; +wire [uprCClassBit:lwrCClassBit] ex3_congr_cl_q; +wire [0:numCClass-1] ex3_congr_cl_1hot; +wire [uprCClassBit:lwrCClassBit] ex4_congr_cl_d; +wire [uprCClassBit:lwrCClassBit] ex4_congr_cl_q; +wire [uprCClassBit:lwrCClassBit] ex5_congr_cl_d; +wire [uprCClassBit:lwrCClassBit] ex5_congr_cl_q; +wire [0:numWays-1] ex4_dcarr_perr_way; +wire [0:numWays-1] stq6_dcarr_perr_way; +wire [0:numWays-1] ex4_perr_way; +wire ex5_cr_watch_d; +wire ex5_cr_watch_q; +wire congr_cl_ex3_ex4_cmp_d; +wire congr_cl_ex3_ex4_cmp_q; +wire congr_cl_ex3_ex5_cmp_d; +wire congr_cl_ex3_ex5_cmp_q; +wire congr_cl_ex3_ex6_cmp_d; +wire congr_cl_ex3_ex6_cmp_q; +wire congr_cl_ex3_stq4_cmp_d; +wire congr_cl_ex3_stq4_cmp_q; +wire congr_cl_ex3_stq5_cmp_d; +wire congr_cl_ex3_stq5_cmp_q; +wire congr_cl_ex4_ex5_cmp_d; +wire congr_cl_ex4_ex5_cmp_q; +wire congr_cl_ex4_ex6_cmp_d; +wire congr_cl_ex4_ex6_cmp_q; +wire congr_cl_ex5_ex6_cmp_d; +wire congr_cl_ex5_ex6_cmp_q; +wire congr_cl_ex5_ex7_cmp_d; +wire congr_cl_ex5_ex7_cmp_q; +wire congr_cl_ex5_stq5_cmp_d; +wire congr_cl_ex5_stq5_cmp_q; +wire congr_cl_ex5_stq6_cmp_d; +wire congr_cl_ex5_stq6_cmp_q; +wire congr_cl_ex5_stq7_cmp_d; +wire congr_cl_ex5_stq7_cmp_q; +wire congr_cl_ex4_ex6_rest_d; +wire congr_cl_ex4_ex6_rest_q; +wire congr_cl_ex4_byp_restart; +wire congr_cl_ex3_ex4_m; +wire congr_cl_ex3_ex5_m; +wire congr_cl_ex3_ex6_m; +wire congr_cl_ex3_stq4_m; +wire congr_cl_ex3_stq5_m; +wire ex5_inval_clr_lock; +wire ex5_cClass_lock_set_d; +wire ex5_cClass_lock_set_q; +wire [0:`THREADS-1] stq4_dci_watch_lost; +reg [0:`THREADS-1] ex5_lost_watch; +wire [0:`THREADS-1] ex5_watchlost_binv; +reg [0:`THREADS-1] ex5_cClass_thrd_watch_d; +wire [0:`THREADS-1] ex5_cClass_thrd_watch_q; +wire [0:`THREADS-1] ex5_watchlost_upd; +wire [0:`THREADS-1] ex5_watchlost_set; +wire ex4_curr_watch; +wire ex4_stm_watchlost_sel; +wire ex4_hit_and_01_b; +wire ex4_hit_and_23_b; +wire ex4_hit_and_45_b; +wire ex4_hit_and_67_b; +wire ex4_hit_or_01_b; +wire ex4_hit_or_23_b; +wire ex4_hit_or_45_b; +wire ex4_hit_or_67_b; +wire ex4_hit_or_0123; +wire ex4_hit_or_4567; +wire ex4_hit_and_0123; +wire ex4_hit_and_4567; +wire ex4_multi_hit_err2_0; +wire ex4_multi_hit_err2_1; +wire ex4_hit_or_01234567_b; +wire [0:2] ex4_multi_hit_err3_b; +wire ex4_dir_multihit_val_0; +wire ex4_dir_multihit_val_1; +wire ex4_dir_multihit_val_b; +wire ex5_dir_multihit_val_b_d; +wire ex5_dir_multihit_val_b_q; +wire ex5_dir_multihit_val; +wire ex5_dir_multihit_det; +wire ex5_dir_multihit_flush; +wire ex5_multihit_lock_lost; +wire [0:`THREADS-1] ex5_multihit_watch_lost; +wire [0:7] ex4_dir_perr_det; +wire [0:7] ex4_dc_perr_det; +wire [0:7] ex4_err_det_way; +wire [0:7] ex5_err_det_way_d; +wire [0:7] ex5_err_det_way_q; +wire [0:7] ex4_err_lock_lost; +wire ex5_perr_lock_lost_d; +wire ex5_perr_lock_lost_q; +reg [0:`THREADS-1] ex5_perr_watchlost_d; +wire [0:`THREADS-1] ex5_perr_watchlost_q; +wire ex5_dir_perr_det_d; +wire ex5_dir_perr_det_q; +wire ex5_dc_perr_det_d; +wire ex5_dc_perr_det_q; +wire ex5_dir_perr_flush_d; +wire ex5_dir_perr_flush_q; +wire ex5_dc_perr_flush_d; +wire ex5_dc_perr_flush_q; +wire ex5_way_perr_det_d; +wire ex5_way_perr_det_q; +wire [0:numWays-1] ex5_way_perr_inval; +wire ex5_xuop_perr_det; +wire ex5_way_err_val; +wire ex4_stq2_congr_cl_m_d; +wire ex4_stq2_congr_cl_m_q; +wire ex4_stq2_set_rel_coll; +wire ex4_stq3_set_rel_coll_d; +wire ex4_stq3_set_rel_coll_q; +wire ex4_stq4_set_rel_coll_d; +wire ex4_stq4_set_rel_coll_q; +wire ex4_lockwatchSet_rel_coll; +wire [0:numWays-1] binv5_ex5_way_upd; +wire [0:numWays-1] binv6_ex6_way_upd; +wire [0:numWays-1] binv7_ex7_way_upd; +wire [0:numWays-1] stq5_way_upd; +wire [0:numWays-1] stq6_way_upd; +wire [0:numWays-1] stq7_way_upd; +reg [1:dirState-1] binv5_ex5_dir_data; +wire [1:dirState-1] binv6_ex6_dir_data_d; +wire [1:dirState-1] binv6_ex6_dir_data_q; +wire [1:dirState-1] binv7_ex7_dir_data_d; +wire [1:dirState-1] binv7_ex7_dir_data_q; +reg [1:dirState-1] stq5_dir_data; +wire [1:dirState-1] stq6_dir_data_d; +wire [1:dirState-1] stq6_dir_data_q; +wire [1:dirState-1] stq7_dir_data_d; +wire [1:dirState-1] stq7_dir_data_q; +wire binv5_inval_lck; +wire binv5_inval_lock_val; +wire [0:`THREADS-1] binv5_inval_watch; +wire [0:`THREADS-1] binv5_inval_watch_val; +wire binv5_ex6_coll; +wire binv5_ex7_coll; +wire binv5_stq5_coll; +wire binv5_stq6_coll; +wire binv5_stq7_coll; +wire binv5_coll_val; +wire [0:4] binv5_pri_byp_sel; +wire [1:dirState-1] binv5_byp_dir_data; +wire stq2_ci_d; +wire stq2_ci_q; +wire stq2_cen_acc; +wire stq2_cen_acc_d; +wire stq2_cen_acc_q; +wire stq2_dci_val_d; +wire stq2_dci_val_q; +wire stq3_dci_val_d; +wire stq3_dci_val_q; +wire stq4_dci_val_d; +wire stq4_dci_val_q; +wire stq2_val; +wire stq2_val_d; +wire stq2_val_q; +wire stq3_val_d; +wire stq3_val_q; +wire stq4_val_d; +wire stq4_val_q; +wire [0:`THREADS-1] stq2_thrd_id_d; +wire [0:`THREADS-1] stq2_thrd_id_q; +wire [0:`THREADS-1] stq3_thrd_id_d; +wire [0:`THREADS-1] stq3_thrd_id_q; +wire [0:`THREADS-1] stq4_thrd_id_d; +wire [0:`THREADS-1] stq4_thrd_id_q; +wire [0:`THREADS-1] rel2_thrd_id_d; +wire [0:`THREADS-1] rel2_thrd_id_q; +wire [0:`THREADS-1] rel3_thrd_id_d; +wire [0:`THREADS-1] rel3_thrd_id_q; +wire stq2_lock_clr_d; +wire stq2_lock_clr_q; +wire stq3_lock_clr_d; +wire stq3_lock_clr_q; +wire stq2_watch_clr_d; +wire stq2_watch_clr_q; +wire stq3_watch_clr_d; +wire stq3_watch_clr_q; +wire stq2_store_val_d; +wire stq2_store_val_q; +wire stq3_store_val_d; +wire stq3_store_val_q; +wire stq2_l_fld_b1_d; +wire stq2_l_fld_b1_q; +wire stq3_l_fld_b1_d; +wire stq3_l_fld_b1_q; +wire stq4_l_fld_b1_d; +wire stq4_l_fld_b1_q; +wire stq2_inval_op_d; +wire stq2_inval_op_q; +wire stq3_inval_op_d; +wire stq3_inval_op_q; +wire stq1_watch_clr_all; +wire stq2_watch_clr_all_d; +wire stq2_watch_clr_all_q; +wire stq3_watch_clr_all_d; +wire stq3_watch_clr_all_q; +wire stq4_watch_clr_all_d; +wire stq4_watch_clr_all_q; +wire [uprCClassBit:lwrCClassBit] stq1_congr_cl; +wire [uprCClassBit:lwrCClassBit] stq2_congr_cl_d; +wire [uprCClassBit:lwrCClassBit] stq2_congr_cl_q; +wire [0:numCClass-1] stq2_congr_cl_1hot; +wire [uprCClassBit:lwrCClassBit] stq3_congr_cl_d; +wire [uprCClassBit:lwrCClassBit] stq3_congr_cl_q; +wire [uprCClassBit:lwrCClassBit] stq4_congr_cl_d; +wire [uprCClassBit:lwrCClassBit] stq4_congr_cl_q; +wire [uprCClassBit:lwrCClassBit] stq5_congr_cl_d; +wire [uprCClassBit:lwrCClassBit] stq5_congr_cl_q; +wire [uprCClassBit:lwrCClassBit] stq6_congr_cl_d; +wire [uprCClassBit:lwrCClassBit] stq6_congr_cl_q; +wire rel2_clr_stg_val; +wire rel2_clr_stg_val_d; +wire rel2_clr_stg_val_q; +wire rel3_clr_stg_val_d; +wire rel3_clr_stg_val_q; +wire rel4_clr_stg_val_d; +wire rel4_clr_stg_val_q; +wire rel5_clr_stg_val_d; +wire rel5_clr_stg_val_q; +wire rel2_set_dir_val; +wire rel3_set_dir_val_d; +wire rel3_set_dir_val_q; +wire rel4_set_dir_val_d; +wire rel4_set_dir_val_q; +wire rel2_set_stg_val_d; +wire rel2_set_stg_val_q; +wire rel3_set_stg_val_d; +wire rel3_set_stg_val_q; +wire rel2_back_inv_d; +wire rel2_back_inv_q; +wire rel3_back_inv_d; +wire rel3_back_inv_q; +wire rel3_upd_val_d; +wire rel3_upd_val_q; +wire rel2_lock_set_d; +wire rel2_lock_set_q; +wire rel3_lock_set_d; +wire rel3_lock_set_q; +wire rel3_lock_pipe_d; +wire rel3_lock_pipe_q; +wire rel2_watch_set_d; +wire rel2_watch_set_q; +wire rel3_watch_set_d; +wire rel3_watch_set_q; +wire rel3_watch_pipe_d; +wire rel3_watch_pipe_q; +wire stq2_dir_upd_val; +wire stq3_dir_upd_val_d; +wire stq3_dir_upd_val_q; +wire stq4_dir_upd_val_d; +wire stq4_dir_upd_val_q; +wire stq3_rel3_val_d; +wire stq3_rel3_val_q; +wire stq4_rel4_val_d; +wire stq4_rel4_val_q; +wire stq3_clr_lock; +wire [0:`THREADS-1] rel3_set_watch; +wire stq4_lose_watch_d; +wire stq4_lose_watch_q; +wire [0:`THREADS-1] stq3_store_clr_watch; +wire [0:`THREADS-1] stq3_wclr_clr_watch; +wire [0:`THREADS-1] stq3_inval_clr_watch; +wire [0:`THREADS-1] stq3_clr_watch; +wire [0:numWays-1] stq4_way_hit_d; +wire [0:numWays-1] stq4_way_hit_q; +wire congr_cl_stq2_stq3_cmp_d; +wire congr_cl_stq2_stq3_cmp_q; +wire congr_cl_stq2_stq4_cmp_d; +wire congr_cl_stq2_stq4_cmp_q; +wire congr_cl_stq2_stq5_cmp_d; +wire congr_cl_stq2_stq5_cmp_q; +wire congr_cl_stq3_stq4_cmp_d; +wire congr_cl_stq3_stq4_cmp_q; +wire congr_cl_stq2_ex5_cmp_d; +wire congr_cl_stq2_ex5_cmp_q; +wire congr_cl_stq2_ex6_cmp_d; +wire congr_cl_stq2_ex6_cmp_q; +wire congr_cl_stq3_ex6_cmp_d; +wire congr_cl_stq3_ex6_cmp_q; +wire congr_cl_stq3_ex5_cmp_d; +wire congr_cl_stq3_ex5_cmp_q; +wire congr_cl_stq4_ex5_cmp_d; +wire congr_cl_stq4_ex5_cmp_q; +wire congr_cl_stq2_stq3_m; +wire congr_cl_stq2_stq4_m; +wire congr_cl_stq2_stq5_m; +wire congr_cl_stq2_ex5_m; +wire congr_cl_stq2_ex6_m; +wire stq4_inval_clr_lock; +wire stq4_cClass_lock_set_d; +wire stq4_cClass_lock_set_q; +wire rel3_way_set; +wire rel3_binv_lock_lost; +wire rel3_l1dump_lock_lost; +wire binv_rel_lock_lost; +wire rel3_binv_watch_lost; +wire rel3_l1dump_watch_lost; +wire rel3_ovl_watch_lost; +wire [0:`THREADS-1] rel3_all_watch_lost; +wire [0:`THREADS-1] rel4_all_watch_lost_d; +wire [0:`THREADS-1] rel4_all_watch_lost_q; +wire [0:`THREADS-1] stq4_lost_watch; +reg [0:`THREADS-1] stq4_cClass_thrd_watch_d; +wire [0:`THREADS-1] stq4_cClass_thrd_watch_q; +wire [0:`THREADS-1] stq4_watchlost_value; +wire [0:`THREADS-1] stq4_watch_clr_all; +wire [0:`THREADS-1] stq4_watchlost_upd; +wire [0:`THREADS-1] stq4_watchlost_set; +wire [0:`THREADS-1] lost_watch_evict_ovl_d; +wire [0:`THREADS-1] lost_watch_evict_ovl_q; +reg [0:`THREADS-1] stq4_instr_watch_lost; +reg [0:`THREADS-1] rel_lost_watch_evict; +reg [0:`THREADS-1] ex7_lost_watch_evict; +wire stq3_hit_and_01_b; +wire stq3_hit_and_23_b; +wire stq3_hit_and_45_b; +wire stq3_hit_and_67_b; +wire stq3_hit_or_01_b; +wire stq3_hit_or_23_b; +wire stq3_hit_or_45_b; +wire stq3_hit_or_67_b; +wire stq3_hit_or_0123; +wire stq3_hit_or_4567; +wire stq3_hit_and_0123; +wire stq3_hit_and_4567; +wire stq3_multi_hit_err2_0; +wire stq3_multi_hit_err2_1; +wire stq3_hit_or_01234567_b; +wire [0:2] stq3_multi_hit_err3_b; +wire stq3_dir_multihit_val_0; +wire stq3_dir_multihit_val_1; +wire stq3_dir_multihit_val_b; +wire stq4_dir_multihit_val_b_d; +wire stq4_dir_multihit_val_b_q; +wire stq4_dir_multihit_det; +wire stq4_multihit_lock_lost; +wire [0:`THREADS-1] stq4_multihit_watch_lost; +wire [0:numWays-1] stq3_err_det_way; +wire [0:numWays-1] stq4_err_det_way_d; +wire [0:numWays-1] stq4_err_det_way_q; +wire [0:numWays-1] stq3_err_lock_lost; +wire stq4_perr_lock_lost_d; +wire stq4_perr_lock_lost_q; +reg [0:`THREADS-1] stq4_perr_watchlost_d; +wire [0:`THREADS-1] stq4_perr_watchlost_q; +wire stq4_dir_perr_det_d; +wire stq4_dir_perr_det_q; +wire [0:numWays-1] stq4_way_perr_inval; +wire [0:numWays-1] stq5_way_perr_inval_d; +wire [0:numWays-1] stq5_way_perr_inval_q; +wire stq4_dir_err_val; +wire stq5_dir_err_val_d; +wire stq5_dir_err_val_q; +wire ex5_stp_perr_flush_d; +wire ex5_stp_perr_flush_q; +wire ex5_stp_multihit_flush; +wire [0:1] stm_upd_watchlost_tid[0:`THREADS-1]; +wire [0:`THREADS-1] stm_watchlost; +wire [0:`THREADS-1] stm_watchlost_state_d; +wire [0:`THREADS-1] stm_watchlost_state_q; +wire p0_wren_d; +wire p0_wren_q; +wire p0_wren_cpy_d; +wire p0_wren_cpy_q; +wire p0_wren_stg_d; +wire p0_wren_stg_q; +wire p1_wren_d; +wire p1_wren_q; +wire p1_wren_cpy_d; +wire p1_wren_cpy_q; +wire stq6_wren_d; +wire stq6_wren_q; +wire stq7_wren_d; +wire stq7_wren_q; +wire congr_cl_all_act_d; +wire congr_cl_all_act_q; +wire lock_finval_d; +wire lock_finval_q; +wire val_finval_d; +wire val_finval_q; +wire [0:`THREADS-1] watch_finval_d; +wire [0:`THREADS-1] watch_finval_q; +wire spr_xucr0_clfc_d; +wire spr_xucr0_clfc_q; +wire inj_dirmultihit_ldp_b; +wire inj_dirmultihit_ldp_d; +wire inj_dirmultihit_ldp_q; +wire inj_dirmultihit_stp_b; +wire inj_dirmultihit_stp_d; +wire inj_dirmultihit_stp_q; +wire xucr0_cslc_xuop_d; +wire xucr0_cslc_xuop_q; +wire xucr0_cslc_binv_d; +wire xucr0_cslc_binv_q; +wire perf_dir_binv_val; +wire perf_dir_binv_hit; +wire [0:`THREADS-1] perf_dir_interTid_watchlost; +wire [0:`THREADS-1] perf_dir_evict_watchlost; +wire [0:`THREADS-1] perf_dir_binv_watchlost; +wire [0:`THREADS-1] lost_watch_inter_thrd_d; +wire [0:`THREADS-1] lost_watch_inter_thrd_q; +wire [0:`THREADS-1] lost_watch_evict_val_d; +wire [0:`THREADS-1] lost_watch_evict_val_q; +wire [0:`THREADS-1] lost_watch_binv_d; +wire [0:`THREADS-1] lost_watch_binv_q; + +//-------------------------- +// constants +//-------------------------- +parameter congr_cl_wA_offset = 0; +parameter congr_cl_wB_offset = congr_cl_wA_offset + numCClass*dirState; +parameter congr_cl_wC_offset = congr_cl_wB_offset + numCClass*dirState; +parameter congr_cl_wD_offset = congr_cl_wC_offset + numCClass*dirState; +parameter congr_cl_wE_offset = congr_cl_wD_offset + numCClass*dirState; +parameter congr_cl_wF_offset = congr_cl_wE_offset + numCClass*dirState; +parameter congr_cl_wG_offset = congr_cl_wF_offset + numCClass*dirState; +parameter congr_cl_wH_offset = congr_cl_wG_offset + numCClass*dirState; +parameter p0_congr_cl_act_offset = congr_cl_wH_offset + numCClass*dirState; +parameter p1_congr_cl_act_offset = p0_congr_cl_act_offset + numCClass; +parameter ex4_way_val_offset = p1_congr_cl_act_offset + numCClass; +parameter ex5_way_val_offset = ex4_way_val_offset + numWays*dirState; +parameter ex5_clr_lck_way_offset = ex5_way_val_offset + numWays*dirState; +parameter ex5_way_upd_offset = ex5_clr_lck_way_offset + numWays; +parameter ex6_way_upd_offset = ex5_way_upd_offset + numWays; +parameter ex7_way_upd_offset = ex6_way_upd_offset + numWays; +parameter ex5_dir_way_offset = ex7_way_upd_offset + numWays; +parameter ex6_dir_way_offset = ex5_dir_way_offset + numWays*dirState; +parameter ex7_dir_way_offset = ex6_dir_way_offset + numWays*dirState; +parameter stq3_way_val_offset = ex7_dir_way_offset + numWays*(dirState-2); +parameter stq4_way_val_offset = stq3_way_val_offset + numWays*dirState; +parameter stq4_dir_way_offset = stq4_way_val_offset + numWays*(dirState-2); +parameter stq5_dir_way_offset = stq4_dir_way_offset + numWays*dirState; +parameter stq3_ex6_ldp_err_offset = stq5_dir_way_offset + numWays*dirState; +parameter stq4_ex7_ldp_err_offset = stq3_ex6_ldp_err_offset + numWays; +parameter stq4_ex6_ldp_err_offset = stq4_ex7_ldp_err_offset + numWays; +parameter stq3_stq5_stp_err_offset = stq4_ex6_ldp_err_offset + numWays; +parameter stq4_stq6_stp_err_offset = stq3_stq5_stp_err_offset + numWays; +parameter stq4_stq5_stp_err_offset = stq4_stq6_stp_err_offset + numWays; +parameter stq4_clr_lck_way_offset = stq4_stq5_stp_err_offset + numWays; +parameter stq4_way_upd_offset = stq4_clr_lck_way_offset + numWays; +parameter stq5_way_upd_offset = stq4_way_upd_offset + numWays; +parameter stq6_way_upd_offset = stq5_way_upd_offset + numWays; +parameter stq7_way_upd_offset = stq6_way_upd_offset + numWays; +parameter stq4_rel_way_clr_offset = stq7_way_upd_offset + numWays; +parameter ex4_cache_acc_offset = stq4_rel_way_clr_offset + numWays; +parameter ex5_cache_acc_offset = ex4_cache_acc_offset + 1; +parameter ex5_mhit_cacc_offset = ex5_cache_acc_offset + 1; +parameter ex4_pfetch_val_offset = ex5_mhit_cacc_offset + 1; +parameter ex3_binv_val_offset = ex4_pfetch_val_offset + 1; +parameter ex4_binv_val_offset = ex3_binv_val_offset + 1; +parameter ex5_binv_val_offset = ex4_binv_val_offset + 1; +parameter ex3_thrd_id_offset = ex5_binv_val_offset + 1; +parameter ex4_thrd_id_offset = ex3_thrd_id_offset + `THREADS; +parameter ex5_thrd_id_offset = ex4_thrd_id_offset + `THREADS; +parameter ex4_lock_set_offset = ex5_thrd_id_offset + `THREADS; +parameter ex5_lock_set_offset = ex4_lock_set_offset + 1; +parameter ex4_watch_set_offset = ex5_lock_set_offset + 1; +parameter ex5_watch_set_offset = ex4_watch_set_offset + 1; +parameter ex6_watch_set_offset = ex5_watch_set_offset + 1; +parameter ex4_larx_val_offset = ex6_watch_set_offset + 1; +parameter ex7_watch_set_inval_offset = ex4_larx_val_offset + 1; +parameter ex5_lose_watch_offset = ex7_watch_set_inval_offset + 1; +parameter ex4_xuop_upd_val_offset = ex5_lose_watch_offset+ 1; +parameter ex5_xuop_upd_val_offset = ex4_xuop_upd_val_offset + 1; +parameter binv5_ex5_dir_val_offset = ex5_xuop_upd_val_offset + 1; +parameter ex5_way_hit_offset = binv5_ex5_dir_val_offset + 1; +parameter ex3_congr_cl_offset = ex5_way_hit_offset + numWays; +parameter ex4_congr_cl_offset = ex3_congr_cl_offset + (lwrCClassBit-uprCClassBit+1); +parameter ex5_congr_cl_offset = ex4_congr_cl_offset + (lwrCClassBit-uprCClassBit+1); +parameter ex5_cr_watch_offset = ex5_congr_cl_offset + (lwrCClassBit-uprCClassBit+1); +parameter congr_cl_ex3_ex4_cmp_offset = ex5_cr_watch_offset + 1; +parameter congr_cl_ex3_ex5_cmp_offset = congr_cl_ex3_ex4_cmp_offset + 1; +parameter congr_cl_ex3_ex6_cmp_offset = congr_cl_ex3_ex5_cmp_offset + 1; +parameter congr_cl_ex3_stq4_cmp_offset = congr_cl_ex3_ex6_cmp_offset + 1; +parameter congr_cl_ex3_stq5_cmp_offset = congr_cl_ex3_stq4_cmp_offset + 1; +parameter congr_cl_ex4_ex5_cmp_offset = congr_cl_ex3_stq5_cmp_offset + 1; +parameter congr_cl_ex4_ex6_cmp_offset = congr_cl_ex4_ex5_cmp_offset + 1; +parameter congr_cl_ex5_ex6_cmp_offset = congr_cl_ex4_ex6_cmp_offset + 1; +parameter congr_cl_ex5_ex7_cmp_offset = congr_cl_ex5_ex6_cmp_offset + 1; +parameter congr_cl_ex5_stq5_cmp_offset = congr_cl_ex5_ex7_cmp_offset + 1; +parameter congr_cl_ex5_stq6_cmp_offset = congr_cl_ex5_stq5_cmp_offset + 1; +parameter congr_cl_ex5_stq7_cmp_offset = congr_cl_ex5_stq6_cmp_offset + 1; +parameter congr_cl_ex4_ex6_rest_offset = congr_cl_ex5_stq7_cmp_offset + 1; +parameter ex5_cClass_lock_set_offset = congr_cl_ex4_ex6_rest_offset + 1; +parameter ex5_cClass_thrd_watch_offset = ex5_cClass_lock_set_offset + 1; +parameter ex5_dir_multihit_val_b_offset = ex5_cClass_thrd_watch_offset + `THREADS; +parameter ex5_err_det_way_offset = ex5_dir_multihit_val_b_offset + 1; +parameter ex5_perr_lock_lost_offset = ex5_err_det_way_offset + 8; +parameter ex5_perr_watchlost_offset = ex5_perr_lock_lost_offset + 1; +parameter ex5_dir_perr_det_offset = ex5_perr_watchlost_offset + `THREADS; +parameter ex5_dc_perr_det_offset = ex5_dir_perr_det_offset + 1; +parameter ex5_dir_perr_flush_offset = ex5_dc_perr_det_offset + 1; +parameter ex5_dc_perr_flush_offset = ex5_dir_perr_flush_offset + 1; +parameter ex5_way_perr_det_offset = ex5_dc_perr_flush_offset + 1; +parameter ex4_stq2_congr_cl_m_offset = ex5_way_perr_det_offset + 1; +parameter ex4_stq3_set_rel_coll_offset = ex4_stq2_congr_cl_m_offset + 1; +parameter ex4_stq4_set_rel_coll_offset = ex4_stq3_set_rel_coll_offset + 1; +parameter binv6_ex6_dir_data_offset = ex4_stq4_set_rel_coll_offset + 1; +parameter binv7_ex7_dir_data_offset = binv6_ex6_dir_data_offset + (dirState-1); +parameter stq6_dir_data_offset = binv7_ex7_dir_data_offset + (dirState-1); +parameter stq7_dir_data_offset = stq6_dir_data_offset + (dirState-1); +parameter stq2_ci_offset = stq7_dir_data_offset + (dirState-1); +parameter stq2_cen_acc_offset = stq2_ci_offset + 1; +parameter stq2_val_offset = stq2_cen_acc_offset + 1; +parameter stq3_val_offset = stq2_val_offset + 1; +parameter stq4_val_offset = stq3_val_offset + 1; +parameter stq2_dci_val_offset = stq4_val_offset + 1; +parameter stq3_dci_val_offset = stq2_dci_val_offset + 1; +parameter stq4_dci_val_offset = stq3_dci_val_offset + 1; +parameter stq2_thrd_id_offset = stq4_dci_val_offset + 1; +parameter stq3_thrd_id_offset = stq2_thrd_id_offset + `THREADS; +parameter stq4_thrd_id_offset = stq3_thrd_id_offset + `THREADS; +parameter rel2_thrd_id_offset = stq4_thrd_id_offset + `THREADS; +parameter rel3_thrd_id_offset = rel2_thrd_id_offset + `THREADS; +parameter stq2_lock_clr_offset = rel3_thrd_id_offset + `THREADS; +parameter stq3_lock_clr_offset = stq2_lock_clr_offset + 1; +parameter stq2_watch_clr_offset = stq3_lock_clr_offset + 1; +parameter stq3_watch_clr_offset = stq2_watch_clr_offset + 1; +parameter stq2_store_val_offset = stq3_watch_clr_offset + 1; +parameter stq3_store_val_offset = stq2_store_val_offset + 1; +parameter stq2_l_fld_b1_offset = stq3_store_val_offset + 1; +parameter stq3_l_fld_b1_offset = stq2_l_fld_b1_offset + 1; +parameter stq4_l_fld_b1_offset = stq3_l_fld_b1_offset + 1; +parameter stq2_inval_op_offset = stq4_l_fld_b1_offset + 1; +parameter stq3_inval_op_offset = stq2_inval_op_offset + 1; +parameter stq2_watch_clr_all_offset = stq3_inval_op_offset + 1; +parameter stq3_watch_clr_all_offset = stq2_watch_clr_all_offset + 1; +parameter stq4_watch_clr_all_offset = stq3_watch_clr_all_offset + 1; +parameter stq2_congr_cl_offset = stq4_watch_clr_all_offset + 1; +parameter stq3_congr_cl_offset = stq2_congr_cl_offset + (lwrCClassBit-uprCClassBit+1); +parameter stq4_congr_cl_offset = stq3_congr_cl_offset + (lwrCClassBit-uprCClassBit+1); +parameter stq5_congr_cl_offset = stq4_congr_cl_offset + (lwrCClassBit-uprCClassBit+1); +parameter stq6_congr_cl_offset = stq5_congr_cl_offset + (lwrCClassBit-uprCClassBit+1); +parameter rel2_clr_stg_val_offset = stq6_congr_cl_offset + (lwrCClassBit-uprCClassBit+1); +parameter rel3_clr_stg_val_offset = rel2_clr_stg_val_offset + 1; +parameter rel4_clr_stg_val_offset = rel3_clr_stg_val_offset + 1; +parameter rel5_clr_stg_val_offset = rel4_clr_stg_val_offset + 1; +parameter rel3_set_dir_val_offset = rel5_clr_stg_val_offset + 1; +parameter rel4_set_dir_val_offset = rel3_set_dir_val_offset + 1; +parameter rel2_set_stg_val_offset = rel4_set_dir_val_offset + 1; +parameter rel3_set_stg_val_offset = rel2_set_stg_val_offset + 1; +parameter rel2_back_inv_offset = rel3_set_stg_val_offset + 1; +parameter rel3_back_inv_offset = rel2_back_inv_offset + 1; +parameter rel3_upd_val_offset = rel3_back_inv_offset + 1; +parameter rel2_lock_set_offset = rel3_upd_val_offset + 1; +parameter rel3_lock_set_offset = rel2_lock_set_offset + 1; +parameter rel3_lock_pipe_offset = rel3_lock_set_offset + 1; +parameter rel2_watch_set_offset = rel3_lock_pipe_offset + 1; +parameter rel3_watch_set_offset = rel2_watch_set_offset + 1; +parameter rel3_watch_pipe_offset = rel3_watch_set_offset + 1; +parameter stq3_dir_upd_val_offset = rel3_watch_pipe_offset + 1; +parameter stq4_dir_upd_val_offset = stq3_dir_upd_val_offset + 1; +parameter stq3_rel3_val_offset = stq4_dir_upd_val_offset + 1; +parameter stq4_rel4_val_offset = stq3_rel3_val_offset + 1; +parameter stq4_lose_watch_offset = stq4_rel4_val_offset + 1; +parameter stq4_way_hit_offset = stq4_lose_watch_offset + 1; +parameter congr_cl_stq2_stq3_cmp_offset = stq4_way_hit_offset + numWays; +parameter congr_cl_stq2_stq4_cmp_offset = congr_cl_stq2_stq3_cmp_offset + 1; +parameter congr_cl_stq2_stq5_cmp_offset = congr_cl_stq2_stq4_cmp_offset + 1; +parameter congr_cl_stq3_stq4_cmp_offset = congr_cl_stq2_stq5_cmp_offset + 1; +parameter congr_cl_stq2_ex5_cmp_offset = congr_cl_stq3_stq4_cmp_offset + 1; +parameter congr_cl_stq2_ex6_cmp_offset = congr_cl_stq2_ex5_cmp_offset + 1; +parameter congr_cl_stq3_ex6_cmp_offset = congr_cl_stq2_ex6_cmp_offset + 1; +parameter congr_cl_stq3_ex5_cmp_offset = congr_cl_stq3_ex6_cmp_offset + 1; +parameter congr_cl_stq4_ex5_cmp_offset = congr_cl_stq3_ex5_cmp_offset + 1; +parameter stq4_cClass_lock_set_offset = congr_cl_stq4_ex5_cmp_offset + 1; +parameter stq4_cClass_thrd_watch_offset = stq4_cClass_lock_set_offset + 1; +parameter rel4_all_watch_lost_offset = stq4_cClass_thrd_watch_offset + `THREADS; +parameter lost_watch_evict_ovl_offset = rel4_all_watch_lost_offset + `THREADS; +parameter stq4_dir_multihit_val_b_offset = lost_watch_evict_ovl_offset + `THREADS; +parameter stq4_err_det_way_offset = stq4_dir_multihit_val_b_offset + 1; +parameter stq4_perr_lock_lost_offset = stq4_err_det_way_offset + numWays; +parameter stq4_perr_watchlost_offset = stq4_perr_lock_lost_offset + 1; +parameter stq4_dir_perr_det_offset = stq4_perr_watchlost_offset + `THREADS; +parameter stq5_way_perr_inval_offset = stq4_dir_perr_det_offset + 1; +parameter stq5_dir_err_val_offset = stq5_way_perr_inval_offset + numWays; +parameter ex5_stp_perr_flush_offset = stq5_dir_err_val_offset + 1; +parameter stm_watchlost_state_offset = ex5_stp_perr_flush_offset + 1; +parameter p0_wren_offset = stm_watchlost_state_offset + `THREADS; +parameter p0_wren_cpy_offset = p0_wren_offset + 1; +parameter p0_wren_stg_offset = p0_wren_cpy_offset + 1; +parameter p1_wren_offset = p0_wren_stg_offset + 1; +parameter p1_wren_cpy_offset = p1_wren_offset + 1; +parameter stq6_wren_offset = p1_wren_cpy_offset + 1; +parameter stq7_wren_offset = stq6_wren_offset + 1; +parameter congr_cl_all_act_offset = stq7_wren_offset + 1; +parameter spr_xucr0_clfc_offset = congr_cl_all_act_offset + 1; +parameter lock_finval_offset = spr_xucr0_clfc_offset + 1; +parameter val_finval_offset = lock_finval_offset + 1; +parameter watch_finval_offset = val_finval_offset + 1; +parameter inj_dirmultihit_ldp_offset = watch_finval_offset + `THREADS; +parameter inj_dirmultihit_stp_offset = inj_dirmultihit_ldp_offset + 1; +parameter xucr0_cslc_xuop_offset = inj_dirmultihit_stp_offset + 1; +parameter xucr0_cslc_binv_offset = xucr0_cslc_xuop_offset + 1; +parameter lost_watch_inter_thrd_offset = xucr0_cslc_binv_offset + 1; +parameter lost_watch_evict_val_offset = lost_watch_inter_thrd_offset + `THREADS; +parameter lost_watch_binv_offset = lost_watch_evict_val_offset + `THREADS; +parameter scan_right = lost_watch_binv_offset + `THREADS - 1; +parameter numScanChains = scan_right/1248; + +wire tiup; +wire [0:scan_right] siv; +wire [0:scan_right] sov; +(* analysis_not_referenced="true" *) +wire unused; + +//!! Bugspray Include: lq_dir_val +assign tiup = 1'b1; +assign unused = dcc_dir_ex3_watch_chk; + +// #################################################### +// Inputs +// #################################################### +assign spr_xucr0_clfc_d = xu_lq_spr_xucr0_clfc; +assign val_finval_d = stq4_dci_val_q; +assign lock_finval_d = stq4_dci_val_q | spr_xucr0_clfc_q; +assign watch_finval_d = stq4_dci_watch_lost | (stq4_watch_clr_all & {`THREADS{stq4_val_q}}); +assign inj_dirmultihit_ldp_d = pc_lq_inj_dcachedir_ldp_multihit; +assign inj_dirmultihit_stp_d = pc_lq_inj_dcachedir_stp_multihit; + +assign rel_way_clr = {rel_way_clr_a, rel_way_clr_b, rel_way_clr_c, rel_way_clr_d, rel_way_clr_e, rel_way_clr_f, rel_way_clr_g, rel_way_clr_h}; +assign rel_way_set = {rel_way_wen_a, rel_way_wen_b, rel_way_wen_c, rel_way_wen_d, rel_way_wen_e, rel_way_wen_f, rel_way_wen_g, rel_way_wen_h}; +assign ex4_way_cmp = {ex4_way_cmp_a, ex4_way_cmp_b, ex4_way_cmp_c, ex4_way_cmp_d, ex4_way_cmp_e, ex4_way_cmp_f, ex4_way_cmp_g, ex4_way_cmp_h}; +assign stq3_way_cmp = {stq3_way_cmp_a, stq3_way_cmp_b, stq3_way_cmp_c, stq3_way_cmp_d, stq3_way_cmp_e, stq3_way_cmp_f, stq3_way_cmp_g, stq3_way_cmp_h}; + +// #################################################### +// Execution Pipe Control +// Port0 => Execution Pipe or Back-Invalidate +// #################################################### + +// Execution and Back-Invalidate Pipeline Staging +assign ex4_cache_acc_d = dcc_dir_ex3_cache_acc & ~fgen_ex3_stg_flush; +assign ex5_cache_acc_d = ex4_cache_acc_q & ~fgen_ex4_stg_flush; +assign ex5_mhit_cacc_d = ex4_cache_acc_q & ~fgen_ex4_cp_flush; +assign ex4_pfetch_val_d = dcc_dir_ex3_pfetch_val; +assign ex4_cache_en_val = (ex4_cache_acc_q | ex4_pfetch_val_q) & ~derat_dir_ex4_wimge_i; +assign ex3_binv_val_d = dcc_dir_ex2_binv_val & ~spr_xucr0_dcdis; +assign ex4_binv_val_d = ex3_binv_val_q; +assign ex5_binv_val_d = ex4_binv_val_q; +assign ex2_thrd_id = dcc_dir_ex2_thrd_id; +assign ex3_thrd_id_d = ex2_thrd_id; +assign ex4_thrd_id_d = ex3_thrd_id_q; +assign ex5_thrd_id_d = ex4_thrd_id_q; +assign ex2_congr_cl = ex2_eff_addr; +assign ex3_congr_cl_d = ex2_congr_cl; +assign ex4_congr_cl_d = ex3_congr_cl_q; +assign ex5_congr_cl_d = ex4_congr_cl_q; +assign ex4_dcarr_perr_way = dat_ctl_dcarr_perr_way & {numWays{dcc_dir_ex4_load_val}}; +assign stq6_dcarr_perr_way = dat_ctl_dcarr_perr_way & {numWays{dcc_dir_stq6_store_val}}; +assign ex4_perr_way = ex4_tag_perr_way | ex4_dcarr_perr_way; + +assign ex3_lock_set = dcc_dir_ex3_lock_set & dcc_dir_ex3_th_c; +assign ex4_lock_set_d = ex3_lock_set & ~fgen_ex3_stg_flush; +assign ex5_lock_set_d = ex4_lock_set_q & ~fgen_ex4_stg_flush; +assign ex4_watch_set_d = dcc_dir_ex3_watch_set & ~fgen_ex3_stg_flush; +assign ex5_watch_set_d = ex4_watch_set_q & ~fgen_ex4_stg_flush; +assign ex6_watch_set_d = ex5_watch_set_q & ~fgen_ex5_stg_flush; +assign ex4_larx_val_d = dcc_dir_ex3_larx_val & ~fgen_ex3_stg_flush; +assign ex7_watch_set_inval_d = ex6_watch_set_q & congr_cl_stq3_ex6_cmp_q; + +// Clear Watch Bit on an invalidate type op or WCLR +assign ex4_clr_watch = ex4_clr_val_way; +assign ex4_set_watch = ex4_thrd_id_q & {`THREADS{ex4_watch_set_q}}; +assign ex5_lose_watch_d = ex4_clr_watch; + +assign ex4_clr_val_way = ex4_larx_val_q | ex4_binv_val_q; +assign ex4_xuop_upd_val_d = (ex3_lock_set | dcc_dir_ex3_watch_set | dcc_dir_ex3_larx_val) & ~fgen_ex3_stg_flush; +assign ex4_xuop_upd_val = ex4_xuop_upd_val_q & ex4_cache_en_val & ~spr_xucr0_dcdis; +assign ex5_xuop_upd_val_d = ex4_xuop_upd_val & ~fgen_ex4_stg_flush; +assign ex5_xuop_upd_val = ex5_xuop_upd_val_q & ~fgen_ex5_stg_flush; + +assign binv4_ex4_xuop_upd = ex4_binv_val_q | ex4_xuop_upd_val; +assign binv4_ex4_dir_val = ex4_binv_val_q | ex4_cache_acc_q | ex4_pfetch_val_q; +assign binv5_ex5_dir_val_d = ex4_binv_val_q | (ex4_cache_acc_q & ~fgen_ex4_cp_flush) | ex4_pfetch_val_q; +assign inj_dirmultihit_ldp_b = ~(inj_dirmultihit_ldp_q & binv4_ex4_dir_val); + +assign ex5_way_hit_d = ex4_way_hit; + +// #################################################### +// Execution Pipe Directory Read +// #################################################### +// 1-hot Congruence Class Select +generate begin : ldpCClass + genvar cclass; + for (cclass=0; cclass Reload or Commit +// #################################################### + +// Store Commit Pipeline Staging +assign stq2_ci_d = lsq_ctl_stq1_ci; +assign stq2_cen_acc_d = lsq_ctl_stq1_lock_clr | (lsq_ctl_stq1_watch_clr & lsq_ctl_stq1_l_fld[0]) | lsq_ctl_stq1_store_val; +assign stq2_cen_acc = stq2_cen_acc_q & ~stq2_ci_q; +assign stq2_dci_val_d = lsq_ctl_stq1_dci_val; +assign stq3_dci_val_d = stq2_val_q & stq2_dci_val_q & ~lsq_ctl_stq2_blk_req; +assign stq4_dci_val_d = stq3_dci_val_q; +assign stq2_val_d = lsq_ctl_stq1_val; +assign stq2_val = stq2_val_q & (stq2_cen_acc | stq2_inval_op_q | stq2_watch_clr_all_q | stq2_dci_val_q) & ~(lsq_ctl_stq2_blk_req | spr_xucr0_dcdis); +assign stq3_val_d = stq2_val; +assign stq4_val_d = stq3_val_q; +assign stq2_thrd_id_d = lsq_ctl_stq1_thrd_id; +assign stq3_thrd_id_d = stq2_thrd_id_q; +assign stq4_thrd_id_d = stq3_thrd_id_q; +assign rel2_thrd_id_d = lsq_ctl_rel1_thrd_id; +assign rel3_thrd_id_d = rel2_thrd_id_q; +assign stq2_lock_clr_d = lsq_ctl_stq1_lock_clr; +assign stq3_lock_clr_d = stq2_lock_clr_q & stq2_val; +assign stq2_watch_clr_d = lsq_ctl_stq1_watch_clr & lsq_ctl_stq1_l_fld[0]; +assign stq3_watch_clr_d = stq2_watch_clr_q & stq2_val; +assign stq2_store_val_d = lsq_ctl_stq1_store_val; +assign stq3_store_val_d = stq2_store_val_q & stq2_val; + +// Cacheline Invalidate type instructions, still invalidate if I=1 +assign stq2_inval_op_d = lsq_ctl_stq1_inval; +assign stq3_inval_op_d = stq2_inval_op_q & stq2_val; + +// Watch Clear All updates STM_WATCHLOST indicator if DCDIS, +// but does not update the watch bits in the directory +assign stq1_watch_clr_all = lsq_ctl_stq1_watch_clr & (~lsq_ctl_stq1_l_fld[0]); +assign stq2_watch_clr_all_d = stq1_watch_clr_all; +assign stq3_watch_clr_all_d = stq2_watch_clr_all_q & stq2_val_q & ~lsq_ctl_stq2_blk_req; +assign stq4_watch_clr_all_d = stq3_watch_clr_all_q; +assign stq2_l_fld_b1_d = lsq_ctl_stq1_l_fld[1]; +assign stq3_l_fld_b1_d = stq2_l_fld_b1_q; +assign stq4_l_fld_b1_d = stq3_l_fld_b1_q; +assign inj_dirmultihit_stp_b = ~(inj_dirmultihit_stp_q & stq3_dir_upd_val_q); + +generate + if (`CL_SIZE == 6) begin : cl64size + assign stq1_congr_cl[uprCClassBit:lwrCClassBit - 1] = lsq_ctl_stq1_addr[uprCClassBit:lwrCClassBit - 1]; + assign stq1_congr_cl[lwrCClassBit] = lsq_ctl_stq1_addr[lwrCClassBit] | spr_xucr0_cls; + end +endgenerate + +generate + if (`CL_SIZE == 7) begin : cl128size + assign stq1_congr_cl = lsq_ctl_stq1_addr; + end +endgenerate + +assign stq2_congr_cl_d = stq1_congr_cl; +assign stq3_congr_cl_d = stq2_congr_cl_q; +assign stq4_congr_cl_d = stq3_congr_cl_q; +assign stq5_congr_cl_d = stq4_congr_cl_q; +assign stq6_congr_cl_d = stq5_congr_cl_q; + +// Reload Pipeline Staging +assign rel2_clr_stg_val_d = lsq_ctl_rel1_clr_val & ~spr_xucr0_dcdis; +assign rel2_clr_stg_val = rel2_clr_stg_val_q & ~lsq_ctl_rel2_blk_req; +assign rel3_clr_stg_val_d = rel2_clr_stg_val; +assign rel4_clr_stg_val_d = rel3_clr_stg_val_q; +assign rel5_clr_stg_val_d = rel4_clr_stg_val_q; +assign rel2_set_stg_val_d = lsq_ctl_rel1_set_val & ~spr_xucr0_dcdis; +assign rel2_set_dir_val = rel2_set_stg_val_q & lsq_ctl_rel2_upd_val & ~(lsq_ctl_rel2_blk_req | rel2_back_inv_q); +assign rel3_set_dir_val_d = rel2_set_dir_val; +assign rel4_set_dir_val_d = rel3_set_dir_val_q; +assign rel3_set_stg_val_d = rel2_set_stg_val_q & ~lsq_ctl_rel2_blk_req; +assign rel2_back_inv_d = lsq_ctl_rel1_back_inv; +assign rel3_back_inv_d = rel2_back_inv_q; +assign rel3_upd_val_d = lsq_ctl_rel2_upd_val; +assign rel2_lock_set_d = lsq_ctl_rel1_lock_set; +assign rel3_lock_set_d = rel2_lock_set_q & rel2_set_stg_val_q & ~lsq_ctl_rel2_blk_req; +assign rel3_lock_pipe_d = rel2_lock_set_q; +assign rel2_watch_set_d = lsq_ctl_rel1_watch_set; +assign rel3_watch_set_d = rel2_watch_set_q & rel2_set_stg_val_q & ~lsq_ctl_rel2_blk_req; +assign rel3_watch_pipe_d = rel2_watch_set_q; + +// COMMIT/Reload Pipe Update Valid +assign stq2_dir_upd_val = stq2_val_q & (stq2_cen_acc | stq2_inval_op_q) & ~(lsq_ctl_stq2_blk_req | spr_xucr0_dcdis); +assign stq3_dir_upd_val_d = stq2_dir_upd_val; +assign stq4_dir_upd_val_d = stq3_dir_upd_val_q; +// removed rel2_set_dir_val, moved dir tag update to the set stage, was getting stale +// tag hits when bypassing rel_set_dir stages to stq2 commit stage before the directory +// was updated +assign stq3_rel3_val_d = stq2_dir_upd_val | rel2_clr_stg_val; +assign stq4_rel4_val_d = stq3_rel3_val_q; + +assign stq3_clr_lock = stq3_inval_op_q | stq3_lock_clr_q; +assign rel3_set_watch = rel3_thrd_id_q & {`THREADS{rel3_watch_set_q}}; +assign stq4_lose_watch_d = stq3_inval_op_q & stq3_dir_upd_val_q; +assign stq3_store_clr_watch = ~stq3_thrd_id_q & {`THREADS{stq3_store_val_q}}; +assign stq3_wclr_clr_watch = stq3_thrd_id_q & {`THREADS{stq3_watch_clr_q}}; +assign stq3_inval_clr_watch = {`THREADS{stq3_inval_op_q}}; +assign stq3_clr_watch = stq3_store_clr_watch | stq3_wclr_clr_watch | stq3_inval_clr_watch; +assign stq4_way_hit_d = stq3_way_hit; + +// #################################################### +// Reload Pipe Directory Read +// #################################################### +// 1-hot Congruence Class Select +generate begin : stpCClass + genvar cclass; + for (cclass=0; cclass updated the following cycle of the first beat, +// need to invalidate the way that will be overwritten +// 2) Reload -> updated on the last data beat when no ECC error was detected, +// the Way will be validated that was replaced +// 3) Back-Invalidate -> updated the following cycle +// 4) DCBF -> Updated in ex5 +// 5) DCBI -> Updated in ex5 +// 6) DCBZ -> Updated in ex5 +// 7) LWARX Hit Invalidate -> Updated in ex5 +// 8) STWCX Hit Invalidate -> Updated in ex5 +// +// Lock Bits are updated for the following operations +// 1) Reload -> updated the following cycle of the first beat, +// need to clear the lock bit for the way that will be overwritten +// 2) Reload -> updated on the last data beat when no ECC error was detected, +// the Lock bit will be set that was replaced if originally a lock type op +// 3) Back-Invalidate -> will clear lock bit the following cycle +// 4) DCBF -> will clear lock bit in ex5 +// 5) DCBI -> will clear lock bit in ex5 +// 6) DCBZ -> will clear lock bit in ex5 +// 7) LWARX Hit Invalidate -> will clear lock bit in ex5 +// 8) STWCX Hit Invalidate -> will clear lock bit in ex5 +// 9) DCBLC -> will clear lock bit in ex5 +//10) DCBTLS/DCBTSTLS -> will set lock bit in ex5 if hit + +// Port0 Updates +// 1) XU Invalidate Op +// 2) BACK-INV Update +// 3) XU clear Lock Op +// 4) XU set Lock Op +assign p0_wren_d = ex5_xuop_upd_val | ex5_binv_val_q | ex5_way_err_val; +assign p0_wren_cpy_d = ex5_xuop_upd_val | ex5_binv_val_q | ex5_way_err_val; +assign p0_wren_stg_d = p0_wren_q; + +// Port1 Updates +// 1) RELOAD_CLR +// 2) RELOAD_SET +// 3) DC Array Parity Error with Loadhit followed by storehit update - need to invalidate storehit cline +assign p1_wren_d = stq4_rel4_val_q | rel4_set_dir_val_q; +assign p1_wren_cpy_d = stq4_rel4_val_q | rel4_set_dir_val_q; +assign stq6_wren_d = p1_wren_q; +assign stq7_wren_d = stq6_wren_q; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Table for selecting Ports data for +// updating to the same way and +// same congruence class +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// P0 P1 | PortSel +//------------------------------------------ +// binv2 relclr | P1 +// binv2 relset | P1 +// binv2 binv2 | P1 <- Impossible +// flush relclr | P1 +// flush relset | P1 +// flush binv2 | P1 <- FlushOp is flushed +// lckset relclr | P1 +// lckset relset | P1 +// lckset binv2 | P1 <- LockSetOp is flushed +// lckclr relclr | P1 +// lckclr relset | P1 +// lckclr binv2 | P1 <- LockClrOp is flushed + +// Act Pin to all Directory Latches +assign congr_cl_all_act_d = (stq4_watch_clr_all_q & stq4_val_q) | stq4_dci_val_q | spr_xucr0_clfc_q; + +generate begin : dirUpdCtrl + genvar cclass; + for (cclass=0; cclass Flush to ucode +// XUCR[FLSTA] = '1' => Flush to Alignment Interrupt +// XUCR[AFLSTA] = '0' => Flush to ucode (AXUop) +// XUCR[AFLSTA] = '1' => Flush to Alignment Interrupt (AXUop) +assign force_align_int_a = ex3_axu_op_val & (spr_xucr0_aflsta | ex3_ldst_fexcpt); +assign force_align_int_x = ~ex3_axu_op_val & spr_xucr0_flsta; +assign force_align_int = force_align_int_x | force_align_int_a | ex3_resv_instr | ex3_ldawx_instr | ex3_mword_instr; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// UCODE Memory Attributes Array +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +generate + if (`THREADS_POOL_ENC == 0) begin : tid1 + wire [0:`THREADS_POOL_ENC] ex0_i0_enc_tid; + wire [0:`THREADS_POOL_ENC] ex0_i1_enc_tid; + wire [0:`THREADS_POOL_ENC] ex3_enc_tid; + wire [0:`THREADS_POOL_ENC] ex4_enc_tid; + + assign ex0_i0_tid_ucode_cnt = ex0_i0_ucode_cnt; + assign ex0_i1_tid_ucode_cnt = ex0_i1_ucode_cnt; + assign ex3_tid_ucode_cnt = ex3_ucode_cnt; + assign ex4_tid_ucode_cnt = ex4_ucode_cnt_q; + assign ex0_i0_enc_tid[`THREADS_POOL_ENC:`THREADS_POOL_ENC] = tidn; + assign ex0_i1_enc_tid[`THREADS_POOL_ENC:`THREADS_POOL_ENC] = tidn; + assign ex3_enc_tid[`THREADS_POOL_ENC:`THREADS_POOL_ENC] = tidn; + assign ex4_enc_tid[`THREADS_POOL_ENC:`THREADS_POOL_ENC] = tidn; + + assign unused = ex0_i0_enc_tid[`THREADS_POOL_ENC] | ex0_i1_enc_tid[`THREADS_POOL_ENC] | ex3_enc_tid[`THREADS_POOL_ENC] | ex4_enc_tid[`THREADS_POOL_ENC]; + end +endgenerate + +generate + if (`THREADS_POOL_ENC > 0) begin : tidMulti + reg [0:`THREADS_POOL_ENC] ex0_i0_enc_tid; + reg [0:`THREADS_POOL_ENC] ex0_i1_enc_tid; + reg [0:`THREADS_POOL_ENC] ex3_enc_tid; + reg [0:`THREADS_POOL_ENC] ex4_enc_tid; + always @(*) begin: tidEnc + reg [0:`THREADS_POOL_ENC-1] i0Tid; + reg [0:`THREADS_POOL_ENC-1] i1Tid; + reg [0:`THREADS_POOL_ENC-1] ex3Tid; + reg [0:`THREADS_POOL_ENC-1] ex4Tid; + + //(* analysis_not_referenced="true" *) + + reg [0:31] tid; + i0Tid = {`THREADS_POOL_ENC{1'b0}}; + i1Tid = {`THREADS_POOL_ENC{1'b0}}; + ex3Tid = {`THREADS_POOL_ENC{1'b0}}; + ex4Tid = {`THREADS_POOL_ENC{1'b0}}; + ex0_i0_enc_tid[`THREADS_POOL_ENC:`THREADS_POOL_ENC] <= tidn; + ex0_i1_enc_tid[`THREADS_POOL_ENC:`THREADS_POOL_ENC] <= tidn; + ex3_enc_tid[`THREADS_POOL_ENC:`THREADS_POOL_ENC] <= tidn; + ex4_enc_tid[`THREADS_POOL_ENC:`THREADS_POOL_ENC] <= tidn; + for (tid=0; tid<`THREADS; tid=tid+1) begin + i0Tid = (tid[32-`THREADS_POOL_ENC:31] & {`THREADS_POOL_ENC{ex0_i0_vld[tid]}}) | i0Tid; + i1Tid = (tid[32-`THREADS_POOL_ENC:31] & {`THREADS_POOL_ENC{ex0_i1_vld[tid]}}) | i1Tid; + ex3Tid = (tid[32-`THREADS_POOL_ENC:31] & {`THREADS_POOL_ENC{ex3_thrd_id[tid]}}) | ex3Tid; + ex4Tid = (tid[32-`THREADS_POOL_ENC:31] & {`THREADS_POOL_ENC{ex4_thrd_id[tid]}}) | ex4Tid; + end + ex0_i0_enc_tid[0:`THREADS_POOL_ENC-1] <= i0Tid; + ex0_i1_enc_tid[0:`THREADS_POOL_ENC-1] <= i1Tid; + ex3_enc_tid[0:`THREADS_POOL_ENC-1] <= ex3Tid; + ex4_enc_tid[0:`THREADS_POOL_ENC-1] <= ex4Tid; + end + assign ex0_i0_tid_ucode_cnt = {ex0_i0_enc_tid[0:`THREADS_POOL_ENC-1], ex0_i0_ucode_cnt}; + assign ex0_i1_tid_ucode_cnt = {ex0_i1_enc_tid[0:`THREADS_POOL_ENC-1], ex0_i1_ucode_cnt}; + assign ex3_tid_ucode_cnt = {ex3_enc_tid[0:`THREADS_POOL_ENC-1], ex3_ucode_cnt}; + assign ex4_tid_ucode_cnt = {ex4_enc_tid[0:`THREADS_POOL_ENC-1], ex4_ucode_cnt_q}; + + assign unused = ex0_i0_enc_tid[`THREADS_POOL_ENC] | ex0_i1_enc_tid[`THREADS_POOL_ENC] | ex3_enc_tid[`THREADS_POOL_ENC] | ex4_enc_tid[`THREADS_POOL_ENC]; + end +endgenerate + +generate begin : memAttrQ + genvar ucodeEntry; + for (ucodeEntry=0; ucodeEntry program interrupts, these interrupts ignore any bad machine path errors detected by +// data cache, directory, and erat +// 2) mid priority interrupt ex4_excp_pri(7:11) => machine check enabled and bad machine path error detected by +// data cache, directory, or erat +// 3) mid priority interrupt ex4_excp_pri(12:14) => machine check enabled and bad machine path error detected by the MMU, these exceptions +// are gated if error detected by data cache, directory, or erat and machine check disabled for error +// 4) low priority interrupt ex4_excp_pri(15:25) => translation type interrupts, these exceptions are gated if error detected by +// data cache, directory, mmu, or erat and machine check disabled for error +assign ex5_exception_val = ex5_high_pri_excp_q | ex5_flush_req_mchk | (ex5_tlb_mchk_req_q & ~ex5_flush_req_int) | (ex5_low_pri_excp_q & ~(ex5_flush_req_int | ex5_tlb_flush_req_q)); +assign ex5_exception = ex5_exception_int; +assign ex5_dear_val = ex5_dear_val_q; +assign ex5_blk_tlb_req = ex5_high_pri_excp_q | ex5_flush_req_int; +assign fgen_ex4_stg_flush = ex4_cp_flush_val | ex4_n_flush_req | ex4_non_cp_next_excp | ex4_cp_next_excp_det; +assign fgen_ex5_stg_flush = ex5_cp_flush_val | ex5_local_flush | ex5_restart_val | ex5_dac_int_det_q; +assign ex5_flush_pfetch = dir_dcc_ex5_dir_perr_det | dir_dcc_ex5_dc_perr_det | dir_dcc_ex5_multihit_det | + ex5_derat_multihit_det_q | ex5_derat_perr_det_q | dir_dcc_stq4_dir_perr_det | + dir_dcc_stq4_multihit_det; +assign fgen_ex4_cp_flush = ex4_cp_flush_val; +assign fgen_ex5_cp_flush = ex5_cp_flush_val; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// FIR Error Reporting +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +assign perv_fir_rpt_d = {derat_fir_par_err, dir_dcc_ex5_dir_perr_det, dir_dcc_ex5_dc_perr_det, derat_fir_multihit, dir_dcc_ex5_multihit_det, dir_dcc_stq4_dir_perr_det, dir_dcc_stq4_multihit_det}; + +tri_direct_err_rpt #(.WIDTH(7)) pervFir( + .vd(vdd), + .gd(gnd), + .err_in(perv_fir_rpt_q), + .err_out(perv_fir_rpt) +); + +assign lq_pc_err_derat_parity = perv_fir_rpt[0]; +assign lq_pc_err_dir_ldp_parity = perv_fir_rpt[1]; +assign lq_pc_err_dcache_parity = perv_fir_rpt[2]; +assign lq_pc_err_derat_multihit = perv_fir_rpt[3]; +assign lq_pc_err_dir_ldp_multihit = perv_fir_rpt[4]; +assign lq_pc_err_dir_stp_parity = perv_fir_rpt[5]; +assign lq_pc_err_dir_stp_multihit = perv_fir_rpt[6]; + +// xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +// Performance Events +// xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +assign ex5_misalign_flush = ex5_misalign_flush_q; + +//xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +// Registers +//xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_valid_resv_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_valid_resv_offset]), + .scout(sov[ex4_valid_resv_offset]), + .din(ex4_valid_resv_d), + .dout(ex4_valid_resv_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_prealign_int_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_prealign_int_offset]), + .scout(sov[ex4_prealign_int_offset]), + .din(ex4_prealign_int_d), + .dout(ex4_prealign_int_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_flush_2ucode_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_flush_2ucode_offset]), + .scout(sov[ex4_flush_2ucode_offset]), + .din(ex4_flush_2ucode_d), + .dout(ex4_flush_2ucode_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_flush_2ucode_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_flush_2ucode_offset]), + .scout(sov[ex5_flush_2ucode_offset]), + .din(ex5_flush_2ucode_d), + .dout(ex5_flush_2ucode_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_ucode_dis_prog_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_ucode_dis_prog_offset]), + .scout(sov[ex4_ucode_dis_prog_offset]), + .din(ex4_ucode_dis_prog_d), + .dout(ex4_ucode_dis_prog_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_is_dcbz_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_is_dcbz_offset]), + .scout(sov[ex4_is_dcbz_offset]), + .din(ex4_is_dcbz_d), + .dout(ex4_is_dcbz_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_misalign_flush_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_misalign_flush_offset]), + .scout(sov[ex5_misalign_flush_offset]), + .din(ex5_misalign_flush_d), + .dout(ex5_misalign_flush_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_axu_ap_unavail_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_axu_ap_unavail_offset]), + .scout(sov[ex4_axu_ap_unavail_offset]), + .din(ex4_axu_ap_unavail_d), + .dout(ex4_axu_ap_unavail_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_axu_fp_unavail_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_axu_fp_unavail_offset]), + .scout(sov[ex4_axu_fp_unavail_offset]), + .din(ex4_axu_fp_unavail_d), + .dout(ex4_axu_fp_unavail_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_axu_spv_unavail_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_axu_spv_unavail_offset]), + .scout(sov[ex4_axu_spv_unavail_offset]), + .din(ex4_axu_spv_unavail_d), + .dout(ex4_axu_spv_unavail_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_local_flush_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_local_flush_offset]), + .scout(sov[ex5_local_flush_offset]), + .din(ex5_local_flush_d), + .dout(ex5_local_flush_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_tlb_flush_req_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_tlb_flush_req_offset]), + .scout(sov[ex5_tlb_flush_req_offset]), + .din(ex5_tlb_flush_req_d), + .dout(ex5_tlb_flush_req_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_tlb_mchk_req_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_tlb_mchk_req_offset]), + .scout(sov[ex5_tlb_mchk_req_offset]), + .din(ex5_tlb_mchk_req_d), + .dout(ex5_tlb_mchk_req_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_low_pri_excp_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_low_pri_excp_offset]), + .scout(sov[ex5_low_pri_excp_offset]), + .din(ex5_low_pri_excp_d), + .dout(ex5_low_pri_excp_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_high_pri_excp_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_high_pri_excp_offset]), + .scout(sov[ex5_high_pri_excp_offset]), + .din(ex5_high_pri_excp_d), + .dout(ex5_high_pri_excp_q) +); + +tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) ex5_exception_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_exception_offset:ex5_exception_offset + 6 - 1]), + .scout(sov[ex5_exception_offset:ex5_exception_offset + 6 - 1]), + .din(ex5_exception_d), + .dout(ex5_exception_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex5_dear_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_dear_val_offset:ex5_dear_val_offset + `THREADS - 1]), + .scout(sov[ex5_dear_val_offset:ex5_dear_val_offset + `THREADS - 1]), + .din(ex5_dear_val_d), + .dout(ex5_dear_val_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_derat_multihit_flush_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_derat_multihit_flush_offset]), + .scout(sov[ex5_derat_multihit_flush_offset]), + .din(ex5_derat_multihit_flush_d), + .dout(ex5_derat_multihit_flush_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_derat_multihit_det_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_derat_multihit_det_offset]), + .scout(sov[ex5_derat_multihit_det_offset]), + .din(ex5_derat_multihit_det_d), + .dout(ex5_derat_multihit_det_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_derat_perr_flush_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_derat_perr_flush_offset]), + .scout(sov[ex5_derat_perr_flush_offset]), + .din(ex5_derat_perr_flush_d), + .dout(ex5_derat_perr_flush_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_derat_perr_det_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_derat_perr_det_offset]), + .scout(sov[ex5_derat_perr_det_offset]), + .din(ex5_derat_perr_det_d), + .dout(ex5_derat_perr_det_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sfx_excpt_det_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_sfx_excpt_det_offset]), + .scout(sov[ex2_sfx_excpt_det_offset]), + .din(ex2_sfx_excpt_det_d), + .dout(ex2_sfx_excpt_det_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_sfx_excpt_det_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_sfx_excpt_det_offset]), + .scout(sov[ex3_sfx_excpt_det_offset]), + .din(ex3_sfx_excpt_det_d), + .dout(ex3_sfx_excpt_det_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_sfx_excpt_det_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_sfx_excpt_det_offset]), + .scout(sov[ex4_sfx_excpt_det_offset]), + .din(ex4_sfx_excpt_det_d), + .dout(ex4_sfx_excpt_det_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_priv_prog_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_priv_prog_offset]), + .scout(sov[ex2_priv_prog_offset]), + .din(ex2_priv_prog_d), + .dout(ex2_priv_prog_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_priv_prog_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_priv_prog_offset]), + .scout(sov[ex3_priv_prog_offset]), + .din(ex3_priv_prog_d), + .dout(ex3_priv_prog_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_priv_prog_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_priv_prog_offset]), + .scout(sov[ex4_priv_prog_offset]), + .din(ex4_priv_prog_d), + .dout(ex4_priv_prog_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_hypv_prog_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_hypv_prog_offset]), + .scout(sov[ex2_hypv_prog_offset]), + .din(ex2_hypv_prog_d), + .dout(ex2_hypv_prog_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_hypv_prog_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_hypv_prog_offset]), + .scout(sov[ex3_hypv_prog_offset]), + .din(ex3_hypv_prog_d), + .dout(ex3_hypv_prog_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_hypv_prog_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_hypv_prog_offset]), + .scout(sov[ex4_hypv_prog_offset]), + .din(ex4_hypv_prog_d), + .dout(ex4_hypv_prog_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_illeg_prog_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_illeg_prog_offset]), + .scout(sov[ex2_illeg_prog_offset]), + .din(ex2_illeg_prog_d), + .dout(ex2_illeg_prog_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_illeg_prog_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_illeg_prog_offset]), + .scout(sov[ex3_illeg_prog_offset]), + .din(ex3_illeg_prog_d), + .dout(ex3_illeg_prog_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_illeg_prog_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_illeg_prog_offset]), + .scout(sov[ex4_illeg_prog_offset]), + .din(ex4_illeg_prog_d), + .dout(ex4_illeg_prog_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_dlock_excp_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_dlock_excp_offset]), + .scout(sov[ex2_dlock_excp_offset]), + .din(ex2_dlock_excp_d), + .dout(ex2_dlock_excp_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_dlock_excp_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_dlock_excp_offset]), + .scout(sov[ex3_dlock_excp_offset]), + .din(ex3_dlock_excp_d), + .dout(ex3_dlock_excp_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_dlock_excp_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_dlock_excp_offset]), + .scout(sov[ex4_dlock_excp_offset]), + .din(ex4_dlock_excp_d), + .dout(ex4_dlock_excp_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ilock_excp_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_ilock_excp_offset]), + .scout(sov[ex2_ilock_excp_offset]), + .din(ex2_ilock_excp_d), + .dout(ex2_ilock_excp_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_ilock_excp_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_ilock_excp_offset]), + .scout(sov[ex3_ilock_excp_offset]), + .din(ex3_ilock_excp_d), + .dout(ex3_ilock_excp_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_ilock_excp_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_ilock_excp_offset]), + .scout(sov[ex4_ilock_excp_offset]), + .din(ex4_ilock_excp_d), + .dout(ex4_ilock_excp_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ehpriv_excp_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_ehpriv_excp_offset]), + .scout(sov[ex2_ehpriv_excp_offset]), + .din(ex2_ehpriv_excp_d), + .dout(ex2_ehpriv_excp_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_ehpriv_excp_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_ehpriv_excp_offset]), + .scout(sov[ex3_ehpriv_excp_offset]), + .din(ex3_ehpriv_excp_d), + .dout(ex3_ehpriv_excp_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_cache_acc_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_cache_acc_offset]), + .scout(sov[ex4_cache_acc_offset]), + .din(ex4_cache_acc_d), + .dout(ex4_cache_acc_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_ucode_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_ucode_val_offset]), + .scout(sov[ex4_ucode_val_offset]), + .din(ex4_ucode_val_d), + .dout(ex4_ucode_val_q) +); + +tri_rlmreg_p #(.WIDTH(`UCODE_ENTRIES_ENC), .INIT(0), .NEEDS_SRESET(1)) ex4_ucode_cnt_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex3_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_ucode_cnt_offset:ex4_ucode_cnt_offset + `UCODE_ENTRIES_ENC - 1]), + .scout(sov[ex4_ucode_cnt_offset:ex4_ucode_cnt_offset + `UCODE_ENTRIES_ENC - 1]), + .din(ex4_ucode_cnt_d), + .dout(ex4_ucode_cnt_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_wNComp_rcvd_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_wNComp_rcvd_offset]), + .scout(sov[ex5_wNComp_rcvd_offset]), + .din(ex5_wNComp_rcvd_d), + .dout(ex5_wNComp_rcvd_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_wNComp_excp_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_wNComp_excp_offset]), + .scout(sov[ex6_wNComp_excp_offset]), + .din(ex6_wNComp_excp_d), + .dout(ex6_wNComp_excp_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_dac_int_det_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_dac_int_det_offset]), + .scout(sov[ex5_dac_int_det_offset]), + .din(ex5_dac_int_det_d), + .dout(ex5_dac_int_det_q) +); + +tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(1)) perv_fir_rpt_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[perv_fir_rpt_offset:perv_fir_rpt_offset + 7 - 1]), + .scout(sov[perv_fir_rpt_offset:perv_fir_rpt_offset + 7 - 1]), + .din(perv_fir_rpt_d), + .dout(perv_fir_rpt_q) +); + +tri_rlmreg_p #(.WIDTH(UCODEDEPTH), .INIT(0), .NEEDS_SRESET(1)) ucode_cnt_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ucode_cnt_val_offset:ucode_cnt_val_offset + UCODEDEPTH - 1]), + .scout(sov[ucode_cnt_val_offset:ucode_cnt_val_offset + UCODEDEPTH - 1]), + .din(ucode_cnt_val_d), + .dout(ucode_cnt_val_q) +); + +tri_rlmreg_p #(.WIDTH(UCODEDEPTH), .INIT(0), .NEEDS_SRESET(1)) ucode_cnt_2ucode_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ucode_cnt_2ucode_offset:ucode_cnt_2ucode_offset + UCODEDEPTH - 1]), + .scout(sov[ucode_cnt_2ucode_offset:ucode_cnt_2ucode_offset + UCODEDEPTH - 1]), + .din(ucode_cnt_2ucode_d), + .dout(ucode_cnt_2ucode_q) +); + +generate begin : ucode_cnt_memAttr + genvar ucodeEntry; + for (ucodeEntry=0; ucodeEntry 16K L1D$, 15 => 32K L1D$ +//parameter `CL_SIZE = 6; // 6 => 64B CLINE, 7 => 128B CLINE +//parameter `REAL_IFAR_WIDTH = 42; // real addressing bits + +// RV1 RV Issue Valid +input [0:`THREADS-1] rv_lq_vld; +input rv_lq_isLoad; + +// RV is empty indicator +input [0:`THREADS-1] rv_lq_rvs_empty; + +// SPR Directory Read Valid +input ctl_lsq_rv1_dir_rd_val; + +// Back-Invalidate Valid +input l2_back_inv_val; +input [64-`REAL_IFAR_WIDTH:63-`CL_SIZE] l2_back_inv_addr; + +// Load Request Interface +input ctl_lsq_ex3_ldreq_val; +input ctl_lsq_ex3_pfetch_val; +input ctl_lsq_ex4_ldreq_val; +input ctl_lsq_ex4_streq_val; +input ctl_lsq_ex4_othreq_val; +input [64-`REAL_IFAR_WIDTH:63] ctl_lsq_ex4_p_addr; +input [0:`ITAG_SIZE_ENC-1] ctl_lsq_ex4_itag; +input ctl_lsq_ex4_dReq_val; +input ctl_lsq_ex4_gath_load; +input [0:4] ctl_lsq_ex4_wimge; +input ctl_lsq_ex4_is_sync; +input ctl_lsq_ex4_all_thrd_chk; +input ctl_lsq_ex4_byte_swap; +input ctl_lsq_ex4_is_resv; +input [0:`THREADS-1] ctl_lsq_ex4_thrd_id; +input ctl_lsq_ex5_lock_set; +input ctl_lsq_ex5_watch_set; +input [0:`THREADS-1] ctl_lsq_ex5_thrd_id; +input ctl_lsq_ex5_load_hit; +input [0:2] ctl_lsq_ex5_opsize; +input [0:`AXU_SPARE_ENC+`GPR_POOL_ENC+`THREADS_POOL_ENC-1] ctl_lsq_ex5_tgpr; +input ctl_lsq_ex5_axu_val; // XU,AXU type operation +input [0:3] ctl_lsq_ex5_usr_def; +input ctl_lsq_ex5_drop_rel; // L2 only instructions +input ctl_lsq_ex5_flush_req; // Flush request from LDQ/STQ +input ctl_lsq_ex5_flush_pfetch; // Flush Prefetch in EX5 +input [0:10] ctl_lsq_ex5_cmmt_events; +input ctl_lsq_ex5_perf_val0; +input [0:3] ctl_lsq_ex5_perf_sel0; +input ctl_lsq_ex5_perf_val1; +input [0:3] ctl_lsq_ex5_perf_sel1; +input ctl_lsq_ex5_perf_val2; +input [0:3] ctl_lsq_ex5_perf_sel2; +input ctl_lsq_ex5_perf_val3; +input [0:3] ctl_lsq_ex5_perf_sel3; +input ctl_lsq_ex5_not_touch; +input ctl_lsq_ex5_algebraic; +input [0:1] ctl_lsq_ex5_class_id; +input [0:1] ctl_lsq_ex5_dvc; +input [0:5] ctl_lsq_ex5_ttype; +input [0:3] ctl_lsq_ex5_dacrw; +output [0:3] lsq_ctl_ex6_ldq_events; // LDQ Pipeline Performance Events +output [0:`THREADS-1] lsq_perv_ex7_events; // LDQ Pipeline Performance Events +output [0:(2*`THREADS)+3] lsq_perv_ldq_events; // REL Pipeline Performance Events +input [0:`THREADS-1] ctl_lsq_ex7_thrd_id; + +input [0:`THREADS-1] ctl_lsq_pf_empty; + +// Interface with Local SPR's +input [64-(2**`GPR_WIDTH_ENC):63] ctl_lsq_spr_dvc1_dbg; +input [64-(2**`GPR_WIDTH_ENC):63] ctl_lsq_spr_dvc2_dbg; +input [0:2*`THREADS-1] ctl_lsq_spr_dbcr2_dvc1m; +input [0:8*`THREADS-1] ctl_lsq_spr_dbcr2_dvc1be; +input [0:2*`THREADS-1] ctl_lsq_spr_dbcr2_dvc2m; +input [0:8*`THREADS-1] ctl_lsq_spr_dbcr2_dvc2be; +input [0:`THREADS-1] ctl_lsq_dbg_int_en; +input [0:`THREADS-1] ctl_lsq_ldp_idle; + +input stq_ldq_ex5_stq_restart; +input stq_ldq_ex5_stq_restart_miss; +input stq_ldq_ex5_fwd_val; + +// OrderQ Inputs +input odq_ldq_resolved; +input odq_ldq_report_needed; +input [0:`ITAG_SIZE_ENC-1] odq_ldq_report_itag; +input odq_ldq_n_flush; +input odq_ldq_np1_flush; +input [0:`THREADS-1] odq_ldq_report_tid; +input [0:3] odq_ldq_report_dacrw; +input odq_ldq_report_eccue; +input [0:3] odq_ldq_report_pEvents; +input [0:`THREADS-1] odq_ldq_oldest_ld_tid; +input [0:`ITAG_SIZE_ENC-1] odq_ldq_oldest_ld_itag; +input odq_ldq_ex7_pfetch_blk; + +// Store Queue is Empty +input [0:`THREADS-1] stq_ldq_empty; + +// Completion Inputs +input [0:`THREADS-1] iu_lq_cp_flush; +input [0:`ITAG_SIZE_ENC*`THREADS-1] iu_lq_cp_next_itag; + +// L2 Request Sent +input arb_ldq_ldq_unit_sel; + +// L2 Reload +input l2_lsq_resp_isComing; +input l2_lsq_resp_val; +input [0:4] l2_lsq_resp_cTag; +input [57:59] l2_lsq_resp_qw; +input l2_lsq_resp_crit_qw; +input l2_lsq_resp_l1_dump; +input [0:127] l2_lsq_resp_data; +input l2_lsq_resp_ecc_err; +input l2_lsq_resp_ecc_err_ue; + +// Data Cache Config +input xu_lq_spr_xucr0_cls; // Data Cache Line Size Mode + +// Load Gather Enable Config +input ctl_lsq_spr_lsucr0_lge; +input [0:2] ctl_lsq_spr_lsucr0_lca; + +// Inject Reload Data Array Parity Error +input pc_lq_inj_relq_parity; + +// Interface to Store Queue +output ldq_stq_rel1_blk_store; + +// Store Hit LoadMiss Queue Entries +output [0:`LMQ_ENTRIES-1] ldq_stq_ex5_ldm_hit; +output [0:`LMQ_ENTRIES-1] ldq_stq_ex5_ldm_entry; +output [0:`LMQ_ENTRIES-1] ldq_stq_ldm_cpl; + +// Directory Congruence Class Updated +output ldq_stq_stq4_dir_upd; +output [64-(`DC_SIZE-3):57] ldq_stq_stq4_cclass; + +// RV Reload Release Dependent ITAGs +output [0:`THREADS-1] lq_rv_itag2_vld; +output [0:`ITAG_SIZE_ENC-1] lq_rv_itag2; + +// Physical Register File update data for Reloads +output ldq_rel2_byte_swap; +output [0:127] ldq_rel2_data; + +// Load/Store Request was not restarted +output ldq_odq_vld; +output ldq_odq_pfetch_vld; +output ldq_odq_wimge_i; +output [0:3] ldq_odq_ex6_pEvents; + +// Update Order Queue Entry when reload is complete and itag is not resolved +output ldq_odq_upd_val; +output [0:`ITAG_SIZE_ENC-1] ldq_odq_upd_itag; +output ldq_odq_upd_nFlush; +output ldq_odq_upd_np1Flush; +output [0:`THREADS-1] ldq_odq_upd_tid; +output [0:3] ldq_odq_upd_dacrw; +output ldq_odq_upd_eccue; +output [0:3] ldq_odq_upd_pEvents; + +// Interface to Completion +output [0:`THREADS-1] lq1_iu_execute_vld; +output [0:`ITAG_SIZE_ENC-1] lq1_iu_itag; +output lq1_iu_exception_val; +output [0:5] lq1_iu_exception; +output lq1_iu_n_flush; +output lq1_iu_np1_flush; +output lq1_iu_dacr_type; +output [0:3] lq1_iu_dacrw; +output [0:3] lq1_iu_perf_events; + +// Reservation station hold indicator +output ldq_hold_all_req; + +// Reservation station set barrier indicator +output ldq_rv_set_hold; +output [0:`THREADS-1] ldq_rv_clr_hold; + +// LOADMISS Queue RESTART indicator +output lsq_ctl_ex5_ldq_restart; + +// LDQ Request to the L2 +output ldq_arb_ld_req_pwrToken; +output ldq_arb_ld_req_avail; +output [0:1] ldq_arb_tid; +output [0:3] ldq_arb_usr_def; +output [0:4] ldq_arb_wimge; +output [64-`REAL_IFAR_WIDTH:63] ldq_arb_p_addr; +output [0:5] ldq_arb_ttype; +output [0:2] ldq_arb_opsize; +output [0:4] ldq_arb_cTag; + +// RELOAD Data Control +output ldq_dat_stq1_stg_act; // ACT Pin for DAT +output lsq_dat_rel1_data_val; +output [57:59] lsq_dat_rel1_qw; // RELOAD Data Quadword + +// RELOAD Directory Control +output ldq_ctl_stq1_stg_act; // ACT Pin for CTL +output lsq_ctl_rel1_clr_val; // Reload Data is valid, need to Pick a Way to update +output lsq_ctl_rel1_set_val; // Reload Data is valid for last beat, update Directory Contents and set Valid +output lsq_ctl_rel1_data_val; // Reload Data is Valid, need to update Way in Data Cache +output [0:`THREADS-1] lsq_ctl_rel1_thrd_id; // Reload Thread ID for initial requester +output lsq_ctl_rel1_back_inv; // Reload was Back-Invalidated +output [0:3] lsq_ctl_rel1_tag; // Reload Tag +output [0:1] lsq_ctl_rel1_classid; // Used to index into xucr2 RMT table +output lsq_ctl_rel1_lock_set; // Reload is for a dcbt[st]ls instruction +output lsq_ctl_rel1_watch_set; // Reload is for a ldawx. instruction +output lsq_ctl_rel2_blk_req; // Block Reload due to RV issue or Back-Invalidate +output lsq_ctl_rel2_upd_val; // all 8 data beats have transferred without error, set valid in dir +output lsq_ctl_rel3_l1dump_val; // Reload Complete for an L1_DUMP reload +output lsq_ctl_rel3_clr_relq; // Reload Complete due to an ECC error + +// Control Common to Reload and Commit Pipes +output ldq_arb_rel1_data_sel; +output ldq_arb_rel1_axu_val; +output [0:2] ldq_arb_rel1_op_size; +output [64-`REAL_IFAR_WIDTH:63] ldq_arb_rel1_addr; +output ldq_arb_rel1_ci; +output ldq_arb_rel1_byte_swap; +output [0:`THREADS-1] ldq_arb_rel1_thrd_id; +output [0:127] ldq_arb_rel1_data; +output ldq_arb_rel2_rdat_sel; +output [0:143] ldq_arb_rel2_rd_data; +input [0:143] arb_ldq_rel2_wrt_data; + +// RELOAD Register Control +output lsq_ctl_rel1_gpr_val; // Critical Quadword requires an update of the Regfile +output [0:`AXU_SPARE_ENC+`GPR_POOL_ENC+`THREADS_POOL_ENC-1] lsq_ctl_rel1_ta_gpr; // Reload Target Register +output lsq_ctl_rel1_upd_gpr; // Critical Quadword did not get and ECC error in REL1 + +// Interface to Pervasive Unit +output lq_pc_err_invld_reld; // Reload detected without Loadmiss waiting for reload or got extra beats for cacheable request +output lq_pc_err_l2intrf_ecc; // Reload detected with an ECC error +output lq_pc_err_l2intrf_ue; // Reload detected with an uncorrectable ECC error +output lq_pc_err_relq_parity; // Reload Data Queue Parity Error Detected + +// Thread Quiesced +output [0:`THREADS-1] lq_xu_quiesce; // Thread is Quiesced +output [0:`THREADS-1] lq_pc_ldq_quiesce; +output [0:`THREADS-1] lq_pc_stq_quiesce; +output [0:`THREADS-1] lq_pc_pfetch_quiesce; + +// Interface to MMU +output lq_mm_lmq_stq_empty; // Load and Store Queue is empty + +// Array Pervasive Controls +input bo_enable_2; +input clkoff_dc_b; +input g8t_clkoff_dc_b; +input g8t_d_mode_dc; +input [0:4] g8t_delay_lclkr_dc; +input [0:4] g8t_mpw1_dc_b; +input g8t_mpw2_dc_b; +input pc_lq_ccflush_dc; +input an_ac_scan_dis_dc_b; +input an_ac_scan_diag_dc; +input an_ac_lbist_ary_wrt_thru_dc; +input pc_lq_abist_ena_dc; +input pc_lq_abist_raw_dc_b; +input pc_lq_abist_wl64_comp_ena; +input [3:8] pc_lq_abist_raddr_0; +input pc_lq_abist_g8t_wenb; +input pc_lq_abist_g8t1p_renb_0; +input [0:3] pc_lq_abist_g8t_dcomp; +input pc_lq_abist_g8t_bw_1; +input pc_lq_abist_g8t_bw_0; +input [0:3] pc_lq_abist_di_0; +input [4:9] pc_lq_abist_waddr_0; +input pc_lq_bo_unload; +input pc_lq_bo_repair; +input pc_lq_bo_reset; +input pc_lq_bo_shdata; +input [8:9] pc_lq_bo_select; +output [8:9] lq_pc_bo_fail; +output [8:9] lq_pc_bo_diagout; + +// Pervasive +inout vcs; +inout vdd; +inout gnd; +(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) +input [0:`NCLK_WIDTH-1] nclk; +input sg_0; +input func_sl_thold_0_b; +input func_sl_force; +input func_nsl_thold_0_b; +input func_nsl_force; +input abst_sl_thold_0; +input ary_nsl_thold_0; +input time_sl_thold_0; +input repr_sl_thold_0; +input bolt_sl_thold_0; +input d_mode_dc; +input delay_lclkr_dc; +input mpw1_dc_b; +input mpw2_dc_b; + +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) +input scan_in; +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) +input abst_scan_in; +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) +input time_scan_in; +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) +input repr_scan_in; +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) +output scan_out; +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) +output abst_scan_out; +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) +output time_scan_out; +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) +output repr_scan_out; + +//-------------------------- +// components +//-------------------------- + +//-------------------------- +// signals +//-------------------------- +parameter numGrps = ((((`LMQ_ENTRIES-1)/4)+1)*4); +parameter AXU_TARGET_ENC = `AXU_SPARE_ENC + `GPR_POOL_ENC + `THREADS_POOL_ENC; + +wire [0:`LMQ_ENTRIES-1] ldqe_dRel_d; +wire [0:`LMQ_ENTRIES-1] ldqe_dRel_q; +wire [0:1] ldqe_dGpr_cntrl[0:`LMQ_ENTRIES-1]; +wire [0:`LMQ_ENTRIES-1] ldqe_dGpr_d; +wire [0:`LMQ_ENTRIES-1] ldqe_dGpr_q; +wire [0:`THREADS-1] ldqe_thrd_id_d[0:`LMQ_ENTRIES-1]; +wire [0:`THREADS-1] ldqe_thrd_id_q[0:`LMQ_ENTRIES-1]; +wire [0:`LMQ_ENTRIES-1] ldqe_wimge_i; +wire [0:`LMQ_ENTRIES-1] ldqe_wimge_g; +wire [0:4] ldqe_wimge_d[0:`LMQ_ENTRIES-1]; +wire [0:4] ldqe_wimge_q[0:`LMQ_ENTRIES-1]; +wire [0:`LMQ_ENTRIES-1] ldqe_byte_swap_d; +wire [0:`LMQ_ENTRIES-1] ldqe_byte_swap_q; +wire [0:`LMQ_ENTRIES-1] ldqe_resv_d; +wire [0:`LMQ_ENTRIES-1] ldqe_resv_q; +wire [0:`LMQ_ENTRIES-1] ldqe_pfetch_d; +wire [0:`LMQ_ENTRIES-1] ldqe_pfetch_q; +wire [0:2] ldqe_op_size_d[0:`LMQ_ENTRIES-1]; +wire [0:2] ldqe_op_size_q[0:`LMQ_ENTRIES-1]; +wire [0:AXU_TARGET_ENC-1] ldqe_tgpr_d[0:`LMQ_ENTRIES-1]; +wire [0:AXU_TARGET_ENC-1] ldqe_tgpr_q[0:`LMQ_ENTRIES-1]; +wire [0:`LMQ_ENTRIES-1] ldqe_axu_d; +wire [0:`LMQ_ENTRIES-1] ldqe_axu_q; +wire [0:3] ldqe_usr_def_d[0:`LMQ_ENTRIES-1]; +wire [0:3] ldqe_usr_def_q[0:`LMQ_ENTRIES-1]; +wire [0:`LMQ_ENTRIES-1] ldqe_lock_set_d; +wire [0:`LMQ_ENTRIES-1] ldqe_lock_set_q; +wire [0:`LMQ_ENTRIES-1] ldqe_watch_set_d; +wire [0:`LMQ_ENTRIES-1] ldqe_watch_set_q; +wire [0:`LMQ_ENTRIES-1] ldqe_algebraic_d; +wire [0:`LMQ_ENTRIES-1] ldqe_algebraic_q; +wire [0:1] ldqe_class_id_d[0:`LMQ_ENTRIES-1]; +wire [0:1] ldqe_class_id_q[0:`LMQ_ENTRIES-1]; +wire [0:3] ldqe_perf_events_d[0:`LMQ_ENTRIES-1]; +wire [0:3] ldqe_perf_events_q[0:`LMQ_ENTRIES-1]; +wire [0:1] ldqe_set_gpr_done[0:`LMQ_ENTRIES-1]; +wire [0:1] ldqe_dvc_d[0:`LMQ_ENTRIES-1]; +wire [0:1] ldqe_dvc_q[0:`LMQ_ENTRIES-1]; +wire [0:5] ldqe_ttype_d[0:`LMQ_ENTRIES-1]; +wire [0:5] ldqe_ttype_q[0:`LMQ_ENTRIES-1]; +wire [0:3] ldqe_dacrw_d[0:`LMQ_ENTRIES-1]; +wire [0:3] ldqe_dacrw_q[0:`LMQ_ENTRIES-1]; +wire [0:`ITAG_SIZE_ENC-1] ldqe_itag_d[0:`LMQ_ENTRIES-1]; +wire [0:`ITAG_SIZE_ENC-1] ldqe_itag_q[0:`LMQ_ENTRIES-1]; +wire [64-`REAL_IFAR_WIDTH:57] ldqe_p_addr_msk[0:`LMQ_ENTRIES-1]; +wire [64-`REAL_IFAR_WIDTH:63] ldqe_p_addr_d[0:`LMQ_ENTRIES-1]; +wire [64-`REAL_IFAR_WIDTH:63] ldqe_p_addr_q[0:`LMQ_ENTRIES-1]; +wire [0:`LMQ_ENTRIES-1] ldqe_cp_flush; +wire [0:`LMQ_ENTRIES-1] ldqe_odq_flush; +wire [0:`LMQ_ENTRIES-1] ldqe_pfetch_flush; +wire [0:`LMQ_ENTRIES-1] ldqe_flush; +wire [0:`LMQ_ENTRIES-1] ldqe_kill; +wire [0:`LMQ_ENTRIES-1] ldqe_mkill; +wire [0:`LMQ_ENTRIES-1] ldqe_mkill_d; +wire [0:`LMQ_ENTRIES-1] ldqe_mkill_q; +wire [0:`LMQ_ENTRIES-1] ldqe_resolved; +wire [0:`LMQ_ENTRIES-1] ldqe_resolved_d; +wire [0:`LMQ_ENTRIES-1] ldqe_resolved_q; +wire [0:`LMQ_ENTRIES-1] ldqe_back_inv_d; +wire [0:`LMQ_ENTRIES-1] ldqe_back_inv_q; +wire [0:`LMQ_ENTRIES-1] ldqe_back_inv_nFlush_d; +wire [0:`LMQ_ENTRIES-1] ldqe_back_inv_nFlush_q; +wire [0:`LMQ_ENTRIES-1] ldqe_back_inv_np1Flush_d; +wire [0:`LMQ_ENTRIES-1] ldqe_back_inv_np1Flush_q; +wire [0:`LMQ_ENTRIES-1] ex5_ldm_hit_d; +wire [0:`LMQ_ENTRIES-1] ex5_ldm_hit_q; +wire spr_xucr0_cls_d; +wire spr_xucr0_cls_q; +wire spr_lsucr0_lge_d; +wire spr_lsucr0_lge_q; +wire [0:2] spr_lsucr0_lca_d; +wire [0:2] spr_lsucr0_lca_q; +wire spr_lsucr0_lca_zero; +wire [0:2] spr_lsucr0_lca_ovrd; +wire [0:`THREADS-1] iu_lq_cp_flush_d; +wire [0:`THREADS-1] iu_lq_cp_flush_q; +wire [0:`ITAG_SIZE_ENC-1] iu_lq_cp_next_itag_q[0:`THREADS-1]; +wire ex4_stg_flush; +wire ex5_stg_flush; +wire odq_ldq_n_flush_d; +wire odq_ldq_n_flush_q; +wire odq_ldq_resolved_d; +wire odq_ldq_resolved_q; +wire [0:`ITAG_SIZE_ENC-1] odq_ldq_report_itag_d; +wire [0:`ITAG_SIZE_ENC-1] odq_ldq_report_itag_q; +wire [0:`THREADS-1] odq_ldq_report_tid_d; +wire [0:`THREADS-1] odq_ldq_report_tid_q; +wire [0:`THREADS-1] rv_lq_rvs_empty_d; +wire [0:`THREADS-1] rv_lq_rvs_empty_q; +wire ldq_rel1_set_rviss_dir_coll; +wire ldq_rel1_set_binv_dir_coll; +wire ldq_rel1_set_rd_dir_coll; +wire rel2_blk_req_d; +wire rel2_blk_req_q; +wire rel2_rviss_blk_d; +wire rel2_rviss_blk_q; +wire [64-`REAL_IFAR_WIDTH:57] l2_back_inv_addr_msk; +wire [64-`REAL_IFAR_WIDTH:57] ex4_p_addr_msk; +wire ex4_ldreq_d; +wire ex4_ldreq_q; +wire ex5_ldreq_val; +wire ex5_ldreq_val_d; +wire ex5_ldreq_val_q; +wire ex5_ldreq_flushed; +wire ex4_pfetch_val_d; +wire ex4_pfetch_val_q; +wire ex5_pfetch_val; +wire ex5_pfetch_val_d; +wire ex5_pfetch_val_q; +wire ex5_pfetch_flushed; +wire ex5_odq_ldreq_val_d; +wire ex5_odq_ldreq_val_q; +wire ex5_streq_val_d; +wire ex5_streq_val_q; +wire ex5_othreq_val_d; +wire ex5_othreq_val_q; +wire [64-`REAL_IFAR_WIDTH:63] ex5_p_addr_d; +wire [64-`REAL_IFAR_WIDTH:63] ex5_p_addr_q; +wire [0:4] ex5_wimge_d; +wire [0:4] ex5_wimge_q; +wire [0:11] ex5_cmmt_events; +wire [0:3] ex5_cmmt_perf_events; +wire [0:3] ex6_cmmt_perf_events_d; +wire [0:3] ex6_cmmt_perf_events_q; +wire [0:`LMQ_ENTRIES-1] ex4_ldqe_set_val; +wire [0:`LMQ_ENTRIES-1] ex4_ldqe_set_all; +wire [0:`LMQ_ENTRIES-1] ex5_ldqe_set_all_d; +wire [0:`LMQ_ENTRIES-1] ex5_ldqe_set_all_q; +wire [0:`LMQ_ENTRIES-1] ex5_ldqe_set_val_d; +wire [0:`LMQ_ENTRIES-1] ex5_ldqe_set_val_q; +wire [0:`LMQ_ENTRIES-1] ex6_ldqe_pfetch_val_d; +wire [0:`LMQ_ENTRIES-1] ex6_ldqe_pfetch_val_q; +wire [0:`LMQ_ENTRIES-1] ex7_ldqe_pfetch_val_d; +wire [0:`LMQ_ENTRIES-1] ex7_ldqe_pfetch_val_q; +wire ex7_pfetch_blk_val; +wire [0:`THREADS-1] ex7_pfetch_blk_tid; +wire [0:`LMQ_ENTRIES-1] ex5_ldm_entry; +reg [0:`THREADS-1] ldq_all_req_home; +wire [0:`THREADS-1] lq_xu_quiesce_d; +wire [0:`THREADS-1] lq_xu_quiesce_q; +wire lq_mm_lmq_stq_empty_d; +wire lq_mm_lmq_stq_empty_q; +wire [0:`THREADS-1] lq_pc_ldq_quiesce_d; +wire [0:`THREADS-1] lq_pc_ldq_quiesce_q; +wire [0:`THREADS-1] lq_pc_stq_quiesce_d; +wire [0:`THREADS-1] lq_pc_stq_quiesce_q; +wire [0:`THREADS-1] lq_pc_pfetch_quiesce_d; +wire [0:`THREADS-1] lq_pc_pfetch_quiesce_q; +reg [0:3] ex5_cTag; +reg [0:1] ex5_tid_enc; +wire [0:3] ldqe_beat_init; +wire [0:`LMQ_ENTRIES-1] ldqe_wrt_ptr; +wire [0:`LMQ_ENTRIES-1] ldqe_opposite_ptr; +wire ex4_one_machine_avail; +wire ex4_oldest_load; +wire ex4_reserved_taken; +wire ex5_reserved_taken_d; +wire ex5_reserved_taken_q; +wire ex4_resv_taken_restart; +wire ex5_resv_taken_restart_d; +wire ex5_resv_taken_restart_q; +wire [0:`LMQ_ENTRIES+`LGQ_ENTRIES-1] ldqe_cpl_sel; +wire [0:`LMQ_ENTRIES+`LGQ_ENTRIES-1] ldqe_cpl_sent; +wire [0:`LMQ_ENTRIES-1] ex5_inv_ldqe; +wire ex4_ldq_full; +wire ex5_ldq_full_d; +wire ex5_ldq_full_q; +wire ex4_ldq_full_restart; +wire ex5_ldq_full_restart_d; +wire ex5_ldq_full_restart_q; +wire ex4_ldq_hit; +wire ex5_ldq_hit_d; +wire ex5_ldq_hit_q; +wire ldq_full_qHit_held_set; +wire ldq_full_qHit_held_clr; +wire [0:1] ldq_full_qHit_held_ctrl; +wire ldq_full_qHit_held_d; +wire ldq_full_qHit_held_q; +wire ldq_resv_qHit_held_set; +wire ldq_resv_qHit_held_clr; +wire [0:1] ldq_resv_qHit_held_ctrl; +wire ldq_resv_qHit_held_d; +wire ldq_resv_qHit_held_q; +wire ldq_oth_qHit_clr_d; +wire ldq_oth_qHit_clr_q; +wire ex5_ldq_set_hold_d; +wire ex5_ldq_set_hold_q; +wire ex5_ldq_full_set_hold; +wire ex5_setHold; +wire ldq_clrHold; +wire [0:`THREADS-1] ldq_clrHold_tid; +wire [0:`THREADS-1] ldq_setHold_tid; +wire [0:`THREADS-1] ldq_hold_tid; +wire [0:`THREADS-1] ldq_hold_tid_d; +wire [0:`THREADS-1] ldq_hold_tid_q; +wire ex5_ldq_restart; +wire ex5_ldq_restart_d; +wire ex5_ldq_restart_q; +wire ex6_ldq_full_d; +wire ex6_ldq_full_q; +wire ex6_ldq_hit_d; +wire ex6_ldq_hit_q; +wire ex5_lgq_full_d; +wire ex5_lgq_full_q; +wire ex6_lgq_full_d; +wire ex6_lgq_full_q; +wire ex5_lgq_qwhit_d; +wire ex5_lgq_qwhit_q; +wire ex6_lgq_qwhit_d; +wire ex6_lgq_qwhit_q; +wire ex5_restart_val; +wire ex5_drop_req_val; +wire ex5_drop_gath; +wire perf_ex6_ldq_full_restart; +wire perf_ex6_ldq_hit_restart; +wire perf_ex6_lgq_full_restart; +wire perf_ex6_lgq_qwhit_restart; +wire [0:`LMQ_ENTRIES-1] ldqe_inuse; +wire [0:`THREADS-1] ldqe_tid_inuse[0:`LMQ_ENTRIES-1]; +wire [0:`LMQ_ENTRIES-1] ldqe_req_outstanding; +wire [0:`THREADS-1] ldqe_tid_req_outstanding[0:`LMQ_ENTRIES-1]; +wire [0:`LMQ_ENTRIES-1] ldqe_req_able_to_hold; +wire [0:`LMQ_ENTRIES-1] ldqe_rel_blk_qHit_held; +wire [0:`LMQ_ENTRIES-1] ex4_load_qHit_upd; +wire [0:`LMQ_ENTRIES-1] ex4_addr_m_queue; +wire [0:`LMQ_ENTRIES-1] ex4_qw_hit_queue; +reg [0:`LMQ_ENTRIES-1] ex4_lgq_qw_hit; +wire ex5_ld_gath_d; +wire ex5_ld_gath_q; +wire ex4_ld_gath; +wire [0:`LMQ_ENTRIES-1] ldqe_entry_gatherable; +wire [0:`LMQ_ENTRIES-1] ex4_entry_gatherable; +wire [0:`LMQ_ENTRIES-1] ex4_entry_gath_ld; +wire [0:`LMQ_ENTRIES-1] ex4_entry_gath_full; +wire [0:`LMQ_ENTRIES-1] ex4_entry_gath_qwhit; +wire [0:`LMQ_ENTRIES-1] ex4_thrd_id_m; +wire [0:`LMQ_ENTRIES-1] ex4_larx_hit; +wire [0:`LMQ_ENTRIES-1] ex4_guarded_hit; +wire [0:`LMQ_ENTRIES-1] ex4_req_hit_ldq; +wire [0:`LMQ_ENTRIES-1] ex4_entry_load_qHit; +wire [0:`LMQ_ENTRIES-1] ldqe_back_inv; +wire [0:`LMQ_ENTRIES-1] ldqe_back_inv_flush_upd; +wire [0:`THREADS-1] ldqe_cpNext_tid[0:`LMQ_ENTRIES-1]; +wire [0:`LMQ_ENTRIES-1] ldqe_cpNext_val; +wire [0:((((`LMQ_ENTRIES-1)/4)+1)*4)-1] ldqe_sent; +reg [0:`LMQ_ENTRIES-1] ldqe_req_cmpl_d; +wire [0:`LMQ_ENTRIES-1] ldqe_req_cmpl_q; +reg [0:`LMQ_ENTRIES-1] ldqe_val_d; +wire [0:`LMQ_ENTRIES-1] ldqe_val_q; +wire [0:`LMQ_ENTRIES-1] ldqe_ctrl_act; +wire [0:`LMQ_ENTRIES-1] ldqe_rel_inprog; +wire [0:`LMQ_ENTRIES-1] ldqe_zap; +wire [0:`LMQ_ENTRIES-1] ldqe_need_l2send; +wire [0:1] ldqe_beat_ctrl[0:`LMQ_ENTRIES-1]; +wire [0:3] ldqe_beat_incr[0:`LMQ_ENTRIES-1]; +wire [0:3] ldqe_beat_cntr_d[0:`LMQ_ENTRIES-1]; +wire [0:3] ldqe_beat_cntr_q[0:`LMQ_ENTRIES-1]; +wire ex5_upd_fifo_val; +wire fifo_ldq_act; +wire fifo_ldq_req_compr_val; +wire fifo_ldq_req_sent; +wire fifo_ldq_req0_mkill; +wire fifo_ldq_req0_avail; +wire [0:1] fifo_ldq_wrt_ptr_cntrl; +wire fifo_ldq_reset_ptr; +wire [0:`LMQ_ENTRIES] fifo_ldq_req_nxt_ptr; +wire [0:`LMQ_ENTRIES] fifo_ldq_req_nxt_ptr_d; +wire [0:`LMQ_ENTRIES] fifo_ldq_req_nxt_ptr_q; +wire [0:`LMQ_ENTRIES] fifo_ldq_req_wrt_ptr; +wire [0:`LMQ_ENTRIES-1] fifo_ldq_req_upd; +wire [0:`LMQ_ENTRIES-1] fifo_ldq_req_empty_entry; +wire [0:`LMQ_ENTRIES-1] fifo_ldq_req_push; +wire [0:1] fifo_ldq_req_cntrl[0:`LMQ_ENTRIES-1]; +wire [0:`LMQ_ENTRIES-1] fifo_ldq_req_val; +wire [0:`LMQ_ENTRIES-1] fifo_ldq_req_val_d; +wire [0:`LMQ_ENTRIES-1] fifo_ldq_req_val_q; +wire [0:`LMQ_ENTRIES-1] fifo_ldq_req_pfetch_match; +wire [0:`LMQ_ENTRIES-1] fifo_ldq_req_pfetch_send; +wire [0:`LMQ_ENTRIES-1] fifo_ldq_req_pfetch; +wire [0:`LMQ_ENTRIES-1] fifo_ldq_req_pfetch_d; +wire [0:`LMQ_ENTRIES-1] fifo_ldq_req_pfetch_q; +wire [0:`THREADS-1] fifo_ldq_req_tid_d[0:`LMQ_ENTRIES-1]; +wire [0:`THREADS-1] fifo_ldq_req_tid_q[0:`LMQ_ENTRIES-1]; +wire [0:`LMQ_ENTRIES-1] fifo_ldq_req_d[0:`LMQ_ENTRIES-1]; +wire [0:`LMQ_ENTRIES-1] fifo_ldq_req_q[0:`LMQ_ENTRIES-1]; +reg [0:3] ldq_mux_usr_def; +reg [0:4] ldq_mux_wimge; +reg [64-`REAL_IFAR_WIDTH:63] ldq_mux_p_addr; +reg [0:5] ldq_mux_ttype; +reg [0:2] ldq_mux_opsize; +reg [0:`THREADS-1] ldq_mux_tid; +reg [0:1] ldq_mux_tid_enc; +reg [0:3] ldq_mux_cTag; +wire [0:`LMQ_ENTRIES-1] ldqe_relmin1_cTag; +wire [0:`LMQ_ENTRIES-1] ldqe_rel0_cTag; +wire [0:`LMQ_ENTRIES-1] ldqe_rel1_cTag; +wire [0:`LMQ_ENTRIES-1] ldq_relmin1_l2_val; +wire [0:`LMQ_ENTRIES-1] ldq_rel0_l2_val_d; +wire [0:`LMQ_ENTRIES-1] ldq_rel0_l2_val_q; +wire [0:`LMQ_ENTRIES-1] ldq_relmin1_l2_inval; +wire [0:`LMQ_ENTRIES-1] ldq_rel_l2_l1dumpBlk; +wire [0:`LMQ_ENTRIES-1] ldq_relmin1_l2_qHitBlk; +wire [0:`LMQ_ENTRIES-1] ldqe_cpNext_ecc_err; +wire [0:`LMQ_ENTRIES-1] ldqe_nFlush_ecc_err; +reg [0:6] ldqe_nxt_state[0:`LMQ_ENTRIES-1]; +wire [0:6] ldqe_state_d[0:`LMQ_ENTRIES-1]; +wire [0:6] ldqe_state_q[0:`LMQ_ENTRIES-1]; +wire [0:3] ldq_resp_cTag; +wire [57:59] ldq_resp_qw; +wire [0:`LMQ_ENTRIES-1] ldq_rel1_beats_home; +wire [0:`LMQ_ENTRIES-1] ldq_rel2_beats_home_d; +wire [0:`LMQ_ENTRIES-1] ldq_rel2_beats_home_q; +wire [0:`LMQ_ENTRIES-1] ldq_rel3_beats_home_d; +wire [0:`LMQ_ENTRIES-1] ldq_rel3_beats_home_q; +wire [0:`LMQ_ENTRIES-1] ldq_rel4_beats_home_d; +wire [0:`LMQ_ENTRIES-1] ldq_rel4_beats_home_q; +wire [0:`LMQ_ENTRIES-1] ldq_rel5_beats_home_d; +wire [0:`LMQ_ENTRIES-1] ldq_rel5_beats_home_q; +wire [0:`LMQ_ENTRIES-1] ldq_rel0_entrySent; +wire [0:`LMQ_ENTRIES-1] ldq_rel1_entrySent_d; +wire [0:`LMQ_ENTRIES-1] ldq_rel1_entrySent_q; +wire [0:`LMQ_ENTRIES-1] ldq_rel2_entrySent_d; +wire [0:`LMQ_ENTRIES-1] ldq_rel2_entrySent_q; +wire [0:`LMQ_ENTRIES-1] ldq_rel3_entrySent_d; +wire [0:`LMQ_ENTRIES-1] ldq_rel3_entrySent_q; +wire [0:`LMQ_ENTRIES-1] ldq_rel4_sentL1_d; +wire [0:`LMQ_ENTRIES-1] ldq_rel4_sentL1_q; +wire [0:`LMQ_ENTRIES-1] ldq_rel5_sentL1_d; +wire [0:`LMQ_ENTRIES-1] ldq_rel5_sentL1_q; +wire [0:`LMQ_ENTRIES-1] ldq_rel5_req_noL1done; +wire [0:`LMQ_ENTRIES-1] ldq_rel5_req_done; +wire [0:`LMQ_ENTRIES-1] ldq_rel6_req_done_d; +wire [0:`LMQ_ENTRIES-1] ldq_rel6_req_done_q; +wire [0:`LMQ_ENTRIES-1] ldq_rel2_ci_done; +wire [0:`LMQ_ENTRIES-1] ldq_rel2_drel_done; +wire ldq_rel1_val_d; +wire ldq_rel1_val_q; +wire ldq_rel1_arb_val_d; +wire ldq_rel1_arb_val_q; +wire ldq_rel0_rdat_sel; +wire [0:2] ldq_rel0_rdat_qw; +wire ldq_rel1_l1_dump_d; +wire ldq_rel1_l1_dump_q; +wire ldq_rel2_l1_dump_d; +wire ldq_rel2_l1_dump_q; +wire ldq_rel3_l1_dump_d; +wire ldq_rel3_l1_dump_q; +wire ldq_rel3_l1_dump_val; +wire ldq_rel3_clr_relq_d; +wire ldq_rel3_clr_relq_q; +wire [0:2] ldq_rel1_resp_qw_d; +wire [0:2] ldq_rel1_resp_qw_q; +wire [0:3] ldq_rel1_cTag_d; +wire [0:3] ldq_rel1_cTag_q; +wire l2_rel1_resp_val_d; +wire l2_rel1_resp_val_q; +wire l2_rel2_resp_val_d; +wire l2_rel2_resp_val_q; +wire ldq_err_inval_rel_d; +wire ldq_err_inval_rel_q; +wire ldq_err_ecc_det_d; +wire ldq_err_ecc_det_q; +wire ldq_err_ue_det_d; +wire ldq_err_ue_det_q; +wire ldq_rel3_rdat_par_err; +reg [0:2] ldq_rel_mux_opsize; +reg ldq_rel_mux_wimge_i; +reg ldq_rel_mux_byte_swap; +reg [64-`REAL_IFAR_WIDTH:63] ldq_rel_mux_p_addr; +wire [64-(`DC_SIZE-3):57] ldq_rel_mux_p_addr_msk; +reg [0:1] ldq_rel_mux_dvcEn; +reg ldq_rel_mux_lockSet; +reg ldq_rel_mux_watchSet; +reg [0:AXU_TARGET_ENC-1] ldq_rel_mux_tGpr; +reg ldq_rel_mux_axu; +reg ldq_rel_mux_algEn; +reg [0:1] ldq_rel_mux_classID; +reg [0:`THREADS-1] ldq_rel_mux_tid; +reg ldq_rel1_mux_back_inv; +reg [0:2] lgq_rel_mux_opsize; +reg [59:63] lgq_rel_mux_p_addr; +reg lgq_rel_mux_byte_swap; +reg [0:1] lgq_rel_mux_dvcEn; +reg [0:AXU_TARGET_ENC-1] lgq_rel_mux_tGpr; +reg lgq_rel_mux_axu; +reg lgq_rel_mux_algEn; +reg [0:`THREADS-1] lgq_rel_mux_tid; +wire [0:2] ldq_rel1_opsize_d; +wire [0:2] ldq_rel1_opsize_q; +wire ldq_rel1_wimge_i_d; +wire ldq_rel1_wimge_i_q; +wire ldq_rel1_byte_swap_d; +wire ldq_rel1_byte_swap_q; +wire ldq_rel2_byte_swap_d; +wire ldq_rel2_byte_swap_q; +wire [64-`REAL_IFAR_WIDTH:63] ldq_rel1_p_addr_d; +wire [64-`REAL_IFAR_WIDTH:63] ldq_rel1_p_addr_q; +wire [0:1] ldq_rel1_dvcEn_d; +wire [0:1] ldq_rel1_dvcEn_q; +wire ldq_rel1_lockSet_d; +wire ldq_rel1_lockSet_q; +wire ldq_rel1_watchSet_d; +wire ldq_rel1_watchSet_q; +wire [0:AXU_TARGET_ENC-1] ldq_rel1_tGpr_d; +wire [0:AXU_TARGET_ENC-1] ldq_rel1_tGpr_q; +wire ldq_rel1_axu_d; +wire ldq_rel1_axu_q; +wire ldq_rel1_algEn_d; +wire ldq_rel1_algEn_q; +wire [0:1] ldq_rel1_classID_d; +wire [0:1] ldq_rel1_classID_q; +wire [0:`THREADS-1] ldq_rel1_tid_d; +wire [0:`THREADS-1] ldq_rel1_tid_q; +wire [0:`THREADS-1] ldq_rel2_tid_d; +wire [0:`THREADS-1] ldq_rel2_tid_q; +wire [0:`THREADS-1] ldq_rel1_dir_tid_d; +wire [0:`THREADS-1] ldq_rel1_dir_tid_q; +reg [0:`ITAG_SIZE_ENC-1] ldqe_relmin1_iTag; +reg [0:`THREADS-1] ldqe_relmin1_tid; +reg [0:`ITAG_SIZE_ENC-1] lgqe_relmin1_iTag; +reg [0:`THREADS-1] lgqe_relmin1_tid; +wire [0:`THREADS-1] ldq_relmin1_tid; +wire [0:`ITAG_SIZE_ENC-1] ldq_relmin1_iTag; +wire [0:7] ldq_rel0_beat_upd; +wire [0:`LMQ_ENTRIES-1] ldq_rel2_sentL1; +wire [0:`LMQ_ENTRIES-1] ldq_rel2_sentL1_blk; +wire [0:1] ldqe_sentRel_ctrl[0:`LMQ_ENTRIES-1]; +wire [0:3] ldqe_sentRel_incr[0:`LMQ_ENTRIES-1]; +wire [0:3] ldqe_sentRel_cntr_d[0:`LMQ_ENTRIES-1]; +wire [0:3] ldqe_sentRel_cntr_q[0:`LMQ_ENTRIES-1]; +wire [0:`LMQ_ENTRIES-1] ldqe_sentL1; +wire [0:`LMQ_ENTRIES-1] ldqe_last_beat; +wire [0:`LMQ_ENTRIES-1] ldqe_rel2_l1upd_cmpl; +wire [0:1] ldqe_rel_start_ctrl[0:`LMQ_ENTRIES-1]; +wire [0:`LMQ_ENTRIES-1] ldqe_relDir_start; +wire [0:`LMQ_ENTRIES-1] ldqe_relDir_start_d; +wire [0:`LMQ_ENTRIES-1] ldqe_relDir_start_q; +wire ldq_rel0_arb_val; +wire [0:3] ldq_rel0_arb_cTag; +wire ldq_rel0_arb_thresh; +wire [0:2] ldq_rel0_arb_qw; +wire [0:`LMQ_ENTRIES-1] ldq_rel0_arb_sent; +wire ldq_rel0_arr_wren; +wire ldq_rel1_clr_val; +wire ldq_l2_rel0_qHitBlk_d; +wire ldq_l2_rel0_qHitBlk_q; +wire ldq_l2_resp_hold_all; +wire ldq_rel_arb_hold_all; +wire [64-(`DC_SIZE-3):57] ldq_rel2_cclass_d; +wire [64-(`DC_SIZE-3):57] ldq_rel2_cclass_q; +wire [64-(`DC_SIZE-3):57] ldq_rel3_cclass_d; +wire [64-(`DC_SIZE-3):57] ldq_rel3_cclass_q; +wire [64-(`DC_SIZE-3):57] ldq_rel4_cclass_d; +wire [64-(`DC_SIZE-3):57] ldq_rel4_cclass_q; +wire ldq_rel1_set_val; +wire ldq_rel2_set_val_d; +wire ldq_rel2_set_val_q; +wire ldq_rel3_set_val_d; +wire ldq_rel3_set_val_q; +wire ldq_rel4_set_val_d; +wire ldq_rel4_set_val_q; +wire ldq_rel1_data_val; +wire ldq_rel1_data_sel_d; +wire ldq_rel1_data_sel_q; +wire [0:`LMQ_ENTRIES-1] ldq_rel1_l2_val_d; +wire [0:`LMQ_ENTRIES-1] ldq_rel1_l2_val_q; +wire [0:`LMQ_ENTRIES-1] ldq_rel2_l2_val_d; +wire [0:`LMQ_ENTRIES-1] ldq_rel2_l2_val_q; +wire [0:`LMQ_ENTRIES-1] ldq_rel3_l2_val_d; +wire [0:`LMQ_ENTRIES-1] ldq_rel3_l2_val_q; +wire [0:`LMQ_ENTRIES-1] ldq_rel4_l2_val_d; +wire [0:`LMQ_ENTRIES-1] ldq_rel4_l2_val_q; +wire [0:`LMQ_ENTRIES-1] ldq_rel5_l2_val_d; +wire [0:`LMQ_ENTRIES-1] ldq_rel5_l2_val_q; +reg [0:`LMQ_ENTRIES-1] ldqe_cntr_reset_d; +wire [0:`LMQ_ENTRIES-1] ldqe_cntr_reset_q; +reg [0:`LMQ_ENTRIES-1] ldqe_resent_ecc_err_d; +wire [0:`LMQ_ENTRIES-1] ldqe_resent_ecc_err_q; +reg [0:`LMQ_ENTRIES-1] ldqe_reset_cpl_rpt_d; +wire [0:`LMQ_ENTRIES-1] ldqe_reset_cpl_rpt_q; +wire [0:`LMQ_ENTRIES-1] ldqe_rel_rdat_perr; +reg [0:`LMQ_ENTRIES-1] ldqe_ecc_err_dgpr; +reg [0:`LMQ_ENTRIES-1] ldqe_rst_eccdet; +wire [0:`LMQ_ENTRIES-1] ldqe_rst_eccdet_d; +wire [0:`LMQ_ENTRIES-1] ldqe_rst_eccdet_q; +wire [0:1] ldqe_rel_eccdet_sel[0:`LMQ_ENTRIES-1]; +wire [0:`LMQ_ENTRIES-1] ldqe_rel_eccdet; +wire [0:`LMQ_ENTRIES-1] ldqe_rel_eccdet_d; +wire [0:`LMQ_ENTRIES-1] ldqe_rel_eccdet_q; +wire [0:`LMQ_ENTRIES-1] ldqe_rel_eccdet_ue; +wire [0:`LMQ_ENTRIES-1] ldqe_rel_eccdet_ue_d; +wire [0:`LMQ_ENTRIES-1] ldqe_rel_eccdet_ue_q; +wire [0:`LMQ_ENTRIES-1] ldq_rel2_gpr_ecc_err; +wire [0:`LMQ_ENTRIES-1] ldq_rel2_gpr_eccue_err; +wire [0:1] ldqe_upd_gpr_ecc_sel[0:`LMQ_ENTRIES-1]; +wire [0:`LMQ_ENTRIES-1] ldqe_upd_gpr_ecc; +wire [0:`LMQ_ENTRIES-1] ldqe_upd_gpr_ecc_d; +wire [0:`LMQ_ENTRIES-1] ldqe_upd_gpr_ecc_q; +wire [0:`LMQ_ENTRIES-1] ldqe_upd_gpr_eccue; +wire [0:`LMQ_ENTRIES-1] ldqe_upd_gpr_eccue_d; +wire [0:`LMQ_ENTRIES-1] ldqe_upd_gpr_eccue_q; +wire rel0_stg_act; +wire ldq_reload_val; +wire [0:1] ldqe_rel_l1_dump_ctrl[0:`LMQ_ENTRIES-1]; +wire [0:`LMQ_ENTRIES-1] ldqe_drop_reload_val; +wire [0:`LMQ_ENTRIES-1] ldq_rel_l1_dump; +wire [0:`LMQ_ENTRIES-1] ldqe_l1_dump_d; +wire [0:`LMQ_ENTRIES-1] ldqe_l1_dump_q; +wire [57:59] ldq_reload_qw; +wire [0:`LMQ_ENTRIES-1] ldqe_relmin1_upd_gpr; +wire ldq_itag2_rel_val; +wire [0:`LMQ_ENTRIES-1] ldq_rel0_crit_qw; +wire ldq_rel1_gpr_val; +wire ldq_rel1_gpr_val_d; +wire ldq_rel1_gpr_val_q; +wire rel2_eccdet; +wire rel2_eccdet_ue; +wire rel2_eccdet_err; +wire ldq_rel2_rdat_perr; +wire [0:`LMQ_ENTRIES-1] ldq_rel0_upd_gpr_d; +wire [0:`LMQ_ENTRIES-1] ldq_rel0_upd_gpr_q; +wire [0:`LMQ_ENTRIES-1] ldq_rel1_upd_gpr_d; +wire [0:`LMQ_ENTRIES-1] ldq_rel1_upd_gpr_q; +wire [0:`LMQ_ENTRIES-1] ldq_rel2_upd_gpr_d; +wire [0:`LMQ_ENTRIES-1] ldq_rel2_upd_gpr_q; +wire [0:`LMQ_ENTRIES-1] ldq_rel3_upd_gpr_d; +wire [0:`LMQ_ENTRIES-1] ldq_rel3_upd_gpr_q; +wire [0:`LMQ_ENTRIES-1] ldq_rel1_upd_gpr; +wire [0:`LMQ_ENTRIES-1] ldqe_rel2_drop_cpl_rpt; +wire [0:`LMQ_ENTRIES-1] ldqe_rel3_drop_cpl_rpt_d; +wire [0:`LMQ_ENTRIES-1] ldqe_rel3_drop_cpl_rpt_q; +wire [0:`LMQ_ENTRIES-1] ldqe_reld_cpl_rpt; +wire [0:`LMQ_ENTRIES-1] ldq_rel2_send_cpl_ok; +wire [0:`LMQ_ENTRIES-1] ldq_rel6_send_cpl_ok; +wire [0:`LMQ_ENTRIES-1] ldq_rel_send_cpl_ok; +wire [0:`LMQ_ENTRIES-1] ldq_rel3_odq_cpl; +wire [0:`LMQ_ENTRIES-1] ldq_rel4_odq_cpl_d; +wire [0:`LMQ_ENTRIES-1] ldq_rel4_odq_cpl_q; +wire [0:`LMQ_ENTRIES-1] ldq_rel5_odq_cpl_d; +wire [0:`LMQ_ENTRIES-1] ldq_rel5_odq_cpl_q; +wire ldq_l2_req_need_send; +wire ldq_rel0_updating_cache; +wire ldq_rel1_collide_binv_d; +wire ldq_rel1_collide_binv_q; +wire [0:`LMQ_ENTRIES-1] ldq_rel1_dbeat_val; +wire ldq_stq_rel1_blk_store_d; +wire ldq_stq_rel1_blk_store_q; +wire [0:`LMQ_ENTRIES-1] ldq_rel2_qHit_clr; +wire [0:1] ldqe_qHit_clr_sel[0:`LMQ_ENTRIES-1]; +wire [0:`LMQ_ENTRIES-1] ldq_rel_qHit_clr_d; +wire [0:`LMQ_ENTRIES-1] ldq_rel_qHit_clr_q; +wire [0:1] ldqe_qHit_held_sel[0:`LMQ_ENTRIES-1]; +wire [0:`LMQ_ENTRIES-1] ldqe_qHit_held_d; +wire [0:`LMQ_ENTRIES-1] ldqe_qHit_held_q; +wire ldq_rel2_rv_clr_hold; +wire [0:`LMQ_ENTRIES-1] ldqe_available; +wire [0:`LMQ_ENTRIES-1] ldqe_cpl_rpt_done; +wire [0:`LMQ_ENTRIES-1] ldqe_need_cpl_rst; +wire [0:1] ldqe_need_cpl_sel[0:`LMQ_ENTRIES-1]; +wire [0:`LMQ_ENTRIES-1] ldqe_need_cpl_d; +wire [0:`LMQ_ENTRIES-1] ldqe_need_cpl_q; +wire [0:`LMQ_ENTRIES-1] ldqe_send_cpl; +wire [0:1] ldqe_sent_cpl_sel[0:`LMQ_ENTRIES-1]; +wire [0:`LMQ_ENTRIES-1] ldqe_sent_cpl_d; +wire [0:`LMQ_ENTRIES-1] ldqe_sent_cpl_q; +wire [0:`LMQ_ENTRIES-1] ldqe_complete; +wire [0:`LMQ_ENTRIES+`LGQ_ENTRIES-1] ldqe_remove; +wire [0:3] cpl_grpEntry_val[0:(`LMQ_ENTRIES+`LGQ_ENTRIES-1)/4]; +wire [0:3] cpl_grpEntry_sel[0:(`LMQ_ENTRIES+`LGQ_ENTRIES-1)/4]; +wire [0:(`LMQ_ENTRIES+`LGQ_ENTRIES-1)/4] cpl_grpEntry_sent; +wire [0:3] cpl_grpEntry_last_sel_d[0:(`LMQ_ENTRIES+`LGQ_ENTRIES-1)/4]; +wire [0:3] cpl_grpEntry_last_sel_q[0:(`LMQ_ENTRIES+`LGQ_ENTRIES-1)/4]; +reg [0:`ITAG_SIZE_ENC-1] cpl_grpEntry_iTag[0:(`LMQ_ENTRIES+`LGQ_ENTRIES-1)/4]; +reg [0:(`LMQ_ENTRIES+`LGQ_ENTRIES-1)/4] cpl_grpEntry_ecc; +reg [0:(`LMQ_ENTRIES+`LGQ_ENTRIES-1)/4] cpl_grpEntry_eccue; +reg [0:1] cpl_grpEntry_dvc[0:(`LMQ_ENTRIES+`LGQ_ENTRIES-1)/4]; +reg [0:3] cpl_grpEntry_dacrw[0:(`LMQ_ENTRIES+`LGQ_ENTRIES-1)/4]; +reg [0:`THREADS-1] cpl_grpEntry_tid[0:(`LMQ_ENTRIES+`LGQ_ENTRIES-1)/4]; +reg [0:(`LMQ_ENTRIES+`LGQ_ENTRIES-1)/4] cpl_grpEntry_nFlush; +reg [0:(`LMQ_ENTRIES+`LGQ_ENTRIES-1)/4] cpl_grpEntry_np1Flush; +reg [0:3] cpl_grpEntry_pEvents[0:(`LMQ_ENTRIES+`LGQ_ENTRIES-1)/4]; +reg [0:(`LMQ_ENTRIES+`LGQ_ENTRIES-1)/4] cpl_grpEntry_larx; +wire [0:3] cpl_group_val; +wire [0:3] cpl_group_sel; +wire [0:3] cpl_group_last_sel_d; +wire [0:3] cpl_group_last_sel_q; +wire cpl_credit_sent; +reg [0:`ITAG_SIZE_ENC-1] cpl_send_itag; +reg cpl_ecc_dec; +reg cpl_eccue_dec; +reg [0:1] cpl_dvc; +reg [0:3] cpl_dacrw; +reg [0:`THREADS-1] cpl_tid; +reg cpl_nFlush; +reg cpl_np1Flush; +reg [0:3] cpl_pEvents; +reg cpl_larx; +wire ldq_cpl_odq_zap; +wire ldq_cpl_odq_val; +wire ldq_cpl_odq_dbg_int_en; +wire ldq_cpl_odq_n_flush; +wire [0:3] ldq_cpl_odq_dacrw; +wire ldq_cpl_odq_eccue; +wire ldq_cpl_pending; +wire [0:`THREADS-1] ldq_execute_vld; +wire [0:`THREADS-1] odq_execute_vld; +wire [0:`THREADS-1] lq1_iu_execute_vld_d; +wire [0:`THREADS-1] lq1_iu_execute_vld_q; +wire [0:`ITAG_SIZE_ENC-1] lq1_iu_itag_d; +wire [0:`ITAG_SIZE_ENC-1] lq1_iu_itag_q; +wire lq1_iu_n_flush_d; +wire lq1_iu_n_flush_q; +wire lq1_iu_np1_flush_d; +wire lq1_iu_np1_flush_q; +wire lq1_iu_exception_val_d; +wire lq1_iu_exception_val_q; +wire ldq_cpl_dbg_int_en; +wire ldq_cpl_oth_flush; +wire ldq_cpl_n_flush; +wire ldq_cpl_np1_flush; +wire [0:1] ldq_cpl_dvc; +wire [0:3] ldq_cpl_dacrw; +wire [0:3] lq1_iu_dacrw_d; +wire [0:3] lq1_iu_dacrw_q; +wire [0:3] lq1_iu_perf_events_d; +wire [0:3] lq1_iu_perf_events_q; +wire [0:`THREADS-1] ldq_cpl_larx_d; +wire [0:`THREADS-1] ldq_cpl_larx_q; +wire [0:`THREADS-1] ldq_cpl_binv_d; +wire [0:`THREADS-1] ldq_cpl_binv_q; +wire ldq_rel_cmmt_d; +wire ldq_rel_cmmt_q; +wire ldq_rel_need_hole_d; +wire ldq_rel_need_hole_q; +wire ldq_rel_latency_d; +wire ldq_rel_latency_q; +wire [0:`THREADS-1] perf_ldq_cpl_larx; +wire [0:`THREADS-1] perf_ldq_cpl_binv; +wire perf_ldq_rel_attmpt; +wire perf_ldq_rel_cmmt; +wire perf_ldq_rel_need_hole; +wire perf_ldq_rel_latency; +wire ex4_stg_act_d; +wire ex4_stg_act_q; +wire ex5_stg_act_d; +wire ex5_stg_act_q; +wire [0:`LMQ_ENTRIES-1] ex4_ldqe_act; +wire [0:`LMQ_ENTRIES-1] ex5_ldqe_act; +wire [0:`LMQ_ENTRIES-1] ex4_lgqe_act; +wire [0:`LMQ_ENTRIES-1] ex5_lgqe_act; +reg [0:3] ldq_gath_Tag; +wire [0:`LGQ_ENTRIES-1] lgqe_wrt_ptr; +wire ld_gath_not_full; +wire [0:`LGQ_ENTRIES-1] lgqe_available; +wire [0:`LGQ_ENTRIES-1] lgqe_cpl_sent; +wire [0:`LGQ_ENTRIES-1] lgq_reset_val; +wire [0:`LGQ_ENTRIES-1] lgqe_odq_flush; +wire [0:`LGQ_ENTRIES-1] lgqe_cp_flush; +wire [0:`LGQ_ENTRIES-1] lgqe_kill; +wire [0:`LGQ_ENTRIES-1] lgqe_valid_d; +wire [0:`LGQ_ENTRIES-1] lgqe_valid_q; +wire ex4_gath_val; +wire [0:`LGQ_ENTRIES-1] ex4_lgqe_set_val; +wire [0:`LGQ_ENTRIES-1] ex4_lgqe_set_all; +wire [0:`LGQ_ENTRIES-1] ex5_lgqe_set_all_d; +wire [0:`LGQ_ENTRIES-1] ex5_lgqe_set_all_q; +wire [0:`LGQ_ENTRIES-1] ex5_lgqe_set_val_d; +wire [0:`LGQ_ENTRIES-1] ex5_lgqe_set_val_q; +wire [0:`LGQ_ENTRIES-1] ex5_lgqe_restart; +wire [0:`LGQ_ENTRIES-1] ex5_lgqe_drop; +wire ex5_lgq_restart; +wire [0:`THREADS-1] lgqe_thrd_id_d[0:`LGQ_ENTRIES-1]; +wire [0:`THREADS-1] lgqe_thrd_id_q[0:`LGQ_ENTRIES-1]; +wire [0:`LGQ_ENTRIES-1] lgqe_byte_swap_d; +wire [0:`LGQ_ENTRIES-1] lgqe_byte_swap_q; +wire [0:`LGQ_ENTRIES-1] lqg_qw_match; +wire [0:2] lgqe_set_op_size[0:`LGQ_ENTRIES-1]; +wire [0:2] lgqe_op_size_d[0:`LGQ_ENTRIES-1]; +wire [0:2] lgqe_op_size_q[0:`LGQ_ENTRIES-1]; +wire [0:AXU_TARGET_ENC-1] lgqe_set_tgpr[0:`LGQ_ENTRIES-1]; +wire [0:AXU_TARGET_ENC-1] lgqe_tgpr_d[0:`LGQ_ENTRIES-1]; +wire [0:AXU_TARGET_ENC-1] lgqe_tgpr_q[0:`LGQ_ENTRIES-1]; +wire [0:`LGQ_ENTRIES-1] lgqe_set_axu; +wire [0:`LGQ_ENTRIES-1] lgqe_axu_d; +wire [0:`LGQ_ENTRIES-1] lgqe_axu_q; +wire [0:3] lgqe_perf_events_d[0:`LGQ_ENTRIES-1]; +wire [0:3] lgqe_perf_events_q[0:`LGQ_ENTRIES-1]; +wire [0:`LGQ_ENTRIES-1] lgqe_set_algebraic; +wire [0:`LGQ_ENTRIES-1] lgqe_algebraic_d; +wire [0:`LGQ_ENTRIES-1] lgqe_algebraic_q; +wire [0:`LGQ_ENTRIES-1] lgqe_gpr_done_d; +wire [0:`LGQ_ENTRIES-1] lgqe_gpr_done_q; +wire [0:`LGQ_ENTRIES-1] lgqe_resolved; +wire [0:`LGQ_ENTRIES-1] lgqe_resolved_d; +wire [0:`LGQ_ENTRIES-1] lgqe_resolved_q; +wire [0:`LGQ_ENTRIES-1] lgqe_back_inv_nFlush_d; +wire [0:`LGQ_ENTRIES-1] lgqe_back_inv_nFlush_q; +wire [0:`LGQ_ENTRIES-1] lgqe_back_inv_np1Flush_d; +wire [0:`LGQ_ENTRIES-1] lgqe_back_inv_np1Flush_q; +wire [0:1] lgqe_set_gpr_done[0:`LGQ_ENTRIES-1]; +wire [0:1] lgqe_set_dvc[0:`LGQ_ENTRIES-1]; +wire [0:1] lgqe_dvc_d[0:`LGQ_ENTRIES-1]; +wire [0:1] lgqe_dvc_q[0:`LGQ_ENTRIES-1]; +wire [0:3] lgqe_dacrw_d[0:`LGQ_ENTRIES-1]; +wire [0:3] lgqe_dacrw_q[0:`LGQ_ENTRIES-1]; +wire [0:`ITAG_SIZE_ENC-1] lgqe_itag_d[0:`LGQ_ENTRIES-1]; +wire [0:`ITAG_SIZE_ENC-1] lgqe_itag_q[0:`LGQ_ENTRIES-1]; +wire [57:63] lgqe_p_addr_d[0:`LGQ_ENTRIES-1]; +wire [57:63] lgqe_p_addr_q[0:`LGQ_ENTRIES-1]; +wire [0:3] lgqe_ldTag_d[0:`LGQ_ENTRIES-1]; +wire [0:3] lgqe_ldTag_q[0:`LGQ_ENTRIES-1]; +wire [0:`LGQ_ENTRIES-1] ldq_gath_Tag_1hot[0:`LMQ_ENTRIES-1]; +reg [0:`LMQ_ENTRIES-1] ldqe_gather_done; +wire [0:`LGQ_ENTRIES-1] lgqe_back_inv_flush_upd; +wire [0:`THREADS-1] lgqe_cpNext_tid[0:`LGQ_ENTRIES-1]; +wire [0:`LGQ_ENTRIES-1] lgqe_cpNext_val; +wire [0:1] lgqe_upd_gpr_ecc_sel[0:`LGQ_ENTRIES-1]; +wire [0:`LGQ_ENTRIES-1] lgqe_upd_gpr_ecc; +wire [0:`LGQ_ENTRIES-1] lgqe_upd_gpr_ecc_d; +wire [0:`LGQ_ENTRIES-1] lgqe_upd_gpr_ecc_q; +wire [0:`LGQ_ENTRIES-1] lgqe_upd_gpr_eccue; +wire [0:`LGQ_ENTRIES-1] lgqe_upd_gpr_eccue_d; +wire [0:`LGQ_ENTRIES-1] lgqe_upd_gpr_eccue_q; +wire [0:`LGQ_ENTRIES-1] lgqe_cpl_rpt_done; +wire [0:`LGQ_ENTRIES-1] lgqe_need_cpl_rst; +wire [0:1] lgqe_need_cpl_sel[0:`LGQ_ENTRIES-1]; +wire [0:`LGQ_ENTRIES-1] lgqe_need_cpl_d; +wire [0:`LGQ_ENTRIES-1] lgqe_need_cpl_q; +wire [0:`LGQ_ENTRIES-1] lgqe_send_cpl; +wire lgq_rel1_gpr_val_d; +wire lgq_rel1_gpr_val_q; +wire [0:`LGQ_ENTRIES-1] lgq_rel0_upd_gpr_d; +wire [0:`LGQ_ENTRIES-1] lgq_rel0_upd_gpr_q; +wire [0:`LGQ_ENTRIES-1] lgq_rel1_upd_gpr_d; +wire [0:`LGQ_ENTRIES-1] lgq_rel1_upd_gpr_q; +wire [0:`LGQ_ENTRIES-1] lgq_rel2_upd_gpr_d; +wire [0:`LGQ_ENTRIES-1] lgq_rel2_upd_gpr_q; +wire [0:`LGQ_ENTRIES-1] lgq_rel3_upd_gpr_d; +wire [0:`LGQ_ENTRIES-1] lgq_rel3_upd_gpr_q; +wire [0:`LGQ_ENTRIES-1] lgq_rel4_upd_gpr_d; +wire [0:`LGQ_ENTRIES-1] lgq_rel4_upd_gpr_q; +wire [0:`LGQ_ENTRIES-1] lgq_rel5_upd_gpr_d; +wire [0:`LGQ_ENTRIES-1] lgq_rel5_upd_gpr_q; +wire [0:`LGQ_ENTRIES-1] lgq_rel1_upd_gpr; +wire [0:`LGQ_ENTRIES-1] lgq_rel2_upd_gpr; +wire [0:`LGQ_ENTRIES-1] lgqe_relmin1_match; +wire [0:`LGQ_ENTRIES-1] lgqe_relmin1_upd_gpr; +wire [0:`LGQ_ENTRIES-1] lgq_rel2_send_cpl_ok; +reg [0:`ITAG_SIZE_ENC-1] ldq_rel3_odq_itag; +reg ldq_rel3_odq_ecc; +reg ldq_rel3_odq_eccue; +reg [0:1] ldq_rel3_odq_dvc; +reg [0:3] ldq_rel3_odq_dacrw; +reg [0:`THREADS-1] ldq_rel3_odq_tid; +reg ldq_rel3_odq_nFlush; +reg ldq_rel3_odq_np1Flush; +reg [0:3] ldq_rel3_odq_pEvents; +wire ldq_rel3_odq_dbg_int_en; +wire ldq_rel3_odq_oth_flush; +wire [0:3] ldq_rel3_dacrw; +wire [0:`LMQ_ENTRIES-1] ldq_rel3_odq_val; +wire [0:`LGQ_ENTRIES-1] lgq_rel3_odq_val; +wire [0:`LMQ_ENTRIES-1] ldq_rel5_odq_cpl; +wire [0:`LGQ_ENTRIES-1] lgq_rel5_odq_cpl; +wire ldq_state_machines_idle; +wire ldq_relmin1_ldq_val; +wire [0:3] ldq_relmin1_cTag; +wire l2_rel0_resp_val_d; +wire l2_rel0_resp_val_q; +wire l2_rel0_resp_ldq_val_d; +wire l2_rel0_resp_ldq_val_q; +wire [0:3] l2_rel0_resp_cTag_d; +wire [0:3] l2_rel0_resp_cTag_q; +wire [57:59] l2_rel0_resp_qw_d; +wire [57:59] l2_rel0_resp_qw_q; +wire l2_rel0_resp_crit_qw_d; +wire l2_rel0_resp_crit_qw_q; +wire l2_rel0_resp_l1_dump_d; +wire l2_rel0_resp_l1_dump_q; +wire [0:2] ldq_rel0_opsize; +wire [59:63] ldq_rel0_p_addr; +wire [0:4] ldq_rel0_opsize_1hot; +wire [0:4] ldq_rel0_rot_size; +wire [0:4] ldq_rel0_rot_max_size_le; +wire [0:4] ldq_rel0_rot_sel_le; +wire [0:3] ldq_rel0_rot_sel; +wire ldq_rel0_byte_swap; +wire [0:3] ldq_rel1_algebraic_sel_d; +wire [0:3] ldq_rel1_algebraic_sel_q; +wire lvl1_sel; +wire [0:1] lvl2_sel; +wire [0:1] lvl3_sel; +wire [0:1] rotate_sel1; +wire [0:3] rotate_sel2; +wire [0:3] rotate_sel3; +wire [0:7] ldq_rel1_rot_sel1_d; +wire [0:7] ldq_rel1_rot_sel1_q; +wire [0:7] ldq_rel1_rot_sel2_d; +wire [0:7] ldq_rel1_rot_sel2_q; +wire [0:7] ldq_rel1_rot_sel3_d; +wire [0:7] ldq_rel1_rot_sel3_q; +wire [0:127] ldq_rel1_data; +wire [0:127] ldq_rel2_rot_data; +wire [0:1] ldq_rel2_dvc; +wire [0:`THREADS-1] dbg_int_en_d; +wire [0:`THREADS-1] dbg_int_en_q; +wire rdat_scan_in; +wire rdat_scan_out; + +//-------------------------- +// constants +//-------------------------- +parameter spr_xucr0_cls_offset = 0; +parameter spr_lsucr0_lge_offset = spr_xucr0_cls_offset + 1; +parameter spr_lsucr0_lca_offset = spr_lsucr0_lge_offset + 1; +parameter l2_rel0_resp_val_offset = spr_lsucr0_lca_offset + 3; +parameter l2_rel0_resp_ldq_val_offset = l2_rel0_resp_val_offset + 1; +parameter l2_rel0_resp_cTag_offset = l2_rel0_resp_ldq_val_offset + 1; +parameter l2_rel0_resp_qw_offset = l2_rel0_resp_cTag_offset + 4; +parameter l2_rel0_resp_crit_qw_offset = l2_rel0_resp_qw_offset + 3; +parameter l2_rel0_resp_l1_dump_offset = l2_rel0_resp_crit_qw_offset + 1; +parameter ldq_rel1_algebraic_sel_offset = l2_rel0_resp_l1_dump_offset + 1; +parameter ldq_rel1_rot_sel1_offset = ldq_rel1_algebraic_sel_offset + 4; +parameter ldq_rel1_rot_sel2_offset = ldq_rel1_rot_sel1_offset + 8; +parameter ldq_rel1_rot_sel3_offset = ldq_rel1_rot_sel2_offset + 8; +parameter iu_lq_cp_flush_offset = ldq_rel1_rot_sel3_offset + 8; +parameter iu_lq_cp_next_itag_offset = iu_lq_cp_flush_offset + `THREADS; +parameter odq_ldq_n_flush_offset = iu_lq_cp_next_itag_offset + (`THREADS) * (`ITAG_SIZE_ENC); +parameter odq_ldq_resolved_offset = odq_ldq_n_flush_offset + 1; +parameter odq_ldq_report_itag_offset = odq_ldq_resolved_offset + 1; +parameter odq_ldq_report_tid_offset = odq_ldq_report_itag_offset + `ITAG_SIZE_ENC; +parameter rv_lq_rvs_empty_offset = odq_ldq_report_tid_offset + `THREADS; +parameter rel2_blk_req_offset = rv_lq_rvs_empty_offset + `THREADS; +parameter rel2_rviss_blk_offset = rel2_blk_req_offset + 1; +parameter ldq_rel1_collide_binv_offset = rel2_rviss_blk_offset + 1; +parameter ldq_stq_rel1_blk_store_offset = ldq_rel1_collide_binv_offset + 1; +parameter ex4_ldreq_offset = ldq_stq_rel1_blk_store_offset + 1; +parameter ex5_ldreq_val_offset = ex4_ldreq_offset + 1; +parameter ex4_pfetch_val_offset = ex5_ldreq_val_offset + 1; +parameter ex5_pfetch_val_offset = ex4_pfetch_val_offset + 1; +parameter ex5_odq_ldreq_val_offset = ex5_pfetch_val_offset + 1; +parameter ex5_streq_val_offset = ex5_odq_ldreq_val_offset + 1; +parameter ex5_othreq_val_offset = ex5_streq_val_offset + 1; +parameter ex5_reserved_taken_offset = ex5_othreq_val_offset + 1; +parameter ex5_resv_taken_restart_offset = ex5_reserved_taken_offset + 1; +parameter lq_xu_quiesce_offset = ex5_resv_taken_restart_offset + 1; +parameter lq_pc_ldq_quiesce_offset = lq_xu_quiesce_offset + `THREADS; +parameter lq_pc_stq_quiesce_offset = lq_pc_ldq_quiesce_offset + `THREADS; +parameter lq_pc_pfetch_quiesce_offset = lq_pc_stq_quiesce_offset + `THREADS; +parameter lq_mm_lmq_stq_empty_offset = lq_pc_pfetch_quiesce_offset + `THREADS; +parameter ex5_ldq_full_offset = lq_mm_lmq_stq_empty_offset + 1; +parameter ex5_ldq_full_restart_offset = ex5_ldq_full_offset + 1; +parameter ex5_ldq_hit_offset = ex5_ldq_full_restart_offset + 1; +parameter ex5_ld_gath_offset = ex5_ldq_hit_offset + 1; +parameter ldq_full_qHit_held_offset = ex5_ld_gath_offset + 1; +parameter ldq_resv_qHit_held_offset = ldq_full_qHit_held_offset + 1; +parameter ldq_oth_qHit_clr_offset = ldq_resv_qHit_held_offset + 1; +parameter ex5_ldq_set_hold_offset = ldq_oth_qHit_clr_offset + 1; +parameter ex5_ldq_restart_offset = ex5_ldq_set_hold_offset + 1; +parameter ex6_ldq_full_offset = ex5_ldq_restart_offset + 1; +parameter ex6_ldq_hit_offset = ex6_ldq_full_offset + 1; +parameter ex5_lgq_full_offset = ex6_ldq_hit_offset + 1; +parameter ex6_lgq_full_offset = ex5_lgq_full_offset + 1; +parameter ex5_lgq_qwhit_offset = ex6_lgq_full_offset + 1; +parameter ex6_lgq_qwhit_offset = ex5_lgq_qwhit_offset + 1; +parameter ex5_p_addr_offset = ex6_lgq_qwhit_offset + 1; +parameter ex5_wimge_offset = ex5_p_addr_offset + `REAL_IFAR_WIDTH; +parameter ex6_cmmt_perf_events_offset = ex5_wimge_offset + 5; +parameter ex5_ldqe_set_all_offset = ex6_cmmt_perf_events_offset + 4; +parameter ex5_ldqe_set_val_offset = ex5_ldqe_set_all_offset + `LMQ_ENTRIES; +parameter ex6_ldqe_pfetch_val_offset = ex5_ldqe_set_val_offset + `LMQ_ENTRIES; +parameter ex7_ldqe_pfetch_val_offset = ex6_ldqe_pfetch_val_offset + `LMQ_ENTRIES; +parameter ex5_ldm_hit_offset = ex7_ldqe_pfetch_val_offset + `LMQ_ENTRIES; +parameter ldq_hold_tid_offset = ex5_ldm_hit_offset + `LMQ_ENTRIES; +parameter fifo_ldq_req_nxt_ptr_offset = ldq_hold_tid_offset + `THREADS; +parameter fifo_ldq_req_val_offset = fifo_ldq_req_nxt_ptr_offset + `LMQ_ENTRIES + 1; +parameter fifo_ldq_req_pfetch_offset = fifo_ldq_req_val_offset + `LMQ_ENTRIES; +parameter fifo_ldq_req_tid_offset = fifo_ldq_req_pfetch_offset + `LMQ_ENTRIES; +parameter fifo_ldq_req_offset = fifo_ldq_req_tid_offset + (`THREADS) * `LMQ_ENTRIES; +parameter ldqe_val_offset = fifo_ldq_req_offset + (`LMQ_ENTRIES) * `LMQ_ENTRIES; +parameter ldqe_req_cmpl_offset = ldqe_val_offset + `LMQ_ENTRIES; +parameter ldqe_cntr_reset_offset = ldqe_req_cmpl_offset + `LMQ_ENTRIES; +parameter ldqe_resent_ecc_err_offset = ldqe_cntr_reset_offset + `LMQ_ENTRIES; +parameter ldqe_reset_cpl_rpt_offset = ldqe_resent_ecc_err_offset + `LMQ_ENTRIES; +parameter ldqe_itag_offset = ldqe_reset_cpl_rpt_offset + `LMQ_ENTRIES; +parameter ldqe_thrd_id_offset = ldqe_itag_offset + (`ITAG_SIZE_ENC) * `LMQ_ENTRIES; +parameter ldqe_wimge_offset = ldqe_thrd_id_offset + `THREADS * `LMQ_ENTRIES; +parameter ldqe_byte_swap_offset = ldqe_wimge_offset + 5 * `LMQ_ENTRIES; +parameter ldqe_resv_offset = ldqe_byte_swap_offset + `LMQ_ENTRIES; +parameter ldqe_pfetch_offset = ldqe_resv_offset + `LMQ_ENTRIES; +parameter ldqe_op_size_offset = ldqe_pfetch_offset + `LMQ_ENTRIES; +parameter ldqe_tgpr_offset = ldqe_op_size_offset + 3 * `LMQ_ENTRIES; +parameter ldqe_usr_def_offset = ldqe_tgpr_offset + (`LMQ_ENTRIES) * (AXU_TARGET_ENC); +parameter ldqe_class_id_offset = ldqe_usr_def_offset + 4 * `LMQ_ENTRIES; +parameter ldqe_perf_events_offset = ldqe_class_id_offset + 2 * `LMQ_ENTRIES; +parameter ldqe_dvc_offset = ldqe_perf_events_offset + 4 * `LMQ_ENTRIES; +parameter ldqe_ttype_offset = ldqe_dvc_offset + 2 * `LMQ_ENTRIES; +parameter ldqe_dacrw_offset = ldqe_ttype_offset + 6 * `LMQ_ENTRIES; +parameter ldqe_p_addr_offset = ldqe_dacrw_offset + 4 * `LMQ_ENTRIES; +parameter ldqe_mkill_offset = ldqe_p_addr_offset + `REAL_IFAR_WIDTH * `LMQ_ENTRIES; +parameter ldqe_resolved_offset = ldqe_mkill_offset + `LMQ_ENTRIES; +parameter ldqe_back_inv_offset = ldqe_resolved_offset + `LMQ_ENTRIES; +parameter ldqe_back_inv_nFlush_offset = ldqe_back_inv_offset + `LMQ_ENTRIES; +parameter ldqe_back_inv_np1Flush_offset = ldqe_back_inv_nFlush_offset + `LMQ_ENTRIES; +parameter ldqe_beat_cntr_offset = ldqe_back_inv_np1Flush_offset + `LMQ_ENTRIES; +parameter ldqe_dRel_offset = ldqe_beat_cntr_offset + 4 * `LMQ_ENTRIES; +parameter ldqe_l1_dump_offset = ldqe_dRel_offset + `LMQ_ENTRIES; +parameter ldqe_dGpr_offset = ldqe_l1_dump_offset + `LMQ_ENTRIES; +parameter ldqe_axu_offset = ldqe_dGpr_offset + `LMQ_ENTRIES; +parameter ldqe_lock_set_offset = ldqe_axu_offset + `LMQ_ENTRIES; +parameter ldqe_watch_set_offset = ldqe_lock_set_offset + `LMQ_ENTRIES; +parameter ldqe_algebraic_offset = ldqe_watch_set_offset + `LMQ_ENTRIES; +parameter ldqe_state_offset = ldqe_algebraic_offset + `LMQ_ENTRIES; +parameter ldqe_sentRel_cntr_offset = ldqe_state_offset + 7 * `LMQ_ENTRIES; +parameter ex5_lgqe_set_all_offset = ldqe_sentRel_cntr_offset + 4 * `LMQ_ENTRIES; +parameter ex5_lgqe_set_val_offset = ex5_lgqe_set_all_offset + `LGQ_ENTRIES; +parameter lgqe_valid_offset = ex5_lgqe_set_val_offset + `LGQ_ENTRIES; +parameter lgqe_iTag_offset = lgqe_valid_offset + `LGQ_ENTRIES; +parameter lgqe_ldTag_offset = lgqe_iTag_offset + (`ITAG_SIZE_ENC) * `LGQ_ENTRIES; +parameter lgqe_thrd_id_offset = lgqe_ldTag_offset + 4 * `LGQ_ENTRIES; +parameter lgqe_byte_swap_offset = lgqe_thrd_id_offset + `THREADS * `LGQ_ENTRIES; +parameter lgqe_op_size_offset = lgqe_byte_swap_offset + `LGQ_ENTRIES; +parameter lgqe_tgpr_offset = lgqe_op_size_offset + 3 * `LGQ_ENTRIES; +parameter lgqe_gpr_done_offset = lgqe_tgpr_offset + (`LGQ_ENTRIES) * (AXU_TARGET_ENC); +parameter lgqe_resolved_offset = lgqe_gpr_done_offset + `LGQ_ENTRIES; +parameter lgqe_back_inv_nFlush_offset = lgqe_resolved_offset + `LGQ_ENTRIES; +parameter lgqe_back_inv_np1Flush_offset = lgqe_back_inv_nFlush_offset + `LGQ_ENTRIES; +parameter lgqe_dacrw_offset = lgqe_back_inv_np1Flush_offset + `LGQ_ENTRIES; +parameter lgqe_dvc_offset = lgqe_dacrw_offset + 4 * `LGQ_ENTRIES; +parameter lgqe_p_addr_offset = lgqe_dvc_offset + 2 * `LGQ_ENTRIES; +parameter lgqe_axu_offset = lgqe_p_addr_offset + 7 * `LGQ_ENTRIES; +parameter lgqe_perf_events_offset = lgqe_axu_offset + `LGQ_ENTRIES; +parameter lgqe_upd_gpr_ecc_offset = lgqe_perf_events_offset + 4 * `LGQ_ENTRIES; +parameter lgqe_upd_gpr_eccue_offset = lgqe_upd_gpr_ecc_offset + `LGQ_ENTRIES; +parameter lgqe_need_cpl_offset = lgqe_upd_gpr_eccue_offset + `LGQ_ENTRIES; +parameter lgqe_algebraic_offset = lgqe_need_cpl_offset + `LGQ_ENTRIES; +parameter ldqe_rst_eccdet_offset = lgqe_algebraic_offset + `LMQ_ENTRIES; +parameter ldq_rel2_beats_home_offset = ldqe_rst_eccdet_offset + `LMQ_ENTRIES; +parameter ldq_rel3_beats_home_offset = ldq_rel2_beats_home_offset + `LMQ_ENTRIES; +parameter ldq_rel4_beats_home_offset = ldq_rel3_beats_home_offset + `LMQ_ENTRIES; +parameter ldq_rel5_beats_home_offset = ldq_rel4_beats_home_offset + `LMQ_ENTRIES; +parameter ldq_rel1_entrySent_offset = ldq_rel5_beats_home_offset + `LMQ_ENTRIES; +parameter ldq_rel2_entrySent_offset = ldq_rel1_entrySent_offset + `LMQ_ENTRIES; +parameter ldq_rel3_entrySent_offset = ldq_rel2_entrySent_offset + `LMQ_ENTRIES; +parameter ldq_rel4_sentL1_offset = ldq_rel3_entrySent_offset + `LMQ_ENTRIES; +parameter ldq_rel5_sentL1_offset = ldq_rel4_sentL1_offset + `LMQ_ENTRIES; +parameter ldq_rel6_req_done_offset = ldq_rel5_sentL1_offset + `LMQ_ENTRIES; +parameter l2_rel1_resp_val_offset = ldq_rel6_req_done_offset + `LMQ_ENTRIES; +parameter l2_rel2_resp_val_offset = l2_rel1_resp_val_offset + 1; +parameter ldq_err_inval_rel_offset = l2_rel2_resp_val_offset + 1; +parameter ldq_err_ecc_det_offset = ldq_err_inval_rel_offset + 1; +parameter ldq_err_ue_det_offset = ldq_err_ecc_det_offset + 1; +parameter ldq_rel1_val_offset = ldq_err_ue_det_offset + 1; +parameter ldq_rel1_arb_val_offset = ldq_rel1_val_offset + 1; +parameter ldq_rel1_l1_dump_offset = ldq_rel1_arb_val_offset + 1; +parameter ldq_rel2_l1_dump_offset = ldq_rel1_l1_dump_offset + 1; +parameter ldq_rel3_l1_dump_offset = ldq_rel2_l1_dump_offset + 1; +parameter ldq_rel3_clr_relq_offset = ldq_rel3_l1_dump_offset + 1; +parameter ldq_rel1_resp_qw_offset = ldq_rel3_clr_relq_offset + 1; +parameter ldq_rel1_cTag_offset = ldq_rel1_resp_qw_offset + 3; +parameter ldq_rel1_opsize_offset = ldq_rel1_cTag_offset + 4; +parameter ldq_rel1_wimge_i_offset = ldq_rel1_opsize_offset + 3; +parameter ldq_rel1_byte_swap_offset = ldq_rel1_wimge_i_offset + 1; +parameter ldq_rel2_byte_swap_offset = ldq_rel1_byte_swap_offset + 1; +parameter ldq_rel1_p_addr_offset = ldq_rel2_byte_swap_offset + 1; +parameter ldq_rel1_dvcEn_offset = ldq_rel1_p_addr_offset + `REAL_IFAR_WIDTH; +parameter ldq_rel1_lockSet_offset = ldq_rel1_dvcEn_offset + 2; +parameter ldq_rel1_watchSet_offset = ldq_rel1_lockSet_offset + 1; +parameter ldq_rel1_tGpr_offset = ldq_rel1_watchSet_offset + 1; +parameter ldq_rel1_axu_offset = ldq_rel1_tGpr_offset + AXU_TARGET_ENC; +parameter ldq_rel1_algEn_offset = ldq_rel1_axu_offset + 1; +parameter ldq_rel1_classID_offset = ldq_rel1_algEn_offset + 1; +parameter ldq_rel1_tid_offset = ldq_rel1_classID_offset + 2; +parameter ldq_rel2_tid_offset = ldq_rel1_tid_offset + `THREADS; +parameter ldq_rel1_dir_tid_offset = ldq_rel2_tid_offset + `THREADS; +parameter ldqe_relDir_start_offset = ldq_rel1_dir_tid_offset + `THREADS; +parameter ldq_rel2_set_val_offset = ldqe_relDir_start_offset + `LMQ_ENTRIES; +parameter ldq_rel3_set_val_offset = ldq_rel2_set_val_offset + 1; +parameter ldq_rel4_set_val_offset = ldq_rel3_set_val_offset + 1; +parameter ldq_rel2_cclass_offset = ldq_rel4_set_val_offset + 1; +parameter ldq_rel3_cclass_offset = ldq_rel2_cclass_offset + (57-(64-(`DC_SIZE-3))+1); +parameter ldq_rel4_cclass_offset = ldq_rel3_cclass_offset + (57-(64-(`DC_SIZE-3))+1); +parameter ldq_rel1_data_sel_offset = ldq_rel4_cclass_offset + (57-(64-(`DC_SIZE-3))+1); +parameter ldq_rel0_l2_val_offset = ldq_rel1_data_sel_offset + 1; +parameter ldq_rel1_l2_val_offset = ldq_rel0_l2_val_offset + `LMQ_ENTRIES; +parameter ldq_rel2_l2_val_offset = ldq_rel1_l2_val_offset + `LMQ_ENTRIES; +parameter ldq_rel3_l2_val_offset = ldq_rel2_l2_val_offset + `LMQ_ENTRIES; +parameter ldq_rel4_l2_val_offset = ldq_rel3_l2_val_offset + `LMQ_ENTRIES; +parameter ldq_rel5_l2_val_offset = ldq_rel4_l2_val_offset + `LMQ_ENTRIES; +parameter ldqe_rel_eccdet_offset = ldq_rel5_l2_val_offset + `LMQ_ENTRIES; +parameter ldqe_rel_eccdet_ue_offset = ldqe_rel_eccdet_offset + `LMQ_ENTRIES; +parameter ldqe_upd_gpr_ecc_offset = ldqe_rel_eccdet_ue_offset + `LMQ_ENTRIES; +parameter ldqe_upd_gpr_eccue_offset = ldqe_upd_gpr_ecc_offset + `LMQ_ENTRIES; +parameter ldqe_need_cpl_offset = ldqe_upd_gpr_eccue_offset + `LMQ_ENTRIES; +parameter ldqe_sent_cpl_offset = ldqe_need_cpl_offset + `LMQ_ENTRIES; +parameter ldq_rel1_gpr_val_offset = ldqe_sent_cpl_offset + `LMQ_ENTRIES; +parameter ldq_rel0_upd_gpr_offset = ldq_rel1_gpr_val_offset + 1; +parameter ldq_rel1_upd_gpr_offset = ldq_rel0_upd_gpr_offset + `LMQ_ENTRIES; +parameter ldq_rel2_upd_gpr_offset = ldq_rel1_upd_gpr_offset + `LMQ_ENTRIES; +parameter ldq_rel3_upd_gpr_offset = ldq_rel2_upd_gpr_offset + `LMQ_ENTRIES; +parameter ldqe_rel3_drop_cpl_rpt_offset = ldq_rel3_upd_gpr_offset + `LMQ_ENTRIES; +parameter ldq_l2_rel0_qHitBlk_offset = ldqe_rel3_drop_cpl_rpt_offset + `LMQ_ENTRIES; +parameter lgq_rel1_gpr_val_offset = ldq_l2_rel0_qHitBlk_offset + 1; +parameter lgq_rel0_upd_gpr_offset = lgq_rel1_gpr_val_offset + 1; +parameter lgq_rel1_upd_gpr_offset = lgq_rel0_upd_gpr_offset + `LGQ_ENTRIES; +parameter lgq_rel2_upd_gpr_offset = lgq_rel1_upd_gpr_offset + `LGQ_ENTRIES; +parameter lgq_rel3_upd_gpr_offset = lgq_rel2_upd_gpr_offset + `LGQ_ENTRIES; +parameter lgq_rel4_upd_gpr_offset = lgq_rel3_upd_gpr_offset + `LGQ_ENTRIES; +parameter lgq_rel5_upd_gpr_offset = lgq_rel4_upd_gpr_offset + `LGQ_ENTRIES; +parameter ldq_rel4_odq_cpl_offset = lgq_rel5_upd_gpr_offset + `LGQ_ENTRIES; +parameter ldq_rel5_odq_cpl_offset = ldq_rel4_odq_cpl_offset + `LMQ_ENTRIES; +parameter ldq_rel_qHit_clr_offset = ldq_rel5_odq_cpl_offset + `LMQ_ENTRIES; +parameter ldqe_qHit_held_offset = ldq_rel_qHit_clr_offset + `LMQ_ENTRIES; +parameter cpl_grpEntry_last_sel_offset = ldqe_qHit_held_offset + `LMQ_ENTRIES; +parameter cpl_group_last_sel_offset = cpl_grpEntry_last_sel_offset + 4 * (((`LMQ_ENTRIES + `LGQ_ENTRIES - 1)/4) + 1); +parameter lq1_iu_execute_vld_offset = cpl_group_last_sel_offset + 4; +parameter lq1_iu_itag_offset = lq1_iu_execute_vld_offset + `THREADS; +parameter lq1_iu_n_flush_offset = lq1_iu_itag_offset + `ITAG_SIZE_ENC; +parameter lq1_iu_np1_flush_offset = lq1_iu_n_flush_offset + 1; +parameter lq1_iu_exception_val_offset = lq1_iu_np1_flush_offset + 1; +parameter lq1_iu_dacrw_offset = lq1_iu_exception_val_offset + 1; +parameter lq1_iu_perf_events_offset = lq1_iu_dacrw_offset + 4; +parameter ldq_cpl_larx_offset = lq1_iu_perf_events_offset + 4; +parameter ldq_cpl_binv_offset = ldq_cpl_larx_offset + `THREADS; +parameter ldq_rel_cmmt_offset = ldq_cpl_binv_offset + `THREADS; +parameter ldq_rel_need_hole_offset = ldq_rel_cmmt_offset + 1; +parameter ldq_rel_latency_offset = ldq_rel_need_hole_offset + 1; +parameter dbg_int_en_offset = ldq_rel_latency_offset + 1; +parameter ex4_stg_act_offset = dbg_int_en_offset + `THREADS; +parameter ex5_stg_act_offset = ex4_stg_act_offset + 1; +parameter rrot_scan_offset = ex5_stg_act_offset + 1; +parameter scan_right = rrot_scan_offset + 1 - 1; + +parameter [0:6] LDQ_IDLE = 7'b1000000; // Idle State, Wait for valid request +parameter [0:6] LDQ_VAL = 7'b0100000; // Valid Request, need to send request to L2 +parameter [0:6] LDQ_RPEN = 7'b0010000; // Waiting for Reload +parameter [0:6] LDQ_BEATM = 7'b0001000; // Mulitple Beat Request and all have arrived +parameter [0:6] LDQ_ECC = 7'b0000100; // Check for ECC error +parameter [0:6] LDQ_DCACHE = 7'b0000010; // Reload updated L1D$ with all its beats +parameter [0:6] LDQ_CMPL = 7'b0000001; // Report ITAG completion +parameter [0:4] rot_max_size = 5'b10000; + +wire tiup; +wire tidn; +wire [0:scan_right] siv; +wire [0:scan_right] sov; + + +(* analysis_not_referenced="true" *) +wire unused; + +//!! Bugspray Include: lq_ldq + +assign tiup = 1'b1; +assign tidn = 1'b0; + +assign unused = l2_lsq_resp_isComing | tidn | ldq_rel0_rot_sel_le[0] | fifo_ldq_req_wrt_ptr[8] | ldq_state_machines_idle; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// ACT Generation +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +assign ex4_stg_act_d = ctl_lsq_ex3_ldreq_val | ctl_lsq_ex3_pfetch_val; +assign ex5_stg_act_d = ex4_stg_act_q; + +// EX4 Loadmiss Queue Entry Update ACT +assign ex4_ldqe_act = ldqe_wrt_ptr & {`LMQ_ENTRIES{ex4_stg_act_q}}; +assign ex5_ldqe_act = ex5_ldqe_set_all_q & {`LMQ_ENTRIES{ex5_stg_act_q}}; +assign ex4_lgqe_act = lgqe_wrt_ptr & {`LMQ_ENTRIES{ex4_stg_act_q}}; +assign ex5_lgqe_act = ex5_lgqe_set_all_q & {`LMQ_ENTRIES{ex5_stg_act_q}}; + +// Reload Pipeline ACT +assign rel0_stg_act = ldq_reload_val; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// XU Config Bits +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +// XUCR0[CLS] 128 Byte Cacheline Enabled +// 1 => 128 Byte Cacheline +// 0 => 64 Byte Cacheline +assign spr_xucr0_cls_d = xu_lq_spr_xucr0_cls; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// LSU Config Bits +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +// LSUCR0[LGE] Load gather Enable +// 1 => load gathering enabled +// 0 => load gathering disabled +assign spr_lsucr0_lge_d = ctl_lsq_spr_lsucr0_lge; + +// LSUCR0[LCA] Loadmiss Reload Attempts Count +assign spr_lsucr0_lca_d = ctl_lsq_spr_lsucr0_lca; +assign spr_lsucr0_lca_zero = ~(|(spr_lsucr0_lca_q)); +assign spr_lsucr0_lca_ovrd = spr_lsucr0_lca_zero ? 3'b001 : spr_lsucr0_lca_q; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Completion Interface +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +assign iu_lq_cp_flush_d = iu_lq_cp_flush; +assign ex4_stg_flush = |(ctl_lsq_ex4_thrd_id & iu_lq_cp_flush_q); +assign ex5_stg_flush = |(ctl_lsq_ex5_thrd_id & iu_lq_cp_flush_q) | ctl_lsq_ex5_flush_req; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// ODQ->LDQ Resolved Interface +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +assign odq_ldq_n_flush_d = odq_ldq_resolved & odq_ldq_n_flush & ~ldq_cpl_odq_zap; +//odq_ldq_np1_flush_d <= odq_ldq_resolved and not odq_ldq_report_needed and odq_ldq_np1_flush; +assign odq_ldq_resolved_d = odq_ldq_resolved & (~odq_ldq_report_needed) & ~ldq_cpl_odq_zap; +assign odq_ldq_report_itag_d = odq_ldq_report_itag; +assign odq_ldq_report_tid_d = odq_ldq_report_tid; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// L2 Reload Interface +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +// cTag(1) = 1 => either an IU reload or MMU reload +assign l2_rel0_resp_val_d = l2_lsq_resp_val; +assign l2_rel0_resp_ldq_val_d = ldq_relmin1_ldq_val; +assign l2_rel0_resp_cTag_d = ldq_relmin1_cTag; +assign l2_rel0_resp_qw_d = l2_lsq_resp_qw; +assign l2_rel0_resp_crit_qw_d = l2_lsq_resp_crit_qw; +assign l2_rel0_resp_l1_dump_d = l2_lsq_resp_l1_dump; +assign ldq_relmin1_ldq_val = l2_lsq_resp_val & (~l2_lsq_resp_cTag[1]); +assign ldq_relmin1_cTag = {l2_lsq_resp_cTag[0], l2_lsq_resp_cTag[2:4]}; +assign ldq_rel1_data = l2_lsq_resp_data; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// LOAD QUEUE +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +// RV is empty indicator +assign rv_lq_rvs_empty_d = rv_lq_rvs_empty; + +// Need to block reloads +// 1) RV issued an instruction +// 2) Back-Invalidate Congruence Class collided with Valid Reload Set/Clear Congruence Class +// 3) SPR Directory Read Operation +// 4) REL1 attempt and ECC error detected for same core Tag + +// Need to block reloads +// 1) RV issued an instruction with valid reload set congruence class +assign ldq_rel1_set_rviss_dir_coll = |(rv_lq_vld) & rv_lq_isLoad & ldq_rel1_set_val; +// 2) Back-Invalidate Congruence Class collided with Valid Reload Set/Clear Congruence Class +assign ldq_rel1_set_binv_dir_coll = ldq_rel1_collide_binv_q & ldq_rel1_set_val; +// 3) SPR Directory Read Operation and valid reload set congruence class +assign ldq_rel1_set_rd_dir_coll = ctl_lsq_rv1_dir_rd_val & ldq_rel1_set_val; +assign rel2_blk_req_d = ldq_rel1_set_rviss_dir_coll | ldq_rel1_set_binv_dir_coll | ldq_rel1_set_rd_dir_coll; +assign rel2_rviss_blk_d = ldq_rel1_set_rviss_dir_coll; + +// EX4 Address that is used to compare against all loadmiss queue entries +assign ex4_ldreq_d = ctl_lsq_ex3_ldreq_val; +assign ex4_pfetch_val_d = ctl_lsq_ex3_pfetch_val; +assign ex4_p_addr_msk = {ctl_lsq_ex4_p_addr[64-`REAL_IFAR_WIDTH:56], (ctl_lsq_ex4_p_addr[57] | spr_xucr0_cls_q)}; +assign ex5_ldreq_val_d = ctl_lsq_ex4_ldreq_val & (~(ex4_ldq_full | ctl_lsq_ex4_dReq_val | ex4_stg_flush)); +assign ex5_ldreq_val = ex5_ldreq_val_q & ~ex5_stg_flush; +assign ex5_ldreq_flushed = ex5_ldreq_val_q & ex5_stg_flush; +assign ex5_pfetch_val_d = ex4_pfetch_val_q & (~(ex4_ldq_full | ctl_lsq_ex4_dReq_val)); +assign ex5_pfetch_val = ex5_pfetch_val_q & ~ctl_lsq_ex5_flush_pfetch; +assign ex5_pfetch_flushed = ex5_pfetch_val_q & ctl_lsq_ex5_flush_pfetch; +assign ex5_odq_ldreq_val_d = ctl_lsq_ex4_ldreq_val & (~ex4_stg_flush); +assign ex5_streq_val_d = ctl_lsq_ex4_streq_val & (~ex4_stg_flush); +assign ex5_othreq_val_d = ctl_lsq_ex4_othreq_val & (~ex4_stg_flush); +assign ex5_p_addr_d = ctl_lsq_ex4_p_addr; +assign ex5_wimge_d = ctl_lsq_ex4_wimge; + +// Performance Events that need to go to the Completion Unit +assign ex5_cmmt_events = {ctl_lsq_ex5_cmmt_events, ex5_ld_gath_q}; +assign ex5_cmmt_perf_events[0] = ctl_lsq_ex5_perf_val0 & ((ctl_lsq_ex5_perf_sel0 == 4'b1111) ? ex5_cmmt_events[11] : + (ctl_lsq_ex5_perf_sel0 == 4'b1110) ? ex5_cmmt_events[10] : + (ctl_lsq_ex5_perf_sel0 == 4'b1101) ? ex5_cmmt_events[9] : + (ctl_lsq_ex5_perf_sel0 == 4'b1100) ? ex5_cmmt_events[8] : + (ctl_lsq_ex5_perf_sel0 == 4'b1011) ? ex5_cmmt_events[7] : + (ctl_lsq_ex5_perf_sel0 == 4'b1010) ? ex5_cmmt_events[6] : + (ctl_lsq_ex5_perf_sel0 == 4'b1001) ? ex5_cmmt_events[5] : + (ctl_lsq_ex5_perf_sel0 == 4'b1000) ? ex5_cmmt_events[4] : + (ctl_lsq_ex5_perf_sel0 == 4'b0111) ? ex5_cmmt_events[3] : + (ctl_lsq_ex5_perf_sel0 == 4'b0110) ? ex5_cmmt_events[2] : + (ctl_lsq_ex5_perf_sel0 == 4'b0101) ? ex5_cmmt_events[1] : + (ctl_lsq_ex5_perf_sel0 == 4'b0100) ? ex5_cmmt_events[0] : + 1'b0); +assign ex5_cmmt_perf_events[1] = ctl_lsq_ex5_perf_val1 & ((ctl_lsq_ex5_perf_sel1 == 4'b1111) ? ex5_cmmt_events[11] : + (ctl_lsq_ex5_perf_sel1 == 4'b1110) ? ex5_cmmt_events[10] : + (ctl_lsq_ex5_perf_sel1 == 4'b1101) ? ex5_cmmt_events[9] : + (ctl_lsq_ex5_perf_sel1 == 4'b1100) ? ex5_cmmt_events[8] : + (ctl_lsq_ex5_perf_sel1 == 4'b1011) ? ex5_cmmt_events[7] : + (ctl_lsq_ex5_perf_sel1 == 4'b1010) ? ex5_cmmt_events[6] : + (ctl_lsq_ex5_perf_sel1 == 4'b1001) ? ex5_cmmt_events[5] : + (ctl_lsq_ex5_perf_sel1 == 4'b1000) ? ex5_cmmt_events[4] : + (ctl_lsq_ex5_perf_sel1 == 4'b0111) ? ex5_cmmt_events[3] : + (ctl_lsq_ex5_perf_sel1 == 4'b0110) ? ex5_cmmt_events[2] : + (ctl_lsq_ex5_perf_sel1 == 4'b0101) ? ex5_cmmt_events[1] : + (ctl_lsq_ex5_perf_sel1 == 4'b0100) ? ex5_cmmt_events[0] : + 1'b0); +assign ex5_cmmt_perf_events[2] = ctl_lsq_ex5_perf_val2 & ((ctl_lsq_ex5_perf_sel2 == 4'b1111) ? ex5_cmmt_events[11] : + (ctl_lsq_ex5_perf_sel2 == 4'b1110) ? ex5_cmmt_events[10] : + (ctl_lsq_ex5_perf_sel2 == 4'b1101) ? ex5_cmmt_events[9] : + (ctl_lsq_ex5_perf_sel2 == 4'b1100) ? ex5_cmmt_events[8] : + (ctl_lsq_ex5_perf_sel2 == 4'b1011) ? ex5_cmmt_events[7] : + (ctl_lsq_ex5_perf_sel2 == 4'b1010) ? ex5_cmmt_events[6] : + (ctl_lsq_ex5_perf_sel2 == 4'b1001) ? ex5_cmmt_events[5] : + (ctl_lsq_ex5_perf_sel2 == 4'b1000) ? ex5_cmmt_events[4] : + (ctl_lsq_ex5_perf_sel2 == 4'b0111) ? ex5_cmmt_events[3] : + (ctl_lsq_ex5_perf_sel2 == 4'b0110) ? ex5_cmmt_events[2] : + (ctl_lsq_ex5_perf_sel2 == 4'b0101) ? ex5_cmmt_events[1] : + (ctl_lsq_ex5_perf_sel2 == 4'b0100) ? ex5_cmmt_events[0] : + 1'b0); +assign ex5_cmmt_perf_events[3] = ctl_lsq_ex5_perf_val3 & ((ctl_lsq_ex5_perf_sel3 == 4'b1111) ? ex5_cmmt_events[11] : + (ctl_lsq_ex5_perf_sel3 == 4'b1110) ? ex5_cmmt_events[10] : + (ctl_lsq_ex5_perf_sel3 == 4'b1101) ? ex5_cmmt_events[9] : + (ctl_lsq_ex5_perf_sel3 == 4'b1100) ? ex5_cmmt_events[8] : + (ctl_lsq_ex5_perf_sel3 == 4'b1011) ? ex5_cmmt_events[7] : + (ctl_lsq_ex5_perf_sel3 == 4'b1010) ? ex5_cmmt_events[6] : + (ctl_lsq_ex5_perf_sel3 == 4'b1001) ? ex5_cmmt_events[5] : + (ctl_lsq_ex5_perf_sel3 == 4'b1000) ? ex5_cmmt_events[4] : + (ctl_lsq_ex5_perf_sel3 == 4'b0111) ? ex5_cmmt_events[3] : + (ctl_lsq_ex5_perf_sel3 == 4'b0110) ? ex5_cmmt_events[2] : + (ctl_lsq_ex5_perf_sel3 == 4'b0101) ? ex5_cmmt_events[1] : + (ctl_lsq_ex5_perf_sel3 == 4'b0100) ? ex5_cmmt_events[0] : + 1'b0); +assign ex6_cmmt_perf_events_d = ex5_cmmt_perf_events; + + +// Need to Mask off bit 57 of Back-Invalidate Address depending on the Cacheline Size we are running with +assign l2_back_inv_addr_msk = l2_back_inv_addr[64 - `REAL_IFAR_WIDTH:57]; + +// Init Number of expected Beats +assign ldqe_beat_init = {1'b0, ((~spr_xucr0_cls_q)), 2'b00}; + +// LDQ Entry WRT Pointer Logic +// Look for first IDLE state machine from LOADMISSQ(0) -> LOADMISSQ(`LMQ_ENTRIES-1) +assign ldqe_wrt_ptr[0] = ldqe_available[0]; +generate begin : LdPriWrt + genvar ldq; + for (ldq=1; ldq<`LMQ_ENTRIES; ldq=ldq+1) begin : LdPriWrt + assign ldqe_wrt_ptr[ldq] = &((~ldqe_available[0:ldq - 1])) & ldqe_available[ldq]; + end + end +endgenerate + +// Check for only 1 entry available +// Look for first IDLE state machine from LOADMISSQ(`LMQ_ENTRIES-1) -> LOADMISSQ(0) +assign ldqe_opposite_ptr[`LMQ_ENTRIES - 1] = ldqe_available[`LMQ_ENTRIES - 1]; +generate begin : lastMach + genvar ldq; + for (ldq = 0; ldq <= `LMQ_ENTRIES-2; ldq=ldq+1) begin : lastMach + assign ldqe_opposite_ptr[ldq] = &((~ldqe_available[ldq + 1:`LMQ_ENTRIES - 1])) & ldqe_available[ldq]; + end + end +endgenerate + +assign ex4_one_machine_avail = |(ldqe_wrt_ptr & ldqe_opposite_ptr); + +// Oldest Load can use state machine +assign ex4_oldest_load = (odq_ldq_oldest_ld_itag == ctl_lsq_ex4_itag) & |(odq_ldq_oldest_ld_tid & ctl_lsq_ex4_thrd_id); +assign ex4_reserved_taken = (ctl_lsq_ex4_ldreq_val | ex4_pfetch_val_q) & ex4_one_machine_avail & (~ex4_oldest_load); +assign ex5_reserved_taken_d = ex4_reserved_taken; +assign ex4_resv_taken_restart = ctl_lsq_ex4_ldreq_val & ex4_one_machine_avail & (~(ex4_oldest_load | ex4_stg_flush)); +assign ex5_resv_taken_restart_d = ex4_resv_taken_restart; + +// Load Queue Entry Update Control +assign ex4_ldqe_set_val = ldqe_wrt_ptr & {`LMQ_ENTRIES{((ctl_lsq_ex4_ldreq_val & (~ex4_stg_flush)) | ex4_pfetch_val_q)}}; +assign ex4_ldqe_set_all = ldqe_wrt_ptr & {`LMQ_ENTRIES{(ex4_ldreq_q | ex4_pfetch_val_q)}}; +assign ex5_ldqe_set_all_d = ex4_ldqe_set_all; +assign ex5_ldqe_set_val_d = ex4_ldqe_set_val; +assign ex5_ldm_entry = ex5_ldqe_set_val_q & {`LMQ_ENTRIES{(ex5_ldreq_val_q | ex5_pfetch_val_q)}}; +assign ex6_ldqe_pfetch_val_d = ex5_ldqe_set_all_q & {`LMQ_ENTRIES{(ex5_pfetch_val & ~ex5_drop_req_val)}}; +assign ex7_ldqe_pfetch_val_d = ex6_ldqe_pfetch_val_q; +assign ex7_pfetch_blk_val = |(ex7_ldqe_pfetch_val_q) & odq_ldq_ex7_pfetch_blk; +assign ex7_pfetch_blk_tid = ctl_lsq_ex7_thrd_id & {`THREADS{ex7_pfetch_blk_val}}; + +// Thread Quiesced OR reduce +always @(*) begin: tidQuiesce + reg [0:`THREADS-1] tidQ; + + //(* analysis_not_referenced="true" *) + + integer ldq; + tidQ = {`THREADS{1'b0}}; + for (ldq=0; ldq<`LMQ_ENTRIES; ldq=ldq+1) begin + tidQ = (ldqe_tid_inuse[ldq]) | tidQ; + end + ldq_all_req_home = ~tidQ; +end + +assign lq_xu_quiesce_d = ldq_all_req_home & stq_ldq_empty & rv_lq_rvs_empty_q & ctl_lsq_pf_empty & ctl_lsq_ldp_idle; +assign lq_mm_lmq_stq_empty_d = &(ldq_all_req_home & stq_ldq_empty & rv_lq_rvs_empty_q & ctl_lsq_pf_empty & ctl_lsq_ldp_idle); +assign lq_pc_ldq_quiesce_d = ldq_all_req_home & ctl_lsq_ldp_idle; +assign lq_pc_stq_quiesce_d = stq_ldq_empty; +assign lq_pc_pfetch_quiesce_d = ctl_lsq_pf_empty; + +generate begin : loadQ + genvar ldq; + for (ldq=0; ldq<`LMQ_ENTRIES; ldq=ldq+1) begin : loadQ + wire [0:3] ldqDummy; + assign ldqDummy = ldq[3:0]; + + // ############################################## + // ############################################## + // LDQ ENTRY State Machine + // ############################################## + // ############################################## + + assign ldqe_complete[ldq] = (ldqe_sent_cpl_q[ldq] | ldqe_kill[ldq]) & ldqe_gather_done[ldq]; + + always @(*) begin: ldqState + ldqe_nxt_state[ldq] = LDQ_IDLE; + ldqe_val_d[ldq] = ldqe_val_q[ldq]; + ldqe_req_cmpl_d[ldq] = 1'b0; + ldqe_rst_eccdet[ldq] = 1'b0; + ldqe_cntr_reset_d[ldq] = 1'b0; + ldqe_resent_ecc_err_d[ldq] = ldqe_resent_ecc_err_q[ldq]; + ldqe_ecc_err_dgpr[ldq] = 1'b0; + ldqe_reset_cpl_rpt_d[ldq] = 1'b0; + + case (ldqe_state_q[ldq]) + + // IDLE State + LDQ_IDLE : // STATE(0) + if (ex4_ldqe_set_val[ldq] == 1'b1 & ctl_lsq_ex4_dReq_val == 1'b0) begin // Instructions going to L2 + ldqe_nxt_state[ldq] = LDQ_VAL; + ldqe_val_d[ldq] = 1'b1; + ldqe_cntr_reset_d[ldq] = 1'b1; + ldqe_resent_ecc_err_d[ldq] = 1'b0; + ldqe_reset_cpl_rpt_d[ldq] = 1'b1; + end + else + begin + ldqe_nxt_state[ldq] = LDQ_IDLE; + ldqe_val_d[ldq] = 1'b0; + ldqe_cntr_reset_d[ldq] = 1'b0; + ldqe_resent_ecc_err_d[ldq] = 1'b0; + ldqe_reset_cpl_rpt_d[ldq] = 1'b1; + end + + // VALID State + LDQ_VAL : // STATE(1) + if (ex4_ldqe_set_val[ldq] == 1'b1 & ctl_lsq_ex4_dReq_val == 1'b0) begin // Load Hit in the L1D$ and back-to-back load wants to use same entry + ldqe_nxt_state[ldq] = LDQ_VAL; + ldqe_val_d[ldq] = 1'b1; + end + else if (ldqe_zap[ldq] == 1'b1 & ldqe_sent[ldq] == 1'b0) begin // Entry Zap and havent Sent + ldqe_nxt_state[ldq] = LDQ_IDLE; + ldqe_req_cmpl_d[ldq] = 1'b1; + ldqe_val_d[ldq] = 1'b0; + end + else if (ldqe_sent[ldq] == 1'b1) begin // Request sent to L2 + ldqe_nxt_state[ldq] = LDQ_RPEN; + ldqe_val_d[ldq] = 1'b0; + end + else + ldqe_nxt_state[ldq] = LDQ_VAL; + + // RELOAD PENDING State + LDQ_RPEN : // STATE(2) + if (ldqe_wimge_q[ldq][1] == 1'b1 & ldq_relmin1_l2_val[ldq] == 1'b1) // Cache-Inhibited Reload + ldqe_nxt_state[ldq] = LDQ_ECC; + else if (ldqe_wimge_q[ldq][1] == 1'b0 & ldq_relmin1_l2_val[ldq] == 1'b1) // Cacheable Reload Beat0 Received + ldqe_nxt_state[ldq] = LDQ_BEATM; + else + ldqe_nxt_state[ldq] = LDQ_RPEN; + + // RELOAD MULTIPLE BEATS State + LDQ_BEATM : // STATE(3) + if (ldq_rel1_beats_home[ldq] == 1'b1 & ldq_rel1_l2_val_q[ldq] == 1'b1) + ldqe_nxt_state[ldq] = LDQ_ECC; + else + ldqe_nxt_state[ldq] = LDQ_BEATM; + + // RELOAD CHECK ECC State + LDQ_ECC : // STATE(4) + if (ldq_rel2_l2_val_q[ldq] == 1'b1 & ldqe_rel_eccdet[ldq] == 1'b1) begin // Correctable ECC Error detected on any Beats + ldqe_nxt_state[ldq] = LDQ_RPEN; + ldqe_rst_eccdet[ldq] = 1'b1; + ldqe_cntr_reset_d[ldq] = 1'b1; + ldqe_resent_ecc_err_d[ldq] = 1'b1; + ldqe_ecc_err_dgpr[ldq] = 1'b1; + end + else if (ldq_rel2_l2_val_q[ldq] == 1'b1) // Uncorrectable or Reload Complete + ldqe_nxt_state[ldq] = LDQ_DCACHE; + else + ldqe_nxt_state[ldq] = LDQ_ECC; + + // RELOAD UPDATE CACHE State + LDQ_DCACHE : // STATE(5) + if (ldq_rel6_req_done_q[ldq] == 1'b1) begin // Data Cache and Directory has been updated + if (ldqe_complete[ldq] == 1'b1) begin // Entry was Machine Killed or Already sent completion report + ldqe_nxt_state[ldq] = LDQ_IDLE; + ldqe_reset_cpl_rpt_d[ldq] = 1'b1; + ldqe_resent_ecc_err_d[ldq] = 1'b0; + ldqe_req_cmpl_d[ldq] = 1'b1; + ldqe_rst_eccdet[ldq] = 1'b1; // Reset ECC Error Indicator + end + else + // Entry has not been Machine Killed + ldqe_nxt_state[ldq] = LDQ_CMPL; + end + else + ldqe_nxt_state[ldq] = LDQ_DCACHE; + + // COMPLETION REPORT + LDQ_CMPL : // STATE(6) + if (ldqe_complete[ldq] == 1'b1) begin // Entry was Machine Killed or Completion report returned + ldqe_nxt_state[ldq] = LDQ_IDLE; + ldqe_reset_cpl_rpt_d[ldq] = 1'b1; + ldqe_resent_ecc_err_d[ldq] = 1'b0; + ldqe_req_cmpl_d[ldq] = 1'b1; + ldqe_rst_eccdet[ldq] = 1'b1; // Reset ECC Error Indicator + end + else + ldqe_nxt_state[ldq] = LDQ_CMPL; + + default : + begin + ldqe_nxt_state[ldq] = LDQ_IDLE; + ldqe_val_d[ldq] = ldqe_val_q[ldq]; + ldqe_req_cmpl_d[ldq] = 1'b0; + ldqe_rst_eccdet[ldq] = 1'b0; + ldqe_cntr_reset_d[ldq] = 1'b0; + ldqe_resent_ecc_err_d[ldq] = ldqe_resent_ecc_err_q[ldq]; + ldqe_ecc_err_dgpr[ldq] = 1'b0; + ldqe_reset_cpl_rpt_d[ldq] = 1'b0; + end + endcase + end + + assign ldqe_state_d[ldq] = ldqe_nxt_state[ldq]; + assign ldqe_rst_eccdet_d[ldq] = ldqe_rst_eccdet[ldq]; + + // ############################################## + // Load Queue Contents + + // Drop Reload + assign ldqe_dRel_d[ldq] = ex5_ldqe_set_all_q[ldq] ? ctl_lsq_ex5_drop_rel : ldqe_dRel_q[ldq]; + + // Instructions ITAG + assign ldqe_itag_d[ldq] = ex4_ldqe_set_all[ldq] ? ctl_lsq_ex4_itag : ldqe_itag_q[ldq]; + + // Request Physical Address Bits + assign ldqe_p_addr_d[ldq] = ex4_ldqe_set_all[ldq] ? ctl_lsq_ex4_p_addr : ldqe_p_addr_q[ldq]; + + // WIMGE Bits + assign ldqe_wimge_d[ldq] = ex4_ldqe_set_all[ldq] ? ctl_lsq_ex4_wimge : ldqe_wimge_q[ldq]; + + assign ldqe_wimge_i[ldq] = ldqe_wimge_q[ldq][1]; + assign ldqe_wimge_g[ldq] = ldqe_wimge_q[ldq][3]; + + // Byte Swap Bits + assign ldqe_byte_swap_d[ldq] = ex4_ldqe_set_all[ldq] ? ctl_lsq_ex4_byte_swap : ldqe_byte_swap_q[ldq]; + + // LARX Bits + assign ldqe_resv_d[ldq] = ex4_ldqe_set_all[ldq] ? ctl_lsq_ex4_is_resv : ldqe_resv_q[ldq]; + + // PreFetch Valid Bits + assign ldqe_pfetch_d[ldq] = ex4_ldqe_set_all[ldq] ? ex4_pfetch_val_q : ldqe_pfetch_q[ldq]; + + // `THREADS Bits + assign ldqe_thrd_id_d[ldq] = ex4_ldqe_set_all[ldq] ? ctl_lsq_ex4_thrd_id : ldqe_thrd_id_q[ldq]; + + // lock_set Bits + assign ldqe_lock_set_d[ldq] = ex5_ldqe_set_all_q[ldq] ? ctl_lsq_ex5_lock_set : ldqe_lock_set_q[ldq]; + + // watch_set Bits + assign ldqe_watch_set_d[ldq] = ex5_ldqe_set_all_q[ldq] ? ctl_lsq_ex5_watch_set : ldqe_watch_set_q[ldq]; + + // op_size Bits + assign ldqe_op_size_d[ldq] = ex5_ldqe_set_all_q[ldq] ? ctl_lsq_ex5_opsize : ldqe_op_size_q[ldq]; + + // tgpr Bits + assign ldqe_tgpr_d[ldq] = ex5_ldqe_set_all_q[ldq] ? ctl_lsq_ex5_tgpr : ldqe_tgpr_q[ldq]; + + // axu Bits + assign ldqe_axu_d[ldq] = ex5_ldqe_set_all_q[ldq] ? ctl_lsq_ex5_axu_val : ldqe_axu_q[ldq]; + + // usr_def Bits + assign ldqe_usr_def_d[ldq] = ex5_ldqe_set_all_q[ldq] ? ctl_lsq_ex5_usr_def : ldqe_usr_def_q[ldq]; + + // algebraic Bits + assign ldqe_algebraic_d[ldq] = ex5_ldqe_set_all_q[ldq] ? ctl_lsq_ex5_algebraic : ldqe_algebraic_q[ldq]; + + // class_id Bits + assign ldqe_class_id_d[ldq] = ex5_ldqe_set_all_q[ldq] ? ctl_lsq_ex5_class_id : ldqe_class_id_q[ldq]; + + // performance events + assign ldqe_perf_events_d[ldq] = ex5_ldqe_set_all_q[ldq] ? ex5_cmmt_perf_events : ldqe_perf_events_q[ldq]; + + // GPR Update is done + // ldqe_set_gpr_done = "11" => This should never occur, will need bugspray here + assign ldqe_set_gpr_done[ldq] = {ex5_ldqe_set_all_q[ldq], ldq_rel2_upd_gpr_q[ldq]}; + + // DVC Bits + assign ldqe_dvc_d[ldq] = (ldqe_set_gpr_done[ldq] == 2'b01) ? ldq_rel2_dvc : + (ldqe_set_gpr_done[ldq] == 2'b00) ? ldqe_dvc_q[ldq] : + ctl_lsq_ex5_dvc; + + // ttype Bits + assign ldqe_ttype_d[ldq] = ex5_ldqe_set_all_q[ldq] ? ctl_lsq_ex5_ttype : ldqe_ttype_q[ldq]; + + // DAC Status Bits + assign ldqe_dacrw_d[ldq] = ex5_ldqe_set_all_q[ldq] ? ctl_lsq_ex5_dacrw : ldqe_dacrw_q[ldq]; + + // Load Request was restarted due to load-hit-load + assign ldqe_qHit_held_sel[ldq] = {ex4_load_qHit_upd[ldq], ldq_rel2_qHit_clr[ldq]}; + + assign ldqe_qHit_held_d[ldq] = (ldqe_qHit_held_sel[ldq] == 2'b00) ? ldqe_qHit_held_q[ldq] : + (ldqe_qHit_held_sel[ldq] == 2'b10) ? 1'b1 : + 1'b0; + + // ############################################## + + // ############################################## + // ############################################## + // LDQ Control + // ############################################## + // ############################################## + + // Request Hit Detect Logic + // Detecting QHits for loads hitting against other loadmisses, used for the entry snoop detection + assign ldqe_p_addr_msk[ldq] = {ldqe_p_addr_q[ldq][64 - `REAL_IFAR_WIDTH:56], (ldqe_p_addr_q[ldq][57] | spr_xucr0_cls_q)}; + assign ex4_addr_m_queue[ldq] = (ldqe_p_addr_msk[ldq] == ex4_p_addr_msk); + assign ex4_qw_hit_queue[ldq] = ~spr_xucr0_cls_q ? (ldqe_p_addr_q[ldq][58:59] == ctl_lsq_ex4_p_addr[58:59]) : + (ldqe_p_addr_q[ldq][57:59] == ctl_lsq_ex4_p_addr[57:59]); + assign ex4_thrd_id_m[ldq] = |(ldqe_thrd_id_q[ldq] & ctl_lsq_ex4_thrd_id); + assign ex4_larx_hit[ldq] = ex4_thrd_id_m[ldq] & ldqe_resv_q[ldq]; + assign ex4_guarded_hit[ldq] = ex4_thrd_id_m[ldq] & ldqe_wimge_g[ldq] & ctl_lsq_ex4_wimge[3]; + assign ex4_req_hit_ldq[ldq] = ex4_larx_hit[ldq] | ex4_guarded_hit[ldq] | ex4_addr_m_queue[ldq]; + + // Want to only gather from request that hasnt been sent to the L2 only if the thread matches, if the thread doesnt match, + // the request in ldm queue may get flushed and the gathered request will still be valid which causes the gathered request + // to match on an invalid reload. + // It is not thread dependent if the request has already been sent to the L2, we are guaranteed to get data back if the request in ldm queue + // is flushed. + assign ldqe_entry_gatherable[ldq] = ((ldqe_state_q[ldq][1] & ex4_thrd_id_m[ldq] & (~ex5_inv_ldqe[ldq])) | ldqe_state_q[ldq][2]) & + (~(ldq_relmin1_l2_val[ldq] | ldqe_wimge_q[ldq][1] | ldqe_resv_q[ldq])); + assign ex4_entry_gatherable[ldq] = ex4_addr_m_queue[ldq] & ctl_lsq_ex4_gath_load & spr_lsucr0_lge_q & ~ex4_qw_hit_queue[ldq]; + assign ex4_entry_gath_ld[ldq] = ex4_entry_gatherable[ldq] & ldqe_entry_gatherable[ldq] & ld_gath_not_full & ~ex4_lgq_qw_hit[ldq]; + // Performance Events + assign ex4_entry_gath_full[ldq] = ex4_entry_gatherable[ldq] & ldqe_entry_gatherable[ldq] & ~ld_gath_not_full; + assign ex4_entry_gath_qwhit[ldq] = ex4_entry_gatherable[ldq] & ldqe_entry_gatherable[ldq] & ld_gath_not_full & ex4_lgq_qw_hit[ldq]; + + // THIS STATEMENT CHANGES WHEN THE LDQ DOESNT HOLD UNRESOLVED ITAGS WHEN THE RELOAD IS COMPLETE + // WILL HAVE TO CHANGE LDQE_STATE_Q(LDQ)(2 TO 6) + // ldqe_inuse(ldq) = (ldqe_state_q(ldq)(1) and not ex5_inv_ldqe(ldq)) or or_reduce(ldqe_state_q(ldq)(2 to 5)); + assign ldqe_inuse[ldq] = (ldqe_state_q[ldq][1] & (~ex5_inv_ldqe[ldq])) | |(ldqe_state_q[ldq][2:6]); + assign ldqe_tid_inuse[ldq] = (ldqe_thrd_id_q[ldq] & {`THREADS{ldqe_inuse[ldq]}}); + assign ldqe_req_outstanding[ldq] = (ldqe_state_q[ldq][1] & (~ex5_inv_ldqe[ldq])) | |(ldqe_state_q[ldq][2:5]); + assign ldqe_tid_req_outstanding[ldq] = ldqe_thrd_id_q[ldq] & {`THREADS{ldqe_req_outstanding[ldq]}}; + assign ldqe_req_able_to_hold[ldq] = (ldqe_state_q[ldq][1] & ex4_thrd_id_m[ldq] & (~ex5_inv_ldqe[ldq])) | |(ldqe_state_q[ldq][2:5]); + assign ex4_entry_load_qHit[ldq] = ldqe_req_outstanding[ldq] & ex4_req_hit_ldq[ldq] & (ctl_lsq_ex4_ldreq_val | ex4_pfetch_val_q) & (~ctl_lsq_ex4_dReq_val); + + // Detect when to update qHit_held and when to report SET_HOLD to RV for a particular itag + assign ldqe_rel_blk_qHit_held[ldq] = ldq_rel2_qHit_clr[ldq] | ldq_rel_qHit_clr_q[ldq] | ex4_entry_gath_ld[ldq]; + assign ex4_load_qHit_upd[ldq] = ldqe_req_able_to_hold[ldq] & ex4_req_hit_ldq[ldq] & (~ldqe_rel_blk_qHit_held[ldq]) & ctl_lsq_ex4_ldreq_val & (~ctl_lsq_ex4_dReq_val); + + // Store Request Hit against outstanding Loadmiss Request + // It shouldnt matter if the outstanding load was zapped, the sync still needs to wait for the reload to complete if the request was sent out + // this is the case where a load went out, took forever to come back, got zapped while waiting for reload, sync came down the pipe, + // sync cant go out until reload is back, dci needs to look at all threads with outstanding requests, dci needs to wait until they are all back + assign ex5_ldm_hit_d[ldq] = ctl_lsq_ex4_streq_val & ldqe_req_outstanding[ldq] & (ex4_req_hit_ldq[ldq] | (ex4_thrd_id_m[ldq] & ctl_lsq_ex4_is_sync) | ctl_lsq_ex4_all_thrd_chk); + + // Entry Was Back-Invalidated + assign ldqe_back_inv[ldq] = (ldqe_p_addr_msk[ldq] == l2_back_inv_addr_msk) & ldqe_inuse[ldq] & l2_back_inv_val; + + assign ldqe_back_inv_d[ldq] = ({ex4_ldqe_set_all[ldq], ldqe_back_inv[ldq]} == 2'b00) ? ldqe_back_inv_q[ldq] : + ({ex4_ldqe_set_all[ldq], ldqe_back_inv[ldq]} == 2'b01) ? 1'b1 : + 1'b0; + + // Determine if this entry was for the CP_NEXT itag + begin : ldqeItagTid + genvar tid; + for (tid=0; tid<`THREADS; tid=tid+1) begin : ldqeItagTid + assign ldqe_cpNext_tid[ldq][tid] = ldqe_thrd_id_q[ldq][tid] & (ldqe_itag_q[ldq] == iu_lq_cp_next_itag_q[tid]); + end + end + + assign ldqe_cpNext_val[ldq] = |(ldqe_cpNext_tid[ldq]); + + // Want to Flush if the loadqueue was back-invalidated or the L1 Dump signal is on for the reload + assign ldqe_back_inv_flush_upd[ldq] = ldqe_back_inv[ldq] | ldq_rel_l1_dump[ldq]; + + // NEED TO REVISIT THIS STATEMENT, I BELIEVE THIS SCENARIO ONLY EXISTS IF THE LDQ HOLDS UNRESOLVED ITAGS WHEN THE RELOAD IS COMPLETE + // Want to only capture the first back-invalidate + // There is a hole where it was a cp_next itag when the back-invalidate hit + // then an older loadmiss went to the L2, got newer data + // another back-invalidate comes in and sets the cpnext_val indicator causing an NP1 flush + // when we really wanted an N flush + assign ldqe_back_inv_nFlush_d[ldq] = ({ex4_ldqe_set_all[ldq], ldqe_back_inv_flush_upd[ldq]} == 2'b00) ? ldqe_back_inv_nFlush_q[ldq] : + ({ex4_ldqe_set_all[ldq], ldqe_back_inv_flush_upd[ldq]} == 2'b01) ? (ldqe_back_inv_nFlush_q[ldq] | ((~ldqe_cpNext_val[ldq]))) : + 1'b0; + + assign ldqe_back_inv_np1Flush_d[ldq] = ({ex4_ldqe_set_all[ldq], ldqe_back_inv_flush_upd[ldq]} == 2'b00) ? ldqe_back_inv_np1Flush_q[ldq] : + ({ex4_ldqe_set_all[ldq], ldqe_back_inv_flush_upd[ldq]} == 2'b01) ? (ldqe_back_inv_np1Flush_q[ldq] | ldqe_cpNext_val[ldq]) : + 1'b0; + + // Load Request access to L2 Available + assign ldqe_need_l2send[ldq] = ldqe_val_q[ldq] & (~ex5_ldqe_set_all_q[ldq]); + + // Load Entry Sent to L2 + assign ldqe_sent[ldq] = ((fifo_ldq_req0_avail & fifo_ldq_req_q[0][ldq]) | // Sent from FIFO + ((ex5_ldreq_val | ex5_pfetch_val) & ex5_ldqe_set_all_q[ldq] & + (~(ex5_drop_req_val | ldq_l2_req_need_send)))) & // Sent from Pipe + arb_ldq_ldq_unit_sel; + + // entry needs to be invalidated + // 1) Load was a Load Hit in the L1D$ + // 2) There was only 1 state machine and non oldest load took it + assign ex5_inv_ldqe[ldq] = ex5_ldqe_set_all_q[ldq] & (ex5_drop_req_val | ex5_ldreq_flushed | ex5_pfetch_flushed); + + // Determine if Entry should be Flushed + // CP Flush + assign ldqe_cp_flush[ldq] = |(iu_lq_cp_flush_q & ldqe_thrd_id_q[ldq]) & ~ldqe_pfetch_q[ldq]; + + // OrderQ Flush + assign ldqe_odq_flush[ldq] = (odq_ldq_report_itag_q == ldqe_itag_q[ldq]) & |(odq_ldq_report_tid_q & ldqe_thrd_id_q[ldq]) & odq_ldq_n_flush_q; + + // OrderQ Prefetch Block due to the prefetch would have caused an NFlush of user code + assign ldqe_pfetch_flush[ldq] = ex7_ldqe_pfetch_val_q[ldq] & odq_ldq_ex7_pfetch_blk; + + assign ldqe_flush[ldq] = (ldqe_cp_flush[ldq] | ldqe_odq_flush[ldq] | ldqe_pfetch_flush[ldq]) & (~ldqe_state_q[ldq][0]); + + // Entry is Deleted when the entry is flushed or when we determine the entry was a load hit + assign ldqe_mkill[ldq] = ldqe_flush[ldq]; + assign ldqe_kill[ldq] = ldqe_mkill[ldq] | ldqe_mkill_q[ldq]; + assign ldqe_zap[ldq] = ldqe_mkill[ldq] | ex5_inv_ldqe[ldq]; + + // Load Request got Machine Killed + assign ldqe_mkill_d[ldq] = ({ex4_ldqe_set_all[ldq], ldqe_mkill[ldq]} == 2'b00) ? ldqe_mkill_q[ldq] : + ({ex4_ldqe_set_all[ldq], ldqe_mkill[ldq]} == 2'b01) ? 1'b1 : + 1'b0; + + // Load Entry Has Resolved In Order Queue + assign ldqe_resolved[ldq] = (ldqe_itag_q[ldq] == odq_ldq_report_itag_q) & |(odq_ldq_report_tid_q & ldqe_thrd_id_q[ldq]) & odq_ldq_resolved_q & (~ldqe_state_q[ldq][0]); + + assign ldqe_resolved_d[ldq] = ({ex4_ldqe_set_all[ldq], ldqe_resolved[ldq]} == 2'b00) ? ldqe_resolved_q[ldq] : + ({ex4_ldqe_set_all[ldq], ldqe_resolved[ldq]} == 2'b01) ? 1'b1 : + 1'b0; + + // ############################################## + // ############################################## + // LDQ Reload Control + // ############################################## + // ############################################## + + // Reload for Entry is valid + assign ldqe_ctrl_act[ldq] = ~ldqe_state_q[ldq][0]; + assign ldqe_rel_inprog[ldq] = |(ldqe_state_q[ldq][2:3]); + assign ldqe_rel0_cTag[ldq] = (ldqDummy == ldq_resp_cTag); + assign ldqe_rel1_cTag[ldq] = (ldqDummy == ldq_rel1_cTag_q); + assign ldqe_relmin1_cTag[ldq] = (ldqDummy == ldq_relmin1_cTag); + assign ldq_relmin1_l2_val[ldq] = ldq_relmin1_ldq_val & ldqe_relmin1_cTag[ldq] & ldqe_rel_inprog[ldq]; + assign ldq_rel0_l2_val_d[ldq] = ldq_relmin1_l2_val[ldq]; + assign ldq_relmin1_l2_inval[ldq] = ldq_relmin1_ldq_val & ldqe_relmin1_cTag[ldq] & (~ldqe_rel_inprog[ldq]); + assign ldq_rel_l1_dump[ldq] = ldq_rel0_l2_val_q[ldq] & l2_rel0_resp_l1_dump_q; + assign ldq_rel0_arb_sent[ldq] = ldq_rel0_arb_val & ldqe_rel0_cTag[ldq]; + assign ldq_rel_l2_l1dumpBlk[ldq] = ldq_rel0_l2_val_q[ldq] & l2_rel0_resp_l1_dump_q & (ldqe_watch_set_q[ldq] | ldqe_lock_set_q[ldq]); + assign ldq_relmin1_l2_qHitBlk[ldq] = ldqe_relmin1_cTag[ldq] & ldqe_qHit_held_q[ldq]; + // Reload Data Queue Parity Error should cause an NFlush only if the request was a DCBT[ST]LS or an LDAWX + assign ldqe_cpNext_ecc_err[ldq] = (ldqe_lock_set_q[ldq] | ldqe_watch_set_q[ldq]) & (ldqe_resent_ecc_err_q[ldq] | ldqe_rel_rdat_perr[ldq]); + + // Either L2 Reload or Reload ARB is valid + assign ldq_rel0_entrySent[ldq] = ldq_reload_val & ldqe_rel0_cTag[ldq] & (~(ldqe_wimge_i[ldq] | ldqe_drop_reload_val[ldq] | ldq_rel_l1_dump[ldq])); + assign ldq_rel1_entrySent_d[ldq] = ldq_rel0_entrySent[ldq] & ~ldqe_rst_eccdet_q[ldq]; + assign ldq_rel2_entrySent_d[ldq] = ldq_rel1_entrySent_q[ldq] & ~ldqe_rst_eccdet_q[ldq]; + assign ldq_rel3_entrySent_d[ldq] = ldq_rel2_entrySent_q[ldq] & ~ldqe_rst_eccdet_q[ldq]; + + // L2 reload is valid + assign ldq_rel1_l2_val_d[ldq] = ldq_rel0_l2_val_q[ldq]; + assign ldq_rel2_l2_val_d[ldq] = ldq_rel1_l2_val_q[ldq]; + assign ldq_rel3_l2_val_d[ldq] = ldq_rel2_l2_val_q[ldq] & (~ldqe_rel_eccdet[ldq]); + assign ldq_rel4_l2_val_d[ldq] = ldq_rel3_l2_val_q[ldq]; + assign ldq_rel5_l2_val_d[ldq] = ldq_rel4_l2_val_q[ldq]; + + // L1 Reload is complete, Data Cache has been updated + assign ldq_rel4_sentL1_d[ldq] = ldq_rel3_entrySent_q[ldq] & ldqe_sentL1[ldq]; + assign ldq_rel5_sentL1_d[ldq] = ldq_rel4_sentL1_q[ldq]; + + // Request is complete for REL6 type requests + // I=1 load L2 only load + assign ldq_rel5_req_noL1done[ldq] = ldq_rel5_l2_val_q[ldq] & (ldqe_wimge_i[ldq] | (ldqe_drop_reload_val[ldq] & ldq_rel5_beats_home_q[ldq])); + // I=0 L1 Load + assign ldq_rel5_req_done[ldq] = ldq_rel5_sentL1_q[ldq] | ldq_rel5_req_noL1done[ldq]; + assign ldq_rel6_req_done_d[ldq] = ldq_rel5_req_done[ldq]; + + // Cache-Inhibited Reload is complete + assign ldq_rel2_ci_done[ldq] = ldq_rel2_l2_val_q[ldq] & ldqe_wimge_i[ldq]; + + // Drop Cacheable Reload is complete + assign ldq_rel2_drel_done[ldq] = ldq_rel2_l2_val_q[ldq] & ldqe_drop_reload_val[ldq] & ldq_rel2_beats_home_q[ldq]; + + // Increment Beat Counter + assign ldqe_beat_ctrl[ldq] = {ldqe_cntr_reset_q[ldq], ldq_rel0_l2_val_q[ldq]}; + assign ldqe_beat_incr[ldq] = ldqe_beat_cntr_q[ldq] + 4'b0001; + + assign ldqe_beat_cntr_d[ldq] = (ldqe_beat_ctrl[ldq] == 2'b01) ? ldqe_beat_incr[ldq] : + (ldqe_beat_ctrl[ldq] == 2'b00) ? ldqe_beat_cntr_q[ldq] : + ldqe_beat_init; + + // All Reload Data Beats Recieved + assign ldq_rel1_beats_home[ldq] = ldqe_beat_cntr_q[ldq][0]; + assign ldq_rel2_beats_home_d[ldq] = ldq_rel1_beats_home[ldq]; + assign ldq_rel3_beats_home_d[ldq] = ldq_rel2_beats_home_q[ldq]; + assign ldq_rel4_beats_home_d[ldq] = ldq_rel3_beats_home_q[ldq]; + assign ldq_rel5_beats_home_d[ldq] = ldq_rel4_beats_home_q[ldq]; + + // Reload Critical Quadword beat valid, update regfile + assign ldqe_relmin1_upd_gpr[ldq] = l2_lsq_resp_crit_qw & ldq_relmin1_l2_val[ldq] & (~ldqe_dGpr_q[ldq]); + assign ldq_rel0_upd_gpr_d[ldq] = ldqe_relmin1_upd_gpr[ldq]; + assign ldq_rel0_crit_qw[ldq] = l2_rel0_resp_crit_qw_q & ldq_rel0_l2_val_q[ldq]; + + // Need to Drop Regfile update when the LDQ entry is zapped or if its a touch type operation or + // first reload got an ecc error + assign ldqe_dGpr_cntrl[ldq][0] = ldqe_zap[ldq] | ldqe_ecc_err_dgpr[ldq]; + assign ldqe_dGpr_cntrl[ldq][1] = ex5_ldqe_set_all_q[ldq]; + + assign ldqe_dGpr_d[ldq] = (ldqe_dGpr_cntrl[ldq] == 2'b01) ? (~ctl_lsq_ex5_not_touch) : + (ldqe_dGpr_cntrl[ldq] == 2'b00) ? ldqe_dGpr_q[ldq] : + 1'b1; + + // ECC Error Detect Logic + assign ldqe_rel_eccdet_sel[ldq] = {ldq_rel2_l2_val_q[ldq], ldqe_rst_eccdet_q[ldq]}; + + assign ldqe_rel_eccdet[ldq] = (ldqe_rel_eccdet_sel[ldq] == 2'b10) ? (ldqe_rel_eccdet_q[ldq] | l2_lsq_resp_ecc_err) : + (ldqe_rel_eccdet_sel[ldq] == 2'b00) ? ldqe_rel_eccdet_q[ldq] : + 1'b0; + assign ldqe_rel_eccdet_d[ldq] = ldqe_rel_eccdet[ldq]; + + assign ldqe_rel_eccdet_ue[ldq] = (ldqe_rel_eccdet_sel[ldq] == 2'b10) ? (ldqe_rel_eccdet_ue_q[ldq] | l2_lsq_resp_ecc_err_ue) : + (ldqe_rel_eccdet_sel[ldq] == 2'b00) ? ldqe_rel_eccdet_ue_q[ldq] : + 1'b0; + assign ldqe_rel_eccdet_ue_d[ldq] = ldqe_rel_eccdet_ue[ldq]; + + // ECC Error was detected on the GPR update + assign ldqe_upd_gpr_ecc_sel[ldq] = {ldq_rel2_l2_val_q[ldq], ldqe_reset_cpl_rpt_q[ldq]}; + + assign ldqe_upd_gpr_ecc[ldq] = (ldqe_upd_gpr_ecc_sel[ldq] == 2'b10) ? (ldqe_upd_gpr_ecc_q[ldq] | ldq_rel2_gpr_ecc_err[ldq]) : + (ldqe_upd_gpr_ecc_sel[ldq] == 2'b00) ? ldqe_upd_gpr_ecc_q[ldq] : + 1'b0; + assign ldqe_upd_gpr_ecc_d[ldq] = ldqe_upd_gpr_ecc[ldq]; + + assign ldqe_upd_gpr_eccue[ldq] = (ldqe_upd_gpr_ecc_sel[ldq] == 2'b10) ? (ldqe_upd_gpr_eccue_q[ldq] | ldq_rel2_gpr_eccue_err[ldq]) : + (ldqe_upd_gpr_ecc_sel[ldq] == 2'b00) ? ldqe_upd_gpr_eccue_q[ldq] : + 1'b0; + assign ldqe_upd_gpr_eccue_d[ldq] = ldqe_upd_gpr_eccue[ldq]; + + // ECC error detected, need to create an NFlush + assign ldqe_nFlush_ecc_err[ldq] = ldqe_upd_gpr_ecc_q[ldq] | ldqe_cpNext_ecc_err[ldq]; + + // LoadQ Available, State Machine is IDLE + assign ldqe_available[ldq] = ldqe_state_q[ldq][0] | (ldqe_state_q[ldq][1] & ex5_inv_ldqe[ldq]); + + // LoadQ Entry is complete, Waiting to send Completion Report + assign ldqe_cpl_rpt_done[ldq] = ldqe_cpl_sent[ldq] | ldq_rel5_odq_cpl[ldq]; + assign ldqe_need_cpl_rst[ldq] = ldqe_cpl_rpt_done[ldq] | ldqe_kill[ldq]; + assign ldqe_need_cpl_sel[ldq] = {ldqe_need_cpl_rst[ldq], ldq_rel_send_cpl_ok[ldq]}; + + assign ldqe_need_cpl_d[ldq] = (ldqe_need_cpl_sel[ldq] == 2'b00) ? ldqe_need_cpl_q[ldq] : + (ldqe_need_cpl_sel[ldq] == 2'b01) ? 1'b1 : + 1'b0; + + assign ldqe_send_cpl[ldq] = ldqe_need_cpl_q[ldq] & ldqe_resolved_q[ldq]; + + // LoadQ Entry Sent Completion Report Indicator + assign ldqe_sent_cpl_sel[ldq] = {ldqe_reset_cpl_rpt_q[ldq], ldqe_cpl_rpt_done[ldq]}; + + assign ldqe_sent_cpl_d[ldq] = (ldqe_sent_cpl_sel[ldq] == 2'b00) ? ldqe_sent_cpl_q[ldq] : + (ldqe_sent_cpl_sel[ldq] == 2'b01) ? 1'b1 : + 1'b0; + + // Block the setting of qHit_held if reload is completeing and is in rel2 until the state machine is freed up + assign ldqe_qHit_clr_sel[ldq] = {ldq_rel2_qHit_clr[ldq], ldqe_reset_cpl_rpt_q[ldq]}; + + assign ldq_rel_qHit_clr_d[ldq] = (ldqe_qHit_clr_sel[ldq] == 2'b00) ? ldq_rel_qHit_clr_q[ldq] : + (ldqe_qHit_clr_sel[ldq] == 2'b10) ? 1'b1 : + 1'b0; + + // Drop Reload due to L1 Dump + assign ldqe_rel_l1_dump_ctrl[ldq] = {ldq_rel_l1_dump[ldq], ldqe_cntr_reset_q[ldq]}; + assign ldqe_l1_dump_d[ldq] = (ldqe_rel_l1_dump_ctrl[ldq] == 2'b10) ? ldq_rel_l1_dump[ldq] : + (ldqe_rel_l1_dump_ctrl[ldq] == 2'b00) ? ldqe_l1_dump_q[ldq] : + 1'b0; + + assign ldqe_drop_reload_val[ldq] = ldqe_l1_dump_q[ldq] | ldqe_dRel_q[ldq]; + + // Reload Data Beat is Valid + assign ldq_rel1_dbeat_val[ldq] = ldq_rel1_l2_val_q[ldq] & (~(ldqe_wimge_i[ldq] | ldqe_drop_reload_val[ldq])); + + // Reload Queue Entry was not restarted + assign ldq_rel2_sentL1[ldq] = ldq_rel2_entrySent_q[ldq] & (~rel2_blk_req_q); + + // Reload Queue Entry was restarted + assign ldq_rel2_sentL1_blk[ldq] = ldq_rel2_entrySent_q[ldq] & rel2_rviss_blk_q; + + // Sent to L1 Beat Counter + // Should indicate when all data beats have been sent to the L1 + // including beats coming from both L2 Reload and Reload Arbiters + assign ldqe_sentRel_ctrl[ldq] = {ldqe_cntr_reset_q[ldq], ldq_rel2_sentL1[ldq]}; + assign ldqe_sentRel_incr[ldq] = ldqe_sentRel_cntr_q[ldq] + 4'b0001; + + assign ldqe_sentRel_cntr_d[ldq] = (ldqe_sentRel_ctrl[ldq] == 2'b00) ? ldqe_sentRel_cntr_q[ldq] : + (ldqe_sentRel_ctrl[ldq] == 2'b01) ? ldqe_sentRel_incr[ldq] : + ldqe_beat_init; + + // All Reload Data Beats Recieved + assign ldqe_sentL1[ldq] = ldqe_sentRel_cntr_q[ldq][0]; + + // L1 Data Cache has been updated, Send CLR_HOLD report to RV + assign ldqe_rel2_l1upd_cmpl[ldq] = ldq_rel2_sentL1[ldq] & &(ldqe_sentRel_cntr_q[ldq][1:3]); + + // Need to Determine Last Data Beat to be sent to the L1 + // The last beat missing is when the cntr=7 + assign ldqe_last_beat[ldq] = &(ldqe_sentRel_cntr_d[ldq][1:3]); + + // Reload has Determined a Way to update + assign ldqe_rel_start_ctrl[ldq][0] = ldqe_cntr_reset_q[ldq]; + assign ldqe_rel_start_ctrl[ldq][1] = ldq_rel2_sentL1[ldq] & (~ldqe_relDir_start_q[ldq]); + assign ldqe_relDir_start[ldq] = (ldqe_rel_start_ctrl[ldq] == 2'b00) ? ldqe_relDir_start_q[ldq] : + (ldqe_rel_start_ctrl[ldq] == 2'b01) ? 1'b1 : + 1'b0; + + assign ldqe_relDir_start_d[ldq] = ldqe_relDir_start[ldq]; + end + end +endgenerate + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// LOAD GATHERING QUEUE +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +// determine load tag for the ldq entry that will be gathered into + +always @(*) begin: ldq_gath_Tag_P + reg [0:3] tag; + + //(* analysis_not_referenced="true" *) + + integer ldq; + tag = 4'b0000; + for (ldq=0; ldq<`LMQ_ENTRIES; ldq=ldq+1) + tag = (ldq[3:0] & {4{ex4_entry_gath_ld[ldq]}}) | tag; + ldq_gath_Tag = tag; +end + +// determine if the ex4 load hits against the load gather queue + +always @(*) begin: lgq_qw_hit_P + reg [0:`LMQ_ENTRIES-1] hit; + + //(* analysis_not_referenced="true" *) + + integer lgq; + hit = {`LMQ_ENTRIES{1'b0}}; + for (lgq=0; lgq<`LGQ_ENTRIES; lgq=lgq+1) + hit = (ldq_gath_Tag_1hot[lgq] & {`LMQ_ENTRIES{(lgqe_valid_q[lgq] & lqg_qw_match[lgq])}}) | hit; + ex4_lgq_qw_hit = hit; +end + +// LGQ Entry WRT Pointer Logic +// Look for first available entry +assign lgqe_available = (~lgqe_valid_q); + +assign lgqe_wrt_ptr[0] = lgqe_available[0]; +generate begin : LgPriWrt + genvar lgq; + for (lgq=1; lgq<`LGQ_ENTRIES; lgq=lgq+1) begin : LgPriWrt + assign lgqe_wrt_ptr[lgq] = &((~lgqe_available[0:lgq - 1])) & lgqe_available[lgq]; + end + end +endgenerate + +assign ld_gath_not_full = |(lgqe_available); + +// removed prefetcher from the equation +// should never gather a prefetch +assign ex4_gath_val = ctl_lsq_ex4_ldreq_val & ex4_ld_gath & (~ex4_stg_flush); +assign ex4_lgqe_set_val = lgqe_wrt_ptr & {`LGQ_ENTRIES{ex4_gath_val}}; +assign ex4_lgqe_set_all = lgqe_wrt_ptr & {`LGQ_ENTRIES{ex4_ldreq_q}}; +assign ex5_lgqe_set_all_d = ex4_lgqe_set_all; +assign ex5_lgqe_set_val_d = ex4_lgqe_set_val; + +generate begin : load_gath_Q + genvar lgq; + for (lgq=0; lgq<`LGQ_ENTRIES; lgq=lgq+1) begin : load_gath_Q + + // Gathered and Reload at same cycle, need to restart gathered entry + assign ex5_lgqe_restart[lgq] = ex5_lgqe_set_val_q[lgq] & ldq_relmin1_ldq_val & (lgqe_ldTag_q[lgq] == ldq_relmin1_cTag); + assign ex5_lgqe_drop[lgq] = ex5_lgqe_set_val_q[lgq] & ex5_drop_gath; + + // Determine if Entry should be Flushed + // CP Flush + assign lgqe_cp_flush[lgq] = |(iu_lq_cp_flush_q & lgqe_thrd_id_q[lgq]) & lgqe_valid_q[lgq]; + + // OrderQ Flush + assign lgqe_odq_flush[lgq] = (odq_ldq_report_itag_q == lgqe_itag_q[lgq]) & |(odq_ldq_report_tid_q & lgqe_thrd_id_q[lgq]) & odq_ldq_n_flush_q; + assign lgqe_kill[lgq] = lgqe_cp_flush[lgq] | lgqe_odq_flush[lgq]; + + assign lgq_reset_val[lgq] = lgqe_cpl_rpt_done[lgq] | ex5_lgqe_drop[lgq] | lgqe_kill[lgq]; + + assign lgqe_valid_d[lgq] = ex4_lgqe_set_val[lgq] ? 1'b1 : + lgq_reset_val[lgq] ? 1'b0 : lgqe_valid_q[lgq]; + + // Instructions ITAG + assign lgqe_itag_d[lgq] = ex4_lgqe_set_all[lgq] ? ctl_lsq_ex4_itag : lgqe_itag_q[lgq]; + + // `THREADS Bits + assign lgqe_thrd_id_d[lgq] = ex4_lgqe_set_all[lgq] ? ctl_lsq_ex4_thrd_id : lgqe_thrd_id_q[lgq]; + + // Core TAG of load entry being gathered into + assign lgqe_ldTag_d[lgq] = ex4_lgqe_set_all[lgq] ? ldq_gath_Tag : lgqe_ldTag_q[lgq]; + + // create a 1-hot core tag for each gather queue entry + begin : ldq_gath_Tag_1hot_G + genvar ldq; + for (ldq=0; ldq<`LMQ_ENTRIES; ldq=ldq+1) begin : ldq_gath_Tag_1hot_G + wire [0:3] ldqDummy; + assign ldqDummy = ldq[3:0]; + assign ldq_gath_Tag_1hot[lgq][ldq] = lgqe_ldTag_q[lgq] == ldqDummy; + end + end + + // Request Physical Address QW select Bits + assign lgqe_p_addr_d[lgq] = ex4_lgqe_set_all[lgq] ? ctl_lsq_ex4_p_addr[57:63] : lgqe_p_addr_q[lgq]; + + assign lqg_qw_match[lgq] = ~spr_xucr0_cls_q ? (lgqe_p_addr_q[lgq][58:59] == ctl_lsq_ex4_p_addr[58:59]) : + (lgqe_p_addr_q[lgq][57:59] == ctl_lsq_ex4_p_addr[57:59]); + + // Byte Swap Bits + assign lgqe_byte_swap_d[lgq] = ex4_lgqe_set_all[lgq] ? ctl_lsq_ex4_byte_swap : lgqe_byte_swap_q[lgq]; + + // GPR Update is done + // lgqe_set_gpr_done = "11" => This should never occur, will need bugspray here + assign lgqe_set_gpr_done[lgq] = {ex4_lgqe_set_all[lgq], lgq_rel2_upd_gpr_q[lgq]}; + + // GPR Update is Done Indicator + assign lgqe_gpr_done_d[lgq] = (lgqe_set_gpr_done[lgq] == 2'b00) ? lgqe_gpr_done_q[lgq] : + (lgqe_set_gpr_done[lgq] == 2'b01) ? 1'b1 : + 1'b0; + + // op_size Bits + assign lgqe_set_op_size[lgq] = ex5_lgqe_set_all_q[lgq] ? ctl_lsq_ex5_opsize : lgqe_op_size_q[lgq]; + + assign lgqe_op_size_d[lgq] = lgqe_set_op_size[lgq]; + + // tgpr Bits + assign lgqe_set_tgpr[lgq] = ex5_lgqe_set_all_q[lgq] ? ctl_lsq_ex5_tgpr : lgqe_tgpr_q[lgq]; + + assign lgqe_tgpr_d[lgq] = lgqe_set_tgpr[lgq]; + + // axu Bits + assign lgqe_set_axu[lgq] = ex5_lgqe_set_all_q[lgq] ? ctl_lsq_ex5_axu_val : lgqe_axu_q[lgq]; + + assign lgqe_axu_d[lgq] = lgqe_set_axu[lgq]; + + // performance events + assign lgqe_perf_events_d[lgq] = ex5_lgqe_set_all_q[lgq] ? ex5_cmmt_perf_events : lgqe_perf_events_q[lgq]; + + // algebraic Bits + assign lgqe_set_algebraic[lgq] = ex5_lgqe_set_all_q[lgq] ? ctl_lsq_ex5_algebraic : lgqe_algebraic_q[lgq]; + + assign lgqe_algebraic_d[lgq] = lgqe_set_algebraic[lgq]; + + // DAC Status Bits + assign lgqe_dacrw_d[lgq] = ex5_lgqe_set_all_q[lgq] ? ctl_lsq_ex5_dacrw : lgqe_dacrw_q[lgq]; + + // DVC Bits + // Need to split it out for timing since we can be setting in ex5 and + // the quadword reload is valid the same cycle + // Should never see ex5_lgqe_set_all_q = '1' and lgq_rel4_upd_gpr_q = '1' at the same time + assign lgqe_set_dvc[lgq] = ex5_lgqe_set_all_q[lgq] ? ctl_lsq_ex5_dvc : lgqe_dvc_q[lgq]; + + assign lgqe_dvc_d[lgq] = lgq_rel2_upd_gpr_q[lgq] ? ldq_rel2_dvc : lgqe_set_dvc[lgq]; + + // Want to Flush if the loadqueue was back-invalidated or the L1 Dump signal is on for the reload + // Use back inv bits from the corresponding lmq entry + assign lgqe_back_inv_flush_upd[lgq] = |((ldqe_back_inv_q | ldq_rel_l1_dump) & ldq_gath_Tag_1hot[lgq]); + + // Determine if request is CP_NEXT itag + begin : lgqeItagTid + genvar tid; + for (tid=0; tid<`THREADS; tid=tid+1) begin : lgqeItagTid + assign lgqe_cpNext_tid[lgq][tid] = lgqe_thrd_id_q[lgq][tid] & (lgqe_itag_q[lgq] == iu_lq_cp_next_itag_q[tid]); + end + end + + assign lgqe_cpNext_val[lgq] = |(lgqe_cpNext_tid[lgq]); + + // NEED TO REVISIT THIS STATEMENT, I BELIEVE THIS SCENARIO ONLY EXISTS IF THE LDQ HOLDS UNRESOLVED ITAGS WHEN THE RELOAD IS COMPLETE + // Want to only capture the first back-invalidate + // There is a hole where it was a cp_next itag when the back-invalidate hit + // then an older loadmiss went to the L2, got newer data + // another back-invalidate comes in and sets the cpnext_val indicator causing an NP1 flush + // when we really wanted an N flush + + // Take a snapshot of the CP_NEXT check whenever the loadmiss queue entry was back-invalidated + assign lgqe_back_inv_nFlush_d[lgq] = ({ex4_lgqe_set_all[lgq], lgqe_back_inv_flush_upd[lgq]} == 2'b00) ? lgqe_back_inv_nFlush_q[lgq] : + ({ex4_lgqe_set_all[lgq], lgqe_back_inv_flush_upd[lgq]} == 2'b01) ? (lgqe_back_inv_nFlush_q[lgq] | ((~lgqe_cpNext_val[lgq]))) : + 1'b0; + + assign lgqe_back_inv_np1Flush_d[lgq] = ({ex4_lgqe_set_all[lgq], lgqe_back_inv_flush_upd[lgq]} == 2'b00) ? lgqe_back_inv_np1Flush_q[lgq] : + ({ex4_lgqe_set_all[lgq], lgqe_back_inv_flush_upd[lgq]} == 2'b01) ? (lgqe_back_inv_np1Flush_q[lgq] | lgqe_cpNext_val[lgq]) : + 1'b0; + + // ############################################## + // LGQ Reload Control + // ############################################## + assign lgqe_relmin1_match[lgq] = (ldq_relmin1_cTag == lgqe_ldTag_q[lgq]) & + ((l2_lsq_resp_qw[57] == lgqe_p_addr_q[lgq][57]) | (~spr_xucr0_cls_q)) & + (l2_lsq_resp_qw[58:59] == lgqe_p_addr_q[lgq][58:59]) & lgqe_valid_q[lgq]; + assign lgqe_relmin1_upd_gpr[lgq] = lgqe_relmin1_match[lgq] & ldq_relmin1_ldq_val & (~(lgqe_gpr_done_q[lgq] | ex5_lgqe_set_val_q[lgq])); + assign lgq_rel0_upd_gpr_d[lgq] = lgqe_relmin1_upd_gpr[lgq] & (~lgqe_kill[lgq]); + + // Load Gather Entry Has Resolved In Order Queue + assign lgqe_resolved[lgq] = (lgqe_itag_q[lgq] == odq_ldq_report_itag_q) & |(odq_ldq_report_tid_q & lgqe_thrd_id_q[lgq]) & odq_ldq_resolved_q & lgqe_valid_q[lgq]; + + assign lgqe_resolved_d[lgq] = ({ex4_lgqe_set_all[lgq], lgqe_resolved[lgq]} == 2'b00) ? lgqe_resolved_q[lgq] : + ({ex4_lgqe_set_all[lgq], lgqe_resolved[lgq]} == 2'b01) ? 1'b1 : + 1'b0; + + // LoadQ Entry is complete, Waiting to send Completion Report + assign lgqe_cpl_rpt_done[lgq] = lgqe_cpl_sent[lgq] | (lgqe_need_cpl_q[lgq] & lgq_rel5_odq_cpl[lgq]); + assign lgqe_need_cpl_rst[lgq] = lgqe_cpl_rpt_done[lgq] | lgqe_kill[lgq]; + // Need to delay the completion report to cover the window where i am trying to update an FPR register + // and the gather queue entry got flushed, need to gate the FPR update + assign lgqe_need_cpl_sel[lgq] = {lgqe_need_cpl_rst[lgq], lgq_rel2_send_cpl_ok[lgq]}; + + assign lgqe_need_cpl_d[lgq] = (lgqe_need_cpl_sel[lgq] == 2'b00) ? lgqe_need_cpl_q[lgq] : + (lgqe_need_cpl_sel[lgq] == 2'b01) ? 1'b1 : + 1'b0; + + // Dont really think we need to wait for the full reload to be done on the interface + // We were waiting for the case that the L2 is sending a reload with newer data and a + // back-invalidate is seen for the previous data at the same cycle that the reload is + // occuring, the L2 should never do this, we should always either see the back-invalidate first + // followed by the reload with newer data, or we should see a reload with older data and the back-invalidate + // at the same time. For the second case, we should be covered for the scenario that eventually we get an older + // loadmiss to the same line that would bring in newer data because the younger loadmiss is sitting in the order queue + // and would have been flushed due to the back-invalidate hitting against the order queue. The older instruction may not + // have been resolved yet, so the older instruction would not get flushed. + assign lgqe_send_cpl[lgq] = lgqe_need_cpl_q[lgq] & lgqe_resolved_q[lgq] & lgqe_valid_q[lgq]; + + // ECC Error was detected on the GPR update + assign lgqe_upd_gpr_ecc_sel[lgq] = {lgq_rel2_upd_gpr[lgq], lgqe_need_cpl_rst[lgq]}; + + assign lgqe_upd_gpr_ecc[lgq] = (lgqe_upd_gpr_ecc_sel[lgq] == 2'b10) ? (lgqe_upd_gpr_ecc_q[lgq] | l2_lsq_resp_ecc_err | l2_lsq_resp_ecc_err_ue) : + (lgqe_upd_gpr_ecc_sel[lgq] == 2'b00) ? lgqe_upd_gpr_ecc_q[lgq] : + 1'b0; + assign lgqe_upd_gpr_ecc_d[lgq] = lgqe_upd_gpr_ecc[lgq]; + + assign lgqe_upd_gpr_eccue[lgq] = (lgqe_upd_gpr_ecc_sel[lgq] == 2'b10) ? (lgqe_upd_gpr_eccue_q[lgq] | l2_lsq_resp_ecc_err_ue) : + (lgqe_upd_gpr_ecc_sel[lgq] == 2'b00) ? lgqe_upd_gpr_eccue_q[lgq] : + 1'b0; + assign lgqe_upd_gpr_eccue_d[lgq] = lgqe_upd_gpr_eccue[lgq]; + + end + end +endgenerate + +// determine when lmq entries do not have any more active gathers + +always @(*) begin: ldq_gath_done_P + reg [0:`LMQ_ENTRIES-1] active; + + //(* analysis_not_referenced="true" *) + + integer lgq; + active = {`LMQ_ENTRIES{1'b0}}; + for (lgq=0; lgq<`LGQ_ENTRIES; lgq=lgq+1) + active = (ldq_gath_Tag_1hot[lgq] & {`LGQ_ENTRIES{lgqe_valid_q[lgq]}}) | active; + ldqe_gather_done = (~active); +end + +assign lgq_rel1_gpr_val_d = |(lgq_rel0_upd_gpr_q & (~(ex5_lgqe_drop | lgqe_kill))); +assign lgq_rel1_upd_gpr_d = lgq_rel0_upd_gpr_q & (~(ex5_lgqe_drop | lgqe_kill)); +assign lgq_rel2_upd_gpr_d = lgq_rel1_upd_gpr_q & (~lgqe_kill); +assign lgq_rel3_upd_gpr_d = lgq_rel2_upd_gpr_q & (~lgqe_kill); +assign lgq_rel1_upd_gpr = lgq_rel1_upd_gpr_q & lgqe_valid_q & (~lgqe_kill); +assign lgq_rel2_upd_gpr = lgq_rel2_upd_gpr_q & lgqe_valid_q; + +// Need to Send Completion Report +assign lgq_rel2_send_cpl_ok = lgq_rel2_upd_gpr_q & lgqe_valid_q & (~lgqe_need_cpl_q); + +// LDQ has a Loadmiss Request to send +assign ldq_l2_req_need_send = |(ldqe_need_l2send); + +// Reload will try to update Cache contents +assign ldq_rel0_updating_cache = |(ldq_rel0_entrySent); +assign ldq_stq_rel1_blk_store_d = ldq_rel0_updating_cache | |(ldq_rel_l2_l1dumpBlk) | |(ldq_rel0_upd_gpr_q) | |(lgq_rel0_upd_gpr_q & (~ex5_lgqe_drop)); + +// Clear qHit indicator when reload is about to complete +assign ldq_rel2_qHit_clr = ldqe_rel2_l1upd_cmpl | ldq_rel2_ci_done | ldq_rel2_drel_done; +assign ldq_rel2_rv_clr_hold = |(ldq_rel2_qHit_clr & ldqe_qHit_held_q); +assign ldq_clrHold = ldq_rel2_rv_clr_hold | ldq_oth_qHit_clr_q; +assign ldq_clrHold_tid = ldq_hold_tid & {`THREADS{ldq_clrHold}}; + +// Load Queue Full +assign ex4_ldq_full = &(~ldqe_available); +assign ex5_ldq_full_d = ex4_ldq_full; +assign ex4_ldq_full_restart = ctl_lsq_ex4_ldreq_val & ex4_ldq_full & (~ex4_stg_flush); +assign ex5_ldq_full_restart_d = ex4_ldq_full_restart; + +// Load Queue Full SET_HOLD and CLR_HOLD logic to the reservation station +// Want to clear when the load queue isnt full +assign ldq_full_qHit_held_set = ex5_ldq_full_restart_q & (~(ctl_lsq_ex5_load_hit | stq_ldq_ex5_fwd_val)); +assign ldq_full_qHit_held_clr = ldq_full_qHit_held_q & (~ex4_ldq_full); +assign ldq_full_qHit_held_ctrl = {ldq_full_qHit_held_set, ldq_full_qHit_held_clr}; + +assign ldq_full_qHit_held_d = (ldq_full_qHit_held_ctrl == 2'b00) ? ldq_full_qHit_held_q : + (ldq_full_qHit_held_ctrl == 2'b10) ? 1'b1 : + 1'b0; + +// Load Queue Entry Reserved SET_HOLD and CLR_HOLD logic to the reservation station +// Want to clear when the load queue isnt full or there is one entry available +assign ldq_resv_qHit_held_set = ex5_resv_taken_restart_q & (~(ctl_lsq_ex5_load_hit | stq_ldq_ex5_fwd_val)); +assign ldq_resv_qHit_held_clr = ldq_resv_qHit_held_q & (~(ex4_one_machine_avail | ex4_ldq_full)); +assign ldq_resv_qHit_held_ctrl = {ldq_resv_qHit_held_set, ldq_resv_qHit_held_clr}; + +assign ldq_resv_qHit_held_d = (ldq_resv_qHit_held_ctrl == 2'b00) ? ldq_resv_qHit_held_q : + (ldq_resv_qHit_held_ctrl == 2'b10) ? 1'b1 : + 1'b0; + +// CLR_HOLD indicator for LDQ Full or LDQ Reserved +assign ldq_oth_qHit_clr_d = ldq_full_qHit_held_clr | ldq_resv_qHit_held_clr; + +// SET_HOLD due to LDQ Full or 1 Entry left and is reserved +assign ex5_ldq_full_set_hold = (ex5_ldq_full_restart_q | ex5_resv_taken_restart_q) & (~(ctl_lsq_ex5_load_hit | stq_ldq_ex5_fwd_val)); + +// Queue Hit Indicators +assign ex4_ldq_hit = |(ex4_entry_load_qHit); +assign ex5_ldq_hit_d = ex4_ldq_hit; + +// Load Gathered Indicators +assign ex4_ld_gath = |(ex4_entry_gath_ld); +assign ex5_ld_gath_d = ex4_ld_gath; + +// Set Hold on a LDQ restart +assign ex5_ldq_set_hold_d = |(ex4_load_qHit_upd); +assign ex5_setHold = ex5_ldq_set_hold_q | ex5_ldq_full_set_hold; + +// Set Thread Held Indicator +assign ldq_setHold_tid = ldq_hold_tid_q | {`THREADS{ex5_setHold}}; +generate begin : holdTid + genvar tid; + for (tid=0; tid<`THREADS; tid=tid+1) begin : holdTid + assign ldq_hold_tid[tid] = ctl_lsq_ex5_thrd_id[tid] ? ldq_setHold_tid[tid] : ldq_hold_tid_q[tid]; + end + end +endgenerate + +assign ldq_hold_tid_d = ldq_hold_tid & (~ldq_clrHold_tid); + +// EX5 Request needs to be dropped +assign ex5_drop_req_val = ctl_lsq_ex5_load_hit | // request was a load hit + ex5_reserved_taken_q | // queue entry is reserved for oldest load + ex5_ldq_hit_q | // request hit outstanding request + stq_ldq_ex5_fwd_val | // STQ Forwarded Load Data, dont need to send an L1 Miss request + stq_ldq_ex5_stq_restart | // STQ Restarted Load due to every other reason + stq_ldq_ex5_stq_restart_miss; // STQ Restarted Load due to loadmiss that didnt forward specifically + +assign ex5_drop_gath = ctl_lsq_ex5_load_hit | // request was a load hit + ex5_stg_flush | // request was CP_FLUSHed or will be + ex5_lgq_restart | // request was gathered in EX5 and reload to cTag the same cycle + stq_ldq_ex5_fwd_val | // STQ Forwarded Load Data, dont need to send an L1 Miss request + stq_ldq_ex5_stq_restart | // STQ Restarted Load due to every other reason + stq_ldq_ex5_stq_restart_miss; // STQ Restarted Load due to loadmiss that didnt forward specifically + + +// State Machines are idle +// Simulation uses this signal, dont delete +assign ldq_state_machines_idle = &(ldqe_available); + +// RESTART Request +// 1) Request to Cache line already in LoadMiss Queue +// 2) LoadMiss Queue is full and new loadmiss request +// 3) 1 LoadMiss StateMachine available and not the oldest load request and a loadmiss +assign ex5_ldq_restart_d = (ex4_ldq_full_restart | ex4_reserved_taken) & (~ex4_ld_gath); +assign ex5_lgq_restart = |(ex5_lgqe_restart); +assign ex5_ldq_restart = (ex5_ldq_hit_q & (~ex5_ld_gath_q)) | (ex5_odq_ldreq_val_q & ex5_ldq_restart_q & (~ctl_lsq_ex5_load_hit)) | ex5_lgq_restart; +assign ex6_ldq_full_d = (ex5_ldq_full_q | ex5_reserved_taken_q) & ~ex5_ld_gath_q; +assign ex6_ldq_hit_d = ex5_ldq_hit_q & ~ex5_ld_gath_q; +assign ex5_lgq_full_d = |(ex4_entry_gath_full); +assign ex6_lgq_full_d = ex5_lgq_full_q; +assign ex5_lgq_qwhit_d = |(ex4_entry_gath_qwhit); +assign ex6_lgq_qwhit_d = ex5_lgq_qwhit_q; +assign perf_ex6_ldq_full_restart = ex6_ldq_full_q; +assign perf_ex6_ldq_hit_restart = ex6_ldq_hit_q; +assign perf_ex6_lgq_full_restart = ex6_lgq_full_q; +assign perf_ex6_lgq_qwhit_restart = ex6_lgq_qwhit_q; + +// RESTART Due to LoadmissQ and StoreQ +assign ex5_restart_val = ex5_ldq_restart | stq_ldq_ex5_stq_restart | (stq_ldq_ex5_stq_restart_miss & (~ctl_lsq_ex5_load_hit)); +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Reload Rotator Select Control +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +// 1-Hot opsize +assign ldq_rel0_opsize_1hot = (ldq_rel0_opsize == 3'b110) ? 5'b10000 : // 16Bytes + (ldq_rel0_opsize == 3'b101) ? 5'b01000 : // 8Bytes + (ldq_rel0_opsize == 3'b100) ? 5'b00100 : // 4Bytes + (ldq_rel0_opsize == 3'b010) ? 5'b00010 : // 2Bytes + (ldq_rel0_opsize == 3'b001) ? 5'b00001 : // 1Bytes + 5'b00000; + +// Store/Reload Pipe Rotator Control Calculations +assign ldq_rel0_rot_size = ldq_rel0_p_addr[59:63] + ldq_rel0_opsize_1hot; +assign ldq_rel0_rot_max_size_le = rot_max_size | ldq_rel0_opsize_1hot; +assign ldq_rel0_rot_sel_le = ldq_rel0_rot_max_size_le - ldq_rel0_rot_size; + +// RELOAD PATH LITTLE ENDIAN ROTATOR SELECT CALCULATION +// rel_rot_size = rot_addr + op_size +// rel_rot_sel_le = (rot_max_size or le_op_size) - rel_rot_size +// rel_rot_sel = rel_rot_sel_le => le_mode = 1 +// = rel_rot_size => le_mode = 0 + +// Little Endian Support Reload Data Rotate Select +assign ldq_rel0_rot_sel = ldq_rel0_byte_swap ? ldq_rel0_rot_sel_le[1:4] : ldq_rel0_rot_size[1:4]; + +// Calculate Algebraic Mux control +assign ldq_rel1_algebraic_sel_d = ldq_rel0_rot_sel - ldq_rel0_opsize_1hot[1:4]; + +// Calculate Reload Rotator Mux control +assign lvl1_sel = ldq_rel0_byte_swap; +assign lvl2_sel = ldq_rel0_rot_sel[0:1]; +assign lvl3_sel = ldq_rel0_rot_sel[2:3]; + +assign rotate_sel1 = (lvl1_sel == 1'b0) ? 2'b10 : + 2'b01; + +assign rotate_sel2 = (lvl2_sel == 2'b00) ? 4'b1000 : + (lvl2_sel == 2'b01) ? 4'b0100 : + (lvl2_sel == 2'b10) ? 4'b0010 : + 4'b0001; + +assign rotate_sel3 = (lvl3_sel == 2'b00) ? 4'b1000 : + (lvl3_sel == 2'b01) ? 4'b0100 : + (lvl3_sel == 2'b10) ? 4'b0010 : + 4'b0001; + +assign ldq_rel1_rot_sel1_d = {rotate_sel1, rotate_sel1, rotate_sel1, rotate_sel1}; +assign ldq_rel1_rot_sel2_d = {rotate_sel2, rotate_sel2}; +assign ldq_rel1_rot_sel3_d = {rotate_sel3, rotate_sel3}; +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Reload Rotator Select Control +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +lq_ldq_rot rrotl( + + // ACT + .ldq_rel1_stg_act(ldq_rel1_val_q), + + // Reload Rotator Control + .ldq_rel1_rot_sel1(ldq_rel1_rot_sel1_q), + .ldq_rel1_rot_sel2(ldq_rel1_rot_sel2_q), + .ldq_rel1_rot_sel3(ldq_rel1_rot_sel3_q), + .ldq_rel1_data(ldq_rel1_data), + + // Reload Data Fixup Control + .ldq_rel1_opsize(ldq_rel1_opsize_q), + .ldq_rel1_byte_swap(ldq_rel1_byte_swap_q), + .ldq_rel1_algebraic(ldq_rel1_algEn_q), + .ldq_rel1_algebraic_sel(ldq_rel1_algebraic_sel_q), + .ldq_rel1_gpr_val(ldq_rel1_gpr_val), + .ldq_rel1_dvc1_en(ldq_rel1_dvcEn_q[0]), + .ldq_rel1_dvc2_en(ldq_rel1_dvcEn_q[1]), + .ldq_rel2_thrd_id(ldq_rel2_tid_q), + + // Data Value Compare Registers + .ctl_lsq_spr_dvc1_dbg(ctl_lsq_spr_dvc1_dbg), + .ctl_lsq_spr_dvc2_dbg(ctl_lsq_spr_dvc2_dbg), + .ctl_lsq_spr_dbcr2_dvc1be(ctl_lsq_spr_dbcr2_dvc1be), + .ctl_lsq_spr_dbcr2_dvc1m(ctl_lsq_spr_dbcr2_dvc1m), + .ctl_lsq_spr_dbcr2_dvc2be(ctl_lsq_spr_dbcr2_dvc2be), + .ctl_lsq_spr_dbcr2_dvc2m(ctl_lsq_spr_dbcr2_dvc2m), + + // Reload Rotator Output + .ldq_rel2_rot_data(ldq_rel2_rot_data), + .ldq_rel2_dvc(ldq_rel2_dvc), + + // Pervasive + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .sg_0(sg_0), + .func_sl_thold_0_b(func_sl_thold_0_b), + .func_sl_force(func_sl_force), + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .scan_in(siv[rrot_scan_offset]), + .scan_out(sov[rrot_scan_offset]) +); + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// LOADMISS REQUEST ARBITRATION +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Doing a FIFO scheme +// Request at the bottom will be sent out first +// New Requests should always behind the last valid request + +// New request going to FIFO +assign ex5_upd_fifo_val = (ex5_ldreq_val | ex5_pfetch_val) & ~ex5_drop_req_val & (~arb_ldq_ldq_unit_sel | fifo_ldq_req_val_q[0]); + +// FIFO ACT +// Want to turn on ACT for the following reasons +// 1) request needs to be sent, will cause a compression +// 2) need to compress in the middle +// 3) new loadmiss might be updating fifo +assign fifo_ldq_act = fifo_ldq_req_val_q[0] | |(fifo_ldq_req_empty_entry) | ex5_ldreq_val_q | ex5_pfetch_val_q; + +// FIFO needs compression for 2 reasons +// 1) Bottom of FIFO request was sent +// 2) Entry in between Bottom and Top of FIFO was zapped +assign fifo_ldq_req_compr_val = fifo_ldq_req_sent | |(fifo_ldq_req_empty_entry); + +// FIFO Entry WRT Pointer Logic +assign fifo_ldq_req_wrt_ptr = fifo_ldq_req_compr_val ? ({fifo_ldq_req_nxt_ptr_q[1:`LMQ_ENTRIES], 1'b0}) : fifo_ldq_req_nxt_ptr_q; + +// FIFO Entry WRT Pointer Logic +assign fifo_ldq_wrt_ptr_cntrl = {fifo_ldq_req_compr_val, ex5_upd_fifo_val}; +assign fifo_ldq_req_nxt_ptr = (fifo_ldq_wrt_ptr_cntrl == 2'b10) ? ({fifo_ldq_req_nxt_ptr_q[1:`LMQ_ENTRIES], 1'b0}) : + (fifo_ldq_wrt_ptr_cntrl == 2'b01) ? ({1'b0, fifo_ldq_req_nxt_ptr_q[0:`LMQ_ENTRIES - 1]}) : + fifo_ldq_req_nxt_ptr_q; + +// FIFO Reset when write pointer is not at entry 0 and fifo empty +assign fifo_ldq_reset_ptr = (~fifo_ldq_req_wrt_ptr[0]) & (~(|fifo_ldq_req_val)) & (~ex5_upd_fifo_val); +assign fifo_ldq_req_nxt_ptr_d[0] = fifo_ldq_reset_ptr ? 1'b1 : fifo_ldq_req_nxt_ptr[0]; +assign fifo_ldq_req_nxt_ptr_d[1:`LMQ_ENTRIES] = fifo_ldq_reset_ptr ? {`LMQ_ENTRIES{1'b0}} : fifo_ldq_req_nxt_ptr[1:`LMQ_ENTRIES]; + +// FIFO Entry Sent +assign fifo_ldq_req_sent = fifo_ldq_req_val_q[0] & arb_ldq_ldq_unit_sel; +assign fifo_ldq_req0_mkill = |(fifo_ldq_req_tid_q[0] & iu_lq_cp_flush_q); +assign fifo_ldq_req0_avail = (fifo_ldq_req_val_q[0] & ~fifo_ldq_req0_mkill) & ~fifo_ldq_req_pfetch_q[0]; + +// FIFO Control +generate begin : fifoCtrl + genvar fifo; + for (fifo=0; fifo<`LMQ_ENTRIES; fifo=fifo+1) begin : fifoCtrl + // Fifo Entry Was Zapped + assign fifo_ldq_req_val[fifo] = fifo_ldq_req_val_q[fifo] & |(fifo_ldq_req_q[fifo] & (~ldqe_mkill)); + + // Fifo Entry Prefetch is allowed to be sent status from ODQ + assign fifo_ldq_req_pfetch_match[fifo] = |(fifo_ldq_req_q[fifo] & ex7_ldqe_pfetch_val_q); + assign fifo_ldq_req_pfetch_send[fifo] = fifo_ldq_req_pfetch_match[fifo] & ~odq_ldq_ex7_pfetch_blk; + assign fifo_ldq_req_pfetch[fifo] = (fifo_ldq_req_pfetch_q[fifo] & ~fifo_ldq_req_pfetch_send[fifo]) | (fifo_ldq_req_pfetch_q[fifo] & ~fifo_ldq_req_pfetch_match[fifo]); + + // Figure out if entry behind me is valid and i am not valid, need to push my entry and all entries after mine + if (fifo < `LMQ_ENTRIES - 1) begin : emptyFifo + assign fifo_ldq_req_empty_entry[fifo] = (~fifo_ldq_req_val_q[fifo]) & fifo_ldq_req_val_q[fifo + 1]; + end + if (fifo == `LMQ_ENTRIES - 1) begin : lastFifo + assign fifo_ldq_req_empty_entry[fifo] = 1'b0; + end + + assign fifo_ldq_req_upd[fifo] = fifo_ldq_req_wrt_ptr[fifo] & ex5_upd_fifo_val; + assign fifo_ldq_req_push[fifo] = |(fifo_ldq_req_empty_entry[0:fifo]) | fifo_ldq_req_sent; + assign fifo_ldq_req_cntrl[fifo] = {fifo_ldq_req_upd[fifo], fifo_ldq_req_push[fifo]}; + end + end +endgenerate + +// Last entry of FIFO +assign fifo_ldq_req_tid_d[`LMQ_ENTRIES-1] = ~fifo_ldq_req_cntrl[`LMQ_ENTRIES-1][0] ? fifo_ldq_req_tid_q[`LMQ_ENTRIES-1] : ctl_lsq_ex5_thrd_id; +assign fifo_ldq_req_d[`LMQ_ENTRIES-1] = ~fifo_ldq_req_cntrl[`LMQ_ENTRIES-1][0] ? fifo_ldq_req_q[`LMQ_ENTRIES-1] : ex5_ldqe_set_all_q; +assign fifo_ldq_req_pfetch_d[`LMQ_ENTRIES-1] = (fifo_ldq_req_cntrl[`LMQ_ENTRIES-1] == 2'b00) ? fifo_ldq_req_pfetch[`LMQ_ENTRIES-1] : + (fifo_ldq_req_cntrl[`LMQ_ENTRIES-1] == 2'b01) ? 1'b0 : + ex5_pfetch_val_q; +assign fifo_ldq_req_val_d[`LMQ_ENTRIES-1] = (fifo_ldq_req_cntrl[`LMQ_ENTRIES-1] == 2'b00) ? fifo_ldq_req_val[`LMQ_ENTRIES-1] : + (fifo_ldq_req_cntrl[`LMQ_ENTRIES-1] == 2'b01) ? 1'b0 : + 1'b1; + +// Rest of the entries of FIFO +generate begin : ldqFifo + genvar fifo; + for (fifo=0; fifo<=`LMQ_ENTRIES-2; fifo=fifo+1) begin : ldqFifo + assign fifo_ldq_req_tid_d[fifo] = (fifo_ldq_req_cntrl[fifo] == 2'b00) ? fifo_ldq_req_tid_q[fifo] : + (fifo_ldq_req_cntrl[fifo] == 2'b01) ? fifo_ldq_req_tid_q[fifo+1] : + ctl_lsq_ex5_thrd_id; + + assign fifo_ldq_req_d[fifo] = (fifo_ldq_req_cntrl[fifo] == 2'b00) ? fifo_ldq_req_q[fifo] : + (fifo_ldq_req_cntrl[fifo] == 2'b01) ? fifo_ldq_req_q[fifo+1] : + ex5_ldqe_set_all_q; + + assign fifo_ldq_req_pfetch_d[fifo] = (fifo_ldq_req_cntrl[fifo] == 2'b00) ? fifo_ldq_req_pfetch[fifo] : + (fifo_ldq_req_cntrl[fifo] == 2'b01) ? fifo_ldq_req_pfetch[fifo+1] : + ex5_pfetch_val_q; + + assign fifo_ldq_req_val_d[fifo] = (fifo_ldq_req_cntrl[fifo] == 2'b00) ? fifo_ldq_req_val[fifo] : + (fifo_ldq_req_cntrl[fifo] == 2'b01) ? fifo_ldq_req_val[fifo+1] : + 1'b1; + end + end +endgenerate + +// Muxing Load Request to send to the L2 +always @(*) begin: ldqMux + reg [0:3] usrDef; + reg [0:4] wimge; + reg [64-`REAL_IFAR_WIDTH:63] pAddr; + reg [0:5] tType; + reg [0:2] opsize; + reg [0:`THREADS-1] tid; + + //(* analysis_not_referenced="true" *) + + integer ldq; + usrDef = {4{1'b0}}; + wimge = {5{1'b0}}; + pAddr = {`REAL_IFAR_WIDTH{1'b0}}; + tType = {6{1'b0}}; + opsize = {3{1'b0}}; + tid = {`THREADS{1'b0}}; + for (ldq=0; ldq<`LMQ_ENTRIES; ldq=ldq+1) begin + usrDef = (ldqe_usr_def_q[ldq] & { 4{fifo_ldq_req_q[0][ldq]}}) | usrDef; + wimge = (ldqe_wimge_q[ldq] & { 5{fifo_ldq_req_q[0][ldq]}}) | wimge; + pAddr = (ldqe_p_addr_q[ldq] & {`REAL_IFAR_WIDTH{fifo_ldq_req_q[0][ldq]}}) | pAddr; + tType = (ldqe_ttype_q[ldq] & { 6{fifo_ldq_req_q[0][ldq]}}) | tType; + opsize = (ldqe_op_size_q[ldq] & { 3{fifo_ldq_req_q[0][ldq]}}) | opsize; + tid = (ldqe_thrd_id_q[ldq] & { `THREADS{fifo_ldq_req_q[0][ldq]}}) | tid; + end + ldq_mux_usr_def = usrDef; + ldq_mux_wimge = wimge; + ldq_mux_p_addr = pAddr; + ldq_mux_ttype = tType; + ldq_mux_opsize = opsize; + ldq_mux_tid = tid; +end + +// Generate Encode Thread ID +always @(*) begin: tidMulti + reg [0:1] ex5Tid; + reg [0:1] ldqTid; + + //(* analysis_not_referenced="true" *) + + integer tid; + ex5Tid = {2{1'b0}}; + ldqTid = {2{1'b0}}; + for (tid=1; tid<`THREADS; tid=tid+1) begin + ex5Tid = (tid[1:0] & {2{ctl_lsq_ex5_thrd_id[tid]}}) | ex5Tid; + ldqTid = (tid[1:0] & {2{ ldq_mux_tid[tid]}}) | ldqTid; + end + ex5_tid_enc = ex5Tid; + ldq_mux_tid_enc = ldqTid; +end + +// Generate Core Tag +always @(*) begin: ldqcTag + reg [0:3] entryF; + reg [0:3] entryP; + + //(* analysis_not_referenced="true" *) + + integer ldq; + entryF = 4'b0000; + entryP = 4'b0000; + for (ldq=0; ldq<`LMQ_ENTRIES; ldq=ldq+1) begin + entryF = (ldq[3:0] & {4{ fifo_ldq_req_q[0][ldq]}}) | entryF; + entryP = (ldq[3:0] & {4{ex5_ldqe_set_all_q[ldq]}}) | entryP; + end + ldq_mux_cTag = entryF; + ex5_cTag = entryP; +end + +// Select between entry already in LOADMISSQ and +// entry going into LOADMISSQ +assign ldq_arb_usr_def = fifo_ldq_req_val_q[0] ? ldq_mux_usr_def : ctl_lsq_ex5_usr_def; +assign ldq_arb_tid = fifo_ldq_req_val_q[0] ? ldq_mux_tid_enc : ex5_tid_enc; +assign ldq_arb_wimge = fifo_ldq_req_val_q[0] ? ldq_mux_wimge : ex5_wimge_q; +assign ldq_arb_p_addr = fifo_ldq_req_val_q[0] ? ldq_mux_p_addr : ex5_p_addr_q; +assign ldq_arb_ttype = fifo_ldq_req_val_q[0] ? ldq_mux_ttype : ctl_lsq_ex5_ttype; +assign ldq_arb_opsize = fifo_ldq_req_val_q[0] ? ldq_mux_opsize : ctl_lsq_ex5_opsize; +assign ldq_arb_cTag = fifo_ldq_req_val_q[0] ? {ldq_mux_cTag[0], 1'b0, ldq_mux_cTag[1:3]} : {ex5_cTag[0], 1'b0, ex5_cTag[1:3]}; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// RELOAD DATA BEATS ARBITER +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Select Between L2 Reload and Reload Queue +assign ldq_resp_cTag = l2_rel0_resp_ldq_val_q ? l2_rel0_resp_cTag_q : ldq_rel0_arb_cTag; +assign ldq_resp_qw = l2_rel0_resp_ldq_val_q ? l2_rel0_resp_qw_q : ldq_rel0_arb_qw; + +// Reload Valid +assign ldq_reload_qw = ldq_resp_qw[57:59]; +assign ldq_reload_val = l2_rel0_resp_ldq_val_q | ldq_rel0_arb_val; +assign ldq_rel1_arb_val_d = ldq_rel0_arb_val & ~l2_rel0_resp_ldq_val_q; +assign ldq_rel1_val_d = ldq_reload_val; +assign ldq_rel0_rdat_sel = ldq_rel0_arb_val & (~l2_rel0_resp_ldq_val_q); +assign ldq_rel0_rdat_qw = ldq_reload_qw[57:59]; +assign ldq_rel0_arr_wren = |(ldq_rel0_l2_val_q); +assign ldq_rel1_l1_dump_d = l2_rel0_resp_ldq_val_q & l2_rel0_resp_l1_dump_q; +assign ldq_rel2_l1_dump_d = ldq_rel1_l1_dump_q; +assign ldq_rel3_l1_dump_d = ldq_rel2_l1_dump_q & |(ldq_rel2_l2_val_q & ldq_rel2_beats_home_q & (~(ldqe_wimge_i | ldqe_rel_eccdet))); +assign ldq_rel3_l1_dump_val = ldq_rel3_l1_dump_q; +assign ldq_rel3_clr_relq_d = |(ldq_rel2_beats_home_q & ldq_rel2_l2_val_q & ldqe_rel_eccdet); +assign ldq_rel1_resp_qw_d = spr_xucr0_cls_q ? ldq_reload_qw[57:59] : {ldq_rel_mux_p_addr[57], ldq_reload_qw[58:59]}; +assign ldq_rel1_cTag_d = ldq_resp_cTag; +assign l2_rel1_resp_val_d = l2_rel0_resp_val_q; +assign l2_rel2_resp_val_d = l2_rel1_resp_val_q; +assign ldq_err_inval_rel_d = |(ldq_relmin1_l2_inval); +assign ldq_err_ecc_det_d = l2_rel2_resp_val_q & l2_lsq_resp_ecc_err; +assign ldq_err_ue_det_d = l2_rel2_resp_val_q & l2_lsq_resp_ecc_err_ue; + +// 1-hot of quadword updated +generate begin : relDat + genvar beat; + for (beat=0; beat<8; beat=beat+1) begin : relDat + wire [0:2] beatDummy; + assign beatDummy = beat[2:0]; + assign ldq_rel0_beat_upd[beat] = (beatDummy == ldq_reload_qw); + end + end +endgenerate + +lq_ldq_relq relq( + // ACT's + .ldq_rel0_stg_act(rel0_stg_act), + .ldq_rel1_stg_act(ldq_rel1_val_q), + .ldqe_ctrl_act(ldqe_ctrl_act), + + // Reload Data Beats Control + .ldq_rel0_arb_sent(ldq_rel0_arb_sent), + .ldq_rel0_beat_upd(ldq_rel0_beat_upd), + .ldq_rel0_arr_wren(ldq_rel0_arr_wren), + .ldq_rel0_rdat_qw(ldq_rel0_rdat_qw), + .ldq_rel1_cTag(ldq_rel1_cTag_q), + .ldq_rel1_dbeat_val(ldq_rel1_dbeat_val), + .ldq_rel1_beats_home(ldq_rel1_beats_home), + .ldq_rel2_entrySent(ldq_rel2_entrySent_q), + .ldq_rel2_blk_req(rel2_blk_req_q), + .ldq_rel2_sentL1(ldq_rel2_sentL1), + .ldq_rel2_sentL1_blk(ldq_rel2_sentL1_blk), + .ldqe_rel_eccdet(ldqe_rel_eccdet), + .ldqe_rst_eccdet(ldqe_rst_eccdet_q), + + // Reload Data Select Valid + .ldq_rel0_rdat_sel(ldq_rel0_rdat_sel), + .arb_ldq_rel2_wrt_data(arb_ldq_rel2_wrt_data), + + // Reload Arbiter Control Outputs + .ldq_rel0_arb_val(ldq_rel0_arb_val), + .ldq_rel0_arb_qw(ldq_rel0_arb_qw), + .ldq_rel0_arb_cTag(ldq_rel0_arb_cTag), + .ldq_rel0_arb_thresh(ldq_rel0_arb_thresh), + .ldq_rel2_rdat_perr(ldq_rel2_rdat_perr), + .ldq_rel3_rdat_par_err(ldq_rel3_rdat_par_err), + .ldqe_rel_rdat_perr(ldqe_rel_rdat_perr), + + // Reload Data Arbiter Data + .ldq_arb_rel2_rdat_sel(ldq_arb_rel2_rdat_sel), + .ldq_arb_rel2_rd_data(ldq_arb_rel2_rd_data), + + // SPR's + .pc_lq_inj_relq_parity(pc_lq_inj_relq_parity), + .spr_lsucr0_lca_ovrd(spr_lsucr0_lca_ovrd), + + // Array Pervasive Controls + .bo_enable_2(bo_enable_2), + .clkoff_dc_b(clkoff_dc_b), + .g8t_clkoff_dc_b(g8t_clkoff_dc_b), + .g8t_d_mode_dc(g8t_d_mode_dc), + .g8t_delay_lclkr_dc(g8t_delay_lclkr_dc), + .g8t_mpw1_dc_b(g8t_mpw1_dc_b), + .g8t_mpw2_dc_b(g8t_mpw2_dc_b), + .pc_lq_ccflush_dc(pc_lq_ccflush_dc), + .an_ac_scan_dis_dc_b(an_ac_scan_dis_dc_b), + .an_ac_scan_diag_dc(an_ac_scan_diag_dc), + .an_ac_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc), + .pc_lq_abist_ena_dc(pc_lq_abist_ena_dc), + .pc_lq_abist_raw_dc_b(pc_lq_abist_raw_dc_b), + .pc_lq_abist_wl64_comp_ena(pc_lq_abist_wl64_comp_ena), + .pc_lq_abist_raddr_0(pc_lq_abist_raddr_0), + .pc_lq_abist_g8t_wenb(pc_lq_abist_g8t_wenb), + .pc_lq_abist_g8t1p_renb_0(pc_lq_abist_g8t1p_renb_0), + .pc_lq_abist_g8t_dcomp(pc_lq_abist_g8t_dcomp), + .pc_lq_abist_g8t_bw_1(pc_lq_abist_g8t_bw_1), + .pc_lq_abist_g8t_bw_0(pc_lq_abist_g8t_bw_0), + .pc_lq_abist_di_0(pc_lq_abist_di_0), + .pc_lq_abist_waddr_0(pc_lq_abist_waddr_0), + .pc_lq_bo_unload(pc_lq_bo_unload), + .pc_lq_bo_repair(pc_lq_bo_repair), + .pc_lq_bo_reset(pc_lq_bo_reset), + .pc_lq_bo_shdata(pc_lq_bo_shdata), + .pc_lq_bo_select(pc_lq_bo_select), + .lq_pc_bo_fail(lq_pc_bo_fail), + .lq_pc_bo_diagout(lq_pc_bo_diagout), + + //Pervasive + .vcs(vcs), + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .sg_0(sg_0), + .func_sl_thold_0_b(func_sl_thold_0_b), + .func_sl_force(func_sl_force), + .abst_sl_thold_0(abst_sl_thold_0), + .ary_nsl_thold_0(ary_nsl_thold_0), + .time_sl_thold_0(time_sl_thold_0), + .repr_sl_thold_0(repr_sl_thold_0), + .bolt_sl_thold_0(bolt_sl_thold_0), + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .scan_in(rdat_scan_in), + .abst_scan_in(abst_scan_in), + .time_scan_in(time_scan_in), + .repr_scan_in(repr_scan_in), + .scan_out(rdat_scan_out), + .abst_scan_out(abst_scan_out), + .time_scan_out(time_scan_out), + .repr_scan_out(repr_scan_out) +); + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// RELOAD QUEUE ENTRY SELECT +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Muxing Reload Request to send to the L1 +always @(*) begin: relMux + reg [0:2] opsize; + reg wimge_i; + reg byte_swap; + reg [64-`REAL_IFAR_WIDTH:63] pAddr; + reg [0:1] dvcEn; + reg lockSet; + reg watchSet; + reg [0:AXU_TARGET_ENC-1] tGpr; + reg axu; + reg algEn; + reg [0:1] classID; + reg binv; + reg [0:`THREADS-1] tid; + reg [0:`ITAG_SIZE_ENC-1] iTagM1; + reg [0:`THREADS-1] tidM1; + + //(* analysis_not_referenced="true" *) + + integer ldq; + opsize = {3{1'b0}}; + wimge_i = 1'b0; + byte_swap = 1'b0; + pAddr = {`REAL_IFAR_WIDTH{1'b0}}; + dvcEn = {2{1'b0}}; + lockSet = 1'b0; + watchSet = 1'b0; + tGpr = {AXU_TARGET_ENC{1'b0}}; + axu = 1'b0; + algEn = 1'b0; + classID = {2{1'b0}}; + binv = 1'b0; + tid = {`THREADS{1'b0}}; + iTagM1 = {`ITAG_SIZE_ENC{1'b0}}; + tidM1 = {`THREADS{1'b0}}; + for (ldq=0; ldq<`LMQ_ENTRIES; ldq=ldq+1) begin + opsize = (ldqe_op_size_q[ldq] & { 3{ldqe_rel0_cTag[ldq]}}) | opsize; + wimge_i = (ldqe_wimge_i[ldq] & ldqe_rel0_cTag[ldq]) | wimge_i; + byte_swap = (ldqe_byte_swap_q[ldq] & ldqe_rel0_cTag[ldq]) | byte_swap; + pAddr = (ldqe_p_addr_q[ldq] & {`REAL_IFAR_WIDTH{ldqe_rel0_cTag[ldq]}}) | pAddr; + dvcEn = (ldqe_dvc_q[ldq] & { 2{ldqe_rel0_cTag[ldq]}}) | dvcEn; + lockSet = (ldqe_lock_set_q[ldq] & (~ldqe_resent_ecc_err_q[ldq]) & ldqe_rel0_cTag[ldq]) | lockSet; + watchSet = (ldqe_watch_set_q[ldq] & (~ldqe_resent_ecc_err_q[ldq]) & ldqe_rel0_cTag[ldq]) | watchSet; + tGpr = (ldqe_tgpr_q[ldq] & { AXU_TARGET_ENC{ldqe_rel0_cTag[ldq]}}) | tGpr; + axu = (ldqe_axu_q[ldq] & ldqe_rel0_cTag[ldq]) | axu; + algEn = (ldqe_algebraic_q[ldq] & ldqe_rel0_cTag[ldq]) | algEn; + classID = (ldqe_class_id_q[ldq] & { 2{ldqe_rel0_cTag[ldq]}}) | classID; + tid = (ldqe_thrd_id_q[ldq] & { `THREADS{ldqe_rel0_cTag[ldq]}}) | tid; + binv = (ldqe_back_inv_q[ldq] & ldqe_rel1_cTag[ldq]) | binv; + iTagM1 = (ldqe_itag_q[ldq] & {`ITAG_SIZE_ENC{ldqe_relmin1_cTag[ldq]}}) | iTagM1; + tidM1 = (ldqe_thrd_id_q[ldq] & { `THREADS{ldqe_relmin1_cTag[ldq]}}) | tidM1; + end + ldq_rel_mux_opsize = opsize; + ldq_rel_mux_wimge_i = wimge_i; + ldq_rel_mux_byte_swap = byte_swap; + ldq_rel_mux_p_addr = pAddr; + ldq_rel_mux_dvcEn = dvcEn; + ldq_rel_mux_lockSet = lockSet; + ldq_rel_mux_watchSet = watchSet; + ldq_rel_mux_tGpr = tGpr; + ldq_rel_mux_axu = axu; + ldq_rel_mux_algEn = algEn; + ldq_rel_mux_classID = classID; + ldq_rel_mux_tid = tid; + ldq_rel1_mux_back_inv = binv; + ldqe_relmin1_iTag = iTagM1; + ldqe_relmin1_tid = tidM1; +end + +// Muxing Reload Request from Gather Queue to send to the L1 +always @(*) begin: gath_relMux + reg [0:2] opsize; + reg byte_swap; + reg [0:1] dvcEn; + reg [0:AXU_TARGET_ENC-1] tGpr; + reg axu; + reg algEn; + reg [0:`THREADS-1] tid; + reg [59:63] addr; + reg [0:`ITAG_SIZE_ENC-1] iTagM1; + reg [0:`THREADS-1] tidM1; + + //(* analysis_not_referenced="true" *) + + integer lgq; + opsize = {3{1'b0}}; + byte_swap = 1'b0; + dvcEn = {2{1'b0}}; + tGpr = {AXU_TARGET_ENC{1'b0}}; + axu = 1'b0; + algEn = 1'b0; + tid = {`THREADS{1'b0}}; + addr = {5{1'b0}}; + iTagM1 = {`ITAG_SIZE_ENC{1'b0}}; + tidM1 = {`THREADS{1'b0}}; + for (lgq=0; lgq<`LGQ_ENTRIES; lgq=lgq+1) begin + opsize = (lgqe_op_size_q[lgq] & { 3{lgq_rel0_upd_gpr_q[lgq]}}) | opsize; + byte_swap = (lgqe_byte_swap_q[lgq] & lgq_rel0_upd_gpr_q[lgq]) | byte_swap; + dvcEn = (lgqe_dvc_q[lgq] & { 2{lgq_rel0_upd_gpr_q[lgq]}}) | dvcEn; + tGpr = (lgqe_tgpr_q[lgq] & {AXU_TARGET_ENC{lgq_rel0_upd_gpr_q[lgq]}}) | tGpr; + axu = (lgqe_axu_q[lgq] & lgq_rel0_upd_gpr_q[lgq]) | axu; + algEn = (lgqe_algebraic_q[lgq] & lgq_rel0_upd_gpr_q[lgq]) | algEn; + tid = (lgqe_thrd_id_q[lgq] & { `THREADS{lgq_rel0_upd_gpr_q[lgq]}}) | tid; + addr = (lgqe_p_addr_q[lgq][59:63] & { 5{lgq_rel0_upd_gpr_q[lgq]}}) | addr; + iTagM1 = (lgqe_itag_q[lgq] & {`ITAG_SIZE_ENC{lgqe_relmin1_match[lgq]}}) | iTagM1; + tidM1 = (lgqe_thrd_id_q[lgq] & { `THREADS{lgqe_relmin1_match[lgq]}}) | tidM1; + end + lgq_rel_mux_opsize = opsize; + lgq_rel_mux_byte_swap = byte_swap; + lgq_rel_mux_dvcEn = dvcEn; + lgq_rel_mux_tGpr = tGpr; + lgq_rel_mux_axu = axu; + lgq_rel_mux_algEn = algEn; + lgq_rel_mux_tid = tid; + lgq_rel_mux_p_addr = addr; + lgqe_relmin1_iTag = iTagM1; + lgqe_relmin1_tid = tidM1; +end + +// Latch up Reload Interface to other units +assign ldq_rel0_opsize = l2_rel0_resp_crit_qw_q ? ldq_rel_mux_opsize : lgq_rel_mux_opsize; +assign ldq_rel1_opsize_d = ldq_rel0_opsize; +assign ldq_rel1_wimge_i_d = ldq_rel_mux_wimge_i; +assign ldq_rel0_byte_swap = l2_rel0_resp_crit_qw_q ? ldq_rel_mux_byte_swap : lgq_rel_mux_byte_swap; +assign ldq_rel1_byte_swap_d = ldq_rel0_byte_swap; +assign ldq_rel2_byte_swap_d = ldq_rel1_byte_swap_q; +assign ldq_rel1_p_addr_d[64 - `REAL_IFAR_WIDTH:58] = ldq_rel_mux_p_addr[64 - `REAL_IFAR_WIDTH:58]; +assign ldq_rel0_p_addr[59:63] = l2_rel0_resp_crit_qw_q ? ldq_rel_mux_p_addr[59:63] : lgq_rel_mux_p_addr; +assign ldq_rel1_p_addr_d[59:63] = ldq_rel0_p_addr[59:63]; +assign ldq_rel1_dvcEn_d = l2_rel0_resp_crit_qw_q ? ldq_rel_mux_dvcEn : lgq_rel_mux_dvcEn; +assign ldq_rel1_lockSet_d = ldq_rel_mux_lockSet; +assign ldq_rel1_watchSet_d = ldq_rel_mux_watchSet; +assign ldq_rel1_tGpr_d = l2_rel0_resp_crit_qw_q ? ldq_rel_mux_tGpr : lgq_rel_mux_tGpr; +assign ldq_rel1_axu_d = l2_rel0_resp_crit_qw_q ? ldq_rel_mux_axu : lgq_rel_mux_axu; +assign ldq_rel1_algEn_d = l2_rel0_resp_crit_qw_q ? ldq_rel_mux_algEn : lgq_rel_mux_algEn; +assign ldq_rel1_classID_d = ldq_rel_mux_classID; +assign ldq_rel1_tid_d = l2_rel0_resp_crit_qw_q ? ldq_rel_mux_tid : lgq_rel_mux_tid; +assign ldq_rel1_dir_tid_d = ldq_rel_mux_tid; +assign ldq_rel2_tid_d = ldq_rel1_tid_q; +assign ldq_relmin1_iTag = l2_lsq_resp_crit_qw ? ldqe_relmin1_iTag : lgqe_relmin1_iTag; +assign ldq_relmin1_tid = l2_lsq_resp_crit_qw ? ldqe_relmin1_tid : lgqe_relmin1_tid; + +// Need to Mask off bit 57 of Reload Address depending on the Cacheline Size we are running with +assign ldq_rel_mux_p_addr_msk = {ldq_rel_mux_p_addr[64 - (`DC_SIZE - 3):56], (ldq_rel_mux_p_addr[57] | spr_xucr0_cls_q)}; + +// Back-Invalidate Congruence Class collided with Reload Congruence Class +assign ldq_rel1_collide_binv_d = l2_back_inv_val & ldq_rel0_updating_cache & (l2_back_inv_addr_msk[64-(`DC_SIZE-3):63-`CL_SIZE] == ldq_rel_mux_p_addr_msk); + +// Check to see if any of the data beats got any ECC type errors on the reload +assign rel2_eccdet = |(ldqe_rel_eccdet & ldq_rel2_entrySent_q); +assign rel2_eccdet_ue = |(ldqe_rel_eccdet_ue & ldq_rel2_entrySent_q); +assign rel2_eccdet_err = rel2_eccdet | rel2_eccdet_ue; + +// Need to lookup in the directory to determine which way to update +// Added ldqe_rst_eccdet_q to cover the case where the last beat on the reload interface +// is in rel3 and it got an ECC error on that beat and the reload_dataq is sending a request +// that is currently in the rel1 stage +assign ldq_rel1_clr_val = |(ldq_rel1_entrySent_q & ~(ldqe_relDir_start | ldqe_rst_eccdet_q)); +assign ldq_rel2_cclass_d = {ldq_rel1_p_addr_q[64-(`DC_SIZE-3):56], (ldq_rel1_p_addr_q[57] | spr_xucr0_cls_q)}; +assign ldq_rel3_cclass_d = ldq_rel2_cclass_q; +assign ldq_rel4_cclass_d = ldq_rel3_cclass_q; + +assign ldq_rel1_set_val = |(ldq_rel1_entrySent_q & ldqe_last_beat & ~ldqe_rst_eccdet_q); +assign ldq_rel2_set_val_d = ldq_rel1_set_val; +assign ldq_rel3_set_val_d = ldq_rel2_set_val_q & (~rel2_blk_req_q); +assign ldq_rel4_set_val_d = ldq_rel3_set_val_q; +// reloadQueue included, dont want to block if the arb is sending request since +// it would be the reload queue sending +// if reloadQueue is not included, want to block data_val since arb is only trying to +// update the directory state, the data cache should have already been updated +assign ldq_rel1_data_val = (|(ldq_rel1_entrySent_q & ~ldqe_rst_eccdet_q)) & ~ldq_rel1_arb_val_q; +assign ldq_rel1_data_sel_d = ldq_rel0_updating_cache; +assign ldq_rel1_gpr_val_d = |(ldq_rel0_upd_gpr_q); + +// loadmiss statemachine set itagHold, want to force reload through +// instead of using reload arbitration +assign ldq_l2_rel0_qHitBlk_d = |(ldq_relmin1_l2_qHitBlk); + +// Update GPR detection +assign ldq_rel1_upd_gpr_d = ldq_rel0_crit_qw; +assign ldq_rel2_upd_gpr_d = ldq_rel1_upd_gpr_q; +assign ldq_rel3_upd_gpr_d = ldq_rel2_upd_gpr_q; +assign ldq_rel2_gpr_ecc_err = (ldq_rel2_upd_gpr_q & ~ldqe_dGpr_q) & {`LMQ_ENTRIES{l2_lsq_resp_ecc_err | l2_lsq_resp_ecc_err_ue}}; +assign ldq_rel2_gpr_eccue_err = (ldq_rel2_upd_gpr_q & ~ldqe_dGpr_q) & {`LMQ_ENTRIES{l2_lsq_resp_ecc_err_ue}}; +assign ldq_rel1_upd_gpr = ldq_rel1_upd_gpr_q & (~(ldqe_dGpr_q | ldqe_kill)); + +// Instruction Complete detection, completion report is dependent on the instruction +assign ldqe_rel2_drop_cpl_rpt = ldqe_lock_set_q | ldqe_watch_set_q | ldqe_resv_q | ldqe_sent_cpl_q | ldqe_need_cpl_q; +assign ldqe_rel3_drop_cpl_rpt_d = ldqe_rel2_drop_cpl_rpt; +assign ldqe_reld_cpl_rpt = (ldqe_lock_set_q | ldqe_watch_set_q | ldqe_resv_q) & (~(ldqe_sent_cpl_q | ldqe_need_cpl_q)); +assign ldq_rel2_send_cpl_ok = ldq_rel2_upd_gpr_q & (~ldqe_rel2_drop_cpl_rpt); +assign ldq_rel6_send_cpl_ok = ldq_rel6_req_done_q & ldqe_reld_cpl_rpt; +assign ldq_rel_send_cpl_ok = ldq_rel2_send_cpl_ok | ldq_rel6_send_cpl_ok; +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// ORDER QUEUE REPORT COMPLETE CONTROL +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +// Need to pipe down reload complete indicator to rel3, at rel3, +// we have all the information we need for the reload completion report +// ldawx, dcbt[st]ls, and larx will never send there complete report +// back to the order queue +assign ldq_rel3_odq_cpl = ldq_rel3_upd_gpr_q & (~ldqe_rel3_drop_cpl_rpt_q); + +// Muxing Reload Request from LoadMiss Queue and Gather Queue to send to the Order Queue +always @(*) begin: odqCplMux + reg [0:`ITAG_SIZE_ENC-1] iTag; + reg ecc; + reg eccue; + reg [0:1] dvcEn; + reg [0:3] dacrw; + reg [0:`THREADS-1] tid; + reg nFlush; + reg np1Flush; + reg [0:3] pEvents; + //(* analysis_not_referenced="true" *) + integer ldq; + + iTag = {`ITAG_SIZE_ENC{1'b0}}; + ecc = 1'b0; + eccue = 1'b0; + dvcEn = {2{1'b0}}; + dacrw = {4{1'b0}}; + tid = {`THREADS{1'b0}}; + nFlush = 1'b0; + np1Flush = 1'b0; + pEvents = {4{1'b0}}; + for (ldq=0; ldq <= (`LMQ_ENTRIES+`LGQ_ENTRIES)-1; ldq=ldq+1) begin : odqCplMux + if (ldq < `LMQ_ENTRIES) begin : lmqEntry + iTag = (ldqe_itag_q[ldq] & {`ITAG_SIZE_ENC{ldq_rel3_odq_cpl[ldq]}}) | iTag; + ecc = (ldqe_upd_gpr_ecc_q[ldq] & ldq_rel3_odq_cpl[ldq]) | ecc; + eccue = (ldqe_upd_gpr_eccue_q[ldq] & ldq_rel3_odq_cpl[ldq]) | eccue; + dvcEn = (ldqe_dvc_q[ldq] & {2{ldq_rel3_odq_cpl[ldq]}}) | dvcEn; + dacrw = (ldqe_dacrw_q[ldq] & {4{ldq_rel3_odq_cpl[ldq]}}) | dacrw; + tid = (ldqe_thrd_id_q[ldq] & {`THREADS{ldq_rel3_odq_cpl[ldq]}}) | tid; + nFlush = (ldqe_back_inv_nFlush_q[ldq] & ldq_rel3_odq_cpl[ldq]) | nFlush; + np1Flush = (ldqe_back_inv_np1Flush_q[ldq] & ldq_rel3_odq_cpl[ldq]) | np1Flush; + pEvents = (ldqe_perf_events_q[ldq] & {4{ldq_rel3_odq_cpl[ldq]}}) | pEvents; + end + if (ldq >= `LMQ_ENTRIES) begin : lgqEntry + iTag = (lgqe_itag_q[ldq-`LMQ_ENTRIES] & {`ITAG_SIZE_ENC{lgq_rel3_upd_gpr_q[ldq-`LMQ_ENTRIES]}}) | iTag; + ecc = (lgqe_upd_gpr_ecc_q[ldq-`LMQ_ENTRIES] & lgq_rel3_upd_gpr_q[ldq-`LMQ_ENTRIES]) | ecc; + eccue = (lgqe_upd_gpr_eccue_q[ldq-`LMQ_ENTRIES] & lgq_rel3_upd_gpr_q[ldq-`LMQ_ENTRIES]) | eccue; + dvcEn = (lgqe_dvc_q[ldq-`LMQ_ENTRIES] & {2{lgq_rel3_upd_gpr_q[ldq-`LMQ_ENTRIES]}}) | dvcEn; + dacrw = (lgqe_dacrw_q[ldq-`LMQ_ENTRIES] & {4{lgq_rel3_upd_gpr_q[ldq-`LMQ_ENTRIES]}}) | dacrw; + tid = (lgqe_thrd_id_q[ldq-`LMQ_ENTRIES] & {`THREADS{lgq_rel3_upd_gpr_q[ldq-`LMQ_ENTRIES]}}) | tid; + nFlush = (lgqe_back_inv_nFlush_q[ldq-`LMQ_ENTRIES] & lgq_rel3_upd_gpr_q[ldq-`LMQ_ENTRIES]) | nFlush; + np1Flush = (lgqe_back_inv_np1Flush_q[ldq-`LMQ_ENTRIES] & lgq_rel3_upd_gpr_q[ldq-`LMQ_ENTRIES]) | np1Flush; + pEvents = (lgqe_perf_events_q[ldq-`LMQ_ENTRIES] & {4{lgq_rel3_upd_gpr_q[ldq-`LMQ_ENTRIES]}}) | pEvents; + end + end + ldq_rel3_odq_itag = iTag; + ldq_rel3_odq_ecc = ecc; + ldq_rel3_odq_eccue = eccue; + ldq_rel3_odq_dvc = dvcEn; + ldq_rel3_odq_dacrw = dacrw; + ldq_rel3_odq_tid = tid; + ldq_rel3_odq_nFlush = nFlush; + ldq_rel3_odq_np1Flush = np1Flush; + ldq_rel3_odq_pEvents = pEvents; +end + +// Determine if we should be taking a debug interrupt +assign dbg_int_en_d = ctl_lsq_dbg_int_en; +assign ldq_rel3_odq_dbg_int_en = |(ldq_rel3_odq_tid & dbg_int_en_q); + +// CritQW got ECC Back-Invalidate and not CP_NEXT +assign ldq_rel3_odq_oth_flush = ldq_rel3_odq_ecc | ldq_rel3_odq_nFlush; +assign ldq_rel3_dacrw[0:1] = (ldq_rel3_odq_dacrw[0:1] | ldq_rel3_odq_dvc) & {2{~(ldq_rel3_odq_oth_flush | ldq_rel3_odq_np1Flush)}}; +assign ldq_rel3_dacrw[2:3] = ldq_rel3_odq_dacrw[2:3] & {2{~(ldq_rel3_odq_oth_flush | ldq_rel3_odq_np1Flush)}}; +assign ldq_rel3_odq_val = ldq_rel3_odq_cpl & (~(ldqe_resolved_q | ldqe_kill)); +assign lgq_rel3_odq_val = lgq_rel3_upd_gpr_q & lgqe_valid_q & (~(lgqe_resolved_q | lgqe_kill)); + +// Need to pipeline ODQ update for a few cycles +// Need to check at the end to cover the window +// where the Order Queue already reported resolved +assign ldq_rel4_odq_cpl_d = ldq_rel3_odq_val; +assign ldq_rel5_odq_cpl_d = ldq_rel4_odq_cpl_q & (~ldqe_resolved); +assign ldq_rel5_odq_cpl = ldq_rel5_odq_cpl_q & (~ldqe_resolved_q); +assign lgq_rel4_upd_gpr_d = lgq_rel3_upd_gpr_q & (~lgqe_kill); +assign lgq_rel5_upd_gpr_d = lgq_rel4_upd_gpr_q & (~lgqe_kill); +assign lgq_rel5_odq_cpl = lgq_rel5_upd_gpr_q & lgqe_valid_q & (~(lgqe_resolved_q | lgqe_kill)); + +// Report to ODQ, ODQ needs to update its entry with the following information +assign ldq_odq_upd_val = |(ldq_rel3_odq_val | lgq_rel3_odq_val); +assign ldq_odq_upd_itag = ldq_rel3_odq_itag; +assign ldq_odq_upd_nFlush = ldq_rel3_odq_oth_flush | |(ldq_rel3_dacrw & {4{ldq_rel3_odq_dbg_int_en}}); +assign ldq_odq_upd_np1Flush = ldq_rel3_odq_np1Flush; +assign ldq_odq_upd_dacrw = ldq_rel3_dacrw; +assign ldq_odq_upd_tid = ldq_rel3_odq_tid; +assign ldq_odq_upd_pEvents = ldq_rel3_odq_pEvents; +assign ldq_odq_upd_eccue = ldq_rel3_odq_eccue; +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// ENTRY REMOVAL and CREDIT RETURN ARBITRATION +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Doing a Round Robin Scheme within each 4 entries (called Groups) +// followed by a Round Robin Scheme within each Group + +// Expand LDQ to max supported +generate begin : cplExp + genvar grp; + for (grp=0; grp<=(`LMQ_ENTRIES+`LGQ_ENTRIES-1)/4; grp=grp+1) begin : cplExp + genvar b; + for (b=0; b<4; b=b+1) begin : bitSel + if ((grp*4)+b < `LMQ_ENTRIES) begin : ldqExst + assign ldqe_remove[(grp*4)+b] = ldqe_send_cpl[(grp*4)+b]; + end + if (((grp*4)+b >= `LMQ_ENTRIES) && ((grp*4)+b < `LMQ_ENTRIES+`LGQ_ENTRIES)) begin : lgqExst + assign ldqe_remove[(grp*4)+b] = lgqe_send_cpl[(grp*4)+b-`LMQ_ENTRIES]; + end + if ((grp*4)+b >= `LMQ_ENTRIES+`LGQ_ENTRIES) begin : ldqNExst + assign ldqe_remove[(grp*4)+b] = 1'b0; + end + end + end + end +endgenerate + +// Entry Select within Group +// Round Robin Scheme within each 4 entries in a Group +generate begin : cplGrpEntry + genvar grp; + for (grp = 0; grp <= (`LMQ_ENTRIES + `LGQ_ENTRIES - 1)/4; grp = grp + 1) begin : cplGrpEntry + assign cpl_grpEntry_val[grp] = ldqe_remove[grp * 4:(grp * 4) + 3]; + + assign cpl_grpEntry_sel[grp][0] = (cpl_grpEntry_last_sel_q[grp][0] & ~(|cpl_grpEntry_val[grp][1:3]) & cpl_grpEntry_val[grp][0]) | + (cpl_grpEntry_last_sel_q[grp][1] & ~(|cpl_grpEntry_val[grp][2:3]) & cpl_grpEntry_val[grp][0]) | + (cpl_grpEntry_last_sel_q[grp][2] & ~cpl_grpEntry_val[grp][3] & cpl_grpEntry_val[grp][0]) | + (cpl_grpEntry_last_sel_q[grp][3] & cpl_grpEntry_val[grp][0]); + + assign cpl_grpEntry_sel[grp][1] = (cpl_grpEntry_last_sel_q[grp][0] & cpl_grpEntry_val[grp][1]) | + (cpl_grpEntry_last_sel_q[grp][1] & ~(|{cpl_grpEntry_val[grp][0], cpl_grpEntry_val[grp][2:3]}) & cpl_grpEntry_val[grp][1]) | + (cpl_grpEntry_last_sel_q[grp][2] & ~(|{cpl_grpEntry_val[grp][0], cpl_grpEntry_val[grp][3]}) & cpl_grpEntry_val[grp][1]) | + (cpl_grpEntry_last_sel_q[grp][3] & ~cpl_grpEntry_val[grp][0] & cpl_grpEntry_val[grp][1]); + + assign cpl_grpEntry_sel[grp][2] = (cpl_grpEntry_last_sel_q[grp][0] & ~cpl_grpEntry_val[grp][1] & cpl_grpEntry_val[grp][2]) | + (cpl_grpEntry_last_sel_q[grp][1] & cpl_grpEntry_val[grp][2]) | + (cpl_grpEntry_last_sel_q[grp][2] & ~(|{cpl_grpEntry_val[grp][0:1], cpl_grpEntry_val[grp][3]}) & cpl_grpEntry_val[grp][2]) | + (cpl_grpEntry_last_sel_q[grp][3] & ~(|cpl_grpEntry_val[grp][0:1]) & cpl_grpEntry_val[grp][2]); + + assign cpl_grpEntry_sel[grp][3] = (cpl_grpEntry_last_sel_q[grp][0] & ~(|cpl_grpEntry_val[grp][1:2]) & cpl_grpEntry_val[grp][3]) | + (cpl_grpEntry_last_sel_q[grp][1] & ~cpl_grpEntry_val[grp][2] & cpl_grpEntry_val[grp][3]) | + (cpl_grpEntry_last_sel_q[grp][2] & cpl_grpEntry_val[grp][3]) | + (cpl_grpEntry_last_sel_q[grp][3] & ~(|cpl_grpEntry_val[grp][0:2]) & cpl_grpEntry_val[grp][3]); + + // Load Queue Group Selected + assign cpl_grpEntry_sent[grp] = |(ldqe_cpl_sent[grp*4:(grp*4)+3]); + assign cpl_grpEntry_last_sel_d[grp] = cpl_grpEntry_sent[grp] ? cpl_grpEntry_sel[grp] : cpl_grpEntry_last_sel_q[grp]; + + // Mux Load Queue Entry within a Group + always @(*) begin: cplMux + reg [0:`ITAG_SIZE_ENC-1] iTag; + reg ecc; + reg eccue; + reg [0:3] dacrw; + reg [0:1] dvc; + reg [0:`THREADS-1] tid; + reg nFlush; + reg np1Flush; + reg [0:3] pEvents; + reg larx; + //(* analysis_not_referenced="true" *) + integer ldq; + + iTag = {`ITAG_SIZE_ENC{1'b0}}; + ecc = 1'b0; + eccue = 1'b0; + dvc = {2{1'b0}}; + dacrw = {4{1'b0}}; + tid = {`THREADS{1'b0}}; + nFlush = 1'b0; + np1Flush = 1'b0; + pEvents = {4{1'b0}}; + larx = 1'b0; + for (ldq=0; ldq<4; ldq=ldq+1) begin : cplMux + if ((grp*4)+ldq < `LMQ_ENTRIES) begin : ldqExst + iTag = (ldqe_itag_q[(grp*4)+ldq] & {`ITAG_SIZE_ENC{cpl_grpEntry_sel[grp][ldq]}}) | iTag; + ecc = (ldqe_nFlush_ecc_err[(grp*4)+ldq] & cpl_grpEntry_sel[grp][ldq]) | ecc; + eccue = (ldqe_upd_gpr_eccue_q[(grp*4)+ldq] & cpl_grpEntry_sel[grp][ldq]) | eccue; + dvc = (ldqe_dvc_q[(grp*4)+ldq] & {2{cpl_grpEntry_sel[grp][ldq]}}) | dvc; + dacrw = (ldqe_dacrw_q[(grp*4)+ldq] & {4{cpl_grpEntry_sel[grp][ldq]}}) | dacrw; + tid = (ldqe_thrd_id_q[(grp*4)+ldq] & {`THREADS{cpl_grpEntry_sel[grp][ldq]}}) | tid; + nFlush = (ldqe_back_inv_nFlush_q[(grp*4)+ldq] & cpl_grpEntry_sel[grp][ldq]) | nFlush; + np1Flush = (ldqe_back_inv_np1Flush_q[(grp*4)+ldq] & cpl_grpEntry_sel[grp][ldq]) | np1Flush; + pEvents = (ldqe_perf_events_q[(grp*4)+ldq] & {4{cpl_grpEntry_sel[grp][ldq]}}) | pEvents; + larx = (ldqe_resv_q[(grp*4)+ldq] & cpl_grpEntry_sel[grp][ldq]) | larx; + end + if (((grp*4)+ldq >= `LMQ_ENTRIES) && ((grp*4)+ldq < `LMQ_ENTRIES+`LGQ_ENTRIES)) begin : lgqExst + iTag = (lgqe_itag_q[(grp*4)+ldq-`LMQ_ENTRIES] & {`ITAG_SIZE_ENC{cpl_grpEntry_sel[grp][ldq]}}) | iTag; + ecc = (lgqe_upd_gpr_ecc_q[(grp*4)+ldq-`LMQ_ENTRIES] & cpl_grpEntry_sel[grp][ldq]) | ecc; + eccue = (lgqe_upd_gpr_eccue_q[(grp*4)+ldq-`LMQ_ENTRIES] & cpl_grpEntry_sel[grp][ldq]) | eccue; + dvc = (lgqe_dvc_q[(grp*4)+ldq-`LMQ_ENTRIES] & {2{cpl_grpEntry_sel[grp][ldq]}}) | dvc; + dacrw = (lgqe_dacrw_q[(grp*4)+ldq-`LMQ_ENTRIES] & {4{cpl_grpEntry_sel[grp][ldq]}}) | dacrw; + tid = (lgqe_thrd_id_q[(grp*4)+ldq-`LMQ_ENTRIES] & {`THREADS{cpl_grpEntry_sel[grp][ldq]}}) | tid; + nFlush = (lgqe_back_inv_nFlush_q[(grp*4)+ldq-`LMQ_ENTRIES] & cpl_grpEntry_sel[grp][ldq]) | nFlush; + np1Flush = (lgqe_back_inv_np1Flush_q[(grp*4)+ldq-`LMQ_ENTRIES] & cpl_grpEntry_sel[grp][ldq]) | np1Flush; + pEvents = (lgqe_perf_events_q[(grp*4)+ldq-`LMQ_ENTRIES] & {4{cpl_grpEntry_sel[grp][ldq]}}) | pEvents; + end + end + cpl_grpEntry_iTag[grp] = iTag; + cpl_grpEntry_ecc[grp] = ecc; + cpl_grpEntry_eccue[grp] = eccue; + cpl_grpEntry_dvc[grp] = dvc; + cpl_grpEntry_dacrw[grp] = dacrw; + cpl_grpEntry_tid[grp] = tid; + cpl_grpEntry_nFlush[grp] = nFlush; + cpl_grpEntry_np1Flush[grp] = np1Flush; + cpl_grpEntry_pEvents[grp] = pEvents; + cpl_grpEntry_larx[grp] = larx; + end + end + end +endgenerate + +// Group Select Between all Groups +// Round Robin Scheme within Groups +generate begin : cplGrp + genvar grp; + for (grp=0; grp<=3; grp=grp+1) begin : cplGrp + if (grp <= (`LMQ_ENTRIES+`LGQ_ENTRIES- 1)/4) begin : grpExst + assign cpl_group_val[grp] = |(cpl_grpEntry_val[grp]); + end + if (grp > (`LMQ_ENTRIES+`LGQ_ENTRIES- 1)/4) begin : grpNExst + assign cpl_group_val[grp] = 1'b0; + end + end + end +endgenerate + +assign cpl_group_sel[0] = (cpl_group_last_sel_q[0] & ~(|cpl_group_val[1:3]) & cpl_group_val[0]) | + (cpl_group_last_sel_q[1] & ~(|cpl_group_val[2:3]) & cpl_group_val[0]) | + (cpl_group_last_sel_q[2] & ~cpl_group_val[3] & cpl_group_val[0]) | + (cpl_group_last_sel_q[3] & cpl_group_val[0]); + +assign cpl_group_sel[1] = (cpl_group_last_sel_q[0] & cpl_group_val[1]) | + (cpl_group_last_sel_q[1] & ~(|{cpl_group_val[0], cpl_group_val[2:3]}) & cpl_group_val[1]) | + (cpl_group_last_sel_q[2] & ~(|{cpl_group_val[0], cpl_group_val[3]}) & cpl_group_val[1]) | + (cpl_group_last_sel_q[3] & ~cpl_group_val[0] & cpl_group_val[1]); + +assign cpl_group_sel[2] = (cpl_group_last_sel_q[0] & ~cpl_group_val[1] & cpl_group_val[2]) | + (cpl_group_last_sel_q[1] & cpl_group_val[2]) | + (cpl_group_last_sel_q[2] & ~(|{cpl_group_val[0:1], cpl_group_val[3]}) & cpl_group_val[2]) | + (cpl_group_last_sel_q[3] & ~(|cpl_group_val[0:1]) & cpl_group_val[2]); + +assign cpl_group_sel[3] = (cpl_group_last_sel_q[0] & ~(|cpl_group_val[1:2]) & cpl_group_val[3]) | + (cpl_group_last_sel_q[1] & ~cpl_group_val[2] & cpl_group_val[3]) | + (cpl_group_last_sel_q[2] & cpl_group_val[3]) | + (cpl_group_last_sel_q[3] & ~(|cpl_group_val[0:2]) & cpl_group_val[3]); + +assign cpl_credit_sent = |(ldqe_cpl_sent); + +assign cpl_group_last_sel_d = cpl_credit_sent ? cpl_group_sel : cpl_group_last_sel_q; + +// Mux Load Queue Entry between Groups + +always @(*) begin: cplGrpLqMux + reg [0:`ITAG_SIZE_ENC-1] iTag; + reg ecc; + reg eccue; + reg [0:1] dvc; + reg [0:3] dacrw; + reg [0:`THREADS-1] tid; + reg nFlush; + reg np1Flush; + reg [0:3] pEvents; + reg larx; + //(* analysis_not_referenced="true" *) + integer grp; + + iTag = {`ITAG_SIZE_ENC{1'b0}}; + ecc = 1'b0; + eccue = 1'b0; + dvc = {2{1'b0}}; + dacrw = {4{1'b0}}; + tid = {`THREADS{1'b0}}; + nFlush = 1'b0; + np1Flush = 1'b0; + pEvents = {4{1'b0}}; + larx = 1'b0; + for (grp=0; grp<4; grp=grp+1) begin : cplGrpLqMux + if (grp <= (`LMQ_ENTRIES+`LGQ_ENTRIES-1)/4) begin : GrpExst + iTag = (cpl_grpEntry_iTag[grp] & {`ITAG_SIZE_ENC{cpl_group_sel[grp]}}) | iTag; + ecc = (cpl_grpEntry_ecc[grp] & cpl_group_sel[grp]) | ecc; + eccue = (cpl_grpEntry_eccue[grp] & cpl_group_sel[grp]) | eccue; + dvc = (cpl_grpEntry_dvc[grp] & {2{cpl_group_sel[grp]}}) | dvc; + dacrw = (cpl_grpEntry_dacrw[grp] & {4{cpl_group_sel[grp]}}) | dacrw; + tid = (cpl_grpEntry_tid[grp] & {`THREADS{cpl_group_sel[grp]}}) | tid; + nFlush = (cpl_grpEntry_nFlush[grp] & cpl_group_sel[grp]) | nFlush; + np1Flush = (cpl_grpEntry_np1Flush[grp] & cpl_group_sel[grp]) | np1Flush; + pEvents = (cpl_grpEntry_pEvents[grp] & {4{cpl_group_sel[grp]}}) | pEvents; + larx = (cpl_grpEntry_larx[grp] & cpl_group_sel[grp]) | larx; + end + end + cpl_send_itag = iTag; + cpl_ecc_dec = ecc; + cpl_eccue_dec = eccue; + cpl_dvc = dvc; + cpl_dacrw = dacrw; + cpl_tid = tid; + cpl_nFlush = nFlush; + cpl_np1Flush = np1Flush; + cpl_pEvents = pEvents; + cpl_larx = larx; +end + +// Completion Report has been sent +generate begin : credSent + genvar grp; + for (grp = 0; grp <= (`LMQ_ENTRIES + `LGQ_ENTRIES - 1)/4; grp = grp + 1) begin : credSent + genvar ldq; + for (ldq=0; ldq<=3; ldq=ldq+1) begin : ldqEntry + assign ldqe_cpl_sel[ldq+(grp*4)] = cpl_grpEntry_sel[grp][ldq] & cpl_group_sel[grp]; + + if ((grp*4)+ldq < `LMQ_ENTRIES) begin : ldq_cpl + assign ldqe_cpl_sent[ldq+(grp*4)] = ldqe_cpl_sel[ldq+(grp*4)] & ~(ldqe_kill[ldq+(grp*4)] | ldq_cpl_odq_val); + end + + if ((grp*4)+ldq >= `LMQ_ENTRIES) begin : lgq_cpl + assign ldqe_cpl_sent[ldq+(grp*4)] = ldqe_cpl_sel[ldq+(grp*4)] & ~(lgqe_kill[ldq+(grp*4)-`LMQ_ENTRIES] | ldq_cpl_odq_val); + assign lgqe_cpl_sent[ldq+(grp*4)-`LMQ_ENTRIES] = ldqe_cpl_sent[ldq+(grp*4)]; + end + end + end + end +endgenerate + +// Completion Report bus for exceptions, loadhits, orderq flush, loadmisses, loadmiss with ecc, and storetypes +// Priority Selection +// 1) ORDERQ has highest priority (loadhits or flushes) +// 2) LDQ has last priority (loadmisses) +assign ldq_cpl_odq_zap = |(odq_ldq_report_tid & iu_lq_cp_flush_q); +assign ldq_cpl_odq_val = odq_ldq_resolved & (odq_ldq_n_flush | odq_ldq_report_needed) & (~ldq_cpl_odq_zap); +assign ldq_cpl_odq_dbg_int_en = |(odq_ldq_report_tid & dbg_int_en_q); +assign ldq_cpl_odq_n_flush = |(odq_ldq_report_dacrw &{4{ldq_cpl_odq_dbg_int_en}}) | odq_ldq_n_flush; +assign ldq_cpl_odq_dacrw = odq_ldq_report_dacrw &{4{~odq_ldq_n_flush}}; +assign ldq_cpl_odq_eccue = odq_ldq_report_eccue; +assign ldq_cpl_pending = |(ldqe_cpl_sent); +assign ldq_execute_vld = cpl_tid & {`THREADS{ldq_cpl_pending}}; +assign odq_execute_vld = odq_ldq_report_tid & {`THREADS{ldq_cpl_odq_val}}; +assign lq1_iu_execute_vld_d = ldq_execute_vld | odq_execute_vld; + +assign lq1_iu_n_flush_d = (ldq_cpl_odq_val & ldq_cpl_odq_n_flush) | // ODQ N flush report + (ldq_cpl_pending & ldq_cpl_n_flush); // LDQ N flush report + +assign lq1_iu_np1_flush_d = (ldq_cpl_odq_val & odq_ldq_np1_flush) | // ODQ NP1 flush report + (ldq_cpl_pending & ldq_cpl_np1_flush); // LDQ NP1 flush report + +assign lq1_iu_exception_val_d = (ldq_cpl_odq_val & ldq_cpl_odq_eccue) | // ODQ MCHK report + (ldq_cpl_pending & cpl_eccue_dec); // LDQ MCHK report + +assign lq1_iu_itag_d = ldq_cpl_odq_val ? odq_ldq_report_itag : cpl_send_itag; + +// Need to report pipelined DVC compare results when completion report is piped reload +assign ldq_cpl_dbg_int_en = |(cpl_tid & dbg_int_en_q); +// CritQW got ECC Back-Invalidate and not CP_NEXT +assign ldq_cpl_oth_flush = cpl_ecc_dec | cpl_nFlush; +// DEBUG INTERRUPT +assign ldq_cpl_n_flush = |(ldq_cpl_dacrw & {4{ldq_cpl_dbg_int_en}}) | ldq_cpl_oth_flush; +assign ldq_cpl_np1_flush = cpl_np1Flush; + +// Select LDQ DVC +assign ldq_cpl_dvc = cpl_dvc; + +assign ldq_cpl_dacrw[0:1] = (cpl_dacrw[0:1] | ldq_cpl_dvc) & {2{~(ldq_cpl_oth_flush | ldq_cpl_np1_flush)}}; +assign ldq_cpl_dacrw[2:3] = cpl_dacrw[2:3] & {2{~(ldq_cpl_oth_flush | ldq_cpl_np1_flush)}}; + +// DACR report for piped reload +assign lq1_iu_dacrw_d = ldq_cpl_odq_val ? ldq_cpl_odq_dacrw : ldq_cpl_dacrw; +assign lq1_iu_perf_events_d = ldq_cpl_odq_val ? odq_ldq_report_pEvents : cpl_pEvents; +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Performance Events +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// LARX Finished Performance Event +assign ldq_cpl_larx_d = ldq_execute_vld & {`THREADS{cpl_larx}}; +assign ldq_cpl_binv_d = ldq_execute_vld & {`THREADS{cpl_nFlush}}; +assign ldq_rel_cmmt_d = |(ldq_rel2_sentL1); +assign ldq_rel_need_hole_d = ldq_l2_resp_hold_all | ldq_rel_arb_hold_all; +assign ldq_rel_latency_d = ldqe_req_outstanding[0]; + +assign perf_ldq_cpl_larx = ldq_cpl_larx_q; +assign perf_ldq_cpl_binv = ldq_cpl_binv_q; +assign perf_ldq_rel_attmpt = |ldq_rel1_entrySent_q; +assign perf_ldq_rel_cmmt = ldq_rel_cmmt_q; +assign perf_ldq_rel_need_hole = ldq_rel_need_hole_q; +assign perf_ldq_rel_latency = ldq_rel_latency_q; +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Pervasive Error Reporting +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +tri_direct_err_rpt #(.WIDTH(4)) err_rpt( + .vd(vdd), + .gd(gnd), + .err_in({ldq_err_inval_rel_q, + ldq_err_ecc_det_q, + ldq_err_ue_det_q, + ldq_rel3_rdat_par_err}), + .err_out({lq_pc_err_invld_reld, + lq_pc_err_l2intrf_ecc, + lq_pc_err_l2intrf_ue, + lq_pc_err_relq_parity}) +); + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// OUTPUTS +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +// RV Control +assign ldq_l2_resp_hold_all = l2_rel0_resp_ldq_val_q & ldq_l2_rel0_qHitBlk_q; +assign ldq_rel_arb_hold_all = ldq_rel0_arb_thresh & (~l2_rel0_resp_ldq_val_q); +assign ldq_hold_all_req = ldq_l2_resp_hold_all | ldq_rel_arb_hold_all | l2_back_inv_val; +assign ldq_rel1_gpr_val = ldq_rel1_gpr_val_q | lgq_rel1_gpr_val_q; +assign lsq_ctl_ex5_ldq_restart = ex5_ldq_restart; +assign ldq_rv_set_hold = ex5_setHold; +assign ldq_rv_clr_hold = ldq_clrHold_tid; + +// RV Release Dependent ITAGs +assign ldq_itag2_rel_val = |(ldqe_relmin1_upd_gpr | lgqe_relmin1_upd_gpr); +assign lq_rv_itag2_vld = ldq_relmin1_tid & {`THREADS{ldq_itag2_rel_val}}; +assign lq_rv_itag2 = ldq_relmin1_iTag; + +// Physical Register File update data +assign ldq_rel2_byte_swap = ldq_rel2_byte_swap_q; +assign ldq_rel2_data = ldq_rel2_rot_data; + +// Interface to Completion +assign lq1_iu_execute_vld = lq1_iu_execute_vld_q; +assign lq1_iu_itag = lq1_iu_itag_q; +assign lq1_iu_exception_val = lq1_iu_exception_val_q; +assign lq1_iu_exception = 6'b011010; +assign lq1_iu_n_flush = lq1_iu_n_flush_q; +assign lq1_iu_np1_flush = lq1_iu_np1_flush_q; +assign lq1_iu_dacr_type = 1'b1; +assign lq1_iu_dacrw = lq1_iu_dacrw_q; +assign lq1_iu_perf_events = lq1_iu_perf_events_q; + +// Performance Events +assign lsq_ctl_ex6_ldq_events = {perf_ex6_ldq_full_restart, perf_ex6_ldq_hit_restart, + perf_ex6_lgq_full_restart, perf_ex6_lgq_qwhit_restart}; +assign lsq_perv_ex7_events = ex7_pfetch_blk_tid; + +assign lsq_perv_ldq_events = {perf_ldq_rel_attmpt, perf_ldq_rel_cmmt, perf_ldq_rel_need_hole, + perf_ldq_rel_latency, perf_ldq_cpl_larx, perf_ldq_cpl_binv}; + +// Interface to Store Queue +assign ldq_stq_rel1_blk_store = ldq_stq_rel1_blk_store_q; + +// Store Hit LoadMiss Queue Entry +assign ldq_stq_ex5_ldm_hit = ex5_ldm_hit_q; +assign ldq_stq_ex5_ldm_entry = ex5_ldm_entry & {`LMQ_ENTRIES{~(ex5_drop_req_val | ex5_ldreq_flushed | ex5_pfetch_flushed)}}; +assign ldq_stq_ldm_cpl = ldqe_req_cmpl_q; +assign ldq_stq_stq4_dir_upd = ldq_rel4_set_val_q; +assign ldq_stq_stq4_cclass = ldq_rel4_cclass_q; + +// Reload Update L1 Data Cache +assign ldq_dat_stq1_stg_act = ldq_rel1_val_q; +assign lsq_dat_rel1_data_val = ldq_rel1_data_val; +assign lsq_dat_rel1_qw = ldq_rel1_resp_qw_q; + +// Reload Update L1 Directory +assign ldq_ctl_stq1_stg_act = ldq_rel1_val_q; +assign lsq_ctl_rel1_clr_val = ldq_rel1_clr_val; +assign lsq_ctl_rel1_set_val = ldq_rel1_set_val; +assign lsq_ctl_rel2_upd_val = ldq_rel2_set_val_q & ~(rel2_eccdet_err | ldq_rel2_rdat_perr); +assign lsq_ctl_rel1_data_val = ldq_rel1_data_val; +assign lsq_ctl_rel1_thrd_id = ldq_rel1_dir_tid_q; +assign lsq_ctl_rel1_back_inv = ldq_rel1_mux_back_inv; +assign lsq_ctl_rel1_tag = ldq_rel1_cTag_q; +assign lsq_ctl_rel1_classid = ldq_rel1_classID_q; +assign lsq_ctl_rel1_lock_set = ldq_rel1_lockSet_q; +assign lsq_ctl_rel1_watch_set = ldq_rel1_watchSet_q; +assign lsq_ctl_rel3_l1dump_val = ldq_rel3_l1_dump_val; +assign lsq_ctl_rel3_clr_relq = ldq_rel3_clr_relq_q; + +// Common between Reload and COMMIT Pipe +assign ldq_arb_rel1_data_sel = ldq_rel1_data_sel_q | ldq_rel1_gpr_val; +assign ldq_arb_rel1_axu_val = ldq_rel1_axu_q; +assign ldq_arb_rel1_op_size = ldq_rel1_opsize_q; +assign ldq_arb_rel1_addr = ldq_rel1_p_addr_q; +assign ldq_arb_rel1_ci = ldq_rel1_wimge_i_q; +assign ldq_arb_rel1_byte_swap = ldq_rel1_byte_swap_q; +assign ldq_arb_rel1_thrd_id = ldq_rel1_tid_q; +assign ldq_arb_rel1_data = ldq_rel1_data; + +// Reload Update Physical Register +assign lsq_ctl_rel1_gpr_val = ldq_rel1_gpr_val; +assign lsq_ctl_rel1_ta_gpr = ldq_rel1_tGpr_q; +assign lsq_ctl_rel1_upd_gpr = |(ldq_rel1_upd_gpr) | |(lgq_rel1_upd_gpr); + +// Need to block Reloads and Reissue Stores if Load Queue has issued instructions +assign lsq_ctl_rel2_blk_req = rel2_blk_req_q; + +// L2 request Available +assign ldq_arb_ld_req_pwrToken = ((ex5_ldreq_val_q | ex5_pfetch_val_q) & (~ldq_l2_req_need_send)) | fifo_ldq_req_val_q[0]; +assign ldq_arb_ld_req_avail = (ex5_ldreq_val & (~(ex5_drop_req_val | ldq_l2_req_need_send))) | + fifo_ldq_req0_avail; +assign ldq_odq_vld = ((ex5_odq_ldreq_val_q & (~ex5_restart_val)) | ex5_streq_val_q | (ex5_othreq_val_q & (~ex5_restart_val))) & (~ex5_stg_flush); +assign ldq_odq_pfetch_vld = ex5_pfetch_val; +assign ldq_odq_wimge_i = ex5_wimge_q[1]; +assign ldq_odq_ex6_pEvents = ex6_cmmt_perf_events_q; + +// All reloads for each Load Queue Entries have completed +assign lq_xu_quiesce = lq_xu_quiesce_q; +assign lq_mm_lmq_stq_empty = lq_mm_lmq_stq_empty_q; +assign lq_pc_ldq_quiesce = lq_pc_ldq_quiesce_q; +assign lq_pc_stq_quiesce = lq_pc_stq_quiesce_q; +assign lq_pc_pfetch_quiesce = lq_pc_pfetch_quiesce_q; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// REGISTERS +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr0_cls_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_xucr0_cls_offset]), + .scout(sov[spr_xucr0_cls_offset]), + .din(spr_xucr0_cls_d), + .dout(spr_xucr0_cls_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_lsucr0_lge_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_lsucr0_lge_offset]), + .scout(sov[spr_lsucr0_lge_offset]), + .din(spr_lsucr0_lge_d), + .dout(spr_lsucr0_lge_q) +); + + +tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) spr_lsucr0_lca_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_lsucr0_lca_offset:spr_lsucr0_lca_offset + 3 - 1]), + .scout(sov[spr_lsucr0_lca_offset:spr_lsucr0_lca_offset + 3 - 1]), + .din(spr_lsucr0_lca_d), + .dout(spr_lsucr0_lca_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) l2_rel0_resp_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[l2_rel0_resp_val_offset]), + .scout(sov[l2_rel0_resp_val_offset]), + .din(l2_rel0_resp_val_d), + .dout(l2_rel0_resp_val_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) l2_rel0_resp_ldq_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[l2_rel0_resp_ldq_val_offset]), + .scout(sov[l2_rel0_resp_ldq_val_offset]), + .din(l2_rel0_resp_ldq_val_d), + .dout(l2_rel0_resp_ldq_val_q) +); + + +tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) l2_rel0_resp_cTag_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[l2_rel0_resp_cTag_offset:l2_rel0_resp_cTag_offset + 4 - 1]), + .scout(sov[l2_rel0_resp_cTag_offset:l2_rel0_resp_cTag_offset + 4 - 1]), + .din(l2_rel0_resp_cTag_d), + .dout(l2_rel0_resp_cTag_q) +); + + +tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) l2_rel0_resp_qw_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[l2_rel0_resp_qw_offset:l2_rel0_resp_qw_offset + 3 - 1]), + .scout(sov[l2_rel0_resp_qw_offset:l2_rel0_resp_qw_offset + 3 - 1]), + .din(l2_rel0_resp_qw_d), + .dout(l2_rel0_resp_qw_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) l2_rel0_resp_crit_qw_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[l2_rel0_resp_crit_qw_offset]), + .scout(sov[l2_rel0_resp_crit_qw_offset]), + .din(l2_rel0_resp_crit_qw_d), + .dout(l2_rel0_resp_crit_qw_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) l2_rel0_resp_l1_dump_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[l2_rel0_resp_l1_dump_offset]), + .scout(sov[l2_rel0_resp_l1_dump_offset]), + .din(l2_rel0_resp_l1_dump_d), + .dout(l2_rel0_resp_l1_dump_q) +); + + +tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_algebraic_sel_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel1_algebraic_sel_offset:ldq_rel1_algebraic_sel_offset + 4 - 1]), + .scout(sov[ldq_rel1_algebraic_sel_offset:ldq_rel1_algebraic_sel_offset + 4 - 1]), + .din(ldq_rel1_algebraic_sel_d), + .dout(ldq_rel1_algebraic_sel_q) +); + + +tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_rot_sel1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel1_rot_sel1_offset:ldq_rel1_rot_sel1_offset + 8 - 1]), + .scout(sov[ldq_rel1_rot_sel1_offset:ldq_rel1_rot_sel1_offset + 8 - 1]), + .din(ldq_rel1_rot_sel1_d), + .dout(ldq_rel1_rot_sel1_q) +); + + +tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_rot_sel2_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel1_rot_sel2_offset:ldq_rel1_rot_sel2_offset + 8 - 1]), + .scout(sov[ldq_rel1_rot_sel2_offset:ldq_rel1_rot_sel2_offset + 8 - 1]), + .din(ldq_rel1_rot_sel2_d), + .dout(ldq_rel1_rot_sel2_q) +); + + +tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_rot_sel3_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel1_rot_sel3_offset:ldq_rel1_rot_sel3_offset + 8 - 1]), + .scout(sov[ldq_rel1_rot_sel3_offset:ldq_rel1_rot_sel3_offset + 8 - 1]), + .din(ldq_rel1_rot_sel3_d), + .dout(ldq_rel1_rot_sel3_q) +); + + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) iu_lq_cp_flush_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[iu_lq_cp_flush_offset:iu_lq_cp_flush_offset + `THREADS - 1]), + .scout(sov[iu_lq_cp_flush_offset:iu_lq_cp_flush_offset + `THREADS - 1]), + .din(iu_lq_cp_flush_d), + .dout(iu_lq_cp_flush_q) +); + +generate begin : iu_lq_cp_next_itag_tid + genvar tid; + for (tid=0; tid<`THREADS; tid=tid+1) begin : iu_lq_cp_next_itag_tid + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) iu_lq_cp_next_itag_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[iu_lq_cp_next_itag_offset + `ITAG_SIZE_ENC * tid:iu_lq_cp_next_itag_offset + `ITAG_SIZE_ENC * (tid + 1) - 1]), + .scout(sov[iu_lq_cp_next_itag_offset + `ITAG_SIZE_ENC * tid:iu_lq_cp_next_itag_offset + `ITAG_SIZE_ENC * (tid + 1) - 1]), + .din(iu_lq_cp_next_itag[`ITAG_SIZE_ENC*tid:`ITAG_SIZE_ENC*(tid+1)-1]), + .dout(iu_lq_cp_next_itag_q[tid]) + ); + end + end +endgenerate + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) odq_ldq_n_flush_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[odq_ldq_n_flush_offset]), + .scout(sov[odq_ldq_n_flush_offset]), + .din(odq_ldq_n_flush_d), + .dout(odq_ldq_n_flush_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) odq_ldq_resolved_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[odq_ldq_resolved_offset]), + .scout(sov[odq_ldq_resolved_offset]), + .din(odq_ldq_resolved_d), + .dout(odq_ldq_resolved_q) +); + + +tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) odq_ldq_report_itag_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[odq_ldq_report_itag_offset:odq_ldq_report_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[odq_ldq_report_itag_offset:odq_ldq_report_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(odq_ldq_report_itag_d), + .dout(odq_ldq_report_itag_q) +); + + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) odq_ldq_report_tid_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[odq_ldq_report_tid_offset:odq_ldq_report_tid_offset + `THREADS - 1]), + .scout(sov[odq_ldq_report_tid_offset:odq_ldq_report_tid_offset + `THREADS - 1]), + .din(odq_ldq_report_tid_d), + .dout(odq_ldq_report_tid_q) +); + + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) rv_lq_rvs_empty_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rv_lq_rvs_empty_offset:rv_lq_rvs_empty_offset + `THREADS - 1]), + .scout(sov[rv_lq_rvs_empty_offset:rv_lq_rvs_empty_offset + `THREADS - 1]), + .din(rv_lq_rvs_empty_d), + .dout(rv_lq_rvs_empty_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel2_blk_req_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rel2_blk_req_offset]), + .scout(sov[rel2_blk_req_offset]), + .din(rel2_blk_req_d), + .dout(rel2_blk_req_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel2_rviss_blk_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rel2_rviss_blk_offset]), + .scout(sov[rel2_rviss_blk_offset]), + .din(rel2_rviss_blk_d), + .dout(rel2_rviss_blk_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel1_collide_binv_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel1_collide_binv_offset]), + .scout(sov[ldq_rel1_collide_binv_offset]), + .din(ldq_rel1_collide_binv_d), + .dout(ldq_rel1_collide_binv_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_stq_rel1_blk_store_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_stq_rel1_blk_store_offset]), + .scout(sov[ldq_stq_rel1_blk_store_offset]), + .din(ldq_stq_rel1_blk_store_d), + .dout(ldq_stq_rel1_blk_store_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_ldreq_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_ldreq_offset]), + .scout(sov[ex4_ldreq_offset]), + .din(ex4_ldreq_d), + .dout(ex4_ldreq_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_ldreq_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_ldreq_val_offset]), + .scout(sov[ex5_ldreq_val_offset]), + .din(ex5_ldreq_val_d), + .dout(ex5_ldreq_val_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_pfetch_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_pfetch_val_offset]), + .scout(sov[ex4_pfetch_val_offset]), + .din(ex4_pfetch_val_d), + .dout(ex4_pfetch_val_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_pfetch_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_pfetch_val_offset]), + .scout(sov[ex5_pfetch_val_offset]), + .din(ex5_pfetch_val_d), + .dout(ex5_pfetch_val_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_odq_ldreq_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_odq_ldreq_val_offset]), + .scout(sov[ex5_odq_ldreq_val_offset]), + .din(ex5_odq_ldreq_val_d), + .dout(ex5_odq_ldreq_val_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_streq_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_streq_val_offset]), + .scout(sov[ex5_streq_val_offset]), + .din(ex5_streq_val_d), + .dout(ex5_streq_val_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_othreq_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_othreq_val_offset]), + .scout(sov[ex5_othreq_val_offset]), + .din(ex5_othreq_val_d), + .dout(ex5_othreq_val_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_reserved_taken_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_reserved_taken_offset]), + .scout(sov[ex5_reserved_taken_offset]), + .din(ex5_reserved_taken_d), + .dout(ex5_reserved_taken_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_resv_taken_restart_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_resv_taken_restart_offset]), + .scout(sov[ex5_resv_taken_restart_offset]), + .din(ex5_resv_taken_restart_d), + .dout(ex5_resv_taken_restart_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) lq_xu_quiesce_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lq_xu_quiesce_offset:lq_xu_quiesce_offset + `THREADS - 1]), + .scout(sov[lq_xu_quiesce_offset:lq_xu_quiesce_offset + `THREADS - 1]), + .din(lq_xu_quiesce_d), + .dout(lq_xu_quiesce_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) lq_pc_ldq_quiesce_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lq_pc_ldq_quiesce_offset:lq_pc_ldq_quiesce_offset + `THREADS - 1]), + .scout(sov[lq_pc_ldq_quiesce_offset:lq_pc_ldq_quiesce_offset + `THREADS - 1]), + .din(lq_pc_ldq_quiesce_d), + .dout(lq_pc_ldq_quiesce_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) lq_pc_stq_quiesce_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lq_pc_stq_quiesce_offset:lq_pc_stq_quiesce_offset + `THREADS - 1]), + .scout(sov[lq_pc_stq_quiesce_offset:lq_pc_stq_quiesce_offset + `THREADS - 1]), + .din(lq_pc_stq_quiesce_d), + .dout(lq_pc_stq_quiesce_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) lq_pc_pfetch_quiesce_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lq_pc_pfetch_quiesce_offset:lq_pc_pfetch_quiesce_offset + `THREADS - 1]), + .scout(sov[lq_pc_pfetch_quiesce_offset:lq_pc_pfetch_quiesce_offset + `THREADS - 1]), + .din(lq_pc_pfetch_quiesce_d), + .dout(lq_pc_pfetch_quiesce_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq_mm_lmq_stq_empty_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lq_mm_lmq_stq_empty_offset]), + .scout(sov[lq_mm_lmq_stq_empty_offset]), + .din(lq_mm_lmq_stq_empty_d), + .dout(lq_mm_lmq_stq_empty_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_ldq_full_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_ldq_full_offset]), + .scout(sov[ex5_ldq_full_offset]), + .din(ex5_ldq_full_d), + .dout(ex5_ldq_full_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_ldq_full_restart_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_ldq_full_restart_offset]), + .scout(sov[ex5_ldq_full_restart_offset]), + .din(ex5_ldq_full_restart_d), + .dout(ex5_ldq_full_restart_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_ldq_hit_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_ldq_hit_offset]), + .scout(sov[ex5_ldq_hit_offset]), + .din(ex5_ldq_hit_d), + .dout(ex5_ldq_hit_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_ld_gath_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_ld_gath_offset]), + .scout(sov[ex5_ld_gath_offset]), + .din(ex5_ld_gath_d), + .dout(ex5_ld_gath_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_full_qHit_held_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_full_qHit_held_offset]), + .scout(sov[ldq_full_qHit_held_offset]), + .din(ldq_full_qHit_held_d), + .dout(ldq_full_qHit_held_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_resv_qHit_held_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_resv_qHit_held_offset]), + .scout(sov[ldq_resv_qHit_held_offset]), + .din(ldq_resv_qHit_held_d), + .dout(ldq_resv_qHit_held_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_oth_qHit_clr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_oth_qHit_clr_offset]), + .scout(sov[ldq_oth_qHit_clr_offset]), + .din(ldq_oth_qHit_clr_d), + .dout(ldq_oth_qHit_clr_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_ldq_set_hold_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_ldq_set_hold_offset]), + .scout(sov[ex5_ldq_set_hold_offset]), + .din(ex5_ldq_set_hold_d), + .dout(ex5_ldq_set_hold_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_ldq_restart_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_ldq_restart_offset]), + .scout(sov[ex5_ldq_restart_offset]), + .din(ex5_ldq_restart_d), + .dout(ex5_ldq_restart_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_ldq_full_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_ldq_full_offset]), + .scout(sov[ex6_ldq_full_offset]), + .din(ex6_ldq_full_d), + .dout(ex6_ldq_full_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_ldq_hit_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_ldq_hit_offset]), + .scout(sov[ex6_ldq_hit_offset]), + .din(ex6_ldq_hit_d), + .dout(ex6_ldq_hit_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_lgq_full_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_lgq_full_offset]), + .scout(sov[ex5_lgq_full_offset]), + .din(ex5_lgq_full_d), + .dout(ex5_lgq_full_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_lgq_full_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_lgq_full_offset]), + .scout(sov[ex6_lgq_full_offset]), + .din(ex6_lgq_full_d), + .dout(ex6_lgq_full_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_lgq_qwhit_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_lgq_qwhit_offset]), + .scout(sov[ex5_lgq_qwhit_offset]), + .din(ex5_lgq_qwhit_d), + .dout(ex5_lgq_qwhit_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_lgq_qwhit_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_lgq_qwhit_offset]), + .scout(sov[ex6_lgq_qwhit_offset]), + .din(ex6_lgq_qwhit_d), + .dout(ex6_lgq_qwhit_q) +); + +tri_rlmreg_p #(.WIDTH(`REAL_IFAR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex5_p_addr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_p_addr_offset:ex5_p_addr_offset + `REAL_IFAR_WIDTH - 1]), + .scout(sov[ex5_p_addr_offset:ex5_p_addr_offset + `REAL_IFAR_WIDTH - 1]), + .din(ex5_p_addr_d), + .dout(ex5_p_addr_q) +); + + +tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) ex5_wimge_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_wimge_offset:ex5_wimge_offset + 5 - 1]), + .scout(sov[ex5_wimge_offset:ex5_wimge_offset + 5 - 1]), + .din(ex5_wimge_d), + .dout(ex5_wimge_q) +); + +tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ex6_cmmt_perf_events_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_cmmt_perf_events_offset:ex6_cmmt_perf_events_offset + 4 - 1]), + .scout(sov[ex6_cmmt_perf_events_offset:ex6_cmmt_perf_events_offset + 4 - 1]), + .din(ex6_cmmt_perf_events_d), + .dout(ex6_cmmt_perf_events_q) +); + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex5_ldqe_set_all_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_ldqe_set_all_offset:ex5_ldqe_set_all_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ex5_ldqe_set_all_offset:ex5_ldqe_set_all_offset + `LMQ_ENTRIES - 1]), + .din(ex5_ldqe_set_all_d), + .dout(ex5_ldqe_set_all_q) +); + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex5_ldqe_set_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_ldqe_set_val_offset:ex5_ldqe_set_val_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ex5_ldqe_set_val_offset:ex5_ldqe_set_val_offset + `LMQ_ENTRIES - 1]), + .din(ex5_ldqe_set_val_d), + .dout(ex5_ldqe_set_val_q) +); + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex6_ldqe_pfetch_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_ldqe_pfetch_val_offset:ex6_ldqe_pfetch_val_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ex6_ldqe_pfetch_val_offset:ex6_ldqe_pfetch_val_offset + `LMQ_ENTRIES - 1]), + .din(ex6_ldqe_pfetch_val_d), + .dout(ex6_ldqe_pfetch_val_q) +); + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex7_ldqe_pfetch_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex7_ldqe_pfetch_val_offset:ex7_ldqe_pfetch_val_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ex7_ldqe_pfetch_val_offset:ex7_ldqe_pfetch_val_offset + `LMQ_ENTRIES - 1]), + .din(ex7_ldqe_pfetch_val_d), + .dout(ex7_ldqe_pfetch_val_q) +); + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex5_ldm_hit_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_ldm_hit_offset:ex5_ldm_hit_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ex5_ldm_hit_offset:ex5_ldm_hit_offset + `LMQ_ENTRIES - 1]), + .din(ex5_ldm_hit_d), + .dout(ex5_ldm_hit_q) +); + + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ldq_hold_tid_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_hold_tid_offset:ldq_hold_tid_offset + `THREADS - 1]), + .scout(sov[ldq_hold_tid_offset:ldq_hold_tid_offset + `THREADS - 1]), + .din(ldq_hold_tid_d), + .dout(ldq_hold_tid_q) +); + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES + 1), .INIT(2 ** (`LMQ_ENTRIES)), .NEEDS_SRESET(1)) fifo_ldq_req_nxt_ptr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fifo_ldq_req_nxt_ptr_offset:fifo_ldq_req_nxt_ptr_offset + (`LMQ_ENTRIES+1) - 1]), + .scout(sov[fifo_ldq_req_nxt_ptr_offset:fifo_ldq_req_nxt_ptr_offset + (`LMQ_ENTRIES+1) - 1]), + .din(fifo_ldq_req_nxt_ptr_d), + .dout(fifo_ldq_req_nxt_ptr_q) +); + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) fifo_ldq_req_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fifo_ldq_req_val_offset:fifo_ldq_req_val_offset + `LMQ_ENTRIES - 1]), + .scout(sov[fifo_ldq_req_val_offset:fifo_ldq_req_val_offset + `LMQ_ENTRIES - 1]), + .din(fifo_ldq_req_val_d), + .dout(fifo_ldq_req_val_q) +); + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) fifo_ldq_req_pfetch_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fifo_ldq_req_pfetch_offset:fifo_ldq_req_pfetch_offset + `LMQ_ENTRIES - 1]), + .scout(sov[fifo_ldq_req_pfetch_offset:fifo_ldq_req_pfetch_offset + `LMQ_ENTRIES - 1]), + .din(fifo_ldq_req_pfetch_d), + .dout(fifo_ldq_req_pfetch_q) +); + +generate begin : fifo_ldq_req_tid + genvar ldq; + for (ldq=0; ldq<`LMQ_ENTRIES; ldq=ldq+1) begin : fifo_ldq_req_tid + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) fifo_ldq_req_tid_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(fifo_ldq_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fifo_ldq_req_tid_offset + (`THREADS * ldq):fifo_ldq_req_tid_offset + (`THREADS * (ldq + 1)) - 1]), + .scout(sov[fifo_ldq_req_tid_offset + (`THREADS * ldq):fifo_ldq_req_tid_offset + (`THREADS * (ldq + 1)) - 1]), + .din(fifo_ldq_req_tid_d[ldq]), + .dout(fifo_ldq_req_tid_q[ldq]) + ); + end + end +endgenerate + +generate begin : fifo_ldq_req + genvar ldq0; + for (ldq0=0; ldq0<`LMQ_ENTRIES; ldq0=ldq0+1) begin : fifo_ldq_req + tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) fifo_ldq_req_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(fifo_ldq_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fifo_ldq_req_offset + (`LMQ_ENTRIES * ldq0):fifo_ldq_req_offset + (`LMQ_ENTRIES * (ldq0 + 1)) - 1]), + .scout(sov[fifo_ldq_req_offset + (`LMQ_ENTRIES * ldq0):fifo_ldq_req_offset + (`LMQ_ENTRIES * (ldq0 + 1)) - 1]), + .din(fifo_ldq_req_d[ldq0]), + .dout(fifo_ldq_req_q[ldq0]) + ); + end + end +endgenerate + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldqe_val_offset:ldqe_val_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldqe_val_offset:ldqe_val_offset + `LMQ_ENTRIES - 1]), + .din(ldqe_val_d), + .dout(ldqe_val_q) +); + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_req_cmpl_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldqe_req_cmpl_offset:ldqe_req_cmpl_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldqe_req_cmpl_offset:ldqe_req_cmpl_offset + `LMQ_ENTRIES - 1]), + .din(ldqe_req_cmpl_d), + .dout(ldqe_req_cmpl_q) +); + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_cntr_reset_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldqe_cntr_reset_offset:ldqe_cntr_reset_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldqe_cntr_reset_offset:ldqe_cntr_reset_offset + `LMQ_ENTRIES - 1]), + .din(ldqe_cntr_reset_d), + .dout(ldqe_cntr_reset_q) +); + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_resent_ecc_err_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldqe_resent_ecc_err_offset:ldqe_resent_ecc_err_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldqe_resent_ecc_err_offset:ldqe_resent_ecc_err_offset + `LMQ_ENTRIES - 1]), + .din(ldqe_resent_ecc_err_d), + .dout(ldqe_resent_ecc_err_q) +); + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_reset_cpl_rpt_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldqe_reset_cpl_rpt_offset:ldqe_reset_cpl_rpt_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldqe_reset_cpl_rpt_offset:ldqe_reset_cpl_rpt_offset + `LMQ_ENTRIES - 1]), + .din(ldqe_reset_cpl_rpt_d), + .dout(ldqe_reset_cpl_rpt_q) +); + +generate begin : ldqe_iTag + genvar ldq1; + for (ldq1=0; ldq1<`LMQ_ENTRIES; ldq1=ldq1+1) begin : ldqe_iTag + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ldqe_iTag_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_ldqe_act[ldq1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldqe_itag_offset + (`ITAG_SIZE_ENC * ldq1):ldqe_itag_offset + (`ITAG_SIZE_ENC * (ldq1 + 1)) - 1]), + .scout(sov[ldqe_itag_offset + (`ITAG_SIZE_ENC * ldq1):ldqe_itag_offset + (`ITAG_SIZE_ENC * (ldq1 + 1)) - 1]), + .din(ldqe_itag_d[ldq1]), + .dout(ldqe_itag_q[ldq1]) + ); + end + end +endgenerate + +generate begin : ldqe_thrd_id + genvar ldq2; + for (ldq2=0; ldq2<`LMQ_ENTRIES; ldq2=ldq2+1) begin : ldqe_thrd_id + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ldqe_thrd_id_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_ldqe_act[ldq2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldqe_thrd_id_offset + (`THREADS * ldq2):ldqe_thrd_id_offset + (`THREADS * (ldq2 + 1)) - 1]), + .scout(sov[ldqe_thrd_id_offset + (`THREADS * ldq2):ldqe_thrd_id_offset + (`THREADS * (ldq2 + 1)) - 1]), + .din(ldqe_thrd_id_d[ldq2]), + .dout(ldqe_thrd_id_q[ldq2]) + ); + end + end +endgenerate + +generate begin : ldqe_wimge + genvar ldq3; + for (ldq3=0; ldq3<`LMQ_ENTRIES; ldq3=ldq3+1) begin : ldqe_wimge + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) ldqe_wimge_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_ldqe_act[ldq3]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldqe_wimge_offset + (5 * ldq3):ldqe_wimge_offset + (5 * (ldq3 + 1)) - 1]), + .scout(sov[ldqe_wimge_offset + (5 * ldq3):ldqe_wimge_offset + (5 * (ldq3 + 1)) - 1]), + .din(ldqe_wimge_d[ldq3]), + .dout(ldqe_wimge_q[ldq3]) + ); + end + end +endgenerate + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_byte_swap_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldqe_byte_swap_offset:ldqe_byte_swap_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldqe_byte_swap_offset:ldqe_byte_swap_offset + `LMQ_ENTRIES - 1]), + .din(ldqe_byte_swap_d), + .dout(ldqe_byte_swap_q) +); + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_resv_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldqe_resv_offset:ldqe_resv_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldqe_resv_offset:ldqe_resv_offset + `LMQ_ENTRIES - 1]), + .din(ldqe_resv_d), + .dout(ldqe_resv_q) +); + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_pfetch_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldqe_pfetch_offset:ldqe_pfetch_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldqe_pfetch_offset:ldqe_pfetch_offset + `LMQ_ENTRIES - 1]), + .din(ldqe_pfetch_d), + .dout(ldqe_pfetch_q) +); + +generate begin : ldqe_op_size + genvar ldq4; + for (ldq4=0; ldq4<`LMQ_ENTRIES; ldq4=ldq4+1) begin : ldqe_op_size + tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ldqe_op_size_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_ldqe_act[ldq4]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldqe_op_size_offset + (3 * ldq4):ldqe_op_size_offset + (3 * (ldq4 + 1)) - 1]), + .scout(sov[ldqe_op_size_offset + (3 * ldq4):ldqe_op_size_offset + (3 * (ldq4 + 1)) - 1]), + .din(ldqe_op_size_d[ldq4]), + .dout(ldqe_op_size_q[ldq4]) + ); + end + end +endgenerate + +generate begin : ldqe_tgpr + genvar ldq5; + for (ldq5=0; ldq5<`LMQ_ENTRIES; ldq5=ldq5+1) begin : ldqe_tgpr + tri_rlmreg_p #(.WIDTH(AXU_TARGET_ENC), .INIT(0), .NEEDS_SRESET(1)) ldqe_tgpr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_ldqe_act[ldq5]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldqe_tgpr_offset + (AXU_TARGET_ENC * ldq5):ldqe_tgpr_offset + (AXU_TARGET_ENC * (ldq5 + 1)) - 1]), + .scout(sov[ldqe_tgpr_offset + (AXU_TARGET_ENC * ldq5):ldqe_tgpr_offset + (AXU_TARGET_ENC * (ldq5 + 1)) - 1]), + .din(ldqe_tgpr_d[ldq5]), + .dout(ldqe_tgpr_q[ldq5]) + ); + end + end +endgenerate + +generate begin : ldqe_usr_def + genvar ldq6; + for (ldq6=0; ldq6<`LMQ_ENTRIES; ldq6=ldq6+1) begin : ldqe_usr_def + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ldqe_usr_def_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_ldqe_act[ldq6]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldqe_usr_def_offset + (4 * ldq6):ldqe_usr_def_offset + (4 * (ldq6 + 1)) - 1]), + .scout(sov[ldqe_usr_def_offset + (4 * ldq6):ldqe_usr_def_offset + (4 * (ldq6 + 1)) - 1]), + .din(ldqe_usr_def_d[ldq6]), + .dout(ldqe_usr_def_q[ldq6]) + ); + end + end +endgenerate + +generate begin : ldqe_class_id + genvar ldq7; + for (ldq7=0; ldq7<`LMQ_ENTRIES; ldq7=ldq7+1) begin : ldqe_class_id + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ldqe_class_id_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_ldqe_act[ldq7]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldqe_class_id_offset + (2 * ldq7):ldqe_class_id_offset + (2 * (ldq7 + 1)) - 1]), + .scout(sov[ldqe_class_id_offset + (2 * ldq7):ldqe_class_id_offset + (2 * (ldq7 + 1)) - 1]), + .din(ldqe_class_id_d[ldq7]), + .dout(ldqe_class_id_q[ldq7]) + ); + end + end +endgenerate + +generate begin : ldqe_perf_events + genvar ldq7; + for (ldq7=0; ldq7<`LMQ_ENTRIES; ldq7=ldq7+1) begin : ldqe_perf_events + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ldqe_perf_events_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_ldqe_act[ldq7]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldqe_perf_events_offset + (4 * ldq7):ldqe_perf_events_offset + (4 * (ldq7 + 1)) - 1]), + .scout(sov[ldqe_perf_events_offset + (4 * ldq7):ldqe_perf_events_offset + (4 * (ldq7 + 1)) - 1]), + .din(ldqe_perf_events_d[ldq7]), + .dout(ldqe_perf_events_q[ldq7]) + ); + end + end +endgenerate + +generate begin : ldqe_dvc + genvar ldq8; + for (ldq8=0; ldq8<`LMQ_ENTRIES; ldq8=ldq8+1) begin : ldqe_dvc + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ldqe_dvc_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ldqe_ctrl_act[ldq8]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldqe_dvc_offset + (2 * ldq8):ldqe_dvc_offset + (2 * (ldq8 + 1)) - 1]), + .scout(sov[ldqe_dvc_offset + (2 * ldq8):ldqe_dvc_offset + (2 * (ldq8 + 1)) - 1]), + .din(ldqe_dvc_d[ldq8]), + .dout(ldqe_dvc_q[ldq8]) + ); + end + end +endgenerate + +generate begin : ldqe_ttype + genvar ldq9; + for (ldq9=0; ldq9<`LMQ_ENTRIES; ldq9=ldq9+1) begin : ldqe_ttype + tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) ldqe_ttype_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_ldqe_act[ldq9]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldqe_ttype_offset + (6 * ldq9):ldqe_ttype_offset + (6 * (ldq9 + 1)) - 1]), + .scout(sov[ldqe_ttype_offset + (6 * ldq9):ldqe_ttype_offset + (6 * (ldq9 + 1)) - 1]), + .din(ldqe_ttype_d[ldq9]), + .dout(ldqe_ttype_q[ldq9]) + ); + end + end +endgenerate + +generate begin : ldqe_dacrw + genvar ldq10; + for (ldq10=0; ldq10<`LMQ_ENTRIES; ldq10=ldq10+1) begin : ldqe_dacrw + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ldqe_dacrw_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_ldqe_act[ldq10]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldqe_dacrw_offset + (4 * ldq10):ldqe_dacrw_offset + (4 * (ldq10 + 1)) - 1]), + .scout(sov[ldqe_dacrw_offset + (4 * ldq10):ldqe_dacrw_offset + (4 * (ldq10 + 1)) - 1]), + .din(ldqe_dacrw_d[ldq10]), + .dout(ldqe_dacrw_q[ldq10]) + ); + end + end +endgenerate + +generate begin : ldqe_p_addr + genvar ldq11; + for (ldq11=0; ldq11<`LMQ_ENTRIES; ldq11=ldq11+1) begin : ldqe_p_addr + tri_rlmreg_p #(.WIDTH(`REAL_IFAR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ldqe_p_addr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_ldqe_act[ldq11]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldqe_p_addr_offset + (`REAL_IFAR_WIDTH * ldq11):ldqe_p_addr_offset + (`REAL_IFAR_WIDTH * (ldq11 + 1)) - 1]), + .scout(sov[ldqe_p_addr_offset + (`REAL_IFAR_WIDTH * ldq11):ldqe_p_addr_offset + (`REAL_IFAR_WIDTH * (ldq11 + 1)) - 1]), + .din(ldqe_p_addr_d[ldq11]), + .dout(ldqe_p_addr_q[ldq11]) + ); + end + end +endgenerate + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_mkill_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldqe_mkill_offset:ldqe_mkill_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldqe_mkill_offset:ldqe_mkill_offset + `LMQ_ENTRIES - 1]), + .din(ldqe_mkill_d), + .dout(ldqe_mkill_q) +); + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_resolved_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldqe_resolved_offset:ldqe_resolved_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldqe_resolved_offset:ldqe_resolved_offset + `LMQ_ENTRIES - 1]), + .din(ldqe_resolved_d), + .dout(ldqe_resolved_q) +); + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_back_inv_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldqe_back_inv_offset:ldqe_back_inv_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldqe_back_inv_offset:ldqe_back_inv_offset + `LMQ_ENTRIES - 1]), + .din(ldqe_back_inv_d), + .dout(ldqe_back_inv_q) +); + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_back_inv_nFlush_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldqe_back_inv_nFlush_offset:ldqe_back_inv_nFlush_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldqe_back_inv_nFlush_offset:ldqe_back_inv_nFlush_offset + `LMQ_ENTRIES - 1]), + .din(ldqe_back_inv_nFlush_d), + .dout(ldqe_back_inv_nFlush_q) +); + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_back_inv_np1Flush_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldqe_back_inv_np1Flush_offset:ldqe_back_inv_np1Flush_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldqe_back_inv_np1Flush_offset:ldqe_back_inv_np1Flush_offset + `LMQ_ENTRIES - 1]), + .din(ldqe_back_inv_np1Flush_d), + .dout(ldqe_back_inv_np1Flush_q) +); + +generate begin : ldqe_beat_cntr + genvar ldq12; + for (ldq12=0; ldq12<`LMQ_ENTRIES; ldq12=ldq12+1) begin : ldqe_beat_cntr + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ldqe_beat_cntr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ldqe_ctrl_act[ldq12]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldqe_beat_cntr_offset + (4 * ldq12):ldqe_beat_cntr_offset + (4 * (ldq12 + 1)) - 1]), + .scout(sov[ldqe_beat_cntr_offset + (4 * ldq12):ldqe_beat_cntr_offset + (4 * (ldq12 + 1)) - 1]), + .din(ldqe_beat_cntr_d[ldq12]), + .dout(ldqe_beat_cntr_q[ldq12]) + ); + end + end +endgenerate + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_dRel_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldqe_dRel_offset:ldqe_dRel_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldqe_dRel_offset:ldqe_dRel_offset + `LMQ_ENTRIES - 1]), + .din(ldqe_dRel_d), + .dout(ldqe_dRel_q) +); + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_l1_dump_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldqe_l1_dump_offset:ldqe_l1_dump_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldqe_l1_dump_offset:ldqe_l1_dump_offset + `LMQ_ENTRIES - 1]), + .din(ldqe_l1_dump_d), + .dout(ldqe_l1_dump_q) +); + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_dGpr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldqe_dGpr_offset:ldqe_dGpr_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldqe_dGpr_offset:ldqe_dGpr_offset + `LMQ_ENTRIES - 1]), + .din(ldqe_dGpr_d), + .dout(ldqe_dGpr_q) +); + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_axu_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldqe_axu_offset:ldqe_axu_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldqe_axu_offset:ldqe_axu_offset + `LMQ_ENTRIES - 1]), + .din(ldqe_axu_d), + .dout(ldqe_axu_q) +); + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_lock_set_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldqe_lock_set_offset:ldqe_lock_set_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldqe_lock_set_offset:ldqe_lock_set_offset + `LMQ_ENTRIES - 1]), + .din(ldqe_lock_set_d), + .dout(ldqe_lock_set_q) +); + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_watch_set_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldqe_watch_set_offset:ldqe_watch_set_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldqe_watch_set_offset:ldqe_watch_set_offset + `LMQ_ENTRIES - 1]), + .din(ldqe_watch_set_d), + .dout(ldqe_watch_set_q) +); + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_algebraic_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldqe_algebraic_offset:ldqe_algebraic_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldqe_algebraic_offset:ldqe_algebraic_offset + `LMQ_ENTRIES - 1]), + .din(ldqe_algebraic_d), + .dout(ldqe_algebraic_q) +); + +generate begin : ldqe_state + genvar ldq13; + for (ldq13=0; ldq13<`LMQ_ENTRIES; ldq13=ldq13+1) begin : ldqe_state + tri_rlmreg_p #(.WIDTH(7), .INIT(64), .NEEDS_SRESET(1)) ldqe_state_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldqe_state_offset + (7 * ldq13):ldqe_state_offset + (7 * (ldq13 + 1)) - 1]), + .scout(sov[ldqe_state_offset + (7 * ldq13):ldqe_state_offset + (7 * (ldq13 + 1)) - 1]), + .din(ldqe_state_d[ldq13]), + .dout(ldqe_state_q[ldq13]) + ); + end + end +endgenerate + +generate begin : ldqe_sentRel_cntr + genvar ldq; + for (ldq=0; ldq<`LMQ_ENTRIES; ldq=ldq+1) begin : ldqe_sentRel_cntr + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ldqe_sentRel_cntr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ldqe_ctrl_act[ldq]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldqe_sentRel_cntr_offset + (4 * ldq):ldqe_sentRel_cntr_offset + (4 * (ldq + 1)) - 1]), + .scout(sov[ldqe_sentRel_cntr_offset + (4 * ldq):ldqe_sentRel_cntr_offset + (4 * (ldq + 1)) - 1]), + .din(ldqe_sentRel_cntr_d[ldq]), + .dout(ldqe_sentRel_cntr_q[ldq]) + ); + end + end +endgenerate + +tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex5_lgqe_set_all_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_lgqe_set_all_offset:ex5_lgqe_set_all_offset + `LGQ_ENTRIES - 1]), + .scout(sov[ex5_lgqe_set_all_offset:ex5_lgqe_set_all_offset + `LGQ_ENTRIES - 1]), + .din(ex5_lgqe_set_all_d), + .dout(ex5_lgqe_set_all_q) +); + + +tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex5_lgqe_set_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_lgqe_set_val_offset:ex5_lgqe_set_val_offset + `LGQ_ENTRIES - 1]), + .scout(sov[ex5_lgqe_set_val_offset:ex5_lgqe_set_val_offset + `LGQ_ENTRIES - 1]), + .din(ex5_lgqe_set_val_d), + .dout(ex5_lgqe_set_val_q) +); + + +tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgqe_valid_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lgqe_valid_offset:lgqe_valid_offset + `LGQ_ENTRIES - 1]), + .scout(sov[lgqe_valid_offset:lgqe_valid_offset + `LGQ_ENTRIES - 1]), + .din(lgqe_valid_d), + .dout(lgqe_valid_q) +); + +generate begin : lgqe_iTag + genvar lgq; + for (lgq=0; lgq<`LGQ_ENTRIES; lgq=lgq+1) begin : lgqe_iTag + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) lgqe_iTag_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_lgqe_act[lgq]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lgqe_iTag_offset + (`ITAG_SIZE_ENC * lgq):lgqe_iTag_offset + (`ITAG_SIZE_ENC * (lgq + 1)) - 1]), + .scout(sov[lgqe_iTag_offset + (`ITAG_SIZE_ENC * lgq):lgqe_iTag_offset + (`ITAG_SIZE_ENC * (lgq + 1)) - 1]), + .din(lgqe_itag_d[lgq]), + .dout(lgqe_itag_q[lgq]) + ); + end + end +endgenerate + +generate begin : lgqe_ldTag + genvar lgq0; + for (lgq0=0; lgq0<`LGQ_ENTRIES; lgq0=lgq0+1) begin : lgqe_ldTag + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lgqe_ldTag_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_lgqe_act[lgq0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lgqe_ldTag_offset + (4 * lgq0):lgqe_ldTag_offset + (4 * (lgq0 + 1)) - 1]), + .scout(sov[lgqe_ldTag_offset + (4 * lgq0):lgqe_ldTag_offset + (4 * (lgq0 + 1)) - 1]), + .din(lgqe_ldTag_d[lgq0]), + .dout(lgqe_ldTag_q[lgq0]) + ); + end + end +endgenerate + +generate begin : lgqe_thrd_id + genvar lgq1; + for (lgq1=0; lgq1<`LGQ_ENTRIES; lgq1=lgq1+1) begin : lgqe_thrd_id + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) lgqe_thrd_id_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_lgqe_act[lgq1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lgqe_thrd_id_offset + (`THREADS * lgq1):lgqe_thrd_id_offset + (`THREADS * (lgq1 + 1)) - 1]), + .scout(sov[lgqe_thrd_id_offset + (`THREADS * lgq1):lgqe_thrd_id_offset + (`THREADS * (lgq1 + 1)) - 1]), + .din(lgqe_thrd_id_d[lgq1]), + .dout(lgqe_thrd_id_q[lgq1]) + ); + end + end +endgenerate + + +tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgqe_byte_swap_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lgqe_byte_swap_offset:lgqe_byte_swap_offset + `LGQ_ENTRIES - 1]), + .scout(sov[lgqe_byte_swap_offset:lgqe_byte_swap_offset + `LGQ_ENTRIES - 1]), + .din(lgqe_byte_swap_d), + .dout(lgqe_byte_swap_q) +); + +generate begin : lgqe_op_size + genvar lgq2; + for (lgq2=0; lgq2<`LGQ_ENTRIES; lgq2=lgq2+1) begin : lgqe_op_size + tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) lgqe_op_size_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_lgqe_act[lgq2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lgqe_op_size_offset + (3 * lgq2):lgqe_op_size_offset + (3 * (lgq2 + 1)) - 1]), + .scout(sov[lgqe_op_size_offset + (3 * lgq2):lgqe_op_size_offset + (3 * (lgq2 + 1)) - 1]), + .din(lgqe_op_size_d[lgq2]), + .dout(lgqe_op_size_q[lgq2]) + ); + end + end +endgenerate + +generate begin : lgqe_tgpr + genvar lgq3; + for (lgq3=0; lgq3<`LGQ_ENTRIES; lgq3=lgq3+1) begin : lgqe_tgpr + tri_rlmreg_p #(.WIDTH(AXU_TARGET_ENC), .INIT(0), .NEEDS_SRESET(1)) lgqe_tgpr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_lgqe_act[lgq3]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lgqe_tgpr_offset + (AXU_TARGET_ENC * lgq3):lgqe_tgpr_offset + (AXU_TARGET_ENC * (lgq3 + 1)) - 1]), + .scout(sov[lgqe_tgpr_offset + (AXU_TARGET_ENC * lgq3):lgqe_tgpr_offset + (AXU_TARGET_ENC * (lgq3 + 1)) - 1]), + .din(lgqe_tgpr_d[lgq3]), + .dout(lgqe_tgpr_q[lgq3]) + ); + end + end +endgenerate + + +tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgqe_gpr_done_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lgqe_gpr_done_offset:lgqe_gpr_done_offset + `LGQ_ENTRIES - 1]), + .scout(sov[lgqe_gpr_done_offset:lgqe_gpr_done_offset + `LGQ_ENTRIES - 1]), + .din(lgqe_gpr_done_d), + .dout(lgqe_gpr_done_q) +); + + +tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgqe_resolved_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lgqe_resolved_offset:lgqe_resolved_offset + `LGQ_ENTRIES - 1]), + .scout(sov[lgqe_resolved_offset:lgqe_resolved_offset + `LGQ_ENTRIES - 1]), + .din(lgqe_resolved_d), + .dout(lgqe_resolved_q) +); + + +tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgqe_back_inv_nFlush_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lgqe_back_inv_nFlush_offset:lgqe_back_inv_nFlush_offset + `LGQ_ENTRIES - 1]), + .scout(sov[lgqe_back_inv_nFlush_offset:lgqe_back_inv_nFlush_offset + `LGQ_ENTRIES - 1]), + .din(lgqe_back_inv_nFlush_d), + .dout(lgqe_back_inv_nFlush_q) +); + + +tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgqe_back_inv_np1Flush_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lgqe_back_inv_np1Flush_offset:lgqe_back_inv_np1Flush_offset + `LGQ_ENTRIES - 1]), + .scout(sov[lgqe_back_inv_np1Flush_offset:lgqe_back_inv_np1Flush_offset + `LGQ_ENTRIES - 1]), + .din(lgqe_back_inv_np1Flush_d), + .dout(lgqe_back_inv_np1Flush_q) +); + +generate begin : lgqe_dacrw + genvar lgq4; + for (lgq4=0; lgq4<`LGQ_ENTRIES; lgq4=lgq4+1) begin : lgqe_dacrw + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lgqe_dacrw_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_lgqe_act[lgq4]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lgqe_dacrw_offset + (4 * lgq4):lgqe_dacrw_offset + (4 * (lgq4 + 1)) - 1]), + .scout(sov[lgqe_dacrw_offset + (4 * lgq4):lgqe_dacrw_offset + (4 * (lgq4 + 1)) - 1]), + .din(lgqe_dacrw_d[lgq4]), + .dout(lgqe_dacrw_q[lgq4]) + ); + end + end +endgenerate + +generate begin : lgqe_dvc + genvar lgq5; + for (lgq5=0; lgq5<`LGQ_ENTRIES; lgq5=lgq5+1) begin : lgqe_dvc + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) lgqe_dvc_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lgqe_dvc_offset + (2 * lgq5):lgqe_dvc_offset + (2 * (lgq5 + 1)) - 1]), + .scout(sov[lgqe_dvc_offset + (2 * lgq5):lgqe_dvc_offset + (2 * (lgq5 + 1)) - 1]), + .din(lgqe_dvc_d[lgq5]), + .dout(lgqe_dvc_q[lgq5]) + ); + end + end +endgenerate + +generate begin : lgqe_p_addr + genvar lgq6; + for (lgq6=0; lgq6<`LGQ_ENTRIES; lgq6=lgq6+1) begin : lgqe_p_addr + tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(1)) lgqe_p_addr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_lgqe_act[lgq6]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lgqe_p_addr_offset + (7 * lgq6):lgqe_p_addr_offset + (7 * (lgq6 + 1)) - 1]), + .scout(sov[lgqe_p_addr_offset + (7 * lgq6):lgqe_p_addr_offset + (7 * (lgq6 + 1)) - 1]), + .din(lgqe_p_addr_d[lgq6]), + .dout(lgqe_p_addr_q[lgq6]) + ); + end + end +endgenerate + + +tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgqe_algebraic_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lgqe_algebraic_offset:lgqe_algebraic_offset + `LGQ_ENTRIES - 1]), + .scout(sov[lgqe_algebraic_offset:lgqe_algebraic_offset + `LGQ_ENTRIES - 1]), + .din(lgqe_algebraic_d), + .dout(lgqe_algebraic_q) +); + + +tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgqe_axu_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex5_stg_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lgqe_axu_offset:lgqe_axu_offset + `LGQ_ENTRIES - 1]), + .scout(sov[lgqe_axu_offset:lgqe_axu_offset + `LGQ_ENTRIES - 1]), + .din(lgqe_axu_d), + .dout(lgqe_axu_q) +); + +generate begin : lgqe_perf_events + genvar lgq6; + for (lgq6=0; lgq6<`LGQ_ENTRIES; lgq6=lgq6+1) begin : lgqe_perf_events + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lgqe_perf_events_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex4_lgqe_act[lgq6]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lgqe_perf_events_offset + (4 * lgq6):lgqe_perf_events_offset + (4 * (lgq6 + 1)) - 1]), + .scout(sov[lgqe_perf_events_offset + (4 * lgq6):lgqe_perf_events_offset + (4 * (lgq6 + 1)) - 1]), + .din(lgqe_perf_events_d[lgq6]), + .dout(lgqe_perf_events_q[lgq6]) + ); + end + end +endgenerate + + +tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgqe_upd_gpr_ecc_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lgqe_upd_gpr_ecc_offset:lgqe_upd_gpr_ecc_offset + `LGQ_ENTRIES - 1]), + .scout(sov[lgqe_upd_gpr_ecc_offset:lgqe_upd_gpr_ecc_offset + `LGQ_ENTRIES - 1]), + .din(lgqe_upd_gpr_ecc_d), + .dout(lgqe_upd_gpr_ecc_q) +); + +tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgqe_upd_gpr_eccue_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lgqe_upd_gpr_eccue_offset:lgqe_upd_gpr_eccue_offset + `LGQ_ENTRIES - 1]), + .scout(sov[lgqe_upd_gpr_eccue_offset:lgqe_upd_gpr_eccue_offset + `LGQ_ENTRIES - 1]), + .din(lgqe_upd_gpr_eccue_d), + .dout(lgqe_upd_gpr_eccue_q) +); + +tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgqe_need_cpl_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lgqe_need_cpl_offset:lgqe_need_cpl_offset + `LGQ_ENTRIES - 1]), + .scout(sov[lgqe_need_cpl_offset:lgqe_need_cpl_offset + `LGQ_ENTRIES - 1]), + .din(lgqe_need_cpl_d), + .dout(lgqe_need_cpl_q) +); + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_rst_eccdet_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldqe_rst_eccdet_offset:ldqe_rst_eccdet_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldqe_rst_eccdet_offset:ldqe_rst_eccdet_offset + `LMQ_ENTRIES - 1]), + .din(ldqe_rst_eccdet_d), + .dout(ldqe_rst_eccdet_q) +); + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel2_beats_home_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel2_beats_home_offset:ldq_rel2_beats_home_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldq_rel2_beats_home_offset:ldq_rel2_beats_home_offset + `LMQ_ENTRIES - 1]), + .din(ldq_rel2_beats_home_d), + .dout(ldq_rel2_beats_home_q) +); + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel3_beats_home_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel3_beats_home_offset:ldq_rel3_beats_home_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldq_rel3_beats_home_offset:ldq_rel3_beats_home_offset + `LMQ_ENTRIES - 1]), + .din(ldq_rel3_beats_home_d), + .dout(ldq_rel3_beats_home_q) +); + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel4_beats_home_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel4_beats_home_offset:ldq_rel4_beats_home_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldq_rel4_beats_home_offset:ldq_rel4_beats_home_offset + `LMQ_ENTRIES - 1]), + .din(ldq_rel4_beats_home_d), + .dout(ldq_rel4_beats_home_q) +); + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel5_beats_home_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel5_beats_home_offset:ldq_rel5_beats_home_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldq_rel5_beats_home_offset:ldq_rel5_beats_home_offset + `LMQ_ENTRIES - 1]), + .din(ldq_rel5_beats_home_d), + .dout(ldq_rel5_beats_home_q) +); + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_entrySent_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel1_entrySent_offset:ldq_rel1_entrySent_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldq_rel1_entrySent_offset:ldq_rel1_entrySent_offset + `LMQ_ENTRIES - 1]), + .din(ldq_rel1_entrySent_d), + .dout(ldq_rel1_entrySent_q) +); + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel2_entrySent_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel2_entrySent_offset:ldq_rel2_entrySent_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldq_rel2_entrySent_offset:ldq_rel2_entrySent_offset + `LMQ_ENTRIES - 1]), + .din(ldq_rel2_entrySent_d), + .dout(ldq_rel2_entrySent_q) +); + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel3_entrySent_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel3_entrySent_offset:ldq_rel3_entrySent_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldq_rel3_entrySent_offset:ldq_rel3_entrySent_offset + `LMQ_ENTRIES - 1]), + .din(ldq_rel3_entrySent_d), + .dout(ldq_rel3_entrySent_q) +); + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel4_sentL1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel4_sentL1_offset:ldq_rel4_sentL1_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldq_rel4_sentL1_offset:ldq_rel4_sentL1_offset + `LMQ_ENTRIES - 1]), + .din(ldq_rel4_sentL1_d), + .dout(ldq_rel4_sentL1_q) +); + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel5_sentL1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel5_sentL1_offset:ldq_rel5_sentL1_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldq_rel5_sentL1_offset:ldq_rel5_sentL1_offset + `LMQ_ENTRIES - 1]), + .din(ldq_rel5_sentL1_d), + .dout(ldq_rel5_sentL1_q) +); + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel6_req_done_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel6_req_done_offset:ldq_rel6_req_done_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldq_rel6_req_done_offset:ldq_rel6_req_done_offset + `LMQ_ENTRIES - 1]), + .din(ldq_rel6_req_done_d), + .dout(ldq_rel6_req_done_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) l2_rel1_resp_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[l2_rel1_resp_val_offset]), + .scout(sov[l2_rel1_resp_val_offset]), + .din(l2_rel1_resp_val_d), + .dout(l2_rel1_resp_val_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) l2_rel2_resp_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[l2_rel2_resp_val_offset]), + .scout(sov[l2_rel2_resp_val_offset]), + .din(l2_rel2_resp_val_d), + .dout(l2_rel2_resp_val_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_err_inval_rel_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_err_inval_rel_offset]), + .scout(sov[ldq_err_inval_rel_offset]), + .din(ldq_err_inval_rel_d), + .dout(ldq_err_inval_rel_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_err_ecc_det_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_err_ecc_det_offset]), + .scout(sov[ldq_err_ecc_det_offset]), + .din(ldq_err_ecc_det_d), + .dout(ldq_err_ecc_det_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_err_ue_det_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_err_ue_det_offset]), + .scout(sov[ldq_err_ue_det_offset]), + .din(ldq_err_ue_det_d), + .dout(ldq_err_ue_det_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel1_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel1_val_offset]), + .scout(sov[ldq_rel1_val_offset]), + .din(ldq_rel1_val_d), + .dout(ldq_rel1_val_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel1_arb_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel1_arb_val_offset]), + .scout(sov[ldq_rel1_arb_val_offset]), + .din(ldq_rel1_arb_val_d), + .dout(ldq_rel1_arb_val_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel1_l1_dump_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel1_l1_dump_offset]), + .scout(sov[ldq_rel1_l1_dump_offset]), + .din(ldq_rel1_l1_dump_d), + .dout(ldq_rel1_l1_dump_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel2_l1_dump_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel2_l1_dump_offset]), + .scout(sov[ldq_rel2_l1_dump_offset]), + .din(ldq_rel2_l1_dump_d), + .dout(ldq_rel2_l1_dump_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel3_l1_dump_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel3_l1_dump_offset]), + .scout(sov[ldq_rel3_l1_dump_offset]), + .din(ldq_rel3_l1_dump_d), + .dout(ldq_rel3_l1_dump_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel3_clr_relq_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel3_clr_relq_offset]), + .scout(sov[ldq_rel3_clr_relq_offset]), + .din(ldq_rel3_clr_relq_d), + .dout(ldq_rel3_clr_relq_q) +); + + +tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_resp_qw_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rel0_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel1_resp_qw_offset:ldq_rel1_resp_qw_offset + 3 - 1]), + .scout(sov[ldq_rel1_resp_qw_offset:ldq_rel1_resp_qw_offset + 3 - 1]), + .din(ldq_rel1_resp_qw_d), + .dout(ldq_rel1_resp_qw_q) +); + +tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_cTag_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rel0_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel1_cTag_offset:ldq_rel1_cTag_offset + 4 - 1]), + .scout(sov[ldq_rel1_cTag_offset:ldq_rel1_cTag_offset + 4 - 1]), + .din(ldq_rel1_cTag_d), + .dout(ldq_rel1_cTag_q) +); + + +tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_opsize_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rel0_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel1_opsize_offset:ldq_rel1_opsize_offset + 3 - 1]), + .scout(sov[ldq_rel1_opsize_offset:ldq_rel1_opsize_offset + 3 - 1]), + .din(ldq_rel1_opsize_d), + .dout(ldq_rel1_opsize_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel1_wimge_i_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rel0_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel1_wimge_i_offset]), + .scout(sov[ldq_rel1_wimge_i_offset]), + .din(ldq_rel1_wimge_i_d), + .dout(ldq_rel1_wimge_i_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel1_byte_swap_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rel0_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel1_byte_swap_offset]), + .scout(sov[ldq_rel1_byte_swap_offset]), + .din(ldq_rel1_byte_swap_d), + .dout(ldq_rel1_byte_swap_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel2_byte_swap_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rel0_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel2_byte_swap_offset]), + .scout(sov[ldq_rel2_byte_swap_offset]), + .din(ldq_rel2_byte_swap_d), + .dout(ldq_rel2_byte_swap_q) +); + + +tri_rlmreg_p #(.WIDTH(`REAL_IFAR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_p_addr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rel0_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel1_p_addr_offset:ldq_rel1_p_addr_offset + `REAL_IFAR_WIDTH - 1]), + .scout(sov[ldq_rel1_p_addr_offset:ldq_rel1_p_addr_offset + `REAL_IFAR_WIDTH - 1]), + .din(ldq_rel1_p_addr_d), + .dout(ldq_rel1_p_addr_q) +); + + +tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_dvcEn_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rel0_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel1_dvcEn_offset:ldq_rel1_dvcEn_offset + 2 - 1]), + .scout(sov[ldq_rel1_dvcEn_offset:ldq_rel1_dvcEn_offset + 2 - 1]), + .din(ldq_rel1_dvcEn_d), + .dout(ldq_rel1_dvcEn_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel1_lockSet_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rel0_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel1_lockSet_offset]), + .scout(sov[ldq_rel1_lockSet_offset]), + .din(ldq_rel1_lockSet_d), + .dout(ldq_rel1_lockSet_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel1_watchSet_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rel0_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel1_watchSet_offset]), + .scout(sov[ldq_rel1_watchSet_offset]), + .din(ldq_rel1_watchSet_d), + .dout(ldq_rel1_watchSet_q) +); + + +tri_rlmreg_p #(.WIDTH(AXU_TARGET_ENC), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_tGpr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rel0_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel1_tGpr_offset:ldq_rel1_tGpr_offset + AXU_TARGET_ENC - 1]), + .scout(sov[ldq_rel1_tGpr_offset:ldq_rel1_tGpr_offset + AXU_TARGET_ENC - 1]), + .din(ldq_rel1_tGpr_d), + .dout(ldq_rel1_tGpr_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel1_axu_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rel0_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel1_axu_offset]), + .scout(sov[ldq_rel1_axu_offset]), + .din(ldq_rel1_axu_d), + .dout(ldq_rel1_axu_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel1_algEn_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rel0_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel1_algEn_offset]), + .scout(sov[ldq_rel1_algEn_offset]), + .din(ldq_rel1_algEn_d), + .dout(ldq_rel1_algEn_q) +); + + +tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_classID_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rel0_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel1_classID_offset:ldq_rel1_classID_offset + 2 - 1]), + .scout(sov[ldq_rel1_classID_offset:ldq_rel1_classID_offset + 2 - 1]), + .din(ldq_rel1_classID_d), + .dout(ldq_rel1_classID_q) +); + + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_tid_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rel0_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel1_tid_offset:ldq_rel1_tid_offset + `THREADS - 1]), + .scout(sov[ldq_rel1_tid_offset:ldq_rel1_tid_offset + `THREADS - 1]), + .din(ldq_rel1_tid_d), + .dout(ldq_rel1_tid_q) +); + + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ldq_rel2_tid_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ldq_rel1_val_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel2_tid_offset:ldq_rel2_tid_offset + `THREADS - 1]), + .scout(sov[ldq_rel2_tid_offset:ldq_rel2_tid_offset + `THREADS - 1]), + .din(ldq_rel2_tid_d), + .dout(ldq_rel2_tid_q) +); + + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_dir_tid_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rel0_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel1_dir_tid_offset:ldq_rel1_dir_tid_offset + `THREADS - 1]), + .scout(sov[ldq_rel1_dir_tid_offset:ldq_rel1_dir_tid_offset + `THREADS - 1]), + .din(ldq_rel1_dir_tid_d), + .dout(ldq_rel1_dir_tid_q) +); + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_relDir_start_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldqe_relDir_start_offset:ldqe_relDir_start_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldqe_relDir_start_offset:ldqe_relDir_start_offset + `LMQ_ENTRIES - 1]), + .din(ldqe_relDir_start_d), + .dout(ldqe_relDir_start_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel2_set_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel2_set_val_offset]), + .scout(sov[ldq_rel2_set_val_offset]), + .din(ldq_rel2_set_val_d), + .dout(ldq_rel2_set_val_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel3_set_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel3_set_val_offset]), + .scout(sov[ldq_rel3_set_val_offset]), + .din(ldq_rel3_set_val_d), + .dout(ldq_rel3_set_val_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel4_set_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel4_set_val_offset]), + .scout(sov[ldq_rel4_set_val_offset]), + .din(ldq_rel4_set_val_d), + .dout(ldq_rel4_set_val_q) +); + + +tri_rlmreg_p #(.WIDTH((57-(64-(`DC_SIZE-3))+1)), .INIT(0), .NEEDS_SRESET(1)) ldq_rel2_cclass_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ldq_rel1_val_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel2_cclass_offset:ldq_rel2_cclass_offset + (57-(64-(`DC_SIZE-3))+1) - 1]), + .scout(sov[ldq_rel2_cclass_offset:ldq_rel2_cclass_offset + (57-(64-(`DC_SIZE-3))+1) - 1]), + .din(ldq_rel2_cclass_d), + .dout(ldq_rel2_cclass_q) +); + + +tri_rlmreg_p #(.WIDTH((57-(64-(`DC_SIZE-3))+1)), .INIT(0), .NEEDS_SRESET(1)) ldq_rel3_cclass_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel3_cclass_offset:ldq_rel3_cclass_offset + (57-(64-(`DC_SIZE-3))+1) - 1]), + .scout(sov[ldq_rel3_cclass_offset:ldq_rel3_cclass_offset + (57-(64-(`DC_SIZE-3))+1) - 1]), + .din(ldq_rel3_cclass_d), + .dout(ldq_rel3_cclass_q) +); + + +tri_rlmreg_p #(.WIDTH((57-(64-(`DC_SIZE-3))+1)), .INIT(0), .NEEDS_SRESET(1)) ldq_rel4_cclass_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel4_cclass_offset:ldq_rel4_cclass_offset + (57-(64-(`DC_SIZE-3))+1) - 1]), + .scout(sov[ldq_rel4_cclass_offset:ldq_rel4_cclass_offset + (57-(64-(`DC_SIZE-3))+1) - 1]), + .din(ldq_rel4_cclass_d), + .dout(ldq_rel4_cclass_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel1_data_sel_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel1_data_sel_offset]), + .scout(sov[ldq_rel1_data_sel_offset]), + .din(ldq_rel1_data_sel_d), + .dout(ldq_rel1_data_sel_q) +); + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel0_l2_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel0_l2_val_offset:ldq_rel0_l2_val_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldq_rel0_l2_val_offset:ldq_rel0_l2_val_offset + `LMQ_ENTRIES - 1]), + .din(ldq_rel0_l2_val_d), + .dout(ldq_rel0_l2_val_q) +); + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_l2_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel1_l2_val_offset:ldq_rel1_l2_val_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldq_rel1_l2_val_offset:ldq_rel1_l2_val_offset + `LMQ_ENTRIES - 1]), + .din(ldq_rel1_l2_val_d), + .dout(ldq_rel1_l2_val_q) +); + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel2_l2_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel2_l2_val_offset:ldq_rel2_l2_val_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldq_rel2_l2_val_offset:ldq_rel2_l2_val_offset + `LMQ_ENTRIES - 1]), + .din(ldq_rel2_l2_val_d), + .dout(ldq_rel2_l2_val_q) +); + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel3_l2_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel3_l2_val_offset:ldq_rel3_l2_val_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldq_rel3_l2_val_offset:ldq_rel3_l2_val_offset + `LMQ_ENTRIES - 1]), + .din(ldq_rel3_l2_val_d), + .dout(ldq_rel3_l2_val_q) +); + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel4_l2_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel4_l2_val_offset:ldq_rel4_l2_val_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldq_rel4_l2_val_offset:ldq_rel4_l2_val_offset + `LMQ_ENTRIES - 1]), + .din(ldq_rel4_l2_val_d), + .dout(ldq_rel4_l2_val_q) +); + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel5_l2_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel5_l2_val_offset:ldq_rel5_l2_val_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldq_rel5_l2_val_offset:ldq_rel5_l2_val_offset + `LMQ_ENTRIES - 1]), + .din(ldq_rel5_l2_val_d), + .dout(ldq_rel5_l2_val_q) +); + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_rel_eccdet_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldqe_rel_eccdet_offset:ldqe_rel_eccdet_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldqe_rel_eccdet_offset:ldqe_rel_eccdet_offset + `LMQ_ENTRIES - 1]), + .din(ldqe_rel_eccdet_d), + .dout(ldqe_rel_eccdet_q) +); + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_rel_eccdet_ue_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldqe_rel_eccdet_ue_offset:ldqe_rel_eccdet_ue_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldqe_rel_eccdet_ue_offset:ldqe_rel_eccdet_ue_offset + `LMQ_ENTRIES - 1]), + .din(ldqe_rel_eccdet_ue_d), + .dout(ldqe_rel_eccdet_ue_q) +); + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_upd_gpr_ecc_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldqe_upd_gpr_ecc_offset:ldqe_upd_gpr_ecc_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldqe_upd_gpr_ecc_offset:ldqe_upd_gpr_ecc_offset + `LMQ_ENTRIES - 1]), + .din(ldqe_upd_gpr_ecc_d), + .dout(ldqe_upd_gpr_ecc_q) +); + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_upd_gpr_eccue_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldqe_upd_gpr_eccue_offset:ldqe_upd_gpr_eccue_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldqe_upd_gpr_eccue_offset:ldqe_upd_gpr_eccue_offset + `LMQ_ENTRIES - 1]), + .din(ldqe_upd_gpr_eccue_d), + .dout(ldqe_upd_gpr_eccue_q) +); + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_need_cpl_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldqe_need_cpl_offset:ldqe_need_cpl_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldqe_need_cpl_offset:ldqe_need_cpl_offset + `LMQ_ENTRIES - 1]), + .din(ldqe_need_cpl_d), + .dout(ldqe_need_cpl_q) +); + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_sent_cpl_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldqe_sent_cpl_offset:ldqe_sent_cpl_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldqe_sent_cpl_offset:ldqe_sent_cpl_offset + `LMQ_ENTRIES - 1]), + .din(ldqe_sent_cpl_d), + .dout(ldqe_sent_cpl_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel1_gpr_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel1_gpr_val_offset]), + .scout(sov[ldq_rel1_gpr_val_offset]), + .din(ldq_rel1_gpr_val_d), + .dout(ldq_rel1_gpr_val_q) +); + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel0_upd_gpr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel0_upd_gpr_offset:ldq_rel0_upd_gpr_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldq_rel0_upd_gpr_offset:ldq_rel0_upd_gpr_offset + `LMQ_ENTRIES - 1]), + .din(ldq_rel0_upd_gpr_d), + .dout(ldq_rel0_upd_gpr_q) +); + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_upd_gpr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel1_upd_gpr_offset:ldq_rel1_upd_gpr_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldq_rel1_upd_gpr_offset:ldq_rel1_upd_gpr_offset + `LMQ_ENTRIES - 1]), + .din(ldq_rel1_upd_gpr_d), + .dout(ldq_rel1_upd_gpr_q) +); + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel2_upd_gpr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel2_upd_gpr_offset:ldq_rel2_upd_gpr_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldq_rel2_upd_gpr_offset:ldq_rel2_upd_gpr_offset + `LMQ_ENTRIES - 1]), + .din(ldq_rel2_upd_gpr_d), + .dout(ldq_rel2_upd_gpr_q) +); + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel3_upd_gpr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel3_upd_gpr_offset:ldq_rel3_upd_gpr_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldq_rel3_upd_gpr_offset:ldq_rel3_upd_gpr_offset + `LMQ_ENTRIES - 1]), + .din(ldq_rel3_upd_gpr_d), + .dout(ldq_rel3_upd_gpr_q) +); + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_rel3_drop_cpl_rpt_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldqe_rel3_drop_cpl_rpt_offset:ldqe_rel3_drop_cpl_rpt_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldqe_rel3_drop_cpl_rpt_offset:ldqe_rel3_drop_cpl_rpt_offset + `LMQ_ENTRIES - 1]), + .din(ldqe_rel3_drop_cpl_rpt_d), + .dout(ldqe_rel3_drop_cpl_rpt_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_l2_rel0_qHitBlk_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_l2_rel0_qHitBlk_offset]), + .scout(sov[ldq_l2_rel0_qHitBlk_offset]), + .din(ldq_l2_rel0_qHitBlk_d), + .dout(ldq_l2_rel0_qHitBlk_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lgq_rel1_gpr_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lgq_rel1_gpr_val_offset]), + .scout(sov[lgq_rel1_gpr_val_offset]), + .din(lgq_rel1_gpr_val_d), + .dout(lgq_rel1_gpr_val_q) +); + + +tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgq_rel0_upd_gpr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lgq_rel0_upd_gpr_offset:lgq_rel0_upd_gpr_offset + `LGQ_ENTRIES - 1]), + .scout(sov[lgq_rel0_upd_gpr_offset:lgq_rel0_upd_gpr_offset + `LGQ_ENTRIES - 1]), + .din(lgq_rel0_upd_gpr_d), + .dout(lgq_rel0_upd_gpr_q) +); + + +tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgq_rel1_upd_gpr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lgq_rel1_upd_gpr_offset:lgq_rel1_upd_gpr_offset + `LGQ_ENTRIES - 1]), + .scout(sov[lgq_rel1_upd_gpr_offset:lgq_rel1_upd_gpr_offset + `LGQ_ENTRIES - 1]), + .din(lgq_rel1_upd_gpr_d), + .dout(lgq_rel1_upd_gpr_q) +); + + +tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgq_rel2_upd_gpr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lgq_rel2_upd_gpr_offset:lgq_rel2_upd_gpr_offset + `LGQ_ENTRIES - 1]), + .scout(sov[lgq_rel2_upd_gpr_offset:lgq_rel2_upd_gpr_offset + `LGQ_ENTRIES - 1]), + .din(lgq_rel2_upd_gpr_d), + .dout(lgq_rel2_upd_gpr_q) +); + + +tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgq_rel3_upd_gpr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lgq_rel3_upd_gpr_offset:lgq_rel3_upd_gpr_offset + `LGQ_ENTRIES - 1]), + .scout(sov[lgq_rel3_upd_gpr_offset:lgq_rel3_upd_gpr_offset + `LGQ_ENTRIES - 1]), + .din(lgq_rel3_upd_gpr_d), + .dout(lgq_rel3_upd_gpr_q) +); + + +tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgq_rel4_upd_gpr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lgq_rel4_upd_gpr_offset:lgq_rel4_upd_gpr_offset + `LGQ_ENTRIES - 1]), + .scout(sov[lgq_rel4_upd_gpr_offset:lgq_rel4_upd_gpr_offset + `LGQ_ENTRIES - 1]), + .din(lgq_rel4_upd_gpr_d), + .dout(lgq_rel4_upd_gpr_q) +); + + +tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgq_rel5_upd_gpr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lgq_rel5_upd_gpr_offset:lgq_rel5_upd_gpr_offset + `LGQ_ENTRIES - 1]), + .scout(sov[lgq_rel5_upd_gpr_offset:lgq_rel5_upd_gpr_offset + `LGQ_ENTRIES - 1]), + .din(lgq_rel5_upd_gpr_d), + .dout(lgq_rel5_upd_gpr_q) +); + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel4_odq_cpl_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel4_odq_cpl_offset:ldq_rel4_odq_cpl_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldq_rel4_odq_cpl_offset:ldq_rel4_odq_cpl_offset + `LMQ_ENTRIES - 1]), + .din(ldq_rel4_odq_cpl_d), + .dout(ldq_rel4_odq_cpl_q) +); + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel5_odq_cpl_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel5_odq_cpl_offset:ldq_rel5_odq_cpl_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldq_rel5_odq_cpl_offset:ldq_rel5_odq_cpl_offset + `LMQ_ENTRIES - 1]), + .din(ldq_rel5_odq_cpl_d), + .dout(ldq_rel5_odq_cpl_q) +); + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel_qHit_clr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel_qHit_clr_offset:ldq_rel_qHit_clr_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldq_rel_qHit_clr_offset:ldq_rel_qHit_clr_offset + `LMQ_ENTRIES - 1]), + .din(ldq_rel_qHit_clr_d), + .dout(ldq_rel_qHit_clr_q) +); + + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_qHit_held_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldqe_qHit_held_offset:ldqe_qHit_held_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldqe_qHit_held_offset:ldqe_qHit_held_offset + `LMQ_ENTRIES - 1]), + .din(ldqe_qHit_held_d), + .dout(ldqe_qHit_held_q) +); + +generate begin : cpl_grpEntry_last_sel + genvar grp0; + for (grp0=0; grp0<=(`LMQ_ENTRIES+`LGQ_ENTRIES-1)/4; grp0=grp0+1) begin : cpl_grpEntry_last_sel + tri_rlmreg_p #(.WIDTH(4), .INIT(8), .NEEDS_SRESET(1)) cpl_grpEntry_last_sel_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[cpl_grpEntry_last_sel_offset + (4 * grp0):cpl_grpEntry_last_sel_offset + (4 * (grp0 + 1)) - 1]), + .scout(sov[cpl_grpEntry_last_sel_offset + (4 * grp0):cpl_grpEntry_last_sel_offset + (4 * (grp0 + 1)) - 1]), + .din(cpl_grpEntry_last_sel_d[grp0]), + .dout(cpl_grpEntry_last_sel_q[grp0]) + ); + end + end +endgenerate + + +tri_rlmreg_p #(.WIDTH(4), .INIT(8), .NEEDS_SRESET(1)) cpl_group_last_sel_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[cpl_group_last_sel_offset:cpl_group_last_sel_offset + 4 - 1]), + .scout(sov[cpl_group_last_sel_offset:cpl_group_last_sel_offset + 4 - 1]), + .din(cpl_group_last_sel_d), + .dout(cpl_group_last_sel_q) +); + + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) lq1_iu_execute_vld_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lq1_iu_execute_vld_offset:lq1_iu_execute_vld_offset + `THREADS - 1]), + .scout(sov[lq1_iu_execute_vld_offset:lq1_iu_execute_vld_offset + `THREADS - 1]), + .din(lq1_iu_execute_vld_d), + .dout(lq1_iu_execute_vld_q) +); + + +tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(1), .NEEDS_SRESET(1)) lq1_iu_itag_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lq1_iu_itag_offset:lq1_iu_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[lq1_iu_itag_offset:lq1_iu_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(lq1_iu_itag_d), + .dout(lq1_iu_itag_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq1_iu_n_flush_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lq1_iu_n_flush_offset]), + .scout(sov[lq1_iu_n_flush_offset]), + .din(lq1_iu_n_flush_d), + .dout(lq1_iu_n_flush_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq1_iu_np1_flush_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lq1_iu_np1_flush_offset]), + .scout(sov[lq1_iu_np1_flush_offset]), + .din(lq1_iu_np1_flush_d), + .dout(lq1_iu_np1_flush_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq1_iu_exception_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lq1_iu_exception_val_offset]), + .scout(sov[lq1_iu_exception_val_offset]), + .din(lq1_iu_exception_val_d), + .dout(lq1_iu_exception_val_q) +); + +tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lq1_iu_dacrw_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lq1_iu_dacrw_offset:lq1_iu_dacrw_offset + 4 - 1]), + .scout(sov[lq1_iu_dacrw_offset:lq1_iu_dacrw_offset + 4 - 1]), + .din(lq1_iu_dacrw_d), + .dout(lq1_iu_dacrw_q) +); + +tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lq1_iu_perf_events_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lq1_iu_perf_events_offset:lq1_iu_perf_events_offset + 4 - 1]), + .scout(sov[lq1_iu_perf_events_offset:lq1_iu_perf_events_offset + 4 - 1]), + .din(lq1_iu_perf_events_d), + .dout(lq1_iu_perf_events_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ldq_cpl_larx_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_cpl_larx_offset:ldq_cpl_larx_offset + `THREADS - 1]), + .scout(sov[ldq_cpl_larx_offset:ldq_cpl_larx_offset + `THREADS - 1]), + .din(ldq_cpl_larx_d), + .dout(ldq_cpl_larx_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ldq_cpl_binv_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_cpl_binv_offset:ldq_cpl_binv_offset + `THREADS - 1]), + .scout(sov[ldq_cpl_binv_offset:ldq_cpl_binv_offset + `THREADS - 1]), + .din(ldq_cpl_binv_d), + .dout(ldq_cpl_binv_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel_cmmt_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel_cmmt_offset]), + .scout(sov[ldq_rel_cmmt_offset]), + .din(ldq_rel_cmmt_d), + .dout(ldq_rel_cmmt_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel_need_hole_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel_need_hole_offset]), + .scout(sov[ldq_rel_need_hole_offset]), + .din(ldq_rel_need_hole_d), + .dout(ldq_rel_need_hole_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel_latency_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel_latency_offset]), + .scout(sov[ldq_rel_latency_offset]), + .din(ldq_rel_latency_d), + .dout(ldq_rel_latency_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) dbg_int_en_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[dbg_int_en_offset:dbg_int_en_offset + `THREADS - 1]), + .scout(sov[dbg_int_en_offset:dbg_int_en_offset + `THREADS - 1]), + .din(dbg_int_en_d), + .dout(dbg_int_en_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_stg_act_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_stg_act_offset]), + .scout(sov[ex4_stg_act_offset]), + .din(ex4_stg_act_d), + .dout(ex4_stg_act_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_stg_act_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_stg_act_offset]), + .scout(sov[ex5_stg_act_offset]), + .din(ex5_stg_act_d), + .dout(ex5_stg_act_q) +); + +assign rdat_scan_in = scan_in; +assign siv[0:scan_right] = {sov[1:scan_right], rdat_scan_out}; +assign scan_out = sov[0]; + +endmodule diff --git a/dev/verilog/work/lq_ldq_relq.v b/dev/verilog/work/lq_ldq_relq.v new file mode 100755 index 0000000..4693d47 --- /dev/null +++ b/dev/verilog/work/lq_ldq_relq.v @@ -0,0 +1,1158 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// +// Description: Reload Data Arbiter Control +// +//***************************************************************************** + +`include "tri_a2o.vh" + +module lq_ldq_relq( + ldq_rel0_stg_act, + ldq_rel1_stg_act, + ldqe_ctrl_act, + ldq_rel0_arb_sent, + ldq_rel0_beat_upd, + ldq_rel0_arr_wren, + ldq_rel0_rdat_qw, + ldq_rel1_cTag, + ldq_rel1_dbeat_val, + ldq_rel1_beats_home, + ldq_rel2_entrySent, + ldq_rel2_blk_req, + ldq_rel2_sentL1, + ldq_rel2_sentL1_blk, + ldqe_rel_eccdet, + ldqe_rst_eccdet, + ldq_rel0_rdat_sel, + arb_ldq_rel2_wrt_data, + ldq_rel0_arb_val, + ldq_rel0_arb_qw, + ldq_rel0_arb_cTag, + ldq_rel0_arb_thresh, + ldq_rel2_rdat_perr, + ldq_rel3_rdat_par_err, + ldqe_rel_rdat_perr, + ldq_arb_rel2_rdat_sel, + ldq_arb_rel2_rd_data, + pc_lq_inj_relq_parity, + spr_lsucr0_lca_ovrd, + bo_enable_2, + clkoff_dc_b, + g8t_clkoff_dc_b, + g8t_d_mode_dc, + g8t_delay_lclkr_dc, + g8t_mpw1_dc_b, + g8t_mpw2_dc_b, + pc_lq_ccflush_dc, + an_ac_scan_dis_dc_b, + an_ac_scan_diag_dc, + an_ac_lbist_ary_wrt_thru_dc, + pc_lq_abist_ena_dc, + pc_lq_abist_raw_dc_b, + pc_lq_abist_wl64_comp_ena, + pc_lq_abist_raddr_0, + pc_lq_abist_g8t_wenb, + pc_lq_abist_g8t1p_renb_0, + pc_lq_abist_g8t_dcomp, + pc_lq_abist_g8t_bw_1, + pc_lq_abist_g8t_bw_0, + pc_lq_abist_di_0, + pc_lq_abist_waddr_0, + pc_lq_bo_unload, + pc_lq_bo_repair, + pc_lq_bo_reset, + pc_lq_bo_shdata, + pc_lq_bo_select, + lq_pc_bo_fail, + lq_pc_bo_diagout, + vcs, + vdd, + gnd, + nclk, + sg_0, + func_sl_thold_0_b, + func_sl_force, + abst_sl_thold_0, + ary_nsl_thold_0, + time_sl_thold_0, + repr_sl_thold_0, + bolt_sl_thold_0, + d_mode_dc, + delay_lclkr_dc, + mpw1_dc_b, + mpw2_dc_b, + scan_in, + abst_scan_in, + time_scan_in, + repr_scan_in, + scan_out, + abst_scan_out, + time_scan_out, + repr_scan_out +); + +// ACT's +input ldq_rel0_stg_act; // Rel0 Stage ACT +input ldq_rel1_stg_act; // Rel0 Stage ACT +input [0:`LMQ_ENTRIES-1] ldqe_ctrl_act; // Reload Queue Entry ACT + +//Reload Data Beats Control +input [0:`LMQ_ENTRIES-1] ldq_rel0_arb_sent; // Reload Arbiter Sent Request +input [0:7] ldq_rel0_beat_upd; // 1-hot Reload Data Beat is Valid +input ldq_rel0_arr_wren; // Reload Data Array Write Enable +input [0:2] ldq_rel0_rdat_qw; // Reload Data Array Write Address +input [0:3] ldq_rel1_cTag; // Reload Core Tag +input [0:`LMQ_ENTRIES-1] ldq_rel1_dbeat_val; // Reload Queue Entry Data is Valid +input [0:`LMQ_ENTRIES-1] ldq_rel1_beats_home; // All data beats have been sent by the L2 +input [0:`LMQ_ENTRIES-1] ldq_rel2_entrySent; // Load Queue Entry attempted to update L1 Data Cache +input ldq_rel2_blk_req; // Reload Attempt was blocked +input [0:`LMQ_ENTRIES-1] ldq_rel2_sentL1; // Reload Queue Entry was not restarted +input [0:`LMQ_ENTRIES-1] ldq_rel2_sentL1_blk; // Reload Queue Entry was restarted +input [0:`LMQ_ENTRIES-1] ldqe_rel_eccdet; // Load Queue Entry detected an ECC error +input [0:`LMQ_ENTRIES-1] ldqe_rst_eccdet; // Load Queue Entry reset error conditions + +// Reload Data Select Valid +input ldq_rel0_rdat_sel; +input [0:143] arb_ldq_rel2_wrt_data; // Reload Interface Data + +// Reload Arbiter Control Outputs +output ldq_rel0_arb_val; // Reload Arbiter is attempting to update L1 Data Cache +output [0:2] ldq_rel0_arb_qw; // Reload Arbiter quadword +output [0:3] ldq_rel0_arb_cTag; // Reload Arbiter core tag +output ldq_rel0_arb_thresh; // Reload Arbiter threshold met +output ldq_rel2_rdat_perr; // Reload Data Array contained a parity error +output ldq_rel3_rdat_par_err; // Reload Data Array contained a parity error FIR report +output [0:`LMQ_ENTRIES-1] ldqe_rel_rdat_perr; // Reload Queue Entry had a reload data array parity error + +// RELOAD Data Queue Control +output ldq_arb_rel2_rdat_sel; // Reload Data Array Select Data +output [0:143] ldq_arb_rel2_rd_data; // Reload Data Array Read + +// SPR +input pc_lq_inj_relq_parity; // Inject Reload Data Array Parity Error +input [0:2] spr_lsucr0_lca_ovrd; // LSUCR0[LCA] + +// Array Pervasive Controls +input bo_enable_2; +input clkoff_dc_b; +input g8t_clkoff_dc_b; +input g8t_d_mode_dc; +input [0:4] g8t_delay_lclkr_dc; +input [0:4] g8t_mpw1_dc_b; +input g8t_mpw2_dc_b; +input pc_lq_ccflush_dc; +input an_ac_scan_dis_dc_b; +input an_ac_scan_diag_dc; +input an_ac_lbist_ary_wrt_thru_dc; +input pc_lq_abist_ena_dc; +input pc_lq_abist_raw_dc_b; +input pc_lq_abist_wl64_comp_ena; +input [3:8] pc_lq_abist_raddr_0; +input pc_lq_abist_g8t_wenb; +input pc_lq_abist_g8t1p_renb_0; +input [0:3] pc_lq_abist_g8t_dcomp; +input pc_lq_abist_g8t_bw_1; +input pc_lq_abist_g8t_bw_0; +input [0:3] pc_lq_abist_di_0; +input [4:9] pc_lq_abist_waddr_0; +input pc_lq_bo_unload; +input pc_lq_bo_repair; +input pc_lq_bo_reset; +input pc_lq_bo_shdata; +input [8:9] pc_lq_bo_select; +output [8:9] lq_pc_bo_fail; +output [8:9] lq_pc_bo_diagout; + +// Pervasive +inout vcs; +inout vdd; +inout gnd; +(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) +input [0:`NCLK_WIDTH-1] nclk; +input sg_0; +input func_sl_thold_0_b; +input func_sl_force; +input abst_sl_thold_0; +input ary_nsl_thold_0; +input time_sl_thold_0; +input repr_sl_thold_0; +input bolt_sl_thold_0; +input d_mode_dc; +input delay_lclkr_dc; +input mpw1_dc_b; +input mpw2_dc_b; + +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) +input scan_in; +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) +input abst_scan_in; +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) +input time_scan_in; +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) +input repr_scan_in; +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) +output scan_out; +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) +output abst_scan_out; +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) +output time_scan_out; +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) +output repr_scan_out; + +//-------------------------- +// components +//-------------------------- + +//-------------------------- +// signals +//-------------------------- +parameter numGrps = ((((`LMQ_ENTRIES-1)/4)+1)*4); + +wire [0:7] ldqe_rel_datSet[0:`LMQ_ENTRIES-1]; +wire [0:7] ldqe_rel_datClr[0:`LMQ_ENTRIES-1]; +wire [0:7] ldqe_rel_datRet_d[0:`LMQ_ENTRIES-1]; +wire [0:7] ldqe_rel_datRet_q[0:`LMQ_ENTRIES-1]; +wire [0:7] ldq_rel1_beat_upd_d; +wire [0:7] ldq_rel1_beat_upd_q; +wire [0:7] ldq_rel2_beat_upd_d; +wire [0:7] ldq_rel2_beat_upd_q; +wire [0:1] ldqe_relAttempts_ctrl[0:`LMQ_ENTRIES-1]; +wire [0:2] ldqe_relAttempts_decr[0:`LMQ_ENTRIES-1]; +wire [0:2] ldqe_relAttempts_d[0:`LMQ_ENTRIES-1]; +wire [0:2] ldqe_relAttempts_q[0:`LMQ_ENTRIES-1]; +wire [0:`LMQ_ENTRIES-1] ldqe_relAttempts_done; +wire [0:`LMQ_ENTRIES-1] ldqe_relThreshold_met; +wire [0:7] ldq_rel0_arb_beats[0:`LMQ_ENTRIES-1]; +wire [0:7] ldq_rel1_arb_beats[0:`LMQ_ENTRIES-1]; +wire [0:7] ldq_rel2_arb_beats[0:`LMQ_ENTRIES-1]; +wire [0:`LMQ_ENTRIES-1] ldqe_relBeats_val; +wire [0:7] ldqe_relBeats_avail[0:`LMQ_ENTRIES-1]; +wire [0:7] ldqe_relBeats_nxt[0:`LMQ_ENTRIES-1]; +reg [0:2] ldqe_relBeats[0:`LMQ_ENTRIES-1]; +wire [0:`LMQ_ENTRIES-1] ldq_rel1_arb_sent_d; +wire [0:`LMQ_ENTRIES-1] ldq_rel1_arb_sent_q; +wire ldq_rel0_arb_val_d; +wire ldq_rel0_arb_val_q; +wire [0:numGrps-1] ldq_rel_arb_entry; +reg [0:2] ldq_rel0_arb_qw_d; +wire [0:2] ldq_rel0_arb_qw_q; +reg [0:3] ldq_rel0_arb_cTag_d; +wire [0:3] ldq_rel0_arb_cTag_q; +reg ldq_rel0_arb_thresh_d; +wire ldq_rel0_arb_thresh_q; +wire [0:3] rel_grpEntry_val[0:(`LMQ_ENTRIES-1)/4]; +wire [0:3] rel_grpEntry_sel[0:(`LMQ_ENTRIES-1)/4]; +wire [0:(`LMQ_ENTRIES-1)/4] rel_grpEntry_sent; +wire [0:3] rel_grpEntry_last_sel_d[0:(`LMQ_ENTRIES-1)/4]; +wire [0:3] rel_grpEntry_last_sel_q[0:(`LMQ_ENTRIES-1)/4]; +reg [0:2] rel_grpEntry_qw[0:(`LMQ_ENTRIES-1)/4]; +reg [0:(`LMQ_ENTRIES-1)/4] rel_grpEntry_thresh; +wire [0:3] rel_group_val; +wire [0:3] rel_group_sel; +wire rel_arb_sentL1; +wire [0:3] rel_group_last_sel_d; +wire [0:3] rel_group_last_sel_q; +wire [0:`LMQ_ENTRIES-1] ldqe_rel_sel; +wire ldq_rel1_rdat_sel_d; +wire ldq_rel1_rdat_sel_q; +wire ldq_rel2_rdat_sel_d; +wire ldq_rel2_rdat_sel_q; +wire ldq_rel2_rdat_par_err; +wire ldq_rel3_rdat_par_err_d; +wire ldq_rel3_rdat_par_err_q; +wire [0:`LMQ_ENTRIES-1] ldq_rel2_arb_sent; +wire [0:1] ldqe_rel_rdat_perr_sel[0:`LMQ_ENTRIES-1]; +wire [0:`LMQ_ENTRIES-1] ldqe_rel_rdat_perr_d; +wire [0:`LMQ_ENTRIES-1] ldqe_rel_rdat_perr_q; +wire [0:2] ldq_rel1_rdat_qw_d; +wire [0:2] ldq_rel1_rdat_qw_q; +wire ldq_rel1_arr_wren_d; +wire ldq_rel1_arr_wren_q; +wire ldq_rel2_arr_wren_d; +wire ldq_rel2_arr_wren_q; +wire ldq_rel2_arr_wren; +wire [0:6] ldq_rel2_arr_waddr; +wire [0:6] ldq_rel2_arr_waddr_d; +wire [0:6] ldq_rel2_arr_waddr_q; +wire ldq_rel0_arr_rd_act; +wire [0:6] ldq_rel0_arr_raddr; +wire [0:143] rdat_rel2_rd_data; +wire [0:143] rel2_rd_data; +wire [0:15] rel2_rdat_par_byte; +wire rel2_rdat_par_err; +wire inj_relq_parity_d; +wire inj_relq_parity_q; + +//-------------------------- +// constants +//-------------------------- +parameter ldqe_rel_datRet_offset = 0; +parameter ldq_rel1_beat_upd_offset = ldqe_rel_datRet_offset + 8 * `LMQ_ENTRIES; +parameter ldq_rel2_beat_upd_offset = ldq_rel1_beat_upd_offset + 8; +parameter ldqe_relAttempts_offset = ldq_rel2_beat_upd_offset + 8; +parameter ldq_rel1_arb_sent_offset = ldqe_relAttempts_offset + 3 * `LMQ_ENTRIES; +parameter ldq_rel0_arb_val_offset = ldq_rel1_arb_sent_offset + `LMQ_ENTRIES; +parameter ldq_rel0_arb_qw_offset = ldq_rel0_arb_val_offset + 1; +parameter ldq_rel0_arb_thresh_offset = ldq_rel0_arb_qw_offset + 3; +parameter ldq_rel0_arb_cTag_offset = ldq_rel0_arb_thresh_offset + 1; +parameter rel_grpEntry_last_sel_offset = ldq_rel0_arb_cTag_offset + 4; +parameter rel_group_last_sel_offset = rel_grpEntry_last_sel_offset + 4 * (((`LMQ_ENTRIES - 1)/4) + 1); +parameter ldq_rel1_rdat_sel_offset = rel_group_last_sel_offset + 4; +parameter ldq_rel2_rdat_sel_offset = ldq_rel1_rdat_sel_offset + 1; +parameter ldq_rel3_rdat_par_err_offset = ldq_rel2_rdat_sel_offset + 1; +parameter ldqe_rel_rdat_perr_offset = ldq_rel3_rdat_par_err_offset + 1; +parameter ldq_rel1_arr_wren_offset = ldqe_rel_rdat_perr_offset + `LMQ_ENTRIES; +parameter ldq_rel2_arr_wren_offset = ldq_rel1_arr_wren_offset + 1; +parameter ldq_rel2_arr_waddr_offset = ldq_rel2_arr_wren_offset + 1; +parameter ldq_rel1_rdat_qw_offset = ldq_rel2_arr_waddr_offset + 7; +parameter inj_relq_parity_offset = ldq_rel1_rdat_qw_offset + 3; +parameter scan_right = inj_relq_parity_offset + 1 - 1; + +wire tiup; +wire tidn; +wire [0:scan_right] siv; +wire [0:scan_right] sov; +wire rdat_scan_in; +wire rdat_scan_out; + +(* analysis_not_referenced="true" *) +wire unused; + +assign tiup = 1'b1; +assign tidn = 1'b0; +assign unused = tidn | ldq_rel2_arr_waddr[0] | ldq_rel0_arr_raddr[0]; + +// Load Queue Reload Handling +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +// Reload Quadword Beat that is trying to update +assign ldq_rel1_beat_upd_d = ldq_rel0_beat_upd; +assign ldq_rel2_beat_upd_d = ldq_rel1_beat_upd_q; + +// One of the Loadmiss Queues has data available to be sent to the L1 +assign ldq_rel0_arb_val_d = |(ldqe_relBeats_val & ~ldqe_rel_eccdet); + +// Reload Data Queue Control +assign ldq_rel1_rdat_sel_d = ldq_rel0_rdat_sel; +assign ldq_rel2_rdat_sel_d = ldq_rel1_rdat_sel_q; + +generate begin : relQ + genvar ldq; + for (ldq=0; ldq<`LMQ_ENTRIES; ldq=ldq+1) begin : relQ + + // Reload Data Beat Home + assign ldqe_rel_datSet[ldq] = ldq_rel1_beat_upd_q & {8{ldq_rel1_dbeat_val[ldq]}}; + + begin : relDatRetQ + genvar beat; + for (beat=0; beat<8; beat=beat+1) begin : relDatRetQ + assign ldqe_rel_datClr[ldq][beat] = (ldq_rel2_beat_upd_q[beat] & ldq_rel2_entrySent[ldq] & ~ldq_rel2_blk_req) | ldqe_rel_eccdet[ldq]; + assign ldqe_rel_datRet_d[ldq][beat] = ldqe_rel_datSet[ldq][beat] | (ldqe_rel_datRet_q[ldq][beat] & (~ldqe_rel_datClr[ldq][beat])); + end + end + + // Reload Attempts from Arbiter + assign ldqe_relAttempts_ctrl[ldq] = {ldq_rel2_sentL1[ldq], (ldq_rel2_sentL1_blk[ldq] & (~ldqe_relAttempts_done[ldq]))}; + assign ldqe_relAttempts_decr[ldq] = ldqe_relAttempts_q[ldq] - 3'b001; + + assign ldqe_relAttempts_d[ldq] = (ldqe_relAttempts_ctrl[ldq] == 2'b00) ? ldqe_relAttempts_q[ldq] : + (ldqe_relAttempts_ctrl[ldq] == 2'b01) ? ldqe_relAttempts_decr[ldq] : + spr_lsucr0_lca_ovrd; + + // Reload Update L1D$ attempts threshold met + // need to HOLD RV until reload is complete + assign ldqe_relAttempts_done[ldq] = ~(|ldqe_relAttempts_q[ldq]); + assign ldqe_relThreshold_met[ldq] = ldqe_relAttempts_done[ldq] & ldqe_relBeats_val[ldq] & ldq_rel1_beats_home[ldq]; + + // Reload Arbiter sent reload for reload queue entry + assign ldq_rel1_arb_sent_d[ldq] = ldq_rel0_arb_sent[ldq]; + + // Beats Available in Reload Arbiters to be sent to L1 + assign ldq_rel0_arb_beats[ldq] = ldq_rel0_beat_upd & {8{ldq_rel0_arb_sent[ldq]}}; + assign ldq_rel1_arb_beats[ldq] = ldq_rel1_beat_upd_q & {8{ldq_rel1_arb_sent_q[ldq]}}; + assign ldq_rel2_arb_beats[ldq] = ldq_rel2_beat_upd_q & {8{ldq_rel2_entrySent[ldq]}}; // Merged results of Reload and Arbiter + assign ldqe_relBeats_avail[ldq] = ldqe_rel_datRet_q[ldq] & (~(ldq_rel0_arb_beats[ldq] | ldq_rel1_arb_beats[ldq] | ldq_rel2_arb_beats[ldq])); + assign ldqe_relBeats_val[ldq] = |(ldqe_relBeats_avail[ldq]); + + // Select Beat from Available beats in Reload Arbiters + assign ldqe_relBeats_nxt[ldq][0] = ldqe_relBeats_avail[ldq][0]; + + begin : relSel genvar beat; + for (beat=1; beat<8; beat=beat+1) begin : relSel + assign ldqe_relBeats_nxt[ldq][beat] = &(~ldqe_relBeats_avail[ldq][0:beat-1]) & ldqe_relBeats_avail[ldq][beat]; + end + end + + // Convert Beat Selected into an Array Index + always @(*) begin: relBeatEntry + reg [0:2] entry; + + //(* analysis_not_referenced="true" *) + + integer beat; + entry = 3'b000; + for (beat=0; beat<8; beat=beat+1) + entry = (beat[2:0] & {3{ldqe_relBeats_nxt[ldq][beat]}}) | entry; + ldqe_relBeats[ldq] = entry; + end + + // Reload Data Queue Parity Error + // REL2 Entry Sent is from the Reload Data Queue Arbiter + assign ldq_rel2_arb_sent[ldq] = ldq_rel2_entrySent[ldq] & ldq_rel2_rdat_sel_q; + assign ldqe_rel_rdat_perr_sel[ldq] = {ldq_rel2_arb_sent[ldq], ldqe_rst_eccdet[ldq]}; + + assign ldqe_rel_rdat_perr_d[ldq] = (ldqe_rel_rdat_perr_sel[ldq] == 2'b10) ? (ldqe_rel_rdat_perr_q[ldq] | ldq_rel2_rdat_par_err) : + (ldqe_rel_rdat_perr_sel[ldq] == 2'b00) ? ldqe_rel_rdat_perr_q[ldq] : + 1'b0; + end +end +endgenerate + +// Reload Data Array Arbiter +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Doing a Round Robin Scheme within each 4 entries (called Groups) +// followed by a Round Robin Scheme within each Group + +// Expand LDQ to max supported +generate begin : relExp + genvar grp; + genvar b; + for (grp=0; grp<=(`LMQ_ENTRIES-1)/4; grp=grp+1) begin : relExp + for (b=0; b<=3; b=b+1) begin : bitSel + if ((grp*4)+b < `LMQ_ENTRIES) begin : ldqExst + assign ldq_rel_arb_entry[(grp*4)+b] = ldqe_relBeats_val[(grp*4)+b]; + end + if ((grp*4)+b >= `LMQ_ENTRIES) begin : ldqNExst + assign ldq_rel_arb_entry[(grp*4)+b] = 1'b0; + end + end + end +end +endgenerate + +// Entry Select within Group +// Round Robin Scheme within each 4 entries in a Group +generate begin : relGrpEntry + genvar grp; + for (grp=0; grp<=(`LMQ_ENTRIES-1)/4; grp=grp+1) begin : relGrpEntry + assign rel_grpEntry_val[grp] = {ldq_rel_arb_entry[4*grp+0], ldq_rel_arb_entry[4*grp+1], ldq_rel_arb_entry[4*grp+2], ldq_rel_arb_entry[4*grp+3]}; + assign rel_grpEntry_sel[grp][0] = (rel_grpEntry_last_sel_q[grp][0] & ~(|rel_grpEntry_val[grp][1:3]) & rel_grpEntry_val[grp][0]) | + (rel_grpEntry_last_sel_q[grp][1] & ~(|rel_grpEntry_val[grp][2:3]) & rel_grpEntry_val[grp][0]) | + (rel_grpEntry_last_sel_q[grp][2] & ~rel_grpEntry_val[grp][3] & rel_grpEntry_val[grp][0]) | + (rel_grpEntry_last_sel_q[grp][3] & rel_grpEntry_val[grp][0]); + + assign rel_grpEntry_sel[grp][1] = (rel_grpEntry_last_sel_q[grp][0] & rel_grpEntry_val[grp][1]) | + (rel_grpEntry_last_sel_q[grp][1] & ~(|{rel_grpEntry_val[grp][0], rel_grpEntry_val[grp][2:3]}) & rel_grpEntry_val[grp][1]) | + (rel_grpEntry_last_sel_q[grp][2] & ~(|{rel_grpEntry_val[grp][0], rel_grpEntry_val[grp][3]}) & rel_grpEntry_val[grp][1]) | + (rel_grpEntry_last_sel_q[grp][3] & ~rel_grpEntry_val[grp][0] & rel_grpEntry_val[grp][1]); + + assign rel_grpEntry_sel[grp][2] = (rel_grpEntry_last_sel_q[grp][0] & ~rel_grpEntry_val[grp][1] & rel_grpEntry_val[grp][2]) | + (rel_grpEntry_last_sel_q[grp][1] & rel_grpEntry_val[grp][2]) | + (rel_grpEntry_last_sel_q[grp][2] & ~(|{rel_grpEntry_val[grp][0:1], rel_grpEntry_val[grp][3]}) & rel_grpEntry_val[grp][2]) | + (rel_grpEntry_last_sel_q[grp][3] & ~(|rel_grpEntry_val[grp][0:1]) & rel_grpEntry_val[grp][2]); + + assign rel_grpEntry_sel[grp][3] = (rel_grpEntry_last_sel_q[grp][0] & ~(|rel_grpEntry_val[grp][1:2]) & rel_grpEntry_val[grp][3]) | + (rel_grpEntry_last_sel_q[grp][1] & ~rel_grpEntry_val[grp][2] & rel_grpEntry_val[grp][3]) | + (rel_grpEntry_last_sel_q[grp][2] & rel_grpEntry_val[grp][3]) | + (rel_grpEntry_last_sel_q[grp][3] & ~(|rel_grpEntry_val[grp][0:2]) & rel_grpEntry_val[grp][3]); + + // Load Queue Group Selected + assign rel_grpEntry_sent[grp] = rel_group_sel[grp] & ldq_rel0_arb_val_d; + assign rel_grpEntry_last_sel_d[grp] = rel_grpEntry_sent[grp] ? rel_grpEntry_sel[grp] : rel_grpEntry_last_sel_q[grp]; + + // Mux Load Queue Entry within a Group + always @(*) begin: relMux + reg [0:2] qw; + reg thresh; + //(* analysis_not_referenced="true" *) + integer ldq; + + qw = {3{1'b0}}; + thresh = 1'b0; + for (ldq=0; ldq<=3; ldq=ldq+1) begin : ldqExst + if ((grp*4)+ldq < `LMQ_ENTRIES) begin : ldqExst + qw = (ldqe_relBeats[(grp*4)+ldq] & {3{rel_grpEntry_sel[grp][ldq]}}) | qw; + thresh = (ldqe_relThreshold_met[(grp*4)+ldq] & rel_grpEntry_sel[grp][ldq]) | thresh; + end + end + rel_grpEntry_qw[grp] = qw; + rel_grpEntry_thresh[grp] = thresh; + end + end +end +endgenerate + +// Group Select Between all Groups +// Round Robin Scheme within Groups +generate begin : relGrp + genvar grp; + for (grp=0; grp<=3; grp=grp+1) begin : relGrp + if (grp <= (`LMQ_ENTRIES - 1)/4) begin : grpExst + assign rel_group_val[grp] = |(rel_grpEntry_val[grp]); + end + if (grp > (`LMQ_ENTRIES - 1)/4) begin : grpNExst + assign rel_group_val[grp] = 1'b0; + end + end +end +endgenerate + +assign rel_group_sel[0] = (rel_group_last_sel_q[0] & ~(|rel_group_val[1:3]) & rel_group_val[0]) | + (rel_group_last_sel_q[1] & ~(|rel_group_val[2:3]) & rel_group_val[0]) | + (rel_group_last_sel_q[2] & ~rel_group_val[3] & rel_group_val[0]) | + (rel_group_last_sel_q[3] & rel_group_val[0]); + +assign rel_group_sel[1] = (rel_group_last_sel_q[0] & rel_group_val[1]) | + (rel_group_last_sel_q[1] & ~(|{rel_group_val[0], rel_group_val[2:3]}) & rel_group_val[1]) | + (rel_group_last_sel_q[2] & ~(|{rel_group_val[0], rel_group_val[3]}) & rel_group_val[1]) | + (rel_group_last_sel_q[3] & ~rel_group_val[0] & rel_group_val[1]); + +assign rel_group_sel[2] = (rel_group_last_sel_q[0] & (~rel_group_val[1]) & rel_group_val[2]) | + (rel_group_last_sel_q[1] & rel_group_val[2]) | + (rel_group_last_sel_q[2] & ~(|{rel_group_val[0:1], rel_group_val[3]}) & rel_group_val[2]) | + (rel_group_last_sel_q[3] & ~(|rel_group_val[0:1]) & rel_group_val[2]); + +assign rel_group_sel[3] = (rel_group_last_sel_q[0] & ~(|rel_group_val[1:2]) & rel_group_val[3]) | + (rel_group_last_sel_q[1] & ~rel_group_val[2] & rel_group_val[3]) | + (rel_group_last_sel_q[2] & rel_group_val[3]) | + (rel_group_last_sel_q[3] & ~(|rel_group_val[0:2]) & rel_group_val[3]); + +// Reload Queue Entry Sent +generate begin : relSent + genvar grp; + for (grp=0; grp<=(`LMQ_ENTRIES-1)/4; grp=grp+1) begin : relSent + genvar ldq; + for (ldq=0; ldq<=3; ldq=ldq+1) begin : ldqEntry + assign ldqe_rel_sel[ldq+(grp*4)] = rel_grpEntry_sel[grp][ldq] & rel_group_sel[grp] & ldq_rel0_arb_val_d; + end + end +end +endgenerate + +assign rel_arb_sentL1 = |(ldqe_rel_sel); +assign rel_group_last_sel_d = rel_arb_sentL1 ? rel_group_sel : rel_group_last_sel_q; + +// Mux Load Queue Entry between Groups +always @(*) begin: relGrpLqMux + reg [0:2] qw; + reg thresh; + + //(* analysis_not_referenced="true" *) + integer grp; + + qw = {3{1'b0}}; + thresh = 1'b0; + for (grp=0; grp<=3; grp=grp+1) begin : relGrpLqMux + if (grp <= (`LMQ_ENTRIES-1)/4) begin : GrpExst + qw = (rel_grpEntry_qw[grp] & {3{rel_group_sel[grp]}}) | qw; + thresh = (rel_grpEntry_thresh[grp] & rel_group_sel[grp]) | thresh; + end + end + ldq_rel0_arb_qw_d = qw; + ldq_rel0_arb_thresh_d = thresh; +end + +// Generate Reload Core Tag +always @(*) begin: relcTag + reg [0:3] cTag; + + //(* analysis_not_referenced="true" *) + integer ldq; + + cTag = 4'b0000; + for (ldq=0; ldq<`LMQ_ENTRIES; ldq=ldq+1) + cTag = (ldq[2:0] & {4{ldqe_rel_sel[ldq]}}) | cTag; + ldq_rel0_arb_cTag_d = cTag; +end + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Reload Data Array +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +generate begin : relq + genvar bb; + if (`RELQ_INCLUDE == 1) begin + tri_64x144_1r1w rdat( + + // POWER PINS + .vcs(vcs), + .vdd(vdd), + .gnd(gnd), + + // CLOCK AND CLOCKCONTROL PORTS + .nclk(nclk), + .rd_act(ldq_rel0_arr_rd_act), + .wr_act(ldq_rel2_arr_wren), + .sg_0(sg_0), + .abst_sl_thold_0(abst_sl_thold_0), + .ary_nsl_thold_0(ary_nsl_thold_0), + .time_sl_thold_0(time_sl_thold_0), + .repr_sl_thold_0(repr_sl_thold_0), + .func_sl_force(func_sl_force), + .func_sl_thold_0_b(func_sl_thold_0_b), + .g8t_clkoff_dc_b(g8t_clkoff_dc_b), + .ccflush_dc(pc_lq_ccflush_dc), + .scan_dis_dc_b(an_ac_scan_dis_dc_b), + .scan_diag_dc(an_ac_scan_diag_dc), + .g8t_d_mode_dc(g8t_d_mode_dc), + .g8t_mpw1_dc_b(g8t_mpw1_dc_b), + .g8t_mpw2_dc_b(g8t_mpw2_dc_b), + .g8t_delay_lclkr_dc(g8t_delay_lclkr_dc), + .d_mode_dc(d_mode_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .delay_lclkr_dc(delay_lclkr_dc), + + // ABIST + .wr_abst_act(pc_lq_abist_g8t_wenb), + .rd0_abst_act(pc_lq_abist_g8t1p_renb_0), + .abist_di(pc_lq_abist_di_0), + .abist_bw_odd(pc_lq_abist_g8t_bw_1), + .abist_bw_even(pc_lq_abist_g8t_bw_0), + .abist_wr_adr(pc_lq_abist_waddr_0), + .abist_rd0_adr(pc_lq_abist_raddr_0), + .tc_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc), + .abist_ena_1(pc_lq_abist_ena_dc), + .abist_g8t_rd0_comp_ena(pc_lq_abist_wl64_comp_ena), + .abist_raw_dc_b(pc_lq_abist_raw_dc_b), + .obs0_abist_cmp(pc_lq_abist_g8t_dcomp), + + // SCAN PORTS + .abst_scan_in(abst_scan_in), + .time_scan_in(time_scan_in), + .repr_scan_in(repr_scan_in), + .func_scan_in(rdat_scan_in), + .abst_scan_out(abst_scan_out), + .time_scan_out(time_scan_out), + .repr_scan_out(repr_scan_out), + .func_scan_out(rdat_scan_out), + + // BOLT-ON + .lcb_bolt_sl_thold_0(bolt_sl_thold_0), + .pc_bo_enable_2(bo_enable_2), + .pc_bo_reset(pc_lq_bo_reset), + .pc_bo_unload(pc_lq_bo_unload), + .pc_bo_repair(pc_lq_bo_repair), + .pc_bo_shdata(pc_lq_bo_shdata), + .pc_bo_select(pc_lq_bo_select[8:9]), + .bo_pc_failout(lq_pc_bo_fail[8:9]), + .bo_pc_diagloop(lq_pc_bo_diagout[8:9]), + .tri_lcb_mpw1_dc_b(mpw1_dc_b), + .tri_lcb_mpw2_dc_b(mpw2_dc_b), + .tri_lcb_delay_lclkr_dc(delay_lclkr_dc), + .tri_lcb_clkoff_dc_b(clkoff_dc_b), + .tri_lcb_act_dis_dc(tidn), + + // Write Ports + .write_enable(ldq_rel2_arr_wren), + .addr_wr(ldq_rel2_arr_waddr[1:6]), + .data_in(arb_ldq_rel2_wrt_data), + + // Read Ports + .addr_rd(ldq_rel0_arr_raddr[1:6]), + .data_out(rdat_rel2_rd_data) + ); + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // Reload Queue Parity Error Detection + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // Inject a Parity Error on the Reload Data Queue Access + assign inj_relq_parity_d = pc_lq_inj_relq_parity; + assign rel2_rd_data = {(rdat_rel2_rd_data[0] ^ inj_relq_parity_q), rdat_rel2_rd_data[1:143]}; + + for (bb=0;bb<16;bb=bb+1) begin : relData + assign rel2_rdat_par_byte[bb] = ^({rel2_rd_data[bb*8:(bb*8)+7], rel2_rd_data[128+bb]}); + end + + assign rel2_rdat_par_err = |(rel2_rdat_par_byte); + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // Reload Queue Control + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // Update Reload Array + assign ldq_rel1_rdat_qw_d = ldq_rel0_rdat_qw; + assign ldq_rel1_arr_wren_d = ldq_rel0_arr_wren; + assign ldq_rel2_arr_wren_d = ldq_rel1_arr_wren_q; + assign ldq_rel2_arr_waddr_d = {ldq_rel1_cTag, ldq_rel1_rdat_qw_q}; + + assign ldq_rel0_arr_rd_act = ldq_rel0_rdat_sel; + assign ldq_rel0_arr_raddr = {ldq_rel0_arb_cTag_q, ldq_rel0_arb_qw_q}; + assign ldq_rel2_arr_wren = ldq_rel2_arr_wren_q & ldq_rel2_blk_req; + assign ldq_rel2_arr_waddr = ldq_rel2_arr_waddr_q; + + // Reload Data Queue Parity Error + assign ldq_rel2_rdat_par_err = rel2_rdat_par_err & ldq_rel2_rdat_sel_q & ~ldq_rel2_blk_req; + assign ldq_rel3_rdat_par_err_d = ldq_rel2_rdat_par_err; + end else begin + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // Reload Queue Parity Error Detection + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // Inject a Parity Error on the Reload Data Queue Access + assign inj_relq_parity_d = pc_lq_inj_relq_parity; + assign rdat_rel2_rd_data = 144'b0; + assign rel2_rd_data = {(rdat_rel2_rd_data[0] ^ inj_relq_parity_q), rdat_rel2_rd_data[1:143]}; + + for (bb=0;bb<16;bb=bb+1) begin : relData + assign rel2_rdat_par_byte[bb] = ^({rel2_rd_data[bb*8:(bb*8)+7], rel2_rd_data[128+bb]}); + end + + assign rel2_rdat_par_err = 1'b0; + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // Reload Queue Control + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // Update Reload Array + assign ldq_rel1_rdat_qw_d = 3'b0; + assign ldq_rel1_arr_wren_d = 1'b0; + assign ldq_rel2_arr_wren_d = ldq_rel1_arr_wren_q; + assign ldq_rel2_arr_waddr_d = 7'b0; + + assign ldq_rel0_arr_rd_act = 1'b0; + assign ldq_rel0_arr_raddr = 7'b0; + assign ldq_rel2_arr_wren = 1'b0; + assign ldq_rel2_arr_waddr = ldq_rel2_arr_waddr_q; + + // Reload Data Queue Parity Error + assign ldq_rel2_rdat_par_err = 1'b0; + assign ldq_rel3_rdat_par_err_d = ldq_rel2_rdat_par_err; + + assign abst_scan_out = abst_scan_in; + assign time_scan_out = time_scan_in; + assign repr_scan_out = repr_scan_in; + assign rdat_scan_out = rdat_scan_in; + assign lq_pc_bo_fail = 2'b0; + assign lq_pc_bo_diagout = 2'b0; + end +end endgenerate + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// OUTPUTS +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +// Reload Data Arbiter Control +assign ldq_rel0_arb_val = ldq_rel0_arb_val_q; +assign ldq_rel0_arb_qw = ldq_rel0_arb_qw_q; +assign ldq_rel0_arb_cTag = ldq_rel0_arb_cTag_q; +assign ldq_rel0_arb_thresh = ldq_rel0_arb_thresh_q; +assign ldq_rel2_rdat_perr = |(ldqe_rel_rdat_perr_q & ldq_rel2_entrySent) | ldq_rel2_rdat_par_err; +assign ldq_rel3_rdat_par_err = ldq_rel3_rdat_par_err_q; +assign ldqe_rel_rdat_perr = ldqe_rel_rdat_perr_q; + +// Reload Data Array Control +assign ldq_arb_rel2_rdat_sel = ldq_rel2_rdat_sel_q; +assign ldq_arb_rel2_rd_data = rel2_rd_data; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// REGISTERS +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +generate begin : ldqe_rel_datRet + genvar ldq; + for (ldq=0; ldq<`LMQ_ENTRIES; ldq=ldq+1) begin : ldqe_rel_datRet + tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ldqe_rel_datRet_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ldqe_ctrl_act[ldq]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldqe_rel_datRet_offset + (8 * ldq):ldqe_rel_datRet_offset + (8 * (ldq + 1)) - 1]), + .scout(sov[ldqe_rel_datRet_offset + (8 * ldq):ldqe_rel_datRet_offset + (8 * (ldq + 1)) - 1]), + .din(ldqe_rel_datRet_d[ldq]), + .dout(ldqe_rel_datRet_q[ldq]) + ); + end +end +endgenerate + +tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_beat_upd_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel1_beat_upd_offset:ldq_rel1_beat_upd_offset + 8 - 1]), + .scout(sov[ldq_rel1_beat_upd_offset:ldq_rel1_beat_upd_offset + 8 - 1]), + .din(ldq_rel1_beat_upd_d), + .dout(ldq_rel1_beat_upd_q) +); + +tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ldq_rel2_beat_upd_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel2_beat_upd_offset:ldq_rel2_beat_upd_offset + 8 - 1]), + .scout(sov[ldq_rel2_beat_upd_offset:ldq_rel2_beat_upd_offset + 8 - 1]), + .din(ldq_rel2_beat_upd_d), + .dout(ldq_rel2_beat_upd_q) +); + +generate begin : ldqe_relAttempts + genvar ldq; + for (ldq=0; ldq<`LMQ_ENTRIES; ldq=ldq+1) begin : ldqe_relAttempts + tri_rlmreg_p #(.WIDTH(3), .INIT(7), .NEEDS_SRESET(1)) ldqe_relAttempts_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ldqe_ctrl_act[ldq]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldqe_relAttempts_offset + (3 * ldq):ldqe_relAttempts_offset + (3 * (ldq + 1)) - 1]), + .scout(sov[ldqe_relAttempts_offset + (3 * ldq):ldqe_relAttempts_offset + (3 * (ldq + 1)) - 1]), + .din(ldqe_relAttempts_d[ldq]), + .dout(ldqe_relAttempts_q[ldq]) + ); + end +end +endgenerate + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_arb_sent_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel1_arb_sent_offset:ldq_rel1_arb_sent_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldq_rel1_arb_sent_offset:ldq_rel1_arb_sent_offset + `LMQ_ENTRIES - 1]), + .din(ldq_rel1_arb_sent_d), + .dout(ldq_rel1_arb_sent_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel0_arb_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel0_arb_val_offset]), + .scout(sov[ldq_rel0_arb_val_offset]), + .din(ldq_rel0_arb_val_d), + .dout(ldq_rel0_arb_val_q) +); + +tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ldq_rel0_arb_qw_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel0_arb_qw_offset:ldq_rel0_arb_qw_offset + 3 - 1]), + .scout(sov[ldq_rel0_arb_qw_offset:ldq_rel0_arb_qw_offset + 3 - 1]), + .din(ldq_rel0_arb_qw_d), + .dout(ldq_rel0_arb_qw_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel0_arb_thresh_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel0_arb_thresh_offset]), + .scout(sov[ldq_rel0_arb_thresh_offset]), + .din(ldq_rel0_arb_thresh_d), + .dout(ldq_rel0_arb_thresh_q) +); + +tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ldq_rel0_arb_cTag_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel0_arb_cTag_offset:ldq_rel0_arb_cTag_offset + 4 - 1]), + .scout(sov[ldq_rel0_arb_cTag_offset:ldq_rel0_arb_cTag_offset + 4 - 1]), + .din(ldq_rel0_arb_cTag_d), + .dout(ldq_rel0_arb_cTag_q) +); + +generate begin : rel_grpEntry_last_sel + genvar grp; + for (grp=0; grp<=(`LMQ_ENTRIES-1)/4; grp=grp+1) begin : rel_grpEntry_last_sel + tri_rlmreg_p #(.WIDTH(4), .INIT(8), .NEEDS_SRESET(1)) rel_grpEntry_last_sel_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rel_grpEntry_last_sel_offset + (4 * grp):rel_grpEntry_last_sel_offset + (4 * (grp + 1)) - 1]), + .scout(sov[rel_grpEntry_last_sel_offset + (4 * grp):rel_grpEntry_last_sel_offset + (4 * (grp + 1)) - 1]), + .din(rel_grpEntry_last_sel_d[grp]), + .dout(rel_grpEntry_last_sel_q[grp]) + ); + end +end +endgenerate + +tri_rlmreg_p #(.WIDTH(4), .INIT(8), .NEEDS_SRESET(1)) rel_group_last_sel_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rel_group_last_sel_offset:rel_group_last_sel_offset + 4 - 1]), + .scout(sov[rel_group_last_sel_offset:rel_group_last_sel_offset + 4 - 1]), + .din(rel_group_last_sel_d), + .dout(rel_group_last_sel_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel1_rdat_sel_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel1_rdat_sel_offset]), + .scout(sov[ldq_rel1_rdat_sel_offset]), + .din(ldq_rel1_rdat_sel_d), + .dout(ldq_rel1_rdat_sel_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel2_rdat_sel_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel2_rdat_sel_offset]), + .scout(sov[ldq_rel2_rdat_sel_offset]), + .din(ldq_rel2_rdat_sel_d), + .dout(ldq_rel2_rdat_sel_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel3_rdat_par_err_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel3_rdat_par_err_offset]), + .scout(sov[ldq_rel3_rdat_par_err_offset]), + .din(ldq_rel3_rdat_par_err_d), + .dout(ldq_rel3_rdat_par_err_q) +); + +tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_rel_rdat_perr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldqe_rel_rdat_perr_offset:ldqe_rel_rdat_perr_offset + `LMQ_ENTRIES - 1]), + .scout(sov[ldqe_rel_rdat_perr_offset:ldqe_rel_rdat_perr_offset + `LMQ_ENTRIES - 1]), + .din(ldqe_rel_rdat_perr_d), + .dout(ldqe_rel_rdat_perr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel1_arr_wren_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel1_arr_wren_offset]), + .scout(sov[ldq_rel1_arr_wren_offset]), + .din(ldq_rel1_arr_wren_d), + .dout(ldq_rel1_arr_wren_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel2_arr_wren_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel2_arr_wren_offset]), + .scout(sov[ldq_rel2_arr_wren_offset]), + .din(ldq_rel2_arr_wren_d), + .dout(ldq_rel2_arr_wren_q) +); + +tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(1)) ldq_rel2_arr_waddr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ldq_rel1_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel2_arr_waddr_offset:ldq_rel2_arr_waddr_offset + 7 - 1]), + .scout(sov[ldq_rel2_arr_waddr_offset:ldq_rel2_arr_waddr_offset + 7 - 1]), + .din(ldq_rel2_arr_waddr_d), + .dout(ldq_rel2_arr_waddr_q) +); + +tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_rdat_qw_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ldq_rel0_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_rel1_rdat_qw_offset:ldq_rel1_rdat_qw_offset + 3 - 1]), + .scout(sov[ldq_rel1_rdat_qw_offset:ldq_rel1_rdat_qw_offset + 3 - 1]), + .din(ldq_rel1_rdat_qw_d), + .dout(ldq_rel1_rdat_qw_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) inj_relq_parity_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[inj_relq_parity_offset]), + .scout(sov[inj_relq_parity_offset]), + .din(inj_relq_parity_d), + .dout(inj_relq_parity_q) +); + +assign rdat_scan_in = scan_in; +assign siv[0:scan_right] = {sov[1:scan_right], rdat_scan_out}; +assign scan_out = sov[0]; + +endmodule diff --git a/dev/verilog/work/lq_ldq_rot.v b/dev/verilog/work/lq_ldq_rot.v new file mode 100755 index 0000000..850b3b8 --- /dev/null +++ b/dev/verilog/work/lq_ldq_rot.v @@ -0,0 +1,496 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// +// Description: XU LSU Store Data Rotator Wrapper +// +//***************************************************************************** + +`include "tri_a2o.vh" + +module lq_ldq_rot( + ldq_rel1_stg_act, + ldq_rel1_rot_sel1, + ldq_rel1_rot_sel2, + ldq_rel1_rot_sel3, + ldq_rel1_data, + ldq_rel1_opsize, + ldq_rel1_byte_swap, + ldq_rel1_algebraic, + ldq_rel1_algebraic_sel, + ldq_rel1_gpr_val, + ldq_rel1_dvc1_en, + ldq_rel1_dvc2_en, + ldq_rel2_thrd_id, + ctl_lsq_spr_dvc1_dbg, + ctl_lsq_spr_dvc2_dbg, + ctl_lsq_spr_dbcr2_dvc1be, + ctl_lsq_spr_dbcr2_dvc1m, + ctl_lsq_spr_dbcr2_dvc2be, + ctl_lsq_spr_dbcr2_dvc2m, + ldq_rel2_rot_data, + ldq_rel2_dvc, + vdd, + gnd, + nclk, + sg_0, + func_sl_thold_0_b, + func_sl_force, + d_mode_dc, + delay_lclkr_dc, + mpw1_dc_b, + mpw2_dc_b, + scan_in, + scan_out +); + +//------------------------------------------------------------------- +// Generics +//------------------------------------------------------------------- +//parameter EXPAND_TYPE = 2; // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) +//parameter `GPR_WIDTH_ENC = 6; // Register Mode 5 = 32bit, 6 = 64bit +//parameter `THREADS = 2; // Number of `THREADS + +// ACT +input ldq_rel1_stg_act; + +// Reload Rotator Control +input [0:7] ldq_rel1_rot_sel1; +input [0:7] ldq_rel1_rot_sel2; +input [0:7] ldq_rel1_rot_sel3; +input [0:127] ldq_rel1_data; + +// Reload Data Fixup Control +input [0:2] ldq_rel1_opsize; +input ldq_rel1_byte_swap; +input ldq_rel1_algebraic; +input [0:3] ldq_rel1_algebraic_sel; +input ldq_rel1_gpr_val; +input ldq_rel1_dvc1_en; +input ldq_rel1_dvc2_en; +input [0:`THREADS-1] ldq_rel2_thrd_id; + +// Data Value Compare Registers +input [64-(2**`GPR_WIDTH_ENC):63] ctl_lsq_spr_dvc1_dbg; +input [64-(2**`GPR_WIDTH_ENC):63] ctl_lsq_spr_dvc2_dbg; +input [0:8*`THREADS-1] ctl_lsq_spr_dbcr2_dvc1be; +input [0:2*`THREADS-1] ctl_lsq_spr_dbcr2_dvc1m; +input [0:8*`THREADS-1] ctl_lsq_spr_dbcr2_dvc2be; +input [0:2*`THREADS-1] ctl_lsq_spr_dbcr2_dvc2m; + +// Reload Rotator Output +output [0:127] ldq_rel2_rot_data; +output [0:1] ldq_rel2_dvc; + +// Pervasive + + +inout vdd; + + +inout gnd; + +(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) + +input [0:`NCLK_WIDTH-1] nclk; +input sg_0; +input func_sl_thold_0_b; +input func_sl_force; +input d_mode_dc; +input delay_lclkr_dc; +input mpw1_dc_b; +input mpw2_dc_b; + +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + +input scan_in; + +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + +output scan_out; + + +//-------------------------- +// components +//-------------------------- + +//-------------------------- +// signals +//-------------------------- +wire [0:127] rel1_data_swzl; +wire [0:127] rel1_rot_data; +wire [0:15] be_byte_bit0; +wire [0:15] le_byte_bit0; +wire [0:15] rel1_alg_byte; +wire rel1_alg_bit; +wire [0:4] rel1_1hot_opsize; +wire [0:7] rel1_byte_mask; +wire [0:((2**`GPR_WIDTH_ENC)-1)/8] rel2_byte_mask_d; +wire [0:((2**`GPR_WIDTH_ENC)-1)/8] rel2_byte_mask_q; +wire [0:15] rel1_bittype_mask; +wire [0:127] rel1_optype_mask; +wire [0:127] rel1_msk_data; +wire lh_algebraic; +wire lw_algebraic; +wire [0:47] lh_algebraic_msk; +wire [0:47] lw_algebraic_msk; +wire [0:47] rel1_algebraic_msk; +wire [0:127] rel1_algebraic_msk_data; +wire [0:127] rel1_swzl_data; +wire [0:127] rel2_rot_data_d; +wire [0:127] rel2_rot_data_q; +wire rel2_dvc1_val_d; +wire rel2_dvc1_val_q; +wire rel2_dvc2_val_d; +wire rel2_dvc2_val_q; +wire [0:((2**`GPR_WIDTH_ENC)/8)-1] rel2_dvc1_cmp; +wire [0:((2**`GPR_WIDTH_ENC)/8)-1] rel2_dvc2_cmp; +wire rel2_dvc1r_cmpr; +wire rel2_dvc2r_cmpr; +reg [0:1] spr_dbcr2_dvc1m; +reg [0:1] spr_dbcr2_dvc2m; +reg [8-(2**`GPR_WIDTH_ENC)/8:7] spr_dbcr2_dvc1be; +reg [8-(2**`GPR_WIDTH_ENC)/8:7] spr_dbcr2_dvc2be; +wire [0:7] ctl_lsq_spr_dbcr2_dvc1be_int[0:`THREADS-1]; +wire [0:1] ctl_lsq_spr_dbcr2_dvc1m_int[0:`THREADS-1]; +wire [0:7] ctl_lsq_spr_dbcr2_dvc2be_int[0:`THREADS-1]; +wire [0:1] ctl_lsq_spr_dbcr2_dvc2m_int[0:`THREADS-1]; + +//-------------------------- +// constants +//-------------------------- +parameter rel2_byte_mask_offset = 0; +parameter rel2_rot_data_offset = rel2_byte_mask_offset + (((2**`GPR_WIDTH_ENC)-1)/8-0+1); +parameter rel2_dvc1_val_offset = rel2_rot_data_offset + 128; +parameter rel2_dvc2_val_offset = rel2_dvc1_val_offset + 1; +parameter scan_right = rel2_dvc2_val_offset + 1 - 1; + +wire tiup; +wire [0:scan_right] siv; +wire [0:scan_right] sov; + +assign tiup = 1'b1; + +// ############################################################################################# +// 16 Byte Reload Rotator +// ############################################################################################# + +// Thread Unpack +generate begin : sprTid + genvar tid; + for (tid=0; tid<`THREADS; tid=tid+1) begin : sprTid + assign ctl_lsq_spr_dbcr2_dvc1be_int[tid] = ctl_lsq_spr_dbcr2_dvc1be[8*tid:8*(tid+1)-1]; + assign ctl_lsq_spr_dbcr2_dvc1m_int[tid] = ctl_lsq_spr_dbcr2_dvc1m[2*tid:2*(tid+1)-1]; + assign ctl_lsq_spr_dbcr2_dvc2be_int[tid] = ctl_lsq_spr_dbcr2_dvc2be[8*tid:8*(tid+1)-1]; + assign ctl_lsq_spr_dbcr2_dvc2m_int[tid] = ctl_lsq_spr_dbcr2_dvc2m[2*tid:2*(tid+1)-1]; + end + end +endgenerate + +// Swizzle Rotate Data +generate begin : swzlRelData + genvar t; + for (t=0; t<8; t=t+1) begin : swzlRelData + assign rel1_data_swzl[t*16:(t*16)+15] = {ldq_rel1_data[t+0], ldq_rel1_data[t+8], ldq_rel1_data[t+16], ldq_rel1_data[t+24], + ldq_rel1_data[t+32], ldq_rel1_data[t+40], ldq_rel1_data[t+48], ldq_rel1_data[t+56], + ldq_rel1_data[t+64], ldq_rel1_data[t+72], ldq_rel1_data[t+80], ldq_rel1_data[t+88], + ldq_rel1_data[t+96], ldq_rel1_data[t+104], ldq_rel1_data[t+112], ldq_rel1_data[t+120]}; + end + end +endgenerate + +// Reload Data Rotate +generate begin : rrotl + genvar b; + for (b=0; b<8; b=b+1) begin : rrotl + tri_rot16_lu drotl( + + // Rotator Controls and Data + .rot_sel1(ldq_rel1_rot_sel1), + .rot_sel2(ldq_rel1_rot_sel2), + .rot_sel3(ldq_rel1_rot_sel3), + .rot_data(rel1_data_swzl[b*16:(b*16)+15]), + + // Rotated Data + .data_rot(rel1_rot_data[b*16:(b*16)+15]), + + // Pervasive + .vdd(vdd), + .gnd(gnd) + ); + end + end +endgenerate + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Reload Algebraic Bit Select +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +assign be_byte_bit0 = {ldq_rel1_data[0], ldq_rel1_data[8], ldq_rel1_data[16], ldq_rel1_data[24], + ldq_rel1_data[32], ldq_rel1_data[40], ldq_rel1_data[48], ldq_rel1_data[56], + ldq_rel1_data[64], ldq_rel1_data[72], ldq_rel1_data[80], ldq_rel1_data[88], + ldq_rel1_data[96], ldq_rel1_data[104], ldq_rel1_data[112], ldq_rel1_data[120]}; + +assign le_byte_bit0 = {ldq_rel1_data[120], ldq_rel1_data[112], ldq_rel1_data[104], ldq_rel1_data[96], + ldq_rel1_data[88], ldq_rel1_data[80], ldq_rel1_data[72], ldq_rel1_data[64], + ldq_rel1_data[56], ldq_rel1_data[48], ldq_rel1_data[40], ldq_rel1_data[32], + ldq_rel1_data[24], ldq_rel1_data[16], ldq_rel1_data[8], ldq_rel1_data[0]}; + +// Select between little endian data or big-endian data +assign rel1_alg_byte = ldq_rel1_byte_swap ? le_byte_bit0 : be_byte_bit0; + +// Algebraic Bit Select +assign rel1_alg_bit = (ldq_rel1_algebraic_sel == 4'b0000) ? rel1_alg_byte[0] : + (ldq_rel1_algebraic_sel == 4'b0001) ? rel1_alg_byte[1] : + (ldq_rel1_algebraic_sel == 4'b0010) ? rel1_alg_byte[2] : + (ldq_rel1_algebraic_sel == 4'b0011) ? rel1_alg_byte[3] : + (ldq_rel1_algebraic_sel == 4'b0100) ? rel1_alg_byte[4] : + (ldq_rel1_algebraic_sel == 4'b0101) ? rel1_alg_byte[5] : + (ldq_rel1_algebraic_sel == 4'b0110) ? rel1_alg_byte[6] : + (ldq_rel1_algebraic_sel == 4'b0111) ? rel1_alg_byte[7] : + (ldq_rel1_algebraic_sel == 4'b1000) ? rel1_alg_byte[8] : + (ldq_rel1_algebraic_sel == 4'b1001) ? rel1_alg_byte[9] : + (ldq_rel1_algebraic_sel == 4'b1010) ? rel1_alg_byte[10] : + (ldq_rel1_algebraic_sel == 4'b1011) ? rel1_alg_byte[11] : + (ldq_rel1_algebraic_sel == 4'b1100) ? rel1_alg_byte[12] : + (ldq_rel1_algebraic_sel == 4'b1101) ? rel1_alg_byte[13] : + (ldq_rel1_algebraic_sel == 4'b1110) ? rel1_alg_byte[14] : + rel1_alg_byte[15]; + +// ############################################################################################# +// Op Size Mask Generation for Reloads +// ############################################################################################# + +assign rel1_1hot_opsize = (ldq_rel1_opsize == 3'b110) ? 5'b10000 : // 16Bytes + (ldq_rel1_opsize == 3'b101) ? 5'b01000 : // 8Bytes + (ldq_rel1_opsize == 3'b100) ? 5'b00100 : // 4Bytes + (ldq_rel1_opsize == 3'b010) ? 5'b00010 : // 2Bytes + (ldq_rel1_opsize == 3'b001) ? 5'b00001 : // 1Bytes + 5'b00000; + +// Reload DVC Compare Byte Valid Generation +assign rel1_byte_mask = (8'h01 & {8{rel1_1hot_opsize[4]}}) | (8'h03 & {8{rel1_1hot_opsize[3]}}) | + (8'h0F & {8{rel1_1hot_opsize[2]}}) | (8'hFF & {8{rel1_1hot_opsize[1]}}); + +assign rel2_byte_mask_d = rel1_byte_mask[(8 - ((2 ** `GPR_WIDTH_ENC)/8)):7]; + +// Reload Bit Mask Generation +assign rel1_bittype_mask = (16'h0001 & {16{rel1_1hot_opsize[4]}}) | (16'h0003 & {16{rel1_1hot_opsize[3]}}) | + (16'h000F & {16{rel1_1hot_opsize[2]}}) | (16'h00FF & {16{rel1_1hot_opsize[1]}}) | + (16'hFFFF & {16{rel1_1hot_opsize[0]}}); + +generate begin : maskGen + genvar b; + for (b=0; b <8; b=b+1) begin : maskGen + assign rel1_optype_mask[b*16:(b*16)+15] = rel1_bittype_mask; + end + end +endgenerate + +assign rel1_msk_data = rel1_rot_data & rel1_optype_mask; + +// Reload Algebraic Sign Extension +assign lh_algebraic = rel1_1hot_opsize[3] & ldq_rel1_algebraic; +assign lw_algebraic = rel1_1hot_opsize[2] & ldq_rel1_algebraic; +assign lh_algebraic_msk = {48{rel1_alg_bit}}; +assign lw_algebraic_msk = {{32{rel1_alg_bit}}, 16'h0000}; + +assign rel1_algebraic_msk = (lh_algebraic_msk & {48{lh_algebraic}}) | (lw_algebraic_msk & {48{lw_algebraic}}); + +// Swizzle Data to a proper format +generate begin : swzlData + genvar t; + for (t=0; t<16; t=t+1) begin : swzlData + assign rel1_swzl_data[t*8:(t*8)+7] = {rel1_msk_data[t], rel1_msk_data[t+16], rel1_msk_data[t+32], rel1_msk_data[t+48], + rel1_msk_data[t+64], rel1_msk_data[t+80], rel1_msk_data[t+96], rel1_msk_data[t+112]}; + end + end +endgenerate + +assign rel1_algebraic_msk_data = {rel1_swzl_data[0:63], (rel1_swzl_data[64:111] | rel1_algebraic_msk), rel1_swzl_data[112:127]}; +assign rel2_rot_data_d = rel1_algebraic_msk_data; + +// ############################################################################################# +// RELOAD DEBUG Data Compare +// ############################################################################################# + +assign rel2_dvc1_val_d = ldq_rel1_gpr_val & ldq_rel1_dvc1_en; +assign rel2_dvc2_val_d = ldq_rel1_gpr_val & ldq_rel1_dvc2_en; + +// Reload Data Compare +generate begin : dvcCmpRl + genvar t; + for (t = 0; t <= ((2 ** `GPR_WIDTH_ENC)/8) - 1; t = t + 1) begin : dvcCmpRl + assign rel2_dvc1_cmp[t] = (rel2_rot_data_q[(128 - (2 ** `GPR_WIDTH_ENC)) + t * 8:(128 - (2 ** `GPR_WIDTH_ENC)) + ((t * 8) + 7)] == + ctl_lsq_spr_dvc1_dbg[(64 - (2 ** `GPR_WIDTH_ENC)) + t * 8:(64 - (2 ** `GPR_WIDTH_ENC)) + ((t * 8) + 7)]) & rel2_byte_mask_q[t]; + assign rel2_dvc2_cmp[t] = (rel2_rot_data_q[(128 - (2 ** `GPR_WIDTH_ENC)) + t * 8:(128 - (2 ** `GPR_WIDTH_ENC)) + ((t * 8) + 7)] == + ctl_lsq_spr_dvc2_dbg[(64 - (2 ** `GPR_WIDTH_ENC)) + t * 8:(64 - (2 ** `GPR_WIDTH_ENC)) + ((t * 8) + 7)]) & rel2_byte_mask_q[t]; + end + end +endgenerate + +// Thread Select + +always @(*) begin: relTid + reg [0:1] dvc1m; + reg [0:1] dvc2m; + reg [8-(2**`GPR_WIDTH_ENC)/8:7] dvc1be; + reg [8-(2**`GPR_WIDTH_ENC)/8:7] dvc2be; + + //(* analysis_not_referenced="true" *) + + integer tid; + dvc1m = {2{1'b0}}; + dvc2m = {2{1'b0}}; + dvc1be = {(2**`GPR_WIDTH_ENC)/8{1'b0}}; + dvc2be = {(2**`GPR_WIDTH_ENC)/8{1'b0}}; + for (tid=0; tid<`THREADS; tid=tid+1) begin + dvc1m = (ctl_lsq_spr_dbcr2_dvc1m_int[tid] & { 2{ldq_rel2_thrd_id[tid]}}) | dvc1m; + dvc2m = (ctl_lsq_spr_dbcr2_dvc2m_int[tid] & { 2{ldq_rel2_thrd_id[tid]}}) | dvc2m; + dvc1be = (ctl_lsq_spr_dbcr2_dvc1be_int[tid][8-(2**`GPR_WIDTH_ENC)/8:7] & {(2**`GPR_WIDTH_ENC)/8{ldq_rel2_thrd_id[tid]}}) | dvc1be; + dvc2be = (ctl_lsq_spr_dbcr2_dvc2be_int[tid][8-(2**`GPR_WIDTH_ENC)/8:7] & {(2**`GPR_WIDTH_ENC)/8{ldq_rel2_thrd_id[tid]}}) | dvc2be; + end + spr_dbcr2_dvc1m = dvc1m; + spr_dbcr2_dvc2m = dvc2m; + spr_dbcr2_dvc1be = dvc1be; + spr_dbcr2_dvc2be = dvc2be; +end + + +lq_spr_dvccmp #(.REGSIZE(2**`GPR_WIDTH_ENC)) dvc1Rel( + .en(rel2_dvc1_val_q), + .en00(1'b0), + .cmp(rel2_dvc1_cmp), + .dvcm(spr_dbcr2_dvc1m), + .dvcbe(spr_dbcr2_dvc1be), + .dvc_cmpr(rel2_dvc1r_cmpr) +); + + +lq_spr_dvccmp #(.REGSIZE(2**`GPR_WIDTH_ENC)) dvc2Rel( + .en(rel2_dvc2_val_q), + .en00(1'b0), + .cmp(rel2_dvc2_cmp), + .dvcm(spr_dbcr2_dvc2m), + .dvcbe(spr_dbcr2_dvc2be), + .dvc_cmpr(rel2_dvc2r_cmpr) +); + +// ############################################################################################# +// Outputs +// ############################################################################################# + +assign ldq_rel2_rot_data = rel2_rot_data_q; +assign ldq_rel2_dvc = {rel2_dvc1r_cmpr, rel2_dvc2r_cmpr}; + +// ############################################################################################# +// Registers +// ############################################################################################# + + +tri_rlmreg_p #(.WIDTH((2**`GPR_WIDTH_ENC)/8), .INIT(0), .NEEDS_SRESET(1)) rel2_byte_mask_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ldq_rel1_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rel2_byte_mask_offset:rel2_byte_mask_offset + ((2**`GPR_WIDTH_ENC)/8) - 1]), + .scout(sov[rel2_byte_mask_offset:rel2_byte_mask_offset + ((2**`GPR_WIDTH_ENC)/8) - 1]), + .din(rel2_byte_mask_d), + .dout(rel2_byte_mask_q) +); + + +tri_rlmreg_p #(.WIDTH(128), .INIT(0), .NEEDS_SRESET(1)) rel2_rot_data_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ldq_rel1_stg_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rel2_rot_data_offset:rel2_rot_data_offset + 128 - 1]), + .scout(sov[rel2_rot_data_offset:rel2_rot_data_offset + 128 - 1]), + .din(rel2_rot_data_d), + .dout(rel2_rot_data_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel2_dvc1_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rel2_dvc1_val_offset]), + .scout(sov[rel2_dvc1_val_offset]), + .din(rel2_dvc1_val_d), + .dout(rel2_dvc1_val_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel2_dvc2_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rel2_dvc2_val_offset]), + .scout(sov[rel2_dvc2_val_offset]), + .din(rel2_dvc2_val_d), + .dout(rel2_dvc2_val_q) +); + +assign siv[0:scan_right] = {sov[1:scan_right], scan_in}; +assign scan_out = sov[0]; + +endmodule diff --git a/dev/verilog/work/lq_lsq.v b/dev/verilog/work/lq_lsq.v new file mode 100755 index 0000000..7462e33 --- /dev/null +++ b/dev/verilog/work/lq_lsq.v @@ -0,0 +1,3757 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +// Description: XU LSU L2 Command Queue +// +//***************************************************************************** + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" + +module lq_lsq( + rv_lq_rv1_i0_vld, + rv_lq_rv1_i0_ucode_preissue, + rv_lq_rv1_i0_s3_t, + rv_lq_rv1_i0_isLoad, + rv_lq_rv1_i0_isStore, + rv_lq_rv1_i0_itag, + rv_lq_rv1_i0_rte_lq, + rv_lq_rv1_i0_rte_sq, + rv_lq_rv1_i1_vld, + rv_lq_rv1_i1_ucode_preissue, + rv_lq_rv1_i1_s3_t, + rv_lq_rv1_i1_isLoad, + rv_lq_rv1_i1_isStore, + rv_lq_rv1_i1_itag, + rv_lq_rv1_i1_rte_lq, + rv_lq_rv1_i1_rte_sq, + xu1_lq_ex2_stq_val, + xu1_lq_ex2_stq_itag, + xu1_lq_ex2_stq_dvc1_cmp, + xu1_lq_ex2_stq_dvc2_cmp, + ctl_lsq_ex4_xu1_data, + xu1_lq_ex3_illeg_lswx, + xu1_lq_ex3_strg_noop, + xu_lq_axu_ex_stq_val, + xu_lq_axu_ex_stq_itag, + xu_lq_axu_exp1_stq_data, + rv_lq_vld, + rv_lq_isLoad, + rv_lq_rvs_empty, + ctl_lsq_rv1_dir_rd_val, + ctl_lsq_ex2_streq_val, + ctl_lsq_ex2_itag, + ctl_lsq_ex2_thrd_id, + ctl_lsq_ex3_ldreq_val, + ctl_lsq_ex3_wchkall_val, + ctl_lsq_ex3_pfetch_val, + ctl_lsq_ex3_byte_en, + ctl_lsq_ex3_p_addr, + ctl_lsq_ex3_thrd_id, + ctl_lsq_ex3_algebraic, + ctl_lsq_ex3_opsize, + ctl_lsq_ex4_ldreq_val, + ctl_lsq_ex4_binvreq_val, + ctl_lsq_ex4_streq_val, + ctl_lsq_ex4_othreq_val, + ctl_lsq_ex4_p_addr, + ctl_lsq_ex4_dReq_val, + ctl_lsq_ex4_gath_load, + ctl_lsq_ex4_send_l2, + ctl_lsq_ex4_has_data, + ctl_lsq_ex4_cline_chk, + ctl_lsq_ex4_wimge, + ctl_lsq_ex4_byte_swap, + ctl_lsq_ex4_is_sync, + ctl_lsq_ex4_all_thrd_chk, + ctl_lsq_ex4_is_icbi, + ctl_lsq_ex4_watch_clr, + ctl_lsq_ex4_watch_clr_all, + ctl_lsq_ex4_mtspr_trace, + ctl_lsq_ex4_is_resv, + ctl_lsq_ex4_is_mfgpr, + ctl_lsq_ex4_is_icswxr, + ctl_lsq_ex4_is_store, + ctl_lsq_ex4_is_inval_op, + ctl_lsq_ex4_is_cinval, + ctl_lsq_ex5_lock_clr, + ctl_lsq_ex5_lock_set, + ctl_lsq_ex5_watch_set, + ctl_lsq_ex5_tgpr, + ctl_lsq_ex5_axu_val, + ctl_lsq_ex5_is_epid, + ctl_lsq_ex5_usr_def, + ctl_lsq_ex5_drop_rel, + ctl_lsq_ex5_flush_req, + ctl_lsq_ex5_flush_pfetch, + ctl_lsq_ex5_cmmt_events, + ctl_lsq_ex5_perf_val0, + ctl_lsq_ex5_perf_sel0, + ctl_lsq_ex5_perf_val1, + ctl_lsq_ex5_perf_sel1, + ctl_lsq_ex5_perf_val2, + ctl_lsq_ex5_perf_sel2, + ctl_lsq_ex5_perf_val3, + ctl_lsq_ex5_perf_sel3, + ctl_lsq_ex5_not_touch, + ctl_lsq_ex5_class_id, + ctl_lsq_ex5_dvc, + ctl_lsq_ex5_dacrw, + ctl_lsq_ex5_ttype, + ctl_lsq_ex5_l_fld, + ctl_lsq_ex5_load_hit, + lsq_ctl_ex6_ldq_events, + lsq_ctl_ex6_stq_events, + lsq_perv_ex7_events, + lsq_perv_ldq_events, + lsq_perv_stq_events, + lsq_perv_odq_events, + ctl_lsq_ex6_ldh_dacrw, + ctl_lsq_stq3_icswx_data, + ctl_lsq_spr_dvc1_dbg, + ctl_lsq_spr_dvc2_dbg, + ctl_lsq_spr_dbcr2_dvc1m, + ctl_lsq_spr_dbcr2_dvc1be, + ctl_lsq_spr_dbcr2_dvc2m, + ctl_lsq_spr_dbcr2_dvc2be, + ctl_lsq_dbg_int_en, + ctl_lsq_ldp_idle, + ctl_lsq_spr_lsucr0_b2b, + ctl_lsq_spr_lsucr0_lge, + ctl_lsq_spr_lsucr0_lca, + ctl_lsq_spr_lsucr0_sca, + ctl_lsq_spr_lsucr0_dfwd, + ctl_lsq_pf_empty, + dir_arr_wr_enable, + dir_arr_wr_way, + dir_arr_wr_addr, + dir_arr_wr_data, + dir_arr_rd_data1, + xu_lq_spr_xucr0_cls, + xu_lq_spr_xucr0_cred, + iu_lq_spr_iucr0_icbi_ack, + dat_lsq_stq4_128data, + iu_lq_request, + iu_lq_cTag, + iu_lq_ra, + iu_lq_wimge, + iu_lq_userdef, + lq_iu_icbi_val, + lq_iu_icbi_addr, + iu_lq_icbi_complete, + lq_iu_ici_val, + mm_lq_lsu_req, + mm_lq_lsu_ttype, + mm_lq_lsu_wimge, + mm_lq_lsu_u, + mm_lq_lsu_addr, + mm_lq_lsu_lpid, + mm_lq_lsu_gs, + mm_lq_lsu_ind, + mm_lq_lsu_lbit, + mm_lq_lsu_lpidr, + lq_mm_lsu_token, + lq_mm_lmq_stq_empty, + lq_xu_quiesce, + lq_pc_ldq_quiesce, + lq_pc_stq_quiesce, + lq_pc_pfetch_quiesce, + iu_lq_cp_flush, + iu_lq_recirc_val, + iu_lq_cp_next_itag, + iu_lq_i0_completed, + iu_lq_i0_completed_itag, + iu_lq_i1_completed, + iu_lq_i1_completed_itag, + xu_lq_xer_cp_rd, + an_ac_sync_ack, + an_ac_stcx_complete, + an_ac_stcx_pass, + an_ac_icbi_ack, + an_ac_icbi_ack_thread, + an_ac_coreid, + an_ac_req_ld_pop, + an_ac_req_st_pop, + an_ac_req_st_gather, + an_ac_reld_data_vld, + an_ac_reld_core_tag, + an_ac_reld_qw, + an_ac_reld_data, + an_ac_reld_data_coming, + an_ac_reld_ditc, + an_ac_reld_crit_qw, + an_ac_reld_l1_dump, + an_ac_reld_ecc_err, + an_ac_reld_ecc_err_ue, + an_ac_back_inv, + an_ac_back_inv_addr, + an_ac_back_inv_target_bit1, + an_ac_back_inv_target_bit3, + an_ac_back_inv_target_bit4, + an_ac_req_spare_ctrl_a1, + lq_iu_credit_free, + sq_iu_credit_free, + lsq_ctl_rv_hold_all, + lsq_ctl_rv_set_hold, + lsq_ctl_rv_clr_hold, + lsq_ctl_stq_release_itag_vld, + lsq_ctl_stq_release_itag, + lsq_ctl_stq_release_tid, + lsq_ctl_stq_cpl_ready, + lsq_ctl_stq_cpl_ready_itag, + lsq_ctl_stq_cpl_ready_tid, + lsq_ctl_stq_n_flush, + lsq_ctl_stq_np1_flush, + lsq_ctl_stq_exception_val, + lsq_ctl_stq_exception, + lsq_ctl_stq_dacrw, + ctl_lsq_stq_cpl_blk, + ctl_lsq_ex_pipe_full, + lsq_ctl_ex5_ldq_restart, + lsq_ctl_ex5_stq_restart, + lsq_ctl_ex5_stq_restart_miss, + lsq_ctl_ex5_fwd_val, + lsq_ctl_ex5_fwd_data, + lsq_ctl_sync_in_stq, + lsq_ctl_sync_done, + lq1_iu_execute_vld, + lq1_iu_itag, + lq1_iu_exception_val, + lq1_iu_exception, + lq1_iu_n_flush, + lq1_iu_np1_flush, + lq1_iu_dacr_type, + lq1_iu_dacrw, + lq1_iu_perf_events, + lsq_dat_stq1_stg_act, + lsq_dat_rel1_data_val, + lsq_dat_rel1_qw, + lsq_dat_stq1_val, + lsq_dat_stq1_mftgpr_val, + lsq_dat_stq1_store_val, + lsq_dat_stq1_byte_en, + lsq_dat_stq1_op_size, + lsq_dat_stq1_addr, + lsq_dat_stq1_le_mode, + lsq_dat_stq2_blk_req, + lsq_dat_stq2_store_data, + lsq_ctl_stq1_stg_act, + lsq_ctl_oldest_tid, + lsq_ctl_oldest_itag, + lsq_ctl_rel1_clr_val, + lsq_ctl_rel1_set_val, + lsq_ctl_rel1_data_val, + lsq_ctl_rel1_back_inv, + lsq_ctl_rel1_tag, + lsq_ctl_rel1_classid, + lsq_ctl_rel1_lock_set, + lsq_ctl_rel1_watch_set, + lsq_ctl_rel2_blk_req, + lsq_ctl_stq2_blk_req, + lsq_ctl_rel2_upd_val, + lsq_ctl_rel2_data, + lsq_ctl_rel3_l1dump_val, + lsq_ctl_rel3_clr_relq, + ctl_lsq_stq4_perr_reject, + lsq_ctl_stq1_val, + lsq_ctl_stq1_mftgpr_val, + lsq_ctl_stq1_mfdpf_val, + lsq_ctl_stq1_mfdpa_val, + lsq_ctl_stq1_thrd_id, + lsq_ctl_rel1_thrd_id, + lsq_ctl_stq1_store_val, + lsq_ctl_stq1_lock_clr, + lsq_ctl_stq1_watch_clr, + lsq_ctl_stq1_l_fld, + lsq_ctl_stq1_inval, + lsq_ctl_stq1_dci_val, + lsq_ctl_stq1_addr, + lsq_ctl_stq1_ci, + lsq_ctl_stq1_axu_val, + lsq_ctl_stq1_epid_val, + lsq_ctl_stq4_xucr0_cul, + lsq_ctl_stq5_itag, + lsq_ctl_stq5_tgpr, + lsq_ctl_rel1_gpr_val, + lsq_ctl_rel1_ta_gpr, + lsq_ctl_rel1_upd_gpr, + lsq_ctl_stq1_resv, + lsq_ctl_ex3_strg_val, + lsq_ctl_ex3_strg_noop, + lsq_ctl_ex3_illeg_lswx, + lsq_ctl_ex3_ct_val, + lsq_ctl_ex3_be_ct, + lsq_ctl_ex3_le_ct, + odq_pf_report_tid, + odq_pf_report_itag, + odq_pf_resolved, + lq_xu_cr_l2_we, + lq_xu_cr_l2_wa, + lq_xu_cr_l2_wd, + lq_xu_axu_rel_le, + lsq_ctl_rv0_back_inv, + lsq_ctl_rv1_back_inv_addr, + lq_rv_itag2_vld, + lq_rv_itag2, + lq_xu_dbell_val, + lq_xu_dbell_type, + lq_xu_dbell_brdcast, + lq_xu_dbell_lpid_match, + lq_xu_dbell_pirtag, + ac_an_req_pwr_token, + ac_an_req, + ac_an_req_ra, + ac_an_req_ttype, + ac_an_req_thread, + ac_an_req_wimg_w, + ac_an_req_wimg_i, + ac_an_req_wimg_m, + ac_an_req_wimg_g, + ac_an_req_endian, + ac_an_req_user_defined, + ac_an_req_spare_ctrl_a0, + ac_an_req_ld_core_tag, + ac_an_req_ld_xfr_len, + ac_an_st_byte_enbl, + ac_an_st_data, + ac_an_st_data_pwr_token, + pc_lq_inj_relq_parity, + lq_pc_err_relq_parity, + lq_pc_err_invld_reld, + lq_pc_err_l2intrf_ecc, + lq_pc_err_l2intrf_ue, + lq_pc_err_l2credit_overrun, + vcs, + vdd, + gnd, + nclk, + sg_2, + fce_2, + func_sl_thold_2, + func_nsl_thold_2, + func_slp_sl_thold_2, + pc_lq_ccflush_dc, + clkoff_dc_b, + d_mode_dc, + delay_lclkr_dc, + mpw1_dc_b, + mpw2_dc_b, + g8t_clkoff_dc_b, + g8t_d_mode_dc, + g8t_delay_lclkr_dc, + g8t_mpw1_dc_b, + g8t_mpw2_dc_b, + abst_sl_thold_2, + time_sl_thold_2, + ary_nsl_thold_2, + repr_sl_thold_2, + bolt_sl_thold_2, + bo_enable_2, + an_ac_scan_dis_dc_b, + an_ac_scan_diag_dc, + an_ac_lbist_ary_wrt_thru_dc, + pc_lq_abist_ena_dc, + pc_lq_abist_raw_dc_b, + pc_lq_bo_unload, + pc_lq_bo_repair, + pc_lq_bo_reset, + pc_lq_bo_shdata, + pc_lq_bo_select, + lq_pc_bo_fail, + lq_pc_bo_diagout, + pc_lq_abist_wl64_comp_ena, + pc_lq_abist_g8t_wenb, + pc_lq_abist_g8t1p_renb_0, + pc_lq_abist_g8t_dcomp, + pc_lq_abist_g8t_bw_1, + pc_lq_abist_g8t_bw_0, + pc_lq_abist_di_0, + pc_lq_abist_waddr_0, + pc_lq_abist_raddr_0, + abst_scan_in, + time_scan_in, + repr_scan_in, + func_scan_in, + abst_scan_out, + time_scan_out, + repr_scan_out, + func_scan_out +); +// parameter EXPAND_TYPE = 2; // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) +// parameter GPR_WIDTH_ENC = 6; // Register Mode 5 = 32bit, 6 = 64bit +// parameter LDSTQ_ENTRIES = 16; // Order Queue Size +// parameter LDSTQ_ENTRIES_ENC = 4; // Order Queue Size Encoded +// parameter LMQ_ENTRIES = 8; // Loadmiss Queue Size +// parameter LMQ_ENTRIES_ENC = 3; // Loadmiss Queue Size Encoded +// parameter LGQ_ENTRIES = 8; // Load Gather Queue Size +// parameter STQ_ENTRIES = 12; // Store Queue Size +// parameter STQ_ENTRIES_ENC = 4; // Store Queue Size Encoded +// parameter STQ_FWD_ENTRIES = 4; // number of stq entries that can be forwarded from +// parameter STQ_DATA_SIZE = 64; // 64 or 128 Bit store data sizes supported +// parameter IUQ_ENTRIES = 4; // Instruction Fetch Queue Size +// parameter MMQ_ENTRIES = 1; // Memory Management Queue Size +// parameter ITAG_SIZE_ENC = 7; // ITAG size +// parameter CR_POOL_ENC = 5; // Encode of CR rename pool size +// parameter GPR_POOL_ENC = 6; +// parameter AXU_SPARE_ENC = 3; +// parameter THREADS_POOL_ENC = 1; +// parameter DC_SIZE = 15; // 14 => 16K L1D$, 15 => 32K L1D +// parameter CL_SIZE = 6; // 6 => 64B CLINE, 7 => 128B CLINE +// parameter LOAD_CREDITS = 8; +// parameter STORE_CREDITS = 32; +// parameter THREADS = 2; // Number of Threads in the System +// parameter CR_WIDTH = 4; +// parameter REAL_IFAR_WIDTH = 42; // real addressing bits + parameter WAYDATASIZE = 34; // TagSize + Parity Bits + + // IU interface to RV for instruction insertion + // port 0 + input [0:`THREADS-1] rv_lq_rv1_i0_vld; + input rv_lq_rv1_i0_ucode_preissue; + input [0:2] rv_lq_rv1_i0_s3_t; + input rv_lq_rv1_i0_isLoad; + input rv_lq_rv1_i0_isStore; + input [0:`ITAG_SIZE_ENC-1] rv_lq_rv1_i0_itag; + input rv_lq_rv1_i0_rte_lq; + input rv_lq_rv1_i0_rte_sq; + + // port 1 + input [0:`THREADS-1] rv_lq_rv1_i1_vld; + input rv_lq_rv1_i1_ucode_preissue; + input [0:2] rv_lq_rv1_i1_s3_t; + input rv_lq_rv1_i1_isLoad; + input rv_lq_rv1_i1_isStore; + input [0:`ITAG_SIZE_ENC-1] rv_lq_rv1_i1_itag; + input rv_lq_rv1_i1_rte_lq; + input rv_lq_rv1_i1_rte_sq; + + // FXU0 Data interface + input [0:`THREADS-1] xu1_lq_ex2_stq_val; + input [0:`ITAG_SIZE_ENC-1] xu1_lq_ex2_stq_itag; + input [(64-(2**`GPR_WIDTH_ENC))/8:7] xu1_lq_ex2_stq_dvc1_cmp; + input [(64-(2**`GPR_WIDTH_ENC))/8:7] xu1_lq_ex2_stq_dvc2_cmp; + input [64-(2**`GPR_WIDTH_ENC):63] ctl_lsq_ex4_xu1_data; + input xu1_lq_ex3_illeg_lswx; + input xu1_lq_ex3_strg_noop; + + // AXU Data interface + input [0:`THREADS-1] xu_lq_axu_ex_stq_val; + input [0:`ITAG_SIZE_ENC-1] xu_lq_axu_ex_stq_itag; + input [(128-`STQ_DATA_SIZE):127] xu_lq_axu_exp1_stq_data; + + // RV1 RV Issue Valid + input [0:`THREADS-1] rv_lq_vld; + input rv_lq_isLoad; + + // RV is empty indicator + input [0:`THREADS-1] rv_lq_rvs_empty; + + // SPR Directory Read Valid + input ctl_lsq_rv1_dir_rd_val; + + // Execution Pipe Outputs + input [0:`THREADS-1] ctl_lsq_ex2_streq_val; + input [0:`ITAG_SIZE_ENC-1] ctl_lsq_ex2_itag; + input [0:`THREADS-1] ctl_lsq_ex2_thrd_id; + input [0:`THREADS-1] ctl_lsq_ex3_ldreq_val; + input [0:`THREADS-1] ctl_lsq_ex3_wchkall_val; + input ctl_lsq_ex3_pfetch_val; + input [0:15] ctl_lsq_ex3_byte_en; + input [58:63] ctl_lsq_ex3_p_addr; + input [0:`THREADS-1] ctl_lsq_ex3_thrd_id; + input ctl_lsq_ex3_algebraic; + input [0:2] ctl_lsq_ex3_opsize; + input ctl_lsq_ex4_ldreq_val; + input ctl_lsq_ex4_binvreq_val; + input ctl_lsq_ex4_streq_val; + input ctl_lsq_ex4_othreq_val; + input [64-`REAL_IFAR_WIDTH:57] ctl_lsq_ex4_p_addr; + input ctl_lsq_ex4_dReq_val; + input ctl_lsq_ex4_gath_load; + input ctl_lsq_ex4_send_l2; + input ctl_lsq_ex4_has_data; + input ctl_lsq_ex4_cline_chk; + input [0:4] ctl_lsq_ex4_wimge; + input ctl_lsq_ex4_byte_swap; + input ctl_lsq_ex4_is_sync; + input ctl_lsq_ex4_all_thrd_chk; + input ctl_lsq_ex4_is_icbi; + input ctl_lsq_ex4_watch_clr; + input ctl_lsq_ex4_watch_clr_all; + input ctl_lsq_ex4_mtspr_trace; + input ctl_lsq_ex4_is_resv; + input ctl_lsq_ex4_is_mfgpr; + input ctl_lsq_ex4_is_icswxr; + input ctl_lsq_ex4_is_store; + input ctl_lsq_ex4_is_inval_op; + input ctl_lsq_ex4_is_cinval; + input ctl_lsq_ex5_lock_clr; + input ctl_lsq_ex5_lock_set; + input ctl_lsq_ex5_watch_set; + input [0:`AXU_SPARE_ENC+`GPR_POOL_ENC+`THREADS_POOL_ENC-1] ctl_lsq_ex5_tgpr; + input ctl_lsq_ex5_axu_val; + input ctl_lsq_ex5_is_epid; + input [0:3] ctl_lsq_ex5_usr_def; + input ctl_lsq_ex5_drop_rel; + input ctl_lsq_ex5_flush_req; // Flush request from LDQ/STQ + input ctl_lsq_ex5_flush_pfetch; // Flush Prefetch in EX5 + input [0:10] ctl_lsq_ex5_cmmt_events; + input ctl_lsq_ex5_perf_val0; + input [0:3] ctl_lsq_ex5_perf_sel0; + input ctl_lsq_ex5_perf_val1; + input [0:3] ctl_lsq_ex5_perf_sel1; + input ctl_lsq_ex5_perf_val2; + input [0:3] ctl_lsq_ex5_perf_sel2; + input ctl_lsq_ex5_perf_val3; + input [0:3] ctl_lsq_ex5_perf_sel3; + input ctl_lsq_ex5_not_touch; + input [0:1] ctl_lsq_ex5_class_id; + input [0:1] ctl_lsq_ex5_dvc; + input [0:3] ctl_lsq_ex5_dacrw; + input [0:5] ctl_lsq_ex5_ttype; + input [0:1] ctl_lsq_ex5_l_fld; + input ctl_lsq_ex5_load_hit; + output [0:3] lsq_ctl_ex6_ldq_events; // LDQ Pipeline Performance Events + output [0:1] lsq_ctl_ex6_stq_events; // LDQ Pipeline Performance Events + output [0:`THREADS-1] lsq_perv_ex7_events; // LDQ Pipeline Performance Events + output [0:(2*`THREADS)+3] lsq_perv_ldq_events; // REL Pipeline Performance Events + output [0:(3*`THREADS)+2] lsq_perv_stq_events; // STQ Pipeline Performance Events + output [0:4+`THREADS-1] lsq_perv_odq_events; // ODQ Pipeline Performance Events + input [0:3] ctl_lsq_ex6_ldh_dacrw; + + // ICSWX Data to be sent to the L2 + input [0:26] ctl_lsq_stq3_icswx_data; + + // Interface with Local SPR's + input [64-(2**`GPR_WIDTH_ENC):63] ctl_lsq_spr_dvc1_dbg; + input [64-(2**`GPR_WIDTH_ENC):63] ctl_lsq_spr_dvc2_dbg; + input [0:2*`THREADS-1] ctl_lsq_spr_dbcr2_dvc1m; + input [0:8*`THREADS-1] ctl_lsq_spr_dbcr2_dvc1be; + input [0:2*`THREADS-1] ctl_lsq_spr_dbcr2_dvc2m; + input [0:8*`THREADS-1] ctl_lsq_spr_dbcr2_dvc2be; + input [0:`THREADS-1] ctl_lsq_dbg_int_en; + input [0:`THREADS-1] ctl_lsq_ldp_idle; + input ctl_lsq_spr_lsucr0_b2b; // LSUCR0[B2B] Mode enabled + input ctl_lsq_spr_lsucr0_lge; // LSUCR0[LGE] Load Gather Enable + input [0:2] ctl_lsq_spr_lsucr0_lca; + input [0:2] ctl_lsq_spr_lsucr0_sca; + input ctl_lsq_spr_lsucr0_dfwd; // LSUCR0[DFWD] Store Forwarding Disabled + + input [0:`THREADS-1] ctl_lsq_pf_empty; + + //-------------------------------------------------------------- + // Interface with Commit Pipe Directories + //-------------------------------------------------------------- + input [0:3] dir_arr_wr_enable; + input [0:7] dir_arr_wr_way; + input [64-(`DC_SIZE-3):63-`CL_SIZE] dir_arr_wr_addr; + input [64-`REAL_IFAR_WIDTH:64-`REAL_IFAR_WIDTH+WAYDATASIZE-1] dir_arr_wr_data; + output [0:(8*WAYDATASIZE)-1] dir_arr_rd_data1; + + // Data Cache Config + input xu_lq_spr_xucr0_cls; // Data Cache Line Size Mode + input xu_lq_spr_xucr0_cred; // L2 Credit Control + + // ICBI ACK Enable + input iu_lq_spr_iucr0_icbi_ack; + + // STQ4 Data for L2 write + input [0:127] dat_lsq_stq4_128data; + + // Instruction Fetches + input [0:`THREADS-1] iu_lq_request; + input [0:1] iu_lq_cTag; + input [64-`REAL_IFAR_WIDTH:59] iu_lq_ra; + input [0:4] iu_lq_wimge; + input [0:3] iu_lq_userdef; + + // ICBI Interface to IU + output [0:`THREADS-1] lq_iu_icbi_val; + output [64-`REAL_IFAR_WIDTH:57] lq_iu_icbi_addr; + input [0:`THREADS-1] iu_lq_icbi_complete; + + // ICI Interace + output lq_iu_ici_val; + + // MMU instruction interface + input [0:`THREADS-1] mm_lq_lsu_req; // will only pulse when mm has at least 1 token (1 bit per thread) + input [0:1] mm_lq_lsu_ttype; // 0=TLBIVAX, 1=TLBI_COMPLETE, 2=LOAD (tag=01100), 3=LOAD (tag=01101) + input [0:4] mm_lq_lsu_wimge; + input [0:3] mm_lq_lsu_u; // user defined bits + input [64-`REAL_IFAR_WIDTH:63] mm_lq_lsu_addr; // address for TLBI (or loads, maybe), + + // TLBI_COMPLETE is address-less + input [0:7] mm_lq_lsu_lpid; // muxed LPID for the thread of the mmu command + input mm_lq_lsu_gs; + input mm_lq_lsu_ind; + input mm_lq_lsu_lbit; // "L" bit, for large vs. small + input [0:7] mm_lq_lsu_lpidr; + output lq_mm_lsu_token; + output [0:`THREADS-1] lq_xu_quiesce; // Load and Store Queue is empty + output [0:`THREADS-1] lq_pc_ldq_quiesce; + output [0:`THREADS-1] lq_pc_stq_quiesce; + output [0:`THREADS-1] lq_pc_pfetch_quiesce; + output lq_mm_lmq_stq_empty; + + // Zap Machine + input [0:`THREADS-1] iu_lq_cp_flush; + + // Next Itag Completion + input [0:`THREADS-1] iu_lq_recirc_val; + input [0:(`ITAG_SIZE_ENC*`THREADS)-1] iu_lq_cp_next_itag; + + // Complete iTag + input [0:`THREADS-1] iu_lq_i0_completed; + input [0:(`ITAG_SIZE_ENC*`THREADS)-1] iu_lq_i0_completed_itag; + input [0:`THREADS-1] iu_lq_i1_completed; + input [0:(`ITAG_SIZE_ENC*`THREADS)-1] iu_lq_i1_completed_itag; + + // XER Read for long latency CP_NEXT ops stcx./icswx. + input [0:`THREADS-1] xu_lq_xer_cp_rd; + + // Sync Ack + input [0:`THREADS-1] an_ac_sync_ack; + + // Stcx Complete + input [0:`THREADS-1] an_ac_stcx_complete; + input [0:`THREADS-1] an_ac_stcx_pass; + + // ICBI ACK + input an_ac_icbi_ack; + input [0:1] an_ac_icbi_ack_thread; + + // Core ID + input [6:7] an_ac_coreid; + + // L2 Interface Credit Control + input an_ac_req_ld_pop; + input an_ac_req_st_pop; + input an_ac_req_st_gather; + + // L2 Interface Reload + input an_ac_reld_data_vld; + input [0:4] an_ac_reld_core_tag; + input [58:59] an_ac_reld_qw; + input [0:127] an_ac_reld_data; + input an_ac_reld_data_coming; + input an_ac_reld_ditc; + input an_ac_reld_crit_qw; + input an_ac_reld_l1_dump; + input an_ac_reld_ecc_err; + input an_ac_reld_ecc_err_ue; + + // L2 Interface Back Invalidate + input an_ac_back_inv; + input [64-`REAL_IFAR_WIDTH:63] an_ac_back_inv_addr; + input an_ac_back_inv_target_bit1; + input an_ac_back_inv_target_bit3; + input an_ac_back_inv_target_bit4; + input [0:3] an_ac_req_spare_ctrl_a1; + + // Credit Release to IU + output [0:`THREADS-1] lq_iu_credit_free; + output [0:`THREADS-1] sq_iu_credit_free; + + // Reservation Station Hold indicator + output lsq_ctl_rv_hold_all; + + // Reservation station set barrier indicator + output lsq_ctl_rv_set_hold; + output [0:`THREADS-1] lsq_ctl_rv_clr_hold; + + // STCX/ICSWX Itag Complete + output lsq_ctl_stq_release_itag_vld; + output [0:`ITAG_SIZE_ENC-1] lsq_ctl_stq_release_itag; + output [0:`THREADS-1] lsq_ctl_stq_release_tid; + + // Store Queue Completion Report + output lsq_ctl_stq_cpl_ready; + output [0:`ITAG_SIZE_ENC-1] lsq_ctl_stq_cpl_ready_itag; + output [0:`THREADS-1] lsq_ctl_stq_cpl_ready_tid; + output lsq_ctl_stq_n_flush; + output lsq_ctl_stq_np1_flush; + output lsq_ctl_stq_exception_val; + output [0:5] lsq_ctl_stq_exception; + output [0:3] lsq_ctl_stq_dacrw; + input ctl_lsq_stq_cpl_blk; + input ctl_lsq_ex_pipe_full; + + // LOADMISS Queue RESTART indicator + output lsq_ctl_ex5_ldq_restart; + + // Store Queue RESTART indicator + output lsq_ctl_ex5_stq_restart; + output lsq_ctl_ex5_stq_restart_miss; + + // Store Data Forward + output lsq_ctl_ex5_fwd_val; + output [(128-`STQ_DATA_SIZE):127] lsq_ctl_ex5_fwd_data; + + output lsq_ctl_sync_in_stq; + output lsq_ctl_sync_done; + + // Interface to completion + output [0:`THREADS-1] lq1_iu_execute_vld; + output [0:`ITAG_SIZE_ENC-1] lq1_iu_itag; + output lq1_iu_exception_val; + output [0:5] lq1_iu_exception; + output lq1_iu_n_flush; + output lq1_iu_np1_flush; + output lq1_iu_dacr_type; + output [0:3] lq1_iu_dacrw; + output [0:3] lq1_iu_perf_events; + + // RELOAD/COMMIT Data Control + output lsq_dat_stq1_stg_act; + output lsq_dat_rel1_data_val; + output [57:59] lsq_dat_rel1_qw; // RELOAD Data Quadword + output lsq_dat_stq1_val; + output lsq_dat_stq1_mftgpr_val; + output lsq_dat_stq1_store_val; + output [0:15] lsq_dat_stq1_byte_en; + output [0:2] lsq_dat_stq1_op_size; + output [52:63] lsq_dat_stq1_addr; + output lsq_dat_stq1_le_mode; + output lsq_dat_stq2_blk_req; + output [0:143] lsq_dat_stq2_store_data; + + // RELOAD/COMMIT Directory Control + output lsq_ctl_stq1_stg_act; + output [0:`THREADS-1] lsq_ctl_oldest_tid; + output [0:`ITAG_SIZE_ENC-1] lsq_ctl_oldest_itag; + output lsq_ctl_rel1_clr_val; // Reload Data is valid, need to Pick a Way to update + output lsq_ctl_rel1_set_val; // Reload Data is valid for last beat, update Directory Contents and set Valid + output lsq_ctl_rel1_data_val; // Reload Data is Valid, need to update Way in Data Cache + output lsq_ctl_rel1_back_inv; // Reload was Back-Invalidated + output [0:3] lsq_ctl_rel1_tag; // Reload Tag + output [0:1] lsq_ctl_rel1_classid; // Used to index into xucr2 RMT table + output lsq_ctl_rel1_lock_set; // Reload is for a dcbt[st]ls instruction + output lsq_ctl_rel1_watch_set; // Reload is for a ldawx. instruction + output lsq_ctl_rel2_blk_req; // Block Reload due to RV issue or Back-Invalidate + output lsq_ctl_stq2_blk_req; // Block Store due to RV issue + output lsq_ctl_rel2_upd_val; // all 8 data beats have transferred without error, set valid in dir + output [0:127] lsq_ctl_rel2_data; // Reload PRF update data + output lsq_ctl_rel3_l1dump_val; // Reload Complete for an L1_DUMP reload + output lsq_ctl_rel3_clr_relq; // Reload Complete due to an ECC error + input ctl_lsq_stq4_perr_reject; // STQ4 parity error detect, reject STQ2 Commit + output lsq_ctl_stq1_val; + output lsq_ctl_stq1_mftgpr_val; + output lsq_ctl_stq1_mfdpf_val; + output lsq_ctl_stq1_mfdpa_val; + output [0:`THREADS-1] lsq_ctl_stq1_thrd_id; + output [0:`THREADS-1] lsq_ctl_rel1_thrd_id; + output lsq_ctl_stq1_store_val; + output lsq_ctl_stq1_lock_clr; + output lsq_ctl_stq1_watch_clr; + output [0:1] lsq_ctl_stq1_l_fld; + output lsq_ctl_stq1_inval; + output lsq_ctl_stq1_dci_val; + output [64-`REAL_IFAR_WIDTH:63-`CL_SIZE] lsq_ctl_stq1_addr; + output lsq_ctl_stq1_ci; + output lsq_ctl_stq1_axu_val; + output lsq_ctl_stq1_epid_val; + output lsq_ctl_stq4_xucr0_cul; + output [0:`ITAG_SIZE_ENC-1] lsq_ctl_stq5_itag; + output [0:`AXU_SPARE_ENC+`GPR_POOL_ENC+`THREADS_POOL_ENC-1] lsq_ctl_stq5_tgpr; + + // RELOAD Register Control + output lsq_ctl_rel1_gpr_val; // Critical Quadword requires an update of the Regfile + output [0:`AXU_SPARE_ENC+`GPR_POOL_ENC+`THREADS_POOL_ENC-1] lsq_ctl_rel1_ta_gpr; // Reload Target Register + output lsq_ctl_rel1_upd_gpr; // Critical Quadword did not get and ECC error in REL1 + output lsq_ctl_stq1_resv; + + // Illegal LSWX has been determined + output lsq_ctl_ex3_strg_val; // STQ has checked XER valid + output lsq_ctl_ex3_strg_noop; // STQ detected a noop of LSWX/STSWX + output lsq_ctl_ex3_illeg_lswx; // STQ detected illegal form of LSWX + output lsq_ctl_ex3_ct_val; // ICSWX Data is valid + output [0:5] lsq_ctl_ex3_be_ct; // Big Endian Coprocessor Type Select + output [0:5] lsq_ctl_ex3_le_ct; // Little Endian Coprocessor Type Select + + // release itag to pfetch + output [0:`THREADS-1] odq_pf_report_tid; + output [0:`ITAG_SIZE_ENC-1] odq_pf_report_itag; + output odq_pf_resolved; + + // STCX Update + output lq_xu_cr_l2_we; + output [0:`CR_POOL_ENC+`THREADS_POOL_ENC-1] lq_xu_cr_l2_wa; + output [0:`CR_WIDTH-1] lq_xu_cr_l2_wd; + + // PRF update for reloads + output lq_xu_axu_rel_le; + + // Back-Invalidate + output lsq_ctl_rv0_back_inv; + output [64-`REAL_IFAR_WIDTH:63-`CL_SIZE] lsq_ctl_rv1_back_inv_addr; + + // RV Reload Release Dependent ITAGs + output [0:`THREADS-1] lq_rv_itag2_vld; + output [0:`ITAG_SIZE_ENC-1] lq_rv_itag2; + + // Doorbell Interface + output lq_xu_dbell_val; + output [0:4] lq_xu_dbell_type; + output lq_xu_dbell_brdcast; + output lq_xu_dbell_lpid_match; + output [50:63] lq_xu_dbell_pirtag; + + // L2 Interface Outputs + output ac_an_req_pwr_token; + output ac_an_req; + output [64-`REAL_IFAR_WIDTH:63] ac_an_req_ra; + output [0:5] ac_an_req_ttype; + output [0:2] ac_an_req_thread; + output ac_an_req_wimg_w; + output ac_an_req_wimg_i; + output ac_an_req_wimg_m; + output ac_an_req_wimg_g; + output ac_an_req_endian; + output [0:3] ac_an_req_user_defined; + output [0:3] ac_an_req_spare_ctrl_a0; + output [0:4] ac_an_req_ld_core_tag; + output [0:2] ac_an_req_ld_xfr_len; + output [0:31] ac_an_st_byte_enbl; + output [0:255] ac_an_st_data; + output ac_an_st_data_pwr_token; + + // Interface to Pervasive Unit + input pc_lq_inj_relq_parity; // Inject Parity Error on the Reload Data Queue + output lq_pc_err_relq_parity; // Reload Data Queue Parity Error Detected + output lq_pc_err_invld_reld; // Reload detected without Loadmiss waiting for reload or got extra beats for cacheable request + output lq_pc_err_l2intrf_ecc; // Reload detected with an ECC error + output lq_pc_err_l2intrf_ue; // Reload detected with an uncorrectable ECC error + output lq_pc_err_l2credit_overrun; // L2 Credits were Overrun + + // Pervasive + + + inout vcs; + + + inout vdd; + + + inout gnd; + + (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) + + input [0:`NCLK_WIDTH-1] nclk; + input sg_2; + input fce_2; + input func_sl_thold_2; + input func_nsl_thold_2; + input func_slp_sl_thold_2; + input pc_lq_ccflush_dc; + input clkoff_dc_b; + input d_mode_dc; + input delay_lclkr_dc; + input mpw1_dc_b; + input mpw2_dc_b; + input g8t_clkoff_dc_b; + input g8t_d_mode_dc; + input [0:4] g8t_delay_lclkr_dc; + input [0:4] g8t_mpw1_dc_b; + input g8t_mpw2_dc_b; + input abst_sl_thold_2; + input time_sl_thold_2; + input ary_nsl_thold_2; + input repr_sl_thold_2; + input bolt_sl_thold_2; + input bo_enable_2; + input an_ac_scan_dis_dc_b; + input an_ac_scan_diag_dc; + input an_ac_lbist_ary_wrt_thru_dc; + input pc_lq_abist_ena_dc; + input pc_lq_abist_raw_dc_b; + input pc_lq_bo_unload; + input pc_lq_bo_repair; + input pc_lq_bo_reset; + input pc_lq_bo_shdata; + input [8:13] pc_lq_bo_select; + output [8:13] lq_pc_bo_fail; + output [8:13] lq_pc_bo_diagout; + + // G8T ABIST Control + input pc_lq_abist_wl64_comp_ena; + input pc_lq_abist_g8t_wenb; + input pc_lq_abist_g8t1p_renb_0; + input [0:3] pc_lq_abist_g8t_dcomp; + input pc_lq_abist_g8t_bw_1; + input pc_lq_abist_g8t_bw_0; + input [0:3] pc_lq_abist_di_0; + input [4:9] pc_lq_abist_waddr_0; + input [3:8] pc_lq_abist_raddr_0; + + // SCAN Ports + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + input abst_scan_in; + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + input time_scan_in; + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + input repr_scan_in; + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + input [0:6] func_scan_in; + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + output abst_scan_out; + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + output time_scan_out; + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + output repr_scan_out; + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + output [0:6] func_scan_out; + + //-------------------------- + // signals + //-------------------------- + wire spr_xucr0_cls_d; + wire spr_xucr0_cls_q; + wire lsq_l2_pwrToken; + wire lsq_l2_valid; + wire [0:1] lsq_l2_tid; + wire [64-`REAL_IFAR_WIDTH:63] lsq_l2_p_addr; + wire [0:4] lsq_l2_wimge; + wire [0:3] lsq_l2_usrDef; + wire [0:15] lsq_l2_byteEn; + wire [0:5] lsq_l2_ttype; + wire [0:2] lsq_l2_opSize; + wire [0:4] lsq_l2_coreTag; + wire lsq_l2_dataToken; + wire [0:127] lsq_l2_st_data; + wire an_ac_req_ld_pop_d; + wire an_ac_req_ld_pop_q; + wire an_ac_req_st_pop_d; + wire an_ac_req_st_pop_q; + wire an_ac_req_st_gather_d; + wire an_ac_req_st_gather_q; + wire an_ac_reld_data_vld_d; + wire an_ac_reld_data_vld_q; + wire an_ac_reld_data_vld_stg1_d; + wire an_ac_reld_data_vld_stg1_q; + wire [0:4] an_ac_reld_core_tag_d; + wire [0:4] an_ac_reld_core_tag_q; + wire [58:59] an_ac_reld_qw_d; + wire [58:59] an_ac_reld_qw_q; + wire [0:127] an_ac_reld_data_d; + wire [0:127] an_ac_reld_data_q; + wire an_ac_reld_data_coming_d; + wire an_ac_reld_data_coming_q; + wire an_ac_reld_ditc_d; + wire an_ac_reld_ditc_q; + wire an_ac_reld_crit_qw_d; + wire an_ac_reld_crit_qw_q; + wire an_ac_reld_l1_dump_d; + wire an_ac_reld_l1_dump_q; + wire an_ac_reld_ecc_err_d; + wire an_ac_reld_ecc_err_q; + wire an_ac_reld_ecc_err_ue_d; + wire an_ac_reld_ecc_err_ue_q; + wire an_ac_back_inv_d; + wire an_ac_back_inv_q; + wire [64-`REAL_IFAR_WIDTH:63] an_ac_back_inv_addr_d; + wire [64-`REAL_IFAR_WIDTH:63] an_ac_back_inv_addr_q; + wire an_ac_back_inv_target_bit1_d; + wire an_ac_back_inv_target_bit1_q; + wire an_ac_back_inv_target_bit3_d; + wire an_ac_back_inv_target_bit3_q; + wire an_ac_back_inv_target_bit4_d; + wire an_ac_back_inv_target_bit4_q; + wire [0:7] mm_lq_lsu_lpidr_d; + wire [0:7] mm_lq_lsu_lpidr_q; + wire l2_dbell_val_d; + wire l2_dbell_val_q; + wire l2_back_inv_val_d; + wire l2_back_inv_val_q; + wire [64-`REAL_IFAR_WIDTH:63-`CL_SIZE] l2_back_inv_addr; + wire [64-`REAL_IFAR_WIDTH:63-`CL_SIZE] rv1_back_inv_addr_d; + wire [64-`REAL_IFAR_WIDTH:63-`CL_SIZE] rv1_back_inv_addr_q; + wire [0:3] an_ac_req_spare_ctrl_a1_d; + wire [0:3] an_ac_req_spare_ctrl_a1_q; + wire l2_lsq_resp_isComing; + wire l2_lsq_resp_val; + wire [0:4] l2_lsq_resp_cTag; + wire [57:59] l2_lsq_resp_qw; + wire l2_lsq_resp_crit_qw; + wire l2_lsq_resp_l1_dump; + wire [0:127] l2_lsq_resp_data; + wire l2_lsq_resp_ecc_err; + wire l2_lsq_resp_ecc_err_ue; + wire arb_stq_cred_avail; + wire odq_ldq_n_flush; + wire odq_ldq_np1_flush; + wire odq_ldq_resolved; + wire odq_ldq_report_needed; + wire [0:`THREADS-1] odq_ldq_report_tid; + wire [0:3] odq_ldq_report_pEvents; + wire [0:`ITAG_SIZE_ENC-1] odq_ldq_report_itag; + wire [0:3] odq_ldq_report_dacrw; + wire odq_ldq_report_eccue; + wire [0:`THREADS-1] odq_ldq_oldest_ld_tid; + wire [0:`ITAG_SIZE_ENC-1] odq_ldq_oldest_ld_itag; + wire odq_ldq_ex7_pfetch_blk; + wire odq_stq_resolved; + wire [0:`STQ_ENTRIES-1] odq_stq_stTag; + wire [0:`THREADS-1] stq_ldq_empty; + wire arb_ldq_ldq_unit_sel; + wire arb_imq_iuq_unit_sel; + wire arb_imq_mmq_unit_sel; + wire imq_arb_iuq_ld_req_avail; + wire [0:1] imq_arb_iuq_tid; + wire [0:3] imq_arb_iuq_usr_def; + wire [0:4] imq_arb_iuq_wimge; + wire [64-`REAL_IFAR_WIDTH:63] imq_arb_iuq_p_addr; + wire [0:5] imq_arb_iuq_ttype; + wire [0:2] imq_arb_iuq_opSize; + wire [0:4] imq_arb_iuq_cTag; + wire imq_arb_mmq_ld_req_avail; + wire imq_arb_mmq_st_req_avail; + wire [0:1] imq_arb_mmq_tid; + wire [0:3] imq_arb_mmq_usr_def; + wire [0:4] imq_arb_mmq_wimge; + wire [64-`REAL_IFAR_WIDTH:63] imq_arb_mmq_p_addr; + wire [0:5] imq_arb_mmq_ttype; + wire [0:2] imq_arb_mmq_opSize; + wire [0:4] imq_arb_mmq_cTag; + wire [0:15] imq_arb_mmq_st_data; + wire ldq_arb_ld_req_pwrToken; + wire ldq_arb_ld_req_avail; + wire [0:1] ldq_arb_tid; + wire [0:3] ldq_arb_usr_def; + wire [0:4] ldq_arb_wimge; + wire [64-`REAL_IFAR_WIDTH:63] ldq_arb_p_addr; + wire [0:5] ldq_arb_ttype; + wire [0:2] ldq_arb_opsize; + wire [0:4] ldq_arb_cTag; + wire stq_arb_st_req_avail; + wire stq_arb_stq3_cmmt_val; + wire stq_arb_stq3_cmmt_reject; + wire stq_arb_stq3_req_val; + wire [0:1] stq_arb_stq3_tid; + wire [0:3] stq_arb_stq3_usrDef; + wire [0:4] stq_arb_stq3_wimge; + wire [64-`REAL_IFAR_WIDTH:63] stq_arb_stq3_p_addr; + wire [0:5] stq_arb_stq3_ttype; + wire [0:2] stq_arb_stq3_opSize; + wire [0:15] stq_arb_stq3_byteEn; + wire [0:4] stq_arb_stq3_cTag; + wire [0:`LMQ_ENTRIES-1] ldq_stq_ex5_ldm_hit; + wire [0:`LMQ_ENTRIES-1] ldq_stq_ex5_ldm_entry; + wire [0:`LMQ_ENTRIES-1] ldq_stq_ldm_cpl; + wire ldq_stq_stq4_dir_upd; + wire [64-(`DC_SIZE-3):57] ldq_stq_stq4_cclass; + wire [0:`STQ_ENTRIES_ENC-1] stq_odq_i0_stTag; + wire [0:`STQ_ENTRIES_ENC-1] stq_odq_i1_stTag; + wire stq_odq_stq4_stTag_inval; + wire [0:`STQ_ENTRIES_ENC-1] stq_odq_stq4_stTag; + wire odq_stq_ex2_nxt_oldest_val; + wire [0:`STQ_ENTRIES-1] odq_stq_ex2_nxt_oldest_stTag; + wire odq_stq_ex2_nxt_youngest_val; + wire [0:`STQ_ENTRIES-1] odq_stq_ex2_nxt_youngest_stTag; + wire ldq_stq_rel1_blk_store; + wire [0:127] ldq_arb_rel1_data; + wire ldq_arb_rel1_axu_val; + wire [0:2] ldq_arb_rel1_op_size; + wire [64-`REAL_IFAR_WIDTH:63] ldq_arb_rel1_addr; + wire ldq_arb_rel1_ci; + wire ldq_arb_rel1_byte_swap; + wire [0:`THREADS-1] ldq_arb_rel1_thrd_id; + wire ldq_arb_rel2_rdat_sel; + wire [0:143] ldq_arb_rel2_rd_data; + wire [0:143] arb_ldq_rel2_wrt_data; + wire stq_arb_stq1_axu_val; + wire stq_arb_stq1_epid_val; + wire [0:2] stq_arb_stq1_opSize; + wire [64-`REAL_IFAR_WIDTH:63] stq_arb_stq1_p_addr; + wire stq_arb_stq1_wimge_i; + wire [(128-`STQ_DATA_SIZE):127] stq_arb_stq1_store_data; + wire stq_arb_stq1_byte_swap; + wire [0:`THREADS-1] stq_arb_stq1_thrd_id; + wire stq_arb_release_itag_vld; + wire [0:`ITAG_SIZE_ENC-1] stq_arb_release_itag; + wire [0:`THREADS-1] stq_arb_release_tid; + wire ldq_rel2_blk_req; + wire stq_stq2_blk_req; + wire ldq_hold_all_req; + wire stq_hold_all_req; + wire ldq_rv_set_hold; + wire stq_rv_set_hold; + wire [0:`THREADS-1] ldq_rv_clr_hold; + wire [0:`THREADS-1] stq_rv_clr_hold; + wire [0:`THREADS-1] an_ac_sync_ack_d; + wire [0:`THREADS-1] an_ac_sync_ack_q; + wire [0:`THREADS-1] an_ac_stcx_complete_d; + wire [0:`THREADS-1] an_ac_stcx_complete_q; + wire [0:`THREADS-1] an_ac_stcx_pass_d; + wire [0:`THREADS-1] an_ac_stcx_pass_q; + wire an_ac_icbi_ack_d; + wire an_ac_icbi_ack_q; + wire [0:1] an_ac_icbi_ack_thread_d; + wire [0:1] an_ac_icbi_ack_thread_q; + wire [6:7] an_ac_coreid_d; + wire [6:7] an_ac_coreid_q; + wire ldq_odq_vld; + wire ldq_odq_pfetch_vld; + wire ldq_odq_wimge_i; + wire [0:3] ldq_odq_ex6_pEvents; + wire ldq_odq_hit; + wire ldq_odq_fwd; + wire ldq_odq_inv_d; + wire ldq_odq_inv_q; + wire [64-`REAL_IFAR_WIDTH:59] ldq_odq_addr_d; + wire [64-`REAL_IFAR_WIDTH:59] ldq_odq_addr_q; + wire [0:`ITAG_SIZE_ENC-1] ldq_odq_itag_d; + wire [0:`ITAG_SIZE_ENC-1] ldq_odq_itag_q; + wire ldq_odq_cline_chk_d; + wire ldq_odq_cline_chk_q; + wire ldq_odq_upd_val; + wire [0:`ITAG_SIZE_ENC-1] ldq_odq_upd_itag; + wire ldq_odq_upd_nFlush; + wire ldq_odq_upd_np1Flush; + wire [0:`THREADS-1] ldq_odq_upd_tid; + wire [0:3] ldq_odq_upd_dacrw; + wire ldq_odq_upd_eccue; + wire [0:3] ldq_odq_upd_pEvents; + wire ldq_rel2_byte_swap; + wire [0:127] ldq_rel2_data; + wire stq_ldq_ex5_stq_restart; + wire stq_ldq_ex5_stq_restart_miss; + wire stq_ldq_ex5_fwd_val; + wire [0:`ITAG_SIZE_ENC-1] ex3_itag_d; + wire [0:`ITAG_SIZE_ENC-1] ex3_itag_q; + wire [0:`ITAG_SIZE_ENC-1] ex4_itag_d; + wire [0:`ITAG_SIZE_ENC-1] ex4_itag_q; + wire [0:15] ex4_byte_en_d; + wire [0:15] ex4_byte_en_q; + wire [0:15] ex5_byte_en_d; + wire [0:15] ex5_byte_en_q; + wire [64-`REAL_IFAR_WIDTH:63] ex4_p_addr; + wire [58:63] ex4_p_addr_d; + wire [58:63] ex4_p_addr_q; + wire [0:`THREADS-1] ex4_thrd_id_d; + wire [0:`THREADS-1] ex4_thrd_id_q; + wire [0:`THREADS-1] ex5_thrd_id_d; + wire [0:`THREADS-1] ex5_thrd_id_q; + wire [0:`THREADS-1] ex6_thrd_id_d; + wire [0:`THREADS-1] ex6_thrd_id_q; + wire [0:`THREADS-1] ex7_thrd_id_d; + wire [0:`THREADS-1] ex7_thrd_id_q; + wire [0:`THREADS-1] ex4_streq_val; + wire ex3_ldreq_val; + wire ex4_algebraic_d; + wire ex4_algebraic_q; + wire ex5_algebraic_d; + wire ex5_algebraic_q; + wire [0:2] ex4_opsize_d; + wire [0:2] ex4_opsize_q; + wire [0:2] ex5_opsize_d; + wire [0:2] ex5_opsize_q; + wire ex5_dreq_val_d; + wire ex5_dreq_val_q; + wire [64-(`DC_SIZE-3):63-`CL_SIZE] dir_arr_rd_addr1; + wire ldq_arb_rel1_data_sel; + wire ldq_ctl_stq1_stg_act; + wire stq_ctl_stq1_stg_act; + wire ldq_dat_stq1_stg_act; + wire stq_dat_stq1_stg_act; + + wire func_nsl_thold_1; + wire func_sl_thold_1; + wire func_slp_sl_thold_1; + wire sg_1; + wire fce_1; + wire func_nsl_thold_0; + wire func_sl_thold_0; + wire func_slp_sl_thold_0; + wire sg_0; + wire fce_0; + wire func_nsl_thold_0_b; + wire func_sl_thold_0_b; + wire func_slp_sl_thold_0_b; + wire func_nsl_force; + wire func_sl_force; + wire func_slp_sl_force; + wire abst_scan_in_q; + wire [0:2] abst_scan_out_int; + wire [0:2] abst_scan_out_q; + wire time_scan_in_q; + wire [0:1] time_scan_out_int; + wire [0:1] time_scan_out_q; + wire repr_scan_in_q; + wire [0:1] repr_scan_out_int; + wire [0:1] repr_scan_out_q; + wire [0:6] func_scan_in_q; + wire [0:6] func_scan_out_int; + wire [0:6] func_scan_out_q; + wire arb_func_scan_out; + wire [0:24] abist_siv; + wire [0:24] abist_sov; + wire abst_sl_thold_1; + wire time_sl_thold_1; + wire ary_nsl_thold_1; + wire repr_sl_thold_1; + wire bolt_sl_thold_1; + wire abst_sl_thold_0; + wire time_sl_thold_0; + wire ary_nsl_thold_0; + wire repr_sl_thold_0; + wire bolt_sl_thold_0; + wire abst_sl_thold_0_b; + wire abst_sl_force; + wire pc_lq_abist_wl64_comp_ena_q; + wire [3:8] pc_lq_abist_raddr_0_q; + wire pc_lq_abist_g8t_wenb_q; + wire pc_lq_abist_g8t1p_renb_0_q; + wire [0:3] pc_lq_abist_g8t_dcomp_q; + wire pc_lq_abist_g8t_bw_1_q; + wire pc_lq_abist_g8t_bw_0_q; + wire [0:3] pc_lq_abist_di_0_q; + wire [4:9] pc_lq_abist_waddr_0_q; + wire slat_force; + wire abst_slat_thold_b; + wire abst_slat_d2clk; + wire [0:`NCLK_WIDTH-1] abst_slat_lclk; + wire time_slat_thold_b; + wire time_slat_d2clk; + wire [0:`NCLK_WIDTH-1] time_slat_lclk; + wire repr_slat_thold_b; + wire repr_slat_d2clk; + wire [0:`NCLK_WIDTH-1] repr_slat_lclk; + wire func_slat_thold_b; + wire func_slat_d2clk; + wire [0:`NCLK_WIDTH-1] func_slat_lclk; + + wire [0:3] abst_scan_q; + wire [0:3] abst_scan_q_b; + wire [0:2] time_scan_q; + wire [0:2] time_scan_q_b; + wire [0:2] repr_scan_q; + wire [0:2] repr_scan_q_b; + wire [0:13] func_scan_q; + wire [0:13] func_scan_q_b; + + //-------------------------- + // constants + //-------------------------- + + parameter ldq_odq_inv_offset = 0; + parameter ldq_odq_addr_offset = ldq_odq_inv_offset + 1; + parameter ldq_odq_itag_offset = ldq_odq_addr_offset + (`REAL_IFAR_WIDTH-4); + parameter ldq_odq_cline_chk_offset = ldq_odq_itag_offset + `ITAG_SIZE_ENC; + parameter ex3_itag_offset = ldq_odq_cline_chk_offset + 1; + parameter ex4_itag_offset = ex3_itag_offset + `ITAG_SIZE_ENC; + parameter ex4_byte_en_offset = ex4_itag_offset + `ITAG_SIZE_ENC; + parameter ex5_byte_en_offset = ex4_byte_en_offset + 16; + parameter ex4_p_addr_offset = ex5_byte_en_offset + 16; + parameter ex4_thrd_id_offset = ex4_p_addr_offset + 6; + parameter ex5_thrd_id_offset = ex4_thrd_id_offset + `THREADS; + parameter ex6_thrd_id_offset = ex5_thrd_id_offset + `THREADS; + parameter ex7_thrd_id_offset = ex6_thrd_id_offset + `THREADS; + parameter ex4_algebraic_offset = ex7_thrd_id_offset + `THREADS; + parameter ex5_algebraic_offset = ex4_algebraic_offset + 1; + parameter ex4_opsize_offset = ex5_algebraic_offset + 1; + parameter ex5_opsize_offset = ex4_opsize_offset + 3; + parameter ex5_dreq_val_offset = ex5_opsize_offset + 3; + parameter spr_xucr0_cls_offset = ex5_dreq_val_offset + 1; + parameter an_ac_req_ld_pop_offset = spr_xucr0_cls_offset + 1; + parameter an_ac_req_st_pop_offset = an_ac_req_ld_pop_offset + 1; + parameter an_ac_req_st_gather_offset = an_ac_req_st_pop_offset + 1; + parameter an_ac_reld_data_vld_offset = an_ac_req_st_gather_offset + 1; + parameter an_ac_reld_data_vld_stg1_offset = an_ac_reld_data_vld_offset + 1; + parameter an_ac_reld_data_coming_offset = an_ac_reld_data_vld_stg1_offset + 1; + parameter an_ac_reld_ditc_offset = an_ac_reld_data_coming_offset + 1; + parameter an_ac_reld_crit_qw_offset = an_ac_reld_ditc_offset + 1; + parameter an_ac_reld_l1_dump_offset = an_ac_reld_crit_qw_offset + 1; + parameter an_ac_reld_ecc_err_offset = an_ac_reld_l1_dump_offset + 1; + parameter an_ac_reld_ecc_err_ue_offset = an_ac_reld_ecc_err_offset + 1; + parameter an_ac_back_inv_offset = an_ac_reld_ecc_err_ue_offset + 1; + parameter an_ac_back_inv_target_bit1_offset = an_ac_back_inv_offset + 1; + parameter an_ac_back_inv_target_bit3_offset = an_ac_back_inv_target_bit1_offset + 1; + parameter an_ac_back_inv_target_bit4_offset = an_ac_back_inv_target_bit3_offset + 1; + parameter mm_lq_lsu_lpidr_offset = an_ac_back_inv_target_bit4_offset + 1; + parameter l2_dbell_val_offset = mm_lq_lsu_lpidr_offset + 8; + parameter l2_back_inv_val_offset = l2_dbell_val_offset + 1; + parameter rv1_back_inv_addr_offset = l2_back_inv_val_offset + 1; + parameter an_ac_req_spare_ctrl_a1_offset = rv1_back_inv_addr_offset + (63-`CL_SIZE-(64-`REAL_IFAR_WIDTH)+1); + parameter an_ac_reld_core_tag_offset = an_ac_req_spare_ctrl_a1_offset + 4; + parameter an_ac_reld_qw_offset = an_ac_reld_core_tag_offset + 5; + parameter an_ac_reld_data_offset = an_ac_reld_qw_offset + 2; + parameter an_ac_back_inv_addr_offset = an_ac_reld_data_offset + 128; + parameter an_ac_sync_ack_offset = an_ac_back_inv_addr_offset + `REAL_IFAR_WIDTH; + parameter an_ac_stcx_complete_offset = an_ac_sync_ack_offset + `THREADS; + parameter an_ac_stcx_pass_offset = an_ac_stcx_complete_offset + `THREADS; + parameter an_ac_icbi_ack_offset = an_ac_stcx_pass_offset + `THREADS; + parameter an_ac_icbi_ack_thread_offset = an_ac_icbi_ack_offset + 1; + parameter an_ac_coreid_offset = an_ac_icbi_ack_thread_offset + 2; + parameter scan_right = an_ac_coreid_offset + 2 - 1; + + wire [0:scan_right] siv; + wire [0:scan_right] sov; + wire tiup; + wire tidn; + + (* analysis_not_referenced="true" *) + wire unused; + + + //!! Bugspray Include: lq_lsq + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // Inputs + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + assign tiup = 1'b1; + assign tidn = 1'b0; + + assign unused = |abst_scan_q | |abst_scan_q_b | |time_scan_q | |time_scan_q_b | + |repr_scan_q | |repr_scan_q_b | |func_scan_q | |func_scan_q_b; + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // XU Config Bits + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + + // XUCR0[CLS] 128 Byte Cacheline Enabled + // 1 => 128 Byte Cacheline + // 0 => 64 Byte Cacheline + assign spr_xucr0_cls_d = xu_lq_spr_xucr0_cls; + + assign an_ac_sync_ack_d = an_ac_sync_ack; + assign an_ac_stcx_complete_d = an_ac_stcx_complete; + assign an_ac_stcx_pass_d = an_ac_stcx_pass; + assign an_ac_icbi_ack_d = an_ac_icbi_ack; + assign an_ac_icbi_ack_thread_d = an_ac_icbi_ack_thread; + assign an_ac_coreid_d = an_ac_coreid; + assign an_ac_req_ld_pop_d = an_ac_req_ld_pop; + assign an_ac_req_st_pop_d = an_ac_req_st_pop; + assign an_ac_req_st_gather_d = an_ac_req_st_gather; + + assign an_ac_reld_data_vld_d = an_ac_reld_data_vld; + assign an_ac_reld_core_tag_d = an_ac_reld_core_tag; + assign an_ac_reld_qw_d = an_ac_reld_qw; + assign an_ac_reld_data_d = an_ac_reld_data; + assign an_ac_reld_data_coming_d = an_ac_reld_data_coming; + assign an_ac_reld_ditc_d = an_ac_reld_ditc; + assign an_ac_reld_crit_qw_d = an_ac_reld_crit_qw; + assign an_ac_reld_l1_dump_d = an_ac_reld_l1_dump; + assign an_ac_reld_ecc_err_d = an_ac_reld_ecc_err; + assign an_ac_reld_ecc_err_ue_d = an_ac_reld_ecc_err_ue; + + assign an_ac_back_inv_d = an_ac_back_inv; + assign an_ac_back_inv_addr_d = an_ac_back_inv_addr; + assign an_ac_back_inv_target_bit1_d = an_ac_back_inv_target_bit1; + assign an_ac_back_inv_target_bit3_d = an_ac_back_inv_target_bit3; + assign an_ac_back_inv_target_bit4_d = an_ac_back_inv_target_bit4; + assign an_ac_req_spare_ctrl_a1_d = an_ac_req_spare_ctrl_a1; + assign l2_back_inv_val_d = an_ac_back_inv_q & an_ac_back_inv_target_bit1_q; + // Forcing bit (57) to 1 when running in 128Byte cache line mode + assign l2_back_inv_addr = {an_ac_back_inv_addr_q[64 - `REAL_IFAR_WIDTH:63 - `CL_SIZE - 1], (an_ac_back_inv_addr_q[63 - `CL_SIZE] | spr_xucr0_cls_q)}; + assign rv1_back_inv_addr_d = l2_back_inv_addr; + + // Early inputs to LSQ + assign ex3_itag_d = ctl_lsq_ex2_itag; + assign ex4_itag_d = ex3_itag_q; + assign ex4_byte_en_d = ctl_lsq_ex3_byte_en; + assign ex5_byte_en_d = ex4_byte_en_q; + assign ex4_p_addr_d = ctl_lsq_ex3_p_addr; + assign ex4_p_addr = {ctl_lsq_ex4_p_addr, ex4_p_addr_q[58:63]}; + assign ex4_thrd_id_d = ctl_lsq_ex3_thrd_id; + assign ex5_thrd_id_d = ex4_thrd_id_q; + assign ex6_thrd_id_d = ex5_thrd_id_q; + assign ex7_thrd_id_d = ex6_thrd_id_q; + assign ex4_streq_val = ex4_thrd_id_q & {`THREADS{ctl_lsq_ex4_streq_val}}; + assign ex3_ldreq_val = |(ctl_lsq_ex3_ldreq_val); + assign ex4_algebraic_d = ctl_lsq_ex3_algebraic; + assign ex5_algebraic_d = ex4_algebraic_q; + assign ex4_opsize_d = ctl_lsq_ex3_opsize; + assign ex5_opsize_d = ex4_opsize_q; + assign ex5_dreq_val_d = ctl_lsq_ex4_dReq_val; + + // Order Queue Inputs + assign ldq_odq_hit = ctl_lsq_ex5_load_hit | ex5_dreq_val_q | stq_ldq_ex5_fwd_val; + assign ldq_odq_fwd = stq_ldq_ex5_fwd_val; + assign ldq_odq_inv_d = ctl_lsq_ex4_binvreq_val; + assign ldq_odq_addr_d = ex4_p_addr[64 - `REAL_IFAR_WIDTH:59]; + assign ldq_odq_itag_d = ex4_itag_q; + assign ldq_odq_cline_chk_d = ctl_lsq_ex4_cline_chk; + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // DOORBELL DETECT + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + assign mm_lq_lsu_lpidr_d = mm_lq_lsu_lpidr; + assign l2_dbell_val_d = an_ac_back_inv_q & an_ac_back_inv_target_bit4_q; + assign lq_xu_dbell_val = l2_dbell_val_q; + assign lq_xu_dbell_type = an_ac_back_inv_addr_q[32:36]; + assign lq_xu_dbell_brdcast = an_ac_back_inv_addr_q[37]; + assign lq_xu_dbell_lpid_match = (an_ac_back_inv_addr_q[42:49] == mm_lq_lsu_lpidr_q) | ((~(|(an_ac_back_inv_addr_q[42:49])))); + assign lq_xu_dbell_pirtag = an_ac_back_inv_addr_q[50:63]; + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // DIRECTORY ARRAYS + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + assign dir_arr_rd_addr1 = stq_arb_stq1_p_addr[64 - (`DC_SIZE - 3):63 - `CL_SIZE]; + + generate + if (`DC_SIZE == 15 & `CL_SIZE == 6) + begin : dc32Kdir64B + + // number of addressable register in this array + // width of the bus to address all ports (2^portadrbus_width >= addressable_ports) + // bitwidth of ports + // number of ways + tri_64x34_8w_1r1w #(.addressable_ports(64), .addressbus_width(6), .port_bitwidth(WAYDATASIZE), .ways(8)) arr( + // POWER PINS + .vcs(vdd), + .vdd(vdd), + .gnd(gnd), + + // CLOCK AND CLOCKCONTROL PORTS + .nclk(nclk), + .rd_act(stq_ctl_stq1_stg_act), + .wr_act(tiup), + .sg_0(sg_0), + .abst_sl_thold_0(abst_sl_thold_0), + .ary_nsl_thold_0(ary_nsl_thold_0), + .time_sl_thold_0(time_sl_thold_0), + .repr_sl_thold_0(repr_sl_thold_0), + .func_sl_force(func_sl_force), // Does not use Sleep THOLDS, This copy is not active while in sleep mode + .func_sl_thold_0_b(func_sl_thold_0_b), // Does not use Sleep THOLDS, This copy is not active while in sleep mode + .g8t_clkoff_dc_b(g8t_clkoff_dc_b), + .ccflush_dc(pc_lq_ccflush_dc), + .scan_dis_dc_b(an_ac_scan_dis_dc_b), + .scan_diag_dc(an_ac_scan_diag_dc), + .g8t_d_mode_dc(g8t_d_mode_dc), + .g8t_mpw1_dc_b(g8t_mpw1_dc_b), + .g8t_mpw2_dc_b(g8t_mpw2_dc_b), + .g8t_delay_lclkr_dc(g8t_delay_lclkr_dc), + .d_mode_dc(d_mode_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .delay_lclkr_dc(delay_lclkr_dc), + + // ABIST + .wr_abst_act(pc_lq_abist_g8t_wenb_q), + .rd0_abst_act(pc_lq_abist_g8t1p_renb_0_q), + .abist_di(pc_lq_abist_di_0_q), + .abist_bw_odd(pc_lq_abist_g8t_bw_1_q), + .abist_bw_even(pc_lq_abist_g8t_bw_0_q), + .abist_wr_adr(pc_lq_abist_waddr_0_q), + .abist_rd0_adr(pc_lq_abist_raddr_0_q[3:8]), + .tc_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc), + .abist_ena_1(pc_lq_abist_ena_dc), + .abist_g8t_rd0_comp_ena(pc_lq_abist_wl64_comp_ena_q), + .abist_raw_dc_b(pc_lq_abist_raw_dc_b), + .obs0_abist_cmp(pc_lq_abist_g8t_dcomp_q), + + // SCAN PORTS + .abst_scan_in(abst_scan_in_q), + .time_scan_in(time_scan_in_q), + .repr_scan_in(repr_scan_in_q), + .func_scan_in(arb_func_scan_out), + .abst_scan_out(abst_scan_out_int[0]), + .time_scan_out(time_scan_out_int[0]), + .repr_scan_out(repr_scan_out_int[0]), + .func_scan_out(func_scan_out_int[4]), + + // BOLT-ON + .lcb_bolt_sl_thold_0(bolt_sl_thold_0), + .pc_bo_enable_2(bo_enable_2), + .pc_bo_reset(pc_lq_bo_reset), + .pc_bo_unload(pc_lq_bo_unload), + .pc_bo_repair(pc_lq_bo_repair), + .pc_bo_shdata(pc_lq_bo_shdata), + .pc_bo_select(pc_lq_bo_select[10:13]), + .bo_pc_failout(lq_pc_bo_fail[10:13]), + .bo_pc_diagloop(lq_pc_bo_diagout[10:13]), + .tri_lcb_mpw1_dc_b(mpw1_dc_b), + .tri_lcb_mpw2_dc_b(mpw2_dc_b), + .tri_lcb_delay_lclkr_dc(delay_lclkr_dc), + .tri_lcb_clkoff_dc_b(clkoff_dc_b), + .tri_lcb_act_dis_dc(tidn), + + // Write Ports + .write_enable(dir_arr_wr_enable), + .way(dir_arr_wr_way), + .addr_wr(dir_arr_wr_addr), + .data_in(dir_arr_wr_data), + + // Read Ports + .addr_rd_01(dir_arr_rd_addr1), + .addr_rd_23(dir_arr_rd_addr1), + .addr_rd_45(dir_arr_rd_addr1), + .addr_rd_67(dir_arr_rd_addr1), + .data_out(dir_arr_rd_data1) + ); + end + endgenerate + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // ORDER QUEUE + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + + lq_odq odq( + + // IU interface to RV for instruction insertion + // port 0 + .rv_lq_rv1_i0_vld(rv_lq_rv1_i0_vld), + .rv_lq_rv1_i0_ucode_preissue(rv_lq_rv1_i0_ucode_preissue), + .rv_lq_rv1_i0_s3_t(rv_lq_rv1_i0_s3_t), + .rv_lq_rv1_i0_isLoad(rv_lq_rv1_i0_isLoad), + .rv_lq_rv1_i0_isStore(rv_lq_rv1_i0_isStore), + .rv_lq_rv1_i0_itag(rv_lq_rv1_i0_itag), + .rv_lq_rv1_i0_rte_lq(rv_lq_rv1_i0_rte_lq), + .rv_lq_rv1_i0_rte_sq(rv_lq_rv1_i0_rte_sq), + + // port 1 + .rv_lq_rv1_i1_vld(rv_lq_rv1_i1_vld), + .rv_lq_rv1_i1_ucode_preissue(rv_lq_rv1_i1_ucode_preissue), + .rv_lq_rv1_i1_s3_t(rv_lq_rv1_i1_s3_t), + .rv_lq_rv1_i1_isLoad(rv_lq_rv1_i1_isLoad), + .rv_lq_rv1_i1_isStore(rv_lq_rv1_i1_isStore), + .rv_lq_rv1_i1_itag(rv_lq_rv1_i1_itag), + .rv_lq_rv1_i1_rte_lq(rv_lq_rv1_i1_rte_lq), + .rv_lq_rv1_i1_rte_sq(rv_lq_rv1_i1_rte_sq), + + .ldq_odq_vld(ldq_odq_vld), + .ldq_odq_pfetch_vld(ldq_odq_pfetch_vld), + .ldq_odq_tid(ex5_thrd_id_q), + .ldq_odq_wimge_i(ldq_odq_wimge_i), + .ldq_odq_inv(ldq_odq_inv_q), + .ldq_odq_hit(ldq_odq_hit), + .ldq_odq_fwd(ldq_odq_fwd), + .ldq_odq_addr(ldq_odq_addr_q), + .ldq_odq_bytemask(ex5_byte_en_q), + .ldq_odq_itag(ldq_odq_itag_q), + .ldq_odq_cline_chk(ldq_odq_cline_chk_q), + .ldq_odq_ex6_pEvents(ldq_odq_ex6_pEvents), + .ctl_lsq_ex6_ldh_dacrw(ctl_lsq_ex6_ldh_dacrw), + + // Update Order Queue Entry when reload is complete and itag is not resolved + .ldq_odq_upd_val(ldq_odq_upd_val), + .ldq_odq_upd_itag(ldq_odq_upd_itag), + .ldq_odq_upd_nFlush(ldq_odq_upd_nFlush), + .ldq_odq_upd_np1Flush(ldq_odq_upd_np1Flush), + .ldq_odq_upd_tid(ldq_odq_upd_tid), + .ldq_odq_upd_dacrw(ldq_odq_upd_dacrw), + .ldq_odq_upd_eccue(ldq_odq_upd_eccue), + .ldq_odq_upd_pEvents(ldq_odq_upd_pEvents), + + .odq_ldq_n_flush(odq_ldq_n_flush), + .odq_ldq_np1_flush(odq_ldq_np1_flush), + .odq_ldq_resolved(odq_ldq_resolved), + .odq_ldq_report_needed(odq_ldq_report_needed), + .odq_ldq_report_itag(odq_ldq_report_itag), + .odq_ldq_oldest_ld_tid(odq_ldq_oldest_ld_tid), + .odq_ldq_oldest_ld_itag(odq_ldq_oldest_ld_itag), + .odq_ldq_ex7_pfetch_blk(odq_ldq_ex7_pfetch_blk), + .odq_ldq_report_tid(odq_ldq_report_tid), + .odq_ldq_report_dacrw(odq_ldq_report_dacrw), + .odq_ldq_report_eccue(odq_ldq_report_eccue), + .odq_ldq_report_pEvents(odq_ldq_report_pEvents), + .odq_stq_resolved(odq_stq_resolved), + .odq_stq_stTag(odq_stq_stTag), + .lsq_ctl_oldest_tid(lsq_ctl_oldest_tid), + .lsq_ctl_oldest_itag(lsq_ctl_oldest_itag), + + // Age Detection + // need to determine age for this load in ex2 + .ctl_lsq_ex2_thrd_id(ctl_lsq_ex2_thrd_id), + .ctl_lsq_ex2_itag(ctl_lsq_ex2_itag), + + // store tag used when instruction was inserted to store queue + .stq_odq_i0_stTag(stq_odq_i0_stTag), + .stq_odq_i1_stTag(stq_odq_i1_stTag), + + // store tag is committed, remove from order queue and dont compare against it + .stq_odq_stq4_stTag_inval(stq_odq_stq4_stTag_inval), + .stq_odq_stq4_stTag(stq_odq_stq4_stTag), + + // order queue closest oldest store to the ex2 load request + .odq_stq_ex2_nxt_oldest_val(odq_stq_ex2_nxt_oldest_val), + .odq_stq_ex2_nxt_oldest_stTag(odq_stq_ex2_nxt_oldest_stTag), + + // order queue closest youngest store to the ex2 load request + .odq_stq_ex2_nxt_youngest_val(odq_stq_ex2_nxt_youngest_val), + .odq_stq_ex2_nxt_youngest_stTag(odq_stq_ex2_nxt_youngest_stTag), + + // CP_NEXT Itag + .iu_lq_cp_next_itag(iu_lq_cp_next_itag), + + // Commit Report + .iu_lq_i0_completed(iu_lq_i0_completed), + .iu_lq_i0_completed_itag(iu_lq_i0_completed_itag), + .iu_lq_i1_completed(iu_lq_i1_completed), + .iu_lq_i1_completed_itag(iu_lq_i1_completed_itag), + + // Back-Invalidate Valid + .l2_back_inv_val(l2_back_inv_val_q), + .l2_back_inv_addr(l2_back_inv_addr[64 - (`DC_SIZE - 3):63 - `CL_SIZE]), + + // Zap Machine + .iu_lq_cp_flush(iu_lq_cp_flush), + + // return credit to iu + .lq_iu_credit_free(lq_iu_credit_free), + + // mode bit + .xu_lq_spr_xucr0_cls(xu_lq_spr_xucr0_cls), + + // Performance Events + .lsq_perv_odq_events(lsq_perv_odq_events), + + // Pervasive + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .sg_0(sg_0), + .func_sl_thold_0_b(func_sl_thold_0_b), + .func_sl_force(func_sl_force), + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .scan_in(func_scan_in_q[0]), + .scan_out(func_scan_out_int[0]) + ); + + assign odq_pf_resolved = odq_ldq_resolved; + assign odq_pf_report_tid = odq_ldq_report_tid; + assign odq_pf_report_itag = odq_ldq_report_itag; + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // LOADMISS QUEUE + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + lq_ldq ldq( + + // RV1 RV Issue Valid + .rv_lq_vld(rv_lq_vld), + .rv_lq_isLoad(rv_lq_isLoad), + + // RV is empty indicator + .rv_lq_rvs_empty(rv_lq_rvs_empty), + + // SPR Directory Read Valid + .ctl_lsq_rv1_dir_rd_val(ctl_lsq_rv1_dir_rd_val), + + // Back-Invalidate Valid + .l2_back_inv_val(l2_back_inv_val_q), + .l2_back_inv_addr(l2_back_inv_addr[64-`REAL_IFAR_WIDTH:63-`CL_SIZE]), + + // Load Request Interface + .ctl_lsq_ex3_ldreq_val(ex3_ldreq_val), + .ctl_lsq_ex3_pfetch_val(ctl_lsq_ex3_pfetch_val), + .ctl_lsq_ex4_ldreq_val(ctl_lsq_ex4_ldreq_val), + .ctl_lsq_ex4_streq_val(ctl_lsq_ex4_streq_val), + .ctl_lsq_ex4_othreq_val(ctl_lsq_ex4_othreq_val), + .ctl_lsq_ex4_p_addr(ex4_p_addr), + .ctl_lsq_ex4_itag(ex4_itag_q), + .ctl_lsq_ex4_dReq_val(ctl_lsq_ex4_dReq_val), + .ctl_lsq_ex4_gath_load(ctl_lsq_ex4_gath_load), + .ctl_lsq_ex4_wimge(ctl_lsq_ex4_wimge), + .ctl_lsq_ex4_byte_swap(ctl_lsq_ex4_byte_swap), + .ctl_lsq_ex4_is_resv(ctl_lsq_ex4_is_resv), + .ctl_lsq_ex4_is_sync(ctl_lsq_ex4_is_sync), + .ctl_lsq_ex4_all_thrd_chk(ctl_lsq_ex4_all_thrd_chk), + .ctl_lsq_ex4_thrd_id(ex4_thrd_id_q), + .ctl_lsq_ex5_lock_set(ctl_lsq_ex5_lock_set), + .ctl_lsq_ex5_watch_set(ctl_lsq_ex5_watch_set), + .ctl_lsq_ex5_thrd_id(ex5_thrd_id_q), + .ctl_lsq_ex5_load_hit(ctl_lsq_ex5_load_hit), + .ctl_lsq_ex5_opsize(ex5_opsize_q), + .ctl_lsq_ex5_tgpr(ctl_lsq_ex5_tgpr), + .ctl_lsq_ex5_axu_val(ctl_lsq_ex5_axu_val), + .ctl_lsq_ex5_usr_def(ctl_lsq_ex5_usr_def), + .ctl_lsq_ex5_drop_rel(ctl_lsq_ex5_drop_rel), + .ctl_lsq_ex5_flush_req(ctl_lsq_ex5_flush_req), + .ctl_lsq_ex5_flush_pfetch(ctl_lsq_ex5_flush_pfetch), + .ctl_lsq_ex5_cmmt_events(ctl_lsq_ex5_cmmt_events), + .ctl_lsq_ex5_perf_val0(ctl_lsq_ex5_perf_val0), + .ctl_lsq_ex5_perf_sel0(ctl_lsq_ex5_perf_sel0), + .ctl_lsq_ex5_perf_val1(ctl_lsq_ex5_perf_val1), + .ctl_lsq_ex5_perf_sel1(ctl_lsq_ex5_perf_sel1), + .ctl_lsq_ex5_perf_val2(ctl_lsq_ex5_perf_val2), + .ctl_lsq_ex5_perf_sel2(ctl_lsq_ex5_perf_sel2), + .ctl_lsq_ex5_perf_val3(ctl_lsq_ex5_perf_val3), + .ctl_lsq_ex5_perf_sel3(ctl_lsq_ex5_perf_sel3), + .ctl_lsq_ex5_not_touch(ctl_lsq_ex5_not_touch), + .ctl_lsq_ex5_algebraic(ex5_algebraic_q), + .ctl_lsq_ex5_class_id(ctl_lsq_ex5_class_id), + .ctl_lsq_ex5_dvc(ctl_lsq_ex5_dvc), + .ctl_lsq_ex5_dacrw(ctl_lsq_ex5_dacrw), + .ctl_lsq_ex5_ttype(ctl_lsq_ex5_ttype), + .lsq_ctl_ex6_ldq_events(lsq_ctl_ex6_ldq_events), + .lsq_perv_ex7_events(lsq_perv_ex7_events), + .lsq_perv_ldq_events(lsq_perv_ldq_events), + .ctl_lsq_ex7_thrd_id(ex7_thrd_id_q), + + .ctl_lsq_pf_empty(ctl_lsq_pf_empty), + + // Interface with Local SPR's + .ctl_lsq_spr_dvc1_dbg(ctl_lsq_spr_dvc1_dbg), + .ctl_lsq_spr_dvc2_dbg(ctl_lsq_spr_dvc2_dbg), + .ctl_lsq_spr_dbcr2_dvc1m(ctl_lsq_spr_dbcr2_dvc1m), + .ctl_lsq_spr_dbcr2_dvc1be(ctl_lsq_spr_dbcr2_dvc1be), + .ctl_lsq_spr_dbcr2_dvc2m(ctl_lsq_spr_dbcr2_dvc2m), + .ctl_lsq_spr_dbcr2_dvc2be(ctl_lsq_spr_dbcr2_dvc2be), + .ctl_lsq_dbg_int_en(ctl_lsq_dbg_int_en), + .ctl_lsq_ldp_idle(ctl_lsq_ldp_idle), + + .stq_ldq_ex5_stq_restart(stq_ldq_ex5_stq_restart), + .stq_ldq_ex5_stq_restart_miss(stq_ldq_ex5_stq_restart_miss), + .stq_ldq_ex5_fwd_val(stq_ldq_ex5_fwd_val), + + // OrderQ Inputs + .odq_ldq_n_flush(odq_ldq_n_flush), + .odq_ldq_np1_flush(odq_ldq_np1_flush), + .odq_ldq_resolved(odq_ldq_resolved), + .odq_ldq_report_needed(odq_ldq_report_needed), + .odq_ldq_report_tid(odq_ldq_report_tid), + .odq_ldq_report_itag(odq_ldq_report_itag), + .odq_ldq_report_dacrw(odq_ldq_report_dacrw), + .odq_ldq_report_eccue(odq_ldq_report_eccue), + .odq_ldq_report_pEvents(odq_ldq_report_pEvents), + .odq_ldq_oldest_ld_tid(odq_ldq_oldest_ld_tid), + .odq_ldq_oldest_ld_itag(odq_ldq_oldest_ld_itag), + .odq_ldq_ex7_pfetch_blk(odq_ldq_ex7_pfetch_blk), + + // Store Queue is Empty + .stq_ldq_empty(stq_ldq_empty), + + // Completion Inputs + .iu_lq_cp_flush(iu_lq_cp_flush), + .iu_lq_cp_next_itag(iu_lq_cp_next_itag), + + // L2 Request Sent + .arb_ldq_ldq_unit_sel(arb_ldq_ldq_unit_sel), + + // L2 Reload + .l2_lsq_resp_isComing(l2_lsq_resp_isComing), + .l2_lsq_resp_val(l2_lsq_resp_val), + .l2_lsq_resp_cTag(l2_lsq_resp_cTag), + .l2_lsq_resp_qw(l2_lsq_resp_qw), + .l2_lsq_resp_crit_qw(l2_lsq_resp_crit_qw), + .l2_lsq_resp_l1_dump(l2_lsq_resp_l1_dump), + .l2_lsq_resp_data(l2_lsq_resp_data), + .l2_lsq_resp_ecc_err(l2_lsq_resp_ecc_err), + .l2_lsq_resp_ecc_err_ue(l2_lsq_resp_ecc_err_ue), + + // Data Cache Config + .xu_lq_spr_xucr0_cls(xu_lq_spr_xucr0_cls), + + // LSU Config + .ctl_lsq_spr_lsucr0_lge(ctl_lsq_spr_lsucr0_lge), + .ctl_lsq_spr_lsucr0_lca(ctl_lsq_spr_lsucr0_lca), + + // Inject Reload Data Array Parity Error + .pc_lq_inj_relq_parity(pc_lq_inj_relq_parity), + + // Interface to Store Queue + .ldq_stq_rel1_blk_store(ldq_stq_rel1_blk_store), + + // Store Hit LoadMiss Queue Entries + .ldq_stq_ex5_ldm_hit(ldq_stq_ex5_ldm_hit), + .ldq_stq_ex5_ldm_entry(ldq_stq_ex5_ldm_entry), + .ldq_stq_ldm_cpl(ldq_stq_ldm_cpl), + + // RV Reload Release Dependent ITAGs + .lq_rv_itag2_vld(lq_rv_itag2_vld), + .lq_rv_itag2(lq_rv_itag2), + + // PRF update for reloads + .ldq_rel2_byte_swap(ldq_rel2_byte_swap), + .ldq_rel2_data(ldq_rel2_data), + + // Directory Congruence Class Updated + .ldq_stq_stq4_dir_upd(ldq_stq_stq4_dir_upd), + .ldq_stq_stq4_cclass(ldq_stq_stq4_cclass), + + // Load Request was not restarted + .ldq_odq_vld(ldq_odq_vld), + .ldq_odq_pfetch_vld(ldq_odq_pfetch_vld), + .ldq_odq_wimge_i(ldq_odq_wimge_i), + .ldq_odq_ex6_pEvents(ldq_odq_ex6_pEvents), + + // Update Order Queue Entry when reload is complete and itag is not resolved + .ldq_odq_upd_val(ldq_odq_upd_val), + .ldq_odq_upd_itag(ldq_odq_upd_itag), + .ldq_odq_upd_nFlush(ldq_odq_upd_nFlush), + .ldq_odq_upd_np1Flush(ldq_odq_upd_np1Flush), + .ldq_odq_upd_tid(ldq_odq_upd_tid), + .ldq_odq_upd_dacrw(ldq_odq_upd_dacrw), + .ldq_odq_upd_eccue(ldq_odq_upd_eccue), + .ldq_odq_upd_pEvents(ldq_odq_upd_pEvents), + + // Interface to Completion + .lq1_iu_execute_vld(lq1_iu_execute_vld), + .lq1_iu_itag(lq1_iu_itag), + .lq1_iu_exception_val(lq1_iu_exception_val), + .lq1_iu_exception(lq1_iu_exception), + .lq1_iu_n_flush(lq1_iu_n_flush), + .lq1_iu_np1_flush(lq1_iu_np1_flush), + .lq1_iu_dacr_type(lq1_iu_dacr_type), + .lq1_iu_dacrw(lq1_iu_dacrw), + .lq1_iu_perf_events(lq1_iu_perf_events), + + // Reservation station hold indicator + .ldq_hold_all_req(ldq_hold_all_req), + + // Reservation station set barrier indicator + .ldq_rv_set_hold(ldq_rv_set_hold), + .ldq_rv_clr_hold(ldq_rv_clr_hold), + + // LOADMISS Queue RESTART indicator + .lsq_ctl_ex5_ldq_restart(lsq_ctl_ex5_ldq_restart), + + // LDQ Request to the L2 + .ldq_arb_ld_req_pwrToken(ldq_arb_ld_req_pwrToken), + .ldq_arb_ld_req_avail(ldq_arb_ld_req_avail), + .ldq_arb_tid(ldq_arb_tid), + .ldq_arb_usr_def(ldq_arb_usr_def), + .ldq_arb_wimge(ldq_arb_wimge), + .ldq_arb_p_addr(ldq_arb_p_addr), + .ldq_arb_ttype(ldq_arb_ttype), + .ldq_arb_opsize(ldq_arb_opsize), + .ldq_arb_cTag(ldq_arb_cTag), + + // RELOAD Data Control + .ldq_dat_stq1_stg_act(ldq_dat_stq1_stg_act), + .lsq_dat_rel1_data_val(lsq_dat_rel1_data_val), + .lsq_dat_rel1_qw(lsq_dat_rel1_qw), + + // RELOAD Directory Control + .ldq_ctl_stq1_stg_act(ldq_ctl_stq1_stg_act), + .lsq_ctl_rel1_clr_val(lsq_ctl_rel1_clr_val), + .lsq_ctl_rel1_set_val(lsq_ctl_rel1_set_val), + .lsq_ctl_rel1_data_val(lsq_ctl_rel1_data_val), + .lsq_ctl_rel1_thrd_id(lsq_ctl_rel1_thrd_id), + .lsq_ctl_rel1_back_inv(lsq_ctl_rel1_back_inv), + .lsq_ctl_rel1_tag(lsq_ctl_rel1_tag), + .lsq_ctl_rel1_classid(lsq_ctl_rel1_classid), + .lsq_ctl_rel1_lock_set(lsq_ctl_rel1_lock_set), + .lsq_ctl_rel1_watch_set(lsq_ctl_rel1_watch_set), + .lsq_ctl_rel2_blk_req(ldq_rel2_blk_req), + .lsq_ctl_rel2_upd_val(lsq_ctl_rel2_upd_val), + .lsq_ctl_rel3_l1dump_val(lsq_ctl_rel3_l1dump_val), + .lsq_ctl_rel3_clr_relq(lsq_ctl_rel3_clr_relq), + + // Control Common to Reload and Commit Pipes + .ldq_arb_rel1_data_sel(ldq_arb_rel1_data_sel), + .ldq_arb_rel1_axu_val(ldq_arb_rel1_axu_val), + .ldq_arb_rel1_op_size(ldq_arb_rel1_op_size), + .ldq_arb_rel1_addr(ldq_arb_rel1_addr), + .ldq_arb_rel1_ci(ldq_arb_rel1_ci), + .ldq_arb_rel1_byte_swap(ldq_arb_rel1_byte_swap), + .ldq_arb_rel1_thrd_id(ldq_arb_rel1_thrd_id), + .ldq_arb_rel1_data(ldq_arb_rel1_data), + .ldq_arb_rel2_rdat_sel(ldq_arb_rel2_rdat_sel), + .ldq_arb_rel2_rd_data(ldq_arb_rel2_rd_data), + .arb_ldq_rel2_wrt_data(arb_ldq_rel2_wrt_data), + + // RELOAD Register Control + .lsq_ctl_rel1_gpr_val(lsq_ctl_rel1_gpr_val), + .lsq_ctl_rel1_ta_gpr(lsq_ctl_rel1_ta_gpr), + .lsq_ctl_rel1_upd_gpr(lsq_ctl_rel1_upd_gpr), + + // Interface to Pervasive Unit + .lq_pc_err_invld_reld(lq_pc_err_invld_reld), + .lq_pc_err_l2intrf_ecc(lq_pc_err_l2intrf_ecc), + .lq_pc_err_l2intrf_ue(lq_pc_err_l2intrf_ue), + .lq_pc_err_relq_parity(lq_pc_err_relq_parity), + + // LQ is Quiesced + .lq_xu_quiesce(lq_xu_quiesce), + .lq_pc_ldq_quiesce(lq_pc_ldq_quiesce), + .lq_pc_stq_quiesce(lq_pc_stq_quiesce), + .lq_pc_pfetch_quiesce(lq_pc_pfetch_quiesce), + .lq_mm_lmq_stq_empty(lq_mm_lmq_stq_empty), + + // Array Pervasive Controls + .bo_enable_2(bo_enable_2), + .clkoff_dc_b(clkoff_dc_b), + .g8t_clkoff_dc_b(g8t_clkoff_dc_b), + .g8t_d_mode_dc(g8t_d_mode_dc), + .g8t_delay_lclkr_dc(g8t_delay_lclkr_dc), + .g8t_mpw1_dc_b(g8t_mpw1_dc_b), + .g8t_mpw2_dc_b(g8t_mpw2_dc_b), + .pc_lq_ccflush_dc(pc_lq_ccflush_dc), + .an_ac_scan_dis_dc_b(an_ac_scan_dis_dc_b), + .an_ac_scan_diag_dc(an_ac_scan_diag_dc), + .an_ac_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc), + .pc_lq_abist_ena_dc(pc_lq_abist_ena_dc), + .pc_lq_abist_raw_dc_b(pc_lq_abist_raw_dc_b), + .pc_lq_abist_wl64_comp_ena(pc_lq_abist_wl64_comp_ena), + .pc_lq_abist_raddr_0(pc_lq_abist_raddr_0[3:8]), + .pc_lq_abist_g8t_wenb(pc_lq_abist_g8t_wenb), + .pc_lq_abist_g8t1p_renb_0(pc_lq_abist_g8t1p_renb_0), + .pc_lq_abist_g8t_dcomp(pc_lq_abist_g8t_dcomp), + .pc_lq_abist_g8t_bw_1(pc_lq_abist_g8t_bw_1), + .pc_lq_abist_g8t_bw_0(pc_lq_abist_g8t_bw_0), + .pc_lq_abist_di_0(pc_lq_abist_di_0), + .pc_lq_abist_waddr_0(pc_lq_abist_waddr_0), + .pc_lq_bo_unload(pc_lq_bo_unload), + .pc_lq_bo_repair(pc_lq_bo_repair), + .pc_lq_bo_reset(pc_lq_bo_reset), + .pc_lq_bo_shdata(pc_lq_bo_shdata), + .pc_lq_bo_select(pc_lq_bo_select[8:9]), + .lq_pc_bo_fail(lq_pc_bo_fail[8:9]), + .lq_pc_bo_diagout(lq_pc_bo_diagout[8:9]), + + // Pervasive + .vcs(vdd), + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .sg_0(sg_0), + .func_sl_thold_0_b(func_sl_thold_0_b), + .func_sl_force(func_sl_force), + .func_nsl_thold_0_b(func_nsl_thold_0_b), + .func_nsl_force(func_nsl_force), + .abst_sl_thold_0(abst_sl_thold_0), + .ary_nsl_thold_0(ary_nsl_thold_0), + .time_sl_thold_0(time_sl_thold_0), + .repr_sl_thold_0(repr_sl_thold_0), + .bolt_sl_thold_0(bolt_sl_thold_0), + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .scan_in(func_scan_in_q[1]), + .abst_scan_in(abst_scan_out_q[1]), + .time_scan_in(time_scan_out_q[0]), + .repr_scan_in(repr_scan_out_q[0]), + .scan_out(func_scan_out_int[1]), + .abst_scan_out(abst_scan_out_int[2]), + .time_scan_out(time_scan_out_int[1]), + .repr_scan_out(repr_scan_out_int[1]) + ); + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // STORE QUEUE + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + + lq_stq stq( + + // IU interface to RV for instruction insertion + // port 0 + .rv_lq_rv1_i0_vld(rv_lq_rv1_i0_vld), + .rv_lq_rv1_i0_ucode_preissue(rv_lq_rv1_i0_ucode_preissue), + .rv_lq_rv1_i0_s3_t(rv_lq_rv1_i0_s3_t), + .rv_lq_rv1_i0_rte_sq(rv_lq_rv1_i0_rte_sq), + .rv_lq_rv1_i0_itag(rv_lq_rv1_i0_itag), + + // port 1 + .rv_lq_rv1_i1_vld(rv_lq_rv1_i1_vld), + .rv_lq_rv1_i1_ucode_preissue(rv_lq_rv1_i1_ucode_preissue), + .rv_lq_rv1_i1_s3_t(rv_lq_rv1_i1_s3_t), + .rv_lq_rv1_i1_rte_sq(rv_lq_rv1_i1_rte_sq), + .rv_lq_rv1_i1_itag(rv_lq_rv1_i1_itag), + + // RV1 RV Issue Valid + .rv_lq_vld(rv_lq_vld), + .rv_lq_isLoad(rv_lq_isLoad), + + // FXU0 Data interface + .xu1_lq_ex2_stq_val(xu1_lq_ex2_stq_val), + .xu1_lq_ex2_stq_itag(xu1_lq_ex2_stq_itag), + // xu1_lq_ex2_stq_size => xu1_lq_ex2_stq_size, + .xu1_lq_ex2_stq_dvc1_cmp(xu1_lq_ex2_stq_dvc1_cmp), + .xu1_lq_ex2_stq_dvc2_cmp(xu1_lq_ex2_stq_dvc2_cmp), + .ctl_lsq_ex4_xu1_data(ctl_lsq_ex4_xu1_data), + .xu1_lq_ex3_illeg_lswx(xu1_lq_ex3_illeg_lswx), + .xu1_lq_ex3_strg_noop(xu1_lq_ex3_strg_noop), + + // AXU Data interface + .xu_lq_axu_ex_stq_val(xu_lq_axu_ex_stq_val), + .xu_lq_axu_ex_stq_itag(xu_lq_axu_ex_stq_itag), + .xu_lq_axu_exp1_stq_data(xu_lq_axu_exp1_stq_data), + + // Load Request Interface + .ctl_lsq_ex2_streq_val(ctl_lsq_ex2_streq_val), + .ctl_lsq_ex2_itag(ctl_lsq_ex2_itag), + .ctl_lsq_ex2_thrd_id(ctl_lsq_ex2_thrd_id), + .ctl_lsq_ex3_ldreq_val(ctl_lsq_ex3_ldreq_val), + .ctl_lsq_ex3_pfetch_val(ctl_lsq_ex3_pfetch_val), + .ctl_lsq_ex3_wchkall_val(ctl_lsq_ex3_wchkall_val), + .ctl_lsq_ex3_byte_en(ctl_lsq_ex3_byte_en), + .ctl_lsq_ex3_p_addr(ctl_lsq_ex3_p_addr), + .ctl_lsq_ex3_opsize(ctl_lsq_ex3_opsize), + .ctl_lsq_ex3_algebraic(ctl_lsq_ex3_algebraic), + .ctl_lsq_ex4_streq_val(ex4_streq_val), + .ctl_lsq_ex4_p_addr(ex4_p_addr), + .ctl_lsq_ex4_cline_chk(ctl_lsq_ex4_cline_chk), + .ctl_lsq_ex4_dreq_val(ctl_lsq_ex4_dReq_val), + .ctl_lsq_ex4_send_l2(ctl_lsq_ex4_send_l2), + .ctl_lsq_ex4_has_data(ctl_lsq_ex4_has_data), + .ctl_lsq_ex4_wimge(ctl_lsq_ex4_wimge), + .ctl_lsq_ex4_byte_swap(ctl_lsq_ex4_byte_swap), + .ctl_lsq_ex4_is_sync(ctl_lsq_ex4_is_sync), + .ctl_lsq_ex4_all_thrd_chk(ctl_lsq_ex4_all_thrd_chk), + .ctl_lsq_ex4_is_store(ctl_lsq_ex4_is_store), + .ctl_lsq_ex4_is_resv(ctl_lsq_ex4_is_resv), + .ctl_lsq_ex4_is_mfgpr(ctl_lsq_ex4_is_mfgpr), + .ctl_lsq_ex4_is_icswxr(ctl_lsq_ex4_is_icswxr), + .ctl_lsq_ex4_is_icbi(ctl_lsq_ex4_is_icbi), + .ctl_lsq_ex4_is_inval_op(ctl_lsq_ex4_is_inval_op), + .ctl_lsq_ex4_watch_clr(ctl_lsq_ex4_watch_clr), + .ctl_lsq_ex4_watch_clr_all(ctl_lsq_ex4_watch_clr_all), + .ctl_lsq_ex4_mtspr_trace(ctl_lsq_ex4_mtspr_trace), + .ctl_lsq_ex4_is_cinval(ctl_lsq_ex4_is_cinval), + .ctl_lsq_ex5_lock_clr(ctl_lsq_ex5_lock_clr), + .ctl_lsq_ex5_ttype(ctl_lsq_ex5_ttype), + .ctl_lsq_ex5_axu_val(ctl_lsq_ex5_axu_val), + .ctl_lsq_ex5_is_epid(ctl_lsq_ex5_is_epid), + .ctl_lsq_ex5_usr_def(ctl_lsq_ex5_usr_def), + .ctl_lsq_ex5_l_fld(ctl_lsq_ex5_l_fld), + .ctl_lsq_ex5_tgpr(ctl_lsq_ex5_tgpr), + .ctl_lsq_ex5_dvc(ctl_lsq_ex5_dvc), + .ctl_lsq_ex5_load_hit(ctl_lsq_ex5_load_hit), + .ctl_lsq_ex5_dacrw(ctl_lsq_ex5_dacrw), + .ctl_lsq_ex5_flush_req(ctl_lsq_ex5_flush_req), + .ctl_lsq_rv1_dir_rd_val(ctl_lsq_rv1_dir_rd_val), + + // Interface with Local SPR's + .ctl_lsq_spr_dvc1_dbg(ctl_lsq_spr_dvc1_dbg), + .ctl_lsq_spr_dvc2_dbg(ctl_lsq_spr_dvc2_dbg), + .ctl_lsq_spr_dbcr2_dvc1m(ctl_lsq_spr_dbcr2_dvc1m), + .ctl_lsq_spr_dbcr2_dvc1be(ctl_lsq_spr_dbcr2_dvc1be), + .ctl_lsq_spr_dbcr2_dvc2m(ctl_lsq_spr_dbcr2_dvc2m), + .ctl_lsq_spr_dbcr2_dvc2be(ctl_lsq_spr_dbcr2_dvc2be), + .ctl_lsq_dbg_int_en(ctl_lsq_dbg_int_en), + + // Next Itag Completion + .iu_lq_cp_next_val(iu_lq_recirc_val), + .iu_lq_cp_next_itag(iu_lq_cp_next_itag), + + // Completion Inputs + .iu_lq_cp_flush(iu_lq_cp_flush), + .iu_lq_i0_completed(iu_lq_i0_completed), + .iu_lq_i0_completed_itag(iu_lq_i0_completed_itag), + .iu_lq_i1_completed(iu_lq_i1_completed), + .iu_lq_i1_completed_itag(iu_lq_i1_completed_itag), + + // Store Queue Completion Report + .lsq_ctl_stq_cpl_ready(lsq_ctl_stq_cpl_ready), + .lsq_ctl_stq_cpl_ready_itag(lsq_ctl_stq_cpl_ready_itag), + .lsq_ctl_stq_cpl_ready_tid(lsq_ctl_stq_cpl_ready_tid), + .lsq_ctl_stq_n_flush(lsq_ctl_stq_n_flush), + .lsq_ctl_stq_np1_flush(lsq_ctl_stq_np1_flush), + .lsq_ctl_stq_exception_val(lsq_ctl_stq_exception_val), + .lsq_ctl_stq_exception(lsq_ctl_stq_exception), + .lsq_ctl_stq_dacrw(lsq_ctl_stq_dacrw), + .ctl_lsq_stq_cpl_blk(ctl_lsq_stq_cpl_blk), + .ctl_lsq_ex_pipe_full(ctl_lsq_ex_pipe_full), + + // Store Queue is Empty + .stq_ldq_empty(stq_ldq_empty), + + // L2 Store Credit Available + .arb_stq_cred_avail(arb_stq_cred_avail), + + // Data Cache Config + .xu_lq_spr_xucr0_cls(xu_lq_spr_xucr0_cls), + + // ICBI ACK Enable + .iu_lq_spr_iucr0_icbi_ack(iu_lq_spr_iucr0_icbi_ack), + + // LSUCR0 Config Bits + .ctl_lsq_spr_lsucr0_sca(ctl_lsq_spr_lsucr0_sca), + .ctl_lsq_spr_lsucr0_dfwd(ctl_lsq_spr_lsucr0_dfwd), + + // Interface to Store Queue + .ldq_stq_rel1_blk_store(ldq_stq_rel1_blk_store), + + .ldq_stq_ex5_ldm_hit(ldq_stq_ex5_ldm_hit), + .ldq_stq_ex5_ldm_entry(ldq_stq_ex5_ldm_entry), + .ldq_stq_ldm_cpl(ldq_stq_ldm_cpl), + + .ldq_stq_stq4_dir_upd(ldq_stq_stq4_dir_upd), + .ldq_stq_stq4_cclass(ldq_stq_stq4_cclass), + + // Age Detection + // store tag used when instruction was inserted to store queue + .stq_odq_i0_stTag(stq_odq_i0_stTag), + .stq_odq_i1_stTag(stq_odq_i1_stTag), + + // store tag is committed, remove from order queue and dont compare against it + .stq_odq_stq4_stTag_inval(stq_odq_stq4_stTag_inval), + .stq_odq_stq4_stTag(stq_odq_stq4_stTag), + + // order queue closest oldest store to the ex2 load request + .odq_stq_ex2_nxt_oldest_val(odq_stq_ex2_nxt_oldest_val), + .odq_stq_ex2_nxt_oldest_stTag(odq_stq_ex2_nxt_oldest_stTag), + + // order queue closest youngest store to the ex2 load request + .odq_stq_ex2_nxt_youngest_val(odq_stq_ex2_nxt_youngest_val), + .odq_stq_ex2_nxt_youngest_stTag(odq_stq_ex2_nxt_youngest_stTag), + + // store tag is resolved from odq allow stq to commit + .odq_stq_resolved(odq_stq_resolved), + .odq_stq_stTag(odq_stq_stTag), + + // Reservation station hold indicator + .stq_hold_all_req(stq_hold_all_req), + + // Reservation station set barrier indicator + .stq_rv_set_hold(stq_rv_set_hold), + .stq_rv_clr_hold(stq_rv_clr_hold), + + // STORE Queue RESTART indicator + .lsq_ctl_ex5_stq_restart(stq_ldq_ex5_stq_restart), + .lsq_ctl_ex5_stq_restart_miss(stq_ldq_ex5_stq_restart_miss), + + // STQ Request to the L2 + .stq_arb_st_req_avail(stq_arb_st_req_avail), + .stq_arb_stq3_cmmt_val(stq_arb_stq3_cmmt_val), + .stq_arb_stq3_cmmt_reject(stq_arb_stq3_cmmt_reject), + .stq_arb_stq3_req_val(stq_arb_stq3_req_val), + .stq_arb_stq3_tid(stq_arb_stq3_tid), + .stq_arb_stq3_usrDef(stq_arb_stq3_usrDef), + .stq_arb_stq3_wimge(stq_arb_stq3_wimge), + .stq_arb_stq3_p_addr(stq_arb_stq3_p_addr), + .stq_arb_stq3_ttype(stq_arb_stq3_ttype), + .stq_arb_stq3_opSize(stq_arb_stq3_opSize), + .stq_arb_stq3_byteEn(stq_arb_stq3_byteEn), + .stq_arb_stq3_cTag(stq_arb_stq3_cTag), + + // Store Commit Data Control + .stq_dat_stq1_stg_act(stq_dat_stq1_stg_act), + .lsq_dat_stq1_val(lsq_dat_stq1_val), + .lsq_dat_stq1_mftgpr_val(lsq_dat_stq1_mftgpr_val), + .lsq_dat_stq1_store_val(lsq_dat_stq1_store_val), + .lsq_dat_stq1_byte_en(lsq_dat_stq1_byte_en), + .stq_arb_stq1_axu_val(stq_arb_stq1_axu_val), + .stq_arb_stq1_epid_val(stq_arb_stq1_epid_val), + .stq_arb_stq1_opSize(stq_arb_stq1_opSize), + .stq_arb_stq1_p_addr(stq_arb_stq1_p_addr), + .stq_arb_stq1_wimge_i(stq_arb_stq1_wimge_i), + .stq_arb_stq1_store_data(stq_arb_stq1_store_data), + .stq_arb_stq1_thrd_id(stq_arb_stq1_thrd_id), + .stq_arb_stq1_byte_swap(stq_arb_stq1_byte_swap), + + // Store Commit Directory Control + .stq_ctl_stq1_stg_act(stq_ctl_stq1_stg_act), + .lsq_ctl_stq1_val(lsq_ctl_stq1_val), + .lsq_ctl_stq1_mftgpr_val(lsq_ctl_stq1_mftgpr_val), + .lsq_ctl_stq1_mfdpf_val(lsq_ctl_stq1_mfdpf_val), + .lsq_ctl_stq1_mfdpa_val(lsq_ctl_stq1_mfdpa_val), + .lsq_ctl_stq1_lock_clr(lsq_ctl_stq1_lock_clr), + .lsq_ctl_stq1_watch_clr(lsq_ctl_stq1_watch_clr), + .lsq_ctl_stq1_l_fld(lsq_ctl_stq1_l_fld), + .lsq_ctl_stq1_inval(lsq_ctl_stq1_inval), + .lsq_ctl_stq1_dci_val(lsq_ctl_stq1_dci_val), + .lsq_ctl_stq1_store_val(lsq_ctl_stq1_store_val), + .lsq_ctl_stq4_xucr0_cul(lsq_ctl_stq4_xucr0_cul), + .lsq_ctl_stq5_itag(lsq_ctl_stq5_itag), + .lsq_ctl_stq5_tgpr(lsq_ctl_stq5_tgpr), + .ctl_lsq_stq4_perr_reject(ctl_lsq_stq4_perr_reject), + + // Illegal LSWX has been determined + .lsq_ctl_ex3_strg_val(lsq_ctl_ex3_strg_val), + .lsq_ctl_ex3_strg_noop(lsq_ctl_ex3_strg_noop), + .lsq_ctl_ex3_illeg_lswx(lsq_ctl_ex3_illeg_lswx), + .lsq_ctl_ex3_ct_val(lsq_ctl_ex3_ct_val), + .lsq_ctl_ex3_be_ct(lsq_ctl_ex3_be_ct), + .lsq_ctl_ex3_le_ct(lsq_ctl_ex3_le_ct), + + // Store Commit Control + .lsq_ctl_stq1_resv(lsq_ctl_stq1_resv), + .stq_stq2_blk_req(stq_stq2_blk_req), + + .lsq_ctl_sync_in_stq(lsq_ctl_sync_in_stq), + .lsq_ctl_sync_done(lsq_ctl_sync_done), + + // Store Data Forward + .lsq_ctl_ex5_fwd_val(stq_ldq_ex5_fwd_val), + .lsq_ctl_ex5_fwd_data(lsq_ctl_ex5_fwd_data), + .lsq_ctl_ex6_stq_events(lsq_ctl_ex6_stq_events), + .lsq_perv_stq_events(lsq_perv_stq_events), + + // Store Credit Return + .sq_iu_credit_free(sq_iu_credit_free), + + .an_ac_sync_ack(an_ac_sync_ack), + + // ICBI interface + .lq_iu_icbi_val(lq_iu_icbi_val), + .lq_iu_icbi_addr(lq_iu_icbi_addr), + .iu_lq_icbi_complete(iu_lq_icbi_complete), + + // ICI Interace + .lq_iu_ici_val(lq_iu_ici_val), + + // Back-Invalidate Valid + .l2_back_inv_val(l2_back_inv_val_q), + .l2_back_inv_addr(l2_back_inv_addr[64 - (`DC_SIZE - 3):63 - `CL_SIZE]), + + // L2 Interface Back Invalidate + .an_ac_back_inv(an_ac_back_inv_q), + .an_ac_back_inv_target_bit3(an_ac_back_inv_target_bit3_q), + .an_ac_back_inv_addr(an_ac_back_inv_addr_q[58:60]), + .an_ac_back_inv_addr_lo(an_ac_back_inv_addr_q[62:63]), + + // Stcx Complete + .an_ac_stcx_complete(an_ac_stcx_complete_q), + .an_ac_stcx_pass(an_ac_stcx_pass_q), + + // ICBI ACK + .an_ac_icbi_ack(an_ac_icbi_ack_q), + .an_ac_icbi_ack_thread(an_ac_icbi_ack_thread_q), + + // Core ID + .an_ac_coreid(an_ac_coreid_q), + + // STCX/ICSWX CR Update + .lq_xu_cr_l2_we(lq_xu_cr_l2_we), + .lq_xu_cr_l2_wa(lq_xu_cr_l2_wa), + .lq_xu_cr_l2_wd(lq_xu_cr_l2_wd), + + // XER Read for long latency CP_NEXT ops stcx./icswx. + .xu_lq_xer_cp_rd(xu_lq_xer_cp_rd), + + // Reload Itag Complete + .stq_arb_release_itag_vld(stq_arb_release_itag_vld), + .stq_arb_release_itag(stq_arb_release_itag), + .stq_arb_release_tid(stq_arb_release_tid), + + // Pervasive + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .sg_0(sg_0), + .func_sl_thold_0_b(func_sl_thold_0_b), + .func_sl_force(func_sl_force), + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .scan_in(func_scan_in_q[2]), + .scan_out(func_scan_out_int[2]) + ); + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // INSTRUCTION/MMU QUEUE + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + + lq_imq imq( + + // Instruction Fetches + .iu_lq_request(iu_lq_request), + .iu_lq_cTag(iu_lq_cTag), + .iu_lq_ra(iu_lq_ra), + .iu_lq_wimge(iu_lq_wimge), + .iu_lq_userdef(iu_lq_userdef), + + // MMU instruction interface + .mm_lq_lsu_req(mm_lq_lsu_req), + .mm_lq_lsu_ttype(mm_lq_lsu_ttype), + .mm_lq_lsu_wimge(mm_lq_lsu_wimge), + .mm_lq_lsu_u(mm_lq_lsu_u), + .mm_lq_lsu_addr(mm_lq_lsu_addr), + + // TLBI_COMPLETE is addressless + .mm_lq_lsu_lpid(mm_lq_lsu_lpid), + .mm_lq_lsu_gs(mm_lq_lsu_gs), + .mm_lq_lsu_ind(mm_lq_lsu_ind), + .mm_lq_lsu_lbit(mm_lq_lsu_lbit), + .lq_mm_lsu_token(lq_mm_lsu_token), + + // IUQ Request Sent + .arb_imq_iuq_unit_sel(arb_imq_iuq_unit_sel), + .arb_imq_mmq_unit_sel(arb_imq_mmq_unit_sel), + + // IUQ Request to the L2 + .imq_arb_iuq_ld_req_avail(imq_arb_iuq_ld_req_avail), + .imq_arb_iuq_tid(imq_arb_iuq_tid), + .imq_arb_iuq_usr_def(imq_arb_iuq_usr_def), + .imq_arb_iuq_wimge(imq_arb_iuq_wimge), + .imq_arb_iuq_p_addr(imq_arb_iuq_p_addr), + .imq_arb_iuq_ttype(imq_arb_iuq_ttype), + .imq_arb_iuq_opSize(imq_arb_iuq_opSize), + .imq_arb_iuq_cTag(imq_arb_iuq_cTag), + + // MMQ Request to the L2 + .imq_arb_mmq_ld_req_avail(imq_arb_mmq_ld_req_avail), + .imq_arb_mmq_st_req_avail(imq_arb_mmq_st_req_avail), + .imq_arb_mmq_tid(imq_arb_mmq_tid), + .imq_arb_mmq_usr_def(imq_arb_mmq_usr_def), + .imq_arb_mmq_wimge(imq_arb_mmq_wimge), + .imq_arb_mmq_p_addr(imq_arb_mmq_p_addr), + .imq_arb_mmq_ttype(imq_arb_mmq_ttype), + .imq_arb_mmq_opSize(imq_arb_mmq_opSize), + .imq_arb_mmq_cTag(imq_arb_mmq_cTag), + .imq_arb_mmq_st_data(imq_arb_mmq_st_data), + + // Pervasive + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .sg_0(sg_0), + .func_sl_thold_0_b(func_sl_thold_0_b), + .func_sl_force(func_sl_force), + .func_slp_sl_thold_0_b(func_slp_sl_thold_0_b), + .func_slp_sl_force(func_slp_sl_force), + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .scan_in(func_scan_in_q[3]), + .scan_out(func_scan_out_int[3]) + ); + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // L2 REQUEST ARBITER + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + + lq_arb arb( + + // IUQ Request to the L2 + .imq_arb_iuq_ld_req_avail(imq_arb_iuq_ld_req_avail), + .imq_arb_iuq_tid(imq_arb_iuq_tid), + .imq_arb_iuq_usr_def(imq_arb_iuq_usr_def), + .imq_arb_iuq_wimge(imq_arb_iuq_wimge), + .imq_arb_iuq_p_addr(imq_arb_iuq_p_addr), + .imq_arb_iuq_ttype(imq_arb_iuq_ttype), + .imq_arb_iuq_opSize(imq_arb_iuq_opSize), + .imq_arb_iuq_cTag(imq_arb_iuq_cTag), + + // MMQ Request to the L2 + .imq_arb_mmq_ld_req_avail(imq_arb_mmq_ld_req_avail), + .imq_arb_mmq_st_req_avail(imq_arb_mmq_st_req_avail), + .imq_arb_mmq_tid(imq_arb_mmq_tid), + .imq_arb_mmq_usr_def(imq_arb_mmq_usr_def), + .imq_arb_mmq_wimge(imq_arb_mmq_wimge), + .imq_arb_mmq_p_addr(imq_arb_mmq_p_addr), + .imq_arb_mmq_ttype(imq_arb_mmq_ttype), + .imq_arb_mmq_opSize(imq_arb_mmq_opSize), + .imq_arb_mmq_cTag(imq_arb_mmq_cTag), + .imq_arb_mmq_st_data(imq_arb_mmq_st_data), + + // ldq Request to the L2 + .ldq_arb_ld_req_pwrToken(ldq_arb_ld_req_pwrToken), + .ldq_arb_ld_req_avail(ldq_arb_ld_req_avail), + .ldq_arb_tid(ldq_arb_tid), + .ldq_arb_usr_def(ldq_arb_usr_def), + .ldq_arb_wimge(ldq_arb_wimge), + .ldq_arb_p_addr(ldq_arb_p_addr), + .ldq_arb_ttype(ldq_arb_ttype), + .ldq_arb_opSize(ldq_arb_opsize), + .ldq_arb_cTag(ldq_arb_cTag), + + // Store Type Request to L2 + .stq_arb_stq1_stg_act(stq_dat_stq1_stg_act), + .stq_arb_st_req_avail(stq_arb_st_req_avail), + .stq_arb_stq3_cmmt_val(stq_arb_stq3_cmmt_val), + .stq_arb_stq3_cmmt_reject(stq_arb_stq3_cmmt_reject), + .stq_arb_stq3_req_val(stq_arb_stq3_req_val), + .stq_arb_stq3_tid(stq_arb_stq3_tid), + .stq_arb_stq3_usrDef(stq_arb_stq3_usrDef), + .stq_arb_stq3_wimge(stq_arb_stq3_wimge), + .stq_arb_stq3_p_addr(stq_arb_stq3_p_addr), + .stq_arb_stq3_ttype(stq_arb_stq3_ttype), + .stq_arb_stq3_opSize(stq_arb_stq3_opSize), + .stq_arb_stq3_byteEn(stq_arb_stq3_byteEn), + .stq_arb_stq3_cTag(stq_arb_stq3_cTag), + .dat_lsq_stq4_128data(dat_lsq_stq4_128data), + + // Common Between LDQ and STQ + .ldq_arb_rel1_stg_act(ldq_ctl_stq1_stg_act), + .ldq_arb_rel1_data_sel(ldq_arb_rel1_data_sel), + .ldq_arb_rel1_data(ldq_arb_rel1_data), + .ldq_arb_rel1_blk_store(ldq_stq_rel1_blk_store), + .ldq_arb_rel1_axu_val(ldq_arb_rel1_axu_val), + .ldq_arb_rel1_op_size(ldq_arb_rel1_op_size), + .ldq_arb_rel1_addr(ldq_arb_rel1_addr), + .ldq_arb_rel1_ci(ldq_arb_rel1_ci), + .ldq_arb_rel1_byte_swap(ldq_arb_rel1_byte_swap), + .ldq_arb_rel1_thrd_id(ldq_arb_rel1_thrd_id), + .ldq_arb_rel2_rdat_sel(ldq_arb_rel2_rdat_sel), + .stq_arb_stq1_axu_val(stq_arb_stq1_axu_val), + .stq_arb_stq1_epid_val(stq_arb_stq1_epid_val), + .stq_arb_stq1_opSize(stq_arb_stq1_opSize), + .stq_arb_stq1_p_addr(stq_arb_stq1_p_addr), + .stq_arb_stq1_wimge_i(stq_arb_stq1_wimge_i), + .stq_arb_stq1_store_data(stq_arb_stq1_store_data), + .stq_arb_stq1_byte_swap(stq_arb_stq1_byte_swap), + .stq_arb_stq1_thrd_id(stq_arb_stq1_thrd_id), + .stq_arb_release_itag_vld(stq_arb_release_itag_vld), + .stq_arb_release_itag(stq_arb_release_itag), + .stq_arb_release_tid(stq_arb_release_tid), + + // L2 Credit Control + .l2_lsq_req_ld_pop(an_ac_req_ld_pop_q), + .l2_lsq_req_st_pop(an_ac_req_st_pop_q), + .l2_lsq_req_st_gather(an_ac_req_st_gather_q), + + // ICSWX Data to be sent to the L2 + .ctl_lsq_stq3_icswx_data(ctl_lsq_stq3_icswx_data), + + // Interface with Reload Data Queue + .ldq_arb_rel2_rd_data(ldq_arb_rel2_rd_data), + .arb_ldq_rel2_wrt_data(arb_ldq_rel2_wrt_data), + + // L2 Credits Available + .arb_stq_cred_avail(arb_stq_cred_avail), + + // Unit Selected to Send Request to the L2 + .arb_ldq_ldq_unit_sel(arb_ldq_ldq_unit_sel), + .arb_imq_iuq_unit_sel(arb_imq_iuq_unit_sel), + .arb_imq_mmq_unit_sel(arb_imq_mmq_unit_sel), + + // Common Between LDQ and STQ + .lsq_ctl_stq1_axu_val(lsq_ctl_stq1_axu_val), + .lsq_ctl_stq1_epid_val(lsq_ctl_stq1_epid_val), + .lsq_dat_stq1_op_size(lsq_dat_stq1_op_size), + .lsq_dat_stq1_addr(lsq_dat_stq1_addr), + .lsq_dat_stq1_le_mode(lsq_dat_stq1_le_mode), + .lsq_dat_stq2_store_data(lsq_dat_stq2_store_data), + .lsq_ctl_stq1_addr(lsq_ctl_stq1_addr), + .lsq_ctl_stq1_ci(lsq_ctl_stq1_ci), + .lsq_ctl_stq1_thrd_id(lsq_ctl_stq1_thrd_id), + + // STCX/ICSWX Itag Complete + .lsq_ctl_stq_release_itag_vld(lsq_ctl_stq_release_itag_vld), + .lsq_ctl_stq_release_itag(lsq_ctl_stq_release_itag), + .lsq_ctl_stq_release_tid(lsq_ctl_stq_release_tid), + + // L2 Request Signals + .lsq_l2_pwrToken(lsq_l2_pwrToken), + .lsq_l2_valid(lsq_l2_valid), + .lsq_l2_tid(lsq_l2_tid), + .lsq_l2_p_addr(lsq_l2_p_addr), + .lsq_l2_wimge(lsq_l2_wimge), + .lsq_l2_usrDef(lsq_l2_usrDef), + .lsq_l2_byteEn(lsq_l2_byteEn), + .lsq_l2_ttype(lsq_l2_ttype), + .lsq_l2_opSize(lsq_l2_opSize), + .lsq_l2_coreTag(lsq_l2_coreTag), + .lsq_l2_dataToken(lsq_l2_dataToken), + .lsq_l2_st_data(lsq_l2_st_data), + + // SPR Bits + .ctl_lsq_spr_lsucr0_b2b(ctl_lsq_spr_lsucr0_b2b), + .xu_lq_spr_xucr0_cred(xu_lq_spr_xucr0_cred), + .xu_lq_spr_xucr0_cls(xu_lq_spr_xucr0_cls), + + // Pervasive Error Report + .lq_pc_err_l2credit_overrun(lq_pc_err_l2credit_overrun), + + // Pervasive + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .sg_0(sg_0), + .func_sl_thold_0_b(func_sl_thold_0_b), + .func_sl_force(func_sl_force), + .func_slp_sl_thold_0_b(func_slp_sl_thold_0_b), + .func_slp_sl_force(func_slp_sl_force), + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .scan_in(func_scan_in_q[4]), + .scan_out(arb_func_scan_out) + ); + + assign an_ac_reld_data_vld_stg1_d = an_ac_reld_data_vld_q; + + assign l2_lsq_resp_isComing = an_ac_reld_data_coming_q; + assign l2_lsq_resp_val = an_ac_reld_data_vld_q; + assign l2_lsq_resp_cTag = an_ac_reld_core_tag_q; + assign l2_lsq_resp_qw = {1'b0, an_ac_reld_qw_q}; + assign l2_lsq_resp_crit_qw = an_ac_reld_crit_qw_q; + assign l2_lsq_resp_l1_dump = an_ac_reld_l1_dump_q; + assign l2_lsq_resp_data = an_ac_reld_data_q; + assign l2_lsq_resp_ecc_err = an_ac_reld_ecc_err_q; + assign l2_lsq_resp_ecc_err_ue = an_ac_reld_ecc_err_ue_q; + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // Outputs + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + + assign ac_an_req_pwr_token = lsq_l2_pwrToken; + assign ac_an_req = lsq_l2_valid; + assign ac_an_req_ra = lsq_l2_p_addr; + assign ac_an_req_ttype = lsq_l2_ttype; + assign ac_an_req_thread[0:1] = lsq_l2_tid; + assign ac_an_req_thread[2] = 1'b0; // DITC Indicator + assign ac_an_req_wimg_w = lsq_l2_wimge[0]; + assign ac_an_req_wimg_i = lsq_l2_wimge[1]; + assign ac_an_req_wimg_m = lsq_l2_wimge[2]; + assign ac_an_req_wimg_g = lsq_l2_wimge[3]; + assign ac_an_req_endian = lsq_l2_wimge[4]; + assign ac_an_req_user_defined = lsq_l2_usrDef; + assign ac_an_req_spare_ctrl_a0 = {4{1'b0}}; + assign ac_an_req_ld_core_tag = lsq_l2_coreTag; + assign ac_an_req_ld_xfr_len = lsq_l2_opSize; + assign ac_an_st_byte_enbl[0:15] = lsq_l2_byteEn; + assign ac_an_st_byte_enbl[16:31] = {16{1'b0}}; + assign ac_an_st_data[0:127] = lsq_l2_st_data; + assign ac_an_st_data[128:255] = {128{1'b0}}; + assign ac_an_st_data_pwr_token = lsq_l2_dataToken; + assign lsq_ctl_stq1_stg_act = ldq_ctl_stq1_stg_act | stq_ctl_stq1_stg_act; + assign lsq_dat_stq1_stg_act = ldq_dat_stq1_stg_act | stq_dat_stq1_stg_act; + assign lsq_ctl_rel2_blk_req = ldq_rel2_blk_req; + assign lsq_ctl_stq2_blk_req = stq_stq2_blk_req; + assign lsq_dat_stq2_blk_req = ldq_rel2_blk_req | stq_stq2_blk_req; + assign lsq_ctl_rv_hold_all = ldq_hold_all_req | stq_hold_all_req; + assign lsq_ctl_rv_set_hold = ldq_rv_set_hold | stq_rv_set_hold; + assign lsq_ctl_rv_clr_hold = ldq_rv_clr_hold | stq_rv_clr_hold; + assign lsq_ctl_rv0_back_inv = l2_back_inv_val_q; + assign lsq_ctl_rv1_back_inv_addr = rv1_back_inv_addr_q; + assign lsq_ctl_ex5_stq_restart = stq_ldq_ex5_stq_restart; + assign lsq_ctl_ex5_stq_restart_miss = stq_ldq_ex5_stq_restart_miss; + assign lsq_ctl_ex5_fwd_val = stq_ldq_ex5_fwd_val; + assign lq_xu_axu_rel_le = ldq_rel2_byte_swap; + assign lsq_ctl_rel2_data = ldq_rel2_data; + + // SCAN OUT Gate + assign abst_scan_out = abst_scan_out_q[2] & an_ac_scan_dis_dc_b; + assign time_scan_out = time_scan_out_q[1] & an_ac_scan_dis_dc_b; + assign repr_scan_out = repr_scan_out_q[1] & an_ac_scan_dis_dc_b; + assign func_scan_out = func_scan_out_q & {7{an_ac_scan_dis_dc_b}}; + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // REGISTERS + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_odq_inv_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_odq_inv_offset]), + .scout(sov[ldq_odq_inv_offset]), + .din(ldq_odq_inv_d), + .dout(ldq_odq_inv_q) + ); + + + tri_rlmreg_p #(.WIDTH(`REAL_IFAR_WIDTH-4), .INIT(0), .NEEDS_SRESET(1)) ldq_odq_addr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_odq_addr_offset:ldq_odq_addr_offset + (`REAL_IFAR_WIDTH-4) - 1]), + .scout(sov[ldq_odq_addr_offset:ldq_odq_addr_offset + (`REAL_IFAR_WIDTH-4) - 1]), + .din(ldq_odq_addr_d), + .dout(ldq_odq_addr_q) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ldq_odq_itag_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_odq_itag_offset:ldq_odq_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[ldq_odq_itag_offset:ldq_odq_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(ldq_odq_itag_d), + .dout(ldq_odq_itag_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_odq_cline_chk_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_odq_cline_chk_offset]), + .scout(sov[ldq_odq_cline_chk_offset]), + .din(ldq_odq_cline_chk_d), + .dout(ldq_odq_cline_chk_q) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex3_itag_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_itag_offset:ex3_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[ex3_itag_offset:ex3_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(ex3_itag_d), + .dout(ex3_itag_q) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex4_itag_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_itag_offset:ex4_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[ex4_itag_offset:ex4_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(ex4_itag_d), + .dout(ex4_itag_q) + ); + + + tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) ex4_byte_en_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_byte_en_offset:ex4_byte_en_offset + 16 - 1]), + .scout(sov[ex4_byte_en_offset:ex4_byte_en_offset + 16 - 1]), + .din(ex4_byte_en_d), + .dout(ex4_byte_en_q) + ); + + + tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) ex5_byte_en_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_byte_en_offset:ex5_byte_en_offset + 16 - 1]), + .scout(sov[ex5_byte_en_offset:ex5_byte_en_offset + 16 - 1]), + .din(ex5_byte_en_d), + .dout(ex5_byte_en_q) + ); + + + tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) ex4_p_addr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_p_addr_offset:ex4_p_addr_offset + 6 - 1]), + .scout(sov[ex4_p_addr_offset:ex4_p_addr_offset + 6 - 1]), + .din(ex4_p_addr_d), + .dout(ex4_p_addr_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex4_thrd_id_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_thrd_id_offset:ex4_thrd_id_offset + `THREADS - 1]), + .scout(sov[ex4_thrd_id_offset:ex4_thrd_id_offset + `THREADS - 1]), + .din(ex4_thrd_id_d), + .dout(ex4_thrd_id_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex5_thrd_id_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_thrd_id_offset:ex5_thrd_id_offset + `THREADS - 1]), + .scout(sov[ex5_thrd_id_offset:ex5_thrd_id_offset + `THREADS - 1]), + .din(ex5_thrd_id_d), + .dout(ex5_thrd_id_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex6_thrd_id_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_thrd_id_offset:ex6_thrd_id_offset + `THREADS - 1]), + .scout(sov[ex6_thrd_id_offset:ex6_thrd_id_offset + `THREADS - 1]), + .din(ex6_thrd_id_d), + .dout(ex6_thrd_id_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex7_thrd_id_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex7_thrd_id_offset:ex7_thrd_id_offset + `THREADS - 1]), + .scout(sov[ex7_thrd_id_offset:ex7_thrd_id_offset + `THREADS - 1]), + .din(ex7_thrd_id_d), + .dout(ex7_thrd_id_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_algebraic_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_algebraic_offset]), + .scout(sov[ex4_algebraic_offset]), + .din(ex4_algebraic_d), + .dout(ex4_algebraic_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_algebraic_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_algebraic_offset]), + .scout(sov[ex5_algebraic_offset]), + .din(ex5_algebraic_d), + .dout(ex5_algebraic_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex4_opsize_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_opsize_offset:ex4_opsize_offset + 3 - 1]), + .scout(sov[ex4_opsize_offset:ex4_opsize_offset + 3 - 1]), + .din(ex4_opsize_d), + .dout(ex4_opsize_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex5_opsize_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_opsize_offset:ex5_opsize_offset + 3 - 1]), + .scout(sov[ex5_opsize_offset:ex5_opsize_offset + 3 - 1]), + .din(ex5_opsize_d), + .dout(ex5_opsize_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_dreq_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_dreq_val_offset]), + .scout(sov[ex5_dreq_val_offset]), + .din(ex5_dreq_val_d), + .dout(ex5_dreq_val_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr0_cls_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_xucr0_cls_offset]), + .scout(sov[spr_xucr0_cls_offset]), + .din(spr_xucr0_cls_d), + .dout(spr_xucr0_cls_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) an_ac_req_ld_pop_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[an_ac_req_ld_pop_offset]), + .scout(sov[an_ac_req_ld_pop_offset]), + .din(an_ac_req_ld_pop_d), + .dout(an_ac_req_ld_pop_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) an_ac_req_st_pop_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[an_ac_req_st_pop_offset]), + .scout(sov[an_ac_req_st_pop_offset]), + .din(an_ac_req_st_pop_d), + .dout(an_ac_req_st_pop_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) an_ac_req_st_gather_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[an_ac_req_st_gather_offset]), + .scout(sov[an_ac_req_st_gather_offset]), + .din(an_ac_req_st_gather_d), + .dout(an_ac_req_st_gather_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) an_ac_reld_data_vld_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[an_ac_reld_data_vld_offset]), + .scout(sov[an_ac_reld_data_vld_offset]), + .din(an_ac_reld_data_vld_d), + .dout(an_ac_reld_data_vld_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) an_ac_reld_data_vld_stg1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[an_ac_reld_data_vld_stg1_offset]), + .scout(sov[an_ac_reld_data_vld_stg1_offset]), + .din(an_ac_reld_data_vld_stg1_d), + .dout(an_ac_reld_data_vld_stg1_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) an_ac_reld_data_coming_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[an_ac_reld_data_coming_offset]), + .scout(sov[an_ac_reld_data_coming_offset]), + .din(an_ac_reld_data_coming_d), + .dout(an_ac_reld_data_coming_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) an_ac_reld_ditc_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[an_ac_reld_ditc_offset]), + .scout(sov[an_ac_reld_ditc_offset]), + .din(an_ac_reld_ditc_d), + .dout(an_ac_reld_ditc_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) an_ac_reld_crit_qw_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[an_ac_reld_crit_qw_offset]), + .scout(sov[an_ac_reld_crit_qw_offset]), + .din(an_ac_reld_crit_qw_d), + .dout(an_ac_reld_crit_qw_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) an_ac_reld_l1_dump_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[an_ac_reld_l1_dump_offset]), + .scout(sov[an_ac_reld_l1_dump_offset]), + .din(an_ac_reld_l1_dump_d), + .dout(an_ac_reld_l1_dump_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) an_ac_reld_ecc_err_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[an_ac_reld_ecc_err_offset]), + .scout(sov[an_ac_reld_ecc_err_offset]), + .din(an_ac_reld_ecc_err_d), + .dout(an_ac_reld_ecc_err_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) an_ac_reld_ecc_err_ue_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[an_ac_reld_ecc_err_ue_offset]), + .scout(sov[an_ac_reld_ecc_err_ue_offset]), + .din(an_ac_reld_ecc_err_ue_d), + .dout(an_ac_reld_ecc_err_ue_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) an_ac_back_inv_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[an_ac_back_inv_offset]), + .scout(sov[an_ac_back_inv_offset]), + .din(an_ac_back_inv_d), + .dout(an_ac_back_inv_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) an_ac_back_inv_target_bit1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[an_ac_back_inv_target_bit1_offset]), + .scout(sov[an_ac_back_inv_target_bit1_offset]), + .din(an_ac_back_inv_target_bit1_d), + .dout(an_ac_back_inv_target_bit1_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) an_ac_back_inv_target_bit3_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[an_ac_back_inv_target_bit3_offset]), + .scout(sov[an_ac_back_inv_target_bit3_offset]), + .din(an_ac_back_inv_target_bit3_d), + .dout(an_ac_back_inv_target_bit3_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) an_ac_back_inv_target_bit4_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[an_ac_back_inv_target_bit4_offset]), + .scout(sov[an_ac_back_inv_target_bit4_offset]), + .din(an_ac_back_inv_target_bit4_d), + .dout(an_ac_back_inv_target_bit4_q) + ); + + + tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) mm_lq_lsu_lpidr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[mm_lq_lsu_lpidr_offset:mm_lq_lsu_lpidr_offset + 8 - 1]), + .scout(sov[mm_lq_lsu_lpidr_offset:mm_lq_lsu_lpidr_offset + 8 - 1]), + .din(mm_lq_lsu_lpidr_d), + .dout(mm_lq_lsu_lpidr_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) l2_dbell_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[l2_dbell_val_offset]), + .scout(sov[l2_dbell_val_offset]), + .din(l2_dbell_val_d), + .dout(l2_dbell_val_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) l2_back_inv_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[l2_back_inv_val_offset]), + .scout(sov[l2_back_inv_val_offset]), + .din(l2_back_inv_val_d), + .dout(l2_back_inv_val_q) + ); + + + tri_rlmreg_p #(.WIDTH((63-`CL_SIZE-(64-`REAL_IFAR_WIDTH)+1)), .INIT(0), .NEEDS_SRESET(1)) rv1_back_inv_addr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(l2_back_inv_val_q), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rv1_back_inv_addr_offset:rv1_back_inv_addr_offset + (63-`CL_SIZE-(64-`REAL_IFAR_WIDTH)+1) - 1]), + .scout(sov[rv1_back_inv_addr_offset:rv1_back_inv_addr_offset + (63-`CL_SIZE-(64-`REAL_IFAR_WIDTH)+1) - 1]), + .din(rv1_back_inv_addr_d), + .dout(rv1_back_inv_addr_q) + ); + + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) an_ac_req_spare_ctrl_a1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[an_ac_req_spare_ctrl_a1_offset:an_ac_req_spare_ctrl_a1_offset + 4 - 1]), + .scout(sov[an_ac_req_spare_ctrl_a1_offset:an_ac_req_spare_ctrl_a1_offset + 4 - 1]), + .din(an_ac_req_spare_ctrl_a1_d), + .dout(an_ac_req_spare_ctrl_a1_q) + ); + + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) an_ac_reld_core_tag_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[an_ac_reld_core_tag_offset:an_ac_reld_core_tag_offset + 5 - 1]), + .scout(sov[an_ac_reld_core_tag_offset:an_ac_reld_core_tag_offset + 5 - 1]), + .din(an_ac_reld_core_tag_d), + .dout(an_ac_reld_core_tag_q) + ); + + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) an_ac_reld_qw_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[an_ac_reld_qw_offset:an_ac_reld_qw_offset + 2 - 1]), + .scout(sov[an_ac_reld_qw_offset:an_ac_reld_qw_offset + 2 - 1]), + .din(an_ac_reld_qw_d), + .dout(an_ac_reld_qw_q) + ); + + + tri_rlmreg_p #(.WIDTH(128), .INIT(0), .NEEDS_SRESET(1)) an_ac_reld_data_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(an_ac_reld_data_vld_stg1_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[an_ac_reld_data_offset:an_ac_reld_data_offset + 128 - 1]), + .scout(sov[an_ac_reld_data_offset:an_ac_reld_data_offset + 128 - 1]), + .din(an_ac_reld_data_d), + .dout(an_ac_reld_data_q) + ); + + + tri_rlmreg_p #(.WIDTH(`REAL_IFAR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) an_ac_back_inv_addr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(an_ac_back_inv_q), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[an_ac_back_inv_addr_offset:an_ac_back_inv_addr_offset + `REAL_IFAR_WIDTH - 1]), + .scout(sov[an_ac_back_inv_addr_offset:an_ac_back_inv_addr_offset + `REAL_IFAR_WIDTH - 1]), + .din(an_ac_back_inv_addr_d), + .dout(an_ac_back_inv_addr_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) an_ac_sync_ack_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[an_ac_sync_ack_offset:an_ac_sync_ack_offset + `THREADS - 1]), + .scout(sov[an_ac_sync_ack_offset:an_ac_sync_ack_offset + `THREADS - 1]), + .din(an_ac_sync_ack_d), + .dout(an_ac_sync_ack_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) an_ac_stcx_complete_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[an_ac_stcx_complete_offset:an_ac_stcx_complete_offset + `THREADS - 1]), + .scout(sov[an_ac_stcx_complete_offset:an_ac_stcx_complete_offset + `THREADS - 1]), + .din(an_ac_stcx_complete_d), + .dout(an_ac_stcx_complete_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) an_ac_stcx_pass_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[an_ac_stcx_pass_offset:an_ac_stcx_pass_offset + `THREADS - 1]), + .scout(sov[an_ac_stcx_pass_offset:an_ac_stcx_pass_offset + `THREADS - 1]), + .din(an_ac_stcx_pass_d), + .dout(an_ac_stcx_pass_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) an_ac_icbi_ack_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[an_ac_icbi_ack_offset]), + .scout(sov[an_ac_icbi_ack_offset]), + .din(an_ac_icbi_ack_d), + .dout(an_ac_icbi_ack_q) + ); + + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) an_ac_icbi_ack_thread_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[an_ac_icbi_ack_thread_offset:an_ac_icbi_ack_thread_offset + 2 - 1]), + .scout(sov[an_ac_icbi_ack_thread_offset:an_ac_icbi_ack_thread_offset + 2 - 1]), + .din(an_ac_icbi_ack_thread_d), + .dout(an_ac_icbi_ack_thread_q) + ); + + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) an_ac_coreid_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[an_ac_coreid_offset:an_ac_coreid_offset + 2 - 1]), + .scout(sov[an_ac_coreid_offset:an_ac_coreid_offset + 2 - 1]), + .din(an_ac_coreid_d), + .dout(an_ac_coreid_q) + ); + + //--------------------------------------------------------------------- + // abist latches + //--------------------------------------------------------------------- + + tri_rlmreg_p #(.INIT(0), .WIDTH(25), .NEEDS_SRESET(1)) abist_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pc_lq_abist_ena_dc), + .thold_b(abst_sl_thold_0_b), + .sg(sg_0), + .force_t(abst_sl_force), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .d_mode(d_mode_dc), + .scin(abist_siv[0:24]), + .scout(abist_sov[0:24]), + .din({pc_lq_abist_wl64_comp_ena, + pc_lq_abist_g8t_wenb, + pc_lq_abist_g8t1p_renb_0, + pc_lq_abist_g8t_dcomp, + pc_lq_abist_g8t_bw_1, + pc_lq_abist_g8t_bw_0, + pc_lq_abist_di_0, + pc_lq_abist_waddr_0, + pc_lq_abist_raddr_0}), + .dout({pc_lq_abist_wl64_comp_ena_q, + pc_lq_abist_g8t_wenb_q, + pc_lq_abist_g8t1p_renb_0_q, + pc_lq_abist_g8t_dcomp_q, + pc_lq_abist_g8t_bw_1_q, + pc_lq_abist_g8t_bw_0_q, + pc_lq_abist_di_0_q, + pc_lq_abist_waddr_0_q, + pc_lq_abist_raddr_0_q}) + ); + + //----------------------------------------------- + // Pervasive + //----------------------------------------------- + + tri_plat #(.WIDTH(10)) perv_2to1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(pc_lq_ccflush_dc), + .din({func_nsl_thold_2, + func_sl_thold_2, + func_slp_sl_thold_2, + ary_nsl_thold_2, + abst_sl_thold_2, + time_sl_thold_2, + repr_sl_thold_2, + bolt_sl_thold_2, + sg_2, + fce_2}), + .q({func_nsl_thold_1, + func_sl_thold_1, + func_slp_sl_thold_1, + ary_nsl_thold_1, + abst_sl_thold_1, + time_sl_thold_1, + repr_sl_thold_1, + bolt_sl_thold_1, + sg_1, + fce_1}) + ); + + + tri_plat #(.WIDTH(10)) perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(pc_lq_ccflush_dc), + .din({func_nsl_thold_1, + func_sl_thold_1, + func_slp_sl_thold_1, + ary_nsl_thold_1, + abst_sl_thold_1, + time_sl_thold_1, + repr_sl_thold_1, + bolt_sl_thold_1, + sg_1, + fce_1}), + .q({func_nsl_thold_0, + func_sl_thold_0, + func_slp_sl_thold_0, + ary_nsl_thold_0, + abst_sl_thold_0, + time_sl_thold_0, + repr_sl_thold_0, + bolt_sl_thold_0, + sg_0, + fce_0}) + ); + + + tri_lcbor perv_lcbor_func_sl( + .clkoff_b(clkoff_dc_b), + .thold(func_sl_thold_0), + .sg(sg_0), + .act_dis(tidn), + .force_t(func_sl_force), + .thold_b(func_sl_thold_0_b) + ); + + + tri_lcbor perv_lcbor_func_slp_sl( + .clkoff_b(clkoff_dc_b), + .thold(func_slp_sl_thold_0), + .sg(sg_0), + .act_dis(tidn), + .force_t(func_slp_sl_force), + .thold_b(func_slp_sl_thold_0_b) + ); + + + tri_lcbor perv_lcbor_func_nsl( + .clkoff_b(clkoff_dc_b), + .thold(func_nsl_thold_0), + .sg(fce_0), + .act_dis(tidn), + .force_t(func_nsl_force), + .thold_b(func_nsl_thold_0_b) + ); + + + tri_lcbor perv_lcbor_abst_sl( + .clkoff_b(clkoff_dc_b), + .thold(abst_sl_thold_0), + .sg(sg_0), + .act_dis(tidn), + .force_t(abst_sl_force), + .thold_b(abst_sl_thold_0_b) + ); + + // LCBs for scan only staging latches + assign slat_force = sg_0; + assign abst_slat_thold_b = (~abst_sl_thold_0); + assign time_slat_thold_b = (~time_sl_thold_0); + assign repr_slat_thold_b = (~repr_sl_thold_0); + assign func_slat_thold_b = (~func_sl_thold_0); + + + tri_lcbs perv_lcbs_abst( + .vd(vdd), + .gd(gnd), + .delay_lclkr(delay_lclkr_dc), + .nclk(nclk), + .force_t(slat_force), + .thold_b(abst_slat_thold_b), + .dclk(abst_slat_d2clk), + .lclk(abst_slat_lclk) + ); + + + tri_slat_scan #(.WIDTH(4), .INIT(4'b0000)) perv_abst_stg( + .vd(vdd), + .gd(gnd), + .dclk(abst_slat_d2clk), + .lclk(abst_slat_lclk), + .scan_in({abst_scan_in, + abst_scan_out_int[0], + abst_scan_out_int[1], + abst_scan_out_int[2]}), + .scan_out({abst_scan_in_q, + abst_scan_out_q[0], + abst_scan_out_q[1], + abst_scan_out_q[2]}), + .q(abst_scan_q), + .q_b(abst_scan_q_b) + ); + + + tri_lcbs perv_lcbs_time( + .vd(vdd), + .gd(gnd), + .delay_lclkr(delay_lclkr_dc), + .nclk(nclk), + .force_t(slat_force), + .thold_b(time_slat_thold_b), + .dclk(time_slat_d2clk), + .lclk(time_slat_lclk) + ); + + + tri_slat_scan #(.WIDTH(3), .INIT(3'b000)) perv_time_stg( + .vd(vdd), + .gd(gnd), + .dclk(time_slat_d2clk), + .lclk(time_slat_lclk), + .scan_in({time_scan_in, + time_scan_out_int[0], + time_scan_out_int[1]}), + .scan_out({time_scan_in_q, + time_scan_out_q[0], + time_scan_out_q[1]}), + .q(time_scan_q), + .q_b(time_scan_q_b) + ); + + + tri_lcbs perv_lcbs_repr( + .vd(vdd), + .gd(gnd), + .delay_lclkr(delay_lclkr_dc), + .nclk(nclk), + .force_t(slat_force), + .thold_b(repr_slat_thold_b), + .dclk(repr_slat_d2clk), + .lclk(repr_slat_lclk) + ); + + + tri_slat_scan #(.WIDTH(3), .INIT(3'b000)) perv_repr_stg( + .vd(vdd), + .gd(gnd), + .dclk(repr_slat_d2clk), + .lclk(repr_slat_lclk), + .scan_in({repr_scan_in, + repr_scan_out_int[0], + repr_scan_out_int[1]}), + .scan_out({repr_scan_in_q, + repr_scan_out_q[0], + repr_scan_out_q[1]}), + .q(repr_scan_q), + .q_b(repr_scan_q_b) + ); + + + tri_lcbs perv_lcbs_func( + .vd(vdd), + .gd(gnd), + .delay_lclkr(delay_lclkr_dc), + .nclk(nclk), + .force_t(slat_force), + .thold_b(func_slat_thold_b), + .dclk(func_slat_d2clk), + .lclk(func_slat_lclk) + ); + + + tri_slat_scan #(.WIDTH(14), .INIT(14'b00000000000000)) perv_func_stg( + .vd(vdd), + .gd(gnd), + .dclk(func_slat_d2clk), + .lclk(func_slat_lclk), + .scan_in({func_scan_in[0], + func_scan_in[1], + func_scan_in[2], + func_scan_in[3], + func_scan_in[4], + func_scan_in[5], + func_scan_in[6], + func_scan_out_int[0], + func_scan_out_int[1], + func_scan_out_int[2], + func_scan_out_int[3], + func_scan_out_int[4], + func_scan_out_int[5], + func_scan_out_int[6]}), + .scan_out({func_scan_in_q[0], + func_scan_in_q[1], + func_scan_in_q[2], + func_scan_in_q[3], + func_scan_in_q[4], + func_scan_in_q[5], + func_scan_in_q[6], + func_scan_out_q[0], + func_scan_out_q[1], + func_scan_out_q[2], + func_scan_out_q[3], + func_scan_out_q[4], + func_scan_out_q[5], + func_scan_out_q[6]}), + .q(func_scan_q), + .q_b(func_scan_q_b) + ); + + assign siv[0:scan_right] = {sov[1:scan_right], func_scan_in_q[5]}; + assign func_scan_out_int[5] = sov[0]; + + assign func_scan_out_int[6] = func_scan_in_q[6]; + + assign abist_siv = {abist_sov[1:24], abst_scan_out_q[0]}; + assign abst_scan_out_int[1] = abist_sov[0]; + +endmodule diff --git a/dev/verilog/work/lq_odq.v b/dev/verilog/work/lq_odq.v new file mode 100755 index 0000000..8b5f9ed --- /dev/null +++ b/dev/verilog/work/lq_odq.v @@ -0,0 +1,4080 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// +// Description: XU LSU Order Queue +// +//***************************************************************************** + +`include "tri_a2o.vh" + +module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) + rv_lq_rv1_i0_vld, + rv_lq_rv1_i0_ucode_preissue, + rv_lq_rv1_i0_s3_t, + rv_lq_rv1_i0_rte_lq, + rv_lq_rv1_i0_rte_sq, + rv_lq_rv1_i0_isLoad, + rv_lq_rv1_i0_isStore, + rv_lq_rv1_i0_itag, + rv_lq_rv1_i1_vld, + rv_lq_rv1_i1_ucode_preissue, + rv_lq_rv1_i1_s3_t, + rv_lq_rv1_i1_rte_lq, + rv_lq_rv1_i1_rte_sq, + rv_lq_rv1_i1_isLoad, + rv_lq_rv1_i1_isStore, + rv_lq_rv1_i1_itag, + ldq_odq_vld, + ldq_odq_tid, + ldq_odq_wimge_i, + ldq_odq_inv, + ldq_odq_hit, + ldq_odq_fwd, + ldq_odq_addr, + ldq_odq_bytemask, + ldq_odq_itag, + ldq_odq_cline_chk, + ldq_odq_ex6_pEvents, + ctl_lsq_ex6_ldh_dacrw, + ldq_odq_upd_val, + ldq_odq_upd_itag, + ldq_odq_upd_nFlush, + ldq_odq_upd_np1Flush, + ldq_odq_upd_tid, + ldq_odq_upd_dacrw, + ldq_odq_upd_eccue, + ldq_odq_upd_pEvents, + ldq_odq_pfetch_vld, + odq_ldq_resolved, + odq_ldq_report_needed, + odq_ldq_report_itag, + odq_ldq_n_flush, + odq_ldq_np1_flush, + odq_ldq_report_tid, + odq_ldq_report_dacrw, + odq_ldq_report_eccue, + odq_ldq_report_pEvents, + odq_stq_resolved, + odq_stq_stTag, + odq_ldq_oldest_ld_tid, + odq_ldq_oldest_ld_itag, + odq_ldq_ex7_pfetch_blk, + lsq_ctl_oldest_tid, + lsq_ctl_oldest_itag, + ctl_lsq_ex2_thrd_id, + ctl_lsq_ex2_itag, + stq_odq_i0_stTag, + stq_odq_i1_stTag, + stq_odq_stq4_stTag_inval, + stq_odq_stq4_stTag, + odq_stq_ex2_nxt_oldest_val, + odq_stq_ex2_nxt_oldest_stTag, + odq_stq_ex2_nxt_youngest_val, + odq_stq_ex2_nxt_youngest_stTag, + iu_lq_cp_next_itag, + iu_lq_i0_completed, + iu_lq_i0_completed_itag, + iu_lq_i1_completed, + iu_lq_i1_completed_itag, + l2_back_inv_val, + l2_back_inv_addr, + iu_lq_cp_flush, + lq_iu_credit_free, + xu_lq_spr_xucr0_cls, + lsq_perv_odq_events, + vdd, + gnd, + nclk, + sg_0, + func_sl_thold_0_b, + func_sl_force, + d_mode_dc, + delay_lclkr_dc, + mpw1_dc_b, + mpw2_dc_b, + scan_in, + scan_out +); + + // Parameters used from tri_a2o.vh + // parameter THREADS = 2; // number of threads + // parameter LDSTQ_ENTRIES = 16; // Load Queue Size + // parameter LDSTQ_ENTRIES_ENC = 4; // Load Queue array address width + // parameter STQ_ENTRIES_ENC = 4; // Store Queue Entries Encoded + // parameter STQ_ENTRIES = 12; // Number of Store Queue Entries + // parameter ITAG_SIZE_ENC = 7; // ITag Size + // parameter DC_SIZE = 15 // 14 => 16K L1D$, 15 => 32K L1D$ + // parameter CL_SIZE = 6; // 6 => 64B CLINE, 7 => 128B CLINE + // parameter REAL_IFAR_WIDTH = 42; + parameter DACR_WIDTH = 4; + + + // IU interface to RV for instruction insertion + // port 0 + input [0:`THREADS-1] rv_lq_rv1_i0_vld; + input rv_lq_rv1_i0_ucode_preissue; + input [0:2] rv_lq_rv1_i0_s3_t; + input rv_lq_rv1_i0_rte_lq; + input rv_lq_rv1_i0_rte_sq; + input rv_lq_rv1_i0_isLoad; + input rv_lq_rv1_i0_isStore; + input [0:`ITAG_SIZE_ENC-1] rv_lq_rv1_i0_itag; + + // port 1 + input [0:`THREADS-1] rv_lq_rv1_i1_vld; + input rv_lq_rv1_i1_ucode_preissue; + input [0:2] rv_lq_rv1_i1_s3_t; + input rv_lq_rv1_i1_rte_lq; + input rv_lq_rv1_i1_rte_sq; + input rv_lq_rv1_i1_isLoad; + input rv_lq_rv1_i1_isStore; + input [0:`ITAG_SIZE_ENC-1] rv_lq_rv1_i1_itag; + + // + // These interfaces from ldq are mutually exlcusive + // You can either update and entry or remove an entry + // Interface between ldstq and orderq + input ldq_odq_vld; + input [0:`THREADS-1] ldq_odq_tid; + input ldq_odq_wimge_i; + input ldq_odq_inv; + input ldq_odq_hit; + input ldq_odq_fwd; + input [64-`REAL_IFAR_WIDTH:59] ldq_odq_addr; + input [0:15] ldq_odq_bytemask; + input [0:`ITAG_SIZE_ENC-1] ldq_odq_itag; + input ldq_odq_cline_chk; + input [0:3] ldq_odq_ex6_pEvents; + + // DACRW results for Load hits, 1 cycle after ldq_odq_vld + input [0:DACR_WIDTH-1] ctl_lsq_ex6_ldh_dacrw; + + // second update bus from lq + input ldq_odq_upd_val; + input [0:`ITAG_SIZE_ENC-1] ldq_odq_upd_itag; + input ldq_odq_upd_nFlush; + input ldq_odq_upd_np1Flush; + input [0:`THREADS-1] ldq_odq_upd_tid; + input [0:DACR_WIDTH-1] ldq_odq_upd_dacrw; + input ldq_odq_upd_eccue; + input [0:3] ldq_odq_upd_pEvents; + input ldq_odq_pfetch_vld; + + // send indicator, valid with itag to ldq + output odq_ldq_resolved; + output odq_ldq_report_needed; + output [0:`ITAG_SIZE_ENC-1] odq_ldq_report_itag; + output odq_ldq_n_flush; + output odq_ldq_np1_flush; + output [0:`THREADS-1] odq_ldq_report_tid; + output [0:DACR_WIDTH-1] odq_ldq_report_dacrw; + output odq_ldq_report_eccue; + output [0:3] odq_ldq_report_pEvents; + output odq_stq_resolved; + output [0:`STQ_ENTRIES-1] odq_stq_stTag; + + output [0:`THREADS-1] odq_ldq_oldest_ld_tid; + output [0:`ITAG_SIZE_ENC-1] odq_ldq_oldest_ld_itag; + output odq_ldq_ex7_pfetch_blk; + + output [0:`THREADS-1] lsq_ctl_oldest_tid; + output [0:`ITAG_SIZE_ENC-1] lsq_ctl_oldest_itag; + + // Age Detection + // need to determine age for this load in ex2 + input [0:`THREADS-1] ctl_lsq_ex2_thrd_id; + input [0:`ITAG_SIZE_ENC-1] ctl_lsq_ex2_itag; + + // store tag used when instruction was inserted to store queue + input [0:`STQ_ENTRIES_ENC-1] stq_odq_i0_stTag; + input [0:`STQ_ENTRIES_ENC-1] stq_odq_i1_stTag; + + // store tag is committed, remove from order queue and dont compare against it + input stq_odq_stq4_stTag_inval; + input [0:`STQ_ENTRIES_ENC-1] stq_odq_stq4_stTag; + + // order queue closest oldest store to the ex2 load request + output odq_stq_ex2_nxt_oldest_val; + output [0:`STQ_ENTRIES-1] odq_stq_ex2_nxt_oldest_stTag; + + // order queue closest youngest store to the ex2 load request + output odq_stq_ex2_nxt_youngest_val; + output [0:`STQ_ENTRIES-1] odq_stq_ex2_nxt_youngest_stTag; + + // CP_NEXT Itag + input [0:(`THREADS * `ITAG_SIZE_ENC)-1] iu_lq_cp_next_itag; + + // Commit Report + input [0:`THREADS-1] iu_lq_i0_completed; + input [0:(`THREADS * `ITAG_SIZE_ENC)-1] iu_lq_i0_completed_itag; + input [0:`THREADS-1] iu_lq_i1_completed; + input [0:(`THREADS * `ITAG_SIZE_ENC)-1] iu_lq_i1_completed_itag; + + // Back-Invalidate Valid + input l2_back_inv_val; + input [67-`DC_SIZE:63-`CL_SIZE] l2_back_inv_addr; + + // flush interface + input [0:`THREADS-1] iu_lq_cp_flush; + + // return credit to iu + output [0:`THREADS-1] lq_iu_credit_free; + + // mode bit + input xu_lq_spr_xucr0_cls; + + // Performance Events + output [0:4+`THREADS-1] lsq_perv_odq_events; + + // TODO: What else??? + + // Pervasive + + + inout vdd; + + + inout gnd; + + (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) + + input [0:`NCLK_WIDTH-1] nclk; + input sg_0; + input func_sl_thold_0_b; + input func_sl_force; + input d_mode_dc; + input delay_lclkr_dc; + input mpw1_dc_b; + input mpw2_dc_b; + + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + + input scan_in; + + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + + output scan_out; + + //-------------------------- + // signals + //-------------------------- + wire [0:`LDSTQ_ENTRIES-1] remove_entry_base; + wire [0:`LDSTQ_ENTRIES-1] compress_vector; + wire compress_val; + wire [0:`LDSTQ_ENTRIES_ENC-1] compress_entry; + wire [0:`LDSTQ_ENTRIES-1] remove_entry_vec; + reg [0:`LDSTQ_ENTRIES_ENC-1] remove_entry; + reg [0:`THREADS-1] remove_tid; + + wire [67-`DC_SIZE:63-`CL_SIZE] oldest_entry_p0_cclass; + wire [67-`DC_SIZE:63-`CL_SIZE] oldest_entry_p1_cclass; + wire oldest_entry_p0_m_rv0; + wire oldest_entry_p1_m_rv0; + wire oldest_entry_p1_m_rv1; + wire oldest_entry_p1_m_ex0; + wire oldest_entry_p1_m_ex1; + wire oldest_entry_p1_m_ex2; + wire oldest_entry_p1_m_ex3; + wire oldest_entry_p1_m_ex4; + wire oldest_entry_p1_m_ex5; + wire entry_rv1_blk_d; + wire entry_rv1_blk_q; + wire entry_ex0_blk_d; + wire entry_ex0_blk_q; + wire entry_ex1_blk_d; + wire entry_ex1_blk_q; + wire entry_ex2_blk_d; + wire entry_ex2_blk_q; + wire entry_ex3_blk_d; + wire entry_ex3_blk_q; + wire entry_ex4_blk_d; + wire entry_ex4_blk_q; + wire entry_ex5_blk_d; + wire entry_ex5_blk_q; + wire entry_ex6_blk_d; + wire entry_ex6_blk_q; + wire oldest_entry_blk; + + // Order Queue field values + reg orderq_entry_inuse_d[0:`LDSTQ_ENTRIES-1]; // order queue entry in use + wire orderq_entry_inuse_q[0:`LDSTQ_ENTRIES-1]; + reg [0:`THREADS-1] orderq_entry_tid_d[0:`LDSTQ_ENTRIES-1]; // order queue entry thread ID + wire [0:`THREADS-1] orderq_entry_tid_q[0:`LDSTQ_ENTRIES-1]; + reg orderq_entry_val_d[0:`LDSTQ_ENTRIES-1]; // order queue entry valid + wire orderq_entry_val_q[0:`LDSTQ_ENTRIES-1]; + reg orderq_entry_ld_d[0:`LDSTQ_ENTRIES-1]; // order queue entry is load + wire orderq_entry_ld_q[0:`LDSTQ_ENTRIES-1]; + reg orderq_entry_efs_d[0:`LDSTQ_ENTRIES-1]; // order queue entry needs to stay in order + wire orderq_entry_efs_q[0:`LDSTQ_ENTRIES-1]; + reg orderq_entry_i_d[0:`LDSTQ_ENTRIES-1]; // order queue entry is caching-inhibited + wire orderq_entry_i_q[0:`LDSTQ_ENTRIES-1]; + reg orderq_entry_hit_d[0:`LDSTQ_ENTRIES-1]; // order queue entry is hit + wire orderq_entry_hit_q[0:`LDSTQ_ENTRIES-1]; + reg orderq_entry_fwd_d[0:`LDSTQ_ENTRIES-1]; // order queue entry forwarded from store queue + wire orderq_entry_fwd_q[0:`LDSTQ_ENTRIES-1]; + reg orderq_entry_cls_op_d[0:`LDSTQ_ENTRIES-1]; // order queue op requires full cacheline compare + wire orderq_entry_cls_op_q[0:`LDSTQ_ENTRIES-1]; + reg [0:DACR_WIDTH-1] orderq_entry_dacrw_d[0:`LDSTQ_ENTRIES-1]; // order queue entry DACRW results for load hits only + wire [0:DACR_WIDTH-1] orderq_entry_dacrw_q[0:`LDSTQ_ENTRIES-1]; + reg orderq_entry_eccue_d[0:`LDSTQ_ENTRIES-1]; // order queue entry had an ECC_UE on the L2 interface + wire orderq_entry_eccue_q[0:`LDSTQ_ENTRIES-1]; + reg [0:3] orderq_entry_pEvents_d[0:`LDSTQ_ENTRIES-1]; // order queue entry Performance Events result + wire [0:3] orderq_entry_pEvents_q[0:`LDSTQ_ENTRIES-1]; + reg orderq_entry_pre_d[0:`LDSTQ_ENTRIES-1]; // order queue entry resolved idication has been sent to ldq + wire orderq_entry_pre_q[0:`LDSTQ_ENTRIES-1]; + reg orderq_entry_instq_d[0:`LDSTQ_ENTRIES-1]; // order queue entry is a store queue request + wire orderq_entry_instq_q[0:`LDSTQ_ENTRIES-1]; + reg orderq_entry_flushed_d[0:`LDSTQ_ENTRIES-1]; // order queue entry has been flushed + wire orderq_entry_flushed_q[0:`LDSTQ_ENTRIES-1]; + reg orderq_entry_myflush_d[0:`LDSTQ_ENTRIES-1]; // order queue entry has been flushed + wire orderq_entry_myflush_q[0:`LDSTQ_ENTRIES-1]; + reg orderq_entry_ld_chk_d[0:`LDSTQ_ENTRIES-1]; // order queue entry load needs collision check + wire orderq_entry_ld_chk_q[0:`LDSTQ_ENTRIES-1]; + reg [0:`STQ_ENTRIES_ENC-1] orderq_entry_stTag_d[0:`LDSTQ_ENTRIES-1]; // order queue entry Store Tag + wire [0:`STQ_ENTRIES_ENC-1] orderq_entry_stTag_q[0:`LDSTQ_ENTRIES-1]; + reg orderq_entry_cmmt_d[0:`LDSTQ_ENTRIES-1]; // order queue entry has been committed + wire orderq_entry_cmmt_q[0:`LDSTQ_ENTRIES-1]; + + reg orderq_entry_bi_flag_d[0:`LDSTQ_ENTRIES-1]; // order queue entry had a back invalidate come in after it + wire orderq_entry_bi_flag_q[0:`LDSTQ_ENTRIES-1]; + reg orderq_entry_bi_flush_d[0:`LDSTQ_ENTRIES-1]; // order queue entry needs to be flushed due to back invalidate + wire orderq_entry_bi_flush_q[0:`LDSTQ_ENTRIES-1]; + + reg orderq_entry_val2_d[0:`LDSTQ_ENTRIES-1]; // order queue entry valid for second update bus + wire orderq_entry_val2_q[0:`LDSTQ_ENTRIES-1]; + reg orderq_entry_n_flush_d[0:`LDSTQ_ENTRIES-1]; // order queue entry needs to be np flushed due to back invalidate + wire orderq_entry_n_flush_q[0:`LDSTQ_ENTRIES-1]; + reg orderq_entry_np1_flush_d[0:`LDSTQ_ENTRIES-1]; // order queue entry needs to be np1 flushed due to back invalidate + wire orderq_entry_np1_flush_q[0:`LDSTQ_ENTRIES-1]; + reg orderq_entry_update_pulse_d[0:`LDSTQ_ENTRIES-1];// order queue entry update pulse. Indicates that the entry just became valid. + wire orderq_entry_update_pulse_q[0:`LDSTQ_ENTRIES-1];// it should only be on for a single cycle. + + reg [0:`ITAG_SIZE_ENC-1] orderq_entry_itag_d[0:`LDSTQ_ENTRIES-1]; // order queue entry itag + wire [0:`ITAG_SIZE_ENC-1] orderq_entry_itag_q[0:`LDSTQ_ENTRIES-1]; + + // Address Queue field values + reg addrq_entry_inuse_d[0:`LDSTQ_ENTRIES-1]; // addr queue entry in use + wire addrq_entry_inuse_q[0:`LDSTQ_ENTRIES-1]; + reg addrq_entry_val_d[0:`LDSTQ_ENTRIES-1]; // addr queue entry valid + wire addrq_entry_val_q[0:`LDSTQ_ENTRIES-1]; + reg [0:`THREADS-1] addrq_entry_tid_d[0:`LDSTQ_ENTRIES-1]; // addr queue entry thread ID + wire [0:`THREADS-1] addrq_entry_tid_q[0:`LDSTQ_ENTRIES-1]; + reg [0:`ITAG_SIZE_ENC-1] addrq_entry_itag_d[0:`LDSTQ_ENTRIES-1]; // addr queue entry itag + wire [0:`ITAG_SIZE_ENC-1] addrq_entry_itag_q[0:`LDSTQ_ENTRIES-1]; + reg [64-`REAL_IFAR_WIDTH:59] addrq_entry_address_d[0:`LDSTQ_ENTRIES-1]; // addr queue address + wire [64-`REAL_IFAR_WIDTH:59] addrq_entry_address_q[0:`LDSTQ_ENTRIES-1]; + reg [0:15] addrq_entry_bytemask_d[0:`LDSTQ_ENTRIES-1]; // addr queue byte mask + wire [0:15] addrq_entry_bytemask_q[0:`LDSTQ_ENTRIES-1]; + + wire compress_val_d; + wire compress_val_q; + + + // port 0 + wire [0:`THREADS-1] ex0_i0_vld_q; + wire ex0_i0_rte_lq_q; + wire ex0_i0_rte_sq_q; + wire ex0_i0_ucode_preissue_q; + wire [0:2] ex0_i0_s3_t_q; + wire ex0_i0_isLoad_q; + wire ex0_i0_isStore_q; + wire [0:`ITAG_SIZE_ENC-1] ex0_i0_itag_q; + + wire [0:`THREADS-1] ex1_i0_vld_d; + wire [0:`THREADS-1] ex1_i0_vld_q; + wire ex1_i0_pre_d; + wire ex1_i0_pre_q; + wire ex1_i0_isLoad_d; + wire ex1_i0_isLoad_q; + wire [0:`ITAG_SIZE_ENC-1] ex1_i0_itag_d; + wire [0:`ITAG_SIZE_ENC-1] ex1_i0_itag_q; + + // port 1 + wire [0:`THREADS-1] ex0_i1_vld_q; + wire ex0_i1_rte_lq_q; + wire ex0_i1_rte_sq_q; + wire ex0_i1_ucode_preissue_q; + wire [0:2] ex0_i1_s3_t_q; + wire ex0_i1_isLoad_q; + wire ex0_i1_isStore_q; + wire [0:`ITAG_SIZE_ENC-1] ex0_i1_itag_q; + + wire [0:`THREADS-1] ex1_i1_vld_d; + wire [0:`THREADS-1] ex1_i1_vld_q; + wire ex1_i1_pre_d; + wire ex1_i1_pre_q; + wire ex1_i1_isLoad_d; + wire ex1_i1_isLoad_q; + wire [0:`ITAG_SIZE_ENC-1] ex1_i1_itag_d; + wire [0:`ITAG_SIZE_ENC-1] ex1_i1_itag_q; + + + wire [0:`LDSTQ_ENTRIES] next_fill_ptr_d; + wire [0:`LDSTQ_ENTRIES] next_fill_ptr_q; + + wire [0:`LDSTQ_ENTRIES_ENC-1] flushed_credit_count_d[0:`THREADS-1]; + wire [0:`LDSTQ_ENTRIES_ENC-1] flushed_credit_count_q[0:`THREADS-1]; + + wire [0:`THREADS-1] cp_flush_d; + wire [0:`THREADS-1] cp_flush_q; + wire [0:`THREADS-1] cp_flush2_d; + wire [0:`THREADS-1] cp_flush2_q; + wire [0:`THREADS-1] cp_flush3_d; + wire [0:`THREADS-1] cp_flush3_q; + wire [0:`THREADS-1] cp_flush4_d; + wire [0:`THREADS-1] cp_flush4_q; + wire [0:`THREADS-1] cp_flush5_d; + wire [0:`THREADS-1] cp_flush5_q; + + wire xu_lq_spr_xucr0_cls_q; + wire [0:`THREADS-1] lq_iu_credit_free_d; + wire [0:`THREADS-1] lq_iu_credit_free_q; + + // pipeline latches for ldq_odq interface + wire ldq_odq_vld_q; + wire [0:`THREADS-1] ldq_odq_tid_q; + wire ldq_odq_inv_q; + wire ldq_odq_wimge_i_q; + wire ldq_odq_hit_q; + wire ldq_odq_fwd_q; + wire [0:`ITAG_SIZE_ENC-1] ldq_odq_itag_q; + wire ldq_odq_cline_chk_q; + wire [0:`ITAG_SIZE_ENC-1] iu_lq_cp_next_itag_q[0:`THREADS-1]; + wire [0:`THREADS-1] cp_i0_completed_q; + wire [0:`ITAG_SIZE_ENC-1] cp_i0_completed_itag_q[0:`THREADS-1]; + wire [0:`THREADS-1] cp_i1_completed_q; + wire [0:`ITAG_SIZE_ENC-1] cp_i1_completed_itag_q[0:`THREADS-1]; + + // extra entry is source for compressing the 15th entry + reg orderq_entry_inuse_next[0:`LDSTQ_ENTRIES]; // order queue entry in use + reg [0:`THREADS-1] orderq_entry_tid_next[0:`LDSTQ_ENTRIES]; // order queue entry thread id + reg orderq_entry_val_next[0:`LDSTQ_ENTRIES]; // order queue entry valid + reg orderq_entry_ld_next[0:`LDSTQ_ENTRIES]; // order queue entry is load + reg orderq_entry_efs_next[0:`LDSTQ_ENTRIES]; // order queue entry is load + reg orderq_entry_i_next[0:`LDSTQ_ENTRIES]; // order queue entry is caching-inhibited + reg orderq_entry_hit_next[0:`LDSTQ_ENTRIES]; // order queue entry is cache hit + reg orderq_entry_fwd_next[0:`LDSTQ_ENTRIES]; // order queue entry forwarded from store queue + reg orderq_entry_cls_op_next[0:`LDSTQ_ENTRIES]; // order queue entry is cachline sized operation + reg [0:DACR_WIDTH-1] orderq_entry_dacrw_next[0:`LDSTQ_ENTRIES]; // order queue entry DACRW results for load hits + reg orderq_entry_eccue_next[0:`LDSTQ_ENTRIES]; // order queue entry ECC_UE results + reg [0:3] orderq_entry_pEvents_next[0:`LDSTQ_ENTRIES]; // order queue entry Performance Events results + reg orderq_entry_pre_next[0:`LDSTQ_ENTRIES]; // order queue entry resolved idication has been sent to ldq + reg orderq_entry_instq_next[0:`LDSTQ_ENTRIES]; // order queue entry is a store queue request + reg orderq_entry_flushed_next[0:`LDSTQ_ENTRIES]; // order queue entry has been flushed + reg orderq_entry_myflush_next[0:`LDSTQ_ENTRIES]; // order queue entry has been flushed + reg orderq_entry_ld_chk_next[0:`LDSTQ_ENTRIES]; // order queue entries reload data is ready + reg [0:`STQ_ENTRIES_ENC-1] orderq_entry_stTag_next[0:`LDSTQ_ENTRIES]; // order queue entry Store Tag + reg orderq_entry_cmmt_next[0:`LDSTQ_ENTRIES]; // order queue entry has been committed + reg orderq_entry_bi_flag_next[0:`LDSTQ_ENTRIES]; // order queue entry is a back invalidate + reg orderq_entry_bi_flush_next[0:`LDSTQ_ENTRIES]; // order queue entry is flushed due to back invalidate + reg orderq_entry_val2_next[0:`LDSTQ_ENTRIES]; // order queue entry valid for second update bus + reg orderq_entry_n_flush_next[0:`LDSTQ_ENTRIES]; // order queue entry is np flushed due to back invalidate + reg orderq_entry_np1_flush_next[0:`LDSTQ_ENTRIES]; // order queue entry is np1 flushed due to back invalidate + reg orderq_entry_update_pulse_next[0:`LDSTQ_ENTRIES]; // order queue entry update pulse, on for 1 cycle with val + reg [0:`ITAG_SIZE_ENC-1] orderq_entry_itag_next[0:`LDSTQ_ENTRIES]; // order queue entry itag + wire [0:`STQ_ENTRIES-1] orderq_entry_stTag_1hot[0:`LDSTQ_ENTRIES-1]; // order queue entry 1-hot Store Tag + wire orderq_entry_instq_inval[0:`LDSTQ_ENTRIES-1]; // order queue entry needs to invalidate instq state bit + reg [0:`ITAG_SIZE_ENC-1] oderq_entry_i0_comp_itag[0:`LDSTQ_ENTRIES-1]; // order queue entry committed itag on I0 bus + reg [0:`ITAG_SIZE_ENC-1] oderq_entry_i1_comp_itag[0:`LDSTQ_ENTRIES-1]; // order queue entry committed itag on I1 bus + wire orderq_entry_i0_cmmt[0:`LDSTQ_ENTRIES-1]; // order queue entry committed on I0 bus + wire orderq_entry_i1_cmmt[0:`LDSTQ_ENTRIES-1]; // order queue entry committed on I1 bus + wire orderq_entry_cmmt[0:`LDSTQ_ENTRIES-1]; // order queue entry committed + + reg addrq_entry_inuse_next[0:`LDSTQ_ENTRIES]; // addr queue entry in use + reg addrq_entry_val_next[0:`LDSTQ_ENTRIES]; // addr queue entry valid + reg [0:`THREADS-1] addrq_entry_tid_next[0:`LDSTQ_ENTRIES]; // addr queue entry thread ID + reg [0:`ITAG_SIZE_ENC-1] addrq_entry_itag_next[0:`LDSTQ_ENTRIES]; // order queue entry itag + reg [64-`REAL_IFAR_WIDTH:59] addrq_entry_address_next[0:`LDSTQ_ENTRIES]; // addr queue address + reg [0:15] addrq_entry_bytemask_next[0:`LDSTQ_ENTRIES]; // addr queue byte mask + + wire [0:`LDSTQ_ENTRIES-1] collision_vector_pre; + wire [0:`LDSTQ_ENTRIES-1] collision_vector; + wire [0:`LDSTQ_ENTRIES-1] collision_vector_d; + wire [0:`LDSTQ_ENTRIES-1] collision_vector_q; + + reg [0:`LDSTQ_ENTRIES-1] flush_vector_pre; + wire [0:`LDSTQ_ENTRIES-1] flush_vector; + + wire [0:`LDSTQ_ENTRIES-1] collision_vector_new; + + wire [0:`LDSTQ_ENTRIES-1] ci_flush_detected; + wire [0:`LDSTQ_ENTRIES-1] forw_flush_detected; + wire [0:`LDSTQ_ENTRIES-1] store_flush_detected; + wire [0:`LDSTQ_ENTRIES-1] set_flush_condition; + + wire [0:2] next_fill_sel; + + wire instr0_vld; + wire instr1_vld; + + wire [0:`LDSTQ_ENTRIES-1] next_instr0_ptr; + wire [0:`LDSTQ_ENTRIES-1] next_instr1_ptr; + wire [0:`LDSTQ_ENTRIES-1] write_instr0; + wire [0:`LDSTQ_ENTRIES-1] write_instr1; + wire [0:`LDSTQ_ENTRIES-1] update_vld; + wire [0:`LDSTQ_ENTRIES-1] update2_vld; + wire [0:`LDSTQ_ENTRIES-1] cp_flush_entry; + + wire [0:`LDSTQ_ENTRIES-1] update_addrq_vld; + + reg [0:`LDSTQ_ENTRIES-1] store_collisions_ahead; + reg [0:`LDSTQ_ENTRIES-1] load_collisions_ahead; + reg [0:`LDSTQ_ENTRIES-1] forw_collisions_ahead; + + wire [0:`LDSTQ_ENTRIES-1] queue_entry_is_store; + wire [0:`LDSTQ_ENTRIES-1] queue_entry_is_load; + wire [0:`LDSTQ_ENTRIES-1] oo_collision_detected; + reg [0:`LDSTQ_ENTRIES-1] collision_check_mask; + + wire [0:`LDSTQ_ENTRIES-1] sent_early_flush; + + wire [0:`THREADS-1] inc0_flush_count; + wire [0:`THREADS-1] inc1_flush_count; + wire [0:2] flushed_credit_sel[0:`THREADS-1]; + wire [0:`THREADS-1] flush_credit_avail; + wire [0:`THREADS-1] flush_credit_free; + wire [0:`THREADS-1] flush_credit_token; + + wire compressed_store_collision; + wire [0:`LDSTQ_ENTRIES-1] temp_collision_flush; + + wire cl64; + + reg [0:`THREADS-1] oldest_unrsv_ld_tid; + reg [0:`ITAG_SIZE_ENC-1] oldest_unrsv_ld_itag; + wire [0:`LDSTQ_ENTRIES-1] unresolved_load; + + wire cacheline_size_check[0:`LDSTQ_ENTRIES-1]; + + wire [0:`ITAG_SIZE_ENC-1] oldest_rem_itag; + wire oldest_rem_n_flush_value; + wire oldest_rem_np1_flush_value; + wire oldest_rem_report_needed; + + wire oldest_rem_hit; + wire oldest_rem_is_nonflush_ld; + wire oldest_rem_instq; + wire [0:`STQ_ENTRIES-1] oldest_rem_stTag; + wire [0:DACR_WIDTH-1] oldest_rem_dacrw; + wire oldest_rem_eccue; + wire [0:3] oldest_rem_pEvents; + wire [0:`THREADS-1] oldest_rem_tid; + + wire [0:`LDSTQ_ENTRIES-1] binv_flush_detected; + + wire rv1_binv_val_d; + wire rv1_binv_val_q; + wire ex0_binv_val_d; + wire ex0_binv_val_q; + wire ex1_binv_val_d; + wire ex1_binv_val_q; + wire ex2_binv_val_d; + wire ex2_binv_val_q; + wire ex3_binv_val_d; + wire ex3_binv_val_q; + wire ex4_binv_val_d; + wire ex4_binv_val_q; + wire ex5_binv_val_d; + wire ex5_binv_val_q; + + // 64-(`DC_SIZE-3):63-`CL_SIZE = 67-`DC_SIZE:63-`CL_SIZE + wire [67-`DC_SIZE:63-`CL_SIZE] rv1_binv_addr_d; + wire [67-`DC_SIZE:63-`CL_SIZE] rv1_binv_addr_q; + wire [67-`DC_SIZE:63-`CL_SIZE] ex0_binv_addr_d; + wire [67-`DC_SIZE:63-`CL_SIZE] ex0_binv_addr_q; + wire [67-`DC_SIZE:63-`CL_SIZE] ex1_binv_addr_d; + wire [67-`DC_SIZE:63-`CL_SIZE] ex1_binv_addr_q; + wire [67-`DC_SIZE:63-`CL_SIZE] ex2_binv_addr_d; + wire [67-`DC_SIZE:63-`CL_SIZE] ex2_binv_addr_q; + wire [67-`DC_SIZE:63-`CL_SIZE] ex3_binv_addr_d; + wire [67-`DC_SIZE:63-`CL_SIZE] ex3_binv_addr_q; + wire [67-`DC_SIZE:63-`CL_SIZE] ex4_binv_addr_d; + wire [67-`DC_SIZE:63-`CL_SIZE] ex4_binv_addr_q; + wire [67-`DC_SIZE:63-`CL_SIZE] ex5_binv_addr_d; + wire [67-`DC_SIZE:63-`CL_SIZE] ex5_binv_addr_q; + + wire [0:`LDSTQ_ENTRIES-1] ex2_age_upper_ptr; + wire [0:`LDSTQ_ENTRIES-1] ex2_age_entry_younger; + wire [0:`LDSTQ_ENTRIES-1] ex2_age_entry_older; + wire [0:`LDSTQ_ENTRIES-1] ex2_age_younger_ptr; + wire [0:`LDSTQ_ENTRIES-1] ex2_age_older_ptr; + wire [0:`LDSTQ_ENTRIES-1] ex2_age_younger_st; + wire [0:`LDSTQ_ENTRIES-1] ex2_age_older_st; + wire [0:`LDSTQ_ENTRIES-1] ex2_nxt_youngest_ptr; + wire [0:`LDSTQ_ENTRIES-1] ex2_nxt_oldest_ptr; + reg [0:`STQ_ENTRIES-1] ex2_nxt_youngest_stTag; + reg [0:`STQ_ENTRIES-1] ex2_nxt_oldest_stTag; + + wire ex0_i0_src_xer; + wire ex0_i1_src_xer; + wire ex1_i0_instq_d; + wire ex1_i0_instq_q; + wire ex1_i1_instq_d; + wire ex1_i1_instq_q; + + wire ldq_odq_pfetch_vld_ex6_d; + wire ldq_odq_pfetch_vld_ex6_q; + wire odq_ldq_ex7_pfetch_blk_d; + wire odq_ldq_ex7_pfetch_blk_q; + + + + // these wires are to convert the ports at the top to an array of itags + wire [0:`ITAG_SIZE_ENC-1] iu_lq_cp_next_itag_int[0:`THREADS-1]; + wire [0:`ITAG_SIZE_ENC-1] iu_lq_i0_completed_itag_int[0:`THREADS-1]; + wire [0:`ITAG_SIZE_ENC-1] iu_lq_i1_completed_itag_int[0:`THREADS-1]; + + //---------------------------- + //-- constants + //---------------------------- + parameter orderq_entry_inuse_offset = 0; + parameter orderq_entry_tid_offset = orderq_entry_inuse_offset + `LDSTQ_ENTRIES; + parameter orderq_entry_val_offset = orderq_entry_tid_offset + (`LDSTQ_ENTRIES * `THREADS); + parameter orderq_entry_ld_offset = orderq_entry_val_offset + `LDSTQ_ENTRIES; + parameter orderq_entry_i_offset = orderq_entry_ld_offset + `LDSTQ_ENTRIES; + parameter orderq_entry_hit_offset = orderq_entry_i_offset + `LDSTQ_ENTRIES; + parameter orderq_entry_fwd_offset = orderq_entry_hit_offset + `LDSTQ_ENTRIES; + parameter orderq_entry_cls_op_offset = orderq_entry_fwd_offset + `LDSTQ_ENTRIES; + parameter orderq_entry_dacrw_offset = orderq_entry_cls_op_offset + `LDSTQ_ENTRIES; + parameter orderq_entry_eccue_offset = orderq_entry_dacrw_offset + (`LDSTQ_ENTRIES * DACR_WIDTH); + parameter orderq_entry_pEvents_offset = orderq_entry_eccue_offset + `LDSTQ_ENTRIES; + parameter orderq_entry_pre_offset = orderq_entry_pEvents_offset + (`LDSTQ_ENTRIES * 4); + parameter orderq_entry_instq_offset = orderq_entry_pre_offset + `LDSTQ_ENTRIES; + parameter orderq_entry_flushed_offset = orderq_entry_instq_offset + `LDSTQ_ENTRIES; + parameter orderq_entry_myflush_offset = orderq_entry_flushed_offset + `LDSTQ_ENTRIES; + parameter orderq_entry_itag_offset = orderq_entry_myflush_offset + `LDSTQ_ENTRIES; + parameter orderq_entry_ld_chk_offset = orderq_entry_itag_offset + (`LDSTQ_ENTRIES * `ITAG_SIZE_ENC); + parameter orderq_entry_stTag_offset = orderq_entry_ld_chk_offset + `LDSTQ_ENTRIES; + parameter orderq_entry_cmmt_offset = orderq_entry_stTag_offset + (`LDSTQ_ENTRIES * `STQ_ENTRIES_ENC); + parameter orderq_entry_bi_flag_offset = orderq_entry_cmmt_offset + `LDSTQ_ENTRIES; + parameter orderq_entry_bi_flush_offset = orderq_entry_bi_flag_offset + `LDSTQ_ENTRIES; + parameter orderq_entry_val2_offset = orderq_entry_bi_flush_offset + `LDSTQ_ENTRIES; + parameter orderq_entry_n_flush_offset = orderq_entry_val2_offset + `LDSTQ_ENTRIES; + parameter orderq_entry_np1_flush_offset = orderq_entry_n_flush_offset + `LDSTQ_ENTRIES; + parameter orderq_entry_update_pulse_offset = orderq_entry_np1_flush_offset + `LDSTQ_ENTRIES; + parameter orderq_entry_efs_offset = orderq_entry_update_pulse_offset + `LDSTQ_ENTRIES; + parameter addrq_entry_inuse_offset = orderq_entry_efs_offset + `LDSTQ_ENTRIES; + parameter addrq_entry_val_offset = addrq_entry_inuse_offset + `LDSTQ_ENTRIES; + parameter addrq_entry_tid_offset = addrq_entry_val_offset + `LDSTQ_ENTRIES; + parameter addrq_entry_itag_offset = addrq_entry_tid_offset + (`LDSTQ_ENTRIES * `THREADS); + parameter addrq_entry_address_offset = addrq_entry_itag_offset + (`LDSTQ_ENTRIES * `ITAG_SIZE_ENC); + parameter addrq_entry_bytemask_offset = addrq_entry_address_offset + (`LDSTQ_ENTRIES * (`REAL_IFAR_WIDTH - 4)); + parameter ex0_i0_vld_offset = addrq_entry_bytemask_offset + `LDSTQ_ENTRIES * 16; + parameter ex0_i0_rte_lq_offset = ex0_i0_vld_offset + `THREADS; + parameter ex0_i0_rte_sq_offset = ex0_i0_rte_lq_offset + 1; + parameter ex0_i0_isLoad_offset = ex0_i0_rte_sq_offset + 1; + parameter ex0_i0_ucode_preissue_offset = ex0_i0_isLoad_offset + 1; + parameter ex0_i0_s3_t_offset = ex0_i0_ucode_preissue_offset + 1; + parameter ex0_i0_isStore_offset = ex0_i0_s3_t_offset + 3; + parameter ex0_i0_itag_offset = ex0_i0_isStore_offset + 1; + parameter ex1_i0_vld_offset = ex0_i0_itag_offset + `ITAG_SIZE_ENC; + parameter ex1_i0_isLoad_offset = ex1_i0_vld_offset + `THREADS; + parameter ex1_i0_pre_offset = ex1_i0_isLoad_offset + 1; + parameter ex1_i0_instq_offset = ex1_i0_pre_offset + 1; + parameter ex1_i0_itag_offset = ex1_i0_instq_offset + 1; + parameter ex0_i1_vld_offset = ex1_i0_itag_offset + `ITAG_SIZE_ENC; + parameter ex0_i1_rte_lq_offset = ex0_i1_vld_offset + `THREADS; + parameter ex0_i1_rte_sq_offset = ex0_i1_rte_lq_offset + 1; + parameter ex0_i1_isLoad_offset = ex0_i1_rte_sq_offset + 1; + parameter ex0_i1_ucode_preissue_offset = ex0_i1_isLoad_offset + 1; + parameter ex0_i1_s3_t_offset = ex0_i1_ucode_preissue_offset + 1; + parameter ex0_i1_isStore_offset = ex0_i1_s3_t_offset + 3; + parameter ex0_i1_itag_offset = ex0_i1_isStore_offset + 1; + parameter ex1_i1_vld_offset = ex0_i1_itag_offset + `ITAG_SIZE_ENC; + parameter ex1_i1_isLoad_offset = ex1_i1_vld_offset + `THREADS; + parameter ex1_i1_pre_offset = ex1_i1_isLoad_offset + 1; + parameter ex1_i1_instq_offset = ex1_i1_pre_offset + 1; + parameter ex1_i1_itag_offset = ex1_i1_instq_offset + 1; + parameter ldq_odq_vld_offset = ex1_i1_itag_offset + `ITAG_SIZE_ENC; + parameter ldq_odq_tid_offset = ldq_odq_vld_offset + 1; + parameter ldq_odq_inv_offset = ldq_odq_tid_offset + `THREADS; + parameter ldq_odq_wimge_i_offset = ldq_odq_inv_offset + 1; + parameter ldq_odq_hit_offset = ldq_odq_wimge_i_offset + 1; + parameter ldq_odq_fwd_offset = ldq_odq_hit_offset + 1; + parameter ldq_odq_itag_offset = ldq_odq_fwd_offset + 1; + parameter iu_lq_cp_next_itag_offset = ldq_odq_itag_offset + `ITAG_SIZE_ENC; + parameter cp_i0_completed_offset = iu_lq_cp_next_itag_offset + (`ITAG_SIZE_ENC * `THREADS); + parameter cp_i0_completed_itag_offset = cp_i0_completed_offset + `THREADS; + parameter cp_i1_completed_offset = cp_i0_completed_itag_offset + (`THREADS * `ITAG_SIZE_ENC); + parameter cp_i1_completed_itag_offset = cp_i1_completed_offset + `THREADS; + parameter ldq_odq_cline_chk_offset = cp_i1_completed_itag_offset + (`THREADS * `ITAG_SIZE_ENC); + parameter next_fill_ptr_offset = ldq_odq_cline_chk_offset + 1; + parameter collision_vector_offset = next_fill_ptr_offset + (`LDSTQ_ENTRIES + 1); + parameter flushed_credit_count_offset = collision_vector_offset + `LDSTQ_ENTRIES; + parameter cp_flush_offset = flushed_credit_count_offset + (`LDSTQ_ENTRIES_ENC * `THREADS); + parameter cp_flush2_offset = cp_flush_offset + `THREADS; + parameter cp_flush3_offset = cp_flush2_offset + `THREADS; + parameter cp_flush4_offset = cp_flush3_offset + `THREADS; + parameter cp_flush5_offset = cp_flush4_offset + `THREADS; + parameter xu_lq_spr_xucr0_cls_offset = cp_flush5_offset + `THREADS; + parameter lq_iu_credit_free_offset = xu_lq_spr_xucr0_cls_offset + 1; + parameter compress_val_offset = lq_iu_credit_free_offset + `THREADS; + parameter rv1_binv_val_offset = compress_val_offset + 1; + parameter ex0_binv_val_offset = rv1_binv_val_offset + 1; + parameter ex1_binv_val_offset = ex0_binv_val_offset + 1; + parameter ex2_binv_val_offset = ex1_binv_val_offset + 1; + parameter ex3_binv_val_offset = ex2_binv_val_offset + 1; + parameter ex4_binv_val_offset = ex3_binv_val_offset + 1; + parameter ex5_binv_val_offset = ex4_binv_val_offset + 1; + parameter rv1_binv_addr_offset = ex5_binv_val_offset + 1; + parameter ex0_binv_addr_offset = rv1_binv_addr_offset + (`DC_SIZE - `CL_SIZE - 3); + parameter ex1_binv_addr_offset = ex0_binv_addr_offset + (`DC_SIZE - `CL_SIZE - 3); + parameter ex2_binv_addr_offset = ex1_binv_addr_offset + (`DC_SIZE - `CL_SIZE - 3); + parameter ex3_binv_addr_offset = ex2_binv_addr_offset + (`DC_SIZE - `CL_SIZE - 3); + parameter ex4_binv_addr_offset = ex3_binv_addr_offset + (`DC_SIZE - `CL_SIZE - 3); + parameter ex5_binv_addr_offset = ex4_binv_addr_offset + (`DC_SIZE - `CL_SIZE - 3); + parameter entry_rv1_blk_offset = ex5_binv_addr_offset + (`DC_SIZE - `CL_SIZE - 3); + parameter entry_ex0_blk_offset = entry_rv1_blk_offset + 1; + parameter entry_ex1_blk_offset = entry_ex0_blk_offset + 1; + parameter entry_ex2_blk_offset = entry_ex1_blk_offset + 1; + parameter entry_ex3_blk_offset = entry_ex2_blk_offset + 1; + parameter entry_ex4_blk_offset = entry_ex3_blk_offset + 1; + parameter entry_ex5_blk_offset = entry_ex4_blk_offset + 1; + parameter entry_ex6_blk_offset = entry_ex5_blk_offset + 1; + parameter ldq_odq_pfetch_vld_ex6_offset = entry_ex6_blk_offset + 1; + parameter odq_ldq_ex7_pfetch_blk_offset = ldq_odq_pfetch_vld_ex6_offset + 1; + parameter scan_right = odq_ldq_ex7_pfetch_blk_offset + 1 - 1; + + wire tiup; + wire tidn; + wire [0:scan_right] siv; + wire [0:scan_right] sov; + +// +// Bugsray Include +// +//!! Bugspray Include: lq_odq +// +// + + assign tiup = 1'b1; + assign tidn = 1'b0; + + // This is used to convert the wide vector port inputs into an internal 2 dimesional array format + generate + begin : ports + genvar tid; + for (tid = 0; tid <= `THREADS - 1; tid = tid + 1) + begin : convert + assign iu_lq_cp_next_itag_int[tid] = iu_lq_cp_next_itag[`ITAG_SIZE_ENC*tid:(`ITAG_SIZE_ENC*(tid+1))-1]; + assign iu_lq_i0_completed_itag_int[tid] = iu_lq_i0_completed_itag[`ITAG_SIZE_ENC*tid:(`ITAG_SIZE_ENC*(tid+1))-1]; + assign iu_lq_i1_completed_itag_int[tid] = iu_lq_i1_completed_itag[`ITAG_SIZE_ENC*tid:(`ITAG_SIZE_ENC*(tid+1))-1]; + end + end + endgenerate + + assign compressed_store_collision = 1'b0; + assign lsq_perv_odq_events = {4+`THREADS{1'b0}}; + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // BACK-INVALIDATE IN PROGRESS + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + + // Back-Invalidate in the LQ pipeline + assign rv1_binv_val_d = l2_back_inv_val; + assign ex0_binv_val_d = rv1_binv_val_q; + assign ex1_binv_val_d = ex0_binv_val_q; + assign ex2_binv_val_d = ex1_binv_val_q; + assign ex3_binv_val_d = ex2_binv_val_q; + assign ex4_binv_val_d = ex3_binv_val_q; + assign ex5_binv_val_d = ex4_binv_val_q; + + assign rv1_binv_addr_d = l2_back_inv_addr; + assign ex0_binv_addr_d = rv1_binv_addr_q; + assign ex1_binv_addr_d = ex0_binv_addr_q; + assign ex2_binv_addr_d = ex1_binv_addr_q; + assign ex3_binv_addr_d = ex2_binv_addr_q; + assign ex4_binv_addr_d = ex3_binv_addr_q; + assign ex5_binv_addr_d = ex4_binv_addr_q; + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // ORDER QUEUE + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // + // Bit 0 1 2 3 4 5 6 7 8 9 5 bits 16 bits 4 bits Total Bits = 35 bits per entry + // ------------------------------------------------------------------------------------------ + // | E | V | L | B | OC | H | EF | ld_chk | S | F | itag | collision vector | lsqEntry | + // ------------------------------------------------------------------------------------------ + // | | | | | | | | | | | | | + // | | | | | | | | | | | | Pointer to lsq array entry + // | | | | | | | | | | | Collision vector each bit indicates an address + // | | | | | | | | | | | collision with another entry + // | | | | | | | | | | Itag of the instruction corresponding to this entry + // | | | | | | | | | Command was flushed by someone else + // | | | | | | | | Sent Load/Store to L2 + // | | | | | | | Sent Load Hit w/ unresolved Stores ahead, need to check for collisions and flush if found + // | | | | | | Early flush detect + // | | | | | Entry Hit the cache + // | | | | OrderQ is responsible for completing this instruction + // | | | Entry needs to stay ordered + // | | 1 = Load, 0 = Store + // | Valid entry. This entry has been issued by RV + // Entry exists. This entry has been dispatched to RV. + // + // + // + // Queue is compressing. When an entry is selected for removal. The slot will be compressed + // along with the corresponding collision vector for all entries ordered after. + // + // + // Compress will indicate an entry 0-n which will be translated into a bit vector for each + // latch to either grab the older entries next value or it's own next value + // built into the compress is compression of the collision vector. + // + // + // Bus interfaces + // + // 1) RV interface to fill in an entry + // 2) LQ interface to fill in array pointer and collision vector + // 3) LQ interface to indicate which entry to send + // 4) + // + // + + assign cp_flush_d = iu_lq_cp_flush; + assign cp_flush2_d = cp_flush_q; + assign cp_flush3_d = cp_flush2_q; + assign cp_flush4_d = cp_flush3_q; + assign cp_flush5_d = cp_flush4_q; + + assign ex0_i0_src_xer = (ex0_i0_s3_t_q == 3'b100); + assign ex1_i0_vld_d = (ex0_i0_vld_q & {`THREADS{ex0_i0_rte_lq_q}}); + assign ex1_i0_pre_d = ex0_i0_ucode_preissue_q | ((~ex0_i0_isLoad_q) & (~ex0_i0_isStore_q)); + assign ex1_i0_isLoad_d = ex0_i0_isLoad_q; + assign ex1_i0_itag_d = ex0_i0_itag_q; + assign ex1_i0_instq_d = ex0_i0_rte_sq_q & ((ex0_i0_ucode_preissue_q & ex0_i0_src_xer) | ((~ex0_i0_ucode_preissue_q))); + + assign ex0_i1_src_xer = (ex0_i1_s3_t_q == 3'b100); + assign ex1_i1_vld_d = (ex0_i1_vld_q & {`THREADS{ex0_i1_rte_lq_q}}); + assign ex1_i1_pre_d = ex0_i1_ucode_preissue_q | ((~ex0_i1_isLoad_q) & (~ex0_i1_isStore_q)); + assign ex1_i1_isLoad_d = ex0_i1_isLoad_q; + assign ex1_i1_itag_d = ex0_i1_itag_q; + assign ex1_i1_instq_d = ex0_i1_rte_sq_q & ((ex0_i1_ucode_preissue_q & ex0_i1_src_xer) | ((~ex0_i1_ucode_preissue_q))); + + assign instr0_vld = |(ex1_i0_vld_q & (~(cp_flush_q | cp_flush2_q | cp_flush3_q | cp_flush4_q | cp_flush5_q))); + assign instr1_vld = |(ex1_i1_vld_q & (~(cp_flush_q | cp_flush2_q | cp_flush3_q | cp_flush4_q | cp_flush5_q))); + + + generate + begin : fcf + genvar tid; + for (tid = 0; tid <= `THREADS - 1; tid = tid + 1) + begin : flushCredFree + assign inc0_flush_count[tid] = ex1_i0_vld_q[tid] & (cp_flush_q[tid] | cp_flush2_q[tid] | cp_flush3_q[tid] | cp_flush4_q[tid] | cp_flush5_q[tid]); + assign inc1_flush_count[tid] = ex1_i1_vld_q[tid] & (cp_flush_q[tid] | cp_flush2_q[tid] | cp_flush3_q[tid] | cp_flush4_q[tid] | cp_flush5_q[tid]); + + assign flushed_credit_sel[tid] = {inc0_flush_count[tid], inc1_flush_count[tid], flush_credit_free[tid]}; + assign flushed_credit_count_d[tid] = (flushed_credit_sel[tid] == 3'b110) ? flushed_credit_count_q[tid] + 4'd2 : + (flushed_credit_sel[tid] == 3'b100) ? flushed_credit_count_q[tid] + 4'd1 : + (flushed_credit_sel[tid] == 3'b010) ? flushed_credit_count_q[tid] + 4'd1 : + (flushed_credit_sel[tid] == 3'b111) ? flushed_credit_count_q[tid] + 4'd1 : + (flushed_credit_sel[tid] == 3'b001) ? flushed_credit_count_q[tid] - 4'd1 : + flushed_credit_count_q[tid]; + assign flush_credit_avail[tid] = |(flushed_credit_count_q[tid]); + assign flush_credit_free[tid] = ((~compress_val)) & flush_credit_avail[tid] & flush_credit_token[tid]; + end + end + endgenerate + + // need to do a better scheme here, right now just give thread 0 higher priority. + generate + if (`THREADS == 1) + begin : t1 + assign flush_credit_token[0] = (flushed_credit_count_q[0] != 4'b0000); + end + endgenerate + generate + if (`THREADS == 2) + begin : t2 + assign flush_credit_token[0] = (flushed_credit_count_q[0] != 4'b0000); + assign flush_credit_token[1] = (flushed_credit_count_q[1] != 4'b0000) & (~flush_credit_token[0]); + end + endgenerate + + assign next_fill_sel = {compress_val, instr0_vld, instr1_vld}; + + // not removing and cmd on i0, shift right 1 + // not removing and cmd on both i0 and i1, shift right 2 + // removing command and no new cmds, shift left 1 + // removing command and cmd on both i0 and i1, shift right 1 + // other combinations are either invalid or result in no change + assign next_fill_ptr_d = ((next_fill_sel) == 3'b010) ? ({1'b0, next_fill_ptr_q[0:`LDSTQ_ENTRIES - 1]}) : // not removing and cmd on i1, shift right 1 + ((next_fill_sel) == 3'b001) ? ({1'b0, next_fill_ptr_q[0:`LDSTQ_ENTRIES - 1]}) : + ((next_fill_sel) == 3'b011) ? ({2'b00, next_fill_ptr_q[0:`LDSTQ_ENTRIES - 2]}) : + ((next_fill_sel) == 3'b100) ? ({next_fill_ptr_q[1:`LDSTQ_ENTRIES], 1'b0}) : + ((next_fill_sel) == 3'b111) ? ({1'b0, next_fill_ptr_q[0:`LDSTQ_ENTRIES - 1]}) : + next_fill_ptr_q; + assign next_instr0_ptr = next_fill_ptr_q[0:`LDSTQ_ENTRIES - 1]; + + assign next_instr1_ptr = ((instr0_vld == 1'b1)) ? ({1'b0, next_fill_ptr_q[0:`LDSTQ_ENTRIES - 2]}) : + next_fill_ptr_q[0:`LDSTQ_ENTRIES - 1]; + + // + // Set the shift in value for the last queue entry to all 0's + // + + always @(*) + begin : def + orderq_entry_inuse_next[`LDSTQ_ENTRIES] = tidn; + orderq_entry_tid_next[`LDSTQ_ENTRIES] = {`THREADS{tidn}}; + orderq_entry_val_next[`LDSTQ_ENTRIES] = tidn; + orderq_entry_ld_next[`LDSTQ_ENTRIES] = tidn; + orderq_entry_efs_next[`LDSTQ_ENTRIES] = tidn; + orderq_entry_i_next[`LDSTQ_ENTRIES] = tidn; + orderq_entry_hit_next[`LDSTQ_ENTRIES] = tidn; + orderq_entry_fwd_next[`LDSTQ_ENTRIES] = tidn; + orderq_entry_cls_op_next[`LDSTQ_ENTRIES] = tidn; + orderq_entry_dacrw_next[`LDSTQ_ENTRIES] = {DACR_WIDTH{tidn}}; + orderq_entry_eccue_next[`LDSTQ_ENTRIES] = tidn; + orderq_entry_pEvents_next[`LDSTQ_ENTRIES] = {4{tidn}}; + orderq_entry_pre_next[`LDSTQ_ENTRIES] = tidn; + orderq_entry_instq_next[`LDSTQ_ENTRIES] = tidn; + orderq_entry_flushed_next[`LDSTQ_ENTRIES] = tidn; + orderq_entry_myflush_next[`LDSTQ_ENTRIES] = tidn; + orderq_entry_ld_chk_next[`LDSTQ_ENTRIES] = tidn; + orderq_entry_stTag_next[`LDSTQ_ENTRIES] = {`STQ_ENTRIES_ENC{tidn}}; + orderq_entry_cmmt_next[`LDSTQ_ENTRIES] = tidn; + orderq_entry_bi_flag_next[`LDSTQ_ENTRIES] = tidn; + orderq_entry_bi_flush_next[`LDSTQ_ENTRIES] = tidn; + orderq_entry_val2_next[`LDSTQ_ENTRIES] = tidn; + orderq_entry_n_flush_next[`LDSTQ_ENTRIES] = tidn; + orderq_entry_np1_flush_next[`LDSTQ_ENTRIES] = tidn; + orderq_entry_update_pulse_next[`LDSTQ_ENTRIES] = tidn; + orderq_entry_itag_next[`LDSTQ_ENTRIES] = {`ITAG_SIZE_ENC{tidn}}; + end + + + + + generate + begin : gen_a + genvar entry; + for (entry = 0; entry <= `LDSTQ_ENTRIES - 1; entry = entry + 1) + begin : gen_a + + assign write_instr0[entry] = (next_instr0_ptr[entry] & instr0_vld); + assign write_instr1[entry] = (next_instr1_ptr[entry] & instr1_vld); + assign update_vld[entry] = ldq_odq_vld_q & |(ldq_odq_tid_q & orderq_entry_tid_q[entry]) & orderq_entry_inuse_q[entry] & ((~orderq_entry_val_q[entry])) & (orderq_entry_itag_q[entry] == ldq_odq_itag_q) & ((~orderq_entry_flushed_q[entry])); + + // don't worry about the extra qualifiers, this + assign update2_vld[entry] = ldq_odq_upd_val & |(ldq_odq_upd_tid & orderq_entry_tid_q[entry]) & orderq_entry_inuse_q[entry] & ((~orderq_entry_val2_q[entry])) & (orderq_entry_itag_q[entry] == ldq_odq_upd_itag); + + // CP_Flush Entry + assign cp_flush_entry[entry] = |(cp_flush_q & orderq_entry_tid_q[entry]); + + // temporary fix to flush a load hit that has a collision on a store that is being compressed this cycle + assign temp_collision_flush[entry] = 1'b0; // (compressed_store_collision and update_vld(entry) and orderq_entry_ld_q(entry) and ldq_odq_hit_q); + + // Store has been committed to L1/L2, need to invalidate instq state if still in order queue + assign orderq_entry_instq_inval[entry] = orderq_entry_inuse_q[entry] & stq_odq_stq4_stTag_inval & (orderq_entry_stTag_q[entry] == stq_odq_stq4_stTag); + + // Instruction has received its Commit Report + + //SENS always @(orderq_entry_tid_q[entry] or cp_i0_completed_itag_q or cp_i1_completed_itag_q) + always @(*) + begin: complete_itag_p + reg [0:`ITAG_SIZE_ENC-1] i0_itag; + reg [0:`ITAG_SIZE_ENC-1] i1_itag; + integer tid; + i0_itag = {`ITAG_SIZE_ENC{1'b0}}; + i1_itag = {`ITAG_SIZE_ENC{1'b0}}; + for (tid = 0; tid <= `THREADS - 1; tid = tid + 1) + begin + i0_itag = (cp_i0_completed_itag_q[tid] & {`ITAG_SIZE_ENC{orderq_entry_tid_q[entry][tid]}}) | i0_itag; + i1_itag = (cp_i1_completed_itag_q[tid] & {`ITAG_SIZE_ENC{orderq_entry_tid_q[entry][tid]}}) | i1_itag; + end + oderq_entry_i0_comp_itag[entry] = i0_itag; + oderq_entry_i1_comp_itag[entry] = i1_itag; + end + + assign orderq_entry_i0_cmmt[entry] = |(cp_i0_completed_q & orderq_entry_tid_q[entry]) & (oderq_entry_i0_comp_itag[entry] == orderq_entry_itag_q[entry]); + assign orderq_entry_i1_cmmt[entry] = |(cp_i1_completed_q & orderq_entry_tid_q[entry]) & (oderq_entry_i1_comp_itag[entry] == orderq_entry_itag_q[entry]); + assign orderq_entry_cmmt[entry] = orderq_entry_inuse_q[entry] & (orderq_entry_i0_cmmt[entry] | orderq_entry_i1_cmmt[entry]); + + //always @(flush_vector[entry] or cp_flush_entry[entry] or write_instr0[entry] or write_instr1[entry] or update_vld[entry] or ex1_i0_instq_q or ex1_i1_instq_q or ex1_i0_vld_q or ex1_i1_vld_q or ex1_i0_itag_q or ex1_i1_itag_q or ex1_i0_isLoad_q or ex1_i1_isLoad_q or ex1_i0_pre_q or ex1_i1_pre_q or ldq_odq_wimge_i_q or ldq_odq_hit_q or ldq_odq_cline_chk_q or ctl_lsq_ex6_ldh_dacrw or collision_vector_new[entry] or orderq_entry_inuse_q[entry] or orderq_entry_tid_q[entry] or orderq_entry_val_q[entry] or orderq_entry_ld_q[entry] or orderq_entry_efs_q[entry] or orderq_entry_i_q[entry] or orderq_entry_hit_q[entry] or orderq_entry_fwd_q[entry] or orderq_entry_cls_op_q[entry] or orderq_entry_dacrw_q[entry] or orderq_entry_pre_q[entry] or orderq_entry_instq_q[entry] or orderq_entry_flushed_q[entry] or orderq_entry_myflush_q[entry] or orderq_entry_ld_chk_q[entry] or orderq_entry_stTag_q[entry] or orderq_entry_bi_flag_q[entry] or orderq_entry_bi_flush_q[entry] or orderq_entry_itag_q[entry] or ldq_odq_inv_q or ldq_odq_fwd_q or stq_odq_i0_stTag or stq_odq_i1_stTag or orderq_entry_instq_inval[entry] or orderq_entry_cmmt[entry] or orderq_entry_cmmt_q[entry] or set_flush_condition[entry] or sent_early_flush[entry] or temp_collision_flush[entry] or binv_flush_detected[entry] or orderq_entry_n_flush_q[entry] or orderq_entry_np1_flush_q[entry] or update2_vld[entry] or cp_next_match[entry] or ldq_odq_upd_nFlush or ldq_odq_upd_np1Flush or ldq_odq_upd_dacrw or orderq_entry_val2_q[entry]) + always @(*) + begin: entry_update + + // default + orderq_entry_inuse_next[entry] = orderq_entry_inuse_q[entry]; + orderq_entry_tid_next[entry] = orderq_entry_tid_q[entry]; + orderq_entry_val_next[entry] = orderq_entry_val_q[entry]; + orderq_entry_ld_next[entry] = orderq_entry_ld_q[entry]; + orderq_entry_efs_next[entry] = (sent_early_flush[entry] | orderq_entry_efs_q[entry]); + orderq_entry_i_next[entry] = orderq_entry_i_q[entry]; + orderq_entry_hit_next[entry] = orderq_entry_hit_q[entry]; + orderq_entry_fwd_next[entry] = orderq_entry_fwd_q[entry]; + orderq_entry_cls_op_next[entry] = orderq_entry_cls_op_q[entry]; + orderq_entry_dacrw_next[entry] = orderq_entry_dacrw_q[entry]; + orderq_entry_eccue_next[entry] = orderq_entry_eccue_q[entry]; + orderq_entry_pEvents_next[entry] = orderq_entry_pEvents_q[entry]; + orderq_entry_pre_next[entry] = orderq_entry_pre_q[entry]; + orderq_entry_instq_next[entry] = orderq_entry_instq_q[entry]; + orderq_entry_flushed_next[entry] = orderq_entry_flushed_q[entry]; + orderq_entry_myflush_next[entry] = orderq_entry_myflush_q[entry]; + orderq_entry_ld_chk_next[entry] = ((set_flush_condition[entry] & (~ldq_odq_pfetch_vld_ex6_q)) | orderq_entry_ld_chk_q[entry]); + orderq_entry_stTag_next[entry] = orderq_entry_stTag_q[entry]; + orderq_entry_cmmt_next[entry] = orderq_entry_cmmt_q[entry]; + orderq_entry_bi_flag_next[entry] = orderq_entry_bi_flag_q[entry]; + orderq_entry_bi_flush_next[entry] = orderq_entry_bi_flush_q[entry]; + orderq_entry_val2_next[entry] = orderq_entry_val2_q[entry]; + orderq_entry_n_flush_next[entry] = orderq_entry_n_flush_q[entry]; + orderq_entry_np1_flush_next[entry] = orderq_entry_np1_flush_q[entry]; + orderq_entry_update_pulse_next[entry] = 1'b0; + orderq_entry_itag_next[entry] = orderq_entry_itag_q[entry]; + + // ======================================================================= + // order queue info updated from rv + // ======================================================================= + if (cp_flush_entry[entry] == 1'b1 & flush_vector[entry] == 1'b1 & orderq_entry_cmmt_q[entry] == 1'b0) + orderq_entry_flushed_next[entry] = orderq_entry_inuse_q[entry]; + else if (write_instr0[entry] == 1'b1 | write_instr1[entry] == 1'b1) + orderq_entry_flushed_next[entry] = 1'b0; + + // temporary fix to flush a load hit that has a collision on a store that is being compressed this cycle + if (temp_collision_flush[entry] == 1'b1) + orderq_entry_myflush_next[entry] = 1'b1; + else if (write_instr0[entry] == 1'b1 | write_instr1[entry] == 1'b1) + orderq_entry_myflush_next[entry] = 1'b0; + + // ======================================================================= + // order queue info updated from rv i0 + // ======================================================================= + if (write_instr0[entry] == 1'b1) + begin + orderq_entry_inuse_next[entry] = 1'b1; + orderq_entry_tid_next[entry] = ex1_i0_vld_q; + orderq_entry_val_next[entry] = 1'b0; + orderq_entry_ld_next[entry] = ex1_i0_isLoad_q; + orderq_entry_pre_next[entry] = ex1_i0_pre_q; + orderq_entry_ld_chk_next[entry] = 1'b0; + orderq_entry_stTag_next[entry] = stq_odq_i0_stTag; + orderq_entry_itag_next[entry] = ex1_i0_itag_q; + end + + if (write_instr0[entry] == 1'b1) + orderq_entry_instq_next[entry] = ex1_i0_instq_q; + else if (orderq_entry_instq_inval[entry] == 1'b1) + orderq_entry_instq_next[entry] = 1'b0; + + // ======================================================================= + // order queue info updated from rv i1 + // ======================================================================= + if (write_instr1[entry] == 1'b1) + begin + orderq_entry_inuse_next[entry] = 1'b1; + orderq_entry_tid_next[entry] = ex1_i1_vld_q; + orderq_entry_val_next[entry] = 1'b0; + orderq_entry_ld_next[entry] = ex1_i1_isLoad_q; + orderq_entry_pre_next[entry] = ex1_i1_pre_q; + orderq_entry_ld_chk_next[entry] = 1'b0; + orderq_entry_stTag_next[entry] = stq_odq_i1_stTag; + orderq_entry_itag_next[entry] = ex1_i1_itag_q; + end + + if (write_instr1[entry] == 1'b1) + orderq_entry_instq_next[entry] = ex1_i1_instq_q; + else if (orderq_entry_instq_inval[entry] == 1'b1) + orderq_entry_instq_next[entry] = 1'b0; + + // ======================================================================= + // order queue info updated from ldq + // lsq_entry + // ======================================================================= + if (update_vld[entry] == 1'b1) + begin + orderq_entry_val_next[entry] = 1'b1; + orderq_entry_update_pulse_next[entry] = 1'b1; + orderq_entry_i_next[entry] = ldq_odq_wimge_i_q; + orderq_entry_hit_next[entry] = ldq_odq_hit_q; + orderq_entry_fwd_next[entry] = ldq_odq_fwd_q; + orderq_entry_cls_op_next[entry] = ldq_odq_cline_chk_q; + + if (binv_flush_detected[entry] == 1'b1) + orderq_entry_bi_flush_next[entry] = 1'b1; + end + + // update dacrw bits from both update interfaces + if (update_vld[entry] == 1'b1) begin + orderq_entry_dacrw_next[entry] = ctl_lsq_ex6_ldh_dacrw; + orderq_entry_pEvents_next[entry] = ldq_odq_ex6_pEvents; + orderq_entry_eccue_next[entry] = 1'b0; + end + + if (update2_vld[entry] == 1'b1) begin + orderq_entry_dacrw_next[entry] = ldq_odq_upd_dacrw | orderq_entry_dacrw_q[entry]; + orderq_entry_pEvents_next[entry] = ldq_odq_upd_pEvents | orderq_entry_pEvents_q[entry]; + orderq_entry_eccue_next[entry] = ldq_odq_upd_eccue | orderq_entry_eccue_q[entry]; + end + + // + // Mark all resolved loads with a flag if they hit against a back invalidate + // if any older loads become resolved and hit against a newer + // + if (ldq_odq_inv_q == 1'b1 & collision_vector_new[entry] == 1'b1 & orderq_entry_val_q[entry] == 1'b1 & orderq_entry_ld_q[entry] == 1'b1) + orderq_entry_bi_flag_next[entry] = 1'b1; + + if ((binv_flush_detected[entry] == 1'b1) | (update2_vld[entry] == 1'b1 & ldq_odq_upd_nFlush == 1'b1)) + orderq_entry_n_flush_next[entry] = 1'b1; + + if ((update2_vld[entry] == 1'b1 & ldq_odq_upd_np1Flush == 1'b1)) + orderq_entry_np1_flush_next[entry] = 1'b1; + + // keep track if this entry is the + if (update2_vld[entry] == 1'b1) + orderq_entry_val2_next[entry] = 1'b1; + + // Keep track of committed instructions still in the Order Queue + if (orderq_entry_cmmt[entry] == 1'b1) + orderq_entry_cmmt_next[entry] = 1'b1; + else if (write_instr0[entry] == 1'b1 | write_instr1[entry] == 1'b1) + orderq_entry_cmmt_next[entry] = 1'b0; + + + // ======================================================================= + // order queue info updated from internal + // ======================================================================= + end + + end + end + endgenerate + + // ======================================================================= + // Age Detection + // ======================================================================= + // Trying to determine what the closet youngest store is from my position in the orderq, + // need to also determine what the closet oldest store is from my position in the orderq, + // with these 2 itags, we can determine the AGE of a load with respect to the store queue + + // Determine Closest Youngest Store + generate + begin : ady + genvar entry; + for (entry = 0; entry <= `LDSTQ_ENTRIES - 1; entry = entry + 1) + begin : ageDetectYoung + // Determine where request is located in orderq, anything below this pointer is older, anything above is younger + assign ex2_age_upper_ptr[entry] = |(ctl_lsq_ex2_thrd_id & orderq_entry_tid_q[entry]) & (ctl_lsq_ex2_itag == orderq_entry_itag_q[entry]); + + // Generate a Mask of younger entries + assign ex2_age_entry_younger[entry] = |(ex2_age_younger_ptr[0:entry]); + + // Generate a Mask of older entries + assign ex2_age_entry_older[entry] = |(ex2_age_older_ptr[entry:`LDSTQ_ENTRIES - 1]); + + // Need to determine which entries are the closest youngest valid stores in store queue + assign ex2_age_younger_st[entry] = ex2_age_entry_younger[entry] & orderq_entry_inuse_q[entry] & orderq_entry_instq_q[entry] & (~orderq_entry_flushed_q[entry]); + + // Need to determine which entries are the closest oldest valid stores in store queue + assign ex2_age_older_st[entry] = ex2_age_entry_older[entry] & orderq_entry_inuse_q[entry] & orderq_entry_instq_q[entry] & (~orderq_entry_flushed_q[entry]); + + // Determine the Next youngest store + if (entry == 0) + begin : priYoungEntry0 + assign ex2_nxt_youngest_ptr[entry] = ex2_age_younger_st[entry]; + end + + if (entry > 0) + begin : priYoungerEntry + assign ex2_nxt_youngest_ptr[entry] = (~(|(ex2_age_younger_st[0:entry - 1]))) & ex2_age_younger_st[entry]; + end + + // Generate a 1-hot signal + genvar b; + for (b = 0; b <= `STQ_ENTRIES - 1; b = b + 1) + begin : stTag1Hot + wire [0:`STQ_ENTRIES_ENC-1] bitVect = b; + assign orderq_entry_stTag_1hot[entry][b] = (bitVect == orderq_entry_stTag_q[entry]); + end + end + end + endgenerate + + // Determine Closest Oldest Store + generate + begin : ado + genvar entry; + for (entry = 0; entry <= `LDSTQ_ENTRIES - 1; entry = entry + 1) + begin : ageDetectOld + // Determine the Next Oldest store + if (entry == `LDSTQ_ENTRIES - 1) + begin : priOldEntryLast + assign ex2_nxt_oldest_ptr[entry] = ex2_age_older_st[entry]; + end + + if (entry < `LDSTQ_ENTRIES - 1) + begin : priOldEntry + assign ex2_nxt_oldest_ptr[entry] = (~(|(ex2_age_older_st[entry + 1:`LDSTQ_ENTRIES - 1]))) & ex2_age_older_st[entry]; + end + end + end + endgenerate + + // Closest Youngest instruction is my entry shifted to the right by 1 + assign ex2_age_younger_ptr = {1'b0, ex2_age_upper_ptr[0:`LDSTQ_ENTRIES - 2]}; + + // Closest Oldest instruction is my entry shifted to the left by 1 + assign ex2_age_older_ptr = {ex2_age_upper_ptr[1:`LDSTQ_ENTRIES - 1], 1'b0}; + + // Mux out ITAG and THREAD_ID for youngest and oldest entries + + //SENS always @(ex2_nxt_youngest_ptr or ex2_nxt_oldest_ptr or orderq_entry_stTag_1hot) + always @(*) + begin: ageMux + reg [0:`STQ_ENTRIES-1] yStTag; + reg [0:`STQ_ENTRIES-1] oStTag; + integer entry; + yStTag = {`STQ_ENTRIES{1'b0}}; + oStTag = {`STQ_ENTRIES{1'b0}}; + for (entry = 0; entry <= `LDSTQ_ENTRIES - 1; entry = entry + 1) + begin + yStTag = (orderq_entry_stTag_1hot[entry] & {`STQ_ENTRIES{ex2_nxt_youngest_ptr[entry]}}) | yStTag; + oStTag = (orderq_entry_stTag_1hot[entry] & {`STQ_ENTRIES{ex2_nxt_oldest_ptr[entry]}}) | oStTag; + end + ex2_nxt_youngest_stTag = yStTag; + ex2_nxt_oldest_stTag = oStTag; + end + + assign odq_stq_ex2_nxt_oldest_val = |(ex2_nxt_oldest_ptr); + assign odq_stq_ex2_nxt_oldest_stTag = ex2_nxt_oldest_stTag; + assign odq_stq_ex2_nxt_youngest_val = |(ex2_nxt_youngest_ptr); + assign odq_stq_ex2_nxt_youngest_stTag = ex2_nxt_youngest_stTag; + + // ======================================================================= + // Flush Scenario Detection + // ======================================================================= + + // + // Determine if we have a load colliding with an incomming store that is older than it, these need to be flushed + // + generate + begin : flush_a + genvar entry; + for (entry = 0; entry <= `LDSTQ_ENTRIES - 1; entry = entry + 1) + begin : flush_a + assign store_flush_detected[entry] = store_collisions_ahead[entry] & orderq_entry_val_q[entry] & orderq_entry_ld_q[entry]; + assign binv_flush_detected[entry] = load_collisions_ahead[entry] & orderq_entry_bi_flag_q[entry] & orderq_entry_ld_q[entry]; + assign ci_flush_detected[entry] = load_collisions_ahead[entry] & orderq_entry_val_q[entry] & orderq_entry_ld_q[entry] & orderq_entry_i_q[entry]; + assign forw_flush_detected[entry] = forw_collisions_ahead[entry] & orderq_entry_val_q[entry] & orderq_entry_ld_q[entry] & (~orderq_entry_hit_q[entry]); + assign set_flush_condition[entry] = store_flush_detected[entry] | forw_flush_detected[entry] | ci_flush_detected[entry]; + end + end + endgenerate + + // TODO: + // + // Determine if we have an older load miss that hits a younger load hit that is already in the queue (reordered). + // These need to be flushed + // + + // TODO: + // + // Need to change the back invalidate flush to be all entries that hit except for the oldest one in the queue. + // + + + //SENS always @(orderq_entry_inuse_q) + always @(*) + begin: cmp + integer i; + + for (i = 0; i <= `LDSTQ_ENTRIES - 1; i = i + 1) + + flush_vector_pre[i] = orderq_entry_inuse_q[i]; + + end + + // + // Generate the compression string from the entry + // + // Need to compress when all commands are resolved ahead of + assign compress_val = |(remove_entry_vec); + assign compress_entry = remove_entry; + + // return credit whenever we remove an entry or we have prevented a command from entering the queue due to cp_flush + assign lq_iu_credit_free_d = (remove_tid & {`THREADS{compress_val}}) | flush_credit_free; + assign lq_iu_credit_free = lq_iu_credit_free_q; + + generate + begin : compVect + genvar entry; + for (entry = 0; entry <= `LDSTQ_ENTRIES - 1; entry = entry + 1) + begin : compVect + if (entry == 0) + begin : en0 + assign remove_entry_base[entry] = remove_entry_vec[entry]; + assign compress_vector[entry] = remove_entry_base[entry]; + end + if (entry > 0) + begin : en + assign remove_entry_base[entry] = remove_entry_vec[entry] & (~(|(remove_entry_vec[0:entry - 1]))); + assign compress_vector[entry] = |(remove_entry_base[0:entry]); + end + end + end + endgenerate + + // + // if we are compressing this cycle, shift the flush vector so it is correct + // + //flush_vector <= flush_vector_pre(1 to `LDSTQ_ENTRIES-1) & '0' when (compress_val = '1') else + assign flush_vector = flush_vector_pre; + + generate + begin : cmp_loop + genvar entry; + for (entry = 0; entry <= `LDSTQ_ENTRIES - 1; entry = entry + 1) + begin : cmp_loop + + // ############################################## + // ############################################## + // Order Queue Compression + // ############################################## + // ############################################## + + + //always @(compress_vector[entry] or compress_val or orderq_entry_inuse_next[entry] or orderq_entry_tid_next[entry] or orderq_entry_val_next[entry] or orderq_entry_ld_next[entry] or orderq_entry_efs_next[entry] or orderq_entry_i_next[entry] or orderq_entry_hit_next[entry] or orderq_entry_fwd_next[entry] or orderq_entry_cls_op_next[entry] or orderq_entry_dacrw_next[entry] or orderq_entry_pre_next[entry] or orderq_entry_instq_next[entry] or orderq_entry_flushed_next[entry] or orderq_entry_myflush_next[entry] or orderq_entry_ld_chk_next[entry] or orderq_entry_stTag_next[entry] or orderq_entry_cmmt_next[entry] or orderq_entry_bi_flag_next[entry] or orderq_entry_bi_flush_next[entry] or orderq_entry_n_flush_next[entry] or orderq_entry_np1_flush_next[entry] or orderq_entry_update_pulse_next[entry] or orderq_entry_itag_next[entry] or orderq_entry_val2_next[entry] or orderq_entry_inuse_next[entry + 1] or orderq_entry_tid_next[entry + 1] or orderq_entry_val_next[entry + 1] or orderq_entry_ld_next[entry + 1] or orderq_entry_efs_next[entry + 1] or orderq_entry_i_next[entry + 1] or orderq_entry_hit_next[entry + 1] or orderq_entry_fwd_next[entry + 1] or orderq_entry_cls_op_next[entry + 1] or orderq_entry_dacrw_next[entry + 1] or orderq_entry_pre_next[entry + 1] or orderq_entry_instq_next[entry + 1] or orderq_entry_flushed_next[entry + 1] or orderq_entry_myflush_next[entry + 1] or orderq_entry_ld_chk_next[entry + 1] or orderq_entry_stTag_next[entry + 1] or orderq_entry_cmmt_next[entry + 1] or orderq_entry_bi_flag_next[entry + 1] or orderq_entry_bi_flush_next[entry + 1] or orderq_entry_n_flush_next[entry + 1] or orderq_entry_np1_flush_next[entry + 1] or orderq_entry_update_pulse_next[entry + 1] or orderq_entry_itag_next[entry + 1] or orderq_entry_val2_next[entry + 1]) + always @(*) + begin: cmp + + orderq_entry_inuse_d[entry] = orderq_entry_inuse_next[entry]; + orderq_entry_tid_d[entry] = orderq_entry_tid_next[entry]; + orderq_entry_val_d[entry] = orderq_entry_val_next[entry]; + orderq_entry_ld_d[entry] = orderq_entry_ld_next[entry]; + orderq_entry_efs_d[entry] = orderq_entry_efs_next[entry]; + orderq_entry_i_d[entry] = orderq_entry_i_next[entry]; + orderq_entry_hit_d[entry] = orderq_entry_hit_next[entry]; + orderq_entry_fwd_d[entry] = orderq_entry_fwd_next[entry]; + orderq_entry_cls_op_d[entry] = orderq_entry_cls_op_next[entry]; + orderq_entry_dacrw_d[entry] = orderq_entry_dacrw_next[entry]; + orderq_entry_eccue_d[entry] = orderq_entry_eccue_next[entry]; + orderq_entry_pEvents_d[entry] = orderq_entry_pEvents_next[entry]; + orderq_entry_pre_d[entry] = orderq_entry_pre_next[entry]; + orderq_entry_instq_d[entry] = orderq_entry_instq_next[entry]; + orderq_entry_flushed_d[entry] = orderq_entry_flushed_next[entry]; + orderq_entry_myflush_d[entry] = orderq_entry_myflush_next[entry]; + orderq_entry_ld_chk_d[entry] = orderq_entry_ld_chk_next[entry]; + orderq_entry_stTag_d[entry] = orderq_entry_stTag_next[entry]; + orderq_entry_cmmt_d[entry] = orderq_entry_cmmt_next[entry]; + orderq_entry_bi_flag_d[entry] = orderq_entry_bi_flag_next[entry]; + orderq_entry_bi_flush_d[entry] = orderq_entry_bi_flush_next[entry]; + orderq_entry_val2_d[entry] = orderq_entry_val2_next[entry]; + orderq_entry_n_flush_d[entry] = orderq_entry_n_flush_next[entry]; + orderq_entry_np1_flush_d[entry] = orderq_entry_np1_flush_next[entry]; + orderq_entry_update_pulse_d[entry] = orderq_entry_update_pulse_next[entry]; + orderq_entry_itag_d[entry] = orderq_entry_itag_next[entry]; + + if (compress_vector[entry] == 1'b1 & compress_val == 1'b1) + begin + orderq_entry_inuse_d[entry] = orderq_entry_inuse_next[entry + 1]; + orderq_entry_tid_d[entry] = orderq_entry_tid_next[entry + 1]; + orderq_entry_val_d[entry] = orderq_entry_val_next[entry + 1]; + orderq_entry_ld_d[entry] = orderq_entry_ld_next[entry + 1]; + orderq_entry_efs_d[entry] = orderq_entry_efs_next[entry + 1]; + orderq_entry_i_d[entry] = orderq_entry_i_next[entry + 1]; + orderq_entry_hit_d[entry] = orderq_entry_hit_next[entry + 1]; + orderq_entry_fwd_d[entry] = orderq_entry_fwd_next[entry + 1]; + orderq_entry_cls_op_d[entry] = orderq_entry_cls_op_next[entry + 1]; + orderq_entry_dacrw_d[entry] = orderq_entry_dacrw_next[entry + 1]; + orderq_entry_eccue_d[entry] = orderq_entry_eccue_next[entry + 1]; + orderq_entry_pEvents_d[entry] = orderq_entry_pEvents_next[entry + 1]; + orderq_entry_pre_d[entry] = orderq_entry_pre_next[entry + 1]; + orderq_entry_instq_d[entry] = orderq_entry_instq_next[entry + 1]; + orderq_entry_flushed_d[entry] = orderq_entry_flushed_next[entry + 1]; + orderq_entry_myflush_d[entry] = orderq_entry_myflush_next[entry + 1]; + orderq_entry_ld_chk_d[entry] = orderq_entry_ld_chk_next[entry + 1]; + orderq_entry_stTag_d[entry] = orderq_entry_stTag_next[entry + 1]; + orderq_entry_cmmt_d[entry] = orderq_entry_cmmt_next[entry + 1]; + orderq_entry_bi_flag_d[entry] = orderq_entry_bi_flag_next[entry + 1]; + orderq_entry_bi_flush_d[entry] = orderq_entry_bi_flush_next[entry + 1]; + orderq_entry_val2_d[entry] = orderq_entry_val2_next[entry + 1]; + orderq_entry_n_flush_d[entry] = orderq_entry_n_flush_next[entry + 1]; + orderq_entry_np1_flush_d[entry] = orderq_entry_np1_flush_next[entry + 1]; + orderq_entry_update_pulse_d[entry] = orderq_entry_update_pulse_next[entry + 1]; + orderq_entry_itag_d[entry] = orderq_entry_itag_next[entry + 1]; + end + end + end + end + endgenerate + + + // + // Create a vector which we can or in with each entry as an update to its current state + // this is needed to update entries that are sent out of order with the correct collision info + // The process needs to take the collision_vector and change it from the perspective of each + // entry in the queue, basically using the bit value that corresponds to its own entry as the value + // for the collision bit entry that is being updated by lq. + // + // Example: + // If we had the following queue + // Entry InUse Valid Collision vectors + // 3 1 1 L 0000 + // 2 1 1 L 0000 + // 1 1 1 L 0000 + // 0 1 0 S 0000 + // + // If incomming collison vector for entry 0 looks like this 0111, we would need to create the following or masks + // + // Entry InUse Valid Collision or masks + // 3 1 1 1110 + // 2 1 1 1101 + // 1 1 1 1011 + // 0 1 0 ---- + + // After applying the masks the final collision vectors should look like the following + // + // Entry InUse Valid Collision or masks + // 3 1 1 1110 + // 2 1 1 1101 + // 1 1 1 1011 + // 0 1 0 0111 + // + + // + // Temp fix...need to look at this...If we ever need + // to remove from the middle this won't work. We can + // just shift the collison vector left. + // + assign compress_val_d = compress_val; + + + // + // New Collision detection logic + // + assign collision_vector_new = (compress_val_q == 1'b0) ? collision_vector_q : + {collision_vector_q[1:`LDSTQ_ENTRIES - 1], 1'b0}; + generate + begin : gen_ops + genvar entry; + for (entry = 0; entry <= `LDSTQ_ENTRIES - 1; entry = entry + 1) + begin : gen_ops + assign queue_entry_is_store[entry] = ((orderq_entry_ld_q[entry] == 1'b0) & orderq_entry_pre_q[entry] == 1'b0); + assign queue_entry_is_load[entry] = (orderq_entry_ld_q[entry] == 1'b1); + end + end + endgenerate + + //collision_check_mask(0) <= '0'; + generate + begin : col_det_g + genvar entry; + for (entry = 0; entry <= `LDSTQ_ENTRIES - 1; entry = entry + 1) + begin : col_det_g + assign oo_collision_detected[entry] = collision_vector_new[entry] & collision_check_mask[entry]; + end + end + endgenerate + + always @(*) + begin : def2 + collision_check_mask[0] = tidn; + store_collisions_ahead[0] = tidn; + load_collisions_ahead[0] = tidn; + forw_collisions_ahead[0] = tidn; + end + + generate + begin : col_det_f + genvar entry; + for (entry = 1; entry <= `LDSTQ_ENTRIES - 1; entry = entry + 1) + begin : col_det_f + + //SENS always @(update_vld[0:entry - 1] or oo_collision_detected[entry] or queue_entry_is_load[0:entry - 1] or queue_entry_is_store[0:entry - 1] or ldq_odq_vld_q or ldq_odq_fwd_q) + always @(*) + begin: col_chk + collision_check_mask[entry] = ((|(update_vld[0:entry - 1])) | ldq_odq_pfetch_vld_ex6_q); + store_collisions_ahead[entry] = oo_collision_detected[entry] & |(update_vld[0:entry - 1] & queue_entry_is_store[0:entry - 1]); + load_collisions_ahead[entry] = oo_collision_detected[entry] & |(update_vld[0:entry - 1] & queue_entry_is_load[0:entry - 1]); + forw_collisions_ahead[entry] = oo_collision_detected[entry] & ldq_odq_vld_q & ldq_odq_fwd_q; + end + end + end + endgenerate + + + assign ldq_odq_pfetch_vld_ex6_d = ldq_odq_pfetch_vld; + + assign odq_ldq_ex7_pfetch_blk_d = ((|(set_flush_condition[0:`LDSTQ_ENTRIES-1])) & ldq_odq_pfetch_vld_ex6_q); + assign odq_ldq_ex7_pfetch_blk = odq_ldq_ex7_pfetch_blk_q; + + assign sent_early_flush = {`LDSTQ_ENTRIES{1'b0}}; + + // ======================================================================= + // + // Ordering rules + // The following are the rules that need to be followed when deciding + // if a load/store op is allowed to be sent. + // + // ======================================================================= + + // TODO + + // What are the rules + // A) ON LOAD MISS + // 1) it can only be sent if there are no unresolved stores in front of it, and there are no store collisions ahead of it + // 2) + // B) ON LOAD HIT + // 1) it can only be sent if there are no unresolved stores or loads in front of it and there are no collisions. + // 2) if there are outstanding unresolved stores, the load must be marked to be checked when all stores are resolved + // if there ends up being a collision, a flush needs to be issued for the load. + // 3) + // C) ON STORE + // 1) stores can be sent as long as all ops ahead are resolved and there are no collisions + // 2) + + // + // NOTE: The odq_ldq_send_cmd signal is generatated from the following logic. The way flushes work currently + // I don't have an indicator that an entry has been completed. If we have an old itag that matches a new + // itag that gets flushed, the old itag's flushed indicator will come on to ldq. This could be fixed by + // getting completion results from ldq and storing them and gating cp_flush for the entry if it is considered + // completed by the ldq. + // Instead of adding this logic we decided to allow the flush to come on for the old itag and we do not gate off + // cmd_send for the entry. The command send will get gated off for the myflush and early_flush indicators + // so ldq can qualify next itag to complete. + // + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // Address Compare Push down queue + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // + // Bits 0 1 60 bits 16 bits 5 bits + // ------------------------------------------------------------------------------------------ + // | E | V | Address | Mask | itag | + // ------------------------------------------------------------------------------------------ + // | | | | | + // | | | | | + // | | | | | + // | | | | Itag of the instruction corresponding to this entry + // | | | Byte Mask + // | | Address(0:59) + // | Valid entry. This entry has been issued by RV + // Entry exists. This entry has been dispatched to RV. + // + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + + // + // Set the shift in value for the last queue entry to all 0's + // + always @(*) + begin : def3 + addrq_entry_inuse_next[`LDSTQ_ENTRIES] = tidn; + addrq_entry_val_next[`LDSTQ_ENTRIES] = tidn; + addrq_entry_tid_next[`LDSTQ_ENTRIES] = {`THREADS{tidn}}; + addrq_entry_itag_next[`LDSTQ_ENTRIES] = {`ITAG_SIZE_ENC{tidn}}; + addrq_entry_address_next[`LDSTQ_ENTRIES] = {`REAL_IFAR_WIDTH-4{tidn}}; + addrq_entry_bytemask_next[`LDSTQ_ENTRIES] = {16{tidn}}; + end + + generate + begin : gen_b + genvar entry; + for (entry = 0; entry <= `LDSTQ_ENTRIES - 1; entry = entry + 1) + begin : gen_b + + assign update_addrq_vld[entry] = ldq_odq_vld & |(ldq_odq_tid & addrq_entry_tid_q[entry]) & addrq_entry_inuse_q[entry] & (~addrq_entry_val_q[entry]) & (addrq_entry_itag_q[entry] == ldq_odq_itag) & (~orderq_entry_flushed_q[entry]); + + //SENS always @(write_instr0[entry] or write_instr1[entry] or update_addrq_vld[entry] or ex1_i0_itag_q or ex1_i1_itag_q or ex1_i1_vld_q or ex0_i1_vld_q or ldq_odq_addr or ldq_odq_bytemask or addrq_entry_itag_q[entry] or addrq_entry_inuse_q[entry] or addrq_entry_val_q[entry] or addrq_entry_tid_q[entry] or orderq_entry_itag_q[entry] or addrq_entry_address_q[entry] or addrq_entry_bytemask_q[entry]) + always @(*) + begin: entry_update + + // default + addrq_entry_inuse_next[entry] = addrq_entry_inuse_q[entry]; + addrq_entry_val_next[entry] = addrq_entry_val_q[entry]; + addrq_entry_tid_next[entry] = addrq_entry_tid_q[entry]; + addrq_entry_itag_next[entry] = addrq_entry_itag_q[entry]; + addrq_entry_address_next[entry] = addrq_entry_address_q[entry]; + addrq_entry_bytemask_next[entry] = addrq_entry_bytemask_q[entry]; + + // ======================================================================= + // order queue info updated from rv i0 + // ======================================================================= + if (write_instr0[entry] == 1'b1) + begin + addrq_entry_inuse_next[entry] = 1'b1; + addrq_entry_val_next[entry] = 1'b0; + addrq_entry_tid_next[entry] = ex1_i0_vld_q; + addrq_entry_itag_next[entry] = ex1_i0_itag_q; + end + + // ======================================================================= + // order queue info updated from rv i1 + // ======================================================================= + if (write_instr1[entry] == 1'b1) + begin + addrq_entry_inuse_next[entry] = 1'b1; + addrq_entry_val_next[entry] = 1'b0; + addrq_entry_tid_next[entry] = ex1_i1_vld_q; + addrq_entry_itag_next[entry] = ex1_i1_itag_q; + end + + // ======================================================================= + // order queue info updated from ldq + // lsq_entry + // ======================================================================= + if (update_addrq_vld[entry] == 1'b1) + begin + addrq_entry_val_next[entry] = 1'b1; + addrq_entry_address_next[entry] = ldq_odq_addr; + addrq_entry_bytemask_next[entry] = ldq_odq_bytemask; + end + + + // ======================================================================= + // addr queue info updated from internal + // ======================================================================= + + end + end + end + endgenerate + + generate + begin : cmp2_loop + genvar entry; + for (entry = 0; entry <= `LDSTQ_ENTRIES - 1; entry = entry + 1) + begin : cmp2_loop + + // ############################################## + // ############################################## + // Addr Queue Compression + // ############################################## + // ############################################## + + + //always @(compress_vector[entry] or compress_val or addrq_entry_inuse_next[entry] or addrq_entry_val_next[entry] or addrq_entry_tid_next[entry] or addrq_entry_itag_next[entry] or addrq_entry_address_next[entry] or addrq_entry_bytemask_next[entry] or addrq_entry_inuse_next[entry + 1] or addrq_entry_val_next[entry + 1] or addrq_entry_tid_next[entry + 1] or addrq_entry_itag_next[entry + 1] or addrq_entry_address_next[entry + 1] or addrq_entry_bytemask_next[entry + 1]) + always @(*) + begin: cmp + + addrq_entry_inuse_d[entry] = addrq_entry_inuse_next[entry]; + addrq_entry_val_d[entry] = addrq_entry_val_next[entry]; + addrq_entry_tid_d[entry] = addrq_entry_tid_next[entry]; + addrq_entry_itag_d[entry] = addrq_entry_itag_next[entry]; + addrq_entry_address_d[entry] = addrq_entry_address_next[entry]; + addrq_entry_bytemask_d[entry] = addrq_entry_bytemask_next[entry]; + + if (compress_vector[entry] == 1'b1 & compress_val == 1'b1) + begin + addrq_entry_inuse_d[entry] = addrq_entry_inuse_next[entry + 1]; + addrq_entry_val_d[entry] = addrq_entry_val_next[entry + 1]; + addrq_entry_tid_d[entry] = addrq_entry_tid_next[entry + 1]; + addrq_entry_itag_d[entry] = addrq_entry_itag_next[entry + 1]; + addrq_entry_address_d[entry] = addrq_entry_address_next[entry + 1]; + addrq_entry_bytemask_d[entry] = addrq_entry_bytemask_next[entry + 1]; // if we are compressing use the compressed collision vector + end + + end + + // + // + // Collision Detection + // + // Coll = A(0:57) = B(0:57) and + // ((cl64 = '0' and cls_op = '1') or ((cl64 = '1' or cls_op = '0') and A(58) = B(58))) and + // (( cls_op = '1') or (( cls_op = '0') and A(59) = B(59))) and + // (( cls_op = '1') or (( cls_op = '0') and ByteCompare) + // + // ByteCompare = or_reduce(BM_A and BM_B) + // + + assign cacheline_size_check[entry] = orderq_entry_cls_op_q[entry] | ldq_odq_cline_chk; + + // [ Always compare on address(0 to 57) ] + assign collision_vector_pre[entry] = ((addrq_entry_val_q[entry] == 1'b1) & + ((addrq_entry_address_q[entry][64 - `REAL_IFAR_WIDTH:57] == ldq_odq_addr[64 - `REAL_IFAR_WIDTH:57]) & + // [ Force match if CL=128 and we are not doing a byte compare or op is cl size], or [ CL=64 or we are doing a byte compare and bit 58 matches ] + ((cl64 == 1'b0 & cacheline_size_check[entry] == 1'b1) | ((cl64 == 1'b1 | cacheline_size_check[entry] == 1'b0) & (addrq_entry_address_q[entry][58] == ldq_odq_addr[58]))) & + // [ Force match if we are not doing a byte compare or op is cl size], or [ we are doing a byte compare and bit 59 matches ] + ((cacheline_size_check[entry] == 1'b1) | ((cacheline_size_check[entry] == 1'b0) & (addrq_entry_address_q[entry][59] == ldq_odq_addr[59]))) & + // [ Force match if we are not doing a byte compare or op is cl size], or [ we are doing a byte compare and bytemasks match ] + ((cacheline_size_check[entry] == 1'b1) | ((cacheline_size_check[entry] == 1'b0) & |(addrq_entry_bytemask_q[entry] & ldq_odq_bytemask))))); + + // for pre-issued ucode instrutions we need to make sure they do + // not collide with any instruction + assign collision_vector[entry] = (collision_vector_pre[entry] & ((~orderq_entry_pre_q[entry]))); + end + end + endgenerate + + assign collision_vector_d = collision_vector; + + assign cl64 = xu_lq_spr_xucr0_cls_q; + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // + // Machine Kill Scenarios + // + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // + // 1. Back-invalidate hits a loadmiss/loadhit in the orderQ + // Load is marked with B-INV status, needs to check older unresolved addresses + // If older unresolved addresses hit, need to machine kill newer load that has the B-INV status set, else no machine kill + // + // 2. Newer Loadmiss-Hit-Older Unresolved Store + // Loadmiss is sent speculatively + // If reload comes back, without store resolved, update L1D$, cant complete until store is resolved + // Once store is resolved, if overlap with store bytes, then loadmiss machine kill + // If reload not back before store resolves, update the L1D$ + // if overlap with store bytes, then loadmiss machine kill when reload gets back and updates L1D$ + // + // 3. Newer Loadhit-Hit-Older Unresolved Store + // Loadhit waits for stores address resolution + // If address resolution of store results in byte overlap, then machine kill loadhit + // + // 4. Load hit Store with Mismatching EA and Matching RA coming down the pipeline to ORDQ + // MACHINE_KILL older instruction + // + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // + // Generate all resolved ahead indication for ldq + // + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + + // resolved indicator (Indicates itag is ok to complete) + + //all_resolved_ahead( + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // + // Generate Flush indication to ldq + // + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + + // + // Conditions where we flush + // + // 1. Load hit hit store + // + // 2. Back invalidate comes in and marks all sent loads it hits. If any + // load becomes resolved and hits an older marked load it must be flushed. + + assign odq_ldq_resolved = remove_entry_vec[0] & oldest_rem_is_nonflush_ld; + assign odq_ldq_report_itag = oldest_rem_itag; + assign odq_ldq_n_flush = oldest_rem_n_flush_value; + assign odq_ldq_np1_flush = oldest_rem_np1_flush_value; + assign odq_ldq_report_needed = oldest_rem_report_needed | oldest_rem_hit; + assign odq_ldq_report_dacrw = oldest_rem_dacrw; + assign odq_ldq_report_eccue = oldest_rem_eccue; + assign odq_ldq_report_tid = oldest_rem_tid; + assign odq_ldq_report_pEvents = oldest_rem_pEvents; + assign odq_stq_resolved = remove_entry_vec[0] & oldest_rem_instq; + assign odq_stq_stTag = oldest_rem_stTag; + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // + // Generate oldest unresolved itag for ldq + // + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + + generate + begin : urld_gen + genvar entry; + for (entry = 0; entry <= `LDSTQ_ENTRIES - 1; entry = entry + 1) + begin : urld_gen + assign unresolved_load[entry] = orderq_entry_inuse_q[entry] & ((~orderq_entry_val_q[entry])) & orderq_entry_ld_q[entry]; + end + end + endgenerate + + + //SENS always @(unresolved_load[0:`LDSTQ_ENTRIES - 1] or orderq_entry_itag_q) + always @(*) + begin: old_itag + integer i; + oldest_unrsv_ld_tid = {`THREADS{1'b0}}; + oldest_unrsv_ld_itag = {`ITAG_SIZE_ENC{1'b0}}; + for (i = `LDSTQ_ENTRIES - 1; i >= 0; i = i - 1) + if (unresolved_load[i] == 1'b1) + begin + oldest_unrsv_ld_tid = orderq_entry_tid_q[i]; + oldest_unrsv_ld_itag = orderq_entry_itag_q[i]; + end + end + + assign odq_ldq_oldest_ld_tid = oldest_unrsv_ld_tid; + assign odq_ldq_oldest_ld_itag = oldest_unrsv_ld_itag; + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // + // Generate oldest resolved or flushed itag for ldq + // + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + + // Back-Invalidate in the pipe check against the oldest entry in the order queue + assign oldest_entry_p0_cclass = {addrq_entry_address_q[0][64 - (`DC_SIZE - 3):56], (addrq_entry_address_q[0][57] | xu_lq_spr_xucr0_cls_q)}; + assign oldest_entry_p1_cclass = {addrq_entry_address_q[1][64 - (`DC_SIZE - 3):56], (addrq_entry_address_q[1][57] | xu_lq_spr_xucr0_cls_q)}; + assign oldest_entry_p0_m_rv0 = orderq_entry_inuse_q[0] & orderq_entry_val_q[0] & orderq_entry_ld_q[0] & l2_back_inv_val & (l2_back_inv_addr == oldest_entry_p0_cclass); + assign oldest_entry_p1_m_rv0 = orderq_entry_inuse_q[1] & orderq_entry_val_q[1] & orderq_entry_ld_q[1] & l2_back_inv_val & (l2_back_inv_addr == oldest_entry_p1_cclass); + assign oldest_entry_p1_m_rv1 = orderq_entry_inuse_q[1] & orderq_entry_val_q[1] & orderq_entry_ld_q[1] & rv1_binv_val_q & (rv1_binv_addr_q == oldest_entry_p1_cclass); + assign oldest_entry_p1_m_ex0 = orderq_entry_inuse_q[1] & orderq_entry_val_q[1] & orderq_entry_ld_q[1] & ex0_binv_val_q & (ex0_binv_addr_q == oldest_entry_p1_cclass); + assign oldest_entry_p1_m_ex1 = orderq_entry_inuse_q[1] & orderq_entry_val_q[1] & orderq_entry_ld_q[1] & ex1_binv_val_q & (ex1_binv_addr_q == oldest_entry_p1_cclass); + assign oldest_entry_p1_m_ex2 = orderq_entry_inuse_q[1] & orderq_entry_val_q[1] & orderq_entry_ld_q[1] & ex2_binv_val_q & (ex2_binv_addr_q == oldest_entry_p1_cclass); + assign oldest_entry_p1_m_ex3 = orderq_entry_inuse_q[1] & orderq_entry_val_q[1] & orderq_entry_ld_q[1] & ex3_binv_val_q & (ex3_binv_addr_q == oldest_entry_p1_cclass); + assign oldest_entry_p1_m_ex4 = orderq_entry_inuse_q[1] & orderq_entry_val_q[1] & orderq_entry_ld_q[1] & ex4_binv_val_q & (ex4_binv_addr_q == oldest_entry_p1_cclass); + assign oldest_entry_p1_m_ex5 = orderq_entry_inuse_q[1] & orderq_entry_val_q[1] & orderq_entry_ld_q[1] & ex5_binv_val_q & (ex5_binv_addr_q == oldest_entry_p1_cclass); + assign entry_rv1_blk_d = oldest_entry_p0_m_rv0 | oldest_entry_p1_m_rv0; + assign entry_ex0_blk_d = entry_rv1_blk_q | oldest_entry_p1_m_rv1; + assign entry_ex1_blk_d = entry_ex0_blk_q | oldest_entry_p1_m_ex0; + assign entry_ex2_blk_d = entry_ex1_blk_q | oldest_entry_p1_m_ex1; + assign entry_ex3_blk_d = entry_ex2_blk_q | oldest_entry_p1_m_ex2; + assign entry_ex4_blk_d = entry_ex3_blk_q | oldest_entry_p1_m_ex3; + assign entry_ex5_blk_d = entry_ex4_blk_q | oldest_entry_p1_m_ex4; + assign entry_ex6_blk_d = entry_ex5_blk_q | oldest_entry_p1_m_ex5; + assign oldest_entry_blk = (orderq_entry_ld_q[0] & l2_back_inv_val) | entry_rv1_blk_q | entry_ex0_blk_q | entry_ex1_blk_q | entry_ex2_blk_q | entry_ex3_blk_q | entry_ex4_blk_q | entry_ex5_blk_q | entry_ex6_blk_q; + + // Want to gate the compression of the oldest entry if there is a back-invalidate in the pipeline + // targetting the same congruence class as the oldest load entry + assign remove_entry_vec[0] = orderq_entry_inuse_q[0] & ((orderq_entry_val_q[0] & (~oldest_entry_blk)) | orderq_entry_flushed_q[0]); + + // + // This logic allows for removal of flushed entries from the middle of the queue. There are issues with this as some of the shifting being + // done is assuming that entries will only be allowed to remove from the oldest location. We could fix this by: + // 1. not allowing removal from middle. + // 2. put in the extra logic in the collision detection logic to shift based on actual entry being compressed instead of assuming it + // is entry 0 and just doing a full shift of all entries. + // 3. prevent removal of entries > 0 concurrent with the update of the entry from the ldq. + // + // For now I am choosing option 3 at it will be the best timing and still gets most of the benefit from removing the flushed entries + // from the middle. I will check ldq_odq_vld and only allow a flushed entry removal from the middle if this value is 0. + // + generate + begin : rld_gen + genvar entry; + for (entry = 1; entry <= `LDSTQ_ENTRIES - 1; entry = entry + 1) + begin : rld_gen + assign remove_entry_vec[entry] = (orderq_entry_inuse_q[entry] & orderq_entry_flushed_q[entry] & ((~ldq_odq_vld))); + end + end + endgenerate + + + //SENS always @(remove_entry_vec or orderq_entry_tid_q) + always @(*) + begin: rm_entry + integer i; + remove_entry = {`LDSTQ_ENTRIES_ENC{1'b0}}; + remove_tid = {`THREADS{1'b0}}; + for (i = `LDSTQ_ENTRIES - 1; i >= 0; i = i - 1) + if (remove_entry_vec[i] == 1'b1) + begin + remove_entry = i; + remove_tid = orderq_entry_tid_q[i]; + end + end + + + assign oldest_rem_itag = orderq_entry_itag_q[0]; + assign oldest_rem_n_flush_value = (orderq_entry_ld_chk_q[0] | orderq_entry_myflush_q[0] | orderq_entry_efs_q[0] | orderq_entry_bi_flush_q[0] | orderq_entry_n_flush_q[0]); + assign oldest_rem_np1_flush_value = orderq_entry_np1_flush_q[0]; + assign oldest_rem_report_needed = orderq_entry_val2_q[0]; + assign oldest_rem_hit = orderq_entry_hit_q[0]; + assign oldest_rem_is_nonflush_ld = (orderq_entry_ld_q[0] & ((~orderq_entry_flushed_q[0]))); + assign oldest_rem_dacrw = orderq_entry_dacrw_q[0]; + assign oldest_rem_eccue = orderq_entry_eccue_q[0]; + assign oldest_rem_pEvents = orderq_entry_pEvents_q[0]; + assign oldest_rem_tid = orderq_entry_tid_q[0]; + assign oldest_rem_instq = orderq_entry_instq_q[0] & (~orderq_entry_flushed_q[0]); + + generate + genvar b; + for (b = 0; b <= `STQ_ENTRIES - 1; b = b + 1) + begin : stTag1Hot + wire [0:`STQ_ENTRIES_ENC-1] bitVect = b; + assign oldest_rem_stTag[b] = (bitVect == orderq_entry_stTag_q[0]); + end + endgenerate + + // + assign lsq_ctl_oldest_tid = orderq_entry_tid_q[0]; + assign lsq_ctl_oldest_itag = orderq_entry_itag_q[0]; + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // REGISTERS + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + + generate + /*begin : oqe*/ + genvar entry; + for (entry = 0; entry <= `LDSTQ_ENTRIES - 1; entry = entry + 1) + begin : oqe + + // + // Order Queue Entry Latches + // + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) orderq_entry_inuse_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[orderq_entry_inuse_offset + entry]), + .scout(sov[orderq_entry_inuse_offset + entry]), + .din(orderq_entry_inuse_d[entry]), + .dout(orderq_entry_inuse_q[entry]) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) orderq_entry_tid_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[orderq_entry_tid_offset + (`THREADS * entry):orderq_entry_tid_offset + (`THREADS * (entry + 1)) - 1]), + .scout(sov[orderq_entry_tid_offset + (`THREADS * entry):orderq_entry_tid_offset + (`THREADS * (entry + 1)) - 1]), + .din(orderq_entry_tid_d[entry]), + .dout(orderq_entry_tid_q[entry]) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) orderq_entry_val_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[orderq_entry_val_offset + entry]), + .scout(sov[orderq_entry_val_offset + entry]), + .din(orderq_entry_val_d[entry]), + .dout(orderq_entry_val_q[entry]) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) orderq_entry_ld_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[orderq_entry_ld_offset + entry]), + .scout(sov[orderq_entry_ld_offset + entry]), + .din(orderq_entry_ld_d[entry]), + .dout(orderq_entry_ld_q[entry]) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) orderq_entry_i_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[orderq_entry_i_offset + entry]), + .scout(sov[orderq_entry_i_offset + entry]), + .din(orderq_entry_i_d[entry]), + .dout(orderq_entry_i_q[entry]) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) orderq_entry_hit_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[orderq_entry_hit_offset + entry]), + .scout(sov[orderq_entry_hit_offset + entry]), + .din(orderq_entry_hit_d[entry]), + .dout(orderq_entry_hit_q[entry]) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) orderq_entry_fwd_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[orderq_entry_fwd_offset + entry]), + .scout(sov[orderq_entry_fwd_offset + entry]), + .din(orderq_entry_fwd_d[entry]), + .dout(orderq_entry_fwd_q[entry]) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) orderq_entry_cls_op_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[orderq_entry_cls_op_offset + entry]), + .scout(sov[orderq_entry_cls_op_offset + entry]), + .din(orderq_entry_cls_op_d[entry]), + .dout(orderq_entry_cls_op_q[entry]) + ); + + + tri_rlmreg_p #(.WIDTH(DACR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) orderq_entry_dacrw_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[orderq_entry_dacrw_offset + (DACR_WIDTH * entry):orderq_entry_dacrw_offset + (DACR_WIDTH * (entry + 1)) - 1]), + .scout(sov[orderq_entry_dacrw_offset + (DACR_WIDTH * entry):orderq_entry_dacrw_offset + (DACR_WIDTH * (entry + 1)) - 1]), + .din(orderq_entry_dacrw_d[entry]), + .dout(orderq_entry_dacrw_q[entry]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) orderq_entry_eccue_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[orderq_entry_eccue_offset + entry]), + .scout(sov[orderq_entry_eccue_offset + entry]), + .din(orderq_entry_eccue_d[entry]), + .dout(orderq_entry_eccue_q[entry]) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) orderq_entry_pEvents_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[orderq_entry_pEvents_offset + (4 * entry):orderq_entry_pEvents_offset + (4 * (entry + 1)) - 1]), + .scout(sov[orderq_entry_pEvents_offset + (4 * entry):orderq_entry_pEvents_offset + (4 * (entry + 1)) - 1]), + .din(orderq_entry_pEvents_d[entry]), + .dout(orderq_entry_pEvents_q[entry]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) orderq_entry_pre_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[orderq_entry_pre_offset + entry]), + .scout(sov[orderq_entry_pre_offset + entry]), + .din(orderq_entry_pre_d[entry]), + .dout(orderq_entry_pre_q[entry]) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) orderq_entry_instq_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[orderq_entry_instq_offset + entry]), + .scout(sov[orderq_entry_instq_offset + entry]), + .din(orderq_entry_instq_d[entry]), + .dout(orderq_entry_instq_q[entry]) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) orderq_entry_flushed_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[orderq_entry_flushed_offset + entry]), + .scout(sov[orderq_entry_flushed_offset + entry]), + .din(orderq_entry_flushed_d[entry]), + .dout(orderq_entry_flushed_q[entry]) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) orderq_entry_myflush_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[orderq_entry_myflush_offset + entry]), + .scout(sov[orderq_entry_myflush_offset + entry]), + .din(orderq_entry_myflush_d[entry]), + .dout(orderq_entry_myflush_q[entry]) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) orderq_entry_itag_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[orderq_entry_itag_offset + (`ITAG_SIZE_ENC * entry):orderq_entry_itag_offset + (`ITAG_SIZE_ENC * (entry + 1)) - 1]), + .scout(sov[orderq_entry_itag_offset + (`ITAG_SIZE_ENC * entry):orderq_entry_itag_offset + (`ITAG_SIZE_ENC * (entry + 1)) - 1]), + .din(orderq_entry_itag_d[entry]), + .dout(orderq_entry_itag_q[entry]) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) orderq_entry_ld_chk_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[orderq_entry_ld_chk_offset + entry]), + .scout(sov[orderq_entry_ld_chk_offset + entry]), + .din(orderq_entry_ld_chk_d[entry]), + .dout(orderq_entry_ld_chk_q[entry]) + ); + + + tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES_ENC), .INIT(0), .NEEDS_SRESET(1)) orderq_entry_stTag_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[orderq_entry_stTag_offset + (`STQ_ENTRIES_ENC * entry):orderq_entry_stTag_offset + (`STQ_ENTRIES_ENC * (entry + 1)) - 1]), + .scout(sov[orderq_entry_stTag_offset + (`STQ_ENTRIES_ENC * entry):orderq_entry_stTag_offset + (`STQ_ENTRIES_ENC * (entry + 1)) - 1]), + .din(orderq_entry_stTag_d[entry]), + .dout(orderq_entry_stTag_q[entry]) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) orderq_entry_cmmt_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[orderq_entry_cmmt_offset + entry]), + .scout(sov[orderq_entry_cmmt_offset + entry]), + .din(orderq_entry_cmmt_d[entry]), + .dout(orderq_entry_cmmt_q[entry]) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) orderq_entry_bi_flag_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[orderq_entry_bi_flag_offset + entry]), + .scout(sov[orderq_entry_bi_flag_offset + entry]), + .din(orderq_entry_bi_flag_d[entry]), + .dout(orderq_entry_bi_flag_q[entry]) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) orderq_entry_bi_flush_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[orderq_entry_bi_flush_offset + entry]), + .scout(sov[orderq_entry_bi_flush_offset + entry]), + .din(orderq_entry_bi_flush_d[entry]), + .dout(orderq_entry_bi_flush_q[entry]) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) orderq_entry_val2_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[orderq_entry_val2_offset + entry]), + .scout(sov[orderq_entry_val2_offset + entry]), + .din(orderq_entry_val2_d[entry]), + .dout(orderq_entry_val2_q[entry]) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) orderq_entry_n_flush_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[orderq_entry_n_flush_offset + entry]), + .scout(sov[orderq_entry_n_flush_offset + entry]), + .din(orderq_entry_n_flush_d[entry]), + .dout(orderq_entry_n_flush_q[entry]) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) orderq_entry_np1_flush_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[orderq_entry_np1_flush_offset + entry]), + .scout(sov[orderq_entry_np1_flush_offset + entry]), + .din(orderq_entry_np1_flush_d[entry]), + .dout(orderq_entry_np1_flush_q[entry]) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) orderq_entry_update_pulse_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[orderq_entry_update_pulse_offset + entry]), + .scout(sov[orderq_entry_update_pulse_offset + entry]), + .din(orderq_entry_update_pulse_d[entry]), + .dout(orderq_entry_update_pulse_q[entry]) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) orderq_entry_efs_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[orderq_entry_efs_offset + entry]), + .scout(sov[orderq_entry_efs_offset + entry]), + .din(orderq_entry_efs_d[entry]), + .dout(orderq_entry_efs_q[entry]) + ); + + // addr queue latches + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) addrq_entry_inuse_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[addrq_entry_inuse_offset + entry]), + .scout(sov[addrq_entry_inuse_offset + entry]), + .din(addrq_entry_inuse_d[entry]), + .dout(addrq_entry_inuse_q[entry]) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) addrq_entry_val_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[addrq_entry_val_offset + entry]), + .scout(sov[addrq_entry_val_offset + entry]), + .din(addrq_entry_val_d[entry]), + .dout(addrq_entry_val_q[entry]) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) addrq_entry_tid_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[addrq_entry_tid_offset + (`THREADS * entry):addrq_entry_tid_offset + (`THREADS * (entry + 1)) - 1]), + .scout(sov[addrq_entry_tid_offset + (`THREADS * entry):addrq_entry_tid_offset + (`THREADS * (entry + 1)) - 1]), + .din(addrq_entry_tid_d[entry]), + .dout(addrq_entry_tid_q[entry]) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) addrq_entry_itag_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[addrq_entry_itag_offset + (`ITAG_SIZE_ENC * entry):addrq_entry_itag_offset + (`ITAG_SIZE_ENC * (entry + 1)) - 1]), + .scout(sov[addrq_entry_itag_offset + (`ITAG_SIZE_ENC * entry):addrq_entry_itag_offset + (`ITAG_SIZE_ENC * (entry + 1)) - 1]), + .din(addrq_entry_itag_d[entry]), + .dout(addrq_entry_itag_q[entry]) + ); + + + tri_rlmreg_p #(.WIDTH(`REAL_IFAR_WIDTH-4), .INIT(0), .NEEDS_SRESET(1)) addrq_entry_address_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[addrq_entry_address_offset + ((`REAL_IFAR_WIDTH-4) * entry):addrq_entry_address_offset + ((`REAL_IFAR_WIDTH-4) * (entry + 1)) - 1]), + .scout(sov[addrq_entry_address_offset + ((`REAL_IFAR_WIDTH-4) * entry):addrq_entry_address_offset + ((`REAL_IFAR_WIDTH-4) * (entry + 1)) - 1]), + .din(addrq_entry_address_d[entry]), + .dout(addrq_entry_address_q[entry]) + ); + + + tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) addrq_entry_bytemask_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[addrq_entry_bytemask_offset + (16 * entry):addrq_entry_bytemask_offset + (16 * (entry + 1)) - 1]), + .scout(sov[addrq_entry_bytemask_offset + (16 * entry):addrq_entry_bytemask_offset + (16 * (entry + 1)) - 1]), + .din(addrq_entry_bytemask_d[entry]), + .dout(addrq_entry_bytemask_q[entry]) + ); + end + /* end */ + endgenerate + + // + // Interface latches + // + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex0_i0_vld_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_i0_vld_offset:ex0_i0_vld_offset + `THREADS - 1]), + .scout(sov[ex0_i0_vld_offset:ex0_i0_vld_offset + `THREADS - 1]), + .din(rv_lq_rv1_i0_vld), + .dout(ex0_i0_vld_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_i0_rte_lq_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_i0_rte_lq_offset]), + .scout(sov[ex0_i0_rte_lq_offset]), + .din(rv_lq_rv1_i0_rte_lq), + .dout(ex0_i0_rte_lq_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_i0_rte_sq_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_i0_rte_sq_offset]), + .scout(sov[ex0_i0_rte_sq_offset]), + .din(rv_lq_rv1_i0_rte_sq), + .dout(ex0_i0_rte_sq_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_i0_isLoad_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_i0_isLoad_offset]), + .scout(sov[ex0_i0_isLoad_offset]), + .din(rv_lq_rv1_i0_isLoad), + .dout(ex0_i0_isLoad_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_i0_ucode_preissue_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_i0_ucode_preissue_offset]), + .scout(sov[ex0_i0_ucode_preissue_offset]), + .din(rv_lq_rv1_i0_ucode_preissue), + .dout(ex0_i0_ucode_preissue_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex0_i0_s3_t_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_i0_s3_t_offset:ex0_i0_s3_t_offset + 3 - 1]), + .scout(sov[ex0_i0_s3_t_offset:ex0_i0_s3_t_offset + 3 - 1]), + .din(rv_lq_rv1_i0_s3_t), + .dout(ex0_i0_s3_t_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_i0_isStore_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_i0_isStore_offset]), + .scout(sov[ex0_i0_isStore_offset]), + .din(rv_lq_rv1_i0_isStore), + .dout(ex0_i0_isStore_q) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex0_i0_itag_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_i0_itag_offset:ex0_i0_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[ex0_i0_itag_offset:ex0_i0_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(rv_lq_rv1_i0_itag), + .dout(ex0_i0_itag_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex1_i0_vld_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_i0_vld_offset:ex1_i0_vld_offset + `THREADS - 1]), + .scout(sov[ex1_i0_vld_offset:ex1_i0_vld_offset + `THREADS - 1]), + .din(ex1_i0_vld_d), + .dout(ex1_i0_vld_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_i0_isLoad_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_i0_isLoad_offset]), + .scout(sov[ex1_i0_isLoad_offset]), + .din(ex1_i0_isLoad_d), + .dout(ex1_i0_isLoad_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_i0_pre_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_i0_pre_offset]), + .scout(sov[ex1_i0_pre_offset]), + .din(ex1_i0_pre_d), + .dout(ex1_i0_pre_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_i0_instq_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_i0_instq_offset]), + .scout(sov[ex1_i0_instq_offset]), + .din(ex1_i0_instq_d), + .dout(ex1_i0_instq_q) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex1_i0_itag_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_i0_itag_offset:ex1_i0_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[ex1_i0_itag_offset:ex1_i0_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(ex1_i0_itag_d), + .dout(ex1_i0_itag_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex0_i1_vld_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_i1_vld_offset:ex0_i1_vld_offset + `THREADS - 1]), + .scout(sov[ex0_i1_vld_offset:ex0_i1_vld_offset + `THREADS - 1]), + .din(rv_lq_rv1_i1_vld), + .dout(ex0_i1_vld_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_i1_rte_lq_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_i1_rte_lq_offset]), + .scout(sov[ex0_i1_rte_lq_offset]), + .din(rv_lq_rv1_i1_rte_lq), + .dout(ex0_i1_rte_lq_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_i1_rte_sq_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_i1_rte_sq_offset]), + .scout(sov[ex0_i1_rte_sq_offset]), + .din(rv_lq_rv1_i1_rte_sq), + .dout(ex0_i1_rte_sq_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_i1_isLoad_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_i1_isLoad_offset]), + .scout(sov[ex0_i1_isLoad_offset]), + .din(rv_lq_rv1_i1_isLoad), + .dout(ex0_i1_isLoad_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_i1_ucode_preissue_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_i1_ucode_preissue_offset]), + .scout(sov[ex0_i1_ucode_preissue_offset]), + .din(rv_lq_rv1_i1_ucode_preissue), + .dout(ex0_i1_ucode_preissue_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex0_i1_s3_t_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_i1_s3_t_offset:ex0_i1_s3_t_offset + 3 - 1]), + .scout(sov[ex0_i1_s3_t_offset:ex0_i1_s3_t_offset + 3 - 1]), + .din(rv_lq_rv1_i1_s3_t), + .dout(ex0_i1_s3_t_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_i1_isStore_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_i1_isStore_offset]), + .scout(sov[ex0_i1_isStore_offset]), + .din(rv_lq_rv1_i1_isStore), + .dout(ex0_i1_isStore_q) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex0_i1_itag_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_i1_itag_offset:ex0_i1_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[ex0_i1_itag_offset:ex0_i1_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(rv_lq_rv1_i1_itag), + .dout(ex0_i1_itag_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex1_i1_vld_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_i1_vld_offset:ex1_i1_vld_offset + `THREADS - 1]), + .scout(sov[ex1_i1_vld_offset:ex1_i1_vld_offset + `THREADS - 1]), + .din(ex1_i1_vld_d), + .dout(ex1_i1_vld_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_i1_isLoad_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_i1_isLoad_offset]), + .scout(sov[ex1_i1_isLoad_offset]), + .din(ex1_i1_isLoad_d), + .dout(ex1_i1_isLoad_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_i1_pre_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_i1_pre_offset]), + .scout(sov[ex1_i1_pre_offset]), + .din(ex1_i1_pre_d), + .dout(ex1_i1_pre_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_i1_instq_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_i1_instq_offset]), + .scout(sov[ex1_i1_instq_offset]), + .din(ex1_i1_instq_d), + .dout(ex1_i1_instq_q) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex1_i1_itag_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_i1_itag_offset:ex1_i1_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[ex1_i1_itag_offset:ex1_i1_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(ex1_i1_itag_d), + .dout(ex1_i1_itag_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_odq_vld_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_odq_vld_offset]), + .scout(sov[ldq_odq_vld_offset]), + .din(ldq_odq_vld), + .dout(ldq_odq_vld_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ldq_odq_tid_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_odq_tid_offset:ldq_odq_tid_offset + `THREADS - 1]), + .scout(sov[ldq_odq_tid_offset:ldq_odq_tid_offset + `THREADS - 1]), + .din(ldq_odq_tid), + .dout(ldq_odq_tid_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_odq_inv_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_odq_inv_offset]), + .scout(sov[ldq_odq_inv_offset]), + .din(ldq_odq_inv), + .dout(ldq_odq_inv_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_odq_wimge_i_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_odq_wimge_i_offset]), + .scout(sov[ldq_odq_wimge_i_offset]), + .din(ldq_odq_wimge_i), + .dout(ldq_odq_wimge_i_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_odq_hit_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_odq_hit_offset]), + .scout(sov[ldq_odq_hit_offset]), + .din(ldq_odq_hit), + .dout(ldq_odq_hit_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_odq_fwd_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_odq_fwd_offset]), + .scout(sov[ldq_odq_fwd_offset]), + .din(ldq_odq_fwd), + .dout(ldq_odq_fwd_q) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ldq_odq_itag_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_odq_itag_offset:ldq_odq_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[ldq_odq_itag_offset:ldq_odq_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(ldq_odq_itag), + .dout(ldq_odq_itag_q) + ); + + generate + /*begin : gen_rega*/ + genvar tid; + for (tid = 0; tid <= `THREADS - 1; tid = tid + 1) + begin : iu_lq_cp_next_itag_tid + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) iu_lq_cp_next_itag_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[iu_lq_cp_next_itag_offset + (`ITAG_SIZE_ENC * tid):iu_lq_cp_next_itag_offset + (`ITAG_SIZE_ENC * (tid + 1)) - 1]), + .scout(sov[iu_lq_cp_next_itag_offset + (`ITAG_SIZE_ENC * tid):iu_lq_cp_next_itag_offset + (`ITAG_SIZE_ENC * (tid + 1)) - 1]), + .din(iu_lq_cp_next_itag_int[tid]), + .dout(iu_lq_cp_next_itag_q[tid]) + ); + + end + + for (tid = 0; tid <= `THREADS-1; tid = tid + 1) + begin : cp_i0_completed_itag_latch_gen + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) cp_i0_completed_itag_latch + ( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(iu_lq_i0_completed[tid]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[cp_i0_completed_itag_offset + (`ITAG_SIZE_ENC * tid):cp_i0_completed_itag_offset + (`ITAG_SIZE_ENC * (tid + 1)) - 1]), + .scout(sov[cp_i0_completed_itag_offset + (`ITAG_SIZE_ENC * tid):cp_i0_completed_itag_offset + (`ITAG_SIZE_ENC * (tid + 1)) - 1]), + .din(iu_lq_i0_completed_itag_int[tid]), + .dout(cp_i0_completed_itag_q[tid]) + ); + end + + for (tid = 0; tid <= `THREADS-1; tid = tid + 1) + begin : cp_i1_completed_itag_latch_gen + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) cp_i1_completed_itag_latch + ( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(iu_lq_i1_completed[tid]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[cp_i1_completed_itag_offset + (`ITAG_SIZE_ENC * tid):cp_i1_completed_itag_offset + (`ITAG_SIZE_ENC * (tid + 1)) - 1]), + .scout(sov[cp_i1_completed_itag_offset + (`ITAG_SIZE_ENC * tid):cp_i1_completed_itag_offset + (`ITAG_SIZE_ENC * (tid + 1)) - 1]), + .din(iu_lq_i1_completed_itag_int[tid]), + .dout(cp_i1_completed_itag_q[tid]) + ); + end + + for (tid = 0; tid <= `THREADS - 1; tid = tid + 1) + begin : flushed_credit_count + + tri_rlmreg_p #(.WIDTH(`LDSTQ_ENTRIES_ENC), .INIT(0), .NEEDS_SRESET(1)) flushed_credit_count_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[flushed_credit_count_offset + (`LDSTQ_ENTRIES_ENC * tid):flushed_credit_count_offset + (`LDSTQ_ENTRIES_ENC * (tid + 1)) - 1]), + .scout(sov[flushed_credit_count_offset + (`LDSTQ_ENTRIES_ENC * tid):flushed_credit_count_offset + (`LDSTQ_ENTRIES_ENC * (tid + 1)) - 1]), + .din(flushed_credit_count_d[tid]), + .dout(flushed_credit_count_q[tid]) + ); + + + end + /*end */ + endgenerate + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) cp_i0_completed_latch + ( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[cp_i0_completed_offset:cp_i0_completed_offset + `THREADS - 1]), + .scout(sov[cp_i0_completed_offset:cp_i0_completed_offset + `THREADS - 1]), + .din(iu_lq_i0_completed), + .dout(cp_i0_completed_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) cp_i1_completed_latch + ( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[cp_i1_completed_offset:cp_i1_completed_offset + `THREADS - 1]), + .scout(sov[cp_i1_completed_offset:cp_i1_completed_offset + `THREADS - 1]), + .din(iu_lq_i1_completed), + .dout(cp_i1_completed_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_odq_cline_chk_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_odq_cline_chk_offset]), + .scout(sov[ldq_odq_cline_chk_offset]), + .din(ldq_odq_cline_chk), + .dout(ldq_odq_cline_chk_q) + ); + + + tri_rlmreg_p #(.WIDTH(`LDSTQ_ENTRIES + 1), .INIT((2 ** `LDSTQ_ENTRIES)), .NEEDS_SRESET(1)) next_fill_ptr_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[next_fill_ptr_offset:next_fill_ptr_offset + (`LDSTQ_ENTRIES+1) - 1]), + .scout(sov[next_fill_ptr_offset:next_fill_ptr_offset + (`LDSTQ_ENTRIES+1) - 1]), + .din(next_fill_ptr_d), + .dout(next_fill_ptr_q) + ); + + + tri_rlmreg_p #(.WIDTH(`LDSTQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) collision_vector_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[collision_vector_offset:collision_vector_offset + `LDSTQ_ENTRIES - 1]), + .scout(sov[collision_vector_offset:collision_vector_offset + `LDSTQ_ENTRIES - 1]), + .din(collision_vector_d), + .dout(collision_vector_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) cp_flush_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[cp_flush_offset:cp_flush_offset + `THREADS - 1]), + .scout(sov[cp_flush_offset:cp_flush_offset + `THREADS - 1]), + .din(cp_flush_d), + .dout(cp_flush_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) cp_flush2_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[cp_flush2_offset:cp_flush2_offset + `THREADS - 1]), + .scout(sov[cp_flush2_offset:cp_flush2_offset + `THREADS - 1]), + .din(cp_flush2_d), + .dout(cp_flush2_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) cp_flush3_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[cp_flush3_offset:cp_flush3_offset + `THREADS - 1]), + .scout(sov[cp_flush3_offset:cp_flush3_offset + `THREADS - 1]), + .din(cp_flush3_d), + .dout(cp_flush3_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) cp_flush4_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[cp_flush4_offset:cp_flush4_offset + `THREADS - 1]), + .scout(sov[cp_flush4_offset:cp_flush4_offset + `THREADS - 1]), + .din(cp_flush4_d), + .dout(cp_flush4_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) cp_flush5_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[cp_flush5_offset:cp_flush5_offset + `THREADS - 1]), + .scout(sov[cp_flush5_offset:cp_flush5_offset + `THREADS - 1]), + .din(cp_flush5_d), + .dout(cp_flush5_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_lq_spr_xucr0_cls_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[xu_lq_spr_xucr0_cls_offset]), + .scout(sov[xu_lq_spr_xucr0_cls_offset]), + .din(xu_lq_spr_xucr0_cls), + .dout(xu_lq_spr_xucr0_cls_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) lq_iu_credit_free_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lq_iu_credit_free_offset:lq_iu_credit_free_offset + `THREADS - 1]), + .scout(sov[lq_iu_credit_free_offset:lq_iu_credit_free_offset + `THREADS - 1]), + .din(lq_iu_credit_free_d), + .dout(lq_iu_credit_free_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) compress_val_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[compress_val_offset]), + .scout(sov[compress_val_offset]), + .din(compress_val_d), + .dout(compress_val_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rv1_binv_val_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rv1_binv_val_offset]), + .scout(sov[rv1_binv_val_offset]), + .din(rv1_binv_val_d), + .dout(rv1_binv_val_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_binv_val_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_binv_val_offset]), + .scout(sov[ex0_binv_val_offset]), + .din(ex0_binv_val_d), + .dout(ex0_binv_val_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_binv_val_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_binv_val_offset]), + .scout(sov[ex1_binv_val_offset]), + .din(ex1_binv_val_d), + .dout(ex1_binv_val_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_binv_val_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_binv_val_offset]), + .scout(sov[ex2_binv_val_offset]), + .din(ex2_binv_val_d), + .dout(ex2_binv_val_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_binv_val_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_binv_val_offset]), + .scout(sov[ex3_binv_val_offset]), + .din(ex3_binv_val_d), + .dout(ex3_binv_val_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_binv_val_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_binv_val_offset]), + .scout(sov[ex4_binv_val_offset]), + .din(ex4_binv_val_d), + .dout(ex4_binv_val_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_binv_val_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_binv_val_offset]), + .scout(sov[ex5_binv_val_offset]), + .din(ex5_binv_val_d), + .dout(ex5_binv_val_q) + ); + + + tri_rlmreg_p #(.WIDTH((`DC_SIZE-`CL_SIZE-3)), .INIT(0), .NEEDS_SRESET(1)) rv1_binv_addr_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rv1_binv_addr_offset:rv1_binv_addr_offset + (`DC_SIZE-`CL_SIZE-3) - 1]), + .scout(sov[rv1_binv_addr_offset:rv1_binv_addr_offset + (`DC_SIZE-`CL_SIZE-3) - 1]), + .din(rv1_binv_addr_d), + .dout(rv1_binv_addr_q) + ); + + + tri_rlmreg_p #(.WIDTH((`DC_SIZE-`CL_SIZE-3)), .INIT(0), .NEEDS_SRESET(1)) ex0_binv_addr_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_binv_addr_offset:ex0_binv_addr_offset + (`DC_SIZE-`CL_SIZE-3) - 1]), + .scout(sov[ex0_binv_addr_offset:ex0_binv_addr_offset + (`DC_SIZE-`CL_SIZE-3) - 1]), + .din(ex0_binv_addr_d), + .dout(ex0_binv_addr_q) + ); + + + tri_rlmreg_p #(.WIDTH((`DC_SIZE-`CL_SIZE-3)), .INIT(0), .NEEDS_SRESET(1)) ex1_binv_addr_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_binv_addr_offset:ex1_binv_addr_offset + (`DC_SIZE-`CL_SIZE-3) - 1]), + .scout(sov[ex1_binv_addr_offset:ex1_binv_addr_offset + (`DC_SIZE-`CL_SIZE-3) - 1]), + .din(ex1_binv_addr_d), + .dout(ex1_binv_addr_q) + ); + + + tri_rlmreg_p #(.WIDTH((`DC_SIZE-`CL_SIZE-3)), .INIT(0), .NEEDS_SRESET(1)) ex2_binv_addr_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_binv_addr_offset:ex2_binv_addr_offset + (`DC_SIZE-`CL_SIZE-3) - 1]), + .scout(sov[ex2_binv_addr_offset:ex2_binv_addr_offset + (`DC_SIZE-`CL_SIZE-3) - 1]), + .din(ex2_binv_addr_d), + .dout(ex2_binv_addr_q) + ); + + + tri_rlmreg_p #(.WIDTH((`DC_SIZE-`CL_SIZE-3)), .INIT(0), .NEEDS_SRESET(1)) ex3_binv_addr_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_binv_addr_offset:ex3_binv_addr_offset + (`DC_SIZE-`CL_SIZE-3) - 1]), + .scout(sov[ex3_binv_addr_offset:ex3_binv_addr_offset + (`DC_SIZE-`CL_SIZE-3) - 1]), + .din(ex3_binv_addr_d), + .dout(ex3_binv_addr_q) + ); + + + tri_rlmreg_p #(.WIDTH((`DC_SIZE-`CL_SIZE-3)), .INIT(0), .NEEDS_SRESET(1)) ex4_binv_addr_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_binv_addr_offset:ex4_binv_addr_offset + (`DC_SIZE-`CL_SIZE-3) - 1]), + .scout(sov[ex4_binv_addr_offset:ex4_binv_addr_offset + (`DC_SIZE-`CL_SIZE-3) - 1]), + .din(ex4_binv_addr_d), + .dout(ex4_binv_addr_q) + ); + + + tri_rlmreg_p #(.WIDTH((`DC_SIZE-`CL_SIZE-3)), .INIT(0), .NEEDS_SRESET(1)) ex5_binv_addr_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_binv_addr_offset:ex5_binv_addr_offset + (`DC_SIZE-`CL_SIZE-3) - 1]), + .scout(sov[ex5_binv_addr_offset:ex5_binv_addr_offset + (`DC_SIZE-`CL_SIZE-3) - 1]), + .din(ex5_binv_addr_d), + .dout(ex5_binv_addr_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) entry_rv1_blk_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[entry_rv1_blk_offset]), + .scout(sov[entry_rv1_blk_offset]), + .din(entry_rv1_blk_d), + .dout(entry_rv1_blk_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) entry_ex0_blk_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[entry_ex0_blk_offset]), + .scout(sov[entry_ex0_blk_offset]), + .din(entry_ex0_blk_d), + .dout(entry_ex0_blk_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) entry_ex1_blk_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[entry_ex1_blk_offset]), + .scout(sov[entry_ex1_blk_offset]), + .din(entry_ex1_blk_d), + .dout(entry_ex1_blk_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) entry_ex2_blk_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[entry_ex2_blk_offset]), + .scout(sov[entry_ex2_blk_offset]), + .din(entry_ex2_blk_d), + .dout(entry_ex2_blk_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) entry_ex3_blk_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[entry_ex3_blk_offset]), + .scout(sov[entry_ex3_blk_offset]), + .din(entry_ex3_blk_d), + .dout(entry_ex3_blk_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) entry_ex4_blk_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[entry_ex4_blk_offset]), + .scout(sov[entry_ex4_blk_offset]), + .din(entry_ex4_blk_d), + .dout(entry_ex4_blk_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) entry_ex5_blk_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[entry_ex5_blk_offset]), + .scout(sov[entry_ex5_blk_offset]), + .din(entry_ex5_blk_d), + .dout(entry_ex5_blk_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) entry_ex6_blk_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[entry_ex6_blk_offset]), + .scout(sov[entry_ex6_blk_offset]), + .din(entry_ex6_blk_d), + .dout(entry_ex6_blk_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_odq_pfetch_vld_ex6_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ldq_odq_pfetch_vld_ex6_offset]), + .scout(sov[ldq_odq_pfetch_vld_ex6_offset]), + .din(ldq_odq_pfetch_vld_ex6_d), + .dout(ldq_odq_pfetch_vld_ex6_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) odq_ldq_ex7_pfetch_blk_reg + ( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[odq_ldq_ex7_pfetch_blk_offset]), + .scout(sov[odq_ldq_ex7_pfetch_blk_offset]), + .din(odq_ldq_ex7_pfetch_blk_d), + .dout(odq_ldq_ex7_pfetch_blk_q) + ); + + + assign siv[0:scan_right] = {sov[1:scan_right], scan_in}; + assign scan_out = sov[0]; + +endmodule diff --git a/dev/verilog/work/lq_perv.v b/dev/verilog/work/lq_perv.v new file mode 100755 index 0000000..63fcebc --- /dev/null +++ b/dev/verilog/work/lq_perv.v @@ -0,0 +1,1064 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: XU Pervasive +// +//***************************************************************************** + +`include "tri_a2o.vh" + +module lq_perv( + vdd, + gnd, + nclk, + pc_lq_trace_bus_enable, + pc_lq_debug_mux1_ctrls, + pc_lq_debug_mux2_ctrls, + pc_lq_instr_trace_mode, + pc_lq_instr_trace_tid, + debug_bus_in, + coretrace_ctrls_in, + lq_debug_bus0, + debug_bus_out, + coretrace_ctrls_out, + pc_lq_event_bus_enable, + pc_lq_event_count_mode, + ctl_perv_spr_lesr1, + ctl_perv_spr_lesr2, + ctl_perv_ex6_perf_events, + ctl_perv_stq4_perf_events, + ctl_perv_dir_perf_events, + lsq_perv_ex7_events, + lsq_perv_ldq_events, + lsq_perv_stq_events, + lsq_perv_odq_events, + xu_lq_spr_msr_pr, + xu_lq_spr_msr_gs, + event_bus_in, + event_bus_out, + pc_lq_sg_3, + pc_lq_func_sl_thold_3, + pc_lq_func_slp_sl_thold_3, + pc_lq_func_nsl_thold_3, + pc_lq_func_slp_nsl_thold_3, + pc_lq_gptr_sl_thold_3, + pc_lq_abst_sl_thold_3, + pc_lq_abst_slp_sl_thold_3, + pc_lq_time_sl_thold_3, + pc_lq_repr_sl_thold_3, + pc_lq_bolt_sl_thold_3, + pc_lq_cfg_slp_sl_thold_3, + pc_lq_regf_slp_sl_thold_3, + pc_lq_cfg_sl_thold_3, + pc_lq_ary_nsl_thold_3, + pc_lq_ary_slp_nsl_thold_3, + pc_lq_fce_3, + pc_lq_ccflush_dc, + pc_lq_bo_enable_3, + an_ac_scan_diag_dc, + bo_enable_2, + sg_2, + fce_2, + func_sl_thold_2, + func_slp_sl_thold_2, + func_nsl_thold_2, + func_slp_nsl_thold_2, + abst_sl_thold_2, + abst_slp_sl_thold_2, + time_sl_thold_2, + repr_sl_thold_2, + bolt_sl_thold_2, + cfg_slp_sl_thold_2, + regf_slp_sl_thold_2, + ary_nsl_thold_2, + ary_slp_nsl_thold_2, + cfg_sl_thold_2, + clkoff_dc_b, + d_mode_dc, + delay_lclkr_dc, + mpw1_dc_b, + mpw2_dc_b, + g6t_clkoff_dc_b, + g6t_d_mode_dc, + g6t_delay_lclkr_dc, + g6t_mpw1_dc_b, + g6t_mpw2_dc_b, + g8t_clkoff_dc_b, + g8t_d_mode_dc, + g8t_delay_lclkr_dc, + g8t_mpw1_dc_b, + g8t_mpw2_dc_b, + cam_clkoff_dc_b, + cam_d_mode_dc, + cam_delay_lclkr_dc, + cam_act_dis_dc, + cam_mpw1_dc_b, + cam_mpw2_dc_b, + gptr_scan_in, + gptr_scan_out, + func_scan_in, + func_scan_out +); + +inout vdd; +inout gnd; +(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) +input [0:`NCLK_WIDTH-1] nclk; + +// Pervasive Debug Control +input pc_lq_trace_bus_enable; +input [0:10] pc_lq_debug_mux1_ctrls; +input [0:10] pc_lq_debug_mux2_ctrls; +input pc_lq_instr_trace_mode; +input [0:`THREADS-1] pc_lq_instr_trace_tid; + +// Pass Thru Debug Trace Bus +input [0:31] debug_bus_in; +input [0:3] coretrace_ctrls_in; + +// Debug Data +input [0:31] lq_debug_bus0; + +// Outputs +output [0:31] debug_bus_out; +output [0:3] coretrace_ctrls_out; + +// Pervasive Performance Event Control +input pc_lq_event_bus_enable; +input [0:2] pc_lq_event_count_mode; +input [0:23] ctl_perv_spr_lesr1; +input [0:23] ctl_perv_spr_lesr2; +input [0:18+`THREADS-1] ctl_perv_ex6_perf_events; +input [0:6+`THREADS-1] ctl_perv_stq4_perf_events; +input [0:(`THREADS*3)+1] ctl_perv_dir_perf_events; +input [0:`THREADS-1] lsq_perv_ex7_events; +input [0:(2*`THREADS)+3] lsq_perv_ldq_events; +input [0:(3*`THREADS)+2] lsq_perv_stq_events; +input [0:4+`THREADS-1] lsq_perv_odq_events; + +input [0:`THREADS-1] xu_lq_spr_msr_pr; +input [0:`THREADS-1] xu_lq_spr_msr_gs; + +// Performance Event Outputs +input [0:(4*`THREADS)-1] event_bus_in; +output [0:(4*`THREADS)-1] event_bus_out; + +// Pervasive Clock Controls +input pc_lq_sg_3; +input pc_lq_func_sl_thold_3; +input pc_lq_func_slp_sl_thold_3; +input pc_lq_func_nsl_thold_3; +input pc_lq_func_slp_nsl_thold_3; +input pc_lq_gptr_sl_thold_3; +input pc_lq_abst_sl_thold_3; +input pc_lq_abst_slp_sl_thold_3; +input pc_lq_time_sl_thold_3; +input pc_lq_repr_sl_thold_3; +input pc_lq_bolt_sl_thold_3; +input pc_lq_cfg_slp_sl_thold_3; +input pc_lq_regf_slp_sl_thold_3; +input pc_lq_cfg_sl_thold_3; +input pc_lq_ary_nsl_thold_3; +input pc_lq_ary_slp_nsl_thold_3; +input pc_lq_fce_3; +input pc_lq_ccflush_dc; +input pc_lq_bo_enable_3; +input an_ac_scan_diag_dc; +output bo_enable_2; +output sg_2; +output fce_2; +output func_sl_thold_2; +output func_slp_sl_thold_2; +output func_nsl_thold_2; +output func_slp_nsl_thold_2; +output abst_sl_thold_2; +output abst_slp_sl_thold_2; +output time_sl_thold_2; +output repr_sl_thold_2; +output bolt_sl_thold_2; +output cfg_slp_sl_thold_2; +output regf_slp_sl_thold_2; +output ary_nsl_thold_2; +output ary_slp_nsl_thold_2; +output cfg_sl_thold_2; +output clkoff_dc_b; +output d_mode_dc; +output [0:9] delay_lclkr_dc; +output [0:9] mpw1_dc_b; +output mpw2_dc_b; +output g6t_clkoff_dc_b; +output g6t_d_mode_dc; +output [0:4] g6t_delay_lclkr_dc; +output [0:4] g6t_mpw1_dc_b; +output g6t_mpw2_dc_b; +output g8t_clkoff_dc_b; +output g8t_d_mode_dc; +output [0:4] g8t_delay_lclkr_dc; +output [0:4] g8t_mpw1_dc_b; +output g8t_mpw2_dc_b; +output cam_clkoff_dc_b; +output cam_d_mode_dc; +output [0:4] cam_delay_lclkr_dc; +output cam_act_dis_dc; +output [0:4] cam_mpw1_dc_b; +output cam_mpw2_dc_b; +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) +input gptr_scan_in; +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) +output gptr_scan_out; +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) +input func_scan_in; +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) +output func_scan_out; + +//-------------------------- +// signals +//-------------------------- +wire [0:4] gptr_siv; +wire [0:4] gptr_sov; +wire perv_sg_2; +wire gptr_sl_thold_2; +wire gptr_sl_thold_1; +wire sg_1; +wire gptr_sl_thold_0; +wire sg_0; +wire g6t_clkoff_dc_b_int; +wire g6t_d_mode_dc_int; +wire [0:4] g6t_delay_lclkr_dc_int; +wire g6t_act_dis_dc_int; +wire [0:4] g6t_mpw1_dc_b_int; +wire g6t_mpw2_dc_b_int; +wire g8t_clkoff_dc_b_int; +wire g8t_d_mode_dc_int; +wire [0:4] g8t_delay_lclkr_dc_int; +wire g8t_act_dis_dc_int; +wire [0:4] g8t_mpw1_dc_b_int; +wire g8t_mpw2_dc_b_int; +wire cam_clkoff_dc_b_int; +wire cam_d_mode_dc_int; +wire [0:4] cam_delay_lclkr_dc_int; +wire cam_act_dis_ac_int; +wire [0:4] cam_mpw1_dc_b_int; +wire cam_mpw2_dc_b_int; +wire func_slp_sl_thold_2_int; +wire func_slp_sl_thold_1; +wire func_slp_sl_thold_0; +wire func_slp_sl_thold_0_b; +wire func_slp_sl_force; +wire [0:1] clkoff_dc_b_int; +wire [0:1] d_mode_dc_int; +wire [0:1] act_dis_dc_int; +wire [0:9] delay_lclkr_dc_int; +wire [0:9] mpw1_dc_b_int; +wire [0:1] mpw2_dc_b_int; +wire pc_lq_trace_bus_enable_q; +wire [0:10] pc_lq_debug_mux1_ctrls_q; +wire [0:10] pc_lq_debug_mux2_ctrls_q; +wire pc_lq_instr_trace_mode_q; +wire [0:`THREADS-1] pc_lq_instr_trace_tid_q; +wire pc_lq_event_bus_enable_q; +wire [0:2] pc_lq_event_count_mode_q; +wire [0:31] lq_dbg_data_mux1[0:31]; +wire [0:31] lq_dbg_data_mux2[0:31]; +wire [0:31] lq_mux1_debug_data_in; +wire [0:3] lq_mux1_coretrace_in; +wire [0:31] lq_mux1_debug_data_out_d; +wire [0:31] lq_mux1_debug_data_out_q; +wire [0:3] lq_mux1_coretrace_out_d; +wire [0:3] lq_mux1_coretrace_out_q; +wire [0:31] lq_mux2_debug_data_in; +wire [0:3] lq_mux2_coretrace_in; +wire [0:31] lq_mux2_debug_data_out_d; +wire [0:31] lq_mux2_debug_data_out_q; +wire [0:3] lq_mux2_coretrace_out_d; +wire [0:3] lq_mux2_coretrace_out_q; +wire [0:`THREADS-1] spr_msr_gs_d; +wire [0:`THREADS-1] spr_msr_gs_q; +wire [0:`THREADS-1] spr_msr_pr_d; +wire [0:`THREADS-1] spr_msr_pr_q; +wire [0:47] perf_event_mux_ctrl; +wire [0:`THREADS-1] perf_event_en_d; +wire [0:`THREADS-1] perf_event_en_q; +wire [0:(4*`THREADS)-1] perf_event_data_d; +wire [0:(4*`THREADS)-1] perf_event_data_q; +wire [0:17] ex6_perf_events[0:`THREADS-1]; +wire [0:5] stq4_perf_events[0:`THREADS-1]; +wire [0:3] odq_perf_events[0:`THREADS-1]; +wire [0:4] dir_perf_events[0:`THREADS-1]; +wire [0:5] stq_perf_events[0:`THREADS-1]; +wire [0:5] ldq_perf_events[0:`THREADS-1]; +wire [1:63] lq_perf_events[0:`THREADS-1]; +wire [1:63] lq_events_en[0:`THREADS-1]; + +//-------------------------- +// register constants +//-------------------------- +parameter pc_lq_trace_bus_enable_offset = 0; +parameter pc_lq_debug_mux1_ctrls_offset = pc_lq_trace_bus_enable_offset + 1; +parameter pc_lq_debug_mux2_ctrls_offset = pc_lq_debug_mux1_ctrls_offset + 11; +parameter pc_lq_instr_trace_mode_offset = pc_lq_debug_mux2_ctrls_offset + 11; +parameter pc_lq_instr_trace_tid_offset = pc_lq_instr_trace_mode_offset + 1; +parameter lq_mux1_debug_data_out_offset = pc_lq_instr_trace_tid_offset + `THREADS; +parameter lq_mux1_coretrace_out_offset = lq_mux1_debug_data_out_offset + 32; +parameter lq_mux2_debug_data_out_offset = lq_mux1_coretrace_out_offset + 4; +parameter lq_mux2_coretrace_out_offset = lq_mux2_debug_data_out_offset + 32; +parameter spr_msr_gs_offset = lq_mux2_coretrace_out_offset + 4; +parameter spr_msr_pr_offset = spr_msr_gs_offset + `THREADS; +parameter pc_lq_event_bus_enable_offset = spr_msr_pr_offset + `THREADS; +parameter perf_event_en_offset = pc_lq_event_bus_enable_offset + 1; +parameter perf_event_data_offset = perf_event_en_offset + `THREADS; +parameter pc_lq_event_count_mode_offset = perf_event_data_offset + (4*`THREADS); +parameter scan_right = pc_lq_event_count_mode_offset + 3 - 1; + +wire tiup; +wire tidn; +wire [0:scan_right] siv; +wire [0:scan_right] sov; +(* analysis_not_referenced="true" *) +wire unused; + +assign tiup = 1; +assign tidn = 0; +assign unused = (|perf_event_mux_ctrl) | clkoff_dc_b_int[1] | d_mode_dc_int[1] | act_dis_dc_int[1] | mpw2_dc_b_int[1] | + g6t_act_dis_dc_int | g8t_act_dis_dc_int | cam_act_dis_ac_int; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Debug Bus Control Logic +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +generate + begin : dbgData + genvar bus; + for (bus=0; bus<32; bus=bus+1) begin : dbgData + assign lq_dbg_data_mux1[bus] = lq_debug_bus0; + assign lq_dbg_data_mux2[bus] = lq_debug_bus0; + end + end +endgenerate + +assign lq_mux1_debug_data_in = debug_bus_in; +assign lq_mux1_coretrace_in = coretrace_ctrls_in; + +tri_debug_mux32 dbgMux1( + .select_bits(pc_lq_debug_mux1_ctrls_q), + .trace_data_in(lq_mux1_debug_data_in), + .coretrace_ctrls_in(lq_mux1_coretrace_in), + .dbg_group0(lq_dbg_data_mux1[0]), + .dbg_group1(lq_dbg_data_mux1[1]), + .dbg_group2(lq_dbg_data_mux1[2]), + .dbg_group3(lq_dbg_data_mux1[3]), + .dbg_group4(lq_dbg_data_mux1[4]), + .dbg_group5(lq_dbg_data_mux1[5]), + .dbg_group6(lq_dbg_data_mux1[6]), + .dbg_group7(lq_dbg_data_mux1[7]), + .dbg_group8(lq_dbg_data_mux1[8]), + .dbg_group9(lq_dbg_data_mux1[9]), + .dbg_group10(lq_dbg_data_mux1[10]), + .dbg_group11(lq_dbg_data_mux1[11]), + .dbg_group12(lq_dbg_data_mux1[12]), + .dbg_group13(lq_dbg_data_mux1[13]), + .dbg_group14(lq_dbg_data_mux1[14]), + .dbg_group15(lq_dbg_data_mux1[15]), + .dbg_group16(lq_dbg_data_mux1[16]), + .dbg_group17(lq_dbg_data_mux1[17]), + .dbg_group18(lq_dbg_data_mux1[18]), + .dbg_group19(lq_dbg_data_mux1[19]), + .dbg_group20(lq_dbg_data_mux1[20]), + .dbg_group21(lq_dbg_data_mux1[21]), + .dbg_group22(lq_dbg_data_mux1[22]), + .dbg_group23(lq_dbg_data_mux1[23]), + .dbg_group24(lq_dbg_data_mux1[24]), + .dbg_group25(lq_dbg_data_mux1[25]), + .dbg_group26(lq_dbg_data_mux1[26]), + .dbg_group27(lq_dbg_data_mux1[27]), + .dbg_group28(lq_dbg_data_mux1[28]), + .dbg_group29(lq_dbg_data_mux1[29]), + .dbg_group30(lq_dbg_data_mux1[30]), + .dbg_group31(lq_dbg_data_mux1[31]), + .trace_data_out(lq_mux1_debug_data_out_d), + .coretrace_ctrls_out(lq_mux1_coretrace_out_d) +); + +assign lq_mux2_debug_data_in = lq_mux1_debug_data_out_q; +assign lq_mux2_coretrace_in = lq_mux1_coretrace_out_q; + +tri_debug_mux32 dbgmux2( + .select_bits(pc_lq_debug_mux2_ctrls_q), + .trace_data_in(lq_mux2_debug_data_in), + .coretrace_ctrls_in(lq_mux2_coretrace_in), + .dbg_group0(lq_dbg_data_mux2[0]), + .dbg_group1(lq_dbg_data_mux2[1]), + .dbg_group2(lq_dbg_data_mux2[2]), + .dbg_group3(lq_dbg_data_mux2[3]), + .dbg_group4(lq_dbg_data_mux2[4]), + .dbg_group5(lq_dbg_data_mux2[5]), + .dbg_group6(lq_dbg_data_mux2[6]), + .dbg_group7(lq_dbg_data_mux2[7]), + .dbg_group8(lq_dbg_data_mux2[8]), + .dbg_group9(lq_dbg_data_mux2[9]), + .dbg_group10(lq_dbg_data_mux2[10]), + .dbg_group11(lq_dbg_data_mux2[11]), + .dbg_group12(lq_dbg_data_mux2[12]), + .dbg_group13(lq_dbg_data_mux2[13]), + .dbg_group14(lq_dbg_data_mux2[14]), + .dbg_group15(lq_dbg_data_mux2[15]), + .dbg_group16(lq_dbg_data_mux2[16]), + .dbg_group17(lq_dbg_data_mux2[17]), + .dbg_group18(lq_dbg_data_mux2[18]), + .dbg_group19(lq_dbg_data_mux2[19]), + .dbg_group20(lq_dbg_data_mux2[20]), + .dbg_group21(lq_dbg_data_mux2[21]), + .dbg_group22(lq_dbg_data_mux2[22]), + .dbg_group23(lq_dbg_data_mux2[23]), + .dbg_group24(lq_dbg_data_mux2[24]), + .dbg_group25(lq_dbg_data_mux2[25]), + .dbg_group26(lq_dbg_data_mux2[26]), + .dbg_group27(lq_dbg_data_mux2[27]), + .dbg_group28(lq_dbg_data_mux2[28]), + .dbg_group29(lq_dbg_data_mux2[29]), + .dbg_group30(lq_dbg_data_mux2[30]), + .dbg_group31(lq_dbg_data_mux2[31]), + .trace_data_out(lq_mux2_debug_data_out_d), + .coretrace_ctrls_out(lq_mux2_coretrace_out_d) +); + +assign debug_bus_out = lq_mux2_debug_data_out_q; +assign coretrace_ctrls_out = lq_mux2_coretrace_out_q; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Performance Events Control Logic +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +// MSR[GS] Guest State +// 1 => Processor is in Guest State +// 0 => Processor is in Hypervisor State +assign spr_msr_gs_d = xu_lq_spr_msr_gs; + +// MSR[PR] Problem State +// 1 => Processor is in User Mode +// 0 => Processor is in Supervisor Mode +assign spr_msr_pr_d = xu_lq_spr_msr_pr; + +// Processor State Control +assign perf_event_en_d = ( spr_msr_pr_q & {`THREADS{pc_lq_event_count_mode_q[0]}}) | // User + (~spr_msr_pr_q & spr_msr_gs_q & {`THREADS{pc_lq_event_count_mode_q[1]}}) | // Guest Supervisor + (~spr_msr_pr_q & ~spr_msr_gs_q & {`THREADS{pc_lq_event_count_mode_q[2]}}); // Hypervisor + +// Muxing +assign perf_event_mux_ctrl = {ctl_perv_spr_lesr1, ctl_perv_spr_lesr2}; + +generate begin : TidPerf + genvar tid; + for (tid=0;tid<`THREADS;tid=tid+1) begin : TidPerf + // Generate Events Per Thread + assign ex6_perf_events[tid] = ctl_perv_ex6_perf_events[0:17] & {18{ctl_perv_ex6_perf_events[18+tid]}}; + assign stq4_perf_events[tid] = ctl_perv_stq4_perf_events[0:5] & {6{ctl_perv_stq4_perf_events[6+tid]}}; + assign odq_perf_events[tid] = lsq_perv_odq_events[0:3] & {4{lsq_perv_odq_events[4+tid]}}; + assign dir_perf_events[tid] = {ctl_perv_dir_perf_events[0:1], ctl_perv_dir_perf_events[2+(0*`THREADS)+tid], + ctl_perv_dir_perf_events[2+(1*`THREADS)+tid], ctl_perv_dir_perf_events[2+(2*`THREADS)+tid]}; + assign stq_perf_events[tid] = {lsq_perv_stq_events[0:2], lsq_perv_stq_events[3+(0*`THREADS)+tid], + lsq_perv_stq_events[3+(1*`THREADS)+tid], lsq_perv_stq_events[3+(2*`THREADS)+tid]}; + assign ldq_perf_events[tid] = {lsq_perv_ldq_events[0:3], lsq_perv_ldq_events[4+(0*`THREADS)+tid], + lsq_perv_ldq_events[4+(1*`THREADS)+tid]}; + + // Tie Up all performance events + // (0) => => empty events, tied to 0 <-- Needs to always be 0 + // (1) => => empty events, tied to 0 + // (2) => => empty events, tied to 0 + // (3) => => empty events, tied to 0 + // (4) => => empty events, tied to 0 + // (5) => => empty events, tied to 0 + // (6) => perf_ex6_derat_attmpts => ctl_perv_ex6_perf_events(0) + // (7) => perf_ex6_derat_restarts => ctl_perv_ex6_perf_events(1) + assign lq_perf_events[tid][1:7] = {{5{1'b0}}, ex6_perf_events[tid][0:1]}; + + // (8) => perf_ex6_pfetch_iss => ctl_perv_ex6_perf_events(2) + // (9) => perf_ex6_pfetch_hit => ctl_perv_ex6_perf_events(3) + // (10) => perf_ex6_pfetch_emiss => ctl_perv_ex6_perf_events(4) + // (11) => perf_ex6_pfetch_ldq_full => ctl_perv_ex6_perf_events(5) + // (12) => perf_ex6_pfetch_ldq_hit => ctl_perv_ex6_perf_events(6) + // (13) => perf_ex6_pfetch_stq_restart => ctl_perv_ex6_perf_events(7) + // (14) => perf_ex6_pfetch_odq_restart => lsq_perv_ex7_events(0) + // (15) => perf_ex6_dir_restart => ctl_perv_ex6_perf_events(8) + assign lq_perf_events[tid][8:15] = {ex6_perf_events[tid][2:7], lsq_perv_ex7_events[tid], ex6_perf_events[tid][8]}; + + // (16) => perf_ex6_dec_restart => ctl_perv_ex6_perf_events(9) + // (17) => perf_ex6_wNComp_restart => ctl_perv_ex6_perf_events(10) + // (18) => perf_ex6_ldq_full => ctl_perv_ex6_perf_events(11) + // (19) => perf_ex6_ldq_hit => ctl_perv_ex6_perf_events(12) + // (20) => perf_ex6_lgq_full => ctl_perv_ex6_perf_events(13) + // (21) => perf_ex6_lgq_hit => ctl_perv_ex6_perf_events(14) + // (22) => perf_ex6_stq_sametid => ctl_perv_ex6_perf_events(15) + // (23) => perf_ex6_stq_difftid => ctl_perv_ex6_perf_events(16) + assign lq_perf_events[tid][16:23] = ex6_perf_events[tid][9:16]; + + // (24) => perf_dir_binv_val => ctl_perv_dir_perf_events(0) + // (25) => perf_dir_binv_hit => ctl_perv_dir_perf_events(1) + // (26) => perf_dir_binv_watchlost => ctl_perv_dir_perf_events(2+(0*`THREADS)) + // (27) => perf_dir_evict_watchlost => ctl_perv_dir_perf_events(2+(1*`THREADS)) + // (28) => perf_dir_interTid_watchlost => ctl_perv_dir_perf_events(2+(2*`THREADS)) + // (29) => perf_stq_stores => ctl_perv_stq4_perf_events(0) + // (30) => perf_stq_store_miss => ctl_perv_stq4_perf_events(1) + // (31) => perf_stq_stcx_exec => ctl_perv_stq4_perf_events(2) + assign lq_perf_events[tid][24:31] = {dir_perf_events[tid], stq4_perf_events[tid][0:2]}; + + // (32) => perf_stq_stcx_fail => lsq_perv_stq_events(3+(0*`THREADS)) + // (33) => perf_stq_axu_store => ctl_perv_stq4_perf_events(3) + // (34) => perf_stq_icswxr_nbusy => lsq_perv_stq_events(3+(1*`THREADS)) + // (35) => perf_stq_icswxr_busy => lsq_perv_stq_events(3+(2*`THREADS)) + // (36) => perf_stq_wclr => ctl_perv_stq4_perf_events(4) + // (37) => perf_stq_wclr_set => ctl_perv_stq4_perf_events(5) + // (38) => perf_ldq_cpl_larx => lsq_perv_ldq_events(4+(0*`THREADS)) + // (39) => perf_ldq_rel_attmpt => lsq_perv_ldq_events(0) + assign lq_perf_events[tid][32:39] = {stq_perf_events[tid][3], stq4_perf_events[tid][3], stq_perf_events[tid][4:5], stq4_perf_events[tid][4:5], + ldq_perf_events[tid][4], ldq_perf_events[tid][0]}; + + // (40) => perf_ldq_rel_cmmt => lsq_perv_ldq_events(1) + // (41) => perf_ldq_rel_need_hole => lsq_perv_ldq_events(2) + // (42) => perf_stq_cmmt_attmpt => lsq_perv_stq_events(0) + // (43) => perf_stq_cmmt_val => lsq_perv_stq_events(1) + // (44) => perf_stq_need_hole => lsq_perv_stq_events(2) + // (45) => perf_ex6_align_flush => ctl_perv_ex6_perf_events(17) + // (46) => perf_ldq_cpl_binv => lsq_perv_ldq_events(4+(1*`THREADS)) + // (47) => => lsq_perv_odq_events(0) + assign lq_perf_events[tid][40:47] = {ldq_perf_events[tid][1:2], stq_perf_events[tid][0:2], ex6_perf_events[tid][17], ldq_perf_events[tid][5], + odq_perf_events[tid][0]}; + + // (48) => => lsq_perv_odq_events(1) + // (49) => => lsq_perv_odq_events(2) + // (50) => => lsq_perv_odq_events(3) + // (51) => perf_ldq_rel_latency => lsq_perv_ldq_events(3) + // (52) => perf_com_loads => commit events, tied to 0 + // (53) => perf_com_loadmiss => commit events, tied to 0 + // (54) => perf_com_cinh_loads => commit events, tied to 0 + // (55) => perf_com_load_fwd => commit events, tied to 0 + assign lq_perf_events[tid][48:55] = {odq_perf_events[tid][1:3], ldq_perf_events[tid][3], {4{1'b0}}}; + + // (56) => perf_com_axu_load => commit events, tied to 0 + // (57) => perf_com_dcbt_sent => commit events, tied to 0 + // (58) => perf_com_dcbt_hit => commit events, tied to 0 + // (59) => perf_com_watch_set => commit events, tied to 0 + // (60) => perf_com_watch_dup => commit events, tied to 0 + // (61) => perf_com_wchkall => commit events, tied to 0 + // (62) => perf_com_wchkall_succ => commit events, tied to 0 + // (63) => ex5_ld_gath_q => commit events, tied to 0 + assign lq_perf_events[tid][56:63] = {8{1'b0}}; + + assign lq_events_en[tid] = lq_perf_events[tid] & {63{perf_event_en_q[tid]}}; + + tri_event_mux1t #(.EVENTS_IN(64)) perfMux( + .vd(vdd), + .gd(gnd), + .select_bits(perf_event_mux_ctrl[tid*24:(tid*24)+23]), + .unit_events_in(lq_events_en[tid]), + .event_bus_in(event_bus_in[tid*4:(tid*4)+3]), + .event_bus_out(perf_event_data_d[tid*4:(tid*4)+3]) + ); + end +end +endgenerate + +assign event_bus_out = perf_event_data_q; + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Pervasive Clock Control Logic +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + +tri_plat #(.WIDTH(18)) perv_3to2_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(pc_lq_ccflush_dc), + .din({pc_lq_func_sl_thold_3, + pc_lq_func_slp_sl_thold_3, + pc_lq_gptr_sl_thold_3, + pc_lq_sg_3, + pc_lq_fce_3, + pc_lq_func_nsl_thold_3, + pc_lq_func_slp_nsl_thold_3, + pc_lq_abst_sl_thold_3, + pc_lq_abst_slp_sl_thold_3, + pc_lq_time_sl_thold_3, + pc_lq_ary_nsl_thold_3, + pc_lq_ary_slp_nsl_thold_3, + pc_lq_cfg_sl_thold_3, + pc_lq_repr_sl_thold_3, + pc_lq_bolt_sl_thold_3, + pc_lq_cfg_slp_sl_thold_3, + pc_lq_regf_slp_sl_thold_3, + pc_lq_bo_enable_3}), + .q({func_sl_thold_2, + func_slp_sl_thold_2_int, + gptr_sl_thold_2, + perv_sg_2, + fce_2, + func_nsl_thold_2, + func_slp_nsl_thold_2, + abst_sl_thold_2, + abst_slp_sl_thold_2, + time_sl_thold_2, + ary_nsl_thold_2, + ary_slp_nsl_thold_2, + cfg_sl_thold_2, + repr_sl_thold_2, + bolt_sl_thold_2, + cfg_slp_sl_thold_2, + regf_slp_sl_thold_2, + bo_enable_2}) +); + +assign sg_2 = perv_sg_2; + +assign g6t_clkoff_dc_b = g6t_clkoff_dc_b_int; +assign g6t_d_mode_dc = g6t_d_mode_dc_int; +assign g6t_delay_lclkr_dc = g6t_delay_lclkr_dc_int; +assign g6t_mpw1_dc_b = g6t_mpw1_dc_b_int; +assign g6t_mpw2_dc_b = g6t_mpw2_dc_b_int; + +assign g8t_clkoff_dc_b = g8t_clkoff_dc_b_int; +assign g8t_d_mode_dc = g8t_d_mode_dc_int; +assign g8t_delay_lclkr_dc = g8t_delay_lclkr_dc_int; +assign g8t_mpw1_dc_b = g8t_mpw1_dc_b_int; +assign g8t_mpw2_dc_b = g8t_mpw2_dc_b_int; + +assign cam_clkoff_dc_b = cam_clkoff_dc_b_int; +assign cam_delay_lclkr_dc = cam_delay_lclkr_dc_int; +assign cam_act_dis_dc = 1'b0; +assign cam_d_mode_dc = cam_d_mode_dc_int; +assign cam_mpw1_dc_b = cam_mpw1_dc_b_int; +assign cam_mpw2_dc_b = cam_mpw2_dc_b_int; + +assign func_slp_sl_thold_2 = func_slp_sl_thold_2_int; +assign clkoff_dc_b = clkoff_dc_b_int[0]; +assign d_mode_dc = d_mode_dc_int[0]; +assign delay_lclkr_dc = delay_lclkr_dc_int; +assign mpw1_dc_b = mpw1_dc_b_int; +assign mpw2_dc_b = mpw2_dc_b_int[0]; + + +tri_plat #(.WIDTH(3)) perv_2to1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(pc_lq_ccflush_dc), + .din({gptr_sl_thold_2, + func_slp_sl_thold_2_int, + perv_sg_2}), + .q({gptr_sl_thold_1, + func_slp_sl_thold_1, + sg_1}) +); + +tri_plat #(.WIDTH(3)) perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(pc_lq_ccflush_dc), + .din({gptr_sl_thold_1, + func_slp_sl_thold_1, + sg_1}), + .q({gptr_sl_thold_0, + func_slp_sl_thold_0, + sg_0}) +); + +tri_lcbor perv_lcbor_func_slp_sl( + .clkoff_b(clkoff_dc_b_int[0]), + .thold(func_slp_sl_thold_0), + .sg(sg_0), + .act_dis(tidn), + .force_t(func_slp_sl_force), + .thold_b(func_slp_sl_thold_0_b) +); + +tri_lcbcntl_mac perv_lcbctrl_0( + .vdd(vdd), + .gnd(gnd), + .sg(sg_0), + .nclk(nclk), + .scan_in(gptr_siv[3]), + .scan_diag_dc(an_ac_scan_diag_dc), + .thold(gptr_sl_thold_0), + .clkoff_dc_b(clkoff_dc_b_int[0]), + .delay_lclkr_dc(delay_lclkr_dc_int[0:4]), + .act_dis_dc(act_dis_dc_int[0]), + .d_mode_dc(d_mode_dc_int[0]), + .mpw1_dc_b(mpw1_dc_b_int[0:4]), + .mpw2_dc_b(mpw2_dc_b_int[0]), + .scan_out(gptr_sov[3]) +); + +tri_lcbcntl_mac perv_lcbctrl_1( + .vdd(vdd), + .gnd(gnd), + .sg(sg_0), + .nclk(nclk), + .scan_in(gptr_siv[4]), + .scan_diag_dc(an_ac_scan_diag_dc), + .thold(gptr_sl_thold_0), + .clkoff_dc_b(clkoff_dc_b_int[1]), + .delay_lclkr_dc(delay_lclkr_dc_int[5:9]), + .act_dis_dc(act_dis_dc_int[1]), + .d_mode_dc(d_mode_dc_int[1]), + .mpw1_dc_b(mpw1_dc_b_int[5:9]), + .mpw2_dc_b(mpw2_dc_b_int[1]), + .scan_out(gptr_sov[4]) +); + +tri_lcbcntl_array_mac perv_lcbctrl_g6t_0( + .vdd(vdd), + .gnd(gnd), + .sg(sg_0), + .nclk(nclk), + .scan_in(gptr_siv[0]), + .scan_diag_dc(an_ac_scan_diag_dc), + .thold(gptr_sl_thold_0), + .clkoff_dc_b(g6t_clkoff_dc_b_int), + .delay_lclkr_dc(g6t_delay_lclkr_dc_int[0:4]), + .act_dis_dc(g6t_act_dis_dc_int), + .d_mode_dc(g6t_d_mode_dc_int), + .mpw1_dc_b(g6t_mpw1_dc_b_int[0:4]), + .mpw2_dc_b(g6t_mpw2_dc_b_int), + .scan_out(gptr_sov[0]) +); + +tri_lcbcntl_array_mac perv_lcbctrl_g8t_0( + .vdd(vdd), + .gnd(gnd), + .sg(sg_0), + .nclk(nclk), + .scan_in(gptr_siv[1]), + .scan_diag_dc(an_ac_scan_diag_dc), + .thold(gptr_sl_thold_0), + .clkoff_dc_b(g8t_clkoff_dc_b_int), + .delay_lclkr_dc(g8t_delay_lclkr_dc_int[0:4]), + .act_dis_dc(g8t_act_dis_dc_int), + .d_mode_dc(g8t_d_mode_dc_int), + .mpw1_dc_b(g8t_mpw1_dc_b_int[0:4]), + .mpw2_dc_b(g8t_mpw2_dc_b_int), + .scan_out(gptr_sov[1]) +); + +tri_lcbcntl_array_mac perv_lcbctrl_cam_0( + .vdd(vdd), + .gnd(gnd), + .sg(sg_0), + .nclk(nclk), + .scan_in(gptr_siv[2]), + .scan_diag_dc(an_ac_scan_diag_dc), + .thold(gptr_sl_thold_0), + .clkoff_dc_b(cam_clkoff_dc_b_int), + .delay_lclkr_dc(cam_delay_lclkr_dc_int[0:4]), + .act_dis_dc(cam_act_dis_ac_int), + .d_mode_dc(cam_d_mode_dc_int), + .mpw1_dc_b(cam_mpw1_dc_b_int[0:4]), + .mpw2_dc_b(cam_mpw2_dc_b_int), + .scan_out(gptr_sov[2]) +); + +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +// Registers +// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pc_lq_trace_bus_enable_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc_int[0]), + .delay_lclkr(delay_lclkr_dc_int[0]), + .mpw1_b(mpw1_dc_b_int[0]), + .mpw2_b(mpw2_dc_b_int[0]), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[pc_lq_trace_bus_enable_offset]), + .scout(sov[pc_lq_trace_bus_enable_offset]), + .din(pc_lq_trace_bus_enable), + .dout(pc_lq_trace_bus_enable_q) +); + +tri_rlmreg_p #(.WIDTH(11), .INIT(0), .NEEDS_SRESET(1)) pc_lq_debug_mux1_ctrls_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pc_lq_trace_bus_enable_q), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc_int[0]), + .delay_lclkr(delay_lclkr_dc_int[0]), + .mpw1_b(mpw1_dc_b_int[0]), + .mpw2_b(mpw2_dc_b_int[0]), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[pc_lq_debug_mux1_ctrls_offset:pc_lq_debug_mux1_ctrls_offset + 11 - 1]), + .scout(sov[pc_lq_debug_mux1_ctrls_offset:pc_lq_debug_mux1_ctrls_offset + 11 - 1]), + .din(pc_lq_debug_mux1_ctrls), + .dout(pc_lq_debug_mux1_ctrls_q) +); + +tri_rlmreg_p #(.WIDTH(11), .INIT(0), .NEEDS_SRESET(1)) pc_lq_debug_mux2_ctrls_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pc_lq_trace_bus_enable_q), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc_int[0]), + .delay_lclkr(delay_lclkr_dc_int[0]), + .mpw1_b(mpw1_dc_b_int[0]), + .mpw2_b(mpw2_dc_b_int[0]), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[pc_lq_debug_mux2_ctrls_offset:pc_lq_debug_mux2_ctrls_offset + 11 - 1]), + .scout(sov[pc_lq_debug_mux2_ctrls_offset:pc_lq_debug_mux2_ctrls_offset + 11 - 1]), + .din(pc_lq_debug_mux2_ctrls), + .dout(pc_lq_debug_mux2_ctrls_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pc_lq_instr_trace_mode_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc_int[0]), + .delay_lclkr(delay_lclkr_dc_int[0]), + .mpw1_b(mpw1_dc_b_int[0]), + .mpw2_b(mpw2_dc_b_int[0]), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[pc_lq_instr_trace_mode_offset]), + .scout(sov[pc_lq_instr_trace_mode_offset]), + .din(pc_lq_instr_trace_mode), + .dout(pc_lq_instr_trace_mode_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) pc_lq_instr_trace_tid_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pc_lq_trace_bus_enable_q), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc_int[0]), + .delay_lclkr(delay_lclkr_dc_int[0]), + .mpw1_b(mpw1_dc_b_int[0]), + .mpw2_b(mpw2_dc_b_int[0]), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[pc_lq_instr_trace_tid_offset:pc_lq_instr_trace_tid_offset + `THREADS - 1]), + .scout(sov[pc_lq_instr_trace_tid_offset:pc_lq_instr_trace_tid_offset + `THREADS - 1]), + .din(pc_lq_instr_trace_tid), + .dout(pc_lq_instr_trace_tid_q) +); + +tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) lq_mux1_debug_data_out_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pc_lq_trace_bus_enable_q), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc_int[0]), + .delay_lclkr(delay_lclkr_dc_int[0]), + .mpw1_b(mpw1_dc_b_int[0]), + .mpw2_b(mpw2_dc_b_int[0]), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lq_mux1_debug_data_out_offset:lq_mux1_debug_data_out_offset + 32 - 1]), + .scout(sov[lq_mux1_debug_data_out_offset:lq_mux1_debug_data_out_offset + 32 - 1]), + .din(lq_mux1_debug_data_out_d), + .dout(lq_mux1_debug_data_out_q) +); + +tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lq_mux1_coretrace_out_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pc_lq_trace_bus_enable_q), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc_int[0]), + .delay_lclkr(delay_lclkr_dc_int[0]), + .mpw1_b(mpw1_dc_b_int[0]), + .mpw2_b(mpw2_dc_b_int[0]), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lq_mux1_coretrace_out_offset:lq_mux1_coretrace_out_offset + 4 - 1]), + .scout(sov[lq_mux1_coretrace_out_offset:lq_mux1_coretrace_out_offset + 4 - 1]), + .din(lq_mux1_coretrace_out_d), + .dout(lq_mux1_coretrace_out_q) +); + +tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) lq_mux2_debug_data_out_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pc_lq_trace_bus_enable_q), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc_int[0]), + .delay_lclkr(delay_lclkr_dc_int[0]), + .mpw1_b(mpw1_dc_b_int[0]), + .mpw2_b(mpw2_dc_b_int[0]), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lq_mux2_debug_data_out_offset:lq_mux2_debug_data_out_offset + 32 - 1]), + .scout(sov[lq_mux2_debug_data_out_offset:lq_mux2_debug_data_out_offset + 32 - 1]), + .din(lq_mux2_debug_data_out_d), + .dout(lq_mux2_debug_data_out_q) +); + +tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lq_mux2_coretrace_out_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pc_lq_trace_bus_enable_q), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc_int[0]), + .delay_lclkr(delay_lclkr_dc_int[0]), + .mpw1_b(mpw1_dc_b_int[0]), + .mpw2_b(mpw2_dc_b_int[0]), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lq_mux2_coretrace_out_offset:lq_mux2_coretrace_out_offset + 4 - 1]), + .scout(sov[lq_mux2_coretrace_out_offset:lq_mux2_coretrace_out_offset + 4 - 1]), + .din(lq_mux2_coretrace_out_d), + .dout(lq_mux2_coretrace_out_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_msr_gs_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc_int[0]), + .delay_lclkr(delay_lclkr_dc_int[0]), + .mpw1_b(mpw1_dc_b_int[0]), + .mpw2_b(mpw2_dc_b_int[0]), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_msr_gs_offset:spr_msr_gs_offset + `THREADS - 1]), + .scout(sov[spr_msr_gs_offset:spr_msr_gs_offset + `THREADS - 1]), + .din(spr_msr_gs_d), + .dout(spr_msr_gs_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_msr_pr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc_int[0]), + .delay_lclkr(delay_lclkr_dc_int[0]), + .mpw1_b(mpw1_dc_b_int[0]), + .mpw2_b(mpw2_dc_b_int[0]), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_msr_pr_offset:spr_msr_pr_offset + `THREADS - 1]), + .scout(sov[spr_msr_pr_offset:spr_msr_pr_offset + `THREADS - 1]), + .din(spr_msr_pr_d), + .dout(spr_msr_pr_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pc_lq_event_bus_enable_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc_int[0]), + .delay_lclkr(delay_lclkr_dc_int[0]), + .mpw1_b(mpw1_dc_b_int[0]), + .mpw2_b(mpw2_dc_b_int[0]), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[pc_lq_event_bus_enable_offset]), + .scout(sov[pc_lq_event_bus_enable_offset]), + .din(pc_lq_event_bus_enable), + .dout(pc_lq_event_bus_enable_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) perf_event_en_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pc_lq_event_bus_enable_q), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc_int[0]), + .delay_lclkr(delay_lclkr_dc_int[0]), + .mpw1_b(mpw1_dc_b_int[0]), + .mpw2_b(mpw2_dc_b_int[0]), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[perf_event_en_offset:perf_event_en_offset + `THREADS - 1]), + .scout(sov[perf_event_en_offset:perf_event_en_offset + `THREADS - 1]), + .din(perf_event_en_d), + .dout(perf_event_en_q) +); + +tri_rlmreg_p #(.WIDTH((4*`THREADS)), .INIT(0), .NEEDS_SRESET(1)) perf_event_data_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pc_lq_event_bus_enable_q), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc_int[0]), + .delay_lclkr(delay_lclkr_dc_int[0]), + .mpw1_b(mpw1_dc_b_int[0]), + .mpw2_b(mpw2_dc_b_int[0]), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[perf_event_data_offset:perf_event_data_offset + (4*`THREADS) - 1]), + .scout(sov[perf_event_data_offset:perf_event_data_offset + (4*`THREADS) - 1]), + .din(perf_event_data_d), + .dout(perf_event_data_q) +); + +tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) pc_lq_event_count_mode_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pc_lq_event_bus_enable_q), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc_int[0]), + .delay_lclkr(delay_lclkr_dc_int[0]), + .mpw1_b(mpw1_dc_b_int[0]), + .mpw2_b(mpw2_dc_b_int[0]), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[pc_lq_event_count_mode_offset:pc_lq_event_count_mode_offset + 3 - 1]), + .scout(sov[pc_lq_event_count_mode_offset:pc_lq_event_count_mode_offset + 3 - 1]), + .din(pc_lq_event_count_mode), + .dout(pc_lq_event_count_mode_q) +); + +assign gptr_siv[0:4] = {gptr_sov[1:4], gptr_scan_in}; +assign gptr_scan_out = gptr_sov[0]; +assign siv[0:scan_right] = {sov[1:scan_right], func_scan_in}; +assign func_scan_out = sov[0]; + +endmodule diff --git a/dev/verilog/work/lq_pfetch.v b/dev/verilog/work/lq_pfetch.v new file mode 100755 index 0000000..07906ea --- /dev/null +++ b/dev/verilog/work/lq_pfetch.v @@ -0,0 +1,2889 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// +// Description: XU LSU Data Prefetcher +// +//***************************************************************************** + +`include "tri_a2o.vh" + +// parameter EXPAND_TYPE = 2; +// parameter GPR_WIDTH_ENC = 6; // 5 = 32bit mode, 6 = 64bit mode +// parameter CL_SIZE = 6; // 6 => 64B CLINE, 7 => 128B CLINE +// parameter THREADS = 2; // Number of Threads in the system +// parameter REAL_IFAR_WIDTH = 42; // width of the read address +// parameter ITAG_SIZE_ENC = 7; +// parameter LDSTQ_ENTRIES = 16; // Order Queue Size +// `define PF_IFAR_WIDTH 12 // number of IAR bits used by prefetch +// `define PFETCH_INITIAL_DEPTH 0 // the initial value for the SPR that determines how many lines to prefetch +// `define PFETCH_Q_SIZE_ENC 3 // number of bits to address queue size (3 => 8 entries, 4 => 16 entries) +// `define PFETCH_Q_SIZE 8 // number of entries in prefetch queue + +module lq_pfetch( + rv_lq_rv1_i0_vld, + rv_lq_rv1_i0_rte_lq, + rv_lq_rv1_i0_isLoad, + rv_lq_rv1_i0_ifar, + rv_lq_rv1_i0_itag, + rv_lq_rv1_i1_vld, + rv_lq_rv1_i1_rte_lq, + rv_lq_rv1_i1_isLoad, + rv_lq_rv1_i1_ifar, + rv_lq_rv1_i1_itag, + iu_lq_cp_flush, + ctl_pf_clear_queue, + odq_pf_report_tid, + odq_pf_report_itag, + odq_pf_resolved, + dcc_pf_ex5_eff_addr, + dcc_pf_ex5_req_val_4pf, + dcc_pf_ex5_act, + dcc_pf_ex5_loadmiss, + dcc_pf_ex5_thrd_id, + dcc_pf_ex5_itag, + spr_pf_spr_dscr_lsd, + spr_pf_spr_dscr_snse, + spr_pf_spr_dscr_sse, + spr_pf_spr_dscr_dpfd, + spr_pf_spr_pesr, + pf_dec_req_addr, + pf_dec_req_thrd, + pf_dec_req_val, + dec_pf_ack, + pf_empty, + pc_lq_inj_prefetcher_parity, + lq_pc_err_prefetcher_parity, + vdd, + gnd, + vcs, + nclk, + sg_0, + func_sl_thold_0_b, + func_sl_force, + d_mode_dc, + delay_lclkr_dc, + clkoff_dc_b, + mpw1_dc_b, + mpw2_dc_b, + scan_in, + scan_out, + abst_sl_thold_0, + ary_nsl_thold_0, + time_sl_thold_0, + repr_sl_thold_0, + g8t_clkoff_dc_b, + pc_lq_ccflush_dc, + an_ac_scan_dis_dc_b, + an_ac_scan_diag_dc, + g8t_d_mode_dc, + g8t_mpw1_dc_b, + g8t_mpw2_dc_b, + g8t_delay_lclkr_dc, + pc_xu_abist_g8t_wenb_q, + pc_xu_abist_g8t1p_renb_0_q, + pc_xu_abist_di_0_q, + pc_xu_abist_g8t_bw_1_q, + pc_xu_abist_g8t_bw_0_q, + pc_xu_abist_waddr_0_q, + pc_xu_abist_raddr_0_q, + an_ac_lbist_ary_wrt_thru_dc, + pc_xu_abist_ena_dc, + pc_xu_abist_wl64_comp_ena_q, + pc_xu_abist_raw_dc_b, + pc_xu_abist_g8t_dcomp_q, + abst_scan_in, + time_scan_in, + repr_scan_in, + abst_scan_out, + time_scan_out, + repr_scan_out, + bolt_sl_thold_0, + pc_bo_enable_2, + pc_xu_bo_reset, + pc_xu_bo_unload, + pc_xu_bo_repair, + pc_xu_bo_shdata, + pc_xu_bo_select, + xu_pc_bo_fail, + xu_pc_bo_diagout +); + + // iar and itag of the load instruction from dispatch + input [0:`THREADS-1] rv_lq_rv1_i0_vld; + input rv_lq_rv1_i0_rte_lq; + input rv_lq_rv1_i0_isLoad; + input [61-`PF_IFAR_WIDTH+1:61] rv_lq_rv1_i0_ifar; + input [0:`ITAG_SIZE_ENC-1] rv_lq_rv1_i0_itag; + input [0:`THREADS-1] rv_lq_rv1_i1_vld; + input rv_lq_rv1_i1_rte_lq; + input rv_lq_rv1_i1_isLoad; + input [61-`PF_IFAR_WIDTH+1:61] rv_lq_rv1_i1_ifar; + input [0:`ITAG_SIZE_ENC-1] rv_lq_rv1_i1_itag; + + // flush interface + input [0:`THREADS-1] iu_lq_cp_flush; + + input ctl_pf_clear_queue; + + // release itag to pfetch + input [0:`THREADS-1] odq_pf_report_tid; + input [0:`ITAG_SIZE_ENC-1] odq_pf_report_itag; + input odq_pf_resolved; + + // EA of load miss that is valid for pre-fetching + input [64-(2**`GPR_WIDTH_ENC):59] dcc_pf_ex5_eff_addr; + input dcc_pf_ex5_req_val_4pf; + input dcc_pf_ex5_act; + input dcc_pf_ex5_loadmiss; + input [0:`THREADS-1] dcc_pf_ex5_thrd_id; + input [0:`ITAG_SIZE_ENC-1] dcc_pf_ex5_itag; + + input [0:`THREADS-1] spr_pf_spr_dscr_lsd; + input [0:`THREADS-1] spr_pf_spr_dscr_snse; + input [0:`THREADS-1] spr_pf_spr_dscr_sse; + input [0:3*`THREADS-1] spr_pf_spr_dscr_dpfd; + input [0:31] spr_pf_spr_pesr; + + // EA of prefetch request + output [64-(2**`GPR_WIDTH_ENC):63-`CL_SIZE] pf_dec_req_addr; + output [0:`THREADS-1] pf_dec_req_thrd; + output pf_dec_req_val; + input dec_pf_ack; + + output [0:`THREADS-1] pf_empty; + + // parity error signals + input pc_lq_inj_prefetcher_parity; + output lq_pc_err_prefetcher_parity; + + // Pervasive + + + inout vcs; + + + inout vdd; + + + inout gnd; + + (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) + + input [0:`NCLK_WIDTH-1] nclk; + input sg_0; + input func_sl_thold_0_b; + input func_sl_force; + input d_mode_dc; + input delay_lclkr_dc; + input clkoff_dc_b; + input mpw1_dc_b; + input mpw2_dc_b; + + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + + input scan_in; + + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + + output scan_out; + + // array pervasive + input abst_sl_thold_0; + input ary_nsl_thold_0; + input time_sl_thold_0; + input repr_sl_thold_0; + input g8t_clkoff_dc_b; + input pc_lq_ccflush_dc; + input an_ac_scan_dis_dc_b; + input an_ac_scan_diag_dc; + input g8t_d_mode_dc; + input [0:4] g8t_mpw1_dc_b; + input g8t_mpw2_dc_b; + input [0:4] g8t_delay_lclkr_dc; + // ABIST + input pc_xu_abist_g8t_wenb_q; + input pc_xu_abist_g8t1p_renb_0_q; + input [0:3] pc_xu_abist_di_0_q; + input pc_xu_abist_g8t_bw_1_q; + input pc_xu_abist_g8t_bw_0_q; + input [0:4] pc_xu_abist_waddr_0_q; + input [0:4] pc_xu_abist_raddr_0_q; + input an_ac_lbist_ary_wrt_thru_dc; + input pc_xu_abist_ena_dc; + input pc_xu_abist_wl64_comp_ena_q; + input pc_xu_abist_raw_dc_b; + input [0:3] pc_xu_abist_g8t_dcomp_q; + // Scan + + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + + input [0:1] abst_scan_in; + + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + + input time_scan_in; + + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + + input repr_scan_in; + + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + + output [0:1] abst_scan_out; + + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + + output time_scan_out; + + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + + output repr_scan_out; + // BOLT-ON + input bolt_sl_thold_0; + input pc_bo_enable_2; // general bolt-on enable + input pc_xu_bo_reset; // reset + input pc_xu_bo_unload; // unload sticky bits + input pc_xu_bo_repair; // execute sticky bit decode + input pc_xu_bo_shdata; // shift data for timing write and diag loop + input [0:1] pc_xu_bo_select; // select for mask and hier writes + output [0:1] xu_pc_bo_fail; // fail/no-fix reg + + output [0:1] xu_pc_bo_diagout; + + //-------------------------- + // signals + //-------------------------- + wire [0:`THREADS-1] pfetch_dis_thrd; + reg pf1_disable; + reg ex6_pf_disable; + + wire [58:63] pf_dscr_reg[0:`THREADS-1]; + reg [58:63] pf1_dscr; + wire [0:`THREADS-1] rv_i0_vld_d; + wire [0:`THREADS-1] rv_i0_vld_q; + wire rv_i0_rte_lq_q; + wire rv_i0_isLoad_q; + wire [61-`PF_IFAR_WIDTH+1:61] rv_i0_ifar_q; + wire [0:`ITAG_SIZE_ENC-1] rv_i0_itag_q; + wire [0:`THREADS-1] rv_i1_vld_d; + wire [0:`THREADS-1] rv_i1_vld_q; + wire rv_i1_rte_lq_q; + wire rv_i1_isLoad_q; + wire [61-`PF_IFAR_WIDTH+1:61] rv_i1_ifar_q; + wire [0:`ITAG_SIZE_ENC-1] rv_i1_itag_q; + wire [0:`THREADS-1] cp_flush_q; + wire [0:`THREADS-1] cp_flush2_q; + wire [0:`THREADS-1] cp_flush3_q; + wire [0:`THREADS-1] cp_flush4_q; + + wire new_itag_i0_val; + wire new_itag_i1_val; + wire [0:`LDSTQ_ENTRIES-1] pf_iar_i0_wen; + wire [0:`LDSTQ_ENTRIES-1] pf_iar_val_for_i1; + wire [0:`LDSTQ_ENTRIES-1] pf_iar_i1_wen; + wire [61-`PF_IFAR_WIDTH+1:61] pf_iar_tbl_d[0:`LDSTQ_ENTRIES-1]; + wire [61-`PF_IFAR_WIDTH+1:61] pf_iar_tbl_q[0:`LDSTQ_ENTRIES-1]; + wire [0:`ITAG_SIZE_ENC-1] pf_itag_tbl_d[0:`LDSTQ_ENTRIES-1]; + wire [0:`ITAG_SIZE_ENC-1] pf_itag_tbl_q[0:`LDSTQ_ENTRIES-1]; + wire [0:`THREADS-1] pf_tid_tbl_d[0:`LDSTQ_ENTRIES-1]; + wire [0:`THREADS-1] pf_tid_tbl_q[0:`LDSTQ_ENTRIES-1]; + wire [0:`LDSTQ_ENTRIES-1] pf_iar_tbl_val_d; + wire [0:`LDSTQ_ENTRIES-1] pf_iar_tbl_val_q; + wire [0:`LDSTQ_ENTRIES-1] ex5_itag_match; + reg [61-`PF_IFAR_WIDTH+1:61] ex5_iar; + wire [61-`PF_IFAR_WIDTH+1:61] ex6_iar_q; + wire [61-`PF_IFAR_WIDTH+1:61] ex7_iar_q; + wire [61-`PF_IFAR_WIDTH+1:61] ex8_iar_q; + wire [0:`LDSTQ_ENTRIES-1] pf_iar_tbl_reset; + wire odq_resolved_q; + wire [0:`ITAG_SIZE_ENC-1] odq_report_itag_q; + wire [0:`THREADS-1] odq_report_tid_q; + + wire [0:21] pfq_stride_d[0:`PFETCH_Q_SIZE-1]; + wire [0:21] pfq_stride_q[0:`PFETCH_Q_SIZE-1]; + wire [64-(2**`GPR_WIDTH_ENC):59] pfq_data_ea_d[0:`PFETCH_Q_SIZE-1]; + wire [64-(2**`GPR_WIDTH_ENC):59] pfq_data_ea_q[0:`PFETCH_Q_SIZE-1]; + wire [0:`PFETCH_Q_SIZE-1] pfq_dup_flag_d; + wire [0:`PFETCH_Q_SIZE-1] pfq_dup_flag_q; + wire [0:`THREADS-1] pfq_thrd_d[0:`PFETCH_Q_SIZE-1]; + wire [0:`THREADS-1] pfq_thrd_q[0:`PFETCH_Q_SIZE-1]; + wire [61:63] pfq_dscr_d[0:`PFETCH_Q_SIZE-1]; + wire [61:63] pfq_dscr_q[0:`PFETCH_Q_SIZE-1]; + wire [0:`PFETCH_Q_SIZE-1] pfq_wen; + wire [0:`PFETCH_Q_SIZE_ENC-1] pfq_wrt_ptr_plus1; + wire [0:`PFETCH_Q_SIZE_ENC-1] pfq_wrt_ptr_d; + wire [0:`PFETCH_Q_SIZE_ENC-1] pfq_wrt_ptr_q; + wire [0:`PFETCH_Q_SIZE_ENC-1] pfq_rd_ptr_d; + wire [0:`PFETCH_Q_SIZE_ENC-1] pfq_rd_ptr_q; + wire pfq_full_d; + wire pfq_full_q; + wire pfq_wrt_val; + reg [0:21] pf3_stride_d; + wire [0:21] pf3_stride_q; + reg [64-(2**`GPR_WIDTH_ENC):59] pfq_rd_data_ea; + reg pfq_rd_dup_flag; + reg [0:`THREADS-1] pfq_rd_thrd; + reg [0:`THREADS-1] pfq_thrd_v; + reg [61:63] pfq_rd_dscr; + wire pf_rd_val; + wire pf_idle; + wire pf_gen; + wire pf_send; + wire pf_next; + wire pf_done; + reg pf_nxt_idle; + reg pf_nxt_gen; + reg pf_nxt_send; + reg pf_nxt_next; + reg pf_nxt_done; + wire [0:4] pf_nxt_state; + wire [0:4] pf_state_q; + wire [0:2] pf_count_d; + wire [0:2] pf_count_q; + wire [0:21] pf1_new_stride_d; + wire [0:21] pf1_new_stride_q; + wire [0:21] pf1_rpt_stride_q; + wire stride_match; + wire generate_pfetch; + wire [0:2] nxt_state_cntrl; + wire [0:1] burst_cnt_inc; + wire [0:21] pf2_next_stride_d; + wire [0:21] pf2_stride_q; + wire [61-`PF_IFAR_WIDTH+1:61] pf1_iar_d; + wire [61-`PF_IFAR_WIDTH+1:61] pf1_iar_q; + wire [61-`PF_IFAR_WIDTH+1:61] pf2_iar_q; + wire [64-(2**`GPR_WIDTH_ENC):59] pf1_data_ea_d; + wire [64-(2**`GPR_WIDTH_ENC):59] pf1_data_ea_q; + wire [64-(2**`GPR_WIDTH_ENC):59] pf1_new_data_ea; + wire [64-(2**`GPR_WIDTH_ENC):59] pf2_data_ea_d; + wire [64-(2**`GPR_WIDTH_ENC):59] pf2_data_ea_q; + wire [0:1] pf1_pf_state_d; + wire [0:1] pf1_pf_state_q; + wire [0:1] pf2_next_state_d; + wire [0:1] pf1_update_state; + wire [0:1] pf2_pf_state_q; + wire [0:1] pf1_burst_cnt_d; + wire [0:1] pf1_burst_cnt_q; + wire [0:1] pf2_burst_cnt_d; + wire [0:1] pf2_burst_cnt_q; + wire pf1_dup_flag_d; + wire pf1_dup_flag_q; + wire [0:2] ex8_pf_hits_d; + wire [0:2] ex8_pf_hits_q; + wire [0:1] ex8_rpt_pe_d; + wire [0:1] ex8_rpt_pe_q; + wire [38:59] ex8_last_dat_addr_q; + wire [0:21] ex8_stride_q; + wire [0:1] ex8_pf_state_q; + wire [0:1] ex8_burst_cnt_q; + wire ex8_dup_flag_q; + wire [0:2] pf1_hits_d; + wire [0:2] pf1_hits_q; + wire [0:1] pf1_rpt_pe_q; + wire [0:2] pf2_hits_q; + wire [0:1] pf2_rpt_pe_q; + wire [0:`THREADS-1] pf1_thrd_d; + wire [0:`THREADS-1] pf1_thrd_q; + wire [0:`THREADS-1] pf2_thrd_q; + wire [0:`THREADS-1] pf3_thrd_d; + wire [0:`THREADS-1] pf3_thrd_q; + wire pf2_gen_pfetch_q; + wire pf2_valid; + reg old_rpt_lru; + wire new_rpt_lru; + wire [0:31] rpt_lru_d; + wire [0:31] rpt_lru_q; + + wire [0:1] rpt_wen; + wire [0:1] rpt_rd_act; + wire [0:1] rpt_byp_val; + wire [0:4] rpt_wrt_addr; + wire [0:69] rpt_data_in; + wire [0:4] rpt_rd_addr; + wire [0:139] rpt_data_out; + wire [0:69] rpt_byp_dat_d; + wire [0:69] rpt_byp_dat_q; + wire [0:69] rpt_byp_dat1_d; + wire [0:69] rpt_byp_dat1_q; + wire [0:1] byp_rpt_ary_d; + wire [0:1] byp_rpt_ary_q; + wire [0:1] byp1_rpt_ary_d; + wire [0:1] byp1_rpt_ary_q; + wire [0:69] ex7_rpt_entry0; + wire [0:69] ex7_rpt_entry1; + wire entry0_hit; + wire entry1_hit; + wire [0:56] ex7_rpt_entry_mux; + wire [0:56] new_rpt_entry; + wire [0:21] new_stride_prelim; + wire same_cline; + wire pf1_stride_too_small_q; + wire pf1_same_cline_q; + wire stride_too_small; + wire stride_lessthan_cline_pos; + wire stride_lessthan_cline_neg; + + wire [0:`THREADS-1] ex6_thrd_q; + wire [0:`THREADS-1] ex7_thrd_q; + wire [0:`THREADS-1] ex8_thrd_q; + wire [64-(2**`GPR_WIDTH_ENC):59] ex6_eff_addr_q; + wire [64-(2**`GPR_WIDTH_ENC):59] ex7_eff_addr_q; + wire [64-(2**`GPR_WIDTH_ENC):59] ex8_eff_addr_q; + wire ex6_req_val_4pf_q; + wire ex7_req_val_4pf_d; + wire ex7_req_val_4pf_q; + wire ex8_req_val_4pf_q; + wire pf1_req_val_4pf_q; + wire pf2_req_val_4pf_d; + wire pf2_req_val_4pf_q; + wire ex5_valid_loadmiss; + wire ex6_loadmiss_q; + wire ex7_loadmiss_q; + wire pf3_req_val_d; + wire pf3_req_val_q; + wire [64-(2**`GPR_WIDTH_ENC):59] pf3_req_addr_d; + wire [64-(2**`GPR_WIDTH_ENC):59] pf3_req_addr_q; + wire block_dup_pfetch; + wire inj_pfetch_parity_q; + wire ex7_rpt_entry0_pe; + wire ex7_rpt_entry1_pe; + wire ex8_pfetch_pe_d; + wire ex8_pfetch_pe_q; + wire [57+`THREADS:64+`THREADS] ex7_rpt_entry0_par; + wire [57+`THREADS:64+`THREADS] ex7_rpt_entry1_par; + wire [0:`LDSTQ_ENTRIES-1] pf_itag_tbl_act; + wire ex6_pf_act; + wire ex7_pf_act; + wire ex8_pf_act; + wire pf1_act; + wire pf2_act; + wire pf3_act; + wire byp_act; + wire byp1_act; + wire rpt_func_scan_in; + wire rpt_func_scan_out; + + //-------------------------- + // constants + //-------------------------- + + parameter rv_i0_vld_offset = 0; + + parameter rv_i0_isLoad_offset = rv_i0_vld_offset + `THREADS; + parameter rv_i0_rte_lq_offset = rv_i0_isLoad_offset + 1; + parameter rv_i0_ifar_offset = rv_i0_rte_lq_offset + 1; + parameter rv_i0_itag_offset = rv_i0_ifar_offset + `PF_IFAR_WIDTH; + parameter rv_i1_vld_offset = rv_i0_itag_offset + `ITAG_SIZE_ENC; + parameter rv_i1_isLoad_offset = rv_i1_vld_offset + `THREADS; + parameter rv_i1_rte_lq_offset = rv_i1_isLoad_offset + 1; + parameter rv_i1_ifar_offset = rv_i1_rte_lq_offset + 1; + parameter rv_i1_itag_offset = rv_i1_ifar_offset + `PF_IFAR_WIDTH; + parameter cp_flush_offset = rv_i1_itag_offset + `ITAG_SIZE_ENC; + parameter cp_flush2_offset = cp_flush_offset + `THREADS; + parameter cp_flush3_offset = cp_flush2_offset + `THREADS; + parameter cp_flush4_offset = cp_flush3_offset + `THREADS; + parameter inj_pfetch_parity_offset = cp_flush4_offset + `THREADS; + parameter odq_resolved_offset = inj_pfetch_parity_offset + 1; + parameter odq_report_itag_offset = odq_resolved_offset + 1; + parameter odq_report_tid_offset = odq_report_itag_offset + `ITAG_SIZE_ENC; + parameter pf_iar_tbl_offset = odq_report_tid_offset + `THREADS; + parameter pf_itag_tbl_offset = pf_iar_tbl_offset + `PF_IFAR_WIDTH * `LDSTQ_ENTRIES; + parameter pf_tid_tbl_offset = pf_itag_tbl_offset + `ITAG_SIZE_ENC * `LDSTQ_ENTRIES; + parameter pf_iar_tbl_val_offset = pf_tid_tbl_offset + `THREADS * `LDSTQ_ENTRIES; + parameter ex6_iar_offset = pf_iar_tbl_val_offset + `LDSTQ_ENTRIES; + parameter ex7_iar_offset = ex6_iar_offset + `PF_IFAR_WIDTH; + parameter ex8_iar_offset = ex7_iar_offset + `PF_IFAR_WIDTH; + parameter ex6_thrd_offset = ex8_iar_offset + `PF_IFAR_WIDTH; + parameter ex7_thrd_offset = ex6_thrd_offset + `THREADS; + parameter ex8_thrd_offset = ex7_thrd_offset + `THREADS; + parameter ex6_eff_addr_offset = ex8_thrd_offset + `THREADS; + parameter ex7_eff_addr_offset = ex6_eff_addr_offset + (59-(64-(2**`GPR_WIDTH_ENC))+1); + parameter ex8_eff_addr_offset = ex7_eff_addr_offset + (59-(64-(2**`GPR_WIDTH_ENC))+1); + parameter ex6_req_val_4pf_offset = ex8_eff_addr_offset + (59-(64-(2**`GPR_WIDTH_ENC))+1); + parameter ex7_req_val_4pf_offset = ex6_req_val_4pf_offset + 1; + parameter ex8_req_val_4pf_offset = ex7_req_val_4pf_offset + 1; + parameter pf1_req_val_4pf_offset = ex8_req_val_4pf_offset + 1; + parameter pf2_req_val_4pf_offset = pf1_req_val_4pf_offset + 1; + parameter ex6_loadmiss_offset = pf2_req_val_4pf_offset + 1; + parameter ex7_loadmiss_offset = ex6_loadmiss_offset + 1; + parameter byp_rpt_ary_offset = ex7_loadmiss_offset + 1; + parameter byp1_rpt_ary_offset = byp_rpt_ary_offset + 2; + parameter rpt_byp_dat_offset = byp1_rpt_ary_offset + 2; + parameter rpt_byp_dat1_offset = rpt_byp_dat_offset + 70; + parameter ex8_last_dat_addr_offset = rpt_byp_dat1_offset + 70; + parameter ex8_stride_offset = ex8_last_dat_addr_offset + 22; + parameter ex8_pf_state_offset = ex8_stride_offset + 22; + parameter ex8_burst_cnt_offset = ex8_pf_state_offset + 2; + parameter ex8_dup_flag_offset = ex8_burst_cnt_offset + 2; + parameter ex8_pf_hits_offset = ex8_dup_flag_offset + 1; + parameter ex8_rpt_pe_offset = ex8_pf_hits_offset + 3; + parameter ex8_pfetch_pe_offset = ex8_rpt_pe_offset + 2; + parameter pfq_stride_offset = ex8_pfetch_pe_offset + 1; + parameter pfq_data_ea_offset = pfq_stride_offset + 22 * `PFETCH_Q_SIZE; + parameter pfq_thrd_offset = pfq_data_ea_offset + (59-(64-(2**`GPR_WIDTH_ENC))+1) * `PFETCH_Q_SIZE; + parameter pfq_dscr_offset = pfq_thrd_offset + `THREADS * `PFETCH_Q_SIZE; + parameter pfq_dup_flag_offset = pfq_dscr_offset + 3 * `PFETCH_Q_SIZE; + parameter pfq_full_offset = pfq_dup_flag_offset + `PFETCH_Q_SIZE; + parameter pfq_wrt_ptr_offset = pfq_full_offset + 1; + parameter pf_state_offset = pfq_wrt_ptr_offset + `PFETCH_Q_SIZE_ENC; + parameter pf_count_offset = pf_state_offset + 5; + parameter pf1_new_stride_offset = pf_count_offset + 3; + parameter pf1_rpt_stride_offset = pf1_new_stride_offset + 22; + parameter pf1_data_ea_offset = pf1_rpt_stride_offset + 22; + parameter pf1_iar_offset = pf1_data_ea_offset + (59-(64-(2**`GPR_WIDTH_ENC))+1); + parameter pf1_pf_state_offset = pf1_iar_offset + `PF_IFAR_WIDTH; + parameter pf1_burst_cnt_offset = pf1_pf_state_offset + 2; + parameter pf1_dup_flag_offset = pf1_burst_cnt_offset + 2; + parameter pf1_hits_offset = pf1_dup_flag_offset + 1; + parameter pf1_rpt_pe_offset = pf1_hits_offset + 3; + parameter pf1_thrd_offset = pf1_rpt_pe_offset + 2; + parameter pf1_same_cline_offset = pf1_thrd_offset + `THREADS; + parameter pf1_stride_too_small_offset = pf1_same_cline_offset + 1; + parameter pf2_gen_pfetch_offset = pf1_stride_too_small_offset + 1; + parameter pf2_rpt_stride_offset = pf2_gen_pfetch_offset + 1; + parameter pf2_data_ea_offset = pf2_rpt_stride_offset + 22; + parameter pf2_iar_offset = pf2_data_ea_offset + (59-(64-(2**`GPR_WIDTH_ENC))+1); + parameter pf2_pf_state_offset = pf2_iar_offset + `PF_IFAR_WIDTH; + parameter pf2_burst_cnt_offset = pf2_pf_state_offset + 2; + parameter pf2_hits_offset = pf2_burst_cnt_offset + 2; + parameter pf2_rpt_pe_offset = pf2_hits_offset + 3; + parameter pf2_thrd_offset = pf2_rpt_pe_offset + 2; + parameter rpt_lru_offset = pf2_thrd_offset + `THREADS; + parameter pfq_rd_ptr_offset = rpt_lru_offset + 32; + parameter pf3_stride_offset = pfq_rd_ptr_offset + `PFETCH_Q_SIZE_ENC; + parameter pf3_req_addr_offset = pf3_stride_offset + 22; + parameter pf3_req_val_offset = pf3_req_addr_offset + (59-(64-(2**`GPR_WIDTH_ENC))+1); + parameter pf3_thrd_offset = pf3_req_val_offset + 1; + + parameter scan_right = pf3_thrd_offset + `THREADS - 1; + + wire tiup; + wire tidn; + wire [0:scan_right] siv; + wire [0:scan_right] sov; + wire [0:31] value1; + wire [0:31] value2; + + //!! Bugspray Include: lq_pfetch + + assign tiup = 1'b1; + assign tidn = 1'b0; + assign value1 = 32'h00000001; + assign value2 = 32'h00000002; + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // SPR for prefetch depth + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + + generate + begin : xhdl0 + genvar tid; + for (tid = 0; tid <= `THREADS - 1; tid = tid + 1) + begin : sprThrd + assign pf_dscr_reg[tid] = {spr_pf_spr_dscr_lsd[tid], spr_pf_spr_dscr_snse[tid], spr_pf_spr_dscr_sse[tid], + spr_pf_spr_dscr_dpfd[tid * 3:(tid * 3) + 2]}; + assign pfetch_dis_thrd[tid] = pf_dscr_reg[tid][58] | (pf_dscr_reg[tid][61:62] == 2'b00); + end + end + endgenerate + + + always @(*) + begin: tid_pd_dis_p + reg pf_dis; + reg ex6_dis; + reg [58:63] pf_dscr; + integer tid; + + ex6_dis = 1'b0; + pf_dis = 1'b0; + pf_dscr = {6{1'b0}}; + for (tid = 0; tid <= `THREADS - 1; tid = tid + 1) + begin + ex6_dis = (pfetch_dis_thrd[tid] & ex6_thrd_q[tid]) | ex6_dis; + pf_dis = (pfetch_dis_thrd[tid] & pf1_thrd_q[tid]) | pf_dis; + pf_dscr = (pf_dscr_reg[tid] & {6{pf1_thrd_q[tid]}}) | pf_dscr; + end + ex6_pf_disable = ex6_dis; + pf1_disable = pf_dis; + pf1_dscr = pf_dscr; + end + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // latch iu signals before using + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + + assign rv_i0_vld_d = rv_lq_rv1_i0_vld; + assign rv_i1_vld_d = rv_lq_rv1_i1_vld; + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) rv_i0_vld_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rv_i0_vld_offset:rv_i0_vld_offset + `THREADS - 1]), + .scout(sov[rv_i0_vld_offset:rv_i0_vld_offset + `THREADS - 1]), + .din(rv_i0_vld_d), + .dout(rv_i0_vld_q) + ); + + + tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) rv_i0_isLoad_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rv_i0_isLoad_offset:rv_i0_isLoad_offset]), + .scout(sov[rv_i0_isLoad_offset:rv_i0_isLoad_offset]), + .din(rv_lq_rv1_i0_isLoad), + .dout(rv_i0_isLoad_q) + ); + + + tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) rv_i0_rte_lq_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rv_i0_rte_lq_offset:rv_i0_rte_lq_offset]), + .scout(sov[rv_i0_rte_lq_offset:rv_i0_rte_lq_offset]), + .din(rv_lq_rv1_i0_rte_lq), + .dout(rv_i0_rte_lq_q) + ); + + + tri_rlmreg_p #(.WIDTH(`PF_IFAR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) rv_i0_ifar_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rv_i0_ifar_offset:rv_i0_ifar_offset + `PF_IFAR_WIDTH - 1]), + .scout(sov[rv_i0_ifar_offset:rv_i0_ifar_offset + `PF_IFAR_WIDTH - 1]), + .din(rv_lq_rv1_i0_ifar), + .dout(rv_i0_ifar_q) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) rv_i0_itag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rv_i0_itag_offset:rv_i0_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[rv_i0_itag_offset:rv_i0_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(rv_lq_rv1_i0_itag), + .dout(rv_i0_itag_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) rv_i1_vld_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rv_i1_vld_offset:rv_i1_vld_offset + `THREADS - 1]), + .scout(sov[rv_i1_vld_offset:rv_i1_vld_offset + `THREADS - 1]), + .din(rv_i1_vld_d), + .dout(rv_i1_vld_q) + ); + + + tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) rv_i1_isLoad_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rv_i1_isLoad_offset:rv_i1_isLoad_offset]), + .scout(sov[rv_i1_isLoad_offset:rv_i1_isLoad_offset]), + .din(rv_lq_rv1_i1_isLoad), + .dout(rv_i1_isLoad_q) + ); + + + tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) rv_i1_rte_lq_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rv_i1_rte_lq_offset:rv_i1_rte_lq_offset]), + .scout(sov[rv_i1_rte_lq_offset:rv_i1_rte_lq_offset]), + .din(rv_lq_rv1_i1_rte_lq), + .dout(rv_i1_rte_lq_q) + ); + + + tri_rlmreg_p #(.WIDTH(`PF_IFAR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) rv_i1_ifar_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rv_i1_ifar_offset:rv_i1_ifar_offset + `PF_IFAR_WIDTH - 1]), + .scout(sov[rv_i1_ifar_offset:rv_i1_ifar_offset + `PF_IFAR_WIDTH - 1]), + .din(rv_lq_rv1_i1_ifar), + .dout(rv_i1_ifar_q) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) rv_i1_itag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rv_i1_itag_offset:rv_i1_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[rv_i1_itag_offset:rv_i1_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(rv_lq_rv1_i1_itag), + .dout(rv_i1_itag_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) cp_flush_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[cp_flush_offset:cp_flush_offset + `THREADS - 1]), + .scout(sov[cp_flush_offset:cp_flush_offset + `THREADS - 1]), + .din(iu_lq_cp_flush), + .dout(cp_flush_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) cp_flush2_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[cp_flush2_offset:cp_flush2_offset + `THREADS - 1]), + .scout(sov[cp_flush2_offset:cp_flush2_offset + `THREADS - 1]), + .din(cp_flush_q), + .dout(cp_flush2_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) cp_flush3_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[cp_flush3_offset:cp_flush3_offset + `THREADS - 1]), + .scout(sov[cp_flush3_offset:cp_flush3_offset + `THREADS - 1]), + .din(cp_flush2_q), + .dout(cp_flush3_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) cp_flush4_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[cp_flush4_offset:cp_flush4_offset + `THREADS - 1]), + .scout(sov[cp_flush4_offset:cp_flush4_offset + `THREADS - 1]), + .din(cp_flush3_q), + .dout(cp_flush4_q) + ); + + + tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) inj_pfetch_parity_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[inj_pfetch_parity_offset:inj_pfetch_parity_offset]), + .scout(sov[inj_pfetch_parity_offset:inj_pfetch_parity_offset]), + .din(pc_lq_inj_prefetcher_parity), + .dout(inj_pfetch_parity_q) + ); + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // Save iar and itag from dispatch + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + + assign new_itag_i0_val = |(rv_i0_vld_q & (~(cp_flush_q | cp_flush2_q | cp_flush3_q | cp_flush4_q))) & rv_i0_rte_lq_q & rv_i0_isLoad_q; + assign new_itag_i1_val = |(rv_i1_vld_q & (~(cp_flush_q | cp_flush2_q | cp_flush3_q | cp_flush4_q))) & rv_i1_rte_lq_q & rv_i1_isLoad_q; + + assign pf_iar_i0_wen[0] = new_itag_i0_val & (pf_iar_tbl_val_q[0] == 1'b0); + assign pf_iar_i0_wen[1] = new_itag_i0_val & (pf_iar_tbl_val_q[0:1] == 2'b10); + + generate + begin : xhdl1 + genvar i; + for (i = 2; i <= `LDSTQ_ENTRIES - 1; i = i + 1) + begin : pf_iar_i0_wen_gen + assign pf_iar_i0_wen[i] = new_itag_i0_val & &(pf_iar_tbl_val_q[0:i - 1]) & (pf_iar_tbl_val_q[i] == 1'b0); + end + end + endgenerate + + assign pf_iar_val_for_i1 = pf_iar_tbl_val_q | pf_iar_i0_wen; + + assign pf_iar_i1_wen[0] = new_itag_i1_val & (pf_iar_val_for_i1[0] == 1'b0); + assign pf_iar_i1_wen[1] = new_itag_i1_val & (pf_iar_val_for_i1[0:1] == 2'b10); + + generate + begin : xhdl2 + genvar i; + for (i = 2; i <= `LDSTQ_ENTRIES - 1; i = i + 1) + begin : pf_iar_i1_wen_gen + assign pf_iar_i1_wen[i] = new_itag_i1_val & &(pf_iar_val_for_i1[0:i - 1]) & (pf_iar_val_for_i1[i] == 1'b0); + end + end + endgenerate + + // latch itag report from odq + + + tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) odq_resolved_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[odq_resolved_offset:odq_resolved_offset]), + .scout(sov[odq_resolved_offset:odq_resolved_offset]), + .din(odq_pf_resolved), + .dout(odq_resolved_q) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) odq_report_itag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[odq_report_itag_offset:odq_report_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[odq_report_itag_offset:odq_report_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(odq_pf_report_itag), + .dout(odq_report_itag_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) odq_report_tid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[odq_report_tid_offset:odq_report_tid_offset + `THREADS - 1]), + .scout(sov[odq_report_tid_offset:odq_report_tid_offset + `THREADS - 1]), + .din(odq_pf_report_tid), + .dout(odq_report_tid_q) + ); + + generate + begin : xhdl3 + genvar i; + for (i = 0; i <= `LDSTQ_ENTRIES - 1; i = i + 1) + begin : done_itag_match_gen + assign pf_iar_tbl_reset[i] = (odq_report_itag_q == pf_itag_tbl_q[i]) & + |(odq_report_tid_q & pf_tid_tbl_q[i]) & + odq_resolved_q & pf_iar_tbl_val_q[i]; + end + end + endgenerate + + generate + begin : xhdl4 + genvar i; + for (i = 0; i <= `LDSTQ_ENTRIES - 1; i = i + 1) + begin : pf_iar_table + + assign pf_itag_tbl_act[i] = pf_iar_i0_wen[i] | pf_iar_i1_wen[i] | pf_iar_tbl_reset[i] | |(cp_flush_q); + + assign pf_iar_tbl_d[i] = (pf_iar_i0_wen[i] == 1'b1) ? rv_i0_ifar_q : + (pf_iar_i1_wen[i] == 1'b1) ? rv_i1_ifar_q : + pf_iar_tbl_q[i]; + assign pf_itag_tbl_d[i] = (pf_iar_i0_wen[i] == 1'b1) ? rv_i0_itag_q : + (pf_iar_i1_wen[i] == 1'b1) ? rv_i1_itag_q : + pf_itag_tbl_q[i]; + assign pf_tid_tbl_d[i] = (pf_iar_i0_wen[i] == 1'b1) ? rv_i0_vld_q : + (pf_iar_i1_wen[i] == 1'b1) ? rv_i1_vld_q : + pf_tid_tbl_q[i]; + + assign pf_iar_tbl_val_d[i] = pf_iar_i0_wen[i] | pf_iar_i1_wen[i] | + (pf_iar_tbl_val_q[i] & (~(|(pf_tid_tbl_q[i] & cp_flush_q) | pf_iar_tbl_reset[i]))); + + + tri_rlmreg_p #(.WIDTH(`PF_IFAR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) pf_iar_tbl_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pf_itag_tbl_act[i]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[pf_iar_tbl_offset + `PF_IFAR_WIDTH * i:pf_iar_tbl_offset + `PF_IFAR_WIDTH * (i + 1) - 1]), + .scout(sov[pf_iar_tbl_offset + `PF_IFAR_WIDTH * i:pf_iar_tbl_offset + `PF_IFAR_WIDTH * (i + 1) - 1]), + .din(pf_iar_tbl_d[i]), + .dout(pf_iar_tbl_q[i]) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) pf_itag_tbl_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pf_itag_tbl_act[i]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[pf_itag_tbl_offset + `ITAG_SIZE_ENC * i:pf_itag_tbl_offset + `ITAG_SIZE_ENC * (i + 1) - 1]), + .scout(sov[pf_itag_tbl_offset + `ITAG_SIZE_ENC * i:pf_itag_tbl_offset + `ITAG_SIZE_ENC * (i + 1) - 1]), + .din(pf_itag_tbl_d[i]), + .dout(pf_itag_tbl_q[i]) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) pf_tid_tbl_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pf_itag_tbl_act[i]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[pf_tid_tbl_offset + `THREADS * i:pf_tid_tbl_offset + `THREADS * (i + 1) - 1]), + .scout(sov[pf_tid_tbl_offset + `THREADS * i:pf_tid_tbl_offset + `THREADS * (i + 1) - 1]), + .din(pf_tid_tbl_d[i]), + .dout(pf_tid_tbl_q[i]) + ); + end + end + endgenerate + + + tri_rlmreg_p #(.WIDTH(`LDSTQ_ENTRIES), .INIT(0)) latch_pf_iar_tbl_val( + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(siv[pf_iar_tbl_val_offset:pf_iar_tbl_val_offset + `LDSTQ_ENTRIES - 1]), + .scout(sov[pf_iar_tbl_val_offset:pf_iar_tbl_val_offset + `LDSTQ_ENTRIES - 1]), + .din(pf_iar_tbl_val_d), + .dout(pf_iar_tbl_val_q) + ); + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // lookup iar from itag-iar table + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + + generate + begin : xhdl5 + genvar i; + for (i = 0; i <= `LDSTQ_ENTRIES - 1; i = i + 1) + begin : new_itag_match_gen + assign ex5_itag_match[i] = (dcc_pf_ex5_itag == pf_itag_tbl_q[i]) & + |(dcc_pf_ex5_thrd_id & pf_tid_tbl_q[i]) & + pf_iar_tbl_val_q[i]; + end + end + endgenerate + + always @(*) + begin: ex5_iar_proc + reg [61-`PF_IFAR_WIDTH+1:61] iar; + integer i; + iar = {61-(61-`PF_IFAR_WIDTH+1)+1{1'b0}}; + for (i = 0; i <= `LDSTQ_ENTRIES - 1; i = i + 1) + iar = ({`PF_IFAR_WIDTH{ex5_itag_match[i]}} & pf_iar_tbl_q[i]) | iar; + + ex5_iar = iar; + end + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // stage out signals to ex7 + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + + assign ex6_pf_act = dcc_pf_ex5_act | ex6_req_val_4pf_q; + assign ex7_pf_act = (ex6_req_val_4pf_q & (~ex6_pf_disable)) | ex7_req_val_4pf_q; + assign ex8_pf_act = ex7_req_val_4pf_q | ex8_req_val_4pf_q; + assign pf1_act = ex8_req_val_4pf_q | pf1_req_val_4pf_q; + assign pf2_act = pf1_req_val_4pf_q | pf2_req_val_4pf_q; + + + tri_rlmreg_p #(.WIDTH(`PF_IFAR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex6_iar_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex6_pf_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_iar_offset:ex6_iar_offset + `PF_IFAR_WIDTH - 1]), + .scout(sov[ex6_iar_offset:ex6_iar_offset + `PF_IFAR_WIDTH - 1]), + .din(ex5_iar), + .dout(ex6_iar_q) + ); + + + tri_rlmreg_p #(.WIDTH(`PF_IFAR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex7_iar_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex7_pf_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex7_iar_offset:ex7_iar_offset + `PF_IFAR_WIDTH - 1]), + .scout(sov[ex7_iar_offset:ex7_iar_offset + `PF_IFAR_WIDTH - 1]), + .din(ex6_iar_q), + .dout(ex7_iar_q) + ); + + + tri_rlmreg_p #(.WIDTH(`PF_IFAR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex8_iar_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex8_pf_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex8_iar_offset:ex8_iar_offset + `PF_IFAR_WIDTH - 1]), + .scout(sov[ex8_iar_offset:ex8_iar_offset + `PF_IFAR_WIDTH - 1]), + .din(ex7_iar_q), + .dout(ex8_iar_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex6_thrd_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex6_pf_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_thrd_offset:ex6_thrd_offset + `THREADS - 1]), + .scout(sov[ex6_thrd_offset:ex6_thrd_offset + `THREADS - 1]), + .din(dcc_pf_ex5_thrd_id), + .dout(ex6_thrd_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex7_thrd_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex7_pf_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex7_thrd_offset:ex7_thrd_offset + `THREADS - 1]), + .scout(sov[ex7_thrd_offset:ex7_thrd_offset + `THREADS - 1]), + .din(ex6_thrd_q), + .dout(ex7_thrd_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex8_thrd_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex8_pf_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex8_thrd_offset:ex8_thrd_offset + `THREADS - 1]), + .scout(sov[ex8_thrd_offset:ex8_thrd_offset + `THREADS - 1]), + .din(ex7_thrd_q), + .dout(ex8_thrd_q) + ); + + + tri_rlmreg_p #(.WIDTH((59-(64-(2**`GPR_WIDTH_ENC))+1)), .INIT(0), .NEEDS_SRESET(1)) ex6_eff_addr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex6_pf_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_eff_addr_offset:ex6_eff_addr_offset + (59-(64-(2**`GPR_WIDTH_ENC))+1) - 1]), + .scout(sov[ex6_eff_addr_offset:ex6_eff_addr_offset + (59-(64-(2**`GPR_WIDTH_ENC))+1) - 1]), + .din(dcc_pf_ex5_eff_addr), + .dout(ex6_eff_addr_q) + ); + + + tri_rlmreg_p #(.WIDTH((59-(64-(2**`GPR_WIDTH_ENC))+1)), .INIT(0), .NEEDS_SRESET(1)) ex7_eff_addr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex7_pf_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex7_eff_addr_offset:ex7_eff_addr_offset + (59-(64-(2**`GPR_WIDTH_ENC))+1) - 1]), + .scout(sov[ex7_eff_addr_offset:ex7_eff_addr_offset + (59-(64-(2**`GPR_WIDTH_ENC))+1) - 1]), + .din(ex6_eff_addr_q), + .dout(ex7_eff_addr_q) + ); + + + tri_rlmreg_p #(.WIDTH((59-(64-(2**`GPR_WIDTH_ENC))+1)), .INIT(0), .NEEDS_SRESET(1)) ex8_eff_addr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex8_pf_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex8_eff_addr_offset:ex8_eff_addr_offset + (59-(64-(2**`GPR_WIDTH_ENC))+1) - 1]), + .scout(sov[ex8_eff_addr_offset:ex8_eff_addr_offset + (59-(64-(2**`GPR_WIDTH_ENC))+1) - 1]), + .din(ex7_eff_addr_q), + .dout(ex8_eff_addr_q) + ); + + + tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex6_req_val_4pf_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex6_pf_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_req_val_4pf_offset:ex6_req_val_4pf_offset]), + .scout(sov[ex6_req_val_4pf_offset:ex6_req_val_4pf_offset]), + .din(dcc_pf_ex5_req_val_4pf), + .dout(ex6_req_val_4pf_q) + ); + + assign ex7_req_val_4pf_d = ex6_req_val_4pf_q & (~ex6_pf_disable); + + + tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex7_req_val_4pf_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex7_pf_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex7_req_val_4pf_offset:ex7_req_val_4pf_offset]), + .scout(sov[ex7_req_val_4pf_offset:ex7_req_val_4pf_offset]), + .din(ex7_req_val_4pf_d), + .dout(ex7_req_val_4pf_q) + ); + + + tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex8_req_val_4pf_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex8_pf_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex8_req_val_4pf_offset:ex8_req_val_4pf_offset]), + .scout(sov[ex8_req_val_4pf_offset:ex8_req_val_4pf_offset]), + .din(ex7_req_val_4pf_q), + .dout(ex8_req_val_4pf_q) + ); + + + tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) pf1_req_val_4pf_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pf1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[pf1_req_val_4pf_offset:pf1_req_val_4pf_offset]), + .scout(sov[pf1_req_val_4pf_offset:pf1_req_val_4pf_offset]), + .din(ex8_req_val_4pf_q), + .dout(pf1_req_val_4pf_q) + ); + + assign pf2_req_val_4pf_d = pf1_req_val_4pf_q & (~pf1_stride_too_small_q); + + + tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) pf2_req_val_4pf_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pf2_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[pf2_req_val_4pf_offset:pf2_req_val_4pf_offset]), + .scout(sov[pf2_req_val_4pf_offset:pf2_req_val_4pf_offset]), + .din(pf2_req_val_4pf_d), + .dout(pf2_req_val_4pf_q) + ); + + assign ex5_valid_loadmiss = dcc_pf_ex5_loadmiss & dcc_pf_ex5_req_val_4pf; + + + tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex6_loadmiss_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex6_pf_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_loadmiss_offset:ex6_loadmiss_offset]), + .scout(sov[ex6_loadmiss_offset:ex6_loadmiss_offset]), + .din(ex5_valid_loadmiss), + .dout(ex6_loadmiss_q) + ); + + + tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex7_loadmiss_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex7_pf_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex7_loadmiss_offset:ex7_loadmiss_offset]), + .scout(sov[ex7_loadmiss_offset:ex7_loadmiss_offset]), + .din(ex6_loadmiss_q), + .dout(ex7_loadmiss_q) + ); + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // lookup entry in RPT (Reference Predictor Table) + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + + assign rpt_rd_addr = ex5_iar[57:61]; + + tri_32x70_2w_1r1w rpt( + // POWER PINS + .gnd(gnd), + .vdd(vdd), + .vcs(vcs), + // CLOCK and CLOCKCONTROL ports + .nclk(nclk), + .rd_act(rpt_rd_act[0:1]), + .wr_act(rpt_wen[0:1]), + .sg_0(sg_0), + .abst_sl_thold_0(abst_sl_thold_0), + .ary_nsl_thold_0(ary_nsl_thold_0), + .time_sl_thold_0(time_sl_thold_0), + .repr_sl_thold_0(repr_sl_thold_0), + .func_sl_force(func_sl_force), + .func_sl_thold_0_b(func_sl_thold_0_b), + .g8t_clkoff_dc_b(g8t_clkoff_dc_b), + .ccflush_dc(pc_lq_ccflush_dc), + .scan_dis_dc_b(an_ac_scan_dis_dc_b), + .scan_diag_dc(an_ac_scan_diag_dc), + .g8t_d_mode_dc(g8t_d_mode_dc), + .g8t_mpw1_dc_b(g8t_mpw1_dc_b[0:4]), + .g8t_mpw2_dc_b(g8t_mpw2_dc_b), + .g8t_delay_lclkr_dc(g8t_delay_lclkr_dc[0:4]), + .d_mode_dc(d_mode_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .delay_lclkr_dc(delay_lclkr_dc), + // ABIST + .wr_abst_act(pc_xu_abist_g8t_wenb_q), + .rd0_abst_act(pc_xu_abist_g8t1p_renb_0_q), + .abist_di(pc_xu_abist_di_0_q[0:3]), + .abist_bw_odd(pc_xu_abist_g8t_bw_1_q), + .abist_bw_even(pc_xu_abist_g8t_bw_0_q), + .abist_wr_adr(pc_xu_abist_waddr_0_q[0:4]), + .abist_rd0_adr(pc_xu_abist_raddr_0_q[0:4]), + .tc_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc), + .abist_ena_1(pc_xu_abist_ena_dc), + .abist_g8t_rd0_comp_ena(pc_xu_abist_wl64_comp_ena_q), + .abist_raw_dc_b(pc_xu_abist_raw_dc_b), + .obs0_abist_cmp(pc_xu_abist_g8t_dcomp_q[0:3]), + // Scan + .abst_scan_in(abst_scan_in[0:1]), + .time_scan_in(time_scan_in), + .repr_scan_in(repr_scan_in), + .func_scan_in(rpt_func_scan_in), + .abst_scan_out(abst_scan_out[0:1]), + .time_scan_out(time_scan_out), + .repr_scan_out(repr_scan_out), + .func_scan_out(rpt_func_scan_out), + // BOLT-ON + .lcb_bolt_sl_thold_0(bolt_sl_thold_0), + .pc_bo_enable_2(pc_bo_enable_2), // general bolt-on enable + .pc_bo_reset(pc_xu_bo_reset), // reset + .pc_bo_unload(pc_xu_bo_unload), // unload sticky bits + .pc_bo_repair(pc_xu_bo_repair), // execute sticky bit decode + .pc_bo_shdata(pc_xu_bo_shdata), // shift data for timing write and diag loop + .pc_bo_select(pc_xu_bo_select[0:1]), // select for mask and hier writes + .bo_pc_failout(xu_pc_bo_fail[0:1]), // fail/no-fix reg + .bo_pc_diagloop(xu_pc_bo_diagout[0:1]), + .tri_lcb_mpw1_dc_b(mpw1_dc_b), + .tri_lcb_mpw2_dc_b(mpw2_dc_b), + .tri_lcb_delay_lclkr_dc(delay_lclkr_dc), + .tri_lcb_clkoff_dc_b(clkoff_dc_b), + .tri_lcb_act_dis_dc(tidn), + // Write Ports + .wr_way(rpt_wen[0:1]), + .wr_addr(rpt_wrt_addr[0:4]), + .data_in(rpt_data_in[0:69]), + // Read Ports + .rd_addr(rpt_rd_addr[0:4]), + .data_out(rpt_data_out[0:139]) + ); + + // bypass around array when wrt addr equals read addr (and turn off rd act) + + assign rpt_byp_val[0] = (rpt_rd_addr == rpt_wrt_addr) & rpt_wen[0]; + assign rpt_byp_val[1] = (rpt_rd_addr == rpt_wrt_addr) & rpt_wen[1]; + + assign rpt_rd_act[0] = dcc_pf_ex5_act & ~rpt_byp_val[0] & ~(&(pfetch_dis_thrd)); + assign rpt_rd_act[1] = dcc_pf_ex5_act & ~rpt_byp_val[1] & ~(&(pfetch_dis_thrd)); + + assign byp_act = rpt_wen[0] | rpt_wen[1]; + assign byp1_act = |(byp_rpt_ary_q); + + assign byp_rpt_ary_d = (~rpt_rd_act); + assign byp1_rpt_ary_d = byp_rpt_ary_q; + + assign rpt_byp_dat_d = rpt_data_in[0:69]; + assign rpt_byp_dat1_d = rpt_byp_dat_q[0:69]; + + assign ex7_rpt_entry0 = (byp1_rpt_ary_q[0] == 1'b1) ? rpt_byp_dat1_q[0:69] : + rpt_data_out[0:69]; + + assign ex7_rpt_entry1 = (byp1_rpt_ary_q[1] == 1'b1) ? rpt_byp_dat1_q[0:69] : + rpt_data_out[70:139]; + + assign ex7_rpt_entry0_par[57 + `THREADS] = ^(ex7_rpt_entry0[0:7]); + assign ex7_rpt_entry0_par[58 + `THREADS] = ^(ex7_rpt_entry0[8:15]); + assign ex7_rpt_entry0_par[59 + `THREADS] = ^(ex7_rpt_entry0[16:23]); + assign ex7_rpt_entry0_par[60 + `THREADS] = ^(ex7_rpt_entry0[24:31]); + assign ex7_rpt_entry0_par[61 + `THREADS] = ^(ex7_rpt_entry0[32:39]); + assign ex7_rpt_entry0_par[62 + `THREADS] = ^(ex7_rpt_entry0[40:47]); + assign ex7_rpt_entry0_par[63 + `THREADS] = ^(ex7_rpt_entry0[48:55]); + assign ex7_rpt_entry0_par[64 + `THREADS] = ^(ex7_rpt_entry0[56:57 + `THREADS - 1]); + + assign ex7_rpt_entry1_par[57 + `THREADS] = ^(ex7_rpt_entry1[0:7]); + assign ex7_rpt_entry1_par[58 + `THREADS] = ^(ex7_rpt_entry1[8:15]); + assign ex7_rpt_entry1_par[59 + `THREADS] = ^(ex7_rpt_entry1[16:23]); + assign ex7_rpt_entry1_par[60 + `THREADS] = ^(ex7_rpt_entry1[24:31]); + assign ex7_rpt_entry1_par[61 + `THREADS] = ^(ex7_rpt_entry1[32:39]); + assign ex7_rpt_entry1_par[62 + `THREADS] = ^(ex7_rpt_entry1[40:47]); + assign ex7_rpt_entry1_par[63 + `THREADS] = ^(ex7_rpt_entry1[48:55]); + assign ex7_rpt_entry1_par[64 + `THREADS] = ^(ex7_rpt_entry1[56:57 + `THREADS - 1]); + + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) byp_rpt_ary_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[byp_rpt_ary_offset:byp_rpt_ary_offset + 2 - 1]), + .scout(sov[byp_rpt_ary_offset:byp_rpt_ary_offset + 2 - 1]), + .din(byp_rpt_ary_d), + .dout(byp_rpt_ary_q) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) byp1_rpt_ary_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[byp1_rpt_ary_offset:byp1_rpt_ary_offset + 2 - 1]), + .scout(sov[byp1_rpt_ary_offset:byp1_rpt_ary_offset + 2 - 1]), + .din(byp1_rpt_ary_d), + .dout(byp1_rpt_ary_q) + ); + + + tri_rlmreg_p #(.WIDTH(70), .INIT(0), .NEEDS_SRESET(1)) rpt_byp_dat_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(byp_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rpt_byp_dat_offset:rpt_byp_dat_offset + 70 - 1]), + .scout(sov[rpt_byp_dat_offset:rpt_byp_dat_offset + 70 - 1]), + .din(rpt_byp_dat_d), + .dout(rpt_byp_dat_q) + ); + + tri_rlmreg_p #(.WIDTH(70), .INIT(0), .NEEDS_SRESET(1)) rpt_byp_dat1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(byp1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rpt_byp_dat1_offset:rpt_byp_dat1_offset + 70 - 1]), + .scout(sov[rpt_byp_dat1_offset:rpt_byp_dat1_offset + 70 - 1]), + .din(rpt_byp_dat1_d), + .dout(rpt_byp_dat1_q) + ); + + + + assign ex7_rpt_entry0_pe = |(ex7_rpt_entry0_par ^ ex7_rpt_entry0[57 + `THREADS:57 + `THREADS + 7]); + assign ex7_rpt_entry1_pe = |(ex7_rpt_entry1_par ^ ex7_rpt_entry1[57 + `THREADS:57 + `THREADS + 7]); + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // Check entry hit/miss and create new entry + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + + assign entry0_hit = ex7_rpt_entry0[0] & ex7_req_val_4pf_q & (~ex7_rpt_entry0_pe) & + (ex7_iar_q[50:56] == ex7_rpt_entry0[45:51]) & + (ex7_thrd_q == ex7_rpt_entry0[57:57 + `THREADS - 1]); + + assign entry1_hit = ex7_rpt_entry1[0] & ex7_req_val_4pf_q & (~ex7_rpt_entry1_pe) & + (ex7_iar_q[50:56] == ex7_rpt_entry1[45:51]) & + (ex7_thrd_q == ex7_rpt_entry1[57:57 + `THREADS - 1]); + + assign new_rpt_entry[0] = 1'b1; // valid bit + assign new_rpt_entry[1:22] = ex7_eff_addr_q[38:59]; // last data address + assign new_rpt_entry[23:44] = {22{1'b0}}; // stride + assign new_rpt_entry[45:51] = ex7_iar_q[50:56]; // iar tag + assign new_rpt_entry[52:53] = 2'b01; // prefetch state + assign new_rpt_entry[54:55] = 2'b00; // burst counter + assign new_rpt_entry[56] = 1'b0; // duplicate flag + + assign ex7_rpt_entry_mux = (entry0_hit == 1'b1) ? ex7_rpt_entry0[0:56] : + (entry1_hit == 1'b1) ? ex7_rpt_entry1[0:56] : + new_rpt_entry; + + assign ex8_pf_hits_d = {entry0_hit, entry1_hit, ex7_loadmiss_q}; + + assign ex8_rpt_pe_d = {ex7_rpt_entry0_pe, ex7_rpt_entry1_pe}; + + assign ex8_pfetch_pe_d = ex7_req_val_4pf_q & (ex7_rpt_entry0_pe | ex7_rpt_entry1_pe); + + + tri_rlmreg_p #(.WIDTH(22), .INIT(0), .NEEDS_SRESET(1)) ex8_last_dat_addr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex8_pf_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex8_last_dat_addr_offset:ex8_last_dat_addr_offset + 22 - 1]), + .scout(sov[ex8_last_dat_addr_offset:ex8_last_dat_addr_offset + 22 - 1]), + .din(ex7_rpt_entry_mux[1:22]), + .dout(ex8_last_dat_addr_q) + ); + + + tri_rlmreg_p #(.WIDTH(22), .INIT(0), .NEEDS_SRESET(1)) ex8_stride_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex8_pf_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex8_stride_offset:ex8_stride_offset + 22 - 1]), + .scout(sov[ex8_stride_offset:ex8_stride_offset + 22 - 1]), + .din(ex7_rpt_entry_mux[23:44]), + .dout(ex8_stride_q) + ); + + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex8_pf_state_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex8_pf_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex8_pf_state_offset:ex8_pf_state_offset + 2 - 1]), + .scout(sov[ex8_pf_state_offset:ex8_pf_state_offset + 2 - 1]), + .din(ex7_rpt_entry_mux[52:53]), + .dout(ex8_pf_state_q) + ); + + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex8_burst_cnt_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex8_pf_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex8_burst_cnt_offset:ex8_burst_cnt_offset + 2 - 1]), + .scout(sov[ex8_burst_cnt_offset:ex8_burst_cnt_offset + 2 - 1]), + .din(ex7_rpt_entry_mux[54:55]), + .dout(ex8_burst_cnt_q) + ); + + + tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex8_dup_flag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex8_pf_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex8_dup_flag_offset:ex8_dup_flag_offset]), + .scout(sov[ex8_dup_flag_offset:ex8_dup_flag_offset]), + .din(ex7_rpt_entry_mux[56]), + .dout(ex8_dup_flag_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex8_pf_hits_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex8_pf_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex8_pf_hits_offset:ex8_pf_hits_offset + 3 - 1]), + .scout(sov[ex8_pf_hits_offset:ex8_pf_hits_offset + 3 - 1]), + .din(ex8_pf_hits_d), + .dout(ex8_pf_hits_q) + ); + + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex8_rpt_pe_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex8_pf_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex8_rpt_pe_offset:ex8_rpt_pe_offset + 2 - 1]), + .scout(sov[ex8_rpt_pe_offset:ex8_rpt_pe_offset + 2 - 1]), + .din(ex8_rpt_pe_d), + .dout(ex8_rpt_pe_q) + ); + + tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex8_pfetch_pe_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ex8_pf_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex8_pfetch_pe_offset:ex8_pfetch_pe_offset]), + .scout(sov[ex8_pfetch_pe_offset:ex8_pfetch_pe_offset]), + .din(ex8_pfetch_pe_d), + .dout(ex8_pfetch_pe_q) + ); + + + tri_direct_err_rpt #(.WIDTH(1)) pfetch_err_rpt( + .vd(vdd), + .gd(gnd), + .err_in(ex8_pfetch_pe_q), + .err_out(lq_pc_err_prefetcher_parity) + ); + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // Compute new Stride + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + + assign new_stride_prelim = ex8_eff_addr_q[38:59] - ex8_last_dat_addr_q[38:59]; // Data EA - last address + + assign same_cline = ex8_eff_addr_q[38:57] == ex8_last_dat_addr_q[38:57]; + + // transaction dropped if stride is not at least half a cache line (stride of 0, 1 or -1) + assign stride_too_small = ((new_stride_prelim == {20'h00000, 2'b00}) | // 0 + (new_stride_prelim == {20'h00000, 2'b01}) | // +1 (+16 bytes) + (new_stride_prelim == {20'hFFFFF, 2'b11})) & // -1 (-16 bytes) + (ex8_pf_hits_q[0] | ex8_pf_hits_q[1]); // hit on either entry 0 or 1 + + //if stride is less than a cache line, round up + + assign stride_lessthan_cline_pos = (new_stride_prelim == {20'h00000, 2'b10}) | // +2 (+32 bytes) + (new_stride_prelim == {20'h00000, 2'b11}); // +3 (+48 bytes) + + + assign stride_lessthan_cline_neg = (new_stride_prelim == {20'hFFFFF, 2'b10}) | // -2 (-32 bytes) + (new_stride_prelim == {20'hFFFFF, 2'b01}); // -3 (-48 bytes) + + assign pf1_new_stride_d = (stride_lessthan_cline_pos == 1'b1) ? {20'h00001, 2'b00} : + (stride_lessthan_cline_neg == 1'b1) ? {20'hFFFFF, 2'b00} : + new_stride_prelim; + + assign pf1_iar_d = ex8_iar_q; + assign pf1_data_ea_d = ex8_eff_addr_q; + assign pf1_pf_state_d = ex8_pf_state_q; + assign pf1_burst_cnt_d = ex8_burst_cnt_q; + assign pf1_dup_flag_d = ex8_dup_flag_q; + assign pf1_hits_d = ex8_pf_hits_q; + assign pf1_thrd_d = ex8_thrd_q; + + + tri_rlmreg_p #(.WIDTH(22), .INIT(0)) latch_pf1_new_stride( + .nclk(nclk), + .act(pf1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(siv[pf1_new_stride_offset:pf1_new_stride_offset + 22 - 1]), + .scout(sov[pf1_new_stride_offset:pf1_new_stride_offset + 22 - 1]), + .din(pf1_new_stride_d), + .dout(pf1_new_stride_q) + ); + + + tri_rlmreg_p #(.WIDTH(22), .INIT(0)) latch_pf1_rpt_stride( + .nclk(nclk), + .act(pf1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(siv[pf1_rpt_stride_offset:pf1_rpt_stride_offset + 22 - 1]), + .scout(sov[pf1_rpt_stride_offset:pf1_rpt_stride_offset + 22 - 1]), + .din(ex8_stride_q), + .dout(pf1_rpt_stride_q) + ); + + + tri_rlmreg_p #(.WIDTH((59-(64-(2**`GPR_WIDTH_ENC))+1)), .INIT(0)) latch_pf1_data_ea( + .nclk(nclk), + .act(pf1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(siv[pf1_data_ea_offset:pf1_data_ea_offset + (59-(64-(2**`GPR_WIDTH_ENC))+1) - 1]), + .scout(sov[pf1_data_ea_offset:pf1_data_ea_offset + (59-(64-(2**`GPR_WIDTH_ENC))+1) - 1]), + .din(pf1_data_ea_d), + .dout(pf1_data_ea_q) + ); + + + tri_rlmreg_p #(.WIDTH(`PF_IFAR_WIDTH), .INIT(0)) latch_pf1_iar( + .nclk(nclk), + .act(pf1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(siv[pf1_iar_offset:pf1_iar_offset + `PF_IFAR_WIDTH - 1]), + .scout(sov[pf1_iar_offset:pf1_iar_offset + `PF_IFAR_WIDTH - 1]), + .din(pf1_iar_d), + .dout(pf1_iar_q) + ); + + + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) latch_pf1_pf_state( + .nclk(nclk), + .act(pf1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(siv[pf1_pf_state_offset:pf1_pf_state_offset + 2 - 1]), + .scout(sov[pf1_pf_state_offset:pf1_pf_state_offset + 2 - 1]), + .din(pf1_pf_state_d), + .dout(pf1_pf_state_q) + ); + + + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) latch_pf1_burst_cnt( + .nclk(nclk), + .act(pf1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(siv[pf1_burst_cnt_offset:pf1_burst_cnt_offset + 2 - 1]), + .scout(sov[pf1_burst_cnt_offset:pf1_burst_cnt_offset + 2 - 1]), + .din(pf1_burst_cnt_d), + .dout(pf1_burst_cnt_q) + ); + + + tri_rlmreg_p #(.WIDTH(1), .INIT(0)) latch_pf1_dup_flag( + .nclk(nclk), + .act(pf1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(siv[pf1_dup_flag_offset:pf1_dup_flag_offset]), + .scout(sov[pf1_dup_flag_offset:pf1_dup_flag_offset]), + .din(pf1_dup_flag_d), + .dout(pf1_dup_flag_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) latch_pf1_hits( + .nclk(nclk), + .act(pf1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(siv[pf1_hits_offset:pf1_hits_offset + 3 - 1]), + .scout(sov[pf1_hits_offset:pf1_hits_offset + 3 - 1]), + .din(pf1_hits_d), + .dout(pf1_hits_q) + ); + + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) pf1_rpt_pe_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pf1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[pf1_rpt_pe_offset:pf1_rpt_pe_offset + 2 - 1]), + .scout(sov[pf1_rpt_pe_offset:pf1_rpt_pe_offset + 2 - 1]), + .din(ex8_rpt_pe_q), + .dout(pf1_rpt_pe_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) latch_pf1_thrd( + .nclk(nclk), + .act(pf1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(siv[pf1_thrd_offset:pf1_thrd_offset + `THREADS - 1]), + .scout(sov[pf1_thrd_offset:pf1_thrd_offset + `THREADS - 1]), + .din(pf1_thrd_d), + .dout(pf1_thrd_q) + ); + + + tri_rlmreg_p #(.WIDTH(1), .INIT(0)) latch_pf1_same_cline( + .nclk(nclk), + .act(pf1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(siv[pf1_same_cline_offset:pf1_same_cline_offset]), + .scout(sov[pf1_same_cline_offset:pf1_same_cline_offset]), + .din(same_cline), + .dout(pf1_same_cline_q) + ); + + + tri_rlmreg_p #(.WIDTH(1), .INIT(0)) latch_pf1_stride_too_small( + .nclk(nclk), + .act(pf1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(siv[pf1_stride_too_small_offset:pf1_stride_too_small_offset]), + .scout(sov[pf1_stride_too_small_offset:pf1_stride_too_small_offset]), + .din(stride_too_small), + .dout(pf1_stride_too_small_q) + ); + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // Stride Compare + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + + assign stride_match = pf1_new_stride_q == pf1_rpt_stride_q; + + + + assign generate_pfetch = (~(pf1_pf_state_q == 2'b11)) & // state 0, 1, or 2 + (stride_match | (pf1_burst_cnt_q == 2'b11 & pf1_pf_state_q == 2'b00)) & // stride correct or burst count is 3 + (~(pf1_hits_q[0:1] == 2'b00)) & // not for a new RPT entry + (~pf1_stride_too_small_q); + + assign nxt_state_cntrl = {stride_match, pf1_pf_state_q}; + + assign pf1_update_state = ((nxt_state_cntrl) == 3'b100) ? 2'b00 : // state is 01 for new entry + ((nxt_state_cntrl) == 3'b101) ? 2'b00 : + ((nxt_state_cntrl) == 3'b110) ? 2'b00 : + ((nxt_state_cntrl) == 3'b111) ? 2'b10 : + ((nxt_state_cntrl) == 3'b000) ? 2'b01 : + ((nxt_state_cntrl) == 3'b001) ? 2'b10 : + ((nxt_state_cntrl) == 3'b010) ? 2'b11 : + 2'b11; + + assign pf2_next_state_d = (pf1_hits_q[0:1] == 2'b00) ? 2'b01 : + pf1_update_state; + + assign pf2_next_stride_d = (((~stride_match) & (~(pf1_pf_state_q == 2'b00))) == 1'b1) ? pf1_new_stride_q : + pf1_rpt_stride_q; + + assign burst_cnt_inc = (pf1_burst_cnt_q == 2'b00) ? 2'b01 : + (pf1_burst_cnt_q == 2'b01) ? 2'b10 : + 2'b11; + + assign pf2_burst_cnt_d = ((pf1_pf_state_q == 2'b01 & stride_match) == 1'b1) ? burst_cnt_inc : + ((pf1_pf_state_q == 2'b01 & (~stride_match)) == 1'b1) ? 2'b00 : + pf1_burst_cnt_q; + + assign pf2_data_ea_d = pf1_data_ea_q; + + + tri_rlmreg_p #(.WIDTH(1), .INIT(0)) latch_pf2_gen_pfetch( + .nclk(nclk), + .act(pf2_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(siv[pf2_gen_pfetch_offset:pf2_gen_pfetch_offset]), + .scout(sov[pf2_gen_pfetch_offset:pf2_gen_pfetch_offset]), + .din(generate_pfetch), + .dout(pf2_gen_pfetch_q) + ); + + + tri_rlmreg_p #(.WIDTH(22), .INIT(0)) latch_pf2_rpt_stride( + .nclk(nclk), + .act(pf2_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(siv[pf2_rpt_stride_offset:pf2_rpt_stride_offset + 22 - 1]), + .scout(sov[pf2_rpt_stride_offset:pf2_rpt_stride_offset + 22 - 1]), + .din(pf2_next_stride_d), + .dout(pf2_stride_q) + ); + + + tri_rlmreg_p #(.WIDTH((59-(64-(2**`GPR_WIDTH_ENC))+1)), .INIT(0)) latch_pf2_data_ea( + .nclk(nclk), + .act(pf2_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(siv[pf2_data_ea_offset:pf2_data_ea_offset + (59-(64-(2**`GPR_WIDTH_ENC))+1) - 1]), + .scout(sov[pf2_data_ea_offset:pf2_data_ea_offset + (59-(64-(2**`GPR_WIDTH_ENC))+1) - 1]), + .din(pf2_data_ea_d), + .dout(pf2_data_ea_q) + ); + + + tri_rlmreg_p #(.WIDTH(`PF_IFAR_WIDTH), .INIT(0)) latch_pf2_iar( + .nclk(nclk), + .act(pf2_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(siv[pf2_iar_offset:pf2_iar_offset + `PF_IFAR_WIDTH - 1]), + .scout(sov[pf2_iar_offset:pf2_iar_offset + `PF_IFAR_WIDTH - 1]), + .din(pf1_iar_q), + .dout(pf2_iar_q) + ); + + + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) latch_pf2_pf_state( + .nclk(nclk), + .act(pf2_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(siv[pf2_pf_state_offset:pf2_pf_state_offset + 2 - 1]), + .scout(sov[pf2_pf_state_offset:pf2_pf_state_offset + 2 - 1]), + .din(pf2_next_state_d), + .dout(pf2_pf_state_q) + ); + + + tri_rlmreg_p #(.WIDTH(2), .INIT(0)) latch_pf2_burst_cnt( + .nclk(nclk), + .act(pf2_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(siv[pf2_burst_cnt_offset:pf2_burst_cnt_offset + 2 - 1]), + .scout(sov[pf2_burst_cnt_offset:pf2_burst_cnt_offset + 2 - 1]), + .din(pf2_burst_cnt_d), + .dout(pf2_burst_cnt_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) latch_pf2_hits( + .nclk(nclk), + .act(pf2_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(siv[pf2_hits_offset:pf2_hits_offset + 3 - 1]), + .scout(sov[pf2_hits_offset:pf2_hits_offset + 3 - 1]), + .din(pf1_hits_q), + .dout(pf2_hits_q) + ); + + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) pf2_rpt_pe_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pf2_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[pf2_rpt_pe_offset:pf2_rpt_pe_offset + 2 - 1]), + .scout(sov[pf2_rpt_pe_offset:pf2_rpt_pe_offset + 2 - 1]), + .din(pf1_rpt_pe_q), + .dout(pf2_rpt_pe_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) latch_pf2_thrd( + .nclk(nclk), + .act(pf2_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(siv[pf2_thrd_offset:pf2_thrd_offset + `THREADS - 1]), + .scout(sov[pf2_thrd_offset:pf2_thrd_offset + `THREADS - 1]), + .din(pf1_thrd_q), + .dout(pf2_thrd_q) + ); + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // RPT update + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + + assign pf2_valid = pf2_req_val_4pf_q; + + assign rpt_data_in[0] = ~|(pf2_rpt_pe_q); // valid bit + assign rpt_data_in[1:22] = pf2_data_ea_q[38:59]; // last data address + assign rpt_data_in[23:44] = pf2_stride_q; // stride + assign rpt_data_in[45:51] = pf2_iar_q[50:56]; // iar tag + assign rpt_data_in[52:53] = pf2_pf_state_q; // prefetch state + assign rpt_data_in[54:55] = pf2_burst_cnt_q; // burst counter + assign rpt_data_in[56] = pf2_gen_pfetch_q; // duplicate flag + assign rpt_data_in[57:57 + `THREADS - 1] = pf2_thrd_q; // thread id + + assign rpt_data_in[57 + `THREADS] = ^({rpt_data_in[0:7], inj_pfetch_parity_q}); + assign rpt_data_in[58 + `THREADS] = ^(rpt_data_in[8:15]); + assign rpt_data_in[59 + `THREADS] = ^(rpt_data_in[16:23]); + assign rpt_data_in[60 + `THREADS] = ^(rpt_data_in[24:31]); + assign rpt_data_in[61 + `THREADS] = ^(rpt_data_in[32:39]); + assign rpt_data_in[62 + `THREADS] = ^(rpt_data_in[40:47]); + assign rpt_data_in[63 + `THREADS] = ^(rpt_data_in[48:55]); + assign rpt_data_in[64 + `THREADS] = ^(rpt_data_in[56:57 + `THREADS - 1]); + + assign rpt_data_in[65 + `THREADS:69] = 0; // unused + + assign rpt_wrt_addr = pf2_iar_q[57:61]; + + + always @(*) + begin: old_lru_proc + reg lru; + + //(* analysis_not_referenced="true" *) + + integer i; + lru = 1'b0; + for (i = 0; i <= 31; i = i + 1) + lru = (rpt_lru_q[i] & (pf2_iar_q[57:61] == i[4:0])) | lru; + + old_rpt_lru = lru; + end + + assign new_rpt_lru = (pf2_hits_q[0:1] == 2'b01) ? 1'b0 : + (pf2_hits_q[0:1] == 2'b10) ? 1'b1 : + (~old_rpt_lru); + + generate + begin : xhdl6 + genvar i; + for (i = 0; i <= 31; i = i + 1) + begin : rpt_lru_gen + wire [0:4] iDummy=i; + assign rpt_lru_d[i] = ((pf2_iar_q[57:61] == iDummy)) ? new_rpt_lru : + rpt_lru_q[i]; + end + end + endgenerate + + assign rpt_wen[0:1] = |(pf2_rpt_pe_q) ? pf2_rpt_pe_q : + ((pf2_valid & (~new_rpt_lru)) == 1'b1) ? 2'b01 : + ((pf2_valid & new_rpt_lru) == 1'b1) ? 2'b10 : + 2'b00; + + + tri_rlmreg_p #(.WIDTH(32), .INIT(0)) latch_rpt_lru( + .nclk(nclk), + .act(pf2_valid), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(siv[rpt_lru_offset:rpt_lru_offset + 32 - 1]), + .scout(sov[rpt_lru_offset:rpt_lru_offset + 32 - 1]), + .din(rpt_lru_d), + .dout(rpt_lru_q) + ); + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // Create new prefetches based current load request and store into queue + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + + // latch new EA, stride, and dup flag in to prefetch queue + + assign pfq_wrt_ptr_plus1 = pfq_wrt_ptr_q + value1[32-`PFETCH_Q_SIZE_ENC:31]; + + assign pfq_full_d = (((pfq_wrt_ptr_plus1 == pfq_rd_ptr_q) & pfq_wrt_val) | (pfq_full_q & (~(pfq_wrt_ptr_plus1 == pfq_rd_ptr_q)))) & + ~ctl_pf_clear_queue; + + assign pfq_wrt_val = (generate_pfetch & (~(pf1_dup_flag_q & pf1_same_cline_q))) & (~pfq_full_q) & (~pf1_disable); + + assign pfq_wrt_ptr_d = (ctl_pf_clear_queue == 1'b1) ? {`PFETCH_Q_SIZE_ENC{1'b0}} : + (pfq_wrt_val == 1'b1) ? pfq_wrt_ptr_plus1 : + pfq_wrt_ptr_q; + + assign pf1_new_data_ea = pf1_data_ea_q + ({ {59-21-1-(64-(2**`GPR_WIDTH_ENC))+1{pf1_rpt_stride_q[0]}}, pf1_rpt_stride_q }); + + generate + begin : xhdl7 + genvar i; + for (i = 0; i <= `PFETCH_Q_SIZE - 1; i = i + 1) + begin : pfq_gen + wire [0:`PFETCH_Q_SIZE_ENC-1] iDummy=i; + assign pfq_wen[i] = pfq_wrt_val & (pfq_wrt_ptr_q == iDummy); + + assign pfq_stride_d[i] = (pfq_wen[i] == 1'b1) ? pf1_rpt_stride_q : + pfq_stride_q[i]; + + assign pfq_data_ea_d[i] = (pfq_wen[i] == 1'b1) ? pf1_new_data_ea : + pfq_data_ea_q[i]; + + assign pfq_dup_flag_d[i] = (pfq_wen[i] == 1'b1) ? pf1_dup_flag_q : + pfq_dup_flag_q[i]; + + assign pfq_thrd_d[i] = (ctl_pf_clear_queue == 1'b1) ? {`THREADS{1'b0}}: + (pfq_wen[i] == 1'b1) ? pf1_thrd_q : + (pf_done & (pfq_rd_ptr_q == iDummy)) ? {`THREADS{1'b0}}: + pfq_thrd_q[i]; + + assign pfq_dscr_d[i] = (pfq_wen[i] == 1'b1) ? pf1_dscr[61:63] : + pfq_dscr_q[i]; + + + tri_rlmreg_p #(.WIDTH(22), .INIT(0), .NEEDS_SRESET(1)) pfq_stride_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pf2_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[pfq_stride_offset + 22 * i:pfq_stride_offset + 22 * (i + 1) - 1]), + .scout(sov[pfq_stride_offset + 22 * i:pfq_stride_offset + 22 * (i + 1) - 1]), + .din(pfq_stride_d[i]), + .dout(pfq_stride_q[i]) + ); + + + tri_rlmreg_p #(.WIDTH((59-(64-(2**`GPR_WIDTH_ENC))+1)), .INIT(0), .NEEDS_SRESET(1)) pfq_data_ea_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pf2_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[pfq_data_ea_offset + (59-(64-(2**`GPR_WIDTH_ENC))+1) * i:pfq_data_ea_offset + (59-(64-(2**`GPR_WIDTH_ENC))+1) * (i + 1) - 1]), + .scout(sov[pfq_data_ea_offset + (59-(64-(2**`GPR_WIDTH_ENC))+1) * i:pfq_data_ea_offset + (59-(64-(2**`GPR_WIDTH_ENC))+1) * (i + 1) - 1]), + .din(pfq_data_ea_d[i]), + .dout(pfq_data_ea_q[i]) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) pfq_thrd_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[pfq_thrd_offset + `THREADS * i:pfq_thrd_offset + `THREADS * (i + 1) - 1]), + .scout(sov[pfq_thrd_offset + `THREADS * i:pfq_thrd_offset + `THREADS * (i + 1) - 1]), + .din(pfq_thrd_d[i]), + .dout(pfq_thrd_q[i]) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) pfq_dscr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pf2_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[pfq_dscr_offset + 3 * i:pfq_dscr_offset + 3 * (i + 1) - 1]), + .scout(sov[pfq_dscr_offset + 3 * i:pfq_dscr_offset + 3 * (i + 1) - 1]), + .din(pfq_dscr_d[i]), + .dout(pfq_dscr_q[i]) + ); + end + end + endgenerate + + + tri_rlmreg_p #(.WIDTH(`PFETCH_Q_SIZE), .INIT(1)) latch_pfq_dup_flag( + .nclk(nclk), + .act(pf2_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(siv[pfq_dup_flag_offset:pfq_dup_flag_offset + `PFETCH_Q_SIZE - 1]), + .scout(sov[pfq_dup_flag_offset:pfq_dup_flag_offset + `PFETCH_Q_SIZE - 1]), + .din(pfq_dup_flag_d), + .dout(pfq_dup_flag_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pfq_full_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[pfq_full_offset]), + .scout(sov[pfq_full_offset]), + .din(pfq_full_d), + .dout(pfq_full_q) + ); + + + tri_rlmreg_p #(.WIDTH(`PFETCH_Q_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) pfq_wrt_ptr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[pfq_wrt_ptr_offset:pfq_wrt_ptr_offset + `PFETCH_Q_SIZE_ENC - 1]), + .scout(sov[pfq_wrt_ptr_offset:pfq_wrt_ptr_offset + `PFETCH_Q_SIZE_ENC - 1]), + .din(pfq_wrt_ptr_d), + .dout(pfq_wrt_ptr_q) + ); + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // State Machine to read the prefetch queue + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + + assign pf_rd_val = ((~(pfq_wrt_ptr_q == pfq_rd_ptr_q)) | pfq_full_q) & (~ctl_pf_clear_queue); + + assign pf_empty = ~(pfq_thrd_v) & + ~({`THREADS{ex6_req_val_4pf_q}} & ex6_thrd_q) & + ~({`THREADS{ex7_req_val_4pf_q}} & ex7_thrd_q) & + ~({`THREADS{ex8_req_val_4pf_q}} & ex8_thrd_q) & + ~({`THREADS{pf1_req_val_4pf_q}} & pf1_thrd_q) & + ~({`THREADS{pf2_req_val_4pf_q}} & pf2_thrd_q); + + assign pf_idle = pf_state_q[4]; + assign pf_gen = pf_state_q[0]; + assign pf_send = pf_state_q[1]; + assign pf_next = pf_state_q[2]; + assign pf_done = pf_state_q[3]; + + + always @(*) + begin: pf_state_mach + + pf_nxt_idle = 1'b0; + pf_nxt_gen = 1'b0; + pf_nxt_send = 1'b0; + pf_nxt_next = 1'b0; + pf_nxt_done = 1'b0; + + if (pf_idle == 1'b1) + begin + if (pf_rd_val == 1'b1) + pf_nxt_gen = 1'b1; + else + pf_nxt_idle = 1'b1; + end + + if (pf_gen == 1'b1) + begin + if (block_dup_pfetch == 1'b0) + pf_nxt_send = 1'b1; + else + pf_nxt_next = 1'b1; + end + + if (pf_send == 1'b1) + begin + if (dec_pf_ack == 1'b1) + pf_nxt_next = 1'b1; + else + pf_nxt_send = 1'b1; + end + + if (pf_next == 1'b1) + begin + if (pf_count_q == 3'b000) + pf_nxt_done = 1'b1; + else if (block_dup_pfetch == 1'b0) + pf_nxt_send = 1'b1; + else + pf_nxt_next = 1'b1; + end + + if (pf_done == 1'b1) + pf_nxt_idle = 1'b1; + + end + + assign pf_nxt_state[4] = pf_nxt_idle | ctl_pf_clear_queue; + assign pf_nxt_state[0] = pf_nxt_gen & (~ctl_pf_clear_queue); + assign pf_nxt_state[1] = pf_nxt_send & (~ctl_pf_clear_queue); + assign pf_nxt_state[2] = pf_nxt_next & (~ctl_pf_clear_queue); + assign pf_nxt_state[3] = pf_nxt_done & (~ctl_pf_clear_queue); + + + tri_rlmreg_p #(.WIDTH(5), .INIT(1)) latch_pf_state( + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(siv[pf_state_offset:pf_state_offset + 5 - 1]), + .scout(sov[pf_state_offset:pf_state_offset + 5 - 1]), + .din(pf_nxt_state), + .dout(pf_state_q) + ); + + // count the number of prefetches to issue + assign pf_count_d = (pf_gen == 1'b1) ? pfq_rd_dscr[61:63] - value2[29:31] : + (pf_next == 1'b1) ? pf_count_q - value1[29:31] : + pf_count_q; + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) latch_pf_count( + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(siv[pf_count_offset:pf_count_offset + 3 - 1]), + .scout(sov[pf_count_offset:pf_count_offset + 3 - 1]), + .din(pf_count_d), + .dout(pf_count_q) + ); + + // increment read pointer when prefetches for that entry are done + assign pfq_rd_ptr_d = (ctl_pf_clear_queue == 1'b1) ? {`PFETCH_Q_SIZE_ENC{1'b0}} : + (pf_done == 1'b1) ? pfq_rd_ptr_q + value1[32-`PFETCH_Q_SIZE_ENC:31] : + pfq_rd_ptr_q; + + + tri_rlmreg_p #(.WIDTH(`PFETCH_Q_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) pfq_rd_ptr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[pfq_rd_ptr_offset:pfq_rd_ptr_offset + `PFETCH_Q_SIZE_ENC - 1]), + .scout(sov[pfq_rd_ptr_offset:pfq_rd_ptr_offset + `PFETCH_Q_SIZE_ENC - 1]), + .din(pfq_rd_ptr_d), + .dout(pfq_rd_ptr_q) + ); + + // mux next address from prefetch queue + + always @(*) + begin: pfq_rd_data_proc + reg [0:21] rd_stride; + reg [64-(2**`GPR_WIDTH_ENC):59] rd_data_ea; + reg rd_dup_flag; + reg [0:`THREADS-1] rd_thrd; + reg [61:63] rd_dscr; + reg [0:`THREADS-1] thrd_v; + reg [0:31] i; + rd_stride = {22{1'b0}}; + rd_data_ea = {59-(64-(2**`GPR_WIDTH_ENC))+1{1'b0}}; + rd_dup_flag = 1'b0; + rd_thrd = {`THREADS{1'b0}}; + rd_dscr = {3{1'b0}}; + thrd_v = {`THREADS{1'b0}}; + for (i = 0; i <= `PFETCH_Q_SIZE - 1; i = i + 1) + begin + rd_stride = ( {22{(pfq_rd_ptr_q == i[32-`PFETCH_Q_SIZE_ENC:31])}} & pfq_stride_q[i]) | rd_stride; + rd_data_ea = ({59-(64-(2**`GPR_WIDTH_ENC))+1{(pfq_rd_ptr_q == i[32-`PFETCH_Q_SIZE_ENC:31])}} & pfq_data_ea_q[i]) | rd_data_ea; + rd_dup_flag = ( (pfq_rd_ptr_q == i[32-`PFETCH_Q_SIZE_ENC:31]) & pfq_dup_flag_q[i]) | rd_dup_flag; + rd_thrd = ( {`THREADS{(pfq_rd_ptr_q == i[32-`PFETCH_Q_SIZE_ENC:31])}} & pfq_thrd_q[i]) | rd_thrd; + rd_dscr = ( {3{pfq_rd_ptr_q == i[32-`PFETCH_Q_SIZE_ENC:31]}} & pfq_dscr_q[i]) | rd_dscr; + thrd_v = pfq_thrd_q[i] | thrd_v; + end + pf3_stride_d = rd_stride; + pfq_rd_data_ea = rd_data_ea; + pfq_rd_dup_flag = rd_dup_flag; + pfq_rd_thrd = rd_thrd; + pfq_rd_dscr = rd_dscr; + pfq_thrd_v = thrd_v; + end + + assign pf3_act = (~pf_idle); + + + tri_rlmreg_p #(.WIDTH(22), .INIT(0), .NEEDS_SRESET(1)) pf3_stride_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pf3_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[pf3_stride_offset:pf3_stride_offset + 22 - 1]), + .scout(sov[pf3_stride_offset:pf3_stride_offset + 22 - 1]), + .din(pf3_stride_d), + .dout(pf3_stride_q) + ); + + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + // Prefetch Generation + // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX + + assign block_dup_pfetch = (pfq_rd_dup_flag & (~(pf_count_d == 3'b000))); // after 1st set of N prefetches, only prefetch the last of N + + assign pf3_req_val_d = ((pf_gen | (pf_next & (~(pf_count_q == 3'b000)))) == 1'b1) ? pf_rd_val & (~block_dup_pfetch) : + ((pf_send & (~dec_pf_ack)) == 1'b1) ? pf3_req_val_q & (~ctl_pf_clear_queue) : + 1'b0; + + assign pf3_thrd_d = (pf_gen == 1'b1) ? pfq_rd_thrd : + pf3_thrd_q; + + assign pf3_req_addr_d = (pf_gen == 1'b1) ? pfq_rd_data_ea : + (pf_next == 1'b1) ? pf3_req_addr_q + ({ {59-21-1-(64-(2**`GPR_WIDTH_ENC))+1{pf3_stride_q[0]}}, pf3_stride_q }) : + pf3_req_addr_q; + + + tri_rlmreg_p #(.WIDTH((59-(64-(2**`GPR_WIDTH_ENC))+1)), .INIT(0)) latch_pf3_req_addr( + .nclk(nclk), + .act(pf3_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(siv[pf3_req_addr_offset:pf3_req_addr_offset + (59-(64-(2**`GPR_WIDTH_ENC))+1) - 1]), + .scout(sov[pf3_req_addr_offset:pf3_req_addr_offset + (59-(64-(2**`GPR_WIDTH_ENC))+1) - 1]), + .din(pf3_req_addr_d), + .dout(pf3_req_addr_q) + ); + + assign pf_dec_req_addr = pf3_req_addr_q[64 - (2 ** `GPR_WIDTH_ENC):63 - `CL_SIZE]; + + + tri_rlmreg_p #(.WIDTH(1), .INIT(0)) latch_pf3_req_val( + .nclk(nclk), + .act(pf3_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(siv[pf3_req_val_offset:pf3_req_val_offset]), + .scout(sov[pf3_req_val_offset:pf3_req_val_offset]), + .din(pf3_req_val_d), + .dout(pf3_req_val_q) + ); + + assign pf_dec_req_val = pf3_req_val_q & (~ctl_pf_clear_queue); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) latch_pf3_thrd( + .nclk(nclk), + .act(pf3_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .vd(vdd), + .gd(gnd), + .scin(siv[pf3_thrd_offset:pf3_thrd_offset + `THREADS - 1]), + .scout(sov[pf3_thrd_offset:pf3_thrd_offset + `THREADS - 1]), + .din(pf3_thrd_d), + .dout(pf3_thrd_q) + ); + + assign pf_dec_req_thrd = pf3_thrd_q; + + assign rpt_func_scan_in = scan_in; + assign siv[0:scan_right] = {sov[1:scan_right], rpt_func_scan_out}; + assign scan_out = sov[0]; + +endmodule diff --git a/dev/verilog/work/lq_spr.v b/dev/verilog/work/lq_spr.v new file mode 100755 index 0000000..f521fa6 --- /dev/null +++ b/dev/verilog/work/lq_spr.v @@ -0,0 +1,678 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" + +module lq_spr +#( + parameter hvmode = 1, + parameter a2mode = 1 +)( + + (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) + input [0:`NCLK_WIDTH-1] nclk, + + input d_mode_dc, + input delay_lclkr_dc, + input mpw1_dc_b, + input mpw2_dc_b, + + input ccfg_sl_force, + input ccfg_sl_thold_0_b, + input func_sl_force, + input func_sl_thold_0_b, + input func_nsl_force, + input func_nsl_thold_0_b, + input sg_0, + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + input scan_in, + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + output scan_out, + + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + input ccfg_scan_in, + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + output ccfg_scan_out, + + input [0:`THREADS-1] flush, + input [0:`THREADS-1] ex1_valid, + input ex3_data_val, + input [64-`GPR_WIDTH:63] ex3_eff_addr, + + // SlowSPR Interface + input slowspr_val_in, + input slowspr_rw_in, + input [0:1] slowspr_etid_in, + input [0:9] slowspr_addr_in, + input [64-`GPR_WIDTH:63] slowspr_data_in, + input slowspr_done_in, + + output slowspr_val_out, + output slowspr_rw_out, + output [0:1] slowspr_etid_out, + output [0:9] slowspr_addr_out, + output [64-`GPR_WIDTH:63] slowspr_data_out, + output slowspr_done_out, + + // DAC + input ex2_is_any_load_dac, + input ex2_is_any_store_dac, + + output spr_dcc_ex4_dvc1_en, + output spr_dcc_ex4_dvc2_en, + output spr_dcc_ex4_dacrw1_cmpr, + output spr_dcc_ex4_dacrw2_cmpr, + output spr_dcc_ex4_dacrw3_cmpr, + output spr_dcc_ex4_dacrw4_cmpr, + + // SPRs + input [0:`THREADS-1] spr_msr_pr, + input [0:`THREADS-1] spr_msr_gs, + input [0:`THREADS-1] spr_msr_ds, + input [0:2*`THREADS-1] spr_dbcr0_dac1, + input [0:2*`THREADS-1] spr_dbcr0_dac2, + input [0:2*`THREADS-1] spr_dbcr0_dac3, + input [0:2*`THREADS-1] spr_dbcr0_dac4, + + output spr_xudbg0_exec, + output [0:`THREADS-1] spr_xudbg0_tid, + input spr_xudbg0_done, + input spr_xudbg1_valid, + input [0:3] spr_xudbg1_watch, + input [0:3] spr_xudbg1_parity, + input [0:6] spr_xudbg1_lru, + input spr_xudbg1_lock, + input [33:63] spr_xudbg2_tag, + output [0:8*`THREADS-1] spr_dbcr2_dvc1be, + output [0:8*`THREADS-1] spr_dbcr2_dvc2be, + output [0:2*`THREADS-1] spr_dbcr2_dvc1m, + output [0:2*`THREADS-1] spr_dbcr2_dvc2m, + output [0:`THREADS-1] spr_epsc_wr, + output [0:`THREADS-1] spr_eplc_wr, + output [0:31] spr_pesr, + + output [0:`GPR_WIDTH-1] spr_dvc1, + output [0:`GPR_WIDTH-1] spr_dvc2, + output [0:5] spr_lesr1_muxseleb0, + output [0:5] spr_lesr1_muxseleb1, + output [0:5] spr_lesr1_muxseleb2, + output [0:5] spr_lesr1_muxseleb3, + output [0:5] spr_lesr2_muxseleb4, + output [0:5] spr_lesr2_muxseleb5, + output [0:5] spr_lesr2_muxseleb6, + output [0:5] spr_lesr2_muxseleb7, + output [0:2] spr_lsucr0_lca, + output [0:2] spr_lsucr0_sca, + output spr_lsucr0_lge, + output spr_lsucr0_b2b, + output spr_lsucr0_dfwd, + output spr_lsucr0_clchk, + output spr_lsucr0_ford, + output [0:7] spr_xucr2_rmt3, + output [0:7] spr_xucr2_rmt2, + output [0:7] spr_xucr2_rmt1, + output [0:7] spr_xucr2_rmt0, + output [0:2] spr_xudbg0_way, + output [0:5] spr_xudbg0_row, + output [0:32*`THREADS-1] spr_acop_ct, + output [0:`THREADS-1] spr_dbcr3_ivc, + output [0:`THREADS-1] spr_dscr_lsd, + output [0:`THREADS-1] spr_dscr_snse, + output [0:`THREADS-1] spr_dscr_sse, + output [0:3*`THREADS-1] spr_dscr_dpfd, + output [0:`THREADS-1] spr_eplc_epr, + output [0:`THREADS-1] spr_eplc_eas, + output [0:`THREADS-1] spr_eplc_egs, + output [0:8*`THREADS-1] spr_eplc_elpid, + output [0:14*`THREADS-1] spr_eplc_epid, + output [0:`THREADS-1] spr_epsc_epr, + output [0:`THREADS-1] spr_epsc_eas, + output [0:`THREADS-1] spr_epsc_egs, + output [0:8*`THREADS-1] spr_epsc_elpid, + output [0:14*`THREADS-1] spr_epsc_epid, + output [0:32*`THREADS-1] spr_hacop_ct, + + // Power + inout vdd, + inout gnd +); + + +localparam tiup = 1'b1; +wire slowspr_val_in_q; // input=>slowspr_val_in ,act=>tiup ,scan=>Y ,sleep=>N, ring=>func +wire slowspr_rw_in_q; // input=>slowspr_rw_in ,act=>slowspr_act_in ,scan=>Y ,sleep=>N, ring=>func +wire [0:1] slowspr_etid_in_q; // input=>slowspr_etid_in ,act=>slowspr_act_in ,scan=>Y ,sleep=>N, ring=>func +wire [0:9] slowspr_addr_in_q; // input=>slowspr_addr_in ,act=>slowspr_act_in ,scan=>Y ,sleep=>N, ring=>func +wire [64-`GPR_WIDTH:63] slowspr_data_in_q; // input=>slowspr_data_in ,act=>slowspr_act_in ,scan=>Y ,sleep=>N, ring=>func +wire slowspr_done_in_q; // input=>slowspr_done_in ,act=>tiup ,scan=>Y ,sleep=>N, ring=>func +wire slowspr_val_out_q; // input=>slowspr_val_in_q ,act=>tiup ,scan=>Y ,sleep=>N, ring=>func +wire slowspr_rw_out_q; // input=>slowspr_rw_in_q ,act=>slowspr_val_in_q ,scan=>Y ,sleep=>N, ring=>func +wire [0:1] slowspr_etid_out_q; // input=>slowspr_etid_in_q ,act=>slowspr_val_in_q ,scan=>Y ,sleep=>N, ring=>func +wire [0:9] slowspr_addr_out_q; // input=>slowspr_addr_in_q ,act=>slowspr_val_in_q ,scan=>Y ,sleep=>N, ring=>func +wire [64-`GPR_WIDTH:63] slowspr_data_out_q; // input=>slowspr_data_out_d ,act=>slowspr_val_in_q ,scan=>Y ,sleep=>N, ring=>func +wire [64-`GPR_WIDTH:63] slowspr_data_out_d; +wire slowspr_done_out_q; // input=>slowspr_done_out_d ,act=>tiup ,scan=>Y ,sleep=>N, ring=>func +wire slowspr_done_out_d; +wire [0:`THREADS-1] flush_q; // input=>flush ,act=>tiup ,scan=>Y ,sleep=>N, ring=>func + +// Scanchain +parameter slowspr_val_in_offset = `THREADS + 1; +parameter slowspr_rw_in_offset = slowspr_val_in_offset + 1; +parameter slowspr_etid_in_offset = slowspr_rw_in_offset + 1; +parameter slowspr_addr_in_offset = slowspr_etid_in_offset + 2; +parameter slowspr_data_in_offset = slowspr_addr_in_offset + 10; +parameter slowspr_done_in_offset = slowspr_data_in_offset + `GPR_WIDTH; +parameter slowspr_val_out_offset = slowspr_done_in_offset + 1; +parameter slowspr_rw_out_offset = slowspr_val_out_offset + 1; +parameter slowspr_etid_out_offset = slowspr_rw_out_offset + 1; +parameter slowspr_addr_out_offset = slowspr_etid_out_offset + 2; +parameter slowspr_data_out_offset = slowspr_addr_out_offset + 10; +parameter slowspr_done_out_offset = slowspr_data_out_offset + `GPR_WIDTH; +parameter flush_offset = slowspr_done_out_offset + 1; +parameter scan_right = flush_offset + `THREADS; +wire [0:scan_right-1] siv; +wire [0:scan_right-1] sov; +// Signals +wire slowspr_act_in; +wire [0:`THREADS-1] slowspr_val_tid; +wire [0:3] slowspr_tid; +wire [0:3] slowspr_tid_in; +wire [0:2*`THREADS-1] tspr_cspr_dbcr2_dac1us; +wire [0:2*`THREADS-1] tspr_cspr_dbcr2_dac1er; +wire [0:2*`THREADS-1] tspr_cspr_dbcr2_dac2us; +wire [0:2*`THREADS-1] tspr_cspr_dbcr2_dac2er; +wire [0:2*`THREADS-1] tspr_cspr_dbcr3_dac3us; +wire [0:2*`THREADS-1] tspr_cspr_dbcr3_dac3er; +wire [0:2*`THREADS-1] tspr_cspr_dbcr3_dac4us; +wire [0:2*`THREADS-1] tspr_cspr_dbcr3_dac4er; +wire [0:`THREADS-1] tspr_cspr_dbcr2_dac12m; +wire [0:`THREADS-1] tspr_cspr_dbcr3_dac34m; +wire [0:2*`THREADS-1] tspr_cspr_dbcr2_dvc1m; +wire [0:2*`THREADS-1] tspr_cspr_dbcr2_dvc2m; +wire [0:8*`THREADS-1] tspr_cspr_dbcr2_dvc1be; +wire [0:8*`THREADS-1] tspr_cspr_dbcr2_dvc2be; +wire [0:`THREADS-1] tspr_done; +wire [0:`THREADS-1] tspr_sel; +wire [0:`GPR_WIDTH-1] tspr_rt[0:`THREADS-1]; +wire cspr_done; +wire [64-`GPR_WIDTH:63] cspr_rt; +wire [0:`THREADS-1] cspr_tspr_msr_pr; +wire [0:`THREADS-1] cspr_tspr_msr_gs; +wire slowspr_val_in_gate; +wire slowspr_val_in_stg; +reg [0:`GPR_WIDTH-1] tspr_tid_mux; + +assign slowspr_tid = (slowspr_etid_in_q == 2'b00) ? 4'b1000 : + (slowspr_etid_in_q == 2'b01) ? 4'b0100 : + (slowspr_etid_in_q == 2'b10) ? 4'b0010 : + (slowspr_etid_in_q == 2'b11) ? 4'b0001 : + 4'b0000; + +assign slowspr_tid_in = (slowspr_etid_in == 2'b00) ? 4'b1000 : + (slowspr_etid_in == 2'b01) ? 4'b0100 : + (slowspr_etid_in == 2'b10) ? 4'b0010 : + (slowspr_etid_in == 2'b11) ? 4'b0001 : + 4'b0000; + +assign slowspr_val_tid = slowspr_tid[0:`THREADS-1] & {`THREADS{slowspr_val_in_q}}; +assign tspr_sel = tspr_done & slowspr_val_tid; +assign slowspr_val_in_gate = slowspr_val_in & ~(|(slowspr_tid_in[0:`THREADS - 1] & flush_q)); +assign slowspr_val_in_stg = slowspr_val_in_q & ~(|(slowspr_tid[0:`THREADS - 1] & flush_q)); +assign slowspr_act_in = slowspr_val_in; +assign slowspr_val_out = slowspr_val_out_q; +assign slowspr_rw_out = slowspr_rw_out_q; +assign slowspr_etid_out = slowspr_etid_out_q; +assign slowspr_addr_out = slowspr_addr_out_q; +assign slowspr_data_out = slowspr_data_out_q; +assign slowspr_done_out = slowspr_done_out_q; +assign spr_xudbg0_tid = slowspr_tid[0:`THREADS-1]; + +always @* begin : tsprMux + reg [0:`GPR_WIDTH-1] tspr; + integer tid; + tspr = {`GPR_WIDTH{1'b0}}; + for (tid=0; tid<`THREADS; tid=tid+1) begin + tspr = (tspr_rt[tid] & {`GPR_WIDTH{tspr_sel[tid]}}) | tspr; + end + tspr_tid_mux = tspr; +end + +assign slowspr_done_out_d = slowspr_done_in_q | |(tspr_done) | cspr_done; +assign slowspr_data_out_d = slowspr_data_in_q | tspr_tid_mux | (cspr_rt & {`GPR_WIDTH{cspr_done}}); + +assign spr_dbcr2_dvc1be = tspr_cspr_dbcr2_dvc1be; +assign spr_dbcr2_dvc2be = tspr_cspr_dbcr2_dvc2be; +assign spr_dbcr2_dvc1m = tspr_cspr_dbcr2_dvc1m; +assign spr_dbcr2_dvc2m = tspr_cspr_dbcr2_dvc2m; + +lq_spr_cspr #(.hvmode(hvmode), .a2mode(a2mode)) lq_spr_cspr( + .nclk(nclk), + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .ccfg_sl_force(ccfg_sl_force), + .ccfg_sl_thold_0_b(ccfg_sl_thold_0_b), + .func_sl_force(func_sl_force), + .func_sl_thold_0_b(func_sl_thold_0_b), + .func_nsl_force(func_nsl_force), + .func_nsl_thold_0_b(func_nsl_thold_0_b), + .sg_0(sg_0), + .scan_in(siv[`THREADS]), + .scan_out(sov[`THREADS]), + .ccfg_scan_in(ccfg_scan_in), + .ccfg_scan_out(ccfg_scan_out), + + .flush(flush_q), + .ex1_valid(ex1_valid), + .ex3_data_val(ex3_data_val), + .ex3_eff_addr(ex3_eff_addr), + // SlowSPR Interface + .slowspr_val_in(slowspr_val_in_q), + .slowspr_rw_in(slowspr_rw_in_q), + .slowspr_addr_in(slowspr_addr_in_q), + .slowspr_data_in(slowspr_data_in_q), + .cspr_done(cspr_done), + .cspr_rt(cspr_rt), + // DAC + .ex2_is_any_load_dac(ex2_is_any_load_dac), + .ex2_is_any_store_dac(ex2_is_any_store_dac), + .spr_dcc_ex4_dvc1_en(spr_dcc_ex4_dvc1_en), + .spr_dcc_ex4_dvc2_en(spr_dcc_ex4_dvc2_en), + .spr_dcc_ex4_dacrw1_cmpr(spr_dcc_ex4_dacrw1_cmpr), + .spr_dcc_ex4_dacrw2_cmpr(spr_dcc_ex4_dacrw2_cmpr), + .spr_dcc_ex4_dacrw3_cmpr(spr_dcc_ex4_dacrw3_cmpr), + .spr_dcc_ex4_dacrw4_cmpr(spr_dcc_ex4_dacrw4_cmpr), + + // SPRs + .spr_msr_pr(spr_msr_pr), + .spr_msr_gs(spr_msr_gs), + .spr_msr_ds(spr_msr_ds), + .spr_dbcr0_dac1(spr_dbcr0_dac1), + .spr_dbcr0_dac2(spr_dbcr0_dac2), + .spr_dbcr0_dac3(spr_dbcr0_dac3), + .spr_dbcr0_dac4(spr_dbcr0_dac4), + .spr_xudbg0_exec(spr_xudbg0_exec), + .spr_xudbg0_done(spr_xudbg0_done), + .spr_xudbg1_valid(spr_xudbg1_valid), + .spr_xudbg1_watch(spr_xudbg1_watch), + .spr_xudbg1_parity(spr_xudbg1_parity), + .spr_xudbg1_lru(spr_xudbg1_lru), + .spr_xudbg1_lock(spr_xudbg1_lock), + .spr_xudbg2_tag(spr_xudbg2_tag), + .spr_pesr(spr_pesr), + .cspr_tspr_msr_pr(cspr_tspr_msr_pr), + .cspr_tspr_msr_gs(cspr_tspr_msr_gs), + .tspr_cspr_dbcr2_dac1us(tspr_cspr_dbcr2_dac1us), + .tspr_cspr_dbcr2_dac1er(tspr_cspr_dbcr2_dac1er), + .tspr_cspr_dbcr2_dac2us(tspr_cspr_dbcr2_dac2us), + .tspr_cspr_dbcr2_dac2er(tspr_cspr_dbcr2_dac2er), + .tspr_cspr_dbcr3_dac3us(tspr_cspr_dbcr3_dac3us), + .tspr_cspr_dbcr3_dac3er(tspr_cspr_dbcr3_dac3er), + .tspr_cspr_dbcr3_dac4us(tspr_cspr_dbcr3_dac4us), + .tspr_cspr_dbcr3_dac4er(tspr_cspr_dbcr3_dac4er), + .tspr_cspr_dbcr2_dac12m(tspr_cspr_dbcr2_dac12m), + .tspr_cspr_dbcr3_dac34m(tspr_cspr_dbcr3_dac34m), + .tspr_cspr_dbcr2_dvc1m(tspr_cspr_dbcr2_dvc1m), + .tspr_cspr_dbcr2_dvc2m(tspr_cspr_dbcr2_dvc2m), + .tspr_cspr_dbcr2_dvc1be(tspr_cspr_dbcr2_dvc1be), + .tspr_cspr_dbcr2_dvc2be(tspr_cspr_dbcr2_dvc2be), + + .spr_dvc1(spr_dvc1), + .spr_dvc2(spr_dvc2), + .spr_lesr1_muxseleb0(spr_lesr1_muxseleb0), + .spr_lesr1_muxseleb1(spr_lesr1_muxseleb1), + .spr_lesr1_muxseleb2(spr_lesr1_muxseleb2), + .spr_lesr1_muxseleb3(spr_lesr1_muxseleb3), + .spr_lesr2_muxseleb4(spr_lesr2_muxseleb4), + .spr_lesr2_muxseleb5(spr_lesr2_muxseleb5), + .spr_lesr2_muxseleb6(spr_lesr2_muxseleb6), + .spr_lesr2_muxseleb7(spr_lesr2_muxseleb7), + .spr_lsucr0_lca(spr_lsucr0_lca), + .spr_lsucr0_sca(spr_lsucr0_sca), + .spr_lsucr0_lge(spr_lsucr0_lge), + .spr_lsucr0_b2b(spr_lsucr0_b2b), + .spr_lsucr0_dfwd(spr_lsucr0_dfwd), + .spr_lsucr0_clchk(spr_lsucr0_clchk), + .spr_lsucr0_ford(spr_lsucr0_ford), + .spr_xucr2_rmt3(spr_xucr2_rmt3), + .spr_xucr2_rmt2(spr_xucr2_rmt2), + .spr_xucr2_rmt1(spr_xucr2_rmt1), + .spr_xucr2_rmt0(spr_xucr2_rmt0), + .spr_xudbg0_way(spr_xudbg0_way), + .spr_xudbg0_row(spr_xudbg0_row), + // Power + .vdd(vdd), + .gnd(gnd) +); + +generate begin : thread + genvar t; + for (t=0; t<`THREADS; t=t+1) begin : thread + lq_spr_tspr #(.hvmode(hvmode), .a2mode(a2mode)) lq_spr_tspr( + .nclk(nclk), + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .func_sl_force(func_sl_force), + .func_sl_thold_0_b(func_sl_thold_0_b), + .sg_0(sg_0), + .scan_in(siv[t]), + .scan_out(sov[t]), + // SlowSPR Interface + .slowspr_val_in(slowspr_val_tid[t]), + .slowspr_rw_in(slowspr_rw_in_q), + .slowspr_addr_in(slowspr_addr_in_q), + .slowspr_data_in(slowspr_data_in_q), + .tspr_done(tspr_done[t]), + .tspr_rt(tspr_rt[t]), + // SPRs + .cspr_tspr_msr_pr(cspr_tspr_msr_pr[t]), + .cspr_tspr_msr_gs(cspr_tspr_msr_gs[t]), + .tspr_cspr_dbcr2_dac1us(tspr_cspr_dbcr2_dac1us[t*2:2*(t+1)-1]), + .tspr_cspr_dbcr2_dac1er(tspr_cspr_dbcr2_dac1er[t*2:2*(t+1)-1]), + .tspr_cspr_dbcr2_dac2us(tspr_cspr_dbcr2_dac2us[t*2:2*(t+1)-1]), + .tspr_cspr_dbcr2_dac2er(tspr_cspr_dbcr2_dac2er[t*2:2*(t+1)-1]), + .tspr_cspr_dbcr3_dac3us(tspr_cspr_dbcr3_dac3us[t*2:2*(t+1)-1]), + .tspr_cspr_dbcr3_dac3er(tspr_cspr_dbcr3_dac3er[t*2:2*(t+1)-1]), + .tspr_cspr_dbcr3_dac4us(tspr_cspr_dbcr3_dac4us[t*2:2*(t+1)-1]), + .tspr_cspr_dbcr3_dac4er(tspr_cspr_dbcr3_dac4er[t*2:2*(t+1)-1]), + .tspr_cspr_dbcr2_dac12m(tspr_cspr_dbcr2_dac12m[t]), + .tspr_cspr_dbcr3_dac34m(tspr_cspr_dbcr3_dac34m[t]), + .tspr_cspr_dbcr2_dvc1m(tspr_cspr_dbcr2_dvc1m[t*2:2*(t+1)-1]), + .tspr_cspr_dbcr2_dvc2m(tspr_cspr_dbcr2_dvc2m[t*2:2*(t+1)-1]), + .tspr_cspr_dbcr2_dvc1be(tspr_cspr_dbcr2_dvc1be[t*8:8*(t+1)-1]), + .tspr_cspr_dbcr2_dvc2be(tspr_cspr_dbcr2_dvc2be[t*8:8*(t+1)-1]), + .spr_epsc_wr(spr_epsc_wr[t]), + .spr_eplc_wr(spr_eplc_wr[t]), + .spr_acop_ct(spr_acop_ct[32*t : 32*(t+1)-1]), + .spr_dbcr3_ivc(spr_dbcr3_ivc[t]), + .spr_dscr_lsd(spr_dscr_lsd[t]), + .spr_dscr_snse(spr_dscr_snse[t]), + .spr_dscr_sse(spr_dscr_sse[t]), + .spr_dscr_dpfd(spr_dscr_dpfd[3*t : 3*(t+1)-1]), + .spr_eplc_epr(spr_eplc_epr[t]), + .spr_eplc_eas(spr_eplc_eas[t]), + .spr_eplc_egs(spr_eplc_egs[t]), + .spr_eplc_elpid(spr_eplc_elpid[8*t : 8*(t+1)-1]), + .spr_eplc_epid(spr_eplc_epid[14*t : 14*(t+1)-1]), + .spr_epsc_epr(spr_epsc_epr[t]), + .spr_epsc_eas(spr_epsc_eas[t]), + .spr_epsc_egs(spr_epsc_egs[t]), + .spr_epsc_elpid(spr_epsc_elpid[8*t : 8*(t+1)-1]), + .spr_epsc_epid(spr_epsc_epid[14*t : 14*(t+1)-1]), + .spr_hacop_ct(spr_hacop_ct[32*t : 32*(t+1)-1]), + // Power + .vdd(vdd), + .gnd(gnd) + ); + end + end +endgenerate + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) slowspr_val_in_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[slowspr_val_in_offset]), + .scout(sov[slowspr_val_in_offset]), + .din(slowspr_val_in_gate), + .dout(slowspr_val_in_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) slowspr_rw_in_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(slowspr_act_in), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[slowspr_rw_in_offset]), + .scout(sov[slowspr_rw_in_offset]), + .din(slowspr_rw_in), + .dout(slowspr_rw_in_q) +); + +tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) slowspr_etid_in_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(slowspr_act_in), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[slowspr_etid_in_offset:slowspr_etid_in_offset + 2 - 1]), + .scout(sov[slowspr_etid_in_offset:slowspr_etid_in_offset + 2 - 1]), + .din(slowspr_etid_in), + .dout(slowspr_etid_in_q) +); + +tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) slowspr_addr_in_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(slowspr_act_in), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[slowspr_addr_in_offset:slowspr_addr_in_offset + 10 - 1]), + .scout(sov[slowspr_addr_in_offset:slowspr_addr_in_offset + 10 - 1]), + .din(slowspr_addr_in), + .dout(slowspr_addr_in_q) +); + +tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) slowspr_data_in_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(slowspr_act_in), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[slowspr_data_in_offset:slowspr_data_in_offset + `GPR_WIDTH - 1]), + .scout(sov[slowspr_data_in_offset:slowspr_data_in_offset + `GPR_WIDTH - 1]), + .din(slowspr_data_in), + .dout(slowspr_data_in_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) slowspr_done_in_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[slowspr_done_in_offset]), + .scout(sov[slowspr_done_in_offset]), + .din(slowspr_done_in), + .dout(slowspr_done_in_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) slowspr_val_out_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[slowspr_val_out_offset]), + .scout(sov[slowspr_val_out_offset]), + .din(slowspr_val_in_stg), + .dout(slowspr_val_out_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) slowspr_rw_out_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(slowspr_val_in_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[slowspr_rw_out_offset]), + .scout(sov[slowspr_rw_out_offset]), + .din(slowspr_rw_in_q), + .dout(slowspr_rw_out_q) +); + +tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) slowspr_etid_out_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(slowspr_val_in_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[slowspr_etid_out_offset:slowspr_etid_out_offset + 2 - 1]), + .scout(sov[slowspr_etid_out_offset:slowspr_etid_out_offset + 2 - 1]), + .din(slowspr_etid_in_q), + .dout(slowspr_etid_out_q) +); + +tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) slowspr_addr_out_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(slowspr_val_in_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[slowspr_addr_out_offset:slowspr_addr_out_offset + 10 - 1]), + .scout(sov[slowspr_addr_out_offset:slowspr_addr_out_offset + 10 - 1]), + .din(slowspr_addr_in_q), + .dout(slowspr_addr_out_q) +); + +tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) slowspr_data_out_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(slowspr_val_in_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[slowspr_data_out_offset:slowspr_data_out_offset + `GPR_WIDTH - 1]), + .scout(sov[slowspr_data_out_offset:slowspr_data_out_offset + `GPR_WIDTH - 1]), + .din(slowspr_data_out_d), + .dout(slowspr_data_out_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) slowspr_done_out_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[slowspr_done_out_offset]), + .scout(sov[slowspr_done_out_offset]), + .din(slowspr_done_out_d), + .dout(slowspr_done_out_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) flush_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[flush_offset:flush_offset + `THREADS - 1]), + .scout(sov[flush_offset:flush_offset + `THREADS - 1]), + .din(flush), + .dout(flush_q) +); + +assign siv[0:scan_right - 1] = {sov[1:scan_right - 1], scan_in}; +assign scan_out = sov[0]; + +endmodule diff --git a/dev/verilog/work/lq_spr_cspr.v b/dev/verilog/work/lq_spr_cspr.v new file mode 100755 index 0000000..fed26d2 --- /dev/null +++ b/dev/verilog/work/lq_spr_cspr.v @@ -0,0 +1,1497 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" + +module lq_spr_cspr +#( + parameter hvmode = 1, + parameter a2mode = 1 +)( + + (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) + input [0:`NCLK_WIDTH-1] nclk, + + input d_mode_dc, + input delay_lclkr_dc, + input mpw1_dc_b, + input mpw2_dc_b, + + input ccfg_sl_force, + input ccfg_sl_thold_0_b, + input func_sl_force, + input func_sl_thold_0_b, + input func_nsl_force, + input func_nsl_thold_0_b, + input sg_0, + + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + input scan_in, + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + output scan_out, + + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + input ccfg_scan_in, + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + output ccfg_scan_out, + + input [0:`THREADS-1] ex1_valid, + input [0:`THREADS-1] flush, + + // SlowSPR Interface + input slowspr_val_in, + input slowspr_rw_in, + input [0:9] slowspr_addr_in, + input [64-`GPR_WIDTH:63] slowspr_data_in, + + output cspr_done, + output [64-`GPR_WIDTH:63] cspr_rt, + + input ex3_data_val, + input [64-`GPR_WIDTH:63] ex3_eff_addr, + + // DAC + input ex2_is_any_load_dac, + input ex2_is_any_store_dac, + + output spr_dcc_ex4_dvc1_en, + output spr_dcc_ex4_dvc2_en, + output spr_dcc_ex4_dacrw1_cmpr, + output spr_dcc_ex4_dacrw2_cmpr, + output spr_dcc_ex4_dacrw3_cmpr, + output spr_dcc_ex4_dacrw4_cmpr, + + // SPRs + input [0:`THREADS-1] spr_msr_pr, + input [0:`THREADS-1] spr_msr_gs, + input [0:`THREADS-1] spr_msr_ds, + + input [0:2*`THREADS-1] spr_dbcr0_dac1, + input [0:2*`THREADS-1] spr_dbcr0_dac2, + input [0:2*`THREADS-1] spr_dbcr0_dac3, + input [0:2*`THREADS-1] spr_dbcr0_dac4, + + output [0:`THREADS-1] cspr_tspr_msr_pr, + output [0:`THREADS-1] cspr_tspr_msr_gs, + + input [0:2*`THREADS-1] tspr_cspr_dbcr2_dac1us, + input [0:2*`THREADS-1] tspr_cspr_dbcr2_dac1er, + input [0:2*`THREADS-1] tspr_cspr_dbcr2_dac2us, + input [0:2*`THREADS-1] tspr_cspr_dbcr2_dac2er, + input [0:2*`THREADS-1] tspr_cspr_dbcr3_dac3us, + input [0:2*`THREADS-1] tspr_cspr_dbcr3_dac3er, + input [0:2*`THREADS-1] tspr_cspr_dbcr3_dac4us, + input [0:2*`THREADS-1] tspr_cspr_dbcr3_dac4er, + + input [0:`THREADS-1] tspr_cspr_dbcr2_dac12m, + input [0:`THREADS-1] tspr_cspr_dbcr3_dac34m, + input [0:2*`THREADS-1] tspr_cspr_dbcr2_dvc1m, + input [0:2*`THREADS-1] tspr_cspr_dbcr2_dvc2m, + input [0:8*`THREADS-1] tspr_cspr_dbcr2_dvc1be, + input [0:8*`THREADS-1] tspr_cspr_dbcr2_dvc2be, + + output spr_xudbg0_exec, + input spr_xudbg0_done, + input spr_xudbg1_valid, + input [0:3] spr_xudbg1_watch, + input [0:3] spr_xudbg1_parity, + input [0:6] spr_xudbg1_lru, + input spr_xudbg1_lock, + input [33:63] spr_xudbg2_tag, + output [0:31] spr_pesr, + + output [0:`GPR_WIDTH-1] spr_dvc1, + output [0:`GPR_WIDTH-1] spr_dvc2, + output [0:5] spr_lesr1_muxseleb0, + output [0:5] spr_lesr1_muxseleb1, + output [0:5] spr_lesr1_muxseleb2, + output [0:5] spr_lesr1_muxseleb3, + output [0:5] spr_lesr2_muxseleb4, + output [0:5] spr_lesr2_muxseleb5, + output [0:5] spr_lesr2_muxseleb6, + output [0:5] spr_lesr2_muxseleb7, + output [0:2] spr_lsucr0_lca, + output [0:2] spr_lsucr0_sca, + output spr_lsucr0_lge, + output spr_lsucr0_b2b, + output spr_lsucr0_dfwd, + output spr_lsucr0_clchk, + output spr_lsucr0_ford, + output [0:7] spr_xucr2_rmt3, + output [0:7] spr_xucr2_rmt2, + output [0:7] spr_xucr2_rmt1, + output [0:7] spr_xucr2_rmt0, + output [0:2] spr_xudbg0_way, + output [0:5] spr_xudbg0_row, + + inout vdd, + inout gnd +); + + +// SPR Registers + // SPR Registers + wire [64-(`GPR_WIDTH):63] dac1_d, dac1_q; + wire [64-(`GPR_WIDTH):63] dac2_d, dac2_q; + wire [64-(`GPR_WIDTH):63] dac3_d, dac3_q; + wire [64-(`GPR_WIDTH):63] dac4_d, dac4_q; + wire [64-(`GPR_WIDTH):63] dvc1_d, dvc1_q; + wire [64-(`GPR_WIDTH):63] dvc2_d, dvc2_q; + wire [40:63] lesr1_d, lesr1_q; + wire [40:63] lesr2_d, lesr2_q; + wire [53:63] lsucr0_d, lsucr0_q; + wire [32:63] pesr_d, pesr_q; + wire [32:63] xucr2_d, xucr2_q; + wire [55:63] xudbg0_d, xudbg0_q; +// FUNC Scanchain + localparam dac1_offset = 0; + localparam dac2_offset = dac1_offset + `GPR_WIDTH*a2mode; + localparam dac3_offset = dac2_offset + `GPR_WIDTH*a2mode; + localparam dac4_offset = dac3_offset + `GPR_WIDTH; + localparam dvc1_offset = dac4_offset + `GPR_WIDTH; + localparam dvc2_offset = dvc1_offset + `GPR_WIDTH*a2mode; + localparam lesr1_offset = dvc2_offset + `GPR_WIDTH*a2mode; + localparam lesr2_offset = lesr1_offset + 24; + localparam pesr_offset = lesr2_offset + 24; + localparam xucr2_offset = pesr_offset + 32; + localparam xudbg0_offset = xucr2_offset + 32; + localparam last_reg_offset = xudbg0_offset + 9; +// CCFG Scanchain + localparam lsucr0_offset_ccfg = 0; + localparam last_reg_offset_ccfg = lsucr0_offset_ccfg + 11; +// Latches +wire [2:3] exx_act_q; // input=>exx_act_d , act=>tiup , scan=>Y, sleep=>N, ring=>func +wire [2:3] exx_act_d; +wire [0:7] ex3_dac12m_q; // input=>ex3_dac12m_d , act=>exx_act(2) , scan=>N, sleep=>N, ring=>func +wire [0:7] ex3_dac12m_d; +wire [0:7] ex3_dac34m_q; // input=>ex3_dac34m_d , act=>exx_act(2) , scan=>N, sleep=>N, ring=>func +wire [0:7] ex3_dac34m_d; +wire ex3_is_any_load_dac_q; // input=>ex2_is_any_load_dac , act=>exx_act(2) , scan=>N, sleep=>N, ring=>func +wire ex3_is_any_store_dac_q; // input=>ex2_is_any_store_dac , act=>exx_act(2) , scan=>N, sleep=>N, ring=>func +wire [0:3] ex4_dacrw_cmpr_q; // input=>ex4_dacrw_cmpr_d , act=>exx_act(3) , scan=>Y, sleep=>N, ring=>func +wire [0:3] ex4_dacrw_cmpr_d; +wire [0:`THREADS-1] ex2_val_q; // input=>ex1_val , act=>tiup , scan=>Y, sleep=>N, ring=>func +wire [0:`THREADS-1] ex1_val; +wire [0:`THREADS-1] ex3_val_q; // input=>ex2_val , act=>tiup , scan=>Y, sleep=>N, ring=>func +wire [0:`THREADS-1] ex2_val; +wire [0:`THREADS-1] ex4_val_q; // input=>ex3_val , act=>tiup , scan=>Y, sleep=>N, ring=>func +wire [0:`THREADS-1] ex3_val; +wire [0:1] dbcr0_dac1_q[0:`THREADS-1]; // input=>spr_dbcr0_dac1 , act=>tiup , scan=>Y, sleep=>N, ring=>func +wire [0:1] dbcr0_dac2_q[0:`THREADS-1]; // input=>spr_dbcr0_dac2 , act=>tiup , scan=>Y, sleep=>N, ring=>func +wire [0:1] dbcr0_dac3_q[0:`THREADS-1]; // input=>spr_dbcr0_dac3 , act=>tiup , scan=>Y, sleep=>N, ring=>func +wire [0:1] dbcr0_dac4_q[0:`THREADS-1]; // input=>spr_dbcr0_dac4 , act=>tiup , scan=>Y, sleep=>N, ring=>func +wire [0:`THREADS-1] dbcr2_dvc1m_on_q; // input=>dbcr2_dvc1m_on_d , act=>tiup , scan=>Y, sleep=>N, ring=>func +wire [0:`THREADS-1] dbcr2_dvc1m_on_d; +wire [0:`THREADS-1] dbcr2_dvc2m_on_q; // input=>dbcr2_dvc2m_on_d , act=>tiup , scan=>Y, sleep=>N, ring=>func +wire [0:`THREADS-1] dbcr2_dvc2m_on_d; +wire [0:`THREADS-1] msr_ds_q; // input=>spr_msr_ds , act=>tiup , scan=>Y, sleep=>N, ring=>func +wire [0:`THREADS-1] msr_pr_q; // input=>spr_msr_pr , act=>tiup , scan=>Y, sleep=>N, ring=>func +wire [0:`THREADS-1] msr_gs_q; // input=>spr_msr_gs , act=>tiup , scan=>Y, sleep=>N, ring=>func +wire ex4_data_val_q; // input=>ex3_data_val , act=>tiup , scan=>Y, sleep=>N, ring=>func +wire dvc1_act_q; // input=>dvc1_act_d , act=>tiup , scan=>Y, sleep=>N, ring=>func +wire dvc1_act_d; +wire dvc2_act_q; // input=>dvc2_act_d , act=>tiup , scan=>Y, sleep=>N, ring=>func +wire dvc2_act_d; +wire xudbg0_inprog_q; // input=>xudbg0_inprog_d , act=>tiup , scan=>Y, sleep=>N, ring=>func +wire xudbg0_inprog_d; +wire xudbg0_done_d; +wire xudbg0_done_q; +// Scanchains +parameter exx_act_offset = last_reg_offset; +parameter ex3_dac12m_offset = exx_act_offset + 2; +parameter ex3_dac34m_offset = ex3_dac12m_offset + 8; +parameter ex3_is_any_load_dac_offset = ex3_dac34m_offset + 8; +parameter ex3_is_any_store_dac_offset = ex3_is_any_load_dac_offset + 1; +parameter ex4_dacrw_cmpr_offset = ex3_is_any_store_dac_offset + 1; +parameter ex2_val_offset = ex4_dacrw_cmpr_offset + 4; +parameter ex3_val_offset = ex2_val_offset + `THREADS; +parameter ex4_val_offset = ex3_val_offset + `THREADS; +parameter dbcr0_dac1_offset = ex4_val_offset + `THREADS; +parameter dbcr0_dac2_offset = dbcr0_dac1_offset + (`THREADS) * 2; +parameter dbcr0_dac3_offset = dbcr0_dac2_offset + (`THREADS) * 2; +parameter dbcr0_dac4_offset = dbcr0_dac3_offset + (`THREADS) * 2; +parameter dbcr2_dvc1m_on_offset = dbcr0_dac4_offset + (`THREADS) * 2; +parameter dbcr2_dvc2m_on_offset = dbcr2_dvc1m_on_offset + `THREADS; +parameter msr_ds_offset = dbcr2_dvc2m_on_offset + `THREADS; +parameter msr_pr_offset = msr_ds_offset + `THREADS; +parameter msr_gs_offset = msr_pr_offset + `THREADS; +parameter ex4_data_val_offset = msr_gs_offset + `THREADS; +parameter dvc1_act_offset = ex4_data_val_offset + 1; +parameter dvc2_act_offset = dvc1_act_offset + 1; +parameter xudbg0_inprog_offset = dvc2_act_offset + 1; +parameter xudbg0_done_offset = xudbg0_inprog_offset + 1; +parameter scan_right = xudbg0_done_offset + 1; + +wire [0:scan_right-1] siv; +wire [0:scan_right-1] sov; +parameter scan_right_ccfg = last_reg_offset_ccfg; +wire [0:scan_right_ccfg-1] siv_ccfg; +wire [0:scan_right_ccfg-1] sov_ccfg; +// Signals +wire tiup; +wire [0:63] tidn; +wire sspr_spr_we; +wire [11:20] sspr_instr; +wire sspr_is_mtspr; +wire [64-`GPR_WIDTH:63] sspr_spr_wd; +wire [64-`GPR_WIDTH:63] ex3_dac2_mask; +wire [64-`GPR_WIDTH:63] ex3_dac4_mask; +wire ex3_dac1_cmpr; +wire ex3_dac1_cmpr_sel; +wire ex3_dac2_cmpr; +wire ex3_dac2_cmpr_sel; +wire ex3_dac3_cmpr; +wire ex3_dac3_cmpr_sel; +wire ex3_dac4_cmpr; +wire ex3_dac4_cmpr_sel; +wire [0:`THREADS-1] ex3_dac1r_en; +wire [0:`THREADS-1] ex3_dac1w_en; +wire [0:`THREADS-1] ex3_dac2r_en; +wire [0:`THREADS-1] ex3_dac2w_en; +wire [0:`THREADS-1] ex3_dac3r_en; +wire [0:`THREADS-1] ex3_dac3w_en; +wire [0:`THREADS-1] ex3_dac4r_en; +wire [0:`THREADS-1] ex3_dac4w_en; +wire [0:`THREADS-1] ex3_dac1r_cmpr; +wire [0:`THREADS-1] ex3_dac1w_cmpr; +wire [0:`THREADS-1] ex3_dac2r_cmpr; +wire [0:`THREADS-1] ex3_dac2w_cmpr; +wire [0:`THREADS-1] ex3_dac3r_cmpr; +wire [0:`THREADS-1] ex3_dac3w_cmpr; +wire [0:`THREADS-1] ex3_dac4r_cmpr; +wire [0:`THREADS-1] ex3_dac4w_cmpr; +wire [1:3] exx_act; + +// Data + + wire [64-(`GPR_WIDTH):63] sspr_dac1_di; + wire [64-(`GPR_WIDTH):63] sspr_dac2_di; + wire [64-(`GPR_WIDTH):63] sspr_dac3_di; + wire [64-(`GPR_WIDTH):63] sspr_dac4_di; + wire [64-(`GPR_WIDTH):63] sspr_dvc1_di; + wire [64-(`GPR_WIDTH):63] sspr_dvc2_di; + wire [40:63] sspr_lesr1_di; + wire [40:63] sspr_lesr2_di; + wire [53:63] sspr_lsucr0_di; + wire [32:63] sspr_pesr_di; + wire [32:63] sspr_xucr2_di; + wire [55:63] sspr_xudbg0_di; + wire + sspr_dac1_rdec , sspr_dac2_rdec , sspr_dac3_rdec , sspr_dac4_rdec + , sspr_dvc1_rdec , sspr_dvc2_rdec , sspr_lesr1_rdec, sspr_lesr2_rdec + , sspr_lsucr0_rdec, sspr_pesr_rdec , sspr_xucr2_rdec, sspr_xudbg0_rdec + , sspr_xudbg1_rdec, sspr_xudbg2_rdec; + wire + sspr_dac1_re , sspr_dac2_re , sspr_dac3_re , sspr_dac4_re + , sspr_dvc1_re , sspr_dvc2_re , sspr_lesr1_re , sspr_lesr2_re + , sspr_lsucr0_re , sspr_pesr_re , sspr_xucr2_re , sspr_xudbg0_re + , sspr_xudbg1_re , sspr_xudbg2_re ; + wire + sspr_dac1_wdec , sspr_dac2_wdec , sspr_dac3_wdec , sspr_dac4_wdec + , sspr_dvc1_wdec , sspr_dvc2_wdec , sspr_lesr1_wdec, sspr_lesr2_wdec + , sspr_lsucr0_wdec, sspr_pesr_wdec , sspr_xucr2_wdec, sspr_xudbg0_wdec; + wire + sspr_dac1_we , sspr_dac2_we , sspr_dac3_we , sspr_dac4_we + , sspr_dvc1_we , sspr_dvc2_we , sspr_lesr1_we , sspr_lesr2_we + , sspr_lsucr0_we , sspr_pesr_we , sspr_xucr2_we , sspr_xudbg0_we ; + wire + dac1_act , dac2_act , dac3_act , dac4_act + , dvc1_act , dvc2_act , lesr1_act , lesr2_act + , lsucr0_act , pesr_act , xucr2_act , xudbg0_act + , xudbg1_act , xudbg2_act ; + wire [0:64] + dac1_do , dac2_do , dac3_do , dac4_do + , dvc1_do , dvc2_do , lesr1_do , lesr2_do + , lsucr0_do , pesr_do , xucr2_do , xudbg0_do + , xudbg1_do , xudbg2_do ; +wire [0:2*`THREADS-1] dbcr0_dac1_int; +wire [0:2*`THREADS-1] dbcr0_dac2_int; +wire [0:2*`THREADS-1] dbcr0_dac3_int; +wire [0:2*`THREADS-1] dbcr0_dac4_int; +wire [0:7] tspr_cspr_dbcr2_dvc1be_int[0:`THREADS-1]; +wire [0:7] tspr_cspr_dbcr2_dvc2be_int[0:`THREADS-1]; +wire [0:1] tspr_cspr_dbcr2_dvc1m_int[0:`THREADS-1]; +wire [0:1] tspr_cspr_dbcr2_dvc2m_int[0:`THREADS-1]; + +//!! Bugspray Include: lq_spr_cspr; + +assign tiup = 1'b1; +assign tidn = {64{1'b0}}; + +assign exx_act_d = exx_act[1:2]; + +assign exx_act[1] = |(ex1_valid); +assign exx_act[2] = exx_act_q[2]; +assign exx_act[3] = exx_act_q[3]; + +assign ex1_val = ex1_valid & (~flush); +assign ex2_val = ex2_val_q & (~flush); +assign ex3_val = ex3_val_q & (~flush); + +assign sspr_is_mtspr = (~slowspr_rw_in); +assign sspr_instr = {slowspr_addr_in[5:9], slowspr_addr_in[0:4]}; +assign sspr_spr_we = slowspr_val_in; +assign sspr_spr_wd = slowspr_data_in; + +// SPR Input Control +// DAC1 +assign dac1_act = sspr_dac1_we; +assign dac1_d = sspr_dac1_di; + +// DAC2 +assign dac2_act = sspr_dac2_we; +assign dac2_d = sspr_dac2_di; + +// DAC3 +assign dac3_act = sspr_dac3_we; +assign dac3_d = sspr_dac3_di; + +// DAC4 +assign dac4_act = sspr_dac4_we; +assign dac4_d = sspr_dac4_di; + +// DVC1 +assign dvc1_act = sspr_dvc1_we; +assign dvc1_act_d = sspr_dvc1_we; +assign dvc1_d = sspr_dvc1_di; + +// DVC2 +assign dvc2_act = sspr_dvc2_we; +assign dvc2_act_d = sspr_dvc2_we; +assign dvc2_d = sspr_dvc2_di; + +// LSUCR0 +assign lsucr0_act = sspr_lsucr0_we; +assign lsucr0_d = sspr_lsucr0_di; + +// PESR +assign pesr_act = sspr_pesr_we; +assign pesr_d = sspr_pesr_di; + +// XUCR2 +assign xucr2_act = sspr_xucr2_we; +assign xucr2_d = sspr_xucr2_di; + +// XUDBG0 +assign xudbg0_act = sspr_xudbg0_we & (~xudbg0_inprog_q); +assign xudbg0_d = sspr_xudbg0_di; + +wire [0:1] xudbg0_done_sel = {(sspr_xudbg0_we & (~xudbg0_inprog_q)), spr_xudbg0_done}; +assign xudbg0_done_d = (xudbg0_done_sel == 2'b00) ? xudbg0_done_q : + (xudbg0_done_sel == 2'b10) ? sspr_spr_wd[63] : + spr_xudbg0_done; + +assign spr_xudbg0_exec = sspr_xudbg0_we & sspr_spr_wd[62] & (~xudbg0_inprog_q); +assign xudbg0_inprog_d = (sspr_xudbg0_we & sspr_spr_wd[62]) | (xudbg0_inprog_q & (~spr_xudbg0_done)); + +// XUDBG0 +assign xudbg1_act = tiup; + +// XUDBG0 +assign xudbg2_act = tiup; + +// LESR1 +assign lesr1_act = sspr_lesr1_we; +assign lesr1_d = sspr_lesr1_di; + +// LESR2 +assign lesr2_act = sspr_lesr2_we; +assign lesr2_d = sspr_lesr2_di; + +// Compare Address Against DAC regs +assign ex3_dac12m_d = {8{|(tspr_cspr_dbcr2_dac12m & ex2_val_q)}}; +assign ex3_dac34m_d = {8{|(tspr_cspr_dbcr3_dac34m & ex2_val_q)}}; + +assign ex3_dac2_mask = dac2_q | {`GPR_WIDTH/8{~ex3_dac12m_q}}; +assign ex3_dac4_mask = dac4_q | {`GPR_WIDTH/8{~ex3_dac34m_q}}; + +assign ex3_dac1_cmpr = &((ex3_eff_addr ~^ dac1_q) | (~ex3_dac2_mask)); +assign ex3_dac2_cmpr = &((ex3_eff_addr ~^ dac2_q)); +assign ex3_dac3_cmpr = &((ex3_eff_addr ~^ dac3_q) | (~ex3_dac4_mask)); +assign ex3_dac4_cmpr = &((ex3_eff_addr ~^ dac4_q)); + +assign ex3_dac1_cmpr_sel = ex3_dac1_cmpr; +assign ex3_dac2_cmpr_sel = (ex3_dac12m_q[0] == 1'b0) ? ex3_dac2_cmpr : + ex3_dac1_cmpr; +assign ex3_dac3_cmpr_sel = ex3_dac3_cmpr; +assign ex3_dac4_cmpr_sel = (ex3_dac34m_q[0] == 1'b0) ? ex3_dac4_cmpr : + ex3_dac3_cmpr; + +// Determine if DAC is enabled for this thread +generate begin : sprTidOut + genvar tid; + for (tid=0; tid<`THREADS; tid=tid+1) begin : sprTidOut + assign dbcr0_dac1_int[tid*2:(tid*2)+1] = dbcr0_dac1_q[tid]; + assign dbcr0_dac2_int[tid*2:(tid*2)+1] = dbcr0_dac2_q[tid]; + assign dbcr0_dac3_int[tid*2:(tid*2)+1] = dbcr0_dac3_q[tid]; + assign dbcr0_dac4_int[tid*2:(tid*2)+1] = dbcr0_dac4_q[tid]; + assign tspr_cspr_dbcr2_dvc1be_int[tid] = tspr_cspr_dbcr2_dvc1be[tid*8:tid*8+7]; + assign tspr_cspr_dbcr2_dvc2be_int[tid] = tspr_cspr_dbcr2_dvc2be[tid*8:tid*8+7]; + assign tspr_cspr_dbcr2_dvc1m_int[tid] = tspr_cspr_dbcr2_dvc1m[tid*2:tid*2+1]; + assign tspr_cspr_dbcr2_dvc2m_int[tid] = tspr_cspr_dbcr2_dvc2m[tid*2:tid*2+1]; + end +end +endgenerate + +lq_spr_dacen lq_spr_dac1en( + .spr_msr_pr(msr_pr_q), + .spr_msr_ds(msr_ds_q), + .spr_dbcr0_dac(dbcr0_dac1_int), + .spr_dbcr_dac_us(tspr_cspr_dbcr2_dac1us), + .spr_dbcr_dac_er(tspr_cspr_dbcr2_dac1er), + .val(ex3_val_q), + .load(ex3_is_any_load_dac_q), + .store(ex3_is_any_store_dac_q), + .dacr_en(ex3_dac1r_en), + .dacw_en(ex3_dac1w_en) +); + + +lq_spr_dacen lq_spr_dac2en( + .spr_msr_pr(msr_pr_q), + .spr_msr_ds(msr_ds_q), + .spr_dbcr0_dac(dbcr0_dac2_int), + .spr_dbcr_dac_us(tspr_cspr_dbcr2_dac2us), + .spr_dbcr_dac_er(tspr_cspr_dbcr2_dac2er), + .val(ex3_val_q), + .load(ex3_is_any_load_dac_q), + .store(ex3_is_any_store_dac_q), + .dacr_en(ex3_dac2r_en), + .dacw_en(ex3_dac2w_en) +); + + +lq_spr_dacen lq_spr_dac3en( + .spr_msr_pr(msr_pr_q), + .spr_msr_ds(msr_ds_q), + .spr_dbcr0_dac(dbcr0_dac3_int), + .spr_dbcr_dac_us(tspr_cspr_dbcr3_dac3us), + .spr_dbcr_dac_er(tspr_cspr_dbcr3_dac3er), + .val(ex3_val_q), + .load(ex3_is_any_load_dac_q), + .store(ex3_is_any_store_dac_q), + .dacr_en(ex3_dac3r_en), + .dacw_en(ex3_dac3w_en) +); + + +lq_spr_dacen lq_spr_dac4en( + .spr_msr_pr(msr_pr_q), + .spr_msr_ds(msr_ds_q), + .spr_dbcr0_dac(dbcr0_dac4_int), + .spr_dbcr_dac_us(tspr_cspr_dbcr3_dac4us), + .spr_dbcr_dac_er(tspr_cspr_dbcr3_dac4er), + .val(ex3_val_q), + .load(ex3_is_any_load_dac_q), + .store(ex3_is_any_store_dac_q), + .dacr_en(ex3_dac4r_en), + .dacw_en(ex3_dac4w_en) +); + +generate begin : lq_spr_dvc_cmp + genvar t; + for (t = 0; t <= `THREADS - 1; t = t + 1) begin : lq_spr_dvc_cmp + assign dbcr2_dvc1m_on_d[t] = |(tspr_cspr_dbcr2_dvc1m_int[t]) & |(tspr_cspr_dbcr2_dvc1be_int[t][8 - `GPR_WIDTH/8:7]); + assign dbcr2_dvc2m_on_d[t] = |(tspr_cspr_dbcr2_dvc2m_int[t]) & |(tspr_cspr_dbcr2_dvc2be_int[t][8 - `GPR_WIDTH/8:7]); + end +end +endgenerate + +assign ex3_dac1r_cmpr = ex3_dac1r_en & {`THREADS{ex3_dac1_cmpr_sel}}; +assign ex3_dac2r_cmpr = ex3_dac2r_en & {`THREADS{ex3_dac2_cmpr_sel}}; +assign ex3_dac3r_cmpr = ex3_dac3r_en & {`THREADS{ex3_dac3_cmpr_sel}}; +assign ex3_dac4r_cmpr = ex3_dac4r_en & {`THREADS{ex3_dac4_cmpr_sel}}; + +assign ex3_dac1w_cmpr = ex3_dac1w_en & {`THREADS{ex3_dac1_cmpr_sel}}; +assign ex3_dac2w_cmpr = ex3_dac2w_en & {`THREADS{ex3_dac2_cmpr_sel}}; +assign ex3_dac3w_cmpr = ex3_dac3w_en & {`THREADS{ex3_dac3_cmpr_sel}}; +assign ex3_dac4w_cmpr = ex3_dac4w_en & {`THREADS{ex3_dac4_cmpr_sel}}; + +assign ex4_dacrw_cmpr_d[0] = |({ex3_dac1r_cmpr, ex3_dac1w_cmpr}); +assign ex4_dacrw_cmpr_d[1] = |({ex3_dac2r_cmpr, ex3_dac2w_cmpr}); +assign ex4_dacrw_cmpr_d[2] = |({ex3_dac3r_cmpr, ex3_dac3w_cmpr}); +assign ex4_dacrw_cmpr_d[3] = |({ex3_dac4r_cmpr, ex3_dac4w_cmpr}); + +assign spr_dcc_ex4_dvc1_en = |(ex4_val_q & dbcr2_dvc1m_on_q) & ex4_dacrw_cmpr_q[0] & ex4_data_val_q; +assign spr_dcc_ex4_dvc2_en = |(ex4_val_q & dbcr2_dvc2m_on_q) & ex4_dacrw_cmpr_q[1] & ex4_data_val_q; +assign spr_dcc_ex4_dacrw1_cmpr = |(ex4_val_q & (~dbcr2_dvc1m_on_q)) & ex4_dacrw_cmpr_q[0]; +assign spr_dcc_ex4_dacrw2_cmpr = |(ex4_val_q & (~dbcr2_dvc2m_on_q)) & ex4_dacrw_cmpr_q[1]; +assign spr_dcc_ex4_dacrw3_cmpr = |(ex4_val_q) & ex4_dacrw_cmpr_q[2]; +assign spr_dcc_ex4_dacrw4_cmpr = |(ex4_val_q) & ex4_dacrw_cmpr_q[3]; + +assign spr_pesr = pesr_q; + +generate + if (a2mode == 0 & hvmode == 0) begin : readmux_00 + assign cspr_rt = + (dac3_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_dac3_re }}) | + (dac4_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_dac4_re }}) | + (lesr1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_lesr1_re }}) | + (lesr2_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_lesr2_re }}) | + (lsucr0_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_lsucr0_re }}) | + (pesr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_pesr_re }}) | + (xucr2_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_xucr2_re }}) | + (xudbg0_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_xudbg0_re }}) | + (xudbg1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_xudbg1_re }}) | + (xudbg2_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_xudbg2_re }}); + end +endgenerate +generate + if (a2mode == 0 & hvmode == 1) begin : readmux_01 + assign cspr_rt = + (dac3_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_dac3_re }}) | + (dac4_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_dac4_re }}) | + (lesr1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_lesr1_re }}) | + (lesr2_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_lesr2_re }}) | + (lsucr0_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_lsucr0_re }}) | + (pesr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_pesr_re }}) | + (xucr2_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_xucr2_re }}) | + (xudbg0_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_xudbg0_re }}) | + (xudbg1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_xudbg1_re }}) | + (xudbg2_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_xudbg2_re }}); + end +endgenerate +generate + if (a2mode == 1 & hvmode == 0) begin : readmux_10 + assign cspr_rt = + (dac1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_dac1_re }}) | + (dac2_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_dac2_re }}) | + (dac3_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_dac3_re }}) | + (dac4_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_dac4_re }}) | + (dvc1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_dvc1_re }}) | + (dvc2_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_dvc2_re }}) | + (lesr1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_lesr1_re }}) | + (lesr2_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_lesr2_re }}) | + (lsucr0_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_lsucr0_re }}) | + (pesr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_pesr_re }}) | + (xucr2_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_xucr2_re }}) | + (xudbg0_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_xudbg0_re }}) | + (xudbg1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_xudbg1_re }}) | + (xudbg2_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_xudbg2_re }}); + end +endgenerate +generate + if (a2mode == 1 & hvmode == 1) begin : readmux_11 + assign cspr_rt = + (dac1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_dac1_re }}) | + (dac2_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_dac2_re }}) | + (dac3_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_dac3_re }}) | + (dac4_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_dac4_re }}) | + (dvc1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_dvc1_re }}) | + (dvc2_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_dvc2_re }}) | + (lesr1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_lesr1_re }}) | + (lesr2_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_lesr2_re }}) | + (lsucr0_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_lsucr0_re }}) | + (pesr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_pesr_re }}) | + (xucr2_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_xucr2_re }}) | + (xudbg0_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_xudbg0_re }}) | + (xudbg1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_xudbg1_re }}) | + (xudbg2_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_xudbg2_re }}); + end +endgenerate + + assign sspr_dac1_rdec = (sspr_instr[11:20] == 10'b1110001001); // 316 + assign sspr_dac2_rdec = (sspr_instr[11:20] == 10'b1110101001); // 317 + assign sspr_dac3_rdec = (sspr_instr[11:20] == 10'b1000111010); // 849 + assign sspr_dac4_rdec = (sspr_instr[11:20] == 10'b1001011010); // 850 + assign sspr_dvc1_rdec = (sspr_instr[11:20] == 10'b1111001001); // 318 + assign sspr_dvc2_rdec = (sspr_instr[11:20] == 10'b1111101001); // 319 + assign sspr_lesr1_rdec = (sspr_instr[11:20] == 10'b1100011100); // 920 + assign sspr_lesr2_rdec = (sspr_instr[11:20] == 10'b1100111100); // 921 + assign sspr_lsucr0_rdec = (sspr_instr[11:20] == 10'b1001111001); // 819 + assign sspr_pesr_rdec = (sspr_instr[11:20] == 10'b1110111011); // 893 + assign sspr_xucr2_rdec = (sspr_instr[11:20] == 10'b1100011111); // 1016 + assign sspr_xudbg0_rdec = (sspr_instr[11:20] == 10'b1010111011); // 885 + assign sspr_xudbg1_rdec = (sspr_instr[11:20] == 10'b1011011011); // 886 + assign sspr_xudbg2_rdec = (sspr_instr[11:20] == 10'b1011111011); // 887 + assign sspr_dac1_re = sspr_dac1_rdec; + assign sspr_dac2_re = sspr_dac2_rdec; + assign sspr_dac3_re = sspr_dac3_rdec; + assign sspr_dac4_re = sspr_dac4_rdec; + assign sspr_dvc1_re = sspr_dvc1_rdec; + assign sspr_dvc2_re = sspr_dvc2_rdec; + assign sspr_lesr1_re = sspr_lesr1_rdec; + assign sspr_lesr2_re = sspr_lesr2_rdec; + assign sspr_lsucr0_re = sspr_lsucr0_rdec; + assign sspr_pesr_re = sspr_pesr_rdec; + assign sspr_xucr2_re = sspr_xucr2_rdec; + assign sspr_xudbg0_re = sspr_xudbg0_rdec; + assign sspr_xudbg1_re = sspr_xudbg1_rdec; + assign sspr_xudbg2_re = sspr_xudbg2_rdec; + + assign sspr_dac1_wdec = sspr_dac1_rdec; + assign sspr_dac2_wdec = sspr_dac2_rdec; + assign sspr_dac3_wdec = sspr_dac3_rdec; + assign sspr_dac4_wdec = sspr_dac4_rdec; + assign sspr_dvc1_wdec = sspr_dvc1_rdec; + assign sspr_dvc2_wdec = sspr_dvc2_rdec; + assign sspr_lesr1_wdec = sspr_lesr1_rdec; + assign sspr_lesr2_wdec = sspr_lesr2_rdec; + assign sspr_lsucr0_wdec = sspr_lsucr0_rdec; + assign sspr_pesr_wdec = sspr_pesr_rdec; + assign sspr_xucr2_wdec = sspr_xucr2_rdec; + assign sspr_xudbg0_wdec = sspr_xudbg0_rdec; + assign sspr_dac1_we = sspr_spr_we & sspr_is_mtspr & sspr_dac1_wdec; + assign sspr_dac2_we = sspr_spr_we & sspr_is_mtspr & sspr_dac2_wdec; + assign sspr_dac3_we = sspr_spr_we & sspr_is_mtspr & sspr_dac3_wdec; + assign sspr_dac4_we = sspr_spr_we & sspr_is_mtspr & sspr_dac4_wdec; + assign sspr_dvc1_we = sspr_spr_we & sspr_is_mtspr & sspr_dvc1_wdec; + assign sspr_dvc2_we = sspr_spr_we & sspr_is_mtspr & sspr_dvc2_wdec; + assign sspr_lesr1_we = sspr_spr_we & sspr_is_mtspr & sspr_lesr1_wdec; + assign sspr_lesr2_we = sspr_spr_we & sspr_is_mtspr & sspr_lesr2_wdec; + assign sspr_lsucr0_we = sspr_spr_we & sspr_is_mtspr & sspr_lsucr0_wdec; + assign sspr_pesr_we = sspr_spr_we & sspr_is_mtspr & sspr_pesr_wdec; + assign sspr_xucr2_we = sspr_spr_we & sspr_is_mtspr & sspr_xucr2_wdec; + assign sspr_xudbg0_we = sspr_spr_we & sspr_is_mtspr & sspr_xudbg0_wdec; + +assign cspr_done = slowspr_val_in & ( + sspr_dac1_rdec | sspr_dac2_rdec | sspr_dac3_rdec + | sspr_dac4_rdec | sspr_dvc1_rdec | sspr_dvc2_rdec + | sspr_lesr1_rdec | sspr_lesr2_rdec | sspr_lsucr0_rdec + | sspr_pesr_rdec | sspr_xucr2_rdec | sspr_xudbg0_rdec + | sspr_xudbg1_rdec | sspr_xudbg2_rdec ); + + +assign cspr_tspr_msr_pr = msr_pr_q; +assign cspr_tspr_msr_gs = msr_gs_q; + + assign spr_dvc1 = dvc1_q[64-(`GPR_WIDTH):63]; + assign spr_dvc2 = dvc2_q[64-(`GPR_WIDTH):63]; + assign spr_lesr1_muxseleb0 = lesr1_q[40:45]; + assign spr_lesr1_muxseleb1 = lesr1_q[46:51]; + assign spr_lesr1_muxseleb2 = lesr1_q[52:57]; + assign spr_lesr1_muxseleb3 = lesr1_q[58:63]; + assign spr_lesr2_muxseleb4 = lesr2_q[40:45]; + assign spr_lesr2_muxseleb5 = lesr2_q[46:51]; + assign spr_lesr2_muxseleb6 = lesr2_q[52:57]; + assign spr_lesr2_muxseleb7 = lesr2_q[58:63]; + assign spr_lsucr0_lca = lsucr0_q[53:55]; + assign spr_lsucr0_sca = lsucr0_q[56:58]; + assign spr_lsucr0_lge = lsucr0_q[59]; + assign spr_lsucr0_b2b = lsucr0_q[60]; + assign spr_lsucr0_dfwd = lsucr0_q[61]; + assign spr_lsucr0_clchk = lsucr0_q[62]; + assign spr_lsucr0_ford = lsucr0_q[63]; + assign spr_xucr2_rmt3 = xucr2_q[32:39]; + assign spr_xucr2_rmt2 = xucr2_q[40:47]; + assign spr_xucr2_rmt1 = xucr2_q[48:55]; + assign spr_xucr2_rmt0 = xucr2_q[56:63]; + assign spr_xudbg0_way = xudbg0_q[55:57]; + assign spr_xudbg0_row = xudbg0_q[58:63]; + + // DAC1 + assign sspr_dac1_di = { sspr_spr_wd[64-(`GPR_WIDTH):63] }; //DAC1 + + assign dac1_do = { tidn[0:64-(`GPR_WIDTH)] , + dac1_q[64-(`GPR_WIDTH):63] }; //DAC1 + // DAC2 + assign sspr_dac2_di = { sspr_spr_wd[64-(`GPR_WIDTH):63] }; //DAC2 + + assign dac2_do = { tidn[0:64-(`GPR_WIDTH)] , + dac2_q[64-(`GPR_WIDTH):63] }; //DAC2 + // DAC3 + assign sspr_dac3_di = { sspr_spr_wd[64-(`GPR_WIDTH):63] }; //DAC3 + + assign dac3_do = { tidn[0:64-(`GPR_WIDTH)] , + dac3_q[64-(`GPR_WIDTH):63] }; //DAC3 + // DAC4 + assign sspr_dac4_di = { sspr_spr_wd[64-(`GPR_WIDTH):63] }; //DAC4 + + assign dac4_do = { tidn[0:64-(`GPR_WIDTH)] , + dac4_q[64-(`GPR_WIDTH):63] }; //DAC4 + // DVC1 + assign sspr_dvc1_di = { sspr_spr_wd[64-(`GPR_WIDTH):63] }; //DVC1 + + assign dvc1_do = { tidn[0:64-(`GPR_WIDTH)] , + dvc1_q[64-(`GPR_WIDTH):63] }; //DVC1 + // DVC2 + assign sspr_dvc2_di = { sspr_spr_wd[64-(`GPR_WIDTH):63] }; //DVC2 + + assign dvc2_do = { tidn[0:64-(`GPR_WIDTH)] , + dvc2_q[64-(`GPR_WIDTH):63] }; //DVC2 + // LESR1 + assign sspr_lesr1_di = { sspr_spr_wd[32:37] , //MUXSELEB0 + sspr_spr_wd[38:43] , //MUXSELEB1 + sspr_spr_wd[44:49] , //MUXSELEB2 + sspr_spr_wd[50:55] }; //MUXSELEB3 + + assign lesr1_do = { tidn[0:0] , + tidn[0:31] , ///// + lesr1_q[40:45] , //MUXSELEB0 + lesr1_q[46:51] , //MUXSELEB1 + lesr1_q[52:57] , //MUXSELEB2 + lesr1_q[58:63] , //MUXSELEB3 + tidn[56:63] }; ///// + // LESR2 + assign sspr_lesr2_di = { sspr_spr_wd[32:37] , //MUXSELEB4 + sspr_spr_wd[38:43] , //MUXSELEB5 + sspr_spr_wd[44:49] , //MUXSELEB6 + sspr_spr_wd[50:55] }; //MUXSELEB7 + + assign lesr2_do = { tidn[0:0] , + tidn[0:31] , ///// + lesr2_q[40:45] , //MUXSELEB4 + lesr2_q[46:51] , //MUXSELEB5 + lesr2_q[52:57] , //MUXSELEB6 + lesr2_q[58:63] , //MUXSELEB7 + tidn[56:63] }; ///// + // LSUCR0 + assign sspr_lsucr0_di = { sspr_spr_wd[49:51] , //LCA + sspr_spr_wd[53:55] , //SCA + sspr_spr_wd[59:59] , //LGE + sspr_spr_wd[60:60] , //B2B + sspr_spr_wd[61:61] , //DFWD + sspr_spr_wd[62:62] , //CLCHK + sspr_spr_wd[63:63] }; //FORD + + assign lsucr0_do = { tidn[0:0] , + tidn[0:31] , ///// + tidn[32:48] , ///// + lsucr0_q[53:55] , //LCA + tidn[52:52] , ///// + lsucr0_q[56:58] , //SCA + tidn[56:58] , ///// + lsucr0_q[59:59] , //LGE + lsucr0_q[60:60] , //B2B + lsucr0_q[61:61] , //DFWD + lsucr0_q[62:62] , //CLCHK + lsucr0_q[63:63] }; //FORD + // PESR + assign sspr_pesr_di = { sspr_spr_wd[32:35] , //MUXSELEB0 + sspr_spr_wd[36:39] , //MUXSELEB1 + sspr_spr_wd[40:43] , //MUXSELEB2 + sspr_spr_wd[44:47] , //MUXSELEB3 + sspr_spr_wd[48:51] , //MUXSELEB4 + sspr_spr_wd[52:55] , //MUXSELEB5 + sspr_spr_wd[56:59] , //MUXSELEB6 + sspr_spr_wd[60:63] }; //MUXSELEB7 + + assign pesr_do = { tidn[0:0] , + tidn[0:31] , ///// + pesr_q[32:35] , //MUXSELEB0 + pesr_q[36:39] , //MUXSELEB1 + pesr_q[40:43] , //MUXSELEB2 + pesr_q[44:47] , //MUXSELEB3 + pesr_q[48:51] , //MUXSELEB4 + pesr_q[52:55] , //MUXSELEB5 + pesr_q[56:59] , //MUXSELEB6 + pesr_q[60:63] }; //MUXSELEB7 + // XUCR2 + assign sspr_xucr2_di = { sspr_spr_wd[32:39] , //RMT3 + sspr_spr_wd[40:47] , //RMT2 + sspr_spr_wd[48:55] , //RMT1 + sspr_spr_wd[56:63] }; //RMT0 + + assign xucr2_do = { tidn[0:0] , + tidn[0:31] , ///// + xucr2_q[32:39] , //RMT3 + xucr2_q[40:47] , //RMT2 + xucr2_q[48:55] , //RMT1 + xucr2_q[56:63] }; //RMT0 + // XUDBG0 + assign sspr_xudbg0_di = { sspr_spr_wd[49:51] , //WAY + sspr_spr_wd[52:57] }; //ROW + + assign xudbg0_do = { tidn[0:0] , + tidn[0:31] , ///// + tidn[32:48] , ///// + xudbg0_q[55:57] , //WAY + xudbg0_q[58:63] , //ROW + tidn[58:61] , ///// + 1'b0 , //EXEC + xudbg0_done_q }; //DONE + // XUDBG1 + assign xudbg1_do = { tidn[0:0] , + tidn[0:31] , ///// + tidn[32:44] , ///// + spr_xudbg1_watch[0:3] , //WATCH + spr_xudbg1_lru[0:6] , //LRU + spr_xudbg1_parity[0:3] , //PARITY + tidn[60:61] , ///// + spr_xudbg1_lock , //LOCK + spr_xudbg1_valid }; //VALID + // XUDBG2 + assign xudbg2_do = { tidn[0:0] , + tidn[0:31] , ///// + tidn[32:32] , ///// + spr_xudbg2_tag[33:63] }; //TAG + + // Unused Signals + wire unused_do_bits = |{ + dac1_do[0:64-`GPR_WIDTH] + ,dac2_do[0:64-`GPR_WIDTH] + ,dac3_do[0:64-`GPR_WIDTH] + ,dac4_do[0:64-`GPR_WIDTH] + ,dvc1_do[0:64-`GPR_WIDTH] + ,dvc2_do[0:64-`GPR_WIDTH] + ,lesr1_do[0:64-`GPR_WIDTH] + ,lesr2_do[0:64-`GPR_WIDTH] + ,lsucr0_do[0:64-`GPR_WIDTH] + ,pesr_do[0:64-`GPR_WIDTH] + ,xucr2_do[0:64-`GPR_WIDTH] + ,xudbg0_do[0:64-`GPR_WIDTH] + ,xudbg1_do[0:64-`GPR_WIDTH] + ,xudbg2_do[0:64-`GPR_WIDTH] + }; + +generate + if (a2mode == 1) begin : dac1_latch_gen + tri_ser_rlmreg_p #(.WIDTH(`GPR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) dac1_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(dac1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b),.mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[dac1_offset:dac1_offset + `GPR_WIDTH - 1]), + .scout(sov[dac1_offset:dac1_offset + `GPR_WIDTH - 1]), + .din(dac1_d), + .dout(dac1_q) + ); + end + if (a2mode == 0) begin : dac1_latch_tie + assign dac1_q = {`GPR_WIDTH{1'b0}}; + end +endgenerate +generate + if (a2mode == 1) begin : dac2_latch_gen + tri_ser_rlmreg_p #(.WIDTH(`GPR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) dac2_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(dac2_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b),.mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[dac2_offset:dac2_offset + `GPR_WIDTH - 1]), + .scout(sov[dac2_offset:dac2_offset + `GPR_WIDTH - 1]), + .din(dac2_d), + .dout(dac2_q) + ); + end + if (a2mode == 0) begin : dac2_latch_tie + assign dac2_q = {`GPR_WIDTH{1'b0}}; + end +endgenerate + tri_ser_rlmreg_p #(.WIDTH(`GPR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) dac3_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(dac3_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b),.mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[dac3_offset:dac3_offset + `GPR_WIDTH - 1]), + .scout(sov[dac3_offset:dac3_offset + `GPR_WIDTH - 1]), + .din(dac3_d), + .dout(dac3_q) + ); + tri_ser_rlmreg_p #(.WIDTH(`GPR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) dac4_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(dac4_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b),.mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[dac4_offset:dac4_offset + `GPR_WIDTH - 1]), + .scout(sov[dac4_offset:dac4_offset + `GPR_WIDTH - 1]), + .din(dac4_d), + .dout(dac4_q) + ); +generate + if (a2mode == 1) begin : dvc1_latch_gen + tri_ser_rlmreg_p #(.WIDTH(`GPR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) dvc1_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(dvc1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b),.mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[dvc1_offset:dvc1_offset + `GPR_WIDTH - 1]), + .scout(sov[dvc1_offset:dvc1_offset + `GPR_WIDTH - 1]), + .din(dvc1_d), + .dout(dvc1_q) + ); + end + if (a2mode == 0) begin : dvc1_latch_tie + assign dvc1_q = {`GPR_WIDTH{1'b0}}; + end +endgenerate +generate + if (a2mode == 1) begin : dvc2_latch_gen + tri_ser_rlmreg_p #(.WIDTH(`GPR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) dvc2_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(dvc2_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b),.mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[dvc2_offset:dvc2_offset + `GPR_WIDTH - 1]), + .scout(sov[dvc2_offset:dvc2_offset + `GPR_WIDTH - 1]), + .din(dvc2_d), + .dout(dvc2_q) + ); + end + if (a2mode == 0) begin : dvc2_latch_tie + assign dvc2_q = {`GPR_WIDTH{1'b0}}; + end +endgenerate + tri_ser_rlmreg_p #(.WIDTH(24), .INIT(0), .NEEDS_SRESET(1)) lesr1_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(lesr1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b),.mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lesr1_offset:lesr1_offset + 24 - 1]), + .scout(sov[lesr1_offset:lesr1_offset + 24 - 1]), + .din(lesr1_d), + .dout(lesr1_q) + ); + tri_ser_rlmreg_p #(.WIDTH(24), .INIT(0), .NEEDS_SRESET(1)) lesr2_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(lesr2_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b),.mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lesr2_offset:lesr2_offset + 24 - 1]), + .scout(sov[lesr2_offset:lesr2_offset + 24 - 1]), + .din(lesr2_d), + .dout(lesr2_q) + ); + //wtf set dfwd=1 tri_ser_rlmreg_p #(.WIDTH(11), .INIT(1848), .NEEDS_SRESET(1)) lsucr0_latch( + tri_ser_rlmreg_p #(.WIDTH(11), .INIT(1852), .NEEDS_SRESET(1)) lsucr0_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(lsucr0_act), + .force_t(ccfg_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b),.mpw2_b(mpw2_dc_b), + .thold_b(ccfg_sl_thold_0_b), + .sg(sg_0), + .scin(siv_ccfg[lsucr0_offset_ccfg:lsucr0_offset_ccfg + 11 - 1]), + .scout(sov_ccfg[lsucr0_offset_ccfg:lsucr0_offset_ccfg + 11 - 1]), + .din(lsucr0_d), + .dout(lsucr0_q) + ); + tri_ser_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) pesr_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(pesr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b),.mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[pesr_offset:pesr_offset + 32 - 1]), + .scout(sov[pesr_offset:pesr_offset + 32 - 1]), + .din(pesr_d), + .dout(pesr_q) + ); + tri_ser_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) xucr2_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(xucr2_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b),.mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[xucr2_offset:xucr2_offset + 32 - 1]), + .scout(sov[xucr2_offset:xucr2_offset + 32 - 1]), + .din(xucr2_d), + .dout(xucr2_q) + ); + tri_ser_rlmreg_p #(.WIDTH(9), .INIT(0), .NEEDS_SRESET(1)) xudbg0_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(xudbg0_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b),.mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[xudbg0_offset:xudbg0_offset + 9 - 1]), + .scout(sov[xudbg0_offset:xudbg0_offset + 9 - 1]), + .din(xudbg0_d), + .dout(xudbg0_q) + ); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xudbg0_done_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[xudbg0_done_offset]), + .scout(sov[xudbg0_done_offset]), + .din(xudbg0_done_d), + .dout(xudbg0_done_q) +); + +// Latch Instances + +tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) exx_act_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[exx_act_offset:exx_act_offset + 2 - 1]), + .scout(sov[exx_act_offset:exx_act_offset + 2 - 1]), + .din(exx_act_d), + .dout(exx_act_q) +); + +tri_regk #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex3_dac12m_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(exx_act[2]), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_dac12m_offset:ex3_dac12m_offset + 8 - 1]), + .scout(sov[ex3_dac12m_offset:ex3_dac12m_offset + 8 - 1]), + .din(ex3_dac12m_d), + .dout(ex3_dac12m_q) +); + +tri_regk #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex3_dac34m_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(exx_act[2]), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_dac34m_offset:ex3_dac34m_offset + 8 - 1]), + .scout(sov[ex3_dac34m_offset:ex3_dac34m_offset + 8 - 1]), + .din(ex3_dac34m_d), + .dout(ex3_dac34m_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_is_any_load_dac_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(exx_act[2]), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_is_any_load_dac_offset]), + .scout(sov[ex3_is_any_load_dac_offset]), + .din(ex2_is_any_load_dac), + .dout(ex3_is_any_load_dac_q) +); + +tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_is_any_store_dac_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(exx_act[2]), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_is_any_store_dac_offset]), + .scout(sov[ex3_is_any_store_dac_offset]), + .din(ex2_is_any_store_dac), + .dout(ex3_is_any_store_dac_q) +); + +tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ex4_dacrw_cmpr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(exx_act[3]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_dacrw_cmpr_offset:ex4_dacrw_cmpr_offset + 4 - 1]), + .scout(sov[ex4_dacrw_cmpr_offset:ex4_dacrw_cmpr_offset + 4 - 1]), + .din(ex4_dacrw_cmpr_d), + .dout(ex4_dacrw_cmpr_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex2_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_val_offset:ex2_val_offset + `THREADS - 1]), + .scout(sov[ex2_val_offset:ex2_val_offset + `THREADS - 1]), + .din(ex1_val), + .dout(ex2_val_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex3_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_val_offset:ex3_val_offset + `THREADS - 1]), + .scout(sov[ex3_val_offset:ex3_val_offset + `THREADS - 1]), + .din(ex2_val), + .dout(ex3_val_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex4_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_val_offset:ex4_val_offset + `THREADS - 1]), + .scout(sov[ex4_val_offset:ex4_val_offset + `THREADS - 1]), + .din(ex3_val), + .dout(ex4_val_q) +); +generate begin : dbcr0_dac1 + genvar tid; + for (tid = 0; tid <= `THREADS - 1; tid = tid + 1) begin : dbcr0_dac1 + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) dbcr0_dac1_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[dbcr0_dac1_offset + 2 * tid:dbcr0_dac1_offset + 2 * (tid + 1) - 1]), + .scout(sov[dbcr0_dac1_offset + 2 * tid:dbcr0_dac1_offset + 2 * (tid + 1) - 1]), + .din(spr_dbcr0_dac1[tid*2:tid*2+1]), + .dout(dbcr0_dac1_q[tid]) + ); + end + end +endgenerate +generate begin : dbcr0_dac2 + genvar tid; + for (tid = 0; tid <= `THREADS - 1; tid = tid + 1) begin : dbcr0_dac2 + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) dbcr0_dac2_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[dbcr0_dac2_offset + 2 * tid:dbcr0_dac2_offset + 2 * (tid + 1) - 1]), + .scout(sov[dbcr0_dac2_offset + 2 * tid:dbcr0_dac2_offset + 2 * (tid + 1) - 1]), + .din(spr_dbcr0_dac2[tid*2:tid*2+1]), + .dout(dbcr0_dac2_q[tid]) + ); + end +end +endgenerate +generate begin : dbcr0_dac3 + genvar tid; + for (tid = 0; tid <= `THREADS - 1; tid = tid + 1) begin : dbcr0_dac3 + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) dbcr0_dac3_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[dbcr0_dac3_offset + 2 * tid:dbcr0_dac3_offset + 2 * (tid + 1) - 1]), + .scout(sov[dbcr0_dac3_offset + 2 * tid:dbcr0_dac3_offset + 2 * (tid + 1) - 1]), + .din(spr_dbcr0_dac3[tid*2:tid*2+1]), + .dout(dbcr0_dac3_q[tid]) + ); + end +end +endgenerate +generate begin : dbcr0_dac4 + genvar tid; + for (tid = 0; tid <= `THREADS - 1; tid = tid + 1) begin : dbcr0_dac4 + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) dbcr0_dac4_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[dbcr0_dac4_offset + 2 * tid:dbcr0_dac4_offset + 2 * (tid + 1) - 1]), + .scout(sov[dbcr0_dac4_offset + 2 * tid:dbcr0_dac4_offset + 2 * (tid + 1) - 1]), + .din(spr_dbcr0_dac4[tid*2:tid*2+1]), + .dout(dbcr0_dac4_q[tid]) + ); + end +end +endgenerate + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) dbcr2_dvc1m_on_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[dbcr2_dvc1m_on_offset:dbcr2_dvc1m_on_offset + `THREADS - 1]), + .scout(sov[dbcr2_dvc1m_on_offset:dbcr2_dvc1m_on_offset + `THREADS - 1]), + .din(dbcr2_dvc1m_on_d), + .dout(dbcr2_dvc1m_on_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) dbcr2_dvc2m_on_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[dbcr2_dvc2m_on_offset:dbcr2_dvc2m_on_offset + `THREADS - 1]), + .scout(sov[dbcr2_dvc2m_on_offset:dbcr2_dvc2m_on_offset + `THREADS - 1]), + .din(dbcr2_dvc2m_on_d), + .dout(dbcr2_dvc2m_on_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) msr_ds_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[msr_ds_offset:msr_ds_offset + `THREADS - 1]), + .scout(sov[msr_ds_offset:msr_ds_offset + `THREADS - 1]), + .din(spr_msr_ds), + .dout(msr_ds_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) msr_pr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[msr_pr_offset:msr_pr_offset + `THREADS - 1]), + .scout(sov[msr_pr_offset:msr_pr_offset + `THREADS - 1]), + .din(spr_msr_pr), + .dout(msr_pr_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) msr_gs_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[msr_gs_offset:msr_gs_offset + `THREADS - 1]), + .scout(sov[msr_gs_offset:msr_gs_offset + `THREADS - 1]), + .din(spr_msr_gs), + .dout(msr_gs_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_data_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_data_val_offset]), + .scout(sov[ex4_data_val_offset]), + .din(ex3_data_val), + .dout(ex4_data_val_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dvc1_act_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[dvc1_act_offset]), + .scout(sov[dvc1_act_offset]), + .din(dvc1_act_d), + .dout(dvc1_act_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dvc2_act_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[dvc2_act_offset]), + .scout(sov[dvc2_act_offset]), + .din(dvc2_act_d), + .dout(dvc2_act_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xudbg0_inprog_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[xudbg0_inprog_offset]), + .scout(sov[xudbg0_inprog_offset]), + .din(xudbg0_inprog_d), + .dout(xudbg0_inprog_q) +); + +assign siv[0:scan_right - 1] = {sov[1:scan_right - 1], scan_in}; +assign scan_out = sov[0]; + +assign siv_ccfg[0:scan_right_ccfg - 1] = {sov_ccfg[1:scan_right_ccfg - 1], ccfg_scan_in}; +assign ccfg_scan_out = sov_ccfg[0]; + +endmodule diff --git a/dev/verilog/work/lq_spr_dacen.v b/dev/verilog/work/lq_spr_dacen.v new file mode 100755 index 0000000..1ab747a --- /dev/null +++ b/dev/verilog/work/lq_spr_dacen.v @@ -0,0 +1,104 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +// Description: XU SPR - DAC Enable Component +// +//***************************************************************************** + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" + +module lq_spr_dacen( + spr_msr_pr, + spr_msr_ds, + spr_dbcr0_dac, + spr_dbcr_dac_us, + spr_dbcr_dac_er, + val, + load, + store, + dacr_en, + dacw_en +); + +//------------------------------------------------------------------- +// Generics +//------------------------------------------------------------------- +//parameter `THREADS = 4; + +input [0:`THREADS-1] spr_msr_pr; +input [0:`THREADS-1] spr_msr_ds; + +input [0:2*`THREADS-1] spr_dbcr0_dac; +input [0:2*`THREADS-1] spr_dbcr_dac_us; +input [0:2*`THREADS-1] spr_dbcr_dac_er; + +input [0:`THREADS-1] val; +input load; +input store; + +output [0:`THREADS-1] dacr_en; +output [0:`THREADS-1] dacw_en; + +// Signals +wire [0:1] spr_dbcr0_dac_tid[0:`THREADS-1]; +wire [0:1] spr_dbcr_dac_us_tid[0:`THREADS-1]; +wire [0:1] spr_dbcr_dac_er_tid[0:`THREADS-1]; +wire [0:`THREADS-1] dac_ld_en; +wire [0:`THREADS-1] dac_st_en; +wire [0:`THREADS-1] dac_us_en; +wire [0:`THREADS-1] dac_er_en; + +generate begin : sprTid + genvar tid; + for (tid=0; tid<`THREADS; tid=tid+1) begin : sprTid + assign spr_dbcr0_dac_tid[tid] = spr_dbcr0_dac[tid*2:tid*2+1]; + assign spr_dbcr_dac_us_tid[tid] = spr_dbcr_dac_us[tid*2:tid*2+1]; + assign spr_dbcr_dac_er_tid[tid] = spr_dbcr_dac_er[tid*2:tid*2+1]; + end +end +endgenerate + +generate begin : dacen_gen + genvar t; + for (t = 0; t <= `THREADS - 1; t = t + 1) begin : dacen_gen + assign dac_ld_en[t] = spr_dbcr0_dac_tid[t][0] & load; + assign dac_st_en[t] = spr_dbcr0_dac_tid[t][1] & store; + + assign dac_us_en[t] = ((~spr_dbcr_dac_us_tid[t][0]) & (~spr_dbcr_dac_us_tid[t][1])) | (spr_dbcr_dac_us_tid[t][0] & (spr_dbcr_dac_us_tid[t][1] ~^ spr_msr_pr[t])); + + assign dac_er_en[t] = ((~spr_dbcr_dac_er_tid[t][0]) & (~spr_dbcr_dac_er_tid[t][1])) | (spr_dbcr_dac_er_tid[t][0] & (spr_dbcr_dac_er_tid[t][1] ~^ spr_msr_ds[t])); + assign dacr_en[t] = val[t] & dac_ld_en[t] & dac_us_en[t] & dac_er_en[t]; + assign dacw_en[t] = val[t] & dac_st_en[t] & dac_us_en[t] & dac_er_en[t]; + end + end +endgenerate + +endmodule + diff --git a/dev/verilog/work/lq_spr_dvccmp.v b/dev/verilog/work/lq_spr_dvccmp.v new file mode 100755 index 0000000..620a898 --- /dev/null +++ b/dev/verilog/work/lq_spr_dvccmp.v @@ -0,0 +1,93 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: XU SPR - DVC compare component +// +//***************************************************************************** + +`include "tri_a2o.vh" + +module lq_spr_dvccmp( + en, + en00, + cmp, + dvcm, + dvcbe, + dvc_cmpr +); + +//------------------------------------------------------------------- +// Generics +//------------------------------------------------------------------- +parameter REGSIZE = 64; + +input en; +input en00; +input [8-(REGSIZE/8):7] cmp; +input [0:1] dvcm; +input [8-(REGSIZE/8):7] dvcbe; +output dvc_cmpr; + +// Signals +wire [8-(REGSIZE/8):7] cmp_mask_or; +wire [8-(REGSIZE/8):7] cmp_mask_and; +wire cmp_and; +wire cmp_or; +wire cmp_andor; + +assign cmp_mask_or = (cmp | (~dvcbe)) & {(REGSIZE/8){|(dvcbe)}}; +assign cmp_mask_and = (cmp & dvcbe); + +assign cmp_and = &(cmp_mask_or); + +assign cmp_or = |(cmp_mask_and); + +generate + if (REGSIZE == 32) begin : cmp_andor_gen32 + assign cmp_andor = (&(cmp_mask_or[4:5]) & |(dvcbe[4:5])) | + (&(cmp_mask_or[6:7]) & |(dvcbe[6:7])); + end +endgenerate + +generate + if (REGSIZE == 64) begin : cmp_andor_gen64 + assign cmp_andor = (&(cmp_mask_or[0:1]) & |(dvcbe[0:1])) | + (&(cmp_mask_or[2:3]) & |(dvcbe[2:3])) | + (&(cmp_mask_or[4:5]) & |(dvcbe[4:5])) | + (&(cmp_mask_or[6:7]) & |(dvcbe[6:7])); + end +endgenerate + +assign dvc_cmpr = (dvcm[0:1] == 2'b00) ? en00 : + (dvcm[0:1] == 2'b01) ? (en & cmp_and) : + (dvcm[0:1] == 2'b10) ? (en & cmp_or) : + (en & cmp_andor); + +endmodule diff --git a/dev/verilog/work/lq_spr_tspr.v b/dev/verilog/work/lq_spr_tspr.v new file mode 100755 index 0000000..c969f3f --- /dev/null +++ b/dev/verilog/work/lq_spr_tspr.v @@ -0,0 +1,639 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" + +module lq_spr_tspr +#( + parameter hvmode = 1, + parameter a2mode = 1 +)( + + (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) + input [0:`NCLK_WIDTH-1] nclk, + + input d_mode_dc, + input delay_lclkr_dc, + input mpw1_dc_b, + input mpw2_dc_b, + input func_sl_force, + input func_sl_thold_0_b, + input sg_0, + + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + input scan_in, + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + output scan_out, + + // SlowSPR Interface + input slowspr_val_in, + input slowspr_rw_in, + input [0:9] slowspr_addr_in, + input [64-`GPR_WIDTH:63] slowspr_data_in, + + output tspr_done, + output [64-`GPR_WIDTH:63] tspr_rt, + + // SPRs + input cspr_tspr_msr_pr, + input cspr_tspr_msr_gs, + output [0:1] tspr_cspr_dbcr2_dac1us, + output [0:1] tspr_cspr_dbcr2_dac1er, + output [0:1] tspr_cspr_dbcr2_dac2us, + output [0:1] tspr_cspr_dbcr2_dac2er, + output [0:1] tspr_cspr_dbcr3_dac3us, + output [0:1] tspr_cspr_dbcr3_dac3er, + output [0:1] tspr_cspr_dbcr3_dac4us, + output [0:1] tspr_cspr_dbcr3_dac4er, + output tspr_cspr_dbcr2_dac12m, + output tspr_cspr_dbcr3_dac34m, + output [0:1] tspr_cspr_dbcr2_dvc1m, + output [0:1] tspr_cspr_dbcr2_dvc2m, + output [0:7] tspr_cspr_dbcr2_dvc1be, + output [0:7] tspr_cspr_dbcr2_dvc2be, + output spr_epsc_wr, + output spr_eplc_wr, + output [0:31] spr_acop_ct, + output spr_dbcr3_ivc, + output spr_dscr_lsd, + output spr_dscr_snse, + output spr_dscr_sse, + output [0:2] spr_dscr_dpfd, + output spr_eplc_epr, + output spr_eplc_eas, + output spr_eplc_egs, + output [0:7] spr_eplc_elpid, + output [0:13] spr_eplc_epid, + output spr_epsc_epr, + output spr_epsc_eas, + output spr_epsc_egs, + output [0:7] spr_epsc_elpid, + output [0:13] spr_epsc_epid, + output [0:31] spr_hacop_ct, + + // Power + inout vdd, + inout gnd +); + + +// Types +wire eplc_we_d; +wire eplc_we_q; +wire epsc_we_d; +wire epsc_we_q; + +// SPR Registers + wire [32:63] acop_d, acop_q; + wire [35:63] dbcr2_d, dbcr2_q; + wire [54:63] dbcr3_d, dbcr3_q; + wire [58:63] dscr_d, dscr_q; + wire [39:63] eplc_d, eplc_q; + wire [39:63] epsc_d, epsc_q; + wire [32:63] hacop_d, hacop_q; +// FUNC Scanchain + localparam acop_offset = 0; + localparam dbcr2_offset = acop_offset + 32*a2mode; + localparam dbcr3_offset = dbcr2_offset + 29*a2mode; + localparam dscr_offset = dbcr3_offset + 10; + localparam eplc_offset = dscr_offset + 6; + localparam epsc_offset = eplc_offset + 25*hvmode; + localparam hacop_offset = epsc_offset + 25*hvmode; + localparam last_reg_offset = hacop_offset + 32*hvmode; +parameter eplc_we_offset = last_reg_offset; +parameter epsc_we_offset = eplc_we_offset + 1; +parameter scan_right = epsc_we_offset + 1; +wire [0:scan_right-1] siv; +wire [0:scan_right-1] sov; +// Signals +wire tiup; +wire [00:63] tidn; +wire sspr_spr_we; +wire [11:20] sspr_instr; +wire sspr_is_mtspr; +wire [64-`GPR_WIDTH:63] sspr_spr_wd; +wire hyp_state; +// Data + wire [0:1] spr_dbcr2_dac1us; + wire [0:1] spr_dbcr2_dac1er; + wire [0:1] spr_dbcr2_dac2us; + wire [0:1] spr_dbcr2_dac2er; + wire spr_dbcr2_dac12m; + wire [0:1] spr_dbcr2_dvc1m; + wire [0:1] spr_dbcr2_dvc2m; + wire [0:7] spr_dbcr2_dvc1be; + wire [0:7] spr_dbcr2_dvc2be; + wire [0:1] spr_dbcr3_dac3us; + wire [0:1] spr_dbcr3_dac3er; + wire [0:1] spr_dbcr3_dac4us; + wire [0:1] spr_dbcr3_dac4er; + wire spr_dbcr3_dac34m; + wire [32:63] sspr_acop_di; + wire [35:63] sspr_dbcr2_di; + wire [54:63] sspr_dbcr3_di; + wire [58:63] sspr_dscr_di; + wire [39:63] sspr_eplc_di; + wire [39:63] sspr_epsc_di; + wire [32:63] sspr_hacop_di; + wire + sspr_acop_rdec , sspr_dbcr2_rdec, sspr_dbcr3_rdec, sspr_dscr_rdec + , sspr_eplc_rdec , sspr_epsc_rdec , sspr_hacop_rdec; + wire + sspr_acop_re , sspr_dbcr2_re , sspr_dbcr3_re , sspr_dscr_re + , sspr_eplc_re , sspr_epsc_re , sspr_hacop_re ; + wire + sspr_acop_wdec , sspr_dbcr2_wdec, sspr_dbcr3_wdec, sspr_dscr_wdec + , sspr_eplc_wdec , sspr_epsc_wdec , sspr_hacop_wdec; + wire + sspr_acop_we , sspr_dbcr2_we , sspr_dbcr3_we , sspr_dscr_we + , sspr_eplc_we , sspr_epsc_we , sspr_hacop_we ; + wire + acop_act , dbcr2_act , dbcr3_act , dscr_act + , eplc_act , epsc_act , hacop_act ; + wire [0:64] + acop_do , dbcr2_do , dbcr3_do , dscr_do + , eplc_do , epsc_do , hacop_do ; + +//!! Bugspray Include: lq_spr_tspr; +//## figtree_source: lq_spr_tspr.fig; + +assign tiup = 1'b1; +assign tidn = {64{1'b0}}; + +assign sspr_is_mtspr = (~slowspr_rw_in); +assign sspr_instr = {slowspr_addr_in[5:9], slowspr_addr_in[0:4]}; +assign sspr_spr_we = slowspr_val_in; +assign sspr_spr_wd = slowspr_data_in; + +assign hyp_state = ~(cspr_tspr_msr_pr | cspr_tspr_msr_gs); + +// SPR Input Control +// ACOP +assign acop_act = sspr_acop_we; +assign acop_d = sspr_acop_di; + +// HACOP +assign hacop_act = sspr_hacop_we; +assign hacop_d = sspr_hacop_di; + +// DBCR2 +assign dbcr2_act = sspr_dbcr2_we; +assign dbcr2_d = sspr_dbcr2_di; + +// DBCR3 +assign dbcr3_act = sspr_dbcr3_we; +assign dbcr3_d = sspr_dbcr3_di; + +// DSCR +assign dscr_act = sspr_dscr_we; +assign dscr_d = sspr_dscr_di; + +// EPLC +assign eplc_act = sspr_eplc_we; +assign eplc_we_d = sspr_eplc_we; +assign eplc_d[39:1 + 39] = sspr_eplc_di[39:1 + 39]; +assign eplc_d[(2 + 39) + 9:63] = sspr_eplc_di[(2 + 39) + 9:63]; + +assign eplc_d[2 + 39:(2 + 39) + 8] = (hyp_state == 1'b1) ? sspr_eplc_di[2 + 39:(2 + 39) + 8] : + eplc_q[2 + 39:(2 + 39) + 8]; + +// EPSC +assign epsc_act = sspr_epsc_we; +assign epsc_we_d = sspr_epsc_we; +assign epsc_d[39:1 + 39] = sspr_epsc_di[39:1 + 39]; +assign epsc_d[(2 + 39) + 9:63] = sspr_epsc_di[(2 + 39) + 9:63]; + +assign epsc_d[2 + 39:(2 + 39) + 8] = (hyp_state == 1'b1) ? sspr_epsc_di[2 + 39:(2 + 39) + 8] : + epsc_q[2 + 39:(2 + 39) + 8]; + +generate + if (a2mode == 0 & hvmode == 0) begin : readmux_00 + assign tspr_rt = + (dbcr3_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_dbcr3_re }}) | + (dscr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_dscr_re }}); + end +endgenerate +generate + if (a2mode == 0 & hvmode == 1) begin : readmux_01 + assign tspr_rt = + (dbcr3_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_dbcr3_re }}) | + (dscr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_dscr_re }}) | + (eplc_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_eplc_re }}) | + (epsc_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_epsc_re }}) | + (hacop_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_hacop_re }}); + end +endgenerate +generate + if (a2mode == 1 & hvmode == 0) begin : readmux_10 + assign tspr_rt = + (acop_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_acop_re }}) | + (dbcr2_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_dbcr2_re }}) | + (dbcr3_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_dbcr3_re }}) | + (dscr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_dscr_re }}); + end +endgenerate +generate + if (a2mode == 1 & hvmode == 1) begin : readmux_11 + assign tspr_rt = + (acop_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_acop_re }}) | + (dbcr2_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_dbcr2_re }}) | + (dbcr3_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_dbcr3_re }}) | + (dscr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_dscr_re }}) | + (eplc_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_eplc_re }}) | + (epsc_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_epsc_re }}) | + (hacop_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{sspr_hacop_re }}); + end +endgenerate + + assign sspr_acop_rdec = (sspr_instr[11:20] == 10'b1111100000); // 31 + assign sspr_dbcr2_rdec = (sspr_instr[11:20] == 10'b1011001001); // 310 + assign sspr_dbcr3_rdec = (sspr_instr[11:20] == 10'b1000011010); // 848 + assign sspr_dscr_rdec = (sspr_instr[11:20] == 10'b1000100000); // 17 + assign sspr_eplc_rdec = (sspr_instr[11:20] == 10'b1001111101); // 947 + assign sspr_epsc_rdec = (sspr_instr[11:20] == 10'b1010011101); // 948 + assign sspr_hacop_rdec = (sspr_instr[11:20] == 10'b1111101010); // 351 + assign sspr_acop_re = sspr_acop_rdec; + assign sspr_dbcr2_re = sspr_dbcr2_rdec; + assign sspr_dbcr3_re = sspr_dbcr3_rdec; + assign sspr_dscr_re = sspr_dscr_rdec; + assign sspr_eplc_re = sspr_eplc_rdec; + assign sspr_epsc_re = sspr_epsc_rdec; + assign sspr_hacop_re = sspr_hacop_rdec; + + assign sspr_acop_wdec = sspr_acop_rdec; + assign sspr_dbcr2_wdec = sspr_dbcr2_rdec; + assign sspr_dbcr3_wdec = sspr_dbcr3_rdec; + assign sspr_dscr_wdec = sspr_dscr_rdec; + assign sspr_eplc_wdec = sspr_eplc_rdec; + assign sspr_epsc_wdec = sspr_epsc_rdec; + assign sspr_hacop_wdec = (sspr_instr[11:20] == 10'b1111101010); // 351 + assign sspr_acop_we = sspr_spr_we & sspr_is_mtspr & sspr_acop_wdec; + assign sspr_dbcr2_we = sspr_spr_we & sspr_is_mtspr & sspr_dbcr2_wdec; + assign sspr_dbcr3_we = sspr_spr_we & sspr_is_mtspr & sspr_dbcr3_wdec; + assign sspr_dscr_we = sspr_spr_we & sspr_is_mtspr & sspr_dscr_wdec; + assign sspr_eplc_we = sspr_spr_we & sspr_is_mtspr & sspr_eplc_wdec; + assign sspr_epsc_we = sspr_spr_we & sspr_is_mtspr & sspr_epsc_wdec; + assign sspr_hacop_we = sspr_spr_we & sspr_is_mtspr & sspr_hacop_wdec; + +assign tspr_done = slowspr_val_in & ( + sspr_acop_rdec | sspr_dbcr2_rdec | sspr_dbcr3_rdec + | sspr_dscr_rdec | sspr_eplc_rdec | sspr_epsc_rdec + | sspr_hacop_rdec ); + + assign spr_acop_ct = acop_q[32:63]; + assign spr_dbcr2_dac1us = dbcr2_q[35:36]; + assign spr_dbcr2_dac1er = dbcr2_q[37:38]; + assign spr_dbcr2_dac2us = dbcr2_q[39:40]; + assign spr_dbcr2_dac2er = dbcr2_q[41:42]; + assign spr_dbcr2_dac12m = dbcr2_q[43]; + assign spr_dbcr2_dvc1m = dbcr2_q[44:45]; + assign spr_dbcr2_dvc2m = dbcr2_q[46:47]; + assign spr_dbcr2_dvc1be = dbcr2_q[48:55]; + assign spr_dbcr2_dvc2be = dbcr2_q[56:63]; + assign spr_dbcr3_dac3us = dbcr3_q[54:55]; + assign spr_dbcr3_dac3er = dbcr3_q[56:57]; + assign spr_dbcr3_dac4us = dbcr3_q[58:59]; + assign spr_dbcr3_dac4er = dbcr3_q[60:61]; + assign spr_dbcr3_dac34m = dbcr3_q[62]; + assign spr_dbcr3_ivc = dbcr3_q[63]; + assign spr_dscr_lsd = dscr_q[58]; + assign spr_dscr_snse = dscr_q[59]; + assign spr_dscr_sse = dscr_q[60]; + assign spr_dscr_dpfd = dscr_q[61:63]; + assign spr_eplc_epr = eplc_q[39]; + assign spr_eplc_eas = eplc_q[40]; + assign spr_eplc_egs = eplc_q[41]; + assign spr_eplc_elpid = eplc_q[42:49]; + assign spr_eplc_epid = eplc_q[50:63]; + assign spr_epsc_epr = epsc_q[39]; + assign spr_epsc_eas = epsc_q[40]; + assign spr_epsc_egs = epsc_q[41]; + assign spr_epsc_elpid = epsc_q[42:49]; + assign spr_epsc_epid = epsc_q[50:63]; + assign spr_hacop_ct = hacop_q[32:63]; +assign tspr_cspr_dbcr2_dac1us = spr_dbcr2_dac1us; +assign tspr_cspr_dbcr2_dac1er = spr_dbcr2_dac1er; +assign tspr_cspr_dbcr2_dac2us = spr_dbcr2_dac2us; +assign tspr_cspr_dbcr2_dac2er = spr_dbcr2_dac2er; +assign tspr_cspr_dbcr3_dac3us = spr_dbcr3_dac3us; +assign tspr_cspr_dbcr3_dac3er = spr_dbcr3_dac3er; +assign tspr_cspr_dbcr3_dac4us = spr_dbcr3_dac4us; +assign tspr_cspr_dbcr3_dac4er = spr_dbcr3_dac4er; +assign tspr_cspr_dbcr2_dac12m = spr_dbcr2_dac12m; +assign tspr_cspr_dbcr3_dac34m = spr_dbcr3_dac34m; +assign tspr_cspr_dbcr2_dvc1m = spr_dbcr2_dvc1m; +assign tspr_cspr_dbcr2_dvc2m = spr_dbcr2_dvc2m; +assign tspr_cspr_dbcr2_dvc1be = spr_dbcr2_dvc1be; +assign tspr_cspr_dbcr2_dvc2be = spr_dbcr2_dvc2be; +assign spr_epsc_wr = epsc_we_q; +assign spr_eplc_wr = eplc_we_q; + + + // ACOP + assign sspr_acop_di = { sspr_spr_wd[32:63] }; //CT + + assign acop_do = { tidn[0:0] , + tidn[0:31] , ///// + acop_q[32:63] }; //CT + // DBCR2 + assign sspr_dbcr2_di = { sspr_spr_wd[32:33] , //DAC1US + sspr_spr_wd[34:35] , //DAC1ER + sspr_spr_wd[36:37] , //DAC2US + sspr_spr_wd[38:39] , //DAC2ER + sspr_spr_wd[41:41] , //DAC12M + sspr_spr_wd[44:45] , //DVC1M + sspr_spr_wd[46:47] , //DVC2M + sspr_spr_wd[48:55] , //DVC1BE + sspr_spr_wd[56:63] }; //DVC2BE + + assign dbcr2_do = { tidn[0:0] , + tidn[0:31] , ///// + dbcr2_q[35:36] , //DAC1US + dbcr2_q[37:38] , //DAC1ER + dbcr2_q[39:40] , //DAC2US + dbcr2_q[41:42] , //DAC2ER + tidn[40:40] , ///// + dbcr2_q[43:43] , //DAC12M + tidn[42:43] , ///// + dbcr2_q[44:45] , //DVC1M + dbcr2_q[46:47] , //DVC2M + dbcr2_q[48:55] , //DVC1BE + dbcr2_q[56:63] }; //DVC2BE + // DBCR3 + assign sspr_dbcr3_di = { sspr_spr_wd[32:33] , //DAC3US + sspr_spr_wd[34:35] , //DAC3ER + sspr_spr_wd[36:37] , //DAC4US + sspr_spr_wd[38:39] , //DAC4ER + sspr_spr_wd[41:41] , //DAC34M + sspr_spr_wd[63:63] }; //IVC + + assign dbcr3_do = { tidn[0:0] , + tidn[0:31] , ///// + dbcr3_q[54:55] , //DAC3US + dbcr3_q[56:57] , //DAC3ER + dbcr3_q[58:59] , //DAC4US + dbcr3_q[60:61] , //DAC4ER + tidn[40:40] , ///// + dbcr3_q[62:62] , //DAC34M + tidn[42:62] , ///// + dbcr3_q[63:63] }; //IVC + // DSCR + assign sspr_dscr_di = { sspr_spr_wd[58:58] , //LSD + sspr_spr_wd[59:59] , //SNSE + sspr_spr_wd[60:60] , //SSE + sspr_spr_wd[61:63] }; //DPFD + + assign dscr_do = { tidn[0:0] , + tidn[0:31] , ///// + tidn[32:57] , ///// + dscr_q[58:58] , //LSD + dscr_q[59:59] , //SNSE + dscr_q[60:60] , //SSE + dscr_q[61:63] }; //DPFD + // EPLC + assign sspr_eplc_di = { sspr_spr_wd[32:32] , //EPR + sspr_spr_wd[33:33] , //EAS + sspr_spr_wd[34:34] , //EGS + sspr_spr_wd[40:47] , //ELPID + sspr_spr_wd[50:63] }; //EPID + + assign eplc_do = { tidn[0:0] , + tidn[0:31] , ///// + eplc_q[39:39] , //EPR + eplc_q[40:40] , //EAS + eplc_q[41:41] , //EGS + tidn[35:39] , ///// + eplc_q[42:49] , //ELPID + tidn[48:49] , ///// + eplc_q[50:63] }; //EPID + // EPSC + assign sspr_epsc_di = { sspr_spr_wd[32:32] , //EPR + sspr_spr_wd[33:33] , //EAS + sspr_spr_wd[34:34] , //EGS + sspr_spr_wd[40:47] , //ELPID + sspr_spr_wd[50:63] }; //EPID + + assign epsc_do = { tidn[0:0] , + tidn[0:31] , ///// + epsc_q[39:39] , //EPR + epsc_q[40:40] , //EAS + epsc_q[41:41] , //EGS + tidn[35:39] , ///// + epsc_q[42:49] , //ELPID + tidn[48:49] , ///// + epsc_q[50:63] }; //EPID + // HACOP + assign sspr_hacop_di = { sspr_spr_wd[32:63] }; //CT + + assign hacop_do = { tidn[0:0] , + tidn[0:31] , ///// + hacop_q[32:63] }; //CT + + // Unused Signals + wire unused_do_bits = |{ + acop_do[0:64-`GPR_WIDTH] + ,dbcr2_do[0:64-`GPR_WIDTH] + ,dbcr3_do[0:64-`GPR_WIDTH] + ,dscr_do[0:64-`GPR_WIDTH] + ,eplc_do[0:64-`GPR_WIDTH] + ,epsc_do[0:64-`GPR_WIDTH] + ,hacop_do[0:64-`GPR_WIDTH] + }; + +generate + if (a2mode == 1) begin : acop_latch_gen + tri_ser_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) acop_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(acop_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b),.mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[acop_offset:acop_offset + 32 - 1]), + .scout(sov[acop_offset:acop_offset + 32 - 1]), + .din(acop_d), + .dout(acop_q) + ); + end + if (a2mode == 0) begin : acop_latch_tie + assign acop_q = {32{1'b0}}; + end +endgenerate +generate + if (a2mode == 1) begin : dbcr2_latch_gen + tri_ser_rlmreg_p #(.WIDTH(29), .INIT(0), .NEEDS_SRESET(1)) dbcr2_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(dbcr2_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b),.mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[dbcr2_offset:dbcr2_offset + 29 - 1]), + .scout(sov[dbcr2_offset:dbcr2_offset + 29 - 1]), + .din(dbcr2_d), + .dout(dbcr2_q) + ); + end + if (a2mode == 0) begin : dbcr2_latch_tie + assign dbcr2_q = {29{1'b0}}; + end +endgenerate + tri_ser_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) dbcr3_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(dbcr3_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b),.mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[dbcr3_offset:dbcr3_offset + 10 - 1]), + .scout(sov[dbcr3_offset:dbcr3_offset + 10 - 1]), + .din(dbcr3_d), + .dout(dbcr3_q) + ); + tri_ser_rlmreg_p #(.WIDTH(6), .INIT(32), .NEEDS_SRESET(1)) dscr_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(dscr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b),.mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[dscr_offset:dscr_offset + 6 - 1]), + .scout(sov[dscr_offset:dscr_offset + 6 - 1]), + .din(dscr_d), + .dout(dscr_q) + ); +generate + if (hvmode == 1) begin : eplc_latch_gen + tri_ser_rlmreg_p #(.WIDTH(25), .INIT(0), .NEEDS_SRESET(1)) eplc_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(eplc_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b),.mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[eplc_offset:eplc_offset + 25 - 1]), + .scout(sov[eplc_offset:eplc_offset + 25 - 1]), + .din(eplc_d), + .dout(eplc_q) + ); + end + if (hvmode == 0) begin : eplc_latch_tie + assign eplc_q = {25{1'b0}}; + end +endgenerate +generate + if (hvmode == 1) begin : epsc_latch_gen + tri_ser_rlmreg_p #(.WIDTH(25), .INIT(0), .NEEDS_SRESET(1)) epsc_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(epsc_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b),.mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[epsc_offset:epsc_offset + 25 - 1]), + .scout(sov[epsc_offset:epsc_offset + 25 - 1]), + .din(epsc_d), + .dout(epsc_q) + ); + end + if (hvmode == 0) begin : epsc_latch_tie + assign epsc_q = {25{1'b0}}; + end +endgenerate +generate + if (hvmode == 1) begin : hacop_latch_gen + tri_ser_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) hacop_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(hacop_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b),.mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[hacop_offset:hacop_offset + 32 - 1]), + .scout(sov[hacop_offset:hacop_offset + 32 - 1]), + .din(hacop_d), + .dout(hacop_q) + ); + end + if (hvmode == 0) begin : hacop_latch_tie + assign hacop_q = {32{1'b0}}; + end +endgenerate + + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) eplc_we_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[eplc_we_offset]), + .scout(sov[eplc_we_offset]), + .din(eplc_we_d), + .dout(eplc_we_q) +); + + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) epsc_we_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[epsc_we_offset]), + .scout(sov[epsc_we_offset]), + .din(epsc_we_d), + .dout(epsc_we_q) +); + +assign siv[0:scan_right - 1] = {sov[1:scan_right - 1], scan_in}; +assign scan_out = sov[0]; + +endmodule diff --git a/dev/verilog/work/lq_stq.v b/dev/verilog/work/lq_stq.v new file mode 100755 index 0000000..a588024 --- /dev/null +++ b/dev/verilog/work/lq_stq.v @@ -0,0 +1,7584 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// +// Description: Store Queue +// +//***************************************************************************** + +// ########################################################################################## +// Contents +// 1) Load Queue +// 2) Store +// 3) Load/Store Queue Control +// ########################################################################################## + +`include "tri_a2o.vh" + + // `define `EXPAND_TYPE 2; + // `define `GPR_WIDTH_ENC 6; // Register Mode 5 32bit, 6 64bit + // `define `STQ_ENTRIES 12; // Store Queue Size + // `define STQ_FWD_ENTRIES 4; // number of stq entries that can be forwarded from + // `define `STQ_ENTRIES_ENC 4; // Store Queue Encoded Size + // `define STQ_DATA_SIZE 64; // 64 or 128 Bit store data sizes supported + // `define `ITAG_SIZE_ENC 7; // ITAG size + // `define `CR_POOL_ENC 5; // Encode of CR rename pool size + // `define `GPR_POOL_ENC 6; + // `define AXU_SPARE_ENC 3; + // `define THREADS_POOL_ENC 1; + // `define DC_SIZE 15; // 14 > 16K L1D$, 15 > 32K L1D$ + // `define CL_SIZE 6; // 6 > 64B CLINE, 7 > 128B CLINE + // `define REAL_IFAR_WIDTH 42; // real addressing bits + // `define `THREADS 2; + // `define LMQ_ENTRIES 8; + +module lq_stq( + rv_lq_rv1_i0_vld, + rv_lq_rv1_i0_ucode_preissue, + rv_lq_rv1_i0_s3_t, + rv_lq_rv1_i0_rte_sq, + rv_lq_rv1_i0_itag, + rv_lq_rv1_i1_vld, + rv_lq_rv1_i1_ucode_preissue, + rv_lq_rv1_i1_s3_t, + rv_lq_rv1_i1_rte_sq, + rv_lq_rv1_i1_itag, + rv_lq_vld, + rv_lq_isLoad, + xu1_lq_ex2_stq_val, + xu1_lq_ex2_stq_itag, + xu1_lq_ex2_stq_dvc1_cmp, + xu1_lq_ex2_stq_dvc2_cmp, + ctl_lsq_ex4_xu1_data, + xu1_lq_ex3_illeg_lswx, + xu1_lq_ex3_strg_noop, + xu_lq_axu_ex_stq_val, + xu_lq_axu_ex_stq_itag, + xu_lq_axu_exp1_stq_data, + ctl_lsq_ex2_itag, + ctl_lsq_ex2_thrd_id, + ctl_lsq_ex3_byte_en, + ctl_lsq_ex3_p_addr, + ctl_lsq_ex3_algebraic, + ctl_lsq_ex2_streq_val, + ctl_lsq_ex4_streq_val, + ctl_lsq_ex3_ldreq_val, + ctl_lsq_ex3_pfetch_val, + ctl_lsq_ex3_wchkall_val, + ctl_lsq_ex3_opsize, + ctl_lsq_ex4_p_addr, + ctl_lsq_ex4_cline_chk, + ctl_lsq_ex4_wimge, + ctl_lsq_ex4_byte_swap, + ctl_lsq_ex4_is_sync, + ctl_lsq_ex4_all_thrd_chk, + ctl_lsq_ex4_is_store, + ctl_lsq_ex4_is_resv, + ctl_lsq_ex4_is_mfgpr, + ctl_lsq_ex4_is_icswxr, + ctl_lsq_ex4_is_icbi, + ctl_lsq_ex4_is_inval_op, + ctl_lsq_ex4_dreq_val, + ctl_lsq_ex4_has_data, + ctl_lsq_ex4_send_l2, + ctl_lsq_ex4_watch_clr, + ctl_lsq_ex4_watch_clr_all, + ctl_lsq_ex4_mtspr_trace, + ctl_lsq_ex4_is_cinval, + ctl_lsq_ex5_lock_clr, + ctl_lsq_ex5_ttype, + ctl_lsq_ex5_axu_val, + ctl_lsq_ex5_is_epid, + ctl_lsq_ex5_usr_def, + ctl_lsq_ex5_l_fld, + ctl_lsq_ex5_tgpr, + ctl_lsq_ex5_dvc, + ctl_lsq_ex5_dacrw, + ctl_lsq_ex5_load_hit, + ctl_lsq_ex5_flush_req, + ctl_lsq_rv1_dir_rd_val, + ldq_stq_ldm_cpl, + ldq_stq_ex5_ldm_hit, + ldq_stq_ex5_ldm_entry, + ldq_stq_stq4_dir_upd, + ldq_stq_stq4_cclass, + stq_odq_i0_stTag, + stq_odq_i1_stTag, + stq_odq_stq4_stTag_inval, + stq_odq_stq4_stTag, + odq_stq_ex2_nxt_oldest_val, + odq_stq_ex2_nxt_oldest_stTag, + odq_stq_ex2_nxt_youngest_val, + odq_stq_ex2_nxt_youngest_stTag, + odq_stq_resolved, + odq_stq_stTag, + ctl_lsq_spr_dvc1_dbg, + ctl_lsq_spr_dvc2_dbg, + ctl_lsq_spr_dbcr2_dvc1m, + ctl_lsq_spr_dbcr2_dvc1be, + ctl_lsq_spr_dbcr2_dvc2m, + ctl_lsq_spr_dbcr2_dvc2be, + ctl_lsq_dbg_int_en, + iu_lq_cp_next_val, + iu_lq_cp_next_itag, + iu_lq_cp_flush, + iu_lq_i0_completed, + iu_lq_i0_completed_itag, + iu_lq_i1_completed, + iu_lq_i1_completed_itag, + lsq_ctl_stq_cpl_ready, + lsq_ctl_stq_cpl_ready_itag, + lsq_ctl_stq_cpl_ready_tid, + lsq_ctl_stq_n_flush, + lsq_ctl_stq_np1_flush, + lsq_ctl_stq_exception_val, + lsq_ctl_stq_exception, + lsq_ctl_stq_dacrw, + ctl_lsq_stq_cpl_blk, + ctl_lsq_ex_pipe_full, + stq_ldq_empty, + arb_stq_cred_avail, + xu_lq_spr_xucr0_cls, + iu_lq_spr_iucr0_icbi_ack, + ctl_lsq_spr_lsucr0_sca, + ctl_lsq_spr_lsucr0_dfwd, + ldq_stq_rel1_blk_store, + stq_hold_all_req, + stq_rv_set_hold, + stq_rv_clr_hold, + lsq_ctl_ex5_stq_restart, + lsq_ctl_ex5_stq_restart_miss, + stq_arb_st_req_avail, + stq_arb_stq3_cmmt_val, + stq_arb_stq3_cmmt_reject, + stq_arb_stq3_req_val, + stq_arb_stq3_tid, + stq_arb_stq3_usrDef, + stq_arb_stq3_wimge, + stq_arb_stq3_p_addr, + stq_arb_stq3_ttype, + stq_arb_stq3_opSize, + stq_arb_stq3_byteEn, + stq_arb_stq3_cTag, + stq_arb_stq1_byte_swap, + stq_arb_stq1_thrd_id, + stq_dat_stq1_stg_act, + lsq_dat_stq1_val, + lsq_dat_stq1_mftgpr_val, + lsq_dat_stq1_store_val, + lsq_dat_stq1_byte_en, + stq_arb_stq1_axu_val, + stq_arb_stq1_epid_val, + stq_arb_stq1_opSize, + stq_arb_stq1_p_addr, + stq_arb_stq1_wimge_i, + stq_arb_stq1_store_data, + stq_ctl_stq1_stg_act, + lsq_ctl_stq1_val, + lsq_ctl_stq1_mftgpr_val, + lsq_ctl_stq1_mfdpf_val, + lsq_ctl_stq1_mfdpa_val, + lsq_ctl_stq1_lock_clr, + lsq_ctl_stq1_watch_clr, + lsq_ctl_stq1_l_fld, + lsq_ctl_stq1_inval, + lsq_ctl_stq1_dci_val, + lsq_ctl_stq1_store_val, + lsq_ctl_stq4_xucr0_cul, + lsq_ctl_stq5_itag, + lsq_ctl_stq5_tgpr, + ctl_lsq_stq4_perr_reject, + lsq_ctl_ex3_strg_val, + lsq_ctl_ex3_strg_noop, + lsq_ctl_ex3_illeg_lswx, + lsq_ctl_ex3_ct_val, + lsq_ctl_ex3_be_ct, + lsq_ctl_ex3_le_ct, + lsq_ctl_stq1_resv, + stq_stq2_blk_req, + lsq_ctl_ex5_fwd_data, + lsq_ctl_ex5_fwd_val, + lsq_ctl_ex6_stq_events, + lsq_perv_stq_events, + lsq_ctl_sync_in_stq, + lsq_ctl_sync_done, + sq_iu_credit_free, + an_ac_sync_ack, + lq_iu_icbi_val, + lq_iu_icbi_addr, + iu_lq_icbi_complete, + lq_iu_ici_val, + l2_back_inv_val, + l2_back_inv_addr, + an_ac_back_inv, + an_ac_back_inv_target_bit3, + an_ac_back_inv_addr, + an_ac_back_inv_addr_lo, + an_ac_stcx_complete, + an_ac_stcx_pass, + an_ac_icbi_ack, + an_ac_icbi_ack_thread, + an_ac_coreid, + xu_lq_xer_cp_rd, + lq_xu_cr_l2_we, + lq_xu_cr_l2_wa, + lq_xu_cr_l2_wd, + stq_arb_release_itag_vld, + stq_arb_release_itag, + stq_arb_release_tid, + vdd, + gnd, + nclk, + sg_0, + func_sl_thold_0_b, + func_sl_force, + d_mode_dc, + delay_lclkr_dc, + mpw1_dc_b, + mpw2_dc_b, + scan_in, + scan_out +); + + // IU interface to RV for instruction insertion + // port 0 + input [0:`THREADS-1] rv_lq_rv1_i0_vld; + input rv_lq_rv1_i0_ucode_preissue; + input [0:2] rv_lq_rv1_i0_s3_t; + input rv_lq_rv1_i0_rte_sq; + input [0:`ITAG_SIZE_ENC-1] rv_lq_rv1_i0_itag; + + // port 1 + input [0:`THREADS-1] rv_lq_rv1_i1_vld; + input rv_lq_rv1_i1_ucode_preissue; + input [0:2] rv_lq_rv1_i1_s3_t; + input rv_lq_rv1_i1_rte_sq; + input [0:`ITAG_SIZE_ENC-1] rv_lq_rv1_i1_itag; + + // LQ RV Snoop + input [0:`THREADS-1] rv_lq_vld; + input rv_lq_isLoad; + + // FXU0 Data interface + input [0:`THREADS-1] xu1_lq_ex2_stq_val; + input [0:`ITAG_SIZE_ENC-1] xu1_lq_ex2_stq_itag; + input [(64-(2**`GPR_WIDTH_ENC))/8:7] xu1_lq_ex2_stq_dvc1_cmp; + input [(64-(2**`GPR_WIDTH_ENC))/8:7] xu1_lq_ex2_stq_dvc2_cmp; + input [64-(2**`GPR_WIDTH_ENC):63] ctl_lsq_ex4_xu1_data; + input xu1_lq_ex3_illeg_lswx; + input xu1_lq_ex3_strg_noop; + + // AXU Data interface + input [0:`THREADS-1] xu_lq_axu_ex_stq_val; + input [0:`ITAG_SIZE_ENC-1] xu_lq_axu_ex_stq_itag; + input [(128-`STQ_DATA_SIZE):127] xu_lq_axu_exp1_stq_data; + + // Store Request Control (data into q) + input [0:`ITAG_SIZE_ENC-1] ctl_lsq_ex2_itag; + input [0:`THREADS-1] ctl_lsq_ex2_thrd_id; + input [0:15] ctl_lsq_ex3_byte_en; + input [58:63] ctl_lsq_ex3_p_addr; + input ctl_lsq_ex3_algebraic; + input [0:`THREADS-1] ctl_lsq_ex2_streq_val; + input [0:`THREADS-1] ctl_lsq_ex4_streq_val; + input [0:`THREADS-1] ctl_lsq_ex3_ldreq_val; + input ctl_lsq_ex3_pfetch_val; + input [0:`THREADS-1] ctl_lsq_ex3_wchkall_val; + input [0:2] ctl_lsq_ex3_opsize; + input [64-`REAL_IFAR_WIDTH:63] ctl_lsq_ex4_p_addr; + input ctl_lsq_ex4_cline_chk; // cacheline op + input [0:4] ctl_lsq_ex4_wimge; + input ctl_lsq_ex4_byte_swap; + input ctl_lsq_ex4_is_sync; + input ctl_lsq_ex4_all_thrd_chk; + input ctl_lsq_ex4_is_store; + input ctl_lsq_ex4_is_resv; + input ctl_lsq_ex4_is_mfgpr; + input ctl_lsq_ex4_is_icswxr; + input ctl_lsq_ex4_is_icbi; + input ctl_lsq_ex4_is_inval_op; + input ctl_lsq_ex4_dreq_val; + input ctl_lsq_ex4_has_data; + input ctl_lsq_ex4_send_l2; + input ctl_lsq_ex4_watch_clr; + input ctl_lsq_ex4_watch_clr_all; + input ctl_lsq_ex4_mtspr_trace; + input ctl_lsq_ex4_is_cinval; + input ctl_lsq_ex5_lock_clr; + input [0:5] ctl_lsq_ex5_ttype; + input ctl_lsq_ex5_axu_val; // XU;AXU type operation + input ctl_lsq_ex5_is_epid; + input [0:3] ctl_lsq_ex5_usr_def; + input [0:1] ctl_lsq_ex5_l_fld; + input [0:`AXU_SPARE_ENC+`GPR_POOL_ENC+`THREADS_POOL_ENC-1] ctl_lsq_ex5_tgpr; + input [0:1] ctl_lsq_ex5_dvc; + input [0:3] ctl_lsq_ex5_dacrw; + input ctl_lsq_ex5_load_hit; + input ctl_lsq_ex5_flush_req; + input ctl_lsq_rv1_dir_rd_val; + + input [0:`LMQ_ENTRIES-1] ldq_stq_ldm_cpl; + input [0:`LMQ_ENTRIES-1] ldq_stq_ex5_ldm_hit; + input [0:`LMQ_ENTRIES-1] ldq_stq_ex5_ldm_entry; + input ldq_stq_stq4_dir_upd; + input [64-(`DC_SIZE-3):57] ldq_stq_stq4_cclass; + + // Age Detection + // store tag used when instruction was inserted to store queue + output [0:`STQ_ENTRIES_ENC-1] stq_odq_i0_stTag; + output [0:`STQ_ENTRIES_ENC-1] stq_odq_i1_stTag; + + // store tag is committed; remove from order queue and dont compare against it + output stq_odq_stq4_stTag_inval; + output [0:`STQ_ENTRIES_ENC-1] stq_odq_stq4_stTag; + + // order queue closest oldest store to the ex2 load request + input odq_stq_ex2_nxt_oldest_val; + input [0:`STQ_ENTRIES-1] odq_stq_ex2_nxt_oldest_stTag; + + // order queue closest youngest store to the ex2 load request + input odq_stq_ex2_nxt_youngest_val; + input [0:`STQ_ENTRIES-1] odq_stq_ex2_nxt_youngest_stTag; + + // store tag is resolved from odq allow stq to commit + input odq_stq_resolved; + input [0:`STQ_ENTRIES-1] odq_stq_stTag; + + // Interface with Local SPR's + input [64-(2**`GPR_WIDTH_ENC):63] ctl_lsq_spr_dvc1_dbg; + input [64-(2**`GPR_WIDTH_ENC):63] ctl_lsq_spr_dvc2_dbg; + input [0:2*`THREADS-1] ctl_lsq_spr_dbcr2_dvc1m; + input [0:8*`THREADS-1] ctl_lsq_spr_dbcr2_dvc1be; + input [0:2*`THREADS-1] ctl_lsq_spr_dbcr2_dvc2m; + input [0:8*`THREADS-1] ctl_lsq_spr_dbcr2_dvc2be; + input [0:`THREADS-1] ctl_lsq_dbg_int_en; + + // Completion Inputs + input [0:`THREADS-1] iu_lq_cp_next_val; + input [0:(`ITAG_SIZE_ENC*`THREADS)-1] iu_lq_cp_next_itag; + input [0:`THREADS-1] iu_lq_cp_flush; + input [0:`THREADS-1] iu_lq_i0_completed; + input [0:(`ITAG_SIZE_ENC*`THREADS)-1] iu_lq_i0_completed_itag; + input [0:`THREADS-1] iu_lq_i1_completed; + input [0:(`ITAG_SIZE_ENC*`THREADS)-1] iu_lq_i1_completed_itag; + + // Store Queue Completion Report + output lsq_ctl_stq_cpl_ready; + output [0:`ITAG_SIZE_ENC-1] lsq_ctl_stq_cpl_ready_itag; + output [0:`THREADS-1] lsq_ctl_stq_cpl_ready_tid; + output lsq_ctl_stq_n_flush; + output lsq_ctl_stq_np1_flush; + output lsq_ctl_stq_exception_val; + output [0:5] lsq_ctl_stq_exception; + output [0:3] lsq_ctl_stq_dacrw; + input ctl_lsq_stq_cpl_blk; + input ctl_lsq_ex_pipe_full; + + // Store Queue is empty + output [0:`THREADS-1] stq_ldq_empty; + + // L2 Credits Available + input arb_stq_cred_avail; + + // Data Cache Config + input xu_lq_spr_xucr0_cls; // Data Cache Line Size Mode + + // ICBI ACK Enable + input iu_lq_spr_iucr0_icbi_ack; + + // LSUCR0 Config Bits + input [0:2] ctl_lsq_spr_lsucr0_sca; + input ctl_lsq_spr_lsucr0_dfwd; + + // Interface to Store Queue (reload block) + input ldq_stq_rel1_blk_store; + + // Reservation station hold (times for forcing a hole) + output stq_hold_all_req; + + // Reservation station set barrier indicator + output stq_rv_set_hold; + output [0:`THREADS-1] stq_rv_clr_hold; + + // STORE Queue RESTART indicator + output lsq_ctl_ex5_stq_restart; + output lsq_ctl_ex5_stq_restart_miss; + + // STQ Request to the L2 + output stq_arb_st_req_avail; + output stq_arb_stq3_cmmt_val; + output stq_arb_stq3_cmmt_reject; + output stq_arb_stq3_req_val; + output [0:1] stq_arb_stq3_tid; + output reg [0:3] stq_arb_stq3_usrDef; + output reg [0:4] stq_arb_stq3_wimge; + output reg [64-`REAL_IFAR_WIDTH:63] stq_arb_stq3_p_addr; + output [0:5] stq_arb_stq3_ttype; + output reg [0:2] stq_arb_stq3_opSize; + output reg [0:15] stq_arb_stq3_byteEn; + output [0:4] stq_arb_stq3_cTag; + output reg stq_arb_stq1_byte_swap; + output reg [0:`THREADS-1] stq_arb_stq1_thrd_id; + + // Store Commit Data Control + output stq_dat_stq1_stg_act; // ACT Pin for DAT + output lsq_dat_stq1_val; + output lsq_dat_stq1_mftgpr_val; + output reg lsq_dat_stq1_store_val; + output reg [0:15] lsq_dat_stq1_byte_en; + output reg stq_arb_stq1_axu_val; + output reg stq_arb_stq1_epid_val; + output reg [0:2] stq_arb_stq1_opSize; + output [64-`REAL_IFAR_WIDTH:63] stq_arb_stq1_p_addr; + output reg stq_arb_stq1_wimge_i; + output reg [(128-`STQ_DATA_SIZE):127] stq_arb_stq1_store_data; + + // Store Commit Directory Control + output stq_ctl_stq1_stg_act; // ACT Pin for CTL + output lsq_ctl_stq1_val; + output lsq_ctl_stq1_mftgpr_val; + output lsq_ctl_stq1_mfdpf_val; + output lsq_ctl_stq1_mfdpa_val; + output reg lsq_ctl_stq1_lock_clr; + output reg lsq_ctl_stq1_watch_clr; + output reg [0:1] lsq_ctl_stq1_l_fld; + output reg lsq_ctl_stq1_inval; + output lsq_ctl_stq1_dci_val; + output reg lsq_ctl_stq1_store_val; + output lsq_ctl_stq4_xucr0_cul; + output reg [0:`ITAG_SIZE_ENC-1] lsq_ctl_stq5_itag; + output reg [0:`AXU_SPARE_ENC+`GPR_POOL_ENC+`THREADS_POOL_ENC-1] lsq_ctl_stq5_tgpr; + input ctl_lsq_stq4_perr_reject; + + // Illegal LSWX has been determined + output lsq_ctl_ex3_strg_val; // STQ has checked XER valid + output lsq_ctl_ex3_strg_noop; // STQ detected a noop of LSWX/STSWX + output lsq_ctl_ex3_illeg_lswx; // STQ detected illegal form of LSWX + output lsq_ctl_ex3_ct_val; // ICSWX Data is valid + output [0:5] lsq_ctl_ex3_be_ct; // Big Endian Coprocessor Type Select + output [0:5] lsq_ctl_ex3_le_ct; // Little Endian Coprocessor Type Select + + // Store Commit Control + output reg lsq_ctl_stq1_resv; + output stq_stq2_blk_req; + + output [(128-`STQ_DATA_SIZE):127] lsq_ctl_ex5_fwd_data; + output lsq_ctl_ex5_fwd_val; + output [0:1] lsq_ctl_ex6_stq_events; + output [0:(3*`THREADS)+2] lsq_perv_stq_events; + + output lsq_ctl_sync_in_stq; + output lsq_ctl_sync_done; + + output [0:`THREADS-1] sq_iu_credit_free; + + input [0:`THREADS-1] an_ac_sync_ack; + + // ICBI interface + output [0:`THREADS-1] lq_iu_icbi_val; + output [64-`REAL_IFAR_WIDTH:57] lq_iu_icbi_addr; + input [0:`THREADS-1] iu_lq_icbi_complete; + + // ICI Interace + output lq_iu_ici_val; + + // Back-Invalidate Valid + input l2_back_inv_val; + input [64-(`DC_SIZE-3):63-`CL_SIZE] l2_back_inv_addr; + + // L2 Interface Back Invalidate + input an_ac_back_inv; + input an_ac_back_inv_target_bit3; + input [58:60] an_ac_back_inv_addr; + input [62:63] an_ac_back_inv_addr_lo; + + // Stcx Complete + input [0:`THREADS-1] an_ac_stcx_complete; + input [0:`THREADS-1] an_ac_stcx_pass; + + // ICBI ACK + input an_ac_icbi_ack; + input [0:1] an_ac_icbi_ack_thread; + + // Core ID + input [6:7] an_ac_coreid; + + // STCX/ICSWX CR Update + input [0:`THREADS-1] xu_lq_xer_cp_rd; + output lq_xu_cr_l2_we; + output [0:`CR_POOL_ENC+`THREADS_POOL_ENC-1] lq_xu_cr_l2_wa; + output [0:3] lq_xu_cr_l2_wd; + + // Reload Itag Complete + output stq_arb_release_itag_vld; + output [0:`ITAG_SIZE_ENC-1] stq_arb_release_itag; + output [0:`THREADS-1] stq_arb_release_tid; + + // Pervasive + + + inout vdd; + + + inout gnd; + + (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) + + input [0:`NCLK_WIDTH-1] nclk; + input sg_0; + input func_sl_thold_0_b; + input func_sl_force; + input d_mode_dc; + input delay_lclkr_dc; + input mpw1_dc_b; + input mpw2_dc_b; + + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + + input scan_in; + + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + + output scan_out; + + parameter tiup = 1'b1; + parameter tidn = 1'b0; + parameter RI = 64 - `REAL_IFAR_WIDTH; + parameter AXU_TARGET_ENC = `AXU_SPARE_ENC + `GPR_POOL_ENC + `THREADS_POOL_ENC; + + // Latches + wire rv_lq_vld_d; // input=>rv_lq_vld_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire rv_lq_vld_q; + wire rv_lq_ld_vld_d; // input=>rv_lq_ld_vld_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire rv_lq_ld_vld_q; + wire ex0_dir_rd_val_d; // input=>ex0_dir_rd_val_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire ex0_dir_rd_val_q; + + wire [0:`THREADS-1] rv0_cp_flush_q; // input=>rv0_cp_flush_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`THREADS-1] rv0_cp_flush_d; + wire [0:`THREADS-1] rv1_cp_flush_q; // input=>rv1_cp_flush_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`THREADS-1] rv1_cp_flush_d; + wire [0:`THREADS-1] rv1_i0_vld; + wire rv1_i0_flushed; + wire [0:`THREADS-1] rv1_i1_vld; + wire rv1_i1_flushed; + wire [0:`THREADS-1] ex0_i0_vld_q; // input=>rv2_i0_vld_q ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire ex0_i0_flushed_q; // input=rv2_i0_flushed ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`ITAG_SIZE_ENC-1] ex0_i0_itag_q; // input=>rv2_i0_itag_q ,act=>rv2_i0_act ,scan=>Y ,needs_sreset=>0 + wire [0:`THREADS-1] ex0_i1_vld_q; // input=>rv2_i1_vld_q ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire ex0_i1_flushed_q; // input=rv2_i1_flushed ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`ITAG_SIZE_ENC-1] ex0_i1_itag_q; // input=>rv2_i1_itag_q ,act=>rv2_i1_act ,scan=>Y ,needs_sreset=>0 + wire [0:`THREADS-1] ex1_i0_vld_q; // input=>rv2_i0_vld_q ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire ex1_i0_flushed_q; // input=rv2_i0_flushed ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`ITAG_SIZE_ENC-1] ex1_i0_itag_q; // input=>rv2_i0_itag_q ,act=>rv2_i0_act ,scan=>Y ,needs_sreset=>0 + wire [0:`THREADS-1] ex1_i1_vld_q; // input=>rv2_i1_vld_q ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire ex1_i1_flushed_q; // input=rv2_i1_flushed ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`ITAG_SIZE_ENC-1] ex1_i1_itag_q; // input=>rv2_i1_itag_q ,act=>rv2_i1_act ,scan=>Y ,needs_sreset=>0 + wire [0:`STQ_ENTRIES-1] stqe_alloc_ptr_q; // input=>stqe_alloc_ptr_d ,act=>stq_alloc_val(0) ,scan=>Y ,needs_sreset=>1 ,init=>2**(`STQ_ENTRIES-1) + wire [0:`STQ_ENTRIES-1] stqe_alloc_ptr_d; + wire [0:`STQ_ENTRIES-1] stqe_alloc_d; // input=>stqe_alloc_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`STQ_ENTRIES] stqe_alloc_q; // input=>stqe_alloc_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`STQ_ENTRIES-1] stqe_addr_val_d; // input=>stqe_addr_val_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`STQ_ENTRIES] stqe_addr_val_q; // input=>stqe_addr_val_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`STQ_ENTRIES-1] stqe_fwd_addr_val_d; // input=>stqe_fwd_addr_val_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`STQ_ENTRIES] stqe_fwd_addr_val_q; // input=>stqe_fwd_addr_val_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`STQ_ENTRIES-1] stqe_data_val_d; // input=>stqe_data_val_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`STQ_ENTRIES] stqe_data_val_q; // input=>stqe_data_val_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`STQ_ENTRIES-1] stqe_data_nxt_d; // input=>stqe_data_nxt_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`STQ_ENTRIES] stqe_data_nxt_q; // input=>stqe_data_nxt_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`STQ_ENTRIES-1] stqe_illeg_lswx_d; // input=>stqe_illeg_lswx_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`STQ_ENTRIES] stqe_illeg_lswx_q; // input=>stqe_illeg_lswx_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`STQ_ENTRIES-1] stqe_strg_noop_d; // input=>stqe_strg_noop_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`STQ_ENTRIES] stqe_strg_noop_q; // input=>stqe_strg_noop_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`STQ_ENTRIES-1] stqe_ready_sent_d; // input=>stqe_ready_sent_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`STQ_ENTRIES] stqe_ready_sent_q; // input=>stqe_ready_sent_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`STQ_ENTRIES-1] stqe_odq_resolved_d; // input=>stqe_odq_resolved_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`STQ_ENTRIES] stqe_odq_resolved_q; // input=>stqe_odq_resolved_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`STQ_ENTRIES-1] stqe_compl_rcvd_d; // input=>stqe_compl_rcvd_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`STQ_ENTRIES] stqe_compl_rcvd_q; // input=>stqe_compl_rcvd_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`STQ_ENTRIES-1] stqe_have_cp_next_d; // input=>stqe_have_cp_next_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`STQ_ENTRIES] stqe_have_cp_next_q; // input=>stqe_have_cp_next_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`STQ_ENTRIES-1] stqe_need_ready_ptr_d; // input=>stqe_need_ready_ptr_d ,act=>stqe_need_ready_act ,scan=>Y ,needs_sreset=>1 ,init=>2**(`STQ_ENTRIES-1) + wire [0:`STQ_ENTRIES] stqe_need_ready_ptr_q; // input=>stqe_need_ready_ptr_d ,act=>stqe_need_ready_act ,scan=>Y ,needs_sreset=>1 ,init=>2**(`STQ_ENTRIES-1) + wire [0:`STQ_ENTRIES-1] stqe_flushed_d; // input=>stqe_flushed_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`STQ_ENTRIES] stqe_flushed_q; // input=>stqe_flushed_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`STQ_ENTRIES-1] stqe_ack_rcvd_d; // input=>stqe_ack_rcvd_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`STQ_ENTRIES] stqe_ack_rcvd_q; // input=>stqe_ack_rcvd_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`LMQ_ENTRIES-1] stqe_lmqhit_d[0:`STQ_ENTRIES-1]; // input=>stqe_lmqhit_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 ,iterator=>i ,array=>Y + wire [0:`LMQ_ENTRIES-1] stqe_lmqhit_q[0:`STQ_ENTRIES]; // input=>stqe_lmqhit_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 ,iterator=>i ,array=>Y + wire [0:`STQ_ENTRIES-1] stqe_need_ext_ack_d; // input=>stqe_need_ext_ack_d ,act=>ex4_addr_act(i) ,scan=>Y ,needs_sreset=>1 ,iterator=>i ,array=>Y + wire [0:`STQ_ENTRIES] stqe_need_ext_ack_q; // input=>stqe_need_ext_ack_d ,act=>ex4_addr_act(i) ,scan=>Y ,needs_sreset=>1 ,iterator=>i ,array=>Y + wire [0:`STQ_ENTRIES-1] stqe_blk_loads_d; // input=>stqe_blk_loads_d ,act=>ex4_addr_act(i) ,scan=>Y ,needs_sreset=>1 ,iterator=>i ,array=>Y + wire [0:`STQ_ENTRIES] stqe_blk_loads_q; // input=>stqe_blk_loads_d ,act=>ex4_addr_act(i) ,scan=>Y ,needs_sreset=>1 ,iterator=>i ,array=>Y + wire [0:`STQ_ENTRIES-1] stqe_all_thrd_chk_d; // input=>stqe_all_thrd_chk_d ,act=>ex4_addr_act(i) ,scan=>Y ,needs_sreset=>1 ,iterator=>i ,array=>Y + wire [0:`STQ_ENTRIES] stqe_all_thrd_chk_q; // input=>stqe_all_thrd_chk_d ,act=>ex4_addr_act(i) ,scan=>Y ,needs_sreset=>1 ,iterator=>i ,array=>Y + wire [0:`ITAG_SIZE_ENC-1] stqe_itag_d[0:`STQ_ENTRIES-1]; // input=>stqe_itag_d ,act=>stqe_itag_act(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i ,array=>Y + wire [0:`ITAG_SIZE_ENC-1] stqe_itag_q[0:`STQ_ENTRIES]; // input=>stqe_itag_d ,act=>stqe_itag_act(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i ,array=>Y + wire [64-`REAL_IFAR_WIDTH:63] stqe_addr_d[0:`STQ_ENTRIES-1]; // input=>ctl_lsq_ex4_p_addr ,act=>ex4_addr_act(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i ,array=>Y + wire [64-`REAL_IFAR_WIDTH:63] stqe_addr_q[0:`STQ_ENTRIES]; // input=>ctl_lsq_ex4_p_addr ,act=>ex4_addr_act(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i ,array=>Y + wire [0:15] stqe_rotcmp_d[0:`STQ_ENTRIES-1]; // input=>stq_rotcmp, ,act=>ex3_addr_act(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i ,array=>Y + wire [0:15] stqe_rotcmp_q[0:`STQ_ENTRIES]; // input=>stq_rotcmp, ,act=>ex3_addr_act(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i ,array=>Y + wire [0:`STQ_ENTRIES-1] stqe_cline_chk_d; // input=>ctl_lsq_ex4_cline_chk ,act=>ex4_addr_act(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i + wire [0:`STQ_ENTRIES] stqe_cline_chk_q; // input=>ctl_lsq_ex4_cline_chk ,act=>ex4_addr_act(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i + wire [0:5] stqe_ttype_d[0:`STQ_ENTRIES-1]; // input=>ctl_lsq_ex5_ttype ,act=>ex5_addr_act(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i ,array=>Y + wire [0:5] stqe_ttype_q[0:`STQ_ENTRIES]; // input=>ctl_lsq_ex5_ttype ,act=>ex5_addr_act(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i ,array=>Y + wire [0:15] stqe_byte_en_d[0:`STQ_ENTRIES-1]; // input=>ctl_lsq_ex3_byte_en ,act=>ex3_addr_act(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i ,array=>Y + wire [0:15] stqe_byte_en_q[0:`STQ_ENTRIES]; // input=>ctl_lsq_ex3_byte_en ,act=>ex3_addr_act(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i ,array=>Y + wire [0:4] stqe_wimge_d[0:`STQ_ENTRIES-1]; // input=>ctl_lsq_ex4_wimge ,act=>ex4_addr_act(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i ,array=>Y + wire [0:4] stqe_wimge_q[0:`STQ_ENTRIES]; // input=>ctl_lsq_ex4_wimge ,act=>ex4_addr_act(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i ,array=>Y + wire [0:`STQ_ENTRIES-1] stqe_byte_swap_d; // input=>ctl_lsq_ex4_byte_swap ,act=>ex4_addr_act(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i + wire [0:`STQ_ENTRIES] stqe_byte_swap_q; // input=>ctl_lsq_ex4_byte_swap ,act=>ex4_addr_act(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i + wire [0:2] stqe_opsize_d[0:`STQ_ENTRIES-1]; // input=>ex4_req_opsize_q ,act=>ex4_addr_act(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i ,array=>Y + wire [0:2] stqe_opsize_q[0:`STQ_ENTRIES]; // input=>ex4_req_opsize_q ,act=>ex4_addr_act(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i ,array=>Y + wire [0:`STQ_ENTRIES-1] stqe_axu_val_d; // input=>ctl_lsq_ex5_axu_val ,act=>ex5_addr_act(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i + wire [0:`STQ_ENTRIES] stqe_axu_val_q; // input=>ctl_lsq_ex5_axu_val ,act=>ex5_addr_act(i) ,scan=>Y ,needs_sreset=>0 ,iterator=> + wire [0:`STQ_ENTRIES-1] stqe_epid_val_d; // input=>ctl_lsq_ex5_is_epid ,act=>ex5_addr_act(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i + wire [0:`STQ_ENTRIES] stqe_epid_val_q; // input=>ctl_lsq_ex5_is_epid ,act=>ex5_addr_act(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i + wire [0:3] stqe_usr_def_d[0:`STQ_ENTRIES-1]; // input=>ctl_lsq_ex5_usr_def ,act=>ex5_addr_act(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i ,array=>Y + wire [0:3] stqe_usr_def_q[0:`STQ_ENTRIES]; // input=>ctl_lsq_ex5_usr_def ,act=>ex5_addr_act(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i ,array=>Y + wire [0:`STQ_ENTRIES-1] stqe_is_store_d; // input=>ctl_lsq_ex4_is_store ,act=>ex4_addr_act(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i + wire [0:`STQ_ENTRIES] stqe_is_store_q; // input=>ctl_lsq_ex4_is_store ,act=>ex4_addr_act(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i + wire [0:`STQ_ENTRIES-1] stqe_is_sync_d; // input=>ctl_lsq_ex4_is_sync ,act=>ex4_addr_act(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i + wire [0:`STQ_ENTRIES] stqe_is_sync_q; // input=>ctl_lsq_ex4_is_sync ,act=>ex4_addr_act(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i + wire [0:`STQ_ENTRIES-1] stqe_is_resv_d; // input=>ctl_lsq_ex4_is_resv ,act=>ex4_addr_act(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i + wire [0:`STQ_ENTRIES-1] stqe_is_icswxr_d; // input=>ctl_lsq_ex4_is_icswxr ,act=>ex4_addr_act(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i + wire [0:`STQ_ENTRIES-1] stqe_is_icbi_d; // input=>ctl_lsq_ex4_is_icbi ,act=>ex4_addr_act(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i + wire [0:`STQ_ENTRIES-1] stqe_is_inval_op_d; // input=>ctl_lsq_ex4_is_inval_op ,act=>ex4_addr_act(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i + wire [0:`STQ_ENTRIES-1] stqe_dreq_val_d; // input=>ctl_lsq_ex4_dreq_val ,act=>ex4_addr_act(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i + wire [0:`STQ_ENTRIES] stqe_dreq_val_q; // input=>ctl_lsq_ex4_dreq_val ,act=>ex4_addr_act(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i + wire [0:`STQ_ENTRIES-1] stqe_has_data_d; // input=>ctl_lsq_ex4_has_data ,act=>ex4_addr_act(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i + wire [0:`STQ_ENTRIES-1] stqe_send_l2_d; // input=>ctl_lsq_ex4_send_l2 ,act=>ex4_addr_act(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i + wire [0:`STQ_ENTRIES-1] stqe_watch_clr_d; // input=>ctl_lsq_ex4_watch_clr ,act=>ex4_addr_act(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i + wire [0:`STQ_ENTRIES] stqe_is_resv_q; // input=>ctl_lsq_ex4_is_resv ,act=>ex4_addr_act(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i + wire [0:`STQ_ENTRIES] stqe_is_icswxr_q; // input=>ctl_lsq_ex4_is_icswxr ,act=>ex4_addr_act(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i + wire [0:`STQ_ENTRIES] stqe_is_icbi_q; // input=>ctl_lsq_ex4_is_icbi ,act=>ex4_addr_act(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i + wire [0:`STQ_ENTRIES] stqe_is_inval_op_q; // input=>ctl_lsq_ex4_is_inval_op ,act=>ex4_addr_act(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i + wire [0:`STQ_ENTRIES] stqe_has_data_q; // input=>ctl_lsq_ex4_has_data ,act=>ex4_addr_act(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i + wire [0:`STQ_ENTRIES] stqe_send_l2_q; // input=>ctl_lsq_ex4_send_l2 ,act=>ex4_addr_act(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i + wire [0:`STQ_ENTRIES] stqe_watch_clr_q; // input=>ctl_lsq_ex4_watch_clr ,act=>ex4_addr_act(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i + wire [0:`STQ_ENTRIES-1] stqe_lock_clr_d; // input=>ctl_lsq_ex5_lock_clr ,act=>ex5_addr_act(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i + wire [0:`STQ_ENTRIES] stqe_lock_clr_q; // input=>ctl_lsq_ex5_lock_clr ,act=>ex5_addr_act(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i + wire [0:1] stqe_l_fld_d[0:`STQ_ENTRIES-1]; // input=>ctl_lsq_ex5_l_fld ,act=>ex5_addr_act(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i ,array=>Y + wire [0:1] stqe_l_fld_q[0:`STQ_ENTRIES]; // input=>ctl_lsq_ex5_l_fld ,act=>ex5_addr_act(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i ,array=>Y + wire [0:`THREADS-1] stqe_thrd_id_d[0:`STQ_ENTRIES-1]; // input=>stqe_thrd_id_d ,act=>stqe_itag_act(i) ,scan=>Y ,needs_sreset=>1 ,iterator=>i ,array=>Y + wire [0:`THREADS-1] stqe_thrd_id_q[0:`STQ_ENTRIES]; // input=>stqe_thrd_id_d ,act=>stqe_itag_act(i) ,scan=>Y ,needs_sreset=>1 ,iterator=>i ,array=>Y + wire [0:AXU_TARGET_ENC-1] stqe_tgpr_d[0:`STQ_ENTRIES-1]; // input=>ctl_lsq_ex5_tgpr ,act=>ex5_addr_act(i) ,scan=>Y ,needs_sreset=>1 ,iterator=>i ,array=>Y + wire [0:AXU_TARGET_ENC-1] stqe_tgpr_q[0:`STQ_ENTRIES]; // input=>ctl_lsq_ex5_tgpr ,act=>ex5_addr_act(i) ,scan=>Y ,needs_sreset=>1 ,iterator=>i ,array=>Y + wire [0:1] stqe_dvc_en_d[0:`STQ_ENTRIES-1]; // input=>ctl_lsq_ex5_dvc ,act=>ex5_addr_act(i) ,scan=>Y ,needs_sreset=>1 ,iterator=>i ,array=>Y + wire [0:1] stqe_dvc_en_q[0:`STQ_ENTRIES]; // input=>ctl_lsq_ex5_dvc ,act=>ex5_addr_act(i) ,scan=>Y ,needs_sreset=>1 ,iterator=>i ,array=>Y + wire [0:3] stqe_dacrw_d[0:`STQ_ENTRIES-1]; // input=>ctl_lsq_ex5_dacrw ,act=>ex5_addr_act(i) ,scan=>Y ,needs_sreset=>1 ,iterator=>i ,array=>Y + wire [0:3] stqe_dacrw_q[0:`STQ_ENTRIES]; // input=>ctl_lsq_ex5_dacrw ,act=>ex5_addr_act(i) ,scan=>Y ,needs_sreset=>1 ,iterator=>i ,array=>Y + wire [0:1] stqe_dvcr_cmpr_q[0:`STQ_ENTRIES]; // input=>stqe_dvcr_cmpr_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 ,iterator=>i ,array=>Y + wire [0:1] stqe_dvcr_cmpr_d[0:`STQ_ENTRIES-1]; + wire [0:`STQ_ENTRIES-1] stqe_qHit_held_q; // input=>stqe_qHit_held_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 ,iterator=>i + wire [0:`STQ_ENTRIES-1] stqe_qHit_held_d; + wire [0:`STQ_ENTRIES-1] stqe_held_early_clr_d; // input=>stqe_held_early_clr_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`STQ_ENTRIES] stqe_held_early_clr_q; // input=>stqe_held_early_clr_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [(128-`STQ_DATA_SIZE):127] stqe_data1_d[0:`STQ_ENTRIES-1]; // input=>stqe_data1_d, ,act=>stqe_data_val(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i ,array=>Y + wire [(128-`STQ_DATA_SIZE):127] stqe_data1_q[0:`STQ_ENTRIES]; // input=>stqe_data1_d, ,act=>stqe_data_val(i) ,scan=>Y ,needs_sreset=>0 ,iterator=>i ,array=>Y + wire [0:`STQ_ENTRIES-1] ex4_fxu1_data_ptr_q; // input=>ex4_fxu1_data_ptr_d ,act=>ex3_fxu1_val ,scan=>Y ,needs_sreset=>0 + wire [0:`STQ_ENTRIES-1] ex4_fxu1_data_ptr_d; + wire [0:`STQ_ENTRIES-1] ex4_axu_data_ptr_q; // input=>ex4_axu_data_ptr_d ,act=>ex3_axu_val ,scan=>Y ,needs_sreset=>0 + wire [0:`STQ_ENTRIES-1] ex4_axu_data_ptr_d; + wire [(128-`STQ_DATA_SIZE):127] ex4_fu_data_q; // input=>xu_lq_axu_exp1_stq_data ,act=>ex3_axu_val ,scan=>Y ,needs_sreset=>0 + wire [0:`THREADS-1] cp_flush_q; // input=>iu_lq_cp_flush ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`THREADS-1] cp_next_val_q; // input=>iu_lq_cp_next_val ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`ITAG_SIZE_ENC-1] cp_next_itag_q[0:`THREADS-1]; // input=>iu_lq_cp_next_itag ,act=>iu_lq_cp_next_val ,scan=>Y ,needs_sreset=>0 + wire [0:`THREADS-1] cp_i0_completed_q; // input=>iu_lq_i0_completed ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`ITAG_SIZE_ENC-1] cp_i0_completed_itag_q[0:`THREADS-1]; // input=>iu_lq_i0_completed_itag ,act=>iu_lq_i0_completed ,scan=>Y ,needs_sreset=>0 + wire [0:`THREADS-1] cp_i1_completed_q; // input=>iu_lq_i1_completed ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`ITAG_SIZE_ENC-1] cp_i1_completed_itag_q[0:`THREADS-1]; // input=>iu_lq_i1_completed_itag ,act=>iu_lq_i1_completed ,scan=>Y ,needs_sreset=>0 + wire stq_cpl_need_hold_q; // input=>stq_cpl_need_hold_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire stq_cpl_need_hold_d; + wire [0:`THREADS-1] iu_lq_icbi_complete_q; // input=>iu_lq_icbi_complete ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire stq2_cmmt_flushed_q; // input=>stq1_cmmt_flushed ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire stq1_cmmt_flushed; + wire stq3_cmmt_flushed_q; // input=>stq1_cmmt_flushed ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire stq4_cmmt_flushed_q; // input=>stq1_cmmt_flushed ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire stq5_cmmt_flushed_q; // input=>stq1_cmmt_flushed ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire stq6_cmmt_flushed_q; // input=>stq1_cmmt_flushed ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire stq7_cmmt_flushed_q; // input=>stq1_cmmt_flushed ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`STQ_ENTRIES-1] stq1_cmmt_ptr_q; // input=>stq1_cmmt_ptr_d ,act=>stq1_cmmt_act ,scan=>Y ,needs_sreset=>1 ,init=>2**(`STQ_ENTRIES-1) + wire [0:`STQ_ENTRIES-1] stq1_cmmt_ptr_d; + wire [0:`STQ_ENTRIES-1] stq2_cmmt_ptr_q; // input=>stq1_cmmt_ptr_q ,act=>stq1_cmmt_act ,scan=>Y ,needs_sreset=>0 + wire [0:`STQ_ENTRIES-1] stq2_cmmt_ptr_d; + wire [0:`STQ_ENTRIES-1] stq3_cmmt_ptr_q; // input=>stq2_cmmt_ptr_q ,act=>stq2_cmmt_val_q ,scan=>Y ,needs_sreset=>0 + wire [0:`STQ_ENTRIES-1] stq3_cmmt_ptr_d; + wire [0:`STQ_ENTRIES-1] stq4_cmmt_ptr_q; // input=>stq3_cmmt_ptr_q ,act=>stq3_cmmt_val_q ,scan=>Y ,needs_sreset=>0 + wire [0:`STQ_ENTRIES-1] stq4_cmmt_ptr_d; + wire [0:`STQ_ENTRIES-1] stq5_cmmt_ptr_q; // input=>stq4_cmmt_ptr_q ,act=>stq4_cmmt_val_q ,scan=>Y ,needs_sreset=>0 + wire [0:`STQ_ENTRIES-1] stq5_cmmt_ptr_d; + wire [0:`STQ_ENTRIES-1] stq6_cmmt_ptr_q; // input=>stq5_cmmt_ptr_q ,act=>stq5_cmmt_val_q ,scan=>Y ,needs_sreset=>0 + wire [0:`STQ_ENTRIES-1] stq6_cmmt_ptr_d; + wire [0:`STQ_ENTRIES-1] stq7_cmmt_ptr_q; // input=>stq7_cmmt_ptr_d ,act=>stq6_cmmt_val_q ,scan=>Y ,needs_sreset=>0 + wire [0:`STQ_ENTRIES-1] stq7_cmmt_ptr_d; + wire stq2_cmmt_val_q; // input=>stq1_cmmt_val ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire stq1_cmmt_val; + wire stq3_cmmt_val_q; // input=>stq2_cmmt_val ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire stq2_cmmt_val; + wire stq4_cmmt_val_q; // input=>stq3_cmmt_val_q ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire stq5_cmmt_val_q; // input=>stq4_cmmt_val_q ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire stq6_cmmt_val_q; // input=>stq5_cmmt_val_q ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire stq7_cmmt_val_q; // input=>stq6_cmmt_val_q ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`THREADS-1] ext_ack_queue_v_q; // input=>ext_ack_queue_v_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`THREADS-1] ext_ack_queue_v_d; + wire [0:`THREADS-1] ext_ack_queue_sync_q; // input=>ext_ack_queue_sync_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`THREADS-1] ext_ack_queue_sync_d; + wire [0:`THREADS-1] ext_ack_queue_stcx_q; // input=>ext_ack_queue_stcx_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`THREADS-1] ext_ack_queue_stcx_d; + wire [0:`THREADS-1] ext_ack_queue_icswxr_q; // input=>ext_ack_queue_icswxr_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`THREADS-1] ext_ack_queue_icswxr_d; + wire [0:`ITAG_SIZE_ENC-1] ext_ack_queue_itag_q[0:`THREADS-1]; // input=>ext_ack_queue_itag_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`ITAG_SIZE_ENC-1] ext_ack_queue_itag_d[0:`THREADS-1]; + wire [0:`CR_POOL_ENC+`THREADS_POOL_ENC-1] ext_ack_queue_cr_wa_q[0:`THREADS-1]; // input=>ext_ack_queue_cr_wa_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`CR_POOL_ENC+`THREADS_POOL_ENC-1] ext_ack_queue_cr_wa_d[0:`THREADS-1]; + wire [0:3] ext_ack_queue_dacrw_det_q[0:`THREADS-1]; // input=>ext_ack_queue_dacrw_det_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:3] ext_ack_queue_dacrw_det_d[0:`THREADS-1]; + wire [0:`THREADS-1] ext_ack_queue_dacrw_rpt_q; // input=>ext_ack_queue_dacrw_rpt_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`THREADS-1] ext_ack_queue_dacrw_rpt_d; + wire stq2_mftgpr_val_q; // input=>stq2_mftgpr_val_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire stq2_mftgpr_val_d; + wire [0:2] stq2_rtry_cnt_q; // input=>stq2_rtry_cnt_d ,act=>stq2_rtry_cnt_act ,scan=>Y ,needs_sreset=>1 + wire [0:2] stq2_rtry_cnt_d; + wire ex5_stq_restart_q; // input=>ex5_stq_restart_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire ex5_stq_restart_d; + wire ex5_stq_restart_miss_q; // input=>ex5_stq_restart_miss_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire ex5_stq_restart_miss_d; + wire [0:`STQ_FWD_ENTRIES-2] stq_fwd_pri_mask_d; + wire [0:`STQ_FWD_ENTRIES-1] stq_fwd_pri_mask_q; + wire ex5_fwd_val_q; // input=>ex5_fwd_val_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire ex5_fwd_val_d; + wire [(128-`STQ_DATA_SIZE):127] ex5_fwd_data_q; // input=>ex5_fwd_data_d ,act=>ex4_ldreq_val_q ,scan=>Y ,needs_sreset=>1 + reg [(128-`STQ_DATA_SIZE):127] ex5_fwd_data_d; + wire [0:`STQ_ENTRIES] ex4_set_stq_q; // input=>ex3_addr_act ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`STQ_ENTRIES] ex5_set_stq_q; // input=>ex4_set_stq_q ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`THREADS-1] ex4_ldreq_val_q; // input=>ex3_ldreq_val ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`THREADS-1] ex3_ldreq_val; + wire ex4_pfetch_val_q; // input=>ex4_pfetch_val_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire ex4_pfetch_val_d; + wire [0:`THREADS-1] ex3_streq_val_q; // input=>ex2_streq_val ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`THREADS-1] ex2_streq_val; + wire [0:`THREADS-1] ex5_streq_val_q; // input=>ex4_streq_val ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`THREADS-1] ex4_streq_val; + wire [0:`THREADS-1] ex4_wchkall_val_q; // input=>ex3_wchkall_val ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`THREADS-1] ex3_wchkall_val; + wire [0:`THREADS-1] hwsync_ack_q; // input=>hwsync_ack ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`THREADS-1] hwsync_ack; + wire [0:`THREADS-1] lwsync_ack_q; // input=>lwsync_ack ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`THREADS-1] lwsync_ack; + wire icswxr_ack_q; // input=>icswxr_ack ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire icswxr_ack; + wire icswxr_ack_dly1_q; // input=>icswxr_ack_q ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`THREADS-1] local_instr_ack_q; // input=>local_instr_ack ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`THREADS-1] local_instr_ack; + wire [0:`THREADS-1] resv_ack_q; // input=>resv_ack ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`THREADS-1] resv_ack_d; + wire [0:`THREADS-1] stcx_pass_q; // input=>stcx_ack ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`THREADS-1] icbi_ack_q; // input=>icbi_ack ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`THREADS-1] icbi_ack; + wire [0:`THREADS-1] icbi_val_q; // input=>icbi_val_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`THREADS-1] icbi_val_d; + wire [RI:57] icbi_addr_q; // input=>icbi_addr_d ,act=>stq2_cmmt_val_q ,scan=>Y ,needs_sreset=>1 + reg [RI:57] icbi_addr_d; + wire ici_val_q; // input=>ici_val_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire ici_val_d; + wire [0:`THREADS-1] credit_free_q; // input=>credit_free_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`THREADS-1] credit_free_d; + wire [0:`STQ_ENTRIES-1] ex4_fwd_agecmp_q; // input=>ex3_fwd_agecmp ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`STQ_ENTRIES-1] ex4_fwd_agecmp_d; + wire [0:`ITAG_SIZE_ENC-1] ex3_req_itag_q; // input=>ctl_lsq_ex2_itag ,act=>tiup ,scan=>Y ,needs_sreset=>0 + wire [0:`ITAG_SIZE_ENC-1] ex4_req_itag_q; // input=>ex3_req_itag_q ,act=>tiup ,scan=>Y ,needs_sreset=>0 + wire [0:15] ex4_req_byte_en_q; // input=>ctl_lsq_ex3_byte_en ,act=>ex3_req_act ,scan=>Y ,needs_sreset=>1 + wire [58:63] ex4_req_p_addr_l_q; // input=>ctl_lsq_ex3_p_addr ,act=>ex3_req_act ,scan=>Y ,needs_sreset=>1 + wire [0:2] ex4_req_opsize_q; // input=>ctl_lsq_ex3_opsize ,act=>ex3_req_act ,scan=>Y ,needs_sreset=>1 + wire ex4_req_algebraic_q; // input=>ctl_lsq_ex3_algebraic ,act=>ex3_req_act ,scan=>Y ,needs_sreset=>1 + wire [0:`THREADS-1] ex3_req_thrd_id_q; // input=>ctl_lsq_ex2_thrd_id ,act=>ex3_req_act ,scan=>Y ,needs_sreset=>1 + wire [0:`THREADS-1] ex4_req_thrd_id_q; // input=>ex3_req_thrd_id_q ,act=>ex3_req_act ,scan=>Y ,needs_sreset=>1 + wire [0:`THREADS-1] ex5_req_thrd_id_q; // input=>ex4_req_thrd_id_q ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`THREADS-1] thrd_held_d; // input=>thrd_held_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`THREADS-1] thrd_held_q; + wire [0:`THREADS-1] rv0_cr_hole_q; // input=>rv0_cr_hole_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`THREADS-1] rv0_cr_hole_d; + wire [0:`THREADS-1] rv1_cr_hole_q; // input=>rv1_cr_hole_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`THREADS-1] rv1_cr_hole_d; + wire [0:`THREADS-1] ex0_cr_hole_q; // input=>ex0_cr_hole_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`THREADS-1] ex0_cr_hole_d; + wire [0:`THREADS-1] cr_ack_q; // input=>cr_ack_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`THREADS-1] cr_ack_d; + wire sync_ack_save_q; // input=>sync_ack_save ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire sync_ack_save_d; + wire cr_we_q; // input=>cr_we_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire cr_we_d; + wire [0:`CR_POOL_ENC+`THREADS_POOL_ENC-1] cr_wa_q; // input=>cr_wa_d ,act=>cr_we_d ,scan=>Y ,needs_sreset=>0 + reg [0:`CR_POOL_ENC+`THREADS_POOL_ENC-1] cr_wa_d; + wire [0:3] cr_wd_q; // input=>cr_wd_d ,act=>cr_we_d ,scan=>Y ,needs_sreset=>0 + wire [0:3] cr_wd_d; + wire [0:`THREADS-1] stcx_thrd_fail_q; // input=>stcx_thrd_fail_d ,act=>tiup ,scan=>Y ,needs_sreset=>0 + wire [0:`THREADS-1] stcx_thrd_fail_d; + wire stq3_cmmt_attmpt_q; // input=>stq3_cmmt_attmpt_d ,act=>tiup ,scan=>Y ,needs_sreset=>0 + wire stq3_cmmt_attmpt_d; + wire stq_need_hole_q; // input=>stq_need_hole_d ,act=>tiup ,scan=>Y ,needs_sreset=>0 + wire stq_need_hole_d; + wire [0:`THREADS-1] icswxr_thrd_busy_q; // input=>icswxr_thrd_busy_d ,act=>tiup ,scan=>Y ,needs_sreset=>0 + wire [0:`THREADS-1] icswxr_thrd_busy_d; + wire [0:`THREADS-1] icswxr_thrd_nbusy_q; // input=>icswxr_thrd_nbusy_d ,act=>tiup ,scan=>Y ,needs_sreset=>0 + wire [0:`THREADS-1] icswxr_thrd_nbusy_d; + wire [0:`THREADS-1] any_ack_hold_q; // input=>any_ack_hold_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`THREADS-1] any_ack_hold_d; + wire [0:`THREADS-1] any_ack_val_ok_q; // input=>any_ack_val_ok_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`THREADS-1] any_ack_val_ok_d; + wire [0:`THREADS-1] arb_release_itag_vld_q; // input=>arb_release_itag_vld ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`THREADS-1] arb_release_itag_vld_d; + wire spr_xucr0_cls_q; // input=>spr_xucr0_cls_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire spr_xucr0_cls_d; + wire spr_iucr0_icbi_ack_q; // input=>spr_iucr0_icbi_ack_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire spr_iucr0_icbi_ack_d; + wire spr_lsucr0_dfwd_q ; // input=>spr_lsucr0_dfwd_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire spr_lsucr0_dfwd_d ; + wire ex5_thrd_match_restart_q; // input=>ex5_thrd_match_restart_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire ex5_thrd_match_restart_d; + wire ex6_thrd_match_restart_q; // input=>ex6_thrd_match_restart_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire ex6_thrd_match_restart_d; + wire ex5_thrd_nomatch_restart_q; // input=>ex5_thrd_nomatch_restart_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire ex5_thrd_nomatch_restart_d; + wire ex6_thrd_nomatch_restart_q; // input=>ex6_thrd_nomatch_restart_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire ex6_thrd_nomatch_restart_d; + wire [0:`STQ_ENTRIES-1] ex5_older_ldmiss_d; // input=>ex5_older_ldmiss_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`STQ_ENTRIES] ex5_older_ldmiss_q; // input=>ex5_older_ldmiss_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire ex4_fxu1_illeg_lswx_q; // input=>ex4_fxu1_illeg_lswx_d ,act=>ex3_fxu0_val ,scan=>Y ,needs_sreset=>0 + wire ex4_fxu1_illeg_lswx_d; + wire ex4_fxu1_strg_noop_q; // input=>ex4_fxu1_strg_noop_d ,act=>ex3_fxu0_val ,scan=>Y ,needs_sreset=>0 + wire ex4_fxu1_strg_noop_d; + wire [0:`THREADS-1] ex3_fxu1_val_q; // input=>ex3_fxu1_val_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`THREADS-1] ex3_fxu1_val_d; + wire [0:`ITAG_SIZE_ENC-1] ex3_fxu1_itag_q; // input=>ex3_fxu1_itag_d ,act=>ex2_fxu1_val ,scan=>Y ,needs_sreset=>0 + wire [0:`ITAG_SIZE_ENC-1] ex3_fxu1_itag_d; + wire [0:((2**`GPR_WIDTH_ENC)/8)-1] ex3_fxu1_dvc1_cmp_q; // input=>ex3_fxu1_dvc1_cmp_d ,act=>ex2_fxu1_val ,scan=>Y ,needs_sreset=>0 + wire [0:((2**`GPR_WIDTH_ENC)/8)-1] ex3_fxu1_dvc1_cmp_d; + wire [0:((2**`GPR_WIDTH_ENC)/8)-1] ex3_fxu1_dvc2_cmp_q; // input=>ex3_fxu1_dvc2_cmp_d ,act=>ex2_fxu1_val ,scan=>Y ,needs_sreset=>0 + wire [0:((2**`GPR_WIDTH_ENC)/8)-1] ex3_fxu1_dvc2_cmp_d; + wire [0:`THREADS-1] ex4_fxu1_val_q; // input=>ex4_fxu1_val_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`THREADS-1] ex4_fxu1_val_d; + wire [0:`THREADS-1] ex3_axu_val_q; // input=>ex3_axu_val_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`THREADS-1] ex3_axu_val_d; + wire [0:`ITAG_SIZE_ENC-1] ex3_axu_itag_q; // input=>ex3_axu_itag_d ,act=>ex2_axu_val ,scan=>Y ,needs_sreset=>0 + wire [0:`ITAG_SIZE_ENC-1] ex3_axu_itag_d; + wire [0:`THREADS-1] ex4_axu_val_q; // input=>ex4_axu_val_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`THREADS-1] ex4_axu_val_d; + wire [0:`STQ_ENTRIES-1] ex5_qHit_set_oth_d; // input=>ex5_qHit_set_oth_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`STQ_ENTRIES] ex5_qHit_set_oth_q; // input=>ex5_qHit_set_oth_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`STQ_ENTRIES-1] ex5_qHit_set_miss_q; // input=>ex5_qHit_set_miss_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`STQ_ENTRIES-1] ex5_qHit_set_miss_d; + wire [0:`THREADS-1] iu_icbi_ack_q; // input=>iu_icbi_ack_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`THREADS-1] iu_icbi_ack_d; + wire [0:`THREADS-1] l2_icbi_ack_q; // input=>l2_icbi_ack_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`THREADS-1] l2_icbi_ack_d; + wire rv1_binv_val_q; // input=>rv1_binv_val_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire rv1_binv_val_d; + wire ex0_binv_val_q; // input=>ex0_binv_val_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire ex0_binv_val_d; + wire ex1_binv_val_q; // input=>ex1_binv_val_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire ex1_binv_val_d; + wire ex2_binv_val_q; // input=>ex2_binv_val_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire ex2_binv_val_d; + wire ex3_binv_val_q; // input=>ex3_binv_val_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire ex3_binv_val_d; + wire [64-(`DC_SIZE-3):63-`CL_SIZE] rv1_binv_addr_q; // input=>rv1_binv_addr_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [64-(`DC_SIZE-3):63-`CL_SIZE] rv1_binv_addr_d; + wire [64-(`DC_SIZE-3):63-`CL_SIZE] ex0_binv_addr_q; // input=>ex0_binv_addr_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [64-(`DC_SIZE-3):63-`CL_SIZE] ex0_binv_addr_d; + wire [64-(`DC_SIZE-3):63-`CL_SIZE] ex1_binv_addr_q; // input=>ex1_binv_addr_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [64-(`DC_SIZE-3):63-`CL_SIZE] ex1_binv_addr_d; + wire [64-(`DC_SIZE-3):63-`CL_SIZE] ex2_binv_addr_q; // input=>ex2_binv_addr_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [64-(`DC_SIZE-3):63-`CL_SIZE] ex2_binv_addr_d; + wire [64-(`DC_SIZE-3):63-`CL_SIZE] ex3_binv_addr_q; // input=>ex3_binv_addr_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [64-(`DC_SIZE-3):63-`CL_SIZE] ex3_binv_addr_d; + wire stq2_binv_blk_cclass_q; // input=>stq2_binv_blk_cclass_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire stq2_binv_blk_cclass_d; + wire stq2_ici_val_q; // input=>stq2_ici_val_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire stq2_ici_val_d; + wire stq4_xucr0_cul_q; // input=>stq4_xucr0_cul_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire stq4_xucr0_cul_d; + wire stq2_reject_dci_q; // input=>stq2_reject_dci_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire stq2_reject_dci_d; + wire stq3_cmmt_reject_q; // input=>stq3_cmmt_reject_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire stq3_cmmt_reject_d; + wire stq2_dci_val_q; // input=>stq2_dci_val_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire stq2_dci_val_d; + wire stq3_cmmt_dci_val_q; // input=>stq3_cmmt_dci_val_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire stq3_cmmt_dci_val_d; + wire stq4_cmmt_dci_val_q; // input=>stq4_cmmt_dci_val_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire stq4_cmmt_dci_val_d; + wire stq5_cmmt_dci_val_q; // input=>stq5_cmmt_dci_val_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire stq5_cmmt_dci_val_d; + wire [0:`STQ_ENTRIES-1] ex3_nxt_oldest_q; // input=>ex3_nxt_oldest_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`STQ_ENTRIES-1] ex3_nxt_oldest_d; + wire [0:`STQ_ENTRIES-1] stq_tag_val_q; // input=>stq_tag_val_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`STQ_ENTRIES-1] stq_tag_val_d; + wire [0:`STQ_ENTRIES-1] stq_tag_ptr_q[0:`STQ_ENTRIES-1]; // input=>stq_tag_ptr_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`STQ_ENTRIES-1] stq_tag_ptr_d[0:`STQ_ENTRIES-1]; + wire [0:`STQ_ENTRIES_ENC-1] stq4_cmmt_tag_q; // input=>stq4_cmmt_tag_d ,act=>stq3_cmmt_val_q ,scan=>Y ,needs_sreset=>1 + wire [0:`STQ_ENTRIES_ENC-1] stq4_cmmt_tag_d; + wire [0:`THREADS-1] dbg_int_en_q; // input=>dbg_int_en_d ,act=>tiup ,scan=>Y ,needs_sreset=>1 + wire [0:`THREADS-1] dbg_int_en_d; + + + parameter rv_lq_vld_offset = 0; + parameter rv_lq_ld_vld_offset = rv_lq_vld_offset + 1; + parameter ex0_dir_rd_val_offset = rv_lq_ld_vld_offset + 1; + parameter rv0_cp_flush_offset = ex0_dir_rd_val_offset + 1; + parameter rv1_cp_flush_offset = rv0_cp_flush_offset + `THREADS; + parameter ex0_i0_vld_offset = rv1_cp_flush_offset + `THREADS; + parameter ex0_i0_flushed_offset = ex0_i0_vld_offset + `THREADS; + parameter ex0_i0_itag_offset = ex0_i0_flushed_offset + 1; + parameter ex0_i1_vld_offset = ex0_i0_itag_offset + `ITAG_SIZE_ENC; + parameter ex0_i1_flushed_offset = ex0_i1_vld_offset + `THREADS; + parameter ex0_i1_itag_offset = ex0_i1_flushed_offset + 1; + parameter ex1_i0_vld_offset = ex0_i1_itag_offset + `ITAG_SIZE_ENC; + parameter ex1_i0_flushed_offset = ex1_i0_vld_offset + `THREADS; + parameter ex1_i0_itag_offset = ex1_i0_flushed_offset + 1; + parameter ex1_i1_vld_offset = ex1_i0_itag_offset + `ITAG_SIZE_ENC; + parameter ex1_i1_flushed_offset = ex1_i1_vld_offset + `THREADS; + parameter ex1_i1_itag_offset = ex1_i1_flushed_offset + 1; + parameter stqe_alloc_ptr_offset = ex1_i1_itag_offset + `ITAG_SIZE_ENC; + parameter stqe_alloc_offset = stqe_alloc_ptr_offset + `STQ_ENTRIES; + parameter stqe_addr_val_offset = stqe_alloc_offset + `STQ_ENTRIES; + parameter stqe_fwd_addr_val_offset = stqe_addr_val_offset + `STQ_ENTRIES; + parameter stqe_rotcmp_offset = stqe_fwd_addr_val_offset + `STQ_ENTRIES; + parameter stqe_data_val_offset = stqe_rotcmp_offset + 16 * `STQ_ENTRIES; + parameter stqe_data_nxt_offset = stqe_data_val_offset + `STQ_ENTRIES; + parameter stqe_illeg_lswx_offset = stqe_data_nxt_offset + `STQ_ENTRIES; + parameter stqe_strg_noop_offset = stqe_illeg_lswx_offset + `STQ_ENTRIES; + parameter stqe_ready_sent_offset = stqe_strg_noop_offset + `STQ_ENTRIES; + parameter stqe_odq_resolved_offset = stqe_ready_sent_offset + `STQ_ENTRIES; + parameter stqe_compl_rcvd_offset = stqe_odq_resolved_offset + `STQ_ENTRIES; + parameter stqe_have_cp_next_offset = stqe_compl_rcvd_offset + `STQ_ENTRIES; + parameter stqe_need_ready_ptr_offset = stqe_have_cp_next_offset + `STQ_ENTRIES; + parameter stqe_flushed_offset = stqe_need_ready_ptr_offset + `STQ_ENTRIES; + parameter stqe_ack_rcvd_offset = stqe_flushed_offset + `STQ_ENTRIES; + parameter stqe_lmqhit_offset = stqe_ack_rcvd_offset + `STQ_ENTRIES; + parameter stqe_need_ext_ack_offset = stqe_lmqhit_offset + `LMQ_ENTRIES * `STQ_ENTRIES; + parameter stqe_blk_loads_offset = stqe_need_ext_ack_offset + `STQ_ENTRIES; + parameter stqe_all_thrd_chk_offset = stqe_blk_loads_offset + `STQ_ENTRIES; + parameter stqe_itag_offset = stqe_all_thrd_chk_offset + `STQ_ENTRIES; + parameter stqe_addr_offset = stqe_itag_offset + `ITAG_SIZE_ENC * `STQ_ENTRIES; + parameter stqe_cline_chk_offset = stqe_addr_offset + `REAL_IFAR_WIDTH * `STQ_ENTRIES; + parameter stqe_ttype_offset = stqe_cline_chk_offset + `STQ_ENTRIES; + parameter stqe_byte_en_offset = stqe_ttype_offset + 6 * `STQ_ENTRIES; + parameter stqe_byte_swap_offset = stqe_byte_en_offset + 16 * `STQ_ENTRIES; + parameter stqe_wimge_offset = stqe_byte_swap_offset + `STQ_ENTRIES; + parameter stqe_opsize_offset = stqe_wimge_offset + 5 * `STQ_ENTRIES; + parameter stqe_axu_val_offset = stqe_opsize_offset + 3 * `STQ_ENTRIES; + parameter stqe_epid_val_offset = stqe_axu_val_offset + `STQ_ENTRIES; + parameter stqe_usr_def_offset = stqe_epid_val_offset + `STQ_ENTRIES; + parameter stqe_is_store_offset = stqe_usr_def_offset + 4 * `STQ_ENTRIES; + parameter stqe_is_sync_offset = stqe_is_store_offset + `STQ_ENTRIES; + parameter stqe_is_resv_offset = stqe_is_sync_offset + `STQ_ENTRIES; + parameter stqe_is_icswxr_offset = stqe_is_resv_offset + `STQ_ENTRIES; + parameter stqe_is_icbi_offset = stqe_is_icswxr_offset + `STQ_ENTRIES; + parameter stqe_is_inval_op_offset = stqe_is_icbi_offset + `STQ_ENTRIES; + parameter stqe_dreq_val_offset = stqe_is_inval_op_offset + `STQ_ENTRIES; + parameter stqe_has_data_offset = stqe_dreq_val_offset + `STQ_ENTRIES; + parameter stqe_send_l2_offset = stqe_has_data_offset + `STQ_ENTRIES; + parameter stqe_lock_clr_offset = stqe_send_l2_offset + `STQ_ENTRIES; + parameter stqe_watch_clr_offset = stqe_lock_clr_offset + `STQ_ENTRIES; + parameter stqe_l_fld_offset = stqe_watch_clr_offset + `STQ_ENTRIES; + parameter stqe_thrd_id_offset = stqe_l_fld_offset + 2 * `STQ_ENTRIES; + parameter stqe_tgpr_offset = stqe_thrd_id_offset + `THREADS * `STQ_ENTRIES; + parameter stqe_dvc_en_offset = stqe_tgpr_offset + AXU_TARGET_ENC * `STQ_ENTRIES; + parameter stqe_dacrw_offset = stqe_dvc_en_offset + 2 * `STQ_ENTRIES; + parameter stqe_dvcr_cmpr_offset = stqe_dacrw_offset + 4 * `STQ_ENTRIES; + parameter stqe_qHit_held_offset = stqe_dvcr_cmpr_offset + 2 * `STQ_ENTRIES; + parameter stqe_held_early_clr_offset = stqe_qHit_held_offset + `STQ_ENTRIES; + parameter stqe_data1_offset = stqe_held_early_clr_offset + `STQ_ENTRIES; + parameter ex4_fxu1_data_ptr_offset = stqe_data1_offset + `STQ_DATA_SIZE * `STQ_ENTRIES; + parameter ex4_axu_data_ptr_offset = ex4_fxu1_data_ptr_offset + `STQ_ENTRIES; + parameter ex4_fu_data_offset = ex4_axu_data_ptr_offset + `STQ_ENTRIES; + parameter cp_flush_offset = ex4_fu_data_offset + `STQ_DATA_SIZE; + parameter cp_next_val_offset = cp_flush_offset + `THREADS; + parameter cp_next_itag_offset = cp_next_val_offset + `THREADS; + parameter cp_i0_completed_offset = cp_next_itag_offset + `THREADS * `ITAG_SIZE_ENC; + parameter cp_i0_completed_itag_offset = cp_i0_completed_offset + `THREADS; + parameter cp_i1_completed_offset = cp_i0_completed_itag_offset + `THREADS * `ITAG_SIZE_ENC; + parameter cp_i1_completed_itag_offset = cp_i1_completed_offset + `THREADS; + parameter stq_cpl_need_hold_offset = cp_i1_completed_itag_offset + `THREADS * `ITAG_SIZE_ENC; + parameter iu_lq_icbi_complete_offset = stq_cpl_need_hold_offset + 1; + parameter iu_icbi_ack_offset = iu_lq_icbi_complete_offset + `THREADS; + parameter l2_icbi_ack_offset = iu_icbi_ack_offset + `THREADS; + parameter rv1_binv_val_offset = l2_icbi_ack_offset + `THREADS; + parameter ex0_binv_val_offset = rv1_binv_val_offset + 1; + parameter ex1_binv_val_offset = ex0_binv_val_offset + 1; + parameter ex2_binv_val_offset = ex1_binv_val_offset + 1; + parameter ex3_binv_val_offset = ex2_binv_val_offset + 1; + parameter rv1_binv_addr_offset = ex3_binv_val_offset + 1; + parameter ex0_binv_addr_offset = rv1_binv_addr_offset + ((63-`CL_SIZE)-(64-(`DC_SIZE-3))+1); + parameter ex1_binv_addr_offset = ex0_binv_addr_offset + ((63-`CL_SIZE)-(64-(`DC_SIZE-3))+1); + parameter ex2_binv_addr_offset = ex1_binv_addr_offset + ((63-`CL_SIZE)-(64-(`DC_SIZE-3))+1); + parameter ex3_binv_addr_offset = ex2_binv_addr_offset + ((63-`CL_SIZE)-(64-(`DC_SIZE-3))+1); + parameter stq2_binv_blk_cclass_offset = ex3_binv_addr_offset + ((63-`CL_SIZE)-(64-(`DC_SIZE-3))+1); + parameter stq2_ici_val_offset = stq2_binv_blk_cclass_offset + 1; + parameter stq4_xucr0_cul_offset = stq2_ici_val_offset + 1; + parameter stq2_reject_dci_offset = stq4_xucr0_cul_offset + 1; + parameter stq3_cmmt_reject_offset = stq2_reject_dci_offset + 1; + parameter stq2_dci_val_offset = stq3_cmmt_reject_offset + 1; + parameter stq3_cmmt_dci_val_offset = stq2_dci_val_offset + 1; + parameter stq4_cmmt_dci_val_offset = stq3_cmmt_dci_val_offset + 1; + parameter stq5_cmmt_dci_val_offset = stq4_cmmt_dci_val_offset + 1; + parameter stq2_cmmt_flushed_offset = stq5_cmmt_dci_val_offset + 1; + parameter stq3_cmmt_flushed_offset = stq2_cmmt_flushed_offset + 1; + parameter stq4_cmmt_flushed_offset = stq3_cmmt_flushed_offset + 1; + parameter stq5_cmmt_flushed_offset = stq4_cmmt_flushed_offset + 1; + parameter stq6_cmmt_flushed_offset = stq5_cmmt_flushed_offset + 1; + parameter stq7_cmmt_flushed_offset = stq6_cmmt_flushed_offset + 1; + parameter stq1_cmmt_ptr_offset = stq7_cmmt_flushed_offset + 1; + parameter stq2_cmmt_ptr_offset = stq1_cmmt_ptr_offset + `STQ_ENTRIES; + parameter stq3_cmmt_ptr_offset = stq2_cmmt_ptr_offset + `STQ_ENTRIES; + parameter stq4_cmmt_ptr_offset = stq3_cmmt_ptr_offset + `STQ_ENTRIES; + parameter stq5_cmmt_ptr_offset = stq4_cmmt_ptr_offset + `STQ_ENTRIES; + parameter stq6_cmmt_ptr_offset = stq5_cmmt_ptr_offset + `STQ_ENTRIES; + parameter stq7_cmmt_ptr_offset = stq6_cmmt_ptr_offset + `STQ_ENTRIES; + parameter stq2_cmmt_val_offset = stq7_cmmt_ptr_offset + `STQ_ENTRIES; + parameter stq3_cmmt_val_offset = stq2_cmmt_val_offset + 1; + parameter stq4_cmmt_val_offset = stq3_cmmt_val_offset + 1; + parameter stq5_cmmt_val_offset = stq4_cmmt_val_offset + 1; + parameter stq6_cmmt_val_offset = stq5_cmmt_val_offset + 1; + parameter stq7_cmmt_val_offset = stq6_cmmt_val_offset + 1; + parameter ext_ack_queue_v_offset = stq7_cmmt_val_offset + 1; + parameter ext_ack_queue_sync_offset = ext_ack_queue_v_offset + `THREADS; + parameter ext_ack_queue_stcx_offset = ext_ack_queue_sync_offset + `THREADS; + parameter ext_ack_queue_icswxr_offset = ext_ack_queue_stcx_offset + `THREADS; + parameter ext_ack_queue_itag_offset = ext_ack_queue_icswxr_offset + `THREADS; + parameter ext_ack_queue_cr_wa_offset = ext_ack_queue_itag_offset + `ITAG_SIZE_ENC * `THREADS; + parameter ext_ack_queue_dacrw_det_offset = ext_ack_queue_cr_wa_offset + (`CR_POOL_ENC+`THREADS_POOL_ENC) * `THREADS; + parameter ext_ack_queue_dacrw_rpt_offset = ext_ack_queue_dacrw_det_offset + 4 * `THREADS; + parameter stq2_mftgpr_val_offset = ext_ack_queue_dacrw_rpt_offset + `THREADS; + parameter stq2_rtry_cnt_offset = stq2_mftgpr_val_offset + 1; + parameter ex5_stq_restart_offset = stq2_rtry_cnt_offset + 3; + parameter ex5_stq_restart_miss_offset = ex5_stq_restart_offset + 1; + parameter stq_fwd_pri_mask_offset = ex5_stq_restart_miss_offset + 1; + parameter ex5_fwd_val_offset = stq_fwd_pri_mask_offset + (`STQ_FWD_ENTRIES-1); + parameter ex5_fwd_data_offset = ex5_fwd_val_offset + 1; + parameter ex4_set_stq_offset = ex5_fwd_data_offset + `STQ_DATA_SIZE; + parameter ex5_set_stq_offset = ex4_set_stq_offset + `STQ_ENTRIES; + parameter ex4_ldreq_val_offset = ex5_set_stq_offset + `STQ_ENTRIES; + parameter ex4_pfetch_val_offset = ex4_ldreq_val_offset + `THREADS; + parameter ex3_streq_val_offset = ex4_pfetch_val_offset + 1; + parameter ex5_streq_val_offset = ex3_streq_val_offset + `THREADS; + parameter ex4_wchkall_val_offset = ex5_streq_val_offset + `THREADS; + parameter hwsync_ack_offset = ex4_wchkall_val_offset + `THREADS; + parameter lwsync_ack_offset = hwsync_ack_offset + `THREADS; + parameter icswxr_ack_offset = lwsync_ack_offset + `THREADS; + parameter icswxr_ack_dly1_offset = icswxr_ack_offset + 1; + parameter local_instr_ack_offset = icswxr_ack_dly1_offset + 1; + parameter resv_ack_offset = local_instr_ack_offset + `THREADS; + parameter stcx_pass_offset = resv_ack_offset + `THREADS; + parameter icbi_ack_offset = stcx_pass_offset + `THREADS; + parameter icbi_val_offset = icbi_ack_offset + `THREADS; + parameter icbi_addr_offset = icbi_val_offset + `THREADS; + parameter ici_val_offset = icbi_addr_offset + (57-RI+1); + parameter credit_free_offset = ici_val_offset + 1; + parameter ex4_fwd_agecmp_offset = credit_free_offset + `THREADS; + parameter ex3_req_itag_offset = ex4_fwd_agecmp_offset + `STQ_ENTRIES; + parameter ex4_req_itag_offset = ex3_req_itag_offset + `ITAG_SIZE_ENC; + parameter ex4_req_byte_en_offset = ex4_req_itag_offset + `ITAG_SIZE_ENC; + parameter ex4_req_p_addr_l_offset = ex4_req_byte_en_offset + 16; + parameter ex4_req_opsize_offset = ex4_req_p_addr_l_offset + 6; + parameter ex4_req_algebraic_offset = ex4_req_opsize_offset + 3; + parameter ex3_req_thrd_id_offset = ex4_req_algebraic_offset + 1; + parameter ex4_req_thrd_id_offset = ex3_req_thrd_id_offset + `THREADS; + parameter ex5_req_thrd_id_offset = ex4_req_thrd_id_offset + `THREADS; + parameter thrd_held_offset = ex5_req_thrd_id_offset + `THREADS; + parameter rv0_cr_hole_offset = thrd_held_offset + `THREADS; + parameter rv1_cr_hole_offset = rv0_cr_hole_offset + `THREADS; + parameter ex0_cr_hole_offset = rv1_cr_hole_offset + `THREADS; + parameter cr_ack_offset = ex0_cr_hole_offset + `THREADS; + parameter sync_ack_save_offset = cr_ack_offset + `THREADS; + parameter cr_we_offset = sync_ack_save_offset + 1; + parameter cr_wa_offset = cr_we_offset + 1; + parameter cr_wd_offset = cr_wa_offset + (`CR_POOL_ENC+`THREADS_POOL_ENC-1+1); + parameter stcx_thrd_fail_offset = cr_wd_offset + 4; + parameter icswxr_thrd_busy_offset = stcx_thrd_fail_offset + `THREADS; + parameter icswxr_thrd_nbusy_offset = icswxr_thrd_busy_offset + `THREADS; + parameter stq3_cmmt_attmpt_offset = icswxr_thrd_nbusy_offset + `THREADS; + parameter stq_need_hole_offset = stq3_cmmt_attmpt_offset + 1; + parameter any_ack_hold_offset = stq_need_hole_offset + 1; + parameter any_ack_val_ok_offset = any_ack_hold_offset + `THREADS; + parameter arb_release_itag_vld_offset = any_ack_val_ok_offset + `THREADS; + parameter spr_xucr0_cls_offset = arb_release_itag_vld_offset + `THREADS; + parameter spr_iucr0_icbi_ack_offset = spr_xucr0_cls_offset + 1; + parameter spr_lsucr0_dfwd_offset = spr_iucr0_icbi_ack_offset + 1; + parameter ex5_thrd_match_restart_offset = spr_lsucr0_dfwd_offset + 1; + parameter ex6_thrd_match_restart_offset = ex5_thrd_match_restart_offset + 1; + parameter ex5_thrd_nomatch_restart_offset = ex6_thrd_match_restart_offset + 1; + parameter ex6_thrd_nomatch_restart_offset = ex5_thrd_nomatch_restart_offset + 1; + parameter ex5_older_ldmiss_offset = ex6_thrd_nomatch_restart_offset + 1; + + parameter ex4_fxu1_illeg_lswx_offset = ex5_older_ldmiss_offset + `STQ_ENTRIES; + parameter ex4_fxu1_strg_noop_offset = ex4_fxu1_illeg_lswx_offset + 1; + parameter ex3_fxu1_val_offset = ex4_fxu1_strg_noop_offset + 1; + parameter ex3_fxu1_itag_offset = ex3_fxu1_val_offset + `THREADS; + parameter ex3_fxu1_dvc1_cmp_offset = ex3_fxu1_itag_offset + `ITAG_SIZE_ENC; + parameter ex3_fxu1_dvc2_cmp_offset = ex3_fxu1_dvc1_cmp_offset + (((2**`GPR_WIDTH_ENC)/8)-1-0+1); + parameter ex4_fxu1_val_offset = ex3_fxu1_dvc2_cmp_offset + (((2**`GPR_WIDTH_ENC)/8)-1-0+1); + parameter ex3_axu_val_offset = ex4_fxu1_val_offset + `THREADS; + parameter ex3_axu_itag_offset = ex3_axu_val_offset + `THREADS; + parameter ex4_axu_val_offset = ex3_axu_itag_offset + `ITAG_SIZE_ENC; + parameter ex5_qHit_set_oth_offset = ex4_axu_val_offset + `THREADS; + parameter ex5_qHit_set_miss_offset = ex5_qHit_set_oth_offset + `STQ_ENTRIES; + parameter ex3_nxt_oldest_offset = ex5_qHit_set_miss_offset + `STQ_ENTRIES; + parameter stq_tag_val_offset = ex3_nxt_oldest_offset + `STQ_ENTRIES; + parameter stq_tag_ptr_offset = stq_tag_val_offset + `STQ_ENTRIES; + parameter stq4_cmmt_tag_offset = stq_tag_ptr_offset + `STQ_ENTRIES * `STQ_ENTRIES; + parameter dbg_int_en_offset = stq4_cmmt_tag_offset + `STQ_ENTRIES_ENC; + parameter scan_right = dbg_int_en_offset + `THREADS; + + + + wire [0:scan_right-1] siv; + wire [0:scan_right-1] sov; + + // Signals + wire spr_xucr0_64cls; + wire a2_icbi_ack_en; + wire ex3_req_act; + wire [0:8] stqe_state[0:`STQ_ENTRIES-1]; + reg [0:`STQ_ENTRIES] set_stqe_odq_resolved; + wire [0:`STQ_ENTRIES-1] stqe_ready_state; + wire [0:`STQ_ENTRIES-1] stqe_ready_ctl_act; + wire [0:`STQ_ENTRIES-1] stqe_ready_dat_act; + wire [0:`STQ_ENTRIES] stq7_entry_delete; + wire stq_push_down; + wire [0:`STQ_ENTRIES-1] stqe_need_ready_ptr_r1; + wire [0:`STQ_ENTRIES-1] stqe_need_ready_ptr_l1; + wire [0:1] stqe_need_ready_ptr_sel; + wire [0:`STQ_ENTRIES-1] stqe_need_ready; + wire [0:`STQ_ENTRIES-1] stqe_need_ready_blk; + wire [0:`STQ_ENTRIES-1] stqe_need_ready_rpt; + wire [0:`STQ_ENTRIES] cp_i0_itag_cmp; + wire [0:`STQ_ENTRIES] cp_i1_itag_cmp; + wire rv1_i0_drop_req; + wire rv1_i1_drop_req; + wire rv1_i0_act; + wire rv1_i1_act; + wire ex0_i0_act; + wire ex0_i1_act; + wire stq_alloc_sel; + wire stq_act; + wire [0:1] stq_alloc_val; + wire [0:1] stq_alloc_flushed; + wire [0:`ITAG_SIZE_ENC-1] stqe_alloc_itag0; + wire [0:`ITAG_SIZE_ENC-1] stqe_alloc_itag1; + wire [0:`THREADS-1] stq_alloc_thrd_id0; + wire [0:`THREADS-1] stq_alloc_thrd_id1; + wire [0:`STQ_ENTRIES-1] stqe_alloc_ptr_r1; + wire [0:`STQ_ENTRIES-1] stqe_alloc_ptr_r2; + wire [0:`STQ_ENTRIES-1] stqe_alloc_ptr_l1; + wire [0:`STQ_ENTRIES-1] stqe_alloc_i0_wrt_ptr; + wire [0:`STQ_ENTRIES-1] stqe_alloc_i1_wrt_ptr; + wire [0:2] stqe_alloc_ptr_sel; + wire [0:`STQ_ENTRIES-1] stqe_wrt_new; + wire stq1_cmmt_act; + wire [0:`STQ_ENTRIES-1] stq1_cmmt_ptr_r1; + wire [0:`STQ_ENTRIES-1] stq1_cmmt_ptr_l1; + wire [0:2] stq1_cmmt_ptr_sel; + wire [0:`STQ_ENTRIES-1] stq2_cmmt_ptr_l1; + wire [0:`STQ_ENTRIES-1] stq2_cmmt_ptr_remove; + wire [64-(`DC_SIZE-3):57] stq1_cclass; + wire stq1_rel_blk_cclass; + wire stq1_binv1_cclass_m; + wire stq1_binv2_cclass_m; + wire stq1_binv3_cclass_m; + wire stq1_binv_blk_cclass; + wire stq1_binv_wclrall; + wire stq2_reject_val; + wire stq2_reject_rv_coll; + wire stq2_cmmt_reject; + wire stqe0_icswxdot_val; + wire [0:`STQ_ENTRIES-1] ex4_fwd_addrcmp_hi; + wire [0:`STQ_ENTRIES-1] ex4_fwd_addrcmp_lo; + wire [0:`STQ_ENTRIES-1] ex4_fwd_addrcmp; + wire [0:`STQ_ENTRIES-1] ex4_fwd_sel; + reg [0:`STQ_FWD_ENTRIES-1] fwd_pri_mask; + reg [0:`STQ_FWD_ENTRIES-1] ex4_stqe_match_addr; + reg [0:`STQ_FWD_ENTRIES-1] ex4_stqe_match; + reg [0:`STQ_FWD_ENTRIES-1] stq_mask; + wire [0:`STQ_ENTRIES-1] stqe_fwd_enable; + wire [0:`STQ_ENTRIES-1] ex4_fwd_entry; + wire ex4_fwd_val; + wire [0:`STQ_FWD_ENTRIES-1] ex4_fwd_chk_fail; + wire [`STQ_FWD_ENTRIES:`STQ_ENTRIES-1] ex4_nofwd_entry; + wire [0:`STQ_ENTRIES-1] ex4_fwd_restart_entry; + wire ex4_fwd_restart; + wire [0:`STQ_ENTRIES-1] ex4_fwd_endian_mux; + wire [0:`STQ_ENTRIES-1] ex4_fwd_is_store_mux; + wire [0:`STQ_ENTRIES-1] ex4_fwd_is_cline_chk; + wire [0:`STQ_ENTRIES-1] ex4_fwd_is_miss_chk; + wire [0:`STQ_ENTRIES-1] ex4_fwd_is_larx_chk; + wire [0:`STQ_ENTRIES-1] ex4_fwd_is_blk_load_chk; + wire [0:`STQ_ENTRIES-1] ex4_fwd_is_gload_chk; + wire [0:`STQ_ENTRIES-1] stqe_rej_newer_gload; + wire [0:`STQ_ENTRIES-1] stqe_rej_other; + wire [0:`STQ_ENTRIES-1] stqe_rej_cline_chk; + wire [0:`STQ_ENTRIES-1] stqe_rej_cline_miss; + wire [0:`STQ_ENTRIES-1] stqe_rej_wchkall; + wire [0:`STQ_ENTRIES-1] stqe_rej_hit_no_fwd; + wire [0:`STQ_ENTRIES] set_hold_early_clear; + wire [0:`STQ_ENTRIES] ex5_qHit_set_miss; + wire [0:`STQ_ENTRIES-1] ex4_qHit_set_oth; + wire [0:`STQ_ENTRIES-1] ex4_qHit_set_miss; + wire [0:`STQ_ENTRIES-1] ex4_older_ldmiss; + wire [0:`STQ_ENTRIES-1] ex4_fwd_rej_guarded; + wire [0:`STQ_ENTRIES-1] stqe_itag_act; + wire [0:`STQ_ENTRIES] stqe_data_val; + wire [0:`STQ_ENTRIES-1] stqe_data_act; + wire [0:`STQ_ENTRIES] ex3_stq_data_val; + wire [0:`STQ_ENTRIES-1] stqe_fxu1_data_sel; + wire [0:`STQ_ENTRIES-1] stqe_axu_data_sel; + wire [0:`STQ_ENTRIES] stqe_fxu1_dvcr_val; + wire [0:`STQ_ENTRIES-1] stqe_fxu1_data_val; + wire [0:`STQ_ENTRIES-1] stqe_axu_data_val; + wire [0:`STQ_ENTRIES-1] ex3_fxu1_data_ptr; + wire cpl_ready; + wire skip_ready; + wire [0:`STQ_ENTRIES-1] stqe_skip_ready; + reg [0:`ITAG_SIZE_ENC-1] cpl_ready_itag; + wire [0:`ITAG_SIZE_ENC-1] cpl_ready_itag_final; + reg [0:`ITAG_SIZE_ENC-1] ext_act_queue_itag; + reg [0:3] ext_act_queue_dacrw_det; + reg ext_act_queue_dacrw_rpt; + reg [0:`ITAG_SIZE_ENC-1] stq_ext_act_itag; + reg [0:3] stq_ext_act_dacrw_det; + reg stq_ext_act_dacrw_rpt; + reg [0:`CR_POOL_ENC+`THREADS_POOL_ENC-1] stq_ext_act_cr_wa; + reg [0:`THREADS-1] cpl_ready_thrd_id; + wire [0:`THREADS-1] cpl_ready_tid_final; + reg [0:5] cpl_ttype; + reg cpl_dreq_val; + wire dacrw_report; + wire [0:3] dacrw_det; + wire [0:`STQ_ENTRIES-1] stqe_guarded; + wire [0:`STQ_ENTRIES-1] ex3_fwd_agecmp; + wire ex3_ex4_agecmp; + wire ex3_ex4_agecmp_sametid; + wire ex3_ex4_byte_en_hit; + wire ex4_rej_newer_gload; + wire stqe_need_ready_act; + wire stqe_need_ready_next; + wire stq2_rtry_cnt_act; + wire rtry_cnt_reset; + wire ex4_rej_other; + wire ex4_rej_sync_pending; + wire ex4_rej_cline_chk; + wire ex4_rej_cline_miss; + wire ex4_rej_wchkall; + wire ex4_thrd_match_restart; + wire ex4_thrd_nomatch_restart; + wire [0:`STQ_ENTRIES-1] stqe_l_zero; + wire [0:`STQ_ENTRIES] stqe_flushed; + wire [0:`STQ_ENTRIES] stqe_alloc_flushed; + wire [0:`THREADS-1] any_ack_val; + wire [0:`THREADS-1] any_ack_rcvd; + wire [0:`STQ_ENTRIES-1] ex4_byte_en_ok; + wire [0:`STQ_ENTRIES-1] ex4_byte_en_miss; + wire [0:`STQ_ENTRIES-1] ex4_1byte_chk_ok; + wire [0:`STQ_ENTRIES-1] ex4_byte_chk_ok; + wire [0:`STQ_ENTRIES-1] ex4_thrd_match; + wire [0:`STQ_ENTRIES-1] ex4_thrd_id_ok; + wire [0:`STQ_ENTRIES-1] stqe_flush_cmp; + wire [0:`STQ_ENTRIES] stqe_compl_rcvd; + wire [0:`THREADS-1] ex5_streq_val; + wire [0:`THREADS-1] ex3_streq_val; + wire [0:`THREADS-1] ex4_ldreq_val; + wire [0:`THREADS-1] ex4_wchkall_val; + wire ex3_streq_valid; + wire ex4_streq_valid; + wire ex5_streq_valid; + wire ex4_ldreq_valid; + wire ex3_pfetch_val; + wire ex4_wchkall_valid; + wire ex4_fwd_hit; + wire ex0_i0_flushed; + wire ex0_i1_flushed; + wire ex1_i0_flushed; + wire ex1_i1_flushed; + reg [0:`THREADS-1] stq_empty; + wire [0:`STQ_ENTRIES-1] stq_chk_alloc; + wire [0:`THREADS-1] cr_ack; + wire [0:`THREADS-1] sync_ack; + wire [0:`THREADS-1] cr_thrd; + wire [0:`THREADS-1] cr_block; + wire [0:`THREADS-1] resv_ack; + wire [0:`THREADS-1] stcx_pass; + wire cr_xer_so; + wire cr_stcx_pass; + wire [0:`THREADS-1] icswxr_ack_val; + wire [0:`THREADS-1] icswxr_ack_thrd; + wire [0:`THREADS-1] sync_ack_all; + wire [0:`THREADS-1] perf_stq_stcx_fail; + wire [0:`THREADS-1] perf_stq_icswxr_nbusy; + wire [0:`THREADS-1] perf_stq_icswxr_busy; + wire perf_stq_cmmt_attmpt; + wire perf_stq_cmmt_val; + wire perf_stq_need_hole; + wire [0:15] stq_rotcmp; + wire [0:`STQ_ENTRIES] ex3_agecmp; + wire [0:3] ex4_rot_sel_be[0:`STQ_ENTRIES-1]; + wire [0:3] ex4_rot_sel_le[0:`STQ_ENTRIES-1]; + wire [0:3] ex4_rot_sel[0:`STQ_ENTRIES-1]; + wire [(128-`STQ_DATA_SIZE):127] stqe_fwd_data[0:`STQ_ENTRIES-1]; + wire [0:63] stqe_data1_swzl[0:`STQ_ENTRIES-1]; + wire [0:63] ex4_fwd_data1[0:`STQ_ENTRIES-1]; + wire [0:63] ex4_fwd_data1_swzl[0:`STQ_ENTRIES-1]; + wire [0:7] ex4_se_b[0:`STQ_ENTRIES-1]; + wire [0:`STQ_ENTRIES-1] ex4_se; + wire [0:`STQ_ENTRIES-1] ex4_sext; + wire [0:3] ex4_rot_mask; + wire [0:4] ex4_req_opsize_1hot; + wire ex4_req_opsize1; + wire [0:3] ex4_hw_addr_cmp[0:`STQ_ENTRIES-1]; + wire [0:3] ex4_rev_rot_sel[0:`STQ_ENTRIES-1]; + wire [0:3] ex4_shft_rot_sel[0:`STQ_ENTRIES-1]; + wire [0:3] ex4_sext8_le_sel[0:`STQ_ENTRIES-1]; + wire [0:3] ex4_sext4_le_sel[0:`STQ_ENTRIES-1]; + wire [0:3] ex4_sext2_le_sel[0:`STQ_ENTRIES-1]; + wire [0:3] ex4_sext_le_sel[0:`STQ_ENTRIES-1]; + wire [0:3] ex4_sext_sel[0:`STQ_ENTRIES-1]; + wire [0:3] stqe_rotcmp_val[0:`STQ_ENTRIES-1]; + wire [0:`STQ_ENTRIES-1] stqe_opsize8; + wire [0:`STQ_ENTRIES-1] stqe_opsize4; + wire [0:`STQ_ENTRIES-1] stqe_opsize2; + wire [0:`STQ_ENTRIES-1] stqe_opsize1; + wire [0:`STQ_ENTRIES-1] ex4_opsize8_be; + wire [0:`STQ_ENTRIES-1] ex4_opsize4_be; + wire [0:`STQ_ENTRIES-1] ex4_opsize2_be; + wire [0:`STQ_ENTRIES-1] ex4_opsize1_be; + wire [0:`STQ_ENTRIES-1] ex4_opsize8_le; + wire [0:`STQ_ENTRIES-1] ex4_opsize4_le; + wire [0:`STQ_ENTRIES-1] ex4_opsize2_le; + wire [0:`STQ_ENTRIES-1] ex4_opsize1_le; + wire [0:2] ex3_opsize_1hot; + wire [0:3] ex3_rotcmp2_fld; + wire [0:3] ex3_rotcmp3_fld; + wire stq1_cmmt_dreq_val; + wire stq3_cmmt_dreq_val; + wire stq1_cmmt_send_l2; + wire stq3_cmmt_send_l2; + wire stq1_cmmt_dvc_val; + wire stq3_cmmt_dvc_val; + reg [64-`REAL_IFAR_WIDTH:63] stq1_p_addr; + reg [0:5] stq1_ttype; + wire stq1_mftgpr_val; + reg stq1_wclr_all; + reg [0:`THREADS-1] stq2_thrd_id; + reg [0:5] stq3_ttype; + reg [0:`THREADS-1] stq3_tid; + reg [0:1] stq3_tid_enc; + wire [0:`STQ_ENTRIES-1] ex3_data_val; + wire [0:`STQ_ENTRIES-1] ex3_illeg_lswx; + wire [0:`STQ_ENTRIES-1] ex3_strg_noop; + reg [0:1] fxu1_spr_dbcr2_dvc1m; + reg [0:1] fxu1_spr_dbcr2_dvc2m; + reg [8-(2**`GPR_WIDTH_ENC)/8:7] fxu1_spr_dbcr2_dvc1be; + reg [8-(2**`GPR_WIDTH_ENC)/8:7] fxu1_spr_dbcr2_dvc2be; + wire ex3_fxu1_dvc1r_cmpr; + wire ex3_fxu1_dvc2r_cmpr; + wire [0:1] ex3_fxu1_dvcr_cmpr; + wire [0:`STQ_ENTRIES-1] stqe_dacrw_det0; + wire [0:`STQ_ENTRIES-1] stqe_dacrw_det1; + wire [0:`STQ_ENTRIES-1] stqe_dacrw_det2; + wire [0:`STQ_ENTRIES-1] stqe_dacrw_det3; + wire [0:`STQ_ENTRIES-1] stqe_dvc_int_det; + wire [0:`STQ_ENTRIES-1] stq2_cmmt_entry; + wire [0:`STQ_ENTRIES-1] stq3_cmmt_entry; + wire [0:`STQ_ENTRIES-1] stq4_cmmt_entry; + wire [0:`STQ_ENTRIES-1] stq5_cmmt_entry; + wire [0:`STQ_ENTRIES-1] stq6_cmmt_entry; + wire [0:`STQ_ENTRIES-1] stq7_cmmt_entry; + wire [0:`STQ_ENTRIES-1] stqe_cmmt_entry; + wire [0:`STQ_ENTRIES-1] stqe_qHit_held_set; + wire [0:`STQ_ENTRIES] stqe_qHit_held_mux; + wire [0:`STQ_ENTRIES] stqe_qHit_held_clr; + wire [0:1] stqe_qHit_held_ctrl[0:`STQ_ENTRIES-1]; + wire [0:`THREADS-1] set_hold_thread; + wire ex5_stq_set_hold; + wire [0:`THREADS-1] clr_hold_thread; + wire [0:`STQ_ENTRIES] stqe_need_ready_flushed; + wire ex2_fxu1_val; + wire ex3_fxu1_val; + wire ex2_axu_val; + wire ex3_axu_val; + wire [0:11] stqe_icswx_ct_sel[0:`STQ_ENTRIES-1]; + reg [0:11] ex3_ct_sel; + reg [0:1] ex4_thrd_id_enc; + wire [64-`REAL_IFAR_WIDTH:63] ex4_p_addr_ovrd; + wire stq2_cmmt_dci_val; + wire stq_dci_inprog; + wire stq_reject_dci_coll; + wire stq3_dcblc_instr; + wire stq3_icblc_instr; + reg [0:5] stq6_ttype; + reg [0:`THREADS-1] stq6_tid; + wire stq6_dci; + wire stq6_ici; + reg stq6_wclr_all_val; + wire stq6_icswxnr; + wire stq6_mftgpr; + wire stq6_local_ack_val; + wire [0:`THREADS-1] l2_icbi_ack; + wire [0:`STQ_ENTRIES-1] stqe_valid_sync; + wire [0:`THREADS-1] stqe_tid_inuse[0:`STQ_ENTRIES-1]; + wire [0:`STQ_ENTRIES] stq_cp_next_val; + wire [0:`STQ_ENTRIES-1] stq_i0_comp_val; + wire [0:`STQ_ENTRIES-1] stq_i1_comp_val; + wire [0:`STQ_ENTRIES-1] ex3_set_stq; + wire [0:`STQ_ENTRIES-1] ex3_addr_act; + wire [0:`STQ_ENTRIES-1] ex4_set_stq; + wire [0:`STQ_ENTRIES-1] ex4_addr_act; + wire [0:`STQ_ENTRIES-1] ex5_set_stq; + wire [0:`STQ_ENTRIES-1] ex5_addr_act; + wire [(128-`STQ_DATA_SIZE):127] stqe_data1_mux[0:`STQ_ENTRIES]; + wire rv_hold; + wire [0:2] stq2_rtry_cnt_incr; + reg [0:`ITAG_SIZE_ENC-1] stq_cp_next_itag[0:`STQ_ENTRIES]; + reg [0:`ITAG_SIZE_ENC-1] stq_i0_comp_itag[0:`STQ_ENTRIES-1]; + reg [0:`ITAG_SIZE_ENC-1] stq_i1_comp_itag[0:`STQ_ENTRIES-1]; + reg [0:`STQ_ENTRIES-1] ex2_nxt_oldest_ptr; + reg [0:`STQ_ENTRIES-1] ex2_nxt_youngest_ptr; + wire ex2_no_nxt_match; + wire [0:`STQ_ENTRIES-1] ex2_no_nxt_oldest; + wire [0:`STQ_ENTRIES-1] ex2_nxt_youngest_shft; + wire [0:`STQ_ENTRIES-1] ex2_nxt_oldest; + wire [0:`STQ_ENTRIES-1] stq_tag_available; + wire [0:`STQ_ENTRIES-1] stq_wrt_i0_ptr; + wire [0:`STQ_ENTRIES-1] stq_wrt_i1_ptr; + wire [0:`STQ_ENTRIES-1] stq_wrt_i0_mux; + reg [0:`STQ_ENTRIES_ENC-1] stq_tag_i0_entry; + reg [0:`STQ_ENTRIES_ENC-1] stq_tag_i1_entry; + wire [0:`STQ_ENTRIES-1] stq_tag_act; + wire [0:`STQ_ENTRIES-1] stq_tag_inval; + wire [0:`STQ_ENTRIES-1] stq_tag_i0_upd_val; + wire [0:`STQ_ENTRIES-1] stq_tag_i1_upd_val; + wire [0:`STQ_ENTRIES-1] stq_tag_i0_stq_sel; + wire [0:`STQ_ENTRIES-1] stq_tag_i1_stq_sel; + wire [0:`STQ_ENTRIES-1] stq_tag_ptr_compr[0:`STQ_ENTRIES-1]; + wire [0:2] stq_tag_ptr_ctrl[0:`STQ_ENTRIES-1]; + wire [0:`STQ_ENTRIES-1] stq3_cmmt_tag_entry; + reg [0:`STQ_ENTRIES_ENC-1] stq3_cmmt_tag; + + // these wires are to convert the ports at the top to an array of itags + wire [0:`ITAG_SIZE_ENC-1] iu_lq_cp_next_itag_int[0:`THREADS-1]; + wire [0:`ITAG_SIZE_ENC-1] iu_lq_i0_completed_itag_int[0:`THREADS-1]; + wire [0:`ITAG_SIZE_ENC-1] iu_lq_i1_completed_itag_int[0:`THREADS-1]; + wire [0:1] ctl_lsq_spr_dbcr2_dvc1m_int[0:`THREADS-1]; + wire [0:7] ctl_lsq_spr_dbcr2_dvc1be_int[0:`THREADS-1]; + wire [0:1] ctl_lsq_spr_dbcr2_dvc2m_int[0:`THREADS-1]; + wire [0:7] ctl_lsq_spr_dbcr2_dvc2be_int[0:`THREADS-1]; + + + //!! Bugspray Include: lq_stq + + // This is used to convert the wide vector port inputs into an internal 2 dimesional array format + generate + begin : ports + genvar tid; + for (tid = 0; tid <= `THREADS - 1; tid = tid + 1) + begin : convert + assign iu_lq_cp_next_itag_int[tid] = iu_lq_cp_next_itag[`ITAG_SIZE_ENC*tid:(`ITAG_SIZE_ENC*(tid+1))-1]; + assign iu_lq_i0_completed_itag_int[tid] = iu_lq_i0_completed_itag[`ITAG_SIZE_ENC*tid:(`ITAG_SIZE_ENC*(tid+1))-1]; + assign iu_lq_i1_completed_itag_int[tid] = iu_lq_i1_completed_itag[`ITAG_SIZE_ENC*tid:(`ITAG_SIZE_ENC*(tid+1))-1]; + assign ctl_lsq_spr_dbcr2_dvc1m_int[tid] = ctl_lsq_spr_dbcr2_dvc1m[2*tid:(2*(tid+1))-1]; + assign ctl_lsq_spr_dbcr2_dvc2m_int[tid] = ctl_lsq_spr_dbcr2_dvc2m[2*tid:(2*(tid+1))-1]; + assign ctl_lsq_spr_dbcr2_dvc1be_int[tid] = ctl_lsq_spr_dbcr2_dvc1be[8*tid:8*(tid+1)-1]; + assign ctl_lsq_spr_dbcr2_dvc2be_int[tid] = ctl_lsq_spr_dbcr2_dvc2be[8*tid:8*(tid+1)-1]; + end + end + endgenerate + + // Allocate an entry in the Queue off IU dispatch, insert itag + // Do itag lookup to determine, queue entry, when data/address are available + // When both address & data are ready for any entry, send lsq_ctl_cpl_ready for that entry + // obviously start with the oldest entry + // Completion will then report itag_complete + // IF + // arb_stq_cred_avail=1 + // ldq_stq_rel1_blk_store=0 + // THEN + // Initiate STQ Commit + // starts with asserting stq commit pipe interface + // if rv issues at stq2, retry the stq interface (sink will cancel) + // drive L2 at stq3 + // delete entry at stq7 + // free sq credit + + // DONT CP flush stuff that have itag_complete + + //<> + assign ex3_req_act = 1'b1; + + //------------------------------------------------------------------------------ + // XU Config Bits + //------------------------------------------------------------------------------ + + // XUCR0[CLS] 128 Byte Cacheline Enabled + // 1 => 128 Byte Cacheline + // 0 => 64 Byte Cacheline + assign spr_xucr0_cls_d = xu_lq_spr_xucr0_cls; + assign spr_xucr0_64cls = (~spr_xucr0_cls_q); + + // IUCR0[ICBI_ACK_EN] ICBI L2 Acknoledge Enable + // 1 => ICBI Acknowledged by the L2 + // 0 => ICBI Acknowledged by the A2 + assign spr_iucr0_icbi_ack_d = iu_lq_spr_iucr0_icbi_ack; + assign a2_icbi_ack_en = (~spr_iucr0_icbi_ack_q); + + // LSUCR0[DFWD] Store Data Forwarding is Disabled + // 1 => Store Data Forwarding is Disabled + // 0 => Store Data Forwarding is Enabled + assign spr_lsucr0_dfwd_d = ctl_lsq_spr_lsucr0_dfwd; + + //------------------------------------------------------------------------------ + // Back-Invalidate In Progress + //------------------------------------------------------------------------------ + // Back-Invalidate in the LQ pipeline + assign rv1_binv_val_d = l2_back_inv_val; + assign ex0_binv_val_d = rv1_binv_val_q; + assign ex1_binv_val_d = ex0_binv_val_q; + assign ex2_binv_val_d = ex1_binv_val_q; + assign ex3_binv_val_d = ex2_binv_val_q; + + assign rv1_binv_addr_d = l2_back_inv_addr; + assign ex0_binv_addr_d = rv1_binv_addr_q; + assign ex1_binv_addr_d = ex0_binv_addr_q; + assign ex2_binv_addr_d = ex1_binv_addr_q; + assign ex3_binv_addr_d = ex2_binv_addr_q; + + //------------------------------------------------------------------------------ + // STQ TAG Mapping + //------------------------------------------------------------------------------ + + // Determine Which entries are available for updating + assign stq_tag_available = (~stq_tag_val_q); + + // I0 starts at the beginning of the TAG queue and works its way to the end, it looks for the first available + assign stq_wrt_i0_ptr[0] = stq_tag_available[0]; + generate + begin : xhdl0 + genvar stq; + for (stq = 1; stq <= `STQ_ENTRIES - 1; stq = stq + 1) + begin : stqI0Wrt + assign stq_wrt_i0_ptr[stq] = &(~stq_tag_available[0:stq - 1]) & stq_tag_available[stq]; + end + end + endgenerate + + // I1 starts at the end of the TAG queue and works its way to the beginning, it looks for the first available entry + assign stq_wrt_i1_ptr[`STQ_ENTRIES - 1] = stq_tag_available[`STQ_ENTRIES - 1]; + generate + begin : xhdl1 + genvar stq; + for (stq = 0; stq <= `STQ_ENTRIES - 2; stq = stq + 1) + begin : stqI1Wrt + assign stq_wrt_i1_ptr[stq] = &(~stq_tag_available[stq + 1:`STQ_ENTRIES - 1]) & stq_tag_available[stq]; + end + end + endgenerate + + // Generate STQ TAG Entry Encoded + always @(*) + begin: stqTag + reg [0:`STQ_ENTRIES_ENC-1] entryI0; + reg [0:`STQ_ENTRIES_ENC-1] entryI1; + reg [0:`STQ_ENTRIES_ENC-1] cmmtTag; + integer stq; + entryI0 = 0; + entryI1 = 0; + cmmtTag = 0; + for (stq = 0; stq <= `STQ_ENTRIES - 1; stq = stq + 1) + begin + entryI0 = (stq & {`STQ_ENTRIES_ENC{stq_wrt_i0_ptr[stq]}}) | entryI0; + entryI1 = (stq & {`STQ_ENTRIES_ENC{stq_wrt_i1_ptr[stq]}}) | entryI1; + cmmtTag = (stq & {`STQ_ENTRIES_ENC{stq3_cmmt_tag_entry[stq]}}) | cmmtTag; + end + stq_tag_i0_entry = entryI0; + stq_tag_i1_entry = entryI1; + stq3_cmmt_tag = cmmtTag; + end + + generate + begin : xhdl2 + genvar stq; + for (stq = 0; stq <= `STQ_ENTRIES - 1; stq = stq + 1) + begin : stqTagAlloc + // STQ TAG Alloc is valid + assign stq_tag_act[stq] = stq_tag_i0_upd_val[stq] | stq_tag_i1_upd_val[stq] | stq_tag_val_q[stq]; + assign stq_tag_inval[stq] = |(stq_tag_ptr_q[stq] & stq7_entry_delete[0:`STQ_ENTRIES - 1]); + assign stq_tag_i0_upd_val[stq] = stq_wrt_i0_ptr[stq] & |(ex1_i0_vld_q); + assign stq_tag_i1_upd_val[stq] = stq_wrt_i1_ptr[stq] & |(ex1_i1_vld_q); + assign stq_tag_val_d[stq] = stq_tag_i0_upd_val[stq] | stq_tag_i1_upd_val[stq] | (stq_tag_val_q[stq] & (~stq_tag_inval[stq])); + + // wrt_i0 needs to be wrt_i1 when ex1_i1_vld and not ex1_i0_vld, since wrt_i1_ptr is being set valid and alloc_i0_wrt_ptr is valid + + // STQ TAG Alloc Control + // I0 is updating the Store Queue + assign stq_wrt_i0_mux[stq] = (stq_alloc_sel == 1'b1) ? stq_wrt_i1_ptr[stq] : + stq_wrt_i0_ptr[stq]; + assign stq_tag_i0_stq_sel[stq] = stq_wrt_i0_mux[stq] & stq_alloc_val[0]; + assign stq_tag_ptr_ctrl[stq][0] = stq_tag_i0_stq_sel[stq]; + + // I1 is updating the Store Queue + assign stq_tag_i1_stq_sel[stq] = stq_wrt_i1_ptr[stq] & stq_alloc_val[1]; + assign stq_tag_ptr_ctrl[stq][1] = stq_tag_i1_stq_sel[stq]; + + // Store Queue is compressing, need to compress all pointers + assign stq_tag_ptr_ctrl[stq][2] = stq_push_down; + + // Compress each pointer in the STQ TAG Alloc Array + assign stq_tag_ptr_compr[stq] = {stq_tag_ptr_q[stq][1:`STQ_ENTRIES - 1], 1'b0}; + + // TAG Points to the STQ Entry + // We should never see ctrl = 110 or ctrl = 111, will need bugspray + + // STQ TAG will is committing, should be a 1-hot, will need bugspray + assign stq_tag_ptr_d[stq] = (stq_tag_ptr_ctrl[stq] == 3'b100) ? stqe_alloc_i0_wrt_ptr : + (stq_tag_ptr_ctrl[stq] == 3'b101) ? stqe_alloc_i0_wrt_ptr : + (stq_tag_ptr_ctrl[stq] == 3'b010) ? stqe_alloc_i1_wrt_ptr : + (stq_tag_ptr_ctrl[stq] == 3'b011) ? stqe_alloc_i1_wrt_ptr : + (stq_tag_ptr_ctrl[stq] == 3'b001) ? stq_tag_ptr_compr[stq] : + stq_tag_ptr_q[stq]; + assign stq3_cmmt_tag_entry[stq] = |(stq_tag_ptr_q[stq] & stq3_cmmt_ptr_q) & stq_tag_val_q[stq]; + end + end + endgenerate + + // Order Queue Update with STQ TAG + assign stq_odq_i0_stTag = stq_tag_i0_entry; + assign stq_odq_i1_stTag = stq_tag_i1_entry; + + // Order Queue invalidated STQ TAG + assign stq4_cmmt_tag_d = stq3_cmmt_tag; + assign stq_odq_stq4_stTag_inval = stq4_cmmt_val_q; + assign stq_odq_stq4_stTag = stq4_cmmt_tag_q; + + //------------------------------------------------------------------------------ + // STQ Entry Allocation + //------------------------------------------------------------------------------ + assign stq_alloc_val[0] = |(ex1_i0_vld_q) | |(ex1_i1_vld_q); + assign stq_alloc_val[1] = |(ex1_i0_vld_q) & |(ex1_i1_vld_q); + + assign stq_alloc_sel = (~(|(ex1_i0_vld_q))) & |(ex1_i1_vld_q); + + assign stq_act = stq_alloc_val[0] | |(stqe_alloc_q) | stq2_cmmt_flushed_q | stq3_cmmt_flushed_q | stq4_cmmt_flushed_q | stq5_cmmt_flushed_q | stq6_cmmt_flushed_q | stq7_cmmt_flushed_q; + + assign stqe_alloc_itag0 = (stq_alloc_sel == 1'b1) ? ex1_i1_itag_q : + ex1_i0_itag_q; + + assign stq_alloc_flushed[0] = (stq_alloc_sel == 1'b1) ? ex1_i1_flushed : + ex1_i0_flushed; + + assign stq_alloc_thrd_id0 = (stq_alloc_sel == 1'b1) ? ex1_i1_vld_q : + ex1_i0_vld_q; + assign stq_alloc_thrd_id1 = ex1_i1_vld_q; + assign stqe_alloc_itag1 = ex1_i1_itag_q; + assign stq_alloc_flushed[1] = ex1_i1_flushed; + + assign stqe_alloc_ptr_r1 = {1'b0, stqe_alloc_ptr_q[0:`STQ_ENTRIES - 2]}; + assign stqe_alloc_ptr_r2 = {1'b0, stqe_alloc_ptr_r1[0:`STQ_ENTRIES - 2]}; + assign stqe_alloc_ptr_l1 = {stqe_alloc_ptr_q[1:`STQ_ENTRIES - 1], ((~(|(stqe_alloc_ptr_q))))}; + + assign stqe_alloc_ptr_sel = {stq_alloc_val[0:1], stq_push_down}; + // stqe_alloc_ptr_q when "011", can't happen + // stqe_alloc_ptr_r1 when "010", can't happen + // "000" + + assign stqe_alloc_ptr_d = (stqe_alloc_ptr_sel == 3'b111) ? stqe_alloc_ptr_r1 : + (stqe_alloc_ptr_sel == 3'b110) ? stqe_alloc_ptr_r2 : + (stqe_alloc_ptr_sel == 3'b101) ? stqe_alloc_ptr_q : + (stqe_alloc_ptr_sel == 3'b100) ? stqe_alloc_ptr_r1 : + (stqe_alloc_ptr_sel == 3'b001) ? stqe_alloc_ptr_l1 : + stqe_alloc_ptr_q; + assign stqe_alloc_i0_wrt_ptr = (stq_push_down == 1'b0) ? stqe_alloc_ptr_q : + stqe_alloc_ptr_l1; + + assign stqe_alloc_i1_wrt_ptr = (stq_push_down == 1'b0) ? stqe_alloc_ptr_r1 : + stqe_alloc_ptr_q; + + // Thread Quiesced OR reduce + always @(*) begin: tidQuiesce + reg [0:`THREADS-1] tidQ; + + //(* analysis_not_referenced="true" *) + + integer stq; + tidQ = {`THREADS{1'b0}}; + for (stq=0; stq<`STQ_ENTRIES; stq=stq+1) begin + tidQ = (stqe_tid_inuse[stq]) | tidQ; + end + stq_empty = ~tidQ; + end + + assign stq_ldq_empty = stq_empty & ~ext_ack_queue_v_q; + + assign stq_chk_alloc = (~stqe_alloc_q[0:`STQ_ENTRIES - 1]) & (~stqe_alloc_ptr_q) & (stq1_cmmt_ptr_q | stqe_need_ready_ptr_q[0:`STQ_ENTRIES - 1] | ex4_fxu1_data_ptr_q); + + //------------------------------------------------------------------------------ + // STQ Completion Request Pointer + //------------------------------------------------------------------------------ + assign stqe_need_ready_ptr_r1 = {1'b0, stqe_need_ready_ptr_q[0:`STQ_ENTRIES - 2]}; + assign stqe_need_ready_ptr_l1 = {stqe_need_ready_ptr_q[1:`STQ_ENTRIES - 1], ((~(|(stqe_need_ready_ptr_q))))}; + + assign stqe_need_ready_ptr_sel = {stqe_need_ready_next, stq_push_down}; + + assign stqe_need_ready_ptr_d = (stqe_need_ready_ptr_sel == 2'b10) ? stqe_need_ready_ptr_r1 : + (stqe_need_ready_ptr_sel == 2'b01) ? stqe_need_ready_ptr_l1 : + stqe_need_ready_ptr_q[0:`STQ_ENTRIES - 1]; + assign stqe_need_ready_blk = {`STQ_ENTRIES{ctl_lsq_stq_cpl_blk}}; + assign stqe_need_ready_rpt = stqe_addr_val_q[0:`STQ_ENTRIES - 1] & + (stqe_data_nxt_q[0:`STQ_ENTRIES - 1] | (~stqe_has_data_q[0:`STQ_ENTRIES - 1])) & + (stqe_have_cp_next_q[0:`STQ_ENTRIES - 1] | (~stqe_need_ext_ack_q[0:`STQ_ENTRIES - 1])) & + (~stqe_ready_sent_q[0:`STQ_ENTRIES - 1]) & + (~stqe_flushed_q[0:`STQ_ENTRIES - 1]); + + assign stq_cpl_need_hold_d = ctl_lsq_ex_pipe_full & ctl_lsq_stq_cpl_blk & (|(stqe_need_ready_rpt) | |(ext_ack_queue_v_q)); + + assign stqe_need_ready = stqe_need_ready_rpt & (~stqe_need_ready_blk); + + assign stqe_need_ready_flushed = stqe_flushed_q & stqe_need_ready_ptr_q & stqe_need_ready_ptr_q & (~stqe_ready_sent_q); + + assign stqe_need_ready_next = |(stqe_need_ready_flushed) | cpl_ready | skip_ready; + assign stqe_need_ready_act = stqe_need_ready_next | stq_push_down; + + assign cpl_ready = (~(|(cp_flush_q & cpl_ready_tid_final))) & (~(|(any_ack_val))) & |(stqe_need_ready & stqe_need_ready_ptr_q[0:`STQ_ENTRIES - 1] & (stqe_dreq_val_q[0:`STQ_ENTRIES - 1] | stqe_dvc_int_det | ((~stqe_need_ext_ack_q[0:`STQ_ENTRIES - 1])))); + + generate + begin : xhdl3 + genvar i; + for (i = 0; i <= `STQ_ENTRIES - 1; i = i + 1) + begin : skip_ready_gen + assign stqe_skip_ready[i] = (~(|(cp_flush_q & stqe_thrd_id_q[i]))) & (stqe_need_ready_rpt[i] & stqe_need_ready_ptr_q[i] & stqe_need_ext_ack_q[i]); + end + end + endgenerate + assign skip_ready = |(stqe_skip_ready); + + assign dacrw_det[0] = |(stqe_dacrw_det0 & stqe_need_ready_ptr_q[0:`STQ_ENTRIES - 1]); + assign dacrw_det[1] = |(stqe_dacrw_det1 & stqe_need_ready_ptr_q[0:`STQ_ENTRIES - 1]); + assign dacrw_det[2] = |(stqe_dacrw_det2 & stqe_need_ready_ptr_q[0:`STQ_ENTRIES - 1]); + assign dacrw_det[3] = |(stqe_dacrw_det3 & stqe_need_ready_ptr_q[0:`STQ_ENTRIES - 1]); + assign dacrw_report = |(stqe_dvc_int_det & stqe_need_ready_ptr_q[0:`STQ_ENTRIES - 1]); + + // Qualified with lsq_ctl_cpl_ready in lq_ldq + assign lsq_ctl_stq_cpl_ready = cpl_ready | |(any_ack_val); + + assign cpl_ready_itag_final = (any_ack_val == {`THREADS{1'b0}}) ? cpl_ready_itag : + ext_act_queue_itag; + assign lsq_ctl_stq_cpl_ready_itag = cpl_ready_itag_final; + + assign cpl_ready_tid_final = (any_ack_val == {`THREADS{1'b0}}) ? cpl_ready_thrd_id : + any_ack_val; + assign lsq_ctl_stq_cpl_ready_tid = cpl_ready_tid_final; + + assign lsq_ctl_stq_exception_val = 0; + assign lsq_ctl_stq_exception = 0; + assign lsq_ctl_stq_n_flush = (any_ack_val == {`THREADS{1'b0}}) ? dacrw_report : + ext_act_queue_dacrw_rpt; + assign lsq_ctl_stq_dacrw = (any_ack_val == {`THREADS{1'b0}}) ? dacrw_det : + ext_act_queue_dacrw_det; + + // We may want to add syncs here for single thread, when we go to 2 `THREADS, flushing may not matter + // DCI ICI + assign lsq_ctl_stq_np1_flush = ((cpl_ttype == 6'b101111) | (cpl_ttype == 6'b101110)) & (~cpl_dreq_val); + + //------------------------------------------------------------------------------ + // L2 Acks + //------------------------------------------------------------------------------ + // (probably overkill on the latches here, but I'll leave it) + assign hwsync_ack = an_ac_sync_ack; // and or_reduce(stqe_is_sync_q(0 to `STQ_ENTRIES-1) and stqe_l_zero and stqe_need_ready_ptr_q(0 to `STQ_ENTRIES-1)); + + generate + begin : xhdl4 + genvar t; + for (t = 0; t <= `THREADS - 1; t = t + 1) + begin : sync_thrd_gen + assign lwsync_ack[t] = stq6_cmmt_val_q & |(stqe_is_sync_q[0:`STQ_ENTRIES - 1] & (~stqe_l_zero) & stq6_cmmt_ptr_q & stqe_need_ext_ack_q[0:`STQ_ENTRIES - 1]) & stq6_tid[t]; + assign local_instr_ack[t] = stq6_cmmt_val_q & |((~stqe_dreq_val_q[0:`STQ_ENTRIES - 1]) & stq6_cmmt_ptr_q & stqe_need_ext_ack_q[0:`STQ_ENTRIES - 1]) & stq6_local_ack_val & stq6_tid[t]; + assign icswxr_ack_thrd[t] = an_ac_back_inv_addr_lo[62:63] == t; + + assign l2_icbi_ack_d[t] = (((an_ac_icbi_ack_thread == t) & an_ac_icbi_ack) | l2_icbi_ack_q[t]) & (~icbi_ack[t]); + end + end + endgenerate + + assign icswxr_ack = an_ac_back_inv & an_ac_back_inv_target_bit3; + assign icswxr_ack_val = icswxr_ack_thrd & {`THREADS{icswxr_ack_q}}; + + assign resv_ack_d[0] = an_ac_stcx_complete[0] | (resv_ack_q[0] & icswxr_ack_dly1_q); + assign resv_ack[0] = (an_ac_stcx_complete[0] & ~icswxr_ack_q) | (resv_ack_q[0] & icswxr_ack_dly1_q); + generate + if (`THREADS == 2) + begin : res_ack_t1 + assign resv_ack_d[1] = an_ac_stcx_complete[1] | (resv_ack_q[1] & (resv_ack_q[0] | icswxr_ack_dly1_q)); + assign resv_ack[1] = (an_ac_stcx_complete[1] & (~an_ac_stcx_complete[0]) & ~icswxr_ack_q) | (resv_ack_q[1] & (resv_ack_q[0] | icswxr_ack_dly1_q)); + end + endgenerate + + // Dont need thread indicator for now, may change if the store queue design + // changes for multiple `THREADS + assign iu_icbi_ack_d = (iu_lq_icbi_complete_q | iu_icbi_ack_q) & (~icbi_ack); + + assign l2_icbi_ack = {`THREADS{a2_icbi_ack_en}} | l2_icbi_ack_q; + assign icbi_ack = iu_icbi_ack_q & l2_icbi_ack & ext_ack_queue_v_q; + assign sync_ack_all = hwsync_ack_q | lwsync_ack_q | icbi_ack_q | local_instr_ack_q; + + assign sync_ack_save_d = &(sync_ack_all); + + assign sync_ack[0] = sync_ack_all[0]; + generate // this logic only works for 1 or 2 `THREADS + begin : xhdl5 + genvar t; + for (t = 1; t <= `THREADS - 1; t = t + 1) + begin : sync_ack_thrd_gen + assign sync_ack[t] = (sync_ack_all[t] & (~sync_ack_all[t - 1])) | sync_ack_save_q; + end + end + endgenerate + + assign lsq_ctl_sync_done = |(hwsync_ack_q | lwsync_ack_q); + + // These guys have to fight over cr completion bus. + // Do not release if ldq_stq_rel1_blk_store=1 + assign cr_block = {`THREADS{ldq_stq_rel1_blk_store}} | (~ex0_cr_hole_q); + + assign cr_ack_d = (icswxr_ack_val | resv_ack_q) | (cr_ack_q & (~cr_ack)); + + assign cr_ack[0] = cr_ack_q[0] & (~cr_block[0]) & (~(|(sync_ack_all))); + generate // this logic only works for 1 or 2 `THREADS + begin : xhdl6 + genvar t; + for (t = 1; t <= `THREADS - 1; t = t + 1) + begin : cr_ack_thrd_gen + assign cr_ack[t] = cr_ack_q[t] & (~(cr_ack_q[t - 1] & (~cr_block[t - 1]))) & (~cr_block[t]) & (~(|(sync_ack_all))); + end + end + endgenerate + + // Local Ack for the following instructions + // These are instructions that require CP_NEXT to execute + // and have no dependency on another unit for an ACK + // 1) DCI + // 2) ICI + // 3) WCLR_ALL + // 4) ICSWX + // 5) MFTGPR + assign stq6_dci = (stq6_ttype == 6'b101111); + assign stq6_ici = (stq6_ttype == 6'b101110); + assign stq6_icswxnr = (stq6_ttype == 6'b100110); + assign stq6_mftgpr = (stq6_ttype == 6'b111000); + assign stq6_local_ack_val = stq6_dci | stq6_ici | stq6_wclr_all_val | stq6_icswxnr | stq6_mftgpr; + assign any_ack_rcvd = cr_ack | sync_ack; + + assign any_ack_hold_d = any_ack_rcvd | (any_ack_hold_q & (~({`THREADS{(~ctl_lsq_stq_cpl_blk)}} & any_ack_val))); + + assign any_ack_val[0] = any_ack_hold_q[0] & (~ctl_lsq_stq_cpl_blk); + + generate // this logic only works for 1 or 2 `THREADS + begin : xhdl7 + genvar t; + for (t = 1; t <= `THREADS - 1; t = t + 1) + begin : any_ack_val_thrd_gen + assign any_ack_val[t] = any_ack_hold_q[t] & (~any_ack_hold_q[t - 1]) & (~ctl_lsq_stq_cpl_blk); + end + end + endgenerate + + assign any_ack_val_ok_d = any_ack_val; + + // Request a hole until the ack is released, REL1 Block could be on. + // Kill the request once cr_ack=1 + assign rv0_cr_hole_d = icswxr_ack_val | resv_ack_q | (rv0_cr_hole_q & (~(arb_release_itag_vld_q & {`THREADS{(~ctl_lsq_stq_cpl_blk)}}))); + assign rv1_cr_hole_d = rv0_cr_hole_q & (~(arb_release_itag_vld_q & {`THREADS{(~ctl_lsq_stq_cpl_blk)}})); + assign ex0_cr_hole_d = rv1_cr_hole_q & (~(arb_release_itag_vld_q & {`THREADS{(~ctl_lsq_stq_cpl_blk)}})); + + // RV release itag + assign arb_release_itag_vld_d = cr_ack | (arb_release_itag_vld_q & {`THREADS{ctl_lsq_stq_cpl_blk}}); + assign stq_arb_release_itag_vld = |(arb_release_itag_vld_q) & (~ctl_lsq_stq_cpl_blk); + assign stq_arb_release_itag = cpl_ready_itag_final; + assign stq_arb_release_tid = cpl_ready_tid_final; + + assign stcx_pass = an_ac_stcx_complete & an_ac_stcx_pass; + + // Delay icswx back_inv comes a cycle late + assign cr_we_d = icswxr_ack_q | |(resv_ack); + + assign cr_thrd = icswxr_ack_val | resv_ack; + + assign cr_xer_so = |(xu_lq_xer_cp_rd & cr_thrd); + assign cr_stcx_pass = |((stcx_pass | stcx_pass_q) & cr_thrd); + + assign cr_wd_d = (icswxr_ack_q == 1'b1) ? {an_ac_back_inv_addr[58:60], 1'b0} : + {2'b00, cr_stcx_pass, cr_xer_so}; + assign lq_xu_cr_l2_we = cr_we_q; + assign lq_xu_cr_l2_wa = cr_wa_q; + assign lq_xu_cr_l2_wd = cr_wd_q; + + //------------------------------------------------------------------------------ + // Performance Events + //------------------------------------------------------------------------------ + assign icswxr_thrd_busy_d = icswxr_ack_val & {`THREADS{ an_ac_back_inv_addr[59]}}; + assign icswxr_thrd_nbusy_d = icswxr_ack_val & {`THREADS{~an_ac_back_inv_addr[59]}}; + assign stcx_thrd_fail_d = resv_ack & ~icswxr_ack_val & {`THREADS{~cr_stcx_pass}}; + assign stq3_cmmt_attmpt_d = stq2_cmmt_val_q; + assign stq_need_hole_d = rv_hold | stq_cpl_need_hold_q; + assign perf_stq_icswxr_busy = icswxr_thrd_busy_q; + assign perf_stq_icswxr_nbusy = icswxr_thrd_nbusy_q; + assign perf_stq_stcx_fail = stcx_thrd_fail_q; + assign perf_stq_cmmt_attmpt = stq3_cmmt_attmpt_q; + assign perf_stq_cmmt_val = stq3_cmmt_val_q; + assign perf_stq_need_hole = stq_need_hole_q; + + assign lsq_perv_stq_events = {perf_stq_cmmt_attmpt, perf_stq_cmmt_val, perf_stq_need_hole, + perf_stq_stcx_fail, perf_stq_icswxr_nbusy, perf_stq_icswxr_busy}; + + //------------------------------------------------------------------------------ + // STQ Commit Pipe + //------------------------------------------------------------------------------ + assign rv_lq_vld_d = |(rv_lq_vld); + assign rv_lq_ld_vld_d = |(rv_lq_vld) & rv_lq_isLoad; + assign ex0_dir_rd_val_d = ctl_lsq_rv1_dir_rd_val; + + assign stq1_cmmt_act = stq2_cmmt_reject | stq1_cmmt_val | stq1_cmmt_flushed | stq_push_down; + assign stq1_cclass = {stq1_p_addr[64 - (`DC_SIZE - 3):56], (stq1_p_addr[57] | spr_xucr0_cls_q)}; + assign stq1_rel_blk_cclass = (stq1_cclass == ldq_stq_stq4_cclass) & ldq_stq_stq4_dir_upd; + assign stq1_binv1_cclass_m = (stq1_cclass == ex1_binv_addr_q) & ex1_binv_val_q; + assign stq1_binv2_cclass_m = (stq1_cclass == ex2_binv_addr_q) & ex2_binv_val_q; + assign stq1_binv3_cclass_m = (stq1_cclass == ex3_binv_addr_q) & ex3_binv_val_q; + assign stq1_binv_wclrall = (ex1_binv_val_q | ex2_binv_val_q | ex3_binv_val_q) & stq1_wclr_all; + assign stq1_binv_blk_cclass = stq1_binv1_cclass_m | stq1_binv2_cclass_m | stq1_binv3_cclass_m | stq1_binv_wclrall; + assign stq2_binv_blk_cclass_d = stq1_binv_blk_cclass | stq1_rel_blk_cclass; + + assign stq1_cmmt_val = (~stq2_cmmt_reject) & |(stqe_ready_state & stq1_cmmt_ptr_q); + assign stq1_cmmt_flushed = (~stq2_cmmt_reject) & |(stqe_flushed_q[0:`STQ_ENTRIES - 1] & stq1_cmmt_ptr_q); + assign stq1_cmmt_dreq_val = |(stqe_dreq_val_q[0:`STQ_ENTRIES - 1] & stq1_cmmt_ptr_q); + assign stq1_cmmt_dvc_val = |(stqe_dvc_int_det & stq1_cmmt_ptr_q); + assign stq1_cmmt_send_l2 = |(stqe_send_l2_q[0:`STQ_ENTRIES - 1] & stq1_cmmt_ptr_q); + assign stq3_cmmt_send_l2 = |(stqe_send_l2_q[0:`STQ_ENTRIES - 1] & stq3_cmmt_ptr_q); + assign stq3_cmmt_dreq_val = |(stqe_dreq_val_q[0:`STQ_ENTRIES - 1] & stq3_cmmt_ptr_q); + assign stq3_cmmt_dvc_val = |(stqe_dvc_int_det & stq3_cmmt_ptr_q); + assign stq2_cmmt_ptr_remove = stq2_cmmt_ptr_q & (stqe_dreq_val_q[0:`STQ_ENTRIES - 1] | stqe_dvc_int_det | ((~stqe_need_ext_ack_q[0:`STQ_ENTRIES - 1]))); + + assign stq1_cmmt_ptr_r1 = {1'b0, stq1_cmmt_ptr_q[0:`STQ_ENTRIES - 2]}; + assign stq1_cmmt_ptr_l1 = {stq1_cmmt_ptr_q[1:`STQ_ENTRIES - 1], ((~(|(stq1_cmmt_ptr_q))))}; + assign stq2_cmmt_ptr_l1 = {stq2_cmmt_ptr_q[1:`STQ_ENTRIES - 1], ((~(|(stq2_cmmt_ptr_q))))}; + + assign stq1_cmmt_ptr_sel = {stq2_cmmt_reject, (stq1_cmmt_val | stq1_cmmt_flushed), stq_push_down}; + // "000" + + assign stq1_cmmt_ptr_d = (stq1_cmmt_ptr_sel == 3'b100) ? stq2_cmmt_ptr_q : + (stq1_cmmt_ptr_sel == 3'b110) ? stq2_cmmt_ptr_q : + (stq1_cmmt_ptr_sel == 3'b101) ? stq2_cmmt_ptr_l1 : + (stq1_cmmt_ptr_sel == 3'b111) ? stq2_cmmt_ptr_l1 : + (stq1_cmmt_ptr_sel == 3'b001) ? stq1_cmmt_ptr_l1 : + (stq1_cmmt_ptr_sel == 3'b011) ? stq1_cmmt_ptr_q : + (stq1_cmmt_ptr_sel == 3'b010) ? stq1_cmmt_ptr_r1 : + stq1_cmmt_ptr_q; + assign stq2_cmmt_ptr_d = (stq_push_down == 1'b0) ? stq1_cmmt_ptr_q : + stq1_cmmt_ptr_l1; + + assign stq3_cmmt_ptr_d = (stq_push_down == 1'b0) ? stq2_cmmt_ptr_q : + {stq2_cmmt_ptr_q[1:`STQ_ENTRIES - 1], ((~(|(stq2_cmmt_ptr_q))))}; + + assign stq4_cmmt_ptr_d = (stq_push_down == 1'b0) ? stq3_cmmt_ptr_q : + {stq3_cmmt_ptr_q[1:`STQ_ENTRIES - 1], ((~(|(stq3_cmmt_ptr_q))))}; + + assign stq5_cmmt_ptr_d = (stq_push_down == 1'b0) ? stq4_cmmt_ptr_q : + {stq4_cmmt_ptr_q[1:`STQ_ENTRIES - 1], ((~(|(stq4_cmmt_ptr_q))))}; + + assign stq6_cmmt_ptr_d = (stq_push_down == 1'b0) ? stq5_cmmt_ptr_q : + {stq5_cmmt_ptr_q[1:`STQ_ENTRIES - 1], ((~(|(stq5_cmmt_ptr_q))))}; + + // Fix for mftgpr colliding with a store update form issued by RV + // every other store commit request should only be rejected if + // RV issued a load + // XUDBG0 command in the LQ pipeline + assign stq2_reject_rv_coll = (rv_lq_vld_q & stq2_mftgpr_val_q) | (rv_lq_ld_vld_q) | ex0_dir_rd_val_q; + assign stq2_reject_dci_d = stq_reject_dci_coll; + assign stq2_reject_val = stq2_reject_rv_coll | stq2_binv_blk_cclass_q | stq2_reject_dci_q | ctl_lsq_stq4_perr_reject; + assign stq2_cmmt_reject = stq2_cmmt_val_q & stq2_reject_val; + assign stq3_cmmt_reject_d = stq2_cmmt_reject; + assign stq2_cmmt_val = stq2_cmmt_val_q & (~stq2_reject_val); + assign stq_stq2_blk_req = stq2_cmmt_reject; + + assign stqe0_icswxdot_val = stqe_is_icswxr_q[0] & (stqe_ttype_q[0] == 6'b100111); + + generate + begin : xhdl8 + genvar t; + for (t = 0; t <= `THREADS - 1; t = t + 1) + begin : ext_ack_queue_gen + assign ext_ack_queue_v_d[t] = (stq7_cmmt_val_q & stqe_need_ext_ack_q[0] & stqe_thrd_id_q[0][t] & (~stqe_ack_rcvd_q[0])) | + (ext_ack_queue_v_q[t] & (~any_ack_val[t])); + + assign ext_ack_queue_sync_d[t] = (stq7_cmmt_val_q & stqe_need_ext_ack_q[0] & stqe_thrd_id_q[0][t] & stqe_is_sync_q[0]) | + (ext_ack_queue_sync_q[t] & (~any_ack_val[t])); + + assign ext_ack_queue_stcx_d[t] = (stq7_cmmt_val_q & stqe_need_ext_ack_q[0] & stqe_thrd_id_q[0][t] & stqe_is_resv_q[0]) | + (ext_ack_queue_stcx_q[t] & (~any_ack_val[t])); + + assign ext_ack_queue_icswxr_d[t] = (stq7_cmmt_val_q & stqe_need_ext_ack_q[0] & stqe_thrd_id_q[0][t] & stqe_is_icswxr_q[0] & stqe0_icswxdot_val) | + (ext_ack_queue_icswxr_q[t] & (~any_ack_val[t])); + + assign ext_ack_queue_itag_d[t] = ((stq7_cmmt_val_q & stqe_need_ext_ack_q[0] & stqe_thrd_id_q[0][t]) == 1'b1) ? stqe_itag_q[0] : + ext_ack_queue_itag_q[t]; + + assign ext_ack_queue_cr_wa_d[t] = ((stq7_cmmt_val_q & stqe_need_ext_ack_q[0] & stqe_thrd_id_q[0][t]) == 1'b1) ? stqe_tgpr_q[0][AXU_TARGET_ENC - (`CR_POOL_ENC + `THREADS_POOL_ENC):AXU_TARGET_ENC - 1] : + ext_ack_queue_cr_wa_q[t]; + + assign ext_ack_queue_dacrw_det_d[t] = ((stq7_cmmt_val_q & stqe_need_ext_ack_q[0] & stqe_thrd_id_q[0][t]) == 1'b1) ? stqe_dacrw_q[0] : + ext_ack_queue_dacrw_det_q[t]; + + assign ext_ack_queue_dacrw_rpt_d[t] = ((stq7_cmmt_val_q & stqe_need_ext_ack_q[0] & stqe_thrd_id_q[0][t]) == 1'b1) ? stqe_dvc_int_det[0] : + ext_ack_queue_dacrw_rpt_q[t]; + end + end + endgenerate + + + always @(*) + begin: ext_act_queue_thrd_sel_proc + reg [0:`ITAG_SIZE_ENC-1] itag; + reg [0:`CR_POOL_ENC+`THREADS_POOL_ENC-1] cr_wa; + reg [0:3] dacrw_det; + reg dacrw_rpt; + integer t; + itag = 0; + cr_wa = 0; + dacrw_det = 0; + dacrw_rpt = 0; + + for (t = 0; t <= `THREADS - 1; t = t + 1) + begin + itag = (ext_ack_queue_itag_q[t] & {`ITAG_SIZE_ENC{(any_ack_val[t] & ext_ack_queue_v_q[t])}}) | + (stq_ext_act_itag & {`ITAG_SIZE_ENC{(any_ack_val[t] & (~ext_ack_queue_v_q[t]))}}) | itag; + + cr_wa = (ext_ack_queue_cr_wa_q[t] & {`CR_POOL_ENC+`THREADS_POOL_ENC{(cr_thrd[t] & ext_ack_queue_v_q[t])}}) | + (stq_ext_act_cr_wa & {`CR_POOL_ENC+`THREADS_POOL_ENC{(cr_thrd[t] & (~ext_ack_queue_v_q[t]))}}) | cr_wa; + + dacrw_det = (ext_ack_queue_dacrw_det_q[t] & {4{(any_ack_val[t] & ext_ack_queue_v_q[t])}}) | + (stq_ext_act_dacrw_det & {4{(any_ack_val[t] & (~ext_ack_queue_v_q[t]))}}) | dacrw_det; + + dacrw_rpt = (ext_ack_queue_dacrw_rpt_q[t] & (any_ack_val[t] & ext_ack_queue_v_q[t])) | + (stq_ext_act_dacrw_rpt & (any_ack_val[t] & (~ext_ack_queue_v_q[t]))) | dacrw_rpt; + end + + ext_act_queue_itag = itag; + cr_wa_d = cr_wa; + ext_act_queue_dacrw_det = dacrw_det; + ext_act_queue_dacrw_rpt = dacrw_rpt; + end + + // Count number of flushes, force a hole once the threshold is reached + assign stq2_rtry_cnt_act = stq2_cmmt_val_q | rtry_cnt_reset; + assign stq2_rtry_cnt_incr = stq2_rtry_cnt_q + 3'b001; + + assign stq2_rtry_cnt_d = (((~(stq2_reject_rv_coll)) | rtry_cnt_reset) == 1'b1) ? 3'b110 : + stq2_rtry_cnt_incr; + assign rtry_cnt_reset = stq2_rtry_cnt_q == 3'b111; + assign rv_hold = (stq2_rtry_cnt_incr == 3'b111) & (stq2_cmmt_val_q & stq2_reject_rv_coll); + assign stq_hold_all_req = rv_hold | |(rv0_cr_hole_q) | stq_cpl_need_hold_q; + assign ex5_stq_set_hold = |(stqe_qHit_held_set & (~stqe_qHit_held_clr[0:`STQ_ENTRIES - 1])); + assign set_hold_thread = ex5_req_thrd_id_q & {`THREADS{ex5_stq_set_hold}}; + assign stq_rv_set_hold = ex5_stq_set_hold; + assign thrd_held_d = set_hold_thread | (thrd_held_q & (~clr_hold_thread)); + assign clr_hold_thread = (thrd_held_q & {`THREADS{ |(stqe_qHit_held_clr[0:`STQ_ENTRIES - 1] & stqe_qHit_held_q)}}) | + (thrd_held_q & {`THREADS{ |(any_ack_val_ok_q)}}); + assign stq_rv_clr_hold = clr_hold_thread; + + // STQ Commit Valids + assign lsq_ctl_stq1_val = stq1_cmmt_val & (~(stq1_cmmt_dreq_val | stq1_cmmt_dvc_val)); + assign lsq_dat_stq1_val = stq1_cmmt_val & (~(stq1_cmmt_dreq_val | stq1_cmmt_dvc_val)); + assign stq_ctl_stq1_stg_act = |(stqe_ready_ctl_act) & ~stq1_rel_blk_cclass; + assign stq_dat_stq1_stg_act = |(stqe_ready_dat_act); + assign stq_arb_st_req_avail = stq1_cmmt_val & (~(stq1_cmmt_dreq_val | stq1_cmmt_dvc_val)) & stq1_cmmt_send_l2; + assign stq_arb_stq3_req_val = stq3_cmmt_val_q & (~(stq3_cmmt_dreq_val | stq3_cmmt_dvc_val)) & stq3_cmmt_send_l2; + assign stq_arb_stq3_cmmt_val = stq3_cmmt_val_q; + assign stq_arb_stq3_cmmt_reject = stq3_cmmt_reject_q; + + // Temp fix + assign sq_iu_credit_free = credit_free_q; + // fix for requests that have DREQ_VAL and NEED_EXT_ACK set, also want to drop requests if DVC_INT_EN is set + assign credit_free_d = (stq2_thrd_id & {`THREADS{ ((stq2_cmmt_val & |(stq2_cmmt_ptr_remove)) | stq2_cmmt_flushed_q)}}) | any_ack_val; + + assign lq_iu_icbi_addr = icbi_addr_q; + assign lq_iu_icbi_val = icbi_val_q; + // dont want to send ICBI request to the IU if DREQ_VAL is set + assign icbi_val_d = stq2_thrd_id & {`THREADS{ (stq2_cmmt_val & |(stq2_cmmt_ptr_q & stqe_is_icbi_q[0:`STQ_ENTRIES - 1] & (~stqe_dreq_val_q[0:`STQ_ENTRIES - 1]))) }}; + + assign stq2_dci_val_d = stq1_cmmt_val & (stq1_ttype == 6'b101111); + assign stq2_cmmt_dci_val = stq2_cmmt_val & stq2_dci_val_q & |(stq2_cmmt_ptr_q & (~stqe_dreq_val_q[0:`STQ_ENTRIES - 1])); + assign stq3_cmmt_dci_val_d = stq2_cmmt_dci_val; + assign stq4_cmmt_dci_val_d = stq3_cmmt_dci_val_q; + assign stq5_cmmt_dci_val_d = stq4_cmmt_dci_val_q; + assign stq_reject_dci_coll = stq2_cmmt_dci_val; + assign stq_dci_inprog = stq3_cmmt_dci_val_q | stq4_cmmt_dci_val_q | stq5_cmmt_dci_val_q; + assign stq2_ici_val_d = (stq1_ttype == 6'b101110); + assign ici_val_d = stq2_cmmt_val & stq2_ici_val_q & |(stq2_cmmt_ptr_q & (~stqe_dreq_val_q[0:`STQ_ENTRIES - 1])); + assign lq_iu_ici_val = ici_val_q; + + // need to set XUCR0[CUL] for a dcblc/icblc that is being dropped + assign stq3_dcblc_instr = (stq3_ttype == 6'b100101); + assign stq3_icblc_instr = (stq3_ttype == 6'b100100); + assign stq4_xucr0_cul_d = stq3_cmmt_val_q & stq3_cmmt_dreq_val & (stq3_dcblc_instr | stq3_icblc_instr); + + // Kill the pointer for instructions that require an external ack + // Want to delete the entry if DVC_INT_EN is set + + assign stq7_cmmt_ptr_d = (stq_push_down == 1'b0) ? stq6_cmmt_ptr_q : + {stq6_cmmt_ptr_q[1:`STQ_ENTRIES - 1], 1'b0}; + + assign stq7_entry_delete[0:`STQ_ENTRIES - 1] = (stq2_cmmt_ptr_q & {`STQ_ENTRIES{stq2_cmmt_flushed_q}}) | + (stq7_cmmt_ptr_q & {`STQ_ENTRIES{stq7_cmmt_val_q}}); + + assign stq_push_down = stq7_cmmt_flushed_q | (stq7_cmmt_val_q & stq7_cmmt_ptr_q[0]); + + // since the stq is pushed down in stq7, the stq3 commit pointer will never be higher than 4 + + assign stq_arb_stq3_cTag[2:4] = (stq3_cmmt_ptr_q[0:4] == 5'b10000) ? 3'b000 : + (stq3_cmmt_ptr_q[0:4] == 5'b01000) ? 3'b001 : + (stq3_cmmt_ptr_q[0:4] == 5'b00100) ? 3'b010 : + (stq3_cmmt_ptr_q[0:4] == 5'b00010) ? 3'b011 : + (stq3_cmmt_ptr_q[0:4] == 5'b00001) ? 3'b100 : + 3'b111; + assign stq_arb_stq3_cTag[0:1] = 2'b00; + + assign stq1_mftgpr_val = (stq1_ttype == 6'b111000); + assign stq2_mftgpr_val_d = stq1_mftgpr_val; + assign lsq_dat_stq1_mftgpr_val = stq1_mftgpr_val; + assign lsq_ctl_stq1_mftgpr_val = stq1_mftgpr_val; + assign lsq_ctl_stq1_mfdpf_val = (stq1_ttype == 6'b011000); + assign lsq_ctl_stq1_mfdpa_val = (stq1_ttype == 6'b010000); + assign lsq_ctl_stq1_dci_val = (stq1_ttype == 6'b101111); + assign stq_arb_stq3_ttype = stq3_ttype; + assign stq_arb_stq3_tid = stq3_tid_enc; + assign lsq_ctl_stq4_xucr0_cul = stq4_xucr0_cul_q; + + // Generate Encode Thread ID + always @(*) + begin: tidMulti + reg [0:1] stqTid; + integer tid; + stqTid = 0; + for (tid = 0; tid <= `THREADS - 1; tid = tid + 1) + stqTid = (tid & stq3_tid[tid]) | stqTid; + + stq3_tid_enc = stqTid; + end + + //------------------------------------------------------------------------------ + //------------------------------------------------------------------------------ + // mtspr_trace Logic + //------------------------------------------------------------------------------ + //------------------------------------------------------------------------------ + + // Encode Thread ID + + always @(*) + begin: tidEnc + reg [0:1] tenc; + integer tid; + tenc = 0; + for (tid = 0; tid <= `THREADS - 1; tid = tid + 1) + tenc = (tid & ex4_req_thrd_id_q[tid]) | tenc; + + ex4_thrd_id_enc = tenc; + end + + // 32bit Real Address MTSPR TRACE Muxing + generate + if (`REAL_IFAR_WIDTH == 32) + begin : ra32bit + assign ex4_p_addr_ovrd[49:63] = ctl_lsq_ex4_p_addr[49:63]; + + assign ex4_p_addr_ovrd[32:33] = (ctl_lsq_ex4_mtspr_trace == 1'b0) ? ctl_lsq_ex4_p_addr[32:33] : + ex4_thrd_id_enc; + + assign ex4_p_addr_ovrd[34:43] = (ctl_lsq_ex4_mtspr_trace == 1'b0) ? ctl_lsq_ex4_p_addr[34:43] : + ctl_lsq_ex4_p_addr[50:59]; + + assign ex4_p_addr_ovrd[44] = (ctl_lsq_ex4_mtspr_trace == 1'b0) ? ctl_lsq_ex4_p_addr[44] : + 1'b0; + + assign ex4_p_addr_ovrd[45] = (ctl_lsq_ex4_mtspr_trace == 1'b0) ? ctl_lsq_ex4_p_addr[45] : + ctl_lsq_ex4_p_addr[60]; + + assign ex4_p_addr_ovrd[46] = (ctl_lsq_ex4_mtspr_trace == 1'b0) ? ctl_lsq_ex4_p_addr[46] : + ctl_lsq_ex4_p_addr[63]; + + assign ex4_p_addr_ovrd[47] = (ctl_lsq_ex4_mtspr_trace == 1'b0) ? ctl_lsq_ex4_p_addr[47] : + ctl_lsq_ex4_p_addr[62]; + assign ex4_p_addr_ovrd[48] = (ctl_lsq_ex4_mtspr_trace == 1'b0) ? ctl_lsq_ex4_p_addr[48] : + ctl_lsq_ex4_p_addr[61]; + end + endgenerate + + // greater than 32bit Real Address MTSPR TRACE Muxing + generate + if (`REAL_IFAR_WIDTH > 32) + begin : raN32bit + assign ex4_p_addr_ovrd[64 - `REAL_IFAR_WIDTH:29] = ctl_lsq_ex4_p_addr[64 - `REAL_IFAR_WIDTH:29]; + assign ex4_p_addr_ovrd[49:63] = ctl_lsq_ex4_p_addr[49:63]; + + assign ex4_p_addr_ovrd[30:31] = (ctl_lsq_ex4_mtspr_trace == 1'b0) ? ctl_lsq_ex4_p_addr[30:31] : + an_ac_coreid; + + assign ex4_p_addr_ovrd[32:33] = (ctl_lsq_ex4_mtspr_trace == 1'b0) ? ctl_lsq_ex4_p_addr[32:33] : + ex4_thrd_id_enc; + + assign ex4_p_addr_ovrd[34:43] = (ctl_lsq_ex4_mtspr_trace == 1'b0) ? ctl_lsq_ex4_p_addr[34:43] : + ctl_lsq_ex4_p_addr[50:59]; + + assign ex4_p_addr_ovrd[44] = (ctl_lsq_ex4_mtspr_trace == 1'b0) ? ctl_lsq_ex4_p_addr[44] : + 1'b0; + + assign ex4_p_addr_ovrd[45] = (ctl_lsq_ex4_mtspr_trace == 1'b0) ? ctl_lsq_ex4_p_addr[45] : + ctl_lsq_ex4_p_addr[60]; + + assign ex4_p_addr_ovrd[46] = (ctl_lsq_ex4_mtspr_trace == 1'b0) ? ctl_lsq_ex4_p_addr[46] : + ctl_lsq_ex4_p_addr[63]; + + assign ex4_p_addr_ovrd[47] = (ctl_lsq_ex4_mtspr_trace == 1'b0) ? ctl_lsq_ex4_p_addr[47] : + ctl_lsq_ex4_p_addr[62]; + assign ex4_p_addr_ovrd[48] = (ctl_lsq_ex4_mtspr_trace == 1'b0) ? ctl_lsq_ex4_p_addr[48] : + ctl_lsq_ex4_p_addr[61]; + end + endgenerate + + //------------------------------------------------------------------------------ + //------------------------------------------------------------------------------ + // STQ Address Entries + //------------------------------------------------------------------------------ + //------------------------------------------------------------------------------ + + // the offset is determined by the size of the store operation in EX3 + assign ex3_opsize_1hot[0] = ctl_lsq_ex3_opsize == 3'b101; //8B + assign ex3_opsize_1hot[1] = ctl_lsq_ex3_opsize == 3'b100; //4B + assign ex3_opsize_1hot[2] = ctl_lsq_ex3_opsize == 3'b010; //2B + assign ex3_rotcmp2_fld = {1'b0, (3'b100 & {3{ex3_opsize_1hot[0]}})}; + assign ex3_rotcmp3_fld = {1'b0, ((3'b110 & {3{ ex3_opsize_1hot[0]}}) | (3'b010 & {3{ex3_opsize_1hot[1]}}))}; + assign stq_rotcmp[0:3] = ctl_lsq_ex3_p_addr[60:63]; + assign stq_rotcmp[4:7] = stq_rotcmp[0:3] + 4'b0010; // + 2; + assign stq_rotcmp[8:11] = stq_rotcmp[0:3] + ex3_rotcmp2_fld; + assign stq_rotcmp[12:15] = stq_rotcmp[0:3] + ex3_rotcmp3_fld; + + // create dummy blank stq entry to pushdown on the top of the queue + assign stqe_thrd_id_q[`STQ_ENTRIES] = 0; + assign stqe_itag_q[`STQ_ENTRIES] = 0; + assign stqe_lmqhit_q[`STQ_ENTRIES] = 0; + assign ex5_older_ldmiss_q[`STQ_ENTRIES] = 0; + assign stqe_rotcmp_q[`STQ_ENTRIES] = 0; + assign stqe_byte_en_q[`STQ_ENTRIES] = 0; + assign stqe_addr_q[`STQ_ENTRIES] = 0; + assign stqe_wimge_q[`STQ_ENTRIES] = 0; + assign stqe_opsize_q[`STQ_ENTRIES] = 0; + assign stqe_ttype_q[`STQ_ENTRIES] = 0; + assign stqe_usr_def_q[`STQ_ENTRIES] = 0; + assign stqe_l_fld_q[`STQ_ENTRIES] = 0; + assign stqe_tgpr_q[`STQ_ENTRIES] = 0; + assign stqe_dvc_en_q[`STQ_ENTRIES] = 0; + assign stqe_dacrw_q[`STQ_ENTRIES] = 0; + assign stqe_data1_q[`STQ_ENTRIES] = 0; + assign stqe_data1_mux[`STQ_ENTRIES] = 0; + assign ex5_set_stq_q[`STQ_ENTRIES] = 0; + assign ex4_set_stq_q[`STQ_ENTRIES] = 0; + assign stqe_alloc_q[`STQ_ENTRIES] = 0; + assign stqe_flushed_q[`STQ_ENTRIES] = 0; + assign stqe_ack_rcvd_q[`STQ_ENTRIES] = 0; + assign stq7_entry_delete[`STQ_ENTRIES] = 0; + assign stqe_have_cp_next_q[`STQ_ENTRIES] = 0; + assign stqe_addr_val_q[`STQ_ENTRIES] = 0; + assign stqe_fwd_addr_val_q[`STQ_ENTRIES] = 0; + assign stqe_ready_sent_q[`STQ_ENTRIES] = 0; + assign stqe_need_ready_ptr_q[`STQ_ENTRIES] = 0; + assign stqe_compl_rcvd_q[`STQ_ENTRIES] = 0; + assign stqe_compl_rcvd[`STQ_ENTRIES] = 0; + assign cp_i0_itag_cmp[`STQ_ENTRIES] = 0; + assign cp_i1_itag_cmp[`STQ_ENTRIES] = 0; + assign stqe_flushed[`STQ_ENTRIES] = 0; + assign stqe_alloc_flushed[`STQ_ENTRIES] = 0; + assign stqe_need_ext_ack_q[`STQ_ENTRIES] = 0; + assign stqe_blk_loads_q[`STQ_ENTRIES] = 0; + assign stqe_all_thrd_chk_q[`STQ_ENTRIES] = 0; + assign stqe_cline_chk_q[`STQ_ENTRIES] = 0; + assign stqe_byte_swap_q[`STQ_ENTRIES] = 0; + assign stqe_is_store_q[`STQ_ENTRIES] = 0; + assign stqe_is_sync_q[`STQ_ENTRIES] = 0; + assign stqe_is_resv_q[`STQ_ENTRIES] = 0; + assign stqe_is_icswxr_q[`STQ_ENTRIES] = 0; + assign stqe_is_icbi_q[`STQ_ENTRIES] = 0; + assign stqe_is_inval_op_q[`STQ_ENTRIES] = 0; + assign stqe_dreq_val_q[`STQ_ENTRIES] = 0; + assign stqe_has_data_q[`STQ_ENTRIES] = 0; + assign stqe_send_l2_q[`STQ_ENTRIES] = 0; + assign stqe_watch_clr_q[`STQ_ENTRIES] = 0; + assign stqe_axu_val_q[`STQ_ENTRIES] = 0; + assign stqe_epid_val_q[`STQ_ENTRIES] = 0; + assign stqe_lock_clr_q[`STQ_ENTRIES] = 0; + assign stqe_data_val[`STQ_ENTRIES] = 0; + assign stqe_fxu1_dvcr_val[`STQ_ENTRIES] = 0; + assign stqe_dvcr_cmpr_q[`STQ_ENTRIES] = 2'b0; + assign stqe_data_nxt_q[`STQ_ENTRIES] = 0; + assign ex3_stq_data_val[`STQ_ENTRIES] = 0; + assign stqe_data_val_q[`STQ_ENTRIES] = 0; + assign stqe_illeg_lswx_q[`STQ_ENTRIES] = 0; + assign stqe_strg_noop_q[`STQ_ENTRIES] = 0; + assign ex3_agecmp[`STQ_ENTRIES] = 0; + assign stqe_qHit_held_mux[`STQ_ENTRIES] = 0; + assign stqe_held_early_clr_q[`STQ_ENTRIES] = 0; + assign set_hold_early_clear[`STQ_ENTRIES] = 0; + assign stqe_qHit_held_clr[`STQ_ENTRIES] = 0; + assign stq_cp_next_val[`STQ_ENTRIES] = 0; + assign stqe_odq_resolved_q[`STQ_ENTRIES] = 0; + assign ex5_qHit_set_oth_q[`STQ_ENTRIES] = 0; + assign ex5_qHit_set_miss[`STQ_ENTRIES] = 0; + + always @(stq_push_down) + begin: dummy + stq_cp_next_itag[`STQ_ENTRIES] = 0; + set_stqe_odq_resolved[`STQ_ENTRIES] = 0; + end + + + always @(*) + begin: odq_sttagMux + reg [0:`STQ_ENTRIES-1] odq_resolved_ptr; + integer stq; + odq_resolved_ptr = 0; + for (stq = 0; stq <= `STQ_ENTRIES - 1; stq = stq + 1) + odq_resolved_ptr = (stq_tag_ptr_q[stq] & {`STQ_ENTRIES{odq_stq_stTag[stq]}}) | odq_resolved_ptr; + + set_stqe_odq_resolved[0:`STQ_ENTRIES - 1] = odq_resolved_ptr & {`STQ_ENTRIES{odq_stq_resolved}}; + end + + generate + begin : xhdl9 + genvar i; + for (i = 0; i <= `STQ_ENTRIES - 1; i = i + 1) + begin : stq_addr_entry_gen + + assign stqe_odq_resolved_d[i] = (stq_push_down == 1'b0) ? (set_stqe_odq_resolved[i] | stqe_odq_resolved_q[i]) & (~stq7_entry_delete[i]) : + (set_stqe_odq_resolved[i + 1] | stqe_odq_resolved_q[i + 1]) & (~stq7_entry_delete[i + 1]); + + assign stqe_state[i] = {stqe_alloc_q[i], + stqe_addr_val_q[i], + (stqe_data_val_q[i] | (~stqe_has_data_q[i])), + (stqe_compl_rcvd_q[i] | stqe_need_ext_ack_q[i]), + (stqe_have_cp_next_q[i] | (~stqe_need_ext_ack_q[i])), + arb_stq_cred_avail, + stqe_odq_resolved_q[i], + (~(|(stqe_lmqhit_q[i]))), + (~(ldq_stq_rel1_blk_store | stq_dci_inprog))}; + + assign stqe_ready_state[i] = (~stqe_flushed_q[i]) & &(stqe_state[i]); + + assign stqe_ready_ctl_act[i] = &({stqe_alloc_q[i], + stqe_addr_val_q[i], + (stqe_data_val_q[i] | (~stqe_has_data_q[i])), + (stqe_compl_rcvd_q[i] | stqe_need_ext_ack_q[i]), + (stqe_have_cp_next_q[i] | (~stqe_need_ext_ack_q[i])), + (~(|(stqe_lmqhit_q[i]))), + (~stqe_flushed_q[i])}); + + assign stqe_ready_dat_act[i] = &({stqe_alloc_q[i], + stqe_addr_val_q[i], + (stqe_data_val_q[i]), + (stqe_compl_rcvd_q[i] | stqe_need_ext_ack_q[i]), + (stqe_have_cp_next_q[i] | (~stqe_need_ext_ack_q[i])), + (~(|(stqe_lmqhit_q[i]))), + (~stqe_flushed_q[i])}); + + assign stqe_lmqhit_d[i] = (stq_push_down == 1'b0) ? ((ldq_stq_ex5_ldm_hit & {`LMQ_ENTRIES{ex5_set_stq_q[i]}}) | + (ldq_stq_ex5_ldm_entry & {`LMQ_ENTRIES{ex5_older_ldmiss_q[i]}}) | + stqe_lmqhit_q[i]) & (~ldq_stq_ldm_cpl) : + ((ldq_stq_ex5_ldm_hit & {`LMQ_ENTRIES{ex5_set_stq_q[i + 1]}}) | + (ldq_stq_ex5_ldm_entry & {`LMQ_ENTRIES{ex5_older_ldmiss_q[i + 1]}}) | + stqe_lmqhit_q[i + 1]) & (~ldq_stq_ldm_cpl); + + assign stqe_wrt_new[i] = (stqe_alloc_i0_wrt_ptr[i] & stq_alloc_val[0]) | (stqe_alloc_i1_wrt_ptr[i] & stq_alloc_val[1]); + + assign stqe_thrd_id_d[i] = (stq_alloc_thrd_id0 & {`THREADS{stqe_alloc_i0_wrt_ptr[i]}}) | + (stq_alloc_thrd_id1 & {`THREADS{stqe_alloc_i1_wrt_ptr[i]}}) | + (stqe_thrd_id_q[i + 1] & {`THREADS{(~stqe_wrt_new[i])}}); + + assign stqe_tid_inuse[i] = stqe_thrd_id_q[i] & {`THREADS{stqe_alloc_q[i]}}; + + assign stqe_itag_act[i] = stqe_wrt_new[i] | stq_push_down; + + assign stqe_alloc_d[i] = stqe_wrt_new[i] | + (stqe_alloc_q[i + 1] & (~stq7_entry_delete[i + 1]) & stq_push_down) | + (stqe_alloc_q[i] & (~stq7_entry_delete[i]) & (~stq_push_down)); + + assign stqe_itag_d[i] = (stqe_alloc_itag0 & {`ITAG_SIZE_ENC{(stqe_alloc_i0_wrt_ptr[i] & stq_alloc_val[0])}}) | + (stqe_alloc_itag1 & {`ITAG_SIZE_ENC{(stqe_alloc_i1_wrt_ptr[i] & stq_alloc_val[1])}}) | + (stqe_itag_q[i + 1] & {`ITAG_SIZE_ENC{(~stqe_wrt_new[i])}}); + + // Report back to LDQ on LSWX status + assign ex3_data_val[i] = stqe_data_val_q[i] & (stqe_itag_q[i] == ex3_req_itag_q) & (stqe_thrd_id_q[i] == ex3_req_thrd_id_q) & (~(stqe_flushed_q[i] | stqe_compl_rcvd_q[i])); + assign ex3_illeg_lswx[i] = stqe_data_val_q[i] & (stqe_itag_q[i] == ex3_req_itag_q) & (stqe_thrd_id_q[i] == ex3_req_thrd_id_q) & ((~stqe_compl_rcvd_q[i])) & stqe_illeg_lswx_q[i]; + assign ex3_strg_noop[i] = stqe_data_val_q[i] & (stqe_itag_q[i] == ex3_req_itag_q) & (stqe_thrd_id_q[i] == ex3_req_thrd_id_q) & ((~stqe_compl_rcvd_q[i])) & stqe_strg_noop_q[i]; + + // ITAG Compare for CP_NEXT + assign stq_cp_next_val[i] = |(cp_next_val_q & stqe_thrd_id_q[i]); + + + always @(*) + begin: cp_next_itag_p + reg [0:`ITAG_SIZE_ENC-1] itag; + integer tid; + itag = 0; + for (tid = 0; tid <= `THREADS - 1; tid = tid + 1) + itag = (cp_next_itag_q[tid] & {`ITAG_SIZE_ENC{stqe_thrd_id_q[i][tid]}}) | itag; + + stq_cp_next_itag[i] = itag; + end + + assign stqe_have_cp_next_d[i] = (stq_push_down == 1'b0) ? ((stq_cp_next_val[i] & stqe_alloc_q[i] & (stqe_itag_q[i] == stq_cp_next_itag[i])) | + stqe_have_cp_next_q[i]) & (~(stq7_entry_delete[i] | stqe_flushed_q[i])) : + ((stq_cp_next_val[i + 1] & stqe_alloc_q[i + 1] & (stqe_itag_q[i + 1] == stq_cp_next_itag[i + 1])) | + stqe_have_cp_next_q[i + 1]) & (~(stq7_entry_delete[i + 1] | stqe_flushed_q[i + 1])); + + // Address Valid + assign ex3_set_stq[i] = (stq_push_down == 1'b0) ? ex3_streq_valid & stqe_alloc_q[i] & (stqe_itag_q[i] == ex3_req_itag_q) & + (stqe_thrd_id_q[i] == ex3_req_thrd_id_q) & (~(stqe_flushed_q[i] | stqe_compl_rcvd_q[i])) : + ex3_streq_valid & stqe_alloc_q[i + 1] & (stqe_itag_q[i + 1] == ex3_req_itag_q) & + (stqe_thrd_id_q[i + 1] == ex3_req_thrd_id_q) & (~(stqe_flushed_q[i + 1] | stqe_compl_rcvd_q[i + 1])); + + assign ex3_addr_act[i] = ex3_set_stq[i] | stq_push_down; + + assign ex4_addr_act[i] = ex4_set_stq_q[i] | stq_push_down; + + assign ex4_set_stq[i] = (ex4_set_stq_q[i] & (~stq_push_down)) | (ex4_set_stq_q[i + 1] & stq_push_down); + + assign ex5_addr_act[i] = ex5_set_stq_q[i] | stq_push_down; + + assign ex5_set_stq[i] = (ex5_set_stq_q[i] & (~stq_push_down)) | (ex5_set_stq_q[i + 1] & stq_push_down); + + assign stqe_rotcmp_d[i] = (ex3_set_stq[i] == 1'b1) ? stq_rotcmp : + stqe_rotcmp_q[i + 1]; + + assign stqe_byte_en_d[i] = (ex3_set_stq[i] == 1'b1) ? ctl_lsq_ex3_byte_en : + stqe_byte_en_q[i + 1]; + + assign stqe_addr_d[i] = (ex4_set_stq[i] == 1'b1) ? ex4_p_addr_ovrd : + stqe_addr_q[i + 1]; + + assign stqe_cline_chk_d[i] = (ex4_set_stq[i] == 1'b1) ? ctl_lsq_ex4_cline_chk : + stqe_cline_chk_q[i + 1]; + + assign stqe_wimge_d[i] = (ex4_set_stq[i] == 1'b1) ? ctl_lsq_ex4_wimge : + stqe_wimge_q[i + 1]; + + assign stqe_byte_swap_d[i] = (ex4_set_stq[i] == 1'b1) ? ctl_lsq_ex4_byte_swap : + stqe_byte_swap_q[i + 1]; + + assign stqe_opsize_d[i] = (ex4_set_stq[i] == 1'b1) ? ex4_req_opsize_q : + stqe_opsize_q[i + 1]; + + assign stqe_is_store_d[i] = (ex4_set_stq[i] == 1'b1) ? ctl_lsq_ex4_is_store : + stqe_is_store_q[i + 1]; + + assign stqe_is_sync_d[i] = (ex4_set_stq[i] == 1'b1) ? ctl_lsq_ex4_is_sync : + stqe_is_sync_q[i + 1]; + + assign stqe_is_resv_d[i] = (ex4_set_stq[i] == 1'b1) ? ctl_lsq_ex4_is_resv : + stqe_is_resv_q[i + 1]; + + assign stqe_is_icswxr_d[i] = (ex4_set_stq[i] == 1'b1) ? ctl_lsq_ex4_is_icswxr : + stqe_is_icswxr_q[i + 1]; + + assign stqe_is_icbi_d[i] = (ex4_set_stq[i] == 1'b1) ? ctl_lsq_ex4_is_icbi : + stqe_is_icbi_q[i + 1]; + + assign stqe_is_inval_op_d[i] = (ex4_set_stq[i] == 1'b1) ? ctl_lsq_ex4_is_inval_op : + stqe_is_inval_op_q[i + 1]; + + assign stqe_dreq_val_d[i] = (ex4_set_stq[i] == 1'b1) ? ctl_lsq_ex4_dreq_val : + stqe_dreq_val_q[i + 1]; + + assign stqe_has_data_d[i] = (ex4_set_stq[i] == 1'b1) ? ctl_lsq_ex4_has_data : + stqe_has_data_q[i + 1]; + + assign stqe_send_l2_d[i] = (ex4_set_stq[i] == 1'b1) ? ctl_lsq_ex4_send_l2 : + stqe_send_l2_q[i + 1]; + + assign stqe_watch_clr_d[i] = (ex4_set_stq[i] == 1'b1) ? ctl_lsq_ex4_watch_clr : + stqe_watch_clr_q[i + 1]; + + assign stqe_ttype_d[i] = (ex5_set_stq[i] == 1'b1) ? ctl_lsq_ex5_ttype : + stqe_ttype_q[i + 1]; + + assign stqe_axu_val_d[i] = (ex5_set_stq[i] == 1'b1) ? ctl_lsq_ex5_axu_val : + stqe_axu_val_q[i + 1]; + + assign stqe_epid_val_d[i] = (ex5_set_stq[i] == 1'b1) ? ctl_lsq_ex5_is_epid : + stqe_epid_val_q[i + 1]; + + assign stqe_usr_def_d[i] = (ex5_set_stq[i] == 1'b1) ? ctl_lsq_ex5_usr_def : + stqe_usr_def_q[i + 1]; + + assign stqe_lock_clr_d[i] = (ex5_set_stq[i] == 1'b1) ? ctl_lsq_ex5_lock_clr : + stqe_lock_clr_q[i + 1]; + + assign stqe_l_fld_d[i] = (ex5_set_stq[i] == 1'b1) ? ctl_lsq_ex5_l_fld : + stqe_l_fld_q[i + 1]; + + assign stqe_tgpr_d[i] = (ex5_set_stq[i] == 1'b1) ? ctl_lsq_ex5_tgpr : + stqe_tgpr_q[i + 1]; + + assign stqe_dvc_en_d[i] = (ex5_set_stq[i] == 1'b1) ? ctl_lsq_ex5_dvc : + stqe_dvc_en_q[i + 1]; + + assign stqe_dacrw_d[i] = (ex5_set_stq[i] == 1'b1) ? ctl_lsq_ex5_dacrw : + stqe_dacrw_q[i + 1]; + + assign stqe_addr_val_d[i] = (stq_push_down == 1'b0) ? ((ex5_streq_valid & ex5_set_stq_q[i]) | (stqe_addr_val_q[i] & (~stq7_entry_delete[i]))) & (~(stqe_flushed_q[i])) : + ((ex5_streq_valid & ex5_set_stq_q[i + 1]) | (stqe_addr_val_q[i + 1] & (~stq7_entry_delete[i + 1]))) & (~(stqe_flushed_q[i + 1])); + + // fix for forwarding store data to load + assign stqe_fwd_addr_val_d[i] = (stq_push_down == 1'b0) ? ((ex4_streq_valid & ex4_set_stq_q[i]) | (stqe_fwd_addr_val_q[i] & (~stq7_entry_delete[i]))) & (~(stqe_flushed_q[i])) : + ((ex4_streq_valid & ex4_set_stq_q[i + 1]) | (stqe_fwd_addr_val_q[i + 1] & (~stq7_entry_delete[i + 1]))) & (~(stqe_flushed_q[i + 1])); + + // This indicates ready has been sent to cpl + // Can be delated unless addl checking desired??? + assign stqe_ready_sent_d[i] = (stq_push_down == 1'b0) ? ((cpl_ready & stqe_need_ready_ptr_q[i]) | stqe_ready_sent_q[i] | stqe_need_ready_flushed[i]) & (~stq7_entry_delete[i]) : + ((cpl_ready & stqe_need_ready_ptr_q[i + 1]) | stqe_ready_sent_q[i + 1] | stqe_need_ready_flushed[i + 1]) & (~stq7_entry_delete[i + 1]); + + // Snoop Completion Busses for itags which are "complete" + assign stq_i0_comp_val[i] = |(cp_i0_completed_q & stqe_thrd_id_q[i]); + assign stq_i1_comp_val[i] = |(cp_i1_completed_q & stqe_thrd_id_q[i]); + + + always @(*) + begin: complete_itag_p + reg [0:`ITAG_SIZE_ENC-1] i0_itag; + reg [0:`ITAG_SIZE_ENC-1] i1_itag; + integer tid; + i0_itag = 0; + i1_itag = 0; + for (tid = 0; tid <= `THREADS - 1; tid = tid + 1) + begin + i0_itag = (cp_i0_completed_itag_q[tid] & {`ITAG_SIZE_ENC{stqe_thrd_id_q[i][tid]}}) | i0_itag; + i1_itag = (cp_i1_completed_itag_q[tid] & {`ITAG_SIZE_ENC{stqe_thrd_id_q[i][tid]}}) | i1_itag; + end + stq_i0_comp_itag[i] = i0_itag; + stq_i1_comp_itag[i] = i1_itag; + end + + assign cp_i0_itag_cmp[i] = stqe_alloc_q[i] & (stqe_itag_q[i] == stq_i0_comp_itag[i]) & (~stqe_compl_rcvd_q[i]); + assign cp_i1_itag_cmp[i] = stqe_alloc_q[i] & (stqe_itag_q[i] == stq_i1_comp_itag[i]) & (~stqe_compl_rcvd_q[i]); + + assign stqe_compl_rcvd[i] = ((stq_i0_comp_val[i] & cp_i0_itag_cmp[i] & stqe_ready_sent_q[i] & (~stqe_flushed_q[i])) | + (stq_i1_comp_val[i] & cp_i1_itag_cmp[i] & stqe_ready_sent_q[i] & (~stqe_flushed_q[i]))) | + (stqe_compl_rcvd_q[i] & (~stq7_entry_delete[i])); + + assign stqe_compl_rcvd_d[i] = (stq_push_down == 1'b0) ? stqe_compl_rcvd[i] : + stqe_compl_rcvd[i + 1]; + + assign stqe_flush_cmp[i] = |(cp_flush_q & stqe_thrd_id_q[i]); + + assign stqe_flushed[i] = stqe_alloc_q[i] & (~stqe_compl_rcvd[i]) & stqe_flush_cmp[i]; + + assign stqe_alloc_flushed[i] = (stqe_alloc_ptr_q[i] & stq_alloc_val[0] & stq_alloc_flushed[0]) | (stqe_alloc_ptr_r1[i] & stq_alloc_val[1] & stq_alloc_flushed[1]); + + assign stqe_flushed_d[i] = (stq_push_down == 1'b0) ? (stqe_flushed[i] | stqe_alloc_flushed[i] | stqe_flushed_q[i]) & (~stq7_entry_delete[i]) : + (stqe_flushed[i + 1] | stqe_alloc_flushed[i + 1] | stqe_flushed_q[i + 1]) & (~stq7_entry_delete[i + 1]); + + assign stqe_need_ext_ack_d[i] = (ex4_set_stq[i] == 1'b1) ? ctl_lsq_ex4_is_sync | ctl_lsq_ex4_is_icbi | ctl_lsq_ex4_is_icswxr | ctl_lsq_ex4_is_resv | + ctl_lsq_ex4_is_mfgpr | ctl_lsq_ex4_is_cinval | ctl_lsq_ex4_watch_clr_all : + stqe_need_ext_ack_q[i + 1]; + + assign stqe_blk_loads_d[i] = (ex4_set_stq[i] == 1'b1) ? ctl_lsq_ex4_is_sync | ctl_lsq_ex4_is_resv | ctl_lsq_ex4_is_cinval | ctl_lsq_ex4_watch_clr_all : + stqe_blk_loads_q[i + 1]; + + + assign stqe_all_thrd_chk_d[i] = (ex4_set_stq[i] == 1'b1) ? ctl_lsq_ex4_all_thrd_chk: stqe_all_thrd_chk_q[i + 1]; + + assign stqe_l_zero[i] = stqe_l_fld_q[i][0:1] == 2'b00; + + assign stqe_valid_sync[i] = stqe_is_sync_q[i] & stqe_alloc_q[i] & (~stqe_flushed_q[i]); + + assign stqe_ack_rcvd_d[i] = (stq_push_down == 1'b0) ? (((any_ack_val_ok_q == stqe_thrd_id_q[i]) & stqe_need_ext_ack_q[i] & stqe_have_cp_next_q[i] & + (~stqe_is_icbi_q[i])) | stqe_ack_rcvd_q[i]) : + (((any_ack_val_ok_q == stqe_thrd_id_q[i + 1]) & stqe_need_ext_ack_q[i + 1] & stqe_have_cp_next_q[i + 1] & + (~stqe_is_icbi_q[i + 1])) | stqe_ack_rcvd_q[i + 1]); + end + end + endgenerate + + // drop prefetches when a sync in valid in the stq + assign lsq_ctl_sync_in_stq = |(stqe_valid_sync) | |(ext_ack_queue_sync_q); + + // LQ Pipe checking for illegal lswx received by SQ + assign lsq_ctl_ex3_strg_val = |(ex3_data_val); + assign lsq_ctl_ex3_illeg_lswx = |(ex3_illeg_lswx); + assign lsq_ctl_ex3_strg_noop = |(ex3_strg_noop); + assign lsq_ctl_ex3_ct_val = |(ex3_data_val); + assign lsq_ctl_ex3_be_ct = ex3_ct_sel[0:5]; + assign lsq_ctl_ex3_le_ct = ex3_ct_sel[6:11]; + + //------------------------------------------------------------------------------ + // Multi-Thread Age Detection + //------------------------------------------------------------------------------ + // Multi-Thread Age Detection + // Following Table should explain the idea behind other `THREADS Age Determination + // Oldest Youngest Result + // 0 0 All Stores with addr_val in Store Queue are oldest + // 0 1 Stores are older from Youngest_Itag as upper bound, but not including Youngest_Itag, used in case Oldest_Itag is not in ODQ + // 1 0 Stores are older from Oldest_Itag as upper bound, including Oldest_Itag + // 1 1 Stores are older from Oldest_Itag as upper bound, including Oldest_Itag + // Need to validate the oldest entries + generate + begin : xhdl10 + genvar stq; + for (stq = 0; stq <= `STQ_ENTRIES - 1; stq = stq + 1) + begin : ageExpand + assign ex3_agecmp[stq] = |(ex3_nxt_oldest_q[stq:`STQ_ENTRIES - 1]) | ex3_pfetch_val; + end + end + endgenerate + + // Muxing TAG Pointer + + always @(*) + begin: sttagMux + reg [0:`STQ_ENTRIES-1] oldest; + reg [0:`STQ_ENTRIES-1] youngest; + integer stq; + oldest = 0; + youngest = 0; + for (stq = 0; stq <= `STQ_ENTRIES - 1; stq = stq + 1) + begin + oldest = (stq_tag_ptr_q[stq] & {`STQ_ENTRIES{odq_stq_ex2_nxt_oldest_stTag[stq]}}) | oldest; + youngest = (stq_tag_ptr_q[stq] & {`STQ_ENTRIES{odq_stq_ex2_nxt_youngest_stTag[stq]}}) | youngest; + end + ex2_nxt_oldest_ptr = oldest; + ex2_nxt_youngest_ptr = youngest; + end + + assign ex2_no_nxt_match = (~(odq_stq_ex2_nxt_oldest_val | odq_stq_ex2_nxt_youngest_val)); + assign ex2_no_nxt_oldest = (stqe_addr_val_q[0:`STQ_ENTRIES - 1] & (~stqe_flushed_q[0:`STQ_ENTRIES - 1])) & {`STQ_ENTRIES{ex2_no_nxt_match}}; + + // Need to shift youngest pointer since we care of everything below this entry + assign ex2_nxt_youngest_shft = {ex2_nxt_youngest_ptr[1:`STQ_ENTRIES - 1], 1'b0}; + + // Oldest Pointer is the OR of oldest_itag pointer with youngest_itag_shifted pointer and with no_oldest_youngest pointer + assign ex2_nxt_oldest = ex2_nxt_oldest_ptr | ex2_nxt_youngest_shft | ex2_no_nxt_oldest; + assign ex3_nxt_oldest_d = (stq_push_down == 1'b0) ? ex2_nxt_oldest : + ({ex2_nxt_oldest[1:`STQ_ENTRIES - 1], 1'b0}); + + //------------------------------------------------------------------------------ + // Data Forwarding + //------------------------------------------------------------------------------ + // For some sizes, we could rotate too far and not leave enough data + assign ex4_rot_mask = (ex4_req_opsize_q == 3'b001) ? 4'b0000 : // 1B None + (ex4_req_opsize_q == 3'b010) ? 4'b1111 : // 2B Any + (ex4_req_opsize_q == 3'b100) ? 4'b1110 : // 4B Sel3 will not leave 4B of data + (ex4_req_opsize_q == 3'b101) ? 4'b1000 : // 8B Exact Match Only + (ex4_req_opsize_q == 3'b110) ? 4'b1000 : // 16B Exact Match Only + 4'b0000; + + assign ex4_req_opsize_1hot[0] = ex4_req_opsize_q == 3'b110; // 16B + assign ex4_req_opsize_1hot[1] = ex4_req_opsize_q == 3'b101; // 8B + assign ex4_req_opsize_1hot[2] = ex4_req_opsize_q == 3'b100; // 4B + assign ex4_req_opsize_1hot[3] = ex4_req_opsize_q == 3'b010; // 2B + assign ex4_req_opsize_1hot[4] = ex4_req_opsize_q == 3'b001; // 1B + assign ex4_req_opsize1 = ~ex4_req_opsize_q[0] & ex4_req_opsize_q[2]; + + generate begin : xhdl12 + genvar i; + genvar b; + + for (i = 0; i <= `STQ_ENTRIES - 1; i = i + 1) begin : stq_fwd_gen + if ((58 - RI) == 36) begin : bitStack36 + // Address Compare for data forwarding + tri_addrcmp stq_fwd_addrcmp( + .enable_lsb(spr_xucr0_64cls), + .d0(stqe_addr_q[i][RI:57]), + .d1(ctl_lsq_ex4_p_addr[RI:57]), + .eq(ex4_fwd_addrcmp_hi[i])); + end + + if ((58 - RI) != 36) begin : nobitStack + assign ex4_fwd_addrcmp_hi[i] = (({stqe_addr_q[i][RI:56], (stqe_addr_q[i][57] & spr_xucr0_64cls)}) == ({ctl_lsq_ex4_p_addr[RI:56], (ctl_lsq_ex4_p_addr[57] & spr_xucr0_64cls)})); + end + + assign ex4_fwd_addrcmp_lo[i] = stqe_addr_q[i][58:59] == ex4_req_p_addr_l_q[58:59]; + assign ex4_fwd_addrcmp[i] = ex4_fwd_addrcmp_hi[i] & ex4_fwd_addrcmp_lo[i]; + + // Check that Thread ID matches + assign ex4_thrd_match[i] = |(ex4_req_thrd_id_q & stqe_thrd_id_q[i]) | stqe_all_thrd_chk_q[i]; + + // Check that they are from the same thread or from different thread that has received its commit report + assign ex4_thrd_id_ok[i] = ex4_thrd_match[i] | stqe_compl_rcvd_q[i]; + + // Check the address for inclusivity based on the opsize + assign ex4_byte_en_ok[i] = ~(|(ex4_req_byte_en_q & (~stqe_byte_en_q[i]))); + assign ex4_byte_en_miss[i] = ~(|(ex4_req_byte_en_q & stqe_byte_en_q[i])); + + // If they are byte misaligned, we can't rotate. + // For some sizes, we could rotate too far and not leave enough data + // 1Byte load can forward only from a 1Byte store to the same address + assign ex4_1byte_chk_ok[i] = ex4_hw_addr_cmp[i][3] & stqe_opsize1[i] & ex4_req_opsize1; //1Byte request only + assign ex4_byte_chk_ok[i] = |(ex4_hw_addr_cmp[i] & ex4_rot_mask) | //All Byte Combination greater than 1Byte requests + (ex4_1byte_chk_ok[i]); + + // need to mask off offsets that dont reflect the size of the store + assign stqe_rotcmp_val[i][0] = stqe_opsize_q[i][0] & stqe_opsize_q[i][2]; // 8B requests + assign stqe_rotcmp_val[i][1] = stqe_opsize_q[i][0] & stqe_opsize_q[i][2]; // 8B requests + assign stqe_rotcmp_val[i][2] = stqe_opsize_q[i][0]; // 8B/4B requests + assign stqe_rotcmp_val[i][3] = |(stqe_opsize_q[i]); // 8B/4B/2B/1B requests + assign stqe_opsize8[i] = stqe_opsize_q[i][0] & stqe_opsize_q[i][2]; + assign stqe_opsize4[i] = stqe_opsize_q[i][0] & ~stqe_opsize_q[i][2]; + assign stqe_opsize2[i] = ~stqe_opsize_q[i][0] & stqe_opsize_q[i][1]; + assign stqe_opsize1[i] = ~stqe_opsize_q[i][0] & stqe_opsize_q[i][2]; + + assign ex4_hw_addr_cmp[i][0] = (ex4_req_p_addr_l_q[60:63] == stqe_rotcmp_q[i][0:3]) & stqe_rotcmp_val[i][0]; + assign ex4_hw_addr_cmp[i][1] = (ex4_req_p_addr_l_q[60:63] == stqe_rotcmp_q[i][4:7]) & stqe_rotcmp_val[i][1]; + assign ex4_hw_addr_cmp[i][2] = (ex4_req_p_addr_l_q[60:63] == stqe_rotcmp_q[i][8:11]) & stqe_rotcmp_val[i][2]; + assign ex4_hw_addr_cmp[i][3] = (ex4_req_p_addr_l_q[60:63] == stqe_rotcmp_q[i][12:15]) & stqe_rotcmp_val[i][3]; + + assign ex4_opsize8_be[i] = ex4_req_opsize_1hot[1] & ~stqe_byte_swap_q[i]; + assign ex4_opsize4_be[i] = ex4_req_opsize_1hot[2] & ~stqe_byte_swap_q[i]; + assign ex4_opsize2_be[i] = ex4_req_opsize_1hot[3] & ~stqe_byte_swap_q[i]; + assign ex4_opsize1_be[i] = ex4_req_opsize_1hot[4] & ~stqe_byte_swap_q[i]; + assign ex4_opsize8_le[i] = ex4_req_opsize_1hot[1] & stqe_byte_swap_q[i]; + assign ex4_opsize4_le[i] = ex4_req_opsize_1hot[2] & stqe_byte_swap_q[i]; + assign ex4_opsize2_le[i] = ex4_req_opsize_1hot[3] & stqe_byte_swap_q[i]; + assign ex4_opsize1_le[i] = ex4_req_opsize_1hot[4] & stqe_byte_swap_q[i]; + + assign ex4_rot_sel_be[i][0] = (ex4_opsize8_be[i] & ex4_hw_addr_cmp[i][0]) | (ex4_opsize4_be[i] & ex4_hw_addr_cmp[i][2]) | + (ex4_opsize2_be[i] & ex4_hw_addr_cmp[i][3]) | (ex4_opsize1_be[i] & ex4_hw_addr_cmp[i][3]); + assign ex4_rot_sel_be[i][1] = (ex4_opsize4_be[i] & ex4_hw_addr_cmp[i][1]) | (ex4_opsize2_be[i] & ex4_hw_addr_cmp[i][2]); + assign ex4_rot_sel_be[i][2] = (ex4_opsize4_be[i] & ex4_hw_addr_cmp[i][0]) | (ex4_opsize2_be[i] & ex4_hw_addr_cmp[i][1]); + assign ex4_rot_sel_be[i][3] = (ex4_opsize2_be[i] & ex4_hw_addr_cmp[i][0]); + + assign ex4_rot_sel_le[i][0] = ((stqe_opsize8[i] & (ex4_opsize8_le[i] | ex4_opsize4_le[i] | ex4_opsize2_le[i])) & ex4_hw_addr_cmp[i][0]) | + ((stqe_opsize4[i] & (ex4_opsize4_le[i] | ex4_opsize2_le[i])) & ex4_hw_addr_cmp[i][2]) | + (stqe_opsize2[i] & ex4_opsize2_le[i] & ex4_hw_addr_cmp[i][3]) | + (stqe_opsize1[i] & ex4_opsize1_le[i] & ex4_hw_addr_cmp[i][3]); + assign ex4_rot_sel_le[i][1] = ((stqe_opsize8[i] & (ex4_opsize4_le[i] | ex4_opsize2_le[i])) & ex4_hw_addr_cmp[i][1]) | + ((stqe_opsize4[i] & (ex4_opsize2_le[i])) & ex4_hw_addr_cmp[i][3]); + assign ex4_rot_sel_le[i][2] = ((stqe_opsize8[i] & (ex4_opsize4_le[i] | ex4_opsize2_le[i])) & ex4_hw_addr_cmp[i][2]); + assign ex4_rot_sel_le[i][3] = ((stqe_opsize8[i] & (ex4_opsize2_le[i])) & ex4_hw_addr_cmp[i][3]); + + assign ex4_rot_sel[i] = ex4_rot_sel_le[i] | ex4_rot_sel_be[i]; + + // Little Endian Sign Extension Byte Select + // StoreSize8 | HW_CMP | SEXT_SEL + //-------------------------------------- + // LoadSize4 | 1000 | 0010 + // LoadSize2 | 1000 | 0001 + // LoadSize4 | 0100 | 0100 + // LoadSize2 | 0100 | 0010 + // LoadSize4 | 0010 | 1000 + // LoadSize2 | 0010 | 0100 + // LoadSize2 | 0001 | 1000 + //-------------------------------------- + // StoreSize4 | HW_CMP | SEXT_SEL + //-------------------------------------- + // LoadSize4 | 0010 | 0010 + // LoadSize2 | 0010 | 0001 + // LoadSize2 | 0001 | 0001 + //-------------------------------------- + // StoreSize2 | HW_CMP | SEXT_SEL + //-------------------------------------- + // LoadSize2 | 0001 | 0001 + + assign ex4_rev_rot_sel[i] = {ex4_hw_addr_cmp[i][3], ex4_hw_addr_cmp[i][2], ex4_hw_addr_cmp[i][1], ex4_hw_addr_cmp[i][0]}; + assign ex4_shft_rot_sel[i] = {ex4_rev_rot_sel[i][1:3], 1'b0}; + assign ex4_sext8_le_sel[i] = (ex4_rev_rot_sel[i] & {4{(ex4_opsize2_le[i] & stqe_opsize8[i])}}) | + (ex4_shft_rot_sel[i] & {4{(ex4_opsize4_le[i] & stqe_opsize8[i])}}); + assign ex4_sext4_le_sel[i][0:1] = 2'b00; + assign ex4_sext4_le_sel[i][2] = stqe_opsize4[i] & (ex4_opsize4_le[i] | (ex4_opsize2_le[i] & ex4_hw_addr_cmp[i][3])); + assign ex4_sext4_le_sel[i][3] = stqe_opsize4[i] & ex4_opsize2_le[i] & ex4_hw_addr_cmp[i][2]; + assign ex4_sext2_le_sel[i][0:2] = 3'b000; + assign ex4_sext2_le_sel[i][3] = stqe_opsize2[i]; + assign ex4_sext_le_sel[i] = ex4_sext8_le_sel[i] | ex4_sext4_le_sel[i] | ex4_sext2_le_sel[i]; + assign ex4_sext_sel[i] = ex4_sext_le_sel[i] | (ex4_hw_addr_cmp[i] & {4{(~stqe_byte_swap_q[i])}}); + + assign ex4_sext[i] = (ex4_sext_sel[i][0:3] == 4'b1000) ? stqe_data1_q[i][64] : + (ex4_sext_sel[i][0:3] == 4'b0100) ? stqe_data1_q[i][80] : + (ex4_sext_sel[i][0:3] == 4'b0010) ? stqe_data1_q[i][96] : + (ex4_sext_sel[i][0:3] == 4'b0001) ? stqe_data1_q[i][112] : + 1'b0; + assign ex4_se[i] = ex4_req_algebraic_q & ex4_sext[i]; + assign ex4_se_b[i][0:7] = {8{(~ex4_se[i])}}; + + for (b = 0; b <= 7; b = b + 1) begin : rotate_gen + assign stqe_data1_swzl[i][b * 8:(b * 8) + 7] = {stqe_data1_q[i][b + 64], stqe_data1_q[i][b + 72], stqe_data1_q[i][b + 80], + stqe_data1_q[i][b + 88], stqe_data1_q[i][b + 96], stqe_data1_q[i][b + 104], + stqe_data1_q[i][b + 112], stqe_data1_q[i][b + 120]}; + + assign ex4_fwd_data1[i][b * 8:(b * 8) + 7] = {ex4_fwd_data1_swzl[i][b + 0], ex4_fwd_data1_swzl[i][b + 8], ex4_fwd_data1_swzl[i][b + 16], + ex4_fwd_data1_swzl[i][b + 24], ex4_fwd_data1_swzl[i][b + 32], ex4_fwd_data1_swzl[i][b + 40], + ex4_fwd_data1_swzl[i][b + 48], ex4_fwd_data1_swzl[i][b + 56]}; + + + lq_stq_rot rotate( + .rot_sel(ex4_rot_sel[i]), + .mask(ex4_req_opsize_1hot[1:4]), + .se_b(ex4_se_b[i][b]), + .rot_data(stqe_data1_swzl[i][b * 8:(b * 8) + 7]), + .data_rot(ex4_fwd_data1_swzl[i][b * 8:(b * 8) + 7]) + ); + end + + // OrderQ will indicate which entries are older + // itag age Compare for data forwarding + // stq_fwd_agecmp : entity tri.tri_agecmp + // generic map(size => `ITAG_SIZE_ENC) + // port map ( + // a => ex3_req_itag_q, -- Incoming Load + // b => stqe_itag_q(i), -- Store Entry + // a_newer_b => ex3_agecmp_itag(i) -- Load newer than Store? + // ); + + // If COMMIT report has been recieved, entry is always the oldest automatically + assign ex3_fwd_agecmp[i] = ex3_agecmp[i]; + + assign ex4_fwd_agecmp_d[i] = (stq_push_down == 1'b0) ? ex3_agecmp[i] : + ex3_agecmp[i + 1]; + + assign stqe_guarded[i] = stqe_wimge_q[i][3]; + + assign ex4_fwd_endian_mux[i] = (~(ctl_lsq_ex4_byte_swap ^ stqe_byte_swap_q[i])); + assign ex4_fwd_is_store_mux[i] = stqe_is_store_q[i] & (~(stqe_cline_chk_q[i] | ctl_lsq_ex4_cline_chk)); + assign ex4_fwd_is_cline_chk[i] = stqe_fwd_addr_val_q[i] & ex4_fwd_addrcmp_hi[i] & (stqe_cline_chk_q[i] | ctl_lsq_ex4_cline_chk); + assign ex4_fwd_is_miss_chk[i] = stqe_fwd_addr_val_q[i] & ex4_fwd_addrcmp_hi[i]; + assign ex4_fwd_is_larx_chk[i] = stqe_fwd_addr_val_q[i] & ex4_thrd_match[i] & ctl_lsq_ex4_is_resv; + assign ex4_fwd_is_blk_load_chk[i] = stqe_fwd_addr_val_q[i] & ex4_thrd_match[i] & stqe_blk_loads_q[i]; + assign ex4_fwd_is_gload_chk[i] = stqe_fwd_addr_val_q[i] & ex4_thrd_match[i] & stqe_guarded[i] & ctl_lsq_ex4_wimge[3]; + assign ex4_fwd_rej_guarded[i] = ctl_lsq_ex4_wimge[3]; + + assign stqe_rej_newer_gload[i] = stqe_fwd_addr_val_q[i] & ex4_fwd_agecmp_q[i] & ex4_ldreq_valid & ex4_fwd_is_gload_chk[i]; + assign stqe_rej_other[i] = stqe_fwd_addr_val_q[i] & ex4_fwd_agecmp_q[i] & ex4_ldreq_valid & ex4_fwd_is_blk_load_chk[i]; + assign stqe_rej_cline_chk[i] = stqe_fwd_addr_val_q[i] & ex4_fwd_agecmp_q[i] & ex4_ldreq_valid & ex4_fwd_is_cline_chk[i]; + assign stqe_rej_cline_miss[i] = stqe_fwd_addr_val_q[i] & ex4_fwd_agecmp_q[i] & ex4_ldreq_valid & ex4_fwd_is_miss_chk[i]; + assign stqe_rej_wchkall[i] = stqe_fwd_addr_val_q[i] & ex4_fwd_agecmp_q[i] & ex4_wchkall_valid; + + assign stqe_rej_hit_no_fwd[i] = ex4_fwd_sel[i] & ex4_fwd_restart_entry[i] & ex4_ldreq_valid; + + if (i > `STQ_FWD_ENTRIES - 1) begin : hold_nonfwd + assign set_hold_early_clear[i] = ex4_nofwd_entry[i] & ex4_ldreq_valid; + end + if (i < `STQ_FWD_ENTRIES) begin : hold_nodata + assign set_hold_early_clear[i] = ex4_fwd_sel[i] & (~stqe_data_val_q[i]) & ex4_ldreq_valid; + end + end + end + endgenerate + + // Entry Address compared down to the 16 Byte boundary + assign ex4_fwd_sel = ex4_fwd_addrcmp & ex4_fwd_agecmp_q & stqe_fwd_addr_val_q[0:`STQ_ENTRIES - 1] & (~ex4_byte_en_miss); + + // itag age Compare for data forwarding + tri_agecmp #(.SIZE(`ITAG_SIZE_ENC)) nxt_stq_fwd_agecmp( + .a(ex3_req_itag_q), // Incoming Load + .b(ex4_req_itag_q), // being written into next Store Entry + .a_newer_b(ex3_ex4_agecmp)); // Load newer than Store? + + assign ex3_ex4_agecmp_sametid = ex3_ex4_agecmp & |(ex3_req_thrd_id_q & ex4_req_thrd_id_q); + assign ex3_ex4_byte_en_hit = |(ctl_lsq_ex3_byte_en & ex4_req_byte_en_q); + + // compare the forwardable entries to each other to determine the forwarding priority mask + generate begin : fwd_pri_gen_l1 + genvar i; + for (i = 0; i <= `STQ_FWD_ENTRIES - 1; i = i + 1) begin : fwd_pri_gen_l1 + always @(*) begin: fwd_pri_gen_l2 + reg [(i+1):`STQ_FWD_ENTRIES] match; + reg [(i+1):`STQ_FWD_ENTRIES] match_addr; + reg [(i+1):`STQ_FWD_ENTRIES] match_incom_addr; + reg [(i+1):`STQ_FWD_ENTRIES] match_stqe_addr; + reg [(i+1):`STQ_FWD_ENTRIES] match_chk_val; + reg [(i+1):`STQ_FWD_ENTRIES] stqe_byte_en_hit; + reg [(i+1):`STQ_FWD_ENTRIES] ex4_set_byte_en_hit; + integer j; + match = 0; + match_addr = 0; + match_incom_addr = 0; + match_stqe_addr = 0; + match_chk_val = 0; + stqe_byte_en_hit = 0; + ex4_set_byte_en_hit = 0; + for (j = i + 1; j <= `STQ_FWD_ENTRIES; j = j + 1) begin + stqe_byte_en_hit[j] = stqe_fwd_addr_val_q[j] & |(ctl_lsq_ex3_byte_en & stqe_byte_en_q[j]); + ex4_set_byte_en_hit[j] = ex4_set_stq_q[j] & ex3_ex4_byte_en_hit; + match_incom_addr[j] = ex4_fwd_addrcmp[i] & ex4_set_stq_q[j]; // incoming address matched against my entry i + match_stqe_addr[j] = (({stqe_addr_q[i][RI:56], (stqe_addr_q[i][57] & spr_xucr0_64cls)}) == + ({stqe_addr_q[j][RI:56], (stqe_addr_q[j][57] & spr_xucr0_64cls)})) & (stqe_addr_q[i][58:59] == stqe_addr_q[j][58:59]); + match_addr[j] = match_incom_addr[j] | match_stqe_addr[j]; + match_chk_val[j] = (stqe_fwd_addr_val_q[i] | ex4_set_stq_q[i]) & (stqe_byte_en_hit[j] | ex4_set_byte_en_hit[j]) & ex3_fwd_agecmp[j]; + match[j] = (match_addr[j] | ex4_fwd_addrcmp[j]) & match_chk_val[j]; + end + stq_mask[i] = |(match); + + // dont think the ODQ age needs to be taken into account, since the store is in ex4, if it were from the other thread, + // the store wont be in a commit state and the load request should be restarted + ex4_stqe_match_addr[i] = ex4_fwd_addrcmp[i] & stqe_fwd_addr_val_q[i] & |(ex4_set_stq_q); + ex4_stqe_match[i] = (ex4_stqe_match_addr[i] & ex3_ex4_byte_en_hit & ex3_fwd_agecmp[i]); + fwd_pri_mask[i] = stq_mask[i]; + end + end + end endgenerate + + assign stq_fwd_pri_mask_d = (stq_push_down == 1'b0) ? fwd_pri_mask[0:`STQ_FWD_ENTRIES - 2] : + fwd_pri_mask[1:`STQ_FWD_ENTRIES - 1]; + + // Entries non-address checks passed + assign stqe_fwd_enable = {`STQ_ENTRIES{~spr_lsucr0_dfwd_q}}; + assign ex4_fwd_entry = ex4_byte_en_ok & ex4_byte_chk_ok & ex4_thrd_id_ok & stqe_data_val_q[0:`STQ_ENTRIES - 1] & ex4_fwd_endian_mux & ex4_fwd_is_store_mux & ~ex4_fwd_rej_guarded & stqe_fwd_enable; + assign ex4_fwd_val = |(ex4_fwd_sel[0:`STQ_FWD_ENTRIES - 1] & ex4_fwd_entry[0:`STQ_FWD_ENTRIES - 1]); + + // Check that we wanted to forward from the Forwadable Entries + // but couldnt due to forward checks + assign ex4_fwd_chk_fail = ex4_fwd_sel[0:`STQ_FWD_ENTRIES - 1] & (~ex4_fwd_entry[0:`STQ_FWD_ENTRIES - 1]); + + // Check that we wanted to forward from the Non-Forwadable Entries, need to restart if + // we hit against those + assign ex4_nofwd_entry = ex4_fwd_sel[`STQ_FWD_ENTRIES:`STQ_ENTRIES - 1]; + + // Restart scenarios + assign ex4_fwd_restart_entry = {ex4_fwd_chk_fail, ex4_nofwd_entry}; + assign ex4_fwd_restart = |(ex4_fwd_restart_entry); + + assign ex4_fwd_hit = |(ex4_fwd_sel); + + // ENDIAN, EX$_GUARDED, and NON-STORE rejects are included in the fwd_entry logic now + + // These special rejects occur regardless of address collision + assign ex4_rej_newer_gload = |(stqe_fwd_addr_val_q[0:`STQ_ENTRIES - 1] & ex4_fwd_agecmp_q & ex4_fwd_is_gload_chk); // Store Op is guarded + assign ex4_rej_other = |(stqe_fwd_addr_val_q[0:`STQ_ENTRIES - 1] & ex4_fwd_agecmp_q & ex4_fwd_is_blk_load_chk); // Store Op is a STCX, DCI, ICI, SYNC, MBAR, WCLR ALL + assign ex4_rej_cline_chk = |(stqe_fwd_addr_val_q[0:`STQ_ENTRIES - 1] & ex4_fwd_agecmp_q & ex4_fwd_is_cline_chk); // Store Op affects entire cacheline + assign ex4_rej_cline_miss = |(stqe_fwd_addr_val_q[0:`STQ_ENTRIES - 1] & ex4_fwd_agecmp_q & ex4_fwd_is_miss_chk); // Store Op should reject a loadmiss + + // Determine Restart based on thread + assign ex4_thrd_match_restart = |(((ex4_fwd_agecmp_q & (ex4_fwd_is_cline_chk | ex4_fwd_is_miss_chk | ex4_fwd_is_gload_chk | ex4_fwd_is_blk_load_chk)) | + ex4_fwd_restart_entry) & ex4_thrd_match) | ex4_rej_sync_pending; + assign ex4_thrd_nomatch_restart = |(((ex4_fwd_agecmp_q & (ex4_fwd_is_cline_chk | ex4_fwd_is_miss_chk)) | ex4_fwd_restart_entry) & ~ex4_thrd_match); + assign ex5_thrd_match_restart_d = ex4_thrd_match_restart; + assign ex6_thrd_match_restart_d = ex5_thrd_match_restart_q; + assign ex5_thrd_nomatch_restart_d = ex4_thrd_nomatch_restart; + assign ex6_thrd_nomatch_restart_d = ex5_thrd_nomatch_restart_q; + + // LARX/GuardedLoad check is added for the case where a larx/guardedload went out for a thread, it got an ECC error, + // reported completion without a flush, a store can commit to the L1/L2 before the resend + // of the LARX/GuardedLoad completes + assign ex4_older_ldmiss = (ex4_fwd_is_miss_chk | ex4_fwd_is_larx_chk | ex4_fwd_is_blk_load_chk | ex4_fwd_is_gload_chk) & (~ex4_fwd_agecmp_q); + assign ex5_older_ldmiss_d = (stq_push_down == 1'b0) ? ex4_older_ldmiss : + {ex4_older_ldmiss[1:`STQ_ENTRIES - 1], 1'b0}; + + assign ex4_rej_wchkall = |(stqe_fwd_addr_val_q[0:`STQ_ENTRIES - 1] & ex4_fwd_agecmp_q); // WCHKALL colliding with older instructions in store queue, + // need to guarantee all watch effects have completed + assign ex4_rej_sync_pending = |(ex4_req_thrd_id_q & (ext_ack_queue_sync_q | ext_ack_queue_stcx_q)); + + assign ex5_stq_restart_d = ((ex4_ldreq_valid | ex4_pfetch_val_q) & (ex4_fwd_restart | ex4_rej_newer_gload | + ex4_rej_other | ex4_rej_cline_chk | ex4_rej_sync_pending)) | + (ex4_wchkall_valid & ex4_rej_wchkall); + assign ex5_stq_restart_miss_d = (ex4_ldreq_valid | ex4_pfetch_val_q) & ex4_rej_cline_miss & (~ex4_fwd_val); // cacheline compared and I am not forwarding + assign ex5_fwd_val_d = ex4_ldreq_valid & ex4_fwd_val; + + assign ex4_qHit_set_oth = (stqe_rej_newer_gload | stqe_rej_other | stqe_rej_cline_chk | stqe_rej_wchkall | stqe_rej_hit_no_fwd) & (~stqe_cmmt_entry); + assign ex4_qHit_set_miss = stqe_rej_cline_miss & (~stqe_cmmt_entry); + + assign ex5_qHit_set_oth_d = (stq_push_down == 1'b0) ? ex4_qHit_set_oth : + {ex4_qHit_set_oth[1:`STQ_ENTRIES - 1], 1'b0}; + + assign ex5_qHit_set_miss_d = (stq_push_down == 1'b0) ? ex4_qHit_set_miss : + {ex4_qHit_set_miss[1:`STQ_ENTRIES - 1], 1'b0}; + + assign ex5_qHit_set_miss[0:`STQ_ENTRIES - 1] = ex5_qHit_set_miss_q & {`STQ_ENTRIES{(~(ctl_lsq_ex5_load_hit | ex5_fwd_val_q))}}; + + assign lsq_ctl_ex5_stq_restart = ex5_stq_restart_q; + assign lsq_ctl_ex5_stq_restart_miss = ex5_stq_restart_miss_q; + assign lsq_ctl_ex5_fwd_val = ex5_fwd_val_q; + assign lsq_ctl_ex5_fwd_data = ex5_fwd_data_q; + assign lsq_ctl_ex6_stq_events = {ex6_thrd_match_restart_q, ex6_thrd_nomatch_restart_q}; + + //------------------------------------------------------------------------------ + //------------------------------------------------------------------------------ + // FXU0 SPR Mux Select + //------------------------------------------------------------------------------ + //------------------------------------------------------------------------------ + // Thread Select + //fxu0StTid : process (ex4_fxu0_val_q, ctl_lsq_spr_dbcr2_dvc1m, ctl_lsq_spr_dbcr2_dvc1be, + // ctl_lsq_spr_dbcr2_dvc2m, ctl_lsq_spr_dbcr2_dvc2be) + // variable dvc1m :std_ulogic_vector(0 to 1); + // variable dvc2m :std_ulogic_vector(0 to 1); + // variable dvc1be :std_ulogic_vector(8-(2**`GPR_WIDTH_ENC)/8 to 7); + // variable dvc2be :std_ulogic_vector(8-(2**`GPR_WIDTH_ENC)/8 to 7); + //begin + // dvc1m := (others=>'0'); + // dvc2m := (others=>'0'); + // dvc1be := (others=>'0'); + // dvc2be := (others=>'0'); + // for tid in 0 to `THREADS-1 loop + // dvc1m := gate(ctl_lsq_spr_dbcr2_dvc1m(2*tid to 2*tid+1), ex4_fxu0_val_q(tid)) or dvc1m; + // dvc2m := gate(ctl_lsq_spr_dbcr2_dvc2m(2*tid to 2*tid+1), ex4_fxu0_val_q(tid)) or dvc2m; + // dvc1be := gate(ctl_lsq_spr_dbcr2_dvc1be(tid*8+(8-fxu0_spr_dbcr2_dvc1be'length) to tid*8+7), ex4_fxu0_val_q(tid)) or dvc1be; + // dvc2be := gate(ctl_lsq_spr_dbcr2_dvc2be(tid*8+(8-fxu0_spr_dbcr2_dvc2be'length) to tid*8+7), ex4_fxu0_val_q(tid)) or dvc2be; + // end loop; + // fxu0_spr_dbcr2_dvc1m <= dvc1m; + // fxu0_spr_dbcr2_dvc2m <= dvc2m; + // fxu0_spr_dbcr2_dvc1be <= dvc1be; + // fxu0_spr_dbcr2_dvc2be <= dvc2be; + //end process fxu0StTid; + + //------------------------------------------------------------------------------ + //------------------------------------------------------------------------------ + // FXU1 SPR Mux Select + //------------------------------------------------------------------------------ + //------------------------------------------------------------------------------ + // Thread Select + + always @(*) + begin: fxu1StTid + reg [0:1] dvc1m; + reg [0:1] dvc2m; + reg [8-(2**`GPR_WIDTH_ENC)/8:7] dvc1be; + reg [8-(2**`GPR_WIDTH_ENC)/8:7] dvc2be; + integer tid; + dvc1m = 0; + dvc2m = 0; + dvc1be = 0; + dvc2be = 0; + for (tid = 0; tid <= `THREADS - 1; tid = tid + 1) + begin + dvc1m = (ctl_lsq_spr_dbcr2_dvc1m_int[tid] & {2{ex3_fxu1_val_q[tid]}}) | dvc1m; + dvc2m = (ctl_lsq_spr_dbcr2_dvc2m_int[tid] & {2{ex3_fxu1_val_q[tid]}}) | dvc2m; + dvc1be = (ctl_lsq_spr_dbcr2_dvc1be_int[tid][8-(2**`GPR_WIDTH_ENC)/8:7] & {((2**`GPR_WIDTH_ENC)/8){ex3_fxu1_val_q[tid]}}) | dvc1be; + dvc2be = (ctl_lsq_spr_dbcr2_dvc2be_int[tid][8-(2**`GPR_WIDTH_ENC)/8:7] & {((2**`GPR_WIDTH_ENC)/8){ex3_fxu1_val_q[tid]}}) | dvc2be; + end + fxu1_spr_dbcr2_dvc1m = dvc1m; + fxu1_spr_dbcr2_dvc2m = dvc2m; + fxu1_spr_dbcr2_dvc1be = dvc1be; + fxu1_spr_dbcr2_dvc2be = dvc2be; + end + + lq_spr_dvccmp #(.REGSIZE((2 ** `GPR_WIDTH_ENC))) fxu1DVC1St( + .en(tiup), + .en00(tidn), + .cmp(ex3_fxu1_dvc1_cmp_q), + .dvcm(fxu1_spr_dbcr2_dvc1m), + .dvcbe(fxu1_spr_dbcr2_dvc1be), + .dvc_cmpr(ex3_fxu1_dvc1r_cmpr) + ); + + + lq_spr_dvccmp #(.REGSIZE((2 ** `GPR_WIDTH_ENC))) fxu1DVC2St( + .en(tiup), + .en00(tidn), + .cmp(ex3_fxu1_dvc2_cmp_q), + .dvcm(fxu1_spr_dbcr2_dvc2m), + .dvcbe(fxu1_spr_dbcr2_dvc2be), + .dvc_cmpr(ex3_fxu1_dvc2r_cmpr) + ); + assign ex3_fxu1_dvcr_cmpr = {ex3_fxu1_dvc1r_cmpr, ex3_fxu1_dvc2r_cmpr}; + assign dbg_int_en_d = ctl_lsq_dbg_int_en; + + //------------------------------------------------------------------------------ + //------------------------------------------------------------------------------ + // ICSWX Coprocessor CT Mux Select + //------------------------------------------------------------------------------ + //------------------------------------------------------------------------------ + // ITAG Select + + always @(*) + begin: icswxCt + reg [0:11] ctSel; + integer stq; + ctSel = 0; + for (stq = 0; stq <= `STQ_ENTRIES - 1; stq = stq + 1) + ctSel = (stqe_icswx_ct_sel[stq] & {12{ex3_data_val[stq]}}) | ctSel; + + ex3_ct_sel = ctSel; + end + + //------------------------------------------------------------------------------ + //------------------------------------------------------------------------------ + // STQ Data Entries + //------------------------------------------------------------------------------ + //------------------------------------------------------------------------------ + // FXU0 Data interfaces + assign ex4_fxu1_illeg_lswx_d = xu1_lq_ex3_illeg_lswx; + assign ex4_fxu1_strg_noop_d = xu1_lq_ex3_strg_noop; + + // FXU1 Data interfaces + assign ex2_fxu1_val = |(xu1_lq_ex2_stq_val); + assign ex3_fxu1_val_d = xu1_lq_ex2_stq_val & (~cp_flush_q); + assign ex3_fxu1_itag_d = xu1_lq_ex2_stq_itag; + assign ex3_fxu1_val = |(ex3_fxu1_val_q); + assign ex3_fxu1_dvc1_cmp_d = xu1_lq_ex2_stq_dvc1_cmp; + assign ex3_fxu1_dvc2_cmp_d = xu1_lq_ex2_stq_dvc2_cmp; + assign ex4_fxu1_val_d = ex3_fxu1_val_q & (~cp_flush_q); + + // AXU Data interfaces + assign ex2_axu_val = |(xu_lq_axu_ex_stq_val); + assign ex3_axu_val_d = xu_lq_axu_ex_stq_val & (~cp_flush_q); + assign ex3_axu_itag_d = xu_lq_axu_ex_stq_itag; + assign ex3_axu_val = |(ex3_axu_val_q); + assign ex4_axu_val_d = ex3_axu_val_q & (~cp_flush_q); + + generate + begin : xhdl14 + genvar i; + for (i = 0; i <= `STQ_ENTRIES - 1; i = i + 1) + begin : stq_data_entry_gen + assign ex3_fxu1_data_ptr[i] = (stqe_alloc_q[i] & (ex3_fxu1_itag_q == stqe_itag_q[i]) & |(ex3_fxu1_val_q & stqe_thrd_id_q[i]) & (~stqe_compl_rcvd_q[i]) & (~stq_push_down)) | + (stqe_alloc_q[i + 1] & (ex3_fxu1_itag_q == stqe_itag_q[i + 1]) & |(ex3_fxu1_val_q & stqe_thrd_id_q[i + 1]) & (~stqe_compl_rcvd_q[i + 1]) & stq_push_down); + assign ex4_fxu1_data_ptr_d[i] = ex3_fxu1_data_ptr[i]; + assign ex4_axu_data_ptr_d[i] = (stqe_alloc_q[i] & (ex3_axu_itag_q == stqe_itag_q[i]) & (ex3_axu_val_q == stqe_thrd_id_q[i]) & (~stqe_compl_rcvd_q[i]) & (~stq_push_down)) | + (stqe_alloc_q[i + 1] & (ex3_axu_itag_q == stqe_itag_q[i + 1]) & (ex3_axu_val_q == stqe_thrd_id_q[i + 1]) & (~stqe_compl_rcvd_q[i + 1]) & stq_push_down); + + assign ex3_stq_data_val[i] = (stqe_alloc_q[i] & (ex3_fxu1_itag_q == stqe_itag_q[i]) & ((ex3_fxu1_val_q & (~cp_flush_q)) == stqe_thrd_id_q[i])) | + (stqe_alloc_q[i] & (ex3_axu_itag_q == stqe_itag_q[i]) & ((ex3_axu_val_q & (~cp_flush_q)) == stqe_thrd_id_q[i])); + + assign stqe_data_val[i] = stqe_fxu1_data_val[i] | stqe_axu_data_val[i]; + assign stqe_data_act[i] = stqe_data_val[i] | stq_push_down; + + assign stqe_fxu1_dvcr_val[i] = stqe_alloc_q[i] & (ex3_fxu1_itag_q == stqe_itag_q[i]) & |(ex3_fxu1_val_q & stqe_thrd_id_q[i]) & ~stqe_compl_rcvd_q[i]; + assign stqe_fxu1_data_val[i] = ex4_fxu1_data_ptr_q[i] & stqe_alloc_q[i] & |(ex4_fxu1_val_q & (~cp_flush_q)); + assign stqe_axu_data_val[i] = ex4_axu_data_ptr_q[i] & stqe_alloc_q[i] & |(ex4_axu_val_q & (~cp_flush_q)); + + assign stqe_fxu1_data_sel[i] = ex4_fxu1_data_ptr_q[i] & |(ex4_fxu1_val_q); + assign stqe_axu_data_sel[i] = ex4_axu_data_ptr_q[i] & |(ex4_axu_val_q); + + assign stqe_data_nxt_d[i] = ((ex3_stq_data_val[i] | stqe_data_nxt_q[i]) & (~(stq7_entry_delete[i] | stqe_flushed_q[i])) & (~stq_push_down)) | + ((ex3_stq_data_val[i + 1] | stqe_data_nxt_q[i + 1]) & (~(stq7_entry_delete[i + 1] | stqe_flushed_q[i + 1])) & stq_push_down); + assign stqe_data_val_d[i] = ((stqe_data_val[i] | stqe_data_val_q[i]) & (~(stq7_entry_delete[i] | stqe_flushed_q[i])) & (~stq_push_down)) | + ((stqe_data_val[i + 1] | stqe_data_val_q[i + 1]) & (~(stq7_entry_delete[i + 1] | stqe_flushed_q[i + 1])) & stq_push_down); + assign stqe_illeg_lswx_d[i] = (((stqe_data_val[i] & ex4_fxu1_illeg_lswx_q) | stqe_illeg_lswx_q[i]) & (~(stq7_entry_delete[i] | stqe_flushed_q[i])) & (~stq_push_down)) | + (((stqe_data_val[i + 1] & ex4_fxu1_illeg_lswx_q) | stqe_illeg_lswx_q[i + 1]) & (~(stq7_entry_delete[i + 1] | stqe_flushed_q[i + 1])) & stq_push_down); + assign stqe_strg_noop_d[i] = (((stqe_data_val[i] & ex4_fxu1_strg_noop_q) | stqe_strg_noop_q[i]) & (~(stq7_entry_delete[i] | stqe_flushed_q[i])) & (~stq_push_down)) | + (((stqe_data_val[i + 1] & ex4_fxu1_strg_noop_q) | stqe_strg_noop_q[i + 1]) & (~(stq7_entry_delete[i + 1] | stqe_flushed_q[i + 1])) & stq_push_down); + + // Data Value Compare Control + assign stqe_dvcr_cmpr_d[i] = (((ex3_fxu1_dvcr_cmpr & {2{stqe_fxu1_dvcr_val[i] }}) | stqe_dvcr_cmpr_q[i]) & {2{~stq_push_down}}) | + (((ex3_fxu1_dvcr_cmpr & {2{stqe_fxu1_dvcr_val[i+1]}}) | stqe_dvcr_cmpr_q[i+1]) & {2{ stq_push_down}}); + + assign stqe_dacrw_det0[i] = stqe_dacrw_q[i][0] | (stqe_dvcr_cmpr_q[i][0] & stqe_dvc_en_q[i][0]); + assign stqe_dacrw_det1[i] = stqe_dacrw_q[i][1] | (stqe_dvcr_cmpr_q[i][1] & stqe_dvc_en_q[i][1]); + assign stqe_dacrw_det2[i] = stqe_dacrw_q[i][2]; + assign stqe_dacrw_det3[i] = stqe_dacrw_q[i][3]; + + // Debug Interrupt Detected + assign stqe_dvc_int_det[i] = (stqe_dacrw_det0[i] | stqe_dacrw_det1[i] | stqe_dacrw_det2[i] | stqe_dacrw_det3[i]) & |(stqe_thrd_id_q[i] & dbg_int_en_q); + + // Logic for SET_HOLD and CLR_HOLD to the Reservation station + // Request was restarted due to hitting against store queue entry + assign stq2_cmmt_entry[i] = stqe_qHit_held_clr[i]; + assign stq3_cmmt_entry[i] = stq3_cmmt_ptr_q[i] & stq3_cmmt_val_q; + assign stq4_cmmt_entry[i] = stq4_cmmt_ptr_q[i] & stq4_cmmt_val_q; + assign stq5_cmmt_entry[i] = stq5_cmmt_ptr_q[i] & stq5_cmmt_val_q; + assign stq6_cmmt_entry[i] = stq6_cmmt_ptr_q[i] & stq6_cmmt_val_q; + assign stq7_cmmt_entry[i] = stq7_cmmt_ptr_q[i] & stq7_cmmt_val_q; + assign stqe_cmmt_entry[i] = stq2_cmmt_entry[i] | stq3_cmmt_entry[i] | stq4_cmmt_entry[i] | stq5_cmmt_entry[i] | stq6_cmmt_entry[i] | stq7_cmmt_entry[i]; + assign stqe_qHit_held_set[i] = (ex5_qHit_set_oth_q[i] | ex5_qHit_set_miss[i]) & (~(|(ex5_qHit_set_oth_q[i + 1:`STQ_ENTRIES] | ex5_qHit_set_miss[i + 1:`STQ_ENTRIES]))); // only set for highest stq entry + + if (i < `STQ_FWD_ENTRIES) + begin : clr_fwd_entries + assign stqe_qHit_held_clr[i] = (stq2_cmmt_ptr_remove[i] & stq2_cmmt_val) | + (stq2_cmmt_ptr_q[i] & stq2_cmmt_flushed_q) | + (stqe_need_ext_ack_q[i] & (any_ack_val_ok_q == stqe_thrd_id_q[i])) | + (stqe_held_early_clr_q[i] & (stqe_data_nxt_q[i] | stqe_data_val_q[i])); + end + + if (i == `STQ_FWD_ENTRIES) + begin : clr_next_fwd_entry + assign stqe_qHit_held_clr[i] = (stq2_cmmt_ptr_remove[i] & stq2_cmmt_val) | + (stq2_cmmt_ptr_q[i] & stq2_cmmt_flushed_q) | + (stqe_need_ext_ack_q[i] & (any_ack_val_ok_q == stqe_thrd_id_q[i])) | + (stqe_held_early_clr_q[i] & stqe_data_val_q[i] & stq2_cmmt_val & stq2_cmmt_ptr_remove[i-`STQ_FWD_ENTRIES]); + end + + if (i > `STQ_FWD_ENTRIES) + begin : clr_nonfwd_entries + assign stqe_qHit_held_clr[i] = (stq2_cmmt_ptr_remove[i] & stq2_cmmt_val) | + (stq2_cmmt_ptr_q[i] & stq2_cmmt_flushed_q) | + (stqe_need_ext_ack_q[i] & (any_ack_val_ok_q == stqe_thrd_id_q[i])) | + (stqe_held_early_clr_q[i] & stqe_data_val_q[i] & stq2_cmmt_val & stq2_cmmt_ptr_remove[i-`STQ_FWD_ENTRIES]); + end + + assign stqe_qHit_held_ctrl[i] = {stqe_qHit_held_set[i], stqe_qHit_held_clr[i]}; + + assign stqe_qHit_held_mux[i] = (stqe_qHit_held_ctrl[i] == 2'b00) ? stqe_qHit_held_q[i] : + (stqe_qHit_held_ctrl[i] == 2'b10) ? 1'b1 : + 1'b0; + assign stqe_qHit_held_d[i] = (stq_push_down == 1'b0) ? stqe_qHit_held_mux[i] : + stqe_qHit_held_mux[i + 1]; + + assign stqe_held_early_clr_d[i] = (stq_push_down == 1'b0) ? set_hold_early_clear[i] | (stqe_held_early_clr_q[i] & (~stqe_qHit_held_clr[i])) : + set_hold_early_clear[i + 1] | (stqe_held_early_clr_q[i + 1] & (~stqe_qHit_held_clr[i + 1])); + + // ICSWX CT mux select fields + assign stqe_icswx_ct_sel[i] = {stqe_data1_q[i][106:111], stqe_data1_q[i][114:119]}; + + if (`STQ_DATA_SIZE == 64) + begin : stqData64 + assign stqe_fwd_data[i] = ex4_fwd_data1[i]; + + if ((2 ** `GPR_WIDTH_ENC) == 64) + begin : fxDat64 + assign stqe_data1_mux[i] = (ctl_lsq_ex4_xu1_data & {64{(stqe_fxu1_data_sel[i])}}) | + (ex4_fu_data_q[64:127] & {64{(stqe_axu_data_sel[i])}}); + end + + if ((2 ** `GPR_WIDTH_ENC) == 32) + begin : fxDat32 + assign stqe_data1_mux[i][64:95] = ex4_fu_data_q[64:95]; + assign stqe_data1_mux[i][96:127] = (ctl_lsq_ex4_xu1_data & {32{(stqe_fxu1_data_sel[i])}}) | + (ex4_fu_data_q[96:127] & {32{(stqe_axu_data_sel[i])}}); + end + end + + if (`STQ_DATA_SIZE == 128) + begin : stqData128 + assign stqe_fwd_data[i][0:63] = stqe_data1_q[i][0:63]; + assign stqe_fwd_data[i][64:127] = ex4_fwd_data1[i]; + assign stqe_data1_mux[i][0:63] = ex4_fu_data_q[0:63]; + + if ((2 ** `GPR_WIDTH_ENC) == 64) + begin : fxDat64 + assign stqe_data1_mux[i][64:127] = (ctl_lsq_ex4_xu1_data & {64{(stqe_fxu1_data_sel[i])}}) | + (ex4_fu_data_q[64:127] & {64{(stqe_axu_data_sel[i])}}); + end + + if ((2 ** `GPR_WIDTH_ENC) == 32) + begin : fxDat32 + assign stqe_data1_mux[i][64:95] = ex4_fu_data_q[64:95]; + assign stqe_data1_mux[i][96:127] = (ctl_lsq_ex4_xu1_data & {32{(stqe_fxu1_data_sel[i])}}) | + (ex4_fu_data_q[96:127] & {32{(stqe_axu_data_sel[i])}}); + end + end + + assign stqe_data1_d[i] = (stq_push_down == 1'b0) ? stqe_data1_mux[i] : + ((stq_push_down == 1'b1 & stqe_data_val[i + 1] == 1'b1)) ? stqe_data1_mux[i + 1] : + stqe_data1_q[i + 1]; + end + end + endgenerate + + //------------------------------------------------------------------------------ + // interface staging / Flushing + //------------------------------------------------------------------------------ + // stq2 + // stq3 ex0 ---- + // stq4 rv2 + // stq5 rv1 + // stq5 rv0 + // stq6 iu6 + // stq7 iu5 + + assign rv1_i0_act = |(rv_lq_rv1_i0_vld); + assign rv1_i1_act = |(rv_lq_rv1_i1_vld); + assign ex0_i0_act = |(ex0_i0_vld_q); + assign ex0_i1_act = |(ex0_i1_vld_q); + + assign rv1_i0_vld = rv_lq_rv1_i0_vld & {`THREADS{rv_lq_rv1_i0_rte_sq}}; + assign rv1_i1_vld = rv_lq_rv1_i1_vld & {`THREADS{rv_lq_rv1_i1_rte_sq}}; + + // Need to return credits right away for ucode preissued stores, except for preissued ucode indexed load/store string ops + assign rv1_i0_drop_req = rv_lq_rv1_i0_rte_sq & rv_lq_rv1_i0_ucode_preissue & (~(rv_lq_rv1_i0_s3_t == 3'b100)); + assign rv1_i1_drop_req = rv_lq_rv1_i1_rte_sq & rv_lq_rv1_i1_ucode_preissue & (~(rv_lq_rv1_i1_s3_t == 3'b100)); + + assign rv0_cp_flush_d = cp_flush_q; + assign rv1_cp_flush_d = rv0_cp_flush_q; + + assign rv1_i0_flushed = |(rv1_i0_vld & (cp_flush_q | rv0_cp_flush_q | rv1_cp_flush_q | {`THREADS{rv1_i0_drop_req}})); + assign rv1_i1_flushed = |(rv1_i1_vld & (cp_flush_q | rv0_cp_flush_q | rv1_cp_flush_q | {`THREADS{rv1_i1_drop_req}})); + + assign ex0_i0_flushed = ex0_i0_flushed_q | |(ex0_i0_vld_q & cp_flush_q); + assign ex0_i1_flushed = ex0_i1_flushed_q | |(ex0_i1_vld_q & cp_flush_q); + + assign ex1_i0_flushed = ex1_i0_flushed_q | |(ex1_i0_vld_q & cp_flush_q); + assign ex1_i1_flushed = ex1_i1_flushed_q | |(ex1_i1_vld_q & cp_flush_q); + + assign ex2_streq_val = ctl_lsq_ex2_streq_val & (~cp_flush_q); + assign ex3_streq_val = ex3_streq_val_q & (~cp_flush_q); + assign ex4_streq_val = ctl_lsq_ex4_streq_val & (~cp_flush_q); + assign ex5_streq_val = ex5_streq_val_q & (~(cp_flush_q | {`THREADS{ctl_lsq_ex5_flush_req}})); + + assign ex3_ldreq_val = ctl_lsq_ex3_ldreq_val & (~cp_flush_q); + assign ex4_ldreq_val = ex4_ldreq_val_q & (~cp_flush_q); + + assign ex3_pfetch_val = ctl_lsq_ex3_pfetch_val; + assign ex4_pfetch_val_d = ex3_pfetch_val; + + assign ex4_ldreq_valid = |(ex4_ldreq_val); + assign ex3_streq_valid = |(ex3_streq_val_q); + assign ex4_streq_valid = |(ex4_streq_val); + assign ex5_streq_valid = |(ex5_streq_val); + + assign ex3_wchkall_val = ctl_lsq_ex3_wchkall_val & (~cp_flush_q); + assign ex4_wchkall_val = ex4_wchkall_val_q & (~cp_flush_q); + assign ex4_wchkall_valid = |(ex4_wchkall_val); + + //------------------------------------------------------------------------------ + // Generate Muxing Zzzzzzzzzzzz + //------------------------------------------------------------------------------ + + always @(*) + begin: cpl_ready_mux_proc + integer i; + cpl_ready_itag = 0; + cpl_ready_thrd_id = 0; + stq_ext_act_itag = 0; + stq_ext_act_dacrw_det = 0; + stq_ext_act_cr_wa = 0; + cpl_ttype = 0; + cpl_dreq_val = 1'b0; + stq_ext_act_dacrw_rpt = 1'b0; + + for (i = 0; i <= `STQ_ENTRIES - 1; i = i + 1) + begin + if (stqe_need_ready_ptr_q[i] == 1'b1) + begin + cpl_ready_itag = stqe_itag_q[i]; + cpl_ready_thrd_id = stqe_thrd_id_q[i]; + cpl_ttype = stqe_ttype_q[i]; + cpl_dreq_val = stqe_dreq_val_q[i]; + end + if ((stqe_need_ext_ack_q[i] == 1'b1) & (stqe_thrd_id_q[i] == any_ack_val)) + begin + stq_ext_act_itag = stqe_itag_q[i]; + stq_ext_act_dacrw_det = stqe_dacrw_q[i]; + stq_ext_act_dacrw_rpt = stqe_dvc_int_det[i]; + end + if ((stqe_need_ext_ack_q[i] == 1'b1) & (stqe_thrd_id_q[i] == cr_thrd)) + stq_ext_act_cr_wa = stqe_tgpr_q[i][AXU_TARGET_ENC - (`CR_POOL_ENC + `THREADS_POOL_ENC):AXU_TARGET_ENC - 1]; + end + end + + + always @(*) + begin: stq1_mux_proc + integer i; + stq_arb_stq1_axu_val = 0; + stq_arb_stq1_epid_val = 0; + lsq_dat_stq1_byte_en = 0; + stq_arb_stq1_opSize = 0; + stq_arb_stq1_wimge_i = 0; + lsq_ctl_stq1_lock_clr = 0; + lsq_ctl_stq1_watch_clr =0; + lsq_ctl_stq1_l_fld = 0; + lsq_ctl_stq1_inval = 0; + stq1_p_addr = 0; + stq_arb_stq1_thrd_id = 0; + lsq_ctl_stq1_resv = 0; + lsq_dat_stq1_store_val = 0; + lsq_ctl_stq1_store_val = 0; + stq_arb_stq1_byte_swap = 0; + stq_arb_stq1_store_data = 0; + stq1_ttype = 0; + stq1_wclr_all = 0; + + for (i = 0; i <= `STQ_ENTRIES - 1; i = i + 1) + if (stq1_cmmt_ptr_q[i] == 1'b1) + begin + stq_arb_stq1_axu_val = stqe_axu_val_q[i]; + stq_arb_stq1_epid_val = stqe_epid_val_q[i]; + lsq_dat_stq1_byte_en = stqe_byte_en_q[i]; + stq_arb_stq1_opSize = stqe_opsize_q[i]; + stq_arb_stq1_wimge_i = stqe_wimge_q[i][1]; + lsq_ctl_stq1_lock_clr = stqe_lock_clr_q[i]; + lsq_ctl_stq1_watch_clr = stqe_watch_clr_q[i]; + lsq_ctl_stq1_l_fld = stqe_l_fld_q[i]; + lsq_ctl_stq1_inval = stqe_is_inval_op_q[i]; + stq1_p_addr = stqe_addr_q[i]; + stq_arb_stq1_thrd_id = stqe_thrd_id_q[i]; + lsq_ctl_stq1_resv = stqe_is_resv_q[i]; + lsq_dat_stq1_store_val = stqe_is_store_q[i]; + lsq_ctl_stq1_store_val = stqe_is_store_q[i]; + stq_arb_stq1_byte_swap = stqe_byte_swap_q[i]; + stq_arb_stq1_store_data = stqe_data1_q[i]; + stq1_ttype = stqe_ttype_q[i]; + stq1_wclr_all = stqe_watch_clr_q[i] & (~stqe_l_fld_q[i][0]); + end + end + + assign stq_arb_stq1_p_addr = stq1_p_addr; + + + always @(*) + begin: stq2_mux_proc + integer i; + + stq2_thrd_id = 0; + icbi_addr_d = 0; + + for (i = 0; i <= `STQ_ENTRIES - 1; i = i + 1) + if (stq2_cmmt_ptr_q[i] == 1'b1) + begin + stq2_thrd_id = stqe_thrd_id_q[i]; + icbi_addr_d = stqe_addr_q[i][RI:57]; + end + end + + + always @(*) + begin: stq3_mux_proc + integer i; + + stq_arb_stq3_wimge = 0; + stq_arb_stq3_p_addr = 0; + stq_arb_stq3_opSize = 0; + stq_arb_stq3_usrDef = 0; + stq_arb_stq3_byteEn = 0; + stq3_ttype = 0; + stq3_tid = 0; + + for (i = 0; i <= `STQ_ENTRIES - 1; i = i + 1) + if (stq3_cmmt_ptr_q[i] == 1'b1) + begin + stq_arb_stq3_wimge = stqe_wimge_q[i]; + stq_arb_stq3_p_addr = stqe_addr_q[i]; + stq_arb_stq3_opSize = stqe_opsize_q[i]; + stq_arb_stq3_usrDef = stqe_usr_def_q[i]; + stq_arb_stq3_byteEn = stqe_byte_en_q[i]; + stq3_ttype = stqe_ttype_q[i]; + stq3_tid = stqe_thrd_id_q[i]; + end + end + + + always @(*) + begin: stq5_mux_proc + integer i; + + lsq_ctl_stq5_itag = 0; + lsq_ctl_stq5_tgpr = 0; + + for (i = 0; i <= `STQ_ENTRIES - 1; i = i + 1) + if (stq5_cmmt_ptr_q[i] == 1'b1) + begin + lsq_ctl_stq5_itag = stqe_itag_q[i]; + lsq_ctl_stq5_tgpr = stqe_tgpr_q[i]; + end + end + + + always @(*) + begin: stq6_mux_proc + integer i; + + stq6_ttype = 0; + stq6_tid = 0; + stq6_wclr_all_val = 0; + + for (i = 0; i <= `STQ_ENTRIES - 1; i = i + 1) + if (stq6_cmmt_ptr_q[i] == 1'b1) + begin + stq6_ttype = stqe_ttype_q[i]; + stq6_wclr_all_val = stqe_watch_clr_q[i] & (~stqe_l_fld_q[i][0]); + stq6_tid = stqe_thrd_id_q[i]; + end + end + + assign stq_fwd_pri_mask_q[`STQ_FWD_ENTRIES - 1] = 1'b0; + + + always @(*) + begin: stq_data_mux_proc + integer i; + ex5_fwd_data_d = 0; + + for (i = 0; i <= `STQ_FWD_ENTRIES - 1; i = i + 1) + if ((ex4_fwd_sel[i] & (~stq_fwd_pri_mask_q[i])) == 1'b1) + ex5_fwd_data_d = stqe_fwd_data[i]; + end + +//------------------------------------------------------------------------------ +// Latch Instances +//------------------------------------------------------------------------------ + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rv_lq_vld_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rv_lq_vld_offset]), + .scout(sov[rv_lq_vld_offset]), + .din(rv_lq_vld_d), + .dout(rv_lq_vld_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rv_lq_ld_vld_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rv_lq_ld_vld_offset]), + .scout(sov[rv_lq_ld_vld_offset]), + .din(rv_lq_ld_vld_d), + .dout(rv_lq_ld_vld_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_dir_rd_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_dir_rd_val_offset]), + .scout(sov[ex0_dir_rd_val_offset]), + .din(ex0_dir_rd_val_d), + .dout(ex0_dir_rd_val_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) rv0_cp_flush_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rv0_cp_flush_offset:rv0_cp_flush_offset + `THREADS - 1]), + .scout(sov[rv0_cp_flush_offset:rv0_cp_flush_offset + `THREADS - 1]), + .din(rv0_cp_flush_d), + .dout(rv0_cp_flush_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) rv1_cp_flush_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rv1_cp_flush_offset:rv1_cp_flush_offset + `THREADS - 1]), + .scout(sov[rv1_cp_flush_offset:rv1_cp_flush_offset + `THREADS - 1]), + .din(rv1_cp_flush_d), + .dout(rv1_cp_flush_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex0_i0_vld_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_i0_vld_offset:ex0_i0_vld_offset + `THREADS - 1]), + .scout(sov[ex0_i0_vld_offset:ex0_i0_vld_offset + `THREADS - 1]), + .din(rv1_i0_vld), + .dout(ex0_i0_vld_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_i0_flushed_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_i0_flushed_offset]), + .scout(sov[ex0_i0_flushed_offset]), + .din(rv1_i0_flushed), + .dout(ex0_i0_flushed_q) +); + +tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex0_i0_itag_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rv1_i0_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_i0_itag_offset:ex0_i0_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[ex0_i0_itag_offset:ex0_i0_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(rv_lq_rv1_i0_itag), + .dout(ex0_i0_itag_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex0_i1_vld_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_i1_vld_offset:ex0_i1_vld_offset + `THREADS - 1]), + .scout(sov[ex0_i1_vld_offset:ex0_i1_vld_offset + `THREADS - 1]), + .din(rv1_i1_vld), + .dout(ex0_i1_vld_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_i1_flushed_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_i1_flushed_offset]), + .scout(sov[ex0_i1_flushed_offset]), + .din(rv1_i1_flushed), + .dout(ex0_i1_flushed_q) +); + +tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex0_i1_itag_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rv1_i1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_i1_itag_offset:ex0_i1_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[ex0_i1_itag_offset:ex0_i1_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(rv_lq_rv1_i1_itag), + .dout(ex0_i1_itag_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex1_i0_vld_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_i0_vld_offset:ex1_i0_vld_offset + `THREADS - 1]), + .scout(sov[ex1_i0_vld_offset:ex1_i0_vld_offset + `THREADS - 1]), + .din(ex0_i0_vld_q), + .dout(ex1_i0_vld_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_i0_flushed_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_i0_flushed_offset]), + .scout(sov[ex1_i0_flushed_offset]), + .din(ex0_i0_flushed), + .dout(ex1_i0_flushed_q) +); + +tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex1_i0_itag_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex0_i0_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_i0_itag_offset:ex1_i0_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[ex1_i0_itag_offset:ex1_i0_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(ex0_i0_itag_q), + .dout(ex1_i0_itag_q) +); + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex1_i1_vld_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_i1_vld_offset:ex1_i1_vld_offset + `THREADS - 1]), + .scout(sov[ex1_i1_vld_offset:ex1_i1_vld_offset + `THREADS - 1]), + .din(ex0_i1_vld_q), + .dout(ex1_i1_vld_q) +); + +tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_i1_flushed_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_i1_flushed_offset]), + .scout(sov[ex1_i1_flushed_offset]), + .din(ex0_i1_flushed), + .dout(ex1_i1_flushed_q) +); + +tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex1_i1_itag_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex0_i1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_i1_itag_offset:ex1_i1_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[ex1_i1_itag_offset:ex1_i1_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(ex0_i1_itag_q), + .dout(ex1_i1_itag_q) +); + +tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(2 ** (`STQ_ENTRIES - 1)), .NEEDS_SRESET(1)) stqe_alloc_ptr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(stq_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_alloc_ptr_offset:stqe_alloc_ptr_offset + `STQ_ENTRIES - 1]), + .scout(sov[stqe_alloc_ptr_offset:stqe_alloc_ptr_offset + `STQ_ENTRIES - 1]), + .din(stqe_alloc_ptr_d), + .dout(stqe_alloc_ptr_q) +); + +tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stqe_alloc_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(stq_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_alloc_offset:stqe_alloc_offset + `STQ_ENTRIES - 1]), + .scout(sov[stqe_alloc_offset:stqe_alloc_offset + `STQ_ENTRIES - 1]), + .din(stqe_alloc_d), + .dout(stqe_alloc_q[0:`STQ_ENTRIES - 1]) +); + +tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stqe_addr_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(stq_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_addr_val_offset:stqe_addr_val_offset + `STQ_ENTRIES - 1]), + .scout(sov[stqe_addr_val_offset:stqe_addr_val_offset + `STQ_ENTRIES - 1]), + .din(stqe_addr_val_d), + .dout(stqe_addr_val_q[0:`STQ_ENTRIES - 1]) +); + +tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stqe_fwd_addr_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(stq_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_fwd_addr_val_offset:stqe_fwd_addr_val_offset + `STQ_ENTRIES - 1]), + .scout(sov[stqe_fwd_addr_val_offset:stqe_fwd_addr_val_offset + `STQ_ENTRIES - 1]), + .din(stqe_fwd_addr_val_d), + .dout(stqe_fwd_addr_val_q[0:`STQ_ENTRIES - 1]) +); + +tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stqe_data_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(stq_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_data_val_offset:stqe_data_val_offset + `STQ_ENTRIES - 1]), + .scout(sov[stqe_data_val_offset:stqe_data_val_offset + `STQ_ENTRIES - 1]), + .din(stqe_data_val_d), + .dout(stqe_data_val_q[0:`STQ_ENTRIES - 1]) +); + +tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stqe_data_nxt_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(stq_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_data_nxt_offset:stqe_data_nxt_offset + `STQ_ENTRIES - 1]), + .scout(sov[stqe_data_nxt_offset:stqe_data_nxt_offset + `STQ_ENTRIES - 1]), + .din(stqe_data_nxt_d), + .dout(stqe_data_nxt_q[0:`STQ_ENTRIES - 1]) +); + +tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stqe_illeg_lswx_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(stq_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_illeg_lswx_offset:stqe_illeg_lswx_offset + `STQ_ENTRIES - 1]), + .scout(sov[stqe_illeg_lswx_offset:stqe_illeg_lswx_offset + `STQ_ENTRIES - 1]), + .din(stqe_illeg_lswx_d), + .dout(stqe_illeg_lswx_q[0:`STQ_ENTRIES - 1]) +); + +tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stqe_strg_noop_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(stq_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_strg_noop_offset:stqe_strg_noop_offset + `STQ_ENTRIES - 1]), + .scout(sov[stqe_strg_noop_offset:stqe_strg_noop_offset + `STQ_ENTRIES - 1]), + .din(stqe_strg_noop_d), + .dout(stqe_strg_noop_q[0:`STQ_ENTRIES - 1]) +); + +tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stqe_ready_sent_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(stq_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_ready_sent_offset:stqe_ready_sent_offset + `STQ_ENTRIES - 1]), + .scout(sov[stqe_ready_sent_offset:stqe_ready_sent_offset + `STQ_ENTRIES - 1]), + .din(stqe_ready_sent_d), + .dout(stqe_ready_sent_q[0:`STQ_ENTRIES - 1]) +); + +tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stqe_odq_resolved_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(stq_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_odq_resolved_offset:stqe_odq_resolved_offset + `STQ_ENTRIES - 1]), + .scout(sov[stqe_odq_resolved_offset:stqe_odq_resolved_offset + `STQ_ENTRIES - 1]), + .din(stqe_odq_resolved_d), + .dout(stqe_odq_resolved_q[0:`STQ_ENTRIES - 1]) +); + +tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stqe_compl_rcvd_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(stq_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_compl_rcvd_offset:stqe_compl_rcvd_offset + `STQ_ENTRIES - 1]), + .scout(sov[stqe_compl_rcvd_offset:stqe_compl_rcvd_offset + `STQ_ENTRIES - 1]), + .din(stqe_compl_rcvd_d), + .dout(stqe_compl_rcvd_q[0:`STQ_ENTRIES - 1]) +); + +tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stqe_have_cp_next_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(stq_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_have_cp_next_offset:stqe_have_cp_next_offset + `STQ_ENTRIES - 1]), + .scout(sov[stqe_have_cp_next_offset:stqe_have_cp_next_offset + `STQ_ENTRIES - 1]), + .din(stqe_have_cp_next_d), + .dout(stqe_have_cp_next_q[0:`STQ_ENTRIES - 1]) +); + +tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(2 ** (`STQ_ENTRIES - 1)), .NEEDS_SRESET(1)) stqe_need_ready_ptr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(stqe_need_ready_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_need_ready_ptr_offset:stqe_need_ready_ptr_offset + `STQ_ENTRIES - 1]), + .scout(sov[stqe_need_ready_ptr_offset:stqe_need_ready_ptr_offset + `STQ_ENTRIES - 1]), + .din(stqe_need_ready_ptr_d), + .dout(stqe_need_ready_ptr_q[0:`STQ_ENTRIES - 1]) +); + +tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stqe_flushed_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(stq_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_flushed_offset:stqe_flushed_offset + `STQ_ENTRIES - 1]), + .scout(sov[stqe_flushed_offset:stqe_flushed_offset + `STQ_ENTRIES - 1]), + .din(stqe_flushed_d), + .dout(stqe_flushed_q[0:`STQ_ENTRIES - 1]) +); + +tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stqe_ack_rcvd_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(stq_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_ack_rcvd_offset:stqe_ack_rcvd_offset + `STQ_ENTRIES - 1]), + .scout(sov[stqe_ack_rcvd_offset:stqe_ack_rcvd_offset + `STQ_ENTRIES - 1]), + .din(stqe_ack_rcvd_d), + .dout(stqe_ack_rcvd_q[0:`STQ_ENTRIES - 1]) +); +generate + begin : xhdl15 + genvar i; + for (i = 0; i <= `STQ_ENTRIES - 1; i = i + 1) + begin : stqe_lmqhit_latch_gen + + tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stqe_lmqhit_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(stq_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_lmqhit_offset + `LMQ_ENTRIES * i:stqe_lmqhit_offset + `LMQ_ENTRIES * (i + 1) - 1]), + .scout(sov[stqe_lmqhit_offset + `LMQ_ENTRIES * i:stqe_lmqhit_offset + `LMQ_ENTRIES * (i + 1) - 1]), + .din(stqe_lmqhit_d[i]), + .dout(stqe_lmqhit_q[i]) + ); + end + end +endgenerate +generate + begin : xhdl16 + genvar i; + for (i = 0; i <= `STQ_ENTRIES - 1; i = i + 1) + begin : stqe_need_ext_ack_latch_gen + + tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stqe_need_ext_ack_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex4_addr_act[i]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_need_ext_ack_offset + i:stqe_need_ext_ack_offset + i]), + .scout(sov[stqe_need_ext_ack_offset + i:stqe_need_ext_ack_offset + i]), + .din(stqe_need_ext_ack_d[i]), + .dout(stqe_need_ext_ack_q[i]) + ); + end + end + endgenerate + +generate + begin : stqe_blk_loads_latch_gen + genvar i; + for (i = 0; i <= `STQ_ENTRIES - 1; i = i + 1) begin : stqe_blk_loads_latch_gen + + tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stqe_blk_loads_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex4_addr_act[i]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_blk_loads_offset + i:stqe_blk_loads_offset + i]), + .scout(sov[stqe_blk_loads_offset + i:stqe_blk_loads_offset + i]), + .din(stqe_blk_loads_d[i]), + .dout(stqe_blk_loads_q[i]) + ); + end + end + endgenerate + +generate + begin : xhdl57 + genvar i; + for (i = 0; i <= `STQ_ENTRIES - 1; i = i + 1) + begin : stqe_all_thrd_chk_latch_gen + + tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stqe_all_thrd_chk_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex4_addr_act[i]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_all_thrd_chk_offset + i:stqe_all_thrd_chk_offset + i]), + .scout(sov[stqe_all_thrd_chk_offset + i:stqe_all_thrd_chk_offset + i]), + .din(stqe_all_thrd_chk_d[i]), + .dout(stqe_all_thrd_chk_q[i]) + ); + end + end + endgenerate + + generate + begin : xhdl17 + genvar i; + for (i = 0; i <= `STQ_ENTRIES - 1; i = i + 1) + begin : stqe_itag_latch_gen + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) + stqe_itag_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(stqe_itag_act[i]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_itag_offset + `ITAG_SIZE_ENC * i:stqe_itag_offset + `ITAG_SIZE_ENC * (i + 1) - 1]), + .scout(sov[stqe_itag_offset + `ITAG_SIZE_ENC * i:stqe_itag_offset + `ITAG_SIZE_ENC * (i + 1) - 1]), + .din(stqe_itag_d[i]), + .dout(stqe_itag_q[i]) + ); + end + end + endgenerate + generate + begin : xhdl18 + genvar i; + for (i = 0; i <= `STQ_ENTRIES - 1; i = i + 1) + begin : stqe_addr_latch_gen + + tri_rlmreg_p #(.WIDTH(`REAL_IFAR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) stqe_addr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex4_addr_act[i]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_addr_offset + `REAL_IFAR_WIDTH * i:stqe_addr_offset + `REAL_IFAR_WIDTH * (i + 1) - 1]), + .scout(sov[stqe_addr_offset + `REAL_IFAR_WIDTH * i:stqe_addr_offset + `REAL_IFAR_WIDTH * (i + 1) - 1]), + .din(stqe_addr_d[i]), + .dout(stqe_addr_q[i]) + ); + end + end + endgenerate + generate + begin : xhdl19 + genvar i; + for (i = 0; i <= `STQ_ENTRIES - 1; i = i + 1) + begin : stqe_rotcmp_latch_gen + + tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) stqe_rotcmp_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_addr_act[i]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_rotcmp_offset + 16 * i:stqe_rotcmp_offset + 16 * (i + 1) - 1]), + .scout(sov[stqe_rotcmp_offset + 16 * i:stqe_rotcmp_offset + 16 * (i + 1) - 1]), + .din(stqe_rotcmp_d[i]), + .dout(stqe_rotcmp_q[i]) + ); + end + end + endgenerate + generate + begin : xhdl20 + genvar i; + for (i = 0; i <= `STQ_ENTRIES-1; i = i + 1) + begin : stqe_cline_chk_latch_gen + + tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stqe_cline_chk_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex4_addr_act[i]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_cline_chk_offset + i:stqe_cline_chk_offset + i]), + .scout(sov[stqe_cline_chk_offset + i:stqe_cline_chk_offset + i]), + .din(stqe_cline_chk_d[i]), + .dout(stqe_cline_chk_q[i]) + ); + end + end + endgenerate + generate + begin : xhdl21 + genvar i; + for (i = 0; i <= `STQ_ENTRIES-1; i = i + 1) + begin : stqe_ttype_latch_gen + + tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) stqe_ttype_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex5_addr_act[i]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_ttype_offset + 6 * i:stqe_ttype_offset + 6 * (i + 1) - 1]), + .scout(sov[stqe_ttype_offset + 6 * i:stqe_ttype_offset + 6 * (i + 1) - 1]), + .din(stqe_ttype_d[i]), + .dout(stqe_ttype_q[i]) + ); + end + end + endgenerate + generate + begin : xhdl22 + genvar i; + for (i = 0; i <= `STQ_ENTRIES-1; i = i + 1) + begin : stqe_byte_en_latch_gen + + tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) stqe_byte_en_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_addr_act[i]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_byte_en_offset + 16 * i:stqe_byte_en_offset + 16 * (i + 1) - 1]), + .scout(sov[stqe_byte_en_offset + 16 * i:stqe_byte_en_offset + 16 * (i + 1) - 1]), + .din(stqe_byte_en_d[i]), + .dout(stqe_byte_en_q[i]) + ); + end + end + endgenerate + generate + begin : xhdl23 + genvar i; + for (i = 0; i <= `STQ_ENTRIES-1; i = i + 1) + begin : stqe_wimge_latch_gen + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) stqe_wimge_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex4_addr_act[i]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_wimge_offset + 5 * i:stqe_wimge_offset + 5 * (i + 1) - 1]), + .scout(sov[stqe_wimge_offset + 5 * i:stqe_wimge_offset + 5 * (i + 1) - 1]), + .din(stqe_wimge_d[i]), + .dout(stqe_wimge_q[i]) + ); + end + end + endgenerate + generate + begin : xhdl24 + genvar i; + for (i = 0; i <= `STQ_ENTRIES-1; i = i + 1) + begin : stqe_byte_swap_latch_gen + + tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stqe_byte_swap_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex4_addr_act[i]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_byte_swap_offset + i:stqe_byte_swap_offset + i]), + .scout(sov[stqe_byte_swap_offset + i:stqe_byte_swap_offset + i]), + .din(stqe_byte_swap_d[i]), + .dout(stqe_byte_swap_q[i]) + ); + end + end + endgenerate + generate + begin : xhdl25 + genvar i; + for (i = 0; i <= `STQ_ENTRIES-1; i = i + 1) + begin : stqe_opsize_latch_gen + + tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) stqe_opsize_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex4_addr_act[i]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_opsize_offset + 3 * i:stqe_opsize_offset + 3 * (i + 1) - 1]), + .scout(sov[stqe_opsize_offset + 3 * i:stqe_opsize_offset + 3 * (i + 1) - 1]), + .din(stqe_opsize_d[i]), + .dout(stqe_opsize_q[i]) + ); + end + end + endgenerate + generate + begin : xhdl26 + genvar i; + for (i = 0; i <= `STQ_ENTRIES-1; i = i + 1) + begin : stqe_axu_val_latch_gen + + tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stqe_axu_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex5_addr_act[i]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_axu_val_offset + i:stqe_axu_val_offset + i]), + .scout(sov[stqe_axu_val_offset + i:stqe_axu_val_offset + i]), + .din(stqe_axu_val_d[i]), + .dout(stqe_axu_val_q[i]) + ); + end + end + endgenerate + generate + begin : xhdl27 + genvar i; + for (i = 0; i <= `STQ_ENTRIES-1; i = i + 1) + begin : stqe_epid_val_latch_gen + + tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stqe_epid_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex5_addr_act[i]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_epid_val_offset + i:stqe_epid_val_offset + i]), + .scout(sov[stqe_epid_val_offset + i:stqe_epid_val_offset + i]), + .din(stqe_epid_val_d[i]), + .dout(stqe_epid_val_q[i]) + ); + end + end + endgenerate + generate + begin : xhdl28 + genvar i; + for (i = 0; i <= `STQ_ENTRIES-1; i = i + 1) + begin : stqe_usr_def_latch_gen + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) stqe_usr_def_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex5_addr_act[i]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_usr_def_offset + 4 * i:stqe_usr_def_offset + 4 * (i + 1) - 1]), + .scout(sov[stqe_usr_def_offset + 4 * i:stqe_usr_def_offset + 4 * (i + 1) - 1]), + .din(stqe_usr_def_d[i]), + .dout(stqe_usr_def_q[i]) + ); + end + end + endgenerate + generate + begin : xhdl29 + genvar i; + for (i = 0; i <= `STQ_ENTRIES-1; i = i + 1) + begin : stqe_is_store_latch_gen + + tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stqe_is_store_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex4_addr_act[i]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_is_store_offset + i:stqe_is_store_offset + i]), + .scout(sov[stqe_is_store_offset + i:stqe_is_store_offset + i]), + .din(stqe_is_store_d[i]), + .dout(stqe_is_store_q[i]) + ); + end + end + endgenerate + generate + begin : xhdl30 + genvar i; + for (i = 0; i <= `STQ_ENTRIES-1; i = i + 1) + begin : stqe_is_sync_latch_gen + + tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stqe_is_sync_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex4_addr_act[i]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_is_sync_offset + i:stqe_is_sync_offset + i]), + .scout(sov[stqe_is_sync_offset + i:stqe_is_sync_offset + i]), + .din(stqe_is_sync_d[i]), + .dout(stqe_is_sync_q[i]) + ); + end + end + endgenerate + generate + begin : xhdl31 + genvar i; + for (i = 0; i <= `STQ_ENTRIES-1; i = i + 1) + begin : stqe_is_resv_latch_gen + + tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stqe_is_resv_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex4_addr_act[i]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_is_resv_offset + i:stqe_is_resv_offset + i]), + .scout(sov[stqe_is_resv_offset + i:stqe_is_resv_offset + i]), + .din(stqe_is_resv_d[i]), + .dout(stqe_is_resv_q[i]) + ); + end + end + endgenerate + generate + begin : xhdl32 + genvar i; + for (i = 0; i <= `STQ_ENTRIES-1; i = i + 1) + begin : stqe_is_icswxr_latch_gen + + tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stqe_is_icswxr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex4_addr_act[i]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_is_icswxr_offset + i:stqe_is_icswxr_offset + i]), + .scout(sov[stqe_is_icswxr_offset + i:stqe_is_icswxr_offset + i]), + .din(stqe_is_icswxr_d[i]), + .dout(stqe_is_icswxr_q[i]) + ); + end + end + endgenerate + generate + begin : xhdl33 + genvar i; + for (i = 0; i <= `STQ_ENTRIES-1; i = i + 1) + begin : stqe_is_icbi_latch_gen + + tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stqe_is_icbi_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex4_addr_act[i]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_is_icbi_offset + i:stqe_is_icbi_offset + i]), + .scout(sov[stqe_is_icbi_offset + i:stqe_is_icbi_offset + i]), + .din(stqe_is_icbi_d[i]), + .dout(stqe_is_icbi_q[i]) + ); + end + end + endgenerate + generate + begin : xhdl34 + genvar i; + for (i = 0; i <= `STQ_ENTRIES-1; i = i + 1) + begin : stqe_is_inval_op_latch_gen + + tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stqe_is_inval_op_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex4_addr_act[i]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_is_inval_op_offset + i:stqe_is_inval_op_offset + i]), + .scout(sov[stqe_is_inval_op_offset + i:stqe_is_inval_op_offset + i]), + .din(stqe_is_inval_op_d[i]), + .dout(stqe_is_inval_op_q[i]) + ); + end + end + endgenerate + generate + begin : xhdl35 + genvar i; + for (i = 0; i <= `STQ_ENTRIES-1; i = i + 1) + begin : stqe_dreq_val_latch_gen + + tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stqe_dreq_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex4_addr_act[i]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_dreq_val_offset + i:stqe_dreq_val_offset + i]), + .scout(sov[stqe_dreq_val_offset + i:stqe_dreq_val_offset + i]), + .din(stqe_dreq_val_d[i]), + .dout(stqe_dreq_val_q[i]) + ); + end + end + endgenerate + generate + begin : xhdl36 + genvar i; + for (i = 0; i <= `STQ_ENTRIES-1; i = i + 1) + begin : stqe_has_data_latch_gen + + tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stqe_has_data_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex4_addr_act[i]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_has_data_offset + i:stqe_has_data_offset + i]), + .scout(sov[stqe_has_data_offset + i:stqe_has_data_offset + i]), + .din(stqe_has_data_d[i]), + .dout(stqe_has_data_q[i]) + ); + end + end + endgenerate + generate + begin : xhdl37 + genvar i; + for (i = 0; i <= `STQ_ENTRIES-1; i = i + 1) + begin : stqe_send_l2_latch_gen + + tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stqe_send_l2_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex4_addr_act[i]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_send_l2_offset + i:stqe_send_l2_offset + i]), + .scout(sov[stqe_send_l2_offset + i:stqe_send_l2_offset + i]), + .din(stqe_send_l2_d[i]), + .dout(stqe_send_l2_q[i]) + ); + end + end + endgenerate + generate + begin : xhdl38 + genvar i; + for (i = 0; i <= `STQ_ENTRIES-1; i = i + 1) + begin : stqe_lock_clr_latch_gen + + tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stqe_lock_clr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex5_addr_act[i]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_lock_clr_offset + i:stqe_lock_clr_offset + i]), + .scout(sov[stqe_lock_clr_offset + i:stqe_lock_clr_offset + i]), + .din(stqe_lock_clr_d[i]), + .dout(stqe_lock_clr_q[i]) + ); + end + end + endgenerate + generate + begin : xhdl39 + genvar i; + for (i = 0; i <= `STQ_ENTRIES-1; i = i + 1) + begin : stqe_watch_clr_latch_gen + + tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stqe_watch_clr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex4_addr_act[i]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_watch_clr_offset + i:stqe_watch_clr_offset + i]), + .scout(sov[stqe_watch_clr_offset + i:stqe_watch_clr_offset + i]), + .din(stqe_watch_clr_d[i]), + .dout(stqe_watch_clr_q[i]) + ); + end + end + endgenerate + generate + begin : xhdl40 + genvar i; + for (i = 0; i <= `STQ_ENTRIES - 1; i = i + 1) + begin : stqe_l_fld_latch_gen + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) stqe_l_fld_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex5_addr_act[i]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_l_fld_offset + 2 * i:stqe_l_fld_offset + 2 * (i + 1) - 1]), + .scout(sov[stqe_l_fld_offset + 2 * i:stqe_l_fld_offset + 2 * (i + 1) - 1]), + .din(stqe_l_fld_d[i]), + .dout(stqe_l_fld_q[i]) + ); + end + end + endgenerate + generate + begin : xhdl41 + genvar i; + for (i = 0; i <= `STQ_ENTRIES - 1; i = i + 1) + begin : stqe_thrd_id_latch_gen + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) stqe_thrd_id_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(stqe_itag_act[i]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_thrd_id_offset + `THREADS * i:stqe_thrd_id_offset + `THREADS * (i + 1) - 1]), + .scout(sov[stqe_thrd_id_offset + `THREADS * i:stqe_thrd_id_offset + `THREADS * (i + 1) - 1]), + .din(stqe_thrd_id_d[i]), + .dout(stqe_thrd_id_q[i]) + ); + end + end + endgenerate + generate + begin : xhdl42 + genvar i; + for (i = 0; i <= `STQ_ENTRIES - 1; i = i + 1) + begin : stqe_tgpr_latch_gen + + tri_rlmreg_p #(.WIDTH(AXU_TARGET_ENC), .INIT(0), .NEEDS_SRESET(1)) stqe_tgpr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex5_addr_act[i]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_tgpr_offset + AXU_TARGET_ENC * i:stqe_tgpr_offset + AXU_TARGET_ENC * (i + 1) - 1]), + .scout(sov[stqe_tgpr_offset + AXU_TARGET_ENC * i:stqe_tgpr_offset + AXU_TARGET_ENC * (i + 1) - 1]), + .din(stqe_tgpr_d[i]), + .dout(stqe_tgpr_q[i]) + ); + end + end + endgenerate + generate + begin : xhdl43 + genvar i; + for (i = 0; i <= `STQ_ENTRIES - 1; i = i + 1) + begin : stqe_dvc_en_latch_gen + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) stqe_dvc_en_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex5_addr_act[i]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_dvc_en_offset + 2 * i:stqe_dvc_en_offset + 2 * (i + 1) - 1]), + .scout(sov[stqe_dvc_en_offset + 2 * i:stqe_dvc_en_offset + 2 * (i + 1) - 1]), + .din(stqe_dvc_en_d[i]), + .dout(stqe_dvc_en_q[i]) + ); + end + end + endgenerate + generate + begin : xhdl44 + genvar i; + for (i = 0; i <= `STQ_ENTRIES - 1; i = i + 1) + begin : stqe_dacrw_latch_gen + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) stqe_dacrw_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex5_addr_act[i]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_dacrw_offset + 4 * i:stqe_dacrw_offset + 4 * (i + 1) - 1]), + .scout(sov[stqe_dacrw_offset + 4 * i:stqe_dacrw_offset + 4 * (i + 1) - 1]), + .din(stqe_dacrw_d[i]), + .dout(stqe_dacrw_q[i]) + ); + end + end + endgenerate + generate + begin : xhdl45 + genvar i; + for (i = 0; i <= `STQ_ENTRIES - 1; i = i + 1) + begin : stqe_dvcr_cmpr_latch_gen + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) stqe_dvcr_cmpr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(stq_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_dvcr_cmpr_offset + 2 * i:stqe_dvcr_cmpr_offset + 2 * (i + 1) - 1]), + .scout(sov[stqe_dvcr_cmpr_offset + 2 * i:stqe_dvcr_cmpr_offset + 2 * (i + 1) - 1]), + .din(stqe_dvcr_cmpr_d[i]), + .dout(stqe_dvcr_cmpr_q[i]) + ); + end + end + endgenerate + generate + begin : xhdl47 + genvar i; + for (i = 0; i <= `STQ_ENTRIES-1; i = i + 1) + begin : stqe_qHit_held_latch_gen + + tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stqe_qHit_held_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(stq_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_qHit_held_offset + i:stqe_qHit_held_offset + i]), + .scout(sov[stqe_qHit_held_offset + i:stqe_qHit_held_offset + i]), + .din(stqe_qHit_held_d[i]), + .dout(stqe_qHit_held_q[i]) + ); + end + end + endgenerate + generate + begin : xhdl48 + genvar i; + for (i = 0; i <= `STQ_ENTRIES-1; i = i + 1) + begin : stqe_held_early_clr_latch_gen + + tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stqe_held_early_clr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(stq_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_held_early_clr_offset + i:stqe_held_early_clr_offset + i]), + .scout(sov[stqe_held_early_clr_offset + i:stqe_held_early_clr_offset + i]), + .din(stqe_held_early_clr_d[i]), + .dout(stqe_held_early_clr_q[i]) + ); + end + end + endgenerate + generate + begin : xhdl49 + genvar i; + for (i = 0; i <= `STQ_ENTRIES-1; i = i + 1) + begin : stqe_data1_latch_gen + + tri_rlmreg_p #(.WIDTH(`STQ_DATA_SIZE), .INIT(0), .NEEDS_SRESET(1)) stqe_data1_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(stqe_data_act[i]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stqe_data1_offset + `STQ_DATA_SIZE * i:stqe_data1_offset + `STQ_DATA_SIZE * (i + 1) - 1]), + .scout(sov[stqe_data1_offset + `STQ_DATA_SIZE * i:stqe_data1_offset + `STQ_DATA_SIZE * (i + 1) - 1]), + .din(stqe_data1_d[i]), + .dout(stqe_data1_q[i]) + ); + end + end + endgenerate + + tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex4_fxu1_data_ptr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_fxu1_val), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_fxu1_data_ptr_offset:ex4_fxu1_data_ptr_offset + `STQ_ENTRIES - 1]), + .scout(sov[ex4_fxu1_data_ptr_offset:ex4_fxu1_data_ptr_offset + `STQ_ENTRIES - 1]), + .din(ex4_fxu1_data_ptr_d), + .dout(ex4_fxu1_data_ptr_q) + ); + + tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex4_axu_data_ptr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_axu_val), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_axu_data_ptr_offset:ex4_axu_data_ptr_offset + `STQ_ENTRIES - 1]), + .scout(sov[ex4_axu_data_ptr_offset:ex4_axu_data_ptr_offset + `STQ_ENTRIES - 1]), + .din(ex4_axu_data_ptr_d), + .dout(ex4_axu_data_ptr_q) + ); + + tri_rlmreg_p #(.WIDTH((`STQ_DATA_SIZE)), .INIT(0), .NEEDS_SRESET(1)) ex4_fu_data_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_axu_val), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_fu_data_offset:ex4_fu_data_offset + (`STQ_DATA_SIZE) - 1]), + .scout(sov[ex4_fu_data_offset:ex4_fu_data_offset + (`STQ_DATA_SIZE) - 1]), + .din(xu_lq_axu_exp1_stq_data), + .dout(ex4_fu_data_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) cp_flush_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[cp_flush_offset:cp_flush_offset + `THREADS - 1]), + .scout(sov[cp_flush_offset:cp_flush_offset + `THREADS - 1]), + .din(iu_lq_cp_flush), + .dout(cp_flush_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) cp_next_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[cp_next_val_offset:cp_next_val_offset + `THREADS - 1]), + .scout(sov[cp_next_val_offset:cp_next_val_offset + `THREADS - 1]), + .din(iu_lq_cp_next_val), + .dout(cp_next_val_q) + ); + + generate + begin : xhdl50 + genvar i; + for (i = 0; i <= `THREADS-1; i = i + 1) + begin : cp_next_itag_latch_gen + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) cp_next_itag_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(iu_lq_cp_next_val[i]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[cp_next_itag_offset + `ITAG_SIZE_ENC * i:cp_next_itag_offset + `ITAG_SIZE_ENC * (i + 1) - 1]), + .scout(sov[cp_next_itag_offset + `ITAG_SIZE_ENC * i:cp_next_itag_offset + `ITAG_SIZE_ENC * (i + 1) - 1]), + .din(iu_lq_cp_next_itag_int[i]), + .dout(cp_next_itag_q[i]) + ); + end + end + endgenerate + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) cp_i0_completed_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[cp_i0_completed_offset:cp_i0_completed_offset + `THREADS - 1]), + .scout(sov[cp_i0_completed_offset:cp_i0_completed_offset + `THREADS - 1]), + .din(iu_lq_i0_completed), + .dout(cp_i0_completed_q) + ); + generate + begin : xhdl51 + genvar i; + for (i = 0; i <= `THREADS-1; i = i + 1) + begin : cp_i0_completed_itag_latch_gen + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) cp_i0_completed_itag_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(iu_lq_i0_completed[i]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[cp_i0_completed_itag_offset + `ITAG_SIZE_ENC * i:cp_i0_completed_itag_offset + `ITAG_SIZE_ENC * (i + 1) - 1]), + .scout(sov[cp_i0_completed_itag_offset + `ITAG_SIZE_ENC * i:cp_i0_completed_itag_offset + `ITAG_SIZE_ENC * (i + 1) - 1]), + .din(iu_lq_i0_completed_itag_int[i]), + .dout(cp_i0_completed_itag_q[i]) + ); + end + end + endgenerate + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) cp_i1_completed_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[cp_i1_completed_offset:cp_i1_completed_offset + `THREADS - 1]), + .scout(sov[cp_i1_completed_offset:cp_i1_completed_offset + `THREADS - 1]), + .din(iu_lq_i1_completed), + .dout(cp_i1_completed_q) + ); + generate + begin : xhdl52 + genvar i; + for (i = 0; i <= `THREADS-1; i = i + 1) + begin : cp_i1_completed_itag_latch_gen + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) cp_I1_completed_itag_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(iu_lq_i1_completed[i]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[cp_i1_completed_itag_offset + `ITAG_SIZE_ENC * i:cp_i1_completed_itag_offset + `ITAG_SIZE_ENC * (i + 1) - 1]), + .scout(sov[cp_i1_completed_itag_offset + `ITAG_SIZE_ENC * i:cp_i1_completed_itag_offset + `ITAG_SIZE_ENC * (i + 1) - 1]), + .din(iu_lq_i1_completed_itag_int[i]), + .dout(cp_i1_completed_itag_q[i]) + ); + end + end + endgenerate + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq_cpl_need_hold_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq_cpl_need_hold_offset]), + .scout(sov[stq_cpl_need_hold_offset]), + .din(stq_cpl_need_hold_d), + .dout(stq_cpl_need_hold_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) iu_lq_icbi_complete_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[iu_lq_icbi_complete_offset:iu_lq_icbi_complete_offset + `THREADS - 1]), + .scout(sov[iu_lq_icbi_complete_offset:iu_lq_icbi_complete_offset + `THREADS - 1]), + .din(iu_lq_icbi_complete), + .dout(iu_lq_icbi_complete_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) iu_icbi_ack_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[iu_icbi_ack_offset:iu_icbi_ack_offset + `THREADS - 1]), + .scout(sov[iu_icbi_ack_offset:iu_icbi_ack_offset + `THREADS - 1]), + .din(iu_icbi_ack_d), + .dout(iu_icbi_ack_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) l2_icbi_ack_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[l2_icbi_ack_offset:l2_icbi_ack_offset + `THREADS - 1]), + .scout(sov[l2_icbi_ack_offset:l2_icbi_ack_offset + `THREADS - 1]), + .din(l2_icbi_ack_d), + .dout(l2_icbi_ack_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rv1_binv_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rv1_binv_val_offset]), + .scout(sov[rv1_binv_val_offset]), + .din(rv1_binv_val_d), + .dout(rv1_binv_val_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_binv_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_binv_val_offset]), + .scout(sov[ex0_binv_val_offset]), + .din(ex0_binv_val_d), + .dout(ex0_binv_val_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_binv_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_binv_val_offset]), + .scout(sov[ex1_binv_val_offset]), + .din(ex1_binv_val_d), + .dout(ex1_binv_val_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_binv_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_binv_val_offset]), + .scout(sov[ex2_binv_val_offset]), + .din(ex2_binv_val_d), + .dout(ex2_binv_val_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_binv_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_binv_val_offset]), + .scout(sov[ex3_binv_val_offset]), + .din(ex3_binv_val_d), + .dout(ex3_binv_val_q) + ); + + tri_rlmreg_p #(.WIDTH(((63-`CL_SIZE)-(64-(`DC_SIZE-3))+1)), .INIT(0), .NEEDS_SRESET(1)) rv1_binv_addr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(l2_back_inv_val), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rv1_binv_addr_offset:rv1_binv_addr_offset + ((63-`CL_SIZE)-(64-(`DC_SIZE-3))+1) - 1]), + .scout(sov[rv1_binv_addr_offset:rv1_binv_addr_offset + ((63-`CL_SIZE)-(64-(`DC_SIZE-3))+1) - 1]), + .din(rv1_binv_addr_d), + .dout(rv1_binv_addr_q) + ); + + tri_rlmreg_p #(.WIDTH(((63-`CL_SIZE)-(64-(`DC_SIZE-3))+1)), .INIT(0), .NEEDS_SRESET(1)) ex0_binv_addr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rv1_binv_val_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_binv_addr_offset:ex0_binv_addr_offset + ((63-`CL_SIZE)-(64-(`DC_SIZE-3))+1) - 1]), + .scout(sov[ex0_binv_addr_offset:ex0_binv_addr_offset + ((63-`CL_SIZE)-(64-(`DC_SIZE-3))+1) - 1]), + .din(ex0_binv_addr_d), + .dout(ex0_binv_addr_q) + ); + + tri_rlmreg_p #(.WIDTH(((63-`CL_SIZE)-(64-(`DC_SIZE-3))+1)), .INIT(0), .NEEDS_SRESET(1)) ex1_binv_addr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex0_binv_val_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_binv_addr_offset:ex1_binv_addr_offset + ((63-`CL_SIZE)-(64-(`DC_SIZE-3))+1) - 1]), + .scout(sov[ex1_binv_addr_offset:ex1_binv_addr_offset + ((63-`CL_SIZE)-(64-(`DC_SIZE-3))+1) - 1]), + .din(ex1_binv_addr_d), + .dout(ex1_binv_addr_q) + ); + + tri_rlmreg_p #(.WIDTH(((63-`CL_SIZE)-(64-(`DC_SIZE-3))+1)), .INIT(0), .NEEDS_SRESET(1)) ex2_binv_addr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_binv_val_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_binv_addr_offset:ex2_binv_addr_offset + ((63-`CL_SIZE)-(64-(`DC_SIZE-3))+1) - 1]), + .scout(sov[ex2_binv_addr_offset:ex2_binv_addr_offset + ((63-`CL_SIZE)-(64-(`DC_SIZE-3))+1) - 1]), + .din(ex2_binv_addr_d), + .dout(ex2_binv_addr_q) + ); + + tri_rlmreg_p #(.WIDTH(((63-`CL_SIZE)-(64-(`DC_SIZE-3))+1)), .INIT(0), .NEEDS_SRESET(1)) ex3_binv_addr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_binv_val_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_binv_addr_offset:ex3_binv_addr_offset + ((63-`CL_SIZE)-(64-(`DC_SIZE-3))+1) - 1]), + .scout(sov[ex3_binv_addr_offset:ex3_binv_addr_offset + ((63-`CL_SIZE)-(64-(`DC_SIZE-3))+1) - 1]), + .din(ex3_binv_addr_d), + .dout(ex3_binv_addr_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_binv_blk_cclass_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(stq_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq2_binv_blk_cclass_offset]), + .scout(sov[stq2_binv_blk_cclass_offset]), + .din(stq2_binv_blk_cclass_d), + .dout(stq2_binv_blk_cclass_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_ici_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(stq1_cmmt_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq2_ici_val_offset]), + .scout(sov[stq2_ici_val_offset]), + .din(stq2_ici_val_d), + .dout(stq2_ici_val_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_xucr0_cul_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq4_xucr0_cul_offset]), + .scout(sov[stq4_xucr0_cul_offset]), + .din(stq4_xucr0_cul_d), + .dout(stq4_xucr0_cul_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_reject_dci_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq2_reject_dci_offset]), + .scout(sov[stq2_reject_dci_offset]), + .din(stq2_reject_dci_d), + .dout(stq2_reject_dci_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq3_cmmt_reject_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq3_cmmt_reject_offset]), + .scout(sov[stq3_cmmt_reject_offset]), + .din(stq3_cmmt_reject_d), + .dout(stq3_cmmt_reject_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_dci_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(stq1_cmmt_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq2_dci_val_offset]), + .scout(sov[stq2_dci_val_offset]), + .din(stq2_dci_val_d), + .dout(stq2_dci_val_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq3_cmmt_dci_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq3_cmmt_dci_val_offset]), + .scout(sov[stq3_cmmt_dci_val_offset]), + .din(stq3_cmmt_dci_val_d), + .dout(stq3_cmmt_dci_val_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_cmmt_dci_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq4_cmmt_dci_val_offset]), + .scout(sov[stq4_cmmt_dci_val_offset]), + .din(stq4_cmmt_dci_val_d), + .dout(stq4_cmmt_dci_val_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq5_cmmt_dci_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq5_cmmt_dci_val_offset]), + .scout(sov[stq5_cmmt_dci_val_offset]), + .din(stq5_cmmt_dci_val_d), + .dout(stq5_cmmt_dci_val_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_cmmt_flushed_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq2_cmmt_flushed_offset]), + .scout(sov[stq2_cmmt_flushed_offset]), + .din(stq1_cmmt_flushed), + .dout(stq2_cmmt_flushed_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq3_cmmt_flushed_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq3_cmmt_flushed_offset]), + .scout(sov[stq3_cmmt_flushed_offset]), + .din(stq2_cmmt_flushed_q), + .dout(stq3_cmmt_flushed_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_cmmt_flushed_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq4_cmmt_flushed_offset]), + .scout(sov[stq4_cmmt_flushed_offset]), + .din(stq3_cmmt_flushed_q), + .dout(stq4_cmmt_flushed_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq5_cmmt_flushed_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq5_cmmt_flushed_offset]), + .scout(sov[stq5_cmmt_flushed_offset]), + .din(stq4_cmmt_flushed_q), + .dout(stq5_cmmt_flushed_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq6_cmmt_flushed_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq6_cmmt_flushed_offset]), + .scout(sov[stq6_cmmt_flushed_offset]), + .din(stq5_cmmt_flushed_q), + .dout(stq6_cmmt_flushed_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq7_cmmt_flushed_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq7_cmmt_flushed_offset]), + .scout(sov[stq7_cmmt_flushed_offset]), + .din(stq6_cmmt_flushed_q), + .dout(stq7_cmmt_flushed_q) + ); + + tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(2 ** (`STQ_ENTRIES - 1)), .NEEDS_SRESET(1)) stq1_cmmt_ptr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(stq1_cmmt_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq1_cmmt_ptr_offset:stq1_cmmt_ptr_offset + `STQ_ENTRIES - 1]), + .scout(sov[stq1_cmmt_ptr_offset:stq1_cmmt_ptr_offset + `STQ_ENTRIES - 1]), + .din(stq1_cmmt_ptr_d), + .dout(stq1_cmmt_ptr_q) + ); + + tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stq2_cmmt_ptr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(stq1_cmmt_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq2_cmmt_ptr_offset:stq2_cmmt_ptr_offset + `STQ_ENTRIES - 1]), + .scout(sov[stq2_cmmt_ptr_offset:stq2_cmmt_ptr_offset + `STQ_ENTRIES - 1]), + .din(stq2_cmmt_ptr_d), + .dout(stq2_cmmt_ptr_q) + ); + + tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stq3_cmmt_ptr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(stq2_cmmt_val_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq3_cmmt_ptr_offset:stq3_cmmt_ptr_offset + `STQ_ENTRIES - 1]), + .scout(sov[stq3_cmmt_ptr_offset:stq3_cmmt_ptr_offset + `STQ_ENTRIES - 1]), + .din(stq3_cmmt_ptr_d), + .dout(stq3_cmmt_ptr_q) + ); + + tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stq4_cmmt_ptr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(stq3_cmmt_val_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq4_cmmt_ptr_offset:stq4_cmmt_ptr_offset + `STQ_ENTRIES - 1]), + .scout(sov[stq4_cmmt_ptr_offset:stq4_cmmt_ptr_offset + `STQ_ENTRIES - 1]), + .din(stq4_cmmt_ptr_d), + .dout(stq4_cmmt_ptr_q) + ); + + tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stq5_cmmt_ptr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(stq4_cmmt_val_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq5_cmmt_ptr_offset:stq5_cmmt_ptr_offset + `STQ_ENTRIES - 1]), + .scout(sov[stq5_cmmt_ptr_offset:stq5_cmmt_ptr_offset + `STQ_ENTRIES - 1]), + .din(stq5_cmmt_ptr_d), + .dout(stq5_cmmt_ptr_q) + ); + + tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stq6_cmmt_ptr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(stq5_cmmt_val_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq6_cmmt_ptr_offset:stq6_cmmt_ptr_offset + `STQ_ENTRIES - 1]), + .scout(sov[stq6_cmmt_ptr_offset:stq6_cmmt_ptr_offset + `STQ_ENTRIES - 1]), + .din(stq6_cmmt_ptr_d), + .dout(stq6_cmmt_ptr_q) + ); + + tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stq7_cmmt_ptr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(stq6_cmmt_val_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq7_cmmt_ptr_offset:stq7_cmmt_ptr_offset + `STQ_ENTRIES - 1]), + .scout(sov[stq7_cmmt_ptr_offset:stq7_cmmt_ptr_offset + `STQ_ENTRIES - 1]), + .din(stq7_cmmt_ptr_d), + .dout(stq7_cmmt_ptr_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_cmmt_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(stq_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq2_cmmt_val_offset]), + .scout(sov[stq2_cmmt_val_offset]), + .din(stq1_cmmt_val), + .dout(stq2_cmmt_val_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq3_cmmt_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(stq_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq3_cmmt_val_offset]), + .scout(sov[stq3_cmmt_val_offset]), + .din(stq2_cmmt_val), + .dout(stq3_cmmt_val_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_cmmt_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(stq_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq4_cmmt_val_offset]), + .scout(sov[stq4_cmmt_val_offset]), + .din(stq3_cmmt_val_q), + .dout(stq4_cmmt_val_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq5_cmmt_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(stq_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq5_cmmt_val_offset]), + .scout(sov[stq5_cmmt_val_offset]), + .din(stq4_cmmt_val_q), + .dout(stq5_cmmt_val_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq6_cmmt_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(stq_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq6_cmmt_val_offset]), + .scout(sov[stq6_cmmt_val_offset]), + .din(stq5_cmmt_val_q), + .dout(stq6_cmmt_val_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq7_cmmt_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(stq_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq7_cmmt_val_offset]), + .scout(sov[stq7_cmmt_val_offset]), + .din(stq6_cmmt_val_q), + .dout(stq7_cmmt_val_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ext_ack_queue_v_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ext_ack_queue_v_offset:ext_ack_queue_v_offset + `THREADS - 1]), + .scout(sov[ext_ack_queue_v_offset:ext_ack_queue_v_offset + `THREADS - 1]), + .din(ext_ack_queue_v_d), + .dout(ext_ack_queue_v_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ext_ack_queue_sync_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ext_ack_queue_sync_offset:ext_ack_queue_sync_offset + `THREADS - 1]), + .scout(sov[ext_ack_queue_sync_offset:ext_ack_queue_sync_offset + `THREADS - 1]), + .din(ext_ack_queue_sync_d), + .dout(ext_ack_queue_sync_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ext_ack_queue_stcx_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ext_ack_queue_stcx_offset:ext_ack_queue_stcx_offset + `THREADS - 1]), + .scout(sov[ext_ack_queue_stcx_offset:ext_ack_queue_stcx_offset + `THREADS - 1]), + .din(ext_ack_queue_stcx_d), + .dout(ext_ack_queue_stcx_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ext_ack_queue_icswxr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ext_ack_queue_icswxr_offset:ext_ack_queue_icswxr_offset + `THREADS - 1]), + .scout(sov[ext_ack_queue_icswxr_offset:ext_ack_queue_icswxr_offset + `THREADS - 1]), + .din(ext_ack_queue_icswxr_d), + .dout(ext_ack_queue_icswxr_q) + ); + + + generate + begin : xhdl53 + genvar i; + for (i = 0; i <= `THREADS-1; i = i + 1) + begin : ext_ack_queue_itag_latch_gen + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ext_ack_queue_itag_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ext_ack_queue_itag_offset + `ITAG_SIZE_ENC * i:ext_ack_queue_itag_offset + `ITAG_SIZE_ENC * (i + 1) - 1]), + .scout(sov[ext_ack_queue_itag_offset + `ITAG_SIZE_ENC * i:ext_ack_queue_itag_offset + `ITAG_SIZE_ENC * (i + 1) - 1]), + .din(ext_ack_queue_itag_d[i]), + .dout(ext_ack_queue_itag_q[i]) + ); + end + end + endgenerate + generate + begin : xhdl54 + genvar i; + for (i = 0; i <= `THREADS-1; i = i + 1) + begin : ext_ack_queue_cr_wa_latch_gen + + tri_rlmreg_p #(.WIDTH(`CR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) ext_ack_queue_cr_wa_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ext_ack_queue_cr_wa_offset + (`CR_POOL_ENC+`THREADS_POOL_ENC) * i:ext_ack_queue_cr_wa_offset + (`CR_POOL_ENC+`THREADS_POOL_ENC) * (i + 1) - 1]), + .scout(sov[ext_ack_queue_cr_wa_offset + (`CR_POOL_ENC+`THREADS_POOL_ENC) * i:ext_ack_queue_cr_wa_offset + (`CR_POOL_ENC+`THREADS_POOL_ENC) * (i + 1) - 1]), + .din(ext_ack_queue_cr_wa_d[i]), + .dout(ext_ack_queue_cr_wa_q[i]) + ); + end + end + endgenerate + generate + begin : xhdl55 + genvar i; + for (i = 0; i <= `THREADS-1; i = i + 1) + begin : ext_ack_queue_dacrw_det_latch_gen + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ext_ack_queue_dacrw_det_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ext_ack_queue_dacrw_det_offset + 4 * i:ext_ack_queue_dacrw_det_offset + 4 * (i + 1) - 1]), + .scout(sov[ext_ack_queue_dacrw_det_offset + 4 * i:ext_ack_queue_dacrw_det_offset + 4 * (i + 1) - 1]), + .din(ext_ack_queue_dacrw_det_d[i]), + .dout(ext_ack_queue_dacrw_det_q[i]) + ); + end + end + endgenerate + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ext_ack_queue_dacrw_rpt_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ext_ack_queue_dacrw_rpt_offset:ext_ack_queue_dacrw_rpt_offset + `THREADS - 1]), + .scout(sov[ext_ack_queue_dacrw_rpt_offset:ext_ack_queue_dacrw_rpt_offset + `THREADS - 1]), + .din(ext_ack_queue_dacrw_rpt_d), + .dout(ext_ack_queue_dacrw_rpt_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_mftgpr_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(stq_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq2_mftgpr_val_offset]), + .scout(sov[stq2_mftgpr_val_offset]), + .din(stq2_mftgpr_val_d), + .dout(stq2_mftgpr_val_q) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(6), .NEEDS_SRESET(1)) stq2_rtry_cnt_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(stq2_rtry_cnt_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq2_rtry_cnt_offset:stq2_rtry_cnt_offset + 3 - 1]), + .scout(sov[stq2_rtry_cnt_offset:stq2_rtry_cnt_offset + 3 - 1]), + .din(stq2_rtry_cnt_d), + .dout(stq2_rtry_cnt_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_stq_restart_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_stq_restart_offset]), + .scout(sov[ex5_stq_restart_offset]), + .din(ex5_stq_restart_d), + .dout(ex5_stq_restart_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_stq_restart_miss_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_stq_restart_miss_offset]), + .scout(sov[ex5_stq_restart_miss_offset]), + .din(ex5_stq_restart_miss_d), + .dout(ex5_stq_restart_miss_q) + ); + + tri_rlmreg_p #(.WIDTH((`STQ_FWD_ENTRIES-1)), .INIT(0), .NEEDS_SRESET(1)) stq_fwd_pri_mask_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(stq_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq_fwd_pri_mask_offset:stq_fwd_pri_mask_offset + (`STQ_FWD_ENTRIES-1) - 1]), + .scout(sov[stq_fwd_pri_mask_offset:stq_fwd_pri_mask_offset + (`STQ_FWD_ENTRIES-1) - 1]), + .din(stq_fwd_pri_mask_d), + .dout(stq_fwd_pri_mask_q[0:`STQ_FWD_ENTRIES - 2]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_fwd_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_fwd_val_offset]), + .scout(sov[ex5_fwd_val_offset]), + .din(ex5_fwd_val_d), + .dout(ex5_fwd_val_q) + ); + + tri_rlmreg_p #(.WIDTH((`STQ_DATA_SIZE)), .INIT(0), .NEEDS_SRESET(1)) ex5_fwd_data_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex4_ldreq_valid), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_fwd_data_offset:ex5_fwd_data_offset + `STQ_DATA_SIZE - 1]), + .scout(sov[ex5_fwd_data_offset:ex5_fwd_data_offset + `STQ_DATA_SIZE - 1]), + .din(ex5_fwd_data_d), + .dout(ex5_fwd_data_q) + ); + + tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex4_set_stq_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_set_stq_offset:ex4_set_stq_offset + `STQ_ENTRIES - 1]), + .scout(sov[ex4_set_stq_offset:ex4_set_stq_offset + `STQ_ENTRIES - 1]), + .din(ex3_set_stq), + .dout(ex4_set_stq_q[0:`STQ_ENTRIES - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex5_set_stq_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_set_stq_offset:ex5_set_stq_offset + `STQ_ENTRIES - 1]), + .scout(sov[ex5_set_stq_offset:ex5_set_stq_offset + `STQ_ENTRIES - 1]), + .din(ex4_set_stq[0:`STQ_ENTRIES - 1]), + .dout(ex5_set_stq_q[0:`STQ_ENTRIES - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex4_ldreq_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_ldreq_val_offset:ex4_ldreq_val_offset + `THREADS - 1]), + .scout(sov[ex4_ldreq_val_offset:ex4_ldreq_val_offset + `THREADS - 1]), + .din(ex3_ldreq_val), + .dout(ex4_ldreq_val_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_pfetch_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_pfetch_val_offset]), + .scout(sov[ex4_pfetch_val_offset]), + .din(ex3_pfetch_val), + .dout(ex4_pfetch_val_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex3_streq_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_streq_val_offset:ex3_streq_val_offset + `THREADS - 1]), + .scout(sov[ex3_streq_val_offset:ex3_streq_val_offset + `THREADS - 1]), + .din(ex2_streq_val), + .dout(ex3_streq_val_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex5_streq_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_streq_val_offset:ex5_streq_val_offset + `THREADS - 1]), + .scout(sov[ex5_streq_val_offset:ex5_streq_val_offset + `THREADS - 1]), + .din(ex4_streq_val), + .dout(ex5_streq_val_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex4_wchkall_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_wchkall_val_offset:ex4_wchkall_val_offset + `THREADS - 1]), + .scout(sov[ex4_wchkall_val_offset:ex4_wchkall_val_offset + `THREADS - 1]), + .din(ex3_wchkall_val), + .dout(ex4_wchkall_val_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) hwsync_ack_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[hwsync_ack_offset:hwsync_ack_offset + `THREADS - 1]), + .scout(sov[hwsync_ack_offset:hwsync_ack_offset + `THREADS - 1]), + .din(hwsync_ack), + .dout(hwsync_ack_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) lwsync_ack_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lwsync_ack_offset:lwsync_ack_offset + `THREADS - 1]), + .scout(sov[lwsync_ack_offset:lwsync_ack_offset + `THREADS - 1]), + .din(lwsync_ack), + .dout(lwsync_ack_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) icswxr_ack_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[icswxr_ack_offset]), + .scout(sov[icswxr_ack_offset]), + .din(icswxr_ack), + .dout(icswxr_ack_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) icswxr_ack_dly1_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[icswxr_ack_dly1_offset]), + .scout(sov[icswxr_ack_dly1_offset]), + .din(icswxr_ack_q), + .dout(icswxr_ack_dly1_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) local_instr_ack_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[local_instr_ack_offset:local_instr_ack_offset + `THREADS - 1]), + .scout(sov[local_instr_ack_offset:local_instr_ack_offset + `THREADS - 1]), + .din(local_instr_ack), + .dout(local_instr_ack_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) resv_ack_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[resv_ack_offset:resv_ack_offset + `THREADS - 1]), + .scout(sov[resv_ack_offset:resv_ack_offset + `THREADS - 1]), + .din(resv_ack_d), + .dout(resv_ack_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) stcx_pass_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stcx_pass_offset:stcx_pass_offset + `THREADS - 1]), + .scout(sov[stcx_pass_offset:stcx_pass_offset + `THREADS - 1]), + .din(stcx_pass), + .dout(stcx_pass_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) icbi_ack_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[icbi_ack_offset:icbi_ack_offset + `THREADS - 1]), + .scout(sov[icbi_ack_offset:icbi_ack_offset + `THREADS - 1]), + .din(icbi_ack), + .dout(icbi_ack_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) icbi_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[icbi_val_offset:icbi_val_offset + `THREADS - 1]), + .scout(sov[icbi_val_offset:icbi_val_offset + `THREADS - 1]), + .din(icbi_val_d), + .dout(icbi_val_q) + ); + + tri_rlmreg_p #(.WIDTH((57-RI+1)), .INIT(0), .NEEDS_SRESET(1)) icbi_addr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(stq2_cmmt_val_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[icbi_addr_offset:icbi_addr_offset + (57-RI+1) - 1]), + .scout(sov[icbi_addr_offset:icbi_addr_offset + (57-RI+1) - 1]), + .din(icbi_addr_d), + .dout(icbi_addr_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ici_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ici_val_offset]), + .scout(sov[ici_val_offset]), + .din(ici_val_d), + .dout(ici_val_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) credit_free_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[credit_free_offset:credit_free_offset + `THREADS - 1]), + .scout(sov[credit_free_offset:credit_free_offset + `THREADS - 1]), + .din(credit_free_d), + .dout(credit_free_q) + ); + + tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex4_fwd_agecmp_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_fwd_agecmp_offset:ex4_fwd_agecmp_offset + `STQ_ENTRIES - 1]), + .scout(sov[ex4_fwd_agecmp_offset:ex4_fwd_agecmp_offset + `STQ_ENTRIES - 1]), + .din(ex4_fwd_agecmp_d), + .dout(ex4_fwd_agecmp_q) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex3_req_itag_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_req_itag_offset:ex3_req_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[ex3_req_itag_offset:ex3_req_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(ctl_lsq_ex2_itag), + .dout(ex3_req_itag_q) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex4_req_itag_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_req_itag_offset:ex4_req_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[ex4_req_itag_offset:ex4_req_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(ex3_req_itag_q), + .dout(ex4_req_itag_q) + ); + + tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) ex4_req_byte_en_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_req_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_req_byte_en_offset:ex4_req_byte_en_offset + 16 - 1]), + .scout(sov[ex4_req_byte_en_offset:ex4_req_byte_en_offset + 16 - 1]), + .din(ctl_lsq_ex3_byte_en), + .dout(ex4_req_byte_en_q) + ); + + tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) ex4_req_p_addr_l_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_req_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_req_p_addr_l_offset:ex4_req_p_addr_l_offset + 6 - 1]), + .scout(sov[ex4_req_p_addr_l_offset:ex4_req_p_addr_l_offset + 6 - 1]), + .din(ctl_lsq_ex3_p_addr), + .dout(ex4_req_p_addr_l_q) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex4_req_opsize_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_req_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_req_opsize_offset:ex4_req_opsize_offset + 3 - 1]), + .scout(sov[ex4_req_opsize_offset:ex4_req_opsize_offset + 3 - 1]), + .din(ctl_lsq_ex3_opsize), + .dout(ex4_req_opsize_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_req_algebraic_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_req_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_req_algebraic_offset]), + .scout(sov[ex4_req_algebraic_offset]), + .din(ctl_lsq_ex3_algebraic), + .dout(ex4_req_algebraic_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex3_req_thrd_id_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_req_thrd_id_offset:ex3_req_thrd_id_offset + `THREADS - 1]), + .scout(sov[ex3_req_thrd_id_offset:ex3_req_thrd_id_offset + `THREADS - 1]), + .din(ctl_lsq_ex2_thrd_id), + .dout(ex3_req_thrd_id_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex4_req_thrd_id_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_req_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_req_thrd_id_offset:ex4_req_thrd_id_offset + `THREADS - 1]), + .scout(sov[ex4_req_thrd_id_offset:ex4_req_thrd_id_offset + `THREADS - 1]), + .din(ex3_req_thrd_id_q), + .dout(ex4_req_thrd_id_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex5_req_thrd_id_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_req_thrd_id_offset:ex5_req_thrd_id_offset + `THREADS - 1]), + .scout(sov[ex5_req_thrd_id_offset:ex5_req_thrd_id_offset + `THREADS - 1]), + .din(ex4_req_thrd_id_q), + .dout(ex5_req_thrd_id_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) thrd_held_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[thrd_held_offset:thrd_held_offset + `THREADS - 1]), + .scout(sov[thrd_held_offset:thrd_held_offset + `THREADS - 1]), + .din(thrd_held_d), + .dout(thrd_held_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) rv0_cr_hole_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rv0_cr_hole_offset:rv0_cr_hole_offset + `THREADS - 1]), + .scout(sov[rv0_cr_hole_offset:rv0_cr_hole_offset + `THREADS - 1]), + .din(rv0_cr_hole_d), + .dout(rv0_cr_hole_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) rv1_cr_hole_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rv1_cr_hole_offset:rv1_cr_hole_offset + `THREADS - 1]), + .scout(sov[rv1_cr_hole_offset:rv1_cr_hole_offset + `THREADS - 1]), + .din(rv1_cr_hole_d), + .dout(rv1_cr_hole_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex0_cr_hole_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_cr_hole_offset:ex0_cr_hole_offset + `THREADS - 1]), + .scout(sov[ex0_cr_hole_offset:ex0_cr_hole_offset + `THREADS - 1]), + .din(ex0_cr_hole_d), + .dout(ex0_cr_hole_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) cr_ack_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[cr_ack_offset:cr_ack_offset + `THREADS - 1]), + .scout(sov[cr_ack_offset:cr_ack_offset + `THREADS - 1]), + .din(cr_ack_d), + .dout(cr_ack_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) sync_ack_save_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[sync_ack_save_offset]), + .scout(sov[sync_ack_save_offset]), + .din(sync_ack_save_d), + .dout(sync_ack_save_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cr_we_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[cr_we_offset]), + .scout(sov[cr_we_offset]), + .din(cr_we_d), + .dout(cr_we_q) + ); + + tri_rlmreg_p #(.WIDTH((`CR_POOL_ENC+`THREADS_POOL_ENC-1+1)), .INIT(0), .NEEDS_SRESET(1)) cr_wa_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cr_we_d), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[cr_wa_offset:cr_wa_offset + (`CR_POOL_ENC+`THREADS_POOL_ENC-1+1) - 1]), + .scout(sov[cr_wa_offset:cr_wa_offset + (`CR_POOL_ENC+`THREADS_POOL_ENC-1+1) - 1]), + .din(cr_wa_d), + .dout(cr_wa_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) cr_wd_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(cr_we_d), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[cr_wd_offset:cr_wd_offset + 4 - 1]), + .scout(sov[cr_wd_offset:cr_wd_offset + 4 - 1]), + .din(cr_wd_d), + .dout(cr_wd_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) stcx_thrd_fail_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stcx_thrd_fail_offset:stcx_thrd_fail_offset + `THREADS - 1]), + .scout(sov[stcx_thrd_fail_offset:stcx_thrd_fail_offset + `THREADS - 1]), + .din(stcx_thrd_fail_d), + .dout(stcx_thrd_fail_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) icswxr_thrd_busy_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[icswxr_thrd_busy_offset:icswxr_thrd_busy_offset + `THREADS - 1]), + .scout(sov[icswxr_thrd_busy_offset:icswxr_thrd_busy_offset + `THREADS - 1]), + .din(icswxr_thrd_busy_d), + .dout(icswxr_thrd_busy_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) icswxr_thrd_nbusy_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[icswxr_thrd_nbusy_offset:icswxr_thrd_nbusy_offset + `THREADS - 1]), + .scout(sov[icswxr_thrd_nbusy_offset:icswxr_thrd_nbusy_offset + `THREADS - 1]), + .din(icswxr_thrd_nbusy_d), + .dout(icswxr_thrd_nbusy_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq3_cmmt_attmpt_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq3_cmmt_attmpt_offset]), + .scout(sov[stq3_cmmt_attmpt_offset]), + .din(stq3_cmmt_attmpt_d), + .dout(stq3_cmmt_attmpt_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq_need_hole_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq_need_hole_offset]), + .scout(sov[stq_need_hole_offset]), + .din(stq_need_hole_d), + .dout(stq_need_hole_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) any_ack_hold_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[any_ack_hold_offset:any_ack_hold_offset + `THREADS - 1]), + .scout(sov[any_ack_hold_offset:any_ack_hold_offset + `THREADS - 1]), + .din(any_ack_hold_d), + .dout(any_ack_hold_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) any_ack_val_ok_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[any_ack_val_ok_offset:any_ack_val_ok_offset + `THREADS - 1]), + .scout(sov[any_ack_val_ok_offset:any_ack_val_ok_offset + `THREADS - 1]), + .din(any_ack_val_ok_d), + .dout(any_ack_val_ok_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) arb_release_itag_vld_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[arb_release_itag_vld_offset:arb_release_itag_vld_offset + `THREADS - 1]), + .scout(sov[arb_release_itag_vld_offset:arb_release_itag_vld_offset + `THREADS - 1]), + .din(arb_release_itag_vld_d), + .dout(arb_release_itag_vld_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr0_cls_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_xucr0_cls_offset]), + .scout(sov[spr_xucr0_cls_offset]), + .din(spr_xucr0_cls_d), + .dout(spr_xucr0_cls_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_iucr0_icbi_ack_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_iucr0_icbi_ack_offset]), + .scout(sov[spr_iucr0_icbi_ack_offset]), + .din(spr_iucr0_icbi_ack_d), + .dout(spr_iucr0_icbi_ack_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_lsucr0_dfwd_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_lsucr0_dfwd_offset]), + .scout(sov[spr_lsucr0_dfwd_offset]), + .din(spr_lsucr0_dfwd_d), + .dout(spr_lsucr0_dfwd_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_thrd_match_restart_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_thrd_match_restart_offset]), + .scout(sov[ex5_thrd_match_restart_offset]), + .din(ex5_thrd_match_restart_d), + .dout(ex5_thrd_match_restart_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_thrd_match_restart_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_thrd_match_restart_offset]), + .scout(sov[ex6_thrd_match_restart_offset]), + .din(ex6_thrd_match_restart_d), + .dout(ex6_thrd_match_restart_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_thrd_nomatch_restart_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_thrd_nomatch_restart_offset]), + .scout(sov[ex5_thrd_nomatch_restart_offset]), + .din(ex5_thrd_nomatch_restart_d), + .dout(ex5_thrd_nomatch_restart_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_thrd_nomatch_restart_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_thrd_nomatch_restart_offset]), + .scout(sov[ex6_thrd_nomatch_restart_offset]), + .din(ex6_thrd_nomatch_restart_d), + .dout(ex6_thrd_nomatch_restart_q) + ); + + tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex5_older_ldmiss_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_older_ldmiss_offset:ex5_older_ldmiss_offset + `STQ_ENTRIES - 1]), + .scout(sov[ex5_older_ldmiss_offset:ex5_older_ldmiss_offset + `STQ_ENTRIES - 1]), + .din(ex5_older_ldmiss_d), + .dout(ex5_older_ldmiss_q[0:`STQ_ENTRIES - 1]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_fxu1_illeg_lswx_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_fxu1_val), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_fxu1_illeg_lswx_offset]), + .scout(sov[ex4_fxu1_illeg_lswx_offset]), + .din(ex4_fxu1_illeg_lswx_d), + .dout(ex4_fxu1_illeg_lswx_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_fxu1_strg_noop_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_fxu1_val), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_fxu1_strg_noop_offset]), + .scout(sov[ex4_fxu1_strg_noop_offset]), + .din(ex4_fxu1_strg_noop_d), + .dout(ex4_fxu1_strg_noop_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex3_fxu1_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_fxu1_val_offset:ex3_fxu1_val_offset + `THREADS - 1]), + .scout(sov[ex3_fxu1_val_offset:ex3_fxu1_val_offset + `THREADS - 1]), + .din(ex3_fxu1_val_d), + .dout(ex3_fxu1_val_q) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex3_fxu1_itag_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_fxu1_val), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_fxu1_itag_offset:ex3_fxu1_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[ex3_fxu1_itag_offset:ex3_fxu1_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(ex3_fxu1_itag_d), + .dout(ex3_fxu1_itag_q) + ); + + tri_rlmreg_p #(.WIDTH((((2**`GPR_WIDTH_ENC)/8)-1-0+1)), .INIT(0), .NEEDS_SRESET(1)) ex3_fxu1_dvc1_cmp_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_fxu1_val), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_fxu1_dvc1_cmp_offset:ex3_fxu1_dvc1_cmp_offset + (((2**`GPR_WIDTH_ENC)/8)-1-0+1) - 1]), + .scout(sov[ex3_fxu1_dvc1_cmp_offset:ex3_fxu1_dvc1_cmp_offset + (((2**`GPR_WIDTH_ENC)/8)-1-0+1) - 1]), + .din(ex3_fxu1_dvc1_cmp_d), + .dout(ex3_fxu1_dvc1_cmp_q) + ); + + tri_rlmreg_p #(.WIDTH((((2**`GPR_WIDTH_ENC)/8)-1-0+1)), .INIT(0), .NEEDS_SRESET(1)) ex3_fxu1_dvc2_cmp_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_fxu1_val), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_fxu1_dvc2_cmp_offset:ex3_fxu1_dvc2_cmp_offset + (((2**`GPR_WIDTH_ENC)/8)-1-0+1) - 1]), + .scout(sov[ex3_fxu1_dvc2_cmp_offset:ex3_fxu1_dvc2_cmp_offset + (((2**`GPR_WIDTH_ENC)/8)-1-0+1) - 1]), + .din(ex3_fxu1_dvc2_cmp_d), + .dout(ex3_fxu1_dvc2_cmp_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex4_fxu1_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_fxu1_val_offset:ex4_fxu1_val_offset + `THREADS - 1]), + .scout(sov[ex4_fxu1_val_offset:ex4_fxu1_val_offset + `THREADS - 1]), + .din(ex4_fxu1_val_d), + .dout(ex4_fxu1_val_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex3_axu_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_axu_val_offset:ex3_axu_val_offset + `THREADS - 1]), + .scout(sov[ex3_axu_val_offset:ex3_axu_val_offset + `THREADS - 1]), + .din(ex3_axu_val_d), + .dout(ex3_axu_val_q) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex3_axu_itag_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_axu_val), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_axu_itag_offset:ex3_axu_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[ex3_axu_itag_offset:ex3_axu_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(ex3_axu_itag_d), + .dout(ex3_axu_itag_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex4_axu_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_axu_val_offset:ex4_axu_val_offset + `THREADS - 1]), + .scout(sov[ex4_axu_val_offset:ex4_axu_val_offset + `THREADS - 1]), + .din(ex4_axu_val_d), + .dout(ex4_axu_val_q) + ); + + tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex5_qHit_set_oth_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_qHit_set_oth_offset:ex5_qHit_set_oth_offset + `STQ_ENTRIES - 1]), + .scout(sov[ex5_qHit_set_oth_offset:ex5_qHit_set_oth_offset + `STQ_ENTRIES - 1]), + .din(ex5_qHit_set_oth_d), + .dout(ex5_qHit_set_oth_q[0:`STQ_ENTRIES - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex5_qHit_set_miss_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_qHit_set_miss_offset:ex5_qHit_set_miss_offset + `STQ_ENTRIES - 1]), + .scout(sov[ex5_qHit_set_miss_offset:ex5_qHit_set_miss_offset + `STQ_ENTRIES - 1]), + .din(ex5_qHit_set_miss_d), + .dout(ex5_qHit_set_miss_q) + ); + + tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex3_nxt_oldest_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_nxt_oldest_offset:ex3_nxt_oldest_offset + `STQ_ENTRIES - 1]), + .scout(sov[ex3_nxt_oldest_offset:ex3_nxt_oldest_offset + `STQ_ENTRIES - 1]), + .din(ex3_nxt_oldest_d), + .dout(ex3_nxt_oldest_q) + ); + + tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stq_tag_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq_tag_val_offset:stq_tag_val_offset + `STQ_ENTRIES - 1]), + .scout(sov[stq_tag_val_offset:stq_tag_val_offset + `STQ_ENTRIES - 1]), + .din(stq_tag_val_d), + .dout(stq_tag_val_q) + ); + generate + begin : xhdl56 + genvar i; + for (i = 0; i <= `STQ_ENTRIES-1; i = i + 1) + begin : stq_tag_ptr_latch_gen + + tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stq_tag_ptr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(stq_tag_act[i]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq_tag_ptr_offset + `STQ_ENTRIES * i:stq_tag_ptr_offset + `STQ_ENTRIES * (i + 1) - 1]), + .scout(sov[stq_tag_ptr_offset + `STQ_ENTRIES * i:stq_tag_ptr_offset + `STQ_ENTRIES * (i + 1) - 1]), + .din(stq_tag_ptr_d[i]), + .dout(stq_tag_ptr_q[i]) + ); + end + end + endgenerate + + tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES_ENC), .INIT(0), .NEEDS_SRESET(1)) stq4_cmmt_tag_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(stq3_cmmt_val_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[stq4_cmmt_tag_offset:stq4_cmmt_tag_offset + `STQ_ENTRIES_ENC - 1]), + .scout(sov[stq4_cmmt_tag_offset:stq4_cmmt_tag_offset + `STQ_ENTRIES_ENC - 1]), + .din(stq4_cmmt_tag_d), + .dout(stq4_cmmt_tag_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) dbg_int_en_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[dbg_int_en_offset:dbg_int_en_offset + `THREADS - 1]), + .scout(sov[dbg_int_en_offset:dbg_int_en_offset + `THREADS - 1]), + .din(dbg_int_en_d), + .dout(dbg_int_en_q) + ); + + + assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in}; + assign scan_out = sov[0]; + +endmodule diff --git a/dev/verilog/work/lq_stq_rot.v b/dev/verilog/work/lq_stq_rot.v new file mode 100755 index 0000000..2940162 --- /dev/null +++ b/dev/verilog/work/lq_stq_rot.v @@ -0,0 +1,103 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// +// Description: XU LSU Store Data Mux +//***************************************************************************** + + +module lq_stq_rot( + rot_sel, + mask, + se_b, + rot_data, + data_rot +); + input [0:3] rot_sel; + input [0:3] mask; + input se_b; + input [0:7] rot_data; + + + output [0:7] data_rot; + + wire [0:5] se1; + wire [0:7] mx1_d0; + wire [0:7] mx1_d1; + wire [0:7] mx1_d2; + wire [0:7] mx1_d3; + wire [0:7] mx1_s0; + wire [0:7] mx1_s1; + wire [0:7] mx1_s2; + wire [0:7] mx1_s3; + wire [0:7] mx1_0_b; + wire [0:7] mx1_1_b; + wire [0:7] mx1; + wire [0:7] mask_exp; + + //-------------------------------------------------------------------------------------- + // Muxing <0,2,4,6 bytes> + //-------------------------------------------------------------------------------------- + assign mx1_s0[0:7] = {8{rot_sel[0]}}; + assign mx1_s1[0:7] = {8{rot_sel[1]}}; + assign mx1_s2[0:7] = {8{rot_sel[2]}}; + assign mx1_s3[0:7] = {8{rot_sel[3]}}; + + // Generate a Mask that is dependent on the size of the operation + assign mask_exp[0] = mask[0]; // 8B + assign mask_exp[1] = mask[0]; // 8B + assign mask_exp[2] = mask[0]; // 8B + assign mask_exp[3] = mask[0]; // 8B + assign mask_exp[4] = mask[0] | mask[1]; // 8B/4B + assign mask_exp[5] = mask[0] | mask[1]; // 8B/4B + assign mask_exp[6] = mask[0] | mask[1] | mask[2]; // 8B/4B/2B + assign mask_exp[7] = mask[0] | mask[1] | mask[2] | mask[3]; // 8B/4B/2B/1B + + assign se1[0:3] = {4{((~se_b))}}; + assign se1[4:5] = {2{(((~se_b)) & mask[2])}}; + + assign mx1_d0 = (rot_data[0:7]) & mask_exp; + assign mx1_d1 = ({2'b0, rot_data[0:5]}) & mask_exp; + assign mx1_d2 = ({4'b0, rot_data[0:3]}) & mask_exp; + assign mx1_d3 = ({6'b0, rot_data[0:1]}) & mask_exp; + + + //assign mx1_0_b[0:7] = (~((mx1_s0[0:7] & mx1_d0[0:7]) | (mx1_s1[0:7] & mx1_d1[0:7]))); + tri_aoi22 #(.WIDTH(8)) mx1_0_b_0 (.y(mx1_0_b[0:7]), .a0(mx1_s0[0:7]), .a1(mx1_d0[0:7]), .b0(mx1_s1[0:7]), .b1(mx1_d1[0:7])); + + //assign mx1_1_b[0:7] = (~((mx1_s2[0:7] & mx1_d2[0:7]) | (mx1_s3[0:7] & mx1_d3[0:7]))); + tri_aoi22 #(.WIDTH(8)) mx1_1_b_0 (.y(mx1_1_b[0:7]), .a0(mx1_s2[0:7]), .a1(mx1_d2[0:7]), .b0(mx1_s3[0:7]), .b1(mx1_d3[0:7])); + + //assign mx1[0:7] = (~(mx1_0_b[0:7] & mx1_1_b[0:7])); + tri_nand2 #(.WIDTH(8)) mx1_0 (.y(mx1[0:7]), .a(mx1_0_b[0:7]), .b(mx1_1_b[0:7])); + + assign data_rot = {(mx1[0:5] | se1[0:5]), mx1[6:7]}; + +endmodule diff --git a/dev/verilog/work/mmq.v b/dev/verilog/work/mmq.v new file mode 100755 index 0000000..a926fdb --- /dev/null +++ b/dev/verilog/work/mmq.v @@ -0,0 +1,4251 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +//******************************************************************** +//* TITLE: Memory Management Unit Top Level +//********************************************************************* + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" +`include "mmu_a2o.vh" +`define ERAT_STATE_WIDTH 4 // this is erat->tlb state width + +(* recursive_synthesis="0" *) +module mmq( + + (* pin_data = "PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) + input [0:`NCLK_WIDTH-1] nclk, + + input tc_ac_ccflush_dc, + input tc_ac_scan_dis_dc_b, + input tc_ac_scan_diag_dc, + input tc_ac_lbist_en_dc, + input pc_mm_gptr_sl_thold_3, + input pc_mm_time_sl_thold_3, + input pc_mm_repr_sl_thold_3, + input pc_mm_abst_sl_thold_3, + input pc_mm_abst_slp_sl_thold_3, + input [0:1] pc_mm_func_sl_thold_3, + input [0:1] pc_mm_func_slp_sl_thold_3, + input pc_mm_cfg_sl_thold_3, + input pc_mm_cfg_slp_sl_thold_3, + input pc_mm_func_nsl_thold_3, + input pc_mm_func_slp_nsl_thold_3, + input pc_mm_ary_nsl_thold_3, + input pc_mm_ary_slp_nsl_thold_3, + input [0:1] pc_mm_sg_3, + input pc_mm_fce_3, + + input [0:`DEBUG_TRACE_WIDTH-1] debug_bus_in, + output [0:`DEBUG_TRACE_WIDTH-1] debug_bus_out, + + // Instruction Trace (HTM) Control Signals: + // 0 - ac_an_coretrace_first_valid + // 1 - ac_an_coretrace_valid + // 2:3 - ac_an_coretrace_type[0:1] + input [0:3] coretrace_ctrls_in, + output [0:3] coretrace_ctrls_out, + + input [0:10] pc_mm_debug_mux1_ctrls, + input pc_mm_trace_bus_enable, + + input [0:2] pc_mm_event_count_mode, + input rp_mm_event_bus_enable_q, + + input [0:`PERF_EVENT_WIDTH*`THREADS-1] mm_event_bus_in, + output [0:`PERF_EVENT_WIDTH*`THREADS-1] mm_event_bus_out, + + input [0:3] pc_mm_abist_dcomp_g6t_2r, + input [0:3] pc_mm_abist_di_0, + input [0:3] pc_mm_abist_di_g6t_2r, + input pc_mm_abist_ena_dc, + input pc_mm_abist_g6t_r_wb, + input pc_mm_abist_g8t1p_renb_0, + input pc_mm_abist_g8t_bw_0, + input pc_mm_abist_g8t_bw_1, + input [0:3] pc_mm_abist_g8t_dcomp, + input pc_mm_abist_g8t_wenb, + input [0:9] pc_mm_abist_raddr_0, + input pc_mm_abist_raw_dc_b, + input [0:9] pc_mm_abist_waddr_0, + input pc_mm_abist_wl128_comp_ena, + input pc_mm_bolt_sl_thold_3, + input pc_mm_bo_enable_3, + input pc_mm_bo_reset, + input pc_mm_bo_unload, + input pc_mm_bo_repair, + input pc_mm_bo_shdata, + input [0:4] pc_mm_bo_select, + output [0:4] mm_pc_bo_fail, + output [0:4] mm_pc_bo_diagout, + input iu_mm_ierat_req, + input [0:51] iu_mm_ierat_epn, + input [0:`THREADS-1] iu_mm_ierat_thdid, + input [0:`ERAT_STATE_WIDTH-1] iu_mm_ierat_state, + input [0:`PID_WIDTH-1] iu_mm_ierat_tid, + input iu_mm_ierat_req_nonspec, + input [0:`THREADS-1] iu_mm_ierat_flush, + output [0:4] mm_iu_ierat_rel_val, + output [0:`ERAT_REL_DATA_WIDTH-1] mm_iu_ierat_rel_data, + output mm_iu_ierat_snoop_coming, + output mm_iu_ierat_snoop_val, + output [0:25] mm_iu_ierat_snoop_attr, + output [52-`EPN_WIDTH:51] mm_iu_ierat_snoop_vpn, + input iu_mm_ierat_snoop_ack, + + output [0:`PID_WIDTH-1] mm_iu_t0_ierat_pid, + output [0:`MMUCR0_WIDTH-1] mm_iu_t0_ierat_mmucr0, +`ifdef MM_THREADS2 + output [0:`PID_WIDTH-1] mm_iu_t1_ierat_pid, + output [0:`MMUCR0_WIDTH-1] mm_iu_t1_ierat_mmucr0, +`endif + + input [0:17] iu_mm_ierat_mmucr0, + input [0:`THREADS-1] iu_mm_ierat_mmucr0_we, + output [0:8] mm_iu_ierat_mmucr1, + output mm_iu_tlbwe_binv, + input [0:3] iu_mm_ierat_mmucr1, + input [0:`THREADS-1] iu_mm_ierat_mmucr1_we, + + input xu_mm_derat_req, + input [64-`RS_DATA_WIDTH:51] xu_mm_derat_epn, + input [0:`THREADS-1] xu_mm_derat_thdid, + input [0:1] xu_mm_derat_ttype, + input [0:`ERAT_STATE_WIDTH-1] xu_mm_derat_state, + input [0:`LPID_WIDTH-1] xu_mm_derat_lpid, + input [0:`PID_WIDTH-1] xu_mm_derat_tid, + input lq_mm_derat_req_nonspec, + input [0:`ITAG_SIZE_ENC-1] lq_mm_derat_req_itag, + input [0:`EMQ_ENTRIES-1] lq_mm_derat_req_emq, + output [0:4] mm_xu_derat_rel_val, + output [0:`ERAT_REL_DATA_WIDTH-1] mm_xu_derat_rel_data, + output [0:`ITAG_SIZE_ENC-1] mm_xu_derat_rel_itag, + output [0:`EMQ_ENTRIES-1] mm_xu_derat_rel_emq, + output mm_xu_derat_snoop_coming, + output mm_xu_derat_snoop_val, + output [0:25] mm_xu_derat_snoop_attr, + output [52-`EPN_WIDTH:51] mm_xu_derat_snoop_vpn, + input xu_mm_derat_snoop_ack, + + output [0:`PID_WIDTH-1] mm_xu_t0_derat_pid, + output [0:`MMUCR0_WIDTH-1] mm_xu_t0_derat_mmucr0, +`ifdef MM_THREADS2 + output [0:`PID_WIDTH-1] mm_xu_t1_derat_pid, + output [0:`MMUCR0_WIDTH-1] mm_xu_t1_derat_mmucr0, +`endif + input [0:17] xu_mm_derat_mmucr0, + input [0:`THREADS-1] xu_mm_derat_mmucr0_we, + output [0:9] mm_xu_derat_mmucr1, + input [0:4] xu_mm_derat_mmucr1, + input [0:`THREADS-1] xu_mm_derat_mmucr1_we, + + input [0:`THREADS-1] xu_mm_rf1_val, + input xu_mm_rf1_is_tlbre, + input xu_mm_rf1_is_tlbwe, + input xu_mm_rf1_is_tlbsx, + input xu_mm_rf1_is_tlbsxr, + input xu_mm_rf1_is_tlbsrx, + input xu_mm_rf1_is_tlbivax, + input xu_mm_rf1_is_tlbilx, + input xu_mm_rf1_is_erativax, + input xu_mm_rf1_is_eratilx, + input xu_mm_ex1_is_isync, + input xu_mm_ex1_is_csync, + input [0:2] xu_mm_rf1_t, + input [0:8] xu_mm_ex1_rs_is, + input [64-`RS_DATA_WIDTH:63] xu_mm_ex2_eff_addr, + input [0:`THREADS-1] xu_mm_msr_gs, + input [0:`THREADS-1] xu_mm_msr_pr, + input [0:`THREADS-1] xu_mm_msr_is, + input [0:`THREADS-1] xu_mm_msr_ds, + input [0:`THREADS-1] xu_mm_msr_cm, + input [0:`THREADS-1] xu_mm_spr_epcr_dmiuh, + input [0:`THREADS-1] xu_mm_spr_epcr_dgtmi, + input xu_mm_hid_mmu_mode, + input xu_mm_xucr4_mmu_mchk, + input xu_mm_lmq_stq_empty, + input iu_mm_lmq_empty, + input [0:`THREADS-1] xu_rf1_flush, + input [0:`THREADS-1] xu_ex1_flush, + input [0:`THREADS-1] xu_ex2_flush, + input [0:`THREADS-1] xu_ex3_flush, + input [0:`THREADS-1] xu_ex4_flush, + input [0:`THREADS-1] xu_ex5_flush, + input [0:`THREADS-1] xu_mm_ex4_flush, + input [0:`THREADS-1] xu_mm_ex5_flush, + input [0:`THREADS-1] xu_mm_ierat_miss, + input [0:`THREADS-1] xu_mm_ierat_flush, + input [0:`THREADS-1] lq_mm_perf_dtlb, + input [0:`THREADS-1] iu_mm_perf_itlb, + + output [0:`THREADS-1] mm_xu_eratmiss_done, + output [0:`THREADS-1] mm_xu_cr0_eq, + output [0:`THREADS-1] mm_xu_cr0_eq_valid, + output [0:`THREADS-1] mm_xu_tlb_miss, + output [0:`THREADS-1] mm_xu_lrat_miss, + output [0:`THREADS-1] mm_xu_tlb_inelig, + output [0:`THREADS-1] mm_xu_pt_fault, + output [0:`THREADS-1] mm_xu_hv_priv, + output [0:`THREADS-1] mm_xu_illeg_instr, + output [0:`THREADS-1] mm_xu_esr_pt, + output [0:`THREADS-1] mm_xu_esr_data, + output [0:`THREADS-1] mm_xu_esr_epid, + output [0:`THREADS-1] mm_xu_esr_st, + output [0:`THREADS-1] mm_xu_tlb_multihit_err, + output [0:`THREADS-1] mm_xu_tlb_par_err, + output [0:`THREADS-1] mm_xu_lru_par_err, + output [0:`THREADS-1] mm_xu_local_snoop_reject, + + output mm_xu_ord_tlb_multihit, + output mm_xu_ord_tlb_par_err, + output mm_xu_ord_lru_par_err, + + output mm_xu_tlb_miss_ored, + output mm_xu_lrat_miss_ored, + output mm_xu_tlb_inelig_ored, + output mm_xu_pt_fault_ored, + output mm_xu_hv_priv_ored, + output mm_xu_illeg_instr_ored, + output mm_xu_cr0_eq_ored, + output mm_xu_cr0_eq_valid_ored, + output mm_pc_tlb_multihit_err_ored, + output mm_pc_tlb_par_err_ored, + output mm_pc_lru_par_err_ored, + output mm_pc_local_snoop_reject_ored, + + input [0:`ITAG_SIZE_ENC-1] xu_mm_rf1_itag, + output [0:`THREADS-1] mm_xu_ord_n_flush_req, + output [0:`THREADS-1] mm_xu_ord_np1_flush_req, + output [0:`THREADS-1] mm_xu_ord_read_done, + output [0:`THREADS-1] mm_xu_ord_write_done, + output mm_xu_ord_n_flush_req_ored, + output mm_xu_ord_np1_flush_req_ored, + output mm_xu_ord_read_done_ored, + output mm_xu_ord_write_done_ored, + output [0:`ITAG_SIZE_ENC-1] mm_xu_itag, + + input [0:`THREADS-1] iu_mm_hold_ack, + output [0:`THREADS-1] mm_iu_hold_req, + output [0:`THREADS-1] mm_iu_hold_done, + output [0:`THREADS-1] mm_iu_flush_req, + input [0:`THREADS-1] iu_mm_bus_snoop_hold_ack, + output [0:`THREADS-1] mm_iu_bus_snoop_hold_req, + output [0:`THREADS-1] mm_iu_bus_snoop_hold_done, + output [0:`THREADS-1] mm_iu_tlbi_complete, + output [0:`THREADS-1] mm_xu_ex3_flush_req, + output [0:`THREADS-1] mm_xu_quiesce, + output [0:`THREADS-1] mm_pc_tlb_req_quiesce, + output [0:`THREADS-1] mm_pc_tlb_ctl_quiesce, + output [0:`THREADS-1] mm_pc_htw_quiesce, + output [0:`THREADS-1] mm_pc_inval_quiesce, + +`ifdef WAIT_UPDATES + input [0:5] cp_mm_except_taken_t0, +`ifndef THREADS1 + input [0:5] cp_mm_except_taken_t1, +`endif + // 0 - val + // 1 - I=0/D=1 + // 2 - TLB miss + // 3 - Storage int (TLBI/PTfault) + // 4 - LRAT miss + // 5 - Mcheck +`endif + + output [0:`THREADS-1] mm_xu_lsu_req, + output [0:1] mm_xu_lsu_ttype, + output [0:4] mm_xu_lsu_wimge, + output [0:3] mm_xu_lsu_u, + output [64-`REAL_ADDR_WIDTH:63] mm_xu_lsu_addr, + output [0:7] mm_xu_lsu_lpid, + output [0:7] mm_xu_lsu_lpidr, + output mm_xu_lsu_gs, + output mm_xu_lsu_ind, + output mm_xu_lsu_lbit, + input xu_mm_lsu_token, + + input slowspr_val_in, + input slowspr_rw_in, + input [0:1] slowspr_etid_in, + input [0:9] slowspr_addr_in, + input [64-`SPR_DATA_WIDTH:63] slowspr_data_in, + input slowspr_done_in, + output slowspr_val_out, + output slowspr_rw_out, + output [0:1] slowspr_etid_out, + output [0:9] slowspr_addr_out, + output [64-`SPR_DATA_WIDTH:63] slowspr_data_out, + output slowspr_done_out, + +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + input gptr_scan_in, +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + input time_scan_in, +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + input repr_scan_in, +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + input [0:1] abst_scan_in, +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + input [0:9] func_scan_in, +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + input bcfg_scan_in, +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + input ccfg_scan_in, +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + input dcfg_scan_in, +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + output [0:1] abst_scan_out, +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + output [0:9] func_scan_out, +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + output gptr_scan_out, +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + output repr_scan_out, +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + output time_scan_out, +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + output bcfg_scan_out, +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + output ccfg_scan_out, +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + output dcfg_scan_out, + + input ac_an_power_managed_imm, + input an_ac_lbist_ary_wrt_thru_dc, + input an_ac_back_inv, + input an_ac_back_inv_target, + input [64-`REAL_ADDR_WIDTH:63] an_ac_back_inv_addr, + input an_ac_back_inv_local, + input an_ac_back_inv_lbit, + input an_ac_back_inv_gs, + input an_ac_back_inv_ind, + input [0:`LPID_WIDTH-1] an_ac_back_inv_lpar_id, + output ac_an_back_inv_reject, + output [0:`LPID_WIDTH-1] ac_an_lpar_id, + input [0:4] an_ac_reld_core_tag, + input [0:127] an_ac_reld_data, + input an_ac_reld_data_vld, + input an_ac_reld_ecc_err, + input an_ac_reld_ecc_err_ue, + input [58:59] an_ac_reld_qw, + input an_ac_reld_ditc, + input an_ac_reld_crit_qw + +); + + parameter BCFG_MMUCR1_VALUE = 201326592; // mmucr1 32-bits boot value, 201326592 -> bits 4:5 csinv="11" + parameter BCFG_MMUCR2_VALUE = 685361; // mmucr2 32-bits boot value, 0xa7531 + parameter BCFG_MMUCR3_VALUE = 15; // mmucr2 15-bits boot value, 0x000f + parameter BCFG_MMUCFG_VALUE = 3; // mmucfg lrat|twc bits boot value + parameter BCFG_TLB0CFG_VALUE = 7; // tlb0cfg pt|ind|gtwe bits boot value + parameter MMQ_SPR_CSWITCH_0TO3 = 8; // chicken switch values: 8=disable mmucr1 read clear, 4=disable mmucr1.tlbwe_binv + parameter MMQ_INVAL_CSWITCH_0TO3 = 0; + parameter MMQ_TLB_CMP_CSWITCH_0TO7 = 0; + + parameter LRAT_NUM_ENTRY_LOG2 = 3; + + parameter MMU_Mode_Value = 1'b0; + parameter [0:1] TlbSel_Tlb = 2'b00; + parameter [0:1] TlbSel_IErat = 2'b10; + parameter [0:1] TlbSel_DErat = 2'b11; + + // func scan bit 0 is mmq_inval (701), mmq_spr(0) non-mas (439) ~1140 + // func scan bit 1 is mmq_spr(1) mas regs (1017) ~1017 + // func scan bit 2 is tlb_req ~1196 + // func scan bit 3 is tlb_ctl ~1101 + // func scan bit 4 is tlb_cmp(0) ~1134 + // func scan bit 5 is tlb_cmp(1) ~1134 + // func scan bit 6 is tlb_lrat ~1059 + // func scan bit 7 is tlb_htw(0) ~802 + // func scan bit 8 is tlb_htw(1) ~663 + // func scan bit 9 is tlb_cmp(2), perf (60), debug daisy chain (134) ~636 + + parameter mmq_inval_offset = 0; + parameter mmq_spr_offset_0 = mmq_inval_offset + 1; + parameter scan_right_0 = mmq_spr_offset_0; + parameter tlb_cmp2_offset = 0; + parameter mmq_perf_offset = tlb_cmp2_offset + 1; + parameter mmq_dbg_offset = mmq_perf_offset + 1; + parameter scan_right_1 = mmq_dbg_offset; + parameter mmq_spr_bcfg_offset = 0; + parameter boot_scan_right = mmq_spr_bcfg_offset + 1 - 1; + + // genvar statements + genvar tid; + + // Power signals + wire vdd; + wire gnd; + assign vdd = 1'b1; + assign gnd = 1'b0; + + // local spr signals + wire [0:`MM_THREADS-1] cp_flush_p1; + wire [0:`PID_WIDTH-1] pid0_sig; + wire [0:`MMUCR0_WIDTH-1] mmucr0_0_sig; + wire [64-`MMUCR3_WIDTH:63] mmucr3_0_sig; + wire [1:3] tstmode4k_0_sig; +`ifdef MM_THREADS2 + wire [0:`PID_WIDTH-1] pid1_sig; + wire [0:`MMUCR0_WIDTH-1] mmucr0_1_sig; + wire [64-`MMUCR3_WIDTH:63] mmucr3_1_sig; + wire [1:3] tstmode4k_1_sig; +`endif + wire [0:`MMUCR1_WIDTH-1] mmucr1_sig; + wire [0:`MMUCR2_WIDTH-1] mmucr2_sig; + wire [0:`LPID_WIDTH-1] lpidr_sig; + wire [0:`MESR1_WIDTH+`MESR2_WIDTH-1] mmq_spr_event_mux_ctrls_sig; + wire [0:`LPID_WIDTH-1] ac_an_lpar_id_sig; + wire [0:4] mm_iu_ierat_rel_val_sig; + wire [0:`ERAT_REL_DATA_WIDTH-1] mm_iu_ierat_rel_data_sig; + wire [0:4] mm_xu_derat_rel_val_sig; + wire [0:`ERAT_REL_DATA_WIDTH-1] mm_xu_derat_rel_data_sig; + wire [0:`MM_THREADS-1] mm_iu_hold_req_sig; + wire [0:`MM_THREADS-1] mm_iu_hold_done_sig; + wire [0:`MM_THREADS-1] mm_iu_flush_req_sig; + wire [0:`MM_THREADS-1] mm_iu_bus_snoop_hold_req_sig; + wire [0:`MM_THREADS-1] mm_iu_bus_snoop_hold_done_sig; + wire [0:`MM_THREADS-1] mm_iu_tlbi_complete_sig; + wire [0:6] tlb_cmp_ierat_dup_val_sig; + wire [0:6] tlb_cmp_derat_dup_val_sig; + wire [0:1] tlb_cmp_erat_dup_wait_sig; + wire [0:`MM_THREADS-1] tlb_ctl_ex2_flush_req_sig; + wire [0:`MM_THREADS-1] tlb_ctl_ex2_illeg_instr_sig; + wire [0:`MM_THREADS-1] tlb_ctl_barrier_done_sig; + wire [0:2] tlb_ctl_ord_type; + wire [0:`ITAG_SIZE_ENC-1] tlb_ctl_ex2_itag_sig; + wire [0:`MM_THREADS-1] tlb_ctl_ex6_illeg_instr_sig; + wire [0:`MM_THREADS-1] mm_xu_ex3_flush_req_sig; + wire [0:`MM_THREADS-1] mm_xu_quiesce_sig; + wire [0:`MM_THREADS-1] mm_pc_tlb_req_quiesce_sig; + wire [0:`MM_THREADS-1] mm_pc_tlb_ctl_quiesce_sig; + wire [0:`MM_THREADS-1] mm_pc_htw_quiesce_sig; + wire [0:`MM_THREADS-1] mm_pc_inval_quiesce_sig; + wire [0:`MM_THREADS-1] mm_xu_eratmiss_done_sig; + wire [0:`MM_THREADS-1] mm_xu_tlb_miss_sig; + wire [0:`MM_THREADS-1] mm_xu_lrat_miss_sig; + wire [0:`MM_THREADS-1] mm_xu_pt_fault_sig; + wire [0:`MM_THREADS-1] mm_xu_hv_priv_sig; + wire [0:`MM_THREADS-1] mm_xu_illeg_instr_sig; + wire [0:`MM_THREADS-1] mm_xu_tlb_inelig_sig; + wire [0:`MM_THREADS-1] mm_xu_esr_pt_sig; + wire [0:`MM_THREADS-1] mm_xu_esr_data_sig; + wire [0:`MM_THREADS-1] mm_xu_esr_epid_sig; + wire [0:`MM_THREADS-1] mm_xu_esr_st_sig; + wire [0:`MM_THREADS-1] mm_xu_cr0_eq_sig; + wire [0:`MM_THREADS-1] mm_xu_cr0_eq_valid_sig; + wire [0:`MM_THREADS-1] mm_xu_local_snoop_reject_sig; + //signal mm_pc_err_local_snoop_reject_sig : std_ulogic_vector(0 to (`MM_THREADS-1)); + wire [0:`THDID_WIDTH-1] tlb_req_quiesce_sig; + wire [0:`MM_THREADS-1] tlb_ctl_quiesce_sig; + wire [0:`THDID_WIDTH-1] htw_quiesce_sig; + wire [1:12] xu_mm_ccr2_notlb_b; + wire [0:`MM_THREADS-1] xu_mm_epcr_dgtmi_sig; + wire xu_mm_xucr4_mmu_mchk_q; + wire mm_xu_tlb_miss_ored_sig; + wire mm_xu_lrat_miss_ored_sig; + wire mm_xu_tlb_inelig_ored_sig; + wire mm_xu_pt_fault_ored_sig; + wire mm_xu_hv_priv_ored_sig; + wire mm_xu_cr0_eq_ored_sig; + wire mm_xu_cr0_eq_valid_ored_sig; + wire mm_pc_tlb_multihit_err_ored_sig; + wire mm_pc_tlb_par_err_ored_sig; + wire mm_pc_lru_par_err_ored_sig; + wire mm_pc_local_snoop_reject_ored_sig; + // Internal signals + wire [0:`LRU_WIDTH-1] lru_write; + wire [0:`TLB_ADDR_WIDTH-1] lru_wr_addr; + wire [0:`TLB_ADDR_WIDTH-1] lru_rd_addr; + wire [0:`LRU_WIDTH-1] lru_datain; + wire [0:`LRU_WIDTH-1] lru_dataout; + wire [0:`TLB_TAG_WIDTH-1] tlb_tag2_sig; + wire [0:`TLB_ADDR_WIDTH-1] tlb_addr2_sig; + wire [0:`TLB_ADDR_WIDTH-1] tlb_addr4; + wire [0:`TLB_WAYS-1] tlb_write; + //signal tlb_way : std_ulogic_vector(0 to `TLB_WAYS-1); + wire [0:`TLB_ADDR_WIDTH-1] tlb_addr; + wire [0:`TLB_WAY_WIDTH-1] tlb_dataina; + wire [0:`TLB_WAY_WIDTH-1] tlb_datainb; + wire [0:`TLB_WAY_WIDTH*`TLB_WAYS-1] tlb_dataout; + wire [0:15] lru_tag4_dataout; + wire [0:2] tlb_tag4_esel; + wire [0:1] tlb_tag4_wq; + wire [0:1] tlb_tag4_is; + wire tlb_tag4_gs; + wire tlb_tag4_pr; + wire tlb_tag4_hes; + wire tlb_tag4_atsel; + wire tlb_tag4_pt; + wire tlb_tag4_cmp_hit; + wire tlb_tag4_way_ind; + wire tlb_tag4_ptereload; + wire tlb_tag4_endflag; + wire tlb_tag4_parerr; + wire [0:`TLB_WAYS-1] tlb_tag4_parerr_write; + wire tlb_tag5_parerr_zeroize; + wire [0:`MM_THREADS-1] tlb_tag5_except; + wire [0:`ITAG_SIZE_ENC-1] tlb_tag4_itag_sig; + wire [0:`ITAG_SIZE_ENC-1] tlb_tag5_itag_sig; + wire [0:`EMQ_ENTRIES-1] tlb_tag5_emq_sig; + wire [0:`PTE_WIDTH-1] ptereload_req_pte_lat; + wire [0:1] ex6_illeg_instr; // bad op tlbre/we indication from tlb_ctl + wire [0:`MM_THREADS-1] tlb_ctl_tag2_flush_sig; + wire [0:`MM_THREADS-1] tlb_ctl_tag3_flush_sig; + wire [0:`MM_THREADS-1] tlb_ctl_tag4_flush_sig; + wire [0:`MM_THREADS-1] tlb_resv_match_vec_sig; + wire [0:`MM_THREADS-1] tlb_ctl_ex3_valid_sig; + wire [0:4] tlb_ctl_ex3_ttype_sig; + wire tlb_ctl_ex3_hv_state_sig; + wire ierat_req_taken; + wire derat_req_taken; + wire tlb_seq_ierat_req; + wire tlb_seq_derat_req; + wire tlb_seq_ierat_done; + wire tlb_seq_derat_done; + wire tlb_seq_idle; + wire [0:`EPN_WIDTH-1] ierat_req_epn; + wire [0:`PID_WIDTH-1] ierat_req_pid; + wire [0:`ERAT_STATE_WIDTH-1] ierat_req_state; + wire [0:`THDID_WIDTH-1] ierat_req_thdid; + wire [0:1] ierat_req_dup; + wire ierat_req_nonspec; + wire [0:`EPN_WIDTH-1] derat_req_epn; + wire [0:`PID_WIDTH-1] derat_req_pid; + wire [0:`LPID_WIDTH-1] derat_req_lpid; + wire [0:`ERAT_STATE_WIDTH-1] derat_req_state; + wire [0:1] derat_req_ttype; + wire [0:`THDID_WIDTH-1] derat_req_thdid; + wire [0:1] derat_req_dup; + wire [0:`ITAG_SIZE_ENC-1] derat_req_itag; + wire [0:`EMQ_ENTRIES-1] derat_req_emq; + wire derat_req_nonspec; + wire ptereload_req_valid; + wire [0:`TLB_TAG_WIDTH-1] ptereload_req_tag; + wire [0:`PTE_WIDTH-1] ptereload_req_pte; + wire ptereload_req_taken; + wire tlb_htw_req_valid; + wire [0:`TLB_TAG_WIDTH-1] tlb_htw_req_tag; + wire [`TLB_WORD_WIDTH:`TLB_WAY_WIDTH-1] tlb_htw_req_way; + wire htw_lsu_req_valid; + wire [0:`THDID_WIDTH-1] htw_lsu_thdid; + wire [0:1] htw_dbg_lsu_thdid; + // 0=tlbivax_op, 1=tlbi_complete, 2=mmu read with core_tag=01100, 3=mmu read with core_tag=01101 + wire [0:1] htw_lsu_ttype; + wire [0:4] htw_lsu_wimge; + wire [0:3] htw_lsu_u; + wire [64-`REAL_ADDR_WIDTH:63] htw_lsu_addr; + wire htw_lsu_req_taken; + wire htw_req0_valid; + wire [0:`THDID_WIDTH-1] htw_req0_thdid; + wire [0:1] htw_req0_type; + wire htw_req1_valid; + wire [0:`THDID_WIDTH-1] htw_req1_thdid; + wire [0:1] htw_req1_type; + wire htw_req2_valid; + wire [0:`THDID_WIDTH-1] htw_req2_thdid; + wire [0:1] htw_req2_type; + wire htw_req3_valid; + wire [0:`THDID_WIDTH-1] htw_req3_thdid; + wire [0:1] htw_req3_type; + wire [0:`MM_THREADS-1] mm_xu_lsu_req_sig; + wire [0:1] mm_xu_lsu_ttype_sig; + wire [0:4] mm_xu_lsu_wimge_sig; + wire [0:3] mm_xu_lsu_u_sig; + wire [64-`REAL_ADDR_WIDTH:63] mm_xu_lsu_addr_sig; + wire [0:7] mm_xu_lsu_lpid_sig; + //signal mm_xu_lsu_lpidr_sig : std_ulogic_vector(0 to 7); -- lpidr spr to lsu + wire mm_xu_lsu_gs_sig; + wire mm_xu_lsu_ind_sig; + wire mm_xu_lsu_lbit_sig; + wire [64-`RS_DATA_WIDTH:63] xu_mm_ex2_eff_addr_sig; + wire [0:5] repr_scan_int; + wire [0:5] time_scan_int; + wire [0:6] abst_scan_int; + wire tlbwe_back_inv_valid_sig; + wire [0:`MM_THREADS-1] tlbwe_back_inv_thdid_sig; + wire [52-`EPN_WIDTH:51] tlbwe_back_inv_addr_sig; + wire [0:34] tlbwe_back_inv_attr_sig; + wire tlbwe_back_inv_pending_sig; + wire tlb_tag5_write; + // these are needed regardless of tlb existence + wire tlb_snoop_coming; + wire tlb_snoop_val; + wire [0:34] tlb_snoop_attr; + wire [52-`EPN_WIDTH:51] tlb_snoop_vpn; + wire tlb_snoop_ack; + wire mas0_0_atsel; + wire [0:2] mas0_0_esel; + wire mas0_0_hes; + wire [0:1] mas0_0_wq; + wire mas1_0_v; + wire mas1_0_iprot; + wire [0:13] mas1_0_tid; + wire mas1_0_ind; + wire mas1_0_ts; + wire [0:3] mas1_0_tsize; + wire [0:51] mas2_0_epn; + wire [0:4] mas2_0_wimge; + wire [32:52] mas3_0_rpnl; + wire [0:3] mas3_0_ubits; + wire [0:5] mas3_0_usxwr; + wire mas5_0_sgs; + wire [0:7] mas5_0_slpid; + wire [0:13] mas6_0_spid; + wire [0:3] mas6_0_isize; + wire mas6_0_sind; + wire mas6_0_sas; + wire [22:31] mas7_0_rpnu; + wire mas8_0_tgs; + wire mas8_0_vf; + wire [0:7] mas8_0_tlpid; +`ifdef MM_THREADS2 + wire mas0_1_atsel; + wire [0:2] mas0_1_esel; + wire mas0_1_hes; + wire [0:1] mas0_1_wq; + wire mas1_1_v; + wire mas1_1_iprot; + wire [0:13] mas1_1_tid; + wire mas1_1_ind; + wire mas1_1_ts; + wire [0:3] mas1_1_tsize; + wire [0:51] mas2_1_epn; + wire [0:4] mas2_1_wimge; + wire [32:52] mas3_1_rpnl; + wire [0:3] mas3_1_ubits; + wire [0:5] mas3_1_usxwr; + wire mas5_1_sgs; + wire [0:7] mas5_1_slpid; + wire [0:13] mas6_1_spid; + wire [0:3] mas6_1_isize; + wire mas6_1_sind; + wire mas6_1_sas; + wire [22:31] mas7_1_rpnu; + wire mas8_1_tgs; + wire mas8_1_vf; + wire [0:7] mas8_1_tlpid; +`endif + wire mmucfg_lrat; + wire mmucfg_twc; + wire mmucsr0_tlb0fi; + wire mmq_inval_tlb0fi_done; + wire tlb0cfg_pt; + wire tlb0cfg_ind; + wire tlb0cfg_gtwe; + wire [0:2] tlb_mas0_esel; + wire tlb_mas1_v; + wire tlb_mas1_iprot; + wire [0:`PID_WIDTH-1] tlb_mas1_tid; + wire [0:`PID_WIDTH-1] tlb_mas1_tid_error; + wire tlb_mas1_ind; + wire tlb_mas1_ts; + wire tlb_mas1_ts_error; + wire [0:3] tlb_mas1_tsize; + wire [0:51] tlb_mas2_epn; + wire [0:51] tlb_mas2_epn_error; + wire [0:4] tlb_mas2_wimge; + wire [32:51] tlb_mas3_rpnl; + wire [0:3] tlb_mas3_ubits; + wire [0:5] tlb_mas3_usxwr; + wire [22:31] tlb_mas7_rpnu; + wire tlb_mas8_tgs; + wire tlb_mas8_vf; + wire [0:7] tlb_mas8_tlpid; + wire [0:8] tlb_mmucr1_een; + wire tlb_mmucr1_we; + wire [0:`THDID_WIDTH-1] tlb_mmucr3_thdid; + wire tlb_mmucr3_resvattr; + wire [0:1] tlb_mmucr3_wlc; + wire [0:`CLASS_WIDTH-1] tlb_mmucr3_class; + wire [0:`EXTCLASS_WIDTH-1] tlb_mmucr3_extclass; + wire [0:1] tlb_mmucr3_rc; + wire tlb_mmucr3_x; + wire tlb_mas_tlbre; + wire tlb_mas_tlbsx_hit; + wire tlb_mas_tlbsx_miss; + wire tlb_mas_dtlb_error; + wire tlb_mas_itlb_error; + wire [0:`MM_THREADS-1] tlb_mas_thdid; + wire [0:`THDID_WIDTH-1] tlb_mas_thdid_dbg; + wire [0:2] lrat_mas0_esel; + wire lrat_mas1_v; + wire [0:3] lrat_mas1_tsize; + wire [0:51] lrat_mas2_epn; + wire [32:51] lrat_mas3_rpnl; + wire [22:31] lrat_mas7_rpnu; + wire [0:`LPID_WIDTH-1] lrat_mas8_tlpid; + wire lrat_mmucr3_x; + wire lrat_mas_tlbre; + wire lrat_mas_tlbsx_hit; + wire lrat_mas_tlbsx_miss; + wire [0:`MM_THREADS-1] lrat_mas_thdid; + wire [0:`THDID_WIDTH-1] lrat_mas_thdid_dbg; + wire [64-`REAL_ADDR_WIDTH:51] lrat_tag3_lpn; + wire [64-`REAL_ADDR_WIDTH:51] lrat_tag3_rpn; + wire [0:3] lrat_tag3_hit_status; + wire [0:LRAT_NUM_ENTRY_LOG2-1] lrat_tag3_hit_entry; + wire [64-`REAL_ADDR_WIDTH:51] lrat_tag4_lpn; + wire [64-`REAL_ADDR_WIDTH:51] lrat_tag4_rpn; + wire [0:3] lrat_tag4_hit_status; + wire [0:LRAT_NUM_ENTRY_LOG2-1] lrat_tag4_hit_entry; + wire [52-`EPN_WIDTH:51] tlb_tag0_epn; + wire [0:`THDID_WIDTH-1] tlb_tag0_thdid; + wire [0:7] tlb_tag0_type; + wire [0:`LPID_WIDTH-1] tlb_tag0_lpid; + wire tlb_tag0_atsel; + wire [0:3] tlb_tag0_size; + wire tlb_tag0_addr_cap; + wire tlb_tag0_nonspec; + wire tlb_tag4_nonspec; + wire [64-`REAL_ADDR_WIDTH:51] pte_tag0_lpn; + wire [0:`LPID_WIDTH-1] pte_tag0_lpid; + wire [64-`REAL_ADDR_WIDTH:51] tlb_lper_lpn; + wire [60:63] tlb_lper_lps; + wire [0:`MM_THREADS-1] tlb_lper_we; + wire [0:`PID_WIDTH-1] ierat_req0_pid_sig; + wire ierat_req0_as_sig; + wire ierat_req0_gs_sig; + wire [0:`EPN_WIDTH-1] ierat_req0_epn_sig; + wire [0:`THDID_WIDTH-1] ierat_req0_thdid_sig; + wire ierat_req0_valid_sig; + wire ierat_req0_nonspec_sig; + wire [0:`PID_WIDTH-1] ierat_req1_pid_sig; + wire ierat_req1_as_sig; + wire ierat_req1_gs_sig; + wire [0:`EPN_WIDTH-1] ierat_req1_epn_sig; + wire [0:`THDID_WIDTH-1] ierat_req1_thdid_sig; + wire ierat_req1_valid_sig; + wire ierat_req1_nonspec_sig; + wire [0:`PID_WIDTH-1] ierat_req2_pid_sig; + wire ierat_req2_as_sig; + wire ierat_req2_gs_sig; + wire [0:`EPN_WIDTH-1] ierat_req2_epn_sig; + wire [0:`THDID_WIDTH-1] ierat_req2_thdid_sig; + wire ierat_req2_valid_sig; + wire ierat_req2_nonspec_sig; + wire [0:`PID_WIDTH-1] ierat_req3_pid_sig; + wire ierat_req3_as_sig; + wire ierat_req3_gs_sig; + wire [0:`EPN_WIDTH-1] ierat_req3_epn_sig; + wire [0:`THDID_WIDTH-1] ierat_req3_thdid_sig; + wire ierat_req3_valid_sig; + wire ierat_req3_nonspec_sig; + wire [0:`PID_WIDTH-1] ierat_iu4_pid_sig; + wire ierat_iu4_gs_sig; + wire ierat_iu4_as_sig; + wire [0:`EPN_WIDTH-1] ierat_iu4_epn_sig; + wire [0:`THDID_WIDTH-1] ierat_iu4_thdid_sig; + wire ierat_iu4_valid_sig; + wire [0:`LPID_WIDTH-1] derat_req0_lpid_sig; + wire [0:`PID_WIDTH-1] derat_req0_pid_sig; + wire derat_req0_as_sig; + wire derat_req0_gs_sig; + wire [0:`EPN_WIDTH-1] derat_req0_epn_sig; + wire [0:`THDID_WIDTH-1] derat_req0_thdid_sig; + wire [0:`EMQ_ENTRIES-1] derat_req0_emq_sig; + wire derat_req0_valid_sig; + wire derat_req0_nonspec_sig; + wire [0:`LPID_WIDTH-1] derat_req1_lpid_sig; + wire [0:`PID_WIDTH-1] derat_req1_pid_sig; + wire derat_req1_as_sig; + wire derat_req1_gs_sig; + wire [0:`EPN_WIDTH-1] derat_req1_epn_sig; + wire [0:`THDID_WIDTH-1] derat_req1_thdid_sig; + wire [0:`EMQ_ENTRIES-1] derat_req1_emq_sig; + wire derat_req1_valid_sig; + wire derat_req1_nonspec_sig; + wire [0:`LPID_WIDTH-1] derat_req2_lpid_sig; + wire [0:`PID_WIDTH-1] derat_req2_pid_sig; + wire derat_req2_as_sig; + wire derat_req2_gs_sig; + wire [0:`EPN_WIDTH-1] derat_req2_epn_sig; + wire [0:`THDID_WIDTH-1] derat_req2_thdid_sig; + wire [0:`EMQ_ENTRIES-1] derat_req2_emq_sig; + wire derat_req2_valid_sig; + wire derat_req2_nonspec_sig; + wire [0:`LPID_WIDTH-1] derat_req3_lpid_sig; + wire [0:`PID_WIDTH-1] derat_req3_pid_sig; + wire derat_req3_as_sig; + wire derat_req3_gs_sig; + wire [0:`EPN_WIDTH-1] derat_req3_epn_sig; + wire [0:`THDID_WIDTH-1] derat_req3_thdid_sig; + wire [0:`EMQ_ENTRIES-1] derat_req3_emq_sig; + wire derat_req3_valid_sig; + wire derat_req3_nonspec_sig; + wire [0:`LPID_WIDTH-1] derat_ex5_lpid_sig; + wire [0:`PID_WIDTH-1] derat_ex5_pid_sig; + wire derat_ex5_gs_sig; + wire derat_ex5_as_sig; + wire [0:`EPN_WIDTH-1] derat_ex5_epn_sig; + wire [0:`THDID_WIDTH-1] derat_ex5_thdid_sig; + wire derat_ex5_valid_sig; + wire [0:9] tlb_cmp_perf_event_t0; + wire [0:9] tlb_cmp_perf_event_t1; + wire [0:1] tlb_cmp_perf_state; + wire tlb_cmp_perf_miss_direct; + wire tlb_cmp_perf_hit_direct; + wire tlb_cmp_perf_hit_indirect; + wire tlb_cmp_perf_hit_first_page; + wire tlb_cmp_perf_ptereload; + wire tlb_cmp_perf_ptereload_noexcep; + wire tlb_cmp_perf_lrat_request; + wire tlb_cmp_perf_lrat_miss; + wire tlb_cmp_perf_pt_fault; + wire tlb_cmp_perf_pt_inelig; + wire tlb_ctl_perf_tlbwec_resv; + wire tlb_ctl_perf_tlbwec_noresv; + wire inval_perf_tlbilx; + wire inval_perf_tlbivax; + wire inval_perf_tlbivax_snoop; + wire inval_perf_tlb_flush; +`ifdef WAIT_UPDATES + wire [0:`MM_THREADS+5-1] cp_mm_perf_except_taken_q; +`endif + + //--------- debug signals + wire spr_dbg_match_64b; + wire spr_dbg_match_any_mmu; + wire spr_dbg_match_any_mas; + wire spr_dbg_match_pid; + wire spr_dbg_match_lpidr; + wire spr_dbg_match_mmucr0; + wire spr_dbg_match_mmucr1; + wire spr_dbg_match_mmucr2; + wire spr_dbg_match_mmucr3; + wire spr_dbg_match_mmucsr0; + wire spr_dbg_match_mmucfg; + wire spr_dbg_match_tlb0cfg; + wire spr_dbg_match_tlb0ps; + wire spr_dbg_match_lratcfg; + wire spr_dbg_match_lratps; + wire spr_dbg_match_eptcfg; + wire spr_dbg_match_lper; + wire spr_dbg_match_lperu; + wire spr_dbg_match_mas0; + wire spr_dbg_match_mas1; + wire spr_dbg_match_mas2; + wire spr_dbg_match_mas2u; + wire spr_dbg_match_mas3; + wire spr_dbg_match_mas4; + wire spr_dbg_match_mas5; + wire spr_dbg_match_mas6; + wire spr_dbg_match_mas7; + wire spr_dbg_match_mas8; + wire spr_dbg_match_mas01_64b; + wire spr_dbg_match_mas56_64b; + wire spr_dbg_match_mas73_64b; + wire spr_dbg_match_mas81_64b; + wire spr_dbg_slowspr_val_int; + wire spr_dbg_slowspr_rw_int; + wire [0:1] spr_dbg_slowspr_etid_int; + wire [0:9] spr_dbg_slowspr_addr_int; + wire spr_dbg_slowspr_val_out; + wire spr_dbg_slowspr_done_out; + wire [64-`SPR_DATA_WIDTH:63] spr_dbg_slowspr_data_out; + wire [0:4] inval_dbg_seq_q; + wire inval_dbg_seq_idle; + wire inval_dbg_seq_snoop_inprogress; + wire inval_dbg_seq_snoop_done; + wire inval_dbg_seq_local_done; + wire inval_dbg_seq_tlb0fi_done; + wire inval_dbg_seq_tlbwe_snoop_done; + wire inval_dbg_ex6_valid; + wire [0:1] inval_dbg_ex6_thdid; + wire [0:2] inval_dbg_ex6_ttype; + wire inval_dbg_snoop_forme; + wire inval_dbg_snoop_local_reject; + wire [2:8] inval_dbg_an_ac_back_inv_q; + wire [0:7] inval_dbg_an_ac_back_inv_lpar_id_q; + wire [22:63] inval_dbg_an_ac_back_inv_addr_q; + wire [0:2] inval_dbg_snoop_valid_q; + wire [0:2] inval_dbg_snoop_ack_q; + wire [0:34] inval_dbg_snoop_attr_q; + wire [18:19] inval_dbg_snoop_attr_tlb_spec_q; + wire [17:51] inval_dbg_snoop_vpn_q; + wire [0:1] inval_dbg_lsu_tokens_q; + wire tlb_req_dbg_ierat_iu5_valid_q; + wire [0:1] tlb_req_dbg_ierat_iu5_thdid; + wire [0:3] tlb_req_dbg_ierat_iu5_state_q; + wire [0:1] tlb_req_dbg_ierat_inptr_q; + wire [0:1] tlb_req_dbg_ierat_outptr_q; + wire [0:3] tlb_req_dbg_ierat_req_valid_q; + wire [0:3] tlb_req_dbg_ierat_req_nonspec_q; + wire [0:7] tlb_req_dbg_ierat_req_thdid; + wire [0:3] tlb_req_dbg_ierat_req_dup_q; + wire tlb_req_dbg_derat_ex6_valid_q; + wire [0:1] tlb_req_dbg_derat_ex6_thdid; + wire [0:3] tlb_req_dbg_derat_ex6_state_q; + wire [0:1] tlb_req_dbg_derat_inptr_q; + wire [0:1] tlb_req_dbg_derat_outptr_q; + wire [0:3] tlb_req_dbg_derat_req_valid_q; + wire [0:7] tlb_req_dbg_derat_req_thdid; + wire [0:7] tlb_req_dbg_derat_req_ttype_q; + wire [0:3] tlb_req_dbg_derat_req_dup_q; + wire [0:5] tlb_ctl_dbg_seq_q; + wire tlb_ctl_dbg_seq_idle; + wire tlb_ctl_dbg_seq_any_done_sig; + wire tlb_ctl_dbg_seq_abort; + wire tlb_ctl_dbg_any_tlb_req_sig; + wire tlb_ctl_dbg_any_req_taken_sig; + wire tlb_ctl_dbg_tag0_valid; + wire [0:1] tlb_ctl_dbg_tag0_thdid; + wire [0:2] tlb_ctl_dbg_tag0_type; + wire [0:1] tlb_ctl_dbg_tag0_wq; + wire tlb_ctl_dbg_tag0_gs; + wire tlb_ctl_dbg_tag0_pr; + wire tlb_ctl_dbg_tag0_atsel; + wire [0:3] tlb_ctl_dbg_tag5_tlb_write_q; + wire [0:3] tlb_ctl_dbg_resv_valid; + wire [0:3] tlb_ctl_dbg_set_resv; + wire [0:3] tlb_ctl_dbg_resv_match_vec_q; + wire tlb_ctl_dbg_any_tag_flush_sig; + wire tlb_ctl_dbg_resv0_tag0_lpid_match; + wire tlb_ctl_dbg_resv0_tag0_pid_match; + wire tlb_ctl_dbg_resv0_tag0_as_snoop_match; + wire tlb_ctl_dbg_resv0_tag0_gs_snoop_match; + wire tlb_ctl_dbg_resv0_tag0_as_tlbwe_match; + wire tlb_ctl_dbg_resv0_tag0_gs_tlbwe_match; + wire tlb_ctl_dbg_resv0_tag0_ind_match; + wire tlb_ctl_dbg_resv0_tag0_epn_loc_match; + wire tlb_ctl_dbg_resv0_tag0_epn_glob_match; + wire tlb_ctl_dbg_resv0_tag0_class_match; + wire tlb_ctl_dbg_resv1_tag0_lpid_match; + wire tlb_ctl_dbg_resv1_tag0_pid_match; + wire tlb_ctl_dbg_resv1_tag0_as_snoop_match; + wire tlb_ctl_dbg_resv1_tag0_gs_snoop_match; + wire tlb_ctl_dbg_resv1_tag0_as_tlbwe_match; + wire tlb_ctl_dbg_resv1_tag0_gs_tlbwe_match; + wire tlb_ctl_dbg_resv1_tag0_ind_match; + wire tlb_ctl_dbg_resv1_tag0_epn_loc_match; + wire tlb_ctl_dbg_resv1_tag0_epn_glob_match; + wire tlb_ctl_dbg_resv1_tag0_class_match; + wire tlb_ctl_dbg_resv2_tag0_lpid_match; + wire tlb_ctl_dbg_resv2_tag0_pid_match; + wire tlb_ctl_dbg_resv2_tag0_as_snoop_match; + wire tlb_ctl_dbg_resv2_tag0_gs_snoop_match; + wire tlb_ctl_dbg_resv2_tag0_as_tlbwe_match; + wire tlb_ctl_dbg_resv2_tag0_gs_tlbwe_match; + wire tlb_ctl_dbg_resv2_tag0_ind_match; + wire tlb_ctl_dbg_resv2_tag0_epn_loc_match; + wire tlb_ctl_dbg_resv2_tag0_epn_glob_match; + wire tlb_ctl_dbg_resv2_tag0_class_match; + wire tlb_ctl_dbg_resv3_tag0_lpid_match; + wire tlb_ctl_dbg_resv3_tag0_pid_match; + wire tlb_ctl_dbg_resv3_tag0_as_snoop_match; + wire tlb_ctl_dbg_resv3_tag0_gs_snoop_match; + wire tlb_ctl_dbg_resv3_tag0_as_tlbwe_match; + wire tlb_ctl_dbg_resv3_tag0_gs_tlbwe_match; + wire tlb_ctl_dbg_resv3_tag0_ind_match; + wire tlb_ctl_dbg_resv3_tag0_epn_loc_match; + wire tlb_ctl_dbg_resv3_tag0_epn_glob_match; + wire tlb_ctl_dbg_resv3_tag0_class_match; + wire [0:3] tlb_ctl_dbg_clr_resv_q; + wire [0:3] tlb_ctl_dbg_clr_resv_terms; + wire [0:`TLB_TAG_WIDTH-1] tlb_cmp_dbg_tag4; + wire [0:`TLB_WAYS] tlb_cmp_dbg_tag4_wayhit; + wire [0:`TLB_ADDR_WIDTH-1] tlb_cmp_dbg_addr4; + wire [0:`TLB_WAY_WIDTH-1] tlb_cmp_dbg_tag4_way; + wire [0:4] tlb_cmp_dbg_tag4_parerr; + wire [0:`LRU_WIDTH-5] tlb_cmp_dbg_tag4_lru_dataout_q; + wire [0:`TLB_WAY_WIDTH-1] tlb_cmp_dbg_tag5_tlb_datain_q; + wire [0:`LRU_WIDTH-5] tlb_cmp_dbg_tag5_lru_datain_q; + wire tlb_cmp_dbg_tag5_lru_write; + wire tlb_cmp_dbg_tag5_any_exception; + wire [0:3] tlb_cmp_dbg_tag5_except_type_q; + wire [0:1] tlb_cmp_dbg_tag5_except_thdid_q; + wire [0:9] tlb_cmp_dbg_tag5_erat_rel_val; + wire [0:131] tlb_cmp_dbg_tag5_erat_rel_data; + wire [0:19] tlb_cmp_dbg_erat_dup_q; + wire [0:8] tlb_cmp_dbg_addr_enable; + wire tlb_cmp_dbg_pgsize_enable; + wire tlb_cmp_dbg_class_enable; + wire [0:1] tlb_cmp_dbg_extclass_enable; + wire [0:1] tlb_cmp_dbg_state_enable; + wire tlb_cmp_dbg_thdid_enable; + wire tlb_cmp_dbg_pid_enable; + wire tlb_cmp_dbg_lpid_enable; + wire tlb_cmp_dbg_ind_enable; + wire tlb_cmp_dbg_iprot_enable; + wire tlb_cmp_dbg_way0_entry_v; + wire tlb_cmp_dbg_way0_addr_match; + wire tlb_cmp_dbg_way0_pgsize_match; + wire tlb_cmp_dbg_way0_class_match; + wire tlb_cmp_dbg_way0_extclass_match; + wire tlb_cmp_dbg_way0_state_match; + wire tlb_cmp_dbg_way0_thdid_match; + wire tlb_cmp_dbg_way0_pid_match; + wire tlb_cmp_dbg_way0_lpid_match; + wire tlb_cmp_dbg_way0_ind_match; + wire tlb_cmp_dbg_way0_iprot_match; + wire tlb_cmp_dbg_way1_entry_v; + wire tlb_cmp_dbg_way1_addr_match; + wire tlb_cmp_dbg_way1_pgsize_match; + wire tlb_cmp_dbg_way1_class_match; + wire tlb_cmp_dbg_way1_extclass_match; + wire tlb_cmp_dbg_way1_state_match; + wire tlb_cmp_dbg_way1_thdid_match; + wire tlb_cmp_dbg_way1_pid_match; + wire tlb_cmp_dbg_way1_lpid_match; + wire tlb_cmp_dbg_way1_ind_match; + wire tlb_cmp_dbg_way1_iprot_match; + wire tlb_cmp_dbg_way2_entry_v; + wire tlb_cmp_dbg_way2_addr_match; + wire tlb_cmp_dbg_way2_pgsize_match; + wire tlb_cmp_dbg_way2_class_match; + wire tlb_cmp_dbg_way2_extclass_match; + wire tlb_cmp_dbg_way2_state_match; + wire tlb_cmp_dbg_way2_thdid_match; + wire tlb_cmp_dbg_way2_pid_match; + wire tlb_cmp_dbg_way2_lpid_match; + wire tlb_cmp_dbg_way2_ind_match; + wire tlb_cmp_dbg_way2_iprot_match; + wire tlb_cmp_dbg_way3_entry_v; + wire tlb_cmp_dbg_way3_addr_match; + wire tlb_cmp_dbg_way3_pgsize_match; + wire tlb_cmp_dbg_way3_class_match; + wire tlb_cmp_dbg_way3_extclass_match; + wire tlb_cmp_dbg_way3_state_match; + wire tlb_cmp_dbg_way3_thdid_match; + wire tlb_cmp_dbg_way3_pid_match; + wire tlb_cmp_dbg_way3_lpid_match; + wire tlb_cmp_dbg_way3_ind_match; + wire tlb_cmp_dbg_way3_iprot_match; + wire lrat_dbg_tag1_addr_enable; + wire [0:7] lrat_dbg_tag2_matchline_q; + wire lrat_dbg_entry0_addr_match; + wire lrat_dbg_entry0_lpid_match; + wire lrat_dbg_entry0_entry_v; + wire lrat_dbg_entry0_entry_x; + wire [0:3] lrat_dbg_entry0_size; + wire lrat_dbg_entry1_addr_match; + wire lrat_dbg_entry1_lpid_match; + wire lrat_dbg_entry1_entry_v; + wire lrat_dbg_entry1_entry_x; + wire [0:3] lrat_dbg_entry1_size; + wire lrat_dbg_entry2_addr_match; + wire lrat_dbg_entry2_lpid_match; + wire lrat_dbg_entry2_entry_v; + wire lrat_dbg_entry2_entry_x; + wire [0:3] lrat_dbg_entry2_size; + wire lrat_dbg_entry3_addr_match; + wire lrat_dbg_entry3_lpid_match; + wire lrat_dbg_entry3_entry_v; + wire lrat_dbg_entry3_entry_x; + wire [0:3] lrat_dbg_entry3_size; + wire lrat_dbg_entry4_addr_match; + wire lrat_dbg_entry4_lpid_match; + wire lrat_dbg_entry4_entry_v; + wire lrat_dbg_entry4_entry_x; + wire [0:3] lrat_dbg_entry4_size; + wire lrat_dbg_entry5_addr_match; + wire lrat_dbg_entry5_lpid_match; + wire lrat_dbg_entry5_entry_v; + wire lrat_dbg_entry5_entry_x; + wire [0:3] lrat_dbg_entry5_size; + wire lrat_dbg_entry6_addr_match; + wire lrat_dbg_entry6_lpid_match; + wire lrat_dbg_entry6_entry_v; + wire lrat_dbg_entry6_entry_x; + wire [0:3] lrat_dbg_entry6_size; + wire lrat_dbg_entry7_addr_match; + wire lrat_dbg_entry7_lpid_match; + wire lrat_dbg_entry7_entry_v; + wire lrat_dbg_entry7_entry_x; + wire [0:3] lrat_dbg_entry7_size; + wire htw_dbg_seq_idle; + wire htw_dbg_pte0_seq_idle; + wire htw_dbg_pte1_seq_idle; + wire [0:1] htw_dbg_seq_q; + wire [0:1] htw_dbg_inptr_q; + wire [0:2] htw_dbg_pte0_seq_q; + wire [0:2] htw_dbg_pte1_seq_q; + wire htw_dbg_ptereload_ptr_q; + wire [0:1] htw_dbg_lsuptr_q; + wire [0:3] htw_dbg_req_valid_q; + wire [0:3] htw_dbg_resv_valid_vec; + wire [0:3] htw_dbg_tag4_clr_resv_q; + wire [0:3] htw_dbg_tag4_clr_resv_terms; + wire [0:1] htw_dbg_pte0_score_ptr_q; + wire [58:60] htw_dbg_pte0_score_cl_offset_q; + wire [0:2] htw_dbg_pte0_score_error_q; + wire [0:3] htw_dbg_pte0_score_qwbeat_q; + wire htw_dbg_pte0_score_pending_q; + wire htw_dbg_pte0_score_ibit_q; + wire htw_dbg_pte0_score_dataval_q; + wire htw_dbg_pte0_reld_for_me_tm1; + wire [0:1] htw_dbg_pte1_score_ptr_q; + wire [58:60] htw_dbg_pte1_score_cl_offset_q; + wire [0:2] htw_dbg_pte1_score_error_q; + wire [0:3] htw_dbg_pte1_score_qwbeat_q; + wire htw_dbg_pte1_score_pending_q; + wire htw_dbg_pte1_score_ibit_q; + wire htw_dbg_pte1_score_dataval_q; + wire htw_dbg_pte1_reld_for_me_tm1; + // power clock gating sigs + wire [9:33] tlb_delayed_act; + + (* analysis_not_referenced="true" *) + wire [0:71+`MM_THREADS-`THREADS] unused_dc; + + (* analysis_not_referenced="true" *) + wire [0:0] unused_dc_array_scan; + + // Pervasive + wire lcb_clkoff_dc_b; + wire lcb_act_dis_dc; + wire lcb_d_mode_dc; + wire [0:4] lcb_delay_lclkr_dc; + wire [0:4] lcb_mpw1_dc_b; + wire lcb_mpw2_dc_b; + wire g6t_gptr_lcb_clkoff_dc_b; + wire g6t_gptr_lcb_act_dis_dc; + wire g6t_gptr_lcb_d_mode_dc; + wire [0:4] g6t_gptr_lcb_delay_lclkr_dc; + wire [0:4] g6t_gptr_lcb_mpw1_dc_b; + wire g6t_gptr_lcb_mpw2_dc_b; + wire g8t_gptr_lcb_clkoff_dc_b; + wire g8t_gptr_lcb_act_dis_dc; + wire g8t_gptr_lcb_d_mode_dc; + wire [0:4] g8t_gptr_lcb_delay_lclkr_dc; + wire [0:4] g8t_gptr_lcb_mpw1_dc_b; + wire g8t_gptr_lcb_mpw2_dc_b; + wire [0:1] pc_func_sl_thold_2; + wire [0:1] pc_func_slp_sl_thold_2; + wire pc_func_slp_nsl_thold_2; + wire pc_fce_2; + wire pc_cfg_sl_thold_2; + wire pc_cfg_slp_sl_thold_2; + wire [0:1] pc_sg_2; + wire [0:1] pc_sg_1; + wire [0:1] pc_sg_0; + wire [0:1] pc_func_sl_thold_0; + wire [0:1] pc_func_sl_thold_0_b; + wire [0:1] pc_func_slp_sl_thold_0; + wire [0:1] pc_func_slp_sl_thold_0_b; + wire pc_abst_sl_thold_0; + wire pc_abst_slp_sl_thold_0; + wire pc_repr_sl_thold_0; + wire pc_time_sl_thold_0; + wire pc_ary_nsl_thold_0; + wire pc_ary_slp_nsl_thold_0; + wire pc_mm_bolt_sl_thold_0; + wire pc_mm_bo_enable_2; + wire pc_mm_abist_g8t_wenb_q; + wire pc_mm_abist_g8t1p_renb_0_q; + wire [0:3] pc_mm_abist_di_0_q; + wire pc_mm_abist_g8t_bw_1_q; + wire pc_mm_abist_g8t_bw_0_q; + wire [0:9] pc_mm_abist_waddr_0_q; + wire [0:9] pc_mm_abist_raddr_0_q; + wire pc_mm_abist_wl128_comp_ena_q; + wire [0:3] pc_mm_abist_g8t_dcomp_q; + wire [0:3] pc_mm_abist_dcomp_g6t_2r_q; + wire [0:3] pc_mm_abist_di_g6t_2r_q; + wire pc_mm_abist_g6t_r_wb_q; + wire time_scan_in_int; + wire time_scan_out_int; + wire [0:9] func_scan_in_int; + wire [0:9] func_scan_out_int; + wire repr_scan_in_int; + wire repr_scan_out_int; + wire [0:1] abst_scan_in_int; + wire [0:1] abst_scan_out_int; + wire bcfg_scan_in_int; + wire bcfg_scan_out_int; + wire ccfg_scan_in_int; + wire ccfg_scan_out_int; + wire dcfg_scan_in_int; + wire dcfg_scan_out_int; + wire [0:scan_right_0] siv_0; + wire [0:scan_right_0] sov_0; + wire [0:scan_right_1] siv_1; + wire [0:scan_right_1] sov_1; + wire [0:boot_scan_right] bsiv; + wire [0:boot_scan_right] bsov; + wire tidn; + wire tiup; + // threading generic conversion sigs + wire [0:`THDID_WIDTH-1] iu_mm_ierat_thdid_sig; + wire [0:`THDID_WIDTH-1] iu_mm_ierat_flush_sig; + wire [0:`MM_THREADS-1] iu_mm_ierat_mmucr0_we_sig; + wire [0:`MM_THREADS-1] iu_mm_ierat_mmucr1_we_sig; + wire [0:`MM_THREADS-1] iu_mm_hold_ack_sig; + wire [0:`MM_THREADS-1] iu_mm_bus_snoop_hold_ack_sig; + wire [0:`MM_THREADS-1] xu_mm_derat_mmucr0_we_sig; + wire [0:`MM_THREADS-1] xu_mm_derat_mmucr1_we_sig; + wire [0:`THDID_WIDTH-1] xu_mm_derat_thdid_sig; + wire [0:`MM_THREADS-1] mm_xu_ord_n_flush_req_sig; + wire [0:`MM_THREADS-1] mm_xu_ord_np1_flush_req_sig; + wire [0:`MM_THREADS-1] mm_xu_ord_read_done_sig; + wire [0:`MM_THREADS-1] mm_xu_ord_write_done_sig; + wire [0:`MM_THREADS-1] xu_mm_msr_gs_sig; + wire [0:`MM_THREADS-1] xu_mm_msr_pr_sig; + wire [0:`MM_THREADS-1] xu_mm_msr_is_sig; + wire [0:`MM_THREADS-1] xu_mm_msr_ds_sig; + wire [0:`MM_THREADS-1] xu_mm_msr_cm_sig; + wire [0:`MM_THREADS-1] xu_mm_spr_epcr_dgtmi_sig; + wire [0:`MM_THREADS-1] xu_mm_spr_epcr_dmiuh_sig; + wire [0:`MM_THREADS-1] xu_rf1_flush_sig; + wire [0:`MM_THREADS-1] xu_ex1_flush_sig; + wire [0:`MM_THREADS-1] xu_ex2_flush_sig; + wire [0:`THDID_WIDTH-1] xu_ex3_flush_sig; + wire [0:`MM_THREADS-1] xu_ex4_flush_sig; + wire [0:`MM_THREADS-1] xu_ex5_flush_sig; + wire [0:`THDID_WIDTH-1] xu_mm_ex4_flush_sig; + wire [0:`THDID_WIDTH-1] xu_mm_ex5_flush_sig; + wire [0:`THDID_WIDTH-1] xu_mm_ierat_flush_sig; + wire [0:`THDID_WIDTH-1] xu_mm_ierat_miss_sig; + wire [0:`MM_THREADS-1] mm_xu_tlb_multihit_err_sig; + wire [0:`MM_THREADS-1] mm_xu_tlb_par_err_sig; + wire [0:`MM_THREADS-1] mm_xu_lru_par_err_sig; + + wire mm_xu_ord_tlb_multihit_sig; + wire mm_xu_ord_tlb_par_err_sig; + wire mm_xu_ord_lru_par_err_sig; + + wire [0:`MM_THREADS-1] xu_mm_rf1_val_sig; + wire [0:`THDID_WIDTH-1] lq_mm_perf_dtlb_sig; + wire [0:`THDID_WIDTH-1] iu_mm_perf_itlb_sig; + wire [0:`THDID_WIDTH-1] xu_mm_msr_gs_perf; + wire [0:`THDID_WIDTH-1] xu_mm_msr_pr_perf; + + wire [0:`PID_WIDTH-1] mm_iu_ierat_pid_sig [0:`MM_THREADS-1]; + wire [0:`PID_WIDTH-1] mm_xu_derat_pid_sig [0:`MM_THREADS-1]; + + wire [0:`MMUCR0_WIDTH-1] mm_iu_ierat_mmucr0_sig [0:`MM_THREADS-1]; + wire [0:`MMUCR0_WIDTH-1] mm_xu_derat_mmucr0_sig [0:`MM_THREADS-1]; + +`ifdef WAIT_UPDATES + wire [0:5] cp_mm_except_taken_t0_sig; + wire [0:5] cp_mm_except_taken_t1_sig; +`endif + + //--------------------------------------------------------------------- + // common stuff for tlb and erat-only modes + //--------------------------------------------------------------------- + assign tidn = 1'b0; + assign tiup = 1'b1; + + assign ac_an_lpar_id = ac_an_lpar_id_sig; + assign mm_xu_lsu_lpidr = lpidr_sig; + +`ifdef WAIT_UPDATES + assign cp_mm_except_taken_t0_sig = cp_mm_except_taken_t0; +`ifndef THREADS1 + assign cp_mm_except_taken_t1_sig = cp_mm_except_taken_t1; +`else + assign cp_mm_except_taken_t1_sig = 6'b0; +`endif +`endif + + + // input port threadwise widening `THREADS(n) -> `MM_THREADS(m) + generate + begin : xhdl0 +// genvar tid; + for (tid = 0; tid <= `MM_THREADS-1; tid = tid + 1) + begin : mmThreads + if (tid < `THREADS) + begin : tidExist + assign iu_mm_ierat_mmucr0_we_sig[tid] = iu_mm_ierat_mmucr0_we[tid]; + assign iu_mm_ierat_mmucr1_we_sig[tid] = iu_mm_ierat_mmucr1_we[tid]; + assign xu_mm_derat_mmucr0_we_sig[tid] = xu_mm_derat_mmucr0_we[tid]; + assign xu_mm_derat_mmucr1_we_sig[tid] = xu_mm_derat_mmucr1_we[tid]; + assign iu_mm_hold_ack_sig[tid] = iu_mm_hold_ack[tid]; + assign iu_mm_bus_snoop_hold_ack_sig[tid] = iu_mm_bus_snoop_hold_ack[tid]; + assign xu_mm_msr_gs_sig[tid] = xu_mm_msr_gs[tid]; + assign xu_mm_msr_pr_sig[tid] = xu_mm_msr_pr[tid]; + assign xu_mm_msr_is_sig[tid] = xu_mm_msr_is[tid]; + assign xu_mm_msr_ds_sig[tid] = xu_mm_msr_ds[tid]; + assign xu_mm_msr_cm_sig[tid] = xu_mm_msr_cm[tid]; + assign xu_mm_spr_epcr_dgtmi_sig[tid] = xu_mm_spr_epcr_dgtmi[tid]; + assign xu_mm_spr_epcr_dmiuh_sig[tid] = xu_mm_spr_epcr_dmiuh[tid]; + assign xu_rf1_flush_sig[tid] = xu_rf1_flush[tid]; + assign xu_ex1_flush_sig[tid] = xu_ex1_flush[tid]; + assign xu_ex2_flush_sig[tid] = xu_ex2_flush[tid]; + assign xu_ex4_flush_sig[tid] = xu_ex4_flush[tid]; + assign xu_ex5_flush_sig[tid] = xu_ex5_flush[tid]; + assign xu_mm_rf1_val_sig[tid] = xu_mm_rf1_val[tid]; + end + if (tid >= `THREADS) + begin : tidNExist + assign iu_mm_ierat_mmucr0_we_sig[tid] = tidn; + assign iu_mm_ierat_mmucr1_we_sig[tid] = tidn; + assign xu_mm_derat_mmucr0_we_sig[tid] = tidn; + assign xu_mm_derat_mmucr1_we_sig[tid] = tidn; + assign iu_mm_hold_ack_sig[tid] = tiup; + assign iu_mm_bus_snoop_hold_ack_sig[tid] = tiup; + assign xu_mm_msr_gs_sig[tid] = tidn; + assign xu_mm_msr_pr_sig[tid] = tidn; + assign xu_mm_msr_is_sig[tid] = tidn; + assign xu_mm_msr_ds_sig[tid] = tidn; + assign xu_mm_msr_cm_sig[tid] = tidn; + assign xu_mm_spr_epcr_dgtmi_sig[tid] = tidn; + assign xu_mm_spr_epcr_dmiuh_sig[tid] = tidn; + assign xu_rf1_flush_sig[tid] = tidn; + assign xu_ex1_flush_sig[tid] = tidn; + assign xu_ex2_flush_sig[tid] = tidn; + assign xu_ex4_flush_sig[tid] = tidn; + assign xu_ex5_flush_sig[tid] = tidn; + assign xu_mm_rf1_val_sig[tid] = tidn; + end + end + end + endgenerate + + generate + begin : xhdl1 +// genvar tid; + for (tid = 0; tid <= `THDID_WIDTH - 1; tid = tid + 1) + begin : mmDbgThreads + if (tid < `MM_THREADS) + begin : tidDbgExist + assign tlb_mas_thdid_dbg[tid] = tlb_mas_thdid[tid]; + assign lrat_mas_thdid_dbg[tid] = lrat_mas_thdid[tid]; + end + if (tid >= `MM_THREADS) + begin : tidDbgNExist + assign tlb_mas_thdid_dbg[tid] = tidn; + assign lrat_mas_thdid_dbg[tid] = tidn; + end + end +end +endgenerate + +generate + begin : xhdl2 +// genvar tid; + for (tid = 0; tid <= `THDID_WIDTH - 1; tid = tid + 1) + begin : mmperfThreads + if (tid < `THREADS) + begin : tidperfExist + assign xu_mm_msr_gs_perf[tid] = xu_mm_msr_gs[tid]; + assign xu_mm_msr_pr_perf[tid] = xu_mm_msr_gs[tid]; + assign xu_ex3_flush_sig[tid] = xu_ex3_flush[tid]; + assign xu_mm_ex4_flush_sig[tid] = xu_mm_ex4_flush[tid]; + assign xu_mm_ex5_flush_sig[tid] = xu_mm_ex5_flush[tid]; + assign lq_mm_perf_dtlb_sig[tid] = lq_mm_perf_dtlb[tid]; + assign iu_mm_perf_itlb_sig[tid] = iu_mm_perf_itlb[tid]; + assign xu_mm_derat_thdid_sig[tid] = xu_mm_derat_thdid[tid]; + assign xu_mm_ierat_flush_sig[tid] = xu_mm_ierat_flush[tid]; + assign xu_mm_ierat_miss_sig[tid] = xu_mm_ierat_miss[tid]; + assign iu_mm_ierat_thdid_sig[tid] = iu_mm_ierat_thdid[tid]; + assign iu_mm_ierat_flush_sig[tid] = iu_mm_ierat_flush[tid]; + end + if (tid >= `THREADS) + begin : tidperfNExist + assign xu_mm_msr_gs_perf[tid] = tidn; + assign xu_mm_msr_pr_perf[tid] = tidn; + assign xu_ex3_flush_sig[tid] = tidn; + assign xu_mm_ex4_flush_sig[tid] = tidn; + assign xu_mm_ex5_flush_sig[tid] = tidn; + assign lq_mm_perf_dtlb_sig[tid] = tidn; + assign iu_mm_perf_itlb_sig[tid] = tidn; + assign xu_mm_derat_thdid_sig[tid] = tidn; + assign xu_mm_ierat_flush_sig[tid] = tidn; + assign xu_mm_ierat_miss_sig[tid] = tidn; + assign iu_mm_ierat_thdid_sig[tid] = tidn; + assign iu_mm_ierat_flush_sig[tid] = tidn; + end +end +end +endgenerate + +//--------------------------------------------------------------------- +// Invalidate Component Instantiation +//--------------------------------------------------------------------- + +mmq_inval #(.MMQ_INVAL_CSWITCH_0TO3(MMQ_INVAL_CSWITCH_0TO3)) mmq_inval( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .tc_ccflush_dc(tc_ac_ccflush_dc), + .tc_scan_dis_dc_b(tc_ac_scan_dis_dc_b), + .tc_scan_diag_dc(tc_ac_scan_diag_dc), + .tc_lbist_en_dc(tc_ac_lbist_en_dc), + + .lcb_d_mode_dc(lcb_d_mode_dc), + .lcb_clkoff_dc_b(lcb_clkoff_dc_b), + .lcb_act_dis_dc(lcb_act_dis_dc), + .lcb_mpw1_dc_b(lcb_mpw1_dc_b), + .lcb_mpw2_dc_b(lcb_mpw2_dc_b), + .lcb_delay_lclkr_dc(lcb_delay_lclkr_dc), + + .ac_func_scan_in(siv_0[mmq_inval_offset]), + .ac_func_scan_out(sov_0[mmq_inval_offset]), + + .pc_sg_2(pc_sg_2[0]), + .pc_func_sl_thold_2(pc_func_sl_thold_2[0]), + .pc_func_slp_sl_thold_2(pc_func_slp_sl_thold_2[0]), + .pc_func_slp_nsl_thold_2(pc_func_slp_nsl_thold_2), + .pc_fce_2(pc_fce_2), + .mmucr2_act_override(mmucr2_sig[7]), + .xu_mm_ccr2_notlb(xu_mm_hid_mmu_mode), + .xu_mm_ccr2_notlb_b(xu_mm_ccr2_notlb_b), + + .mm_iu_ierat_snoop_coming(mm_iu_ierat_snoop_coming), + .mm_iu_ierat_snoop_val(mm_iu_ierat_snoop_val), + .mm_iu_ierat_snoop_attr(mm_iu_ierat_snoop_attr), + .mm_iu_ierat_snoop_vpn(mm_iu_ierat_snoop_vpn), + .iu_mm_ierat_snoop_ack(iu_mm_ierat_snoop_ack), + + .mm_xu_derat_snoop_coming(mm_xu_derat_snoop_coming), + .mm_xu_derat_snoop_val(mm_xu_derat_snoop_val), + .mm_xu_derat_snoop_attr(mm_xu_derat_snoop_attr), + .mm_xu_derat_snoop_vpn(mm_xu_derat_snoop_vpn), + .xu_mm_derat_snoop_ack(xu_mm_derat_snoop_ack), + + .tlb_snoop_coming(tlb_snoop_coming), + .tlb_snoop_val(tlb_snoop_val), + .tlb_snoop_attr(tlb_snoop_attr), + .tlb_snoop_vpn(tlb_snoop_vpn), + .tlb_snoop_ack(tlb_snoop_ack), + + .tlb_ctl_barrier_done(tlb_ctl_barrier_done_sig), + .tlb_ctl_ex2_flush_req(tlb_ctl_ex2_flush_req_sig), + .tlb_ctl_ex2_illeg_instr(tlb_ctl_ex2_illeg_instr_sig), + .tlb_ctl_ex6_illeg_instr(tlb_ctl_ex6_illeg_instr_sig), + .tlb_ctl_ex2_itag(tlb_ctl_ex2_itag_sig), + .tlb_ctl_ord_type(tlb_ctl_ord_type), + .tlb_tag4_itag(tlb_tag4_itag_sig), + .tlb_tag5_except(tlb_tag5_except), + .tlb_ctl_quiesce(tlb_ctl_quiesce_sig), + .tlb_req_quiesce(tlb_req_quiesce_sig[0:`MM_THREADS-1]), + + .mm_xu_ex3_flush_req(mm_xu_ex3_flush_req_sig), + .mm_xu_illeg_instr(mm_xu_illeg_instr_sig), + .mm_xu_local_snoop_reject(mm_xu_local_snoop_reject_sig), + .mm_xu_ord_n_flush_req(mm_xu_ord_n_flush_req_sig), + .mm_xu_ord_np1_flush_req(mm_xu_ord_np1_flush_req_sig), + .mm_xu_ord_read_done(mm_xu_ord_read_done_sig), + .mm_xu_ord_write_done(mm_xu_ord_write_done_sig), + .mm_xu_illeg_instr_ored(mm_xu_illeg_instr_ored), + .mm_xu_ord_n_flush_req_ored(mm_xu_ord_n_flush_req_ored), + .mm_xu_ord_np1_flush_req_ored(mm_xu_ord_np1_flush_req_ored), + .mm_xu_ord_read_done_ored(mm_xu_ord_read_done_ored), + .mm_xu_ord_write_done_ored(mm_xu_ord_write_done_ored), + + .mm_xu_itag(mm_xu_itag), + + .mm_pc_local_snoop_reject_ored(mm_pc_local_snoop_reject_ored_sig), + + .an_ac_back_inv(an_ac_back_inv), + .an_ac_back_inv_target(an_ac_back_inv_target), + .an_ac_back_inv_local(an_ac_back_inv_local), + .an_ac_back_inv_lbit(an_ac_back_inv_lbit), + .an_ac_back_inv_gs(an_ac_back_inv_gs), + .an_ac_back_inv_ind(an_ac_back_inv_ind), + .an_ac_back_inv_addr(an_ac_back_inv_addr), + .an_ac_back_inv_lpar_id(an_ac_back_inv_lpar_id), + .ac_an_back_inv_reject(ac_an_back_inv_reject), + .ac_an_power_managed(ac_an_power_managed_imm), + .lpidr(lpidr_sig), + .mas5_0_sgs(mas5_0_sgs), + .mas5_0_slpid(mas5_0_slpid), + .mas6_0_spid(mas6_0_spid), + .mas6_0_isize(mas6_0_isize), + .mas6_0_sind(mas6_0_sind), + .mas6_0_sas(mas6_0_sas), + .mmucr0_0(mmucr0_0_sig[2:19]), +`ifdef MM_THREADS2 + .mas5_1_sgs(mas5_1_sgs), + .mas5_1_slpid(mas5_1_slpid), + .mas6_1_spid(mas6_1_spid), + .mas6_1_isize(mas6_1_isize), + .mas6_1_sind(mas6_1_sind), + .mas6_1_sas(mas6_1_sas), + .mmucr0_1(mmucr0_1_sig[2:19]), +`endif + .mmucr1(mmucr1_sig[12:19]), + .mmucr1_csinv(mmucr1_sig[4:5]), + .mmucsr0_tlb0fi(mmucsr0_tlb0fi), + .mmq_inval_tlb0fi_done(mmq_inval_tlb0fi_done), + + .xu_mm_rf1_val(xu_mm_rf1_val_sig), + .xu_mm_rf1_is_tlbivax(xu_mm_rf1_is_tlbivax), + .xu_mm_rf1_is_tlbilx(xu_mm_rf1_is_tlbilx), + .xu_mm_rf1_is_erativax(xu_mm_rf1_is_erativax), + .xu_mm_rf1_is_eratilx(xu_mm_rf1_is_eratilx), + .xu_mm_ex1_rs_is(xu_mm_ex1_rs_is), + .xu_mm_ex1_is_isync(xu_mm_ex1_is_isync), + .xu_mm_ex1_is_csync(xu_mm_ex1_is_csync), + .xu_mm_ex2_eff_addr(xu_mm_ex2_eff_addr_sig), + .xu_mm_rf1_t(xu_mm_rf1_t), + .xu_mm_rf1_itag(xu_mm_rf1_itag), + .xu_mm_msr_gs(xu_mm_msr_gs_sig), + .xu_mm_msr_pr(xu_mm_msr_pr_sig), + .xu_mm_spr_epcr_dgtmi(xu_mm_spr_epcr_dgtmi_sig), + .xu_mm_epcr_dgtmi(xu_mm_epcr_dgtmi_sig), + .xu_rf1_flush(xu_rf1_flush_sig), + .xu_ex1_flush(xu_ex1_flush_sig), + .xu_ex2_flush(xu_ex2_flush_sig), + .xu_ex3_flush(xu_ex3_flush_sig[0:`MM_THREADS-1]), + .xu_ex4_flush(xu_ex4_flush_sig), + .xu_ex5_flush(xu_ex5_flush_sig), + .xu_mm_lmq_stq_empty(xu_mm_lmq_stq_empty), + .iu_mm_lmq_empty(iu_mm_lmq_empty), + .iu_mm_hold_ack(iu_mm_hold_ack_sig), + .mm_iu_hold_req(mm_iu_hold_req_sig), + .mm_iu_hold_done(mm_iu_hold_done_sig), + .mm_iu_flush_req(mm_iu_flush_req_sig), + .iu_mm_bus_snoop_hold_ack(iu_mm_bus_snoop_hold_ack_sig), + .mm_iu_bus_snoop_hold_req(mm_iu_bus_snoop_hold_req_sig), + .mm_iu_bus_snoop_hold_done(mm_iu_bus_snoop_hold_done_sig), + .mm_iu_tlbi_complete(mm_iu_tlbi_complete_sig), + + .mm_xu_quiesce(mm_xu_quiesce_sig), + .mm_pc_tlb_req_quiesce(mm_pc_tlb_req_quiesce_sig), + .mm_pc_tlb_ctl_quiesce(mm_pc_tlb_ctl_quiesce_sig), + .mm_pc_htw_quiesce(mm_pc_htw_quiesce_sig), + .mm_pc_inval_quiesce(mm_pc_inval_quiesce_sig), + .inval_perf_tlbilx(inval_perf_tlbilx), + .inval_perf_tlbivax(inval_perf_tlbivax), + .inval_perf_tlbivax_snoop(inval_perf_tlbivax_snoop), + .inval_perf_tlb_flush(inval_perf_tlb_flush), + + .htw_lsu_req_valid(htw_lsu_req_valid), + .htw_lsu_thdid(htw_lsu_thdid[0:`MM_THREADS-1]), + .htw_lsu_ttype(htw_lsu_ttype), + .htw_lsu_wimge(htw_lsu_wimge), + .htw_lsu_u(htw_lsu_u), + .htw_lsu_addr(htw_lsu_addr), + .htw_lsu_req_taken(htw_lsu_req_taken), + .htw_quiesce(htw_quiesce_sig[0:`MM_THREADS-1]), + + .tlbwe_back_inv_valid(tlbwe_back_inv_valid_sig), + .tlbwe_back_inv_thdid(tlbwe_back_inv_thdid_sig), + .tlbwe_back_inv_addr(tlbwe_back_inv_addr_sig), + .tlbwe_back_inv_attr(tlbwe_back_inv_attr_sig), + .tlbwe_back_inv_pending(tlbwe_back_inv_pending_sig), + .tlb_tag5_write(tlb_tag5_write), + + .mm_xu_lsu_req(mm_xu_lsu_req_sig), + .mm_xu_lsu_ttype(mm_xu_lsu_ttype_sig), + .mm_xu_lsu_wimge(mm_xu_lsu_wimge_sig), + .mm_xu_lsu_u(mm_xu_lsu_u_sig), + .mm_xu_lsu_addr(mm_xu_lsu_addr_sig), + .mm_xu_lsu_lpid(mm_xu_lsu_lpid_sig), + .mm_xu_lsu_gs(mm_xu_lsu_gs_sig), + .mm_xu_lsu_ind(mm_xu_lsu_ind_sig), + .mm_xu_lsu_lbit(mm_xu_lsu_lbit_sig), + .xu_mm_lsu_token(xu_mm_lsu_token), + + .inval_dbg_seq_q(inval_dbg_seq_q), + .inval_dbg_seq_idle(inval_dbg_seq_idle), + .inval_dbg_seq_snoop_inprogress(inval_dbg_seq_snoop_inprogress), + .inval_dbg_seq_snoop_done(inval_dbg_seq_snoop_done), + .inval_dbg_seq_local_done(inval_dbg_seq_local_done), + .inval_dbg_seq_tlb0fi_done(inval_dbg_seq_tlb0fi_done), + .inval_dbg_seq_tlbwe_snoop_done(inval_dbg_seq_tlbwe_snoop_done), + .inval_dbg_ex6_valid(inval_dbg_ex6_valid), + .inval_dbg_ex6_thdid(inval_dbg_ex6_thdid), + .inval_dbg_ex6_ttype(inval_dbg_ex6_ttype), + .inval_dbg_snoop_forme(inval_dbg_snoop_forme), + .inval_dbg_snoop_local_reject(inval_dbg_snoop_local_reject), + .inval_dbg_an_ac_back_inv_q(inval_dbg_an_ac_back_inv_q), + .inval_dbg_an_ac_back_inv_lpar_id_q(inval_dbg_an_ac_back_inv_lpar_id_q), + .inval_dbg_an_ac_back_inv_addr_q(inval_dbg_an_ac_back_inv_addr_q), + .inval_dbg_snoop_valid_q(inval_dbg_snoop_valid_q), + .inval_dbg_snoop_ack_q(inval_dbg_snoop_ack_q), + .inval_dbg_snoop_attr_q(inval_dbg_snoop_attr_q), + .inval_dbg_snoop_attr_tlb_spec_q(inval_dbg_snoop_attr_tlb_spec_q), + .inval_dbg_snoop_vpn_q(inval_dbg_snoop_vpn_q), + .inval_dbg_lsu_tokens_q(inval_dbg_lsu_tokens_q) +); +// End of mmq_inval component instantiation + +//--------------------------------------------------------------------- +// Special Purpose Register Component Instantiation +//--------------------------------------------------------------------- + +mmq_spr #(.BCFG_MMUCR1_VALUE(BCFG_MMUCR1_VALUE), .BCFG_MMUCR2_VALUE(BCFG_MMUCR2_VALUE), .BCFG_MMUCR3_VALUE(BCFG_MMUCR3_VALUE), + .BCFG_MMUCFG_VALUE(BCFG_MMUCFG_VALUE), .BCFG_TLB0CFG_VALUE(BCFG_TLB0CFG_VALUE), .MMQ_SPR_CSWITCH_0TO3(MMQ_SPR_CSWITCH_0TO3)) mmq_spr( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .cp_flush(xu_ex5_flush[0:`THREADS - 1]), + .cp_flush_p1(cp_flush_p1), + .tc_ccflush_dc(tc_ac_ccflush_dc), + .tc_scan_dis_dc_b(tc_ac_scan_dis_dc_b), + .tc_scan_diag_dc(tc_ac_scan_diag_dc), + .tc_lbist_en_dc(tc_ac_lbist_en_dc), + + .lcb_d_mode_dc(lcb_d_mode_dc), + .lcb_clkoff_dc_b(lcb_clkoff_dc_b), + .lcb_act_dis_dc(lcb_act_dis_dc), + .lcb_mpw1_dc_b(lcb_mpw1_dc_b), + .lcb_mpw2_dc_b(lcb_mpw2_dc_b), + .lcb_delay_lclkr_dc(lcb_delay_lclkr_dc), + + .ac_func_scan_in( {siv_0[mmq_spr_offset_0], func_scan_in_int[1]} ), + .ac_func_scan_out( {sov_0[mmq_spr_offset_0], func_scan_out_int[1]} ), + .ac_bcfg_scan_in(bsiv[mmq_spr_bcfg_offset]), + .ac_bcfg_scan_out(bsov[mmq_spr_bcfg_offset]), + + .pc_sg_2(pc_sg_2[0]), + .pc_func_sl_thold_2(pc_func_sl_thold_2[0]), + .pc_func_slp_sl_thold_2(pc_func_slp_sl_thold_2[0]), + .pc_func_slp_nsl_thold_2(pc_func_slp_nsl_thold_2), + .pc_cfg_sl_thold_2(pc_cfg_sl_thold_2), + .pc_cfg_slp_sl_thold_2(pc_cfg_slp_sl_thold_2), + .pc_fce_2(pc_fce_2), + .xu_mm_ccr2_notlb_b(xu_mm_ccr2_notlb_b[1]), + .mmucr2_act_override(mmucr2_sig[5:6]), + + .tlb_delayed_act(tlb_delayed_act[29:29 + `MM_THREADS-1]), + +`ifdef WAIT_UPDATES + .cp_mm_except_taken_t0(cp_mm_except_taken_t0_sig), +`ifdef MM_THREADS2 + .cp_mm_except_taken_t1(cp_mm_except_taken_t1_sig), +`endif + .cp_mm_perf_except_taken_q(cp_mm_perf_except_taken_q), +`endif + + .mm_iu_ierat_pid0(mm_iu_ierat_pid_sig[0]), + .mm_iu_ierat_mmucr0_0(mm_iu_ierat_mmucr0_sig[0]), +`ifdef MM_THREADS2 + .mm_iu_ierat_pid1(mm_iu_ierat_pid_sig[1]), + .mm_iu_ierat_mmucr0_1(mm_iu_ierat_mmucr0_sig[1]), +`endif + .iu_mm_ierat_mmucr0(iu_mm_ierat_mmucr0), + .iu_mm_ierat_mmucr0_we(iu_mm_ierat_mmucr0_we_sig), + .mm_iu_ierat_mmucr1(mm_iu_ierat_mmucr1), + .iu_mm_ierat_mmucr1(iu_mm_ierat_mmucr1), + .iu_mm_ierat_mmucr1_we(iu_mm_ierat_mmucr1_we_sig), + + .mm_xu_derat_pid0(mm_xu_derat_pid_sig[0]), + .mm_xu_derat_mmucr0_0(mm_xu_derat_mmucr0_sig[0]), +`ifdef MM_THREADS2 + .mm_xu_derat_pid1(mm_xu_derat_pid_sig[1]), + .mm_xu_derat_mmucr0_1(mm_xu_derat_mmucr0_sig[1]), +`endif + .xu_mm_derat_mmucr0(xu_mm_derat_mmucr0), + .xu_mm_derat_mmucr0_we(xu_mm_derat_mmucr0_we_sig), + .mm_xu_derat_mmucr1(mm_xu_derat_mmucr1), + .xu_mm_derat_mmucr1(xu_mm_derat_mmucr1), + .xu_mm_derat_mmucr1_we(xu_mm_derat_mmucr1_we_sig), + + .pid0(pid0_sig), + .mmucr0_0(mmucr0_0_sig), + .mmucr3_0(mmucr3_0_sig), + .tstmode4k_0(tstmode4k_0_sig), +`ifdef MM_THREADS2 + .pid1(pid1_sig), + .mmucr0_1(mmucr0_1_sig), + .mmucr3_1(mmucr3_1_sig), + .tstmode4k_1(tstmode4k_1_sig), +`endif + .mmucr1(mmucr1_sig), + .mmucr2(mmucr2_sig), + .mmucfg_lrat(mmucfg_lrat), + .mmucfg_twc(mmucfg_twc), + .tlb0cfg_pt(tlb0cfg_pt), + .tlb0cfg_ind(tlb0cfg_ind), + .tlb0cfg_gtwe(tlb0cfg_gtwe), + .mmq_spr_event_mux_ctrls(mmq_spr_event_mux_ctrls_sig), + .mas0_0_atsel(mas0_0_atsel), + .mas0_0_esel(mas0_0_esel), + .mas0_0_hes(mas0_0_hes), + .mas0_0_wq(mas0_0_wq), + .mas1_0_v(mas1_0_v), + .mas1_0_iprot(mas1_0_iprot), + .mas1_0_tid(mas1_0_tid), + .mas1_0_ind(mas1_0_ind), + .mas1_0_ts(mas1_0_ts), + .mas1_0_tsize(mas1_0_tsize), + .mas2_0_epn(mas2_0_epn), + .mas2_0_wimge(mas2_0_wimge), + .mas3_0_rpnl(mas3_0_rpnl), + .mas3_0_ubits(mas3_0_ubits), + .mas3_0_usxwr(mas3_0_usxwr), + .mas5_0_sgs(mas5_0_sgs), + .mas5_0_slpid(mas5_0_slpid), + .mas6_0_spid(mas6_0_spid), + .mas6_0_isize(mas6_0_isize), + .mas6_0_sind(mas6_0_sind), + .mas6_0_sas(mas6_0_sas), + .mas7_0_rpnu(mas7_0_rpnu), + .mas8_0_tgs(mas8_0_tgs), + .mas8_0_vf(mas8_0_vf), + .mas8_0_tlpid(mas8_0_tlpid), +`ifdef MM_THREADS2 + .mas0_1_atsel(mas0_1_atsel), + .mas0_1_esel(mas0_1_esel), + .mas0_1_hes(mas0_1_hes), + .mas0_1_wq(mas0_1_wq), + .mas1_1_v(mas1_1_v), + .mas1_1_iprot(mas1_1_iprot), + .mas1_1_tid(mas1_1_tid), + .mas1_1_ind(mas1_1_ind), + .mas1_1_ts(mas1_1_ts), + .mas1_1_tsize(mas1_1_tsize), + .mas2_1_epn(mas2_1_epn), + .mas2_1_wimge(mas2_1_wimge), + .mas3_1_rpnl(mas3_1_rpnl), + .mas3_1_ubits(mas3_1_ubits), + .mas3_1_usxwr(mas3_1_usxwr), + .mas5_1_sgs(mas5_1_sgs), + .mas5_1_slpid(mas5_1_slpid), + .mas6_1_spid(mas6_1_spid), + .mas6_1_isize(mas6_1_isize), + .mas6_1_sind(mas6_1_sind), + .mas6_1_sas(mas6_1_sas), + .mas7_1_rpnu(mas7_1_rpnu), + .mas8_1_tgs(mas8_1_tgs), + .mas8_1_vf(mas8_1_vf), + .mas8_1_tlpid(mas8_1_tlpid), +`endif + .tlb_mas0_esel(tlb_mas0_esel), + .tlb_mas1_v(tlb_mas1_v), + .tlb_mas1_iprot(tlb_mas1_iprot), + .tlb_mas1_tid(tlb_mas1_tid), + .tlb_mas1_tid_error(tlb_mas1_tid_error), + .tlb_mas1_ind(tlb_mas1_ind), + .tlb_mas1_ts(tlb_mas1_ts), + .tlb_mas1_ts_error(tlb_mas1_ts_error), + .tlb_mas1_tsize(tlb_mas1_tsize), + .tlb_mas2_epn(tlb_mas2_epn), + .tlb_mas2_epn_error(tlb_mas2_epn_error), + .tlb_mas2_wimge(tlb_mas2_wimge), + .tlb_mas3_rpnl(tlb_mas3_rpnl), + .tlb_mas3_ubits(tlb_mas3_ubits), + .tlb_mas3_usxwr(tlb_mas3_usxwr), + .tlb_mas7_rpnu(tlb_mas7_rpnu), + .tlb_mas8_tgs(tlb_mas8_tgs), + .tlb_mas8_vf(tlb_mas8_vf), + .tlb_mas8_tlpid(tlb_mas8_tlpid), + + .tlb_mmucr1_een(tlb_mmucr1_een), + .tlb_mmucr1_we(tlb_mmucr1_we), + .tlb_mmucr3_thdid(tlb_mmucr3_thdid), + .tlb_mmucr3_resvattr(tlb_mmucr3_resvattr), + .tlb_mmucr3_wlc(tlb_mmucr3_wlc), + .tlb_mmucr3_class(tlb_mmucr3_class), + .tlb_mmucr3_extclass(tlb_mmucr3_extclass), + .tlb_mmucr3_rc(tlb_mmucr3_rc), + .tlb_mmucr3_x(tlb_mmucr3_x), + .tlb_mas_tlbre(tlb_mas_tlbre), + .tlb_mas_tlbsx_hit(tlb_mas_tlbsx_hit), + .tlb_mas_tlbsx_miss(tlb_mas_tlbsx_miss), + .tlb_mas_dtlb_error(tlb_mas_dtlb_error), + .tlb_mas_itlb_error(tlb_mas_itlb_error), + .tlb_mas_thdid(tlb_mas_thdid), + + .mmucsr0_tlb0fi(mmucsr0_tlb0fi), + .mmq_inval_tlb0fi_done(mmq_inval_tlb0fi_done), + + .lrat_mmucr3_x(lrat_mmucr3_x), + .lrat_mas0_esel(lrat_mas0_esel), + .lrat_mas1_v(lrat_mas1_v), + .lrat_mas1_tsize(lrat_mas1_tsize), + .lrat_mas2_epn(lrat_mas2_epn), + .lrat_mas3_rpnl(lrat_mas3_rpnl), + .lrat_mas7_rpnu(lrat_mas7_rpnu), + .lrat_mas8_tlpid(lrat_mas8_tlpid), + .lrat_mas_tlbre(lrat_mas_tlbre), + .lrat_mas_tlbsx_hit(lrat_mas_tlbsx_hit), + .lrat_mas_tlbsx_miss(lrat_mas_tlbsx_miss), + .lrat_mas_thdid(lrat_mas_thdid), + .lrat_tag4_hit_entry(lrat_tag4_hit_entry), + + .tlb_lper_lpn(tlb_lper_lpn), + .tlb_lper_lps(tlb_lper_lps), + .tlb_lper_we(tlb_lper_we), + + .lpidr(lpidr_sig), + .ac_an_lpar_id(ac_an_lpar_id_sig), + + .spr_dbg_match_64b(spr_dbg_match_64b), + .spr_dbg_match_any_mmu(spr_dbg_match_any_mmu), + .spr_dbg_match_any_mas(spr_dbg_match_any_mas), + .spr_dbg_match_pid(spr_dbg_match_pid), + .spr_dbg_match_lpidr(spr_dbg_match_lpidr), + .spr_dbg_match_mmucr0(spr_dbg_match_mmucr0), + .spr_dbg_match_mmucr1(spr_dbg_match_mmucr1), + .spr_dbg_match_mmucr2(spr_dbg_match_mmucr2), + .spr_dbg_match_mmucr3(spr_dbg_match_mmucr3), + + .spr_dbg_match_mmucsr0(spr_dbg_match_mmucsr0), + .spr_dbg_match_mmucfg(spr_dbg_match_mmucfg), + .spr_dbg_match_tlb0cfg(spr_dbg_match_tlb0cfg), + .spr_dbg_match_tlb0ps(spr_dbg_match_tlb0ps), + .spr_dbg_match_lratcfg(spr_dbg_match_lratcfg), + .spr_dbg_match_lratps(spr_dbg_match_lratps), + .spr_dbg_match_eptcfg(spr_dbg_match_eptcfg), + .spr_dbg_match_lper(spr_dbg_match_lper), + .spr_dbg_match_lperu(spr_dbg_match_lperu), + + .spr_dbg_match_mas0(spr_dbg_match_mas0), + .spr_dbg_match_mas1(spr_dbg_match_mas1), + .spr_dbg_match_mas2(spr_dbg_match_mas2), + .spr_dbg_match_mas2u(spr_dbg_match_mas2u), + .spr_dbg_match_mas3(spr_dbg_match_mas3), + .spr_dbg_match_mas4(spr_dbg_match_mas4), + .spr_dbg_match_mas5(spr_dbg_match_mas5), + .spr_dbg_match_mas6(spr_dbg_match_mas6), + .spr_dbg_match_mas7(spr_dbg_match_mas7), + .spr_dbg_match_mas8(spr_dbg_match_mas8), + .spr_dbg_match_mas01_64b(spr_dbg_match_mas01_64b), + .spr_dbg_match_mas56_64b(spr_dbg_match_mas56_64b), + .spr_dbg_match_mas73_64b(spr_dbg_match_mas73_64b), + .spr_dbg_match_mas81_64b(spr_dbg_match_mas81_64b), + + .spr_dbg_slowspr_val_int(spr_dbg_slowspr_val_int), + .spr_dbg_slowspr_rw_int(spr_dbg_slowspr_rw_int), + .spr_dbg_slowspr_etid_int(spr_dbg_slowspr_etid_int), + .spr_dbg_slowspr_addr_int(spr_dbg_slowspr_addr_int), + .spr_dbg_slowspr_val_out(spr_dbg_slowspr_val_out), + .spr_dbg_slowspr_done_out(spr_dbg_slowspr_done_out), + .spr_dbg_slowspr_data_out(spr_dbg_slowspr_data_out), + + .xu_mm_slowspr_val(slowspr_val_in), + .xu_mm_slowspr_rw(slowspr_rw_in), + .xu_mm_slowspr_etid(slowspr_etid_in), + .xu_mm_slowspr_addr(slowspr_addr_in), + .xu_mm_slowspr_data(slowspr_data_in), + .xu_mm_slowspr_done(slowspr_done_in), + + .mm_iu_slowspr_val(slowspr_val_out), + .mm_iu_slowspr_rw(slowspr_rw_out), + .mm_iu_slowspr_etid(slowspr_etid_out), + .mm_iu_slowspr_addr(slowspr_addr_out), + .mm_iu_slowspr_data(slowspr_data_out), + + .mm_iu_slowspr_done(slowspr_done_out) + +); +// End of mmq_spr component instantiation + + +//--------------------------------------------------------------------- +// Debug Trace component instantiation +//--------------------------------------------------------------------- + +//work.mmq_dbg #(.`THREADS(`THREADS), .`THDID_WIDTH(`THDID_WIDTH), .`TLB_TAG_WIDTH(`TLB_TAG_WIDTH), .`EXPAND_TYPE(`EXPAND_TYPE)) mmq_dbg( +mmq_dbg mmq_dbg( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .pc_func_slp_sl_thold_2(pc_func_slp_sl_thold_2[0]), + .pc_func_slp_nsl_thold_2(pc_func_slp_nsl_thold_2), + .pc_sg_2(pc_sg_2[0]), + .pc_fce_2(pc_fce_2), + .tc_ac_ccflush_dc(tc_ac_ccflush_dc), + .lcb_clkoff_dc_b(lcb_clkoff_dc_b), + .lcb_act_dis_dc(lcb_act_dis_dc), + .lcb_d_mode_dc(lcb_d_mode_dc), + .lcb_delay_lclkr_dc(lcb_delay_lclkr_dc[0]), + .lcb_mpw1_dc_b(lcb_mpw1_dc_b[0]), + .lcb_mpw2_dc_b(lcb_mpw2_dc_b), + .scan_in(siv_1[mmq_dbg_offset]), + .scan_out(sov_1[mmq_dbg_offset]), + + .mmucr2(mmucr2_sig[8:11]), + .pc_mm_trace_bus_enable(pc_mm_trace_bus_enable), + .pc_mm_debug_mux1_ctrls(pc_mm_debug_mux1_ctrls), + + .debug_bus_in(debug_bus_in), + .debug_bus_out(debug_bus_out), + +// Instruction Trace (HTM) Control Signals: +// 0 - ac_an_coretrace_first_valid +// 1 - ac_an_coretrace_valid +// 2:3 - ac_an_coretrace_type[0:1] + .coretrace_ctrls_in(coretrace_ctrls_in), // input [0:3] + .coretrace_ctrls_out(coretrace_ctrls_out), // output [0:3] + + .spr_dbg_match_64b(spr_dbg_match_64b), + .spr_dbg_match_any_mmu(spr_dbg_match_any_mmu), + .spr_dbg_match_any_mas(spr_dbg_match_any_mas), + .spr_dbg_match_pid(spr_dbg_match_pid), + .spr_dbg_match_lpidr(spr_dbg_match_lpidr), + .spr_dbg_match_mmucr0(spr_dbg_match_mmucr0), + .spr_dbg_match_mmucr1(spr_dbg_match_mmucr1), + .spr_dbg_match_mmucr2(spr_dbg_match_mmucr2), + .spr_dbg_match_mmucr3(spr_dbg_match_mmucr3), + + .spr_dbg_match_mmucsr0(spr_dbg_match_mmucsr0), + .spr_dbg_match_mmucfg(spr_dbg_match_mmucfg), + .spr_dbg_match_tlb0cfg(spr_dbg_match_tlb0cfg), + .spr_dbg_match_tlb0ps(spr_dbg_match_tlb0ps), + .spr_dbg_match_lratcfg(spr_dbg_match_lratcfg), + .spr_dbg_match_lratps(spr_dbg_match_lratps), + .spr_dbg_match_eptcfg(spr_dbg_match_eptcfg), + .spr_dbg_match_lper(spr_dbg_match_lper), + .spr_dbg_match_lperu(spr_dbg_match_lperu), + + .spr_dbg_match_mas0(spr_dbg_match_mas0), + .spr_dbg_match_mas1(spr_dbg_match_mas1), + .spr_dbg_match_mas2(spr_dbg_match_mas2), + .spr_dbg_match_mas2u(spr_dbg_match_mas2u), + .spr_dbg_match_mas3(spr_dbg_match_mas3), + .spr_dbg_match_mas4(spr_dbg_match_mas4), + .spr_dbg_match_mas5(spr_dbg_match_mas5), + .spr_dbg_match_mas6(spr_dbg_match_mas6), + .spr_dbg_match_mas7(spr_dbg_match_mas7), + .spr_dbg_match_mas8(spr_dbg_match_mas8), + .spr_dbg_match_mas01_64b(spr_dbg_match_mas01_64b), + .spr_dbg_match_mas56_64b(spr_dbg_match_mas56_64b), + .spr_dbg_match_mas73_64b(spr_dbg_match_mas73_64b), + .spr_dbg_match_mas81_64b(spr_dbg_match_mas81_64b), + + .spr_dbg_slowspr_val_int(spr_dbg_slowspr_val_int), + .spr_dbg_slowspr_rw_int(spr_dbg_slowspr_rw_int), + .spr_dbg_slowspr_etid_int(spr_dbg_slowspr_etid_int), + .spr_dbg_slowspr_addr_int(spr_dbg_slowspr_addr_int), + .spr_dbg_slowspr_val_out(spr_dbg_slowspr_val_out), + .spr_dbg_slowspr_done_out(spr_dbg_slowspr_done_out), + .spr_dbg_slowspr_data_out(spr_dbg_slowspr_data_out), + .inval_dbg_seq_q(inval_dbg_seq_q), + .inval_dbg_seq_idle(inval_dbg_seq_idle), + .inval_dbg_seq_snoop_inprogress(inval_dbg_seq_snoop_inprogress), + .inval_dbg_seq_snoop_done(inval_dbg_seq_snoop_done), + .inval_dbg_seq_local_done(inval_dbg_seq_local_done), + .inval_dbg_seq_tlb0fi_done(inval_dbg_seq_tlb0fi_done), + .inval_dbg_seq_tlbwe_snoop_done(inval_dbg_seq_tlbwe_snoop_done), + .inval_dbg_ex6_valid(inval_dbg_ex6_valid), + .inval_dbg_ex6_thdid(inval_dbg_ex6_thdid), + .inval_dbg_ex6_ttype(inval_dbg_ex6_ttype), + .inval_dbg_snoop_forme(inval_dbg_snoop_forme), + .inval_dbg_snoop_local_reject(inval_dbg_snoop_local_reject), + .inval_dbg_an_ac_back_inv_q(inval_dbg_an_ac_back_inv_q), + .inval_dbg_an_ac_back_inv_lpar_id_q(inval_dbg_an_ac_back_inv_lpar_id_q), + .inval_dbg_an_ac_back_inv_addr_q(inval_dbg_an_ac_back_inv_addr_q), + .inval_dbg_snoop_valid_q(inval_dbg_snoop_valid_q), + .inval_dbg_snoop_ack_q(inval_dbg_snoop_ack_q), + .inval_dbg_snoop_attr_q(inval_dbg_snoop_attr_q), + .inval_dbg_snoop_attr_tlb_spec_q(inval_dbg_snoop_attr_tlb_spec_q), + .inval_dbg_snoop_vpn_q(inval_dbg_snoop_vpn_q), + .inval_dbg_lsu_tokens_q(inval_dbg_lsu_tokens_q), + .tlb_req_dbg_ierat_iu5_valid_q(tlb_req_dbg_ierat_iu5_valid_q), + .tlb_req_dbg_ierat_iu5_thdid(tlb_req_dbg_ierat_iu5_thdid), + .tlb_req_dbg_ierat_iu5_state_q(tlb_req_dbg_ierat_iu5_state_q), + .tlb_req_dbg_ierat_inptr_q(tlb_req_dbg_ierat_inptr_q), + .tlb_req_dbg_ierat_outptr_q(tlb_req_dbg_ierat_outptr_q), + .tlb_req_dbg_ierat_req_valid_q(tlb_req_dbg_ierat_req_valid_q), + .tlb_req_dbg_ierat_req_nonspec_q(tlb_req_dbg_ierat_req_nonspec_q), + .tlb_req_dbg_ierat_req_thdid(tlb_req_dbg_ierat_req_thdid), + .tlb_req_dbg_ierat_req_dup_q(tlb_req_dbg_ierat_req_dup_q), + .tlb_req_dbg_derat_ex6_valid_q(tlb_req_dbg_derat_ex6_valid_q), + .tlb_req_dbg_derat_ex6_thdid(tlb_req_dbg_derat_ex6_thdid), + .tlb_req_dbg_derat_ex6_state_q(tlb_req_dbg_derat_ex6_state_q), + .tlb_req_dbg_derat_inptr_q(tlb_req_dbg_derat_inptr_q), + .tlb_req_dbg_derat_outptr_q(tlb_req_dbg_derat_outptr_q), + .tlb_req_dbg_derat_req_valid_q(tlb_req_dbg_derat_req_valid_q), + .tlb_req_dbg_derat_req_thdid(tlb_req_dbg_derat_req_thdid), + .tlb_req_dbg_derat_req_ttype_q(tlb_req_dbg_derat_req_ttype_q), + .tlb_req_dbg_derat_req_dup_q(tlb_req_dbg_derat_req_dup_q), + + .tlb_ctl_dbg_seq_q(tlb_ctl_dbg_seq_q), + .tlb_ctl_dbg_seq_idle(tlb_ctl_dbg_seq_idle), + .tlb_ctl_dbg_seq_any_done_sig(tlb_ctl_dbg_seq_any_done_sig), + .tlb_ctl_dbg_seq_abort(tlb_ctl_dbg_seq_abort), + .tlb_ctl_dbg_any_tlb_req_sig(tlb_ctl_dbg_any_tlb_req_sig), + .tlb_ctl_dbg_any_req_taken_sig(tlb_ctl_dbg_any_req_taken_sig), + .tlb_ctl_dbg_tag0_valid(tlb_ctl_dbg_tag0_valid), + .tlb_ctl_dbg_tag0_thdid(tlb_ctl_dbg_tag0_thdid), + .tlb_ctl_dbg_tag0_type(tlb_ctl_dbg_tag0_type), + .tlb_ctl_dbg_tag0_wq(tlb_ctl_dbg_tag0_wq), + .tlb_ctl_dbg_tag0_gs(tlb_ctl_dbg_tag0_gs), + .tlb_ctl_dbg_tag0_pr(tlb_ctl_dbg_tag0_pr), + .tlb_ctl_dbg_tag0_atsel(tlb_ctl_dbg_tag0_atsel), + .tlb_ctl_dbg_tag5_tlb_write_q(tlb_ctl_dbg_tag5_tlb_write_q), + .tlb_ctl_dbg_resv_valid(tlb_ctl_dbg_resv_valid), + .tlb_ctl_dbg_set_resv(tlb_ctl_dbg_set_resv), + .tlb_ctl_dbg_resv_match_vec_q(tlb_ctl_dbg_resv_match_vec_q), + .tlb_ctl_dbg_any_tag_flush_sig(tlb_ctl_dbg_any_tag_flush_sig), + .tlb_ctl_dbg_resv0_tag0_lpid_match(tlb_ctl_dbg_resv0_tag0_lpid_match), + .tlb_ctl_dbg_resv0_tag0_pid_match(tlb_ctl_dbg_resv0_tag0_pid_match), + .tlb_ctl_dbg_resv0_tag0_as_snoop_match(tlb_ctl_dbg_resv0_tag0_as_snoop_match), + .tlb_ctl_dbg_resv0_tag0_gs_snoop_match(tlb_ctl_dbg_resv0_tag0_gs_snoop_match), + .tlb_ctl_dbg_resv0_tag0_as_tlbwe_match(tlb_ctl_dbg_resv0_tag0_as_tlbwe_match), + .tlb_ctl_dbg_resv0_tag0_gs_tlbwe_match(tlb_ctl_dbg_resv0_tag0_gs_tlbwe_match), + .tlb_ctl_dbg_resv0_tag0_ind_match(tlb_ctl_dbg_resv0_tag0_ind_match), + .tlb_ctl_dbg_resv0_tag0_epn_loc_match(tlb_ctl_dbg_resv0_tag0_epn_loc_match), + .tlb_ctl_dbg_resv0_tag0_epn_glob_match(tlb_ctl_dbg_resv0_tag0_epn_glob_match), + .tlb_ctl_dbg_resv0_tag0_class_match(tlb_ctl_dbg_resv0_tag0_class_match), + .tlb_ctl_dbg_resv1_tag0_lpid_match(tlb_ctl_dbg_resv1_tag0_lpid_match), + .tlb_ctl_dbg_resv1_tag0_pid_match(tlb_ctl_dbg_resv1_tag0_pid_match), + .tlb_ctl_dbg_resv1_tag0_as_snoop_match(tlb_ctl_dbg_resv1_tag0_as_snoop_match), + .tlb_ctl_dbg_resv1_tag0_gs_snoop_match(tlb_ctl_dbg_resv1_tag0_gs_snoop_match), + .tlb_ctl_dbg_resv1_tag0_as_tlbwe_match(tlb_ctl_dbg_resv1_tag0_as_tlbwe_match), + .tlb_ctl_dbg_resv1_tag0_gs_tlbwe_match(tlb_ctl_dbg_resv1_tag0_gs_tlbwe_match), + .tlb_ctl_dbg_resv1_tag0_ind_match(tlb_ctl_dbg_resv1_tag0_ind_match), + .tlb_ctl_dbg_resv1_tag0_epn_loc_match(tlb_ctl_dbg_resv1_tag0_epn_loc_match), + .tlb_ctl_dbg_resv1_tag0_epn_glob_match(tlb_ctl_dbg_resv1_tag0_epn_glob_match), + .tlb_ctl_dbg_resv1_tag0_class_match(tlb_ctl_dbg_resv1_tag0_class_match), + .tlb_ctl_dbg_resv2_tag0_lpid_match(tlb_ctl_dbg_resv2_tag0_lpid_match), + .tlb_ctl_dbg_resv2_tag0_pid_match(tlb_ctl_dbg_resv2_tag0_pid_match), + .tlb_ctl_dbg_resv2_tag0_as_snoop_match(tlb_ctl_dbg_resv2_tag0_as_snoop_match), + .tlb_ctl_dbg_resv2_tag0_gs_snoop_match(tlb_ctl_dbg_resv2_tag0_gs_snoop_match), + .tlb_ctl_dbg_resv2_tag0_as_tlbwe_match(tlb_ctl_dbg_resv2_tag0_as_tlbwe_match), + .tlb_ctl_dbg_resv2_tag0_gs_tlbwe_match(tlb_ctl_dbg_resv2_tag0_gs_tlbwe_match), + .tlb_ctl_dbg_resv2_tag0_ind_match(tlb_ctl_dbg_resv2_tag0_ind_match), + .tlb_ctl_dbg_resv2_tag0_epn_loc_match(tlb_ctl_dbg_resv2_tag0_epn_loc_match), + .tlb_ctl_dbg_resv2_tag0_epn_glob_match(tlb_ctl_dbg_resv2_tag0_epn_glob_match), + .tlb_ctl_dbg_resv2_tag0_class_match(tlb_ctl_dbg_resv2_tag0_class_match), + .tlb_ctl_dbg_resv3_tag0_lpid_match(tlb_ctl_dbg_resv3_tag0_lpid_match), + .tlb_ctl_dbg_resv3_tag0_pid_match(tlb_ctl_dbg_resv3_tag0_pid_match), + .tlb_ctl_dbg_resv3_tag0_as_snoop_match(tlb_ctl_dbg_resv3_tag0_as_snoop_match), + .tlb_ctl_dbg_resv3_tag0_gs_snoop_match(tlb_ctl_dbg_resv3_tag0_gs_snoop_match), + .tlb_ctl_dbg_resv3_tag0_as_tlbwe_match(tlb_ctl_dbg_resv3_tag0_as_tlbwe_match), + .tlb_ctl_dbg_resv3_tag0_gs_tlbwe_match(tlb_ctl_dbg_resv3_tag0_gs_tlbwe_match), + .tlb_ctl_dbg_resv3_tag0_ind_match(tlb_ctl_dbg_resv3_tag0_ind_match), + .tlb_ctl_dbg_resv3_tag0_epn_loc_match(tlb_ctl_dbg_resv3_tag0_epn_loc_match), + .tlb_ctl_dbg_resv3_tag0_epn_glob_match(tlb_ctl_dbg_resv3_tag0_epn_glob_match), + .tlb_ctl_dbg_resv3_tag0_class_match(tlb_ctl_dbg_resv3_tag0_class_match), + .tlb_ctl_dbg_clr_resv_q(tlb_ctl_dbg_clr_resv_q), + .tlb_ctl_dbg_clr_resv_terms(tlb_ctl_dbg_clr_resv_terms), + .tlb_cmp_dbg_tag4(tlb_cmp_dbg_tag4), + .tlb_cmp_dbg_tag4_wayhit(tlb_cmp_dbg_tag4_wayhit), + .tlb_cmp_dbg_addr4(tlb_cmp_dbg_addr4), + .tlb_cmp_dbg_tag4_way(tlb_cmp_dbg_tag4_way), + .tlb_cmp_dbg_tag4_parerr(tlb_cmp_dbg_tag4_parerr), + .tlb_cmp_dbg_tag4_lru_dataout_q(tlb_cmp_dbg_tag4_lru_dataout_q), + .tlb_cmp_dbg_tag5_tlb_datain_q(tlb_cmp_dbg_tag5_tlb_datain_q), + .tlb_cmp_dbg_tag5_lru_datain_q(tlb_cmp_dbg_tag5_lru_datain_q), + .tlb_cmp_dbg_tag5_lru_write(tlb_cmp_dbg_tag5_lru_write), + .tlb_cmp_dbg_tag5_any_exception(tlb_cmp_dbg_tag5_any_exception), + .tlb_cmp_dbg_tag5_except_type_q(tlb_cmp_dbg_tag5_except_type_q), + .tlb_cmp_dbg_tag5_except_thdid_q(tlb_cmp_dbg_tag5_except_thdid_q), + .tlb_cmp_dbg_tag5_erat_rel_val(tlb_cmp_dbg_tag5_erat_rel_val), + .tlb_cmp_dbg_tag5_erat_rel_data(tlb_cmp_dbg_tag5_erat_rel_data), + .tlb_cmp_dbg_erat_dup_q(tlb_cmp_dbg_erat_dup_q), + .tlb_cmp_dbg_addr_enable(tlb_cmp_dbg_addr_enable), + .tlb_cmp_dbg_pgsize_enable(tlb_cmp_dbg_pgsize_enable), + .tlb_cmp_dbg_class_enable(tlb_cmp_dbg_class_enable), + .tlb_cmp_dbg_extclass_enable(tlb_cmp_dbg_extclass_enable), + .tlb_cmp_dbg_state_enable(tlb_cmp_dbg_state_enable), + .tlb_cmp_dbg_thdid_enable(tlb_cmp_dbg_thdid_enable), + .tlb_cmp_dbg_pid_enable(tlb_cmp_dbg_pid_enable), + .tlb_cmp_dbg_lpid_enable(tlb_cmp_dbg_lpid_enable), + .tlb_cmp_dbg_ind_enable(tlb_cmp_dbg_ind_enable), + .tlb_cmp_dbg_iprot_enable(tlb_cmp_dbg_iprot_enable), + .tlb_cmp_dbg_way0_entry_v(tlb_cmp_dbg_way0_entry_v), + .tlb_cmp_dbg_way0_addr_match(tlb_cmp_dbg_way0_addr_match), + .tlb_cmp_dbg_way0_pgsize_match(tlb_cmp_dbg_way0_pgsize_match), + .tlb_cmp_dbg_way0_class_match(tlb_cmp_dbg_way0_class_match), + .tlb_cmp_dbg_way0_extclass_match(tlb_cmp_dbg_way0_extclass_match), + .tlb_cmp_dbg_way0_state_match(tlb_cmp_dbg_way0_state_match), + .tlb_cmp_dbg_way0_thdid_match(tlb_cmp_dbg_way0_thdid_match), + .tlb_cmp_dbg_way0_pid_match(tlb_cmp_dbg_way0_pid_match), + .tlb_cmp_dbg_way0_lpid_match(tlb_cmp_dbg_way0_lpid_match), + .tlb_cmp_dbg_way0_ind_match(tlb_cmp_dbg_way0_ind_match), + .tlb_cmp_dbg_way0_iprot_match(tlb_cmp_dbg_way0_iprot_match), + .tlb_cmp_dbg_way1_entry_v(tlb_cmp_dbg_way1_entry_v), + .tlb_cmp_dbg_way1_addr_match(tlb_cmp_dbg_way1_addr_match), + .tlb_cmp_dbg_way1_pgsize_match(tlb_cmp_dbg_way1_pgsize_match), + .tlb_cmp_dbg_way1_class_match(tlb_cmp_dbg_way1_class_match), + .tlb_cmp_dbg_way1_extclass_match(tlb_cmp_dbg_way1_extclass_match), + .tlb_cmp_dbg_way1_state_match(tlb_cmp_dbg_way1_state_match), + .tlb_cmp_dbg_way1_thdid_match(tlb_cmp_dbg_way1_thdid_match), + .tlb_cmp_dbg_way1_pid_match(tlb_cmp_dbg_way1_pid_match), + .tlb_cmp_dbg_way1_lpid_match(tlb_cmp_dbg_way1_lpid_match), + .tlb_cmp_dbg_way1_ind_match(tlb_cmp_dbg_way1_ind_match), + .tlb_cmp_dbg_way1_iprot_match(tlb_cmp_dbg_way1_iprot_match), + .tlb_cmp_dbg_way2_entry_v(tlb_cmp_dbg_way2_entry_v), + .tlb_cmp_dbg_way2_addr_match(tlb_cmp_dbg_way2_addr_match), + .tlb_cmp_dbg_way2_pgsize_match(tlb_cmp_dbg_way2_pgsize_match), + .tlb_cmp_dbg_way2_class_match(tlb_cmp_dbg_way2_class_match), + .tlb_cmp_dbg_way2_extclass_match(tlb_cmp_dbg_way2_extclass_match), + .tlb_cmp_dbg_way2_state_match(tlb_cmp_dbg_way2_state_match), + .tlb_cmp_dbg_way2_thdid_match(tlb_cmp_dbg_way2_thdid_match), + .tlb_cmp_dbg_way2_pid_match(tlb_cmp_dbg_way2_pid_match), + .tlb_cmp_dbg_way2_lpid_match(tlb_cmp_dbg_way2_lpid_match), + .tlb_cmp_dbg_way2_ind_match(tlb_cmp_dbg_way2_ind_match), + .tlb_cmp_dbg_way2_iprot_match(tlb_cmp_dbg_way2_iprot_match), + .tlb_cmp_dbg_way3_entry_v(tlb_cmp_dbg_way3_entry_v), + .tlb_cmp_dbg_way3_addr_match(tlb_cmp_dbg_way3_addr_match), + .tlb_cmp_dbg_way3_pgsize_match(tlb_cmp_dbg_way3_pgsize_match), + .tlb_cmp_dbg_way3_class_match(tlb_cmp_dbg_way3_class_match), + .tlb_cmp_dbg_way3_extclass_match(tlb_cmp_dbg_way3_extclass_match), + .tlb_cmp_dbg_way3_state_match(tlb_cmp_dbg_way3_state_match), + .tlb_cmp_dbg_way3_thdid_match(tlb_cmp_dbg_way3_thdid_match), + .tlb_cmp_dbg_way3_pid_match(tlb_cmp_dbg_way3_pid_match), + .tlb_cmp_dbg_way3_lpid_match(tlb_cmp_dbg_way3_lpid_match), + .tlb_cmp_dbg_way3_ind_match(tlb_cmp_dbg_way3_ind_match), + .tlb_cmp_dbg_way3_iprot_match(tlb_cmp_dbg_way3_iprot_match), + + .lrat_dbg_tag1_addr_enable(lrat_dbg_tag1_addr_enable), + .lrat_dbg_tag2_matchline_q(lrat_dbg_tag2_matchline_q), + .lrat_dbg_entry0_addr_match(lrat_dbg_entry0_addr_match), + .lrat_dbg_entry0_lpid_match(lrat_dbg_entry0_lpid_match), + .lrat_dbg_entry0_entry_v(lrat_dbg_entry0_entry_v), + .lrat_dbg_entry0_entry_x(lrat_dbg_entry0_entry_x), + .lrat_dbg_entry0_size(lrat_dbg_entry0_size), + .lrat_dbg_entry1_addr_match(lrat_dbg_entry1_addr_match), + .lrat_dbg_entry1_lpid_match(lrat_dbg_entry1_lpid_match), + .lrat_dbg_entry1_entry_v(lrat_dbg_entry1_entry_v), + .lrat_dbg_entry1_entry_x(lrat_dbg_entry1_entry_x), + .lrat_dbg_entry1_size(lrat_dbg_entry1_size), + .lrat_dbg_entry2_addr_match(lrat_dbg_entry2_addr_match), + .lrat_dbg_entry2_lpid_match(lrat_dbg_entry2_lpid_match), + .lrat_dbg_entry2_entry_v(lrat_dbg_entry2_entry_v), + .lrat_dbg_entry2_entry_x(lrat_dbg_entry2_entry_x), + .lrat_dbg_entry2_size(lrat_dbg_entry2_size), + .lrat_dbg_entry3_addr_match(lrat_dbg_entry3_addr_match), + .lrat_dbg_entry3_lpid_match(lrat_dbg_entry3_lpid_match), + .lrat_dbg_entry3_entry_v(lrat_dbg_entry3_entry_v), + .lrat_dbg_entry3_entry_x(lrat_dbg_entry3_entry_x), + .lrat_dbg_entry3_size(lrat_dbg_entry3_size), + .lrat_dbg_entry4_addr_match(lrat_dbg_entry4_addr_match), + .lrat_dbg_entry4_lpid_match(lrat_dbg_entry4_lpid_match), + .lrat_dbg_entry4_entry_v(lrat_dbg_entry4_entry_v), + .lrat_dbg_entry4_entry_x(lrat_dbg_entry4_entry_x), + .lrat_dbg_entry4_size(lrat_dbg_entry4_size), + .lrat_dbg_entry5_addr_match(lrat_dbg_entry5_addr_match), + .lrat_dbg_entry5_lpid_match(lrat_dbg_entry5_lpid_match), + .lrat_dbg_entry5_entry_v(lrat_dbg_entry5_entry_v), + .lrat_dbg_entry5_entry_x(lrat_dbg_entry5_entry_x), + .lrat_dbg_entry5_size(lrat_dbg_entry5_size), + .lrat_dbg_entry6_addr_match(lrat_dbg_entry6_addr_match), + .lrat_dbg_entry6_lpid_match(lrat_dbg_entry6_lpid_match), + .lrat_dbg_entry6_entry_v(lrat_dbg_entry6_entry_v), + .lrat_dbg_entry6_entry_x(lrat_dbg_entry6_entry_x), + .lrat_dbg_entry6_size(lrat_dbg_entry6_size), + .lrat_dbg_entry7_addr_match(lrat_dbg_entry7_addr_match), + .lrat_dbg_entry7_lpid_match(lrat_dbg_entry7_lpid_match), + .lrat_dbg_entry7_entry_v(lrat_dbg_entry7_entry_v), + .lrat_dbg_entry7_entry_x(lrat_dbg_entry7_entry_x), + .lrat_dbg_entry7_size(lrat_dbg_entry7_size), + .htw_dbg_seq_idle(htw_dbg_seq_idle), + .htw_dbg_pte0_seq_idle(htw_dbg_pte0_seq_idle), + .htw_dbg_pte1_seq_idle(htw_dbg_pte1_seq_idle), + .htw_dbg_seq_q(htw_dbg_seq_q), + .htw_dbg_inptr_q(htw_dbg_inptr_q), + .htw_dbg_pte0_seq_q(htw_dbg_pte0_seq_q), + .htw_dbg_pte1_seq_q(htw_dbg_pte1_seq_q), + .htw_dbg_ptereload_ptr_q(htw_dbg_ptereload_ptr_q), + .htw_dbg_lsuptr_q(htw_dbg_lsuptr_q), + .htw_dbg_req_valid_q(htw_dbg_req_valid_q), + .htw_dbg_resv_valid_vec(htw_dbg_resv_valid_vec), + .htw_dbg_tag4_clr_resv_q(htw_dbg_tag4_clr_resv_q), + .htw_dbg_tag4_clr_resv_terms(htw_dbg_tag4_clr_resv_terms), + .htw_dbg_pte0_score_ptr_q(htw_dbg_pte0_score_ptr_q), + .htw_dbg_pte0_score_cl_offset_q(htw_dbg_pte0_score_cl_offset_q), + .htw_dbg_pte0_score_error_q(htw_dbg_pte0_score_error_q), + .htw_dbg_pte0_score_qwbeat_q(htw_dbg_pte0_score_qwbeat_q), + .htw_dbg_pte0_score_pending_q(htw_dbg_pte0_score_pending_q), + .htw_dbg_pte0_score_ibit_q(htw_dbg_pte0_score_ibit_q), + .htw_dbg_pte0_score_dataval_q(htw_dbg_pte0_score_dataval_q), + .htw_dbg_pte0_reld_for_me_tm1(htw_dbg_pte0_reld_for_me_tm1), + .htw_dbg_pte1_score_ptr_q(htw_dbg_pte1_score_ptr_q), + .htw_dbg_pte1_score_cl_offset_q(htw_dbg_pte1_score_cl_offset_q), + .htw_dbg_pte1_score_error_q(htw_dbg_pte1_score_error_q), + .htw_dbg_pte1_score_qwbeat_q(htw_dbg_pte1_score_qwbeat_q), + .htw_dbg_pte1_score_pending_q(htw_dbg_pte1_score_pending_q), + .htw_dbg_pte1_score_ibit_q(htw_dbg_pte1_score_ibit_q), + .htw_dbg_pte1_score_dataval_q(htw_dbg_pte1_score_dataval_q), + .htw_dbg_pte1_reld_for_me_tm1(htw_dbg_pte1_reld_for_me_tm1), + + .mm_xu_lsu_req(mm_xu_lsu_req_sig[0:`THREADS - 1]), + .mm_xu_lsu_ttype(mm_xu_lsu_ttype_sig), + .mm_xu_lsu_wimge(mm_xu_lsu_wimge_sig), + .mm_xu_lsu_u(mm_xu_lsu_u_sig), + .mm_xu_lsu_addr(mm_xu_lsu_addr_sig), + .mm_xu_lsu_lpid(mm_xu_lsu_lpid_sig), + .mm_xu_lsu_gs(mm_xu_lsu_gs_sig), + .mm_xu_lsu_ind(mm_xu_lsu_ind_sig), + .mm_xu_lsu_lbit(mm_xu_lsu_lbit_sig), + .xu_mm_lsu_token(xu_mm_lsu_token), + .tlb_mas_tlbre(tlb_mas_tlbre), + .tlb_mas_tlbsx_hit(tlb_mas_tlbsx_hit), + .tlb_mas_tlbsx_miss(tlb_mas_tlbsx_miss), + .tlb_mas_dtlb_error(tlb_mas_dtlb_error), + .tlb_mas_itlb_error(tlb_mas_itlb_error), + .tlb_mas_thdid(tlb_mas_thdid_dbg), + .lrat_mas_tlbre(lrat_mas_tlbre), + .lrat_mas_tlbsx_hit(lrat_mas_tlbsx_hit), + .lrat_mas_tlbsx_miss(lrat_mas_tlbsx_miss), + .lrat_mas_thdid(lrat_mas_thdid_dbg), + .lrat_tag3_hit_status(lrat_tag3_hit_status), + .lrat_tag3_hit_entry(lrat_tag3_hit_entry), + + .tlb_seq_ierat_req(tlb_seq_ierat_req), + .tlb_seq_derat_req(tlb_seq_derat_req), + .mm_xu_hold_req(mm_iu_hold_req_sig[0:`THREADS - 1]), + .xu_mm_hold_ack(iu_mm_hold_ack_sig[0:`THREADS - 1]), + .mm_xu_hold_done(mm_iu_hold_done_sig[0:`THREADS - 1]), + .mm_iu_barrier_done(mm_iu_tlbi_complete_sig[0:`THREADS - 1]), + .mmucsr0_tlb0fi(mmucsr0_tlb0fi), + .tlbwe_back_inv_valid(tlbwe_back_inv_valid_sig), + .tlbwe_back_inv_attr(tlbwe_back_inv_attr_sig[18:19]), + .xu_mm_lmq_stq_empty(xu_mm_lmq_stq_empty), + .iu_mm_lmq_empty(iu_mm_lmq_empty), + .mm_xu_eratmiss_done(mm_xu_eratmiss_done_sig[0:`THREADS - 1]), + .mm_xu_ex3_flush_req(mm_xu_ex3_flush_req_sig[0:`THREADS - 1]), + .mm_xu_illeg_instr(mm_xu_illeg_instr_sig[0:`THREADS - 1]), + .lrat_tag4_hit_status(lrat_tag4_hit_status), + .lrat_tag4_hit_entry(lrat_tag4_hit_entry), + .mm_xu_cr0_eq(mm_xu_cr0_eq_sig[0:`THREADS - 1]), + .mm_xu_cr0_eq_valid(mm_xu_cr0_eq_valid_sig[0:`THREADS - 1]), + .tlb_htw_req_valid(tlb_htw_req_valid), + .htw_lsu_req_valid(htw_lsu_req_valid), + .htw_dbg_lsu_thdid(htw_dbg_lsu_thdid), + .htw_lsu_ttype(htw_lsu_ttype), + .htw_lsu_addr(htw_lsu_addr), + .ptereload_req_taken(ptereload_req_taken), + .ptereload_req_pte(ptereload_req_pte) +); +// End of mmq_dbg component instantiation + + +//--------------------------------------------------------------------- +// Performance Event component instantiation +//--------------------------------------------------------------------- + +//work.mmq_perf #(.`THREADS(`THREADS), .`THDID_WIDTH(`THDID_WIDTH), .`EXPAND_TYPE(`EXPAND_TYPE)) mmq_perf( +mmq_perf mmq_perf( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .pc_func_sl_thold_2(pc_func_sl_thold_2[0]), + .pc_func_slp_nsl_thold_2(pc_func_slp_nsl_thold_2), + .pc_sg_2(pc_sg_2[0]), + .pc_fce_2(pc_fce_2), + .tc_ac_ccflush_dc(tc_ac_ccflush_dc), + .lcb_clkoff_dc_b(lcb_clkoff_dc_b), + .lcb_act_dis_dc(lcb_act_dis_dc), + .lcb_d_mode_dc(lcb_d_mode_dc), + .lcb_delay_lclkr_dc(lcb_delay_lclkr_dc[0]), + .lcb_mpw1_dc_b(lcb_mpw1_dc_b[0]), + .lcb_mpw2_dc_b(lcb_mpw2_dc_b), + .scan_in(siv_1[mmq_perf_offset]), + .scan_out(sov_1[mmq_perf_offset]), + .cp_flush_p1(cp_flush_p1), + + .xu_mm_msr_gs(xu_mm_msr_gs_perf), + .xu_mm_msr_pr(xu_mm_msr_pr_perf), + .xu_mm_ccr2_notlb_b(xu_mm_ccr2_notlb_b[2]), + +// count event inputs + .iu_mm_perf_itlb(iu_mm_perf_itlb_sig), + .lq_mm_perf_dtlb(lq_mm_perf_dtlb_sig), + .iu_mm_ierat_req_nonspec(iu_mm_ierat_req_nonspec), + .lq_mm_derat_req_nonspec(lq_mm_derat_req_nonspec), + + .tlb_cmp_perf_event_t0(tlb_cmp_perf_event_t0), + .tlb_cmp_perf_event_t1(tlb_cmp_perf_event_t1), + .tlb_cmp_perf_state(tlb_cmp_perf_state), + + .derat_req0_thdid(derat_req0_thdid_sig), + .derat_req0_valid(derat_req0_valid_sig), + .derat_req0_nonspec(derat_req0_nonspec_sig), + .derat_req1_thdid(derat_req1_thdid_sig), + .derat_req1_valid(derat_req1_valid_sig), + .derat_req1_nonspec(derat_req1_nonspec_sig), + .derat_req2_thdid(derat_req2_thdid_sig), + .derat_req2_valid(derat_req2_valid_sig), + .derat_req2_nonspec(derat_req2_nonspec_sig), + .derat_req3_thdid(derat_req3_thdid_sig), + .derat_req3_valid(derat_req3_valid_sig), + .derat_req3_nonspec(derat_req3_nonspec_sig), + .ierat_req0_thdid(ierat_req0_thdid_sig), + .ierat_req0_valid(ierat_req0_valid_sig), + .ierat_req0_nonspec(ierat_req0_nonspec_sig), + .ierat_req1_thdid(ierat_req1_thdid_sig), + .ierat_req1_valid(ierat_req1_valid_sig), + .ierat_req1_nonspec(ierat_req1_nonspec_sig), + .ierat_req2_thdid(ierat_req2_thdid_sig), + .ierat_req2_valid(ierat_req2_valid_sig), + .ierat_req2_nonspec(ierat_req2_nonspec_sig), + .ierat_req3_thdid(ierat_req3_thdid_sig), + .ierat_req3_valid(ierat_req3_valid_sig), + .ierat_req3_nonspec(ierat_req3_nonspec_sig), + .ierat_req_taken(ierat_req_taken), + .derat_req_taken(derat_req_taken), + + .tlb_tag0_thdid(tlb_tag0_thdid), + .tlb_tag0_type(tlb_tag0_type[0:1]), + .tlb_tag0_nonspec(tlb_tag0_nonspec), + .tlb_tag4_nonspec(tlb_tag4_nonspec), + .tlb_seq_idle(tlb_seq_idle), + + .inval_perf_tlbilx(inval_perf_tlbilx), + .inval_perf_tlbivax(inval_perf_tlbivax), + .inval_perf_tlbivax_snoop(inval_perf_tlbivax_snoop), + .inval_perf_tlb_flush(inval_perf_tlb_flush), + + .htw_req0_valid(htw_req0_valid), + .htw_req0_thdid(htw_req0_thdid), + .htw_req0_type(htw_req0_type), + .htw_req1_valid(htw_req1_valid), + .htw_req1_thdid(htw_req1_thdid), + .htw_req1_type(htw_req1_type), + .htw_req2_valid(htw_req2_valid), + .htw_req2_thdid(htw_req2_thdid), + .htw_req2_type(htw_req2_type), + .htw_req3_valid(htw_req3_valid), + .htw_req3_thdid(htw_req3_thdid), + .htw_req3_type(htw_req3_type), +`ifdef WAIT_UPDATES + .cp_mm_perf_except_taken_q(cp_mm_perf_except_taken_q), +`endif + + .tlb_cmp_perf_miss_direct(tlb_cmp_perf_miss_direct), + .tlb_cmp_perf_hit_direct(tlb_cmp_perf_hit_direct), + .tlb_cmp_perf_hit_indirect(tlb_cmp_perf_hit_indirect), + .tlb_cmp_perf_hit_first_page(tlb_cmp_perf_hit_first_page), + .tlb_cmp_perf_ptereload(tlb_cmp_perf_ptereload), + .tlb_cmp_perf_ptereload_noexcep(tlb_cmp_perf_ptereload_noexcep), + .tlb_cmp_perf_lrat_request(tlb_cmp_perf_lrat_request), + .tlb_cmp_perf_lrat_miss(tlb_cmp_perf_lrat_miss), + .tlb_cmp_perf_pt_fault(tlb_cmp_perf_pt_fault), + .tlb_cmp_perf_pt_inelig(tlb_cmp_perf_pt_inelig), + .tlb_ctl_perf_tlbwec_resv(tlb_ctl_perf_tlbwec_resv), + .tlb_ctl_perf_tlbwec_noresv(tlb_ctl_perf_tlbwec_noresv), + +// control inputs + .mmq_spr_event_mux_ctrls(mmq_spr_event_mux_ctrls_sig[0:`MESR1_WIDTH*`THREADS-1]), + .pc_mm_event_count_mode(pc_mm_event_count_mode[0:2]), + .rp_mm_event_bus_enable_q(rp_mm_event_bus_enable_q), + .mm_event_bus_in(mm_event_bus_in), + .mm_event_bus_out(mm_event_bus_out) +); +// End of mmq_perf component instantiation + + +//--------------------------------------------------------------------- +// Pervasive and LCB Control Component Instantiation +//--------------------------------------------------------------------- + +//work.mmq_perv #(.`EXPAND_TYPE(`EXPAND_TYPE)) mmq_perv( +mmq_perv mmq_perv( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .pc_mm_sg_3(pc_mm_sg_3), + .pc_mm_func_sl_thold_3(pc_mm_func_sl_thold_3), + .pc_mm_func_slp_sl_thold_3(pc_mm_func_slp_sl_thold_3), + .pc_mm_gptr_sl_thold_3(pc_mm_gptr_sl_thold_3), + .pc_mm_fce_3(pc_mm_fce_3), + .pc_mm_time_sl_thold_3(pc_mm_time_sl_thold_3), + .pc_mm_repr_sl_thold_3(pc_mm_repr_sl_thold_3), + .pc_mm_abst_sl_thold_3(pc_mm_abst_sl_thold_3), + .pc_mm_abst_slp_sl_thold_3(pc_mm_abst_slp_sl_thold_3), + .pc_mm_cfg_sl_thold_3(pc_mm_cfg_sl_thold_3), + .pc_mm_cfg_slp_sl_thold_3(pc_mm_cfg_slp_sl_thold_3), + .pc_mm_func_nsl_thold_3(pc_mm_func_nsl_thold_3), + .pc_mm_func_slp_nsl_thold_3(pc_mm_func_slp_nsl_thold_3), + .pc_mm_ary_nsl_thold_3(pc_mm_ary_nsl_thold_3), + .pc_mm_ary_slp_nsl_thold_3(pc_mm_ary_slp_nsl_thold_3), + .tc_ac_ccflush_dc(tc_ac_ccflush_dc), + .tc_scan_diag_dc(tc_ac_scan_diag_dc), + .tc_ac_scan_dis_dc_b(tc_ac_scan_dis_dc_b), + + .pc_sg_0(pc_sg_0), + .pc_sg_1(pc_sg_1), + .pc_sg_2(pc_sg_2), + .pc_func_sl_thold_2(pc_func_sl_thold_2), + .pc_func_slp_sl_thold_2(pc_func_slp_sl_thold_2), + .pc_func_slp_nsl_thold_2(pc_func_slp_nsl_thold_2), + .pc_cfg_sl_thold_2(pc_cfg_sl_thold_2), + .pc_cfg_slp_sl_thold_2(pc_cfg_slp_sl_thold_2), + .pc_fce_2(pc_fce_2), + .pc_time_sl_thold_0(pc_time_sl_thold_0), + .pc_repr_sl_thold_0(pc_repr_sl_thold_0), + .pc_abst_sl_thold_0(pc_abst_sl_thold_0), + .pc_abst_slp_sl_thold_0(pc_abst_slp_sl_thold_0), + .pc_ary_nsl_thold_0(pc_ary_nsl_thold_0), + .pc_ary_slp_nsl_thold_0(pc_ary_slp_nsl_thold_0), + .pc_func_sl_thold_0(pc_func_sl_thold_0), + .pc_func_sl_thold_0_b(pc_func_sl_thold_0_b), + .pc_func_slp_sl_thold_0(pc_func_slp_sl_thold_0), + .pc_func_slp_sl_thold_0_b(pc_func_slp_sl_thold_0_b), + .lcb_clkoff_dc_b(lcb_clkoff_dc_b), + .lcb_act_dis_dc(lcb_act_dis_dc), + .lcb_d_mode_dc(lcb_d_mode_dc), + .lcb_delay_lclkr_dc(lcb_delay_lclkr_dc), + .lcb_mpw1_dc_b(lcb_mpw1_dc_b), + .lcb_mpw2_dc_b(lcb_mpw2_dc_b), + .g8t_gptr_lcb_clkoff_dc_b(g8t_gptr_lcb_clkoff_dc_b), + .g8t_gptr_lcb_act_dis_dc(g8t_gptr_lcb_act_dis_dc), + .g8t_gptr_lcb_d_mode_dc(g8t_gptr_lcb_d_mode_dc), + .g8t_gptr_lcb_delay_lclkr_dc(g8t_gptr_lcb_delay_lclkr_dc), + .g8t_gptr_lcb_mpw1_dc_b(g8t_gptr_lcb_mpw1_dc_b), + .g8t_gptr_lcb_mpw2_dc_b(g8t_gptr_lcb_mpw2_dc_b), + .g6t_gptr_lcb_clkoff_dc_b(g6t_gptr_lcb_clkoff_dc_b), + .g6t_gptr_lcb_act_dis_dc(g6t_gptr_lcb_act_dis_dc), + .g6t_gptr_lcb_d_mode_dc(g6t_gptr_lcb_d_mode_dc), + .g6t_gptr_lcb_delay_lclkr_dc(g6t_gptr_lcb_delay_lclkr_dc), + .g6t_gptr_lcb_mpw1_dc_b(g6t_gptr_lcb_mpw1_dc_b), + .g6t_gptr_lcb_mpw2_dc_b(g6t_gptr_lcb_mpw2_dc_b), + + .pc_mm_abist_dcomp_g6t_2r(pc_mm_abist_dcomp_g6t_2r), + .pc_mm_abist_di_0(pc_mm_abist_di_0), + .pc_mm_abist_di_g6t_2r(pc_mm_abist_di_g6t_2r), + .pc_mm_abist_ena_dc(pc_mm_abist_ena_dc), + .pc_mm_abist_g6t_r_wb(pc_mm_abist_g6t_r_wb), + .pc_mm_abist_g8t1p_renb_0(pc_mm_abist_g8t1p_renb_0), + .pc_mm_abist_g8t_bw_0(pc_mm_abist_g8t_bw_0), + .pc_mm_abist_g8t_bw_1(pc_mm_abist_g8t_bw_1), + .pc_mm_abist_g8t_dcomp(pc_mm_abist_g8t_dcomp), + .pc_mm_abist_g8t_wenb(pc_mm_abist_g8t_wenb), + .pc_mm_abist_raddr_0(pc_mm_abist_raddr_0), + .pc_mm_abist_waddr_0(pc_mm_abist_waddr_0), + .pc_mm_abist_wl128_comp_ena(pc_mm_abist_wl128_comp_ena), + + .pc_mm_abist_g8t_wenb_q(pc_mm_abist_g8t_wenb_q), + .pc_mm_abist_g8t1p_renb_0_q(pc_mm_abist_g8t1p_renb_0_q), + .pc_mm_abist_di_0_q(pc_mm_abist_di_0_q), + .pc_mm_abist_g8t_bw_1_q(pc_mm_abist_g8t_bw_1_q), + .pc_mm_abist_g8t_bw_0_q(pc_mm_abist_g8t_bw_0_q), + .pc_mm_abist_waddr_0_q(pc_mm_abist_waddr_0_q), + .pc_mm_abist_raddr_0_q(pc_mm_abist_raddr_0_q), + .pc_mm_abist_wl128_comp_ena_q(pc_mm_abist_wl128_comp_ena_q), + .pc_mm_abist_g8t_dcomp_q(pc_mm_abist_g8t_dcomp_q), + .pc_mm_abist_dcomp_g6t_2r_q(pc_mm_abist_dcomp_g6t_2r_q), + .pc_mm_abist_di_g6t_2r_q(pc_mm_abist_di_g6t_2r_q), + .pc_mm_abist_g6t_r_wb_q(pc_mm_abist_g6t_r_wb_q), + + .pc_mm_bolt_sl_thold_3(pc_mm_bolt_sl_thold_3), + .pc_mm_bo_enable_3(pc_mm_bo_enable_3), + .pc_mm_bolt_sl_thold_0(pc_mm_bolt_sl_thold_0), + .pc_mm_bo_enable_2(pc_mm_bo_enable_2), + + .gptr_scan_in(gptr_scan_in), + .gptr_scan_out(gptr_scan_out), + + .time_scan_in(time_scan_in), + .time_scan_in_int(time_scan_in_int), + .time_scan_out_int(time_scan_out_int), + .time_scan_out(time_scan_out), + + .func_scan_in({func_scan_in[0:8], func_scan_in[9]}), + .func_scan_in_int(func_scan_in_int), + .func_scan_out_int(func_scan_out_int), + .func_scan_out({func_scan_out[0:8], func_scan_out[9]}), + + .repr_scan_in(repr_scan_in), + .repr_scan_in_int(repr_scan_in_int), + .repr_scan_out_int(repr_scan_out_int), + .repr_scan_out(repr_scan_out), + + .abst_scan_in(abst_scan_in[0:1]), + .abst_scan_in_int(abst_scan_in_int), + .abst_scan_out_int(abst_scan_out_int), + .abst_scan_out(abst_scan_out[0:1]), + + .bcfg_scan_in(bcfg_scan_in), + .bcfg_scan_in_int(bcfg_scan_in_int), + .bcfg_scan_out_int(bcfg_scan_out_int), + .bcfg_scan_out(bcfg_scan_out), + + .ccfg_scan_in(ccfg_scan_in), + .ccfg_scan_in_int(ccfg_scan_in_int), + .ccfg_scan_out_int(ccfg_scan_out_int), + .ccfg_scan_out(ccfg_scan_out), + + .dcfg_scan_in(dcfg_scan_in), + .dcfg_scan_in_int(dcfg_scan_in_int), + .dcfg_scan_out_int(dcfg_scan_out_int), + .dcfg_scan_out(dcfg_scan_out) +); +// End of mmq_perv component instantiation + + +//--------------------------------------------------------------------- +// output assignments +//--------------------------------------------------------------------- +// tie off undriven ports when tlb components are not present +// keep this here for people that like to control TLB existence with generics +generate +if (`EXPAND_TLB_TYPE == 0) +begin : eratonly_tieoffs_gen + assign mm_iu_ierat_rel_val_sig = {-3{1'b0}}; + assign mm_iu_ierat_rel_data_sig = {`ERAT_REL_DATA_WIDTH{1'b0}}; + assign mm_xu_derat_rel_val_sig = {-3{1'b0}}; + assign mm_xu_derat_rel_data_sig = {`ERAT_REL_DATA_WIDTH{1'b0}}; + assign tlb_cmp_ierat_dup_val_sig = {-5{1'b0}}; + assign tlb_cmp_derat_dup_val_sig = {-5{1'b0}}; + assign tlb_cmp_erat_dup_wait_sig = {0{1'b0}}; + assign tlb_ctl_barrier_done_sig = {0{1'b0}}; + assign tlb_ctl_ex2_flush_req_sig = {0{1'b0}}; + assign tlb_ctl_ex2_illeg_instr_sig = {0{1'b0}}; + assign tlb_ctl_ex6_illeg_instr_sig = {0{1'b0}}; + assign tlb_ctl_ex2_itag_sig = {`ITAG_SIZE_ENC{1'b0}}; + assign tlb_ctl_ord_type = {-1{1'b0}}; + assign tlb_tag4_itag_sig = {`ITAG_SIZE_ENC{1'b0}}; + assign tlb_tag5_itag_sig = {`ITAG_SIZE_ENC{1'b0}}; + assign tlb_tag5_emq_sig = {`EMQ_ENTRIES{1'b0}}; + assign tlb_tag5_except = {0{1'b0}}; + assign tlb_req_quiesce_sig = {`THDID_WIDTH{1'b1}}; + assign tlb_ctl_quiesce_sig = {`MM_THREADS{1'b1}}; + assign htw_quiesce_sig = {`THDID_WIDTH{1'b1}}; + // missing perf count signals + assign tlb_cmp_perf_event_t0 = {10{1'b0}}; + assign tlb_cmp_perf_event_t1 = {10{1'b0}}; + assign tlb_cmp_perf_state = {0{1'b0}}; + assign derat_req0_thdid_sig = {`THDID_WIDTH{1'b0}}; + assign derat_req0_emq_sig = {`EMQ_ENTRIES{1'b0}}; + assign derat_req0_valid_sig = 1'b0; + assign derat_req0_nonspec_sig = 1'b0; + assign derat_req1_thdid_sig = {`THDID_WIDTH{1'b0}}; + assign derat_req1_emq_sig = {`EMQ_ENTRIES{1'b0}}; + assign derat_req1_valid_sig = 1'b0; + assign derat_req1_nonspec_sig = 1'b0; + assign derat_req2_thdid_sig = {`THDID_WIDTH{1'b0}}; + assign derat_req2_emq_sig = {`EMQ_ENTRIES{1'b0}}; + assign derat_req2_valid_sig = 1'b0; + assign derat_req2_nonspec_sig = 1'b0; + assign derat_req3_thdid_sig = {`THDID_WIDTH{1'b0}}; + assign derat_req3_emq_sig = {`EMQ_ENTRIES{1'b0}}; + assign derat_req3_valid_sig = 1'b0; + assign derat_req3_nonspec_sig = 1'b0; + assign ierat_req0_thdid_sig = {`THDID_WIDTH{1'b0}}; + assign ierat_req0_valid_sig = 1'b0; + assign ierat_req0_nonspec_sig = 1'b0; + assign ierat_req1_thdid_sig = {`THDID_WIDTH{1'b0}}; + assign ierat_req1_valid_sig = 1'b0; + assign ierat_req1_nonspec_sig = 1'b0; + assign ierat_req2_thdid_sig = {`THDID_WIDTH{1'b0}}; + assign ierat_req2_valid_sig = 1'b0; + assign ierat_req2_nonspec_sig = 1'b0; + assign ierat_req3_thdid_sig = {`THDID_WIDTH{1'b0}}; + assign ierat_req3_valid_sig = 1'b0; + assign ierat_req3_nonspec_sig = 1'b0; + assign tlb_tag0_thdid = {`THDID_WIDTH{1'b0}}; + assign tlb_tag0_type = {-6{1'b0}}; + assign tlb_seq_idle = 1'b0; + assign htw_req0_valid = 1'b0; + assign htw_req0_thdid = {`THDID_WIDTH{1'b0}}; + assign htw_req0_type = {0{1'b0}}; + assign htw_req1_valid = 1'b0; + assign htw_req1_thdid = {`THDID_WIDTH{1'b0}}; + assign htw_req1_type = {0{1'b0}}; + assign htw_req2_valid = 1'b0; + assign htw_req2_thdid = {`THDID_WIDTH{1'b0}}; + assign htw_req2_type = {0{1'b0}}; + assign htw_req3_valid = 1'b0; + assign htw_req3_thdid = {`THDID_WIDTH{1'b0}}; + assign htw_req3_type = {0{1'b0}}; + assign tlb_cmp_perf_miss_direct = 1'b0; + assign tlb_cmp_perf_hit_direct = 1'b0; + assign tlb_cmp_perf_hit_indirect = 1'b0; + assign tlb_cmp_perf_hit_first_page = 1'b0; + assign tlb_cmp_perf_ptereload = 1'b0; + assign tlb_cmp_perf_ptereload_noexcep = 1'b0; + assign tlb_cmp_perf_lrat_request = 1'b0; + assign tlb_cmp_perf_lrat_miss = 1'b0; + assign tlb_cmp_perf_pt_fault = 1'b0; + assign tlb_cmp_perf_pt_inelig = 1'b0; + assign tlb_ctl_perf_tlbwec_resv = 1'b0; + assign tlb_ctl_perf_tlbwec_noresv = 1'b0; + // missing debug signals + assign tlb_cmp_dbg_tag4 = {`TLB_TAG_WIDTH{1'b0}}; + assign tlb_cmp_dbg_tag4_wayhit = {`TLB_WAYS+1{1'b0}}; + assign tlb_cmp_dbg_addr4 = {`TLB_ADDR_WIDTH{1'b0}}; + assign tlb_cmp_dbg_tag4_way = {`TLB_WAY_WIDTH{1'b0}}; + assign mm_xu_eratmiss_done_sig = {0{1'b0}}; + assign mm_xu_tlb_miss_sig = {0{1'b0}}; + assign mm_xu_lrat_miss_sig = {0{1'b0}}; + assign mm_xu_tlb_inelig_sig = {0{1'b0}}; + assign mm_xu_pt_fault_sig = {0{1'b0}}; + assign mm_xu_hv_priv_sig = {0{1'b0}}; + assign mm_xu_cr0_eq_sig = {0{1'b0}}; + assign mm_xu_cr0_eq_valid_sig = {0{1'b0}}; + assign mm_xu_esr_pt_sig = {0{1'b0}}; + assign mm_xu_esr_data_sig = {0{1'b0}}; + assign mm_xu_esr_epid_sig = {0{1'b0}}; + assign mm_xu_esr_st_sig = {0{1'b0}}; + assign mm_xu_tlb_miss_ored_sig = 1'b0; + assign mm_xu_lrat_miss_ored_sig = 1'b0; + assign mm_xu_tlb_inelig_ored_sig = 1'b0; + assign mm_xu_pt_fault_ored_sig = 1'b0; + assign mm_xu_hv_priv_ored_sig = 1'b0; + assign mm_xu_cr0_eq_ored_sig = 1'b0; + assign mm_xu_cr0_eq_valid_ored_sig = 1'b0; + assign mm_xu_tlb_multihit_err_sig = {0{1'b0}}; + assign mm_xu_tlb_par_err_sig = {0{1'b0}}; + assign mm_xu_lru_par_err_sig = {0{1'b0}}; + assign mm_xu_ord_tlb_multihit_sig = {0{1'b0}}; + assign mm_xu_ord_tlb_par_err_sig = {0{1'b0}}; + assign mm_xu_ord_lru_par_err_sig = {0{1'b0}}; + assign mm_pc_tlb_multihit_err_ored_sig = 1'b0; + assign mm_pc_tlb_par_err_ored_sig = 1'b0; + assign mm_pc_lru_par_err_ored_sig = 1'b0; + assign tlb_snoop_ack = 1'b0; +end +endgenerate + +assign mm_iu_ierat_rel_val = mm_iu_ierat_rel_val_sig; +assign mm_iu_ierat_rel_data = mm_iu_ierat_rel_data_sig; +assign mm_xu_derat_rel_val = mm_xu_derat_rel_val_sig; +assign mm_xu_derat_rel_data = mm_xu_derat_rel_data_sig; +assign mm_xu_ord_n_flush_req = mm_xu_ord_n_flush_req_sig[0:`THREADS - 1]; +assign mm_xu_ord_np1_flush_req = mm_xu_ord_np1_flush_req_sig[0:`THREADS - 1]; +assign mm_xu_ord_read_done = mm_xu_ord_read_done_sig[0:`THREADS - 1]; +assign mm_xu_ord_write_done = mm_xu_ord_write_done_sig[0:`THREADS - 1]; + + assign mm_iu_hold_req = mm_iu_hold_req_sig[0:`THREADS - 1]; + assign mm_iu_hold_done = mm_iu_hold_done_sig[0:`THREADS - 1]; + assign mm_iu_flush_req = mm_iu_flush_req_sig[0:`THREADS - 1]; + assign mm_iu_bus_snoop_hold_req = mm_iu_bus_snoop_hold_req_sig[0:`THREADS - 1]; + assign mm_iu_bus_snoop_hold_done = mm_iu_bus_snoop_hold_done_sig[0:`THREADS - 1]; + assign mm_iu_tlbi_complete = mm_iu_tlbi_complete_sig[0:`THREADS - 1]; + assign mm_xu_ex3_flush_req = mm_xu_ex3_flush_req_sig[0:`THREADS - 1]; + assign mm_xu_eratmiss_done = mm_xu_eratmiss_done_sig[0:`THREADS - 1]; + assign mm_xu_tlb_miss = mm_xu_tlb_miss_sig[0:`THREADS - 1]; + assign mm_xu_lrat_miss = mm_xu_lrat_miss_sig[0:`THREADS - 1]; + assign mm_xu_tlb_inelig = mm_xu_tlb_inelig_sig[0:`THREADS - 1]; + assign mm_xu_pt_fault = mm_xu_pt_fault_sig[0:`THREADS - 1]; + assign mm_xu_hv_priv = mm_xu_hv_priv_sig[0:`THREADS - 1]; + assign mm_xu_illeg_instr = mm_xu_illeg_instr_sig[0:`THREADS - 1]; + assign mm_xu_esr_pt = mm_xu_esr_pt_sig[0:`THREADS - 1]; + assign mm_xu_esr_data = mm_xu_esr_data_sig[0:`THREADS - 1]; + assign mm_xu_esr_epid = mm_xu_esr_epid_sig[0:`THREADS - 1]; + assign mm_xu_esr_st = mm_xu_esr_st_sig[0:`THREADS - 1]; + assign mm_xu_cr0_eq = mm_xu_cr0_eq_sig[0:`THREADS - 1]; + assign mm_xu_cr0_eq_valid = mm_xu_cr0_eq_valid_sig[0:`THREADS - 1]; + assign mm_xu_quiesce = mm_xu_quiesce_sig[0:`THREADS - 1]; + assign mm_pc_tlb_req_quiesce = mm_pc_tlb_req_quiesce_sig[0:`THREADS - 1]; + assign mm_pc_tlb_ctl_quiesce = mm_pc_tlb_ctl_quiesce_sig[0:`THREADS - 1]; + assign mm_pc_htw_quiesce = mm_pc_htw_quiesce_sig[0:`THREADS - 1]; + assign mm_pc_inval_quiesce = mm_pc_inval_quiesce_sig[0:`THREADS - 1]; + + assign mm_xu_local_snoop_reject = mm_xu_local_snoop_reject_sig[0:`THREADS - 1]; + assign mm_xu_tlb_multihit_err = mm_xu_tlb_multihit_err_sig[0:`THREADS - 1]; + assign mm_xu_tlb_par_err = mm_xu_tlb_par_err_sig[0:`THREADS - 1]; + assign mm_xu_lru_par_err = mm_xu_lru_par_err_sig[0:`THREADS - 1]; + + assign mm_xu_ord_tlb_multihit = mm_xu_ord_tlb_multihit_sig; + assign mm_xu_ord_tlb_par_err = mm_xu_ord_tlb_par_err_sig; + assign mm_xu_ord_lru_par_err = mm_xu_ord_lru_par_err_sig; + + assign mm_xu_tlb_miss_ored = mm_xu_tlb_miss_ored_sig; + assign mm_xu_lrat_miss_ored = mm_xu_lrat_miss_ored_sig; + assign mm_xu_tlb_inelig_ored = mm_xu_tlb_inelig_ored_sig; + assign mm_xu_pt_fault_ored = mm_xu_pt_fault_ored_sig; + assign mm_xu_hv_priv_ored = mm_xu_hv_priv_ored_sig; + assign mm_xu_cr0_eq_ored = mm_xu_cr0_eq_ored_sig; + assign mm_xu_cr0_eq_valid_ored = mm_xu_cr0_eq_valid_ored_sig; + assign mm_pc_local_snoop_reject_ored = mm_pc_local_snoop_reject_ored_sig; + assign mm_pc_tlb_multihit_err_ored = mm_pc_tlb_multihit_err_ored_sig; + assign mm_pc_tlb_par_err_ored = mm_pc_tlb_par_err_ored_sig; + assign mm_pc_lru_par_err_ored = mm_pc_lru_par_err_ored_sig; + assign mm_iu_tlbwe_binv = mmucr1_sig[17]; + assign mm_xu_lsu_req = mm_xu_lsu_req_sig[0:`THREADS - 1]; + assign mm_xu_lsu_ttype = mm_xu_lsu_ttype_sig; + assign mm_xu_lsu_wimge = mm_xu_lsu_wimge_sig; + assign mm_xu_lsu_u = mm_xu_lsu_u_sig; + assign mm_xu_lsu_addr = mm_xu_lsu_addr_sig; + assign mm_xu_lsu_lpid = mm_xu_lsu_lpid_sig; + assign mm_xu_lsu_gs = mm_xu_lsu_gs_sig; + assign mm_xu_lsu_ind = mm_xu_lsu_ind_sig; + assign mm_xu_lsu_lbit = mm_xu_lsu_lbit_sig; + +// using ifdef's now for t0/t1 assignment to iu,lq in top level + assign mm_iu_t0_ierat_pid = mm_iu_ierat_pid_sig[0]; + assign mm_xu_t0_derat_pid = mm_xu_derat_pid_sig[0]; + assign mm_iu_t0_ierat_mmucr0 = mm_iu_ierat_mmucr0_sig[0]; + assign mm_xu_t0_derat_mmucr0 = mm_xu_derat_mmucr0_sig[0]; +`ifdef MM_THREADS2 + assign mm_iu_t1_ierat_pid = mm_iu_ierat_pid_sig[1]; + assign mm_xu_t1_derat_pid = mm_xu_derat_pid_sig[1]; + assign mm_iu_t1_ierat_mmucr0 = mm_iu_ierat_mmucr0_sig[1]; + assign mm_xu_t1_derat_mmucr0 = mm_xu_derat_mmucr0_sig[1]; +`endif + + + + //------------------ end of common stuff for both erat-only and tlb ------------- + + + //--------------------------------------------------------------------- + // Start of TLB logic + //--------------------------------------------------------------------- + generate + if (`EXPAND_TLB_TYPE > 0) + begin : tlb_gen_logic + + //--------------------------------------------------------------------- + // TLB Request Queue Component Instantiation + //--------------------------------------------------------------------- + //work.mmq_tlb_req #(.`THREADS(`THREADS), .`THDID_WIDTH(`THDID_WIDTH), .`PID_WIDTH(`PID_WIDTH), .`PID_WIDTH_erat(`PID_WIDTH_erat), .`LPID_WIDTH(`LPID_WIDTH), .`EPN_WIDTH(`EPN_WIDTH), .`RS_DATA_WIDTH(`RS_DATA_WIDTH), .`EXPAND_TYPE(`EXPAND_TYPE)) mmq_tlb_req( + mmq_tlb_req mmq_tlb_req( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .tc_ccflush_dc(tc_ac_ccflush_dc), + .tc_scan_dis_dc_b(tc_ac_scan_dis_dc_b), + .tc_scan_diag_dc(tc_ac_scan_diag_dc), + .tc_lbist_en_dc(tc_ac_lbist_en_dc), + + .lcb_d_mode_dc(lcb_d_mode_dc), + .lcb_clkoff_dc_b(lcb_clkoff_dc_b), + .lcb_act_dis_dc(lcb_act_dis_dc), + .lcb_mpw1_dc_b(lcb_mpw1_dc_b), + .lcb_mpw2_dc_b(lcb_mpw2_dc_b), + .lcb_delay_lclkr_dc(lcb_delay_lclkr_dc), + + .ac_func_scan_in(func_scan_in_int[2]), + .ac_func_scan_out(func_scan_out_int[2]), + + .pc_sg_2(pc_sg_2[1]), + .pc_func_sl_thold_2(pc_func_sl_thold_2[1]), + .pc_func_slp_sl_thold_2(pc_func_slp_sl_thold_2[1]), + .pid0(pid0_sig), +`ifdef MM_THREADS2 + .pid1(pid1_sig), +`endif + .lpidr(lpidr_sig), + .xu_mm_ccr2_notlb_b(xu_mm_ccr2_notlb_b[3]), + .mmucr2_act_override(mmucr2_sig[0]), + .iu_mm_ierat_req(iu_mm_ierat_req), + .iu_mm_ierat_epn(iu_mm_ierat_epn), + .iu_mm_ierat_thdid(iu_mm_ierat_thdid_sig), + .iu_mm_ierat_state(iu_mm_ierat_state), + .iu_mm_ierat_tid(iu_mm_ierat_tid), + .iu_mm_ierat_req_nonspec(iu_mm_ierat_req_nonspec), + .iu_mm_ierat_flush(iu_mm_ierat_flush_sig), + + .xu_mm_derat_req(xu_mm_derat_req), + .xu_mm_derat_epn(xu_mm_derat_epn), + .xu_mm_derat_thdid(xu_mm_derat_thdid_sig), + .xu_mm_derat_ttype(xu_mm_derat_ttype), + .xu_mm_derat_state(xu_mm_derat_state), + .xu_mm_derat_tid(xu_mm_derat_tid), + .xu_mm_derat_lpid(xu_mm_derat_lpid), + .lq_mm_derat_req_nonspec(lq_mm_derat_req_nonspec), + .lq_mm_derat_req_itag(lq_mm_derat_req_itag), + .lq_mm_derat_req_emq(lq_mm_derat_req_emq), + + .ierat_req0_pid(ierat_req0_pid_sig), + .ierat_req0_as(ierat_req0_as_sig), + .ierat_req0_gs(ierat_req0_gs_sig), + .ierat_req0_epn(ierat_req0_epn_sig), + .ierat_req0_thdid(ierat_req0_thdid_sig), + .ierat_req0_valid(ierat_req0_valid_sig), + .ierat_req0_nonspec(ierat_req0_nonspec_sig), + .ierat_req1_pid(ierat_req1_pid_sig), + .ierat_req1_as(ierat_req1_as_sig), + .ierat_req1_gs(ierat_req1_gs_sig), + .ierat_req1_epn(ierat_req1_epn_sig), + .ierat_req1_thdid(ierat_req1_thdid_sig), + .ierat_req1_valid(ierat_req1_valid_sig), + .ierat_req1_nonspec(ierat_req1_nonspec_sig), + .ierat_req2_pid(ierat_req2_pid_sig), + .ierat_req2_as(ierat_req2_as_sig), + .ierat_req2_gs(ierat_req2_gs_sig), + .ierat_req2_epn(ierat_req2_epn_sig), + .ierat_req2_thdid(ierat_req2_thdid_sig), + .ierat_req2_valid(ierat_req2_valid_sig), + .ierat_req2_nonspec(ierat_req2_nonspec_sig), + .ierat_req3_pid(ierat_req3_pid_sig), + .ierat_req3_as(ierat_req3_as_sig), + .ierat_req3_gs(ierat_req3_gs_sig), + .ierat_req3_epn(ierat_req3_epn_sig), + .ierat_req3_thdid(ierat_req3_thdid_sig), + .ierat_req3_valid(ierat_req3_valid_sig), + .ierat_req3_nonspec(ierat_req3_nonspec_sig), + .ierat_iu4_pid(ierat_iu4_pid_sig), + .ierat_iu4_gs(ierat_iu4_gs_sig), + .ierat_iu4_as(ierat_iu4_as_sig), + .ierat_iu4_epn(ierat_iu4_epn_sig), + .ierat_iu4_thdid(ierat_iu4_thdid_sig), + .ierat_iu4_valid(ierat_iu4_valid_sig), + + .derat_req0_lpid(derat_req0_lpid_sig), + .derat_req0_pid(derat_req0_pid_sig), + .derat_req0_as(derat_req0_as_sig), + .derat_req0_gs(derat_req0_gs_sig), + .derat_req0_epn(derat_req0_epn_sig), + .derat_req0_thdid(derat_req0_thdid_sig), + .derat_req0_emq(derat_req0_emq_sig), + .derat_req0_valid(derat_req0_valid_sig), + .derat_req0_nonspec(derat_req0_nonspec_sig), + .derat_req1_lpid(derat_req1_lpid_sig), + .derat_req1_pid(derat_req1_pid_sig), + .derat_req1_as(derat_req1_as_sig), + .derat_req1_gs(derat_req1_gs_sig), + .derat_req1_epn(derat_req1_epn_sig), + .derat_req1_thdid(derat_req1_thdid_sig), + .derat_req1_emq(derat_req1_emq_sig), + .derat_req1_valid(derat_req1_valid_sig), + .derat_req1_nonspec(derat_req1_nonspec_sig), + .derat_req2_lpid(derat_req2_lpid_sig), + .derat_req2_pid(derat_req2_pid_sig), + .derat_req2_as(derat_req2_as_sig), + .derat_req2_gs(derat_req2_gs_sig), + .derat_req2_epn(derat_req2_epn_sig), + .derat_req2_thdid(derat_req2_thdid_sig), + .derat_req2_emq(derat_req2_emq_sig), + .derat_req2_valid(derat_req2_valid_sig), + .derat_req2_nonspec(derat_req2_nonspec_sig), + .derat_req3_lpid(derat_req3_lpid_sig), + .derat_req3_pid(derat_req3_pid_sig), + .derat_req3_as(derat_req3_as_sig), + .derat_req3_gs(derat_req3_gs_sig), + .derat_req3_epn(derat_req3_epn_sig), + .derat_req3_thdid(derat_req3_thdid_sig), + .derat_req3_emq(derat_req3_emq_sig), + .derat_req3_valid(derat_req3_valid_sig), + .derat_req3_nonspec(derat_req3_nonspec_sig), + .derat_ex5_lpid(derat_ex5_lpid_sig), + .derat_ex5_pid(derat_ex5_pid_sig), + .derat_ex5_gs(derat_ex5_gs_sig), + .derat_ex5_as(derat_ex5_as_sig), + .derat_ex5_epn(derat_ex5_epn_sig), + .derat_ex5_thdid(derat_ex5_thdid_sig), + .derat_ex5_valid(derat_ex5_valid_sig), + + .xu_ex3_flush(xu_ex3_flush_sig), + .xu_mm_ex4_flush(xu_mm_ex4_flush_sig), + .xu_mm_ex5_flush(xu_mm_ex5_flush_sig), + .xu_mm_ierat_flush(xu_mm_ierat_flush_sig), + .xu_mm_ierat_miss(xu_mm_ierat_miss_sig), + + .tlb_cmp_ierat_dup_val(tlb_cmp_ierat_dup_val_sig), + .tlb_cmp_derat_dup_val(tlb_cmp_derat_dup_val_sig), + + .tlb_seq_ierat_req(tlb_seq_ierat_req), + .tlb_seq_derat_req(tlb_seq_derat_req), + .tlb_seq_ierat_done(tlb_seq_ierat_done), + .tlb_seq_derat_done(tlb_seq_derat_done), + .ierat_req_taken(ierat_req_taken), + .derat_req_taken(derat_req_taken), + .ierat_req_epn(ierat_req_epn), + .ierat_req_pid(ierat_req_pid), + .ierat_req_state(ierat_req_state), + .ierat_req_thdid(ierat_req_thdid), + .ierat_req_dup(ierat_req_dup), + .ierat_req_nonspec(ierat_req_nonspec), + .derat_req_epn(derat_req_epn), + .derat_req_pid(derat_req_pid), + .derat_req_lpid(derat_req_lpid), + .derat_req_state(derat_req_state), + .derat_req_ttype(derat_req_ttype), + .derat_req_thdid(derat_req_thdid), + .derat_req_dup(derat_req_dup), + .derat_req_itag(derat_req_itag), + .derat_req_emq(derat_req_emq), + .derat_req_nonspec(derat_req_nonspec), + + .tlb_req_quiesce(tlb_req_quiesce_sig), + + .tlb_req_dbg_ierat_iu5_valid_q(tlb_req_dbg_ierat_iu5_valid_q), + .tlb_req_dbg_ierat_iu5_thdid(tlb_req_dbg_ierat_iu5_thdid), + .tlb_req_dbg_ierat_iu5_state_q(tlb_req_dbg_ierat_iu5_state_q), + .tlb_req_dbg_ierat_inptr_q(tlb_req_dbg_ierat_inptr_q), + .tlb_req_dbg_ierat_outptr_q(tlb_req_dbg_ierat_outptr_q), + .tlb_req_dbg_ierat_req_valid_q(tlb_req_dbg_ierat_req_valid_q), + .tlb_req_dbg_ierat_req_nonspec_q(tlb_req_dbg_ierat_req_nonspec_q), + .tlb_req_dbg_ierat_req_thdid(tlb_req_dbg_ierat_req_thdid), + .tlb_req_dbg_ierat_req_dup_q(tlb_req_dbg_ierat_req_dup_q), + .tlb_req_dbg_derat_ex6_valid_q(tlb_req_dbg_derat_ex6_valid_q), + .tlb_req_dbg_derat_ex6_thdid(tlb_req_dbg_derat_ex6_thdid), + .tlb_req_dbg_derat_ex6_state_q(tlb_req_dbg_derat_ex6_state_q), + .tlb_req_dbg_derat_inptr_q(tlb_req_dbg_derat_inptr_q), + .tlb_req_dbg_derat_outptr_q(tlb_req_dbg_derat_outptr_q), + .tlb_req_dbg_derat_req_valid_q(tlb_req_dbg_derat_req_valid_q), + .tlb_req_dbg_derat_req_thdid(tlb_req_dbg_derat_req_thdid), + .tlb_req_dbg_derat_req_ttype_q(tlb_req_dbg_derat_req_ttype_q), + .tlb_req_dbg_derat_req_dup_q(tlb_req_dbg_derat_req_dup_q) + ); + // End of mmq_tlb_req component instantiation + + + //--------------------------------------------------------------------- + // TLB Control Logic Component Instantiation + //--------------------------------------------------------------------- + + //work.mmq_tlb_ctl #(.`THREADS(`THREADS), .`THDID_WIDTH(`THDID_WIDTH), .`EPN_WIDTH(`EPN_WIDTH), .`PID_WIDTH(`PID_WIDTH), .`REAL_ADDR_WIDTH(`REAL_ADDR_WIDTH), .`RS_DATA_WIDTH(`RS_DATA_WIDTH), .`DATA_OUT_WIDTH(`DATA_OUT_WIDTH), .`TLB_TAG_WIDTH(`TLB_TAG_WIDTH), .`EXPAND_TYPE(`EXPAND_TYPE)) mmq_tlb_ctl( + mmq_tlb_ctl mmq_tlb_ctl( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .tc_ccflush_dc(tc_ac_ccflush_dc), + .tc_scan_dis_dc_b(tc_ac_scan_dis_dc_b), + .tc_scan_diag_dc(tc_ac_scan_diag_dc), + .tc_lbist_en_dc(tc_ac_lbist_en_dc), + + .lcb_d_mode_dc(lcb_d_mode_dc), + .lcb_clkoff_dc_b(lcb_clkoff_dc_b), + .lcb_act_dis_dc(lcb_act_dis_dc), + .lcb_mpw1_dc_b(lcb_mpw1_dc_b), + .lcb_mpw2_dc_b(lcb_mpw2_dc_b), + .lcb_delay_lclkr_dc(lcb_delay_lclkr_dc), + + .ac_func_scan_in(func_scan_in_int[3]), + .ac_func_scan_out(func_scan_out_int[3]), + + .pc_sg_2(pc_sg_2[1]), + .pc_func_sl_thold_2(pc_func_sl_thold_2[1]), + .pc_func_slp_sl_thold_2(pc_func_slp_sl_thold_2[1]), + .pc_func_slp_nsl_thold_2(pc_func_slp_nsl_thold_2), + .pc_fce_2(pc_fce_2), + .xu_mm_rf1_val(xu_mm_rf1_val_sig), + .xu_mm_rf1_is_tlbre(xu_mm_rf1_is_tlbre), + .xu_mm_rf1_is_tlbwe(xu_mm_rf1_is_tlbwe), + .xu_mm_rf1_is_tlbsx(xu_mm_rf1_is_tlbsx), + .xu_mm_rf1_is_tlbsxr(xu_mm_rf1_is_tlbsxr), + .xu_mm_rf1_is_tlbsrx(xu_mm_rf1_is_tlbsrx), + .xu_mm_ex2_epn(xu_mm_ex2_eff_addr_sig[64 - `RS_DATA_WIDTH:51]), + .xu_mm_rf1_itag(xu_mm_rf1_itag), + + .xu_mm_msr_gs(xu_mm_msr_gs_sig), + .xu_mm_msr_pr(xu_mm_msr_pr_sig), + .xu_mm_msr_is(xu_mm_msr_is_sig), + .xu_mm_msr_ds(xu_mm_msr_ds_sig), + .xu_mm_msr_cm(xu_mm_msr_cm_sig), + + .xu_mm_ccr2_notlb_b(xu_mm_ccr2_notlb_b[4]), + .xu_mm_epcr_dgtmi(xu_mm_epcr_dgtmi_sig), + .xu_mm_xucr4_mmu_mchk(xu_mm_xucr4_mmu_mchk), + .xu_mm_xucr4_mmu_mchk_q(xu_mm_xucr4_mmu_mchk_q), + .xu_rf1_flush(xu_rf1_flush_sig), + .xu_ex1_flush(xu_ex1_flush_sig), + .xu_ex2_flush(xu_ex2_flush_sig), + .xu_ex3_flush(xu_ex3_flush_sig[0:`MM_THREADS-1]), + .xu_ex4_flush(xu_ex4_flush_sig), + .xu_ex5_flush(xu_ex5_flush_sig), + + .tlb_ctl_ex3_valid(tlb_ctl_ex3_valid_sig), + .tlb_ctl_ex3_ttype(tlb_ctl_ex3_ttype_sig), + .tlb_ctl_ex3_hv_state(tlb_ctl_ex3_hv_state_sig), + + .tlb_ctl_tag2_flush(tlb_ctl_tag2_flush_sig), + .tlb_ctl_tag3_flush(tlb_ctl_tag3_flush_sig), + .tlb_ctl_tag4_flush(tlb_ctl_tag4_flush_sig), + .tlb_resv_match_vec(tlb_resv_match_vec_sig), + .tlb_ctl_barrier_done(tlb_ctl_barrier_done_sig), + .tlb_ctl_ex2_flush_req(tlb_ctl_ex2_flush_req_sig), + .tlb_ctl_ord_type(tlb_ctl_ord_type), + .tlb_ctl_ex2_itag(tlb_ctl_ex2_itag_sig), + .tlb_ctl_ex6_illeg_instr(tlb_ctl_ex6_illeg_instr_sig), + .tlb_ctl_ex2_illeg_instr(tlb_ctl_ex2_illeg_instr_sig), + .tlb_ctl_quiesce(tlb_ctl_quiesce_sig), + .ex6_illeg_instr(ex6_illeg_instr), + + .mm_xu_eratmiss_done(mm_xu_eratmiss_done_sig), + .mm_xu_tlb_miss(mm_xu_tlb_miss_sig), + .mm_xu_tlb_inelig(mm_xu_tlb_inelig_sig), + + .tlbwe_back_inv_pending(tlbwe_back_inv_pending_sig), + .pid0(pid0_sig), +`ifdef MM_THREADS2 + .pid1(pid1_sig), +`endif + .mmucr1_tlbi_msb(mmucr1_sig[18]), + .mmucr1_tlbwe_binv(mmucr1_sig[17]), + .mmucr2(mmucr2_sig), + .mmucr3_0(mmucr3_0_sig), +`ifdef MM_THREADS2 + .mmucr3_1(mmucr3_1_sig), +`endif + .lpidr(lpidr_sig), + .mmucfg_lrat(mmucfg_lrat), + .mmucfg_twc(mmucfg_twc), + .mmucsr0_tlb0fi(mmucsr0_tlb0fi), + .tlb0cfg_pt(tlb0cfg_pt), + .tlb0cfg_ind(tlb0cfg_ind), + .tlb0cfg_gtwe(tlb0cfg_gtwe), + + .mas0_0_atsel(mas0_0_atsel), + .mas0_0_esel(mas0_0_esel), + .mas0_0_hes(mas0_0_hes), + .mas0_0_wq(mas0_0_wq), + .mas1_0_v(mas1_0_v), + .mas1_0_iprot(mas1_0_iprot), + .mas1_0_tid(mas1_0_tid), + .mas1_0_ind(mas1_0_ind), + .mas1_0_ts(mas1_0_ts), + .mas1_0_tsize(mas1_0_tsize), + .mas2_0_epn(mas2_0_epn), + .mas2_0_wimge(mas2_0_wimge), + .mas3_0_usxwr(mas3_0_usxwr[0:3]), + .mas5_0_sgs(mas5_0_sgs), + .mas5_0_slpid(mas5_0_slpid), + .mas6_0_spid(mas6_0_spid), + .mas6_0_sind(mas6_0_sind), + .mas6_0_sas(mas6_0_sas), + .mas8_0_tgs(mas8_0_tgs), + .mas8_0_tlpid(mas8_0_tlpid), +`ifdef MM_THREADS2 + .mas0_1_atsel(mas0_1_atsel), + .mas0_1_esel(mas0_1_esel), + .mas0_1_hes(mas0_1_hes), + .mas0_1_wq(mas0_1_wq), + .mas1_1_v(mas1_1_v), + .mas1_1_iprot(mas1_1_iprot), + .mas1_1_tid(mas1_1_tid), + .mas1_1_ind(mas1_1_ind), + .mas1_1_ts(mas1_1_ts), + .mas1_1_tsize(mas1_1_tsize), + .mas2_1_epn(mas2_1_epn), + .mas2_1_wimge(mas2_1_wimge), + .mas3_1_usxwr(mas3_1_usxwr[0:3]), + .mas5_1_sgs(mas5_1_sgs), + .mas5_1_slpid(mas5_1_slpid), + .mas6_1_spid(mas6_1_spid), + .mas6_1_sind(mas6_1_sind), + .mas6_1_sas(mas6_1_sas), + .mas8_1_tgs(mas8_1_tgs), + .mas8_1_tlpid(mas8_1_tlpid), +`endif + + .tlb_seq_ierat_req(tlb_seq_ierat_req), + .tlb_seq_derat_req(tlb_seq_derat_req), + .tlb_seq_ierat_done(tlb_seq_ierat_done), + .tlb_seq_derat_done(tlb_seq_derat_done), + .tlb_seq_idle(tlb_seq_idle), + .ierat_req_taken(ierat_req_taken), + .derat_req_taken(derat_req_taken), + .ierat_req_epn(ierat_req_epn), + .ierat_req_pid(ierat_req_pid), + .ierat_req_state(ierat_req_state), + .ierat_req_thdid(ierat_req_thdid), + .ierat_req_dup(ierat_req_dup), + .ierat_req_nonspec(ierat_req_nonspec), + .derat_req_epn(derat_req_epn), + .derat_req_pid(derat_req_pid), + .derat_req_lpid(derat_req_lpid), + .derat_req_state(derat_req_state), + .derat_req_ttype(derat_req_ttype), + .derat_req_thdid(derat_req_thdid), + .derat_req_dup(derat_req_dup), + .derat_req_itag(derat_req_itag), + .derat_req_emq(derat_req_emq), + .derat_req_nonspec(derat_req_nonspec), + .ptereload_req_valid(ptereload_req_valid), + .ptereload_req_tag(ptereload_req_tag), + .ptereload_req_pte(ptereload_req_pte), + .ptereload_req_taken(ptereload_req_taken), + + .tlb_snoop_coming(tlb_snoop_coming), + .tlb_snoop_val(tlb_snoop_val), + .tlb_snoop_attr(tlb_snoop_attr), + .tlb_snoop_vpn(tlb_snoop_vpn), + .tlb_snoop_ack(tlb_snoop_ack), + + .lru_rd_addr(lru_rd_addr), + .lru_tag4_dataout(lru_tag4_dataout), + .tlb_addr4(tlb_addr4), + .tlb_tag4_esel(tlb_tag4_esel), + .tlb_tag4_wq(tlb_tag4_wq), + .tlb_tag4_is(tlb_tag4_is), + .tlb_tag4_gs(tlb_tag4_gs), + .tlb_tag4_pr(tlb_tag4_pr), + .tlb_tag4_hes(tlb_tag4_hes), + .tlb_tag4_atsel(tlb_tag4_atsel), + .tlb_tag4_pt(tlb_tag4_pt), + .tlb_tag4_cmp_hit(tlb_tag4_cmp_hit), + .tlb_tag4_way_ind(tlb_tag4_way_ind), + .tlb_tag4_ptereload(tlb_tag4_ptereload), + .tlb_tag4_endflag(tlb_tag4_endflag), + .tlb_tag4_parerr(tlb_tag4_parerr), + .tlb_tag4_parerr_write(tlb_tag4_parerr_write), + .tlb_tag5_parerr_zeroize(tlb_tag5_parerr_zeroize), + .tlb_tag5_except(tlb_tag5_except), + .tlb_cmp_erat_dup_wait(tlb_cmp_erat_dup_wait_sig), + + .tlb_tag0_epn(tlb_tag0_epn), + .tlb_tag0_thdid(tlb_tag0_thdid), + .tlb_tag0_type(tlb_tag0_type), + .tlb_tag0_lpid(tlb_tag0_lpid), + .tlb_tag0_atsel(tlb_tag0_atsel), + .tlb_tag0_size(tlb_tag0_size), + .tlb_tag0_addr_cap(tlb_tag0_addr_cap), + .tlb_tag0_nonspec(tlb_tag0_nonspec), + + .tlb_tag2(tlb_tag2_sig), + .tlb_addr2(tlb_addr2_sig), + + .tlb_ctl_perf_tlbwec_resv(tlb_ctl_perf_tlbwec_resv), + .tlb_ctl_perf_tlbwec_noresv(tlb_ctl_perf_tlbwec_noresv), + + .lrat_tag4_hit_status(lrat_tag4_hit_status), + + .tlb_lper_lpn(tlb_lper_lpn), + .tlb_lper_lps(tlb_lper_lps), + .tlb_lper_we(tlb_lper_we), + + .ptereload_req_pte_lat(ptereload_req_pte_lat), + .pte_tag0_lpn(pte_tag0_lpn[64 - `REAL_ADDR_WIDTH:51]), + .pte_tag0_lpid(pte_tag0_lpid), + + .tlb_write(tlb_write), + .tlb_addr(tlb_addr), + .tlb_tag5_write(tlb_tag5_write), + .tlb_delayed_act(tlb_delayed_act), + + .tlb_ctl_dbg_seq_q(tlb_ctl_dbg_seq_q), + .tlb_ctl_dbg_seq_idle(tlb_ctl_dbg_seq_idle), + .tlb_ctl_dbg_seq_any_done_sig(tlb_ctl_dbg_seq_any_done_sig), + .tlb_ctl_dbg_seq_abort(tlb_ctl_dbg_seq_abort), + .tlb_ctl_dbg_any_tlb_req_sig(tlb_ctl_dbg_any_tlb_req_sig), + .tlb_ctl_dbg_any_req_taken_sig(tlb_ctl_dbg_any_req_taken_sig), + .tlb_ctl_dbg_tag0_valid(tlb_ctl_dbg_tag0_valid), + .tlb_ctl_dbg_tag0_thdid(tlb_ctl_dbg_tag0_thdid), + .tlb_ctl_dbg_tag0_type(tlb_ctl_dbg_tag0_type), + .tlb_ctl_dbg_tag0_wq(tlb_ctl_dbg_tag0_wq), + .tlb_ctl_dbg_tag0_gs(tlb_ctl_dbg_tag0_gs), + .tlb_ctl_dbg_tag0_pr(tlb_ctl_dbg_tag0_pr), + .tlb_ctl_dbg_tag0_atsel(tlb_ctl_dbg_tag0_atsel), + .tlb_ctl_dbg_tag5_tlb_write_q(tlb_ctl_dbg_tag5_tlb_write_q), + .tlb_ctl_dbg_resv_valid(tlb_ctl_dbg_resv_valid), + .tlb_ctl_dbg_set_resv(tlb_ctl_dbg_set_resv), + .tlb_ctl_dbg_resv_match_vec_q(tlb_ctl_dbg_resv_match_vec_q), + .tlb_ctl_dbg_any_tag_flush_sig(tlb_ctl_dbg_any_tag_flush_sig), + .tlb_ctl_dbg_resv0_tag0_lpid_match(tlb_ctl_dbg_resv0_tag0_lpid_match), + .tlb_ctl_dbg_resv0_tag0_pid_match(tlb_ctl_dbg_resv0_tag0_pid_match), + .tlb_ctl_dbg_resv0_tag0_as_snoop_match(tlb_ctl_dbg_resv0_tag0_as_snoop_match), + .tlb_ctl_dbg_resv0_tag0_gs_snoop_match(tlb_ctl_dbg_resv0_tag0_gs_snoop_match), + .tlb_ctl_dbg_resv0_tag0_as_tlbwe_match(tlb_ctl_dbg_resv0_tag0_as_tlbwe_match), + .tlb_ctl_dbg_resv0_tag0_gs_tlbwe_match(tlb_ctl_dbg_resv0_tag0_gs_tlbwe_match), + .tlb_ctl_dbg_resv0_tag0_ind_match(tlb_ctl_dbg_resv0_tag0_ind_match), + .tlb_ctl_dbg_resv0_tag0_epn_loc_match(tlb_ctl_dbg_resv0_tag0_epn_loc_match), + .tlb_ctl_dbg_resv0_tag0_epn_glob_match(tlb_ctl_dbg_resv0_tag0_epn_glob_match), + .tlb_ctl_dbg_resv0_tag0_class_match(tlb_ctl_dbg_resv0_tag0_class_match), + .tlb_ctl_dbg_resv1_tag0_lpid_match(tlb_ctl_dbg_resv1_tag0_lpid_match), + .tlb_ctl_dbg_resv1_tag0_pid_match(tlb_ctl_dbg_resv1_tag0_pid_match), + .tlb_ctl_dbg_resv1_tag0_as_snoop_match(tlb_ctl_dbg_resv1_tag0_as_snoop_match), + .tlb_ctl_dbg_resv1_tag0_gs_snoop_match(tlb_ctl_dbg_resv1_tag0_gs_snoop_match), + .tlb_ctl_dbg_resv1_tag0_as_tlbwe_match(tlb_ctl_dbg_resv1_tag0_as_tlbwe_match), + .tlb_ctl_dbg_resv1_tag0_gs_tlbwe_match(tlb_ctl_dbg_resv1_tag0_gs_tlbwe_match), + .tlb_ctl_dbg_resv1_tag0_ind_match(tlb_ctl_dbg_resv1_tag0_ind_match), + .tlb_ctl_dbg_resv1_tag0_epn_loc_match(tlb_ctl_dbg_resv1_tag0_epn_loc_match), + .tlb_ctl_dbg_resv1_tag0_epn_glob_match(tlb_ctl_dbg_resv1_tag0_epn_glob_match), + .tlb_ctl_dbg_resv1_tag0_class_match(tlb_ctl_dbg_resv1_tag0_class_match), + .tlb_ctl_dbg_resv2_tag0_lpid_match(tlb_ctl_dbg_resv2_tag0_lpid_match), + .tlb_ctl_dbg_resv2_tag0_pid_match(tlb_ctl_dbg_resv2_tag0_pid_match), + .tlb_ctl_dbg_resv2_tag0_as_snoop_match(tlb_ctl_dbg_resv2_tag0_as_snoop_match), + .tlb_ctl_dbg_resv2_tag0_gs_snoop_match(tlb_ctl_dbg_resv2_tag0_gs_snoop_match), + .tlb_ctl_dbg_resv2_tag0_as_tlbwe_match(tlb_ctl_dbg_resv2_tag0_as_tlbwe_match), + .tlb_ctl_dbg_resv2_tag0_gs_tlbwe_match(tlb_ctl_dbg_resv2_tag0_gs_tlbwe_match), + .tlb_ctl_dbg_resv2_tag0_ind_match(tlb_ctl_dbg_resv2_tag0_ind_match), + .tlb_ctl_dbg_resv2_tag0_epn_loc_match(tlb_ctl_dbg_resv2_tag0_epn_loc_match), + .tlb_ctl_dbg_resv2_tag0_epn_glob_match(tlb_ctl_dbg_resv2_tag0_epn_glob_match), + .tlb_ctl_dbg_resv2_tag0_class_match(tlb_ctl_dbg_resv2_tag0_class_match), + .tlb_ctl_dbg_resv3_tag0_lpid_match(tlb_ctl_dbg_resv3_tag0_lpid_match), + .tlb_ctl_dbg_resv3_tag0_pid_match(tlb_ctl_dbg_resv3_tag0_pid_match), + .tlb_ctl_dbg_resv3_tag0_as_snoop_match(tlb_ctl_dbg_resv3_tag0_as_snoop_match), + .tlb_ctl_dbg_resv3_tag0_gs_snoop_match(tlb_ctl_dbg_resv3_tag0_gs_snoop_match), + .tlb_ctl_dbg_resv3_tag0_as_tlbwe_match(tlb_ctl_dbg_resv3_tag0_as_tlbwe_match), + .tlb_ctl_dbg_resv3_tag0_gs_tlbwe_match(tlb_ctl_dbg_resv3_tag0_gs_tlbwe_match), + .tlb_ctl_dbg_resv3_tag0_ind_match(tlb_ctl_dbg_resv3_tag0_ind_match), + .tlb_ctl_dbg_resv3_tag0_epn_loc_match(tlb_ctl_dbg_resv3_tag0_epn_loc_match), + .tlb_ctl_dbg_resv3_tag0_epn_glob_match(tlb_ctl_dbg_resv3_tag0_epn_glob_match), + .tlb_ctl_dbg_resv3_tag0_class_match(tlb_ctl_dbg_resv3_tag0_class_match), + .tlb_ctl_dbg_clr_resv_q(tlb_ctl_dbg_clr_resv_q), + .tlb_ctl_dbg_clr_resv_terms(tlb_ctl_dbg_clr_resv_terms) + ); + // End of mmq_tlb_ctl component instantiation + + + //--------------------------------------------------------------------- + // TLB Compare Logic Component Instantiation + //--------------------------------------------------------------------- + + mmq_tlb_cmp #(.MMQ_TLB_CMP_CSWITCH_0TO7(MMQ_TLB_CMP_CSWITCH_0TO7)) mmq_tlb_cmp( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .tc_ccflush_dc(tc_ac_ccflush_dc), + .tc_scan_dis_dc_b(tc_ac_scan_dis_dc_b), + .tc_scan_diag_dc(tc_ac_scan_diag_dc), + .tc_lbist_en_dc(tc_ac_lbist_en_dc), + + .lcb_d_mode_dc(lcb_d_mode_dc), + .lcb_clkoff_dc_b(lcb_clkoff_dc_b), + .lcb_act_dis_dc(lcb_act_dis_dc), + .lcb_mpw1_dc_b(lcb_mpw1_dc_b), + .lcb_mpw2_dc_b(lcb_mpw2_dc_b), + .lcb_delay_lclkr_dc(lcb_delay_lclkr_dc), + + .ac_func_scan_in( {func_scan_in_int[4], func_scan_in_int[5], siv_1[tlb_cmp2_offset]} ), + .ac_func_scan_out( {func_scan_out_int[4], func_scan_out_int[5], sov_1[tlb_cmp2_offset]} ), + + .pc_sg_2(pc_sg_2[1]), + .pc_func_sl_thold_2(pc_func_sl_thold_2[1]), + .pc_func_slp_sl_thold_2(pc_func_slp_sl_thold_2[1]), + .pc_func_slp_nsl_thold_2(pc_func_slp_nsl_thold_2), + .pc_fce_2(pc_fce_2), + .xu_mm_ccr2_notlb_b(xu_mm_ccr2_notlb_b[5]), + .xu_mm_spr_epcr_dmiuh(xu_mm_spr_epcr_dmiuh_sig), + .xu_mm_epcr_dgtmi(xu_mm_epcr_dgtmi_sig), + .xu_mm_msr_gs(xu_mm_msr_gs_sig), + .xu_mm_msr_pr(xu_mm_msr_pr_sig), + .xu_mm_xucr4_mmu_mchk_q(xu_mm_xucr4_mmu_mchk_q), + .lpidr(lpidr_sig), + .mmucr1(mmucr1_sig[10:18]), + .mmucr3_0(mmucr3_0_sig), + .tstmode4k_0(tstmode4k_0_sig), +`ifdef MM_THREADS2 + .mmucr3_1(mmucr3_1_sig), + .tstmode4k_1(tstmode4k_1_sig), +`endif + .mm_iu_ierat_rel_val(mm_iu_ierat_rel_val_sig), + .mm_iu_ierat_rel_data(mm_iu_ierat_rel_data_sig), + + .mm_xu_derat_rel_val(mm_xu_derat_rel_val_sig), + .mm_xu_derat_rel_data(mm_xu_derat_rel_data_sig), + .tlb_cmp_ierat_dup_val(tlb_cmp_ierat_dup_val_sig), + .tlb_cmp_derat_dup_val(tlb_cmp_derat_dup_val_sig), + .tlb_cmp_erat_dup_wait(tlb_cmp_erat_dup_wait_sig), + .ierat_req0_pid(ierat_req0_pid_sig), + .ierat_req0_as(ierat_req0_as_sig), + .ierat_req0_gs(ierat_req0_gs_sig), + .ierat_req0_epn(ierat_req0_epn_sig), + .ierat_req0_thdid(ierat_req0_thdid_sig), + .ierat_req0_valid(ierat_req0_valid_sig), + .ierat_req0_nonspec(ierat_req0_nonspec_sig), + .ierat_req1_pid(ierat_req1_pid_sig), + .ierat_req1_as(ierat_req1_as_sig), + .ierat_req1_gs(ierat_req1_gs_sig), + .ierat_req1_epn(ierat_req1_epn_sig), + .ierat_req1_thdid(ierat_req1_thdid_sig), + .ierat_req1_valid(ierat_req1_valid_sig), + .ierat_req1_nonspec(ierat_req1_nonspec_sig), + .ierat_req2_pid(ierat_req2_pid_sig), + .ierat_req2_as(ierat_req2_as_sig), + .ierat_req2_gs(ierat_req2_gs_sig), + .ierat_req2_epn(ierat_req2_epn_sig), + .ierat_req2_thdid(ierat_req2_thdid_sig), + .ierat_req2_valid(ierat_req2_valid_sig), + .ierat_req2_nonspec(ierat_req2_nonspec_sig), + .ierat_req3_pid(ierat_req3_pid_sig), + .ierat_req3_as(ierat_req3_as_sig), + .ierat_req3_gs(ierat_req3_gs_sig), + .ierat_req3_epn(ierat_req3_epn_sig), + .ierat_req3_thdid(ierat_req3_thdid_sig), + .ierat_req3_valid(ierat_req3_valid_sig), + .ierat_req3_nonspec(ierat_req3_nonspec_sig), + .ierat_iu4_pid(ierat_iu4_pid_sig), + .ierat_iu4_gs(ierat_iu4_gs_sig), + .ierat_iu4_as(ierat_iu4_as_sig), + .ierat_iu4_epn(ierat_iu4_epn_sig), + .ierat_iu4_thdid(ierat_iu4_thdid_sig), + .ierat_iu4_valid(ierat_iu4_valid_sig), + + .derat_req0_lpid(derat_req0_lpid_sig), + .derat_req0_pid(derat_req0_pid_sig), + .derat_req0_as(derat_req0_as_sig), + .derat_req0_gs(derat_req0_gs_sig), + .derat_req0_epn(derat_req0_epn_sig), + .derat_req0_thdid(derat_req0_thdid_sig), + .derat_req0_emq(derat_req0_emq_sig), + .derat_req0_valid(derat_req0_valid_sig), + .derat_req1_lpid(derat_req1_lpid_sig), + .derat_req1_pid(derat_req1_pid_sig), + .derat_req1_as(derat_req1_as_sig), + .derat_req1_gs(derat_req1_gs_sig), + .derat_req1_epn(derat_req1_epn_sig), + .derat_req1_thdid(derat_req1_thdid_sig), + .derat_req1_emq(derat_req1_emq_sig), + .derat_req1_valid(derat_req1_valid_sig), + .derat_req2_lpid(derat_req2_lpid_sig), + .derat_req2_pid(derat_req2_pid_sig), + .derat_req2_as(derat_req2_as_sig), + .derat_req2_gs(derat_req2_gs_sig), + .derat_req2_epn(derat_req2_epn_sig), + .derat_req2_thdid(derat_req2_thdid_sig), + .derat_req2_emq(derat_req2_emq_sig), + .derat_req2_valid(derat_req2_valid_sig), + .derat_req3_lpid(derat_req3_lpid_sig), + .derat_req3_pid(derat_req3_pid_sig), + .derat_req3_as(derat_req3_as_sig), + .derat_req3_gs(derat_req3_gs_sig), + .derat_req3_epn(derat_req3_epn_sig), + .derat_req3_thdid(derat_req3_thdid_sig), + .derat_req3_emq(derat_req3_emq_sig), + .derat_req3_valid(derat_req3_valid_sig), + .derat_ex5_lpid(derat_ex5_lpid_sig), + .derat_ex5_pid(derat_ex5_pid_sig), + .derat_ex5_gs(derat_ex5_gs_sig), + .derat_ex5_as(derat_ex5_as_sig), + .derat_ex5_epn(derat_ex5_epn_sig), + .derat_ex5_thdid(derat_ex5_thdid_sig), + .derat_ex5_valid(derat_ex5_valid_sig), + + .tlb_tag2(tlb_tag2_sig), + .tlb_addr2(tlb_addr2_sig), + .ex6_illeg_instr(ex6_illeg_instr), + + .ierat_req_taken(ierat_req_taken), + .derat_req_taken(derat_req_taken), + .ptereload_req_taken(ptereload_req_taken), + .tlb_tag0_type(tlb_tag0_type[0:1]), + + .lru_dataout(lru_dataout[0:15]), + .tlb_dataout(tlb_dataout), + .tlb_dataina(tlb_dataina), + .tlb_datainb(tlb_datainb), + .lru_write(lru_write[0:15]), + .lru_wr_addr(lru_wr_addr), + .lru_datain(lru_datain[0:15]), + .lru_tag4_dataout(lru_tag4_dataout), + .tlb_addr4(tlb_addr4), + .tlb_tag4_esel(tlb_tag4_esel), + .tlb_tag4_wq(tlb_tag4_wq), + .tlb_tag4_is(tlb_tag4_is), + .tlb_tag4_gs(tlb_tag4_gs), + .tlb_tag4_pr(tlb_tag4_pr), + .tlb_tag4_hes(tlb_tag4_hes), + .tlb_tag4_atsel(tlb_tag4_atsel), + .tlb_tag4_pt(tlb_tag4_pt), + .tlb_tag4_cmp_hit(tlb_tag4_cmp_hit), + .tlb_tag4_way_ind(tlb_tag4_way_ind), + .tlb_tag4_ptereload(tlb_tag4_ptereload), + .tlb_tag4_endflag(tlb_tag4_endflag), + .tlb_tag4_parerr(tlb_tag4_parerr), + .tlb_tag4_parerr_write(tlb_tag4_parerr_write), + .tlb_tag5_parerr_zeroize(tlb_tag5_parerr_zeroize), + .tlb_tag4_nonspec(tlb_tag4_nonspec), + .tlb_tag5_except(tlb_tag5_except), + .tlb_tag4_itag(tlb_tag4_itag_sig), + .tlb_tag5_itag(tlb_tag5_itag_sig), + .tlb_tag5_emq(tlb_tag5_emq_sig), + + .mmucfg_twc(mmucfg_twc), + .mmucfg_lrat(mmucfg_lrat), + .tlb0cfg_pt(tlb0cfg_pt), + .tlb0cfg_gtwe(tlb0cfg_gtwe), + .tlb0cfg_ind(tlb0cfg_ind), + + .mas2_0_wimge(mas2_0_wimge), + .mas3_0_rpnl(mas3_0_rpnl), + .mas3_0_ubits(mas3_0_ubits), + .mas3_0_usxwr(mas3_0_usxwr), + .mas7_0_rpnu(mas7_0_rpnu), + .mas8_0_vf(mas8_0_vf), +`ifdef MM_THREADS2 + .mas2_1_wimge(mas2_1_wimge), + .mas3_1_rpnl(mas3_1_rpnl), + .mas3_1_ubits(mas3_1_ubits), + .mas3_1_usxwr(mas3_1_usxwr), + .mas7_1_rpnu(mas7_1_rpnu), + .mas8_1_vf(mas8_1_vf), +`endif + .tlb_mas0_esel(tlb_mas0_esel), + .tlb_mas1_v(tlb_mas1_v), + .tlb_mas1_iprot(tlb_mas1_iprot), + .tlb_mas1_tid(tlb_mas1_tid), + .tlb_mas1_tid_error(tlb_mas1_tid_error), + .tlb_mas1_ind(tlb_mas1_ind), + .tlb_mas1_ts(tlb_mas1_ts), + .tlb_mas1_ts_error(tlb_mas1_ts_error), + .tlb_mas1_tsize(tlb_mas1_tsize), + .tlb_mas2_epn(tlb_mas2_epn), + .tlb_mas2_epn_error(tlb_mas2_epn_error), + .tlb_mas2_wimge(tlb_mas2_wimge), + .tlb_mas3_rpnl(tlb_mas3_rpnl), + .tlb_mas3_ubits(tlb_mas3_ubits), + .tlb_mas3_usxwr(tlb_mas3_usxwr), + .tlb_mas7_rpnu(tlb_mas7_rpnu), + .tlb_mas8_tgs(tlb_mas8_tgs), + .tlb_mas8_vf(tlb_mas8_vf), + .tlb_mas8_tlpid(tlb_mas8_tlpid), + + .tlb_mmucr1_een(tlb_mmucr1_een), + .tlb_mmucr1_we(tlb_mmucr1_we), + .tlb_mmucr3_thdid(tlb_mmucr3_thdid), + .tlb_mmucr3_resvattr(tlb_mmucr3_resvattr), + .tlb_mmucr3_wlc(tlb_mmucr3_wlc), + .tlb_mmucr3_class(tlb_mmucr3_class), + .tlb_mmucr3_extclass(tlb_mmucr3_extclass), + .tlb_mmucr3_rc(tlb_mmucr3_rc), + .tlb_mmucr3_x(tlb_mmucr3_x), + .tlb_mas_tlbre(tlb_mas_tlbre), + .tlb_mas_tlbsx_hit(tlb_mas_tlbsx_hit), + .tlb_mas_tlbsx_miss(tlb_mas_tlbsx_miss), + .tlb_mas_dtlb_error(tlb_mas_dtlb_error), + .tlb_mas_itlb_error(tlb_mas_itlb_error), + .tlb_mas_thdid(tlb_mas_thdid), + .lrat_tag3_lpn(lrat_tag3_lpn), + .lrat_tag3_rpn(lrat_tag3_rpn), + .lrat_tag3_hit_status(lrat_tag3_hit_status), + .lrat_tag3_hit_entry(lrat_tag3_hit_entry), + .lrat_tag4_lpn(lrat_tag4_lpn), + .lrat_tag4_rpn(lrat_tag4_rpn), + .lrat_tag4_hit_status(lrat_tag4_hit_status), + .lrat_tag4_hit_entry(lrat_tag4_hit_entry), + + .tlb_htw_req_valid(tlb_htw_req_valid), + .tlb_htw_req_tag(tlb_htw_req_tag), + .tlb_htw_req_way(tlb_htw_req_way), + + .tlbwe_back_inv_valid(tlbwe_back_inv_valid_sig), + .tlbwe_back_inv_thdid(tlbwe_back_inv_thdid_sig), + .tlbwe_back_inv_addr(tlbwe_back_inv_addr_sig), + .tlbwe_back_inv_attr(tlbwe_back_inv_attr_sig), + + .ptereload_req_pte_lat(ptereload_req_pte_lat), + + .tlb_ctl_tag2_flush(tlb_ctl_tag2_flush_sig), + .tlb_ctl_tag3_flush(tlb_ctl_tag3_flush_sig), + .tlb_ctl_tag4_flush(tlb_ctl_tag4_flush_sig), + .tlb_resv_match_vec(tlb_resv_match_vec_sig), + + .mm_xu_eratmiss_done(mm_xu_eratmiss_done_sig), + .mm_xu_tlb_miss(mm_xu_tlb_miss_sig), + .mm_xu_tlb_inelig(mm_xu_tlb_inelig_sig), + + .mm_xu_lrat_miss(mm_xu_lrat_miss_sig), + .mm_xu_pt_fault(mm_xu_pt_fault_sig), + .mm_xu_hv_priv(mm_xu_hv_priv_sig), + + .mm_xu_esr_pt(mm_xu_esr_pt_sig), + .mm_xu_esr_data(mm_xu_esr_data_sig), + .mm_xu_esr_epid(mm_xu_esr_epid_sig), + .mm_xu_esr_st(mm_xu_esr_st_sig), + + .mm_xu_cr0_eq(mm_xu_cr0_eq_sig), + .mm_xu_cr0_eq_valid(mm_xu_cr0_eq_valid_sig), + + .mm_xu_tlb_multihit_err(mm_xu_tlb_multihit_err_sig), + .mm_xu_tlb_par_err(mm_xu_tlb_par_err_sig), + .mm_xu_lru_par_err(mm_xu_lru_par_err_sig), + + .mm_xu_ord_tlb_multihit(mm_xu_ord_tlb_multihit_sig), + .mm_xu_ord_tlb_par_err(mm_xu_ord_tlb_par_err_sig), + .mm_xu_ord_lru_par_err(mm_xu_ord_lru_par_err_sig), + + .mm_xu_tlb_miss_ored(mm_xu_tlb_miss_ored_sig), + .mm_xu_lrat_miss_ored(mm_xu_lrat_miss_ored_sig), + .mm_xu_tlb_inelig_ored(mm_xu_tlb_inelig_ored_sig), + .mm_xu_pt_fault_ored(mm_xu_pt_fault_ored_sig), + .mm_xu_hv_priv_ored(mm_xu_hv_priv_ored_sig), + .mm_xu_cr0_eq_ored(mm_xu_cr0_eq_ored_sig), + .mm_xu_cr0_eq_valid_ored(mm_xu_cr0_eq_valid_ored_sig), + + .mm_pc_tlb_multihit_err_ored(mm_pc_tlb_multihit_err_ored_sig), + .mm_pc_tlb_par_err_ored(mm_pc_tlb_par_err_ored_sig), + .mm_pc_lru_par_err_ored(mm_pc_lru_par_err_ored_sig), + + .tlb_delayed_act(tlb_delayed_act[9:16]), + + .tlb_cmp_perf_event_t0(tlb_cmp_perf_event_t0), + .tlb_cmp_perf_event_t1(tlb_cmp_perf_event_t1), + .tlb_cmp_perf_state(tlb_cmp_perf_state), + + .tlb_cmp_perf_miss_direct(tlb_cmp_perf_miss_direct), + .tlb_cmp_perf_hit_direct(tlb_cmp_perf_hit_direct), + .tlb_cmp_perf_hit_indirect(tlb_cmp_perf_hit_indirect), + .tlb_cmp_perf_hit_first_page(tlb_cmp_perf_hit_first_page), + .tlb_cmp_perf_ptereload(tlb_cmp_perf_ptereload), + .tlb_cmp_perf_ptereload_noexcep(tlb_cmp_perf_ptereload_noexcep), + .tlb_cmp_perf_lrat_request(tlb_cmp_perf_lrat_request), + .tlb_cmp_perf_lrat_miss(tlb_cmp_perf_lrat_miss), + .tlb_cmp_perf_pt_fault(tlb_cmp_perf_pt_fault), + .tlb_cmp_perf_pt_inelig(tlb_cmp_perf_pt_inelig), + + .tlb_cmp_dbg_tag4(tlb_cmp_dbg_tag4), + .tlb_cmp_dbg_tag4_wayhit(tlb_cmp_dbg_tag4_wayhit), + .tlb_cmp_dbg_addr4(tlb_cmp_dbg_addr4), + .tlb_cmp_dbg_tag4_way(tlb_cmp_dbg_tag4_way), + .tlb_cmp_dbg_tag4_parerr(tlb_cmp_dbg_tag4_parerr), + .tlb_cmp_dbg_tag4_lru_dataout_q(tlb_cmp_dbg_tag4_lru_dataout_q), + .tlb_cmp_dbg_tag5_tlb_datain_q(tlb_cmp_dbg_tag5_tlb_datain_q), + .tlb_cmp_dbg_tag5_lru_datain_q(tlb_cmp_dbg_tag5_lru_datain_q), + .tlb_cmp_dbg_tag5_lru_write(tlb_cmp_dbg_tag5_lru_write), + .tlb_cmp_dbg_tag5_any_exception(tlb_cmp_dbg_tag5_any_exception), + .tlb_cmp_dbg_tag5_except_type_q(tlb_cmp_dbg_tag5_except_type_q), + .tlb_cmp_dbg_tag5_except_thdid_q(tlb_cmp_dbg_tag5_except_thdid_q), + .tlb_cmp_dbg_tag5_erat_rel_val(tlb_cmp_dbg_tag5_erat_rel_val), + .tlb_cmp_dbg_tag5_erat_rel_data(tlb_cmp_dbg_tag5_erat_rel_data), + .tlb_cmp_dbg_erat_dup_q(tlb_cmp_dbg_erat_dup_q), + .tlb_cmp_dbg_addr_enable(tlb_cmp_dbg_addr_enable), + .tlb_cmp_dbg_pgsize_enable(tlb_cmp_dbg_pgsize_enable), + .tlb_cmp_dbg_class_enable(tlb_cmp_dbg_class_enable), + .tlb_cmp_dbg_extclass_enable(tlb_cmp_dbg_extclass_enable), + .tlb_cmp_dbg_state_enable(tlb_cmp_dbg_state_enable), + .tlb_cmp_dbg_thdid_enable(tlb_cmp_dbg_thdid_enable), + .tlb_cmp_dbg_pid_enable(tlb_cmp_dbg_pid_enable), + .tlb_cmp_dbg_lpid_enable(tlb_cmp_dbg_lpid_enable), + .tlb_cmp_dbg_ind_enable(tlb_cmp_dbg_ind_enable), + .tlb_cmp_dbg_iprot_enable(tlb_cmp_dbg_iprot_enable), + .tlb_cmp_dbg_way0_entry_v(tlb_cmp_dbg_way0_entry_v), + .tlb_cmp_dbg_way0_addr_match(tlb_cmp_dbg_way0_addr_match), + .tlb_cmp_dbg_way0_pgsize_match(tlb_cmp_dbg_way0_pgsize_match), + .tlb_cmp_dbg_way0_class_match(tlb_cmp_dbg_way0_class_match), + .tlb_cmp_dbg_way0_extclass_match(tlb_cmp_dbg_way0_extclass_match), + .tlb_cmp_dbg_way0_state_match(tlb_cmp_dbg_way0_state_match), + .tlb_cmp_dbg_way0_thdid_match(tlb_cmp_dbg_way0_thdid_match), + .tlb_cmp_dbg_way0_pid_match(tlb_cmp_dbg_way0_pid_match), + .tlb_cmp_dbg_way0_lpid_match(tlb_cmp_dbg_way0_lpid_match), + .tlb_cmp_dbg_way0_ind_match(tlb_cmp_dbg_way0_ind_match), + .tlb_cmp_dbg_way0_iprot_match(tlb_cmp_dbg_way0_iprot_match), + .tlb_cmp_dbg_way1_entry_v(tlb_cmp_dbg_way1_entry_v), + .tlb_cmp_dbg_way1_addr_match(tlb_cmp_dbg_way1_addr_match), + .tlb_cmp_dbg_way1_pgsize_match(tlb_cmp_dbg_way1_pgsize_match), + .tlb_cmp_dbg_way1_class_match(tlb_cmp_dbg_way1_class_match), + .tlb_cmp_dbg_way1_extclass_match(tlb_cmp_dbg_way1_extclass_match), + .tlb_cmp_dbg_way1_state_match(tlb_cmp_dbg_way1_state_match), + .tlb_cmp_dbg_way1_thdid_match(tlb_cmp_dbg_way1_thdid_match), + .tlb_cmp_dbg_way1_pid_match(tlb_cmp_dbg_way1_pid_match), + .tlb_cmp_dbg_way1_lpid_match(tlb_cmp_dbg_way1_lpid_match), + .tlb_cmp_dbg_way1_ind_match(tlb_cmp_dbg_way1_ind_match), + .tlb_cmp_dbg_way1_iprot_match(tlb_cmp_dbg_way1_iprot_match), + .tlb_cmp_dbg_way2_entry_v(tlb_cmp_dbg_way2_entry_v), + .tlb_cmp_dbg_way2_addr_match(tlb_cmp_dbg_way2_addr_match), + .tlb_cmp_dbg_way2_pgsize_match(tlb_cmp_dbg_way2_pgsize_match), + .tlb_cmp_dbg_way2_class_match(tlb_cmp_dbg_way2_class_match), + .tlb_cmp_dbg_way2_extclass_match(tlb_cmp_dbg_way2_extclass_match), + .tlb_cmp_dbg_way2_state_match(tlb_cmp_dbg_way2_state_match), + .tlb_cmp_dbg_way2_thdid_match(tlb_cmp_dbg_way2_thdid_match), + .tlb_cmp_dbg_way2_pid_match(tlb_cmp_dbg_way2_pid_match), + .tlb_cmp_dbg_way2_lpid_match(tlb_cmp_dbg_way2_lpid_match), + .tlb_cmp_dbg_way2_ind_match(tlb_cmp_dbg_way2_ind_match), + .tlb_cmp_dbg_way2_iprot_match(tlb_cmp_dbg_way2_iprot_match), + .tlb_cmp_dbg_way3_entry_v(tlb_cmp_dbg_way3_entry_v), + .tlb_cmp_dbg_way3_addr_match(tlb_cmp_dbg_way3_addr_match), + .tlb_cmp_dbg_way3_pgsize_match(tlb_cmp_dbg_way3_pgsize_match), + .tlb_cmp_dbg_way3_class_match(tlb_cmp_dbg_way3_class_match), + .tlb_cmp_dbg_way3_extclass_match(tlb_cmp_dbg_way3_extclass_match), + .tlb_cmp_dbg_way3_state_match(tlb_cmp_dbg_way3_state_match), + .tlb_cmp_dbg_way3_thdid_match(tlb_cmp_dbg_way3_thdid_match), + .tlb_cmp_dbg_way3_pid_match(tlb_cmp_dbg_way3_pid_match), + .tlb_cmp_dbg_way3_lpid_match(tlb_cmp_dbg_way3_lpid_match), + .tlb_cmp_dbg_way3_ind_match(tlb_cmp_dbg_way3_ind_match), + + .tlb_cmp_dbg_way3_iprot_match(tlb_cmp_dbg_way3_iprot_match) + ); + // End of mmq_tlb_cmp component instantiation + + + //--------------------------------------------------------------------- + // TLB Logical to Real Address Translation Logic Component Instantiation + //--------------------------------------------------------------------- + + //work.mmq_tlb_lrat #(.`THREADS(`THREADS), .`THDID_WIDTH(`THDID_WIDTH), .`EPN_WIDTH(`EPN_WIDTH), .`SPR_DATA_WIDTH(`SPR_DATA_WIDTH), .`REAL_ADDR_WIDTH(`REAL_ADDR_WIDTH), .`RPN_WIDTH(`RPN_WIDTH), .`LPID_WIDTH(`LPID_WIDTH), .`EXPAND_TYPE(`EXPAND_TYPE)) mmq_tlb_lrat( + mmq_tlb_lrat mmq_tlb_lrat( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .tc_ccflush_dc(tc_ac_ccflush_dc), + .tc_scan_dis_dc_b(tc_ac_scan_dis_dc_b), + .tc_scan_diag_dc(tc_ac_scan_diag_dc), + .tc_lbist_en_dc(tc_ac_lbist_en_dc), + + .lcb_d_mode_dc(lcb_d_mode_dc), + .lcb_clkoff_dc_b(lcb_clkoff_dc_b), + .lcb_act_dis_dc(lcb_act_dis_dc), + .lcb_mpw1_dc_b(lcb_mpw1_dc_b), + .lcb_mpw2_dc_b(lcb_mpw2_dc_b), + .lcb_delay_lclkr_dc(lcb_delay_lclkr_dc), + + .ac_func_scan_in(func_scan_in_int[6]), + .ac_func_scan_out(func_scan_out_int[6]), + + .pc_sg_2(pc_sg_2[1]), + .pc_func_sl_thold_2(pc_func_sl_thold_2[1]), + .pc_func_slp_sl_thold_2(pc_func_slp_sl_thold_2[1]), + + .xu_mm_ccr2_notlb_b(xu_mm_ccr2_notlb_b[6]), + .tlb_delayed_act(tlb_delayed_act[20:23]), + .mmucr2_act_override(mmucr2_sig[3]), + + .tlb_ctl_ex3_valid(tlb_ctl_ex3_valid_sig), + .tlb_ctl_ex3_ttype(tlb_ctl_ex3_ttype_sig), + .tlb_ctl_ex3_hv_state(tlb_ctl_ex3_hv_state_sig), + .xu_ex3_flush(xu_ex3_flush_sig[0:`MM_THREADS-1]), + .xu_ex4_flush(xu_ex4_flush_sig), + .xu_ex5_flush(xu_ex5_flush_sig), + .tlb_tag0_epn(tlb_tag0_epn[64 - `REAL_ADDR_WIDTH:51]), + .tlb_tag0_thdid(tlb_tag0_thdid), + .tlb_tag0_type(tlb_tag0_type), + .tlb_tag0_lpid(tlb_tag0_lpid), + .tlb_tag0_atsel(tlb_tag0_atsel), + .tlb_tag0_size(tlb_tag0_size), + .tlb_tag0_addr_cap(tlb_tag0_addr_cap), + .ex6_illeg_instr(ex6_illeg_instr), + + .pte_tag0_lpn(pte_tag0_lpn[64 - `REAL_ADDR_WIDTH:51]), + .pte_tag0_lpid(pte_tag0_lpid), + .mas0_0_atsel(mas0_0_atsel), + .mas0_0_esel(mas0_0_esel), + .mas0_0_hes(mas0_0_hes), + .mas0_0_wq(mas0_0_wq), + .mas1_0_v(mas1_0_v), + .mas1_0_tsize(mas1_0_tsize), + .mas2_0_epn(mas2_0_epn[64 - `REAL_ADDR_WIDTH:51]), + .mas7_0_rpnu(mas7_0_rpnu), + .mas3_0_rpnl(mas3_0_rpnl[32:51]), + .mas8_0_tlpid(mas8_0_tlpid), + .mmucr3_0_x(mmucr3_0_sig[49]), +`ifdef MM_THREADS2 + .mas0_1_atsel(mas0_1_atsel), + .mas0_1_esel(mas0_1_esel), + .mas0_1_hes(mas0_1_hes), + .mas0_1_wq(mas0_1_wq), + .mas1_1_v(mas1_1_v), + .mas1_1_tsize(mas1_1_tsize), + .mas2_1_epn(mas2_1_epn[64 - `REAL_ADDR_WIDTH:51]), + .mas7_1_rpnu(mas7_1_rpnu), + .mas3_1_rpnl(mas3_1_rpnl[32:51]), + .mas8_1_tlpid(mas8_1_tlpid), + .mmucr3_1_x(mmucr3_1_sig[49]), +`endif + .lrat_mmucr3_x(lrat_mmucr3_x), + .lrat_mas0_esel(lrat_mas0_esel), + .lrat_mas1_v(lrat_mas1_v), + .lrat_mas1_tsize(lrat_mas1_tsize), + .lrat_mas2_epn(lrat_mas2_epn), + .lrat_mas3_rpnl(lrat_mas3_rpnl), + .lrat_mas7_rpnu(lrat_mas7_rpnu), + .lrat_mas8_tlpid(lrat_mas8_tlpid), + .lrat_mas_tlbre(lrat_mas_tlbre), + .lrat_mas_tlbsx_hit(lrat_mas_tlbsx_hit), + .lrat_mas_tlbsx_miss(lrat_mas_tlbsx_miss), + .lrat_mas_thdid(lrat_mas_thdid), + + .lrat_tag3_lpn(lrat_tag3_lpn), + .lrat_tag3_rpn(lrat_tag3_rpn), + .lrat_tag3_hit_status(lrat_tag3_hit_status), + .lrat_tag3_hit_entry(lrat_tag3_hit_entry), + .lrat_tag4_lpn(lrat_tag4_lpn), + .lrat_tag4_rpn(lrat_tag4_rpn), + .lrat_tag4_hit_status(lrat_tag4_hit_status), + .lrat_tag4_hit_entry(lrat_tag4_hit_entry), + + .lrat_dbg_tag1_addr_enable(lrat_dbg_tag1_addr_enable), + .lrat_dbg_tag2_matchline_q(lrat_dbg_tag2_matchline_q), + .lrat_dbg_entry0_addr_match(lrat_dbg_entry0_addr_match), + .lrat_dbg_entry0_lpid_match(lrat_dbg_entry0_lpid_match), + .lrat_dbg_entry0_entry_v(lrat_dbg_entry0_entry_v), + .lrat_dbg_entry0_entry_x(lrat_dbg_entry0_entry_x), + .lrat_dbg_entry0_size(lrat_dbg_entry0_size), + .lrat_dbg_entry1_addr_match(lrat_dbg_entry1_addr_match), + .lrat_dbg_entry1_lpid_match(lrat_dbg_entry1_lpid_match), + .lrat_dbg_entry1_entry_v(lrat_dbg_entry1_entry_v), + .lrat_dbg_entry1_entry_x(lrat_dbg_entry1_entry_x), + .lrat_dbg_entry1_size(lrat_dbg_entry1_size), + .lrat_dbg_entry2_addr_match(lrat_dbg_entry2_addr_match), + .lrat_dbg_entry2_lpid_match(lrat_dbg_entry2_lpid_match), + .lrat_dbg_entry2_entry_v(lrat_dbg_entry2_entry_v), + .lrat_dbg_entry2_entry_x(lrat_dbg_entry2_entry_x), + .lrat_dbg_entry2_size(lrat_dbg_entry2_size), + .lrat_dbg_entry3_addr_match(lrat_dbg_entry3_addr_match), + .lrat_dbg_entry3_lpid_match(lrat_dbg_entry3_lpid_match), + .lrat_dbg_entry3_entry_v(lrat_dbg_entry3_entry_v), + .lrat_dbg_entry3_entry_x(lrat_dbg_entry3_entry_x), + .lrat_dbg_entry3_size(lrat_dbg_entry3_size), + .lrat_dbg_entry4_addr_match(lrat_dbg_entry4_addr_match), + .lrat_dbg_entry4_lpid_match(lrat_dbg_entry4_lpid_match), + .lrat_dbg_entry4_entry_v(lrat_dbg_entry4_entry_v), + .lrat_dbg_entry4_entry_x(lrat_dbg_entry4_entry_x), + .lrat_dbg_entry4_size(lrat_dbg_entry4_size), + .lrat_dbg_entry5_addr_match(lrat_dbg_entry5_addr_match), + .lrat_dbg_entry5_lpid_match(lrat_dbg_entry5_lpid_match), + .lrat_dbg_entry5_entry_v(lrat_dbg_entry5_entry_v), + .lrat_dbg_entry5_entry_x(lrat_dbg_entry5_entry_x), + .lrat_dbg_entry5_size(lrat_dbg_entry5_size), + .lrat_dbg_entry6_addr_match(lrat_dbg_entry6_addr_match), + .lrat_dbg_entry6_lpid_match(lrat_dbg_entry6_lpid_match), + .lrat_dbg_entry6_entry_v(lrat_dbg_entry6_entry_v), + .lrat_dbg_entry6_entry_x(lrat_dbg_entry6_entry_x), + .lrat_dbg_entry6_size(lrat_dbg_entry6_size), + .lrat_dbg_entry7_addr_match(lrat_dbg_entry7_addr_match), + .lrat_dbg_entry7_lpid_match(lrat_dbg_entry7_lpid_match), + .lrat_dbg_entry7_entry_v(lrat_dbg_entry7_entry_v), + .lrat_dbg_entry7_entry_x(lrat_dbg_entry7_entry_x), + .lrat_dbg_entry7_size(lrat_dbg_entry7_size) + ); + // End of mmq_tlb_lrat component instantiation + + + //--------------------------------------------------------------------- + // Hardware Table Walker Logic Component Instantiation + //--------------------------------------------------------------------- + + //work.mmq_htw #(.`THREADS(`THREADS), .`THDID_WIDTH(`THDID_WIDTH), .`PID_WIDTH(`PID_WIDTH), .`LPID_WIDTH(`LPID_WIDTH), .`EPN_WIDTH(`EPN_WIDTH), .`REAL_ADDR_WIDTH(`REAL_ADDR_WIDTH), .`RPN_WIDTH(`RPN_WIDTH), .`TLB_WAY_WIDTH(`TLB_WAY_WIDTH), .`TLB_WORD_WIDTH(`TLB_WORD_WIDTH), .`TLB_TAG_WIDTH(`TLB_TAG_WIDTH), .`PTE_WIDTH(`PTE_WIDTH), .`EXPAND_TYPE(`EXPAND_TYPE)) mmq_htw( + mmq_htw mmq_htw( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .tc_ccflush_dc(tc_ac_ccflush_dc), + .tc_scan_dis_dc_b(tc_ac_scan_dis_dc_b), + .tc_scan_diag_dc(tc_ac_scan_diag_dc), + .tc_lbist_en_dc(tc_ac_lbist_en_dc), + + .lcb_d_mode_dc(lcb_d_mode_dc), + .lcb_clkoff_dc_b(lcb_clkoff_dc_b), + .lcb_act_dis_dc(lcb_act_dis_dc), + .lcb_mpw1_dc_b(lcb_mpw1_dc_b), + .lcb_mpw2_dc_b(lcb_mpw2_dc_b), + .lcb_delay_lclkr_dc(lcb_delay_lclkr_dc), + + .ac_func_scan_in( func_scan_in_int[7:8] ), + .ac_func_scan_out( func_scan_out_int[7:8] ), + + .pc_sg_2(pc_sg_2[1]), + .pc_func_sl_thold_2(pc_func_sl_thold_2[1]), + .pc_func_slp_sl_thold_2(pc_func_slp_sl_thold_2[1]), + + .xu_mm_ccr2_notlb_b(xu_mm_ccr2_notlb_b[7]), + + .tlb_delayed_act(tlb_delayed_act[24:28]), + .mmucr2_act_override(mmucr2_sig[4]), + + .tlb_ctl_tag2_flush(tlb_ctl_tag2_flush_sig), + .tlb_ctl_tag3_flush(tlb_ctl_tag3_flush_sig), + .tlb_ctl_tag4_flush(tlb_ctl_tag4_flush_sig), + + .tlb_tag2(tlb_tag2_sig), + .tlb_tag5_except(tlb_tag5_except), + + .tlb_htw_req_valid(tlb_htw_req_valid), + .tlb_htw_req_tag(tlb_htw_req_tag), + .tlb_htw_req_way(tlb_htw_req_way), + .htw_lsu_req_valid(htw_lsu_req_valid), + .htw_lsu_thdid(htw_lsu_thdid), + .htw_dbg_lsu_thdid(htw_dbg_lsu_thdid), + .htw_lsu_ttype(htw_lsu_ttype), + .htw_lsu_wimge(htw_lsu_wimge), + .htw_lsu_u(htw_lsu_u), + .htw_lsu_addr(htw_lsu_addr), + .htw_lsu_req_taken(htw_lsu_req_taken), + .htw_quiesce(htw_quiesce_sig), + + .htw_req0_valid(htw_req0_valid), + .htw_req0_thdid(htw_req0_thdid), + .htw_req0_type(htw_req0_type), + .htw_req1_valid(htw_req1_valid), + .htw_req1_thdid(htw_req1_thdid), + .htw_req1_type(htw_req1_type), + .htw_req2_valid(htw_req2_valid), + .htw_req2_thdid(htw_req2_thdid), + .htw_req2_type(htw_req2_type), + .htw_req3_valid(htw_req3_valid), + .htw_req3_thdid(htw_req3_thdid), + .htw_req3_type(htw_req3_type), + .ptereload_req_valid(ptereload_req_valid), + .ptereload_req_tag(ptereload_req_tag), + .ptereload_req_pte(ptereload_req_pte), + .ptereload_req_taken(ptereload_req_taken), + .an_ac_reld_core_tag(an_ac_reld_core_tag), + .an_ac_reld_data(an_ac_reld_data), + .an_ac_reld_data_vld(an_ac_reld_data_vld), + .an_ac_reld_ecc_err(an_ac_reld_ecc_err), + .an_ac_reld_ecc_err_ue(an_ac_reld_ecc_err_ue), + .an_ac_reld_qw(an_ac_reld_qw[58:59]), + .an_ac_reld_ditc(an_ac_reld_ditc), + .an_ac_reld_crit_qw(an_ac_reld_crit_qw), + + .htw_dbg_seq_idle(htw_dbg_seq_idle), + .htw_dbg_pte0_seq_idle(htw_dbg_pte0_seq_idle), + .htw_dbg_pte1_seq_idle(htw_dbg_pte1_seq_idle), + .htw_dbg_seq_q(htw_dbg_seq_q), + .htw_dbg_inptr_q(htw_dbg_inptr_q), + .htw_dbg_pte0_seq_q(htw_dbg_pte0_seq_q), + .htw_dbg_pte1_seq_q(htw_dbg_pte1_seq_q), + .htw_dbg_ptereload_ptr_q(htw_dbg_ptereload_ptr_q), + .htw_dbg_lsuptr_q(htw_dbg_lsuptr_q), + .htw_dbg_req_valid_q(htw_dbg_req_valid_q), + .htw_dbg_resv_valid_vec(htw_dbg_resv_valid_vec), + .htw_dbg_tag4_clr_resv_q(htw_dbg_tag4_clr_resv_q), + .htw_dbg_tag4_clr_resv_terms(htw_dbg_tag4_clr_resv_terms), + .htw_dbg_pte0_score_ptr_q(htw_dbg_pte0_score_ptr_q), + .htw_dbg_pte0_score_cl_offset_q(htw_dbg_pte0_score_cl_offset_q), + .htw_dbg_pte0_score_error_q(htw_dbg_pte0_score_error_q), + .htw_dbg_pte0_score_qwbeat_q(htw_dbg_pte0_score_qwbeat_q), + .htw_dbg_pte0_score_pending_q(htw_dbg_pte0_score_pending_q), + .htw_dbg_pte0_score_ibit_q(htw_dbg_pte0_score_ibit_q), + .htw_dbg_pte0_score_dataval_q(htw_dbg_pte0_score_dataval_q), + .htw_dbg_pte0_reld_for_me_tm1(htw_dbg_pte0_reld_for_me_tm1), + .htw_dbg_pte1_score_ptr_q(htw_dbg_pte1_score_ptr_q), + .htw_dbg_pte1_score_cl_offset_q(htw_dbg_pte1_score_cl_offset_q), + .htw_dbg_pte1_score_error_q(htw_dbg_pte1_score_error_q), + .htw_dbg_pte1_score_qwbeat_q(htw_dbg_pte1_score_qwbeat_q), + .htw_dbg_pte1_score_pending_q(htw_dbg_pte1_score_pending_q), + .htw_dbg_pte1_score_ibit_q(htw_dbg_pte1_score_ibit_q), + .htw_dbg_pte1_score_dataval_q(htw_dbg_pte1_score_dataval_q), + + .htw_dbg_pte1_reld_for_me_tm1(htw_dbg_pte1_reld_for_me_tm1) + ); + end + endgenerate + // End of mmq_htw component instantiation + + generate + if (`EXPAND_TLB_TYPE == 1) + begin : tlb_gen_noarrays + assign tlb_dataout[0:`TLB_WAY_WIDTH - 1] = tlb_dataina; + assign tlb_dataout[`TLB_WAY_WIDTH:2 * `TLB_WAY_WIDTH - 1] = tlb_dataina; + assign tlb_dataout[2 * `TLB_WAY_WIDTH:3 * `TLB_WAY_WIDTH - 1] = tlb_dataina; + assign tlb_dataout[3 * `TLB_WAY_WIDTH:4 * `TLB_WAY_WIDTH - 1] = tlb_dataina; + assign lru_dataout = lru_datain; + assign time_scan_int[1:5] = {5{1'b0}}; + assign repr_scan_int[1:5] = {5{1'b0}}; + assign abst_scan_int[1:6] = {6{1'b0}}; + end + endgenerate + + //--------------------------------------------------------------------- + // TLB Instantiation + //--------------------------------------------------------------------- + generate + if (`EXPAND_TLB_TYPE == 2) + begin : tlb_gen_instance + + //tri.tri_128x168_1w_0 #(.`EXPAND_TYPE(`EXPAND_TYPE)) tlb_array0( + tri_128x168_1w_0 tlb_array0( + .gnd(gnd), + .vdd(vdd), + .vcs(vdd), + .nclk(nclk), + .act(tlb_delayed_act[17]), + .ccflush_dc(tc_ac_ccflush_dc), + .scan_dis_dc_b(tc_ac_scan_dis_dc_b), + .scan_diag_dc(tc_ac_scan_diag_dc), + .repr_scan_in(repr_scan_int[0]), + .time_scan_in(time_scan_int[0]), + .abst_scan_in(abst_scan_int[0]), + .repr_scan_out(repr_scan_int[1]), + .time_scan_out(time_scan_int[1]), + .abst_scan_out(abst_scan_int[1]), + .lcb_d_mode_dc(g6t_gptr_lcb_d_mode_dc), + .lcb_clkoff_dc_b(g6t_gptr_lcb_clkoff_dc_b), + .lcb_act_dis_dc(g6t_gptr_lcb_act_dis_dc), + .lcb_mpw1_dc_b(g6t_gptr_lcb_mpw1_dc_b), + .lcb_mpw2_dc_b(g6t_gptr_lcb_mpw2_dc_b), + .lcb_delay_lclkr_dc(g6t_gptr_lcb_delay_lclkr_dc), + + .tri_lcb_mpw1_dc_b(lcb_mpw1_dc_b[0]), + .tri_lcb_mpw2_dc_b(lcb_mpw2_dc_b), + .tri_lcb_delay_lclkr_dc(lcb_delay_lclkr_dc[0]), + .tri_lcb_clkoff_dc_b(lcb_clkoff_dc_b), + .tri_lcb_act_dis_dc(lcb_act_dis_dc), + + .lcb_sg_1(pc_sg_1[0]), + .lcb_time_sg_0(pc_sg_0[0]), + .lcb_repr_sg_0(pc_sg_0[0]), + .lcb_abst_sl_thold_0(pc_abst_sl_thold_0), + .lcb_repr_sl_thold_0(pc_repr_sl_thold_0), + .lcb_time_sl_thold_0(pc_time_sl_thold_0), + .lcb_ary_nsl_thold_0(pc_ary_slp_nsl_thold_0), + .tc_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc), + .abist_en_1(pc_mm_abist_ena_dc), + .din_abist(pc_mm_abist_di_g6t_2r_q), + .abist_cmp_en(pc_mm_abist_wl128_comp_ena_q), + .abist_raw_b_dc(pc_mm_abist_raw_dc_b), + .data_cmp_abist(pc_mm_abist_dcomp_g6t_2r_q), + .addr_abist(pc_mm_abist_raddr_0_q[3:9]), + .r_wb_abist(pc_mm_abist_g6t_r_wb_q), + .lcb_bolt_sl_thold_0(pc_mm_bolt_sl_thold_0), + .pc_bo_enable_2(pc_mm_bo_enable_2), + .pc_bo_reset(pc_mm_bo_reset), + .pc_bo_unload(pc_mm_bo_unload), + .pc_bo_repair(pc_mm_bo_repair), + .pc_bo_shdata(pc_mm_bo_shdata), + .pc_bo_select(pc_mm_bo_select[0]), + .bo_pc_failout(mm_pc_bo_fail[0]), + .bo_pc_diagloop(mm_pc_bo_diagout[0]), + + .write_enable(tlb_write[0]), + .addr(tlb_addr), + .data_in(tlb_dataina), + .data_out(tlb_dataout[0:`TLB_WAY_WIDTH - 1]) + ); + + //tri.tri_128x168_1w_0 #(.`EXPAND_TYPE(`EXPAND_TYPE)) tlb_array1( + tri_128x168_1w_0 tlb_array1( + .gnd(gnd), + .vdd(vdd), + .vcs(vdd), + .nclk(nclk), + .act(tlb_delayed_act[17]), + + .ccflush_dc(tc_ac_ccflush_dc), + .scan_dis_dc_b(tc_ac_scan_dis_dc_b), + .scan_diag_dc(tc_ac_scan_diag_dc), + .repr_scan_in(repr_scan_int[1]), + .time_scan_in(time_scan_int[1]), + .abst_scan_in(abst_scan_int[1]), + .repr_scan_out(repr_scan_int[2]), + .time_scan_out(time_scan_int[2]), + .abst_scan_out(abst_scan_int[2]), + .lcb_d_mode_dc(g6t_gptr_lcb_d_mode_dc), + .lcb_clkoff_dc_b(g6t_gptr_lcb_clkoff_dc_b), + .lcb_act_dis_dc(g6t_gptr_lcb_act_dis_dc), + .lcb_mpw1_dc_b(g6t_gptr_lcb_mpw1_dc_b), + .lcb_mpw2_dc_b(g6t_gptr_lcb_mpw2_dc_b), + .lcb_delay_lclkr_dc(g6t_gptr_lcb_delay_lclkr_dc), + + .tri_lcb_mpw1_dc_b(lcb_mpw1_dc_b[0]), + .tri_lcb_mpw2_dc_b(lcb_mpw2_dc_b), + .tri_lcb_delay_lclkr_dc(lcb_delay_lclkr_dc[0]), + .tri_lcb_clkoff_dc_b(lcb_clkoff_dc_b), + .tri_lcb_act_dis_dc(lcb_act_dis_dc), + + .lcb_sg_1(pc_sg_1[0]), + .lcb_time_sg_0(pc_sg_0[0]), + .lcb_repr_sg_0(pc_sg_0[0]), + .lcb_abst_sl_thold_0(pc_abst_sl_thold_0), + .lcb_repr_sl_thold_0(pc_repr_sl_thold_0), + .lcb_time_sl_thold_0(pc_time_sl_thold_0), + .lcb_ary_nsl_thold_0(pc_ary_slp_nsl_thold_0), + .tc_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc), + .abist_en_1(pc_mm_abist_ena_dc), + .din_abist(pc_mm_abist_di_g6t_2r_q), + .abist_cmp_en(pc_mm_abist_wl128_comp_ena_q), + .abist_raw_b_dc(pc_mm_abist_raw_dc_b), + .data_cmp_abist(pc_mm_abist_dcomp_g6t_2r_q), + .addr_abist(pc_mm_abist_raddr_0_q[3:9]), + .r_wb_abist(pc_mm_abist_g6t_r_wb_q), + .lcb_bolt_sl_thold_0(pc_mm_bolt_sl_thold_0), + .pc_bo_enable_2(pc_mm_bo_enable_2), + .pc_bo_reset(pc_mm_bo_reset), + .pc_bo_unload(pc_mm_bo_unload), + .pc_bo_repair(pc_mm_bo_repair), + .pc_bo_shdata(pc_mm_bo_shdata), + .pc_bo_select(pc_mm_bo_select[1]), + .bo_pc_failout(mm_pc_bo_fail[1]), + .bo_pc_diagloop(mm_pc_bo_diagout[1]), + + .write_enable(tlb_write[1]), + .addr(tlb_addr), + .data_in(tlb_dataina), + .data_out(tlb_dataout[`TLB_WAY_WIDTH:2 * `TLB_WAY_WIDTH - 1]) + ); + + //tri.tri_128x168_1w_0 #(.`EXPAND_TYPE(`EXPAND_TYPE)) tlb_array2( + tri_128x168_1w_0 tlb_array2( + .gnd(gnd), + .vdd(vdd), + .vcs(vdd), + .nclk(nclk), + .act(tlb_delayed_act[18]), + .ccflush_dc(tc_ac_ccflush_dc), + .scan_dis_dc_b(tc_ac_scan_dis_dc_b), + .scan_diag_dc(tc_ac_scan_diag_dc), + .repr_scan_in(repr_scan_int[2]), + .time_scan_in(time_scan_int[2]), + .abst_scan_in(abst_scan_int[3]), + .repr_scan_out(repr_scan_int[3]), + .time_scan_out(time_scan_int[3]), + .abst_scan_out(abst_scan_int[4]), + .lcb_d_mode_dc(g6t_gptr_lcb_d_mode_dc), + .lcb_clkoff_dc_b(g6t_gptr_lcb_clkoff_dc_b), + .lcb_act_dis_dc(g6t_gptr_lcb_act_dis_dc), + .lcb_mpw1_dc_b(g6t_gptr_lcb_mpw1_dc_b), + .lcb_mpw2_dc_b(g6t_gptr_lcb_mpw2_dc_b), + .lcb_delay_lclkr_dc(g6t_gptr_lcb_delay_lclkr_dc), + + .tri_lcb_mpw1_dc_b(lcb_mpw1_dc_b[0]), + .tri_lcb_mpw2_dc_b(lcb_mpw2_dc_b), + .tri_lcb_delay_lclkr_dc(lcb_delay_lclkr_dc[0]), + .tri_lcb_clkoff_dc_b(lcb_clkoff_dc_b), + .tri_lcb_act_dis_dc(lcb_act_dis_dc), + + .lcb_sg_1(pc_sg_1[1]), + .lcb_time_sg_0(pc_sg_0[1]), + .lcb_repr_sg_0(pc_sg_0[1]), + .lcb_abst_sl_thold_0(pc_abst_sl_thold_0), + .lcb_repr_sl_thold_0(pc_repr_sl_thold_0), + .lcb_time_sl_thold_0(pc_time_sl_thold_0), + .lcb_ary_nsl_thold_0(pc_ary_slp_nsl_thold_0), + .tc_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc), + .abist_en_1(pc_mm_abist_ena_dc), + .din_abist(pc_mm_abist_di_g6t_2r_q), + .abist_cmp_en(pc_mm_abist_wl128_comp_ena_q), + .abist_raw_b_dc(pc_mm_abist_raw_dc_b), + .data_cmp_abist(pc_mm_abist_dcomp_g6t_2r_q), + .addr_abist(pc_mm_abist_raddr_0_q[3:9]), + .r_wb_abist(pc_mm_abist_g6t_r_wb_q), + .lcb_bolt_sl_thold_0(pc_mm_bolt_sl_thold_0), + .pc_bo_enable_2(pc_mm_bo_enable_2), + .pc_bo_reset(pc_mm_bo_reset), + .pc_bo_unload(pc_mm_bo_unload), + .pc_bo_repair(pc_mm_bo_repair), + .pc_bo_shdata(pc_mm_bo_shdata), + .pc_bo_select(pc_mm_bo_select[2]), + .bo_pc_failout(mm_pc_bo_fail[2]), + .bo_pc_diagloop(mm_pc_bo_diagout[2]), + + .write_enable(tlb_write[2]), + .addr(tlb_addr), + .data_in(tlb_datainb), + .data_out(tlb_dataout[2 * `TLB_WAY_WIDTH:3 * `TLB_WAY_WIDTH - 1]) + ); + + //tri.tri_128x168_1w_0 #(.`EXPAND_TYPE(`EXPAND_TYPE)) tlb_array3( + tri_128x168_1w_0 tlb_array3( + .gnd(gnd), + .vdd(vdd), + .vcs(vdd), + .nclk(nclk), + .act(tlb_delayed_act[18]), + + .ccflush_dc(tc_ac_ccflush_dc), + .scan_dis_dc_b(tc_ac_scan_dis_dc_b), + .scan_diag_dc(tc_ac_scan_diag_dc), + .repr_scan_in(repr_scan_int[3]), + .time_scan_in(time_scan_int[3]), + .abst_scan_in(abst_scan_int[4]), + .repr_scan_out(repr_scan_int[4]), + .time_scan_out(time_scan_int[4]), + .abst_scan_out(abst_scan_int[5]), + .lcb_d_mode_dc(g6t_gptr_lcb_d_mode_dc), + .lcb_clkoff_dc_b(g6t_gptr_lcb_clkoff_dc_b), + .lcb_act_dis_dc(g6t_gptr_lcb_act_dis_dc), + .lcb_mpw1_dc_b(g6t_gptr_lcb_mpw1_dc_b), + .lcb_mpw2_dc_b(g6t_gptr_lcb_mpw2_dc_b), + .lcb_delay_lclkr_dc(g6t_gptr_lcb_delay_lclkr_dc), + + .tri_lcb_mpw1_dc_b(lcb_mpw1_dc_b[0]), + .tri_lcb_mpw2_dc_b(lcb_mpw2_dc_b), + .tri_lcb_delay_lclkr_dc(lcb_delay_lclkr_dc[0]), + .tri_lcb_clkoff_dc_b(lcb_clkoff_dc_b), + .tri_lcb_act_dis_dc(lcb_act_dis_dc), + + .lcb_sg_1(pc_sg_1[1]), + .lcb_time_sg_0(pc_sg_0[1]), + .lcb_repr_sg_0(pc_sg_0[1]), + .lcb_abst_sl_thold_0(pc_abst_sl_thold_0), + .lcb_repr_sl_thold_0(pc_repr_sl_thold_0), + .lcb_time_sl_thold_0(pc_time_sl_thold_0), + .lcb_ary_nsl_thold_0(pc_ary_slp_nsl_thold_0), + .tc_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc), + .abist_en_1(pc_mm_abist_ena_dc), + .din_abist(pc_mm_abist_di_g6t_2r_q), + .abist_cmp_en(pc_mm_abist_wl128_comp_ena_q), + .abist_raw_b_dc(pc_mm_abist_raw_dc_b), + .data_cmp_abist(pc_mm_abist_dcomp_g6t_2r_q), + .addr_abist(pc_mm_abist_raddr_0_q[3:9]), + .r_wb_abist(pc_mm_abist_g6t_r_wb_q), + .lcb_bolt_sl_thold_0(pc_mm_bolt_sl_thold_0), + .pc_bo_enable_2(pc_mm_bo_enable_2), + .pc_bo_reset(pc_mm_bo_reset), + .pc_bo_unload(pc_mm_bo_unload), + .pc_bo_repair(pc_mm_bo_repair), + .pc_bo_shdata(pc_mm_bo_shdata), + .pc_bo_select(pc_mm_bo_select[3]), + .bo_pc_failout(mm_pc_bo_fail[3]), + .bo_pc_diagloop(mm_pc_bo_diagout[3]), + + .write_enable(tlb_write[3]), + .addr(tlb_addr), + .data_in(tlb_datainb), + .data_out(tlb_dataout[3 * `TLB_WAY_WIDTH:4 * `TLB_WAY_WIDTH - 1]) + ); + + //--------------------------------------------------------------------- + // LRU Instantiation + //--------------------------------------------------------------------- + + //tri.tri_128x16_1r1w_1 #(.`EXPAND_TYPE(`EXPAND_TYPE)) lru_array0( + tri_128x16_1r1w_1 lru_array0( + .gnd(gnd), + .vdd(vdd), + .vcs(vdd), + .nclk(nclk), + .rd_act(tlb_delayed_act[19]), + .wr_act(tlb_delayed_act[33]), + + .lcb_d_mode_dc(g8t_gptr_lcb_d_mode_dc), + .lcb_clkoff_dc_b(g8t_gptr_lcb_clkoff_dc_b), + .lcb_mpw1_dc_b(g8t_gptr_lcb_mpw1_dc_b), + .lcb_mpw2_dc_b(g8t_gptr_lcb_mpw2_dc_b), + .lcb_delay_lclkr_dc(g8t_gptr_lcb_delay_lclkr_dc), + .tri_lcb_mpw1_dc_b(lcb_mpw1_dc_b[0]), + .tri_lcb_mpw2_dc_b(lcb_mpw2_dc_b), + .tri_lcb_delay_lclkr_dc(lcb_delay_lclkr_dc[0]), + .tri_lcb_clkoff_dc_b(lcb_clkoff_dc_b), + .tri_lcb_act_dis_dc(lcb_act_dis_dc), + + .ccflush_dc(tc_ac_ccflush_dc), + .scan_dis_dc_b(tc_ac_scan_dis_dc_b), + .scan_diag_dc(tc_ac_scan_diag_dc), + .func_scan_in(tidn), + .func_scan_out(unused_dc_array_scan[0]), + + .lcb_sg_0(pc_sg_0[1]), + .lcb_sl_thold_0_b(pc_func_slp_sl_thold_0_b[1]), + + .lcb_time_sl_thold_0(pc_time_sl_thold_0), + .lcb_abst_sl_thold_0(pc_abst_slp_sl_thold_0), + .lcb_repr_sl_thold_0(pc_repr_sl_thold_0), + .lcb_ary_nsl_thold_0(pc_ary_slp_nsl_thold_0), + + .time_scan_in(time_scan_int[4]), + .time_scan_out(time_scan_int[5]), + .repr_scan_in(repr_scan_int[4]), + .repr_scan_out(repr_scan_int[5]), + .abst_scan_in(abst_scan_int[5]), + .abst_scan_out(abst_scan_int[6]), + + .abist_di(pc_mm_abist_di_0_q), + .abist_bw_odd(pc_mm_abist_g8t_bw_1_q), + .abist_bw_even(pc_mm_abist_g8t_bw_0_q), + .abist_wr_adr(pc_mm_abist_waddr_0_q[3:9]), + .wr_abst_act(pc_mm_abist_g8t_wenb_q), + .abist_rd0_adr(pc_mm_abist_raddr_0_q[3:9]), + .rd0_abst_act(pc_mm_abist_g8t1p_renb_0_q), + .tc_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc), + .abist_ena_1(pc_mm_abist_ena_dc), + .abist_g8t_rd0_comp_ena(pc_mm_abist_wl128_comp_ena_q), + .abist_raw_dc_b(pc_mm_abist_raw_dc_b), + .obs0_abist_cmp(pc_mm_abist_g8t_dcomp_q), + + .lcb_bolt_sl_thold_0(pc_mm_bolt_sl_thold_0), + .pc_bo_enable_2(pc_mm_bo_enable_2), + .pc_bo_reset(pc_mm_bo_reset), + .pc_bo_unload(pc_mm_bo_unload), + .pc_bo_repair(pc_mm_bo_repair), + .pc_bo_shdata(pc_mm_bo_shdata), + .pc_bo_select(pc_mm_bo_select[4]), + .bo_pc_failout(mm_pc_bo_fail[4]), + .bo_pc_diagloop(mm_pc_bo_diagout[4]), + + .bw(lru_write[0:`LRU_WIDTH - 1]), + .wr_adr(lru_wr_addr), + .rd_adr(lru_rd_addr), + .di(lru_datain[0:`LRU_WIDTH - 1]), + .dout(lru_dataout[0:`LRU_WIDTH - 1]) + ); + end + endgenerate + + assign xu_mm_ex2_eff_addr_sig = xu_mm_ex2_eff_addr; + //--------------------------------------------------------------------- + // end of TLB logic + //--------------------------------------------------------------------- + + //--------------------------------------------------------------------- + // Scan + //--------------------------------------------------------------------- + assign siv_0[0:scan_right_0] = {sov_0[1:scan_right_0], func_scan_in_int[0]}; + assign func_scan_out_int[0] = sov_0[0]; + assign siv_1[0:scan_right_1] = {sov_1[1:scan_right_1], func_scan_in_int[9]}; + assign func_scan_out_int[9] = sov_1[0]; + assign time_scan_int[0] = time_scan_in_int; + assign repr_scan_int[0] = repr_scan_in_int; + assign abst_scan_int[0] = abst_scan_in_int[0]; + assign abst_scan_int[3] = abst_scan_in_int[1]; + assign abst_scan_out_int[0] = abst_scan_int[2]; + assign abst_scan_out_int[1] = abst_scan_int[6]; + assign time_scan_out_int = time_scan_int[5]; + assign repr_scan_out_int = repr_scan_int[5]; + assign bcfg_scan_out_int = bcfg_scan_in_int; + assign dcfg_scan_out_int = dcfg_scan_in_int; + assign bsiv[0] = ccfg_scan_in_int; + assign ccfg_scan_out_int = bsov[boot_scan_right]; + assign unused_dc[0] = 1'b0; + assign unused_dc[1] = pc_ary_nsl_thold_0; + assign unused_dc[2:3] = pc_func_sl_thold_0[0:1]; + assign unused_dc[4:5] = pc_func_sl_thold_0_b[0:1]; + assign unused_dc[6:7] = pc_func_slp_sl_thold_0[0:1]; + assign unused_dc[8] = g8t_gptr_lcb_act_dis_dc; + assign unused_dc[9:11] = pc_mm_abist_raddr_0_q[0:2]; + assign unused_dc[12:14] = pc_mm_abist_waddr_0_q[0:2]; + assign unused_dc[15] = pc_func_slp_sl_thold_0_b[0]; +`ifdef MM_THREADS2 + assign unused_dc[16] = |(mmucr0_0_sig[0:1]) | |(mmucr0_1_sig[0:1]); +`else + assign unused_dc[16] = |(mmucr0_0_sig[0:1]); +`endif + + generate + if (`MM_THREADS - `THREADS == 1) + begin : mmUnusedDCThreads1 + assign unused_dc[17] = |(mm_iu_ierat_pid_sig[`MM_THREADS-1]) | |(mm_iu_ierat_mmucr0_sig[`MM_THREADS-1]) | |(mm_xu_derat_pid_sig[`MM_THREADS-1]) | |(mm_xu_derat_mmucr0_sig[`MM_THREADS-1]); + assign unused_dc[18:19] = {2{1'b0}}; + end + endgenerate + + generate + if (`MM_THREADS - `THREADS == 2) + begin : mmUnusedDCThreads2 + assign unused_dc[17] = |(mm_iu_ierat_pid_sig[`MM_THREADS-2]) | |(mm_iu_ierat_mmucr0_sig[`MM_THREADS-2]) | |(mm_xu_derat_pid_sig[`MM_THREADS-2]) | |(mm_xu_derat_mmucr0_sig[`MM_THREADS-2]); + assign unused_dc[18] = |(mm_iu_ierat_pid_sig[`MM_THREADS-1]) | |(mm_iu_ierat_mmucr0_sig[`MM_THREADS-1]) | |(mm_xu_derat_pid_sig[`MM_THREADS-1]) | |(mm_xu_derat_mmucr0_sig[`MM_THREADS-1]); + assign unused_dc[19] = 1'b0; + end + endgenerate + + generate + if (`MM_THREADS - `THREADS == 3) + begin : mmUnusedDCThreads3 + assign unused_dc[17] = |(mm_iu_ierat_pid_sig[`MM_THREADS-3]) | |(mm_iu_ierat_mmucr0_sig[`MM_THREADS-3]) | |(mm_xu_derat_pid_sig[`MM_THREADS-3]) | |(mm_xu_derat_mmucr0_sig[`MM_THREADS-3]); + assign unused_dc[18] = |(mm_iu_ierat_pid_sig[`MM_THREADS-2]) | |(mm_iu_ierat_mmucr0_sig[`MM_THREADS-2]) | |(mm_xu_derat_pid_sig[`MM_THREADS-2]) | |(mm_xu_derat_mmucr0_sig[`MM_THREADS-2]); + assign unused_dc[19] = |(mm_iu_ierat_pid_sig[`MM_THREADS-1]) | |(mm_iu_ierat_mmucr0_sig[`MM_THREADS-1]) | |(mm_xu_derat_pid_sig[`MM_THREADS-1]) | |(mm_xu_derat_mmucr0_sig[`MM_THREADS-1]); + end + endgenerate + + generate + if (`THREADS == `MM_THREADS) + begin : mmUnusedDCThreadsEQ + assign unused_dc[17:19] = {3{1'b0}}; + end + endgenerate + + generate + if (`MM_THREADS < 4) + begin : mmUnusedACT + assign unused_dc[20] = |(tlb_delayed_act[29 + `MM_THREADS:32]); + assign unused_dc[21] = |(tlb_req_quiesce_sig[`MM_THREADS:3]); + assign unused_dc[22] = |(htw_quiesce_sig[`MM_THREADS:3]); + assign unused_dc[23] = |(htw_lsu_thdid[`MM_THREADS:3]); + end + endgenerate + + generate + if (`MM_THREADS == 4) + begin : mmUsedACT + assign unused_dc[20:23] = {4{1'b0}}; + end + endgenerate + + assign unused_dc[24:27] = mmucr1_sig[0:3]; + assign unused_dc[28:31] = mmucr1_sig[6:9]; + assign unused_dc[32:43] = mmucr1_sig[20:31]; + assign unused_dc[44:65] = tlb_tag0_epn[0:21]; + assign unused_dc[66:70] = xu_mm_ccr2_notlb_b[8:12]; + +`ifdef THREADS1 + assign unused_dc[71] = |(cp_mm_except_taken_t1_sig); +`else + assign unused_dc[71] = 1'b0; +`endif + + generate + if (`THREADS < `MM_THREADS) + begin : mmUnusedDCThreads + assign unused_dc[72:72 + `MM_THREADS-`THREADS-1] = mm_xu_ord_n_flush_req_sig[`THREADS:`MM_THREADS-1] | mm_xu_ord_np1_flush_req_sig[`THREADS:`MM_THREADS-1] | + mm_xu_ord_read_done_sig[`THREADS:`MM_THREADS-1] | mm_xu_ord_write_done_sig[`THREADS:`MM_THREADS-1] | mm_xu_lrat_miss_sig[`THREADS:`MM_THREADS-1] | + mm_xu_pt_fault_sig[`THREADS:`MM_THREADS-1] | mm_xu_hv_priv_sig[`THREADS:`MM_THREADS-1] | mm_xu_esr_pt_sig[`THREADS:`MM_THREADS-1] | + mm_xu_esr_data_sig[`THREADS:`MM_THREADS-1] | mm_xu_esr_epid_sig[`THREADS:`MM_THREADS-1] | mm_xu_esr_st_sig[`THREADS:`MM_THREADS-1] | + mm_xu_quiesce_sig[`THREADS:`MM_THREADS-1] | mm_pc_tlb_req_quiesce_sig[`THREADS:`MM_THREADS-1] | mm_pc_tlb_ctl_quiesce_sig[`THREADS:`MM_THREADS-1] | + mm_pc_htw_quiesce_sig[`THREADS:`MM_THREADS-1] | mm_pc_inval_quiesce_sig[`THREADS:`MM_THREADS-1] | + mm_xu_local_snoop_reject_sig[`THREADS:`MM_THREADS-1] | + mm_xu_tlb_multihit_err_sig[`THREADS:`MM_THREADS-1] | mm_xu_tlb_par_err_sig[`THREADS:`MM_THREADS-1] | mm_xu_lru_par_err_sig[`THREADS:`MM_THREADS-1] | + mm_xu_ex3_flush_req_sig[`THREADS:`MM_THREADS-1] | mm_iu_hold_req_sig[`THREADS:`MM_THREADS-1] | + mm_iu_hold_done_sig[`THREADS:`MM_THREADS-1] | mm_iu_bus_snoop_hold_req_sig[`THREADS:`MM_THREADS-1] | mm_iu_bus_snoop_hold_done_sig[`THREADS:`MM_THREADS-1] | + mm_iu_flush_req_sig[`THREADS:`MM_THREADS-1] | mm_iu_tlbi_complete_sig[`THREADS:`MM_THREADS-1] | mm_xu_illeg_instr_sig[`THREADS:`MM_THREADS-1] | + mm_xu_cr0_eq_sig[`THREADS:`MM_THREADS-1] | mm_xu_cr0_eq_valid_sig[`THREADS:`MM_THREADS-1] | mm_xu_lsu_req_sig[`THREADS:`MM_THREADS-1]; + end + endgenerate + + assign mm_xu_derat_rel_itag = tlb_tag5_itag_sig; + assign mm_xu_derat_rel_emq = tlb_tag5_emq_sig; + +endmodule diff --git a/dev/verilog/work/mmq_dbg.v b/dev/verilog/work/mmq_dbg.v new file mode 100755 index 0000000..3ea41b2 --- /dev/null +++ b/dev/verilog/work/mmq_dbg.v @@ -0,0 +1,1821 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +//******************************************************************** +//* +//* TITLE: debug event mux +//* +//* NAME: mmq_dbg.v +//* +//********************************************************************* + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" +`include "mmu_a2o.vh" + + +module mmq_dbg( + + inout vdd, + inout gnd, + (* pin_data ="PIN_FUNCTION=/G_CLK/" *) + input [0:`NCLK_WIDTH-1] nclk, + + input pc_func_slp_sl_thold_2, + input pc_func_slp_nsl_thold_2, + input pc_sg_2, + input pc_fce_2, + input tc_ac_ccflush_dc, + + input lcb_clkoff_dc_b, + input lcb_act_dis_dc, + input lcb_d_mode_dc, + input lcb_delay_lclkr_dc, + input lcb_mpw1_dc_b, + input lcb_mpw2_dc_b, + +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + input scan_in, +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + output scan_out, + + input [8:11] mmucr2, + + input pc_mm_trace_bus_enable, + input [0:10] pc_mm_debug_mux1_ctrls, + + input [0:`DEBUG_TRACE_WIDTH-1] debug_bus_in, + output [0:`DEBUG_TRACE_WIDTH-1] debug_bus_out, + + // Instruction Trace (HTM) Control Signals: + // 0 - ac_an_coretrace_first_valid + // 1 - ac_an_coretrace_valid + // 2:3 - ac_an_coretrace_type[0:1] + input [0:3] coretrace_ctrls_in, + output [0:3] coretrace_ctrls_out, + + //--------- spr debug signals + input spr_dbg_match_64b, // these match sigs are spr_int phase + input spr_dbg_match_any_mmu, + input spr_dbg_match_any_mas, + input spr_dbg_match_pid, + input spr_dbg_match_lpidr, + input spr_dbg_match_mmucr0, + input spr_dbg_match_mmucr1, + input spr_dbg_match_mmucr2, + input spr_dbg_match_mmucr3, + + input spr_dbg_match_mmucsr0, + input spr_dbg_match_mmucfg, + input spr_dbg_match_tlb0cfg, + input spr_dbg_match_tlb0ps, + input spr_dbg_match_lratcfg, + input spr_dbg_match_lratps, + input spr_dbg_match_eptcfg, + input spr_dbg_match_lper, + input spr_dbg_match_lperu, + + input spr_dbg_match_mas0, + input spr_dbg_match_mas1, + input spr_dbg_match_mas2, + input spr_dbg_match_mas2u, + input spr_dbg_match_mas3, + input spr_dbg_match_mas4, + input spr_dbg_match_mas5, + input spr_dbg_match_mas6, + input spr_dbg_match_mas7, + input spr_dbg_match_mas8, + input spr_dbg_match_mas01_64b, + input spr_dbg_match_mas56_64b, + input spr_dbg_match_mas73_64b, + input spr_dbg_match_mas81_64b, + + input spr_dbg_slowspr_val_int, // spr_int phase + input spr_dbg_slowspr_rw_int, + input [0:1] spr_dbg_slowspr_etid_int, + input [0:9] spr_dbg_slowspr_addr_int, + input spr_dbg_slowspr_val_out, // spr_out phase + input spr_dbg_slowspr_done_out, + input [0:63] spr_dbg_slowspr_data_out, + + //--------- mmq_inval debug signals + input [0:4] inval_dbg_seq_q, + input inval_dbg_seq_idle, + input inval_dbg_seq_snoop_inprogress, + input inval_dbg_seq_snoop_done, + input inval_dbg_seq_local_done, + input inval_dbg_seq_tlb0fi_done, + input inval_dbg_seq_tlbwe_snoop_done, + input inval_dbg_ex6_valid, + input [0:1] inval_dbg_ex6_thdid, // encoded + input [0:2] inval_dbg_ex6_ttype, // encoded + input inval_dbg_snoop_forme, + input inval_dbg_snoop_local_reject, + input [2:8] inval_dbg_an_ac_back_inv_q, // 2=valid b, 3=target b, 4=L, 5=GS, 6=IND, 7=local, 8=reject + input [0:7] inval_dbg_an_ac_back_inv_lpar_id_q, + input [22:63] inval_dbg_an_ac_back_inv_addr_q, + input [0:2] inval_dbg_snoop_valid_q, + input [0:2] inval_dbg_snoop_ack_q, + input [0:34] inval_dbg_snoop_attr_q, + input [18:19] inval_dbg_snoop_attr_tlb_spec_q, + input [17:51] inval_dbg_snoop_vpn_q, + input [0:1] inval_dbg_lsu_tokens_q, + + //--------- tlb_req debug signals + input tlb_req_dbg_ierat_iu5_valid_q, + input [0:1] tlb_req_dbg_ierat_iu5_thdid, + input [0:3] tlb_req_dbg_ierat_iu5_state_q, + input [0:1] tlb_req_dbg_ierat_inptr_q, + input [0:1] tlb_req_dbg_ierat_outptr_q, + input [0:3] tlb_req_dbg_ierat_req_valid_q, + input [0:3] tlb_req_dbg_ierat_req_nonspec_q, + input [0:7] tlb_req_dbg_ierat_req_thdid, // encoded + input [0:3] tlb_req_dbg_ierat_req_dup_q, + input tlb_req_dbg_derat_ex6_valid_q, + input [0:1] tlb_req_dbg_derat_ex6_thdid, // encoded + input [0:3] tlb_req_dbg_derat_ex6_state_q, + input [0:1] tlb_req_dbg_derat_inptr_q, + input [0:1] tlb_req_dbg_derat_outptr_q, + input [0:3] tlb_req_dbg_derat_req_valid_q, + input [0:7] tlb_req_dbg_derat_req_thdid, // encoded + input [0:7] tlb_req_dbg_derat_req_ttype_q, + input [0:3] tlb_req_dbg_derat_req_dup_q, + + //--------- tlb_ctl debug signals + input [0:5] tlb_ctl_dbg_seq_q, // tlb_seq_q + input tlb_ctl_dbg_seq_idle, + input tlb_ctl_dbg_seq_any_done_sig, + input tlb_ctl_dbg_seq_abort, + input tlb_ctl_dbg_any_tlb_req_sig, + input tlb_ctl_dbg_any_req_taken_sig, + input tlb_ctl_dbg_tag0_valid, + input [0:1] tlb_ctl_dbg_tag0_thdid, // encoded + input [0:2] tlb_ctl_dbg_tag0_type, // encoded + input [0:1] tlb_ctl_dbg_tag0_wq, // encoded + input tlb_ctl_dbg_tag0_gs, + input tlb_ctl_dbg_tag0_pr, + input tlb_ctl_dbg_tag0_atsel, + input [0:3] tlb_ctl_dbg_tag5_tlb_write_q, + input [0:3] tlb_ctl_dbg_resv_valid, + input [0:3] tlb_ctl_dbg_set_resv, + input [0:3] tlb_ctl_dbg_resv_match_vec_q, + input tlb_ctl_dbg_any_tag_flush_sig, + input tlb_ctl_dbg_resv0_tag0_lpid_match, + input tlb_ctl_dbg_resv0_tag0_pid_match, + input tlb_ctl_dbg_resv0_tag0_as_snoop_match, + input tlb_ctl_dbg_resv0_tag0_gs_snoop_match, + input tlb_ctl_dbg_resv0_tag0_as_tlbwe_match, + input tlb_ctl_dbg_resv0_tag0_gs_tlbwe_match, + input tlb_ctl_dbg_resv0_tag0_ind_match, + input tlb_ctl_dbg_resv0_tag0_epn_loc_match, + input tlb_ctl_dbg_resv0_tag0_epn_glob_match, + input tlb_ctl_dbg_resv0_tag0_class_match, + input tlb_ctl_dbg_resv1_tag0_lpid_match, + input tlb_ctl_dbg_resv1_tag0_pid_match, + input tlb_ctl_dbg_resv1_tag0_as_snoop_match, + input tlb_ctl_dbg_resv1_tag0_gs_snoop_match, + input tlb_ctl_dbg_resv1_tag0_as_tlbwe_match, + input tlb_ctl_dbg_resv1_tag0_gs_tlbwe_match, + input tlb_ctl_dbg_resv1_tag0_ind_match, + input tlb_ctl_dbg_resv1_tag0_epn_loc_match, + input tlb_ctl_dbg_resv1_tag0_epn_glob_match, + input tlb_ctl_dbg_resv1_tag0_class_match, + input tlb_ctl_dbg_resv2_tag0_lpid_match, + input tlb_ctl_dbg_resv2_tag0_pid_match, + input tlb_ctl_dbg_resv2_tag0_as_snoop_match, + input tlb_ctl_dbg_resv2_tag0_gs_snoop_match, + input tlb_ctl_dbg_resv2_tag0_as_tlbwe_match, + input tlb_ctl_dbg_resv2_tag0_gs_tlbwe_match, + input tlb_ctl_dbg_resv2_tag0_ind_match, + input tlb_ctl_dbg_resv2_tag0_epn_loc_match, + input tlb_ctl_dbg_resv2_tag0_epn_glob_match, + input tlb_ctl_dbg_resv2_tag0_class_match, + input tlb_ctl_dbg_resv3_tag0_lpid_match, + input tlb_ctl_dbg_resv3_tag0_pid_match, + input tlb_ctl_dbg_resv3_tag0_as_snoop_match, + input tlb_ctl_dbg_resv3_tag0_gs_snoop_match, + input tlb_ctl_dbg_resv3_tag0_as_tlbwe_match, + input tlb_ctl_dbg_resv3_tag0_gs_tlbwe_match, + input tlb_ctl_dbg_resv3_tag0_ind_match, + input tlb_ctl_dbg_resv3_tag0_epn_loc_match, + input tlb_ctl_dbg_resv3_tag0_epn_glob_match, + input tlb_ctl_dbg_resv3_tag0_class_match, + input [0:3] tlb_ctl_dbg_clr_resv_q, // tag5 + input [0:3] tlb_ctl_dbg_clr_resv_terms, // tag5, threadwise condensed into to tlbivax, tlbilx, tlbwe, ptereload + + //--------- tlb_cmp debug signals + input [0:`TLB_TAG_WIDTH-1] tlb_cmp_dbg_tag4, + input [0:`TLB_WAYS] tlb_cmp_dbg_tag4_wayhit, + input [0:`TLB_ADDR_WIDTH-1] tlb_cmp_dbg_addr4, + input [0:`TLB_WAY_WIDTH-1] tlb_cmp_dbg_tag4_way, + input [0:4] tlb_cmp_dbg_tag4_parerr, + input [0:`LRU_WIDTH-5] tlb_cmp_dbg_tag4_lru_dataout_q, + input [0:`TLB_WAY_WIDTH-1] tlb_cmp_dbg_tag5_tlb_datain_q, + input [0:`LRU_WIDTH-5] tlb_cmp_dbg_tag5_lru_datain_q, + input tlb_cmp_dbg_tag5_lru_write, + input tlb_cmp_dbg_tag5_any_exception, + input [0:3] tlb_cmp_dbg_tag5_except_type_q, + input [0:1] tlb_cmp_dbg_tag5_except_thdid_q, + input [0:9] tlb_cmp_dbg_tag5_erat_rel_val, + input [0:131] tlb_cmp_dbg_tag5_erat_rel_data, + input [0:19] tlb_cmp_dbg_erat_dup_q, + + input [0:8] tlb_cmp_dbg_addr_enable, + input tlb_cmp_dbg_pgsize_enable, + input tlb_cmp_dbg_class_enable, + input [0:1] tlb_cmp_dbg_extclass_enable, + input [0:1] tlb_cmp_dbg_state_enable, + input tlb_cmp_dbg_thdid_enable, + input tlb_cmp_dbg_pid_enable, + input tlb_cmp_dbg_lpid_enable, + input tlb_cmp_dbg_ind_enable, + input tlb_cmp_dbg_iprot_enable, + input tlb_cmp_dbg_way0_entry_v, // these are tag3 versions + input tlb_cmp_dbg_way0_addr_match, + input tlb_cmp_dbg_way0_pgsize_match, + input tlb_cmp_dbg_way0_class_match, + input tlb_cmp_dbg_way0_extclass_match, + input tlb_cmp_dbg_way0_state_match, + input tlb_cmp_dbg_way0_thdid_match, + input tlb_cmp_dbg_way0_pid_match, + input tlb_cmp_dbg_way0_lpid_match, + input tlb_cmp_dbg_way0_ind_match, + input tlb_cmp_dbg_way0_iprot_match, + input tlb_cmp_dbg_way1_entry_v, + input tlb_cmp_dbg_way1_addr_match, + input tlb_cmp_dbg_way1_pgsize_match, + input tlb_cmp_dbg_way1_class_match, + input tlb_cmp_dbg_way1_extclass_match, + input tlb_cmp_dbg_way1_state_match, + input tlb_cmp_dbg_way1_thdid_match, + input tlb_cmp_dbg_way1_pid_match, + input tlb_cmp_dbg_way1_lpid_match, + input tlb_cmp_dbg_way1_ind_match, + input tlb_cmp_dbg_way1_iprot_match, + input tlb_cmp_dbg_way2_entry_v, + input tlb_cmp_dbg_way2_addr_match, + input tlb_cmp_dbg_way2_pgsize_match, + input tlb_cmp_dbg_way2_class_match, + input tlb_cmp_dbg_way2_extclass_match, + input tlb_cmp_dbg_way2_state_match, + input tlb_cmp_dbg_way2_thdid_match, + input tlb_cmp_dbg_way2_pid_match, + input tlb_cmp_dbg_way2_lpid_match, + input tlb_cmp_dbg_way2_ind_match, + input tlb_cmp_dbg_way2_iprot_match, + input tlb_cmp_dbg_way3_entry_v, + input tlb_cmp_dbg_way3_addr_match, + input tlb_cmp_dbg_way3_pgsize_match, + input tlb_cmp_dbg_way3_class_match, + input tlb_cmp_dbg_way3_extclass_match, + input tlb_cmp_dbg_way3_state_match, + input tlb_cmp_dbg_way3_thdid_match, + input tlb_cmp_dbg_way3_pid_match, + input tlb_cmp_dbg_way3_lpid_match, + input tlb_cmp_dbg_way3_ind_match, + input tlb_cmp_dbg_way3_iprot_match, + + //--------- lrat debug signals + input lrat_dbg_tag1_addr_enable, + input [0:7] lrat_dbg_tag2_matchline_q, + input lrat_dbg_entry0_addr_match, // tag2 + input lrat_dbg_entry0_lpid_match, + input lrat_dbg_entry0_entry_v, + input lrat_dbg_entry0_entry_x, + input [0:3] lrat_dbg_entry0_size, + input lrat_dbg_entry1_addr_match, // tag2 + input lrat_dbg_entry1_lpid_match, + input lrat_dbg_entry1_entry_v, + input lrat_dbg_entry1_entry_x, + input [0:3] lrat_dbg_entry1_size, + input lrat_dbg_entry2_addr_match, // tag2 + input lrat_dbg_entry2_lpid_match, + input lrat_dbg_entry2_entry_v, + input lrat_dbg_entry2_entry_x, + input [0:3] lrat_dbg_entry2_size, + input lrat_dbg_entry3_addr_match, // tag2 + input lrat_dbg_entry3_lpid_match, + input lrat_dbg_entry3_entry_v, + input lrat_dbg_entry3_entry_x, + input [0:3] lrat_dbg_entry3_size, + input lrat_dbg_entry4_addr_match, // tag2 + input lrat_dbg_entry4_lpid_match, + input lrat_dbg_entry4_entry_v, + input lrat_dbg_entry4_entry_x, + input [0:3] lrat_dbg_entry4_size, + input lrat_dbg_entry5_addr_match, // tag2 + input lrat_dbg_entry5_lpid_match, + input lrat_dbg_entry5_entry_v, + input lrat_dbg_entry5_entry_x, + input [0:3] lrat_dbg_entry5_size, + input lrat_dbg_entry6_addr_match, // tag2 + input lrat_dbg_entry6_lpid_match, + input lrat_dbg_entry6_entry_v, + input lrat_dbg_entry6_entry_x, + input [0:3] lrat_dbg_entry6_size, + input lrat_dbg_entry7_addr_match, // tag2 + input lrat_dbg_entry7_lpid_match, + input lrat_dbg_entry7_entry_v, + input lrat_dbg_entry7_entry_x, + input [0:3] lrat_dbg_entry7_size, + + //--------- mmq_htw debug signals + input htw_dbg_seq_idle, + input htw_dbg_pte0_seq_idle, + input htw_dbg_pte1_seq_idle, + input [0:1] htw_dbg_seq_q, + input [0:1] htw_dbg_inptr_q, + input [0:2] htw_dbg_pte0_seq_q, + input [0:2] htw_dbg_pte1_seq_q, + input htw_dbg_ptereload_ptr_q, + input [0:1] htw_dbg_lsuptr_q, + input [0:3] htw_dbg_req_valid_q, + input [0:3] htw_dbg_resv_valid_vec, + input [0:3] htw_dbg_tag4_clr_resv_q, + input [0:3] htw_dbg_tag4_clr_resv_terms, // tag4, threadwise condensed into to tlbivax, tlbilx, tlbwe, ptereload + input [0:1] htw_dbg_pte0_score_ptr_q, + input [58:60] htw_dbg_pte0_score_cl_offset_q, + input [0:2] htw_dbg_pte0_score_error_q, + input [0:3] htw_dbg_pte0_score_qwbeat_q, // 4 beats of data per CL + input htw_dbg_pte0_score_pending_q, + input htw_dbg_pte0_score_ibit_q, + input htw_dbg_pte0_score_dataval_q, + input htw_dbg_pte0_reld_for_me_tm1, + input [0:1] htw_dbg_pte1_score_ptr_q, + input [58:60] htw_dbg_pte1_score_cl_offset_q, + input [0:2] htw_dbg_pte1_score_error_q, + input [0:3] htw_dbg_pte1_score_qwbeat_q, // 4 beats of data per CL + input htw_dbg_pte1_score_pending_q, + input htw_dbg_pte1_score_ibit_q, + input htw_dbg_pte1_score_dataval_q, + input htw_dbg_pte1_reld_for_me_tm1, + + //--------- lsu debug signals + input [0:`THREADS-1] mm_xu_lsu_req, + // 0=tlbivax_op, 1=tlbi_complete, 2=mmu read with core_tag=01100, 3=mmu read with core_tag=01101 + input [0:1] mm_xu_lsu_ttype, + input [0:4] mm_xu_lsu_wimge, + input [0:3] mm_xu_lsu_u, + input [22:63] mm_xu_lsu_addr, + input [0:7] mm_xu_lsu_lpid, // tlbivax data + input mm_xu_lsu_gs, // tlbivax data + input mm_xu_lsu_ind, // tlbivax data + input mm_xu_lsu_lbit, // -- tlbivax data, "L" bit, for large vs. small + input xu_mm_lsu_token, + + //--------- misc top level debug signals + input tlb_mas_tlbre, + input tlb_mas_tlbsx_hit, + input tlb_mas_tlbsx_miss, + input tlb_mas_dtlb_error, + input tlb_mas_itlb_error, + input [0:`THDID_WIDTH-1] tlb_mas_thdid, + input lrat_mas_tlbre, + input lrat_mas_tlbsx_hit, + input lrat_mas_tlbsx_miss, + input [0:`THDID_WIDTH-1] lrat_mas_thdid, + input [0:3] lrat_tag3_hit_status, // val,hit,multihit,inval_pgsize + input [0:2] lrat_tag3_hit_entry, + + input tlb_seq_ierat_req, + input tlb_seq_derat_req, + input [0:`THREADS-1] mm_xu_hold_req, + input [0:`THREADS-1] xu_mm_hold_ack, + input [0:`THREADS-1] mm_xu_hold_done, + input mmucsr0_tlb0fi, + input tlbwe_back_inv_valid, + input [18:19] tlbwe_back_inv_attr, + input xu_mm_lmq_stq_empty, + input iu_mm_lmq_empty, + input [0:`THREADS-1] mm_xu_eratmiss_done, + input [0:`THREADS-1] mm_iu_barrier_done, + input [0:`THREADS-1] mm_xu_ex3_flush_req, + input [0:`THREADS-1] mm_xu_illeg_instr, + input [0:3] lrat_tag4_hit_status, + input [0:2] lrat_tag4_hit_entry, + input [0:`THREADS-1] mm_xu_cr0_eq, // for record forms + input [0:`THREADS-1] mm_xu_cr0_eq_valid, // for record forms + input tlb_htw_req_valid, + input htw_lsu_req_valid, + input [0:1] htw_dbg_lsu_thdid, + input [0:1] htw_lsu_ttype, + input [22:63] htw_lsu_addr, + input ptereload_req_taken, + + input [0:63] ptereload_req_pte // pte entry + +); + + + parameter DEBUG_LATCH_WIDTH = 372; + parameter TRIGGER_LATCH_WIDTH = 48; + + wire pc_mm_trace_bus_enable_q; // input=>pc_mm_trace_bus_enable, sleep=>Y, needs_sreset=>0 +//======================================================================================== + wire [0:10] pc_mm_debug_mux1_ctrls_q; // input=>pc_mm_debug_mux1_ctrls, act=>pc_mm_trace_bus_enable_q, sleep=>Y, needs_sreset=>0 + wire [0:10] pc_mm_debug_mux1_ctrls_loc_d; + wire [0:10] pc_mm_debug_mux1_ctrls_loc_q; + wire [0:`DEBUG_TRIGGER_WIDTH-1] trigger_data_out_d; + wire [0:`DEBUG_TRIGGER_WIDTH-1] trigger_data_out_q; + wire [0:`DEBUG_TRACE_WIDTH-1] trace_data_out_d; + wire [0:`DEBUG_TRACE_WIDTH-1] trace_data_out_q; + wire [0:7] trace_data_out_int_q; + wire [0:DEBUG_LATCH_WIDTH-1] debug_d; // act=>pc_mm_trace_bus_enable_q, sleep=>Y, needs_sreset=>0, scan=>N + wire [0:DEBUG_LATCH_WIDTH-1] debug_q; + wire [0:TRIGGER_LATCH_WIDTH-1] trigger_d; // act=>pc_mm_trace_bus_enable_q, sleep=>Y, needs_sreset=>0, scan=>N + wire [0:TRIGGER_LATCH_WIDTH-1] trigger_q; + wire [0:`DEBUG_TRACE_WIDTH-1] debug_bus_in_q; + wire [0:`DEBUG_TRIGGER_WIDTH-1] trace_triggers_in_q; + wire [0:3] coretrace_ctrls_in_q; + wire [0:3] coretrace_ctrls_out_d, coretrace_ctrls_out_q; + + parameter trace_bus_enable_offset = 0; + parameter debug_mux1_ctrls_offset = trace_bus_enable_offset + 1; + parameter debug_mux1_ctrls_loc_offset = debug_mux1_ctrls_offset + 11; + parameter trigger_data_out_offset = debug_mux1_ctrls_loc_offset + 11; + parameter trace_data_out_offset = trigger_data_out_offset + `DEBUG_TRIGGER_WIDTH; + parameter trace_data_out_int_offset = trace_data_out_offset + `DEBUG_TRACE_WIDTH; + parameter coretrace_ctrls_out_offset = trace_data_out_int_offset + 8; + parameter scan_right = coretrace_ctrls_out_offset + 4 - 1; +//======================================================================================== + // non-scan latches + + wire [0:87] dbg_group0; + wire [0:87] dbg_group1; + wire [0:87] dbg_group2; + wire [0:87] dbg_group3; + wire [0:87] dbg_group4; + wire [0:87] dbg_group5; + wire [0:87] dbg_group6; + wire [0:87] dbg_group7; + wire [0:87] dbg_group8; + wire [0:87] dbg_group9; + + wire [0:87] dbg_group10a; + wire [0:87] dbg_group11a; + wire [0:87] dbg_group12a; + wire [0:87] dbg_group13a; + wire [0:87] dbg_group14a; + wire [0:87] dbg_group15a; + wire [0:87] dbg_group10b; + wire [0:87] dbg_group11b; + wire [0:87] dbg_group12b; + wire [0:87] dbg_group13b; + wire [0:87] dbg_group14b; + wire [0:87] dbg_group15b; + wire [0:87] dbg_group10; + wire [0:87] dbg_group11; + wire [0:87] dbg_group12; + wire [0:87] dbg_group13; + wire [0:87] dbg_group14; + wire [0:87] dbg_group15; + + parameter group12_offset = 68; + parameter group13_offset = 112; + + wire [0:11] trg_group0; + wire [0:11] trg_group1; + wire [0:11] trg_group2; + wire [0:11] trg_group3a; + wire [0:11] trg_group3b; + wire [0:11] trg_group3; + + wire [24:55] dbg_group0a; + + wire tlb_ctl_dbg_tag1_valid; + wire [0:1] tlb_ctl_dbg_tag1_thdid; + wire [0:2] tlb_ctl_dbg_tag1_type; + wire [0:1] tlb_ctl_dbg_tag1_wq; + wire tlb_ctl_dbg_tag1_gs; + wire tlb_ctl_dbg_tag1_pr; + wire tlb_ctl_dbg_tag1_atsel; + wire [0:1] tlb_cmp_dbg_tag4_thdid; // encoded + wire [0:2] tlb_cmp_dbg_tag4_type; // encoded + wire tlb_cmp_dbg_tag4_valid; + wire [0:`TLB_WAYS] tlb_cmp_dbg_tag5_wayhit; + wire [0:1] tlb_cmp_dbg_tag5_thdid; // encoded + wire [0:2] tlb_cmp_dbg_tag5_type; // encoded + wire [0:1] tlb_cmp_dbg_tag5_class; // what kind of derat is it? + wire tlb_cmp_dbg_tag5_iorderat_rel_val; // i or d + wire tlb_cmp_dbg_tag5_iorderat_rel_hit; // i or d + wire [0:167] tlb_cmp_dbg_tag5_way; + wire [0:11] tlb_cmp_dbg_tag5_lru_dataout; + + (* analysis_not_referenced="true" *) + wire [0:11] unused_dc; + + wire [0:DEBUG_LATCH_WIDTH-1] unused_debug_latch_scan; + wire [0:TRIGGER_LATCH_WIDTH-1] unused_trigger_latch_scan; + wire [0:`DEBUG_TRACE_WIDTH-1] unused_busin_latch_scan; + wire [0:`DEBUG_TRIGGER_WIDTH-1] unused_trigin_latch_scan; + wire [0:3] unused_coretrace_ctrls_in_latch_scan; + + // Pervasive + wire pc_func_slp_sl_thold_1; + wire pc_func_slp_sl_thold_0; + wire pc_func_slp_sl_thold_0_b; + wire pc_func_slp_sl_force; + wire pc_func_slp_nsl_thold_1; + wire pc_func_slp_nsl_thold_0; + wire pc_func_slp_nsl_thold_0_b; + wire pc_func_slp_nsl_force; + wire pc_sg_1; + wire pc_sg_0; + wire pc_fce_1; + wire pc_fce_0; + + wire [0:scan_right] siv; + wire [0:scan_right] sov; + + wire tidn; + wire tiup; + + //--------------------------------------------------------------------- + // Logic + //--------------------------------------------------------------------- + + assign tidn = 1'b0; + assign tiup = 1'b1; + + assign pc_mm_debug_mux1_ctrls_loc_d = pc_mm_debug_mux1_ctrls_q; // local timing latches + + //--------------------------------------------------------------------- + // debug input signals from various logic entities + //--------------------------------------------------------------------- + assign debug_d[12] = tlb_ctl_dbg_tag0_valid; + assign debug_d[13:14] = tlb_ctl_dbg_tag0_thdid[0:1]; + assign debug_d[15:17] = tlb_ctl_dbg_tag0_type[0:2]; + assign debug_d[18:19] = tlb_ctl_dbg_tag0_wq[0:1]; + assign debug_d[20] = tlb_ctl_dbg_tag0_gs; + assign debug_d[21] = tlb_ctl_dbg_tag0_pr; + assign debug_d[22] = tlb_ctl_dbg_tag0_atsel; + assign debug_d[23] = 1'b0; + + assign tlb_ctl_dbg_tag1_valid = debug_q[12]; + assign tlb_ctl_dbg_tag1_thdid[0:1] = debug_q[13:14]; + assign tlb_ctl_dbg_tag1_type[0:2] = debug_q[15:17]; + assign tlb_ctl_dbg_tag1_wq[0:1] = debug_q[18:19]; + assign tlb_ctl_dbg_tag1_gs = debug_q[20]; + assign tlb_ctl_dbg_tag1_pr = debug_q[21]; + assign tlb_ctl_dbg_tag1_atsel = debug_q[22]; + + // tlb_low_data + // [0:51] - EPN + // [52:55] - SIZE (4b) + // [56:59] - ThdID + // [60:61] - Class + // [62] - ExtClass + // [63] - TID_NZ + // [64:65] - reserved (2b) + // [66:73] - 8b for LPID + // [74:83] - parity 10bits + assign debug_d[192:275] = tlb_cmp_dbg_tag4_way[0:83]; + assign tlb_cmp_dbg_tag5_way[0:83] = debug_q[192:275]; + + // tlb_high_data + // [84] - [0] - X-bit + // [85:87] - [1:3] - reserved (3b) + // [88:117] - [4:33] - RPN (30b) + // [118:119] - [34:35] - R,C + // [120:121] - [36:37] - WLC (2b) + // [122] - [38] - ResvAttr + // [123] - [39] - VF + // [124] - [40] - IND + // [125:128] - [41:44] - U0-U3 + // [129:133] - [45:49] - WIMGE + // [134:135] - [50:51] - UX,SX + // [136:137] - [52:53] - UW,SW + // [138:139] - [54:55] - UR,SR + // [140] - [56] - GS + // [141] - [57] - TS + // [142:143] - [58:59] - reserved (2b) + // [144:149] - [60:65] - 6b TID msbs + // [150:157] - [66:73] - 8b TID lsbs + // [158:167] - [74:83] - parity 10bits + assign debug_d[276:359] = tlb_cmp_dbg_tag4_way[84:167]; + assign tlb_cmp_dbg_tag5_way[84:167] = debug_q[276:359]; + + // lru data format + // [0:3] - valid(0:3) + // [4:6] - LRU + // [7] - parity + // [8:11] - iprot(0:3) + // [12:14] - reserved + // [15] - parity + assign debug_d[360:371] = tlb_cmp_dbg_tag4_lru_dataout_q[0:11]; + assign tlb_cmp_dbg_tag5_lru_dataout[0:11] = debug_q[360:371]; + + assign trigger_d[0:11] = {12{1'b0}}; + assign trigger_d[12:23] = {12{1'b0}}; + assign trigger_d[24:35] = {12{1'b0}}; + assign trigger_d[36:47] = {12{1'b0}}; + + //group0 (slowspr interface) + assign dbg_group0[0] = spr_dbg_slowspr_val_int; // spr_int phase + assign dbg_group0[1] = spr_dbg_slowspr_rw_int; + assign dbg_group0[2:3] = spr_dbg_slowspr_etid_int; + assign dbg_group0[4:13] = spr_dbg_slowspr_addr_int; + assign dbg_group0[14] = spr_dbg_slowspr_done_out; // spr_out phase + assign dbg_group0[15] = spr_dbg_match_any_mmu; // spr_int phase + assign dbg_group0[16] = spr_dbg_match_any_mas; + assign dbg_group0[17] = spr_dbg_match_pid; + assign dbg_group0[18] = spr_dbg_match_lpidr; + assign dbg_group0[19] = spr_dbg_match_mas2; + assign dbg_group0[20] = spr_dbg_match_mas01_64b; + assign dbg_group0[21] = spr_dbg_match_mas56_64b; + assign dbg_group0[22] = spr_dbg_match_mas73_64b; + assign dbg_group0[23] = spr_dbg_match_mas81_64b; + + // alternate bit muxes when 64b decodes 19:23=00000 + assign dbg_group0a[24] = spr_dbg_match_mmucr0; + assign dbg_group0a[25] = spr_dbg_match_mmucr1; + assign dbg_group0a[26] = spr_dbg_match_mmucr2; + assign dbg_group0a[27] = spr_dbg_match_mmucr3; + assign dbg_group0a[28] = spr_dbg_match_mmucsr0; + assign dbg_group0a[29] = spr_dbg_match_mmucfg; + assign dbg_group0a[30] = spr_dbg_match_tlb0cfg; + assign dbg_group0a[31] = spr_dbg_match_tlb0ps; + assign dbg_group0a[32] = spr_dbg_match_lratcfg; + assign dbg_group0a[33] = spr_dbg_match_lratps; + assign dbg_group0a[34] = spr_dbg_match_eptcfg; + assign dbg_group0a[35] = spr_dbg_match_lper; + assign dbg_group0a[36] = spr_dbg_match_lperu; + assign dbg_group0a[37] = spr_dbg_match_mas0; + assign dbg_group0a[38] = spr_dbg_match_mas1; + assign dbg_group0a[39] = spr_dbg_match_mas2u; + assign dbg_group0a[40] = spr_dbg_match_mas3; + assign dbg_group0a[41] = spr_dbg_match_mas4; + assign dbg_group0a[42] = spr_dbg_match_mas5; + assign dbg_group0a[43] = spr_dbg_match_mas6; + assign dbg_group0a[44] = spr_dbg_match_mas7; + assign dbg_group0a[45] = spr_dbg_match_mas8; + assign dbg_group0a[46] = tlb_mas_tlbre; + assign dbg_group0a[47] = tlb_mas_tlbsx_hit; + assign dbg_group0a[48] = tlb_mas_tlbsx_miss; + assign dbg_group0a[49] = tlb_mas_dtlb_error; + assign dbg_group0a[50] = tlb_mas_itlb_error; + assign dbg_group0a[51] = tlb_mas_thdid[2] | tlb_mas_thdid[3]; // encoded + assign dbg_group0a[52] = tlb_mas_thdid[1] | tlb_mas_thdid[3]; // encoded + assign dbg_group0a[53] = lrat_mas_tlbre; + assign dbg_group0a[54] = lrat_mas_thdid[2] | lrat_mas_thdid[3]; // encoded + assign dbg_group0a[55] = lrat_mas_thdid[1] | lrat_mas_thdid[3]; // encoded + // alternate bit muxes when 64b decodes 19:23/=00000 + assign dbg_group0[24:55] = ({55-24+1{spr_dbg_match_64b}} & spr_dbg_slowspr_data_out[0:31]) | + ({55-24+1{(~(spr_dbg_match_64b))}} & dbg_group0a[24:55]); + assign dbg_group0[56:87] = spr_dbg_slowspr_data_out[32:63]; + + // snoop_attr: + // 0 -> Local + // 1:3 -> IS/Class: 0=all, 1=tid, 2=gs, 3=epn, 4=class0, 5=class1, 6=class2, 7=class3 + // 4:5 -> GS/TS + // 6:13 -> TID(6:13) + // 14:17 -> Size + // 18 -> reserved for tlb, extclass_enable(0) for erats + // 19 -> mmucsr0.tlb0fi for tlb, or TID_NZ for erats + // 20:25 -> TID(0:5) + // 26:33 -> LPID + // 34 -> IND + + //group1 (invalidate, local generation) + assign dbg_group1[0:4] = inval_dbg_seq_q[0:4]; + assign dbg_group1[5] = inval_dbg_ex6_valid; + assign dbg_group1[6:7] = inval_dbg_ex6_thdid[0:1]; // encoded + assign dbg_group1[8:9] = inval_dbg_ex6_ttype[1:2]; // encoded + assign dbg_group1[10] = htw_lsu_req_valid; + assign dbg_group1[11] = mmucsr0_tlb0fi; + assign dbg_group1[12] = tlbwe_back_inv_valid; + assign dbg_group1[13] = inval_dbg_snoop_forme; + assign dbg_group1[14] = inval_dbg_an_ac_back_inv_q[4]; // L bit + assign dbg_group1[15] = inval_dbg_an_ac_back_inv_q[7]; // local bit + assign dbg_group1[16:50] = inval_dbg_snoop_attr_q[0:34]; + assign dbg_group1[51:52] = inval_dbg_snoop_attr_tlb_spec_q[18:19]; + assign dbg_group1[53:87] = inval_dbg_snoop_vpn_q[17:51]; + + //group2 (invalidate, bus snoops) + assign dbg_group2[0:4] = inval_dbg_seq_q[0:4]; + assign dbg_group2[5] = inval_dbg_snoop_forme; + assign dbg_group2[6] = inval_dbg_snoop_local_reject; + assign dbg_group2[7:13] = inval_dbg_an_ac_back_inv_q[2:8]; // 2=valid b, 3=target b, 4=L, 5=GS, 6=IND, 7=local, 8=reject + assign dbg_group2[14:21] = inval_dbg_an_ac_back_inv_lpar_id_q[0:7]; + assign dbg_group2[22:63] = inval_dbg_an_ac_back_inv_addr_q[22:63]; + assign dbg_group2[64:66] = inval_dbg_snoop_valid_q[0:2]; + assign dbg_group2[67:87] = {inval_dbg_snoop_attr_q[0:19], inval_dbg_snoop_attr_q[34]}; + + //group3 (lsu interface) + assign dbg_group3[0:4] = inval_dbg_seq_q[0:4]; + assign dbg_group3[5] = inval_dbg_ex6_valid; + assign dbg_group3[6:7] = inval_dbg_ex6_thdid[0:1]; // encoded + assign dbg_group3[8:9] = inval_dbg_ex6_ttype[1:2]; // encoded + assign dbg_group3[10] = inval_dbg_snoop_forme; + assign dbg_group3[11] = inval_dbg_an_ac_back_inv_q[7]; // 2=valid b, 3=target b, 4=L, 5=GS, 6=IND, 7=local, 8=reject + assign dbg_group3[12] = xu_mm_lmq_stq_empty; + assign dbg_group3[13] = iu_mm_lmq_empty; + assign dbg_group3[14:15] = htw_dbg_seq_q[0:1]; + assign dbg_group3[16] = htw_lsu_req_valid; + assign dbg_group3[17:18] = htw_dbg_lsu_thdid[0:1]; + assign dbg_group3[19:20] = htw_lsu_ttype[0:1]; + assign dbg_group3[21] = xu_mm_lsu_token; + assign dbg_group3[22] = inval_dbg_lsu_tokens_q[1]; + assign dbg_group3[23] = |(mm_xu_lsu_req); + assign dbg_group3[24:25] = mm_xu_lsu_ttype; // 0=tlbivax_op L=0, 1=tlbi_complete, 2=mmu read with core_tag=01100, 3=mmu read with core_tag=01101 + assign dbg_group3[26:30] = mm_xu_lsu_wimge; + assign dbg_group3[31] = mm_xu_lsu_ind; // tlbivax sec enc data + assign dbg_group3[32] = mm_xu_lsu_gs; // tlbivax sec enc data + assign dbg_group3[33] = mm_xu_lsu_lbit; // tlbivax sec enc data, "L" bit, for large vs. small + assign dbg_group3[34:37] = mm_xu_lsu_u; + assign dbg_group3[38:45] = mm_xu_lsu_lpid; // tlbivax lpar id data + assign dbg_group3[46:87] = mm_xu_lsu_addr[22:63]; + + // `tagpos_epn : natural := 0; + // `tagpos_pid : natural := 52; -- 14 bits + // `tagpos_is : natural := 66; + // `tagpos_class : natural := 68; + // `tagpos_state : natural := 70; -- state: 0:pr 1:gs 2:as 3:cm + // `tagpos_thdid : natural := 74; + // `tagpos_size : natural := 78; + // `tagpos_type : natural := 82; -- derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload + // `tagpos_lpid : natural := 90; + // `tagpos_ind : natural := 98; + // `tagpos_atsel : natural := 99; + // `tagpos_esel : natural := 100; + // `tagpos_hes : natural := 103; + // `tagpos_wq : natural := 104; + // `tagpos_lrat : natural := 106; + // `tagpos_pt : natural := 107; + // `tagpos_recform : natural := 108; + // `tagpos_endflag : natural := 109; + + assign tlb_cmp_dbg_tag5_iorderat_rel_val = |(tlb_cmp_dbg_tag5_erat_rel_val[0:3] | tlb_cmp_dbg_tag5_erat_rel_val[5:8]); // i or d + assign tlb_cmp_dbg_tag5_iorderat_rel_hit = tlb_cmp_dbg_tag5_erat_rel_val[4] | tlb_cmp_dbg_tag5_erat_rel_val[9]; // i or d + + //group4 (sequencers, the big picture) + assign dbg_group4[0:5] = tlb_ctl_dbg_seq_q[0:5]; // tlb_seq_q + assign dbg_group4[6:7] = tlb_ctl_dbg_tag0_thdid[0:1]; // encoded + assign dbg_group4[8:10] = tlb_ctl_dbg_tag0_type[0:2]; // encoded + assign dbg_group4[11] = tlb_ctl_dbg_any_tag_flush_sig; + assign dbg_group4[12:15] = tlb_cmp_dbg_tag4_wayhit[0:3]; + //assign dbg_group4(16 to 19) = mm_xu_eratmiss_done[0:3]; + //assign dbg_group4[20 to 23) = mm_iu_barrier_done[0:3]; + //assign dbg_group4[24 to 27) = mm_xu_ex3_flush_req[0:3]; + assign dbg_group4[28] = tlb_cmp_dbg_tag5_iorderat_rel_val; // i or d + assign dbg_group4[29] = tlb_cmp_dbg_tag5_iorderat_rel_hit; // i or d + assign dbg_group4[30:31] = htw_dbg_seq_q[0:1]; + assign dbg_group4[32:34] = htw_dbg_pte0_seq_q[0:2]; + assign dbg_group4[35:37] = htw_dbg_pte1_seq_q[0:2]; + assign dbg_group4[38:42] = inval_dbg_seq_q[0:4]; + assign dbg_group4[43] = mmucsr0_tlb0fi; + assign dbg_group4[44] = inval_dbg_ex6_valid; + assign dbg_group4[45:46] = inval_dbg_ex6_thdid[0:1]; // encoded + assign dbg_group4[47:49] = inval_dbg_ex6_ttype[0:2]; // encoded tlbilx & tlbivax & eratilx & erativax, csync, isync + assign dbg_group4[50] = inval_dbg_snoop_forme; + assign dbg_group4[51:57] = inval_dbg_an_ac_back_inv_q[2:8]; // 2=valid b, 3=target b, 4=L, 5=GS, 6=IND, 7=local, 8=reject + assign dbg_group4[58] = xu_mm_lmq_stq_empty; + assign dbg_group4[59] = iu_mm_lmq_empty; + + generate + begin : xhdl0 + genvar tid; + for (tid = 0; tid <= 3; tid = tid + 1) + begin : Grp4Threads + if (tid < `THREADS) + begin : Grp4Exist + assign dbg_group4[16 + tid] = mm_xu_eratmiss_done[tid]; + assign dbg_group4[20 + tid] = mm_iu_barrier_done[tid]; + assign dbg_group4[24 + tid] = mm_xu_ex3_flush_req[tid]; + assign dbg_group4[60 + tid] = mm_xu_hold_req[tid]; + assign dbg_group4[64 + tid] = xu_mm_hold_ack[tid]; + assign dbg_group4[68 + tid] = mm_xu_hold_done[tid]; + end + if (tid >= `THREADS) + begin : Grp4NExist + assign dbg_group4[16 + tid] = tidn; + assign dbg_group4[20 + tid] = tidn; + assign dbg_group4[24 + tid] = tidn; + assign dbg_group4[60 + tid] = tidn; + assign dbg_group4[64 + tid] = tidn; + assign dbg_group4[68 + tid] = tidn; + end + end + end + endgenerate + + assign dbg_group4[72:74] = inval_dbg_snoop_valid_q[0:2]; + assign dbg_group4[75:77] = inval_dbg_snoop_ack_q[0:2]; + assign dbg_group4[78] = |(mm_xu_lsu_req); + assign dbg_group4[79:80] = mm_xu_lsu_ttype; // 0=tlbivax_op L=0, 1=tlbi_complete, 2=mmu read with core_tag=01100, 3=mmu read with core_tag=01101 + assign dbg_group4[81] = |(mm_xu_illeg_instr); + assign dbg_group4[82:85] = tlb_cmp_dbg_tag5_except_type_q[0:3]; // tag5 except valid/type, (hv_priv | lrat_miss | pt_fault | pt_inelig) + assign dbg_group4[86:87] = tlb_cmp_dbg_tag5_except_thdid_q[0:1]; // tag5 encoded thdid + + //group5 (tlb_req) + assign dbg_group5[0] = tlb_req_dbg_ierat_iu5_valid_q; + assign dbg_group5[1:2] = tlb_req_dbg_ierat_iu5_thdid[0:1]; // encoded + assign dbg_group5[3:6] = tlb_req_dbg_ierat_iu5_state_q[0:3]; + assign dbg_group5[7] = tlb_seq_ierat_req; + assign dbg_group5[8:9] = tlb_req_dbg_ierat_inptr_q[0:1]; + assign dbg_group5[10:11] = tlb_req_dbg_ierat_outptr_q[0:1]; + assign dbg_group5[12:15] = tlb_req_dbg_ierat_req_valid_q[0:3]; + assign dbg_group5[16:19] = tlb_req_dbg_ierat_req_nonspec_q[0:3]; + assign dbg_group5[20:27] = tlb_req_dbg_ierat_req_thdid[0:7]; // encoded + assign dbg_group5[28:31] = tlb_req_dbg_ierat_req_dup_q[0:3]; + assign dbg_group5[32] = tlb_req_dbg_derat_ex6_valid_q; + assign dbg_group5[33:34] = tlb_req_dbg_derat_ex6_thdid[0:1]; // encoded + assign dbg_group5[35:38] = tlb_req_dbg_derat_ex6_state_q[0:3]; + assign dbg_group5[39] = tlb_seq_derat_req; + assign dbg_group5[40:41] = tlb_req_dbg_derat_inptr_q[0:1]; + assign dbg_group5[42:43] = tlb_req_dbg_derat_outptr_q[0:1]; + assign dbg_group5[44:47] = tlb_req_dbg_derat_req_valid_q[0:3]; + assign dbg_group5[48:55] = tlb_req_dbg_derat_req_thdid[0:7]; // encoded + assign dbg_group5[56:63] = tlb_req_dbg_derat_req_ttype_q[0:7]; + assign dbg_group5[64:67] = tlb_req_dbg_derat_req_dup_q[0:3]; + assign dbg_group5[68:87] = tlb_cmp_dbg_erat_dup_q[0:19]; + + // unused tag bits for certain ops are re-purposed as below: + // unused `tagpos_is def is mas1_v, mas1_iprot for tlbwe, and is pte.valid & 0 for ptereloads + // unused `tagpos_pt, `tagpos_recform def are mas8_tgs, mas1_ts for tlbwe + // unused `tagpos_atsel | `tagpos_esel used as indirect entry's thdid to update tlb_entry.thdid for ptereloads + // unused `tagpos_wq used as htw reserv write enab & dup bits (set in htw) for ptereloads + // unused esel for derat,ierat,tlbsx,tlbsrx becomes tlb_seq page size attempted number (1 thru 5) + // unused "is" for derat,ierat,tlbsx,tlbsrx becomes tlb_seq page size attempted number msb (9 thru 13, or 17 thru 21) + // unused HES bit for snoops is used as mmucsr0.tlb0fi full invalidate of all non-protected entries + + // some encoding of debug sigs + // ttype: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload + assign tlb_cmp_dbg_tag4_valid = |(tlb_cmp_dbg_tag4[`tagpos_thdid:`tagpos_thdid + 3]); + + assign tlb_cmp_dbg_tag4_thdid[0] = (tlb_cmp_dbg_tag4[`tagpos_thdid + 2] | tlb_cmp_dbg_tag4[`tagpos_thdid + 3]); // encoded + assign tlb_cmp_dbg_tag4_thdid[1] = (tlb_cmp_dbg_tag4[`tagpos_thdid + 1] | tlb_cmp_dbg_tag4[`tagpos_thdid + 3]); // encoded + + assign tlb_cmp_dbg_tag4_type[0] = (tlb_cmp_dbg_tag4[`tagpos_type_snoop] | tlb_cmp_dbg_tag4[`tagpos_type_tlbre] | tlb_cmp_dbg_tag4[`tagpos_type_tlbwe] | tlb_cmp_dbg_tag4[`tagpos_type_ptereload]); // encoded + assign tlb_cmp_dbg_tag4_type[1] = (tlb_cmp_dbg_tag4[`tagpos_type_tlbsx] | tlb_cmp_dbg_tag4[`tagpos_type_tlbsrx] | tlb_cmp_dbg_tag4[`tagpos_type_tlbwe] | tlb_cmp_dbg_tag4[`tagpos_type_ptereload]); // encoded + assign tlb_cmp_dbg_tag4_type[2] = (tlb_cmp_dbg_tag4[`tagpos_type_ierat] | tlb_cmp_dbg_tag4[`tagpos_type_tlbsrx] | tlb_cmp_dbg_tag4[`tagpos_type_tlbre] | tlb_cmp_dbg_tag4[`tagpos_type_ptereload]); // encoded + + //group6 (general erat and search compare values, truncated epn) + assign dbg_group6[0] = tlb_cmp_dbg_tag4_valid; // or_reduce of thdid; + assign dbg_group6[1:2] = tlb_cmp_dbg_tag4_thdid[0:1]; // encoded + assign dbg_group6[3:5] = tlb_cmp_dbg_tag4_type[0:2]; // encoded + assign dbg_group6[6:7] = tlb_cmp_dbg_tag4[`tagpos_class:`tagpos_class + 1]; + assign dbg_group6[8:9] = tlb_cmp_dbg_tag4[`tagpos_is:`tagpos_is + 1]; + assign dbg_group6[10:12] = tlb_cmp_dbg_tag4[`tagpos_esel:`tagpos_esel + 2]; + assign dbg_group6[13] = tlb_cmp_dbg_tag4[`tagpos_cm]; + assign dbg_group6[14] = tlb_cmp_dbg_tag4[`tagpos_pr]; + assign dbg_group6[15] = tlb_cmp_dbg_tag4[`tagpos_ind]; + assign dbg_group6[16] = tlb_cmp_dbg_tag4[`tagpos_endflag]; + assign dbg_group6[17:23] = tlb_cmp_dbg_addr4[0:6]; + assign dbg_group6[24:27] = tlb_cmp_dbg_tag4_wayhit[0:`TLB_WAYS - 1]; + assign dbg_group6[28] = tlb_cmp_dbg_tag4[`tagpos_gs]; + assign dbg_group6[29:36] = tlb_cmp_dbg_tag4[`tagpos_lpid:`tagpos_lpid + 7]; + assign dbg_group6[37] = tlb_cmp_dbg_tag4[`tagpos_as]; + assign dbg_group6[38:51] = tlb_cmp_dbg_tag4[`tagpos_pid:`tagpos_pid + 13]; + assign dbg_group6[52:87] = tlb_cmp_dbg_tag4[`tagpos_epn + 16:`tagpos_epn + 51]; + + // match <= addr_match and -- Address compare + // pgsize_match and -- Size compare + // class_match and -- Class compare + // extclass_match and -- ExtClass compare + // state_match and -- State compare + // thdid_match and -- ThdID compare + // pid_match and -- PID compare + // lpid_match and -- LPID compare + // ind_match and -- indirect compare + // iprot_match and -- inval prot compare + // entry_v; -- Valid + + //group7 (detailed compare/match) + assign dbg_group7[0] = tlb_cmp_dbg_tag4_valid; + assign dbg_group7[1:2] = tlb_cmp_dbg_tag4_thdid[0:1]; + assign dbg_group7[3:5] = tlb_cmp_dbg_tag4_type[0:2]; + assign dbg_group7[6:7] = tlb_cmp_dbg_tag4[`tagpos_is:`tagpos_is + 1]; + assign dbg_group7[8:9] = tlb_cmp_dbg_tag4[`tagpos_class:`tagpos_class + 1]; + assign dbg_group7[10:12] = tlb_cmp_dbg_tag4[`tagpos_esel:`tagpos_esel + 2]; + assign dbg_group7[13:19] = tlb_cmp_dbg_addr4[0:6]; + assign dbg_group7[20:23] = tlb_cmp_dbg_tag4_wayhit[0:3]; + + assign debug_d[24:32] = tlb_cmp_dbg_addr_enable[0:8]; // these are tag3 versions coming in + assign debug_d[33] = tlb_cmp_dbg_pgsize_enable; + assign debug_d[34] = tlb_cmp_dbg_class_enable; + assign debug_d[35:36] = tlb_cmp_dbg_extclass_enable[0:1]; + assign debug_d[37:38] = tlb_cmp_dbg_state_enable[0:1]; + assign debug_d[39] = tlb_cmp_dbg_thdid_enable; + assign debug_d[40] = tlb_cmp_dbg_pid_enable; + assign debug_d[41] = tlb_cmp_dbg_lpid_enable; + assign debug_d[42] = tlb_cmp_dbg_ind_enable; + assign debug_d[43] = tlb_cmp_dbg_iprot_enable; + assign debug_d[44] = tlb_cmp_dbg_way0_entry_v; + assign debug_d[45] = tlb_cmp_dbg_way0_addr_match; + assign debug_d[46] = tlb_cmp_dbg_way0_pgsize_match; + assign debug_d[47] = tlb_cmp_dbg_way0_class_match; + assign debug_d[48] = tlb_cmp_dbg_way0_extclass_match; + assign debug_d[49] = tlb_cmp_dbg_way0_state_match; + assign debug_d[50] = tlb_cmp_dbg_way0_thdid_match; + assign debug_d[51] = tlb_cmp_dbg_way0_pid_match; + assign debug_d[52] = tlb_cmp_dbg_way0_lpid_match; + assign debug_d[53] = tlb_cmp_dbg_way0_ind_match; + assign debug_d[54] = tlb_cmp_dbg_way0_iprot_match; + assign debug_d[55] = tlb_cmp_dbg_way1_entry_v; + assign debug_d[56] = tlb_cmp_dbg_way1_addr_match; + assign debug_d[57] = tlb_cmp_dbg_way1_pgsize_match; + assign debug_d[58] = tlb_cmp_dbg_way1_class_match; + assign debug_d[59] = tlb_cmp_dbg_way1_extclass_match; + assign debug_d[60] = tlb_cmp_dbg_way1_state_match; + assign debug_d[61] = tlb_cmp_dbg_way1_thdid_match; + assign debug_d[62] = tlb_cmp_dbg_way1_pid_match; + assign debug_d[63] = tlb_cmp_dbg_way1_lpid_match; + assign debug_d[64] = tlb_cmp_dbg_way1_ind_match; + assign debug_d[65] = tlb_cmp_dbg_way1_iprot_match; + assign debug_d[66] = tlb_cmp_dbg_way2_entry_v; + assign debug_d[67] = tlb_cmp_dbg_way2_addr_match; + assign debug_d[68] = tlb_cmp_dbg_way2_pgsize_match; + assign debug_d[69] = tlb_cmp_dbg_way2_class_match; + assign debug_d[70] = tlb_cmp_dbg_way2_extclass_match; + assign debug_d[71] = tlb_cmp_dbg_way2_state_match; + assign debug_d[72] = tlb_cmp_dbg_way2_thdid_match; + assign debug_d[73] = tlb_cmp_dbg_way2_pid_match; + assign debug_d[74] = tlb_cmp_dbg_way2_lpid_match; + assign debug_d[75] = tlb_cmp_dbg_way2_ind_match; + assign debug_d[76] = tlb_cmp_dbg_way2_iprot_match; + assign debug_d[77] = tlb_cmp_dbg_way3_entry_v; + assign debug_d[78] = tlb_cmp_dbg_way3_addr_match; + assign debug_d[79] = tlb_cmp_dbg_way3_pgsize_match; + assign debug_d[80] = tlb_cmp_dbg_way3_class_match; + assign debug_d[81] = tlb_cmp_dbg_way3_extclass_match; + assign debug_d[82] = tlb_cmp_dbg_way3_state_match; + assign debug_d[83] = tlb_cmp_dbg_way3_thdid_match; + assign debug_d[84] = tlb_cmp_dbg_way3_pid_match; + assign debug_d[85] = tlb_cmp_dbg_way3_lpid_match; + assign debug_d[86] = tlb_cmp_dbg_way3_ind_match; + assign debug_d[87] = tlb_cmp_dbg_way3_iprot_match; + + assign dbg_group7[24:87] = debug_q[24:87]; // tag4 phase, see below + + // unused tag bits for certain ops are re-purposed as below: + // unused `tagpos_is def is mas1_v, mas1_iprot for tlbwe, and is pte.valid & 0 for ptereloads + // unused `tagpos_pt, `tagpos_recform def are mas8_tgs, mas1_ts for tlbwe + // unused `tagpos_atsel | `tagpos_esel used as indirect entry's thdid to update tlb_entry.thdid for ptereloads + // unused `tagpos_wq used as htw reserv write enab & dup bits (set in htw) for ptereloads + // unused esel for derat,ierat,tlbsx,tlbsrx becomes tlb_seq page size attempted number (1 thru 5) + // unused "is" for derat,ierat,tlbsx,tlbsrx becomes tlb_seq page size attempted number msb (9 thru 13, or 17 thru 21) + // unused HES bit for snoops is used as mmucsr0.tlb0fi full invalidate of all non-protected entries + // unused class is derat ttype for derat miss, 0=load,1=store,2=epid load,3=epid store + + //group8 (erat miss, tlbre, tlbsx mas updates and parerr) + assign dbg_group8[0] = tlb_cmp_dbg_tag4_valid; + assign dbg_group8[1:2] = tlb_cmp_dbg_tag4_thdid[0:1]; + assign dbg_group8[3:5] = tlb_cmp_dbg_tag4_type[0:2]; + assign dbg_group8[6:7] = tlb_cmp_dbg_tag4[`tagpos_class:`tagpos_class + 1]; + assign dbg_group8[8] = tlb_cmp_dbg_tag4[`tagpos_cm]; + assign dbg_group8[9] = tlb_cmp_dbg_tag4[`tagpos_gs]; + assign dbg_group8[10] = tlb_cmp_dbg_tag4[`tagpos_pr]; + assign dbg_group8[11] = tlb_cmp_dbg_tag4[`tagpos_endflag]; + assign dbg_group8[12] = tlb_cmp_dbg_tag4[`tagpos_atsel]; + assign dbg_group8[13:15] = tlb_cmp_dbg_tag4[`tagpos_esel:`tagpos_esel + 2]; + assign dbg_group8[16:19] = tlb_cmp_dbg_tag4[`tagpos_size:`tagpos_size + 3]; + assign dbg_group8[20:33] = tlb_cmp_dbg_tag4[`tagpos_pid:`tagpos_pid + 13]; + assign dbg_group8[34:58] = tlb_cmp_dbg_tag4[`tagpos_epn + 27:`tagpos_epn + 51]; + assign dbg_group8[59:65] = tlb_cmp_dbg_addr4[0:6]; + assign dbg_group8[66:69] = tlb_cmp_dbg_tag4_wayhit[0:`TLB_WAYS - 1]; + assign dbg_group8[70] = tlb_mas_dtlb_error; + assign dbg_group8[71] = tlb_mas_itlb_error; + assign dbg_group8[72] = tlb_mas_tlbsx_hit; + assign dbg_group8[73] = tlb_mas_tlbsx_miss; + assign dbg_group8[74] = tlb_mas_tlbre; + assign dbg_group8[75] = lrat_mas_tlbre; + assign dbg_group8[76] = lrat_mas_tlbsx_hit; + assign dbg_group8[77] = lrat_mas_tlbsx_miss; + assign dbg_group8[78:80] = lrat_tag4_hit_entry[0:2]; + assign dbg_group8[81:85] = tlb_cmp_dbg_tag4_parerr[0:4]; // way0 to 3, lru + assign dbg_group8[86] = |(mm_xu_cr0_eq_valid); + assign dbg_group8[87] = |(mm_xu_cr0_eq & mm_xu_cr0_eq_valid); + + //group9 (tlbwe, ptereload write control) + assign dbg_group9[0] = tlb_cmp_dbg_tag4_valid; + assign dbg_group9[1:2] = tlb_cmp_dbg_tag4_thdid[0:1]; + assign dbg_group9[3:5] = tlb_cmp_dbg_tag4_type[0:2]; + assign dbg_group9[6] = tlb_cmp_dbg_tag4[`tagpos_gs]; + assign dbg_group9[7] = tlb_cmp_dbg_tag4[`tagpos_pr]; + assign dbg_group9[8] = tlb_cmp_dbg_tag4[`tagpos_cm]; + assign dbg_group9[9] = tlb_cmp_dbg_tag4[`tagpos_hes]; + assign dbg_group9[10:11] = tlb_cmp_dbg_tag4[`tagpos_wq:`tagpos_wq + 1]; + assign dbg_group9[12] = tlb_cmp_dbg_tag4[`tagpos_atsel]; + assign dbg_group9[13:15] = tlb_cmp_dbg_tag4[`tagpos_esel:`tagpos_esel + 2]; + assign dbg_group9[16:17] = tlb_cmp_dbg_tag4[`tagpos_is:`tagpos_is + 1]; + assign dbg_group9[18] = tlb_cmp_dbg_tag4[`tagpos_pt]; + assign dbg_group9[19] = tlb_cmp_dbg_tag4[`tagpos_recform]; + assign dbg_group9[20] = tlb_cmp_dbg_tag4[`tagpos_ind]; + assign dbg_group9[21:27] = tlb_cmp_dbg_addr4[0:6]; + assign dbg_group9[28:31] = tlb_cmp_dbg_tag4_wayhit[0:`TLB_WAYS - 1]; + assign dbg_group9[32:43] = tlb_cmp_dbg_tag4_lru_dataout_q[0:11]; // current valid. lru, iprot + assign dbg_group9[44:47] = lrat_tag4_hit_status[0:3]; + assign dbg_group9[48:50] = lrat_tag4_hit_entry[0:2]; + assign dbg_group9[51] = |(mm_iu_barrier_done); + assign dbg_group9[52:55] = tlb_ctl_dbg_resv_valid[0:3]; + assign dbg_group9[56:59] = tlb_ctl_dbg_resv_match_vec_q[0:3]; // tag4 + assign dbg_group9[60:63] = tlb_ctl_dbg_tag5_tlb_write_q[0:3]; // tag5 + assign dbg_group9[64:75] = tlb_cmp_dbg_tag5_lru_datain_q[0:11]; // tag5 + assign dbg_group9[76] = tlb_cmp_dbg_tag5_lru_write; // all bits the same + assign dbg_group9[77] = |(mm_xu_illeg_instr); + assign dbg_group9[78:81] = tlb_cmp_dbg_tag5_except_type_q[0:3]; // tag5 except valid/type, (hv_priv | lrat_miss | pt_fault | pt_inelig) + assign dbg_group9[82:83] = tlb_cmp_dbg_tag5_except_thdid_q[0:1]; // tag5 encoded thdid + assign dbg_group9[84] = tlbwe_back_inv_valid; // valid + assign dbg_group9[85] = tlbwe_back_inv_attr[18]; // not extclass enable + assign dbg_group9[86] = tlbwe_back_inv_attr[19]; // tid_nz + assign dbg_group9[87] = 1'b0; + + // constant `eratpos_epn : natural := 0; + // constant `eratpos_x : natural := 52; + // constant `eratpos_size : natural := 53; + // constant `eratpos_v : natural := 56; + // constant `eratpos_thdid : natural := 57; + // constant `eratpos_class : natural := 61; + // constant `eratpos_extclass : natural := 63; + // constant `eratpos_wren : natural := 65; + // constant `eratpos_rpnrsvd : natural := 66; + // constant `eratpos_rpn : natural := 70; + // constant `eratpos_r : natural := 100; + // constant `eratpos_c : natural := 101; + // constant `eratpos_rsv : natural := 102; + // constant `eratpos_wlc : natural := 103; + // constant `eratpos_resvattr : natural := 105; + // constant `eratpos_vf : natural := 106; + // constant `eratpos_ubits : natural := 107; + // constant `eratpos_wimge : natural := 111; + // constant `eratpos_usxwr : natural := 116; + // constant `eratpos_gs : natural := 122; + // constant `eratpos_ts : natural := 123; + // constant `eratpos_tid : natural := 124; -- 8 bits + + assign debug_d[0:1] = tlb_cmp_dbg_tag4_thdid; // tag5 thdid encoded + assign debug_d[2:4] = tlb_cmp_dbg_tag4_type; // tag5 type encoded + assign debug_d[5:6] = tlb_cmp_dbg_tag4[`tagpos_class:`tagpos_class + 1]; // what kind of derat is it? + assign debug_d[7:11] = tlb_cmp_dbg_tag4_wayhit[0:`TLB_WAYS]; + + assign tlb_cmp_dbg_tag5_thdid[0:1] = debug_q[0:1]; + assign tlb_cmp_dbg_tag5_type[0:2] = debug_q[2:4]; + assign tlb_cmp_dbg_tag5_class[0:1] = debug_q[5:6]; + assign tlb_cmp_dbg_tag5_wayhit[0:4] = debug_q[7:11]; + + //group10 (erat reload bus, epn) --------> can mux tlb_datain(0:83) epn for tlbwe/ptereload ops + assign dbg_group10a[0] = tlb_cmp_dbg_tag5_iorderat_rel_val; + assign dbg_group10a[1:2] = tlb_cmp_dbg_tag5_thdid[0:1]; + assign dbg_group10a[3:5] = tlb_cmp_dbg_tag5_type[0:2]; + assign dbg_group10a[6:7] = tlb_cmp_dbg_tag5_class[0:1]; // what kind of derat is it? + assign dbg_group10a[8:11] = tlb_cmp_dbg_tag5_wayhit[0:`TLB_WAYS - 1]; + assign dbg_group10a[12:21] = tlb_cmp_dbg_tag5_erat_rel_val[0:9]; + assign dbg_group10a[22:87] = tlb_cmp_dbg_tag5_erat_rel_data[`eratpos_epn:`eratpos_wren]; + + // tlb_low_data + // [0:51] - EPN + // [52:55] - SIZE (4b) + // [56:59] - ThdID + // [60:61] - Class + // [62] - ExtClass + // [63] - TID_NZ + // [64:65] - reserved (2b) + // [66:73] - 8b for LPID + // [74:83] - parity 10bits + assign dbg_group10b[0:83] = tlb_cmp_dbg_tag5_tlb_datain_q[0:83]; // tlb_datain epn + assign dbg_group10b[84] = (tlb_cmp_dbg_tag5_type[0:2] == 3'b110) & |(tlb_ctl_dbg_tag5_tlb_write_q); // tlbwe + assign dbg_group10b[85] = (tlb_cmp_dbg_tag5_type[0:2] == 3'b111) & |(tlb_ctl_dbg_tag5_tlb_write_q); // ptereload + assign dbg_group10b[86] = (tlb_ctl_dbg_tag5_tlb_write_q[2] | tlb_ctl_dbg_tag5_tlb_write_q[3]); + assign dbg_group10b[87] = (tlb_ctl_dbg_tag5_tlb_write_q[1] | tlb_ctl_dbg_tag5_tlb_write_q[3]); + + assign dbg_group10 = (mmucr2[8] == 1'b1) ? dbg_group10b : + dbg_group10a; + + //group11 (erat reload bus, rpn) --------> can mux tlb_datain(84:167) rpn for tlbwe/ptereload ops + assign dbg_group11a[0] = tlb_cmp_dbg_tag5_iorderat_rel_val; + assign dbg_group11a[1:2] = tlb_cmp_dbg_tag5_thdid[0:1]; + assign dbg_group11a[3:5] = tlb_cmp_dbg_tag5_type[0:2]; + assign dbg_group11a[6:7] = tlb_cmp_dbg_tag5_class[0:1]; // what kind of derat is it? + assign dbg_group11a[8:11] = tlb_cmp_dbg_tag5_wayhit[0:`TLB_WAYS - 1]; + assign dbg_group11a[12:21] = tlb_cmp_dbg_tag5_erat_rel_val[0:9]; + assign dbg_group11a[22:87] = tlb_cmp_dbg_tag5_erat_rel_data[`eratpos_rpnrsvd:`eratpos_tid + 7]; + + // tlb_high_data + // [84] - [0] - X-bit + // [85:87] - [1:3] - reserved (3b) + // [88:117] - [4:33] - RPN (30b) + // [118:119] - [34:35] - R,C + // [120:121] - [36:37] - WLC (2b) + // [122] - [38] - ResvAttr + // [123] - [39] - VF + // [124] - [40] - IND + // [125:128] - [41:44] - U0-U3 + // [129:133] - [45:49] - WIMGE + // [134:135] - [50:51] - UX,SX + // [136:137] - [52:53] - UW,SW + // [138:139] - [54:55] - UR,SR + // [140] - [56] - GS + // [141] - [57] - TS + // [142:143] - [58:59] - reserved (2b) + // [144:149] - [60:65] - 6b TID msbs + // [150:157] - [66:73] - 8b TID lsbs + // [158:167] - [74:83] - parity 10bits + assign dbg_group11b[0:83] = tlb_cmp_dbg_tag5_tlb_datain_q[84:167]; // tlb_datain rpn + assign dbg_group11b[84] = (tlb_cmp_dbg_tag5_type[0:2] == 3'b110) & |(tlb_ctl_dbg_tag5_tlb_write_q); // tlbwe + assign dbg_group11b[85] = (tlb_cmp_dbg_tag5_type[0:2] == 3'b111) & |(tlb_ctl_dbg_tag5_tlb_write_q); // ptereload + assign dbg_group11b[86] = (tlb_ctl_dbg_tag5_tlb_write_q[2] | tlb_ctl_dbg_tag5_tlb_write_q[3]); + assign dbg_group11b[87] = (tlb_ctl_dbg_tag5_tlb_write_q[1] | tlb_ctl_dbg_tag5_tlb_write_q[3]); + + assign dbg_group11 = (mmucr2[8] == 1'b1) ? dbg_group11b : + dbg_group11a; + + //group12 (reservations) + assign dbg_group12a[0] = tlb_ctl_dbg_tag1_valid; + assign dbg_group12a[1:2] = tlb_ctl_dbg_tag1_thdid[0:1]; + assign dbg_group12a[3:5] = tlb_ctl_dbg_tag1_type[0:2]; + assign dbg_group12a[6:7] = tlb_ctl_dbg_tag1_wq[0:1]; + + assign dbg_group12a[8:11] = tlb_ctl_dbg_resv_valid[0:3]; + assign dbg_group12a[12:15] = tlb_ctl_dbg_set_resv[0:3]; + assign dbg_group12a[16:19] = tlb_ctl_dbg_resv_match_vec_q[0:3]; // tag4 + + assign debug_d[group12_offset + 20] = tlb_ctl_dbg_resv0_tag0_lpid_match; + assign debug_d[group12_offset + 21] = tlb_ctl_dbg_resv0_tag0_pid_match; + assign debug_d[group12_offset + 22] = tlb_ctl_dbg_resv0_tag0_as_snoop_match; + assign debug_d[group12_offset + 23] = tlb_ctl_dbg_resv0_tag0_gs_snoop_match; + assign debug_d[group12_offset + 24] = tlb_ctl_dbg_resv0_tag0_as_tlbwe_match; + assign debug_d[group12_offset + 25] = tlb_ctl_dbg_resv0_tag0_gs_tlbwe_match; + assign debug_d[group12_offset + 26] = tlb_ctl_dbg_resv0_tag0_ind_match; + assign debug_d[group12_offset + 27] = tlb_ctl_dbg_resv0_tag0_epn_loc_match; + assign debug_d[group12_offset + 28] = tlb_ctl_dbg_resv0_tag0_epn_glob_match; + assign debug_d[group12_offset + 29] = tlb_ctl_dbg_resv0_tag0_class_match; + assign debug_d[group12_offset + 30] = tlb_ctl_dbg_resv1_tag0_lpid_match; + assign debug_d[group12_offset + 31] = tlb_ctl_dbg_resv1_tag0_pid_match; + assign debug_d[group12_offset + 32] = tlb_ctl_dbg_resv1_tag0_as_snoop_match; + assign debug_d[group12_offset + 33] = tlb_ctl_dbg_resv1_tag0_gs_snoop_match; + assign debug_d[group12_offset + 34] = tlb_ctl_dbg_resv1_tag0_as_tlbwe_match; + assign debug_d[group12_offset + 35] = tlb_ctl_dbg_resv1_tag0_gs_tlbwe_match; + assign debug_d[group12_offset + 36] = tlb_ctl_dbg_resv1_tag0_ind_match; + assign debug_d[group12_offset + 37] = tlb_ctl_dbg_resv1_tag0_epn_loc_match; + assign debug_d[group12_offset + 38] = tlb_ctl_dbg_resv1_tag0_epn_glob_match; + assign debug_d[group12_offset + 39] = tlb_ctl_dbg_resv1_tag0_class_match; + assign debug_d[group12_offset + 40] = tlb_ctl_dbg_resv2_tag0_lpid_match; + assign debug_d[group12_offset + 41] = tlb_ctl_dbg_resv2_tag0_pid_match; + assign debug_d[group12_offset + 42] = tlb_ctl_dbg_resv2_tag0_as_snoop_match; + assign debug_d[group12_offset + 43] = tlb_ctl_dbg_resv2_tag0_gs_snoop_match; + assign debug_d[group12_offset + 44] = tlb_ctl_dbg_resv2_tag0_as_tlbwe_match; + assign debug_d[group12_offset + 45] = tlb_ctl_dbg_resv2_tag0_gs_tlbwe_match; + assign debug_d[group12_offset + 46] = tlb_ctl_dbg_resv2_tag0_ind_match; + assign debug_d[group12_offset + 47] = tlb_ctl_dbg_resv2_tag0_epn_loc_match; + assign debug_d[group12_offset + 48] = tlb_ctl_dbg_resv2_tag0_epn_glob_match; + assign debug_d[group12_offset + 49] = tlb_ctl_dbg_resv2_tag0_class_match; + assign debug_d[group12_offset + 50] = tlb_ctl_dbg_resv3_tag0_lpid_match; + assign debug_d[group12_offset + 51] = tlb_ctl_dbg_resv3_tag0_pid_match; + assign debug_d[group12_offset + 52] = tlb_ctl_dbg_resv3_tag0_as_snoop_match; + assign debug_d[group12_offset + 53] = tlb_ctl_dbg_resv3_tag0_gs_snoop_match; + assign debug_d[group12_offset + 54] = tlb_ctl_dbg_resv3_tag0_as_tlbwe_match; + assign debug_d[group12_offset + 55] = tlb_ctl_dbg_resv3_tag0_gs_tlbwe_match; + assign debug_d[group12_offset + 56] = tlb_ctl_dbg_resv3_tag0_ind_match; + assign debug_d[group12_offset + 57] = tlb_ctl_dbg_resv3_tag0_epn_loc_match; + assign debug_d[group12_offset + 58] = tlb_ctl_dbg_resv3_tag0_epn_glob_match; + assign debug_d[group12_offset + 59] = tlb_ctl_dbg_resv3_tag0_class_match; + + assign dbg_group12a[20:59] = debug_q[group12_offset + 20:group12_offset + 59]; // tag1 + + assign dbg_group12a[60:63] = tlb_ctl_dbg_clr_resv_q[0:3]; // tag5 + assign dbg_group12a[64:67] = tlb_ctl_dbg_clr_resv_terms[0:3]; // tag5, threadwise condensed into to tlbivax, tlbilx, tlbwe, ptereload + + assign dbg_group12a[68:71] = htw_dbg_req_valid_q[0:3]; + assign dbg_group12a[72:75] = htw_dbg_resv_valid_vec[0:3]; + assign dbg_group12a[76:79] = htw_dbg_tag4_clr_resv_q[0:3]; + assign dbg_group12a[80:83] = htw_dbg_tag4_clr_resv_terms[0:3]; // tag4, threadwise condensed into to tlbivax, tlbilx, tlbwe, ptereload + assign dbg_group12a[84:87] = 4'b0000; + + // tlb_low_data + // [0:51] - EPN + // [52:55] - SIZE (4b) + // [56:59] - ThdID + // [60:61] - Class + // [62] - ExtClass + // [63] - TID_NZ + // [64:65] - reserved (2b) + // [66:73] - 8b for LPID + // [74:83] - parity 10bits + assign dbg_group12b[0:83] = tlb_cmp_dbg_tag5_way[0:83]; // tag5 way epn + assign dbg_group12b[84] = (tlb_cmp_dbg_tag5_lru_dataout[0] & tlb_cmp_dbg_tag5_wayhit[0]) | (tlb_cmp_dbg_tag5_lru_dataout[1] & tlb_cmp_dbg_tag5_wayhit[1]) | (tlb_cmp_dbg_tag5_lru_dataout[2] & tlb_cmp_dbg_tag5_wayhit[2]) | (tlb_cmp_dbg_tag5_lru_dataout[3] & tlb_cmp_dbg_tag5_wayhit[3]); // valid + assign dbg_group12b[85] = (tlb_cmp_dbg_tag5_lru_dataout[8] & tlb_cmp_dbg_tag5_wayhit[0]) | (tlb_cmp_dbg_tag5_lru_dataout[9] & tlb_cmp_dbg_tag5_wayhit[1]) | (tlb_cmp_dbg_tag5_lru_dataout[10] & tlb_cmp_dbg_tag5_wayhit[2]) | (tlb_cmp_dbg_tag5_lru_dataout[11] & tlb_cmp_dbg_tag5_wayhit[3]); // iprot + assign dbg_group12b[86] = tlb_cmp_dbg_tag5_lru_dataout[4]; // encoded lru way msb + assign dbg_group12b[87] = ((~(tlb_cmp_dbg_tag5_lru_dataout[4])) & tlb_cmp_dbg_tag5_lru_dataout[5]) | (tlb_cmp_dbg_tag5_lru_dataout[4] & tlb_cmp_dbg_tag5_lru_dataout[6]); // encoded lru way lsb + + assign dbg_group12 = (mmucr2[9] == 1'b1) ? dbg_group12b : + dbg_group12a; + + // unused tag bits for certain ops are re-purposed as below: + // unused `tagpos_is def is mas1_v, mas1_iprot for tlbwe, and is pte.valid & 0 for ptereloads + // unused `tagpos_pt, `tagpos_recform def are mas8_tgs, mas1_ts for tlbwe + // unused `tagpos_atsel | `tagpos_esel used as indirect entry's thdid to update tlb_entry.thdid for ptereloads + // unused `tagpos_wq used as htw reserv write enab & dup bits (set in htw) for ptereloads + // unused esel for derat,ierat,tlbsx,tlbsrx becomes tlb_seq page size attempted number (1 thru 5) + // unused "is" for derat,ierat,tlbsx,tlbsrx becomes tlb_seq page size attempted number msb (9 thru 13, or 17 thru 21) + // unused HES bit for snoops is used as mmucsr0.tlb0fi full invalidate of all non-protected entries + // unused class is derat ttype for derat miss, 0=load,1=store,2=epid load,3=epid store + + // type: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload + + //group13 (lrat match logic) + assign dbg_group13a[0] = lrat_dbg_tag1_addr_enable; // tlb_addr_cap_q(1) + assign dbg_group13a[1] = tlb_ctl_dbg_tag1_valid; + assign dbg_group13a[2:3] = tlb_ctl_dbg_tag1_thdid[0:1]; + assign dbg_group13a[4:5] = {(tlb_ctl_dbg_tag1_type[0] & tlb_ctl_dbg_tag1_type[1]), (tlb_ctl_dbg_tag1_type[0] & tlb_ctl_dbg_tag1_type[2])}; // tlbsx,tlbre,tlbwe,ptereload + assign dbg_group13a[6] = tlb_ctl_dbg_tag1_gs; + assign dbg_group13a[7] = tlb_ctl_dbg_tag1_pr; + assign dbg_group13a[8] = tlb_ctl_dbg_tag1_atsel; + assign dbg_group13a[9:11] = lrat_tag3_hit_entry[0:2]; + assign dbg_group13a[12:15] = lrat_tag3_hit_status[0:3]; // hit_status to val,hit,multihit,inval_pgsize + + assign debug_d[group13_offset + 16] = lrat_dbg_entry0_addr_match; // tag1 + assign debug_d[group13_offset + 17] = lrat_dbg_entry0_lpid_match; + assign debug_d[group13_offset + 18] = lrat_dbg_entry0_entry_v; + assign debug_d[group13_offset + 19] = lrat_dbg_entry0_entry_x; + assign debug_d[group13_offset + 20:group13_offset + 23] = lrat_dbg_entry0_size[0:3]; + assign debug_d[group13_offset + 24] = lrat_dbg_entry1_addr_match; // tag1 + assign debug_d[group13_offset + 25] = lrat_dbg_entry1_lpid_match; + assign debug_d[group13_offset + 26] = lrat_dbg_entry1_entry_v; + assign debug_d[group13_offset + 27] = lrat_dbg_entry1_entry_x; + assign debug_d[group13_offset + 28:group13_offset + 31] = lrat_dbg_entry1_size[0:3]; + assign debug_d[group13_offset + 32] = lrat_dbg_entry2_addr_match; // tag1 + assign debug_d[group13_offset + 33] = lrat_dbg_entry2_lpid_match; + assign debug_d[group13_offset + 34] = lrat_dbg_entry2_entry_v; + assign debug_d[group13_offset + 35] = lrat_dbg_entry2_entry_x; + assign debug_d[group13_offset + 36:group13_offset + 39] = lrat_dbg_entry2_size[0:3]; + assign debug_d[group13_offset + 40] = lrat_dbg_entry3_addr_match; // tag1 + assign debug_d[group13_offset + 41] = lrat_dbg_entry3_lpid_match; + assign debug_d[group13_offset + 42] = lrat_dbg_entry3_entry_v; + assign debug_d[group13_offset + 43] = lrat_dbg_entry3_entry_x; + assign debug_d[group13_offset + 44:group13_offset + 47] = lrat_dbg_entry3_size[0:3]; + assign debug_d[group13_offset + 48] = lrat_dbg_entry4_addr_match; // tag1 + assign debug_d[group13_offset + 49] = lrat_dbg_entry4_lpid_match; + assign debug_d[group13_offset + 50] = lrat_dbg_entry4_entry_v; + assign debug_d[group13_offset + 51] = lrat_dbg_entry4_entry_x; + assign debug_d[group13_offset + 52:group13_offset + 55] = lrat_dbg_entry4_size[0:3]; + assign debug_d[group13_offset + 56] = lrat_dbg_entry5_addr_match; // tag1 + assign debug_d[group13_offset + 57] = lrat_dbg_entry5_lpid_match; + assign debug_d[group13_offset + 58] = lrat_dbg_entry5_entry_v; + assign debug_d[group13_offset + 59] = lrat_dbg_entry5_entry_x; + assign debug_d[group13_offset + 60:group13_offset + 63] = lrat_dbg_entry5_size[0:3]; + assign debug_d[group13_offset + 64] = lrat_dbg_entry6_addr_match; // tag1 + assign debug_d[group13_offset + 65] = lrat_dbg_entry6_lpid_match; + assign debug_d[group13_offset + 66] = lrat_dbg_entry6_entry_v; + assign debug_d[group13_offset + 67] = lrat_dbg_entry6_entry_x; + assign debug_d[group13_offset + 68:group13_offset + 71] = lrat_dbg_entry6_size[0:3]; + assign debug_d[group13_offset + 72] = lrat_dbg_entry7_addr_match; // tag1 + assign debug_d[group13_offset + 73] = lrat_dbg_entry7_lpid_match; + assign debug_d[group13_offset + 74] = lrat_dbg_entry7_entry_v; + assign debug_d[group13_offset + 75] = lrat_dbg_entry7_entry_x; + assign debug_d[group13_offset + 76:group13_offset + 79] = lrat_dbg_entry7_size[0:3]; + + assign dbg_group13a[16:79] = debug_q[group13_offset + 16:group13_offset + 79]; // tag2 + assign dbg_group13a[80:87] = lrat_dbg_tag2_matchline_q[0:7]; + + // tlb_high_data + // [84] - [0] - X-bit + // [85:87] - [1:3] - reserved (3b) + // [88:117] - [4:33] - RPN (30b) + // [118:119] - [34:35] - R,C + // [120:121] - [36:37] - WLC (2b) + // [122] - [38] - ResvAttr + // [123] - [39] - VF + // [124] - [40] - IND + // [125:128] - [41:44] - U0-U3 + // [129:133] - [45:49] - WIMGE + // [134:135] - [50:51] - UX,SX + // [136:137] - [52:53] - UW,SW + // [138:139] - [54:55] - UR,SR + // [140] - [56] - GS + // [141] - [57] - TS + // [142:143] - [58:59] - reserved (2b) + // [144:149] - [60:65] - 6b TID msbs + // [150:157] - [66:73] - 8b TID lsbs + // [158:167] - [74:83] - parity 10bits + assign dbg_group13b[0:83] = tlb_cmp_dbg_tag5_way[84:167]; // tag5 way rpn + assign dbg_group13b[84] = (tlb_cmp_dbg_tag5_lru_dataout[0] & tlb_cmp_dbg_tag5_wayhit[0]) | (tlb_cmp_dbg_tag5_lru_dataout[1] & tlb_cmp_dbg_tag5_wayhit[1]) | (tlb_cmp_dbg_tag5_lru_dataout[2] & tlb_cmp_dbg_tag5_wayhit[2]) | (tlb_cmp_dbg_tag5_lru_dataout[3] & tlb_cmp_dbg_tag5_wayhit[3]); // valid + assign dbg_group13b[85] = (tlb_cmp_dbg_tag5_lru_dataout[8] & tlb_cmp_dbg_tag5_wayhit[0]) | (tlb_cmp_dbg_tag5_lru_dataout[9] & tlb_cmp_dbg_tag5_wayhit[1]) | (tlb_cmp_dbg_tag5_lru_dataout[10] & tlb_cmp_dbg_tag5_wayhit[2]) | (tlb_cmp_dbg_tag5_lru_dataout[11] & tlb_cmp_dbg_tag5_wayhit[3]); // iprot + assign dbg_group13b[86] = tlb_cmp_dbg_tag5_lru_dataout[4]; // encoded lru way msb + assign dbg_group13b[87] = ((~(tlb_cmp_dbg_tag5_lru_dataout[4])) & tlb_cmp_dbg_tag5_lru_dataout[5]) | (tlb_cmp_dbg_tag5_lru_dataout[4] & tlb_cmp_dbg_tag5_lru_dataout[6]); // encoded lru way lsb + + assign dbg_group13 = (mmucr2[9] == 1'b1) ? dbg_group13b : + dbg_group13a; + + //group14 (htw control) + assign dbg_group14a[0:1] = htw_dbg_seq_q[0:1]; + assign dbg_group14a[2:3] = htw_dbg_inptr_q[0:1]; + assign dbg_group14a[4] = htw_dbg_ptereload_ptr_q; + assign dbg_group14a[5:6] = htw_dbg_lsuptr_q[0:1]; + assign dbg_group14a[7] = htw_lsu_ttype[1]; + assign dbg_group14a[8:9] = htw_dbg_lsu_thdid[0:1]; // encoded + assign dbg_group14a[10:51] = htw_lsu_addr[22:63]; + assign dbg_group14a[52:54] = htw_dbg_pte0_seq_q[0:2]; + assign dbg_group14a[55:56] = htw_dbg_pte0_score_ptr_q[0:1]; + assign dbg_group14a[57:59] = htw_dbg_pte0_score_cl_offset_q[58:60]; + assign dbg_group14a[60:62] = htw_dbg_pte0_score_error_q[0:2]; + assign dbg_group14a[63:66] = htw_dbg_pte0_score_qwbeat_q[0:3]; // 4 beats of data per CL + assign dbg_group14a[67] = htw_dbg_pte0_score_pending_q; + assign dbg_group14a[68] = htw_dbg_pte0_score_ibit_q; + assign dbg_group14a[69] = htw_dbg_pte0_score_dataval_q; + assign dbg_group14a[70:72] = htw_dbg_pte1_seq_q[0:2]; + assign dbg_group14a[73:74] = htw_dbg_pte1_score_ptr_q[0:1]; + assign dbg_group14a[75:77] = htw_dbg_pte1_score_cl_offset_q[58:60]; + assign dbg_group14a[78:80] = htw_dbg_pte1_score_error_q[0:2]; + assign dbg_group14a[81:84] = htw_dbg_pte1_score_qwbeat_q[0:3]; // 4 beats of data per CL + assign dbg_group14a[85] = htw_dbg_pte1_score_pending_q; + assign dbg_group14a[86] = htw_dbg_pte1_score_ibit_q; + assign dbg_group14a[87] = htw_dbg_pte1_score_dataval_q; + + // tlb_low_data + // [0:51] - EPN + // [52:55] - SIZE (4b) + // [56:59] - ThdID + // [60:61] - Class + // [62] - ExtClass + // [63] - TID_NZ + // [64:65] - reserved (2b) + // [66:73] - 8b for LPID + // [74:83] - parity 10bits + + // tlb_high_data + // [84] - [0] - X-bit + // [85:87] - [1:3] - reserved (3b) + // [88:117] - [4:33] - RPN (30b) + // [118:119] - [34:35] - R,C + // [120:121] - [36:37] - WLC (2b) + // [122] - [38] - ResvAttr + // [123] - [39] - VF + // [124] - [40] - IND + // [125:128] - [41:44] - U0-U3 + // [129:133] - [45:49] - WIMGE + // [134:135] - [50:51] - UX,SX + // [136:137] - [52:53] - UW,SW + // [138:139] - [54:55] - UR,SR + // [140] - [56] - GS + // [141] - [57] - TS + // [142:143] - [58:59] - reserved (2b) + // [144:149] - [60:65] - 6b TID msbs + // [150:157] - [66:73] - 8b TID lsbs + // [158:167] - [74:83] - parity 10bits + assign dbg_group14b[0] = (tlb_cmp_dbg_tag5_lru_dataout[0] & tlb_cmp_dbg_tag5_wayhit[0]) | (tlb_cmp_dbg_tag5_lru_dataout[1] & tlb_cmp_dbg_tag5_wayhit[1]) | (tlb_cmp_dbg_tag5_lru_dataout[2] & tlb_cmp_dbg_tag5_wayhit[2]) | (tlb_cmp_dbg_tag5_lru_dataout[3] & tlb_cmp_dbg_tag5_wayhit[3]); // valid + assign dbg_group14b[1] = (tlb_cmp_dbg_tag5_lru_dataout[8] & tlb_cmp_dbg_tag5_wayhit[0]) | (tlb_cmp_dbg_tag5_lru_dataout[9] & tlb_cmp_dbg_tag5_wayhit[1]) | (tlb_cmp_dbg_tag5_lru_dataout[10] & tlb_cmp_dbg_tag5_wayhit[2]) | (tlb_cmp_dbg_tag5_lru_dataout[11] & tlb_cmp_dbg_tag5_wayhit[3]); // iprot + + assign dbg_group14b[2] = tlb_cmp_dbg_tag5_way[140]; // gs + assign dbg_group14b[3] = tlb_cmp_dbg_tag5_way[141]; // ts + assign dbg_group14b[4:11] = tlb_cmp_dbg_tag5_way[66:73]; // tlpid + assign dbg_group14b[12:25] = tlb_cmp_dbg_tag5_way[144:157]; // tid, 14bits + assign dbg_group14b[26:45] = tlb_cmp_dbg_tag5_way[32:51]; // epn truncated to lower 20b + assign dbg_group14b[46:49] = tlb_cmp_dbg_tag5_way[52:55]; // size + assign dbg_group14b[50:53] = tlb_cmp_dbg_tag5_way[56:59]; // thdid + assign dbg_group14b[54] = tlb_cmp_dbg_tag5_way[84]; // xbit + assign dbg_group14b[55] = tlb_cmp_dbg_tag5_way[40]; // ind + assign dbg_group14b[56:57] = tlb_cmp_dbg_tag5_way[60:61]; // class + assign dbg_group14b[58:77] = tlb_cmp_dbg_tag5_way[98:117]; // rpn truncated to lower 20b + assign dbg_group14b[78:81] = tlb_cmp_dbg_tag5_way[130:133]; // imge + assign dbg_group14b[82:87] = tlb_cmp_dbg_tag5_way[134:139]; // user/sup prot bits + + assign dbg_group14 = (mmucr2[10] == 1'b1) ? dbg_group14b : + dbg_group14a; + + //group15 (ptereload pte) + assign dbg_group15a[0:1] = htw_dbg_seq_q[0:1]; + assign dbg_group15a[2:4] = htw_dbg_pte0_seq_q[0:2]; + assign dbg_group15a[5:7] = htw_dbg_pte1_seq_q[0:2]; + assign dbg_group15a[8] = htw_lsu_req_valid; + assign dbg_group15a[9:21] = htw_lsu_addr[48:60]; + assign dbg_group15a[22] = htw_dbg_ptereload_ptr_q; + assign dbg_group15a[23] = ptereload_req_taken; + assign dbg_group15a[24:87] = ptereload_req_pte[0:63]; // pte entry + + assign dbg_group15b[0:73] = tlb_cmp_dbg_tag5_way[0:73]; // tag5 way epn + assign dbg_group15b[74:77] = tlb_cmp_dbg_tag5_lru_dataout[0:3]; + assign dbg_group15b[78:81] = tlb_cmp_dbg_tag5_lru_dataout[8:11]; + assign dbg_group15b[82] = tlb_cmp_dbg_tag5_lru_dataout[4]; // encoded lsu way msb + assign dbg_group15b[83] = ((~(tlb_cmp_dbg_tag5_lru_dataout[4])) & tlb_cmp_dbg_tag5_lru_dataout[5]) | (tlb_cmp_dbg_tag5_lru_dataout[4] & tlb_cmp_dbg_tag5_lru_dataout[6]); // encoded lsu way lsb + assign dbg_group15b[84:87] = tlb_cmp_dbg_tag5_wayhit[0:3]; + + assign dbg_group15 = (mmucr2[10] == 1'b1) ? dbg_group15b : + dbg_group15a; + + // trigger group0 + assign trg_group0[0] = (~(tlb_ctl_dbg_seq_idle)); + assign trg_group0[1:2] = tlb_ctl_dbg_tag0_thdid[0:1]; // encoded + assign trg_group0[3:5] = tlb_ctl_dbg_tag0_type[0:2]; // encoded + assign trg_group0[6] = (~(inval_dbg_seq_idle)); + assign trg_group0[7] = inval_dbg_seq_snoop_inprogress; // bus snoop + assign trg_group0[8] = (~(htw_dbg_seq_idle)); + assign trg_group0[9] = (~(htw_dbg_pte0_seq_idle)); + assign trg_group0[10] = (~(htw_dbg_pte1_seq_idle)); + assign trg_group0[11] = tlb_cmp_dbg_tag5_any_exception; // big or gate + + // trigger group1 + assign trg_group1[0:5] = tlb_ctl_dbg_seq_q[0:5]; + assign trg_group1[6:10] = inval_dbg_seq_q[0:4]; + assign trg_group1[11] = tlb_ctl_dbg_seq_any_done_sig | tlb_ctl_dbg_seq_abort | inval_dbg_seq_snoop_done | inval_dbg_seq_local_done | inval_dbg_seq_tlb0fi_done | inval_dbg_seq_tlbwe_snoop_done; + + // trigger group2 + assign trg_group2[0] = tlb_req_dbg_ierat_iu5_valid_q; + assign trg_group2[1] = tlb_req_dbg_derat_ex6_valid_q; + assign trg_group2[2] = tlb_ctl_dbg_any_tlb_req_sig; + assign trg_group2[3] = tlb_ctl_dbg_any_req_taken_sig; + assign trg_group2[4] = tlb_ctl_dbg_seq_any_done_sig | tlb_ctl_dbg_seq_abort; + assign trg_group2[5] = inval_dbg_ex6_valid; //--------------> need tlbivax/erativax indication? + assign trg_group2[6] = mmucsr0_tlb0fi; + assign trg_group2[7] = inval_dbg_snoop_forme; + assign trg_group2[8] = tlbwe_back_inv_valid; + assign trg_group2[9] = htw_lsu_req_valid; + assign trg_group2[10] = inval_dbg_seq_snoop_done | inval_dbg_seq_local_done | inval_dbg_seq_tlb0fi_done | inval_dbg_seq_tlbwe_snoop_done; + assign trg_group2[11] = |(mm_xu_lsu_req); + + // trigger group3 + assign trg_group3a[0] = spr_dbg_slowspr_val_int; + assign trg_group3a[1] = spr_dbg_slowspr_rw_int; + assign trg_group3a[2:3] = spr_dbg_slowspr_etid_int; + assign trg_group3a[4] = spr_dbg_match_64b; + assign trg_group3a[5] = spr_dbg_match_any_mmu; // int phase + assign trg_group3a[6] = spr_dbg_match_any_mas; + assign trg_group3a[7] = spr_dbg_match_mmucr0 | spr_dbg_match_mmucr1 | spr_dbg_match_mmucr2 | spr_dbg_match_mmucr3; + assign trg_group3a[8] = spr_dbg_match_pid | spr_dbg_match_lpidr; + assign trg_group3a[9] = spr_dbg_match_lper | spr_dbg_match_lperu; + assign trg_group3a[10] = spr_dbg_slowspr_val_out; + assign trg_group3a[11] = spr_dbg_slowspr_done_out; + + assign trg_group3b[0] = tlb_htw_req_valid; + assign trg_group3b[1:2] = htw_dbg_seq_q[0:1]; + assign trg_group3b[3:5] = htw_dbg_pte0_seq_q[0:2]; + assign trg_group3b[6:8] = htw_dbg_pte1_seq_q[0:2]; + assign trg_group3b[9] = htw_dbg_pte0_reld_for_me_tm1 | htw_dbg_pte1_reld_for_me_tm1; + assign trg_group3b[10] = |(htw_dbg_pte0_score_error_q | htw_dbg_pte1_score_error_q); + assign trg_group3b[11] = tlb_cmp_dbg_tag5_any_exception; + + assign trg_group3 = (mmucr2[11] == 1'b1) ? trg_group3b : + trg_group3a; + + tri_debug_mux16 #(.DBG_WIDTH(`DEBUG_TRACE_WIDTH)) dbg_mux0( + .select_bits(pc_mm_debug_mux1_ctrls_loc_q), + .trace_data_in(debug_bus_in_q), + + .dbg_group0(dbg_group0[0:31]), + .dbg_group1(dbg_group1[0:31]), + .dbg_group2(dbg_group2[0:31]), + .dbg_group3(dbg_group3[0:31]), + .dbg_group4(dbg_group4[0:31]), + .dbg_group5(dbg_group5[0:31]), + .dbg_group6(dbg_group6[0:31]), + .dbg_group7(dbg_group7[0:31]), + .dbg_group8(dbg_group8[0:31]), + .dbg_group9(dbg_group9[0:31]), + .dbg_group10(dbg_group10[0:31]), + .dbg_group11(dbg_group11[0:31]), + .dbg_group12(dbg_group12[0:31]), + .dbg_group13(dbg_group13[0:31]), + .dbg_group14(dbg_group14[0:31]), + .dbg_group15(dbg_group15[0:31]), + + .trace_data_out(trace_data_out_d), + + // Instruction Trace (HTM) Control Signals: + // 0 - ac_an_coretrace_first_valid + // 1 - ac_an_coretrace_valid + // 2:3 - ac_an_coretrace_type[0:1] + .coretrace_ctrls_in(coretrace_ctrls_in_q), // input [0:3] + .coretrace_ctrls_out(coretrace_ctrls_out_d) // output [0:3] + + ); + + assign debug_bus_out = trace_data_out_q; + assign coretrace_ctrls_out = coretrace_ctrls_out_q; + + + // unused spare signal assignments + assign unused_dc[0] = tlb_mas_thdid[0]; + assign unused_dc[1] = lrat_mas_thdid[0]; + assign unused_dc[2] = lrat_mas_thdid[0]; + assign unused_dc[3] = inval_dbg_lsu_tokens_q[0]; + assign unused_dc[4] = tlb_cmp_dbg_tag4[82]; // `tagpos_derat, not used for type encoding of '0' + assign unused_dc[5] = tlb_cmp_dbg_tag4[106]; // `tagpos_lrat + + assign unused_dc[6] = |(tlb_cmp_dbg_tag4[0:7]); // `tagpos_epn + assign unused_dc[7] = |(tlb_cmp_dbg_tag4[8:15]); + assign unused_dc[8] = tlb_cmp_dbg_tag5_wayhit[4]; + + generate + if (`TLB_TAG_WIDTH > 110) + begin : itagExist + assign unused_dc[9] = debug_q[23] | |(tlb_cmp_dbg_tag4[110:`TLB_TAG_WIDTH - 1]); // tag bits + end + endgenerate + + generate + if (`TLB_TAG_WIDTH < 111) + begin : itagNExist + assign unused_dc[9] = debug_q[23]; // tag bits + end + endgenerate + + assign unused_dc[10] = |(trigger_q[0:47]); + assign unused_dc[11] = tlb_cmp_dbg_tag5_lru_dataout[7]; // lru parity bit + + //--------------------------------------------------------------------- + // Latches + //--------------------------------------------------------------------- + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(0)) trace_bus_enable_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(pc_func_slp_sl_force), + .d_mode(lcb_d_mode_dc), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .scin(siv[trace_bus_enable_offset]), + .scout(sov[trace_bus_enable_offset]), + .din(pc_mm_trace_bus_enable), + .dout(pc_mm_trace_bus_enable_q) + ); + +//======================================================================================== + tri_rlmreg_p #(.WIDTH(11), .INIT(0), .NEEDS_SRESET(0)) debug_mux1_ctrls_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(pc_mm_trace_bus_enable_q), + .force_t(pc_func_slp_sl_force), + .d_mode(lcb_d_mode_dc), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .scin(siv[debug_mux1_ctrls_offset:debug_mux1_ctrls_offset + 11 - 1]), + .scout(sov[debug_mux1_ctrls_offset:debug_mux1_ctrls_offset + 11 - 1]), + .din(pc_mm_debug_mux1_ctrls), + .dout(pc_mm_debug_mux1_ctrls_q) + ); + + tri_rlmreg_p #(.WIDTH(11), .INIT(0), .NEEDS_SRESET(0)) debug_mux1_ctrls_loc_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(pc_mm_trace_bus_enable_q), + .force_t(pc_func_slp_sl_force), + .d_mode(lcb_d_mode_dc), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .scin(siv[debug_mux1_ctrls_loc_offset:debug_mux1_ctrls_loc_offset + 11 - 1]), + .scout(sov[debug_mux1_ctrls_loc_offset:debug_mux1_ctrls_loc_offset + 11 - 1]), + .din(pc_mm_debug_mux1_ctrls_loc_d), + .dout(pc_mm_debug_mux1_ctrls_loc_q) + ); +//======================================================================================== + + tri_rlmreg_p #(.WIDTH(`DEBUG_TRIGGER_WIDTH), .INIT(0)) trigger_data_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pc_mm_trace_bus_enable_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[trigger_data_out_offset:trigger_data_out_offset + 12 - 1]), + .scout(sov[trigger_data_out_offset:trigger_data_out_offset + 12 - 1]), + .din({12{1'b0}}), + .dout(trigger_data_out_q) + ); + + + tri_rlmreg_p #(.WIDTH(`DEBUG_TRACE_WIDTH), .INIT(0)) trace_data_out_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pc_mm_trace_bus_enable_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[trace_data_out_offset:trace_data_out_offset + `DEBUG_TRACE_WIDTH - 1]), + .scout(sov[trace_data_out_offset:trace_data_out_offset + `DEBUG_TRACE_WIDTH - 1]), + .din(trace_data_out_d), + .dout(trace_data_out_q) + ); + + + tri_rlmreg_p #(.WIDTH(8), .INIT(0)) trace_data_out_int_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pc_mm_trace_bus_enable_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[trace_data_out_int_offset:trace_data_out_int_offset + 8 - 1]), + .scout(sov[trace_data_out_int_offset:trace_data_out_int_offset + 8 - 1]), + .din(trace_data_out_d[0:7]), + .dout(trace_data_out_int_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) coretrace_ctrls_out_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pc_mm_trace_bus_enable_q), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[coretrace_ctrls_out_offset:coretrace_ctrls_out_offset + 4 - 1]), + .scout(sov[coretrace_ctrls_out_offset:coretrace_ctrls_out_offset + 4 - 1]), + .din(coretrace_ctrls_out_d), + .dout(coretrace_ctrls_out_q) + ); + + + tri_regk #(.WIDTH(DEBUG_LATCH_WIDTH), .INIT(0), .NEEDS_SRESET(0)) debug_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(pc_mm_trace_bus_enable_q), + .sg(pc_sg_0), + .force_t(pc_func_slp_nsl_force), + .d_mode(lcb_d_mode_dc), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .thold_b(pc_func_slp_nsl_thold_0_b), + .scin(unused_debug_latch_scan), + .scout(unused_debug_latch_scan), + .din(debug_d), + .dout(debug_q) + ); + + + tri_regk #(.WIDTH(TRIGGER_LATCH_WIDTH), .INIT(0), .NEEDS_SRESET(0)) trigger_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(pc_mm_trace_bus_enable_q), + .sg(pc_sg_0), + .force_t(pc_func_slp_nsl_force), + .d_mode(lcb_d_mode_dc), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .thold_b(pc_func_slp_nsl_thold_0_b), + .scin(unused_trigger_latch_scan), + .scout(unused_trigger_latch_scan), + .din(trigger_d), + .dout(trigger_q) + ); + + + tri_regk #(.WIDTH(`DEBUG_TRACE_WIDTH), .INIT(0), .NEEDS_SRESET(0)) debug_bus_in_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(pc_mm_trace_bus_enable_q), + .sg(pc_sg_0), + .force_t(pc_func_slp_nsl_force), + .d_mode(lcb_d_mode_dc), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .thold_b(pc_func_slp_nsl_thold_0_b), + .scin(unused_busin_latch_scan), + .scout(unused_busin_latch_scan), + .din(debug_bus_in), + .dout(debug_bus_in_q) + ); + + + tri_regk #(.WIDTH(`DEBUG_TRIGGER_WIDTH), .INIT(0), .NEEDS_SRESET(0)) trace_triggers_in_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(pc_mm_trace_bus_enable_q), + .force_t(pc_func_slp_nsl_force), + .sg(pc_sg_0), + .d_mode(lcb_d_mode_dc), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .thold_b(pc_func_slp_nsl_thold_0_b), + .scin(unused_trigin_latch_scan), + .scout(unused_trigin_latch_scan), + .din({12{1'b0}}), + .dout(trace_triggers_in_q) + ); + + tri_regk #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(0)) coretrace_ctrls_in_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(pc_mm_trace_bus_enable_q), + .force_t(pc_func_slp_nsl_force), + .sg(pc_sg_0), + .d_mode(lcb_d_mode_dc), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .thold_b(pc_func_slp_nsl_thold_0_b), + .scin(unused_coretrace_ctrls_in_latch_scan), + .scout(unused_coretrace_ctrls_in_latch_scan), + .din(coretrace_ctrls_in), + .dout(coretrace_ctrls_in_q) + ); + + //----------------------------------------------- + // pervasive + //----------------------------------------------- + + + tri_plat #(.WIDTH(4)) perv_2to1_plat( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + .din( {pc_func_slp_sl_thold_2, pc_func_slp_nsl_thold_2, pc_sg_2, pc_fce_2} ), + .q( {pc_func_slp_sl_thold_1, pc_func_slp_nsl_thold_1, pc_sg_1, pc_fce_1} ) + ); + + + tri_plat #(.WIDTH(4)) perv_1to0_plat( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + .din( {pc_func_slp_sl_thold_1, pc_func_slp_nsl_thold_1, pc_sg_1, pc_fce_1} ), + .q( {pc_func_slp_sl_thold_0, pc_func_slp_nsl_thold_0, pc_sg_0, pc_fce_0} ) + ); + + + tri_lcbor perv_sl_lcbor( + .clkoff_b(lcb_clkoff_dc_b), + .thold(pc_func_slp_sl_thold_0), + .sg(pc_sg_0), + .act_dis(lcb_act_dis_dc), + .force_t(pc_func_slp_sl_force), + .thold_b(pc_func_slp_sl_thold_0_b) + ); + + + tri_lcbor perv_nsl_lcbor( + .clkoff_b(lcb_clkoff_dc_b), + .thold(pc_func_slp_nsl_thold_0), + .sg(pc_fce_0), + .act_dis(tidn), + .force_t(pc_func_slp_nsl_force), + .thold_b(pc_func_slp_nsl_thold_0_b) + ); + + //--------------------------------------------------------------------- + // Scan + //--------------------------------------------------------------------- + assign siv[0:scan_right] = {sov[1:scan_right], scan_in}; + assign scan_out = sov[0]; + + +endmodule diff --git a/dev/verilog/work/mmq_htw.v b/dev/verilog/work/mmq_htw.v new file mode 100755 index 0000000..5c7f921 --- /dev/null +++ b/dev/verilog/work/mmq_htw.v @@ -0,0 +1,2864 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +//******************************************************************** +//* TITLE: Memory Management Unit Hardware Table Walker Logic +//********************************************************************* + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" +`include "mmu_a2o.vh" +`define HTW_SEQ_WIDTH 2 +`define PTE_SEQ_WIDTH 3 + + +module mmq_htw( + inout vdd, + inout gnd, + (* pin_data ="PIN_FUNCTION=/G_CLK/" *) + input [0:`NCLK_WIDTH-1] nclk, + + input tc_ccflush_dc, + input tc_scan_dis_dc_b, + input tc_scan_diag_dc, + input tc_lbist_en_dc, + input lcb_d_mode_dc, + input lcb_clkoff_dc_b, + input lcb_act_dis_dc, + input [0:4] lcb_mpw1_dc_b, + input lcb_mpw2_dc_b, + input [0:4] lcb_delay_lclkr_dc, + input pc_sg_2, + input pc_func_sl_thold_2, + input pc_func_slp_sl_thold_2, + +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + input [0:1] ac_func_scan_in, +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + output [0:1] ac_func_scan_out, + + input xu_mm_ccr2_notlb_b, + input mmucr2_act_override, + input [24:28] tlb_delayed_act, + input [0:`MM_THREADS-1] tlb_ctl_tag2_flush, + input [0:`MM_THREADS-1] tlb_ctl_tag3_flush, + input [0:`MM_THREADS-1] tlb_ctl_tag4_flush, + input [0:`TLB_TAG_WIDTH-1] tlb_tag2, + input [0:`MM_THREADS-1] tlb_tag5_except, + input tlb_htw_req_valid, + input [0:`TLB_TAG_WIDTH-1] tlb_htw_req_tag, + input [`TLB_WORD_WIDTH:`TLB_WAY_WIDTH-1] tlb_htw_req_way, + output reg htw_lsu_req_valid, + output [0:`THDID_WIDTH-1] htw_lsu_thdid, + output [0:1] htw_dbg_lsu_thdid, + output [0:1] htw_lsu_ttype, + output [0:4] htw_lsu_wimge, + output [0:3] htw_lsu_u, + output [64-`REAL_ADDR_WIDTH:63] htw_lsu_addr, + input htw_lsu_req_taken, + output [0:`THDID_WIDTH-1] htw_quiesce, + output htw_req0_valid, + output [0:`THDID_WIDTH-1] htw_req0_thdid, + output [0:1] htw_req0_type, + output htw_req1_valid, + output [0:`THDID_WIDTH-1] htw_req1_thdid, + output [0:1] htw_req1_type, + output htw_req2_valid, + output [0:`THDID_WIDTH-1] htw_req2_thdid, + output [0:1] htw_req2_type, + output htw_req3_valid, + output [0:`THDID_WIDTH-1] htw_req3_thdid, + output [0:1] htw_req3_type, + output ptereload_req_valid, + output [0:`TLB_TAG_WIDTH-1] ptereload_req_tag, + output [0:`PTE_WIDTH-1] ptereload_req_pte, + input ptereload_req_taken, + input [0:4] an_ac_reld_core_tag, + input [0:127] an_ac_reld_data, + input an_ac_reld_data_vld, + input an_ac_reld_ecc_err, + input an_ac_reld_ecc_err_ue, + input [58:59] an_ac_reld_qw, + input an_ac_reld_ditc, + input an_ac_reld_crit_qw, + output htw_dbg_seq_idle, + output htw_dbg_pte0_seq_idle, + output htw_dbg_pte1_seq_idle, + output [0:1] htw_dbg_seq_q, + output [0:1] htw_dbg_inptr_q, + output [0:2] htw_dbg_pte0_seq_q, + output [0:2] htw_dbg_pte1_seq_q, + output htw_dbg_ptereload_ptr_q, + output [0:1] htw_dbg_lsuptr_q, + output [0:3] htw_dbg_req_valid_q, + output [0:3] htw_dbg_resv_valid_vec, + output [0:3] htw_dbg_tag4_clr_resv_q, + output [0:3] htw_dbg_tag4_clr_resv_terms, + output [0:1] htw_dbg_pte0_score_ptr_q, + output [58:60] htw_dbg_pte0_score_cl_offset_q, + output [0:2] htw_dbg_pte0_score_error_q, + output [0:3] htw_dbg_pte0_score_qwbeat_q, + output htw_dbg_pte0_score_pending_q, + output htw_dbg_pte0_score_ibit_q, + output htw_dbg_pte0_score_dataval_q, + output htw_dbg_pte0_reld_for_me_tm1, + output [0:1] htw_dbg_pte1_score_ptr_q, + output [58:60] htw_dbg_pte1_score_cl_offset_q, + output [0:2] htw_dbg_pte1_score_error_q, + output [0:3] htw_dbg_pte1_score_qwbeat_q, + output htw_dbg_pte1_score_pending_q, + output htw_dbg_pte1_score_ibit_q, + output htw_dbg_pte1_score_dataval_q, + + output htw_dbg_pte1_reld_for_me_tm1 + +); + + + + parameter MMU_Mode_Value = 1'b0; + parameter [0:1] TlbSel_Tlb = 2'b00; + parameter [0:1] TlbSel_IErat = 2'b10; + parameter [0:1] TlbSel_DErat = 2'b11; + parameter [0:4] Core_Tag0_Value = 5'b01100; + parameter [0:4] Core_Tag1_Value = 5'b01101; + parameter [0:2] ERAT_PgSize_1GB = 3'b110; + parameter [0:2] ERAT_PgSize_16MB = 3'b111; + parameter [0:2] ERAT_PgSize_1MB = 3'b101; + parameter [0:2] ERAT_PgSize_64KB = 3'b011; + parameter [0:2] ERAT_PgSize_4KB = 3'b001; + parameter [0:3] TLB_PgSize_1GB = 4'b1010; + parameter [0:3] TLB_PgSize_16MB = 4'b0111; + parameter [0:3] TLB_PgSize_1MB = 4'b0101; + parameter [0:3] TLB_PgSize_64KB = 4'b0011; + parameter [0:3] TLB_PgSize_4KB = 4'b0001; + // reserved for indirect entries + parameter [0:2] ERAT_PgSize_256MB = 3'b100; + parameter [0:3] TLB_PgSize_256MB = 4'b1001; + parameter [0:1] HtwSeq_Idle = 2'b00; + parameter [0:1] HtwSeq_Stg1 = 2'b01; + parameter [0:1] HtwSeq_Stg2 = 2'b11; + parameter [0:1] HtwSeq_Stg3 = 2'b10; + parameter [0:2] PteSeq_Idle = 3'b000; + parameter [0:2] PteSeq_Stg1 = 3'b001; + parameter [0:2] PteSeq_Stg2 = 3'b011; + parameter [0:2] PteSeq_Stg3 = 3'b010; + parameter [0:2] PteSeq_Stg4 = 3'b110; + parameter [0:2] PteSeq_Stg5 = 3'b111; + parameter [0:2] PteSeq_Stg6 = 3'b101; + parameter [0:2] PteSeq_Stg7 = 3'b100; + //constant command_width : integer := (EFF_IFAR'length+ibuff_data_width); + + parameter tlb_htw_req0_valid_offset = 0; + parameter tlb_htw_req0_pending_offset = tlb_htw_req0_valid_offset + 1; + parameter tlb_htw_req0_tag_offset = tlb_htw_req0_pending_offset + 1; + parameter tlb_htw_req0_way_offset = tlb_htw_req0_tag_offset + `TLB_TAG_WIDTH; + parameter tlb_htw_req1_valid_offset = tlb_htw_req0_way_offset + `TLB_WORD_WIDTH; + parameter tlb_htw_req1_pending_offset = tlb_htw_req1_valid_offset + 1; + parameter tlb_htw_req1_tag_offset = tlb_htw_req1_pending_offset + 1; + parameter tlb_htw_req1_way_offset = tlb_htw_req1_tag_offset + `TLB_TAG_WIDTH; + parameter tlb_htw_req2_valid_offset = tlb_htw_req1_way_offset + `TLB_WORD_WIDTH; + parameter tlb_htw_req2_pending_offset = tlb_htw_req2_valid_offset + 1; + parameter tlb_htw_req2_tag_offset = tlb_htw_req2_pending_offset + 1; + parameter tlb_htw_req2_way_offset = tlb_htw_req2_tag_offset + `TLB_TAG_WIDTH; + parameter tlb_htw_req3_valid_offset = tlb_htw_req2_way_offset + `TLB_WORD_WIDTH; + parameter tlb_htw_req3_pending_offset = tlb_htw_req3_valid_offset + 1; + parameter tlb_htw_req3_tag_offset = tlb_htw_req3_pending_offset + 1; + parameter tlb_htw_req3_way_offset = tlb_htw_req3_tag_offset + `TLB_TAG_WIDTH; + parameter spare_a_offset = tlb_htw_req3_way_offset + `TLB_WORD_WIDTH; + parameter scan_right_0 = spare_a_offset + 16 - 1; + parameter htw_seq_offset = 0; + parameter htw_inptr_offset = htw_seq_offset + `HTW_SEQ_WIDTH; + parameter htw_lsuptr_offset = htw_inptr_offset + 2; + parameter htw_lsu_ttype_offset = htw_lsuptr_offset + 2; + parameter htw_lsu_thdid_offset = htw_lsu_ttype_offset + 2; + parameter htw_lsu_wimge_offset = htw_lsu_thdid_offset + `THDID_WIDTH; + parameter htw_lsu_u_offset = htw_lsu_wimge_offset + 5; + parameter htw_lsu_addr_offset = htw_lsu_u_offset + 4; + parameter pte0_seq_offset = htw_lsu_addr_offset + `REAL_ADDR_WIDTH; + parameter pte0_score_ptr_offset = pte0_seq_offset + `PTE_SEQ_WIDTH; + parameter pte0_score_cl_offset_offset = pte0_score_ptr_offset + 2; + parameter pte0_score_error_offset = pte0_score_cl_offset_offset + 3; + parameter pte0_score_qwbeat_offset = pte0_score_error_offset + 3; + parameter pte0_score_ibit_offset = pte0_score_qwbeat_offset + 4; + parameter pte0_score_pending_offset = pte0_score_ibit_offset + 1; + parameter pte0_score_dataval_offset = pte0_score_pending_offset + 1; + parameter pte1_seq_offset = pte0_score_dataval_offset + 1; + parameter pte1_score_ptr_offset = pte1_seq_offset + `PTE_SEQ_WIDTH; + parameter pte1_score_cl_offset_offset = pte1_score_ptr_offset + 2; + parameter pte1_score_error_offset = pte1_score_cl_offset_offset + 3; + parameter pte1_score_qwbeat_offset = pte1_score_error_offset + 3; + parameter pte1_score_ibit_offset = pte1_score_qwbeat_offset + 4; + parameter pte1_score_pending_offset = pte1_score_ibit_offset + 1; + parameter pte1_score_dataval_offset = pte1_score_pending_offset + 1; + parameter pte_load_ptr_offset = pte1_score_dataval_offset + 1; + parameter ptereload_ptr_offset = pte_load_ptr_offset + 1; + // ptereload_ptr_offset + 1 phase + parameter reld_core_tag_tm1_offset = ptereload_ptr_offset + 1; + parameter reld_qw_tm1_offset = reld_core_tag_tm1_offset + 5; + parameter reld_crit_qw_tm1_offset = reld_qw_tm1_offset + 2; + parameter reld_ditc_tm1_offset = reld_crit_qw_tm1_offset + 1; + parameter reld_data_vld_tm1_offset = reld_ditc_tm1_offset + 1; + // reld_data_vld_tm1_offset + 1 phase + parameter reld_core_tag_t_offset = reld_data_vld_tm1_offset + 1; + parameter reld_qw_t_offset = reld_core_tag_t_offset + 5; + parameter reld_crit_qw_t_offset = reld_qw_t_offset + 2; + parameter reld_ditc_t_offset = reld_crit_qw_t_offset + 1; + parameter reld_data_vld_t_offset = reld_ditc_t_offset + 1; + // reld_data_vld_t_offset + 1 phase + parameter reld_core_tag_tp1_offset = reld_data_vld_t_offset + 1; + parameter reld_qw_tp1_offset = reld_core_tag_tp1_offset + 5; + parameter reld_crit_qw_tp1_offset = reld_qw_tp1_offset + 2; + parameter reld_ditc_tp1_offset = reld_crit_qw_tp1_offset + 1; + parameter reld_data_vld_tp1_offset = reld_ditc_tp1_offset + 1; + // reld_data_vld_tp1_offset + 1 phase + parameter reld_core_tag_tp2_offset = reld_data_vld_tp1_offset + 1; + parameter reld_qw_tp2_offset = reld_core_tag_tp2_offset + 5; + parameter reld_crit_qw_tp2_offset = reld_qw_tp2_offset + 2; + parameter reld_ditc_tp2_offset = reld_crit_qw_tp2_offset + 1; + parameter reld_data_vld_tp2_offset = reld_ditc_tp2_offset + 1; + parameter reld_ecc_err_tp2_offset = reld_data_vld_tp2_offset + 1; + parameter reld_ecc_err_ue_tp2_offset = reld_ecc_err_tp2_offset + 1; + parameter reld_data_tp1_offset = reld_ecc_err_ue_tp2_offset + 1; + parameter reld_data_tp2_offset = reld_data_tp1_offset + 128; + parameter pte0_reld_data_tp3_offset = reld_data_tp2_offset + 128; + parameter pte1_reld_data_tp3_offset = pte0_reld_data_tp3_offset + 64; + parameter htw_tag3_offset = pte1_reld_data_tp3_offset + 64; + parameter htw_tag4_clr_resv_offset = htw_tag3_offset + `TLB_TAG_WIDTH; + parameter htw_tag5_clr_resv_offset = htw_tag4_clr_resv_offset + `THDID_WIDTH; + parameter spare_b_offset = htw_tag5_clr_resv_offset + `THDID_WIDTH; + parameter scan_right_1 = spare_b_offset + 16 - 1; + +`ifdef MM_THREADS2 + parameter BUGSP_MM_THREADS = 2; +`else + parameter BUGSP_MM_THREADS = 1; +`endif + + //tlb_tag0_d <= ( 0:51 epn & + // 52:65 pid & + // 66:67 IS, or derat_ttype & + // 68:69 Class & + // 70:73 state (pr,gs,as,cm) & + // 74:77 thdid & + // 78:81 size & + // 82:83 derat_miss/ierat_miss & + // 84:85 tlbsx/tlbsrx & + // 86:87 inval_snoop/tlbre & + // 88:89 tlbwe/ptereload & + // 90:97 lpid & + // 98 indirect + // 99 atsel & + // 100:102 esel, or ptereload errors & + // 103:105 hes/wq(0:1) & + // 106:107 ltwe/lpte & + // 108 recform, or ptrpn for ptereloads + // 109 endflag + + // ttype: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload + + // state: 0:pr 1:gs 2:as 3:cm + + // Latch signals + reg [0:1] htw_seq_d; + wire [0:1] htw_seq_q; + wire [0:1] htw_inptr_d; + wire [0:1] htw_inptr_q; + wire [0:1] htw_lsuptr_d; + wire [0:1] htw_lsuptr_q; + wire [0:1] htw_lsu_ttype_d; + wire [0:1] htw_lsu_ttype_q; + wire [0:`THDID_WIDTH-1] htw_lsu_thdid_d; + wire [0:`THDID_WIDTH-1] htw_lsu_thdid_q; + wire [0:4] htw_lsu_wimge_d; + wire [0:4] htw_lsu_wimge_q; + wire [0:3] htw_lsu_u_d; + wire [0:3] htw_lsu_u_q; + wire [64-`REAL_ADDR_WIDTH:63] htw_lsu_addr_d; + wire [64-`REAL_ADDR_WIDTH:63] htw_lsu_addr_q; + reg [0:2] pte0_seq_d; + wire [0:2] pte0_seq_q; + wire [0:1] pte0_score_ptr_d; + wire [0:1] pte0_score_ptr_q; + wire [58:60] pte0_score_cl_offset_d; + wire [58:60] pte0_score_cl_offset_q; + wire [0:2] pte0_score_error_d; + wire [0:2] pte0_score_error_q; + wire [0:3] pte0_score_qwbeat_d; + wire [0:3] pte0_score_qwbeat_q; + wire pte0_score_pending_d; + wire pte0_score_pending_q; + wire pte0_score_ibit_d; + wire pte0_score_ibit_q; + wire pte0_score_dataval_d; + wire pte0_score_dataval_q; + reg [0:2] pte1_seq_d; + wire [0:2] pte1_seq_q; + wire [0:1] pte1_score_ptr_d; + wire [0:1] pte1_score_ptr_q; + wire [58:60] pte1_score_cl_offset_d; + wire [58:60] pte1_score_cl_offset_q; + wire [0:2] pte1_score_error_d; + wire [0:2] pte1_score_error_q; + wire [0:3] pte1_score_qwbeat_d; + wire [0:3] pte1_score_qwbeat_q; + wire pte1_score_pending_d; + wire pte1_score_pending_q; + wire pte1_score_ibit_d; + wire pte1_score_ibit_q; + wire pte1_score_dataval_d; + wire pte1_score_dataval_q; + wire ptereload_ptr_d; + wire ptereload_ptr_q; + wire pte_load_ptr_d; + wire pte_load_ptr_q; + wire tlb_htw_req0_valid_d; + wire tlb_htw_req0_valid_q; + wire tlb_htw_req0_pending_d; + wire tlb_htw_req0_pending_q; + wire [0:`TLB_TAG_WIDTH-1] tlb_htw_req0_tag_d; + wire [0:`TLB_TAG_WIDTH-1] tlb_htw_req0_tag_q; + wire [`TLB_WORD_WIDTH:`TLB_WAY_WIDTH-1] tlb_htw_req0_way_d; + wire [`TLB_WORD_WIDTH:`TLB_WAY_WIDTH-1] tlb_htw_req0_way_q; + wire tlb_htw_req0_tag_act; + wire tlb_htw_req1_valid_d; + wire tlb_htw_req1_valid_q; + wire tlb_htw_req1_pending_d; + wire tlb_htw_req1_pending_q; + wire [0:`TLB_TAG_WIDTH-1] tlb_htw_req1_tag_d; + wire [0:`TLB_TAG_WIDTH-1] tlb_htw_req1_tag_q; + wire [`TLB_WORD_WIDTH:`TLB_WAY_WIDTH-1] tlb_htw_req1_way_d; + wire [`TLB_WORD_WIDTH:`TLB_WAY_WIDTH-1] tlb_htw_req1_way_q; + wire tlb_htw_req1_tag_act; + wire tlb_htw_req2_valid_d; + wire tlb_htw_req2_valid_q; + wire tlb_htw_req2_pending_d; + wire tlb_htw_req2_pending_q; + wire [0:`TLB_TAG_WIDTH-1] tlb_htw_req2_tag_d; + wire [0:`TLB_TAG_WIDTH-1] tlb_htw_req2_tag_q; + wire [`TLB_WORD_WIDTH:`TLB_WAY_WIDTH-1] tlb_htw_req2_way_d; + wire [`TLB_WORD_WIDTH:`TLB_WAY_WIDTH-1] tlb_htw_req2_way_q; + wire tlb_htw_req2_tag_act; + wire tlb_htw_req3_valid_d; + wire tlb_htw_req3_valid_q; + wire tlb_htw_req3_pending_d; + wire tlb_htw_req3_pending_q; + wire [0:`TLB_TAG_WIDTH-1] tlb_htw_req3_tag_d; + wire [0:`TLB_TAG_WIDTH-1] tlb_htw_req3_tag_q; + wire [`TLB_WORD_WIDTH:`TLB_WAY_WIDTH-1] tlb_htw_req3_way_d; + wire [`TLB_WORD_WIDTH:`TLB_WAY_WIDTH-1] tlb_htw_req3_way_q; + wire tlb_htw_req3_tag_act; + // t minus 1 phase + wire [0:4] reld_core_tag_tm1_d; + wire [0:4] reld_core_tag_tm1_q; + wire [0:1] reld_qw_tm1_d; + wire [0:1] reld_qw_tm1_q; + wire reld_crit_qw_tm1_d; + wire reld_crit_qw_tm1_q; + wire reld_ditc_tm1_d; + wire reld_ditc_tm1_q; + wire reld_data_vld_tm1_d; + wire reld_data_vld_tm1_q; + // t phase + wire [0:4] reld_core_tag_t_d; + wire [0:4] reld_core_tag_t_q; + wire [0:1] reld_qw_t_d; + wire [0:1] reld_qw_t_q; + wire reld_crit_qw_t_d; + wire reld_crit_qw_t_q; + wire reld_ditc_t_d; + wire reld_ditc_t_q; + wire reld_data_vld_t_d; + wire reld_data_vld_t_q; + // t plus 1 phase + wire [0:4] reld_core_tag_tp1_d; + wire [0:4] reld_core_tag_tp1_q; + wire [0:1] reld_qw_tp1_d; + wire [0:1] reld_qw_tp1_q; + wire reld_crit_qw_tp1_d; + wire reld_crit_qw_tp1_q; + wire reld_ditc_tp1_d; + wire reld_ditc_tp1_q; + wire reld_data_vld_tp1_d; + wire reld_data_vld_tp1_q; + wire [0:127] reld_data_tp1_d; + wire [0:127] reld_data_tp1_q; + // t plus 2 phase + wire [0:4] reld_core_tag_tp2_d; + wire [0:4] reld_core_tag_tp2_q; + wire [0:1] reld_qw_tp2_d; + wire [0:1] reld_qw_tp2_q; + wire reld_crit_qw_tp2_d; + wire reld_crit_qw_tp2_q; + wire reld_ditc_tp2_d; + wire reld_ditc_tp2_q; + wire reld_data_vld_tp2_d; + wire reld_data_vld_tp2_q; + wire [0:127] reld_data_tp2_d; + wire [0:127] reld_data_tp2_q; + wire reld_ecc_err_tp2_d; + wire reld_ecc_err_tp2_q; + wire reld_ecc_err_ue_tp2_d; + wire reld_ecc_err_ue_tp2_q; + // t plus 3 phase + wire [0:63] pte0_reld_data_tp3_d; + wire [0:63] pte0_reld_data_tp3_q; + wire [0:63] pte1_reld_data_tp3_d; + wire [0:63] pte1_reld_data_tp3_q; + wire [0:`TLB_TAG_WIDTH-1] htw_tag3_d; + wire [0:`TLB_TAG_WIDTH-1] htw_tag3_q; + wire [0:`THDID_WIDTH-1] htw_tag3_clr_resv_term2; + wire [0:`THDID_WIDTH-1] htw_tag3_clr_resv_term4; + wire [0:`THDID_WIDTH-1] htw_tag3_clr_resv_term5; + wire [0:`THDID_WIDTH-1] htw_tag3_clr_resv_term6; + wire [0:`THDID_WIDTH-1] htw_tag3_clr_resv_term7; + wire [0:`THDID_WIDTH-1] htw_tag3_clr_resv_term8; + wire [0:`THDID_WIDTH-1] htw_tag3_clr_resv_term9; + wire [0:`THDID_WIDTH-1] htw_tag3_clr_resv_term11; + wire [0:`THDID_WIDTH-1] htw_tag4_clr_resv_d; + wire [0:`THDID_WIDTH-1] htw_tag4_clr_resv_q; + wire [0:`THDID_WIDTH-1] htw_tag5_clr_resv_d; + wire [0:`THDID_WIDTH-1] htw_tag5_clr_resv_q; + wire [0:15] spare_a_q; + wire [0:15] spare_b_q; + // logic signals + wire htw_seq_idle; + reg htw_seq_load_pteaddr; + wire [0:`THDID_WIDTH-1] htw_quiesce_b; + wire [0:`THDID_WIDTH-1] tlb_htw_req_valid_vec; + wire [0:`THDID_WIDTH-1] tlb_htw_req_valid_notpend_vec; + wire tlb_htw_pte_machines_full; + wire [0:1] htw_lsuptr_alt_d; + wire pte0_seq_idle; + reg pte0_reload_req_valid; + reg pte0_reload_req_taken; + wire pte0_reld_for_me_tm1; + wire pte0_reld_for_me_tp2; + reg pte0_reld_enable_lo_tp2; + reg pte0_reld_enable_hi_tp2; + reg pte0_seq_score_load; + reg pte0_seq_score_done; + reg pte0_seq_data_retry; + reg pte0_seq_clr_resv_ue; + wire pte1_seq_idle; + reg pte1_reload_req_valid; + reg pte1_reload_req_taken; + wire pte1_reld_for_me_tm1; + wire pte1_reld_for_me_tp2; + reg pte1_reld_enable_lo_tp2; + reg pte1_reld_enable_hi_tp2; + reg pte1_seq_score_load; + reg pte1_seq_score_done; + reg pte1_seq_data_retry; + reg pte1_seq_clr_resv_ue; + wire [64-`REAL_ADDR_WIDTH:63] pte_ra_0; + wire [64-`REAL_ADDR_WIDTH:63] pte_ra_0_spsize4K; + wire [64-`REAL_ADDR_WIDTH:63] pte_ra_0_spsize64K; + wire [64-`REAL_ADDR_WIDTH:63] pte_ra_1; + wire [64-`REAL_ADDR_WIDTH:63] pte_ra_1_spsize4K; + wire [64-`REAL_ADDR_WIDTH:63] pte_ra_1_spsize64K; + wire [64-`REAL_ADDR_WIDTH:63] pte_ra_2; + wire [64-`REAL_ADDR_WIDTH:63] pte_ra_2_spsize4K; + wire [64-`REAL_ADDR_WIDTH:63] pte_ra_2_spsize64K; + wire [64-`REAL_ADDR_WIDTH:63] pte_ra_3; + wire [64-`REAL_ADDR_WIDTH:63] pte_ra_3_spsize4K; + wire [64-`REAL_ADDR_WIDTH:63] pte_ra_3_spsize64K; + wire htw_resv0_tag3_lpid_match; + wire htw_resv0_tag3_pid_match; + wire htw_resv0_tag3_as_match; + wire htw_resv0_tag3_gs_match; + wire htw_resv0_tag3_epn_loc_match; + wire htw_resv0_tag3_epn_glob_match; + wire tlb_htw_req0_clr_resv_ue; + wire htw_resv1_tag3_lpid_match; + wire htw_resv1_tag3_pid_match; + wire htw_resv1_tag3_as_match; + wire htw_resv1_tag3_gs_match; + wire htw_resv1_tag3_epn_loc_match; + wire htw_resv1_tag3_epn_glob_match; + wire tlb_htw_req1_clr_resv_ue; + wire htw_resv2_tag3_lpid_match; + wire htw_resv2_tag3_pid_match; + wire htw_resv2_tag3_as_match; + wire htw_resv2_tag3_gs_match; + wire htw_resv2_tag3_epn_loc_match; + wire htw_resv2_tag3_epn_glob_match; + wire tlb_htw_req2_clr_resv_ue; + wire htw_resv3_tag3_lpid_match; + wire htw_resv3_tag3_pid_match; + wire htw_resv3_tag3_as_match; + wire htw_resv3_tag3_gs_match; + wire htw_resv3_tag3_epn_loc_match; + wire htw_resv3_tag3_epn_glob_match; + wire tlb_htw_req3_clr_resv_ue; + wire [0:`THDID_WIDTH-1] htw_resv_valid_vec; + wire [0:3] htw_tag4_clr_resv_terms; + wire htw_lsu_act; + wire pte0_score_act; + wire pte1_score_act; + wire reld_act; + wire pte0_reld_act; + wire pte1_reld_act; + (* analysis_not_referenced="true" *) + wire [0:21] unused_dc; + + // Pervasive + wire pc_sg_1; + wire pc_sg_0; + wire pc_func_sl_thold_1; + wire pc_func_sl_thold_0; + wire pc_func_sl_thold_0_b; + wire pc_func_slp_sl_thold_1; + wire pc_func_slp_sl_thold_0; + wire pc_func_slp_sl_thold_0_b; + wire pc_func_sl_force; + wire pc_func_slp_sl_force; + wire [0:scan_right_0] siv_0; + wire [0:scan_right_0] sov_0; + wire [0:scan_right_1] siv_1; + wire [0:scan_right_1] sov_1; + //@@ START OF EXECUTABLE CODE FOR MMQ_HTW + + //begin + //!! Bugspray Include: mmq_htw; + + //--------------------------------------------------------------------- + // Logic + //--------------------------------------------------------------------- + + // not quiesced + assign htw_quiesce_b[0:`THDID_WIDTH - 1] = ({`THDID_WIDTH{tlb_htw_req0_valid_q}} & tlb_htw_req0_tag_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) | + ({`THDID_WIDTH{tlb_htw_req1_valid_q}} & tlb_htw_req1_tag_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) | + ({`THDID_WIDTH{tlb_htw_req2_valid_q}} & tlb_htw_req2_tag_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) | + ({`THDID_WIDTH{tlb_htw_req3_valid_q}} & tlb_htw_req3_tag_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]); + assign htw_quiesce = (~htw_quiesce_b); + + assign tlb_htw_pte_machines_full = ((pte0_score_pending_q == 1'b1 & pte1_score_pending_q == 1'b1)) ? 1'b1 : + 1'b0; + + assign tlb_htw_req_valid_vec = { (tlb_htw_req0_valid_q & (pte0_score_pending_q == 1'b0 | pte0_score_ptr_q != 2'b00) & (pte1_score_pending_q == 1'b0 | pte1_score_ptr_q != 2'b00)), + (tlb_htw_req1_valid_q & (pte0_score_pending_q == 1'b0 | pte0_score_ptr_q != 2'b01) & (pte1_score_pending_q == 1'b0 | pte1_score_ptr_q != 2'b01)), + (tlb_htw_req2_valid_q & (pte0_score_pending_q == 1'b0 | pte0_score_ptr_q != 2'b10) & (pte1_score_pending_q == 1'b0 | pte1_score_ptr_q != 2'b10)), + (tlb_htw_req3_valid_q & (pte0_score_pending_q == 1'b0 | pte0_score_ptr_q != 2'b11) & (pte1_score_pending_q == 1'b0 | pte1_score_ptr_q != 2'b11)) }; + + + // HTW sequencer for servicing indirect tlb entry hits + always @(htw_seq_q or tlb_htw_req_valid_vec or tlb_htw_pte_machines_full or htw_lsu_req_taken) + begin: Htw_Sequencer + htw_seq_load_pteaddr = 1'b0; + htw_lsu_req_valid = 1'b0; + case (htw_seq_q) + HtwSeq_Idle : + if (tlb_htw_req_valid_vec != 4'b0000 & tlb_htw_pte_machines_full == 1'b0) + htw_seq_d = HtwSeq_Stg1; + else + htw_seq_d = HtwSeq_Idle; + HtwSeq_Stg1 : + begin + htw_seq_load_pteaddr = 1'b1; + htw_seq_d = HtwSeq_Stg2; + end + + HtwSeq_Stg2 : + begin + htw_lsu_req_valid = 1'b1; + if (htw_lsu_req_taken == 1'b1) + htw_seq_d = HtwSeq_Idle; + else + htw_seq_d = HtwSeq_Stg2; + end + + default : + htw_seq_d = HtwSeq_Idle; + + endcase + end + assign htw_seq_idle = (htw_seq_q == HtwSeq_Idle) ? 1'b1 : + 1'b0; + + // PTE sequencer for servicing pte data reloads + + always @(pte0_seq_q or pte_load_ptr_q or ptereload_ptr_q or htw_lsu_req_taken or ptereload_req_taken or pte0_score_pending_q or pte0_score_dataval_q or pte0_score_error_q or pte0_score_qwbeat_q or pte0_score_ibit_q) + begin: Pte0_Sequencer + pte0_reload_req_valid = 1'b0; + pte0_reload_req_taken = 1'b0; + pte0_seq_score_load = 1'b0; + pte0_seq_score_done = 1'b0; + pte0_seq_data_retry = 1'b0; + pte0_reld_enable_lo_tp2 = 1'b0; + pte0_reld_enable_hi_tp2 = 1'b0; + pte0_seq_clr_resv_ue = 1'b0; + case (pte0_seq_q) + PteSeq_Idle : + if (pte_load_ptr_q == 1'b0 & htw_lsu_req_taken == 1'b1) + begin + pte0_seq_score_load = 1'b1; + pte0_seq_d = PteSeq_Stg1; + end + else + pte0_seq_d = PteSeq_Idle; + PteSeq_Stg1 : + if (pte0_score_pending_q == 1'b1 & pte0_score_dataval_q == 1'b1) + pte0_seq_d = PteSeq_Stg2; + else + pte0_seq_d = PteSeq_Stg1; + + PteSeq_Stg2 : + if (pte0_score_error_q[1] == 1'b1 & (pte0_score_qwbeat_q == 4'b1111 | pte0_score_ibit_q == 1'b1)) + pte0_seq_d = PteSeq_Stg4; + else if (pte0_score_error_q == 3'b100 & (pte0_score_qwbeat_q == 4'b1111 | pte0_score_ibit_q == 1'b1)) + begin + pte0_seq_data_retry = 1'b1; + pte0_seq_d = PteSeq_Stg1; + end + else if (pte0_score_error_q[1] == 1'b0 & (pte0_score_qwbeat_q == 4'b1111 | pte0_score_ibit_q == 1'b1)) + pte0_seq_d = PteSeq_Stg3; + else + pte0_seq_d = PteSeq_Stg2; + + PteSeq_Stg3 : + begin + pte0_reload_req_valid = 1'b1; + if (ptereload_ptr_q == 1'b0 & ptereload_req_taken == 1'b1) + begin + pte0_seq_score_done = 1'b1; + pte0_reload_req_taken = 1'b1; + pte0_seq_d = PteSeq_Idle; + end + else + pte0_seq_d = PteSeq_Stg3; + end + + PteSeq_Stg4 : + begin + pte0_seq_clr_resv_ue = 1'b1; + pte0_seq_d = PteSeq_Stg5; + end + + PteSeq_Stg5 : + begin + pte0_reload_req_valid = 1'b1; + if (ptereload_ptr_q == 1'b0 & ptereload_req_taken == 1'b1) + begin + pte0_seq_score_done = 1'b1; + pte0_reload_req_taken = 1'b1; + pte0_seq_d = PteSeq_Idle; + end + else + pte0_seq_d = PteSeq_Stg5; + end + + default : + pte0_seq_d = PteSeq_Idle; + + endcase + end + assign pte0_seq_idle = (pte0_seq_q == PteSeq_Idle) ? 1'b1 : + 1'b0; + // PTE sequencer for servicing pte data reloads + + always @(pte1_seq_q or pte_load_ptr_q or ptereload_ptr_q or htw_lsu_req_taken or ptereload_req_taken or pte1_score_pending_q or pte1_score_dataval_q or pte1_score_error_q or pte1_score_qwbeat_q or pte1_score_ibit_q) + begin: Pte1_Sequencer + pte1_reload_req_valid = 1'b0; + pte1_reload_req_taken = 1'b0; + pte1_seq_score_load = 1'b0; + pte1_seq_score_done = 1'b0; + pte1_seq_data_retry = 1'b0; + pte1_reld_enable_lo_tp2 = 1'b0; + pte1_reld_enable_hi_tp2 = 1'b0; + pte1_seq_clr_resv_ue = 1'b0; + case (pte1_seq_q) + PteSeq_Idle : + if (pte_load_ptr_q == 1'b1 & htw_lsu_req_taken == 1'b1) + begin + pte1_seq_score_load = 1'b1; + pte1_seq_d = PteSeq_Stg1; + end + else + pte1_seq_d = PteSeq_Idle; + PteSeq_Stg1 : + if (pte1_score_pending_q == 1'b1 & pte1_score_dataval_q == 1'b1) + pte1_seq_d = PteSeq_Stg2; + else + pte1_seq_d = PteSeq_Stg1; + + PteSeq_Stg2 : + if (pte1_score_error_q[1] == 1'b1 & (pte1_score_qwbeat_q == 4'b1111 | pte1_score_ibit_q == 1'b1)) + pte1_seq_d = PteSeq_Stg4; + else if (pte1_score_error_q == 3'b100 & (pte1_score_qwbeat_q == 4'b1111 | pte1_score_ibit_q == 1'b1)) + begin + pte1_seq_data_retry = 1'b1; + pte1_seq_d = PteSeq_Stg1; + end + else if (pte1_score_error_q[1] == 1'b0 & (pte1_score_qwbeat_q == 4'b1111 | pte1_score_ibit_q == 1'b1)) + pte1_seq_d = PteSeq_Stg3; + else + pte1_seq_d = PteSeq_Stg2; + + PteSeq_Stg3 : + begin + pte1_reload_req_valid = 1'b1; + if (ptereload_ptr_q == 1'b1 & ptereload_req_taken == 1'b1) + begin + pte1_seq_score_done = 1'b1; + pte1_reload_req_taken = 1'b1; + pte1_seq_d = PteSeq_Idle; + end + else + pte1_seq_d = PteSeq_Stg3; + end + + PteSeq_Stg4 : + begin + pte1_seq_clr_resv_ue = 1'b1; + pte1_seq_d = PteSeq_Stg5; + end + + PteSeq_Stg5 : + begin + pte1_reload_req_valid = 1'b1; + if (ptereload_ptr_q == 1'b1 & ptereload_req_taken == 1'b1) + begin + pte1_seq_score_done = 1'b1; + pte1_reload_req_taken = 1'b1; + pte1_seq_d = PteSeq_Idle; + end + else + pte1_seq_d = PteSeq_Stg5; + end + + default : + pte1_seq_d = PteSeq_Idle; + + endcase + end + assign pte1_seq_idle = (pte1_seq_q == PteSeq_Idle) ? 1'b1 : + 1'b0; + // tlb_way IND=0 IND=1 + // 134 UX SPSIZE0 + // 135 SX SPSIZE1 + // 136 UW SPSIZE2 + // 137 SW SPSIZE3 + // 138 UR PTRPN + // 139 SR PA52 + assign tlb_htw_req0_valid_d = ((tlb_htw_req_valid == 1'b1 & tlb_htw_req0_valid_q == 1'b0 & htw_inptr_q == 2'b00)) ? 1'b1 : + ((pte0_reload_req_taken == 1'b1 & tlb_htw_req0_valid_q == 1'b1 & pte0_score_ptr_q == 2'b00)) ? 1'b0 : + ((pte1_reload_req_taken == 1'b1 & tlb_htw_req0_valid_q == 1'b1 & pte1_score_ptr_q == 2'b00)) ? 1'b0 : + tlb_htw_req0_valid_q; + assign tlb_htw_req0_pending_d = ((htw_lsu_req_taken == 1'b1 & tlb_htw_req0_pending_q == 1'b0 & htw_lsuptr_q == 2'b00)) ? 1'b1 : + ((pte0_reload_req_taken == 1'b1 & tlb_htw_req0_pending_q == 1'b1 & pte0_score_ptr_q == 2'b00)) ? 1'b0 : + ((pte1_reload_req_taken == 1'b1 & tlb_htw_req0_pending_q == 1'b1 & pte1_score_ptr_q == 2'b00)) ? 1'b0 : + tlb_htw_req0_pending_q; + // the rpn part of the tlb way + assign tlb_htw_req0_way_d = ((tlb_htw_req_valid == 1'b1 & tlb_htw_req0_valid_q == 1'b0 & htw_inptr_q == 2'b00)) ? tlb_htw_req_way : + tlb_htw_req0_way_q; + assign tlb_htw_req0_tag_d[0:`tagpos_wq - 1] = ((tlb_htw_req_valid == 1'b1 & tlb_htw_req0_valid_q == 1'b0 & htw_inptr_q == 2'b00)) ? tlb_htw_req_tag[0:`tagpos_wq - 1] : + tlb_htw_req0_tag_q[0:`tagpos_wq - 1]; + assign tlb_htw_req0_tag_d[`tagpos_wq + 2:`TLB_TAG_WIDTH - 1] = ((tlb_htw_req_valid == 1'b1 & tlb_htw_req0_valid_q == 1'b0 & htw_inptr_q == 2'b00)) ? tlb_htw_req_tag[`tagpos_wq + 2:`TLB_TAG_WIDTH - 1] : + tlb_htw_req0_tag_q[`tagpos_wq + 2:`TLB_TAG_WIDTH - 1]; + // the WQ bits of the tag are re-purposed as reservation valid and duplicate bits + // set reservation valid at tlb handoff, clear when ptereload taken.. + // or, clear reservation if tlbwe,ptereload,tlbi from another thread to avoid duplicates + // or, clear reservation when L2 UE for this reload + assign tlb_htw_req0_tag_d[`tagpos_wq] = (((htw_tag5_clr_resv_q[0] == 1'b1 & |(tlb_tag5_except) == 1'b0) | tlb_htw_req0_clr_resv_ue == 1'b1)) ? 1'b0 : + ((tlb_htw_req_valid == 1'b1 & tlb_htw_req0_valid_q == 1'b0 & htw_inptr_q == 2'b00)) ? 1'b1 : + ((pte0_reload_req_taken == 1'b1 & tlb_htw_req0_valid_q == 1'b1 & pte0_score_ptr_q == 2'b00)) ? 1'b0 : + ((pte1_reload_req_taken == 1'b1 & tlb_htw_req0_valid_q == 1'b1 & pte1_score_ptr_q == 2'b00)) ? 1'b0 : + tlb_htw_req0_tag_q[`tagpos_wq]; + // spare, wq+1 is duplicate indicator in tlb_cmp, but would not make it to tlb handoff + assign tlb_htw_req0_tag_d[`tagpos_wq + 1] = tlb_htw_req0_tag_q[`tagpos_wq + 1]; + assign tlb_htw_req0_tag_act = tlb_delayed_act[24 + 0] | tlb_htw_req0_valid_q; + + assign tlb_htw_req0_clr_resv_ue = {(pte0_seq_clr_resv_ue & (pte0_score_ptr_q == 2'b00)) | (pte1_seq_clr_resv_ue & (pte1_score_ptr_q == 2'b00))}; + + assign htw_req0_valid = tlb_htw_req0_valid_q; + assign htw_req0_thdid = tlb_htw_req0_tag_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]; + assign htw_req0_type = tlb_htw_req0_tag_q[`tagpos_type_derat:`tagpos_type_ierat]; + // FIX THESE!!!!!! for 32bit generates into smaller RA's + assign pte_ra_0_spsize4K = {tlb_htw_req0_way_q[`waypos_rpn:`waypos_rpn + `RPN_WIDTH - 1], tlb_htw_req0_way_q[`waypos_usxwr + 5], tlb_htw_req0_tag_q[`tagpos_epn + `EPN_WIDTH - 8:`tagpos_epn + `EPN_WIDTH - 1], 3'b000}; + assign pte_ra_0_spsize64K = {tlb_htw_req0_way_q[`waypos_rpn:`waypos_rpn + `RPN_WIDTH - 4], tlb_htw_req0_tag_q[`tagpos_epn + `EPN_WIDTH - 16:`tagpos_epn + `EPN_WIDTH - 5], 3'b000}; + // select based on SPSIZE + assign pte_ra_0 = (tlb_htw_req0_way_q[`waypos_usxwr:`waypos_usxwr + 3] == TLB_PgSize_64KB) ? pte_ra_0_spsize64K : + pte_ra_0_spsize4K; + assign tlb_htw_req1_valid_d = ((tlb_htw_req_valid == 1'b1 & tlb_htw_req1_valid_q == 1'b0 & htw_inptr_q == 2'b01)) ? 1'b1 : + ((pte0_reload_req_taken == 1'b1 & tlb_htw_req1_valid_q == 1'b1 & pte0_score_ptr_q == 2'b01)) ? 1'b0 : + ((pte1_reload_req_taken == 1'b1 & tlb_htw_req1_valid_q == 1'b1 & pte1_score_ptr_q == 2'b01)) ? 1'b0 : + tlb_htw_req1_valid_q; + assign tlb_htw_req1_pending_d = ((htw_lsu_req_taken == 1'b1 & tlb_htw_req1_pending_q == 1'b0 & htw_lsuptr_q == 2'b01)) ? 1'b1 : + ((pte0_reload_req_taken == 1'b1 & tlb_htw_req1_pending_q == 1'b1 & pte0_score_ptr_q == 2'b01)) ? 1'b0 : + ((pte1_reload_req_taken == 1'b1 & tlb_htw_req1_pending_q == 1'b1 & pte1_score_ptr_q == 2'b01)) ? 1'b0 : + tlb_htw_req1_pending_q; + // the rpn part of the tlb way + assign tlb_htw_req1_way_d = ((tlb_htw_req_valid == 1'b1 & tlb_htw_req1_valid_q == 1'b0 & htw_inptr_q == 2'b01)) ? tlb_htw_req_way : + tlb_htw_req1_way_q; + assign tlb_htw_req1_tag_d[0:`tagpos_wq - 1] = ((tlb_htw_req_valid == 1'b1 & tlb_htw_req1_valid_q == 1'b0 & htw_inptr_q == 2'b01)) ? tlb_htw_req_tag[0:`tagpos_wq - 1] : + tlb_htw_req1_tag_q[0:`tagpos_wq - 1]; + assign tlb_htw_req1_tag_d[`tagpos_wq + 2:`TLB_TAG_WIDTH - 1] = ((tlb_htw_req_valid == 1'b1 & tlb_htw_req1_valid_q == 1'b0 & htw_inptr_q == 2'b01)) ? tlb_htw_req_tag[`tagpos_wq + 2:`TLB_TAG_WIDTH - 1] : + tlb_htw_req1_tag_q[`tagpos_wq + 2:`TLB_TAG_WIDTH - 1]; + // the WQ bits of the tag are re-purposed as reservation valid and duplicate bits + // set reservation valid at tlb handoff, clear when ptereload taken.. + // or, clear reservation if tlbwe,ptereload,tlbi from another thread to avoid duplicates + // or, clear reservation when L2 UE for this reload + assign tlb_htw_req1_tag_d[`tagpos_wq] = (((htw_tag5_clr_resv_q[1] == 1'b1 & |(tlb_tag5_except) == 1'b0) | tlb_htw_req1_clr_resv_ue == 1'b1)) ? 1'b0 : + ((tlb_htw_req_valid == 1'b1 & tlb_htw_req1_valid_q == 1'b0 & htw_inptr_q == 2'b01)) ? 1'b1 : + ((pte0_reload_req_taken == 1'b1 & tlb_htw_req1_valid_q == 1'b1 & pte0_score_ptr_q == 2'b01)) ? 1'b0 : + ((pte1_reload_req_taken == 1'b1 & tlb_htw_req1_valid_q == 1'b1 & pte1_score_ptr_q == 2'b01)) ? 1'b0 : + tlb_htw_req1_tag_q[`tagpos_wq]; + // spare, wq+1 is duplicate indicator in tlb_cmp, but would not make it to tlb handoff + assign tlb_htw_req1_tag_d[`tagpos_wq + 1] = tlb_htw_req1_tag_q[`tagpos_wq + 1]; + assign tlb_htw_req1_tag_act = tlb_delayed_act[24 + 1] | tlb_htw_req1_valid_q; + assign tlb_htw_req1_clr_resv_ue = {(pte0_seq_clr_resv_ue & (pte0_score_ptr_q == 2'b01)) | (pte1_seq_clr_resv_ue & (pte1_score_ptr_q == 2'b01))}; + assign htw_req1_valid = tlb_htw_req1_valid_q; + assign htw_req1_thdid = tlb_htw_req1_tag_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]; + assign htw_req1_type = tlb_htw_req1_tag_q[`tagpos_type_derat:`tagpos_type_ierat]; + // FIX THESE!!!!!! for 32bit generates into smaller RA's + assign pte_ra_1_spsize4K = {tlb_htw_req1_way_q[`waypos_rpn:`waypos_rpn + `RPN_WIDTH - 1], tlb_htw_req1_way_q[`waypos_usxwr + 5], tlb_htw_req1_tag_q[`tagpos_epn + `EPN_WIDTH - 8:`tagpos_epn + `EPN_WIDTH - 1], 3'b000}; + assign pte_ra_1_spsize64K = {tlb_htw_req1_way_q[`waypos_rpn:`waypos_rpn + `RPN_WIDTH - 4], tlb_htw_req1_tag_q[`tagpos_epn + `EPN_WIDTH - 16:`tagpos_epn + `EPN_WIDTH - 5], 3'b000}; + // select based on SPSIZE + assign pte_ra_1 = (tlb_htw_req1_way_q[`waypos_usxwr:`waypos_usxwr + 3] == TLB_PgSize_64KB) ? pte_ra_1_spsize64K : + pte_ra_1_spsize4K; + assign tlb_htw_req2_valid_d = ((tlb_htw_req_valid == 1'b1 & tlb_htw_req2_valid_q == 1'b0 & htw_inptr_q == 2'b10)) ? 1'b1 : + ((pte0_reload_req_taken == 1'b1 & tlb_htw_req2_valid_q == 1'b1 & pte0_score_ptr_q == 2'b10)) ? 1'b0 : + ((pte1_reload_req_taken == 1'b1 & tlb_htw_req2_valid_q == 1'b1 & pte1_score_ptr_q == 2'b10)) ? 1'b0 : + tlb_htw_req2_valid_q; + assign tlb_htw_req2_pending_d = ((htw_lsu_req_taken == 1'b1 & tlb_htw_req2_pending_q == 1'b0 & htw_lsuptr_q == 2'b10)) ? 1'b1 : + ((pte0_reload_req_taken == 1'b1 & tlb_htw_req2_pending_q == 1'b1 & pte0_score_ptr_q == 2'b10)) ? 1'b0 : + ((pte1_reload_req_taken == 1'b1 & tlb_htw_req2_pending_q == 1'b1 & pte1_score_ptr_q == 2'b10)) ? 1'b0 : + tlb_htw_req2_pending_q; + // the rpn part of the tlb way + assign tlb_htw_req2_way_d = ((tlb_htw_req_valid == 1'b1 & tlb_htw_req2_valid_q == 1'b0 & htw_inptr_q == 2'b10)) ? tlb_htw_req_way : + tlb_htw_req2_way_q; + assign tlb_htw_req2_tag_d[0:`tagpos_wq - 1] = ((tlb_htw_req_valid == 1'b1 & tlb_htw_req2_valid_q == 1'b0 & htw_inptr_q == 2'b10)) ? tlb_htw_req_tag[0:`tagpos_wq - 1] : + tlb_htw_req2_tag_q[0:`tagpos_wq - 1]; + assign tlb_htw_req2_tag_d[`tagpos_wq + 2:`TLB_TAG_WIDTH - 1] = ((tlb_htw_req_valid == 1'b1 & tlb_htw_req2_valid_q == 1'b0 & htw_inptr_q == 2'b10)) ? tlb_htw_req_tag[`tagpos_wq + 2:`TLB_TAG_WIDTH - 1] : + tlb_htw_req2_tag_q[`tagpos_wq + 2:`TLB_TAG_WIDTH - 1]; + // the WQ bits of the tag are re-purposed as reservation valid and duplicate bits + // set reservation valid at tlb handoff, clear when ptereload taken.. + // or, clear reservation if tlbwe,ptereload,tlbi from another thread to avoid duplicates + // or, clear reservation when L2 UE for this reload + assign tlb_htw_req2_tag_d[`tagpos_wq] = (((htw_tag5_clr_resv_q[2] == 1'b1 & |(tlb_tag5_except) == 1'b0) | tlb_htw_req2_clr_resv_ue == 1'b1)) ? 1'b0 : + ((tlb_htw_req_valid == 1'b1 & tlb_htw_req2_valid_q == 1'b0 & htw_inptr_q == 2'b10)) ? 1'b1 : + ((pte0_reload_req_taken == 1'b1 & tlb_htw_req2_valid_q == 1'b1 & pte0_score_ptr_q == 2'b10)) ? 1'b0 : + ((pte1_reload_req_taken == 1'b1 & tlb_htw_req2_valid_q == 1'b1 & pte1_score_ptr_q == 2'b10)) ? 1'b0 : + tlb_htw_req2_tag_q[`tagpos_wq]; + // spare, wq+1 is duplicate indicator in tlb_cmp, but would not make it to tlb handoff + assign tlb_htw_req2_tag_d[`tagpos_wq + 1] = tlb_htw_req2_tag_q[`tagpos_wq + 1]; + assign tlb_htw_req2_tag_act = tlb_delayed_act[24 + 2] | tlb_htw_req2_valid_q; + assign tlb_htw_req2_clr_resv_ue = {(pte0_seq_clr_resv_ue & (pte0_score_ptr_q == 2'b10)) | (pte1_seq_clr_resv_ue & (pte1_score_ptr_q == 2'b10))}; + assign htw_req2_valid = tlb_htw_req2_valid_q; + assign htw_req2_thdid = tlb_htw_req2_tag_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]; + assign htw_req2_type = tlb_htw_req2_tag_q[`tagpos_type_derat:`tagpos_type_ierat]; + // FIX THESE!!!!!! for 32bit generates into smaller RA's + assign pte_ra_2_spsize4K = {tlb_htw_req2_way_q[`waypos_rpn:`waypos_rpn + `RPN_WIDTH - 1], tlb_htw_req2_way_q[`waypos_usxwr + 5], tlb_htw_req2_tag_q[`tagpos_epn + `EPN_WIDTH - 8:`tagpos_epn + `EPN_WIDTH - 1], 3'b000}; + assign pte_ra_2_spsize64K = {tlb_htw_req2_way_q[`waypos_rpn:`waypos_rpn + `RPN_WIDTH - 4], tlb_htw_req2_tag_q[`tagpos_epn + `EPN_WIDTH - 16:`tagpos_epn + `EPN_WIDTH - 5], 3'b000}; + // select based on SPSIZE + assign pte_ra_2 = (tlb_htw_req2_way_q[`waypos_usxwr:`waypos_usxwr + 3] == TLB_PgSize_64KB) ? pte_ra_2_spsize64K : + pte_ra_2_spsize4K; + assign tlb_htw_req3_valid_d = ((tlb_htw_req_valid == 1'b1 & tlb_htw_req3_valid_q == 1'b0 & htw_inptr_q == 2'b11)) ? 1'b1 : + ((pte0_reload_req_taken == 1'b1 & tlb_htw_req3_valid_q == 1'b1 & pte0_score_ptr_q == 2'b11)) ? 1'b0 : + ((pte1_reload_req_taken == 1'b1 & tlb_htw_req3_valid_q == 1'b1 & pte1_score_ptr_q == 2'b11)) ? 1'b0 : + tlb_htw_req3_valid_q; + assign tlb_htw_req3_pending_d = ((htw_lsu_req_taken == 1'b1 & tlb_htw_req3_pending_q == 1'b0 & htw_lsuptr_q == 2'b11)) ? 1'b1 : + ((pte0_reload_req_taken == 1'b1 & tlb_htw_req3_pending_q == 1'b1 & pte0_score_ptr_q == 2'b11)) ? 1'b0 : + ((pte1_reload_req_taken == 1'b1 & tlb_htw_req3_pending_q == 1'b1 & pte1_score_ptr_q == 2'b11)) ? 1'b0 : + tlb_htw_req3_pending_q; + // the rpn part of the tlb way + assign tlb_htw_req3_way_d = ((tlb_htw_req_valid == 1'b1 & tlb_htw_req3_valid_q == 1'b0 & htw_inptr_q == 2'b11)) ? tlb_htw_req_way : + tlb_htw_req3_way_q; + assign tlb_htw_req3_tag_d[0:`tagpos_wq - 1] = ((tlb_htw_req_valid == 1'b1 & tlb_htw_req3_valid_q == 1'b0 & htw_inptr_q == 2'b11)) ? tlb_htw_req_tag[0:`tagpos_wq - 1] : + tlb_htw_req3_tag_q[0:`tagpos_wq - 1]; + assign tlb_htw_req3_tag_d[`tagpos_wq + 2:`TLB_TAG_WIDTH - 1] = ((tlb_htw_req_valid == 1'b1 & tlb_htw_req3_valid_q == 1'b0 & htw_inptr_q == 2'b11)) ? tlb_htw_req_tag[`tagpos_wq + 2:`TLB_TAG_WIDTH - 1] : + tlb_htw_req3_tag_q[`tagpos_wq + 2:`TLB_TAG_WIDTH - 1]; + // the WQ bits of the tag are re-purposed as reservation valid and duplicate bits + // set reservation valid at tlb handoff, clear when ptereload taken.. + // or, clear reservation if tlbwe,ptereload,tlbi from another thread to avoid duplicates + // or, clear reservation when L2 UE for this reload + assign tlb_htw_req3_tag_d[`tagpos_wq] = (((htw_tag5_clr_resv_q[3] == 1'b1 & |(tlb_tag5_except) == 1'b0) | tlb_htw_req3_clr_resv_ue == 1'b1)) ? 1'b0 : + ((tlb_htw_req_valid == 1'b1 & tlb_htw_req3_valid_q == 1'b0 & htw_inptr_q == 2'b11)) ? 1'b1 : + ((pte0_reload_req_taken == 1'b1 & tlb_htw_req3_valid_q == 1'b1 & pte0_score_ptr_q == 2'b11)) ? 1'b0 : + ((pte1_reload_req_taken == 1'b1 & tlb_htw_req3_valid_q == 1'b1 & pte1_score_ptr_q == 2'b11)) ? 1'b0 : + tlb_htw_req3_tag_q[`tagpos_wq]; + // spare, wq+1 is duplicate indicator in tlb_cmp, but would not make it to tlb handoff + assign tlb_htw_req3_tag_d[`tagpos_wq + 1] = tlb_htw_req3_tag_q[`tagpos_wq + 1]; + assign tlb_htw_req3_tag_act = tlb_delayed_act[24 + 3] | tlb_htw_req3_valid_q; + assign tlb_htw_req3_clr_resv_ue = {(pte0_seq_clr_resv_ue & (pte0_score_ptr_q == 2'b11)) | (pte1_seq_clr_resv_ue & (pte1_score_ptr_q == 2'b11))}; + assign htw_req3_valid = tlb_htw_req3_valid_q; + assign htw_req3_thdid = tlb_htw_req3_tag_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]; + assign htw_req3_type = tlb_htw_req3_tag_q[`tagpos_type_derat:`tagpos_type_ierat]; + + // FIX THESE!!!!!! for 32bit generates into smaller RA's + assign pte_ra_3_spsize4K = {tlb_htw_req3_way_q[`waypos_rpn:`waypos_rpn + `RPN_WIDTH - 1], tlb_htw_req3_way_q[`waypos_usxwr + 5], tlb_htw_req3_tag_q[`tagpos_epn + `EPN_WIDTH - 8:`tagpos_epn + `EPN_WIDTH - 1], 3'b000}; + assign pte_ra_3_spsize64K = {tlb_htw_req3_way_q[`waypos_rpn:`waypos_rpn + `RPN_WIDTH - 4], tlb_htw_req3_tag_q[`tagpos_epn + `EPN_WIDTH - 16:`tagpos_epn + `EPN_WIDTH - 5], 3'b000}; + // select based on SPSIZE + assign pte_ra_3 = (tlb_htw_req3_way_q[`waypos_usxwr:`waypos_usxwr + 3] == TLB_PgSize_64KB) ? pte_ra_3_spsize64K : + pte_ra_3_spsize4K; + // tag forwarding from tlb_ctl, for reservation clear compares + assign htw_tag3_d[0:`tagpos_thdid - 1] = tlb_tag2[0:`tagpos_thdid - 1]; + assign htw_tag3_d[`tagpos_thdid + `THDID_WIDTH:`TLB_TAG_WIDTH - 1] = tlb_tag2[`tagpos_thdid + `THDID_WIDTH:`TLB_TAG_WIDTH - 1]; + assign htw_tag3_d[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] = tlb_tag2[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] & (~(tlb_ctl_tag2_flush)); + + generate + if (`THDID_WIDTH > `MM_THREADS) + begin : htwtag3NExist + assign htw_tag3_d[`tagpos_thdid + `MM_THREADS:`tagpos_thdid + `THDID_WIDTH - 1] = tlb_tag2[`tagpos_thdid + `MM_THREADS:`tagpos_thdid + `THDID_WIDTH - 1]; + end + endgenerate + + // reservation clear: + // (1) proc holding resv executes another tlbsrx. overwriting the old resv + // (2) any tlbivax snoop with gs,as,lpid,pid,sizemasked(epn,mas6.isize) matching resv.gs,as,lpid,pid,sizemasked(epn,mas6.isize) + // (note ind bit is not part of tlbivax criteria!!) + // (3) any proc sets mmucsr0.TLB0_FI=1 with lpidr matching resv.lpid + // (4) any proc executes tlbilx T=0 (all) with mas5.slpid matching resv.lpid + // (5) any proc executes tlbilx T=1 (pid) with mas5.slpid and mas6.spid matching resv.lpid,pid + // (6) any proc executes tlbilx T=3 (vpn) with mas gs,as,slpid,spid,sizemasked(epn,mas6.isize) matching + // resv.gs,as,lpid,pid,sizemasked(epn,mas6.isize) + // (note ind bit is not part of tlbilx criteria!!) + // (7) any proc executes tlbwe not causing exception and with (wq=00 always, or wq=01 and proc holds resv) + // and mas regs ind,tgs,ts,tlpid,tid,sizemasked(epn,mas1.tsize) match resv.ind,gs,as,lpid,pid,sizemasked(epn,mas1.tsize) + // (8) any page table reload not causing an exception (due to pt fault, tlb inelig, or lrat miss) + // and PTE's tag ind=0,tgs,ts,tlpid,tid,sizemasked(epn,pte.size) match resv.ind=0,gs,as,lpid,pid,sizemasked(epn.pte.size) + // A2-specific non-architected clear states + // (9) any proc executes tlbwe not causing exception and with (wq=10 clear, or wq=11 always (same as 00)) + // and mas regs ind,tgs,ts,tlpid,tid,sizemasked(epn,mas1.tsize) match resv.ind,gs,as,lpid,pid,sizemasked(epn,mas1.tsize) + // (basically same as 7, + // (10) any proc executes tlbilx T=2 (gs) with mas5.sgs matching resv.gs + // (11) any proc executes tlbilx T=4 to 7 (class) with T(1:2) matching resv.class + // ttype <= tlbre & tlbwe & tlbsx & tlbsxr & tlbsrx; + // IS0: Local bit + // IS1/Class: 0=all, 1=tid, 2=gs, 3=vpn, 4=class0, 5=class1, 6=class2, 7=class3 + // mas0.wq: 00=ignore reserv write always, 01=write if reserved, 10=clear reserv, 11=same as 00 + assign htw_tag3_clr_resv_term2[0] = ((|(htw_tag3_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & htw_tag3_q[`tagpos_type_snoop] == 1'b1 & htw_tag3_q[`tagpos_is:`tagpos_is + 3] == 4'b0011 & + htw_resv0_tag3_lpid_match == 1'b1 & htw_resv0_tag3_pid_match == 1'b1 & htw_resv0_tag3_gs_match == 1'b1 & + htw_resv0_tag3_as_match == 1'b1 & htw_resv0_tag3_epn_glob_match == 1'b1)) ? 1'b1 : + 1'b0; + assign htw_tag3_clr_resv_term4[0] = ((|(htw_tag3_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & htw_tag3_q[`tagpos_type_snoop] == 1'b1 & htw_tag3_q[`tagpos_is:`tagpos_is + 3] == 4'b1000 & + htw_resv0_tag3_lpid_match == 1'b1)) ? 1'b1 : + 1'b0; + assign htw_tag3_clr_resv_term5[0] = ((|(htw_tag3_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & htw_tag3_q[`tagpos_type_snoop] == 1'b1 & htw_tag3_q[`tagpos_is:`tagpos_is + 3] == 4'b1001 & + htw_resv0_tag3_lpid_match == 1'b1 & htw_resv0_tag3_pid_match == 1'b1)) ? 1'b1 : + 1'b0; + assign htw_tag3_clr_resv_term6[0] = ((|(htw_tag3_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & htw_tag3_q[`tagpos_type_snoop] == 1'b1 & htw_tag3_q[`tagpos_is:`tagpos_is + 3] == 4'b1011 & + htw_resv0_tag3_lpid_match == 1'b1 & htw_resv0_tag3_pid_match == 1'b1 & htw_resv0_tag3_gs_match == 1'b1 & + htw_resv0_tag3_as_match == 1'b1 & htw_resv0_tag3_epn_loc_match == 1'b1)) ? 1'b1 : + 1'b0; + assign htw_tag3_clr_resv_term7[0] = ((((|(htw_tag3_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] & (~(tlb_ctl_tag3_flush))) == 1'b1 & htw_tag3_q[`tagpos_wq:`tagpos_wq + 1] == 2'b01) | + (|(htw_tag3_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] & (~(tlb_ctl_tag3_flush))) == 1'b1 & htw_tag3_q[`tagpos_wq:`tagpos_wq + 1] == 2'b00)) & + htw_tag3_q[`tagpos_type_tlbwe] == 1'b1 & htw_resv0_tag3_gs_match == 1'b1 & htw_resv0_tag3_as_match == 1'b1 & + htw_resv0_tag3_lpid_match == 1'b1 & htw_resv0_tag3_pid_match == 1'b1 & htw_resv0_tag3_epn_loc_match == 1'b1)) ? 1'b1 : + 1'b0; + assign htw_tag3_clr_resv_term8[0] = ((|(htw_tag3_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & htw_tag3_q[`tagpos_type_ptereload] == 1'b1 & htw_tag3_q[`tagpos_wq:`tagpos_wq + 1] == 2'b10 & + htw_resv0_tag3_gs_match == 1'b1 & htw_resv0_tag3_as_match == 1'b1 & htw_resv0_tag3_lpid_match == 1'b1 & + htw_resv0_tag3_pid_match == 1'b1 & htw_resv0_tag3_epn_loc_match == 1'b1)) ? 1'b1 : + 1'b0; + assign htw_tag3_clr_resv_term9[0] = ((((|(htw_tag3_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS -1] & (~(tlb_ctl_tag3_flush))) == 1'b1 & htw_tag3_q[`tagpos_wq:`tagpos_wq + 1] == 2'b10) | + (|(htw_tag3_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] & (~(tlb_ctl_tag3_flush))) == 1'b1 & htw_tag3_q[`tagpos_wq:`tagpos_wq + 1] == 2'b11)) & + htw_tag3_q[`tagpos_type_tlbwe] == 1'b1 & htw_resv0_tag3_gs_match == 1'b1 & htw_resv0_tag3_as_match == 1'b1 & + htw_resv0_tag3_lpid_match == 1'b1 & htw_resv0_tag3_pid_match == 1'b1 & htw_resv0_tag3_epn_loc_match == 1'b1)) ? 1'b1 : + 1'b0; + assign htw_tag3_clr_resv_term11[0] = ((|(htw_tag3_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & htw_tag3_q[`tagpos_type_snoop] == 1'b1 & htw_tag3_q[`tagpos_is:`tagpos_is + 1] == 2'b11)) ? 1'b1 : + 1'b0; + assign htw_tag4_clr_resv_d[0] = htw_tag3_clr_resv_term2[0] | htw_tag3_clr_resv_term4[0] | htw_tag3_clr_resv_term5[0] | htw_tag3_clr_resv_term6[0] | + htw_tag3_clr_resv_term7[0] | htw_tag3_clr_resv_term8[0] | htw_tag3_clr_resv_term9[0] | htw_tag3_clr_resv_term11[0]; + + + assign htw_tag3_clr_resv_term2[1] = ((|(htw_tag3_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & htw_tag3_q[`tagpos_type_snoop] == 1'b1 & htw_tag3_q[`tagpos_is:`tagpos_is + 3] == 4'b0011 & + htw_resv1_tag3_lpid_match == 1'b1 & htw_resv1_tag3_pid_match == 1'b1 & htw_resv1_tag3_gs_match == 1'b1 & + htw_resv1_tag3_as_match == 1'b1 & htw_resv1_tag3_epn_glob_match == 1'b1)) ? 1'b1 : + 1'b0; + assign htw_tag3_clr_resv_term4[1] = ((|(htw_tag3_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & htw_tag3_q[`tagpos_type_snoop] == 1'b1 & htw_tag3_q[`tagpos_is:`tagpos_is + 3] == 4'b1000 & + htw_resv1_tag3_lpid_match == 1'b1)) ? 1'b1 : + 1'b0; + assign htw_tag3_clr_resv_term5[1] = ((|(htw_tag3_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & htw_tag3_q[`tagpos_type_snoop] == 1'b1 & htw_tag3_q[`tagpos_is:`tagpos_is + 3] == 4'b1001 & + htw_resv1_tag3_lpid_match == 1'b1 & htw_resv1_tag3_pid_match == 1'b1)) ? 1'b1 : + 1'b0; + assign htw_tag3_clr_resv_term6[1] = ((|(htw_tag3_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & htw_tag3_q[`tagpos_type_snoop] == 1'b1 & htw_tag3_q[`tagpos_is:`tagpos_is + 3] == 4'b1011 & + htw_resv1_tag3_lpid_match == 1'b1 & htw_resv1_tag3_pid_match == 1'b1 & htw_resv1_tag3_gs_match == 1'b1 & + htw_resv1_tag3_as_match == 1'b1 & htw_resv1_tag3_epn_loc_match == 1'b1)) ? 1'b1 : + 1'b0; + assign htw_tag3_clr_resv_term7[1] = ((((|(htw_tag3_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] & (~(tlb_ctl_tag3_flush))) == 1'b1 & htw_tag3_q[`tagpos_wq:`tagpos_wq + 1] == 2'b01) | + (|(htw_tag3_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] & (~(tlb_ctl_tag3_flush))) == 1'b1 & htw_tag3_q[`tagpos_wq:`tagpos_wq + 1] == 2'b00)) & + htw_tag3_q[`tagpos_type_tlbwe] == 1'b1 & htw_resv1_tag3_gs_match == 1'b1 & htw_resv1_tag3_as_match == 1'b1 & + htw_resv1_tag3_lpid_match == 1'b1 & htw_resv1_tag3_pid_match == 1'b1 & htw_resv1_tag3_epn_loc_match == 1'b1)) ? 1'b1 : + 1'b0; + assign htw_tag3_clr_resv_term8[1] = ((|(htw_tag3_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & htw_tag3_q[`tagpos_type_ptereload] == 1'b1 & htw_tag3_q[`tagpos_wq:`tagpos_wq + 1] == 2'b10 & + htw_resv1_tag3_gs_match == 1'b1 & htw_resv1_tag3_as_match == 1'b1 & htw_resv1_tag3_lpid_match == 1'b1 & + htw_resv1_tag3_pid_match == 1'b1 & htw_resv1_tag3_epn_loc_match == 1'b1)) ? 1'b1 : + 1'b0; + assign htw_tag3_clr_resv_term9[1] = ((((|(htw_tag3_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] & (~(tlb_ctl_tag3_flush))) == 1'b1 & htw_tag3_q[`tagpos_wq:`tagpos_wq + 1] == 2'b10) | + (|(htw_tag3_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] & (~(tlb_ctl_tag3_flush))) == 1'b1 & htw_tag3_q[`tagpos_wq:`tagpos_wq + 1] == 2'b11)) & + htw_tag3_q[`tagpos_type_tlbwe] == 1'b1 & htw_resv1_tag3_gs_match == 1'b1 & htw_resv1_tag3_as_match == 1'b1 & + htw_resv1_tag3_lpid_match == 1'b1 & htw_resv1_tag3_pid_match == 1'b1 & htw_resv1_tag3_epn_loc_match == 1'b1)) ? 1'b1 : + 1'b0; + assign htw_tag3_clr_resv_term11[1] = ((|(htw_tag3_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & htw_tag3_q[`tagpos_type_snoop] == 1'b1 & htw_tag3_q[`tagpos_is:`tagpos_is + 1] == 2'b11)) ? 1'b1 : + 1'b0; + assign htw_tag4_clr_resv_d[1] = htw_tag3_clr_resv_term2[1] | htw_tag3_clr_resv_term4[1] | htw_tag3_clr_resv_term5[1] | htw_tag3_clr_resv_term6[1] | + htw_tag3_clr_resv_term7[1] | htw_tag3_clr_resv_term8[1] | htw_tag3_clr_resv_term9[1] | htw_tag3_clr_resv_term11[1]; + + + assign htw_tag3_clr_resv_term2[2] = ((|(htw_tag3_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & htw_tag3_q[`tagpos_type_snoop] == 1'b1 & htw_tag3_q[`tagpos_is:`tagpos_is + 3] == 4'b0011 & + htw_resv2_tag3_lpid_match == 1'b1 & htw_resv2_tag3_pid_match == 1'b1 & htw_resv2_tag3_gs_match == 1'b1 & + htw_resv2_tag3_as_match == 1'b1 & htw_resv2_tag3_epn_glob_match == 1'b1)) ? 1'b1 : + 1'b0; + assign htw_tag3_clr_resv_term4[2] = ((|(htw_tag3_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & htw_tag3_q[`tagpos_type_snoop] == 1'b1 & htw_tag3_q[`tagpos_is:`tagpos_is + 3] == 4'b1000 & + htw_resv2_tag3_lpid_match == 1'b1)) ? 1'b1 : + 1'b0; + assign htw_tag3_clr_resv_term5[2] = ((|(htw_tag3_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & htw_tag3_q[`tagpos_type_snoop] == 1'b1 & htw_tag3_q[`tagpos_is:`tagpos_is + 3] == 4'b1001 & + htw_resv2_tag3_lpid_match == 1'b1 & htw_resv2_tag3_pid_match == 1'b1)) ? 1'b1 : + 1'b0; + assign htw_tag3_clr_resv_term6[2] = ((|(htw_tag3_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & htw_tag3_q[`tagpos_type_snoop] == 1'b1 & htw_tag3_q[`tagpos_is:`tagpos_is + 3] == 4'b1011 & + htw_resv2_tag3_lpid_match == 1'b1 & htw_resv2_tag3_pid_match == 1'b1 & htw_resv2_tag3_gs_match == 1'b1 & + htw_resv2_tag3_as_match == 1'b1 & htw_resv2_tag3_epn_loc_match == 1'b1)) ? 1'b1 : + 1'b0; + assign htw_tag3_clr_resv_term7[2] = ((((|(htw_tag3_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] & (~(tlb_ctl_tag3_flush))) == 1'b1 & htw_tag3_q[`tagpos_wq:`tagpos_wq + 1] == 2'b01) | + (|(htw_tag3_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] & (~(tlb_ctl_tag3_flush))) == 1'b1 & htw_tag3_q[`tagpos_wq:`tagpos_wq + 1] == 2'b00)) & + htw_tag3_q[`tagpos_type_tlbwe] == 1'b1 & htw_resv2_tag3_gs_match == 1'b1 & htw_resv2_tag3_as_match == 1'b1 & + htw_resv2_tag3_lpid_match == 1'b1 & htw_resv2_tag3_pid_match == 1'b1 & htw_resv2_tag3_epn_loc_match == 1'b1)) ? 1'b1 : + 1'b0; + assign htw_tag3_clr_resv_term8[2] = ((|(htw_tag3_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & htw_tag3_q[`tagpos_type_ptereload] == 1'b1 & htw_tag3_q[`tagpos_wq:`tagpos_wq + 1] == 2'b10 & + htw_resv2_tag3_gs_match == 1'b1 & htw_resv2_tag3_as_match == 1'b1 & htw_resv2_tag3_lpid_match == 1'b1 & + htw_resv2_tag3_pid_match == 1'b1 & htw_resv2_tag3_epn_loc_match == 1'b1)) ? 1'b1 : + 1'b0; + assign htw_tag3_clr_resv_term9[2] = ((((|(htw_tag3_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] & (~(tlb_ctl_tag3_flush))) == 1'b1 & htw_tag3_q[`tagpos_wq:`tagpos_wq + 1] == 2'b10) | + (|(htw_tag3_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] & (~(tlb_ctl_tag3_flush))) == 1'b1 & htw_tag3_q[`tagpos_wq:`tagpos_wq + 1] == 2'b11)) & + htw_tag3_q[`tagpos_type_tlbwe] == 1'b1 & htw_resv2_tag3_gs_match == 1'b1 & htw_resv2_tag3_as_match == 1'b1 & + htw_resv2_tag3_lpid_match == 1'b1 & htw_resv2_tag3_pid_match == 1'b1 & htw_resv2_tag3_epn_loc_match == 1'b1)) ? 1'b1 : + 1'b0; + assign htw_tag3_clr_resv_term11[2] = ((|(htw_tag3_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & htw_tag3_q[`tagpos_type_snoop] == 1'b1 & htw_tag3_q[`tagpos_is:`tagpos_is + 1] == 2'b11)) ? 1'b1 : + 1'b0; + assign htw_tag4_clr_resv_d[2] = htw_tag3_clr_resv_term2[2] | htw_tag3_clr_resv_term4[2] | htw_tag3_clr_resv_term5[2] | htw_tag3_clr_resv_term6[2] | + htw_tag3_clr_resv_term7[2] | htw_tag3_clr_resv_term8[2] | htw_tag3_clr_resv_term9[2] | htw_tag3_clr_resv_term11[2]; + + + assign htw_tag3_clr_resv_term2[3] = ((|(htw_tag3_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & htw_tag3_q[`tagpos_type_snoop] == 1'b1 & htw_tag3_q[`tagpos_is:`tagpos_is + 3] == 4'b0011 & + htw_resv3_tag3_lpid_match == 1'b1 & htw_resv3_tag3_pid_match == 1'b1 & htw_resv3_tag3_gs_match == 1'b1 & + htw_resv3_tag3_as_match == 1'b1 & htw_resv3_tag3_epn_glob_match == 1'b1)) ? 1'b1 : + 1'b0; + assign htw_tag3_clr_resv_term4[3] = ((|(htw_tag3_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & htw_tag3_q[`tagpos_type_snoop] == 1'b1 & htw_tag3_q[`tagpos_is:`tagpos_is + 3] == 4'b1000 & + htw_resv3_tag3_lpid_match == 1'b1)) ? 1'b1 : + 1'b0; + assign htw_tag3_clr_resv_term5[3] = ((|(htw_tag3_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & htw_tag3_q[`tagpos_type_snoop] == 1'b1 & htw_tag3_q[`tagpos_is:`tagpos_is + 3] == 4'b1001 & + htw_resv3_tag3_lpid_match == 1'b1 & htw_resv3_tag3_pid_match == 1'b1)) ? 1'b1 : + 1'b0; + assign htw_tag3_clr_resv_term6[3] = ((|(htw_tag3_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & htw_tag3_q[`tagpos_type_snoop] == 1'b1 & htw_tag3_q[`tagpos_is:`tagpos_is + 3] == 4'b1011 & + htw_resv3_tag3_lpid_match == 1'b1 & htw_resv3_tag3_pid_match == 1'b1 & htw_resv3_tag3_gs_match == 1'b1 & + htw_resv3_tag3_as_match == 1'b1 & htw_resv3_tag3_epn_loc_match == 1'b1)) ? 1'b1 : + 1'b0; + assign htw_tag3_clr_resv_term7[3] = ((((|(htw_tag3_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] & (~(tlb_ctl_tag3_flush))) == 1'b1 & htw_tag3_q[`tagpos_wq:`tagpos_wq + 1] == 2'b01) | + (|(htw_tag3_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] & (~(tlb_ctl_tag3_flush))) == 1'b1 & htw_tag3_q[`tagpos_wq:`tagpos_wq + 1] == 2'b00)) & + htw_tag3_q[`tagpos_type_tlbwe] == 1'b1 & htw_resv3_tag3_gs_match == 1'b1 & htw_resv3_tag3_as_match == 1'b1 & + htw_resv3_tag3_lpid_match == 1'b1 & htw_resv3_tag3_pid_match == 1'b1 & htw_resv3_tag3_epn_loc_match == 1'b1)) ? 1'b1 : + 1'b0; + assign htw_tag3_clr_resv_term8[3] = ((|(htw_tag3_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & htw_tag3_q[`tagpos_type_ptereload] == 1'b1 & htw_tag3_q[`tagpos_wq:`tagpos_wq + 1] == 2'b10 & + htw_resv3_tag3_gs_match == 1'b1 & htw_resv3_tag3_as_match == 1'b1 & htw_resv3_tag3_lpid_match == 1'b1 & + htw_resv3_tag3_pid_match == 1'b1 & htw_resv3_tag3_epn_loc_match == 1'b1)) ? 1'b1 : + 1'b0; + assign htw_tag3_clr_resv_term9[3] = ((((|(htw_tag3_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] & (~(tlb_ctl_tag3_flush))) == 1'b1 & htw_tag3_q[`tagpos_wq:`tagpos_wq + 1] == 2'b10) | + (|(htw_tag3_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] & (~(tlb_ctl_tag3_flush))) == 1'b1 & htw_tag3_q[`tagpos_wq:`tagpos_wq + 1] == 2'b11)) & + htw_tag3_q[`tagpos_type_tlbwe] == 1'b1 & htw_resv3_tag3_gs_match == 1'b1 & htw_resv3_tag3_as_match == 1'b1 & + htw_resv3_tag3_lpid_match == 1'b1 & htw_resv3_tag3_pid_match == 1'b1 & htw_resv3_tag3_epn_loc_match == 1'b1)) ? 1'b1 : + 1'b0; + assign htw_tag3_clr_resv_term11[3] = ((|(htw_tag3_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & htw_tag3_q[`tagpos_type_snoop] == 1'b1 & htw_tag3_q[`tagpos_is:`tagpos_is + 1] == 2'b11)) ? 1'b1 : + 1'b0; + + assign htw_tag4_clr_resv_d[3] = htw_tag3_clr_resv_term2[3] | htw_tag3_clr_resv_term4[3] | htw_tag3_clr_resv_term5[3] | htw_tag3_clr_resv_term6[3] | htw_tag3_clr_resv_term7[3] | htw_tag3_clr_resv_term8[3] | htw_tag3_clr_resv_term9[3] | htw_tag3_clr_resv_term11[3]; + + + assign htw_tag5_clr_resv_d = (|(tlb_htw_req_tag[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] & (~(tlb_ctl_tag4_flush))) == 1'b1) ? htw_tag4_clr_resv_q : + 4'b0000; + + assign htw_resv_valid_vec = {tlb_htw_req0_tag_q[`tagpos_wq], tlb_htw_req1_tag_q[`tagpos_wq], tlb_htw_req2_tag_q[`tagpos_wq], tlb_htw_req3_tag_q[`tagpos_wq]}; + + assign htw_resv0_tag3_lpid_match = ((htw_tag3_q[`tagpos_lpid:`tagpos_lpid + `LPID_WIDTH - 1] == tlb_htw_req0_tag_q[`tagpos_lpid:`tagpos_lpid + `LPID_WIDTH - 1])) ? 1'b1 : + 1'b0; + assign htw_resv0_tag3_pid_match = ((htw_tag3_q[`tagpos_pid:`tagpos_pid + `PID_WIDTH - 1] == tlb_htw_req0_tag_q[`tagpos_pid:`tagpos_pid + `PID_WIDTH - 1])) ? 1'b1 : + 1'b0; + assign htw_resv0_tag3_as_match = ((htw_tag3_q[`tagpos_as] == tlb_htw_req0_tag_q[`tagpos_as])) ? 1'b1 : + 1'b0; + assign htw_resv0_tag3_gs_match = ((htw_tag3_q[`tagpos_gs] == tlb_htw_req0_tag_q[`tagpos_gs])) ? 1'b1 : + 1'b0; + + // local match includes upper epn bits + assign htw_resv0_tag3_epn_loc_match = ((htw_tag3_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 1] == tlb_htw_req0_tag_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 1] & htw_tag3_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_4KB) | (htw_tag3_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 5] == tlb_htw_req0_tag_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 5] & htw_tag3_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_64KB) | (htw_tag3_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 9] == tlb_htw_req0_tag_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 9] & htw_tag3_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_1MB) | (htw_tag3_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 13] == tlb_htw_req0_tag_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 13] & htw_tag3_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_16MB) | (htw_tag3_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 19] == tlb_htw_req0_tag_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 19] & htw_tag3_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_1GB)) ? 1'b1 : + 1'b0; + // global match ignores certain upper epn bits that are not tranferred over bus + // fix me!! use various upper nibbles dependent on pgsize and mmucr1.tlbi_msb + assign htw_resv0_tag3_epn_glob_match = ((htw_tag3_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 1] == tlb_htw_req0_tag_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 1] & htw_tag3_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_4KB) | (htw_tag3_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 5] == tlb_htw_req0_tag_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 5] & htw_tag3_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_64KB) | (htw_tag3_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 9] == tlb_htw_req0_tag_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 9] & htw_tag3_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_1MB) | (htw_tag3_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 13] == tlb_htw_req0_tag_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 13] & htw_tag3_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_16MB) | (htw_tag3_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 19] == tlb_htw_req0_tag_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 19] & htw_tag3_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_1GB)) ? 1'b1 : + 1'b0; + assign htw_resv1_tag3_lpid_match = ((htw_tag3_q[`tagpos_lpid:`tagpos_lpid + `LPID_WIDTH - 1] == tlb_htw_req1_tag_q[`tagpos_lpid:`tagpos_lpid + `LPID_WIDTH - 1])) ? 1'b1 : + 1'b0; + assign htw_resv1_tag3_pid_match = ((htw_tag3_q[`tagpos_pid:`tagpos_pid + `PID_WIDTH - 1] == tlb_htw_req1_tag_q[`tagpos_pid:`tagpos_pid + `PID_WIDTH - 1])) ? 1'b1 : + 1'b0; + assign htw_resv1_tag3_as_match = ((htw_tag3_q[`tagpos_as] == tlb_htw_req1_tag_q[`tagpos_as])) ? 1'b1 : + 1'b0; + assign htw_resv1_tag3_gs_match = ((htw_tag3_q[`tagpos_gs] == tlb_htw_req1_tag_q[`tagpos_gs])) ? 1'b1 : + 1'b0; + + // local match includes upper epn bits + assign htw_resv1_tag3_epn_loc_match = ((htw_tag3_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 1] == tlb_htw_req1_tag_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 1] & htw_tag3_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_4KB) | (htw_tag3_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 5] == tlb_htw_req1_tag_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 5] & htw_tag3_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_64KB) | (htw_tag3_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 9] == tlb_htw_req1_tag_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 9] & htw_tag3_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_1MB) | (htw_tag3_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 13] == tlb_htw_req1_tag_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 13] & htw_tag3_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_16MB) | (htw_tag3_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 19] == tlb_htw_req1_tag_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 19] & htw_tag3_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_1GB)) ? 1'b1 : + 1'b0; + // global match ignores certain upper epn bits that are not tranferred over bus + // fix me!! use various upper nibbles dependent on pgsize and mmucr1.tlbi_msb + assign htw_resv1_tag3_epn_glob_match = ((htw_tag3_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 1] == tlb_htw_req1_tag_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 1] & htw_tag3_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_4KB) | (htw_tag3_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 5] == tlb_htw_req1_tag_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 5] & htw_tag3_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_64KB) | (htw_tag3_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 9] == tlb_htw_req1_tag_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 9] & htw_tag3_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_1MB) | (htw_tag3_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 13] == tlb_htw_req1_tag_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 13] & htw_tag3_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_16MB) | (htw_tag3_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 19] == tlb_htw_req1_tag_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 19] & htw_tag3_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_1GB)) ? 1'b1 : + 1'b0; + assign htw_resv2_tag3_lpid_match = ((htw_tag3_q[`tagpos_lpid:`tagpos_lpid + `LPID_WIDTH - 1] == tlb_htw_req2_tag_q[`tagpos_lpid:`tagpos_lpid + `LPID_WIDTH - 1])) ? 1'b1 : + 1'b0; + assign htw_resv2_tag3_pid_match = ((htw_tag3_q[`tagpos_pid:`tagpos_pid + `PID_WIDTH - 1] == tlb_htw_req2_tag_q[`tagpos_pid:`tagpos_pid + `PID_WIDTH - 1])) ? 1'b1 : + 1'b0; + assign htw_resv2_tag3_as_match = ((htw_tag3_q[`tagpos_as] == tlb_htw_req2_tag_q[`tagpos_as])) ? 1'b1 : + 1'b0; + assign htw_resv2_tag3_gs_match = ((htw_tag3_q[`tagpos_gs] == tlb_htw_req2_tag_q[`tagpos_gs])) ? 1'b1 : + 1'b0; + + // local match includes upper epn bits + assign htw_resv2_tag3_epn_loc_match = ((htw_tag3_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 1] == tlb_htw_req2_tag_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 1] & htw_tag3_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_4KB) | (htw_tag3_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 5] == tlb_htw_req2_tag_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 5] & htw_tag3_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_64KB) | (htw_tag3_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 9] == tlb_htw_req2_tag_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 9] & htw_tag3_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_1MB) | (htw_tag3_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 13] == tlb_htw_req2_tag_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 13] & htw_tag3_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_16MB) | (htw_tag3_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 19] == tlb_htw_req2_tag_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 19] & htw_tag3_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_1GB)) ? 1'b1 : + 1'b0; + // global match ignores certain upper epn bits that are not tranferred over bus + // fix me!! use various upper nibbles dependent on pgsize and mmucr1.tlbi_msb + assign htw_resv2_tag3_epn_glob_match = ((htw_tag3_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 1] == tlb_htw_req2_tag_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 1] & htw_tag3_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_4KB) | (htw_tag3_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 5] == tlb_htw_req2_tag_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 5] & htw_tag3_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_64KB) | (htw_tag3_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 9] == tlb_htw_req2_tag_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 9] & htw_tag3_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_1MB) | (htw_tag3_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 13] == tlb_htw_req2_tag_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 13] & htw_tag3_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_16MB) | (htw_tag3_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 19] == tlb_htw_req2_tag_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 19] & htw_tag3_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_1GB)) ? 1'b1 : + 1'b0; + assign htw_resv3_tag3_lpid_match = ((htw_tag3_q[`tagpos_lpid:`tagpos_lpid + `LPID_WIDTH - 1] == tlb_htw_req3_tag_q[`tagpos_lpid:`tagpos_lpid + `LPID_WIDTH - 1])) ? 1'b1 : + 1'b0; + assign htw_resv3_tag3_pid_match = ((htw_tag3_q[`tagpos_pid:`tagpos_pid + `PID_WIDTH - 1] == tlb_htw_req3_tag_q[`tagpos_pid:`tagpos_pid + `PID_WIDTH - 1])) ? 1'b1 : + 1'b0; + assign htw_resv3_tag3_as_match = ((htw_tag3_q[`tagpos_as] == tlb_htw_req3_tag_q[`tagpos_as])) ? 1'b1 : + 1'b0; + assign htw_resv3_tag3_gs_match = ((htw_tag3_q[`tagpos_gs] == tlb_htw_req3_tag_q[`tagpos_gs])) ? 1'b1 : + 1'b0; + + // local match includes upper epn bits + assign htw_resv3_tag3_epn_loc_match = ((htw_tag3_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 1] == tlb_htw_req3_tag_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 1] & htw_tag3_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_4KB) | (htw_tag3_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 5] == tlb_htw_req3_tag_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 5] & htw_tag3_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_64KB) | (htw_tag3_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 9] == tlb_htw_req3_tag_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 9] & htw_tag3_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_1MB) | (htw_tag3_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 13] == tlb_htw_req3_tag_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 13] & htw_tag3_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_16MB) | (htw_tag3_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 19] == tlb_htw_req3_tag_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 19] & htw_tag3_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_1GB)) ? 1'b1 : + 1'b0; + // global match ignores certain upper epn bits that are not tranferred over bus + // fix me!! use various upper nibbles dependent on pgsize and mmucr1.tlbi_msb + assign htw_resv3_tag3_epn_glob_match = ((htw_tag3_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 1] == tlb_htw_req3_tag_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 1] & htw_tag3_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_4KB) | (htw_tag3_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 5] == tlb_htw_req3_tag_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 5] & htw_tag3_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_64KB) | (htw_tag3_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 9] == tlb_htw_req3_tag_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 9] & htw_tag3_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_1MB) | (htw_tag3_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 13] == tlb_htw_req3_tag_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 13] & htw_tag3_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_16MB) | (htw_tag3_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 19] == tlb_htw_req3_tag_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 19] & htw_tag3_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_1GB)) ? 1'b1 : + 1'b0; + assign pte0_score_act = (|(pte0_seq_q) | |(htw_seq_q) | mmucr2_act_override) & xu_mm_ccr2_notlb_b; + assign pte0_score_ptr_d = (pte0_seq_score_load == 1'b1) ? htw_lsuptr_q : + pte0_score_ptr_q; + assign pte0_score_cl_offset_d = (pte0_seq_score_load == 1'b1 & htw_lsuptr_q == 2'b00) ? pte_ra_0[58:60] : + (pte0_seq_score_load == 1'b1 & htw_lsuptr_q == 2'b01) ? pte_ra_1[58:60] : + (pte0_seq_score_load == 1'b1 & htw_lsuptr_q == 2'b10) ? pte_ra_2[58:60] : + (pte0_seq_score_load == 1'b1 & htw_lsuptr_q == 2'b11) ? pte_ra_3[58:60] : + pte0_score_cl_offset_q; + assign pte0_score_ibit_d = (pte0_seq_score_load == 1'b1 & htw_lsuptr_q == 2'b00) ? tlb_htw_req0_way_q[`waypos_wimge + 1] : + (pte0_seq_score_load == 1'b1 & htw_lsuptr_q == 2'b01) ? tlb_htw_req1_way_q[`waypos_wimge + 1] : + (pte0_seq_score_load == 1'b1 & htw_lsuptr_q == 2'b10) ? tlb_htw_req2_way_q[`waypos_wimge + 1] : + (pte0_seq_score_load == 1'b1 & htw_lsuptr_q == 2'b11) ? tlb_htw_req3_way_q[`waypos_wimge + 1] : + pte0_score_ibit_q; + assign pte0_score_pending_d = (pte0_seq_score_load == 1'b1) ? 1'b1 : + (pte0_seq_score_done == 1'b1) ? 1'b0 : + pte0_score_pending_q; + + // 4 quadword data beats being returned; entire CL repeated if any beat has ecc error + // beats need to be set regardless of ecc present..ecc and any qw happen simultaneously + assign pte0_score_qwbeat_d[0] = (pte0_seq_score_load == 1'b1 | pte0_seq_data_retry == 1'b1) ? 1'b0 : + ((pte0_score_pending_q == 1'b1 & reld_data_vld_tp2_q == 1'b1 & reld_ditc_tp2_q == 1'b0 & reld_core_tag_tp2_q == Core_Tag0_Value & reld_qw_tp2_q == 2'b00)) ? 1'b1 : + pte0_score_qwbeat_q[0]; + assign pte0_score_qwbeat_d[1] = (pte0_seq_score_load == 1'b1 | pte0_seq_data_retry == 1'b1) ? 1'b0 : + ((pte0_score_pending_q == 1'b1 & reld_data_vld_tp2_q == 1'b1 & reld_ditc_tp2_q == 1'b0 & reld_core_tag_tp2_q == Core_Tag0_Value & reld_qw_tp2_q == 2'b01)) ? 1'b1 : + pte0_score_qwbeat_q[1]; + assign pte0_score_qwbeat_d[2] = (pte0_seq_score_load == 1'b1 | pte0_seq_data_retry == 1'b1) ? 1'b0 : + ((pte0_score_pending_q == 1'b1 & reld_data_vld_tp2_q == 1'b1 & reld_ditc_tp2_q == 1'b0 & reld_core_tag_tp2_q == Core_Tag0_Value & reld_qw_tp2_q == 2'b10)) ? 1'b1 : + pte0_score_qwbeat_q[2]; + assign pte0_score_qwbeat_d[3] = (pte0_seq_score_load == 1'b1 | pte0_seq_data_retry == 1'b1) ? 1'b0 : + ((pte0_score_pending_q == 1'b1 & reld_data_vld_tp2_q == 1'b1 & reld_ditc_tp2_q == 1'b0 & reld_core_tag_tp2_q == Core_Tag0_Value & reld_qw_tp2_q == 2'b11)) ? 1'b1 : + pte0_score_qwbeat_q[3]; + // ecc error detection: bit0=ECC, bit1=UE, bit2=retry + assign pte0_score_error_d[0] = (pte0_seq_score_load == 1'b1) ? 1'b0 : + ((pte0_score_pending_q == 1'b1 & reld_data_vld_tp2_q == 1'b1 & reld_ditc_tp2_q == 1'b0 & reld_core_tag_tp2_q == Core_Tag0_Value & reld_ecc_err_tp2_q == 1'b1)) ? 1'b1 : + pte0_score_error_q[0]; + assign pte0_score_error_d[1] = (pte0_seq_score_load == 1'b1) ? 1'b0 : + ((pte0_score_pending_q == 1'b1 & reld_data_vld_tp2_q == 1'b1 & reld_ditc_tp2_q == 1'b0 & reld_core_tag_tp2_q == Core_Tag0_Value & reld_ecc_err_ue_tp2_q == 1'b1)) ? 1'b1 : + pte0_score_error_q[1]; + assign pte0_score_error_d[2] = (pte0_seq_score_load == 1'b1) ? 1'b0 : + (pte0_seq_data_retry == 1'b1) ? 1'b1 : + pte0_score_error_q[2]; + assign pte0_score_dataval_d = (pte0_seq_score_load == 1'b1 | pte0_seq_data_retry == 1'b1) ? 1'b0 : + ((pte0_score_pending_q == 1'b1 & reld_data_vld_tp2_q == 1'b1 & reld_ditc_tp2_q == 1'b0 & reld_crit_qw_tp2_q == 1'b1 & reld_qw_tp2_q == pte0_score_cl_offset_q[58:59] & reld_core_tag_tp2_q == Core_Tag0_Value)) ? 1'b1 : + pte0_score_dataval_q; + + + assign pte1_score_act = (|(pte1_seq_q) | |(htw_seq_q) | mmucr2_act_override) & xu_mm_ccr2_notlb_b; + assign pte1_score_ptr_d = (pte1_seq_score_load == 1'b1) ? htw_lsuptr_q : + pte1_score_ptr_q; + assign pte1_score_cl_offset_d = (pte1_seq_score_load == 1'b1 & htw_lsuptr_q == 2'b00) ? pte_ra_0[58:60] : + (pte1_seq_score_load == 1'b1 & htw_lsuptr_q == 2'b01) ? pte_ra_1[58:60] : + (pte1_seq_score_load == 1'b1 & htw_lsuptr_q == 2'b10) ? pte_ra_2[58:60] : + (pte1_seq_score_load == 1'b1 & htw_lsuptr_q == 2'b11) ? pte_ra_3[58:60] : + pte1_score_cl_offset_q; + assign pte1_score_ibit_d = (pte1_seq_score_load == 1'b1 & htw_lsuptr_q == 2'b00) ? tlb_htw_req0_way_q[`waypos_wimge + 1] : + (pte1_seq_score_load == 1'b1 & htw_lsuptr_q == 2'b01) ? tlb_htw_req1_way_q[`waypos_wimge + 1] : + (pte1_seq_score_load == 1'b1 & htw_lsuptr_q == 2'b10) ? tlb_htw_req2_way_q[`waypos_wimge + 1] : + (pte1_seq_score_load == 1'b1 & htw_lsuptr_q == 2'b11) ? tlb_htw_req3_way_q[`waypos_wimge + 1] : + pte1_score_ibit_q; + assign pte1_score_pending_d = (pte1_seq_score_load == 1'b1) ? 1'b1 : + (pte1_seq_score_done == 1'b1) ? 1'b0 : + pte1_score_pending_q; + + // 4 quadword data beats being returned; entire CL repeated if any beat has ecc error + // beats need to be set regardless of ecc present..ecc and any qw happen simultaneously + assign pte1_score_qwbeat_d[0] = (pte1_seq_score_load == 1'b1 | pte1_seq_data_retry == 1'b1) ? 1'b0 : + ((pte1_score_pending_q == 1'b1 & reld_data_vld_tp2_q == 1'b1 & reld_ditc_tp2_q == 1'b0 & reld_core_tag_tp2_q == Core_Tag1_Value & reld_qw_tp2_q == 2'b00)) ? 1'b1 : + pte1_score_qwbeat_q[0]; + assign pte1_score_qwbeat_d[1] = (pte1_seq_score_load == 1'b1 | pte1_seq_data_retry == 1'b1) ? 1'b0 : + ((pte1_score_pending_q == 1'b1 & reld_data_vld_tp2_q == 1'b1 & reld_ditc_tp2_q == 1'b0 & reld_core_tag_tp2_q == Core_Tag1_Value & reld_qw_tp2_q == 2'b01)) ? 1'b1 : + pte1_score_qwbeat_q[1]; + assign pte1_score_qwbeat_d[2] = (pte1_seq_score_load == 1'b1 | pte1_seq_data_retry == 1'b1) ? 1'b0 : + ((pte1_score_pending_q == 1'b1 & reld_data_vld_tp2_q == 1'b1 & reld_ditc_tp2_q == 1'b0 & reld_core_tag_tp2_q == Core_Tag1_Value & reld_qw_tp2_q == 2'b10)) ? 1'b1 : + pte1_score_qwbeat_q[2]; + assign pte1_score_qwbeat_d[3] = (pte1_seq_score_load == 1'b1 | pte1_seq_data_retry == 1'b1) ? 1'b0 : + ((pte1_score_pending_q == 1'b1 & reld_data_vld_tp2_q == 1'b1 & reld_ditc_tp2_q == 1'b0 & reld_core_tag_tp2_q == Core_Tag1_Value & reld_qw_tp2_q == 2'b11)) ? 1'b1 : + pte1_score_qwbeat_q[3]; + // ecc error detection: bit0=ECC, bit1=UE, bit2=retry + assign pte1_score_error_d[0] = (pte1_seq_score_load == 1'b1) ? 1'b0 : + ((pte1_score_pending_q == 1'b1 & reld_data_vld_tp2_q == 1'b1 & reld_ditc_tp2_q == 1'b0 & reld_core_tag_tp2_q == Core_Tag1_Value & reld_ecc_err_tp2_q == 1'b1)) ? 1'b1 : + pte1_score_error_q[0]; + assign pte1_score_error_d[1] = (pte1_seq_score_load == 1'b1) ? 1'b0 : + ((pte1_score_pending_q == 1'b1 & reld_data_vld_tp2_q == 1'b1 & reld_ditc_tp2_q == 1'b0 & reld_core_tag_tp2_q == Core_Tag1_Value & reld_ecc_err_ue_tp2_q == 1'b1)) ? 1'b1 : + pte1_score_error_q[1]; + assign pte1_score_error_d[2] = (pte1_seq_score_load == 1'b1) ? 1'b0 : + (pte1_seq_data_retry == 1'b1) ? 1'b1 : + pte1_score_error_q[2]; + assign pte1_score_dataval_d = (pte1_seq_score_load == 1'b1 | pte1_seq_data_retry == 1'b1) ? 1'b0 : + ((pte1_score_pending_q == 1'b1 & reld_data_vld_tp2_q == 1'b1 & reld_ditc_tp2_q == 1'b0 & reld_crit_qw_tp2_q == 1'b1 & reld_qw_tp2_q == pte1_score_cl_offset_q[58:59] & reld_core_tag_tp2_q == Core_Tag1_Value)) ? 1'b1 : + pte1_score_dataval_q; + + + // pointers: + // htw_inptr: tlb to htw incoming request queue pointer, 4 total + // htw_lsuptr: htw to lru outgoing request queue pointer, 4 total + // pte_load_ptr: pte machine pointer next to load, 2 total + // ptereload_ptr: pte to tlb data reload select, 2 total + assign htw_inptr_d = (htw_inptr_q == 2'b00 & tlb_htw_req0_valid_q == 1'b0 & tlb_htw_req1_valid_q == 1'b0 & tlb_htw_req_valid == 1'b1) ? 2'b01 : + (htw_inptr_q == 2'b00 & tlb_htw_req0_valid_q == 1'b0 & tlb_htw_req1_valid_q == 1'b1 & tlb_htw_req2_valid_q == 1'b0 & tlb_htw_req_valid == 1'b1) ? 2'b10 : + (htw_inptr_q == 2'b00 & tlb_htw_req0_valid_q == 1'b0 & tlb_htw_req1_valid_q == 1'b1 & tlb_htw_req2_valid_q == 1'b1 & tlb_htw_req3_valid_q == 1'b0 & tlb_htw_req_valid == 1'b1) ? 2'b11 : + (htw_inptr_q == 2'b01 & tlb_htw_req1_valid_q == 1'b0 & tlb_htw_req2_valid_q == 1'b0 & tlb_htw_req_valid == 1'b1) ? 2'b10 : + (htw_inptr_q == 2'b01 & tlb_htw_req1_valid_q == 1'b0 & tlb_htw_req2_valid_q == 1'b1 & tlb_htw_req3_valid_q == 1'b0 & tlb_htw_req_valid == 1'b1) ? 2'b11 : + (htw_inptr_q == 2'b01 & tlb_htw_req1_valid_q == 1'b0 & tlb_htw_req2_valid_q == 1'b1 & tlb_htw_req3_valid_q == 1'b1 & tlb_htw_req0_valid_q == 1'b0 & tlb_htw_req_valid == 1'b1) ? 2'b00 : + (htw_inptr_q == 2'b10 & tlb_htw_req2_valid_q == 1'b0 & tlb_htw_req3_valid_q == 1'b0 & tlb_htw_req_valid == 1'b1) ? 2'b11 : + (htw_inptr_q == 2'b10 & tlb_htw_req2_valid_q == 1'b0 & tlb_htw_req3_valid_q == 1'b1 & tlb_htw_req0_valid_q == 1'b0 & tlb_htw_req_valid == 1'b1) ? 2'b00 : + (htw_inptr_q == 2'b10 & tlb_htw_req2_valid_q == 1'b0 & tlb_htw_req3_valid_q == 1'b1 & tlb_htw_req0_valid_q == 1'b1 & tlb_htw_req1_valid_q == 1'b0 & tlb_htw_req_valid == 1'b1) ? 2'b01 : + (htw_inptr_q == 2'b11 & tlb_htw_req3_valid_q == 1'b0 & tlb_htw_req0_valid_q == 1'b0 & tlb_htw_req_valid == 1'b1) ? 2'b00 : + (htw_inptr_q == 2'b11 & tlb_htw_req3_valid_q == 1'b0 & tlb_htw_req0_valid_q == 1'b1 & tlb_htw_req1_valid_q == 1'b0 & tlb_htw_req_valid == 1'b1) ? 2'b01 : + (htw_inptr_q == 2'b11 & tlb_htw_req3_valid_q == 1'b0 & tlb_htw_req0_valid_q == 1'b1 & tlb_htw_req1_valid_q == 1'b1 & tlb_htw_req2_valid_q == 1'b0 & tlb_htw_req_valid == 1'b1) ? 2'b10 : + (ptereload_ptr_q == 1'b0 & ptereload_req_taken == 1'b1) ? pte0_score_ptr_q : + (ptereload_ptr_q == 1'b1 & ptereload_req_taken == 1'b1) ? pte1_score_ptr_q : + htw_inptr_q; + + assign htw_lsuptr_d = (htw_lsuptr_q == 2'b00 & tlb_htw_req_valid_vec[0] == 1'b0 & tlb_htw_req_valid_vec[1] == 1'b1) ? 2'b01 : + (htw_lsuptr_q == 2'b00 & tlb_htw_req_valid_vec[0] == 1'b0 & tlb_htw_req_valid_vec[1] == 1'b0 & tlb_htw_req_valid_vec[2] == 1'b1) ? 2'b10 : + (htw_lsuptr_q == 2'b00 & tlb_htw_req_valid_vec[0] == 1'b0 & tlb_htw_req_valid_vec[1] == 1'b0 & tlb_htw_req_valid_vec[2] == 1'b0 & tlb_htw_req_valid_vec[3] == 1'b1) ? 2'b11 : + (htw_lsuptr_q == 2'b01 & tlb_htw_req_valid_vec[1] == 1'b0 & tlb_htw_req_valid_vec[2] == 1'b1) ? 2'b10 : + (htw_lsuptr_q == 2'b01 & tlb_htw_req_valid_vec[1] == 1'b0 & tlb_htw_req_valid_vec[2] == 1'b0 & tlb_htw_req_valid_vec[3] == 1'b1) ? 2'b11 : + (htw_lsuptr_q == 2'b01 & tlb_htw_req_valid_vec[1] == 1'b0 & tlb_htw_req_valid_vec[2] == 1'b0 & tlb_htw_req_valid_vec[3] == 1'b0 & tlb_htw_req_valid_vec[0] == 1'b1) ? 2'b00 : + (htw_lsuptr_q == 2'b10 & tlb_htw_req_valid_vec[2] == 1'b0 & tlb_htw_req_valid_vec[3] == 1'b1) ? 2'b11 : + (htw_lsuptr_q == 2'b10 & tlb_htw_req_valid_vec[2] == 1'b0 & tlb_htw_req_valid_vec[3] == 1'b0 & tlb_htw_req_valid_vec[0] == 1'b1) ? 2'b00 : + (htw_lsuptr_q == 2'b10 & tlb_htw_req_valid_vec[2] == 1'b0 & tlb_htw_req_valid_vec[3] == 1'b0 & tlb_htw_req_valid_vec[0] == 1'b0 & tlb_htw_req_valid_vec[1] == 1'b1) ? 2'b01 : + (htw_lsuptr_q == 2'b11 & tlb_htw_req_valid_vec[3] == 1'b0 & tlb_htw_req_valid_vec[0] == 1'b1) ? 2'b00 : + (htw_lsuptr_q == 2'b11 & tlb_htw_req_valid_vec[3] == 1'b0 & tlb_htw_req_valid_vec[0] == 1'b0 & tlb_htw_req_valid_vec[1] == 1'b1) ? 2'b01 : + (htw_lsuptr_q == 2'b11 & tlb_htw_req_valid_vec[3] == 1'b0 & tlb_htw_req_valid_vec[0] == 1'b0 & tlb_htw_req_valid_vec[1] == 1'b0 & tlb_htw_req_valid_vec[2] == 1'b1) ? 2'b10 : + htw_lsuptr_q; + + assign tlb_htw_req_valid_notpend_vec = {(tlb_htw_req0_valid_q & (~tlb_htw_req0_pending_q)), (tlb_htw_req1_valid_q & (~tlb_htw_req1_pending_q)), (tlb_htw_req2_valid_q & (~tlb_htw_req2_pending_q)), (tlb_htw_req3_valid_q & (~tlb_htw_req3_pending_q))}; + + assign htw_lsuptr_alt_d = (htw_lsuptr_q == 2'b00 & tlb_htw_req_valid_notpend_vec[0] == 1'b1 & htw_lsu_req_taken == 1'b1) ? 2'b01 : + (htw_lsuptr_q == 2'b01 & tlb_htw_req_valid_notpend_vec[1] == 1'b1 & htw_lsu_req_taken == 1'b1) ? 2'b10 : + (htw_lsuptr_q == 2'b10 & tlb_htw_req_valid_notpend_vec[2] == 1'b1 & htw_lsu_req_taken == 1'b1) ? 2'b11 : + (htw_lsuptr_q == 2'b11 & tlb_htw_req_valid_notpend_vec[3] == 1'b1 & htw_lsu_req_taken == 1'b1) ? 2'b00 : + (htw_lsuptr_q == 2'b00 & tlb_htw_req_valid_notpend_vec[0] == 1'b0 & tlb_htw_req_valid_notpend_vec[1] == 1'b1) ? 2'b01 : + (htw_lsuptr_q == 2'b00 & tlb_htw_req_valid_notpend_vec[0] == 1'b0 & tlb_htw_req_valid_notpend_vec[1] == 1'b0 & tlb_htw_req_valid_notpend_vec[2] == 1'b1) ? 2'b10 : + (htw_lsuptr_q == 2'b00 & tlb_htw_req_valid_notpend_vec[0] == 1'b0 & tlb_htw_req_valid_notpend_vec[1] == 1'b0 & tlb_htw_req_valid_notpend_vec[2] == 1'b0 & tlb_htw_req_valid_notpend_vec[3] == 1'b1) ? 2'b11 : + (htw_lsuptr_q == 2'b01 & tlb_htw_req_valid_notpend_vec[1] == 1'b0 & tlb_htw_req_valid_notpend_vec[2] == 1'b1) ? 2'b10 : + (htw_lsuptr_q == 2'b01 & tlb_htw_req_valid_notpend_vec[1] == 1'b0 & tlb_htw_req_valid_notpend_vec[2] == 1'b0 & tlb_htw_req_valid_notpend_vec[3] == 1'b1) ? 2'b11 : + (htw_lsuptr_q == 2'b01 & tlb_htw_req_valid_notpend_vec[1] == 1'b0 & tlb_htw_req_valid_notpend_vec[2] == 1'b0 & tlb_htw_req_valid_notpend_vec[3] == 1'b0 & tlb_htw_req_valid_notpend_vec[0] == 1'b1) ? 2'b00 : + (htw_lsuptr_q == 2'b10 & tlb_htw_req_valid_notpend_vec[2] == 1'b0 & tlb_htw_req_valid_notpend_vec[3] == 1'b1) ? 2'b11 : + (htw_lsuptr_q == 2'b10 & tlb_htw_req_valid_notpend_vec[2] == 1'b0 & tlb_htw_req_valid_notpend_vec[3] == 1'b0 & tlb_htw_req_valid_notpend_vec[0] == 1'b1) ? 2'b00 : + (htw_lsuptr_q == 2'b10 & tlb_htw_req_valid_notpend_vec[2] == 1'b0 & tlb_htw_req_valid_notpend_vec[3] == 1'b0 & tlb_htw_req_valid_notpend_vec[0] == 1'b0 & tlb_htw_req_valid_notpend_vec[1] == 1'b1) ? 2'b01 : + (htw_lsuptr_q == 2'b11 & tlb_htw_req_valid_notpend_vec[3] == 1'b0 & tlb_htw_req_valid_notpend_vec[0] == 1'b1) ? 2'b00 : + (htw_lsuptr_q == 2'b11 & tlb_htw_req_valid_notpend_vec[3] == 1'b0 & tlb_htw_req_valid_notpend_vec[0] == 1'b0 & tlb_htw_req_valid_notpend_vec[1] == 1'b1) ? 2'b01 : + (htw_lsuptr_q == 2'b11 & tlb_htw_req_valid_notpend_vec[3] == 1'b0 & tlb_htw_req_valid_notpend_vec[0] == 1'b0 & tlb_htw_req_valid_notpend_vec[1] == 1'b0 & tlb_htw_req_valid_notpend_vec[2] == 1'b1) ? 2'b10 : + htw_lsuptr_q; + + assign pte_load_ptr_d = (ptereload_ptr_q == 1'b1 & pte1_score_pending_q == 1'b1 & pte0_score_pending_d == 1'b1 & ptereload_req_taken == 1'b1) ? 1'b1 : + (ptereload_ptr_q == 1'b0 & pte0_score_pending_q == 1'b1 & pte1_score_pending_d == 1'b1 & ptereload_req_taken == 1'b1) ? 1'b0 : + (pte_load_ptr_q == 1'b0 & pte0_seq_score_load == 1'b1 & pte1_score_pending_q == 1'b0) ? 1'b1 : + (pte_load_ptr_q == 1'b1 & pte1_seq_score_load == 1'b1 & pte0_score_pending_q == 1'b0) ? 1'b0 : + pte_load_ptr_q; + + assign ptereload_ptr_d = (ptereload_ptr_q == 1'b0 & ptereload_req_taken == 1'b1) ? 1'b1 : + (ptereload_ptr_q == 1'b0 & pte0_reload_req_valid == 1'b0 & pte1_reload_req_valid == 1'b1) ? 1'b1 : + (ptereload_ptr_q == 1'b1 & ptereload_req_taken == 1'b1) ? 1'b0 : + (ptereload_ptr_q == 1'b1 & pte0_reload_req_valid == 1'b1 & pte1_reload_req_valid == 1'b0) ? 1'b0 : + ptereload_ptr_q; + + // 0=tlbivax_op, 1=tlbi_complete, 2=mmu read with core_tag=01100, 3=mmu read with core_tag=01101 + assign htw_lsu_ttype_d = ((pte_load_ptr_q == 1'b1 & htw_seq_load_pteaddr == 1'b1)) ? 2'b11 : + (htw_seq_load_pteaddr == 1'b1) ? 2'b10 : + htw_lsu_ttype_q; + assign htw_lsu_thdid_d = (htw_lsuptr_q == 2'b00 & tlb_htw_req0_valid_q == 1'b1 & htw_seq_load_pteaddr == 1'b1) ? tlb_htw_req0_tag_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1] : + (htw_lsuptr_q == 2'b01 & tlb_htw_req1_valid_q == 1'b1 & htw_seq_load_pteaddr == 1'b1) ? tlb_htw_req1_tag_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1] : + (htw_lsuptr_q == 2'b10 & tlb_htw_req2_valid_q == 1'b1 & htw_seq_load_pteaddr == 1'b1) ? tlb_htw_req2_tag_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1] : + (htw_lsuptr_q == 2'b11 & tlb_htw_req3_valid_q == 1'b1 & htw_seq_load_pteaddr == 1'b1) ? tlb_htw_req3_tag_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1] : + htw_lsu_thdid_q; + assign htw_lsu_wimge_d = (htw_lsuptr_q == 2'b00 & tlb_htw_req0_valid_q == 1'b1 & htw_seq_load_pteaddr == 1'b1) ? tlb_htw_req0_way_q[`waypos_wimge:`waypos_wimge + 4] : + (htw_lsuptr_q == 2'b01 & tlb_htw_req1_valid_q == 1'b1 & htw_seq_load_pteaddr == 1'b1) ? tlb_htw_req1_way_q[`waypos_wimge:`waypos_wimge + 4] : + (htw_lsuptr_q == 2'b10 & tlb_htw_req2_valid_q == 1'b1 & htw_seq_load_pteaddr == 1'b1) ? tlb_htw_req2_way_q[`waypos_wimge:`waypos_wimge + 4] : + (htw_lsuptr_q == 2'b11 & tlb_htw_req3_valid_q == 1'b1 & htw_seq_load_pteaddr == 1'b1) ? tlb_htw_req3_way_q[`waypos_wimge:`waypos_wimge + 4] : + htw_lsu_wimge_q; + assign htw_lsu_u_d = (htw_lsuptr_q == 2'b00 & tlb_htw_req0_valid_q == 1'b1 & htw_seq_load_pteaddr == 1'b1) ? tlb_htw_req0_way_q[`waypos_ubits:`waypos_ubits + 3] : + (htw_lsuptr_q == 2'b01 & tlb_htw_req1_valid_q == 1'b1 & htw_seq_load_pteaddr == 1'b1) ? tlb_htw_req1_way_q[`waypos_ubits:`waypos_ubits + 3] : + (htw_lsuptr_q == 2'b10 & tlb_htw_req2_valid_q == 1'b1 & htw_seq_load_pteaddr == 1'b1) ? tlb_htw_req2_way_q[`waypos_ubits:`waypos_ubits + 3] : + (htw_lsuptr_q == 2'b11 & tlb_htw_req3_valid_q == 1'b1 & htw_seq_load_pteaddr == 1'b1) ? tlb_htw_req3_way_q[`waypos_ubits:`waypos_ubits + 3] : + htw_lsu_u_q; + assign htw_lsu_addr_d = (htw_lsuptr_q == 2'b00 & tlb_htw_req0_valid_q == 1'b1 & htw_seq_load_pteaddr == 1'b1) ? pte_ra_0 : + (htw_lsuptr_q == 2'b01 & tlb_htw_req1_valid_q == 1'b1 & htw_seq_load_pteaddr == 1'b1) ? pte_ra_1 : + (htw_lsuptr_q == 2'b10 & tlb_htw_req2_valid_q == 1'b1 & htw_seq_load_pteaddr == 1'b1) ? pte_ra_2 : + (htw_lsuptr_q == 2'b11 & tlb_htw_req3_valid_q == 1'b1 & htw_seq_load_pteaddr == 1'b1) ? pte_ra_3 : + htw_lsu_addr_q; + assign htw_lsu_act = (|(htw_seq_q) | mmucr2_act_override) & xu_mm_ccr2_notlb_b; + assign htw_lsu_thdid = htw_lsu_thdid_q; + assign htw_dbg_lsu_thdid[0] = htw_lsu_thdid_q[2] | htw_lsu_thdid_q[3]; + assign htw_dbg_lsu_thdid[1] = htw_lsu_thdid_q[1] | htw_lsu_thdid_q[3]; + assign htw_lsu_ttype = htw_lsu_ttype_q; + assign htw_lsu_wimge = htw_lsu_wimge_q; + assign htw_lsu_u = htw_lsu_u_q; + assign htw_lsu_addr = htw_lsu_addr_q; + // L2 data reload stages + // t minus 2 phase + assign reld_core_tag_tm1_d = an_ac_reld_core_tag; + assign reld_qw_tm1_d = an_ac_reld_qw; + assign reld_crit_qw_tm1_d = an_ac_reld_crit_qw; + assign reld_ditc_tm1_d = an_ac_reld_ditc; + assign reld_data_vld_tm1_d = an_ac_reld_data_vld; + // t minus 1 phase + assign reld_core_tag_t_d = reld_core_tag_tm1_q; + assign reld_qw_t_d = reld_qw_tm1_q; + assign reld_crit_qw_t_d = reld_crit_qw_tm1_q; + assign reld_ditc_t_d = reld_ditc_tm1_q; + assign reld_data_vld_t_d = reld_data_vld_tm1_q; + assign pte0_reld_for_me_tm1 = ((reld_data_vld_tm1_q == 1'b1 & reld_ditc_tm1_q == 1'b0 & reld_crit_qw_tm1_q == 1'b1 & reld_qw_tm1_q == pte0_score_cl_offset_q[58:59] & reld_core_tag_tm1_q == Core_Tag0_Value)) ? 1'b1 : + 1'b0; + assign pte1_reld_for_me_tm1 = ((reld_data_vld_tm1_q == 1'b1 & reld_ditc_tm1_q == 1'b0 & reld_crit_qw_tm1_q == 1'b1 & reld_qw_tm1_q == pte1_score_cl_offset_q[58:59] & reld_core_tag_tm1_q == Core_Tag1_Value)) ? 1'b1 : + 1'b0; + // t phase + assign reld_core_tag_tp1_d = reld_core_tag_t_q; + assign reld_qw_tp1_d = reld_qw_t_q; + assign reld_crit_qw_tp1_d = reld_crit_qw_t_q; + assign reld_ditc_tp1_d = reld_ditc_t_q; + assign reld_data_vld_tp1_d = reld_data_vld_t_q; + assign reld_data_tp1_d = an_ac_reld_data; + // t plus 1 phase + assign reld_core_tag_tp2_d = reld_core_tag_tp1_q; + assign reld_qw_tp2_d = reld_qw_tp1_q; + assign reld_crit_qw_tp2_d = reld_crit_qw_tp1_q; + assign reld_ditc_tp2_d = reld_ditc_tp1_q; + assign reld_data_vld_tp2_d = reld_data_vld_tp1_q; + assign reld_data_tp2_d = reld_data_tp1_q; + assign reld_ecc_err_tp2_d = an_ac_reld_ecc_err; + assign reld_ecc_err_ue_tp2_d = an_ac_reld_ecc_err_ue; + // t plus 2 phase + assign pte0_reld_for_me_tp2 = ((reld_data_vld_tp2_q == 1'b1 & reld_ditc_tp2_q == 1'b0 & reld_crit_qw_tp2_q == 1'b1 & reld_qw_tp2_q == pte0_score_cl_offset_q[58:59] & reld_core_tag_tp2_q == Core_Tag0_Value)) ? 1'b1 : + 1'b0; + assign pte0_reld_data_tp3_d = ((pte0_reld_for_me_tp2 == 1'b1 & pte0_score_cl_offset_q[60] == 1'b0)) ? reld_data_tp2_q[0:63] : + ((pte0_reld_for_me_tp2 == 1'b1 & pte0_score_cl_offset_q[60] == 1'b1)) ? reld_data_tp2_q[64:127] : + pte0_reld_data_tp3_q; + assign pte1_reld_for_me_tp2 = ((reld_data_vld_tp2_q == 1'b1 & reld_ditc_tp2_q == 1'b0 & reld_crit_qw_tp2_q == 1'b1 & reld_qw_tp2_q == pte1_score_cl_offset_q[58:59] & reld_core_tag_tp2_q == Core_Tag1_Value)) ? 1'b1 : + 1'b0; + assign pte1_reld_data_tp3_d = ((pte1_reld_for_me_tp2 == 1'b1 & pte1_score_cl_offset_q[60] == 1'b0)) ? reld_data_tp2_q[0:63] : + ((pte1_reld_for_me_tp2 == 1'b1 & pte1_score_cl_offset_q[60] == 1'b1)) ? reld_data_tp2_q[64:127] : + pte1_reld_data_tp3_q; + assign reld_act = (|(pte0_seq_q) | |(pte1_seq_q) | mmucr2_act_override) & xu_mm_ccr2_notlb_b; + assign pte0_reld_act = (|(pte0_seq_q) | mmucr2_act_override) & xu_mm_ccr2_notlb_b; + assign pte1_reld_act = (|(pte1_seq_q) | mmucr2_act_override) & xu_mm_ccr2_notlb_b; + // ptereload requests to tlb_ctl + assign ptereload_req_valid = ((htw_tag4_clr_resv_q != 4'b0000 | htw_tag5_clr_resv_q != 4'b0000)) ? 1'b0 : + (ptereload_ptr_q == 1'b1) ? pte1_reload_req_valid : + pte0_reload_req_valid; + assign ptereload_req_tag = (((ptereload_ptr_q == 1'b0 & pte0_score_ptr_q == 2'b01) | (ptereload_ptr_q == 1'b1 & pte1_score_ptr_q == 2'b01))) ? tlb_htw_req1_tag_q : + (((ptereload_ptr_q == 1'b0 & pte0_score_ptr_q == 2'b10) | (ptereload_ptr_q == 1'b1 & pte1_score_ptr_q == 2'b10))) ? tlb_htw_req2_tag_q : + (((ptereload_ptr_q == 1'b0 & pte0_score_ptr_q == 2'b11) | (ptereload_ptr_q == 1'b1 & pte1_score_ptr_q == 2'b11))) ? tlb_htw_req3_tag_q : + tlb_htw_req0_tag_q; + assign ptereload_req_pte = (ptereload_ptr_q == 1'b1) ? pte1_reld_data_tp3_q : + pte0_reld_data_tp3_q; + + assign htw_tag4_clr_resv_terms = {4{1'b0}}; + assign htw_dbg_seq_idle = htw_seq_idle; + assign htw_dbg_pte0_seq_idle = pte0_seq_idle; + assign htw_dbg_pte1_seq_idle = pte1_seq_idle; + assign htw_dbg_seq_q = htw_seq_q; + assign htw_dbg_inptr_q = htw_inptr_q; + assign htw_dbg_pte0_seq_q = pte0_seq_q; + assign htw_dbg_pte1_seq_q = pte1_seq_q; + assign htw_dbg_ptereload_ptr_q = ptereload_ptr_q; + assign htw_dbg_lsuptr_q = htw_lsuptr_q; + assign htw_dbg_req_valid_q = {tlb_htw_req0_valid_q, tlb_htw_req1_valid_q, tlb_htw_req2_valid_q, tlb_htw_req3_valid_q}; + assign htw_dbg_resv_valid_vec = htw_resv_valid_vec; + assign htw_dbg_tag4_clr_resv_q = htw_tag4_clr_resv_q; + assign htw_dbg_tag4_clr_resv_terms = htw_tag4_clr_resv_terms; + assign htw_dbg_pte0_score_ptr_q = pte0_score_ptr_q; + assign htw_dbg_pte0_score_cl_offset_q = pte0_score_cl_offset_q; + assign htw_dbg_pte0_score_error_q = pte0_score_error_q; + assign htw_dbg_pte0_score_qwbeat_q = pte0_score_qwbeat_q; + assign htw_dbg_pte0_score_pending_q = pte0_score_pending_q; + assign htw_dbg_pte0_score_ibit_q = pte0_score_ibit_q; + assign htw_dbg_pte0_score_dataval_q = pte0_score_dataval_q; + assign htw_dbg_pte0_reld_for_me_tm1 = pte0_reld_for_me_tm1; + assign htw_dbg_pte1_score_ptr_q = pte1_score_ptr_q; + assign htw_dbg_pte1_score_cl_offset_q = pte1_score_cl_offset_q; + assign htw_dbg_pte1_score_error_q = pte1_score_error_q; + assign htw_dbg_pte1_score_qwbeat_q = pte1_score_qwbeat_q; + assign htw_dbg_pte1_score_pending_q = pte1_score_pending_q; + assign htw_dbg_pte1_score_ibit_q = pte1_score_ibit_q; + assign htw_dbg_pte1_score_dataval_q = pte1_score_dataval_q; + assign htw_dbg_pte1_reld_for_me_tm1 = pte1_reld_for_me_tm1; + + // unused spare signal assignments + assign unused_dc[0] = |(lcb_delay_lclkr_dc[1:4]); + assign unused_dc[1] = |(lcb_mpw1_dc_b[1:4]); + assign unused_dc[2] = pc_func_sl_force; + assign unused_dc[3] = pc_func_sl_thold_0_b; + assign unused_dc[4] = tc_scan_dis_dc_b; + assign unused_dc[5] = tc_scan_diag_dc; + assign unused_dc[6] = tc_lbist_en_dc; + assign unused_dc[7] = |(tlb_htw_req_tag[104:105]); + assign unused_dc[8] = htw_tag3_q[70]; + assign unused_dc[9] = htw_tag3_q[73]; + assign unused_dc[10] = |(htw_tag3_q[82:85]); + assign unused_dc[11] = htw_tag3_q[87]; + assign unused_dc[12] = |(htw_tag3_q[98:103]); + assign unused_dc[13] = |(htw_tag3_q[106:`TLB_TAG_WIDTH - 1]); + assign unused_dc[14] = pte0_reld_enable_lo_tp2 | pte0_reld_enable_hi_tp2; + assign unused_dc[15] = pte1_reld_enable_lo_tp2 | pte1_reld_enable_hi_tp2; + assign unused_dc[16:19] = {tlb_htw_req0_pending_q, tlb_htw_req1_pending_q, tlb_htw_req2_pending_q, tlb_htw_req3_pending_q}; + assign unused_dc[20:21] = htw_lsuptr_alt_d; + //--------------------------------------------------------------------- + // Latches + //--------------------------------------------------------------------- + // tlb request valid latches + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_htw_req0_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_htw_req0_valid_offset]), + .scout(sov_0[tlb_htw_req0_valid_offset]), + .din(tlb_htw_req0_valid_d), + .dout(tlb_htw_req0_valid_q) + ); + // tlb request pending latches.. this req is loaded into a pte machine + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_htw_req0_pending_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_htw_req0_pending_offset]), + .scout(sov_0[tlb_htw_req0_pending_offset]), + .din(tlb_htw_req0_pending_d), + .dout(tlb_htw_req0_pending_q) + ); + // tlb request tag latches + + tri_rlmreg_p #(.WIDTH(`TLB_TAG_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_htw_req0_tag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_htw_req0_tag_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_htw_req0_tag_offset:tlb_htw_req0_tag_offset + `TLB_TAG_WIDTH - 1]), + .scout(sov_0[tlb_htw_req0_tag_offset:tlb_htw_req0_tag_offset + `TLB_TAG_WIDTH - 1]), + .din(tlb_htw_req0_tag_d), + .dout(tlb_htw_req0_tag_q) + ); + // tlb request tag latches + + tri_rlmreg_p #(.WIDTH((`TLB_WAY_WIDTH-1-`TLB_WORD_WIDTH+1)), .INIT(0), .NEEDS_SRESET(1)) tlb_htw_req0_way_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[24 + 0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_htw_req0_way_offset:tlb_htw_req0_way_offset + (`TLB_WAY_WIDTH-1-`TLB_WORD_WIDTH+1) - 1]), + .scout(sov_0[tlb_htw_req0_way_offset:tlb_htw_req0_way_offset + (`TLB_WAY_WIDTH-1-`TLB_WORD_WIDTH+1) - 1]), + .din(tlb_htw_req0_way_d), + .dout(tlb_htw_req0_way_q) + ); + // tlb request valid latches + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_htw_req1_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_htw_req1_valid_offset]), + .scout(sov_0[tlb_htw_req1_valid_offset]), + .din(tlb_htw_req1_valid_d), + .dout(tlb_htw_req1_valid_q) + ); + // tlb request pending latches.. this req is loaded into a pte machine + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_htw_req1_pending_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_htw_req1_pending_offset]), + .scout(sov_0[tlb_htw_req1_pending_offset]), + .din(tlb_htw_req1_pending_d), + .dout(tlb_htw_req1_pending_q) + ); + // tlb request tag latches + + tri_rlmreg_p #(.WIDTH(`TLB_TAG_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_htw_req1_tag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_htw_req1_tag_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_htw_req1_tag_offset:tlb_htw_req1_tag_offset + `TLB_TAG_WIDTH - 1]), + .scout(sov_0[tlb_htw_req1_tag_offset:tlb_htw_req1_tag_offset + `TLB_TAG_WIDTH - 1]), + .din(tlb_htw_req1_tag_d), + .dout(tlb_htw_req1_tag_q) + ); + // tlb request tag latches + + tri_rlmreg_p #(.WIDTH((`TLB_WAY_WIDTH-1-`TLB_WORD_WIDTH+1)), .INIT(0), .NEEDS_SRESET(1)) tlb_htw_req1_way_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[24 + 1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_htw_req1_way_offset:tlb_htw_req1_way_offset + (`TLB_WAY_WIDTH-1-`TLB_WORD_WIDTH+1) - 1]), + .scout(sov_0[tlb_htw_req1_way_offset:tlb_htw_req1_way_offset + (`TLB_WAY_WIDTH-1-`TLB_WORD_WIDTH+1) - 1]), + .din(tlb_htw_req1_way_d), + .dout(tlb_htw_req1_way_q) + ); + // tlb request valid latches + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_htw_req2_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_htw_req2_valid_offset]), + .scout(sov_0[tlb_htw_req2_valid_offset]), + .din(tlb_htw_req2_valid_d), + .dout(tlb_htw_req2_valid_q) + ); + // tlb request pending latches.. this req is loaded into a pte machine + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_htw_req2_pending_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_htw_req2_pending_offset]), + .scout(sov_0[tlb_htw_req2_pending_offset]), + .din(tlb_htw_req2_pending_d), + .dout(tlb_htw_req2_pending_q) + ); + // tlb request tag latches + + tri_rlmreg_p #(.WIDTH(`TLB_TAG_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_htw_req2_tag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_htw_req2_tag_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_htw_req2_tag_offset:tlb_htw_req2_tag_offset + `TLB_TAG_WIDTH - 1]), + .scout(sov_0[tlb_htw_req2_tag_offset:tlb_htw_req2_tag_offset + `TLB_TAG_WIDTH - 1]), + .din(tlb_htw_req2_tag_d), + .dout(tlb_htw_req2_tag_q) + ); + // tlb request tag latches + + tri_rlmreg_p #(.WIDTH((`TLB_WAY_WIDTH-1-`TLB_WORD_WIDTH+1)), .INIT(0), .NEEDS_SRESET(1)) tlb_htw_req2_way_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[24 + 2]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_htw_req2_way_offset:tlb_htw_req2_way_offset + (`TLB_WAY_WIDTH-1-`TLB_WORD_WIDTH+1) - 1]), + .scout(sov_0[tlb_htw_req2_way_offset:tlb_htw_req2_way_offset + (`TLB_WAY_WIDTH-1-`TLB_WORD_WIDTH+1) - 1]), + .din(tlb_htw_req2_way_d), + .dout(tlb_htw_req2_way_q) + ); + // tlb request valid latches + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_htw_req3_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_htw_req3_valid_offset]), + .scout(sov_0[tlb_htw_req3_valid_offset]), + .din(tlb_htw_req3_valid_d), + .dout(tlb_htw_req3_valid_q) + ); + // tlb request pending latches.. this req is loaded into a pte machine + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_htw_req3_pending_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_htw_req3_pending_offset]), + .scout(sov_0[tlb_htw_req3_pending_offset]), + .din(tlb_htw_req3_pending_d), + .dout(tlb_htw_req3_pending_q) + ); + // tlb request tag latches + + tri_rlmreg_p #(.WIDTH(`TLB_TAG_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_htw_req3_tag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_htw_req3_tag_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_htw_req3_tag_offset:tlb_htw_req3_tag_offset + `TLB_TAG_WIDTH - 1]), + .scout(sov_0[tlb_htw_req3_tag_offset:tlb_htw_req3_tag_offset + `TLB_TAG_WIDTH - 1]), + .din(tlb_htw_req3_tag_d), + .dout(tlb_htw_req3_tag_q) + ); + // tlb request tag latches + + tri_rlmreg_p #(.WIDTH((`TLB_WAY_WIDTH-1-`TLB_WORD_WIDTH+1)), .INIT(0), .NEEDS_SRESET(1)) tlb_htw_req3_way_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[24 + 3]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_htw_req3_way_offset:tlb_htw_req3_way_offset + (`TLB_WAY_WIDTH-1-`TLB_WORD_WIDTH+1) - 1]), + .scout(sov_0[tlb_htw_req3_way_offset:tlb_htw_req3_way_offset + (`TLB_WAY_WIDTH-1-`TLB_WORD_WIDTH+1) - 1]), + .din(tlb_htw_req3_way_d), + .dout(tlb_htw_req3_way_q) + ); + + tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) spare_a_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spare_a_offset:spare_a_offset + 16 - 1]), + .scout(sov_0[spare_a_offset:spare_a_offset + 16 - 1]), + .din(spare_a_q), + .dout(spare_a_q) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) htw_seq_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[htw_seq_offset:htw_seq_offset + 2 - 1]), + .scout(sov_1[htw_seq_offset:htw_seq_offset + 2 - 1]), + .din(htw_seq_d[0:`HTW_SEQ_WIDTH - 1]), + .dout(htw_seq_q[0:`HTW_SEQ_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) htw_inptr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[htw_inptr_offset:htw_inptr_offset + 2 - 1]), + .scout(sov_1[htw_inptr_offset:htw_inptr_offset + 2 - 1]), + .din(htw_inptr_d), + .dout(htw_inptr_q) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) htw_lsuptr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[htw_lsuptr_offset:htw_lsuptr_offset + 2 - 1]), + .scout(sov_1[htw_lsuptr_offset:htw_lsuptr_offset + 2 - 1]), + .din(htw_lsuptr_d), + .dout(htw_lsuptr_q) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) htw_lsu_ttype_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(htw_lsu_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[htw_lsu_ttype_offset:htw_lsu_ttype_offset + 2 - 1]), + .scout(sov_1[htw_lsu_ttype_offset:htw_lsu_ttype_offset + 2 - 1]), + .din(htw_lsu_ttype_d), + .dout(htw_lsu_ttype_q) + ); + + tri_rlmreg_p #(.WIDTH(`THDID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) htw_lsu_thdid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(htw_lsu_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[htw_lsu_thdid_offset:htw_lsu_thdid_offset + `THDID_WIDTH - 1]), + .scout(sov_1[htw_lsu_thdid_offset:htw_lsu_thdid_offset + `THDID_WIDTH - 1]), + .din(htw_lsu_thdid_d), + .dout(htw_lsu_thdid_q) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) htw_lsu_wimge_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(htw_lsu_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[htw_lsu_wimge_offset:htw_lsu_wimge_offset + 5 - 1]), + .scout(sov_1[htw_lsu_wimge_offset:htw_lsu_wimge_offset + 5 - 1]), + .din(htw_lsu_wimge_d), + .dout(htw_lsu_wimge_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) htw_lsu_u_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(htw_lsu_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[htw_lsu_u_offset:htw_lsu_u_offset + 4 - 1]), + .scout(sov_1[htw_lsu_u_offset:htw_lsu_u_offset + 4 - 1]), + .din(htw_lsu_u_d), + .dout(htw_lsu_u_q) + ); + + tri_rlmreg_p #(.WIDTH(`REAL_ADDR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) htw_lsu_addr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(htw_lsu_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[htw_lsu_addr_offset:htw_lsu_addr_offset + `REAL_ADDR_WIDTH - 1]), + .scout(sov_1[htw_lsu_addr_offset:htw_lsu_addr_offset + `REAL_ADDR_WIDTH - 1]), + .din(htw_lsu_addr_d), + .dout(htw_lsu_addr_q) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) pte0_seq_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[pte0_seq_offset:pte0_seq_offset + 3 - 1]), + .scout(sov_1[pte0_seq_offset:pte0_seq_offset + 3 - 1]), + .din(pte0_seq_d), + .dout(pte0_seq_q) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) pte0_score_ptr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pte0_score_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[pte0_score_ptr_offset:pte0_score_ptr_offset + 2 - 1]), + .scout(sov_1[pte0_score_ptr_offset:pte0_score_ptr_offset + 2 - 1]), + .din(pte0_score_ptr_d), + .dout(pte0_score_ptr_q) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) pte0_score_cl_offset_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pte0_score_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[pte0_score_cl_offset_offset:pte0_score_cl_offset_offset + 3 - 1]), + .scout(sov_1[pte0_score_cl_offset_offset:pte0_score_cl_offset_offset + 3 - 1]), + .din(pte0_score_cl_offset_d), + .dout(pte0_score_cl_offset_q) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) pte0_score_error_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pte0_score_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[pte0_score_error_offset:pte0_score_error_offset + 3 - 1]), + .scout(sov_1[pte0_score_error_offset:pte0_score_error_offset + 3 - 1]), + .din(pte0_score_error_d), + .dout(pte0_score_error_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) pte0_score_qwbeat_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pte0_score_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[pte0_score_qwbeat_offset:pte0_score_qwbeat_offset + 4 - 1]), + .scout(sov_1[pte0_score_qwbeat_offset:pte0_score_qwbeat_offset + 4 - 1]), + .din(pte0_score_qwbeat_d), + .dout(pte0_score_qwbeat_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pte0_score_ibit_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pte0_score_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[pte0_score_ibit_offset]), + .scout(sov_1[pte0_score_ibit_offset]), + .din(pte0_score_ibit_d), + .dout(pte0_score_ibit_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pte0_score_pending_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pte0_score_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[pte0_score_pending_offset]), + .scout(sov_1[pte0_score_pending_offset]), + .din(pte0_score_pending_d), + .dout(pte0_score_pending_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pte0_score_dataval_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pte0_score_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[pte0_score_dataval_offset]), + .scout(sov_1[pte0_score_dataval_offset]), + .din(pte0_score_dataval_d), + .dout(pte0_score_dataval_q) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) pte1_seq_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[pte1_seq_offset:pte1_seq_offset + 3 - 1]), + .scout(sov_1[pte1_seq_offset:pte1_seq_offset + 3 - 1]), + .din(pte1_seq_d), + .dout(pte1_seq_q) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) pte1_score_ptr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pte1_score_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[pte1_score_ptr_offset:pte1_score_ptr_offset + 2 - 1]), + .scout(sov_1[pte1_score_ptr_offset:pte1_score_ptr_offset + 2 - 1]), + .din(pte1_score_ptr_d), + .dout(pte1_score_ptr_q) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) pte1_score_cl_offset_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pte1_score_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[pte1_score_cl_offset_offset:pte1_score_cl_offset_offset + 3 - 1]), + .scout(sov_1[pte1_score_cl_offset_offset:pte1_score_cl_offset_offset + 3 - 1]), + .din(pte1_score_cl_offset_d), + .dout(pte1_score_cl_offset_q) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) pte1_score_error_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pte1_score_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[pte1_score_error_offset:pte1_score_error_offset + 3 - 1]), + .scout(sov_1[pte1_score_error_offset:pte1_score_error_offset + 3 - 1]), + .din(pte1_score_error_d), + .dout(pte1_score_error_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) pte1_score_qwbeat_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pte1_score_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[pte1_score_qwbeat_offset:pte1_score_qwbeat_offset + 4 - 1]), + .scout(sov_1[pte1_score_qwbeat_offset:pte1_score_qwbeat_offset + 4 - 1]), + .din(pte1_score_qwbeat_d), + .dout(pte1_score_qwbeat_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pte1_score_ibit_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pte1_score_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[pte1_score_ibit_offset]), + .scout(sov_1[pte1_score_ibit_offset]), + .din(pte1_score_ibit_d), + .dout(pte1_score_ibit_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pte1_score_pending_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pte1_score_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[pte1_score_pending_offset]), + .scout(sov_1[pte1_score_pending_offset]), + .din(pte1_score_pending_d), + .dout(pte1_score_pending_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pte1_score_dataval_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pte1_score_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[pte1_score_dataval_offset]), + .scout(sov_1[pte1_score_dataval_offset]), + .din(pte1_score_dataval_d), + .dout(pte1_score_dataval_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pte_load_ptr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[pte_load_ptr_offset]), + .scout(sov_1[pte_load_ptr_offset]), + .din(pte_load_ptr_d), + .dout(pte_load_ptr_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ptereload_ptr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[ptereload_ptr_offset]), + .scout(sov_1[ptereload_ptr_offset]), + .din(ptereload_ptr_d), + .dout(ptereload_ptr_q) + ); + // t minus 1 phase latches + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) reld_core_tag_tm1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(reld_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[reld_core_tag_tm1_offset:reld_core_tag_tm1_offset + 5 - 1]), + .scout(sov_1[reld_core_tag_tm1_offset:reld_core_tag_tm1_offset + 5 - 1]), + .din(reld_core_tag_tm1_d), + .dout(reld_core_tag_tm1_q) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) reld_qw_tm1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(reld_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[reld_qw_tm1_offset:reld_qw_tm1_offset + 2 - 1]), + .scout(sov_1[reld_qw_tm1_offset:reld_qw_tm1_offset + 2 - 1]), + .din(reld_qw_tm1_d), + .dout(reld_qw_tm1_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) reld_crit_qw_tm1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(reld_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[reld_crit_qw_tm1_offset]), + .scout(sov_1[reld_crit_qw_tm1_offset]), + .din(reld_crit_qw_tm1_d), + .dout(reld_crit_qw_tm1_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) reld_ditc_tm1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(reld_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[reld_ditc_tm1_offset]), + .scout(sov_1[reld_ditc_tm1_offset]), + .din(reld_ditc_tm1_d), + .dout(reld_ditc_tm1_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) reld_data_vld_tm1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(reld_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[reld_data_vld_tm1_offset]), + .scout(sov_1[reld_data_vld_tm1_offset]), + .din(reld_data_vld_tm1_d), + .dout(reld_data_vld_tm1_q) + ); + // t phase latches + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) reld_core_tag_t_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(reld_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[reld_core_tag_t_offset:reld_core_tag_t_offset + 5 - 1]), + .scout(sov_1[reld_core_tag_t_offset:reld_core_tag_t_offset + 5 - 1]), + .din(reld_core_tag_t_d), + .dout(reld_core_tag_t_q) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) reld_qw_t_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(reld_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[reld_qw_t_offset:reld_qw_t_offset + 2 - 1]), + .scout(sov_1[reld_qw_t_offset:reld_qw_t_offset + 2 - 1]), + .din(reld_qw_t_d), + .dout(reld_qw_t_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) reld_crit_qw_t_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(reld_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[reld_crit_qw_t_offset]), + .scout(sov_1[reld_crit_qw_t_offset]), + .din(reld_crit_qw_t_d), + .dout(reld_crit_qw_t_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) reld_ditc_t_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(reld_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[reld_ditc_t_offset]), + .scout(sov_1[reld_ditc_t_offset]), + .din(reld_ditc_t_d), + .dout(reld_ditc_t_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) reld_data_vld_t_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(reld_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[reld_data_vld_t_offset]), + .scout(sov_1[reld_data_vld_t_offset]), + .din(reld_data_vld_t_d), + .dout(reld_data_vld_t_q) + ); + // t plus 1 phase latches + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) reld_core_tag_tp1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(reld_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[reld_core_tag_tp1_offset:reld_core_tag_tp1_offset + 5 - 1]), + .scout(sov_1[reld_core_tag_tp1_offset:reld_core_tag_tp1_offset + 5 - 1]), + .din(reld_core_tag_tp1_d), + .dout(reld_core_tag_tp1_q) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) reld_qw_tp1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(reld_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[reld_qw_tp1_offset:reld_qw_tp1_offset + 2 - 1]), + .scout(sov_1[reld_qw_tp1_offset:reld_qw_tp1_offset + 2 - 1]), + .din(reld_qw_tp1_d), + .dout(reld_qw_tp1_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) reld_crit_qw_tp1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(reld_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[reld_crit_qw_tp1_offset]), + .scout(sov_1[reld_crit_qw_tp1_offset]), + .din(reld_crit_qw_tp1_d), + .dout(reld_crit_qw_tp1_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) reld_ditc_tp1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(reld_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[reld_ditc_tp1_offset]), + .scout(sov_1[reld_ditc_tp1_offset]), + .din(reld_ditc_tp1_d), + .dout(reld_ditc_tp1_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) reld_data_vld_tp1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(reld_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[reld_data_vld_tp1_offset]), + .scout(sov_1[reld_data_vld_tp1_offset]), + .din(reld_data_vld_tp1_d), + .dout(reld_data_vld_tp1_q) + ); + + tri_rlmreg_p #(.WIDTH(128), .INIT(0), .NEEDS_SRESET(1)) reld_data_tp1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(reld_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[reld_data_tp1_offset:reld_data_tp1_offset + 128 - 1]), + .scout(sov_1[reld_data_tp1_offset:reld_data_tp1_offset + 128 - 1]), + .din(reld_data_tp1_d), + .dout(reld_data_tp1_q) + ); + // t plus 2 phase latches + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) reld_core_tag_tp2_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(reld_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[reld_core_tag_tp2_offset:reld_core_tag_tp2_offset + 5 - 1]), + .scout(sov_1[reld_core_tag_tp2_offset:reld_core_tag_tp2_offset + 5 - 1]), + .din(reld_core_tag_tp2_d), + .dout(reld_core_tag_tp2_q) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) reld_qw_tp2_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(reld_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[reld_qw_tp2_offset:reld_qw_tp2_offset + 2 - 1]), + .scout(sov_1[reld_qw_tp2_offset:reld_qw_tp2_offset + 2 - 1]), + .din(reld_qw_tp2_d), + .dout(reld_qw_tp2_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) reld_crit_qw_tp2_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(reld_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[reld_crit_qw_tp2_offset]), + .scout(sov_1[reld_crit_qw_tp2_offset]), + .din(reld_crit_qw_tp2_d), + .dout(reld_crit_qw_tp2_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) reld_ditc_tp2_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(reld_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[reld_ditc_tp2_offset]), + .scout(sov_1[reld_ditc_tp2_offset]), + .din(reld_ditc_tp2_d), + .dout(reld_ditc_tp2_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) reld_data_vld_tp2_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(reld_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[reld_data_vld_tp2_offset]), + .scout(sov_1[reld_data_vld_tp2_offset]), + .din(reld_data_vld_tp2_d), + .dout(reld_data_vld_tp2_q) + ); + + tri_rlmreg_p #(.WIDTH(128), .INIT(0), .NEEDS_SRESET(1)) reld_data_tp2_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(reld_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[reld_data_tp2_offset:reld_data_tp2_offset + 128 - 1]), + .scout(sov_1[reld_data_tp2_offset:reld_data_tp2_offset + 128 - 1]), + .din(reld_data_tp2_d), + .dout(reld_data_tp2_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) reld_ecc_err_tp2_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(reld_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[reld_ecc_err_tp2_offset]), + .scout(sov_1[reld_ecc_err_tp2_offset]), + .din(reld_ecc_err_tp2_d), + .dout(reld_ecc_err_tp2_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) reld_ecc_err_ue_tp2_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(reld_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[reld_ecc_err_ue_tp2_offset]), + .scout(sov_1[reld_ecc_err_ue_tp2_offset]), + .din(reld_ecc_err_ue_tp2_d), + .dout(reld_ecc_err_ue_tp2_q) + ); + // t plus 3 phase + + tri_rlmreg_p #(.WIDTH(64), .INIT(0), .NEEDS_SRESET(1)) pte0_reld_data_tp3_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pte0_reld_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[pte0_reld_data_tp3_offset:pte0_reld_data_tp3_offset + 64 - 1]), + .scout(sov_1[pte0_reld_data_tp3_offset:pte0_reld_data_tp3_offset + 64 - 1]), + .din(pte0_reld_data_tp3_d), + .dout(pte0_reld_data_tp3_q) + ); + + tri_rlmreg_p #(.WIDTH(64), .INIT(0), .NEEDS_SRESET(1)) pte1_reld_data_tp3_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pte1_reld_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[pte1_reld_data_tp3_offset:pte1_reld_data_tp3_offset + 64 - 1]), + .scout(sov_1[pte1_reld_data_tp3_offset:pte1_reld_data_tp3_offset + 64 - 1]), + .din(pte1_reld_data_tp3_d), + .dout(pte1_reld_data_tp3_q) + ); + + tri_rlmreg_p #(.WIDTH(`TLB_TAG_WIDTH), .INIT(0), .NEEDS_SRESET(1)) htw_tag3_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[28]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[htw_tag3_offset:htw_tag3_offset + `TLB_TAG_WIDTH - 1]), + .scout(sov_1[htw_tag3_offset:htw_tag3_offset + `TLB_TAG_WIDTH - 1]), + .din(htw_tag3_d), + .dout(htw_tag3_q) + ); + + tri_rlmreg_p #(.WIDTH(`THDID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) htw_tag4_clr_resv_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[28]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[htw_tag4_clr_resv_offset:htw_tag4_clr_resv_offset + `THDID_WIDTH - 1]), + .scout(sov_1[htw_tag4_clr_resv_offset:htw_tag4_clr_resv_offset + `THDID_WIDTH - 1]), + .din(htw_tag4_clr_resv_d), + .dout(htw_tag4_clr_resv_q) + ); + + tri_rlmreg_p #(.WIDTH(`THDID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) htw_tag5_clr_resv_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[28]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[htw_tag5_clr_resv_offset:htw_tag5_clr_resv_offset + `THDID_WIDTH - 1]), + .scout(sov_1[htw_tag5_clr_resv_offset:htw_tag5_clr_resv_offset + `THDID_WIDTH - 1]), + .din(htw_tag5_clr_resv_d), + .dout(htw_tag5_clr_resv_q) + ); + + tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) spare_b_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spare_b_offset:spare_b_offset + 16 - 1]), + .scout(sov_1[spare_b_offset:spare_b_offset + 16 - 1]), + .din(spare_b_q), + .dout(spare_b_q) + ); + //------------------------------------------------ + // thold/sg latches + //------------------------------------------------ + + tri_plat #(.WIDTH(3)) perv_2to1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ccflush_dc), + .din( {pc_func_sl_thold_2, pc_func_slp_sl_thold_2, pc_sg_2} ), + .q( {pc_func_sl_thold_1, pc_func_slp_sl_thold_1, pc_sg_1} ) + ); + + tri_plat #(.WIDTH(3)) perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ccflush_dc), + .din( {pc_func_sl_thold_1, pc_func_slp_sl_thold_1, pc_sg_1} ), + .q( {pc_func_sl_thold_0, pc_func_slp_sl_thold_0, pc_sg_0} ) + ); + + tri_lcbor perv_lcbor_func_sl( + .clkoff_b(lcb_clkoff_dc_b), + .thold(pc_func_sl_thold_0), + .sg(pc_sg_0), + .act_dis(lcb_act_dis_dc), + .force_t(pc_func_sl_force), + .thold_b(pc_func_sl_thold_0_b) + ); + + tri_lcbor perv_lcbor_func_slp_sl( + .clkoff_b(lcb_clkoff_dc_b), + .thold(pc_func_slp_sl_thold_0), + .sg(pc_sg_0), + .act_dis(lcb_act_dis_dc), + .force_t(pc_func_slp_sl_force), + .thold_b(pc_func_slp_sl_thold_0_b) + ); + + + //--------------------------------------------------------------------- + // Scan + //--------------------------------------------------------------------- + assign siv_0[0:scan_right_0] = {sov_0[1:scan_right_0], ac_func_scan_in[0]}; + assign ac_func_scan_out[0] = sov_0[0]; + assign siv_1[0:scan_right_1] = {sov_1[1:scan_right_1], ac_func_scan_in[1]}; + assign ac_func_scan_out[1] = sov_1[0]; + + function Eq; + input a, b; + reg result; + begin + if (a == b) + begin + result = 1'b1; + end + else + begin + result = 1'b0; + end + Eq = result; + end + endfunction + +endmodule diff --git a/dev/verilog/work/mmq_inval.v b/dev/verilog/work/mmq_inval.v new file mode 100755 index 0000000..20a2011 --- /dev/null +++ b/dev/verilog/work/mmq_inval.v @@ -0,0 +1,3909 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +// VHDL 1076 Macro Expander C version 07/11/00 +// job was run on Tue Apr 19 13:45:22 2011 + +//INCLUDES : FILE mmu_config.cfg +//******************************************************************** +//* TITLE: Memory Management Unit Invalidate Control Logic +//********************************************************************* + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" +`include "mmu_a2o.vh" +`define MMQ_INVAL_TTYPE_WIDTH 6 +`define MMQ_INVAL_STATE_WIDTH 2 +`define INV_SEQ_WIDTH 6 +`define BUS_SNOOP_SEQ_WIDTH 2 + + +module mmq_inval( + + inout vdd, + inout gnd, + (* pin_data ="PIN_FUNCTION=/G_CLK/" *) + input [0:`NCLK_WIDTH-1] nclk, + + input tc_ccflush_dc, + input tc_scan_dis_dc_b, + input tc_scan_diag_dc, + input tc_lbist_en_dc, + + input lcb_d_mode_dc, + input lcb_clkoff_dc_b, + input lcb_act_dis_dc, + input [0:4] lcb_mpw1_dc_b, + input lcb_mpw2_dc_b, + input [0:4] lcb_delay_lclkr_dc, + +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + input ac_func_scan_in, +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + output ac_func_scan_out, + + input pc_sg_2, + input pc_func_sl_thold_2, + input pc_func_slp_sl_thold_2, + input pc_func_slp_nsl_thold_2, + input pc_fce_2, + input mmucr2_act_override, + input xu_mm_ccr2_notlb, + output [1:12] xu_mm_ccr2_notlb_b, + + output mm_iu_ierat_snoop_coming, + output mm_iu_ierat_snoop_val, + output [0:25] mm_iu_ierat_snoop_attr, + output [52-`EPN_WIDTH:51] mm_iu_ierat_snoop_vpn, + input iu_mm_ierat_snoop_ack, + + output mm_xu_derat_snoop_coming, + output mm_xu_derat_snoop_val, + output [0:25] mm_xu_derat_snoop_attr, + output [52-`EPN_WIDTH:51] mm_xu_derat_snoop_vpn, + input xu_mm_derat_snoop_ack, + output tlb_snoop_coming, + output tlb_snoop_val, + output [0:34] tlb_snoop_attr, + output [52-`EPN_WIDTH:51] tlb_snoop_vpn, + input tlb_snoop_ack, + input an_ac_back_inv, + input an_ac_back_inv_target, + input an_ac_back_inv_local, + input an_ac_back_inv_lbit, + input an_ac_back_inv_gs, + input an_ac_back_inv_ind, + input [64-`REAL_ADDR_WIDTH:63] an_ac_back_inv_addr, + input [0:`LPID_WIDTH-1] an_ac_back_inv_lpar_id, + input ac_an_power_managed, + output ac_an_back_inv_reject, + + input [0:`LPID_WIDTH-1] lpidr, + input mas5_0_sgs, + input [0:7] mas5_0_slpid, + input [0:13] mas6_0_spid, + input [0:3] mas6_0_isize, + input mas6_0_sind, + input mas6_0_sas, + input [2:19] mmucr0_0, +`ifdef MM_THREADS2 + input mas5_1_sgs, + input [0:7] mas5_1_slpid, + input [0:13] mas6_1_spid, + input [0:3] mas6_1_isize, + input mas6_1_sind, + input mas6_1_sas, + input [2:19] mmucr0_1, +`endif + input [12:19] mmucr1, + input [0:1] mmucr1_csinv, + input mmucsr0_tlb0fi, + output mmq_inval_tlb0fi_done, + + input [0:`MM_THREADS-1] xu_mm_rf1_val, + input xu_mm_rf1_is_tlbivax, + input xu_mm_rf1_is_tlbilx, + input xu_mm_rf1_is_erativax, + input xu_mm_rf1_is_eratilx, + input [0:`RS_IS_WIDTH-1] xu_mm_ex1_rs_is, + input xu_mm_ex1_is_isync, + input xu_mm_ex1_is_csync, + input [64-`RS_DATA_WIDTH:63] xu_mm_ex2_eff_addr, + input [0:`T_WIDTH-1] xu_mm_rf1_t, + input [0:`ITAG_SIZE_ENC-1] xu_mm_rf1_itag, + input [0:`MM_THREADS-1] xu_mm_msr_gs, + input [0:`MM_THREADS-1] xu_mm_msr_pr, + input [0:`MM_THREADS-1] xu_mm_spr_epcr_dgtmi, + output [0:`MM_THREADS-1] xu_mm_epcr_dgtmi, + input [0:`MM_THREADS-1] xu_rf1_flush, + input [0:`MM_THREADS-1] xu_ex1_flush, + input [0:`MM_THREADS-1] xu_ex2_flush, + input [0:`MM_THREADS-1] xu_ex3_flush, + input [0:`MM_THREADS-1] xu_ex4_flush, + input [0:`MM_THREADS-1] xu_ex5_flush, + input xu_mm_lmq_stq_empty, + input iu_mm_lmq_empty, + input [0:`MM_THREADS-1] tlb_ctl_barrier_done, + input [0:`MM_THREADS-1] tlb_ctl_ex2_flush_req, + input [0:`MM_THREADS-1] tlb_ctl_ex2_illeg_instr, + input [0:`MM_THREADS-1] tlb_ctl_ex6_illeg_instr, + input [0:`ITAG_SIZE_ENC-1] tlb_ctl_ex2_itag, + input [0:2] tlb_ctl_ord_type, + input [0:`ITAG_SIZE_ENC-1] tlb_tag4_itag, + input [0:`MM_THREADS-1] tlb_tag5_except, + input [0:`MM_THREADS-1] tlb_ctl_quiesce, + input [0:`MM_THREADS-1] tlb_req_quiesce, + output [0:`MM_THREADS-1] mm_xu_quiesce, + output [0:`MM_THREADS-1] mm_pc_tlb_req_quiesce, + output [0:`MM_THREADS-1] mm_pc_tlb_ctl_quiesce, + output [0:`MM_THREADS-1] mm_pc_htw_quiesce, + output [0:`MM_THREADS-1] mm_pc_inval_quiesce, + + output [0:`MM_THREADS-1] mm_xu_ex3_flush_req, + output [0:`MM_THREADS-1] mm_xu_illeg_instr, + output [0:`MM_THREADS-1] mm_xu_local_snoop_reject, + + input [0:`MM_THREADS-1] iu_mm_hold_ack, + output [0:`MM_THREADS-1] mm_iu_hold_req, + output [0:`MM_THREADS-1] mm_iu_hold_done, + output [0:`MM_THREADS-1] mm_iu_flush_req, + input [0:`MM_THREADS-1] iu_mm_bus_snoop_hold_ack, + output [0:`MM_THREADS-1] mm_iu_bus_snoop_hold_req, + output [0:`MM_THREADS-1] mm_iu_bus_snoop_hold_done, + output [0:`MM_THREADS-1] mm_iu_tlbi_complete, + + output [0:`MM_THREADS-1] mm_xu_ord_n_flush_req, + output [0:`MM_THREADS-1] mm_xu_ord_np1_flush_req, + output [0:`MM_THREADS-1] mm_xu_ord_read_done, + output [0:`MM_THREADS-1] mm_xu_ord_write_done, + output [0:`ITAG_SIZE_ENC-1] mm_xu_itag, + output mm_xu_ord_n_flush_req_ored, + output mm_xu_ord_np1_flush_req_ored, + output mm_xu_ord_read_done_ored, + output mm_xu_ord_write_done_ored, + output mm_xu_illeg_instr_ored, + output mm_pc_local_snoop_reject_ored, + + output inval_perf_tlbilx, + output inval_perf_tlbivax, + output inval_perf_tlbivax_snoop, + output inval_perf_tlb_flush, + + input htw_lsu_req_valid, + input [0:`MM_THREADS-1] htw_lsu_thdid, + input [0:1] htw_lsu_ttype, + input [0:4] htw_lsu_wimge, + input [0:3] htw_lsu_u, + input [64-`REAL_ADDR_WIDTH:63] htw_lsu_addr, + output htw_lsu_req_taken, + input [0:`MM_THREADS-1] htw_quiesce, + input tlbwe_back_inv_valid, + input [0:`MM_THREADS-1] tlbwe_back_inv_thdid, + input [52-`EPN_WIDTH:51] tlbwe_back_inv_addr, + input [0:34] tlbwe_back_inv_attr, + input tlb_tag5_write, + output tlbwe_back_inv_pending, + + output [0:`MM_THREADS-1] mm_xu_lsu_req, + output [0:1] mm_xu_lsu_ttype, + output [0:4] mm_xu_lsu_wimge, + output [0:3] mm_xu_lsu_u, + output [64-`REAL_ADDR_WIDTH:63] mm_xu_lsu_addr, + output [0:7] mm_xu_lsu_lpid, + output mm_xu_lsu_gs, + output mm_xu_lsu_ind, + output mm_xu_lsu_lbit, + input xu_mm_lsu_token, + + output [0:4] inval_dbg_seq_q, + output inval_dbg_seq_idle, + output inval_dbg_seq_snoop_inprogress, + output inval_dbg_seq_snoop_done, + output inval_dbg_seq_local_done, + output inval_dbg_seq_tlb0fi_done, + output inval_dbg_seq_tlbwe_snoop_done, + output inval_dbg_ex6_valid, + output [0:1] inval_dbg_ex6_thdid, // encoded + output [0:2] inval_dbg_ex6_ttype, // encoded + output inval_dbg_snoop_forme, + output inval_dbg_snoop_local_reject, + output [2:8] inval_dbg_an_ac_back_inv_q, + output [0:7] inval_dbg_an_ac_back_inv_lpar_id_q, + output [22:63] inval_dbg_an_ac_back_inv_addr_q, + output [0:2] inval_dbg_snoop_valid_q, + output [0:2] inval_dbg_snoop_ack_q, + output [0:34] inval_dbg_snoop_attr_q, + output [18:19] inval_dbg_snoop_attr_tlb_spec_q, + output [17:51] inval_dbg_snoop_vpn_q, + output [0:1] inval_dbg_lsu_tokens_q + +); + + + // chicken switches + // 0 - override lsu empty requirement for sending tlbivax + // 1 - override lsu empty requirement for processing incoming tlbivax snoop + // 2 - override wait for tlbwe back_inv erat snoop complete before issuing barrier_done, ord_read_done + // 3 - override i-fetch miss queue empty requirement for processing incoming tlbivax snoop + parameter MMQ_INVAL_CSWITCH_0TO3 = 0; + + parameter MMU_Mode_Value = 1'b0; + parameter ERAT_Mode_Value = 1'b1; + parameter [0:1] TlbSel_Tlb = 2'b00; + parameter [0:1] TlbSel_IErat = 2'b10; + parameter [0:1] TlbSel_DErat = 2'b11; + parameter [0:3] TLB_PgSize_1GB = 4'b1010; + parameter [0:3] TLB_PgSize_16MB = 4'b0111; + parameter [0:3] TLB_PgSize_1MB = 4'b0101; + parameter [0:3] TLB_PgSize_64KB = 4'b0011; + parameter [0:3] TLB_PgSize_4KB = 4'b0001; + parameter [0:3] TLB_PgSize_256MB = 4'b1001; + parameter [0:5] InvSeq_Idle = 6'b000000; + parameter [0:5] InvSeq_Stg1 = 6'b000001; + parameter [0:5] InvSeq_Stg2 = 6'b000011; + parameter [0:5] InvSeq_Stg3 = 6'b000010; + parameter [0:5] InvSeq_Stg4 = 6'b000110; + parameter [0:5] InvSeq_Stg5 = 6'b000100; + parameter [0:5] InvSeq_Stg6 = 6'b000101; + parameter [0:5] InvSeq_Stg7 = 6'b000111; + parameter [0:5] InvSeq_Stg8 = 6'b001000; + parameter [0:5] InvSeq_Stg9 = 6'b001001; + parameter [0:5] InvSeq_Stg10 = 6'b001011; + parameter [0:5] InvSeq_Stg11 = 6'b001010; + parameter [0:5] InvSeq_Stg12 = 6'b001110; + parameter [0:5] InvSeq_Stg13 = 6'b001100; + parameter [0:5] InvSeq_Stg14 = 6'b001101; + parameter [0:5] InvSeq_Stg15 = 6'b001111; + parameter [0:5] InvSeq_Stg16 = 6'b010000; + parameter [0:5] InvSeq_Stg17 = 6'b010001; + parameter [0:5] InvSeq_Stg18 = 6'b010011; + parameter [0:5] InvSeq_Stg19 = 6'b010010; + parameter [0:5] InvSeq_Stg20 = 6'b010110; + parameter [0:5] InvSeq_Stg21 = 6'b010100; + parameter [0:5] InvSeq_Stg22 = 6'b010101; + parameter [0:5] InvSeq_Stg23 = 6'b010111; + parameter [0:5] InvSeq_Stg24 = 6'b011000; + parameter [0:5] InvSeq_Stg25 = 6'b011001; + parameter [0:5] InvSeq_Stg26 = 6'b011011; + parameter [0:5] InvSeq_Stg27 = 6'b011010; + parameter [0:5] InvSeq_Stg28 = 6'b011110; + parameter [0:5] InvSeq_Stg29 = 6'b011100; + parameter [0:5] InvSeq_Stg30 = 6'b011101; + parameter [0:5] InvSeq_Stg31 = 6'b011111; + parameter [0:5] InvSeq_Stg32 = 6'b100000; + parameter [0:1] SnoopSeq_Idle = 2'b00; + parameter [0:1] SnoopSeq_Stg1 = 2'b01; + parameter [0:1] SnoopSeq_Stg2 = 2'b10; + parameter [0:1] SnoopSeq_Stg3 = 2'b11; + + // mmucr1 bits: 12:13-ICTID/ITTID,14:15-DCTID/DTTID,16:17-resv, TLBI_MSB/TLBI_REJ + parameter pos_ictid = 12; + parameter pos_ittid = 13; + parameter pos_dctid = 14; + parameter pos_dttid = 15; + parameter pos_tlbi_msb = 18; + parameter pos_tlbi_rej = 19; + parameter ex1_valid_offset = 0; + parameter ex1_ttype_offset = ex1_valid_offset + `MM_THREADS; + parameter ex1_state_offset = ex1_ttype_offset + `MMQ_INVAL_TTYPE_WIDTH - 2; + parameter ex1_t_offset = ex1_state_offset + `MMQ_INVAL_STATE_WIDTH; + parameter ex2_valid_offset = ex1_t_offset + `T_WIDTH; + parameter ex2_ttype_offset = ex2_valid_offset + `MM_THREADS; + parameter ex2_rs_is_offset = ex2_ttype_offset + `MMQ_INVAL_TTYPE_WIDTH; + parameter ex2_state_offset = ex2_rs_is_offset + `RS_IS_WIDTH; + parameter ex2_t_offset = ex2_state_offset + `MMQ_INVAL_STATE_WIDTH; + parameter ex3_valid_offset = ex2_t_offset + `T_WIDTH; + parameter ex3_ttype_offset = ex3_valid_offset + `MM_THREADS; + parameter ex3_rs_is_offset = ex3_ttype_offset + `MMQ_INVAL_TTYPE_WIDTH; + parameter ex3_state_offset = ex3_rs_is_offset + `RS_IS_WIDTH; + parameter ex3_t_offset = ex3_state_offset + `MMQ_INVAL_STATE_WIDTH; + parameter ex3_flush_req_offset = ex3_t_offset + `T_WIDTH; + parameter ex3_ea_offset = ex3_flush_req_offset + `MM_THREADS; + parameter ex4_valid_offset = ex3_ea_offset + `EPN_WIDTH + 12; + parameter ex4_ttype_offset = ex4_valid_offset + `MM_THREADS; + parameter ex4_rs_is_offset = ex4_ttype_offset + `MMQ_INVAL_TTYPE_WIDTH; + parameter ex4_state_offset = ex4_rs_is_offset + `RS_IS_WIDTH; + parameter ex4_t_offset = ex4_state_offset + `MMQ_INVAL_STATE_WIDTH; + parameter ex5_valid_offset = ex4_t_offset + `T_WIDTH; + parameter ex5_ttype_offset = ex5_valid_offset + `MM_THREADS; + parameter ex5_rs_is_offset = ex5_ttype_offset + `MMQ_INVAL_TTYPE_WIDTH; + parameter ex5_state_offset = ex5_rs_is_offset + `RS_IS_WIDTH; + parameter ex5_t_offset = ex5_state_offset + `MMQ_INVAL_STATE_WIDTH; + parameter ex6_valid_offset = ex5_t_offset + `T_WIDTH; + parameter ex6_ttype_offset = ex6_valid_offset + `MM_THREADS; + parameter ex6_isel_offset = ex6_ttype_offset + `MMQ_INVAL_TTYPE_WIDTH; + parameter ex6_size_offset = ex6_isel_offset + 3; + parameter ex6_gs_offset = ex6_size_offset + 4; + parameter ex6_ts_offset = ex6_gs_offset + 1; + parameter ex6_ind_offset = ex6_ts_offset + 1; + parameter ex6_pid_offset = ex6_ind_offset + 1; + parameter ex6_lpid_offset = ex6_pid_offset + `PID_WIDTH; + parameter ex1_itag_offset = ex6_lpid_offset + `LPID_WIDTH; + parameter ex2_itag_offset = ex1_itag_offset + `ITAG_SIZE_ENC; + parameter ex3_itag_offset = ex2_itag_offset + `ITAG_SIZE_ENC; + parameter ex4_itag_offset = ex3_itag_offset + `ITAG_SIZE_ENC; + parameter ex5_itag_offset = ex4_itag_offset + `ITAG_SIZE_ENC; + parameter ex6_itag_offset = ex5_itag_offset + `ITAG_SIZE_ENC; + parameter mm_xu_itag_offset = ex6_itag_offset + `ITAG_SIZE_ENC; + parameter ord_read_done_offset = mm_xu_itag_offset + `ITAG_SIZE_ENC; + parameter ord_write_done_offset = ord_read_done_offset + `MM_THREADS; + parameter ord_np1_flush_offset = ord_write_done_offset + `MM_THREADS; + parameter inv_seq_offset = ord_np1_flush_offset + `MM_THREADS; + parameter hold_req_offset = inv_seq_offset + `INV_SEQ_WIDTH; + parameter hold_ack_offset = hold_req_offset + `MM_THREADS; + parameter hold_done_offset = hold_ack_offset + `MM_THREADS; + parameter local_barrier_offset = hold_done_offset + `MM_THREADS; + parameter global_barrier_offset = local_barrier_offset + `MM_THREADS; + parameter ex3_illeg_instr_offset = global_barrier_offset + `MM_THREADS; + parameter ex4_illeg_instr_offset = ex3_illeg_instr_offset + `MM_THREADS; + parameter ex5_illeg_instr_offset = ex4_illeg_instr_offset + `MM_THREADS; + parameter ex6_illeg_instr_offset = ex5_illeg_instr_offset + `MM_THREADS; + parameter ex7_illeg_instr_offset = ex6_illeg_instr_offset + `MM_THREADS; + parameter ex3_ivax_lpid_reject_offset = ex7_illeg_instr_offset + `MM_THREADS; + parameter ex4_ivax_lpid_reject_offset = ex3_ivax_lpid_reject_offset + `MM_THREADS; + parameter bus_snoop_seq_offset = ex4_ivax_lpid_reject_offset + `MM_THREADS; + parameter bus_snoop_hold_req_offset = bus_snoop_seq_offset + `BUS_SNOOP_SEQ_WIDTH; + parameter bus_snoop_hold_ack_offset = bus_snoop_hold_req_offset + `MM_THREADS; + parameter bus_snoop_hold_done_offset = bus_snoop_hold_ack_offset + `MM_THREADS; + parameter tlbi_complete_offset = bus_snoop_hold_done_offset + `MM_THREADS; + parameter iu_flush_req_offset = tlbi_complete_offset + `MM_THREADS; + parameter local_snoop_reject_offset = iu_flush_req_offset + `MM_THREADS; + parameter snoop_valid_offset = local_snoop_reject_offset + `MM_THREADS; + parameter snoop_attr_offset = snoop_valid_offset + 3; + parameter snoop_vpn_offset = snoop_attr_offset + 35; + parameter snoop_attr_clone_offset = snoop_vpn_offset + `EPN_WIDTH; + parameter snoop_attr_tlb_spec_offset = snoop_attr_clone_offset + 26; + parameter snoop_vpn_clone_offset = snoop_attr_tlb_spec_offset + 2; + parameter snoop_ack_offset = snoop_vpn_clone_offset + `EPN_WIDTH; + parameter snoop_coming_offset = snoop_ack_offset + 3; + parameter mm_xu_quiesce_offset = snoop_coming_offset + 5; + parameter mm_pc_quiesce_offset = mm_xu_quiesce_offset + `MM_THREADS; + parameter inv_seq_inprogress_offset = mm_pc_quiesce_offset + 4*`MM_THREADS; + parameter xu_mm_ccr2_notlb_offset = inv_seq_inprogress_offset + 6; + parameter spare_offset = xu_mm_ccr2_notlb_offset + 13; + parameter an_ac_back_inv_offset = spare_offset + 16; + parameter an_ac_back_inv_addr_offset = an_ac_back_inv_offset + 9; + parameter an_ac_back_inv_lpar_id_offset = an_ac_back_inv_addr_offset + `REAL_ADDR_WIDTH; + parameter lsu_tokens_offset = an_ac_back_inv_lpar_id_offset + `LPID_WIDTH; + parameter lsu_req_offset = lsu_tokens_offset + 2; + parameter lsu_ttype_offset = lsu_req_offset + `MM_THREADS; + parameter lsu_ubits_offset = lsu_ttype_offset + 2; + parameter lsu_wimge_offset = lsu_ubits_offset + 4; + parameter lsu_addr_offset = lsu_wimge_offset + 5; + parameter lsu_lpid_offset = lsu_addr_offset + `REAL_ADDR_WIDTH; + parameter lsu_ind_offset = lsu_lpid_offset + `LPID_WIDTH; + parameter lsu_gs_offset = lsu_ind_offset + 1; + parameter lsu_lbit_offset = lsu_gs_offset + 1; + parameter power_managed_offset = lsu_lbit_offset + 1; + parameter cswitch_offset = power_managed_offset + 4; + parameter tlbwe_back_inv_offset = cswitch_offset + 4; + parameter tlbwe_back_inv_addr_offset = tlbwe_back_inv_offset + `MM_THREADS + 2; + parameter tlbwe_back_inv_attr_offset = tlbwe_back_inv_addr_offset + `EPN_WIDTH; + parameter scan_right = tlbwe_back_inv_attr_offset + 35 - 1; + +`ifdef MM_THREADS2 + parameter BUGSP_MM_THREADS = 2; +`else + parameter BUGSP_MM_THREADS = 1; +`endif + + wire [0:`MM_THREADS-1] ex1_valid_d; + wire [0:`MM_THREADS-1] ex1_valid_q; + wire [0:`MMQ_INVAL_TTYPE_WIDTH-3] ex1_ttype_d; + wire [0:`MMQ_INVAL_TTYPE_WIDTH-3] ex1_ttype_q; + wire [0:`MMQ_INVAL_STATE_WIDTH-1] ex1_state_d; + wire [0:`MMQ_INVAL_STATE_WIDTH-1] ex1_state_q; + wire [0:`T_WIDTH-1] ex1_t_d; + wire [0:`T_WIDTH-1] ex1_t_q; + wire [0:`MM_THREADS-1] ex2_valid_d; + wire [0:`MM_THREADS-1] ex2_valid_q; + wire [0:`MMQ_INVAL_TTYPE_WIDTH-1] ex2_ttype_d; + wire [0:`MMQ_INVAL_TTYPE_WIDTH-1] ex2_ttype_q; + wire [0:`RS_IS_WIDTH-1] ex2_rs_is_d; + wire [0:`RS_IS_WIDTH-1] ex2_rs_is_q; + wire [0:`MMQ_INVAL_STATE_WIDTH-1] ex2_state_d; + wire [0:`MMQ_INVAL_STATE_WIDTH-1] ex2_state_q; + wire [0:`T_WIDTH-1] ex2_t_d; + wire [0:`T_WIDTH-1] ex2_t_q; + wire [64-`RS_DATA_WIDTH:63] ex3_ea_d; + wire [64-`RS_DATA_WIDTH:63] ex3_ea_q; + wire [0:`MM_THREADS-1] ex3_valid_d; + wire [0:`MM_THREADS-1] ex3_valid_q; + wire [0:`MMQ_INVAL_TTYPE_WIDTH-1] ex3_ttype_d; + wire [0:`MMQ_INVAL_TTYPE_WIDTH-1] ex3_ttype_q; + wire [0:`RS_IS_WIDTH-1] ex3_rs_is_d; + wire [0:`RS_IS_WIDTH-1] ex3_rs_is_q; + wire [0:`MMQ_INVAL_STATE_WIDTH-1] ex3_state_d; + wire [0:`MMQ_INVAL_STATE_WIDTH-1] ex3_state_q; + wire [0:`T_WIDTH-1] ex3_t_d; + wire [0:`T_WIDTH-1] ex3_t_q; + wire [0:`MM_THREADS-1] ex3_flush_req_d; + wire [0:`MM_THREADS-1] ex3_flush_req_q; + wire [0:`MM_THREADS-1] ex4_valid_d; + wire [0:`MM_THREADS-1] ex4_valid_q; + wire [0:`MMQ_INVAL_TTYPE_WIDTH-1] ex4_ttype_d; + wire [0:`MMQ_INVAL_TTYPE_WIDTH-1] ex4_ttype_q; + wire [0:`RS_IS_WIDTH-1] ex4_rs_is_d; + wire [0:`RS_IS_WIDTH-1] ex4_rs_is_q; + wire [0:`MMQ_INVAL_STATE_WIDTH-1] ex4_state_d; + wire [0:`MMQ_INVAL_STATE_WIDTH-1] ex4_state_q; + wire [0:`T_WIDTH-1] ex4_t_d; + wire [0:`T_WIDTH-1] ex4_t_q; + wire [0:`MM_THREADS-1] ex5_valid_d; + wire [0:`MM_THREADS-1] ex5_valid_q; + wire [0:`MMQ_INVAL_TTYPE_WIDTH-1] ex5_ttype_d; + wire [0:`MMQ_INVAL_TTYPE_WIDTH-1] ex5_ttype_q; + wire [0:`RS_IS_WIDTH-1] ex5_rs_is_d; + wire [0:`RS_IS_WIDTH-1] ex5_rs_is_q; + wire [0:`MMQ_INVAL_STATE_WIDTH-1] ex5_state_d; + wire [0:`MMQ_INVAL_STATE_WIDTH-1] ex5_state_q; + wire [0:`T_WIDTH-1] ex5_t_d; + wire [0:`T_WIDTH-1] ex5_t_q; + wire [0:`MM_THREADS-1] ex6_valid_d; + wire [0:`MM_THREADS-1] ex6_valid_q; + wire [0:`MMQ_INVAL_TTYPE_WIDTH-1] ex6_ttype_d; + wire [0:`MMQ_INVAL_TTYPE_WIDTH-1] ex6_ttype_q; + wire [0:2] ex6_isel_d; + wire [0:2] ex6_isel_q; + wire [0:3] ex6_size_d; + wire [0:3] ex6_size_q; + wire ex6_gs_d; + wire ex6_gs_q; + wire ex6_ts_d; + wire ex6_ts_q; + wire ex6_ind_d; + wire ex6_ind_q; + wire [0:`PID_WIDTH-1] ex6_pid_d; + wire [0:`PID_WIDTH-1] ex6_pid_q; + wire [0:`LPID_WIDTH-1] ex6_lpid_d; + wire [0:`LPID_WIDTH-1] ex6_lpid_q; + wire [0:`ITAG_SIZE_ENC-1] ex1_itag_d; + wire [0:`ITAG_SIZE_ENC-1] ex1_itag_q; + wire [0:`ITAG_SIZE_ENC-1] ex2_itag_d; + wire [0:`ITAG_SIZE_ENC-1] ex2_itag_q; + wire [0:`ITAG_SIZE_ENC-1] ex3_itag_d; + wire [0:`ITAG_SIZE_ENC-1] ex3_itag_q; + wire [0:`ITAG_SIZE_ENC-1] ex4_itag_d; + wire [0:`ITAG_SIZE_ENC-1] ex4_itag_q; + wire [0:`ITAG_SIZE_ENC-1] ex5_itag_d; + wire [0:`ITAG_SIZE_ENC-1] ex5_itag_q; + wire [0:`ITAG_SIZE_ENC-1] ex6_itag_d; + wire [0:`ITAG_SIZE_ENC-1] ex6_itag_q; + wire [0:`ITAG_SIZE_ENC-1] mm_xu_itag_d; + wire [0:`ITAG_SIZE_ENC-1] mm_xu_itag_q; + wire [0:`MM_THREADS-1] ord_read_done_d; + wire [0:`MM_THREADS-1] ord_read_done_q; + wire [0:`MM_THREADS-1] ord_write_done_d; + wire [0:`MM_THREADS-1] ord_write_done_q; + wire [0:`MM_THREADS-1] ord_np1_flush_d; + wire [0:`MM_THREADS-1] ord_np1_flush_q; + reg [0:`INV_SEQ_WIDTH-1] inv_seq_d; + wire [0:`INV_SEQ_WIDTH-1] inv_seq_q; + wire [0:`MM_THREADS-1] hold_req_d; + wire [0:`MM_THREADS-1] hold_req_q; + wire [0:`MM_THREADS-1] hold_ack_d; + wire [0:`MM_THREADS-1] hold_ack_q; + wire [0:`MM_THREADS-1] hold_done_d; + wire [0:`MM_THREADS-1] hold_done_q; + wire [0:`MM_THREADS-1] local_barrier_d; + wire [0:`MM_THREADS-1] local_barrier_q; + wire [0:`MM_THREADS-1] global_barrier_d; + wire [0:`MM_THREADS-1] global_barrier_q; + wire [0:`MM_THREADS-1] ex3_illeg_instr_d; + wire [0:`MM_THREADS-1] ex3_illeg_instr_q; + wire [0:`MM_THREADS-1] ex3_ivax_lpid_reject_d, ex3_ivax_lpid_reject_q; + wire [0:`MM_THREADS-1] ex4_ivax_lpid_reject_d, ex4_ivax_lpid_reject_q; + reg [0:`BUS_SNOOP_SEQ_WIDTH-1] bus_snoop_seq_d; + wire [0:`BUS_SNOOP_SEQ_WIDTH-1] bus_snoop_seq_q; + wire [0:`MM_THREADS-1] bus_snoop_hold_req_d; + wire [0:`MM_THREADS-1] bus_snoop_hold_req_q; + wire [0:`MM_THREADS-1] bus_snoop_hold_ack_d; + wire [0:`MM_THREADS-1] bus_snoop_hold_ack_q; + wire [0:`MM_THREADS-1] bus_snoop_hold_done_d; + wire [0:`MM_THREADS-1] bus_snoop_hold_done_q; + wire [0:`MM_THREADS-1] tlbi_complete_d; + wire [0:`MM_THREADS-1] tlbi_complete_q; + wire [0:`MM_THREADS-1] iu_flush_req_d; + wire [0:`MM_THREADS-1] iu_flush_req_q; + wire [0:`MM_THREADS-1] ex4_illeg_instr_d; + wire [0:`MM_THREADS-1] ex4_illeg_instr_q; + wire [0:`MM_THREADS-1] ex5_illeg_instr_d; + wire [0:`MM_THREADS-1] ex5_illeg_instr_q; + wire [0:`MM_THREADS-1] ex6_illeg_instr_d; + wire [0:`MM_THREADS-1] ex6_illeg_instr_q; + wire [0:`MM_THREADS-1] ex7_illeg_instr_d; + wire [0:`MM_THREADS-1] ex7_illeg_instr_q; + wire local_snoop_reject_ored; + wire [0:`MM_THREADS-1] local_snoop_reject_d, local_snoop_reject_q; + wire [0:5] inv_seq_inprogress_d; + wire [0:5] inv_seq_inprogress_q; + wire [0:2] snoop_valid_d; + wire [0:2] snoop_valid_q; + wire [0:34] snoop_attr_d; + wire [0:34] snoop_attr_q; + wire [52-`EPN_WIDTH:51] snoop_vpn_d; + wire [52-`EPN_WIDTH:51] snoop_vpn_q; + wire [0:25] snoop_attr_clone_d; + wire [0:25] snoop_attr_clone_q; + wire [18:19] snoop_attr_tlb_spec_d; + wire [18:19] snoop_attr_tlb_spec_q; + wire [52-`EPN_WIDTH:51] snoop_vpn_clone_d; + wire [52-`EPN_WIDTH:51] snoop_vpn_clone_q; + wire [0:2] snoop_ack_d; + wire [0:2] snoop_ack_q; + wire [0:4] snoop_coming_d; + wire [0:4] snoop_coming_q; + wire [0:8] an_ac_back_inv_d; + wire [0:8] an_ac_back_inv_q; + wire [64-`REAL_ADDR_WIDTH:63] an_ac_back_inv_addr_d; + wire [64-`REAL_ADDR_WIDTH:63] an_ac_back_inv_addr_q; + wire [0:`LPID_WIDTH-1] an_ac_back_inv_lpar_id_d; + wire [0:`LPID_WIDTH-1] an_ac_back_inv_lpar_id_q; + wire [0:1] lsu_tokens_d; + wire [0:1] lsu_tokens_q; + wire [0:`MM_THREADS-1] lsu_req_d; + wire [0:`MM_THREADS-1] lsu_req_q; + wire [0:1] lsu_ttype_d; + wire [0:1] lsu_ttype_q; + wire [0:3] lsu_ubits_d; + wire [0:3] lsu_ubits_q; + wire [0:4] lsu_wimge_d; + wire [0:4] lsu_wimge_q; + wire [64-`REAL_ADDR_WIDTH:63] lsu_addr_d; + wire [64-`REAL_ADDR_WIDTH:63] lsu_addr_q; + wire [0:`LPID_WIDTH-1] lsu_lpid_d; + wire [0:`LPID_WIDTH-1] lsu_lpid_q; + wire lsu_ind_d; + wire lsu_ind_q; + wire lsu_gs_d; + wire lsu_gs_q; + wire lsu_lbit_d; + wire lsu_lbit_q; + wire [0:12] xu_mm_ccr2_notlb_d; + wire [0:12] xu_mm_ccr2_notlb_q; + wire [0:`MM_THREADS-1] xu_mm_epcr_dgtmi_q; + wire [0:`LPID_WIDTH-1] lpidr_q; + wire [12:19] mmucr1_q; + wire [0:1] mmucr1_csinv_q; + wire [0:15] spare_q; + wire [0:3] power_managed_d; + wire [0:3] power_managed_q; + wire [0:3] cswitch_q; + wire [0:`MM_THREADS-1] mm_xu_quiesce_d; + wire [0:`MM_THREADS-1] mm_xu_quiesce_q; + wire [0:`MM_THREADS-1] inval_quiesce_b; + wire [0:4*`MM_THREADS-1] mm_pc_quiesce_d, mm_pc_quiesce_q; + + reg inv_seq_local_done; + reg inv_seq_snoop_done; + reg [0:`MM_THREADS-1] inv_seq_hold_req; + reg [0:`MM_THREADS-1] inv_seq_hold_done; + reg inv_seq_tlbi_load; + reg inv_seq_tlbi_complete; + reg inv_seq_tlb_snoop_val; + reg inv_seq_htw_load; + reg inv_seq_ierat_snoop_val; + reg inv_seq_derat_snoop_val; + reg inv_seq_snoop_inprogress; + wire [0:1] inv_seq_snoop_inprogress_q; + reg inv_seq_local_inprogress; + reg inv_seq_local_barrier_set; + reg inv_seq_global_barrier_set; + reg inv_seq_local_barrier_done; + reg inv_seq_global_barrier_done; + reg inv_seq_idle; + reg bus_snoop_seq_idle; + reg bus_snoop_seq_hold_req; + reg bus_snoop_seq_ready; + reg bus_snoop_seq_done; + wire inval_snoop_forme; + wire inval_snoop_local_reject; + wire ex6_size_large; + reg inv_seq_tlb0fi_inprogress; + wire [0:1] inv_seq_tlb0fi_inprogress_q; + reg inv_seq_tlb0fi_done; + wire ex3_ea_hold; + reg htw_lsu_req_taken_sig; + reg inv_seq_tlbwe_inprogress; + wire [0:1] inv_seq_tlbwe_inprogress_q; + reg inv_seq_tlbwe_snoop_done; + wire tlbwe_back_inv_tid_nz; + wire [0:`MM_THREADS+1] tlbwe_back_inv_d; + wire [0:`MM_THREADS+1] tlbwe_back_inv_q; + wire [52-`EPN_WIDTH:51] tlbwe_back_inv_addr_d; + wire [52-`EPN_WIDTH:51] tlbwe_back_inv_addr_q; + wire [0:34] tlbwe_back_inv_attr_d; + wire [0:34] tlbwe_back_inv_attr_q; + wire back_inv_tid_nz; + wire ex6_tid_nz; + wire ex2_rs_pgsize_not_supp; + wire [0:`MM_THREADS-1] mas6_isize_not_supp; + wire [0:`MM_THREADS-1] mas5_slpid_neq_lpidr; + wire ex2_hv_state; + wire ex2_priv_state; + wire ex2_dgtmi_state; + wire ex5_hv_state; + wire ex5_priv_state; + wire ex5_dgtmi_state; + (* analysis_not_referenced="true" *) + wire [0:16] unused_dc; + + // Pervasive + wire pc_sg_1; + wire pc_sg_0; + wire pc_fce_1; + wire pc_fce_0; + wire pc_func_sl_thold_1; + wire pc_func_sl_thold_0; + wire pc_func_sl_thold_0_b; + wire pc_func_slp_sl_thold_1; + wire pc_func_slp_sl_thold_0; + wire pc_func_slp_sl_thold_0_b; + wire pc_func_slp_nsl_thold_1; + wire pc_func_slp_nsl_thold_0; + wire pc_func_slp_nsl_thold_0_b; + wire pc_func_sl_force; + wire pc_func_slp_sl_force; + wire pc_func_slp_nsl_force; + wire [0:scan_right] siv; + wire [0:scan_right] sov; + wire tidn; + wire tiup; + + //!! Bugspray Include: mmq_inval; + + assign tidn = 1'b0; + assign tiup = 1'b1; + + assign xu_mm_ccr2_notlb_d = {13{xu_mm_ccr2_notlb}}; + + assign power_managed_d[0] = ac_an_power_managed; + assign power_managed_d[1] = power_managed_q[1]; + assign power_managed_d[2] = power_managed_q[2]; + assign power_managed_d[3] = power_managed_q[3]; + assign mm_xu_quiesce = mm_xu_quiesce_q; + assign mm_xu_quiesce_d = tlb_req_quiesce & tlb_ctl_quiesce & htw_quiesce & (~inval_quiesce_b); + // not quiesced + assign inval_quiesce_b = ex6_valid_q | + ({`MM_THREADS{inv_seq_tlbwe_inprogress}} & tlbwe_back_inv_q[0:`MM_THREADS-1]); + + assign mm_pc_quiesce_d[0:`MM_THREADS-1] = tlb_req_quiesce; + assign mm_pc_quiesce_d[`MM_THREADS:2*`MM_THREADS-1] = tlb_ctl_quiesce; + assign mm_pc_quiesce_d[2*`MM_THREADS:3*`MM_THREADS-1] = htw_quiesce; + assign mm_pc_quiesce_d[3*`MM_THREADS:4*`MM_THREADS-1] = (~inval_quiesce_b); + assign mm_pc_tlb_req_quiesce = mm_pc_quiesce_q[0:`MM_THREADS-1]; + assign mm_pc_tlb_ctl_quiesce = mm_pc_quiesce_q[`MM_THREADS:2*`MM_THREADS-1]; + assign mm_pc_htw_quiesce = mm_pc_quiesce_q[2*`MM_THREADS:3*`MM_THREADS-1]; + assign mm_pc_inval_quiesce = mm_pc_quiesce_q[3*`MM_THREADS:4*`MM_THREADS-1]; + + assign ex1_valid_d = xu_mm_rf1_val & (~(xu_rf1_flush)); + assign ex1_ttype_d[0:`MMQ_INVAL_TTYPE_WIDTH - 3] = {xu_mm_rf1_is_tlbilx, xu_mm_rf1_is_tlbivax, xu_mm_rf1_is_eratilx, xu_mm_rf1_is_erativax}; + assign ex1_state_d[0] = |(xu_mm_msr_gs & xu_mm_rf1_val); + assign ex1_state_d[1] = |(xu_mm_msr_pr & xu_mm_rf1_val); + assign ex1_t_d = xu_mm_rf1_t; + + assign ex2_valid_d = ex1_valid_q & (~(xu_ex1_flush)); + assign ex2_ttype_d[0:`MMQ_INVAL_TTYPE_WIDTH - 3] = ex1_ttype_q[0:`MMQ_INVAL_TTYPE_WIDTH - 3]; + assign ex2_ttype_d[`MMQ_INVAL_TTYPE_WIDTH - 2:`MMQ_INVAL_TTYPE_WIDTH - 1] = {xu_mm_ex1_is_csync, xu_mm_ex1_is_isync}; + assign ex2_rs_is_d = xu_mm_ex1_rs_is; + // RS(55) -> Local rs_is(0) + // RS(56:57) -> IS rs_is(1 to 2) + // RS(58:59) -> Class rs_is(3 to 4) + // RS(60:63) -> Size rs_is(5 to 8) + assign ex2_state_d = ex1_state_q; + assign ex2_t_d = ex1_t_q; + // ex2 effective addr capture latch.. hold addr until inv_seq done with it + assign ex3_ea_hold = (|(ex3_valid_q) & |(ex3_ttype_q[0:3])) | (|(ex4_valid_q) & |(ex4_ttype_q[0:3])) | (|(ex5_valid_q) & |(ex5_ttype_q[0:3])) | (|(ex6_valid_q) & |(ex6_ttype_q[0:3])); + assign ex3_ea_d = (ex3_ea_q & {`RS_DATA_WIDTH{ex3_ea_hold}}) | (xu_mm_ex2_eff_addr & {`RS_DATA_WIDTH{~ex3_ea_hold}}); + assign ex2_hv_state = (~ex2_state_q[0]) & (~ex2_state_q[1]); + assign ex2_priv_state = (~ex2_state_q[1]); + assign ex2_dgtmi_state = |(ex2_valid_q & xu_mm_epcr_dgtmi_q); + + assign ex3_valid_d = ex2_valid_q & (~(xu_ex2_flush)); + assign ex3_ttype_d[0:`MMQ_INVAL_TTYPE_WIDTH - 3] = ex2_ttype_q[0:`MMQ_INVAL_TTYPE_WIDTH - 3]; + assign ex3_ttype_d[`MMQ_INVAL_TTYPE_WIDTH - 2] = (ex2_ttype_q[`MMQ_INVAL_TTYPE_WIDTH - 2] & (~mmucr1_csinv_q[0])); + assign ex3_ttype_d[`MMQ_INVAL_TTYPE_WIDTH - 1] = (ex2_ttype_q[`MMQ_INVAL_TTYPE_WIDTH - 1] & (~mmucr1_csinv_q[1])); + assign ex3_rs_is_d = ex2_rs_is_q; + assign ex3_state_d = ex2_state_q; + assign ex3_t_d = ex2_t_q; + + assign ex3_flush_req_d = ((ex2_ttype_q[0:3] != 4'b0000 & (inv_seq_idle == 1'b0 | + (|(ex3_valid_q) == 1'b1 & |(ex3_ttype_q[0:3]) == 1'b1) | + (|(ex4_valid_q) == 1'b1 & |(ex4_ttype_q[0:3]) == 1'b1) | + (|(ex5_valid_q) == 1'b1 & |(ex5_ttype_q[0:3]) == 1'b1) | + (|(ex6_valid_q) == 1'b1 & |(ex6_ttype_q[0:3]) == 1'b1)))) ? (ex2_valid_q & (~(xu_ex2_flush))) : + tlb_ctl_ex2_flush_req; + + assign ex4_valid_d = ex3_valid_q & (~(xu_ex3_flush)) & (~(ex3_flush_req_q)) & (~(ex3_illeg_instr_q)) & (~(ex3_ivax_lpid_reject_q)); + assign ex4_ttype_d = ex3_ttype_q; + assign ex4_rs_is_d = ex3_rs_is_q; + assign ex4_state_d = ex3_state_q; + assign ex4_t_d = ex3_t_q; + + assign ex5_valid_d = ex4_valid_q & (~(xu_ex4_flush)); + assign ex5_ttype_d = ex4_ttype_q; + assign ex5_rs_is_d = ex4_rs_is_q; + assign ex5_state_d = ex4_state_q; + assign ex5_t_d = ex4_t_q; + assign ex5_hv_state = (~ex5_state_q[0]) & (~ex5_state_q[1]); + assign ex5_priv_state = (~ex5_state_q[1]); + assign ex5_dgtmi_state = |(ex5_valid_q & xu_mm_epcr_dgtmi_q); + + // these are ex6 capture latches.. hold invalidate op until inv_seq done with it + assign ex6_valid_d = (inv_seq_local_done == 1'b1) ? {`MM_THREADS{1'b0}} : + ((|(ex6_valid_q) == 1'b0 & ((ex5_ttype_q[0] == 1'b1 & ex5_priv_state == 1'b1 & ex5_dgtmi_state == 1'b0) | (ex5_ttype_q[0] == 1'b1 & ex5_hv_state == 1'b1 & ex5_dgtmi_state == 1'b1) | (|(ex5_ttype_q[1:3]) == 1'b1 & ex5_hv_state == 1'b1)))) ? (ex5_valid_q & (~(xu_ex5_flush))) : + ex6_valid_q; + //ttype <= tlbilx & tlbivax & eratilx & erativax & csync & isync; + assign ex6_ttype_d = ((|(ex5_valid_q) == 1'b1 & |(ex5_ttype_q[0:3]) == 1'b1 & |(ex6_valid_q) == 1'b0)) ? ex5_ttype_q : + ex6_ttype_q; + // ttype -> 0 1 2 3 + // sources for ttype -> tlbilx tlbivax eratilx erativax + // RS(55) -> Local rs_is(0) 1 0 1 0 + // RS(56:57) -> IS rs_is(1 to 2) f(T) 11 f(T) RS(56:57) + // RS(58:59) -> Class rs_is(3 to 4) g(T) 00 g(T) RS(58:59) + // RS(60:63) -> Size rs_is(5 to 8) mas6 mas6 n/a RS(60:63) + // TS (state(1)) mas6 mas6 mmucr0 mmucr0 + // TID mas6 mas6 mmucr0 mmucr0 + // GS (state(0)) mas5 mas5 mmucr0 mmucr0 + // LPID mas5 mas5 lpidr lpidr + // IND mas6 mas6 0 0 + assign ex6_isel_d = ((|(ex5_valid_q) == 1'b1 & ex5_ttype_q[3] == 1'b1 & ex5_rs_is_q[1:2] == 2'b10 & |(ex6_valid_q) == 1'b0)) ? {1'b1, ex5_rs_is_q[3:4]} : + ((|(ex5_valid_q) == 1'b1 & ex5_ttype_q[3] == 1'b1 & ex5_rs_is_q[1:2] != 2'b10 & |(ex6_valid_q) == 1'b0)) ? {1'b0, ex5_rs_is_q[1:2]} : + ((|(ex5_valid_q) == 1'b1 & ex5_ttype_q[2] == 1'b1 & |(ex6_valid_q) == 1'b0)) ? ex5_t_q[0:2] : + ((|(ex5_valid_q) == 1'b1 & ex5_ttype_q[1] == 1'b1 & |(ex6_valid_q) == 1'b0)) ? 3'b011 : + ((|(ex5_valid_q) == 1'b1 & ex5_ttype_q[0] == 1'b1 & |(ex6_valid_q) == 1'b0)) ? ex5_t_q[0:2] : + ex6_isel_q; + // T field from tlbilx/eratilx is 0=all, 1=pid, 2=resvd/GS, 3=address, 4-7=class + // ex1_rs_is(0 to 9) from erativax instr. + // RS(55) -> ex1_rs_is(0) -> snoop_attr(0) -> Local + // RS(56:57) -> ex1_rs_is(1:2) -> snoop_attr(0:1) -> IS + // RS(58:59) -> ex1_rs_is(3:4) -> snoop_attr(2:3) -> Class + // n/a -> n/a -> snoop_attr(4:5) -> State + // n/a -> n/a -> snoop_attr(6:13) -> TID(6:13) + // RS(60:63) -> ex1_rs_is(5:8) -> snoop_attr(14:17) -> Size + // n/a -> n/a -> snoop_attr(20:25) -> TID(0:5) + // erat snoop_attr: + // 0 -> Local + // 1:3 -> IS/Class: 0=all, 1=tid, 2=gs, 3=epn, 4=class0, 5=class1, 6=class2, 7=class3 + // 4:5 -> GS/TS + // 6:13 -> TID(6:13) + // 14:17 -> Size + // 18 -> TID_NZ + // 19 -> mmucsr0.tlb0fi + // 20:25 -> TID(0:5) + assign ex6_size_d = ((|(ex5_valid_q) == 1'b1 & ex5_ttype_q[3] == 1'b1 & |(ex6_valid_q) == 1'b0)) ? ex5_rs_is_q[5:8] : + ((|(ex5_valid_q) == 1'b1 & ex5_ttype_q[2] == 1'b1 & |(ex6_valid_q) == 1'b0)) ? 4'b0000 : + ((ex5_valid_q[0] == 1'b1 & ex5_ttype_q[0:1] != 2'b00 & |(ex6_valid_q) == 1'b0)) ? mas6_0_isize : + `ifdef MM_THREADS2 + ((ex5_valid_q[1] == 1'b1 & ex5_ttype_q[0:1] != 2'b00 & |(ex6_valid_q) == 1'b0)) ? mas6_1_isize : + `endif + ex6_size_q; + assign ex6_size_large = ((ex6_size_q == TLB_PgSize_64KB | ex6_size_q == TLB_PgSize_1MB | ex6_size_q == TLB_PgSize_16MB | ex6_size_q == TLB_PgSize_256MB | ex6_size_q == TLB_PgSize_1GB)) ? 1'b1 : + 1'b0; + // mmucr0: 0:1-ExtClass, 2:3-TGS/TS, 4:5-TLBSel, 6:19-TID, + // ttype <= tlbilx & tlbivax & eratilx & erativax & csync & isync; + assign ex6_gs_d = ((ex5_valid_q[0] == 1'b1 & |(ex5_ttype_q[2:3]) == 1'b1 & |(ex6_valid_q) == 1'b0)) ? mmucr0_0[2] : + ((ex5_valid_q[0] == 1'b1 & |(ex5_ttype_q[0:1]) == 1'b1 & |(ex6_valid_q) == 1'b0)) ? mas5_0_sgs : + `ifdef MM_THREADS2 + ((ex5_valid_q[1] == 1'b1 & |(ex5_ttype_q[2:3]) == 1'b1 & |(ex6_valid_q) == 1'b0)) ? mmucr0_1[2] : + ((ex5_valid_q[1] == 1'b1 & |(ex5_ttype_q[0:1]) == 1'b1 & |(ex6_valid_q) == 1'b0)) ? mas5_1_sgs : + `endif + ex6_gs_q; + assign ex6_ts_d = ((ex5_valid_q[0] == 1'b1 & |(ex5_ttype_q[2:3]) == 1'b1 & |(ex6_valid_q) == 1'b0)) ? mmucr0_0[3] : + ((ex5_valid_q[0] == 1'b1 & |(ex5_ttype_q[0:1]) == 1'b1 & |(ex6_valid_q) == 1'b0)) ? mas6_0_sas : + `ifdef MM_THREADS2 + ((ex5_valid_q[1] == 1'b1 & |(ex5_ttype_q[2:3]) == 1'b1 & |(ex6_valid_q) == 1'b0)) ? mmucr0_1[3] : + ((ex5_valid_q[1] == 1'b1 & |(ex5_ttype_q[0:1]) == 1'b1 & |(ex6_valid_q) == 1'b0)) ? mas6_1_sas : + `endif + ex6_ts_q; + //ttype <= tlbilx & tlbivax & eratilx & erativax & csync & isync; + assign ex6_ind_d = ((ex5_valid_q[0] == 1'b1 & |(ex5_ttype_q[2:3]) == 1'b1 & |(ex6_valid_q) == 1'b0)) ? 1'b0 : + ((ex5_valid_q[0] == 1'b1 & |(ex5_ttype_q[0:1]) == 1'b1 & |(ex6_valid_q) == 1'b0)) ? mas6_0_sind : + `ifdef MM_THREADS2 + ((ex5_valid_q[1] == 1'b1 & |(ex5_ttype_q[2:3]) == 1'b1 & |(ex6_valid_q) == 1'b0)) ? 1'b0 : + ((ex5_valid_q[1] == 1'b1 & |(ex5_ttype_q[0:1]) == 1'b1 & |(ex6_valid_q) == 1'b0)) ? mas6_1_sind : + `endif + ex6_ind_q; + assign ex6_pid_d = ((ex5_valid_q[0] == 1'b1 & |(ex5_ttype_q[2:3]) == 1'b1 & |(ex6_valid_q) == 1'b0)) ? mmucr0_0[6:19] : + ((ex5_valid_q[0] == 1'b1 & |(ex5_ttype_q[0:1]) == 1'b1 & |(ex6_valid_q) == 1'b0)) ? mas6_0_spid : + `ifdef MM_THREADS2 + ((ex5_valid_q[1] == 1'b1 & |(ex5_ttype_q[2:3]) == 1'b1 & |(ex6_valid_q) == 1'b0)) ? mmucr0_1[6:19] : + ((ex5_valid_q[1] == 1'b1 & |(ex5_ttype_q[0:1]) == 1'b1 & |(ex6_valid_q) == 1'b0)) ? mas6_1_spid : + `endif + ex6_pid_q; + assign ex6_lpid_d = ((|(ex5_valid_q) == 1'b1 & |(ex5_ttype_q[2:3]) == 1'b1 & |(ex6_valid_q) == 1'b0)) ? lpidr_q : + ((ex5_valid_q[0] == 1'b1 & |(ex5_ttype_q[0:1]) == 1'b1 & |(ex6_valid_q) == 1'b0)) ? mas5_0_slpid : + `ifdef MM_THREADS2 + ((ex5_valid_q[1] == 1'b1 & |(ex5_ttype_q[0:1]) == 1'b1 & |(ex6_valid_q) == 1'b0)) ? mas5_1_slpid : + `endif + ex6_lpid_q; + + assign ex1_itag_d = xu_mm_rf1_itag; + assign ex2_itag_d = ex1_itag_q; + assign ex3_itag_d = ex2_itag_q; + assign ex4_itag_d = ex3_itag_q; + assign ex5_itag_d = ex4_itag_q; + assign ex6_itag_d = ((|(ex5_valid_q) == 1'b1 & |(ex5_ttype_q[0:3]) == 1'b1 & |(ex6_valid_q) == 1'b0)) ? ex5_itag_q : + ex6_itag_q; + // an_ac_back_inv_q: 0=valid b-1, 1=target b-1, 2=valid b, 3=target b, 4=L, 5=GS, 6=IND, 7=local, 8=reject + // iu barrier op shadow status + assign local_barrier_d = (inv_seq_local_barrier_done == 1'b1) ? (local_barrier_q & (~(ex6_valid_q))) : + (inv_seq_local_barrier_set == 1'b1) ? (ex6_valid_q | local_barrier_q) : + local_barrier_q; + assign global_barrier_d = (((inv_seq_global_barrier_done == 1'b1 & an_ac_back_inv_q[7] == 1'b1) | inval_snoop_local_reject == 1'b1)) ? {`MM_THREADS{1'b0}} : + (inv_seq_global_barrier_set == 1'b1) ? (ex6_valid_q | global_barrier_q) : + global_barrier_q; + assign ord_np1_flush_d = (inv_seq_local_done == 1'b1) ? ex6_valid_q : + {`MM_THREADS{1'b0}}; + // tlb_ctl ordered types: 0-tlbre, 1-tlbwe, 2-tlbsx/tlbsrx + assign ord_read_done_d = (inv_seq_local_barrier_done == 1'b1) ? (local_barrier_q & ex6_valid_q) : + ((inv_seq_tlbi_load == 1'b1)) ? ex6_valid_q : + (((tlbwe_back_inv_q[`MM_THREADS] == 1'b1 & inv_seq_tlbwe_snoop_done == 1'b1 & cswitch_q[2] == 1'b0) | + (tlbwe_back_inv_q[`MM_THREADS] == 1'b1 & tlbwe_back_inv_q[`MM_THREADS+1] == 1'b0 & tlb_tag5_write == 1'b0 & cswitch_q[2] == 1'b0))) ? tlbwe_back_inv_q[0:`MM_THREADS-1] : + ((tlb_ctl_ord_type[1] == 1'b1 & (tlbwe_back_inv_valid == 1'b0 | cswitch_q[2] == 1'b1))) ? tlb_ctl_barrier_done : + {`MM_THREADS{1'b0}}; + assign ord_write_done_d = (((tlb_ctl_ord_type[0] == 1'b1 | tlb_ctl_ord_type[2] == 1'b1) & (tlbwe_back_inv_valid == 1'b0 | cswitch_q[2] == 1'b1))) ? tlb_ctl_barrier_done : + {`MM_THREADS{1'b0}}; + assign tlbi_complete_d = (((inv_seq_global_barrier_done == 1'b1 & an_ac_back_inv_q[7] == 1'b1) | inval_snoop_local_reject == 1'b1)) ? global_barrier_q : + {`MM_THREADS{1'b0}}; + // Illegal instr logic + assign ex2_rs_pgsize_not_supp = ((ex2_rs_is_q[5:8] == TLB_PgSize_4KB | ex2_rs_is_q[5:8] == TLB_PgSize_64KB | ex2_rs_is_q[5:8] == TLB_PgSize_1MB | ex2_rs_is_q[5:8] == TLB_PgSize_16MB | ex2_rs_is_q[5:8] == TLB_PgSize_1GB)) ? 1'b0 : + 1'b1; + assign mas6_isize_not_supp[0] = (((mas6_0_isize == TLB_PgSize_4KB | mas6_0_isize == TLB_PgSize_64KB | mas6_0_isize == TLB_PgSize_1MB | mas6_0_isize == TLB_PgSize_16MB | mas6_0_isize == TLB_PgSize_1GB) & mas6_0_sind == 1'b0) | ((mas6_0_isize == TLB_PgSize_1MB | mas6_0_isize == TLB_PgSize_256MB) & mas6_0_sind == 1'b1)) ? 1'b0 : + 1'b1; +`ifdef MM_THREADS2 + assign mas6_isize_not_supp[1] = (((mas6_1_isize == TLB_PgSize_4KB | mas6_1_isize == TLB_PgSize_64KB | mas6_1_isize == TLB_PgSize_1MB | mas6_1_isize == TLB_PgSize_16MB | mas6_1_isize == TLB_PgSize_1GB) & mas6_1_sind == 1'b0) | ((mas6_1_isize == TLB_PgSize_1MB | mas6_1_isize == TLB_PgSize_256MB) & mas6_1_sind == 1'b1)) ? 1'b0 : + 1'b1; +`endif + + assign mas5_slpid_neq_lpidr[0] = ~(mas5_0_slpid == lpidr_q); +`ifdef MM_THREADS2 + assign mas5_slpid_neq_lpidr[1] = ~(mas5_1_slpid == lpidr_q); +`endif + + //ttype <= tlbilx & tlbivax & eratilx & erativax; + // T field from tlbilx/eratilx is 0=all, 1=pid, 2=resvd/GS, 3=address, 4-7=class + // ex2_hv_state <= not ex2_state_q(0) and not ex2_state_q(1); -- gs=0, pr=0 + // ex2_priv_state <= not ex2_state_q(1); -- pr=0 + // ex2_dgtmi_state <= |(ex2_valid_q and xu_mm_epcr_dgtmi_q); -- disable guest tlb mgmt instr's + assign ex3_illeg_instr_d = ( ex2_valid_q & mas6_isize_not_supp & {`MM_THREADS{ex2_ttype_q[1] & ex2_hv_state}} ) | + ( ex2_valid_q & mas6_isize_not_supp & ({`MM_THREADS{ex2_ttype_q[0] & (ex2_t_q == 3'b011)}} & {`MM_THREADS{ex2_hv_state | (ex2_priv_state & (~ex2_dgtmi_state))}}) ) | + ( ex2_valid_q & {`MM_THREADS{ex2_ttype_q[3] & ex2_hv_state & ex2_rs_pgsize_not_supp}} ) | + ( ex2_valid_q & {`MM_THREADS{ex2_ttype_q[2] & ex2_hv_state & ex2_t_q[0] & mmucr1_q[pos_ictid] & mmucr1_q[pos_dctid]}} ) | + (tlb_ctl_ex2_illeg_instr); + + assign ex4_illeg_instr_d = ex3_illeg_instr_q & (~(ex3_flush_req_q)); + assign ex5_illeg_instr_d = ex4_illeg_instr_q; + assign ex6_illeg_instr_d = ex5_illeg_instr_q; + assign ex7_illeg_instr_d = ex6_illeg_instr_q | tlb_ctl_ex6_illeg_instr; + + assign ex3_ivax_lpid_reject_d = ( ex2_valid_q & mas5_slpid_neq_lpidr & ~mas6_isize_not_supp & {`MM_THREADS{ex2_ttype_q[1] & ex2_hv_state & + (xu_mm_ccr2_notlb_q[0] == MMU_Mode_Value) & mmucr1_q[pos_tlbi_rej]}} ); + // for erativax, this would be a nonsensical check for outgoing ivax because + // source (lpidr) is same thing we check incoming snoop lpid value against + // ( ex2_valid_q & lpidr_neq_lpidr & {`MM_THREADS{ex2_ttype_q[3] & ex2_hv_state & + // ~ex2_rs_pgsize_not_supp & (xu_mm_ccr2_notlb_q[0] == ERAT_Mode_Value)}} ); + + assign ex4_ivax_lpid_reject_d = (ex3_ivax_lpid_reject_q & ~ex3_illeg_instr_q & ~ex3_flush_req_q & ~xu_ex3_flush); + + // invalidate sequencer + //Inv_Sequencer: PROCESS (inv_seq_q, por_seq_q, an_ac_back_inv, an_ac_back_inv_target, + // ex6_valid_q, ex6_ttype_q) + + always @(inv_seq_q or xu_mm_lmq_stq_empty or iu_mm_lmq_empty or hold_ack_q or lsu_tokens_q or xu_mm_ccr2_notlb_q[0] or snoop_ack_q or ex6_valid_q or ex6_ttype_q[0:3] or ex6_ind_q or ex6_isel_q or bus_snoop_seq_ready or mmucsr0_tlb0fi or tlbwe_back_inv_q[`MM_THREADS+1] or an_ac_back_inv_q[6] or an_ac_back_inv_addr_q[54:55] or htw_lsu_req_valid or lsu_req_q or cswitch_q[0:1] or cswitch_q[3] or power_managed_q[0] or power_managed_q[2] or power_managed_q[3]) + begin: Inv_Sequencer + inv_seq_idle = 1'b0; + inv_seq_snoop_inprogress = 1'b0; + inv_seq_local_inprogress = 1'b0; + inv_seq_local_barrier_set = 1'b0; + inv_seq_global_barrier_set = 1'b0; + inv_seq_local_barrier_done = 1'b0; + inv_seq_global_barrier_done = 1'b0; + inv_seq_snoop_done = 1'b0; + inv_seq_local_done = 1'b0; + inv_seq_tlbi_load = 1'b0; + inv_seq_tlbi_complete = 1'b0; + inv_seq_htw_load = 1'b0; + htw_lsu_req_taken_sig = 1'b0; + inv_seq_hold_req = {`MM_THREADS{1'b0}}; + inv_seq_hold_done = {`MM_THREADS{1'b0}}; + inv_seq_tlb_snoop_val = 1'b0; + inv_seq_ierat_snoop_val = 1'b0; + inv_seq_derat_snoop_val = 1'b0; + inv_seq_tlb0fi_inprogress = 1'b0; + inv_seq_tlb0fi_done = 1'b0; + inv_seq_tlbwe_snoop_done = 1'b0; + inv_seq_tlbwe_inprogress = 1'b0; + + case (inv_seq_q) + // wait for an invalidation to service + // ttype = tlbilx & tlbivax & eratilx & erativax; + + InvSeq_Idle : + begin + inv_seq_idle = 1'b1; + if (bus_snoop_seq_ready == 1'b1) + // invalidate snoop from bus + begin + inv_seq_snoop_inprogress = 1'b1; + inv_seq_hold_req = {`MM_THREADS{1'b1}}; + inv_seq_d = InvSeq_Stg8; + end + else if (htw_lsu_req_valid == 1'b1) + // table walk load from htw + inv_seq_d = InvSeq_Stg31; + else if (|(ex6_valid_q) == 1'b1 & (ex6_ttype_q[1] == 1'b1 | ex6_ttype_q[3] == 1'b1)) + // locally sourced global invalidate from instr + begin + inv_seq_local_inprogress = 1'b1; + inv_seq_global_barrier_set = 1'b1; + inv_seq_d = InvSeq_Stg1; + end + else if (|(ex6_valid_q) == 1'b1 & (ex6_ttype_q[0] == 1'b1 | ex6_ttype_q[2] == 1'b1)) + // locally sourced local invalidate from instr + begin + inv_seq_hold_req = {`MM_THREADS{1'b1}}; + inv_seq_local_inprogress = 1'b1; + inv_seq_local_barrier_set = 1'b1; + inv_seq_d = InvSeq_Stg2; + end + else if (mmucsr0_tlb0fi == 1'b1) + // locally sourced full invalidate from mmucsr0.tlb0fi + begin + inv_seq_hold_req = {`MM_THREADS{1'b1}}; + inv_seq_tlb0fi_inprogress = 1'b1; + inv_seq_d = InvSeq_Stg16; + end + else if (tlbwe_back_inv_q[`MM_THREADS+1] == 1'b1) + // locally sourced tlbwe back invalidate for erats + begin + inv_seq_hold_req = {`MM_THREADS{1'b1}}; + inv_seq_tlbwe_inprogress = 1'b1; + inv_seq_d = InvSeq_Stg24; + end + else + inv_seq_d = InvSeq_Idle; + end + + InvSeq_Stg1 : + // locally sourced global invalidate action 1 + // go idle and see global invalidate snoop from bus later.. + // ttype = tlbilx & tlbivax & eratilx & erativax; + begin + inv_seq_local_inprogress = 1'b1; + if (lsu_tokens_q != 2'b00 & (xu_mm_lmq_stq_empty == 1'b1 | cswitch_q[0] == 1'b1)) + begin + inv_seq_tlbi_load = 1'b1; + inv_seq_local_done = 1'b1; + inv_seq_d = InvSeq_Idle; + end + else + inv_seq_d = InvSeq_Stg1; + end + + InvSeq_Stg2 : + // locally sourced local invalidate action 1 + // let hold_req be asserted + begin + inv_seq_local_inprogress = 1'b1; + if (&(hold_ack_q | ex6_valid_q) == 1'b1) + // this thread held, other threads held and flushed + inv_seq_d = InvSeq_Stg3; + else if (htw_lsu_req_valid == 1'b1) + // table walk load request from htw; could be ucode, so service it + inv_seq_d = InvSeq_Stg23; + else + inv_seq_d = InvSeq_Stg2; + end + + InvSeq_Stg3 : + // locally sourced local invalidate action 2 + // ttype = tlbilx & tlbivax & eratilx & erativax; + begin + inv_seq_local_inprogress = 1'b1; + if (iu_mm_lmq_empty == 1'b1 & xu_mm_lmq_stq_empty == 1'b1 & xu_mm_ccr2_notlb_q[0] == MMU_Mode_Value & ex6_ttype_q[0] == 1'b1) + // invalidate the TLB first, assuming it exists + inv_seq_d = InvSeq_Stg4; + else if (iu_mm_lmq_empty == 1'b1 & xu_mm_lmq_stq_empty == 1'b1) + // invalidate the ERAT's + inv_seq_d = InvSeq_Stg6; + else if (htw_lsu_req_valid == 1'b1) + // table walk load request from htw; could hang waiting on empty, so service it + inv_seq_d = InvSeq_Stg23; + else + inv_seq_d = InvSeq_Stg3; + end + + InvSeq_Stg4 : + // locally sourced local invalidate action 3 + // invalidate the TLB + begin + inv_seq_local_inprogress = 1'b1; + inv_seq_tlb_snoop_val = 1'b1; + inv_seq_d = InvSeq_Stg5; + end + + InvSeq_Stg5 : + // locally sourced local invalidate action 4 + begin + inv_seq_local_inprogress = 1'b1; + if (snoop_ack_q[2] == 1'b1) + inv_seq_d = InvSeq_Stg6; + else + inv_seq_d = InvSeq_Stg5; + end + + InvSeq_Stg6 : + // locally sourced local invalidate action 5 + // invalidate the ERAT's after TLB copy(s) destroyed + // but don't invalidate erats for T=3, ind=1 snoops + begin + inv_seq_local_inprogress = 1'b1; + if ( (~(ex6_ind_q & (ex6_isel_q == 3'b011))) == 1'b1 ) + begin + inv_seq_ierat_snoop_val = 1'b1; + inv_seq_derat_snoop_val = 1'b1; + end + inv_seq_d = InvSeq_Stg7; + end + + InvSeq_Stg7 : + // locally sourced local invalidate action 6 + begin + inv_seq_local_inprogress = 1'b1; + if (snoop_ack_q[0:1] == 2'b11 | (ex6_ind_q & (ex6_isel_q == 3'b011)) == 1'b1) + begin + inv_seq_local_done = 1'b1; + inv_seq_local_barrier_done = 1'b1; + inv_seq_hold_done = {`MM_THREADS{1'b1}}; + inv_seq_d = InvSeq_Idle; + end + else + inv_seq_d = InvSeq_Stg7; + end + + //------------ incoming snoop from bus ------- + // power_managed_q(0) = power managed state + // power_managed_q(1) = reject snoops from bus when in power managed state + // power_managed_q(2) = inval_seq bus snoops: bypass handshakes and ack's when in power managed state + // power_managed_q(3) = inval_seq bus snoops: skip erat and tlb snoops when in power managed state + InvSeq_Stg8 : + // global invalidate snoop action 1 + begin + // bus_snoop_hold_req/ack has been completed by side sequencer + inv_seq_snoop_inprogress = 1'b1; + if (htw_lsu_req_valid == 1'b1) + // table walk load request from htw; could be ucode, so service it + inv_seq_d = InvSeq_Stg28; + else + inv_seq_d = InvSeq_Stg9; + end + + InvSeq_Stg9 : + // global invalidate snoop action 2 + // let XU drive flushes, etc. + begin + inv_seq_snoop_inprogress = 1'b1; + inv_seq_d = InvSeq_Stg10; + end + + InvSeq_Stg10 : + // global invalidate snoop action 3 + begin + inv_seq_snoop_inprogress = 1'b1; + if (power_managed_q[0] == 1'b1 & power_managed_q[3] == 1'b1) + // sleep mode, bit 3 skip the snoops + inv_seq_d = InvSeq_Stg14; + else if ((iu_mm_lmq_empty == 1'b1 | cswitch_q[3] == 1'b1 | power_managed_q[0] == 1'b1) & (xu_mm_lmq_stq_empty == 1'b1 | cswitch_q[1] == 1'b1 | (power_managed_q[0] == 1'b1 & power_managed_q[2] == 1'b1)) & xu_mm_ccr2_notlb_q[0] == MMU_Mode_Value) + // invalidate the TLB first, assuming it exists + inv_seq_d = InvSeq_Stg11; + else if ((iu_mm_lmq_empty == 1'b1 | cswitch_q[3] == 1'b1 | power_managed_q[0] == 1'b1) & + // sleep mode, skip the iu status + (xu_mm_lmq_stq_empty == 1'b1 | cswitch_q[1] == 1'b1 | (power_managed_q[0] == 1'b1 & power_managed_q[2] == 1'b1))) + // sleep mode, bit 2 skip the xu status + // invalidate the ERAT's + inv_seq_d = InvSeq_Stg13; + else if (htw_lsu_req_valid == 1'b1) + // table walk load request from htw; could hang waiting on empty, so service it + inv_seq_d = InvSeq_Stg28; + else + inv_seq_d = InvSeq_Stg10; + end + + InvSeq_Stg11 : + // global invalidate snoop action 4 + // invalidate the TLB + begin + inv_seq_snoop_inprogress = 1'b1; + inv_seq_tlb_snoop_val = 1'b1; + inv_seq_d = InvSeq_Stg12; + end + + InvSeq_Stg12 : + // global invalidate snoop action 5 + begin + inv_seq_snoop_inprogress = 1'b1; + if (snoop_ack_q[2] == 1'b1 | (power_managed_q[0] == 1'b1 & power_managed_q[2] == 1'b1)) + inv_seq_d = InvSeq_Stg13; + else + inv_seq_d = InvSeq_Stg12; + end + + InvSeq_Stg13 : + // global invalidate snoop action 6 + // invalidate the ERAT's after TLB copy(s) destroyed + // but don't invalidate erats for ind=1 entries + begin + inv_seq_snoop_inprogress = 1'b1; + if ( (~(an_ac_back_inv_q[6] & (an_ac_back_inv_addr_q[54:55] == 2'b11))) == 1'b1 ) + begin + inv_seq_ierat_snoop_val = 1'b1; + inv_seq_derat_snoop_val = 1'b1; + end + inv_seq_d = InvSeq_Stg14; + end + + InvSeq_Stg14 : + // global invalidate snoop action 7 + begin + inv_seq_snoop_inprogress = 1'b1; + if (power_managed_q[0] == 1'b1 & power_managed_q[2] == 1'b1) + // sleep mode, bit 2 skip the acks + begin + inv_seq_tlbi_complete = 1'b1; // send tlbi_complete + inv_seq_d = InvSeq_Stg15; + end + else if (lsu_tokens_q != 2'b00 & (snoop_ack_q[0:1] == 2'b11 | (an_ac_back_inv_q[6] & (an_ac_back_inv_addr_q[54:55] == 2'b11)) == 1'b1)) + // wait for tokens and (erat acks or ind=1) + begin + inv_seq_tlbi_complete = 1'b1; // send tlbi_complete + inv_seq_d = InvSeq_Stg15; + end + else + inv_seq_d = InvSeq_Stg14; + end + + InvSeq_Stg15 : + // global invalidate snoop action 8 + // wait until lsu request was sent and token is returned, meaning the tlbi complete has been sent to L2 + // or we are in sleep mode and bit 2 skip the handshakes + if ((|(lsu_req_q) == 1'b0 & lsu_tokens_q != 2'b00) | (power_managed_q[0] == 1'b1 & power_managed_q[2] == 1'b1)) + begin + inv_seq_snoop_inprogress = 1'b0; + inv_seq_snoop_done = 1'b1; + inv_seq_hold_done = {`MM_THREADS{1'b1}}; + inv_seq_global_barrier_done = 1'b1; + inv_seq_d = InvSeq_Idle; // all done.. go idle + end + else + begin + inv_seq_snoop_inprogress = 1'b1; + inv_seq_d = InvSeq_Stg15; + end + + //--------- Local MMUCSR0 tlb0fi bit set for full invalidates + InvSeq_Stg16 : + // locally sourced full invalidate action 1 + // let hold_req be asserted + begin + inv_seq_tlb0fi_inprogress = 1'b1; + if (&(hold_ack_q) == 1'b1) + inv_seq_d = InvSeq_Stg17; + else if (htw_lsu_req_valid == 1'b1) + // table walk load request from htw; could be ucode, so service it + inv_seq_d = InvSeq_Stg22; + else + inv_seq_d = InvSeq_Stg16; + end + + InvSeq_Stg17 : + // locally sourced full invalidate action 2 + begin + inv_seq_tlb0fi_inprogress = 1'b1; + if (iu_mm_lmq_empty == 1'b1 & xu_mm_lmq_stq_empty == 1'b1 & xu_mm_ccr2_notlb_q[0] == MMU_Mode_Value) + // invalidate the TLB + inv_seq_d = InvSeq_Stg18; + else if (iu_mm_lmq_empty == 1'b1 & xu_mm_lmq_stq_empty == 1'b1) + // invalidate the ERATs only + inv_seq_d = InvSeq_Stg20; + else if (htw_lsu_req_valid == 1'b1) + // table walk load request from htw; could hang waiting on empty, so service it + inv_seq_d = InvSeq_Stg22; + else + inv_seq_d = InvSeq_Stg17; // let fetches/loads/stores drain + end + + InvSeq_Stg18 : + // locally sourced full invalidate action 3 + // invalidate the TLB + begin + inv_seq_tlb0fi_inprogress = 1'b1; + inv_seq_tlb_snoop_val = 1'b1; + inv_seq_d = InvSeq_Stg19; + end + + InvSeq_Stg19 : + // locally sourced full invalidate action 4 + begin + inv_seq_tlb0fi_inprogress = 1'b1; + if (snoop_ack_q[2] == 1'b1) + inv_seq_d = InvSeq_Stg20; + else + inv_seq_d = InvSeq_Stg19; + end + + InvSeq_Stg20 : + // locally sourced full invalidate action 5 + // invalidate the ERAT's after TLB copy(s) destroyed + begin + inv_seq_tlb0fi_inprogress = 1'b1; + inv_seq_ierat_snoop_val = 1'b1; + inv_seq_derat_snoop_val = 1'b1; + inv_seq_d = InvSeq_Stg21; + end + + InvSeq_Stg21 : + // locally sourced full invalidate action 6 + if (snoop_ack_q[0:1] == 2'b11) + begin + inv_seq_tlb0fi_inprogress = 1'b0; + inv_seq_tlb0fi_done = 1'b1; + inv_seq_hold_done = {`MM_THREADS{1'b1}}; + inv_seq_d = InvSeq_Idle; // go idle.. + end + else + begin + inv_seq_tlb0fi_inprogress = 1'b1; + inv_seq_d = InvSeq_Stg21; + end + + InvSeq_Stg22 : + // locally sourced table walker load request overlaps with locally sourced full invalidate service from Stg16 + begin + inv_seq_tlb0fi_inprogress = 1'b1; + if (lsu_tokens_q != 2'b00) + begin + inv_seq_htw_load = 1'b1; + htw_lsu_req_taken_sig = 1'b1; + inv_seq_d = InvSeq_Stg16; // back to where you came from + end + else + inv_seq_d = InvSeq_Stg22; // wait for tokens + end + + InvSeq_Stg23 : + // locally sourced table walker load request overlaps with locally sourced local invalidate service from Stg2 + begin + inv_seq_local_inprogress = 1'b1; + if (lsu_tokens_q != 2'b00) + begin + inv_seq_htw_load = 1'b1; + htw_lsu_req_taken_sig = 1'b1; + inv_seq_d = InvSeq_Stg2; // back to where you came from + end + else + inv_seq_d = InvSeq_Stg23; // wait for tokens + end + + //--------- Local tlbwe from tlb_cmp for erat back invalidates + InvSeq_Stg24 : + // locally sourced tlbwe erat back invalidate action 1 + // let hold_req be asserted + begin + inv_seq_tlbwe_inprogress = 1'b1; + if (&(hold_ack_q | tlbwe_back_inv_q[0:`MM_THREADS-1]) == 1'b1) + // this thread held, other threads held and flushed + inv_seq_d = InvSeq_Stg25; + else if (htw_lsu_req_valid == 1'b1) + // table walk load request from htw; could be ucode, so service it + inv_seq_d = InvSeq_Stg29; + else + inv_seq_d = InvSeq_Stg24; + end + + InvSeq_Stg25 : + // locally sourced tlbwe erat back invalidate action 2 + begin + inv_seq_tlbwe_inprogress = 1'b1; + if (iu_mm_lmq_empty == 1'b1 & xu_mm_lmq_stq_empty == 1'b1) + // invalidate the erats + inv_seq_d = InvSeq_Stg26; + else if (htw_lsu_req_valid == 1'b1) + // table walk load request from htw; could hang waiting on empty, so service it + inv_seq_d = InvSeq_Stg29; + else + inv_seq_d = InvSeq_Stg25; // let fetches/loads/stores drain + end + + InvSeq_Stg26 : + // locally sourced tlbwe erat back invalidate action 3 + // invalidate the ERAT's after TLB copy(s) destroyed + begin + inv_seq_tlbwe_inprogress = 1'b1; + inv_seq_ierat_snoop_val = 1'b1; + inv_seq_derat_snoop_val = 1'b1; + inv_seq_d = InvSeq_Stg27; + end + + InvSeq_Stg27 : + // locally sourced tlbwe erat back invalidate action 4 + if (snoop_ack_q[0:1] == 2'b11) + begin + inv_seq_tlbwe_inprogress = 1'b0; + inv_seq_tlbwe_snoop_done = 1'b1; + inv_seq_hold_done = {`MM_THREADS{1'b1}}; + inv_seq_d = InvSeq_Idle; + end + else + begin + inv_seq_tlbwe_inprogress = 1'b1; + inv_seq_d = InvSeq_Stg27; + end + + InvSeq_Stg28 : + // locally sourced table walker load request overlaps with bus snoop service from Stg8 + begin + inv_seq_snoop_inprogress = 1'b1; + if (lsu_tokens_q != 2'b00) // have tokens + begin + inv_seq_htw_load = 1'b1; + htw_lsu_req_taken_sig = 1'b1; + inv_seq_d = InvSeq_Stg8; // back to where you came from + end + else + inv_seq_d = InvSeq_Stg28; // wait for tokens + end + + InvSeq_Stg29 : + // locally sourced table walker load request overlaps with locally sourced tlbwe erat back invalidate service from Stg24 + begin + inv_seq_tlbwe_inprogress = 1'b1; + if (lsu_tokens_q != 2'b00) // have tokens + begin + inv_seq_htw_load = 1'b1; + htw_lsu_req_taken_sig = 1'b1; + inv_seq_d = InvSeq_Stg24; // back to where you came from + end + else + inv_seq_d = InvSeq_Stg29; // wait for tokens + end + + //-------- Hardware Table Walker requests to LSU + InvSeq_Stg31 : + if (lsu_tokens_q != 2'b00) // have tokens + begin + inv_seq_htw_load = 1'b1; + htw_lsu_req_taken_sig = 1'b1; + inv_seq_d = InvSeq_Idle; + end + else + inv_seq_d = InvSeq_Stg31; // wait for tokens + default : + inv_seq_d = InvSeq_Idle; + endcase + end + + assign hold_req_d = inv_seq_hold_req; + assign hold_done_d = inv_seq_hold_done; + // added + // 1. locally sourced local invalidate - hold all threads, flush other threads, not thread doing current op + // 2. locally sourced tlbwe with back invalidate - hold all threads, flush other threads, not thread doing current op + // 3. locally sourced mmucsr0.tlb0fi spr bit set - hold and flush all threads + // 4. bus snoop handled elsewhere by dedicated bus_snoop_hold interface to do early hold and flush all threads + assign iu_flush_req_d[0] = ((~(ex6_valid_q[0])) & inv_seq_local_barrier_set) | ((~(tlbwe_back_inv_q[0])) & inv_seq_hold_req[0] & inv_seq_tlbwe_inprogress) | (inv_seq_hold_req[0] & inv_seq_tlb0fi_inprogress); +`ifdef MM_THREADS2 + assign iu_flush_req_d[1] = ((~(ex6_valid_q[1])) & inv_seq_local_barrier_set) | ((~(tlbwe_back_inv_q[1])) & inv_seq_hold_req[1] & inv_seq_tlbwe_inprogress) | (inv_seq_hold_req[1] & inv_seq_tlb0fi_inprogress); +`endif + assign inv_seq_inprogress_d[0] = inv_seq_snoop_inprogress; + assign inv_seq_inprogress_d[1] = inv_seq_snoop_inprogress; + assign inv_seq_inprogress_d[2] = inv_seq_tlb0fi_inprogress; + assign inv_seq_inprogress_d[3] = inv_seq_tlb0fi_inprogress; + assign inv_seq_inprogress_d[4] = inv_seq_tlbwe_inprogress; + assign inv_seq_inprogress_d[5] = inv_seq_tlbwe_inprogress; + assign inv_seq_snoop_inprogress_q[0] = inv_seq_inprogress_q[0]; + assign inv_seq_snoop_inprogress_q[1] = inv_seq_inprogress_q[1]; + assign inv_seq_tlb0fi_inprogress_q[0] = inv_seq_inprogress_q[2]; + assign inv_seq_tlb0fi_inprogress_q[1] = inv_seq_inprogress_q[3]; + assign inv_seq_tlbwe_inprogress_q[0] = inv_seq_inprogress_q[4]; + assign inv_seq_tlbwe_inprogress_q[1] = inv_seq_inprogress_q[5]; + assign hold_ack_d[0] = ((inv_seq_local_done == 1'b1 | inv_seq_tlb0fi_done == 1'b1 | inv_seq_tlbwe_snoop_done == 1'b1)) ? 1'b0 : + (hold_ack_q[0] == 1'b0) ? iu_mm_hold_ack[0] : + hold_ack_q[0]; +`ifdef MM_THREADS2 + assign hold_ack_d[1] = ((inv_seq_local_done == 1'b1 | inv_seq_tlb0fi_done == 1'b1 | inv_seq_tlbwe_snoop_done == 1'b1)) ? 1'b0 : + (hold_ack_q[1] == 1'b0) ? iu_mm_hold_ack[1] : + hold_ack_q[1]; +`endif + + always @(bus_snoop_seq_q or inval_snoop_forme or bus_snoop_hold_ack_q or inv_seq_snoop_done or power_managed_q) + begin: Bus_Snoop_Sequencer + bus_snoop_seq_idle = 1'b0; + bus_snoop_seq_hold_req = 1'b0; + bus_snoop_seq_ready = 1'b0; + bus_snoop_seq_done = 1'b0; + case (bus_snoop_seq_q) + SnoopSeq_Idle : + if (inval_snoop_forme == 1'b1) + begin + bus_snoop_seq_idle = 1'b0; + bus_snoop_seq_hold_req = 1'b1; + bus_snoop_seq_d = SnoopSeq_Stg1; + end + else + begin + bus_snoop_seq_idle = 1'b1; + bus_snoop_seq_d = SnoopSeq_Idle; + end + SnoopSeq_Stg1 : + if (&(bus_snoop_hold_ack_q) == 1'b1 | (power_managed_q[0] == 1'b1 & power_managed_q[2] == 1'b1)) + bus_snoop_seq_d = SnoopSeq_Stg3; + else + bus_snoop_seq_d = SnoopSeq_Stg1; + + SnoopSeq_Stg3 : + begin + bus_snoop_seq_ready = 1'b1; + if (inv_seq_snoop_done == 1'b1) + bus_snoop_seq_d = SnoopSeq_Stg2; + else + bus_snoop_seq_d = SnoopSeq_Stg3; + end + + SnoopSeq_Stg2 : + begin + bus_snoop_seq_done = 1'b1; + bus_snoop_seq_d = SnoopSeq_Idle; + end + + default : + bus_snoop_seq_d = SnoopSeq_Idle; + endcase + end + assign bus_snoop_hold_req_d[0] = bus_snoop_seq_hold_req; + assign bus_snoop_hold_done_d[0] = bus_snoop_seq_done; + assign bus_snoop_hold_ack_d[0] = ((inv_seq_snoop_done == 1'b1)) ? 1'b0 : + (bus_snoop_hold_ack_q[0] == 1'b0) ? iu_mm_bus_snoop_hold_ack[0] : + bus_snoop_hold_ack_q[0]; +`ifdef MM_THREADS2 + assign bus_snoop_hold_req_d[1] = bus_snoop_seq_hold_req; + assign bus_snoop_hold_done_d[1] = bus_snoop_seq_done; + assign bus_snoop_hold_ack_d[1] = ((inv_seq_snoop_done == 1'b1)) ? 1'b0 : + (bus_snoop_hold_ack_q[1] == 1'b0) ? iu_mm_bus_snoop_hold_ack[1] : + bus_snoop_hold_ack_q[1]; +`endif + assign mm_iu_hold_req = hold_req_q; + assign mm_iu_hold_done = hold_done_q; + assign mm_iu_flush_req = iu_flush_req_q; + assign mm_iu_bus_snoop_hold_req = bus_snoop_hold_req_q; + assign mm_iu_bus_snoop_hold_done = bus_snoop_hold_done_q; + assign mm_iu_tlbi_complete = tlbi_complete_q; + assign mm_xu_illeg_instr = ex7_illeg_instr_q; + assign mm_xu_illeg_instr_ored = |(ex7_illeg_instr_q); + assign mm_xu_ex3_flush_req = ex3_flush_req_q; + assign mm_xu_local_snoop_reject = ex4_ivax_lpid_reject_q; + assign mmq_inval_tlb0fi_done = inv_seq_tlb0fi_done; + assign mm_xu_ord_n_flush_req = ex3_flush_req_q; + assign mm_xu_ord_np1_flush_req = ord_np1_flush_q; + assign mm_xu_ord_read_done = ord_read_done_q; + assign mm_xu_ord_write_done = ord_write_done_q; + assign mm_xu_ord_n_flush_req_ored = |(ex3_flush_req_q); + assign mm_xu_ord_np1_flush_req_ored = |(ord_np1_flush_q); + assign mm_xu_ord_read_done_ored = |(ord_read_done_q); + assign mm_xu_ord_write_done_ored = |(ord_write_done_q); + assign mm_xu_itag_d = ((|(ex2_ttype_q[0:3]) == 1'b1 & (inv_seq_idle == 1'b0 | (|(ex3_valid_q) == 1'b1 & |(ex3_ttype_q[0:3]) == 1'b1) | (|(ex4_valid_q) == 1'b1 & |(ex4_ttype_q[0:3]) == 1'b1) | (|(ex5_valid_q) == 1'b1 & |(ex5_ttype_q[0:3]) == 1'b1) | (|(ex6_valid_q) == 1'b1 & |(ex6_ttype_q[0:3]) == 1'b1)))) ? ex2_itag_q : + (|(tlb_ctl_ex2_flush_req) == 1'b1) ? tlb_ctl_ex2_itag : + ((tlbwe_back_inv_q[`MM_THREADS] == 1'b1 & cswitch_q[2] == 1'b0)) ? mm_xu_itag_q : + tlb_tag4_itag; + assign mm_xu_itag = mm_xu_itag_q; + + //--------------------------------------------------------------------- + // L2 snoop invalidate capture latch signals + //--------------------------------------------------------------------- + // seeing an active mmu target snoop with my lpar id + assign inval_snoop_forme = ( an_ac_back_inv_q[2] & an_ac_back_inv_q[3] & (~(power_managed_q[0] & power_managed_q[1])) & (xu_mm_ccr2_notlb_q[0] == MMU_Mode_Value) & ~mmucr1_q[pos_tlbi_rej] ) | + ( an_ac_back_inv_q[2] & an_ac_back_inv_q[3] & (~(power_managed_q[0] & power_managed_q[1])) & (an_ac_back_inv_lpar_id_q == lpidr_q) ); + + // ttype <= tlbilx & tlbivax & eratilx & erativax; + assign inval_snoop_local_reject = ( an_ac_back_inv_q[2] & an_ac_back_inv_q[3] & (~(power_managed_q[0] & power_managed_q[1])) & an_ac_back_inv_q[7] & + (~(an_ac_back_inv_lpar_id_q == lpidr_q)) & ((xu_mm_ccr2_notlb_q[0] == ERAT_Mode_Value) | mmucr1_q[pos_tlbi_rej]) ); + + // local snoop reject mcheck to xu and pc fir's, local core caused snoop, but rejected due to lpid mismatch + assign local_snoop_reject_d = (global_barrier_q & {`MM_THREADS{inval_snoop_local_reject}}) | + (ex3_ivax_lpid_reject_q & ~ex3_illeg_instr_q & ~ex3_flush_req_q); + + assign local_snoop_reject_ored = |(local_snoop_reject_q); + + //--------------------------------------------------------------------- + // FIR error reporting macro + //--------------------------------------------------------------------- + + tri_direct_err_rpt #(.WIDTH(1)) tlb_snoop_reject_err_rpt( + .vd(vdd), + .gd(gnd), + .err_in(local_snoop_reject_ored), + .err_out(mm_pc_local_snoop_reject_ored) + ); + + // an_ac_back_inv_q: 0=valid b-1, 1=target b-1, 2=valid b, 3=target b, 4=L, 5=GS, 6=IND, 7=local, 8=reject + assign an_ac_back_inv_d[0] = an_ac_back_inv; + assign an_ac_back_inv_d[1] = an_ac_back_inv_target; + assign an_ac_back_inv_d[2] = (inval_snoop_forme == 1'b0) ? an_ac_back_inv_q[0] : + (inv_seq_snoop_done == 1'b1) ? 1'b0 : + an_ac_back_inv_q[2]; + assign an_ac_back_inv_d[3] = (inval_snoop_forme == 1'b0) ? an_ac_back_inv_q[1] : + (inv_seq_snoop_done == 1'b1) ? 1'b0 : + an_ac_back_inv_q[3]; + assign an_ac_back_inv_d[4] = (inval_snoop_forme == 1'b0) ? an_ac_back_inv_lbit : + an_ac_back_inv_q[4]; + assign an_ac_back_inv_d[5] = (inval_snoop_forme == 1'b0) ? an_ac_back_inv_gs : + an_ac_back_inv_q[5]; + assign an_ac_back_inv_d[6] = (inval_snoop_forme == 1'b0) ? an_ac_back_inv_ind : + an_ac_back_inv_q[6]; + assign an_ac_back_inv_d[7] = (inval_snoop_forme == 1'b0) ? an_ac_back_inv_local : + an_ac_back_inv_q[7]; + + // bit 8 is reject back to L2 (b phase) mmu targetted, but lpar id doesn't match (for local or remote snoops) + assign an_ac_back_inv_d[8] = ( an_ac_back_inv_q[2] & an_ac_back_inv_q[3] & (~(an_ac_back_inv_lpar_id_q == lpidr_q)) & ((xu_mm_ccr2_notlb_q[0] == ERAT_Mode_Value) | mmucr1_q[pos_tlbi_rej]) ) | + ( an_ac_back_inv_q[2] & an_ac_back_inv_q[3] & power_managed_q[0] & power_managed_q[1] ); + + assign an_ac_back_inv_addr_d = (inval_snoop_forme == 1'b0) ? an_ac_back_inv_addr : + an_ac_back_inv_addr_q; + assign an_ac_back_inv_lpar_id_d = (inval_snoop_forme == 1'b0) ? an_ac_back_inv_lpar_id : + an_ac_back_inv_lpar_id_q; + assign ac_an_back_inv_reject = an_ac_back_inv_q[8]; + // tlbwe back-invalidate to erats request from tlb_cmp + assign tlbwe_back_inv_d[0:`MM_THREADS-1] = (tlbwe_back_inv_q[`MM_THREADS] == 1'b0) ? tlbwe_back_inv_thdid : + ((tlbwe_back_inv_q[`MM_THREADS] == 1'b1 & tlbwe_back_inv_q[`MM_THREADS+1] == 1'b0 & tlb_tag5_write == 1'b0)) ? {`MM_THREADS{1'b0}} : + (inv_seq_tlbwe_snoop_done == 1'b1) ? {`MM_THREADS{1'b0}} : + tlbwe_back_inv_q[0:`MM_THREADS-1]; + assign tlbwe_back_inv_d[`MM_THREADS] = (tlbwe_back_inv_q[`MM_THREADS] == 1'b0) ? tlbwe_back_inv_valid : + ((tlbwe_back_inv_q[`MM_THREADS] == 1'b1 & tlbwe_back_inv_q[`MM_THREADS+1] == 1'b0 & tlb_tag5_write == 1'b0)) ? 1'b0 : + (inv_seq_tlbwe_snoop_done == 1'b1) ? 1'b0 : + tlbwe_back_inv_q[`MM_THREADS]; + assign tlbwe_back_inv_d[`MM_THREADS+1] = (tlbwe_back_inv_q[`MM_THREADS+1] == 1'b0) ? (tlbwe_back_inv_q[`MM_THREADS] & tlb_tag5_write) : + (inv_seq_tlbwe_snoop_done == 1'b1) ? 1'b0 : + tlbwe_back_inv_q[`MM_THREADS+1]; + assign tlbwe_back_inv_addr_d = (tlbwe_back_inv_q[`MM_THREADS] == 1'b0) ? tlbwe_back_inv_addr : + tlbwe_back_inv_addr_q; + assign tlbwe_back_inv_attr_d = (tlbwe_back_inv_q[`MM_THREADS] == 1'b0) ? tlbwe_back_inv_attr : + tlbwe_back_inv_attr_q; + assign tlbwe_back_inv_pending = |(tlbwe_back_inv_q[`MM_THREADS:`MM_THREADS+1]); + //--------------------------------------------------------------------- + // Load/Store unit request interface + //--------------------------------------------------------------------- + assign htw_lsu_req_taken = htw_lsu_req_taken_sig; + // lsu reserves 1 token for mmu.. lsu_tokens_q initialized to 1, this logic provides for expansion >1 + assign lsu_tokens_d = ((xu_mm_lsu_token == 1'b1 & lsu_tokens_q == 2'b00)) ? 2'b01 : + ((xu_mm_lsu_token == 1'b1 & lsu_tokens_q == 2'b01)) ? 2'b10 : + ((xu_mm_lsu_token == 1'b1 & lsu_tokens_q == 2'b10)) ? 2'b11 : + ((|(lsu_req_q) == 1'b1 & lsu_tokens_q == 2'b11)) ? 2'b10 : + ((|(lsu_req_q) == 1'b1 & lsu_tokens_q == 2'b10)) ? 2'b01 : + ((|(lsu_req_q) == 1'b1 & lsu_tokens_q == 2'b01)) ? 2'b00 : + lsu_tokens_q; + assign lsu_req_d = (lsu_tokens_q == 2'b00) ? {`MM_THREADS{1'b0}} : + `ifdef MM_THREADS2 + (inv_seq_tlbi_complete == 1'b1) ? {1'b1, {`MM_THREADS-1{1'b0}}} : + `else + (inv_seq_tlbi_complete == 1'b1) ? {1'b1} : + `endif + (inv_seq_htw_load == 1'b1) ? htw_lsu_thdid : + (inv_seq_tlbi_load == 1'b1) ? ex6_valid_q : + {`MM_THREADS{1'b0}}; + assign lsu_ttype_d = (inv_seq_tlbi_complete == 1'b1) ? 2'b01 : + (inv_seq_htw_load == 1'b1) ? htw_lsu_ttype : + {2'b0}; + assign lsu_wimge_d = (inv_seq_htw_load == 1'b1) ? htw_lsu_wimge : + {5'b0}; + assign lsu_ubits_d = (inv_seq_htw_load == 1'b1) ? htw_lsu_u : + {4'b0}; + // A2 to L2 interface req_ra epn bits for tlbivax op + // page size mmucr1.tlbi_msb 27:30 31:33 34:35 36:39 40:43 44:47 48:51 TLB w value + // 4K 0 EA(27:30) EA(31:33) EA(34:35) EA(36:39) EA(40:43) EA(44:47) EA(48:51) 31 + // 64K 0 EA(27:30) EA(31:33) EA(34:35) EA(36:39) EA(40:43) EA(44:47) 0b0011 31 + // 1M 0 EA(27:30) EA(31:33) EA(34:35) EA(36:39) EA(40:43) EA(27:30) 0b0101 27 + // 16M 0 EA(27:30) EA(31:33) EA(34:35) EA(36:39) EA(23:26) EA(27:30) 0b0111 23 + // 256M 0 EA(27:30) EA(31:33) EA(34:35) EA(19:22) EA(23:26) EA(27:30) 0b1001 19 + // 1G 0 EA(27:30) EA(31:33) EA(17:18) EA(19:22) EA(23:26) EA(27:30) 0b1010 17 + // 4K 1 EA(27:30) EA(31:33) EA(34:35) EA(36:39) EA(40:43) EA(44:47) EA(48:51) 27 + // 64K 1 EA(27:30) EA(31:33) EA(34:35) EA(36:39) EA(40:43) EA(44:47) 0b0011 27 + // 1M 1 EA(27:30) EA(31:33) EA(34:35) EA(36:39) EA(40:43) EA(23:26) 0b0101 23 + // 16M 1 EA(27:30) EA(31:33) EA(34:35) EA(36:39) EA(19:22) EA(23:26) 0b0111 19 + // 256M 1 EA(27:30) EA(31:33) EA(34:35) EA(15:18) EA(19:22) EA(23:26) 0b1001 15 + // 1G 1 EA(27:30) EA(31:33) EA(13:14) EA(15:18) EA(19:22) EA(23:26) 0b1010 13 + // A2 to L2 interface req_ra for tlbivax op: + // 22:26 TID(1:5) + // 27:51 EPN + // 52 TS + // 53 TID(0) + // 54:55 attributes + // 56:63 TID(6:13) + assign lsu_addr_d[64 - `REAL_ADDR_WIDTH:64 - `REAL_ADDR_WIDTH + 4] = (inv_seq_htw_load == 1'b1) ? htw_lsu_addr[64 - `REAL_ADDR_WIDTH:64 - `REAL_ADDR_WIDTH + 4] : + (inv_seq_tlbi_load == 1'b1) ? ex6_pid_q[`PID_WIDTH - 13:`PID_WIDTH - 9] : + lsu_addr_q[64 - `REAL_ADDR_WIDTH:64 - `REAL_ADDR_WIDTH + 4]; + assign lsu_addr_d[64 - `REAL_ADDR_WIDTH + 5:33] = (inv_seq_htw_load == 1'b1) ? htw_lsu_addr[64 - `REAL_ADDR_WIDTH + 5:33] : + (inv_seq_tlbi_load == 1'b1) ? ex3_ea_q[64 - `REAL_ADDR_WIDTH + 5:33] : + lsu_addr_q[64 - `REAL_ADDR_WIDTH + 5:33]; + assign lsu_addr_d[34:35] = (inv_seq_htw_load == 1'b1) ? htw_lsu_addr[34:35] : + ((inv_seq_tlbi_load == 1'b1 & mmucr1[pos_tlbi_msb] == 1'b1 & ex6_size_q == TLB_PgSize_1GB)) ? ex3_ea_q[13:14] : + ((inv_seq_tlbi_load == 1'b1 & mmucr1[pos_tlbi_msb] == 1'b0 & ex6_size_q == TLB_PgSize_1GB)) ? ex3_ea_q[17:18] : + (inv_seq_tlbi_load == 1'b1) ? ex3_ea_q[34:35] : + lsu_addr_q[34:35]; + assign lsu_addr_d[36:39] = (inv_seq_htw_load == 1'b1) ? htw_lsu_addr[36:39] : + ((inv_seq_tlbi_load == 1'b1 & mmucr1[pos_tlbi_msb] == 1'b1 & (ex6_size_q == TLB_PgSize_1GB | ex6_size_q == TLB_PgSize_256MB))) ? ex3_ea_q[15:18] : + ((inv_seq_tlbi_load == 1'b1 & mmucr1[pos_tlbi_msb] == 1'b0 & (ex6_size_q == TLB_PgSize_1GB | ex6_size_q == TLB_PgSize_256MB))) ? ex3_ea_q[19:22] : + (inv_seq_tlbi_load == 1'b1) ? ex3_ea_q[36:39] : + lsu_addr_q[36:39]; + assign lsu_addr_d[40:41] = (inv_seq_htw_load == 1'b1) ? htw_lsu_addr[40:41] : + ((inv_seq_tlbi_load == 1'b1 & mmucr1[pos_tlbi_msb] == 1'b1 & (ex6_size_q == TLB_PgSize_1GB | ex6_size_q == TLB_PgSize_256MB | ex6_size_q == TLB_PgSize_16MB))) ? ex3_ea_q[19:20] : + ((inv_seq_tlbi_load == 1'b1 & mmucr1[pos_tlbi_msb] == 1'b0 & (ex6_size_q == TLB_PgSize_1GB | ex6_size_q == TLB_PgSize_256MB | ex6_size_q == TLB_PgSize_16MB))) ? ex3_ea_q[23:24] : + (inv_seq_tlbi_load == 1'b1) ? ex3_ea_q[40:41] : + lsu_addr_q[40:41]; + assign lsu_addr_d[42:43] = (inv_seq_htw_load == 1'b1) ? htw_lsu_addr[42:43] : + ((ex6_isel_q[0] == 1'b1 & inv_seq_tlbi_load == 1'b1)) ? ex6_isel_q[1:2] : + ((ex6_isel_q[0] == 1'b0 & inv_seq_tlbi_load == 1'b1 & mmucr1[pos_tlbi_msb] == 1'b1 & (ex6_size_q == TLB_PgSize_1GB | ex6_size_q == TLB_PgSize_256MB | ex6_size_q == TLB_PgSize_16MB))) ? ex3_ea_q[21:22] : + ((ex6_isel_q[0] == 1'b0 & inv_seq_tlbi_load == 1'b1 & mmucr1[pos_tlbi_msb] == 1'b0 & (ex6_size_q == TLB_PgSize_1GB | ex6_size_q == TLB_PgSize_256MB | ex6_size_q == TLB_PgSize_16MB))) ? ex3_ea_q[25:26] : + ((ex6_isel_q[0] == 1'b0 & inv_seq_tlbi_load == 1'b1)) ? ex3_ea_q[42:43] : + lsu_addr_q[42:43]; + assign lsu_addr_d[44:47] = (inv_seq_htw_load == 1'b1) ? htw_lsu_addr[44:47] : + ((inv_seq_tlbi_load == 1'b1 & mmucr1[pos_tlbi_msb] == 1'b1 & (ex6_size_q == TLB_PgSize_1GB | ex6_size_q == TLB_PgSize_256MB | ex6_size_q == TLB_PgSize_16MB | ex6_size_q == TLB_PgSize_1MB))) ? ex3_ea_q[23:26] : + ((inv_seq_tlbi_load == 1'b1 & mmucr1[pos_tlbi_msb] == 1'b0 & (ex6_size_q == TLB_PgSize_1GB | ex6_size_q == TLB_PgSize_256MB | ex6_size_q == TLB_PgSize_16MB | ex6_size_q == TLB_PgSize_1MB))) ? ex3_ea_q[27:30] : + (inv_seq_tlbi_load == 1'b1) ? ex3_ea_q[44:47] : + lsu_addr_q[44:47]; + assign lsu_addr_d[48:51] = (inv_seq_htw_load == 1'b1) ? htw_lsu_addr[48:51] : + (inv_seq_tlbi_load == 1'b1 & ex6_size_large == 1'b1) ? ex6_size_q[0:3] : + (inv_seq_tlbi_load == 1'b1 & ex6_size_large == 1'b0) ? ex3_ea_q[48:51] : + lsu_addr_q[48:51]; + assign lsu_addr_d[52] = (inv_seq_htw_load == 1'b1) ? htw_lsu_addr[52] : + (inv_seq_tlbi_load == 1'b1) ? ex6_ts_q : + lsu_addr_q[52]; + assign lsu_addr_d[53] = (inv_seq_htw_load == 1'b1) ? htw_lsu_addr[53] : + (inv_seq_tlbi_load == 1'b1) ? ex6_pid_q[0] : + lsu_addr_q[53]; + assign lsu_addr_d[54:55] = (inv_seq_htw_load == 1'b1) ? htw_lsu_addr[54:55] : + ((ex6_isel_q[0] == 1'b0 & inv_seq_tlbi_load == 1'b1)) ? ex6_isel_q[1:2] : + ((ex6_isel_q[0] == 1'b1 & inv_seq_tlbi_load == 1'b1)) ? 2'b10 : + lsu_addr_q[54:55]; + assign lsu_addr_d[56:63] = (inv_seq_htw_load == 1'b1) ? htw_lsu_addr[56:63] : + (inv_seq_tlbi_load == 1'b1) ? ex6_pid_q[`PID_WIDTH - 8:`PID_WIDTH - 1] : + lsu_addr_q[56:63]; + assign lsu_lpid_d = (inv_seq_tlbi_load == 1'b1) ? ex6_lpid_q : + lsu_lpid_q; + assign lsu_ind_d = (inv_seq_tlbi_load == 1'b1) ? ex6_ind_q : + lsu_ind_q; + assign lsu_gs_d = (inv_seq_tlbi_load == 1'b1) ? ex6_gs_q : + lsu_gs_q; + assign lsu_lbit_d = ((inv_seq_tlbi_load == 1'b1 & ex6_size_large == 1'b1)) ? 1'b1 : + ((inv_seq_tlbi_load == 1'b1 & ex6_size_large == 1'b0)) ? 1'b0 : + lsu_lbit_q; + assign mm_xu_lsu_req = lsu_req_q; + assign mm_xu_lsu_ttype = lsu_ttype_q; + assign mm_xu_lsu_wimge = lsu_wimge_q; + assign mm_xu_lsu_u = lsu_ubits_q; + assign mm_xu_lsu_addr = lsu_addr_q; + assign mm_xu_lsu_lpid = lsu_lpid_q; + assign mm_xu_lsu_ind = lsu_ind_q; + assign mm_xu_lsu_gs = lsu_gs_q; + assign mm_xu_lsu_lbit = lsu_lbit_q; + //--------------------------------------------------------------------- + // Snoop interfaces to erats and tlb + //--------------------------------------------------------------------- + assign snoop_valid_d[0] = inv_seq_ierat_snoop_val; + assign snoop_valid_d[1] = inv_seq_derat_snoop_val; + assign snoop_valid_d[2] = inv_seq_tlb_snoop_val; + assign snoop_coming_d[0] = inv_seq_tlb0fi_inprogress | inv_seq_tlbwe_inprogress | inv_seq_local_inprogress | inv_seq_snoop_inprogress; + assign snoop_coming_d[1] = snoop_coming_d[0]; + assign snoop_coming_d[2] = snoop_coming_d[0]; + assign snoop_coming_d[3] = snoop_coming_d[0] | mmucr2_act_override; + assign snoop_coming_d[4] = snoop_coming_d[0] | mmucr2_act_override; + generate + if (`REAL_ADDR_WIDTH > 32) + begin : gen64_snoop_attr + assign ex6_tid_nz = |(ex6_pid_q[0:`PID_WIDTH - 1]); + assign back_inv_tid_nz = |({an_ac_back_inv_addr_q[53], an_ac_back_inv_addr_q[22:26], an_ac_back_inv_addr_q[56:63]}); + assign tlbwe_back_inv_tid_nz = |({tlbwe_back_inv_attr_q[20:25], tlbwe_back_inv_attr_q[6:13]}); + assign snoop_attr_d[0] = (~inv_seq_snoop_inprogress_q[0]); + assign snoop_attr_d[1:3] = (inv_seq_snoop_inprogress_q[0] == 1'b1 & an_ac_back_inv_addr_q[54:55] == 2'b10) ? {1'b1, an_ac_back_inv_addr_q[42:43]} : + (inv_seq_snoop_inprogress_q[0] == 1'b1 & an_ac_back_inv_addr_q[54:55] != 2'b10) ? {1'b0, an_ac_back_inv_addr_q[54:55]} : + (inv_seq_tlbwe_inprogress_q[0] == 1'b1) ? 3'b011 : + (ex6_isel_q[0:2] & {3{(~inv_seq_tlb0fi_inprogress_q[0])}}); + assign snoop_attr_d[4:13] = (inv_seq_snoop_inprogress_q[0] == 1'b1) ? {an_ac_back_inv_q[5], an_ac_back_inv_addr_q[52], an_ac_back_inv_addr_q[56:63]} : + (inv_seq_tlbwe_inprogress_q[0] == 1'b1) ? tlbwe_back_inv_attr_q[4:13] : + {ex6_gs_q, ex6_ts_q, ex6_pid_q[`PID_WIDTH - 8:`PID_WIDTH - 1]}; + assign snoop_attr_d[14:17] = (inv_seq_snoop_inprogress_q[0] == 1'b1 & an_ac_back_inv_q[4] == 1'b0) ? 4'b0001 : + (inv_seq_snoop_inprogress_q[0] == 1'b1 & an_ac_back_inv_q[4] == 1'b1) ? an_ac_back_inv_addr_q[48:51] : + (inv_seq_tlbwe_inprogress_q[0] == 1'b1) ? tlbwe_back_inv_attr_q[14:17] : + ex6_size_q[0:3]; + assign snoop_attr_d[18] = (~inv_seq_tlbwe_inprogress_q[0]) | (~tlbwe_back_inv_attr_q[18]); + assign snoop_attr_d[19] = (inv_seq_snoop_inprogress_q[0] == 1'b1) ? back_inv_tid_nz : + (inv_seq_tlbwe_inprogress_q[0] == 1'b1) ? tlbwe_back_inv_tid_nz : + ex6_tid_nz; + assign snoop_attr_tlb_spec_d[18] = 1'b0; + assign snoop_attr_tlb_spec_d[19] = inv_seq_tlb0fi_inprogress_q[0]; + assign snoop_attr_d[20:25] = (inv_seq_snoop_inprogress_q[0] == 1'b1) ? {an_ac_back_inv_addr_q[53], an_ac_back_inv_addr_q[22:26]} : + (inv_seq_tlbwe_inprogress_q[0] == 1'b1) ? tlbwe_back_inv_attr_q[20:25] : + ex6_pid_q[`PID_WIDTH - 14:`PID_WIDTH - 9]; + assign snoop_attr_d[26:33] = (inv_seq_snoop_inprogress_q[0] == 1'b1) ? an_ac_back_inv_lpar_id_q : + (inv_seq_tlbwe_inprogress_q[0] == 1'b1) ? tlbwe_back_inv_attr_q[26:33] : + (inv_seq_tlb0fi_inprogress_q[0] == 1'b1) ? lpidr_q : + ex6_lpid_q; + assign snoop_attr_d[34] = (inv_seq_snoop_inprogress_q[0] == 1'b1) ? an_ac_back_inv_q[6] : + (inv_seq_tlbwe_inprogress_q[0] == 1'b1) ? tlbwe_back_inv_attr_q[34] : + ex6_ind_q; + assign snoop_attr_clone_d[0] = (~inv_seq_snoop_inprogress_q[1]); + assign snoop_attr_clone_d[1:3] = (inv_seq_snoop_inprogress_q[1] == 1'b1 & an_ac_back_inv_addr_q[54:55] == 2'b10) ? {1'b1, an_ac_back_inv_addr_q[42:43]} : + (inv_seq_snoop_inprogress_q[1] == 1'b1 & an_ac_back_inv_addr_q[54:55] != 2'b10) ? {1'b0, an_ac_back_inv_addr_q[54:55]} : + (inv_seq_tlbwe_inprogress_q[1] == 1'b1) ? 3'b011 : + (ex6_isel_q[0:2] & {3{(~inv_seq_tlb0fi_inprogress_q[1])}}); + assign snoop_attr_clone_d[4:13] = (inv_seq_snoop_inprogress_q[1] == 1'b1) ? {an_ac_back_inv_q[5], an_ac_back_inv_addr_q[52], an_ac_back_inv_addr_q[56:63]} : + (inv_seq_tlbwe_inprogress_q[1] == 1'b1) ? tlbwe_back_inv_attr_q[4:13] : + {ex6_gs_q, ex6_ts_q, ex6_pid_q[`PID_WIDTH - 8:`PID_WIDTH - 1]}; + assign snoop_attr_clone_d[14:17] = (inv_seq_snoop_inprogress_q[1] == 1'b1 & an_ac_back_inv_q[4] == 1'b0) ? 4'b0001 : + (inv_seq_snoop_inprogress_q[1] == 1'b1 & an_ac_back_inv_q[4] == 1'b1) ? an_ac_back_inv_addr_q[48:51] : + (inv_seq_tlbwe_inprogress_q[1] == 1'b1) ? tlbwe_back_inv_attr_q[14:17] : + ex6_size_q[0:3]; + assign snoop_attr_clone_d[18] = (~inv_seq_tlbwe_inprogress_q[1]) | (~tlbwe_back_inv_attr_q[18]); + assign snoop_attr_clone_d[19] = (inv_seq_snoop_inprogress_q[1] == 1'b1) ? back_inv_tid_nz : + (inv_seq_tlbwe_inprogress_q[1] == 1'b1) ? tlbwe_back_inv_tid_nz : + ex6_tid_nz; + assign snoop_attr_clone_d[20:25] = (inv_seq_snoop_inprogress_q[1] == 1'b1) ? {an_ac_back_inv_addr_q[53], an_ac_back_inv_addr_q[22:26]} : + (inv_seq_tlbwe_inprogress_q[1] == 1'b1) ? tlbwe_back_inv_attr_q[20:25] : + ex6_pid_q[`PID_WIDTH - 14:`PID_WIDTH - 9]; + end + endgenerate + generate + if (`REAL_ADDR_WIDTH < 33) + begin : gen32_snoop_attr + assign ex6_tid_nz = |(ex6_pid_q[0:`PID_WIDTH - 1]); + assign back_inv_tid_nz = |(an_ac_back_inv_addr_q[56:63]); + assign tlbwe_back_inv_tid_nz = |({tlbwe_back_inv_attr_q[20:25], tlbwe_back_inv_attr_q[6:13]}); + assign snoop_attr_d[0] = (~inv_seq_snoop_inprogress_q[0]); + assign snoop_attr_d[1:3] = (inv_seq_snoop_inprogress_q[0] == 1'b1 & an_ac_back_inv_addr_q[54:55] == 2'b10) ? {1'b1, an_ac_back_inv_addr_q[42:43]} : + (inv_seq_snoop_inprogress_q[0] == 1'b1 & an_ac_back_inv_addr_q[54:55] != 2'b10) ? {1'b0, an_ac_back_inv_addr_q[54:55]} : + (inv_seq_tlbwe_inprogress_q[0] == 1'b1) ? 3'b011 : + ex6_isel_q[0:2]; + assign snoop_attr_d[4:13] = (inv_seq_snoop_inprogress_q[0] == 1'b1) ? {an_ac_back_inv_q[5], an_ac_back_inv_addr_q[52], an_ac_back_inv_addr_q[56:63]} : + (inv_seq_tlbwe_inprogress_q[0] == 1'b1) ? tlbwe_back_inv_attr_q[4:13] : + {ex6_gs_q, ex6_ts_q, ex6_pid_q[`PID_WIDTH - 8:`PID_WIDTH - 1]}; + assign snoop_attr_d[14:17] = (inv_seq_snoop_inprogress_q[0] == 1'b1 & an_ac_back_inv_q[4] == 1'b0) ? 4'b0001 : + (inv_seq_snoop_inprogress_q[0] == 1'b1 & an_ac_back_inv_q[4] == 1'b1) ? an_ac_back_inv_addr_q[48:51] : + (inv_seq_tlbwe_inprogress_q[0] == 1'b1) ? tlbwe_back_inv_attr_q[14:17] : + ex6_size_q[0:3]; + assign snoop_attr_d[18] = (~inv_seq_tlbwe_inprogress_q[0]) | (~tlbwe_back_inv_attr_q[18]); + assign snoop_attr_d[19] = (inv_seq_snoop_inprogress_q[0] == 1'b1) ? back_inv_tid_nz : + (inv_seq_tlbwe_inprogress_q[0] == 1'b1) ? tlbwe_back_inv_tid_nz : + ex6_tid_nz; + assign snoop_attr_tlb_spec_d[18] = 1'b0; + assign snoop_attr_tlb_spec_d[19] = inv_seq_tlb0fi_inprogress_q[0]; + assign snoop_attr_d[20:25] = (inv_seq_snoop_inprogress_q[0] == 1'b1) ? {6{1'b0}} : + (inv_seq_tlbwe_inprogress_q[0] == 1'b1) ? tlbwe_back_inv_attr_q[20:25] : + ex6_pid_q[`PID_WIDTH - 14:`PID_WIDTH - 9]; + assign snoop_attr_d[26:33] = (inv_seq_snoop_inprogress_q[0] == 1'b1) ? an_ac_back_inv_lpar_id_q : + (inv_seq_tlbwe_inprogress_q[0] == 1'b1) ? tlbwe_back_inv_attr_q[26:33] : + (inv_seq_tlb0fi_inprogress_q[0] == 1'b1) ? lpidr_q : + ex6_lpid_q; + assign snoop_attr_d[34] = (inv_seq_snoop_inprogress_q[0] == 1'b1) ? an_ac_back_inv_q[6] : + (inv_seq_tlbwe_inprogress_q[0] == 1'b1) ? tlbwe_back_inv_attr_q[34] : + ex6_ind_q; + assign snoop_attr_clone_d[0] = (~inv_seq_snoop_inprogress_q[1]); + assign snoop_attr_clone_d[1:3] = (inv_seq_snoop_inprogress_q[1] == 1'b1 & an_ac_back_inv_addr_q[54:55] == 2'b10) ? {1'b1, an_ac_back_inv_addr_q[42:43]} : + (inv_seq_snoop_inprogress_q[1] == 1'b1 & an_ac_back_inv_addr_q[54:55] != 2'b10) ? {1'b0, an_ac_back_inv_addr_q[54:55]} : + (inv_seq_tlbwe_inprogress_q[1] == 1'b1) ? 3'b011 : + ex6_isel_q[0:2]; + assign snoop_attr_clone_d[4:13] = (inv_seq_snoop_inprogress_q[1] == 1'b1) ? {an_ac_back_inv_q[5], an_ac_back_inv_addr_q[52], an_ac_back_inv_addr_q[56:63]} : + (inv_seq_tlbwe_inprogress_q[1] == 1'b1) ? tlbwe_back_inv_attr_q[4:13] : + {ex6_gs_q, ex6_ts_q, ex6_pid_q[`PID_WIDTH - 8:`PID_WIDTH - 1]}; + assign snoop_attr_clone_d[14:17] = (inv_seq_snoop_inprogress_q[1] == 1'b1 & an_ac_back_inv_q[4] == 1'b0) ? 4'b0001 : + (inv_seq_snoop_inprogress_q[1] == 1'b1 & an_ac_back_inv_q[4] == 1'b1) ? an_ac_back_inv_addr_q[48:51] : + (inv_seq_tlbwe_inprogress_q[1] == 1'b1) ? tlbwe_back_inv_attr_q[14:17] : + ex6_size_q[0:3]; + assign snoop_attr_clone_d[18] = (~inv_seq_tlbwe_inprogress_q[1]) | (~tlbwe_back_inv_attr_q[18]); + assign snoop_attr_clone_d[19] = (inv_seq_snoop_inprogress_q[1] == 1'b1) ? back_inv_tid_nz : + (inv_seq_tlbwe_inprogress_q[1] == 1'b1) ? tlbwe_back_inv_tid_nz : + ex6_tid_nz; + assign snoop_attr_clone_d[20:25] = (inv_seq_snoop_inprogress_q[1] == 1'b1) ? {6{1'b0}} : + (inv_seq_tlbwe_inprogress_q[1] == 1'b1) ? tlbwe_back_inv_attr_q[20:25] : + ex6_pid_q[`PID_WIDTH - 14:`PID_WIDTH - 9]; + end + endgenerate + // A2 to L2 interface req_ra epn bits for tlbivax op + // page size mmucr1.tlbi_msb 27:30 31:33 34:35 36:39 40:43 44:47 48:51 TLB w value + // 4K 0 EA(27:30) EA(31:33) EA(34:35) EA(36:39) EA(40:43) EA(44:47) EA(48:51) 31 + // 64K 0 EA(27:30) EA(31:33) EA(34:35) EA(36:39) EA(40:43) EA(44:47) 0b0011 31 + // 1M 0 EA(27:30) EA(31:33) EA(34:35) EA(36:39) EA(40:43) EA(27:30) 0b0101 27 + // 16M 0 EA(27:30) EA(31:33) EA(34:35) EA(36:39) EA(23:26) EA(27:30) 0b0111 23 + // 256M 0 EA(27:30) EA(31:33) EA(34:35) EA(19:22) EA(23:26) EA(27:30) 0b1001 19 + // 1G 0 EA(27:30) EA(31:33) EA(17:18) EA(19:22) EA(23:26) EA(27:30) 0b1010 17 + // 4K 1 EA(27:30) EA(31:33) EA(34:35) EA(36:39) EA(40:43) EA(44:47) EA(48:51) 27 + // 64K 1 EA(27:30) EA(31:33) EA(34:35) EA(36:39) EA(40:43) EA(44:47) 0b0011 27 + // 1M 1 EA(27:30) EA(31:33) EA(34:35) EA(36:39) EA(40:43) EA(23:26) 0b0101 23 + // 16M 1 EA(27:30) EA(31:33) EA(34:35) EA(36:39) EA(19:22) EA(23:26) 0b0111 19 + // 256M 1 EA(27:30) EA(31:33) EA(34:35) EA(15:18) EA(19:22) EA(23:26) 0b1001 15 + // 1G 1 EA(27:30) EA(31:33) EA(13:14) EA(15:18) EA(19:22) EA(23:26) 0b1010 13 + // A2 to L2 interface req_ra for tlbivax op: + // 22:26 TID(1:5) + // 27:51 EPN + // 52 TS + // 53 TID(0) + // 54:55 attributes + // 56:63 TID(6:13) + generate + if ((`RS_DATA_WIDTH > `EPN_WIDTH - 1) & (`EPN_WIDTH > `REAL_ADDR_WIDTH)) + begin : gen_rs_gte_epn_snoop_vpn + assign snoop_vpn_d[52 - `EPN_WIDTH:12] = (inv_seq_snoop_inprogress_q[0] == 1'b1) ? {13{1'b0}} : + (inv_seq_tlbwe_inprogress_q[0] == 1'b1) ? tlbwe_back_inv_addr_q[0:12] : + ex3_ea_q[52 - `EPN_WIDTH:12]; + assign snoop_vpn_d[13:14] = ((inv_seq_snoop_inprogress_q[0] == 1'b1 & an_ac_back_inv_q[4] == 1'b1 & mmucr1_q[pos_tlbi_msb] == 1'b1 & an_ac_back_inv_addr_q[48:51] == TLB_PgSize_1GB)) ? an_ac_back_inv_addr_q[34:35] : + (inv_seq_snoop_inprogress_q[0] == 1'b1) ? {2{1'b0}} : + (inv_seq_tlbwe_inprogress_q[0] == 1'b1) ? tlbwe_back_inv_addr_q[13:14] : + ex3_ea_q[13:14]; + assign snoop_vpn_d[15:16] = ((inv_seq_snoop_inprogress_q[0] == 1'b1 & an_ac_back_inv_q[4] == 1'b1 & mmucr1_q[pos_tlbi_msb] == 1'b1 & (an_ac_back_inv_addr_q[48:51] == TLB_PgSize_1GB | an_ac_back_inv_addr_q[48:51] == TLB_PgSize_256MB))) ? an_ac_back_inv_addr_q[36:37] : + (inv_seq_snoop_inprogress_q[0] == 1'b1) ? {2{1'b0}} : + (inv_seq_tlbwe_inprogress_q[0] == 1'b1) ? tlbwe_back_inv_addr_q[15:16] : + ex3_ea_q[15:16]; + assign snoop_vpn_d[17:18] = ((inv_seq_snoop_inprogress_q[0] == 1'b1 & an_ac_back_inv_q[4] == 1'b1 & mmucr1_q[pos_tlbi_msb] == 1'b1 & (an_ac_back_inv_addr_q[48:51] == TLB_PgSize_1GB | an_ac_back_inv_addr_q[48:51] == TLB_PgSize_256MB))) ? an_ac_back_inv_addr_q[38:39] : + ((inv_seq_snoop_inprogress_q[0] == 1'b1 & an_ac_back_inv_q[4] == 1'b1 & mmucr1_q[pos_tlbi_msb] == 1'b0 & an_ac_back_inv_addr_q[48:51] == TLB_PgSize_1GB)) ? an_ac_back_inv_addr_q[34:35] : + (inv_seq_snoop_inprogress_q[0] == 1'b1) ? {2{1'b0}} : + (inv_seq_tlbwe_inprogress_q[0] == 1'b1) ? tlbwe_back_inv_addr_q[17:18] : + ex3_ea_q[17:18]; + assign snoop_vpn_d[19:22] = ((inv_seq_snoop_inprogress_q[0] == 1'b1 & an_ac_back_inv_q[4] == 1'b1 & mmucr1_q[pos_tlbi_msb] == 1'b1 & (an_ac_back_inv_addr_q[48:51] == TLB_PgSize_1GB | an_ac_back_inv_addr_q[48:51] == TLB_PgSize_256MB | an_ac_back_inv_addr_q[48:51] == TLB_PgSize_16MB))) ? an_ac_back_inv_addr_q[40:43] : + ((inv_seq_snoop_inprogress_q[0] == 1'b1 & an_ac_back_inv_q[4] == 1'b1 & mmucr1_q[pos_tlbi_msb] == 1'b0 & (an_ac_back_inv_addr_q[48:51] == TLB_PgSize_1GB | an_ac_back_inv_addr_q[48:51] == TLB_PgSize_256MB))) ? an_ac_back_inv_addr_q[36:39] : + (inv_seq_snoop_inprogress_q[0] == 1'b1) ? {4{1'b0}} : + (inv_seq_tlbwe_inprogress_q[0] == 1'b1) ? tlbwe_back_inv_addr_q[19:22] : + ex3_ea_q[19:22]; + assign snoop_vpn_d[23:26] = ((inv_seq_snoop_inprogress_q[0] == 1'b1 & an_ac_back_inv_q[4] == 1'b1 & mmucr1_q[pos_tlbi_msb] == 1'b1 & (an_ac_back_inv_addr_q[48:51] == TLB_PgSize_1GB | an_ac_back_inv_addr_q[48:51] == TLB_PgSize_256MB | an_ac_back_inv_addr_q[48:51] == TLB_PgSize_16MB | an_ac_back_inv_addr_q[48:51] == TLB_PgSize_1MB))) ? an_ac_back_inv_addr_q[44:47] : + ((inv_seq_snoop_inprogress_q[0] == 1'b1 & an_ac_back_inv_q[4] == 1'b1 & mmucr1_q[pos_tlbi_msb] == 1'b0 & (an_ac_back_inv_addr_q[48:51] == TLB_PgSize_1GB | an_ac_back_inv_addr_q[48:51] == TLB_PgSize_256MB | an_ac_back_inv_addr_q[48:51] == TLB_PgSize_16MB))) ? an_ac_back_inv_addr_q[40:43] : + (inv_seq_snoop_inprogress_q[0] == 1'b1) ? {4{1'b0}} : + (inv_seq_tlbwe_inprogress_q[0] == 1'b1) ? tlbwe_back_inv_addr_q[23:26] : + ex3_ea_q[23:26]; + assign snoop_vpn_d[27:30] = ((inv_seq_snoop_inprogress_q[0] == 1'b1 & an_ac_back_inv_q[4] == 1'b1 & mmucr1_q[pos_tlbi_msb] == 1'b0 & (an_ac_back_inv_addr_q[48:51] == TLB_PgSize_1GB | an_ac_back_inv_addr_q[48:51] == TLB_PgSize_256MB | an_ac_back_inv_addr_q[48:51] == TLB_PgSize_16MB | an_ac_back_inv_addr_q[48:51] == TLB_PgSize_1MB))) ? an_ac_back_inv_addr_q[44:47] : + (inv_seq_snoop_inprogress_q[0] == 1'b1) ? an_ac_back_inv_addr_q[27:30] : + (inv_seq_tlbwe_inprogress_q[0] == 1'b1) ? tlbwe_back_inv_addr_q[27:30] : + ex3_ea_q[27:30]; + assign snoop_vpn_d[31] = (inv_seq_snoop_inprogress_q[0] == 1'b1) ? an_ac_back_inv_addr_q[31] : + (inv_seq_tlbwe_inprogress_q[0] == 1'b1) ? tlbwe_back_inv_addr_q[31] : + ex3_ea_q[31]; + assign snoop_vpn_clone_d[52 - `EPN_WIDTH:12] = (inv_seq_snoop_inprogress_q[1] == 1'b1) ? {13{1'b0}} : + (inv_seq_tlbwe_inprogress_q[1] == 1'b1) ? tlbwe_back_inv_addr_q[0:12] : + ex3_ea_q[52 - `EPN_WIDTH:12]; + assign snoop_vpn_clone_d[13:14] = ((inv_seq_snoop_inprogress_q[1] == 1'b1 & an_ac_back_inv_q[4] == 1'b1 & mmucr1_q[pos_tlbi_msb] == 1'b1 & an_ac_back_inv_addr_q[48:51] == TLB_PgSize_1GB)) ? an_ac_back_inv_addr_q[34:35] : + (inv_seq_snoop_inprogress_q[1] == 1'b1) ? {2{1'b0}} : + (inv_seq_tlbwe_inprogress_q[1] == 1'b1) ? tlbwe_back_inv_addr_q[13:14] : + ex3_ea_q[13:14]; + assign snoop_vpn_clone_d[15:16] = ((inv_seq_snoop_inprogress_q[1] == 1'b1 & an_ac_back_inv_q[4] == 1'b1 & mmucr1_q[pos_tlbi_msb] == 1'b1 & (an_ac_back_inv_addr_q[48:51] == TLB_PgSize_1GB | an_ac_back_inv_addr_q[48:51] == TLB_PgSize_256MB))) ? an_ac_back_inv_addr_q[36:37] : + (inv_seq_snoop_inprogress_q[1] == 1'b1) ? {2{1'b0}} : + (inv_seq_tlbwe_inprogress_q[1] == 1'b1) ? tlbwe_back_inv_addr_q[15:16] : + ex3_ea_q[15:16]; + assign snoop_vpn_clone_d[17:18] = ((inv_seq_snoop_inprogress_q[1] == 1'b1 & an_ac_back_inv_q[4] == 1'b1 & mmucr1_q[pos_tlbi_msb] == 1'b1 & (an_ac_back_inv_addr_q[48:51] == TLB_PgSize_1GB | an_ac_back_inv_addr_q[48:51] == TLB_PgSize_256MB))) ? an_ac_back_inv_addr_q[38:39] : + ((inv_seq_snoop_inprogress_q[1] == 1'b1 & an_ac_back_inv_q[4] == 1'b1 & mmucr1_q[pos_tlbi_msb] == 1'b0 & an_ac_back_inv_addr_q[48:51] == TLB_PgSize_1GB)) ? an_ac_back_inv_addr_q[34:35] : + (inv_seq_snoop_inprogress_q[1] == 1'b1) ? {2{1'b0}} : + (inv_seq_tlbwe_inprogress_q[1] == 1'b1) ? tlbwe_back_inv_addr_q[17:18] : + ex3_ea_q[17:18]; + assign snoop_vpn_clone_d[19:22] = ((inv_seq_snoop_inprogress_q[1] == 1'b1 & an_ac_back_inv_q[4] == 1'b1 & mmucr1_q[pos_tlbi_msb] == 1'b1 & (an_ac_back_inv_addr_q[48:51] == TLB_PgSize_1GB | an_ac_back_inv_addr_q[48:51] == TLB_PgSize_256MB | an_ac_back_inv_addr_q[48:51] == TLB_PgSize_16MB))) ? an_ac_back_inv_addr_q[40:43] : + ((inv_seq_snoop_inprogress_q[1] == 1'b1 & an_ac_back_inv_q[4] == 1'b1 & mmucr1_q[pos_tlbi_msb] == 1'b0 & (an_ac_back_inv_addr_q[48:51] == TLB_PgSize_1GB | an_ac_back_inv_addr_q[48:51] == TLB_PgSize_256MB))) ? an_ac_back_inv_addr_q[36:39] : + (inv_seq_snoop_inprogress_q[1] == 1'b1) ? {4{1'b0}} : + (inv_seq_tlbwe_inprogress_q[1] == 1'b1) ? tlbwe_back_inv_addr_q[19:22] : + ex3_ea_q[19:22]; + assign snoop_vpn_clone_d[23:26] = ((inv_seq_snoop_inprogress_q[1] == 1'b1 & an_ac_back_inv_q[4] == 1'b1 & mmucr1_q[pos_tlbi_msb] == 1'b1 & (an_ac_back_inv_addr_q[48:51] == TLB_PgSize_1GB | an_ac_back_inv_addr_q[48:51] == TLB_PgSize_256MB | an_ac_back_inv_addr_q[48:51] == TLB_PgSize_16MB | an_ac_back_inv_addr_q[48:51] == TLB_PgSize_1MB))) ? an_ac_back_inv_addr_q[44:47] : + ((inv_seq_snoop_inprogress_q[1] == 1'b1 & an_ac_back_inv_q[4] == 1'b1 & mmucr1_q[pos_tlbi_msb] == 1'b0 & (an_ac_back_inv_addr_q[48:51] == TLB_PgSize_1GB | an_ac_back_inv_addr_q[48:51] == TLB_PgSize_256MB | an_ac_back_inv_addr_q[48:51] == TLB_PgSize_16MB))) ? an_ac_back_inv_addr_q[40:43] : + (inv_seq_snoop_inprogress_q[1] == 1'b1) ? {4{1'b0}} : + (inv_seq_tlbwe_inprogress_q[1] == 1'b1) ? tlbwe_back_inv_addr_q[23:26] : + ex3_ea_q[23:26]; + assign snoop_vpn_clone_d[27:30] = ((inv_seq_snoop_inprogress_q[1] == 1'b1 & an_ac_back_inv_q[4] == 1'b1 & mmucr1_q[pos_tlbi_msb] == 1'b0 & (an_ac_back_inv_addr_q[48:51] == TLB_PgSize_1GB | an_ac_back_inv_addr_q[48:51] == TLB_PgSize_256MB | an_ac_back_inv_addr_q[48:51] == TLB_PgSize_16MB | an_ac_back_inv_addr_q[48:51] == TLB_PgSize_1MB))) ? an_ac_back_inv_addr_q[44:47] : + (inv_seq_snoop_inprogress_q[1] == 1'b1) ? an_ac_back_inv_addr_q[27:30] : + (inv_seq_tlbwe_inprogress_q[1] == 1'b1) ? tlbwe_back_inv_addr_q[27:30] : + ex3_ea_q[27:30]; + assign snoop_vpn_clone_d[31] = (inv_seq_snoop_inprogress_q[1] == 1'b1) ? an_ac_back_inv_addr_q[31] : + (inv_seq_tlbwe_inprogress_q[1] == 1'b1) ? tlbwe_back_inv_addr_q[31] : + ex3_ea_q[31]; + end + endgenerate + generate + if (`RS_DATA_WIDTH > `REAL_ADDR_WIDTH - 1) + begin : gen_rs_gte_ra_snoop_vpn + assign snoop_vpn_d[32:51] = (inv_seq_snoop_inprogress_q[0] == 1'b1) ? an_ac_back_inv_addr_q[32:51] : + (inv_seq_tlbwe_inprogress_q[0] == 1'b1) ? tlbwe_back_inv_addr_q[32:51] : + ex3_ea_q[32:51]; + assign snoop_vpn_clone_d[32:51] = (inv_seq_snoop_inprogress_q[1] == 1'b1) ? an_ac_back_inv_addr_q[32:51] : + (inv_seq_tlbwe_inprogress_q[1] == 1'b1) ? tlbwe_back_inv_addr_q[32:51] : + ex3_ea_q[32:51]; + end + endgenerate + generate + if (`RS_DATA_WIDTH < `REAL_ADDR_WIDTH) + begin : gen_ra_gt_rs_snoop_vpn + assign snoop_vpn_d[64 - `REAL_ADDR_WIDTH:51] = (inv_seq_snoop_inprogress_q[0] == 1'b1) ? an_ac_back_inv_addr_q[64 - `REAL_ADDR_WIDTH:51] : + (inv_seq_tlbwe_inprogress_q[0] == 1'b1) ? tlbwe_back_inv_addr_q[64 - `REAL_ADDR_WIDTH:51] : + {1'b0, ex3_ea_q[64 - `RS_DATA_WIDTH:51]}; + assign snoop_vpn_clone_d[64 - `REAL_ADDR_WIDTH:51] = (inv_seq_snoop_inprogress_q[1] == 1'b1) ? an_ac_back_inv_addr_q[64 - `REAL_ADDR_WIDTH:51] : + (inv_seq_tlbwe_inprogress_q[1] == 1'b1) ? tlbwe_back_inv_addr_q[64 - `REAL_ADDR_WIDTH:51] : + {1'b0, ex3_ea_q[64 - `RS_DATA_WIDTH:51]}; + end + endgenerate + generate + if ((`EPN_WIDTH > `REAL_ADDR_WIDTH) & (`RS_DATA_WIDTH < `EPN_WIDTH)) + begin : gen_epn_gt_rs_snoop_vpn + assign snoop_vpn_d[52 - `EPN_WIDTH:63 - `REAL_ADDR_WIDTH] = {22{1'b0}}; + assign snoop_vpn_clone_d[52 - `EPN_WIDTH:63 - `REAL_ADDR_WIDTH] = {22{1'b0}}; + end + endgenerate + assign snoop_ack_d[0] = (snoop_ack_q[0] == 1'b0) ? iu_mm_ierat_snoop_ack : + ((inv_seq_snoop_done == 1'b1 | inv_seq_local_done == 1'b1 | inv_seq_tlb0fi_done == 1'b1 | inv_seq_tlbwe_snoop_done == 1'b1)) ? 1'b0 : + snoop_ack_q[0]; + assign snoop_ack_d[1] = (snoop_ack_q[1] == 1'b0) ? xu_mm_derat_snoop_ack : + ((inv_seq_snoop_done == 1'b1 | inv_seq_local_done == 1'b1 | inv_seq_tlb0fi_done == 1'b1 | inv_seq_tlbwe_snoop_done == 1'b1)) ? 1'b0 : + snoop_ack_q[1]; + assign snoop_ack_d[2] = (snoop_ack_q[2] == 1'b0) ? tlb_snoop_ack : + ((inv_seq_snoop_done == 1'b1 | inv_seq_local_done == 1'b1 | inv_seq_tlb0fi_done == 1'b1 | inv_seq_tlbwe_snoop_done == 1'b1)) ? 1'b0 : + snoop_ack_q[2]; + assign mm_iu_ierat_snoop_coming = snoop_coming_q[0]; + assign mm_iu_ierat_snoop_val = snoop_valid_q[0]; + assign mm_iu_ierat_snoop_attr = snoop_attr_q[0:25]; + assign mm_iu_ierat_snoop_vpn = snoop_vpn_q; + assign mm_xu_derat_snoop_coming = snoop_coming_q[1]; + assign mm_xu_derat_snoop_val = snoop_valid_q[1]; + assign mm_xu_derat_snoop_attr = snoop_attr_clone_q[0:25]; + assign mm_xu_derat_snoop_vpn = snoop_vpn_clone_q; + assign tlb_snoop_coming = snoop_coming_q[2]; + assign tlb_snoop_val = snoop_valid_q[2]; + assign tlb_snoop_attr[0:17] = snoop_attr_q[0:17]; + assign tlb_snoop_attr[18:19] = snoop_attr_tlb_spec_q[18:19]; + assign tlb_snoop_attr[20:34] = snoop_attr_q[20:34]; + assign tlb_snoop_vpn = snoop_vpn_q; + assign xu_mm_ccr2_notlb_b = (~xu_mm_ccr2_notlb_q[1:12]); + assign xu_mm_epcr_dgtmi = xu_mm_epcr_dgtmi_q; + assign inval_perf_tlbilx = inv_seq_local_done & (~inv_seq_tlbi_load); + assign inval_perf_tlbivax = inv_seq_local_done & inv_seq_tlbi_load; + assign inval_perf_tlbivax_snoop = inv_seq_snoop_done; + assign inval_perf_tlb_flush = |(ex3_flush_req_q); + assign inval_dbg_seq_q = inv_seq_q[1:5]; + assign inval_dbg_seq_idle = inv_seq_idle; + assign inval_dbg_seq_snoop_inprogress = inv_seq_snoop_inprogress; + assign inval_dbg_seq_snoop_done = inv_seq_snoop_done; + assign inval_dbg_seq_local_done = inv_seq_local_done; + assign inval_dbg_seq_tlb0fi_done = inv_seq_tlb0fi_done; + assign inval_dbg_seq_tlbwe_snoop_done = inv_seq_tlbwe_snoop_done; + assign inval_dbg_ex6_valid = |(ex6_valid_q); + `ifdef MM_THREADS2 + assign inval_dbg_ex6_thdid[0] = 1'b0; + assign inval_dbg_ex6_thdid[1] = ex6_valid_q[1]; + `else + assign inval_dbg_ex6_thdid[0] = 1'b0; + assign inval_dbg_ex6_thdid[1] = 1'b0; + `endif + assign inval_dbg_ex6_ttype[0] = (ex6_ttype_q[4] | ex6_ttype_q[5]); + assign inval_dbg_ex6_ttype[1] = (ex6_ttype_q[2] | ex6_ttype_q[3]); + assign inval_dbg_ex6_ttype[2] = (ex6_ttype_q[1] | ex6_ttype_q[3] | ex6_ttype_q[5]); + assign inval_dbg_snoop_forme = inval_snoop_forme; + assign inval_dbg_snoop_local_reject = inval_snoop_local_reject | |(ex3_ivax_lpid_reject_q); + assign inval_dbg_an_ac_back_inv_q = an_ac_back_inv_q[2:8]; + assign inval_dbg_an_ac_back_inv_lpar_id_q = an_ac_back_inv_lpar_id_q; + assign inval_dbg_an_ac_back_inv_addr_q = an_ac_back_inv_addr_q; + assign inval_dbg_snoop_valid_q = snoop_valid_q; + assign inval_dbg_snoop_ack_q = snoop_ack_q; + assign inval_dbg_snoop_attr_q = snoop_attr_q; + assign inval_dbg_snoop_attr_tlb_spec_q = snoop_attr_tlb_spec_q; + assign inval_dbg_snoop_vpn_q = snoop_vpn_q[17:51]; + assign inval_dbg_lsu_tokens_q = lsu_tokens_q; + // unused spare signal assignments + assign unused_dc[0] = |(lcb_delay_lclkr_dc[1:4]); + assign unused_dc[1] = |(lcb_mpw1_dc_b[1:4]); + assign unused_dc[2] = pc_func_sl_force; + assign unused_dc[3] = pc_func_sl_thold_0_b; + assign unused_dc[4] = tc_scan_dis_dc_b; + assign unused_dc[5] = tc_scan_diag_dc; + assign unused_dc[6] = tc_lbist_en_dc; + `ifdef MM_THREADS2 + assign unused_dc[7] = mmucr0_0[4] | mmucr0_1[4]; + assign unused_dc[8] = mmucr0_0[5] | mmucr0_1[5]; + `else + assign unused_dc[7] = mmucr0_0[4]; + assign unused_dc[8] = mmucr0_0[5]; + `endif + assign unused_dc[9] = |(tlb_tag5_except); + assign unused_dc[10] = mmucr1_q[13]; + assign unused_dc[11] = |(mmucr1_q[15:17]); + assign unused_dc[12] = ex5_rs_is_q[0] | bus_snoop_seq_idle; + + //------------------------------------------------ + // latches + //------------------------------------------------ + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex1_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex1_valid_offset:ex1_valid_offset + `MM_THREADS - 1]), + .scout(sov[ex1_valid_offset:ex1_valid_offset + `MM_THREADS - 1]), + .din(ex1_valid_d), + .dout(ex1_valid_q) + ); + + tri_rlmreg_p #(.WIDTH((`MMQ_INVAL_TTYPE_WIDTH-2)), .INIT(0), .NEEDS_SRESET(1)) ex1_ttype_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex1_ttype_offset:ex1_ttype_offset + (`MMQ_INVAL_TTYPE_WIDTH-2) - 1]), + .scout(sov[ex1_ttype_offset:ex1_ttype_offset + (`MMQ_INVAL_TTYPE_WIDTH-2) - 1]), + .din(ex1_ttype_d), + .dout(ex1_ttype_q) + ); + + tri_rlmreg_p #(.WIDTH(`MMQ_INVAL_STATE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex1_state_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex1_state_offset:ex1_state_offset + `MMQ_INVAL_STATE_WIDTH - 1]), + .scout(sov[ex1_state_offset:ex1_state_offset + `MMQ_INVAL_STATE_WIDTH - 1]), + .din(ex1_state_d[0:`MMQ_INVAL_STATE_WIDTH - 1]), + .dout(ex1_state_q[0:`MMQ_INVAL_STATE_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`T_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex1_t_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex1_t_offset:ex1_t_offset + `T_WIDTH - 1]), + .scout(sov[ex1_t_offset:ex1_t_offset + `T_WIDTH - 1]), + .din(ex1_t_d[0:`T_WIDTH - 1]), + .dout(ex1_t_q[0:`T_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex1_itag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex1_itag_offset:ex1_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[ex1_itag_offset:ex1_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(ex1_itag_d), + .dout(ex1_itag_q) + ); + //----------------------------------------------------------------------------- + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex2_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex2_valid_offset:ex2_valid_offset + `MM_THREADS - 1]), + .scout(sov[ex2_valid_offset:ex2_valid_offset + `MM_THREADS - 1]), + .din(ex2_valid_d), + .dout(ex2_valid_q) + ); + + tri_rlmreg_p #(.WIDTH(`MMQ_INVAL_TTYPE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex2_ttype_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex2_ttype_offset:ex2_ttype_offset + `MMQ_INVAL_TTYPE_WIDTH - 1]), + .scout(sov[ex2_ttype_offset:ex2_ttype_offset + `MMQ_INVAL_TTYPE_WIDTH - 1]), + .din(ex2_ttype_d[0:`MMQ_INVAL_TTYPE_WIDTH - 1]), + .dout(ex2_ttype_q[0:`MMQ_INVAL_TTYPE_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`RS_IS_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex2_rs_is_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex2_rs_is_offset:ex2_rs_is_offset + `RS_IS_WIDTH - 1]), + .scout(sov[ex2_rs_is_offset:ex2_rs_is_offset + `RS_IS_WIDTH - 1]), + .din(ex2_rs_is_d[0:`RS_IS_WIDTH - 1]), + .dout(ex2_rs_is_q[0:`RS_IS_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`MMQ_INVAL_STATE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex2_state_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex2_state_offset:ex2_state_offset + `MMQ_INVAL_STATE_WIDTH - 1]), + .scout(sov[ex2_state_offset:ex2_state_offset + `MMQ_INVAL_STATE_WIDTH - 1]), + .din(ex2_state_d[0:`MMQ_INVAL_STATE_WIDTH - 1]), + .dout(ex2_state_q[0:`MMQ_INVAL_STATE_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`T_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex2_t_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex2_t_offset:ex2_t_offset + `T_WIDTH - 1]), + .scout(sov[ex2_t_offset:ex2_t_offset + `T_WIDTH - 1]), + .din(ex2_t_d[0:`T_WIDTH - 1]), + .dout(ex2_t_q[0:`T_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex2_itag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex2_itag_offset:ex2_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[ex2_itag_offset:ex2_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(ex2_itag_d), + .dout(ex2_itag_q) + ); + //----------------------------------------------------------------------------- + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex3_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex3_valid_offset:ex3_valid_offset + `MM_THREADS - 1]), + .scout(sov[ex3_valid_offset:ex3_valid_offset + `MM_THREADS - 1]), + .din(ex3_valid_d), + .dout(ex3_valid_q) + ); + + tri_rlmreg_p #(.WIDTH(`MMQ_INVAL_TTYPE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex3_ttype_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex3_ttype_offset:ex3_ttype_offset + `MMQ_INVAL_TTYPE_WIDTH - 1]), + .scout(sov[ex3_ttype_offset:ex3_ttype_offset + `MMQ_INVAL_TTYPE_WIDTH - 1]), + .din(ex3_ttype_d[0:`MMQ_INVAL_TTYPE_WIDTH - 1]), + .dout(ex3_ttype_q[0:`MMQ_INVAL_TTYPE_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`RS_IS_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex3_rs_is_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex3_rs_is_offset:ex3_rs_is_offset + `RS_IS_WIDTH - 1]), + .scout(sov[ex3_rs_is_offset:ex3_rs_is_offset + `RS_IS_WIDTH - 1]), + .din(ex3_rs_is_d[0:`RS_IS_WIDTH - 1]), + .dout(ex3_rs_is_q[0:`RS_IS_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`MMQ_INVAL_STATE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex3_state_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex3_state_offset:ex3_state_offset + `MMQ_INVAL_STATE_WIDTH - 1]), + .scout(sov[ex3_state_offset:ex3_state_offset + `MMQ_INVAL_STATE_WIDTH - 1]), + .din(ex3_state_d[0:`MMQ_INVAL_STATE_WIDTH - 1]), + .dout(ex3_state_q[0:`MMQ_INVAL_STATE_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`T_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex3_t_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex3_t_offset:ex3_t_offset + `T_WIDTH - 1]), + .scout(sov[ex3_t_offset:ex3_t_offset + `T_WIDTH - 1]), + .din(ex3_t_d[0:`T_WIDTH - 1]), + .dout(ex3_t_q[0:`T_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex3_flush_req_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex3_flush_req_offset:ex3_flush_req_offset + `MM_THREADS - 1]), + .scout(sov[ex3_flush_req_offset:ex3_flush_req_offset + `MM_THREADS - 1]), + .din(ex3_flush_req_d), + .dout(ex3_flush_req_q) + ); + + tri_rlmreg_p #(.WIDTH(`RS_DATA_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex3_ea_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex3_ea_offset:ex3_ea_offset + `RS_DATA_WIDTH - 1]), + .scout(sov[ex3_ea_offset:ex3_ea_offset + `RS_DATA_WIDTH - 1]), + .din(ex3_ea_d[64 - `RS_DATA_WIDTH:63]), + .dout(ex3_ea_q[64 - `RS_DATA_WIDTH:63]) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex3_itag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex3_itag_offset:ex3_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[ex3_itag_offset:ex3_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(ex3_itag_d), + .dout(ex3_itag_q) + ); + //----------------------------------------------------------------------------- + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex4_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex4_valid_offset:ex4_valid_offset + `MM_THREADS - 1]), + .scout(sov[ex4_valid_offset:ex4_valid_offset + `MM_THREADS - 1]), + .din(ex4_valid_d), + .dout(ex4_valid_q) + ); + + tri_rlmreg_p #(.WIDTH(`MMQ_INVAL_TTYPE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex4_ttype_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex4_ttype_offset:ex4_ttype_offset + `MMQ_INVAL_TTYPE_WIDTH - 1]), + .scout(sov[ex4_ttype_offset:ex4_ttype_offset + `MMQ_INVAL_TTYPE_WIDTH - 1]), + .din(ex4_ttype_d[0:`MMQ_INVAL_TTYPE_WIDTH - 1]), + .dout(ex4_ttype_q[0:`MMQ_INVAL_TTYPE_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`RS_IS_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex4_rs_is_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex4_rs_is_offset:ex4_rs_is_offset + `RS_IS_WIDTH - 1]), + .scout(sov[ex4_rs_is_offset:ex4_rs_is_offset + `RS_IS_WIDTH - 1]), + .din(ex4_rs_is_d[0:`RS_IS_WIDTH - 1]), + .dout(ex4_rs_is_q[0:`RS_IS_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`MMQ_INVAL_STATE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex4_state_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex4_state_offset:ex4_state_offset + `MMQ_INVAL_STATE_WIDTH - 1]), + .scout(sov[ex4_state_offset:ex4_state_offset + `MMQ_INVAL_STATE_WIDTH - 1]), + .din(ex4_state_d[0:`MMQ_INVAL_STATE_WIDTH - 1]), + .dout(ex4_state_q[0:`MMQ_INVAL_STATE_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`T_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex4_t_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex4_t_offset:ex4_t_offset + `T_WIDTH - 1]), + .scout(sov[ex4_t_offset:ex4_t_offset + `T_WIDTH - 1]), + .din(ex4_t_d[0:`T_WIDTH - 1]), + .dout(ex4_t_q[0:`T_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex4_itag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex4_itag_offset:ex4_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[ex4_itag_offset:ex4_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(ex4_itag_d), + .dout(ex4_itag_q) + ); + //------------------------------------------------ + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex5_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex5_valid_offset:ex5_valid_offset + `MM_THREADS - 1]), + .scout(sov[ex5_valid_offset:ex5_valid_offset + `MM_THREADS - 1]), + .din(ex5_valid_d), + .dout(ex5_valid_q) + ); + + tri_rlmreg_p #(.WIDTH(`MMQ_INVAL_TTYPE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex5_ttype_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex5_ttype_offset:ex5_ttype_offset + `MMQ_INVAL_TTYPE_WIDTH - 1]), + .scout(sov[ex5_ttype_offset:ex5_ttype_offset + `MMQ_INVAL_TTYPE_WIDTH - 1]), + .din(ex5_ttype_d[0:`MMQ_INVAL_TTYPE_WIDTH - 1]), + .dout(ex5_ttype_q[0:`MMQ_INVAL_TTYPE_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`RS_IS_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex5_rs_is_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex5_rs_is_offset:ex5_rs_is_offset + `RS_IS_WIDTH - 1]), + .scout(sov[ex5_rs_is_offset:ex5_rs_is_offset + `RS_IS_WIDTH - 1]), + .din(ex5_rs_is_d[0:`RS_IS_WIDTH - 1]), + .dout(ex5_rs_is_q[0:`RS_IS_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`MMQ_INVAL_STATE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex5_state_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex5_state_offset:ex5_state_offset + `MMQ_INVAL_STATE_WIDTH - 1]), + .scout(sov[ex5_state_offset:ex5_state_offset + `MMQ_INVAL_STATE_WIDTH - 1]), + .din(ex5_state_d[0:`MMQ_INVAL_STATE_WIDTH - 1]), + .dout(ex5_state_q[0:`MMQ_INVAL_STATE_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`T_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex5_t_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex5_t_offset:ex5_t_offset + `T_WIDTH - 1]), + .scout(sov[ex5_t_offset:ex5_t_offset + `T_WIDTH - 1]), + .din(ex5_t_d[0:`T_WIDTH - 1]), + .dout(ex5_t_q[0:`T_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex5_itag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex5_itag_offset:ex5_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[ex5_itag_offset:ex5_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(ex5_itag_d), + .dout(ex5_itag_q) + ); + //------------------------------------------------ + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex6_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex6_valid_offset:ex6_valid_offset + `MM_THREADS - 1]), + .scout(sov[ex6_valid_offset:ex6_valid_offset + `MM_THREADS - 1]), + .din(ex6_valid_d), + .dout(ex6_valid_q) + ); + + tri_rlmreg_p #(.WIDTH(`MMQ_INVAL_TTYPE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex6_ttype_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex6_ttype_offset:ex6_ttype_offset + `MMQ_INVAL_TTYPE_WIDTH - 1]), + .scout(sov[ex6_ttype_offset:ex6_ttype_offset + `MMQ_INVAL_TTYPE_WIDTH - 1]), + .din(ex6_ttype_d[0:`MMQ_INVAL_TTYPE_WIDTH - 1]), + .dout(ex6_ttype_q[0:`MMQ_INVAL_TTYPE_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex6_isel_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex6_isel_offset:ex6_isel_offset + 3 - 1]), + .scout(sov[ex6_isel_offset:ex6_isel_offset + 3 - 1]), + .din(ex6_isel_d[0:3 - 1]), + .dout(ex6_isel_q[0:3 - 1]) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ex6_size_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex6_size_offset:ex6_size_offset + 4 - 1]), + .scout(sov[ex6_size_offset:ex6_size_offset + 4 - 1]), + .din(ex6_size_d[0:4 - 1]), + .dout(ex6_size_q[0:4 - 1]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_gs_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex6_gs_offset]), + .scout(sov[ex6_gs_offset]), + .din(ex6_gs_d), + .dout(ex6_gs_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_ts_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex6_ts_offset]), + .scout(sov[ex6_ts_offset]), + .din(ex6_ts_d), + .dout(ex6_ts_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_ind_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex6_ind_offset]), + .scout(sov[ex6_ind_offset]), + .din(ex6_ind_d), + .dout(ex6_ind_q) + ); + + tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex6_pid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex6_pid_offset:ex6_pid_offset + `PID_WIDTH - 1]), + .scout(sov[ex6_pid_offset:ex6_pid_offset + `PID_WIDTH - 1]), + .din(ex6_pid_d[0:`PID_WIDTH - 1]), + .dout(ex6_pid_q[0:`PID_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex6_lpid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex6_lpid_offset:ex6_lpid_offset + `LPID_WIDTH - 1]), + .scout(sov[ex6_lpid_offset:ex6_lpid_offset + `LPID_WIDTH - 1]), + .din(ex6_lpid_d[0:`LPID_WIDTH - 1]), + .dout(ex6_lpid_q[0:`LPID_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex6_itag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex6_itag_offset:ex6_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[ex6_itag_offset:ex6_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(ex6_itag_d), + .dout(ex6_itag_q) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) mm_xu_itag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[mm_xu_itag_offset:mm_xu_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[mm_xu_itag_offset:mm_xu_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(mm_xu_itag_d), + .dout(mm_xu_itag_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ord_np1_flush_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ord_np1_flush_offset:ord_np1_flush_offset + `MM_THREADS - 1]), + .scout(sov[ord_np1_flush_offset:ord_np1_flush_offset + `MM_THREADS - 1]), + .din(ord_np1_flush_d), + .dout(ord_np1_flush_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ord_read_done_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ord_read_done_offset:ord_read_done_offset + `MM_THREADS - 1]), + .scout(sov[ord_read_done_offset:ord_read_done_offset + `MM_THREADS - 1]), + .din(ord_read_done_d), + .dout(ord_read_done_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ord_write_done_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ord_write_done_offset:ord_write_done_offset + `MM_THREADS - 1]), + .scout(sov[ord_write_done_offset:ord_write_done_offset + `MM_THREADS - 1]), + .din(ord_write_done_d), + .dout(ord_write_done_q) + ); + //------------------------------------------------ + + tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) inv_seq_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[inv_seq_offset:inv_seq_offset + 6 - 1]), + .scout(sov[inv_seq_offset:inv_seq_offset + 6 - 1]), + .din(inv_seq_d[0:`INV_SEQ_WIDTH - 1]), + .dout(inv_seq_q[0:`INV_SEQ_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) hold_req_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[hold_req_offset:hold_req_offset + `MM_THREADS - 1]), + .scout(sov[hold_req_offset:hold_req_offset + `MM_THREADS - 1]), + .din(hold_req_d), + .dout(hold_req_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) hold_ack_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[hold_ack_offset:hold_ack_offset + `MM_THREADS - 1]), + .scout(sov[hold_ack_offset:hold_ack_offset + `MM_THREADS - 1]), + .din(hold_ack_d), + .dout(hold_ack_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) hold_done_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[hold_done_offset:hold_done_offset + `MM_THREADS - 1]), + .scout(sov[hold_done_offset:hold_done_offset + `MM_THREADS - 1]), + .din(hold_done_d), + .dout(hold_done_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) iu_flush_req_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[iu_flush_req_offset:iu_flush_req_offset + `MM_THREADS - 1]), + .scout(sov[iu_flush_req_offset:iu_flush_req_offset + `MM_THREADS - 1]), + .din(iu_flush_req_d), + .dout(iu_flush_req_q) + ); + + tri_rlmreg_p #(.WIDTH(`BUS_SNOOP_SEQ_WIDTH), .INIT(0), .NEEDS_SRESET(1)) bus_snoop_seq_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[bus_snoop_seq_offset:bus_snoop_seq_offset + `BUS_SNOOP_SEQ_WIDTH - 1]), + .scout(sov[bus_snoop_seq_offset:bus_snoop_seq_offset + `BUS_SNOOP_SEQ_WIDTH - 1]), + .din(bus_snoop_seq_d), + .dout(bus_snoop_seq_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) bus_snoop_hold_req_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[bus_snoop_hold_req_offset:bus_snoop_hold_req_offset + `MM_THREADS - 1]), + .scout(sov[bus_snoop_hold_req_offset:bus_snoop_hold_req_offset + `MM_THREADS - 1]), + .din(bus_snoop_hold_req_d), + .dout(bus_snoop_hold_req_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) bus_snoop_hold_ack_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[bus_snoop_hold_ack_offset:bus_snoop_hold_ack_offset + `MM_THREADS - 1]), + .scout(sov[bus_snoop_hold_ack_offset:bus_snoop_hold_ack_offset + `MM_THREADS - 1]), + .din(bus_snoop_hold_ack_d), + .dout(bus_snoop_hold_ack_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) bus_snoop_hold_done_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[bus_snoop_hold_done_offset:bus_snoop_hold_done_offset + `MM_THREADS - 1]), + .scout(sov[bus_snoop_hold_done_offset:bus_snoop_hold_done_offset + `MM_THREADS - 1]), + .din(bus_snoop_hold_done_d), + .dout(bus_snoop_hold_done_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) tlbi_complete_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[tlbi_complete_offset:tlbi_complete_offset + `MM_THREADS - 1]), + .scout(sov[tlbi_complete_offset:tlbi_complete_offset + `MM_THREADS - 1]), + .din(tlbi_complete_d), + .dout(tlbi_complete_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) local_barrier_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[local_barrier_offset:local_barrier_offset + `MM_THREADS - 1]), + .scout(sov[local_barrier_offset:local_barrier_offset + `MM_THREADS - 1]), + .din(local_barrier_d), + .dout(local_barrier_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) global_barrier_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[global_barrier_offset:global_barrier_offset + `MM_THREADS - 1]), + .scout(sov[global_barrier_offset:global_barrier_offset + `MM_THREADS - 1]), + .din(global_barrier_d), + .dout(global_barrier_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex3_illeg_instr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex3_illeg_instr_offset:ex3_illeg_instr_offset + `MM_THREADS - 1]), + .scout(sov[ex3_illeg_instr_offset:ex3_illeg_instr_offset + `MM_THREADS - 1]), + .din(ex3_illeg_instr_d), + .dout(ex3_illeg_instr_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex4_illeg_instr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex4_illeg_instr_offset:ex4_illeg_instr_offset + `MM_THREADS - 1]), + .scout(sov[ex4_illeg_instr_offset:ex4_illeg_instr_offset + `MM_THREADS - 1]), + .din(ex4_illeg_instr_d), + .dout(ex4_illeg_instr_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex5_illeg_instr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex5_illeg_instr_offset:ex5_illeg_instr_offset + `MM_THREADS - 1]), + .scout(sov[ex5_illeg_instr_offset:ex5_illeg_instr_offset + `MM_THREADS - 1]), + .din(ex5_illeg_instr_d), + .dout(ex5_illeg_instr_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex6_illeg_instr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex6_illeg_instr_offset:ex6_illeg_instr_offset + `MM_THREADS - 1]), + .scout(sov[ex6_illeg_instr_offset:ex6_illeg_instr_offset + `MM_THREADS - 1]), + .din(ex6_illeg_instr_d), + .dout(ex6_illeg_instr_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex7_illeg_instr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex7_illeg_instr_offset:ex7_illeg_instr_offset + `MM_THREADS - 1]), + .scout(sov[ex7_illeg_instr_offset:ex7_illeg_instr_offset + `MM_THREADS - 1]), + .din(ex7_illeg_instr_d), + .dout(ex7_illeg_instr_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex3_ivax_lpid_reject_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex3_ivax_lpid_reject_offset:ex3_ivax_lpid_reject_offset + `MM_THREADS - 1]), + .scout(sov[ex3_ivax_lpid_reject_offset:ex3_ivax_lpid_reject_offset + `MM_THREADS - 1]), + .din(ex3_ivax_lpid_reject_d), + .dout(ex3_ivax_lpid_reject_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex4_ivax_lpid_reject_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex4_ivax_lpid_reject_offset:ex4_ivax_lpid_reject_offset + `MM_THREADS - 1]), + .scout(sov[ex4_ivax_lpid_reject_offset:ex4_ivax_lpid_reject_offset + `MM_THREADS - 1]), + .din(ex4_ivax_lpid_reject_d), + .dout(ex4_ivax_lpid_reject_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) local_snoop_reject_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[local_snoop_reject_offset:local_snoop_reject_offset + `MM_THREADS - 1]), + .scout(sov[local_snoop_reject_offset:local_snoop_reject_offset + `MM_THREADS - 1]), + .din(local_snoop_reject_d), + .dout(local_snoop_reject_q) + ); + // snoop output and ack latches 0:ierat, 1:derat, 2:tlb + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) snoop_coming_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[snoop_coming_offset:snoop_coming_offset + 5 - 1]), + .scout(sov[snoop_coming_offset:snoop_coming_offset + 5 - 1]), + .din(snoop_coming_d), + .dout(snoop_coming_q) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) snoop_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[snoop_valid_offset:snoop_valid_offset + 3 - 1]), + .scout(sov[snoop_valid_offset:snoop_valid_offset + 3 - 1]), + .din(snoop_valid_d), + .dout(snoop_valid_q) + ); + + tri_rlmreg_p #(.WIDTH(35), .INIT(0), .NEEDS_SRESET(1)) snoop_attr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(snoop_coming_q[3]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[snoop_attr_offset:snoop_attr_offset + 35 - 1]), + .scout(sov[snoop_attr_offset:snoop_attr_offset + 35 - 1]), + .din(snoop_attr_d), + .dout(snoop_attr_q) + ); + + tri_rlmreg_p #(.WIDTH(`EPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) snoop_vpn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(snoop_coming_q[3]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[snoop_vpn_offset:snoop_vpn_offset + `EPN_WIDTH - 1]), + .scout(sov[snoop_vpn_offset:snoop_vpn_offset + `EPN_WIDTH - 1]), + .din(snoop_vpn_d[52 - `EPN_WIDTH:51]), + .dout(snoop_vpn_q[52 - `EPN_WIDTH:51]) + ); + + tri_rlmreg_p #(.WIDTH(26), .INIT(0), .NEEDS_SRESET(1)) snoop_attr_clone_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(snoop_coming_q[4]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[snoop_attr_clone_offset:snoop_attr_clone_offset + 26 - 1]), + .scout(sov[snoop_attr_clone_offset:snoop_attr_clone_offset + 26 - 1]), + .din(snoop_attr_clone_d), + .dout(snoop_attr_clone_q) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) snoop_attr_tlb_spec_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(snoop_coming_q[3]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[snoop_attr_tlb_spec_offset:snoop_attr_tlb_spec_offset + 2 - 1]), + .scout(sov[snoop_attr_tlb_spec_offset:snoop_attr_tlb_spec_offset + 2 - 1]), + .din(snoop_attr_tlb_spec_d), + .dout(snoop_attr_tlb_spec_q) + ); + + tri_rlmreg_p #(.WIDTH(`EPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) snoop_vpn_clone_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(snoop_coming_q[4]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[snoop_vpn_clone_offset:snoop_vpn_clone_offset + `EPN_WIDTH - 1]), + .scout(sov[snoop_vpn_clone_offset:snoop_vpn_clone_offset + `EPN_WIDTH - 1]), + .din(snoop_vpn_clone_d[52 - `EPN_WIDTH:51]), + .dout(snoop_vpn_clone_q[52 - `EPN_WIDTH:51]) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) snoop_ack_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[snoop_ack_offset:snoop_ack_offset + 3 - 1]), + .scout(sov[snoop_ack_offset:snoop_ack_offset + 3 - 1]), + .din(snoop_ack_d), + .dout(snoop_ack_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) mm_xu_quiesce_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[mm_xu_quiesce_offset:mm_xu_quiesce_offset + `MM_THREADS - 1]), + .scout(sov[mm_xu_quiesce_offset:mm_xu_quiesce_offset + `MM_THREADS - 1]), + .din(mm_xu_quiesce_d), + .dout(mm_xu_quiesce_q) + ); + + tri_rlmreg_p #(.WIDTH(4*`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) mm_pc_quiesce_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[mm_pc_quiesce_offset:mm_pc_quiesce_offset + 4*`MM_THREADS - 1]), + .scout(sov[mm_pc_quiesce_offset:mm_pc_quiesce_offset + 4*`MM_THREADS - 1]), + .din(mm_pc_quiesce_d), + .dout(mm_pc_quiesce_q) + ); + + // snoop invalidate input latches + + tri_rlmreg_p #(.WIDTH(9), .INIT(0), .NEEDS_SRESET(1)) an_ac_back_inv_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[an_ac_back_inv_offset:an_ac_back_inv_offset + 9 - 1]), + .scout(sov[an_ac_back_inv_offset:an_ac_back_inv_offset + 9 - 1]), + .din(an_ac_back_inv_d), + .dout(an_ac_back_inv_q) + ); + + tri_rlmreg_p #(.WIDTH(`REAL_ADDR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) an_ac_back_inv_addr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[an_ac_back_inv_addr_offset:an_ac_back_inv_addr_offset + `REAL_ADDR_WIDTH - 1]), + .scout(sov[an_ac_back_inv_addr_offset:an_ac_back_inv_addr_offset + `REAL_ADDR_WIDTH - 1]), + .din(an_ac_back_inv_addr_d[64 - `REAL_ADDR_WIDTH:63]), + .dout(an_ac_back_inv_addr_q[64 - `REAL_ADDR_WIDTH:63]) + ); + + tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) an_ac_back_inv_lpar_id_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[an_ac_back_inv_lpar_id_offset:an_ac_back_inv_lpar_id_offset + `LPID_WIDTH - 1]), + .scout(sov[an_ac_back_inv_lpar_id_offset:an_ac_back_inv_lpar_id_offset + `LPID_WIDTH - 1]), + .din(an_ac_back_inv_lpar_id_d[0:`LPID_WIDTH - 1]), + .dout(an_ac_back_inv_lpar_id_q[0:`LPID_WIDTH - 1]) + ); + // Load/Store unit request interface latches + + tri_rlmreg_p #(.WIDTH(2), .INIT(1), .NEEDS_SRESET(1)) lsu_tokens_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lsu_tokens_offset:lsu_tokens_offset + 2 - 1]), + .scout(sov[lsu_tokens_offset:lsu_tokens_offset + 2 - 1]), + .din(lsu_tokens_d[0:1]), + .dout(lsu_tokens_q[0:1]) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) lsu_req_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lsu_req_offset:lsu_req_offset + `MM_THREADS - 1]), + .scout(sov[lsu_req_offset:lsu_req_offset + `MM_THREADS - 1]), + .din(lsu_req_d), + .dout(lsu_req_q) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) lsu_ttype_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lsu_ttype_offset:lsu_ttype_offset + 2 - 1]), + .scout(sov[lsu_ttype_offset:lsu_ttype_offset + 2 - 1]), + .din(lsu_ttype_d[0:1]), + .dout(lsu_ttype_q[0:1]) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lsu_ubits_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lsu_ubits_offset:lsu_ubits_offset + 4 - 1]), + .scout(sov[lsu_ubits_offset:lsu_ubits_offset + 4 - 1]), + .din(lsu_ubits_d[0:3]), + .dout(lsu_ubits_q[0:3]) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) lsu_wimge_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lsu_wimge_offset:lsu_wimge_offset + 5 - 1]), + .scout(sov[lsu_wimge_offset:lsu_wimge_offset + 5 - 1]), + .din(lsu_wimge_d[0:4]), + .dout(lsu_wimge_q[0:4]) + ); + + tri_rlmreg_p #(.WIDTH(`REAL_ADDR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lsu_addr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lsu_addr_offset:lsu_addr_offset + `REAL_ADDR_WIDTH - 1]), + .scout(sov[lsu_addr_offset:lsu_addr_offset + `REAL_ADDR_WIDTH - 1]), + .din(lsu_addr_d[64 - `REAL_ADDR_WIDTH:63]), + .dout(lsu_addr_q[64 - `REAL_ADDR_WIDTH:63]) + ); + + tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lsu_lpid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lsu_lpid_offset:lsu_lpid_offset + `LPID_WIDTH - 1]), + .scout(sov[lsu_lpid_offset:lsu_lpid_offset + `LPID_WIDTH - 1]), + .din(lsu_lpid_d[0:`LPID_WIDTH - 1]), + .dout(lsu_lpid_q[0:`LPID_WIDTH - 1]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lsu_ind_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lsu_ind_offset]), + .scout(sov[lsu_ind_offset]), + .din(lsu_ind_d), + .dout(lsu_ind_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lsu_gs_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lsu_gs_offset]), + .scout(sov[lsu_gs_offset]), + .din(lsu_gs_d), + .dout(lsu_gs_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lsu_lbit_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lsu_lbit_offset]), + .scout(sov[lsu_lbit_offset]), + .din(lsu_lbit_d), + .dout(lsu_lbit_q) + ); + // core night-night sleep mode + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) power_managed_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[power_managed_offset:power_managed_offset + 4 - 1]), + .scout(sov[power_managed_offset:power_managed_offset + 4 - 1]), + .din(power_managed_d), + .dout(power_managed_q) + ); + + // chicken switches + // 0 - override lsu empty requirement for sending tlbivax + // 1 - override lsu empty requirement for processing incoming tlbivax snoop + // 2 - override wait for tlbwe back_inv erat snoop complete before issuing barrier_done, ord_read_done + // 3 - override i-fetch miss queue empty requirement for processing incoming tlbivax snoop + tri_rlmreg_p #(.WIDTH(4), .INIT(MMQ_INVAL_CSWITCH_0TO3), .NEEDS_SRESET(1)) cswitch_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[cswitch_offset:cswitch_offset + 4 - 1]), + .scout(sov[cswitch_offset:cswitch_offset + 4 - 1]), + .din(cswitch_q), + .dout(cswitch_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS+2), .INIT(0), .NEEDS_SRESET(1)) tlbwe_back_inv_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[tlbwe_back_inv_offset:tlbwe_back_inv_offset + `MM_THREADS + 2 - 1]), + .scout(sov[tlbwe_back_inv_offset:tlbwe_back_inv_offset + `MM_THREADS + 2 - 1]), + .din(tlbwe_back_inv_d[0:`MM_THREADS+1]), + .dout(tlbwe_back_inv_q[0:`MM_THREADS+1]) + ); + + tri_rlmreg_p #(.WIDTH(`EPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlbwe_back_inv_addr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[tlbwe_back_inv_addr_offset:tlbwe_back_inv_addr_offset + `EPN_WIDTH - 1]), + .scout(sov[tlbwe_back_inv_addr_offset:tlbwe_back_inv_addr_offset + `EPN_WIDTH - 1]), + .din(tlbwe_back_inv_addr_d[0:`EPN_WIDTH - 1]), + .dout(tlbwe_back_inv_addr_q[0:`EPN_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(35), .INIT(0), .NEEDS_SRESET(1)) tlbwe_back_inv_attr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[tlbwe_back_inv_attr_offset:tlbwe_back_inv_attr_offset + 35 - 1]), + .scout(sov[tlbwe_back_inv_attr_offset:tlbwe_back_inv_attr_offset + 35 - 1]), + .din(tlbwe_back_inv_attr_d), + .dout(tlbwe_back_inv_attr_q) + ); + + tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) inv_seq_inprogress_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[inv_seq_inprogress_offset:inv_seq_inprogress_offset + 6 - 1]), + .scout(sov[inv_seq_inprogress_offset:inv_seq_inprogress_offset + 6 - 1]), + .din(inv_seq_inprogress_d), + .dout(inv_seq_inprogress_q) + ); + + tri_rlmreg_p #(.WIDTH(13), .INIT(0), .NEEDS_SRESET(1)) xu_mm_ccr2_notlb_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[xu_mm_ccr2_notlb_offset:xu_mm_ccr2_notlb_offset + 13 - 1]), + .scout(sov[xu_mm_ccr2_notlb_offset:xu_mm_ccr2_notlb_offset + 13 - 1]), + .din(xu_mm_ccr2_notlb_d), + .dout(xu_mm_ccr2_notlb_q) + ); + + tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) spare_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[spare_offset:spare_offset + 16 - 1]), + .scout(sov[spare_offset:spare_offset + 16 - 1]), + .din(spare_q), + .dout(spare_q) + ); + // non-scannable config latches, includes bogus sg, scin, scout ports + + tri_regk #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(0)) epcr_dgtmi_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .sg(pc_sg_0), + .force_t(pc_func_slp_nsl_force), + .d_mode(lcb_d_mode_dc), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .thold_b(pc_func_slp_nsl_thold_0_b), + .scin({`MM_THREADS{tidn}}), + //.scout(unused_dc[13]), + .din(xu_mm_spr_epcr_dgtmi), + .dout(xu_mm_epcr_dgtmi_q) + ); + + tri_regk #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(0)) lpidr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .sg(pc_sg_0), + .force_t(pc_func_slp_nsl_force), + .d_mode(lcb_d_mode_dc), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .thold_b(pc_func_slp_nsl_thold_0_b), + .scin({`LPID_WIDTH{tidn}}), + //.scout(unused_dc[14]), + .din(lpidr), + .dout(lpidr_q) + ); + + tri_regk #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(0)) mmucr1_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .sg(pc_sg_0), + .force_t(pc_func_slp_nsl_force), + .d_mode(lcb_d_mode_dc), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .thold_b(pc_func_slp_nsl_thold_0_b), + .scin({8{tidn}}), + //.scout(unused_dc[15]), + .din(mmucr1), + .dout(mmucr1_q) + ); + + tri_regk #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(0)) mmucr1_csinv_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(pc_func_slp_nsl_force), + .sg(pc_sg_0), + .d_mode(lcb_d_mode_dc), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .thold_b(pc_func_slp_nsl_thold_0_b), + .scin({2{tidn}}), + //.scout(unused_dc[16]), + .din(mmucr1_csinv), + .dout(mmucr1_csinv_q) + ); + + //------------------------------------------------ + // thold/sg latches + //------------------------------------------------ + + tri_plat #(.WIDTH(5)) perv_2to1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ccflush_dc), + .din( {pc_func_sl_thold_2, pc_func_slp_sl_thold_2, pc_func_slp_nsl_thold_2, pc_sg_2, pc_fce_2} ), + .q( {pc_func_sl_thold_1, pc_func_slp_sl_thold_1, pc_func_slp_nsl_thold_1, pc_sg_1, pc_fce_1} ) + ); + + tri_plat #(.WIDTH(5)) perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ccflush_dc), + .din( {pc_func_sl_thold_1, pc_func_slp_sl_thold_1, pc_func_slp_nsl_thold_1, pc_sg_1, pc_fce_1} ), + .q( {pc_func_sl_thold_0, pc_func_slp_sl_thold_0, pc_func_slp_nsl_thold_0, pc_sg_0, pc_fce_0} ) + ); + + tri_lcbor perv_lcbor_func_sl( + .clkoff_b(lcb_clkoff_dc_b), + .thold(pc_func_sl_thold_0), + .sg(pc_sg_0), + .act_dis(lcb_act_dis_dc), + .force_t(pc_func_sl_force), + .thold_b(pc_func_sl_thold_0_b) + ); + + tri_lcbor perv_lcbor_func_slp_sl( + .clkoff_b(lcb_clkoff_dc_b), + .thold(pc_func_slp_sl_thold_0), + .sg(pc_sg_0), + .act_dis(lcb_act_dis_dc), + .force_t(pc_func_slp_sl_force), + .thold_b(pc_func_slp_sl_thold_0_b) + ); + + tri_lcbor perv_nsl_lcbor( + .clkoff_b(lcb_clkoff_dc_b), + .thold(pc_func_slp_nsl_thold_0), + .sg(pc_fce_0), + .act_dis(tidn), + .force_t(pc_func_slp_nsl_force), + .thold_b(pc_func_slp_nsl_thold_0_b) + ); + + //--------------------------------------------------------------------- + // Scan + //--------------------------------------------------------------------- + assign siv[0:scan_right] = {sov[1:scan_right], ac_func_scan_in}; + assign ac_func_scan_out = sov[0]; + +endmodule diff --git a/dev/verilog/work/mmq_perf.v b/dev/verilog/work/mmq_perf.v new file mode 100755 index 0000000..1978e24 --- /dev/null +++ b/dev/verilog/work/mmq_perf.v @@ -0,0 +1,990 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +//******************************************************************** +//* +//* TITLE: Performance event mux +//* +//* NAME: mmq_perf.v +//* +//********************************************************************* + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" +`include "mmu_a2o.vh" + + +module mmq_perf( + + inout vdd, + inout gnd, + (* pin_data ="PIN_FUNCTION=/G_CLK/" *) + input [0:`NCLK_WIDTH-1] nclk, + + + input pc_func_sl_thold_2, + input pc_func_slp_nsl_thold_2, + input pc_sg_2, + input pc_fce_2, + input tc_ac_ccflush_dc, + + input lcb_clkoff_dc_b, + input lcb_act_dis_dc, + input lcb_d_mode_dc, + input lcb_delay_lclkr_dc, + input lcb_mpw1_dc_b, + input lcb_mpw2_dc_b, + +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + input scan_in, +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + output scan_out, + + input [0:`MM_THREADS-1] cp_flush_p1, + + input [0:`THDID_WIDTH-1] xu_mm_msr_gs, + input [0:`THDID_WIDTH-1] xu_mm_msr_pr, + input xu_mm_ccr2_notlb_b, + + // count event inputs + input [0:`THDID_WIDTH-1] lq_mm_perf_dtlb, + input [0:`THDID_WIDTH-1] iu_mm_perf_itlb, + input lq_mm_derat_req_nonspec, + input iu_mm_ierat_req_nonspec, + + input [0:9] tlb_cmp_perf_event_t0, + input [0:9] tlb_cmp_perf_event_t1, + input [0:1] tlb_cmp_perf_state, // gs & pr + + input tlb_cmp_perf_miss_direct, + input tlb_cmp_perf_hit_direct, + input tlb_cmp_perf_hit_indirect, + input tlb_cmp_perf_hit_first_page, + input tlb_cmp_perf_ptereload, + input tlb_cmp_perf_ptereload_noexcep, + input tlb_cmp_perf_lrat_request, + input tlb_cmp_perf_lrat_miss, + input tlb_cmp_perf_pt_fault, + input tlb_cmp_perf_pt_inelig, + input tlb_ctl_perf_tlbwec_resv, + input tlb_ctl_perf_tlbwec_noresv, + + input [0:`THDID_WIDTH-1] derat_req0_thdid, + input derat_req0_valid, + input derat_req0_nonspec, + input [0:`THDID_WIDTH-1] derat_req1_thdid, + input derat_req1_valid, + input derat_req1_nonspec, + input [0:`THDID_WIDTH-1] derat_req2_thdid, + input derat_req2_valid, + input derat_req2_nonspec, + input [0:`THDID_WIDTH-1] derat_req3_thdid, + input derat_req3_valid, + input derat_req3_nonspec, + + input [0:`THDID_WIDTH-1] ierat_req0_thdid, + input ierat_req0_valid, + input ierat_req0_nonspec, + input [0:`THDID_WIDTH-1] ierat_req1_thdid, + input ierat_req1_valid, + input ierat_req1_nonspec, + input [0:`THDID_WIDTH-1] ierat_req2_thdid, + input ierat_req2_valid, + input ierat_req2_nonspec, + input [0:`THDID_WIDTH-1] ierat_req3_thdid, + input ierat_req3_valid, + input ierat_req3_nonspec, + + input ierat_req_taken, + input derat_req_taken, + + input [0:`THDID_WIDTH-1] tlb_tag0_thdid, + input [0:1] tlb_tag0_type, // derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload + input tlb_tag0_nonspec, + input tlb_tag4_nonspec, + input tlb_seq_idle, + + input inval_perf_tlbilx, + input inval_perf_tlbivax, + input inval_perf_tlbivax_snoop, + input inval_perf_tlb_flush, + + input htw_req0_valid, + input [0:`THDID_WIDTH-1] htw_req0_thdid, + input [0:1] htw_req0_type, + input htw_req1_valid, + input [0:`THDID_WIDTH-1] htw_req1_thdid, + input [0:1] htw_req1_type, + input htw_req2_valid, + input [0:`THDID_WIDTH-1] htw_req2_thdid, + input [0:1] htw_req2_type, + input htw_req3_valid, + input [0:`THDID_WIDTH-1] htw_req3_thdid, + input [0:1] htw_req3_type, + +`ifdef WAIT_UPDATES + input [0:`MM_THREADS+5-1] cp_mm_perf_except_taken_q, + // 0:1 - thdid/val + // 2 - I=0/D=1 + // 3 - TLB miss + // 4 - Storage int (TLBI/PTfault) + // 5 - LRAT miss + // 6 - Mcheck +`endif + + // control inputs + input [0:`MESR1_WIDTH*`THREADS-1] mmq_spr_event_mux_ctrls, + input [0:2] pc_mm_event_count_mode, // 0=count events in problem state,1=sup,2=hypv + input rp_mm_event_bus_enable_q, // act for perf related latches from repower + + input [0:`PERF_EVENT_WIDTH*`THREADS-1] mm_event_bus_in, + output [0:`PERF_EVENT_WIDTH*`THREADS-1] mm_event_bus_out + +); + + + parameter rp_mm_event_bus_enable_offset = 0; + parameter mmq_spr_event_mux_ctrls_offset = rp_mm_event_bus_enable_offset + 1; + parameter pc_mm_event_count_mode_offset = mmq_spr_event_mux_ctrls_offset + `MESR1_WIDTH*`THREADS; + parameter xu_mm_msr_gs_offset = pc_mm_event_count_mode_offset + 3; + parameter xu_mm_msr_pr_offset = xu_mm_msr_gs_offset + `THDID_WIDTH; + parameter event_bus_out_offset = xu_mm_msr_pr_offset + `THDID_WIDTH; + parameter scan_right = event_bus_out_offset + `PERF_EVENT_WIDTH*`THREADS - 1; + + wire [0:`PERF_EVENT_WIDTH*`THREADS-1] event_bus_out_d, event_bus_out_q; + + wire rp_mm_event_bus_enable_int_q; + wire [0:`MESR1_WIDTH*`THREADS-1] mmq_spr_event_mux_ctrls_q; + wire [0:2] pc_mm_event_count_mode_q; // 0=count events in problem state,1=sup,2=hypv + + wire [0:23] mm_perf_event_t0_d, mm_perf_event_t0_q; // t0 threadwise events + wire [0:23] mm_perf_event_t1_d, mm_perf_event_t1_q; // t1 threadwise events + wire [0:31] mm_perf_event_core_level_d, mm_perf_event_core_level_q; // thread independent events + + wire [0:`THDID_WIDTH-1] xu_mm_msr_gs_q; + wire [0:`THDID_WIDTH-1] xu_mm_msr_pr_q; + wire [0:`THDID_WIDTH] event_en; + + wire [0:`PERF_MUX_WIDTH-1] unit_t0_events_in; +`ifndef THREADS1 + wire [0:`PERF_MUX_WIDTH-1] unit_t1_events_in; +`endif + + wire [0:scan_right] siv; + wire [0:scan_right] sov; + + wire tidn; + wire tiup; + + wire pc_func_sl_thold_1; + wire pc_func_sl_thold_0; + wire pc_func_sl_thold_0_b; + wire pc_func_slp_nsl_thold_1; + wire pc_func_slp_nsl_thold_0; + wire pc_func_slp_nsl_thold_0_b; + wire pc_func_slp_nsl_force; + wire pc_sg_1; + wire pc_sg_0; + wire pc_fce_1; + wire pc_fce_0; + wire force_t; + + wire [0:79] tri_regk_unused_scan; + + //--------------------------------------------------------------------- + // Logic + //--------------------------------------------------------------------- + + assign tidn = 1'b0; + assign tiup = 1'b1; + + assign event_en[0:3] = (xu_mm_msr_pr_q[0:3] & {4{pc_mm_event_count_mode_q[0]}}) | + // User problem state + ((~xu_mm_msr_pr_q[0:3]) & xu_mm_msr_gs_q[0:3] & {4{pc_mm_event_count_mode_q[1]}}) | + // Guest Supervisor + ((~xu_mm_msr_pr_q[0:3]) & (~xu_mm_msr_gs_q[0:3]) & {4{pc_mm_event_count_mode_q[2]}}); + // Hypervisor + + //tlb_cmp_perf_state: 0 =gs, 1=pr + assign event_en[4] = (tlb_cmp_perf_state[1] & pc_mm_event_count_mode_q[0]) | + // User problem state + (tlb_cmp_perf_state[0] & (~tlb_cmp_perf_state[1]) & pc_mm_event_count_mode_q[1]) | + // Guest Supervisor + ((~tlb_cmp_perf_state[0]) & (~tlb_cmp_perf_state[1]) & pc_mm_event_count_mode_q[2]); + // Hypervisor + + //-------------------------------------------------- + // t* threadwise event list + //-------------------------------------------------- + // 0 TLB hit direct entry (instr.) (ind=0 entry hit for fetch) + // 1 TLB miss direct entry (instr.) (ind=0 entry missed for fetch) + // 2 TLB miss indirect entry (instr.) (ind=1 entry missed for fetch, results in i-tlb exception) + // 3 H/W tablewalk hit (instr.) (ptereload with PTE.V=1 for fetch) + // 4 H/W tablewalk miss (instr.) (ptereload with PTE.V=0 for fetch, results in PT fault exception -> isi) + // 5 TLB hit direct entry (data) (ind=0 entry hit for load/store/cache op) + // 6 TLB miss direct entry (data) (ind=0 entry miss for load/store/cache op) + // 7 TLB miss indirect entry (data) (ind=1 entry missed for load/store/cache op, results in d-tlb exception) + // 8 H/W tablewalk hit (data) (ptereload with PTE.V=1 for load/store/cache op) + // 9 H/W tablewalk miss (data) (ptereload with PTE.V=0 for load/store/cache op, results in PT fault exception -> dsi) + // 10 IERAT miss (or latency), edge (or level) (total ierat misses or latency) + // 11 DERAT miss (or latency), edge (or level) (total derat misses or latency) + + // 12 TLB hit direct entry (instr.) (ind=0 entry hit for NONSPECULATIVE fetch) + // 13 TLB miss direct entry (instr.) (ind=0 entry missed for NONSPECULATIVE fetch) + // 14 TLB hit direct entry (data) (ind=0 entry hit for NONSPECULATIVE load/store/cache op) + // 15 TLB miss direct entry (data) (ind=0 entry miss for NONSPECULATIVE load/store/cache op) + // 16 IERAT miss (or latency), edge (or level) (total NONSPECULATIVE ierat misses or latency) + // 17 DERAT miss (or latency), edge (or level) (total NONSPECULATIVE derat misses or latency) + + // 18 TLB hit direct entry (instr.) (ind=0 entry hit for SPECULATIVE fetch) + // 19 TLB miss direct entry (instr.) (ind=0 entry missed for SPECULATIVE fetch) + // 20 TLB hit direct entry (data) (ind=0 entry hit for SPECULATIVE load/store/cache op) + // 21 TLB miss direct entry (data) (ind=0 entry miss for SPECULATIVE load/store/cache op) + // 22 IERAT miss (or latency), edge (or level) (total SPECULATIVE ierat misses or latency) + // 23 DERAT miss (or latency), edge (or level) (total SPECULATIVE derat misses or latency) + + //-------------------------------------------------- + // core single event list + //-------------------------------------------------- + // 0 IERAT miss total (part of direct entry search total) + // 1 DERAT miss total (part of direct entry search total) + // 2 TLB miss direct entry total (total TLB ind=0 misses) + // 3 TLB hit direct entry first page size + //-------------------------------------------------- + // 4 TLB indirect entry hits total (=page table searches) + // 5 H/W tablewalk successful installs total (with no PTfault, TLB ineligible, or LRAT miss) + // 6 LRAT translation request total (for GS=1 tlbwe and ptereload) + // 7 LRAT misses total (for GS=1 tlbwe and ptereload) + //-------------------------------------------------- + // 8 Page table faults total (PTE.V=0 for ptereload, resulting in isi/dsi) + // 9 TLB ineligible total (all TLB ways are iprot=1 for ptereloads, resulting in isi/dsi) + // 10 tlbwe conditional failed total (total tlbwe WQ=01 with no reservation match) + // 11 tlbwe conditional success total (total tlbwe WQ=01 with reservation match) + //-------------------------------------------------- + // 12 tlbilx local invalidations sourced total (sourced tlbilx on this core total) + // 13 tlbivax invalidations sourced total (sourced tlbivax on this core total) + // 14 tlbivax snoops total (total tlbivax snoops received from bus, local bit = don't care) + // 15 TLB flush requests total (TLB requested flushes due to TLB busy or instruction hazards) + //-------------------------------------------------- + // 16 IERAT NONSPECULATIVE miss total (part of direct entry search total) + // 17 DERAT NONSPECULATIVE miss total (part of direct entry search total) + // 18 TLB NONSPECULATIVE miss direct entry total (total TLB ind=0 misses) + // 19 TLB NONSPECULATIVE hit direct entry first page size + //-------------------------------------------------- + // 20 IERAT SPECULATIVE miss total (part of direct entry search total) + // 21 DERAT SPECULATIVE miss total (part of direct entry search total) + // 22 TLB SPECULATIVE miss direct entry total (total TLB ind=0 misses) + // 23 TLB SPECULATIVE hit direct entry first page size + //-------------------------------------------------- + // 24 ERAT miss total (TLB direct entry search total for both I and D sides) + // 25 ERAT NONSPECULATIVE miss total (TLB direct entry nonspeculative search total for both I and D sides) + // 26 ERAT SPECULATIVE miss total (TLB direct entry speculative search total for both I and D sides) + // 27 TLB hit direct entry total (total TLB ind=0 hits for both I and D sides) + // 28 TLB NONSPECULATIVE hit direct entry total (total TLB ind=0 nonspeculative hits for both I and D sides) + // 29 TLB SPECULATIVE hit direct entry total (total TLB ind=0 speculative hits for both I and D sides) + // 30 PTE reload attempts total (with valid htw-reservation, no duplicate set, and pt=1) + // 31 Raw Total ERAT misses, either mode + + + //-------------------------------------------------- + // t* threadwise event list + //-------------------------------------------------- + // 0 TLB hit direct entry (instr.) (ind=0 entry hit for fetch) + // 1 TLB miss direct entry (instr.) (ind=0 entry missed for fetch) + // 2 TLB miss indirect entry (instr.) (ind=1 entry missed for fetch, results in i-tlb exception) + // 3 H/W tablewalk hit (instr.) (ptereload with PTE.V=1 for fetch) + // 4 H/W tablewalk miss (instr.) (ptereload with PTE.V=0 for fetch, results in PT fault exception -> isi) + // 5 TLB hit direct entry (data) (ind=0 entry hit for load/store/cache op) + // 6 TLB miss direct entry (data) (ind=0 entry miss for load/store/cache op) + // 7 TLB miss indirect entry (data) (ind=1 entry missed for load/store/cache op, results in d-tlb exception) + // 8 H/W tablewalk hit (data) (ptereload with PTE.V=1 for load/store/cache op) + // 9 H/W tablewalk miss (data) (ptereload with PTE.V=0 for load/store/cache op, results in PT fault exception -> dsi) + assign mm_perf_event_t0_d[0:9] = tlb_cmp_perf_event_t0[0:9] & {10{event_en[0]}}; + + // 10 IERAT miss (or latency), edge (or level) (total ierat misses or latency) + // type: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload + assign mm_perf_event_t0_d[10] = (((ierat_req0_valid & ierat_req0_thdid[0]) | + (ierat_req1_valid & ierat_req1_thdid[0]) | + (ierat_req2_valid & ierat_req2_thdid[0]) | + (ierat_req3_valid & ierat_req3_thdid[0]) | + // ierat nonspec miss request + ((~tlb_seq_idle) & tlb_tag0_type[1] & tlb_tag0_thdid[0]) | + // searching tlb for direct entry, or ptereload of instr + (htw_req0_valid & htw_req0_type[1] & htw_req0_thdid[0]) | + (htw_req1_valid & htw_req1_type[1] & htw_req1_thdid[0]) | + (htw_req2_valid & htw_req2_type[1] & htw_req2_thdid[0]) | + (htw_req3_valid & htw_req3_type[1] & htw_req3_thdid[0])) & xu_mm_ccr2_notlb_b) | + // htw servicing miss of instr + (iu_mm_perf_itlb[0] & (~xu_mm_ccr2_notlb_b)); + + // 11 DERAT miss (or latency), edge (or level) (total derat misses or latency) + // type: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload + assign mm_perf_event_t0_d[11] = (((derat_req0_valid & derat_req0_thdid[0]) | + (derat_req1_valid & derat_req1_thdid[0]) | + (derat_req2_valid & derat_req2_thdid[0]) | + (derat_req3_valid & derat_req3_thdid[0]) | + // derat nonspec miss request + ((~tlb_seq_idle) & tlb_tag0_type[0] & tlb_tag0_thdid[0]) | + // searching tlb for direct entry, or ptereload of data + (htw_req0_valid & htw_req0_type[0] & htw_req0_thdid[0]) | + (htw_req1_valid & htw_req1_type[0] & htw_req1_thdid[0]) | + (htw_req2_valid & htw_req2_type[0] & htw_req2_thdid[0]) | + (htw_req3_valid & htw_req3_type[0] & htw_req3_thdid[0])) & xu_mm_ccr2_notlb_b) | + // htw servicing miss of data + (lq_mm_perf_dtlb[0] & (~xu_mm_ccr2_notlb_b)); + + // 12 TLB hit direct entry (instr.) (ind=0 entry hit for NONSPECULATIVE fetch) + assign mm_perf_event_t0_d[12] = tlb_cmp_perf_event_t0[0] & event_en[0] & tlb_tag4_nonspec; + + // 13 TLB miss direct entry (instr.) (ind=0 entry missed for NONSPECULATIVE fetch) + assign mm_perf_event_t0_d[13] = tlb_cmp_perf_event_t0[1] & event_en[0] & tlb_tag4_nonspec; + + // 14 TLB hit direct entry (data) (ind=0 entry hit for NONSPECULATIVE load/store/cache op) + assign mm_perf_event_t0_d[14] = tlb_cmp_perf_event_t0[5] & event_en[0] & tlb_tag4_nonspec; + + // 15 TLB miss direct entry (data) (ind=0 entry miss for NONSPECULATIVE load/store/cache op) + assign mm_perf_event_t0_d[15] = tlb_cmp_perf_event_t0[6] & event_en[0] & tlb_tag4_nonspec; + + // 16 IERAT miss (or latency), edge (or level) (total NONSPECULATIVE ierat misses or latency) + // type: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload + assign mm_perf_event_t0_d[16] = (((ierat_req0_valid & ierat_req0_nonspec & ierat_req0_thdid[0]) | + (ierat_req1_valid & ierat_req1_nonspec & ierat_req1_thdid[0]) | + (ierat_req2_valid & ierat_req2_nonspec & ierat_req2_thdid[0]) | + (ierat_req3_valid & ierat_req3_nonspec & ierat_req3_thdid[0]) | + // ierat nonspec miss request + ((~tlb_seq_idle) & tlb_tag0_type[1] & tlb_tag0_thdid[0] & tlb_tag0_nonspec) | + // searching tlb for direct entry, or ptereload of instr + (htw_req0_valid & htw_req0_type[1] & htw_req0_thdid[0]) | + (htw_req1_valid & htw_req1_type[1] & htw_req1_thdid[0]) | + (htw_req2_valid & htw_req2_type[1] & htw_req2_thdid[0]) | + (htw_req3_valid & htw_req3_type[1] & htw_req3_thdid[0])) & xu_mm_ccr2_notlb_b) | + // htw servicing miss of instr + (iu_mm_perf_itlb[0] & iu_mm_ierat_req_nonspec & (~xu_mm_ccr2_notlb_b)); + + // 17 DERAT miss (or latency), edge (or level) (total NONSPECULATIVE derat misses or latency) + // type: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload + assign mm_perf_event_t0_d[17] = (((derat_req0_valid & derat_req0_nonspec & derat_req0_thdid[0]) | + (derat_req1_valid & derat_req1_nonspec & derat_req1_thdid[0]) | + (derat_req2_valid & derat_req2_nonspec & derat_req2_thdid[0]) | + (derat_req3_valid & derat_req3_nonspec & derat_req3_thdid[0]) | + // derat nonspec miss request + ((~tlb_seq_idle) & tlb_tag0_type[0] & tlb_tag0_thdid[0] & tlb_tag0_nonspec) | + // searching tlb for direct entry, or ptereload of data + (htw_req0_valid & htw_req0_type[0] & htw_req0_thdid[0]) | + (htw_req1_valid & htw_req1_type[0] & htw_req1_thdid[0]) | + (htw_req2_valid & htw_req2_type[0] & htw_req2_thdid[0]) | + (htw_req3_valid & htw_req3_type[0] & htw_req3_thdid[0])) & xu_mm_ccr2_notlb_b) | + // htw servicing miss of data + (lq_mm_perf_dtlb[0] & lq_mm_derat_req_nonspec & (~xu_mm_ccr2_notlb_b)); + + + // 18 TLB hit direct entry (instr.) (ind=0 entry hit for SPECULATIVE fetch) + assign mm_perf_event_t0_d[18] = tlb_cmp_perf_event_t0[0] & event_en[0] & ~tlb_tag4_nonspec; + + // 19 TLB miss direct entry (instr.) (ind=0 entry missed for SPECULATIVE fetch) + assign mm_perf_event_t0_d[19] = tlb_cmp_perf_event_t0[1] & event_en[0] & ~tlb_tag4_nonspec; + + // 20 TLB hit direct entry (data) (ind=0 entry hit for SPECULATIVE load/store/cache op) + assign mm_perf_event_t0_d[20] = tlb_cmp_perf_event_t0[5] & event_en[0] & ~tlb_tag4_nonspec; + + // 21 TLB miss direct entry (data) (ind=0 entry miss for SPECULATIVE load/store/cache op) + assign mm_perf_event_t0_d[21] = tlb_cmp_perf_event_t0[6] & event_en[0] & ~tlb_tag4_nonspec; + + // 22 IERAT miss (or latency), edge (or level) (total SPECULATIVE ierat misses or latency) + // type: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload + // NOTE - speculative requests do not envoke h/w tablewalker actions.. + // ..tablewalker handles only non-speculative requests + assign mm_perf_event_t0_d[22] = (((ierat_req0_valid & ~ierat_req0_nonspec & ierat_req0_thdid[0]) | + (ierat_req1_valid & ~ierat_req1_nonspec & ierat_req1_thdid[0]) | + (ierat_req2_valid & ~ierat_req2_nonspec & ierat_req2_thdid[0]) | + (ierat_req3_valid & ~ierat_req3_nonspec & ierat_req3_thdid[0]) | + // ierat nonspec miss request + ((~tlb_seq_idle) & tlb_tag0_type[1] & tlb_tag0_thdid[0] & ~tlb_tag0_nonspec)) & xu_mm_ccr2_notlb_b) | + // searching tlb for direct entry, or ptereload of instr + (iu_mm_perf_itlb[0] & (~iu_mm_ierat_req_nonspec) & (~xu_mm_ccr2_notlb_b)); + + // 23 DERAT miss (or latency), edge (or level) (total SPECULATIVE derat misses or latency) + // type: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload + // NOTE - speculative requests do not envoke h/w tablewalker actions.. + // ..tablewalker handles only non-speculative requests + assign mm_perf_event_t0_d[23] = (((derat_req0_valid & ~derat_req0_nonspec & derat_req0_thdid[0]) | + (derat_req1_valid & ~derat_req1_nonspec & derat_req1_thdid[0]) | + (derat_req2_valid & ~derat_req2_nonspec & derat_req2_thdid[0]) | + (derat_req3_valid & ~derat_req3_nonspec & derat_req3_thdid[0]) | + // derat nonspec miss request + ((~tlb_seq_idle) & tlb_tag0_type[0] & tlb_tag0_thdid[0] & ~tlb_tag0_nonspec)) & xu_mm_ccr2_notlb_b) | + // searching tlb for direct entry, or ptereload of data + (lq_mm_perf_dtlb[0] & (~lq_mm_derat_req_nonspec) & (~xu_mm_ccr2_notlb_b)); + + + //-------------------------------------------------- + // t* threadwise event list + //-------------------------------------------------- + // 0 TLB hit direct entry (instr.) (ind=0 entry hit for fetch) + // 1 TLB miss direct entry (instr.) (ind=0 entry missed for fetch) + // 2 TLB miss indirect entry (instr.) (ind=1 entry missed for fetch, results in i-tlb exception) + // 3 H/W tablewalk hit (instr.) (ptereload with PTE.V=1 for fetch) + // 4 H/W tablewalk miss (instr.) (ptereload with PTE.V=0 for fetch, results in PT fault exception -> isi) + // 5 TLB hit direct entry (data) (ind=0 entry hit for load/store/cache op) + // 6 TLB miss direct entry (data) (ind=0 entry miss for load/store/cache op) + // 7 TLB miss indirect entry (data) (ind=1 entry missed for load/store/cache op, results in d-tlb exception) + // 8 H/W tablewalk hit (data) (ptereload with PTE.V=1 for load/store/cache op) + // 9 H/W tablewalk miss (data) (ptereload with PTE.V=0 for load/store/cache op, results in PT fault exception -> dsi) + assign mm_perf_event_t1_d[0:9] = tlb_cmp_perf_event_t1[0:9] & {10{event_en[1]}}; + + // 10 IERAT miss (or latency), edge (or level) (total ierat misses or latency) + // type: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload + assign mm_perf_event_t1_d[10] = (((ierat_req0_valid & ierat_req0_thdid[1]) | + (ierat_req1_valid & ierat_req1_thdid[1]) | + (ierat_req2_valid & ierat_req2_thdid[1]) | + (ierat_req3_valid & ierat_req3_thdid[1]) | + // ierat nonspec miss request + ((~tlb_seq_idle) & tlb_tag0_type[1] & tlb_tag0_thdid[1]) | + // searching tlb for direct entry, or ptereload of instr + (htw_req0_valid & htw_req0_type[1] & htw_req0_thdid[1]) | + (htw_req1_valid & htw_req1_type[1] & htw_req1_thdid[1]) | + (htw_req2_valid & htw_req2_type[1] & htw_req2_thdid[1]) | + (htw_req3_valid & htw_req3_type[1] & htw_req3_thdid[1])) & xu_mm_ccr2_notlb_b) | + // htw servicing miss of instr + (iu_mm_perf_itlb[1] & (~xu_mm_ccr2_notlb_b)); + + // 11 DERAT miss (or latency), edge (or level) (total derat misses or latency) + // type: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload + assign mm_perf_event_t1_d[11] = (((derat_req0_valid & derat_req0_thdid[1]) | + (derat_req1_valid & derat_req1_thdid[1]) | + (derat_req2_valid & derat_req2_thdid[1]) | + (derat_req3_valid & derat_req3_thdid[1]) | + // derat nonspec miss request + ((~tlb_seq_idle) & tlb_tag0_type[0] & tlb_tag0_thdid[1]) | + // searching tlb for direct entry, or ptereload of data + (htw_req0_valid & htw_req0_type[0] & htw_req0_thdid[1]) | + (htw_req1_valid & htw_req1_type[0] & htw_req1_thdid[1]) | + (htw_req2_valid & htw_req2_type[0] & htw_req2_thdid[1]) | + (htw_req3_valid & htw_req3_type[0] & htw_req3_thdid[1])) & xu_mm_ccr2_notlb_b) | + // htw servicing miss of data + (lq_mm_perf_dtlb[1] & (~xu_mm_ccr2_notlb_b)); + + + // 12 TLB hit direct entry (instr.) (ind=0 entry hit for NONSPECULATIVE fetch) + assign mm_perf_event_t1_d[12] = tlb_cmp_perf_event_t1[0] & event_en[1] & tlb_tag4_nonspec; + + // 13 TLB miss direct entry (instr.) (ind=0 entry missed for NONSPECULATIVE fetch) + assign mm_perf_event_t1_d[13] = tlb_cmp_perf_event_t1[1] & event_en[1] & tlb_tag4_nonspec; + + // 14 TLB hit direct entry (data) (ind=0 entry hit for NONSPECULATIVE load/store/cache op) + assign mm_perf_event_t1_d[14] = tlb_cmp_perf_event_t1[5] & event_en[1] & tlb_tag4_nonspec; + + // 15 TLB miss direct entry (data) (ind=0 entry miss for NONSPECULATIVE load/store/cache op) + assign mm_perf_event_t1_d[15] = tlb_cmp_perf_event_t1[6] & event_en[1] & tlb_tag4_nonspec; + + // 16 IERAT miss (or latency), edge (or level) (total NONSPECULATIVE ierat misses or latency) + assign mm_perf_event_t1_d[16] = (((ierat_req0_valid & ierat_req0_nonspec & ierat_req0_thdid[1]) | + (ierat_req1_valid & ierat_req1_nonspec & ierat_req1_thdid[1]) | + (ierat_req2_valid & ierat_req2_nonspec & ierat_req2_thdid[1]) | + (ierat_req3_valid & ierat_req3_nonspec & ierat_req3_thdid[1]) | + // ierat nonspec miss request + ((~tlb_seq_idle) & tlb_tag0_type[1] & tlb_tag0_thdid[1] & tlb_tag0_nonspec) | + // searching tlb for direct entry, or ptereload of instr + (htw_req0_valid & htw_req0_type[1] & htw_req0_thdid[1]) | + (htw_req1_valid & htw_req1_type[1] & htw_req1_thdid[1]) | + (htw_req2_valid & htw_req2_type[1] & htw_req2_thdid[1]) | + (htw_req3_valid & htw_req3_type[1] & htw_req3_thdid[1])) & xu_mm_ccr2_notlb_b) | + // htw servicing miss of instr + (iu_mm_perf_itlb[1] & iu_mm_ierat_req_nonspec & (~xu_mm_ccr2_notlb_b)); + + // 17 DERAT miss (or latency), edge (or level) (total NONSPECULATIVE derat misses or latency) + assign mm_perf_event_t1_d[17] = (((derat_req0_valid & derat_req0_nonspec & derat_req0_thdid[1]) | + (derat_req1_valid & derat_req1_nonspec & derat_req1_thdid[1]) | + (derat_req2_valid & derat_req2_nonspec & derat_req2_thdid[1]) | + (derat_req3_valid & derat_req3_nonspec & derat_req3_thdid[1]) | + // derat nonspec miss request + ((~tlb_seq_idle) & tlb_tag0_type[0] & tlb_tag0_thdid[1] & tlb_tag0_nonspec) | + // searching tlb for direct entry, or ptereload of data + (htw_req0_valid & htw_req0_type[0] & htw_req0_thdid[1]) | + (htw_req1_valid & htw_req1_type[0] & htw_req1_thdid[1]) | + (htw_req2_valid & htw_req2_type[0] & htw_req2_thdid[1]) | + (htw_req3_valid & htw_req3_type[0] & htw_req3_thdid[1])) & xu_mm_ccr2_notlb_b) | + // htw servicing miss of data + (lq_mm_perf_dtlb[1] & lq_mm_derat_req_nonspec & (~xu_mm_ccr2_notlb_b)); + + + // 18 TLB hit direct entry (instr.) (ind=0 entry hit for SPECULATIVE fetch) + assign mm_perf_event_t1_d[18] = tlb_cmp_perf_event_t1[0] & event_en[1] & ~tlb_tag4_nonspec; + + // 19 TLB miss direct entry (instr.) (ind=0 entry missed for SPECULATIVE fetch) + assign mm_perf_event_t1_d[19] = tlb_cmp_perf_event_t1[1] & event_en[1] & ~tlb_tag4_nonspec; + + // 20 TLB hit direct entry (data) (ind=0 entry hit for SPECULATIVE load/store/cache op) + assign mm_perf_event_t1_d[20] = tlb_cmp_perf_event_t1[5] & event_en[1] & ~tlb_tag4_nonspec; + + // 21 TLB miss direct entry (data) (ind=0 entry miss for SPECULATIVE load/store/cache op) + assign mm_perf_event_t1_d[21] = tlb_cmp_perf_event_t1[6] & event_en[1] & ~tlb_tag4_nonspec; + + // 22 IERAT miss (or latency), edge (or level) (total SPECULATIVE ierat misses or latency) + // type: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload + // NOTE - speculative requests do not envoke h/w tablewalker actions.. + // ..tablewalker handles only non-speculative requests + assign mm_perf_event_t1_d[22] = (((ierat_req0_valid & ~ierat_req0_nonspec & ierat_req0_thdid[1]) | + (ierat_req1_valid & ~ierat_req1_nonspec & ierat_req1_thdid[1]) | + (ierat_req2_valid & ~ierat_req2_nonspec & ierat_req2_thdid[1]) | + (ierat_req3_valid & ~ierat_req3_nonspec & ierat_req3_thdid[1]) | + // ierat nonspec miss request + ((~tlb_seq_idle) & tlb_tag0_type[1] & tlb_tag0_thdid[1] & ~tlb_tag0_nonspec)) & xu_mm_ccr2_notlb_b) | + // searching tlb for direct entry, or ptereload of instr + (iu_mm_perf_itlb[1] & (~iu_mm_ierat_req_nonspec) & (~xu_mm_ccr2_notlb_b)); + + // 23 DERAT miss (or latency), edge (or level) (total SPECULATIVE derat misses or latency) + // type: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload + // NOTE - speculative requests do not envoke h/w tablewalker actions.. + // ..tablewalker handles only non-speculative requests + assign mm_perf_event_t1_d[23] = (((derat_req0_valid & ~derat_req0_nonspec & derat_req0_thdid[1]) | + (derat_req1_valid & ~derat_req1_nonspec & derat_req1_thdid[1]) | + (derat_req2_valid & ~derat_req2_nonspec & derat_req2_thdid[1]) | + (derat_req3_valid & ~derat_req3_nonspec & derat_req3_thdid[1]) | + // derat nonspec miss request + ((~tlb_seq_idle) & tlb_tag0_type[0] & tlb_tag0_thdid[1] & ~tlb_tag0_nonspec)) & xu_mm_ccr2_notlb_b) | + // searching tlb for direct entry, or ptereload of data + (lq_mm_perf_dtlb[1] & (~lq_mm_derat_req_nonspec) & (~xu_mm_ccr2_notlb_b)); + + + + //-------------------------------------------------- + // core single event list + //-------------------------------------------------- + // 0 IERAT miss total (part of direct entry search total) + // 1 DERAT miss total (part of direct entry search total) + // 2 TLB miss direct entry total (total TLB ind=0 misses) + // 3 TLB hit direct entry first page size + //-------------------------------------------------- + // 4 TLB indirect entry hits total (=page table searches) + // 5 H/W tablewalk successful installs total (with no PTfault, TLB ineligible, or LRAT miss) + // 6 LRAT translation request total (for GS=1 tlbwe and ptereload) + // 7 LRAT misses total (for GS=1 tlbwe and ptereload) + //-------------------------------------------------- + // 8 Page table faults total (PTE.V=0 for ptereload, resulting in isi/dsi) + // 9 TLB ineligible total (all TLB ways are iprot=1 for ptereloads, resulting in isi/dsi) + // 10 tlbwe conditional failed total (total tlbwe WQ=01 with no reservation match) + // 11 tlbwe conditional success total (total tlbwe WQ=01 with reservation match) + //-------------------------------------------------- + // 12 tlbilx local invalidations sourced total (sourced tlbilx on this core total) + // 13 tlbivax invalidations sourced total (sourced tlbivax on this core total) + // 14 tlbivax snoops total (total tlbivax snoops received from bus, local bit = don't care) + // 15 TLB flush requests total (TLB requested flushes due to TLB busy or instruction hazards) + //-------------------------------------------------- + // 16 IERAT NONSPECULATIVE miss total (part of direct entry search total) + // 17 DERAT NONSPECULATIVE miss total (part of direct entry search total) + // 18 TLB NONSPECULATIVE miss direct entry total (total TLB ind=0 misses) + // 19 TLB NONSPECULATIVE hit direct entry first page size + //-------------------------------------------------- + // 20 IERAT SPECULATIVE miss total (part of direct entry search total) + // 21 DERAT SPECULATIVE miss total (part of direct entry search total) + // 22 TLB SPECULATIVE miss direct entry total (total TLB ind=0 misses) + // 23 TLB SPECULATIVE hit direct entry first page size + //-------------------------------------------------- + // 24 ERAT miss total (TLB direct entry search total for both I and D sides) + // 25 ERAT NONSPECULATIVE miss total (TLB direct entry nonspeculative search total for both I and D sides) + // 26 ERAT SPECULATIVE miss total (TLB direct entry speculative search total for both I and D sides) + // 27 TLB hit direct entry total (total TLB ind=0 hits for both I and D sides) + // 28 TLB NONSPECULATIVE hit direct entry total (total TLB ind=0 nonspeculative hits for both I and D sides) + // 29 TLB SPECULATIVE hit direct entry total (total TLB ind=0 speculative hits for both I and D sides) + // 30 PTE reload attempts total (with valid htw-reservation, no duplicate set, and pt=1) + // 31 Raw Total ERAT misses, either mode + + // 0 IERAT miss total (part of direct entry search total) + assign mm_perf_event_core_level_d[0] = (ierat_req_taken & xu_mm_ccr2_notlb_b) | + ( |(iu_mm_perf_itlb) & (~xu_mm_ccr2_notlb_b) ); + + // 1 DERAT miss total (part of direct entry search total) + assign mm_perf_event_core_level_d[1] = (derat_req_taken & xu_mm_ccr2_notlb_b) | + ( |(lq_mm_perf_dtlb) & (~xu_mm_ccr2_notlb_b) ); + + // 2 TLB miss direct entry total (total TLB ind=0 misses) + assign mm_perf_event_core_level_d[2] = tlb_cmp_perf_miss_direct & event_en[4]; + + // 3 TLB hit direct entry first page size + assign mm_perf_event_core_level_d[3] = tlb_cmp_perf_hit_first_page & event_en[4]; + + // 4 TLB indirect entry hits total (=page table searches) + assign mm_perf_event_core_level_d[4] = tlb_cmp_perf_hit_indirect & event_en[4]; + + // 5 H/W tablewalk successful installs total (with no PTfault, TLB ineligible, or LRAT miss) + assign mm_perf_event_core_level_d[5] = tlb_cmp_perf_ptereload_noexcep & event_en[4]; + + // 6 LRAT translation request total (for GS=1 tlbwe and ptereload) + assign mm_perf_event_core_level_d[6] = tlb_cmp_perf_lrat_request & event_en[4]; + + // 7 LRAT misses total (for GS=1 tlbwe and ptereload) + assign mm_perf_event_core_level_d[7] = tlb_cmp_perf_lrat_miss & event_en[4]; + + // 8 Page table faults total (PTE.V=0 for ptereload, resulting in isi/dsi) + assign mm_perf_event_core_level_d[8] = tlb_cmp_perf_pt_fault & event_en[4]; + + // 9 TLB ineligible total (all TLB ways are iprot=1 for ptereloads, resulting in isi/dsi) + assign mm_perf_event_core_level_d[9] = tlb_cmp_perf_pt_inelig & event_en[4]; + + // 10 tlbwe conditional failed total (total tlbwe WQ=01 with no reservation match) + assign mm_perf_event_core_level_d[10] = tlb_ctl_perf_tlbwec_noresv & event_en[4]; + + // 11 tlbwe conditional success total (total tlbwe WQ=01 with reservation match) + assign mm_perf_event_core_level_d[11] = tlb_ctl_perf_tlbwec_resv & event_en[4]; + + // 12 tlbilx local invalidations sourced total (sourced tlbilx on this core total) + assign mm_perf_event_core_level_d[12] = inval_perf_tlbilx; + + // 13 tlbivax invalidations sourced total (sourced tlbivax on this core total) + assign mm_perf_event_core_level_d[13] = inval_perf_tlbivax; + + // 14 tlbivax snoops total (total tlbivax snoops received from bus, local bit = don't care) + assign mm_perf_event_core_level_d[14] = inval_perf_tlbivax_snoop; + + // 15 TLB flush requests total (TLB requested flushes due to TLB busy or instruction hazards) + assign mm_perf_event_core_level_d[15] = inval_perf_tlb_flush; + + //-------------------------------------------------- + // 16 IERAT NONSPECULATIVE miss total (part of direct entry search total) + assign mm_perf_event_core_level_d[16] = (mm_perf_event_core_level_q[0] & tlb_tag0_nonspec & xu_mm_ccr2_notlb_b) | // ierat_req_taken, nonspec + ( |(iu_mm_perf_itlb) & iu_mm_ierat_req_nonspec & (~xu_mm_ccr2_notlb_b) ); + + // 17 DERAT NONSPECULATIVE miss total (part of direct entry search total) + assign mm_perf_event_core_level_d[17] = (mm_perf_event_core_level_q[1] & tlb_tag0_nonspec & xu_mm_ccr2_notlb_b) | // derat_req_taken, nonspec + ( |(lq_mm_perf_dtlb) & lq_mm_derat_req_nonspec & (~xu_mm_ccr2_notlb_b) ); + + // 18 TLB NONSPECULATIVE miss direct entry total (total TLB ind=0 misses) + assign mm_perf_event_core_level_d[18] = tlb_cmp_perf_miss_direct & event_en[4] & tlb_tag4_nonspec; + + // 19 TLB NONSPECULATIVE hit direct entry first page size + assign mm_perf_event_core_level_d[19] = tlb_cmp_perf_hit_first_page & event_en[4] & tlb_tag4_nonspec; + + //-------------------------------------------------- + // 20 IERAT SPECULATIVE miss total (part of direct entry search total) + assign mm_perf_event_core_level_d[20] = (mm_perf_event_core_level_q[0] & ~tlb_tag0_nonspec & xu_mm_ccr2_notlb_b) | // ierat_req_taken, spec + ( |(iu_mm_perf_itlb) & (~iu_mm_ierat_req_nonspec) & (~xu_mm_ccr2_notlb_b) ); + + // 21 DERAT SPECULATIVE miss total (part of direct entry search total) + assign mm_perf_event_core_level_d[21] = (mm_perf_event_core_level_q[1] & ~tlb_tag0_nonspec & xu_mm_ccr2_notlb_b) | // derat_req_taken, spec + ( |(lq_mm_perf_dtlb) & (~lq_mm_derat_req_nonspec) & (~xu_mm_ccr2_notlb_b) ); + + // 22 TLB SPECULATIVE miss direct entry total (total TLB ind=0 misses) + assign mm_perf_event_core_level_d[22] = tlb_cmp_perf_miss_direct & event_en[4] & ~tlb_tag4_nonspec; + + // 23 TLB SPECULATIVE hit direct entry first page size + assign mm_perf_event_core_level_d[23] = tlb_cmp_perf_hit_first_page & event_en[4] & ~tlb_tag4_nonspec; + + //-------------------------------------------------- + // 24 ERAT miss total (TLB direct entry search total for both I and D sides) + assign mm_perf_event_core_level_d[24] = (mm_perf_event_core_level_q[0] | mm_perf_event_core_level_q[1]); // i/derat_req_taken (tlb mode), + // or raw i/derat misses (erat-only mode) + + // 25 ERAT NONSPECULATIVE miss total (TLB direct entry nonspeculative search total for both I and D sides) + assign mm_perf_event_core_level_d[25] = ( (mm_perf_event_core_level_q[0] | mm_perf_event_core_level_q[1]) & tlb_tag0_nonspec & xu_mm_ccr2_notlb_b ) | // nonspec i/derat_req_taken (tlb mode) + ( (mm_perf_event_core_level_q[16] | mm_perf_event_core_level_q[17]) & (~xu_mm_ccr2_notlb_b) ); // raw nonspec i/derat misses (erat-only mode) + + // 26 ERAT SPECULATIVE miss total (TLB direct entry speculative search total for both I and D sides) + assign mm_perf_event_core_level_d[26] = ( (mm_perf_event_core_level_q[0] | mm_perf_event_core_level_q[1]) & ~tlb_tag0_nonspec & xu_mm_ccr2_notlb_b ) | // spec i/derat_req_taken (tlb mode) + ( (mm_perf_event_core_level_q[20] | mm_perf_event_core_level_q[21]) & (~xu_mm_ccr2_notlb_b) ); // raw spec i/derat misses (erat-only mode) + + // 27 TLB hit direct entry total (total TLB ind=0 hits for both I and D sides) + assign mm_perf_event_core_level_d[27] = tlb_cmp_perf_hit_direct & event_en[4]; + + // 28 TLB NONSPECULATIVE hit direct entry total (total TLB ind=0 nonspeculative hits for both I and D sides) + assign mm_perf_event_core_level_d[28] = tlb_cmp_perf_hit_direct & event_en[4] & tlb_tag4_nonspec; + + // 29 TLB SPECULATIVE hit direct entry total (total TLB ind=0 speculative hits for both I and D sides) + assign mm_perf_event_core_level_d[29] = tlb_cmp_perf_hit_direct & event_en[4] & ~tlb_tag4_nonspec; + + // 30 PTE reload attempts total (with valid htw-reservation, no duplicate set, and pt=1) + assign mm_perf_event_core_level_d[30] = tlb_cmp_perf_ptereload & event_en[4]; + + // 31 Raw Total ERAT misses, either mode + assign mm_perf_event_core_level_d[31] = ( |(iu_mm_perf_itlb) | |(lq_mm_perf_dtlb) ); + + //-------------------------------------------------- + // end of core single event list + //-------------------------------------------------- + + assign unit_t0_events_in = {1'b0, mm_perf_event_t0_q[0:23], + 7'b0, + mm_perf_event_core_level_q[0:31]}; + + tri_event_mux1t #(.EVENTS_IN(`PERF_MUX_WIDTH), .EVENTS_OUT(4)) event_mux0( + .vd(vdd), + .gd(gnd), + .select_bits(mmq_spr_event_mux_ctrls_q[0:`MESR1_WIDTH - 1]), + .unit_events_in(unit_t0_events_in[1:63]), + .event_bus_in(mm_event_bus_in[0:3]), + .event_bus_out(event_bus_out_d[0:3]) + ); + +`ifndef THREADS1 + assign unit_t1_events_in = {1'b0, mm_perf_event_t1_q[0:23], + 7'b0, + mm_perf_event_core_level_q[0:31]}; + + + tri_event_mux1t #(.EVENTS_IN(`PERF_MUX_WIDTH), .EVENTS_OUT(4)) event_mux1( + .vd(vdd), + .gd(gnd), + .select_bits(mmq_spr_event_mux_ctrls_q[`MESR1_WIDTH:`MESR1_WIDTH+`MESR2_WIDTH - 1]), + .unit_events_in(unit_t1_events_in), + .event_bus_in(mm_event_bus_in[4:7]), + .event_bus_out(event_bus_out_d[4:7]) + ); +`endif + + assign mm_event_bus_out = event_bus_out_q; + + + //--------------------------------------------------------------------- + // Latches + //--------------------------------------------------------------------- + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rp_mm_event_bus_enable_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(force_t), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[rp_mm_event_bus_enable_offset]), + .scout(sov[rp_mm_event_bus_enable_offset]), + .din(rp_mm_event_bus_enable_q), // yes, this in the input name + .dout(rp_mm_event_bus_enable_int_q) // this is local internal version + ); + + + tri_rlmreg_p #(.WIDTH(`MESR1_WIDTH*`THREADS), .INIT(0)) mmq_spr_event_mux_ctrls_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(force_t), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[mmq_spr_event_mux_ctrls_offset:mmq_spr_event_mux_ctrls_offset + `MESR1_WIDTH*`THREADS - 1]), + .scout(sov[mmq_spr_event_mux_ctrls_offset:mmq_spr_event_mux_ctrls_offset + `MESR1_WIDTH*`THREADS - 1]), + .din(mmq_spr_event_mux_ctrls), + .dout(mmq_spr_event_mux_ctrls_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) pc_mm_event_count_mode_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(force_t), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[pc_mm_event_count_mode_offset:pc_mm_event_count_mode_offset + 3 - 1]), + .scout(sov[pc_mm_event_count_mode_offset:pc_mm_event_count_mode_offset + 3 - 1]), + .din(pc_mm_event_count_mode), + .dout(pc_mm_event_count_mode_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THDID_WIDTH), .INIT(0)) xu_mm_msr_gs_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rp_mm_event_bus_enable_int_q), + .thold_b(pc_func_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(force_t), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[xu_mm_msr_gs_offset:xu_mm_msr_gs_offset + `THDID_WIDTH - 1]), + .scout(sov[xu_mm_msr_gs_offset:xu_mm_msr_gs_offset + `THDID_WIDTH - 1]), + .din(xu_mm_msr_gs), + .dout(xu_mm_msr_gs_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THDID_WIDTH), .INIT(0)) xu_mm_msr_pr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rp_mm_event_bus_enable_int_q), + .thold_b(pc_func_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(force_t), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[xu_mm_msr_pr_offset:xu_mm_msr_pr_offset + `THDID_WIDTH - 1]), + .scout(sov[xu_mm_msr_pr_offset:xu_mm_msr_pr_offset + `THDID_WIDTH - 1]), + .din(xu_mm_msr_pr), + .dout(xu_mm_msr_pr_q) + ); + + + tri_rlmreg_p #(.WIDTH(`PERF_EVENT_WIDTH*`THREADS), .INIT(0)) event_bus_out_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rp_mm_event_bus_enable_int_q), + .thold_b(pc_func_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(force_t), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[event_bus_out_offset:event_bus_out_offset + `PERF_EVENT_WIDTH*`THREADS - 1]), + .scout(sov[event_bus_out_offset:event_bus_out_offset + `PERF_EVENT_WIDTH*`THREADS - 1]), + .din(event_bus_out_d), + .dout(event_bus_out_q) + ); + + + tri_regk #(.WIDTH(24), .INIT(0), .NEEDS_SRESET(0)) mm_perf_event_t0_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rp_mm_event_bus_enable_int_q), + .sg(pc_sg_0), + .force_t(pc_func_slp_nsl_force), + .d_mode(lcb_d_mode_dc), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .thold_b(pc_func_slp_nsl_thold_0_b), + .scin(tri_regk_unused_scan[0:23]), + .scout(tri_regk_unused_scan[0:23]), + .din(mm_perf_event_t0_d), + .dout(mm_perf_event_t0_q) + ); + + + tri_regk #(.WIDTH(24), .INIT(0), .NEEDS_SRESET(0)) mm_perf_event_t1_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rp_mm_event_bus_enable_int_q), + .sg(pc_sg_0), + .force_t(pc_func_slp_nsl_force), + .d_mode(lcb_d_mode_dc), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .thold_b(pc_func_slp_nsl_thold_0_b), + .scin(tri_regk_unused_scan[24:47]), + .scout(tri_regk_unused_scan[24:47]), + .din(mm_perf_event_t1_d), + .dout(mm_perf_event_t1_q) + ); + + + tri_regk #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(0)) mm_perf_event_core_level_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(rp_mm_event_bus_enable_int_q), + .sg(pc_sg_0), + .force_t(pc_func_slp_nsl_force), + .d_mode(lcb_d_mode_dc), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .thold_b(pc_func_slp_nsl_thold_0_b), + .scin(tri_regk_unused_scan[48:79]), + .scout(tri_regk_unused_scan[48:79]), + .din(mm_perf_event_core_level_d), + .dout(mm_perf_event_core_level_q) + ); + + + + //----------------------------------------------- + // pervasive + //----------------------------------------------- + + + tri_plat #(.WIDTH(4)) perv_2to1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + .din( {pc_func_sl_thold_2, pc_func_slp_nsl_thold_2, pc_sg_2, pc_fce_2} ), + .q( {pc_func_sl_thold_1, pc_func_slp_nsl_thold_1, pc_sg_1, pc_fce_1} ) + ); + + + tri_plat #(.WIDTH(4)) perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + .din( {pc_func_sl_thold_1, pc_func_slp_nsl_thold_1, pc_sg_1, pc_fce_1} ), + .q( {pc_func_sl_thold_0, pc_func_slp_nsl_thold_0, pc_sg_0, pc_fce_0} ) + ); + + + tri_lcbor perv_lcbor( + .clkoff_b(lcb_clkoff_dc_b), + .thold(pc_func_sl_thold_0), + .sg(pc_sg_0), + .act_dis(lcb_act_dis_dc), + .force_t(force_t), + .thold_b(pc_func_sl_thold_0_b) + ); + + + tri_lcbor perv_nsl_lcbor( + .clkoff_b(lcb_clkoff_dc_b), + .thold(pc_func_slp_nsl_thold_0), + .sg(pc_fce_0), + .act_dis(tidn), + .force_t(pc_func_slp_nsl_force), + .thold_b(pc_func_slp_nsl_thold_0_b) + ); + + //--------------------------------------------------------------------- + // Scan + //--------------------------------------------------------------------- + assign siv[0:scan_right] = {sov[1:scan_right], scan_in}; + assign scan_out = sov[0]; + + +endmodule diff --git a/dev/verilog/work/mmq_perv.v b/dev/verilog/work/mmq_perv.v new file mode 100755 index 0000000..f1e0443 --- /dev/null +++ b/dev/verilog/work/mmq_perv.v @@ -0,0 +1,867 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +// ********************************************************************* +// +// This is the ENTITY for mmq_perv (pervasive logic) +// +// ********************************************************************* + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" +`include "mmu_a2o.vh" + +module mmq_perv( + + inout vdd, + inout gnd, + (* pin_data ="PIN_FUNCTION=/G_CLK/" *) + input [0:`NCLK_WIDTH-1] nclk, + + input [0:1] pc_mm_sg_3, + input [0:1] pc_mm_func_sl_thold_3, + input [0:1] pc_mm_func_slp_sl_thold_3, + input pc_mm_gptr_sl_thold_3, + input pc_mm_fce_3, + + input pc_mm_time_sl_thold_3, + input pc_mm_repr_sl_thold_3, + input pc_mm_abst_sl_thold_3, + input pc_mm_abst_slp_sl_thold_3, + input pc_mm_cfg_sl_thold_3, + input pc_mm_cfg_slp_sl_thold_3, + input pc_mm_func_nsl_thold_3, + input pc_mm_func_slp_nsl_thold_3, + input pc_mm_ary_nsl_thold_3, + input pc_mm_ary_slp_nsl_thold_3, + + input tc_ac_ccflush_dc, + input tc_scan_diag_dc, + input tc_ac_scan_dis_dc_b, + + output [0:1] pc_sg_0, + output [0:1] pc_sg_1, + output [0:1] pc_sg_2, + output [0:1] pc_func_sl_thold_2, + output [0:1] pc_func_slp_sl_thold_2, + output pc_func_slp_nsl_thold_2, + output pc_cfg_sl_thold_2, + output pc_cfg_slp_sl_thold_2, + output pc_fce_2, + + output pc_time_sl_thold_0, + output pc_repr_sl_thold_0, + output pc_abst_sl_thold_0, + output pc_abst_slp_sl_thold_0, + output pc_ary_nsl_thold_0, + output pc_ary_slp_nsl_thold_0, + output [0:1] pc_func_sl_thold_0, + output [0:1] pc_func_sl_thold_0_b, + output [0:1] pc_func_slp_sl_thold_0, + output [0:1] pc_func_slp_sl_thold_0_b, + + output lcb_clkoff_dc_b, + output lcb_act_dis_dc, + output lcb_d_mode_dc, + output [0:4] lcb_delay_lclkr_dc, + output [0:4] lcb_mpw1_dc_b, + output lcb_mpw2_dc_b, + output g6t_gptr_lcb_clkoff_dc_b, + output g6t_gptr_lcb_act_dis_dc, + output g6t_gptr_lcb_d_mode_dc, + output [0:4] g6t_gptr_lcb_delay_lclkr_dc, + output [0:4] g6t_gptr_lcb_mpw1_dc_b, + output g6t_gptr_lcb_mpw2_dc_b, + output g8t_gptr_lcb_clkoff_dc_b, + output g8t_gptr_lcb_act_dis_dc, + output g8t_gptr_lcb_d_mode_dc, + output [0:4] g8t_gptr_lcb_delay_lclkr_dc, + output [0:4] g8t_gptr_lcb_mpw1_dc_b, + output g8t_gptr_lcb_mpw2_dc_b, + + // abist engine controls for arrays from pervasive + input [0:3] pc_mm_abist_dcomp_g6t_2r, + input [0:3] pc_mm_abist_di_0, + input [0:3] pc_mm_abist_di_g6t_2r, + input pc_mm_abist_ena_dc, + input pc_mm_abist_g6t_r_wb, + input pc_mm_abist_g8t1p_renb_0, + input pc_mm_abist_g8t_bw_0, + input pc_mm_abist_g8t_bw_1, + input [0:3] pc_mm_abist_g8t_dcomp, + input pc_mm_abist_g8t_wenb, + input [0:9] pc_mm_abist_raddr_0, + input [0:9] pc_mm_abist_waddr_0, + input pc_mm_abist_wl128_comp_ena, + + output pc_mm_abist_g8t_wenb_q, + output pc_mm_abist_g8t1p_renb_0_q, + output [0:3] pc_mm_abist_di_0_q, + output pc_mm_abist_g8t_bw_1_q, + output pc_mm_abist_g8t_bw_0_q, + output [0:9] pc_mm_abist_waddr_0_q, + output [0:9] pc_mm_abist_raddr_0_q, + output pc_mm_abist_wl128_comp_ena_q, + output [0:3] pc_mm_abist_g8t_dcomp_q, + output [0:3] pc_mm_abist_dcomp_g6t_2r_q, + output [0:3] pc_mm_abist_di_g6t_2r_q, + output pc_mm_abist_g6t_r_wb_q, + + // BOLT-ON pervasive stuff for asic + input pc_mm_bolt_sl_thold_3, + input pc_mm_bo_enable_3, // general bolt-on enable + output pc_mm_bolt_sl_thold_0, + output pc_mm_bo_enable_2, + +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + input gptr_scan_in, +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + output gptr_scan_out, + +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + input time_scan_in, + output time_scan_in_int, + input time_scan_out_int, +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + output time_scan_out, + +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + input [0:9] func_scan_in, + output [0:9] func_scan_in_int, + input [0:9] func_scan_out_int, +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + output [0:9] func_scan_out, + +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + input repr_scan_in, + output repr_scan_in_int, + input repr_scan_out_int, +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + output repr_scan_out, + +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + input [0:1] abst_scan_in, + output [0:1] abst_scan_in_int, + input [0:1] abst_scan_out_int, +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + output [0:1] abst_scan_out, + +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + input bcfg_scan_in, // config latches that are setup same on all cores + output bcfg_scan_in_int, + input bcfg_scan_out_int, +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + output bcfg_scan_out, + +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + input ccfg_scan_in, // config latches that could be setup differently on multiple cores + output ccfg_scan_in_int, + input ccfg_scan_out_int, +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + output ccfg_scan_out, + +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + input dcfg_scan_in, + output dcfg_scan_in_int, + input dcfg_scan_out_int, +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + output dcfg_scan_out + +); + + wire tidn; + wire tiup; + + wire [0:1] pc_func_sl_thold_2_int; + wire [0:1] pc_func_slp_sl_thold_2_int; + wire [0:1] pc_sg_2_int; + wire pc_gptr_sl_thold_2_int; + wire pc_fce_2_int; + wire pc_time_sl_thold_2_int; + wire pc_repr_sl_thold_2_int; + wire pc_abst_sl_thold_2_int; + wire pc_abst_slp_sl_thold_2_int; + wire pc_cfg_sl_thold_2_int; + wire pc_cfg_slp_sl_thold_2_int; + wire pc_func_nsl_thold_2_int; + wire pc_func_slp_nsl_thold_2_int; + wire pc_ary_nsl_thold_2_int; + wire pc_ary_slp_nsl_thold_2_int; + wire pc_mm_bolt_sl_thold_2_int; + + wire [0:1] pc_func_sl_thold_1_int; + wire [0:1] pc_func_slp_sl_thold_1_int; + wire [0:1] pc_sg_1_int; + wire pc_gptr_sl_thold_1_int; + wire pc_fce_1_int; + wire pc_time_sl_thold_1_int; + wire pc_repr_sl_thold_1_int; + wire pc_abst_sl_thold_1_int; + wire pc_abst_slp_sl_thold_1_int; + wire pc_cfg_sl_thold_1_int; + wire pc_cfg_slp_sl_thold_1_int; + wire pc_func_nsl_thold_1_int; + wire pc_func_slp_nsl_thold_1_int; + wire pc_ary_nsl_thold_1_int; + wire pc_ary_slp_nsl_thold_1_int; + wire pc_mm_bolt_sl_thold_1_int; + + wire [0:1] pc_func_sl_thold_0_int; + wire [0:1] pc_func_slp_sl_thold_0_int; + wire [0:1] pc_sg_0_int; + wire pc_gptr_sl_thold_0_int; + wire pc_fce_0_int; + wire pc_time_sl_thold_0_int; + wire pc_repr_sl_thold_0_int; + wire pc_abst_sl_thold_0_int; + wire pc_abst_slp_sl_thold_0_int; + wire pc_cfg_sl_thold_0_int; + wire pc_cfg_slp_sl_thold_0_int; + wire pc_func_nsl_thold_0_int; + wire pc_func_slp_nsl_thold_0_int; + wire pc_ary_nsl_thold_0_int; + wire pc_ary_slp_nsl_thold_0_int; + + wire [0:1] pc_func_sl_thold_0_b_int; + wire [0:1] pc_func_slp_sl_thold_0_b_int; + wire [0:1] pc_func_slp_sl_force_int; + wire [0:1] pc_func_sl_force_int; + + wire [0:1] abst_scan_in_q; + wire [0:1] abst_scan_out_q; + wire time_scan_in_q; + wire time_scan_out_q; + wire repr_scan_in_q; + wire repr_scan_out_q; + wire gptr_scan_in_q; + wire gptr_scan_out_int; + wire gptr_scan_out_q; + wire [0:1] gptr_scan_lcbctrl; + wire bcfg_scan_in_q; + wire bcfg_scan_out_q; + wire ccfg_scan_in_q; + wire ccfg_scan_out_q; + wire dcfg_scan_in_q; + wire dcfg_scan_out_q; + wire [0:9] func_scan_in_q; + wire [0:9] func_scan_out_q; + + wire [0:1] slat_force; + wire abst_slat_thold_b; + wire abst_slat_d2clk; + wire [0:`NCLK_WIDTH-1] abst_slat_lclk; + wire time_slat_thold_b; + wire time_slat_d2clk; + wire [0:`NCLK_WIDTH-1] time_slat_lclk; + wire repr_slat_thold_b; + wire repr_slat_d2clk; + wire [0:`NCLK_WIDTH-1] repr_slat_lclk; + wire gptr_slat_thold_b; + wire gptr_slat_d2clk; + wire [0:`NCLK_WIDTH-1] gptr_slat_lclk; + wire bcfg_slat_thold_b; + wire bcfg_slat_d2clk; + wire [0:`NCLK_WIDTH-1] bcfg_slat_lclk; + wire ccfg_slat_thold_b; + wire ccfg_slat_d2clk; + wire [0:`NCLK_WIDTH-1] ccfg_slat_lclk; + wire dcfg_slat_thold_b; + wire dcfg_slat_d2clk; + wire [0:`NCLK_WIDTH-1] dcfg_slat_lclk; + wire func_slat_thold_b; + wire func_slat_d2clk; + wire [0:`NCLK_WIDTH-1] func_slat_lclk; + + wire pc_abst_sl_thold_0_b; + wire pc_abst_sl_force; + wire [0:4] lcb_delay_lclkr_dc_int; + wire lcb_d_mode_dc_int; + wire [0:4] lcb_mpw1_dc_b_int; + wire lcb_mpw2_dc_b_int; + wire lcb_clkoff_dc_b_int; + + wire [0:41] abist_siv; + wire [0:41] abist_sov; + + (* analysis_not_referenced="true" *) + wire [0:8] unused_dc; + + (* analysis_not_referenced="true" *) + wire [0:3] perv_abst_stg_q, perv_abst_stg_q_b; + + (* analysis_not_referenced="true" *) + wire [0:1] perv_time_stg_q, perv_time_stg_q_b, perv_repr_stg_q, perv_repr_stg_q_b, + perv_gptr_stg_q, perv_gptr_stg_q_b, perv_bcfg_stg_q, perv_bcfg_stg_q_b, + perv_ccfg_stg_q, perv_ccfg_stg_q_b, perv_dcfg_stg_q, perv_dcfg_stg_q_b; + + (* analysis_not_referenced="true" *) + wire [0:19] perv_func_stg_q, perv_func_stg_q_b; + + assign tidn = 1'b0; + assign tiup = 1'b1; + + + tri_plat #(.WIDTH(20)) perv_3to2_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + .din( {pc_mm_sg_3[0:1], + pc_mm_func_slp_sl_thold_3[0:1], + pc_mm_func_sl_thold_3[0:1], + pc_mm_gptr_sl_thold_3, + pc_mm_fce_3, + pc_mm_time_sl_thold_3, + pc_mm_repr_sl_thold_3, + pc_mm_abst_sl_thold_3, + pc_mm_abst_slp_sl_thold_3, + pc_mm_cfg_sl_thold_3, + pc_mm_cfg_slp_sl_thold_3, + pc_mm_func_nsl_thold_3, + pc_mm_func_slp_nsl_thold_3, + pc_mm_ary_nsl_thold_3, + pc_mm_ary_slp_nsl_thold_3, + pc_mm_bolt_sl_thold_3, + pc_mm_bo_enable_3} ), + + .q( {pc_sg_2_int[0:1], + pc_func_slp_sl_thold_2_int[0:1], + pc_func_sl_thold_2_int[0:1], + pc_gptr_sl_thold_2_int, + pc_fce_2_int, + pc_time_sl_thold_2_int, + pc_repr_sl_thold_2_int, + pc_abst_sl_thold_2_int, + pc_abst_slp_sl_thold_2_int, + pc_cfg_sl_thold_2_int, + pc_cfg_slp_sl_thold_2_int, + pc_func_nsl_thold_2_int, + pc_func_slp_nsl_thold_2_int, + pc_ary_nsl_thold_2_int, + pc_ary_slp_nsl_thold_2_int, + pc_mm_bolt_sl_thold_2_int, + pc_mm_bo_enable_2} ) + ); + + + tri_plat #(.WIDTH(19)) perv_2to1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + .din( {pc_sg_2_int[0:1], + pc_func_slp_sl_thold_2_int[0:1], + pc_func_sl_thold_2_int[0:1], + pc_gptr_sl_thold_2_int, + pc_fce_2_int, + pc_time_sl_thold_2_int, + pc_repr_sl_thold_2_int, + pc_abst_sl_thold_2_int, + pc_abst_slp_sl_thold_2_int, + pc_cfg_sl_thold_2_int, + pc_cfg_slp_sl_thold_2_int, + pc_func_nsl_thold_2_int, + pc_func_slp_nsl_thold_2_int, + pc_ary_nsl_thold_2_int, + pc_ary_slp_nsl_thold_2_int, + pc_mm_bolt_sl_thold_2_int} ), + .q( {pc_sg_1_int[0:1], + pc_func_slp_sl_thold_1_int[0:1], + pc_func_sl_thold_1_int[0:1], + pc_gptr_sl_thold_1_int, + pc_fce_1_int, + pc_time_sl_thold_1_int, + pc_repr_sl_thold_1_int, + pc_abst_sl_thold_1_int, + pc_abst_slp_sl_thold_1_int, + pc_cfg_sl_thold_1_int, + pc_cfg_slp_sl_thold_1_int, + pc_func_nsl_thold_1_int, + pc_func_slp_nsl_thold_1_int, + pc_ary_nsl_thold_1_int, + pc_ary_slp_nsl_thold_1_int, + pc_mm_bolt_sl_thold_1_int} ) + ); + + + tri_plat #(.WIDTH(19)) perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + .din( {pc_sg_1_int[0:1], + pc_func_slp_sl_thold_1_int[0:1], + pc_func_sl_thold_1_int[0:1], + pc_gptr_sl_thold_1_int, + pc_fce_1_int, + pc_time_sl_thold_1_int, + pc_repr_sl_thold_1_int, + pc_abst_sl_thold_1_int, + pc_abst_slp_sl_thold_1_int, + pc_cfg_sl_thold_1_int, + pc_cfg_slp_sl_thold_1_int, + pc_func_nsl_thold_1_int, + pc_func_slp_nsl_thold_1_int, + pc_ary_nsl_thold_1_int, + pc_ary_slp_nsl_thold_1_int, + pc_mm_bolt_sl_thold_1_int} ), + .q( {pc_sg_0_int[0:1], + pc_func_slp_sl_thold_0_int[0:1], + pc_func_sl_thold_0_int[0:1], + pc_gptr_sl_thold_0_int, + pc_fce_0_int, + pc_time_sl_thold_0_int, + pc_repr_sl_thold_0_int, + pc_abst_sl_thold_0_int, + pc_abst_slp_sl_thold_0_int, + pc_cfg_sl_thold_0_int, + pc_cfg_slp_sl_thold_0_int, + pc_func_nsl_thold_0_int, + pc_func_slp_nsl_thold_0_int, + pc_ary_nsl_thold_0_int, + pc_ary_slp_nsl_thold_0_int, + pc_mm_bolt_sl_thold_0} ) + ); + + assign pc_time_sl_thold_0 = pc_time_sl_thold_0_int; + assign pc_abst_sl_thold_0 = pc_abst_sl_thold_0_int; + assign pc_abst_slp_sl_thold_0 = pc_abst_slp_sl_thold_0_int; + assign pc_repr_sl_thold_0 = pc_repr_sl_thold_0_int; + assign pc_ary_nsl_thold_0 = pc_ary_nsl_thold_0_int; + assign pc_ary_slp_nsl_thold_0 = pc_ary_slp_nsl_thold_0_int; + + assign pc_func_sl_thold_0 = pc_func_sl_thold_0_int; + assign pc_func_sl_thold_0_b = pc_func_sl_thold_0_b_int; + assign pc_func_slp_sl_thold_0 = pc_func_slp_sl_thold_0_int; + assign pc_func_slp_sl_thold_0_b = pc_func_slp_sl_thold_0_b_int; + + assign pc_sg_0 = pc_sg_0_int; + assign pc_sg_1 = pc_sg_1_int; + assign pc_sg_2 = pc_sg_2_int; + + assign pc_func_sl_thold_2 = pc_func_sl_thold_2_int; + assign pc_func_slp_sl_thold_2 = pc_func_slp_sl_thold_2_int; + assign pc_func_slp_nsl_thold_2 = pc_func_slp_nsl_thold_2_int; + assign pc_cfg_sl_thold_2 = pc_cfg_sl_thold_2_int; + assign pc_cfg_slp_sl_thold_2 = pc_cfg_slp_sl_thold_2_int; + assign pc_fce_2 = pc_fce_2_int; + + assign lcb_clkoff_dc_b = lcb_clkoff_dc_b_int; + assign lcb_d_mode_dc = lcb_d_mode_dc_int; + assign lcb_delay_lclkr_dc = lcb_delay_lclkr_dc_int; + assign lcb_mpw1_dc_b = lcb_mpw1_dc_b_int; + assign lcb_mpw2_dc_b = lcb_mpw2_dc_b_int; + + + tri_lcbcntl_mac perv_lcbctrl( + .vdd(vdd), + .gnd(gnd), + .sg(pc_sg_0_int[0]), + .nclk(nclk), + .scan_in(gptr_scan_in_q), + .scan_diag_dc(tc_scan_diag_dc), + .thold(pc_gptr_sl_thold_0_int), + .clkoff_dc_b(lcb_clkoff_dc_b_int), + .delay_lclkr_dc(lcb_delay_lclkr_dc_int[0:4]), + .act_dis_dc(unused_dc[6]), + .d_mode_dc(lcb_d_mode_dc_int), + .mpw1_dc_b(lcb_mpw1_dc_b_int[0:4]), + .mpw2_dc_b(lcb_mpw2_dc_b_int), + .scan_out(gptr_scan_lcbctrl[0]) + ); + + + tri_lcbcntl_array_mac perv_g6t_gptr_lcbctrl( + .vdd(vdd), + .gnd(gnd), + .sg(pc_sg_0_int[1]), + .nclk(nclk), + .scan_in(gptr_scan_lcbctrl[0]), + .scan_diag_dc(tc_scan_diag_dc), + .thold(pc_gptr_sl_thold_0_int), + .clkoff_dc_b(g6t_gptr_lcb_clkoff_dc_b), + .delay_lclkr_dc(g6t_gptr_lcb_delay_lclkr_dc[0:4]), + .act_dis_dc(unused_dc[7]), + .d_mode_dc(g6t_gptr_lcb_d_mode_dc), + .mpw1_dc_b(g6t_gptr_lcb_mpw1_dc_b[0:4]), + .mpw2_dc_b(g6t_gptr_lcb_mpw2_dc_b), + .scan_out(gptr_scan_lcbctrl[1]) + ); + + + tri_lcbcntl_array_mac perv_g8t_gptr_lcbctrl( + .vdd(vdd), + .gnd(gnd), + .sg(pc_sg_0_int[1]), + .nclk(nclk), + .scan_in(gptr_scan_lcbctrl[1]), + .scan_diag_dc(tc_scan_diag_dc), + .thold(pc_gptr_sl_thold_0_int), + .clkoff_dc_b(g8t_gptr_lcb_clkoff_dc_b), + .delay_lclkr_dc(g8t_gptr_lcb_delay_lclkr_dc[0:4]), + .act_dis_dc(unused_dc[8]), + .d_mode_dc(g8t_gptr_lcb_d_mode_dc), + .mpw1_dc_b(g8t_gptr_lcb_mpw1_dc_b[0:4]), + .mpw2_dc_b(g8t_gptr_lcb_mpw2_dc_b), + .scan_out(gptr_scan_out_int) + ); + + //never disable act pins, they are used functionally + assign lcb_act_dis_dc = 1'b0; + assign g8t_gptr_lcb_act_dis_dc = 1'b0; + assign g6t_gptr_lcb_act_dis_dc = 1'b0; + + assign time_scan_in_int = time_scan_in_q; + assign repr_scan_in_int = repr_scan_in_q; + assign func_scan_in_int = func_scan_in_q; + assign bcfg_scan_in_int = bcfg_scan_in_q; + assign ccfg_scan_in_int = ccfg_scan_in_q; + assign dcfg_scan_in_int = dcfg_scan_in_q; + + assign time_scan_out = time_scan_out_q & tc_ac_scan_dis_dc_b; + assign gptr_scan_out = gptr_scan_out_q & tc_ac_scan_dis_dc_b; + assign repr_scan_out = repr_scan_out_q & tc_ac_scan_dis_dc_b; + assign func_scan_out = func_scan_out_q & {10{tc_ac_scan_dis_dc_b}}; + assign abst_scan_out = abst_scan_out_q & {2{tc_ac_scan_dis_dc_b}}; + assign bcfg_scan_out = bcfg_scan_out_q & tc_ac_scan_dis_dc_b; + assign ccfg_scan_out = ccfg_scan_out_q & tc_ac_scan_dis_dc_b; + assign dcfg_scan_out = dcfg_scan_out_q & tc_ac_scan_dis_dc_b; + + // LCBs for scan only staging latches + assign slat_force = pc_sg_0_int; + assign abst_slat_thold_b = (~pc_abst_sl_thold_0_int); + assign time_slat_thold_b = (~pc_time_sl_thold_0_int); + assign repr_slat_thold_b = (~pc_repr_sl_thold_0_int); + assign gptr_slat_thold_b = (~pc_gptr_sl_thold_0_int); + assign bcfg_slat_thold_b = (~pc_cfg_sl_thold_0_int); + assign ccfg_slat_thold_b = (~pc_cfg_sl_thold_0_int); + assign dcfg_slat_thold_b = (~pc_cfg_sl_thold_0_int); + assign func_slat_thold_b = (~pc_func_sl_thold_0_int[0]); + + + tri_lcbs perv_lcbs_abst( + .vd(vdd), + .gd(gnd), + .delay_lclkr(lcb_delay_lclkr_dc_int[0]), + .nclk(nclk), + .force_t(slat_force[1]), + .thold_b(abst_slat_thold_b), + .dclk(abst_slat_d2clk), + .lclk(abst_slat_lclk) + ); + + + tri_slat_scan #(.WIDTH(4), .INIT(4'b0000)) perv_abst_stg( + .vd(vdd), + .gd(gnd), + .dclk(abst_slat_d2clk), + .lclk(abst_slat_lclk), + .scan_in( {abst_scan_out_int, abst_scan_in} ), + .scan_out( {abst_scan_out_q, abst_scan_in_q} ), + .q( perv_abst_stg_q), + .q_b( perv_abst_stg_q_b) + ); + + + tri_lcbs perv_lcbs_time( + .vd(vdd), + .gd(gnd), + .delay_lclkr(lcb_delay_lclkr_dc_int[0]), + .nclk(nclk), + .force_t(slat_force[1]), + .thold_b(time_slat_thold_b), + .dclk(time_slat_d2clk), + .lclk(time_slat_lclk) + ); + + + tri_slat_scan #(.WIDTH(2), .INIT(2'b00)) perv_time_stg( + .vd(vdd), + .gd(gnd), + .dclk(time_slat_d2clk), + .lclk(time_slat_lclk), + .scan_in( {time_scan_in, time_scan_out_int} ), + .scan_out( {time_scan_in_q, time_scan_out_q} ), + .q( perv_time_stg_q), + .q_b( perv_time_stg_q_b) + ); + + + tri_lcbs perv_lcbs_repr( + .vd(vdd), + .gd(gnd), + .delay_lclkr(lcb_delay_lclkr_dc_int[0]), + .nclk(nclk), + .force_t(slat_force[1]), + .thold_b(repr_slat_thold_b), + .dclk(repr_slat_d2clk), + .lclk(repr_slat_lclk) + ); + + + tri_slat_scan #(.WIDTH(2), .INIT(2'b00)) perv_repr_stg( + .vd(vdd), + .gd(gnd), + .dclk(repr_slat_d2clk), + .lclk(repr_slat_lclk), + .scan_in( {repr_scan_in, repr_scan_out_int} ), + .scan_out( {repr_scan_in_q, repr_scan_out_q} ), + .q( perv_repr_stg_q), + .q_b( perv_repr_stg_q_b) + ); + + + tri_lcbs perv_lcbs_gptr( + .vd(vdd), + .gd(gnd), + .delay_lclkr(tiup), + .nclk(nclk), + .force_t(slat_force[0]), + .thold_b(gptr_slat_thold_b), + .dclk(gptr_slat_d2clk), + .lclk(gptr_slat_lclk) + ); + + + tri_slat_scan #(.WIDTH(2), .INIT(2'b00)) perv_gptr_stg( + .vd(vdd), + .gd(gnd), + .dclk(gptr_slat_d2clk), + .lclk(gptr_slat_lclk), + .scan_in( {gptr_scan_in, gptr_scan_out_int} ), + .scan_out( {gptr_scan_in_q, gptr_scan_out_q} ), + .q( perv_gptr_stg_q), + .q_b( perv_gptr_stg_q_b) + ); + + + tri_lcbs perv_lcbs_bcfg( + .vd(vdd), + .gd(gnd), + .delay_lclkr(lcb_delay_lclkr_dc_int[0]), + .nclk(nclk), + .force_t(slat_force[0]), + .thold_b(bcfg_slat_thold_b), + .dclk(bcfg_slat_d2clk), + .lclk(bcfg_slat_lclk) + ); + + + tri_slat_scan #(.WIDTH(2), .INIT(2'b00)) perv_bcfg_stg( + .vd(vdd), + .gd(gnd), + .dclk(bcfg_slat_d2clk), + .lclk(bcfg_slat_lclk), + .scan_in( {bcfg_scan_in, bcfg_scan_out_int} ), + .scan_out( {bcfg_scan_in_q, bcfg_scan_out_q} ), + .q( perv_bcfg_stg_q), + .q_b( perv_bcfg_stg_q_b) + ); + + + tri_lcbs perv_lcbs_ccfg( + .vd(vdd), + .gd(gnd), + .delay_lclkr(lcb_delay_lclkr_dc_int[0]), + .nclk(nclk), + .force_t(slat_force[0]), + .thold_b(ccfg_slat_thold_b), + .dclk(ccfg_slat_d2clk), + .lclk(ccfg_slat_lclk) + ); + + + tri_slat_scan #(.WIDTH(2), .INIT(2'b00)) perv_ccfg_stg( + .vd(vdd), + .gd(gnd), + .dclk(ccfg_slat_d2clk), + .lclk(ccfg_slat_lclk), + .scan_in( {ccfg_scan_in, ccfg_scan_out_int} ), + .scan_out( {ccfg_scan_in_q, ccfg_scan_out_q} ), + .q( perv_ccfg_stg_q), + .q_b( perv_ccfg_stg_q_b) + ); + + + tri_lcbs perv_lcbs_dcfg( + .vd(vdd), + .gd(gnd), + .delay_lclkr(lcb_delay_lclkr_dc_int[0]), + .nclk(nclk), + .force_t(slat_force[0]), + .thold_b(dcfg_slat_thold_b), + .dclk(dcfg_slat_d2clk), + .lclk(dcfg_slat_lclk) + ); + + + tri_slat_scan #(.WIDTH(2), .INIT(2'b00)) perv_dcfg_stg( + .vd(vdd), + .gd(gnd), + .dclk(dcfg_slat_d2clk), + .lclk(dcfg_slat_lclk), + .scan_in( {dcfg_scan_in, dcfg_scan_out_int} ), + .scan_out( {dcfg_scan_in_q, dcfg_scan_out_q} ), + .q( perv_dcfg_stg_q), + .q_b( perv_dcfg_stg_q_b) + ); + + + tri_lcbs perv_lcbs_func( + .vd(vdd), + .gd(gnd), + .delay_lclkr(lcb_delay_lclkr_dc_int[0]), + .nclk(nclk), + .force_t(slat_force[0]), + .thold_b(func_slat_thold_b), + .dclk(func_slat_d2clk), + .lclk(func_slat_lclk) + ); + + + tri_slat_scan #(.WIDTH(20), .INIT(20'b00000000000000000000)) perv_func_stg( + .vd(vdd), + .gd(gnd), + .dclk(func_slat_d2clk), + .lclk(func_slat_lclk), + .scan_in( {func_scan_out_int, func_scan_in} ), + .scan_out( {func_scan_out_q, func_scan_in_q} ), + .q( perv_func_stg_q), + .q_b( perv_func_stg_q_b) + ); + + + tri_lcbor perv_lcbor_func_sl_0( + .clkoff_b(lcb_clkoff_dc_b_int), + .thold(pc_func_sl_thold_0_int[0]), + .sg(pc_sg_0_int[0]), + .act_dis(tidn), + .force_t(pc_func_sl_force_int[0]), + .thold_b(pc_func_sl_thold_0_b_int[0]) + ); + + + tri_lcbor perv_lcbor_func_sl_1( + .clkoff_b(lcb_clkoff_dc_b_int), + .thold(pc_func_sl_thold_0_int[1]), + .sg(pc_sg_0_int[1]), + .act_dis(tidn), + .force_t(pc_func_sl_force_int[1]), + .thold_b(pc_func_sl_thold_0_b_int[1]) + ); + + + tri_lcbor perv_lcbor_func_slp_sl_0( + .clkoff_b(lcb_clkoff_dc_b_int), + .thold(pc_func_slp_sl_thold_0_int[0]), + .sg(pc_sg_0_int[0]), + .act_dis(tidn), + .force_t(pc_func_slp_sl_force_int[0]), + .thold_b(pc_func_slp_sl_thold_0_b_int[0]) + ); + + + tri_lcbor perv_lcbor_func_slp_sl_1( + .clkoff_b(lcb_clkoff_dc_b_int), + .thold(pc_func_slp_sl_thold_0_int[1]), + .sg(pc_sg_0_int[1]), + .act_dis(tidn), + .force_t(pc_func_slp_sl_force_int[1]), + .thold_b(pc_func_slp_sl_thold_0_b_int[1]) + ); + + + tri_lcbor perv_lcbor_abst_sl( + .clkoff_b(lcb_clkoff_dc_b_int), + .thold(pc_abst_sl_thold_0_int), + .sg(pc_sg_0_int[1]), + .act_dis(tidn), + .force_t(pc_abst_sl_force), + .thold_b(pc_abst_sl_thold_0_b) + ); + + //--------------------------------------------------------------------- + // abist latches + //--------------------------------------------------------------------- + + + tri_rlmreg_p #(.INIT(0), .WIDTH(42), .NEEDS_SRESET(0)) abist_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(pc_mm_abist_ena_dc), + .thold_b(pc_abst_sl_thold_0_b), + .sg(pc_sg_0_int[1]), + .force_t(pc_abst_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc_int[0]), + .mpw1_b(lcb_mpw1_dc_b_int[0]), + .mpw2_b(lcb_mpw2_dc_b_int), + .d_mode(lcb_d_mode_dc_int), + .scin(abist_siv[0:41]), + .scout(abist_sov[0:41]), + .din( {pc_mm_abist_g8t_wenb, + pc_mm_abist_g8t1p_renb_0, + pc_mm_abist_di_0, + pc_mm_abist_g8t_bw_1, + pc_mm_abist_g8t_bw_0, + pc_mm_abist_waddr_0, + pc_mm_abist_raddr_0, + pc_mm_abist_wl128_comp_ena, + pc_mm_abist_g8t_dcomp, + pc_mm_abist_dcomp_g6t_2r, + pc_mm_abist_di_g6t_2r, + pc_mm_abist_g6t_r_wb} ), + .dout( {pc_mm_abist_g8t_wenb_q, + pc_mm_abist_g8t1p_renb_0_q, + pc_mm_abist_di_0_q, + pc_mm_abist_g8t_bw_1_q, + pc_mm_abist_g8t_bw_0_q, + pc_mm_abist_waddr_0_q, + pc_mm_abist_raddr_0_q, + pc_mm_abist_wl128_comp_ena_q, + pc_mm_abist_g8t_dcomp_q, + pc_mm_abist_dcomp_g6t_2r_q, + pc_mm_abist_di_g6t_2r_q, + pc_mm_abist_g6t_r_wb_q} ) + ); + + assign abist_siv = {abist_sov[1:41], abst_scan_in_q[0]}; + assign abst_scan_in_int[0] = abist_sov[0]; + assign abst_scan_in_int[1] = abst_scan_in_q[1]; + + // unused spare signal assignments + assign unused_dc[0] = pc_fce_0_int; + assign unused_dc[1] = pc_cfg_slp_sl_thold_0_int; + assign unused_dc[2] = pc_func_nsl_thold_0_int; + assign unused_dc[3] = pc_func_slp_nsl_thold_0_int; + assign unused_dc[4] = |(pc_func_sl_force_int); + assign unused_dc[5] = |(pc_func_slp_sl_force_int); + + +endmodule diff --git a/dev/verilog/work/mmq_spr.v b/dev/verilog/work/mmq_spr.v new file mode 100755 index 0000000..1452d5c --- /dev/null +++ b/dev/verilog/work/mmq_spr.v @@ -0,0 +1,5949 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +//******************************************************************** +//* TITLE: Memory Management Unit Special Purpose Registers +//********************************************************************* + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" +`include "mmu_a2o.vh" + +module mmq_spr( + + inout vdd, + inout gnd, + (* pin_data ="PIN_FUNCTION=/G_CLK/" *) + input [0:`NCLK_WIDTH-1] nclk, + + input [0:`THREADS-1] cp_flush, + output [0:`MM_THREADS-1] cp_flush_p1, + + input tc_ccflush_dc, + input tc_scan_dis_dc_b, + input tc_scan_diag_dc, + input tc_lbist_en_dc, + + input lcb_d_mode_dc, + input lcb_clkoff_dc_b, + input lcb_act_dis_dc, + input [0:4] lcb_mpw1_dc_b, + input lcb_mpw2_dc_b, + input [0:4] lcb_delay_lclkr_dc, + +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + input [0:1] ac_func_scan_in, +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + output [0:1] ac_func_scan_out, +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + input ac_bcfg_scan_in, +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + output ac_bcfg_scan_out, + + input pc_sg_2, + input pc_func_sl_thold_2, + input pc_func_slp_sl_thold_2, + input pc_func_slp_nsl_thold_2, + input pc_cfg_sl_thold_2, + input pc_cfg_slp_sl_thold_2, + input pc_fce_2, + input xu_mm_ccr2_notlb_b, + input [5:6] mmucr2_act_override, + input [29:29+`MM_THREADS-1] tlb_delayed_act, + +`ifdef WAIT_UPDATES + // 0 - val + // 1 - I=0/D=1 + // 2 - TLB miss + // 3 - Storage int (TLBI/PTfault) + // 4 - LRAT miss + // 5 - Mcheck + input [0:5] cp_mm_except_taken_t0, +`ifdef MM_THREADS2 + input [0:5] cp_mm_except_taken_t1, +`endif + output [0:`MM_THREADS+5-1] cp_mm_perf_except_taken_q, + // 0:1 - thdid/val + // 2 - I=0/D=1 + // 3 - TLB miss + // 4 - Storage int (TLBI/PTfault) + // 5 - LRAT miss + // 6 - Mcheck +`endif + + + output [0:`PID_WIDTH-1] mm_iu_ierat_pid0, +`ifdef MM_THREADS2 + output [0:`PID_WIDTH-1] mm_iu_ierat_pid1, +`endif + output [0:19] mm_iu_ierat_mmucr0_0, +`ifdef MM_THREADS2 + output [0:19] mm_iu_ierat_mmucr0_1, +`endif + input [0:17] iu_mm_ierat_mmucr0, + input [0:`MM_THREADS-1] iu_mm_ierat_mmucr0_we, + output [0:8] mm_iu_ierat_mmucr1, + input [0:3] iu_mm_ierat_mmucr1, + input [0:`MM_THREADS-1] iu_mm_ierat_mmucr1_we, + + output [0:`PID_WIDTH-1] mm_xu_derat_pid0, +`ifdef MM_THREADS2 + output [0:`PID_WIDTH-1] mm_xu_derat_pid1, +`endif + output [0:19] mm_xu_derat_mmucr0_0, +`ifdef MM_THREADS2 + output [0:19] mm_xu_derat_mmucr0_1, +`endif + input [0:17] xu_mm_derat_mmucr0, + input [0:`MM_THREADS-1] xu_mm_derat_mmucr0_we, + output [0:9] mm_xu_derat_mmucr1, + input [0:4] xu_mm_derat_mmucr1, + input [0:`MM_THREADS-1] xu_mm_derat_mmucr1_we, + + output [0:`PID_WIDTH-1] pid0, +`ifdef MM_THREADS2 + output [0:`PID_WIDTH-1] pid1, +`endif + output [0:`MMUCR0_WIDTH-1] mmucr0_0, +`ifdef MM_THREADS2 + output [0:`MMUCR0_WIDTH-1] mmucr0_1, +`endif + output [0:`MMUCR1_WIDTH-1] mmucr1, + output [0:`MMUCR2_WIDTH-1] mmucr2, + output [64-`MMUCR3_WIDTH:63] mmucr3_0, + output [1:3] tstmode4k_0, +`ifdef MM_THREADS2 + output [64-`MMUCR3_WIDTH:63] mmucr3_1, + output [1:3] tstmode4k_1, +`endif + + output mmucfg_lrat, + output mmucfg_twc, + output tlb0cfg_pt, + output tlb0cfg_ind, + output tlb0cfg_gtwe, + output [0:`MESR1_WIDTH+`MESR2_WIDTH-1] mmq_spr_event_mux_ctrls, + + output mas0_0_atsel, + output [0:2] mas0_0_esel, + output mas0_0_hes, + output [0:1] mas0_0_wq, + output mas1_0_v, + output mas1_0_iprot, + output [0:13] mas1_0_tid, + output mas1_0_ind, + output mas1_0_ts, + output [0:3] mas1_0_tsize, + output [0:51] mas2_0_epn, + output [0:4] mas2_0_wimge, + output [32:52] mas3_0_rpnl, + output [0:3] mas3_0_ubits, + output [0:5] mas3_0_usxwr, + output mas5_0_sgs, + output [0:7] mas5_0_slpid, + output [0:13] mas6_0_spid, + output [0:3] mas6_0_isize, + output mas6_0_sind, + output mas6_0_sas, + output [22:31] mas7_0_rpnu, + output mas8_0_tgs, + output mas8_0_vf, + output [0:7] mas8_0_tlpid, +`ifdef MM_THREADS2 + output mas0_1_atsel, + output [0:2] mas0_1_esel, + output mas0_1_hes, + output [0:1] mas0_1_wq, + output mas1_1_v, + output mas1_1_iprot, + output [0:13] mas1_1_tid, + output mas1_1_ind, + output mas1_1_ts, + output [0:3] mas1_1_tsize, + output [0:51] mas2_1_epn, + output [0:4] mas2_1_wimge, + output [32:52] mas3_1_rpnl, + output [0:3] mas3_1_ubits, + output [0:5] mas3_1_usxwr, + output mas5_1_sgs, + output [0:7] mas5_1_slpid, + output [0:13] mas6_1_spid, + output [0:3] mas6_1_isize, + output mas6_1_sind, + output mas6_1_sas, + output [22:31] mas7_1_rpnu, + output mas8_1_tgs, + output mas8_1_vf, + output [0:7] mas8_1_tlpid, +`endif + input [0:2] tlb_mas0_esel, + input tlb_mas1_v, + input tlb_mas1_iprot, + input [0:`PID_WIDTH-1] tlb_mas1_tid, + input [0:`PID_WIDTH-1] tlb_mas1_tid_error, + input tlb_mas1_ind, + input tlb_mas1_ts, + input tlb_mas1_ts_error, + input [0:3] tlb_mas1_tsize, + input [0:`EPN_WIDTH-1] tlb_mas2_epn, + input [0:`EPN_WIDTH-1] tlb_mas2_epn_error, + input [0:4] tlb_mas2_wimge, + input [32:51] tlb_mas3_rpnl, + input [0:3] tlb_mas3_ubits, + input [0:5] tlb_mas3_usxwr, + input [22:31] tlb_mas7_rpnu, + input tlb_mas8_tgs, + input tlb_mas8_vf, + input [0:7] tlb_mas8_tlpid, + + input [0:8] tlb_mmucr1_een, + input tlb_mmucr1_we, + input [0:`THDID_WIDTH-1] tlb_mmucr3_thdid, + input tlb_mmucr3_resvattr, + input [0:1] tlb_mmucr3_wlc, + input [0:`CLASS_WIDTH-1] tlb_mmucr3_class, + input [0:`EXTCLASS_WIDTH-1] tlb_mmucr3_extclass, + input [0:1] tlb_mmucr3_rc, + input tlb_mmucr3_x, + input tlb_mas_tlbre, + input tlb_mas_tlbsx_hit, + input tlb_mas_tlbsx_miss, + input tlb_mas_dtlb_error, + input tlb_mas_itlb_error, + input [0:`MM_THREADS-1] tlb_mas_thdid, + + output mmucsr0_tlb0fi, + input mmq_inval_tlb0fi_done, + + input lrat_mmucr3_x, + input [0:2] lrat_mas0_esel, + input lrat_mas1_v, + input [0:3] lrat_mas1_tsize, + input [0:51] lrat_mas2_epn, + input [32:51] lrat_mas3_rpnl, + input [22:31] lrat_mas7_rpnu, + input [0:`LPID_WIDTH-1] lrat_mas8_tlpid, + input lrat_mas_tlbre, + input lrat_mas_tlbsx_hit, + input lrat_mas_tlbsx_miss, + input [0:`MM_THREADS-1] lrat_mas_thdid, + input [0:2] lrat_tag4_hit_entry, + + input [64-`REAL_ADDR_WIDTH:51] tlb_lper_lpn, + input [60:63] tlb_lper_lps, + input [0:`MM_THREADS-1] tlb_lper_we, + + output [0:`LPID_WIDTH-1] lpidr, + output [0:`LPID_WIDTH-1] ac_an_lpar_id, + + output spr_dbg_match_64b, + output spr_dbg_match_any_mmu, + output spr_dbg_match_any_mas, + output spr_dbg_match_pid, + output spr_dbg_match_lpidr, + output spr_dbg_match_mmucr0, + output spr_dbg_match_mmucr1, + output spr_dbg_match_mmucr2, + output spr_dbg_match_mmucr3, + + output spr_dbg_match_mmucsr0, + output spr_dbg_match_mmucfg, + output spr_dbg_match_tlb0cfg, + output spr_dbg_match_tlb0ps, + output spr_dbg_match_lratcfg, + output spr_dbg_match_lratps, + output spr_dbg_match_eptcfg, + output spr_dbg_match_lper, + output spr_dbg_match_lperu, + + output spr_dbg_match_mas0, + output spr_dbg_match_mas1, + output spr_dbg_match_mas2, + output spr_dbg_match_mas2u, + output spr_dbg_match_mas3, + output spr_dbg_match_mas4, + output spr_dbg_match_mas5, + output spr_dbg_match_mas6, + output spr_dbg_match_mas7, + output spr_dbg_match_mas8, + output spr_dbg_match_mas01_64b, + output spr_dbg_match_mas56_64b, + output spr_dbg_match_mas73_64b, + output spr_dbg_match_mas81_64b, + + output spr_dbg_slowspr_val_int, + output spr_dbg_slowspr_rw_int, + output [0:1] spr_dbg_slowspr_etid_int, + output [0:9] spr_dbg_slowspr_addr_int, + output spr_dbg_slowspr_val_out, + output spr_dbg_slowspr_done_out, + output [64-`SPR_DATA_WIDTH:63] spr_dbg_slowspr_data_out, + + input xu_mm_slowspr_val, + input xu_mm_slowspr_rw, + input [0:1] xu_mm_slowspr_etid, + input [0:9] xu_mm_slowspr_addr, + input [64-`SPR_DATA_WIDTH:63] xu_mm_slowspr_data, + input xu_mm_slowspr_done, + + output mm_iu_slowspr_val, + output mm_iu_slowspr_rw, + output [0:1] mm_iu_slowspr_etid, + output [0:9] mm_iu_slowspr_addr, + output [64-`SPR_DATA_WIDTH:63] mm_iu_slowspr_data, + + output mm_iu_slowspr_done + +); + + parameter BCFG_MMUCR1_VALUE = 201326592; // mmucr1 32-bits boot value, 201326592 -> bits 4:5 csinv="11" + parameter BCFG_MMUCR2_VALUE = 685361; // mmucr2 32-bits boot value, 0xa7531 + parameter BCFG_MMUCR3_VALUE = 15; // mmucr2 15-bits boot value, 0x000f + parameter BCFG_MMUCFG_VALUE = 3; // mmucfg lrat|twc bits boot value + parameter BCFG_TLB0CFG_VALUE = 7; // tlb0cfg pt|ind|gtwe bits boot value + parameter MMQ_SPR_CSWITCH_0TO3 = 8; // chicken switch values: 8=disable mmucr1 read clear, 4=disable mmucr1.tlbwe_binv + + + parameter [0:9] Spr_Addr_PID = 10'b0000110000; + //constant Spr_Addr_LPID : std_ulogic_vector(0 to 9) := 1001111110 ; -- dec 638 + parameter [0:9] Spr_Addr_LPID = 10'b0101010010; + parameter [0:9] Spr_Addr_MMUCR0 = 10'b1111111100; + parameter [0:9] Spr_Addr_MMUCR1 = 10'b1111111101; + parameter [0:9] Spr_Addr_MMUCR2 = 10'b1111111110; + parameter [0:9] Spr_Addr_MMUCR3 = 10'b1111111111; + parameter Spr_RW_Write = 1'b0; + parameter Spr_RW_Read = 1'b1; + parameter [0:9] Spr_Addr_MESR1 = 10'b1110010100; + parameter [0:9] Spr_Addr_MESR2 = 10'b1110010101; + parameter [0:9] Spr_Addr_MAS0 = 10'b1001110000; + parameter [0:9] Spr_Addr_MAS1 = 10'b1001110001; + parameter [0:9] Spr_Addr_MAS2 = 10'b1001110010; + parameter [0:9] Spr_Addr_MAS2U = 10'b1001110111; + parameter [0:9] Spr_Addr_MAS3 = 10'b1001110011; + parameter [0:9] Spr_Addr_MAS4 = 10'b1001110100; + parameter [0:9] Spr_Addr_MAS5 = 10'b0101010011; + parameter [0:9] Spr_Addr_MAS6 = 10'b1001110110; + parameter [0:9] Spr_Addr_MAS7 = 10'b1110110000; + parameter [0:9] Spr_Addr_MAS8 = 10'b0101010101; + parameter [0:9] Spr_Addr_MAS56_64b = 10'b0101011100; + parameter [0:9] Spr_Addr_MAS81_64b = 10'b0101011101; + parameter [0:9] Spr_Addr_MAS73_64b = 10'b0101110100; + parameter [0:9] Spr_Addr_MAS01_64b = 10'b0101110101; + parameter [0:9] Spr_Addr_MMUCFG = 10'b1111110111; + parameter [0:9] Spr_Addr_MMUCSR0 = 10'b1111110100; + parameter [0:9] Spr_Addr_TLB0CFG = 10'b1010110000; + parameter [0:9] Spr_Addr_TLB0PS = 10'b0101011000; + parameter [0:9] Spr_Addr_LRATCFG = 10'b0101010110; + parameter [0:9] Spr_Addr_LRATPS = 10'b0101010111; + parameter [0:9] Spr_Addr_EPTCFG = 10'b0101011110; + parameter [0:9] Spr_Addr_LPER = 10'b0000111000; + parameter [0:9] Spr_Addr_LPERU = 10'b0000111001; + // MMUCFG: 32:35 resv, 36:39 LPIDSIZE=0x8, 40:46 RASIZE=0x2a, 47 LRAT bcfg, 48 TWC bcfg, + // 49:52 resv, 53:57 PIDSIZE=0xd, 58:59 resv, 60:61 NTLBS=0b00, 62:63 MAVN=0b01 + parameter [32:63] Spr_Data_MMUCFG = 32'b00001000010101011000001101000001; + // TLB0CFG: 32:39 ASSOC=0x04, 40:44 resv, 45 PT bcfg, 46 IND bcfg, 47 GTWE bcfg, + // 48 IPROT=1, 49 resv, 50 HES=1, 51 resv, 52:63 NENTRY=0x200 + parameter [32:63] Spr_Data_TLB0CFG = 32'b00000100000000001010001000000000; + // TLB0PS: 32:63 PS31-PS0=0x0010_4444 (PS20, PS14, PS10, PS6, PS2 = 1, others = 0) + parameter [32:63] Spr_Data_TLB0PS = 32'b00000000000100000100010001000100; + // LRATCFG: 32:39 ASSOC=0x00, 40:46 LASIZE=0x2a, 47:49 resv, 50 LPID=1, 51 resv, 52:63 NENTRY=0x008 + parameter [32:63] Spr_Data_LRATCFG = 32'b00000000010101000010000000001000; + // LRATPS: 32:63 PS31-PS0=0x5154_4400 (PS30, PS28, PS24, PS22, PS20, PS18, PS14, PS10 = 1, others = 0) + parameter [32:63] Spr_Data_LRATPS = 32'b01010001010101000100010000000000; + // EPTCFG: 32:43 resv, 44:48 PS1=0x12, 49:53 SPS1=0x06, 54:58 PS0=0x0a, 59:63 SPS0=0x02 + parameter [32:63] Spr_Data_EPTCFG = 32'b00000000000010010001100101000010; + + parameter [0:15] TSTMODE4KCONST1 = 16'b0101101001101001; // 0x5A69 + parameter [0:11] TSTMODE4KCONST2 = 12'b110000111011; // 0xC3B + + // latches scan chain constants + parameter cp_flush_offset = 0; + parameter cp_flush_p1_offset = cp_flush_offset + `MM_THREADS; + parameter spr_ctl_in_offset = cp_flush_p1_offset + `MM_THREADS; + parameter spr_etid_in_offset = spr_ctl_in_offset + `SPR_CTL_WIDTH; + parameter spr_addr_in_offset = spr_etid_in_offset + `SPR_ETID_WIDTH; + parameter spr_data_in_offset = spr_addr_in_offset + `SPR_ADDR_WIDTH; + parameter spr_ctl_int_offset = spr_data_in_offset + `SPR_DATA_WIDTH; + parameter spr_etid_int_offset = spr_ctl_int_offset + `SPR_CTL_WIDTH; + parameter spr_addr_int_offset = spr_etid_int_offset + `SPR_ETID_WIDTH; + parameter spr_data_int_offset = spr_addr_int_offset + `SPR_ADDR_WIDTH; + parameter spr_ctl_out_offset = spr_data_int_offset + `SPR_DATA_WIDTH; + parameter spr_etid_out_offset = spr_ctl_out_offset + `SPR_CTL_WIDTH; + parameter spr_addr_out_offset = spr_etid_out_offset + `SPR_ETID_WIDTH; + parameter spr_data_out_offset = spr_addr_out_offset + `SPR_ADDR_WIDTH; + parameter spr_match_any_mmu_offset = spr_data_out_offset + `SPR_DATA_WIDTH; + parameter spr_match_pid0_offset = spr_match_any_mmu_offset + 1; +`ifdef MM_THREADS2 + parameter spr_match_pid1_offset = spr_match_pid0_offset + 1; + parameter spr_match_mmucr0_0_offset = spr_match_pid1_offset + 1; + parameter spr_match_mmucr0_1_offset = spr_match_mmucr0_0_offset + 1; + parameter spr_match_mmucr1_offset = spr_match_mmucr0_1_offset + 1; +`else + parameter spr_match_mmucr0_0_offset = spr_match_pid0_offset + 1; + parameter spr_match_mmucr1_offset = spr_match_mmucr0_0_offset + 1; +`endif + parameter spr_match_mmucr2_offset = spr_match_mmucr1_offset + 1; + parameter spr_match_mmucr3_0_offset = spr_match_mmucr2_offset + 1; +`ifdef MM_THREADS2 + parameter spr_match_mmucr3_1_offset = spr_match_mmucr3_0_offset + 1; + parameter spr_match_lpidr_offset = spr_match_mmucr3_1_offset + 1; +`else + parameter spr_match_lpidr_offset = spr_match_mmucr3_0_offset + 1; +`endif + parameter spr_match_mesr1_offset = spr_match_lpidr_offset + 1; + parameter spr_match_mesr2_offset = spr_match_mesr1_offset + 1; + parameter pid0_offset = spr_match_mesr2_offset + 1; +`ifdef MM_THREADS2 + parameter pid1_offset = pid0_offset + `PID_WIDTH; + parameter mmucr0_0_offset = pid1_offset + `PID_WIDTH; +`else + parameter mmucr0_0_offset = pid0_offset + `PID_WIDTH; +`endif +`ifdef MM_THREADS2 + parameter mmucr0_1_offset = mmucr0_0_offset + `MMUCR0_WIDTH; + parameter lpidr_offset = mmucr0_1_offset + `MMUCR0_WIDTH; +`else + parameter lpidr_offset = mmucr0_0_offset + `MMUCR0_WIDTH; +`endif + parameter mesr1_offset = lpidr_offset + `LPID_WIDTH; + parameter mesr2_offset = mesr1_offset + `MESR1_WIDTH; + parameter spare_a_offset = mesr2_offset + `MESR2_WIDTH; + parameter spr_mmu_act_offset = spare_a_offset + 32; + parameter spr_val_act_offset = spr_mmu_act_offset + `MM_THREADS + 1; +`ifdef WAIT_UPDATES + parameter cp_mm_except_taken_t0_offset = spr_val_act_offset + 4; + parameter tlb_mas_dtlb_error_pending_offset = cp_mm_except_taken_t0_offset + 6; + parameter tlb_mas_itlb_error_pending_offset = tlb_mas_dtlb_error_pending_offset + `MM_THREADS; + parameter tlb_lper_we_pending_offset = tlb_mas_itlb_error_pending_offset + `MM_THREADS; + parameter tlb_mmucr1_we_pending_offset = tlb_lper_we_pending_offset + `MM_THREADS; + parameter ierat_mmucr1_we_pending_offset = tlb_mmucr1_we_pending_offset + `MM_THREADS; + parameter derat_mmucr1_we_pending_offset = ierat_mmucr1_we_pending_offset + `MM_THREADS; + parameter tlb_mas1_0_ts_error_offset = derat_mmucr1_we_pending_offset + `MM_THREADS; + parameter tlb_mas1_0_tid_error_offset = tlb_mas1_0_ts_error_offset + 1; + parameter tlb_mas2_0_epn_error_offset = tlb_mas1_0_tid_error_offset + `PID_WIDTH; + parameter tlb_lper_0_lpn_offset = tlb_mas2_0_epn_error_offset + `EPN_WIDTH; + parameter tlb_lper_0_lps_offset = tlb_lper_0_lpn_offset + `REAL_ADDR_WIDTH-12; + parameter tlb_mmucr1_0_een_offset = tlb_lper_0_lps_offset + 4; + parameter ierat_mmucr1_0_een_offset = tlb_mmucr1_0_een_offset + 9; + parameter derat_mmucr1_0_een_offset = ierat_mmucr1_0_een_offset + 4; +`ifdef MM_THREADS2 + parameter cp_mm_except_taken_t1_offset = derat_mmucr1_0_een_offset + 5; + parameter tlb_mas1_1_ts_error_offset = cp_mm_except_taken_t1_offset + 6; + parameter tlb_mas1_1_tid_error_offset = tlb_mas1_1_ts_error_offset + 1; + parameter tlb_mas2_1_epn_error_offset = tlb_mas1_1_tid_error_offset + `PID_WIDTH; + parameter tlb_lper_1_lpn_offset = tlb_mas2_1_epn_error_offset + `EPN_WIDTH; + parameter tlb_lper_1_lps_offset = tlb_lper_1_lpn_offset + `REAL_ADDR_WIDTH-12; + parameter tlb_mmucr1_1_een_offset = tlb_lper_1_lps_offset + 4; + parameter ierat_mmucr1_1_een_offset = tlb_mmucr1_1_een_offset + 9; + parameter derat_mmucr1_1_een_offset = ierat_mmucr1_1_een_offset + 4; + parameter cswitch_offset = derat_mmucr1_1_een_offset + 5; +`else + parameter cswitch_offset = derat_mmucr1_0_een_offset + 5; +`endif +`else + parameter cswitch_offset = spr_val_act_offset + 4; +`endif + parameter scan_right_0 = cswitch_offset + 4 - 1; + + + // MAS register constants + parameter spr_match_mmucsr0_offset = 0; + parameter spr_match_mmucfg_offset = spr_match_mmucsr0_offset + 1; + parameter spr_match_tlb0cfg_offset = spr_match_mmucfg_offset + 1; + parameter spr_match_tlb0ps_offset = spr_match_tlb0cfg_offset + 1; + parameter spr_match_lratcfg_offset = spr_match_tlb0ps_offset + 1; + parameter spr_match_lratps_offset = spr_match_lratcfg_offset + 1; + parameter spr_match_eptcfg_offset = spr_match_lratps_offset + 1; + parameter spr_match_lper_0_offset = spr_match_eptcfg_offset + 1; +`ifdef MM_THREADS2 + parameter spr_match_lper_1_offset = spr_match_lper_0_offset + 1; + parameter spr_match_lperu_0_offset = spr_match_lper_1_offset + 1; + parameter spr_match_lperu_1_offset = spr_match_lperu_0_offset + 1; + parameter spr_match_mas0_0_offset = spr_match_lperu_1_offset + 1; +`else + parameter spr_match_lperu_0_offset = spr_match_lper_0_offset + 1; + parameter spr_match_mas0_0_offset = spr_match_lperu_0_offset + 1; +`endif + parameter spr_match_mas1_0_offset = spr_match_mas0_0_offset + 1; + parameter spr_match_mas2_0_offset = spr_match_mas1_0_offset + 1; + parameter spr_match_mas2u_0_offset = spr_match_mas2_0_offset + 1; + parameter spr_match_mas3_0_offset = spr_match_mas2u_0_offset + 1; + parameter spr_match_mas4_0_offset = spr_match_mas3_0_offset + 1; + parameter spr_match_mas5_0_offset = spr_match_mas4_0_offset + 1; + parameter spr_match_mas6_0_offset = spr_match_mas5_0_offset + 1; + parameter spr_match_mas7_0_offset = spr_match_mas6_0_offset + 1; + parameter spr_match_mas8_0_offset = spr_match_mas7_0_offset + 1; + parameter spr_match_mas01_64b_0_offset = spr_match_mas8_0_offset + 1; + parameter spr_match_mas56_64b_0_offset = spr_match_mas01_64b_0_offset + 1; + parameter spr_match_mas73_64b_0_offset = spr_match_mas56_64b_0_offset + 1; + parameter spr_match_mas81_64b_0_offset = spr_match_mas73_64b_0_offset + 1; +`ifdef MM_THREADS2 + parameter spr_match_mas0_1_offset = spr_match_mas81_64b_0_offset + 1; + parameter spr_match_mas1_1_offset = spr_match_mas0_1_offset + 1; + parameter spr_match_mas2_1_offset = spr_match_mas1_1_offset + 1; + parameter spr_match_mas2u_1_offset = spr_match_mas2_1_offset + 1; + parameter spr_match_mas3_1_offset = spr_match_mas2u_1_offset + 1; + parameter spr_match_mas4_1_offset = spr_match_mas3_1_offset + 1; + parameter spr_match_mas5_1_offset = spr_match_mas4_1_offset + 1; + parameter spr_match_mas6_1_offset = spr_match_mas5_1_offset + 1; + parameter spr_match_mas7_1_offset = spr_match_mas6_1_offset + 1; + parameter spr_match_mas8_1_offset = spr_match_mas7_1_offset + 1; + parameter spr_match_mas01_64b_1_offset = spr_match_mas8_1_offset + 1; + parameter spr_match_mas56_64b_1_offset = spr_match_mas01_64b_1_offset + 1; + parameter spr_match_mas73_64b_1_offset = spr_match_mas56_64b_1_offset + 1; + parameter spr_match_mas81_64b_1_offset = spr_match_mas73_64b_1_offset + 1; + parameter spr_match_64b_offset = spr_match_mas81_64b_1_offset + 1; +`else + parameter spr_match_64b_offset = spr_match_mas81_64b_0_offset + 1; +`endif + parameter spr_addr_in_clone_offset = spr_match_64b_offset + 1; + parameter spr_mas_data_out_offset = spr_addr_in_clone_offset + `SPR_ADDR_WIDTH; + parameter spr_match_any_mas_offset = spr_mas_data_out_offset + `SPR_DATA_WIDTH; + parameter mas0_0_atsel_offset = spr_match_any_mas_offset + 1; + parameter mas0_0_esel_offset = mas0_0_atsel_offset + 1; + parameter mas0_0_hes_offset = mas0_0_esel_offset + 3; + parameter mas0_0_wq_offset = mas0_0_hes_offset + 1; + parameter mas1_0_v_offset = mas0_0_wq_offset + 2; + parameter mas1_0_iprot_offset = mas1_0_v_offset + 1; + parameter mas1_0_tid_offset = mas1_0_iprot_offset + 1; + parameter mas1_0_ind_offset = mas1_0_tid_offset + `PID_WIDTH; + parameter mas1_0_ts_offset = mas1_0_ind_offset + 1; + parameter mas1_0_tsize_offset = mas1_0_ts_offset + 1; + parameter mas2_0_epn_offset = mas1_0_tsize_offset + 4; + parameter mas2_0_wimge_offset = mas2_0_epn_offset + `EPN_WIDTH + `SPR_DATA_WIDTH - 64; + parameter mas3_0_rpnl_offset = mas2_0_wimge_offset + 5; + parameter mas3_0_ubits_offset = mas3_0_rpnl_offset + 21; + parameter mas3_0_usxwr_offset = mas3_0_ubits_offset + 4; + parameter mas5_0_sgs_offset = mas3_0_usxwr_offset + 6; + parameter mas5_0_slpid_offset = mas5_0_sgs_offset + 1; + parameter mas6_0_spid_offset = mas5_0_slpid_offset + 8; + parameter mas6_0_isize_offset = mas6_0_spid_offset + 14; + parameter mas6_0_sind_offset = mas6_0_isize_offset + 4; + parameter mas6_0_sas_offset = mas6_0_sind_offset + 1; + parameter mas7_0_rpnu_offset = mas6_0_sas_offset + 1; + parameter mas8_0_tgs_offset = mas7_0_rpnu_offset + 10; + parameter mas8_0_vf_offset = mas8_0_tgs_offset + 1; + parameter mas8_0_tlpid_offset = mas8_0_vf_offset + 1; +`ifdef MM_THREADS2 + parameter mas0_1_atsel_offset = mas8_0_tlpid_offset + `LPID_WIDTH; + parameter mas0_1_esel_offset = mas0_1_atsel_offset + 1; + parameter mas0_1_hes_offset = mas0_1_esel_offset + 3; + parameter mas0_1_wq_offset = mas0_1_hes_offset + 1; + parameter mas1_1_v_offset = mas0_1_wq_offset + 2; + parameter mas1_1_iprot_offset = mas1_1_v_offset + 1; + parameter mas1_1_tid_offset = mas1_1_iprot_offset + 1; + parameter mas1_1_ind_offset = mas1_1_tid_offset + `PID_WIDTH; + parameter mas1_1_ts_offset = mas1_1_ind_offset + 1; + parameter mas1_1_tsize_offset = mas1_1_ts_offset + 1; + parameter mas2_1_epn_offset = mas1_1_tsize_offset + 4; + parameter mas2_1_wimge_offset = mas2_1_epn_offset + `EPN_WIDTH + `SPR_DATA_WIDTH - 64; + parameter mas3_1_rpnl_offset = mas2_1_wimge_offset + 5; + parameter mas3_1_ubits_offset = mas3_1_rpnl_offset + 21; + parameter mas3_1_usxwr_offset = mas3_1_ubits_offset + 4; + parameter mas5_1_sgs_offset = mas3_1_usxwr_offset + 6; + parameter mas5_1_slpid_offset = mas5_1_sgs_offset + 1; + parameter mas6_1_spid_offset = mas5_1_slpid_offset + 8; + parameter mas6_1_isize_offset = mas6_1_spid_offset + 14; + parameter mas6_1_sind_offset = mas6_1_isize_offset + 4; + parameter mas6_1_sas_offset = mas6_1_sind_offset + 1; + parameter mas7_1_rpnu_offset = mas6_1_sas_offset + 1; + parameter mas8_1_tgs_offset = mas7_1_rpnu_offset + 10; + parameter mas8_1_vf_offset = mas8_1_tgs_offset + 1; + parameter mas8_1_tlpid_offset = mas8_1_vf_offset + 1; + parameter mmucsr0_tlb0fi_offset = mas8_1_tlpid_offset + `LPID_WIDTH; +`else + parameter mmucsr0_tlb0fi_offset = mas8_0_tlpid_offset + `LPID_WIDTH; +`endif + parameter lper_0_alpn_offset = mmucsr0_tlb0fi_offset + 1; + parameter lper_0_lps_offset = lper_0_alpn_offset + `REAL_ADDR_WIDTH - 12; +`ifdef MM_THREADS2 + parameter lper_1_alpn_offset = lper_0_lps_offset + 4; + parameter lper_1_lps_offset = lper_1_alpn_offset + `REAL_ADDR_WIDTH - 12; + parameter spare_b_offset = lper_1_lps_offset + 4; +`else + parameter spare_b_offset = lper_0_lps_offset + 4; +`endif + parameter cat_emf_act_offset = spare_b_offset + 64; + parameter scan_right_1 = cat_emf_act_offset + `MM_THREADS - 1; + + // boot config scan bits + parameter mmucfg_offset = 0; + parameter tlb0cfg_offset = mmucfg_offset + 2; + parameter mmucr1_offset = tlb0cfg_offset + 3; + parameter mmucr2_offset = mmucr1_offset + `MMUCR1_WIDTH; +`ifdef MM_THREADS2 + parameter mmucr3_0_offset = mmucr2_offset + `MMUCR2_WIDTH; + parameter tstmode4k_0_offset = mmucr3_0_offset + `MMUCR3_WIDTH; + parameter mmucr3_1_offset = tstmode4k_0_offset + 4; + parameter tstmode4k_1_offset = mmucr3_1_offset + `MMUCR3_WIDTH; + parameter mas4_0_indd_offset = tstmode4k_1_offset + 4; + parameter mas4_0_tsized_offset = mas4_0_indd_offset + 1; + parameter mas4_0_wimged_offset = mas4_0_tsized_offset + 4; + parameter mas4_1_indd_offset = mas4_0_wimged_offset + 5; + parameter mas4_1_tsized_offset = mas4_1_indd_offset + 1; + parameter mas4_1_wimged_offset = mas4_1_tsized_offset + 4; + parameter bcfg_spare_offset = mas4_1_wimged_offset + 5; + parameter boot_scan_right = bcfg_spare_offset + 16 - 1; +`else + parameter mmucr3_0_offset = mmucr2_offset + `MMUCR2_WIDTH; + parameter tstmode4k_0_offset = mmucr3_0_offset + `MMUCR3_WIDTH; + parameter mas4_0_indd_offset = tstmode4k_0_offset + 4; + parameter mas4_0_tsized_offset = mas4_0_indd_offset + 1; + parameter mas4_0_wimged_offset = mas4_0_tsized_offset + 4; + parameter bcfg_spare_offset = mas4_0_wimged_offset + 5; + parameter boot_scan_right = bcfg_spare_offset + 16 - 1; +`endif + +`ifdef MM_THREADS2 + parameter BUGSP_MM_THREADS = 2; +`else + parameter BUGSP_MM_THREADS = 1; +`endif + + wire spr_match_any_mmu; + wire spr_match_any_mmu_q; + wire spr_match_pid0; + wire spr_match_pid0_q; + wire spr_match_mmucr0_0; + wire spr_match_mmucr0_0_q; + wire spr_match_mmucr3_0; + wire spr_match_mmucr3_0_q; +`ifdef MM_THREADS2 + wire spr_match_pid1; + wire spr_match_pid1_q; + wire spr_match_mmucr0_1; + wire spr_match_mmucr0_1_q; + wire spr_match_mmucr3_1; + wire spr_match_mmucr3_1_q; +`endif + wire spr_match_mmucr1; + wire spr_match_mmucr1_q; + wire spr_match_mmucr2; + wire spr_match_mmucr2_q; + wire spr_match_lpidr; + wire spr_match_lpidr_q; + wire spr_match_mesr1; + wire spr_match_mesr1_q; + wire spr_match_mesr2; + wire spr_match_mesr2_q; + wire spr_match_mmucsr0; + wire spr_match_mmucsr0_q; + wire spr_match_mmucfg; + wire spr_match_mmucfg_q; + wire spr_match_tlb0cfg; + wire spr_match_tlb0cfg_q; + wire spr_match_tlb0ps; + wire spr_match_tlb0ps_q; + wire spr_match_lratcfg; + wire spr_match_lratcfg_q; + wire spr_match_lratps; + wire spr_match_lratps_q; + wire spr_match_eptcfg; + wire spr_match_eptcfg_q; + wire spr_match_lper_0; + wire spr_match_lper_0_q; + wire spr_match_lperu_0; + wire spr_match_lperu_0_q; +`ifdef MM_THREADS2 + wire spr_match_lper_1; + wire spr_match_lper_1_q; + wire spr_match_lperu_1; + wire spr_match_lperu_1_q; +`endif + wire spr_match_mas0_0; + wire spr_match_mas0_0_q; + wire spr_match_mas1_0; + wire spr_match_mas1_0_q; + wire spr_match_mas2_0; + wire spr_match_mas2_0_q; + wire spr_match_mas2u_0; + wire spr_match_mas2u_0_q; + wire spr_match_mas3_0; + wire spr_match_mas3_0_q; + wire spr_match_mas4_0; + wire spr_match_mas4_0_q; + wire spr_match_mas5_0; + wire spr_match_mas5_0_q; + wire spr_match_mas6_0; + wire spr_match_mas6_0_q; + wire spr_match_mas7_0; + wire spr_match_mas7_0_q; + wire spr_match_mas8_0; + wire spr_match_mas8_0_q; + wire spr_match_mas01_64b_0; + wire spr_match_mas01_64b_0_q; + wire spr_match_mas56_64b_0; + wire spr_match_mas56_64b_0_q; + wire spr_match_mas73_64b_0; + wire spr_match_mas73_64b_0_q; + wire spr_match_mas81_64b_0; + wire spr_match_mas81_64b_0_q; +`ifdef MM_THREADS2 + wire spr_match_mas0_1; + wire spr_match_mas0_1_q; + wire spr_match_mas1_1; + wire spr_match_mas1_1_q; + wire spr_match_mas2_1; + wire spr_match_mas2_1_q; + wire spr_match_mas2u_1; + wire spr_match_mas2u_1_q; + wire spr_match_mas3_1; + wire spr_match_mas3_1_q; + wire spr_match_mas4_1; + wire spr_match_mas4_1_q; + wire spr_match_mas5_1; + wire spr_match_mas5_1_q; + wire spr_match_mas6_1; + wire spr_match_mas6_1_q; + wire spr_match_mas7_1; + wire spr_match_mas7_1_q; + wire spr_match_mas8_1; + wire spr_match_mas8_1_q; + wire spr_match_mas01_64b_1; + wire spr_match_mas01_64b_1_q; + wire spr_match_mas56_64b_1; + wire spr_match_mas56_64b_1_q; + wire spr_match_mas73_64b_1; + wire spr_match_mas73_64b_1_q; + wire spr_match_mas81_64b_1; + wire spr_match_mas81_64b_1_q; +`endif + wire [64-`SPR_DATA_WIDTH:63] spr_mas_data_out; + wire [64-`SPR_DATA_WIDTH:63] spr_mas_data_out_q; + wire spr_match_any_mas; + wire spr_match_any_mas_q; + wire spr_match_mas2_64b; + wire spr_match_mas01_64b; + wire spr_match_mas56_64b; + wire spr_match_mas73_64b; + wire spr_match_mas81_64b; + wire spr_match_64b; + wire spr_match_64b_q; + // added input latches for timing with adding numerous mas regs + wire [0:`SPR_CTL_WIDTH-1] spr_ctl_in_d; + wire [0:`SPR_CTL_WIDTH-1] spr_ctl_in_q; + wire [0:`SPR_ETID_WIDTH-1] spr_etid_in_d; + wire [0:`SPR_ETID_WIDTH-1] spr_etid_in_q; + wire [0:`SPR_ADDR_WIDTH-1] spr_addr_in_d; + wire [0:`SPR_ADDR_WIDTH-1] spr_addr_in_q; + wire [64-`SPR_DATA_WIDTH:63] spr_data_in_d; + wire [64-`SPR_DATA_WIDTH:63] spr_data_in_q; + wire [0:`SPR_ADDR_WIDTH-1] spr_addr_in_clone_d; + wire [0:`SPR_ADDR_WIDTH-1] spr_addr_in_clone_q; + wire [0:`SPR_CTL_WIDTH-1] spr_ctl_int_d; + wire [0:`SPR_CTL_WIDTH-1] spr_ctl_int_q; + wire [0:`SPR_ETID_WIDTH-1] spr_etid_int_d; + wire [0:`SPR_ETID_WIDTH-1] spr_etid_int_q; + wire [0:`SPR_ADDR_WIDTH-1] spr_addr_int_d; + wire [0:`SPR_ADDR_WIDTH-1] spr_addr_int_q; + wire [64-`SPR_DATA_WIDTH:63] spr_data_int_d; + wire [64-`SPR_DATA_WIDTH:63] spr_data_int_q; + wire [0:`SPR_CTL_WIDTH-1] spr_ctl_out_d; + wire [0:`SPR_CTL_WIDTH-1] spr_ctl_out_q; + wire [0:`SPR_ETID_WIDTH-1] spr_etid_out_d; + wire [0:`SPR_ETID_WIDTH-1] spr_etid_out_q; + wire [0:`SPR_ADDR_WIDTH-1] spr_addr_out_d; + wire [0:`SPR_ADDR_WIDTH-1] spr_addr_out_q; + wire [64-`SPR_DATA_WIDTH:63] spr_data_out_d; + wire [64-`SPR_DATA_WIDTH:63] spr_data_out_q; + wire [0:3] spr_etid_onehot; + wire [0:3] spr_etid_in_onehot; + wire [0:3] spr_etid_int_onehot; + wire [0:3] spr_etid_flushed; + wire [0:3] spr_etid_in_flushed; + wire [0:3] spr_etid_int_flushed; + wire spr_val_flushed; + wire spr_val_in_flushed; + wire spr_val_int_flushed; + wire [0:`PID_WIDTH-1] pid0_d; + wire [0:`PID_WIDTH-1] pid0_q; + wire [0:`MMUCR0_WIDTH-1] mmucr0_0_d; + wire [0:`MMUCR0_WIDTH-1] mmucr0_0_q; + wire [64-`MMUCR3_WIDTH:63] mmucr3_0_d; + wire [64-`MMUCR3_WIDTH:63] mmucr3_0_q; + wire [0:3] tstmode4k_0_d, tstmode4k_0_q; +`ifdef MM_THREADS2 + wire [0:`PID_WIDTH-1] pid1_d; + wire [0:`PID_WIDTH-1] pid1_q; + wire [0:`MMUCR0_WIDTH-1] mmucr0_1_d; + wire [0:`MMUCR0_WIDTH-1] mmucr0_1_q; + wire [64-`MMUCR3_WIDTH:63] mmucr3_1_d; + wire [64-`MMUCR3_WIDTH:63] mmucr3_1_q; + wire [0:3] tstmode4k_1_d, tstmode4k_1_q; +`endif + wire [0:`MMUCR1_WIDTH-1] mmucr1_d; + wire [0:`MMUCR1_WIDTH-1] mmucr1_q; + wire [0:`MMUCR2_WIDTH-1] mmucr2_d; + wire [0:`MMUCR2_WIDTH-1] mmucr2_q; + wire [0:`LPID_WIDTH-1] lpidr_d; + wire [0:`LPID_WIDTH-1] lpidr_q; + wire [32:32+`MESR1_WIDTH-1] mesr1_d; + wire [32:32+`MESR1_WIDTH-1] mesr1_q; + wire [32:32+`MESR2_WIDTH-1] mesr2_d; + wire [32:32+`MESR2_WIDTH-1] mesr2_q; + wire mas0_0_atsel_d; + wire mas0_0_atsel_q; + wire [0:2] mas0_0_esel_d; + wire [0:2] mas0_0_esel_q; + wire mas0_0_hes_d; + wire mas0_0_hes_q; + wire [0:1] mas0_0_wq_d; + wire [0:1] mas0_0_wq_q; + wire mas1_0_v_d; + wire mas1_0_v_q; + wire mas1_0_iprot_d; + wire mas1_0_iprot_q; + wire [0:`PID_WIDTH-1] mas1_0_tid_d; + wire [0:`PID_WIDTH-1] mas1_0_tid_q; + wire mas1_0_ind_d; + wire mas1_0_ind_q; + wire mas1_0_ts_d; + wire mas1_0_ts_q; + wire [0:3] mas1_0_tsize_d; + wire [0:3] mas1_0_tsize_q; + wire [64-`SPR_DATA_WIDTH:51] mas2_0_epn_d; + wire [64-`SPR_DATA_WIDTH:51] mas2_0_epn_q; + wire [0:4] mas2_0_wimge_d; + wire [0:4] mas2_0_wimge_q; + wire [32:52] mas3_0_rpnl_d; + wire [32:52] mas3_0_rpnl_q; + wire [0:3] mas3_0_ubits_d; + wire [0:3] mas3_0_ubits_q; + wire [0:5] mas3_0_usxwr_d; + wire [0:5] mas3_0_usxwr_q; + wire mas4_0_indd_d; + wire mas4_0_indd_q; + wire [0:3] mas4_0_tsized_d; + wire [0:3] mas4_0_tsized_q; + wire [0:4] mas4_0_wimged_d; + wire [0:4] mas4_0_wimged_q; + wire mas5_0_sgs_d; + wire mas5_0_sgs_q; + wire [0:7] mas5_0_slpid_d; + wire [0:7] mas5_0_slpid_q; + wire [0:13] mas6_0_spid_d; + wire [0:13] mas6_0_spid_q; + wire [0:3] mas6_0_isize_d; + wire [0:3] mas6_0_isize_q; + wire mas6_0_sind_d; + wire mas6_0_sind_q; + wire mas6_0_sas_d; + wire mas6_0_sas_q; + wire [22:31] mas7_0_rpnu_d; + wire [22:31] mas7_0_rpnu_q; + wire mas8_0_tgs_d; + wire mas8_0_tgs_q; + wire mas8_0_vf_d; + wire mas8_0_vf_q; + wire [0:7] mas8_0_tlpid_d; + wire [0:7] mas8_0_tlpid_q; +`ifdef MM_THREADS2 + wire mas0_1_atsel_d; + wire mas0_1_atsel_q; + wire [0:2] mas0_1_esel_d; + wire [0:2] mas0_1_esel_q; + wire mas0_1_hes_d; + wire mas0_1_hes_q; + wire [0:1] mas0_1_wq_d; + wire [0:1] mas0_1_wq_q; + wire mas1_1_v_d; + wire mas1_1_v_q; + wire mas1_1_iprot_d; + wire mas1_1_iprot_q; + wire [0:`PID_WIDTH-1] mas1_1_tid_d; + wire [0:`PID_WIDTH-1] mas1_1_tid_q; + wire mas1_1_ind_d; + wire mas1_1_ind_q; + wire mas1_1_ts_d; + wire mas1_1_ts_q; + wire [0:3] mas1_1_tsize_d; + wire [0:3] mas1_1_tsize_q; + wire [64-`SPR_DATA_WIDTH:51] mas2_1_epn_d; + wire [64-`SPR_DATA_WIDTH:51] mas2_1_epn_q; + wire [0:4] mas2_1_wimge_d; + wire [0:4] mas2_1_wimge_q; + wire [32:52] mas3_1_rpnl_d; + wire [32:52] mas3_1_rpnl_q; + wire [0:3] mas3_1_ubits_d; + wire [0:3] mas3_1_ubits_q; + wire [0:5] mas3_1_usxwr_d; + wire [0:5] mas3_1_usxwr_q; + wire mas4_1_indd_d; + wire mas4_1_indd_q; + wire [0:3] mas4_1_tsized_d; + wire [0:3] mas4_1_tsized_q; + wire [0:4] mas4_1_wimged_d; + wire [0:4] mas4_1_wimged_q; + wire mas5_1_sgs_d; + wire mas5_1_sgs_q; + wire [0:7] mas5_1_slpid_d; + wire [0:7] mas5_1_slpid_q; + wire [0:13] mas6_1_spid_d; + wire [0:13] mas6_1_spid_q; + wire [0:3] mas6_1_isize_d; + wire [0:3] mas6_1_isize_q; + wire mas6_1_sind_d; + wire mas6_1_sind_q; + wire mas6_1_sas_d; + wire mas6_1_sas_q; + wire [22:31] mas7_1_rpnu_d; + wire [22:31] mas7_1_rpnu_q; + wire mas8_1_tgs_d; + wire mas8_1_tgs_q; + wire mas8_1_vf_d; + wire mas8_1_vf_q; + wire [0:7] mas8_1_tlpid_d; + wire [0:7] mas8_1_tlpid_q; +`endif + + wire mmucsr0_tlb0fi_d; + wire mmucsr0_tlb0fi_q; + wire [64-`REAL_ADDR_WIDTH:51] lper_0_alpn_d; + wire [64-`REAL_ADDR_WIDTH:51] lper_0_alpn_q; + wire [60:63] lper_0_lps_d; + wire [60:63] lper_0_lps_q; +`ifdef MM_THREADS2 + wire [64-`REAL_ADDR_WIDTH:51] lper_1_alpn_d; + wire [64-`REAL_ADDR_WIDTH:51] lper_1_alpn_q; + wire [60:63] lper_1_lps_d; + wire [60:63] lper_1_lps_q; +`endif + // timing nsl's + wire [0:17] iu_mm_ierat_mmucr0_q; + wire [0:`MM_THREADS-1] iu_mm_ierat_mmucr0_we_q; + wire [0:17] xu_mm_derat_mmucr0_q; + wire [0:`MM_THREADS-1] xu_mm_derat_mmucr0_we_q; + wire [0:3] iu_mm_ierat_mmucr1_q; + wire [0:`MM_THREADS-1] iu_mm_ierat_mmucr1_we_d, iu_mm_ierat_mmucr1_we_q; + wire [0:4] xu_mm_derat_mmucr1_q; + wire [0:`MM_THREADS-1] xu_mm_derat_mmucr1_we_d, xu_mm_derat_mmucr1_we_q; + + wire [0:`MM_THREADS-1] tlb_mas_dtlb_error_upd; + wire [0:`MM_THREADS-1] tlb_mas_itlb_error_upd; + wire [0:`MM_THREADS-1] tlb_lper_we_upd; + wire [0:`MM_THREADS-1] tlb_mmucr1_we_upd; + wire [0:`MM_THREADS-1] iu_mm_ierat_mmucr1_we_upd; + wire [0:`MM_THREADS-1] xu_mm_derat_mmucr1_we_upd; + wire tlb_mas1_0_ts_error_upd; + wire [0:`PID_WIDTH-1] tlb_mas1_0_tid_error_upd; + wire [0:`EPN_WIDTH-1] tlb_mas2_0_epn_error_upd; + wire [64-`REAL_ADDR_WIDTH:51] tlb_lper_0_lpn_upd; + wire [60:63] tlb_lper_0_lps_upd; + wire [0:8] tlb_mmucr1_0_een_upd; + wire [0:3] ierat_mmucr1_0_een_upd; + wire [0:4] derat_mmucr1_0_een_upd; +`ifdef MM_THREADS2 + wire tlb_mas1_1_ts_error_upd; + wire [0:`PID_WIDTH-1] tlb_mas1_1_tid_error_upd; + wire [0:`EPN_WIDTH-1] tlb_mas2_1_epn_error_upd; + wire [64-`REAL_ADDR_WIDTH:51] tlb_lper_1_lpn_upd; + wire [60:63] tlb_lper_1_lps_upd; + wire [0:8] tlb_mmucr1_1_een_upd; + wire [0:3] ierat_mmucr1_1_een_upd; + wire [0:4] derat_mmucr1_1_een_upd; +`endif + +`ifdef WAIT_UPDATES + wire [0:5] cp_mm_except_taken_t0_d, cp_mm_except_taken_t0_q; + wire [0:`MM_THREADS-1] tlb_mas_dtlb_error_pending_d, tlb_mas_dtlb_error_pending_q; + wire [0:`MM_THREADS-1] tlb_mas_itlb_error_pending_d, tlb_mas_itlb_error_pending_q; + wire [0:`MM_THREADS-1] tlb_lper_we_pending_d, tlb_lper_we_pending_q; + wire [0:`MM_THREADS-1] tlb_mmucr1_we_pending_d, tlb_mmucr1_we_pending_q; + wire [0:`MM_THREADS-1] ierat_mmucr1_we_pending_d, ierat_mmucr1_we_pending_q; + wire [0:`MM_THREADS-1] derat_mmucr1_we_pending_d, derat_mmucr1_we_pending_q; + + wire tlb_mas1_0_ts_error_d, tlb_mas1_0_ts_error_q; + wire [0:`PID_WIDTH-1] tlb_mas1_0_tid_error_d, tlb_mas1_0_tid_error_q; + wire [0:`EPN_WIDTH-1] tlb_mas2_0_epn_error_d, tlb_mas2_0_epn_error_q; + wire [64-`REAL_ADDR_WIDTH:51] tlb_lper_0_lpn_d, tlb_lper_0_lpn_q; + wire [60:63] tlb_lper_0_lps_d, tlb_lper_0_lps_q; + wire [0:8] tlb_mmucr1_0_een_d, tlb_mmucr1_0_een_q; + wire [0:3] ierat_mmucr1_0_een_d, ierat_mmucr1_0_een_q; + wire [0:4] derat_mmucr1_0_een_d, derat_mmucr1_0_een_q; +`ifdef MM_THREADS2 + wire [0:5] cp_mm_except_taken_t1_d, cp_mm_except_taken_t1_q; + wire tlb_mas1_1_ts_error_d, tlb_mas1_1_ts_error_q; + wire [0:`PID_WIDTH-1] tlb_mas1_1_tid_error_d, tlb_mas1_1_tid_error_q; + wire [0:`EPN_WIDTH-1] tlb_mas2_1_epn_error_d, tlb_mas2_1_epn_error_q; + wire [64-`REAL_ADDR_WIDTH:51] tlb_lper_1_lpn_d, tlb_lper_1_lpn_q; + wire [60:63] tlb_lper_1_lps_d, tlb_lper_1_lps_q; + wire [0:8] tlb_mmucr1_1_een_d, tlb_mmucr1_1_een_q; + wire [0:3] ierat_mmucr1_1_een_d, ierat_mmucr1_1_een_q; + wire [0:4] derat_mmucr1_1_een_d, derat_mmucr1_1_een_q; +`endif +`endif + + wire [0:31] spare_a_q; + wire [0:63] spare_b_q; + + (* analysis_not_referenced="true" *) + wire [0:13] unused_dc; + (* analysis_not_referenced="true" *) + wire [`THREADS:3] unused_dc_threads; + wire [0:45+(4*`MM_THREADS)-1] tri_regk_unused_scan; + + // Pervasive + wire pc_sg_1; + wire pc_sg_0; + wire pc_fce_1; + wire pc_fce_0; + wire pc_func_sl_thold_1; + wire pc_func_sl_thold_0; + wire pc_func_sl_thold_0_b; + wire pc_func_slp_sl_thold_1; + wire pc_func_slp_sl_thold_0; + wire pc_func_slp_sl_thold_0_b; + wire pc_func_sl_force; + wire pc_func_slp_sl_force; + wire pc_cfg_sl_thold_1; + wire pc_cfg_sl_thold_0; + wire pc_cfg_slp_sl_force; + wire pc_cfg_slp_sl_thold_1; + wire pc_cfg_slp_sl_thold_0; + wire pc_cfg_slp_sl_thold_0_b; + wire pc_func_slp_nsl_thold_1; + wire pc_func_slp_nsl_thold_0; + wire pc_func_slp_nsl_thold_0_b; + wire pc_func_slp_nsl_force; + + //signal reset_alias : std_ulogic; + wire [0:scan_right_0] siv_0; + wire [0:scan_right_0] sov_0; + wire [0:scan_right_1] siv_1; + wire [0:scan_right_1] sov_1; + wire [0:boot_scan_right] bsiv; + wire [0:boot_scan_right] bsov; + wire [47:48] mmucfg_q; + wire [45:47] tlb0cfg_q; + wire [0:15] bcfg_spare_q; + + wire pc_cfg_sl_thold_0_b; + wire pc_cfg_sl_force; + wire lcb_dclk; + wire [0:`NCLK_WIDTH-1] lcb_lclk; + wire [47:48] mmucfg_q_b; + wire [45:47] tlb0cfg_q_b; + wire [0:15] bcfg_spare_q_b; + + wire [0:`MM_THREADS-1] cat_emf_act_d; + wire [0:`MM_THREADS-1] cat_emf_act_q; + wire [0:`MM_THREADS] spr_mmu_act_d; + wire [0:`MM_THREADS] spr_mmu_act_q; + wire [0:3] spr_val_act_d; + wire [0:3] spr_val_act_q; + wire spr_val_act; + wire spr_match_act; + wire spr_match_mas_act; + wire spr_mas_data_out_act; + wire [0:`MM_THREADS-1] mas_update_pending_act; + + wire [0:3] cswitch_q; + wire [0:`MM_THREADS-1] cp_flush_d, cp_flush_q; + wire [0:`MM_THREADS-1] cp_flush_p1_d, cp_flush_p1_q; + + // array of 2 bit bin values + wire [0:1] bin_2bit [0:3]; + wire tidn; + wire tiup; + + //## figtree_source: mmq_spr.fig; + //!! Bugspray Include: mmq_spr; + + assign tidn = 1'b0; + assign tiup = 1'b1; + assign bin_2bit[0] = 2'b00; + assign bin_2bit[1] = 2'b01; + assign bin_2bit[2] = 2'b10; + assign bin_2bit[3] = 2'b11; + + genvar i; + generate + for (i=0; i<`MM_THREADS; i=i+1) + begin : genacts + assign cat_emf_act_d[i] = (spr_match_any_mmu & (spr_etid_in_q == bin_2bit[i])) | mmucr2_act_override[6] | (tlb_delayed_act[29+i] & xu_mm_ccr2_notlb_b); + assign spr_mmu_act_d[i] = (spr_match_any_mmu & (spr_etid_in_q == bin_2bit[i])) | mmucr2_act_override[5]; + end + endgenerate + + assign spr_mmu_act_d[`MM_THREADS] = spr_match_any_mmu | mmucr2_act_override[5]; + assign spr_val_act_d[0] = xu_mm_slowspr_val; + assign spr_val_act_d[1] = spr_val_act_q[0]; + assign spr_val_act_d[2] = spr_val_act_q[1]; + assign spr_val_act_d[3] = spr_val_act_q[2]; + assign spr_val_act = spr_val_act_q[0] | spr_val_act_q[1] | spr_val_act_q[2] | spr_val_act_q[3] | mmucr2_act_override[5]; + assign spr_match_act = spr_val_act_q[0] | spr_val_act_q[1] | mmucr2_act_override[5]; + assign spr_match_mas_act = spr_val_act_q[0] | spr_val_act_q[1] | mmucr2_act_override[6]; + assign spr_mas_data_out_act = spr_val_act_q[0] | mmucr2_act_override[6]; +`ifdef WAIT_UPDATES + assign mas_update_pending_act = cat_emf_act_q | tlb_mas_dtlb_error_pending_q | tlb_mas_itlb_error_pending_q | tlb_lper_we_pending_q | + tlb_mmucr1_we_pending_q | ierat_mmucr1_we_pending_q | derat_mmucr1_we_pending_q; +`else + assign mas_update_pending_act = cat_emf_act_q; +`endif + + + //--------------------------------------------------------------------- + // slow spr logic + //--------------------------------------------------------------------- + // input latches for spr access + assign spr_etid_onehot[0] = (xu_mm_slowspr_etid == 2'b00); + assign spr_etid_onehot[1] = (xu_mm_slowspr_etid == 2'b01); + assign spr_etid_onehot[2] = (xu_mm_slowspr_etid == 2'b10); + assign spr_etid_onehot[3] = (xu_mm_slowspr_etid == 2'b11); + assign spr_etid_in_onehot[0] = (spr_etid_in_q == 2'b00); + assign spr_etid_in_onehot[1] = (spr_etid_in_q == 2'b01); + assign spr_etid_in_onehot[2] = (spr_etid_in_q == 2'b10); + assign spr_etid_in_onehot[3] = (spr_etid_in_q == 2'b11); + assign spr_etid_int_onehot[0] = (spr_etid_int_q == 2'b00); + assign spr_etid_int_onehot[1] = (spr_etid_int_q == 2'b01); + assign spr_etid_int_onehot[2] = (spr_etid_int_q == 2'b10); + assign spr_etid_int_onehot[3] = (spr_etid_int_q == 2'b11); + + generate + begin : etid_generate + genvar tid; + for (tid = 0; tid <= 3; tid = tid + 1) + begin : mmqsprflush + if (tid < `THREADS) + begin : mmqsprtidExist + assign spr_etid_flushed[tid] = cp_flush_q[tid] & spr_etid_onehot[tid]; + assign spr_etid_in_flushed[tid] = cp_flush_q[tid] & spr_etid_in_onehot[tid]; + assign spr_etid_int_flushed[tid] = cp_flush_q[tid] & spr_etid_int_onehot[tid]; + end + if (tid >= `THREADS) + begin : mmqsprtidNExist + assign spr_etid_flushed[tid] = 1'b0; + assign spr_etid_in_flushed[tid] = 1'b0; + assign spr_etid_int_flushed[tid] = 1'b0; + assign unused_dc_threads[tid] = spr_etid_onehot[tid] | spr_etid_in_onehot[tid] | spr_etid_int_onehot[tid]; + end + end + end + endgenerate + +`ifdef WAIT_UPDATES + generate + begin : mmq_spr_tid_generate + genvar tid; + for (tid = 0; tid <= `MM_THREADS-1; tid = tid + 1) + begin : mmThreads + if (tid < `THREADS) + begin : tidExist + assign cp_flush_d[tid] = cp_flush[tid]; + end + if (tid >= `THREADS) + begin : tidNExist + assign cp_flush_d[tid] = tidn; + end + end + end + endgenerate +`endif + +assign iu_mm_ierat_mmucr1_we_d = iu_mm_ierat_mmucr1_we; +assign xu_mm_derat_mmucr1_we_d = xu_mm_derat_mmucr1_we; + + // delay because cp_mm_except_taken bus lags cp_flush from completion by 1 cyc + assign cp_flush_p1_d = cp_flush_q; + assign cp_flush_p1 = cp_flush_p1_q; + + //masthdNExist : if `THDID_WIDTH > (`MM_THREADS) generate begin + // masthdunused : for tid in (`MM_THREADS) to (`THDID_WIDTH-1) generate begin + // unused_dc_thdid(tid) <= lrat_mas_thdid(tid) or tlb_lper_we_upd(tid) or tlb_delayed_act(tid+29); + // end generate masthdunused; + //end generate masthdNExist; + assign spr_val_flushed = |(spr_etid_flushed); + assign spr_val_in_flushed = |(spr_etid_in_flushed); + assign spr_val_int_flushed = |(spr_etid_int_flushed); + assign spr_ctl_in_d[0] = xu_mm_slowspr_val & (~(spr_val_flushed)); + assign spr_ctl_in_d[1] = xu_mm_slowspr_rw; + assign spr_ctl_in_d[2] = xu_mm_slowspr_done; + assign spr_etid_in_d = xu_mm_slowspr_etid; + assign spr_addr_in_d = xu_mm_slowspr_addr; + assign spr_addr_in_clone_d = xu_mm_slowspr_addr; + assign spr_data_in_d = xu_mm_slowspr_data; + // internal select latches for spr access + assign spr_ctl_int_d[0] = spr_ctl_in_q[0] & (~(spr_val_in_flushed)); + assign spr_ctl_int_d[1:2] = spr_ctl_in_q[1:2]; + assign spr_etid_int_d = spr_etid_in_q; + assign spr_addr_int_d = spr_addr_in_q; + assign spr_data_int_d = spr_data_in_q; + + assign spr_match_any_mmu = ( spr_ctl_in_q[0] & + ((spr_addr_in_q == Spr_Addr_PID) | + (spr_addr_in_q == Spr_Addr_MMUCR0) | (spr_addr_in_q == Spr_Addr_MMUCR1) | (spr_addr_in_q == Spr_Addr_MMUCR2) | (spr_addr_in_q == Spr_Addr_MMUCR3) | + (spr_addr_in_q == Spr_Addr_LPID) | + (spr_addr_in_q == Spr_Addr_MESR1) | (spr_addr_in_q == Spr_Addr_MESR2) | + (spr_addr_in_clone_q == Spr_Addr_MAS0) | (spr_addr_in_clone_q == Spr_Addr_MAS1) | + (spr_addr_in_clone_q == Spr_Addr_MAS2) | (spr_addr_in_clone_q == Spr_Addr_MAS3) | + (spr_addr_in_clone_q == Spr_Addr_MAS4) | (spr_addr_in_clone_q == Spr_Addr_MAS5) | + (spr_addr_in_clone_q == Spr_Addr_MAS6) | (spr_addr_in_clone_q == Spr_Addr_MAS7) | + (spr_addr_in_clone_q == Spr_Addr_MAS8) | (spr_addr_in_clone_q == Spr_Addr_MAS2U) | + (spr_addr_in_clone_q == Spr_Addr_MAS01_64b) | (spr_addr_in_clone_q == Spr_Addr_MAS56_64b) | + (spr_addr_in_clone_q == Spr_Addr_MAS73_64b) | (spr_addr_in_clone_q == Spr_Addr_MAS81_64b) | + (spr_addr_in_clone_q == Spr_Addr_MMUCFG) | (spr_addr_in_clone_q == Spr_Addr_MMUCSR0) | + (spr_addr_in_clone_q == Spr_Addr_TLB0CFG) | (spr_addr_in_clone_q == Spr_Addr_TLB0PS) | + (spr_addr_in_clone_q == Spr_Addr_LRATCFG) | (spr_addr_in_clone_q == Spr_Addr_LRATPS) | + (spr_addr_in_clone_q == Spr_Addr_EPTCFG) | (spr_addr_in_clone_q == Spr_Addr_LPER) | + (spr_addr_in_clone_q == Spr_Addr_LPERU)) ); + + assign spr_match_pid0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_q == Spr_Addr_PID)); + assign spr_match_mmucr0_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_q == Spr_Addr_MMUCR0)); + assign spr_match_mmucr3_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_q == Spr_Addr_MMUCR3)); +`ifdef MM_THREADS2 + assign spr_match_pid1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_q == Spr_Addr_PID)); + assign spr_match_mmucr0_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_q == Spr_Addr_MMUCR0)); + assign spr_match_mmucr3_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_q == Spr_Addr_MMUCR3)); +`endif + assign spr_match_mmucr1 = (spr_ctl_in_q[0] & (spr_addr_in_q == Spr_Addr_MMUCR1)); + assign spr_match_mmucr2 = (spr_ctl_in_q[0] & (spr_addr_in_q == Spr_Addr_MMUCR2)); + assign spr_match_lpidr = (spr_ctl_in_q[0] & (spr_addr_in_q == Spr_Addr_LPID)); + assign spr_match_mesr1 = (spr_ctl_in_q[0] & (spr_addr_in_q == Spr_Addr_MESR1)); + assign spr_match_mesr2 = (spr_ctl_in_q[0] & (spr_addr_in_q == Spr_Addr_MESR2)); + assign spr_match_mmucsr0 = (spr_ctl_in_q[0] & (spr_addr_in_clone_q == Spr_Addr_MMUCSR0)); + assign spr_match_mmucfg = (spr_ctl_in_q[0] & (spr_addr_in_clone_q == Spr_Addr_MMUCFG)); + assign spr_match_tlb0cfg = (spr_ctl_in_q[0] & (spr_addr_in_clone_q == Spr_Addr_TLB0CFG)); + assign spr_match_tlb0ps = (spr_ctl_in_q[0] & (spr_addr_in_clone_q == Spr_Addr_TLB0PS)); + assign spr_match_lratcfg = (spr_ctl_in_q[0] & (spr_addr_in_clone_q == Spr_Addr_LRATCFG)); + assign spr_match_lratps = (spr_ctl_in_q[0] & (spr_addr_in_clone_q == Spr_Addr_LRATPS)); + assign spr_match_eptcfg = (spr_ctl_in_q[0] & (spr_addr_in_clone_q == Spr_Addr_EPTCFG)); + assign spr_match_lper_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_clone_q == Spr_Addr_LPER)); + assign spr_match_lperu_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_clone_q == Spr_Addr_LPERU)); +`ifdef MM_THREADS2 + assign spr_match_lper_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_clone_q == Spr_Addr_LPER)); + assign spr_match_lperu_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_clone_q == Spr_Addr_LPERU)); +`endif + assign spr_match_any_mas = (spr_ctl_in_q[0] & ((spr_addr_in_clone_q == Spr_Addr_MAS0) | (spr_addr_in_clone_q == Spr_Addr_MAS1) | (spr_addr_in_clone_q == Spr_Addr_MAS2) | (spr_addr_in_clone_q == Spr_Addr_MAS2U) | (spr_addr_in_clone_q == Spr_Addr_MAS3) | (spr_addr_in_clone_q == Spr_Addr_MAS4) | (spr_addr_in_clone_q == Spr_Addr_MAS5) | (spr_addr_in_clone_q == Spr_Addr_MAS6) | (spr_addr_in_clone_q == Spr_Addr_MAS7) | (spr_addr_in_clone_q == Spr_Addr_MAS8) | (spr_addr_in_clone_q == Spr_Addr_MAS01_64b) | (spr_addr_in_clone_q == Spr_Addr_MAS56_64b) | (spr_addr_in_clone_q == Spr_Addr_MAS73_64b) | (spr_addr_in_clone_q == Spr_Addr_MAS81_64b))); + assign spr_match_mas0_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_clone_q == Spr_Addr_MAS0)); + assign spr_match_mas1_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_clone_q == Spr_Addr_MAS1)); + assign spr_match_mas2_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_clone_q == Spr_Addr_MAS2)); + assign spr_match_mas2u_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_clone_q == Spr_Addr_MAS2U)); + assign spr_match_mas3_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_clone_q == Spr_Addr_MAS3)); + assign spr_match_mas4_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_clone_q == Spr_Addr_MAS4)); + assign spr_match_mas5_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_clone_q == Spr_Addr_MAS5)); + assign spr_match_mas6_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_clone_q == Spr_Addr_MAS6)); + assign spr_match_mas7_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_clone_q == Spr_Addr_MAS7)); + assign spr_match_mas8_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_clone_q == Spr_Addr_MAS8)); + assign spr_match_mas01_64b_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_clone_q == Spr_Addr_MAS01_64b)); + assign spr_match_mas56_64b_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_clone_q == Spr_Addr_MAS56_64b)); + assign spr_match_mas73_64b_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_clone_q == Spr_Addr_MAS73_64b)); + assign spr_match_mas81_64b_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_clone_q == Spr_Addr_MAS81_64b)); +`ifdef MM_THREADS2 + assign spr_match_mas0_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_clone_q == Spr_Addr_MAS0)); + assign spr_match_mas1_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_clone_q == Spr_Addr_MAS1)); + assign spr_match_mas2_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_clone_q == Spr_Addr_MAS2)); + assign spr_match_mas2u_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_clone_q == Spr_Addr_MAS2U)); + assign spr_match_mas3_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_clone_q == Spr_Addr_MAS3)); + assign spr_match_mas4_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_clone_q == Spr_Addr_MAS4)); + assign spr_match_mas5_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_clone_q == Spr_Addr_MAS5)); + assign spr_match_mas6_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_clone_q == Spr_Addr_MAS6)); + assign spr_match_mas7_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_clone_q == Spr_Addr_MAS7)); + assign spr_match_mas8_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_clone_q == Spr_Addr_MAS8)); + assign spr_match_mas01_64b_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_clone_q == Spr_Addr_MAS01_64b)); + assign spr_match_mas56_64b_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_clone_q == Spr_Addr_MAS56_64b)); + assign spr_match_mas73_64b_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_clone_q == Spr_Addr_MAS73_64b)); + assign spr_match_mas81_64b_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_clone_q == Spr_Addr_MAS81_64b)); +`endif + assign spr_match_mas2_64b = (spr_ctl_in_q[0] & (spr_addr_in_clone_q == Spr_Addr_MAS2)); + assign spr_match_mas01_64b = (spr_ctl_in_q[0] & (spr_addr_in_clone_q == Spr_Addr_MAS01_64b)); + assign spr_match_mas56_64b = (spr_ctl_in_q[0] & (spr_addr_in_clone_q == Spr_Addr_MAS56_64b)); + assign spr_match_mas73_64b = (spr_ctl_in_q[0] & (spr_addr_in_clone_q == Spr_Addr_MAS73_64b)); + assign spr_match_mas81_64b = (spr_ctl_in_q[0] & (spr_addr_in_clone_q == Spr_Addr_MAS81_64b)); + assign spr_match_64b = spr_match_mas2_64b | spr_match_mas01_64b | spr_match_mas56_64b | spr_match_mas73_64b | spr_match_mas81_64b; + + + assign pid0_d = ((spr_match_pid0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[64 - `PID_WIDTH:63] : + pid0_q; +`ifdef MM_THREADS2 + assign pid1_d = ((spr_match_pid1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[64 - `PID_WIDTH:63] : + pid1_q; +`endif + // mmucr0: 0-ExtClass, 1-TID_NZ, 2:3-GS/TS, 4:5-TLBSel, 6:19-TID + assign mmucr0_0_d = ((spr_match_mmucr0_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? {spr_data_int_q[32], |(spr_data_int_q[50:63]), spr_data_int_q[34:37], spr_data_int_q[50:63]} : + (xu_mm_derat_mmucr0_we_q[0] == 1'b1 & mmucr1_q[14:15] == 2'b01) ? {xu_mm_derat_mmucr0_q[0:3], 2'b11, mmucr0_0_q[6:7], xu_mm_derat_mmucr0_q[6:17]} : + (xu_mm_derat_mmucr0_we_q[0] == 1'b1 & mmucr1_q[14:15] == 2'b10) ? {xu_mm_derat_mmucr0_q[0:3], 2'b11, xu_mm_derat_mmucr0_q[4:5], mmucr0_0_q[8:11], xu_mm_derat_mmucr0_q[10:17]} : + (xu_mm_derat_mmucr0_we_q[0] == 1'b1 & mmucr1_q[14:15] == 2'b11) ? {xu_mm_derat_mmucr0_q[0:3], 2'b11, xu_mm_derat_mmucr0_q[4:17]} : + (xu_mm_derat_mmucr0_we_q[0] == 1'b1) ? {xu_mm_derat_mmucr0_q[0:3], 2'b11, mmucr0_0_q[6:11], xu_mm_derat_mmucr0_q[10:17]} : + (iu_mm_ierat_mmucr0_we_q[0] == 1'b1 & mmucr1_q[12:13] == 2'b01) ? {iu_mm_ierat_mmucr0_q[0:3], 2'b11, mmucr0_0_q[6:7], iu_mm_ierat_mmucr0_q[6:17]} : + (iu_mm_ierat_mmucr0_we_q[0] == 1'b1 & mmucr1_q[12:13] == 2'b10) ? {iu_mm_ierat_mmucr0_q[0:3], 2'b11, iu_mm_ierat_mmucr0_q[4:5], mmucr0_0_q[8:11], iu_mm_ierat_mmucr0_q[10:17]} : + (iu_mm_ierat_mmucr0_we_q[0] == 1'b1 & mmucr1_q[12:13] == 2'b11) ? {iu_mm_ierat_mmucr0_q[0:3], 2'b11, iu_mm_ierat_mmucr0_q[4:17]} : + (iu_mm_ierat_mmucr0_we_q[0] == 1'b1) ? {iu_mm_ierat_mmucr0_q[0:3], 2'b10, mmucr0_0_q[6:11], iu_mm_ierat_mmucr0_q[10:17]} : + mmucr0_0_q; +`ifdef MM_THREADS2 + assign mmucr0_1_d = ((spr_match_mmucr0_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? {spr_data_int_q[32], |(spr_data_int_q[50:63]), spr_data_int_q[34:37], spr_data_int_q[50:63]} : + (xu_mm_derat_mmucr0_we_q[1] == 1'b1 & mmucr1_q[14:15] == 2'b01) ? {xu_mm_derat_mmucr0_q[0:3], 2'b11, mmucr0_1_q[6:7], xu_mm_derat_mmucr0_q[6:17]} : + (xu_mm_derat_mmucr0_we_q[1] == 1'b1 & mmucr1_q[14:15] == 2'b10) ? {xu_mm_derat_mmucr0_q[0:3], 2'b11, xu_mm_derat_mmucr0_q[4:5], mmucr0_1_q[8:11], xu_mm_derat_mmucr0_q[10:17]} : + (xu_mm_derat_mmucr0_we_q[1] == 1'b1 & mmucr1_q[14:15] == 2'b11) ? {xu_mm_derat_mmucr0_q[0:3], 2'b11, xu_mm_derat_mmucr0_q[4:17]} : + (xu_mm_derat_mmucr0_we_q[1] == 1'b1) ? {xu_mm_derat_mmucr0_q[0:3], 2'b11, mmucr0_1_q[6:11], xu_mm_derat_mmucr0_q[10:17]} : + (iu_mm_ierat_mmucr0_we_q[1] == 1'b1 & mmucr1_q[12:13] == 2'b01) ? {iu_mm_ierat_mmucr0_q[0:3], 2'b11, mmucr0_1_q[6:7], iu_mm_ierat_mmucr0_q[6:17]} : + (iu_mm_ierat_mmucr0_we_q[1] == 1'b1 & mmucr1_q[12:13] == 2'b10) ? {iu_mm_ierat_mmucr0_q[0:3], 2'b11, iu_mm_ierat_mmucr0_q[4:5], mmucr0_1_q[8:11], iu_mm_ierat_mmucr0_q[10:17]} : + (iu_mm_ierat_mmucr0_we_q[1] == 1'b1 & mmucr1_q[12:13] == 2'b11) ? {iu_mm_ierat_mmucr0_q[0:3], 2'b11, iu_mm_ierat_mmucr0_q[4:17]} : + (iu_mm_ierat_mmucr0_we_q[1] == 1'b1) ? {iu_mm_ierat_mmucr0_q[0:3], 2'b10, mmucr0_1_q[6:11], iu_mm_ierat_mmucr0_q[10:17]} : + mmucr0_1_q; +`endif + + // mmucr1: 0-IRRE, 1-DRRE, 2-REE, 3-CEE, + // 4-Disable any context sync inst from invalidating extclass=0 erat entries, + // 5-Disable isync inst from invalidating extclass=0 erat entries, + // 6:7-IPEI, 8:9-DPEI, 10:11-TPEI, 12:13-ICTID/ITTID, 14:15-DCTID/DTTID, + // 16-DCCD, 17-TLBWE_BINV, 18-TLBI_MSB, 19-TLBI_REJ, + // 20-IERRDET, 21-DERRDET, 22-TERRDET, 23:31-EEN + // 2) mmucr1: merge EEN bits into single field, seperate I/D/T ERRDET bits + // 3) mmucr1: add ICTID, ITTID, DCTID, DTTID, TLBI_REJ, and TLBI_MSB bits + assign mmucr1_d[0:16] = ((spr_match_mmucr1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32:48] : + mmucr1_q[0:16]; + assign mmucr1_d[17] = ((spr_match_mmucr1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? (spr_data_int_q[49] & (~cswitch_q[1])) : + mmucr1_q[17]; + assign mmucr1_d[18:19] = ((spr_match_mmucr1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[50:51] : + mmucr1_q[18:19]; + // added cswitch0 to prevent side effect of clearing on read + assign mmucr1_d[20] = ((spr_match_mmucr1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Read & cswitch_q[0] == 1'b0)) ? 1'b0 : + ((spr_match_mmucr1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write & cswitch_q[0] == 1'b1)) ? spr_data_int_q[52] : + ((|(iu_mm_ierat_mmucr1_we_upd) == 1'b1 & |(xu_mm_derat_mmucr1_we_upd) == 1'b0 & |(tlb_mmucr1_we_upd) == 1'b0 & mmucr1_q[20:22] == 3'b000)) ? 1'b1 : + mmucr1_q[20]; + assign mmucr1_d[21] = ((spr_match_mmucr1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Read & cswitch_q[0] == 1'b0)) ? 1'b0 : + ((spr_match_mmucr1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write & cswitch_q[0] == 1'b1)) ? spr_data_int_q[53] : + ((|(xu_mm_derat_mmucr1_we_upd) == 1'b1 & |(tlb_mmucr1_we_upd) == 1'b0 & mmucr1_q[20:22] == 3'b000)) ? 1'b1 : + mmucr1_q[21]; + assign mmucr1_d[22] = ((spr_match_mmucr1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Read & cswitch_q[0] == 1'b0)) ? 1'b0 : + ((spr_match_mmucr1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write & cswitch_q[0] == 1'b1)) ? spr_data_int_q[54] : + ((|(tlb_mmucr1_we_upd) == 1'b1 & mmucr1_q[20:22] == 3'b000)) ? 1'b1 : + mmucr1_q[22]; + assign mmucr1_d[23:31] = ((spr_match_mmucr1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Read & cswitch_q[0] == 1'b0)) ? {9{1'b0}} : + ((spr_match_mmucr1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write & cswitch_q[0] == 1'b1)) ? spr_data_int_q[55:63] : + ((tlb_mmucr1_we_upd[0] == 1'b1 & mmucr1_q[20:22] == 3'b000)) ? tlb_mmucr1_0_een_upd : +`ifdef MM_THREADS2 + ((tlb_mmucr1_we_upd[1] == 1'b1 & mmucr1_q[20:22] == 3'b000)) ? tlb_mmucr1_1_een_upd : +`endif + ((xu_mm_derat_mmucr1_we_upd[0] == 1'b1 & mmucr1_q[20:22] == 3'b000)) ? {4'b0000, derat_mmucr1_0_een_upd} : +`ifdef MM_THREADS2 + ((xu_mm_derat_mmucr1_we_upd[1] == 1'b1 & mmucr1_q[20:22] == 3'b000)) ? {4'b0000, derat_mmucr1_1_een_upd} : +`endif + ((iu_mm_ierat_mmucr1_we_upd[0] == 1'b1 & mmucr1_q[20:22] == 3'b000)) ? {5'b00000, ierat_mmucr1_0_een_upd} : +`ifdef MM_THREADS2 + ((iu_mm_ierat_mmucr1_we_upd[1] == 1'b1 & mmucr1_q[20:22] == 3'b000)) ? {5'b00000, ierat_mmucr1_1_een_upd} : +`endif + mmucr1_q[23:31]; + + // mmucr2: + assign mmucr2_d[0:31] = ((spr_match_mmucr2_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32:63] : + mmucr2_q[0:31]; + + // mmucr3: + assign mmucr3_0_d = ((spr_match_mmucr3_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? { spr_data_int_q[64 - `MMUCR3_WIDTH:59+`MM_THREADS], {`THDID_WIDTH-`MM_THREADS{1'b0}} } : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? { tlb_mmucr3_x, tlb_mmucr3_rc, tlb_mmucr3_extclass, tlb_mmucr3_class, tlb_mmucr3_wlc, tlb_mmucr3_resvattr, 1'b0, tlb_mmucr3_thdid[0:`MM_THREADS-1], {`THDID_WIDTH-`MM_THREADS{1'b0}} } : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? { lrat_mmucr3_x, 2'b00, 1'b0, 1'b0, 2'b00, 2'b00, 1'b0, 1'b0, {`MM_THREADS{1'b1}}, {`THDID_WIDTH-`MM_THREADS{1'b0}} } : + mmucr3_0_q; + + assign tstmode4k_0_d[0] = ((spr_match_mmucr3_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write & spr_data_int_q[32:47] == TSTMODE4KCONST1 )) ? 1'b1 : + ((spr_match_mmucr3_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write )) ? 1'b0 : + tstmode4k_0_q[0]; + + assign tstmode4k_0_d[1] = ((spr_match_mmucr3_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write & tstmode4k_0_q[0] == 1'b1 & spr_data_int_q[32:43] == TSTMODE4KCONST2 )) ? 1'b1 : + ((spr_match_mmucr3_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write )) ? 1'b0 : + tstmode4k_0_q[1]; + + assign tstmode4k_0_d[2:3] = ((spr_match_mmucr3_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write & tstmode4k_0_q[0] == 1'b1 & spr_data_int_q[32:43] == TSTMODE4KCONST2 )) ? spr_data_int_q[46:47]: + ((spr_match_mmucr3_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write )) ? 2'b00 : + tstmode4k_0_q[2:3]; + + +`ifdef MM_THREADS2 + assign mmucr3_1_d = ((spr_match_mmucr3_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? { spr_data_int_q[64 - `MMUCR3_WIDTH:59+`MM_THREADS], {`THDID_WIDTH-`MM_THREADS{1'b0}} } : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? { tlb_mmucr3_x, tlb_mmucr3_rc, tlb_mmucr3_extclass, tlb_mmucr3_class, tlb_mmucr3_wlc, tlb_mmucr3_resvattr, 1'b0, tlb_mmucr3_thdid[0:`MM_THREADS-1], {`THDID_WIDTH-`MM_THREADS{1'b0}} } : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? { lrat_mmucr3_x, 2'b00, 1'b0, 1'b0, 2'b00, 2'b00, 1'b0, 1'b0, {`MM_THREADS{1'b1}}, {`THDID_WIDTH-`MM_THREADS{1'b0}} } : + mmucr3_1_q; + + assign tstmode4k_1_d[0] = ((spr_match_mmucr3_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write & spr_data_int_q[32:47] == TSTMODE4KCONST1 )) ? 1'b1 : + ((spr_match_mmucr3_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write )) ? 1'b0 : + tstmode4k_1_q[0]; + + assign tstmode4k_1_d[1] = ((spr_match_mmucr3_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write & tstmode4k_1_q[0] == 1'b1 & spr_data_int_q[32:43] == TSTMODE4KCONST2 )) ? 1'b1 : + ((spr_match_mmucr3_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write )) ? 1'b0 : + tstmode4k_1_q[1]; + + assign tstmode4k_1_d[2:3] = ((spr_match_mmucr3_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write & tstmode4k_1_q[0] == 1'b1 & spr_data_int_q[32:43] == TSTMODE4KCONST2 )) ? spr_data_int_q[46:47]: + ((spr_match_mmucr3_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write )) ? 2'b00 : + tstmode4k_1_q[2:3]; + + `endif + + assign lpidr_d = ((spr_match_lpidr_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[64 - `LPID_WIDTH:63] : + lpidr_q; + + // Perf event select registers + // Each field controls selection of 1 of 64 events per event bus bit + // mesr1: 32:37 - MUXSELEB0, + // 38:43 - MUXSELEB1, + // 44:49 - MUXSELEB2, + // 50:55 - MUXSELEB3 + // mesr2: 32:37 - MUXSELEB4, + // 38:43 - MUXSELEB5, + // 44:49 - MUXSELEB6, + // 50:55 - MUXSELEB7 + assign mesr1_d[32:32 + `MESR1_WIDTH - 1] = ((spr_match_mesr1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32:32 + `MESR1_WIDTH - 1] : + mesr1_q[32:32 + `MESR1_WIDTH - 1]; + assign mesr2_d[32:32 + `MESR2_WIDTH - 1] = ((spr_match_mesr2_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32:32 + `MESR2_WIDTH - 1] : + mesr2_q[32:32 + `MESR2_WIDTH - 1]; + + assign mmucsr0_tlb0fi_d = ((mmucsr0_tlb0fi_q == 1'b0 & spr_match_mmucsr0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write & spr_data_int_q[61] == 1'b1)) ? 1'b1 : + (mmq_inval_tlb0fi_done == 1'b1) ? 1'b0 : + mmucsr0_tlb0fi_q; + + +`ifdef WAIT_UPDATES + // cp_mm_except_taken_t0_q + // 0 - val + // 1 - I=0/D=1 + // 2 - TLB miss + // 3 - Storage int (TLBI/PTfault) + // 4 - LRAT miss + // 5 - Mcheck + + assign cp_mm_except_taken_t0_d = cp_mm_except_taken_t0; + + assign tlb_mas_dtlb_error_upd[0] = tlb_mas_dtlb_error_pending_q[0] & cp_mm_except_taken_t0_q[0] & {1{cp_mm_except_taken_t0_q[1:5] == 5'b11000}}; // dtlb miss except taken + assign tlb_mas_itlb_error_upd[0] = tlb_mas_itlb_error_pending_q[0] & cp_mm_except_taken_t0_q[0] & {1{cp_mm_except_taken_t0_q[1:5] == 5'b01000}}; // itlb miss except taken + assign tlb_lper_we_upd[0] = tlb_lper_we_pending_q[0] & cp_mm_except_taken_t0_q[0] & {1{cp_mm_except_taken_t0_q[2:5] == 4'b0010}}; // lrat error except taken + assign tlb_mmucr1_we_upd[0] = tlb_mmucr1_we_pending_q[0] & cp_mm_except_taken_t0_q[0] & {1{cp_mm_except_taken_t0_q[2:5] == 4'b0001}}; // tlb mcheck except taken + assign iu_mm_ierat_mmucr1_we_upd[0] = ierat_mmucr1_we_pending_q[0] & cp_mm_except_taken_t0_q[0] & {1{cp_mm_except_taken_t0_q[2:5] == 4'b0001}}; // ierat mcheck except taken + assign xu_mm_derat_mmucr1_we_upd[0] = derat_mmucr1_we_pending_q[0] & cp_mm_except_taken_t0_q[0] & {1{cp_mm_except_taken_t0_q[2:5] == 4'b0001}}; // derat mcheck except taken + + assign tlb_mas_dtlb_error_pending_d[0] = (tlb_mas_dtlb_error_pending_q[0] == 1'b1 & cp_mm_except_taken_t0_q[0] == 1'b1 & cp_mm_except_taken_t0_q[1:5] == 5'b11000 ) ? 1'b0 : + (tlb_mas_dtlb_error_pending_q[0] == 1'b1 & cp_flush_p1_q[0] == 1'b1) ? 1'b0 : + (tlb_mas_dtlb_error_pending_q[0] == 1'b0 & tlb_mas_dtlb_error == 1'b1 & tlb_mas_thdid[0] == 1'b1) ? 1'b1 : + tlb_mas_dtlb_error_pending_q[0]; + + assign tlb_mas_itlb_error_pending_d[0] = (tlb_mas_itlb_error_pending_q[0] == 1'b1 & cp_mm_except_taken_t0_q[0] == 1'b1 & cp_mm_except_taken_t0_q[1:5] == 5'b01000 ) ? 1'b0 : + (tlb_mas_itlb_error_pending_q[0] == 1'b1 & cp_flush_p1_q[0] == 1'b1) ? 1'b0 : + (tlb_mas_itlb_error_pending_q[0] == 1'b0 & tlb_mas_itlb_error == 1'b1 & tlb_mas_thdid[0] == 1'b1) ? 1'b1 : + tlb_mas_itlb_error_pending_q[0]; + + assign tlb_lper_we_pending_d[0] = (tlb_lper_we_pending_q[0] == 1'b1 & cp_mm_except_taken_t0_q[0] == 1'b1 & cp_mm_except_taken_t0_q[2:5] == 4'b0010 ) ? 1'b0 : + (tlb_lper_we_pending_q[0] == 1'b1 & cp_flush_p1_q[0] == 1'b1) ? 1'b0 : + (tlb_lper_we_pending_q[0] == 1'b0 & tlb_lper_we[0] == 1'b1) ? 1'b1 : + tlb_lper_we_pending_q[0]; + + assign tlb_mmucr1_we_pending_d[0] = (tlb_mmucr1_we_pending_q[0] == 1'b1 & cp_mm_except_taken_t0_q[0] == 1'b1 & cp_mm_except_taken_t0_q[2:5] == 4'b0001 ) ? 1'b0 : + (tlb_mmucr1_we_pending_q[0] == 1'b1 & cp_flush_p1_q[0] == 1'b1) ? 1'b0 : + (tlb_mmucr1_we_pending_q[0] == 1'b0 & tlb_mmucr1_we == 1'b1 & tlb_mas_thdid[0] == 1'b1) ? 1'b1 : + tlb_mmucr1_we_pending_q[0]; + + assign ierat_mmucr1_we_pending_d[0] = (ierat_mmucr1_we_pending_q[0] == 1'b1 & cp_mm_except_taken_t0_q[0] == 1'b1 & cp_mm_except_taken_t0_q[2:5] == 4'b0001 ) ? 1'b0 : + (ierat_mmucr1_we_pending_q[0] == 1'b1 & cp_flush_p1_q[0] == 1'b1) ? 1'b0 : + (ierat_mmucr1_we_pending_q[0] == 1'b0 & iu_mm_ierat_mmucr1_we_q[0] == 1'b1) ? 1'b1 : + ierat_mmucr1_we_pending_q[0]; + + assign derat_mmucr1_we_pending_d[0] = (derat_mmucr1_we_pending_q[0] == 1'b1 & cp_mm_except_taken_t0_q[0] == 1'b1 & cp_mm_except_taken_t0_q[2:5] == 4'b0001 ) ? 1'b0 : + (derat_mmucr1_we_pending_q[0] == 1'b1 & cp_flush_p1_q[0] == 1'b1) ? 1'b0 : + (derat_mmucr1_we_pending_q[0] == 1'b0 & xu_mm_derat_mmucr1_we_q[0] == 1'b1) ? 1'b1 : + derat_mmucr1_we_pending_q[0]; + + + assign tlb_mas1_0_ts_error_d = ((tlb_mas_dtlb_error == 1'b1 | tlb_mas_itlb_error == 1'b1) & tlb_mas_thdid[0] == 1'b1) ? tlb_mas1_ts_error : + tlb_mas1_0_ts_error_q; + assign tlb_mas1_0_tid_error_d = ((tlb_mas_dtlb_error == 1'b1 | tlb_mas_itlb_error == 1'b1) & tlb_mas_thdid[0] == 1'b1) ? tlb_mas1_tid_error : + tlb_mas1_0_tid_error_q; + assign tlb_mas2_0_epn_error_d = ((tlb_mas_dtlb_error == 1'b1 | tlb_mas_itlb_error == 1'b1) & tlb_mas_thdid[0] == 1'b1) ? tlb_mas2_epn_error : + tlb_mas2_0_epn_error_q; + assign tlb_lper_0_lpn_d = (tlb_lper_we[0] == 1'b1) ? tlb_lper_lpn : + tlb_lper_0_lpn_q; + assign tlb_lper_0_lps_d = (tlb_lper_we[0] == 1'b1) ? tlb_lper_lps : + tlb_lper_0_lps_q; + + assign tlb_mmucr1_0_een_d = (tlb_mmucr1_we_pending_q[0] == 1'b0 & tlb_mmucr1_we == 1'b1 & tlb_mas_thdid[0] == 1'b1) ? tlb_mmucr1_een : + tlb_mmucr1_0_een_q; + + assign ierat_mmucr1_0_een_d = (ierat_mmucr1_we_pending_q[0] == 1'b0 & iu_mm_ierat_mmucr1_we_q[0] == 1'b1) ? iu_mm_ierat_mmucr1_q : + ierat_mmucr1_0_een_q; + + assign derat_mmucr1_0_een_d = (derat_mmucr1_we_pending_q[0] == 1'b0 & xu_mm_derat_mmucr1_we_q[0] == 1'b1) ? xu_mm_derat_mmucr1_q : + derat_mmucr1_0_een_q; + + + assign tlb_mas1_0_ts_error_upd = tlb_mas1_0_ts_error_q; + assign tlb_mas1_0_tid_error_upd = tlb_mas1_0_tid_error_q; + assign tlb_mas2_0_epn_error_upd = tlb_mas2_0_epn_error_q; + assign tlb_lper_0_lpn_upd = tlb_lper_0_lpn_q; + assign tlb_lper_0_lps_upd = tlb_lper_0_lps_q; + assign tlb_mmucr1_0_een_upd = tlb_mmucr1_0_een_q; + assign ierat_mmucr1_0_een_upd = ierat_mmucr1_0_een_q; + assign derat_mmucr1_0_een_upd = derat_mmucr1_0_een_q; + +`ifdef MM_THREADS2 + // cp_mm_except_taken_t1_q + // 0 - val + // 1 - I=0/D=1 + // 2 - TLB miss + // 3 - Storage int (TLBI/PTfault) + // 4 - LRAT miss + // 5 - Mcheck + assign cp_mm_except_taken_t1_d = cp_mm_except_taken_t1; + + assign tlb_mas_dtlb_error_upd[1] = tlb_mas_dtlb_error_pending_q[1] & cp_mm_except_taken_t1_q[0] & {1{cp_mm_except_taken_t1_q[1:5] == 5'b11000}}; // dtlb miss except taken + assign tlb_mas_itlb_error_upd[1] = tlb_mas_itlb_error_pending_q[1] & cp_mm_except_taken_t1_q[0] & {1{cp_mm_except_taken_t1_q[1:5] == 5'b01000}}; // itlb miss except taken + assign tlb_lper_we_upd[1] = tlb_lper_we_pending_q[1] & cp_mm_except_taken_t1_q[0] & {1{cp_mm_except_taken_t1_q[2:5] == 4'b0010}}; // lrat error except taken + assign tlb_mmucr1_we_upd[1] = tlb_mmucr1_we_pending_q[1] & cp_mm_except_taken_t1_q[0] & {1{cp_mm_except_taken_t1_q[2:5] == 4'b0001}}; // tlb mcheck except taken + assign iu_mm_ierat_mmucr1_we_upd[1] = ierat_mmucr1_we_pending_q[1] & cp_mm_except_taken_t1_q[0] & {1{cp_mm_except_taken_t1_q[2:5] == 4'b0001}}; // ierat mcheck except taken + assign xu_mm_derat_mmucr1_we_upd[1] = derat_mmucr1_we_pending_q[1] & cp_mm_except_taken_t1_q[0] & {1{cp_mm_except_taken_t1_q[2:5] == 4'b0001}}; // derat mcheck except taken + + assign tlb_mas_dtlb_error_pending_d[1] = (tlb_mas_dtlb_error_pending_q[1] == 1'b1 & cp_mm_except_taken_t1_q[0] == 1'b1 & cp_mm_except_taken_t1_q[1:5] == 5'b11000 ) ? 1'b0 : + (tlb_mas_dtlb_error_pending_q[1] == 1'b1 & cp_flush_p1_q[1] == 1'b1) ? 1'b0 : + (tlb_mas_dtlb_error_pending_q[1] == 1'b0 & tlb_mas_dtlb_error == 1'b1 & tlb_mas_thdid[1] == 1'b1) ? 1'b1 : + tlb_mas_dtlb_error_pending_q[1]; + + assign tlb_mas_itlb_error_pending_d[1] = (tlb_mas_itlb_error_pending_q[1] == 1'b1 & cp_mm_except_taken_t1_q[0] == 1'b1 & cp_mm_except_taken_t1_q[1:5] == 5'b01000 ) ? 1'b0 : + (tlb_mas_itlb_error_pending_q[1] == 1'b1 & cp_flush_p1_q[1] == 1'b1) ? 1'b0 : + (tlb_mas_itlb_error_pending_q[1] == 1'b0 & tlb_mas_itlb_error == 1'b1 & tlb_mas_thdid[1] == 1'b1) ? 1'b1 : + tlb_mas_itlb_error_pending_q[1]; + + assign tlb_lper_we_pending_d[1] = (tlb_lper_we_pending_q[1] == 1'b1 & cp_mm_except_taken_t1_q[0] == 1'b1 & cp_mm_except_taken_t1_q[2:5] == 4'b0010 ) ? 1'b0 : + (tlb_lper_we_pending_q[1] == 1'b1 & cp_flush_p1_q[1] == 1'b1) ? 1'b0 : + (tlb_lper_we_pending_q[1] == 1'b0 & tlb_lper_we[1] == 1'b1) ? 1'b1 : + tlb_lper_we_pending_q[1]; + + assign tlb_mmucr1_we_pending_d[1] = (tlb_mmucr1_we_pending_q[1] == 1'b1 & cp_mm_except_taken_t1_q[0] == 1'b1 & cp_mm_except_taken_t1_q[2:5] == 4'b0001 ) ? 1'b0 : + (tlb_mmucr1_we_pending_q[1] == 1'b1 & cp_flush_p1_q[1] == 1'b1) ? 1'b0 : + (tlb_mmucr1_we_pending_q[1] == 1'b0 & tlb_mmucr1_we == 1'b1 & tlb_mas_thdid[1] == 1'b1) ? 1'b1 : + tlb_mmucr1_we_pending_q[1]; + + assign ierat_mmucr1_we_pending_d[1] = (ierat_mmucr1_we_pending_q[1] == 1'b1 & cp_mm_except_taken_t1_q[0] == 1'b1 & cp_mm_except_taken_t1_q[2:5] == 4'b0001 ) ? 1'b0 : + (ierat_mmucr1_we_pending_q[1] == 1'b1 & cp_flush_p1_q[1] == 1'b1) ? 1'b0 : + (ierat_mmucr1_we_pending_q[1] == 1'b0 & iu_mm_ierat_mmucr1_we_q[1] == 1'b1) ? 1'b1 : + ierat_mmucr1_we_pending_q[1]; + + assign derat_mmucr1_we_pending_d[1] = (derat_mmucr1_we_pending_q[1] == 1'b1 & cp_mm_except_taken_t1_q[1] == 1'b1 & cp_mm_except_taken_t1_q[2:5] == 4'b0001 ) ? 1'b0 : + (derat_mmucr1_we_pending_q[1] == 1'b1 & cp_flush_p1_q[1] == 1'b1) ? 1'b0 : + (derat_mmucr1_we_pending_q[1] == 1'b0 & xu_mm_derat_mmucr1_we_q[1] == 1'b1) ? 1'b1 : + derat_mmucr1_we_pending_q[1]; + + assign tlb_mas1_1_ts_error_d = ((tlb_mas_dtlb_error == 1'b1 | tlb_mas_itlb_error == 1'b1) & tlb_mas_thdid[1] == 1'b1) ? tlb_mas1_ts_error : + tlb_mas1_1_ts_error_q; + assign tlb_mas1_1_tid_error_d = ((tlb_mas_dtlb_error == 1'b1 | tlb_mas_itlb_error == 1'b1) & tlb_mas_thdid[1] == 1'b1) ? tlb_mas1_tid_error : + tlb_mas1_1_tid_error_q; + assign tlb_mas2_1_epn_error_d = ((tlb_mas_dtlb_error == 1'b1 | tlb_mas_itlb_error == 1'b1) & tlb_mas_thdid[1] == 1'b1) ? tlb_mas2_epn_error : + tlb_mas2_1_epn_error_q; + assign tlb_lper_1_lpn_d = (tlb_lper_we[1] == 1'b1) ? tlb_lper_lpn : + tlb_lper_1_lpn_q; + assign tlb_lper_1_lps_d = (tlb_lper_we[1] == 1'b1) ? tlb_lper_lps : + tlb_lper_1_lps_q; + + assign tlb_mmucr1_1_een_d = (tlb_mmucr1_we_pending_q[1] == 1'b0 & tlb_mmucr1_we == 1'b1 & tlb_mas_thdid[1] == 1'b1) ? tlb_mmucr1_een : + tlb_mmucr1_1_een_q; + + assign ierat_mmucr1_1_een_d = (ierat_mmucr1_we_pending_q[1] == 1'b0 & iu_mm_ierat_mmucr1_we_q[1] == 1'b1) ? iu_mm_ierat_mmucr1_q : + ierat_mmucr1_1_een_q; + + assign derat_mmucr1_1_een_d = (derat_mmucr1_we_pending_q[1] == 1'b0 & xu_mm_derat_mmucr1_we_q[1] == 1'b1) ? xu_mm_derat_mmucr1_q : + derat_mmucr1_1_een_q; + + + assign tlb_mas1_1_ts_error_upd = tlb_mas1_1_ts_error_q; + assign tlb_mas1_1_tid_error_upd = tlb_mas1_1_tid_error_q; + assign tlb_mas2_1_epn_error_upd = tlb_mas2_1_epn_error_q; + assign tlb_lper_1_lpn_upd = tlb_lper_1_lpn_q; + assign tlb_lper_1_lps_upd = tlb_lper_1_lps_q; + assign tlb_mmucr1_1_een_upd = tlb_mmucr1_1_een_q; + assign ierat_mmucr1_1_een_upd = ierat_mmucr1_1_een_q; + assign derat_mmucr1_1_een_upd = derat_mmucr1_1_een_q; +`endif +`else + assign tlb_mas_dtlb_error_upd = tlb_mas_thdid & {`MM_THREADS{tlb_mas_dtlb_error}}; + assign tlb_mas_itlb_error_upd = tlb_mas_thdid & {`MM_THREADS{tlb_mas_itlb_error}}; + assign tlb_lper_we_upd = tlb_lper_we; + + assign tlb_mmucr1_we_upd = {`MM_THREADS{tlb_mmucr1_we}} & tlb_mas_thdid[0:`MM_THREADS-1]; + assign iu_mm_ierat_mmucr1_we_upd = iu_mm_ierat_mmucr1_we_q; + assign xu_mm_derat_mmucr1_we_upd = xu_mm_derat_mmucr1_we_q; + + assign tlb_mas1_0_ts_error_upd = tlb_mas1_ts_error; + assign tlb_mas1_0_tid_error_upd = tlb_mas1_tid_error; + assign tlb_mas2_0_epn_error_upd = tlb_mas2_epn_error; + assign tlb_lper_0_lpn_upd = tlb_lper_lpn; + assign tlb_lper_0_lps_upd = tlb_lper_lps; + assign tlb_mmucr1_0_een_upd = tlb_mmucr1_een; + assign ierat_mmucr1_0_een_upd = iu_mm_ierat_mmucr1_q; + assign derat_mmucr1_0_een_upd = xu_mm_derat_mmucr1_q; +`ifdef MM_THREADS2 + assign tlb_mas1_1_ts_error_upd = tlb_mas1_ts_error; + assign tlb_mas1_1_tid_error_upd = tlb_mas1_tid_error; + assign tlb_mas2_1_epn_error_upd = tlb_mas2_epn_error; + assign tlb_lper_1_lpn_upd = tlb_lper_lpn; + assign tlb_lper_1_lps_upd = tlb_lper_lps; + assign tlb_mmucr1_1_een_upd = tlb_mmucr1_een; + assign ierat_mmucr1_1_een_upd = iu_mm_ierat_mmucr1_q; + assign derat_mmucr1_1_een_upd = xu_mm_derat_mmucr1_q; +`endif +`endif + + + assign lper_0_alpn_d[32:51] = ((spr_match_lper_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32:51] : + (tlb_lper_we_upd[0] == 1'b1) ? tlb_lper_0_lpn_upd[32:51] : + lper_0_alpn_q[32:51]; + generate + if (`SPR_DATA_WIDTH == 64) + begin : gen64_lper_0_alpn + assign lper_0_alpn_d[64 - `REAL_ADDR_WIDTH:31] = ((spr_match_lper_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[64 - `REAL_ADDR_WIDTH:31] : + ((spr_match_lperu_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[64 - `REAL_ADDR_WIDTH + 32:63] : + (tlb_lper_we_upd[0] == 1'b1) ? tlb_lper_0_lpn_upd[64 - `REAL_ADDR_WIDTH:31] : + lper_0_alpn_q[64 - `REAL_ADDR_WIDTH:31]; + end + endgenerate + + generate + if (`SPR_DATA_WIDTH == 32) + begin : gen32_lper_0_alpn + assign lper_0_alpn_d[64 - `REAL_ADDR_WIDTH:31] = ((spr_match_lperu_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[64 - `REAL_ADDR_WIDTH + 32:63] : + (tlb_lper_we_upd[0] == 1'b1) ? tlb_lper_0_lpn_upd[64 - `REAL_ADDR_WIDTH:31] : + lper_0_alpn_q[64 - `REAL_ADDR_WIDTH:31]; + end + endgenerate + + assign lper_0_lps_d = ((spr_match_lper_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[60:63] : + (tlb_lper_we_upd[0] == 1'b1) ? tlb_lper_0_lps_upd[60:63] : + lper_0_lps_q; + +`ifdef MM_THREADS2 + assign lper_1_alpn_d[32:51] = ((spr_match_lper_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32:51] : + (tlb_lper_we_upd[1] == 1'b1) ? tlb_lper_1_lpn_upd[32:51] : + lper_1_alpn_q[32:51]; + generate + if (`SPR_DATA_WIDTH == 64) + begin : gen64_lper_1_alpn + assign lper_1_alpn_d[64 - `REAL_ADDR_WIDTH:31] = ((spr_match_lper_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[64 - `REAL_ADDR_WIDTH:31] : + ((spr_match_lperu_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[64 - `REAL_ADDR_WIDTH + 32:63] : + (tlb_lper_we_upd[1] == 1'b1) ? tlb_lper_1_lpn_upd[64 - `REAL_ADDR_WIDTH:31] : + lper_1_alpn_q[64 - `REAL_ADDR_WIDTH:31]; + end + endgenerate + + generate + if (`SPR_DATA_WIDTH == 32) + begin : gen32_lper_1_alpn + assign lper_1_alpn_d[64 - `REAL_ADDR_WIDTH:31] = ((spr_match_lperu_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[64 - `REAL_ADDR_WIDTH + 32:63] : + (tlb_lper_we_upd[1] == 1'b1) ? tlb_lper_1_lpn_upd[64 - `REAL_ADDR_WIDTH:31] : + lper_1_alpn_q[64 - `REAL_ADDR_WIDTH:31]; + end + endgenerate + + assign lper_1_lps_d = ((spr_match_lper_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[60:63] : + (tlb_lper_we_upd[1] == 1'b1) ? tlb_lper_1_lps_upd[60:63] : + lper_1_lps_q; +`endif + + + + assign mas1_0_v_d = (((spr_match_mas1_0_q == 1'b1 | spr_match_mas01_64b_0_q == 1'b1 | spr_match_mas81_64b_0_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32] : + ((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[0] == 1'b1)) ? 1'b0 : + ((tlb_mas_tlbsx_hit == 1'b1 & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1) ? 1'b1 : + ((tlb_mas_tlbre == 1'b1 & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas1_v : + ((lrat_mas_tlbsx_miss == 1'b1 & lrat_mas_thdid[0] == 1'b1)) ? 1'b0 : + ((lrat_mas_tlbsx_hit == 1'b1 & lrat_mas_thdid[0] == 1'b1)) ? 1'b1 : + ((lrat_mas_tlbre == 1'b1 & lrat_mas_thdid[0] == 1'b1)) ? lrat_mas1_v : + mas1_0_v_q; + assign mas1_0_iprot_d = (((spr_match_mas1_0_q == 1'b1 | spr_match_mas01_64b_0_q == 1'b1 | spr_match_mas81_64b_0_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[33] : + ((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1) ? 1'b0 : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas1_iprot : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? 1'b0 : + mas1_0_iprot_q; + assign mas1_0_tid_d = (((spr_match_mas1_0_q == 1'b1 | spr_match_mas01_64b_0_q == 1'b1 | spr_match_mas81_64b_0_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[34:47] : + ((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[0] == 1'b1)) ? mas6_0_spid_q : + ((tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1)) ? tlb_mas1_0_tid_error_upd : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas1_tid : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? {`PID_WIDTH{1'b0}} : + mas1_0_tid_q; + assign mas1_0_ind_d = (((spr_match_mas1_0_q == 1'b1 | spr_match_mas01_64b_0_q == 1'b1 | spr_match_mas81_64b_0_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[50] : + ((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1) ? mas4_0_indd_q : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas1_ind : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? 1'b0 : + mas1_0_ind_q; + assign mas1_0_ts_d = (((spr_match_mas1_0_q == 1'b1 | spr_match_mas01_64b_0_q == 1'b1 | spr_match_mas81_64b_0_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[51] : + ((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[0] == 1'b1)) ? mas6_0_sas_q : + ((tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1)) ? tlb_mas1_0_ts_error_upd : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas1_ts : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? 1'b0 : + mas1_0_ts_q; + assign mas1_0_tsize_d = (((spr_match_mas1_0_q == 1'b1 | spr_match_mas01_64b_0_q == 1'b1 | spr_match_mas81_64b_0_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[52:55] : + (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1)) ? mas4_0_tsized_q : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas1_tsize : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? lrat_mas1_tsize : + mas1_0_tsize_q; + + assign mas2_0_epn_d[32:51] = ((spr_match_mas2_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32:51] : + ((tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1)) ? tlb_mas2_0_epn_error_upd[32:51] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas2_epn[32:51] : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? lrat_mas2_epn[32:51] : + mas2_0_epn_q[32:51]; + assign mas2_0_wimge_d = ((spr_match_mas2_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[59:63] : + (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1)) ? mas4_0_wimged_q : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas2_wimge : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? 5'b0 : + mas2_0_wimge_q; + + assign mas3_0_rpnl_d = (((spr_match_mas3_0_q == 1'b1 | spr_match_mas73_64b_0_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32:52] : + (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1)) ? {21{1'b0}} : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? {tlb_mas3_rpnl, (tlb_mas3_usxwr[5] & tlb_mas1_ind)} : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? {lrat_mas3_rpnl, 1'b0} : + mas3_0_rpnl_q; + assign mas3_0_ubits_d = (((spr_match_mas3_0_q == 1'b1 | spr_match_mas73_64b_0_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[54:57] : + (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1)) ? 4'b0 : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas3_ubits : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? 4'b0 : + mas3_0_ubits_q; + assign mas3_0_usxwr_d = (((spr_match_mas3_0_q == 1'b1 | spr_match_mas73_64b_0_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[58:63] : + (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1)) ? 6'b0 : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? ({tlb_mas3_usxwr[0:4], (tlb_mas3_usxwr[5] & (~tlb_mas1_ind))}) : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? 6'b0 : + mas3_0_usxwr_q; + + // no h/w updates to mas4 + assign mas4_0_indd_d = ((spr_match_mas4_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[48] : + mas4_0_indd_q; + assign mas4_0_tsized_d = ((spr_match_mas4_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[52:55] : + mas4_0_tsized_q; + assign mas4_0_wimged_d = ((spr_match_mas4_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[59:63] : + mas4_0_wimged_q; + + assign mas6_0_spid_d = (((spr_match_mas6_0_q == 1'b1 | spr_match_mas56_64b_0_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[34:47] : + ((tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1)) ? tlb_mas1_0_tid_error_upd : + mas6_0_spid_q; + assign mas6_0_isize_d = (((spr_match_mas6_0_q == 1'b1 | spr_match_mas56_64b_0_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[52:55] : + ((tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1)) ? mas4_0_tsized_q : + mas6_0_isize_q; + assign mas6_0_sind_d = (((spr_match_mas6_0_q == 1'b1 | spr_match_mas56_64b_0_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[62] : + ((tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1)) ? mas4_0_indd_q : + mas6_0_sind_q; + assign mas6_0_sas_d = (((spr_match_mas6_0_q == 1'b1 | spr_match_mas56_64b_0_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[63] : + ((tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1)) ? tlb_mas1_0_ts_error_upd : + mas6_0_sas_q; + +`ifdef MM_THREADS2 + assign mas1_1_v_d = (((spr_match_mas1_1_q == 1'b1 | spr_match_mas01_64b_1_q == 1'b1 | spr_match_mas81_64b_1_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32] : + ((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[1] == 1'b1)) ? 1'b0 : + ((tlb_mas_tlbsx_hit == 1'b1 & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1) ? 1'b1 : + ((tlb_mas_tlbre == 1'b1 & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas1_v : + ((lrat_mas_tlbsx_miss == 1'b1 & lrat_mas_thdid[1] == 1'b1)) ? 1'b0 : + ((lrat_mas_tlbsx_hit == 1'b1 & lrat_mas_thdid[1] == 1'b1)) ? 1'b1 : + ((lrat_mas_tlbre == 1'b1 & lrat_mas_thdid[1] == 1'b1)) ? lrat_mas1_v : + mas1_1_v_q; + assign mas1_1_iprot_d = (((spr_match_mas1_1_q == 1'b1 | spr_match_mas01_64b_1_q == 1'b1 | spr_match_mas81_64b_1_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[33] : + (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1)) ? 1'b0 : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas1_iprot : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? 1'b0 : + mas1_1_iprot_q; + assign mas1_1_tid_d = (((spr_match_mas1_1_q == 1'b1 | spr_match_mas01_64b_1_q == 1'b1 | spr_match_mas81_64b_1_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[34:47] : + ((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[1] == 1'b1)) ? mas6_1_spid_q : + (((tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1))) ? tlb_mas1_1_tid_error_upd : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas1_tid : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? {`PID_WIDTH{1'b0}} : + mas1_1_tid_q; + assign mas1_1_ind_d = (((spr_match_mas1_1_q == 1'b1 | spr_match_mas01_64b_1_q == 1'b1 | spr_match_mas81_64b_1_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[50] : + (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1)) ? mas4_1_indd_q : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas1_ind : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? 1'b0 : + mas1_1_ind_q; + assign mas1_1_ts_d = (((spr_match_mas1_1_q == 1'b1 | spr_match_mas01_64b_1_q == 1'b1 | spr_match_mas81_64b_1_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[51] : + ((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[1] == 1'b1)) ? mas6_1_sas_q : + (((tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1))) ? tlb_mas1_1_ts_error_upd : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas1_ts : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? 1'b0 : + mas1_1_ts_q; + assign mas1_1_tsize_d = (((spr_match_mas1_1_q == 1'b1 | spr_match_mas01_64b_1_q == 1'b1 | spr_match_mas81_64b_1_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[52:55] : + (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1)) ? mas4_1_tsized_q : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas1_tsize : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? lrat_mas1_tsize : + mas1_1_tsize_q; + + assign mas2_1_epn_d[32:51] = ((spr_match_mas2_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32:51] : + (((tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1))) ? tlb_mas2_1_epn_error_upd[32:51] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas2_epn[32:51] : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? lrat_mas2_epn[32:51] : + mas2_1_epn_q[32:51]; + assign mas2_1_wimge_d = ((spr_match_mas2_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[59:63] : + (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1)) ? mas4_1_wimged_q : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas2_wimge : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? 5'b0 : + mas2_1_wimge_q; + + assign mas3_1_rpnl_d = (((spr_match_mas3_1_q == 1'b1 | spr_match_mas73_64b_1_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32:52] : + (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1)) ? 21'b0 : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? {tlb_mas3_rpnl, (tlb_mas3_usxwr[5] & tlb_mas1_ind)} : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? {lrat_mas3_rpnl, 1'b0} : + mas3_1_rpnl_q; + assign mas3_1_ubits_d = (((spr_match_mas3_1_q == 1'b1 | spr_match_mas73_64b_1_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[54:57] : + (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1)) ? 4'b0 : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas3_ubits : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? 4'b0 : + mas3_1_ubits_q; + assign mas3_1_usxwr_d = (((spr_match_mas3_1_q == 1'b1 | spr_match_mas73_64b_1_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[58:63] : + (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1)) ? 6'b0 : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? ({tlb_mas3_usxwr[0:4], (tlb_mas3_usxwr[5] & (~tlb_mas1_ind))}) : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? 6'b0 : + mas3_1_usxwr_q; + + // no h/w updates to mas4 + assign mas4_1_indd_d = ((spr_match_mas4_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[48] : + mas4_1_indd_q; + assign mas4_1_tsized_d = ((spr_match_mas4_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[52:55] : + mas4_1_tsized_q; + assign mas4_1_wimged_d = ((spr_match_mas4_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[59:63] : + mas4_1_wimged_q; + + assign mas6_1_spid_d = (((spr_match_mas6_1_q == 1'b1 | spr_match_mas56_64b_1_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[34:47] : + (((tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1))) ? tlb_mas1_1_tid_error_upd : + mas6_1_spid_q; + assign mas6_1_isize_d = (((spr_match_mas6_1_q == 1'b1 | spr_match_mas56_64b_1_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[52:55] : + (((tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1))) ? mas4_1_tsized_q : + mas6_1_isize_q; + assign mas6_1_sind_d = (((spr_match_mas6_1_q == 1'b1 | spr_match_mas56_64b_1_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[62] : + (((tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1))) ? mas4_1_indd_q : + mas6_1_sind_q; + assign mas6_1_sas_d = (((spr_match_mas6_1_q == 1'b1 | spr_match_mas56_64b_1_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[63] : + (((tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1))) ? tlb_mas1_1_ts_error_upd : + mas6_1_sas_q; +`endif + + generate + if (`SPR_DATA_WIDTH == 32) + begin : gen32_mas_d + assign mas0_0_atsel_d = ((spr_match_mas0_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbsx_miss == 1'b1) & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1) ? 1'b0 : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbsx_miss == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? 1'b1 : + mas0_0_atsel_q; + assign mas0_0_esel_d = ((spr_match_mas0_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[45:47] : + (((tlb_mas_tlbsx_hit == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas0_esel : + (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1)) ? 3'b0 : + (((lrat_mas_tlbsx_hit == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? lrat_mas0_esel : + mas0_0_esel_q; + assign mas0_0_hes_d = ((spr_match_mas0_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[49] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbsx_miss == 1'b1) & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1) ? 1'b1 : + mas0_0_hes_q; + assign mas0_0_wq_d = ((spr_match_mas0_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[50:51] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbsx_miss == 1'b1) & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1) ? 2'b01 : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbsx_miss == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? 2'b00 : + mas0_0_wq_q; + + assign mas5_0_sgs_d = ((spr_match_mas5_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32] : + mas5_0_sgs_q; + assign mas5_0_slpid_d = ((spr_match_mas5_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[56:63] : + mas5_0_slpid_q; + + assign mas7_0_rpnu_d = ((spr_match_mas7_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[54:63] : + (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1)) ? {`REAL_ADDR_WIDTH-32{1'b0}} : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas7_rpnu : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? lrat_mas7_rpnu : + mas7_0_rpnu_q; + + assign mas8_0_tgs_d = ((spr_match_mas8_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas8_tgs : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? 1'b0 : + mas8_0_tgs_q; + assign mas8_0_vf_d = ((spr_match_mas8_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[33] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas8_vf : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? 1'b0 : + mas8_0_vf_q; + assign mas8_0_tlpid_d = ((spr_match_mas8_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[56:63] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas8_tlpid : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? lrat_mas8_tlpid : + mas8_0_tlpid_q; + +`ifdef MM_THREADS2 + assign mas0_1_atsel_d = ((spr_match_mas0_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbsx_miss == 1'b1) & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1) ? 1'b0 : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbsx_miss == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? 1'b1 : + mas0_1_atsel_q; + assign mas0_1_esel_d = ((spr_match_mas0_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[45:47] : + (((tlb_mas_tlbsx_hit == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas0_esel : + (((tlb_mas_tlbsx_miss == 1'b1) & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1) ? 3'b0 : + (((lrat_mas_tlbsx_hit == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? lrat_mas0_esel : + mas0_1_esel_q; + assign mas0_1_hes_d = ((spr_match_mas0_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[49] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbsx_miss == 1'b1) & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1) ? 1'b1 : + mas0_1_hes_q; + assign mas0_1_wq_d = ((spr_match_mas0_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[50:51] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbsx_miss == 1'b1) & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1) ? 2'b01 : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbsx_miss == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? 2'b00 : + mas0_1_wq_q; + + assign mas5_1_sgs_d = ((spr_match_mas5_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32] : + mas5_1_sgs_q; + assign mas5_1_slpid_d = ((spr_match_mas5_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[56:63] : + mas5_1_slpid_q; + + assign mas7_1_rpnu_d = ((spr_match_mas7_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[54:63] : + (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1)) ? {`REAL_ADDR_WIDTH-32{1'b0}} : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas7_rpnu : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? lrat_mas7_rpnu : + mas7_1_rpnu_q; + + assign mas8_1_tgs_d = ((spr_match_mas8_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas8_tgs : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? 1'b0 : + mas8_1_tgs_q; + assign mas8_1_vf_d = ((spr_match_mas8_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[33] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas8_vf : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? 1'b0 : + mas8_1_vf_q; + assign mas8_1_tlpid_d = ((spr_match_mas8_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[56:63] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas8_tlpid : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? lrat_mas8_tlpid : + mas8_1_tlpid_q; +`endif + end + endgenerate + + generate + if (`SPR_DATA_WIDTH == 64) + begin : gen64_mas_d + assign mas0_0_atsel_d = ((spr_match_mas0_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32] : + ((spr_match_mas01_64b_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[0] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbsx_miss == 1'b1) & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1) ? 1'b0 : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbsx_miss == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? 1'b1 : + mas0_0_atsel_q; + assign mas0_0_esel_d = ((spr_match_mas0_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[45:47] : + ((spr_match_mas01_64b_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[13:15] : + (((tlb_mas_tlbsx_hit == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas0_esel : + (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1)) ? 3'b0 : + (((lrat_mas_tlbsx_hit == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? lrat_mas0_esel : + mas0_0_esel_q; + assign mas0_0_hes_d = ((spr_match_mas0_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[49] : + ((spr_match_mas01_64b_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[17] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbsx_miss == 1'b1) & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1) ? 1'b1 : + mas0_0_hes_q; + assign mas0_0_wq_d = ((spr_match_mas0_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[50:51] : + ((spr_match_mas01_64b_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[18:19] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbsx_miss == 1'b1) & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1) ? 2'b01 : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbsx_miss == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? 2'b00 : + mas0_0_wq_q; + + assign mas2_0_epn_d[0:31] = ((spr_match_mas2u_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32:63] : + ((spr_match_mas2_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[0:31] : + (((tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1))) ? tlb_mas2_0_epn_error_upd[0:31] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas2_epn[0:31] : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? lrat_mas2_epn[0:31] : + mas2_0_epn_q[0:31]; + + assign mas5_0_sgs_d = ((spr_match_mas5_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32] : + ((spr_match_mas56_64b_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[0] : + mas5_0_sgs_q; + assign mas5_0_slpid_d = ((spr_match_mas5_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[56:63] : + ((spr_match_mas56_64b_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[24:31] : + mas5_0_slpid_q; + + assign mas7_0_rpnu_d = ((spr_match_mas7_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[54:63] : + (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1)) ? {`REAL_ADDR_WIDTH-32{1'b0}} : + ((spr_match_mas73_64b_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[22:31] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas7_rpnu : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? lrat_mas7_rpnu : + mas7_0_rpnu_q; + + assign mas8_0_tgs_d = ((spr_match_mas8_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32] : + ((spr_match_mas81_64b_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[0] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas8_tgs : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? 1'b0 : + mas8_0_tgs_q; + assign mas8_0_vf_d = ((spr_match_mas8_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[33] : + ((spr_match_mas81_64b_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[1] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas8_vf : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? 1'b0 : + mas8_0_vf_q; + assign mas8_0_tlpid_d = ((spr_match_mas8_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[56:63] : + ((spr_match_mas81_64b_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[24:31] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas8_tlpid : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? lrat_mas8_tlpid : + mas8_0_tlpid_q; + +`ifdef MM_THREADS2 + assign mas0_1_atsel_d = ((spr_match_mas0_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32] : + ((spr_match_mas01_64b_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[0] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbsx_miss == 1'b1) & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1) ? 1'b0 : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbsx_miss == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? 1'b1 : + mas0_1_atsel_q; + assign mas0_1_esel_d = ((spr_match_mas0_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[45:47] : + ((spr_match_mas01_64b_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[13:15] : + (((tlb_mas_tlbsx_hit == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas0_esel : + (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1)) ? 3'b0 : + (((lrat_mas_tlbsx_hit == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? lrat_mas0_esel : + mas0_1_esel_q; + assign mas0_1_hes_d = ((spr_match_mas0_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[49] : + ((spr_match_mas01_64b_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[17] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbsx_miss == 1'b1) & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1) ? 1'b1 : + mas0_1_hes_q; + assign mas0_1_wq_d = ((spr_match_mas0_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[50:51] : + ((spr_match_mas01_64b_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[18:19] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbsx_miss == 1'b1) & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1) ? 2'b01 : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbsx_miss == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? 2'b00 : + mas0_1_wq_q; + + assign mas2_1_epn_d[0:31] = ((spr_match_mas2u_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32:63] : + ((spr_match_mas2_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[0:31] : + (((tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1))) ? tlb_mas2_1_epn_error_upd[0:31] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas2_epn[0:31] : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? lrat_mas2_epn[0:31] : + mas2_1_epn_q[0:31]; + + assign mas5_1_sgs_d = ((spr_match_mas5_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32] : + ((spr_match_mas56_64b_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[0] : + mas5_1_sgs_q; + assign mas5_1_slpid_d = ((spr_match_mas5_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[56:63] : + ((spr_match_mas56_64b_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[24:31] : + mas5_1_slpid_q; + + assign mas7_1_rpnu_d = ((spr_match_mas7_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[54:63] : + (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1)) ? {`REAL_ADDR_WIDTH-32{1'b0}} : + ((spr_match_mas73_64b_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[22:31] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas7_rpnu : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? lrat_mas7_rpnu : + mas7_1_rpnu_q; + + assign mas8_1_tgs_d = ((spr_match_mas8_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32] : + ((spr_match_mas81_64b_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[0] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas8_tgs : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? 1'b0 : + mas8_1_tgs_q; + assign mas8_1_vf_d = ((spr_match_mas8_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[33] : + ((spr_match_mas81_64b_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[1] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas8_vf : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? 1'b0 : + mas8_1_vf_q; + assign mas8_1_tlpid_d = ((spr_match_mas8_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[56:63] : + ((spr_match_mas81_64b_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[24:31] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas8_tlpid : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? lrat_mas8_tlpid : + mas8_1_tlpid_q; +`endif + end + endgenerate + + // 0: val, 1: rw, 2: done + assign spr_ctl_out_d[0] = spr_ctl_int_q[0] & (~(spr_val_int_flushed)); + assign spr_ctl_out_d[1] = spr_ctl_int_q[1]; + assign spr_ctl_out_d[2] = (spr_ctl_int_q[2] | spr_match_any_mmu_q) & (~(spr_val_int_flushed)); + assign spr_etid_out_d = spr_etid_int_q; + assign spr_addr_out_d = spr_addr_int_q; + //constant Spr_RW_Write : std_ulogic := '0'; -- write value for rw signal + //constant Spr_RW_Read : std_ulogic := '1'; -- read value for rw signal + + assign spr_data_out_d[32:63] = ( {{32-`LPID_WIDTH{1'b0}}, lpidr_q} & {32{(spr_match_lpidr_q & spr_ctl_int_q[1])}} ) | + ( {{32-`PID_WIDTH{1'b0}}, pid0_q} & {32{(spr_match_pid0_q & spr_ctl_int_q[1])}} ) | + ( {mmucr0_0_q[0:5], 12'b0, mmucr0_0_q[6:19]} & {32{(spr_match_mmucr0_0_q & spr_ctl_int_q[1])}} ) | + ( mmucr1_q & {32{(spr_match_mmucr1_q & spr_ctl_int_q[1])}} ) | + ( mmucr2_q & {32{(spr_match_mmucr2_q & spr_ctl_int_q[1])}} ) | + ( {{32-`MMUCR3_WIDTH{1'b0}}, mmucr3_0_q[64 - `MMUCR3_WIDTH:58], 1'b0, mmucr3_0_q[60:59+`MM_THREADS], {`THDID_WIDTH-`MM_THREADS{1'b0}} } & {32{(spr_match_mmucr3_0_q & spr_ctl_int_q[1])}} ) | + ( {mesr1_q[32:32 + `MESR1_WIDTH - 1], {32-`MESR1_WIDTH{1'b0}}} & {32{(spr_match_mesr1_q & spr_ctl_int_q[1])}} ) | + ( {mesr2_q[32:32 + `MESR2_WIDTH - 1], {32-`MESR2_WIDTH{1'b0}}} & {32{(spr_match_mesr2_q & spr_ctl_int_q[1])}} ) | + ( {29'b0, mmucsr0_tlb0fi_q, 2'b00} & {32{(spr_match_mmucsr0_q & spr_ctl_int_q[1])}} ) | + ( {Spr_Data_MMUCFG[32:46], mmucfg_q[47:48], Spr_Data_MMUCFG[49:63]} & {32{(spr_match_mmucfg_q & spr_ctl_int_q[1])}} ) | + ( {Spr_Data_TLB0CFG[32:44], tlb0cfg_q[45:47], Spr_Data_TLB0CFG[48:63]} & {32{(spr_match_tlb0cfg_q & spr_ctl_int_q[1])}} ) | + ( Spr_Data_TLB0PS & {32{(spr_match_tlb0ps_q & spr_ctl_int_q[1])}} ) | + ( Spr_Data_LRATCFG & {32{(spr_match_lratcfg_q & spr_ctl_int_q[1])}} ) | + ( Spr_Data_LRATPS & {32{(spr_match_lratps_q & spr_ctl_int_q[1])}} ) | + ( Spr_Data_EPTCFG & {32{(spr_match_eptcfg_q & spr_ctl_int_q[1])}} ) | + ( {lper_0_alpn_q[32:51], 8'b0, lper_0_lps_q[60:63]} & {32{(spr_match_lper_0_q & spr_ctl_int_q[1])}} ) | + ( {{64-`REAL_ADDR_WIDTH{1'b0}}, lper_0_alpn_q[64 - `REAL_ADDR_WIDTH:31]} & {32{(spr_match_lperu_0_q & spr_ctl_int_q[1])}} ) | +`ifdef MM_THREADS2 + ( {{32-`PID_WIDTH{1'b0}}, pid1_q} & {32{(spr_match_pid1_q & spr_ctl_int_q[1])}} ) | + ( {mmucr0_1_q[0:5], 12'b0, mmucr0_1_q[6:19]} & {32{(spr_match_mmucr0_1_q & spr_ctl_int_q[1])}} ) | + ( {{32-`MMUCR3_WIDTH{1'b0}}, mmucr3_1_q[64 - `MMUCR3_WIDTH:58], 1'b0, mmucr3_1_q[60:59+`MM_THREADS], {`THDID_WIDTH-`MM_THREADS{1'b0}} } & {32{(spr_match_mmucr3_1_q & spr_ctl_int_q[1])}} ) | + ( {lper_1_alpn_q[32:51], 8'b0, lper_1_lps_q[60:63]} & {32{(spr_match_lper_1_q & spr_ctl_int_q[1])}} ) | + ( {{64-`REAL_ADDR_WIDTH{1'b0}}, lper_1_alpn_q[64 - `REAL_ADDR_WIDTH:31]} & {32{(spr_match_lperu_1_q & spr_ctl_int_q[1])}} ) | +`endif + ( (spr_mas_data_out_q[32:63]) & {32{(spr_match_any_mas_q & spr_ctl_int_q[1])}} ) | + ( spr_data_int_q[32:63] & {32{(~spr_match_any_mmu_q)}} ); + + assign spr_mas_data_out[32:63] = ( {mas0_0_atsel_q, 12'b0, mas0_0_esel_q, 1'b0, mas0_0_hes_q, mas0_0_wq_q, 12'b0} & {32{spr_match_mas0_0}} ) | + ( {mas1_0_v_q, mas1_0_iprot_q, mas1_0_tid_q, 2'b00, mas1_0_ind_q, mas1_0_ts_q, mas1_0_tsize_q, 8'b00000000} & {32{(spr_match_mas1_0 | spr_match_mas01_64b_0 | spr_match_mas81_64b_0)}} ) | + ( {mas2_0_epn_q[32:51], 7'b0000000, mas2_0_wimge_q} & {32{spr_match_mas2_0}} ) | + ( {mas2_0_epn_q[0:31]} & {32{spr_match_mas2u_0}} ) | + ( {mas3_0_rpnl_q, 1'b0, mas3_0_ubits_q, mas3_0_usxwr_q} & {32{(spr_match_mas3_0 | spr_match_mas73_64b_0)}} ) | + ( {16'b0, mas4_0_indd_q, 3'b000, mas4_0_tsized_q, 3'b000, mas4_0_wimged_q} & {32{spr_match_mas4_0}} ) | + ( {mas5_0_sgs_q, 23'b0, mas5_0_slpid_q} & {32{spr_match_mas5_0}} ) | + ( {2'b00, mas6_0_spid_q, 4'b0000, mas6_0_isize_q, 6'b000000, mas6_0_sind_q, mas6_0_sas_q} & {32{(spr_match_mas6_0 | spr_match_mas56_64b_0)}} ) | + ( {22'b0, mas7_0_rpnu_q} & {32{spr_match_mas7_0}} ) | +`ifdef MM_THREADS2 + ( {mas8_0_tgs_q, mas8_0_vf_q, 22'b0, mas8_0_tlpid_q} & {32{spr_match_mas8_0}} ) | + ( {mas0_1_atsel_q, 12'b0, mas0_1_esel_q, 1'b0, mas0_1_hes_q, mas0_1_wq_q, 12'b0} & {32{spr_match_mas0_1}} ) | + ( {mas1_1_v_q, mas1_1_iprot_q, mas1_1_tid_q, 2'b00, mas1_1_ind_q, mas1_1_ts_q, mas1_1_tsize_q, 8'b00000000} & {32{(spr_match_mas1_1 | spr_match_mas01_64b_1 | spr_match_mas81_64b_1)}} ) | + ( {mas2_1_epn_q[32:51], 7'b0000000, mas2_1_wimge_q} & {32{spr_match_mas2_1}} ) | + ( {mas2_1_epn_q[0:31]} & {32{spr_match_mas2u_1}} ) | + ( {mas3_1_rpnl_q, 1'b0, mas3_1_ubits_q, mas3_1_usxwr_q} & {32{(spr_match_mas3_1 | spr_match_mas73_64b_1)}} ) | + ( {16'b0, mas4_1_indd_q, 3'b000, mas4_1_tsized_q, 3'b000, mas4_1_wimged_q} & {32{spr_match_mas4_1}} ) | + ( {mas5_1_sgs_q, 23'b0, mas5_1_slpid_q} & {32{spr_match_mas5_1}} ) | + ( {2'b00, mas6_1_spid_q, 4'b0000, mas6_1_isize_q, 6'b000000, mas6_1_sind_q, mas6_1_sas_q} & {32{(spr_match_mas6_1 | spr_match_mas56_64b_1)}} ) | + ( {22'b0, mas7_1_rpnu_q} & {32{spr_match_mas7_1}} ) | + ( {mas8_1_tgs_q, mas8_1_vf_q, 22'b0, mas8_1_tlpid_q} & {32{spr_match_mas8_1}} ); +`else + ( {mas8_0_tgs_q, mas8_0_vf_q, 22'b0, mas8_0_tlpid_q} & {32{spr_match_mas8_0}} ); +`endif + + generate + if (`SPR_DATA_WIDTH == 64) + begin : gen64_spr_data + assign spr_mas_data_out[0:31] = ( mas2_0_epn_q[0:31] & {32{spr_match_mas2_0}} ) | + ( {mas0_0_atsel_q, 12'b0, mas0_0_esel_q, 1'b0, mas0_0_hes_q, mas0_0_wq_q, 12'b0} & {32{spr_match_mas01_64b_0}} ) | + ( {mas5_0_sgs_q, 23'b0, mas5_0_slpid_q} & {32{spr_match_mas56_64b_0}} ) | + ( {22'b0, mas7_0_rpnu_q} & {32{spr_match_mas73_64b_0}} ) | +`ifdef MM_THREADS2 + ( {mas8_0_tgs_q, mas8_0_vf_q, 22'b0, mas8_0_tlpid_q} & {32{spr_match_mas81_64b_0}} ) | + ( {mas2_1_epn_q[0:31]} & {32{spr_match_mas2_1}} ) | + ( {mas0_1_atsel_q, 12'b0, mas0_1_esel_q, 1'b0, mas0_1_hes_q, mas0_1_wq_q, 12'b0} & {32{spr_match_mas01_64b_1}} ) | + ( {mas5_1_sgs_q, 23'b0, mas5_1_slpid_q} & {32{spr_match_mas56_64b_1}} ) | + ( {22'b0, mas7_1_rpnu_q} & {32{spr_match_mas73_64b_1}} ) | + ( {mas8_1_tgs_q, mas8_1_vf_q, 22'b0, mas8_1_tlpid_q} & {32{spr_match_mas81_64b_1}} ); +`else + ( {mas8_0_tgs_q, mas8_0_vf_q, 22'b0, mas8_0_tlpid_q} & {32{spr_match_mas81_64b_0}} ); +`endif + + //constant Spr_RW_Write : std_ulogic := '0'; -- write value for rw signal + //constant Spr_RW_Read : std_ulogic := '1'; -- read value for rw signal + assign spr_data_out_d[0:31] = ( {{64-`REAL_ADDR_WIDTH{1'b0}}, lper_0_alpn_q[64 - `REAL_ADDR_WIDTH:31]} & {32{(spr_match_lper_0_q & spr_ctl_int_q[1])}} ) | +`ifdef MM_THREADS2 + ( {{64-`REAL_ADDR_WIDTH{1'b0}}, lper_1_alpn_q[64 - `REAL_ADDR_WIDTH:31]} & {32{(spr_match_lper_1_q & spr_ctl_int_q[1])}} ) | +`endif + ( {spr_mas_data_out_q[0:31]} & {32{(spr_match_any_mas_q & spr_ctl_int_q[1])}} ) | + ( {spr_data_int_q[0:31]} & {32{((~(spr_match_any_mmu_q)) | (~(spr_ctl_int_q[1])))}} ); + end + endgenerate + + assign mm_iu_slowspr_val = spr_ctl_out_q[0]; + assign mm_iu_slowspr_rw = spr_ctl_out_q[1]; + assign mm_iu_slowspr_etid = spr_etid_out_q; + assign mm_iu_slowspr_addr = spr_addr_out_q; + assign mm_iu_slowspr_data = spr_data_out_q; + assign mm_iu_slowspr_done = spr_ctl_out_q[2]; + + assign mm_iu_ierat_pid0 = pid0_q; + assign mm_iu_ierat_mmucr0_0 = mmucr0_0_q; + assign mm_iu_ierat_mmucr1 = {mmucr1_q[0], mmucr1_q[2:5], mmucr1_q[6:7], mmucr1_q[12:13]}; + assign mm_xu_derat_pid0 = pid0_q; + assign mm_xu_derat_mmucr0_0 = mmucr0_0_q; + assign mm_xu_derat_mmucr1 = {mmucr1_q[1], mmucr1_q[2:5], mmucr1_q[8:9], mmucr1_q[14:16]}; +`ifdef MM_THREADS2 + assign mm_iu_ierat_pid1 = pid1_q; + assign mm_iu_ierat_mmucr0_1 = mmucr0_1_q; + assign mm_xu_derat_pid1 = pid1_q; + assign mm_xu_derat_mmucr0_1 = mmucr0_1_q; +`endif + + // mmucr1: 0-IRRE, 1-DRRE, 2-REE, 3-CEE, + // 4-Disable any context sync inst from invalidating extclass=0 erat entries, + // 5-Disable isync inst from invalidating extclass=0 erat entries, + // 6:7-IPEI, 8:9-DPEI, 10:11-TPEI, 12:13-ICTID/ITTID, 14:15-DCTID/DTTID, + // 16-DCCD, 17-TLBWE_BINV, 18-TLBI_MSB, 19-TLBI_REJ, + // 20-IERRDET, 21-DERRDET, 22-TERRDET, 23:31-EEN + assign pid0 = pid0_q; + assign mmucr0_0 = mmucr0_0_q; + assign mmucr1 = mmucr1_q; + assign mmucr2 = mmucr2_q; + assign mmucr3_0 = mmucr3_0_q; + assign tstmode4k_0 = tstmode4k_0_q[1:3]; +`ifdef MM_THREADS2 + assign pid1 = pid1_q; + assign mmucr0_1 = mmucr0_1_q; + assign mmucr3_1 = mmucr3_1_q; + assign tstmode4k_1 = tstmode4k_1_q[1:3]; +`endif + assign lpidr = lpidr_q; + assign ac_an_lpar_id = lpidr_q; + assign mmucfg_lrat = mmucfg_q[47]; + assign mmucfg_twc = mmucfg_q[48]; + assign tlb0cfg_pt = tlb0cfg_q[45]; + assign tlb0cfg_ind = tlb0cfg_q[46]; + assign tlb0cfg_gtwe = tlb0cfg_q[47]; + assign mmq_spr_event_mux_ctrls = {mesr1_q, mesr2_q}; + assign mas0_0_atsel = mas0_0_atsel_q; + assign mas0_0_esel = mas0_0_esel_q; + assign mas0_0_hes = mas0_0_hes_q; + assign mas0_0_wq = mas0_0_wq_q; + assign mas1_0_v = mas1_0_v_q; + assign mas1_0_iprot = mas1_0_iprot_q; + assign mas1_0_tid = mas1_0_tid_q; + assign mas1_0_ind = mas1_0_ind_q; + assign mas1_0_ts = mas1_0_ts_q; + assign mas1_0_tsize = mas1_0_tsize_q; + + generate + if (`SPR_DATA_WIDTH == 32) + begin : gen32_mas2_0_epn + assign mas2_0_epn[0:31] = {32{1'b0}}; + assign mas2_0_epn[32:51] = mas2_0_epn_q[32:51]; + end + endgenerate + generate + if (`SPR_DATA_WIDTH == 64) + begin : gen64_mas2_0_epn + assign mas2_0_epn = mas2_0_epn_q; + end + endgenerate + + assign mas2_0_wimge = mas2_0_wimge_q; + assign mas3_0_rpnl = mas3_0_rpnl_q; + assign mas3_0_ubits = mas3_0_ubits_q; + assign mas3_0_usxwr = mas3_0_usxwr_q; + assign mas5_0_sgs = mas5_0_sgs_q; + assign mas5_0_slpid = mas5_0_slpid_q; + assign mas6_0_spid = mas6_0_spid_q; + assign mas6_0_isize = mas6_0_isize_q; + assign mas6_0_sind = mas6_0_sind_q; + assign mas6_0_sas = mas6_0_sas_q; + assign mas7_0_rpnu = mas7_0_rpnu_q; + assign mas8_0_tgs = mas8_0_tgs_q; + assign mas8_0_vf = mas8_0_vf_q; + assign mas8_0_tlpid = mas8_0_tlpid_q; +`ifdef MM_THREADS2 + assign mas0_1_atsel = mas0_1_atsel_q; + assign mas0_1_esel = mas0_1_esel_q; + assign mas0_1_hes = mas0_1_hes_q; + assign mas0_1_wq = mas0_1_wq_q; + assign mas1_1_v = mas1_1_v_q; + assign mas1_1_iprot = mas1_1_iprot_q; + assign mas1_1_tid = mas1_1_tid_q; + assign mas1_1_ind = mas1_1_ind_q; + assign mas1_1_ts = mas1_1_ts_q; + assign mas1_1_tsize = mas1_1_tsize_q; + + generate + if (`SPR_DATA_WIDTH == 32) + begin : gen32_mas2_1_epn + assign mas2_1_epn[0:31] = {32{1'b0}}; + assign mas2_1_epn[32:51] = mas2_1_epn_q[32:51]; + end + endgenerate + generate + if (`SPR_DATA_WIDTH == 64) + begin : gen64_mas2_1_epn + assign mas2_1_epn = mas2_1_epn_q; + end + endgenerate + + assign mas2_1_wimge = mas2_1_wimge_q; + assign mas3_1_rpnl = mas3_1_rpnl_q; + assign mas3_1_ubits = mas3_1_ubits_q; + assign mas3_1_usxwr = mas3_1_usxwr_q; + assign mas5_1_sgs = mas5_1_sgs_q; + assign mas5_1_slpid = mas5_1_slpid_q; + assign mas6_1_spid = mas6_1_spid_q; + assign mas6_1_isize = mas6_1_isize_q; + assign mas6_1_sind = mas6_1_sind_q; + assign mas6_1_sas = mas6_1_sas_q; + assign mas7_1_rpnu = mas7_1_rpnu_q; + assign mas8_1_tgs = mas8_1_tgs_q; + assign mas8_1_vf = mas8_1_vf_q; + assign mas8_1_tlpid = mas8_1_tlpid_q; +`endif + + assign mmucsr0_tlb0fi = mmucsr0_tlb0fi_q; + +`ifdef WAIT_UPDATES +`ifdef MM_THREADS2 + assign cp_mm_perf_except_taken_q[0] = cp_mm_except_taken_t0_q[0]; + assign cp_mm_perf_except_taken_q[1] = cp_mm_except_taken_t1_q[0]; + assign cp_mm_perf_except_taken_q[2:6] = (cp_mm_except_taken_t0_q[1:5] | cp_mm_except_taken_t1_q[1:5]); +`else + assign cp_mm_perf_except_taken_q = cp_mm_except_taken_t0_q; +`endif +`endif + + + // debug output formation + //spr_dbg_slowspr_val_in <= spr_ctl_in_q(0); -- 0: val, 1: rw, 2: done + //spr_dbg_slowspr_rw_in <= spr_ctl_in_q(1); + //spr_dbg_slowspr_etid_in <= spr_etid_in_q; + //spr_dbg_slowspr_addr_in <= spr_addr_in_q; + assign spr_dbg_slowspr_val_int = spr_ctl_int_q[0]; + assign spr_dbg_slowspr_rw_int = spr_ctl_int_q[1]; + assign spr_dbg_slowspr_etid_int = spr_etid_int_q; + assign spr_dbg_slowspr_addr_int = spr_addr_int_q; + assign spr_dbg_slowspr_val_out = spr_ctl_out_q[0]; + assign spr_dbg_slowspr_done_out = spr_ctl_out_q[2]; + assign spr_dbg_slowspr_data_out = spr_data_out_q; + assign spr_dbg_match_64b = spr_match_64b_q; + assign spr_dbg_match_any_mmu = spr_match_any_mmu_q; + assign spr_dbg_match_any_mas = spr_match_any_mas_q; + assign spr_dbg_match_mmucr1 = spr_match_mmucr1_q; + assign spr_dbg_match_mmucr2 = spr_match_mmucr2_q; + assign spr_dbg_match_lpidr = spr_match_lpidr_q; + assign spr_dbg_match_mmucsr0 = spr_match_mmucsr0_q; + assign spr_dbg_match_mmucfg = spr_match_mmucfg_q; + assign spr_dbg_match_tlb0cfg = spr_match_tlb0cfg_q; + assign spr_dbg_match_tlb0ps = spr_match_tlb0ps_q; + assign spr_dbg_match_lratcfg = spr_match_lratcfg; + assign spr_dbg_match_lratps = spr_match_lratps_q; + assign spr_dbg_match_eptcfg = spr_match_eptcfg_q; +`ifdef MM_THREADS2 + assign spr_dbg_match_pid = spr_match_pid0_q | spr_match_pid1_q; + assign spr_dbg_match_mmucr0 = spr_match_mmucr0_0_q | spr_match_mmucr0_1_q; + assign spr_dbg_match_mmucr3 = spr_match_mmucr3_0_q | spr_match_mmucr3_1_q; + assign spr_dbg_match_lper = spr_match_lper_0_q | spr_match_lper_1_q; + assign spr_dbg_match_lperu = spr_match_lperu_0_q | spr_match_lperu_1_q; + assign spr_dbg_match_mas0 = spr_match_mas0_0_q | spr_match_mas0_1_q; + assign spr_dbg_match_mas1 = spr_match_mas1_0_q | spr_match_mas1_1_q; + assign spr_dbg_match_mas2 = spr_match_mas2_0_q | spr_match_mas2_1_q; + assign spr_dbg_match_mas2u = spr_match_mas2u_0_q | spr_match_mas2u_1_q; + assign spr_dbg_match_mas3 = spr_match_mas3_0_q | spr_match_mas3_1_q; + assign spr_dbg_match_mas4 = spr_match_mas4_0_q | spr_match_mas4_1_q; + assign spr_dbg_match_mas5 = spr_match_mas5_0_q | spr_match_mas5_1_q; + assign spr_dbg_match_mas6 = spr_match_mas6_0_q | spr_match_mas6_1_q; + assign spr_dbg_match_mas7 = spr_match_mas7_0_q | spr_match_mas7_1_q; + assign spr_dbg_match_mas8 = spr_match_mas8_0_q | spr_match_mas8_1_q; + assign spr_dbg_match_mas01_64b = spr_match_mas01_64b_0_q | spr_match_mas01_64b_1_q; + assign spr_dbg_match_mas56_64b = spr_match_mas56_64b_0_q | spr_match_mas56_64b_1_q; + assign spr_dbg_match_mas73_64b = spr_match_mas73_64b_0_q | spr_match_mas73_64b_1_q; + assign spr_dbg_match_mas81_64b = spr_match_mas81_64b_0_q | spr_match_mas81_64b_1_q; +`else + assign spr_dbg_match_pid = spr_match_pid0_q; + assign spr_dbg_match_mmucr0 = spr_match_mmucr0_0_q; + assign spr_dbg_match_mmucr3 = spr_match_mmucr3_0_q; + assign spr_dbg_match_lper = spr_match_lper_0_q; + assign spr_dbg_match_lperu = spr_match_lperu_0_q; + assign spr_dbg_match_mas0 = spr_match_mas0_0_q; + assign spr_dbg_match_mas1 = spr_match_mas1_0_q; + assign spr_dbg_match_mas2 = spr_match_mas2_0_q; + assign spr_dbg_match_mas2u = spr_match_mas2u_0_q; + assign spr_dbg_match_mas3 = spr_match_mas3_0_q; + assign spr_dbg_match_mas4 = spr_match_mas4_0_q; + assign spr_dbg_match_mas5 = spr_match_mas5_0_q; + assign spr_dbg_match_mas6 = spr_match_mas6_0_q; + assign spr_dbg_match_mas7 = spr_match_mas7_0_q; + assign spr_dbg_match_mas8 = spr_match_mas8_0_q; + assign spr_dbg_match_mas01_64b = spr_match_mas01_64b_0_q; + assign spr_dbg_match_mas56_64b = spr_match_mas56_64b_0_q; + assign spr_dbg_match_mas73_64b = spr_match_mas73_64b_0_q; + assign spr_dbg_match_mas81_64b = spr_match_mas81_64b_0_q; +`endif + + // unused spare signal assignments + assign unused_dc[0] = |(lcb_delay_lclkr_dc[1:4]); + assign unused_dc[1] = |(lcb_mpw1_dc_b[1:4]); + assign unused_dc[2] = pc_func_sl_force; + assign unused_dc[3] = pc_func_sl_thold_0_b; + assign unused_dc[4] = tc_scan_dis_dc_b; + assign unused_dc[5] = tc_scan_diag_dc; + assign unused_dc[6] = tc_lbist_en_dc; + +generate + if (`EXPAND_TYPE != 1) + begin + assign unused_dc[7] = |(mmucfg_q_b); + assign unused_dc[8] = |(tlb0cfg_q_b); + assign unused_dc[13] = |(bcfg_spare_q_b); + end + else + begin + assign unused_dc[7] = 1'b0; + assign unused_dc[8] = 1'b0; + assign unused_dc[13] = pc_cfg_sl_thold_0; + end +endgenerate + + assign unused_dc[9] = 1'b0; + assign unused_dc[10] = 1'b0; + assign unused_dc[11] = |(lrat_tag4_hit_entry); + assign unused_dc[12] = |(bcfg_spare_q); + + //------------------------------------------------ + // latches + //------------------------------------------------ + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) cp_flush_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[cp_flush_offset:cp_flush_offset + `MM_THREADS - 1]), + .scout(sov_0[cp_flush_offset:cp_flush_offset + `MM_THREADS - 1]), + .din(cp_flush_d[0:`MM_THREADS - 1]), + .dout(cp_flush_q[0:`MM_THREADS - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) cp_flush_p1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[cp_flush_p1_offset:cp_flush_p1_offset + `MM_THREADS - 1]), + .scout(sov_0[cp_flush_p1_offset:cp_flush_p1_offset + `MM_THREADS - 1]), + .din(cp_flush_p1_d[0:`MM_THREADS - 1]), + .dout(cp_flush_p1_q[0:`MM_THREADS - 1]) + ); + + // slow spr daisy-chain latches + + tri_rlmreg_p #(.WIDTH(`SPR_CTL_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_ctl_in_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_ctl_in_offset:spr_ctl_in_offset + `SPR_CTL_WIDTH - 1]), + .scout(sov_0[spr_ctl_in_offset:spr_ctl_in_offset + `SPR_CTL_WIDTH - 1]), + .din(spr_ctl_in_d[0:`SPR_CTL_WIDTH - 1]), + .dout(spr_ctl_in_q[0:`SPR_CTL_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`SPR_ETID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_etid_in_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_etid_in_offset:spr_etid_in_offset + `SPR_ETID_WIDTH - 1]), + .scout(sov_0[spr_etid_in_offset:spr_etid_in_offset + `SPR_ETID_WIDTH - 1]), + .din(spr_etid_in_d[0:`SPR_ETID_WIDTH - 1]), + .dout(spr_etid_in_q[0:`SPR_ETID_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`SPR_ADDR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_addr_in_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_addr_in_offset:spr_addr_in_offset + `SPR_ADDR_WIDTH - 1]), + .scout(sov_0[spr_addr_in_offset:spr_addr_in_offset + `SPR_ADDR_WIDTH - 1]), + .din(spr_addr_in_d[0:`SPR_ADDR_WIDTH - 1]), + .dout(spr_addr_in_q[0:`SPR_ADDR_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`SPR_ADDR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_addr_in_clone_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_addr_in_clone_offset:spr_addr_in_clone_offset + `SPR_ADDR_WIDTH - 1]), + .scout(sov_1[spr_addr_in_clone_offset:spr_addr_in_clone_offset + `SPR_ADDR_WIDTH - 1]), + .din(spr_addr_in_clone_d[0:`SPR_ADDR_WIDTH - 1]), + .dout(spr_addr_in_clone_q[0:`SPR_ADDR_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`SPR_DATA_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_data_in_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_data_in_offset:spr_data_in_offset + `SPR_DATA_WIDTH - 1]), + .scout(sov_0[spr_data_in_offset:spr_data_in_offset + `SPR_DATA_WIDTH - 1]), + .din(spr_data_in_d[64 - `SPR_DATA_WIDTH:63]), + .dout(spr_data_in_q[64 - `SPR_DATA_WIDTH:63]) + ); + // these are the spr internal select stage latches below + + tri_rlmreg_p #(.WIDTH(`SPR_CTL_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_ctl_int_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_val_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_ctl_int_offset:spr_ctl_int_offset + `SPR_CTL_WIDTH - 1]), + .scout(sov_0[spr_ctl_int_offset:spr_ctl_int_offset + `SPR_CTL_WIDTH - 1]), + .din(spr_ctl_int_d[0:`SPR_CTL_WIDTH - 1]), + .dout(spr_ctl_int_q[0:`SPR_CTL_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`SPR_ETID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_etid_int_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_val_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_etid_int_offset:spr_etid_int_offset + `SPR_ETID_WIDTH - 1]), + .scout(sov_0[spr_etid_int_offset:spr_etid_int_offset + `SPR_ETID_WIDTH - 1]), + .din(spr_etid_int_d[0:`SPR_ETID_WIDTH - 1]), + .dout(spr_etid_int_q[0:`SPR_ETID_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`SPR_ADDR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_addr_int_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_val_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_addr_int_offset:spr_addr_int_offset + `SPR_ADDR_WIDTH - 1]), + .scout(sov_0[spr_addr_int_offset:spr_addr_int_offset + `SPR_ADDR_WIDTH - 1]), + .din(spr_addr_int_d[0:`SPR_ADDR_WIDTH - 1]), + .dout(spr_addr_int_q[0:`SPR_ADDR_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`SPR_DATA_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_data_int_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_val_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_data_int_offset:spr_data_int_offset + `SPR_DATA_WIDTH - 1]), + .scout(sov_0[spr_data_int_offset:spr_data_int_offset + `SPR_DATA_WIDTH - 1]), + .din(spr_data_int_d[64 - `SPR_DATA_WIDTH:63]), + .dout(spr_data_int_q[64 - `SPR_DATA_WIDTH:63]) + ); + // these are the spr out latches below + + tri_rlmreg_p #(.WIDTH(`SPR_CTL_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_ctl_out_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_val_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_ctl_out_offset:spr_ctl_out_offset + `SPR_CTL_WIDTH - 1]), + .scout(sov_0[spr_ctl_out_offset:spr_ctl_out_offset + `SPR_CTL_WIDTH - 1]), + .din(spr_ctl_out_d[0:`SPR_CTL_WIDTH - 1]), + .dout(spr_ctl_out_q[0:`SPR_CTL_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`SPR_ETID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_etid_out_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_val_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_etid_out_offset:spr_etid_out_offset + `SPR_ETID_WIDTH - 1]), + .scout(sov_0[spr_etid_out_offset:spr_etid_out_offset + `SPR_ETID_WIDTH - 1]), + .din(spr_etid_out_d[0:`SPR_ETID_WIDTH - 1]), + .dout(spr_etid_out_q[0:`SPR_ETID_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`SPR_ADDR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_addr_out_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_val_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_addr_out_offset:spr_addr_out_offset + `SPR_ADDR_WIDTH - 1]), + .scout(sov_0[spr_addr_out_offset:spr_addr_out_offset + `SPR_ADDR_WIDTH - 1]), + .din(spr_addr_out_d[0:`SPR_ADDR_WIDTH - 1]), + .dout(spr_addr_out_q[0:`SPR_ADDR_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`SPR_DATA_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_data_out_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_val_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_data_out_offset:spr_data_out_offset + `SPR_DATA_WIDTH - 1]), + .scout(sov_0[spr_data_out_offset:spr_data_out_offset + `SPR_DATA_WIDTH - 1]), + .din(spr_data_out_d[64 - `SPR_DATA_WIDTH:63]), + .dout(spr_data_out_q[64 - `SPR_DATA_WIDTH:63]) + ); + // spr decode match latches for timing + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_any_mmu_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_match_any_mmu_offset]), + .scout(sov_0[spr_match_any_mmu_offset]), + .din(spr_match_any_mmu), + .dout(spr_match_any_mmu_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_pid0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_match_pid0_offset]), + .scout(sov_0[spr_match_pid0_offset]), + .din(spr_match_pid0), + .dout(spr_match_pid0_q) + ); + +`ifdef MM_THREADS2 + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_pid1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_match_pid1_offset]), + .scout(sov_0[spr_match_pid1_offset]), + .din(spr_match_pid1), + .dout(spr_match_pid1_q) + ); +`endif + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mmucr0_0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_match_mmucr0_0_offset]), + .scout(sov_0[spr_match_mmucr0_0_offset]), + .din(spr_match_mmucr0_0), + .dout(spr_match_mmucr0_0_q) + ); + +`ifdef MM_THREADS2 + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mmucr0_1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_match_mmucr0_1_offset]), + .scout(sov_0[spr_match_mmucr0_1_offset]), + .din(spr_match_mmucr0_1), + .dout(spr_match_mmucr0_1_q) + ); +`endif + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mmucr1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_match_mmucr1_offset]), + .scout(sov_0[spr_match_mmucr1_offset]), + .din(spr_match_mmucr1), + .dout(spr_match_mmucr1_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mmucr2_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_match_mmucr2_offset]), + .scout(sov_0[spr_match_mmucr2_offset]), + .din(spr_match_mmucr2), + .dout(spr_match_mmucr2_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mmucr3_0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_match_mmucr3_0_offset]), + .scout(sov_0[spr_match_mmucr3_0_offset]), + .din(spr_match_mmucr3_0), + .dout(spr_match_mmucr3_0_q) + ); + +`ifdef MM_THREADS2 + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mmucr3_1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_match_mmucr3_1_offset]), + .scout(sov_0[spr_match_mmucr3_1_offset]), + .din(spr_match_mmucr3_1), + .dout(spr_match_mmucr3_1_q) + ); +`endif + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_lpidr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_match_lpidr_offset]), + .scout(sov_0[spr_match_lpidr_offset]), + .din(spr_match_lpidr), + .dout(spr_match_lpidr_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mesr1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_match_mesr1_offset]), + .scout(sov_0[spr_match_mesr1_offset]), + .din(spr_match_mesr1), + .dout(spr_match_mesr1_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mesr2_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_match_mesr2_offset]), + .scout(sov_0[spr_match_mesr2_offset]), + .din(spr_match_mesr2), + .dout(spr_match_mesr2_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mmucsr0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mmucsr0_offset]), + .scout(sov_1[spr_match_mmucsr0_offset]), + .din(spr_match_mmucsr0), + .dout(spr_match_mmucsr0_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mmucfg_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mmucfg_offset]), + .scout(sov_1[spr_match_mmucfg_offset]), + .din(spr_match_mmucfg), + .dout(spr_match_mmucfg_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_tlb0cfg_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_tlb0cfg_offset]), + .scout(sov_1[spr_match_tlb0cfg_offset]), + .din(spr_match_tlb0cfg), + .dout(spr_match_tlb0cfg_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_tlb0ps_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_tlb0ps_offset]), + .scout(sov_1[spr_match_tlb0ps_offset]), + .din(spr_match_tlb0ps), + .dout(spr_match_tlb0ps_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_lratcfg_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_lratcfg_offset]), + .scout(sov_1[spr_match_lratcfg_offset]), + .din(spr_match_lratcfg), + .dout(spr_match_lratcfg_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_lratps_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_lratps_offset]), + .scout(sov_1[spr_match_lratps_offset]), + .din(spr_match_lratps), + .dout(spr_match_lratps_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_eptcfg_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_eptcfg_offset]), + .scout(sov_1[spr_match_eptcfg_offset]), + .din(spr_match_eptcfg), + .dout(spr_match_eptcfg_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_lper_0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_lper_0_offset]), + .scout(sov_1[spr_match_lper_0_offset]), + .din(spr_match_lper_0), + .dout(spr_match_lper_0_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_lperu_0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_lperu_0_offset]), + .scout(sov_1[spr_match_lperu_0_offset]), + .din(spr_match_lperu_0), + .dout(spr_match_lperu_0_q) + ); + +`ifdef MM_THREADS2 + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_lper_1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_lper_1_offset]), + .scout(sov_1[spr_match_lper_1_offset]), + .din(spr_match_lper_1), + .dout(spr_match_lper_1_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_lperu_1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_lperu_1_offset]), + .scout(sov_1[spr_match_lperu_1_offset]), + .din(spr_match_lperu_1), + .dout(spr_match_lperu_1_q) + ); +`endif + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas0_0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas0_0_offset]), + .scout(sov_1[spr_match_mas0_0_offset]), + .din(spr_match_mas0_0), + .dout(spr_match_mas0_0_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas1_0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas1_0_offset]), + .scout(sov_1[spr_match_mas1_0_offset]), + .din(spr_match_mas1_0), + .dout(spr_match_mas1_0_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas2_0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas2_0_offset]), + .scout(sov_1[spr_match_mas2_0_offset]), + .din(spr_match_mas2_0), + .dout(spr_match_mas2_0_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas3_0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas3_0_offset]), + .scout(sov_1[spr_match_mas3_0_offset]), + .din(spr_match_mas3_0), + .dout(spr_match_mas3_0_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas4_0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas4_0_offset]), + .scout(sov_1[spr_match_mas4_0_offset]), + .din(spr_match_mas4_0), + .dout(spr_match_mas4_0_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas5_0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas5_0_offset]), + .scout(sov_1[spr_match_mas5_0_offset]), + .din(spr_match_mas5_0), + .dout(spr_match_mas5_0_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas6_0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas6_0_offset]), + .scout(sov_1[spr_match_mas6_0_offset]), + .din(spr_match_mas6_0), + .dout(spr_match_mas6_0_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas7_0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas7_0_offset]), + .scout(sov_1[spr_match_mas7_0_offset]), + .din(spr_match_mas7_0), + .dout(spr_match_mas7_0_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas8_0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas8_0_offset]), + .scout(sov_1[spr_match_mas8_0_offset]), + .din(spr_match_mas8_0), + .dout(spr_match_mas8_0_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas2u_0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas2u_0_offset]), + .scout(sov_1[spr_match_mas2u_0_offset]), + .din(spr_match_mas2u_0), + .dout(spr_match_mas2u_0_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas01_64b_0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas01_64b_0_offset]), + .scout(sov_1[spr_match_mas01_64b_0_offset]), + .din(spr_match_mas01_64b_0), + .dout(spr_match_mas01_64b_0_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas56_64b_0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas56_64b_0_offset]), + .scout(sov_1[spr_match_mas56_64b_0_offset]), + .din(spr_match_mas56_64b_0), + .dout(spr_match_mas56_64b_0_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas73_64b_0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas73_64b_0_offset]), + .scout(sov_1[spr_match_mas73_64b_0_offset]), + .din(spr_match_mas73_64b_0), + .dout(spr_match_mas73_64b_0_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas81_64b_0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas81_64b_0_offset]), + .scout(sov_1[spr_match_mas81_64b_0_offset]), + .din(spr_match_mas81_64b_0), + .dout(spr_match_mas81_64b_0_q) + ); + +`ifdef MM_THREADS2 + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas0_1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas0_1_offset]), + .scout(sov_1[spr_match_mas0_1_offset]), + .din(spr_match_mas0_1), + .dout(spr_match_mas0_1_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas1_1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas1_1_offset]), + .scout(sov_1[spr_match_mas1_1_offset]), + .din(spr_match_mas1_1), + .dout(spr_match_mas1_1_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas2_1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas2_1_offset]), + .scout(sov_1[spr_match_mas2_1_offset]), + .din(spr_match_mas2_1), + .dout(spr_match_mas2_1_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas3_1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas3_1_offset]), + .scout(sov_1[spr_match_mas3_1_offset]), + .din(spr_match_mas3_1), + .dout(spr_match_mas3_1_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas4_1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas4_1_offset]), + .scout(sov_1[spr_match_mas4_1_offset]), + .din(spr_match_mas4_1), + .dout(spr_match_mas4_1_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas5_1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas5_1_offset]), + .scout(sov_1[spr_match_mas5_1_offset]), + .din(spr_match_mas5_1), + .dout(spr_match_mas5_1_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas6_1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas6_1_offset]), + .scout(sov_1[spr_match_mas6_1_offset]), + .din(spr_match_mas6_1), + .dout(spr_match_mas6_1_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas7_1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas7_1_offset]), + .scout(sov_1[spr_match_mas7_1_offset]), + .din(spr_match_mas7_1), + .dout(spr_match_mas7_1_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas8_1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas8_1_offset]), + .scout(sov_1[spr_match_mas8_1_offset]), + .din(spr_match_mas8_1), + .dout(spr_match_mas8_1_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas2u_1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas2u_1_offset]), + .scout(sov_1[spr_match_mas2u_1_offset]), + .din(spr_match_mas2u_1), + .dout(spr_match_mas2u_1_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas01_64b_1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas01_64b_1_offset]), + .scout(sov_1[spr_match_mas01_64b_1_offset]), + .din(spr_match_mas01_64b_1), + .dout(spr_match_mas01_64b_1_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas56_64b_1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas56_64b_1_offset]), + .scout(sov_1[spr_match_mas56_64b_1_offset]), + .din(spr_match_mas56_64b_1), + .dout(spr_match_mas56_64b_1_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas73_64b_1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas73_64b_1_offset]), + .scout(sov_1[spr_match_mas73_64b_1_offset]), + .din(spr_match_mas73_64b_1), + .dout(spr_match_mas73_64b_1_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas81_64b_1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas81_64b_1_offset]), + .scout(sov_1[spr_match_mas81_64b_1_offset]), + .din(spr_match_mas81_64b_1), + .dout(spr_match_mas81_64b_1_q) + ); +`endif + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_64b_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_64b_offset]), + .scout(sov_1[spr_match_64b_offset]), + .din(spr_match_64b), + .dout(spr_match_64b_q) + ); + // internal mas data output register + + tri_rlmreg_p #(.WIDTH(`SPR_DATA_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_mas_data_out_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_mas_data_out_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_mas_data_out_offset:spr_mas_data_out_offset + `SPR_DATA_WIDTH - 1]), + .scout(sov_1[spr_mas_data_out_offset:spr_mas_data_out_offset + `SPR_DATA_WIDTH - 1]), + .din(spr_mas_data_out[64 - `SPR_DATA_WIDTH:63]), + .dout(spr_mas_data_out_q[64 - `SPR_DATA_WIDTH:63]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_any_mas_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_any_mas_offset]), + .scout(sov_1[spr_match_any_mas_offset]), + .din(spr_match_any_mas), + .dout(spr_match_any_mas_q) + ); + // pid spr's + + tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) pid0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_mmu_act_q[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[pid0_offset:pid0_offset + `PID_WIDTH - 1]), + .scout(sov_0[pid0_offset:pid0_offset + `PID_WIDTH - 1]), + .din(pid0_d[0:`PID_WIDTH - 1]), + .dout(pid0_q[0:`PID_WIDTH - 1]) + ); + +`ifdef MM_THREADS2 + tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) pid1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_mmu_act_q[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[pid1_offset:pid1_offset + `PID_WIDTH - 1]), + .scout(sov_0[pid1_offset:pid1_offset + `PID_WIDTH - 1]), + .din(pid1_d[0:`PID_WIDTH - 1]), + .dout(pid1_q[0:`PID_WIDTH - 1]) + ); +`endif + + tri_rlmreg_p #(.WIDTH(`MMUCR0_WIDTH), .INIT(0), .NEEDS_SRESET(1)) mmucr0_0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[mmucr0_0_offset:mmucr0_0_offset + `MMUCR0_WIDTH - 1]), + .scout(sov_0[mmucr0_0_offset:mmucr0_0_offset + `MMUCR0_WIDTH - 1]), + .din(mmucr0_0_d[0:`MMUCR0_WIDTH - 1]), + .dout(mmucr0_0_q[0:`MMUCR0_WIDTH - 1]) + ); + +`ifdef MM_THREADS2 + tri_rlmreg_p #(.WIDTH(`MMUCR0_WIDTH), .INIT(0), .NEEDS_SRESET(1)) mmucr0_1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[mmucr0_1_offset:mmucr0_1_offset + `MMUCR0_WIDTH - 1]), + .scout(sov_0[mmucr0_1_offset:mmucr0_1_offset + `MMUCR0_WIDTH - 1]), + .din(mmucr0_1_d[0:`MMUCR0_WIDTH - 1]), + .dout(mmucr0_1_q[0:`MMUCR0_WIDTH - 1]) + ); +`endif + + tri_rlmreg_p #(.WIDTH(`MMUCR1_WIDTH), .INIT(BCFG_MMUCR1_VALUE), .NEEDS_SRESET(1)) mmucr1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_cfg_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_cfg_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(bsiv[mmucr1_offset:mmucr1_offset + `MMUCR1_WIDTH - 1]), + .scout(bsov[mmucr1_offset:mmucr1_offset + `MMUCR1_WIDTH - 1]), + .din(mmucr1_d[0:`MMUCR1_WIDTH - 1]), + .dout(mmucr1_q[0:`MMUCR1_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`MMUCR2_WIDTH), .INIT(BCFG_MMUCR2_VALUE), .NEEDS_SRESET(1)) mmucr2_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_cfg_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_cfg_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(bsiv[mmucr2_offset:mmucr2_offset + `MMUCR2_WIDTH - 1]), + .scout(bsov[mmucr2_offset:mmucr2_offset + `MMUCR2_WIDTH - 1]), + .din(mmucr2_d[0:`MMUCR2_WIDTH - 1]), + .dout(mmucr2_q[0:`MMUCR2_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`MMUCR3_WIDTH), .INIT(BCFG_MMUCR3_VALUE), .NEEDS_SRESET(1)) mmucr3_0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[0]), + .thold_b(pc_cfg_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_cfg_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(bsiv[mmucr3_0_offset:mmucr3_0_offset + `MMUCR3_WIDTH - 1]), + .scout(bsov[mmucr3_0_offset:mmucr3_0_offset + `MMUCR3_WIDTH - 1]), + .din(mmucr3_0_d[64 - `MMUCR3_WIDTH:63]), + .dout(mmucr3_0_q[64 - `MMUCR3_WIDTH:63]) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) tstmode4k_0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[0]), + .thold_b(pc_cfg_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_cfg_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(bsiv[tstmode4k_0_offset:tstmode4k_0_offset + 3]), + .scout(bsov[tstmode4k_0_offset:tstmode4k_0_offset + 3]), + .din(tstmode4k_0_d), + .dout(tstmode4k_0_q) + ); + +`ifdef MM_THREADS2 + tri_rlmreg_p #(.WIDTH(`MMUCR3_WIDTH), .INIT(BCFG_MMUCR3_VALUE), .NEEDS_SRESET(1)) mmucr3_1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[1]), + .thold_b(pc_cfg_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_cfg_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(bsiv[mmucr3_1_offset:mmucr3_1_offset + `MMUCR3_WIDTH - 1]), + .scout(bsov[mmucr3_1_offset:mmucr3_1_offset + `MMUCR3_WIDTH - 1]), + .din(mmucr3_1_d[64 - `MMUCR3_WIDTH:63]), + .dout(mmucr3_1_q[64 - `MMUCR3_WIDTH:63]) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) tstmode4k_1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[1]), + .thold_b(pc_cfg_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_cfg_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(bsiv[tstmode4k_1_offset:tstmode4k_1_offset + 3]), + .scout(bsov[tstmode4k_1_offset:tstmode4k_1_offset + 3]), + .din(tstmode4k_1_d), + .dout(tstmode4k_1_q) + ); + +`endif + + tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lpidr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_mmu_act_q[`MM_THREADS]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[lpidr_offset:lpidr_offset + `LPID_WIDTH - 1]), + .scout(sov_0[lpidr_offset:lpidr_offset + `LPID_WIDTH - 1]), + .din(lpidr_d[0:`LPID_WIDTH - 1]), + .dout(lpidr_q[0:`LPID_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`MESR1_WIDTH), .INIT(0), .NEEDS_SRESET(1)) mesr1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_mmu_act_q[`MM_THREADS]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[mesr1_offset:mesr1_offset + `MESR1_WIDTH - 1]), + .scout(sov_0[mesr1_offset:mesr1_offset + `MESR1_WIDTH - 1]), + .din(mesr1_d), + .dout(mesr1_q) + ); + + tri_rlmreg_p #(.WIDTH(`MESR2_WIDTH), .INIT(0), .NEEDS_SRESET(1)) mesr2_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_mmu_act_q[`MM_THREADS]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[mesr2_offset:mesr2_offset + `MESR2_WIDTH - 1]), + .scout(sov_0[mesr2_offset:mesr2_offset + `MESR2_WIDTH - 1]), + .din(mesr2_d), + .dout(mesr2_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas0_0_atsel_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas0_0_atsel_offset]), + .scout(sov_1[mas0_0_atsel_offset]), + .din(mas0_0_atsel_d), + .dout(mas0_0_atsel_q) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) mas0_0_esel_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas0_0_esel_offset:mas0_0_esel_offset + 3 - 1]), + .scout(sov_1[mas0_0_esel_offset:mas0_0_esel_offset + 3 - 1]), + .din(mas0_0_esel_d[0:3 - 1]), + .dout(mas0_0_esel_q[0:3 - 1]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas0_0_hes_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas0_0_hes_offset]), + .scout(sov_1[mas0_0_hes_offset]), + .din(mas0_0_hes_d), + .dout(mas0_0_hes_q) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) mas0_0_wq_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas0_0_wq_offset:mas0_0_wq_offset + 2 - 1]), + .scout(sov_1[mas0_0_wq_offset:mas0_0_wq_offset + 2 - 1]), + .din(mas0_0_wq_d[0:2 - 1]), + .dout(mas0_0_wq_q[0:2 - 1]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas1_0_v_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas1_0_v_offset]), + .scout(sov_1[mas1_0_v_offset]), + .din(mas1_0_v_d), + .dout(mas1_0_v_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas1_0_iprot_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas1_0_iprot_offset]), + .scout(sov_1[mas1_0_iprot_offset]), + .din(mas1_0_iprot_d), + .dout(mas1_0_iprot_q) + ); + + tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) mas1_0_tid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas1_0_tid_offset:mas1_0_tid_offset + 14 - 1]), + .scout(sov_1[mas1_0_tid_offset:mas1_0_tid_offset + 14 - 1]), + .din(mas1_0_tid_d[0:`PID_WIDTH - 1]), + .dout(mas1_0_tid_q[0:`PID_WIDTH - 1]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas1_0_ind_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas1_0_ind_offset]), + .scout(sov_1[mas1_0_ind_offset]), + .din(mas1_0_ind_d), + .dout(mas1_0_ind_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas1_0_ts_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas1_0_ts_offset]), + .scout(sov_1[mas1_0_ts_offset]), + .din(mas1_0_ts_d), + .dout(mas1_0_ts_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) mas1_0_tsize_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas1_0_tsize_offset:mas1_0_tsize_offset + 4 - 1]), + .scout(sov_1[mas1_0_tsize_offset:mas1_0_tsize_offset + 4 - 1]), + .din(mas1_0_tsize_d[0:4 - 1]), + .dout(mas1_0_tsize_q[0:4 - 1]) + ); + + tri_rlmreg_p #(.WIDTH(52-(64-`SPR_DATA_WIDTH)), .INIT(0), .NEEDS_SRESET(1)) mas2_0_epn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas2_0_epn_offset:mas2_0_epn_offset + (52-(64-`SPR_DATA_WIDTH)) - 1]), + .scout(sov_1[mas2_0_epn_offset:mas2_0_epn_offset + (52-(64-`SPR_DATA_WIDTH)) - 1]), + .din(mas2_0_epn_d[(64-`SPR_DATA_WIDTH):51]), + .dout(mas2_0_epn_q[(64-`SPR_DATA_WIDTH):51]) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) mas2_0_wimge_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas2_0_wimge_offset:mas2_0_wimge_offset + 5 - 1]), + .scout(sov_1[mas2_0_wimge_offset:mas2_0_wimge_offset + 5 - 1]), + .din(mas2_0_wimge_d[0:5 - 1]), + .dout(mas2_0_wimge_q[0:5 - 1]) + ); + + tri_rlmreg_p #(.WIDTH(21), .INIT(0), .NEEDS_SRESET(1)) mas3_0_rpnl_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas3_0_rpnl_offset:mas3_0_rpnl_offset + 21 - 1]), + .scout(sov_1[mas3_0_rpnl_offset:mas3_0_rpnl_offset + 21 - 1]), + .din(mas3_0_rpnl_d[32:32 + 21 - 1]), + .dout(mas3_0_rpnl_q[32:32 + 21 - 1]) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) mas3_0_ubits_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas3_0_ubits_offset:mas3_0_ubits_offset + 4 - 1]), + .scout(sov_1[mas3_0_ubits_offset:mas3_0_ubits_offset + 4 - 1]), + .din(mas3_0_ubits_d[0:4 - 1]), + .dout(mas3_0_ubits_q[0:4 - 1]) + ); + + tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) mas3_0_usxwr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas3_0_usxwr_offset:mas3_0_usxwr_offset + 6 - 1]), + .scout(sov_1[mas3_0_usxwr_offset:mas3_0_usxwr_offset + 6 - 1]), + .din(mas3_0_usxwr_d[0:6 - 1]), + .dout(mas3_0_usxwr_q[0:6 - 1]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas4_0_indd_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[0]), + .thold_b(pc_cfg_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_cfg_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(bsiv[mas4_0_indd_offset]), + .scout(bsov[mas4_0_indd_offset]), + .din(mas4_0_indd_d), + .dout(mas4_0_indd_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(1), .NEEDS_SRESET(1)) mas4_0_tsized_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[0]), + .thold_b(pc_cfg_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_cfg_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(bsiv[mas4_0_tsized_offset:mas4_0_tsized_offset + 4 - 1]), + .scout(bsov[mas4_0_tsized_offset:mas4_0_tsized_offset + 4 - 1]), + .din(mas4_0_tsized_d[0:4 - 1]), + .dout(mas4_0_tsized_q[0:4 - 1]) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) mas4_0_wimged_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[0]), + .thold_b(pc_cfg_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_cfg_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(bsiv[mas4_0_wimged_offset:mas4_0_wimged_offset + 5 - 1]), + .scout(bsov[mas4_0_wimged_offset:mas4_0_wimged_offset + 5 - 1]), + .din(mas4_0_wimged_d[0:5 - 1]), + .dout(mas4_0_wimged_q[0:5 - 1]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas5_0_sgs_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas5_0_sgs_offset]), + .scout(sov_1[mas5_0_sgs_offset]), + .din(mas5_0_sgs_d), + .dout(mas5_0_sgs_q) + ); + + tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) mas5_0_slpid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas5_0_slpid_offset:mas5_0_slpid_offset + 8 - 1]), + .scout(sov_1[mas5_0_slpid_offset:mas5_0_slpid_offset + 8 - 1]), + .din(mas5_0_slpid_d[0:8 - 1]), + .dout(mas5_0_slpid_q[0:8 - 1]) + ); + + tri_rlmreg_p #(.WIDTH(14), .INIT(0), .NEEDS_SRESET(1)) mas6_0_spid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas6_0_spid_offset:mas6_0_spid_offset + 14 - 1]), + .scout(sov_1[mas6_0_spid_offset:mas6_0_spid_offset + 14 - 1]), + .din(mas6_0_spid_d[0:14 - 1]), + .dout(mas6_0_spid_q[0:14 - 1]) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) mas6_0_isize_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas6_0_isize_offset:mas6_0_isize_offset + 4 - 1]), + .scout(sov_1[mas6_0_isize_offset:mas6_0_isize_offset + 4 - 1]), + .din(mas6_0_isize_d[0:4 - 1]), + .dout(mas6_0_isize_q[0:4 - 1]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas6_0_sind_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas6_0_sind_offset]), + .scout(sov_1[mas6_0_sind_offset]), + .din(mas6_0_sind_d), + .dout(mas6_0_sind_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas6_0_sas_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas6_0_sas_offset]), + .scout(sov_1[mas6_0_sas_offset]), + .din(mas6_0_sas_d), + .dout(mas6_0_sas_q) + ); + + tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) mas7_0_rpnu_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas7_0_rpnu_offset:mas7_0_rpnu_offset + 10 - 1]), + .scout(sov_1[mas7_0_rpnu_offset:mas7_0_rpnu_offset + 10 - 1]), + .din(mas7_0_rpnu_d[22:22 + 10 - 1]), + .dout(mas7_0_rpnu_q[22:22 + 10 - 1]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas8_0_tgs_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas8_0_tgs_offset]), + .scout(sov_1[mas8_0_tgs_offset]), + .din(mas8_0_tgs_d), + .dout(mas8_0_tgs_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas8_0_vf_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas8_0_vf_offset]), + .scout(sov_1[mas8_0_vf_offset]), + .din(mas8_0_vf_d), + .dout(mas8_0_vf_q) + ); + + tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) mas8_0_tlpid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas8_0_tlpid_offset:mas8_0_tlpid_offset + 8 - 1]), + .scout(sov_1[mas8_0_tlpid_offset:mas8_0_tlpid_offset + 8 - 1]), + .din(mas8_0_tlpid_d[0:8 - 1]), + .dout(mas8_0_tlpid_q[0:8 - 1]) + ); + +`ifdef MM_THREADS2 + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas0_1_atsel_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas0_1_atsel_offset]), + .scout(sov_1[mas0_1_atsel_offset]), + .din(mas0_1_atsel_d), + .dout(mas0_1_atsel_q) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) mas0_1_esel_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas0_1_esel_offset:mas0_1_esel_offset + 3 - 1]), + .scout(sov_1[mas0_1_esel_offset:mas0_1_esel_offset + 3 - 1]), + .din(mas0_1_esel_d[0:3 - 1]), + .dout(mas0_1_esel_q[0:3 - 1]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas0_1_hes_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas0_1_hes_offset]), + .scout(sov_1[mas0_1_hes_offset]), + .din(mas0_1_hes_d), + .dout(mas0_1_hes_q) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) mas0_1_wq_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas0_1_wq_offset:mas0_1_wq_offset + 2 - 1]), + .scout(sov_1[mas0_1_wq_offset:mas0_1_wq_offset + 2 - 1]), + .din(mas0_1_wq_d[0:2 - 1]), + .dout(mas0_1_wq_q[0:2 - 1]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas1_1_v_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas1_1_v_offset]), + .scout(sov_1[mas1_1_v_offset]), + .din(mas1_1_v_d), + .dout(mas1_1_v_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas1_1_iprot_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas1_1_iprot_offset]), + .scout(sov_1[mas1_1_iprot_offset]), + .din(mas1_1_iprot_d), + .dout(mas1_1_iprot_q) + ); + + tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) mas1_1_tid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas1_1_tid_offset:mas1_1_tid_offset + 14 - 1]), + .scout(sov_1[mas1_1_tid_offset:mas1_1_tid_offset + 14 - 1]), + .din(mas1_1_tid_d[0:`PID_WIDTH - 1]), + .dout(mas1_1_tid_q[0:`PID_WIDTH - 1]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas1_1_ind_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas1_1_ind_offset]), + .scout(sov_1[mas1_1_ind_offset]), + .din(mas1_1_ind_d), + .dout(mas1_1_ind_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas1_1_ts_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas1_1_ts_offset]), + .scout(sov_1[mas1_1_ts_offset]), + .din(mas1_1_ts_d), + .dout(mas1_1_ts_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) mas1_1_tsize_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas1_1_tsize_offset:mas1_1_tsize_offset + 4 - 1]), + .scout(sov_1[mas1_1_tsize_offset:mas1_1_tsize_offset + 4 - 1]), + .din(mas1_1_tsize_d[0:4 - 1]), + .dout(mas1_1_tsize_q[0:4 - 1]) + ); + + tri_rlmreg_p #(.WIDTH(52-(64-`SPR_DATA_WIDTH)), .INIT(0), .NEEDS_SRESET(1)) mas2_1_epn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas2_1_epn_offset:mas2_1_epn_offset + (52-(64-`SPR_DATA_WIDTH)) - 1]), + .scout(sov_1[mas2_1_epn_offset:mas2_1_epn_offset + (52-(64-`SPR_DATA_WIDTH)) - 1]), + .din(mas2_1_epn_d[(64-`SPR_DATA_WIDTH):51]), + .dout(mas2_1_epn_q[(64-`SPR_DATA_WIDTH):51]) + ); + + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) mas2_1_wimge_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas2_1_wimge_offset:mas2_1_wimge_offset + 5 - 1]), + .scout(sov_1[mas2_1_wimge_offset:mas2_1_wimge_offset + 5 - 1]), + .din(mas2_1_wimge_d[0:5 - 1]), + .dout(mas2_1_wimge_q[0:5 - 1]) + ); + + tri_rlmreg_p #(.WIDTH(21), .INIT(0), .NEEDS_SRESET(1)) mas3_1_rpnl_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas3_1_rpnl_offset:mas3_1_rpnl_offset + 21 - 1]), + .scout(sov_1[mas3_1_rpnl_offset:mas3_1_rpnl_offset + 21 - 1]), + .din(mas3_1_rpnl_d[32:32 + 21 - 1]), + .dout(mas3_1_rpnl_q[32:32 + 21 - 1]) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) mas3_1_ubits_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas3_1_ubits_offset:mas3_1_ubits_offset + 4 - 1]), + .scout(sov_1[mas3_1_ubits_offset:mas3_1_ubits_offset + 4 - 1]), + .din(mas3_1_ubits_d[0:4 - 1]), + .dout(mas3_1_ubits_q[0:4 - 1]) + ); + + tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) mas3_1_usxwr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas3_1_usxwr_offset:mas3_1_usxwr_offset + 6 - 1]), + .scout(sov_1[mas3_1_usxwr_offset:mas3_1_usxwr_offset + 6 - 1]), + .din(mas3_1_usxwr_d[0:6 - 1]), + .dout(mas3_1_usxwr_q[0:6 - 1]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas4_1_indd_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[1]), + .thold_b(pc_cfg_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_cfg_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(bsiv[mas4_1_indd_offset]), + .scout(bsov[mas4_1_indd_offset]), + .din(mas4_1_indd_d), + .dout(mas4_1_indd_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(1), .NEEDS_SRESET(1)) mas4_1_tsized_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[1]), + .thold_b(pc_cfg_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_cfg_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(bsiv[mas4_1_tsized_offset:mas4_1_tsized_offset + 4 - 1]), + .scout(bsov[mas4_1_tsized_offset:mas4_1_tsized_offset + 4 - 1]), + .din(mas4_1_tsized_d[0:4 - 1]), + .dout(mas4_1_tsized_q[0:4 - 1]) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) mas4_1_wimged_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[1]), + .thold_b(pc_cfg_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_cfg_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(bsiv[mas4_1_wimged_offset:mas4_1_wimged_offset + 5 - 1]), + .scout(bsov[mas4_1_wimged_offset:mas4_1_wimged_offset + 5 - 1]), + .din(mas4_1_wimged_d[0:5 - 1]), + .dout(mas4_1_wimged_q[0:5 - 1]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas5_1_sgs_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas5_1_sgs_offset]), + .scout(sov_1[mas5_1_sgs_offset]), + .din(mas5_1_sgs_d), + .dout(mas5_1_sgs_q) + ); + + tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) mas5_1_slpid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas5_1_slpid_offset:mas5_1_slpid_offset + 8 - 1]), + .scout(sov_1[mas5_1_slpid_offset:mas5_1_slpid_offset + 8 - 1]), + .din(mas5_1_slpid_d[0:8 - 1]), + .dout(mas5_1_slpid_q[0:8 - 1]) + ); + + tri_rlmreg_p #(.WIDTH(14), .INIT(0), .NEEDS_SRESET(1)) mas6_1_spid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas6_1_spid_offset:mas6_1_spid_offset + 14 - 1]), + .scout(sov_1[mas6_1_spid_offset:mas6_1_spid_offset + 14 - 1]), + .din(mas6_1_spid_d[0:14 - 1]), + .dout(mas6_1_spid_q[0:14 - 1]) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) mas6_1_isize_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas6_1_isize_offset:mas6_1_isize_offset + 4 - 1]), + .scout(sov_1[mas6_1_isize_offset:mas6_1_isize_offset + 4 - 1]), + .din(mas6_1_isize_d[0:4 - 1]), + .dout(mas6_1_isize_q[0:4 - 1]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas6_1_sind_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas6_1_sind_offset]), + .scout(sov_1[mas6_1_sind_offset]), + .din(mas6_1_sind_d), + .dout(mas6_1_sind_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas6_1_sas_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas6_1_sas_offset]), + .scout(sov_1[mas6_1_sas_offset]), + .din(mas6_1_sas_d), + .dout(mas6_1_sas_q) + ); + + tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) mas7_1_rpnu_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas7_1_rpnu_offset:mas7_1_rpnu_offset + 10 - 1]), + .scout(sov_1[mas7_1_rpnu_offset:mas7_1_rpnu_offset + 10 - 1]), + .din(mas7_1_rpnu_d[22:22 + 10 - 1]), + .dout(mas7_1_rpnu_q[22:22 + 10 - 1]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas8_1_tgs_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas8_1_tgs_offset]), + .scout(sov_1[mas8_1_tgs_offset]), + .din(mas8_1_tgs_d), + .dout(mas8_1_tgs_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas8_1_vf_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas8_1_vf_offset]), + .scout(sov_1[mas8_1_vf_offset]), + .din(mas8_1_vf_d), + .dout(mas8_1_vf_q) + ); + + tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) mas8_1_tlpid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas8_1_tlpid_offset:mas8_1_tlpid_offset + 8 - 1]), + .scout(sov_1[mas8_1_tlpid_offset:mas8_1_tlpid_offset + 8 - 1]), + .din(mas8_1_tlpid_d[0:8 - 1]), + .dout(mas8_1_tlpid_q[0:8 - 1]) + ); +`endif + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mmucsr0_tlb0fi_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mmucsr0_tlb0fi_offset]), + .scout(sov_1[mmucsr0_tlb0fi_offset]), + .din(mmucsr0_tlb0fi_d), + .dout(mmucsr0_tlb0fi_q) + ); + + tri_rlmreg_p #(.WIDTH(52-(64-`REAL_ADDR_WIDTH)), .INIT(0), .NEEDS_SRESET(1)) lper_0_alpn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[lper_0_alpn_offset:lper_0_alpn_offset + (52 -(64-`REAL_ADDR_WIDTH)) - 1]), + .scout(sov_1[lper_0_alpn_offset:lper_0_alpn_offset + (52 -(64-`REAL_ADDR_WIDTH)) - 1]), + .din(lper_0_alpn_d), + .dout(lper_0_alpn_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lper_0_lps_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[lper_0_lps_offset:lper_0_lps_offset + 4 - 1]), + .scout(sov_1[lper_0_lps_offset:lper_0_lps_offset + 4 - 1]), + .din(lper_0_lps_d), + .dout(lper_0_lps_q) + ); + +`ifdef MM_THREADS2 + tri_rlmreg_p #(.WIDTH(52 -(64-`REAL_ADDR_WIDTH)), .INIT(0), .NEEDS_SRESET(1)) lper_1_alpn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[lper_1_alpn_offset:lper_1_alpn_offset + (52 -(64-`REAL_ADDR_WIDTH)) - 1]), + .scout(sov_1[lper_1_alpn_offset:lper_1_alpn_offset + (52 -(64-`REAL_ADDR_WIDTH)) - 1]), + .din(lper_1_alpn_d), + .dout(lper_1_alpn_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lper_1_lps_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[lper_1_lps_offset:lper_1_lps_offset + 4 - 1]), + .scout(sov_1[lper_1_lps_offset:lper_1_lps_offset + 4 - 1]), + .din(lper_1_lps_d), + .dout(lper_1_lps_q) + ); +`endif + + tri_rlmreg_p #(.WIDTH(`MM_THREADS+1), .INIT(0), .NEEDS_SRESET(1)) spr_mmu_act_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_mmu_act_offset:spr_mmu_act_offset + `MM_THREADS+1 - 1]), + .scout(sov_0[spr_mmu_act_offset:spr_mmu_act_offset + `MM_THREADS+1 - 1]), + .din(spr_mmu_act_d), + .dout(spr_mmu_act_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) spr_val_act_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_val_act_offset:spr_val_act_offset + 4 - 1]), + .scout(sov_0[spr_val_act_offset:spr_val_act_offset + 4 - 1]), + .din(spr_val_act_d), + .dout(spr_val_act_q) + ); + +`ifdef WAIT_UPDATES + tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) cp_mm_except_taken_t0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[cp_mm_except_taken_t0_offset:cp_mm_except_taken_t0_offset + 6 - 1]), + .scout(sov_0[cp_mm_except_taken_t0_offset:cp_mm_except_taken_t0_offset + 6 - 1]), + .din(cp_mm_except_taken_t0_d), + .dout(cp_mm_except_taken_t0_q) + ); + // cp_mm_except_taken + // 0 - thdid/val + // 1 - I=0/D=1 + // 2 - TLB miss + // 3 - Storage int (TLBI/PTfault) + // 4 - LRAT miss + // 5 - Mcheck + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) tlb_mas_dtlb_error_pending_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_mas_dtlb_error_pending_offset:tlb_mas_dtlb_error_pending_offset + `MM_THREADS - 1]), + .scout(sov_0[tlb_mas_dtlb_error_pending_offset:tlb_mas_dtlb_error_pending_offset + `MM_THREADS - 1]), + .din(tlb_mas_dtlb_error_pending_d), + .dout(tlb_mas_dtlb_error_pending_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) tlb_mas_itlb_error_pending_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_mas_itlb_error_pending_offset:tlb_mas_itlb_error_pending_offset + `MM_THREADS - 1]), + .scout(sov_0[tlb_mas_itlb_error_pending_offset:tlb_mas_itlb_error_pending_offset + `MM_THREADS - 1]), + .din(tlb_mas_itlb_error_pending_d), + .dout(tlb_mas_itlb_error_pending_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) tlb_lper_we_pending_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_lper_we_pending_offset:tlb_lper_we_pending_offset + `MM_THREADS - 1]), + .scout(sov_0[tlb_lper_we_pending_offset:tlb_lper_we_pending_offset + `MM_THREADS - 1]), + .din(tlb_lper_we_pending_d), + .dout(tlb_lper_we_pending_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) tlb_mmucr1_we_pending_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_mmucr1_we_pending_offset:tlb_mmucr1_we_pending_offset + `MM_THREADS - 1]), + .scout(sov_0[tlb_mmucr1_we_pending_offset:tlb_mmucr1_we_pending_offset + `MM_THREADS - 1]), + .din(tlb_mmucr1_we_pending_d), + .dout(tlb_mmucr1_we_pending_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ierat_mmucr1_we_pending_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ierat_mmucr1_we_pending_offset:ierat_mmucr1_we_pending_offset + `MM_THREADS - 1]), + .scout(sov_0[ierat_mmucr1_we_pending_offset:ierat_mmucr1_we_pending_offset + `MM_THREADS - 1]), + .din(ierat_mmucr1_we_pending_d), + .dout(ierat_mmucr1_we_pending_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) derat_mmucr1_we_pending_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[derat_mmucr1_we_pending_offset:derat_mmucr1_we_pending_offset + `MM_THREADS - 1]), + .scout(sov_0[derat_mmucr1_we_pending_offset:derat_mmucr1_we_pending_offset + `MM_THREADS - 1]), + .din(derat_mmucr1_we_pending_d), + .dout(derat_mmucr1_we_pending_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_mas1_0_ts_error_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_mas1_0_ts_error_offset]), + .scout(sov_0[tlb_mas1_0_ts_error_offset]), + .din(tlb_mas1_0_ts_error_d), + .dout(tlb_mas1_0_ts_error_q) + ); + + tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_mas1_0_tid_error_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_mas1_0_tid_error_offset:tlb_mas1_0_tid_error_offset + `PID_WIDTH - 1]), + .scout(sov_0[tlb_mas1_0_tid_error_offset:tlb_mas1_0_tid_error_offset + `PID_WIDTH - 1]), + .din(tlb_mas1_0_tid_error_d), + .dout(tlb_mas1_0_tid_error_q) + ); + + tri_rlmreg_p #(.WIDTH(`EPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_mas2_0_epn_error_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_mas2_0_epn_error_offset:tlb_mas2_0_epn_error_offset + `EPN_WIDTH - 1]), + .scout(sov_0[tlb_mas2_0_epn_error_offset:tlb_mas2_0_epn_error_offset + `EPN_WIDTH - 1]), + .din(tlb_mas2_0_epn_error_d), + .dout(tlb_mas2_0_epn_error_q) + ); + + tri_rlmreg_p #(.WIDTH(`REAL_ADDR_WIDTH-12), .INIT(0), .NEEDS_SRESET(1)) tlb_lper_0_lpn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_lper_0_lpn_offset:tlb_lper_0_lpn_offset + `REAL_ADDR_WIDTH-12 - 1]), + .scout(sov_0[tlb_lper_0_lpn_offset:tlb_lper_0_lpn_offset + `REAL_ADDR_WIDTH-12 - 1]), + .din(tlb_lper_0_lpn_d), + .dout(tlb_lper_0_lpn_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) tlb_lper_0_lps_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_lper_0_lps_offset:tlb_lper_0_lps_offset + 4 - 1]), + .scout(sov_0[tlb_lper_0_lps_offset:tlb_lper_0_lps_offset + 4 - 1]), + .din(tlb_lper_0_lps_d), + .dout(tlb_lper_0_lps_q) + ); + + tri_rlmreg_p #(.WIDTH(9), .INIT(0), .NEEDS_SRESET(1)) tlb_mmucr1_0_een_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_mmucr1_0_een_offset:tlb_mmucr1_0_een_offset + 9 - 1]), + .scout(sov_0[tlb_mmucr1_0_een_offset:tlb_mmucr1_0_een_offset + 9 - 1]), + .din(tlb_mmucr1_0_een_d), + .dout(tlb_mmucr1_0_een_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ierat_mmucr1_0_een_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu_mm_ierat_mmucr1_we_q[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ierat_mmucr1_0_een_offset:ierat_mmucr1_0_een_offset + 4 - 1]), + .scout(sov_0[ierat_mmucr1_0_een_offset:ierat_mmucr1_0_een_offset + 4 - 1]), + .din(ierat_mmucr1_0_een_d), + .dout(ierat_mmucr1_0_een_q) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) derat_mmucr1_0_een_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_derat_mmucr1_we_q[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[derat_mmucr1_0_een_offset:derat_mmucr1_0_een_offset + 5 - 1]), + .scout(sov_0[derat_mmucr1_0_een_offset:derat_mmucr1_0_een_offset + 5 - 1]), + .din(derat_mmucr1_0_een_d), + .dout(derat_mmucr1_0_een_q) + ); + + +`ifdef MM_THREADS2 + tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) cp_mm_except_taken_t1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[cp_mm_except_taken_t1_offset:cp_mm_except_taken_t1_offset + 6 - 1]), + .scout(sov_0[cp_mm_except_taken_t1_offset:cp_mm_except_taken_t1_offset + 6 - 1]), + .din(cp_mm_except_taken_t1_d), + .dout(cp_mm_except_taken_t1_q) + ); + // cp_mm_except_taken + // 0 - thdid/val + // 1 - I=0/D=1 + // 2 - TLB miss + // 3 - Storage int (TLBI/PTfault) + // 4 - LRAT miss + // 5 - Mcheck + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_mas1_1_ts_error_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_mas1_1_ts_error_offset]), + .scout(sov_0[tlb_mas1_1_ts_error_offset]), + .din(tlb_mas1_1_ts_error_d), + .dout(tlb_mas1_1_ts_error_q) + ); + + tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_mas1_1_tid_error_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_mas1_1_tid_error_offset:tlb_mas1_1_tid_error_offset + `PID_WIDTH - 1]), + .scout(sov_0[tlb_mas1_1_tid_error_offset:tlb_mas1_1_tid_error_offset + `PID_WIDTH - 1]), + .din(tlb_mas1_1_tid_error_d), + .dout(tlb_mas1_1_tid_error_q) + ); + + tri_rlmreg_p #(.WIDTH(`EPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_mas2_1_epn_error_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_mas2_1_epn_error_offset:tlb_mas2_1_epn_error_offset + `EPN_WIDTH - 1]), + .scout(sov_0[tlb_mas2_1_epn_error_offset:tlb_mas2_1_epn_error_offset + `EPN_WIDTH - 1]), + .din(tlb_mas2_1_epn_error_d), + .dout(tlb_mas2_1_epn_error_q) + ); + + tri_rlmreg_p #(.WIDTH(`REAL_ADDR_WIDTH-12), .INIT(0), .NEEDS_SRESET(1)) tlb_lper_1_lpn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_lper_1_lpn_offset:tlb_lper_1_lpn_offset + `REAL_ADDR_WIDTH-12 - 1]), + .scout(sov_0[tlb_lper_1_lpn_offset:tlb_lper_1_lpn_offset + `REAL_ADDR_WIDTH-12 - 1]), + .din(tlb_lper_1_lpn_d), + .dout(tlb_lper_1_lpn_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) tlb_lper_1_lps_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_lper_1_lps_offset:tlb_lper_1_lps_offset + 4 - 1]), + .scout(sov_0[tlb_lper_1_lps_offset:tlb_lper_1_lps_offset + 4 - 1]), + .din(tlb_lper_1_lps_d), + .dout(tlb_lper_1_lps_q) + ); + + tri_rlmreg_p #(.WIDTH(9), .INIT(0), .NEEDS_SRESET(1)) tlb_mmucr1_1_een_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_mmucr1_1_een_offset:tlb_mmucr1_1_een_offset + 9 - 1]), + .scout(sov_0[tlb_mmucr1_1_een_offset:tlb_mmucr1_1_een_offset + 9 - 1]), + .din(tlb_mmucr1_1_een_d), + .dout(tlb_mmucr1_1_een_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ierat_mmucr1_1_een_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu_mm_ierat_mmucr1_we_q[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ierat_mmucr1_1_een_offset:ierat_mmucr1_1_een_offset + 4 - 1]), + .scout(sov_0[ierat_mmucr1_1_een_offset:ierat_mmucr1_1_een_offset + 4 - 1]), + .din(ierat_mmucr1_1_een_d), + .dout(ierat_mmucr1_1_een_q) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) derat_mmucr1_1_een_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_derat_mmucr1_we_q[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[derat_mmucr1_1_een_offset:derat_mmucr1_1_een_offset + 5 - 1]), + .scout(sov_0[derat_mmucr1_1_een_offset:derat_mmucr1_1_een_offset + 5 - 1]), + .din(derat_mmucr1_1_een_d), + .dout(derat_mmucr1_1_een_q) + ); + +`endif +`endif + + tri_rlmreg_p #(.WIDTH(4), .INIT(MMQ_SPR_CSWITCH_0TO3), .NEEDS_SRESET(1)) cswitch_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[cswitch_offset:cswitch_offset + 4 - 1]), + .scout(sov_0[cswitch_offset:cswitch_offset + 4 - 1]), + .din(cswitch_q), + .dout(cswitch_q) + ); + // cswitch0: 1=disable side affect of clearing I/D/TERRDET and EEN when reading mmucr1 + // cswitch1: 1=disable mmucr1.tlbwe_binv bit (make it look like it is reserved per dd1) + // cswitch2: reserved + // cswitch3: reserved + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) cat_emf_act_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[cat_emf_act_offset:cat_emf_act_offset + `MM_THREADS - 1]), + .scout(sov_1[cat_emf_act_offset:cat_emf_act_offset + `MM_THREADS - 1]), + .din(cat_emf_act_d), + .dout(cat_emf_act_q) + ); + + tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) spare_a_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spare_a_offset:spare_a_offset + 32 - 1]), + .scout(sov_0[spare_a_offset:spare_a_offset + 32 - 1]), + .din(spare_a_q), + .dout(spare_a_q) + ); + + tri_rlmreg_p #(.WIDTH(64), .INIT(0), .NEEDS_SRESET(1)) spare_b_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spare_b_offset:spare_b_offset + 64 - 1]), + .scout(sov_1[spare_b_offset:spare_b_offset + 64 - 1]), + .din(spare_b_q), + .dout(spare_b_q) + ); + + // non-scannable timing latches + tri_regk #(.WIDTH(18), .INIT(0), .NEEDS_SRESET(0)) iu_mm_ierat_mmucr0_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .sg(pc_sg_0), + .force_t(pc_func_slp_nsl_force), + .d_mode(lcb_d_mode_dc), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .thold_b(pc_func_slp_nsl_thold_0_b), + .scin(tri_regk_unused_scan[0:17]), + .scout(tri_regk_unused_scan[0:17]), + .din(iu_mm_ierat_mmucr0), + .dout(iu_mm_ierat_mmucr0_q) + ); + + tri_regk #(.WIDTH(18), .INIT(0), .NEEDS_SRESET(0)) xu_mm_derat_mmucr0_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .sg(pc_sg_0), + .force_t(pc_func_slp_nsl_force), + .d_mode(lcb_d_mode_dc), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .thold_b(pc_func_slp_nsl_thold_0_b), + .scin(tri_regk_unused_scan[18:35]), + .scout(tri_regk_unused_scan[18:35]), + .din(xu_mm_derat_mmucr0), + .dout(xu_mm_derat_mmucr0_q) + ); + + tri_regk #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(0)) iu_mm_ierat_mmucr1_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .sg(pc_sg_0), + .force_t(pc_func_slp_nsl_force), + .d_mode(lcb_d_mode_dc), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .thold_b(pc_func_slp_nsl_thold_0_b), + .scin(tri_regk_unused_scan[36:39]), + .scout(tri_regk_unused_scan[36:39]), + .din(iu_mm_ierat_mmucr1), + .dout(iu_mm_ierat_mmucr1_q) + ); + + tri_regk #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(0)) xu_mm_derat_mmucr1_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .sg(pc_sg_0), + .force_t(pc_func_slp_nsl_force), + .d_mode(lcb_d_mode_dc), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .thold_b(pc_func_slp_nsl_thold_0_b), + .scin(tri_regk_unused_scan[40:44]), + .scout(tri_regk_unused_scan[40:44]), + .din(xu_mm_derat_mmucr1), + .dout(xu_mm_derat_mmucr1_q) + ); + + tri_regk #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(0)) iu_mm_ierat_mmucr1_we_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .sg(pc_sg_0), + .force_t(pc_func_slp_nsl_force), + .d_mode(lcb_d_mode_dc), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .thold_b(pc_func_slp_nsl_thold_0_b), + .scin(tri_regk_unused_scan[45:45+`MM_THREADS-1]), + .scout(tri_regk_unused_scan[45:45+`MM_THREADS-1]), + .din(iu_mm_ierat_mmucr1_we_d), + .dout(iu_mm_ierat_mmucr1_we_q) + ); + + tri_regk #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(0)) xu_mm_derat_mmucr1_we_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .sg(pc_sg_0), + .force_t(pc_func_slp_nsl_force), + .d_mode(lcb_d_mode_dc), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .thold_b(pc_func_slp_nsl_thold_0_b), + .scin(tri_regk_unused_scan[45+`MM_THREADS:45+(2*`MM_THREADS)-1]), + .scout(tri_regk_unused_scan[45+`MM_THREADS:45+(2*`MM_THREADS)-1]), + .din(xu_mm_derat_mmucr1_we_d), + .dout(xu_mm_derat_mmucr1_we_q) + ); + + tri_regk #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(0)) iu_mm_ierat_mmucr0_we_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .sg(pc_sg_0), + .force_t(pc_func_slp_nsl_force), + .d_mode(lcb_d_mode_dc), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .thold_b(pc_func_slp_nsl_thold_0_b), + .scin(tri_regk_unused_scan[45+(2*`MM_THREADS):45+(3*`MM_THREADS)-1]), + .scout(tri_regk_unused_scan[45+(2*`MM_THREADS):45+(3*`MM_THREADS)-1]), + .din(iu_mm_ierat_mmucr0_we), + .dout(iu_mm_ierat_mmucr0_we_q) + ); + + tri_regk #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(0)) xu_mm_derat_mmucr0_we_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .sg(pc_sg_0), + .force_t(pc_func_slp_nsl_force), + .d_mode(lcb_d_mode_dc), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .thold_b(pc_func_slp_nsl_thold_0_b), + .scin(tri_regk_unused_scan[45+(3*`MM_THREADS):45+(4*`MM_THREADS)-1]), + .scout(tri_regk_unused_scan[45+(3*`MM_THREADS):45+(4*`MM_THREADS)-1]), + .din(xu_mm_derat_mmucr0_we), + .dout(xu_mm_derat_mmucr0_we_q) + ); + + //------------------------------------------------ + // scan only latches for boot config + // mmucr1, mmucr2, and mmucr3 also in boot config + //------------------------------------------------ + generate + if (`EXPAND_TYPE != 1) + begin : mpg_bcfg_gen + + tri_slat_scan #(.WIDTH(2), .INIT(BCFG_MMUCFG_VALUE), .RESET_INVERTS_SCAN(1'b1)) mmucfg_47to48_latch( + .vd(vdd), + .gd(gnd), + .dclk(lcb_dclk), + .lclk(lcb_lclk), + .scan_in(bsiv[mmucfg_offset:mmucfg_offset + 1]), + .scan_out(bsov[mmucfg_offset:mmucfg_offset + 1]), + .q(mmucfg_q[47:48]), + .q_b(mmucfg_q_b[47:48]) + ); + + tri_slat_scan #(.WIDTH(3), .INIT(BCFG_TLB0CFG_VALUE), .RESET_INVERTS_SCAN(1'b1)) tlb0cfg_45to47_latch( + .vd(vdd), + .gd(gnd), + .dclk(lcb_dclk), + .lclk(lcb_lclk), + .scan_in(bsiv[tlb0cfg_offset:tlb0cfg_offset + 2]), + .scan_out(bsov[tlb0cfg_offset:tlb0cfg_offset + 2]), + .q(tlb0cfg_q[45:47]), + .q_b(tlb0cfg_q_b[45:47]) + ); + + tri_slat_scan #(.WIDTH(16), .INIT(0), .RESET_INVERTS_SCAN(1'b1)) bcfg_spare_latch( + .vd(vdd), + .gd(gnd), + .dclk(lcb_dclk), + .lclk(lcb_lclk), + .scan_in(bsiv[bcfg_spare_offset:bcfg_spare_offset + 16 - 1]), + .scan_out(bsov[bcfg_spare_offset:bcfg_spare_offset + 16 - 1]), + .q(bcfg_spare_q), + .q_b(bcfg_spare_q_b) + ); + + // these terms in the absence of another lcbor component + // that drives the thold_b and force into the bcfg_lcb for slat's + assign pc_cfg_sl_thold_0_b = (~pc_cfg_sl_thold_0); + assign pc_cfg_sl_force = pc_sg_0; + + //------------------------------------------------ + // local clock buffer for boot config + //------------------------------------------------ + + tri_lcbs bcfg_lcb( + .vd(vdd), + .gd(gnd), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .nclk(nclk), + .force_t(pc_cfg_sl_force), + .thold_b(pc_cfg_sl_thold_0_b), + .dclk(lcb_dclk), + .lclk(lcb_lclk) + ); + + end + endgenerate + + generate + if (`EXPAND_TYPE == 1) + begin : fpga_bcfg_gen + + tri_rlmreg_p #(.WIDTH(2), .INIT(BCFG_MMUCFG_VALUE), .NEEDS_SRESET(1)) mmucfg_47to48_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_cfg_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_cfg_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(bsiv[mmucfg_offset:mmucfg_offset + 1]), + .scout(bsov[mmucfg_offset:mmucfg_offset + 1]), + .din(mmucfg_q[47:48]), + .dout(mmucfg_q[47:48]) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(BCFG_TLB0CFG_VALUE), .NEEDS_SRESET(1)) tlb0cfg_45to47_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_cfg_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_cfg_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(bsiv[tlb0cfg_offset:tlb0cfg_offset + 2]), + .scout(bsov[tlb0cfg_offset:tlb0cfg_offset + 2]), + .din(tlb0cfg_q[45:47]), + .dout(tlb0cfg_q[45:47]) + ); + + tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) bcfg_spare_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_cfg_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_cfg_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(bsiv[bcfg_spare_offset:bcfg_spare_offset + 16 - 1]), + .scout(bsov[bcfg_spare_offset:bcfg_spare_offset + 16 - 1]), + .din(bcfg_spare_q), + .dout(bcfg_spare_q) + ); + end + endgenerate + + // Latch counts + // 3319 + // spr_ctl_in_q 3 + // spr_etid_in_q 2 + // spr_addr_in_q 10 + // spr_data_in_q 64 79 + // spr_ctl_int_q 3 + // spr_etid_int_q 2 + // spr_addr_int_q 10 + // spr_data_int_q 64 79 + // spr_ctl_out_q 3 + // spr_etid_out_q 2 + // spr_addr_out_q 10 + // spr_data_out_q 64 79 + // lper_ 0:3 _alpn_q 30 x 4 + // lper_ 0:3 _lps_q 4 x 4 136 + // pid 0:3 _q 14 x 4 + // mmucr0_ 0:3 _q 20 x 4 + // mmucr1_q 32 + // mmucr2_q 32 + // mmucr3_ 0:3 _q 15 x 4 + // lpidr_q 8 + // mmucsr0_tlb0fi_q 1 269 + // mas0__atsel_q 1 x 4 : std_ulogic; + // mas0__esel_q 3 x 4 : std_ulogic_vector(0 to 2); + // mas0__hes_q 1 x 4 : std_ulogic; + // mas0__wq_q 2 x 4 : std_ulogic_vector(0 to 1); + // mas1__v_q 1 x 4 : std_ulogic; + // mas1__iprot_q 1 x 4 : std_ulogic; + // mas1__tid_q 14 x 4 : std_ulogic_vector(0 to 13); + // mas1__ind_q 1 x 4 : std_ulogic; + // mas1__ts_q 1 x 4 : std_ulogic; + // mas1__tsize_q 4 x 4 : std_ulogic_vector(0 to 3); + // mas2__epn_q 52 x 4 : std_ulogic_vector(64-`SPR_DATA_WIDTH to 51); + // mas2__wimge_q 5 x 4 : std_ulogic_vector(0 to 4); + // mas3__rpnl_q 21 x 4 : std_ulogic_vector(32 to 52); + // mas3__ubits_q 4 x 4 : std_ulogic_vector(0 to 3); + // mas3__usxwr_q 6 x 4 : std_ulogic_vector(0 to 5); + // mas4__indd_q 1 x 4 : std_ulogic; + // mas4__tsized_q 4 x 4 : std_ulogic_vector(0 to 3); + // mas4__wimged_q 5 x 4 : std_ulogic_vector(0 to 4); + // mas5__sgs_q 1 x 4 : std_ulogic; + // mas5__slpid_q 8 x 4 : std_ulogic_vector(0 to 7); + // mas6__spid_q 14 x 4 : std_ulogic_vector(0 to 13); + // mas6__isize_q 4 x 4 : std_ulogic_vector(0 to 3); + // mas6__sind_q 1 x 4 : std_ulogic; + // mas6__sas_q 1 x 4 : std_ulogic; + // mas7__rpnu_q 10 x 4 : std_ulogic_vector(22 to 31); + // mas8__tgs_q 1 x 4 : std_ulogic; + // mas8__vf_q 1 x 4 : std_ulogic; + // mas8__tlpid_q 8 x 4 : std_ulogic_vector(0 to 7); + // subtotal 176 x 4 = 704 + //-------------------------------------------------------------- + // total 1346 + //------------------------------------------------ + //------------------------------------------------ + // thold/sg latches + //------------------------------------------------ + + tri_plat #(.WIDTH(7)) perv_2to1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ccflush_dc), + .din( {pc_func_sl_thold_2, pc_func_slp_sl_thold_2, pc_cfg_sl_thold_2, pc_cfg_slp_sl_thold_2, pc_func_slp_nsl_thold_2, pc_sg_2, pc_fce_2} ), + .q( {pc_func_sl_thold_1, pc_func_slp_sl_thold_1, pc_cfg_sl_thold_1, pc_cfg_slp_sl_thold_1, pc_func_slp_nsl_thold_1, pc_sg_1, pc_fce_1} ) + ); + + tri_plat #(.WIDTH(7)) perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ccflush_dc), + .din( {pc_func_sl_thold_1, pc_func_slp_sl_thold_1, pc_cfg_sl_thold_1, pc_cfg_slp_sl_thold_1, pc_func_slp_nsl_thold_1, pc_sg_1, pc_fce_1} ), + .q( {pc_func_sl_thold_0, pc_func_slp_sl_thold_0, pc_cfg_sl_thold_0, pc_cfg_slp_sl_thold_0, pc_func_slp_nsl_thold_0, pc_sg_0, pc_fce_0} ) + ); + + tri_lcbor perv_lcbor_func_sl( + .clkoff_b(lcb_clkoff_dc_b), + .thold(pc_func_sl_thold_0), + .sg(pc_sg_0), + .act_dis(lcb_act_dis_dc), + .force_t(pc_func_sl_force), + .thold_b(pc_func_sl_thold_0_b) + ); + + tri_lcbor perv_lcbor_func_slp_sl( + .clkoff_b(lcb_clkoff_dc_b), + .thold(pc_func_slp_sl_thold_0), + .sg(pc_sg_0), + .act_dis(lcb_act_dis_dc), + .force_t(pc_func_slp_sl_force), + .thold_b(pc_func_slp_sl_thold_0_b) + ); + + tri_lcbor perv_lcbor_cfg_slp_sl( + .clkoff_b(lcb_clkoff_dc_b), + .thold(pc_cfg_slp_sl_thold_0), + .sg(pc_sg_0), + .act_dis(lcb_act_dis_dc), + .force_t(pc_cfg_slp_sl_force), + .thold_b(pc_cfg_slp_sl_thold_0_b) + ); + + tri_lcbor perv_lcbor_func_slp_nsl( + .clkoff_b(lcb_clkoff_dc_b), + .thold(pc_func_slp_nsl_thold_0), + .sg(pc_fce_0), + .act_dis(tidn), + .force_t(pc_func_slp_nsl_force), + .thold_b(pc_func_slp_nsl_thold_0_b) + ); + + //--------------------------------------------------------------------- + // Scan + //--------------------------------------------------------------------- + assign siv_0[0:scan_right_0] = {sov_0[1:scan_right_0], ac_func_scan_in[0]}; + assign ac_func_scan_out[0] = sov_0[0]; + assign siv_1[0:scan_right_1] = {sov_1[1:scan_right_1], ac_func_scan_in[1]}; + assign ac_func_scan_out[1] = sov_1[0]; + assign bsiv[0:boot_scan_right] = {bsov[1:boot_scan_right], ac_bcfg_scan_in}; + assign ac_bcfg_scan_out = bsov[0]; + + function Eq; + input a, b; + reg result; + begin + if (a == b) + begin + result = 1'b1; + end + else + begin + result = 1'b0; + end + Eq = result; + end + endfunction + +endmodule diff --git a/dev/verilog/work/mmq_tlb_cmp.v b/dev/verilog/work/mmq_tlb_cmp.v new file mode 100755 index 0000000..aa2bc72 --- /dev/null +++ b/dev/verilog/work/mmq_tlb_cmp.v @@ -0,0 +1,6849 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +//******************************************************************** +//* TITLE: Memory Management Unit TLB Compare Logic +//* NAME: mmq_tlb_cmp.v +//********************************************************************* + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" +`include "mmu_a2o.vh" + +module mmq_tlb_cmp( + inout vdd, + inout gnd, + (* pin_data ="PIN_FUNCTION=/G_CLK/" *) + input [0:`NCLK_WIDTH-1] nclk, + + input tc_ccflush_dc, + input tc_scan_dis_dc_b, + input tc_scan_diag_dc, + input tc_lbist_en_dc, + input lcb_d_mode_dc, + input lcb_clkoff_dc_b, + input lcb_act_dis_dc, + input [0:4] lcb_mpw1_dc_b, + input lcb_mpw2_dc_b, + input [0:4] lcb_delay_lclkr_dc, + input pc_sg_2, + input pc_func_sl_thold_2, + input pc_func_slp_sl_thold_2, + input pc_func_slp_nsl_thold_2, + input pc_fce_2, + + (* pin_data ="PIN_FUNCTION=/SCAN_IN/" *) + input [0:2] ac_func_scan_in, + (* pin_data ="PIN_FUNCTION=/SCAN_OUT/" *) + output [0:2] ac_func_scan_out, + + input xu_mm_ccr2_notlb_b, + input [0:`MM_THREADS-1] xu_mm_spr_epcr_dmiuh, + input [0:`MM_THREADS-1] xu_mm_epcr_dgtmi, + input [0:`MM_THREADS-1] xu_mm_msr_gs, + input [0:`MM_THREADS-1] xu_mm_msr_pr, + input xu_mm_xucr4_mmu_mchk_q, + + input [0:`LPID_WIDTH-1] lpidr, + input [10:18] mmucr1, + input [64-`MMUCR3_WIDTH:63] mmucr3_0, + input [1:3] tstmode4k_0, +`ifdef MM_THREADS2 + input [64-`MMUCR3_WIDTH:63] mmucr3_1, + input [1:3] tstmode4k_1, +`endif + output [0:4] mm_iu_ierat_rel_val, + output [0:`ERAT_REL_DATA_WIDTH-1] mm_iu_ierat_rel_data, + output [0:4] mm_xu_derat_rel_val, + output [0:`ERAT_REL_DATA_WIDTH-1] mm_xu_derat_rel_data, + output [0:6] tlb_cmp_ierat_dup_val, + output [0:6] tlb_cmp_derat_dup_val, + output [0:1] tlb_cmp_erat_dup_wait, + input [0:`PID_WIDTH-1] ierat_req0_pid, + input ierat_req0_as, + input ierat_req0_gs, + input [0:`EPN_WIDTH-1] ierat_req0_epn, + input [0:`THDID_WIDTH-1] ierat_req0_thdid, + input ierat_req0_valid, + input ierat_req0_nonspec, + input [0:`PID_WIDTH-1] ierat_req1_pid, + input ierat_req1_as, + input ierat_req1_gs, + input [0:`EPN_WIDTH-1] ierat_req1_epn, + input [0:`THDID_WIDTH-1] ierat_req1_thdid, + input ierat_req1_valid, + input ierat_req1_nonspec, + input [0:`PID_WIDTH-1] ierat_req2_pid, + input ierat_req2_as, + input ierat_req2_gs, + input [0:`EPN_WIDTH-1] ierat_req2_epn, + input [0:`THDID_WIDTH-1] ierat_req2_thdid, + input ierat_req2_valid, + input ierat_req2_nonspec, + input [0:`PID_WIDTH-1] ierat_req3_pid, + input ierat_req3_as, + input ierat_req3_gs, + input [0:`EPN_WIDTH-1] ierat_req3_epn, + input [0:`THDID_WIDTH-1] ierat_req3_thdid, + input ierat_req3_valid, + input ierat_req3_nonspec, + input [0:`PID_WIDTH-1] ierat_iu4_pid, + input ierat_iu4_gs, + input ierat_iu4_as, + input [0:`EPN_WIDTH-1] ierat_iu4_epn, + input [0:`THDID_WIDTH-1] ierat_iu4_thdid, + input ierat_iu4_valid, + input [0:`LPID_WIDTH-1] derat_req0_lpid, + input [0:`PID_WIDTH-1] derat_req0_pid, + input derat_req0_as, + input derat_req0_gs, + input [0:`EPN_WIDTH-1] derat_req0_epn, + input [0:`THDID_WIDTH-1] derat_req0_thdid, + input [0:`EMQ_ENTRIES-1] derat_req0_emq, + input derat_req0_valid, + input [0:`LPID_WIDTH-1] derat_req1_lpid, + input [0:`PID_WIDTH-1] derat_req1_pid, + input derat_req1_as, + input derat_req1_gs, + input [0:`EPN_WIDTH-1] derat_req1_epn, + input [0:`THDID_WIDTH-1] derat_req1_thdid, + input [0:`EMQ_ENTRIES-1] derat_req1_emq, + input derat_req1_valid, + input [0:`LPID_WIDTH-1] derat_req2_lpid, + input [0:`PID_WIDTH-1] derat_req2_pid, + input derat_req2_as, + input derat_req2_gs, + input [0:`EPN_WIDTH-1] derat_req2_epn, + input [0:`THDID_WIDTH-1] derat_req2_thdid, + input [0:`EMQ_ENTRIES-1] derat_req2_emq, + input derat_req2_valid, + input [0:`LPID_WIDTH-1] derat_req3_lpid, + input [0:`PID_WIDTH-1] derat_req3_pid, + input derat_req3_as, + input derat_req3_gs, + input [0:`EPN_WIDTH-1] derat_req3_epn, + input [0:`THDID_WIDTH-1] derat_req3_thdid, + input [0:`EMQ_ENTRIES-1] derat_req3_emq, + input derat_req3_valid, + input [0:`LPID_WIDTH-1] derat_ex5_lpid, + input [0:`PID_WIDTH-1] derat_ex5_pid, + input derat_ex5_gs, + input derat_ex5_as, + input [0:`EPN_WIDTH-1] derat_ex5_epn, + input [0:`THDID_WIDTH-1] derat_ex5_thdid, + input derat_ex5_valid, + input [0:`TLB_TAG_WIDTH-1] tlb_tag2, + input [0:`TLB_ADDR_WIDTH-1] tlb_addr2, + input [0:1] ex6_illeg_instr, + input ierat_req_taken, + input derat_req_taken, + input ptereload_req_taken, + input [0:1] tlb_tag0_type, + input [64-`REAL_ADDR_WIDTH:51] lrat_tag3_lpn, + input [64-`REAL_ADDR_WIDTH:51] lrat_tag3_rpn, + input [0:3] lrat_tag3_hit_status, + input [0:2] lrat_tag3_hit_entry, + input [64-`REAL_ADDR_WIDTH:51] lrat_tag4_lpn, + input [64-`REAL_ADDR_WIDTH:51] lrat_tag4_rpn, + input [0:3] lrat_tag4_hit_status, + input [0:2] lrat_tag4_hit_entry, + input [0:15] lru_dataout, + input [0:`TLB_WAY_WIDTH*`TLB_WAYS-1] tlb_dataout, + output [0:`TLB_WAY_WIDTH-1] tlb_dataina, + output [0:`TLB_WAY_WIDTH-1] tlb_datainb, + output [0:`TLB_ADDR_WIDTH-1] lru_wr_addr, + output [0:15] lru_write, + output [0:15] lru_datain, + output [0:15] lru_tag4_dataout, + output [0:2] tlb_tag4_esel, + output [0:1] tlb_tag4_wq, + output [0:1] tlb_tag4_is, + output tlb_tag4_gs, + output tlb_tag4_pr, + output tlb_tag4_hes, + output tlb_tag4_atsel, + output tlb_tag4_pt, + output tlb_tag4_cmp_hit, + output tlb_tag4_way_ind, + output tlb_tag4_ptereload, + output tlb_tag4_endflag, + output tlb_tag4_parerr, + output tlb_tag4_nonspec, + output [0:`TLB_ADDR_WIDTH-1] tlb_addr4, + output [0:`TLB_WAYS-1] tlb_tag4_parerr_write, + output tlb_tag5_parerr_zeroize, + output [0:`MM_THREADS-1] tlb_tag5_except, + output [0:`ITAG_SIZE_ENC-1] tlb_tag4_itag, + output [0:`ITAG_SIZE_ENC-1] tlb_tag5_itag, + output [0:`EMQ_ENTRIES-1] tlb_tag5_emq, + input mmucfg_twc, + input mmucfg_lrat, + input tlb0cfg_pt, + input tlb0cfg_gtwe, + input tlb0cfg_ind, + input [0:4] mas2_0_wimge, + input [32:52] mas3_0_rpnl, + input [0:3] mas3_0_ubits, + input [0:5] mas3_0_usxwr, + input [22:31] mas7_0_rpnu, + input mas8_0_vf, +`ifdef MM_THREADS2 + input [0:4] mas2_1_wimge, + input [32:52] mas3_1_rpnl, + input [0:3] mas3_1_ubits, + input [0:5] mas3_1_usxwr, + input [22:31] mas7_1_rpnu, + input mas8_1_vf, +`endif + output [0:2] tlb_mas0_esel, + output tlb_mas1_v, + output tlb_mas1_iprot, + output [0:`PID_WIDTH-1] tlb_mas1_tid, + output [0:`PID_WIDTH-1] tlb_mas1_tid_error, + output tlb_mas1_ind, + output tlb_mas1_ts, + output tlb_mas1_ts_error, + output [0:3] tlb_mas1_tsize, + output [0:`EPN_WIDTH-1] tlb_mas2_epn, + output [0:`EPN_WIDTH-1] tlb_mas2_epn_error, + output [0:4] tlb_mas2_wimge, + output [32:51] tlb_mas3_rpnl, + output [0:3] tlb_mas3_ubits, + output [0:5] tlb_mas3_usxwr, + output [22:31] tlb_mas7_rpnu, + output tlb_mas8_tgs, + output tlb_mas8_vf, + output [0:7] tlb_mas8_tlpid, + output [0:8] tlb_mmucr1_een, + output tlb_mmucr1_we, + output [0:`THDID_WIDTH-1] tlb_mmucr3_thdid, + output tlb_mmucr3_resvattr, + output [0:1] tlb_mmucr3_wlc, + output [0:`CLASS_WIDTH-1] tlb_mmucr3_class, + output [0:`EXTCLASS_WIDTH-1] tlb_mmucr3_extclass, + output [0:1] tlb_mmucr3_rc, + output tlb_mmucr3_x, + output tlb_mas_tlbre, + output tlb_mas_tlbsx_hit, + output tlb_mas_tlbsx_miss, + output tlb_mas_dtlb_error, + output tlb_mas_itlb_error, + output [0:`MM_THREADS-1] tlb_mas_thdid, + output tlb_htw_req_valid, + output [0:`TLB_TAG_WIDTH-1] tlb_htw_req_tag, + output [`TLB_WORD_WIDTH:`TLB_WAY_WIDTH-1] tlb_htw_req_way, + output tlbwe_back_inv_valid, + output [0:`MM_THREADS-1] tlbwe_back_inv_thdid, + output [52-`EPN_WIDTH:51] tlbwe_back_inv_addr, + output [0:34] tlbwe_back_inv_attr, + + input [0:`PTE_WIDTH-1] ptereload_req_pte_lat, + input [0:`MM_THREADS-1] tlb_ctl_tag2_flush, + input [0:`MM_THREADS-1] tlb_ctl_tag3_flush, + input [0:`MM_THREADS-1] tlb_ctl_tag4_flush, + input [0:`MM_THREADS-1] tlb_resv_match_vec, + + output [0:`MM_THREADS-1] mm_xu_eratmiss_done, + output [0:`MM_THREADS-1] mm_xu_tlb_miss, + output [0:`MM_THREADS-1] mm_xu_tlb_inelig, + output [0:`MM_THREADS-1] mm_xu_lrat_miss, + output [0:`MM_THREADS-1] mm_xu_pt_fault, + output [0:`MM_THREADS-1] mm_xu_hv_priv, + output [0:`MM_THREADS-1] mm_xu_esr_pt, + output [0:`MM_THREADS-1] mm_xu_esr_data, + output [0:`MM_THREADS-1] mm_xu_esr_epid, + output [0:`MM_THREADS-1] mm_xu_esr_st, + output [0:`MM_THREADS-1] mm_xu_cr0_eq, + output [0:`MM_THREADS-1] mm_xu_cr0_eq_valid, + output [0:`MM_THREADS-1] mm_xu_tlb_multihit_err, + output [0:`MM_THREADS-1] mm_xu_tlb_par_err, + output [0:`MM_THREADS-1] mm_xu_lru_par_err, + + output mm_xu_ord_tlb_multihit, + output mm_xu_ord_tlb_par_err, + output mm_xu_ord_lru_par_err, + + output mm_xu_tlb_miss_ored, + output mm_xu_lrat_miss_ored, + output mm_xu_tlb_inelig_ored, + output mm_xu_pt_fault_ored, + output mm_xu_hv_priv_ored, + output mm_xu_cr0_eq_ored, + output mm_xu_cr0_eq_valid_ored, + output mm_pc_tlb_multihit_err_ored, + output mm_pc_tlb_par_err_ored, + output mm_pc_lru_par_err_ored, + input [9:16] tlb_delayed_act, + output [0:9] tlb_cmp_perf_event_t0, + output [0:9] tlb_cmp_perf_event_t1, + output [0:1] tlb_cmp_perf_state, + output tlb_cmp_perf_miss_direct, + output tlb_cmp_perf_hit_direct, + output tlb_cmp_perf_hit_indirect, + output tlb_cmp_perf_hit_first_page, + output tlb_cmp_perf_ptereload, + output tlb_cmp_perf_ptereload_noexcep, + output tlb_cmp_perf_lrat_request, + output tlb_cmp_perf_lrat_miss, + output tlb_cmp_perf_pt_fault, + output tlb_cmp_perf_pt_inelig, + output [0:`TLB_TAG_WIDTH-1] tlb_cmp_dbg_tag4, + output [0:`TLB_WAYS] tlb_cmp_dbg_tag4_wayhit, + output [0:`TLB_ADDR_WIDTH-1] tlb_cmp_dbg_addr4, + output [0:`TLB_WAY_WIDTH-1] tlb_cmp_dbg_tag4_way, + output [0:4] tlb_cmp_dbg_tag4_parerr, + output [0:11] tlb_cmp_dbg_tag4_lru_dataout_q, + output [0:`TLB_WAY_WIDTH-1] tlb_cmp_dbg_tag5_tlb_datain_q, + output [0:11] tlb_cmp_dbg_tag5_lru_datain_q, + output tlb_cmp_dbg_tag5_lru_write, + output tlb_cmp_dbg_tag5_any_exception, + output [0:3] tlb_cmp_dbg_tag5_except_type_q, + output [0:1] tlb_cmp_dbg_tag5_except_thdid_q, + output [0:9] tlb_cmp_dbg_tag5_erat_rel_val, + output [0:131] tlb_cmp_dbg_tag5_erat_rel_data, + output [0:19] tlb_cmp_dbg_erat_dup_q, + output [0:8] tlb_cmp_dbg_addr_enable, + output tlb_cmp_dbg_pgsize_enable, + output tlb_cmp_dbg_class_enable, + output [0:1] tlb_cmp_dbg_extclass_enable, + output [0:1] tlb_cmp_dbg_state_enable, + output tlb_cmp_dbg_thdid_enable, + output tlb_cmp_dbg_pid_enable, + output tlb_cmp_dbg_lpid_enable, + output tlb_cmp_dbg_ind_enable, + output tlb_cmp_dbg_iprot_enable, + output tlb_cmp_dbg_way0_entry_v, + output tlb_cmp_dbg_way0_addr_match, + output tlb_cmp_dbg_way0_pgsize_match, + output tlb_cmp_dbg_way0_class_match, + output tlb_cmp_dbg_way0_extclass_match, + output tlb_cmp_dbg_way0_state_match, + output tlb_cmp_dbg_way0_thdid_match, + output tlb_cmp_dbg_way0_pid_match, + output tlb_cmp_dbg_way0_lpid_match, + output tlb_cmp_dbg_way0_ind_match, + output tlb_cmp_dbg_way0_iprot_match, + output tlb_cmp_dbg_way1_entry_v, + output tlb_cmp_dbg_way1_addr_match, + output tlb_cmp_dbg_way1_pgsize_match, + output tlb_cmp_dbg_way1_class_match, + output tlb_cmp_dbg_way1_extclass_match, + output tlb_cmp_dbg_way1_state_match, + output tlb_cmp_dbg_way1_thdid_match, + output tlb_cmp_dbg_way1_pid_match, + output tlb_cmp_dbg_way1_lpid_match, + output tlb_cmp_dbg_way1_ind_match, + output tlb_cmp_dbg_way1_iprot_match, + output tlb_cmp_dbg_way2_entry_v, + output tlb_cmp_dbg_way2_addr_match, + output tlb_cmp_dbg_way2_pgsize_match, + output tlb_cmp_dbg_way2_class_match, + output tlb_cmp_dbg_way2_extclass_match, + output tlb_cmp_dbg_way2_state_match, + output tlb_cmp_dbg_way2_thdid_match, + output tlb_cmp_dbg_way2_pid_match, + output tlb_cmp_dbg_way2_lpid_match, + output tlb_cmp_dbg_way2_ind_match, + output tlb_cmp_dbg_way2_iprot_match, + output tlb_cmp_dbg_way3_entry_v, + output tlb_cmp_dbg_way3_addr_match, + output tlb_cmp_dbg_way3_pgsize_match, + output tlb_cmp_dbg_way3_class_match, + output tlb_cmp_dbg_way3_extclass_match, + output tlb_cmp_dbg_way3_state_match, + output tlb_cmp_dbg_way3_thdid_match, + output tlb_cmp_dbg_way3_pid_match, + output tlb_cmp_dbg_way3_lpid_match, + output tlb_cmp_dbg_way3_ind_match, + output tlb_cmp_dbg_way3_iprot_match + +); + + parameter MMQ_TLB_CMP_CSWITCH_0TO7 = 0; + + parameter MMU_Mode_Value = 1'b0; + parameter [0:1] TlbSel_Tlb = 2'b00; + parameter [0:1] TlbSel_IErat = 2'b10; + parameter [0:1] TlbSel_DErat = 2'b11; + parameter [0:2] ERAT_PgSize_1GB = 3'b110; + parameter [0:2] ERAT_PgSize_16MB = 3'b111; + parameter [0:2] ERAT_PgSize_1MB = 3'b101; + parameter [0:2] ERAT_PgSize_64KB = 3'b011; + parameter [0:2] ERAT_PgSize_4KB = 3'b001; + parameter [0:3] TLB_PgSize_1GB = 4'b1010; + parameter [0:3] TLB_PgSize_16MB = 4'b0111; + parameter [0:3] TLB_PgSize_1MB = 4'b0101; + parameter [0:3] TLB_PgSize_64KB = 4'b0011; + parameter [0:3] TLB_PgSize_4KB = 4'b0001; + // reserved for indirect entries + parameter [0:2] ERAT_PgSize_256MB = 3'b100; + parameter [0:3] TLB_PgSize_256MB = 4'b1001; + + // mmucr1 bits + parameter pos_tlb_pei = 10; + parameter pos_lru_pei = 11; + parameter pos_ictid = 12; + parameter pos_ittid = 13; + parameter pos_dctid = 14; + parameter pos_dttid = 15; + parameter pos_dccd = 16; + parameter pos_tlbwe_binv = 17; + parameter pos_tlbi_msb = 18; + parameter pos_tlbi_rej = 19; + + + parameter tlb_way0_offset = 0; + parameter tlb_way1_offset = tlb_way0_offset + `TLB_WAY_WIDTH; + parameter tlb_way0_cmpmask_offset = tlb_way1_offset + `TLB_WAY_WIDTH; + parameter tlb_way1_cmpmask_offset = tlb_way0_cmpmask_offset + 5; + parameter tlb_way0_xbitmask_offset = tlb_way1_cmpmask_offset + 5; + parameter tlb_way1_xbitmask_offset = tlb_way0_xbitmask_offset + 5; + parameter tlb_tag3_cmpmask_offset = tlb_way1_xbitmask_offset + 5; + parameter tlb_tag3_clone1_offset = tlb_tag3_cmpmask_offset + 5; + parameter tlb_tag4_way_offset = tlb_tag3_clone1_offset + `TLB_TAG_WIDTH; + parameter tlb_tag4_way_rw_offset = tlb_tag4_way_offset + `TLB_WAY_WIDTH; + parameter tlb_dataina_offset = tlb_tag4_way_rw_offset + `TLB_WAY_WIDTH; + parameter tlb_erat_rel_offset = tlb_dataina_offset + `TLB_WAY_WIDTH; + parameter mmucr1_offset = tlb_erat_rel_offset + 132; + parameter spare_a_offset = mmucr1_offset + 9; + parameter scan_right_0 = spare_a_offset + 16 - 1; + parameter tlb_way2_offset = 0; + parameter tlb_way3_offset = tlb_way2_offset + `TLB_WAY_WIDTH; + parameter tlb_way2_cmpmask_offset = tlb_way3_offset + `TLB_WAY_WIDTH; + parameter tlb_way3_cmpmask_offset = tlb_way2_cmpmask_offset + 5; + parameter tlb_way2_xbitmask_offset = tlb_way3_cmpmask_offset + 5; + parameter tlb_way3_xbitmask_offset = tlb_way2_xbitmask_offset + 5; + parameter tlb_tag3_clone2_offset = tlb_way3_xbitmask_offset + 5; + parameter tlb_tag3_cmpmask_clone_offset = tlb_tag3_clone2_offset + `TLB_TAG_WIDTH; + parameter tlb_erat_rel_clone_offset = tlb_tag3_cmpmask_clone_offset + 5; + parameter tlb_tag4_way_clone_offset = tlb_erat_rel_clone_offset + 132; + parameter tlb_tag4_way_rw_clone_offset = tlb_tag4_way_clone_offset + `TLB_WAY_WIDTH; + parameter tlb_datainb_offset = tlb_tag4_way_rw_clone_offset + `TLB_WAY_WIDTH; + parameter mmucr1_clone_offset = tlb_datainb_offset + `TLB_WAY_WIDTH; + parameter spare_b_offset = mmucr1_clone_offset + 9; + parameter scan_right_1 = spare_b_offset + 16 - 1; + parameter tlb_tag3_offset = 0; + parameter tlb_addr3_offset = tlb_tag3_offset + `TLB_TAG_WIDTH; + parameter lru_tag3_dataout_offset = tlb_addr3_offset + `TLB_ADDR_WIDTH; + parameter tlb_tag4_offset = lru_tag3_dataout_offset + 16; + parameter tlb_tag4_wayhit_offset = tlb_tag4_offset + `TLB_TAG_WIDTH; + parameter tlb_addr4_offset = tlb_tag4_wayhit_offset + `TLB_WAYS + 1; + parameter lru_tag4_dataout_offset = tlb_addr4_offset + `TLB_ADDR_WIDTH; + parameter tlbwe_tag4_back_inv_offset = lru_tag4_dataout_offset + 16; + parameter tlbwe_tag4_back_inv_attr_offset = tlbwe_tag4_back_inv_offset + 2 + 1; + parameter tlb_erat_val_offset = tlbwe_tag4_back_inv_attr_offset + 2; + parameter tlb_erat_dup_offset = tlb_erat_val_offset + 2 * `THDID_WIDTH + 2; + parameter lru_write_offset = tlb_erat_dup_offset + 2 * `THDID_WIDTH + 14; + parameter lru_wr_addr_offset = lru_write_offset + `LRU_WIDTH; + parameter lru_datain_offset = lru_wr_addr_offset + `TLB_ADDR_WIDTH; + parameter eratmiss_done_offset = lru_datain_offset + `LRU_WIDTH; + parameter tlb_miss_offset = eratmiss_done_offset + 2; + parameter tlb_inelig_offset = tlb_miss_offset + 2; + parameter lrat_miss_offset = tlb_inelig_offset + 2; + parameter pt_fault_offset = lrat_miss_offset + 2; + parameter hv_priv_offset = pt_fault_offset + 2; + parameter tlb_tag5_except_offset = hv_priv_offset + 2; + parameter lru_update_clear_enab_offset = tlb_tag5_except_offset + 2; + parameter tlb_tag5_parerr_zeroize_offset = lru_update_clear_enab_offset + 1; + parameter mm_xu_ord_par_mhit_err_offset = tlb_tag5_parerr_zeroize_offset + 1; + parameter tlb_dsi_offset = mm_xu_ord_par_mhit_err_offset + 3; + parameter tlb_isi_offset = tlb_dsi_offset + 2; + parameter esr_pt_offset = tlb_isi_offset + 2; + parameter esr_data_offset = esr_pt_offset + 2; + parameter esr_epid_offset = esr_data_offset + 2; + parameter esr_st_offset = esr_epid_offset + 2; + parameter cr0_eq_offset = esr_st_offset + 2; + parameter cr0_eq_valid_offset = cr0_eq_offset + 2; + parameter tlb_multihit_err_offset = cr0_eq_valid_offset + 2; + parameter tag4_parerr_offset = tlb_multihit_err_offset + 2; + parameter tlb_par_err_offset = tag4_parerr_offset + `TLB_WAYS + 1; + parameter lru_par_err_offset = tlb_par_err_offset + 2; + parameter tlb_tag5_itag_offset = lru_par_err_offset + 2; + parameter tlb_tag5_emq_offset = tlb_tag5_itag_offset + `ITAG_SIZE_ENC; + parameter tlb_tag5_perf_offset = tlb_tag5_emq_offset + `EMQ_ENTRIES; + parameter cswitch_offset = tlb_tag5_perf_offset + 8; + parameter spare_c_offset = cswitch_offset + 8; + parameter scan_right_2 = spare_c_offset + 16 - 1; + +`ifdef MM_THREADS2 + parameter BUGSP_MM_THREADS = 2; +`else + parameter BUGSP_MM_THREADS = 1; +`endif + + //tlb_tag3_d <= ( 0:51 epn & + // 52:65 pid & + // 66:67 IS & + // 68:69 Class & + // 70:73 state (pr,gs,as,cm) & + // 74:77 thdid & + // 78:81 size & + // 82:83 derat_miss/ierat_miss & + // 84:85 tlbsx/tlbsrx & + // 86:87 inval_snoop/tlbre & + // 88:89 tlbwe/ptereload & + // 90:97 lpid & + // 98 indirect + // 99 atsel & + // 100:102 esel & + // 103:105 hes/wq(0:1) & + // 106:107 lrat/pt & + // 108 record form + // 109 endflag + + // derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload + + // state: 0:pr 1:gs 2:as 3:cm + + (* NO_MODIFICATION="TRUE" *) + wire [1:170] LRU_UPDATE_DATA_PT; + (* NO_MODIFICATION="TRUE" *) + wire [0:2] lru_update_data; + (* NO_MODIFICATION="TRUE" *) + wire lru_update_data_enab; + (* NO_MODIFICATION="TRUE" *) + wire lru_update_clear_enab; + (* NO_MODIFICATION="TRUE" *) + wire tlb_tag4_parerr_zeroize; + wire tlb_tag5_parerr_zeroize_q; + + // Latch signals + // tag3 phase + (* NO_MODIFICATION="TRUE" *) + wire [0:`TLB_WAY_WIDTH-1] tlb_way0_d; + (* NO_MODIFICATION="TRUE" *) + wire [0:`TLB_WAY_WIDTH-1] tlb_way0_q; + (* NO_MODIFICATION="TRUE" *) + wire [0:`TLB_WAY_WIDTH-1] tlb_way1_d; + (* NO_MODIFICATION="TRUE" *) + wire [0:`TLB_WAY_WIDTH-1] tlb_way1_q; + (* NO_MODIFICATION="TRUE" *) + wire [0:`TLB_WAY_WIDTH-1] tlb_way2_d; + (* NO_MODIFICATION="TRUE" *) + wire [0:`TLB_WAY_WIDTH-1] tlb_way2_q; + (* NO_MODIFICATION="TRUE" *) + wire [0:`TLB_WAY_WIDTH-1] tlb_way3_d; + (* NO_MODIFICATION="TRUE" *) + wire [0:`TLB_WAY_WIDTH-1] tlb_way3_q; + (* NO_MODIFICATION="TRUE" *) + wire [0:`TLB_TAG_WIDTH-1] tlb_tag3_d; + (* NO_MODIFICATION="TRUE" *) + wire [0:`TLB_TAG_WIDTH-1] tlb_tag3_q; + (* NO_MODIFICATION="TRUE" *) + wire [0:`TLB_TAG_WIDTH-1] tlb_tag3_clone1_d; + (* NO_MODIFICATION="TRUE" *) + wire [0:`TLB_TAG_WIDTH-1] tlb_tag3_clone1_q; + (* NO_MODIFICATION="TRUE" *) + wire [0:`TLB_TAG_WIDTH-1] tlb_tag3_clone2_d; + (* NO_MODIFICATION="TRUE" *) + wire [0:`TLB_TAG_WIDTH-1] tlb_tag3_clone2_q; + (* NO_MODIFICATION="TRUE" *) + wire [0:`TLB_ADDR_WIDTH-1] tlb_addr3_d; + (* NO_MODIFICATION="TRUE" *) + wire [0:`TLB_ADDR_WIDTH-1] tlb_addr3_q; + (* NO_MODIFICATION="TRUE" *) + wire [0:15] lru_tag3_dataout_d; + (* NO_MODIFICATION="TRUE" *) + wire [0:15] lru_tag3_dataout_q; + + wire [0:4] tlb_tag3_cmpmask_d; + wire [0:4] tlb_tag3_cmpmask_q; + wire [0:4] tlb_tag3_cmpmask_clone_d; + wire [0:4] tlb_tag3_cmpmask_clone_q; + wire [0:4] tlb_way0_cmpmask_d; + wire [0:4] tlb_way0_cmpmask_q; + wire [0:4] tlb_way1_cmpmask_d; + wire [0:4] tlb_way1_cmpmask_q; + wire [0:4] tlb_way2_cmpmask_d; + wire [0:4] tlb_way2_cmpmask_q; + wire [0:4] tlb_way3_cmpmask_d; + wire [0:4] tlb_way3_cmpmask_q; + wire [0:4] tlb_way0_xbitmask_d; + wire [0:4] tlb_way0_xbitmask_q; + wire [0:4] tlb_way1_xbitmask_d; + wire [0:4] tlb_way1_xbitmask_q; + wire [0:4] tlb_way2_xbitmask_d; + wire [0:4] tlb_way2_xbitmask_q; + wire [0:4] tlb_way3_xbitmask_d; + wire [0:4] tlb_way3_xbitmask_q; + + // tag4 phase + (* NO_MODIFICATION="TRUE" *) + wire [0:`TLB_TAG_WIDTH-1] tlb_tag4_d; + (* NO_MODIFICATION="TRUE" *) + wire [0:`TLB_TAG_WIDTH-1] tlb_tag4_q; + (* NO_MODIFICATION="TRUE" *) + wire [0:`TLB_WAYS] tlb_tag4_wayhit_d; + (* NO_MODIFICATION="TRUE" *) + wire [0:`TLB_WAYS] tlb_tag4_wayhit_q; + (* NO_MODIFICATION="TRUE" *) + wire [0:`TLB_ADDR_WIDTH-1] tlb_addr4_d; + (* NO_MODIFICATION="TRUE" *) + wire [0:`TLB_ADDR_WIDTH-1] tlb_addr4_q; + + (* NO_MODIFICATION="TRUE" *) + wire [0:`TLB_WAY_WIDTH-1] tlb_dataina_d; + (* NO_MODIFICATION="TRUE" *) + wire [0:`TLB_WAY_WIDTH-1] tlb_dataina_q; + (* NO_MODIFICATION="TRUE" *) + wire [0:`TLB_WAY_WIDTH-1] tlb_datainb_d; + (* NO_MODIFICATION="TRUE" *) + wire [0:`TLB_WAY_WIDTH-1] tlb_datainb_q; + (* NO_MODIFICATION="TRUE" *) + wire [0:`LRU_WIDTH-1] lru_tag4_dataout_d; + (* NO_MODIFICATION="TRUE" *) + wire [0:`LRU_WIDTH-1] lru_tag4_dataout_q; + (* NO_MODIFICATION="TRUE" *) + wire [0:`TLB_WAY_WIDTH-1] tlb_tag4_way_d; + (* NO_MODIFICATION="TRUE" *) + wire [0:`TLB_WAY_WIDTH-1] tlb_tag4_way_q; + (* NO_MODIFICATION="TRUE" *) + wire [0:`TLB_WAY_WIDTH-1] tlb_tag4_way_clone_d; + (* NO_MODIFICATION="TRUE" *) + wire [0:`TLB_WAY_WIDTH-1] tlb_tag4_way_clone_q; + (* NO_MODIFICATION="TRUE" *) + wire [0:`TLB_WAY_WIDTH-1] tlb_tag4_way_rw_d; + (* NO_MODIFICATION="TRUE" *) + wire [0:`TLB_WAY_WIDTH-1] tlb_tag4_way_rw_q; + (* NO_MODIFICATION="TRUE" *) + wire [0:`TLB_WAY_WIDTH-1] tlb_tag4_way_rw_clone_d; + (* NO_MODIFICATION="TRUE" *) + wire [0:`TLB_WAY_WIDTH-1] tlb_tag4_way_rw_clone_q; + (* NO_MODIFICATION="TRUE" *) + wire [0:`TLB_WAY_WIDTH-1] tlb_tag4_way_rw_or; + + wire [0:`MM_THREADS] tlbwe_tag4_back_inv_d; + wire [0:`MM_THREADS] tlbwe_tag4_back_inv_q; + wire [18:19] tlbwe_tag4_back_inv_attr_d; + wire [18:19] tlbwe_tag4_back_inv_attr_q; + // tag5 phase + wire [0:2*`THDID_WIDTH+1] tlb_erat_val_d; + wire [0:2*`THDID_WIDTH+1] tlb_erat_val_q; + wire [0:`ERAT_REL_DATA_WIDTH-1] tlb_erat_rel_d; + wire [0:`ERAT_REL_DATA_WIDTH-1] tlb_erat_rel_q; + wire [0:`ERAT_REL_DATA_WIDTH-1] tlb_erat_rel_clone_d; + wire [0:`ERAT_REL_DATA_WIDTH-1] tlb_erat_rel_clone_q; + wire [0:2*`THDID_WIDTH+13] tlb_erat_dup_d; + wire [0:2*`THDID_WIDTH+13] tlb_erat_dup_q; + + (* NO_MODIFICATION="TRUE" *) + wire [0:`LRU_WIDTH-1] lru_write_d; + (* NO_MODIFICATION="TRUE" *) + wire [0:`LRU_WIDTH-1] lru_write_q; + (* NO_MODIFICATION="TRUE" *) + wire [0:`TLB_ADDR_WIDTH-1] lru_wr_addr_d; + (* NO_MODIFICATION="TRUE" *) + wire [0:`TLB_ADDR_WIDTH-1] lru_wr_addr_q; + (* NO_MODIFICATION="TRUE" *) + wire [0:`LRU_WIDTH-1] lru_datain_d; + (* NO_MODIFICATION="TRUE" *) + wire [0:`LRU_WIDTH-1] lru_datain_q; + + wire [0:`MM_THREADS-1] eratmiss_done_d; + wire [0:`MM_THREADS-1] eratmiss_done_q; + wire [0:`MM_THREADS-1] tlb_miss_d; + wire [0:`MM_THREADS-1] tlb_miss_q; + wire [0:`MM_THREADS-1] tlb_inelig_d; + wire [0:`MM_THREADS-1] tlb_inelig_q; + wire [0:`MM_THREADS-1] lrat_miss_d; + wire [0:`MM_THREADS-1] lrat_miss_q; + wire [0:`MM_THREADS-1] pt_fault_d; + wire [0:`MM_THREADS-1] pt_fault_q; + wire [0:`MM_THREADS-1] hv_priv_d; + wire [0:`MM_THREADS-1] hv_priv_q; + wire [0:`MM_THREADS-1] tlb_tag5_except_d; + wire [0:`MM_THREADS-1] tlb_tag5_except_q; + wire [0:`MM_THREADS-1] tlb_dsi_d; + wire [0:`MM_THREADS-1] tlb_dsi_q; + wire [0:`MM_THREADS-1] tlb_isi_d; + wire [0:`MM_THREADS-1] tlb_isi_q; + + wire [0:`TLB_WAYS] tag4_parerr_d, tag4_parerr_q; + wire [0:`ITAG_SIZE_ENC-1] tlb_tag5_itag_d, tlb_tag5_itag_q; + wire [0:`EMQ_ENTRIES-1] tlb_tag5_emq_d, tlb_tag5_emq_q; + wire [0:1] tlb_tag5_perf_d, tlb_tag5_perf_q; + wire [10:18] mmucr1_q; + wire [10:18] mmucr1_clone_q; + + wire [0:`MM_THREADS-1] esr_pt_d; + wire [0:`MM_THREADS-1] esr_pt_q; + wire [0:`MM_THREADS-1] esr_data_d; + wire [0:`MM_THREADS-1] esr_data_q; + wire [0:`MM_THREADS-1] esr_epid_d; + wire [0:`MM_THREADS-1] esr_epid_q; + wire [0:`MM_THREADS-1] esr_st_d; + wire [0:`MM_THREADS-1] esr_st_q; + wire [0:`MM_THREADS-1] tlb_multihit_err_d; + wire [0:`MM_THREADS-1] tlb_multihit_err_q; + wire [0:`MM_THREADS-1] tlb_par_err_d; + wire [0:`MM_THREADS-1] tlb_par_err_q; + wire [0:`MM_THREADS-1] lru_par_err_d; + wire [0:`MM_THREADS-1] lru_par_err_q; + wire [0:`MM_THREADS-1] cr0_eq_d; + wire [0:`MM_THREADS-1] cr0_eq_q; + wire [0:`MM_THREADS-1] cr0_eq_valid_d; + wire [0:`MM_THREADS-1] cr0_eq_valid_q; + wire [0:`MM_THREADS-1] epcr_dmiuh_q; + wire [0:`MM_THREADS-1] msr_gs_q; + wire [0:`MM_THREADS-1] msr_pr_q; + + wire tlb_multihit_err_ored; + wire tlb_par_err_ored; + wire lru_par_err_ored; + wire lru_update_clear_enab_q; + wire [0:2] mm_xu_ord_par_mhit_err_d, mm_xu_ord_par_mhit_err_q; + + wire [0:15] spare_a_q; + wire [0:15] spare_b_q; + wire [0:15] spare_c_q; + wire [0:7] spare_nsl_q; + wire [0:7] spare_nsl_clone_q; + wire [0:7] cswitch_q; + + + // Logic signals + // tag3 phase + (* NO_MODIFICATION="TRUE" *) + wire pgsize_enable; + (* NO_MODIFICATION="TRUE" *) + wire class_enable; + (* NO_MODIFICATION="TRUE" *) + wire thdid_enable; + (* NO_MODIFICATION="TRUE" *) + wire pid_enable; + (* NO_MODIFICATION="TRUE" *) + wire lpid_enable; + (* NO_MODIFICATION="TRUE" *) + wire ind_enable; + (* NO_MODIFICATION="TRUE" *) + wire iprot_enable; + (* NO_MODIFICATION="TRUE" *) + wire [0:1] state_enable; + (* NO_MODIFICATION="TRUE" *) + wire [0:1] extclass_enable; + (* NO_MODIFICATION="TRUE" *) + wire [0:8] addr_enable; + (* NO_MODIFICATION="TRUE" *) + wire comp_iprot; + wire [0:1] comp_extclass; + wire comp_ind; + (* NO_MODIFICATION="TRUE" *) + wire pgsize_enable_clone; + (* NO_MODIFICATION="TRUE" *) + wire class_enable_clone; + (* NO_MODIFICATION="TRUE" *) + wire thdid_enable_clone; + (* NO_MODIFICATION="TRUE" *) + wire pid_enable_clone; + (* NO_MODIFICATION="TRUE" *) + wire lpid_enable_clone; + (* NO_MODIFICATION="TRUE" *) + wire ind_enable_clone; + (* NO_MODIFICATION="TRUE" *) + wire iprot_enable_clone; + (* NO_MODIFICATION="TRUE" *) + wire [0:1] state_enable_clone; + (* NO_MODIFICATION="TRUE" *) + wire [0:1] extclass_enable_clone; + (* NO_MODIFICATION="TRUE" *) + wire [0:8] addr_enable_clone; + wire comp_iprot_clone; + wire [0:1] comp_extclass_clone; + wire comp_ind_clone; + + wire tlbwe_tag3_back_inv_enab; + wire [0:`TLB_WAY_WIDTH-1] tlb_tag4_way_or; + wire tlb_tag4_way_act; + wire tlb_tag4_way_clone_act; + wire tlb_tag4_way_rw_act; + wire tlb_tag4_way_rw_clone_act; + // tag4 phase + wire [0:7] tlb_tag4_type_sig; + wire [0:2] tlb_tag4_esel_sig; + wire tlb_tag4_hes_sig; + wire [0:1] tlb_tag4_wq_sig; + wire [0:3] tlb_tag4_is_sig; + wire [0:`THDID_WIDTH-1] tlb_tag4_hes1_mas1_v; + wire [0:`THDID_WIDTH-1] tlb_tag4_hes0_mas1_v; + wire [0:`THDID_WIDTH-1] tlb_tag4_hes1_mas1_iprot; + wire [0:`THDID_WIDTH-1] tlb_tag4_hes0_mas1_iprot; + wire [0:`THDID_WIDTH-1] tlb_tag4_ptereload_v; + wire [0:`THDID_WIDTH-1] tlb_tag4_ptereload_iprot; + wire tlb_tag4_ptereload_sig; + wire tlb_tag4_erat_data_cap; + + (* NO_MODIFICATION="TRUE" *) + wire [0:`TLB_WAYS-1] tlb_wayhit; + (* NO_MODIFICATION="TRUE" *) + wire multihit; + wire [0:2] erat_pgsize; + wire tlb_tag4_size_not_supp; + wire tlb_tag4_hv_op; + wire tlb_tag4_epcr_dgtmi; + + (* NO_MODIFICATION="TRUE" *) + wire tlb_way0_addr_match; + (* NO_MODIFICATION="TRUE" *) + wire tlb_way0_pgsize_match; + (* NO_MODIFICATION="TRUE" *) + wire tlb_way0_class_match; + (* NO_MODIFICATION="TRUE" *) + wire tlb_way0_extclass_match; + (* NO_MODIFICATION="TRUE" *) + wire tlb_way0_state_match; + (* NO_MODIFICATION="TRUE" *) + wire tlb_way0_thdid_match; + (* NO_MODIFICATION="TRUE" *) + wire tlb_way0_pid_match; + (* NO_MODIFICATION="TRUE" *) + wire tlb_way0_lpid_match; + (* NO_MODIFICATION="TRUE" *) + wire tlb_way0_ind_match; + (* NO_MODIFICATION="TRUE" *) + wire tlb_way0_iprot_match; + (* NO_MODIFICATION="TRUE" *) + wire tlb_way1_addr_match; + (* NO_MODIFICATION="TRUE" *) + wire tlb_way1_pgsize_match; + (* NO_MODIFICATION="TRUE" *) + wire tlb_way1_class_match; + (* NO_MODIFICATION="TRUE" *) + wire tlb_way1_extclass_match; + (* NO_MODIFICATION="TRUE" *) + wire tlb_way1_state_match; + (* NO_MODIFICATION="TRUE" *) + wire tlb_way1_thdid_match; + (* NO_MODIFICATION="TRUE" *) + wire tlb_way1_pid_match; + (* NO_MODIFICATION="TRUE" *) + wire tlb_way1_lpid_match; + (* NO_MODIFICATION="TRUE" *) + wire tlb_way1_ind_match; + (* NO_MODIFICATION="TRUE" *) + wire tlb_way1_iprot_match; + (* NO_MODIFICATION="TRUE" *) + wire tlb_way2_addr_match; + (* NO_MODIFICATION="TRUE" *) + wire tlb_way2_pgsize_match; + (* NO_MODIFICATION="TRUE" *) + wire tlb_way2_class_match; + (* NO_MODIFICATION="TRUE" *) + wire tlb_way2_extclass_match; + (* NO_MODIFICATION="TRUE" *) + wire tlb_way2_state_match; + (* NO_MODIFICATION="TRUE" *) + wire tlb_way2_thdid_match; + (* NO_MODIFICATION="TRUE" *) + wire tlb_way2_pid_match; + (* NO_MODIFICATION="TRUE" *) + wire tlb_way2_lpid_match; + (* NO_MODIFICATION="TRUE" *) + wire tlb_way2_ind_match; + (* NO_MODIFICATION="TRUE" *) + wire tlb_way2_iprot_match; + (* NO_MODIFICATION="TRUE" *) + wire tlb_way3_addr_match; + (* NO_MODIFICATION="TRUE" *) + wire tlb_way3_pgsize_match; + (* NO_MODIFICATION="TRUE" *) + wire tlb_way3_class_match; + (* NO_MODIFICATION="TRUE" *) + wire tlb_way3_extclass_match; + (* NO_MODIFICATION="TRUE" *) + wire tlb_way3_state_match; + (* NO_MODIFICATION="TRUE" *) + wire tlb_way3_thdid_match; + (* NO_MODIFICATION="TRUE" *) + wire tlb_way3_pid_match; + (* NO_MODIFICATION="TRUE" *) + wire tlb_way3_lpid_match; + (* NO_MODIFICATION="TRUE" *) + wire tlb_way3_ind_match; + (* NO_MODIFICATION="TRUE" *) + wire tlb_way3_iprot_match; + + wire ierat_req0_tag4_pid_match; + wire ierat_req0_tag4_as_match; + wire ierat_req0_tag4_gs_match; + wire ierat_req0_tag4_epn_match; + wire ierat_req0_tag4_thdid_match; + wire ierat_req1_tag4_pid_match; + wire ierat_req1_tag4_as_match; + wire ierat_req1_tag4_gs_match; + wire ierat_req1_tag4_epn_match; + wire ierat_req1_tag4_thdid_match; + wire ierat_req2_tag4_pid_match; + wire ierat_req2_tag4_as_match; + wire ierat_req2_tag4_gs_match; + wire ierat_req2_tag4_epn_match; + wire ierat_req2_tag4_thdid_match; + wire ierat_req3_tag4_pid_match; + wire ierat_req3_tag4_as_match; + wire ierat_req3_tag4_gs_match; + wire ierat_req3_tag4_epn_match; + wire ierat_req3_tag4_thdid_match; + wire ierat_iu4_tag4_lpid_match; + wire ierat_iu4_tag4_pid_match; + wire ierat_iu4_tag4_as_match; + wire ierat_iu4_tag4_gs_match; + wire ierat_iu4_tag4_epn_match; + wire ierat_iu4_tag4_thdid_match; + wire derat_req0_tag4_lpid_match; + wire derat_req0_tag4_pid_match; + wire derat_req0_tag4_as_match; + wire derat_req0_tag4_gs_match; + wire derat_req0_tag4_epn_match; + wire derat_req0_tag4_thdid_match; + wire derat_req1_tag4_lpid_match; + wire derat_req1_tag4_pid_match; + wire derat_req1_tag4_as_match; + wire derat_req1_tag4_gs_match; + wire derat_req1_tag4_epn_match; + wire derat_req1_tag4_thdid_match; + wire derat_req2_tag4_lpid_match; + wire derat_req2_tag4_pid_match; + wire derat_req2_tag4_as_match; + wire derat_req2_tag4_gs_match; + wire derat_req2_tag4_epn_match; + wire derat_req2_tag4_thdid_match; + wire derat_req3_tag4_lpid_match; + wire derat_req3_tag4_pid_match; + wire derat_req3_tag4_as_match; + wire derat_req3_tag4_gs_match; + wire derat_req3_tag4_epn_match; + wire derat_req3_tag4_thdid_match; + wire derat_ex5_tag4_lpid_match; + wire derat_ex5_tag4_pid_match; + wire derat_ex5_tag4_as_match; + wire derat_ex5_tag4_gs_match; + wire derat_ex5_tag4_epn_match; + wire derat_ex5_tag4_thdid_match; + wire [0:`THDID_WIDTH-1] ierat_tag4_dup_thdid; + wire [0:`THDID_WIDTH-1] derat_tag4_dup_thdid; + wire [0:`EMQ_ENTRIES-1] derat_tag4_dup_emq; + + wire [0:9] tlb_way0_lo_calc_par; + wire [0:9] tlb_way0_hi_calc_par; + wire tlb_way0_parerr; + wire [0:9] tlb_way1_lo_calc_par; + wire [0:9] tlb_way1_hi_calc_par; + wire tlb_way1_parerr; + wire [0:9] tlb_way2_lo_calc_par; + wire [0:9] tlb_way2_hi_calc_par; + wire tlb_way2_parerr; + wire [0:9] tlb_way3_lo_calc_par; + wire [0:9] tlb_way3_hi_calc_par; + wire tlb_way3_parerr; + wire [0:1] lru_calc_par; + + wire [0:`TLB_WORD_WIDTH-10-1] tlb_datain_lo_tlbwe_0_nopar; + wire [0:9] tlb_datain_lo_tlbwe_0_par; + wire [0:`TLB_WORD_WIDTH-10-1] tlb_datain_hi_hv_tlbwe_0_nopar; + wire [0:`TLB_WORD_WIDTH-10-1] tlb_datain_hi_gs_tlbwe_0_nopar; + wire [0:9] tlb_datain_hi_hv_tlbwe_0_par; + wire [0:9] tlb_datain_hi_gs_tlbwe_0_par; +`ifdef MM_THREADS2 + wire [0:`TLB_WORD_WIDTH-10-1] tlb_datain_lo_tlbwe_1_nopar; + wire [0:9] tlb_datain_lo_tlbwe_1_par; + wire [0:`TLB_WORD_WIDTH-10-1] tlb_datain_hi_hv_tlbwe_1_nopar; + wire [0:`TLB_WORD_WIDTH-10-1] tlb_datain_hi_gs_tlbwe_1_nopar; + wire [0:9] tlb_datain_hi_hv_tlbwe_1_par; + wire [0:9] tlb_datain_hi_gs_tlbwe_1_par; +`endif + wire [0:`TLB_WORD_WIDTH-10-1] tlb_datain_lo_ptereload_nopar; + wire [0:9] tlb_datain_lo_ptereload_par; + wire [0:`TLB_WORD_WIDTH-10-1] tlb_datain_hi_hv_ptereload_nopar; + wire [0:`TLB_WORD_WIDTH-10-1] tlb_datain_hi_gs_ptereload_nopar; + wire [0:9] tlb_datain_hi_hv_ptereload_par; + wire [0:9] tlb_datain_hi_gs_ptereload_par; + wire [0:5] ptereload_req_derived_usxwr; + wire [22:51] lrat_tag3_lpn_sig; + wire [22:51] lrat_tag3_rpn_sig; + wire [22:51] lrat_tag4_lpn_sig; + wire [22:51] lrat_tag4_rpn_sig; + + // possible eco signals + (* NO_MODIFICATION="TRUE" *) + wire [4:9] lru_datain_alt_d; + (* NO_MODIFICATION="TRUE" *) + wire [0:2] lru_update_data_alt; + (* NO_MODIFICATION="TRUE" *) + wire tlb_tag4_parerr_enab; + (* NO_MODIFICATION="TRUE" *) + wire tlb_tag4_tlbre_parerr; + (* NO_MODIFICATION="TRUE" *) + wire [0:2] lru_update_data_snoophit_eco; + (* NO_MODIFICATION="TRUE" *) + wire [0:2] lru_update_data_erathit_eco; + + (* analysis_not_referenced="true" *) + wire [0:41] unused_dc; + + wire [0:15] tri_regk_unused_scan; // spare regk non-scan latches with bogus scan ports + + wire [0:`MM_THREADS-1] tri_regk_unused_scan_epcr_dmiuh; + wire [0:`MM_THREADS-1] tri_regk_unused_scan_msr_gs; + wire [0:`MM_THREADS-1] tri_regk_unused_scan_msr_pr; + + + // dd2 eco signals + wire ECO107332_orred_tag4_thdid_flushed; + wire [0:`MM_THREADS-1] ECO107332_tlb_par_err_d; + wire [0:`MM_THREADS-1] ECO107332_lru_par_err_d; + + // Pervasive + wire pc_sg_1; + wire pc_sg_0; + wire pc_fce_1; + wire pc_fce_0; + wire pc_func_sl_thold_1; + wire pc_func_sl_thold_0; + wire pc_func_sl_thold_0_b; + wire pc_func_slp_sl_thold_1; + wire pc_func_slp_sl_thold_0; + wire pc_func_slp_sl_thold_0_b; + wire pc_func_sl_force; + wire pc_func_slp_sl_force; + wire pc_func_slp_nsl_thold_1; + wire pc_func_slp_nsl_thold_0; + wire [0:1] pc_func_slp_nsl_thold_0_b; + wire [0:1] pc_func_slp_nsl_force; + + wire [0:scan_right_0] siv_0; + wire [0:scan_right_0] sov_0; + wire [0:scan_right_1] siv_1; + wire [0:scan_right_1] sov_1; + wire [0:scan_right_2] siv_2; + wire [0:scan_right_2] sov_2; + + //signal reset_alias : std_ulogic; + wire tidn; + wire tiup; + + //@@ START OF EXECUTABLE CODE FOR MMQ_TLB_CMP + + //begin + //!! Bugspray Include: mmq_tlb_cmp; + + //--------------------------------------------------------------------- + // Logic + //--------------------------------------------------------------------- + assign tidn = 1'b0; + assign tiup = 1'b1; + + // tag2 phase signals, tlbwe/re ex4, tlbsx/srx ex5 + assign tlb_addr3_d = tlb_addr2; + + // latch tlb array outputs + assign tlb_way0_d = tlb_dataout[0:`TLB_WAY_WIDTH - 1]; + assign tlb_way1_d = tlb_dataout[`TLB_WAY_WIDTH:2 * `TLB_WAY_WIDTH - 1]; + assign tlb_way2_d = tlb_dataout[2 * `TLB_WAY_WIDTH:3 * `TLB_WAY_WIDTH - 1]; + assign tlb_way3_d = tlb_dataout[3 * `TLB_WAY_WIDTH:4 * `TLB_WAY_WIDTH - 1]; + + // tlb_ctl may flush the thdid bits + assign tlb_tag3_d[0:`tagpos_thdid - 1] = tlb_tag2[0:`tagpos_thdid - 1]; + + assign tlb_tag3_d[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] = + (((tlb_tag4_wayhit_q[`TLB_WAYS] == 1'b1 | tlb_tag4_q[`tagpos_endflag] == 1'b1 | |(tag4_parerr_q[0:4]) == 1'b1) & tlb_tag4_q[`tagpos_type_ptereload] == 1'b0 & (tlb_tag4_q[`tagpos_type_ierat] == 1'b1 | tlb_tag4_q[`tagpos_type_derat] == 1'b1))) ? {`MM_THREADS{1'b0}} : + (((tlb_tag4_wayhit_q[`TLB_WAYS] == 1'b1 | tlb_tag4_q[`tagpos_endflag] == 1'b1 | |(tag4_parerr_q[0:4]) == 1'b1) & (tlb_tag4_q[`tagpos_type_tlbsx] == 1'b1 | tlb_tag4_q[`tagpos_type_tlbsrx] == 1'b1))) ? {`MM_THREADS{1'b0}} : + ((tlb_tag4_q[`tagpos_endflag] == 1'b1 & tlb_tag4_q[`tagpos_type_snoop] == 1'b1)) ? {`MM_THREADS{1'b0}} : + (((tlb_tag4_q[`tagpos_type_tlbre] == 1'b1 | tlb_tag4_q[`tagpos_type_tlbwe] == 1'b1 | tlb_tag4_q[`tagpos_type_ptereload] == 1'b1) & |(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1)) ? {`MM_THREADS{1'b0}} : + tlb_tag2[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] & (~(tlb_ctl_tag2_flush)); + generate + if (`THDID_WIDTH > `MM_THREADS) + begin : tlbtag3NExist + assign tlb_tag3_d[`tagpos_thdid + `MM_THREADS:`tagpos_thdid + `THDID_WIDTH - 1] = + (((tlb_tag4_wayhit_q[`TLB_WAYS] == 1'b1 | tlb_tag4_q[`tagpos_endflag] == 1'b1 | |(tag4_parerr_q[0:4]) == 1'b1) & tlb_tag4_q[`tagpos_type_ptereload] == 1'b0 & (tlb_tag4_q[`tagpos_type_ierat] == 1'b1 | tlb_tag4_q[`tagpos_type_derat] == 1'b1))) ? {`THDID_WIDTH-`MM_THREADS{1'b0}} : + (((tlb_tag4_wayhit_q[`TLB_WAYS] == 1'b1 | tlb_tag4_q[`tagpos_endflag] == 1'b1 | |(tag4_parerr_q[0:4]) == 1'b1) & (tlb_tag4_q[`tagpos_type_tlbsx] == 1'b1 | tlb_tag4_q[`tagpos_type_tlbsrx] == 1'b1))) ? {`THDID_WIDTH-`MM_THREADS{1'b0}} : + ((tlb_tag4_q[`tagpos_endflag] == 1'b1 & tlb_tag4_q[`tagpos_type_snoop] == 1'b1)) ? {`THDID_WIDTH-`MM_THREADS{1'b0}} : + (((tlb_tag4_q[`tagpos_type_tlbre] == 1'b1 | tlb_tag4_q[`tagpos_type_tlbwe] == 1'b1 | tlb_tag4_q[`tagpos_type_ptereload] == 1'b1) & |(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1)) ? {`THDID_WIDTH-`MM_THREADS{1'b0}} : + tlb_tag2[`tagpos_thdid + `MM_THREADS:`tagpos_thdid + `THDID_WIDTH - 1]; + end + endgenerate + + assign tlb_tag3_d[`tagpos_thdid + `THDID_WIDTH:`TLB_TAG_WIDTH - 1] = tlb_tag2[`tagpos_thdid + `THDID_WIDTH:`TLB_TAG_WIDTH - 1]; + + // clones for timing arrays 0/1 + assign tlb_tag3_clone1_d[0:`tagpos_thdid - 1] = tlb_tag2[0:`tagpos_thdid - 1]; + assign tlb_tag3_clone1_d[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] = + (((tlb_tag4_wayhit_q[`TLB_WAYS] == 1'b1 | tlb_tag4_q[`tagpos_endflag] == 1'b1 | |(tag4_parerr_q[0:4]) == 1'b1) & tlb_tag4_q[`tagpos_type_ptereload] == 1'b0 & (tlb_tag4_q[`tagpos_type_ierat] == 1'b1 | tlb_tag4_q[`tagpos_type_derat] == 1'b1))) ? {`MM_THREADS{1'b0}} : + (((tlb_tag4_wayhit_q[`TLB_WAYS] == 1'b1 | tlb_tag4_q[`tagpos_endflag] == 1'b1 | |(tag4_parerr_q[0:4]) == 1'b1) & (tlb_tag4_q[`tagpos_type_tlbsx] == 1'b1 | tlb_tag4_q[`tagpos_type_tlbsrx] == 1'b1))) ? {`MM_THREADS{1'b0}} : + ((tlb_tag4_q[`tagpos_endflag] == 1'b1 & tlb_tag4_q[`tagpos_type_snoop] == 1'b1)) ? {`MM_THREADS{1'b0}} : + (((tlb_tag4_q[`tagpos_type_tlbre] == 1'b1 | tlb_tag4_q[`tagpos_type_tlbwe] == 1'b1 | tlb_tag4_q[`tagpos_type_ptereload] == 1'b1) & |(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1)) ? {`MM_THREADS{1'b0}} : + tlb_tag2[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] & (~(tlb_ctl_tag2_flush)); + generate + if (`THDID_WIDTH > `MM_THREADS) + begin : tlbtag3c1NExist + assign tlb_tag3_clone1_d[`tagpos_thdid + `MM_THREADS:`tagpos_thdid + `THDID_WIDTH - 1] = + (((tlb_tag4_wayhit_q[`TLB_WAYS] == 1'b1 | tlb_tag4_q[`tagpos_endflag] == 1'b1 | |(tag4_parerr_q[0:4]) == 1'b1) & tlb_tag4_q[`tagpos_type_ptereload] == 1'b0 & (tlb_tag4_q[`tagpos_type_ierat] == 1'b1 | tlb_tag4_q[`tagpos_type_derat] == 1'b1))) ? {`THDID_WIDTH-`MM_THREADS{1'b0}} : + (((tlb_tag4_wayhit_q[`TLB_WAYS] == 1'b1 | tlb_tag4_q[`tagpos_endflag] == 1'b1 | |(tag4_parerr_q[0:4]) == 1'b1) & (tlb_tag4_q[`tagpos_type_tlbsx] == 1'b1 | tlb_tag4_q[`tagpos_type_tlbsrx] == 1'b1))) ? {`THDID_WIDTH-`MM_THREADS{1'b0}} : + ((tlb_tag4_q[`tagpos_endflag] == 1'b1 & tlb_tag4_q[`tagpos_type_snoop] == 1'b1)) ? {`THDID_WIDTH-`MM_THREADS{1'b0}} : + (((tlb_tag4_q[`tagpos_type_tlbre] == 1'b1 | tlb_tag4_q[`tagpos_type_tlbwe] == 1'b1 | tlb_tag4_q[`tagpos_type_ptereload] == 1'b1) & |(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1)) ? {`THDID_WIDTH-`MM_THREADS{1'b0}} : + tlb_tag2[`tagpos_thdid + `MM_THREADS:`tagpos_thdid + `THDID_WIDTH - 1]; + end + endgenerate + + assign tlb_tag3_clone1_d[`tagpos_thdid + `THDID_WIDTH:`TLB_TAG_WIDTH - 1] = tlb_tag2[`tagpos_thdid + `THDID_WIDTH:`TLB_TAG_WIDTH - 1]; + + // clones for timing arrays 2/3 + assign tlb_tag3_clone2_d[0:`tagpos_thdid - 1] = tlb_tag2[0:`tagpos_thdid - 1]; + assign tlb_tag3_clone2_d[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] = + (((tlb_tag4_wayhit_q[`TLB_WAYS] == 1'b1 | tlb_tag4_q[`tagpos_endflag] == 1'b1 | |(tag4_parerr_q[0:4]) == 1'b1) & tlb_tag4_q[`tagpos_type_ptereload] == 1'b0 & (tlb_tag4_q[`tagpos_type_ierat] == 1'b1 | tlb_tag4_q[`tagpos_type_derat] == 1'b1))) ? {`MM_THREADS{1'b0}} : + (((tlb_tag4_wayhit_q[`TLB_WAYS] == 1'b1 | tlb_tag4_q[`tagpos_endflag] == 1'b1 | |(tag4_parerr_q[0:4]) == 1'b1) & (tlb_tag4_q[`tagpos_type_tlbsx] == 1'b1 | tlb_tag4_q[`tagpos_type_tlbsrx] == 1'b1))) ? {`MM_THREADS{1'b0}} : + ((tlb_tag4_q[`tagpos_endflag] == 1'b1 & tlb_tag4_q[`tagpos_type_snoop] == 1'b1)) ? {`MM_THREADS{1'b0}} : + (((tlb_tag4_q[`tagpos_type_tlbre] == 1'b1 | tlb_tag4_q[`tagpos_type_tlbwe] == 1'b1 | tlb_tag4_q[`tagpos_type_ptereload] == 1'b1) & |(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1)) ? {`MM_THREADS{1'b0}} : + tlb_tag2[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] & (~(tlb_ctl_tag2_flush)); + generate + if (`THDID_WIDTH > `MM_THREADS) + begin : tlbtag3c2NExist + assign tlb_tag3_clone2_d[`tagpos_thdid + `MM_THREADS:`tagpos_thdid + `THDID_WIDTH - 1] = + (((tlb_tag4_wayhit_q[`TLB_WAYS] == 1'b1 | tlb_tag4_q[`tagpos_endflag] == 1'b1 | |(tag4_parerr_q[0:4]) == 1'b1) & tlb_tag4_q[`tagpos_type_ptereload] == 1'b0 & (tlb_tag4_q[`tagpos_type_ierat] == 1'b1 | tlb_tag4_q[`tagpos_type_derat] == 1'b1))) ? {`THDID_WIDTH-`MM_THREADS{1'b0}} : + (((tlb_tag4_wayhit_q[`TLB_WAYS] == 1'b1 | tlb_tag4_q[`tagpos_endflag] == 1'b1 | |(tag4_parerr_q[0:4]) == 1'b1) & (tlb_tag4_q[`tagpos_type_tlbsx] == 1'b1 | tlb_tag4_q[`tagpos_type_tlbsrx] == 1'b1))) ? {`THDID_WIDTH-`MM_THREADS{1'b0}} : + ((tlb_tag4_q[`tagpos_endflag] == 1'b1 & tlb_tag4_q[`tagpos_type_snoop] == 1'b1)) ? {`THDID_WIDTH-`MM_THREADS{1'b0}} : + (((tlb_tag4_q[`tagpos_type_tlbre] == 1'b1 | tlb_tag4_q[`tagpos_type_tlbwe] == 1'b1 | tlb_tag4_q[`tagpos_type_ptereload] == 1'b1) & |(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1)) ? {`THDID_WIDTH-`MM_THREADS{1'b0}} : + tlb_tag2[`tagpos_thdid + `MM_THREADS:`tagpos_thdid + `THDID_WIDTH - 1]; + end + endgenerate + + assign tlb_tag3_clone2_d[`tagpos_thdid + `THDID_WIDTH:`TLB_TAG_WIDTH - 1] = tlb_tag2[`tagpos_thdid + `THDID_WIDTH:`TLB_TAG_WIDTH - 1]; + + // size tlb_tag3_cmpmask: 01234 + // 1GB 11111 + // 256MB 01111 + // 16MB 00111 + // 1MB 00011 + // 64KB 00001 + // 4KB 00000 + + assign tlb_tag3_cmpmask_d[0] = (tlb_tag2[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_1GB); + assign tlb_tag3_cmpmask_d[1] = (tlb_tag2[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_1GB) | (tlb_tag2[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_256MB); + assign tlb_tag3_cmpmask_d[2] = (tlb_tag2[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_1GB) | (tlb_tag2[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_256MB) | (tlb_tag2[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_16MB); + assign tlb_tag3_cmpmask_d[3] = (tlb_tag2[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_1GB) | (tlb_tag2[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_256MB) | (tlb_tag2[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_16MB) | (tlb_tag2[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_1MB); + assign tlb_tag3_cmpmask_d[4] = (tlb_tag2[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_1GB) | (tlb_tag2[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_256MB) | (tlb_tag2[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_16MB) | (tlb_tag2[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_1MB) | (tlb_tag2[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_64KB); + + assign tlb_tag3_cmpmask_clone_d[0] = (tlb_tag2[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_1GB); + assign tlb_tag3_cmpmask_clone_d[1] = (tlb_tag2[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_1GB) | (tlb_tag2[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_256MB); + assign tlb_tag3_cmpmask_clone_d[2] = (tlb_tag2[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_1GB) | (tlb_tag2[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_256MB) | (tlb_tag2[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_16MB); + assign tlb_tag3_cmpmask_clone_d[3] = (tlb_tag2[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_1GB) | (tlb_tag2[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_256MB) | (tlb_tag2[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_16MB) | (tlb_tag2[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_1MB); + assign tlb_tag3_cmpmask_clone_d[4] = (tlb_tag2[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_1GB) | (tlb_tag2[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_256MB) | (tlb_tag2[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_16MB) | (tlb_tag2[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_1MB) | (tlb_tag2[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_64KB); + + // size tlb_way_cmpmask: 01234 + // 1GB 11111 + // 256MB 01111 + // 16MB 00111 + // 1MB 00011 + // 64KB 00001 + // 4KB 00000 + // size tlb_way_xbitmask: 01234 + // 1GB 10000 + // 256MB 01000 + // 16MB 00100 + // 1MB 00010 + // 64KB 00001 + // 4KB 00000 + assign tlb_way0_cmpmask_d[0] = (tlb_dataout[0 * `TLB_WAY_WIDTH + `waypos_size:0 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_1GB); + assign tlb_way0_cmpmask_d[1] = (tlb_dataout[0 * `TLB_WAY_WIDTH + `waypos_size:0 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_1GB) | (tlb_dataout[0 * `TLB_WAY_WIDTH + `waypos_size:0 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_256MB); + assign tlb_way0_cmpmask_d[2] = (tlb_dataout[0 * `TLB_WAY_WIDTH + `waypos_size:0 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_1GB) | (tlb_dataout[0 * `TLB_WAY_WIDTH + `waypos_size:0 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_256MB) | (tlb_dataout[0 * `TLB_WAY_WIDTH + `waypos_size:0 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_16MB); + assign tlb_way0_cmpmask_d[3] = (tlb_dataout[0 * `TLB_WAY_WIDTH + `waypos_size:0 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_1GB) | (tlb_dataout[0 * `TLB_WAY_WIDTH + `waypos_size:0 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_256MB) | (tlb_dataout[0 * `TLB_WAY_WIDTH + `waypos_size:0 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_16MB) | (tlb_dataout[0 * `TLB_WAY_WIDTH + `waypos_size:0 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_1MB); + assign tlb_way0_cmpmask_d[4] = (tlb_dataout[0 * `TLB_WAY_WIDTH + `waypos_size:0 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_1GB) | (tlb_dataout[0 * `TLB_WAY_WIDTH + `waypos_size:0 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_256MB) | (tlb_dataout[0 * `TLB_WAY_WIDTH + `waypos_size:0 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_16MB) | (tlb_dataout[0 * `TLB_WAY_WIDTH + `waypos_size:0 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_1MB) | (tlb_dataout[0 * `TLB_WAY_WIDTH + `waypos_size:0 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_64KB); + assign tlb_way0_xbitmask_d[0] = (tlb_dataout[0 * `TLB_WAY_WIDTH + `waypos_size:0 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_1GB); + assign tlb_way0_xbitmask_d[1] = (tlb_dataout[0 * `TLB_WAY_WIDTH + `waypos_size:0 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_256MB); + assign tlb_way0_xbitmask_d[2] = (tlb_dataout[0 * `TLB_WAY_WIDTH + `waypos_size:0 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_16MB); + assign tlb_way0_xbitmask_d[3] = (tlb_dataout[0 * `TLB_WAY_WIDTH + `waypos_size:0 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_1MB); + assign tlb_way0_xbitmask_d[4] = (tlb_dataout[0 * `TLB_WAY_WIDTH + `waypos_size:0 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_64KB); + assign tlb_way1_cmpmask_d[0] = (tlb_dataout[1 * `TLB_WAY_WIDTH + `waypos_size:1 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_1GB); + assign tlb_way1_cmpmask_d[1] = (tlb_dataout[1 * `TLB_WAY_WIDTH + `waypos_size:1 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_1GB) | (tlb_dataout[1 * `TLB_WAY_WIDTH + `waypos_size:1 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_256MB); + assign tlb_way1_cmpmask_d[2] = (tlb_dataout[1 * `TLB_WAY_WIDTH + `waypos_size:1 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_1GB) | (tlb_dataout[1 * `TLB_WAY_WIDTH + `waypos_size:1 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_256MB) | (tlb_dataout[1 * `TLB_WAY_WIDTH + `waypos_size:1 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_16MB); + assign tlb_way1_cmpmask_d[3] = (tlb_dataout[1 * `TLB_WAY_WIDTH + `waypos_size:1 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_1GB) | (tlb_dataout[1 * `TLB_WAY_WIDTH + `waypos_size:1 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_256MB) | (tlb_dataout[1 * `TLB_WAY_WIDTH + `waypos_size:1 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_16MB) | (tlb_dataout[1 * `TLB_WAY_WIDTH + `waypos_size:1 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_1MB); + assign tlb_way1_cmpmask_d[4] = (tlb_dataout[1 * `TLB_WAY_WIDTH + `waypos_size:1 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_1GB) | (tlb_dataout[1 * `TLB_WAY_WIDTH + `waypos_size:1 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_256MB) | (tlb_dataout[1 * `TLB_WAY_WIDTH + `waypos_size:1 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_16MB) | (tlb_dataout[1 * `TLB_WAY_WIDTH + `waypos_size:1 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_1MB) | (tlb_dataout[1 * `TLB_WAY_WIDTH + `waypos_size:1 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_64KB); + assign tlb_way1_xbitmask_d[0] = (tlb_dataout[1 * `TLB_WAY_WIDTH + `waypos_size:1 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_1GB); + assign tlb_way1_xbitmask_d[1] = (tlb_dataout[1 * `TLB_WAY_WIDTH + `waypos_size:1 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_256MB); + assign tlb_way1_xbitmask_d[2] = (tlb_dataout[1 * `TLB_WAY_WIDTH + `waypos_size:1 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_16MB); + assign tlb_way1_xbitmask_d[3] = (tlb_dataout[1 * `TLB_WAY_WIDTH + `waypos_size:1 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_1MB); + assign tlb_way1_xbitmask_d[4] = (tlb_dataout[1 * `TLB_WAY_WIDTH + `waypos_size:1 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_64KB); + assign tlb_way2_cmpmask_d[0] = (tlb_dataout[2 * `TLB_WAY_WIDTH + `waypos_size:2 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_1GB); + assign tlb_way2_cmpmask_d[1] = (tlb_dataout[2 * `TLB_WAY_WIDTH + `waypos_size:2 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_1GB) | (tlb_dataout[2 * `TLB_WAY_WIDTH + `waypos_size:2 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_256MB); + assign tlb_way2_cmpmask_d[2] = (tlb_dataout[2 * `TLB_WAY_WIDTH + `waypos_size:2 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_1GB) | (tlb_dataout[2 * `TLB_WAY_WIDTH + `waypos_size:2 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_256MB) | (tlb_dataout[2 * `TLB_WAY_WIDTH + `waypos_size:2 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_16MB); + assign tlb_way2_cmpmask_d[3] = (tlb_dataout[2 * `TLB_WAY_WIDTH + `waypos_size:2 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_1GB) | (tlb_dataout[2 * `TLB_WAY_WIDTH + `waypos_size:2 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_256MB) | (tlb_dataout[2 * `TLB_WAY_WIDTH + `waypos_size:2 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_16MB) | (tlb_dataout[2 * `TLB_WAY_WIDTH + `waypos_size:2 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_1MB); + assign tlb_way2_cmpmask_d[4] = (tlb_dataout[2 * `TLB_WAY_WIDTH + `waypos_size:2 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_1GB) | (tlb_dataout[2 * `TLB_WAY_WIDTH + `waypos_size:2 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_256MB) | (tlb_dataout[2 * `TLB_WAY_WIDTH + `waypos_size:2 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_16MB) | (tlb_dataout[2 * `TLB_WAY_WIDTH + `waypos_size:2 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_1MB) | (tlb_dataout[2 * `TLB_WAY_WIDTH + `waypos_size:2 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_64KB); + assign tlb_way2_xbitmask_d[0] = (tlb_dataout[2 * `TLB_WAY_WIDTH + `waypos_size:2 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_1GB); + assign tlb_way2_xbitmask_d[1] = (tlb_dataout[2 * `TLB_WAY_WIDTH + `waypos_size:2 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_256MB); + assign tlb_way2_xbitmask_d[2] = (tlb_dataout[2 * `TLB_WAY_WIDTH + `waypos_size:2 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_16MB); + assign tlb_way2_xbitmask_d[3] = (tlb_dataout[2 * `TLB_WAY_WIDTH + `waypos_size:2 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_1MB); + assign tlb_way2_xbitmask_d[4] = (tlb_dataout[2 * `TLB_WAY_WIDTH + `waypos_size:2 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_64KB); + assign tlb_way3_cmpmask_d[0] = (tlb_dataout[3 * `TLB_WAY_WIDTH + `waypos_size:3 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_1GB); + assign tlb_way3_cmpmask_d[1] = (tlb_dataout[3 * `TLB_WAY_WIDTH + `waypos_size:3 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_1GB) | (tlb_dataout[3 * `TLB_WAY_WIDTH + `waypos_size:3 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_256MB); + assign tlb_way3_cmpmask_d[2] = (tlb_dataout[3 * `TLB_WAY_WIDTH + `waypos_size:3 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_1GB) | (tlb_dataout[3 * `TLB_WAY_WIDTH + `waypos_size:3 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_256MB) | (tlb_dataout[3 * `TLB_WAY_WIDTH + `waypos_size:3 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_16MB); + assign tlb_way3_cmpmask_d[3] = (tlb_dataout[3 * `TLB_WAY_WIDTH + `waypos_size:3 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_1GB) | (tlb_dataout[3 * `TLB_WAY_WIDTH + `waypos_size:3 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_256MB) | (tlb_dataout[3 * `TLB_WAY_WIDTH + `waypos_size:3 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_16MB) | (tlb_dataout[3 * `TLB_WAY_WIDTH + `waypos_size:3 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_1MB); + assign tlb_way3_cmpmask_d[4] = (tlb_dataout[3 * `TLB_WAY_WIDTH + `waypos_size:3 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_1GB) | (tlb_dataout[3 * `TLB_WAY_WIDTH + `waypos_size:3 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_256MB) | (tlb_dataout[3 * `TLB_WAY_WIDTH + `waypos_size:3 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_16MB) | (tlb_dataout[3 * `TLB_WAY_WIDTH + `waypos_size:3 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_1MB) | (tlb_dataout[3 * `TLB_WAY_WIDTH + `waypos_size:3 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_64KB); + assign tlb_way3_xbitmask_d[0] = (tlb_dataout[3 * `TLB_WAY_WIDTH + `waypos_size:3 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_1GB); + assign tlb_way3_xbitmask_d[1] = (tlb_dataout[3 * `TLB_WAY_WIDTH + `waypos_size:3 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_256MB); + assign tlb_way3_xbitmask_d[2] = (tlb_dataout[3 * `TLB_WAY_WIDTH + `waypos_size:3 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_16MB); + assign tlb_way3_xbitmask_d[3] = (tlb_dataout[3 * `TLB_WAY_WIDTH + `waypos_size:3 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_1MB); + assign tlb_way3_xbitmask_d[4] = (tlb_dataout[3 * `TLB_WAY_WIDTH + `waypos_size:3 * `TLB_WAY_WIDTH + `waypos_size + 3] == TLB_PgSize_64KB); + // TLB Parity Checking + assign tlb_way0_lo_calc_par[0] = ^(tlb_way0_q[0:7]); + assign tlb_way0_lo_calc_par[1] = ^(tlb_way0_q[8:15]); + assign tlb_way0_lo_calc_par[2] = ^(tlb_way0_q[16:23]); + assign tlb_way0_lo_calc_par[3] = ^(tlb_way0_q[24:31]); + assign tlb_way0_lo_calc_par[4] = ^(tlb_way0_q[32:39]); + assign tlb_way0_lo_calc_par[5] = ^(tlb_way0_q[40:47]); + assign tlb_way0_lo_calc_par[6] = ^(tlb_way0_q[48:51]); + assign tlb_way0_lo_calc_par[7] = ^(tlb_way0_q[52:59]); + assign tlb_way0_lo_calc_par[8] = ^(tlb_way0_q[60:65]); + assign tlb_way0_lo_calc_par[9] = ^(tlb_way0_q[66:73]); + assign tlb_way1_lo_calc_par[0] = ^(tlb_way1_q[0:7]); + assign tlb_way1_lo_calc_par[1] = ^(tlb_way1_q[8:15]); + assign tlb_way1_lo_calc_par[2] = ^(tlb_way1_q[16:23]); + assign tlb_way1_lo_calc_par[3] = ^(tlb_way1_q[24:31]); + assign tlb_way1_lo_calc_par[4] = ^(tlb_way1_q[32:39]); + assign tlb_way1_lo_calc_par[5] = ^(tlb_way1_q[40:47]); + assign tlb_way1_lo_calc_par[6] = ^(tlb_way1_q[48:51]); + assign tlb_way1_lo_calc_par[7] = ^(tlb_way1_q[52:59]); + assign tlb_way1_lo_calc_par[8] = ^(tlb_way1_q[60:65]); + assign tlb_way1_lo_calc_par[9] = ^(tlb_way1_q[66:73]); + assign tlb_way2_lo_calc_par[0] = ^(tlb_way2_q[0:7]); + assign tlb_way2_lo_calc_par[1] = ^(tlb_way2_q[8:15]); + assign tlb_way2_lo_calc_par[2] = ^(tlb_way2_q[16:23]); + assign tlb_way2_lo_calc_par[3] = ^(tlb_way2_q[24:31]); + assign tlb_way2_lo_calc_par[4] = ^(tlb_way2_q[32:39]); + assign tlb_way2_lo_calc_par[5] = ^(tlb_way2_q[40:47]); + assign tlb_way2_lo_calc_par[6] = ^(tlb_way2_q[48:51]); + assign tlb_way2_lo_calc_par[7] = ^(tlb_way2_q[52:59]); + assign tlb_way2_lo_calc_par[8] = ^(tlb_way2_q[60:65]); + assign tlb_way2_lo_calc_par[9] = ^(tlb_way2_q[66:73]); + assign tlb_way3_lo_calc_par[0] = ^(tlb_way3_q[0:7]); + assign tlb_way3_lo_calc_par[1] = ^(tlb_way3_q[8:15]); + assign tlb_way3_lo_calc_par[2] = ^(tlb_way3_q[16:23]); + assign tlb_way3_lo_calc_par[3] = ^(tlb_way3_q[24:31]); + assign tlb_way3_lo_calc_par[4] = ^(tlb_way3_q[32:39]); + assign tlb_way3_lo_calc_par[5] = ^(tlb_way3_q[40:47]); + assign tlb_way3_lo_calc_par[6] = ^(tlb_way3_q[48:51]); + assign tlb_way3_lo_calc_par[7] = ^(tlb_way3_q[52:59]); + assign tlb_way3_lo_calc_par[8] = ^(tlb_way3_q[60:65]); + assign tlb_way3_lo_calc_par[9] = ^(tlb_way3_q[66:73]); + assign tlb_way0_hi_calc_par[0] = ^(tlb_way0_q[`TLB_WORD_WIDTH + 0:`TLB_WORD_WIDTH + 7]); + assign tlb_way0_hi_calc_par[1] = ^(tlb_way0_q[`TLB_WORD_WIDTH + 8:`TLB_WORD_WIDTH + 15]); + assign tlb_way0_hi_calc_par[2] = ^(tlb_way0_q[`TLB_WORD_WIDTH + 16:`TLB_WORD_WIDTH + 23]); + assign tlb_way0_hi_calc_par[3] = ^(tlb_way0_q[`TLB_WORD_WIDTH + 24:`TLB_WORD_WIDTH + 31]); + assign tlb_way0_hi_calc_par[4] = ^(tlb_way0_q[`TLB_WORD_WIDTH + 32:`TLB_WORD_WIDTH + 39]); + assign tlb_way0_hi_calc_par[5] = ^(tlb_way0_q[`TLB_WORD_WIDTH + 40:`TLB_WORD_WIDTH + 44]); + assign tlb_way0_hi_calc_par[6] = ^(tlb_way0_q[`TLB_WORD_WIDTH + 45:`TLB_WORD_WIDTH + 49]); + assign tlb_way0_hi_calc_par[7] = ^(tlb_way0_q[`TLB_WORD_WIDTH + 50:`TLB_WORD_WIDTH + 57]); + assign tlb_way0_hi_calc_par[8] = ^(tlb_way0_q[`TLB_WORD_WIDTH + 58:`TLB_WORD_WIDTH + 65]); + assign tlb_way0_hi_calc_par[9] = ^(tlb_way0_q[`TLB_WORD_WIDTH + 66:`TLB_WORD_WIDTH + 73]); + assign tlb_way1_hi_calc_par[0] = ^(tlb_way1_q[`TLB_WORD_WIDTH + 0:`TLB_WORD_WIDTH + 7]); + assign tlb_way1_hi_calc_par[1] = ^(tlb_way1_q[`TLB_WORD_WIDTH + 8:`TLB_WORD_WIDTH + 15]); + assign tlb_way1_hi_calc_par[2] = ^(tlb_way1_q[`TLB_WORD_WIDTH + 16:`TLB_WORD_WIDTH + 23]); + assign tlb_way1_hi_calc_par[3] = ^(tlb_way1_q[`TLB_WORD_WIDTH + 24:`TLB_WORD_WIDTH + 31]); + assign tlb_way1_hi_calc_par[4] = ^(tlb_way1_q[`TLB_WORD_WIDTH + 32:`TLB_WORD_WIDTH + 39]); + assign tlb_way1_hi_calc_par[5] = ^(tlb_way1_q[`TLB_WORD_WIDTH + 40:`TLB_WORD_WIDTH + 44]); + assign tlb_way1_hi_calc_par[6] = ^(tlb_way1_q[`TLB_WORD_WIDTH + 45:`TLB_WORD_WIDTH + 49]); + assign tlb_way1_hi_calc_par[7] = ^(tlb_way1_q[`TLB_WORD_WIDTH + 50:`TLB_WORD_WIDTH + 57]); + assign tlb_way1_hi_calc_par[8] = ^(tlb_way1_q[`TLB_WORD_WIDTH + 58:`TLB_WORD_WIDTH + 65]); + assign tlb_way1_hi_calc_par[9] = ^(tlb_way1_q[`TLB_WORD_WIDTH + 66:`TLB_WORD_WIDTH + 73]); + assign tlb_way2_hi_calc_par[0] = ^(tlb_way2_q[`TLB_WORD_WIDTH + 0:`TLB_WORD_WIDTH + 7]); + assign tlb_way2_hi_calc_par[1] = ^(tlb_way2_q[`TLB_WORD_WIDTH + 8:`TLB_WORD_WIDTH + 15]); + assign tlb_way2_hi_calc_par[2] = ^(tlb_way2_q[`TLB_WORD_WIDTH + 16:`TLB_WORD_WIDTH + 23]); + assign tlb_way2_hi_calc_par[3] = ^(tlb_way2_q[`TLB_WORD_WIDTH + 24:`TLB_WORD_WIDTH + 31]); + assign tlb_way2_hi_calc_par[4] = ^(tlb_way2_q[`TLB_WORD_WIDTH + 32:`TLB_WORD_WIDTH + 39]); + assign tlb_way2_hi_calc_par[5] = ^(tlb_way2_q[`TLB_WORD_WIDTH + 40:`TLB_WORD_WIDTH + 44]); + assign tlb_way2_hi_calc_par[6] = ^(tlb_way2_q[`TLB_WORD_WIDTH + 45:`TLB_WORD_WIDTH + 49]); + assign tlb_way2_hi_calc_par[7] = ^(tlb_way2_q[`TLB_WORD_WIDTH + 50:`TLB_WORD_WIDTH + 57]); + assign tlb_way2_hi_calc_par[8] = ^(tlb_way2_q[`TLB_WORD_WIDTH + 58:`TLB_WORD_WIDTH + 65]); + assign tlb_way2_hi_calc_par[9] = ^(tlb_way2_q[`TLB_WORD_WIDTH + 66:`TLB_WORD_WIDTH + 73]); + assign tlb_way3_hi_calc_par[0] = ^(tlb_way3_q[`TLB_WORD_WIDTH + 0:`TLB_WORD_WIDTH + 7]); + assign tlb_way3_hi_calc_par[1] = ^(tlb_way3_q[`TLB_WORD_WIDTH + 8:`TLB_WORD_WIDTH + 15]); + assign tlb_way3_hi_calc_par[2] = ^(tlb_way3_q[`TLB_WORD_WIDTH + 16:`TLB_WORD_WIDTH + 23]); + assign tlb_way3_hi_calc_par[3] = ^(tlb_way3_q[`TLB_WORD_WIDTH + 24:`TLB_WORD_WIDTH + 31]); + assign tlb_way3_hi_calc_par[4] = ^(tlb_way3_q[`TLB_WORD_WIDTH + 32:`TLB_WORD_WIDTH + 39]); + assign tlb_way3_hi_calc_par[5] = ^(tlb_way3_q[`TLB_WORD_WIDTH + 40:`TLB_WORD_WIDTH + 44]); + assign tlb_way3_hi_calc_par[6] = ^(tlb_way3_q[`TLB_WORD_WIDTH + 45:`TLB_WORD_WIDTH + 49]); + assign tlb_way3_hi_calc_par[7] = ^(tlb_way3_q[`TLB_WORD_WIDTH + 50:`TLB_WORD_WIDTH + 57]); + assign tlb_way3_hi_calc_par[8] = ^(tlb_way3_q[`TLB_WORD_WIDTH + 58:`TLB_WORD_WIDTH + 65]); + assign tlb_way3_hi_calc_par[9] = ^(tlb_way3_q[`TLB_WORD_WIDTH + 66:`TLB_WORD_WIDTH + 73]); + assign tlb_way0_parerr = |(tlb_way0_lo_calc_par[0:9] ^ tlb_way0_q[74:83]) | |(tlb_way0_hi_calc_par[0:9] ^ tlb_way0_q[`TLB_WORD_WIDTH + 74:`TLB_WORD_WIDTH + 83]); + assign tag4_parerr_d[0] = tlb_way0_parerr; + assign tlb_way1_parerr = |(tlb_way1_lo_calc_par[0:9] ^ tlb_way1_q[74:83]) | |(tlb_way1_hi_calc_par[0:9] ^ tlb_way1_q[`TLB_WORD_WIDTH + 74:`TLB_WORD_WIDTH + 83]); + assign tag4_parerr_d[1] = tlb_way1_parerr; + assign tlb_way2_parerr = |(tlb_way2_lo_calc_par[0:9] ^ tlb_way2_q[74:83]) | |(tlb_way2_hi_calc_par[0:9] ^ tlb_way2_q[`TLB_WORD_WIDTH + 74:`TLB_WORD_WIDTH + 83]); + assign tag4_parerr_d[2] = tlb_way2_parerr; + assign tlb_way3_parerr = |(tlb_way3_lo_calc_par[0:9] ^ tlb_way3_q[74:83]) | |(tlb_way3_hi_calc_par[0:9] ^ tlb_way3_q[`TLB_WORD_WIDTH + 74:`TLB_WORD_WIDTH + 83]); + assign tag4_parerr_d[3] = tlb_way3_parerr; + // end of TLB Parity Checking + + assign tlb_tag4_parerr_write = ((xu_mm_xucr4_mmu_mchk_q == 1'b0 & xu_mm_ccr2_notlb_b == 1'b1 & + ((tlb_tag4_q[`tagpos_type_derat] == 1'b1 | tlb_tag4_q[`tagpos_type_ierat] == 1'b1) & tlb_tag4_q[`tagpos_type_ptereload] == 1'b0) & + |(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & tlb_tag4_q[`tagpos_nonspec] == 1'b1 )) ? tag4_parerr_q[0:`TLB_WAYS-1] : + `TLB_WAYS'b0; + + assign tlb_tag4_parerr_zeroize = ((xu_mm_xucr4_mmu_mchk_q == 1'b0 & xu_mm_ccr2_notlb_b == 1'b1 & + ((tlb_tag4_q[`tagpos_type_derat] == 1'b1 | tlb_tag4_q[`tagpos_type_ierat] == 1'b1) & tlb_tag4_q[`tagpos_type_ptereload] == 1'b0) & + |(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & tlb_tag4_q[`tagpos_nonspec] == 1'b1 )) ? |(tag4_parerr_q[0:`TLB_WAYS-1]) : + 1'b0; + + assign tlb_tag5_parerr_zeroize = tlb_tag5_parerr_zeroize_q; + + + // lru data format + // 0:3 - valid(0:3) + // 4:6 - LRU + // 7 - parity + // 8:11 - iprot(0:3) + // 12:14 - reserved + // 15 - parity + assign lru_tag3_dataout_d = lru_dataout; + + // tag3 phase signals, tlbwe/re ex5, tlbsx/srx ex6 + // tlb_ctl may flush the thdid bits + assign tlb_tag4_d[0:`tagpos_thdid - 1] = tlb_tag3_q[0:`tagpos_thdid - 1]; + assign tlb_tag4_d[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] = + (((tlb_tag4_wayhit_q[`TLB_WAYS] == 1'b1 | tlb_tag4_q[`tagpos_endflag] == 1'b1 | |(tag4_parerr_q[0:4]) == 1'b1) & tlb_tag4_q[`tagpos_type_ptereload] == 1'b0 & (tlb_tag4_q[`tagpos_type_ierat] == 1'b1 | tlb_tag4_q[`tagpos_type_derat] == 1'b1))) ? {`MM_THREADS{1'b0}} : + (((tlb_tag4_wayhit_q[`TLB_WAYS] == 1'b1 | tlb_tag4_q[`tagpos_endflag] == 1'b1 | |(tag4_parerr_q[0:4]) == 1'b1) & (tlb_tag4_q[`tagpos_type_tlbsx] == 1'b1 | tlb_tag4_q[`tagpos_type_tlbsrx] == 1'b1))) ? {`MM_THREADS{1'b0}} : + ((tlb_tag4_q[`tagpos_endflag] == 1'b1 & tlb_tag4_q[`tagpos_type_snoop] == 1'b1)) ? {`MM_THREADS{1'b0}} : + (((tlb_tag4_q[`tagpos_type_tlbre] == 1'b1 | tlb_tag4_q[`tagpos_type_tlbwe] == 1'b1 | tlb_tag4_q[`tagpos_type_ptereload] == 1'b1) & |(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1)) ? {`MM_THREADS{1'b0}} : + tlb_tag3_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] & (~(tlb_ctl_tag3_flush)); + generate + if (`THDID_WIDTH > `MM_THREADS) + begin : tlbtag4NExist + assign tlb_tag4_d[`tagpos_thdid + `MM_THREADS:`tagpos_thdid + `THDID_WIDTH - 1] = + (((tlb_tag4_wayhit_q[`TLB_WAYS] == 1'b1 | tlb_tag4_q[`tagpos_endflag] == 1'b1 | |(tag4_parerr_q[0:4]) == 1'b1) & tlb_tag4_q[`tagpos_type_ptereload] == 1'b0 & (tlb_tag4_q[`tagpos_type_ierat] == 1'b1 | tlb_tag4_q[`tagpos_type_derat] == 1'b1))) ? {`THDID_WIDTH-`MM_THREADS{1'b0}} : + (((tlb_tag4_wayhit_q[`TLB_WAYS] == 1'b1 | tlb_tag4_q[`tagpos_endflag] == 1'b1 | |(tag4_parerr_q[0:4]) == 1'b1) & (tlb_tag4_q[`tagpos_type_tlbsx] == 1'b1 | tlb_tag4_q[`tagpos_type_tlbsrx] == 1'b1))) ? {`THDID_WIDTH-`MM_THREADS{1'b0}} : + ((tlb_tag4_q[`tagpos_endflag] == 1'b1 & tlb_tag4_q[`tagpos_type_snoop] == 1'b1)) ? {`THDID_WIDTH-`MM_THREADS{1'b0}} : + (((tlb_tag4_q[`tagpos_type_tlbre] == 1'b1 | tlb_tag4_q[`tagpos_type_tlbwe] == 1'b1 | tlb_tag4_q[`tagpos_type_ptereload] == 1'b1) & |(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1)) ? {`THDID_WIDTH-`MM_THREADS{1'b0}} : + tlb_tag3_q[`tagpos_thdid + `MM_THREADS:`tagpos_thdid + `THDID_WIDTH - 1]; + end + endgenerate + + assign tlb_tag4_d[`tagpos_thdid + `THDID_WIDTH:`TLB_TAG_WIDTH - 1] = tlb_tag3_q[`tagpos_thdid + `THDID_WIDTH:`TLB_TAG_WIDTH - 1]; + assign tlb_addr4_d = tlb_addr3_q; + + // chosen way logic + // `tagpos_type_derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload + // (ierat or derat) ptereload (tlbsx or tlbsrx) tlbre tlbwe tlb_wayhit MAS0.HES MAS0.ESEL old_lru tag4_way + // 1 0 x x x 0 x x x 0 + // 1 0 x x x 1 x x x 1 + // 1 0 x x x 2 x x x 2 + // 1 0 x x x 3 x x x 3 + // x 0 1 x x 0 x x x 0 + // x 0 1 x x 1 x x x 1 + // x 0 1 x x 2 x x x 2 + // x 0 1 x x 3 x x x 3 + // x x x 1 x x x 0 x 0 + // x x x 1 x x x 1 x 1 + // x x x 1 x x x 2 x 2 + // x x x 1 x x x 3 x 3 + // x x x x 1 x 0 0 x 0 + // x x x x 1 x 0 1 x 1 + // x x x x 1 x 0 2 x 2 + // x x x x 1 x 0 3 x 3 + // x x x x 1 x 1 x 0 0 + // x x x x 1 x 1 x 1 1 + // x x x x 1 x 1 x 2 2 + // x x x x 1 x 1 x 3 3 + // x 1 x x x x x x 0 0 + // x 1 x x x x x x 1 1 + // x 1 x x x x x x 2 2 + // x 1 x x x x x x 3 3 + + assign tlb_tag4_way_d = (tlb_way0_q & {`TLB_WAY_WIDTH{tlb_wayhit[0]}}) | (tlb_way1_q & {`TLB_WAY_WIDTH{tlb_wayhit[1]}}); + + assign tlb_tag4_way_clone_d = (tlb_way2_q & {`TLB_WAY_WIDTH{tlb_wayhit[2]}}) | (tlb_way3_q & {`TLB_WAY_WIDTH{tlb_wayhit[3]}}); + + assign tlb_tag4_way_or = tlb_tag4_way_q | tlb_tag4_way_clone_q; + + assign tlb_tag4_way_rw_d = ( tlb_way0_q & ( {`TLB_WAY_WIDTH{(~tlb_tag3_clone1_q[`tagpos_esel + 1]) & (~tlb_tag3_clone1_q[`tagpos_esel + 2]) & |(tlb_tag3_clone1_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) & + (tlb_tag3_clone1_q[`tagpos_type_tlbre] | (tlb_tag3_clone1_q[`tagpos_type_tlbwe] & (~tlb_tag3_clone1_q[`tagpos_hes])))}} ) ) | + + ( tlb_way1_q & ( {`TLB_WAY_WIDTH{(~tlb_tag3_clone1_q[`tagpos_esel + 1]) & tlb_tag3_clone1_q[`tagpos_esel + 2] & |(tlb_tag3_clone1_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) & + (tlb_tag3_clone1_q[`tagpos_type_tlbre] | (tlb_tag3_clone1_q[`tagpos_type_tlbwe] & (~tlb_tag3_clone1_q[`tagpos_hes])))}} ) ) | + + ( tlb_way0_q & ( {`TLB_WAY_WIDTH{(~lru_tag3_dataout_q[4]) & (~lru_tag3_dataout_q[5]) & |(tlb_tag3_clone1_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) & + (tlb_tag3_clone1_q[`tagpos_type_ptereload] | (tlb_tag3_clone1_q[`tagpos_type_tlbwe] & tlb_tag3_clone1_q[`tagpos_hes]))}} ) ) | + + ( tlb_way1_q & ( {`TLB_WAY_WIDTH{(~lru_tag3_dataout_q[4]) & lru_tag3_dataout_q[5] & |(tlb_tag3_clone1_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) & + (tlb_tag3_clone1_q[`tagpos_type_ptereload] | (tlb_tag3_clone1_q[`tagpos_type_tlbwe] & tlb_tag3_clone1_q[`tagpos_hes]))}} ) ); + + assign tlb_tag4_way_rw_clone_d = ( tlb_way2_q & ( {`TLB_WAY_WIDTH{tlb_tag3_clone2_q[`tagpos_esel + 1] & (~tlb_tag3_clone2_q[`tagpos_esel + 2]) & |(tlb_tag3_clone2_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) & + (tlb_tag3_clone2_q[`tagpos_type_tlbre] | (tlb_tag3_clone2_q[`tagpos_type_tlbwe] & (~tlb_tag3_clone2_q[`tagpos_hes])))}} ) ) | + + ( tlb_way3_q & ( {`TLB_WAY_WIDTH{tlb_tag3_clone2_q[`tagpos_esel + 1] & tlb_tag3_clone2_q[`tagpos_esel + 2] & |(tlb_tag3_clone2_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) & + (tlb_tag3_clone2_q[`tagpos_type_tlbre] | (tlb_tag3_clone2_q[`tagpos_type_tlbwe] & (~tlb_tag3_clone2_q[`tagpos_hes])))}} ) ) | + + ( tlb_way2_q & ( {`TLB_WAY_WIDTH{lru_tag3_dataout_q[4] & (~lru_tag3_dataout_q[6]) & |(tlb_tag3_clone2_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) & + (tlb_tag3_clone2_q[`tagpos_type_ptereload] | (tlb_tag3_clone2_q[`tagpos_type_tlbwe] & tlb_tag3_clone2_q[`tagpos_hes]))}} ) ) | + + ( tlb_way3_q & ( {`TLB_WAY_WIDTH{lru_tag3_dataout_q[4] & lru_tag3_dataout_q[6] & |(tlb_tag3_clone2_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) & + (tlb_tag3_clone2_q[`tagpos_type_ptereload] | (tlb_tag3_clone2_q[`tagpos_type_tlbwe] & tlb_tag3_clone2_q[`tagpos_hes]))}} ) ); + + assign tlb_tag4_way_rw_or = tlb_tag4_way_rw_q | tlb_tag4_way_rw_clone_q; + + assign tlb_tag4_wayhit_d[0:`TLB_WAYS - 1] = tlb_wayhit[0:`TLB_WAYS - 1]; + + assign tlb_tag4_wayhit_d[`TLB_WAYS] = ((tlb_tag4_wayhit_q[`TLB_WAYS] == 1'b0 & |(tlb_wayhit[0:`TLB_WAYS - 1]) == 1'b1 & |(tlb_tag3_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1)) ? 1'b1 : + 1'b0; + + assign tlb_tag4_way_act = (|(tlb_tag3_clone1_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1])) & (~(tlb_tag4_wayhit_q[`TLB_WAYS])) & (~tlb_tag3_clone1_q[`tagpos_type_ptereload]) & + (tlb_tag3_clone1_q[`tagpos_type_derat] | tlb_tag3_clone1_q[`tagpos_type_ierat] | tlb_tag3_clone1_q[`tagpos_type_tlbsx] | tlb_tag3_clone1_q[`tagpos_type_tlbsrx]); + + assign tlb_tag4_way_clone_act = (|(tlb_tag3_clone2_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1])) & (~(tlb_tag4_wayhit_q[`TLB_WAYS])) & (~tlb_tag3_clone2_q[`tagpos_type_ptereload]) & + (tlb_tag3_clone2_q[`tagpos_type_derat] | tlb_tag3_clone2_q[`tagpos_type_ierat] | tlb_tag3_clone2_q[`tagpos_type_tlbsx] | tlb_tag3_clone2_q[`tagpos_type_tlbsrx]); + + assign tlb_tag4_way_rw_act = (|(tlb_tag3_clone1_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1])) & + (tlb_tag3_clone1_q[`tagpos_type_tlbre] | tlb_tag3_clone1_q[`tagpos_type_tlbwe] | tlb_tag3_clone1_q[`tagpos_type_ptereload]); + + assign tlb_tag4_way_rw_clone_act = (|(tlb_tag3_clone2_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1])) & + (tlb_tag3_clone2_q[`tagpos_type_tlbre] | tlb_tag3_clone2_q[`tagpos_type_tlbwe] | tlb_tag3_clone2_q[`tagpos_type_ptereload]); + + assign lru_tag4_dataout_d = lru_tag3_dataout_q; + + + //tlb_tag3_d <= ( 0:51 epn & + // 52:65 pid & + // 66:67 IS & + // 68:69 Class & + // 70:73 state (pr,gs,as,cm) & + // 74:77 thdid & + // 78:81 size & + // 82:83 derat_miss/ierat_miss & + // 84:85 tlbsx/tlbsrx & + // 86:87 inval_snoop/tlbre & + // 88:89 tlbwe/ptereload & + // 90:97 lpid & + // 98 indirect + // 99 atsel & + // 100:102 esel & + // 103:105 hes/wq(0:1) & + // 106:107 lrat/pt & + // 108 record form + // 109 endflag + // `tagpos_epn : natural := 0; + // `tagpos_pid : natural := 52; -- 14 bits + // `tagpos_is : natural := 66; + // `tagpos_class : natural := 68; + // `tagpos_state : natural := 70; -- state: 0:pr 1:gs 2:as 3:cm + // `tagpos_thdid : natural := 74; + // `tagpos_size : natural := 78; + // `tagpos_type : natural := 82; -- derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload + // `tagpos_lpid : natural := 90; + // `tagpos_ind : natural := 98; + // `tagpos_atsel : natural := 99; + // `tagpos_esel : natural := 100; + // `tagpos_hes : natural := 103; + // `tagpos_wq : natural := 104; + // `tagpos_lrat : natural := 106; + // `tagpos_pt : natural := 107; + // `tagpos_recform : natural := 108; + // `tagpos_endflag : natural := 109; + + // For snoop ttypes... + // `tagpos_is -> IS(0): Local snoop + // `tagpos_is+1 to `tagpos_is+3 -> IS(1)/Class: 0=all in lpar, 1=tid, 2=gs, 3=vpn, 4=class0, 5=class1, 6=class2, 7=class3 + + // bits 0-7: override for chunks of msb of address for bus snoops, depends on pgsize and mmucr1.tlbi_msb bit + // mmucr1 11-LRUPEI, 12:13-ICTID/ITTID, 14:15-DCTID/DTTID, 16-DCCD, 17-TLBWE_BINV, 18-TLBI_MSB + + // size tlb_tag3_cmpmask_q: 01234 + // 1GB 11111 + // 256MB 01111 + // 16MB 00111 + // 1MB 00011 + // 64KB 00001 + // 4KB 00000 + + assign addr_enable[0] = (|(tlb_tag3_clone1_q[`tagpos_type_derat:`tagpos_type_tlbsrx]) & (~tlb_tag3_clone1_q[`tagpos_type_ptereload])) | + (tlb_tag3_clone1_q[`tagpos_type_snoop] & (tlb_tag3_clone1_q[`tagpos_is:`tagpos_is + 3] == 4'b1011)); + + assign addr_enable[1] = (|(tlb_tag3_clone1_q[`tagpos_type_derat:`tagpos_type_tlbsrx]) & (~tlb_tag3_clone1_q[`tagpos_type_ptereload])) | + (tlb_tag3_clone1_q[`tagpos_type_snoop] & (tlb_tag3_clone1_q[`tagpos_is:`tagpos_is + 3] == 4'b1011)) | + (tlb_tag3_clone1_q[`tagpos_type_snoop] & (tlb_tag3_clone1_q[`tagpos_is:`tagpos_is + 3] == 4'b0011) & mmucr1_q[pos_tlbi_msb] & tlb_tag3_cmpmask_q[0]); + + assign addr_enable[2] = (|(tlb_tag3_clone1_q[`tagpos_type_derat:`tagpos_type_tlbsrx]) & (~tlb_tag3_clone1_q[`tagpos_type_ptereload])) | + (tlb_tag3_clone1_q[`tagpos_type_snoop] & (tlb_tag3_clone1_q[`tagpos_is:`tagpos_is + 3] == 4'b1011)) | + (tlb_tag3_clone1_q[`tagpos_type_snoop] & (tlb_tag3_clone1_q[`tagpos_is:`tagpos_is + 3] == 4'b0011) & mmucr1_q[pos_tlbi_msb] & tlb_tag3_cmpmask_q[1]); + + assign addr_enable[3] = (|(tlb_tag3_clone1_q[`tagpos_type_derat:`tagpos_type_tlbsrx]) & (~tlb_tag3_clone1_q[`tagpos_type_ptereload])) | + (tlb_tag3_clone1_q[`tagpos_type_snoop] & (tlb_tag3_clone1_q[`tagpos_is:`tagpos_is + 3] == 4'b1011)) | + (tlb_tag3_clone1_q[`tagpos_type_snoop] & (tlb_tag3_clone1_q[`tagpos_is:`tagpos_is + 3] == 4'b0011) & mmucr1_q[pos_tlbi_msb] & tlb_tag3_cmpmask_q[1]) | + (tlb_tag3_clone1_q[`tagpos_type_snoop] & (tlb_tag3_clone1_q[`tagpos_is:`tagpos_is + 3] == 4'b0011) & (~mmucr1_q[pos_tlbi_msb]) & tlb_tag3_cmpmask_q[0]); + + assign addr_enable[4] = (|(tlb_tag3_clone1_q[`tagpos_type_derat:`tagpos_type_tlbsrx]) & (~tlb_tag3_clone1_q[`tagpos_type_ptereload])) | + (tlb_tag3_clone1_q[`tagpos_type_snoop] & (tlb_tag3_clone1_q[`tagpos_is:`tagpos_is + 3] == 4'b1011)) | + (tlb_tag3_clone1_q[`tagpos_type_snoop] & (tlb_tag3_clone1_q[`tagpos_is:`tagpos_is + 3] == 4'b0011) & mmucr1_q[pos_tlbi_msb] & tlb_tag3_cmpmask_q[2]) | + (tlb_tag3_clone1_q[`tagpos_type_snoop] & (tlb_tag3_clone1_q[`tagpos_is:`tagpos_is + 3] == 4'b0011) & (~mmucr1_q[pos_tlbi_msb]) & tlb_tag3_cmpmask_q[1]); + + assign addr_enable[5] = (|(tlb_tag3_clone1_q[`tagpos_type_derat:`tagpos_type_tlbsrx]) & (~tlb_tag3_clone1_q[`tagpos_type_ptereload])) | + (tlb_tag3_clone1_q[`tagpos_type_snoop] & (tlb_tag3_clone1_q[`tagpos_is:`tagpos_is + 3] == 4'b1011)) | + (tlb_tag3_clone1_q[`tagpos_type_snoop] & (tlb_tag3_clone1_q[`tagpos_is:`tagpos_is + 3] == 4'b0011) & mmucr1_q[pos_tlbi_msb] & tlb_tag3_cmpmask_q[3]) | + (tlb_tag3_clone1_q[`tagpos_type_snoop] & (tlb_tag3_clone1_q[`tagpos_is:`tagpos_is + 3] == 4'b0011) & (~mmucr1_q[pos_tlbi_msb]) & tlb_tag3_cmpmask_q[2]); + + assign addr_enable[6] = (|(tlb_tag3_clone1_q[`tagpos_type_derat:`tagpos_type_tlbsrx]) & (~tlb_tag3_clone1_q[`tagpos_type_ptereload])) | + (tlb_tag3_clone1_q[`tagpos_type_snoop] & (tlb_tag3_clone1_q[`tagpos_is:`tagpos_is + 3] == 4'b1011)) | + (tlb_tag3_clone1_q[`tagpos_type_snoop] & (tlb_tag3_clone1_q[`tagpos_is:`tagpos_is + 3] == 4'b0011) & mmucr1_q[pos_tlbi_msb]) | + (tlb_tag3_clone1_q[`tagpos_type_snoop] & (tlb_tag3_clone1_q[`tagpos_is:`tagpos_is + 3] == 4'b0011) & (~mmucr1_q[pos_tlbi_msb]) & tlb_tag3_cmpmask_q[3]); + + assign addr_enable[7] = (|(tlb_tag3_clone1_q[`tagpos_type_derat:`tagpos_type_tlbsrx]) & (~tlb_tag3_clone1_q[`tagpos_type_ptereload])) | + (tlb_tag3_clone1_q[`tagpos_type_snoop] & (tlb_tag3_clone1_q[`tagpos_is + 1:`tagpos_is + 3] == 3'b011)); + + // bit 8: override to ignore all address bits + assign addr_enable[8] = (|(tlb_tag3_clone1_q[`tagpos_type_derat:`tagpos_type_tlbsrx]) & (~tlb_tag3_clone1_q[`tagpos_type_ptereload])) | + (tlb_tag3_clone1_q[`tagpos_type_snoop] & (tlb_tag3_clone1_q[`tagpos_is + 1:`tagpos_is + 3] == 3'b011)); + + assign class_enable = ((tlb_tag3_clone1_q[`tagpos_type_snoop] == 1'b1 & tlb_tag3_clone1_q[`tagpos_is + 1] == 1'b1)) ? 1'b1 : + 1'b0; + + assign pgsize_enable = tlb_tag3_clone1_q[`tagpos_type_snoop] & (tlb_tag3_clone1_q[`tagpos_is + 1:`tagpos_is + 3] == 3'b011); + + assign extclass_enable = 2'b00; + + // `tagpos_type : natural := 82; -- derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload + //thdid_enable <= '1' when (tlb_tag3_clone1_q(`tagpos_type_derat to `tagpos_type_ierat) /= 00 and tlb_tag3_clone1_q(`tagpos_type_ptereload)='0') + // else '0'; -- derat,ierat + + assign thdid_enable = (|(tlb_tag3_clone1_q[`tagpos_type_derat:`tagpos_type_tlbsrx])) & (~tlb_tag3_clone1_q[`tagpos_type_ptereload]); + + assign pid_enable = ((tlb_tag3_clone1_q[`tagpos_type_derat:`tagpos_type_tlbsrx] != 4'b0000 & tlb_tag3_clone1_q[`tagpos_type_ptereload] == 1'b0)) ? 1'b1 : + ((tlb_tag3_clone1_q[`tagpos_type_snoop] == 1'b1 & tlb_tag3_clone1_q[`tagpos_is + 1:`tagpos_is + 3] == 3'b001)) ? 1'b1 : + ((tlb_tag3_clone1_q[`tagpos_type_snoop] == 1'b1 & tlb_tag3_clone1_q[`tagpos_is + 1:`tagpos_is + 3] == 3'b011)) ? 1'b1 : + 1'b0; + // gs enable + assign state_enable[0] = ((tlb_tag3_clone1_q[`tagpos_type_derat:`tagpos_type_tlbsrx] != 4'b0000 & tlb_tag3_clone1_q[`tagpos_type_ptereload] == 1'b0)) ? 1'b1 : + ((tlb_tag3_clone1_q[`tagpos_type_snoop] == 1'b1 & tlb_tag3_clone1_q[`tagpos_is + 1:`tagpos_is + 3] == 3'b010)) ? 1'b1 : + ((tlb_tag3_clone1_q[`tagpos_type_snoop] == 1'b1 & tlb_tag3_clone1_q[`tagpos_is + 1:`tagpos_is + 3] == 3'b011)) ? 1'b1 : + 1'b0; + // as enable + assign state_enable[1] = ((tlb_tag3_clone1_q[`tagpos_type_derat:`tagpos_type_tlbsrx] != 4'b0000 & tlb_tag3_clone1_q[`tagpos_type_ptereload] == 1'b0)) ? 1'b1 : + ((tlb_tag3_clone1_q[`tagpos_type_snoop] == 1'b1 & tlb_tag3_clone1_q[`tagpos_is + 1:`tagpos_is + 3] == 3'b011)) ? 1'b1 : + 1'b0; + assign lpid_enable = ((tlb_tag3_clone1_q[`tagpos_type_derat:`tagpos_type_tlbsrx] != 4'b0000 & tlb_tag3_clone1_q[`tagpos_type_ptereload] == 1'b0)) ? 1'b1 : + ((tlb_tag3_clone1_q[`tagpos_type_snoop] == 1'b1)) ? (~(tlb_tag3_clone1_q[`tagpos_hes])) : + 1'b0; + assign ind_enable = ( |(tlb_tag3_clone1_q[`tagpos_type_derat:`tagpos_type_tlbsrx]) & (~tlb_tag3_clone1_q[`tagpos_type_ptereload]) ) | + ( tlb_tag3_clone1_q[`tagpos_type_snoop] & (tlb_tag3_clone1_q[`tagpos_is + 1:`tagpos_is + 3] == 3'b011) ) | + ( tlb_tag3_clone1_q[`tagpos_type_snoop] & (tlb_tag3_clone1_q[`tagpos_is + 1:`tagpos_is + 3] == 3'b001) & tlb_tag3_clone1_q[`tagpos_ind] ); + + assign iprot_enable = tlb_tag3_clone1_q[`tagpos_type_snoop]; + + // For snoop ttypes... + // `tagpos_is -> IS(0): Local snoop + // `tagpos_is+1 to `tagpos_is+3 -> IS(1)/Class: 0=all in lpar, 1=tid, 2=gs, 3=vpn, 4=class0, 5=class1, 6=class2, 7=class3 + assign comp_extclass = 2'b00; + + assign comp_iprot = 1'b0; + + // added for ISA v2.06 addendum: tlbilx T=1 by pid, use mas6.sind as ind bit compare enable, compare value=0 + assign comp_ind = tlb_tag3_clone1_q[`tagpos_ind] & (~(tlb_tag3_clone1_q[`tagpos_type_snoop] & (tlb_tag3_clone1_q[`tagpos_is + 1:`tagpos_is + 3] == 3'b001))); + + //----------------- cloned compare logic, for timing: tlb array 0/1 on set above, tlb array 2/3 on set below + assign addr_enable_clone[0] = (|(tlb_tag3_clone2_q[`tagpos_type_derat:`tagpos_type_tlbsrx]) & (~tlb_tag3_clone2_q[`tagpos_type_ptereload])) | + (tlb_tag3_clone2_q[`tagpos_type_snoop] & (tlb_tag3_clone2_q[`tagpos_is:`tagpos_is + 3] == 4'b1011)); + + assign addr_enable_clone[1] = (|(tlb_tag3_clone2_q[`tagpos_type_derat:`tagpos_type_tlbsrx]) & (~tlb_tag3_clone2_q[`tagpos_type_ptereload])) | + (tlb_tag3_clone2_q[`tagpos_type_snoop] & (tlb_tag3_clone2_q[`tagpos_is:`tagpos_is + 3] == 4'b1011)) | + (tlb_tag3_clone2_q[`tagpos_type_snoop] & (tlb_tag3_clone2_q[`tagpos_is:`tagpos_is + 3] == 4'b0011) & mmucr1_clone_q[pos_tlbi_msb] & tlb_tag3_cmpmask_clone_q[0]); + + assign addr_enable_clone[2] = (|(tlb_tag3_clone2_q[`tagpos_type_derat:`tagpos_type_tlbsrx]) & (~tlb_tag3_clone2_q[`tagpos_type_ptereload])) | + (tlb_tag3_clone2_q[`tagpos_type_snoop] & (tlb_tag3_clone2_q[`tagpos_is:`tagpos_is + 3] == 4'b1011)) | + (tlb_tag3_clone2_q[`tagpos_type_snoop] & (tlb_tag3_clone2_q[`tagpos_is:`tagpos_is + 3] == 4'b0011) & mmucr1_clone_q[pos_tlbi_msb] & tlb_tag3_cmpmask_clone_q[1]); + + assign addr_enable_clone[3] = (|(tlb_tag3_clone2_q[`tagpos_type_derat:`tagpos_type_tlbsrx]) & (~tlb_tag3_clone2_q[`tagpos_type_ptereload])) | + (tlb_tag3_clone2_q[`tagpos_type_snoop] & (tlb_tag3_clone2_q[`tagpos_is:`tagpos_is + 3] == 4'b1011)) | + (tlb_tag3_clone2_q[`tagpos_type_snoop] & (tlb_tag3_clone2_q[`tagpos_is:`tagpos_is + 3] == 4'b0011) & mmucr1_clone_q[pos_tlbi_msb] & tlb_tag3_cmpmask_clone_q[1]) | + (tlb_tag3_clone2_q[`tagpos_type_snoop] & (tlb_tag3_clone2_q[`tagpos_is:`tagpos_is + 3] == 4'b0011) & (~mmucr1_clone_q[pos_tlbi_msb]) & tlb_tag3_cmpmask_clone_q[0]); + + assign addr_enable_clone[4] = (|(tlb_tag3_clone2_q[`tagpos_type_derat:`tagpos_type_tlbsrx]) & (~tlb_tag3_clone2_q[`tagpos_type_ptereload])) | + (tlb_tag3_clone2_q[`tagpos_type_snoop] & (tlb_tag3_clone2_q[`tagpos_is:`tagpos_is + 3] == 4'b1011)) | + (tlb_tag3_clone2_q[`tagpos_type_snoop] & (tlb_tag3_clone2_q[`tagpos_is:`tagpos_is + 3] == 4'b0011) & mmucr1_clone_q[pos_tlbi_msb] & tlb_tag3_cmpmask_clone_q[2]) | + (tlb_tag3_clone2_q[`tagpos_type_snoop] & (tlb_tag3_clone2_q[`tagpos_is:`tagpos_is + 3] == 4'b0011) & (~mmucr1_clone_q[pos_tlbi_msb]) & tlb_tag3_cmpmask_clone_q[1]); + + assign addr_enable_clone[5] = (|(tlb_tag3_clone2_q[`tagpos_type_derat:`tagpos_type_tlbsrx]) & (~tlb_tag3_clone2_q[`tagpos_type_ptereload])) | + (tlb_tag3_clone2_q[`tagpos_type_snoop] & (tlb_tag3_clone2_q[`tagpos_is:`tagpos_is + 3] == 4'b1011)) | + (tlb_tag3_clone2_q[`tagpos_type_snoop] & (tlb_tag3_clone2_q[`tagpos_is:`tagpos_is + 3] == 4'b0011) & mmucr1_clone_q[pos_tlbi_msb] & tlb_tag3_cmpmask_clone_q[3]) | + (tlb_tag3_clone2_q[`tagpos_type_snoop] & (tlb_tag3_clone2_q[`tagpos_is:`tagpos_is + 3] == 4'b0011) & (~mmucr1_clone_q[pos_tlbi_msb]) & tlb_tag3_cmpmask_clone_q[2]); + + assign addr_enable_clone[6] = (|(tlb_tag3_clone2_q[`tagpos_type_derat:`tagpos_type_tlbsrx]) & (~tlb_tag3_clone2_q[`tagpos_type_ptereload])) | + (tlb_tag3_clone2_q[`tagpos_type_snoop] & (tlb_tag3_clone2_q[`tagpos_is:`tagpos_is + 3] == 4'b1011)) | + (tlb_tag3_clone2_q[`tagpos_type_snoop] & (tlb_tag3_clone2_q[`tagpos_is:`tagpos_is + 3] == 4'b0011) & mmucr1_clone_q[pos_tlbi_msb]) | + (tlb_tag3_clone2_q[`tagpos_type_snoop] & (tlb_tag3_clone2_q[`tagpos_is:`tagpos_is + 3] == 4'b0011) & (~mmucr1_clone_q[pos_tlbi_msb]) & tlb_tag3_cmpmask_clone_q[3]); + + assign addr_enable_clone[7] = (|(tlb_tag3_clone2_q[`tagpos_type_derat:`tagpos_type_tlbsrx]) & (~tlb_tag3_clone2_q[`tagpos_type_ptereload])) | + (tlb_tag3_clone2_q[`tagpos_type_snoop] & (tlb_tag3_clone2_q[`tagpos_is + 1:`tagpos_is + 3] == 3'b011)); + + // bit 8: override to ignore all address bits + assign addr_enable_clone[8] = (|(tlb_tag3_clone2_q[`tagpos_type_derat:`tagpos_type_tlbsrx]) & (~tlb_tag3_clone2_q[`tagpos_type_ptereload])) | + (tlb_tag3_clone2_q[`tagpos_type_snoop] & (tlb_tag3_clone2_q[`tagpos_is + 1:`tagpos_is + 3] == 3'b011)); + + assign class_enable_clone = ((tlb_tag3_clone2_q[`tagpos_type_snoop] == 1'b1 & tlb_tag3_clone2_q[`tagpos_is + 1] == 1'b1)) ? 1'b1 : + 1'b0; + + assign pgsize_enable_clone = tlb_tag3_clone2_q[`tagpos_type_snoop] & (tlb_tag3_clone2_q[`tagpos_is + 1:`tagpos_is + 3] == 3'b011); + + assign extclass_enable_clone = 2'b00; + + // `tagpos_type : natural := 82; -- derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload + assign thdid_enable_clone = (|(tlb_tag3_clone2_q[`tagpos_type_derat:`tagpos_type_tlbsrx])) & (~tlb_tag3_clone2_q[`tagpos_type_ptereload]); + + assign pid_enable_clone = ((tlb_tag3_clone2_q[`tagpos_type_derat:`tagpos_type_tlbsrx] != 4'b0000 & tlb_tag3_clone2_q[`tagpos_type_ptereload] == 1'b0)) ? 1'b1 : + ((tlb_tag3_clone2_q[`tagpos_type_snoop] == 1'b1 & tlb_tag3_clone2_q[`tagpos_is + 1:`tagpos_is + 3] == 3'b001)) ? 1'b1 : + ((tlb_tag3_clone2_q[`tagpos_type_snoop] == 1'b1 & tlb_tag3_clone2_q[`tagpos_is + 1:`tagpos_is + 3] == 3'b011)) ? 1'b1 : + 1'b0; + // gs enable + assign state_enable_clone[0] = ((tlb_tag3_clone2_q[`tagpos_type_derat:`tagpos_type_tlbsrx] != 4'b0000 & tlb_tag3_clone2_q[`tagpos_type_ptereload] == 1'b0)) ? 1'b1 : + ((tlb_tag3_clone2_q[`tagpos_type_snoop] == 1'b1 & tlb_tag3_clone2_q[`tagpos_is + 1:`tagpos_is + 3] == 3'b010)) ? 1'b1 : + ((tlb_tag3_clone2_q[`tagpos_type_snoop] == 1'b1 & tlb_tag3_clone2_q[`tagpos_is + 1:`tagpos_is + 3] == 3'b011)) ? 1'b1 : + 1'b0; + // as enable + assign state_enable_clone[1] = ((tlb_tag3_clone2_q[`tagpos_type_derat:`tagpos_type_tlbsrx] != 4'b0000 & tlb_tag3_clone2_q[`tagpos_type_ptereload] == 1'b0)) ? 1'b1 : + ((tlb_tag3_clone2_q[`tagpos_type_snoop] == 1'b1 & tlb_tag3_clone2_q[`tagpos_is + 1:`tagpos_is + 3] == 3'b011)) ? 1'b1 : + 1'b0; + assign lpid_enable_clone = ((tlb_tag3_clone2_q[`tagpos_type_derat:`tagpos_type_tlbsrx] != 4'b0000 & tlb_tag3_clone2_q[`tagpos_type_ptereload] == 1'b0)) ? 1'b1 : + ((tlb_tag3_clone2_q[`tagpos_type_snoop] == 1'b1)) ? (~(tlb_tag3_clone2_q[`tagpos_hes])) : + 1'b0; + + assign ind_enable_clone = (|(tlb_tag3_clone2_q[`tagpos_type_derat:`tagpos_type_tlbsrx]) & (~tlb_tag3_clone2_q[`tagpos_type_ptereload])) | + (tlb_tag3_clone2_q[`tagpos_type_snoop] & (tlb_tag3_clone2_q[`tagpos_is + 1:`tagpos_is + 3] == 3'b011)) | + (tlb_tag3_clone2_q[`tagpos_type_snoop] & (tlb_tag3_clone2_q[`tagpos_is + 1:`tagpos_is + 3] == 3'b001) & tlb_tag3_clone2_q[`tagpos_ind]); + + assign iprot_enable_clone = tlb_tag3_clone2_q[`tagpos_type_snoop]; + + // For snoop ttypes... + // `tagpos_is -> IS(0): Local snoop + // `tagpos_is+1 to `tagpos_is+3 -> IS(1)/Class: 0=all in lpar, 1=tid, 2=gs, 3=vpn, 4=class0, 5=class1, 6=class2, 7=class3 + assign comp_extclass_clone = 2'b00; + + assign comp_iprot_clone = 1'b0; + + // added for ISA v2.06 addendum: tlbilx T=1 by pid, use mas6.sind as ind bit compare enable, compare value=0 + assign comp_ind_clone = tlb_tag3_clone2_q[`tagpos_ind] & (~(tlb_tag3_clone2_q[`tagpos_type_snoop] & (tlb_tag3_clone2_q[`tagpos_is + 1:`tagpos_is + 3] == 3'b001))); + + //----------------- end of cloned compare logic + + + // tag4 phase signals, tlbwe/re ex6, tlbsx/srx ex7 + assign tlb_tag4_type_sig[0:7] = tlb_tag4_q[`tagpos_type:`tagpos_type + 7]; + assign tlb_tag4_esel_sig[0:2] = tlb_tag4_q[`tagpos_esel:`tagpos_esel + 2]; + assign tlb_tag4_hes_sig = tlb_tag4_q[`tagpos_hes]; + assign tlb_tag4_wq_sig[0:1] = tlb_tag4_q[`tagpos_wq:`tagpos_wq + 1]; + assign tlb_tag4_is_sig[0:3] = tlb_tag4_q[`tagpos_is:`tagpos_is + 3]; + assign tlb_tag4_hv_op = |((~msr_gs_q) & (~msr_pr_q) & tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1]); + + assign multihit = (~((tlb_tag4_wayhit_q[0:3] == 4'b0000) | (tlb_tag4_wayhit_q[0:3] == 4'b1000) | + (tlb_tag4_wayhit_q[0:3] == 4'b0100) | (tlb_tag4_wayhit_q[0:3] == 4'b0010) | + (tlb_tag4_wayhit_q[0:3] == 4'b0001))) & |(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]); + + // unused `tagpos_is def is mas1_v, mas1_iprot for tlbwe, and is (pte.valid & 0) for ptereloads + // hes=1 valid bits update data + + assign tlb_tag4_hes1_mas1_v[0:`THDID_WIDTH - 1] = ( ({tlb_tag4_q[`tagpos_is], lru_tag4_dataout_q[1:3]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 0] & tlb_tag4_q[`tagpos_hes] & (~lru_tag4_dataout_q[4]) & (~lru_tag4_dataout_q[5]))}} ) | + ( ({lru_tag4_dataout_q[0], tlb_tag4_q[`tagpos_is], lru_tag4_dataout_q[2:3]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 0] & tlb_tag4_q[`tagpos_hes] & (~lru_tag4_dataout_q[4]) & lru_tag4_dataout_q[5])}} ) | + ( ({lru_tag4_dataout_q[0:1], tlb_tag4_q[`tagpos_is], lru_tag4_dataout_q[3]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 0] & tlb_tag4_q[`tagpos_hes] & lru_tag4_dataout_q[4] & (~lru_tag4_dataout_q[6]))}} ) | + ( ({lru_tag4_dataout_q[0:2], tlb_tag4_q[`tagpos_is]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 0] & tlb_tag4_q[`tagpos_hes] & lru_tag4_dataout_q[4] & lru_tag4_dataout_q[6])}} ) | + + ( ({tlb_tag4_q[`tagpos_is], lru_tag4_dataout_q[1:3]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 1] & tlb_tag4_q[`tagpos_hes] & (~lru_tag4_dataout_q[4]) & (~lru_tag4_dataout_q[5]))}} ) | + ( ({lru_tag4_dataout_q[0], tlb_tag4_q[`tagpos_is], lru_tag4_dataout_q[2:3]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 1] & tlb_tag4_q[`tagpos_hes] & (~lru_tag4_dataout_q[4]) & lru_tag4_dataout_q[5])}} ) | + ( ({lru_tag4_dataout_q[0:1], tlb_tag4_q[`tagpos_is], lru_tag4_dataout_q[3]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 1] & tlb_tag4_q[`tagpos_hes] & lru_tag4_dataout_q[4] & (~lru_tag4_dataout_q[6]))}} ) | + ( ({lru_tag4_dataout_q[0:2], tlb_tag4_q[`tagpos_is]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 1] & tlb_tag4_q[`tagpos_hes] & lru_tag4_dataout_q[4] & lru_tag4_dataout_q[6])}} ) | + + ( ({tlb_tag4_q[`tagpos_is], lru_tag4_dataout_q[1:3]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 2] & tlb_tag4_q[`tagpos_hes] & (~lru_tag4_dataout_q[4]) & (~lru_tag4_dataout_q[5]))}} ) | + ( ({lru_tag4_dataout_q[0], tlb_tag4_q[`tagpos_is], lru_tag4_dataout_q[2:3]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 2] & tlb_tag4_q[`tagpos_hes] & (~lru_tag4_dataout_q[4]) & lru_tag4_dataout_q[5])}} ) | + ( ({lru_tag4_dataout_q[0:1], tlb_tag4_q[`tagpos_is], lru_tag4_dataout_q[3]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 2] & tlb_tag4_q[`tagpos_hes] & lru_tag4_dataout_q[4] & (~lru_tag4_dataout_q[6]))}} ) | + ( ({lru_tag4_dataout_q[0:2], tlb_tag4_q[`tagpos_is]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 2] & tlb_tag4_q[`tagpos_hes] & lru_tag4_dataout_q[4] & lru_tag4_dataout_q[6])}} ) | + + ( ({tlb_tag4_q[`tagpos_is], lru_tag4_dataout_q[1:3]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 3] & tlb_tag4_q[`tagpos_hes] & (~lru_tag4_dataout_q[4]) & (~lru_tag4_dataout_q[5]))}} ) | + ( ({lru_tag4_dataout_q[0], tlb_tag4_q[`tagpos_is], lru_tag4_dataout_q[2:3]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 3] & tlb_tag4_q[`tagpos_hes] & (~lru_tag4_dataout_q[4]) & lru_tag4_dataout_q[5])}} ) | + ( ({lru_tag4_dataout_q[0:1], tlb_tag4_q[`tagpos_is], lru_tag4_dataout_q[3]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 3] & tlb_tag4_q[`tagpos_hes] & lru_tag4_dataout_q[4] & (~lru_tag4_dataout_q[6]))}} ) | + ( ({lru_tag4_dataout_q[0:2], tlb_tag4_q[`tagpos_is]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 3] & tlb_tag4_q[`tagpos_hes] & lru_tag4_dataout_q[4] & lru_tag4_dataout_q[6])}} ); + // hes=0 valid bits update data + assign tlb_tag4_hes0_mas1_v[0:`THDID_WIDTH - 1] = ( ({tlb_tag4_q[`tagpos_is], lru_tag4_dataout_q[1:3]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 0] & (~tlb_tag4_q[`tagpos_hes]) & (~tlb_tag4_q[`tagpos_esel + 1]) & (~tlb_tag4_q[`tagpos_esel + 2]))}} ) | + ( ({lru_tag4_dataout_q[0], tlb_tag4_q[`tagpos_is], lru_tag4_dataout_q[2:3]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 0] & (~tlb_tag4_q[`tagpos_hes]) & (~tlb_tag4_q[`tagpos_esel + 1]) & tlb_tag4_q[`tagpos_esel + 2])}} ) | + ( ({lru_tag4_dataout_q[0:1], tlb_tag4_q[`tagpos_is], lru_tag4_dataout_q[3]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 0] & (~tlb_tag4_q[`tagpos_hes]) & tlb_tag4_q[`tagpos_esel + 1] & (~tlb_tag4_q[`tagpos_esel + 2]))}} ) | + ( ({lru_tag4_dataout_q[0:2], tlb_tag4_q[`tagpos_is]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 0] & (~tlb_tag4_q[`tagpos_hes]) & tlb_tag4_q[`tagpos_esel + 1] & tlb_tag4_q[`tagpos_esel + 2])}} ) | + + ( ({tlb_tag4_q[`tagpos_is], lru_tag4_dataout_q[1:3]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 1] & (~tlb_tag4_q[`tagpos_hes]) & (~tlb_tag4_q[`tagpos_esel + 1]) & (~tlb_tag4_q[`tagpos_esel + 2]))}} ) | + ( ({lru_tag4_dataout_q[0], tlb_tag4_q[`tagpos_is], lru_tag4_dataout_q[2:3]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 1] & (~tlb_tag4_q[`tagpos_hes]) & (~tlb_tag4_q[`tagpos_esel + 1]) & tlb_tag4_q[`tagpos_esel + 2])}} ) | + ( ({lru_tag4_dataout_q[0:1], tlb_tag4_q[`tagpos_is], lru_tag4_dataout_q[3]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 1] & (~tlb_tag4_q[`tagpos_hes]) & tlb_tag4_q[`tagpos_esel + 1] & (~tlb_tag4_q[`tagpos_esel + 2]))}} ) | + ( ({lru_tag4_dataout_q[0:2], tlb_tag4_q[`tagpos_is]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 1] & (~tlb_tag4_q[`tagpos_hes]) & tlb_tag4_q[`tagpos_esel + 1] & tlb_tag4_q[`tagpos_esel + 2])}} ) | + + ( ({tlb_tag4_q[`tagpos_is], lru_tag4_dataout_q[1:3]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 2] & (~tlb_tag4_q[`tagpos_hes]) & (~tlb_tag4_q[`tagpos_esel + 1]) & (~tlb_tag4_q[`tagpos_esel + 2]))}} ) | + ( ({lru_tag4_dataout_q[0], tlb_tag4_q[`tagpos_is], lru_tag4_dataout_q[2:3]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 2] & (~tlb_tag4_q[`tagpos_hes]) & (~tlb_tag4_q[`tagpos_esel + 1]) & tlb_tag4_q[`tagpos_esel + 2])}} ) | + ( ({lru_tag4_dataout_q[0:1], tlb_tag4_q[`tagpos_is], lru_tag4_dataout_q[3]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 2] & (~tlb_tag4_q[`tagpos_hes]) & tlb_tag4_q[`tagpos_esel + 1] & (~tlb_tag4_q[`tagpos_esel + 2]))}} ) | + ( ({lru_tag4_dataout_q[0:2], tlb_tag4_q[`tagpos_is]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 2] & (~tlb_tag4_q[`tagpos_hes]) & tlb_tag4_q[`tagpos_esel + 1] & tlb_tag4_q[`tagpos_esel + 2])}} ) | + + ( ({tlb_tag4_q[`tagpos_is], lru_tag4_dataout_q[1:3]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 3] & (~tlb_tag4_q[`tagpos_hes]) & (~tlb_tag4_q[`tagpos_esel + 1]) & (~tlb_tag4_q[`tagpos_esel + 2]))}} ) | + ( ({lru_tag4_dataout_q[0], tlb_tag4_q[`tagpos_is], lru_tag4_dataout_q[2:3]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 3] & (~tlb_tag4_q[`tagpos_hes]) & (~tlb_tag4_q[`tagpos_esel + 1]) & tlb_tag4_q[`tagpos_esel + 2])}} ) | + ( ({lru_tag4_dataout_q[0:1], tlb_tag4_q[`tagpos_is], lru_tag4_dataout_q[3]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 3] & (~tlb_tag4_q[`tagpos_hes]) & tlb_tag4_q[`tagpos_esel + 1] & (~tlb_tag4_q[`tagpos_esel + 2]))}} ) | + ( ({lru_tag4_dataout_q[0:2], tlb_tag4_q[`tagpos_is]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 3] & (~tlb_tag4_q[`tagpos_hes]) & tlb_tag4_q[`tagpos_esel + 1] & tlb_tag4_q[`tagpos_esel + 2])}} ); + + // hes=1 iprot bits update data + + assign tlb_tag4_hes1_mas1_iprot[0:`THDID_WIDTH - 1] = ( ({tlb_tag4_q[`tagpos_is + 1], lru_tag4_dataout_q[9:11]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 0] & tlb_tag4_q[`tagpos_hes] & (~lru_tag4_dataout_q[4]) & (~lru_tag4_dataout_q[5]))}} ) | + ( ({lru_tag4_dataout_q[8], tlb_tag4_q[`tagpos_is + 1], lru_tag4_dataout_q[10:11]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 0] & tlb_tag4_q[`tagpos_hes] & (~lru_tag4_dataout_q[4]) & lru_tag4_dataout_q[5])}} ) | + ( ({lru_tag4_dataout_q[8:9], tlb_tag4_q[`tagpos_is + 1], lru_tag4_dataout_q[11]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 0] & tlb_tag4_q[`tagpos_hes] & lru_tag4_dataout_q[4] & (~lru_tag4_dataout_q[6]))}} ) | + ( ({lru_tag4_dataout_q[8:10], tlb_tag4_q[`tagpos_is + 1]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 0] & tlb_tag4_q[`tagpos_hes] & lru_tag4_dataout_q[4] & lru_tag4_dataout_q[6])}} ) | + + ( ({tlb_tag4_q[`tagpos_is + 1], lru_tag4_dataout_q[9:11]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 1] & tlb_tag4_q[`tagpos_hes] & (~lru_tag4_dataout_q[4]) & (~lru_tag4_dataout_q[5]))}} ) | + ( ({lru_tag4_dataout_q[8], tlb_tag4_q[`tagpos_is + 1], lru_tag4_dataout_q[10:11]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 1] & tlb_tag4_q[`tagpos_hes] & (~lru_tag4_dataout_q[4]) & lru_tag4_dataout_q[5])}} ) | + ( ({lru_tag4_dataout_q[8:9], tlb_tag4_q[`tagpos_is + 1], lru_tag4_dataout_q[11]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 1] & tlb_tag4_q[`tagpos_hes] & lru_tag4_dataout_q[4] & (~lru_tag4_dataout_q[6]))}} ) | + ( ({lru_tag4_dataout_q[8:10], tlb_tag4_q[`tagpos_is + 1]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 1] & tlb_tag4_q[`tagpos_hes] & lru_tag4_dataout_q[4] & lru_tag4_dataout_q[6])}} ) | + + ( ({tlb_tag4_q[`tagpos_is + 1], lru_tag4_dataout_q[9:11]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 2] & tlb_tag4_q[`tagpos_hes] & (~lru_tag4_dataout_q[4]) & (~lru_tag4_dataout_q[5]))}} ) | + ( ({lru_tag4_dataout_q[8], tlb_tag4_q[`tagpos_is + 1], lru_tag4_dataout_q[10:11]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 2] & tlb_tag4_q[`tagpos_hes] & (~lru_tag4_dataout_q[4]) & lru_tag4_dataout_q[5])}} ) | + ( ({lru_tag4_dataout_q[8:9], tlb_tag4_q[`tagpos_is + 1], lru_tag4_dataout_q[11]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 2] & tlb_tag4_q[`tagpos_hes] & lru_tag4_dataout_q[4] & (~lru_tag4_dataout_q[6]))}} ) | + ( ({lru_tag4_dataout_q[8:10], tlb_tag4_q[`tagpos_is + 1]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 2] & tlb_tag4_q[`tagpos_hes] & lru_tag4_dataout_q[4] & lru_tag4_dataout_q[6])}} ) | + + ( ({tlb_tag4_q[`tagpos_is + 1], lru_tag4_dataout_q[9:11]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 3] & tlb_tag4_q[`tagpos_hes] & (~lru_tag4_dataout_q[4]) & (~lru_tag4_dataout_q[5]))}} ) | + ( ({lru_tag4_dataout_q[8], tlb_tag4_q[`tagpos_is + 1], lru_tag4_dataout_q[10:11]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 3] & tlb_tag4_q[`tagpos_hes] & (~lru_tag4_dataout_q[4]) & lru_tag4_dataout_q[5])}} ) | + ( ({lru_tag4_dataout_q[8:9], tlb_tag4_q[`tagpos_is + 1], lru_tag4_dataout_q[11]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 3] & tlb_tag4_q[`tagpos_hes] & lru_tag4_dataout_q[4] & (~lru_tag4_dataout_q[6]))}} ) | + ( ({lru_tag4_dataout_q[8:10], tlb_tag4_q[`tagpos_is + 1]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 3] & tlb_tag4_q[`tagpos_hes] & lru_tag4_dataout_q[4] & lru_tag4_dataout_q[6])}} ); + + // hes=0 iprot bits update data + assign tlb_tag4_hes0_mas1_iprot[0:`THDID_WIDTH - 1] = ( ({tlb_tag4_q[`tagpos_is + 1], lru_tag4_dataout_q[9:11]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 0] & (~tlb_tag4_q[`tagpos_hes]) & (~tlb_tag4_q[`tagpos_esel + 1]) & (~tlb_tag4_q[`tagpos_esel + 2]))}} ) | + ( ({lru_tag4_dataout_q[8], tlb_tag4_q[`tagpos_is + 1], lru_tag4_dataout_q[10:11]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 0] & (~tlb_tag4_q[`tagpos_hes]) & (~tlb_tag4_q[`tagpos_esel + 1]) & tlb_tag4_q[`tagpos_esel + 2])}} ) | + ( ({lru_tag4_dataout_q[8:9], tlb_tag4_q[`tagpos_is + 1], lru_tag4_dataout_q[11]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 0] & (~tlb_tag4_q[`tagpos_hes]) & tlb_tag4_q[`tagpos_esel + 1] & (~tlb_tag4_q[`tagpos_esel + 2]))}} ) | + ( ({lru_tag4_dataout_q[8:10], tlb_tag4_q[`tagpos_is + 1]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 0] & (~tlb_tag4_q[`tagpos_hes]) & tlb_tag4_q[`tagpos_esel + 1] & tlb_tag4_q[`tagpos_esel + 2])}} ) | + + ( ({tlb_tag4_q[`tagpos_is + 1], lru_tag4_dataout_q[9:11]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 1] & (~tlb_tag4_q[`tagpos_hes]) & (~tlb_tag4_q[`tagpos_esel + 1]) & (~tlb_tag4_q[`tagpos_esel + 2]))}} ) | + ( ({lru_tag4_dataout_q[8], tlb_tag4_q[`tagpos_is + 1], lru_tag4_dataout_q[10:11]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 1] & (~tlb_tag4_q[`tagpos_hes]) & (~tlb_tag4_q[`tagpos_esel + 1]) & tlb_tag4_q[`tagpos_esel + 2])}} ) | + ( ({lru_tag4_dataout_q[8:9], tlb_tag4_q[`tagpos_is + 1], lru_tag4_dataout_q[11]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 1] & (~tlb_tag4_q[`tagpos_hes]) & tlb_tag4_q[`tagpos_esel + 1] & (~tlb_tag4_q[`tagpos_esel + 2]))}} ) | + ( ({lru_tag4_dataout_q[8:10], tlb_tag4_q[`tagpos_is + 1]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 1] & (~tlb_tag4_q[`tagpos_hes]) & tlb_tag4_q[`tagpos_esel + 1] & tlb_tag4_q[`tagpos_esel + 2])}} ) | + + ( ({tlb_tag4_q[`tagpos_is + 1], lru_tag4_dataout_q[9:11]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 2] & (~tlb_tag4_q[`tagpos_hes]) & (~tlb_tag4_q[`tagpos_esel + 1]) & (~tlb_tag4_q[`tagpos_esel + 2]))}} ) | + ( ({lru_tag4_dataout_q[8], tlb_tag4_q[`tagpos_is + 1], lru_tag4_dataout_q[10:11]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 2] & (~tlb_tag4_q[`tagpos_hes]) & (~tlb_tag4_q[`tagpos_esel + 1]) & tlb_tag4_q[`tagpos_esel + 2])}} ) | + ( ({lru_tag4_dataout_q[8:9], tlb_tag4_q[`tagpos_is + 1], lru_tag4_dataout_q[11]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 2] & (~tlb_tag4_q[`tagpos_hes]) & tlb_tag4_q[`tagpos_esel + 1] & (~tlb_tag4_q[`tagpos_esel + 2]))}} ) | + ( ({lru_tag4_dataout_q[8:10], tlb_tag4_q[`tagpos_is + 1]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 2] & (~tlb_tag4_q[`tagpos_hes]) & tlb_tag4_q[`tagpos_esel + 1] & tlb_tag4_q[`tagpos_esel + 2])}} ) | + + ( ({tlb_tag4_q[`tagpos_is + 1], lru_tag4_dataout_q[9:11]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 3] & (~tlb_tag4_q[`tagpos_hes]) & (~tlb_tag4_q[`tagpos_esel + 1]) & (~tlb_tag4_q[`tagpos_esel + 2]))}} ) | + ( ({lru_tag4_dataout_q[8], tlb_tag4_q[`tagpos_is + 1], lru_tag4_dataout_q[10:11]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 3] & (~tlb_tag4_q[`tagpos_hes]) & (~tlb_tag4_q[`tagpos_esel + 1]) & tlb_tag4_q[`tagpos_esel + 2])}} ) | + ( ({lru_tag4_dataout_q[8:9], tlb_tag4_q[`tagpos_is + 1], lru_tag4_dataout_q[11]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 3] & (~tlb_tag4_q[`tagpos_hes]) & tlb_tag4_q[`tagpos_esel + 1] & (~tlb_tag4_q[`tagpos_esel + 2]))}} ) | + ( ({lru_tag4_dataout_q[8:10], tlb_tag4_q[`tagpos_is + 1]}) & {`THDID_WIDTH{(tlb_tag4_q[`tagpos_thdid + 3] & (~tlb_tag4_q[`tagpos_hes]) & tlb_tag4_q[`tagpos_esel + 1] & tlb_tag4_q[`tagpos_esel + 2])}} ); + + // ptereload write phase signals + assign tlb_tag4_ptereload_v[0:`THDID_WIDTH - 1] = ((lru_tag4_dataout_q[4:5] == 2'b00)) ? ({ptereload_req_pte_lat[`ptepos_valid], lru_tag4_dataout_q[1:3]}) : + ((lru_tag4_dataout_q[4:5] == 2'b01)) ? ({lru_tag4_dataout_q[0], ptereload_req_pte_lat[`ptepos_valid], lru_tag4_dataout_q[2:3]}) : + ((lru_tag4_dataout_q[4] == 1'b1 & lru_tag4_dataout_q[6] == 1'b0)) ? ({lru_tag4_dataout_q[0:1], ptereload_req_pte_lat[`ptepos_valid], lru_tag4_dataout_q[3]}) : + ((lru_tag4_dataout_q[4] == 1'b1 & lru_tag4_dataout_q[6] == 1'b1)) ? ({lru_tag4_dataout_q[0:2], ptereload_req_pte_lat[`ptepos_valid]}) : + lru_tag4_dataout_q[0:3]; + assign tlb_tag4_ptereload_iprot[0:`THDID_WIDTH - 1] = ((lru_tag4_dataout_q[4:5] == 2'b00)) ? ({1'b0, lru_tag4_dataout_q[9:11]}) : + ((lru_tag4_dataout_q[4:5] == 2'b01)) ? ({lru_tag4_dataout_q[8], 1'b0, lru_tag4_dataout_q[10:11]}) : + ((lru_tag4_dataout_q[4] == 1'b1 & lru_tag4_dataout_q[6] == 1'b0)) ? ({lru_tag4_dataout_q[8:9], 1'b0, lru_tag4_dataout_q[11]}) : + ((lru_tag4_dataout_q[4] == 1'b1 & lru_tag4_dataout_q[6] == 1'b1)) ? ({lru_tag4_dataout_q[8:10], 1'b0}) : + lru_tag4_dataout_q[8:11]; + + // 0 1 2 3 4 5 6 7 + // tag type bits --> derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload + // lrat_tag4_hit_status(0:3) -> val,hit,multihit,inval_pgsize + assign lru_write_d = ( (tlb_tag4_q[`tagpos_type_derat] == 1'b1 | tlb_tag4_q[`tagpos_type_ierat] == 1'b1) & tlb_tag4_q[`tagpos_type_ptereload] == 1'b0 & + |(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & + ((|(tlb_tag4_wayhit_q[0:`TLB_WAYS - 1]) == 1'b1 & multihit == 1'b0 & |(tag4_parerr_q[0:4]) == 1'b0) | + (xu_mm_xucr4_mmu_mchk_q == 1'b0 & xu_mm_ccr2_notlb_b == 1'b1 & tlb_tag4_q[`tagpos_nonspec] == 1'b1 & + (multihit == 1'b1 | |(tag4_parerr_q[0:4]) == 1'b1))) ) ? {`LRU_WIDTH{1'b1}} : + ( tlb_tag4_q[`tagpos_type_snoop] == 1'b1 & |(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & + (|(tlb_tag4_wayhit_q[0:`TLB_WAYS - 1]) == 1'b1 | tlb_tag4_q[`tagpos_is + 1:`tagpos_is + 3] == 3'b000) ) ? {`LRU_WIDTH{1'b1}} : + ( tlb_tag4_q[`tagpos_type_tlbwe] == 1'b1 & tlb_tag4_q[`tagpos_pr] == 1'b0 & ex6_illeg_instr[1] == 1'b0 & + |(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] & (~tlb_ctl_tag4_flush)) == 1'b1 & + ((|(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] & tlb_resv_match_vec) == 1'b1 & + tlb_tag4_q[`tagpos_wq:`tagpos_wq + 1] == 2'b01 & mmucfg_twc == 1'b1) | tlb_tag4_q[`tagpos_wq:`tagpos_wq + 1] == 2'b00 | + tlb_tag4_q[`tagpos_wq:`tagpos_wq + 1] == 2'b11) & ((tlb_tag4_q[`tagpos_gs] == 1'b0 & tlb_tag4_q[`tagpos_atsel] == 1'b0) | + (tlb_tag4_q[`tagpos_gs] == 1'b1 & tlb_tag4_q[`tagpos_hes] == 1'b1 & tlb_tag4_q[`tagpos_is + 1] == 1'b0 & tlb0cfg_gtwe == 1'b1 & + tlb_tag4_epcr_dgtmi == 1'b0 & lrat_tag4_hit_status == 4'b1100 & + (((lru_tag4_dataout_q[0] == 1'b0 | lru_tag4_dataout_q[8] == 1'b0) & lru_tag4_dataout_q[4:5] == 2'b00) | + ((lru_tag4_dataout_q[1] == 1'b0 | lru_tag4_dataout_q[9] == 1'b0) & lru_tag4_dataout_q[4:5] == 2'b01) | + ((lru_tag4_dataout_q[2] == 1'b0 | lru_tag4_dataout_q[10] == 1'b0) & lru_tag4_dataout_q[4] == 1'b1 & lru_tag4_dataout_q[6] == 1'b0) | + ((lru_tag4_dataout_q[3] == 1'b0 | lru_tag4_dataout_q[11] == 1'b0) & lru_tag4_dataout_q[4] == 1'b1 & lru_tag4_dataout_q[6] == 1'b1)))) ) ? {`LRU_WIDTH{1'b1}} : + ( tlb_tag4_q[`tagpos_type_ptereload] == 1'b1 & (|(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1) & + (tlb_tag4_q[`tagpos_gs] == 1'b0 | (tlb_tag4_q[`tagpos_gs] == 1'b1 & lrat_tag4_hit_status == 4'b1100)) & + (tlb_tag4_q[`tagpos_wq:`tagpos_wq + 1] == 2'b10) & (tlb_tag4_q[`tagpos_pt] == 1'b1) & + (((lru_tag4_dataout_q[0] == 1'b0 | lru_tag4_dataout_q[8] == 1'b0) & lru_tag4_dataout_q[4:5] == 2'b00) | + ((lru_tag4_dataout_q[1] == 1'b0 | lru_tag4_dataout_q[9] == 1'b0) & lru_tag4_dataout_q[4:5] == 2'b01) | + ((lru_tag4_dataout_q[2] == 1'b0 | lru_tag4_dataout_q[10] == 1'b0) & lru_tag4_dataout_q[4] == 1'b1 & lru_tag4_dataout_q[6] == 1'b0) | + ((lru_tag4_dataout_q[3] == 1'b0 | lru_tag4_dataout_q[11] == 1'b0) & lru_tag4_dataout_q[4] == 1'b1 & lru_tag4_dataout_q[6] == 1'b1)) ) ? {`LRU_WIDTH{ptereload_req_pte_lat[`ptepos_valid]}} : + {`LRU_WIDTH{1'b0}}; + + assign lru_wr_addr_d = tlb_addr4_q; + + // lru data format + // 0:3 - valid(0:3) + // 4:6 - LRU + // 7 - parity + // 8:11 - iprot(0:3) + // 12:14 - reserved + // 15 - parity + // `tagpos_type: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload + + assign lru_update_clear_enab = ((xu_mm_xucr4_mmu_mchk_q == 1'b0 & xu_mm_ccr2_notlb_b == 1'b1 & + ((tlb_tag4_q[`tagpos_type_derat] == 1'b1 | tlb_tag4_q[`tagpos_type_ierat] == 1'b1) & tlb_tag4_q[`tagpos_type_ptereload] == 1'b0) & + tlb_tag4_q[`tagpos_nonspec] == 1'b1 & (multihit == 1'b1 | |(tag4_parerr_q[0:4]) == 1'b1))) ? 1'b1 : + 1'b0; + + assign lru_update_data_enab = ( ((tlb_tag4_q[`tagpos_type_derat] == 1'b1 | tlb_tag4_q[`tagpos_type_ierat] == 1'b1) & tlb_tag4_q[`tagpos_type_ptereload] == 1'b0 & + multihit == 1'b0 & |(tag4_parerr_q[0:4]) == 1'b0) | + (tlb_tag4_q[`tagpos_type_tlbwe] == 1'b1 & (tlb_tag4_q[`tagpos_atsel] == 1'b0 | tlb_tag4_q[`tagpos_gs] == 1'b1)) | + (tlb_tag4_q[`tagpos_type_ptereload] == 1'b1) | (tlb_tag4_q[`tagpos_type_snoop] == 1'b1) ) ? 1'b1 : + 1'b0; + // valid bits + assign lru_datain_d[0:3] = (lru_update_clear_enab == 1'b1) ? {4{1'b0}} : + (tlb_tag4_q[`tagpos_type_snoop] == 1'b1) ? (lru_tag4_dataout_q[0:3] & (lru_tag4_dataout_q[8:11] | (~(tlb_tag4_wayhit_q[0:3])))) : + (tlb_tag4_q[`tagpos_type_tlbwe] == 1'b1 & tlb_tag4_q[`tagpos_hes] == 1'b1) ? tlb_tag4_hes1_mas1_v[0:`THDID_WIDTH - 1] : + (tlb_tag4_q[`tagpos_type_tlbwe] == 1'b1 & tlb_tag4_q[`tagpos_hes] == 1'b0) ? tlb_tag4_hes0_mas1_v[0:`THDID_WIDTH - 1] : + (tlb_tag4_q[`tagpos_type_ptereload] == 1'b1) ? tlb_tag4_ptereload_v[0:`THDID_WIDTH - 1] : + lru_tag4_dataout_q[0:3]; + // LRU bits + assign lru_datain_d[4:6] = (lru_update_clear_enab == 1'b1) ? {3{1'b0}} : + (lru_update_data_enab == 1'b1) ? lru_update_data : + lru_tag4_dataout_q[4:6]; + + // alternate LRU bits for possible eco + assign lru_datain_alt_d[4:6] = (((tlb_tag4_q[`tagpos_type_derat] == 1'b1 | tlb_tag4_q[`tagpos_type_ierat] == 1'b1 | tlb_tag4_q[`tagpos_type_snoop] == 1'b1) & tlb_tag4_q[`tagpos_type_ptereload] == 1'b0)) ? lru_update_data_alt : + ((tlb_tag4_q[`tagpos_type_tlbwe] == 1'b1 & (tlb_tag4_q[`tagpos_atsel] == 1'b0 | tlb_tag4_q[`tagpos_gs] == 1'b1))) ? lru_update_data : + ((tlb_tag4_q[`tagpos_type_ptereload] == 1'b1)) ? lru_update_data : + lru_tag4_dataout_q[4:6]; + + // old lru value if no hits + assign lru_update_data_alt = ( lru_tag4_dataout_q[4:6] & {3{(~tlb_tag4_wayhit_q[4])}} ) | + ( lru_update_data_snoophit_eco & {3{(tlb_tag4_wayhit_q[4] & tlb_tag4_q[`tagpos_type_snoop])}} ) | + ( lru_update_data_erathit_eco & {3{(tlb_tag4_wayhit_q[4] & (~tlb_tag4_q[`tagpos_type_ptereload]) & (tlb_tag4_q[`tagpos_type_derat] | tlb_tag4_q[`tagpos_type_ierat]))}} ); + + assign lru_datain_alt_d[7] = ^({lru_datain_d[0:3], lru_datain_alt_d[4:6]}); + + assign lru_update_data_snoophit_eco[0:2] = ((tlb_tag4_wayhit_q[0] & (~lru_tag4_dataout_q[6]) & (~lru_tag4_dataout_q[8])) == 1'b1) ? 3'b000 : + ((tlb_tag4_wayhit_q[0] & lru_tag4_dataout_q[6] & (~lru_tag4_dataout_q[8])) == 1'b1) ? 3'b001 : + ((tlb_tag4_wayhit_q[1] & (~lru_tag4_dataout_q[6]) & (~lru_tag4_dataout_q[9])) == 1'b1) ? 3'b010 : + ((tlb_tag4_wayhit_q[1] & lru_tag4_dataout_q[6] & (~lru_tag4_dataout_q[9])) == 1'b1) ? 3'b011 : + ((tlb_tag4_wayhit_q[2] & (~lru_tag4_dataout_q[5]) & (~lru_tag4_dataout_q[10])) == 1'b1) ? 3'b100 : + ((tlb_tag4_wayhit_q[2] & lru_tag4_dataout_q[5] & (~lru_tag4_dataout_q[10])) == 1'b1) ? 3'b110 : + ((tlb_tag4_wayhit_q[3] & (~lru_tag4_dataout_q[5]) & (~lru_tag4_dataout_q[11])) == 1'b1) ? 3'b101 : + ((tlb_tag4_wayhit_q[3] & lru_tag4_dataout_q[5] & (~lru_tag4_dataout_q[11])) == 1'b1) ? 3'b111 : + lru_tag4_dataout_q[4:6]; + + assign lru_datain_alt_d[8] = ^({lru_datain_d[0:3], lru_update_data_snoophit_eco[0:2]}); + + assign lru_update_data_erathit_eco[0:2] = ((tlb_tag4_wayhit_q[0] & (~lru_tag4_dataout_q[9])) == 1'b1) ? {2'b01, lru_tag4_dataout_q[6]} : + ((tlb_tag4_wayhit_q[0] & (~lru_tag4_dataout_q[10])) == 1'b1) ? {1'b1, lru_tag4_dataout_q[5], 1'b0} : + ((tlb_tag4_wayhit_q[0] & (~lru_tag4_dataout_q[11])) == 1'b1) ? {1'b1, lru_tag4_dataout_q[5], 1'b1} : + ((tlb_tag4_wayhit_q[1] & (~lru_tag4_dataout_q[10])) == 1'b1) ? {1'b1, lru_tag4_dataout_q[5], 1'b0} : + ((tlb_tag4_wayhit_q[1] & (~lru_tag4_dataout_q[11])) == 1'b1) ? {1'b1, lru_tag4_dataout_q[5], 1'b1} : + ((tlb_tag4_wayhit_q[1] & (~lru_tag4_dataout_q[8])) == 1'b1) ? {2'b00, lru_tag4_dataout_q[6]} : + ((tlb_tag4_wayhit_q[2] & (~lru_tag4_dataout_q[11])) == 1'b1) ? {1'b1, lru_tag4_dataout_q[5], 1'b1} : + ((tlb_tag4_wayhit_q[2] & (~lru_tag4_dataout_q[8])) == 1'b1) ? {2'b00, lru_tag4_dataout_q[6]} : + ((tlb_tag4_wayhit_q[2] & (~lru_tag4_dataout_q[9])) == 1'b1) ? {2'b01, lru_tag4_dataout_q[6]} : + ((tlb_tag4_wayhit_q[3] & (~lru_tag4_dataout_q[8])) == 1'b1) ? {2'b00, lru_tag4_dataout_q[6]} : + ((tlb_tag4_wayhit_q[3] & (~lru_tag4_dataout_q[9])) == 1'b1) ? {2'b01, lru_tag4_dataout_q[6]} : + ((tlb_tag4_wayhit_q[3] & (~lru_tag4_dataout_q[10])) == 1'b1) ? {1'b1, lru_tag4_dataout_q[5], 1'b0} : + lru_tag4_dataout_q[4:6]; + + assign lru_datain_alt_d[9] = ^({lru_datain_d[0:3], lru_update_data_erathit_eco[0:2]}); + + // iprot bits + assign lru_datain_d[8:11] = (lru_update_clear_enab == 1'b1) ? {4{1'b0}} : + (tlb_tag4_q[`tagpos_type_tlbwe] == 1'b1 & tlb_tag4_q[`tagpos_hes] == 1'b1) ? tlb_tag4_hes1_mas1_iprot[0:`THDID_WIDTH - 1] : + (tlb_tag4_q[`tagpos_type_tlbwe] == 1'b1 & tlb_tag4_q[`tagpos_hes] == 1'b0) ? tlb_tag4_hes0_mas1_iprot[0:`THDID_WIDTH - 1] : + (tlb_tag4_q[`tagpos_type_ptereload] == 1'b1) ? tlb_tag4_ptereload_iprot[0:`THDID_WIDTH - 1] : + lru_tag4_dataout_q[8:11]; + + assign lru_datain_d[12:14] = {3{1'b0}}; + + // LRU Parity Generation + assign lru_datain_d[7] = ^(lru_datain_d[0:6]); + assign lru_datain_d[15] = ^({lru_datain_d[8:14], (mmucr1_q[pos_lru_pei] & tlb_tag4_q[`tagpos_type_tlbwe])}); + + // LRU Parity Checking + assign lru_calc_par[0] = ^(lru_tag3_dataout_q[0:6]); + assign lru_calc_par[1] = ^(lru_tag3_dataout_q[8:14]); + + assign tag4_parerr_d[`TLB_WAYS] = |( lru_calc_par[0:1] ^ {lru_tag3_dataout_q[7], lru_tag3_dataout_q[15]} ); + + assign tlb_tag4_parerr_enab = |(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) & |(tlb_tag4_q[`tagpos_type_derat:`tagpos_type_tlbsrx]) | tlb_tag4_q[`tagpos_type_tlbre]; + // end of LRU Parity Checking + + // tag4 phase signals, tlbwe/re ex6, tlbsx/srx ex7 + // 0 1 2 3 4 5 6 7 + // tag type bits --> derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload + // tlb_tag4_is: 0:3 -> IS/Class: 0=all, 1=tid, 2=gs, 3=epn, 4=class0, 5=class1, 6=class2, 7=class3 + + // Encoder for the LRU update data + // `tagpos_is def is mas1_v, mas1_iprot for tlbwe + +/* +//table_start +?TABLE lru_update_data LISTING(final) OPTIMIZE PARMS(ON-SET, OFF-SET); +*INPUTS*============================================*OUTPUTS*=============* +| | | +| tlb_tag4_type_sig | lru_update_data | +| | tlb_tag4_hes_sig | | | +| | | tlb_tag4_esel_sig | | | +| | | | tlb_tag4_wq_sig | | | +| | | | | tlb_tag4_is_sig | | | +| | | | | | tlb_tag4_wayhit_q | | | +| | | | | | | lru_tag4_dataout_q | | | +| | | | | | | | | | | +| | | | | | | | | | | +| | | | | | | | 111111 | | | +| 01234567 | 012 01 0123 0123 0123456789012345 | 012 | +*TYPE*==============================================+=====================+ +| PPPPPPPP P PPP PP PPPP PPPP PPPPPPPPPPPPPPPP | PPP | +*OPTIMIZE*----------------------------------------->| AAA | +*TERMS*=============================================+=====================+ +| 10000000 - --- -- ---- ---- 0-----0--------- | 000 | derat nonvalid ways +| 10000000 - --- -- ---- ---- 0-----1--------- | 001 | +| 10000000 - --- -- ---- ---- 10----0--------- | 010 | +| 10000000 - --- -- ---- ---- 10----1--------- | 011 | +| 10000000 - --- -- ---- ---- 110--0---------- | 100 | +| 10000000 - --- -- ---- ---- 110--1---------- | 110 | +| 10000000 - --- -- ---- ---- 1110-0---------- | 101 | +| 10000000 - --- -- ---- ---- 1110-1---------- | 111 | +| 10000000 - --- -- ---- 0000 1111000--------- | 000 | derat cc full, no hit, no lru change +| 10000000 - --- -- ---- 0000 1111001--------- | 001 | +| 10000000 - --- -- ---- 0000 1111010--------- | 010 | +| 10000000 - --- -- ---- 0000 1111011--------- | 011 | +| 10000000 - --- -- ---- 0000 1111100--------- | 100 | +| 10000000 - --- -- ---- 0000 1111101--------- | 101 | +| 10000000 - --- -- ---- 0000 1111110--------- | 110 | +| 10000000 - --- -- ---- 0000 1111111--------- | 111 | +| 10000000 - --- -- ---- 1000 1111--0-0000---- | 110 | derat cc full, hit way0 (multihits don't write lru) +| 10000000 - --- -- ---- 1000 1111--0-0001---- | 110 | +| 10000000 - --- -- ---- 1000 1111--0-0010---- | 111 | +| 10000000 - --- -- ---- 1000 1111--0-0011---- | 010 | +| 10000000 - --- -- ---- 1000 1111--0-0100---- | 100 | +| 10000000 - --- -- ---- 1000 1111--0-0101---- | 100 | +| 10000000 - --- -- ---- 1000 1111--0-0110---- | 101 | +| 10000000 - --- -- ---- 1000 1111--0-0111---- | 000 | +| 10000000 - --- -- ---- 1000 1111--0-1000---- | 110 | +| 10000000 - --- -- ---- 1000 1111--0-1001---- | 110 | +| 10000000 - --- -- ---- 1000 1111--0-1010---- | 111 | +| 10000000 - --- -- ---- 1000 1111--0-1011---- | 010 | +| 10000000 - --- -- ---- 1000 1111--0-1100---- | 110 | +| 10000000 - --- -- ---- 1000 1111--0-1101---- | 110 | +| 10000000 - --- -- ---- 1000 1111--0-1110---- | 111 | +| 10000000 - --- -- ---- 1000 1111--0-1111---- | 110 | +| 10000000 - --- -- ---- 1000 1111--1-0000---- | 111 | +| 10000000 - --- -- ---- 1000 1111--1-0001---- | 110 | +| 10000000 - --- -- ---- 1000 1111--1-0010---- | 111 | +| 10000000 - --- -- ---- 1000 1111--1-0011---- | 011 | +| 10000000 - --- -- ---- 1000 1111--1-0100---- | 101 | +| 10000000 - --- -- ---- 1000 1111--1-0101---- | 100 | +| 10000000 - --- -- ---- 1000 1111--1-0110---- | 101 | +| 10000000 - --- -- ---- 1000 1111--1-0111---- | 001 | +| 10000000 - --- -- ---- 1000 1111--1-1000---- | 111 | +| 10000000 - --- -- ---- 1000 1111--1-1001---- | 110 | +| 10000000 - --- -- ---- 1000 1111--1-1010---- | 111 | +| 10000000 - --- -- ---- 1000 1111--1-1011---- | 011 | +| 10000000 - --- -- ---- 1000 1111--1-1100---- | 111 | +| 10000000 - --- -- ---- 1000 1111--1-1101---- | 110 | +| 10000000 - --- -- ---- 1000 1111--1-1110---- | 111 | +| 10000000 - --- -- ---- 1000 1111--1-1111---- | 111 | +| 10000000 - --- -- ---- 0100 1111--0-0000---- | 100 | derat cc full, hit way1 +| 10000000 - --- -- ---- 0100 1111--0-0001---- | 100 | +| 10000000 - --- -- ---- 0100 1111--0-0010---- | 101 | +| 10000000 - --- -- ---- 0100 1111--0-0011---- | 000 | +| 10000000 - --- -- ---- 0100 1111--0-0100---- | 100 | +| 10000000 - --- -- ---- 0100 1111--0-0101---- | 100 | +| 10000000 - --- -- ---- 0100 1111--0-0110---- | 101 | +| 10000000 - --- -- ---- 0100 1111--0-0111---- | 000 | +| 10000000 - --- -- ---- 0100 1111--0-1000---- | 110 | +| 10000000 - --- -- ---- 0100 1111--0-1001---- | 110 | +| 10000000 - --- -- ---- 0100 1111--0-1010---- | 111 | +| 10000000 - --- -- ---- 0100 1111--0-1011---- | 010 | +| 10000000 - --- -- ---- 0100 1111--0-1100---- | 100 | +| 10000000 - --- -- ---- 0100 1111--0-1101---- | 100 | +| 10000000 - --- -- ---- 0100 1111--0-1110---- | 101 | +| 10000000 - --- -- ---- 0100 1111--0-1111---- | 100 | +| 10000000 - --- -- ---- 0100 1111--1-0000---- | 101 | +| 10000000 - --- -- ---- 0100 1111--1-0001---- | 100 | +| 10000000 - --- -- ---- 0100 1111--1-0010---- | 101 | +| 10000000 - --- -- ---- 0100 1111--1-0011---- | 001 | +| 10000000 - --- -- ---- 0100 1111--1-0100---- | 101 | +| 10000000 - --- -- ---- 0100 1111--1-0101---- | 100 | +| 10000000 - --- -- ---- 0100 1111--1-0110---- | 101 | +| 10000000 - --- -- ---- 0100 1111--1-0111---- | 001 | +| 10000000 - --- -- ---- 0100 1111--1-1000---- | 111 | +| 10000000 - --- -- ---- 0100 1111--1-1001---- | 110 | +| 10000000 - --- -- ---- 0100 1111--1-1010---- | 111 | +| 10000000 - --- -- ---- 0100 1111--1-1011---- | 011 | +| 10000000 - --- -- ---- 0100 1111--1-1100---- | 101 | +| 10000000 - --- -- ---- 0100 1111--1-1101---- | 100 | +| 10000000 - --- -- ---- 0100 1111--1-1110---- | 101 | +| 10000000 - --- -- ---- 0100 1111--1-1111---- | 101 | +| 10000000 - --- -- ---- 0010 1111-0--0000---- | 001 | derat cc full, hit way2 +| 10000000 - --- -- ---- 0010 1111-0--0001---- | 000 | +| 10000000 - --- -- ---- 0010 1111-0--0010---- | 001 | +| 10000000 - --- -- ---- 0010 1111-0--0011---- | 001 | +| 10000000 - --- -- ---- 0010 1111-0--0100---- | 001 | +| 10000000 - --- -- ---- 0010 1111-0--0101---- | 000 | +| 10000000 - --- -- ---- 0010 1111-0--0110---- | 001 | +| 10000000 - --- -- ---- 0010 1111-0--0111---- | 001 | +| 10000000 - --- -- ---- 0010 1111-0--1000---- | 011 | +| 10000000 - --- -- ---- 0010 1111-0--1001---- | 010 | +| 10000000 - --- -- ---- 0010 1111-0--1010---- | 011 | +| 10000000 - --- -- ---- 0010 1111-0--1011---- | 011 | +| 10000000 - --- -- ---- 0010 1111-0--1100---- | 101 | +| 10000000 - --- -- ---- 0010 1111-0--1101---- | 100 | +| 10000000 - --- -- ---- 0010 1111-0--1110---- | 101 | +| 10000000 - --- -- ---- 0010 1111-0--1111---- | 001 | +| 10000000 - --- -- ---- 0010 1111-1--0000---- | 011 | +| 10000000 - --- -- ---- 0010 1111-1--0001---- | 010 | +| 10000000 - --- -- ---- 0010 1111-1--0010---- | 011 | +| 10000000 - --- -- ---- 0010 1111-1--0011---- | 011 | +| 10000000 - --- -- ---- 0010 1111-1--0100---- | 001 | +| 10000000 - --- -- ---- 0010 1111-1--0101---- | 000 | +| 10000000 - --- -- ---- 0010 1111-1--0110---- | 001 | +| 10000000 - --- -- ---- 0010 1111-1--0111---- | 001 | +| 10000000 - --- -- ---- 0010 1111-1--1000---- | 011 | +| 10000000 - --- -- ---- 0010 1111-1--1001---- | 010 | +| 10000000 - --- -- ---- 0010 1111-1--1010---- | 011 | +| 10000000 - --- -- ---- 0010 1111-1--1011---- | 011 | +| 10000000 - --- -- ---- 0010 1111-1--1100---- | 111 | +| 10000000 - --- -- ---- 0010 1111-1--1101---- | 110 | +| 10000000 - --- -- ---- 0010 1111-1--1110---- | 111 | +| 10000000 - --- -- ---- 0010 1111-1--1111---- | 011 | +| 10000000 - --- -- ---- 0001 1111-0--0000---- | 000 | derat cc full, hit way3 +| 10000000 - --- -- ---- 0001 1111-0--0001---- | 000 | +| 10000000 - --- -- ---- 0001 1111-0--0010---- | 001 | +| 10000000 - --- -- ---- 0001 1111-0--0011---- | 000 | +| 10000000 - --- -- ---- 0001 1111-0--0100---- | 000 | +| 10000000 - --- -- ---- 0001 1111-0--0101---- | 000 | +| 10000000 - --- -- ---- 0001 1111-0--0110---- | 001 | +| 10000000 - --- -- ---- 0001 1111-0--0111---- | 000 | +| 10000000 - --- -- ---- 0001 1111-0--1000---- | 010 | +| 10000000 - --- -- ---- 0001 1111-0--1001---- | 010 | +| 10000000 - --- -- ---- 0001 1111-0--1010---- | 011 | +| 10000000 - --- -- ---- 0001 1111-0--1011---- | 010 | +| 10000000 - --- -- ---- 0001 1111-0--1100---- | 100 | +| 10000000 - --- -- ---- 0001 1111-0--1101---- | 100 | +| 10000000 - --- -- ---- 0001 1111-0--1110---- | 101 | +| 10000000 - --- -- ---- 0001 1111-0--1111---- | 000 | +| 10000000 - --- -- ---- 0001 1111-1--0000---- | 010 | +| 10000000 - --- -- ---- 0001 1111-1--0001---- | 010 | +| 10000000 - --- -- ---- 0001 1111-1--0010---- | 011 | +| 10000000 - --- -- ---- 0001 1111-1--0011---- | 010 | +| 10000000 - --- -- ---- 0001 1111-1--0100---- | 000 | +| 10000000 - --- -- ---- 0001 1111-1--0101---- | 000 | +| 10000000 - --- -- ---- 0001 1111-1--0110---- | 001 | +| 10000000 - --- -- ---- 0001 1111-1--0111---- | 000 | +| 10000000 - --- -- ---- 0001 1111-1--1000---- | 010 | +| 10000000 - --- -- ---- 0001 1111-1--1001---- | 010 | +| 10000000 - --- -- ---- 0001 1111-1--1010---- | 011 | +| 10000000 - --- -- ---- 0001 1111-1--1011---- | 010 | +| 10000000 - --- -- ---- 0001 1111-1--1100---- | 110 | +| 10000000 - --- -- ---- 0001 1111-1--1101---- | 110 | +| 10000000 - --- -- ---- 0001 1111-1--1110---- | 111 | +| 10000000 - --- -- ---- 0001 1111-1--1111---- | 010 | +| 01000000 - --- -- ---- ---- 0-----0--------- | 000 | ierat nonvalid ways +| 01000000 - --- -- ---- ---- 0-----1--------- | 001 | +| 01000000 - --- -- ---- ---- 10----0--------- | 010 | +| 01000000 - --- -- ---- ---- 10----1--------- | 011 | +| 01000000 - --- -- ---- ---- 110--0---------- | 100 | +| 01000000 - --- -- ---- ---- 110--1---------- | 110 | +| 01000000 - --- -- ---- ---- 1110-0---------- | 101 | +| 01000000 - --- -- ---- ---- 1110-1---------- | 111 | +| 01000000 - --- -- ---- 0000 1111000--------- | 000 | ierat cc full, no hit, no lru change +| 01000000 - --- -- ---- 0000 1111001--------- | 001 | +| 01000000 - --- -- ---- 0000 1111010--------- | 010 | +| 01000000 - --- -- ---- 0000 1111011--------- | 011 | +| 01000000 - --- -- ---- 0000 1111100--------- | 100 | +| 01000000 - --- -- ---- 0000 1111101--------- | 101 | +| 01000000 - --- -- ---- 0000 1111110--------- | 110 | +| 01000000 - --- -- ---- 0000 1111111--------- | 111 | +| 01000000 - --- -- ---- 1000 1111--0-0000---- | 110 | ierat cc full, hit way0 (multihits don't write lru) +| 01000000 - --- -- ---- 1000 1111--0-0001---- | 110 | +| 01000000 - --- -- ---- 1000 1111--0-0010---- | 111 | +| 01000000 - --- -- ---- 1000 1111--0-0011---- | 010 | +| 01000000 - --- -- ---- 1000 1111--0-0100---- | 100 | +| 01000000 - --- -- ---- 1000 1111--0-0101---- | 100 | +| 01000000 - --- -- ---- 1000 1111--0-0110---- | 101 | +| 01000000 - --- -- ---- 1000 1111--0-0111---- | 000 | +| 01000000 - --- -- ---- 1000 1111--0-1000---- | 110 | +| 01000000 - --- -- ---- 1000 1111--0-1001---- | 110 | +| 01000000 - --- -- ---- 1000 1111--0-1010---- | 111 | +| 01000000 - --- -- ---- 1000 1111--0-1011---- | 010 | +| 01000000 - --- -- ---- 1000 1111--0-1100---- | 110 | +| 01000000 - --- -- ---- 1000 1111--0-1101---- | 110 | +| 01000000 - --- -- ---- 1000 1111--0-1110---- | 111 | +| 01000000 - --- -- ---- 1000 1111--0-1111---- | 110 | +| 01000000 - --- -- ---- 1000 1111--1-0000---- | 111 | +| 01000000 - --- -- ---- 1000 1111--1-0001---- | 110 | +| 01000000 - --- -- ---- 1000 1111--1-0010---- | 111 | +| 01000000 - --- -- ---- 1000 1111--1-0011---- | 011 | +| 01000000 - --- -- ---- 1000 1111--1-0100---- | 101 | +| 01000000 - --- -- ---- 1000 1111--1-0101---- | 100 | +| 01000000 - --- -- ---- 1000 1111--1-0110---- | 101 | +| 01000000 - --- -- ---- 1000 1111--1-0111---- | 001 | +| 01000000 - --- -- ---- 1000 1111--1-1000---- | 111 | +| 01000000 - --- -- ---- 1000 1111--1-1001---- | 110 | +| 01000000 - --- -- ---- 1000 1111--1-1010---- | 111 | +| 01000000 - --- -- ---- 1000 1111--1-1011---- | 011 | +| 01000000 - --- -- ---- 1000 1111--1-1100---- | 111 | +| 01000000 - --- -- ---- 1000 1111--1-1101---- | 110 | +| 01000000 - --- -- ---- 1000 1111--1-1110---- | 111 | +| 01000000 - --- -- ---- 1000 1111--1-1111---- | 111 | +| 01000000 - --- -- ---- 0100 1111--0-0000---- | 100 | ierat cc full, hit way1 +| 01000000 - --- -- ---- 0100 1111--0-0001---- | 100 | +| 01000000 - --- -- ---- 0100 1111--0-0010---- | 101 | +| 01000000 - --- -- ---- 0100 1111--0-0011---- | 000 | +| 01000000 - --- -- ---- 0100 1111--0-0100---- | 100 | +| 01000000 - --- -- ---- 0100 1111--0-0101---- | 100 | +| 01000000 - --- -- ---- 0100 1111--0-0110---- | 101 | +| 01000000 - --- -- ---- 0100 1111--0-0111---- | 000 | +| 01000000 - --- -- ---- 0100 1111--0-1000---- | 110 | +| 01000000 - --- -- ---- 0100 1111--0-1001---- | 110 | +| 01000000 - --- -- ---- 0100 1111--0-1010---- | 111 | +| 01000000 - --- -- ---- 0100 1111--0-1011---- | 010 | +| 01000000 - --- -- ---- 0100 1111--0-1100---- | 100 | +| 01000000 - --- -- ---- 0100 1111--0-1101---- | 100 | +| 01000000 - --- -- ---- 0100 1111--0-1110---- | 101 | +| 01000000 - --- -- ---- 0100 1111--0-1111---- | 100 | +| 01000000 - --- -- ---- 0100 1111--1-0000---- | 101 | +| 01000000 - --- -- ---- 0100 1111--1-0001---- | 100 | +| 01000000 - --- -- ---- 0100 1111--1-0010---- | 101 | +| 01000000 - --- -- ---- 0100 1111--1-0011---- | 001 | +| 01000000 - --- -- ---- 0100 1111--1-0100---- | 101 | +| 01000000 - --- -- ---- 0100 1111--1-0101---- | 100 | +| 01000000 - --- -- ---- 0100 1111--1-0110---- | 101 | +| 01000000 - --- -- ---- 0100 1111--1-0111---- | 001 | +| 01000000 - --- -- ---- 0100 1111--1-1000---- | 111 | +| 01000000 - --- -- ---- 0100 1111--1-1001---- | 110 | +| 01000000 - --- -- ---- 0100 1111--1-1010---- | 111 | +| 01000000 - --- -- ---- 0100 1111--1-1011---- | 011 | +| 01000000 - --- -- ---- 0100 1111--1-1100---- | 101 | +| 01000000 - --- -- ---- 0100 1111--1-1101---- | 100 | +| 01000000 - --- -- ---- 0100 1111--1-1110---- | 101 | +| 01000000 - --- -- ---- 0100 1111--1-1111---- | 101 | +| 01000000 - --- -- ---- 0010 1111-0--0000---- | 001 | ierat cc full, hit way2 +| 01000000 - --- -- ---- 0010 1111-0--0001---- | 000 | +| 01000000 - --- -- ---- 0010 1111-0--0010---- | 001 | +| 01000000 - --- -- ---- 0010 1111-0--0011---- | 001 | +| 01000000 - --- -- ---- 0010 1111-0--0100---- | 001 | +| 01000000 - --- -- ---- 0010 1111-0--0101---- | 000 | +| 01000000 - --- -- ---- 0010 1111-0--0110---- | 001 | +| 01000000 - --- -- ---- 0010 1111-0--0111---- | 001 | +| 01000000 - --- -- ---- 0010 1111-0--1000---- | 011 | +| 01000000 - --- -- ---- 0010 1111-0--1001---- | 010 | +| 01000000 - --- -- ---- 0010 1111-0--1010---- | 011 | +| 01000000 - --- -- ---- 0010 1111-0--1011---- | 011 | +| 01000000 - --- -- ---- 0010 1111-0--1100---- | 101 | +| 01000000 - --- -- ---- 0010 1111-0--1101---- | 100 | +| 01000000 - --- -- ---- 0010 1111-0--1110---- | 101 | +| 01000000 - --- -- ---- 0010 1111-0--1111---- | 001 | +| 01000000 - --- -- ---- 0010 1111-1--0000---- | 011 | +| 01000000 - --- -- ---- 0010 1111-1--0001---- | 010 | +| 01000000 - --- -- ---- 0010 1111-1--0010---- | 011 | +| 01000000 - --- -- ---- 0010 1111-1--0011---- | 011 | +| 01000000 - --- -- ---- 0010 1111-1--0100---- | 001 | +| 01000000 - --- -- ---- 0010 1111-1--0101---- | 000 | +| 01000000 - --- -- ---- 0010 1111-1--0110---- | 001 | +| 01000000 - --- -- ---- 0010 1111-1--0111---- | 001 | +| 01000000 - --- -- ---- 0010 1111-1--1000---- | 011 | +| 01000000 - --- -- ---- 0010 1111-1--1001---- | 010 | +| 01000000 - --- -- ---- 0010 1111-1--1010---- | 011 | +| 01000000 - --- -- ---- 0010 1111-1--1011---- | 011 | +| 01000000 - --- -- ---- 0010 1111-1--1100---- | 111 | +| 01000000 - --- -- ---- 0010 1111-1--1101---- | 110 | +| 01000000 - --- -- ---- 0010 1111-1--1110---- | 111 | +| 01000000 - --- -- ---- 0010 1111-1--1111---- | 011 | +| 01000000 - --- -- ---- 0001 1111-0--0000---- | 000 | ierat cc full, hit way3 +| 01000000 - --- -- ---- 0001 1111-0--0001---- | 000 | +| 01000000 - --- -- ---- 0001 1111-0--0010---- | 001 | +| 01000000 - --- -- ---- 0001 1111-0--0011---- | 000 | +| 01000000 - --- -- ---- 0001 1111-0--0100---- | 000 | +| 01000000 - --- -- ---- 0001 1111-0--0101---- | 000 | +| 01000000 - --- -- ---- 0001 1111-0--0110---- | 001 | +| 01000000 - --- -- ---- 0001 1111-0--0111---- | 000 | +| 01000000 - --- -- ---- 0001 1111-0--1000---- | 010 | +| 01000000 - --- -- ---- 0001 1111-0--1001---- | 010 | +| 01000000 - --- -- ---- 0001 1111-0--1010---- | 011 | +| 01000000 - --- -- ---- 0001 1111-0--1011---- | 010 | +| 01000000 - --- -- ---- 0001 1111-0--1100---- | 100 | +| 01000000 - --- -- ---- 0001 1111-0--1101---- | 100 | +| 01000000 - --- -- ---- 0001 1111-0--1110---- | 101 | +| 01000000 - --- -- ---- 0001 1111-0--1111---- | 000 | +| 01000000 - --- -- ---- 0001 1111-1--0000---- | 010 | +| 01000000 - --- -- ---- 0001 1111-1--0001---- | 010 | +| 01000000 - --- -- ---- 0001 1111-1--0010---- | 011 | +| 01000000 - --- -- ---- 0001 1111-1--0011---- | 010 | +| 01000000 - --- -- ---- 0001 1111-1--0100---- | 000 | +| 01000000 - --- -- ---- 0001 1111-1--0101---- | 000 | +| 01000000 - --- -- ---- 0001 1111-1--0110---- | 001 | +| 01000000 - --- -- ---- 0001 1111-1--0111---- | 000 | +| 01000000 - --- -- ---- 0001 1111-1--1000---- | 010 | +| 01000000 - --- -- ---- 0001 1111-1--1001---- | 010 | +| 01000000 - --- -- ---- 0001 1111-1--1010---- | 011 | +| 01000000 - --- -- ---- 0001 1111-1--1011---- | 010 | +| 01000000 - --- -- ---- 0001 1111-1--1100---- | 110 | +| 01000000 - --- -- ---- 0001 1111-1--1101---- | 110 | +| 01000000 - --- -- ---- 0001 1111-1--1110---- | 111 | +| 01000000 - --- -- ---- 0001 1111-1--1111---- | 010 | +| 00001000 - --- -- ---- 0000 ----000--------- | 000 | snoop no hit, no lru change +| 00001000 - --- -- ---- 0000 ----001--------- | 001 | +| 00001000 - --- -- ---- 0000 ----010--------- | 010 | +| 00001000 - --- -- ---- 0000 ----011--------- | 011 | +| 00001000 - --- -- ---- 0000 ----100--------- | 100 | +| 00001000 - --- -- ---- 0000 ----101--------- | 101 | +| 00001000 - --- -- ---- 0000 ----110--------- | 110 | +| 00001000 - --- -- ---- 0000 ----111--------- | 111 | +| 00001000 - --- -- ---- 1--- 0-----0--------- | 000 | snoop hit with existing nonvalid ways +| 00001000 - --- -- ---- 1--- 0-----1--------- | 001 | +| 00001000 - --- -- ---- 1--- 10----0-0------- | 000 | +| 00001000 - --- -- ---- 1--- 10----1-0------- | 001 | +| 00001000 - --- -- ---- 1--- 10----0-1------- | 010 | +| 00001000 - --- -- ---- 1--- 10----1-1------- | 011 | +| 00001000 - --- -- ---- 1--- 110---0-0------- | 000 | +| 00001000 - --- -- ---- 1--- 110---1-0------- | 001 | +| 00001000 - --- -- ---- 1--- 110--0--1------- | 100 | +| 00001000 - --- -- ---- 1--- 110--1--1------- | 110 | +| 00001000 - --- -- ---- 1--- 1110--0-0------- | 000 | +| 00001000 - --- -- ---- 1--- 1110--1-0------- | 001 | +| 00001000 - --- -- ---- 1--- 1110-0--1------- | 101 | +| 00001000 - --- -- ---- 1--- 1110-1--1------- | 111 | +| 00001000 - --- -- ---- 01-- 0-----0--------- | 000 | +| 00001000 - --- -- ---- 01-- 0-----1--------- | 001 | +| 00001000 - --- -- ---- 01-- 10----0--------- | 010 | +| 00001000 - --- -- ---- 01-- 10----1--------- | 011 | +| 00001000 - --- -- ---- 01-- 110---0--0------ | 010 | +| 00001000 - --- -- ---- 01-- 110---1--0------ | 011 | +| 00001000 - --- -- ---- 01-- 110--0---1------ | 100 | +| 00001000 - --- -- ---- 01-- 110--1---1------ | 110 | +| 00001000 - --- -- ---- 01-- 1110--0--0------ | 010 | +| 00001000 - --- -- ---- 01-- 1110--1--0------ | 011 | +| 00001000 - --- -- ---- 01-- 1110-0---1------ | 101 | +| 00001000 - --- -- ---- 01-- 1110-1---1------ | 111 | +| 00001000 - --- -- ---- 001- 0-----0--------- | 000 | +| 00001000 - --- -- ---- 001- 0-----1--------- | 001 | +| 00001000 - --- -- ---- 001- 10----0--------- | 010 | +| 00001000 - --- -- ---- 001- 10----1--------- | 011 | +| 00001000 - --- -- ---- 001- 110--0---------- | 100 | +| 00001000 - --- -- ---- 001- 110--1---------- | 110 | +| 00001000 - --- -- ---- 001- 1110-0----0----- | 100 | +| 00001000 - --- -- ---- 001- 1110-1----0----- | 110 | +| 00001000 - --- -- ---- 001- 1110-0----1----- | 101 | +| 00001000 - --- -- ---- 001- 1110-1----1----- | 111 | +| 00001000 - --- -- ---- 0001 0-----0--------- | 000 | +| 00001000 - --- -- ---- 0001 0-----1--------- | 001 | +| 00001000 - --- -- ---- 0001 10----0--------- | 010 | +| 00001000 - --- -- ---- 0001 10----1--------- | 011 | +| 00001000 - --- -- ---- 0001 110--0---------- | 100 | +| 00001000 - --- -- ---- 0001 110--1---------- | 110 | +| 00001000 - --- -- ---- 0001 1110-0---------- | 101 | +| 00001000 - --- -- ---- 0001 1110-1---------- | 111 | +| 00001000 - --- -- ---- 1--- 1111--0-0------- | 000 | snoop hit way0, all valid, hit is iprot=0 +| 00001000 - --- -- ---- 1--- 1111--1-0------- | 001 | +| 00001000 - --- -- ---- 11-- 1111--0-10------ | 010 | +| 00001000 - --- -- ---- 11-- 1111--1-10------ | 011 | +| 00001000 - --- -- ---- 1-1- 1111-0--110----- | 100 | +| 00001000 - --- -- ---- 1-1- 1111-1--110----- | 110 | +| 00001000 - --- -- ---- 1--1 1111-0--1110---- | 101 | +| 00001000 - --- -- ---- 1--1 1111-1--1110---- | 111 | +| 00001000 - --- -- ---- 01-- 1111--0--0------ | 010 | snoop hit way1, all valid, hit is iprot=0 +| 00001000 - --- -- ---- 01-- 1111--1--0------ | 011 | +| 00001000 - --- -- ---- 011- 1111-0---10----- | 100 | +| 00001000 - --- -- ---- 011- 1111-1---10----- | 110 | +| 00001000 - --- -- ---- 01-1 1111-0---110---- | 101 | +| 00001000 - --- -- ---- 01-1 1111-1---110---- | 111 | +| 00001000 - --- -- ---- 001- 1111-0----0----- | 100 | snoop hit way2, all valid, hit is iprot=0 +| 00001000 - --- -- ---- 001- 1111-1----0----- | 110 | +| 00001000 - --- -- ---- 0011 1111-0----10---- | 101 | +| 00001000 - --- -- ---- 0011 1111-1----10---- | 111 | +| 00001000 - --- -- ---- 0001 1111-0-----0---- | 101 | snoop hit way3, all valid, hit is iprot=0 +| 00001000 - --- -- ---- 0001 1111-1-----0---- | 111 | +| 00001000 - --- -- ---- 1000 1111000-1------- | 000 | snoop hit way0, all valid, hit is iprot=1, no change +| 00001000 - --- -- ---- 1000 1111001-1------- | 001 | +| 00001000 - --- -- ---- 1000 1111010-1------- | 010 | +| 00001000 - --- -- ---- 1000 1111011-1------- | 011 | +| 00001000 - --- -- ---- 1000 1111100-1------- | 100 | +| 00001000 - --- -- ---- 1000 1111101-1------- | 101 | +| 00001000 - --- -- ---- 1000 1111110-1------- | 110 | +| 00001000 - --- -- ---- 1000 1111111-1------- | 111 | +| 00001000 - --- -- ---- 0100 1111000--1------ | 000 | snoop hit way1, all valid, hit is iprot=1, no change +| 00001000 - --- -- ---- 0100 1111001--1------ | 001 | +| 00001000 - --- -- ---- 0100 1111010--1------ | 010 | +| 00001000 - --- -- ---- 0100 1111011--1------ | 011 | +| 00001000 - --- -- ---- 0100 1111100--1------ | 100 | +| 00001000 - --- -- ---- 0100 1111101--1------ | 101 | +| 00001000 - --- -- ---- 0100 1111110--1------ | 110 | +| 00001000 - --- -- ---- 0100 1111111--1------ | 111 | +| 00001000 - --- -- ---- 0010 1111000---1----- | 000 | snoop hit way2, all valid, hit is iprot=1, no change +| 00001000 - --- -- ---- 0010 1111001---1----- | 001 | +| 00001000 - --- -- ---- 0010 1111010---1----- | 010 | +| 00001000 - --- -- ---- 0010 1111011---1----- | 011 | +| 00001000 - --- -- ---- 0010 1111100---1----- | 100 | +| 00001000 - --- -- ---- 0010 1111101---1----- | 101 | +| 00001000 - --- -- ---- 0010 1111110---1----- | 110 | +| 00001000 - --- -- ---- 0010 1111111---1----- | 111 | +| 00001000 - --- -- ---- 0001 1111000----1---- | 000 | snoop hit way3, all valid, hit is iprot=1, no change +| 00001000 - --- -- ---- 0001 1111001----1---- | 001 | +| 00001000 - --- -- ---- 0001 1111010----1---- | 010 | +| 00001000 - --- -- ---- 0001 1111011----1---- | 011 | +| 00001000 - --- -- ---- 0001 1111100----1---- | 100 | +| 00001000 - --- -- ---- 0001 1111101----1---- | 101 | +| 00001000 - --- -- ---- 0001 1111110----1---- | 110 | +| 00001000 - --- -- ---- 0001 1111111----1---- | 111 | +| 00001000 - --- -- ---- 1100 1111000-11------ | 000 | snoop multihit, all valid, all hits are iprot=1, no change +| 00001000 - --- -- ---- 1100 1111001-11------ | 001 | +| 00001000 - --- -- ---- 1100 1111010-11------ | 010 | +| 00001000 - --- -- ---- 1100 1111011-11------ | 011 | +| 00001000 - --- -- ---- 1100 1111100-11------ | 100 | +| 00001000 - --- -- ---- 1100 1111101-11------ | 101 | +| 00001000 - --- -- ---- 1100 1111110-11------ | 110 | +| 00001000 - --- -- ---- 1100 1111111-11------ | 111 | +| 00001000 - --- -- ---- 1010 1111000-1-1----- | 000 | snoop multihit, all valid, all hits are iprot=1, no change +| 00001000 - --- -- ---- 1010 1111001-1-1----- | 001 | +| 00001000 - --- -- ---- 1010 1111010-1-1----- | 010 | +| 00001000 - --- -- ---- 1010 1111011-1-1----- | 011 | +| 00001000 - --- -- ---- 1010 1111100-1-1----- | 100 | +| 00001000 - --- -- ---- 1010 1111101-1-1----- | 101 | +| 00001000 - --- -- ---- 1010 1111110-1-1----- | 110 | +| 00001000 - --- -- ---- 1010 1111111-1-1----- | 111 | +| 00001000 - --- -- ---- 1110 1111000-111----- | 000 | snoop multihit, all valid, all hits are iprot=1, no change +| 00001000 - --- -- ---- 1110 1111001-111----- | 001 | +| 00001000 - --- -- ---- 1110 1111010-111----- | 010 | +| 00001000 - --- -- ---- 1110 1111011-111----- | 011 | +| 00001000 - --- -- ---- 1110 1111100-111----- | 100 | +| 00001000 - --- -- ---- 1110 1111101-111----- | 101 | +| 00001000 - --- -- ---- 1110 1111110-111----- | 110 | +| 00001000 - --- -- ---- 1110 1111111-111----- | 111 | +| 00001000 - --- -- ---- 1001 1111000-1--1---- | 000 | snoop multihit, all valid, all hits are iprot=1, no change +| 00001000 - --- -- ---- 1001 1111001-1--1---- | 001 | +| 00001000 - --- -- ---- 1001 1111010-1--1---- | 010 | +| 00001000 - --- -- ---- 1001 1111011-1--1---- | 011 | +| 00001000 - --- -- ---- 1001 1111100-1--1---- | 100 | +| 00001000 - --- -- ---- 1001 1111101-1--1---- | 101 | +| 00001000 - --- -- ---- 1001 1111110-1--1---- | 110 | +| 00001000 - --- -- ---- 1001 1111111-1--1---- | 111 | +| 00001000 - --- -- ---- 1101 1111000-11-1---- | 000 | snoop multihit, all valid, all hits are iprot=1, no change +| 00001000 - --- -- ---- 1101 1111001-11-1---- | 001 | +| 00001000 - --- -- ---- 1101 1111010-11-1---- | 010 | +| 00001000 - --- -- ---- 1101 1111011-11-1---- | 011 | +| 00001000 - --- -- ---- 1101 1111100-11-1---- | 100 | +| 00001000 - --- -- ---- 1101 1111101-11-1---- | 101 | +| 00001000 - --- -- ---- 1101 1111110-11-1---- | 110 | +| 00001000 - --- -- ---- 1101 1111111-11-1---- | 111 | +| 00001000 - --- -- ---- 1110 1111000-111----- | 000 | snoop multihit, all valid, all hits are iprot=1, no change +| 00001000 - --- -- ---- 1110 1111001-111----- | 001 | +| 00001000 - --- -- ---- 1110 1111010-111----- | 010 | +| 00001000 - --- -- ---- 1110 1111011-111----- | 011 | +| 00001000 - --- -- ---- 1110 1111100-111----- | 100 | +| 00001000 - --- -- ---- 1110 1111101-111----- | 101 | +| 00001000 - --- -- ---- 1110 1111110-111----- | 110 | +| 00001000 - --- -- ---- 1110 1111111-111----- | 111 | +| 00001000 - --- -- ---- 1111 1111000-1111---- | 000 | snoop multihit, all valid, all hits are iprot=1, no change +| 00001000 - --- -- ---- 1111 1111001-1111---- | 001 | +| 00001000 - --- -- ---- 1111 1111010-1111---- | 010 | +| 00001000 - --- -- ---- 1111 1111011-1111---- | 011 | +| 00001000 - --- -- ---- 1111 1111100-1111---- | 100 | +| 00001000 - --- -- ---- 1111 1111101-1111---- | 101 | +| 00001000 - --- -- ---- 1111 1111110-1111---- | 110 | +| 00001000 - --- -- ---- 1111 1111111-1111---- | 111 | +| 00001000 - --- -- ---- 0110 1111000--11----- | 000 | snoop multihit, all valid, all hits are iprot=1, no change +| 00001000 - --- -- ---- 0110 1111001--11----- | 001 | +| 00001000 - --- -- ---- 0110 1111010--11----- | 010 | +| 00001000 - --- -- ---- 0110 1111011--11----- | 011 | +| 00001000 - --- -- ---- 0110 1111100--11----- | 100 | +| 00001000 - --- -- ---- 0110 1111101--11----- | 101 | +| 00001000 - --- -- ---- 0110 1111110--11----- | 110 | +| 00001000 - --- -- ---- 0110 1111111--11----- | 111 | +| 00001000 - --- -- ---- 0101 1111000--1-1---- | 000 | snoop multihit, all valid, all hits are iprot=1, no change +| 00001000 - --- -- ---- 0101 1111001--1-1---- | 001 | +| 00001000 - --- -- ---- 0101 1111010--1-1---- | 010 | +| 00001000 - --- -- ---- 0101 1111011--1-1---- | 011 | +| 00001000 - --- -- ---- 0101 1111100--1-1---- | 100 | +| 00001000 - --- -- ---- 0101 1111101--1-1---- | 101 | +| 00001000 - --- -- ---- 0101 1111110--1-1---- | 110 | +| 00001000 - --- -- ---- 0101 1111111--1-1---- | 111 | +| 00001000 - --- -- ---- 0111 1111000--111---- | 000 | snoop multihit, all valid, all hits are iprot=1, no change +| 00001000 - --- -- ---- 0111 1111001--111---- | 001 | +| 00001000 - --- -- ---- 0111 1111010--111---- | 010 | +| 00001000 - --- -- ---- 0111 1111011--111---- | 011 | +| 00001000 - --- -- ---- 0111 1111100--111---- | 100 | +| 00001000 - --- -- ---- 0111 1111101--111---- | 101 | +| 00001000 - --- -- ---- 0111 1111110--111---- | 110 | +| 00001000 - --- -- ---- 0111 1111111--111---- | 111 | +| 00001000 - --- -- ---- 0011 1111000---11---- | 000 | snoop multihit, all valid, all hits are iprot=1, no change +| 00001000 - --- -- ---- 0011 1111001---11---- | 001 | +| 00001000 - --- -- ---- 0011 1111010---11---- | 010 | +| 00001000 - --- -- ---- 0011 1111011---11---- | 011 | +| 00001000 - --- -- ---- 0011 1111100---11---- | 100 | +| 00001000 - --- -- ---- 0011 1111101---11---- | 101 | +| 00001000 - --- -- ---- 0011 1111110---11---- | 110 | +| 00001000 - --- -- ---- 0011 1111111---11---- | 111 | +| 00000010 0 -0- -- 0--- ---- 0-----0--------- | 000 | tlbwe v=0 and hes=0, unused tagpos_is def is mas1_v, mas1_iprot for tlbwe +| 00000010 0 -0- -- 0--- ---- 0-----1--------- | 001 | +| 00000010 0 -10 -- 0--- ---- 0--------------- | 000 | +| 00000010 0 -11 -- 0--- ---- 0-0------------- | 000 | +| 00000010 0 -11 -- 0--- ---- 0-1------------- | 001 | +| 00000010 0 -00 -- 0--- ---- 1-----0--------- | 000 | +| 00000010 0 -00 -- 0--- ---- 1-----1--------- | 001 | +| 00000010 0 -01 -- 0--- ---- 1-----0--------- | 010 | +| 00000010 0 -01 -- 0--- ---- 1-----1--------- | 011 | +| 00000010 0 -10 -- 0--- ---- 10-------------- | 010 | +| 00000010 0 -11 -- 0--- ---- 100------------- | 010 | +| 00000010 0 -11 -- 0--- ---- 101------------- | 011 | +| 00000010 0 -1- -- 0--- ---- 110--0---------- | 100 | +| 00000010 0 -1- -- 0--- ---- 110--1---------- | 110 | +| 00000010 0 -10 -- 0--- ---- 111--0---------- | 100 | +| 00000010 0 -10 -- 0--- ---- 111--1---------- | 110 | +| 00000010 0 -11 -- 0--- ---- 111--0---------- | 101 | +| 00000010 0 -11 -- 0--- ---- 111--1---------- | 111 | +| 00000010 1 --- -- 0--- ---- 0---0-0--------- | 000 | tlbwe v=0 and hes=1, unused tagpos_is def is mas1_v, mas1_iprot for tlbwe +| 00000010 1 --- -- 0--- ---- 0---0-1--------- | 001 | +| 00000010 1 --- -- 0--- ---- 0---1-0--------- | 000 | +| 00000010 1 --- -- 0--- ---- 0-0-1-1--------- | 000 | +| 00000010 1 --- -- 0--- ---- 0-1-1-1--------- | 001 | +| 00000010 1 --- -- 0--- ---- 1---000--------- | 000 | +| 00000010 1 --- -- 0--- ---- 1---001--------- | 001 | +| 00000010 1 --- -- 0--- ---- 1---010--------- | 010 | +| 00000010 1 --- -- 0--- ---- 1---011--------- | 011 | +| 00000010 1 --- -- 0--- ---- 10--1-0--------- | 010 | +| 00000010 1 --- -- 0--- ---- 100-1-1--------- | 010 | +| 00000010 1 --- -- 0--- ---- 101-1-1--------- | 011 | +| 00000010 1 --- -- 0--- ---- 110-10---------- | 100 | +| 00000010 1 --- -- 0--- ---- 110-11---------- | 110 | +| 00000010 1 --- -- 0--- ---- 111-100--------- | 100 | +| 00000010 1 --- -- 0--- ---- 111-110--------- | 110 | +| 00000010 1 --- -- 0--- ---- 111-101--------- | 101 | +| 00000010 1 --- -- 0--- ---- 111-111--------- | 111 | +| 00000010 0 -01 -- 1--- ---- 0-----0--------- | 000 | tlbwe v=1, hes=0, esel/=open way, unused tagpos_is def is mas1_v, mas1_iprot for tlbwe +| 00000010 0 -01 -- 1--- ---- 0-----1--------- | 001 | +| 00000010 0 -10 -- 10-- ---- 0----------0---- | 001 | +| 00000010 0 -10 -- 10-- ---- 0----------1---- | 000 | +| 00000010 0 -10 -- 11-- ---- 0--------------- | 001 | +| 00000010 0 -11 -- 10-- ---- 0---------0----- | 000 | +| 00000010 0 -11 -- 10-- ---- 0---------1----- | 001 | +| 00000010 0 -11 -- 11-- ---- 0--------------- | 000 | +| 00000010 0 -00 -- 1--- ---- 10----0--------- | 010 | +| 00000010 0 -00 -- 1--- ---- 10----1--------- | 011 | +| 00000010 0 -10 -- 10-- ---- 10---------0---- | 011 | +| 00000010 0 -10 -- 10-- ---- 10---------1---- | 010 | +| 00000010 0 -10 -- 11-- ---- 10-------------- | 011 | +| 00000010 0 -11 -- 10-- ---- 10--------0----- | 010 | +| 00000010 0 -11 -- 10-- ---- 10--------1----- | 011 | +| 00000010 0 -11 -- 11-- ---- 10-------------- | 010 | +| 00000010 0 -00 -- 10-- ---- 110------0------ | 110 | +| 00000010 0 -00 -- 10-- ---- 110------1------ | 100 | +| 00000010 0 -00 -- 11-- ---- 110------------- | 110 | +| 00000010 0 -01 -- 10-- ---- 110-----0------- | 100 | +| 00000010 0 -01 -- 10-- ---- 110-----1------- | 110 | +| 00000010 0 -01 -- 11-- ---- 110------------- | 100 | +| 00000010 0 -11 -- 1--- ---- 110--0---------- | 100 | +| 00000010 0 -11 -- 1--- ---- 110--1---------- | 110 | +| 00000010 0 -00 -- 10-- ---- 1110-----0------ | 111 | +| 00000010 0 -00 -- 10-- ---- 1110-----1------ | 101 | +| 00000010 0 -00 -- 11-- ---- 1110------------ | 111 | +| 00000010 0 -01 -- 10-- ---- 1110----0------- | 101 | +| 00000010 0 -01 -- 10-- ---- 1110----1------- | 111 | +| 00000010 0 -01 -- 11-- ---- 1110------------ | 101 | +| 00000010 0 -10 -- 1--- ---- 1110-0---------- | 101 | +| 00000010 0 -10 -- 1--- ---- 1110-1---------- | 111 | +| 00000010 0 -00 -- 1--- ---- 00----0--------- | 010 | tlbwe v=1, hes=0, esel=0=first open way, multiple open ways +| 00000010 0 -00 -- 1--- ---- 00----1--------- | 011 | +| 00000010 0 -00 -- 1--- ---- 010------0------ | 110 | +| 00000010 0 -00 -- 10-- ---- 010------1------ | 100 | +| 00000010 0 -00 -- 11-- ---- 010------1------ | 110 | +| 00000010 0 -00 -- 1--- ---- 0110-----0------ | 111 | +| 00000010 0 -00 -- 10-- ---- 0110-----1------ | 101 | +| 00000010 0 -00 -- 11-- ---- 0110-----1------ | 111 | +| 00000010 0 -01 -- 1--- ---- 100-----0------- | 100 | tlbwe v=1, hes=0, esel=1=first open way, multiple open ways +| 00000010 0 -01 -- 10-- ---- 100-----1------- | 110 | +| 00000010 0 -01 -- 11-- ---- 100-----1------- | 100 | +| 00000010 0 -01 -- 1--- ---- 1010----0------- | 101 | +| 00000010 0 -01 -- 10-- ---- 1010----1------- | 111 | +| 00000010 0 -01 -- 11-- ---- 1010----1------- | 101 | +| 00000010 0 -10 -- 1--- ---- 1100-0---------- | 101 | tlbwe v=1, hes=0, esel=2=first open way, multiple open ways +| 00000010 0 -10 -- 1--- ---- 1100-1---------- | 111 | +| 00000010 0 -00 -- 1--- ---- 0111--0--00----- | 110 | tlbwe v=1, hes=0, esel=0=open way, 1 open way +| 00000010 0 -00 -- 1--- ---- 0111--0--010---- | 111 | +| 00000010 0 -00 -- 1--- ---- 0111--1--0-0---- | 111 | +| 00000010 0 -00 -- 1--- ---- 0111--1--001---- | 110 | +| 00000010 0 -00 -- 10-- ---- 0111--0--10----- | 100 | +| 00000010 0 -00 -- 10-- ---- 0111--0--110---- | 101 | +| 00000010 0 -00 -- 10-- ---- 0111--1--1-0---- | 101 | +| 00000010 0 -00 -- 10-- ---- 0111--1--101---- | 100 | +| 00000010 0 -00 -- 11-- ---- 0111--0--10----- | 110 | +| 00000010 0 -00 -- 11-- ---- 0111--0--110---- | 111 | +| 00000010 0 -00 -- 11-- ---- 0111--1--1-0---- | 111 | +| 00000010 0 -00 -- 11-- ---- 0111--1--101---- | 110 | +| 00000010 0 -00 -- 1--- ---- 0111--0--011---- | 010 | +| 00000010 0 -00 -- 1--- ---- 0111--1--011---- | 011 | +| 00000010 0 -00 -- 10-- ---- 0111--0--111---- | 000 | +| 00000010 0 -00 -- 10-- ---- 0111--1--111---- | 001 | +| 00000010 0 -00 -- 11-- ---- 0111--0--111---- | 110 | +| 00000010 0 -00 -- 11-- ---- 0111--1--111---- | 111 | +| 00000010 0 -01 -- 1--- ---- 1011--0-0-0----- | 100 | tlbwe v=1, hes=0, esel=1=open way, 1 open way +| 00000010 0 -01 -- 1--- ---- 1011--0-0-10---- | 101 | +| 00000010 0 -01 -- 1--- ---- 1011--1-0--0---- | 101 | +| 00000010 0 -01 -- 1--- ---- 1011--1-0-01---- | 100 | +| 00000010 0 -01 -- 10-- ---- 1011--0-1-0----- | 110 | +| 00000010 0 -01 -- 10-- ---- 1011--0-1-10---- | 111 | +| 00000010 0 -01 -- 10-- ---- 1011--1-1--0---- | 111 | +| 00000010 0 -01 -- 10-- ---- 1011--1-1-01---- | 110 | +| 00000010 0 -01 -- 11-- ---- 1011--0-1-0----- | 100 | +| 00000010 0 -01 -- 11-- ---- 1011--0-1-10---- | 101 | +| 00000010 0 -01 -- 11-- ---- 1011--1-1--0---- | 101 | +| 00000010 0 -01 -- 11-- ---- 1011--1-1-01---- | 100 | +| 00000010 0 -01 -- 1--- ---- 1011--0-0-11---- | 000 | +| 00000010 0 -01 -- 1--- ---- 1011--1-0-11---- | 001 | +| 00000010 0 -01 -- 10-- ---- 1011--0-1-11---- | 010 | +| 00000010 0 -01 -- 10-- ---- 1011--1-1-11---- | 011 | +| 00000010 0 -01 -- 11-- ---- 1011--0-1-11---- | 100 | +| 00000010 0 -01 -- 11-- ---- 1011--1-1-11---- | 101 | +| 00000010 0 -10 -- 1--- ---- 1101-0--0--0---- | 001 | tlbwe v=1, hes=0, esel=2=open way, 1 open way +| 00000010 0 -10 -- 1--- ---- 1101-0--10-0---- | 011 | +| 00000010 0 -10 -- 1--- ---- 1101-1---0-0---- | 011 | +| 00000010 0 -10 -- 1--- ---- 1101-1--01-0---- | 001 | +| 00000010 0 -10 -- 10-- ---- 1101-0--0--1---- | 000 | +| 00000010 0 -10 -- 10-- ---- 1101-0--10-1---- | 010 | +| 00000010 0 -10 -- 10-- ---- 1101-1---0-1---- | 010 | +| 00000010 0 -10 -- 10-- ---- 1101-1--01-1---- | 000 | +| 00000010 0 -10 -- 11-- ---- 1101-0--0--1---- | 001 | +| 00000010 0 -10 -- 11-- ---- 1101-0--10-1---- | 011 | +| 00000010 0 -10 -- 11-- ---- 1101-1---0-1---- | 011 | +| 00000010 0 -10 -- 11-- ---- 1101-1--01-1---- | 001 | +| 00000010 0 -10 -- 1--- ---- 1101-0--11-0---- | 101 | +| 00000010 0 -10 -- 1--- ---- 1101-1--11-0---- | 111 | +| 00000010 0 -10 -- 10-- ---- 1101-0--11-1---- | 100 | +| 00000010 0 -10 -- 10-- ---- 1101-1--11-1---- | 110 | +| 00000010 0 -10 -- 11-- ---- 1101-0--11-1---- | 001 | +| 00000010 0 -10 -- 11-- ---- 1101-1--11-1---- | 011 | +| 00000010 0 -11 -- 1--- ---- 1110-0--0-0----- | 000 | tlbwe v=1, hes=0, esel=3=open way, 1 open way +| 00000010 0 -11 -- 1--- ---- 1110-0--100----- | 010 | +| 00000010 0 -11 -- 1--- ---- 1110-1---00----- | 010 | +| 00000010 0 -11 -- 1--- ---- 1110-1--010----- | 000 | +| 00000010 0 -11 -- 10-- ---- 1110-0--0-1----- | 001 | +| 00000010 0 -11 -- 10-- ---- 1110-0--101----- | 011 | +| 00000010 0 -11 -- 10-- ---- 1110-1---01----- | 011 | +| 00000010 0 -11 -- 10-- ---- 1110-1--011----- | 001 | +| 00000010 0 -11 -- 11-- ---- 1110-0--0-1----- | 000 | +| 00000010 0 -11 -- 11-- ---- 1110-0--101----- | 010 | +| 00000010 0 -11 -- 11-- ---- 1110-1---01----- | 010 | +| 00000010 0 -11 -- 11-- ---- 1110-1--011----- | 000 | +| 00000010 0 -11 -- 1--- ---- 1110-0--110----- | 100 | +| 00000010 0 -11 -- 1--- ---- 1110-1--110----- | 110 | +| 00000010 0 -11 -- 10-- ---- 1110-0--111----- | 101 | +| 00000010 0 -11 -- 10-- ---- 1110-1--111----- | 111 | +| 00000010 0 -11 -- 11-- ---- 1110-0--111----- | 000 | +| 00000010 0 -11 -- 11-- ---- 1110-1--111----- | 010 | +| 00000010 0 -00 -- 1--- ---- 1111--0--00----- | 110 | tlbwe v=1, hes=0, esel=0, full ways +| 00000010 0 -00 -- 1--- ---- 1111--0--010---- | 111 | +| 00000010 0 -00 -- 1--- ---- 1111--1--0-0---- | 111 | +| 00000010 0 -00 -- 1--- ---- 1111--1--001---- | 110 | +| 00000010 0 -00 -- 10-- ---- 1111--0--10----- | 100 | +| 00000010 0 -00 -- 10-- ---- 1111--0--110---- | 101 | +| 00000010 0 -00 -- 10-- ---- 1111--1--1-0---- | 101 | +| 00000010 0 -00 -- 10-- ---- 1111--1--101---- | 100 | +| 00000010 0 -00 -- 11-- ---- 1111--0--10----- | 110 | +| 00000010 0 -00 -- 11-- ---- 1111--0--110---- | 111 | +| 00000010 0 -00 -- 11-- ---- 1111--1--1-0---- | 111 | +| 00000010 0 -00 -- 11-- ---- 1111--1--101---- | 110 | +| 00000010 0 -00 -- 1--- ---- 1111--0--011---- | 010 | +| 00000010 0 -00 -- 1--- ---- 1111--1--011---- | 011 | +| 00000010 0 -00 -- 10-- ---- 1111--0--111---- | 000 | +| 00000010 0 -00 -- 10-- ---- 1111--1--111---- | 001 | +| 00000010 0 -00 -- 11-- ---- 1111--0--111---- | 110 | +| 00000010 0 -00 -- 11-- ---- 1111--1--111---- | 111 | +| 00000010 0 -01 -- 1--- ---- 1111--0-0-0----- | 100 | tlbwe v=1, hes=0, esel=1, full ways +| 00000010 0 -01 -- 1--- ---- 1111--0-0-10---- | 101 | +| 00000010 0 -01 -- 1--- ---- 1111--1-0--0---- | 101 | +| 00000010 0 -01 -- 1--- ---- 1111--1-0-01---- | 100 | +| 00000010 0 -01 -- 10-- ---- 1111--0-1-0----- | 110 | +| 00000010 0 -01 -- 10-- ---- 1111--0-1-10---- | 111 | +| 00000010 0 -01 -- 10-- ---- 1111--1-1--0---- | 111 | +| 00000010 0 -01 -- 10-- ---- 1111--1-1-01---- | 110 | +| 00000010 0 -01 -- 11-- ---- 1111--0-1-0----- | 100 | +| 00000010 0 -01 -- 11-- ---- 1111--0-1-10---- | 101 | +| 00000010 0 -01 -- 11-- ---- 1111--1-1--0---- | 101 | +| 00000010 0 -01 -- 11-- ---- 1111--1-1-01---- | 100 | +| 00000010 0 -01 -- 1--- ---- 1111--0-0-11---- | 000 | +| 00000010 0 -01 -- 1--- ---- 1111--1-0-11---- | 001 | +| 00000010 0 -01 -- 10-- ---- 1111--0-1-11---- | 010 | +| 00000010 0 -01 -- 10-- ---- 1111--1-1-11---- | 011 | +| 00000010 0 -01 -- 11-- ---- 1111--0-1-11---- | 100 | +| 00000010 0 -01 -- 11-- ---- 1111--1-1-11---- | 101 | +| 00000010 0 -10 -- 1--- ---- 1111-0--0--0---- | 001 | tlbwe v=1, hes=0, esel=2, full ways +| 00000010 0 -10 -- 1--- ---- 1111-0--10-0---- | 011 | +| 00000010 0 -10 -- 1--- ---- 1111-1---0-0---- | 011 | +| 00000010 0 -10 -- 1--- ---- 1111-1--01-0---- | 001 | +| 00000010 0 -10 -- 10-- ---- 1111-0--0--1---- | 000 | +| 00000010 0 -10 -- 10-- ---- 1111-0--10-1---- | 010 | +| 00000010 0 -10 -- 10-- ---- 1111-1---0-1---- | 010 | +| 00000010 0 -10 -- 10-- ---- 1111-1--01-1---- | 000 | +| 00000010 0 -10 -- 11-- ---- 1111-0--0--1---- | 001 | +| 00000010 0 -10 -- 11-- ---- 1111-0--10-1---- | 011 | +| 00000010 0 -10 -- 11-- ---- 1111-1---0-1---- | 011 | +| 00000010 0 -10 -- 11-- ---- 1111-1--01-1---- | 001 | +| 00000010 0 -10 -- 1--- ---- 1111-0--11-0---- | 101 | +| 00000010 0 -10 -- 1--- ---- 1111-1--11-0---- | 111 | +| 00000010 0 -10 -- 10-- ---- 1111-0--11-1---- | 100 | +| 00000010 0 -10 -- 10-- ---- 1111-1--11-1---- | 110 | +| 00000010 0 -10 -- 11-- ---- 1111-0--11-1---- | 001 | +| 00000010 0 -10 -- 11-- ---- 1111-1--11-1---- | 011 | +| 00000010 0 -11 -- 1--- ---- 1111-0--0-0----- | 000 | tlbwe v=1, hes=0, esel=3, full ways +| 00000010 0 -11 -- 1--- ---- 1111-0--100----- | 010 | +| 00000010 0 -11 -- 1--- ---- 1111-1---00----- | 010 | +| 00000010 0 -11 -- 1--- ---- 1111-1--010----- | 000 | +| 00000010 0 -11 -- 10-- ---- 1111-0--0-1----- | 001 | +| 00000010 0 -11 -- 10-- ---- 1111-0--101----- | 011 | +| 00000010 0 -11 -- 10-- ---- 1111-1---01----- | 011 | +| 00000010 0 -11 -- 10-- ---- 1111-1--011----- | 001 | +| 00000010 0 -11 -- 11-- ---- 1111-0--0-1----- | 000 | +| 00000010 0 -11 -- 11-- ---- 1111-0--101----- | 010 | +| 00000010 0 -11 -- 11-- ---- 1111-1---01----- | 010 | +| 00000010 0 -11 -- 11-- ---- 1111-1--011----- | 000 | +| 00000010 0 -11 -- 1--- ---- 1111-0--110----- | 100 | +| 00000010 0 -11 -- 1--- ---- 1111-1--110----- | 110 | +| 00000010 0 -11 -- 10-- ---- 1111-0--111----- | 101 | +| 00000010 0 -11 -- 10-- ---- 1111-1--111----- | 111 | +| 00000010 0 -11 -- 11-- ---- 1111-0--111----- | 000 | +| 00000010 0 -11 -- 11-- ---- 1111-1--111----- | 010 | +| 00000010 1 --- -- 1--- ---- 0---010--------- | 000 | tlbwe v=1, hes=1, lru/=first open way, unused tagpos_is def is mas1_v, mas1_iprot for tlbwe +| 00000010 1 --- -- 1--- ---- 0---011--------- | 001 | +| 00000010 1 --- -- 10-- ---- 0---1-0----0---- | 001 | +| 00000010 1 --- -- 10-- ---- 0---1-0----1---- | 000 | +| 00000010 1 --- -- 11-- ---- 0---1-0--------- | 001 | +| 00000010 1 --- -- 10-- ---- 0---1-1---0----- | 000 | +| 00000010 1 --- -- 10-- ---- 0---1-1---1----- | 001 | +| 00000010 1 --- -- 11-- ---- 0---1-1--------- | 000 | +| 00000010 1 --- -- 1--- ---- 10--000--------- | 010 | +| 00000010 1 --- -- 1--- ---- 10--001--------- | 011 | +| 00000010 1 --- -- 10-- ---- 10--1-0----0---- | 011 | +| 00000010 1 --- -- 10-- ---- 10--1-0----1---- | 010 | +| 00000010 1 --- -- 11-- ---- 10--1-0--------- | 011 | +| 00000010 1 --- -- 10-- ---- 10--1-1---0----- | 010 | +| 00000010 1 --- -- 10-- ---- 10--1-1---1----- | 011 | +| 00000010 1 --- -- 11-- ---- 10--1-1--------- | 010 | +| 00000010 1 --- -- 10-- ---- 110-00---0------ | 110 | +| 00000010 1 --- -- 10-- ---- 110-00---1------ | 100 | +| 00000010 1 --- -- 11-- ---- 110-00---------- | 110 | +| 00000010 1 --- -- 10-- ---- 110-01--0------- | 100 | +| 00000010 1 --- -- 10-- ---- 110-01--1------- | 110 | +| 00000010 1 --- -- 11-- ---- 110-01---------- | 100 | +| 00000010 1 --- -- 1--- ---- 110-101--------- | 100 | +| 00000010 1 --- -- 1--- ---- 110-111--------- | 110 | +| 00000010 1 --- -- 10-- ---- 111000---0------ | 111 | +| 00000010 1 --- -- 10-- ---- 111000---1------ | 101 | +| 00000010 1 --- -- 11-- ---- 111000---------- | 111 | +| 00000010 1 --- -- 10-- ---- 111001--0------- | 101 | +| 00000010 1 --- -- 10-- ---- 111001--1------- | 111 | +| 00000010 1 --- -- 11-- ---- 111001---------- | 101 | +| 00000010 1 --- -- 1--- ---- 1110100--------- | 101 | +| 00000010 1 --- -- 1--- ---- 1110110--------- | 111 | +| 00000010 1 --- -- 1--- ---- 00--000--------- | 010 | tlbwe v=1, hes=1, lsu=0=first open way, multiple open ways +| 00000010 1 --- -- 1--- ---- 00--001--------- | 011 | +| 00000010 1 --- -- 1--- ---- 010-00---0------ | 110 | +| 00000010 1 --- -- 10-- ---- 010-00---1------ | 100 | +| 00000010 1 --- -- 11-- ---- 010-00---1------ | 110 | +| 00000010 1 --- -- 1--- ---- 011000---0------ | 111 | +| 00000010 1 --- -- 10-- ---- 011000---1------ | 101 | +| 00000010 1 --- -- 11-- ---- 011000---1------ | 111 | +| 00000010 1 --- -- 1--- ---- 100-01--0------- | 100 | tlbwe v=1, hes=1, lsu=1=first open way, multiple open ways +| 00000010 1 --- -- 10-- ---- 100-01--1------- | 110 | +| 00000010 1 --- -- 11-- ---- 100-01--1------- | 100 | +| 00000010 1 --- -- 1--- ---- 101001--0------- | 101 | +| 00000010 1 --- -- 10-- ---- 101001--1------- | 111 | +| 00000010 1 --- -- 11-- ---- 101001--1------- | 101 | +| 00000010 1 --- -- 1--- ---- 1100100--------- | 101 | tlbwe v=1, hes=1, lru=2=first open way, multiple open ways +| 00000010 1 --- -- 1--- ---- 1100110--------- | 111 | +| 00000010 1 --- -- 1--- ---- 0111000--00----- | 110 | tlbwe v=1, hes=1, lru=0=open way, 1 open way +| 00000010 1 --- -- 1--- ---- 0111000--010---- | 111 | +| 00000010 1 --- -- 1--- ---- 0111001--0-0---- | 111 | +| 00000010 1 --- -- 1--- ---- 0111001--001---- | 110 | +| 00000010 1 --- -- 10-- ---- 0111000--10----- | 100 | +| 00000010 1 --- -- 10-- ---- 0111000--110---- | 101 | +| 00000010 1 --- -- 10-- ---- 0111001--1-0---- | 101 | +| 00000010 1 --- -- 10-- ---- 0111001--101---- | 100 | +| 00000010 1 --- -- 11-- ---- 0111000--10----- | 110 | +| 00000010 1 --- -- 11-- ---- 0111000--110---- | 111 | +| 00000010 1 --- -- 11-- ---- 0111001--1-0---- | 111 | +| 00000010 1 --- -- 11-- ---- 0111001--101---- | 110 | +| 00000010 1 --- -- 1--- ---- 0111000--011---- | 010 | +| 00000010 1 --- -- 1--- ---- 0111001--011---- | 011 | +| 00000010 1 --- -- 10-- ---- 0111000--111---- | 000 | +| 00000010 1 --- -- 10-- ---- 0111001--111---- | 001 | +| 00000010 1 --- -- 11-- ---- 0111000--111---- | 110 | +| 00000010 1 --- -- 11-- ---- 0111001--111---- | 111 | +| 00000010 1 --- -- 1--- ---- 1011010-0-0----- | 100 | tlbwe v=1, hes=1, lru=1=open way, 1 open way +| 00000010 1 --- -- 1--- ---- 1011010-0-10---- | 101 | +| 00000010 1 --- -- 1--- ---- 1011011-0--0---- | 101 | +| 00000010 1 --- -- 1--- ---- 1011011-0-01---- | 100 | +| 00000010 1 --- -- 10-- ---- 1011010-1-0----- | 110 | +| 00000010 1 --- -- 10-- ---- 1011010-1-10---- | 111 | +| 00000010 1 --- -- 10-- ---- 1011011-1--0---- | 111 | +| 00000010 1 --- -- 10-- ---- 1011011-1-01---- | 110 | +| 00000010 1 --- -- 11-- ---- 1011010-1-0----- | 100 | +| 00000010 1 --- -- 11-- ---- 1011010-1-10---- | 101 | +| 00000010 1 --- -- 11-- ---- 1011011-1--0---- | 101 | +| 00000010 1 --- -- 11-- ---- 1011011-1-01---- | 100 | +| 00000010 1 --- -- 1--- ---- 1011010-0-11---- | 000 | +| 00000010 1 --- -- 1--- ---- 1011011-0-11---- | 001 | +| 00000010 1 --- -- 10-- ---- 1011010-1-11---- | 010 | +| 00000010 1 --- -- 10-- ---- 1011011-1-11---- | 011 | +| 00000010 1 --- -- 11-- ---- 1011010-1-11---- | 100 | +| 00000010 1 --- -- 11-- ---- 1011011-1-11---- | 101 | +| 00000010 1 --- -- 1--- ---- 1101100-0--0---- | 001 | tlbwe v=1, hes=1, lru=2=open way, 1 open way +| 00000010 1 --- -- 1--- ---- 1101100-10-0---- | 011 | +| 00000010 1 --- -- 1--- ---- 1101110--0-0---- | 011 | +| 00000010 1 --- -- 1--- ---- 1101110-01-0---- | 001 | +| 00000010 1 --- -- 10-- ---- 1101100-0--1---- | 000 | +| 00000010 1 --- -- 10-- ---- 1101100-10-1---- | 010 | +| 00000010 1 --- -- 10-- ---- 1101110--0-1---- | 010 | +| 00000010 1 --- -- 10-- ---- 1101110-01-1---- | 000 | +| 00000010 1 --- -- 11-- ---- 1101100-0--1---- | 001 | +| 00000010 1 --- -- 11-- ---- 1101100-10-1---- | 011 | +| 00000010 1 --- -- 11-- ---- 1101110--0-1---- | 011 | +| 00000010 1 --- -- 11-- ---- 1101110-01-1---- | 001 | +| 00000010 1 --- -- 1--- ---- 1101100-11-0---- | 101 | +| 00000010 1 --- -- 1--- ---- 1101110-11-0---- | 111 | +| 00000010 1 --- -- 10-- ---- 1101100-11-1---- | 100 | +| 00000010 1 --- -- 10-- ---- 1101110-11-1---- | 110 | +| 00000010 1 --- -- 11-- ---- 1101100-11-1---- | 001 | +| 00000010 1 --- -- 11-- ---- 1101110-11-1---- | 011 | +| 00000010 1 --- -- 1--- ---- 1110101-0-0----- | 000 | tlbwe v=1, hes=1, lru=3=open way, 1 open way +| 00000010 1 --- -- 1--- ---- 1110101-100----- | 010 | +| 00000010 1 --- -- 1--- ---- 1110111--00----- | 010 | +| 00000010 1 --- -- 1--- ---- 1110111-010----- | 000 | +| 00000010 1 --- -- 10-- ---- 1110101-0-1----- | 001 | +| 00000010 1 --- -- 10-- ---- 1110101-101----- | 011 | +| 00000010 1 --- -- 10-- ---- 1110111--01----- | 011 | +| 00000010 1 --- -- 10-- ---- 1110111-011----- | 001 | +| 00000010 1 --- -- 11-- ---- 1110101-0-1----- | 000 | +| 00000010 1 --- -- 11-- ---- 1110101-101----- | 010 | +| 00000010 1 --- -- 11-- ---- 1110111--01----- | 010 | +| 00000010 1 --- -- 11-- ---- 1110111-011----- | 000 | +| 00000010 1 --- -- 1--- ---- 1110101-110----- | 100 | +| 00000010 1 --- -- 1--- ---- 1110111-110----- | 110 | +| 00000010 1 --- -- 10-- ---- 1110101-111----- | 101 | +| 00000010 1 --- -- 10-- ---- 1110111-111----- | 111 | +| 00000010 1 --- -- 11-- ---- 1110101-111----- | 000 | +| 00000010 1 --- -- 11-- ---- 1110111-111----- | 010 | +| 00000010 1 --- -- 1--- ---- 1111000--00----- | 110 | tlbwe v=1, hes=1, lru=0, full ways +| 00000010 1 --- -- 1--- ---- 1111000--010---- | 111 | +| 00000010 1 --- -- 1--- ---- 1111001--0-0---- | 111 | +| 00000010 1 --- -- 1--- ---- 1111001--001---- | 110 | +| 00000010 1 --- -- 10-- ---- 1111000--10----- | 100 | +| 00000010 1 --- -- 10-- ---- 1111000--110---- | 101 | +| 00000010 1 --- -- 10-- ---- 1111001--1-0---- | 101 | +| 00000010 1 --- -- 10-- ---- 1111001--101---- | 100 | +| 00000010 1 --- -- 11-- ---- 1111000--10----- | 110 | +| 00000010 1 --- -- 11-- ---- 1111000--110---- | 111 | +| 00000010 1 --- -- 11-- ---- 1111001--1-0---- | 111 | +| 00000010 1 --- -- 11-- ---- 1111001--101---- | 110 | +| 00000010 1 --- -- 1--- ---- 1111000--011---- | 010 | +| 00000010 1 --- -- 1--- ---- 1111001--011---- | 011 | +| 00000010 1 --- -- 10-- ---- 1111000--111---- | 000 | +| 00000010 1 --- -- 10-- ---- 1111001--111---- | 001 | +| 00000010 1 --- -- 11-- ---- 1111000--111---- | 110 | +| 00000010 1 --- -- 11-- ---- 1111001--111---- | 111 | +| 00000010 1 --- -- 1--- ---- 1111010-0-0----- | 100 | tlbwe v=1, hes=1, lru=1, full ways +| 00000010 1 --- -- 1--- ---- 1111010-0-10---- | 101 | +| 00000010 1 --- -- 1--- ---- 1111011-0--0---- | 101 | +| 00000010 1 --- -- 1--- ---- 1111011-0-01---- | 100 | +| 00000010 1 --- -- 10-- ---- 1111010-1-0----- | 110 | +| 00000010 1 --- -- 10-- ---- 1111010-1-10---- | 111 | +| 00000010 1 --- -- 10-- ---- 1111011-1--0---- | 111 | +| 00000010 1 --- -- 10-- ---- 1111011-1-01---- | 110 | +| 00000010 1 --- -- 11-- ---- 1111010-1-0----- | 100 | +| 00000010 1 --- -- 11-- ---- 1111010-1-10---- | 101 | +| 00000010 1 --- -- 11-- ---- 1111011-1--0---- | 101 | +| 00000010 1 --- -- 11-- ---- 1111011-1-01---- | 100 | +| 00000010 1 --- -- 1--- ---- 1111010-0-11---- | 000 | +| 00000010 1 --- -- 1--- ---- 1111011-0-11---- | 001 | +| 00000010 1 --- -- 10-- ---- 1111010-1-11---- | 010 | +| 00000010 1 --- -- 10-- ---- 1111011-1-11---- | 011 | +| 00000010 1 --- -- 11-- ---- 1111010-1-11---- | 100 | +| 00000010 1 --- -- 11-- ---- 1111011-1-11---- | 101 | +| 00000010 1 --- -- 1--- ---- 1111100-0--0---- | 001 | tlbwe v=1, hes=1, lru=2, full ways +| 00000010 1 --- -- 1--- ---- 1111100-10-0---- | 011 | +| 00000010 1 --- -- 1--- ---- 1111110--0-0---- | 011 | +| 00000010 1 --- -- 1--- ---- 1111110-01-0---- | 001 | +| 00000010 1 --- -- 10-- ---- 1111100-0--1---- | 000 | +| 00000010 1 --- -- 10-- ---- 1111100-10-1---- | 010 | +| 00000010 1 --- -- 10-- ---- 1111110--0-1---- | 010 | +| 00000010 1 --- -- 10-- ---- 1111110-01-1---- | 000 | +| 00000010 1 --- -- 11-- ---- 1111100-0--1---- | 001 | +| 00000010 1 --- -- 11-- ---- 1111100-10-1---- | 011 | +| 00000010 1 --- -- 11-- ---- 1111110--0-1---- | 011 | +| 00000010 1 --- -- 11-- ---- 1111110-01-1---- | 001 | +| 00000010 1 --- -- 1--- ---- 1111100-11-0---- | 101 | +| 00000010 1 --- -- 1--- ---- 1111110-11-0---- | 111 | +| 00000010 1 --- -- 10-- ---- 1111100-11-1---- | 100 | +| 00000010 1 --- -- 10-- ---- 1111110-11-1---- | 110 | +| 00000010 1 --- -- 11-- ---- 1111100-11-1---- | 001 | +| 00000010 1 --- -- 11-- ---- 1111110-11-1---- | 011 | +| 00000010 1 --- -- 1--- ---- 1111101-0-0----- | 000 | tlbwe v=1, hes=1, lru=3, full ways +| 00000010 1 --- -- 1--- ---- 1111101-100----- | 010 | +| 00000010 1 --- -- 1--- ---- 1111111--00----- | 010 | +| 00000010 1 --- -- 1--- ---- 1111111-010----- | 000 | +| 00000010 1 --- -- 10-- ---- 1111101-0-1----- | 001 | +| 00000010 1 --- -- 10-- ---- 1111101-101----- | 011 | +| 00000010 1 --- -- 10-- ---- 1111111--01----- | 011 | +| 00000010 1 --- -- 10-- ---- 1111111-011----- | 001 | +| 00000010 1 --- -- 11-- ---- 1111101-0-1----- | 000 | +| 00000010 1 --- -- 11-- ---- 1111101-101----- | 010 | +| 00000010 1 --- -- 11-- ---- 1111111--01----- | 010 | +| 00000010 1 --- -- 11-- ---- 1111111-011----- | 000 | +| 00000010 1 --- -- 1--- ---- 1111101-110----- | 100 | +| 00000010 1 --- -- 1--- ---- 1111111-110----- | 110 | +| 00000010 1 --- -- 10-- ---- 1111101-111----- | 101 | +| 00000010 1 --- -- 10-- ---- 1111111-111----- | 111 | +| 00000010 1 --- -- 11-- ---- 1111101-111----- | 000 | +| 00000010 1 --- -- 11-- ---- 1111111-111----- | 010 | +| --000001 - --- -- 0--- ---- ----000--------- | 000 | ptereload v=0, no change (pt_fault) +| --000001 - --- -- 0--- ---- ----001--------- | 001 | +| --000001 - --- -- 0--- ---- ----010--------- | 010 | +| --000001 - --- -- 0--- ---- ----011--------- | 011 | +| --000001 - --- -- 0--- ---- ----100--------- | 100 | +| --000001 - --- -- 0--- ---- ----101--------- | 101 | +| --000001 - --- -- 0--- ---- ----110--------- | 110 | +| --000001 - --- -- 0--- ---- ----111--------- | 111 | +| --000001 - --- -- 1--- ---- 0---010--------- | 000 | ptereload v=1, hes=1 and iprot=0 assumed, lru/=first open way +| --000001 - --- -- 1--- ---- 0---011--------- | 001 | +| --000001 - --- -- 1--- ---- 0---1-0----0---- | 001 | +| --000001 - --- -- 1--- ---- 0---1-0----1---- | 000 | +| --000001 - --- -- 1--- ---- 0---1-1---0----- | 000 | +| --000001 - --- -- 1--- ---- 0---1-1---1----- | 001 | +| --000001 - --- -- 1--- ---- 10--000--------- | 010 | +| --000001 - --- -- 1--- ---- 10--001--------- | 011 | +| --000001 - --- -- 1--- ---- 10--1-0----0---- | 011 | +| --000001 - --- -- 1--- ---- 10--1-0----1---- | 010 | +| --000001 - --- -- 1--- ---- 10--1-1---0----- | 010 | +| --000001 - --- -- 1--- ---- 10--1-1---1----- | 011 | +| --000001 - --- -- 1--- ---- 110-00---0------ | 110 | +| --000001 - --- -- 1--- ---- 110-00---1------ | 100 | +| --000001 - --- -- 1--- ---- 110-01--0------- | 100 | +| --000001 - --- -- 1--- ---- 110-01--1------- | 110 | +| --000001 - --- -- 1--- ---- 110-101--------- | 100 | +| --000001 - --- -- 1--- ---- 110-111--------- | 110 | +| --000001 - --- -- 1--- ---- 111000---0------ | 111 | +| --000001 - --- -- 1--- ---- 111000---1------ | 101 | +| --000001 - --- -- 1--- ---- 111001--0------- | 101 | +| --000001 - --- -- 1--- ---- 111001--1------- | 111 | +| --000001 - --- -- 1--- ---- 1110100--------- | 101 | +| --000001 - --- -- 1--- ---- 1110110--------- | 111 | +| --000001 - --- -- 1--- ---- 00--000--------- | 010 | ptereload v=1, hes=1 and iprot=0 assumed, lsu=0=first open way, multiple open ways +| --000001 - --- -- 1--- ---- 00--001--------- | 011 | +| --000001 - --- -- 1--- ---- 010-00---0------ | 110 | +| --000001 - --- -- 1--- ---- 010-00---1------ | 100 | +| --000001 - --- -- 1--- ---- 011000---0------ | 111 | +| --000001 - --- -- 1--- ---- 011000---1------ | 101 | +| --000001 - --- -- 1--- ---- 100-01--0------- | 100 | ptereload v=1, hes=1 and iprot=0 assumed, lsu=1=first open way, multiple open ways +| --000001 - --- -- 1--- ---- 100-01--1------- | 110 | +| --000001 - --- -- 1--- ---- 101001--0------- | 101 | +| --000001 - --- -- 1--- ---- 101001--1------- | 111 | +| --000001 - --- -- 1--- ---- 1100100--------- | 101 | ptereload v=1, hes=1 and iprot=0 assumed, lru=2=first open way, multiple open ways +| --000001 - --- -- 1--- ---- 1100110--------- | 111 | +| --000001 - --- -- 1--- ---- 0111000--00----- | 110 | ptereload v=1, hes=1 and iprot=0 assumed, lru=0=open way, 1 open way +| --000001 - --- -- 1--- ---- 0111000--010---- | 111 | +| --000001 - --- -- 1--- ---- 0111001--0-0---- | 111 | +| --000001 - --- -- 1--- ---- 0111001--001---- | 110 | +| --000001 - --- -- 1--- ---- 0111000--10----- | 100 | +| --000001 - --- -- 1--- ---- 0111000--110---- | 101 | +| --000001 - --- -- 1--- ---- 0111001--1-0---- | 101 | +| --000001 - --- -- 1--- ---- 0111001--101---- | 100 | +| --000001 - --- -- 1--- ---- 0111000--011---- | 010 | +| --000001 - --- -- 1--- ---- 0111001--011---- | 011 | +| --000001 - --- -- 1--- ---- 0111000--111---- | 000 | +| --000001 - --- -- 1--- ---- 0111001--111---- | 001 | +| --000001 - --- -- 1--- ---- 1011010-0-0----- | 100 | ptereload v=1, hes=1 and iprot=0 assumed, lru=1=open way, 1 open way +| --000001 - --- -- 1--- ---- 1011010-0-10---- | 101 | +| --000001 - --- -- 1--- ---- 1011011-0--0---- | 101 | +| --000001 - --- -- 1--- ---- 1011011-0-01---- | 100 | +| --000001 - --- -- 1--- ---- 1011010-1-0----- | 110 | +| --000001 - --- -- 1--- ---- 1011010-1-10---- | 111 | +| --000001 - --- -- 1--- ---- 1011011-1--0---- | 111 | +| --000001 - --- -- 1--- ---- 1011011-1-01---- | 110 | +| --000001 - --- -- 1--- ---- 1011010-0-11---- | 000 | +| --000001 - --- -- 1--- ---- 1011011-0-11---- | 001 | +| --000001 - --- -- 1--- ---- 1011010-1-11---- | 010 | +| --000001 - --- -- 1--- ---- 1011011-1-11---- | 011 | +| --000001 - --- -- 1--- ---- 1101100-0--0---- | 001 | ptereload v=1, hes=1 and iprot=0 assumed, lru=2=open way, 1 open way +| --000001 - --- -- 1--- ---- 1101100-10-0---- | 011 | +| --000001 - --- -- 1--- ---- 1101110--0-0---- | 011 | +| --000001 - --- -- 1--- ---- 1101110-01-0---- | 001 | +| --000001 - --- -- 1--- ---- 1101100-0--1---- | 000 | +| --000001 - --- -- 1--- ---- 1101100-10-1---- | 010 | +| --000001 - --- -- 1--- ---- 1101110--0-1---- | 010 | +| --000001 - --- -- 1--- ---- 1101110-01-1---- | 000 | +| --000001 - --- -- 1--- ---- 1101100-11-0---- | 101 | +| --000001 - --- -- 1--- ---- 1101110-11-0---- | 111 | +| --000001 - --- -- 1--- ---- 1101100-11-1---- | 100 | +| --000001 - --- -- 1--- ---- 1101110-11-1---- | 110 | +| --000001 - --- -- 1--- ---- 1110101-0-0----- | 000 | ptereload v=1, hes=1 and iprot=0 assumed, lru=3=open way, 1 open way +| --000001 - --- -- 1--- ---- 1110101-100----- | 010 | +| --000001 - --- -- 1--- ---- 1110111--00----- | 010 | +| --000001 - --- -- 1--- ---- 1110111-010----- | 000 | +| --000001 - --- -- 1--- ---- 1110101-0-1----- | 001 | +| --000001 - --- -- 1--- ---- 1110101-101----- | 011 | +| --000001 - --- -- 1--- ---- 1110111--01----- | 011 | +| --000001 - --- -- 1--- ---- 1110111-011----- | 001 | +| --000001 - --- -- 1--- ---- 1110101-110----- | 100 | +| --000001 - --- -- 1--- ---- 1110111-110----- | 110 | +| --000001 - --- -- 1--- ---- 1110101-111----- | 101 | +| --000001 - --- -- 1--- ---- 1110111-111----- | 111 | +| --000001 - --- -- 1--- ---- 1111000-000----- | 110 | ptereload v=1, hes=1 and iprot=0 assumed, lru=0, full ways +| --000001 - --- -- 1--- ---- 1111000-0010---- | 111 | +| --000001 - --- -- 1--- ---- 1111001-00-0---- | 111 | +| --000001 - --- -- 1--- ---- 1111001-0001---- | 110 | +| --000001 - --- -- 1--- ---- 1111000-010----- | 100 | +| --000001 - --- -- 1--- ---- 1111000-0110---- | 101 | +| --000001 - --- -- 1--- ---- 1111001-01-0---- | 101 | +| --000001 - --- -- 1--- ---- 1111001-0101---- | 100 | +| --000001 - --- -- 1--- ---- 1111000-0011---- | 010 | +| --000001 - --- -- 1--- ---- 1111001-0011---- | 011 | +| --000001 - --- -- 1--- ---- 1111000-0111---- | 000 | +| --000001 - --- -- 1--- ---- 1111001-0111---- | 001 | +| --000001 - --- -- 1--- ---- 1111010-000----- | 100 | ptereload v=1, hes=1 and iprot=0 assumed, lru=1, full ways +| --000001 - --- -- 1--- ---- 1111010-0010---- | 101 | +| --000001 - --- -- 1--- ---- 1111011-00-0---- | 101 | +| --000001 - --- -- 1--- ---- 1111011-0001---- | 100 | +| --000001 - --- -- 1--- ---- 1111010-100----- | 110 | +| --000001 - --- -- 1--- ---- 1111010-1010---- | 111 | +| --000001 - --- -- 1--- ---- 1111011-10-0---- | 111 | +| --000001 - --- -- 1--- ---- 1111011-1001---- | 110 | +| --000001 - --- -- 1--- ---- 1111010-0011---- | 000 | +| --000001 - --- -- 1--- ---- 1111011-0011---- | 001 | +| --000001 - --- -- 1--- ---- 1111010-1011---- | 010 | +| --000001 - --- -- 1--- ---- 1111011-1011---- | 011 | +| --000001 - --- -- 1--- ---- 1111100-0-00---- | 001 | ptereload v=1, hes=1 and iprot=0 assumed, lru=2, full ways +| --000001 - --- -- 1--- ---- 1111100-1000---- | 011 | +| --000001 - --- -- 1--- ---- 1111110--000---- | 011 | +| --000001 - --- -- 1--- ---- 1111110-0100---- | 001 | +| --000001 - --- -- 1--- ---- 1111100-0-01---- | 000 | +| --000001 - --- -- 1--- ---- 1111100-1001---- | 010 | +| --000001 - --- -- 1--- ---- 1111110--001---- | 010 | +| --000001 - --- -- 1--- ---- 1111110-0101---- | 000 | +| --000001 - --- -- 1--- ---- 1111100-1100---- | 101 | +| --000001 - --- -- 1--- ---- 1111110-1100---- | 111 | +| --000001 - --- -- 1--- ---- 1111100-1101---- | 100 | +| --000001 - --- -- 1--- ---- 1111110-1101---- | 110 | +| --000001 - --- -- 1--- ---- 1111101-0-00---- | 000 | ptereload v=1, hes=1 and iprot=0 assumed, lru=3, full ways +| --000001 - --- -- 1--- ---- 1111101-1000---- | 010 | +| --000001 - --- -- 1--- ---- 1111111--000---- | 010 | +| --000001 - --- -- 1--- ---- 1111111-0100---- | 000 | +| --000001 - --- -- 1--- ---- 1111101-0-10---- | 001 | +| --000001 - --- -- 1--- ---- 1111101-1010---- | 011 | +| --000001 - --- -- 1--- ---- 1111111--010---- | 011 | +| --000001 - --- -- 1--- ---- 1111111-0110---- | 001 | +| --000001 - --- -- 1--- ---- 1111101-1100---- | 100 | +| --000001 - --- -- 1--- ---- 1111111-1100---- | 110 | +| --000001 - --- -- 1--- ---- 1111101-1110---- | 101 | +| --000001 - --- -- 1--- ---- 1111111-1110---- | 111 | +| --000001 - --- -- 1--- ---- 1111000-1111---- | 000 | ptereload v=1, cc full, all protected, no change +| --000001 - --- -- 1--- ---- 1111001-1111---- | 001 | +| --000001 - --- -- 1--- ---- 1111010-1111---- | 010 | +| --000001 - --- -- 1--- ---- 1111011-1111---- | 011 | +| --000001 - --- -- 1--- ---- 1111100-1111---- | 100 | +| --000001 - --- -- 1--- ---- 1111101-1111---- | 101 | +| --000001 - --- -- 1--- ---- 1111110-1111---- | 110 | +| --000001 - --- -- 1--- ---- 1111111-1111---- | 111 | +*END*===============================================+=====================+ +?TABLE END lru_update_data; +//table_end +*/ + + // + // Final Table Listing + // *INPUTS*============================================*OUTPUTS*=============* + // | | | + // | tlb_tag4_type_sig | lru_update_data | + // | | tlb_tag4_hes_sig | | | + // | | | tlb_tag4_esel_sig | | | + // | | | | tlb_tag4_wq_sig | | | + // | | | | | tlb_tag4_is_sig | | | + // | | | | | | tlb_tag4_wayhit_q | | | + // | | | | | | | lru_tag4_dataout_q | | | + // | | | | | | | | | | | + // | | | | | | | | | | | + // | | | | | | | | 111111 | | | + // | 01234567 | 012 01 0123 0123 0123456789012345 | 012 | + // *TYPE*==============================================+=====================+ + // | PPPPPPPP P PPP PP PPPP PPPP PPPPPPPPPPPPPPPP | PPP | + // *POLARITY*----------------------------------------->| +++ | + // *PHASE*-------------------------------------------->| TTT | + // *OPTIMIZE*----------------------------------------->| AAA | + // *TERMS*=============================================+=====================+ + // 1 | ------00 - --- -- ---- ---1 111-----1110---- | 1.1 | + // 2 | ----1--- - --- -- ---- 0--1 111------110---- | 1.1 | + // 3 | ------1- 1 --- -- 1--- ---- -11-00----10---- | 1.1 | + // 4 | -------1 - --- -- 1--- ---- -11-00----10---- | 1.1 | + // 5 | ------1- 1 --- -- 1--- ---- 1-1-01----10---- | 1.1 | + // 6 | -------1 - --- -- 1--- ---- 1-1-01----10---- | 1.1 | + // 7 | ------00 - --- -- ---- 00-1 111-------10---- | ..1 | + // 8 | ----0-00 - --- -- ---- -1-- 111-------10---- | 1.1 | + // 9 | ----0-00 - --- -- ---- 1--- 111-------10---- | 1.1 | + // 10 | ------1- 0 -00 -- 1--- ---- -11-------10---- | 1.1 | + // 11 | ------1- 0 -01 -- 1--- ---- 1-1-------10---- | 1.1 | + // 12 | -------- 1 --- -- ---- ---- 11--1-0-11-0---- | 1.. | + // 13 | ----0-00 - --- -- ---- --1- 11------11-0---- | 1.. | + // 14 | ------1- 0 -10 -- ---- ---- 11------11-0---- | 1.. | + // 15 | ------1- 1 --- -- 1--- ---- ----1-0----0---- | ..1 | + // 16 | -------1 - --- -- 1--- ---- ----1-0----0---- | ..1 | + // 17 | ------1- 1 --- -- ---- ---- --1-0-1----0---- | ..1 | + // 18 | -------1 - --- -- ---- ---- --1-0-1----0---- | ..1 | + // 19 | ----0-00 - --- -- ---- ---0 --1---1----0---- | ..1 | + // 20 | ------1- 0 -0- -- ---- ---- --1---1----0---- | ..1 | + // 21 | ----1--- - --- -- ---- 0001 111--------0---- | ..1 | + // 22 | ----0-00 - --- -- ---- --1- 111--------0---- | ..1 | + // 23 | ----1--- - --- -- ---- 00-1 11---------0---- | 1.. | + // 24 | ------1- 0 -10 -- 1--- ---- -----------0---- | ..1 | + // 25 | -------- 1 --- -- ---- ---- 11--1-1-110----- | 1.. | + // 26 | ----0-00 - --- -- ---- ---1 11------110----- | 1.. | + // 27 | ------00 - --- -- ---- --1- 11------110----- | 1.. | + // 28 | ------1- 0 -11 -- ---- ---- 11------110----- | 1.. | + // 29 | ----1--- - --- -- ---- 0-1- 11-------10----- | 1.. | + // 30 | ------1- 1 --- -- 1--- ---- -1--00----0----- | 1.. | + // 31 | -------1 - --- -- 1--- ---- -1--00----0----- | 1.. | + // 32 | ------1- 1 --- -- 1--- ---- 1---01----0----- | 1.. | + // 33 | -------1 - --- -- 1--- ---- 1---01----0----- | 1.. | + // 34 | ----1--- - --- -- ---- 001- 11--------0----- | 1.. | + // 35 | ----0-00 - --- -- ---- -1-- 11--------0----- | 1.. | + // 36 | ----0-00 - --- -- ---- 1--- 11--------0----- | 1.. | + // 37 | ------1- 0 -00 -- 1--- ---- -1--------0----- | 1.. | + // 38 | ------1- 0 -01 -- 1--- ---- 1---------0----- | 1.. | + // 39 | ------1- 1 --- -- ---- ---- --1-0-1---1----- | ..1 | + // 40 | -------1 - --- -- ---- ---- 10--1-1---1----- | ..1 | + // 41 | -------- 1 --- -- 10-- ---- -0--1-1---1----- | ..1 | + // 42 | -------- 1 --- -- 10-- ---- 0---1-1---1----- | ..1 | + // 43 | ------0- - --- -- ---- ---- 0---1-1---1----- | ..1 | + // 44 | ------0- - --- -- ---- ---0 --1---1---1----- | ..1 | + // 45 | ------0- - --- -- ---- --1- --1---1---1----- | ..1 | + // 46 | ------1- 1 --- -- -0-- ---- --1---1---1----- | ..1 | + // 47 | ------1- 0 -0- -- ---- ---- --1---1---1----- | ..1 | + // 48 | -------1 - --- -- ---- ---- --1---1---1----- | ..1 | + // 49 | ----1--- - --- -- ---- 001- 1110------1----- | 1.1 | + // 50 | ----0-00 - --- -- ---- --1- 111-------1----- | ..1 | + // 51 | ------1- 0 -11 -- -0-- ---- --1-------1----- | ..1 | + // 52 | ------1- 0 -11 -- 10-- ---- -0--------1----- | ..1 | + // 53 | ------1- 0 -11 -- 10-- ---- 0---------1----- | ..1 | + // 54 | ------1- 1 --- -- 1--- ---- 1--11-0-10------ | .1. | + // 55 | -------1 - --- -- 1--- ---- 1--1--0-10------ | .1. | + // 56 | ------1- 1 --- -- 1--- ---- 1-1-1-1-10------ | .1. | + // 57 | -------1 - --- -- 1--- ---- 1-1---1-10------ | .1. | + // 58 | ----0-00 - --- -- ---- ---1 1-11----10------ | .1. | + // 59 | ----0-00 - --- -- ---- --1- 1-11----10------ | .1. | + // 60 | ------00 - --- -- ---- -1-- 1-11----10------ | .1. | + // 61 | ------1- 0 --0 -- 1--- ---- 1--1----10------ | .1. | + // 62 | ------1- 0 -11 -- 1--- ---- 1-1-----10------ | .1. | + // 63 | ------00 - --- -- ---- 11-- --1---1--0------ | ..1 | + // 64 | ----1--- - --- -- ---- 01-- ------1--0------ | ..1 | + // 65 | ------1- 1 --- -- 1--- ---- ----00---0------ | .1. | + // 66 | -------1 - --- -- 1--- ---- ----00---0------ | .1. | + // 67 | ------1- 1 --- -- ---- ---- 1---11---0------ | .1. | + // 68 | -------1 - --- -- ---- ---- 1---11---0------ | .1. | + // 69 | ----0-00 - --- -- ---- -0-- 1----1---0------ | .1. | + // 70 | ------1- 0 -1- -- ---- ---- 1----1---0------ | .1. | + // 71 | ----0-00 - --- -- ---- 1--- 1-11-----0------ | .1. | + // 72 | ----1--- - --- -- ---- 01-- 1--------0------ | .1. | + // 73 | ------1- 0 -00 -- 1--- ---- ---------0------ | .1. | + // 74 | ------0- - --- -- ---- -1-- 11--1---11------ | 1.. | + // 75 | ------1- 1 --- -- -0-- ---- 11--1---11------ | 1.. | + // 76 | -------1 - --- -- ---- ---- 11--1---11------ | 1.. | + // 77 | ----0-00 - --- -- ---- 1--- 1111----11------ | 11. | + // 78 | ----0-00 - --- -- ---- -1-- 11------11------ | 1.. | + // 79 | ------1- 0 -1- -- -0-- ---- 11------11------ | 1.. | + // 80 | ------1- 1 --- -- 11-- ---- -1--00---1------ | 11. | + // 81 | ----1--- - --- -- ---- 0--- 11--1----1------ | 1.. | + // 82 | ----1--- - --- -- ---- 01-- 1110-----1------ | 1.1 | + // 83 | ----1--- - --- -- ---- 01-- 110------1------ | 1.. | + // 84 | ------1- 0 -00 -- 11-- ---- -1-------1------ | 11. | + // 85 | ----1--- - --- -- ---- 1--- ------1-0------- | ..1 | + // 86 | ------1- 1 --- -- 11-- ---- 1---01--1------- | 1.. | + // 87 | ------1- 1 --- -- ---- ---- 1---11--1------- | .1. | + // 88 | ------0- - --- -- ---- -0-- 1----1--1------- | .1. | + // 89 | ------0- - --- -- ---- 1--- 1----1--1------- | .1. | + // 90 | ------1- 1 --- -- -0-- ---- 1----1--1------- | .1. | + // 91 | ------1- 0 -1- -- ---- ---- 1----1--1------- | .1. | + // 92 | -------1 - --- -- ---- ---- 1----1--1------- | .1. | + // 93 | ----1--- - --- -- ---- -0-- 11--1---1------- | 1.. | + // 94 | ----1--- - --- -- ---- 1--- 1110----1------- | 1.1 | + // 95 | ----1--- - --- -- ---- 1--- 110-----1------- | 1.. | + // 96 | ----1--- - --- -- ---- 1--- 10------1------- | .1. | + // 97 | ------1- 0 -01 -- -0-- ---- 1-------1------- | .1. | + // 98 | ------1- 0 -01 -- 11-- ---- 1-------1------- | 1.. | + // 99 | ----0--- 1 --- -- ---- ---- 1--0110--------- | .1. | + // 100 | -------1 - --- -- ---- ---- 1--0110--------- | .1. | + // 101 | ------1- 1 --- -- 1--- ---- 11-01-0--------- | 1.1 | + // 102 | -------1 - --- -- 1--- ---- 11-01-0--------- | 1.1 | + // 103 | ------1- 1 --- -- 11-- ---- ----1-0--------- | ..1 | + // 104 | -------- 1 --- -- ---- ---- -0--001--------- | ..1 | + // 105 | -------1 - --- -- ---- ---- -0--001--------- | ..1 | + // 106 | -------- 1 --- -- ---- ---- 0---011--------- | ..1 | + // 107 | ------0- - --- -- ---- ---- 0---011--------- | ..1 | + // 108 | ----0--- 1 --- -- ---- ---- 1-0-111--------- | .1. | + // 109 | -------1 - --- -- ---- ---- 1-0-111--------- | .1. | + // 110 | ------1- 1 --- -- 0--- ---- ----0-1--------- | ..1 | + // 111 | ----0--- 1 --- -- 1--- ---- 110---1--------- | 1.. | + // 112 | -------1 - --- -- 1--- ---- 110---1--------- | 1.. | + // 113 | ------00 - --- -- ---- 0000 --1---1--------- | ..1 | + // 114 | ----1--- - --- -- ---- --0- --1---1--------- | ..1 | + // 115 | ------1- 1 --- -- 0--- ---- --1---1--------- | ..1 | + // 116 | ------1- 0 -00 -- ---- ---- -0----1--------- | ..1 | + // 117 | ------00 - --- -- ---- ---- -0----1--------- | ..1 | + // 118 | ------1- 0 -01 -- ---- ---- 0-----1--------- | ..1 | + // 119 | ------00 - --- -- ---- ---- 0-----1--------- | ..1 | + // 120 | ----1--- - --- -- ---- 0000 ------1--------- | ..1 | + // 121 | ------1- 0 -0- -- 0--- ---- ------1--------- | ..1 | + // 122 | -------1 - --- -- 0--- ---- ------1--------- | ..1 | + // 123 | ------1- 1 --- -- 1--- ---- -11000---------- | 1.1 | + // 124 | -------1 - --- -- 1--- ---- -11000---------- | 1.1 | + // 125 | ------1- 1 --- -- 1--- ---- -10-00---------- | 1.. | + // 126 | -------1 - --- -- 1--- ---- -10-00---------- | 1.. | + // 127 | ------1- 1 --- -- 1--- ---- -0--00---------- | .1. | + // 128 | -------1 - --- -- 1--- ---- -0--00---------- | .1. | + // 129 | ------1- 1 --- -- 1--- ---- 1-1001---------- | 1.1 | + // 130 | -------1 - --- -- 1--- ---- 1-1001---------- | 1.1 | + // 131 | ------1- 1 --- -- 1--- ---- 1-0-01---------- | 1.. | + // 132 | -------1 - --- -- 1--- ---- 1-0-01---------- | 1.. | + // 133 | ------1- 0 -10 -- ---- ---- 1--0-1---------- | .1. | + // 134 | ----0-00 - --- -- ---- ---- 1--0-1---------- | .1. | + // 135 | ------1- 0 -11 -- ---- ---- 1-0--1---------- | .1. | + // 136 | ----0-00 - --- -- ---- ---- 1-0--1---------- | .1. | + // 137 | ------00 - --- -- ---- 0000 1----1---------- | .1. | + // 138 | ----1--- - --- -- ---- 0--- 1----1---------- | .1. | + // 139 | ------1- - -1- -- 0--- ---- 1----1---------- | .1. | + // 140 | ------1- 1 --- -- 0--- ---- 1----1---------- | .1. | + // 141 | ----1--- - --- -- ---- 0000 -----1---------- | .1. | + // 142 | -------1 - --- -- 0--- ---- -----1---------- | .1. | + // 143 | -------1 - --- -- 1--- ---- 10--1----------- | .1. | + // 144 | ------1- 1 --- -- ---- ---- 10--1----------- | .1. | + // 145 | ------00 - --- -- ---- 0000 11--1----------- | 1.. | + // 146 | ----1--- - --- -- ---- 00-- 11--1----------- | 1.. | + // 147 | ------1- 1 --- -- 0--- ---- 11--1----------- | 1.. | + // 148 | ----1--- - --- -- ---- 0000 ----1----------- | 1.. | + // 149 | -------1 - --- -- 0--- ---- ----1----------- | 1.. | + // 150 | ----1--- - --- -- ---- 0001 1110------------ | 1.1 | + // 151 | ----0-00 - --- -- ---- ---- 1110------------ | 1.1 | + // 152 | ------1- 0 -00 -- 1--- ---- -110------------ | 1.1 | + // 153 | ------1- 0 -01 -- 1--- ---- 1-10------------ | 1.1 | + // 154 | ------1- 0 -10 -- 1--- ---- 11-0------------ | 1.1 | + // 155 | ----1--- - --- -- ---- 00-1 110------------- | 1.. | + // 156 | ----1--- - --- -- ---- 001- 110------------- | 1.. | + // 157 | ------1- 0 -11 -- ---- ---- 110------------- | 1.. | + // 158 | ----0-00 - --- -- ---- ---- 110------------- | 1.. | + // 159 | ------1- 0 -00 -- 1--- ---- -10------------- | 1.. | + // 160 | ------1- 0 -01 -- 1--- ---- 1-0------------- | 1.. | + // 161 | ------1- 0 -11 -- 0--- ---- --1------------- | ..1 | + // 162 | ----1--- - --- -- ---- 0--1 10-------------- | .1. | + // 163 | ----1--- - --- -- ---- 0-1- 10-------------- | .1. | + // 164 | ----1--- - --- -- ---- 01-- 10-------------- | .1. | + // 165 | ------1- 0 -1- -- ---- ---- 10-------------- | .1. | + // 166 | ----0-00 - --- -- ---- ---- 10-------------- | .1. | + // 167 | ------1- 0 -00 -- 1--- ---- -0-------------- | .1. | + // 168 | ------1- 0 -1- -- 0--- ---- 11-------------- | 1.. | + // 169 | ------1- 0 -01 -- 0--- ---- 1--------------- | .1. | + // 170 | ------1- 0 -10 -- 11-- ---- ---------------- | ..1 | + // *=========================================================================* + // + +// Table LRU_UPDATE_DATA Signal Assignments for Product Terms +//assign_start + assign LRU_UPDATE_DATA_PT[1] = (({tlb_tag4_type_sig[6], tlb_tag4_type_sig[7], tlb_tag4_wayhit_q[3], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[2], lru_tag4_dataout_q[8], lru_tag4_dataout_q[9], lru_tag4_dataout_q[10], lru_tag4_dataout_q[11]}) === 10'b0011111110); + assign LRU_UPDATE_DATA_PT[2] = (({tlb_tag4_type_sig[4], tlb_tag4_wayhit_q[0], tlb_tag4_wayhit_q[3], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[2], lru_tag4_dataout_q[9], lru_tag4_dataout_q[10], lru_tag4_dataout_q[11]}) === 9'b101111110); + assign LRU_UPDATE_DATA_PT[3] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_is_sig[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[2], lru_tag4_dataout_q[4], lru_tag4_dataout_q[5], lru_tag4_dataout_q[10], lru_tag4_dataout_q[11]}) === 9'b111110010); + assign LRU_UPDATE_DATA_PT[4] = (({tlb_tag4_type_sig[7], tlb_tag4_is_sig[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[2], lru_tag4_dataout_q[4], lru_tag4_dataout_q[5], lru_tag4_dataout_q[10], lru_tag4_dataout_q[11]}) === 8'b11110010); + assign LRU_UPDATE_DATA_PT[5] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_is_sig[0], lru_tag4_dataout_q[0], lru_tag4_dataout_q[2], lru_tag4_dataout_q[4], lru_tag4_dataout_q[5], lru_tag4_dataout_q[10], lru_tag4_dataout_q[11]}) === 9'b111110110); + assign LRU_UPDATE_DATA_PT[6] = (({tlb_tag4_type_sig[7], tlb_tag4_is_sig[0], lru_tag4_dataout_q[0], lru_tag4_dataout_q[2], lru_tag4_dataout_q[4], lru_tag4_dataout_q[5], lru_tag4_dataout_q[10], lru_tag4_dataout_q[11]}) === 8'b11110110); + assign LRU_UPDATE_DATA_PT[7] = (({tlb_tag4_type_sig[6], tlb_tag4_type_sig[7], tlb_tag4_wayhit_q[0], tlb_tag4_wayhit_q[1], tlb_tag4_wayhit_q[3], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[2], lru_tag4_dataout_q[10], lru_tag4_dataout_q[11]}) === 10'b0000111110); + assign LRU_UPDATE_DATA_PT[8] = (({tlb_tag4_type_sig[4], tlb_tag4_type_sig[6], tlb_tag4_type_sig[7], tlb_tag4_wayhit_q[1], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[2], lru_tag4_dataout_q[10], lru_tag4_dataout_q[11]}) === 9'b000111110); + assign LRU_UPDATE_DATA_PT[9] = (({tlb_tag4_type_sig[4], tlb_tag4_type_sig[6], tlb_tag4_type_sig[7], tlb_tag4_wayhit_q[0], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[2], lru_tag4_dataout_q[10], lru_tag4_dataout_q[11]}) === 9'b000111110); + assign LRU_UPDATE_DATA_PT[10] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_esel_sig[1], tlb_tag4_esel_sig[2], tlb_tag4_is_sig[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[2], lru_tag4_dataout_q[10], lru_tag4_dataout_q[11]}) === 9'b100011110); + assign LRU_UPDATE_DATA_PT[11] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_esel_sig[1], tlb_tag4_esel_sig[2], tlb_tag4_is_sig[0], lru_tag4_dataout_q[0], lru_tag4_dataout_q[2], lru_tag4_dataout_q[10], lru_tag4_dataout_q[11]}) === 9'b100111110); + assign LRU_UPDATE_DATA_PT[12] = (({tlb_tag4_hes_sig, lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[4], lru_tag4_dataout_q[6], lru_tag4_dataout_q[8], lru_tag4_dataout_q[9], lru_tag4_dataout_q[11]}) === 8'b11110110); + assign LRU_UPDATE_DATA_PT[13] = (({tlb_tag4_type_sig[4], tlb_tag4_type_sig[6], tlb_tag4_type_sig[7], tlb_tag4_wayhit_q[2], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[8], lru_tag4_dataout_q[9], lru_tag4_dataout_q[11]}) === 9'b000111110); + assign LRU_UPDATE_DATA_PT[14] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_esel_sig[1], tlb_tag4_esel_sig[2], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[8], lru_tag4_dataout_q[9], lru_tag4_dataout_q[11]}) === 9'b101011110); + assign LRU_UPDATE_DATA_PT[15] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_is_sig[0], lru_tag4_dataout_q[4], lru_tag4_dataout_q[6], lru_tag4_dataout_q[11]}) === 6'b111100); + assign LRU_UPDATE_DATA_PT[16] = (({tlb_tag4_type_sig[7], tlb_tag4_is_sig[0], lru_tag4_dataout_q[4], lru_tag4_dataout_q[6], lru_tag4_dataout_q[11]}) === 5'b11100); + assign LRU_UPDATE_DATA_PT[17] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, lru_tag4_dataout_q[2], lru_tag4_dataout_q[4], lru_tag4_dataout_q[6], lru_tag4_dataout_q[11]}) === 6'b111010); + assign LRU_UPDATE_DATA_PT[18] = (({tlb_tag4_type_sig[7], lru_tag4_dataout_q[2], lru_tag4_dataout_q[4], lru_tag4_dataout_q[6], lru_tag4_dataout_q[11]}) === 5'b11010); + assign LRU_UPDATE_DATA_PT[19] = (({tlb_tag4_type_sig[4], tlb_tag4_type_sig[6], tlb_tag4_type_sig[7], tlb_tag4_wayhit_q[3], lru_tag4_dataout_q[2], lru_tag4_dataout_q[6], lru_tag4_dataout_q[11]}) === 7'b0000110); + assign LRU_UPDATE_DATA_PT[20] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_esel_sig[1], lru_tag4_dataout_q[2], lru_tag4_dataout_q[6], lru_tag4_dataout_q[11]}) === 6'b100110); + assign LRU_UPDATE_DATA_PT[21] = (({tlb_tag4_type_sig[4], tlb_tag4_wayhit_q[0], tlb_tag4_wayhit_q[1], tlb_tag4_wayhit_q[2], tlb_tag4_wayhit_q[3], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[2], lru_tag4_dataout_q[11]}) === 9'b100011110); + assign LRU_UPDATE_DATA_PT[22] = (({tlb_tag4_type_sig[4], tlb_tag4_type_sig[6], tlb_tag4_type_sig[7], tlb_tag4_wayhit_q[2], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[2], lru_tag4_dataout_q[11]}) === 8'b00011110); + assign LRU_UPDATE_DATA_PT[23] = (({tlb_tag4_type_sig[4], tlb_tag4_wayhit_q[0], tlb_tag4_wayhit_q[1], tlb_tag4_wayhit_q[3], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[11]}) === 7'b1001110); + assign LRU_UPDATE_DATA_PT[24] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_esel_sig[1], tlb_tag4_esel_sig[2], tlb_tag4_is_sig[0], lru_tag4_dataout_q[11]}) === 6'b101010); + assign LRU_UPDATE_DATA_PT[25] = (({tlb_tag4_hes_sig, lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[4], lru_tag4_dataout_q[6], lru_tag4_dataout_q[8], lru_tag4_dataout_q[9], lru_tag4_dataout_q[10]}) === 8'b11111110); + assign LRU_UPDATE_DATA_PT[26] = (({tlb_tag4_type_sig[4], tlb_tag4_type_sig[6], tlb_tag4_type_sig[7], tlb_tag4_wayhit_q[3], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[8], lru_tag4_dataout_q[9], lru_tag4_dataout_q[10]}) === 9'b000111110); + assign LRU_UPDATE_DATA_PT[27] = (({tlb_tag4_type_sig[6], tlb_tag4_type_sig[7], tlb_tag4_wayhit_q[2], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[8], lru_tag4_dataout_q[9], lru_tag4_dataout_q[10]}) === 8'b00111110); + assign LRU_UPDATE_DATA_PT[28] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_esel_sig[1], tlb_tag4_esel_sig[2], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[8], lru_tag4_dataout_q[9], lru_tag4_dataout_q[10]}) === 9'b101111110); + assign LRU_UPDATE_DATA_PT[29] = (({tlb_tag4_type_sig[4], tlb_tag4_wayhit_q[0], tlb_tag4_wayhit_q[2], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[9], lru_tag4_dataout_q[10]}) === 7'b1011110); + assign LRU_UPDATE_DATA_PT[30] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_is_sig[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[4], lru_tag4_dataout_q[5], lru_tag4_dataout_q[10]}) === 7'b1111000); + assign LRU_UPDATE_DATA_PT[31] = (({tlb_tag4_type_sig[7], tlb_tag4_is_sig[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[4], lru_tag4_dataout_q[5], lru_tag4_dataout_q[10]}) === 6'b111000); + assign LRU_UPDATE_DATA_PT[32] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_is_sig[0], lru_tag4_dataout_q[0], lru_tag4_dataout_q[4], lru_tag4_dataout_q[5], lru_tag4_dataout_q[10]}) === 7'b1111010); + assign LRU_UPDATE_DATA_PT[33] = (({tlb_tag4_type_sig[7], tlb_tag4_is_sig[0], lru_tag4_dataout_q[0], lru_tag4_dataout_q[4], lru_tag4_dataout_q[5], lru_tag4_dataout_q[10]}) === 6'b111010); + assign LRU_UPDATE_DATA_PT[34] = (({tlb_tag4_type_sig[4], tlb_tag4_wayhit_q[0], tlb_tag4_wayhit_q[1], tlb_tag4_wayhit_q[2], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[10]}) === 7'b1001110); + assign LRU_UPDATE_DATA_PT[35] = (({tlb_tag4_type_sig[4], tlb_tag4_type_sig[6], tlb_tag4_type_sig[7], tlb_tag4_wayhit_q[1], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[10]}) === 7'b0001110); + assign LRU_UPDATE_DATA_PT[36] = (({tlb_tag4_type_sig[4], tlb_tag4_type_sig[6], tlb_tag4_type_sig[7], tlb_tag4_wayhit_q[0], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[10]}) === 7'b0001110); + assign LRU_UPDATE_DATA_PT[37] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_esel_sig[1], tlb_tag4_esel_sig[2], tlb_tag4_is_sig[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[10]}) === 7'b1000110); + assign LRU_UPDATE_DATA_PT[38] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_esel_sig[1], tlb_tag4_esel_sig[2], tlb_tag4_is_sig[0], lru_tag4_dataout_q[0], lru_tag4_dataout_q[10]}) === 7'b1001110); + assign LRU_UPDATE_DATA_PT[39] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, lru_tag4_dataout_q[2], lru_tag4_dataout_q[4], lru_tag4_dataout_q[6], lru_tag4_dataout_q[10]}) === 6'b111011); + assign LRU_UPDATE_DATA_PT[40] = (({tlb_tag4_type_sig[7], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[4], lru_tag4_dataout_q[6], lru_tag4_dataout_q[10]}) === 6'b110111); + assign LRU_UPDATE_DATA_PT[41] = (({tlb_tag4_hes_sig, tlb_tag4_is_sig[0], tlb_tag4_is_sig[1], lru_tag4_dataout_q[1], lru_tag4_dataout_q[4], lru_tag4_dataout_q[6], lru_tag4_dataout_q[10]}) === 7'b1100111); + assign LRU_UPDATE_DATA_PT[42] = (({tlb_tag4_hes_sig, tlb_tag4_is_sig[0], tlb_tag4_is_sig[1], lru_tag4_dataout_q[0], lru_tag4_dataout_q[4], lru_tag4_dataout_q[6], lru_tag4_dataout_q[10]}) === 7'b1100111); + assign LRU_UPDATE_DATA_PT[43] = (({tlb_tag4_type_sig[6], lru_tag4_dataout_q[0], lru_tag4_dataout_q[4], lru_tag4_dataout_q[6], lru_tag4_dataout_q[10]}) === 5'b00111); + assign LRU_UPDATE_DATA_PT[44] = (({tlb_tag4_type_sig[6], tlb_tag4_wayhit_q[3], lru_tag4_dataout_q[2], lru_tag4_dataout_q[6], lru_tag4_dataout_q[10]}) === 5'b00111); + assign LRU_UPDATE_DATA_PT[45] = (({tlb_tag4_type_sig[6], tlb_tag4_wayhit_q[2], lru_tag4_dataout_q[2], lru_tag4_dataout_q[6], lru_tag4_dataout_q[10]}) === 5'b01111); + assign LRU_UPDATE_DATA_PT[46] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_is_sig[1], lru_tag4_dataout_q[2], lru_tag4_dataout_q[6], lru_tag4_dataout_q[10]}) === 6'b110111); + assign LRU_UPDATE_DATA_PT[47] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_esel_sig[1], lru_tag4_dataout_q[2], lru_tag4_dataout_q[6], lru_tag4_dataout_q[10]}) === 6'b100111); + assign LRU_UPDATE_DATA_PT[48] = (({tlb_tag4_type_sig[7], lru_tag4_dataout_q[2], lru_tag4_dataout_q[6], lru_tag4_dataout_q[10]}) === 4'b1111); + assign LRU_UPDATE_DATA_PT[49] = (({tlb_tag4_type_sig[4], tlb_tag4_wayhit_q[0], tlb_tag4_wayhit_q[1], tlb_tag4_wayhit_q[2], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[2], lru_tag4_dataout_q[3], lru_tag4_dataout_q[10]}) === 9'b100111101); + assign LRU_UPDATE_DATA_PT[50] = (({tlb_tag4_type_sig[4], tlb_tag4_type_sig[6], tlb_tag4_type_sig[7], tlb_tag4_wayhit_q[2], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[2], lru_tag4_dataout_q[10]}) === 8'b00011111); + assign LRU_UPDATE_DATA_PT[51] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_esel_sig[1], tlb_tag4_esel_sig[2], tlb_tag4_is_sig[1], lru_tag4_dataout_q[2], lru_tag4_dataout_q[10]}) === 7'b1011011); + assign LRU_UPDATE_DATA_PT[52] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_esel_sig[1], tlb_tag4_esel_sig[2], tlb_tag4_is_sig[0], tlb_tag4_is_sig[1], lru_tag4_dataout_q[1], lru_tag4_dataout_q[10]}) === 8'b10111001); + assign LRU_UPDATE_DATA_PT[53] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_esel_sig[1], tlb_tag4_esel_sig[2], tlb_tag4_is_sig[0], tlb_tag4_is_sig[1], lru_tag4_dataout_q[0], lru_tag4_dataout_q[10]}) === 8'b10111001); + assign LRU_UPDATE_DATA_PT[54] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_is_sig[0], lru_tag4_dataout_q[0], lru_tag4_dataout_q[3], lru_tag4_dataout_q[4], lru_tag4_dataout_q[6], lru_tag4_dataout_q[8], lru_tag4_dataout_q[9]}) === 9'b111111010); + assign LRU_UPDATE_DATA_PT[55] = (({tlb_tag4_type_sig[7], tlb_tag4_is_sig[0], lru_tag4_dataout_q[0], lru_tag4_dataout_q[3], lru_tag4_dataout_q[6], lru_tag4_dataout_q[8], lru_tag4_dataout_q[9]}) === 7'b1111010); + assign LRU_UPDATE_DATA_PT[56] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_is_sig[0], lru_tag4_dataout_q[0], lru_tag4_dataout_q[2], lru_tag4_dataout_q[4], lru_tag4_dataout_q[6], lru_tag4_dataout_q[8], lru_tag4_dataout_q[9]}) === 9'b111111110); + assign LRU_UPDATE_DATA_PT[57] = (({tlb_tag4_type_sig[7], tlb_tag4_is_sig[0], lru_tag4_dataout_q[0], lru_tag4_dataout_q[2], lru_tag4_dataout_q[6], lru_tag4_dataout_q[8], lru_tag4_dataout_q[9]}) === 7'b1111110); + assign LRU_UPDATE_DATA_PT[58] = (({tlb_tag4_type_sig[4], tlb_tag4_type_sig[6], tlb_tag4_type_sig[7], tlb_tag4_wayhit_q[3], lru_tag4_dataout_q[0], lru_tag4_dataout_q[2], lru_tag4_dataout_q[3], lru_tag4_dataout_q[8], lru_tag4_dataout_q[9]}) === 9'b000111110); + assign LRU_UPDATE_DATA_PT[59] = (({tlb_tag4_type_sig[4], tlb_tag4_type_sig[6], tlb_tag4_type_sig[7], tlb_tag4_wayhit_q[2], lru_tag4_dataout_q[0], lru_tag4_dataout_q[2], lru_tag4_dataout_q[3], lru_tag4_dataout_q[8], lru_tag4_dataout_q[9]}) === 9'b000111110); + assign LRU_UPDATE_DATA_PT[60] = (({tlb_tag4_type_sig[6], tlb_tag4_type_sig[7], tlb_tag4_wayhit_q[1], lru_tag4_dataout_q[0], lru_tag4_dataout_q[2], lru_tag4_dataout_q[3], lru_tag4_dataout_q[8], lru_tag4_dataout_q[9]}) === 8'b00111110); + assign LRU_UPDATE_DATA_PT[61] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_esel_sig[2], tlb_tag4_is_sig[0], lru_tag4_dataout_q[0], lru_tag4_dataout_q[3], lru_tag4_dataout_q[8], lru_tag4_dataout_q[9]}) === 8'b10011110); + assign LRU_UPDATE_DATA_PT[62] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_esel_sig[1], tlb_tag4_esel_sig[2], tlb_tag4_is_sig[0], lru_tag4_dataout_q[0], lru_tag4_dataout_q[2], lru_tag4_dataout_q[8], lru_tag4_dataout_q[9]}) === 9'b101111110); + assign LRU_UPDATE_DATA_PT[63] = (({tlb_tag4_type_sig[6], tlb_tag4_type_sig[7], tlb_tag4_wayhit_q[0], tlb_tag4_wayhit_q[1], lru_tag4_dataout_q[2], lru_tag4_dataout_q[6], lru_tag4_dataout_q[9]}) === 7'b0011110); + assign LRU_UPDATE_DATA_PT[64] = (({tlb_tag4_type_sig[4], tlb_tag4_wayhit_q[0], tlb_tag4_wayhit_q[1], lru_tag4_dataout_q[6], lru_tag4_dataout_q[9]}) === 5'b10110); + assign LRU_UPDATE_DATA_PT[65] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_is_sig[0], lru_tag4_dataout_q[4], lru_tag4_dataout_q[5], lru_tag4_dataout_q[9]}) === 6'b111000); + assign LRU_UPDATE_DATA_PT[66] = (({tlb_tag4_type_sig[7], tlb_tag4_is_sig[0], lru_tag4_dataout_q[4], lru_tag4_dataout_q[5], lru_tag4_dataout_q[9]}) === 5'b11000); + assign LRU_UPDATE_DATA_PT[67] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, lru_tag4_dataout_q[0], lru_tag4_dataout_q[4], lru_tag4_dataout_q[5], lru_tag4_dataout_q[9]}) === 6'b111110); + assign LRU_UPDATE_DATA_PT[68] = (({tlb_tag4_type_sig[7], lru_tag4_dataout_q[0], lru_tag4_dataout_q[4], lru_tag4_dataout_q[5], lru_tag4_dataout_q[9]}) === 5'b11110); + assign LRU_UPDATE_DATA_PT[69] = (({tlb_tag4_type_sig[4], tlb_tag4_type_sig[6], tlb_tag4_type_sig[7], tlb_tag4_wayhit_q[1], lru_tag4_dataout_q[0], lru_tag4_dataout_q[5], lru_tag4_dataout_q[9]}) === 7'b0000110); + assign LRU_UPDATE_DATA_PT[70] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_esel_sig[1], lru_tag4_dataout_q[0], lru_tag4_dataout_q[5], lru_tag4_dataout_q[9]}) === 6'b101110); + assign LRU_UPDATE_DATA_PT[71] = (({tlb_tag4_type_sig[4], tlb_tag4_type_sig[6], tlb_tag4_type_sig[7], tlb_tag4_wayhit_q[0], lru_tag4_dataout_q[0], lru_tag4_dataout_q[2], lru_tag4_dataout_q[3], lru_tag4_dataout_q[9]}) === 8'b00011110); + assign LRU_UPDATE_DATA_PT[72] = (({tlb_tag4_type_sig[4], tlb_tag4_wayhit_q[0], tlb_tag4_wayhit_q[1], lru_tag4_dataout_q[0], lru_tag4_dataout_q[9]}) === 5'b10110); + assign LRU_UPDATE_DATA_PT[73] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_esel_sig[1], tlb_tag4_esel_sig[2], tlb_tag4_is_sig[0], lru_tag4_dataout_q[9]}) === 6'b100010); + assign LRU_UPDATE_DATA_PT[74] = (({tlb_tag4_type_sig[6], tlb_tag4_wayhit_q[1], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[4], lru_tag4_dataout_q[8], lru_tag4_dataout_q[9]}) === 7'b0111111); + assign LRU_UPDATE_DATA_PT[75] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_is_sig[1], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[4], lru_tag4_dataout_q[8], lru_tag4_dataout_q[9]}) === 8'b11011111); + assign LRU_UPDATE_DATA_PT[76] = (({tlb_tag4_type_sig[7], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[4], lru_tag4_dataout_q[8], lru_tag4_dataout_q[9]}) === 6'b111111); + assign LRU_UPDATE_DATA_PT[77] = (({tlb_tag4_type_sig[4], tlb_tag4_type_sig[6], tlb_tag4_type_sig[7], tlb_tag4_wayhit_q[0], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[2], lru_tag4_dataout_q[3], lru_tag4_dataout_q[8], lru_tag4_dataout_q[9]}) === 10'b0001111111); + assign LRU_UPDATE_DATA_PT[78] = (({tlb_tag4_type_sig[4], tlb_tag4_type_sig[6], tlb_tag4_type_sig[7], tlb_tag4_wayhit_q[1], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[8], lru_tag4_dataout_q[9]}) === 8'b00011111); + assign LRU_UPDATE_DATA_PT[79] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_esel_sig[1], tlb_tag4_is_sig[1], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[8], lru_tag4_dataout_q[9]}) === 8'b10101111); + assign LRU_UPDATE_DATA_PT[80] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_is_sig[0], tlb_tag4_is_sig[1], lru_tag4_dataout_q[1], lru_tag4_dataout_q[4], lru_tag4_dataout_q[5], lru_tag4_dataout_q[9]}) === 8'b11111001); + assign LRU_UPDATE_DATA_PT[81] = (({tlb_tag4_type_sig[4], tlb_tag4_wayhit_q[0], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[4], lru_tag4_dataout_q[9]}) === 6'b101111); + assign LRU_UPDATE_DATA_PT[82] = (({tlb_tag4_type_sig[4], tlb_tag4_wayhit_q[0], tlb_tag4_wayhit_q[1], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[2], lru_tag4_dataout_q[3], lru_tag4_dataout_q[9]}) === 8'b10111101); + assign LRU_UPDATE_DATA_PT[83] = (({tlb_tag4_type_sig[4], tlb_tag4_wayhit_q[0], tlb_tag4_wayhit_q[1], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[2], lru_tag4_dataout_q[9]}) === 7'b1011101); + assign LRU_UPDATE_DATA_PT[84] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_esel_sig[1], tlb_tag4_esel_sig[2], tlb_tag4_is_sig[0], tlb_tag4_is_sig[1], lru_tag4_dataout_q[1], lru_tag4_dataout_q[9]}) === 8'b10001111); + assign LRU_UPDATE_DATA_PT[85] = (({tlb_tag4_type_sig[4], tlb_tag4_wayhit_q[0], lru_tag4_dataout_q[6], lru_tag4_dataout_q[8]}) === 4'b1110); + assign LRU_UPDATE_DATA_PT[86] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_is_sig[0], tlb_tag4_is_sig[1], lru_tag4_dataout_q[0], lru_tag4_dataout_q[4], lru_tag4_dataout_q[5], lru_tag4_dataout_q[8]}) === 8'b11111011); + assign LRU_UPDATE_DATA_PT[87] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, lru_tag4_dataout_q[0], lru_tag4_dataout_q[4], lru_tag4_dataout_q[5], lru_tag4_dataout_q[8]}) === 6'b111111); + assign LRU_UPDATE_DATA_PT[88] = (({tlb_tag4_type_sig[6], tlb_tag4_wayhit_q[1], lru_tag4_dataout_q[0], lru_tag4_dataout_q[5], lru_tag4_dataout_q[8]}) === 5'b00111); + assign LRU_UPDATE_DATA_PT[89] = (({tlb_tag4_type_sig[6], tlb_tag4_wayhit_q[0], lru_tag4_dataout_q[0], lru_tag4_dataout_q[5], lru_tag4_dataout_q[8]}) === 5'b01111); + assign LRU_UPDATE_DATA_PT[90] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_is_sig[1], lru_tag4_dataout_q[0], lru_tag4_dataout_q[5], lru_tag4_dataout_q[8]}) === 6'b110111); + assign LRU_UPDATE_DATA_PT[91] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_esel_sig[1], lru_tag4_dataout_q[0], lru_tag4_dataout_q[5], lru_tag4_dataout_q[8]}) === 6'b101111); + assign LRU_UPDATE_DATA_PT[92] = (({tlb_tag4_type_sig[7], lru_tag4_dataout_q[0], lru_tag4_dataout_q[5], lru_tag4_dataout_q[8]}) === 4'b1111); + assign LRU_UPDATE_DATA_PT[93] = (({tlb_tag4_type_sig[4], tlb_tag4_wayhit_q[1], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[4], lru_tag4_dataout_q[8]}) === 6'b101111); + assign LRU_UPDATE_DATA_PT[94] = (({tlb_tag4_type_sig[4], tlb_tag4_wayhit_q[0], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[2], lru_tag4_dataout_q[3], lru_tag4_dataout_q[8]}) === 7'b1111101); + assign LRU_UPDATE_DATA_PT[95] = (({tlb_tag4_type_sig[4], tlb_tag4_wayhit_q[0], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[2], lru_tag4_dataout_q[8]}) === 6'b111101); + assign LRU_UPDATE_DATA_PT[96] = (({tlb_tag4_type_sig[4], tlb_tag4_wayhit_q[0], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[8]}) === 5'b11101); + assign LRU_UPDATE_DATA_PT[97] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_esel_sig[1], tlb_tag4_esel_sig[2], tlb_tag4_is_sig[1], lru_tag4_dataout_q[0], lru_tag4_dataout_q[8]}) === 7'b1001011); + assign LRU_UPDATE_DATA_PT[98] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_esel_sig[1], tlb_tag4_esel_sig[2], tlb_tag4_is_sig[0], tlb_tag4_is_sig[1], lru_tag4_dataout_q[0], lru_tag4_dataout_q[8]}) === 8'b10011111); + assign LRU_UPDATE_DATA_PT[99] = (({tlb_tag4_type_sig[4], tlb_tag4_hes_sig, lru_tag4_dataout_q[0], lru_tag4_dataout_q[3], lru_tag4_dataout_q[4], lru_tag4_dataout_q[5], lru_tag4_dataout_q[6]}) === 7'b0110110); + assign LRU_UPDATE_DATA_PT[100] = (({tlb_tag4_type_sig[7], lru_tag4_dataout_q[0], lru_tag4_dataout_q[3], lru_tag4_dataout_q[4], lru_tag4_dataout_q[5], lru_tag4_dataout_q[6]}) === 6'b110110); + assign LRU_UPDATE_DATA_PT[101] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_is_sig[0], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[3], lru_tag4_dataout_q[4], lru_tag4_dataout_q[6]}) === 8'b11111010); + assign LRU_UPDATE_DATA_PT[102] = (({tlb_tag4_type_sig[7], tlb_tag4_is_sig[0], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[3], lru_tag4_dataout_q[4], lru_tag4_dataout_q[6]}) === 7'b1111010); + assign LRU_UPDATE_DATA_PT[103] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_is_sig[0], tlb_tag4_is_sig[1], lru_tag4_dataout_q[4], lru_tag4_dataout_q[6]}) === 6'b111110); + assign LRU_UPDATE_DATA_PT[104] = (({tlb_tag4_hes_sig, lru_tag4_dataout_q[1], lru_tag4_dataout_q[4], lru_tag4_dataout_q[5], lru_tag4_dataout_q[6]}) === 5'b10001); + assign LRU_UPDATE_DATA_PT[105] = (({tlb_tag4_type_sig[7], lru_tag4_dataout_q[1], lru_tag4_dataout_q[4], lru_tag4_dataout_q[5], lru_tag4_dataout_q[6]}) === 5'b10001); + assign LRU_UPDATE_DATA_PT[106] = (({tlb_tag4_hes_sig, lru_tag4_dataout_q[0], lru_tag4_dataout_q[4], lru_tag4_dataout_q[5], lru_tag4_dataout_q[6]}) === 5'b10011); + assign LRU_UPDATE_DATA_PT[107] = (({tlb_tag4_type_sig[6], lru_tag4_dataout_q[0], lru_tag4_dataout_q[4], lru_tag4_dataout_q[5], lru_tag4_dataout_q[6]}) === 5'b00011); + assign LRU_UPDATE_DATA_PT[108] = (({tlb_tag4_type_sig[4], tlb_tag4_hes_sig, lru_tag4_dataout_q[0], lru_tag4_dataout_q[2], lru_tag4_dataout_q[4], lru_tag4_dataout_q[5], lru_tag4_dataout_q[6]}) === 7'b0110111); + assign LRU_UPDATE_DATA_PT[109] = (({tlb_tag4_type_sig[7], lru_tag4_dataout_q[0], lru_tag4_dataout_q[2], lru_tag4_dataout_q[4], lru_tag4_dataout_q[5], lru_tag4_dataout_q[6]}) === 6'b110111); + assign LRU_UPDATE_DATA_PT[110] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_is_sig[0], lru_tag4_dataout_q[4], lru_tag4_dataout_q[6]}) === 5'b11001); + assign LRU_UPDATE_DATA_PT[111] = (({tlb_tag4_type_sig[4], tlb_tag4_hes_sig, tlb_tag4_is_sig[0], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[2], lru_tag4_dataout_q[6]}) === 7'b0111101); + assign LRU_UPDATE_DATA_PT[112] = (({tlb_tag4_type_sig[7], tlb_tag4_is_sig[0], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[2], lru_tag4_dataout_q[6]}) === 6'b111101); + assign LRU_UPDATE_DATA_PT[113] = (({tlb_tag4_type_sig[6], tlb_tag4_type_sig[7], tlb_tag4_wayhit_q[0], tlb_tag4_wayhit_q[1], tlb_tag4_wayhit_q[2], tlb_tag4_wayhit_q[3], lru_tag4_dataout_q[2], lru_tag4_dataout_q[6]}) === 8'b00000011); + assign LRU_UPDATE_DATA_PT[114] = (({tlb_tag4_type_sig[4], tlb_tag4_wayhit_q[2], lru_tag4_dataout_q[2], lru_tag4_dataout_q[6]}) === 4'b1011); + assign LRU_UPDATE_DATA_PT[115] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_is_sig[0], lru_tag4_dataout_q[2], lru_tag4_dataout_q[6]}) === 5'b11011); + assign LRU_UPDATE_DATA_PT[116] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_esel_sig[1], tlb_tag4_esel_sig[2], lru_tag4_dataout_q[1], lru_tag4_dataout_q[6]}) === 6'b100001); + assign LRU_UPDATE_DATA_PT[117] = (({tlb_tag4_type_sig[6], tlb_tag4_type_sig[7], lru_tag4_dataout_q[1], lru_tag4_dataout_q[6]}) === 4'b0001); + assign LRU_UPDATE_DATA_PT[118] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_esel_sig[1], tlb_tag4_esel_sig[2], lru_tag4_dataout_q[0], lru_tag4_dataout_q[6]}) === 6'b100101); + assign LRU_UPDATE_DATA_PT[119] = (({tlb_tag4_type_sig[6], tlb_tag4_type_sig[7], lru_tag4_dataout_q[0], lru_tag4_dataout_q[6]}) === 4'b0001); + assign LRU_UPDATE_DATA_PT[120] = (({tlb_tag4_type_sig[4], tlb_tag4_wayhit_q[0], tlb_tag4_wayhit_q[1], tlb_tag4_wayhit_q[2], tlb_tag4_wayhit_q[3], lru_tag4_dataout_q[6]}) === 6'b100001); + assign LRU_UPDATE_DATA_PT[121] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_esel_sig[1], tlb_tag4_is_sig[0], lru_tag4_dataout_q[6]}) === 5'b10001); + assign LRU_UPDATE_DATA_PT[122] = (({tlb_tag4_type_sig[7], tlb_tag4_is_sig[0], lru_tag4_dataout_q[6]}) === 3'b101); + assign LRU_UPDATE_DATA_PT[123] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_is_sig[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[2], lru_tag4_dataout_q[3], lru_tag4_dataout_q[4], lru_tag4_dataout_q[5]}) === 8'b11111000); + assign LRU_UPDATE_DATA_PT[124] = (({tlb_tag4_type_sig[7], tlb_tag4_is_sig[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[2], lru_tag4_dataout_q[3], lru_tag4_dataout_q[4], lru_tag4_dataout_q[5]}) === 7'b1111000); + assign LRU_UPDATE_DATA_PT[125] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_is_sig[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[2], lru_tag4_dataout_q[4], lru_tag4_dataout_q[5]}) === 7'b1111000); + assign LRU_UPDATE_DATA_PT[126] = (({tlb_tag4_type_sig[7], tlb_tag4_is_sig[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[2], lru_tag4_dataout_q[4], lru_tag4_dataout_q[5]}) === 6'b111000); + assign LRU_UPDATE_DATA_PT[127] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_is_sig[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[4], lru_tag4_dataout_q[5]}) === 6'b111000); + assign LRU_UPDATE_DATA_PT[128] = (({tlb_tag4_type_sig[7], tlb_tag4_is_sig[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[4], lru_tag4_dataout_q[5]}) === 5'b11000); + assign LRU_UPDATE_DATA_PT[129] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_is_sig[0], lru_tag4_dataout_q[0], lru_tag4_dataout_q[2], lru_tag4_dataout_q[3], lru_tag4_dataout_q[4], lru_tag4_dataout_q[5]}) === 8'b11111001); + assign LRU_UPDATE_DATA_PT[130] = (({tlb_tag4_type_sig[7], tlb_tag4_is_sig[0], lru_tag4_dataout_q[0], lru_tag4_dataout_q[2], lru_tag4_dataout_q[3], lru_tag4_dataout_q[4], lru_tag4_dataout_q[5]}) === 7'b1111001); + assign LRU_UPDATE_DATA_PT[131] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_is_sig[0], lru_tag4_dataout_q[0], lru_tag4_dataout_q[2], lru_tag4_dataout_q[4], lru_tag4_dataout_q[5]}) === 7'b1111001); + assign LRU_UPDATE_DATA_PT[132] = (({tlb_tag4_type_sig[7], tlb_tag4_is_sig[0], lru_tag4_dataout_q[0], lru_tag4_dataout_q[2], lru_tag4_dataout_q[4], lru_tag4_dataout_q[5]}) === 6'b111001); + assign LRU_UPDATE_DATA_PT[133] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_esel_sig[1], tlb_tag4_esel_sig[2], lru_tag4_dataout_q[0], lru_tag4_dataout_q[3], lru_tag4_dataout_q[5]}) === 7'b1010101); + assign LRU_UPDATE_DATA_PT[134] = (({tlb_tag4_type_sig[4], tlb_tag4_type_sig[6], tlb_tag4_type_sig[7], lru_tag4_dataout_q[0], lru_tag4_dataout_q[3], lru_tag4_dataout_q[5]}) === 6'b000101); + assign LRU_UPDATE_DATA_PT[135] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_esel_sig[1], tlb_tag4_esel_sig[2], lru_tag4_dataout_q[0], lru_tag4_dataout_q[2], lru_tag4_dataout_q[5]}) === 7'b1011101); + assign LRU_UPDATE_DATA_PT[136] = (({tlb_tag4_type_sig[4], tlb_tag4_type_sig[6], tlb_tag4_type_sig[7], lru_tag4_dataout_q[0], lru_tag4_dataout_q[2], lru_tag4_dataout_q[5]}) === 6'b000101); + assign LRU_UPDATE_DATA_PT[137] = (({tlb_tag4_type_sig[6], tlb_tag4_type_sig[7], tlb_tag4_wayhit_q[0], tlb_tag4_wayhit_q[1], tlb_tag4_wayhit_q[2], tlb_tag4_wayhit_q[3], lru_tag4_dataout_q[0], lru_tag4_dataout_q[5]}) === 8'b00000011); + assign LRU_UPDATE_DATA_PT[138] = (({tlb_tag4_type_sig[4], tlb_tag4_wayhit_q[0], lru_tag4_dataout_q[0], lru_tag4_dataout_q[5]}) === 4'b1011); + assign LRU_UPDATE_DATA_PT[139] = (({tlb_tag4_type_sig[6], tlb_tag4_esel_sig[1], tlb_tag4_is_sig[0], lru_tag4_dataout_q[0], lru_tag4_dataout_q[5]}) === 5'b11011); + assign LRU_UPDATE_DATA_PT[140] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_is_sig[0], lru_tag4_dataout_q[0], lru_tag4_dataout_q[5]}) === 5'b11011); + assign LRU_UPDATE_DATA_PT[141] = (({tlb_tag4_type_sig[4], tlb_tag4_wayhit_q[0], tlb_tag4_wayhit_q[1], tlb_tag4_wayhit_q[2], tlb_tag4_wayhit_q[3], lru_tag4_dataout_q[5]}) === 6'b100001); + assign LRU_UPDATE_DATA_PT[142] = (({tlb_tag4_type_sig[7], tlb_tag4_is_sig[0], lru_tag4_dataout_q[5]}) === 3'b101); + assign LRU_UPDATE_DATA_PT[143] = (({tlb_tag4_type_sig[7], tlb_tag4_is_sig[0], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[4]}) === 5'b11101); + assign LRU_UPDATE_DATA_PT[144] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[4]}) === 5'b11101); + assign LRU_UPDATE_DATA_PT[145] = (({tlb_tag4_type_sig[6], tlb_tag4_type_sig[7], tlb_tag4_wayhit_q[0], tlb_tag4_wayhit_q[1], tlb_tag4_wayhit_q[2], tlb_tag4_wayhit_q[3], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[4]}) === 9'b000000111); + assign LRU_UPDATE_DATA_PT[146] = (({tlb_tag4_type_sig[4], tlb_tag4_wayhit_q[0], tlb_tag4_wayhit_q[1], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[4]}) === 6'b100111); + assign LRU_UPDATE_DATA_PT[147] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_is_sig[0], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[4]}) === 6'b110111); + assign LRU_UPDATE_DATA_PT[148] = (({tlb_tag4_type_sig[4], tlb_tag4_wayhit_q[0], tlb_tag4_wayhit_q[1], tlb_tag4_wayhit_q[2], tlb_tag4_wayhit_q[3], lru_tag4_dataout_q[4]}) === 6'b100001); + assign LRU_UPDATE_DATA_PT[149] = (({tlb_tag4_type_sig[7], tlb_tag4_is_sig[0], lru_tag4_dataout_q[4]}) === 3'b101); + assign LRU_UPDATE_DATA_PT[150] = (({tlb_tag4_type_sig[4], tlb_tag4_wayhit_q[0], tlb_tag4_wayhit_q[1], tlb_tag4_wayhit_q[2], tlb_tag4_wayhit_q[3], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[2], lru_tag4_dataout_q[3]}) === 9'b100011110); + assign LRU_UPDATE_DATA_PT[151] = (({tlb_tag4_type_sig[4], tlb_tag4_type_sig[6], tlb_tag4_type_sig[7], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[2], lru_tag4_dataout_q[3]}) === 7'b0001110); + assign LRU_UPDATE_DATA_PT[152] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_esel_sig[1], tlb_tag4_esel_sig[2], tlb_tag4_is_sig[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[2], lru_tag4_dataout_q[3]}) === 8'b10001110); + assign LRU_UPDATE_DATA_PT[153] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_esel_sig[1], tlb_tag4_esel_sig[2], tlb_tag4_is_sig[0], lru_tag4_dataout_q[0], lru_tag4_dataout_q[2], lru_tag4_dataout_q[3]}) === 8'b10011110); + assign LRU_UPDATE_DATA_PT[154] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_esel_sig[1], tlb_tag4_esel_sig[2], tlb_tag4_is_sig[0], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[3]}) === 8'b10101110); + assign LRU_UPDATE_DATA_PT[155] = (({tlb_tag4_type_sig[4], tlb_tag4_wayhit_q[0], tlb_tag4_wayhit_q[1], tlb_tag4_wayhit_q[3], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[2]}) === 7'b1001110); + assign LRU_UPDATE_DATA_PT[156] = (({tlb_tag4_type_sig[4], tlb_tag4_wayhit_q[0], tlb_tag4_wayhit_q[1], tlb_tag4_wayhit_q[2], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[2]}) === 7'b1001110); + assign LRU_UPDATE_DATA_PT[157] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_esel_sig[1], tlb_tag4_esel_sig[2], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[2]}) === 7'b1011110); + assign LRU_UPDATE_DATA_PT[158] = (({tlb_tag4_type_sig[4], tlb_tag4_type_sig[6], tlb_tag4_type_sig[7], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[2]}) === 6'b000110); + assign LRU_UPDATE_DATA_PT[159] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_esel_sig[1], tlb_tag4_esel_sig[2], tlb_tag4_is_sig[0], lru_tag4_dataout_q[1], lru_tag4_dataout_q[2]}) === 7'b1000110); + assign LRU_UPDATE_DATA_PT[160] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_esel_sig[1], tlb_tag4_esel_sig[2], tlb_tag4_is_sig[0], lru_tag4_dataout_q[0], lru_tag4_dataout_q[2]}) === 7'b1001110); + assign LRU_UPDATE_DATA_PT[161] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_esel_sig[1], tlb_tag4_esel_sig[2], tlb_tag4_is_sig[0], lru_tag4_dataout_q[2]}) === 6'b101101); + assign LRU_UPDATE_DATA_PT[162] = (({tlb_tag4_type_sig[4], tlb_tag4_wayhit_q[0], tlb_tag4_wayhit_q[3], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1]}) === 5'b10110); + assign LRU_UPDATE_DATA_PT[163] = (({tlb_tag4_type_sig[4], tlb_tag4_wayhit_q[0], tlb_tag4_wayhit_q[2], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1]}) === 5'b10110); + assign LRU_UPDATE_DATA_PT[164] = (({tlb_tag4_type_sig[4], tlb_tag4_wayhit_q[0], tlb_tag4_wayhit_q[1], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1]}) === 5'b10110); + assign LRU_UPDATE_DATA_PT[165] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_esel_sig[1], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1]}) === 5'b10110); + assign LRU_UPDATE_DATA_PT[166] = (({tlb_tag4_type_sig[4], tlb_tag4_type_sig[6], tlb_tag4_type_sig[7], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1]}) === 5'b00010); + assign LRU_UPDATE_DATA_PT[167] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_esel_sig[1], tlb_tag4_esel_sig[2], tlb_tag4_is_sig[0], lru_tag4_dataout_q[1]}) === 6'b100010); + assign LRU_UPDATE_DATA_PT[168] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_esel_sig[1], tlb_tag4_is_sig[0], lru_tag4_dataout_q[0], lru_tag4_dataout_q[1]}) === 6'b101011); + assign LRU_UPDATE_DATA_PT[169] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_esel_sig[1], tlb_tag4_esel_sig[2], tlb_tag4_is_sig[0], lru_tag4_dataout_q[0]}) === 6'b100101); + assign LRU_UPDATE_DATA_PT[170] = (({tlb_tag4_type_sig[6], tlb_tag4_hes_sig, tlb_tag4_esel_sig[1], tlb_tag4_esel_sig[2], tlb_tag4_is_sig[0], tlb_tag4_is_sig[1]}) === 6'b101011); + + // Table LRU_UPDATE_DATA Signal Assignments for Outputs + assign lru_update_data[0] = (LRU_UPDATE_DATA_PT[1] | LRU_UPDATE_DATA_PT[2] | + LRU_UPDATE_DATA_PT[3] | LRU_UPDATE_DATA_PT[4] | + LRU_UPDATE_DATA_PT[5] | LRU_UPDATE_DATA_PT[6] | + LRU_UPDATE_DATA_PT[8] | LRU_UPDATE_DATA_PT[9] | + LRU_UPDATE_DATA_PT[10] | LRU_UPDATE_DATA_PT[11] | + LRU_UPDATE_DATA_PT[12] | LRU_UPDATE_DATA_PT[13] | + LRU_UPDATE_DATA_PT[14] | LRU_UPDATE_DATA_PT[23] | + LRU_UPDATE_DATA_PT[25] | LRU_UPDATE_DATA_PT[26] | + LRU_UPDATE_DATA_PT[27] | LRU_UPDATE_DATA_PT[28] | + LRU_UPDATE_DATA_PT[29] | LRU_UPDATE_DATA_PT[30] | + LRU_UPDATE_DATA_PT[31] | LRU_UPDATE_DATA_PT[32] | + LRU_UPDATE_DATA_PT[33] | LRU_UPDATE_DATA_PT[34] | + LRU_UPDATE_DATA_PT[35] | LRU_UPDATE_DATA_PT[36] | + LRU_UPDATE_DATA_PT[37] | LRU_UPDATE_DATA_PT[38] | + LRU_UPDATE_DATA_PT[49] | LRU_UPDATE_DATA_PT[74] | + LRU_UPDATE_DATA_PT[75] | LRU_UPDATE_DATA_PT[76] | + LRU_UPDATE_DATA_PT[77] | LRU_UPDATE_DATA_PT[78] | + LRU_UPDATE_DATA_PT[79] | LRU_UPDATE_DATA_PT[80] | + LRU_UPDATE_DATA_PT[81] | LRU_UPDATE_DATA_PT[82] | + LRU_UPDATE_DATA_PT[83] | LRU_UPDATE_DATA_PT[84] | + LRU_UPDATE_DATA_PT[86] | LRU_UPDATE_DATA_PT[93] | + LRU_UPDATE_DATA_PT[94] | LRU_UPDATE_DATA_PT[95] | + LRU_UPDATE_DATA_PT[98] | LRU_UPDATE_DATA_PT[101] | + LRU_UPDATE_DATA_PT[102] | LRU_UPDATE_DATA_PT[111] | + LRU_UPDATE_DATA_PT[112] | LRU_UPDATE_DATA_PT[123] | + LRU_UPDATE_DATA_PT[124] | LRU_UPDATE_DATA_PT[125] | + LRU_UPDATE_DATA_PT[126] | LRU_UPDATE_DATA_PT[129] | + LRU_UPDATE_DATA_PT[130] | LRU_UPDATE_DATA_PT[131] | + LRU_UPDATE_DATA_PT[132] | LRU_UPDATE_DATA_PT[145] | + LRU_UPDATE_DATA_PT[146] | LRU_UPDATE_DATA_PT[147] | + LRU_UPDATE_DATA_PT[148] | LRU_UPDATE_DATA_PT[149] | + LRU_UPDATE_DATA_PT[150] | LRU_UPDATE_DATA_PT[151] | + LRU_UPDATE_DATA_PT[152] | LRU_UPDATE_DATA_PT[153] | + LRU_UPDATE_DATA_PT[154] | LRU_UPDATE_DATA_PT[155] | + LRU_UPDATE_DATA_PT[156] | LRU_UPDATE_DATA_PT[157] | + LRU_UPDATE_DATA_PT[158] | LRU_UPDATE_DATA_PT[159] | + LRU_UPDATE_DATA_PT[160] | LRU_UPDATE_DATA_PT[168]); + + assign lru_update_data[1] = (LRU_UPDATE_DATA_PT[54] | LRU_UPDATE_DATA_PT[55] | + LRU_UPDATE_DATA_PT[56] | LRU_UPDATE_DATA_PT[57] | + LRU_UPDATE_DATA_PT[58] | LRU_UPDATE_DATA_PT[59] | + LRU_UPDATE_DATA_PT[60] | LRU_UPDATE_DATA_PT[61] | + LRU_UPDATE_DATA_PT[62] | LRU_UPDATE_DATA_PT[65] | + LRU_UPDATE_DATA_PT[66] | LRU_UPDATE_DATA_PT[67] | + LRU_UPDATE_DATA_PT[68] | LRU_UPDATE_DATA_PT[69] | + LRU_UPDATE_DATA_PT[70] | LRU_UPDATE_DATA_PT[71] | + LRU_UPDATE_DATA_PT[72] | LRU_UPDATE_DATA_PT[73] | + LRU_UPDATE_DATA_PT[77] | LRU_UPDATE_DATA_PT[80] | + LRU_UPDATE_DATA_PT[84] | LRU_UPDATE_DATA_PT[87] | + LRU_UPDATE_DATA_PT[88] | LRU_UPDATE_DATA_PT[89] | + LRU_UPDATE_DATA_PT[90] | LRU_UPDATE_DATA_PT[91] | + LRU_UPDATE_DATA_PT[92] | LRU_UPDATE_DATA_PT[96] | + LRU_UPDATE_DATA_PT[97] | LRU_UPDATE_DATA_PT[99] | + LRU_UPDATE_DATA_PT[100] | LRU_UPDATE_DATA_PT[108] | + LRU_UPDATE_DATA_PT[109] | LRU_UPDATE_DATA_PT[127] | + LRU_UPDATE_DATA_PT[128] | LRU_UPDATE_DATA_PT[133] | + LRU_UPDATE_DATA_PT[134] | LRU_UPDATE_DATA_PT[135] | + LRU_UPDATE_DATA_PT[136] | LRU_UPDATE_DATA_PT[137] | + LRU_UPDATE_DATA_PT[138] | LRU_UPDATE_DATA_PT[139] | + LRU_UPDATE_DATA_PT[140] | LRU_UPDATE_DATA_PT[141] | + LRU_UPDATE_DATA_PT[142] | LRU_UPDATE_DATA_PT[143] | + LRU_UPDATE_DATA_PT[144] | LRU_UPDATE_DATA_PT[162] | + LRU_UPDATE_DATA_PT[163] | LRU_UPDATE_DATA_PT[164] | + LRU_UPDATE_DATA_PT[165] | LRU_UPDATE_DATA_PT[166] | + LRU_UPDATE_DATA_PT[167] | LRU_UPDATE_DATA_PT[169]); + + assign lru_update_data[2] = (LRU_UPDATE_DATA_PT[1] | LRU_UPDATE_DATA_PT[2] | + LRU_UPDATE_DATA_PT[3] | LRU_UPDATE_DATA_PT[4] | + LRU_UPDATE_DATA_PT[5] | LRU_UPDATE_DATA_PT[6] | + LRU_UPDATE_DATA_PT[7] | LRU_UPDATE_DATA_PT[8] | + LRU_UPDATE_DATA_PT[9] | LRU_UPDATE_DATA_PT[10] | + LRU_UPDATE_DATA_PT[11] | LRU_UPDATE_DATA_PT[15] | + LRU_UPDATE_DATA_PT[16] | LRU_UPDATE_DATA_PT[17] | + LRU_UPDATE_DATA_PT[18] | LRU_UPDATE_DATA_PT[19] | + LRU_UPDATE_DATA_PT[20] | LRU_UPDATE_DATA_PT[21] | + LRU_UPDATE_DATA_PT[22] | LRU_UPDATE_DATA_PT[24] | + LRU_UPDATE_DATA_PT[39] | LRU_UPDATE_DATA_PT[40] | + LRU_UPDATE_DATA_PT[41] | LRU_UPDATE_DATA_PT[42] | + LRU_UPDATE_DATA_PT[43] | LRU_UPDATE_DATA_PT[44] | + LRU_UPDATE_DATA_PT[45] | LRU_UPDATE_DATA_PT[46] | + LRU_UPDATE_DATA_PT[47] | LRU_UPDATE_DATA_PT[48] | + LRU_UPDATE_DATA_PT[49] | LRU_UPDATE_DATA_PT[50] | + LRU_UPDATE_DATA_PT[51] | LRU_UPDATE_DATA_PT[52] | + LRU_UPDATE_DATA_PT[53] | LRU_UPDATE_DATA_PT[63] | + LRU_UPDATE_DATA_PT[64] | LRU_UPDATE_DATA_PT[82] | + LRU_UPDATE_DATA_PT[85] | LRU_UPDATE_DATA_PT[94] | + LRU_UPDATE_DATA_PT[101] | LRU_UPDATE_DATA_PT[102] | + LRU_UPDATE_DATA_PT[103] | LRU_UPDATE_DATA_PT[104] | + LRU_UPDATE_DATA_PT[105] | LRU_UPDATE_DATA_PT[106] | + LRU_UPDATE_DATA_PT[107] | LRU_UPDATE_DATA_PT[110] | + LRU_UPDATE_DATA_PT[113] | LRU_UPDATE_DATA_PT[114] | + LRU_UPDATE_DATA_PT[115] | LRU_UPDATE_DATA_PT[116] | + LRU_UPDATE_DATA_PT[117] | LRU_UPDATE_DATA_PT[118] | + LRU_UPDATE_DATA_PT[119] | LRU_UPDATE_DATA_PT[120] | + LRU_UPDATE_DATA_PT[121] | LRU_UPDATE_DATA_PT[122] | + LRU_UPDATE_DATA_PT[123] | LRU_UPDATE_DATA_PT[124] | + LRU_UPDATE_DATA_PT[129] | LRU_UPDATE_DATA_PT[130] | + LRU_UPDATE_DATA_PT[150] | LRU_UPDATE_DATA_PT[151] | + LRU_UPDATE_DATA_PT[152] | LRU_UPDATE_DATA_PT[153] | + LRU_UPDATE_DATA_PT[154] | LRU_UPDATE_DATA_PT[161] | + LRU_UPDATE_DATA_PT[170]); +//assign_end + + + // lru data format + // 0:3 - valid(0:3) + // 4:6 - LRU + // 7 - parity + // 8:11 - iprot(0:3) + // 12:14 - reserved + // 15 - parity + // tlb_low_data + // 0:51 - EPN + // 52:55 - SIZE (4b) + // 56:59 - ThdID + // 60:61 - Class + // 62 - ExtClass + // 63 - TID_NZ + // 64:65 - reserved (2b) + // 66:73 - 8b for LPID + // 74:83 - parity 10bits + // mmucr3 + // 49 X-bit + // 50:51 R,C + // 52 ECL + // 53 TID_NZ + // 54:55 Class + // 56:57 WLC + // 58:59 ResvAttr + // 60:63 ThdID + + // unused `tagpos_is def is mas1_v, mas1_iprot for tlbwe, and is (pte.valid & 0) for ptereloads + + generate + if (`RS_DATA_WIDTH == 64) + begin : gen64_tlb_datain + assign tlb_datain_lo_tlbwe_0_nopar[0:`TLB_WORD_WIDTH - 10 - 1] = + //EPN(0:51) size thdid + { (tlb_tag4_q[`tagpos_epn:`tagpos_epn + 31] & {32{tlb_tag4_q[`tagpos_cm]}}), tlb_tag4_q[`tagpos_epn + 32:`tagpos_epn + `EPN_WIDTH - 1], tlb_tag4_q[`tagpos_size:`tagpos_size + 3], mmucr3_0[60:63], + //class ECL TID_NZ + mmucr3_0[54:55], (mmucr3_0[52] & tlb_tag4_q[`tagpos_is + 1]), |(tlb_tag4_q[`tagpos_pid:`tagpos_pid + `PID_WIDTH - 1]), + //rsvd lpid + 2'b00, tlb_tag4_q[`tagpos_lpid:`tagpos_lpid + `LPID_WIDTH - 1] }; + +`ifdef MM_THREADS2 + assign tlb_datain_lo_tlbwe_1_nopar[0:`TLB_WORD_WIDTH - 10 - 1] = + //EPN(0:51) size thdid + { (tlb_tag4_q[`tagpos_epn:`tagpos_epn + 31] & {32{tlb_tag4_q[`tagpos_cm]}}), tlb_tag4_q[`tagpos_epn + 32:`tagpos_epn + `EPN_WIDTH - 1], tlb_tag4_q[`tagpos_size:`tagpos_size + 3], mmucr3_1[60:63], + //class ECL TID_NZ + mmucr3_1[54:55], (mmucr3_1[52] & tlb_tag4_q[`tagpos_is + 1]), |(tlb_tag4_q[`tagpos_pid:`tagpos_pid + `PID_WIDTH - 1]), + //rsvd lpid + 2'b00, tlb_tag4_q[`tagpos_lpid:`tagpos_lpid + `LPID_WIDTH - 1] }; +`endif + assign tlb_datain_lo_ptereload_nopar[0:`TLB_WORD_WIDTH - 10 - 1] = {tlb_tag4_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 1], 1'b0, ptereload_req_pte_lat[`ptepos_size:`ptepos_size + 2], tlb_tag4_q[`tagpos_atsel], tlb_tag4_q[`tagpos_esel:`tagpos_esel + 2], tlb_tag4_q[`tagpos_class], (tlb_tag4_q[`tagpos_class] & tlb_tag4_q[`tagpos_class + 1]), 1'b0, |(tlb_tag4_q[`tagpos_pid:`tagpos_pid + `PID_WIDTH - 1]), 2'b00, tlb_tag4_q[`tagpos_lpid:`tagpos_lpid + `LPID_WIDTH - 1]}; + + assign tlb_dataina_d[0:`TLB_WORD_WIDTH - 1] = (tlb_tag4_q[`tagpos_thdid + 0] == 1'b1 & tlb_tag4_q[`tagpos_type_tlbwe] == 1'b1) ? {tlb_datain_lo_tlbwe_0_nopar, tlb_datain_lo_tlbwe_0_par} : +`ifdef MM_THREADS2 + (tlb_tag4_q[`tagpos_thdid + 1] == 1'b1 & tlb_tag4_q[`tagpos_type_tlbwe] == 1'b1) ? {tlb_datain_lo_tlbwe_1_nopar, tlb_datain_lo_tlbwe_1_par} : +`endif + (tlb_tag4_ptereload_sig == 1'b1) ? {tlb_datain_lo_ptereload_nopar, tlb_datain_lo_ptereload_par} : + (tlb_tag4_parerr_zeroize == 1'b1) ? {`TLB_WORD_WIDTH{1'b0}} : + tlb_dataina_q[0:`TLB_WORD_WIDTH - 1]; + + assign tlb_datainb_d[0:`TLB_WORD_WIDTH - 1] = (tlb_tag4_q[`tagpos_thdid + 0] == 1'b1 & tlb_tag4_q[`tagpos_type_tlbwe] == 1'b1) ? {tlb_datain_lo_tlbwe_0_nopar, tlb_datain_lo_tlbwe_0_par} : +`ifdef MM_THREADS2 + (tlb_tag4_q[`tagpos_thdid + 1] == 1'b1 & tlb_tag4_q[`tagpos_type_tlbwe] == 1'b1) ? {tlb_datain_lo_tlbwe_1_nopar, tlb_datain_lo_tlbwe_1_par} : +`endif + (tlb_tag4_ptereload_sig == 1'b1) ? {tlb_datain_lo_ptereload_nopar, tlb_datain_lo_ptereload_par} : + (tlb_tag4_parerr_zeroize == 1'b1) ? {`TLB_WORD_WIDTH{1'b0}} : + tlb_datainb_q[0:`TLB_WORD_WIDTH - 1]; + end + endgenerate + + generate + if (`RS_DATA_WIDTH == 32) + begin : gen32_tlb_datain + assign tlb_datain_lo_tlbwe_0_nopar[0:`TLB_WORD_WIDTH - 10 - 1] = + //EPN(0:51) size thdid + { {32{1'b0}}, tlb_tag4_q[`tagpos_epn + 32:`tagpos_epn + `EPN_WIDTH - 1], tlb_tag4_q[`tagpos_size:`tagpos_size + 3], mmucr3_0[60:63], + //class ECL TID_NZ + mmucr3_0[54:55], (mmucr3_0[52] & tlb_tag4_q[`tagpos_is + 1]), |(tlb_tag4_q[`tagpos_pid:`tagpos_pid + `PID_WIDTH - 1]), + //rsvd lpid + 2'b00, tlb_tag4_q[`tagpos_lpid:`tagpos_lpid + `LPID_WIDTH - 1] }; + +`ifdef MM_THREADS2 + assign tlb_datain_lo_tlbwe_1_nopar[0:`TLB_WORD_WIDTH - 10 - 1] = + //EPN(0:51) size thdid + { {32{1'b0}}, tlb_tag4_q[`tagpos_epn + 32:`tagpos_epn + `EPN_WIDTH - 1], tlb_tag4_q[`tagpos_size:`tagpos_size + 3], mmucr3_1[60:63], + //class ECL TID_NZ + mmucr3_1[54:55], (mmucr3_1[52] & tlb_tag4_q[`tagpos_is + 1]), |(tlb_tag4_q[`tagpos_pid:`tagpos_pid + `PID_WIDTH - 1]), + //rsvd lpid + 2'b00, tlb_tag4_q[`tagpos_lpid:`tagpos_lpid + `LPID_WIDTH - 1] }; +`endif + + assign tlb_datain_lo_ptereload_nopar[0:`TLB_WORD_WIDTH - 10 - 1] = {1'b0, tlb_tag4_q[`tagpos_epn + 32:`tagpos_epn + `EPN_WIDTH + 32 - 1], 1'b0, ptereload_req_pte_lat[`ptepos_size:`ptepos_size + 2], 4'b1111, tlb_tag4_q[`tagpos_class:`tagpos_class + 1], 1'b0, |(tlb_tag4_q[`tagpos_pid:`tagpos_pid + `PID_WIDTH - 1]), 2'b00, tlb_tag4_q[`tagpos_lpid:`tagpos_lpid + `LPID_WIDTH - 1]}; + + assign tlb_dataina_d[0:`TLB_WORD_WIDTH - 1] = (tlb_tag4_q[`tagpos_thdid + 0] == 1'b1 & tlb_tag4_q[`tagpos_type_tlbwe] == 1'b1) ? {tlb_datain_lo_tlbwe_0_nopar, tlb_datain_lo_tlbwe_0_par} : +`ifdef MM_THREADS2 + (tlb_tag4_q[`tagpos_thdid + 1] == 1'b1 & tlb_tag4_q[`tagpos_type_tlbwe] == 1'b1) ? {tlb_datain_lo_tlbwe_1_nopar, tlb_datain_lo_tlbwe_1_par} : +`endif + (tlb_tag4_ptereload_sig == 1'b1) ? {tlb_datain_lo_ptereload_nopar, tlb_datain_lo_ptereload_par} : + (tlb_tag4_parerr_zeroize == 1'b1) ? {`TLB_WORD_WIDTH{1'b0}} : + tlb_dataina_q[0:`TLB_WORD_WIDTH - 1]; + + assign tlb_datainb_d[0:`TLB_WORD_WIDTH - 1] = (tlb_tag4_q[`tagpos_thdid + 0] == 1'b1 & tlb_tag4_q[`tagpos_type_tlbwe] == 1'b1) ? {tlb_datain_lo_tlbwe_0_nopar, tlb_datain_lo_tlbwe_0_par} : +`ifdef MM_THREADS2 + (tlb_tag4_q[`tagpos_thdid + 1] == 1'b1 & tlb_tag4_q[`tagpos_type_tlbwe] == 1'b1) ? {tlb_datain_lo_tlbwe_1_nopar, tlb_datain_lo_tlbwe_1_par} : +`endif + (tlb_tag4_ptereload_sig == 1'b1) ? {tlb_datain_lo_ptereload_nopar, tlb_datain_lo_ptereload_par} : + (tlb_tag4_parerr_zeroize == 1'b1) ? {`TLB_WORD_WIDTH{1'b0}} : + tlb_datainb_q[0:`TLB_WORD_WIDTH - 1]; + end + endgenerate + + // tlb_high_data + // 84 - 0 - X-bit + // 85:87 - 1:3 - reserved (3b) + // 88:117 - 4:33 - RPN (30b) + // 118:119 - 34:35 - R,C + // 120:121 - 36:37 - WLC (2b) + // 122 - 38 - ResvAttr + // 123 - 39 - VF + // 124 - 40 - IND + // 125:128 - 41:44 - U0-U3 + // 129:133 - 45:49 - WIMGE + // 134:135 - 50:51 - UX,SX + // 136:137 - 52:53 - UW,SW + // 138:139 - 54:55 - UR,SR + // 140 - 56 - GS + // 141 - 57 - TS + // 142:143 - 58:59 - reserved (2b) + // 144:149 - 60:65 - 6b TID msbs + // 150:157 - 66:73 - 8b TID lsbs + // 158:167 - 74:83 - parity 10bits + // mmucr3 + // 49 X-bit + // 50:51 R,C + // 52 ECL + // 53 TID_NZ + // 54:55 Class + // 56:57 WLC + // 58:59 ResvAttr + // 60:63 ThdID + assign ptereload_req_derived_usxwr[0] = ptereload_req_pte_lat[`ptepos_usxwr + 0] & ptereload_req_pte_lat[`ptepos_r]; + assign ptereload_req_derived_usxwr[1] = ptereload_req_pte_lat[`ptepos_usxwr + 1] & ptereload_req_pte_lat[`ptepos_r]; + assign ptereload_req_derived_usxwr[2] = ptereload_req_pte_lat[`ptepos_usxwr + 2] & ptereload_req_pte_lat[`ptepos_r] & ptereload_req_pte_lat[`ptepos_c]; + assign ptereload_req_derived_usxwr[3] = ptereload_req_pte_lat[`ptepos_usxwr + 3] & ptereload_req_pte_lat[`ptepos_r] & ptereload_req_pte_lat[`ptepos_c]; + assign ptereload_req_derived_usxwr[4] = ptereload_req_pte_lat[`ptepos_usxwr + 4] & ptereload_req_pte_lat[`ptepos_r]; + assign ptereload_req_derived_usxwr[5] = ptereload_req_pte_lat[`ptepos_usxwr + 5] & ptereload_req_pte_lat[`ptepos_r]; + + generate + if (`REAL_ADDR_WIDTH < 42) + begin : gen32_lrat_tag3_lpn + assign lrat_tag3_lpn_sig[22:63 - `REAL_ADDR_WIDTH] = {2{1'b0}}; + assign lrat_tag3_lpn_sig[64 - `REAL_ADDR_WIDTH:51] = lrat_tag3_lpn[64 - `REAL_ADDR_WIDTH:51]; + end + endgenerate + + generate + if (`REAL_ADDR_WIDTH > 41) + begin : gen64_lrat_tag3_lpn + assign lrat_tag3_lpn_sig[64 - `REAL_ADDR_WIDTH:51] = lrat_tag3_lpn[64 - `REAL_ADDR_WIDTH:51]; + end + endgenerate + + generate + if (`REAL_ADDR_WIDTH < 42) + begin : gen32_lrat_tag3_rpn + assign lrat_tag3_rpn_sig[22:63 - `REAL_ADDR_WIDTH] = {2{1'b0}}; + assign lrat_tag3_rpn_sig[64 - `REAL_ADDR_WIDTH:51] = lrat_tag3_rpn[64 - `REAL_ADDR_WIDTH:51]; + end + endgenerate + + generate + if (`REAL_ADDR_WIDTH > 41) + begin : gen64_lrat_tag3_rpn + assign lrat_tag3_rpn_sig[64 - `REAL_ADDR_WIDTH:51] = lrat_tag3_rpn[64 - `REAL_ADDR_WIDTH:51]; + end + endgenerate + + generate + if (`REAL_ADDR_WIDTH < 42) + begin : gen32_lrat_tag4_lpn + assign lrat_tag4_lpn_sig[22:63 - `REAL_ADDR_WIDTH] = {2{1'b0}}; + assign lrat_tag4_lpn_sig[64 - `REAL_ADDR_WIDTH:51] = lrat_tag4_lpn[64 - `REAL_ADDR_WIDTH:51]; + end + endgenerate + + generate + if (`REAL_ADDR_WIDTH > 41) + begin : gen64_lrat_tag4_lpn + assign lrat_tag4_lpn_sig[64 - `REAL_ADDR_WIDTH:51] = lrat_tag4_lpn[64 - `REAL_ADDR_WIDTH:51]; + end + endgenerate + + generate + if (`REAL_ADDR_WIDTH < 42) + begin : gen32_lrat_tag4_rpn + assign lrat_tag4_rpn_sig[22:63 - `REAL_ADDR_WIDTH] = {2{1'b0}}; + assign lrat_tag4_rpn_sig[64 - `REAL_ADDR_WIDTH:51] = lrat_tag4_rpn[64 - `REAL_ADDR_WIDTH:51]; + end + endgenerate + + generate + if (`REAL_ADDR_WIDTH > 41) + begin : gen64_lrat_tag4_rpn + assign lrat_tag4_rpn_sig[64 - `REAL_ADDR_WIDTH:51] = lrat_tag4_rpn[64 - `REAL_ADDR_WIDTH:51]; + end + endgenerate + + assign tlb_datain_hi_hv_tlbwe_0_nopar = + // X Rsv RPN (30b) R,C + {mmucr3_0[49], (tstmode4k_0 & {3{~tlb_tag4_q[`tagpos_ind]}}), mas7_0_rpnu, mas3_0_rpnl[32:51], mmucr3_0[50:51], + // WLC ResvAttr VF IND U0:3 WIMGE + mmucr3_0[56:58], mas8_0_vf, (tlb_tag4_q[`tagpos_ind] & tlb0cfg_ind), mas3_0_ubits, mas2_0_wimge, + // UX,SX,UW,SW + mas3_0_usxwr[0:3], + // UR zeroize UR/SPSIZE4 bit for ind=1 entries + (mas3_0_usxwr[4] & ((~tlb_tag4_q[`tagpos_ind]) | (~tlb0cfg_ind))), + // SR (ind=0), or PA52 (ind=1) + ((mas3_0_usxwr[5] & ((~tlb_tag4_q[`tagpos_ind]) | (~tlb0cfg_ind))) | (mas3_0_rpnl[52] & tlb_tag4_q[`tagpos_ind] & tlb0cfg_ind)), + // TGS TS rsvd TID + tlb_tag4_q[`tagpos_pt], tlb_tag4_q[`tagpos_recform], 2'b00, tlb_tag4_q[`tagpos_pid:`tagpos_pid + `PID_WIDTH - 1]}; + + assign tlb_datain_hi_gs_tlbwe_0_nopar = + // X Rsv RPN (30b) R,C + {mmucr3_0[49], (tstmode4k_0 & {3{~tlb_tag4_q[`tagpos_ind]}}), lrat_tag4_rpn_sig[22:51], mmucr3_0[50:51], + // WLC ResvAttr VF IND U0:3 WIMGE + mmucr3_0[56:58], mas8_0_vf, (tlb_tag4_q[`tagpos_ind] & tlb0cfg_ind), mas3_0_ubits, mas2_0_wimge, + // UX,SX,UW,SW + mas3_0_usxwr[0:3], + // UR zeroize UR/SPSIZE4 bit for ind=1 entries + (mas3_0_usxwr[4] & ((~tlb_tag4_q[`tagpos_ind]) | (~tlb0cfg_ind))), + // SR (ind=0), or PA52 (ind=1) + ((mas3_0_usxwr[5] & ((~tlb_tag4_q[`tagpos_ind]) | (~tlb0cfg_ind))) | (mas3_0_rpnl[52] & tlb_tag4_q[`tagpos_ind] & tlb0cfg_ind)), + // TGS TS rsvd TID + tlb_tag4_q[`tagpos_pt], tlb_tag4_q[`tagpos_recform], 2'b00, tlb_tag4_q[`tagpos_pid:`tagpos_pid + `PID_WIDTH - 1]}; +`ifdef MM_THREADS2 + assign tlb_datain_hi_hv_tlbwe_1_nopar = + // X Rsv RPN (30b) R,C + {mmucr3_1[49], (tstmode4k_1 & {3{~tlb_tag4_q[`tagpos_ind]}}), mas7_1_rpnu, mas3_1_rpnl[32:51], mmucr3_1[50:51], + // WLC ResvAttr VF IND U0:3 WIMGE + mmucr3_1[56:58], mas8_1_vf, (tlb_tag4_q[`tagpos_ind] & tlb0cfg_ind), mas3_1_ubits, mas2_1_wimge, + // UX,SX,UW,SW + mas3_1_usxwr[0:3], + // UR zeroize UR/SPSIZE4 bit for ind=1 entries + (mas3_1_usxwr[4] & ((~tlb_tag4_q[`tagpos_ind]) | (~tlb0cfg_ind))), + // SR (ind=0), or PA52 (ind=1) + ((mas3_1_usxwr[5] & ((~tlb_tag4_q[`tagpos_ind]) | (~tlb0cfg_ind))) | (mas3_1_rpnl[52] & tlb_tag4_q[`tagpos_ind] & tlb0cfg_ind)), + // TGS TS rsvd TID + tlb_tag4_q[`tagpos_pt], tlb_tag4_q[`tagpos_recform], 2'b00, tlb_tag4_q[`tagpos_pid:`tagpos_pid + `PID_WIDTH - 1]}; + + assign tlb_datain_hi_gs_tlbwe_1_nopar = + // X Rsv RPN (30b) R,C + {mmucr3_1[49], (tstmode4k_1 & {3{~tlb_tag4_q[`tagpos_ind]}}), lrat_tag4_rpn_sig[22:51], mmucr3_1[50:51], + // WLC ResvAttr VF IND U0:3 WIMGE + mmucr3_1[56:58], mas8_1_vf, (tlb_tag4_q[`tagpos_ind] & tlb0cfg_ind), mas3_1_ubits, mas2_1_wimge, + // UX,SX,UW,SW + mas3_1_usxwr[0:3], + // UR zeroize UR/SPSIZE4 bit for ind=1 entries + (mas3_1_usxwr[4] & ((~tlb_tag4_q[`tagpos_ind]) | (~tlb0cfg_ind))), + // SR (ind=0), or PA52 (ind=1) + ((mas3_1_usxwr[5] & ((~tlb_tag4_q[`tagpos_ind]) | (~tlb0cfg_ind))) | (mas3_1_rpnl[52] & tlb_tag4_q[`tagpos_ind] & tlb0cfg_ind)), + // TGS TS rsvd TID + tlb_tag4_q[`tagpos_pt], tlb_tag4_q[`tagpos_recform], 2'b00, tlb_tag4_q[`tagpos_pid:`tagpos_pid + `PID_WIDTH - 1]}; +`endif + + assign tlb_datain_hi_hv_ptereload_nopar = {1'b0, 3'b000, ptereload_req_pte_lat[`ptepos_rpn + 10:`ptepos_rpn + 39], ptereload_req_pte_lat[`ptepos_r], ptereload_req_pte_lat[`ptepos_c], 2'b00, 1'b0, 1'b0, 1'b0, ptereload_req_pte_lat[`ptepos_ubits:`ptepos_ubits + 3], ptereload_req_pte_lat[`ptepos_wimge:`ptepos_wimge + 4], ptereload_req_derived_usxwr[0:5], tlb_tag4_q[`tagpos_gs], tlb_tag4_q[`tagpos_as], 2'b00, tlb_tag4_q[`tagpos_pid:`tagpos_pid + `PID_WIDTH - 1]}; + assign tlb_datain_hi_gs_ptereload_nopar = {1'b0, 3'b000, lrat_tag4_rpn_sig[22:51], ptereload_req_pte_lat[`ptepos_r], ptereload_req_pte_lat[`ptepos_c], 2'b00, 1'b0, 1'b0, 1'b0, ptereload_req_pte_lat[`ptepos_ubits:`ptepos_ubits + 3], ptereload_req_pte_lat[`ptepos_wimge:`ptepos_wimge + 4], ptereload_req_derived_usxwr[0:5], tlb_tag4_q[`tagpos_gs], tlb_tag4_q[`tagpos_as], 2'b00, tlb_tag4_q[`tagpos_pid:`tagpos_pid + `PID_WIDTH - 1]}; + // unused `tagpos_is def is mas1_v, mas1_iprot for tlbwe, and is (pte.valid & 0) for ptereloads + assign tlb_dataina_d[`TLB_WORD_WIDTH:2 * `TLB_WORD_WIDTH - 1] = (tlb_tag4_q[`tagpos_thdid + 0] == 1'b1 & tlb_tag4_q[`tagpos_type_tlbwe] == 1'b1 & (tlb_tag4_q[`tagpos_gs] == 1'b0 | tlb_tag4_q[`tagpos_is] == 1'b0)) ? {tlb_datain_hi_hv_tlbwe_0_nopar, tlb_datain_hi_hv_tlbwe_0_par} : + (tlb_tag4_q[`tagpos_thdid + 0] == 1'b1 & tlb_tag4_q[`tagpos_type_tlbwe] == 1'b1 & tlb_tag4_q[`tagpos_gs] == 1'b1 & tlb_tag4_q[`tagpos_is] == 1'b1) ? {tlb_datain_hi_gs_tlbwe_0_nopar, tlb_datain_hi_gs_tlbwe_0_par} : +`ifdef MM_THREADS2 + (tlb_tag4_q[`tagpos_thdid + 1] == 1'b1 & tlb_tag4_q[`tagpos_type_tlbwe] == 1'b1 & (tlb_tag4_q[`tagpos_gs] == 1'b0 | tlb_tag4_q[`tagpos_is] == 1'b0)) ? {tlb_datain_hi_hv_tlbwe_1_nopar, tlb_datain_hi_hv_tlbwe_1_par} : + (tlb_tag4_q[`tagpos_thdid + 1] == 1'b1 & tlb_tag4_q[`tagpos_type_tlbwe] == 1'b1 & tlb_tag4_q[`tagpos_gs] == 1'b1 & tlb_tag4_q[`tagpos_is] == 1'b1) ? {tlb_datain_hi_gs_tlbwe_1_nopar, tlb_datain_hi_gs_tlbwe_1_par} : +`endif + (tlb_tag4_ptereload_sig == 1'b1 & tlb_tag4_q[`tagpos_gs] == 1'b0) ? {tlb_datain_hi_hv_ptereload_nopar, tlb_datain_hi_hv_ptereload_par} : + (tlb_tag4_ptereload_sig == 1'b1 & tlb_tag4_q[`tagpos_gs] == 1'b1) ? {tlb_datain_hi_gs_ptereload_nopar, tlb_datain_hi_gs_ptereload_par} : + (tlb_tag4_parerr_zeroize == 1'b1) ? {`TLB_WORD_WIDTH{1'b0}} : + tlb_dataina_q[`TLB_WORD_WIDTH:2 * `TLB_WORD_WIDTH - 1]; + + assign tlb_datainb_d[`TLB_WORD_WIDTH:2 * `TLB_WORD_WIDTH - 1] = (tlb_tag4_q[`tagpos_thdid + 0] == 1'b1 & tlb_tag4_q[`tagpos_type_tlbwe] == 1'b1 & (tlb_tag4_q[`tagpos_gs] == 1'b0 | tlb_tag4_q[`tagpos_is] == 1'b0)) ? {tlb_datain_hi_hv_tlbwe_0_nopar, tlb_datain_hi_hv_tlbwe_0_par} : + (tlb_tag4_q[`tagpos_thdid + 0] == 1'b1 & tlb_tag4_q[`tagpos_type_tlbwe] == 1'b1 & tlb_tag4_q[`tagpos_gs] == 1'b1 & tlb_tag4_q[`tagpos_is] == 1'b1) ? {tlb_datain_hi_gs_tlbwe_0_nopar, tlb_datain_hi_gs_tlbwe_0_par} : +`ifdef MM_THREADS2 + (tlb_tag4_q[`tagpos_thdid + 1] == 1'b1 & tlb_tag4_q[`tagpos_type_tlbwe] == 1'b1 & (tlb_tag4_q[`tagpos_gs] == 1'b0 | tlb_tag4_q[`tagpos_is] == 1'b0)) ? {tlb_datain_hi_hv_tlbwe_1_nopar, tlb_datain_hi_hv_tlbwe_1_par} : + (tlb_tag4_q[`tagpos_thdid + 1] == 1'b1 & tlb_tag4_q[`tagpos_type_tlbwe] == 1'b1 & tlb_tag4_q[`tagpos_gs] == 1'b1 & tlb_tag4_q[`tagpos_is] == 1'b1) ? {tlb_datain_hi_gs_tlbwe_1_nopar, tlb_datain_hi_gs_tlbwe_1_par} : +`endif + (tlb_tag4_ptereload_sig == 1'b1 & tlb_tag4_q[`tagpos_gs] == 1'b0) ? {tlb_datain_hi_hv_ptereload_nopar, tlb_datain_hi_hv_ptereload_par} : + (tlb_tag4_ptereload_sig == 1'b1 & tlb_tag4_q[`tagpos_gs] == 1'b1) ? {tlb_datain_hi_gs_ptereload_nopar, tlb_datain_hi_gs_ptereload_par} : + (tlb_tag4_parerr_zeroize == 1'b1) ? {`TLB_WORD_WIDTH{1'b0}} : + tlb_datainb_q[`TLB_WORD_WIDTH:2 * `TLB_WORD_WIDTH - 1]; + // tlb_high_data + // 84 - 0 - X-bit + // 85:87 - 1:3 - reserved (3b) + // 88:117 - 4:33 - RPN (30b) + // 118:119 - 34:35 - R,C + // 120:121 - 36:37 - WLC (2b) + // 122 - 38 - ResvAttr + // 123 - 39 - VF + // 124 - 40 - IND + // 125:128 - 41:44 - U0-U3 + // 129:133 - 45:49 - WIMGE + // 134:135 - 50:51 - UX,SX + // 136:137 - 52:53 - UW,SW + // 138:139 - 54:55 - UR,SR + // 140 - 56 - GS + // 141 - 57 - TS + // 142:143 - 58:59 - reserved (2b) + // 144:149 - 60:65 - 6b TID msbs + // 150:157 - 66:73 - 8b TID lsbs + // 158:167 - 74:83 - parity 10bits + // mmucr3 + // 49 X-bit + // 50:51 R,C + // 52 ECL + // 53 TID_NZ + // 54:55 Class + // 56:57 WLC + // 58:59 ResvAttr + // 60:63 ThdID + // TLB Parity Generation + assign tlb_datain_lo_tlbwe_0_par[0] = ^(tlb_datain_lo_tlbwe_0_nopar[0:7]); + assign tlb_datain_lo_tlbwe_0_par[1] = ^(tlb_datain_lo_tlbwe_0_nopar[8:15]); + assign tlb_datain_lo_tlbwe_0_par[2] = ^(tlb_datain_lo_tlbwe_0_nopar[16:23]); + assign tlb_datain_lo_tlbwe_0_par[3] = ^(tlb_datain_lo_tlbwe_0_nopar[24:31]); + assign tlb_datain_lo_tlbwe_0_par[4] = ^(tlb_datain_lo_tlbwe_0_nopar[32:39]); + assign tlb_datain_lo_tlbwe_0_par[5] = ^(tlb_datain_lo_tlbwe_0_nopar[40:47]); + assign tlb_datain_lo_tlbwe_0_par[6] = ^({tlb_datain_lo_tlbwe_0_nopar[48:51], mmucr1_q[pos_tlb_pei]}); + assign tlb_datain_lo_tlbwe_0_par[7] = ^(tlb_datain_lo_tlbwe_0_nopar[52:59]); + assign tlb_datain_lo_tlbwe_0_par[8] = ^(tlb_datain_lo_tlbwe_0_nopar[60:65]); + assign tlb_datain_lo_tlbwe_0_par[9] = ^(tlb_datain_lo_tlbwe_0_nopar[66:73]); +`ifdef MM_THREADS2 + assign tlb_datain_lo_tlbwe_1_par[0] = ^(tlb_datain_lo_tlbwe_1_nopar[0:7]); + assign tlb_datain_lo_tlbwe_1_par[1] = ^(tlb_datain_lo_tlbwe_1_nopar[8:15]); + assign tlb_datain_lo_tlbwe_1_par[2] = ^(tlb_datain_lo_tlbwe_1_nopar[16:23]); + assign tlb_datain_lo_tlbwe_1_par[3] = ^(tlb_datain_lo_tlbwe_1_nopar[24:31]); + assign tlb_datain_lo_tlbwe_1_par[4] = ^(tlb_datain_lo_tlbwe_1_nopar[32:39]); + assign tlb_datain_lo_tlbwe_1_par[5] = ^(tlb_datain_lo_tlbwe_1_nopar[40:47]); + assign tlb_datain_lo_tlbwe_1_par[6] = ^({tlb_datain_lo_tlbwe_1_nopar[48:51], mmucr1_q[pos_tlb_pei]}); + assign tlb_datain_lo_tlbwe_1_par[7] = ^(tlb_datain_lo_tlbwe_1_nopar[52:59]); + assign tlb_datain_lo_tlbwe_1_par[8] = ^(tlb_datain_lo_tlbwe_1_nopar[60:65]); + assign tlb_datain_lo_tlbwe_1_par[9] = ^(tlb_datain_lo_tlbwe_1_nopar[66:73]); +`endif + assign tlb_datain_lo_ptereload_par[0] = ^(tlb_datain_lo_ptereload_nopar[0:7]); + assign tlb_datain_lo_ptereload_par[1] = ^(tlb_datain_lo_ptereload_nopar[8:15]); + assign tlb_datain_lo_ptereload_par[2] = ^(tlb_datain_lo_ptereload_nopar[16:23]); + assign tlb_datain_lo_ptereload_par[3] = ^(tlb_datain_lo_ptereload_nopar[24:31]); + assign tlb_datain_lo_ptereload_par[4] = ^(tlb_datain_lo_ptereload_nopar[32:39]); + assign tlb_datain_lo_ptereload_par[5] = ^(tlb_datain_lo_ptereload_nopar[40:47]); + assign tlb_datain_lo_ptereload_par[6] = ^(tlb_datain_lo_ptereload_nopar[48:51]); + assign tlb_datain_lo_ptereload_par[7] = ^(tlb_datain_lo_ptereload_nopar[52:59]); + assign tlb_datain_lo_ptereload_par[8] = ^(tlb_datain_lo_ptereload_nopar[60:65]); + assign tlb_datain_lo_ptereload_par[9] = ^(tlb_datain_lo_ptereload_nopar[66:73]); + assign tlb_datain_hi_hv_tlbwe_0_par[0] = ^(tlb_datain_hi_hv_tlbwe_0_nopar[0:7]); + assign tlb_datain_hi_hv_tlbwe_0_par[1] = ^(tlb_datain_hi_hv_tlbwe_0_nopar[8:15]); + assign tlb_datain_hi_hv_tlbwe_0_par[2] = ^(tlb_datain_hi_hv_tlbwe_0_nopar[16:23]); + assign tlb_datain_hi_hv_tlbwe_0_par[3] = ^(tlb_datain_hi_hv_tlbwe_0_nopar[24:31]); + assign tlb_datain_hi_hv_tlbwe_0_par[4] = ^(tlb_datain_hi_hv_tlbwe_0_nopar[32:39]); + assign tlb_datain_hi_hv_tlbwe_0_par[5] = ^(tlb_datain_hi_hv_tlbwe_0_nopar[40:44]); + assign tlb_datain_hi_hv_tlbwe_0_par[6] = ^(tlb_datain_hi_hv_tlbwe_0_nopar[45:49]); + assign tlb_datain_hi_hv_tlbwe_0_par[7] = ^(tlb_datain_hi_hv_tlbwe_0_nopar[50:57]); + assign tlb_datain_hi_hv_tlbwe_0_par[8] = ^(tlb_datain_hi_hv_tlbwe_0_nopar[58:65]); + assign tlb_datain_hi_hv_tlbwe_0_par[9] = ^(tlb_datain_hi_hv_tlbwe_0_nopar[66:73]); +`ifdef MM_THREADS2 + assign tlb_datain_hi_hv_tlbwe_1_par[0] = ^(tlb_datain_hi_hv_tlbwe_1_nopar[0:7]); + assign tlb_datain_hi_hv_tlbwe_1_par[1] = ^(tlb_datain_hi_hv_tlbwe_1_nopar[8:15]); + assign tlb_datain_hi_hv_tlbwe_1_par[2] = ^(tlb_datain_hi_hv_tlbwe_1_nopar[16:23]); + assign tlb_datain_hi_hv_tlbwe_1_par[3] = ^(tlb_datain_hi_hv_tlbwe_1_nopar[24:31]); + assign tlb_datain_hi_hv_tlbwe_1_par[4] = ^(tlb_datain_hi_hv_tlbwe_1_nopar[32:39]); + assign tlb_datain_hi_hv_tlbwe_1_par[5] = ^(tlb_datain_hi_hv_tlbwe_1_nopar[40:44]); + assign tlb_datain_hi_hv_tlbwe_1_par[6] = ^(tlb_datain_hi_hv_tlbwe_1_nopar[45:49]); + assign tlb_datain_hi_hv_tlbwe_1_par[7] = ^(tlb_datain_hi_hv_tlbwe_1_nopar[50:57]); + assign tlb_datain_hi_hv_tlbwe_1_par[8] = ^(tlb_datain_hi_hv_tlbwe_1_nopar[58:65]); + assign tlb_datain_hi_hv_tlbwe_1_par[9] = ^(tlb_datain_hi_hv_tlbwe_1_nopar[66:73]); +`endif + assign tlb_datain_hi_gs_tlbwe_0_par[0] = ^(tlb_datain_hi_gs_tlbwe_0_nopar[0:7]); + assign tlb_datain_hi_gs_tlbwe_0_par[1] = ^(tlb_datain_hi_gs_tlbwe_0_nopar[8:15]); + assign tlb_datain_hi_gs_tlbwe_0_par[2] = ^(tlb_datain_hi_gs_tlbwe_0_nopar[16:23]); + assign tlb_datain_hi_gs_tlbwe_0_par[3] = ^(tlb_datain_hi_gs_tlbwe_0_nopar[24:31]); + assign tlb_datain_hi_gs_tlbwe_0_par[4] = ^(tlb_datain_hi_gs_tlbwe_0_nopar[32:39]); + assign tlb_datain_hi_gs_tlbwe_0_par[5] = ^(tlb_datain_hi_gs_tlbwe_0_nopar[40:44]); + assign tlb_datain_hi_gs_tlbwe_0_par[6] = ^(tlb_datain_hi_gs_tlbwe_0_nopar[45:49]); + assign tlb_datain_hi_gs_tlbwe_0_par[7] = ^(tlb_datain_hi_gs_tlbwe_0_nopar[50:57]); + assign tlb_datain_hi_gs_tlbwe_0_par[8] = ^(tlb_datain_hi_gs_tlbwe_0_nopar[58:65]); + assign tlb_datain_hi_gs_tlbwe_0_par[9] = ^(tlb_datain_hi_gs_tlbwe_0_nopar[66:73]); +`ifdef MM_THREADS2 + assign tlb_datain_hi_gs_tlbwe_1_par[0] = ^(tlb_datain_hi_gs_tlbwe_1_nopar[0:7]); + assign tlb_datain_hi_gs_tlbwe_1_par[1] = ^(tlb_datain_hi_gs_tlbwe_1_nopar[8:15]); + assign tlb_datain_hi_gs_tlbwe_1_par[2] = ^(tlb_datain_hi_gs_tlbwe_1_nopar[16:23]); + assign tlb_datain_hi_gs_tlbwe_1_par[3] = ^(tlb_datain_hi_gs_tlbwe_1_nopar[24:31]); + assign tlb_datain_hi_gs_tlbwe_1_par[4] = ^(tlb_datain_hi_gs_tlbwe_1_nopar[32:39]); + assign tlb_datain_hi_gs_tlbwe_1_par[5] = ^(tlb_datain_hi_gs_tlbwe_1_nopar[40:44]); + assign tlb_datain_hi_gs_tlbwe_1_par[6] = ^(tlb_datain_hi_gs_tlbwe_1_nopar[45:49]); + assign tlb_datain_hi_gs_tlbwe_1_par[7] = ^(tlb_datain_hi_gs_tlbwe_1_nopar[50:57]); + assign tlb_datain_hi_gs_tlbwe_1_par[8] = ^(tlb_datain_hi_gs_tlbwe_1_nopar[58:65]); + assign tlb_datain_hi_gs_tlbwe_1_par[9] = ^(tlb_datain_hi_gs_tlbwe_1_nopar[66:73]); +`endif + assign tlb_datain_hi_hv_ptereload_par[0] = ^(tlb_datain_hi_hv_ptereload_nopar[0:7]); + assign tlb_datain_hi_hv_ptereload_par[1] = ^(tlb_datain_hi_hv_ptereload_nopar[8:15]); + assign tlb_datain_hi_hv_ptereload_par[2] = ^(tlb_datain_hi_hv_ptereload_nopar[16:23]); + assign tlb_datain_hi_hv_ptereload_par[3] = ^(tlb_datain_hi_hv_ptereload_nopar[24:31]); + assign tlb_datain_hi_hv_ptereload_par[4] = ^(tlb_datain_hi_hv_ptereload_nopar[32:39]); + assign tlb_datain_hi_hv_ptereload_par[5] = ^(tlb_datain_hi_hv_ptereload_nopar[40:44]); + assign tlb_datain_hi_hv_ptereload_par[6] = ^(tlb_datain_hi_hv_ptereload_nopar[45:49]); + assign tlb_datain_hi_hv_ptereload_par[7] = ^(tlb_datain_hi_hv_ptereload_nopar[50:57]); + assign tlb_datain_hi_hv_ptereload_par[8] = ^(tlb_datain_hi_hv_ptereload_nopar[58:65]); + assign tlb_datain_hi_hv_ptereload_par[9] = ^(tlb_datain_hi_hv_ptereload_nopar[66:73]); + assign tlb_datain_hi_gs_ptereload_par[0] = ^(tlb_datain_hi_gs_ptereload_nopar[0:7]); + assign tlb_datain_hi_gs_ptereload_par[1] = ^(tlb_datain_hi_gs_ptereload_nopar[8:15]); + assign tlb_datain_hi_gs_ptereload_par[2] = ^(tlb_datain_hi_gs_ptereload_nopar[16:23]); + assign tlb_datain_hi_gs_ptereload_par[3] = ^(tlb_datain_hi_gs_ptereload_nopar[24:31]); + assign tlb_datain_hi_gs_ptereload_par[4] = ^(tlb_datain_hi_gs_ptereload_nopar[32:39]); + assign tlb_datain_hi_gs_ptereload_par[5] = ^(tlb_datain_hi_gs_ptereload_nopar[40:44]); + assign tlb_datain_hi_gs_ptereload_par[6] = ^(tlb_datain_hi_gs_ptereload_nopar[45:49]); + assign tlb_datain_hi_gs_ptereload_par[7] = ^(tlb_datain_hi_gs_ptereload_nopar[50:57]); + assign tlb_datain_hi_gs_ptereload_par[8] = ^(tlb_datain_hi_gs_ptereload_nopar[58:65]); + assign tlb_datain_hi_gs_ptereload_par[9] = ^(tlb_datain_hi_gs_ptereload_nopar[66:73]); + // ex7 phase signals + assign tlb_dataina = tlb_dataina_q; + assign tlb_datainb = tlb_datainb_q; + assign tlb_cmp_dbg_tag5_tlb_datain_q = tlb_dataina_q; + // + // tlb_low_data + // 0:51 - EPN + // 52:55 - SIZE (4b) + // 56:59 - ThdID + // 60:61 - Class + // 62:63 - ExtClass + // 64:65 - reserved (2b) + // 66:73 - 8b for LPID + // 74:83 - parity 10bits + // tlb_high_data + // 84 - 0 - X-bit + // 85:87 - 1:3 - reserved (3b) + // 88:117 - 4:33 - RPN (30b) + // 118:119 - 34:35 - R,C + // 120:121 - 36:37 - WLC (2b) + // 122 - 38 - ResvAttr + // 123 - 39 - VF + // 124 - 40 - IND + // 125:128 - 41:44 - U0-U3 + // 129:133 - 45:49 - WIMGE + // 134:136 - 50:52 - UX,UW,UR + // 137:139 - 53:55 - SX,SW,SR + // 140 - 56 - GS + // 141 - 57 - TS + // 142:143 - 58:59 - reserved (2b) + // 144:149 - 60:65 - 6b TID msbs + // 150:157 - 66:73 - 8b TID lsbs + // 158:167 - 74:83 - parity 10bits + //--------- this is what the erat expects on reload bus + // 0:51 - EPN + // 52 - X + // 53:55 - SIZE + // 56 - V + // 57:60 - ThdID + // 61:62 - Class + // 63:64 - ExtClass + // 65 - write enable + // 0:3 66:69 - reserved RPN + // 4:33 70:99 - RPN + // 34:35 100:101 - R,C + // 36 102 - reserved + // 37:38 103:104 - WLC + // 39 105 - ResvAttr + // 40 106 - VF + // 41:44 107:110 - U0-U3 + // 45:49 111:115 - WIMGE + // 50:51 116:117 - UX,SX + // 52:53 118:119 - UW,SW + // 54:55 120:121 - UR,SR + // 56 122 - GS + // 57 123 - TS + // 58:65 124:131 - TID lsbs + //--------- + // `waypos_epn : natural := 0; + // `waypos_size : natural := 52; + // `waypos_thdid : natural := 56; + // `waypos_class : natural := 60; + // `waypos_extclass : natural := 62; + // `waypos_lpid : natural := 66; + // `waypos_xbit : natural := 84; + // `waypos_tstmode4k : natural := 85; + // `waypos_rpn : natural := 88; + // `waypos_rc : natural := 118; + // `waypos_wlc : natural := 120; + // `waypos_resvattr : natural := 122; + // `waypos_vf : natural := 123; + // `waypos_ind : natural := 124; + // `waypos_ubits : natural := 125; + // `waypos_wimge : natural := 129; + // `waypos_usxwr : natural := 134; + // `waypos_gs : natural := 140; + // `waypos_ts : natural := 141; + // `waypos_tid : natural := 144; -- 14 bits + + // Adding tstmode4k muxing + + assign tlb_erat_rel_d[`eratpos_epn:`EPN_WIDTH - 1] = (tlb_tag4_erat_data_cap == 1'b1 & tlb_tag4_way_or[`waypos_tstmode4k:`waypos_tstmode4k+2] == 3'b100) ? tlb_tag4_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 1] : + (tlb_tag4_erat_data_cap == 1'b1 & tlb_tag4_way_or[`waypos_tstmode4k:`waypos_tstmode4k+2] == 3'b101) ? {tlb_tag4_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 5], 4'b0000} : + (tlb_tag4_erat_data_cap == 1'b1 & tlb_tag4_way_or[`waypos_tstmode4k:`waypos_tstmode4k+2] == 3'b110) ? {tlb_tag4_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 9], 8'b00000000} : + (tlb_tag4_erat_data_cap == 1'b1 & tlb_tag4_way_or[`waypos_tstmode4k:`waypos_tstmode4k+2] == 3'b111) ? {tlb_tag4_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 13], 12'b000000000000} : + (tlb_tag4_erat_data_cap == 1'b1) ? tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 1] : + tlb_erat_rel_q[`eratpos_epn:`EPN_WIDTH - 1]; + + assign tlb_erat_rel_d[`eratpos_size:`eratpos_size + 2] = (tlb_tag4_erat_data_cap == 1'b1 & tlb_tag4_way_or[`waypos_tstmode4k:`waypos_tstmode4k+2] == 3'b100) ? ERAT_PgSize_4KB : + (tlb_tag4_erat_data_cap == 1'b1 & tlb_tag4_way_or[`waypos_tstmode4k:`waypos_tstmode4k+2] == 3'b101) ? ERAT_PgSize_64KB : + (tlb_tag4_erat_data_cap == 1'b1 & tlb_tag4_way_or[`waypos_tstmode4k:`waypos_tstmode4k+2] == 3'b110) ? ERAT_PgSize_1MB : + (tlb_tag4_erat_data_cap == 1'b1 & tlb_tag4_way_or[`waypos_tstmode4k:`waypos_tstmode4k+2] == 3'b111) ? ERAT_PgSize_16MB : + (tlb_tag4_erat_data_cap == 1'b1) ? erat_pgsize[0:2] : + tlb_erat_rel_q[`eratpos_size:`eratpos_size + 2]; + + assign tlb_erat_rel_d[`eratpos_x] = (tlb_tag4_erat_data_cap == 1'b1 & tlb_tag4_way_or[`waypos_tstmode4k] == 1'b1) ? 1'b0 : + (tlb_tag4_erat_data_cap == 1'b1) ? tlb_tag4_way_or[`waypos_xbit] : + tlb_erat_rel_q[`eratpos_x]; + assign tlb_erat_rel_d[`eratpos_v] = (tlb_tag4_erat_data_cap == 1'b1) ? 1'b1 : + tlb_erat_rel_q[`eratpos_v]; + + // Adding tstmode4k muxing + + assign tlb_erat_rel_clone_d[`eratpos_epn:`EPN_WIDTH - 1] = (tlb_tag4_erat_data_cap == 1'b1 & tlb_tag4_way_or[`waypos_tstmode4k:`waypos_tstmode4k+2] == 3'b100) ? tlb_tag4_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 1] : + (tlb_tag4_erat_data_cap == 1'b1 & tlb_tag4_way_or[`waypos_tstmode4k:`waypos_tstmode4k+2] == 3'b101) ? {tlb_tag4_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 5], 4'b0000} : + (tlb_tag4_erat_data_cap == 1'b1 & tlb_tag4_way_or[`waypos_tstmode4k:`waypos_tstmode4k+2] == 3'b110) ? {tlb_tag4_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 9], 8'b00000000} : + (tlb_tag4_erat_data_cap == 1'b1 & tlb_tag4_way_or[`waypos_tstmode4k:`waypos_tstmode4k+2] == 3'b111) ? {tlb_tag4_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 13], 12'b000000000000} : + (tlb_tag4_erat_data_cap == 1'b1) ? tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 1] : + tlb_erat_rel_clone_q[`eratpos_epn:`EPN_WIDTH - 1]; + + assign tlb_erat_rel_clone_d[`eratpos_size:`eratpos_size + 2] = (tlb_tag4_erat_data_cap == 1'b1 & tlb_tag4_way_or[`waypos_tstmode4k:`waypos_tstmode4k+2] == 3'b100) ? ERAT_PgSize_4KB : + (tlb_tag4_erat_data_cap == 1'b1 & tlb_tag4_way_or[`waypos_tstmode4k:`waypos_tstmode4k+2] == 3'b101) ? ERAT_PgSize_64KB : + (tlb_tag4_erat_data_cap == 1'b1 & tlb_tag4_way_or[`waypos_tstmode4k:`waypos_tstmode4k+2] == 3'b110) ? ERAT_PgSize_1MB : + (tlb_tag4_erat_data_cap == 1'b1 & tlb_tag4_way_or[`waypos_tstmode4k:`waypos_tstmode4k+2] == 3'b111) ? ERAT_PgSize_16MB : + (tlb_tag4_erat_data_cap == 1'b1) ? erat_pgsize[0:2] : + tlb_erat_rel_clone_q[`eratpos_size:`eratpos_size + 2]; + + assign tlb_erat_rel_clone_d[`eratpos_x] = (tlb_tag4_erat_data_cap == 1'b1 & tlb_tag4_way_or[`waypos_tstmode4k] == 1'b1) ? 1'b0 : + (tlb_tag4_erat_data_cap == 1'b1) ? tlb_tag4_way_or[`waypos_xbit] : + tlb_erat_rel_clone_q[`eratpos_x]; + assign tlb_erat_rel_clone_d[`eratpos_v] = (tlb_tag4_erat_data_cap == 1'b1) ? 1'b1 : + tlb_erat_rel_clone_q[`eratpos_v]; + + // mmucr1 11-LRUPEI, 12:13-ICTID/ITTID, 14:15-DCTID/DTTID, 16-DCCD, 17-TLBWE_BINV, 18-TLBI_MSB + // + // ERAT reload THDID values + // TTYPE ITTID DTTID DCCD THDID(0:3) term + //--------------------------------------------------------------------- + // ierat 0 - - TLB_entry.thdid(0:3) (1) + // ierat 1 - - TLB_entry.tid(2:5) (2) + // htw inst 0 - - IND entry.thdid(0:3) (3) + // htw inst 1 - - PTE_reload.pid(2:5) (4) + // derat - 0 - TLB_entry.thdid(0:3) (1) + // derat - 1 - TLB_entry.tid(2:5) (2) + // htw data - 0 - IND entry.thdid(0:3) (3) + // htw data - 1 - PTE_reload.pid(2:5) (4) + // + assign tlb_erat_rel_d[`eratpos_thdid:`eratpos_thdid + `THDID_WIDTH - 1] = (((tlb_tag4_q[`tagpos_type_ierat] == 1'b1 & tlb_tag4_q[`tagpos_type_ptereload] == 1'b0 & mmucr1_q[pos_ittid] == 1'b0 & tlb_tag4_q[`tagpos_ind] == 1'b0) | (tlb_tag4_q[`tagpos_type_derat] == 1'b1 & tlb_tag4_q[`tagpos_type_ptereload] == 1'b0 & mmucr1_q[pos_dttid] == 1'b0 & tlb_tag4_q[`tagpos_ind] == 1'b0))) ? tlb_tag4_way_or[`waypos_thdid:`waypos_thdid + `THDID_WIDTH - 1] : + (((tlb_tag4_q[`tagpos_type_ierat] == 1'b1 & tlb_tag4_q[`tagpos_type_ptereload] == 1'b0 & mmucr1_q[pos_ittid] == 1'b1 & tlb_tag4_q[`tagpos_ind] == 1'b0) | (tlb_tag4_q[`tagpos_type_derat] == 1'b1 & tlb_tag4_q[`tagpos_type_ptereload] == 1'b0 & mmucr1_q[pos_dttid] == 1'b1 & tlb_tag4_q[`tagpos_ind] == 1'b0))) ? tlb_tag4_way_or[`waypos_tid + 2:`waypos_tid + 5] : + (((tlb_tag4_q[`tagpos_type_ierat] == 1'b1 & tlb_tag4_q[`tagpos_type_ptereload] == 1'b1 & mmucr1_q[pos_ittid] == 1'b0 & tlb_tag4_q[`tagpos_ind] == 1'b0) | (tlb_tag4_q[`tagpos_type_derat] == 1'b1 & tlb_tag4_q[`tagpos_type_ptereload] == 1'b1 & mmucr1_q[pos_dttid] == 1'b0 & tlb_tag4_q[`tagpos_ind] == 1'b0))) ? ({tlb_tag4_q[`tagpos_atsel], tlb_tag4_q[`tagpos_esel:`tagpos_esel + 2]}) : + (((tlb_tag4_q[`tagpos_type_ierat] == 1'b1 & tlb_tag4_q[`tagpos_type_ptereload] == 1'b1 & mmucr1_q[pos_ittid] == 1'b1 & tlb_tag4_q[`tagpos_ind] == 1'b0) | (tlb_tag4_q[`tagpos_type_derat] == 1'b1 & tlb_tag4_q[`tagpos_type_ptereload] == 1'b1 & mmucr1_q[pos_dttid] == 1'b1 & tlb_tag4_q[`tagpos_ind] == 1'b0))) ? tlb_tag4_q[`tagpos_pid + 2:`tagpos_pid + 5] : + tlb_erat_rel_q[`eratpos_thdid:`eratpos_thdid + `THDID_WIDTH - 1]; + assign tlb_erat_rel_clone_d[`eratpos_thdid:`eratpos_thdid + `THDID_WIDTH - 1] = (((tlb_tag4_q[`tagpos_type_ierat] == 1'b1 & tlb_tag4_q[`tagpos_type_ptereload] == 1'b0 & mmucr1_clone_q[pos_ittid] == 1'b0 & tlb_tag4_q[`tagpos_ind] == 1'b0) | (tlb_tag4_q[`tagpos_type_derat] == 1'b1 & tlb_tag4_q[`tagpos_type_ptereload] == 1'b0 & mmucr1_clone_q[pos_dttid] == 1'b0 & tlb_tag4_q[`tagpos_ind] == 1'b0))) ? tlb_tag4_way_or[`waypos_thdid:`waypos_thdid + `THDID_WIDTH - 1] : + (((tlb_tag4_q[`tagpos_type_ierat] == 1'b1 & tlb_tag4_q[`tagpos_type_ptereload] == 1'b0 & mmucr1_clone_q[pos_ittid] == 1'b1 & tlb_tag4_q[`tagpos_ind] == 1'b0) | (tlb_tag4_q[`tagpos_type_derat] == 1'b1 & tlb_tag4_q[`tagpos_type_ptereload] == 1'b0 & mmucr1_clone_q[pos_dttid] == 1'b1 & tlb_tag4_q[`tagpos_ind] == 1'b0))) ? tlb_tag4_way_or[`waypos_tid + 2:`waypos_tid + 5] : + (((tlb_tag4_q[`tagpos_type_ierat] == 1'b1 & tlb_tag4_q[`tagpos_type_ptereload] == 1'b1 & mmucr1_clone_q[pos_ittid] == 1'b0 & tlb_tag4_q[`tagpos_ind] == 1'b0) | (tlb_tag4_q[`tagpos_type_derat] == 1'b1 & tlb_tag4_q[`tagpos_type_ptereload] == 1'b1 & mmucr1_clone_q[pos_dttid] == 1'b0 & tlb_tag4_q[`tagpos_ind] == 1'b0))) ? ({tlb_tag4_q[`tagpos_atsel], tlb_tag4_q[`tagpos_esel:`tagpos_esel + 2]}) : + (((tlb_tag4_q[`tagpos_type_ierat] == 1'b1 & tlb_tag4_q[`tagpos_type_ptereload] == 1'b1 & mmucr1_clone_q[pos_ittid] == 1'b1 & tlb_tag4_q[`tagpos_ind] == 1'b0) | (tlb_tag4_q[`tagpos_type_derat] == 1'b1 & tlb_tag4_q[`tagpos_type_ptereload] == 1'b1 & mmucr1_clone_q[pos_dttid] == 1'b1 & tlb_tag4_q[`tagpos_ind] == 1'b0))) ? tlb_tag4_q[`tagpos_pid + 2:`tagpos_pid + 5] : + tlb_erat_rel_clone_q[`eratpos_thdid:`eratpos_thdid + `THDID_WIDTH - 1]; + // mmucr1 11-LRUPEI, 12:13-ICTID/ITTID, 14:15-DCTID/DTTID, 16-DCCD, 17-TLBWE_BINV, 18-TLBI_MSB + // + // ERAT reload CLASS values + // TTYPE ICTID DCTID DCCD CLASS(0:1) term + //------------------------------------------------------------------------- + // ierat 0 - - TLB_entry.class(0:1) (1) + // ierat 1 - - TLB_entry.tid(0:1) (2) + // htw inst 0 - - 00 (4) + // htw inst 1 - - PTE_reload.pid(0:1) (5) + // derat non-epid - 0 0 0 & TLB_entry.class(1) (3) + // derat non-epid - 0 1 TLB_entry.class(0:1) (1) + // derat non-epid - 1 - TLB_entry.tid(0:1) (2) + // derat epid load - 0 0 10 (3) + // derat epid store - 0 0 11 (3) + // derat epid - 0 1 TLB_entry.class(0:1) (1) + // derat epid - 1 - TLB_entry.tid(0:1) (2) + // htw data non-epid - 0 - 00 (4) + // htw data non-epid - 1 - PTE_reload.pid(0:1) (5) + // htw data epid load - 0 - 10 (4) + // htw data epid store - 0 - 11 (4) + // htw data epid - 1 - PTE_reload.pid(0:1) (5) + // + // non-clone is the ierat side + assign tlb_erat_rel_d[`eratpos_class:`eratpos_class + `CLASS_WIDTH - 1] = (tlb_tag4_erat_data_cap == 1'b1 & ((tlb_tag4_q[`tagpos_type_ierat] == 1'b1 & tlb_tag4_q[`tagpos_type_ptereload] == 1'b0 & mmucr1_q[pos_ictid] == 1'b0 & tlb_tag4_q[`tagpos_ind] == 1'b0) | + (tlb_tag4_q[`tagpos_type_derat] == 1'b1 & tlb_tag4_q[`tagpos_type_ptereload] == 1'b0 & mmucr1_q[pos_dctid] == 1'b0 & mmucr1_q[pos_dccd] == 1'b1 & tlb_tag4_q[`tagpos_ind] == 1'b0))) ? tlb_tag4_way_or[`waypos_class:`waypos_class + `CLASS_WIDTH - 1] : + (tlb_tag4_erat_data_cap == 1'b1 & ((tlb_tag4_q[`tagpos_type_ierat] == 1'b1 & tlb_tag4_q[`tagpos_type_ptereload] == 1'b0 & mmucr1_q[pos_ictid] == 1'b1 & tlb_tag4_q[`tagpos_ind] == 1'b0) | + (tlb_tag4_q[`tagpos_type_derat] == 1'b1 & tlb_tag4_q[`tagpos_type_ptereload] == 1'b0 & mmucr1_q[pos_dctid] == 1'b1 & tlb_tag4_q[`tagpos_ind] == 1'b0))) ? tlb_tag4_way_or[`waypos_tid + 0:`waypos_tid + 1] : + ((tlb_tag4_erat_data_cap == 1'b1 & tlb_tag4_q[`tagpos_type_derat] == 1'b1 & tlb_tag4_q[`tagpos_type_ptereload] == 1'b0 & mmucr1_q[pos_dctid] == 1'b0 & mmucr1_q[pos_dccd] == 1'b0 & tlb_tag4_q[`tagpos_ind] == 1'b0)) ? ({tlb_tag4_q[`tagpos_class], ((tlb_tag4_q[`tagpos_class] & tlb_tag4_q[`tagpos_class + 1]) | ((~(tlb_tag4_q[`tagpos_class])) & tlb_tag4_way_or[`waypos_class + 1]))}) : + (tlb_tag4_erat_data_cap == 1'b1 & ((tlb_tag4_q[`tagpos_type_ierat] == 1'b1 & tlb_tag4_q[`tagpos_type_ptereload] == 1'b1 & mmucr1_q[pos_ictid] == 1'b0 & tlb_tag4_q[`tagpos_ind] == 1'b0) | + (tlb_tag4_q[`tagpos_type_derat] == 1'b1 & tlb_tag4_q[`tagpos_type_ptereload] == 1'b1 & mmucr1_q[pos_dctid] == 1'b0 & tlb_tag4_q[`tagpos_ind] == 1'b0))) ? ({tlb_tag4_q[`tagpos_class], (tlb_tag4_q[`tagpos_class] & tlb_tag4_q[`tagpos_class + 1])}) : + (tlb_tag4_erat_data_cap == 1'b1 & ((tlb_tag4_q[`tagpos_type_ierat] == 1'b1 & tlb_tag4_q[`tagpos_type_ptereload] == 1'b1 & mmucr1_q[pos_ictid] == 1'b1 & tlb_tag4_q[`tagpos_ind] == 1'b0) | + (tlb_tag4_q[`tagpos_type_derat] == 1'b1 & tlb_tag4_q[`tagpos_type_ptereload] == 1'b1 & mmucr1_q[pos_dctid] == 1'b1 & tlb_tag4_q[`tagpos_ind] == 1'b0))) ? tlb_tag4_q[`tagpos_pid + 0:`tagpos_pid + 1] : + tlb_erat_rel_q[`eratpos_class:`eratpos_class + `CLASS_WIDTH - 1]; + // clone is the derat side + assign tlb_erat_rel_clone_d[`eratpos_class:`eratpos_class + `CLASS_WIDTH - 1] = (tlb_tag4_erat_data_cap == 1'b1 & ((tlb_tag4_q[`tagpos_type_ierat] == 1'b1 & tlb_tag4_q[`tagpos_type_ptereload] == 1'b0 & mmucr1_clone_q[pos_ictid] == 1'b0 & tlb_tag4_q[`tagpos_ind] == 1'b0) | (tlb_tag4_q[`tagpos_type_derat] == 1'b1 & tlb_tag4_q[`tagpos_type_ptereload] == 1'b0 & mmucr1_clone_q[pos_dctid] == 1'b0 & mmucr1_clone_q[pos_dccd] == 1'b1 & tlb_tag4_q[`tagpos_ind] == 1'b0))) ? tlb_tag4_way_or[`waypos_class:`waypos_class + `CLASS_WIDTH - 1] : + (tlb_tag4_erat_data_cap == 1'b1 & ((tlb_tag4_q[`tagpos_type_ierat] == 1'b1 & tlb_tag4_q[`tagpos_type_ptereload] == 1'b0 & mmucr1_clone_q[pos_ictid] == 1'b1 & tlb_tag4_q[`tagpos_ind] == 1'b0) | (tlb_tag4_q[`tagpos_type_derat] == 1'b1 & tlb_tag4_q[`tagpos_type_ptereload] == 1'b0 & mmucr1_clone_q[pos_dctid] == 1'b1 & tlb_tag4_q[`tagpos_ind] == 1'b0))) ? tlb_tag4_way_or[`waypos_tid + 0:`waypos_tid + 1] : + ((tlb_tag4_erat_data_cap == 1'b1 & tlb_tag4_q[`tagpos_type_derat] == 1'b1 & tlb_tag4_q[`tagpos_type_ptereload] == 1'b0 & mmucr1_clone_q[pos_dctid] == 1'b0 & mmucr1_clone_q[pos_dccd] == 1'b0 & tlb_tag4_q[`tagpos_ind] == 1'b0)) ? ({tlb_tag4_q[`tagpos_class], ((tlb_tag4_q[`tagpos_class] & tlb_tag4_q[`tagpos_class + 1]) | ((~(tlb_tag4_q[`tagpos_class])) & tlb_tag4_way_or[`waypos_class + 1]))}) : + (tlb_tag4_erat_data_cap == 1'b1 & ((tlb_tag4_q[`tagpos_type_ierat] == 1'b1 & tlb_tag4_q[`tagpos_type_ptereload] == 1'b1 & mmucr1_clone_q[pos_ictid] == 1'b0 & tlb_tag4_q[`tagpos_ind] == 1'b0) | (tlb_tag4_q[`tagpos_type_derat] == 1'b1 & tlb_tag4_q[`tagpos_type_ptereload] == 1'b1 & mmucr1_clone_q[pos_dctid] == 1'b0 & tlb_tag4_q[`tagpos_ind] == 1'b0))) ? ({tlb_tag4_q[`tagpos_class], (tlb_tag4_q[`tagpos_class] & tlb_tag4_q[`tagpos_class + 1])}) : + (tlb_tag4_erat_data_cap == 1'b1 & ((tlb_tag4_q[`tagpos_type_ierat] == 1'b1 & tlb_tag4_q[`tagpos_type_ptereload] == 1'b1 & mmucr1_clone_q[pos_ictid] == 1'b1 & tlb_tag4_q[`tagpos_ind] == 1'b0) | (tlb_tag4_q[`tagpos_type_derat] == 1'b1 & tlb_tag4_q[`tagpos_type_ptereload] == 1'b1 & mmucr1_clone_q[pos_dctid] == 1'b1 & tlb_tag4_q[`tagpos_ind] == 1'b0))) ? tlb_tag4_q[`tagpos_pid + 0:`tagpos_pid + 1] : + tlb_erat_rel_clone_q[`eratpos_class:`eratpos_class + `CLASS_WIDTH - 1]; + // non-clone is the ierat side + assign tlb_erat_rel_d[`eratpos_extclass:`eratpos_extclass + 1] = (tlb_tag4_erat_data_cap == 1'b1) ? tlb_tag4_way_or[`waypos_extclass:`waypos_extclass + 1] : + tlb_erat_rel_q[`eratpos_extclass:`eratpos_extclass + 1]; + assign tlb_erat_rel_d[`eratpos_wren] = ((tlb_tag4_erat_data_cap == 1'b1 & (tlb_tag4_q[`tagpos_type_ierat] == 1'b1 | tlb_tag4_q[`tagpos_type_derat] == 1'b1) & tlb_tag4_q[`tagpos_type_ptereload] == 1'b0 & + tlb_tag4_wayhit_q[`TLB_WAYS] == 1'b1 & tlb_tag4_q[`tagpos_wq + 1] == 1'b0 & tlb_tag4_q[`tagpos_ind] == 1'b0 & + multihit == 1'b0 & |(tag4_parerr_q[0:4]) == 1'b0)) ? 1'b1 : + (tlb_tag4_erat_data_cap == 1'b1) ? 1'b0 : + tlb_erat_rel_q[`eratpos_wren]; + assign tlb_erat_rel_d[`eratpos_rpnrsvd:`eratpos_rpnrsvd + 3] = {4{1'b0}}; + assign tlb_erat_rel_d[`eratpos_rpn:`eratpos_rpn + `RPN_WIDTH - 1] = (tlb_tag4_erat_data_cap == 1'b1) ? tlb_tag4_way_or[`waypos_rpn:`waypos_rpn + `RPN_WIDTH - 1] : + tlb_erat_rel_q[`eratpos_rpn:`eratpos_rpn + `RPN_WIDTH - 1]; + assign tlb_erat_rel_d[`eratpos_r:`eratpos_c] = (tlb_tag4_erat_data_cap == 1'b1) ? tlb_tag4_way_or[`waypos_rc:`waypos_rc + 1] : + tlb_erat_rel_q[`eratpos_r:`eratpos_c]; + assign tlb_erat_rel_d[`eratpos_relsoon] = ierat_req_taken | ptereload_req_taken | tlb_tag0_type[1]; + assign tlb_erat_rel_d[`eratpos_wlc:`eratpos_wlc + 1] = (tlb_tag4_erat_data_cap == 1'b1) ? tlb_tag4_way_or[`waypos_wlc:`waypos_wlc + 1] : + tlb_erat_rel_q[`eratpos_wlc:`eratpos_wlc + 1]; + assign tlb_erat_rel_d[`eratpos_resvattr] = (tlb_tag4_erat_data_cap == 1'b1) ? tlb_tag4_way_or[`waypos_resvattr] : + tlb_erat_rel_q[`eratpos_resvattr]; + assign tlb_erat_rel_d[`eratpos_vf] = (tlb_tag4_erat_data_cap == 1'b1) ? tlb_tag4_way_or[`waypos_vf] : + tlb_erat_rel_q[`eratpos_vf]; + assign tlb_erat_rel_d[`eratpos_ubits:`eratpos_ubits + 3] = (tlb_tag4_erat_data_cap == 1'b1) ? tlb_tag4_way_or[`waypos_ubits:`waypos_ubits + 3] : + tlb_erat_rel_q[`eratpos_ubits:`eratpos_ubits + 3]; + assign tlb_erat_rel_d[`eratpos_wimge:`eratpos_wimge + 4] = (tlb_tag4_erat_data_cap == 1'b1) ? tlb_tag4_way_or[`waypos_wimge:`waypos_wimge + 4] : + tlb_erat_rel_q[`eratpos_wimge:`eratpos_wimge + 4]; + assign tlb_erat_rel_d[`eratpos_usxwr:`eratpos_usxwr + 5] = (tlb_tag4_erat_data_cap == 1'b1) ? tlb_tag4_way_or[`waypos_usxwr:`waypos_usxwr + 5] : + tlb_erat_rel_q[`eratpos_usxwr:`eratpos_usxwr + 5]; + assign tlb_erat_rel_d[`eratpos_gs] = (tlb_tag4_erat_data_cap == 1'b1) ? tlb_tag4_way_or[`waypos_gs] : + tlb_erat_rel_q[`eratpos_gs]; + assign tlb_erat_rel_d[`eratpos_ts] = (tlb_tag4_erat_data_cap == 1'b1) ? tlb_tag4_way_or[`waypos_ts] : + tlb_erat_rel_q[`eratpos_ts]; + assign tlb_erat_rel_d[`eratpos_tid:`eratpos_tid + `PID_WIDTH_ERAT - 1] = (tlb_tag4_erat_data_cap == 1'b1) ? tlb_tag4_way_or[`waypos_tid + 6:`waypos_tid + 14 - 1] : + tlb_erat_rel_q[`eratpos_tid:`eratpos_tid + `PID_WIDTH_ERAT - 1]; + // clone is the derat side + assign tlb_erat_rel_clone_d[`eratpos_extclass:`eratpos_extclass + 1] = (tlb_tag4_erat_data_cap == 1'b1) ? tlb_tag4_way_or[`waypos_extclass:`waypos_extclass + 1] : + tlb_erat_rel_clone_q[`eratpos_extclass:`eratpos_extclass + 1]; + assign tlb_erat_rel_clone_d[`eratpos_wren] = ((tlb_tag4_erat_data_cap == 1'b1 & (tlb_tag4_q[`tagpos_type_ierat] == 1'b1 | tlb_tag4_q[`tagpos_type_derat] == 1'b1) & tlb_tag4_q[`tagpos_type_ptereload] == 1'b0 & tlb_tag4_wayhit_q[`TLB_WAYS] == 1'b1 & tlb_tag4_q[`tagpos_wq + 1] == 1'b0 & tlb_tag4_q[`tagpos_ind] == 1'b0 & multihit == 1'b0)) ? 1'b1 : + (tlb_tag4_erat_data_cap == 1'b1) ? 1'b0 : + tlb_erat_rel_clone_q[`eratpos_wren]; + assign tlb_erat_rel_clone_d[`eratpos_rpnrsvd:`eratpos_rpnrsvd + 3] = {4{1'b0}}; + assign tlb_erat_rel_clone_d[`eratpos_rpn:`eratpos_rpn + `RPN_WIDTH - 1] = (tlb_tag4_erat_data_cap == 1'b1) ? tlb_tag4_way_or[`waypos_rpn:`waypos_rpn + `RPN_WIDTH - 1] : + tlb_erat_rel_clone_q[`eratpos_rpn:`eratpos_rpn + `RPN_WIDTH - 1]; + assign tlb_erat_rel_clone_d[`eratpos_r:`eratpos_c] = (tlb_tag4_erat_data_cap == 1'b1) ? tlb_tag4_way_or[`waypos_rc:`waypos_rc + 1] : + tlb_erat_rel_clone_q[`eratpos_r:`eratpos_c]; + assign tlb_erat_rel_clone_d[`eratpos_relsoon] = derat_req_taken | ptereload_req_taken | tlb_tag0_type[0]; + assign tlb_erat_rel_clone_d[`eratpos_wlc:`eratpos_wlc + 1] = (tlb_tag4_erat_data_cap == 1'b1) ? tlb_tag4_way_or[`waypos_wlc:`waypos_wlc + 1] : + tlb_erat_rel_clone_q[`eratpos_wlc:`eratpos_wlc + 1]; + assign tlb_erat_rel_clone_d[`eratpos_resvattr] = (tlb_tag4_erat_data_cap == 1'b1) ? tlb_tag4_way_or[`waypos_resvattr] : + tlb_erat_rel_clone_q[`eratpos_resvattr]; + assign tlb_erat_rel_clone_d[`eratpos_vf] = (tlb_tag4_erat_data_cap == 1'b1) ? tlb_tag4_way_or[`waypos_vf] : + tlb_erat_rel_clone_q[`eratpos_vf]; + assign tlb_erat_rel_clone_d[`eratpos_ubits:`eratpos_ubits + 3] = (tlb_tag4_erat_data_cap == 1'b1) ? tlb_tag4_way_or[`waypos_ubits:`waypos_ubits + 3] : + tlb_erat_rel_clone_q[`eratpos_ubits:`eratpos_ubits + 3]; + assign tlb_erat_rel_clone_d[`eratpos_wimge:`eratpos_wimge + 4] = (tlb_tag4_erat_data_cap == 1'b1) ? tlb_tag4_way_or[`waypos_wimge:`waypos_wimge + 4] : + tlb_erat_rel_clone_q[`eratpos_wimge:`eratpos_wimge + 4]; + assign tlb_erat_rel_clone_d[`eratpos_usxwr:`eratpos_usxwr + 5] = (tlb_tag4_erat_data_cap == 1'b1) ? tlb_tag4_way_or[`waypos_usxwr:`waypos_usxwr + 5] : + tlb_erat_rel_clone_q[`eratpos_usxwr:`eratpos_usxwr + 5]; + assign tlb_erat_rel_clone_d[`eratpos_gs] = (tlb_tag4_erat_data_cap == 1'b1) ? tlb_tag4_way_or[`waypos_gs] : + tlb_erat_rel_clone_q[`eratpos_gs]; + assign tlb_erat_rel_clone_d[`eratpos_ts] = (tlb_tag4_erat_data_cap == 1'b1) ? tlb_tag4_way_or[`waypos_ts] : + tlb_erat_rel_clone_q[`eratpos_ts]; + assign tlb_erat_rel_clone_d[`eratpos_tid:`eratpos_tid + `PID_WIDTH_ERAT - 1] = (tlb_tag4_erat_data_cap == 1'b1) ? tlb_tag4_way_or[`waypos_tid + 6:`waypos_tid + 14 - 1] : + tlb_erat_rel_clone_q[`eratpos_tid:`eratpos_tid + `PID_WIDTH_ERAT - 1]; + assign tlb_tag4_erat_data_cap = (((tlb_tag4_q[`tagpos_type_ierat] == 1'b1 | tlb_tag4_q[`tagpos_type_derat] == 1'b1) & tlb_tag4_q[`tagpos_type_ptereload] == 1'b0 & tlb_tag4_q[`tagpos_ind] == 1'b0 & + (tlb_tag4_wayhit_q[`TLB_WAYS] == 1'b1 | |(tag4_parerr_q[0:4]) == 1'b1) & |((tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS-1] & (~tlb_ctl_tag4_flush))) == 1'b1)) ? 1'b1 : + (((tlb_tag4_q[`tagpos_type_ierat] == 1'b1 | tlb_tag4_q[`tagpos_type_derat] == 1'b1) & tlb_tag4_q[`tagpos_type_ptereload] == 1'b1 & + tlb_tag4_q[`tagpos_ind] == 1'b0 & |(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1)) ? 1'b1 : + 1'b0; + // page size 4b to 3b swizzles for erat reloads + assign erat_pgsize[0:2] = (tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_1GB) ? ERAT_PgSize_1GB : + (tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_16MB) ? ERAT_PgSize_16MB : + (tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_1MB) ? ERAT_PgSize_1MB : + (tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_64KB) ? ERAT_PgSize_64KB : + ERAT_PgSize_4KB; + // `tagpos_epn : natural := 0; + // `tagpos_pid : natural := 52; -- 14 bits + // `tagpos_is : natural := 66; + // `tagpos_class : natural := 68; + // `tagpos_state : natural := 70; -- state: 0:pr 1:gs 2:as 3:cm + // `tagpos_thdid : natural := 74; + // `tagpos_size : natural := 78; + // `tagpos_type : natural := 82; -- derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload + // `tagpos_lpid : natural := 90; + // `tagpos_ind : natural := 98; + // `tagpos_atsel : natural := 99; + // `tagpos_esel : natural := 100; + // `tagpos_hes : natural := 103; + // `tagpos_wq : natural := 104; + // `tagpos_lrat : natural := 106; + // `tagpos_pt : natural := 107; + // `tagpos_recform : natural := 108; + // `tagpos_endflag : natural := 109; + // the ierat response + // ierat threadwise valid + assign tlb_erat_val_d[0:3] = ((tlb_tag4_q[`tagpos_type_ierat] == 1'b1 & tlb_tag4_q[`tagpos_type_ptereload] == 1'b0 & tlb_tag4_q[`tagpos_ind] == 1'b0 & tlb_tag4_wayhit_q[`TLB_WAYS] == 1'b1 & |(tag4_parerr_q[0:4]) == 1'b0 & multihit == 1'b0 & |(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS-1] & (~tlb_ctl_tag4_flush)) == 1'b1)) ? (tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1] | ierat_tag4_dup_thdid[0:`THDID_WIDTH - 1]) : + ((tlb_tag4_q[`tagpos_type_ierat] == 1'b1 & tlb_tag4_q[`tagpos_type_ptereload] == 1'b0 & ((tlb_tag4_q[`tagpos_endflag] == 1'b1 & tlb_tag4_wayhit_q[`TLB_WAYS] == 1'b0) | |(tag4_parerr_q[0:4]) == 1'b1 | multihit == 1'b1) & |(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS-1] & (~tlb_ctl_tag4_flush)) == 1'b1)) ? tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1] : + ((tlb_tag4_q[`tagpos_type_ierat] == 1'b1 & tlb_tag4_q[`tagpos_type_ptereload] == 1'b1)) ? tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1] : + {4{1'b0}}; + assign tlb_erat_val_d[4] = ((tlb_tag4_q[`tagpos_type_ptereload] == 1'b0 & tlb_tag4_q[`tagpos_ind] == 1'b0 & tlb_tag4_wayhit_q[`TLB_WAYS] == 1'b1 & multihit == 1'b0 & |(tag4_parerr_q[0:4]) == 1'b0 & |(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS-1] & (~tlb_ctl_tag4_flush)) == 1'b1)) ? tlb_tag4_q[`tagpos_type_ierat] : + ((tlb_tag4_q[`tagpos_type_ptereload] == 1'b1 & |(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1)) ? tlb_tag4_q[`tagpos_type_ierat] : + 1'b0; + // the derat response + // derat threadwise valid + assign tlb_erat_val_d[5:8] = ((tlb_tag4_q[`tagpos_type_derat] == 1'b1 & tlb_tag4_q[`tagpos_type_ptereload] == 1'b0 & tlb_tag4_q[`tagpos_ind] == 1'b0 & tlb_tag4_wayhit_q[`TLB_WAYS] == 1'b1 & |(tag4_parerr_q[0:4]) == 1'b0 & multihit == 1'b0 & |(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS-1] & (~tlb_ctl_tag4_flush)) == 1'b1)) ? (tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1] | derat_tag4_dup_thdid[0:`THDID_WIDTH - 1]) : + ((tlb_tag4_q[`tagpos_type_derat] == 1'b1 & tlb_tag4_q[`tagpos_type_ptereload] == 1'b0 & ((tlb_tag4_q[`tagpos_endflag] == 1'b1 & tlb_tag4_wayhit_q[`TLB_WAYS] == 1'b0) | |(tag4_parerr_q[0:4]) == 1'b1 | multihit == 1'b1) & |(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS-1] & (~tlb_ctl_tag4_flush)) == 1'b1)) ? tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1] : + ((tlb_tag4_q[`tagpos_type_derat] == 1'b1 & tlb_tag4_q[`tagpos_type_ptereload] == 1'b1)) ? tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1] : + {4{1'b0}}; + assign tlb_erat_val_d[9] = ((tlb_tag4_q[`tagpos_type_ptereload] == 1'b0 & tlb_tag4_q[`tagpos_ind] == 1'b0 & tlb_tag4_wayhit_q[`TLB_WAYS] == 1'b1 & multihit == 1'b0 & |(tag4_parerr_q[0:4]) == 1'b0 & |(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS-1] & (~tlb_ctl_tag4_flush)) == 1'b1)) ? tlb_tag4_q[`tagpos_type_derat] : + ((tlb_tag4_q[`tagpos_type_ptereload] == 1'b1 & |(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1)) ? tlb_tag4_q[`tagpos_type_derat] : + 1'b0; + // `waypos_epn : natural := 0; + // `waypos_size : natural := 52; + // `waypos_thdid : natural := 56; + // `waypos_class : natural := 60; + // `waypos_extclass : natural := 62; + // `waypos_lpid : natural := 66; + // `waypos_xbit : natural := 84; + // `waypos_tstmode4k : natural := 85; + // `waypos_rpn : natural := 88; + // `waypos_rc : natural := 118; + // `waypos_wlc : natural := 120; + // `waypos_resvattr : natural := 122; + // `waypos_vf : natural := 123; + // `waypos_ind : natural := 124; + // `waypos_ubits : natural := 125; + // `waypos_wimge : natural := 129; + // `waypos_usxwr : natural := 134; + // `waypos_gs : natural := 140; + // `waypos_ts : natural := 141; + // `waypos_tid : natural := 144; -- 14 bits + // chosen tag4_way compares to erat requests from mmq_tlb_req for duplicate checking + assign ierat_req0_tag4_thdid_match = (|(tlb_tag4_way_or[`waypos_thdid:`waypos_thdid + `THDID_WIDTH - 1] & ierat_req0_thdid) == 1'b1) ? 1'b1 : + 1'b0; + assign ierat_req0_tag4_pid_match = ((tlb_tag4_way_or[`waypos_tid:`waypos_tid + `PID_WIDTH - 1] == ierat_req0_pid | |(tlb_tag4_way_or[`waypos_tid:`waypos_tid + `PID_WIDTH - 1]) == 1'b0)) ? 1'b1 : + 1'b0; + assign ierat_req0_tag4_as_match = ((tlb_tag4_way_or[`waypos_ts] == ierat_req0_as)) ? 1'b1 : + 1'b0; + assign ierat_req0_tag4_gs_match = ((tlb_tag4_way_or[`waypos_gs] == ierat_req0_gs)) ? 1'b1 : + 1'b0; + assign ierat_req0_tag4_epn_match = ((tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 1] == ierat_req0_epn[52 - `EPN_WIDTH:51] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_4KB) | (tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 5] == ierat_req0_epn[52 - `EPN_WIDTH:47] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_64KB) | (tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 9] == ierat_req0_epn[52 - `EPN_WIDTH:43] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_1MB) | (tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 13] == ierat_req0_epn[52 - `EPN_WIDTH:39] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_16MB) | (tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 19] == ierat_req0_epn[52 - `EPN_WIDTH:33] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_1GB)) ? 1'b1 : + 1'b0; + assign tlb_erat_dup_d[0] = ((ierat_req0_tag4_pid_match == 1'b1 & ierat_req0_tag4_as_match == 1'b1 & ierat_req0_tag4_gs_match == 1'b1 & ierat_req0_tag4_epn_match == 1'b1 & ierat_req0_tag4_thdid_match == 1'b1 & ierat_req0_valid == 1'b1 & (tlb_erat_dup_d[4] == 1'b0 & tlb_erat_dup_d[5] == 1'b1))) ? 1'b1 : + 1'b0; + assign ierat_req1_tag4_thdid_match = (|(tlb_tag4_way_or[`waypos_thdid:`waypos_thdid + `THDID_WIDTH - 1] & ierat_req1_thdid) == 1'b1) ? 1'b1 : + 1'b0; + assign ierat_req1_tag4_pid_match = ((tlb_tag4_way_or[`waypos_tid:`waypos_tid + `PID_WIDTH - 1] == ierat_req1_pid | |(tlb_tag4_way_or[`waypos_tid:`waypos_tid + `PID_WIDTH - 1]) == 1'b0)) ? 1'b1 : + 1'b0; + assign ierat_req1_tag4_as_match = ((tlb_tag4_way_or[`waypos_ts] == ierat_req1_as)) ? 1'b1 : + 1'b0; + assign ierat_req1_tag4_gs_match = ((tlb_tag4_way_or[`waypos_gs] == ierat_req1_gs)) ? 1'b1 : + 1'b0; + assign ierat_req1_tag4_epn_match = ((tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 1] == ierat_req1_epn[52 - `EPN_WIDTH:51] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_4KB) | (tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 5] == ierat_req1_epn[52 - `EPN_WIDTH:47] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_64KB) | (tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 9] == ierat_req1_epn[52 - `EPN_WIDTH:43] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_1MB) | (tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 13] == ierat_req1_epn[52 - `EPN_WIDTH:39] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_16MB) | (tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 19] == ierat_req1_epn[52 - `EPN_WIDTH:33] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_1GB)) ? 1'b1 : + 1'b0; + assign tlb_erat_dup_d[1] = ((ierat_req1_tag4_pid_match == 1'b1 & ierat_req1_tag4_as_match == 1'b1 & ierat_req1_tag4_gs_match == 1'b1 & ierat_req1_tag4_epn_match == 1'b1 & ierat_req1_tag4_thdid_match == 1'b1 & ierat_req1_valid == 1'b1 & (tlb_erat_dup_d[4] == 1'b0 & tlb_erat_dup_d[5] == 1'b1))) ? 1'b1 : + 1'b0; + assign ierat_req2_tag4_thdid_match = (|(tlb_tag4_way_or[`waypos_thdid:`waypos_thdid + `THDID_WIDTH - 1] & ierat_req2_thdid) == 1'b1) ? 1'b1 : + 1'b0; + assign ierat_req2_tag4_pid_match = ((tlb_tag4_way_or[`waypos_tid:`waypos_tid + `PID_WIDTH - 1] == ierat_req2_pid | |(tlb_tag4_way_or[`waypos_tid:`waypos_tid + `PID_WIDTH - 1]) == 1'b0)) ? 1'b1 : + 1'b0; + assign ierat_req2_tag4_as_match = ((tlb_tag4_way_or[`waypos_ts] == ierat_req2_as)) ? 1'b1 : + 1'b0; + assign ierat_req2_tag4_gs_match = ((tlb_tag4_way_or[`waypos_gs] == ierat_req2_gs)) ? 1'b1 : + 1'b0; + assign ierat_req2_tag4_epn_match = ((tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 1] == ierat_req2_epn[52 - `EPN_WIDTH:51] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_4KB) | (tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 5] == ierat_req2_epn[52 - `EPN_WIDTH:47] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_64KB) | (tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 9] == ierat_req2_epn[52 - `EPN_WIDTH:43] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_1MB) | (tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 13] == ierat_req2_epn[52 - `EPN_WIDTH:39] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_16MB) | (tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 19] == ierat_req2_epn[52 - `EPN_WIDTH:33] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_1GB)) ? 1'b1 : + 1'b0; + assign tlb_erat_dup_d[2] = ((ierat_req2_tag4_pid_match == 1'b1 & ierat_req2_tag4_as_match == 1'b1 & ierat_req2_tag4_gs_match == 1'b1 & ierat_req2_tag4_epn_match == 1'b1 & ierat_req2_tag4_thdid_match == 1'b1 & ierat_req2_valid == 1'b1 & (tlb_erat_dup_d[4] == 1'b0 & tlb_erat_dup_d[5] == 1'b1))) ? 1'b1 : + 1'b0; + assign ierat_req3_tag4_thdid_match = (|(tlb_tag4_way_or[`waypos_thdid:`waypos_thdid + `THDID_WIDTH - 1] & ierat_req3_thdid) == 1'b1) ? 1'b1 : + 1'b0; + assign ierat_req3_tag4_pid_match = ((tlb_tag4_way_or[`waypos_tid:`waypos_tid + `PID_WIDTH - 1] == ierat_req3_pid | |(tlb_tag4_way_or[`waypos_tid:`waypos_tid + `PID_WIDTH - 1]) == 1'b0)) ? 1'b1 : + 1'b0; + assign ierat_req3_tag4_as_match = ((tlb_tag4_way_or[`waypos_ts] == ierat_req3_as)) ? 1'b1 : + 1'b0; + assign ierat_req3_tag4_gs_match = ((tlb_tag4_way_or[`waypos_gs] == ierat_req3_gs)) ? 1'b1 : + 1'b0; + assign ierat_req3_tag4_epn_match = ((tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 1] == ierat_req3_epn[52 - `EPN_WIDTH:51] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_4KB) | (tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 5] == ierat_req3_epn[52 - `EPN_WIDTH:47] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_64KB) | (tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 9] == ierat_req3_epn[52 - `EPN_WIDTH:43] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_1MB) | (tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 13] == ierat_req3_epn[52 - `EPN_WIDTH:39] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_16MB) | (tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 19] == ierat_req3_epn[52 - `EPN_WIDTH:33] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_1GB)) ? 1'b1 : + 1'b0; + assign tlb_erat_dup_d[3] = ((ierat_req3_tag4_pid_match == 1'b1 & ierat_req3_tag4_as_match == 1'b1 & ierat_req3_tag4_gs_match == 1'b1 & ierat_req3_tag4_epn_match == 1'b1 & ierat_req3_tag4_thdid_match == 1'b1 & ierat_req3_valid == 1'b1 & (tlb_erat_dup_d[4] == 1'b0 & tlb_erat_dup_d[5] == 1'b1))) ? 1'b1 : + 1'b0; + assign ierat_iu4_tag4_thdid_match = (|(tlb_tag4_way_or[`waypos_thdid:`waypos_thdid + `THDID_WIDTH - 1] & ierat_iu4_thdid) == 1'b1) ? 1'b1 : + 1'b0; + assign ierat_iu4_tag4_lpid_match = ((tlb_tag4_way_or[`waypos_lpid:`waypos_lpid + `LPID_WIDTH - 1] == lpidr | |(tlb_tag4_way_or[`waypos_lpid:`waypos_lpid + `LPID_WIDTH - 1]) == 1'b0)) ? 1'b1 : + 1'b0; + assign ierat_iu4_tag4_pid_match = ((tlb_tag4_way_or[`waypos_tid:`waypos_tid + `PID_WIDTH - 1] == ierat_iu4_pid | |(tlb_tag4_way_or[`waypos_tid:`waypos_tid + `PID_WIDTH - 1]) == 1'b0)) ? 1'b1 : + 1'b0; + assign ierat_iu4_tag4_as_match = ((tlb_tag4_way_or[`waypos_ts] == ierat_iu4_as)) ? 1'b1 : + 1'b0; + assign ierat_iu4_tag4_gs_match = ((tlb_tag4_way_or[`waypos_gs] == ierat_iu4_gs)) ? 1'b1 : + 1'b0; + assign ierat_iu4_tag4_epn_match = ((tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 1] == ierat_iu4_epn[52 - `EPN_WIDTH:51] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_4KB) | (tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 5] == ierat_iu4_epn[52 - `EPN_WIDTH:47] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_64KB) | (tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 9] == ierat_iu4_epn[52 - `EPN_WIDTH:43] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_1MB) | (tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 13] == ierat_iu4_epn[52 - `EPN_WIDTH:39] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_16MB) | (tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 19] == ierat_iu4_epn[52 - `EPN_WIDTH:33] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_1GB)) ? 1'b1 : + 1'b0; + assign derat_req0_tag4_thdid_match = (|(tlb_tag4_way_or[`waypos_thdid:`waypos_thdid + `THDID_WIDTH - 1] & derat_req0_thdid) == 1'b1) ? 1'b1 : + 1'b0; + assign derat_req0_tag4_lpid_match = ((tlb_tag4_way_or[`waypos_lpid:`waypos_lpid + `LPID_WIDTH - 1] == derat_req0_lpid | |(tlb_tag4_way_or[`waypos_lpid:`waypos_lpid + `LPID_WIDTH - 1]) == 1'b0)) ? 1'b1 : + 1'b0; + assign derat_req0_tag4_pid_match = ((tlb_tag4_way_or[`waypos_tid:`waypos_tid + `PID_WIDTH - 1] == derat_req0_pid | |(tlb_tag4_way_or[`waypos_tid:`waypos_tid + `PID_WIDTH - 1]) == 1'b0)) ? 1'b1 : + 1'b0; + assign derat_req0_tag4_as_match = ((tlb_tag4_way_or[`waypos_ts] == derat_req0_as)) ? 1'b1 : + 1'b0; + assign derat_req0_tag4_gs_match = ((tlb_tag4_way_or[`waypos_gs] == derat_req0_gs)) ? 1'b1 : + 1'b0; + assign derat_req0_tag4_epn_match = ((tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 1] == derat_req0_epn[52 - `EPN_WIDTH:51] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_4KB) | (tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 5] == derat_req0_epn[52 - `EPN_WIDTH:47] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_64KB) | (tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 9] == derat_req0_epn[52 - `EPN_WIDTH:43] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_1MB) | (tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 13] == derat_req0_epn[52 - `EPN_WIDTH:39] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_16MB) | (tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 19] == derat_req0_epn[52 - `EPN_WIDTH:33] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_1GB)) ? 1'b1 : + 1'b0; + assign tlb_erat_dup_d[10] = ((derat_req0_tag4_lpid_match == 1'b1 & derat_req0_tag4_pid_match == 1'b1 & derat_req0_tag4_as_match == 1'b1 & derat_req0_tag4_gs_match == 1'b1 & derat_req0_tag4_epn_match == 1'b1 & derat_req0_tag4_thdid_match == 1'b1 & derat_req0_valid == 1'b1)) ? 1'b1 : + 1'b0; + assign derat_req1_tag4_thdid_match = (|(tlb_tag4_way_or[`waypos_thdid:`waypos_thdid + `THDID_WIDTH - 1] & derat_req1_thdid) == 1'b1) ? 1'b1 : + 1'b0; + assign derat_req1_tag4_lpid_match = ((tlb_tag4_way_or[`waypos_lpid:`waypos_lpid + `LPID_WIDTH - 1] == derat_req1_lpid | |(tlb_tag4_way_or[`waypos_lpid:`waypos_lpid + `LPID_WIDTH - 1]) == 1'b0)) ? 1'b1 : + 1'b0; + assign derat_req1_tag4_pid_match = ((tlb_tag4_way_or[`waypos_tid:`waypos_tid + `PID_WIDTH - 1] == derat_req1_pid | |(tlb_tag4_way_or[`waypos_tid:`waypos_tid + `PID_WIDTH - 1]) == 1'b0)) ? 1'b1 : + 1'b0; + assign derat_req1_tag4_as_match = ((tlb_tag4_way_or[`waypos_ts] == derat_req1_as)) ? 1'b1 : + 1'b0; + assign derat_req1_tag4_gs_match = ((tlb_tag4_way_or[`waypos_gs] == derat_req1_gs)) ? 1'b1 : + 1'b0; + assign derat_req1_tag4_epn_match = ((tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 1] == derat_req1_epn[52 - `EPN_WIDTH:51] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_4KB) | (tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 5] == derat_req1_epn[52 - `EPN_WIDTH:47] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_64KB) | (tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 9] == derat_req1_epn[52 - `EPN_WIDTH:43] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_1MB) | (tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 13] == derat_req1_epn[52 - `EPN_WIDTH:39] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_16MB) | (tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 19] == derat_req1_epn[52 - `EPN_WIDTH:33] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_1GB)) ? 1'b1 : + 1'b0; + assign tlb_erat_dup_d[11] = ((derat_req1_tag4_lpid_match == 1'b1 & derat_req1_tag4_pid_match == 1'b1 & derat_req1_tag4_as_match == 1'b1 & derat_req1_tag4_gs_match == 1'b1 & derat_req1_tag4_epn_match == 1'b1 & derat_req1_tag4_thdid_match == 1'b1 & derat_req1_valid == 1'b1)) ? 1'b1 : + 1'b0; + assign derat_req2_tag4_thdid_match = (|(tlb_tag4_way_or[`waypos_thdid:`waypos_thdid + `THDID_WIDTH - 1] & derat_req2_thdid) == 1'b1) ? 1'b1 : + 1'b0; + assign derat_req2_tag4_lpid_match = ((tlb_tag4_way_or[`waypos_lpid:`waypos_lpid + `LPID_WIDTH - 1] == derat_req2_lpid | |(tlb_tag4_way_or[`waypos_lpid:`waypos_lpid + `LPID_WIDTH - 1]) == 1'b0)) ? 1'b1 : + 1'b0; + assign derat_req2_tag4_pid_match = ((tlb_tag4_way_or[`waypos_tid:`waypos_tid + `PID_WIDTH - 1] == derat_req2_pid | |(tlb_tag4_way_or[`waypos_tid:`waypos_tid + `PID_WIDTH - 1]) == 1'b0)) ? 1'b1 : + 1'b0; + assign derat_req2_tag4_as_match = ((tlb_tag4_way_or[`waypos_ts] == derat_req2_as)) ? 1'b1 : + 1'b0; + assign derat_req2_tag4_gs_match = ((tlb_tag4_way_or[`waypos_gs] == derat_req2_gs)) ? 1'b1 : + 1'b0; + assign derat_req2_tag4_epn_match = ((tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 1] == derat_req2_epn[52 - `EPN_WIDTH:51] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_4KB) | (tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 5] == derat_req2_epn[52 - `EPN_WIDTH:47] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_64KB) | (tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 9] == derat_req2_epn[52 - `EPN_WIDTH:43] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_1MB) | (tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 13] == derat_req2_epn[52 - `EPN_WIDTH:39] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_16MB) | (tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 19] == derat_req2_epn[52 - `EPN_WIDTH:33] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_1GB)) ? 1'b1 : + 1'b0; + assign tlb_erat_dup_d[12] = ((derat_req2_tag4_lpid_match == 1'b1 & derat_req2_tag4_pid_match == 1'b1 & derat_req2_tag4_as_match == 1'b1 & derat_req2_tag4_gs_match == 1'b1 & derat_req2_tag4_epn_match == 1'b1 & derat_req2_tag4_thdid_match == 1'b1 & derat_req2_valid == 1'b1)) ? 1'b1 : + 1'b0; + assign derat_req3_tag4_thdid_match = (|(tlb_tag4_way_or[`waypos_thdid:`waypos_thdid + `THDID_WIDTH - 1] & derat_req3_thdid) == 1'b1) ? 1'b1 : + 1'b0; + assign derat_req3_tag4_lpid_match = ((tlb_tag4_way_or[`waypos_lpid:`waypos_lpid + `LPID_WIDTH - 1] == derat_req3_lpid | |(tlb_tag4_way_or[`waypos_lpid:`waypos_lpid + `LPID_WIDTH - 1]) == 1'b0)) ? 1'b1 : + 1'b0; + assign derat_req3_tag4_pid_match = ((tlb_tag4_way_or[`waypos_tid:`waypos_tid + `PID_WIDTH - 1] == derat_req3_pid | |(tlb_tag4_way_or[`waypos_tid:`waypos_tid + `PID_WIDTH - 1]) == 1'b0)) ? 1'b1 : + 1'b0; + assign derat_req3_tag4_as_match = ((tlb_tag4_way_or[`waypos_ts] == derat_req3_as)) ? 1'b1 : + 1'b0; + assign derat_req3_tag4_gs_match = ((tlb_tag4_way_or[`waypos_gs] == derat_req3_gs)) ? 1'b1 : + 1'b0; + assign derat_req3_tag4_epn_match = ((tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 1] == derat_req3_epn[52 - `EPN_WIDTH:51] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_4KB) | (tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 5] == derat_req3_epn[52 - `EPN_WIDTH:47] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_64KB) | (tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 9] == derat_req3_epn[52 - `EPN_WIDTH:43] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_1MB) | (tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 13] == derat_req3_epn[52 - `EPN_WIDTH:39] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_16MB) | (tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 19] == derat_req3_epn[52 - `EPN_WIDTH:33] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_1GB)) ? 1'b1 : + 1'b0; + assign tlb_erat_dup_d[13] = ((derat_req3_tag4_lpid_match == 1'b1 & derat_req3_tag4_pid_match == 1'b1 & derat_req3_tag4_as_match == 1'b1 & derat_req3_tag4_gs_match == 1'b1 & derat_req3_tag4_epn_match == 1'b1 & derat_req3_tag4_thdid_match == 1'b1 & derat_req3_valid == 1'b1)) ? 1'b1 : + 1'b0; + assign derat_ex5_tag4_thdid_match = (|(tlb_tag4_way_or[`waypos_thdid:`waypos_thdid + `THDID_WIDTH - 1] & derat_ex5_thdid) == 1'b1) ? 1'b1 : + 1'b0; + assign derat_ex5_tag4_lpid_match = ((tlb_tag4_way_or[`waypos_lpid:`waypos_lpid + `LPID_WIDTH - 1] == derat_ex5_lpid | |(tlb_tag4_way_or[`waypos_lpid:`waypos_lpid + `LPID_WIDTH - 1]) == 1'b0)) ? 1'b1 : + 1'b0; + assign derat_ex5_tag4_pid_match = ((tlb_tag4_way_or[`waypos_tid:`waypos_tid + `PID_WIDTH - 1] == derat_ex5_pid | |(tlb_tag4_way_or[`waypos_tid:`waypos_tid + `PID_WIDTH - 1]) == 1'b0)) ? 1'b1 : + 1'b0; + assign derat_ex5_tag4_as_match = ((tlb_tag4_way_or[`waypos_ts] == derat_ex5_as)) ? 1'b1 : + 1'b0; + assign derat_ex5_tag4_gs_match = ((tlb_tag4_way_or[`waypos_gs] == derat_ex5_gs)) ? 1'b1 : + 1'b0; + assign derat_ex5_tag4_epn_match = ((tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 1] == derat_ex5_epn[52 - `EPN_WIDTH:51] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_4KB) | (tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 5] == derat_ex5_epn[52 - `EPN_WIDTH:47] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_64KB) | (tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 9] == derat_ex5_epn[52 - `EPN_WIDTH:43] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_1MB) | (tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 13] == derat_ex5_epn[52 - `EPN_WIDTH:39] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_16MB) | (tlb_tag4_way_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 19] == derat_ex5_epn[52 - `EPN_WIDTH:33] & tlb_tag4_way_or[`waypos_size:`waypos_size + 3] == TLB_PgSize_1GB)) ? 1'b1 : + 1'b0; + // tlb_cmp_ierat_dup_val bits 0:3 are req_tag5_match, 4 is tag5 hit_reload, 5 is stretched hit_reload, 6 is ierat iu5 stage dup, 7:9 counter + // hit pulse to ierat + assign tlb_erat_dup_d[4] = ((tlb_tag4_q[`tagpos_type_ptereload] == 1'b0 & tlb_tag4_way_or[`waypos_ind] == 1'b0 & tlb_tag4_wayhit_q[`TLB_WAYS] == 1'b1 & multihit == 1'b0 & tlb_tag4_q[`tagpos_wq + 1] == 1'b0 & |(tag4_parerr_q[0:4]) == 1'b0)) ? tlb_tag4_q[`tagpos_type_ierat] : + 1'b0; + // extended duplicate strobe to ierat + assign tlb_erat_dup_d[5] = ((tlb_erat_dup_d[4] == 1'b1 | tlb_erat_dup_q[4] == 1'b1)) ? 1'b1 : + ((tlb_erat_dup_q[20] == 1'b1 | tlb_erat_dup_q[7:9] != 3'b000)) ? 1'b1 : + 1'b0; + // ierat duplicate in iu4 stage + assign tlb_erat_dup_d[6] = ((ierat_iu4_tag4_lpid_match == 1'b1 & ierat_iu4_tag4_pid_match == 1'b1 & ierat_iu4_tag4_as_match == 1'b1 & ierat_iu4_tag4_gs_match == 1'b1 & ierat_iu4_tag4_epn_match == 1'b1 & ierat_iu4_tag4_thdid_match == 1'b1 & ierat_iu4_valid == 1'b1 & |(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1)) ? tlb_tag4_q[`tagpos_type_ierat] : + 1'b0; + // ierat duplicate counter + assign tlb_erat_dup_d[7:9] = ((((tlb_erat_dup_q[4] == 1'b1 & tlb_erat_dup_q[20] == 1'b0) | tlb_erat_dup_q[20] == 1'b1) & tlb_erat_dup_q[7:9] == 3'b000)) ? 3'b001 : + (tlb_erat_dup_q[7:9] == 3'b001) ? 3'b010 : + (tlb_erat_dup_q[7:9] == 3'b010) ? 3'b011 : + (tlb_erat_dup_q[7:9] == 3'b011) ? 3'b100 : + (tlb_erat_dup_q[7:9] == 3'b100) ? 3'b101 : + (tlb_erat_dup_q[7:9] == 3'b101) ? 3'b110 : + (tlb_erat_dup_q[7:9] == 3'b110) ? 3'b111 : + (tlb_erat_dup_q[7:9] == 3'b111) ? 3'b000 : + tlb_erat_dup_q[7:9]; + assign tlb_erat_dup_d[20] = ((tlb_erat_dup_q[20] == 1'b0 & tlb_erat_dup_q[7:9] == 3'b111)) ? 1'b1 : + ((tlb_erat_dup_q[20] == 1'b1 & tlb_erat_dup_q[7:9] == 3'b111)) ? 1'b0 : + tlb_erat_dup_q[20]; + // tlb_cmp_ierat_dup_val bits 10:13 are req_tag5_match, 14 is tag5 hit_reload, 15 is stretched hit_reload, 16 is ierat iu5 stage dup, 17:19 counter + // hit pulse to derat + assign tlb_erat_dup_d[14] = ((tlb_tag4_q[`tagpos_type_ptereload] == 1'b0 & tlb_tag4_way_or[`waypos_ind] == 1'b0 & tlb_tag4_wayhit_q[`TLB_WAYS] == 1'b1 & multihit == 1'b0 & tlb_tag4_q[`tagpos_wq + 1] == 1'b0 & |(tag4_parerr_q[0:4]) == 1'b0)) ? tlb_tag4_q[`tagpos_type_derat] : + 1'b0; + // extended duplicate strobe to derat + assign tlb_erat_dup_d[15] = ((tlb_erat_dup_d[14] == 1'b1 | tlb_erat_dup_q[14] == 1'b1)) ? 1'b1 : + ((tlb_erat_dup_q[21] == 1'b1 | tlb_erat_dup_q[17:19] != 3'b000)) ? 1'b1 : + 1'b0; + // derat duplicate in ex5 stage + assign tlb_erat_dup_d[16] = ((derat_ex5_tag4_lpid_match == 1'b1 & derat_ex5_tag4_pid_match == 1'b1 & derat_ex5_tag4_as_match == 1'b1 & derat_ex5_tag4_gs_match == 1'b1 & derat_ex5_tag4_epn_match == 1'b1 & derat_ex5_tag4_thdid_match == 1'b1 & derat_ex5_valid == 1'b1 & |(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1)) ? tlb_tag4_q[`tagpos_type_derat] : + 1'b0; + // derat duplicate hit counter + assign tlb_erat_dup_d[17:19] = ((((tlb_erat_dup_q[14] == 1'b1 & tlb_erat_dup_q[21] == 1'b0) | tlb_erat_dup_q[21] == 1'b1) & tlb_erat_dup_q[17:19] == 3'b000)) ? 3'b001 : + (tlb_erat_dup_q[17:19] == 3'b001) ? 3'b010 : + (tlb_erat_dup_q[17:19] == 3'b010) ? 3'b011 : + (tlb_erat_dup_q[17:19] == 3'b011) ? 3'b100 : + (tlb_erat_dup_q[17:19] == 3'b100) ? 3'b101 : + (tlb_erat_dup_q[17:19] == 3'b101) ? 3'b110 : + (tlb_erat_dup_q[17:19] == 3'b110) ? 3'b111 : + (tlb_erat_dup_q[17:19] == 3'b111) ? 3'b000 : + tlb_erat_dup_q[17:19]; + assign tlb_erat_dup_d[21] = ((tlb_erat_dup_q[21] == 1'b0 & tlb_erat_dup_q[17:19] == 3'b111)) ? 1'b1 : + ((tlb_erat_dup_q[21] == 1'b1 & tlb_erat_dup_q[17:19] == 3'b111)) ? 1'b0 : + tlb_erat_dup_q[21]; + // used in erat reload thdid to invalidate existing duplicates + assign ierat_tag4_dup_thdid = ( {`THDID_WIDTH{tlb_erat_dup_d[0]}} & ierat_req0_thdid[0:`THDID_WIDTH - 1] & {`THDID_WIDTH{(~tlb_tag4_q[`tagpos_wq + 1])}} ) | + ( {`THDID_WIDTH{tlb_erat_dup_d[1]}} & ierat_req1_thdid[0:`THDID_WIDTH - 1] & {`THDID_WIDTH{(~tlb_tag4_q[`tagpos_wq + 1])}} ) | + ( {`THDID_WIDTH{tlb_erat_dup_d[2]}} & ierat_req2_thdid[0:`THDID_WIDTH - 1] & {`THDID_WIDTH{(~tlb_tag4_q[`tagpos_wq + 1])}} ) | + ( {`THDID_WIDTH{tlb_erat_dup_d[3]}} & ierat_req3_thdid[0:`THDID_WIDTH - 1] & {`THDID_WIDTH{(~tlb_tag4_q[`tagpos_wq + 1])}} ); + + assign derat_tag4_dup_thdid = ( {`THDID_WIDTH{tlb_erat_dup_d[10]}} & derat_req0_thdid[0:`THDID_WIDTH - 1] & {`THDID_WIDTH{(~tlb_tag4_q[`tagpos_wq + 1])}} ) | + ( {`THDID_WIDTH{tlb_erat_dup_d[11]}} & derat_req1_thdid[0:`THDID_WIDTH - 1] & {`THDID_WIDTH{(~tlb_tag4_q[`tagpos_wq + 1])}} ) | + ( {`THDID_WIDTH{tlb_erat_dup_d[12]}} & derat_req2_thdid[0:`THDID_WIDTH - 1] & {`THDID_WIDTH{(~tlb_tag4_q[`tagpos_wq + 1])}} ) | + ( {`THDID_WIDTH{tlb_erat_dup_d[13]}} & derat_req3_thdid[0:`THDID_WIDTH - 1] & {`THDID_WIDTH{(~tlb_tag4_q[`tagpos_wq + 1])}} ); + + assign derat_tag4_dup_emq = ( {`THDID_WIDTH{tlb_erat_dup_d[10]}} & derat_req0_emq[0:`THDID_WIDTH - 1] & {`THDID_WIDTH{(~tlb_tag4_q[`tagpos_wq + 1])}} ) | + ( {`THDID_WIDTH{tlb_erat_dup_d[11]}} & derat_req1_emq[0:`THDID_WIDTH - 1] & {`THDID_WIDTH{(~tlb_tag4_q[`tagpos_wq + 1])}} ) | + ( {`THDID_WIDTH{tlb_erat_dup_d[12]}} & derat_req2_emq[0:`THDID_WIDTH - 1] & {`THDID_WIDTH{(~tlb_tag4_q[`tagpos_wq + 1])}} ) | + ( {`THDID_WIDTH{tlb_erat_dup_d[13]}} & derat_req3_emq[0:`THDID_WIDTH - 1] & {`THDID_WIDTH{(~tlb_tag4_q[`tagpos_wq + 1])}} ); + + assign tlb_tag4_epcr_dgtmi = |(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS-1] & xu_mm_epcr_dgtmi); + + assign tlb_tag4_size_not_supp = ( tlb_tag4_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_4KB | tlb_tag4_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_64KB | + tlb_tag4_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_1MB | tlb_tag4_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_16MB | + tlb_tag4_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_1GB | + (tlb_tag4_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_256MB & tlb_tag4_q[`tagpos_ind] == 1'b1) ) ? 1'b0 : + 1'b1; + + // tell the XU that the derat miss is done, and release the thread hold(s) + assign eratmiss_done_d = tlb_erat_val_q[0:`MM_THREADS-1] | tlb_erat_val_q[5:5 + `MM_THREADS-1]; + + // tell the XU that the derat request missed in the TLB + assign tlb_miss_d = ( ((tlb_tag4_q[`tagpos_type_ierat] == 1'b1 | tlb_tag4_q[`tagpos_type_derat] == 1'b1) & tlb_tag4_q[`tagpos_type_ptereload] == 1'b0 & tlb_tag4_q[`tagpos_endflag] == 1'b1 & + |(tlb_tag4_wayhit_q[0:`TLB_WAYS - 1]) == 1'b0 & tlb_tag4_q[`tagpos_nonspec] == 1'b1 & |(tag4_parerr_q[0:4]) == 1'b0) ) ? tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] : + {`MM_THREADS{1'b0}}; + + + // Event | Exceptions + // | PT fault | TLB Inelig | LRAT miss + //-------------------------------------------------------- + // tlbwe | - | hv_priv=1 | lrat_miss=1 + // | | tlbi=1 | esr_pt=0 + // | | esr_pt=0 | + //-------------------------------------------------------- + // ptereload | DSI | DSI | lrat_miss=1 + // (data) | pt_fault=1 | tlbi=1 | esr_pt=1 + // | PT=1 | esr_pt=0 ? | esr_data=1 + // | | | esr_epid=class(0) + // | | | esr_st=class(1) + //-------------------------------------------------------- + // ptereload | ISI | ISI | lrat_miss=1 + // (inst) | pt_fault=1 | tlbi=1 | esr_pt=1 + // | PT=1 | esr_pt=0 ? | esr_data=0 + //-------------------------------------------------------- + // unused `tagpos_is def is mas1_v, mas1_iprot for tlbwe, and is pte.valid & 0 for ptereloads + assign tlb_inelig_d = ((tlb_tag4_q[`tagpos_type_ptereload] == 1'b1 & tlb_tag4_q[`tagpos_is] == 1'b1 & lru_tag4_dataout_q[0:3] == 4'b1111 & lru_tag4_dataout_q[8:11] == 4'b1111) | + (tlb_tag4_q[`tagpos_type_ptereload] == 1'b1 & tlb_tag4_q[`tagpos_is] == 1'b1 & tlb_tag4_size_not_supp == 1'b1) | + (tlb_tag4_q[`tagpos_type_ptereload] == 1'b1 & tlb_tag4_q[`tagpos_is] == 1'b1 & tlb_tag4_q[`tagpos_pt] == 1'b0)) ? tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] : + {`MM_THREADS{1'b0}}; + + assign lrat_miss_d = ((((|(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] & tlb_resv_match_vec) == 1'b1 & tlb_tag4_q[`tagpos_wq:`tagpos_wq + 1] == 2'b01 & mmucfg_twc == 1'b1) | tlb_tag4_q[`tagpos_wq:`tagpos_wq + 1] == 2'b00 | tlb_tag4_q[`tagpos_wq:`tagpos_wq + 1] == 2'b11) & + tlb_tag4_q[`tagpos_type_tlbwe] == 1'b1 & tlb_tag4_q[`tagpos_gs] == 1'b1 & tlb_tag4_q[`tagpos_pr] == 1'b0 & tlb_tag4_epcr_dgtmi == 1'b0 & + mmucfg_lrat == 1'b1 & tlb_tag4_q[`tagpos_is] == 1'b1 & lrat_tag4_hit_status[0:3] != 4'b1100)) ? (tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS-1] & (~(tlb_ctl_tag4_flush))) : + ((tlb_tag4_q[`tagpos_type_ptereload] == 1'b1 & tlb_tag4_q[`tagpos_gs] == 1'b1 & mmucfg_lrat == 1'b1 & tlb_tag4_q[`tagpos_is] == 1'b1 & + lrat_tag4_hit_status[0:3] != 4'b1100 & tlb_tag4_q[`tagpos_wq:`tagpos_wq + 1] == 2'b10 & tlb_tag4_q[`tagpos_pt] == 1'b1)) ? tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS-1] : + {`MM_THREADS{1'b0}}; + + assign pt_fault_d = ((tlb_tag4_q[`tagpos_type_ptereload] == 1'b1 & tlb_tag4_q[`tagpos_is] == 1'b0 & + tlb_tag4_q[`tagpos_wq:`tagpos_wq + 1] == 2'b10 & tlb_tag4_q[`tagpos_pt] == 1'b1)) ? tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] : + {`MM_THREADS{1'b0}}; + + // unused `tagpos_is def is mas1_v, mas1_iprot for tlbwe, and is (pte.valid & 0) for ptereloads + // E.HV Privilege exceptions: + // 1. guest sup executes tlbre, tlbsx, tlbivax, eratre, eratwe, eratsx, eratilx, or erativax (xu_cpl handles) + // 2. guest sup executes mtspr or mfspr to a hv priviledged spr (xu_cpl handles) + // 3. guest sup executes tlbwe, tlbsrx, or tlbilx with EPCR DGTMI =1 (xu_cpl handles) + // 4. guest sup executes cache locking op when MSRP UCLEP =1 (xu_cpl handles) + // 5. guest sup tlbwe when TLB0CFG GTWE =0 + // 6. guest sup tlbwe when MMUCFG LRAT =0 + // 7. guest sup tlbwe when MAS0 HES =1 and TLBE V =1 and TLBE IPROT =1 and (MAS0 WQ =00 or MAS0 WQ =11 or (MAS0 WQ =01 and resv. exists)), + // except when write cond. not allowed by reservation is impl. depend. + // 8. guest sup tlbwe when MAS0 HES =1 and MAS1 IPROT =1 and(MAS0 WQ =00 or MAS0 WQ =11 or (MAS0 WQ =01 and resv. exists)), + // except when write cond. not allowed by reservation is impl. depend. + // 9. guest sup tlbwe when MAS0 HES =0 and MAS0 WQ /=10 + // 10. guest sup tlbwe when MAS0 HES =1 and MAS1 V =0 ??? -> random lru way invalidates allowed by current 2.06 ISA + // ..this is a possible security hole..FSL considering RFC to allow hvpriv except + // 11. guest sup tlbilx with MAS5 SGS =0 ??? -> should be protected via mas5 and mas8 are hv priv spr's + + assign hv_priv_d = ( (tlb_tag4_q[`tagpos_type_tlbwe] == 1'b1 & tlb_tag4_q[`tagpos_gs] == 1'b1 & tlb_tag4_q[`tagpos_pr] == 1'b0 & tlb0cfg_gtwe == 1'b0) | + (tlb_tag4_q[`tagpos_type_tlbwe] == 1'b1 & tlb_tag4_q[`tagpos_gs] == 1'b1 & tlb_tag4_q[`tagpos_pr] == 1'b0 & mmucfg_lrat == 1'b0) | + + ( tlb_tag4_q[`tagpos_type_tlbwe] == 1'b1 & tlb_tag4_q[`tagpos_gs] == 1'b1 & tlb_tag4_q[`tagpos_pr] == 1'b0 & tlb_tag4_q[`tagpos_hes] == 1'b1 & + (tlb_tag4_q[`tagpos_wq:`tagpos_wq + 1] == 2'b00 | tlb_tag4_q[`tagpos_wq:`tagpos_wq + 1] == 2'b11 | + (tlb_tag4_q[`tagpos_wq:`tagpos_wq + 1] == 2'b01 & (|(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] & tlb_resv_match_vec) == 1'b1))) & + ((lru_tag4_dataout_q[0] == 1'b1 & lru_tag4_dataout_q[4:5] == 2'b00 & lru_tag4_dataout_q[8] == 1'b1) | + (lru_tag4_dataout_q[1] == 1'b1 & lru_tag4_dataout_q[4:5] == 2'b01 & lru_tag4_dataout_q[9] == 1'b1) | + (lru_tag4_dataout_q[2] == 1'b1 & lru_tag4_dataout_q[4] == 1'b1 & lru_tag4_dataout_q[6] == 1'b0 & lru_tag4_dataout_q[10] == 1'b1) | + (lru_tag4_dataout_q[3] == 1'b1 & lru_tag4_dataout_q[4] == 1'b1 & lru_tag4_dataout_q[6] == 1'b1 & lru_tag4_dataout_q[11] == 1'b1)) ) | + + ( tlb_tag4_q[`tagpos_type_tlbwe] == 1'b1 & tlb_tag4_q[`tagpos_gs] == 1'b1 & tlb_tag4_q[`tagpos_pr] == 1'b0 & tlb_tag4_q[`tagpos_hes] == 1'b1 & + (tlb_tag4_q[`tagpos_wq:`tagpos_wq + 1] == 2'b00 | tlb_tag4_q[`tagpos_wq:`tagpos_wq + 1] == 2'b11 | + (tlb_tag4_q[`tagpos_wq:`tagpos_wq + 1] == 2'b01 & (|(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] & tlb_resv_match_vec) == 1'b1))) & + tlb_tag4_q[`tagpos_is + 1] == 1'b1 ) | + + (tlb_tag4_q[`tagpos_type_tlbwe] == 1'b1 & tlb_tag4_q[`tagpos_gs] == 1'b1 & tlb_tag4_q[`tagpos_pr] == 1'b0 & + tlb_tag4_q[`tagpos_hes] == 1'b0 & tlb_tag4_q[`tagpos_wq:`tagpos_wq + 1] != 2'b10) ) ? (tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] & (~(tlb_ctl_tag4_flush))) : + {`MM_THREADS{1'b0}}; + + assign esr_pt_d = (pt_fault_d | lrat_miss_d) & {`MM_THREADS{tlb_tag4_q[`tagpos_type_ptereload]}}; + assign esr_data_d = (tlb_miss_d | pt_fault_d | tlb_inelig_d | lrat_miss_d) & {`MM_THREADS{tlb_tag4_q[`tagpos_type_derat]}}; + assign esr_st_d = (tlb_miss_d | pt_fault_d | tlb_inelig_d | lrat_miss_d) & {`MM_THREADS{tlb_tag4_q[`tagpos_type_derat]}} & {`MM_THREADS{tlb_tag4_q[`tagpos_class + 1]}}; + assign esr_epid_d = (tlb_miss_d | pt_fault_d | tlb_inelig_d | lrat_miss_d) & {`MM_THREADS{tlb_tag4_q[`tagpos_type_derat]}} & {`MM_THREADS{tlb_tag4_q[`tagpos_class]}}; + + assign cr0_eq_d = ( ((tlb_tag4_q[`tagpos_type_tlbsrx] == 1'b1 | (tlb_tag4_q[`tagpos_type_tlbsx] == 1'b1 & tlb_tag4_q[`tagpos_recform] == 1'b1)) & tlb_tag4_wayhit_q[`TLB_WAYS] == 1'b1 & + multihit == 1'b0 & |(tag4_parerr_q[0:`TLB_WAYS]) == 1'b0) ) ? tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] : + {`MM_THREADS{1'b0}}; + + assign cr0_eq_valid_d = (((tlb_tag4_q[`tagpos_type_tlbsrx] == 1'b1 | (tlb_tag4_q[`tagpos_type_tlbsx] == 1'b1 & tlb_tag4_q[`tagpos_recform] == 1'b1)) & + (tlb_tag4_q[`tagpos_endflag] == 1'b1 | (tlb_tag4_wayhit_q[`TLB_WAYS] == 1'b1 & multihit == 1'b0)) & + |(tag4_parerr_q[0:`TLB_WAYS]) == 1'b0)) ? tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] : + {`MM_THREADS{1'b0}}; + + assign tlb_multihit_err_d = ((((tlb_tag4_q[`tagpos_type_derat:`tagpos_type_ierat] != 2'b00 & tlb_tag4_q[`tagpos_type_ptereload] == 1'b0 & tlb_tag4_q[`tagpos_nonspec] == 1'b1) | + (tlb_tag4_q[`tagpos_type_tlbsx:`tagpos_type_tlbsrx] != 2'b00)) & multihit == 1'b1 & + (tlb_tag4_q[`tagpos_endflag] == 1'b1 | tlb_tag4_wayhit_q[`TLB_WAYS] == 1'b1))) ? tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] : + {`MM_THREADS{1'b0}}; + + assign mm_xu_ord_par_mhit_err_d[0] = |(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1]) & (tlb_tag4_q[`tagpos_endflag] | tlb_tag4_wayhit_q[`TLB_WAYS]) & + |(tlb_tag4_q[`tagpos_type_tlbsx:`tagpos_type_tlbsrx]) & multihit; + + generate + if (`CHECK_PARITY == 0) + begin : parerr_gen0 + assign tlb_par_err_d = tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] & {`MM_THREADS{tag4_parerr_q[0] & (~(tag4_parerr_q[0])) & |(tlb_tag4_q[`tagpos_type_derat:`tagpos_type_tlbre])}}; + assign lru_par_err_d = tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] & {`MM_THREADS{tag4_parerr_q[2] & (~(tag4_parerr_q[2])) & |(tlb_tag4_q[`tagpos_type_derat:`tagpos_type_tlbre])}}; + assign tlb_tag4_tlbre_parerr = 1'b0; + assign ECO107332_tlb_par_err_d = tlb_par_err_d; + assign ECO107332_lru_par_err_d = lru_par_err_d; + assign mm_xu_ord_par_mhit_err_d[1] = 1'b0; + assign mm_xu_ord_par_mhit_err_d[2] = 1'b0; + end + endgenerate + + //constant `tagpos_type_derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload + //tlb_par_err_d <= tlb_tag4_q(`tagpos_thdid to `tagpos_thdid+`THDID_WIDTH-1) + // IFDEF(A2O) + // and (0 to (MM_THREADS-1) => (|(tag4_parerr_q(0 to 3)) and tlb_tag4_q(`tagpos_nonspec) and + // (|(tlb_tag4_q(`tagpos_type_derat to `tagpos_type_tlbsrx)) or tlb_tag4_q(`tagpos_type_tlbre)))); + // ELSE + // and (0 to (MM_THREADS-1) => (|(tag4_parerr_q(0 to 3)) and + // (|(tlb_tag4_q(`tagpos_type_derat to `tagpos_type_tlbsrx)) or tlb_tag4_q(`tagpos_type_tlbre)))); + // ENDIF + + generate + if (`CHECK_PARITY == 1) + begin : parerr_gen1 + assign tlb_par_err_d = tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] & + {`MM_THREADS{ (|(tag4_parerr_q[0:`TLB_WAYS - 1]) & tlb_tag4_q[`tagpos_nonspec] & |(tlb_tag4_q[`tagpos_type_derat:`tagpos_type_tlbsrx])) | + (tag4_parerr_q[0] & tlb_tag4_q[`tagpos_type_tlbre] & (~tlb_tag4_q[`tagpos_esel + 1]) & (~tlb_tag4_q[`tagpos_esel + 2])) | + (tag4_parerr_q[1] & tlb_tag4_q[`tagpos_type_tlbre] & (~tlb_tag4_q[`tagpos_esel + 1]) & tlb_tag4_q[`tagpos_esel + 2]) | + (tag4_parerr_q[2] & tlb_tag4_q[`tagpos_type_tlbre] & tlb_tag4_q[`tagpos_esel + 1] & (~tlb_tag4_q[`tagpos_esel + 2])) | + (tag4_parerr_q[3] & tlb_tag4_q[`tagpos_type_tlbre] & tlb_tag4_q[`tagpos_esel + 1] & tlb_tag4_q[`tagpos_esel + 2]) }}; + + assign lru_par_err_d = tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] & + {`MM_THREADS{ tag4_parerr_q[4] & tlb_tag4_q[`tagpos_nonspec] & (|(tlb_tag4_q[`tagpos_type_derat:`tagpos_type_tlbsrx]) | tlb_tag4_q[`tagpos_type_tlbre]) }}; + + assign ECO107332_tlb_par_err_d = tlb_par_err_d & (~(tlb_ctl_tag4_flush)); + assign ECO107332_lru_par_err_d = lru_par_err_d & (~(tlb_ctl_tag4_flush)); + + assign tlb_tag4_tlbre_parerr = (tag4_parerr_q[0] & tlb_tag4_q[`tagpos_type_tlbre] & (~tlb_tag4_q[`tagpos_esel + 1]) & (~tlb_tag4_q[`tagpos_esel + 2])) | + (tag4_parerr_q[1] & tlb_tag4_q[`tagpos_type_tlbre] & (~tlb_tag4_q[`tagpos_esel + 1]) & tlb_tag4_q[`tagpos_esel + 2]) | + (tag4_parerr_q[2] & tlb_tag4_q[`tagpos_type_tlbre] & tlb_tag4_q[`tagpos_esel + 1] & (~tlb_tag4_q[`tagpos_esel + 2])) | + (tag4_parerr_q[3] & tlb_tag4_q[`tagpos_type_tlbre] & tlb_tag4_q[`tagpos_esel + 1] & tlb_tag4_q[`tagpos_esel + 2]) | + (tag4_parerr_q[4] & tlb_tag4_q[`tagpos_type_tlbre]); + + assign mm_xu_ord_par_mhit_err_d[1] = |(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1]) & + ( (|(tag4_parerr_q[0:`TLB_WAYS - 1]) & |(tlb_tag4_q[`tagpos_type_tlbsx:`tagpos_type_tlbsrx])) | + (tag4_parerr_q[0] & tlb_tag4_q[`tagpos_type_tlbre] & (~tlb_tag4_q[`tagpos_esel + 1]) & (~tlb_tag4_q[`tagpos_esel + 2])) | + (tag4_parerr_q[1] & tlb_tag4_q[`tagpos_type_tlbre] & (~tlb_tag4_q[`tagpos_esel + 1]) & tlb_tag4_q[`tagpos_esel + 2]) | + (tag4_parerr_q[2] & tlb_tag4_q[`tagpos_type_tlbre] & tlb_tag4_q[`tagpos_esel + 1] & (~tlb_tag4_q[`tagpos_esel + 2])) | + (tag4_parerr_q[3] & tlb_tag4_q[`tagpos_type_tlbre] & tlb_tag4_q[`tagpos_esel + 1] & tlb_tag4_q[`tagpos_esel + 2]) ); + + assign mm_xu_ord_par_mhit_err_d[2] = |(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1]) & ( tag4_parerr_q[4] & + (|(tlb_tag4_q[`tagpos_type_tlbsx:`tagpos_type_tlbsrx]) | tlb_tag4_q[`tagpos_type_tlbre]) ); + + end + endgenerate + + assign mm_xu_ord_tlb_multihit = mm_xu_ord_par_mhit_err_q[0]; + assign mm_xu_ord_tlb_par_err = mm_xu_ord_par_mhit_err_q[1]; + assign mm_xu_ord_lru_par_err = mm_xu_ord_par_mhit_err_q[2]; + + assign tlb_tag5_except_d = (hv_priv_d | lrat_miss_d | tlb_inelig_d | pt_fault_d | tlb_multihit_err_d | tlb_par_err_d | lru_par_err_d); + assign tlb_tag5_itag_d = tlb_tag4_q[`tagpos_itag:`tagpos_itag + `ITAG_SIZE_ENC - 1]; + + assign tlb_tag5_emq_d = ( tlb_tag4_q[`tagpos_type_derat] == 1'b1 & tlb_tag4_q[`tagpos_type_ptereload] == 1'b0 & tlb_tag4_q[`tagpos_ind] == 1'b0 & + tlb_tag4_wayhit_q[`TLB_WAYS] == 1'b1 & |(tag4_parerr_q[0:`TLB_WAYS]) == 1'b0 & multihit == 1'b0 & + |(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] & (~tlb_ctl_tag4_flush)) == 1'b1 ) ? (tlb_tag4_q[`tagpos_emq:`tagpos_emq + `EMQ_ENTRIES - 1] | derat_tag4_dup_emq) : + ( tlb_tag4_q[`tagpos_type_derat] == 1'b1 & tlb_tag4_q[`tagpos_type_ptereload] == 1'b0 & ((tlb_tag4_q[`tagpos_endflag] == 1'b1 & + tlb_tag4_wayhit_q[`TLB_WAYS] == 1'b0) | |(tag4_parerr_q[0:4]) == 1'b1 | multihit == 1'b1) & + |(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] & (~tlb_ctl_tag4_flush)) == 1'b1 ) ? tlb_tag4_q[`tagpos_emq:`tagpos_emq + `EMQ_ENTRIES - 1] : + ( tlb_tag4_q[`tagpos_type_derat] == 1'b1 & tlb_tag4_q[`tagpos_type_ptereload] == 1'b1 ) ? tlb_tag4_q[`tagpos_emq:`tagpos_emq + `EMQ_ENTRIES - 1] : + {`EMQ_ENTRIES{1'b0}}; + + // these are spares for exceptions + assign tlb_isi_d = ( tlb_tag4_q[`tagpos_type_ierat] == 1'b1 & tlb_tag4_q[`tagpos_type_ptereload] == 1'b0 & tlb_tag4_q[`tagpos_nonspec] == 1'b1 & + (|(tlb_tag4_wayhit_q[0:`TLB_WAYS - 1])) == 1'b0 & tlb_tag4_q[`tagpos_endflag] == 1'b1 ) ? tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] : + {`MM_THREADS{1'b0}}; + assign tlb_dsi_d = ( (tlb_tag4_q[`tagpos_type_derat] == 1'b1 & tlb_tag4_q[`tagpos_type_ptereload] == 1'b0 & tlb_tag4_q[`tagpos_nonspec] == 1'b1 & + (|(tlb_tag4_wayhit_q[0:`TLB_WAYS - 1])) == 1'b0 & tlb_tag4_q[`tagpos_endflag] == 1'b1)) ? tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] : + {`MM_THREADS{1'b0}}; + + + // tlb_low_data + // 0:51 - EPN + // 52:55 - SIZE (4b) + // 56:59 - ThdID + // 60:61 - Class + // 62:63 - ExtClass + // 64:65 - reserved (2b) + // 66:73 - 8b for LPID + // 74:83 - parity 10bits + // tlb_high_data + // 84 - 0 - X-bit + // 85:87 - 1:3 - reserved (3b) + // 88:117 - 4:33 - RPN (30b) + // 118:119 - 34:35 - R,C + // 120:121 - 36:37 - WLC (2b) + // 122 - 38 - ResvAttr + // 123 - 39 - VF + // 124 - 40 - IND + // 125:128 - 41:44 - U0-U3 + // 129:133 - 45:49 - WIMGE + // 134:136 - 50:52 - UX,UW,UR + // 137:139 - 53:55 - SX,SW,SR + // 140 - 56 - GS + // 141 - 57 - TS + // 142:143 - 58:59 - reserved (2b) + // 144:149 - 60:65 - 6b TID msbs + // 150:157 - 66:73 - 8b TID lsbs + // 158:167 - 74:83 - parity 10bits + // `tagpos_epn : natural := 0; + // `tagpos_pid : natural := 52; -- 14 bits + // `tagpos_is : natural := 66; + // `tagpos_class : natural := 68; + // `tagpos_state : natural := 70; -- state: 0:pr 1:gs 2:as 3:cm + // `tagpos_thdid : natural := 74; + // `tagpos_size : natural := 78; + // `tagpos_type : natural := 82; -- derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload + // `tagpos_lpid : natural := 90; + // `tagpos_ind : natural := 98; + // `tagpos_atsel : natural := 99; + // `tagpos_esel : natural := 100; + // `tagpos_hes : natural := 103; + // `tagpos_wq : natural := 104; + // `tagpos_lrat : natural := 106; lrat for tlbwe enabled + // `tagpos_pt : natural := 107; tlb can be loaded from page table (hwt enabled) + // `tagpos_recform : natural := 108; + // `tagpos_endflag : natural := 109; + // `waypos_epn : natural := 0; + // `waypos_size : natural := 52; + // `waypos_thdid : natural := 56; + // `waypos_class : natural := 60; + // `waypos_extclass : natural := 62; + // `waypos_lpid : natural := 66; + // `waypos_xbit : natural := 84; + // `waypos_rpn : natural := 88; + // `waypos_rc : natural := 118; + // `waypos_wlc : natural := 120; + // `waypos_resvattr : natural := 122; + // `waypos_vf : natural := 123; + // `waypos_ind : natural := 124; + // `waypos_ubits : natural := 125; + // `waypos_wimge : natural := 129; + // `waypos_usxwr : natural := 134; + // `waypos_gs : natural := 140; + // `waypos_ts : natural := 141; + // `waypos_tid : natural := 144; -- 14 bits + // these are tag3 phase components + + mmq_tlb_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1)) matchline_comb0( + .vdd(vdd), + .gnd(gnd), + .addr_in(tlb_tag3_clone1_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 1]), + .addr_enable(addr_enable), + .comp_pgsize(tlb_tag3_clone1_q[`tagpos_size:`tagpos_size + 3]), + .pgsize_enable(pgsize_enable), + .entry_size(tlb_way0_q[`waypos_size:`waypos_size + 3]), + .entry_cmpmask(tlb_way0_cmpmask_q), + .entry_xbit(tlb_way0_q[`waypos_xbit]), + .entry_xbitmask(tlb_way0_xbitmask_q), + .entry_epn(tlb_way0_q[`waypos_epn:`waypos_epn + `EPN_WIDTH - 1]), + .comp_class(tlb_tag3_clone1_q[`tagpos_class:`tagpos_class + 1]), + .entry_class(tlb_way0_q[`waypos_class:`waypos_class + 1]), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(tlb_way0_q[`waypos_extclass:`waypos_extclass + 1]), + .extclass_enable(extclass_enable), + .comp_state(tlb_tag3_clone1_q[`tagpos_state + 1:`tagpos_state + 2]), + .entry_gs(tlb_way0_q[`waypos_gs]), + .entry_ts(tlb_way0_q[`waypos_ts]), + .state_enable(state_enable), + .entry_thdid(tlb_way0_q[`waypos_thdid:`waypos_thdid + `THDID_WIDTH - 1]), + .comp_thdid(tlb_tag3_clone1_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]), + .thdid_enable(thdid_enable), + .entry_pid(tlb_way0_q[`waypos_tid:`waypos_tid + `PID_WIDTH - 1]), + .comp_pid(tlb_tag3_clone1_q[`tagpos_pid:`tagpos_pid + `PID_WIDTH - 1]), + .pid_enable(pid_enable), + .entry_lpid(tlb_way0_q[`waypos_lpid:`waypos_lpid + `LPID_WIDTH - 1]), + .comp_lpid(tlb_tag3_clone1_q[`tagpos_lpid:`tagpos_lpid + `LPID_WIDTH - 1]), + .lpid_enable(lpid_enable), + .entry_ind(tlb_way0_q[`waypos_ind]), + .comp_ind(comp_ind), + .ind_enable(ind_enable), + .entry_iprot(lru_tag3_dataout_q[8]), + .comp_iprot(comp_iprot), + .iprot_enable(iprot_enable), + .entry_v(lru_tag3_dataout_q[0]), + .comp_invalidate(tlb_tag3_clone1_q[`tagpos_type_snoop]), + + .match(tlb_wayhit[0]), + .dbg_addr_match(tlb_way0_addr_match), + .dbg_pgsize_match(tlb_way0_pgsize_match), + .dbg_class_match(tlb_way0_class_match), + .dbg_extclass_match(tlb_way0_extclass_match), + .dbg_state_match(tlb_way0_state_match), + .dbg_thdid_match(tlb_way0_thdid_match), + .dbg_pid_match(tlb_way0_pid_match), + .dbg_lpid_match(tlb_way0_lpid_match), + .dbg_ind_match(tlb_way0_ind_match), + .dbg_iprot_match(tlb_way0_iprot_match) + ); + + mmq_tlb_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1)) matchline_comb1( + .vdd(vdd), + .gnd(gnd), + .addr_in(tlb_tag3_clone1_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 1]), + .addr_enable(addr_enable), + .comp_pgsize(tlb_tag3_clone1_q[`tagpos_size:`tagpos_size + 3]), + .pgsize_enable(pgsize_enable), + .entry_size(tlb_way1_q[`waypos_size:`waypos_size + 3]), + .entry_cmpmask(tlb_way1_cmpmask_q), + .entry_xbit(tlb_way1_q[`waypos_xbit]), + .entry_xbitmask(tlb_way1_xbitmask_q), + .entry_epn(tlb_way1_q[`waypos_epn:`waypos_epn + `EPN_WIDTH - 1]), + .comp_class(tlb_tag3_clone1_q[`tagpos_class:`tagpos_class + 1]), + .entry_class(tlb_way1_q[`waypos_class:`waypos_class + 1]), + .class_enable(class_enable), + .comp_extclass(comp_extclass), + .entry_extclass(tlb_way1_q[`waypos_extclass:`waypos_extclass + 1]), + .extclass_enable(extclass_enable), + .comp_state(tlb_tag3_clone1_q[`tagpos_state + 1:`tagpos_state + 2]), + .entry_gs(tlb_way1_q[`waypos_gs]), + .entry_ts(tlb_way1_q[`waypos_ts]), + .state_enable(state_enable), + .entry_thdid(tlb_way1_q[`waypos_thdid:`waypos_thdid + `THDID_WIDTH - 1]), + .comp_thdid(tlb_tag3_clone1_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]), + .thdid_enable(thdid_enable), + .entry_pid(tlb_way1_q[`waypos_tid:`waypos_tid + `PID_WIDTH - 1]), + .comp_pid(tlb_tag3_clone1_q[`tagpos_pid:`tagpos_pid + `PID_WIDTH - 1]), + .pid_enable(pid_enable), + .entry_lpid(tlb_way1_q[`waypos_lpid:`waypos_lpid + `LPID_WIDTH - 1]), + .comp_lpid(tlb_tag3_clone1_q[`tagpos_lpid:`tagpos_lpid + `LPID_WIDTH - 1]), + .lpid_enable(lpid_enable), + .entry_ind(tlb_way1_q[`waypos_ind]), + .comp_ind(comp_ind), + .ind_enable(ind_enable), + .entry_iprot(lru_tag3_dataout_q[9]), + .comp_iprot(comp_iprot), + .iprot_enable(iprot_enable), + .entry_v(lru_tag3_dataout_q[1]), + .comp_invalidate(tlb_tag3_clone1_q[`tagpos_type_snoop]), + + .match(tlb_wayhit[1]), + .dbg_addr_match(tlb_way1_addr_match), + .dbg_pgsize_match(tlb_way1_pgsize_match), + .dbg_class_match(tlb_way1_class_match), + .dbg_extclass_match(tlb_way1_extclass_match), + .dbg_state_match(tlb_way1_state_match), + .dbg_thdid_match(tlb_way1_thdid_match), + .dbg_pid_match(tlb_way1_pid_match), + .dbg_lpid_match(tlb_way1_lpid_match), + .dbg_ind_match(tlb_way1_ind_match), + .dbg_iprot_match(tlb_way1_iprot_match) + ); + + mmq_tlb_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1)) matchline_comb2( + .vdd(vdd), + .gnd(gnd), + .addr_in(tlb_tag3_clone2_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 1]), + .addr_enable(addr_enable_clone), + .comp_pgsize(tlb_tag3_clone2_q[`tagpos_size:`tagpos_size + 3]), + .pgsize_enable(pgsize_enable_clone), + .entry_size(tlb_way2_q[`waypos_size:`waypos_size + 3]), + .entry_cmpmask(tlb_way2_cmpmask_q), + .entry_xbit(tlb_way2_q[`waypos_xbit]), + .entry_xbitmask(tlb_way2_xbitmask_q), + .entry_epn(tlb_way2_q[`waypos_epn:`waypos_epn + `EPN_WIDTH - 1]), + .comp_class(tlb_tag3_clone2_q[`tagpos_class:`tagpos_class + 1]), + .entry_class(tlb_way2_q[`waypos_class:`waypos_class + 1]), + .class_enable(class_enable_clone), + .comp_extclass(comp_extclass_clone), + .entry_extclass(tlb_way2_q[`waypos_extclass:`waypos_extclass + 1]), + .extclass_enable(extclass_enable_clone), + .comp_state(tlb_tag3_clone2_q[`tagpos_state + 1:`tagpos_state + 2]), + .entry_gs(tlb_way2_q[`waypos_gs]), + .entry_ts(tlb_way2_q[`waypos_ts]), + .state_enable(state_enable_clone), + .entry_thdid(tlb_way2_q[`waypos_thdid:`waypos_thdid + `THDID_WIDTH - 1]), + .comp_thdid(tlb_tag3_clone2_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]), + .thdid_enable(thdid_enable_clone), + .entry_pid(tlb_way2_q[`waypos_tid:`waypos_tid + `PID_WIDTH - 1]), + .comp_pid(tlb_tag3_clone2_q[`tagpos_pid:`tagpos_pid + `PID_WIDTH - 1]), + .pid_enable(pid_enable_clone), + .entry_lpid(tlb_way2_q[`waypos_lpid:`waypos_lpid + `LPID_WIDTH - 1]), + .comp_lpid(tlb_tag3_clone2_q[`tagpos_lpid:`tagpos_lpid + `LPID_WIDTH - 1]), + .lpid_enable(lpid_enable_clone), + .entry_ind(tlb_way2_q[`waypos_ind]), + .comp_ind(comp_ind_clone), + .ind_enable(ind_enable_clone), + .entry_iprot(lru_tag3_dataout_q[10]), + .comp_iprot(comp_iprot_clone), + .iprot_enable(iprot_enable_clone), + .entry_v(lru_tag3_dataout_q[2]), + .comp_invalidate(tlb_tag3_clone2_q[`tagpos_type_snoop]), + + .match(tlb_wayhit[2]), + + .dbg_addr_match(tlb_way2_addr_match), + .dbg_pgsize_match(tlb_way2_pgsize_match), + .dbg_class_match(tlb_way2_class_match), + .dbg_extclass_match(tlb_way2_extclass_match), + .dbg_state_match(tlb_way2_state_match), + .dbg_thdid_match(tlb_way2_thdid_match), + .dbg_pid_match(tlb_way2_pid_match), + .dbg_lpid_match(tlb_way2_lpid_match), + .dbg_ind_match(tlb_way2_ind_match), + .dbg_iprot_match(tlb_way2_iprot_match) + ); + + mmq_tlb_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1)) matchline_comb3( + .vdd(vdd), + .gnd(gnd), + .addr_in(tlb_tag3_clone2_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 1]), + .addr_enable(addr_enable_clone), + .comp_pgsize(tlb_tag3_clone2_q[`tagpos_size:`tagpos_size + 3]), + .pgsize_enable(pgsize_enable_clone), + .entry_size(tlb_way3_q[`waypos_size:`waypos_size + 3]), + .entry_cmpmask(tlb_way3_cmpmask_q), + .entry_xbit(tlb_way3_q[`waypos_xbit]), + .entry_xbitmask(tlb_way3_xbitmask_q), + .entry_epn(tlb_way3_q[`waypos_epn:`waypos_epn + `EPN_WIDTH - 1]), + .comp_class(tlb_tag3_clone2_q[`tagpos_class:`tagpos_class + 1]), + .entry_class(tlb_way3_q[`waypos_class:`waypos_class + 1]), + .class_enable(class_enable_clone), + .comp_extclass(comp_extclass_clone), + .entry_extclass(tlb_way3_q[`waypos_extclass:`waypos_extclass + 1]), + .extclass_enable(extclass_enable_clone), + .comp_state(tlb_tag3_clone2_q[`tagpos_state + 1:`tagpos_state + 2]), + .entry_gs(tlb_way3_q[`waypos_gs]), + .entry_ts(tlb_way3_q[`waypos_ts]), + .state_enable(state_enable_clone), + .entry_thdid(tlb_way3_q[`waypos_thdid:`waypos_thdid + `THDID_WIDTH - 1]), + .comp_thdid(tlb_tag3_clone2_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]), + .thdid_enable(thdid_enable_clone), + .entry_pid(tlb_way3_q[`waypos_tid:`waypos_tid + `PID_WIDTH - 1]), + .comp_pid(tlb_tag3_clone2_q[`tagpos_pid:`tagpos_pid + `PID_WIDTH - 1]), + .pid_enable(pid_enable_clone), + .entry_lpid(tlb_way3_q[`waypos_lpid:`waypos_lpid + `LPID_WIDTH - 1]), + .comp_lpid(tlb_tag3_clone2_q[`tagpos_lpid:`tagpos_lpid + `LPID_WIDTH - 1]), + .lpid_enable(lpid_enable_clone), + .entry_ind(tlb_way3_q[`waypos_ind]), + .comp_ind(comp_ind_clone), + .ind_enable(ind_enable_clone), + .entry_iprot(lru_tag3_dataout_q[11]), + .comp_iprot(comp_iprot_clone), + .iprot_enable(iprot_enable_clone), + .entry_v(lru_tag3_dataout_q[3]), + .comp_invalidate(tlb_tag3_clone2_q[`tagpos_type_snoop]), + + .match(tlb_wayhit[3]), + + .dbg_addr_match(tlb_way3_addr_match), + .dbg_pgsize_match(tlb_way3_pgsize_match), + .dbg_class_match(tlb_way3_class_match), + .dbg_extclass_match(tlb_way3_extclass_match), + .dbg_state_match(tlb_way3_state_match), + .dbg_thdid_match(tlb_way3_thdid_match), + .dbg_pid_match(tlb_way3_pid_match), + .dbg_lpid_match(tlb_way3_lpid_match), + .dbg_ind_match(tlb_way3_ind_match), + .dbg_iprot_match(tlb_way3_iprot_match) + ); + + + //--------------------------------------------------------------------- + // output assignments + //--------------------------------------------------------------------- + assign tlb_cmp_ierat_dup_val[0:6] = tlb_erat_dup_q[0:6]; + assign tlb_cmp_derat_dup_val[0:6] = tlb_erat_dup_q[10:16]; + assign tlb_cmp_erat_dup_wait = {tlb_erat_dup_q[5], tlb_erat_dup_q[15]}; + assign mm_iu_ierat_rel_val = tlb_erat_val_q[0:4]; + assign mm_iu_ierat_rel_data = tlb_erat_rel_q; + assign mm_xu_derat_rel_val = tlb_erat_val_q[5:9]; + assign mm_xu_derat_rel_data = tlb_erat_rel_clone_q; + assign mm_xu_eratmiss_done = eratmiss_done_q; + assign mm_xu_tlb_miss = tlb_miss_q; + assign mm_xu_tlb_inelig = tlb_inelig_q; + assign mm_xu_lrat_miss = lrat_miss_q; + assign mm_xu_pt_fault = pt_fault_q; + assign mm_xu_hv_priv = hv_priv_q; + assign mm_xu_esr_pt = esr_pt_q; + assign mm_xu_esr_data = esr_data_q; + assign mm_xu_esr_epid = esr_epid_q; + assign mm_xu_esr_st = esr_st_q; + assign mm_xu_cr0_eq = cr0_eq_q; + assign mm_xu_cr0_eq_valid = cr0_eq_valid_q; + assign mm_xu_tlb_multihit_err = tlb_multihit_err_q; + assign mm_xu_tlb_par_err = tlb_par_err_q; + assign mm_xu_lru_par_err = lru_par_err_q; + assign mm_xu_tlb_miss_ored = |(tlb_miss_q); + assign mm_xu_lrat_miss_ored = |(lrat_miss_q); + assign mm_xu_tlb_inelig_ored = |(tlb_inelig_q); + assign mm_xu_pt_fault_ored = |(pt_fault_q); + assign mm_xu_hv_priv_ored = |(hv_priv_q); + assign mm_xu_cr0_eq_ored = |(cr0_eq_q); + assign mm_xu_cr0_eq_valid_ored = |(cr0_eq_valid_q); + assign tlb_multihit_err_ored = |(tlb_multihit_err_q); + assign tlb_par_err_ored = |(tlb_par_err_q); + assign lru_par_err_ored = |(lru_par_err_q); + assign tlb_addr4 = tlb_addr4_q; + assign tlb_tag5_except = tlb_tag5_except_q; + assign tlb_tag4_itag = tlb_tag4_q[`tagpos_itag:`tagpos_itag + `ITAG_SIZE_ENC - 1]; + assign tlb_tag5_itag = tlb_tag5_itag_q; + assign tlb_tag5_emq = tlb_tag5_emq_q; + assign tlb_tag4_esel = tlb_tag4_q[`tagpos_esel:`tagpos_esel + 2]; + assign tlb_tag4_wq = tlb_tag4_q[`tagpos_wq:`tagpos_wq + 1]; + assign tlb_tag4_is = tlb_tag4_q[`tagpos_is:`tagpos_is + 1]; + assign tlb_tag4_hes = tlb_tag4_q[`tagpos_hes]; + assign tlb_tag4_gs = tlb_tag4_q[`tagpos_gs]; + assign tlb_tag4_pr = tlb_tag4_q[`tagpos_pr]; + assign tlb_tag4_atsel = tlb_tag4_q[`tagpos_atsel]; + assign tlb_tag4_pt = tlb_tag4_q[`tagpos_pt]; + assign tlb_tag4_endflag = tlb_tag4_q[`tagpos_endflag] & |(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]); + assign tlb_tag4_nonspec = tlb_tag4_q[`tagpos_nonspec]; + assign lru_tag4_dataout = lru_tag4_dataout_q[0:15]; + assign tlb_tag4_cmp_hit = tlb_tag4_wayhit_q[`TLB_WAYS]; + assign tlb_tag4_way_ind = tlb_tag4_way_or[`waypos_ind]; + assign tlb_tag4_ptereload_sig = tlb_tag4_q[`tagpos_type_ptereload] & |(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]); + assign tlb_tag4_ptereload = tlb_tag4_ptereload_sig; + assign tlb_tag4_parerr = |(tag4_parerr_q[0:4]) & tlb_tag4_parerr_enab; + assign tlb_mas0_esel[0] = 1'b0; + assign tlb_mas0_esel[1:2] = (tlb_tag4_wayhit_q[0:`TLB_WAYS] == 5'b01001) ? 2'b01 : + (tlb_tag4_wayhit_q[0:`TLB_WAYS] == 5'b00101) ? 2'b10 : + (tlb_tag4_wayhit_q[0:`TLB_WAYS] == 5'b00011) ? 2'b11 : + 2'b00; + assign tlb_mas1_v = ((tlb_tag4_q[`tagpos_type_tlbre] == 1'b1 & tlb_tag4_q[`tagpos_esel + 1:`tagpos_esel + 2] == 2'b00)) ? lru_tag4_dataout_q[0] : + ((tlb_tag4_q[`tagpos_type_tlbre] == 1'b1 & tlb_tag4_q[`tagpos_esel + 1:`tagpos_esel + 2] == 2'b01)) ? lru_tag4_dataout_q[1] : + ((tlb_tag4_q[`tagpos_type_tlbre] == 1'b1 & tlb_tag4_q[`tagpos_esel + 1:`tagpos_esel + 2] == 2'b10)) ? lru_tag4_dataout_q[2] : + ((tlb_tag4_q[`tagpos_type_tlbre] == 1'b1 & tlb_tag4_q[`tagpos_esel + 1:`tagpos_esel + 2] == 2'b11)) ? lru_tag4_dataout_q[3] : + (tlb_tag4_q[`tagpos_type_tlbsx] == 1'b1) ? tlb_tag4_wayhit_q[`TLB_WAYS] : + 1'b0; + assign tlb_mas1_iprot = ((tlb_tag4_q[`tagpos_type_tlbsx] == 1'b1 & tlb_tag4_wayhit_q[0:`TLB_WAYS] == 5'b10001) | (tlb_tag4_q[`tagpos_type_tlbre] == 1'b1 & tlb_tag4_q[`tagpos_esel + 1:`tagpos_esel + 2] == 2'b00)) ? lru_tag4_dataout_q[8] : + ((tlb_tag4_q[`tagpos_type_tlbsx] == 1'b1 & tlb_tag4_wayhit_q[0:`TLB_WAYS] == 5'b01001) | (tlb_tag4_q[`tagpos_type_tlbre] == 1'b1 & tlb_tag4_q[`tagpos_esel + 1:`tagpos_esel + 2] == 2'b01)) ? lru_tag4_dataout_q[9] : + ((tlb_tag4_q[`tagpos_type_tlbsx] == 1'b1 & tlb_tag4_wayhit_q[0:`TLB_WAYS] == 5'b00101) | (tlb_tag4_q[`tagpos_type_tlbre] == 1'b1 & tlb_tag4_q[`tagpos_esel + 1:`tagpos_esel + 2] == 2'b10)) ? lru_tag4_dataout_q[10] : + ((tlb_tag4_q[`tagpos_type_tlbsx] == 1'b1 & tlb_tag4_wayhit_q[0:`TLB_WAYS] == 5'b00011) | (tlb_tag4_q[`tagpos_type_tlbre] == 1'b1 & tlb_tag4_q[`tagpos_esel + 1:`tagpos_esel + 2] == 2'b11)) ? lru_tag4_dataout_q[11] : + 1'b0; + // `waypos_epn : natural := 0; + // `waypos_size : natural := 52; + // `waypos_thdid : natural := 56; + // `waypos_class : natural := 60; + // `waypos_extclass : natural := 62; + // `waypos_lpid : natural := 66; + // `waypos_xbit : natural := 84; + // `waypos_tstmode4k : natural := 85; + // `waypos_rpn : natural := 88; + // `waypos_rc : natural := 118; + // `waypos_wlc : natural := 120; + // `waypos_resvattr : natural := 122; + // `waypos_vf : natural := 123; + // `waypos_ind : natural := 124; + // `waypos_ubits : natural := 125; + // `waypos_wimge : natural := 129; + // `waypos_usxwr : natural := 134; + // `waypos_gs : natural := 140; + // `waypos_ts : natural := 141; + // `waypos_tid : natural := 144; -- 14 bits + + // constant `tagpos_type : natural := 82; -- derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload + + assign tlb_mas1_tid = ((|(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & (tlb_tag4_q[`tagpos_type_tlbre] | tlb_tag4_q[`tagpos_type_tlbwe] | tlb_tag4_q[`tagpos_type_ptereload]) == 1'b1)) ? tlb_tag4_way_rw_or[`waypos_tid:`waypos_tid + `PID_WIDTH - 1] : + tlb_tag4_way_or[`waypos_tid:`waypos_tid + `PID_WIDTH - 1]; + + assign tlb_mas1_tid_error = tlb_tag4_q[`tagpos_pid:`tagpos_pid + `PID_WIDTH - 1]; + + assign tlb_mas1_ind = ((|(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & (tlb_tag4_q[`tagpos_type_tlbre] | tlb_tag4_q[`tagpos_type_tlbwe] | tlb_tag4_q[`tagpos_type_ptereload]) == 1'b1)) ? tlb_tag4_way_rw_or[`waypos_ind] : + tlb_tag4_way_or[`waypos_ind]; + + assign tlb_mas1_ts = ((|(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & (tlb_tag4_q[`tagpos_type_tlbre] | tlb_tag4_q[`tagpos_type_tlbwe] | tlb_tag4_q[`tagpos_type_ptereload]) == 1'b1)) ? tlb_tag4_way_rw_or[`waypos_ts] : + tlb_tag4_way_or[`waypos_ts]; + + assign tlb_mas1_ts_error = tlb_tag4_q[`tagpos_state + 2]; + + assign tlb_mas1_tsize = ((|(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & (tlb_tag4_q[`tagpos_type_tlbre] | tlb_tag4_q[`tagpos_type_tlbwe] | tlb_tag4_q[`tagpos_type_ptereload]) == 1'b1)) ? tlb_tag4_way_rw_or[`waypos_size:`waypos_size + 3] : + tlb_tag4_way_or[`waypos_size:`waypos_size + 3]; + + + assign tlb_mas2_epn[0:31] = ( |(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & + (tlb_tag4_q[`tagpos_type_tlbre] | tlb_tag4_q[`tagpos_type_tlbwe] | tlb_tag4_q[`tagpos_type_ptereload]) == 1'b1 ) ? (tlb_tag4_way_rw_or[`waypos_epn:`waypos_epn + 31] & {32{tlb_tag4_q[`tagpos_cm]}}) : + tlb_tag4_way_or[`waypos_epn:`waypos_epn + 31]; + + assign tlb_mas2_epn[32:`EPN_WIDTH - 1] = ((|(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & (tlb_tag4_q[`tagpos_type_tlbre] | tlb_tag4_q[`tagpos_type_tlbwe] | tlb_tag4_q[`tagpos_type_ptereload]) == 1'b1)) ? tlb_tag4_way_rw_or[`waypos_epn + 32:`waypos_epn + `EPN_WIDTH - 1] : + tlb_tag4_way_or[`waypos_epn + 32:`waypos_epn + `EPN_WIDTH - 1]; + + assign tlb_mas2_epn_error = tlb_tag4_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 1]; + + assign tlb_mas2_wimge = ((|(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & (tlb_tag4_q[`tagpos_type_tlbre] | tlb_tag4_q[`tagpos_type_tlbwe] | tlb_tag4_q[`tagpos_type_ptereload]) == 1'b1)) ? tlb_tag4_way_rw_or[`waypos_wimge:`waypos_wimge + 4] : + tlb_tag4_way_or[`waypos_wimge:`waypos_wimge + 4]; + + + assign tlb_mas3_rpnl = ((|(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & (tlb_tag4_q[`tagpos_type_tlbre] | tlb_tag4_q[`tagpos_type_tlbwe] | tlb_tag4_q[`tagpos_type_ptereload]) == 1'b1)) ? tlb_tag4_way_rw_or[`waypos_rpn + 10:`waypos_rpn + `RPN_WIDTH - 1] : + tlb_tag4_way_or[`waypos_rpn + 10:`waypos_rpn + `RPN_WIDTH - 1]; + + assign tlb_mas3_ubits = ((|(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & (tlb_tag4_q[`tagpos_type_tlbre] | tlb_tag4_q[`tagpos_type_tlbwe] | tlb_tag4_q[`tagpos_type_ptereload]) == 1'b1)) ? tlb_tag4_way_rw_or[`waypos_ubits:`waypos_ubits + 3] : + tlb_tag4_way_or[`waypos_ubits:`waypos_ubits + 3]; + + assign tlb_mas3_usxwr = ((|(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & (tlb_tag4_q[`tagpos_type_tlbre] | tlb_tag4_q[`tagpos_type_tlbwe] | tlb_tag4_q[`tagpos_type_ptereload]) == 1'b1)) ? tlb_tag4_way_rw_or[`waypos_usxwr:`waypos_usxwr + 5] : + tlb_tag4_way_or[`waypos_usxwr:`waypos_usxwr + 5]; + + assign tlb_mas7_rpnu = ((|(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & (tlb_tag4_q[`tagpos_type_tlbre] | tlb_tag4_q[`tagpos_type_tlbwe] | tlb_tag4_q[`tagpos_type_ptereload]) == 1'b1)) ? tlb_tag4_way_rw_or[`waypos_rpn:`waypos_rpn + 9] : + tlb_tag4_way_or[`waypos_rpn:`waypos_rpn + 9]; + + assign tlb_mas8_tgs = ((|(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & (tlb_tag4_q[`tagpos_type_tlbre] | tlb_tag4_q[`tagpos_type_tlbwe] | tlb_tag4_q[`tagpos_type_ptereload]) == 1'b1)) ? tlb_tag4_way_rw_or[`waypos_gs] : + tlb_tag4_way_or[`waypos_gs]; + assign tlb_mas8_vf = ((|(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & (tlb_tag4_q[`tagpos_type_tlbre] | tlb_tag4_q[`tagpos_type_tlbwe] | tlb_tag4_q[`tagpos_type_ptereload]) == 1'b1)) ? tlb_tag4_way_rw_or[`waypos_vf] : + tlb_tag4_way_or[`waypos_vf]; + assign tlb_mas8_tlpid = ((|(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & (tlb_tag4_q[`tagpos_type_tlbre] | tlb_tag4_q[`tagpos_type_tlbwe] | tlb_tag4_q[`tagpos_type_ptereload]) == 1'b1)) ? tlb_tag4_way_rw_or[`waypos_lpid:`waypos_lpid + `LPID_WIDTH - 1] : + tlb_tag4_way_or[`waypos_lpid:`waypos_lpid + `LPID_WIDTH - 1]; + + assign tlb_mmucr3_thdid = ((|(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & (tlb_tag4_q[`tagpos_type_tlbre] | tlb_tag4_q[`tagpos_type_tlbwe] | tlb_tag4_q[`tagpos_type_ptereload]) == 1'b1)) ? tlb_tag4_way_rw_or[`waypos_thdid:`waypos_thdid + `THDID_WIDTH - 1] : + tlb_tag4_way_or[`waypos_thdid:`waypos_thdid + `THDID_WIDTH - 1]; + assign tlb_mmucr3_resvattr = ((|(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & (tlb_tag4_q[`tagpos_type_tlbre] | tlb_tag4_q[`tagpos_type_tlbwe] | tlb_tag4_q[`tagpos_type_ptereload]) == 1'b1)) ? tlb_tag4_way_rw_or[`waypos_resvattr] : + tlb_tag4_way_or[`waypos_resvattr]; + assign tlb_mmucr3_wlc = ((|(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & (tlb_tag4_q[`tagpos_type_tlbre] | tlb_tag4_q[`tagpos_type_tlbwe] | tlb_tag4_q[`tagpos_type_ptereload]) == 1'b1)) ? tlb_tag4_way_rw_or[`waypos_wlc:`waypos_wlc + 1] : + tlb_tag4_way_or[`waypos_wlc:`waypos_wlc + 1]; + assign tlb_mmucr3_class = ((|(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & (tlb_tag4_q[`tagpos_type_tlbre] | tlb_tag4_q[`tagpos_type_tlbwe] | tlb_tag4_q[`tagpos_type_ptereload]) == 1'b1)) ? tlb_tag4_way_rw_or[`waypos_class:`waypos_class + 1] : + tlb_tag4_way_or[`waypos_class:`waypos_class + 1]; + assign tlb_mmucr3_extclass = ((|(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & (tlb_tag4_q[`tagpos_type_tlbre] | tlb_tag4_q[`tagpos_type_tlbwe] | tlb_tag4_q[`tagpos_type_ptereload]) == 1'b1)) ? tlb_tag4_way_rw_or[`waypos_extclass:`waypos_extclass + 1] : + tlb_tag4_way_or[`waypos_extclass:`waypos_extclass + 1]; + assign tlb_mmucr3_rc = ((|(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & (tlb_tag4_q[`tagpos_type_tlbre] | tlb_tag4_q[`tagpos_type_tlbwe] | tlb_tag4_q[`tagpos_type_ptereload]) == 1'b1)) ? tlb_tag4_way_rw_or[`waypos_rc:`waypos_rc + 1] : + tlb_tag4_way_or[`waypos_rc:`waypos_rc + 1]; + assign tlb_mmucr3_x = ((|(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & (tlb_tag4_q[`tagpos_type_tlbre] | tlb_tag4_q[`tagpos_type_tlbwe] | tlb_tag4_q[`tagpos_type_ptereload]) == 1'b1)) ? tlb_tag4_way_rw_or[`waypos_xbit] : + tlb_tag4_way_or[`waypos_xbit]; + + assign tlb_mmucr1_een = {tlb_addr4_q, (tag4_parerr_q[2] | tag4_parerr_q[3]), (tag4_parerr_q[1] | tag4_parerr_q[3])}; + + assign tlb_mmucr1_we = ( ( (|(tag4_parerr_q[0:`TLB_WAYS]) & |(tlb_tag4_q[`tagpos_type_derat:`tagpos_type_tlbsrx]) & (~tlb_tag4_q[`tagpos_type_ptereload])) | tlb_tag4_tlbre_parerr ) | + ( multihit & tlb_tag4_wayhit_q[`TLB_WAYS] & |(tlb_tag4_q[`tagpos_type_derat:`tagpos_type_tlbsrx]) & (~tlb_tag4_q[`tagpos_type_ptereload]) ) ) + & tlb_tag4_q[`tagpos_nonspec] & ECO107332_orred_tag4_thdid_flushed & xu_mm_xucr4_mmu_mchk_q & xu_mm_ccr2_notlb_b; + + assign ECO107332_orred_tag4_thdid_flushed = |(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] & (~(tlb_ctl_tag4_flush))); + + assign tlb_mas_dtlb_error = tlb_tag4_q[`tagpos_type_derat] & tlb_tag4_q[`tagpos_endflag] & (~tlb_tag4_wayhit_q[`TLB_WAYS]) & tlb_tag4_q[`tagpos_nonspec] & + ( (~(|(tag4_parerr_q[0:4]))) | cswitch_q[6] ) & |( (msr_gs_q | msr_pr_q | (~epcr_dmiuh_q)) & tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] ); + + assign tlb_mas_itlb_error = tlb_tag4_q[`tagpos_type_ierat] & tlb_tag4_q[`tagpos_endflag] & (~tlb_tag4_wayhit_q[`TLB_WAYS]) & tlb_tag4_q[`tagpos_nonspec] & + ( (~(|(tag4_parerr_q[0:4]))) | cswitch_q[6] ) & |( (msr_gs_q | msr_pr_q | (~epcr_dmiuh_q)) & tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] ); + + assign tlb_mas_tlbsx_hit = tlb_tag4_q[`tagpos_type_tlbsx] & tlb_tag4_wayhit_q[`TLB_WAYS] & (~multihit) & tlb_tag4_hv_op & + ( (~(|(tag4_parerr_q[0:4]))) | cswitch_q[5] ); + + assign tlb_mas_tlbsx_miss = tlb_tag4_q[`tagpos_type_tlbsx] & tlb_tag4_q[`tagpos_endflag] & (~tlb_tag4_wayhit_q[`TLB_WAYS]) & tlb_tag4_hv_op & + ( (~(|(tag4_parerr_q[0:4]))) | cswitch_q[6] ); + + assign tlb_mas_tlbre = tlb_tag4_q[`tagpos_type_tlbre] & (~tlb_tag4_q[`tagpos_atsel]) & tlb_tag4_hv_op & (~ex6_illeg_instr[0]) & + ( (~(tlb_tag4_tlbre_parerr)) | cswitch_q[7] ); + + assign tlb_mas_thdid = tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] & (~(tlb_ctl_tag4_flush)); + + assign tlbwe_tag3_back_inv_enab = (lru_tag3_dataout_q[0] & (lru_tag3_dataout_q[8] | (~cswitch_q[0])) & ((~(tlb_tag3_q[`tagpos_is])) | + (~(cswitch_q[3]))) & (~tlb_tag3_q[`tagpos_hes]) & (~tlb_tag3_q[`tagpos_esel + 1]) & (~tlb_tag3_q[`tagpos_esel + 2])) | + (lru_tag3_dataout_q[1] & (lru_tag3_dataout_q[9] | (~cswitch_q[0])) & ((~(tlb_tag3_q[`tagpos_is])) | + (~(cswitch_q[3]))) & (~tlb_tag3_q[`tagpos_hes]) & (~tlb_tag3_q[`tagpos_esel + 1]) & tlb_tag3_q[`tagpos_esel + 2]) | + (lru_tag3_dataout_q[2] & (lru_tag3_dataout_q[10] | (~cswitch_q[0])) & ((~(tlb_tag3_q[`tagpos_is])) | + (~(cswitch_q[3]))) & (~tlb_tag3_q[`tagpos_hes]) & tlb_tag3_q[`tagpos_esel + 1] & (~tlb_tag3_q[`tagpos_esel + 2])) | + (lru_tag3_dataout_q[3] & (lru_tag3_dataout_q[11] | (~cswitch_q[0])) & ((~(tlb_tag3_q[`tagpos_is])) | + (~(cswitch_q[3]))) & (~tlb_tag3_q[`tagpos_hes]) & tlb_tag3_q[`tagpos_esel + 1] & tlb_tag3_q[`tagpos_esel + 2]) | + (lru_tag3_dataout_q[0] & (lru_tag3_dataout_q[8] | (~cswitch_q[0])) & ((~(tlb_tag3_q[`tagpos_is])) | + (~(cswitch_q[3]))) & tlb_tag3_q[`tagpos_hes] & cswitch_q[1] & (~lru_tag3_dataout_q[4]) & (~lru_tag3_dataout_q[5])) | + (lru_tag3_dataout_q[1] & (lru_tag3_dataout_q[9] | (~cswitch_q[0])) & ((~(tlb_tag3_q[`tagpos_is])) | + (~(cswitch_q[3]))) & tlb_tag3_q[`tagpos_hes] & cswitch_q[1] & (~lru_tag3_dataout_q[4]) & lru_tag3_dataout_q[5]) | + (lru_tag3_dataout_q[2] & (lru_tag3_dataout_q[10] | (~cswitch_q[0])) & ((~(tlb_tag3_q[`tagpos_is])) | + (~(cswitch_q[3]))) & tlb_tag3_q[`tagpos_hes] & cswitch_q[1] & lru_tag3_dataout_q[4] & (~lru_tag3_dataout_q[6])) | + (lru_tag3_dataout_q[3] & (lru_tag3_dataout_q[11] | (~cswitch_q[0])) & ((~(tlb_tag3_q[`tagpos_is])) | + (~(cswitch_q[3]))) & tlb_tag3_q[`tagpos_hes] & cswitch_q[1] & lru_tag3_dataout_q[4] & lru_tag3_dataout_q[6]); + + assign tlbwe_tag4_back_inv_d[0:`MM_THREADS - 1] = tlb_tag3_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] & (~(tlb_ctl_tag3_flush)); + assign tlbwe_tag4_back_inv_d[`MM_THREADS] = ( tlbwe_tag3_back_inv_enab & tlb_tag3_q[`tagpos_type_tlbwe] & (~((tlb_tag3_q[`tagpos_wq:`tagpos_wq + 1] == 2'b10))) & mmucr1_q[pos_tlbwe_binv] & + ( ((~(tlb_tag3_q[`tagpos_gs])) & (~(tlb_tag3_q[`tagpos_atsel]))) | (tlb_tag3_q[`tagpos_gs] & tlb_tag3_q[`tagpos_hes] & lrat_tag3_hit_status[1] & (~lrat_tag3_hit_status[2])) ) & + |( tlb_tag3_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] & (~(tlb_ctl_tag3_flush)) ) ); + + assign tlbwe_tag4_back_inv_attr_d[18] = ( lru_tag3_dataout_q[0] & (lru_tag3_dataout_q[8] | (~cswitch_q[2])) & (~tlb_tag3_q[`tagpos_hes]) & (~tlb_tag3_q[`tagpos_esel + 1]) & (~tlb_tag3_q[`tagpos_esel + 2]) ) | + ( lru_tag3_dataout_q[1] & (lru_tag3_dataout_q[9] | (~cswitch_q[2])) & (~tlb_tag3_q[`tagpos_hes]) & (~tlb_tag3_q[`tagpos_esel + 1]) & tlb_tag3_q[`tagpos_esel + 2] ) | + ( lru_tag3_dataout_q[2] & (lru_tag3_dataout_q[10] | (~cswitch_q[2])) & (~tlb_tag3_q[`tagpos_hes]) & tlb_tag3_q[`tagpos_esel + 1] & (~tlb_tag3_q[`tagpos_esel + 2]) ) | + ( lru_tag3_dataout_q[3] & (lru_tag3_dataout_q[11] | (~cswitch_q[2])) & (~tlb_tag3_q[`tagpos_hes]) & tlb_tag3_q[`tagpos_esel + 1] & tlb_tag3_q[`tagpos_esel + 2] ) | + ( lru_tag3_dataout_q[0] & (lru_tag3_dataout_q[8] | (~cswitch_q[2])) & tlb_tag3_q[`tagpos_hes] & (~lru_tag3_dataout_q[4]) & (~lru_tag3_dataout_q[5]) ) | + ( lru_tag3_dataout_q[1] & (lru_tag3_dataout_q[9] | (~cswitch_q[2])) & tlb_tag3_q[`tagpos_hes] & (~lru_tag3_dataout_q[4]) & lru_tag3_dataout_q[5] ) | + ( lru_tag3_dataout_q[2] & (lru_tag3_dataout_q[10] | (~cswitch_q[2])) & tlb_tag3_q[`tagpos_hes] & lru_tag3_dataout_q[4] & (~lru_tag3_dataout_q[6]) ) | + ( lru_tag3_dataout_q[3] & (lru_tag3_dataout_q[11] | (~cswitch_q[2])) & tlb_tag3_q[`tagpos_hes] & lru_tag3_dataout_q[4] & lru_tag3_dataout_q[6] ); + + assign tlbwe_tag4_back_inv_attr_d[19] = 1'b0; + + assign tlbwe_back_inv_valid = tlbwe_tag4_back_inv_q[`MM_THREADS] & ((~(tlb_tag4_way_rw_or[`waypos_ind])) | cswitch_q[4]); // valid to mmq_inval + + assign tlbwe_back_inv_thdid = tlbwe_tag4_back_inv_q[0:`MM_THREADS - 1]; + + assign tlbwe_back_inv_addr = tlb_tag4_way_rw_or[`waypos_epn:`waypos_epn + `EPN_WIDTH - 1]; + + assign tlbwe_back_inv_attr = { 1'b1, 3'b011, + tlb_tag4_way_rw_or[`waypos_gs], tlb_tag4_way_rw_or[`waypos_ts], + tlb_tag4_way_rw_or[`waypos_tid + 6:`waypos_tid + `PID_WIDTH -1], + tlb_tag4_way_rw_or[`waypos_size:`waypos_size + 3], + tlbwe_tag4_back_inv_attr_q[18:19], + tlb_tag4_way_rw_or[`waypos_tid:`waypos_tid + 5], + tlb_tag4_way_rw_or[`waypos_lpid:`waypos_lpid + `LPID_WIDTH - 1], + tlb_tag4_way_rw_or[`waypos_ind] }; // invalidate attributes to mmq_inval + + assign lru_write = lru_write_q & {`LRU_WIDTH{lru_update_clear_enab_q | (~|(tlb_tag5_except_q))}}; + + assign lru_wr_addr = lru_wr_addr_q; + assign lru_datain = lru_datain_q; + + assign tlb_htw_req_valid = ( tlb_tag4_q[`tagpos_type_derat:`tagpos_type_ierat] != 2'b00 & tlb_tag4_q[`tagpos_type_ptereload] == 1'b0 & tlb_tag4_q[`tagpos_ind] == 1'b1 & + tlb_tag4_q[`tagpos_nonspec] == 1'b1 & tlb_tag4_wayhit_q[`TLB_WAYS] == 1'b1 & multihit == 1'b0 ) ? 1'b1 : + 1'b0; + + assign tlb_htw_req_way = tlb_tag4_way_or[`TLB_WORD_WIDTH:`TLB_WAY_WIDTH - 1]; + + assign tlb_htw_req_tag[0:`EPN_WIDTH - 1] = tlb_tag4_q[0:`EPN_WIDTH - 1]; + assign tlb_htw_req_tag[`tagpos_pid:`tagpos_pid + `PID_WIDTH - 1] = tlb_tag4_way_or[`waypos_tid:`waypos_tid + `PID_WIDTH - 1]; + assign tlb_htw_req_tag[`tagpos_is:`tagpos_class + 1] = tlb_tag4_q[`tagpos_is:`tagpos_class + 1]; + assign tlb_htw_req_tag[`tagpos_pr] = tlb_tag4_q[`tagpos_pr]; + assign tlb_htw_req_tag[`tagpos_gs] = tlb_tag4_way_or[`waypos_gs]; + assign tlb_htw_req_tag[`tagpos_as] = tlb_tag4_way_or[`waypos_ts]; + assign tlb_htw_req_tag[`tagpos_cm] = tlb_tag4_q[`tagpos_cm]; + assign tlb_htw_req_tag[`tagpos_thdid:`tagpos_lpid - 1] = tlb_tag4_q[`tagpos_thdid:`tagpos_lpid - 1]; + assign tlb_htw_req_tag[`tagpos_lpid:`tagpos_lpid + `LPID_WIDTH - 1] = tlb_tag4_way_or[`waypos_lpid:`waypos_lpid + `LPID_WIDTH - 1]; + assign tlb_htw_req_tag[`tagpos_ind] = tlb_tag4_q[`tagpos_ind]; + assign tlb_htw_req_tag[`tagpos_atsel] = tlb_tag4_way_or[`waypos_thdid]; + assign tlb_htw_req_tag[`tagpos_esel:`tagpos_esel + 2] = tlb_tag4_way_or[`waypos_thdid + 1:`waypos_thdid + 3]; + assign tlb_htw_req_tag[`tagpos_hes:`TLB_TAG_WIDTH - 1] = tlb_tag4_q[`tagpos_hes:`TLB_TAG_WIDTH - 1]; + + //constant `tagpos_epn : natural := 0; + //constant `tagpos_pid : natural := 52; -- 14 bits + //constant `tagpos_is : natural := 66; + //constant `tagpos_class : natural := 68; + //constant `tagpos_state : natural := 70; -- state: 0:pr 1:gs 2:as 3:cm + //constant `tagpos_thdid : natural := 74; + //constant `tagpos_size : natural := 78; + //constant `tagpos_type : natural := 82; -- derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload + //constant `tagpos_lpid : natural := 90; + //constant `tagpos_ind : natural := 98; + //constant `tagpos_atsel : natural := 99; + //constant `tagpos_esel : natural := 100; + //constant `tagpos_hes : natural := 103; + //constant `tagpos_wq : natural := 104; + //constant `tagpos_lrat : natural := 106; + //constant `tagpos_pt : natural := 107; + //constant `tagpos_recform : natural := 108; + //constant `tagpos_endflag : natural := 109; + // `waypos_epn : natural := 0; + // `waypos_size : natural := 52; + // `waypos_thdid : natural := 56; + // `waypos_class : natural := 60; + // `waypos_extclass : natural := 62; + // `waypos_lpid : natural := 66; + // `waypos_xbit : natural := 84; + // `waypos_tstmode4k : natural := 85; + // `waypos_rpn : natural := 88; + // `waypos_rc : natural := 118; + // `waypos_wlc : natural := 120; + // `waypos_resvattr : natural := 122; + // `waypos_vf : natural := 123; + // `waypos_ind : natural := 124; + // `waypos_ubits : natural := 125; + // `waypos_wimge : natural := 129; + // `waypos_usxwr : natural := 134; + // `waypos_gs : natural := 140; + // `waypos_ts : natural := 141; + // `waypos_tid : natural := 144; -- 14 bits + //--------------------------------------------------------------------- + // Performance events + //--------------------------------------------------------------------- + //-------------------------------------------------- + // t* threadwise event list + //-------------------------------------------------- + // 0 TLB hit direct entry (instr.) (ind=0 entry hit for fetch) + // 1 TLB miss direct entry (instr.) (ind=0 entry missed for fetch) + // 2 TLB miss indirect entry (instr.) (ind=1 entry missed for fetch, results in i-tlb exception) + // 3 H/W tablewalk hit (instr.) (ptereload with PTE.V=1 for fetch) + // 4 H/W tablewalk miss (instr.) (ptereload with PTE.V=0 for fetch, results in PT fault exception -> isi) + // 5 TLB hit direct entry (data) (ind=0 entry hit for load/store/cache op) + // 6 TLB miss direct entry (data) (ind=0 entry miss for load/store/cache op) + // 7 TLB miss indirect entry (data) (ind=1 entry missed for load/store/cache op, results in d-tlb exception) + // 8 H/W tablewalk hit (data) (ptereload with PTE.V=1 for load/store/cache op) + // 9 H/W tablewalk miss (data) (ptereload with PTE.V=0 for load/store/cache op, results in PT fault exception -> dsi) + assign tlb_cmp_perf_event_t0[0] = tlb_tag4_q[`tagpos_thdid + 0] & tlb_tag4_q[`tagpos_type_ierat] & (~tlb_tag4_q[`tagpos_type_ptereload]) & (~tlb_tag4_q[`tagpos_ind]) & tlb_tag4_wayhit_q[`TLB_WAYS] & (~multihit); + assign tlb_cmp_perf_event_t0[1] = tlb_tag4_q[`tagpos_thdid + 0] & tlb_tag4_q[`tagpos_type_ierat] & (~tlb_tag4_q[`tagpos_type_ptereload]) & (~tlb_tag4_q[`tagpos_ind]) & (~tlb_tag4_wayhit_q[`TLB_WAYS]) & (tlb_tag3_q[`tagpos_ind] | tlb_tag4_q[`tagpos_endflag]); + assign tlb_cmp_perf_event_t0[2] = tlb_tag4_q[`tagpos_thdid + 0] & tlb_tag4_q[`tagpos_type_ierat] & (~tlb_tag4_q[`tagpos_type_ptereload]) & tlb_tag4_q[`tagpos_ind] & (~tlb_tag4_wayhit_q[`TLB_WAYS]) & tlb_tag4_q[`tagpos_endflag]; + assign tlb_cmp_perf_event_t0[3] = tlb_tag4_q[`tagpos_thdid + 0] & tlb_tag4_q[`tagpos_type_ierat] & tlb_tag4_q[`tagpos_type_ptereload] & tlb_tag4_q[`tagpos_is]; + assign tlb_cmp_perf_event_t0[4] = tlb_tag4_q[`tagpos_thdid + 0] & tlb_tag4_q[`tagpos_type_ierat] & tlb_tag4_q[`tagpos_type_ptereload] & (~tlb_tag4_q[`tagpos_is]); + assign tlb_cmp_perf_event_t0[5] = tlb_tag4_q[`tagpos_thdid + 0] & tlb_tag4_q[`tagpos_type_derat] & (~tlb_tag4_q[`tagpos_type_ptereload]) & (~tlb_tag4_q[`tagpos_ind]) & tlb_tag4_wayhit_q[`TLB_WAYS] & (~multihit); + assign tlb_cmp_perf_event_t0[6] = tlb_tag4_q[`tagpos_thdid + 0] & tlb_tag4_q[`tagpos_type_derat] & (~tlb_tag4_q[`tagpos_type_ptereload]) & (~tlb_tag4_q[`tagpos_ind]) & (~tlb_tag4_wayhit_q[`TLB_WAYS]) & (tlb_tag3_q[`tagpos_ind] | tlb_tag4_q[`tagpos_endflag]); + assign tlb_cmp_perf_event_t0[7] = tlb_tag4_q[`tagpos_thdid + 0] & tlb_tag4_q[`tagpos_type_derat] & (~tlb_tag4_q[`tagpos_type_ptereload]) & tlb_tag4_q[`tagpos_ind] & (~tlb_tag4_wayhit_q[`TLB_WAYS]) & tlb_tag4_q[`tagpos_endflag]; + assign tlb_cmp_perf_event_t0[8] = tlb_tag4_q[`tagpos_thdid + 0] & tlb_tag4_q[`tagpos_type_derat] & tlb_tag4_q[`tagpos_type_ptereload] & tlb_tag4_q[`tagpos_is]; + assign tlb_cmp_perf_event_t0[9] = tlb_tag4_q[`tagpos_thdid + 0] & tlb_tag4_q[`tagpos_type_derat] & tlb_tag4_q[`tagpos_type_ptereload] & (~tlb_tag4_q[`tagpos_is]); + assign tlb_cmp_perf_event_t1[0] = tlb_tag4_q[`tagpos_thdid + 1] & tlb_tag4_q[`tagpos_type_ierat] & (~tlb_tag4_q[`tagpos_type_ptereload]) & (~tlb_tag4_q[`tagpos_ind]) & tlb_tag4_wayhit_q[`TLB_WAYS] & (~multihit); + assign tlb_cmp_perf_event_t1[1] = tlb_tag4_q[`tagpos_thdid + 1] & tlb_tag4_q[`tagpos_type_ierat] & (~tlb_tag4_q[`tagpos_type_ptereload]) & (~tlb_tag4_q[`tagpos_ind]) & (~tlb_tag4_wayhit_q[`TLB_WAYS]) & (tlb_tag3_q[`tagpos_ind] | tlb_tag4_q[`tagpos_endflag]); + assign tlb_cmp_perf_event_t1[2] = tlb_tag4_q[`tagpos_thdid + 1] & tlb_tag4_q[`tagpos_type_ierat] & (~tlb_tag4_q[`tagpos_type_ptereload]) & tlb_tag4_q[`tagpos_ind] & (~tlb_tag4_wayhit_q[`TLB_WAYS]) & tlb_tag4_q[`tagpos_endflag]; + assign tlb_cmp_perf_event_t1[3] = tlb_tag4_q[`tagpos_thdid + 1] & tlb_tag4_q[`tagpos_type_ierat] & tlb_tag4_q[`tagpos_type_ptereload] & tlb_tag4_q[`tagpos_is]; + assign tlb_cmp_perf_event_t1[4] = tlb_tag4_q[`tagpos_thdid + 1] & tlb_tag4_q[`tagpos_type_ierat] & tlb_tag4_q[`tagpos_type_ptereload] & (~tlb_tag4_q[`tagpos_is]); + assign tlb_cmp_perf_event_t1[5] = tlb_tag4_q[`tagpos_thdid + 1] & tlb_tag4_q[`tagpos_type_derat] & (~tlb_tag4_q[`tagpos_type_ptereload]) & (~tlb_tag4_q[`tagpos_ind]) & tlb_tag4_wayhit_q[`TLB_WAYS] & (~multihit); + assign tlb_cmp_perf_event_t1[6] = tlb_tag4_q[`tagpos_thdid + 1] & tlb_tag4_q[`tagpos_type_derat] & (~tlb_tag4_q[`tagpos_type_ptereload]) & (~tlb_tag4_q[`tagpos_ind]) & (~tlb_tag4_wayhit_q[`TLB_WAYS]) & (tlb_tag3_q[`tagpos_ind] | tlb_tag4_q[`tagpos_endflag]); + assign tlb_cmp_perf_event_t1[7] = tlb_tag4_q[`tagpos_thdid + 1] & tlb_tag4_q[`tagpos_type_derat] & (~tlb_tag4_q[`tagpos_type_ptereload]) & tlb_tag4_q[`tagpos_ind] & (~tlb_tag4_wayhit_q[`TLB_WAYS]) & tlb_tag4_q[`tagpos_endflag]; + assign tlb_cmp_perf_event_t1[8] = tlb_tag4_q[`tagpos_thdid + 1] & tlb_tag4_q[`tagpos_type_derat] & tlb_tag4_q[`tagpos_type_ptereload] & tlb_tag4_q[`tagpos_is]; + assign tlb_cmp_perf_event_t1[9] = tlb_tag4_q[`tagpos_thdid + 1] & tlb_tag4_q[`tagpos_type_derat] & tlb_tag4_q[`tagpos_type_ptereload] & (~tlb_tag4_q[`tagpos_is]); + assign tlb_cmp_perf_state = {tlb_tag4_q[`tagpos_gs], tlb_tag4_q[`tagpos_pr]}; + + + //-------------------------------------------------- + // core single event list + //-------------------------------------------------- + // 0 IERAT miss total (part of direct entry search total) + // 1 DERAT miss total (part of direct entry search total) + // 2 TLB miss direct entry total (total TLB ind=0 misses) + // 3 TLB hit direct entry first page size + //-------------------------------------------------- + // 4 TLB indirect entry hits total (=page table searches) + // 5 H/W tablewalk successful installs total (with no PTfault, TLB ineligible, or LRAT miss) + // 6 LRAT translation request total (for GS=1 tlbwe and ptereload) + // 7 LRAT misses total (for GS=1 tlbwe and ptereload) + //-------------------------------------------------- + // 8 Page table faults total (PTE.V=0 for ptereload, resulting in isi/dsi) + // 9 TLB ineligible total (all TLB ways are iprot=1 for ptereloads, resulting in isi/dsi) + // 10 tlbwe conditional failed total (total tlbwe WQ=01 with no reservation match) + // 11 tlbwe conditional success total (total tlbwe WQ=01 with reservation match) + //-------------------------------------------------- + // 12 tlbilx local invalidations sourced total (sourced tlbilx on this core total) + // 13 tlbivax invalidations sourced total (sourced tlbivax on this core total) + // 14 tlbivax snoops total (total tlbivax snoops received from bus, local bit = don't care) + // 15 TLB flush requests total (TLB requested flushes due to TLB busy or instruction hazards) + //-------------------------------------------------- + // 16 IERAT NONSPECULATIVE miss total (part of direct entry search total) + // 17 DERAT NONSPECULATIVE miss total (part of direct entry search total) + // 18 TLB NONSPECULATIVE miss direct entry total (total TLB ind=0 misses) + // 19 TLB NONSPECULATIVE hit direct entry first page size + //-------------------------------------------------- + // 20 IERAT SPECULATIVE miss total (part of direct entry search total) + // 21 DERAT SPECULATIVE miss total (part of direct entry search total) + // 22 TLB SPECULATIVE miss direct entry total (total TLB ind=0 misses) + // 23 TLB SPECULATIVE hit direct entry first page size + //-------------------------------------------------- + // 24 ERAT miss total (TLB direct entry search total for both I and D sides) + // 25 ERAT NONSPECULATIVE miss total (TLB direct entry nonspeculative search total for both I and D sides) + // 26 ERAT SPECULATIVE miss total (TLB direct entry speculative search total for both I and D sides) + // 27 TLB hit direct entry total (total TLB ind=0 hits for both I and D sides) + // 28 TLB NONSPECULATIVE hit direct entry total (total TLB ind=0 nonspeculative hits for both I and D sides) + // 29 TLB SPECULATIVE hit direct entry total (total TLB ind=0 speculative hits for both I and D sides) + // 30 PTE reload attempts total (with valid htw-reservation, no duplicate set, and pt=1) + //-------------------------------------------------- + + assign tlb_cmp_perf_miss_direct = |(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) & |(tlb_tag4_q[`tagpos_type_derat:`tagpos_type_ierat]) & + (~tlb_tag4_q[`tagpos_type_ptereload]) & (~tlb_tag4_q[`tagpos_ind]) & (~tlb_tag4_wayhit_q[`TLB_WAYS]) & + (tlb_tag3_q[`tagpos_ind] | tlb_tag4_q[`tagpos_endflag]); // any TLB miss direct entry + + assign tlb_cmp_perf_hit_direct = |(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) & |(tlb_tag4_q[`tagpos_type_derat:`tagpos_type_ierat]) & + (~tlb_tag4_q[`tagpos_type_ptereload]) & (~tlb_tag4_q[`tagpos_ind]) & tlb_tag4_wayhit_q[`TLB_WAYS] & (~multihit); // any TLB hit direct entry + + assign tlb_cmp_perf_hit_indirect = |(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) & |(tlb_tag4_q[`tagpos_type_derat:`tagpos_type_ierat]) & + (~tlb_tag4_q[`tagpos_type_ptereload]) & tlb_tag4_q[`tagpos_ind] & tlb_tag4_wayhit_q[`TLB_WAYS] & (~multihit); // any TLB hit indirect entry + + assign tlb_cmp_perf_hit_first_page = |(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) & |(tlb_tag4_q[`tagpos_type_derat:`tagpos_type_ierat]) & + (~tlb_tag4_q[`tagpos_type_ptereload]) & (~tlb_tag4_q[`tagpos_ind]) & tlb_tag4_wayhit_q[`TLB_WAYS] & (~multihit) & + (tlb_tag4_q[`tagpos_esel:`tagpos_esel + 2] == 3'b001); // any TLB hit direct entry on first page size + + // tag5 phase perf counts + // ptereload attempts + assign tlb_tag5_perf_d[0] = ( (|(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1) & tlb_tag4_q[`tagpos_type_ptereload] == 1'b1 & + (tlb_tag4_q[`tagpos_wq:`tagpos_wq + 1] == 2'b10) & (tlb_tag4_q[`tagpos_pt] == 1'b1) ) ? {1'b1} : + {1'b0}; + + // lrat compare attempts + assign tlb_tag5_perf_d[1] = ((((|(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] & tlb_resv_match_vec) == 1'b1 & tlb_tag4_q[`tagpos_wq:`tagpos_wq + 1] == 2'b01 & mmucfg_twc == 1'b1) | + tlb_tag4_q[`tagpos_wq:`tagpos_wq + 1] == 2'b00 | tlb_tag4_q[`tagpos_wq:`tagpos_wq + 1] == 2'b11) & + tlb_tag4_q[`tagpos_type_tlbwe] == 1'b1 & tlb_tag4_q[`tagpos_gs] == 1'b1 & tlb_tag4_q[`tagpos_pr] == 1'b0 & tlb_tag4_epcr_dgtmi == 1'b0 & + mmucfg_lrat == 1'b1 & tlb_tag4_q[`tagpos_is] == 1'b1)) ? |(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS-1] & (~(tlb_ctl_tag4_flush))) : + ((tlb_tag4_q[`tagpos_type_ptereload] == 1'b1 & tlb_tag4_q[`tagpos_gs] == 1'b1 & mmucfg_lrat == 1'b1 & tlb_tag4_q[`tagpos_is] == 1'b1 & + tlb_tag4_q[`tagpos_wq:`tagpos_wq + 1] == 2'b10 & tlb_tag4_q[`tagpos_pt] == 1'b1)) ? |(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS-1]) : + {1'b0}; + + + assign tlb_cmp_perf_ptereload = tlb_tag5_perf_q[0]; // total ptereload attempts + assign tlb_cmp_perf_ptereload_noexcep = tlb_tag5_perf_q[0] & (~(|(tlb_tag5_except_q))); // successful ptereload attempts + assign tlb_cmp_perf_lrat_request = tlb_tag5_perf_q[1]; // lrat compare attempts + assign tlb_cmp_perf_lrat_miss = |(lrat_miss_q); + assign tlb_cmp_perf_pt_fault = |(pt_fault_q); + assign tlb_cmp_perf_pt_inelig = |(tlb_inelig_q); + + + //--------------------------------------------------------------------- + // Debug trigger and data signals + //--------------------------------------------------------------------- + assign tlb_cmp_dbg_tag4 = tlb_tag4_q; + assign tlb_cmp_dbg_tag4_wayhit = tlb_tag4_wayhit_q; + assign tlb_cmp_dbg_addr4 = tlb_addr4_q; + assign tlb_cmp_dbg_tag4_way = ( |(tlb_tag4_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]) == 1'b1 & + (tlb_tag4_q[`tagpos_type_tlbre] | tlb_tag4_q[`tagpos_type_tlbwe] | tlb_tag4_q[`tagpos_type_ptereload]) == 1'b1 ) ? tlb_tag4_way_rw_or : + tlb_tag4_way_or; + + assign tlb_cmp_dbg_tag4_parerr = tag4_parerr_q; + assign tlb_cmp_dbg_tag4_lru_dataout_q = lru_tag4_dataout_q[0:`LRU_WIDTH - 5]; + assign tlb_cmp_dbg_tag5_lru_datain_q = lru_datain_q[0:`LRU_WIDTH - 5]; + assign tlb_cmp_dbg_tag5_lru_write = lru_write_q[0]; + assign tlb_cmp_dbg_tag5_any_exception = |(tlb_miss_q) | |(hv_priv_q) | |(lrat_miss_q) | |(pt_fault_q) | |(tlb_inelig_q); + assign tlb_cmp_dbg_tag5_except_type_q = { |(hv_priv_q), |(lrat_miss_q), |(pt_fault_q), |(tlb_inelig_q) }; +`ifdef MM_THREADS2 + assign tlb_cmp_dbg_tag5_except_thdid_q[0] = 1'b0; + assign tlb_cmp_dbg_tag5_except_thdid_q[1] = hv_priv_q[1] | lrat_miss_q[1] | pt_fault_q[1] | tlb_inelig_q[1] | tlb_miss_q[1]; +`else + assign tlb_cmp_dbg_tag5_except_thdid_q[0] = 1'b0; + assign tlb_cmp_dbg_tag5_except_thdid_q[1] = 1'b0; +`endif + assign tlb_cmp_dbg_tag5_erat_rel_val = tlb_erat_val_q; + assign tlb_cmp_dbg_tag5_erat_rel_data = tlb_erat_rel_q; + assign tlb_cmp_dbg_erat_dup_q = tlb_erat_dup_q[0:19]; + assign tlb_cmp_dbg_addr_enable = addr_enable; + assign tlb_cmp_dbg_pgsize_enable = pgsize_enable; + assign tlb_cmp_dbg_class_enable = class_enable; + assign tlb_cmp_dbg_extclass_enable = extclass_enable; + assign tlb_cmp_dbg_state_enable = state_enable; + assign tlb_cmp_dbg_thdid_enable = thdid_enable; + assign tlb_cmp_dbg_pid_enable = pid_enable; + assign tlb_cmp_dbg_lpid_enable = lpid_enable; + assign tlb_cmp_dbg_ind_enable = ind_enable; + assign tlb_cmp_dbg_iprot_enable = iprot_enable; + assign tlb_cmp_dbg_way0_entry_v = lru_tag3_dataout_q[0]; + assign tlb_cmp_dbg_way0_addr_match = tlb_way0_addr_match; + assign tlb_cmp_dbg_way0_pgsize_match = tlb_way0_pgsize_match; + assign tlb_cmp_dbg_way0_class_match = tlb_way0_class_match; + assign tlb_cmp_dbg_way0_extclass_match = tlb_way0_extclass_match; + assign tlb_cmp_dbg_way0_state_match = tlb_way0_state_match; + assign tlb_cmp_dbg_way0_thdid_match = tlb_way0_thdid_match; + assign tlb_cmp_dbg_way0_pid_match = tlb_way0_pid_match; + assign tlb_cmp_dbg_way0_lpid_match = tlb_way0_lpid_match; + assign tlb_cmp_dbg_way0_ind_match = tlb_way0_ind_match; + assign tlb_cmp_dbg_way0_iprot_match = tlb_way0_iprot_match; + assign tlb_cmp_dbg_way1_entry_v = lru_tag3_dataout_q[1]; + assign tlb_cmp_dbg_way1_addr_match = tlb_way1_addr_match; + assign tlb_cmp_dbg_way1_pgsize_match = tlb_way1_pgsize_match; + assign tlb_cmp_dbg_way1_class_match = tlb_way1_class_match; + assign tlb_cmp_dbg_way1_extclass_match = tlb_way1_extclass_match; + assign tlb_cmp_dbg_way1_state_match = tlb_way1_state_match; + assign tlb_cmp_dbg_way1_thdid_match = tlb_way1_thdid_match; + assign tlb_cmp_dbg_way1_pid_match = tlb_way1_pid_match; + assign tlb_cmp_dbg_way1_lpid_match = tlb_way1_lpid_match; + assign tlb_cmp_dbg_way1_ind_match = tlb_way1_ind_match; + assign tlb_cmp_dbg_way1_iprot_match = tlb_way1_iprot_match; + assign tlb_cmp_dbg_way2_entry_v = lru_tag3_dataout_q[2]; + assign tlb_cmp_dbg_way2_addr_match = tlb_way2_addr_match; + assign tlb_cmp_dbg_way2_pgsize_match = tlb_way2_pgsize_match; + assign tlb_cmp_dbg_way2_class_match = tlb_way2_class_match; + assign tlb_cmp_dbg_way2_extclass_match = tlb_way2_extclass_match; + assign tlb_cmp_dbg_way2_state_match = tlb_way2_state_match; + assign tlb_cmp_dbg_way2_thdid_match = tlb_way2_thdid_match; + assign tlb_cmp_dbg_way2_pid_match = tlb_way2_pid_match; + assign tlb_cmp_dbg_way2_lpid_match = tlb_way2_lpid_match; + assign tlb_cmp_dbg_way2_ind_match = tlb_way2_ind_match; + assign tlb_cmp_dbg_way2_iprot_match = tlb_way2_iprot_match; + assign tlb_cmp_dbg_way3_entry_v = lru_tag3_dataout_q[3]; + assign tlb_cmp_dbg_way3_addr_match = tlb_way3_addr_match; + assign tlb_cmp_dbg_way3_pgsize_match = tlb_way3_pgsize_match; + assign tlb_cmp_dbg_way3_class_match = tlb_way3_class_match; + assign tlb_cmp_dbg_way3_extclass_match = tlb_way3_extclass_match; + assign tlb_cmp_dbg_way3_state_match = tlb_way3_state_match; + assign tlb_cmp_dbg_way3_thdid_match = tlb_way3_thdid_match; + assign tlb_cmp_dbg_way3_pid_match = tlb_way3_pid_match; + assign tlb_cmp_dbg_way3_lpid_match = tlb_way3_lpid_match; + assign tlb_cmp_dbg_way3_ind_match = tlb_way3_ind_match; + assign tlb_cmp_dbg_way3_iprot_match = tlb_way3_iprot_match; + //--------------------------- + // FIR error reporting macros + //--------------------------- + + tri_direct_err_rpt #(.WIDTH(3)) tlb_direct_err_rpt( + .vd(vdd), + .gd(gnd), + .err_in( {tlb_multihit_err_ored, tlb_par_err_ored, lru_par_err_ored} ), + .err_out( {mm_pc_tlb_multihit_err_ored, mm_pc_tlb_par_err_ored, mm_pc_lru_par_err_ored} ) + ); + + //constant `tagpos_epn : natural := 0; + //constant `tagpos_pid : natural := 52; -- 14 bits + //constant `tagpos_is : natural := 66; + //constant `tagpos_class : natural := 68; + //constant `tagpos_state : natural := 70; -- state: 0:pr 1:gs 2:as 3:cm + //constant `tagpos_thdid : natural := 74; + //constant `tagpos_size : natural := 78; + //constant `tagpos_type : natural := 82; -- derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload + //constant `tagpos_lpid : natural := 90; + //constant `tagpos_ind : natural := 98; + //constant `tagpos_atsel : natural := 99; + //constant `tagpos_esel : natural := 100; + //constant `tagpos_hes : natural := 103; + //constant `tagpos_wq : natural := 104; + //constant `tagpos_lrat : natural := 106; + //constant `tagpos_pt : natural := 107; + //constant `tagpos_recform : natural := 108; + //constant `tagpos_endflag : natural := 109; + // unused spare signal assignments + assign unused_dc[0] = |(lcb_delay_lclkr_dc[1:4]); + assign unused_dc[1] = |(lcb_mpw1_dc_b[1:4]); + assign unused_dc[2] = pc_func_sl_force; + assign unused_dc[3] = pc_func_sl_thold_0_b; + assign unused_dc[4] = tc_scan_dis_dc_b; + assign unused_dc[5] = tc_scan_diag_dc; + assign unused_dc[6] = tc_lbist_en_dc; + assign unused_dc[7] = tlb_tag3_clone1_q[70]; + assign unused_dc[8] = tlb_tag3_clone1_q[73]; + assign unused_dc[9] = |(tlb_tag3_clone1_q[99:100]); + assign unused_dc[10] = |(tlb_tag3_clone1_q[104:109]); + assign unused_dc[11] = tlb_tag3_clone2_q[70]; + assign unused_dc[12] = tlb_tag3_clone2_q[73]; + assign unused_dc[13] = |(tlb_tag3_clone2_q[99:100]); + assign unused_dc[14] = |(tlb_tag3_clone2_q[104:109]); + assign unused_dc[15] = 1'b0; + assign unused_dc[16] = tlb_tag3_cmpmask_q[4]; + assign unused_dc[17] = tlb_tag3_cmpmask_clone_q[4]; + assign unused_dc[18] = |({mmucr1_clone_q[11], mmucr1_clone_q[17]}); + assign unused_dc[19] = |({tlb_tag4_type_sig[0:3], tlb_tag4_type_sig[5]}); + assign unused_dc[20] = tlb_tag4_esel_sig[0]; + assign unused_dc[21] = |(tlb_tag4_wq_sig); + assign unused_dc[22] = |(tlb_tag4_is_sig[2:3]); + assign unused_dc[23] = |(ptereload_req_pte_lat[0:9]); + assign unused_dc[24] = |({ptereload_req_pte_lat[50], ptereload_req_pte_lat[55], ptereload_req_pte_lat[62]}); +`ifdef MM_THREADS2 + assign unused_dc[25] = |({mmucr3_0[53], mmucr3_0[59]}) | |({mmucr3_1[53], mmucr3_1[59]}); +`else + assign unused_dc[25] = |({mmucr3_0[53], mmucr3_0[59]}); +`endif + assign unused_dc[26] = mmucr1_clone_q[pos_tlb_pei]; + assign unused_dc[27] = 1'b0; + assign unused_dc[28] = |(lru_datain_alt_d[4:9]); + assign unused_dc[29] = tlb0cfg_pt; + assign unused_dc[30] = |(tlb_dsi_q); + assign unused_dc[31] = |(tlb_isi_q); + assign unused_dc[32] = |(lrat_tag3_lpn_sig); + assign unused_dc[33] = |(lrat_tag3_rpn_sig); + assign unused_dc[34] = |(lrat_tag4_lpn_sig); + assign unused_dc[35] = lrat_tag3_hit_status[0]; + assign unused_dc[36] = lrat_tag3_hit_status[3]; + assign unused_dc[37] = |(lrat_tag3_hit_entry); + assign unused_dc[38] = |(lrat_tag4_hit_entry); + assign unused_dc[39] = |(tlb_tag3_clone1_q[`tagpos_itag:`tagpos_emq + `EMQ_ENTRIES - 1]); + assign unused_dc[40] = |(tlb_tag3_clone2_q[`tagpos_itag:`tagpos_emq + `EMQ_ENTRIES - 1]); + assign unused_dc[41] = ierat_req0_nonspec | ierat_req1_nonspec | ierat_req2_nonspec | ierat_req3_nonspec; + //--------------------------------------------------------------------- + // Latches + //--------------------------------------------------------------------- + // tag3 phase: tlb array data output way latches + + tri_rlmreg_p #(.WIDTH(`TLB_WAY_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_way0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[12]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_way0_offset:tlb_way0_offset + `TLB_WAY_WIDTH - 1]), + .scout(sov_0[tlb_way0_offset:tlb_way0_offset + `TLB_WAY_WIDTH - 1]), + .din(tlb_way0_d[0:`TLB_WAY_WIDTH - 1]), + .dout(tlb_way0_q[0:`TLB_WAY_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`TLB_WAY_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_way1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[12]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_way1_offset:tlb_way1_offset + `TLB_WAY_WIDTH - 1]), + .scout(sov_0[tlb_way1_offset:tlb_way1_offset + `TLB_WAY_WIDTH - 1]), + .din(tlb_way1_d[0:`TLB_WAY_WIDTH - 1]), + .dout(tlb_way1_q[0:`TLB_WAY_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`TLB_WAY_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_way2_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[13]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[tlb_way2_offset:tlb_way2_offset + `TLB_WAY_WIDTH - 1]), + .scout(sov_1[tlb_way2_offset:tlb_way2_offset + `TLB_WAY_WIDTH - 1]), + .din(tlb_way2_d[0:`TLB_WAY_WIDTH - 1]), + .dout(tlb_way2_q[0:`TLB_WAY_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`TLB_WAY_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_way3_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[13]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[tlb_way3_offset:tlb_way3_offset + `TLB_WAY_WIDTH - 1]), + .scout(sov_1[tlb_way3_offset:tlb_way3_offset + `TLB_WAY_WIDTH - 1]), + .din(tlb_way3_d[0:`TLB_WAY_WIDTH - 1]), + .dout(tlb_way3_q[0:`TLB_WAY_WIDTH - 1]) + ); + // tag3 phase: from tag forwarding pipeline + + tri_rlmreg_p #(.WIDTH(`TLB_TAG_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_tag3_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[9]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_2[tlb_tag3_offset:tlb_tag3_offset + `TLB_TAG_WIDTH - 1]), + .scout(sov_2[tlb_tag3_offset:tlb_tag3_offset + `TLB_TAG_WIDTH - 1]), + .din(tlb_tag3_d[0:`TLB_TAG_WIDTH - 1]), + .dout(tlb_tag3_q[0:`TLB_TAG_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`TLB_TAG_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_tag3_clone1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[12]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_tag3_clone1_offset:tlb_tag3_clone1_offset + `TLB_TAG_WIDTH - 1]), + .scout(sov_0[tlb_tag3_clone1_offset:tlb_tag3_clone1_offset + `TLB_TAG_WIDTH - 1]), + .din(tlb_tag3_clone1_d[0:`TLB_TAG_WIDTH - 1]), + .dout(tlb_tag3_clone1_q[0:`TLB_TAG_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`TLB_TAG_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_tag3_clone2_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[13]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[tlb_tag3_clone2_offset:tlb_tag3_clone2_offset + `TLB_TAG_WIDTH - 1]), + .scout(sov_1[tlb_tag3_clone2_offset:tlb_tag3_clone2_offset + `TLB_TAG_WIDTH - 1]), + .din(tlb_tag3_clone2_d[0:`TLB_TAG_WIDTH - 1]), + .dout(tlb_tag3_clone2_q[0:`TLB_TAG_WIDTH - 1]) + ); + // tag3 phase: from tlb_ctl pipeline addr forwarding + + tri_rlmreg_p #(.WIDTH(`TLB_ADDR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_addr3_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[9]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_2[tlb_addr3_offset:tlb_addr3_offset + `TLB_ADDR_WIDTH - 1]), + .scout(sov_2[tlb_addr3_offset:tlb_addr3_offset + `TLB_ADDR_WIDTH - 1]), + .din(tlb_addr3_d[0:`TLB_ADDR_WIDTH - 1]), + .dout(tlb_addr3_q[0:`TLB_ADDR_WIDTH - 1]) + ); + // lru g8t array is 2 cyc, data out is in tag3 now + // tag3 phase: from lru data output + + tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) lru_tag3_dataout_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[9]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_2[lru_tag3_dataout_offset:lru_tag3_dataout_offset + 16 - 1]), + .scout(sov_2[lru_tag3_dataout_offset:lru_tag3_dataout_offset + 16 - 1]), + .din(lru_tag3_dataout_d[0:15]), + .dout(lru_tag3_dataout_q[0:15]) + ); + // tag3 phase: size decoded compare mask tag bits + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) tlb_tag3_cmpmask_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[12]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_tag3_cmpmask_offset:tlb_tag3_cmpmask_offset + 5 - 1]), + .scout(sov_0[tlb_tag3_cmpmask_offset:tlb_tag3_cmpmask_offset + 5 - 1]), + .din(tlb_tag3_cmpmask_d), + .dout(tlb_tag3_cmpmask_q) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) tlb_tag3_cmpmask_clone_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[13]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[tlb_tag3_cmpmask_clone_offset:tlb_tag3_cmpmask_clone_offset + 5 - 1]), + .scout(sov_1[tlb_tag3_cmpmask_clone_offset:tlb_tag3_cmpmask_clone_offset + 5 - 1]), + .din(tlb_tag3_cmpmask_clone_d), + .dout(tlb_tag3_cmpmask_clone_q) + ); + // tag3 phase: size decoded compare mask way bits + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) tlb_way0_cmpmask_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[12]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_way0_cmpmask_offset:tlb_way0_cmpmask_offset + 5 - 1]), + .scout(sov_0[tlb_way0_cmpmask_offset:tlb_way0_cmpmask_offset + 5 - 1]), + .din(tlb_way0_cmpmask_d), + .dout(tlb_way0_cmpmask_q) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) tlb_way1_cmpmask_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[12]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_way1_cmpmask_offset:tlb_way1_cmpmask_offset + 5 - 1]), + .scout(sov_0[tlb_way1_cmpmask_offset:tlb_way1_cmpmask_offset + 5 - 1]), + .din(tlb_way1_cmpmask_d), + .dout(tlb_way1_cmpmask_q) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) tlb_way2_cmpmask_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[13]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[tlb_way2_cmpmask_offset:tlb_way2_cmpmask_offset + 5 - 1]), + .scout(sov_1[tlb_way2_cmpmask_offset:tlb_way2_cmpmask_offset + 5 - 1]), + .din(tlb_way2_cmpmask_d), + .dout(tlb_way2_cmpmask_q) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) tlb_way3_cmpmask_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[13]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[tlb_way3_cmpmask_offset:tlb_way3_cmpmask_offset + 5 - 1]), + .scout(sov_1[tlb_way3_cmpmask_offset:tlb_way3_cmpmask_offset + 5 - 1]), + .din(tlb_way3_cmpmask_d), + .dout(tlb_way3_cmpmask_q) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) tlb_way0_xbitmask_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[12]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_way0_xbitmask_offset:tlb_way0_xbitmask_offset + 5 - 1]), + .scout(sov_0[tlb_way0_xbitmask_offset:tlb_way0_xbitmask_offset + 5 - 1]), + .din(tlb_way0_xbitmask_d), + .dout(tlb_way0_xbitmask_q) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) tlb_way1_xbitmask_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[12]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_way1_xbitmask_offset:tlb_way1_xbitmask_offset + 5 - 1]), + .scout(sov_0[tlb_way1_xbitmask_offset:tlb_way1_xbitmask_offset + 5 - 1]), + .din(tlb_way1_xbitmask_d), + .dout(tlb_way1_xbitmask_q) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) tlb_way2_xbitmask_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[13]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[tlb_way2_xbitmask_offset:tlb_way2_xbitmask_offset + 5 - 1]), + .scout(sov_1[tlb_way2_xbitmask_offset:tlb_way2_xbitmask_offset + 5 - 1]), + .din(tlb_way2_xbitmask_d), + .dout(tlb_way2_xbitmask_q) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) tlb_way3_xbitmask_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[13]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[tlb_way3_xbitmask_offset:tlb_way3_xbitmask_offset + 5 - 1]), + .scout(sov_1[tlb_way3_xbitmask_offset:tlb_way3_xbitmask_offset + 5 - 1]), + .din(tlb_way3_xbitmask_d), + .dout(tlb_way3_xbitmask_q) + ); + // tag4 phase + + tri_rlmreg_p #(.WIDTH(`TLB_TAG_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_tag4_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[10]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_2[tlb_tag4_offset:tlb_tag4_offset + `TLB_TAG_WIDTH - 1]), + .scout(sov_2[tlb_tag4_offset:tlb_tag4_offset + `TLB_TAG_WIDTH - 1]), + .din(tlb_tag4_d[0:`TLB_TAG_WIDTH - 1]), + .dout(tlb_tag4_q[0:`TLB_TAG_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH((`TLB_WAYS+1)), .INIT(0), .NEEDS_SRESET(1)) tlb_tag4_wayhit_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[10]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_2[tlb_tag4_wayhit_offset:tlb_tag4_wayhit_offset + (`TLB_WAYS+1) - 1]), + .scout(sov_2[tlb_tag4_wayhit_offset:tlb_tag4_wayhit_offset + (`TLB_WAYS+1) - 1]), + .din(tlb_tag4_wayhit_d[0:`TLB_WAYS]), + .dout(tlb_tag4_wayhit_q[0:`TLB_WAYS]) + ); + + tri_rlmreg_p #(.WIDTH(`TLB_ADDR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_addr4_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[10]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_2[tlb_addr4_offset:tlb_addr4_offset + `TLB_ADDR_WIDTH - 1]), + .scout(sov_2[tlb_addr4_offset:tlb_addr4_offset + `TLB_ADDR_WIDTH - 1]), + .din(tlb_addr4_d[0:`TLB_ADDR_WIDTH - 1]), + .dout(tlb_addr4_q[0:`TLB_ADDR_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`TLB_WAY_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_dataina_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[14]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_dataina_offset:tlb_dataina_offset + `TLB_WAY_WIDTH - 1]), + .scout(sov_0[tlb_dataina_offset:tlb_dataina_offset + `TLB_WAY_WIDTH - 1]), + .din(tlb_dataina_d[0:`TLB_WAY_WIDTH - 1]), + .dout(tlb_dataina_q[0:`TLB_WAY_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`TLB_WAY_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_datainb_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[15]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[tlb_datainb_offset:tlb_datainb_offset + `TLB_WAY_WIDTH - 1]), + .scout(sov_1[tlb_datainb_offset:tlb_datainb_offset + `TLB_WAY_WIDTH - 1]), + .din(tlb_datainb_d[0:`TLB_WAY_WIDTH - 1]), + .dout(tlb_datainb_q[0:`TLB_WAY_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`LRU_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lru_tag4_dataout_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[10]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_2[lru_tag4_dataout_offset:lru_tag4_dataout_offset + `LRU_WIDTH - 1]), + .scout(sov_2[lru_tag4_dataout_offset:lru_tag4_dataout_offset + `LRU_WIDTH - 1]), + .din(lru_tag4_dataout_d[0:15]), + .dout(lru_tag4_dataout_q[0:15]) + ); + + tri_rlmreg_p #(.WIDTH(`TLB_WAY_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_tag4_way_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_tag4_way_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_tag4_way_offset:tlb_tag4_way_offset + `TLB_WAY_WIDTH - 1]), + .scout(sov_0[tlb_tag4_way_offset:tlb_tag4_way_offset + `TLB_WAY_WIDTH - 1]), + .din(tlb_tag4_way_d[0:`TLB_WAY_WIDTH - 1]), + .dout(tlb_tag4_way_q[0:`TLB_WAY_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`TLB_WAY_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_tag4_way_clone_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_tag4_way_clone_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[tlb_tag4_way_clone_offset:tlb_tag4_way_clone_offset + `TLB_WAY_WIDTH - 1]), + .scout(sov_1[tlb_tag4_way_clone_offset:tlb_tag4_way_clone_offset + `TLB_WAY_WIDTH - 1]), + .din(tlb_tag4_way_clone_d[0:`TLB_WAY_WIDTH - 1]), + .dout(tlb_tag4_way_clone_q[0:`TLB_WAY_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`TLB_WAY_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_tag4_way_rw_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_tag4_way_rw_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_tag4_way_rw_offset:tlb_tag4_way_rw_offset + `TLB_WAY_WIDTH - 1]), + .scout(sov_0[tlb_tag4_way_rw_offset:tlb_tag4_way_rw_offset + `TLB_WAY_WIDTH - 1]), + .din(tlb_tag4_way_rw_d[0:`TLB_WAY_WIDTH - 1]), + .dout(tlb_tag4_way_rw_q[0:`TLB_WAY_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`TLB_WAY_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_tag4_way_rw_clone_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_tag4_way_rw_clone_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[tlb_tag4_way_rw_clone_offset:tlb_tag4_way_rw_clone_offset + `TLB_WAY_WIDTH - 1]), + .scout(sov_1[tlb_tag4_way_rw_clone_offset:tlb_tag4_way_rw_clone_offset + `TLB_WAY_WIDTH - 1]), + .din(tlb_tag4_way_rw_clone_d[0:`TLB_WAY_WIDTH - 1]), + .dout(tlb_tag4_way_rw_clone_q[0:`TLB_WAY_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS+1), .INIT(0), .NEEDS_SRESET(1)) tlbwe_tag4_back_inv_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[10]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_2[tlbwe_tag4_back_inv_offset:tlbwe_tag4_back_inv_offset + `MM_THREADS]), + .scout(sov_2[tlbwe_tag4_back_inv_offset:tlbwe_tag4_back_inv_offset + `MM_THREADS]), + .din(tlbwe_tag4_back_inv_d), + .dout(tlbwe_tag4_back_inv_q) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) tlbwe_tag4_back_inv_attr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[10]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_2[tlbwe_tag4_back_inv_attr_offset:tlbwe_tag4_back_inv_attr_offset + 2 - 1]), + .scout(sov_2[tlbwe_tag4_back_inv_attr_offset:tlbwe_tag4_back_inv_attr_offset + 2 - 1]), + .din(tlbwe_tag4_back_inv_attr_d), + .dout(tlbwe_tag4_back_inv_attr_q) + ); + // tag5 phase + + tri_rlmreg_p #(.WIDTH((2*`THDID_WIDTH+1+1)), .INIT(0), .NEEDS_SRESET(1)) tlb_erat_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[14]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_2[tlb_erat_val_offset:tlb_erat_val_offset + (2*`THDID_WIDTH+1+1) - 1]), + .scout(sov_2[tlb_erat_val_offset:tlb_erat_val_offset + (2*`THDID_WIDTH+1+1) - 1]), + .din(tlb_erat_val_d[0:2 * `THDID_WIDTH + 1]), + .dout(tlb_erat_val_q[0:2 * `THDID_WIDTH + 1]) + ); + + tri_rlmreg_p #(.WIDTH(`ERAT_REL_DATA_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_erat_rel_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[14]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_erat_rel_offset:tlb_erat_rel_offset + `ERAT_REL_DATA_WIDTH - 1]), + .scout(sov_0[tlb_erat_rel_offset:tlb_erat_rel_offset + `ERAT_REL_DATA_WIDTH - 1]), + .din(tlb_erat_rel_d[0:`ERAT_REL_DATA_WIDTH - 1]), + .dout(tlb_erat_rel_q[0:`ERAT_REL_DATA_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`ERAT_REL_DATA_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_erat_rel_clone_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[15]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[tlb_erat_rel_clone_offset:tlb_erat_rel_clone_offset + `ERAT_REL_DATA_WIDTH - 1]), + .scout(sov_1[tlb_erat_rel_clone_offset:tlb_erat_rel_clone_offset + `ERAT_REL_DATA_WIDTH - 1]), + .din(tlb_erat_rel_clone_d[0:`ERAT_REL_DATA_WIDTH - 1]), + .dout(tlb_erat_rel_clone_q[0:`ERAT_REL_DATA_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH((2*`THDID_WIDTH+13+1)), .INIT(0), .NEEDS_SRESET(1)) tlb_erat_dup_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_2[tlb_erat_dup_offset:tlb_erat_dup_offset + (2*`THDID_WIDTH+13+1) - 1]), + .scout(sov_2[tlb_erat_dup_offset:tlb_erat_dup_offset + (2*`THDID_WIDTH+13+1) - 1]), + .din(tlb_erat_dup_d), + .dout(tlb_erat_dup_q) + ); + + tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) lru_write_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[11]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_2[lru_write_offset:lru_write_offset + 16 - 1]), + .scout(sov_2[lru_write_offset:lru_write_offset + 16 - 1]), + .din(lru_write_d[0:15]), + .dout(lru_write_q[0:15]) + ); + + tri_rlmreg_p #(.WIDTH(`TLB_ADDR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lru_wr_addr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[11]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_2[lru_wr_addr_offset:lru_wr_addr_offset + `TLB_ADDR_WIDTH - 1]), + .scout(sov_2[lru_wr_addr_offset:lru_wr_addr_offset + `TLB_ADDR_WIDTH - 1]), + .din(lru_wr_addr_d[0:`TLB_ADDR_WIDTH - 1]), + .dout(lru_wr_addr_q[0:`TLB_ADDR_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) lru_datain_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[11]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_2[lru_datain_offset:lru_datain_offset + 16 - 1]), + .scout(sov_2[lru_datain_offset:lru_datain_offset + 16 - 1]), + .din(lru_datain_d[0:15]), + .dout(lru_datain_q[0:15]) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) eratmiss_done_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[16]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_2[eratmiss_done_offset:eratmiss_done_offset + `MM_THREADS - 1]), + .scout(sov_2[eratmiss_done_offset:eratmiss_done_offset + `MM_THREADS - 1]), + .din(eratmiss_done_d), + .dout(eratmiss_done_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) tlb_miss_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[16]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_2[tlb_miss_offset:tlb_miss_offset + `MM_THREADS - 1]), + .scout(sov_2[tlb_miss_offset:tlb_miss_offset + `MM_THREADS - 1]), + .din(tlb_miss_d), + .dout(tlb_miss_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) tlb_inelig_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[16]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_2[tlb_inelig_offset:tlb_inelig_offset + `MM_THREADS - 1]), + .scout(sov_2[tlb_inelig_offset:tlb_inelig_offset + `MM_THREADS - 1]), + .din(tlb_inelig_d), + .dout(tlb_inelig_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) lrat_miss_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[16]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_2[lrat_miss_offset:lrat_miss_offset + `MM_THREADS - 1]), + .scout(sov_2[lrat_miss_offset:lrat_miss_offset + `MM_THREADS - 1]), + .din(lrat_miss_d), + .dout(lrat_miss_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) pt_fault_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[16]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_2[pt_fault_offset:pt_fault_offset + `MM_THREADS - 1]), + .scout(sov_2[pt_fault_offset:pt_fault_offset + `MM_THREADS - 1]), + .din(pt_fault_d), + .dout(pt_fault_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) hv_priv_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[16]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_2[hv_priv_offset:hv_priv_offset + `MM_THREADS - 1]), + .scout(sov_2[hv_priv_offset:hv_priv_offset + `MM_THREADS - 1]), + .din(hv_priv_d), + .dout(hv_priv_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) tlb_tag5_except_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[11]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_2[tlb_tag5_except_offset:tlb_tag5_except_offset + `MM_THREADS - 1]), + .scout(sov_2[tlb_tag5_except_offset:tlb_tag5_except_offset + `MM_THREADS - 1]), + .din(tlb_tag5_except_d), + .dout(tlb_tag5_except_q) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) mm_xu_ord_par_mhit_err_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[11]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_2[mm_xu_ord_par_mhit_err_offset:mm_xu_ord_par_mhit_err_offset + 3 - 1]), + .scout(sov_2[mm_xu_ord_par_mhit_err_offset:mm_xu_ord_par_mhit_err_offset + 3 - 1]), + .din(mm_xu_ord_par_mhit_err_d), + .dout(mm_xu_ord_par_mhit_err_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lru_update_clear_enab_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[11]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_2[lru_update_clear_enab_offset]), + .scout(sov_2[lru_update_clear_enab_offset]), + .din(lru_update_clear_enab), + .dout(lru_update_clear_enab_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_tag5_parerr_zeroize_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[11]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_2[tlb_tag5_parerr_zeroize_offset]), + .scout(sov_2[tlb_tag5_parerr_zeroize_offset]), + .din(tlb_tag4_parerr_zeroize), + .dout(tlb_tag5_parerr_zeroize_q) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) tlb_tag5_itag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[11]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_2[tlb_tag5_itag_offset:tlb_tag5_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov_2[tlb_tag5_itag_offset:tlb_tag5_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(tlb_tag5_itag_d), + .dout(tlb_tag5_itag_q) + ); + + tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) tlb_tag5_emq_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[11]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_2[tlb_tag5_emq_offset:tlb_tag5_emq_offset + `EMQ_ENTRIES - 1]), + .scout(sov_2[tlb_tag5_emq_offset:tlb_tag5_emq_offset + `EMQ_ENTRIES - 1]), + .din(tlb_tag5_emq_d), + .dout(tlb_tag5_emq_q) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) tlb_tag5_perf_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[11]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_2[tlb_tag5_perf_offset:tlb_tag5_perf_offset + 2 - 1]), + .scout(sov_2[tlb_tag5_perf_offset:tlb_tag5_perf_offset + 2 - 1]), + .din(tlb_tag5_perf_d), + .dout(tlb_tag5_perf_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) tlb_dsi_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[16]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_2[tlb_dsi_offset:tlb_dsi_offset + `MM_THREADS - 1]), + .scout(sov_2[tlb_dsi_offset:tlb_dsi_offset + `MM_THREADS - 1]), + .din(tlb_dsi_d), + .dout(tlb_dsi_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) tlb_isi_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[16]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_2[tlb_isi_offset:tlb_isi_offset + `MM_THREADS - 1]), + .scout(sov_2[tlb_isi_offset:tlb_isi_offset + `MM_THREADS - 1]), + .din(tlb_isi_d), + .dout(tlb_isi_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) esr_pt_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[16]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_2[esr_pt_offset:esr_pt_offset + `MM_THREADS - 1]), + .scout(sov_2[esr_pt_offset:esr_pt_offset + `MM_THREADS - 1]), + .din(esr_pt_d), + .dout(esr_pt_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) esr_data_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[16]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_2[esr_data_offset:esr_data_offset + `MM_THREADS - 1]), + .scout(sov_2[esr_data_offset:esr_data_offset + `MM_THREADS - 1]), + .din(esr_data_d), + .dout(esr_data_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) esr_st_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[16]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_2[esr_st_offset:esr_st_offset + `MM_THREADS - 1]), + .scout(sov_2[esr_st_offset:esr_st_offset + `MM_THREADS - 1]), + .din(esr_st_d), + .dout(esr_st_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) esr_epid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[16]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_2[esr_epid_offset:esr_epid_offset + `MM_THREADS - 1]), + .scout(sov_2[esr_epid_offset:esr_epid_offset + `MM_THREADS - 1]), + .din(esr_epid_d), + .dout(esr_epid_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) cr0_eq_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[16]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_2[cr0_eq_offset:cr0_eq_offset + `MM_THREADS - 1]), + .scout(sov_2[cr0_eq_offset:cr0_eq_offset + `MM_THREADS - 1]), + .din(cr0_eq_d), + .dout(cr0_eq_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) cr0_eq_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[16]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_2[cr0_eq_valid_offset:cr0_eq_valid_offset + `MM_THREADS - 1]), + .scout(sov_2[cr0_eq_valid_offset:cr0_eq_valid_offset + `MM_THREADS - 1]), + .din(cr0_eq_valid_d), + .dout(cr0_eq_valid_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) tlb_multihit_err_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[16]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_2[tlb_multihit_err_offset:tlb_multihit_err_offset + `MM_THREADS - 1]), + .scout(sov_2[tlb_multihit_err_offset:tlb_multihit_err_offset + `MM_THREADS - 1]), + .din(tlb_multihit_err_d), + .dout(tlb_multihit_err_q) + ); + + tri_rlmreg_p #(.WIDTH((`TLB_WAYS+1)), .INIT(0), .NEEDS_SRESET(1)) tag4_parerr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[10]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_2[tag4_parerr_offset:tag4_parerr_offset + (`TLB_WAYS+1) - 1]), + .scout(sov_2[tag4_parerr_offset:tag4_parerr_offset + (`TLB_WAYS+1) - 1]), + .din(tag4_parerr_d), + .dout(tag4_parerr_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) tlb_par_err_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[16]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_2[tlb_par_err_offset:tlb_par_err_offset + `MM_THREADS - 1]), + .scout(sov_2[tlb_par_err_offset:tlb_par_err_offset + `MM_THREADS - 1]), + .din(ECO107332_tlb_par_err_d), + .dout(tlb_par_err_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) lru_par_err_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[16]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_2[lru_par_err_offset:lru_par_err_offset + `MM_THREADS - 1]), + .scout(sov_2[lru_par_err_offset:lru_par_err_offset + `MM_THREADS - 1]), + .din(ECO107332_lru_par_err_d), + .dout(lru_par_err_q) + ); + // Changed these to scannable to fix nsl > 1 depth into mmq_dbg nsl's + + tri_rlmreg_p #(.WIDTH(9), .INIT(0), .NEEDS_SRESET(1)) mmucr1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[mmucr1_offset:mmucr1_offset + 9 - 1]), + .scout(sov_0[mmucr1_offset:mmucr1_offset + 9 - 1]), + .din(mmucr1), + .dout(mmucr1_q) + ); + // Changed these to scannable to fix nsl > 1 depth into mmq_dbg nsl's + + tri_rlmreg_p #(.WIDTH(9), .INIT(0), .NEEDS_SRESET(1)) mmucr1_clone_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mmucr1_clone_offset:mmucr1_clone_offset + 9 - 1]), + .scout(sov_1[mmucr1_clone_offset:mmucr1_clone_offset + 9 - 1]), + .din(mmucr1), + .dout(mmucr1_clone_q) + ); + + tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) spare_a_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[14]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spare_a_offset:spare_a_offset + 16 - 1]), + .scout(sov_0[spare_a_offset:spare_a_offset + 16 - 1]), + .din(spare_a_q), + .dout(spare_a_q) + ); + + tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) spare_b_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[15]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spare_b_offset:spare_b_offset + 16 - 1]), + .scout(sov_1[spare_b_offset:spare_b_offset + 16 - 1]), + .din(spare_b_q), + .dout(spare_b_q) + ); + + tri_rlmreg_p #(.WIDTH(8), .INIT(MMQ_TLB_CMP_CSWITCH_0TO7), .NEEDS_SRESET(1)) cswitch_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_2[cswitch_offset:cswitch_offset + 8 - 1]), + .scout(sov_2[cswitch_offset:cswitch_offset + 8 - 1]), + .din(cswitch_q), + .dout(cswitch_q) + ); + // cswitch0: 1= allow tlbwe back inv for iprot=1 entries only + // cswitch1: 1= allow tlbwe back inv for hes=1 (lru selected) + // cswitch2: 1= allow tlbwe back inv that ignores erat extclass for iprot=1 entries only + // cswitch3: 1= allow tlbwe back inv for ind=1 entries + // cswitch4: 1= allow tlbwe back inv for ind=1 entries + // cswitch5: 1= allow tlbsx hit with parerr to update mas regs + // cswitch6: 1= allow tlbsx miss with parerr to update mas regs + // cswitch7: 1= allow tlbre with parerr to update mas regs + + tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) spare_c_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[16]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_2[spare_c_offset:spare_c_offset + 16 - 1]), + .scout(sov_2[spare_c_offset:spare_c_offset + 16 - 1]), + .din(spare_c_q), + .dout(spare_c_q) + ); + + // non-scannable timing latches + // Changed these to spares + + tri_regk #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(0)) spare_nsl_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(xu_mm_ccr2_notlb_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_nsl_force[0]), + .d_mode(lcb_d_mode_dc), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .thold_b(pc_func_slp_nsl_thold_0_b[0]), + .scin(tri_regk_unused_scan[0:7]), + .scout(tri_regk_unused_scan[0:7]), + .din(spare_nsl_q), + .dout(spare_nsl_q) + ); + + tri_regk #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(0)) spare_nsl_clone_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(xu_mm_ccr2_notlb_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_nsl_force[1]), + .d_mode(lcb_d_mode_dc), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .thold_b(pc_func_slp_nsl_thold_0_b[1]), + .scin(tri_regk_unused_scan[8:15]), + .scout(tri_regk_unused_scan[8:15]), + .din(spare_nsl_clone_q), + .dout(spare_nsl_clone_q) + ); + + tri_regk #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(0)) epcr_dmiuh_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(xu_mm_ccr2_notlb_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_nsl_force[0]), + .d_mode(lcb_d_mode_dc), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .thold_b(pc_func_slp_nsl_thold_0_b[0]), + .scin(tri_regk_unused_scan_epcr_dmiuh), + .scout(tri_regk_unused_scan_epcr_dmiuh), + .din(xu_mm_spr_epcr_dmiuh), + .dout(epcr_dmiuh_q) + ); + + tri_regk #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(0)) msr_gs_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(xu_mm_ccr2_notlb_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_nsl_force[0]), + .d_mode(lcb_d_mode_dc), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .thold_b(pc_func_slp_nsl_thold_0_b[0]), + .scin(tri_regk_unused_scan_msr_gs), + .scout(tri_regk_unused_scan_msr_gs), + .din(xu_mm_msr_gs), + .dout(msr_gs_q) + ); + + tri_regk #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(0)) msr_pr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(xu_mm_ccr2_notlb_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_nsl_force[0]), + .d_mode(lcb_d_mode_dc), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .thold_b(pc_func_slp_nsl_thold_0_b[0]), + .scin(tri_regk_unused_scan_msr_pr), + .scout(tri_regk_unused_scan_msr_pr), + .din(xu_mm_msr_pr), + .dout(msr_pr_q) + ); + + + + //------------------------------------------------ + // thold/sg latches + //------------------------------------------------ + + tri_plat #(.WIDTH(5)) perv_2to1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ccflush_dc), + .din( {pc_func_sl_thold_2, pc_func_slp_sl_thold_2, pc_func_slp_nsl_thold_2, pc_sg_2, pc_fce_2} ), + .q( {pc_func_sl_thold_1, pc_func_slp_sl_thold_1, pc_func_slp_nsl_thold_1, pc_sg_1, pc_fce_1} ) + ); + + tri_plat #(.WIDTH(5)) perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ccflush_dc), + .din( {pc_func_sl_thold_1, pc_func_slp_sl_thold_1, pc_func_slp_nsl_thold_1, pc_sg_1, pc_fce_1} ), + .q( {pc_func_sl_thold_0, pc_func_slp_sl_thold_0, pc_func_slp_nsl_thold_0, pc_sg_0, pc_fce_0} ) + ); + + tri_lcbor perv_lcbor_func_sl( + .clkoff_b(lcb_clkoff_dc_b), + .thold(pc_func_sl_thold_0), + .sg(pc_sg_0), + .act_dis(lcb_act_dis_dc), + .force_t(pc_func_sl_force), + .thold_b(pc_func_sl_thold_0_b) + ); + + tri_lcbor perv_lcbor_func_slp_sl( + .clkoff_b(lcb_clkoff_dc_b), + .thold(pc_func_slp_sl_thold_0), + .sg(pc_sg_0), + .act_dis(lcb_act_dis_dc), + .force_t(pc_func_slp_sl_force), + .thold_b(pc_func_slp_sl_thold_0_b) + ); + + tri_lcbor perv_nsl_lcbor( + .clkoff_b(lcb_clkoff_dc_b), + .thold(pc_func_slp_nsl_thold_0), + .sg(pc_fce_0), + .act_dis(tidn), + .force_t(pc_func_slp_nsl_force[0]), + .thold_b(pc_func_slp_nsl_thold_0_b[0]) + ); + + tri_lcbor perv_nsl_lcbor_clone( + .clkoff_b(lcb_clkoff_dc_b), + .thold(pc_func_slp_nsl_thold_0), + .sg(pc_fce_0), + .act_dis(tidn), + .force_t(pc_func_slp_nsl_force[1]), + .thold_b(pc_func_slp_nsl_thold_0_b[1]) + ); + + + //--------------------------------------------------------------------- + // Scan + //--------------------------------------------------------------------- + assign siv_0[0:scan_right_0] = {sov_0[1:scan_right_0], ac_func_scan_in[0]}; + assign ac_func_scan_out[0] = sov_0[0]; + assign siv_1[0:scan_right_1] = {sov_1[1:scan_right_1], ac_func_scan_in[1]}; + assign ac_func_scan_out[1] = sov_1[0]; + assign siv_2[0:scan_right_2] = {sov_2[1:scan_right_2], ac_func_scan_in[2]}; + assign ac_func_scan_out[2] = sov_2[0]; + + function Eq; + input a, b; + reg result; + begin + if (a == b) + begin + result = 1'b1; + end + else + begin + result = 1'b0; + end + Eq = result; + end + endfunction + +endmodule diff --git a/dev/verilog/work/mmq_tlb_ctl.v b/dev/verilog/work/mmq_tlb_ctl.v new file mode 100755 index 0000000..550ac75 --- /dev/null +++ b/dev/verilog/work/mmq_tlb_ctl.v @@ -0,0 +1,4776 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +//******************************************************************** +//* TITLE: Memory Management Unit TLB Central Control Logic +//* NAME: mmq_tlb_ctl.v +//********************************************************************* + + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" +`include "mmu_a2o.vh" +`define CTL_TTYPE_WIDTH 5 +`define CTL_STATE_WIDTH 4 + +module mmq_tlb_ctl( + inout vdd, + inout gnd, + (* pin_data ="PIN_FUNCTION=/G_CLK/" *) + input [0:`NCLK_WIDTH-1] nclk, + + input tc_ccflush_dc, + input tc_scan_dis_dc_b, + input tc_scan_diag_dc, + input tc_lbist_en_dc, + input lcb_d_mode_dc, + input lcb_clkoff_dc_b, + input lcb_act_dis_dc, + input [0:4] lcb_mpw1_dc_b, + input lcb_mpw2_dc_b, + input [0:4] lcb_delay_lclkr_dc, + + input pc_sg_2, + input pc_func_sl_thold_2, + input pc_func_slp_sl_thold_2, + input pc_func_slp_nsl_thold_2, + input pc_fce_2, + +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + input ac_func_scan_in, +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + output ac_func_scan_out, + + input [0:`MM_THREADS-1] xu_mm_rf1_val, + input xu_mm_rf1_is_tlbre, + input xu_mm_rf1_is_tlbwe, + input xu_mm_rf1_is_tlbsx, + input xu_mm_rf1_is_tlbsxr, + input xu_mm_rf1_is_tlbsrx, + input [64-`RS_DATA_WIDTH:51] xu_mm_ex2_epn, + input [0:`ITAG_SIZE_ENC-1] xu_mm_rf1_itag, + input [0:`MM_THREADS-1] xu_mm_msr_gs, + input [0:`MM_THREADS-1] xu_mm_msr_pr, + input [0:`MM_THREADS-1] xu_mm_msr_is, + input [0:`MM_THREADS-1] xu_mm_msr_ds, + input [0:`MM_THREADS-1] xu_mm_msr_cm, + input xu_mm_ccr2_notlb_b, + input [0:`MM_THREADS-1] xu_mm_epcr_dgtmi, + input xu_mm_xucr4_mmu_mchk, + output xu_mm_xucr4_mmu_mchk_q, + + input [0:`MM_THREADS-1] xu_rf1_flush, + input [0:`MM_THREADS-1] xu_ex1_flush, + input [0:`MM_THREADS-1] xu_ex2_flush, + input [0:`MM_THREADS-1] xu_ex3_flush, + input [0:`MM_THREADS-1] xu_ex4_flush, + input [0:`MM_THREADS-1] xu_ex5_flush, + + output [0:`MM_THREADS-1] tlb_ctl_ex3_valid, + output [0:`CTL_TTYPE_WIDTH-1] tlb_ctl_ex3_ttype, + output tlb_ctl_ex3_hv_state, + output [0:`MM_THREADS-1] tlb_ctl_tag2_flush, + output [0:`MM_THREADS-1] tlb_ctl_tag3_flush, + output [0:`MM_THREADS-1] tlb_ctl_tag4_flush, + + input [0:`MM_THREADS-1] mm_xu_eratmiss_done, + input [0:`MM_THREADS-1] mm_xu_tlb_miss, + input [0:`MM_THREADS-1] mm_xu_tlb_inelig, + output [0:`MM_THREADS-1] tlb_resv_match_vec, + output [0:`MM_THREADS-1] tlb_ctl_barrier_done, + output [0:`MM_THREADS-1] tlb_ctl_ex2_flush_req, + + output [0:`ITAG_SIZE_ENC-1] tlb_ctl_ex2_itag, + output [0:2] tlb_ctl_ord_type, + + output [0:`MM_THREADS-1] tlb_ctl_quiesce, + output [0:`MM_THREADS-1] tlb_ctl_ex2_illeg_instr, + output [0:`MM_THREADS-1] tlb_ctl_ex6_illeg_instr, + output [0:1] ex6_illeg_instr, // constant width, bad tlbre/we op indication to tlb_cmp + + input tlbwe_back_inv_pending, + input mmucr1_tlbi_msb, + input mmucr1_tlbwe_binv, + input [0:`MMUCR2_WIDTH-1] mmucr2, + input [64-`MMUCR3_WIDTH:63] mmucr3_0, + input [0:`PID_WIDTH-1] pid0, +`ifdef MM_THREADS2 + input [0:`PID_WIDTH-1] pid1, + input [64-`MMUCR3_WIDTH:63] mmucr3_1, +`endif + input [0:`LPID_WIDTH-1] lpidr, + input mmucfg_lrat, + input mmucfg_twc, + input tlb0cfg_pt, + input tlb0cfg_ind, + input tlb0cfg_gtwe, + input mmucsr0_tlb0fi, + input mas0_0_atsel, + input [0:2] mas0_0_esel, + input mas0_0_hes, + input [0:1] mas0_0_wq, + input mas1_0_v, + input mas1_0_iprot, + input [0:13] mas1_0_tid, + input mas1_0_ind, + input mas1_0_ts, + input [0:3] mas1_0_tsize, + input [0:51] mas2_0_epn, + input [0:4] mas2_0_wimge, + input [0:3] mas3_0_usxwr, + input mas5_0_sgs, + input [0:7] mas5_0_slpid, + input [0:13] mas6_0_spid, + input mas6_0_sind, + input mas6_0_sas, + input mas8_0_tgs, + input [0:7] mas8_0_tlpid, +`ifdef MM_THREADS2 + input mas0_1_atsel, + input [0:2] mas0_1_esel, + input mas0_1_hes, + input [0:1] mas0_1_wq, + input mas1_1_v, + input mas1_1_iprot, + input [0:13] mas1_1_tid, + input mas1_1_ind, + input mas1_1_ts, + input [0:3] mas1_1_tsize, + input [0:51] mas2_1_epn, + input [0:4] mas2_1_wimge, + input [0:3] mas3_1_usxwr, + input mas5_1_sgs, + input [0:7] mas5_1_slpid, + input [0:13] mas6_1_spid, + input mas6_1_sind, + input mas6_1_sas, + input mas8_1_tgs, + input [0:7] mas8_1_tlpid, +`endif + input tlb_seq_ierat_req, + input tlb_seq_derat_req, + output tlb_seq_ierat_done, + output tlb_seq_derat_done, + output tlb_seq_idle, + output ierat_req_taken, + output derat_req_taken, + input [0:`EPN_WIDTH-1] ierat_req_epn, + input [0:`PID_WIDTH-1] ierat_req_pid, + input [0:`CTL_STATE_WIDTH-1] ierat_req_state, + input [0:`THDID_WIDTH-1] ierat_req_thdid, + input [0:1] ierat_req_dup, + input ierat_req_nonspec, + input [0:`EPN_WIDTH-1] derat_req_epn, + input [0:`PID_WIDTH-1] derat_req_pid, + input [0:`LPID_WIDTH-1] derat_req_lpid, + input [0:`CTL_STATE_WIDTH-1] derat_req_state, + input [0:1] derat_req_ttype, + input [0:`THDID_WIDTH-1] derat_req_thdid, + input [0:1] derat_req_dup, + input [0:`ITAG_SIZE_ENC-1] derat_req_itag, + input [0:`EMQ_ENTRIES-1] derat_req_emq, + input derat_req_nonspec, + input ptereload_req_valid, + input [0:`TLB_TAG_WIDTH-1] ptereload_req_tag, + input [0:`PTE_WIDTH-1] ptereload_req_pte, + output ptereload_req_taken, + input tlb_snoop_coming, + input tlb_snoop_val, + input [0:34] tlb_snoop_attr, + input [52-`EPN_WIDTH:51] tlb_snoop_vpn, + output tlb_snoop_ack, + output [0:`TLB_ADDR_WIDTH-1] lru_rd_addr, + input [0:15] lru_tag4_dataout, + input [0:`TLB_ADDR_WIDTH-1] tlb_addr4, + input [0:2] tlb_tag4_esel, + input [0:1] tlb_tag4_wq, + input [0:1] tlb_tag4_is, + input tlb_tag4_gs, + input tlb_tag4_pr, + input tlb_tag4_hes, + input tlb_tag4_atsel, + input tlb_tag4_pt, + input tlb_tag4_cmp_hit, + input tlb_tag4_way_ind, + input tlb_tag4_ptereload, + input tlb_tag4_endflag, + input tlb_tag4_parerr, + input [0:`TLB_WAYS-1] tlb_tag4_parerr_write, + input tlb_tag5_parerr_zeroize, + input [0:`MM_THREADS-1] tlb_tag5_except, + input [0:1] tlb_cmp_erat_dup_wait, + output [52-`EPN_WIDTH:51] tlb_tag0_epn, + output [0:`THDID_WIDTH-1] tlb_tag0_thdid, + output [0:7] tlb_tag0_type, + output [0:`LPID_WIDTH-1] tlb_tag0_lpid, + output tlb_tag0_atsel, + output [0:3] tlb_tag0_size, + output tlb_tag0_addr_cap, + output tlb_tag0_nonspec, + output [0:`TLB_TAG_WIDTH-1] tlb_tag2, + output [0:`TLB_ADDR_WIDTH-1] tlb_addr2, + output tlb_ctl_perf_tlbwec_resv, + output tlb_ctl_perf_tlbwec_noresv, + input [0:3] lrat_tag4_hit_status, + + output [64-`REAL_ADDR_WIDTH:51] tlb_lper_lpn, + output [60:63] tlb_lper_lps, + output [0:`MM_THREADS-1] tlb_lper_we, + output [0:`PTE_WIDTH-1] ptereload_req_pte_lat, + output [64-`REAL_ADDR_WIDTH:51] pte_tag0_lpn, + output [0:`LPID_WIDTH-1] pte_tag0_lpid, + output [0:`TLB_WAYS-1] tlb_write, + output [0:`TLB_ADDR_WIDTH-1] tlb_addr, + output tlb_tag5_write, + output [9:33] tlb_delayed_act, + + output [0:5] tlb_ctl_dbg_seq_q, + output tlb_ctl_dbg_seq_idle, + output tlb_ctl_dbg_seq_any_done_sig, + output tlb_ctl_dbg_seq_abort, + output tlb_ctl_dbg_any_tlb_req_sig, + output tlb_ctl_dbg_any_req_taken_sig, + output [0:3] tlb_ctl_dbg_tag5_tlb_write_q, + output tlb_ctl_dbg_tag0_valid, + output [0:1] tlb_ctl_dbg_tag0_thdid, // encoded + output [0:2] tlb_ctl_dbg_tag0_type, // encoded + output [0:1] tlb_ctl_dbg_tag0_wq, + output tlb_ctl_dbg_tag0_gs, + output tlb_ctl_dbg_tag0_pr, + output tlb_ctl_dbg_tag0_atsel, + output [0:3] tlb_ctl_dbg_resv_valid, + output [0:3] tlb_ctl_dbg_set_resv, + output [0:3] tlb_ctl_dbg_resv_match_vec_q, + output tlb_ctl_dbg_any_tag_flush_sig, + output tlb_ctl_dbg_resv0_tag0_lpid_match, + output tlb_ctl_dbg_resv0_tag0_pid_match, + output tlb_ctl_dbg_resv0_tag0_as_snoop_match, + output tlb_ctl_dbg_resv0_tag0_gs_snoop_match, + output tlb_ctl_dbg_resv0_tag0_as_tlbwe_match, + output tlb_ctl_dbg_resv0_tag0_gs_tlbwe_match, + output tlb_ctl_dbg_resv0_tag0_ind_match, + output tlb_ctl_dbg_resv0_tag0_epn_loc_match, + output tlb_ctl_dbg_resv0_tag0_epn_glob_match, + output tlb_ctl_dbg_resv0_tag0_class_match, + output tlb_ctl_dbg_resv1_tag0_lpid_match, + output tlb_ctl_dbg_resv1_tag0_pid_match, + output tlb_ctl_dbg_resv1_tag0_as_snoop_match, + output tlb_ctl_dbg_resv1_tag0_gs_snoop_match, + output tlb_ctl_dbg_resv1_tag0_as_tlbwe_match, + output tlb_ctl_dbg_resv1_tag0_gs_tlbwe_match, + output tlb_ctl_dbg_resv1_tag0_ind_match, + output tlb_ctl_dbg_resv1_tag0_epn_loc_match, + output tlb_ctl_dbg_resv1_tag0_epn_glob_match, + output tlb_ctl_dbg_resv1_tag0_class_match, + output tlb_ctl_dbg_resv2_tag0_lpid_match, + output tlb_ctl_dbg_resv2_tag0_pid_match, + output tlb_ctl_dbg_resv2_tag0_as_snoop_match, + output tlb_ctl_dbg_resv2_tag0_gs_snoop_match, + output tlb_ctl_dbg_resv2_tag0_as_tlbwe_match, + output tlb_ctl_dbg_resv2_tag0_gs_tlbwe_match, + output tlb_ctl_dbg_resv2_tag0_ind_match, + output tlb_ctl_dbg_resv2_tag0_epn_loc_match, + output tlb_ctl_dbg_resv2_tag0_epn_glob_match, + output tlb_ctl_dbg_resv2_tag0_class_match, + output tlb_ctl_dbg_resv3_tag0_lpid_match, + output tlb_ctl_dbg_resv3_tag0_pid_match, + output tlb_ctl_dbg_resv3_tag0_as_snoop_match, + output tlb_ctl_dbg_resv3_tag0_gs_snoop_match, + output tlb_ctl_dbg_resv3_tag0_as_tlbwe_match, + output tlb_ctl_dbg_resv3_tag0_gs_tlbwe_match, + output tlb_ctl_dbg_resv3_tag0_ind_match, + output tlb_ctl_dbg_resv3_tag0_epn_loc_match, + output tlb_ctl_dbg_resv3_tag0_epn_glob_match, + output tlb_ctl_dbg_resv3_tag0_class_match, + output [0:3] tlb_ctl_dbg_clr_resv_q, + output [0:3] tlb_ctl_dbg_clr_resv_terms + +); + + + parameter MMU_Mode_Value = 1'b0; + parameter [0:1] TlbSel_Tlb = 2'b00; + parameter [0:1] TlbSel_IErat = 2'b10; + parameter [0:1] TlbSel_DErat = 2'b11; + parameter [0:2] ERAT_PgSize_1GB = 3'b110; + parameter [0:2] ERAT_PgSize_16MB = 3'b111; + parameter [0:2] ERAT_PgSize_1MB = 3'b101; + parameter [0:2] ERAT_PgSize_64KB = 3'b011; + parameter [0:2] ERAT_PgSize_4KB = 3'b001; + parameter [0:3] TLB_PgSize_1GB = 4'b1010; + parameter [0:3] TLB_PgSize_16MB = 4'b0111; + parameter [0:3] TLB_PgSize_1MB = 4'b0101; + parameter [0:3] TLB_PgSize_64KB = 4'b0011; + parameter [0:3] TLB_PgSize_4KB = 4'b0001; + // reserved for indirect entries + parameter [0:2] ERAT_PgSize_256MB = 3'b100; + parameter [0:3] TLB_PgSize_256MB = 4'b1001; + // LRAT page sizes + parameter [0:3] LRAT_PgSize_1TB = 4'b1111; + parameter [0:3] LRAT_PgSize_256GB = 4'b1110; + parameter [0:3] LRAT_PgSize_16GB = 4'b1100; + parameter [0:3] LRAT_PgSize_4GB = 4'b1011; + parameter [0:3] LRAT_PgSize_1GB = 4'b1010; + parameter [0:3] LRAT_PgSize_256MB = 4'b1001; + parameter [0:3] LRAT_PgSize_16MB = 4'b0111; + parameter [0:3] LRAT_PgSize_1MB = 4'b0101; + parameter [0:5] TlbSeq_Idle = 6'b000000; + parameter [0:5] TlbSeq_Stg1 = 6'b000001; + parameter [0:5] TlbSeq_Stg2 = 6'b000011; + parameter [0:5] TlbSeq_Stg3 = 6'b000010; + parameter [0:5] TlbSeq_Stg4 = 6'b000110; + parameter [0:5] TlbSeq_Stg5 = 6'b000100; + parameter [0:5] TlbSeq_Stg6 = 6'b000101; + parameter [0:5] TlbSeq_Stg7 = 6'b000111; + parameter [0:5] TlbSeq_Stg8 = 6'b001000; + parameter [0:5] TlbSeq_Stg9 = 6'b001001; + parameter [0:5] TlbSeq_Stg10 = 6'b001011; + parameter [0:5] TlbSeq_Stg11 = 6'b001010; + parameter [0:5] TlbSeq_Stg12 = 6'b001110; + parameter [0:5] TlbSeq_Stg13 = 6'b001100; + parameter [0:5] TlbSeq_Stg14 = 6'b001101; + parameter [0:5] TlbSeq_Stg15 = 6'b001111; + parameter [0:5] TlbSeq_Stg16 = 6'b010000; + parameter [0:5] TlbSeq_Stg17 = 6'b010001; + parameter [0:5] TlbSeq_Stg18 = 6'b010011; + parameter [0:5] TlbSeq_Stg19 = 6'b010010; + parameter [0:5] TlbSeq_Stg20 = 6'b010110; + parameter [0:5] TlbSeq_Stg21 = 6'b010100; + parameter [0:5] TlbSeq_Stg22 = 6'b010101; + parameter [0:5] TlbSeq_Stg23 = 6'b010111; + parameter [0:5] TlbSeq_Stg24 = 6'b011000; + parameter [0:5] TlbSeq_Stg25 = 6'b011001; + parameter [0:5] TlbSeq_Stg26 = 6'b011011; + parameter [0:5] TlbSeq_Stg27 = 6'b011010; + parameter [0:5] TlbSeq_Stg28 = 6'b011110; + parameter [0:5] TlbSeq_Stg29 = 6'b011100; + parameter [0:5] TlbSeq_Stg30 = 6'b011101; + parameter [0:5] TlbSeq_Stg31 = 6'b011111; + parameter [0:5] TlbSeq_Stg32 = 6'b100000; + + + parameter xu_ex1_flush_offset = 0; + parameter ex1_valid_offset = xu_ex1_flush_offset + `MM_THREADS; + parameter ex1_ttype_offset = ex1_valid_offset + `MM_THREADS; + parameter ex1_state_offset = ex1_ttype_offset + `CTL_TTYPE_WIDTH; + parameter ex1_itag_offset = ex1_state_offset + `CTL_STATE_WIDTH + 1; + parameter ex1_pid_offset = ex1_itag_offset + `ITAG_SIZE_ENC; + parameter ex2_valid_offset = ex1_pid_offset + `PID_WIDTH; + parameter ex2_flush_offset = ex2_valid_offset + `MM_THREADS; + parameter ex2_flush_req_offset = ex2_flush_offset + `MM_THREADS; + parameter ex2_ttype_offset = ex2_flush_req_offset + `MM_THREADS; + parameter ex2_state_offset = ex2_ttype_offset + `CTL_TTYPE_WIDTH; + parameter ex2_itag_offset = ex2_state_offset + `CTL_STATE_WIDTH + 1; + parameter ex2_pid_offset = ex2_itag_offset + `ITAG_SIZE_ENC; + parameter ex3_valid_offset = ex2_pid_offset + `PID_WIDTH; + parameter ex3_flush_offset = ex3_valid_offset + `MM_THREADS; + parameter ex3_ttype_offset = ex3_flush_offset + `MM_THREADS; + parameter ex3_state_offset = ex3_ttype_offset + `CTL_TTYPE_WIDTH; + parameter ex3_pid_offset = ex3_state_offset + `CTL_STATE_WIDTH + 1; + parameter ex4_valid_offset = ex3_pid_offset + `PID_WIDTH; + parameter ex4_flush_offset = ex4_valid_offset + `MM_THREADS; + parameter ex4_ttype_offset = ex4_flush_offset + `MM_THREADS; + parameter ex4_state_offset = ex4_ttype_offset + `CTL_TTYPE_WIDTH; + parameter ex4_pid_offset = ex4_state_offset + `CTL_STATE_WIDTH + 1; + parameter ex5_valid_offset = ex4_pid_offset + `PID_WIDTH; + parameter ex5_flush_offset = ex5_valid_offset + `MM_THREADS; + parameter ex5_ttype_offset = ex5_flush_offset + `MM_THREADS; + parameter ex5_state_offset = ex5_ttype_offset + `CTL_TTYPE_WIDTH; + parameter ex5_pid_offset = ex5_state_offset + `CTL_STATE_WIDTH + 1; + parameter ex6_valid_offset = ex5_pid_offset + `PID_WIDTH; + parameter ex6_flush_offset = ex6_valid_offset + `MM_THREADS; + parameter ex6_ttype_offset = ex6_flush_offset + `MM_THREADS; + parameter ex6_state_offset = ex6_ttype_offset + `CTL_TTYPE_WIDTH; + parameter ex6_pid_offset = ex6_state_offset + `CTL_STATE_WIDTH + 1; + parameter tlb_addr_offset = ex6_pid_offset + `PID_WIDTH; + parameter tlb_addr2_offset = tlb_addr_offset + `TLB_ADDR_WIDTH; + parameter tlb_write_offset = tlb_addr2_offset + `TLB_ADDR_WIDTH; + parameter tlb_tag0_offset = tlb_write_offset + `TLB_WAYS; + parameter tlb_tag1_offset = tlb_tag0_offset + `TLB_TAG_WIDTH; + parameter tlb_tag2_offset = tlb_tag1_offset + `TLB_TAG_WIDTH; + parameter tlb_seq_offset = tlb_tag2_offset + `TLB_TAG_WIDTH; + parameter derat_taken_offset = tlb_seq_offset + `TLB_SEQ_WIDTH; + parameter xucr4_mmu_mchk_offset = derat_taken_offset + 1; + parameter ex6_illeg_instr_offset = xucr4_mmu_mchk_offset + 1; + + parameter snoop_val_offset = ex6_illeg_instr_offset + 2; // this is constant for tlbre/we illegal + parameter snoop_attr_offset = snoop_val_offset + 2; + parameter snoop_vpn_offset = snoop_attr_offset + 35; + parameter tlb_clr_resv_offset = snoop_vpn_offset + `EPN_WIDTH; + parameter tlb_resv_match_vec_offset = tlb_clr_resv_offset + `MM_THREADS; + parameter tlb_resv0_valid_offset = tlb_resv_match_vec_offset + `MM_THREADS; + parameter tlb_resv0_epn_offset = tlb_resv0_valid_offset + 1; + parameter tlb_resv0_pid_offset = tlb_resv0_epn_offset + `EPN_WIDTH; + parameter tlb_resv0_lpid_offset = tlb_resv0_pid_offset + `PID_WIDTH; + parameter tlb_resv0_as_offset = tlb_resv0_lpid_offset + `LPID_WIDTH; + parameter tlb_resv0_gs_offset = tlb_resv0_as_offset + 1; + parameter tlb_resv0_ind_offset = tlb_resv0_gs_offset + 1; + parameter tlb_resv0_class_offset = tlb_resv0_ind_offset + 1; +`ifdef MM_THREADS2 + parameter tlb_resv1_valid_offset = tlb_resv0_class_offset + `CLASS_WIDTH; + parameter tlb_resv1_epn_offset = tlb_resv1_valid_offset + 1; + parameter tlb_resv1_pid_offset = tlb_resv1_epn_offset + `EPN_WIDTH; + parameter tlb_resv1_lpid_offset = tlb_resv1_pid_offset + `PID_WIDTH; + parameter tlb_resv1_as_offset = tlb_resv1_lpid_offset + `LPID_WIDTH; + parameter tlb_resv1_gs_offset = tlb_resv1_as_offset + 1; + parameter tlb_resv1_ind_offset = tlb_resv1_gs_offset + 1; + parameter tlb_resv1_class_offset = tlb_resv1_ind_offset + 1; + parameter ptereload_req_pte_offset = tlb_resv1_class_offset + `CLASS_WIDTH; +`else + parameter ptereload_req_pte_offset = tlb_resv0_class_offset + `CLASS_WIDTH; +`endif + parameter tlb_delayed_act_offset = ptereload_req_pte_offset + `PTE_WIDTH; + parameter tlb_ctl_spare_offset = tlb_delayed_act_offset + 34; + parameter scan_right = tlb_ctl_spare_offset + 32 - 1; + +`ifdef MM_THREADS2 + parameter BUGSP_MM_THREADS = 2; +`else + parameter BUGSP_MM_THREADS = 1; +`endif + + // Latch signals + wire [0:`MM_THREADS-1] xu_ex1_flush_d; + wire [0:`MM_THREADS-1] xu_ex1_flush_q; + wire [0:`MM_THREADS-1] ex1_valid_d; + wire [0:`MM_THREADS-1] ex1_valid_q; + wire [0:`CTL_TTYPE_WIDTH-1] ex1_ttype_d, ex1_ttype_q; + wire [0:`CTL_STATE_WIDTH] ex1_state_d; + wire [0:`CTL_STATE_WIDTH] ex1_state_q; + wire [0:`PID_WIDTH-1] ex1_pid_d; + wire [0:`PID_WIDTH-1] ex1_pid_q; + wire [0:`MM_THREADS-1] ex2_valid_d; + wire [0:`MM_THREADS-1] ex2_valid_q; + wire [0:`MM_THREADS-1] ex2_flush_d; + wire [0:`MM_THREADS-1] ex2_flush_q; + wire [0:`MM_THREADS-1] ex2_flush_req_d; + wire [0:`MM_THREADS-1] ex2_flush_req_q; + wire [0:`CTL_TTYPE_WIDTH-1] ex2_ttype_d; + wire [0:`CTL_TTYPE_WIDTH-1] ex2_ttype_q; + wire [0:`CTL_STATE_WIDTH] ex2_state_d; + wire [0:`CTL_STATE_WIDTH] ex2_state_q; + wire [0:`PID_WIDTH-1] ex2_pid_d; + wire [0:`PID_WIDTH-1] ex2_pid_q; + wire [0:`ITAG_SIZE_ENC-1] ex1_itag_d; + wire [0:`ITAG_SIZE_ENC-1] ex1_itag_q; + wire [0:`ITAG_SIZE_ENC-1] ex2_itag_d; + wire [0:`ITAG_SIZE_ENC-1] ex2_itag_q; + wire [0:`MM_THREADS-1] ex3_valid_d; + wire [0:`MM_THREADS-1] ex3_valid_q; + wire [0:`MM_THREADS-1] ex3_flush_d; + wire [0:`MM_THREADS-1] ex3_flush_q; + wire [0:`CTL_TTYPE_WIDTH-1] ex3_ttype_d; + wire [0:`CTL_TTYPE_WIDTH-1] ex3_ttype_q; + wire [0:`CTL_STATE_WIDTH] ex3_state_d; + wire [0:`CTL_STATE_WIDTH] ex3_state_q; + wire [0:`PID_WIDTH-1] ex3_pid_d; + wire [0:`PID_WIDTH-1] ex3_pid_q; + wire [0:`MM_THREADS-1] ex4_valid_d; + wire [0:`MM_THREADS-1] ex4_valid_q; + wire [0:`MM_THREADS-1] ex4_flush_d; + wire [0:`MM_THREADS-1] ex4_flush_q; + wire [0:`CTL_TTYPE_WIDTH-1] ex4_ttype_d; + wire [0:`CTL_TTYPE_WIDTH-1] ex4_ttype_q; + wire [0:`CTL_STATE_WIDTH] ex4_state_d; + wire [0:`CTL_STATE_WIDTH] ex4_state_q; + wire [0:`PID_WIDTH-1] ex4_pid_d; + wire [0:`PID_WIDTH-1] ex4_pid_q; + wire [0:`MM_THREADS-1] ex5_valid_d; + wire [0:`MM_THREADS-1] ex5_valid_q; + wire [0:`MM_THREADS-1] ex5_flush_d; + wire [0:`MM_THREADS-1] ex5_flush_q; + wire [0:`CTL_TTYPE_WIDTH-1] ex5_ttype_d; + wire [0:`CTL_TTYPE_WIDTH-1] ex5_ttype_q; + wire [0:`CTL_STATE_WIDTH] ex5_state_d; + wire [0:`CTL_STATE_WIDTH] ex5_state_q; + wire [0:`PID_WIDTH-1] ex5_pid_d; + wire [0:`PID_WIDTH-1] ex5_pid_q; + wire [0:`MM_THREADS-1] ex6_valid_d; + wire [0:`MM_THREADS-1] ex6_valid_q; + wire [0:`MM_THREADS-1] ex6_flush_d; + wire [0:`MM_THREADS-1] ex6_flush_q; + wire [0:`CTL_TTYPE_WIDTH-1] ex6_ttype_d; + wire [0:`CTL_TTYPE_WIDTH-1] ex6_ttype_q; + wire [0:`CTL_STATE_WIDTH] ex6_state_d; + wire [0:`CTL_STATE_WIDTH] ex6_state_q; + wire [0:`PID_WIDTH-1] ex6_pid_d; + wire [0:`PID_WIDTH-1] ex6_pid_q; + wire [0:`TLB_TAG_WIDTH-1] tlb_tag0_d; + wire [0:`TLB_TAG_WIDTH-1] tlb_tag0_q; + wire [0:`TLB_TAG_WIDTH-1] tlb_tag1_d; + wire [0:`TLB_TAG_WIDTH-1] tlb_tag1_q; + wire [0:`TLB_TAG_WIDTH-1] tlb_tag2_d; + wire [0:`TLB_TAG_WIDTH-1] tlb_tag2_q; + wire [0:`TLB_ADDR_WIDTH-1] tlb_addr_d; + wire [0:`TLB_ADDR_WIDTH-1] tlb_addr_q; + wire [0:`TLB_ADDR_WIDTH-1] tlb_addr2_d; + wire [0:`TLB_ADDR_WIDTH-1] tlb_addr2_q; + wire [0:`TLB_WAYS-1] tlb_write_d; + wire [0:`TLB_WAYS-1] tlb_write_q; + wire [0:5] tlb_seq_d; + wire [0:5] tlb_seq_q; + wire derat_taken_d; + wire derat_taken_q; + wire [0:1] ex6_illeg_instr_d; + wire [0:1] ex6_illeg_instr_q; + wire [0:1] snoop_val_d; + wire [0:1] snoop_val_q; + wire [0:34] snoop_attr_d; + wire [0:34] snoop_attr_q; + wire [52-`EPN_WIDTH:51] snoop_vpn_d; + wire [52-`EPN_WIDTH:51] snoop_vpn_q; + wire tlb_resv0_valid_d; + wire tlb_resv0_valid_q; + wire [52-`EPN_WIDTH:51] tlb_resv0_epn_d; + wire [52-`EPN_WIDTH:51] tlb_resv0_epn_q; + wire [0:`PID_WIDTH-1] tlb_resv0_pid_d; + wire [0:`PID_WIDTH-1] tlb_resv0_pid_q; + wire [0:`LPID_WIDTH-1] tlb_resv0_lpid_d; + wire [0:`LPID_WIDTH-1] tlb_resv0_lpid_q; + wire tlb_resv0_as_d; + wire tlb_resv0_as_q; + wire tlb_resv0_gs_d; + wire tlb_resv0_gs_q; + wire tlb_resv0_ind_d; + wire tlb_resv0_ind_q; + wire [0:`CLASS_WIDTH-1] tlb_resv0_class_d; + wire [0:`CLASS_WIDTH-1] tlb_resv0_class_q; +`ifdef MM_THREADS2 + wire tlb_resv1_valid_d; + wire tlb_resv1_valid_q; + wire [52-`EPN_WIDTH:51] tlb_resv1_epn_d; + wire [52-`EPN_WIDTH:51] tlb_resv1_epn_q; + wire [0:`PID_WIDTH-1] tlb_resv1_pid_d; + wire [0:`PID_WIDTH-1] tlb_resv1_pid_q; + wire [0:`LPID_WIDTH-1] tlb_resv1_lpid_d; + wire [0:`LPID_WIDTH-1] tlb_resv1_lpid_q; + wire tlb_resv1_as_d; + wire tlb_resv1_as_q; + wire tlb_resv1_gs_d; + wire tlb_resv1_gs_q; + wire tlb_resv1_ind_d; + wire tlb_resv1_ind_q; + wire [0:`CLASS_WIDTH-1] tlb_resv1_class_d; + wire [0:`CLASS_WIDTH-1] tlb_resv1_class_q; +`endif + wire [0:`PTE_WIDTH-1] ptereload_req_pte_d; + wire [0:`PTE_WIDTH-1] ptereload_req_pte_q; + wire [0:`MM_THREADS-1] tlb_clr_resv_d; + wire [0:`MM_THREADS-1] tlb_clr_resv_q; + wire [0:`MM_THREADS-1] tlb_resv_match_vec_d; + wire [0:`MM_THREADS-1] tlb_resv_match_vec_q; + wire [0:33] tlb_delayed_act_d; + wire [0:33] tlb_delayed_act_q; + wire [0:31] tlb_ctl_spare_q; + + // logic signals + reg [0:5] tlb_seq_next; + wire tlb_resv0_tag0_lpid_match; + wire tlb_resv0_tag0_pid_match; + wire tlb_resv0_tag0_as_snoop_match; + wire tlb_resv0_tag0_gs_snoop_match; + wire tlb_resv0_tag0_as_tlbwe_match; + wire tlb_resv0_tag0_gs_tlbwe_match; + wire tlb_resv0_tag0_ind_match; + wire tlb_resv0_tag0_epn_loc_match; + wire tlb_resv0_tag0_epn_glob_match; + wire tlb_resv0_tag0_class_match; + wire tlb_resv0_tag1_lpid_match; + wire tlb_resv0_tag1_pid_match; + wire tlb_resv0_tag1_as_snoop_match; + wire tlb_resv0_tag1_gs_snoop_match; + wire tlb_resv0_tag1_as_tlbwe_match; + wire tlb_resv0_tag1_gs_tlbwe_match; + wire tlb_resv0_tag1_ind_match; + wire tlb_resv0_tag1_epn_loc_match; + wire tlb_resv0_tag1_epn_glob_match; + wire tlb_resv0_tag1_class_match; +`ifdef MM_THREADS2 + wire tlb_resv1_tag0_lpid_match; + wire tlb_resv1_tag0_pid_match; + wire tlb_resv1_tag0_as_snoop_match; + wire tlb_resv1_tag0_gs_snoop_match; + wire tlb_resv1_tag0_as_tlbwe_match; + wire tlb_resv1_tag0_gs_tlbwe_match; + wire tlb_resv1_tag0_ind_match; + wire tlb_resv1_tag0_epn_loc_match; + wire tlb_resv1_tag0_epn_glob_match; + wire tlb_resv1_tag0_class_match; + wire tlb_resv1_tag1_lpid_match; + wire tlb_resv1_tag1_pid_match; + wire tlb_resv1_tag1_as_snoop_match; + wire tlb_resv1_tag1_gs_snoop_match; + wire tlb_resv1_tag1_as_tlbwe_match; + wire tlb_resv1_tag1_gs_tlbwe_match; + wire tlb_resv1_tag1_ind_match; + wire tlb_resv1_tag1_epn_loc_match; + wire tlb_resv1_tag1_epn_glob_match; + wire tlb_resv1_tag1_class_match; +`endif + wire [0:`MM_THREADS-1] tlb_resv_valid_vec; + + reg tlb_seq_set_resv; + reg tlb_seq_snoop_resv; + reg tlb_seq_snoop_inprogress; + wire [0:`MM_THREADS-1] tlb_seq_snoop_resv_q; + reg tlb_seq_lru_rd_act; + reg tlb_seq_lru_wr_act; + + wire [0:`TLB_ADDR_WIDTH-1] tlb_hashed_addr1; + wire [0:`TLB_ADDR_WIDTH-1] tlb_hashed_addr2; + wire [0:`TLB_ADDR_WIDTH-1] tlb_hashed_addr3; + wire [0:`TLB_ADDR_WIDTH-1] tlb_hashed_addr4; + wire [0:`TLB_ADDR_WIDTH-1] tlb_hashed_addr5; + wire [0:`TLB_ADDR_WIDTH-1] tlb_hashed_tid0_addr1; + wire [0:`TLB_ADDR_WIDTH-1] tlb_hashed_tid0_addr2; + wire [0:`TLB_ADDR_WIDTH-1] tlb_hashed_tid0_addr3; + wire [0:`TLB_ADDR_WIDTH-1] tlb_hashed_tid0_addr4; + wire [0:`TLB_ADDR_WIDTH-1] tlb_hashed_tid0_addr5; + wire [0:`TLB_ADDR_WIDTH-1] tlb_tag0_hashed_addr; + wire [0:`TLB_ADDR_WIDTH-1] tlb_tag0_hashed_tid0_addr; + wire tlb_tag0_tid_notzero; + wire [0:`TLB_ADDR_WIDTH-1] size_4K_hashed_addr; + wire [0:`TLB_ADDR_WIDTH-1] size_64K_hashed_addr; + wire [0:`TLB_ADDR_WIDTH-1] size_1M_hashed_addr; + wire [0:`TLB_ADDR_WIDTH-1] size_16M_hashed_addr; + wire [0:`TLB_ADDR_WIDTH-1] size_1G_hashed_addr; + wire [0:`TLB_ADDR_WIDTH-1] size_4K_hashed_tid0_addr; + wire [0:`TLB_ADDR_WIDTH-1] size_64K_hashed_tid0_addr; + wire [0:`TLB_ADDR_WIDTH-1] size_1M_hashed_tid0_addr; + wire [0:`TLB_ADDR_WIDTH-1] size_16M_hashed_tid0_addr; + wire [0:`TLB_ADDR_WIDTH-1] size_1G_hashed_tid0_addr; + // reserved for HTW + wire [0:`TLB_ADDR_WIDTH-1] size_256M_hashed_addr; + wire [0:`TLB_ADDR_WIDTH-1] size_256M_hashed_tid0_addr; + + reg [0:3] tlb_seq_pgsize; + reg [0:`TLB_ADDR_WIDTH-1] tlb_seq_addr; + reg [0:2] tlb_seq_esel; + reg [0:1] tlb_seq_is; + wire [0:`TLB_ADDR_WIDTH-1] tlb_addr_p1; + wire tlb_addr_maxcntm1; + reg tlb_seq_addr_incr; + reg tlb_seq_addr_clr; + reg tlb_seq_tag0_addr_cap; + reg tlb_seq_addr_update; + reg tlb_seq_lrat_enable; + wire tlb_seq_idle_sig; + reg tlb_seq_ind; + reg tlb_seq_ierat_done_sig; + reg tlb_seq_derat_done_sig; + reg tlb_seq_snoop_done_sig; + reg tlb_seq_search_done_sig; + reg tlb_seq_searchresv_done_sig; + reg tlb_seq_read_done_sig; + reg tlb_seq_write_done_sig; + reg tlb_seq_ptereload_done_sig; + wire tlb_seq_any_done_sig; + reg tlb_seq_endflag; + + wire tlb_search_req; + wire tlb_searchresv_req; + wire tlb_read_req; + wire tlb_write_req; + + (* NO_MODIFICATION="true" *) + wire tlb_set_resv0; +`ifdef MM_THREADS2 + (* NO_MODIFICATION="true" *) + wire tlb_set_resv1; +`endif + wire any_tlb_req_sig; + wire any_req_taken_sig; + reg ierat_req_taken_sig; + reg derat_req_taken_sig; + reg snoop_req_taken_sig; + reg search_req_taken_sig; + reg searchresv_req_taken_sig; + reg read_req_taken_sig; + reg write_req_taken_sig; + reg ptereload_req_taken_sig; + wire ex3_valid_32b; + wire ex1_mas0_atsel; + wire [0:2] ex1_mas0_esel; + wire ex1_mas0_hes; + wire [0:1] ex1_mas0_wq; + wire ex1_mas1_v; + wire ex1_mas1_iprot; + wire ex1_mas1_ind; + wire [0:`PID_WIDTH-1] ex1_mas1_tid; + wire ex1_mas1_ts; + wire [0:3] ex1_mas1_tsize; + wire [52-`EPN_WIDTH:51] ex1_mas2_epn; + wire ex1_mas8_tgs; + wire [0:`LPID_WIDTH-1] ex1_mas8_tlpid; + + wire [0:`CLASS_WIDTH-1] ex1_mmucr3_class; + wire ex2_mas0_atsel; + wire [0:2] ex2_mas0_esel; + wire ex2_mas0_hes; + wire [0:1] ex2_mas0_wq; + wire ex2_mas1_ind; + wire [0:`PID_WIDTH-1] ex2_mas1_tid; + wire [0:`LPID_WIDTH-1] ex2_mas5_slpid; + wire [0:`CTL_STATE_WIDTH-1] ex2_mas5_1_state; + wire [0:`CTL_STATE_WIDTH-1] ex2_mas5_6_state; + wire ex2_mas6_sind; + wire [0:`PID_WIDTH-1] ex2_mas6_spid; + wire ex2_hv_state; + wire ex6_hv_state; + wire ex6_priv_state; + wire ex6_dgtmi_state; + + wire [0:`MM_THREADS-1] tlb_ctl_tag1_flush_sig; + wire [0:`MM_THREADS-1] tlb_ctl_tag2_flush_sig; + wire [0:`MM_THREADS-1] tlb_ctl_tag3_flush_sig; + wire [0:`MM_THREADS-1] tlb_ctl_tag4_flush_sig; + wire tlb_ctl_any_tag_flush_sig; + wire tlb_seq_abort; + wire tlb_tag4_hit_or_parerr; + wire [0:`MM_THREADS-1] tlb_ctl_quiesce_b; + wire [0:`MM_THREADS-1] ex2_flush_req_local; + wire tlbwe_back_inv_holdoff; + wire pgsize1_valid; + wire pgsize2_valid; + wire pgsize3_valid; + wire pgsize4_valid; + wire pgsize5_valid; + wire pgsize1_tid0_valid; + wire pgsize2_tid0_valid; + wire pgsize3_tid0_valid; + wire pgsize4_tid0_valid; + wire pgsize5_tid0_valid; + wire [0:2] pgsize_qty; + wire [0:2] pgsize_tid0_qty; + wire tlb_tag1_pgsize_eq_16mb; + wire tlb_tag1_pgsize_gte_1mb; + wire tlb_tag1_pgsize_gte_64kb; + // mas settings errors + wire [0:`MM_THREADS-1] mas1_tsize_direct; + wire [0:`MM_THREADS-1] mas1_tsize_indirect; + wire [0:`MM_THREADS-1] mas1_tsize_lrat; + wire [0:`MM_THREADS-1] mas3_spsize_indirect; + wire [0:`MM_THREADS-1] ex2_tlbre_mas1_tsize_not_supp; + wire [0:`MM_THREADS-1] ex5_tlbre_mas1_tsize_not_supp; + wire [0:`MM_THREADS-1] ex5_tlbwe_mas1_tsize_not_supp; + wire [0:`MM_THREADS-1] ex6_tlbwe_mas1_tsize_not_supp; + wire [0:`MM_THREADS-1] ex5_tlbwe_mas0_lrat_bad_selects; + wire [0:`MM_THREADS-1] ex6_tlbwe_mas0_lrat_bad_selects; + wire [0:`MM_THREADS-1] ex5_tlbwe_mas2_ind_bad_wimge; + wire [0:`MM_THREADS-1] ex6_tlbwe_mas2_ind_bad_wimge; + wire [0:`MM_THREADS-1] ex5_tlbwe_mas3_ind_bad_spsize; + wire [0:`MM_THREADS-1] ex6_tlbwe_mas3_ind_bad_spsize; + // power clock gating signals + wire tlb_early_act; + wire tlb_tag0_act; + wire tlb_snoop_act; + + (* analysis_not_referenced="true" *) + wire [0:36] unused_dc; + (* analysis_not_referenced="true" *) + wire [`MM_THREADS:`THDID_WIDTH-1] unused_dc_thdid; + + wire [0:(`MM_THREADS*11)-1] tri_regk_unused_scan; + + + // Pervasive + wire pc_sg_1; + wire pc_sg_0; + wire pc_fce_1; + wire pc_fce_0; + wire pc_func_sl_thold_1; + wire pc_func_sl_thold_0; + wire pc_func_sl_thold_0_b; + wire pc_func_slp_sl_thold_1; + wire pc_func_slp_sl_thold_0; + wire pc_func_slp_sl_thold_0_b; + wire pc_func_sl_force; + wire pc_func_slp_sl_force; + wire pc_func_slp_nsl_thold_1; + wire pc_func_slp_nsl_thold_0; + wire pc_func_slp_nsl_thold_0_b; + wire pc_func_slp_nsl_force; + + wire [0:scan_right] siv; + wire [0:scan_right] sov; + + wire tidn; + wire tiup; + + + //begin + //!! Bugspray Include: mmq_tlb_ctl; + //--------------------------------------------------------------------- + // Logic + //--------------------------------------------------------------------- + //--------------------------------------------------------------------- + // Common stuff for erat-only and tlb + //--------------------------------------------------------------------- + assign tidn = 1'b0; + assign tiup = 1'b1; + + // snoop from bus being serviced + // not quiesced + assign tlb_ctl_quiesce_b[0:`MM_THREADS-1] = ( {`MM_THREADS{(~(tlb_seq_idle_sig) & ~(tlb_seq_snoop_inprogress))}} & tlb_tag0_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS -1] ); + assign tlb_ctl_quiesce = (~tlb_ctl_quiesce_b); + + assign xu_ex1_flush_d = xu_rf1_flush; + assign ex1_valid_d = xu_mm_rf1_val & (~(xu_rf1_flush)); + assign ex1_ttype_d = {xu_mm_rf1_is_tlbre, xu_mm_rf1_is_tlbwe, xu_mm_rf1_is_tlbsx, xu_mm_rf1_is_tlbsxr, xu_mm_rf1_is_tlbsrx}; + assign ex1_state_d[0] = |(xu_mm_msr_pr & xu_mm_rf1_val); + assign ex1_state_d[1] = |(xu_mm_msr_gs & xu_mm_rf1_val); + assign ex1_state_d[2] = |(xu_mm_msr_ds & xu_mm_rf1_val); + assign ex1_state_d[3] = |(xu_mm_msr_cm & xu_mm_rf1_val); + assign ex1_state_d[4] = |(xu_mm_msr_is & xu_mm_rf1_val); + assign ex1_itag_d = xu_mm_rf1_itag; +`ifdef MM_THREADS2 + assign ex1_pid_d = (pid0 & {`PID_WIDTH{xu_mm_rf1_val[0]}}) | (pid1 & {`PID_WIDTH{xu_mm_rf1_val[1]}}); + assign ex1_mas0_atsel = (mas0_0_atsel & ex1_valid_q[0]) | (mas0_1_atsel & ex1_valid_q[1]); + assign ex1_mas0_esel = (mas0_0_esel & {3{ex1_valid_q[0]}}) | (mas0_1_esel & {3{ex1_valid_q[1]}}); + assign ex1_mas0_hes = (mas0_0_hes & ex1_valid_q[0]) | (mas0_1_hes & ex1_valid_q[1]); + assign ex1_mas0_wq = (mas0_0_wq & {2{ex1_valid_q[0]}}) | (mas0_1_wq & {2{ex1_valid_q[1]}} ); + assign ex1_mas1_tid = (mas1_0_tid & {`PID_WIDTH{ex1_valid_q[0]}}) | (mas1_1_tid & {`PID_WIDTH{ex1_valid_q[1]}}); + assign ex1_mas1_ts = (mas1_0_ts & ex1_valid_q[0]) | (mas1_1_ts & ex1_valid_q[1]); + assign ex1_mas1_tsize = (mas1_0_tsize & {4{ex1_valid_q[0]}}) | (mas1_1_tsize & {4{ex1_valid_q[1]}}); + assign ex1_mas1_ind = (mas1_0_ind & ex1_valid_q[0]) | (mas1_1_ind & ex1_valid_q[1]); + assign ex1_mas1_v = (mas1_0_v & ex1_valid_q[0]) | (mas1_1_v & ex1_valid_q[1]); + assign ex1_mas1_iprot = (mas1_0_iprot & ex1_valid_q[0]) | (mas1_1_iprot & ex1_valid_q[1]); + assign ex1_mas2_epn = (mas2_0_epn[52 - `EPN_WIDTH:51] & {`EPN_WIDTH{ex1_valid_q[0]}}) | (mas2_1_epn[52 - `EPN_WIDTH:51] & {`EPN_WIDTH{ex1_valid_q[1]}}); + assign ex1_mas8_tgs = (mas8_0_tgs & ex1_valid_q[0]) | (mas8_1_tgs & ex1_valid_q[1]); + assign ex1_mas8_tlpid = (mas8_0_tlpid & {`LPID_WIDTH{ex1_valid_q[0]}}) | (mas8_1_tlpid & {`LPID_WIDTH{ex1_valid_q[1]}}); + + assign ex1_mmucr3_class = (mmucr3_0[54:55] & {`CLASS_WIDTH{ex1_valid_q[0]}}) | (mmucr3_1[54:55] & {`CLASS_WIDTH{ex1_valid_q[1]}}); + assign ex2_mas0_atsel = (mas0_0_atsel & ex2_valid_q[0]) | (mas0_1_atsel & ex2_valid_q[1]); + assign ex2_mas0_esel = (mas0_0_esel & {3{ex2_valid_q[0]}}) | (mas0_1_esel & {3{ex2_valid_q[1]}}); + assign ex2_mas0_hes = (mas0_0_hes & ex2_valid_q[0]) | (mas0_1_hes & ex2_valid_q[1]); + assign ex2_mas0_wq = (mas0_0_wq & {2{ex2_valid_q[0]}}) | (mas0_1_wq & {2{ex2_valid_q[1]}}); + assign ex2_mas1_ind = (mas1_0_ind & ex2_valid_q[0]) | (mas1_1_ind & ex2_valid_q[1]); + assign ex2_mas1_tid = (mas1_0_tid & {`PID_WIDTH{ex2_valid_q[0]}}) | (mas1_1_tid & {`PID_WIDTH{ex2_valid_q[1]}}); + + // state: 0:pr 1:gs 2:as 3:cm + assign ex2_mas5_1_state = ( {ex2_state_q[0], mas5_0_sgs, mas1_0_ts, ex2_state_q[3]} & {`CTL_STATE_WIDTH{ex2_valid_q[0]}} ) | + ( {ex2_state_q[0], mas5_1_sgs, mas1_1_ts, ex2_state_q[3]} & {`CTL_STATE_WIDTH{ex2_valid_q[1]}} ); + + assign ex2_mas5_6_state = ( {ex2_state_q[0], mas5_0_sgs, mas6_0_sas, ex2_state_q[3]} & {`CTL_STATE_WIDTH{ex2_valid_q[0]}} ) | + ( {ex2_state_q[0], mas5_1_sgs, mas6_1_sas, ex2_state_q[3]} & {`CTL_STATE_WIDTH{ex2_valid_q[1]}} ); + + assign ex2_mas5_slpid = (mas5_0_slpid & {`LPID_WIDTH{ex2_valid_q[0]}}) | (mas5_1_slpid & {`LPID_WIDTH{ex2_valid_q[1]}}); + + assign ex2_mas6_spid = (mas6_0_spid & {`PID_WIDTH{ex2_valid_q[0]}}) | (mas6_1_spid & {`PID_WIDTH{ex2_valid_q[1]}}); + + assign ex2_mas6_sind = (mas6_0_sind & ex2_valid_q[0]) | (mas6_1_sind & ex2_valid_q[1]); +`else + assign ex1_pid_d = (pid0 & {`PID_WIDTH{xu_mm_rf1_val[0]}}); + assign ex1_mas0_atsel = (mas0_0_atsel & ex1_valid_q[0]); + assign ex1_mas0_esel = (mas0_0_esel & {3{ex1_valid_q[0]}}); + assign ex1_mas0_hes = (mas0_0_hes & ex1_valid_q[0]); + assign ex1_mas0_wq = (mas0_0_wq & {2{ex1_valid_q[0]}}); + assign ex1_mas1_tid = (mas1_0_tid & {`PID_WIDTH{ex1_valid_q[0]}}); + assign ex1_mas1_ts = (mas1_0_ts & ex1_valid_q[0]); + assign ex1_mas1_tsize = (mas1_0_tsize & {4{ex1_valid_q[0]}}); + assign ex1_mas1_ind = (mas1_0_ind & ex1_valid_q[0]); + assign ex1_mas1_v = (mas1_0_v & ex1_valid_q[0]); + assign ex1_mas1_iprot = (mas1_0_iprot & ex1_valid_q[0]); + assign ex1_mas2_epn = (mas2_0_epn[52 - `EPN_WIDTH:51] & {`EPN_WIDTH{ex1_valid_q[0]}}); + assign ex1_mas8_tgs = (mas8_0_tgs & ex1_valid_q[0]); + assign ex1_mas8_tlpid = (mas8_0_tlpid & {`LPID_WIDTH{ex1_valid_q[0]}}); + + assign ex1_mmucr3_class = (mmucr3_0[54:55] & {`CLASS_WIDTH{ex1_valid_q[0]}}); + assign ex2_mas0_atsel = (mas0_0_atsel & ex2_valid_q[0]); + assign ex2_mas0_esel = (mas0_0_esel & {3{ex2_valid_q[0]}}); + assign ex2_mas0_hes = (mas0_0_hes & ex2_valid_q[0]); + assign ex2_mas0_wq = (mas0_0_wq & {2{ex2_valid_q[0]}}); + assign ex2_mas1_ind = (mas1_0_ind & ex2_valid_q[0]); + assign ex2_mas1_tid = (mas1_0_tid & {`PID_WIDTH{ex2_valid_q[0]}}); + + // state: 0:pr 1:gs 2:as 3:cm + assign ex2_mas5_1_state = ( {ex2_state_q[0], mas5_0_sgs, mas1_0_ts, ex2_state_q[3]} & {`CTL_STATE_WIDTH{ex2_valid_q[0]}} ); + + assign ex2_mas5_6_state = ( {ex2_state_q[0], mas5_0_sgs, mas6_0_sas, ex2_state_q[3]} & {`CTL_STATE_WIDTH{ex2_valid_q[0]}} ); + + assign ex2_mas5_slpid = (mas5_0_slpid & {`LPID_WIDTH{ex2_valid_q[0]}}); + + assign ex2_mas6_spid = (mas6_0_spid & {`PID_WIDTH{ex2_valid_q[0]}}); + + assign ex2_mas6_sind = (mas6_0_sind & ex2_valid_q[0]); +`endif + + assign ex2_itag_d = ex1_itag_q; + assign ex2_valid_d = ex1_valid_q & (~(xu_ex1_flush)); + assign ex2_flush_d = (|(ex1_ttype_q) == 1'b1) ? (ex1_valid_q & xu_ex1_flush) : + {`MM_THREADS{1'b0}}; + assign ex2_flush_req_d = ((ex1_ttype_q[0:1] != 2'b00 & read_req_taken_sig == 1'b0 & write_req_taken_sig == 1'b0)) ? (ex1_valid_q & (~(xu_ex1_flush))) : + {`MM_THREADS{1'b0}}; + assign ex2_ttype_d = ex1_ttype_q; + assign ex2_state_d = ex1_state_q; + assign ex2_pid_d = ex1_pid_q; + assign ex2_flush_req_local = ( (ex2_ttype_q[2:4] != 3'b000) & (search_req_taken_sig == 1'b0) & (searchresv_req_taken_sig == 1'b0) ) ? ex2_valid_q : + {`MM_THREADS{1'b0}}; + + // state: 0:pr 1:gs 2:as 3:cm + assign ex2_hv_state = (~ex2_state_q[0]) & (~ex2_state_q[1]); + assign ex6_hv_state = (~ex6_state_q[0]) & (~ex6_state_q[1]); + assign ex6_priv_state = (~ex6_state_q[0]); + assign ex6_dgtmi_state = |(ex6_valid_q & xu_mm_epcr_dgtmi); + assign ex3_valid_d = ex2_valid_q & (~(xu_ex2_flush)) & (~(ex2_flush_req_q)) & (~(ex2_flush_req_local)); + assign ex3_flush_d = (|(ex2_ttype_q) == 1'b1) ? ((ex2_valid_q & xu_ex2_flush) | ex2_flush_q | ex2_flush_req_q | ex2_flush_req_local) : + {`MM_THREADS{1'b0}}; + assign ex3_ttype_d = ex2_ttype_q; + assign ex3_state_d = ex2_state_q; + assign ex3_pid_d = ex2_pid_q; + assign tlb_ctl_ex3_valid = ex3_valid_q; + assign tlb_ctl_ex3_ttype = ex3_ttype_q; + // state: 0:pr 1:gs 2:as 3:cm + assign tlb_ctl_ex3_hv_state = (~ex3_state_q[0]) & (~ex3_state_q[1]); + + assign ex4_valid_d = ex3_valid_q & (~(xu_ex3_flush)); + assign ex4_flush_d = (|(ex3_ttype_q) == 1'b1) ? ((ex3_valid_q & xu_ex3_flush) | ex3_flush_q) : + {`MM_THREADS{1'b0}}; + assign ex4_ttype_d = ex3_ttype_q; + // state: 0:pr 1:gs 2:as 3:cm + assign ex4_state_d = ex3_state_q; + assign ex4_pid_d = ex3_pid_q; + + assign ex5_valid_d = ex4_valid_q & (~(xu_ex4_flush)); + assign ex5_flush_d = (|(ex4_ttype_q) == 1'b1) ? ((ex4_valid_q & xu_ex4_flush) | ex4_flush_q) : + {`MM_THREADS{1'b0}}; + assign ex5_ttype_d = ex4_ttype_q; + assign ex5_state_d = ex4_state_q; + assign ex5_pid_d = ex4_pid_q; + + // ex6 phase are holding latches for non-flushed tlbre,we,sx until tlb_seq is done + assign ex6_valid_d = ((tlb_seq_read_done_sig == 1'b1 | tlb_seq_write_done_sig == 1'b1 | tlb_seq_search_done_sig == 1'b1 | tlb_seq_searchresv_done_sig == 1'b1)) ? {`MM_THREADS{1'b0}} : + ((|(ex6_valid_q) == 1'b0 & |(ex5_ttype_q) == 1'b1)) ? (ex5_valid_q & (~(xu_ex5_flush))) : + ex6_valid_q; + assign ex6_flush_d = (|(ex5_ttype_q) == 1'b1) ? ((ex5_valid_q & xu_ex5_flush) | ex5_flush_q) : + {`MM_THREADS{1'b0}}; + assign ex6_ttype_d = (|(ex6_valid_q) == 1'b0) ? ex5_ttype_q : + ex6_ttype_q; + assign ex6_state_d = (|(ex6_valid_q) == 1'b0) ? ex5_state_q : + ex6_state_q; + assign ex6_pid_d = (|(ex6_valid_q) == 1'b0) ? ex5_pid_q : + ex6_pid_q; + assign tlb_ctl_barrier_done = ((tlb_seq_read_done_sig == 1'b1 | tlb_seq_write_done_sig == 1'b1 | tlb_seq_search_done_sig == 1'b1 | tlb_seq_searchresv_done_sig == 1'b1)) ? ex6_valid_q : + {`MM_THREADS{1'b0}}; + assign tlb_ctl_ord_type = {ex6_ttype_q[0:1], |(ex6_ttype_q[2:4])}; + // TLB Reservations + // ttype <= tlbre & tlbwe & tlbsx & tlbsxr & tlbsrx; + // mas0.wq: 00=ignore reserv, 01=write if reserved, 10=clear reserv, 11=not used + // reservation set: + // (1) proc completion of tlbsrx. when no reservation exists + // (2) proc holding resv executes another tlbsrx. thus establishing new resv + assign tlb_set_resv0 = ((ex6_valid_q[0] == 1'b1 & ex6_ttype_q[4] == 1'b1 & tlb_seq_set_resv == 1'b1)) ? 1'b1 : + 1'b0; +`ifdef MM_THREADS2 + assign tlb_set_resv1 = ((ex6_valid_q[1] == 1'b1 & ex6_ttype_q[4] == 1'b1 & tlb_seq_set_resv == 1'b1)) ? 1'b1 : + 1'b0; +`endif + + // reservation clear: + // (1) proc holding resv executes another tlbsrx. overwriting the old resv + // (2) any tlbivax snoop with gs,as,lpid,pid,sizemasked(epn,mas6.isize) matching resv.gs,as,lpid,pid,sizemasked(epn,mas6.isize) + // (note ind bit is not part of tlbivax criteria!!) + // (3) any proc sets mmucsr0.TLB0_FI=1 with lpidr matching resv.lpid + // (4) any proc executes tlbilx T=0 (all) with mas5.slpid matching resv.lpid + // (5) any proc executes tlbilx T=1 (pid) with mas5.slpid and mas6.spid matching resv.lpid,pid + // (6) any proc executes tlbilx T=3 (vpn) with mas gs,as,slpid,spid,sizemasked(epn,mas6.isize) matching + // resv.gs,as,lpid,pid,sizemasked(epn,mas6.isize) + // (note ind bit is not part of tlbilx criteria!!) + // (7a) any proc executes tlbwe not causing exception and with (wq=00 always, or wq=01 and proc holds resv) + // and mas regs ind,tgs,ts,tlpid,tid,sizemasked(epn,mas1.tsize) match resv.ind,gs,as,lpid,pid,sizemasked(epn,mas1.tsize) + // (7b) this proc executes tlbwe not causing exception and with (wq=10 clear my resv regardless of va) + // (8) any page table reload not causing an exception (due to pt fault, tlb inelig, or lrat miss) + // and PTE's tag ind=0,tgs,ts,tlpid,tid,sizemasked(epn,pte.size) match resv.ind=0,gs,as,lpid,pid,sizemasked(epn.pte.size) + // A2-specific non-architected clear states + // (9) any proc executes tlbwe not causing exception and with (wq=10 clear, or wq=11 always (same as 00)) + // and mas regs ind,tgs,ts,tlpid,tid,sizemasked(epn,mas1.tsize) match resv.ind,gs,as,lpid,pid,sizemasked(epn,mas1.tsize) + // (basically same as 7) + // (10) any proc executes tlbilx T=2 (gs) with mas5.sgs matching resv.gs + // (11) any proc executes tlbilx T=4 to 7 (class) with T(1:2) matching resv.class + // ttype <= tlbre & tlbwe & tlbsx & tlbsxr & tlbsrx; + // IS0: Local bit + // IS1/Class: 0=all, 1=tid, 2=gs, 3=vpn, 4=class0, 5=class1, 6=class2, 7=class3 + // mas0.wq: 00=ignore reserv write always, 01=write if reserved, 10=clear reserv, 11=same as 00 + assign tlb_clr_resv_d[0] = + // term 1, overwriting reservation, part of set_resv terms + // term 2, tlbivax VA match, snoop same as term 6 tlbilx T=3 (by vpn in lpid) + ( tlb_seq_snoop_resv_q[0] & (tlb_tag1_q[`tagpos_is:`tagpos_is + 3] == 4'b0011) & tlb_resv0_tag1_lpid_match & + tlb_resv0_tag1_pid_match & tlb_resv0_tag1_gs_snoop_match & tlb_resv0_tag1_as_snoop_match & tlb_resv0_tag1_epn_glob_match ) | + // term 3, mmucsr0.TLB0_FI=1, snoop same as term 4 tlbilx T=0 (all in lpid) + // term 4, tlbilx T=0 (all in lpid) + ( tlb_seq_snoop_resv_q[0] & (tlb_tag1_q[`tagpos_is:`tagpos_is + 3] == 4'b1000) & tlb_resv0_tag1_lpid_match ) | + // term 5, tlbilx T=1 (by pid in lpid) + ( tlb_seq_snoop_resv_q[0] & (tlb_tag1_q[`tagpos_is:`tagpos_is + 3] == 4'b1001) & tlb_resv0_tag1_lpid_match & tlb_resv0_tag1_pid_match ) | + // term 6, tlbilx T=3 (by vpn) + ( tlb_seq_snoop_resv_q[0] & (tlb_tag1_q[`tagpos_is:`tagpos_is + 3] == 4'b1011) & tlb_resv0_tag1_lpid_match & + tlb_resv0_tag1_pid_match & tlb_resv0_tag1_gs_snoop_match & tlb_resv0_tag1_as_snoop_match & tlb_resv0_tag1_epn_loc_match ) | + // term 7a, tlbwe wq=00 always, or wq=01 and proc holds resv + ( ((|(ex6_valid_q & tlb_resv_valid_vec) & (tlb_tag4_wq == 2'b01)) | (|(ex6_valid_q) & (tlb_tag4_wq == 2'b00))) & + ex6_ttype_q[1] & tlb_resv0_tag1_gs_tlbwe_match & tlb_resv0_tag1_as_tlbwe_match & tlb_resv0_tag1_lpid_match & tlb_resv0_tag1_pid_match & + tlb_resv0_tag1_epn_loc_match & tlb_resv0_tag1_ind_match ) | + // term 7b, tlbwe wq=10 unconditionally clear my resv (regardless of va) + ( ex6_valid_q[0] & ex6_ttype_q[1] & (tlb_tag4_wq == 2'b10) ) | + // term 8, ptereload (matching resv.vpn) + ( tlb_tag4_ptereload & tlb_resv0_tag1_gs_snoop_match & tlb_resv0_tag1_as_snoop_match & tlb_resv0_tag1_lpid_match & tlb_resv0_tag1_pid_match & tlb_resv0_tag1_epn_loc_match & tlb_resv0_tag1_ind_match ) | + // A2-specific non-architected clear states + // term 9, tlbwe wq=10 clear from anybody, or wq=11 from anybody always (same as 00) + ( ((|(ex6_valid_q) & (tlb_tag4_wq == 2'b10)) | (|(ex6_valid_q) & (tlb_tag4_wq == 2'b11))) & + ex6_ttype_q[1] & tlb_resv0_tag1_gs_tlbwe_match & tlb_resv0_tag1_as_tlbwe_match & tlb_resv0_tag1_lpid_match & tlb_resv0_tag1_pid_match & tlb_resv0_tag1_epn_loc_match & tlb_resv0_tag1_ind_match ) | + // term 10, tlbilx T=2 (gs=1) + // or (tlb_seq_snoop_resv_q() and Eq(tlb_tag1_q(tagpos_is to tagpos_is+3),"1010") and + // tlb_resv_tag1_gs_snoop_match) + // term 11, tlbilx T=4 (by class) + ( tlb_seq_snoop_resv_q[0] & (tlb_tag1_q[`tagpos_is:`tagpos_is + 1] == 2'b11) & tlb_resv0_tag1_class_match ); + +`ifdef MM_THREADS2 + assign tlb_clr_resv_d[1] = ( tlb_seq_snoop_resv_q[1] & (tlb_tag1_q[`tagpos_is:`tagpos_is + 3] == 4'b0011) & tlb_resv1_tag1_lpid_match & tlb_resv1_tag1_pid_match & + tlb_resv1_tag1_gs_snoop_match & tlb_resv1_tag1_as_snoop_match & tlb_resv1_tag1_epn_glob_match ) | + ( tlb_seq_snoop_resv_q[1] & (tlb_tag1_q[`tagpos_is:`tagpos_is + 3] == 4'b1000) & tlb_resv1_tag1_lpid_match ) | + ( tlb_seq_snoop_resv_q[1] & (tlb_tag1_q[`tagpos_is:`tagpos_is + 3] == 4'b1001) & tlb_resv1_tag1_lpid_match & tlb_resv1_tag1_pid_match ) | + ( tlb_seq_snoop_resv_q[1] & (tlb_tag1_q[`tagpos_is:`tagpos_is + 3] == 4'b1011) & tlb_resv1_tag1_lpid_match & tlb_resv1_tag1_pid_match & tlb_resv1_tag1_gs_snoop_match & tlb_resv1_tag1_as_snoop_match & tlb_resv1_tag1_epn_loc_match ) | + ( ((|(ex6_valid_q & tlb_resv_valid_vec) & (tlb_tag4_wq == 2'b01)) | (|(ex6_valid_q) & (tlb_tag4_wq == 2'b00))) & ex6_ttype_q[1] & + tlb_resv1_tag1_gs_tlbwe_match & tlb_resv1_tag1_as_tlbwe_match & tlb_resv1_tag1_lpid_match & tlb_resv1_tag1_pid_match & tlb_resv1_tag1_epn_loc_match & tlb_resv1_tag1_ind_match ) | + ( ex6_valid_q[1] & ex6_ttype_q[1] & (tlb_tag4_wq == 2'b10) ) | + ( tlb_tag4_ptereload & tlb_resv1_tag1_gs_snoop_match & tlb_resv1_tag1_as_snoop_match & tlb_resv1_tag1_lpid_match & tlb_resv1_tag1_pid_match & tlb_resv1_tag1_epn_loc_match & tlb_resv1_tag1_ind_match ) | + ( ((|(ex6_valid_q) & (tlb_tag4_wq == 2'b10)) | (|(ex6_valid_q) & (tlb_tag4_wq == 2'b11))) & ex6_ttype_q[1] & + tlb_resv1_tag1_gs_tlbwe_match & tlb_resv1_tag1_as_tlbwe_match & tlb_resv1_tag1_lpid_match & tlb_resv1_tag1_pid_match & tlb_resv1_tag1_epn_loc_match & tlb_resv1_tag1_ind_match ) | + ( tlb_seq_snoop_resv_q[1] & (tlb_tag1_q[`tagpos_is:`tagpos_is + 1] == 2'b11) & tlb_resv1_tag1_class_match ); + + assign tlb_resv_valid_vec = {tlb_resv0_valid_q, tlb_resv1_valid_q}; +`else + assign tlb_resv_valid_vec = {tlb_resv0_valid_q}; +`endif + assign tlb_resv_match_vec = tlb_resv_match_vec_q; + assign tlb_resv0_valid_d = (tlb_clr_resv_q[0] == 1'b1 & tlb_tag5_except[0] == 1'b0) ? 1'b0 : + (tlb_set_resv0 == 1'b1) ? ex6_valid_q[0] : + tlb_resv0_valid_q; + assign tlb_resv0_epn_d = ((tlb_set_resv0 == 1'b1)) ? tlb_tag0_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 1] : + tlb_resv0_epn_q; + assign tlb_resv0_pid_d = ((tlb_set_resv0 == 1'b1)) ? mas1_0_tid : + tlb_resv0_pid_q; + assign tlb_resv0_lpid_d = ((tlb_set_resv0 == 1'b1)) ? mas5_0_slpid : + tlb_resv0_lpid_q; + assign tlb_resv0_as_d = ((tlb_set_resv0 == 1'b1)) ? mas1_0_ts : + tlb_resv0_as_q; + assign tlb_resv0_gs_d = ((tlb_set_resv0 == 1'b1)) ? mas5_0_sgs : + tlb_resv0_gs_q; + assign tlb_resv0_ind_d = ((tlb_set_resv0 == 1'b1)) ? mas1_0_ind : + tlb_resv0_ind_q; + assign tlb_resv0_class_d = ((tlb_set_resv0 == 1'b1)) ? mmucr3_0[54:55] : + tlb_resv0_class_q; + // uniquify snoop/tlbwe as/gs match sigs because `tagpos_as/gs are msr state for tlbwe, not mas values + assign tlb_resv0_tag0_lpid_match = ((tlb_tag0_q[`tagpos_lpid:`tagpos_lpid + `LPID_WIDTH - 1] == tlb_resv0_lpid_q)) ? 1'b1 : + 1'b0; + assign tlb_resv0_tag0_pid_match = ((tlb_tag0_q[`tagpos_pid:`tagpos_pid + `PID_WIDTH - 1] == tlb_resv0_pid_q)) ? 1'b1 : + 1'b0; + assign tlb_resv0_tag0_gs_snoop_match = ((tlb_tag0_q[`tagpos_gs] == tlb_resv0_gs_q)) ? 1'b1 : + 1'b0; + assign tlb_resv0_tag0_as_snoop_match = ((tlb_tag0_q[`tagpos_as] == tlb_resv0_as_q)) ? 1'b1 : + 1'b0; + // unused `tagpos_pt, `tagpos_recform def are mas8_tgs, mas1_ts for tlbwe + assign tlb_resv0_tag0_gs_tlbwe_match = ((tlb_tag0_q[`tagpos_pt] == tlb_resv0_gs_q)) ? 1'b1 : + 1'b0; + assign tlb_resv0_tag0_as_tlbwe_match = ((tlb_tag0_q[`tagpos_recform] == tlb_resv0_as_q)) ? 1'b1 : + 1'b0; + assign tlb_resv0_tag0_ind_match = ((tlb_tag0_q[`tagpos_ind] == tlb_resv0_ind_q)) ? 1'b1 : + 1'b0; + assign tlb_resv0_tag0_class_match = ((tlb_tag0_q[`tagpos_class:`tagpos_class + 1] == tlb_resv0_class_q)) ? 1'b1 : + 1'b0; + // local match includes upper epn bits + assign tlb_resv0_tag0_epn_loc_match = ((tlb_tag0_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 1] == tlb_resv0_epn_q[52 - `EPN_WIDTH:51] & tlb_tag0_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_4KB) | (tlb_tag0_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 5] == tlb_resv0_epn_q[52 - `EPN_WIDTH:47] & tlb_tag0_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_64KB) | (tlb_tag0_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 9] == tlb_resv0_epn_q[52 - `EPN_WIDTH:43] & tlb_tag0_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_1MB) | (tlb_tag0_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 13] == tlb_resv0_epn_q[52 - `EPN_WIDTH:39] & tlb_tag0_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_16MB) | (tlb_tag0_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 17] == tlb_resv0_epn_q[52 - `EPN_WIDTH:35] & tlb_tag0_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_256MB) | (tlb_tag0_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 19] == tlb_resv0_epn_q[52 - `EPN_WIDTH:33] & tlb_tag0_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_1GB)) ? 1'b1 : + 1'b0; + // global match ignores certain upper epn bits that are not tranferred over bus + // fix me!! use various upper nibbles dependent on pgsize and mmucr1.tlbi_msb + assign tlb_resv0_tag0_epn_glob_match = ((tlb_tag0_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 1] == tlb_resv0_epn_q[52 - `EPN_WIDTH + 31:51] & tlb_tag0_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_4KB) | (tlb_tag0_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 5] == tlb_resv0_epn_q[52 - `EPN_WIDTH + 31:47] & tlb_tag0_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_64KB) | (tlb_tag0_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 9] == tlb_resv0_epn_q[52 - `EPN_WIDTH + 31:43] & tlb_tag0_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_1MB) | (tlb_tag0_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 13] == tlb_resv0_epn_q[52 - `EPN_WIDTH + 31:39] & tlb_tag0_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_16MB) | (tlb_tag0_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 17] == tlb_resv0_epn_q[52 - `EPN_WIDTH + 31:35] & tlb_tag0_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_256MB) | (tlb_tag0_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 19] == tlb_resv0_epn_q[52 - `EPN_WIDTH + 31:33] & tlb_tag0_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_1GB)) ? 1'b1 : + 1'b0; + // NOTE: ind is part of reservation tlbwe/ptereload match criteria, but not invalidate criteria + assign tlb_resv_match_vec_d[0] = (tlb_resv0_valid_q & tlb_tag0_q[`tagpos_type_snoop] == 1'b1 & tlb_resv0_tag0_epn_loc_match & tlb_resv0_tag0_lpid_match & tlb_resv0_tag0_pid_match & tlb_resv0_tag0_as_snoop_match & tlb_resv0_tag0_gs_snoop_match) | (tlb_resv0_valid_q & tlb_tag0_q[`tagpos_type_tlbwe] == 1'b1 & tlb_resv0_tag0_epn_loc_match & tlb_resv0_tag0_lpid_match & tlb_resv0_tag0_pid_match & tlb_resv0_tag0_as_tlbwe_match & tlb_resv0_tag0_gs_tlbwe_match & tlb_resv0_tag0_ind_match) | (tlb_resv0_valid_q & tlb_tag0_q[`tagpos_type_ptereload] == 1'b1 & tlb_resv0_tag0_epn_loc_match & tlb_resv0_tag0_lpid_match & tlb_resv0_tag0_pid_match & tlb_resv0_tag0_as_snoop_match & tlb_resv0_tag0_gs_snoop_match & tlb_resv0_tag0_ind_match); + +`ifdef MM_THREADS2 + assign tlb_resv1_valid_d = (tlb_clr_resv_q[1] == 1'b1 & tlb_tag5_except[1] == 1'b0) ? 1'b0 : + (tlb_set_resv1 == 1'b1) ? ex6_valid_q[1] : + tlb_resv1_valid_q; + assign tlb_resv1_epn_d = ((tlb_set_resv1 == 1'b1)) ? tlb_tag0_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 1] : + tlb_resv1_epn_q; + assign tlb_resv1_pid_d = ((tlb_set_resv1 == 1'b1)) ? mas1_1_tid : + tlb_resv1_pid_q; + assign tlb_resv1_lpid_d = ((tlb_set_resv1 == 1'b1)) ? mas5_1_slpid : + tlb_resv1_lpid_q; + assign tlb_resv1_as_d = ((tlb_set_resv1 == 1'b1)) ? mas1_1_ts : + tlb_resv1_as_q; + assign tlb_resv1_gs_d = ((tlb_set_resv1 == 1'b1)) ? mas5_1_sgs : + tlb_resv1_gs_q; + assign tlb_resv1_ind_d = ((tlb_set_resv1 == 1'b1)) ? mas1_1_ind : + tlb_resv1_ind_q; + assign tlb_resv1_class_d = ((tlb_set_resv1 == 1'b1)) ? mmucr3_1[54:55] : + tlb_resv1_class_q; + // uniquify snoop/tlbwe as/gs match sigs because `tagpos_as/gs are msr state for tlbwe, not mas values + assign tlb_resv1_tag0_lpid_match = ((tlb_tag0_q[`tagpos_lpid:`tagpos_lpid + `LPID_WIDTH - 1] == tlb_resv1_lpid_q)) ? 1'b1 : + 1'b0; + assign tlb_resv1_tag0_pid_match = ((tlb_tag0_q[`tagpos_pid:`tagpos_pid + `PID_WIDTH - 1] == tlb_resv1_pid_q)) ? 1'b1 : + 1'b0; + assign tlb_resv1_tag0_gs_snoop_match = ((tlb_tag0_q[`tagpos_gs] == tlb_resv1_gs_q)) ? 1'b1 : + 1'b0; + assign tlb_resv1_tag0_as_snoop_match = ((tlb_tag0_q[`tagpos_as] == tlb_resv1_as_q)) ? 1'b1 : + 1'b0; + assign tlb_resv1_tag0_gs_tlbwe_match = ((tlb_tag0_q[`tagpos_pt] == tlb_resv1_gs_q)) ? 1'b1 : + 1'b0; + assign tlb_resv1_tag0_as_tlbwe_match = ((tlb_tag0_q[`tagpos_recform] == tlb_resv1_as_q)) ? 1'b1 : + 1'b0; + assign tlb_resv1_tag0_ind_match = ((tlb_tag0_q[`tagpos_ind] == tlb_resv1_ind_q)) ? 1'b1 : + 1'b0; + assign tlb_resv1_tag0_class_match = ((tlb_tag0_q[`tagpos_class:`tagpos_class + 1] == tlb_resv1_class_q)) ? 1'b1 : + 1'b0; + // local match includes upper epn bits + assign tlb_resv1_tag0_epn_loc_match = ((tlb_tag0_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 1] == tlb_resv1_epn_q[52 - `EPN_WIDTH:51] & tlb_tag0_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_4KB) | (tlb_tag0_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 5] == tlb_resv1_epn_q[52 - `EPN_WIDTH:47] & tlb_tag0_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_64KB) | (tlb_tag0_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 9] == tlb_resv1_epn_q[52 - `EPN_WIDTH:43] & tlb_tag0_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_1MB) | (tlb_tag0_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 13] == tlb_resv1_epn_q[52 - `EPN_WIDTH:39] & tlb_tag0_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_16MB) | (tlb_tag0_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 17] == tlb_resv1_epn_q[52 - `EPN_WIDTH:35] & tlb_tag0_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_256MB) | (tlb_tag0_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 19] == tlb_resv1_epn_q[52 - `EPN_WIDTH:33] & tlb_tag0_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_1GB)) ? 1'b1 : + 1'b0; + // global match ignores certain upper epn bits that are not tranferred over bus + // fix me!! use various upper nibbles dependent on pgsize and mmucr1.tlbi_msb + assign tlb_resv1_tag0_epn_glob_match = ((tlb_tag0_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 1] == tlb_resv1_epn_q[52 - `EPN_WIDTH + 31:51] & tlb_tag0_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_4KB) | (tlb_tag0_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 5] == tlb_resv1_epn_q[52 - `EPN_WIDTH + 31:47] & tlb_tag0_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_64KB) | (tlb_tag0_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 9] == tlb_resv1_epn_q[52 - `EPN_WIDTH + 31:43] & tlb_tag0_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_1MB) | (tlb_tag0_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 13] == tlb_resv1_epn_q[52 - `EPN_WIDTH + 31:39] & tlb_tag0_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_16MB) | (tlb_tag0_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 17] == tlb_resv1_epn_q[52 - `EPN_WIDTH + 31:35] & tlb_tag0_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_256MB) | (tlb_tag0_q[`tagpos_epn + 31:`tagpos_epn + `EPN_WIDTH - 19] == tlb_resv1_epn_q[52 - `EPN_WIDTH + 31:33] & tlb_tag0_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_1GB)) ? 1'b1 : + 1'b0; + // NOTE: ind is part of reservation tlbwe/ptereload match criteria, but not invalidate criteria + assign tlb_resv_match_vec_d[1] = (tlb_resv1_valid_q & tlb_tag0_q[`tagpos_type_snoop] == 1'b1 & tlb_resv1_tag0_epn_loc_match & tlb_resv1_tag0_lpid_match & tlb_resv1_tag0_pid_match & tlb_resv1_tag0_as_snoop_match & tlb_resv1_tag0_gs_snoop_match) | (tlb_resv1_valid_q & tlb_tag0_q[`tagpos_type_tlbwe] == 1'b1 & tlb_resv1_tag0_epn_loc_match & tlb_resv1_tag0_lpid_match & tlb_resv1_tag0_pid_match & tlb_resv1_tag0_as_tlbwe_match & tlb_resv1_tag0_gs_tlbwe_match & tlb_resv1_tag0_ind_match) | (tlb_resv1_valid_q & tlb_tag0_q[`tagpos_type_ptereload] == 1'b1 & tlb_resv1_tag0_epn_loc_match & tlb_resv1_tag0_lpid_match & tlb_resv1_tag0_pid_match & tlb_resv1_tag0_as_snoop_match & tlb_resv1_tag0_gs_snoop_match & tlb_resv1_tag0_ind_match); +`endif + + // TLB Address Hash xor terms per size + // 4K 64K 1M 16M 256M 1G + //----------------------------------------------- + // 6 51 44 37 47 37 43 36 39 35 33 + // 5 50 43 36 46 36 42 35 38 34 32 + // 4 49 42 35 45 35 41 34 37 33 31 + // 3 48 41 34 44 34 40 33 36 32 32 30 + // 2 47 40 33 43 40 33 39 32 35 31 31 29 + // 1 46 39 32 42 39 32 38 31 34 30 30 28 28 + // 0 45 38 31 41 38 31 37 30 33 29 29 27 27 + // pid(9:15) <- tlb_tag0_q(53:59) + generate + if (`TLB_ADDR_WIDTH == 7) + begin : tlbaddrwidth7_gen + assign size_1G_hashed_addr[6] = tlb_tag0_q[33] ^ tlb_tag0_q[`tagpos_pid + `PID_WIDTH - 1]; + assign size_1G_hashed_addr[5] = tlb_tag0_q[32] ^ tlb_tag0_q[`tagpos_pid + `PID_WIDTH - 2]; + assign size_1G_hashed_addr[4] = tlb_tag0_q[31] ^ tlb_tag0_q[`tagpos_pid + `PID_WIDTH - 3]; + assign size_1G_hashed_addr[3] = tlb_tag0_q[30] ^ tlb_tag0_q[`tagpos_pid + `PID_WIDTH - 4]; + assign size_1G_hashed_addr[2] = tlb_tag0_q[29] ^ tlb_tag0_q[`tagpos_pid + `PID_WIDTH - 5]; + assign size_1G_hashed_addr[1] = tlb_tag0_q[28] ^ tlb_tag0_q[`tagpos_pid + `PID_WIDTH - 6]; + assign size_1G_hashed_addr[0] = tlb_tag0_q[27] ^ tlb_tag0_q[`tagpos_pid + `PID_WIDTH - 7]; + assign size_1G_hashed_tid0_addr[6] = tlb_tag0_q[33]; + assign size_1G_hashed_tid0_addr[5] = tlb_tag0_q[32]; + assign size_1G_hashed_tid0_addr[4] = tlb_tag0_q[31]; + assign size_1G_hashed_tid0_addr[3] = tlb_tag0_q[30]; + assign size_1G_hashed_tid0_addr[2] = tlb_tag0_q[29]; + assign size_1G_hashed_tid0_addr[1] = tlb_tag0_q[28]; + assign size_1G_hashed_tid0_addr[0] = tlb_tag0_q[27]; + assign size_256M_hashed_addr[6] = tlb_tag0_q[35] ^ tlb_tag0_q[`tagpos_pid + `PID_WIDTH - 1]; + assign size_256M_hashed_addr[5] = tlb_tag0_q[34] ^ tlb_tag0_q[`tagpos_pid + `PID_WIDTH - 2]; + assign size_256M_hashed_addr[4] = tlb_tag0_q[33] ^ tlb_tag0_q[`tagpos_pid + `PID_WIDTH - 3]; + assign size_256M_hashed_addr[3] = tlb_tag0_q[32] ^ tlb_tag0_q[`tagpos_pid + `PID_WIDTH - 4]; + assign size_256M_hashed_addr[2] = tlb_tag0_q[31] ^ tlb_tag0_q[`tagpos_pid + `PID_WIDTH - 5]; + assign size_256M_hashed_addr[1] = tlb_tag0_q[30] ^ tlb_tag0_q[28] ^ tlb_tag0_q[`tagpos_pid + `PID_WIDTH - 6]; + assign size_256M_hashed_addr[0] = tlb_tag0_q[29] ^ tlb_tag0_q[27] ^ tlb_tag0_q[`tagpos_pid + `PID_WIDTH - 7]; + assign size_256M_hashed_tid0_addr[6] = tlb_tag0_q[35]; + assign size_256M_hashed_tid0_addr[5] = tlb_tag0_q[34]; + assign size_256M_hashed_tid0_addr[4] = tlb_tag0_q[33]; + assign size_256M_hashed_tid0_addr[3] = tlb_tag0_q[32]; + assign size_256M_hashed_tid0_addr[2] = tlb_tag0_q[31]; + assign size_256M_hashed_tid0_addr[1] = tlb_tag0_q[30] ^ tlb_tag0_q[28]; + assign size_256M_hashed_tid0_addr[0] = tlb_tag0_q[29] ^ tlb_tag0_q[27]; + assign size_16M_hashed_addr[6] = tlb_tag0_q[39] ^ tlb_tag0_q[`tagpos_pid + `PID_WIDTH - 1]; + assign size_16M_hashed_addr[5] = tlb_tag0_q[38] ^ tlb_tag0_q[`tagpos_pid + `PID_WIDTH - 2]; + assign size_16M_hashed_addr[4] = tlb_tag0_q[37] ^ tlb_tag0_q[`tagpos_pid + `PID_WIDTH - 3]; + assign size_16M_hashed_addr[3] = tlb_tag0_q[36] ^ tlb_tag0_q[32] ^ tlb_tag0_q[`tagpos_pid + `PID_WIDTH - 4]; + assign size_16M_hashed_addr[2] = tlb_tag0_q[35] ^ tlb_tag0_q[31] ^ tlb_tag0_q[`tagpos_pid + `PID_WIDTH - 5]; + assign size_16M_hashed_addr[1] = tlb_tag0_q[34] ^ tlb_tag0_q[30] ^ tlb_tag0_q[`tagpos_pid + `PID_WIDTH - 6]; + assign size_16M_hashed_addr[0] = tlb_tag0_q[33] ^ tlb_tag0_q[29] ^ tlb_tag0_q[`tagpos_pid + `PID_WIDTH - 7]; + assign size_16M_hashed_tid0_addr[6] = tlb_tag0_q[39]; + assign size_16M_hashed_tid0_addr[5] = tlb_tag0_q[38]; + assign size_16M_hashed_tid0_addr[4] = tlb_tag0_q[37]; + assign size_16M_hashed_tid0_addr[3] = tlb_tag0_q[36] ^ tlb_tag0_q[32]; + assign size_16M_hashed_tid0_addr[2] = tlb_tag0_q[35] ^ tlb_tag0_q[31]; + assign size_16M_hashed_tid0_addr[1] = tlb_tag0_q[34] ^ tlb_tag0_q[30]; + assign size_16M_hashed_tid0_addr[0] = tlb_tag0_q[33] ^ tlb_tag0_q[29]; + assign size_1M_hashed_addr[6] = tlb_tag0_q[43] ^ tlb_tag0_q[36] ^ tlb_tag0_q[`tagpos_pid + `PID_WIDTH - 1]; + assign size_1M_hashed_addr[5] = tlb_tag0_q[42] ^ tlb_tag0_q[35] ^ tlb_tag0_q[`tagpos_pid + `PID_WIDTH - 2]; + assign size_1M_hashed_addr[4] = tlb_tag0_q[41] ^ tlb_tag0_q[34] ^ tlb_tag0_q[`tagpos_pid + `PID_WIDTH - 3]; + assign size_1M_hashed_addr[3] = tlb_tag0_q[40] ^ tlb_tag0_q[33] ^ tlb_tag0_q[`tagpos_pid + `PID_WIDTH - 4]; + assign size_1M_hashed_addr[2] = tlb_tag0_q[39] ^ tlb_tag0_q[32] ^ tlb_tag0_q[`tagpos_pid + `PID_WIDTH - 5]; + assign size_1M_hashed_addr[1] = tlb_tag0_q[38] ^ tlb_tag0_q[31] ^ tlb_tag0_q[`tagpos_pid + `PID_WIDTH - 6]; + assign size_1M_hashed_addr[0] = tlb_tag0_q[37] ^ tlb_tag0_q[30] ^ tlb_tag0_q[`tagpos_pid + `PID_WIDTH - 7]; + assign size_1M_hashed_tid0_addr[6] = tlb_tag0_q[43] ^ tlb_tag0_q[36]; + assign size_1M_hashed_tid0_addr[5] = tlb_tag0_q[42] ^ tlb_tag0_q[35]; + assign size_1M_hashed_tid0_addr[4] = tlb_tag0_q[41] ^ tlb_tag0_q[34]; + assign size_1M_hashed_tid0_addr[3] = tlb_tag0_q[40] ^ tlb_tag0_q[33]; + assign size_1M_hashed_tid0_addr[2] = tlb_tag0_q[39] ^ tlb_tag0_q[32]; + assign size_1M_hashed_tid0_addr[1] = tlb_tag0_q[38] ^ tlb_tag0_q[31]; + assign size_1M_hashed_tid0_addr[0] = tlb_tag0_q[37] ^ tlb_tag0_q[30]; + assign size_64K_hashed_addr[6] = tlb_tag0_q[47] ^ tlb_tag0_q[37] ^ tlb_tag0_q[`tagpos_pid + `PID_WIDTH - 1]; + assign size_64K_hashed_addr[5] = tlb_tag0_q[46] ^ tlb_tag0_q[36] ^ tlb_tag0_q[`tagpos_pid + `PID_WIDTH - 2]; + assign size_64K_hashed_addr[4] = tlb_tag0_q[45] ^ tlb_tag0_q[35] ^ tlb_tag0_q[`tagpos_pid + `PID_WIDTH - 3]; + assign size_64K_hashed_addr[3] = tlb_tag0_q[44] ^ tlb_tag0_q[34] ^ tlb_tag0_q[`tagpos_pid + `PID_WIDTH - 4]; + assign size_64K_hashed_addr[2] = tlb_tag0_q[43] ^ tlb_tag0_q[40] ^ tlb_tag0_q[33] ^ tlb_tag0_q[`tagpos_pid + `PID_WIDTH - 5]; + assign size_64K_hashed_addr[1] = tlb_tag0_q[42] ^ tlb_tag0_q[39] ^ tlb_tag0_q[32] ^ tlb_tag0_q[`tagpos_pid + `PID_WIDTH - 6]; + assign size_64K_hashed_addr[0] = tlb_tag0_q[41] ^ tlb_tag0_q[38] ^ tlb_tag0_q[31] ^ tlb_tag0_q[`tagpos_pid + `PID_WIDTH - 7]; + assign size_64K_hashed_tid0_addr[6] = tlb_tag0_q[47] ^ tlb_tag0_q[37]; + assign size_64K_hashed_tid0_addr[5] = tlb_tag0_q[46] ^ tlb_tag0_q[36]; + assign size_64K_hashed_tid0_addr[4] = tlb_tag0_q[45] ^ tlb_tag0_q[35]; + assign size_64K_hashed_tid0_addr[3] = tlb_tag0_q[44] ^ tlb_tag0_q[34]; + assign size_64K_hashed_tid0_addr[2] = tlb_tag0_q[43] ^ tlb_tag0_q[40] ^ tlb_tag0_q[33]; + assign size_64K_hashed_tid0_addr[1] = tlb_tag0_q[42] ^ tlb_tag0_q[39] ^ tlb_tag0_q[32]; + assign size_64K_hashed_tid0_addr[0] = tlb_tag0_q[41] ^ tlb_tag0_q[38] ^ tlb_tag0_q[31]; + assign size_4K_hashed_addr[6] = tlb_tag0_q[51] ^ tlb_tag0_q[44] ^ tlb_tag0_q[37] ^ tlb_tag0_q[`tagpos_pid + `PID_WIDTH - 1]; + assign size_4K_hashed_addr[5] = tlb_tag0_q[50] ^ tlb_tag0_q[43] ^ tlb_tag0_q[36] ^ tlb_tag0_q[`tagpos_pid + `PID_WIDTH - 2]; + assign size_4K_hashed_addr[4] = tlb_tag0_q[49] ^ tlb_tag0_q[42] ^ tlb_tag0_q[35] ^ tlb_tag0_q[`tagpos_pid + `PID_WIDTH - 3]; + assign size_4K_hashed_addr[3] = tlb_tag0_q[48] ^ tlb_tag0_q[41] ^ tlb_tag0_q[34] ^ tlb_tag0_q[`tagpos_pid + `PID_WIDTH - 4]; + assign size_4K_hashed_addr[2] = tlb_tag0_q[47] ^ tlb_tag0_q[40] ^ tlb_tag0_q[33] ^ tlb_tag0_q[`tagpos_pid + `PID_WIDTH - 5]; + assign size_4K_hashed_addr[1] = tlb_tag0_q[46] ^ tlb_tag0_q[39] ^ tlb_tag0_q[32] ^ tlb_tag0_q[`tagpos_pid + `PID_WIDTH - 6]; + assign size_4K_hashed_addr[0] = tlb_tag0_q[45] ^ tlb_tag0_q[38] ^ tlb_tag0_q[31] ^ tlb_tag0_q[`tagpos_pid + `PID_WIDTH - 7]; + assign size_4K_hashed_tid0_addr[6] = tlb_tag0_q[51] ^ tlb_tag0_q[44] ^ tlb_tag0_q[37]; + assign size_4K_hashed_tid0_addr[5] = tlb_tag0_q[50] ^ tlb_tag0_q[43] ^ tlb_tag0_q[36]; + assign size_4K_hashed_tid0_addr[4] = tlb_tag0_q[49] ^ tlb_tag0_q[42] ^ tlb_tag0_q[35]; + assign size_4K_hashed_tid0_addr[3] = tlb_tag0_q[48] ^ tlb_tag0_q[41] ^ tlb_tag0_q[34]; + assign size_4K_hashed_tid0_addr[2] = tlb_tag0_q[47] ^ tlb_tag0_q[40] ^ tlb_tag0_q[33]; + assign size_4K_hashed_tid0_addr[1] = tlb_tag0_q[46] ^ tlb_tag0_q[39] ^ tlb_tag0_q[32]; + assign size_4K_hashed_tid0_addr[0] = tlb_tag0_q[45] ^ tlb_tag0_q[38] ^ tlb_tag0_q[31]; + end + endgenerate + //constant TLB_PgSize_1GB := 1010 ; + //constant TLB_PgSize_256MB := 1001 ; + //constant TLB_PgSize_16MB := 0111 ; + //constant TLB_PgSize_1MB := 0101 ; + //constant TLB_PgSize_64KB := 0011 ; + //constant TLB_PgSize_4KB := 0001 ; + assign tlb_tag0_tid_notzero = |(tlb_tag0_q[`tagpos_pid:`tagpos_pid + `PID_WIDTH - 1]); + // these are used for direct and indirect page sizes + assign tlb_tag0_hashed_addr = (tlb_tag0_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_1GB) ? size_1G_hashed_addr : + (tlb_tag0_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_256MB) ? size_256M_hashed_addr : + (tlb_tag0_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_16MB) ? size_16M_hashed_addr : + (tlb_tag0_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_1MB) ? size_1M_hashed_addr : + (tlb_tag0_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_64KB) ? size_64K_hashed_addr : + size_4K_hashed_addr; + assign tlb_tag0_hashed_tid0_addr = (tlb_tag0_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_1GB) ? size_1G_hashed_tid0_addr : + (tlb_tag0_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_256MB) ? size_256M_hashed_tid0_addr : + (tlb_tag0_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_16MB) ? size_16M_hashed_tid0_addr : + (tlb_tag0_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_1MB) ? size_1M_hashed_tid0_addr : + (tlb_tag0_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_64KB) ? size_64K_hashed_tid0_addr : + size_4K_hashed_tid0_addr; + // these are used for direct page sizes only + assign tlb_hashed_addr1 = (mmucr2[28:31] == TLB_PgSize_1GB) ? size_1G_hashed_addr : + (mmucr2[28:31] == TLB_PgSize_16MB) ? size_16M_hashed_addr : + (mmucr2[28:31] == TLB_PgSize_1MB) ? size_1M_hashed_addr : + (mmucr2[28:31] == TLB_PgSize_64KB) ? size_64K_hashed_addr : + size_4K_hashed_addr; + assign tlb_hashed_tid0_addr1 = (mmucr2[28:31] == TLB_PgSize_1GB) ? size_1G_hashed_tid0_addr : + (mmucr2[28:31] == TLB_PgSize_16MB) ? size_16M_hashed_tid0_addr : + (mmucr2[28:31] == TLB_PgSize_1MB) ? size_1M_hashed_tid0_addr : + (mmucr2[28:31] == TLB_PgSize_64KB) ? size_64K_hashed_tid0_addr : + size_4K_hashed_tid0_addr; + assign tlb_hashed_addr2 = (mmucr2[24:27] == TLB_PgSize_1GB) ? size_1G_hashed_addr : + (mmucr2[24:27] == TLB_PgSize_16MB) ? size_16M_hashed_addr : + (mmucr2[24:27] == TLB_PgSize_1MB) ? size_1M_hashed_addr : + (mmucr2[24:27] == TLB_PgSize_64KB) ? size_64K_hashed_addr : + size_4K_hashed_addr; + assign tlb_hashed_tid0_addr2 = (mmucr2[24:27] == TLB_PgSize_1GB) ? size_1G_hashed_tid0_addr : + (mmucr2[24:27] == TLB_PgSize_16MB) ? size_16M_hashed_tid0_addr : + (mmucr2[24:27] == TLB_PgSize_1MB) ? size_1M_hashed_tid0_addr : + (mmucr2[24:27] == TLB_PgSize_64KB) ? size_64K_hashed_tid0_addr : + size_4K_hashed_tid0_addr; + assign tlb_hashed_addr3 = (mmucr2[20:23] == TLB_PgSize_1GB) ? size_1G_hashed_addr : + (mmucr2[20:23] == TLB_PgSize_16MB) ? size_16M_hashed_addr : + (mmucr2[20:23] == TLB_PgSize_1MB) ? size_1M_hashed_addr : + (mmucr2[20:23] == TLB_PgSize_64KB) ? size_64K_hashed_addr : + size_4K_hashed_addr; + assign tlb_hashed_tid0_addr3 = (mmucr2[20:23] == TLB_PgSize_1GB) ? size_1G_hashed_tid0_addr : + (mmucr2[20:23] == TLB_PgSize_16MB) ? size_16M_hashed_tid0_addr : + (mmucr2[20:23] == TLB_PgSize_1MB) ? size_1M_hashed_tid0_addr : + (mmucr2[20:23] == TLB_PgSize_64KB) ? size_64K_hashed_tid0_addr : + size_4K_hashed_tid0_addr; + assign tlb_hashed_addr4 = (mmucr2[16:19] == TLB_PgSize_1GB) ? size_1G_hashed_addr : + (mmucr2[16:19] == TLB_PgSize_16MB) ? size_16M_hashed_addr : + (mmucr2[16:19] == TLB_PgSize_1MB) ? size_1M_hashed_addr : + (mmucr2[16:19] == TLB_PgSize_64KB) ? size_64K_hashed_addr : + size_4K_hashed_addr; + assign tlb_hashed_tid0_addr4 = (mmucr2[16:19] == TLB_PgSize_1GB) ? size_1G_hashed_tid0_addr : + (mmucr2[16:19] == TLB_PgSize_16MB) ? size_16M_hashed_tid0_addr : + (mmucr2[16:19] == TLB_PgSize_1MB) ? size_1M_hashed_tid0_addr : + (mmucr2[16:19] == TLB_PgSize_64KB) ? size_64K_hashed_tid0_addr : + size_4K_hashed_tid0_addr; + assign tlb_hashed_addr5 = (mmucr2[12:15] == TLB_PgSize_1GB) ? size_1G_hashed_addr : + (mmucr2[12:15] == TLB_PgSize_16MB) ? size_16M_hashed_addr : + (mmucr2[12:15] == TLB_PgSize_1MB) ? size_1M_hashed_addr : + (mmucr2[12:15] == TLB_PgSize_64KB) ? size_64K_hashed_addr : + size_4K_hashed_addr; + assign tlb_hashed_tid0_addr5 = (mmucr2[12:15] == TLB_PgSize_1GB) ? size_1G_hashed_tid0_addr : + (mmucr2[12:15] == TLB_PgSize_16MB) ? size_16M_hashed_tid0_addr : + (mmucr2[12:15] == TLB_PgSize_1MB) ? size_1M_hashed_tid0_addr : + (mmucr2[12:15] == TLB_PgSize_64KB) ? size_64K_hashed_tid0_addr : + size_4K_hashed_tid0_addr; + assign pgsize1_valid = |(mmucr2[28:31]); + assign pgsize2_valid = |(mmucr2[24:27]); + assign pgsize3_valid = |(mmucr2[20:23]); + assign pgsize4_valid = |(mmucr2[16:19]); + assign pgsize5_valid = |(mmucr2[12:15]); + assign pgsize1_tid0_valid = |(mmucr2[28:31]); + assign pgsize2_tid0_valid = |(mmucr2[24:27]); + assign pgsize3_tid0_valid = |(mmucr2[20:23]); + assign pgsize4_tid0_valid = |(mmucr2[16:19]); + assign pgsize5_tid0_valid = |(mmucr2[12:15]); + assign pgsize_qty = ((pgsize5_valid == 1'b1 & pgsize4_valid == 1'b1 & pgsize3_valid == 1'b1 & pgsize2_valid == 1'b1 & pgsize1_valid == 1'b1)) ? 3'b101 : + ((pgsize4_valid == 1'b1 & pgsize3_valid == 1'b1 & pgsize2_valid == 1'b1 & pgsize1_valid == 1'b1)) ? 3'b100 : + ((pgsize3_valid == 1'b1 & pgsize2_valid == 1'b1 & pgsize1_valid == 1'b1)) ? 3'b011 : + ((pgsize2_valid == 1'b1 & pgsize1_valid == 1'b1)) ? 3'b010 : + ((pgsize1_valid == 1'b1)) ? 3'b001 : + 3'b000; + assign pgsize_tid0_qty = ((pgsize5_tid0_valid == 1'b1 & pgsize4_tid0_valid == 1'b1 & pgsize3_tid0_valid == 1'b1 & pgsize2_tid0_valid == 1'b1 & pgsize1_tid0_valid == 1'b1)) ? 3'b101 : + ((pgsize4_tid0_valid == 1'b1 & pgsize3_tid0_valid == 1'b1 & pgsize2_tid0_valid == 1'b1 & pgsize1_tid0_valid == 1'b1)) ? 3'b100 : + ((pgsize3_tid0_valid == 1'b1 & pgsize2_tid0_valid == 1'b1 & pgsize1_tid0_valid == 1'b1)) ? 3'b011 : + ((pgsize2_tid0_valid == 1'b1 & pgsize1_tid0_valid == 1'b1)) ? 3'b010 : + ((pgsize1_tid0_valid == 1'b1)) ? 3'b001 : + 3'b000; + assign derat_taken_d = (derat_req_taken_sig == 1'b1) ? 1'b1 : + (ierat_req_taken_sig == 1'b1) ? 1'b0 : + derat_taken_q; + // ttype: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload + assign tlb_read_req = ((|(ex1_valid_q) == 1'b1 & ex1_ttype_q[0] == 1'b1)) ? 1'b1 : + 1'b0; + assign tlb_write_req = ((|(ex1_valid_q) == 1'b1 & ex1_ttype_q[1] == 1'b1)) ? 1'b1 : + 1'b0; + assign tlb_search_req = ((|(ex2_valid_q) == 1'b1 & ex2_ttype_q[2:3] != 2'b00)) ? 1'b1 : + 1'b0; + assign tlb_searchresv_req = ((|(ex2_valid_q) == 1'b1 & ex2_ttype_q[4] == 1'b1)) ? 1'b1 : + 1'b0; + assign tlb_seq_idle_sig = (tlb_seq_q == TlbSeq_Idle) ? 1'b1 : + 1'b0; + assign tlbwe_back_inv_holdoff = tlbwe_back_inv_pending & mmucr1_tlbwe_binv; + assign tlb_seq_any_done_sig = tlb_seq_ierat_done_sig | tlb_seq_derat_done_sig | tlb_seq_snoop_done_sig | tlb_seq_search_done_sig | tlb_seq_searchresv_done_sig | tlb_seq_read_done_sig | tlb_seq_write_done_sig | tlb_seq_ptereload_done_sig; + assign any_tlb_req_sig = snoop_val_q[0] | ptereload_req_valid | tlb_seq_ierat_req | tlb_seq_derat_req | tlb_search_req | tlb_searchresv_req | tlb_write_req | tlb_read_req; + assign any_req_taken_sig = ierat_req_taken_sig | derat_req_taken_sig | snoop_req_taken_sig | search_req_taken_sig | searchresv_req_taken_sig | read_req_taken_sig | write_req_taken_sig | ptereload_req_taken_sig; + assign tlb_tag4_hit_or_parerr = tlb_tag4_cmp_hit | tlb_tag4_parerr; + + // abort control sequencer back to state_idle + // tlbsx, tlbsrx, tlbre, tlbwe are flushable ops, so short-cycle sequencer + assign tlb_seq_abort = |( tlb_tag0_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS -1] & (tlb_ctl_tag1_flush_sig | tlb_ctl_tag2_flush_sig | tlb_ctl_tag3_flush_sig | tlb_ctl_tag4_flush_sig) ); + + assign tlb_seq_d = tlb_seq_next & {`TLB_SEQ_WIDTH{(~(tlb_seq_abort))}}; + + + // TLB access sequencer for multiple page size compares for reloads + always @(tlb_seq_q or tlb_tag0_q[`tagpos_is + 1:`tagpos_is + 3] or tlb_tag0_q[`tagpos_size:`tagpos_size + 3] or + tlb_tag0_q[`tagpos_type:`tagpos_type + 7] or tlb_tag0_q[`tagpos_type:`tagpos_type + 7] or tlb_tag1_q[`tagpos_endflag] or + tlb_tag0_tid_notzero or tlb_tag0_q[`tagpos_nonspec] or tlb_tag4_hit_or_parerr or tlb_tag4_way_ind or tlb_addr_maxcntm1 or + tlb_cmp_erat_dup_wait or tlb_seq_ierat_req or tlb_seq_derat_req or tlb_search_req or tlb_searchresv_req or snoop_val_q[0] or + tlb_read_req or tlb_write_req or ptereload_req_valid or mmucr2[12:31] or derat_taken_q or + tlb_hashed_addr1 or tlb_hashed_addr2 or tlb_hashed_addr3 or tlb_hashed_addr4 or tlb_hashed_addr5 or + tlb_hashed_tid0_addr1 or tlb_hashed_tid0_addr2 or tlb_hashed_tid0_addr3 or tlb_hashed_tid0_addr4 or tlb_hashed_tid0_addr5 or + pgsize2_valid or pgsize3_valid or pgsize4_valid or pgsize5_valid or + pgsize2_tid0_valid or pgsize3_tid0_valid or pgsize4_tid0_valid or pgsize5_tid0_valid or + size_1M_hashed_addr or size_1M_hashed_tid0_addr or size_256M_hashed_addr or size_256M_hashed_tid0_addr or + tlb_tag0_hashed_addr or tlb_tag0_hashed_tid0_addr or tlb0cfg_ind or tlbwe_back_inv_holdoff) + begin: Tlb_Sequencer + tlb_seq_addr = {`TLB_ADDR_WIDTH{1'b0}}; + tlb_seq_pgsize = mmucr2[28:31]; + tlb_seq_ind = 1'b0; + tlb_seq_esel = 3'b000; + tlb_seq_is = 2'b00; + tlb_seq_tag0_addr_cap = 1'b0; + tlb_seq_addr_update = 1'b0; + tlb_seq_addr_clr = 1'b0; + tlb_seq_addr_incr = 1'b0; + tlb_seq_lrat_enable = 1'b0; + tlb_seq_endflag = 1'b0; + tlb_seq_ierat_done_sig = 1'b0; + tlb_seq_derat_done_sig = 1'b0; + tlb_seq_snoop_done_sig = 1'b0; + tlb_seq_search_done_sig = 1'b0; + tlb_seq_searchresv_done_sig = 1'b0; + tlb_seq_read_done_sig = 1'b0; + tlb_seq_write_done_sig = 1'b0; + tlb_seq_ptereload_done_sig = 1'b0; + tlb_seq_lru_rd_act = 1'b0; + tlb_seq_lru_wr_act = 1'b0; + ierat_req_taken_sig = 1'b0; + derat_req_taken_sig = 1'b0; + search_req_taken_sig = 1'b0; + searchresv_req_taken_sig = 1'b0; + snoop_req_taken_sig = 1'b0; + read_req_taken_sig = 1'b0; + write_req_taken_sig = 1'b0; + ptereload_req_taken_sig = 1'b0; + tlb_seq_set_resv = 1'b0; + tlb_seq_snoop_resv = 1'b0; + tlb_seq_snoop_inprogress = 1'b0; + + case (tlb_seq_q) + // wait for snoop, ptereload, erat miss, search, write, or read to service + TlbSeq_Idle : + if (snoop_val_q[0] == 1'b1) + // service invalidate snoop + begin + tlb_seq_next = TlbSeq_Stg24; + snoop_req_taken_sig = 1'b1; + tlb_seq_snoop_inprogress = 1'b1; + tlb_seq_lru_rd_act = 1'b1; + end + else if (ptereload_req_valid == 1'b1) + // service pte reload + begin + tlb_seq_next = TlbSeq_Stg19; + ptereload_req_taken_sig = 1'b1; + tlb_seq_lru_rd_act = 1'b1; + end + else if (tlb_seq_ierat_req == 1'b1 & tlb_cmp_erat_dup_wait[0] == 1'b0 & tlb_cmp_erat_dup_wait[1] == 1'b0 & (derat_taken_q == 1'b1 | tlb_seq_derat_req == 1'b0)) + // service ierat miss + begin + tlb_seq_next = TlbSeq_Stg1; + ierat_req_taken_sig = 1'b1; + tlb_seq_lru_rd_act = 1'b1; + end + else if (tlb_seq_derat_req == 1'b1 & tlb_cmp_erat_dup_wait[0] == 1'b0 & tlb_cmp_erat_dup_wait[1] == 1'b0) + begin + // service derat miss + tlb_seq_next = TlbSeq_Stg1; + derat_req_taken_sig = 1'b1; + tlb_seq_lru_rd_act = 1'b1; + end + else if (tlb_search_req == 1'b1) + // service search + begin + tlb_seq_next = TlbSeq_Stg1; + search_req_taken_sig = 1'b1; + tlb_seq_lru_rd_act = 1'b1; + end + else if (tlb_searchresv_req == 1'b1) + // service search and reserve + begin + tlb_seq_next = TlbSeq_Stg1; + searchresv_req_taken_sig = 1'b1; + tlb_seq_lru_rd_act = 1'b1; + end + else if (tlb_write_req == 1'b1 & tlbwe_back_inv_holdoff == 1'b0) + // service write + begin + tlb_seq_next = TlbSeq_Stg19; + write_req_taken_sig = 1'b1; + tlb_seq_lru_rd_act = 1'b1; + end + else if (tlb_read_req == 1'b1) + // service read + begin + tlb_seq_next = TlbSeq_Stg19; + read_req_taken_sig = 1'b1; + tlb_seq_lru_rd_act = 1'b1; + end + else + tlb_seq_next = TlbSeq_Idle; + + TlbSeq_Stg1 : + // tag0 phase, erat miss, or ex3 phase tlbsx/tlbsrx + begin + tlb_seq_tag0_addr_cap = 1'b1; + tlb_seq_addr_update = 1'b1; + tlb_seq_addr = tlb_hashed_addr1; // hash for tid=pid page size 1 + tlb_seq_pgsize = mmucr2[28:31]; + tlb_seq_is = 2'b00; // ind=0, tid/=0 pages + tlb_seq_esel = 3'b001; // page 1 + tlb_seq_lru_rd_act = 1'b1; + if (pgsize2_valid == 1'b1) + tlb_seq_next = TlbSeq_Stg2; + else + tlb_seq_next = TlbSeq_Stg6; + end + + TlbSeq_Stg2 : + // tag1 phase, ex4 phase + begin + tlb_seq_addr_update = 1'b1; + tlb_seq_addr = tlb_hashed_addr2; // hash for tid=pid page size 2 + tlb_seq_pgsize = mmucr2[24:27]; + tlb_seq_is = 2'b00; // ind=0, tid/=0 pages + tlb_seq_esel = 3'b010; // page 2 + tlb_seq_lru_rd_act = 1'b1; + if (pgsize3_valid == 1'b1) + tlb_seq_next = TlbSeq_Stg3; + else + tlb_seq_next = TlbSeq_Stg6; + end + + TlbSeq_Stg3 : + // tag2 phase, ex5 phase + begin + tlb_seq_addr_update = 1'b1; + tlb_seq_addr = tlb_hashed_addr3; // hash for tid=pid page size 3 + tlb_seq_pgsize = mmucr2[20:23]; + tlb_seq_is = 2'b00; // ind=0, tid/=0 pages + tlb_seq_esel = 3'b011; // page 3 + tlb_seq_lru_rd_act = 1'b1; + if (pgsize4_valid == 1'b1) + tlb_seq_next = TlbSeq_Stg4; + else + tlb_seq_next = TlbSeq_Stg6; + end + + TlbSeq_Stg4 : + // tag3 phase, ex6 phase + begin + tlb_seq_addr_update = 1'b1; + tlb_seq_addr = tlb_hashed_addr4; // hash for tid=pid page size 4 + tlb_seq_pgsize = mmucr2[16:19]; + tlb_seq_is = 2'b00; // ind=0, tid/=0 pages + tlb_seq_esel = 3'b100; // page 4 + tlb_seq_lru_rd_act = 1'b1; + if (pgsize5_valid == 1'b1) + tlb_seq_next = TlbSeq_Stg5; + else + tlb_seq_next = TlbSeq_Stg6; + end + + TlbSeq_Stg5 : + // tag4 phase, ex7 phase + begin + tlb_seq_addr_update = 1'b1; + tlb_seq_addr = tlb_hashed_addr5; // hash for tid=pid page size 5 + tlb_seq_pgsize = mmucr2[12:15]; + tlb_seq_is = 2'b00; // ind=0, tid/=0 pages + tlb_seq_esel = 3'b101; // page 5 + if (tlb_tag4_hit_or_parerr == 1'b1 & |(tlb_tag0_q[`tagpos_type_tlbsx:`tagpos_type_tlbsrx]) == 1'b1) + begin + tlb_seq_next = TlbSeq_Stg30; + tlb_seq_lru_rd_act = 1'b0; + end + else if (tlb_tag4_hit_or_parerr == 1'b1 & tlb_tag4_way_ind == 1'b0) + begin + tlb_seq_next = TlbSeq_Stg31; + tlb_seq_lru_rd_act = 1'b0; + tlb_seq_lru_wr_act = 1'b1; + end + else + begin + tlb_seq_next = TlbSeq_Stg6; + tlb_seq_lru_rd_act = 1'b1; + end + end + + TlbSeq_Stg6 : + // start checking ind=0, tid=0 page possibilites + begin + tlb_seq_addr_update = 1'b1; + tlb_seq_addr = tlb_hashed_tid0_addr1; // hash for tid=0 page size 1 + tlb_seq_pgsize = mmucr2[28:31]; + tlb_seq_is = 2'b01; // ind=0, tid=0 pages + tlb_seq_esel = 3'b001; // page 1 + if (tlb_tag4_hit_or_parerr == 1'b1 & |(tlb_tag0_q[`tagpos_type_tlbsx:`tagpos_type_tlbsrx]) == 1'b1) + begin + // results for previous direct page size + tlb_seq_next = TlbSeq_Stg30; + tlb_seq_lru_rd_act = 1'b0; + end + else if (tlb_tag4_hit_or_parerr == 1'b1 & tlb_tag4_way_ind == 1'b0) + begin + // results for previous direct page size + tlb_seq_next = TlbSeq_Stg31; + tlb_seq_lru_rd_act = 1'b0; + tlb_seq_lru_wr_act = 1'b1; + end + else if (pgsize2_tid0_valid == 1'b1) + begin + tlb_seq_next = TlbSeq_Stg7; // check next page hash + tlb_seq_lru_rd_act = 1'b1; + end + else if (tlb0cfg_ind == 1'b1 & tlb_tag0_q[`tagpos_nonspec] == 1'b1) // this is a non-speculative erat miss + begin + tlb_seq_next = TlbSeq_Stg11; // check indirect entries + tlb_seq_lru_rd_act = 1'b1; + end + else + begin + tlb_seq_endflag = 1'b1; + tlb_seq_next = TlbSeq_Stg15; // start of wait states + tlb_seq_lru_rd_act = 1'b1; + end + end + + TlbSeq_Stg7 : + begin + tlb_seq_addr_update = 1'b1; + tlb_seq_addr = tlb_hashed_tid0_addr2; // hash for tid=0 page size 2 + tlb_seq_pgsize = mmucr2[24:27]; + tlb_seq_is = 2'b01; // ind=0, tid=0 pages + tlb_seq_esel = 3'b010; // page 2 + if (tlb_tag4_hit_or_parerr == 1'b1 & |(tlb_tag0_q[`tagpos_type_tlbsx:`tagpos_type_tlbsrx]) == 1'b1) + begin + // results for previous direct page size + tlb_seq_next = TlbSeq_Stg30; + tlb_seq_lru_rd_act = 1'b0; + end + else if (tlb_tag4_hit_or_parerr == 1'b1 & tlb_tag4_way_ind == 1'b0) + begin + // results for previous direct page size + tlb_seq_next = TlbSeq_Stg31; + tlb_seq_lru_rd_act = 1'b0; + tlb_seq_lru_wr_act = 1'b1; + end + else if (pgsize3_tid0_valid == 1'b1) + begin + tlb_seq_next = TlbSeq_Stg8; // check next page hash + tlb_seq_lru_rd_act = 1'b1; + end + else if (tlb0cfg_ind == 1'b1 & tlb_tag0_q[`tagpos_nonspec] == 1'b1) + begin + tlb_seq_next = TlbSeq_Stg11; // check indirect entries + tlb_seq_lru_rd_act = 1'b1; + end + else + begin + tlb_seq_endflag = 1'b1; + tlb_seq_next = TlbSeq_Stg15; // start of wait states + tlb_seq_lru_rd_act = 1'b1; + end + end + + TlbSeq_Stg8 : + begin + tlb_seq_addr_update = 1'b1; + tlb_seq_addr = tlb_hashed_tid0_addr3; // hash for tid=0 page size 3 + tlb_seq_pgsize = mmucr2[20:23]; + tlb_seq_is = 2'b01; // ind=0, tid=0 pages + tlb_seq_esel = 3'b011; // page 3 + if (tlb_tag4_hit_or_parerr == 1'b1 & |(tlb_tag0_q[`tagpos_type_tlbsx:`tagpos_type_tlbsrx]) == 1'b1) + begin + // results for previous direct page size + tlb_seq_next = TlbSeq_Stg30; + tlb_seq_lru_rd_act = 1'b0; + end + else if (tlb_tag4_hit_or_parerr == 1'b1 & tlb_tag4_way_ind == 1'b0) + begin + // results for previous direct page size + tlb_seq_next = TlbSeq_Stg31; + tlb_seq_lru_rd_act = 1'b0; + tlb_seq_lru_wr_act = 1'b1; + end + else if (pgsize4_tid0_valid == 1'b1) + begin + tlb_seq_next = TlbSeq_Stg9; // check next page hash + tlb_seq_lru_rd_act = 1'b1; + end + else if (tlb0cfg_ind == 1'b1 & tlb_tag0_q[`tagpos_nonspec] == 1'b1) + begin + tlb_seq_next = TlbSeq_Stg11; // check indirect entries + tlb_seq_lru_rd_act = 1'b1; + end + else + begin + tlb_seq_endflag = 1'b1; + tlb_seq_next = TlbSeq_Stg15; // start of wait states + tlb_seq_lru_rd_act = 1'b1; + end + end + + TlbSeq_Stg9 : + begin + tlb_seq_addr_update = 1'b1; + tlb_seq_addr = tlb_hashed_tid0_addr4; // hash for tid=0 page size 4 + tlb_seq_pgsize = mmucr2[16:19]; + tlb_seq_is = 2'b01; // ind=0, tid=0 pages + tlb_seq_esel = 3'b100; // page 4 + if (tlb_tag4_hit_or_parerr == 1'b1 & |(tlb_tag0_q[`tagpos_type_tlbsx:`tagpos_type_tlbsrx]) == 1'b1) + begin + // results for previous direct page size + tlb_seq_next = TlbSeq_Stg30; + tlb_seq_lru_rd_act = 1'b0; + end + else if (tlb_tag4_hit_or_parerr == 1'b1 & tlb_tag4_way_ind == 1'b0) + begin + // results for previous direct page size + tlb_seq_next = TlbSeq_Stg31; + tlb_seq_lru_rd_act = 1'b0; + tlb_seq_lru_wr_act = 1'b1; + end + else if (pgsize5_tid0_valid == 1'b1) + begin + tlb_seq_next = TlbSeq_Stg10; // check next page hash + tlb_seq_lru_rd_act = 1'b1; + end + else if (tlb0cfg_ind == 1'b1 & tlb_tag0_q[`tagpos_nonspec] == 1'b1) + begin + tlb_seq_next = TlbSeq_Stg11; // check indirect entries + tlb_seq_lru_rd_act = 1'b1; + end + else + begin + tlb_seq_endflag = 1'b1; + tlb_seq_next = TlbSeq_Stg15; // start of wait states + tlb_seq_lru_rd_act = 1'b1; + end + end + + TlbSeq_Stg10 : + begin + tlb_seq_addr_update = 1'b1; + tlb_seq_addr = tlb_hashed_tid0_addr5; // hash for tid=0 page size 5 + tlb_seq_pgsize = mmucr2[12:15]; + tlb_seq_is = 2'b01; // ind=0, tid=0 pages + tlb_seq_esel = 3'b101; // page 5 + if (tlb_tag4_hit_or_parerr == 1'b1 & |(tlb_tag0_q[`tagpos_type_tlbsx:`tagpos_type_tlbsrx]) == 1'b1) + begin + // results for previous direct page size + tlb_seq_next = TlbSeq_Stg30; + tlb_seq_lru_rd_act = 1'b0; + end + else if (tlb_tag4_hit_or_parerr == 1'b1 & tlb_tag4_way_ind == 1'b0) + begin + // results for previous direct page size + tlb_seq_next = TlbSeq_Stg31; + tlb_seq_lru_rd_act = 1'b0; + tlb_seq_lru_wr_act = 1'b1; + end + else if (tlb0cfg_ind == 1'b1 & tlb_tag0_q[`tagpos_nonspec] == 1'b1) + begin + tlb_seq_next = TlbSeq_Stg11; // go check for indirect entries + tlb_seq_lru_rd_act = 1'b1; + end + else + begin + tlb_seq_endflag = 1'b1; + tlb_seq_next = TlbSeq_Stg15; // start of wait states + tlb_seq_lru_rd_act = 1'b1; + end + end + + TlbSeq_Stg11 : + // indirect entry size 1MB, 4K sub-pages, tid/=0 + begin + tlb_seq_ind = 1'b1; + tlb_seq_addr_update = 1'b1; + tlb_seq_addr = size_1M_hashed_addr; + tlb_seq_pgsize = TLB_PgSize_1MB; + tlb_seq_is = 2'b10; // ind=1, tid/=0 pages + tlb_seq_esel = 3'b001; // page 1 + if (tlb_tag4_hit_or_parerr == 1'b1 & |(tlb_tag0_q[`tagpos_type_tlbsx:`tagpos_type_tlbsrx]) == 1'b1) + begin + // results for previous direct page size + tlb_seq_next = TlbSeq_Stg30; + tlb_seq_lru_rd_act = 1'b0; + end + else if (tlb_tag4_hit_or_parerr == 1'b1 & tlb_tag4_way_ind == 1'b0) + begin + // results for previous direct page size + tlb_seq_next = TlbSeq_Stg31; + tlb_seq_lru_rd_act = 1'b0; + tlb_seq_lru_wr_act = 1'b1; + end + else + begin + tlb_seq_next = TlbSeq_Stg12; // next ind=1 page size + tlb_seq_lru_rd_act = 1'b1; + end + end + + TlbSeq_Stg12 : + // indirect entry size 256MB, 64K sub-pages, tid/=0 + begin + tlb_seq_ind = 1'b1; + tlb_seq_addr_update = 1'b1; + tlb_seq_addr = size_256M_hashed_addr; + tlb_seq_pgsize = TLB_PgSize_256MB; + tlb_seq_is = 2'b10; // ind=1, tid/=0 pages + tlb_seq_esel = 3'b010; // page 2 + if (tlb_tag4_hit_or_parerr == 1'b1 & |(tlb_tag0_q[`tagpos_type_tlbsx:`tagpos_type_tlbsrx]) == 1'b1) + begin + // results for previous direct page size + tlb_seq_next = TlbSeq_Stg30; + tlb_seq_lru_rd_act = 1'b0; + end + else if (tlb_tag4_hit_or_parerr == 1'b1 & tlb_tag4_way_ind == 1'b0) + begin + // results for previous direct page size + tlb_seq_next = TlbSeq_Stg31; + tlb_seq_lru_rd_act = 1'b0; + tlb_seq_lru_wr_act = 1'b1; + end + else + begin + tlb_seq_next = TlbSeq_Stg13; // go check for ind=1, tid=0 pages + tlb_seq_lru_rd_act = 1'b1; + end + end + + TlbSeq_Stg13 : + // indirect entry size 1MB, 4K sub-pages, tid=0 + begin + tlb_seq_ind = 1'b1; + tlb_seq_addr_update = 1'b1; + tlb_seq_addr = size_1M_hashed_tid0_addr; + tlb_seq_pgsize = TLB_PgSize_1MB; + tlb_seq_is = 2'b11; // ind=1, tid=0 pages + tlb_seq_esel = 3'b001; // page 1 + if (tlb_tag4_hit_or_parerr == 1'b1 & |(tlb_tag0_q[`tagpos_type_tlbsx:`tagpos_type_tlbsrx]) == 1'b1) + begin + // results for previous direct page size + tlb_seq_next = TlbSeq_Stg30; + tlb_seq_lru_rd_act = 1'b0; + end + else if (tlb_tag4_hit_or_parerr == 1'b1 & tlb_tag4_way_ind == 1'b0) + begin + // results for previous direct page size + tlb_seq_next = TlbSeq_Stg31; + tlb_seq_lru_rd_act = 1'b0; + tlb_seq_lru_wr_act = 1'b1; + end + else + begin + tlb_seq_next = TlbSeq_Stg14; // next page size + tlb_seq_lru_rd_act = 1'b1; + end + end + + TlbSeq_Stg14 : + // indirect entry size 256MB, 64K sub-pages, tid=0 + begin + tlb_seq_ind = 1'b1; + tlb_seq_addr_update = 1'b1; + tlb_seq_addr = size_256M_hashed_tid0_addr; + tlb_seq_pgsize = TLB_PgSize_256MB; + tlb_seq_is = 2'b11; // ind=1, tid=0 pages + tlb_seq_esel = 3'b010; // page 2 + if (tlb_tag4_hit_or_parerr == 1'b1 & |(tlb_tag0_q[`tagpos_type_tlbsx:`tagpos_type_tlbsrx]) == 1'b1) + begin + // results for previous direct page size + tlb_seq_next = TlbSeq_Stg30; + tlb_seq_lru_rd_act = 1'b0; + end + else if (tlb_tag4_hit_or_parerr == 1'b1 & tlb_tag4_way_ind == 1'b0) + begin + // results for previous direct page size + tlb_seq_next = TlbSeq_Stg31; + tlb_seq_lru_rd_act = 1'b0; + tlb_seq_lru_wr_act = 1'b1; + end + else + begin + tlb_seq_endflag = 1'b1; + tlb_seq_next = TlbSeq_Stg15; + tlb_seq_lru_rd_act = 1'b1; + end + end + + TlbSeq_Stg15 : + // wait_state_tag1 ..wait for results.. + begin + tlb_seq_addr = {`TLB_ADDR_WIDTH{1'b0}}; + tlb_seq_pgsize = {4{1'b0}}; + if (tlb_tag4_hit_or_parerr == 1'b1 & |(tlb_tag0_q[`tagpos_type_tlbsx:`tagpos_type_tlbsrx]) == 1'b1) + begin + // results for previous direct page size + tlb_seq_next = TlbSeq_Stg30; + tlb_seq_lru_rd_act = 1'b0; + end + else if (tlb_tag4_hit_or_parerr == 1'b1 & tlb_tag4_way_ind == 1'b0) + begin + // results for previous direct page size + tlb_seq_next = TlbSeq_Stg31; + tlb_seq_lru_rd_act = 1'b0; + tlb_seq_lru_wr_act = 1'b1; + end + else if (tlb_tag4_hit_or_parerr == 1'b1 & tlb_tag4_way_ind == 1'b1 & |(tlb_tag0_q[`tagpos_type_derat:`tagpos_type_ierat]) == 1'b1 & tlb_tag0_q[`tagpos_type_ptereload] == 1'b0) + begin + // results for previous indirect page size + tlb_seq_next = TlbSeq_Stg29; // handoff to table walker, or tlb_inelig if pt=0 + tlb_seq_lru_rd_act = 1'b0; + tlb_seq_lru_wr_act = 1'b1; + end + else + begin + tlb_seq_next = TlbSeq_Stg16; // next wait state + tlb_seq_lru_rd_act = 1'b1; + end + end + + TlbSeq_Stg16 : + // wait_state_tag2 ..wait for results.. + begin + tlb_seq_addr = {`TLB_ADDR_WIDTH{1'b0}}; + tlb_seq_pgsize = {4{1'b0}}; + if (tlb_tag4_hit_or_parerr == 1'b1 & |(tlb_tag0_q[`tagpos_type_tlbsx:`tagpos_type_tlbsrx]) == 1'b1) + begin + // results for previous direct page size + tlb_seq_next = TlbSeq_Stg30; + tlb_seq_lru_rd_act = 1'b0; + end + else if (tlb_tag4_hit_or_parerr == 1'b1 & tlb_tag4_way_ind == 1'b0) + begin + // results for previous direct page size + tlb_seq_next = TlbSeq_Stg31; + tlb_seq_lru_rd_act = 1'b0; + tlb_seq_lru_wr_act = 1'b1; + end + else if (tlb_tag4_hit_or_parerr == 1'b1 & tlb_tag4_way_ind == 1'b1) + begin + // results for previous indirect page size + tlb_seq_next = TlbSeq_Stg29; // handoff to table walker, or tlb_inelig if pt=0 + tlb_seq_lru_rd_act = 1'b0; + tlb_seq_lru_wr_act = 1'b1; + end + else + begin + tlb_seq_next = TlbSeq_Stg17; // next wait state + tlb_seq_lru_rd_act = 1'b1; + end + end + + TlbSeq_Stg17 : + // wait_state_tag3 ..wait for results.. + begin + tlb_seq_addr = {`TLB_ADDR_WIDTH{1'b0}}; + tlb_seq_pgsize = {4{1'b0}}; + if (tlb_tag4_hit_or_parerr == 1'b1 & |(tlb_tag0_q[`tagpos_type_tlbsx:`tagpos_type_tlbsrx]) == 1'b1) + begin + // results for previous direct page size + tlb_seq_next = TlbSeq_Stg30; + tlb_seq_lru_rd_act = 1'b0; + end + else if (tlb_tag4_hit_or_parerr == 1'b1 & tlb_tag4_way_ind == 1'b0) + begin + // results for previous direct page size + tlb_seq_next = TlbSeq_Stg31; + tlb_seq_lru_rd_act = 1'b0; + tlb_seq_lru_wr_act = 1'b1; + end + else if (tlb_tag4_hit_or_parerr == 1'b1 & tlb_tag4_way_ind == 1'b1) + begin + // results for previous indirect page size + tlb_seq_next = TlbSeq_Stg29; // handoff to table walker, or tlb_inelig if pt=0 + tlb_seq_lru_rd_act = 1'b0; + tlb_seq_lru_wr_act = 1'b1; + end + else + begin + tlb_seq_next = TlbSeq_Stg18; // next wait state + tlb_seq_lru_rd_act = 1'b1; + end + end + + TlbSeq_Stg18 : + // wait_state_tag4 ..wait for results.. + begin + tlb_seq_addr = {`TLB_ADDR_WIDTH{1'b0}}; + tlb_seq_pgsize = {4{1'b0}}; + if (tlb_tag4_hit_or_parerr == 1'b1 & |(tlb_tag0_q[`tagpos_type_tlbsx:`tagpos_type_tlbsrx]) == 1'b1) + begin + // results for previous direct page size + tlb_seq_next = TlbSeq_Stg30; + tlb_seq_lru_rd_act = 1'b0; + end + else if (tlb_tag4_hit_or_parerr == 1'b1 & tlb_tag4_way_ind == 1'b0) + begin + // results for previous direct page size + tlb_seq_next = TlbSeq_Stg31; + tlb_seq_lru_rd_act = 1'b0; + tlb_seq_lru_wr_act = 1'b1; + end + else if (tlb_tag4_hit_or_parerr == 1'b1 & tlb_tag4_way_ind == 1'b1) + begin + // results for previous indirect page size + tlb_seq_next = TlbSeq_Stg29; // handoff to table walker, or tlb_inelig if pt=0 + tlb_seq_lru_rd_act = 1'b0; + tlb_seq_lru_wr_act = 1'b1; + end + else + begin + tlb_seq_next = TlbSeq_Stg30; // tlb miss + tlb_seq_lru_rd_act = 1'b0; + end + end + + TlbSeq_Stg19 : + // tag0 (ex2) tlbre,tlbwe (flushable), or ptereload (not flushable) + begin + tlb_seq_pgsize = tlb_tag0_q[`tagpos_size:`tagpos_size + 3]; + tlb_seq_tag0_addr_cap = 1'b1; + tlb_seq_addr_update = 1'b1; + tlb_seq_lru_rd_act = 1'b1; + if (tlb_tag0_tid_notzero == 1'b1) + tlb_seq_addr = tlb_tag0_hashed_addr; + else + tlb_seq_addr = tlb_tag0_hashed_tid0_addr; + tlb_seq_next = TlbSeq_Stg20; + end + + TlbSeq_Stg20 : + // tag1 (ex3) tlbre,tlbwe, or ptereload + begin + tlb_seq_addr = {`TLB_ADDR_WIDTH{1'b0}}; + tlb_seq_pgsize = {4{1'b0}}; + tlb_seq_lru_rd_act = 1'b1; + tlb_seq_next = TlbSeq_Stg21; + end + + TlbSeq_Stg21 : + // tag2 (ex4) tlbre,tlbwe, or ptereload + begin + tlb_seq_lrat_enable = tlb_tag0_q[`tagpos_type_tlbwe] | tlb_tag0_q[`tagpos_type_ptereload]; + tlb_seq_addr = {`TLB_ADDR_WIDTH{1'b0}}; + tlb_seq_pgsize = {4{1'b0}}; + tlb_seq_lru_rd_act = 1'b1; + tlb_seq_next = TlbSeq_Stg22; + end + + TlbSeq_Stg22 : + // tag3 (ex5) tlbre,tlbwe, or ptereload + begin + tlb_seq_addr = {`TLB_ADDR_WIDTH{1'b0}}; + tlb_seq_pgsize = {4{1'b0}}; + tlb_seq_lru_rd_act = 1'b1; + tlb_seq_next = TlbSeq_Stg23; + end + + TlbSeq_Stg23 : + // tag4 (ex6) tlbre,tlbwe, or ptereload + // tag type bits --> derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload + begin + tlb_seq_addr = {`TLB_ADDR_WIDTH{1'b0}}; + tlb_seq_pgsize = {4{1'b0}}; + tlb_seq_read_done_sig = tlb_tag0_q[`tagpos_type_tlbre]; + tlb_seq_write_done_sig = tlb_tag0_q[`tagpos_type_tlbwe]; + tlb_seq_ptereload_done_sig = tlb_tag0_q[`tagpos_type_ptereload]; + if (tlb_tag0_q[`tagpos_type_tlbre] == 1'b1) + begin + tlb_seq_lru_rd_act = 1'b0; + tlb_seq_lru_wr_act = 1'b0; + tlb_seq_next = TlbSeq_Idle; // done with read or write + end + else + begin + tlb_seq_lru_rd_act = 1'b0; + tlb_seq_lru_wr_act = 1'b1; + tlb_seq_next = TlbSeq_Stg31; // tlbwe, or ptereload to erat thread stall clear + end + end + + TlbSeq_Stg24 : + // invalidate snoop start, snoop_wait_state_tag0 + begin + tlb_seq_snoop_inprogress = 1'b1; + tlb_seq_pgsize = tlb_tag0_q[`tagpos_size:`tagpos_size + 3]; + tlb_seq_tag0_addr_cap = 1'b1; + tlb_seq_snoop_resv = 1'b1; + tlb_seq_lru_rd_act = 1'b1; + tlb_seq_lru_wr_act = 1'b0; + // IS1/Class: 0=all, 1=tid, 2=gs, 3=vpn, 4=class0, 5=class1, 6=class2, 7=class3 + if (tlb_tag0_q[`tagpos_is + 1:`tagpos_is + 3] == 3'b011) + // inval by vpn, local or global + begin + tlb_seq_addr_update = 1'b1; + tlb_seq_addr_clr = 1'b0; + tlb_seq_endflag = 1'b1; // endflag now, no loop + end + else + begin + tlb_seq_addr_update = 1'b0; + tlb_seq_addr_clr = 1'b1; // clear tlb_addr for loop scenarios + tlb_seq_endflag = 1'b0; // endflag later for loop scenarios + end + if (tlb_tag0_tid_notzero == 1'b1) + tlb_seq_addr = tlb_tag0_hashed_addr; + else + tlb_seq_addr = tlb_tag0_hashed_tid0_addr; + tlb_seq_next = TlbSeq_Stg25; + end + + TlbSeq_Stg25 : + // snoop_wait_state_tag1 ..wait for results.. + // IS1/Class: 0=all, 1=tid, 2=gs, 3=vpn, 4=class0, 5=class1, 6=class2, 7=class3 + begin + tlb_seq_snoop_inprogress = 1'b1; + tlb_seq_addr = {`TLB_ADDR_WIDTH{1'b0}}; + tlb_seq_pgsize = {4{1'b0}}; + if (tlb_tag0_q[`tagpos_is + 1:`tagpos_is + 3] == 3'b011) + // inval by vpn, local or global + begin + tlb_seq_addr_incr = 1'b0; + tlb_seq_endflag = 1'b0; + end + else + begin + tlb_seq_addr_incr = 1'b1; // increment tlb_addr for loop scenarios + tlb_seq_endflag = tlb_addr_maxcntm1; + end + if (tlb_tag0_q[`tagpos_is + 1:`tagpos_is + 3] != 3'b011 & tlb_tag1_q[`tagpos_endflag] == 1'b0) + begin + tlb_seq_lru_rd_act = 1'b1; + tlb_seq_lru_wr_act = 1'b1; + tlb_seq_next = TlbSeq_Stg25; // loop until tag1 endflag + end + else if (tlb_tag0_q[`tagpos_is + 1:`tagpos_is + 3] != 3'b011 & tlb_tag1_q[`tagpos_endflag] == 1'b1) + begin + tlb_seq_lru_rd_act = 1'b1; // allows lru rd_addr to update to x00 + tlb_seq_lru_wr_act = 1'b1; + tlb_seq_next = TlbSeq_Stg26; // loop complete + end + else + begin + tlb_seq_lru_rd_act = 1'b1; + tlb_seq_lru_wr_act = 1'b0; + tlb_seq_next = TlbSeq_Stg26; // by vpn + end + end + + TlbSeq_Stg26 : + // snoop_wait_state_tag2 ..wait for results.. + begin + tlb_seq_snoop_inprogress = 1'b1; + tlb_seq_addr = {`TLB_ADDR_WIDTH{1'b0}}; + tlb_seq_pgsize = {4{1'b0}}; + tlb_seq_lru_rd_act = 1'b0; + tlb_seq_lru_wr_act = 1'b1; + tlb_seq_next = TlbSeq_Stg27; + end + + TlbSeq_Stg27 : + // snoop_wait_state_tag3 ..wait for results.. + begin + tlb_seq_snoop_inprogress = 1'b1; + tlb_seq_addr = {`TLB_ADDR_WIDTH{1'b0}}; + tlb_seq_pgsize = {4{1'b0}}; + tlb_seq_lru_rd_act = 1'b0; + tlb_seq_lru_wr_act = 1'b1; + tlb_seq_next = TlbSeq_Stg28; + end + + TlbSeq_Stg28 : + // snoop_wait_state_tag4 ..wait for results.. + begin + tlb_seq_snoop_inprogress = 1'b1; + tlb_seq_addr = {`TLB_ADDR_WIDTH{1'b0}}; + tlb_seq_pgsize = {4{1'b0}}; + tlb_seq_lru_rd_act = 1'b0; + tlb_seq_lru_wr_act = 1'b1; + tlb_seq_next = TlbSeq_Stg31; // invalidate snoop goto complete + end + + TlbSeq_Stg29 : + // ind=1 hit jumps here + // tag5, handoff to hw table walker and reservations updated + begin + tlb_seq_derat_done_sig = tlb_tag0_q[`tagpos_type_derat] & (~tlb_tag0_q[`tagpos_type_ptereload]); + tlb_seq_ierat_done_sig = tlb_tag0_q[`tagpos_type_ierat] & (~tlb_tag0_q[`tagpos_type_ptereload]); + tlb_seq_addr = {`TLB_ADDR_WIDTH{1'b0}}; + tlb_seq_pgsize = {4{1'b0}}; + tlb_seq_lru_wr_act = 1'b1; + tlb_seq_next = TlbSeq_Idle; // go idle + end + + TlbSeq_Stg30 : + // tlb miss, or search hit/miss, jumps here.. + // wait for possible exceptions to be asserted + // tag type bits --> derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload + begin + tlb_seq_addr = {`TLB_ADDR_WIDTH{1'b0}}; + tlb_seq_pgsize = {4{1'b0}}; + tlb_seq_derat_done_sig = tlb_tag0_q[`tagpos_type_derat] & (~tlb_tag0_q[`tagpos_type_ptereload]); + tlb_seq_ierat_done_sig = tlb_tag0_q[`tagpos_type_ierat] & (~tlb_tag0_q[`tagpos_type_ptereload]); + tlb_seq_search_done_sig = tlb_tag0_q[`tagpos_type_tlbsx]; + tlb_seq_searchresv_done_sig = tlb_tag0_q[`tagpos_type_tlbsrx]; + tlb_seq_snoop_done_sig = tlb_tag0_q[`tagpos_type_snoop]; + tlb_seq_snoop_inprogress = tlb_tag0_q[`tagpos_type_snoop]; + tlb_seq_set_resv = tlb_tag0_q[`tagpos_type_tlbsrx]; + tlb_seq_lru_rd_act = 1'b0; + tlb_seq_lru_wr_act = 1'b0; + + tlb_seq_next = TlbSeq_Idle; + end + + TlbSeq_Stg31 : + // direct entry hits, tlbwe, ptereloads, and snoops jump here.. + // tag5, lru update, erat reloads, and/or ptereload write into tlb + // tag type bits --> derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload + begin + tlb_seq_addr = {`TLB_ADDR_WIDTH{1'b0}}; + tlb_seq_pgsize = {4{1'b0}}; + tlb_seq_derat_done_sig = tlb_tag0_q[`tagpos_type_derat] & (~tlb_tag0_q[`tagpos_type_ptereload]); + tlb_seq_ierat_done_sig = tlb_tag0_q[`tagpos_type_ierat] & (~tlb_tag0_q[`tagpos_type_ptereload]); + tlb_seq_search_done_sig = tlb_tag0_q[`tagpos_type_tlbsx]; + tlb_seq_searchresv_done_sig = tlb_tag0_q[`tagpos_type_tlbsrx]; + tlb_seq_snoop_done_sig = tlb_tag0_q[`tagpos_type_snoop]; + tlb_seq_snoop_inprogress = tlb_tag0_q[`tagpos_type_snoop]; + tlb_seq_set_resv = tlb_tag0_q[`tagpos_type_tlbsrx]; + tlb_seq_lru_rd_act = 1'b0; + tlb_seq_lru_wr_act = 1'b1; + + if (tlb_tag0_q[`tagpos_type_ierat] == 1'b1 | tlb_tag0_q[`tagpos_type_derat] == 1'b1 | tlb_tag0_q[`tagpos_type_ptereload] == 1'b1) + tlb_seq_next = TlbSeq_Stg32; + else + tlb_seq_next = TlbSeq_Idle; + end + + TlbSeq_Stg32 : + // end of ptereload + // tag6, wait for erat duplicates to be cleared in tlb_req, and reservations updated + begin + tlb_seq_addr = {`TLB_ADDR_WIDTH{1'b0}}; + tlb_seq_pgsize = {4{1'b0}}; + tlb_seq_next = TlbSeq_Idle; + tlb_seq_lru_rd_act = 1'b0; + tlb_seq_lru_wr_act = 1'b0; + end + + default : + tlb_seq_next = TlbSeq_Idle; + + endcase + end + + assign ierat_req_taken = ierat_req_taken_sig; + assign derat_req_taken = derat_req_taken_sig; + assign tlb_seq_ierat_done = tlb_seq_ierat_done_sig; + assign tlb_seq_derat_done = tlb_seq_derat_done_sig; + assign ptereload_req_taken = ptereload_req_taken_sig; + assign tlb_seq_idle = tlb_seq_idle_sig; + // snoop_val: 0 -> valid, 1 -> ack + assign snoop_val_d[0] = (snoop_val_q[0] == 1'b0) ? tlb_snoop_val : + (snoop_req_taken_sig == 1'b1) ? 1'b0 : + snoop_val_q[0]; + assign snoop_val_d[1] = tlb_seq_snoop_done_sig; + assign tlb_snoop_ack = snoop_val_q[1]; + // snoop_attr: + // 0 -> Local + // 1:3 -> IS/Class: 0=all, 1=tid, 2=gs, 3=epn, 4=class0, 5=class1, 6=class2, 7=class3 + // 4:5 -> GS/TS + // 6:13 -> TID(6:13) + // 14:17 -> Size + // 18 -> reserved for tlb, extclass_enable(0) for erats + // 19 -> mmucsr0.tlb0fi for tlb, or TID_NZ for erats + // 20:25 -> TID(0:5) + // 26:33 -> LPID + // 34 -> IND + assign snoop_attr_d = (snoop_val_q[0] == 1'b0) ? tlb_snoop_attr : + snoop_attr_q; + assign snoop_vpn_d[52 - `EPN_WIDTH:51] = (snoop_val_q[0] == 1'b0) ? tlb_snoop_vpn : + snoop_vpn_q[52 - `EPN_WIDTH:51]; + assign ptereload_req_pte_d = (ptereload_req_taken_sig == 1'b1) ? ptereload_req_pte : + ptereload_req_pte_q; + assign ptereload_req_pte_lat = ptereload_req_pte_q; + //tlb_tag0_d <= ( 0:51 epn & + // 52:65 pid & + // 66:67 IS & + // 68:69 Class & + // 70:73 state (pr,gs,as,cm) & + // 74:77 thdid & + // 78:81 size & + // 82:83 derat_miss/ierat_miss & + // 84:85 tlbsx/tlbsrx & + // 86:87 inval_snoop/tlbre & + // 88:89 tlbwe/ptereload & + // 90:97 lpid & + // 98 indirect + // 99 atsel & + // 100:102 esel & + // 103:105 hes/wq(0:1) & + // 106:107 lrat/pt & + // 108 record form + // 109 endflag + // `tagpos_epn : natural := 0; + // `tagpos_pid : natural := 52; -- 14 bits + // `tagpos_is : natural := 66; + // `tagpos_class : natural := 68; + // `tagpos_state : natural := 70; -- state: 0:pr 1:gs 2:as 3:cm + // `tagpos_thdid : natural := 74; + // `tagpos_size : natural := 78; + // `tagpos_type : natural := 82; -- derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload + // `tagpos_lpid : natural := 90; + // `tagpos_ind : natural := 98; + // `tagpos_atsel : natural := 99; + // `tagpos_esel : natural := 100; + // `tagpos_hes : natural := 103; + // `tagpos_wq : natural := 104; + // `tagpos_lrat : natural := 106; + // `tagpos_pt : natural := 107; + // `tagpos_recform : natural := 108; + // `tagpos_endflag : natural := 109; + // snoop_attr: + // 0 -> Local + // 1:3 -> IS/Class: 0=all, 1=tid, 2=gs, 3=epn, 4=class0, 5=class1, 6=class2, 7=class3 + // 4:5 -> GS/TS + // 6:13 -> TID(6:13) + // 14:17 -> Size + // 18 -> reserved for tlb, extclass_enable(0) for erats + // 19 -> mmucsr0.tlb0fi for tlb, or TID_NZ for erats + // 20:25 -> TID(0:5) + // 26:33 -> LPID + // 34 -> IND + // TAG PHASE (q) DESCRPTION OPERATION / EXn + // -1 prehash arb tlbwe ex1 tlbre ex1 tlbsx ex2 tlbsrx ex2 + // 0 hash calc tlbwe ex2 tlbre ex2 tlbsx ex3 tlbsrx ex3 + // 1 tlb/lru cc addr tlbwe ex3 tlbre ex3 tlbsx ex4 tlbsrx ex4 + // 2 tlb/lru data out tlbwe ex4 tlbre ex4 tlbsx ex5 tlbsrx ex5 + // 3 comp & select tlbwe ex5 tlbre ex5 tlbsx ex6 tlbsrx ex6 + // 4 tlb/lru/mas update tlbwe ex6 tlbre ex6 tlbsx ex7 tlbsrx ex7 + // 5 erat reload + assign tlb_ctl_tag1_flush_sig = ((tlb_tag0_q[`tagpos_type_tlbre] == 1'b1 | tlb_tag0_q[`tagpos_type_tlbwe] == 1'b1)) ? ex3_flush_q : + ((tlb_tag0_q[`tagpos_type_tlbsx] == 1'b1 | tlb_tag0_q[`tagpos_type_tlbsrx] == 1'b1)) ? ex4_flush_q : + {`MM_THREADS{1'b0}}; + assign tlb_ctl_tag2_flush_sig = ((tlb_tag0_q[`tagpos_type_tlbre] == 1'b1 | tlb_tag0_q[`tagpos_type_tlbwe] == 1'b1)) ? ex4_flush_q : + ((tlb_tag0_q[`tagpos_type_tlbsx] == 1'b1 | tlb_tag0_q[`tagpos_type_tlbsrx] == 1'b1)) ? ex5_flush_q : + {`MM_THREADS{1'b0}}; + assign tlb_ctl_tag3_flush_sig = ((tlb_tag0_q[`tagpos_type_tlbre] == 1'b1 | tlb_tag0_q[`tagpos_type_tlbwe] == 1'b1)) ? ex5_flush_q : + ((tlb_tag0_q[`tagpos_type_tlbsx] == 1'b1 | tlb_tag0_q[`tagpos_type_tlbsrx] == 1'b1)) ? ex6_flush_q : + {`MM_THREADS{1'b0}}; + assign tlb_ctl_tag4_flush_sig = ((tlb_tag0_q[`tagpos_type_tlbre] == 1'b1 | tlb_tag0_q[`tagpos_type_tlbwe] == 1'b1)) ? ex6_flush_q : + {`MM_THREADS{1'b0}}; + assign tlb_ctl_any_tag_flush_sig = |(tlb_ctl_tag1_flush_sig | tlb_ctl_tag2_flush_sig | tlb_ctl_tag3_flush_sig | tlb_ctl_tag4_flush_sig); + assign tlb_ctl_tag2_flush = tlb_ctl_tag2_flush_sig | tlb_ctl_tag3_flush_sig | tlb_ctl_tag4_flush_sig; + assign tlb_ctl_tag3_flush = tlb_ctl_tag3_flush_sig | tlb_ctl_tag4_flush_sig; + assign tlb_ctl_tag4_flush = tlb_ctl_tag4_flush_sig; + + // 0 1 2 3 4 5 6 7 + // tag type bits --> derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload + // tag -1 phase, tlbwe/re ex1, tlbsx/srx ex2 + //tlb_tag0_d(`tagpos_type to `tagpos_type+7) <= + // ptereload_req_tag(`tagpos_type to `tagpos_type+1) & 000001 when ptereload_req_taken_sig='1' + // else 00000010 when write_req_taken_sig='1' + // else 00000100 when read_req_taken_sig='1' + // else 00001000 when snoop_req_taken_sig='1' + // else 00010000 when searchresv_req_taken_sig='1' + // else 00100000 when search_req_taken_sig='1' + // else 01000000 when ierat_req_taken_sig='1' + // else 10000000 when derat_req_taken_sig='1' + // else 00000000 when (tlb_seq_ierat_done_sig='1' or tlb_seq_derat_done_sig='1' or + // tlb_seq_snoop_done_sig='1' or tlb_seq_search_done_sig='1' or + // tlb_seq_searchresv_done_sig ='1' or tlb_seq_read_done_sig ='1' or + // tlb_seq_write_done_sig ='1' or tlb_seq_ptereload_done_sig ='1' or tlb_seq_abort='1') + // else tlb_tag0_q(`tagpos_type to `tagpos_type+7); + assign tlb_tag0_d[`tagpos_type_derat] = (derat_req_taken_sig) | + (ptereload_req_tag[`tagpos_type_derat] & ptereload_req_taken_sig) | + (tlb_tag0_q[`tagpos_type_derat] & (~tlb_seq_any_done_sig) & (~tlb_seq_abort)); + + assign tlb_tag0_d[`tagpos_type_ierat] = (ierat_req_taken_sig) | + (ptereload_req_tag[`tagpos_type_ierat] & ptereload_req_taken_sig) | + (tlb_tag0_q[`tagpos_type_ierat] & (~tlb_seq_any_done_sig) & (~tlb_seq_abort)); + + assign tlb_tag0_d[`tagpos_type_tlbsx] = (search_req_taken_sig) | + (tlb_tag0_q[`tagpos_type_tlbsx] & (~tlb_seq_any_done_sig) & (~tlb_seq_abort)); + + assign tlb_tag0_d[`tagpos_type_tlbsrx] = (searchresv_req_taken_sig) | + (tlb_tag0_q[`tagpos_type_tlbsrx] & (~tlb_seq_any_done_sig) & (~tlb_seq_abort)); + + assign tlb_tag0_d[`tagpos_type_snoop] = (snoop_req_taken_sig) | + (tlb_tag0_q[`tagpos_type_snoop] & (~tlb_seq_any_done_sig) & (~tlb_seq_abort)); + + assign tlb_tag0_d[`tagpos_type_tlbre] = (read_req_taken_sig) | + (tlb_tag0_q[`tagpos_type_tlbre] & (~tlb_seq_any_done_sig) & (~tlb_seq_abort)); + + assign tlb_tag0_d[`tagpos_type_tlbwe] = (write_req_taken_sig) | + (tlb_tag0_q[`tagpos_type_tlbwe] & (~tlb_seq_any_done_sig) & (~tlb_seq_abort)); + + assign tlb_tag0_d[`tagpos_type_ptereload] = (ptereload_req_taken_sig) | + (tlb_tag0_q[`tagpos_type_ptereload] & (~tlb_seq_any_done_sig) & (~tlb_seq_abort)); + + // state: 0:pr 1:gs 2:as 3:cm + //tlb_tag0_d(`tagpos_epn to `tagpos_epn+`EPN_WIDTH-1) <= + // ptereload_req_tag(`tagpos_epn to `tagpos_epn+`EPN_WIDTH-1) when ptereload_req_taken_sig='1' + // else ex1_mas2_epn when write_req_taken_sig='1' + // else ex1_mas2_epn when read_req_taken_sig='1' + // else snoop_vpn_q when snoop_req_taken_sig='1' + // IFDEF(CAT_EMF) + // else xu_mm_ex2_epn when searchresv_req_taken_sig='1' + // else xu_mm_ex2_epn when search_req_taken_sig='1' + // ELSE + // else xu_mm_ex1_rb when searchresv_req_taken_sig='1' + // else xu_mm_ex1_rb when search_req_taken_sig='1' + // ENDIF + // else ierat_req_epn when ierat_req_taken_sig='1' + // else derat_req_epn when derat_req_taken_sig='1' + // else tlb_tag0_q(`tagpos_epn to `tagpos_epn+`EPN_WIDTH-1); + + generate + if (`RS_DATA_WIDTH == 64) + begin : gen64_tag_epn + assign tlb_tag0_d[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 1] = + ( ptereload_req_tag[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 1] & {`EPN_WIDTH{ptereload_req_taken_sig}} ) | + ( ({(ex1_mas2_epn[0:31] & {32{ex1_state_q[3]}}), ex1_mas2_epn[32:`EPN_WIDTH - 1]}) & {`EPN_WIDTH{write_req_taken_sig}} ) | + ( ({(ex1_mas2_epn[0:31] & {32{ex1_state_q[3]}}), ex1_mas2_epn[32:`EPN_WIDTH - 1]}) & {`EPN_WIDTH{read_req_taken_sig}} ) | + ( snoop_vpn_q & {`EPN_WIDTH{snoop_req_taken_sig}} ) | + ( xu_mm_ex2_epn & {`EPN_WIDTH{searchresv_req_taken_sig}} ) | + ( xu_mm_ex2_epn & {`EPN_WIDTH{search_req_taken_sig}} ) | + ( ierat_req_epn & {`EPN_WIDTH{ierat_req_taken_sig}} ) | + ( derat_req_epn & {`EPN_WIDTH{derat_req_taken_sig}} ) | + ( tlb_tag0_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 1] & {`EPN_WIDTH{(~any_req_taken_sig)}} ); + end + endgenerate + + //tlb_tag0_d(`tagpos_epn to `tagpos_epn+`EPN_WIDTH-1) <= + // ptereload_req_tag(`tagpos_epn to `tagpos_epn+`EPN_WIDTH-1) when ptereload_req_taken_sig='1' + // else ex1_mas2_epn(52-`EPN_WIDTH to 51) when write_req_taken_sig='1' + // else ex1_mas2_epn(52-`EPN_WIDTH to 51) when read_req_taken_sig='1' + // else snoop_vpn_q(52-`EPN_WIDTH to 51) when snoop_req_taken_sig='1' + // IFDEF(CAT_EMF) + // else xu_mm_ex2_epn(52-`EPN_WIDTH to 51) when searchresv_req_taken_sig='1' + // else xu_mm_ex2_epn(52-`EPN_WIDTH to 51) when search_req_taken_sig='1' + // ELSE + // else xu_mm_ex1_rb(52-`EPN_WIDTH to 51) when searchresv_req_taken_sig='1' + // else xu_mm_ex1_rb(52-`EPN_WIDTH to 51) when search_req_taken_sig='1' + // ENDIF + // else ierat_req_epn(52-`EPN_WIDTH to 51) when ierat_req_taken_sig='1' + // else derat_req_epn(52-`EPN_WIDTH to 51) when derat_req_taken_sig='1' + // else tlb_tag0_q(`tagpos_epn to `tagpos_epn+`EPN_WIDTH-1); + generate + if (`RS_DATA_WIDTH == 32) + begin : gen32_tag_epn + assign tlb_tag0_d[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 1] = + ( ptereload_req_tag[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 1] & {`EPN_WIDTH{ptereload_req_taken_sig}} ) | + ( ex1_mas2_epn[52 - `EPN_WIDTH:51] & {`EPN_WIDTH{write_req_taken_sig}} ) | + ( ex1_mas2_epn[52 - `EPN_WIDTH:51] & {`EPN_WIDTH{read_req_taken_sig}} ) | + ( snoop_vpn_q[52 - `EPN_WIDTH:51] & {`EPN_WIDTH{snoop_req_taken_sig}} ) | + ( xu_mm_ex2_epn[52 - `EPN_WIDTH:51] & {`EPN_WIDTH{searchresv_req_taken_sig}} ) | + ( xu_mm_ex2_epn[52 - `EPN_WIDTH:51] & {`EPN_WIDTH{search_req_taken_sig}} ) | + ( ierat_req_epn[52 - `EPN_WIDTH:51] & {`EPN_WIDTH{ierat_req_taken_sig}} ) | + ( derat_req_epn[52 - `EPN_WIDTH:51] & {`EPN_WIDTH{derat_req_taken_sig}} ) | + ( tlb_tag0_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 1] & {`EPN_WIDTH{(~any_req_taken_sig)}} ); + end + endgenerate + + // snoop_attr: + // 0 -> Local + // 1:3 -> IS/Class: 0=all, 1=tid, 2=gs, 3=epn, 4=class0, 5=class1, 6=class2, 7=class3 + // 4:5 -> GS/TS + // 6:13 -> TID(6:13) + // 14:17 -> Size + // 18 -> reserved for tlb, extclass_enable(0) for erats + // 19 -> mmucsr0.tlb0fi for tlb, or TID_NZ for erats + // 20:25 -> TID(0:5) + // 26:33 -> LPID + // 34 -> IND + //tlb_tag0_d(`tagpos_pid to `tagpos_pid+`PID_WIDTH-1) <= + // ptereload_req_tag(`tagpos_pid to `tagpos_pid+`PID_WIDTH-1) when ptereload_req_taken_sig='1' + // else ex1_mas1_tid when write_req_taken_sig='1' + // else ex1_mas1_tid when read_req_taken_sig='1' + // else snoop_attr_q(20 to 25) & snoop_attr_q(6 to 13) when snoop_req_taken_sig='1' + // else ex2_mas1_tid when searchresv_req_taken_sig='1' + // else ex2_mas6_spid when search_req_taken_sig='1' + // else ierat_req_pid when ierat_req_taken_sig='1' + // else derat_req_pid when derat_req_taken_sig='1' + // else tlb_tag0_q(`tagpos_pid to `tagpos_pid+`PID_WIDTH-1); + assign tlb_tag0_d[`tagpos_pid:`tagpos_pid + `PID_WIDTH - 1] = + ( ptereload_req_tag[`tagpos_pid:`tagpos_pid + `PID_WIDTH - 1] & {`PID_WIDTH{ptereload_req_taken_sig}} ) | + ( ex1_mas1_tid & {`PID_WIDTH{write_req_taken_sig}} ) | + ( ex1_mas1_tid & {`PID_WIDTH{read_req_taken_sig}} ) | + ( {snoop_attr_q[20:25], snoop_attr_q[6:13]} & {`PID_WIDTH{snoop_req_taken_sig}} ) | + ( ex2_mas1_tid & {`PID_WIDTH{searchresv_req_taken_sig}} ) | + ( ex2_mas6_spid & {`PID_WIDTH{search_req_taken_sig}} ) | + ( ierat_req_pid & {`PID_WIDTH{ierat_req_taken_sig}} ) | + ( derat_req_pid & {`PID_WIDTH{derat_req_taken_sig}} ) | + ( tlb_tag0_q[`tagpos_pid:`tagpos_pid + `PID_WIDTH - 1] & {`PID_WIDTH{(~any_req_taken_sig)}} ); + + // snoop_attr: 0 -> Local + // snoop_attr: 1:3 -> IS/Class: 0=all, 1=tid, 2=gs, 3=vpn, 4=class0, 5=class1, 6=class2, 7=class3 + // unused `tagpos_is def is mas1_v, mas1_iprot for tlbwe, and is (pte.valid & 0) for ptereloads + //tlb_tag0_d(`tagpos_is to `tagpos_is+1) <= + // ptereload_req_pte(`ptepos_valid) & ptereload_req_tag(`tagpos_is+1) when ptereload_req_taken_sig='1' + // else ex1_mas1_v & ex1_mas1_iprot when write_req_taken_sig='1' -- re-purpose `tagpos_is as tlbwe 0=valid,1=iprot + // else 00 when read_req_taken_sig='1' + // else snoop_attr_q(0 to 1) when snoop_req_taken_sig='1' -- local | is(0) + // else 00 when searchresv_req_taken_sig='1' + // else 00 when search_req_taken_sig='1' + // else 00 when ierat_req_taken_sig='1' + // else 00 when derat_req_taken_sig='1' + // else tlb_tag0_q(`tagpos_is to `tagpos_is+1); + assign tlb_tag0_d[`tagpos_is:`tagpos_is + 1] = + ( ({ptereload_req_pte[`ptepos_valid], ptereload_req_tag[`tagpos_is + 1]}) & {2{ptereload_req_taken_sig}} ) | + ( ({ex1_mas1_v, ex1_mas1_iprot}) & {2{write_req_taken_sig}} ) | + ( snoop_attr_q[0:1] & {2{snoop_req_taken_sig}} ) | + ( tlb_tag0_q[`tagpos_is:`tagpos_is + 1] & {2{(~any_req_taken_sig)}} ); + + //tlb_tag0_d(`tagpos_class to `tagpos_class+1) <= + // ptereload_req_tag(`tagpos_class to `tagpos_class+1) when ptereload_req_taken_sig='1' + // else ex1_mmucr3_class when write_req_taken_sig='1' + // else 00 when read_req_taken_sig='1' + // else snoop_attr_q(2 to 3) when snoop_req_taken_sig='1' -- is(1:2) + // else 00 when searchresv_req_taken_sig='1' + // else 00 when search_req_taken_sig='1' + // else 00 when ierat_req_taken_sig='1' + // else derat_req_ttype when derat_req_taken_sig='1' -- re-purpose class as derat ttype, 0=load,1=store,2=epid load,3=epid store + // else tlb_tag0_q(`tagpos_class to `tagpos_class+1); + assign tlb_tag0_d[`tagpos_class:`tagpos_class + `CLASS_WIDTH - 1] = + ( ptereload_req_tag[`tagpos_class:`tagpos_class + `CLASS_WIDTH - 1] & {`CLASS_WIDTH{ptereload_req_taken_sig}} ) | + ( ex1_mmucr3_class & {`CLASS_WIDTH{write_req_taken_sig}} ) | + ( snoop_attr_q[2:3] & {`CLASS_WIDTH{snoop_req_taken_sig}} ) | + ( derat_req_ttype & {`CLASS_WIDTH{derat_req_taken_sig}} ) | + ( tlb_tag0_q[`tagpos_class:`tagpos_class + 1] & {`CLASS_WIDTH{(~any_req_taken_sig)}} ); + + // state: 0:pr 1:gs 2:as 3:cm + //tlb_tag0_d(`tagpos_state to `tagpos_state+`CTL_STATE_WIDTH-1) <= + // ptereload_req_tag(`tagpos_state to `tagpos_state+`CTL_STATE_WIDTH-1) when ptereload_req_taken_sig='1' + // else ex1_state_q when write_req_taken_sig='1' -- this has to be machine state passed to cmp exceptions, etc. + // else ex1_state_q when read_req_taken_sig='1' + // else ('0' & snoop_attr_q(4 to 5) & '0') when snoop_req_taken_sig='1' + // -- NOTE: may change ex2_mas5_1_state to ex2_mas8_1_state depending on architecture change + // else ex2_mas5_1_state when searchresv_req_taken_sig='1' -- mas5.sgs, mas1.ts + // else ex2_mas5_6_state when search_req_taken_sig='1' -- mas5.sgs, mas6.sas + // else ierat_req_state when ierat_req_taken_sig='1' + // else derat_req_state when derat_req_taken_sig='1' + assign tlb_tag0_d[`tagpos_state:`tagpos_state + `CTL_STATE_WIDTH - 1] = + ( ptereload_req_tag[`tagpos_state:`tagpos_state + `CTL_STATE_WIDTH - 1] & {`CTL_STATE_WIDTH{ptereload_req_taken_sig}} ) | + ( ex1_state_q[0:`CTL_STATE_WIDTH - 1] & {`CTL_STATE_WIDTH{write_req_taken_sig}} ) | + ( ex1_state_q[0:`CTL_STATE_WIDTH - 1] & {`CTL_STATE_WIDTH{read_req_taken_sig}} ) | + ( {1'b0, snoop_attr_q[4:5], 1'b0} & {`CTL_STATE_WIDTH{snoop_req_taken_sig}} ) | + ( ex2_mas5_1_state & {`CTL_STATE_WIDTH{searchresv_req_taken_sig}} ) | + ( ex2_mas5_6_state & {`CTL_STATE_WIDTH{search_req_taken_sig}} ) | + ( ierat_req_state & {`CTL_STATE_WIDTH{ierat_req_taken_sig}} ) | + ( derat_req_state & {`CTL_STATE_WIDTH{derat_req_taken_sig}} ) | + ( tlb_tag0_q[`tagpos_state:`tagpos_state + `CTL_STATE_WIDTH - 1] & {`CTL_STATE_WIDTH{(~any_req_taken_sig)}} ); + + //tlb_tag0_d(`tagpos_thdid to `tagpos_thdid+`THDID_WIDTH-1) <= + // ptereload_req_tag(`tagpos_thdid to `tagpos_thdid+`THDID_WIDTH-1) when ptereload_req_taken_sig='1' + // else ex1_valid_q when write_req_taken_sig='1' + // else ex1_valid_q when read_req_taken_sig='1' + // else 1111 when snoop_req_taken_sig='1' + // else ex2_valid_q when searchresv_req_taken_sig='1' + // else ex2_valid_q when search_req_taken_sig='1' + // else ierat_req_thdid when ierat_req_taken_sig='1' + // else derat_req_thdid when derat_req_taken_sig='1' + // else (others => '0') when (tlb_seq_ierat_done_sig='1' or tlb_seq_derat_done_sig='1' or + // tlb_seq_snoop_done_sig='1' or tlb_seq_search_done_sig='1' or + // tlb_seq_searchresv_done_sig ='1' or tlb_seq_read_done_sig ='1' or + // tlb_seq_write_done_sig ='1' or tlb_seq_ptereload_done_sig ='1' or tlb_seq_abort='1') + // + // else tlb_tag0_q(`tagpos_thdid to `tagpos_thdid+`THDID_WIDTH-1) and not(tlb_ctl_tag1_flush_sig) and + // not(tlb_ctl_tag2_flush_sig) and not(tlb_ctl_tag3_flush_sig) and not(tlb_ctl_tag4_flush_sig); + assign tlb_tag0_d[`tagpos_thdid : `tagpos_thdid + `MM_THREADS -1] = + ( ptereload_req_tag[`tagpos_thdid:`tagpos_thdid + `MM_THREADS -1] & {`MM_THREADS{ptereload_req_taken_sig}} ) | + ( ex1_valid_q & {`MM_THREADS{write_req_taken_sig}} ) | + ( ex1_valid_q & {`MM_THREADS{read_req_taken_sig}} ) | + ( {`MM_THREADS{snoop_req_taken_sig}} ) | + ( ex2_valid_q & {`MM_THREADS{searchresv_req_taken_sig}} ) | + ( ex2_valid_q & {`MM_THREADS{search_req_taken_sig}} ) | + ( ierat_req_thdid[0:`MM_THREADS-1] & {`MM_THREADS{ierat_req_taken_sig}} ) | + ( derat_req_thdid[0:`MM_THREADS-1] & {`MM_THREADS{derat_req_taken_sig}} ) | + ( tlb_tag0_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS-1] & (~(tlb_ctl_tag1_flush_sig)) & (~(tlb_ctl_tag2_flush_sig)) & (~(tlb_ctl_tag3_flush_sig)) & (~(tlb_ctl_tag4_flush_sig)) & + {`MM_THREADS{((~tlb_seq_any_done_sig) & (~any_req_taken_sig) & (~tlb_seq_abort))}} ); + + generate + if (`THDID_WIDTH > `MM_THREADS) + begin : tlbtag0NExist + assign tlb_tag0_d[`tagpos_thdid + `MM_THREADS : `tagpos_thdid + `THDID_WIDTH - 1] = + ( ptereload_req_tag[`tagpos_thdid + `MM_THREADS : `tagpos_thdid + `THDID_WIDTH - 1] & {`THDID_WIDTH - `MM_THREADS{ptereload_req_taken_sig}} ) | + ( {`THDID_WIDTH - `MM_THREADS{snoop_req_taken_sig}} ) | + ( ierat_req_thdid[`MM_THREADS:`THDID_WIDTH - 1] & {`THDID_WIDTH - `MM_THREADS{ierat_req_taken_sig}} ) | + ( derat_req_thdid[`MM_THREADS:`THDID_WIDTH - 1] & {`THDID_WIDTH - `MM_THREADS{derat_req_taken_sig}} ) | + ( tlb_tag0_q[`tagpos_thdid + `MM_THREADS:`tagpos_thdid + `THDID_WIDTH - 1] & {`THDID_WIDTH - `MM_THREADS{((~tlb_seq_any_done_sig) & (~any_req_taken_sig) & (~tlb_seq_abort))}} ); + end + endgenerate + + //tlb_tag0_d(`tagpos_size to `tagpos_size+3) <= + // --ptereload_req_tag(`tagpos_size to `tagpos_size+2) when ptereload_req_taken_sig='1' + // '0' & ptereload_req_pte(`ptepos_size to `ptepos_size+2) when ptereload_req_taken_sig='1' -- 0 | pte.size(0:2) + // else ex1_mas1_tsize when write_req_taken_sig='1' + // else ex1_mas1_tsize when read_req_taken_sig='1' + // else snoop_attr_q(14 to 17) when snoop_req_taken_sig='1' + // else mmucr2(28 to 31) when searchresv_req_taken_sig='1' + // else mmucr2(28 to 31) when search_req_taken_sig='1' + // else mmucr2(28 to 31) when ierat_req_taken_sig='1' + // else mmucr2(28 to 31) when derat_req_taken_sig='1' + // else tlb_tag0_q(`tagpos_size to `tagpos_size+3); + assign tlb_tag0_d[`tagpos_size:`tagpos_size + 3] = + ( ({1'b0, ptereload_req_pte[`ptepos_size:`ptepos_size + 2]}) & {4{ptereload_req_taken_sig}} ) | + ( ex1_mas1_tsize & {4{write_req_taken_sig}} ) | + ( ex1_mas1_tsize & {4{read_req_taken_sig}} ) | + ( snoop_attr_q[14:17] & {4{snoop_req_taken_sig}} ) | + ( mmucr2[28:31] & {4{searchresv_req_taken_sig}} ) | + ( mmucr2[28:31] & {4{search_req_taken_sig}} ) | + ( mmucr2[28:31] & {4{ierat_req_taken_sig}} ) | + ( mmucr2[28:31] & {4{derat_req_taken_sig}} ) | + ( tlb_tag0_q[`tagpos_size:`tagpos_size + 3] & {4{(~any_req_taken_sig)}} ); + + //tlb_tag0_d(`tagpos_lpid to `tagpos_lpid+`LPID_WIDTH-1) <= + // ptereload_req_tag(`tagpos_lpid to `tagpos_lpid+`LPID_WIDTH-1) when ptereload_req_taken_sig='1' + // else ex1_mas8_tlpid when write_req_taken_sig='1' + // else ex1_mas8_tlpid when read_req_taken_sig='1' + // else snoop_attr_q(26 to 33) when snoop_req_taken_sig='1' + // -- NOTE: may change ex2_mas5_slpid to ex2_mas8_tlpid depending on architecture change + // else ex2_mas5_slpid when searchresv_req_taken_sig='1' + // else ex2_mas5_slpid when search_req_taken_sig='1' + // else lpidr when ierat_req_taken_sig='1' + // else derat_req_lpid when derat_req_taken_sig='1' + // else tlb_tag0_q(`tagpos_lpid to `tagpos_lpid+`LPID_WIDTH-1); + assign tlb_tag0_d[`tagpos_lpid:`tagpos_lpid + `LPID_WIDTH - 1] = + ( ptereload_req_tag[`tagpos_lpid:`tagpos_lpid + `LPID_WIDTH - 1] & {`LPID_WIDTH{ptereload_req_taken_sig}} ) | + ( ex1_mas8_tlpid & {`LPID_WIDTH{write_req_taken_sig}} ) | + ( ex1_mas8_tlpid & {`LPID_WIDTH{read_req_taken_sig}} ) | + ( snoop_attr_q[26:33] & {`LPID_WIDTH{snoop_req_taken_sig}} ) | + ( ex2_mas5_slpid & {`LPID_WIDTH{searchresv_req_taken_sig}} ) | + ( ex2_mas5_slpid & {`LPID_WIDTH{search_req_taken_sig}} ) | + ( lpidr & {`LPID_WIDTH{ierat_req_taken_sig}} ) | + ( derat_req_lpid & {`LPID_WIDTH{derat_req_taken_sig}} ) | + ( tlb_tag0_q[`tagpos_lpid:`tagpos_lpid + `LPID_WIDTH - 1] & {`LPID_WIDTH{(~any_req_taken_sig)}} ); + + //tlb_tag0_d(`tagpos_ind) <= + // '0' when ptereload_req_taken_sig='1' -- prevents htw re-request, ptereload is always ind=0 entry + // --ptereload_req_tag(`tagpos_ind) when ptereload_req_taken_sig='1' + // else ex1_mas1_ind when write_req_taken_sig='1' + // else ex1_mas1_ind when read_req_taken_sig='1' + // else snoop_attr_q(34) when snoop_req_taken_sig='1' + // else ex2_mas1_ind when searchresv_req_taken_sig='1' + // else ex2_mas6_sind when search_req_taken_sig='1' + // else '0' when ierat_req_taken_sig='1' + // else '0' when derat_req_taken_sig='1' + // else tlb_tag0_q(`tagpos_ind); + assign tlb_tag0_d[`tagpos_ind] = + ( ex1_mas1_ind & write_req_taken_sig ) | + ( ex1_mas1_ind & read_req_taken_sig ) | + ( snoop_attr_q[34] & snoop_req_taken_sig ) | + ( ex2_mas1_ind & searchresv_req_taken_sig ) | + ( ex2_mas6_sind & search_req_taken_sig ) | + ( tlb_tag0_q[`tagpos_ind] & (~any_req_taken_sig) ); + + //tlb_tag0_d(`tagpos_atsel) <= + // ptereload_req_tag(`tagpos_atsel) when ptereload_req_taken_sig='1' + // else ex1_mas0_atsel when write_req_taken_sig='1' + // else ex1_mas0_atsel when read_req_taken_sig='1' + // else '0' when snoop_req_taken_sig='1' + // else ex2_mas0_atsel when searchresv_req_taken_sig='1' + // else ex2_mas0_atsel when search_req_taken_sig='1' + // else '0' when ierat_req_taken_sig='1' + // else '0' when derat_req_taken_sig='1' + // else tlb_tag0_q(`tagpos_atsel); + assign tlb_tag0_d[`tagpos_atsel] = + ( ptereload_req_tag[`tagpos_atsel] & ptereload_req_taken_sig ) | + ( ex1_mas0_atsel & write_req_taken_sig ) | + ( ex1_mas0_atsel & read_req_taken_sig ) | + ( ex2_mas0_atsel & searchresv_req_taken_sig ) | + ( ex2_mas0_atsel & search_req_taken_sig ) | + ( tlb_tag0_q[`tagpos_atsel] & (~any_req_taken_sig) ); + + //tlb_tag0_d(`tagpos_esel to `tagpos_esel+2) <= + // ptereload_req_tag(`tagpos_esel to `tagpos_esel+2) when ptereload_req_taken_sig='1' + // else ex1_mas0_esel when write_req_taken_sig='1' + // else ex1_mas0_esel when read_req_taken_sig='1' + // else 000 when snoop_req_taken_sig='1' + // else ex2_mas0_esel when searchresv_req_taken_sig='1' + // else ex2_mas0_esel when search_req_taken_sig='1' + // else 000 when ierat_req_taken_sig='1' + // else 000 when derat_req_taken_sig='1' + // else tlb_tag0_q(`tagpos_esel to `tagpos_esel+2); + assign tlb_tag0_d[`tagpos_esel:`tagpos_esel + 2] = + ( ptereload_req_tag[`tagpos_esel:`tagpos_esel + 2] & {3{ptereload_req_taken_sig}} ) | + ( ex1_mas0_esel & {3{write_req_taken_sig}} ) | + ( ex1_mas0_esel & {3{read_req_taken_sig}} ) | + ( ex2_mas0_esel & {3{searchresv_req_taken_sig}} ) | + ( ex2_mas0_esel & {3{search_req_taken_sig}} ) | + ( tlb_tag0_q[`tagpos_esel:`tagpos_esel + 2] & {3{(~any_req_taken_sig)}} ); + + //tlb_tag0_d(`tagpos_hes) <= + // ptereload_req_tag(`tagpos_hes) when ptereload_req_taken_sig='1' + // else ex1_mas0_hes when write_req_taken_sig='1' + // else ex1_mas0_hes when read_req_taken_sig='1' + // else snoop_attr_q(19) when snoop_req_taken_sig='1' -- hes = mmucsr0.tlb0fi invalidate all bit for snoops + // else ex2_mas0_hes when searchresv_req_taken_sig='1' + // else ex2_mas0_hes when search_req_taken_sig='1' + // else '1' when ierat_req_taken_sig='1' + // else '1' when derat_req_taken_sig='1' + // else tlb_tag0_q(`tagpos_hes); + assign tlb_tag0_d[`tagpos_hes] = + ( ptereload_req_tag[`tagpos_hes] & ptereload_req_taken_sig ) | + ( ex1_mas0_hes & write_req_taken_sig ) | + ( ex1_mas0_hes & read_req_taken_sig ) | + ( snoop_attr_q[19] & snoop_req_taken_sig ) | + ( ex2_mas0_hes & searchresv_req_taken_sig ) | + ( ex2_mas0_hes & search_req_taken_sig ) | + ( ierat_req_taken_sig) | (derat_req_taken_sig ) | + ( tlb_tag0_q[`tagpos_hes] & (~any_req_taken_sig) ); + + //tlb_tag0_d(`tagpos_wq to `tagpos_wq+1) <= + // -- unused WQ for ptereloads come back as htw reserv write enab & dup bits set in htw + // ptereload_req_tag(`tagpos_wq to `tagpos_wq+1) when ptereload_req_taken_sig='1' + // else ex1_mas0_wq when write_req_taken_sig='1' + // else ex1_mas0_wq when read_req_taken_sig='1' + // else 00 when snoop_req_taken_sig='1' + // else ex2_mas0_wq when searchresv_req_taken_sig='1' + // else ex2_mas0_wq when search_req_taken_sig='1' + // else ierat_req_dup when ierat_req_taken_sig='1' -- unused WQ is re-purposed as htw reservation write enab or dup bits + // else derat_req_dup when derat_req_taken_sig='1' -- unused WQ is re-purposed as htw reservation write enab or dup bits + // else tlb_tag0_q(`tagpos_wq to `tagpos_wq+1); + assign tlb_tag0_d[`tagpos_wq:`tagpos_wq + 1] = + ( ptereload_req_tag[`tagpos_wq:`tagpos_wq + 1] & {2{ptereload_req_taken_sig}} ) | + ( ex1_mas0_wq & {2{write_req_taken_sig}} ) | + ( ex1_mas0_wq & {2{read_req_taken_sig}} ) | + ( ex2_mas0_wq & {2{searchresv_req_taken_sig}} ) | + ( ex2_mas0_wq & {2{search_req_taken_sig}} ) | + ( ierat_req_dup & {2{ierat_req_taken_sig}} ) | + ( derat_req_dup & {2{derat_req_taken_sig}} ) | + ( tlb_tag0_q[`tagpos_wq:`tagpos_wq + 1] & {2{(~any_req_taken_sig)}} ); + + //tlb_tag0_d(`tagpos_lrat) <= + // ptereload_req_tag(`tagpos_lrat) when ptereload_req_taken_sig='1' + // else ex1_mmucfg_lrat when write_req_taken_sig='1' + // else ex1_mmucfg_lrat when read_req_taken_sig='1' + // else '0' when snoop_req_taken_sig='1' + // else ex2_mmucfg_lrat when searchresv_req_taken_sig='1' + // else ex2_mmucfg_lrat when search_req_taken_sig='1' + // else mmucfg_lrat when ierat_req_taken_sig='1' + // else mmucfg_lrat when derat_req_taken_sig='1' + // else tlb_tag0_q(`tagpos_lrat); + assign tlb_tag0_d[`tagpos_lrat] = + ( ptereload_req_tag[`tagpos_lrat] & ptereload_req_taken_sig ) | + ( mmucfg_lrat & write_req_taken_sig ) | + ( mmucfg_lrat & read_req_taken_sig ) | + ( mmucfg_lrat & searchresv_req_taken_sig ) | + ( mmucfg_lrat & search_req_taken_sig ) | + ( mmucfg_lrat & ierat_req_taken_sig ) | + ( mmucfg_lrat & derat_req_taken_sig ) | + ( tlb_tag0_q[`tagpos_lrat] & (~any_req_taken_sig) ); + + // unused `tagpos_pt def is mas8_tgs for tlbwe + assign tlb_tag0_d[`tagpos_pt] = + ( ptereload_req_tag[`tagpos_pt] & ptereload_req_taken_sig ) | + ( ex1_mas8_tgs & write_req_taken_sig ) | + ( tlb0cfg_pt & read_req_taken_sig ) | + ( tlb0cfg_pt & searchresv_req_taken_sig ) | + ( tlb0cfg_pt & search_req_taken_sig ) | + ( tlb0cfg_pt & ierat_req_taken_sig ) | + ( tlb0cfg_pt & derat_req_taken_sig ) | + ( tlb_tag0_q[`tagpos_pt] & (~any_req_taken_sig ) ); + + // unused `tagpos_recform def is mas1_ts for tlbwe + assign tlb_tag0_d[`tagpos_recform] = + ( ex1_mas1_ts & write_req_taken_sig ) | + ( searchresv_req_taken_sig ) | + ( ex2_ttype_q[3] & search_req_taken_sig ) | + ( tlb_tag0_q[`tagpos_recform] & (~any_req_taken_sig) ); + + assign tlb_tag0_d[`tagpos_endflag] = 1'b0; + + assign tlb_tag0_d[`tagpos_itag:`tagpos_itag + `ITAG_SIZE_ENC - 1] = + ( ptereload_req_tag[`tagpos_itag:`tagpos_itag + `ITAG_SIZE_ENC - 1] & {`ITAG_SIZE_ENC{ptereload_req_taken_sig}} ) | + ( ex1_itag_q & {`ITAG_SIZE_ENC{write_req_taken_sig}} ) | + ( ex1_itag_q & {`ITAG_SIZE_ENC{read_req_taken_sig}} ) | + ( ex2_itag_q & {`ITAG_SIZE_ENC{searchresv_req_taken_sig}} ) | + ( ex2_itag_q & {`ITAG_SIZE_ENC{search_req_taken_sig}} ) | + ( derat_req_itag & {`ITAG_SIZE_ENC{derat_req_taken_sig}} ) | + ( tlb_tag0_q[`tagpos_itag:`tagpos_itag + `ITAG_SIZE_ENC - 1] & {`ITAG_SIZE_ENC{(~any_req_taken_sig)}} ); + + assign tlb_tag0_d[`tagpos_emq:`tagpos_emq + `EMQ_ENTRIES - 1] = + ( ptereload_req_tag[`tagpos_emq:`tagpos_emq + `EMQ_ENTRIES - 1] & {`EMQ_ENTRIES{ptereload_req_taken_sig}} ) | + ( derat_req_emq & {`EMQ_ENTRIES{derat_req_taken_sig}} ) | + (tlb_tag0_q[`tagpos_emq:`tagpos_emq + `EMQ_ENTRIES - 1] & {`EMQ_ENTRIES{(~any_req_taken_sig)}} ); + + assign tlb_tag0_d[`tagpos_nonspec] = + ( ptereload_req_tag[`tagpos_nonspec] & ptereload_req_taken_sig ) | + ( write_req_taken_sig ) | + ( read_req_taken_sig ) | + ( searchresv_req_taken_sig ) | + ( search_req_taken_sig ) | + ( ierat_req_nonspec & ierat_req_taken_sig ) | + ( derat_req_nonspec & derat_req_taken_sig ) | + ( tlb_tag0_q[`tagpos_nonspec] & (~any_req_taken_sig) ); + + // `tagpos_epn : natural := 0; + // `tagpos_pid : natural := 52; -- 14 bits + // `tagpos_is : natural := 66; + // `tagpos_class : natural := 68; + // `tagpos_state : natural := 70; -- state: 0:pr 1:gs 2:as 3:cm + // `tagpos_thdid : natural := 74; + // `tagpos_size : natural := 78; + // `tagpos_type : natural := 82; -- derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload + // `tagpos_lpid : natural := 90; + // `tagpos_ind : natural := 98; + // `tagpos_atsel : natural := 99; + // `tagpos_esel : natural := 100; + // `tagpos_hes : natural := 103; + // `tagpos_wq : natural := 104; + // `tagpos_lrat : natural := 106; + // `tagpos_pt : natural := 107; + // `tagpos_recform : natural := 108; + // `tagpos_endflag : natural := 109; + //ac/q7/vhdl/a2_simwrap_32.vhdl: constant `REAL_ADDR_WIDTH : integer := 32; + //ac/q7/vhdl/a2_simwrap.vhdl: constant `REAL_ADDR_WIDTH : integer := 42; + //ac/q7/vhdl/a2_simwrap_32.vhdl: constant `EPN_WIDTH : integer := 20; + //ac/q7/vhdl/a2_simwrap.vhdl: constant `EPN_WIDTH : integer := 52; + // tag0 phase, tlbwe/re ex2, tlbsx/srx ex3 + + assign tlb_tag0_epn[52 - `EPN_WIDTH:51] = tlb_tag0_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 1]; + + assign tlb_tag0_thdid = tlb_tag0_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]; + + assign tlb_tag0_type = tlb_tag0_q[`tagpos_type:`tagpos_type + 7]; + + assign tlb_tag0_lpid = tlb_tag0_q[`tagpos_lpid:`tagpos_lpid + `LPID_WIDTH - 1]; + + assign tlb_tag0_atsel = tlb_tag0_q[`tagpos_atsel]; + + assign tlb_tag0_size = tlb_tag0_q[`tagpos_size:`tagpos_size + 3]; + + assign tlb_tag0_addr_cap = tlb_seq_tag0_addr_cap; + + assign tlb_tag0_nonspec = tlb_tag0_q[`tagpos_nonspec]; + + assign tlb_tag1_d[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 1] = tlb_tag0_q[`tagpos_epn:`tagpos_epn + `EPN_WIDTH - 1]; + + assign tlb_tag1_d[`tagpos_pid:`tagpos_pid + `PID_WIDTH - 1] = tlb_tag0_q[`tagpos_pid:`tagpos_pid + `PID_WIDTH - 1]; + + // maybe needed for timing here and for ptereload_req_pte(`ptepos_size) stuff + // unused `tagpos_is def is (pte.valid & 0) for ptereloads + //tlb_tag1_d(`tagpos_is to `tagpos_is+1) <= ptereload_req_pte_q(`ptepos_valid) & tlb_tag0_q(`tagpos_is+1) + // when (tlb_seq_tag0_addr_cap='1' and tlb_tag0_q(`tagpos_type_ptereload)='1') + // else tlb_tag0_q(`tagpos_is to `tagpos_is+1); + // tlb_tag1_d(`tagpos_is to `tagpos_is+1) <= tlb_tag0_q(`tagpos_is to `tagpos_is+1); + // unused isel for derat,ierat,tlbsx,tlbsrx becomes page size attempted number msb (9 thru 13, or 17 thru 21) + assign tlb_tag1_d[`tagpos_is:`tagpos_is + 1] = + ( {2{|(tlb_tag0_q[`tagpos_type_derat:`tagpos_type_tlbsrx])}} & {2{(~tlb_tag0_q[`tagpos_type_ptereload])}} & tlb_seq_is) | + ( {2{|(tlb_tag0_q[`tagpos_type_snoop:`tagpos_type_ptereload])}} & tlb_tag0_q[`tagpos_is:`tagpos_is + 1] ); + + assign tlb_tag1_d[`tagpos_class:`tagpos_class + `CLASS_WIDTH - 1] = tlb_tag0_q[`tagpos_class:`tagpos_class + `CLASS_WIDTH - 1]; + + assign tlb_tag1_d[`tagpos_state:`tagpos_state + `CTL_STATE_WIDTH - 1] = tlb_tag0_q[`tagpos_state:`tagpos_state + `CTL_STATE_WIDTH - 1]; + + assign tlb_tag1_d[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] = + ( ((tlb_tag4_hit_or_parerr == 1'b1 | tlb_tag4_endflag == 1'b1) & tlb_tag0_q[`tagpos_type_ptereload] == 1'b0 & + (tlb_tag0_q[`tagpos_type_ierat] == 1'b1 | tlb_tag0_q[`tagpos_type_derat] == 1'b1 | tlb_tag0_q[`tagpos_type_tlbsx] == 1'b1 | tlb_tag0_q[`tagpos_type_tlbsrx] == 1'b1)) | + (tlb_tag4_endflag == 1'b1 & tlb_tag0_q[`tagpos_type_snoop] == 1'b1) | + tlb_seq_any_done_sig == 1'b1 | tlb_seq_abort == 1'b1 ) ? {`MM_THREADS{1'b0}} : + {tlb_tag0_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] & (~(tlb_ctl_tag1_flush_sig)) & (~(tlb_ctl_tag2_flush_sig)) & (~(tlb_ctl_tag3_flush_sig)) & (~(tlb_ctl_tag4_flush_sig))}; + generate + if (`THDID_WIDTH > `MM_THREADS) + begin : tlbtag1NExist + assign tlb_tag1_d[`tagpos_thdid + `MM_THREADS:`tagpos_thdid + `THDID_WIDTH - 1] = + ( ((tlb_tag4_hit_or_parerr == 1'b1 | tlb_tag4_endflag == 1'b1) & tlb_tag0_q[`tagpos_type_ptereload] == 1'b0 & + (tlb_tag0_q[`tagpos_type_ierat] == 1'b1 | tlb_tag0_q[`tagpos_type_derat] == 1'b1 | tlb_tag0_q[`tagpos_type_tlbsx] == 1'b1 | tlb_tag0_q[`tagpos_type_tlbsrx] == 1'b1)) | + (tlb_tag4_endflag == 1'b1 & tlb_tag0_q[`tagpos_type_snoop] == 1'b1) | + tlb_seq_any_done_sig == 1'b1 | tlb_seq_abort == 1'b1) ? {`THDID_WIDTH - `MM_THREADS{1'b0}} : + {tlb_tag0_q[`tagpos_thdid + `MM_THREADS:`tagpos_thdid + `THDID_WIDTH - 1]}; + end + endgenerate + + //tlb_tag1_d(`tagpos_ind) <= '1' when tlb_seq_ind='1' else tlb_tag0_q(`tagpos_ind); + //tlb_tag1_d(`tagpos_esel to `tagpos_esel+2) <= tlb_tag0_q(`tagpos_esel to `tagpos_esel+2); + assign tlb_tag1_d[`tagpos_ind] = ( |(tlb_tag0_q[`tagpos_type_derat:`tagpos_type_ierat]) & tlb_seq_ind ) | + ( (~|(tlb_tag0_q[`tagpos_type_derat:`tagpos_type_ierat])) & tlb_tag0_q[`tagpos_ind] ); + + // unused esel for derat,ierat,tlbsx,tlbsrx becomes page size attempted number (1 thru 5) + assign tlb_tag1_d[`tagpos_esel:`tagpos_esel + 2] = ( {3{|(tlb_tag0_q[`tagpos_type_derat:`tagpos_type_tlbsrx]) & (~tlb_tag0_q[`tagpos_type_ptereload])}} & tlb_seq_esel ) | + ( {3{tlb_tag0_q[`tagpos_type_ptereload] | (~|(tlb_tag0_q[`tagpos_type_derat:`tagpos_type_tlbsrx]))}} & tlb_tag0_q[`tagpos_esel:`tagpos_esel + 2]); + + assign tlb_tag1_d[`tagpos_lpid:`tagpos_lpid + `LPID_WIDTH - 1] = tlb_tag0_q[`tagpos_lpid:`tagpos_lpid + `LPID_WIDTH - 1]; + + assign tlb_tag1_d[`tagpos_atsel] = tlb_tag0_q[`tagpos_atsel]; + + assign tlb_tag1_d[`tagpos_hes] = tlb_tag0_q[`tagpos_hes]; + + assign tlb_tag1_d[`tagpos_wq:`tagpos_wq + 1] = tlb_tag0_q[`tagpos_wq:`tagpos_wq + 1]; + + assign tlb_tag1_d[`tagpos_lrat] = tlb_tag0_q[`tagpos_lrat]; + + assign tlb_tag1_d[`tagpos_pt] = tlb_tag0_q[`tagpos_pt]; + + assign tlb_tag1_d[`tagpos_recform] = tlb_tag0_q[`tagpos_recform]; + + // pgsize bits + assign tlb_tag1_d[`tagpos_size:`tagpos_size + 3] = + ( {4{|(tlb_tag0_q[`tagpos_type_derat:`tagpos_type_tlbsrx]) & (~tlb_tag0_q[`tagpos_type_ptereload])}} & tlb_seq_pgsize ) | + ( {4{tlb_tag0_q[`tagpos_type_ptereload] | (~|(tlb_tag0_q[`tagpos_type_derat:`tagpos_type_tlbsrx]))}} & tlb_tag0_q[`tagpos_size:`tagpos_size + 3] ); + + // tag type bits: derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload + assign tlb_tag1_d[`tagpos_type:`tagpos_type + 7] = + ( (tlb_seq_ierat_done_sig == 1'b1 | tlb_seq_derat_done_sig == 1'b1 | tlb_seq_snoop_done_sig == 1'b1 | + tlb_seq_search_done_sig == 1'b1 | tlb_seq_searchresv_done_sig == 1'b1 | tlb_seq_read_done_sig == 1'b1 | tlb_seq_write_done_sig == 1'b1 | + tlb_seq_ptereload_done_sig == 1'b1 | tlb_seq_abort == 1'b1) ) ? 8'b00000000 : + tlb_tag0_q[`tagpos_type:`tagpos_type + 7]; + + // endflag + assign tlb_tag1_d[`tagpos_endflag] = tlb_seq_endflag; + + assign tlb_addr_d = (|(tlb_tag4_parerr_write) == 1'b1) ? tlb_addr4 : + (tlb_seq_addr_clr == 1'b1) ? {`TLB_ADDR_WIDTH{1'b0}} : + (tlb_seq_addr_incr == 1'b1) ? tlb_addr_p1 : + (tlb_seq_addr_update == 1'b1) ? tlb_seq_addr : + tlb_addr_q; + + assign tlb_addr_p1 = (tlb_addr_q == 7'b1111111) ? 7'b0000000 : + tlb_addr_q + 7'b0000001; + + assign tlb_addr_maxcntm1 = (tlb_addr_q == 7'b1111110) ? 1'b1 : + 1'b0; + + // tag1 phase, tlbwe/re ex3, tlbsx/srx ex4 + //tlb_tag2_d <= tlb_tag1_q; + //tlb_tag2_d(`tagpos_epn to `tagpos_epn+`EPN_WIDTH-1) <= tlb_tag1_q(`tagpos_epn to `tagpos_epn+`EPN_WIDTH-1); + assign tlb_tag1_pgsize_eq_16mb = (tlb_tag1_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_16MB); + assign tlb_tag1_pgsize_gte_1mb = (tlb_tag1_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_1MB) | (tlb_tag1_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_16MB); + assign tlb_tag1_pgsize_gte_64kb = (tlb_tag1_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_1MB) | (tlb_tag1_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_16MB) | (tlb_tag1_q[`tagpos_size:`tagpos_size + 3] == TLB_PgSize_64KB); + assign tlb_tag1_d[`tagpos_itag:`tagpos_itag + `ITAG_SIZE_ENC - 1] = tlb_tag0_q[`tagpos_itag:`tagpos_itag + `ITAG_SIZE_ENC - 1]; + assign tlb_tag1_d[`tagpos_emq:`tagpos_emq + `EMQ_ENTRIES - 1] = tlb_tag0_q[`tagpos_emq:`tagpos_emq + `EMQ_ENTRIES - 1]; + assign tlb_tag1_d[`tagpos_nonspec] = tlb_tag0_q[`tagpos_nonspec]; + + assign tlb_tag2_d[`tagpos_epn:`tagpos_epn + 39] = tlb_tag1_q[`tagpos_epn:`tagpos_epn + 39]; + assign tlb_tag2_d[`tagpos_epn + 40:`tagpos_epn + 43] = tlb_tag1_q[`tagpos_epn + 40:`tagpos_epn + 43] & {4{((~tlb_tag1_pgsize_eq_16mb) | (~tlb_tag1_q[`tagpos_type_ptereload]))}}; + assign tlb_tag2_d[`tagpos_epn + 44:`tagpos_epn + 47] = tlb_tag1_q[`tagpos_epn + 44:`tagpos_epn + 47] & {4{((~tlb_tag1_pgsize_gte_1mb) | (~tlb_tag1_q[`tagpos_type_ptereload]))}}; + assign tlb_tag2_d[`tagpos_epn + 48:`tagpos_epn + 51] = tlb_tag1_q[`tagpos_epn + 48:`tagpos_epn + 51] & {4{((~tlb_tag1_pgsize_gte_64kb) | (~tlb_tag1_q[`tagpos_type_ptereload]))}}; + + assign tlb_tag2_d[`tagpos_pid:`tagpos_pid + `PID_WIDTH - 1] = tlb_tag1_q[`tagpos_pid:`tagpos_pid + `PID_WIDTH - 1]; + assign tlb_tag2_d[`tagpos_is:`tagpos_is + 1] = tlb_tag1_q[`tagpos_is:`tagpos_is + 1]; + assign tlb_tag2_d[`tagpos_class:`tagpos_class + 1] = tlb_tag1_q[`tagpos_class:`tagpos_class + 1]; + assign tlb_tag2_d[`tagpos_state:`tagpos_state + `CTL_STATE_WIDTH - 1] = tlb_tag1_q[`tagpos_state:`tagpos_state + `CTL_STATE_WIDTH - 1]; + + assign tlb_tag2_d[`tagpos_thdid:`tagpos_thdid + `MM_THREADS -1] = (((tlb_tag4_hit_or_parerr == 1'b1 | tlb_tag4_endflag == 1'b1) & tlb_tag1_q[`tagpos_type_ptereload] == 1'b0 & + (tlb_tag1_q[`tagpos_type_ierat] == 1'b1 | tlb_tag1_q[`tagpos_type_derat] == 1'b1 | + tlb_tag1_q[`tagpos_type_tlbsx] == 1'b1 | tlb_tag1_q[`tagpos_type_tlbsrx] == 1'b1)) | + (tlb_tag4_endflag == 1'b1 & tlb_tag1_q[`tagpos_type_snoop] == 1'b1) | + tlb_seq_any_done_sig == 1'b1 | tlb_seq_abort == 1'b1) ? {`MM_THREADS{1'b0}} : + tlb_tag1_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS - 1] & (~(tlb_ctl_tag2_flush_sig)) & (~(tlb_ctl_tag3_flush_sig)) & (~(tlb_ctl_tag4_flush_sig)); + generate + if (`THDID_WIDTH > `MM_THREADS) + begin : tlbtag2NExist + assign tlb_tag2_d[`tagpos_thdid + `MM_THREADS:`tagpos_thdid + `THDID_WIDTH - 1] = (((tlb_tag4_hit_or_parerr == 1'b1 | tlb_tag4_endflag == 1'b1) & tlb_tag1_q[`tagpos_type_ptereload] == 1'b0 & + (tlb_tag1_q[`tagpos_type_ierat] == 1'b1 | tlb_tag1_q[`tagpos_type_derat] == 1'b1 | + tlb_tag1_q[`tagpos_type_tlbsx] == 1'b1 | tlb_tag1_q[`tagpos_type_tlbsrx] == 1'b1)) | + (tlb_tag4_endflag == 1'b1 & tlb_tag1_q[`tagpos_type_snoop] == 1'b1) | + tlb_seq_any_done_sig == 1'b1 | tlb_seq_abort == 1'b1) ? {`THDID_WIDTH - `MM_THREADS{1'b0}} : + tlb_tag1_q[`tagpos_thdid + `MM_THREADS:`tagpos_thdid + `THDID_WIDTH - 1]; + end + endgenerate + + assign tlb_tag2_d[`tagpos_size:`tagpos_size + 3] = tlb_tag1_q[`tagpos_size:`tagpos_size + 3]; + assign tlb_tag2_d[`tagpos_type:`tagpos_type + 7] = ((tlb_seq_ierat_done_sig == 1'b1 | tlb_seq_derat_done_sig == 1'b1 | tlb_seq_snoop_done_sig == 1'b1 | tlb_seq_search_done_sig == 1'b1 | tlb_seq_searchresv_done_sig == 1'b1 | tlb_seq_read_done_sig == 1'b1 | tlb_seq_write_done_sig == 1'b1 | tlb_seq_ptereload_done_sig == 1'b1 | tlb_seq_abort == 1'b1)) ? 8'b00000000 : + tlb_tag1_q[`tagpos_type:`tagpos_type + 7]; + assign tlb_tag2_d[`tagpos_lpid:`tagpos_lpid + `LPID_WIDTH - 1] = tlb_tag1_q[`tagpos_lpid:`tagpos_lpid + `LPID_WIDTH - 1]; + assign tlb_tag2_d[`tagpos_ind] = tlb_tag1_q[`tagpos_ind]; + assign tlb_tag2_d[`tagpos_atsel] = tlb_tag1_q[`tagpos_atsel]; + assign tlb_tag2_d[`tagpos_esel:`tagpos_esel + 2] = tlb_tag1_q[`tagpos_esel:`tagpos_esel + 2]; + assign tlb_tag2_d[`tagpos_hes] = tlb_tag1_q[`tagpos_hes]; + assign tlb_tag2_d[`tagpos_wq:`tagpos_wq + 1] = tlb_tag1_q[`tagpos_wq:`tagpos_wq + 1]; + assign tlb_tag2_d[`tagpos_lrat] = tlb_tag1_q[`tagpos_lrat]; + assign tlb_tag2_d[`tagpos_pt] = tlb_tag1_q[`tagpos_pt]; + assign tlb_tag2_d[`tagpos_recform] = tlb_tag1_q[`tagpos_recform]; + assign tlb_tag2_d[`tagpos_endflag] = tlb_tag1_q[`tagpos_endflag]; + assign tlb_tag2_d[`tagpos_itag:`tagpos_itag + `ITAG_SIZE_ENC - 1] = tlb_tag1_q[`tagpos_itag:`tagpos_itag + `ITAG_SIZE_ENC - 1]; + assign tlb_tag2_d[`tagpos_emq:`tagpos_emq + `EMQ_ENTRIES - 1] = tlb_tag1_q[`tagpos_emq:`tagpos_emq + `EMQ_ENTRIES - 1]; + assign tlb_tag2_d[`tagpos_nonspec] = tlb_tag1_q[`tagpos_nonspec]; + assign lru_rd_addr = tlb_addr_q; + assign tlb_addr = tlb_addr_q; + assign tlb_addr2_d = tlb_addr_q; + // tag2 phase, tlbwe/re ex4, tlbsx/srx ex5 + assign tlb_tag2 = tlb_tag2_q; + assign tlb_addr2 = tlb_addr2_q; + // tag4, tlbwe/re ex6 + + assign tlb_write_d[0] = ((|(ex6_valid_q) == 1'b1 & ex6_ttype_q[1] == 1'b1 & ex6_state_q[0] == 1'b0 & ex6_illeg_instr_q[1] == 1'b0 & ((ex6_state_q[1] == 1'b0 & tlb_tag4_atsel == 1'b0) | (ex6_state_q[1] == 1'b1 & lrat_tag4_hit_status[0:3] == 4'b1100 & (lru_tag4_dataout[0] == 1'b0 | lru_tag4_dataout[8] == 1'b0) & tlb_tag4_is[1] == 1'b0 & tlb0cfg_gtwe == 1'b1 & ex6_dgtmi_state == 1'b0)) & ((|(ex6_valid_q & tlb_resv_match_vec_q) == 1'b1 & tlb_tag4_wq == 2'b01 & mmucfg_twc == 1'b1) | tlb_tag4_wq == 2'b00 | tlb_tag4_wq == 2'b11) & tlb_tag4_hes == 1'b1 & lru_tag4_dataout[4] == 1'b0 & lru_tag4_dataout[5] == 1'b0)) ? 1'b1 : + ((|(ex6_valid_q) == 1'b1 & ex6_ttype_q[1] == 1'b1 & ex6_state_q[0] == 1'b0 & ex6_illeg_instr_q[1] == 1'b0 & ex6_state_q[1] == 1'b0 & tlb_tag4_atsel == 1'b0 & ((|(ex6_valid_q & tlb_resv_match_vec_q) == 1'b1 & tlb_tag4_wq == 2'b01 & mmucfg_twc == 1'b1) | tlb_tag4_wq == 2'b00 | tlb_tag4_wq == 2'b11) & tlb_tag4_hes == 1'b0 & tlb_tag4_esel[1:2] == 2'b00)) ? 1'b1 : + ((tlb_tag4_ptereload == 1'b1 & (tlb_tag4_gs == 1'b0 | (tlb_tag4_gs == 1'b1 & lrat_tag4_hit_status[0:3] == 4'b1100)) & lru_tag4_dataout[4] == 1'b0 & lru_tag4_dataout[5] == 1'b0 & (lru_tag4_dataout[0] == 1'b0 | lru_tag4_dataout[8] == 1'b0) & tlb_tag4_wq == 2'b10 & tlb_tag4_is[0] == 1'b1 & tlb_tag4_pt == 1'b1)) ? 1'b1 : + tlb_tag4_parerr_write[0]; + + assign tlb_write_d[1] = ((|(ex6_valid_q) == 1'b1 & ex6_ttype_q[1] == 1'b1 & ex6_state_q[0] == 1'b0 & ex6_illeg_instr_q[1] == 1'b0 & ((ex6_state_q[1] == 1'b0 & tlb_tag4_atsel == 1'b0) | (ex6_state_q[1] == 1'b1 & lrat_tag4_hit_status[0:3] == 4'b1100 & (lru_tag4_dataout[1] == 1'b0 | lru_tag4_dataout[9] == 1'b0) & tlb_tag4_is[1] == 1'b0 & tlb0cfg_gtwe == 1'b1 & ex6_dgtmi_state == 1'b0)) & ((|(ex6_valid_q & tlb_resv_match_vec_q) == 1'b1 & tlb_tag4_wq == 2'b01 & mmucfg_twc == 1'b1) | tlb_tag4_wq == 2'b00 | tlb_tag4_wq == 2'b11) & tlb_tag4_hes == 1'b1 & lru_tag4_dataout[4] == 1'b0 & lru_tag4_dataout[5] == 1'b1)) ? 1'b1 : + ((|(ex6_valid_q) == 1'b1 & ex6_ttype_q[1] == 1'b1 & ex6_state_q[0] == 1'b0 & ex6_illeg_instr_q[1] == 1'b0 & ex6_state_q[1] == 1'b0 & tlb_tag4_atsel == 1'b0 & ((|(ex6_valid_q & tlb_resv_match_vec_q) == 1'b1 & tlb_tag4_wq == 2'b01 & mmucfg_twc == 1'b1) | tlb_tag4_wq == 2'b00 | tlb_tag4_wq == 2'b11) & tlb_tag4_hes == 1'b0 & tlb_tag4_esel[1:2] == 2'b01)) ? 1'b1 : + ((tlb_tag4_ptereload == 1'b1 & (tlb_tag4_gs == 1'b0 | (tlb_tag4_gs == 1'b1 & lrat_tag4_hit_status[0:3] == 4'b1100)) & lru_tag4_dataout[4:5] == 2'b01 & (lru_tag4_dataout[1] == 1'b0 | lru_tag4_dataout[9] == 1'b0) & tlb_tag4_wq == 2'b10 & tlb_tag4_is[0] == 1'b1 & tlb_tag4_pt == 1'b1)) ? 1'b1 : + tlb_tag4_parerr_write[1]; + + assign tlb_write_d[2] = ((|(ex6_valid_q) == 1'b1 & ex6_ttype_q[1] == 1'b1 & ex6_state_q[0] == 1'b0 & ex6_illeg_instr_q[1] == 1'b0 & ((ex6_state_q[1] == 1'b0 & tlb_tag4_atsel == 1'b0) | (ex6_state_q[1] == 1'b1 & lrat_tag4_hit_status[0:3] == 4'b1100 & (lru_tag4_dataout[2] == 1'b0 | lru_tag4_dataout[10] == 1'b0) & tlb_tag4_is[1] == 1'b0 & tlb0cfg_gtwe == 1'b1 & ex6_dgtmi_state == 1'b0)) & ((|(ex6_valid_q & tlb_resv_match_vec_q) == 1'b1 & tlb_tag4_wq == 2'b01 & mmucfg_twc == 1'b1) | tlb_tag4_wq == 2'b00 | tlb_tag4_wq == 2'b11) & tlb_tag4_hes == 1'b1 & lru_tag4_dataout[4] == 1'b1 & lru_tag4_dataout[6] == 1'b0)) ? 1'b1 : + ((|(ex6_valid_q) == 1'b1 & ex6_ttype_q[1] == 1'b1 & ex6_state_q[0] == 1'b0 & ex6_illeg_instr_q[1] == 1'b0 & ex6_state_q[1] == 1'b0 & tlb_tag4_atsel == 1'b0 & ((|(ex6_valid_q & tlb_resv_match_vec_q) == 1'b1 & tlb_tag4_wq == 2'b01 & mmucfg_twc == 1'b1) | tlb_tag4_wq == 2'b00 | tlb_tag4_wq == 2'b11) & tlb_tag4_hes == 1'b0 & tlb_tag4_esel[1:2] == 2'b10)) ? 1'b1 : + ((tlb_tag4_ptereload == 1'b1 & (tlb_tag4_gs == 1'b0 | (tlb_tag4_gs == 1'b1 & lrat_tag4_hit_status[0:3] == 4'b1100)) & lru_tag4_dataout[4] == 1'b1 & lru_tag4_dataout[6] == 1'b0 & (lru_tag4_dataout[2] == 1'b0 | lru_tag4_dataout[10] == 1'b0) & tlb_tag4_wq == 2'b10 & tlb_tag4_is[0] == 1'b1 & tlb_tag4_pt == 1'b1)) ? 1'b1 : + tlb_tag4_parerr_write[2]; + + assign tlb_write_d[3] = ((|(ex6_valid_q) == 1'b1 & ex6_ttype_q[1] == 1'b1 & ex6_state_q[0] == 1'b0 & ex6_illeg_instr_q[1] == 1'b0 & ((ex6_state_q[1] == 1'b0 & tlb_tag4_atsel == 1'b0) | (ex6_state_q[1] == 1'b1 & lrat_tag4_hit_status[0:3] == 4'b1100 & (lru_tag4_dataout[3] == 1'b0 | lru_tag4_dataout[11] == 1'b0) & tlb_tag4_is[1] == 1'b0 & tlb0cfg_gtwe == 1'b1 & ex6_dgtmi_state == 1'b0)) & ((|(ex6_valid_q & tlb_resv_match_vec_q) == 1'b1 & tlb_tag4_wq == 2'b01 & mmucfg_twc == 1'b1) | tlb_tag4_wq == 2'b00 | tlb_tag4_wq == 2'b11) & tlb_tag4_hes == 1'b1 & lru_tag4_dataout[4] == 1'b1 & lru_tag4_dataout[6] == 1'b1)) ? 1'b1 : + ((|(ex6_valid_q) == 1'b1 & ex6_ttype_q[1] == 1'b1 & ex6_state_q[0] == 1'b0 & ex6_illeg_instr_q[1] == 1'b0 & ex6_state_q[1] == 1'b0 & tlb_tag4_atsel == 1'b0 & ((|(ex6_valid_q & tlb_resv_match_vec_q) == 1'b1 & tlb_tag4_wq == 2'b01 & mmucfg_twc == 1'b1) | tlb_tag4_wq == 2'b00 | tlb_tag4_wq == 2'b11) & tlb_tag4_hes == 1'b0 & tlb_tag4_esel[1:2] == 2'b11)) ? 1'b1 : + ((tlb_tag4_ptereload == 1'b1 & (tlb_tag4_gs == 1'b0 | (tlb_tag4_gs == 1'b1 & lrat_tag4_hit_status[0:3] == 4'b1100)) & lru_tag4_dataout[4] == 1'b1 & lru_tag4_dataout[6] == 1'b1 & (lru_tag4_dataout[3] == 1'b0 | lru_tag4_dataout[11] == 1'b0) & tlb_tag4_wq == 2'b10 & tlb_tag4_is[0] == 1'b1 & tlb_tag4_pt == 1'b1)) ? 1'b1 : + tlb_tag4_parerr_write[3]; + + + // tag5 (ex7) phase signals + // tlb_write <= tlb_write_q; -- tag5, or ex7 + assign tlb_write = tlb_write_q & {`TLB_WAYS{tlb_tag5_parerr_zeroize | (~|(tlb_tag5_except))}}; + + assign tlb_tag5_write = |(tlb_write_q) & (~|(tlb_tag5_except)); + + //--------- this is what the erat expects on reload bus + // 0:51 - EPN + // 52 - X + // 53:55 - SIZE + // 56 - V + // 57:60 - ThdID + // 61:62 - Class + // 63 - ExtClass + // 64 - TID_NZ + // 65 - reserved + // 0:33 66:99 - RPN + // 34:35 100:101 - R,C + // 36:40 102:106 - ResvAttr + // 41:44 107:110 - U0-U3 + // 45:49 111:115 - WIMGE + // 50:52 116:118 - UX,UW,UR + // 53:55 119:121 - SX,SW,SR + // 56 122 - HS + // 57 123 - TS + // 58:65 124:131 - TID + //--------- + // tlb_low_data + // 0:51 - EPN + // 52:55 - SIZE (4b) + // 56:59 - ThdID + // 60:61 - Class + // 62 - ExtClass + // 63 - TID_NZ + // 64:65 - reserved (2b) + // 66:73 - 8b for LPID + // 74:83 - parity 10bits + // tlb_high_data + // 84 - 0 - X-bit + // 85:87 - 1:3 - reserved (3b) + // 88:117 - 4:33 - RPN (30b) + // 118:119 - 34:35 - R,C + // 120:121 - 36:37 - WLC (2b) + // 122 - 38 - ResvAttr + // 123 - 39 - VF + // 124 - 40 - IND + // 125:128 - 41:44 - U0-U3 + // 129:133 - 45:49 - WIMGE + // 134:136 - 50:52 - UX,UW,UR + // 137:139 - 53:55 - SX,SW,SR + // 140 - 56 - GS + // 141 - 57 - TS + // 142:143 - 58:59 - reserved (2b) + // 144:149 - 60:65 - 6b TID msbs + // 150:157 - 66:73 - 8b TID lsbs + // 158:167 - 74:83 - parity 10bits + // lru data format + // 0:3 - valid(0:3) + // 4:6 - LRU + // 7 - parity + // 8:11 - iprot(0:3) + // 12:14 - reserved + // 15 - parity + // wr_ws0_data (LO) + // 0:51 - EPN + // 52:53 - Class + // 54 - V + // 55 - unused + // 56 - X + // 57:59 - SIZE + // 60:63 - ThdID + // wr_ws1_data (HI) + // 0:6 - unused + // 7:11 - ResvAttr + // 12:15 - U0-U3 + // 16:17 - R,C + // 18:51 - RPN + // 52:56 - WIMGE + // 57 - unused + // 58:59 - UX,SX + // 60:61 - UW,SW + // 62:63 - UR,SR + assign ex3_valid_32b = |(ex3_valid_q & (~(xu_mm_msr_cm))); + assign tlb_ctl_ex2_flush_req = ((ex2_ttype_q[2:4] != 3'b000 & search_req_taken_sig == 1'b0 & searchresv_req_taken_sig == 1'b0)) ? (ex2_valid_q & (~(xu_ex2_flush))) : + ((|(ex2_flush_req_q) == 1'b1)) ? (ex2_valid_q & (~(xu_ex2_flush))) : + {`MM_THREADS{1'b0}}; + assign tlb_ctl_ex2_itag = ex2_itag_q; + + // illegal instruction terms + // state: 0:pr 1:gs 2:as 3:cm + assign mas1_tsize_direct[0] = ((mas1_0_tsize == TLB_PgSize_4KB) | (mas1_0_tsize == TLB_PgSize_64KB) | (mas1_0_tsize == TLB_PgSize_1MB) | + (mas1_0_tsize == TLB_PgSize_16MB) | (mas1_0_tsize == TLB_PgSize_1GB)); + + assign mas1_tsize_indirect[0] = ((mas1_0_tsize == TLB_PgSize_1MB) | (mas1_0_tsize == TLB_PgSize_256MB)); + + assign mas1_tsize_lrat[0] = ((mas1_0_tsize == LRAT_PgSize_1MB) | (mas1_0_tsize == LRAT_PgSize_16MB) | (mas1_0_tsize == LRAT_PgSize_256MB) | + (mas1_0_tsize == LRAT_PgSize_1GB) | (mas1_0_tsize == LRAT_PgSize_4GB) | (mas1_0_tsize == LRAT_PgSize_16GB) | + (mas1_0_tsize == LRAT_PgSize_256GB) | (mas1_0_tsize == LRAT_PgSize_1TB)); + + // tlbre illegals only dependent on page size for non-lrat reads; lrat selected by ESEL + assign ex2_tlbre_mas1_tsize_not_supp[0] = ((mas1_tsize_direct[0] == 1'b0 & (mas1_0_ind == 1'b0 | tlb0cfg_ind == 1'b0) & (mas0_0_atsel == 1'b0 | ex2_state_q[1] == 1'b1)) | (mas1_tsize_indirect[0] == 1'b0 & mas1_0_ind == 1'b1 & tlb0cfg_ind == 1'b1 & (mas0_0_atsel == 1'b0 | ex2_state_q[1] == 1'b1))) ? 1'b1 : + 1'b0; + + assign ex5_tlbre_mas1_tsize_not_supp[0] = ((mas1_tsize_direct[0] == 1'b0 & (mas1_0_ind == 1'b0 | tlb0cfg_ind == 1'b0) & (mas0_0_atsel == 1'b0 | ex5_state_q[1] == 1'b1)) | (mas1_tsize_indirect[0] == 1'b0 & mas1_0_ind == 1'b1 & tlb0cfg_ind == 1'b1 & (mas0_0_atsel == 1'b0 | ex5_state_q[1] == 1'b1))) ? 1'b1 : + 1'b0; + + // tlbwe illegals dependent on WQ /= 2, for WQ=2 only trying to kill reservation, not write TLB , and ISA is being changed per this + assign ex5_tlbwe_mas1_tsize_not_supp[0] = ((mas1_tsize_direct[0] == 1'b0 & (mas1_0_ind == 1'b0 | tlb0cfg_ind == 1'b0) & mas0_0_wq != 2'b10 & (mas0_0_atsel == 1'b0 | ex5_state_q[1] == 1'b1)) | (mas1_tsize_indirect[0] == 1'b0 & mas1_0_ind == 1'b1 & tlb0cfg_ind == 1'b1 & mas0_0_wq != 2'b10 & (mas0_0_atsel == 1'b0 | ex5_state_q[1] == 1'b1)) | (mas1_tsize_lrat[0] == 1'b0 & mas0_0_atsel == 1'b1 & (mas0_0_wq == 2'b00 | mas0_0_wq == 2'b11) & ex5_state_q[1] == 1'b0)) ? 1'b1 : + 1'b0; + + assign ex6_tlbwe_mas1_tsize_not_supp[0] = ((mas1_tsize_direct[0] == 1'b0 & (mas1_0_ind == 1'b0 | tlb0cfg_ind == 1'b0) & mas0_0_wq != 2'b10 & (mas0_0_atsel == 1'b0 | ex6_state_q[1] == 1'b1)) | (mas1_tsize_indirect[0] == 1'b0 & mas1_0_ind == 1'b1 & tlb0cfg_ind == 1'b1 & mas0_0_wq != 2'b10 & (mas0_0_atsel == 1'b0 | ex6_state_q[1] == 1'b1)) | (mas1_tsize_lrat[0] == 1'b0 & mas0_0_atsel == 1'b1 & (mas0_0_wq == 2'b00 | mas0_0_wq == 2'b11) & ex6_state_q[1] == 1'b0)) ? 1'b1 : + 1'b0; + + // state: 0:pr 1:gs 2:as 3:cm + assign ex5_tlbwe_mas0_lrat_bad_selects[0] = (((mas0_0_hes == 1'b1 | mas0_0_wq == 2'b01 | mas0_0_wq == 2'b10) & mas0_0_atsel == 1'b1 & ex5_state_q[1] == 1'b0)) ? 1'b1 : + 1'b0; + assign ex6_tlbwe_mas0_lrat_bad_selects[0] = (((mas0_0_hes == 1'b1 | mas0_0_wq == 2'b01 | mas0_0_wq == 2'b10) & mas0_0_atsel == 1'b1 & ex6_state_q[1] == 1'b0)) ? 1'b1 : + 1'b0; + assign ex5_tlbwe_mas2_ind_bad_wimge[0] = ((mas1_0_ind == 1'b1 & tlb0cfg_ind == 1'b1 & mas0_0_wq != 2'b10 & (mas2_0_wimge[1] == 1'b1 | mas2_0_wimge[2] == 1'b0 | mas2_0_wimge[3] == 1'b1 | mas2_0_wimge[4] == 1'b1) & (mas0_0_atsel == 1'b0 | ex5_state_q[1] == 1'b1))) ? 1'b1 : + 1'b0; + assign ex6_tlbwe_mas2_ind_bad_wimge[0] = ((mas1_0_ind == 1'b1 & tlb0cfg_ind == 1'b1 & mas0_0_wq != 2'b10 & (mas2_0_wimge[1] == 1'b1 | mas2_0_wimge[2] == 1'b0 | mas2_0_wimge[3] == 1'b1 | mas2_0_wimge[4] == 1'b1) & (mas0_0_atsel == 1'b0 | ex6_state_q[1] == 1'b1))) ? 1'b1 : + 1'b0; + // Added for illegal indirect page size and sub-page size combinations + // mas3_0_usxwr : in std_ulogic_vector(0 to 3); + assign mas3_spsize_indirect[0] = (((mas1_0_tsize == TLB_PgSize_1MB & mas3_0_usxwr[0:3] == TLB_PgSize_4KB) | (mas1_0_tsize == TLB_PgSize_256MB & mas3_0_usxwr[0:3] == TLB_PgSize_64KB))) ? 1'b1 : + 1'b0; + assign ex5_tlbwe_mas3_ind_bad_spsize[0] = ((mas1_0_ind == 1'b1 & tlb0cfg_ind == 1'b1 & mas0_0_wq != 2'b10 & mas3_spsize_indirect[0] == 1'b0 & (mas0_0_atsel == 1'b0 | ex5_state_q[1] == 1'b1))) ? 1'b1 : + 1'b0; + assign ex6_tlbwe_mas3_ind_bad_spsize[0] = ((mas1_0_ind == 1'b1 & tlb0cfg_ind == 1'b1 & mas0_0_wq != 2'b10 & mas3_spsize_indirect[0] == 1'b0 & (mas0_0_atsel == 1'b0 | ex6_state_q[1] == 1'b1))) ? 1'b1 : + 1'b0; + +`ifdef MM_THREADS2 + assign mas1_tsize_direct[1] = ((mas1_1_tsize == TLB_PgSize_4KB) | (mas1_1_tsize == TLB_PgSize_64KB) | (mas1_1_tsize == TLB_PgSize_1MB) | + (mas1_1_tsize == TLB_PgSize_16MB) | (mas1_1_tsize == TLB_PgSize_1GB)); + + assign mas1_tsize_indirect[1] = ((mas1_1_tsize == TLB_PgSize_1MB) | (mas1_1_tsize == TLB_PgSize_256MB)); + + assign mas1_tsize_lrat[1] = ((mas1_1_tsize == LRAT_PgSize_1MB) | (mas1_1_tsize == LRAT_PgSize_16MB) | (mas1_1_tsize == LRAT_PgSize_256MB) | + (mas1_1_tsize == LRAT_PgSize_1GB) | (mas1_1_tsize == LRAT_PgSize_4GB) | (mas1_1_tsize == LRAT_PgSize_16GB) | + (mas1_1_tsize == LRAT_PgSize_256GB) | (mas1_1_tsize == LRAT_PgSize_1TB)); + + assign ex2_tlbre_mas1_tsize_not_supp[1] = ((mas1_tsize_direct[1] == 1'b0 & (mas1_1_ind == 1'b0 | tlb0cfg_ind == 1'b0) & (mas0_1_atsel == 1'b0 | ex2_state_q[1] == 1'b1)) | (mas1_tsize_indirect[1] == 1'b0 & mas1_1_ind == 1'b1 & tlb0cfg_ind == 1'b1 & (mas0_1_atsel == 1'b0 | ex2_state_q[1] == 1'b1))) ? 1'b1 : + 1'b0; + + assign ex5_tlbre_mas1_tsize_not_supp[1] = ((mas1_tsize_direct[1] == 1'b0 & (mas1_1_ind == 1'b0 | tlb0cfg_ind == 1'b0) & (mas0_1_atsel == 1'b0 | ex5_state_q[1] == 1'b1)) | (mas1_tsize_indirect[1] == 1'b0 & mas1_1_ind == 1'b1 & tlb0cfg_ind == 1'b1 & (mas0_1_atsel == 1'b0 | ex5_state_q[1] == 1'b1))) ? 1'b1 : + 1'b0; + + assign ex5_tlbwe_mas1_tsize_not_supp[1] = ((mas1_tsize_direct[1] == 1'b0 & (mas1_1_ind == 1'b0 | tlb0cfg_ind == 1'b0) & mas0_1_wq != 2'b10 & (mas0_1_atsel == 1'b0 | ex5_state_q[1] == 1'b1)) | (mas1_tsize_indirect[1] == 1'b0 & mas1_1_ind == 1'b1 & tlb0cfg_ind == 1'b1 & mas0_1_wq != 2'b10 & (mas0_1_atsel == 1'b0 | ex5_state_q[1] == 1'b1)) | (mas1_tsize_lrat[1] == 1'b0 & mas0_1_atsel == 1'b1 & (mas0_1_wq == 2'b00 | mas0_1_wq == 2'b11) & ex5_state_q[1] == 1'b0)) ? 1'b1 : + 1'b0; + + assign ex6_tlbwe_mas1_tsize_not_supp[1] = ((mas1_tsize_direct[1] == 1'b0 & (mas1_1_ind == 1'b0 | tlb0cfg_ind == 1'b0) & mas0_1_wq != 2'b10 & (mas0_1_atsel == 1'b0 | ex6_state_q[1] == 1'b1)) | (mas1_tsize_indirect[1] == 1'b0 & mas1_1_ind == 1'b1 & tlb0cfg_ind == 1'b1 & mas0_1_wq != 2'b10 & (mas0_1_atsel == 1'b0 | ex6_state_q[1] == 1'b1)) | (mas1_tsize_lrat[1] == 1'b0 & mas0_1_atsel == 1'b1 & (mas0_1_wq == 2'b00 | mas0_1_wq == 2'b11) & ex6_state_q[1] == 1'b0)) ? 1'b1 : + 1'b0; + + // state: 0:pr 1:gs 2:as 3:cm + assign ex5_tlbwe_mas0_lrat_bad_selects[1] = (((mas0_1_hes == 1'b1 | mas0_1_wq == 2'b01 | mas0_1_wq == 2'b10) & mas0_1_atsel == 1'b1 & ex5_state_q[1] == 1'b0)) ? 1'b1 : + 1'b0; + assign ex6_tlbwe_mas0_lrat_bad_selects[1] = (((mas0_1_hes == 1'b1 | mas0_1_wq == 2'b01 | mas0_1_wq == 2'b10) & mas0_1_atsel == 1'b1 & ex6_state_q[1] == 1'b0)) ? 1'b1 : + 1'b0; + assign ex5_tlbwe_mas2_ind_bad_wimge[1] = ((mas1_1_ind == 1'b1 & tlb0cfg_ind == 1'b1 & mas0_1_wq != 2'b10 & (mas2_1_wimge[1] == 1'b1 | mas2_1_wimge[2] == 1'b0 | mas2_1_wimge[3] == 1'b1 | mas2_1_wimge[4] == 1'b1) & (mas0_1_atsel == 1'b0 | ex5_state_q[1] == 1'b1))) ? 1'b1 : + 1'b0; + + assign ex6_tlbwe_mas2_ind_bad_wimge[1] = ((mas1_1_ind == 1'b1 & tlb0cfg_ind == 1'b1 & mas0_1_wq != 2'b10 & (mas2_1_wimge[1] == 1'b1 | mas2_1_wimge[2] == 1'b0 | mas2_1_wimge[3] == 1'b1 | mas2_1_wimge[4] == 1'b1) & (mas0_1_atsel == 1'b0 | ex6_state_q[1] == 1'b1))) ? 1'b1 : + 1'b0; + + // Added for illegal indirect page size and sub-page size combinations + // mas3_1_usxwr : in std_ulogic_vector(0 to 3); + assign mas3_spsize_indirect[1] = (((mas1_1_tsize == TLB_PgSize_1MB & mas3_1_usxwr[0:3] == TLB_PgSize_4KB) | (mas1_1_tsize == TLB_PgSize_256MB & mas3_1_usxwr[0:3] == TLB_PgSize_64KB))) ? 1'b1 : + 1'b0; + + assign ex5_tlbwe_mas3_ind_bad_spsize[1] = ((mas1_1_ind == 1'b1 & tlb0cfg_ind == 1'b1 & mas0_1_wq != 2'b10 & mas3_spsize_indirect[1] == 1'b0 & (mas0_1_atsel == 1'b0 | ex5_state_q[1] == 1'b1))) ? 1'b1 : + 1'b0; + + assign ex6_tlbwe_mas3_ind_bad_spsize[1] = ((mas1_1_ind == 1'b1 & tlb0cfg_ind == 1'b1 & mas0_1_wq != 2'b10 & mas3_spsize_indirect[1] == 1'b0 & (mas0_1_atsel == 1'b0 | ex6_state_q[1] == 1'b1))) ? 1'b1 : + 1'b0; + +`endif + + assign tlb_ctl_ex2_illeg_instr = ( ex2_tlbre_mas1_tsize_not_supp & ex2_valid_q & (~(xu_ex2_flush)) & {`MM_THREADS{(ex2_ttype_q[0] & ex2_hv_state & (~ex2_mas0_atsel))}} ); + + assign tlb_ctl_ex6_illeg_instr = ( (ex6_tlbwe_mas1_tsize_not_supp | ex6_tlbwe_mas0_lrat_bad_selects | ex6_tlbwe_mas2_ind_bad_wimge | ex6_tlbwe_mas3_ind_bad_spsize) & + ex6_valid_q & {`MM_THREADS{(ex6_ttype_q[1] & (ex6_hv_state | (ex6_priv_state & (~ex6_dgtmi_state))))}} ); + + assign ex6_illeg_instr_d[0] = ex5_ttype_q[0] & |(ex5_tlbre_mas1_tsize_not_supp & ex5_valid_q); + + assign ex6_illeg_instr_d[1] = ex5_ttype_q[1] & |( (ex5_tlbwe_mas1_tsize_not_supp | ex5_tlbwe_mas0_lrat_bad_selects | + ex5_tlbwe_mas2_ind_bad_wimge | ex5_tlbwe_mas3_ind_bad_spsize) & ex5_valid_q ); + + assign ex6_illeg_instr = ex6_illeg_instr_q; + + // state: 0:pr 1:gs 2:as 3:cm + //ex6_hv_state <= not ex6_state_q(0) and not ex6_state_q(1); -- pr=0, gs=0 + //ex6_priv_state <= not ex6_state_q(0); -- pr=0 + //ex6_dgtmi_state <= |(ex6_valid_q and xu_mm_epcr_dgtmi); -- disable guest tlb mgmt instr's + // lru_tag4_dataout : in std_ulogic_vector(0 to 15); -- latched lru_dataout + // tlb_tag4_esel : in std_ulogic_vector(0 to 2); + // tlb_tag4_wq : in std_ulogic_vector(0 to 1); + // tlb_tag4_gs : in std_ulogic; + // tlb_tag4_hes : in std_ulogic; + // tlb_tag4_atsel : in std_ulogic; + // tlb_tag4_cmp_hit : in std_ulogic; -- hit indication + // tlb_tag4_way_ind : in std_ulogic; -- indirect entry hit indication + // tlb_tag4_ptereload : in std_ulogic; -- ptereload write event + // Event | Exceptions + // | PT fault | TLB Inelig | LRAT miss + //-------------------------------------------------------- + // tlbwe | - | hv_priv=1 | lrat_miss=1 + // | | tlbi=1 | esr_pt=0 + // | | esr_pt=0 | + //-------------------------------------------------------- + // ptereload | DSI | DSI | lrat_miss=1 + // (data) | pt_fault=1 | tlbi=1 | esr_pt=1 + // | PT=1 | esr_pt=0 ? | esr_data=1 + // | | | esr_epid=class(0) + // | | | esr_st=class(1) + //-------------------------------------------------------- + // ptereload | ISI | ISI | lrat_miss=1 + // (inst) | pt_fault=1 | tlbi=1 | esr_pt=1 + // | PT=1 | esr_pt=0 ? | esr_data=0 + //-------------------------------------------------------- + assign tlb_lper_lpn = ptereload_req_pte_q[`ptepos_rpn + 10:`ptepos_rpn + 39]; + + assign tlb_lper_lps = ptereload_req_pte_q[`ptepos_size:`ptepos_size + 3]; + + // lrat hit_status: 0:val,1:hit,2:multihit,3:inval_pgsize + // unused `tagpos_is def is mas1_v, mas1_iprot for tlbwe, and is (pte.valid & 0) for ptereloads + assign tlb_lper_we = ( (tlb_tag4_ptereload == 1'b1 & tlb_tag4_gs == 1'b1 & mmucfg_lrat == 1'b1 & + tlb_tag4_pt == 1'b1 & tlb_tag4_wq == 2'b10 & tlb_tag4_is[0] == 1'b1 & + lrat_tag4_hit_status[0:3] != 4'b1100) ) ? tlb_tag0_q[`tagpos_thdid:`tagpos_thdid + `MM_THREADS -1] : + {`MM_THREADS{1'b0}}; + + assign pte_tag0_lpn = ptereload_req_pte_q[`ptepos_rpn + 10:`ptepos_rpn + 39]; + + assign pte_tag0_lpid = tlb_tag0_q[`tagpos_lpid:`tagpos_lpid + `LPID_WIDTH - 1]; + + + // perf count events + assign tlb_ctl_perf_tlbwec_resv = |(ex6_valid_q & tlb_resv_match_vec_q) & ex6_ttype_q[1] & (tlb_tag4_wq == 2'b01); + + assign tlb_ctl_perf_tlbwec_noresv = |(ex6_valid_q & (~tlb_resv_match_vec_q)) & ex6_ttype_q[1] & (tlb_tag4_wq == 2'b01); + + // power clock gating for latches + assign tlb_early_act = xu_mm_ccr2_notlb_b & (any_tlb_req_sig | (~(tlb_seq_idle_sig)) | tlb_ctl_any_tag_flush_sig | tlb_seq_abort); + + assign tlb_delayed_act_d[0:1] = (tlb_early_act == 1'b1) ? 2'b11 : + (tlb_delayed_act_q[0:1] == 2'b11) ? 2'b10 : + (tlb_delayed_act_q[0:1] == 2'b10) ? 2'b01 : + 2'b00; + + // mmq_tlb_req => n/a => mmucr2(0) + // mmq_tlb_ctl => tlb_delayed_act(2 to 8) => mmucr2(1) + // mmq_tlb_cmp => tlb_delayed_act(9 to 16) => mmucr2(2) + // tlb0, tlb1 => tlb_delayed_act(17) => mmucr2(2) + // tlb2, tlb3 => tlb_delayed_act(18) => mmucr2(2) + // lru rd => tlb_delayed_act(19) => removed mmucr2(2) override + // lru wr => tlb_delayed_act(33) => removed mmucr2(2) override + // mmq_tlb_lrat => tlb_delayed_act(20 to 23) => mmucr2(3) + // mmq_htw => tlb_delayed_act(24 to 28) => mmucr2(4) + // mmq_spr => tlb_delayed_act(29 to 32) => mmucr2(5 to 6) + // mmq_inval => n/a => mmucr2(7) + assign tlb_delayed_act_d[2:8] = {7{tlb_early_act | tlb_delayed_act_q[0] | tlb_delayed_act_q[1] | mmucr2[1]}}; + assign tlb_delayed_act_d[9:16] = {8{tlb_early_act | tlb_delayed_act_q[0] | tlb_delayed_act_q[1] | mmucr2[2]}}; + assign tlb_delayed_act_d[17:18] = {2{tlb_early_act | tlb_delayed_act_q[0] | tlb_delayed_act_q[1] | mmucr2[2]}}; // tlb array 0/1, 2/3 act's + assign tlb_delayed_act_d[20:23] = {4{tlb_early_act | tlb_delayed_act_q[0] | tlb_delayed_act_q[1] | mmucr2[3]}}; + assign tlb_delayed_act_d[24:28] = {5{tlb_early_act | tlb_delayed_act_q[0] | tlb_delayed_act_q[1] | mmucr2[4]}}; + assign tlb_delayed_act_d[29:32] = {4{tlb_early_act | tlb_delayed_act_q[0] | tlb_delayed_act_q[1] | mmucr2[6]}}; + + assign tlb_delayed_act_d[19] = xu_mm_ccr2_notlb_b & tlb_seq_lru_rd_act; // lru rd_act + assign tlb_delayed_act_d[33] = xu_mm_ccr2_notlb_b & tlb_seq_lru_wr_act; // lru wr_act + + assign tlb_delayed_act[9:33] = tlb_delayed_act_q[9:33]; + + assign tlb_tag0_act = tlb_early_act | mmucr2[1]; + assign tlb_snoop_act = (tlb_snoop_coming | mmucr2[1]) & xu_mm_ccr2_notlb_b; + assign tlb_ctl_dbg_seq_q = tlb_seq_q; + assign tlb_ctl_dbg_seq_idle = tlb_seq_idle_sig; + assign tlb_ctl_dbg_seq_any_done_sig = tlb_seq_any_done_sig; + assign tlb_ctl_dbg_seq_abort = tlb_seq_abort; + assign tlb_ctl_dbg_any_tlb_req_sig = any_tlb_req_sig; + assign tlb_ctl_dbg_any_req_taken_sig = any_req_taken_sig; + assign tlb_ctl_dbg_tag0_valid = |(tlb_tag0_q[`tagpos_thdid:`tagpos_thdid + `THDID_WIDTH - 1]); + assign tlb_ctl_dbg_tag0_thdid[0] = tlb_tag0_q[`tagpos_thdid + 2] | tlb_tag0_q[`tagpos_thdid + 3]; + assign tlb_ctl_dbg_tag0_thdid[1] = tlb_tag0_q[`tagpos_thdid + 1] | tlb_tag0_q[`tagpos_thdid + 3]; + assign tlb_ctl_dbg_tag0_type[0] = tlb_tag0_q[`tagpos_type + 4] | tlb_tag0_q[`tagpos_type + 5] | tlb_tag0_q[`tagpos_type + 6] | tlb_tag0_q[`tagpos_type + 7]; + assign tlb_ctl_dbg_tag0_type[1] = tlb_tag0_q[`tagpos_type + 2] | tlb_tag0_q[`tagpos_type + 3] | tlb_tag0_q[`tagpos_type + 6] | tlb_tag0_q[`tagpos_type + 7]; + assign tlb_ctl_dbg_tag0_type[2] = tlb_tag0_q[`tagpos_type + 1] | tlb_tag0_q[`tagpos_type + 3] | tlb_tag0_q[`tagpos_type + 5] | tlb_tag0_q[`tagpos_type + 7]; + assign tlb_ctl_dbg_tag0_wq = tlb_tag0_q[`tagpos_wq:`tagpos_wq + 1]; + assign tlb_ctl_dbg_tag0_gs = tlb_tag0_q[`tagpos_gs]; + assign tlb_ctl_dbg_tag0_pr = tlb_tag0_q[`tagpos_pr]; + assign tlb_ctl_dbg_tag0_atsel = tlb_tag0_q[`tagpos_atsel]; + assign tlb_ctl_dbg_tag5_tlb_write_q = tlb_write_q; + assign tlb_ctl_dbg_any_tag_flush_sig = tlb_ctl_any_tag_flush_sig; + assign tlb_ctl_dbg_resv0_tag0_lpid_match = tlb_resv0_tag0_lpid_match; + assign tlb_ctl_dbg_resv0_tag0_pid_match = tlb_resv0_tag0_pid_match; + assign tlb_ctl_dbg_resv0_tag0_as_snoop_match = tlb_resv0_tag0_as_snoop_match; + assign tlb_ctl_dbg_resv0_tag0_gs_snoop_match = tlb_resv0_tag0_gs_snoop_match; + assign tlb_ctl_dbg_resv0_tag0_as_tlbwe_match = tlb_resv0_tag0_as_tlbwe_match; + assign tlb_ctl_dbg_resv0_tag0_gs_tlbwe_match = tlb_resv0_tag0_gs_tlbwe_match; + assign tlb_ctl_dbg_resv0_tag0_ind_match = tlb_resv0_tag0_ind_match; + assign tlb_ctl_dbg_resv0_tag0_epn_loc_match = tlb_resv0_tag0_epn_loc_match; + assign tlb_ctl_dbg_resv0_tag0_epn_glob_match = tlb_resv0_tag0_epn_glob_match; + assign tlb_ctl_dbg_resv0_tag0_class_match = tlb_resv0_tag0_class_match; + assign tlb_ctl_dbg_set_resv[0] = tlb_set_resv0; + assign tlb_ctl_dbg_clr_resv_q[0] = tlb_clr_resv_q[0]; + assign tlb_ctl_dbg_resv_valid[0] = tlb_resv_valid_vec[0]; + assign tlb_ctl_dbg_resv_match_vec_q[0] = tlb_resv_match_vec_q[0]; +`ifdef MM_THREADS2 + assign tlb_ctl_dbg_resv1_tag0_lpid_match = tlb_resv1_tag0_lpid_match; + assign tlb_ctl_dbg_resv1_tag0_pid_match = tlb_resv1_tag0_pid_match; + assign tlb_ctl_dbg_resv1_tag0_as_snoop_match = tlb_resv1_tag0_as_snoop_match; + assign tlb_ctl_dbg_resv1_tag0_gs_snoop_match = tlb_resv1_tag0_gs_snoop_match; + assign tlb_ctl_dbg_resv1_tag0_as_tlbwe_match = tlb_resv1_tag0_as_tlbwe_match; + assign tlb_ctl_dbg_resv1_tag0_gs_tlbwe_match = tlb_resv1_tag0_gs_tlbwe_match; + assign tlb_ctl_dbg_resv1_tag0_ind_match = tlb_resv1_tag0_ind_match; + assign tlb_ctl_dbg_resv1_tag0_epn_loc_match = tlb_resv1_tag0_epn_loc_match; + assign tlb_ctl_dbg_resv1_tag0_epn_glob_match = tlb_resv1_tag0_epn_glob_match; + assign tlb_ctl_dbg_resv1_tag0_class_match = tlb_resv1_tag0_class_match; + assign tlb_ctl_dbg_set_resv[1] = tlb_set_resv1; + assign tlb_ctl_dbg_clr_resv_q[1] = tlb_clr_resv_q[1]; + assign tlb_ctl_dbg_resv_valid[1] = tlb_resv_valid_vec[1]; + assign tlb_ctl_dbg_resv_match_vec_q[1] = tlb_resv_match_vec_q[1]; +`else + assign tlb_ctl_dbg_resv1_tag0_lpid_match = 1'b0; + assign tlb_ctl_dbg_resv1_tag0_pid_match = 1'b0; + assign tlb_ctl_dbg_resv1_tag0_as_snoop_match = 1'b0; + assign tlb_ctl_dbg_resv1_tag0_gs_snoop_match = 1'b0; + assign tlb_ctl_dbg_resv1_tag0_as_tlbwe_match = 1'b0; + assign tlb_ctl_dbg_resv1_tag0_gs_tlbwe_match = 1'b0; + assign tlb_ctl_dbg_resv1_tag0_ind_match = 1'b0; + assign tlb_ctl_dbg_resv1_tag0_epn_loc_match = 1'b0; + assign tlb_ctl_dbg_resv1_tag0_epn_glob_match = 1'b0; + assign tlb_ctl_dbg_resv1_tag0_class_match = 1'b0; + assign tlb_ctl_dbg_set_resv[1] = 1'b0; + assign tlb_ctl_dbg_clr_resv_q[1] = 1'b0; + assign tlb_ctl_dbg_resv_valid[1] = 1'b0; + assign tlb_ctl_dbg_resv_match_vec_q[1] = 1'b0; +`endif + assign tlb_ctl_dbg_resv2_tag0_lpid_match = 1'b0; + assign tlb_ctl_dbg_resv2_tag0_pid_match = 1'b0; + assign tlb_ctl_dbg_resv2_tag0_as_snoop_match = 1'b0; + assign tlb_ctl_dbg_resv2_tag0_gs_snoop_match = 1'b0; + assign tlb_ctl_dbg_resv2_tag0_as_tlbwe_match = 1'b0; + assign tlb_ctl_dbg_resv2_tag0_gs_tlbwe_match = 1'b0; + assign tlb_ctl_dbg_resv2_tag0_ind_match = 1'b0; + assign tlb_ctl_dbg_resv2_tag0_epn_loc_match = 1'b0; + assign tlb_ctl_dbg_resv2_tag0_epn_glob_match = 1'b0; + assign tlb_ctl_dbg_resv2_tag0_class_match = 1'b0; + assign tlb_ctl_dbg_set_resv[2] = 1'b0; + assign tlb_ctl_dbg_clr_resv_q[2] = 1'b0; + assign tlb_ctl_dbg_resv_valid[2] = 1'b0; + assign tlb_ctl_dbg_resv_match_vec_q[2] = 1'b0; + assign tlb_ctl_dbg_resv3_tag0_lpid_match = 1'b0; + assign tlb_ctl_dbg_resv3_tag0_pid_match = 1'b0; + assign tlb_ctl_dbg_resv3_tag0_as_snoop_match = 1'b0; + assign tlb_ctl_dbg_resv3_tag0_gs_snoop_match = 1'b0; + assign tlb_ctl_dbg_resv3_tag0_as_tlbwe_match = 1'b0; + assign tlb_ctl_dbg_resv3_tag0_gs_tlbwe_match = 1'b0; + assign tlb_ctl_dbg_resv3_tag0_ind_match = 1'b0; + assign tlb_ctl_dbg_resv3_tag0_epn_loc_match = 1'b0; + assign tlb_ctl_dbg_resv3_tag0_epn_glob_match = 1'b0; + assign tlb_ctl_dbg_resv3_tag0_class_match = 1'b0; + assign tlb_ctl_dbg_set_resv[3] = 1'b0; + assign tlb_ctl_dbg_clr_resv_q[3] = 1'b0; + assign tlb_ctl_dbg_resv_valid[3] = 1'b0; + assign tlb_ctl_dbg_resv_match_vec_q[3] = 1'b0; + assign tlb_ctl_dbg_clr_resv_terms = {4{1'b0}}; + + // unused spare signal assignments + assign unused_dc[0] = |(lcb_delay_lclkr_dc[1:4]); + assign unused_dc[1] = |(lcb_mpw1_dc_b[1:4]); + assign unused_dc[2] = pc_func_sl_force; + assign unused_dc[3] = pc_func_sl_thold_0_b; + assign unused_dc[4] = tc_scan_dis_dc_b; + assign unused_dc[5] = tc_scan_diag_dc; + assign unused_dc[6] = tc_lbist_en_dc; + assign unused_dc[7] = tlb_tag0_q[109]; +`ifdef MM_THREADS2 + assign unused_dc[8] = mmucr3_0[49] | mmucr3_0[56] | mmucr3_1[49] | mmucr3_1[56]; + assign unused_dc[9] = mmucr3_0[50] | mmucr3_0[57] | mmucr3_1[50] | mmucr3_1[57]; + assign unused_dc[10] = mmucr3_0[51] | mmucr3_0[58] | mmucr3_1[51] | mmucr3_1[58]; + assign unused_dc[11] = mmucr3_0[52] | mmucr3_0[59] | mmucr3_1[52] | mmucr3_1[59]; + assign unused_dc[12] = mmucr3_0[53] | mmucr3_0[60] | mmucr3_1[53] | mmucr3_1[60]; + assign unused_dc[13] = mmucr3_0[61] | mmucr3_1[61]; + assign unused_dc[14] = mmucr3_0[62] | mmucr3_1[62]; + assign unused_dc[15] = mmucr3_0[63] | mmucr3_1[63]; +`else + assign unused_dc[8] = mmucr3_0[49] | mmucr3_0[56]; + assign unused_dc[9] = mmucr3_0[50] | mmucr3_0[57]; + assign unused_dc[10] = mmucr3_0[51] | mmucr3_0[58]; + assign unused_dc[11] = mmucr3_0[52] | mmucr3_0[59]; + assign unused_dc[12] = mmucr3_0[53] | mmucr3_0[60]; + assign unused_dc[13] = mmucr3_0[61]; + assign unused_dc[14] = mmucr3_0[62]; + assign unused_dc[15] = mmucr3_0[63]; +`endif + assign unused_dc[16] = |(pgsize_qty); + assign unused_dc[17] = |(pgsize_tid0_qty); + assign unused_dc[18] = ptereload_req_tag[66]; + assign unused_dc[19] = |(ptereload_req_tag[78:81]); + assign unused_dc[20] = |(ptereload_req_tag[84:89]); + assign unused_dc[21] = ptereload_req_tag[98]; + assign unused_dc[22] = |(ptereload_req_tag[108:109]); + assign unused_dc[23] = lru_tag4_dataout[7]; + assign unused_dc[24] = |(lru_tag4_dataout[12:15]); + assign unused_dc[25] = tlb_tag4_esel[0]; + assign unused_dc[26] = ex3_valid_32b; +`ifdef MM_THREADS2 + assign unused_dc[27] = mas2_0_wimge[0] | mas2_1_wimge[0]; +`else + assign unused_dc[27] = mas2_0_wimge[0]; +`endif + assign unused_dc[28] = |(xu_ex1_flush_q); + assign unused_dc[29] = |(mm_xu_eratmiss_done); + assign unused_dc[30] = |(mm_xu_tlb_miss); + assign unused_dc[31] = |(mm_xu_tlb_inelig); + assign unused_dc[32] = mmucr1_tlbi_msb; + assign unused_dc[33] = mmucsr0_tlb0fi; + assign unused_dc[34] = tlb_tag4_pr; + assign unused_dc[35] = |({mmucr2[0], mmucr2[5], mmucr2[7], mmucr2[8:11]}); + assign unused_dc[36] = tlb_seq_lrat_enable; + + generate + if (`THDID_WIDTH > `MM_THREADS) + begin : tlbctlthdNExist + begin : xhdl0 + genvar tid; + for (tid = `MM_THREADS; tid <= (`THDID_WIDTH - 1); tid = tid + 1) + begin : tlbctlthdunused + assign unused_dc_thdid[tid] = tlb_delayed_act_q[tid + 5]; + end + end + end + endgenerate + + + //--------------------------------------------------------------------- + // Latches + //--------------------------------------------------------------------- + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) xu_ex1_flush_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[xu_ex1_flush_offset:xu_ex1_flush_offset + `MM_THREADS - 1]), + .scout(sov[xu_ex1_flush_offset:xu_ex1_flush_offset + `MM_THREADS - 1]), + .din(xu_ex1_flush_d), + .dout(xu_ex1_flush_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex1_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex1_valid_offset:ex1_valid_offset + `MM_THREADS - 1]), + .scout(sov[ex1_valid_offset:ex1_valid_offset + `MM_THREADS - 1]), + .din(ex1_valid_d), + .dout(ex1_valid_q) + ); + + tri_rlmreg_p #(.WIDTH(`CTL_TTYPE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex1_ttype_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex1_ttype_offset:ex1_ttype_offset + `CTL_TTYPE_WIDTH - 1]), + .scout(sov[ex1_ttype_offset:ex1_ttype_offset + `CTL_TTYPE_WIDTH - 1]), + .din(ex1_ttype_d[0:`CTL_TTYPE_WIDTH - 1]), + .dout(ex1_ttype_q[0:`CTL_TTYPE_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH((`CTL_STATE_WIDTH+1)), .INIT(0), .NEEDS_SRESET(1)) ex1_state_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex1_state_offset:ex1_state_offset + (`CTL_STATE_WIDTH+1) - 1]), + .scout(sov[ex1_state_offset:ex1_state_offset + (`CTL_STATE_WIDTH+1) - 1]), + .din(ex1_state_d[0:`CTL_STATE_WIDTH]), + .dout(ex1_state_q[0:`CTL_STATE_WIDTH]) + ); + + tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex1_pid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex1_pid_offset:ex1_pid_offset + `PID_WIDTH - 1]), + .scout(sov[ex1_pid_offset:ex1_pid_offset + `PID_WIDTH - 1]), + .din(ex1_pid_d[0:`PID_WIDTH - 1]), + .dout(ex1_pid_q[0:`PID_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex1_itag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex1_itag_offset:ex1_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[ex1_itag_offset:ex1_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(ex1_itag_d), + .dout(ex1_itag_q) + ); + //----------------------------------------------------------------------------- + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex2_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex2_valid_offset:ex2_valid_offset + `MM_THREADS - 1]), + .scout(sov[ex2_valid_offset:ex2_valid_offset + `MM_THREADS - 1]), + .din(ex2_valid_d), + .dout(ex2_valid_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex2_flush_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex2_flush_offset:ex2_flush_offset + `MM_THREADS - 1]), + .scout(sov[ex2_flush_offset:ex2_flush_offset + `MM_THREADS - 1]), + .din(ex2_flush_d), + .dout(ex2_flush_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex2_flush_req_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex2_flush_req_offset:ex2_flush_req_offset + `MM_THREADS - 1]), + .scout(sov[ex2_flush_req_offset:ex2_flush_req_offset + `MM_THREADS - 1]), + .din(ex2_flush_req_d), + .dout(ex2_flush_req_q) + ); + + tri_rlmreg_p #(.WIDTH(`CTL_TTYPE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex2_ttype_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex2_ttype_offset:ex2_ttype_offset + `CTL_TTYPE_WIDTH - 1]), + .scout(sov[ex2_ttype_offset:ex2_ttype_offset + `CTL_TTYPE_WIDTH - 1]), + .din(ex2_ttype_d[0:`CTL_TTYPE_WIDTH - 1]), + .dout(ex2_ttype_q[0:`CTL_TTYPE_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH((`CTL_STATE_WIDTH+1)), .INIT(0), .NEEDS_SRESET(1)) ex2_state_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex2_state_offset:ex2_state_offset + (`CTL_STATE_WIDTH+1) - 1]), + .scout(sov[ex2_state_offset:ex2_state_offset + (`CTL_STATE_WIDTH+1) - 1]), + .din(ex2_state_d[0:`CTL_STATE_WIDTH]), + .dout(ex2_state_q[0:`CTL_STATE_WIDTH]) + ); + + tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex2_pid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex2_pid_offset:ex2_pid_offset + `PID_WIDTH - 1]), + .scout(sov[ex2_pid_offset:ex2_pid_offset + `PID_WIDTH - 1]), + .din(ex2_pid_d[0:`PID_WIDTH - 1]), + .dout(ex2_pid_q[0:`PID_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex2_itag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex2_itag_offset:ex2_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[ex2_itag_offset:ex2_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(ex2_itag_d), + .dout(ex2_itag_q) + ); + //----------------------------------------------------------------------------- + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex3_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex3_valid_offset:ex3_valid_offset + `MM_THREADS - 1]), + .scout(sov[ex3_valid_offset:ex3_valid_offset + `MM_THREADS - 1]), + .din(ex3_valid_d), + .dout(ex3_valid_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex3_flush_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex3_flush_offset:ex3_flush_offset + `MM_THREADS - 1]), + .scout(sov[ex3_flush_offset:ex3_flush_offset + `MM_THREADS - 1]), + .din(ex3_flush_d), + .dout(ex3_flush_q) + ); + + tri_rlmreg_p #(.WIDTH(`CTL_TTYPE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex3_ttype_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex3_ttype_offset:ex3_ttype_offset + `CTL_TTYPE_WIDTH - 1]), + .scout(sov[ex3_ttype_offset:ex3_ttype_offset + `CTL_TTYPE_WIDTH - 1]), + .din(ex3_ttype_d[0:`CTL_TTYPE_WIDTH - 1]), + .dout(ex3_ttype_q[0:`CTL_TTYPE_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH((`CTL_STATE_WIDTH+1)), .INIT(0), .NEEDS_SRESET(1)) ex3_state_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex3_state_offset:ex3_state_offset + (`CTL_STATE_WIDTH+1) - 1]), + .scout(sov[ex3_state_offset:ex3_state_offset + (`CTL_STATE_WIDTH+1) - 1]), + .din(ex3_state_d[0:`CTL_STATE_WIDTH]), + .dout(ex3_state_q[0:`CTL_STATE_WIDTH]) + ); + + tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex3_pid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex3_pid_offset:ex3_pid_offset + `PID_WIDTH - 1]), + .scout(sov[ex3_pid_offset:ex3_pid_offset + `PID_WIDTH - 1]), + .din(ex3_pid_d[0:`PID_WIDTH - 1]), + .dout(ex3_pid_q[0:`PID_WIDTH - 1]) + ); + //----------------------------------------------------------------------------- + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex4_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex4_valid_offset:ex4_valid_offset + `MM_THREADS - 1]), + .scout(sov[ex4_valid_offset:ex4_valid_offset + `MM_THREADS - 1]), + .din(ex4_valid_d), + .dout(ex4_valid_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex4_flush_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex4_flush_offset:ex4_flush_offset + `MM_THREADS - 1]), + .scout(sov[ex4_flush_offset:ex4_flush_offset + `MM_THREADS - 1]), + .din(ex4_flush_d), + .dout(ex4_flush_q) + ); + + tri_rlmreg_p #(.WIDTH(`CTL_TTYPE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex4_ttype_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex4_ttype_offset:ex4_ttype_offset + `CTL_TTYPE_WIDTH - 1]), + .scout(sov[ex4_ttype_offset:ex4_ttype_offset + `CTL_TTYPE_WIDTH - 1]), + .din(ex4_ttype_d[0:`CTL_TTYPE_WIDTH - 1]), + .dout(ex4_ttype_q[0:`CTL_TTYPE_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH((`CTL_STATE_WIDTH+1)), .INIT(0), .NEEDS_SRESET(1)) ex4_state_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex4_state_offset:ex4_state_offset + (`CTL_STATE_WIDTH+1) - 1]), + .scout(sov[ex4_state_offset:ex4_state_offset + (`CTL_STATE_WIDTH+1) - 1]), + .din(ex4_state_d[0:`CTL_STATE_WIDTH]), + .dout(ex4_state_q[0:`CTL_STATE_WIDTH]) + ); + + tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex4_pid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex4_pid_offset:ex4_pid_offset + `PID_WIDTH - 1]), + .scout(sov[ex4_pid_offset:ex4_pid_offset + `PID_WIDTH - 1]), + .din(ex4_pid_d[0:`PID_WIDTH - 1]), + .dout(ex4_pid_q[0:`PID_WIDTH - 1]) + ); + //----------------------------------------------------------------------------- + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex5_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex5_valid_offset:ex5_valid_offset + `MM_THREADS - 1]), + .scout(sov[ex5_valid_offset:ex5_valid_offset + `MM_THREADS - 1]), + .din(ex5_valid_d), + .dout(ex5_valid_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex5_flush_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex5_flush_offset:ex5_flush_offset + `MM_THREADS - 1]), + .scout(sov[ex5_flush_offset:ex5_flush_offset + `MM_THREADS - 1]), + .din(ex5_flush_d), + .dout(ex5_flush_q) + ); + + tri_rlmreg_p #(.WIDTH(`CTL_TTYPE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex5_ttype_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex5_ttype_offset:ex5_ttype_offset + `CTL_TTYPE_WIDTH - 1]), + .scout(sov[ex5_ttype_offset:ex5_ttype_offset + `CTL_TTYPE_WIDTH - 1]), + .din(ex5_ttype_d[0:`CTL_TTYPE_WIDTH - 1]), + .dout(ex5_ttype_q[0:`CTL_TTYPE_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH((`CTL_STATE_WIDTH+1)), .INIT(0), .NEEDS_SRESET(1)) ex5_state_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex5_state_offset:ex5_state_offset + (`CTL_STATE_WIDTH+1) - 1]), + .scout(sov[ex5_state_offset:ex5_state_offset + (`CTL_STATE_WIDTH+1) - 1]), + .din(ex5_state_d[0:`CTL_STATE_WIDTH]), + .dout(ex5_state_q[0:`CTL_STATE_WIDTH]) + ); + + tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex5_pid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex5_pid_offset:ex5_pid_offset + `PID_WIDTH - 1]), + .scout(sov[ex5_pid_offset:ex5_pid_offset + `PID_WIDTH - 1]), + .din(ex5_pid_d[0:`PID_WIDTH - 1]), + .dout(ex5_pid_q[0:`PID_WIDTH - 1]) + ); + //------------------------------------------------ + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex6_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex6_valid_offset:ex6_valid_offset + `MM_THREADS - 1]), + .scout(sov[ex6_valid_offset:ex6_valid_offset + `MM_THREADS - 1]), + .din(ex6_valid_d), + .dout(ex6_valid_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex6_flush_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex6_flush_offset:ex6_flush_offset + `MM_THREADS - 1]), + .scout(sov[ex6_flush_offset:ex6_flush_offset + `MM_THREADS - 1]), + .din(ex6_flush_d), + .dout(ex6_flush_q) + ); + + tri_rlmreg_p #(.WIDTH(`CTL_TTYPE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex6_ttype_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex6_ttype_offset:ex6_ttype_offset + `CTL_TTYPE_WIDTH - 1]), + .scout(sov[ex6_ttype_offset:ex6_ttype_offset + `CTL_TTYPE_WIDTH - 1]), + .din(ex6_ttype_d[0:`CTL_TTYPE_WIDTH - 1]), + .dout(ex6_ttype_q[0:`CTL_TTYPE_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH((`CTL_STATE_WIDTH+1)), .INIT(0), .NEEDS_SRESET(1)) ex6_state_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex6_state_offset:ex6_state_offset + (`CTL_STATE_WIDTH+1) - 1]), + .scout(sov[ex6_state_offset:ex6_state_offset + (`CTL_STATE_WIDTH+1) - 1]), + .din(ex6_state_d[0:`CTL_STATE_WIDTH]), + .dout(ex6_state_q[0:`CTL_STATE_WIDTH]) + ); + + tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex6_pid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex6_pid_offset:ex6_pid_offset + `PID_WIDTH - 1]), + .scout(sov[ex6_pid_offset:ex6_pid_offset + `PID_WIDTH - 1]), + .din(ex6_pid_d[0:`PID_WIDTH - 1]), + .dout(ex6_pid_q[0:`PID_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`TLB_TAG_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_tag0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_tag0_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[tlb_tag0_offset:tlb_tag0_offset + `TLB_TAG_WIDTH - 1]), + .scout(sov[tlb_tag0_offset:tlb_tag0_offset + `TLB_TAG_WIDTH - 1]), + .din(tlb_tag0_d[0:`TLB_TAG_WIDTH - 1]), + .dout(tlb_tag0_q[0:`TLB_TAG_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`TLB_TAG_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_tag1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act_q[2]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[tlb_tag1_offset:tlb_tag1_offset + `TLB_TAG_WIDTH - 1]), + .scout(sov[tlb_tag1_offset:tlb_tag1_offset + `TLB_TAG_WIDTH - 1]), + .din(tlb_tag1_d[0:`TLB_TAG_WIDTH - 1]), + .dout(tlb_tag1_q[0:`TLB_TAG_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`TLB_TAG_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_tag2_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act_q[3]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[tlb_tag2_offset:tlb_tag2_offset + `TLB_TAG_WIDTH - 1]), + .scout(sov[tlb_tag2_offset:tlb_tag2_offset + `TLB_TAG_WIDTH - 1]), + .din(tlb_tag2_d[0:`TLB_TAG_WIDTH - 1]), + .dout(tlb_tag2_q[0:`TLB_TAG_WIDTH - 1]) + ); + // hashed address input to tlb, tag1 phase + + tri_rlmreg_p #(.WIDTH(`TLB_ADDR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_addr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act_q[4]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[tlb_addr_offset:tlb_addr_offset + `TLB_ADDR_WIDTH - 1]), + .scout(sov[tlb_addr_offset:tlb_addr_offset + `TLB_ADDR_WIDTH - 1]), + .din(tlb_addr_d[0:`TLB_ADDR_WIDTH - 1]), + .dout(tlb_addr_q[0:`TLB_ADDR_WIDTH - 1]) + ); + // hashed address input to tlb, tag2 phase + + tri_rlmreg_p #(.WIDTH(`TLB_ADDR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_addr2_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act_q[4]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[tlb_addr2_offset:tlb_addr2_offset + `TLB_ADDR_WIDTH - 1]), + .scout(sov[tlb_addr2_offset:tlb_addr2_offset + `TLB_ADDR_WIDTH - 1]), + .din(tlb_addr2_d[0:`TLB_ADDR_WIDTH - 1]), + .dout(tlb_addr2_q[0:`TLB_ADDR_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`TLB_WAYS), .INIT(0), .NEEDS_SRESET(1)) tlb_write_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act_q[4]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[tlb_write_offset:tlb_write_offset + `TLB_WAYS - 1]), + .scout(sov[tlb_write_offset:tlb_write_offset + `TLB_WAYS - 1]), + .din(tlb_write_d[0:`TLB_WAYS - 1]), + .dout(tlb_write_q[0:`TLB_WAYS - 1]) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex6_illeg_instr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act_q[4]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex6_illeg_instr_offset:ex6_illeg_instr_offset + 2 - 1]), + .scout(sov[ex6_illeg_instr_offset:ex6_illeg_instr_offset + 2 - 1]), + .din(ex6_illeg_instr_d), + .dout(ex6_illeg_instr_q) + ); + // sequencer latches + + tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) tlb_seq_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[tlb_seq_offset:tlb_seq_offset + 6 - 1]), + .scout(sov[tlb_seq_offset:tlb_seq_offset + 6 - 1]), + .din(tlb_seq_d[0:`TLB_SEQ_WIDTH - 1]), + .dout(tlb_seq_q[0:`TLB_SEQ_WIDTH - 1]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) derat_taken_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_taken_offset]), + .scout(sov[derat_taken_offset]), + .din(derat_taken_d), + .dout(derat_taken_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xucr4_mmu_mchk_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[xucr4_mmu_mchk_offset]), + .scout(sov[xucr4_mmu_mchk_offset]), + .din(xu_mm_xucr4_mmu_mchk), + .dout(xu_mm_xucr4_mmu_mchk_q) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) snoop_val_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_snoop_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[snoop_val_offset:snoop_val_offset + 2 - 1]), + .scout(sov[snoop_val_offset:snoop_val_offset + 2 - 1]), + .din(snoop_val_d), + .dout(snoop_val_q) + ); + + tri_rlmreg_p #(.WIDTH(35), .INIT(0), .NEEDS_SRESET(1)) snoop_attr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_snoop_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[snoop_attr_offset:snoop_attr_offset + 35 - 1]), + .scout(sov[snoop_attr_offset:snoop_attr_offset + 35 - 1]), + .din(snoop_attr_d), + .dout(snoop_attr_q) + ); + + tri_rlmreg_p #(.WIDTH(`EPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) snoop_vpn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_snoop_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[snoop_vpn_offset:snoop_vpn_offset + `EPN_WIDTH - 1]), + .scout(sov[snoop_vpn_offset:snoop_vpn_offset + `EPN_WIDTH - 1]), + .din(snoop_vpn_d), + .dout(snoop_vpn_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) tlb_clr_resv_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act_q[4]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[tlb_clr_resv_offset:tlb_clr_resv_offset + `MM_THREADS - 1]), + .scout(sov[tlb_clr_resv_offset:tlb_clr_resv_offset + `MM_THREADS - 1]), + .din(tlb_clr_resv_d), + .dout(tlb_clr_resv_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) tlb_resv_match_vec_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act_q[4]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[tlb_resv_match_vec_offset:tlb_resv_match_vec_offset + `MM_THREADS - 1]), + .scout(sov[tlb_resv_match_vec_offset:tlb_resv_match_vec_offset + `MM_THREADS - 1]), + .din(tlb_resv_match_vec_d), + .dout(tlb_resv_match_vec_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_resv0_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act_q[5 + 0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[tlb_resv0_valid_offset]), + .scout(sov[tlb_resv0_valid_offset]), + .din(tlb_resv0_valid_d), + .dout(tlb_resv0_valid_q) + ); + + tri_rlmreg_p #(.WIDTH(`EPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_resv0_epn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act_q[5 + 0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[tlb_resv0_epn_offset:tlb_resv0_epn_offset + `EPN_WIDTH - 1]), + .scout(sov[tlb_resv0_epn_offset:tlb_resv0_epn_offset + `EPN_WIDTH - 1]), + .din(tlb_resv0_epn_d), + .dout(tlb_resv0_epn_q) + ); + + tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_resv0_pid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act_q[5 + 0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[tlb_resv0_pid_offset:tlb_resv0_pid_offset + `PID_WIDTH - 1]), + .scout(sov[tlb_resv0_pid_offset:tlb_resv0_pid_offset + `PID_WIDTH - 1]), + .din(tlb_resv0_pid_d[0:`PID_WIDTH - 1]), + .dout(tlb_resv0_pid_q[0:`PID_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_resv0_lpid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act_q[5 + 0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[tlb_resv0_lpid_offset:tlb_resv0_lpid_offset + `LPID_WIDTH - 1]), + .scout(sov[tlb_resv0_lpid_offset:tlb_resv0_lpid_offset + `LPID_WIDTH - 1]), + .din(tlb_resv0_lpid_d[0:`LPID_WIDTH - 1]), + .dout(tlb_resv0_lpid_q[0:`LPID_WIDTH - 1]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_resv0_as_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act_q[5 + 0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[tlb_resv0_as_offset]), + .scout(sov[tlb_resv0_as_offset]), + .din(tlb_resv0_as_d), + .dout(tlb_resv0_as_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_resv0_gs_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act_q[5 + 0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[tlb_resv0_gs_offset]), + .scout(sov[tlb_resv0_gs_offset]), + .din(tlb_resv0_gs_d), + .dout(tlb_resv0_gs_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_resv0_ind_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act_q[5 + 0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[tlb_resv0_ind_offset]), + .scout(sov[tlb_resv0_ind_offset]), + .din(tlb_resv0_ind_d), + .dout(tlb_resv0_ind_q) + ); + + tri_rlmreg_p #(.WIDTH(`CLASS_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_resv0_class_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act_q[5 + 0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[tlb_resv0_class_offset:tlb_resv0_class_offset + `CLASS_WIDTH - 1]), + .scout(sov[tlb_resv0_class_offset:tlb_resv0_class_offset + `CLASS_WIDTH - 1]), + .din(tlb_resv0_class_d[0:`CLASS_WIDTH - 1]), + .dout(tlb_resv0_class_q[0:`CLASS_WIDTH - 1]) + ); + +`ifdef MM_THREADS2 + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_resv1_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act_q[5 + 1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[tlb_resv1_valid_offset]), + .scout(sov[tlb_resv1_valid_offset]), + .din(tlb_resv1_valid_d), + .dout(tlb_resv1_valid_q) + ); + + tri_rlmreg_p #(.WIDTH(`EPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_resv1_epn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act_q[5 + 1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[tlb_resv1_epn_offset:tlb_resv1_epn_offset + `EPN_WIDTH - 1]), + .scout(sov[tlb_resv1_epn_offset:tlb_resv1_epn_offset + `EPN_WIDTH - 1]), + .din(tlb_resv1_epn_d), + .dout(tlb_resv1_epn_q) + ); + + tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_resv1_pid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act_q[5 + 1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[tlb_resv1_pid_offset:tlb_resv1_pid_offset + `PID_WIDTH - 1]), + .scout(sov[tlb_resv1_pid_offset:tlb_resv1_pid_offset + `PID_WIDTH - 1]), + .din(tlb_resv1_pid_d[0:`PID_WIDTH - 1]), + .dout(tlb_resv1_pid_q[0:`PID_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_resv1_lpid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act_q[5 + 1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[tlb_resv1_lpid_offset:tlb_resv1_lpid_offset + `LPID_WIDTH - 1]), + .scout(sov[tlb_resv1_lpid_offset:tlb_resv1_lpid_offset + `LPID_WIDTH - 1]), + .din(tlb_resv1_lpid_d[0:`LPID_WIDTH - 1]), + .dout(tlb_resv1_lpid_q[0:`LPID_WIDTH - 1]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_resv1_as_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act_q[5 + 1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[tlb_resv1_as_offset]), + .scout(sov[tlb_resv1_as_offset]), + .din(tlb_resv1_as_d), + .dout(tlb_resv1_as_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_resv1_gs_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act_q[5 + 1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[tlb_resv1_gs_offset]), + .scout(sov[tlb_resv1_gs_offset]), + .din(tlb_resv1_gs_d), + .dout(tlb_resv1_gs_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_resv1_ind_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act_q[5 + 1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[tlb_resv1_ind_offset]), + .scout(sov[tlb_resv1_ind_offset]), + .din(tlb_resv1_ind_d), + .dout(tlb_resv1_ind_q) + ); + + tri_rlmreg_p #(.WIDTH(`CLASS_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_resv1_class_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act_q[5 + 1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[tlb_resv1_class_offset:tlb_resv1_class_offset + `CLASS_WIDTH - 1]), + .scout(sov[tlb_resv1_class_offset:tlb_resv1_class_offset + `CLASS_WIDTH - 1]), + .din(tlb_resv1_class_d[0:`CLASS_WIDTH - 1]), + .dout(tlb_resv1_class_q[0:`CLASS_WIDTH - 1]) + ); +`endif + + tri_rlmreg_p #(.WIDTH(`PTE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ptereload_req_pte_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ptereload_req_valid), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ptereload_req_pte_offset:ptereload_req_pte_offset + `PTE_WIDTH - 1]), + .scout(sov[ptereload_req_pte_offset:ptereload_req_pte_offset + `PTE_WIDTH - 1]), + .din(ptereload_req_pte_d), + .dout(ptereload_req_pte_q) + ); + // power clock gating latches + + tri_rlmreg_p #(.WIDTH(34), .INIT(0), .NEEDS_SRESET(1)) tlb_delayed_act_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[tlb_delayed_act_offset:tlb_delayed_act_offset + 34 - 1]), + .scout(sov[tlb_delayed_act_offset:tlb_delayed_act_offset + 34 - 1]), + .din(tlb_delayed_act_d), + .dout(tlb_delayed_act_q) + ); + // spare latches + + tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) tlb_ctl_spare_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[tlb_ctl_spare_offset:tlb_ctl_spare_offset + 32 - 1]), + .scout(sov[tlb_ctl_spare_offset:tlb_ctl_spare_offset + 32 - 1]), + .din(tlb_ctl_spare_q), + .dout(tlb_ctl_spare_q) + ); + + // non-scannable timing latches + tri_regk #(.WIDTH(11), .INIT(0), .NEEDS_SRESET(0)) tlb_resv0_tag1_match_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(xu_mm_ccr2_notlb_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_nsl_force), + .d_mode(lcb_d_mode_dc), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .thold_b(pc_func_slp_nsl_thold_0_b), + .scin(tri_regk_unused_scan[0:10]), + .scout(tri_regk_unused_scan[0:10]), + .din( {tlb_resv0_tag0_lpid_match, tlb_resv0_tag0_pid_match, tlb_resv0_tag0_as_snoop_match, tlb_resv0_tag0_gs_snoop_match, + tlb_resv0_tag0_as_tlbwe_match, tlb_resv0_tag0_gs_tlbwe_match, tlb_resv0_tag0_ind_match, + tlb_resv0_tag0_epn_loc_match, tlb_resv0_tag0_epn_glob_match, + tlb_resv0_tag0_class_match, tlb_seq_snoop_resv} ), + .dout( {tlb_resv0_tag1_lpid_match, tlb_resv0_tag1_pid_match, tlb_resv0_tag1_as_snoop_match, tlb_resv0_tag1_gs_snoop_match, + tlb_resv0_tag1_as_tlbwe_match, tlb_resv0_tag1_gs_tlbwe_match, tlb_resv0_tag1_ind_match, + tlb_resv0_tag1_epn_loc_match, tlb_resv0_tag1_epn_glob_match, + tlb_resv0_tag1_class_match, tlb_seq_snoop_resv_q[0]} ) + ); + +`ifdef MM_THREADS2 + tri_regk #(.WIDTH(11), .INIT(0), .NEEDS_SRESET(0)) tlb_resv1_tag1_match_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(xu_mm_ccr2_notlb_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_nsl_force), + .d_mode(lcb_d_mode_dc), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .thold_b(pc_func_slp_nsl_thold_0_b), + .scin(tri_regk_unused_scan[11:21]), + .scout(tri_regk_unused_scan[11:21]), + .din( {tlb_resv1_tag0_lpid_match, tlb_resv1_tag0_pid_match, tlb_resv1_tag0_as_snoop_match, tlb_resv1_tag0_gs_snoop_match, + tlb_resv1_tag0_as_tlbwe_match, tlb_resv1_tag0_gs_tlbwe_match, tlb_resv1_tag0_ind_match, + tlb_resv1_tag0_epn_loc_match, tlb_resv1_tag0_epn_glob_match, + tlb_resv1_tag0_class_match, tlb_seq_snoop_resv} ), + .dout( {tlb_resv1_tag1_lpid_match, tlb_resv1_tag1_pid_match, tlb_resv1_tag1_as_snoop_match, tlb_resv1_tag1_gs_snoop_match, + tlb_resv1_tag1_as_tlbwe_match, tlb_resv1_tag1_gs_tlbwe_match, tlb_resv1_tag1_ind_match, + tlb_resv1_tag1_epn_loc_match, tlb_resv1_tag1_epn_glob_match, + tlb_resv1_tag1_class_match, tlb_seq_snoop_resv_q[1]} ) + ); +`endif + + //------------------------------------------------ + // thold/sg latches + //------------------------------------------------ + + tri_plat #(.WIDTH(5)) perv_2to1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ccflush_dc), + .din( {pc_func_sl_thold_2, pc_func_slp_sl_thold_2, pc_func_slp_nsl_thold_2, pc_sg_2, pc_fce_2} ), + .q( {pc_func_sl_thold_1, pc_func_slp_sl_thold_1, pc_func_slp_nsl_thold_1, pc_sg_1, pc_fce_1} ) + ); + + tri_plat #(.WIDTH(5)) perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ccflush_dc), + .din( {pc_func_sl_thold_1, pc_func_slp_sl_thold_1, pc_func_slp_nsl_thold_1, pc_sg_1, pc_fce_1} ), + .q( {pc_func_sl_thold_0, pc_func_slp_sl_thold_0, pc_func_slp_nsl_thold_0, pc_sg_0, pc_fce_0} ) + ); + + tri_lcbor perv_lcbor_func_sl( + .clkoff_b(lcb_clkoff_dc_b), + .thold(pc_func_sl_thold_0), + .sg(pc_sg_0), + .act_dis(lcb_act_dis_dc), + .force_t(pc_func_sl_force), + .thold_b(pc_func_sl_thold_0_b) + ); + + tri_lcbor perv_lcbor_func_slp_sl( + .clkoff_b(lcb_clkoff_dc_b), + .thold(pc_func_slp_sl_thold_0), + .sg(pc_sg_0), + .act_dis(lcb_act_dis_dc), + .force_t(pc_func_slp_sl_force), + .thold_b(pc_func_slp_sl_thold_0_b) + ); + + tri_lcbor perv_nsl_lcbor( + .clkoff_b(lcb_clkoff_dc_b), + .thold(pc_func_slp_nsl_thold_0), + .sg(pc_fce_0), + .act_dis(tidn), + .force_t(pc_func_slp_nsl_force), + .thold_b(pc_func_slp_nsl_thold_0_b) + ); + //--------------------------------------------------------------------- + // Scan + //--------------------------------------------------------------------- + assign siv[0:scan_right] = {sov[1:scan_right], ac_func_scan_in}; + assign ac_func_scan_out = sov[0]; + + function Eq; + input a, b; + reg result; + begin + if (a == b) + begin + result = 1'b1; + end + else + begin + result = 1'b0; + end + Eq = result; + end + endfunction + +endmodule diff --git a/dev/verilog/work/mmq_tlb_lrat.v b/dev/verilog/work/mmq_tlb_lrat.v new file mode 100755 index 0000000..bc7330a --- /dev/null +++ b/dev/verilog/work/mmq_tlb_lrat.v @@ -0,0 +1,4088 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +//******************************************************************** +//* TITLE: MMU Logical to Real Translate Logic +//* NAME: mmq_tlb_lrat.vhdl +//********************************************************************* + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" +`include "mmu_a2o.vh" +`define LRAT_TTYPE_WIDTH 5 +`define LRAT_NUM_ENTRY 8 +`define LRAT_NUM_ENTRY_LOG2 3 +`define LRAT_MAXSIZE_LOG2 40 +`define LRAT_MINSIZE_LOG2 20 + + +module mmq_tlb_lrat( + + inout vdd, + inout gnd, + (* pin_data ="PIN_FUNCTION=/G_CLK/" *) + input [0:`NCLK_WIDTH-1] nclk, + + input tc_ccflush_dc, + input tc_scan_dis_dc_b, + input tc_scan_diag_dc, + input tc_lbist_en_dc, + input lcb_d_mode_dc, + input lcb_clkoff_dc_b, + input lcb_act_dis_dc, + input [0:4] lcb_mpw1_dc_b, + input lcb_mpw2_dc_b, + input [0:4] lcb_delay_lclkr_dc, + +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + input ac_func_scan_in, +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + output ac_func_scan_out, + + input pc_sg_2, + input pc_func_sl_thold_2, + input pc_func_slp_sl_thold_2, + + input xu_mm_ccr2_notlb_b, + input [20:23] tlb_delayed_act, + input mmucr2_act_override, + input [0:`MM_THREADS-1] tlb_ctl_ex3_valid, + input [0:`LRAT_TTYPE_WIDTH-1] tlb_ctl_ex3_ttype, + input tlb_ctl_ex3_hv_state, + input [0:`MM_THREADS-1] xu_ex3_flush, + input [0:`MM_THREADS-1] xu_ex4_flush, + input [0:`MM_THREADS-1] xu_ex5_flush, + input [64-`REAL_ADDR_WIDTH:51] tlb_tag0_epn, + input [0:`THDID_WIDTH-1] tlb_tag0_thdid, + input [0:7] tlb_tag0_type, + input [0:`LPID_WIDTH-1] tlb_tag0_lpid, + input [0:3] tlb_tag0_size, + input tlb_tag0_atsel, + input tlb_tag0_addr_cap, + input [0:1] ex6_illeg_instr, // bad tlbre|tlbwe indication from tlb_ctl + input [64-`REAL_ADDR_WIDTH:51] pte_tag0_lpn, + input [0:`LPID_WIDTH-1] pte_tag0_lpid, + input mas0_0_atsel, + input [0:`LRAT_NUM_ENTRY_LOG2-1] mas0_0_esel, + input mas0_0_hes, + input [0:1] mas0_0_wq, + input mas1_0_v, + input [0:3] mas1_0_tsize, + input [64-`REAL_ADDR_WIDTH:51] mas2_0_epn, + input [22:31] mas7_0_rpnu, + input [32:51] mas3_0_rpnl, + input [0:`LPID_WIDTH-1] mas8_0_tlpid, + input mmucr3_0_x, +`ifdef MM_THREADS2 + input mas0_1_atsel, + input [0:`LRAT_NUM_ENTRY_LOG2-1] mas0_1_esel, + input mas0_1_hes, + input [0:1] mas0_1_wq, + input mas1_1_v, + input [0:3] mas1_1_tsize, + input [64-`REAL_ADDR_WIDTH:51] mas2_1_epn, + input [22:31] mas7_1_rpnu, + input [32:51] mas3_1_rpnl, + input [0:`LPID_WIDTH-1] mas8_1_tlpid, + input mmucr3_1_x, +`endif + + output lrat_mmucr3_x, + output [0:2] lrat_mas0_esel, + output lrat_mas1_v, + output [0:3] lrat_mas1_tsize, + output [0:51] lrat_mas2_epn, + output [32:51] lrat_mas3_rpnl, + output [22:31] lrat_mas7_rpnu, + output [0:`LPID_WIDTH-1] lrat_mas8_tlpid, + output lrat_mas_tlbre, + output lrat_mas_tlbsx_hit, + output lrat_mas_tlbsx_miss, + output [0:`MM_THREADS-1] lrat_mas_thdid, + output [64-`REAL_ADDR_WIDTH:51] lrat_tag3_lpn, + output [64-`REAL_ADDR_WIDTH:51] lrat_tag3_rpn, + output [0:3] lrat_tag3_hit_status, + output [0:`LRAT_NUM_ENTRY_LOG2-1] lrat_tag3_hit_entry, + output [64-`REAL_ADDR_WIDTH:51] lrat_tag4_lpn, + output [64-`REAL_ADDR_WIDTH:51] lrat_tag4_rpn, + output [0:3] lrat_tag4_hit_status, + output [0:`LRAT_NUM_ENTRY_LOG2-1] lrat_tag4_hit_entry, + + output lrat_dbg_tag1_addr_enable, + output [0:7] lrat_dbg_tag2_matchline_q, + output lrat_dbg_entry0_addr_match, + output lrat_dbg_entry0_lpid_match, + output lrat_dbg_entry0_entry_v, + output lrat_dbg_entry0_entry_x, + output [0:3] lrat_dbg_entry0_size, + output lrat_dbg_entry1_addr_match, + output lrat_dbg_entry1_lpid_match, + output lrat_dbg_entry1_entry_v, + output lrat_dbg_entry1_entry_x, + output [0:3] lrat_dbg_entry1_size, + output lrat_dbg_entry2_addr_match, + output lrat_dbg_entry2_lpid_match, + output lrat_dbg_entry2_entry_v, + output lrat_dbg_entry2_entry_x, + output [0:3] lrat_dbg_entry2_size, + output lrat_dbg_entry3_addr_match, + output lrat_dbg_entry3_lpid_match, + output lrat_dbg_entry3_entry_v, + output lrat_dbg_entry3_entry_x, + output [0:3] lrat_dbg_entry3_size, + output lrat_dbg_entry4_addr_match, + output lrat_dbg_entry4_lpid_match, + output lrat_dbg_entry4_entry_v, + output lrat_dbg_entry4_entry_x, + output [0:3] lrat_dbg_entry4_size, + output lrat_dbg_entry5_addr_match, + output lrat_dbg_entry5_lpid_match, + output lrat_dbg_entry5_entry_v, + output lrat_dbg_entry5_entry_x, + output [0:3] lrat_dbg_entry5_size, + output lrat_dbg_entry6_addr_match, + output lrat_dbg_entry6_lpid_match, + output lrat_dbg_entry6_entry_v, + output lrat_dbg_entry6_entry_x, + output [0:3] lrat_dbg_entry6_size, + output lrat_dbg_entry7_addr_match, + output lrat_dbg_entry7_lpid_match, + output lrat_dbg_entry7_entry_v, + output lrat_dbg_entry7_entry_x, + output [0:3] lrat_dbg_entry7_size + +); + + parameter MMU_Mode_Value = 1'b0; + parameter [0:3] TLB_PgSize_1GB = 4'b1010; + parameter [0:3] TLB_PgSize_256MB = 4'b1001; + parameter [0:3] TLB_PgSize_16MB = 4'b0111; + parameter [0:3] TLB_PgSize_1MB = 4'b0101; + parameter [0:3] TLB_PgSize_64KB = 4'b0011; + parameter [0:3] TLB_PgSize_4KB = 4'b0001; + parameter [0:3] LRAT_PgSize_1TB = 4'b1111; + parameter [0:3] LRAT_PgSize_256GB = 4'b1110; + parameter [0:3] LRAT_PgSize_16GB = 4'b1100; + parameter [0:3] LRAT_PgSize_4GB = 4'b1011; + parameter [0:3] LRAT_PgSize_1GB = 4'b1010; + parameter [0:3] LRAT_PgSize_256MB = 4'b1001; + parameter [0:3] LRAT_PgSize_16MB = 4'b0111; + parameter [0:3] LRAT_PgSize_1MB = 4'b0101; + parameter LRAT_PgSize_1TB_log2 = 40; + parameter LRAT_PgSize_256GB_log2 = 38; + parameter LRAT_PgSize_16GB_log2 = 34; + parameter LRAT_PgSize_4GB_log2 = 32; + parameter LRAT_PgSize_1GB_log2 = 30; + parameter LRAT_PgSize_256MB_log2 = 28; + parameter LRAT_PgSize_16MB_log2 = 24; + parameter LRAT_PgSize_1MB_log2 = 20; + // derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload + parameter lrat_tagpos_type = 0; + parameter lrat_tagpos_type_derat = lrat_tagpos_type; + parameter lrat_tagpos_type_ierat = lrat_tagpos_type + 1; + parameter lrat_tagpos_type_tlbsx = lrat_tagpos_type + 2; + parameter lrat_tagpos_type_tlbsrx = lrat_tagpos_type + 3; + parameter lrat_tagpos_type_snoop = lrat_tagpos_type + 4; + parameter lrat_tagpos_type_tlbre = lrat_tagpos_type + 5; + parameter lrat_tagpos_type_tlbwe = lrat_tagpos_type + 6; + parameter lrat_tagpos_type_ptereload = lrat_tagpos_type + 7; + + // scan path constants + parameter ex4_valid_offset = 0; + parameter ex4_ttype_offset = ex4_valid_offset + `MM_THREADS; + parameter ex4_hv_state_offset = ex4_ttype_offset + `LRAT_TTYPE_WIDTH; + parameter ex5_valid_offset = ex4_hv_state_offset + 1; + parameter ex5_ttype_offset = ex5_valid_offset + `MM_THREADS; + parameter ex5_esel_offset = ex5_ttype_offset + `LRAT_TTYPE_WIDTH; + parameter ex5_atsel_offset = ex5_esel_offset + 3; + parameter ex5_wq_offset = ex5_atsel_offset + 1; + parameter ex5_hes_offset = ex5_wq_offset + 2; + parameter ex5_hv_state_offset = ex5_hes_offset + 1; + parameter ex6_valid_offset = ex5_hv_state_offset + 1; + parameter ex6_ttype_offset = ex6_valid_offset + `MM_THREADS; + parameter ex6_esel_offset = ex6_ttype_offset + `LRAT_TTYPE_WIDTH; + parameter ex6_atsel_offset = ex6_esel_offset + 3; + parameter ex6_wq_offset = ex6_atsel_offset + 1; + parameter ex6_hes_offset = ex6_wq_offset + 2; + parameter ex6_hv_state_offset = ex6_hes_offset + 1; + parameter lrat_tag1_lpn_offset = ex6_hv_state_offset + 1; + parameter lrat_tag2_lpn_offset = lrat_tag1_lpn_offset + `RPN_WIDTH; + parameter lrat_tag3_lpn_offset = lrat_tag2_lpn_offset + `RPN_WIDTH; + parameter lrat_tag3_rpn_offset = lrat_tag3_lpn_offset + `RPN_WIDTH; + parameter lrat_tag4_lpn_offset = lrat_tag3_rpn_offset + `RPN_WIDTH; + parameter lrat_tag4_rpn_offset = lrat_tag4_lpn_offset + `RPN_WIDTH; + parameter lrat_tag1_lpid_offset = lrat_tag4_rpn_offset + `RPN_WIDTH; + parameter lrat_tag1_size_offset = lrat_tag1_lpid_offset + `LPID_WIDTH; + parameter lrat_tag2_size_offset = lrat_tag1_size_offset + 4; + parameter lrat_tag2_entry_size_offset = lrat_tag2_size_offset + 4; + parameter lrat_tag2_matchline_offset = lrat_tag2_entry_size_offset + 4; + parameter lrat_tag3_hit_status_offset = lrat_tag2_matchline_offset + `LRAT_NUM_ENTRY; + parameter lrat_tag3_hit_entry_offset = lrat_tag3_hit_status_offset + 4; + parameter lrat_tag4_hit_status_offset = lrat_tag3_hit_entry_offset + `LRAT_NUM_ENTRY_LOG2; + parameter lrat_tag4_hit_entry_offset = lrat_tag4_hit_status_offset + 4; + parameter tlb_addr_cap_offset = lrat_tag4_hit_entry_offset + `LRAT_NUM_ENTRY_LOG2; + parameter lrat_entry0_lpn_offset = tlb_addr_cap_offset + 2; + parameter lrat_entry0_rpn_offset = lrat_entry0_lpn_offset + `REAL_ADDR_WIDTH - `LRAT_MINSIZE_LOG2; + parameter lrat_entry0_lpid_offset = lrat_entry0_rpn_offset + `REAL_ADDR_WIDTH - `LRAT_MINSIZE_LOG2; + parameter lrat_entry0_size_offset = lrat_entry0_lpid_offset + `LPID_WIDTH; + parameter lrat_entry0_cmpmask_offset = lrat_entry0_size_offset + 4; + parameter lrat_entry0_xbitmask_offset = lrat_entry0_cmpmask_offset + 7; + parameter lrat_entry0_xbit_offset = lrat_entry0_xbitmask_offset + 7; + parameter lrat_entry0_valid_offset = lrat_entry0_xbit_offset + 1; + parameter lrat_entry1_lpn_offset = lrat_entry0_valid_offset + 1; + parameter lrat_entry1_rpn_offset = lrat_entry1_lpn_offset + `REAL_ADDR_WIDTH - `LRAT_MINSIZE_LOG2; + parameter lrat_entry1_lpid_offset = lrat_entry1_rpn_offset + `REAL_ADDR_WIDTH - `LRAT_MINSIZE_LOG2; + parameter lrat_entry1_size_offset = lrat_entry1_lpid_offset + `LPID_WIDTH; + parameter lrat_entry1_cmpmask_offset = lrat_entry1_size_offset + 4; + parameter lrat_entry1_xbitmask_offset = lrat_entry1_cmpmask_offset + 7; + parameter lrat_entry1_xbit_offset = lrat_entry1_xbitmask_offset + 7; + parameter lrat_entry1_valid_offset = lrat_entry1_xbit_offset + 1; + parameter lrat_entry2_lpn_offset = lrat_entry1_valid_offset + 1; + parameter lrat_entry2_rpn_offset = lrat_entry2_lpn_offset + `REAL_ADDR_WIDTH - `LRAT_MINSIZE_LOG2; + parameter lrat_entry2_lpid_offset = lrat_entry2_rpn_offset + `REAL_ADDR_WIDTH - `LRAT_MINSIZE_LOG2; + parameter lrat_entry2_size_offset = lrat_entry2_lpid_offset + `LPID_WIDTH; + parameter lrat_entry2_cmpmask_offset = lrat_entry2_size_offset + 4; + parameter lrat_entry2_xbitmask_offset = lrat_entry2_cmpmask_offset + 7; + parameter lrat_entry2_xbit_offset = lrat_entry2_xbitmask_offset + 7; + parameter lrat_entry2_valid_offset = lrat_entry2_xbit_offset + 1; + parameter lrat_entry3_lpn_offset = lrat_entry2_valid_offset + 1; + parameter lrat_entry3_rpn_offset = lrat_entry3_lpn_offset + `REAL_ADDR_WIDTH - `LRAT_MINSIZE_LOG2; + parameter lrat_entry3_lpid_offset = lrat_entry3_rpn_offset + `REAL_ADDR_WIDTH - `LRAT_MINSIZE_LOG2; + parameter lrat_entry3_size_offset = lrat_entry3_lpid_offset + `LPID_WIDTH; + parameter lrat_entry3_cmpmask_offset = lrat_entry3_size_offset + 4; + parameter lrat_entry3_xbitmask_offset = lrat_entry3_cmpmask_offset + 7; + parameter lrat_entry3_xbit_offset = lrat_entry3_xbitmask_offset + 7; + parameter lrat_entry3_valid_offset = lrat_entry3_xbit_offset + 1; + parameter lrat_entry4_lpn_offset = lrat_entry3_valid_offset + 1; + parameter lrat_entry4_rpn_offset = lrat_entry4_lpn_offset + `REAL_ADDR_WIDTH - `LRAT_MINSIZE_LOG2; + parameter lrat_entry4_lpid_offset = lrat_entry4_rpn_offset + `REAL_ADDR_WIDTH - `LRAT_MINSIZE_LOG2; + parameter lrat_entry4_size_offset = lrat_entry4_lpid_offset + `LPID_WIDTH; + parameter lrat_entry4_cmpmask_offset = lrat_entry4_size_offset + 4; + parameter lrat_entry4_xbitmask_offset = lrat_entry4_cmpmask_offset + 7; + parameter lrat_entry4_xbit_offset = lrat_entry4_xbitmask_offset + 7; + parameter lrat_entry4_valid_offset = lrat_entry4_xbit_offset + 1; + parameter lrat_entry5_lpn_offset = lrat_entry4_valid_offset + 1; + parameter lrat_entry5_rpn_offset = lrat_entry5_lpn_offset + `REAL_ADDR_WIDTH - `LRAT_MINSIZE_LOG2; + parameter lrat_entry5_lpid_offset = lrat_entry5_rpn_offset + `REAL_ADDR_WIDTH - `LRAT_MINSIZE_LOG2; + parameter lrat_entry5_size_offset = lrat_entry5_lpid_offset + `LPID_WIDTH; + parameter lrat_entry5_cmpmask_offset = lrat_entry5_size_offset + 4; + parameter lrat_entry5_xbitmask_offset = lrat_entry5_cmpmask_offset + 7; + parameter lrat_entry5_xbit_offset = lrat_entry5_xbitmask_offset + 7; + parameter lrat_entry5_valid_offset = lrat_entry5_xbit_offset + 1; + parameter lrat_entry6_lpn_offset = lrat_entry5_valid_offset + 1; + parameter lrat_entry6_rpn_offset = lrat_entry6_lpn_offset + `REAL_ADDR_WIDTH - `LRAT_MINSIZE_LOG2; + parameter lrat_entry6_lpid_offset = lrat_entry6_rpn_offset + `REAL_ADDR_WIDTH - `LRAT_MINSIZE_LOG2; + parameter lrat_entry6_size_offset = lrat_entry6_lpid_offset + `LPID_WIDTH; + parameter lrat_entry6_cmpmask_offset = lrat_entry6_size_offset + 4; + parameter lrat_entry6_xbitmask_offset = lrat_entry6_cmpmask_offset + 7; + parameter lrat_entry6_xbit_offset = lrat_entry6_xbitmask_offset + 7; + parameter lrat_entry6_valid_offset = lrat_entry6_xbit_offset + 1; + parameter lrat_entry7_lpn_offset = lrat_entry6_valid_offset + 1; + parameter lrat_entry7_rpn_offset = lrat_entry7_lpn_offset + `REAL_ADDR_WIDTH - `LRAT_MINSIZE_LOG2; + parameter lrat_entry7_lpid_offset = lrat_entry7_rpn_offset + `REAL_ADDR_WIDTH - `LRAT_MINSIZE_LOG2; + parameter lrat_entry7_size_offset = lrat_entry7_lpid_offset + `LPID_WIDTH; + parameter lrat_entry7_cmpmask_offset = lrat_entry7_size_offset + 4; + parameter lrat_entry7_xbitmask_offset = lrat_entry7_cmpmask_offset + 7; + parameter lrat_entry7_xbit_offset = lrat_entry7_xbitmask_offset + 7; + parameter lrat_entry7_valid_offset = lrat_entry7_xbit_offset + 1; + parameter lrat_datain_lpn_offset = lrat_entry7_valid_offset + 1; + parameter lrat_datain_rpn_offset = lrat_datain_lpn_offset + `REAL_ADDR_WIDTH - `LRAT_MINSIZE_LOG2; + parameter lrat_datain_lpid_offset = lrat_datain_rpn_offset + `REAL_ADDR_WIDTH - `LRAT_MINSIZE_LOG2; + parameter lrat_datain_size_offset = lrat_datain_lpid_offset + `LPID_WIDTH; + parameter lrat_datain_xbit_offset = lrat_datain_size_offset + 4; + parameter lrat_datain_valid_offset = lrat_datain_xbit_offset + 1; + parameter lrat_mas1_v_offset = lrat_datain_valid_offset + 1; + parameter lrat_mas1_tsize_offset = lrat_mas1_v_offset + 1; + parameter lrat_mas2_epn_offset = lrat_mas1_tsize_offset + 4; + parameter lrat_mas3_rpnl_offset = lrat_mas2_epn_offset + `RPN_WIDTH; + parameter lrat_mas7_rpnu_offset = lrat_mas3_rpnl_offset + 20; + parameter lrat_mas8_tlpid_offset = lrat_mas7_rpnu_offset + 10; + parameter lrat_mas_tlbre_offset = lrat_mas8_tlpid_offset + `LPID_WIDTH; + parameter lrat_mas_tlbsx_hit_offset = lrat_mas_tlbre_offset + 1; + parameter lrat_mas_tlbsx_miss_offset = lrat_mas_tlbsx_hit_offset + 1; + parameter lrat_mas_thdid_offset = lrat_mas_tlbsx_miss_offset + 1; + parameter lrat_mmucr3_x_offset = lrat_mas_thdid_offset + `MM_THREADS; + parameter lrat_entry_act_offset = lrat_mmucr3_x_offset + 1; + parameter lrat_mas_act_offset = lrat_entry_act_offset + 8; + parameter lrat_datain_act_offset = lrat_mas_act_offset + 3; + parameter spare_offset = lrat_datain_act_offset + 2; + parameter scan_right = spare_offset + 64 - 1; + + parameter const_lrat_maxsize_log2 = `REAL_ADDR_WIDTH - 2; + +`ifdef MM_THREADS2 + parameter BUGSP_MM_THREADS = 2; +`else + parameter BUGSP_MM_THREADS = 1; +`endif + + // Latch signals + wire [0:`MM_THREADS-1] ex4_valid_d; + wire [0:`MM_THREADS-1] ex4_valid_q; + wire [0:`LRAT_TTYPE_WIDTH-1] ex4_ttype_d; + wire [0:`LRAT_TTYPE_WIDTH-1] ex4_ttype_q; + wire ex4_hv_state_d; + wire ex4_hv_state_q; + wire [0:`MM_THREADS-1] ex5_valid_d; + wire [0:`MM_THREADS-1] ex5_valid_q; + wire [0:`LRAT_TTYPE_WIDTH-1] ex5_ttype_d; + wire [0:`LRAT_TTYPE_WIDTH-1] ex5_ttype_q; + wire [0:`LRAT_NUM_ENTRY_LOG2-1] ex5_esel_d; + wire [0:`LRAT_NUM_ENTRY_LOG2-1] ex5_esel_q; + wire ex5_atsel_d; + wire ex5_atsel_q; + wire ex5_hes_d; + wire ex5_hes_q; + wire [0:1] ex5_wq_d; + wire [0:1] ex5_wq_q; + wire ex5_hv_state_d; + wire ex5_hv_state_q; + wire [0:`MM_THREADS-1] ex6_valid_d; + wire [0:`MM_THREADS-1] ex6_valid_q; + wire [0:`LRAT_TTYPE_WIDTH-1] ex6_ttype_d; + wire [0:`LRAT_TTYPE_WIDTH-1] ex6_ttype_q; + wire [0:`LRAT_NUM_ENTRY_LOG2-1] ex6_esel_d; + wire [0:`LRAT_NUM_ENTRY_LOG2-1] ex6_esel_q; + wire ex6_atsel_d; + wire ex6_atsel_q; + wire ex6_hes_d; + wire ex6_hes_q; + wire [0:1] ex6_wq_d; + wire [0:1] ex6_wq_q; + wire ex6_hv_state_d; + wire ex6_hv_state_q; + wire [64-`REAL_ADDR_WIDTH:51] lrat_tag1_lpn_d; + wire [64-`REAL_ADDR_WIDTH:51] lrat_tag1_lpn_q; + wire [64-`REAL_ADDR_WIDTH:51] lrat_tag2_lpn_d; + wire [64-`REAL_ADDR_WIDTH:51] lrat_tag2_lpn_q; + wire [64-`REAL_ADDR_WIDTH:51] lrat_tag3_lpn_d; + wire [64-`REAL_ADDR_WIDTH:51] lrat_tag3_lpn_q; + wire [64-`REAL_ADDR_WIDTH:51] lrat_tag3_rpn_d; + wire [64-`REAL_ADDR_WIDTH:51] lrat_tag3_rpn_q; + wire [64-`REAL_ADDR_WIDTH:51] lrat_tag4_lpn_d; + wire [64-`REAL_ADDR_WIDTH:51] lrat_tag4_lpn_q; + wire [64-`REAL_ADDR_WIDTH:51] lrat_tag4_rpn_d; + wire [64-`REAL_ADDR_WIDTH:51] lrat_tag4_rpn_q; + wire [0:`LPID_WIDTH-1] lrat_tag1_lpid_d; + wire [0:`LPID_WIDTH-1] lrat_tag1_lpid_q; + wire [0:`LRAT_NUM_ENTRY-1] lrat_tag2_matchline_d; + wire [0:`LRAT_NUM_ENTRY-1] lrat_tag2_matchline_q; + wire [0:3] lrat_tag1_size_d; + wire [0:3] lrat_tag1_size_q; + wire [0:3] lrat_tag2_size_d; + wire [0:3] lrat_tag2_size_q; + wire [0:3] lrat_tag2_entry_size_d; + wire [0:3] lrat_tag2_entry_size_q; + wire [0:3] lrat_tag3_hit_status_d; + wire [0:3] lrat_tag3_hit_status_q; + wire [0:`LRAT_NUM_ENTRY_LOG2-1] lrat_tag3_hit_entry_d; + wire [0:`LRAT_NUM_ENTRY_LOG2-1] lrat_tag3_hit_entry_q; + wire [0:3] lrat_tag4_hit_status_d; + wire [0:3] lrat_tag4_hit_status_q; + wire [0:`LRAT_NUM_ENTRY_LOG2-1] lrat_tag4_hit_entry_d; + wire [0:`LRAT_NUM_ENTRY_LOG2-1] lrat_tag4_hit_entry_q; + wire [1:2] tlb_addr_cap_d; + wire [1:2] tlb_addr_cap_q; + wire lrat_entry0_wren; + wire [64-`REAL_ADDR_WIDTH:64-`LRAT_MINSIZE_LOG2-1] lrat_entry0_lpn_d; + wire [64-`REAL_ADDR_WIDTH:64-`LRAT_MINSIZE_LOG2-1] lrat_entry0_lpn_q; + wire [64-`REAL_ADDR_WIDTH:64-`LRAT_MINSIZE_LOG2-1] lrat_entry0_rpn_d; + wire [64-`REAL_ADDR_WIDTH:64-`LRAT_MINSIZE_LOG2-1] lrat_entry0_rpn_q; + wire [0:`LPID_WIDTH-1] lrat_entry0_lpid_d; + wire [0:`LPID_WIDTH-1] lrat_entry0_lpid_q; + wire [0:3] lrat_entry0_size_d; + wire [0:3] lrat_entry0_size_q; + wire [0:6] lrat_entry0_cmpmask_d; + wire [0:6] lrat_entry0_cmpmask_q; + wire [0:6] lrat_entry0_xbitmask_d; + wire [0:6] lrat_entry0_xbitmask_q; + wire lrat_entry0_xbit_d; + wire lrat_entry0_xbit_q; + wire lrat_entry0_valid_d; + wire lrat_entry0_valid_q; + wire lrat_entry1_wren; + wire [64-`REAL_ADDR_WIDTH:64-`LRAT_MINSIZE_LOG2-1] lrat_entry1_lpn_d; + wire [64-`REAL_ADDR_WIDTH:64-`LRAT_MINSIZE_LOG2-1] lrat_entry1_lpn_q; + wire [64-`REAL_ADDR_WIDTH:64-`LRAT_MINSIZE_LOG2-1] lrat_entry1_rpn_d; + wire [64-`REAL_ADDR_WIDTH:64-`LRAT_MINSIZE_LOG2-1] lrat_entry1_rpn_q; + wire [0:`LPID_WIDTH-1] lrat_entry1_lpid_d; + wire [0:`LPID_WIDTH-1] lrat_entry1_lpid_q; + wire [0:3] lrat_entry1_size_d; + wire [0:3] lrat_entry1_size_q; + wire [0:6] lrat_entry1_cmpmask_d; + wire [0:6] lrat_entry1_cmpmask_q; + wire [0:6] lrat_entry1_xbitmask_d; + wire [0:6] lrat_entry1_xbitmask_q; + wire lrat_entry1_xbit_d; + wire lrat_entry1_xbit_q; + wire lrat_entry1_valid_d; + wire lrat_entry1_valid_q; + wire lrat_entry2_wren; + wire [64-`REAL_ADDR_WIDTH:64-`LRAT_MINSIZE_LOG2-1] lrat_entry2_lpn_d; + wire [64-`REAL_ADDR_WIDTH:64-`LRAT_MINSIZE_LOG2-1] lrat_entry2_lpn_q; + wire [64-`REAL_ADDR_WIDTH:64-`LRAT_MINSIZE_LOG2-1] lrat_entry2_rpn_d; + wire [64-`REAL_ADDR_WIDTH:64-`LRAT_MINSIZE_LOG2-1] lrat_entry2_rpn_q; + wire [0:`LPID_WIDTH-1] lrat_entry2_lpid_d; + wire [0:`LPID_WIDTH-1] lrat_entry2_lpid_q; + wire [0:3] lrat_entry2_size_d; + wire [0:3] lrat_entry2_size_q; + wire [0:6] lrat_entry2_cmpmask_d; + wire [0:6] lrat_entry2_cmpmask_q; + wire [0:6] lrat_entry2_xbitmask_d; + wire [0:6] lrat_entry2_xbitmask_q; + wire lrat_entry2_xbit_d; + wire lrat_entry2_xbit_q; + wire lrat_entry2_valid_d; + wire lrat_entry2_valid_q; + wire lrat_entry3_wren; + wire [64-`REAL_ADDR_WIDTH:64-`LRAT_MINSIZE_LOG2-1] lrat_entry3_lpn_d; + wire [64-`REAL_ADDR_WIDTH:64-`LRAT_MINSIZE_LOG2-1] lrat_entry3_lpn_q; + wire [64-`REAL_ADDR_WIDTH:64-`LRAT_MINSIZE_LOG2-1] lrat_entry3_rpn_d; + wire [64-`REAL_ADDR_WIDTH:64-`LRAT_MINSIZE_LOG2-1] lrat_entry3_rpn_q; + wire [0:`LPID_WIDTH-1] lrat_entry3_lpid_d; + wire [0:`LPID_WIDTH-1] lrat_entry3_lpid_q; + wire [0:3] lrat_entry3_size_d; + wire [0:3] lrat_entry3_size_q; + wire [0:6] lrat_entry3_cmpmask_d; + wire [0:6] lrat_entry3_cmpmask_q; + wire [0:6] lrat_entry3_xbitmask_d; + wire [0:6] lrat_entry3_xbitmask_q; + wire lrat_entry3_xbit_d; + wire lrat_entry3_xbit_q; + wire lrat_entry3_valid_d; + wire lrat_entry3_valid_q; + wire lrat_entry4_wren; + wire [64-`REAL_ADDR_WIDTH:64-`LRAT_MINSIZE_LOG2-1] lrat_entry4_lpn_d; + wire [64-`REAL_ADDR_WIDTH:64-`LRAT_MINSIZE_LOG2-1] lrat_entry4_lpn_q; + wire [64-`REAL_ADDR_WIDTH:64-`LRAT_MINSIZE_LOG2-1] lrat_entry4_rpn_d; + wire [64-`REAL_ADDR_WIDTH:64-`LRAT_MINSIZE_LOG2-1] lrat_entry4_rpn_q; + wire [0:`LPID_WIDTH-1] lrat_entry4_lpid_d; + wire [0:`LPID_WIDTH-1] lrat_entry4_lpid_q; + wire [0:3] lrat_entry4_size_d; + wire [0:3] lrat_entry4_size_q; + wire [0:6] lrat_entry4_cmpmask_d; + wire [0:6] lrat_entry4_cmpmask_q; + wire [0:6] lrat_entry4_xbitmask_d; + wire [0:6] lrat_entry4_xbitmask_q; + wire lrat_entry4_xbit_d; + wire lrat_entry4_xbit_q; + wire lrat_entry4_valid_d; + wire lrat_entry4_valid_q; + wire lrat_entry5_wren; + wire [64-`REAL_ADDR_WIDTH:64-`LRAT_MINSIZE_LOG2-1] lrat_entry5_lpn_d; + wire [64-`REAL_ADDR_WIDTH:64-`LRAT_MINSIZE_LOG2-1] lrat_entry5_lpn_q; + wire [64-`REAL_ADDR_WIDTH:64-`LRAT_MINSIZE_LOG2-1] lrat_entry5_rpn_d; + wire [64-`REAL_ADDR_WIDTH:64-`LRAT_MINSIZE_LOG2-1] lrat_entry5_rpn_q; + wire [0:`LPID_WIDTH-1] lrat_entry5_lpid_d; + wire [0:`LPID_WIDTH-1] lrat_entry5_lpid_q; + wire [0:3] lrat_entry5_size_d; + wire [0:3] lrat_entry5_size_q; + wire [0:6] lrat_entry5_cmpmask_d; + wire [0:6] lrat_entry5_cmpmask_q; + wire [0:6] lrat_entry5_xbitmask_d; + wire [0:6] lrat_entry5_xbitmask_q; + wire lrat_entry5_xbit_d; + wire lrat_entry5_xbit_q; + wire lrat_entry5_valid_d; + wire lrat_entry5_valid_q; + wire lrat_entry6_wren; + wire [64-`REAL_ADDR_WIDTH:64-`LRAT_MINSIZE_LOG2-1] lrat_entry6_lpn_d; + wire [64-`REAL_ADDR_WIDTH:64-`LRAT_MINSIZE_LOG2-1] lrat_entry6_lpn_q; + wire [64-`REAL_ADDR_WIDTH:64-`LRAT_MINSIZE_LOG2-1] lrat_entry6_rpn_d; + wire [64-`REAL_ADDR_WIDTH:64-`LRAT_MINSIZE_LOG2-1] lrat_entry6_rpn_q; + wire [0:`LPID_WIDTH-1] lrat_entry6_lpid_d; + wire [0:`LPID_WIDTH-1] lrat_entry6_lpid_q; + wire [0:3] lrat_entry6_size_d; + wire [0:3] lrat_entry6_size_q; + wire [0:6] lrat_entry6_cmpmask_d; + wire [0:6] lrat_entry6_cmpmask_q; + wire [0:6] lrat_entry6_xbitmask_d; + wire [0:6] lrat_entry6_xbitmask_q; + wire lrat_entry6_xbit_d; + wire lrat_entry6_xbit_q; + wire lrat_entry6_valid_d; + wire lrat_entry6_valid_q; + wire lrat_entry7_wren; + wire [64-`REAL_ADDR_WIDTH:64-`LRAT_MINSIZE_LOG2-1] lrat_entry7_lpn_d; + wire [64-`REAL_ADDR_WIDTH:64-`LRAT_MINSIZE_LOG2-1] lrat_entry7_lpn_q; + wire [64-`REAL_ADDR_WIDTH:64-`LRAT_MINSIZE_LOG2-1] lrat_entry7_rpn_d; + wire [64-`REAL_ADDR_WIDTH:64-`LRAT_MINSIZE_LOG2-1] lrat_entry7_rpn_q; + wire [0:`LPID_WIDTH-1] lrat_entry7_lpid_d; + wire [0:`LPID_WIDTH-1] lrat_entry7_lpid_q; + wire [0:3] lrat_entry7_size_d; + wire [0:3] lrat_entry7_size_q; + wire [0:6] lrat_entry7_cmpmask_d; + wire [0:6] lrat_entry7_cmpmask_q; + wire [0:6] lrat_entry7_xbitmask_d; + wire [0:6] lrat_entry7_xbitmask_q; + wire lrat_entry7_xbit_d; + wire lrat_entry7_xbit_q; + wire lrat_entry7_valid_d; + wire lrat_entry7_valid_q; + wire [64-`REAL_ADDR_WIDTH:64-`LRAT_MINSIZE_LOG2-1] lrat_datain_lpn_d; + wire [64-`REAL_ADDR_WIDTH:64-`LRAT_MINSIZE_LOG2-1] lrat_datain_lpn_q; + wire [64-`REAL_ADDR_WIDTH:64-`LRAT_MINSIZE_LOG2-1] lrat_datain_rpn_d; + wire [64-`REAL_ADDR_WIDTH:64-`LRAT_MINSIZE_LOG2-1] lrat_datain_rpn_q; + wire [0:`LPID_WIDTH-1] lrat_datain_lpid_d; + wire [0:`LPID_WIDTH-1] lrat_datain_lpid_q; + wire [0:3] lrat_datain_size_d; + wire [0:3] lrat_datain_size_q; + wire lrat_datain_xbit_d; + wire lrat_datain_xbit_q; + wire lrat_datain_valid_d; + wire lrat_datain_valid_q; + wire lrat_mas1_v_d; + wire lrat_mas1_v_q; + wire [0:3] lrat_mas1_tsize_d; + wire [0:3] lrat_mas1_tsize_q; + wire [64-`REAL_ADDR_WIDTH:51] lrat_mas2_epn_d; + wire [64-`REAL_ADDR_WIDTH:51] lrat_mas2_epn_q; + wire [32:51] lrat_mas3_rpnl_d; + wire [32:51] lrat_mas3_rpnl_q; + wire [22:31] lrat_mas7_rpnu_d; + wire [22:31] lrat_mas7_rpnu_q; + wire [0:`LPID_WIDTH-1] lrat_mas8_tlpid_d; + wire [0:`LPID_WIDTH-1] lrat_mas8_tlpid_q; + wire lrat_mas_tlbre_d; + wire lrat_mas_tlbre_q; + wire lrat_mas_tlbsx_hit_d; + wire lrat_mas_tlbsx_hit_q; + wire lrat_mas_tlbsx_miss_d; + wire lrat_mas_tlbsx_miss_q; + wire [0:`MM_THREADS-1] lrat_mas_thdid_d; + wire [0:`MM_THREADS-1] lrat_mas_thdid_q; + wire lrat_mmucr3_x_d; + wire lrat_mmucr3_x_q; + wire [0:7] lrat_entry_act_d; + wire [0:7] lrat_entry_act_q; + wire [0:2] lrat_mas_act_d; + wire [0:2] lrat_mas_act_q; + wire [0:1] lrat_datain_act_d; + wire [0:1] lrat_datain_act_q; + wire [0:63] spare_q; + // Logic signals + wire multihit; + wire addr_enable; + wire lpid_enable; + wire lrat_supp_pgsize; + wire lrat_tag2_size_gt_entry_size; + wire [0:`LRAT_NUM_ENTRY-1] lrat_tag1_matchline; + wire lrat_entry0_addr_match; + wire lrat_entry0_lpid_match; + wire lrat_entry1_addr_match; + wire lrat_entry1_lpid_match; + wire lrat_entry2_addr_match; + wire lrat_entry2_lpid_match; + wire lrat_entry3_addr_match; + wire lrat_entry3_lpid_match; + wire lrat_entry4_addr_match; + wire lrat_entry4_lpid_match; + wire lrat_entry5_addr_match; + wire lrat_entry5_lpid_match; + wire lrat_entry6_addr_match; + wire lrat_entry6_lpid_match; + wire lrat_entry7_addr_match; + wire lrat_entry7_lpid_match; + + wire lrat_datain_size_gte_1TB; + wire lrat_datain_size_gte_256GB; + wire lrat_datain_size_gte_16GB; + wire lrat_datain_size_gte_4GB; + wire lrat_datain_size_gte_1GB; + wire lrat_datain_size_gte_256MB; + wire lrat_datain_size_gte_16MB; + + (* analysis_not_referenced="true" *) + wire [0:13] unused_dc; + (* analysis_not_referenced="true" *) + wire [`MM_THREADS:3] unused_dc_threads; + + + // Pervasive + wire pc_sg_1; + wire pc_sg_0; + wire pc_func_sl_thold_1; + wire pc_func_sl_thold_0; + wire pc_func_sl_thold_0_b; + wire pc_func_slp_sl_thold_1; + wire pc_func_slp_sl_thold_0; + wire pc_func_slp_sl_thold_0_b; + wire pc_func_sl_force; + wire pc_func_slp_sl_force; + wire [0:scan_right] siv; + wire [0:scan_right] sov; + + wire tiup; + + //@@ START OF EXECUTABLE CODE FOR MMQ_TLB_LRAT + //begin + //!! Bugspray Include: mmq_tlb_lrat; + + //--------------------------------------------------------------------- + // Logic + //--------------------------------------------------------------------- + assign tiup = 1'b1; + + // tag0 phase signals, tlbwe/re ex2, tlbsx/srx ex3 + assign tlb_addr_cap_d[1] = tlb_tag0_addr_cap & ((tlb_tag0_type[lrat_tagpos_type_tlbsx] & tlb_tag0_atsel) | tlb_tag0_type[lrat_tagpos_type_ptereload] | tlb_tag0_type[lrat_tagpos_type_tlbwe]); + assign lrat_tag1_size_d = (tlb_tag0_addr_cap == 1'b1) ? tlb_tag0_size : + lrat_tag1_size_q; + generate + if (`REAL_ADDR_WIDTH < 33) + begin : gen32_lrat_tag1_lpn + assign lrat_tag1_lpn_d = ((tlb_tag0_addr_cap == 1'b1 & tlb_tag0_type[lrat_tagpos_type_tlbsx] == 1'b1)) ? tlb_tag0_epn[64 - `REAL_ADDR_WIDTH:51] : + ((tlb_tag0_addr_cap == 1'b1 & tlb_tag0_type[lrat_tagpos_type_ptereload] == 1'b1)) ? pte_tag0_lpn[64 - `REAL_ADDR_WIDTH:51] : + ((tlb_tag0_addr_cap == 1'b1 & tlb_tag0_thdid[0] == 1'b1 & tlb_tag0_type[lrat_tagpos_type_tlbwe] == 1'b1)) ? mas3_0_rpnl : +`ifdef MM_THREADS2 + ((tlb_tag0_addr_cap == 1'b1 & tlb_tag0_thdid[1] == 1'b1 & tlb_tag0_type[lrat_tagpos_type_tlbwe] == 1'b1)) ? mas3_1_rpnl : +`endif + lrat_tag1_lpn_q; + end + endgenerate + generate + if (`REAL_ADDR_WIDTH > 32) + begin : gen64_lrat_tag1_lpn + assign lrat_tag1_lpn_d = ((tlb_tag0_addr_cap == 1'b1 & tlb_tag0_type[lrat_tagpos_type_tlbsx] == 1'b1)) ? tlb_tag0_epn[64 - `REAL_ADDR_WIDTH:51] : + ((tlb_tag0_addr_cap == 1'b1 & tlb_tag0_type[lrat_tagpos_type_ptereload] == 1'b1)) ? pte_tag0_lpn[64 - `REAL_ADDR_WIDTH:51] : + ((tlb_tag0_addr_cap == 1'b1 & tlb_tag0_thdid[0] == 1'b1 & tlb_tag0_type[lrat_tagpos_type_tlbwe] == 1'b1)) ? {mas7_0_rpnu[64 - `REAL_ADDR_WIDTH:31], mas3_0_rpnl} : +`ifdef MM_THREADS2 + ((tlb_tag0_addr_cap == 1'b1 & tlb_tag0_thdid[1] == 1'b1 & tlb_tag0_type[lrat_tagpos_type_tlbwe] == 1'b1)) ? {mas7_1_rpnu[64 - `REAL_ADDR_WIDTH:31], mas3_1_rpnl} : +`endif + lrat_tag1_lpn_q; + end + endgenerate + assign lrat_tag1_lpid_d = ((tlb_tag0_addr_cap == 1'b1 & tlb_tag0_type[lrat_tagpos_type_tlbsx] == 1'b1)) ? tlb_tag0_lpid : + ((tlb_tag0_addr_cap == 1'b1 & tlb_tag0_type[lrat_tagpos_type_ptereload] == 1'b1)) ? pte_tag0_lpid : + ((tlb_tag0_addr_cap == 1'b1 & tlb_tag0_thdid[0] == 1'b1 & tlb_tag0_type[lrat_tagpos_type_tlbwe] == 1'b1)) ? mas8_0_tlpid : +`ifdef MM_THREADS2 + ((tlb_tag0_addr_cap == 1'b1 & tlb_tag0_thdid[1] == 1'b1 & tlb_tag0_type[lrat_tagpos_type_tlbwe] == 1'b1)) ? mas8_1_tlpid : +`endif + lrat_tag1_lpid_q; + // tag1 phase signals, tlbwe/re ex3, tlbsx/srx ex4 + assign ex4_valid_d = tlb_ctl_ex3_valid & (~(xu_ex3_flush)); + assign ex4_ttype_d = tlb_ctl_ex3_ttype; + assign ex4_hv_state_d = tlb_ctl_ex3_hv_state; + assign addr_enable = tlb_addr_cap_q[1]; + assign lpid_enable = tlb_addr_cap_q[1]; + assign tlb_addr_cap_d[2] = tlb_addr_cap_q[1]; + assign lrat_tag2_lpn_d = lrat_tag1_lpn_q; + assign lrat_tag2_matchline_d = lrat_tag1_matchline; + assign lrat_tag2_size_d = lrat_tag1_size_q; + assign lrat_tag2_entry_size_d = (lrat_entry0_size_q & {4{lrat_tag1_matchline[0]}}) | + (lrat_entry1_size_q & {4{lrat_tag1_matchline[1]}}) | + (lrat_entry2_size_q & {4{lrat_tag1_matchline[2]}}) | + (lrat_entry3_size_q & {4{lrat_tag1_matchline[3]}}) | + (lrat_entry4_size_q & {4{lrat_tag1_matchline[4]}}) | + (lrat_entry5_size_q & {4{lrat_tag1_matchline[5]}}) | + (lrat_entry6_size_q & {4{lrat_tag1_matchline[6]}}) | + (lrat_entry7_size_q & {4{lrat_tag1_matchline[7]}}); + // tag2 phase signals, tlbwe/re ex4, tlbsx/srx ex5 + assign ex5_valid_d = ex4_valid_q & (~(xu_ex4_flush)); + assign ex5_ttype_d = ex4_ttype_q; +`ifdef MM_THREADS2 + assign ex5_esel_d = (mas0_0_esel & {`LRAT_NUM_ENTRY_LOG2{ex4_valid_q[0]}}) | (mas0_1_esel & {`LRAT_NUM_ENTRY_LOG2{ex4_valid_q[1]}}); + assign ex5_atsel_d = (mas0_0_atsel & ex4_valid_q[0]) | (mas0_1_atsel & ex4_valid_q[1]); + assign ex5_hes_d = (mas0_0_hes & ex4_valid_q[0]) | (mas0_1_hes & ex4_valid_q[1]); + assign ex5_wq_d = (mas0_0_wq & {2{ex4_valid_q[0]}}) | (mas0_1_wq & {2{ex4_valid_q[1]}}); +`else + assign ex5_esel_d = (mas0_0_esel & {`LRAT_NUM_ENTRY_LOG2{ex4_valid_q[0]}}); + assign ex5_atsel_d = (mas0_0_atsel & ex4_valid_q[0]); + assign ex5_hes_d = (mas0_0_hes & ex4_valid_q[0]); + assign ex5_wq_d = (mas0_0_wq & {2{ex4_valid_q[0]}}); +`endif + assign ex5_hv_state_d = ex4_hv_state_q; + assign lrat_tag3_lpn_d = lrat_tag2_lpn_q; + // hit_status: val,hit,multihit,inval_pgsize + assign lrat_tag3_hit_status_d[0] = tlb_addr_cap_q[2]; + assign lrat_tag3_hit_status_d[1] = tlb_addr_cap_q[2] & |(lrat_tag2_matchline_q[0:`LRAT_NUM_ENTRY - 1]); + assign lrat_tag3_hit_status_d[2] = tlb_addr_cap_q[2] & multihit; + assign lrat_tag3_hit_status_d[3] = tlb_addr_cap_q[2] & ((~(lrat_supp_pgsize)) | lrat_tag2_size_gt_entry_size); + assign multihit = ((lrat_tag2_matchline_q[0:`LRAT_NUM_ENTRY - 1] == 8'b00000000 | lrat_tag2_matchline_q[0:`LRAT_NUM_ENTRY - 1] == 8'b10000000 | lrat_tag2_matchline_q[0:`LRAT_NUM_ENTRY - 1] == 8'b01000000 | lrat_tag2_matchline_q[0:`LRAT_NUM_ENTRY - 1] == 8'b00100000 | lrat_tag2_matchline_q[0:`LRAT_NUM_ENTRY - 1] == 8'b00010000 | lrat_tag2_matchline_q[0:`LRAT_NUM_ENTRY - 1] == 8'b00001000 | lrat_tag2_matchline_q[0:`LRAT_NUM_ENTRY - 1] == 8'b00000100 | lrat_tag2_matchline_q[0:`LRAT_NUM_ENTRY - 1] == 8'b00000010 | lrat_tag2_matchline_q[0:`LRAT_NUM_ENTRY - 1] == 8'b00000001)) ? 1'b0 : + 1'b1; + assign lrat_tag3_hit_entry_d = (lrat_tag2_matchline_q[0:`LRAT_NUM_ENTRY - 1] == 8'b01000000) ? 3'b001 : + (lrat_tag2_matchline_q[0:`LRAT_NUM_ENTRY - 1] == 8'b00100000) ? 3'b010 : + (lrat_tag2_matchline_q[0:`LRAT_NUM_ENTRY - 1] == 8'b00010000) ? 3'b011 : + (lrat_tag2_matchline_q[0:`LRAT_NUM_ENTRY - 1] == 8'b00001000) ? 3'b100 : + (lrat_tag2_matchline_q[0:`LRAT_NUM_ENTRY - 1] == 8'b00000100) ? 3'b101 : + (lrat_tag2_matchline_q[0:`LRAT_NUM_ENTRY - 1] == 8'b00000010) ? 3'b110 : + (lrat_tag2_matchline_q[0:`LRAT_NUM_ENTRY - 1] == 8'b00000001) ? 3'b111 : + 3'b000; + // constant TLB_PgSize_1GB : std_ulogic_vector(0 to 3) := 1010 ; + // constant TLB_PgSize_256MB : std_ulogic_vector(0 to 3) := 1001 ; + // constant TLB_PgSize_16MB : std_ulogic_vector(0 to 3) := 0111 ; + // constant TLB_PgSize_1MB : std_ulogic_vector(0 to 3) := 0101 ; + // constant TLB_PgSize_64KB : std_ulogic_vector(0 to 3) := 0011 ; + // constant TLB_PgSize_4KB : std_ulogic_vector(0 to 3) := 0001 ; + // ISA 2.06 pgsize match criteria for tlbwe: + // MAS1.IND=0 and MAS1.TSIZE 10+5 + // ..in other words, the biggest page table for A2 is 256M/64K=4K entries x 8 bytes = 32K, + // .. 32K is always less than the minimum supported LRAT size of 1MB. + // pgsize match criteria for ptereload: + // PTE.PS 33) + begin : gen64_lrat_tag3_rpn_34 + assign lrat_tag3_rpn_d[64 - LRAT_PgSize_16GB_log2:64 - LRAT_PgSize_4GB_log2 - 1] = (((lrat_tag2_entry_size_q == LRAT_PgSize_1MB | lrat_tag2_entry_size_q == LRAT_PgSize_16MB | lrat_tag2_entry_size_q == LRAT_PgSize_256MB | lrat_tag2_entry_size_q == LRAT_PgSize_1GB | lrat_tag2_entry_size_q == LRAT_PgSize_4GB) & lrat_tag2_matchline_q[0] == 1'b1)) ? lrat_entry0_rpn_q[64 - LRAT_PgSize_16GB_log2:64 - LRAT_PgSize_4GB_log2 - 1] : + (((lrat_tag2_entry_size_q == LRAT_PgSize_1MB | lrat_tag2_entry_size_q == LRAT_PgSize_16MB | lrat_tag2_entry_size_q == LRAT_PgSize_256MB | lrat_tag2_entry_size_q == LRAT_PgSize_1GB | lrat_tag2_entry_size_q == LRAT_PgSize_4GB) & lrat_tag2_matchline_q[1] == 1'b1)) ? lrat_entry1_rpn_q[64 - LRAT_PgSize_16GB_log2:64 - LRAT_PgSize_4GB_log2 - 1] : + (((lrat_tag2_entry_size_q == LRAT_PgSize_1MB | lrat_tag2_entry_size_q == LRAT_PgSize_16MB | lrat_tag2_entry_size_q == LRAT_PgSize_256MB | lrat_tag2_entry_size_q == LRAT_PgSize_1GB | lrat_tag2_entry_size_q == LRAT_PgSize_4GB) & lrat_tag2_matchline_q[2] == 1'b1)) ? lrat_entry2_rpn_q[64 - LRAT_PgSize_16GB_log2:64 - LRAT_PgSize_4GB_log2 - 1] : + (((lrat_tag2_entry_size_q == LRAT_PgSize_1MB | lrat_tag2_entry_size_q == LRAT_PgSize_16MB | lrat_tag2_entry_size_q == LRAT_PgSize_256MB | lrat_tag2_entry_size_q == LRAT_PgSize_1GB | lrat_tag2_entry_size_q == LRAT_PgSize_4GB) & lrat_tag2_matchline_q[3] == 1'b1)) ? lrat_entry3_rpn_q[64 - LRAT_PgSize_16GB_log2:64 - LRAT_PgSize_4GB_log2 - 1] : + (((lrat_tag2_entry_size_q == LRAT_PgSize_1MB | lrat_tag2_entry_size_q == LRAT_PgSize_16MB | lrat_tag2_entry_size_q == LRAT_PgSize_256MB | lrat_tag2_entry_size_q == LRAT_PgSize_1GB | lrat_tag2_entry_size_q == LRAT_PgSize_4GB) & lrat_tag2_matchline_q[4] == 1'b1)) ? lrat_entry4_rpn_q[64 - LRAT_PgSize_16GB_log2:64 - LRAT_PgSize_4GB_log2 - 1] : + (((lrat_tag2_entry_size_q == LRAT_PgSize_1MB | lrat_tag2_entry_size_q == LRAT_PgSize_16MB | lrat_tag2_entry_size_q == LRAT_PgSize_256MB | lrat_tag2_entry_size_q == LRAT_PgSize_1GB | lrat_tag2_entry_size_q == LRAT_PgSize_4GB) & lrat_tag2_matchline_q[5] == 1'b1)) ? lrat_entry5_rpn_q[64 - LRAT_PgSize_16GB_log2:64 - LRAT_PgSize_4GB_log2 - 1] : + (((lrat_tag2_entry_size_q == LRAT_PgSize_1MB | lrat_tag2_entry_size_q == LRAT_PgSize_16MB | lrat_tag2_entry_size_q == LRAT_PgSize_256MB | lrat_tag2_entry_size_q == LRAT_PgSize_1GB | lrat_tag2_entry_size_q == LRAT_PgSize_4GB) & lrat_tag2_matchline_q[6] == 1'b1)) ? lrat_entry6_rpn_q[64 - LRAT_PgSize_16GB_log2:64 - LRAT_PgSize_4GB_log2 - 1] : + (((lrat_tag2_entry_size_q == LRAT_PgSize_1MB | lrat_tag2_entry_size_q == LRAT_PgSize_16MB | lrat_tag2_entry_size_q == LRAT_PgSize_256MB | lrat_tag2_entry_size_q == LRAT_PgSize_1GB | lrat_tag2_entry_size_q == LRAT_PgSize_4GB) & lrat_tag2_matchline_q[7] == 1'b1)) ? lrat_entry7_rpn_q[64 - LRAT_PgSize_16GB_log2:64 - LRAT_PgSize_4GB_log2 - 1] : + lrat_tag2_lpn_q[64 - LRAT_PgSize_16GB_log2:64 - LRAT_PgSize_4GB_log2 - 1]; + end + endgenerate + // rpn(26:29) + generate + if (`REAL_ADDR_WIDTH > 37) + begin : gen64_lrat_tag3_rpn_38 + assign lrat_tag3_rpn_d[64 - LRAT_PgSize_256GB_log2:64 - LRAT_PgSize_16GB_log2 - 1] = (((lrat_tag2_entry_size_q == LRAT_PgSize_1MB | lrat_tag2_entry_size_q == LRAT_PgSize_16MB | lrat_tag2_entry_size_q == LRAT_PgSize_256MB | lrat_tag2_entry_size_q == LRAT_PgSize_1GB | lrat_tag2_entry_size_q == LRAT_PgSize_4GB | lrat_tag2_entry_size_q == LRAT_PgSize_16GB) & lrat_tag2_matchline_q[0] == 1'b1)) ? lrat_entry0_rpn_q[64 - LRAT_PgSize_256GB_log2:64 - LRAT_PgSize_16GB_log2 - 1] : + (((lrat_tag2_entry_size_q == LRAT_PgSize_1MB | lrat_tag2_entry_size_q == LRAT_PgSize_16MB | lrat_tag2_entry_size_q == LRAT_PgSize_256MB | lrat_tag2_entry_size_q == LRAT_PgSize_1GB | lrat_tag2_entry_size_q == LRAT_PgSize_4GB | lrat_tag2_entry_size_q == LRAT_PgSize_16GB) & lrat_tag2_matchline_q[1] == 1'b1)) ? lrat_entry1_rpn_q[64 - LRAT_PgSize_256GB_log2:64 - LRAT_PgSize_16GB_log2 - 1] : + (((lrat_tag2_entry_size_q == LRAT_PgSize_1MB | lrat_tag2_entry_size_q == LRAT_PgSize_16MB | lrat_tag2_entry_size_q == LRAT_PgSize_256MB | lrat_tag2_entry_size_q == LRAT_PgSize_1GB | lrat_tag2_entry_size_q == LRAT_PgSize_4GB | lrat_tag2_entry_size_q == LRAT_PgSize_16GB) & lrat_tag2_matchline_q[2] == 1'b1)) ? lrat_entry2_rpn_q[64 - LRAT_PgSize_256GB_log2:64 - LRAT_PgSize_16GB_log2 - 1] : + (((lrat_tag2_entry_size_q == LRAT_PgSize_1MB | lrat_tag2_entry_size_q == LRAT_PgSize_16MB | lrat_tag2_entry_size_q == LRAT_PgSize_256MB | lrat_tag2_entry_size_q == LRAT_PgSize_1GB | lrat_tag2_entry_size_q == LRAT_PgSize_4GB | lrat_tag2_entry_size_q == LRAT_PgSize_16GB) & lrat_tag2_matchline_q[3] == 1'b1)) ? lrat_entry3_rpn_q[64 - LRAT_PgSize_256GB_log2:64 - LRAT_PgSize_16GB_log2 - 1] : + (((lrat_tag2_entry_size_q == LRAT_PgSize_1MB | lrat_tag2_entry_size_q == LRAT_PgSize_16MB | lrat_tag2_entry_size_q == LRAT_PgSize_256MB | lrat_tag2_entry_size_q == LRAT_PgSize_1GB | lrat_tag2_entry_size_q == LRAT_PgSize_4GB | lrat_tag2_entry_size_q == LRAT_PgSize_16GB) & lrat_tag2_matchline_q[4] == 1'b1)) ? lrat_entry4_rpn_q[64 - LRAT_PgSize_256GB_log2:64 - LRAT_PgSize_16GB_log2 - 1] : + (((lrat_tag2_entry_size_q == LRAT_PgSize_1MB | lrat_tag2_entry_size_q == LRAT_PgSize_16MB | lrat_tag2_entry_size_q == LRAT_PgSize_256MB | lrat_tag2_entry_size_q == LRAT_PgSize_1GB | lrat_tag2_entry_size_q == LRAT_PgSize_4GB | lrat_tag2_entry_size_q == LRAT_PgSize_16GB) & lrat_tag2_matchline_q[5] == 1'b1)) ? lrat_entry5_rpn_q[64 - LRAT_PgSize_256GB_log2:64 - LRAT_PgSize_16GB_log2 - 1] : + (((lrat_tag2_entry_size_q == LRAT_PgSize_1MB | lrat_tag2_entry_size_q == LRAT_PgSize_16MB | lrat_tag2_entry_size_q == LRAT_PgSize_256MB | lrat_tag2_entry_size_q == LRAT_PgSize_1GB | lrat_tag2_entry_size_q == LRAT_PgSize_4GB | lrat_tag2_entry_size_q == LRAT_PgSize_16GB) & lrat_tag2_matchline_q[6] == 1'b1)) ? lrat_entry6_rpn_q[64 - LRAT_PgSize_256GB_log2:64 - LRAT_PgSize_16GB_log2 - 1] : + (((lrat_tag2_entry_size_q == LRAT_PgSize_1MB | lrat_tag2_entry_size_q == LRAT_PgSize_16MB | lrat_tag2_entry_size_q == LRAT_PgSize_256MB | lrat_tag2_entry_size_q == LRAT_PgSize_1GB | lrat_tag2_entry_size_q == LRAT_PgSize_4GB | lrat_tag2_entry_size_q == LRAT_PgSize_16GB) & lrat_tag2_matchline_q[7] == 1'b1)) ? lrat_entry7_rpn_q[64 - LRAT_PgSize_256GB_log2:64 - LRAT_PgSize_16GB_log2 - 1] : + lrat_tag2_lpn_q[64 - LRAT_PgSize_256GB_log2:64 - LRAT_PgSize_16GB_log2 - 1]; + end + endgenerate + // rpn(24:25) + generate + if (`REAL_ADDR_WIDTH > 39) + begin : gen64_lrat_tag3_rpn_40 + assign lrat_tag3_rpn_d[64 - LRAT_PgSize_1TB_log2:64 - LRAT_PgSize_256GB_log2 - 1] = (((lrat_tag2_entry_size_q == LRAT_PgSize_1MB | lrat_tag2_entry_size_q == LRAT_PgSize_16MB | lrat_tag2_entry_size_q == LRAT_PgSize_256MB | lrat_tag2_entry_size_q == LRAT_PgSize_1GB | lrat_tag2_entry_size_q == LRAT_PgSize_4GB | lrat_tag2_entry_size_q == LRAT_PgSize_16GB | lrat_tag2_entry_size_q == LRAT_PgSize_256GB) & lrat_tag2_matchline_q[0] == 1'b1)) ? lrat_entry0_rpn_q[64 - LRAT_PgSize_1TB_log2:64 - LRAT_PgSize_256GB_log2 - 1] : + (((lrat_tag2_entry_size_q == LRAT_PgSize_1MB | lrat_tag2_entry_size_q == LRAT_PgSize_16MB | lrat_tag2_entry_size_q == LRAT_PgSize_256MB | lrat_tag2_entry_size_q == LRAT_PgSize_1GB | lrat_tag2_entry_size_q == LRAT_PgSize_4GB | lrat_tag2_entry_size_q == LRAT_PgSize_16GB | lrat_tag2_entry_size_q == LRAT_PgSize_256GB) & lrat_tag2_matchline_q[1] == 1'b1)) ? lrat_entry1_rpn_q[64 - LRAT_PgSize_1TB_log2:64 - LRAT_PgSize_256GB_log2 - 1] : + (((lrat_tag2_entry_size_q == LRAT_PgSize_1MB | lrat_tag2_entry_size_q == LRAT_PgSize_16MB | lrat_tag2_entry_size_q == LRAT_PgSize_256MB | lrat_tag2_entry_size_q == LRAT_PgSize_1GB | lrat_tag2_entry_size_q == LRAT_PgSize_4GB | lrat_tag2_entry_size_q == LRAT_PgSize_16GB | lrat_tag2_entry_size_q == LRAT_PgSize_256GB) & lrat_tag2_matchline_q[2] == 1'b1)) ? lrat_entry2_rpn_q[64 - LRAT_PgSize_1TB_log2:64 - LRAT_PgSize_256GB_log2 - 1] : + (((lrat_tag2_entry_size_q == LRAT_PgSize_1MB | lrat_tag2_entry_size_q == LRAT_PgSize_16MB | lrat_tag2_entry_size_q == LRAT_PgSize_256MB | lrat_tag2_entry_size_q == LRAT_PgSize_1GB | lrat_tag2_entry_size_q == LRAT_PgSize_4GB | lrat_tag2_entry_size_q == LRAT_PgSize_16GB | lrat_tag2_entry_size_q == LRAT_PgSize_256GB) & lrat_tag2_matchline_q[3] == 1'b1)) ? lrat_entry3_rpn_q[64 - LRAT_PgSize_1TB_log2:64 - LRAT_PgSize_256GB_log2 - 1] : + (((lrat_tag2_entry_size_q == LRAT_PgSize_1MB | lrat_tag2_entry_size_q == LRAT_PgSize_16MB | lrat_tag2_entry_size_q == LRAT_PgSize_256MB | lrat_tag2_entry_size_q == LRAT_PgSize_1GB | lrat_tag2_entry_size_q == LRAT_PgSize_4GB | lrat_tag2_entry_size_q == LRAT_PgSize_16GB | lrat_tag2_entry_size_q == LRAT_PgSize_256GB) & lrat_tag2_matchline_q[4] == 1'b1)) ? lrat_entry4_rpn_q[64 - LRAT_PgSize_1TB_log2:64 - LRAT_PgSize_256GB_log2 - 1] : + (((lrat_tag2_entry_size_q == LRAT_PgSize_1MB | lrat_tag2_entry_size_q == LRAT_PgSize_16MB | lrat_tag2_entry_size_q == LRAT_PgSize_256MB | lrat_tag2_entry_size_q == LRAT_PgSize_1GB | lrat_tag2_entry_size_q == LRAT_PgSize_4GB | lrat_tag2_entry_size_q == LRAT_PgSize_16GB | lrat_tag2_entry_size_q == LRAT_PgSize_256GB) & lrat_tag2_matchline_q[5] == 1'b1)) ? lrat_entry5_rpn_q[64 - LRAT_PgSize_1TB_log2:64 - LRAT_PgSize_256GB_log2 - 1] : + (((lrat_tag2_entry_size_q == LRAT_PgSize_1MB | lrat_tag2_entry_size_q == LRAT_PgSize_16MB | lrat_tag2_entry_size_q == LRAT_PgSize_256MB | lrat_tag2_entry_size_q == LRAT_PgSize_1GB | lrat_tag2_entry_size_q == LRAT_PgSize_4GB | lrat_tag2_entry_size_q == LRAT_PgSize_16GB | lrat_tag2_entry_size_q == LRAT_PgSize_256GB) & lrat_tag2_matchline_q[6] == 1'b1)) ? lrat_entry6_rpn_q[64 - LRAT_PgSize_1TB_log2:64 - LRAT_PgSize_256GB_log2 - 1] : + (((lrat_tag2_entry_size_q == LRAT_PgSize_1MB | lrat_tag2_entry_size_q == LRAT_PgSize_16MB | lrat_tag2_entry_size_q == LRAT_PgSize_256MB | lrat_tag2_entry_size_q == LRAT_PgSize_1GB | lrat_tag2_entry_size_q == LRAT_PgSize_4GB | lrat_tag2_entry_size_q == LRAT_PgSize_16GB | lrat_tag2_entry_size_q == LRAT_PgSize_256GB) & lrat_tag2_matchline_q[7] == 1'b1)) ? lrat_entry7_rpn_q[64 - LRAT_PgSize_1TB_log2:64 - LRAT_PgSize_256GB_log2 - 1] : + lrat_tag2_lpn_q[64 - LRAT_PgSize_1TB_log2:64 - LRAT_PgSize_256GB_log2 - 1]; + end + endgenerate + // rpn(22:23) + generate + if (`REAL_ADDR_WIDTH > 41) + begin : gen64_lrat_tag3_rpn_42 + assign lrat_tag3_rpn_d[64 - `REAL_ADDR_WIDTH:64 - `LRAT_MAXSIZE_LOG2 - 1] = (lrat_tag2_matchline_q[0] == 1'b1) ? lrat_entry0_rpn_q[64 - `REAL_ADDR_WIDTH:64 - `LRAT_MAXSIZE_LOG2 - 1] : + (lrat_tag2_matchline_q[1] == 1'b1) ? lrat_entry1_rpn_q[64 - `REAL_ADDR_WIDTH:64 - `LRAT_MAXSIZE_LOG2 - 1] : + (lrat_tag2_matchline_q[2] == 1'b1) ? lrat_entry2_rpn_q[64 - `REAL_ADDR_WIDTH:64 - `LRAT_MAXSIZE_LOG2 - 1] : + (lrat_tag2_matchline_q[3] == 1'b1) ? lrat_entry3_rpn_q[64 - `REAL_ADDR_WIDTH:64 - `LRAT_MAXSIZE_LOG2 - 1] : + (lrat_tag2_matchline_q[4] == 1'b1) ? lrat_entry4_rpn_q[64 - `REAL_ADDR_WIDTH:64 - `LRAT_MAXSIZE_LOG2 - 1] : + (lrat_tag2_matchline_q[5] == 1'b1) ? lrat_entry5_rpn_q[64 - `REAL_ADDR_WIDTH:64 - `LRAT_MAXSIZE_LOG2 - 1] : + (lrat_tag2_matchline_q[6] == 1'b1) ? lrat_entry6_rpn_q[64 - `REAL_ADDR_WIDTH:64 - `LRAT_MAXSIZE_LOG2 - 1] : + (lrat_tag2_matchline_q[7] == 1'b1) ? lrat_entry7_rpn_q[64 - `REAL_ADDR_WIDTH:64 - `LRAT_MAXSIZE_LOG2 - 1] : + lrat_tag2_lpn_q[64 - `REAL_ADDR_WIDTH:64 - `LRAT_MAXSIZE_LOG2 - 1]; + end + endgenerate + //constant LRAT_PgSize_1TB_log2 : integer := 40; + //constant LRAT_PgSize_256GB_log2 : integer := 38; + //constant LRAT_PgSize_16GB_log2 : integer := 34; + //constant LRAT_PgSize_4GB_log2 : integer := 32; + //constant LRAT_PgSize_1GB_log2 : integer := 30; + //constant LRAT_PgSize_256MB_log2 : integer := 28; + //constant LRAT_PgSize_16MB_log2 : integer := 24; + //constant LRAT_PgSize_1MB_log2 : integer := 20; + // tag3 phase signals, tlbwe/re ex4, tlbsx/srx ex5 + assign ex6_valid_d = ex5_valid_q & (~(xu_ex5_flush)); + assign ex6_ttype_d = ex5_ttype_q; + assign ex6_esel_d = ex5_esel_q; + assign ex6_atsel_d = ex5_atsel_q; + assign ex6_hes_d = ex5_hes_q; + assign ex6_wq_d = ex5_wq_q; + assign ex6_hv_state_d = ex5_hv_state_q; + assign lrat_tag4_lpn_d = lrat_tag3_lpn_q; + assign lrat_tag4_rpn_d = lrat_tag3_rpn_q; + assign lrat_tag4_hit_status_d = lrat_tag3_hit_status_q; + assign lrat_tag4_hit_entry_d = lrat_tag3_hit_entry_q; +`ifdef MM_THREADS2 + assign lrat_datain_lpn_d = ((ex5_valid_q[0] == 1'b1)) ? mas2_0_epn[64 - `REAL_ADDR_WIDTH:63 - `LRAT_MINSIZE_LOG2] : + ((ex5_valid_q[1] == 1'b1)) ? mas2_1_epn[64 - `REAL_ADDR_WIDTH:63 - `LRAT_MINSIZE_LOG2] : + lrat_datain_lpn_q; +`else + assign lrat_datain_lpn_d = ((ex5_valid_q[0] == 1'b1)) ? mas2_0_epn[64 - `REAL_ADDR_WIDTH:63 - `LRAT_MINSIZE_LOG2] : + lrat_datain_lpn_q; +`endif + + generate + if (`REAL_ADDR_WIDTH > 32) + begin : gen64_lrat_datain_rpn +`ifdef MM_THREADS2 + assign lrat_datain_rpn_d[64 - `REAL_ADDR_WIDTH:31] = ((ex5_valid_q[0] == 1'b1)) ? mas7_0_rpnu[64 - `REAL_ADDR_WIDTH:31] : + ((ex5_valid_q[1] == 1'b1)) ? mas7_1_rpnu[64 - `REAL_ADDR_WIDTH:31] : + lrat_datain_rpn_q[64 - `REAL_ADDR_WIDTH:31]; +`else + assign lrat_datain_rpn_d[64 - `REAL_ADDR_WIDTH:31] = ((ex5_valid_q[0] == 1'b1)) ? mas7_0_rpnu[64 - `REAL_ADDR_WIDTH:31] : + lrat_datain_rpn_q[64 - `REAL_ADDR_WIDTH:31]; +`endif + end + endgenerate + +`ifdef MM_THREADS2 + assign lrat_datain_rpn_d[32:63 - `LRAT_MINSIZE_LOG2] = ((ex5_valid_q[0] == 1'b1)) ? mas3_0_rpnl[32:63 - `LRAT_MINSIZE_LOG2] : + ((ex5_valid_q[1] == 1'b1)) ? mas3_1_rpnl[32:63 - `LRAT_MINSIZE_LOG2] : + lrat_datain_rpn_q[32:63 - `LRAT_MINSIZE_LOG2]; + assign lrat_datain_lpid_d = ((ex5_valid_q[0] == 1'b1)) ? mas8_0_tlpid : + ((ex5_valid_q[1] == 1'b1)) ? mas8_1_tlpid : + lrat_datain_lpid_q; + assign lrat_datain_size_d = ((ex5_valid_q[0] == 1'b1)) ? mas1_0_tsize : + ((ex5_valid_q[1] == 1'b1)) ? mas1_1_tsize : + lrat_datain_size_q; + assign lrat_datain_valid_d = ((ex5_valid_q[0] == 1'b1)) ? mas1_0_v : + ((ex5_valid_q[1] == 1'b1)) ? mas1_1_v : + lrat_datain_valid_q; + assign lrat_datain_xbit_d = ((ex5_valid_q[0] == 1'b1)) ? mmucr3_0_x : + ((ex5_valid_q[1] == 1'b1)) ? mmucr3_1_x : + lrat_datain_xbit_q; +`else + assign lrat_datain_rpn_d[32:63 - `LRAT_MINSIZE_LOG2] = ((ex5_valid_q[0] == 1'b1)) ? mas3_0_rpnl[32:63 - `LRAT_MINSIZE_LOG2] : + lrat_datain_rpn_q[32:63 - `LRAT_MINSIZE_LOG2]; + assign lrat_datain_lpid_d = ((ex5_valid_q[0] == 1'b1)) ? mas8_0_tlpid : + lrat_datain_lpid_q; + assign lrat_datain_size_d = ((ex5_valid_q[0] == 1'b1)) ? mas1_0_tsize : + lrat_datain_size_q; + assign lrat_datain_valid_d = ((ex5_valid_q[0] == 1'b1)) ? mas1_0_v : + lrat_datain_valid_q; + assign lrat_datain_xbit_d = ((ex5_valid_q[0] == 1'b1)) ? mmucr3_0_x : + lrat_datain_xbit_q; +`endif + assign lrat_mmucr3_x_d = ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b000)) ? lrat_entry0_xbit_q : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b001)) ? lrat_entry1_xbit_q : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b010)) ? lrat_entry2_xbit_q : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b011)) ? lrat_entry3_xbit_q : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b100)) ? lrat_entry4_xbit_q : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b101)) ? lrat_entry5_xbit_q : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b110)) ? lrat_entry6_xbit_q : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b111)) ? lrat_entry7_xbit_q : + lrat_mmucr3_x_q; + assign lrat_mas1_v_d = ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b000)) ? lrat_entry0_valid_q : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b001)) ? lrat_entry1_valid_q : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b010)) ? lrat_entry2_valid_q : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b011)) ? lrat_entry3_valid_q : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b100)) ? lrat_entry4_valid_q : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b101)) ? lrat_entry5_valid_q : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b110)) ? lrat_entry6_valid_q : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b111)) ? lrat_entry7_valid_q : + lrat_mas1_v_q; + assign lrat_mas1_tsize_d = ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b000)) ? lrat_entry0_size_q : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b001)) ? lrat_entry1_size_q : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b010)) ? lrat_entry2_size_q : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b011)) ? lrat_entry3_size_q : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b100)) ? lrat_entry4_size_q : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b101)) ? lrat_entry5_size_q : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b110)) ? lrat_entry6_size_q : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b111)) ? lrat_entry7_size_q : + lrat_mas1_tsize_q; + assign lrat_mas2_epn_d[64 - `REAL_ADDR_WIDTH:64 - `LRAT_MINSIZE_LOG2 - 1] = ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b000)) ? lrat_entry0_lpn_q[64 - `REAL_ADDR_WIDTH:64 - `LRAT_MINSIZE_LOG2 - 1] : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b001)) ? lrat_entry1_lpn_q[64 - `REAL_ADDR_WIDTH:64 - `LRAT_MINSIZE_LOG2 - 1] : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b010)) ? lrat_entry2_lpn_q[64 - `REAL_ADDR_WIDTH:64 - `LRAT_MINSIZE_LOG2 - 1] : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b011)) ? lrat_entry3_lpn_q[64 - `REAL_ADDR_WIDTH:64 - `LRAT_MINSIZE_LOG2 - 1] : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b100)) ? lrat_entry4_lpn_q[64 - `REAL_ADDR_WIDTH:64 - `LRAT_MINSIZE_LOG2 - 1] : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b101)) ? lrat_entry5_lpn_q[64 - `REAL_ADDR_WIDTH:64 - `LRAT_MINSIZE_LOG2 - 1] : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b110)) ? lrat_entry6_lpn_q[64 - `REAL_ADDR_WIDTH:64 - `LRAT_MINSIZE_LOG2 - 1] : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b111)) ? lrat_entry7_lpn_q[64 - `REAL_ADDR_WIDTH:64 - `LRAT_MINSIZE_LOG2 - 1] : + lrat_mas2_epn_q[64 - `REAL_ADDR_WIDTH:64 - `LRAT_MINSIZE_LOG2 - 1]; + assign lrat_mas2_epn_d[64 - `LRAT_MINSIZE_LOG2:51] = ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b000)) ? {8{1'b0}} : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b001)) ? {8{1'b0}} : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b010)) ? {8{1'b0}} : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b011)) ? {8{1'b0}} : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b100)) ? {8{1'b0}} : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b101)) ? {8{1'b0}} : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b110)) ? {8{1'b0}} : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b111)) ? {8{1'b0}} : + lrat_mas2_epn_q[64 - `LRAT_MINSIZE_LOG2:51]; + assign lrat_mas3_rpnl_d[32:64 - `LRAT_MINSIZE_LOG2 - 1] = ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b000)) ? lrat_entry0_rpn_q[32:64 - `LRAT_MINSIZE_LOG2 - 1] : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b001)) ? lrat_entry1_rpn_q[32:64 - `LRAT_MINSIZE_LOG2 - 1] : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b010)) ? lrat_entry2_rpn_q[32:64 - `LRAT_MINSIZE_LOG2 - 1] : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b011)) ? lrat_entry3_rpn_q[32:64 - `LRAT_MINSIZE_LOG2 - 1] : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b100)) ? lrat_entry4_rpn_q[32:64 - `LRAT_MINSIZE_LOG2 - 1] : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b101)) ? lrat_entry5_rpn_q[32:64 - `LRAT_MINSIZE_LOG2 - 1] : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b110)) ? lrat_entry6_rpn_q[32:64 - `LRAT_MINSIZE_LOG2 - 1] : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b111)) ? lrat_entry7_rpn_q[32:64 - `LRAT_MINSIZE_LOG2 - 1] : + lrat_mas3_rpnl_q[32:64 - `LRAT_MINSIZE_LOG2 - 1]; + assign lrat_mas3_rpnl_d[64 - `LRAT_MINSIZE_LOG2:51] = ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b000)) ? {8{1'b0}} : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b001)) ? {8{1'b0}} : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b010)) ? {8{1'b0}} : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b011)) ? {8{1'b0}} : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b100)) ? {8{1'b0}} : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b101)) ? {8{1'b0}} : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b110)) ? {8{1'b0}} : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b111)) ? {8{1'b0}} : + lrat_mas3_rpnl_q[64 - `LRAT_MINSIZE_LOG2:51]; + assign lrat_mas7_rpnu_d[64 - `REAL_ADDR_WIDTH:31] = ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b000)) ? lrat_entry0_rpn_q[64 - `REAL_ADDR_WIDTH:31] : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b001)) ? lrat_entry1_rpn_q[64 - `REAL_ADDR_WIDTH:31] : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b010)) ? lrat_entry2_rpn_q[64 - `REAL_ADDR_WIDTH:31] : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b011)) ? lrat_entry3_rpn_q[64 - `REAL_ADDR_WIDTH:31] : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b100)) ? lrat_entry4_rpn_q[64 - `REAL_ADDR_WIDTH:31] : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b101)) ? lrat_entry5_rpn_q[64 - `REAL_ADDR_WIDTH:31] : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b110)) ? lrat_entry6_rpn_q[64 - `REAL_ADDR_WIDTH:31] : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b111)) ? lrat_entry7_rpn_q[64 - `REAL_ADDR_WIDTH:31] : + lrat_mas7_rpnu_q[64 - `REAL_ADDR_WIDTH:31]; + assign lrat_mas8_tlpid_d = ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b000)) ? lrat_entry0_lpid_q : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b001)) ? lrat_entry1_lpid_q : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b010)) ? lrat_entry2_lpid_q : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b011)) ? lrat_entry3_lpid_q : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b100)) ? lrat_entry4_lpid_q : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b101)) ? lrat_entry5_lpid_q : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b110)) ? lrat_entry6_lpid_q : + ((|(ex5_valid_q) == 1'b1 & ex5_esel_q == 3'b111)) ? lrat_entry7_lpid_q : + lrat_mas8_tlpid_q; + // ttype -> tlbre,tlbwe,tlbsx,tlbsxr,tlbsrx + assign lrat_mas_tlbre_d = ((|(ex5_valid_q & (~(xu_ex5_flush))) == 1'b1 & ex5_ttype_q[0] == 1'b1 & ex5_atsel_q == 1'b1 & ex5_hv_state_q == 1'b1)) ? 1'b1 : + 1'b0; + assign lrat_mas_tlbsx_hit_d = ((|(ex6_valid_q) == 1'b1 & ex6_ttype_q[2:4] != 3'b000 & ex6_ttype_q[0] == 1'b1 & ex6_atsel_q == 1'b1 & ex6_hv_state_q == 1'b1 & lrat_tag3_hit_status_q[1] == 1'b1)) ? 1'b1 : + 1'b0; + assign lrat_mas_tlbsx_miss_d = ((|(ex6_valid_q) == 1'b1 & ex6_ttype_q[2:4] != 3'b000 & ex6_ttype_q[0] == 1'b1 & ex6_atsel_q == 1'b1 & ex6_hv_state_q == 1'b1 & lrat_tag3_hit_status_q[1] == 1'b0)) ? 1'b1 : + 1'b0; + assign lrat_mas_thdid_d[0:`MM_THREADS-1] = (ex5_valid_q & {`MM_THREADS{ex5_ttype_q[0]}}) | + (ex6_valid_q & {`MM_THREADS{|(ex6_ttype_q[2:4])}}); + // power clock gating + assign lrat_mas_act_d[0] = ((|(ex4_valid_q) & |(ex4_ttype_q)) | mmucr2_act_override) & xu_mm_ccr2_notlb_b; + assign lrat_mas_act_d[1] = ((|(ex4_valid_q) & |(ex4_ttype_q)) | mmucr2_act_override) & xu_mm_ccr2_notlb_b; + assign lrat_mas_act_d[2] = (((|(ex4_valid_q) & |(ex4_ttype_q)) | mmucr2_act_override) & xu_mm_ccr2_notlb_b) | + (((|(ex5_valid_q) & |(ex5_ttype_q)) | mmucr2_act_override) & xu_mm_ccr2_notlb_b) | + (((|(ex6_valid_q) & |(ex6_ttype_q)) | mmucr2_act_override) & xu_mm_ccr2_notlb_b); + assign lrat_datain_act_d[0] = ((|(ex4_valid_q) & |(ex4_ttype_q)) | mmucr2_act_override) & xu_mm_ccr2_notlb_b; + assign lrat_datain_act_d[1] = ((|(ex4_valid_q) & |(ex4_ttype_q)) | mmucr2_act_override) & xu_mm_ccr2_notlb_b; + // tag4 phase signals, tlbwe/re ex6 + assign lrat_entry0_wren = ((|(ex6_valid_q) == 1'b1 & ex6_ttype_q[1] == 1'b1 & ex6_hv_state_q == 1'b1 & ex6_atsel_q == 1'b1 & ex6_hes_q == 1'b0 & (ex6_wq_q == 2'b00 | ex6_wq_q == 2'b11) & ex6_esel_q == 3'b000 & ex6_illeg_instr[1] == 1'b0)) ? 1'b1 : + 1'b0; + assign lrat_entry0_lpn_d = ((lrat_entry0_wren == 1'b1)) ? lrat_datain_lpn_q : + lrat_entry0_lpn_q; + assign lrat_entry0_rpn_d = ((lrat_entry0_wren == 1'b1)) ? lrat_datain_rpn_q : + lrat_entry0_rpn_q; + assign lrat_entry0_lpid_d = ((lrat_entry0_wren == 1'b1)) ? lrat_datain_lpid_q : + lrat_entry0_lpid_q; + assign lrat_entry0_size_d = ((lrat_entry0_wren == 1'b1)) ? lrat_datain_size_q : + lrat_entry0_size_q; + assign lrat_entry0_xbit_d = ((lrat_entry0_wren == 1'b1)) ? lrat_datain_xbit_q : + lrat_entry0_xbit_q; + assign lrat_entry0_valid_d = ((lrat_entry0_wren == 1'b1)) ? lrat_datain_valid_q : + lrat_entry0_valid_q; + + assign lrat_datain_size_gte_1TB = (lrat_datain_size_q == LRAT_PgSize_1TB) ? 1'b1 : + 1'b0; + assign lrat_datain_size_gte_256GB = ((lrat_datain_size_q == LRAT_PgSize_1TB) | + (lrat_datain_size_q == LRAT_PgSize_256GB)) ? 1'b1 : + 1'b0; + assign lrat_datain_size_gte_16GB = ((lrat_datain_size_q == LRAT_PgSize_1TB) | + (lrat_datain_size_q == LRAT_PgSize_256GB) | + (lrat_datain_size_q == LRAT_PgSize_16GB)) ? 1'b1 : + 1'b0; + assign lrat_datain_size_gte_4GB = ((lrat_datain_size_q == LRAT_PgSize_1TB) | + (lrat_datain_size_q == LRAT_PgSize_256GB) | + (lrat_datain_size_q == LRAT_PgSize_16GB) | + (lrat_datain_size_q == LRAT_PgSize_4GB)) ? 1'b1 : + 1'b0; + assign lrat_datain_size_gte_1GB = ((lrat_datain_size_q == LRAT_PgSize_1TB) | + (lrat_datain_size_q == LRAT_PgSize_256GB) | + (lrat_datain_size_q == LRAT_PgSize_16GB) | + (lrat_datain_size_q == LRAT_PgSize_4GB) | + (lrat_datain_size_q == LRAT_PgSize_1GB)) ? 1'b1 : + 1'b0; + assign lrat_datain_size_gte_256MB = ((lrat_datain_size_q == LRAT_PgSize_1TB) | + (lrat_datain_size_q == LRAT_PgSize_256GB) | + (lrat_datain_size_q == LRAT_PgSize_16GB) | + (lrat_datain_size_q == LRAT_PgSize_4GB) | + (lrat_datain_size_q == LRAT_PgSize_1GB) | + (lrat_datain_size_q == LRAT_PgSize_256MB)) ? 1'b1 : + 1'b0; + assign lrat_datain_size_gte_16MB = ((lrat_datain_size_q == LRAT_PgSize_1TB) | + (lrat_datain_size_q == LRAT_PgSize_256GB) | + (lrat_datain_size_q == LRAT_PgSize_16GB) | + (lrat_datain_size_q == LRAT_PgSize_4GB) | + (lrat_datain_size_q == LRAT_PgSize_1GB) | + (lrat_datain_size_q == LRAT_PgSize_256MB) | + (lrat_datain_size_q == LRAT_PgSize_16MB)) ? 1'b1 : + 1'b0; + + // size entry_cmpmask: 0123456 + // 1TB 1111111 + // 256GB 0111111 + // 16GB 0011111 + // 4GB 0001111 + // 1GB 0000111 + // 256MB 0000011 + // 16MB 0000001 + // 1MB 0000000 + assign lrat_entry0_cmpmask_d[0] = ((lrat_entry0_wren == 1'b1)) ? (lrat_datain_size_gte_1TB) : + lrat_entry0_cmpmask_q[0]; + assign lrat_entry0_cmpmask_d[1] = ((lrat_entry0_wren == 1'b1)) ? (lrat_datain_size_gte_256GB) : + lrat_entry0_cmpmask_q[1]; + assign lrat_entry0_cmpmask_d[2] = ((lrat_entry0_wren == 1'b1)) ? (lrat_datain_size_gte_16GB) : + lrat_entry0_cmpmask_q[2]; + assign lrat_entry0_cmpmask_d[3] = ((lrat_entry0_wren == 1'b1)) ? (lrat_datain_size_gte_4GB) : + lrat_entry0_cmpmask_q[3]; + assign lrat_entry0_cmpmask_d[4] = ((lrat_entry0_wren == 1'b1)) ? (lrat_datain_size_gte_1GB) : + lrat_entry0_cmpmask_q[4]; + assign lrat_entry0_cmpmask_d[5] = ((lrat_entry0_wren == 1'b1)) ? (lrat_datain_size_gte_256MB) : + lrat_entry0_cmpmask_q[5]; + assign lrat_entry0_cmpmask_d[6] = ((lrat_entry0_wren == 1'b1)) ? (lrat_datain_size_gte_16MB) : + lrat_entry0_cmpmask_q[6]; + // size entry_xbitmask: 0123456 + // 1TB 1000000 + // 256GB 0100000 + // 16GB 0010000 + // 4GB 0001000 + // 1GB 0000100 + // 256MB 0000010 + // 16MB 0000001 + // 1MB 0000000 + assign lrat_entry0_xbitmask_d[0] = ((lrat_entry0_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_1TB) : + lrat_entry0_xbitmask_q[0]; + assign lrat_entry0_xbitmask_d[1] = ((lrat_entry0_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_256GB) : + lrat_entry0_xbitmask_q[1]; + assign lrat_entry0_xbitmask_d[2] = ((lrat_entry0_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_16GB) : + lrat_entry0_xbitmask_q[2]; + assign lrat_entry0_xbitmask_d[3] = ((lrat_entry0_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_4GB) : + lrat_entry0_xbitmask_q[3]; + assign lrat_entry0_xbitmask_d[4] = ((lrat_entry0_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_1GB) : + lrat_entry0_xbitmask_q[4]; + assign lrat_entry0_xbitmask_d[5] = ((lrat_entry0_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_256MB) : + lrat_entry0_xbitmask_q[5]; + assign lrat_entry0_xbitmask_d[6] = ((lrat_entry0_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_16MB) : + lrat_entry0_xbitmask_q[6]; + assign lrat_entry1_wren = ((|(ex6_valid_q) == 1'b1 & ex6_ttype_q[1] == 1'b1 & ex6_hv_state_q == 1'b1 & ex6_atsel_q == 1'b1 & ex6_hes_q == 1'b0 & (ex6_wq_q == 2'b00 | ex6_wq_q == 2'b11) & ex6_esel_q == 3'b001 & ex6_illeg_instr[1] == 1'b0)) ? 1'b1 : + 1'b0; + assign lrat_entry1_lpn_d = ((lrat_entry1_wren == 1'b1)) ? lrat_datain_lpn_q : + lrat_entry1_lpn_q; + assign lrat_entry1_rpn_d = ((lrat_entry1_wren == 1'b1)) ? lrat_datain_rpn_q : + lrat_entry1_rpn_q; + assign lrat_entry1_lpid_d = ((lrat_entry1_wren == 1'b1)) ? lrat_datain_lpid_q : + lrat_entry1_lpid_q; + assign lrat_entry1_size_d = ((lrat_entry1_wren == 1'b1)) ? lrat_datain_size_q : + lrat_entry1_size_q; + assign lrat_entry1_xbit_d = ((lrat_entry1_wren == 1'b1)) ? lrat_datain_xbit_q : + lrat_entry1_xbit_q; + assign lrat_entry1_valid_d = ((lrat_entry1_wren == 1'b1)) ? lrat_datain_valid_q : + lrat_entry1_valid_q; + // size entry_cmpmask: 0123456 + // 1TB 1111111 + // 256GB 0111111 + // 16GB 0011111 + // 4GB 0001111 + // 1GB 0000111 + // 256MB 0000011 + // 16MB 0000001 + // 1MB 0000000 + assign lrat_entry1_cmpmask_d[0] = ((lrat_entry1_wren == 1'b1)) ? (lrat_datain_size_gte_1TB) : + lrat_entry1_cmpmask_q[0]; + assign lrat_entry1_cmpmask_d[1] = ((lrat_entry1_wren == 1'b1)) ? (lrat_datain_size_gte_256GB) : + lrat_entry1_cmpmask_q[1]; + assign lrat_entry1_cmpmask_d[2] = ((lrat_entry1_wren == 1'b1)) ? (lrat_datain_size_gte_16GB) : + lrat_entry1_cmpmask_q[2]; + assign lrat_entry1_cmpmask_d[3] = ((lrat_entry1_wren == 1'b1)) ? (lrat_datain_size_gte_4GB) : + lrat_entry1_cmpmask_q[3]; + assign lrat_entry1_cmpmask_d[4] = ((lrat_entry1_wren == 1'b1)) ? (lrat_datain_size_gte_1GB) : + lrat_entry1_cmpmask_q[4]; + assign lrat_entry1_cmpmask_d[5] = ((lrat_entry1_wren == 1'b1)) ? (lrat_datain_size_gte_256MB) : + lrat_entry1_cmpmask_q[5]; + assign lrat_entry1_cmpmask_d[6] = ((lrat_entry1_wren == 1'b1)) ? (lrat_datain_size_gte_16MB) : + lrat_entry1_cmpmask_q[6]; + // size entry_xbitmask: 0123456 + // 1TB 1000000 + // 256GB 0100000 + // 16GB 0010000 + // 4GB 0001000 + // 1GB 0000100 + // 256MB 0000010 + // 16MB 0000001 + // 1MB 0000000 + assign lrat_entry1_xbitmask_d[0] = ((lrat_entry1_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_1TB) : + lrat_entry1_xbitmask_q[0]; + assign lrat_entry1_xbitmask_d[1] = ((lrat_entry1_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_256GB) : + lrat_entry1_xbitmask_q[1]; + assign lrat_entry1_xbitmask_d[2] = ((lrat_entry1_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_16GB) : + lrat_entry1_xbitmask_q[2]; + assign lrat_entry1_xbitmask_d[3] = ((lrat_entry1_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_4GB) : + lrat_entry1_xbitmask_q[3]; + assign lrat_entry1_xbitmask_d[4] = ((lrat_entry1_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_1GB) : + lrat_entry1_xbitmask_q[4]; + assign lrat_entry1_xbitmask_d[5] = ((lrat_entry1_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_256MB) : + lrat_entry1_xbitmask_q[5]; + assign lrat_entry1_xbitmask_d[6] = ((lrat_entry1_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_16MB) : + lrat_entry1_xbitmask_q[6]; + assign lrat_entry2_wren = ((|(ex6_valid_q) == 1'b1 & ex6_ttype_q[1] == 1'b1 & ex6_hv_state_q == 1'b1 & ex6_atsel_q == 1'b1 & ex6_hes_q == 1'b0 & (ex6_wq_q == 2'b00 | ex6_wq_q == 2'b11) & ex6_esel_q == 3'b010 & ex6_illeg_instr[1] == 1'b0)) ? 1'b1 : + 1'b0; + assign lrat_entry2_lpn_d = ((lrat_entry2_wren == 1'b1)) ? lrat_datain_lpn_q : + lrat_entry2_lpn_q; + assign lrat_entry2_rpn_d = ((lrat_entry2_wren == 1'b1)) ? lrat_datain_rpn_q : + lrat_entry2_rpn_q; + assign lrat_entry2_lpid_d = ((lrat_entry2_wren == 1'b1)) ? lrat_datain_lpid_q : + lrat_entry2_lpid_q; + assign lrat_entry2_size_d = ((lrat_entry2_wren == 1'b1)) ? lrat_datain_size_q : + lrat_entry2_size_q; + assign lrat_entry2_xbit_d = ((lrat_entry2_wren == 1'b1)) ? lrat_datain_xbit_q : + lrat_entry2_xbit_q; + assign lrat_entry2_valid_d = ((lrat_entry2_wren == 1'b1)) ? lrat_datain_valid_q : + lrat_entry2_valid_q; + // size entry_cmpmask: 0123456 + // 1TB 1111111 + // 256GB 0111111 + // 16GB 0011111 + // 4GB 0001111 + // 1GB 0000111 + // 256MB 0000011 + // 16MB 0000001 + // 1MB 0000000 + assign lrat_entry2_cmpmask_d[0] = ((lrat_entry2_wren == 1'b1)) ? (lrat_datain_size_gte_1TB) : + lrat_entry2_cmpmask_q[0]; + assign lrat_entry2_cmpmask_d[1] = ((lrat_entry2_wren == 1'b1)) ? (lrat_datain_size_gte_256GB) : + lrat_entry2_cmpmask_q[1]; + assign lrat_entry2_cmpmask_d[2] = ((lrat_entry2_wren == 1'b1)) ? (lrat_datain_size_gte_16GB) : + lrat_entry2_cmpmask_q[2]; + assign lrat_entry2_cmpmask_d[3] = ((lrat_entry2_wren == 1'b1)) ? (lrat_datain_size_gte_4GB) : + lrat_entry2_cmpmask_q[3]; + assign lrat_entry2_cmpmask_d[4] = ((lrat_entry2_wren == 1'b1)) ? (lrat_datain_size_gte_1GB) : + lrat_entry2_cmpmask_q[4]; + assign lrat_entry2_cmpmask_d[5] = ((lrat_entry2_wren == 1'b1)) ? (lrat_datain_size_gte_256MB) : + lrat_entry2_cmpmask_q[5]; + assign lrat_entry2_cmpmask_d[6] = ((lrat_entry2_wren == 1'b1)) ? (lrat_datain_size_gte_16MB) : + lrat_entry2_cmpmask_q[6]; + // size entry_xbitmask: 0123456 + // 1TB 1000000 + // 256GB 0100000 + // 16GB 0010000 + // 4GB 0001000 + // 1GB 0000100 + // 256MB 0000010 + // 16MB 0000001 + // 1MB 0000000 + assign lrat_entry2_xbitmask_d[0] = ((lrat_entry2_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_1TB) : + lrat_entry2_xbitmask_q[0]; + assign lrat_entry2_xbitmask_d[1] = ((lrat_entry2_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_256GB) : + lrat_entry2_xbitmask_q[1]; + assign lrat_entry2_xbitmask_d[2] = ((lrat_entry2_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_16GB) : + lrat_entry2_xbitmask_q[2]; + assign lrat_entry2_xbitmask_d[3] = ((lrat_entry2_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_4GB) : + lrat_entry2_xbitmask_q[3]; + assign lrat_entry2_xbitmask_d[4] = ((lrat_entry2_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_1GB) : + lrat_entry2_xbitmask_q[4]; + assign lrat_entry2_xbitmask_d[5] = ((lrat_entry2_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_256MB) : + lrat_entry2_xbitmask_q[5]; + assign lrat_entry2_xbitmask_d[6] = ((lrat_entry2_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_16MB) : + lrat_entry2_xbitmask_q[6]; + assign lrat_entry3_wren = ((|(ex6_valid_q) == 1'b1 & ex6_ttype_q[1] == 1'b1 & ex6_hv_state_q == 1'b1 & ex6_atsel_q == 1'b1 & ex6_hes_q == 1'b0 & (ex6_wq_q == 2'b00 | ex6_wq_q == 2'b11) & ex6_esel_q == 3'b011 & ex6_illeg_instr[1] == 1'b0)) ? 1'b1 : + 1'b0; + assign lrat_entry3_lpn_d = ((lrat_entry3_wren == 1'b1)) ? lrat_datain_lpn_q : + lrat_entry3_lpn_q; + assign lrat_entry3_rpn_d = ((lrat_entry3_wren == 1'b1)) ? lrat_datain_rpn_q : + lrat_entry3_rpn_q; + assign lrat_entry3_lpid_d = ((lrat_entry3_wren == 1'b1)) ? lrat_datain_lpid_q : + lrat_entry3_lpid_q; + assign lrat_entry3_size_d = ((lrat_entry3_wren == 1'b1)) ? lrat_datain_size_q : + lrat_entry3_size_q; + assign lrat_entry3_xbit_d = ((lrat_entry3_wren == 1'b1)) ? lrat_datain_xbit_q : + lrat_entry3_xbit_q; + assign lrat_entry3_valid_d = ((lrat_entry3_wren == 1'b1)) ? lrat_datain_valid_q : + lrat_entry3_valid_q; + // size entry_cmpmask: 0123456 + // 1TB 1111111 + // 256GB 0111111 + // 16GB 0011111 + // 4GB 0001111 + // 1GB 0000111 + // 256MB 0000011 + // 16MB 0000001 + // 1MB 0000000 + assign lrat_entry3_cmpmask_d[0] = ((lrat_entry3_wren == 1'b1)) ? (lrat_datain_size_gte_1TB) : + lrat_entry3_cmpmask_q[0]; + assign lrat_entry3_cmpmask_d[1] = ((lrat_entry3_wren == 1'b1)) ? (lrat_datain_size_gte_256GB) : + lrat_entry3_cmpmask_q[1]; + assign lrat_entry3_cmpmask_d[2] = ((lrat_entry3_wren == 1'b1)) ? (lrat_datain_size_gte_16GB) : + lrat_entry3_cmpmask_q[2]; + assign lrat_entry3_cmpmask_d[3] = ((lrat_entry3_wren == 1'b1)) ? (lrat_datain_size_gte_4GB) : + lrat_entry3_cmpmask_q[3]; + assign lrat_entry3_cmpmask_d[4] = ((lrat_entry3_wren == 1'b1)) ? (lrat_datain_size_gte_1GB) : + lrat_entry3_cmpmask_q[4]; + assign lrat_entry3_cmpmask_d[5] = ((lrat_entry3_wren == 1'b1)) ? (lrat_datain_size_gte_256MB) : + lrat_entry3_cmpmask_q[5]; + assign lrat_entry3_cmpmask_d[6] = ((lrat_entry3_wren == 1'b1)) ? (lrat_datain_size_gte_16MB) : + lrat_entry3_cmpmask_q[6]; + // size entry_xbitmask: 0123456 + // 1TB 1000000 + // 256GB 0100000 + // 16GB 0010000 + // 4GB 0001000 + // 1GB 0000100 + // 256MB 0000010 + // 16MB 0000001 + // 1MB 0000000 + assign lrat_entry3_xbitmask_d[0] = ((lrat_entry3_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_1TB) : + lrat_entry3_xbitmask_q[0]; + assign lrat_entry3_xbitmask_d[1] = ((lrat_entry3_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_256GB) : + lrat_entry3_xbitmask_q[1]; + assign lrat_entry3_xbitmask_d[2] = ((lrat_entry3_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_16GB) : + lrat_entry3_xbitmask_q[2]; + assign lrat_entry3_xbitmask_d[3] = ((lrat_entry3_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_4GB) : + lrat_entry3_xbitmask_q[3]; + assign lrat_entry3_xbitmask_d[4] = ((lrat_entry3_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_1GB) : + lrat_entry3_xbitmask_q[4]; + assign lrat_entry3_xbitmask_d[5] = ((lrat_entry3_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_256MB) : + lrat_entry3_xbitmask_q[5]; + assign lrat_entry3_xbitmask_d[6] = ((lrat_entry3_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_16MB) : + lrat_entry3_xbitmask_q[6]; + assign lrat_entry4_wren = ((|(ex6_valid_q) == 1'b1 & ex6_ttype_q[1] == 1'b1 & ex6_hv_state_q == 1'b1 & ex6_atsel_q == 1'b1 & ex6_hes_q == 1'b0 & (ex6_wq_q == 2'b00 | ex6_wq_q == 2'b11) & ex6_esel_q == 3'b100 & ex6_illeg_instr[1] == 1'b0)) ? 1'b1 : + 1'b0; + assign lrat_entry4_lpn_d = ((lrat_entry4_wren == 1'b1)) ? lrat_datain_lpn_q : + lrat_entry4_lpn_q; + assign lrat_entry4_rpn_d = ((lrat_entry4_wren == 1'b1)) ? lrat_datain_rpn_q : + lrat_entry4_rpn_q; + assign lrat_entry4_lpid_d = ((lrat_entry4_wren == 1'b1)) ? lrat_datain_lpid_q : + lrat_entry4_lpid_q; + assign lrat_entry4_size_d = ((lrat_entry4_wren == 1'b1)) ? lrat_datain_size_q : + lrat_entry4_size_q; + assign lrat_entry4_xbit_d = ((lrat_entry4_wren == 1'b1)) ? lrat_datain_xbit_q : + lrat_entry4_xbit_q; + assign lrat_entry4_valid_d = ((lrat_entry4_wren == 1'b1)) ? lrat_datain_valid_q : + lrat_entry4_valid_q; + // size entry_cmpmask: 0123456 + // 1TB 1111111 + // 256GB 0111111 + // 16GB 0011111 + // 4GB 0001111 + // 1GB 0000111 + // 256MB 0000011 + // 16MB 0000001 + // 1MB 0000000 + assign lrat_entry4_cmpmask_d[0] = ((lrat_entry4_wren == 1'b1)) ? (lrat_datain_size_gte_1TB) : + lrat_entry4_cmpmask_q[0]; + assign lrat_entry4_cmpmask_d[1] = ((lrat_entry4_wren == 1'b1)) ? (lrat_datain_size_gte_256GB) : + lrat_entry4_cmpmask_q[1]; + assign lrat_entry4_cmpmask_d[2] = ((lrat_entry4_wren == 1'b1)) ? (lrat_datain_size_gte_16GB) : + lrat_entry4_cmpmask_q[2]; + assign lrat_entry4_cmpmask_d[3] = ((lrat_entry4_wren == 1'b1)) ? (lrat_datain_size_gte_4GB) : + lrat_entry4_cmpmask_q[3]; + assign lrat_entry4_cmpmask_d[4] = ((lrat_entry4_wren == 1'b1)) ? (lrat_datain_size_gte_1GB) : + lrat_entry4_cmpmask_q[4]; + assign lrat_entry4_cmpmask_d[5] = ((lrat_entry4_wren == 1'b1)) ? (lrat_datain_size_gte_256MB) : + lrat_entry4_cmpmask_q[5]; + assign lrat_entry4_cmpmask_d[6] = ((lrat_entry4_wren == 1'b1)) ? (lrat_datain_size_gte_16MB) : + lrat_entry4_cmpmask_q[6]; + // size entry_xbitmask: 0123456 + // 1TB 1000000 + // 256GB 0100000 + // 16GB 0010000 + // 4GB 0001000 + // 1GB 0000100 + // 256MB 0000010 + // 16MB 0000001 + // 1MB 0000000 + assign lrat_entry4_xbitmask_d[0] = ((lrat_entry4_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_1TB) : + lrat_entry4_xbitmask_q[0]; + assign lrat_entry4_xbitmask_d[1] = ((lrat_entry4_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_256GB) : + lrat_entry4_xbitmask_q[1]; + assign lrat_entry4_xbitmask_d[2] = ((lrat_entry4_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_16GB) : + lrat_entry4_xbitmask_q[2]; + assign lrat_entry4_xbitmask_d[3] = ((lrat_entry4_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_4GB) : + lrat_entry4_xbitmask_q[3]; + assign lrat_entry4_xbitmask_d[4] = ((lrat_entry4_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_1GB) : + lrat_entry4_xbitmask_q[4]; + assign lrat_entry4_xbitmask_d[5] = ((lrat_entry4_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_256MB) : + lrat_entry4_xbitmask_q[5]; + assign lrat_entry4_xbitmask_d[6] = ((lrat_entry4_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_16MB) : + lrat_entry4_xbitmask_q[6]; + assign lrat_entry5_wren = ((|(ex6_valid_q) == 1'b1 & ex6_ttype_q[1] == 1'b1 & ex6_hv_state_q == 1'b1 & ex6_atsel_q == 1'b1 & ex6_hes_q == 1'b0 & (ex6_wq_q == 2'b00 | ex6_wq_q == 2'b11) & ex6_esel_q == 3'b101 & ex6_illeg_instr[1] == 1'b0)) ? 1'b1 : + 1'b0; + assign lrat_entry5_lpn_d = ((lrat_entry5_wren == 1'b1)) ? lrat_datain_lpn_q : + lrat_entry5_lpn_q; + assign lrat_entry5_rpn_d = ((lrat_entry5_wren == 1'b1)) ? lrat_datain_rpn_q : + lrat_entry5_rpn_q; + assign lrat_entry5_lpid_d = ((lrat_entry5_wren == 1'b1)) ? lrat_datain_lpid_q : + lrat_entry5_lpid_q; + assign lrat_entry5_size_d = ((lrat_entry5_wren == 1'b1)) ? lrat_datain_size_q : + lrat_entry5_size_q; + assign lrat_entry5_xbit_d = ((lrat_entry5_wren == 1'b1)) ? lrat_datain_xbit_q : + lrat_entry5_xbit_q; + assign lrat_entry5_valid_d = ((lrat_entry5_wren == 1'b1)) ? lrat_datain_valid_q : + lrat_entry5_valid_q; + // size entry_cmpmask: 0123456 + // 1TB 1111111 + // 256GB 0111111 + // 16GB 0011111 + // 4GB 0001111 + // 1GB 0000111 + // 256MB 0000011 + // 16MB 0000001 + // 1MB 0000000 + assign lrat_entry5_cmpmask_d[0] = ((lrat_entry5_wren == 1'b1)) ? (lrat_datain_size_gte_1TB) : + lrat_entry5_cmpmask_q[0]; + assign lrat_entry5_cmpmask_d[1] = ((lrat_entry5_wren == 1'b1)) ? (lrat_datain_size_gte_256GB) : + lrat_entry5_cmpmask_q[1]; + assign lrat_entry5_cmpmask_d[2] = ((lrat_entry5_wren == 1'b1)) ? (lrat_datain_size_gte_16GB) : + lrat_entry5_cmpmask_q[2]; + assign lrat_entry5_cmpmask_d[3] = ((lrat_entry5_wren == 1'b1)) ? (lrat_datain_size_gte_4GB) : + lrat_entry5_cmpmask_q[3]; + assign lrat_entry5_cmpmask_d[4] = ((lrat_entry5_wren == 1'b1)) ? (lrat_datain_size_gte_1GB) : + lrat_entry5_cmpmask_q[4]; + assign lrat_entry5_cmpmask_d[5] = ((lrat_entry5_wren == 1'b1)) ? (lrat_datain_size_gte_256MB) : + lrat_entry5_cmpmask_q[5]; + assign lrat_entry5_cmpmask_d[6] = ((lrat_entry5_wren == 1'b1)) ? (lrat_datain_size_gte_16MB) : + lrat_entry5_cmpmask_q[6]; + // size entry_xbitmask: 0123456 + // 1TB 1000000 + // 256GB 0100000 + // 16GB 0010000 + // 4GB 0001000 + // 1GB 0000100 + // 256MB 0000010 + // 16MB 0000001 + // 1MB 0000000 + assign lrat_entry5_xbitmask_d[0] = ((lrat_entry5_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_1TB) : + lrat_entry5_xbitmask_q[0]; + assign lrat_entry5_xbitmask_d[1] = ((lrat_entry5_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_256GB) : + lrat_entry5_xbitmask_q[1]; + assign lrat_entry5_xbitmask_d[2] = ((lrat_entry5_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_16GB) : + lrat_entry5_xbitmask_q[2]; + assign lrat_entry5_xbitmask_d[3] = ((lrat_entry5_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_4GB) : + lrat_entry5_xbitmask_q[3]; + assign lrat_entry5_xbitmask_d[4] = ((lrat_entry5_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_1GB) : + lrat_entry5_xbitmask_q[4]; + assign lrat_entry5_xbitmask_d[5] = ((lrat_entry5_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_256MB) : + lrat_entry5_xbitmask_q[5]; + assign lrat_entry5_xbitmask_d[6] = ((lrat_entry5_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_16MB) : + lrat_entry5_xbitmask_q[6]; + assign lrat_entry6_wren = ((|(ex6_valid_q) == 1'b1 & ex6_ttype_q[1] == 1'b1 & ex6_hv_state_q == 1'b1 & ex6_atsel_q == 1'b1 & ex6_hes_q == 1'b0 & (ex6_wq_q == 2'b00 | ex6_wq_q == 2'b11) & ex6_esel_q == 3'b110 & ex6_illeg_instr[1] == 1'b0)) ? 1'b1 : + 1'b0; + assign lrat_entry6_lpn_d = ((lrat_entry6_wren == 1'b1)) ? lrat_datain_lpn_q : + lrat_entry6_lpn_q; + assign lrat_entry6_rpn_d = ((lrat_entry6_wren == 1'b1)) ? lrat_datain_rpn_q : + lrat_entry6_rpn_q; + assign lrat_entry6_lpid_d = ((lrat_entry6_wren == 1'b1)) ? lrat_datain_lpid_q : + lrat_entry6_lpid_q; + assign lrat_entry6_size_d = ((lrat_entry6_wren == 1'b1)) ? lrat_datain_size_q : + lrat_entry6_size_q; + assign lrat_entry6_xbit_d = ((lrat_entry6_wren == 1'b1)) ? lrat_datain_xbit_q : + lrat_entry6_xbit_q; + assign lrat_entry6_valid_d = ((lrat_entry6_wren == 1'b1)) ? lrat_datain_valid_q : + lrat_entry6_valid_q; + // size entry_cmpmask: 0123456 + // 1TB 1111111 + // 256GB 0111111 + // 16GB 0011111 + // 4GB 0001111 + // 1GB 0000111 + // 256MB 0000011 + // 16MB 0000001 + // 1MB 0000000 + assign lrat_entry6_cmpmask_d[0] = ((lrat_entry6_wren == 1'b1)) ? (lrat_datain_size_gte_1TB) : + lrat_entry6_cmpmask_q[0]; + assign lrat_entry6_cmpmask_d[1] = ((lrat_entry6_wren == 1'b1)) ? (lrat_datain_size_gte_256GB) : + lrat_entry6_cmpmask_q[1]; + assign lrat_entry6_cmpmask_d[2] = ((lrat_entry6_wren == 1'b1)) ? (lrat_datain_size_gte_16GB) : + lrat_entry6_cmpmask_q[2]; + assign lrat_entry6_cmpmask_d[3] = ((lrat_entry6_wren == 1'b1)) ? (lrat_datain_size_gte_4GB) : + lrat_entry6_cmpmask_q[3]; + assign lrat_entry6_cmpmask_d[4] = ((lrat_entry6_wren == 1'b1)) ? (lrat_datain_size_gte_1GB) : + lrat_entry6_cmpmask_q[4]; + assign lrat_entry6_cmpmask_d[5] = ((lrat_entry6_wren == 1'b1)) ? (lrat_datain_size_gte_256MB) : + lrat_entry6_cmpmask_q[5]; + assign lrat_entry6_cmpmask_d[6] = ((lrat_entry6_wren == 1'b1)) ? (lrat_datain_size_gte_16MB) : + lrat_entry6_cmpmask_q[6]; + // size entry_xbitmask: 0123456 + // 1TB 1000000 + // 256GB 0100000 + // 16GB 0010000 + // 4GB 0001000 + // 1GB 0000100 + // 256MB 0000010 + // 16MB 0000001 + // 1MB 0000000 + assign lrat_entry6_xbitmask_d[0] = ((lrat_entry6_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_1TB) : + lrat_entry6_xbitmask_q[0]; + assign lrat_entry6_xbitmask_d[1] = ((lrat_entry6_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_256GB) : + lrat_entry6_xbitmask_q[1]; + assign lrat_entry6_xbitmask_d[2] = ((lrat_entry6_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_16GB) : + lrat_entry6_xbitmask_q[2]; + assign lrat_entry6_xbitmask_d[3] = ((lrat_entry6_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_4GB) : + lrat_entry6_xbitmask_q[3]; + assign lrat_entry6_xbitmask_d[4] = ((lrat_entry6_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_1GB) : + lrat_entry6_xbitmask_q[4]; + assign lrat_entry6_xbitmask_d[5] = ((lrat_entry6_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_256MB) : + lrat_entry6_xbitmask_q[5]; + assign lrat_entry6_xbitmask_d[6] = ((lrat_entry6_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_16MB) : + lrat_entry6_xbitmask_q[6]; + assign lrat_entry7_wren = ((|(ex6_valid_q) == 1'b1 & ex6_ttype_q[1] == 1'b1 & ex6_hv_state_q == 1'b1 & ex6_atsel_q == 1'b1 & ex6_hes_q == 1'b0 & (ex6_wq_q == 2'b00 | ex6_wq_q == 2'b11) & ex6_esel_q == 3'b111 & ex6_illeg_instr[1] == 1'b0)) ? 1'b1 : + 1'b0; + assign lrat_entry7_lpn_d = ((lrat_entry7_wren == 1'b1)) ? lrat_datain_lpn_q : + lrat_entry7_lpn_q; + assign lrat_entry7_rpn_d = ((lrat_entry7_wren == 1'b1)) ? lrat_datain_rpn_q : + lrat_entry7_rpn_q; + assign lrat_entry7_lpid_d = ((lrat_entry7_wren == 1'b1)) ? lrat_datain_lpid_q : + lrat_entry7_lpid_q; + assign lrat_entry7_size_d = ((lrat_entry7_wren == 1'b1)) ? lrat_datain_size_q : + lrat_entry7_size_q; + assign lrat_entry7_xbit_d = ((lrat_entry7_wren == 1'b1)) ? lrat_datain_xbit_q : + lrat_entry7_xbit_q; + assign lrat_entry7_valid_d = ((lrat_entry7_wren == 1'b1)) ? lrat_datain_valid_q : + lrat_entry7_valid_q; + // size entry_cmpmask: 0123456 + // 1TB 1111111 + // 256GB 0111111 + // 16GB 0011111 + // 4GB 0001111 + // 1GB 0000111 + // 256MB 0000011 + // 16MB 0000001 + // 1MB 0000000 + assign lrat_entry7_cmpmask_d[0] = ((lrat_entry7_wren == 1'b1)) ? (lrat_datain_size_gte_1TB) : + lrat_entry7_cmpmask_q[0]; + assign lrat_entry7_cmpmask_d[1] = ((lrat_entry7_wren == 1'b1)) ? (lrat_datain_size_gte_256GB) : + lrat_entry7_cmpmask_q[1]; + assign lrat_entry7_cmpmask_d[2] = ((lrat_entry7_wren == 1'b1)) ? (lrat_datain_size_gte_16GB) : + lrat_entry7_cmpmask_q[2]; + assign lrat_entry7_cmpmask_d[3] = ((lrat_entry7_wren == 1'b1)) ? (lrat_datain_size_gte_4GB) : + lrat_entry7_cmpmask_q[3]; + assign lrat_entry7_cmpmask_d[4] = ((lrat_entry7_wren == 1'b1)) ? (lrat_datain_size_gte_1GB) : + lrat_entry7_cmpmask_q[4]; + assign lrat_entry7_cmpmask_d[5] = ((lrat_entry7_wren == 1'b1)) ? (lrat_datain_size_gte_256MB) : + lrat_entry7_cmpmask_q[5]; + assign lrat_entry7_cmpmask_d[6] = ((lrat_entry7_wren == 1'b1)) ? (lrat_datain_size_gte_16MB) : + lrat_entry7_cmpmask_q[6]; + // size entry_xbitmask: 0123456 + // 1TB 1000000 + // 256GB 0100000 + // 16GB 0010000 + // 4GB 0001000 + // 1GB 0000100 + // 256MB 0000010 + // 16MB 0000001 + // 1MB 0000000 + assign lrat_entry7_xbitmask_d[0] = ((lrat_entry7_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_1TB) : + lrat_entry7_xbitmask_q[0]; + assign lrat_entry7_xbitmask_d[1] = ((lrat_entry7_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_256GB) : + lrat_entry7_xbitmask_q[1]; + assign lrat_entry7_xbitmask_d[2] = ((lrat_entry7_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_16GB) : + lrat_entry7_xbitmask_q[2]; + assign lrat_entry7_xbitmask_d[3] = ((lrat_entry7_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_4GB) : + lrat_entry7_xbitmask_q[3]; + assign lrat_entry7_xbitmask_d[4] = ((lrat_entry7_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_1GB) : + lrat_entry7_xbitmask_q[4]; + assign lrat_entry7_xbitmask_d[5] = ((lrat_entry7_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_256MB) : + lrat_entry7_xbitmask_q[5]; + assign lrat_entry7_xbitmask_d[6] = ((lrat_entry7_wren == 1'b1)) ? (lrat_datain_size_q == LRAT_PgSize_16MB) : + lrat_entry7_xbitmask_q[6]; + // power clock gating for entries + assign lrat_entry_act_d[0:7] = {8{((|(ex5_valid_q) & ex5_atsel_q) | mmucr2_act_override) & xu_mm_ccr2_notlb_b}}; + // these are tag1 phase matchline components + + mmq_tlb_lrat_matchline #(.HAVE_XBIT(1), + .NUM_PGSIZES(8), + .HAVE_CMPMASK(1)) + matchline_comb0( + .vdd(vdd), + .gnd(gnd), + .addr_in(lrat_tag1_lpn_q[64 - `REAL_ADDR_WIDTH:64 - `LRAT_MINSIZE_LOG2 - 1]), + .addr_enable(addr_enable), + .entry_size(lrat_entry0_size_q[0:3]), + .entry_cmpmask(lrat_entry0_cmpmask_q[0:6]), + .entry_xbit(lrat_entry0_xbit_q), + .entry_xbitmask(lrat_entry0_xbitmask_q[0:6]), + .entry_lpn(lrat_entry0_lpn_q[64 - `REAL_ADDR_WIDTH:64 - `LRAT_MINSIZE_LOG2 - 1]), + .entry_lpid(lrat_entry0_lpid_q[0:`LPID_WIDTH - 1]), + .comp_lpid(lrat_tag1_lpid_q[0:`LPID_WIDTH - 1]), + .lpid_enable(lpid_enable), + .entry_v(lrat_entry0_valid_q), + + .match(lrat_tag1_matchline[0]), + + .dbg_addr_match(lrat_entry0_addr_match), + + .dbg_lpid_match(lrat_entry0_lpid_match) + ); + + mmq_tlb_lrat_matchline #(.HAVE_XBIT(1), + .NUM_PGSIZES(8), + .HAVE_CMPMASK(1)) + matchline_comb1( + .vdd(vdd), + .gnd(gnd), + .addr_in(lrat_tag1_lpn_q[64 - `REAL_ADDR_WIDTH:64 - `LRAT_MINSIZE_LOG2 - 1]), + .addr_enable(addr_enable), + .entry_size(lrat_entry1_size_q[0:3]), + .entry_cmpmask(lrat_entry1_cmpmask_q[0:6]), + .entry_xbit(lrat_entry1_xbit_q), + .entry_xbitmask(lrat_entry1_xbitmask_q[0:6]), + .entry_lpn(lrat_entry1_lpn_q[64 - `REAL_ADDR_WIDTH:64 - `LRAT_MINSIZE_LOG2 - 1]), + .entry_lpid(lrat_entry1_lpid_q[0:`LPID_WIDTH - 1]), + .comp_lpid(lrat_tag1_lpid_q[0:`LPID_WIDTH - 1]), + .lpid_enable(lpid_enable), + .entry_v(lrat_entry1_valid_q), + + .match(lrat_tag1_matchline[1]), + + .dbg_addr_match(lrat_entry1_addr_match), + + .dbg_lpid_match(lrat_entry1_lpid_match) + ); + + mmq_tlb_lrat_matchline #(.HAVE_XBIT(1), + .NUM_PGSIZES(8), + .HAVE_CMPMASK(1)) + matchline_comb2( + .vdd(vdd), + .gnd(gnd), + .addr_in(lrat_tag1_lpn_q[64 - `REAL_ADDR_WIDTH:64 - `LRAT_MINSIZE_LOG2 - 1]), + .addr_enable(addr_enable), + .entry_size(lrat_entry2_size_q[0:3]), + .entry_cmpmask(lrat_entry2_cmpmask_q[0:6]), + .entry_xbit(lrat_entry2_xbit_q), + .entry_xbitmask(lrat_entry2_xbitmask_q[0:6]), + .entry_lpn(lrat_entry2_lpn_q[64 - `REAL_ADDR_WIDTH:64 - `LRAT_MINSIZE_LOG2 - 1]), + .entry_lpid(lrat_entry2_lpid_q[0:`LPID_WIDTH - 1]), + .comp_lpid(lrat_tag1_lpid_q[0:`LPID_WIDTH - 1]), + .lpid_enable(lpid_enable), + .entry_v(lrat_entry2_valid_q), + + .match(lrat_tag1_matchline[2]), + + .dbg_addr_match(lrat_entry2_addr_match), + + .dbg_lpid_match(lrat_entry2_lpid_match) + ); + + mmq_tlb_lrat_matchline #(.HAVE_XBIT(1), + .NUM_PGSIZES(8), + .HAVE_CMPMASK(1)) + matchline_comb3( + .vdd(vdd), + .gnd(gnd), + .addr_in(lrat_tag1_lpn_q[64 - `REAL_ADDR_WIDTH:64 - `LRAT_MINSIZE_LOG2 - 1]), + .addr_enable(addr_enable), + .entry_size(lrat_entry3_size_q[0:3]), + .entry_cmpmask(lrat_entry3_cmpmask_q[0:6]), + .entry_xbit(lrat_entry3_xbit_q), + .entry_xbitmask(lrat_entry3_xbitmask_q[0:6]), + .entry_lpn(lrat_entry3_lpn_q[64 - `REAL_ADDR_WIDTH:64 - `LRAT_MINSIZE_LOG2 - 1]), + .entry_lpid(lrat_entry3_lpid_q[0:`LPID_WIDTH - 1]), + .comp_lpid(lrat_tag1_lpid_q[0:`LPID_WIDTH - 1]), + .lpid_enable(lpid_enable), + .entry_v(lrat_entry3_valid_q), + + .match(lrat_tag1_matchline[3]), + + .dbg_addr_match(lrat_entry3_addr_match), + + .dbg_lpid_match(lrat_entry3_lpid_match) + ); + + mmq_tlb_lrat_matchline #(.HAVE_XBIT(1), + .NUM_PGSIZES(8), + .HAVE_CMPMASK(1)) + matchline_comb4( + .vdd(vdd), + .gnd(gnd), + .addr_in(lrat_tag1_lpn_q[64 - `REAL_ADDR_WIDTH:64 - `LRAT_MINSIZE_LOG2 - 1]), + .addr_enable(addr_enable), + .entry_size(lrat_entry4_size_q[0:3]), + .entry_cmpmask(lrat_entry4_cmpmask_q[0:6]), + .entry_xbit(lrat_entry4_xbit_q), + .entry_xbitmask(lrat_entry4_xbitmask_q[0:6]), + .entry_lpn(lrat_entry4_lpn_q[64 - `REAL_ADDR_WIDTH:64 - `LRAT_MINSIZE_LOG2 - 1]), + .entry_lpid(lrat_entry4_lpid_q[0:`LPID_WIDTH - 1]), + .comp_lpid(lrat_tag1_lpid_q[0:`LPID_WIDTH - 1]), + .lpid_enable(lpid_enable), + .entry_v(lrat_entry4_valid_q), + + .match(lrat_tag1_matchline[4]), + + .dbg_addr_match(lrat_entry4_addr_match), + + .dbg_lpid_match(lrat_entry4_lpid_match) + ); + + mmq_tlb_lrat_matchline #(.HAVE_XBIT(1), + .NUM_PGSIZES(8), + .HAVE_CMPMASK(1)) + matchline_comb5( + .vdd(vdd), + .gnd(gnd), + .addr_in(lrat_tag1_lpn_q[64 - `REAL_ADDR_WIDTH:64 - `LRAT_MINSIZE_LOG2 - 1]), + .addr_enable(addr_enable), + .entry_size(lrat_entry5_size_q[0:3]), + .entry_cmpmask(lrat_entry5_cmpmask_q[0:6]), + .entry_xbit(lrat_entry5_xbit_q), + .entry_xbitmask(lrat_entry5_xbitmask_q[0:6]), + .entry_lpn(lrat_entry5_lpn_q[64 - `REAL_ADDR_WIDTH:64 - `LRAT_MINSIZE_LOG2 - 1]), + .entry_lpid(lrat_entry5_lpid_q[0:`LPID_WIDTH - 1]), + .comp_lpid(lrat_tag1_lpid_q[0:`LPID_WIDTH - 1]), + .lpid_enable(lpid_enable), + .entry_v(lrat_entry5_valid_q), + + .match(lrat_tag1_matchline[5]), + + .dbg_addr_match(lrat_entry5_addr_match), + + .dbg_lpid_match(lrat_entry5_lpid_match) + ); + + mmq_tlb_lrat_matchline #(.HAVE_XBIT(1), + .NUM_PGSIZES(8), + .HAVE_CMPMASK(1)) + matchline_comb6( + .vdd(vdd), + .gnd(gnd), + .addr_in(lrat_tag1_lpn_q[64 - `REAL_ADDR_WIDTH:64 - `LRAT_MINSIZE_LOG2 - 1]), + .addr_enable(addr_enable), + .entry_size(lrat_entry6_size_q[0:3]), + .entry_cmpmask(lrat_entry6_cmpmask_q[0:6]), + .entry_xbit(lrat_entry6_xbit_q), + .entry_xbitmask(lrat_entry6_xbitmask_q[0:6]), + .entry_lpn(lrat_entry6_lpn_q[64 - `REAL_ADDR_WIDTH:64 - `LRAT_MINSIZE_LOG2 - 1]), + .entry_lpid(lrat_entry6_lpid_q[0:`LPID_WIDTH - 1]), + .comp_lpid(lrat_tag1_lpid_q[0:`LPID_WIDTH - 1]), + .lpid_enable(lpid_enable), + .entry_v(lrat_entry6_valid_q), + + .match(lrat_tag1_matchline[6]), + + .dbg_addr_match(lrat_entry6_addr_match), + + .dbg_lpid_match(lrat_entry6_lpid_match) + ); + + mmq_tlb_lrat_matchline #(.HAVE_XBIT(1), + .NUM_PGSIZES(8), + .HAVE_CMPMASK(1)) + matchline_comb7( + .vdd(vdd), + .gnd(gnd), + .addr_in(lrat_tag1_lpn_q[64 - `REAL_ADDR_WIDTH:64 - `LRAT_MINSIZE_LOG2 - 1]), + .addr_enable(addr_enable), + .entry_size(lrat_entry7_size_q[0:3]), + .entry_cmpmask(lrat_entry7_cmpmask_q[0:6]), + .entry_xbit(lrat_entry7_xbit_q), + .entry_xbitmask(lrat_entry7_xbitmask_q[0:6]), + .entry_lpn(lrat_entry7_lpn_q[64 - `REAL_ADDR_WIDTH:64 - `LRAT_MINSIZE_LOG2 - 1]), + .entry_lpid(lrat_entry7_lpid_q[0:`LPID_WIDTH - 1]), + .comp_lpid(lrat_tag1_lpid_q[0:`LPID_WIDTH - 1]), + .lpid_enable(lpid_enable), + .entry_v(lrat_entry7_valid_q), + + .match(lrat_tag1_matchline[7]), + + .dbg_addr_match(lrat_entry7_addr_match), + + .dbg_lpid_match(lrat_entry7_lpid_match) + ); + + //--------------------------------------------------------------------- + // output assignments + //--------------------------------------------------------------------- + assign lrat_tag3_lpn = lrat_tag3_lpn_q[64 - `REAL_ADDR_WIDTH:51]; + assign lrat_tag3_rpn = lrat_tag3_rpn_q[64 - `REAL_ADDR_WIDTH:51]; + assign lrat_tag3_hit_status = lrat_tag3_hit_status_q; + assign lrat_tag3_hit_entry = lrat_tag3_hit_entry_q; + assign lrat_tag4_lpn = lrat_tag4_lpn_q[64 - `REAL_ADDR_WIDTH:51]; + assign lrat_tag4_rpn = lrat_tag4_rpn_q[64 - `REAL_ADDR_WIDTH:51]; + assign lrat_tag4_hit_status = lrat_tag4_hit_status_q; + assign lrat_tag4_hit_entry = lrat_tag4_hit_entry_q; + assign lrat_mas0_esel = lrat_tag4_hit_entry_q; + assign lrat_mas1_v = lrat_mas1_v_q; + assign lrat_mas1_tsize = lrat_mas1_tsize_q; + generate + if (`REAL_ADDR_WIDTH > 32) + begin : gen64_lrat_mas2_epn + assign lrat_mas2_epn[0:63 - `REAL_ADDR_WIDTH] = {22{1'b0}}; + assign lrat_mas2_epn[64 - `REAL_ADDR_WIDTH:31] = lrat_mas2_epn_q[64 - `REAL_ADDR_WIDTH:31]; + assign lrat_mas2_epn[32:51] = lrat_mas2_epn_q[32:51]; + end + endgenerate + generate + if (`REAL_ADDR_WIDTH < 33) + begin : gen32_lrat_mas2_epn + assign lrat_mas2_epn[0:63 - `REAL_ADDR_WIDTH] = {22{1'b0}}; + assign lrat_mas2_epn[64 - `REAL_ADDR_WIDTH:51] = lrat_mas2_epn_q[64 - `REAL_ADDR_WIDTH:51]; + end + endgenerate + assign lrat_mas3_rpnl = lrat_mas3_rpnl_q; + assign lrat_mas7_rpnu = lrat_mas7_rpnu_q; + assign lrat_mas8_tlpid = lrat_mas8_tlpid_q; + assign lrat_mas_tlbre = lrat_mas_tlbre_q; + assign lrat_mas_tlbsx_hit = lrat_mas_tlbsx_hit_q; + assign lrat_mas_tlbsx_miss = lrat_mas_tlbsx_miss_q; + assign lrat_mas_thdid = lrat_mas_thdid_q; + assign lrat_mmucr3_x = lrat_mmucr3_x_q; + assign lrat_dbg_tag1_addr_enable = addr_enable; + assign lrat_dbg_tag2_matchline_q = lrat_tag2_matchline_q; + assign lrat_dbg_entry0_addr_match = lrat_entry0_addr_match; + assign lrat_dbg_entry0_lpid_match = lrat_entry0_lpid_match; + assign lrat_dbg_entry0_entry_v = lrat_entry0_valid_q; + assign lrat_dbg_entry0_entry_x = lrat_entry0_xbit_q; + assign lrat_dbg_entry0_size = lrat_entry0_size_q; + assign lrat_dbg_entry1_addr_match = lrat_entry1_addr_match; + assign lrat_dbg_entry1_lpid_match = lrat_entry1_lpid_match; + assign lrat_dbg_entry1_entry_v = lrat_entry1_valid_q; + assign lrat_dbg_entry1_entry_x = lrat_entry1_xbit_q; + assign lrat_dbg_entry1_size = lrat_entry1_size_q; + assign lrat_dbg_entry2_addr_match = lrat_entry2_addr_match; + assign lrat_dbg_entry2_lpid_match = lrat_entry2_lpid_match; + assign lrat_dbg_entry2_entry_v = lrat_entry2_valid_q; + assign lrat_dbg_entry2_entry_x = lrat_entry2_xbit_q; + assign lrat_dbg_entry2_size = lrat_entry2_size_q; + assign lrat_dbg_entry3_addr_match = lrat_entry3_addr_match; + assign lrat_dbg_entry3_lpid_match = lrat_entry3_lpid_match; + assign lrat_dbg_entry3_entry_v = lrat_entry3_valid_q; + assign lrat_dbg_entry3_entry_x = lrat_entry3_xbit_q; + assign lrat_dbg_entry3_size = lrat_entry3_size_q; + assign lrat_dbg_entry4_addr_match = lrat_entry4_addr_match; + assign lrat_dbg_entry4_lpid_match = lrat_entry4_lpid_match; + assign lrat_dbg_entry4_entry_v = lrat_entry4_valid_q; + assign lrat_dbg_entry4_entry_x = lrat_entry4_xbit_q; + assign lrat_dbg_entry4_size = lrat_entry4_size_q; + assign lrat_dbg_entry5_addr_match = lrat_entry5_addr_match; + assign lrat_dbg_entry5_lpid_match = lrat_entry5_lpid_match; + assign lrat_dbg_entry5_entry_v = lrat_entry5_valid_q; + assign lrat_dbg_entry5_entry_x = lrat_entry5_xbit_q; + assign lrat_dbg_entry5_size = lrat_entry5_size_q; + assign lrat_dbg_entry6_addr_match = lrat_entry6_addr_match; + assign lrat_dbg_entry6_lpid_match = lrat_entry6_lpid_match; + assign lrat_dbg_entry6_entry_v = lrat_entry6_valid_q; + assign lrat_dbg_entry6_entry_x = lrat_entry6_xbit_q; + assign lrat_dbg_entry6_size = lrat_entry6_size_q; + assign lrat_dbg_entry7_addr_match = lrat_entry7_addr_match; + assign lrat_dbg_entry7_lpid_match = lrat_entry7_lpid_match; + assign lrat_dbg_entry7_entry_v = lrat_entry7_valid_q; + assign lrat_dbg_entry7_entry_x = lrat_entry7_xbit_q; + assign lrat_dbg_entry7_size = lrat_entry7_size_q; + // unused spare signal assignments + assign unused_dc[0] = |(lcb_delay_lclkr_dc[1:4]); + assign unused_dc[1] = |(lcb_mpw1_dc_b[1:4]); + assign unused_dc[2] = pc_func_sl_force; + assign unused_dc[3] = pc_func_sl_thold_0_b; + assign unused_dc[4] = tc_scan_dis_dc_b; + assign unused_dc[5] = tc_scan_diag_dc; + assign unused_dc[6] = tc_lbist_en_dc; + assign unused_dc[7] = |({tlb_tag0_type[0:1], tlb_tag0_type[3:5]}); + assign unused_dc[8] = ex6_ttype_q[0]; +`ifdef MM_THREADS2 + assign unused_dc[9] = |(mas2_0_epn[44:45]) | |(mas2_1_epn[44:45]); + assign unused_dc[10] = |(mas2_0_epn[46:47]) | |(mas2_1_epn[46:47]); + assign unused_dc[11] = |(mas2_0_epn[48:49]) | |(mas2_1_epn[48:49]); + assign unused_dc[12] = |(mas2_0_epn[50:51]) | |(mas2_1_epn[50:51]); +`else + assign unused_dc[9] = |(mas2_0_epn[44:45]); + assign unused_dc[10] = |(mas2_0_epn[46:47]); + assign unused_dc[11] = |(mas2_0_epn[48:49]); + assign unused_dc[12] = |(mas2_0_epn[50:51]); +`endif + assign unused_dc[13] = ex6_illeg_instr[0]; + + generate + begin : xhdl0 + genvar tid; + for (tid = 0; tid <= `THDID_WIDTH - 1; tid = tid + 1) + begin : lratunused + if (tid >= `MM_THREADS) + begin : lrattidNExist + assign unused_dc_threads[tid] = tlb_tag0_thdid[tid]; + end + end + end + endgenerate + + //--------------------------------------------------------------------- + // Latches + //--------------------------------------------------------------------- + // ex4 phase: valid latches + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex4_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex4_valid_offset:ex4_valid_offset + `MM_THREADS - 1]), + .scout(sov[ex4_valid_offset:ex4_valid_offset + `MM_THREADS - 1]), + .din(ex4_valid_d), + .dout(ex4_valid_q) + ); + // ex4 phase: ttype latches + + tri_rlmreg_p #(.WIDTH(`LRAT_TTYPE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex4_ttype_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex4_ttype_offset:ex4_ttype_offset + `LRAT_TTYPE_WIDTH - 1]), + .scout(sov[ex4_ttype_offset:ex4_ttype_offset + `LRAT_TTYPE_WIDTH - 1]), + .din(ex4_ttype_d), + .dout(ex4_ttype_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_hv_state_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex4_hv_state_offset]), + .scout(sov[ex4_hv_state_offset]), + .din(ex4_hv_state_d), + .dout(ex4_hv_state_q) + ); + // ex5 phase: valid latches + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex5_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex5_valid_offset:ex5_valid_offset + `MM_THREADS - 1]), + .scout(sov[ex5_valid_offset:ex5_valid_offset + `MM_THREADS - 1]), + .din(ex5_valid_d), + .dout(ex5_valid_q) + ); + // ex5 phase: ttype latches + + tri_rlmreg_p #(.WIDTH(`LRAT_TTYPE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex5_ttype_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex5_ttype_offset:ex5_ttype_offset + `LRAT_TTYPE_WIDTH - 1]), + .scout(sov[ex5_ttype_offset:ex5_ttype_offset + `LRAT_TTYPE_WIDTH - 1]), + .din(ex5_ttype_d), + .dout(ex5_ttype_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_hv_state_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex5_hv_state_offset]), + .scout(sov[ex5_hv_state_offset]), + .din(ex5_hv_state_d), + .dout(ex5_hv_state_q) + ); + // ex6 phase: valid latches + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex6_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex6_valid_offset:ex6_valid_offset + `MM_THREADS - 1]), + .scout(sov[ex6_valid_offset:ex6_valid_offset + `MM_THREADS - 1]), + .din(ex6_valid_d), + .dout(ex6_valid_q) + ); + // ex6 phase: ttype latches + + tri_rlmreg_p #(.WIDTH(`LRAT_TTYPE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex6_ttype_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex6_ttype_offset:ex6_ttype_offset + `LRAT_TTYPE_WIDTH - 1]), + .scout(sov[ex6_ttype_offset:ex6_ttype_offset + `LRAT_TTYPE_WIDTH - 1]), + .din(ex6_ttype_d), + .dout(ex6_ttype_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_hv_state_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex6_hv_state_offset]), + .scout(sov[ex6_hv_state_offset]), + .din(ex6_hv_state_d), + .dout(ex6_hv_state_q) + ); + // ex5 phase: esel latches + + tri_rlmreg_p #(.WIDTH(`LRAT_NUM_ENTRY_LOG2), .INIT(0), .NEEDS_SRESET(1)) ex5_esel_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex5_esel_offset:ex5_esel_offset + `LRAT_NUM_ENTRY_LOG2 - 1]), + .scout(sov[ex5_esel_offset:ex5_esel_offset + `LRAT_NUM_ENTRY_LOG2 - 1]), + .din(ex5_esel_d), + .dout(ex5_esel_q) + ); + // ex5 phase: atsel latches + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_atsel_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex5_atsel_offset]), + .scout(sov[ex5_atsel_offset]), + .din(ex5_atsel_d), + .dout(ex5_atsel_q) + ); + // ex5 phase: hes latches + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_hes_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex5_hes_offset]), + .scout(sov[ex5_hes_offset]), + .din(ex5_hes_d), + .dout(ex5_hes_q) + ); + // ex5 phase: wq latches + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex5_wq_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex5_wq_offset:ex5_wq_offset + 2 - 1]), + .scout(sov[ex5_wq_offset:ex5_wq_offset + 2 - 1]), + .din(ex5_wq_d), + .dout(ex5_wq_q) + ); + // ex6 phase: esel latches + + tri_rlmreg_p #(.WIDTH(`LRAT_NUM_ENTRY_LOG2), .INIT(0), .NEEDS_SRESET(1)) ex6_esel_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex6_esel_offset:ex6_esel_offset + `LRAT_NUM_ENTRY_LOG2 - 1]), + .scout(sov[ex6_esel_offset:ex6_esel_offset + `LRAT_NUM_ENTRY_LOG2 - 1]), + .din(ex6_esel_d), + .dout(ex6_esel_q) + ); + // ex6 phase: atsel latches + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_atsel_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex6_atsel_offset]), + .scout(sov[ex6_atsel_offset]), + .din(ex6_atsel_d), + .dout(ex6_atsel_q) + ); + // ex6 phase: hes latches + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_hes_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex6_hes_offset]), + .scout(sov[ex6_hes_offset]), + .din(ex6_hes_d), + .dout(ex6_hes_q) + ); + // ex6 phase: wq latches + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex6_wq_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ex6_wq_offset:ex6_wq_offset + 2 - 1]), + .scout(sov[ex6_wq_offset:ex6_wq_offset + 2 - 1]), + .din(ex6_wq_d), + .dout(ex6_wq_q) + ); + // tag1 phase: logical page number latches + + tri_rlmreg_p #(.WIDTH(`RPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lrat_tag1_lpn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[20 + 0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_tag1_lpn_offset:lrat_tag1_lpn_offset + `RPN_WIDTH - 1]), + .scout(sov[lrat_tag1_lpn_offset:lrat_tag1_lpn_offset + `RPN_WIDTH - 1]), + .din(lrat_tag1_lpn_d[64 - `REAL_ADDR_WIDTH:51]), + .dout(lrat_tag1_lpn_q[64 - `REAL_ADDR_WIDTH:51]) + ); + // tag2 phase: logical page number latches + + tri_rlmreg_p #(.WIDTH(`RPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lrat_tag2_lpn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[20 + 1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_tag2_lpn_offset:lrat_tag2_lpn_offset + `RPN_WIDTH - 1]), + .scout(sov[lrat_tag2_lpn_offset:lrat_tag2_lpn_offset + `RPN_WIDTH - 1]), + .din(lrat_tag2_lpn_d[64 - `REAL_ADDR_WIDTH:51]), + .dout(lrat_tag2_lpn_q[64 - `REAL_ADDR_WIDTH:51]) + ); + // tag3 phase: logical page number latches + + tri_rlmreg_p #(.WIDTH(`RPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lrat_tag3_lpn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[20 + 2]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_tag3_lpn_offset:lrat_tag3_lpn_offset + `RPN_WIDTH - 1]), + .scout(sov[lrat_tag3_lpn_offset:lrat_tag3_lpn_offset + `RPN_WIDTH - 1]), + .din(lrat_tag3_lpn_d[64 - `REAL_ADDR_WIDTH:51]), + .dout(lrat_tag3_lpn_q[64 - `REAL_ADDR_WIDTH:51]) + ); + // tag4 phase: logical page number latches + + tri_rlmreg_p #(.WIDTH(`RPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lrat_tag4_lpn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[20 + 3]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_tag4_lpn_offset:lrat_tag4_lpn_offset + `RPN_WIDTH - 1]), + .scout(sov[lrat_tag4_lpn_offset:lrat_tag4_lpn_offset + `RPN_WIDTH - 1]), + .din(lrat_tag4_lpn_d[64 - `REAL_ADDR_WIDTH:51]), + .dout(lrat_tag4_lpn_q[64 - `REAL_ADDR_WIDTH:51]) + ); + // tag3 phase: real page number latches + + tri_rlmreg_p #(.WIDTH(`RPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lrat_tag3_rpn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[20 + 2]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_tag3_rpn_offset:lrat_tag3_rpn_offset + `RPN_WIDTH - 1]), + .scout(sov[lrat_tag3_rpn_offset:lrat_tag3_rpn_offset + `RPN_WIDTH - 1]), + .din(lrat_tag3_rpn_d[64 - `REAL_ADDR_WIDTH:51]), + .dout(lrat_tag3_rpn_q[64 - `REAL_ADDR_WIDTH:51]) + ); + // tag4 phase: real page number latches + + tri_rlmreg_p #(.WIDTH(`RPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lrat_tag4_rpn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[20 + 3]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_tag4_rpn_offset:lrat_tag4_rpn_offset + `RPN_WIDTH - 1]), + .scout(sov[lrat_tag4_rpn_offset:lrat_tag4_rpn_offset + `RPN_WIDTH - 1]), + .din(lrat_tag4_rpn_d[64 - `REAL_ADDR_WIDTH:51]), + .dout(lrat_tag4_rpn_q[64 - `REAL_ADDR_WIDTH:51]) + ); + // tag3 phase: hit status latches + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lrat_tag3_hit_status_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[20 + 2]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_tag3_hit_status_offset:lrat_tag3_hit_status_offset + 4 - 1]), + .scout(sov[lrat_tag3_hit_status_offset:lrat_tag3_hit_status_offset + 4 - 1]), + .din(lrat_tag3_hit_status_d), + .dout(lrat_tag3_hit_status_q) + ); + // tag3 phase: hit entry latches + + tri_rlmreg_p #(.WIDTH(`LRAT_NUM_ENTRY_LOG2), .INIT(0), .NEEDS_SRESET(1)) lrat_tag3_hit_entry_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[20 + 2]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_tag3_hit_entry_offset:lrat_tag3_hit_entry_offset + `LRAT_NUM_ENTRY_LOG2 - 1]), + .scout(sov[lrat_tag3_hit_entry_offset:lrat_tag3_hit_entry_offset + `LRAT_NUM_ENTRY_LOG2 - 1]), + .din(lrat_tag3_hit_entry_d), + .dout(lrat_tag3_hit_entry_q) + ); + // tag4 phase: hit status latches + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lrat_tag4_hit_status_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[20 + 3]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_tag4_hit_status_offset:lrat_tag4_hit_status_offset + 4 - 1]), + .scout(sov[lrat_tag4_hit_status_offset:lrat_tag4_hit_status_offset + 4 - 1]), + .din(lrat_tag4_hit_status_d), + .dout(lrat_tag4_hit_status_q) + ); + // tag4 phase: hit entry latches + + tri_rlmreg_p #(.WIDTH(`LRAT_NUM_ENTRY_LOG2), .INIT(0), .NEEDS_SRESET(1)) lrat_tag4_hit_entry_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[20 + 3]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_tag4_hit_entry_offset:lrat_tag4_hit_entry_offset + `LRAT_NUM_ENTRY_LOG2 - 1]), + .scout(sov[lrat_tag4_hit_entry_offset:lrat_tag4_hit_entry_offset + `LRAT_NUM_ENTRY_LOG2 - 1]), + .din(lrat_tag4_hit_entry_d), + .dout(lrat_tag4_hit_entry_q) + ); + + tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lrat_tag1_lpid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[20]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_tag1_lpid_offset:lrat_tag1_lpid_offset + `LPID_WIDTH - 1]), + .scout(sov[lrat_tag1_lpid_offset:lrat_tag1_lpid_offset + `LPID_WIDTH - 1]), + .din(lrat_tag1_lpid_d), + .dout(lrat_tag1_lpid_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lrat_tag1_size_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[20]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_tag1_size_offset:lrat_tag1_size_offset + 4 - 1]), + .scout(sov[lrat_tag1_size_offset:lrat_tag1_size_offset + 4 - 1]), + .din(lrat_tag1_size_d), + .dout(lrat_tag1_size_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lrat_tag2_size_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[21]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_tag2_size_offset:lrat_tag2_size_offset + 4 - 1]), + .scout(sov[lrat_tag2_size_offset:lrat_tag2_size_offset + 4 - 1]), + .din(lrat_tag2_size_d), + .dout(lrat_tag2_size_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lrat_tag2_entry_size_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[21]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_tag2_entry_size_offset:lrat_tag2_entry_size_offset + 4 - 1]), + .scout(sov[lrat_tag2_entry_size_offset:lrat_tag2_entry_size_offset + 4 - 1]), + .din(lrat_tag2_entry_size_d), + .dout(lrat_tag2_entry_size_q) + ); + + tri_rlmreg_p #(.WIDTH(`LRAT_NUM_ENTRY), .INIT(0), .NEEDS_SRESET(1)) lrat_tag2_matchline_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[21]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_tag2_matchline_offset:lrat_tag2_matchline_offset + `LRAT_NUM_ENTRY - 1]), + .scout(sov[lrat_tag2_matchline_offset:lrat_tag2_matchline_offset + `LRAT_NUM_ENTRY - 1]), + .din(lrat_tag2_matchline_d), + .dout(lrat_tag2_matchline_q) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) tlb_addr_cap_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tlb_delayed_act[20]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[tlb_addr_cap_offset:tlb_addr_cap_offset + 2 - 1]), + .scout(sov[tlb_addr_cap_offset:tlb_addr_cap_offset + 2 - 1]), + .din(tlb_addr_cap_d), + .dout(tlb_addr_cap_q) + ); + + tri_rlmreg_p #(.WIDTH(64), .INIT(0), .NEEDS_SRESET(1)) spare_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[spare_offset:spare_offset + 64 - 1]), + .scout(sov[spare_offset:spare_offset + 64 - 1]), + .din(spare_q), + .dout(spare_q) + ); + + tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) lrat_entry_act_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry_act_offset:lrat_entry_act_offset + 8 - 1]), + .scout(sov[lrat_entry_act_offset:lrat_entry_act_offset + 8 - 1]), + .din(lrat_entry_act_d), + .dout(lrat_entry_act_q) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) lrat_mas_act_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_mas_act_offset:lrat_mas_act_offset + 3 - 1]), + .scout(sov[lrat_mas_act_offset:lrat_mas_act_offset + 3 - 1]), + .din(lrat_mas_act_d), + .dout(lrat_mas_act_q) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) lrat_datain_act_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_datain_act_offset:lrat_datain_act_offset + 2 - 1]), + .scout(sov[lrat_datain_act_offset:lrat_datain_act_offset + 2 - 1]), + .din(lrat_datain_act_d), + .dout(lrat_datain_act_q) + ); + // LRAT entry latches + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lrat_entry0_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry0_valid_offset]), + .scout(sov[lrat_entry0_valid_offset]), + .din(lrat_entry0_valid_d), + .dout(lrat_entry0_valid_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lrat_entry0_xbit_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry0_xbit_offset]), + .scout(sov[lrat_entry0_xbit_offset]), + .din(lrat_entry0_xbit_d), + .dout(lrat_entry0_xbit_q) + ); + + tri_rlmreg_p #(.WIDTH((64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1)), .INIT(0), .NEEDS_SRESET(1)) lrat_entry0_lpn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry0_lpn_offset:lrat_entry0_lpn_offset + (64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1) - 1]), + .scout(sov[lrat_entry0_lpn_offset:lrat_entry0_lpn_offset + (64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1) - 1]), + .din(lrat_entry0_lpn_d), + .dout(lrat_entry0_lpn_q) + ); + + tri_rlmreg_p #(.WIDTH((64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1)), .INIT(0), .NEEDS_SRESET(1)) lrat_entry0_rpn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry0_rpn_offset:lrat_entry0_rpn_offset + (64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1) - 1]), + .scout(sov[lrat_entry0_rpn_offset:lrat_entry0_rpn_offset + (64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1) - 1]), + .din(lrat_entry0_rpn_d), + .dout(lrat_entry0_rpn_q) + ); + + tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lrat_entry0_lpid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry0_lpid_offset:lrat_entry0_lpid_offset + `LPID_WIDTH - 1]), + .scout(sov[lrat_entry0_lpid_offset:lrat_entry0_lpid_offset + `LPID_WIDTH - 1]), + .din(lrat_entry0_lpid_d), + .dout(lrat_entry0_lpid_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lrat_entry0_size_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry0_size_offset:lrat_entry0_size_offset + 4 - 1]), + .scout(sov[lrat_entry0_size_offset:lrat_entry0_size_offset + 4 - 1]), + .din(lrat_entry0_size_d), + .dout(lrat_entry0_size_q) + ); + + tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(1)) lrat_entry0_cmpmask_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry0_cmpmask_offset:lrat_entry0_cmpmask_offset + 7 - 1]), + .scout(sov[lrat_entry0_cmpmask_offset:lrat_entry0_cmpmask_offset + 7 - 1]), + .din(lrat_entry0_cmpmask_d), + .dout(lrat_entry0_cmpmask_q) + ); + + tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(1)) lrat_entry0_xbitmask_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry0_xbitmask_offset:lrat_entry0_xbitmask_offset + 7 - 1]), + .scout(sov[lrat_entry0_xbitmask_offset:lrat_entry0_xbitmask_offset + 7 - 1]), + .din(lrat_entry0_xbitmask_d), + .dout(lrat_entry0_xbitmask_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lrat_entry1_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry1_valid_offset]), + .scout(sov[lrat_entry1_valid_offset]), + .din(lrat_entry1_valid_d), + .dout(lrat_entry1_valid_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lrat_entry1_xbit_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry1_xbit_offset]), + .scout(sov[lrat_entry1_xbit_offset]), + .din(lrat_entry1_xbit_d), + .dout(lrat_entry1_xbit_q) + ); + + tri_rlmreg_p #(.WIDTH((64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1)), .INIT(0), .NEEDS_SRESET(1)) lrat_entry1_lpn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry1_lpn_offset:lrat_entry1_lpn_offset + (64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1) - 1]), + .scout(sov[lrat_entry1_lpn_offset:lrat_entry1_lpn_offset + (64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1) - 1]), + .din(lrat_entry1_lpn_d), + .dout(lrat_entry1_lpn_q) + ); + + tri_rlmreg_p #(.WIDTH((64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1)), .INIT(0), .NEEDS_SRESET(1)) lrat_entry1_rpn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry1_rpn_offset:lrat_entry1_rpn_offset + (64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1) - 1]), + .scout(sov[lrat_entry1_rpn_offset:lrat_entry1_rpn_offset + (64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1) - 1]), + .din(lrat_entry1_rpn_d), + .dout(lrat_entry1_rpn_q) + ); + + tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lrat_entry1_lpid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry1_lpid_offset:lrat_entry1_lpid_offset + `LPID_WIDTH - 1]), + .scout(sov[lrat_entry1_lpid_offset:lrat_entry1_lpid_offset + `LPID_WIDTH - 1]), + .din(lrat_entry1_lpid_d), + .dout(lrat_entry1_lpid_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lrat_entry1_size_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry1_size_offset:lrat_entry1_size_offset + 4 - 1]), + .scout(sov[lrat_entry1_size_offset:lrat_entry1_size_offset + 4 - 1]), + .din(lrat_entry1_size_d), + .dout(lrat_entry1_size_q) + ); + + tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(1)) lrat_entry1_cmpmask_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry1_cmpmask_offset:lrat_entry1_cmpmask_offset + 7 - 1]), + .scout(sov[lrat_entry1_cmpmask_offset:lrat_entry1_cmpmask_offset + 7 - 1]), + .din(lrat_entry1_cmpmask_d), + .dout(lrat_entry1_cmpmask_q) + ); + + tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(1)) lrat_entry1_xbitmask_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry1_xbitmask_offset:lrat_entry1_xbitmask_offset + 7 - 1]), + .scout(sov[lrat_entry1_xbitmask_offset:lrat_entry1_xbitmask_offset + 7 - 1]), + .din(lrat_entry1_xbitmask_d), + .dout(lrat_entry1_xbitmask_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lrat_entry2_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[2]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry2_valid_offset]), + .scout(sov[lrat_entry2_valid_offset]), + .din(lrat_entry2_valid_d), + .dout(lrat_entry2_valid_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lrat_entry2_xbit_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[2]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry2_xbit_offset]), + .scout(sov[lrat_entry2_xbit_offset]), + .din(lrat_entry2_xbit_d), + .dout(lrat_entry2_xbit_q) + ); + + tri_rlmreg_p #(.WIDTH((64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1)), .INIT(0), .NEEDS_SRESET(1)) lrat_entry2_lpn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[2]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry2_lpn_offset:lrat_entry2_lpn_offset + (64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1) - 1]), + .scout(sov[lrat_entry2_lpn_offset:lrat_entry2_lpn_offset + (64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1) - 1]), + .din(lrat_entry2_lpn_d), + .dout(lrat_entry2_lpn_q) + ); + + tri_rlmreg_p #(.WIDTH((64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1)), .INIT(0), .NEEDS_SRESET(1)) lrat_entry2_rpn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[2]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry2_rpn_offset:lrat_entry2_rpn_offset + (64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1) - 1]), + .scout(sov[lrat_entry2_rpn_offset:lrat_entry2_rpn_offset + (64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1) - 1]), + .din(lrat_entry2_rpn_d), + .dout(lrat_entry2_rpn_q) + ); + + tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lrat_entry2_lpid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[2]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry2_lpid_offset:lrat_entry2_lpid_offset + `LPID_WIDTH - 1]), + .scout(sov[lrat_entry2_lpid_offset:lrat_entry2_lpid_offset + `LPID_WIDTH - 1]), + .din(lrat_entry2_lpid_d), + .dout(lrat_entry2_lpid_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lrat_entry2_size_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[2]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry2_size_offset:lrat_entry2_size_offset + 4 - 1]), + .scout(sov[lrat_entry2_size_offset:lrat_entry2_size_offset + 4 - 1]), + .din(lrat_entry2_size_d), + .dout(lrat_entry2_size_q) + ); + + tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(1)) lrat_entry2_cmpmask_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[2]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry2_cmpmask_offset:lrat_entry2_cmpmask_offset + 7 - 1]), + .scout(sov[lrat_entry2_cmpmask_offset:lrat_entry2_cmpmask_offset + 7 - 1]), + .din(lrat_entry2_cmpmask_d), + .dout(lrat_entry2_cmpmask_q) + ); + + tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(1)) lrat_entry2_xbitmask_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[2]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry2_xbitmask_offset:lrat_entry2_xbitmask_offset + 7 - 1]), + .scout(sov[lrat_entry2_xbitmask_offset:lrat_entry2_xbitmask_offset + 7 - 1]), + .din(lrat_entry2_xbitmask_d), + .dout(lrat_entry2_xbitmask_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lrat_entry3_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[3]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry3_valid_offset]), + .scout(sov[lrat_entry3_valid_offset]), + .din(lrat_entry3_valid_d), + .dout(lrat_entry3_valid_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lrat_entry3_xbit_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[3]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry3_xbit_offset]), + .scout(sov[lrat_entry3_xbit_offset]), + .din(lrat_entry3_xbit_d), + .dout(lrat_entry3_xbit_q) + ); + + tri_rlmreg_p #(.WIDTH((64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1)), .INIT(0), .NEEDS_SRESET(1)) lrat_entry3_lpn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[3]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry3_lpn_offset:lrat_entry3_lpn_offset + (64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1) - 1]), + .scout(sov[lrat_entry3_lpn_offset:lrat_entry3_lpn_offset + (64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1) - 1]), + .din(lrat_entry3_lpn_d), + .dout(lrat_entry3_lpn_q) + ); + + tri_rlmreg_p #(.WIDTH((64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1)), .INIT(0), .NEEDS_SRESET(1)) lrat_entry3_rpn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[3]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry3_rpn_offset:lrat_entry3_rpn_offset + (64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1) - 1]), + .scout(sov[lrat_entry3_rpn_offset:lrat_entry3_rpn_offset + (64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1) - 1]), + .din(lrat_entry3_rpn_d), + .dout(lrat_entry3_rpn_q) + ); + + tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lrat_entry3_lpid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[3]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry3_lpid_offset:lrat_entry3_lpid_offset + `LPID_WIDTH - 1]), + .scout(sov[lrat_entry3_lpid_offset:lrat_entry3_lpid_offset + `LPID_WIDTH - 1]), + .din(lrat_entry3_lpid_d), + .dout(lrat_entry3_lpid_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lrat_entry3_size_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[3]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry3_size_offset:lrat_entry3_size_offset + 4 - 1]), + .scout(sov[lrat_entry3_size_offset:lrat_entry3_size_offset + 4 - 1]), + .din(lrat_entry3_size_d), + .dout(lrat_entry3_size_q) + ); + + tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(1)) lrat_entry3_cmpmask_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[3]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry3_cmpmask_offset:lrat_entry3_cmpmask_offset + 7 - 1]), + .scout(sov[lrat_entry3_cmpmask_offset:lrat_entry3_cmpmask_offset + 7 - 1]), + .din(lrat_entry3_cmpmask_d), + .dout(lrat_entry3_cmpmask_q) + ); + + tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(1)) lrat_entry3_xbitmask_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[3]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry3_xbitmask_offset:lrat_entry3_xbitmask_offset + 7 - 1]), + .scout(sov[lrat_entry3_xbitmask_offset:lrat_entry3_xbitmask_offset + 7 - 1]), + .din(lrat_entry3_xbitmask_d), + .dout(lrat_entry3_xbitmask_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lrat_entry4_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[4]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry4_valid_offset]), + .scout(sov[lrat_entry4_valid_offset]), + .din(lrat_entry4_valid_d), + .dout(lrat_entry4_valid_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lrat_entry4_xbit_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[4]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry4_xbit_offset]), + .scout(sov[lrat_entry4_xbit_offset]), + .din(lrat_entry4_xbit_d), + .dout(lrat_entry4_xbit_q) + ); + + tri_rlmreg_p #(.WIDTH((64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1)), .INIT(0), .NEEDS_SRESET(1)) lrat_entry4_lpn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[4]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry4_lpn_offset:lrat_entry4_lpn_offset + (64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1) - 1]), + .scout(sov[lrat_entry4_lpn_offset:lrat_entry4_lpn_offset + (64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1) - 1]), + .din(lrat_entry4_lpn_d), + .dout(lrat_entry4_lpn_q) + ); + + tri_rlmreg_p #(.WIDTH((64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1)), .INIT(0), .NEEDS_SRESET(1)) lrat_entry4_rpn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[4]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry4_rpn_offset:lrat_entry4_rpn_offset + (64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1) - 1]), + .scout(sov[lrat_entry4_rpn_offset:lrat_entry4_rpn_offset + (64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1) - 1]), + .din(lrat_entry4_rpn_d), + .dout(lrat_entry4_rpn_q) + ); + + tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lrat_entry4_lpid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[4]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry4_lpid_offset:lrat_entry4_lpid_offset + `LPID_WIDTH - 1]), + .scout(sov[lrat_entry4_lpid_offset:lrat_entry4_lpid_offset + `LPID_WIDTH - 1]), + .din(lrat_entry4_lpid_d), + .dout(lrat_entry4_lpid_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lrat_entry4_size_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[4]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry4_size_offset:lrat_entry4_size_offset + 4 - 1]), + .scout(sov[lrat_entry4_size_offset:lrat_entry4_size_offset + 4 - 1]), + .din(lrat_entry4_size_d), + .dout(lrat_entry4_size_q) + ); + + tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(1)) lrat_entry4_cmpmask_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[4]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry4_cmpmask_offset:lrat_entry4_cmpmask_offset + 7 - 1]), + .scout(sov[lrat_entry4_cmpmask_offset:lrat_entry4_cmpmask_offset + 7 - 1]), + .din(lrat_entry4_cmpmask_d), + .dout(lrat_entry4_cmpmask_q) + ); + + tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(1)) lrat_entry4_xbitmask_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[4]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry4_xbitmask_offset:lrat_entry4_xbitmask_offset + 7 - 1]), + .scout(sov[lrat_entry4_xbitmask_offset:lrat_entry4_xbitmask_offset + 7 - 1]), + .din(lrat_entry4_xbitmask_d), + .dout(lrat_entry4_xbitmask_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lrat_entry5_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[5]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry5_valid_offset]), + .scout(sov[lrat_entry5_valid_offset]), + .din(lrat_entry5_valid_d), + .dout(lrat_entry5_valid_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lrat_entry5_xbit_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[5]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry5_xbit_offset]), + .scout(sov[lrat_entry5_xbit_offset]), + .din(lrat_entry5_xbit_d), + .dout(lrat_entry5_xbit_q) + ); + + tri_rlmreg_p #(.WIDTH((64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1)), .INIT(0), .NEEDS_SRESET(1)) lrat_entry5_lpn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[5]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry5_lpn_offset:lrat_entry5_lpn_offset + (64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1) - 1]), + .scout(sov[lrat_entry5_lpn_offset:lrat_entry5_lpn_offset + (64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1) - 1]), + .din(lrat_entry5_lpn_d), + .dout(lrat_entry5_lpn_q) + ); + + tri_rlmreg_p #(.WIDTH((64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1)), .INIT(0), .NEEDS_SRESET(1)) lrat_entry5_rpn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[5]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry5_rpn_offset:lrat_entry5_rpn_offset + (64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1) - 1]), + .scout(sov[lrat_entry5_rpn_offset:lrat_entry5_rpn_offset + (64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1) - 1]), + .din(lrat_entry5_rpn_d), + .dout(lrat_entry5_rpn_q) + ); + + tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lrat_entry5_lpid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[5]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry5_lpid_offset:lrat_entry5_lpid_offset + `LPID_WIDTH - 1]), + .scout(sov[lrat_entry5_lpid_offset:lrat_entry5_lpid_offset + `LPID_WIDTH - 1]), + .din(lrat_entry5_lpid_d), + .dout(lrat_entry5_lpid_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lrat_entry5_size_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[5]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry5_size_offset:lrat_entry5_size_offset + 4 - 1]), + .scout(sov[lrat_entry5_size_offset:lrat_entry5_size_offset + 4 - 1]), + .din(lrat_entry5_size_d), + .dout(lrat_entry5_size_q) + ); + + tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(1)) lrat_entry5_cmpmask_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[5]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry5_cmpmask_offset:lrat_entry5_cmpmask_offset + 7 - 1]), + .scout(sov[lrat_entry5_cmpmask_offset:lrat_entry5_cmpmask_offset + 7 - 1]), + .din(lrat_entry5_cmpmask_d), + .dout(lrat_entry5_cmpmask_q) + ); + + tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(1)) lrat_entry5_xbitmask_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[5]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry5_xbitmask_offset:lrat_entry5_xbitmask_offset + 7 - 1]), + .scout(sov[lrat_entry5_xbitmask_offset:lrat_entry5_xbitmask_offset + 7 - 1]), + .din(lrat_entry5_xbitmask_d), + .dout(lrat_entry5_xbitmask_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lrat_entry6_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[6]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry6_valid_offset]), + .scout(sov[lrat_entry6_valid_offset]), + .din(lrat_entry6_valid_d), + .dout(lrat_entry6_valid_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lrat_entry6_xbit_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[6]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry6_xbit_offset]), + .scout(sov[lrat_entry6_xbit_offset]), + .din(lrat_entry6_xbit_d), + .dout(lrat_entry6_xbit_q) + ); + + tri_rlmreg_p #(.WIDTH((64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1)), .INIT(0), .NEEDS_SRESET(1)) lrat_entry6_lpn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[6]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry6_lpn_offset:lrat_entry6_lpn_offset + (64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1) - 1]), + .scout(sov[lrat_entry6_lpn_offset:lrat_entry6_lpn_offset + (64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1) - 1]), + .din(lrat_entry6_lpn_d), + .dout(lrat_entry6_lpn_q) + ); + + tri_rlmreg_p #(.WIDTH((64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1)), .INIT(0), .NEEDS_SRESET(1)) lrat_entry6_rpn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[6]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry6_rpn_offset:lrat_entry6_rpn_offset + (64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1) - 1]), + .scout(sov[lrat_entry6_rpn_offset:lrat_entry6_rpn_offset + (64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1) - 1]), + .din(lrat_entry6_rpn_d), + .dout(lrat_entry6_rpn_q) + ); + + tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lrat_entry6_lpid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[6]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry6_lpid_offset:lrat_entry6_lpid_offset + `LPID_WIDTH - 1]), + .scout(sov[lrat_entry6_lpid_offset:lrat_entry6_lpid_offset + `LPID_WIDTH - 1]), + .din(lrat_entry6_lpid_d), + .dout(lrat_entry6_lpid_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lrat_entry6_size_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[6]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry6_size_offset:lrat_entry6_size_offset + 4 - 1]), + .scout(sov[lrat_entry6_size_offset:lrat_entry6_size_offset + 4 - 1]), + .din(lrat_entry6_size_d), + .dout(lrat_entry6_size_q) + ); + + tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(1)) lrat_entry6_cmpmask_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[6]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry6_cmpmask_offset:lrat_entry6_cmpmask_offset + 7 - 1]), + .scout(sov[lrat_entry6_cmpmask_offset:lrat_entry6_cmpmask_offset + 7 - 1]), + .din(lrat_entry6_cmpmask_d), + .dout(lrat_entry6_cmpmask_q) + ); + + tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(1)) lrat_entry6_xbitmask_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[6]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry6_xbitmask_offset:lrat_entry6_xbitmask_offset + 7 - 1]), + .scout(sov[lrat_entry6_xbitmask_offset:lrat_entry6_xbitmask_offset + 7 - 1]), + .din(lrat_entry6_xbitmask_d), + .dout(lrat_entry6_xbitmask_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lrat_entry7_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[7]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry7_valid_offset]), + .scout(sov[lrat_entry7_valid_offset]), + .din(lrat_entry7_valid_d), + .dout(lrat_entry7_valid_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lrat_entry7_xbit_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[7]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry7_xbit_offset]), + .scout(sov[lrat_entry7_xbit_offset]), + .din(lrat_entry7_xbit_d), + .dout(lrat_entry7_xbit_q) + ); + + tri_rlmreg_p #(.WIDTH((64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1)), .INIT(0), .NEEDS_SRESET(1)) lrat_entry7_lpn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[7]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry7_lpn_offset:lrat_entry7_lpn_offset + (64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1) - 1]), + .scout(sov[lrat_entry7_lpn_offset:lrat_entry7_lpn_offset + (64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1) - 1]), + .din(lrat_entry7_lpn_d), + .dout(lrat_entry7_lpn_q) + ); + + tri_rlmreg_p #(.WIDTH((64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1)), .INIT(0), .NEEDS_SRESET(1)) lrat_entry7_rpn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[7]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry7_rpn_offset:lrat_entry7_rpn_offset + (64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1) - 1]), + .scout(sov[lrat_entry7_rpn_offset:lrat_entry7_rpn_offset + (64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1) - 1]), + .din(lrat_entry7_rpn_d), + .dout(lrat_entry7_rpn_q) + ); + + tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lrat_entry7_lpid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[7]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry7_lpid_offset:lrat_entry7_lpid_offset + `LPID_WIDTH - 1]), + .scout(sov[lrat_entry7_lpid_offset:lrat_entry7_lpid_offset + `LPID_WIDTH - 1]), + .din(lrat_entry7_lpid_d), + .dout(lrat_entry7_lpid_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lrat_entry7_size_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[7]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry7_size_offset:lrat_entry7_size_offset + 4 - 1]), + .scout(sov[lrat_entry7_size_offset:lrat_entry7_size_offset + 4 - 1]), + .din(lrat_entry7_size_d), + .dout(lrat_entry7_size_q) + ); + + tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(1)) lrat_entry7_cmpmask_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[7]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry7_cmpmask_offset:lrat_entry7_cmpmask_offset + 7 - 1]), + .scout(sov[lrat_entry7_cmpmask_offset:lrat_entry7_cmpmask_offset + 7 - 1]), + .din(lrat_entry7_cmpmask_d), + .dout(lrat_entry7_cmpmask_q) + ); + + tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(1)) lrat_entry7_xbitmask_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_entry_act_q[7]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_entry7_xbitmask_offset:lrat_entry7_xbitmask_offset + 7 - 1]), + .scout(sov[lrat_entry7_xbitmask_offset:lrat_entry7_xbitmask_offset + 7 - 1]), + .din(lrat_entry7_xbitmask_d), + .dout(lrat_entry7_xbitmask_q) + ); + + tri_rlmreg_p #(.WIDTH((64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1)), .INIT(0), .NEEDS_SRESET(1)) lrat_datain_lpn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_datain_act_q[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_datain_lpn_offset:lrat_datain_lpn_offset + (64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1) - 1]), + .scout(sov[lrat_datain_lpn_offset:lrat_datain_lpn_offset + (64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1) - 1]), + .din(lrat_datain_lpn_d), + .dout(lrat_datain_lpn_q) + ); + + tri_rlmreg_p #(.WIDTH((64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1)), .INIT(0), .NEEDS_SRESET(1)) lrat_datain_rpn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_datain_act_q[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_datain_rpn_offset:lrat_datain_rpn_offset + (64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1) - 1]), + .scout(sov[lrat_datain_rpn_offset:lrat_datain_rpn_offset + (64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1) - 1]), + .din(lrat_datain_rpn_d), + .dout(lrat_datain_rpn_q) + ); + + tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lrat_datain_lpid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_datain_act_q[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_datain_lpid_offset:lrat_datain_lpid_offset + `LPID_WIDTH - 1]), + .scout(sov[lrat_datain_lpid_offset:lrat_datain_lpid_offset + `LPID_WIDTH - 1]), + .din(lrat_datain_lpid_d), + .dout(lrat_datain_lpid_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lrat_datain_size_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_datain_act_q[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_datain_size_offset:lrat_datain_size_offset + 4 - 1]), + .scout(sov[lrat_datain_size_offset:lrat_datain_size_offset + 4 - 1]), + .din(lrat_datain_size_d), + .dout(lrat_datain_size_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lrat_datain_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_datain_act_q[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_datain_valid_offset]), + .scout(sov[lrat_datain_valid_offset]), + .din(lrat_datain_valid_d), + .dout(lrat_datain_valid_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lrat_datain_xbit_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_datain_act_q[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_datain_xbit_offset]), + .scout(sov[lrat_datain_xbit_offset]), + .din(lrat_datain_xbit_d), + .dout(lrat_datain_xbit_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lrat_mas1_v_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_mas_act_q[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_mas1_v_offset]), + .scout(sov[lrat_mas1_v_offset]), + .din(lrat_mas1_v_d), + .dout(lrat_mas1_v_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lrat_mmucr3_x_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_mas_act_q[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_mmucr3_x_offset]), + .scout(sov[lrat_mmucr3_x_offset]), + .din(lrat_mmucr3_x_d), + .dout(lrat_mmucr3_x_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lrat_mas1_tsize_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_mas_act_q[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_mas1_tsize_offset:lrat_mas1_tsize_offset + 4 - 1]), + .scout(sov[lrat_mas1_tsize_offset:lrat_mas1_tsize_offset + 4 - 1]), + .din(lrat_mas1_tsize_d), + .dout(lrat_mas1_tsize_q) + ); + + tri_rlmreg_p #(.WIDTH(`RPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lrat_mas2_epn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_mas_act_q[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_mas2_epn_offset:lrat_mas2_epn_offset + `RPN_WIDTH - 1]), + .scout(sov[lrat_mas2_epn_offset:lrat_mas2_epn_offset + `RPN_WIDTH - 1]), + .din(lrat_mas2_epn_d), + .dout(lrat_mas2_epn_q) + ); + + tri_rlmreg_p #(.WIDTH(20), .INIT(0), .NEEDS_SRESET(1)) lrat_mas3_rpnl_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_mas_act_q[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_mas3_rpnl_offset:lrat_mas3_rpnl_offset + 20 - 1]), + .scout(sov[lrat_mas3_rpnl_offset:lrat_mas3_rpnl_offset + 20 - 1]), + .din(lrat_mas3_rpnl_d), + .dout(lrat_mas3_rpnl_q) + ); + + tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) lrat_mas7_rpnu_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_mas_act_q[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_mas7_rpnu_offset:lrat_mas7_rpnu_offset + 10 - 1]), + .scout(sov[lrat_mas7_rpnu_offset:lrat_mas7_rpnu_offset + 10 - 1]), + .din(lrat_mas7_rpnu_d), + .dout(lrat_mas7_rpnu_q) + ); + + tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lrat_mas8_tlpid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_mas_act_q[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_mas8_tlpid_offset:lrat_mas8_tlpid_offset + `LPID_WIDTH - 1]), + .scout(sov[lrat_mas8_tlpid_offset:lrat_mas8_tlpid_offset + `LPID_WIDTH - 1]), + .din(lrat_mas8_tlpid_d), + .dout(lrat_mas8_tlpid_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) lrat_mas_thdid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_mas_act_q[2]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_mas_thdid_offset:lrat_mas_thdid_offset + `MM_THREADS - 1]), + .scout(sov[lrat_mas_thdid_offset:lrat_mas_thdid_offset + `MM_THREADS - 1]), + .din(lrat_mas_thdid_d), + .dout(lrat_mas_thdid_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lrat_mas_tlbre_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_mas_act_q[2]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_mas_tlbre_offset]), + .scout(sov[lrat_mas_tlbre_offset]), + .din(lrat_mas_tlbre_d), + .dout(lrat_mas_tlbre_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lrat_mas_tlbsx_hit_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_mas_act_q[2]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_mas_tlbsx_hit_offset]), + .scout(sov[lrat_mas_tlbsx_hit_offset]), + .din(lrat_mas_tlbsx_hit_d), + .dout(lrat_mas_tlbsx_hit_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lrat_mas_tlbsx_miss_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lrat_mas_act_q[2]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[lrat_mas_tlbsx_miss_offset]), + .scout(sov[lrat_mas_tlbsx_miss_offset]), + .din(lrat_mas_tlbsx_miss_d), + .dout(lrat_mas_tlbsx_miss_q) + ); + + //------------------------------------------------ + // thold/sg latches + //------------------------------------------------ + + tri_plat #(.WIDTH(3)) perv_2to1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ccflush_dc), + .din( {pc_func_sl_thold_2, pc_func_slp_sl_thold_2, pc_sg_2} ), + .q( {pc_func_sl_thold_1, pc_func_slp_sl_thold_1, pc_sg_1} ) + ); + + tri_plat #(.WIDTH(3)) perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ccflush_dc), + .din( {pc_func_sl_thold_1, pc_func_slp_sl_thold_1, pc_sg_1} ), + .q( {pc_func_sl_thold_0, pc_func_slp_sl_thold_0, pc_sg_0} ) + ); + + tri_lcbor perv_lcbor_func_sl( + .clkoff_b(lcb_clkoff_dc_b), + .thold(pc_func_sl_thold_0), + .sg(pc_sg_0), + .act_dis(lcb_act_dis_dc), + .force_t(pc_func_sl_force), + .thold_b(pc_func_sl_thold_0_b) + ); + + tri_lcbor perv_lcbor_func_slp_sl( + .clkoff_b(lcb_clkoff_dc_b), + .thold(pc_func_slp_sl_thold_0), + .sg(pc_sg_0), + .act_dis(lcb_act_dis_dc), + .force_t(pc_func_slp_sl_force), + .thold_b(pc_func_slp_sl_thold_0_b) + ); + + //--------------------------------------------------------------------- + // Scan + //--------------------------------------------------------------------- + assign siv[0:scan_right] = {sov[1:scan_right], ac_func_scan_in}; + assign ac_func_scan_out = sov[0]; + + function Eq; + input a, b; + reg result; + begin + if (a == b) + begin + result = 1'b1; + end + else + begin + result = 1'b0; + end + Eq = result; + end + endfunction + +endmodule diff --git a/dev/verilog/work/mmq_tlb_lrat_matchline.v b/dev/verilog/work/mmq_tlb_lrat_matchline.v new file mode 100755 index 0000000..1c860a3 --- /dev/null +++ b/dev/verilog/work/mmq_tlb_lrat_matchline.v @@ -0,0 +1,363 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +//******************************************************************** +//* +//* TITLE: MMU TLB LRAT Match Line Logic for Functional Model +//* +//* NAME: mmq_tlb_lrat_matchline +//* +//************ change log at end of this file *************************** +// + +//---------------------------------------------------------------------- +// Entity +//---------------------------------------------------------------------- + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" +`include "mmu_a2o.vh" +`define LRAT_MAXSIZE_LOG2 40 // 1T largest pgsize +`define LRAT_MINSIZE_LOG2 20 // 1M smallest pgsize +`define LRAT_CMPMASK_WIDTH 7 + +module mmq_tlb_lrat_matchline( + + inout vdd, + inout gnd, + + input [64-`REAL_ADDR_WIDTH:64-`LRAT_MINSIZE_LOG2-1] addr_in, + input addr_enable, + input [0:3] entry_size, + input [0:`LRAT_CMPMASK_WIDTH-1] entry_cmpmask, + input entry_xbit, + input [0:`LRAT_CMPMASK_WIDTH-1] entry_xbitmask, + input [64-`REAL_ADDR_WIDTH:64-`LRAT_MINSIZE_LOG2-1] entry_lpn, + input [0:`LPID_WIDTH-1] entry_lpid, + + input [0:`LPID_WIDTH-1] comp_lpid, + input lpid_enable, + input entry_v, + + output match, + output dbg_addr_match, + output dbg_lpid_match + +); + +parameter HAVE_XBIT = 1; +parameter NUM_PGSIZES = 8; +parameter HAVE_CMPMASK = 1; + + + //---------------------------------------------------------------------- + // Components + //---------------------------------------------------------------------- + + //---------------------------------------------------------------------- + // Signals + //---------------------------------------------------------------------- + + wire [64-`LRAT_MAXSIZE_LOG2:64-`LRAT_MINSIZE_LOG2-1] entry_lpn_b; + wire function_24_43; + wire function_26_43; + wire function_30_43; + wire function_32_43; + wire function_34_43; + wire function_36_43; + wire function_40_43; + wire pgsize_eq_16M; // PS7 + wire pgsize_eq_256M; // PS9 + wire pgsize_eq_1G; // PS10 + wire pgsize_eq_4G; // PS11 + wire pgsize_eq_16G; // PS12 + wire pgsize_eq_256G; // PS14 + wire pgsize_eq_1T; // PS15 + wire pgsize_gte_16M; // PS7 + wire pgsize_gte_256M; // PS9 + wire pgsize_gte_1G; // PS10 + wire pgsize_gte_4G; // PS11 + wire pgsize_gte_16G; // PS12 + wire pgsize_gte_256G; // PS14 + wire pgsize_gte_1T; // PS15 + + wire comp_or_24_25; + wire comp_or_26_29; + wire comp_or_30_31; + wire comp_or_32_33; + wire comp_or_34_35; + wire comp_or_36_39; + wire comp_or_40_43; + + wire [64-`REAL_ADDR_WIDTH:64-`LRAT_MINSIZE_LOG2+`LPID_WIDTH-1] match_line; + wire addr_match; + wire lpid_match; + + (* analysis_not_referenced="true" *) + wire [0:2] unused_dc; + + assign match_line[64-`REAL_ADDR_WIDTH : 64-`LRAT_MINSIZE_LOG2+`LPID_WIDTH-1] = + (~ (({entry_lpn[64-`REAL_ADDR_WIDTH : 64-`LRAT_MINSIZE_LOG2-1], entry_lpid[0:`LPID_WIDTH-1]}) ^ + ({ addr_in[64-`REAL_ADDR_WIDTH : 64-`LRAT_MINSIZE_LOG2-1], comp_lpid[0:`LPID_WIDTH-1]})) ); + + generate + if (NUM_PGSIZES == 8) + begin : numpgsz8 + assign entry_lpn_b[64 - `LRAT_MAXSIZE_LOG2:64 - `LRAT_MINSIZE_LOG2 - 1] = (~(entry_lpn[64 - `LRAT_MAXSIZE_LOG2:64 - `LRAT_MINSIZE_LOG2 - 1])); + + if (HAVE_CMPMASK == 0) // PS7 + begin : gen_nocmpmask80 + assign pgsize_eq_16M = ((entry_size == 4'b0111)) ? 1'b1 : + 1'b0; + assign pgsize_eq_256M = ((entry_size == 4'b1001)) ? 1'b1 : // PS9 + 1'b0; + assign pgsize_eq_1G = ((entry_size == 4'b1010)) ? 1'b1 : // PS10 + 1'b0; + assign pgsize_eq_4G = ((entry_size == 4'b1011)) ? 1'b1 : // PS11 + 1'b0; + assign pgsize_eq_16G = ((entry_size == 4'b1100)) ? 1'b1 : // PS12 + 1'b0; + assign pgsize_eq_256G = ((entry_size == 4'b1110)) ? 1'b1 : // PS14 + 1'b0; + assign pgsize_eq_1T = ((entry_size == 4'b1111)) ? 1'b1 : // PS15 + 1'b0; + + assign pgsize_gte_16M = ((entry_size == 4'b0111 | pgsize_gte_256M == 1'b1)) ? 1'b1 : // PS7 or larger + 1'b0; + assign pgsize_gte_256M = ((entry_size == 4'b1001 | pgsize_gte_1G == 1'b1)) ? 1'b1 : // PS9 or larger + 1'b0; + assign pgsize_gte_1G = ((entry_size == 4'b1010 | pgsize_gte_4G == 1'b1)) ? 1'b1 : // PS10 or larger + 1'b0; + assign pgsize_gte_4G = ((entry_size == 4'b1011 | pgsize_gte_16G == 1'b1)) ? 1'b1 : // PS11 or larger + 1'b0; + assign pgsize_gte_16G = ((entry_size == 4'b1100 | pgsize_gte_256G == 1'b1)) ? 1'b1 : // PS12 or larger + 1'b0; + assign pgsize_gte_256G = ((entry_size == 4'b1110 | pgsize_gte_1T == 1'b1)) ? 1'b1 : // PS14 or larger + 1'b0; + assign pgsize_gte_1T = ((entry_size == 4'b1111)) ? 1'b1 : // PS15 + 1'b0; + end + + // size entry_cmpmask: 0123456 + // 1TB 1111111 + // 256GB 0111111 + // 16GB 0011111 + // 4GB 0001111 + // 1GB 0000111 + // 256MB 0000011 + // 16MB 0000001 + // 1MB 0000000 + if (HAVE_CMPMASK == 1) + begin : gen_cmpmask80 + assign pgsize_gte_1T = entry_cmpmask[0]; + assign pgsize_gte_256G = entry_cmpmask[1]; + assign pgsize_gte_16G = entry_cmpmask[2]; + assign pgsize_gte_4G = entry_cmpmask[3]; + assign pgsize_gte_1G = entry_cmpmask[4]; + assign pgsize_gte_256M = entry_cmpmask[5]; + assign pgsize_gte_16M = entry_cmpmask[6]; + + // size entry_xbitmask: 0123456 + // 1TB 1000000 + // 256GB 0100000 + // 16GB 0010000 + // 4GB 0001000 + // 1GB 0000100 + // 256MB 0000010 + // 16MB 0000001 + // 1MB 0000000 + assign pgsize_eq_1T = entry_xbitmask[0]; + assign pgsize_eq_256G = entry_xbitmask[1]; + assign pgsize_eq_16G = entry_xbitmask[2]; + assign pgsize_eq_4G = entry_xbitmask[3]; + assign pgsize_eq_1G = entry_xbitmask[4]; + assign pgsize_eq_256M = entry_xbitmask[5]; + assign pgsize_eq_16M = entry_xbitmask[6]; + end + + if (HAVE_XBIT == 0) + begin : gen_noxbit80 + assign function_24_43 = 1'b0; + assign function_26_43 = 1'b0; + assign function_30_43 = 1'b0; + assign function_32_43 = 1'b0; + assign function_34_43 = 1'b0; + assign function_36_43 = 1'b0; + assign function_40_43 = 1'b0; + end + + if (HAVE_XBIT != 0 & `REAL_ADDR_WIDTH == 42) + begin : gen_xbit80 + assign function_24_43 = (~(entry_xbit)) | (~(pgsize_eq_1T)) | |(entry_lpn_b[24:43] & addr_in[24:43]); + assign function_26_43 = (~(entry_xbit)) | (~(pgsize_eq_256G)) | |(entry_lpn_b[26:43] & addr_in[26:43]); + assign function_30_43 = (~(entry_xbit)) | (~(pgsize_eq_16G)) | |(entry_lpn_b[30:43] & addr_in[30:43]); + assign function_32_43 = (~(entry_xbit)) | (~(pgsize_eq_4G)) | |(entry_lpn_b[32:43] & addr_in[32:43]); + assign function_34_43 = (~(entry_xbit)) | (~(pgsize_eq_1G)) | |(entry_lpn_b[34:43] & addr_in[34:43]); + assign function_36_43 = (~(entry_xbit)) | (~(pgsize_eq_256M)) | |(entry_lpn_b[36:43] & addr_in[36:43]); + assign function_40_43 = (~(entry_xbit)) | (~(pgsize_eq_16M)) | |(entry_lpn_b[40:43] & addr_in[40:43]); + end + +if (HAVE_XBIT != 0 & `REAL_ADDR_WIDTH == 32) +begin : gen_xbit81 + assign function_24_43 = 1'b1; + assign function_26_43 = 1'b1; + assign function_30_43 = 1'b1; + assign function_32_43 = 1'b1; + assign function_34_43 = (~(entry_xbit)) | (~(pgsize_eq_1G)) | |(entry_lpn_b[34:43] & addr_in[34:43]); + assign function_36_43 = (~(entry_xbit)) | (~(pgsize_eq_256M)) | |(entry_lpn_b[36:43] & addr_in[36:43]); + assign function_40_43 = (~(entry_xbit)) | (~(pgsize_eq_16M)) | |(entry_lpn_b[40:43] & addr_in[40:43]); +end + +if (`REAL_ADDR_WIDTH == 42) +begin : gen_comp80 +assign comp_or_24_25 = &(match_line[24:25]) | pgsize_gte_1T; +assign comp_or_26_29 = &(match_line[26:29]) | pgsize_gte_256G; +assign comp_or_30_31 = &(match_line[30:31]) | pgsize_gte_16G; +assign comp_or_32_33 = &(match_line[32:33]) | pgsize_gte_4G; +assign comp_or_34_35 = &(match_line[34:35]) | pgsize_gte_1G; +assign comp_or_36_39 = &(match_line[36:39]) | pgsize_gte_256M; +assign comp_or_40_43 = &(match_line[40:43]) | pgsize_gte_16M; +end + +if (`REAL_ADDR_WIDTH == 32) +begin : gen_comp81 +assign comp_or_24_25 = 1'b1; +assign comp_or_26_29 = 1'b1; +assign comp_or_30_31 = 1'b1; +assign comp_or_32_33 = 1'b1; +assign comp_or_34_35 = &(match_line[34:35]) | pgsize_gte_1G; +assign comp_or_36_39 = &(match_line[36:39]) | pgsize_gte_256M; +assign comp_or_40_43 = &(match_line[40:43]) | pgsize_gte_16M; +end + +if (HAVE_XBIT == 0 & `REAL_ADDR_WIDTH == 42) +begin : gen_noxbit81 +// Regular compare largest page size +assign addr_match = ( &(match_line[22:23]) & + comp_or_24_25 & + comp_or_26_29 & + comp_or_30_31 & + comp_or_32_33 & + comp_or_34_35 & + comp_or_36_39 & + comp_or_40_43 ) | (~(addr_enable)); // Ignore functions based on page size +end +// Include address as part of compare, +// should never ignore for regular compare/read. +// Could ignore for compare/invalidate + +if (HAVE_XBIT == 0 & `REAL_ADDR_WIDTH == 32) +begin : gen_noxbit82 +// Regular compare largest page size +assign addr_match = ( &(match_line[32:33]) & + comp_or_34_35 & + comp_or_36_39 & + comp_or_40_43 ) | (~(addr_enable)); // Ignore functions based on page size +end +// Include address as part of compare, +// should never ignore for regular compare/read. +// Could ignore for compare/invalidate + +if (HAVE_XBIT != 0 & `REAL_ADDR_WIDTH == 42) +begin : gen_xbit82 +// Exclusion functions +// Regular compare largest page size +assign addr_match = ( &(match_line[22:23]) & + comp_or_24_25 & + comp_or_26_29 & + comp_or_30_31 & + comp_or_32_33 & + comp_or_34_35 & + comp_or_36_39 & + comp_or_40_43 & + function_24_43 & + function_26_43 & + function_30_43 & + function_32_43 & + function_34_43 & + function_36_43 & + function_40_43 ) | (~(addr_enable)); // Ignore functions based on page size +end +// Include address as part of compare, +// should never ignore for regular compare/read. +// Could ignore for compare/invalidate + +if (HAVE_XBIT != 0 & `REAL_ADDR_WIDTH == 32) +begin : gen_xbit83 +// Exclusion functions +// Regular compare largest page size +assign addr_match = ( &(match_line[32:33]) & + comp_or_34_35 & + comp_or_36_39 & + comp_or_40_43 & + function_34_43 & + function_36_43 & + function_40_43 ) | (~(addr_enable)); // Ignore functions based on page size +end +end +endgenerate + +// Include address as part of compare, +// should never ignore for regular compare/read. +// Could ignore for compare/invalidate + +// numpgsz8: NUM_PGSIZES = 8 + +//signal match_line : std_ulogic_vector(64-`REAL_ADDR_WIDTH to 64-`LRAT_MINSIZE_LOG2+`LPID_WIDTH-1); + +// entry_lpid=0 ignores lpid match for translation, not invalidation +assign lpid_match = &(match_line[64 - `LRAT_MINSIZE_LOG2:64 - `LRAT_MINSIZE_LOG2 + `LPID_WIDTH - 1]) | (~(|(entry_lpid[0:7]))) | (~(lpid_enable)); + +// Address compare +assign match = addr_match & lpid_match & entry_v; // LPID compare +// Valid + +// debug outputs +assign dbg_addr_match = addr_match; // out std_ulogic; +assign dbg_lpid_match = lpid_match; // out std_ulogic; + +generate +if (HAVE_CMPMASK == 0) +begin : gen_unused0 +assign unused_dc[0] = 1'b0; +assign unused_dc[1] = vdd; +assign unused_dc[2] = gnd; +end +endgenerate + +generate +if (HAVE_CMPMASK == 1) +begin : gen_unused1 +assign unused_dc[0] = |(entry_size); +assign unused_dc[1] = vdd; +assign unused_dc[2] = gnd; +end +endgenerate + +endmodule diff --git a/dev/verilog/work/mmq_tlb_matchline.v b/dev/verilog/work/mmq_tlb_matchline.v new file mode 100755 index 0000000..a838b6c --- /dev/null +++ b/dev/verilog/work/mmq_tlb_matchline.v @@ -0,0 +1,607 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +//******************************************************************** +//* +//* TITLE: MMU TLB Match Line Logic for Functional Model +//* +//* NAME: mmq_tlb_matchline +//* +//************ change log at end of this file *************************** +// + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" +`include "mmu_a2o.vh" +`define TLB_CMPMASK_WIDTH 5 + +module mmq_tlb_matchline( + + inout vdd, + inout gnd, + + input [0:51] addr_in, + input [0:8] addr_enable, + input [0:3] comp_pgsize, + input pgsize_enable, + input [0:3] entry_size, + input [0:`TLB_CMPMASK_WIDTH-1] entry_cmpmask, + input entry_xbit, + input [0:`TLB_CMPMASK_WIDTH-1] entry_xbitmask, + input [0:51] entry_epn, + input [0:1] comp_class, + input [0:1] entry_class, + input class_enable, + input [0:1] comp_extclass, + input [0:1] entry_extclass, + input [0:1] extclass_enable, + input [0:1] comp_state, + input entry_gs, + input entry_ts, + input [0:1] state_enable, + input [0:3] entry_thdid, + input [0:3] comp_thdid, + input thdid_enable, + input [0:13] entry_pid, + input [0:13] comp_pid, + input pid_enable, + input [0:7] entry_lpid, + input [0:7] comp_lpid, + input lpid_enable, + input entry_ind, + input comp_ind, + input ind_enable, + input entry_iprot, + input comp_iprot, + input iprot_enable, + input entry_v, + input comp_invalidate, + + output match, + + output dbg_addr_match, + output dbg_pgsize_match, + output dbg_class_match, + output dbg_extclass_match, + output dbg_state_match, + output dbg_thdid_match, + output dbg_pid_match, + output dbg_lpid_match, + output dbg_ind_match, + + output dbg_iprot_match + +); + +parameter HAVE_XBIT = 1; +parameter NUM_PGSIZES = 5; +parameter HAVE_CMPMASK = 1; + + + //---------------------------------------------------------------------- + // Components + //---------------------------------------------------------------------- + + //---------------------------------------------------------------------- + // Signals + //---------------------------------------------------------------------- + + + wire [30:51] entry_epn_b; + wire function_50_51; + wire function_48_51; + wire function_46_51; + wire function_44_51; + wire function_40_51; + wire function_36_51; + wire function_34_51; + wire pgsize_gte_16K; + wire pgsize_gte_64K; + wire pgsize_gte_256K; + wire pgsize_gte_1M; + wire pgsize_gte_16M; + wire pgsize_gte_256M; + wire pgsize_gte_1G; + wire pgsize_eq_16K; + wire pgsize_eq_64K; + wire pgsize_eq_256K; + wire pgsize_eq_1M; + wire pgsize_eq_16M; + wire pgsize_eq_256M; + wire pgsize_eq_1G; + wire comp_or_34_35; + wire comp_or_36_39; + wire comp_or_40_43; + wire comp_or_44_45; + wire comp_or_44_47; + wire comp_or_46_47; + wire comp_or_48_49; + wire comp_or_48_51; + wire comp_or_50_51; + wire [0:85] match_line; + wire pgsize_match; + wire addr_match; + wire class_match; + wire extclass_match; + wire state_match; + wire thdid_match; + wire pid_match; + wire lpid_match; + wire ind_match; + wire iprot_match; + wire addr_match_xbit_contrib; + wire addr_match_lsb_contrib; + wire addr_match_msb_contrib; + + (* analysis_not_referenced="true" *) + wire [0:6] unused_dc; + + assign match_line[0:85] = ( ~(({entry_epn[0:51], entry_size[0:3], entry_class[0:1], entry_extclass[0:1], entry_gs, entry_ts, entry_pid[0:13], + entry_lpid[0:7], entry_ind, entry_iprot}) ^ ({addr_in[0:51], comp_pgsize[0:3], comp_class[0:1], + comp_extclass[0:1], comp_state[0:1], comp_pid[0:13], comp_lpid[0:7], comp_ind, comp_iprot})) ); + + generate + if (NUM_PGSIZES == 8) + begin : numpgsz8 + assign entry_epn_b[30:51] = (~(entry_epn[30:51])); + + assign unused_dc[0:4] = {5{1'b0}}; + assign unused_dc[5] = vdd; + assign unused_dc[6] = gnd; + + if (HAVE_CMPMASK == 0) + begin : gen_nocmpmask80 + assign pgsize_gte_1G = (entry_size[0] & (~(entry_size[1])) & entry_size[2] & (~(entry_size[3]))); + assign pgsize_gte_256M = (entry_size[0] & (~(entry_size[1])) & (~(entry_size[2])) & entry_size[3]) | pgsize_gte_1G; + assign pgsize_gte_16M = ((~(entry_size[0])) & entry_size[1] & entry_size[2] & entry_size[3]) | pgsize_gte_256M; + assign pgsize_gte_1M = ((~(entry_size[0])) & entry_size[1] & (~(entry_size[2])) & entry_size[3]) | pgsize_gte_16M; + assign pgsize_gte_256K = ((~(entry_size[0])) & entry_size[1] & (~(entry_size[2])) & (~(entry_size[3]))) | pgsize_gte_1M; + assign pgsize_gte_64K = ((~(entry_size[0])) & (~(entry_size[1])) & entry_size[2] & entry_size[3]) | pgsize_gte_256K; + assign pgsize_gte_16K = ((~(entry_size[0])) & (~(entry_size[1])) & entry_size[2] & (~(entry_size[3]))) | pgsize_gte_64K; + end + + // size entry_cmpmask: 0123456 + // 1GB 1111111 + // 256MB 0111111 + // 16MB 0011111 + // 1MB 0001111 + // 256KB 0000111 + // 64KB 0000011 + // 16KB 0000001 + // 4KB 0000000 + if (HAVE_CMPMASK == 1) + begin : gen_cmpmask80 + assign pgsize_gte_1G = entry_cmpmask[0]; + assign pgsize_gte_256M = entry_cmpmask[1]; + assign pgsize_gte_16M = entry_cmpmask[2]; + assign pgsize_gte_1M = entry_cmpmask[3]; + assign pgsize_gte_256K = entry_cmpmask[4]; + assign pgsize_gte_64K = entry_cmpmask[5]; + assign pgsize_gte_16K = entry_cmpmask[6]; + + // size entry_xbitmask: 0123456 + // 1GB 1000000 + // 256MB 0100000 + // 16MB 0010000 + // 1MB 0001000 + // 256KB 0000100 + // 64KB 0000010 + // 16KB 0000001 + // 4KB 0000000 + assign pgsize_eq_1G = entry_xbitmask[0]; + assign pgsize_eq_256M = entry_xbitmask[1]; + assign pgsize_eq_16M = entry_xbitmask[2]; + assign pgsize_eq_1M = entry_xbitmask[3]; + assign pgsize_eq_256K = entry_xbitmask[4]; + assign pgsize_eq_64K = entry_xbitmask[5]; + assign pgsize_eq_16K = entry_xbitmask[6]; + end + + //function_30_51 <= '0'; + if (HAVE_XBIT == 0) + begin : gen_noxbit80 + assign function_34_51 = 1'b0; + assign function_36_51 = 1'b0; + assign function_40_51 = 1'b0; + assign function_44_51 = 1'b0; + assign function_46_51 = 1'b0; + assign function_48_51 = 1'b0; + assign function_50_51 = 1'b0; + end + + // 1G + if (HAVE_XBIT != 0) + begin : gen_xbit80 + assign function_34_51 = (~(entry_xbit)) | (~(pgsize_eq_1G)) | |(entry_epn_b[34:51] & addr_in[34:51]); + assign function_36_51 = (~(entry_xbit)) | (~(pgsize_eq_256M)) | |(entry_epn_b[36:51] & addr_in[36:51]); + assign function_40_51 = (~(entry_xbit)) | (~(pgsize_eq_16M)) | |(entry_epn_b[40:51] & addr_in[40:51]); + assign function_44_51 = (~(entry_xbit)) | (~(pgsize_eq_1M)) | |(entry_epn_b[44:51] & addr_in[44:51]); + assign function_46_51 = (~(entry_xbit)) | (~(pgsize_eq_256K)) | |(entry_epn_b[46:51] & addr_in[46:51]); + assign function_48_51 = (~(entry_xbit)) | (~(pgsize_eq_64K)) | |(entry_epn_b[48:51] & addr_in[48:51]); + assign function_50_51 = (~(entry_xbit)) | (~(pgsize_eq_16K)) | |(entry_epn_b[50:51] & addr_in[50:51]); + end + +assign comp_or_50_51 = &(match_line[50:51]) | pgsize_gte_16K; +assign comp_or_48_49 = &(match_line[48:49]) | pgsize_gte_64K; +assign comp_or_46_47 = &(match_line[46:47]) | pgsize_gte_256K; +assign comp_or_44_45 = &(match_line[44:45]) | pgsize_gte_1M; +assign comp_or_40_43 = &(match_line[40:43]) | pgsize_gte_16M; +assign comp_or_36_39 = &(match_line[36:39]) | pgsize_gte_256M; +assign comp_or_34_35 = &(match_line[34:35]) | pgsize_gte_1G; + +if (HAVE_XBIT == 0) // Ignore functions based on page size +begin : gen_noxbit81 + assign addr_match = ( comp_or_34_35 & + comp_or_36_39 & + comp_or_40_43 & + comp_or_44_45 & + comp_or_46_47 & + comp_or_48_49 & + (&(match_line[0:12]) | (~(addr_enable[0]))) & + (&(match_line[13:14]) | (~(addr_enable[1]))) & + (&(match_line[15:16]) | (~(addr_enable[2]))) & + (&(match_line[17:18]) | (~(addr_enable[3]))) & + (&(match_line[19:22]) | (~(addr_enable[4]))) & + (&(match_line[23:26]) | (~(addr_enable[5]))) & + (&(match_line[27:30]) | (~(addr_enable[6]))) & + (&(match_line[31:33]) | (~(addr_enable[7]))) ) // Regular compare largest page size + | (~(addr_enable[8])); // Include address as part of compare, + // should never ignore for regular compare/read. + // Could ignore for compare/invalidate + assign addr_match_xbit_contrib = 1'b0; + + assign addr_match_lsb_contrib = (comp_or_34_35 & + comp_or_36_39 & + comp_or_40_43 & + comp_or_44_45 & + comp_or_46_47 & + comp_or_48_49 & + comp_or_50_51); // Ignore functions based on page size + + assign addr_match_msb_contrib = (&(match_line[0:12]) | (~(addr_enable[0]))) & + (&(match_line[13:14]) | (~(addr_enable[1]))) & + (&(match_line[15:16]) | (~(addr_enable[2]))) & + (&(match_line[17:18]) | (~(addr_enable[3]))) & + (&(match_line[19:22]) | (~(addr_enable[4]))) & + (&(match_line[23:26]) | (~(addr_enable[5]))) & + (&(match_line[27:30]) | (~(addr_enable[6]))) & + (&(match_line[31:33]) | (~(addr_enable[7]))); +end + +if (HAVE_XBIT != 0) // Exclusion functions +begin : gen_xbit81 +// Regular compare largest page size +assign addr_match = ( function_50_51 & + function_48_51 & + function_46_51 & + function_44_51 & + function_40_51 & + function_36_51 & + function_34_51 & + comp_or_34_35 & + comp_or_36_39 & + comp_or_40_43 & + comp_or_44_45 & + comp_or_46_47 & + comp_or_48_49 & + comp_or_50_51 & + (&(match_line[0:12]) | (~(addr_enable[0]))) & + (&(match_line[13:14]) | (~(addr_enable[1]))) & + (&(match_line[15:16]) | (~(addr_enable[2]))) & + (&(match_line[17:18]) | (~(addr_enable[3]))) & + (&(match_line[19:22]) | (~(addr_enable[4]))) & + (&(match_line[23:26]) | (~(addr_enable[5]))) & + (&(match_line[27:30]) | (~(addr_enable[6]))) & + (&(match_line[31:33]) | (~(addr_enable[7]))) ) // Ignore functions based on page size + | (~(addr_enable[8])); // Include address as part of compare, + // should never ignore for regular compare/read. + // Could ignore for compare/invalidate + +assign addr_match_xbit_contrib = (function_50_51 & + function_48_51 & + function_46_51 & + function_44_51 & + function_40_51 & + function_36_51 & + function_34_51); // Exclusion functions + +assign addr_match_lsb_contrib = (comp_or_34_35 & + comp_or_36_39 & + comp_or_40_43 & + comp_or_44_45 & + comp_or_46_47 & + comp_or_48_49 & + comp_or_50_51); // Ignore functions based on page size + +assign addr_match_msb_contrib = (&(match_line[0:12]) | (~(addr_enable[0]))) & + (&(match_line[13:14]) | (~(addr_enable[1]))) & + (&(match_line[15:16]) | (~(addr_enable[2]))) & + (&(match_line[17:18]) | (~(addr_enable[3]))) & + (&(match_line[19:22]) | (~(addr_enable[4]))) & + (&(match_line[23:26]) | (~(addr_enable[5]))) & + (&(match_line[27:30]) | (~(addr_enable[6]))) & + (&(match_line[31:33]) | (~(addr_enable[7]))); +end +end +endgenerate + +// numpgsz8: NUM_PGSIZES = 8 + +// tie off unused signals +generate +if (NUM_PGSIZES == 5) +begin : numpgsz5 +assign function_50_51 = 1'b0; +assign function_46_51 = 1'b0; +assign pgsize_gte_16K = 1'b0; +assign pgsize_gte_256K = 1'b0; +assign pgsize_eq_16K = 1'b0; +assign pgsize_eq_256K = 1'b0; +assign comp_or_44_45 = 1'b0; +assign comp_or_46_47 = 1'b0; +assign comp_or_48_49 = 1'b0; +assign comp_or_50_51 = 1'b0; + +assign entry_epn_b[30:51] = (~(entry_epn[30:51])); + +assign unused_dc[0] = (pgsize_gte_16K & pgsize_gte_256K & pgsize_eq_16K & pgsize_eq_256K); +assign unused_dc[1] = (function_50_51 & function_46_51); +assign unused_dc[2] = (comp_or_44_45 & comp_or_46_47 & comp_or_48_49 & comp_or_50_51); +assign unused_dc[3] = |(entry_epn_b[30:33]); +assign unused_dc[4] = addr_match_xbit_contrib & addr_match_lsb_contrib & addr_match_msb_contrib; +assign unused_dc[5] = vdd; +assign unused_dc[6] = gnd; + +// 1010 +if (HAVE_CMPMASK == 0) +begin : gen_nocmpmask50 +assign pgsize_gte_1G = (entry_size[0] & (~(entry_size[1])) & entry_size[2] & (~(entry_size[3]))); + +// 1001, large indirect entry size +assign pgsize_gte_256M = (entry_size[0] & (~(entry_size[1])) & (~(entry_size[2])) & entry_size[3]) | pgsize_gte_1G; +// 0111 +assign pgsize_gte_16M = ((~(entry_size[0])) & entry_size[1] & entry_size[2] & entry_size[3]) | pgsize_gte_256M; +// 0101 +assign pgsize_gte_1M = ((~(entry_size[0])) & entry_size[1] & (~(entry_size[2])) & entry_size[3]) | pgsize_gte_16M; +// 0011 +assign pgsize_gte_64K = ((~(entry_size[0])) & (~(entry_size[1])) & entry_size[2] & entry_size[3]) | pgsize_gte_1M; + +// 1010 +assign pgsize_eq_1G = (entry_size[0] & (~(entry_size[1])) & entry_size[2] & (~(entry_size[3]))); +// 1001, large indirect entry size +assign pgsize_eq_256M = (entry_size[0] & (~(entry_size[1])) & (~(entry_size[2])) & entry_size[3]); +// 0111 +assign pgsize_eq_16M = ((~(entry_size[0])) & entry_size[1] & entry_size[2] & entry_size[3]); +// 0101 +assign pgsize_eq_1M = ((~(entry_size[0])) & entry_size[1] & (~(entry_size[2])) & entry_size[3]); +// 0011 +assign pgsize_eq_64K = ((~(entry_size[0])) & (~(entry_size[1])) & entry_size[2] & entry_size[3]); +end + +// size entry_cmpmask: 01234 +// 1GB 11111 +// 256MB 01111 +// 16MB 00111 +// 1MB 00011 +// 64KB 00001 +// 4KB 00000 +if (HAVE_CMPMASK == 1) +begin : gen_cmpmask50 +assign pgsize_gte_1G = entry_cmpmask[0]; +assign pgsize_gte_256M = entry_cmpmask[1]; +assign pgsize_gte_16M = entry_cmpmask[2]; +assign pgsize_gte_1M = entry_cmpmask[3]; +assign pgsize_gte_64K = entry_cmpmask[4]; + +// size entry_xbitmask: 01234 +// 1GB 10000 +// 256MB 01000 +// 16MB 00100 +// 1MB 00010 +// 64KB 00001 +// 4KB 00000 +assign pgsize_eq_1G = entry_xbitmask[0]; +assign pgsize_eq_256M = entry_xbitmask[1]; +assign pgsize_eq_16M = entry_xbitmask[2]; +assign pgsize_eq_1M = entry_xbitmask[3]; +assign pgsize_eq_64K = entry_xbitmask[4]; +end + +if (HAVE_XBIT == 0) +begin : gen_noxbit50 +assign function_34_51 = 1'b0; +assign function_36_51 = 1'b0; +assign function_40_51 = 1'b0; +assign function_44_51 = 1'b0; +assign function_48_51 = 1'b0; +end + +// 1G +if (HAVE_XBIT != 0) +begin : gen_xbit50 +assign function_34_51 = (~(entry_xbit)) | (~(pgsize_eq_1G)) | |(entry_epn_b[34:51] & addr_in[34:51]); +// 256M +assign function_36_51 = (~(entry_xbit)) | (~(pgsize_eq_256M)) | |(entry_epn_b[36:51] & addr_in[36:51]); +// 16M +assign function_40_51 = (~(entry_xbit)) | (~(pgsize_eq_16M)) | |(entry_epn_b[40:51] & addr_in[40:51]); +// 1M +assign function_44_51 = (~(entry_xbit)) | (~(pgsize_eq_1M)) | |(entry_epn_b[44:51] & addr_in[44:51]); +// 64K +assign function_48_51 = (~(entry_xbit)) | (~(pgsize_eq_64K)) | |(entry_epn_b[48:51] & addr_in[48:51]); +end + +assign comp_or_48_51 = &(match_line[48:51]) | pgsize_gte_64K; +assign comp_or_44_47 = &(match_line[44:47]) | pgsize_gte_1M; +assign comp_or_40_43 = &(match_line[40:43]) | pgsize_gte_16M; +assign comp_or_36_39 = &(match_line[36:39]) | pgsize_gte_256M; +assign comp_or_34_35 = &(match_line[34:35]) | pgsize_gte_1G; // glorp + +if (HAVE_XBIT == 0) // Ignore functions based on page size +begin : gen_noxbit51 +assign addr_match = (comp_or_34_35 & + comp_or_36_39 & + comp_or_40_43 & + comp_or_44_47 & + comp_or_48_51 & + (&(match_line[0:12]) | (~(addr_enable[0]))) & + (&(match_line[13:14]) | (~(addr_enable[1]))) & + (&(match_line[15:16]) | (~(addr_enable[2]))) & + (&(match_line[17:18]) | (~(addr_enable[3]))) & + (&(match_line[19:22]) | (~(addr_enable[4]))) & + (&(match_line[23:26]) | (~(addr_enable[5]))) & + (&(match_line[27:30]) | (~(addr_enable[6]))) & + (&(match_line[31:33]) | (~(addr_enable[7])))) // Regular compare largest page size + | (~(addr_enable[8])); // Include address as part of compare, + // should never ignore for regular compare/read. + // Could ignore for compare/invalidate +assign addr_match_xbit_contrib = 1'b0; + +assign addr_match_lsb_contrib = (comp_or_34_35 & + comp_or_36_39 & + comp_or_40_43 & + comp_or_44_47 & + comp_or_48_51); // Ignore functions based on page size + +assign addr_match_msb_contrib = (&(match_line[0:12]) | (~(addr_enable[0]))) & + (&(match_line[13:14]) | (~(addr_enable[1]))) & + (&(match_line[15:16]) | (~(addr_enable[2]))) & + (&(match_line[17:18]) | (~(addr_enable[3]))) & + (&(match_line[19:22]) | (~(addr_enable[4]))) & + (&(match_line[23:26]) | (~(addr_enable[5]))) & + (&(match_line[27:30]) | (~(addr_enable[6]))) & + (&(match_line[31:33]) | (~(addr_enable[7]))); +end + +if (HAVE_XBIT != 0) +begin : gen_xbit51 +// Regular compare largest page size +assign addr_match = (function_48_51 & + function_44_51 & + function_40_51 & + function_36_51 & + function_34_51 & + comp_or_34_35 & + comp_or_36_39 & + comp_or_40_43 & + comp_or_44_47 & + comp_or_48_51 & + (&(match_line[0:12]) | (~(addr_enable[0]))) & + (&(match_line[13:14]) | (~(addr_enable[1]))) & + (&(match_line[15:16]) | (~(addr_enable[2]))) & + (&(match_line[17:18]) | (~(addr_enable[3]))) & + (&(match_line[19:22]) | (~(addr_enable[4]))) & + (&(match_line[23:26]) | (~(addr_enable[5]))) & + (&(match_line[27:30]) | (~(addr_enable[6]))) & + (&(match_line[31:33]) | (~(addr_enable[7])))) // Ignore functions based on page size + | (~(addr_enable[8])); // Include address as part of compare, + // should never ignore for regular compare/read. + // Could ignore for compare/invalidate + +assign addr_match_xbit_contrib = (function_48_51 & + function_44_51 & + function_40_51 & + function_36_51 & + function_34_51); // Exclusion functions + +assign addr_match_lsb_contrib = (comp_or_34_35 & + comp_or_36_39 & + comp_or_40_43 & + comp_or_44_47 & + comp_or_48_51); // Ignore functions based on page size + +assign addr_match_msb_contrib = (&(match_line[0:12]) | (~(addr_enable[0]))) & + (&(match_line[13:14]) | (~(addr_enable[1]))) & + (&(match_line[15:16]) | (~(addr_enable[2]))) & + (&(match_line[17:18]) | (~(addr_enable[3]))) & + (&(match_line[19:22]) | (~(addr_enable[4]))) & + (&(match_line[23:26]) | (~(addr_enable[5]))) & + (&(match_line[27:30]) | (~(addr_enable[6]))) & + (&(match_line[31:33]) | (~(addr_enable[7]))); +end +end +endgenerate + +// numpgsz5: NUM_PGSIZES = 5 + +assign pgsize_match = &(match_line[52:55]) | (~(pgsize_enable)); + +assign class_match = &(match_line[56:57]) | (~(class_enable)); + +assign extclass_match = (match_line[58] | (~(extclass_enable[0]))) & (match_line[59] | (~(extclass_enable[1]))); + +assign state_match = (match_line[60] | (~(state_enable[0]))) & (match_line[61] | (~(state_enable[1]))); + +assign thdid_match = |(entry_thdid[0:3] & comp_thdid[0:3]) | (~(thdid_enable)); + +// entry_pid=0 ignores pid match for translation, not invalidation +assign pid_match = &(match_line[62:75]) | ((~(|(entry_pid[0:13]))) & (~comp_invalidate)) | (~(pid_enable)); + +// entry_lpid=0 ignores lpid match for translation, not invalidation +assign lpid_match = &(match_line[76:83]) | ((~(|(entry_lpid[0:7]))) & (~comp_invalidate)) | (~(lpid_enable)); + +assign ind_match = match_line[84] | (~(ind_enable)); + +assign iprot_match = match_line[85] | (~(iprot_enable)); + +// Address compare +// PgSize compare +// Class compare +// ExtClass compare +// State compare +// ThdID compare +// PID compare +// LPID compare +// indirect compare +// inval prot compare +// Valid +assign match = addr_match & + pgsize_match & + class_match & + extclass_match & + state_match & + thdid_match & + pid_match & + lpid_match & + ind_match & + iprot_match & + entry_v; + +// debug outputs +assign dbg_addr_match = addr_match; +assign dbg_pgsize_match = pgsize_match; +assign dbg_class_match = class_match; +assign dbg_extclass_match = extclass_match; +assign dbg_state_match = state_match; +assign dbg_thdid_match = thdid_match; +assign dbg_pid_match = pid_match; +assign dbg_lpid_match = lpid_match; +assign dbg_ind_match = ind_match; +assign dbg_iprot_match = iprot_match; + +endmodule diff --git a/dev/verilog/work/mmq_tlb_req.v b/dev/verilog/work/mmq_tlb_req.v new file mode 100755 index 0000000..09a777c --- /dev/null +++ b/dev/verilog/work/mmq_tlb_req.v @@ -0,0 +1,3650 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +//******************************************************************** +//* TITLE: Memory Management Unit TLB Input Request Queue from ERATs +//* NAME: mmq_tlb_req.v +//********************************************************************* + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" +`include "mmu_a2o.vh" +`define REQ_STATE_WIDTH 4 + +module mmq_tlb_req( + + inout vdd, + inout gnd, + (* pin_data ="PIN_FUNCTION=/G_CLK/" *) + input [0:`NCLK_WIDTH-1] nclk, + + input tc_ccflush_dc, + input tc_scan_dis_dc_b, + input tc_scan_diag_dc, + input tc_lbist_en_dc, + input lcb_d_mode_dc, + input lcb_clkoff_dc_b, + input lcb_act_dis_dc, + input [0:4] lcb_mpw1_dc_b, + input lcb_mpw2_dc_b, + input [0:4] lcb_delay_lclkr_dc, + +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + input ac_func_scan_in, +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + output ac_func_scan_out, + + input pc_sg_2, + input pc_func_sl_thold_2, + input pc_func_slp_sl_thold_2, + + input xu_mm_ccr2_notlb_b, + input mmucr2_act_override, + input [0:`PID_WIDTH-1] pid0, +`ifdef MM_THREADS2 + input [0:`PID_WIDTH-1] pid1, +`endif + input [0:`LPID_WIDTH-1] lpidr, + + input iu_mm_ierat_req, + input [0:51] iu_mm_ierat_epn, + input [0:`THDID_WIDTH-1] iu_mm_ierat_thdid, + input [0:`REQ_STATE_WIDTH-1] iu_mm_ierat_state, + input [0:`PID_WIDTH-1] iu_mm_ierat_tid, + input [0:`THDID_WIDTH-1] iu_mm_ierat_flush, + input iu_mm_ierat_req_nonspec, + + input xu_mm_derat_req, + input [64-`RS_DATA_WIDTH:51] xu_mm_derat_epn, + input [0:`THDID_WIDTH-1] xu_mm_derat_thdid, + input [0:1] xu_mm_derat_ttype, + input [0:`REQ_STATE_WIDTH-1] xu_mm_derat_state, + input [0:`PID_WIDTH-1] xu_mm_derat_tid, + input [0:`LPID_WIDTH-1] xu_mm_derat_lpid, + + input lq_mm_derat_req_nonspec, + input [0:`ITAG_SIZE_ENC-1] lq_mm_derat_req_itag, + input [0:`EMQ_ENTRIES-1] lq_mm_derat_req_emq, + + output [0:`PID_WIDTH-1] ierat_req0_pid, + output ierat_req0_as, + output ierat_req0_gs, + output [0:`EPN_WIDTH-1] ierat_req0_epn, + output [0:`THDID_WIDTH-1] ierat_req0_thdid, + output ierat_req0_valid, + output ierat_req0_nonspec, + + output [0:`PID_WIDTH-1] ierat_req1_pid, + output ierat_req1_as, + output ierat_req1_gs, + output [0:`EPN_WIDTH-1] ierat_req1_epn, + output [0:`THDID_WIDTH-1] ierat_req1_thdid, + output ierat_req1_valid, + output ierat_req1_nonspec, + + output [0:`PID_WIDTH-1] ierat_req2_pid, + output ierat_req2_as, + output ierat_req2_gs, + output [0:`EPN_WIDTH-1] ierat_req2_epn, + output [0:`THDID_WIDTH-1] ierat_req2_thdid, + output ierat_req2_valid, + output ierat_req2_nonspec, + + output [0:`PID_WIDTH-1] ierat_req3_pid, + output ierat_req3_as, + output ierat_req3_gs, + output [0:`EPN_WIDTH-1] ierat_req3_epn, + output [0:`THDID_WIDTH-1] ierat_req3_thdid, + output ierat_req3_valid, + output ierat_req3_nonspec, + + output [0:`PID_WIDTH-1] ierat_iu4_pid, + output ierat_iu4_gs, + output ierat_iu4_as, + output [0:`EPN_WIDTH-1] ierat_iu4_epn, + output [0:`THDID_WIDTH-1] ierat_iu4_thdid, + output ierat_iu4_valid, + + output [0:`LPID_WIDTH-1] derat_req0_lpid, + output [0:`PID_WIDTH-1] derat_req0_pid, + output derat_req0_as, + output derat_req0_gs, + output [0:`EPN_WIDTH-1] derat_req0_epn, + output [0:`THDID_WIDTH-1] derat_req0_thdid, + output [0:`EMQ_ENTRIES-1] derat_req0_emq, + output derat_req0_valid, + output derat_req0_nonspec, + + output [0:`LPID_WIDTH-1] derat_req1_lpid, + output [0:`PID_WIDTH-1] derat_req1_pid, + output derat_req1_as, + output derat_req1_gs, + output [0:`EPN_WIDTH-1] derat_req1_epn, + output [0:`THDID_WIDTH-1] derat_req1_thdid, + output [0:`EMQ_ENTRIES-1] derat_req1_emq, + output derat_req1_valid, + output derat_req1_nonspec, + + output [0:`LPID_WIDTH-1] derat_req2_lpid, + output [0:`PID_WIDTH-1] derat_req2_pid, + output derat_req2_as, + output derat_req2_gs, + output [0:`EPN_WIDTH-1] derat_req2_epn, + output [0:`THDID_WIDTH-1] derat_req2_thdid, + output [0:`EMQ_ENTRIES-1] derat_req2_emq, + output derat_req2_valid, + output derat_req2_nonspec, + + output [0:`LPID_WIDTH-1] derat_req3_lpid, + output [0:`PID_WIDTH-1] derat_req3_pid, + output derat_req3_as, + output derat_req3_gs, + output [0:`EPN_WIDTH-1] derat_req3_epn, + output [0:`THDID_WIDTH-1] derat_req3_thdid, + output [0:`EMQ_ENTRIES-1] derat_req3_emq, + output derat_req3_valid, + output derat_req3_nonspec, + + output [0:`LPID_WIDTH-1] derat_ex5_lpid, + output [0:`PID_WIDTH-1] derat_ex5_pid, + output derat_ex5_gs, + output derat_ex5_as, + output [0:`EPN_WIDTH-1] derat_ex5_epn, + output [0:`THDID_WIDTH-1] derat_ex5_thdid, + output derat_ex5_valid, + + input [0:`THDID_WIDTH-1] xu_ex3_flush, + input [0:`THDID_WIDTH-1] xu_mm_ex4_flush, + input [0:`THDID_WIDTH-1] xu_mm_ex5_flush, + input [0:`THDID_WIDTH-1] xu_mm_ierat_miss, + input [0:`THDID_WIDTH-1] xu_mm_ierat_flush, + + input [0:6] tlb_cmp_ierat_dup_val, + input [0:6] tlb_cmp_derat_dup_val, + output tlb_seq_ierat_req, + output tlb_seq_derat_req, + input tlb_seq_ierat_done, + input tlb_seq_derat_done, + + input ierat_req_taken, + input derat_req_taken, + output [0:`EPN_WIDTH-1] ierat_req_epn, + output [0:`PID_WIDTH-1] ierat_req_pid, + output [0:`REQ_STATE_WIDTH-1] ierat_req_state, + output [0:`THDID_WIDTH-1] ierat_req_thdid, + output [0:1] ierat_req_dup, + output ierat_req_nonspec, + + output [0:`EPN_WIDTH-1] derat_req_epn, + output [0:`PID_WIDTH-1] derat_req_pid, + output [0:`LPID_WIDTH-1] derat_req_lpid, + output [0:`REQ_STATE_WIDTH-1] derat_req_state, + output [0:1] derat_req_ttype, + output [0:`THDID_WIDTH-1] derat_req_thdid, + output [0:1] derat_req_dup, + output [0:`ITAG_SIZE_ENC-1] derat_req_itag, + output [0:`EMQ_ENTRIES-1] derat_req_emq, + output derat_req_nonspec, + + output [0:`THDID_WIDTH-1] tlb_req_quiesce, + + output tlb_req_dbg_ierat_iu5_valid_q, + output [0:1] tlb_req_dbg_ierat_iu5_thdid, + output [0:3] tlb_req_dbg_ierat_iu5_state_q, + output [0:1] tlb_req_dbg_ierat_inptr_q, + output [0:1] tlb_req_dbg_ierat_outptr_q, + output [0:3] tlb_req_dbg_ierat_req_valid_q, + output [0:3] tlb_req_dbg_ierat_req_nonspec_q, + output [0:7] tlb_req_dbg_ierat_req_thdid, + output [0:3] tlb_req_dbg_ierat_req_dup_q, + output tlb_req_dbg_derat_ex6_valid_q, + output [0:1] tlb_req_dbg_derat_ex6_thdid, + output [0:3] tlb_req_dbg_derat_ex6_state_q, + output [0:1] tlb_req_dbg_derat_inptr_q, + output [0:1] tlb_req_dbg_derat_outptr_q, + output [0:3] tlb_req_dbg_derat_req_valid_q, + output [0:7] tlb_req_dbg_derat_req_thdid, + output [0:7] tlb_req_dbg_derat_req_ttype_q, + output [0:3] tlb_req_dbg_derat_req_dup_q + +); + + + parameter MMU_Mode_Value = 1'b0; + parameter [0:1] TlbSel_Tlb = 2'b00; + parameter [0:1] TlbSel_IErat = 2'b10; + parameter [0:1] TlbSel_DErat = 2'b11; + parameter ierat_req0_valid_offset = 0; + parameter ierat_req0_nonspec_offset = ierat_req0_valid_offset + 1; + parameter ierat_req0_thdid_offset = ierat_req0_nonspec_offset + 1; + parameter ierat_req0_epn_offset = ierat_req0_thdid_offset + `THDID_WIDTH; + parameter ierat_req0_state_offset = ierat_req0_epn_offset + `EPN_WIDTH; + parameter ierat_req0_pid_offset = ierat_req0_state_offset + `REQ_STATE_WIDTH; + parameter ierat_req0_dup_offset = ierat_req0_pid_offset + `PID_WIDTH; + parameter ierat_req1_valid_offset = ierat_req0_dup_offset + 2; + parameter ierat_req1_nonspec_offset = ierat_req1_valid_offset + 1; + parameter ierat_req1_thdid_offset = ierat_req1_nonspec_offset + 1; + parameter ierat_req1_epn_offset = ierat_req1_thdid_offset + `THDID_WIDTH; + parameter ierat_req1_state_offset = ierat_req1_epn_offset + `EPN_WIDTH; + parameter ierat_req1_pid_offset = ierat_req1_state_offset + `REQ_STATE_WIDTH; + parameter ierat_req1_dup_offset = ierat_req1_pid_offset + `PID_WIDTH; + parameter ierat_req2_valid_offset = ierat_req1_dup_offset + 2; + parameter ierat_req2_nonspec_offset = ierat_req2_valid_offset + 1; + parameter ierat_req2_thdid_offset = ierat_req2_nonspec_offset + 1; + parameter ierat_req2_epn_offset = ierat_req2_thdid_offset + `THDID_WIDTH; + parameter ierat_req2_state_offset = ierat_req2_epn_offset + `EPN_WIDTH; + parameter ierat_req2_pid_offset = ierat_req2_state_offset + `REQ_STATE_WIDTH; + parameter ierat_req2_dup_offset = ierat_req2_pid_offset + `PID_WIDTH; + parameter ierat_req3_valid_offset = ierat_req2_dup_offset + 2; + parameter ierat_req3_nonspec_offset = ierat_req3_valid_offset + 1; + parameter ierat_req3_thdid_offset = ierat_req3_nonspec_offset + 1; + parameter ierat_req3_epn_offset = ierat_req3_thdid_offset + `THDID_WIDTH; + parameter ierat_req3_state_offset = ierat_req3_epn_offset + `EPN_WIDTH; + parameter ierat_req3_pid_offset = ierat_req3_state_offset + `REQ_STATE_WIDTH; + parameter ierat_req3_dup_offset = ierat_req3_pid_offset + `PID_WIDTH; + parameter ierat_inptr_offset = ierat_req3_dup_offset + 2; + parameter ierat_outptr_offset = ierat_inptr_offset + 2; + parameter tlb_seq_ierat_req_offset = ierat_outptr_offset + 2; + parameter ierat_iu3_flush_offset = tlb_seq_ierat_req_offset + 1; + parameter xu_mm_ierat_flush_offset = ierat_iu3_flush_offset + `THDID_WIDTH; + parameter xu_mm_ierat_miss_offset = xu_mm_ierat_flush_offset + `THDID_WIDTH; + parameter ierat_iu3_valid_offset = xu_mm_ierat_miss_offset + `THDID_WIDTH; + parameter ierat_iu3_thdid_offset = ierat_iu3_valid_offset + 1; + parameter ierat_iu3_epn_offset = ierat_iu3_thdid_offset + `THDID_WIDTH; + parameter ierat_iu3_state_offset = ierat_iu3_epn_offset + `EPN_WIDTH; + parameter ierat_iu3_pid_offset = ierat_iu3_state_offset + `REQ_STATE_WIDTH; + parameter ierat_iu4_valid_offset = ierat_iu3_pid_offset + `PID_WIDTH; + parameter ierat_iu4_thdid_offset = ierat_iu4_valid_offset + 1; + parameter ierat_iu4_epn_offset = ierat_iu4_thdid_offset + `THDID_WIDTH; + parameter ierat_iu4_state_offset = ierat_iu4_epn_offset + `EPN_WIDTH; + parameter ierat_iu4_pid_offset = ierat_iu4_state_offset + `REQ_STATE_WIDTH; + parameter ierat_iu5_valid_offset = ierat_iu4_pid_offset + `PID_WIDTH; + parameter ierat_iu5_thdid_offset = ierat_iu5_valid_offset + 1; + parameter ierat_iu5_epn_offset = ierat_iu5_thdid_offset + `THDID_WIDTH; + parameter ierat_iu5_state_offset = ierat_iu5_epn_offset + `EPN_WIDTH; + parameter ierat_iu5_pid_offset = ierat_iu5_state_offset + `REQ_STATE_WIDTH; + parameter ierat_iu3_nonspec_offset = ierat_iu5_pid_offset + `PID_WIDTH; + parameter ierat_iu4_nonspec_offset = ierat_iu3_nonspec_offset + 1; + parameter ierat_iu5_nonspec_offset = ierat_iu4_nonspec_offset + 1; + parameter derat_req0_valid_offset = ierat_iu5_nonspec_offset + 1; + parameter derat_req0_thdid_offset = derat_req0_valid_offset + 1; + parameter derat_req0_epn_offset = derat_req0_thdid_offset + `THDID_WIDTH; + parameter derat_req0_state_offset = derat_req0_epn_offset + `EPN_WIDTH; + parameter derat_req0_ttype_offset = derat_req0_state_offset + `REQ_STATE_WIDTH; + parameter derat_req0_pid_offset = derat_req0_ttype_offset + 2; + parameter derat_req0_lpid_offset = derat_req0_pid_offset + `PID_WIDTH; + parameter derat_req0_dup_offset = derat_req0_lpid_offset + `LPID_WIDTH; + parameter derat_req1_valid_offset = derat_req0_dup_offset + 2; + parameter derat_req1_thdid_offset = derat_req1_valid_offset + 1; + parameter derat_req1_epn_offset = derat_req1_thdid_offset + `THDID_WIDTH; + parameter derat_req1_state_offset = derat_req1_epn_offset + `EPN_WIDTH; + parameter derat_req1_ttype_offset = derat_req1_state_offset + `REQ_STATE_WIDTH; + parameter derat_req1_pid_offset = derat_req1_ttype_offset + 2; + parameter derat_req1_lpid_offset = derat_req1_pid_offset + `PID_WIDTH; + parameter derat_req1_dup_offset = derat_req1_lpid_offset + `LPID_WIDTH; + parameter derat_req2_valid_offset = derat_req1_dup_offset + 2; + parameter derat_req2_thdid_offset = derat_req2_valid_offset + 1; + parameter derat_req2_epn_offset = derat_req2_thdid_offset + `THDID_WIDTH; + parameter derat_req2_state_offset = derat_req2_epn_offset + `EPN_WIDTH; + parameter derat_req2_ttype_offset = derat_req2_state_offset + `REQ_STATE_WIDTH; + parameter derat_req2_pid_offset = derat_req2_ttype_offset + 2; + parameter derat_req2_lpid_offset = derat_req2_pid_offset + `PID_WIDTH; + parameter derat_req2_dup_offset = derat_req2_lpid_offset + `LPID_WIDTH; + parameter derat_req3_valid_offset = derat_req2_dup_offset + 2; + parameter derat_req3_thdid_offset = derat_req3_valid_offset + 1; + parameter derat_req3_epn_offset = derat_req3_thdid_offset + `THDID_WIDTH; + parameter derat_req3_state_offset = derat_req3_epn_offset + `EPN_WIDTH; + parameter derat_req3_ttype_offset = derat_req3_state_offset + `REQ_STATE_WIDTH; + parameter derat_req3_pid_offset = derat_req3_ttype_offset + 2; + parameter derat_req3_lpid_offset = derat_req3_pid_offset + `PID_WIDTH; + parameter derat_req3_dup_offset = derat_req3_lpid_offset + `LPID_WIDTH; + parameter derat_inptr_offset = derat_req3_dup_offset + 2; + parameter derat_outptr_offset = derat_inptr_offset + 2; + parameter tlb_seq_derat_req_offset = derat_outptr_offset + 2; + parameter derat_ex4_valid_offset = tlb_seq_derat_req_offset + 1; + parameter derat_ex4_thdid_offset = derat_ex4_valid_offset + 1; + parameter derat_ex4_epn_offset = derat_ex4_thdid_offset + `THDID_WIDTH; + parameter derat_ex4_state_offset = derat_ex4_epn_offset + `EPN_WIDTH; + parameter derat_ex4_ttype_offset = derat_ex4_state_offset + `REQ_STATE_WIDTH; + parameter derat_ex4_pid_offset = derat_ex4_ttype_offset + 2; + parameter derat_ex4_lpid_offset = derat_ex4_pid_offset + `PID_WIDTH; + parameter derat_ex5_valid_offset = derat_ex4_lpid_offset + `LPID_WIDTH; + parameter derat_ex5_thdid_offset = derat_ex5_valid_offset + 1; + parameter derat_ex5_epn_offset = derat_ex5_thdid_offset + `THDID_WIDTH; + parameter derat_ex5_state_offset = derat_ex5_epn_offset + `EPN_WIDTH; + parameter derat_ex5_ttype_offset = derat_ex5_state_offset + `REQ_STATE_WIDTH; + parameter derat_ex5_pid_offset = derat_ex5_ttype_offset + 2; + parameter derat_ex5_lpid_offset = derat_ex5_pid_offset + `PID_WIDTH; + parameter derat_ex6_valid_offset = derat_ex5_lpid_offset + `LPID_WIDTH; + parameter derat_ex6_thdid_offset = derat_ex6_valid_offset + 1; + parameter derat_ex6_epn_offset = derat_ex6_thdid_offset + `THDID_WIDTH; + parameter derat_ex6_state_offset = derat_ex6_epn_offset + `EPN_WIDTH; + parameter derat_ex6_ttype_offset = derat_ex6_state_offset + `REQ_STATE_WIDTH; + parameter derat_ex6_pid_offset = derat_ex6_ttype_offset + 2; + parameter derat_ex6_lpid_offset = derat_ex6_pid_offset + `PID_WIDTH; + parameter derat_ex4_itag_offset = derat_ex6_lpid_offset + `LPID_WIDTH; + parameter derat_ex4_emq_offset = derat_ex4_itag_offset + `ITAG_SIZE_ENC; + parameter derat_ex4_nonspec_offset = derat_ex4_emq_offset + `EMQ_ENTRIES; + parameter derat_ex5_itag_offset = derat_ex4_nonspec_offset + 1; + parameter derat_ex5_emq_offset = derat_ex5_itag_offset + `ITAG_SIZE_ENC; + parameter derat_ex5_nonspec_offset = derat_ex5_emq_offset + `EMQ_ENTRIES; + parameter derat_ex6_itag_offset = derat_ex5_nonspec_offset + 1; + parameter derat_ex6_emq_offset = derat_ex6_itag_offset + `ITAG_SIZE_ENC; + parameter derat_ex6_nonspec_offset = derat_ex6_emq_offset + `EMQ_ENTRIES; + parameter derat_req0_itag_offset = derat_ex6_nonspec_offset + 1; + parameter derat_req0_emq_offset = derat_req0_itag_offset + `ITAG_SIZE_ENC; + parameter derat_req0_nonspec_offset = derat_req0_emq_offset + `EMQ_ENTRIES; + parameter derat_req1_itag_offset = derat_req0_nonspec_offset + 1; + parameter derat_req1_emq_offset = derat_req1_itag_offset + `ITAG_SIZE_ENC; + parameter derat_req1_nonspec_offset = derat_req1_emq_offset + `EMQ_ENTRIES; + parameter derat_req2_itag_offset = derat_req1_nonspec_offset + 1; + parameter derat_req2_emq_offset = derat_req2_itag_offset + `ITAG_SIZE_ENC; + parameter derat_req2_nonspec_offset = derat_req2_emq_offset + `EMQ_ENTRIES; + parameter derat_req3_itag_offset = derat_req2_nonspec_offset + 1; + parameter derat_req3_emq_offset = derat_req3_itag_offset + `ITAG_SIZE_ENC; + parameter derat_req3_nonspec_offset = derat_req3_emq_offset + `EMQ_ENTRIES; + parameter spare_offset = derat_req3_nonspec_offset + 1; + parameter scan_right = spare_offset + 32 - 1; + +`ifdef MM_THREADS2 + parameter BUGSP_MM_THREADS = 2; +`else + parameter BUGSP_MM_THREADS = 1; +`endif + + // Latch signals + wire ierat_req0_valid_d; + wire ierat_req0_valid_q; + wire ierat_req0_nonspec_d; + wire ierat_req0_nonspec_q; + wire [0:`THDID_WIDTH-1] ierat_req0_thdid_d; + wire [0:`THDID_WIDTH-1] ierat_req0_thdid_q; + wire [0:`EPN_WIDTH-1] ierat_req0_epn_d; + wire [0:`EPN_WIDTH-1] ierat_req0_epn_q; + wire [0:`REQ_STATE_WIDTH-1] ierat_req0_state_d; + wire [0:`REQ_STATE_WIDTH-1] ierat_req0_state_q; + wire [0:`PID_WIDTH-1] ierat_req0_pid_d; + wire [0:`PID_WIDTH-1] ierat_req0_pid_q; + wire [0:1] ierat_req0_dup_d; + wire [0:1] ierat_req0_dup_q; + wire ierat_req1_valid_d; + wire ierat_req1_valid_q; + wire ierat_req1_nonspec_d; + wire ierat_req1_nonspec_q; + wire [0:`THDID_WIDTH-1] ierat_req1_thdid_d; + wire [0:`THDID_WIDTH-1] ierat_req1_thdid_q; + wire [0:`EPN_WIDTH-1] ierat_req1_epn_d; + wire [0:`EPN_WIDTH-1] ierat_req1_epn_q; + wire [0:`REQ_STATE_WIDTH-1] ierat_req1_state_d; + wire [0:`REQ_STATE_WIDTH-1] ierat_req1_state_q; + wire [0:`PID_WIDTH-1] ierat_req1_pid_d; + wire [0:`PID_WIDTH-1] ierat_req1_pid_q; + wire [0:1] ierat_req1_dup_d; + wire [0:1] ierat_req1_dup_q; + wire ierat_req2_valid_d; + wire ierat_req2_valid_q; + wire ierat_req2_nonspec_d; + wire ierat_req2_nonspec_q; + wire [0:`THDID_WIDTH-1] ierat_req2_thdid_d; + wire [0:`THDID_WIDTH-1] ierat_req2_thdid_q; + wire [0:`EPN_WIDTH-1] ierat_req2_epn_d; + wire [0:`EPN_WIDTH-1] ierat_req2_epn_q; + wire [0:`REQ_STATE_WIDTH-1] ierat_req2_state_d; + wire [0:`REQ_STATE_WIDTH-1] ierat_req2_state_q; + wire [0:`PID_WIDTH-1] ierat_req2_pid_d; + wire [0:`PID_WIDTH-1] ierat_req2_pid_q; + wire [0:1] ierat_req2_dup_d; + wire [0:1] ierat_req2_dup_q; + wire ierat_req3_valid_d; + wire ierat_req3_valid_q; + wire ierat_req3_nonspec_d; + wire ierat_req3_nonspec_q; + wire [0:`THDID_WIDTH-1] ierat_req3_thdid_d; + wire [0:`THDID_WIDTH-1] ierat_req3_thdid_q; + wire [0:`EPN_WIDTH-1] ierat_req3_epn_d; + wire [0:`EPN_WIDTH-1] ierat_req3_epn_q; + wire [0:`REQ_STATE_WIDTH-1] ierat_req3_state_d; + wire [0:`REQ_STATE_WIDTH-1] ierat_req3_state_q; + wire [0:`PID_WIDTH-1] ierat_req3_pid_d; + wire [0:`PID_WIDTH-1] ierat_req3_pid_q; + wire [0:1] ierat_req3_dup_d; + wire [0:1] ierat_req3_dup_q; + wire ierat_iu3_valid_d; + wire ierat_iu3_valid_q; + wire [0:`THDID_WIDTH-1] ierat_iu3_thdid_d; + wire [0:`THDID_WIDTH-1] ierat_iu3_thdid_q; + wire [0:`EPN_WIDTH-1] ierat_iu3_epn_d; + wire [0:`EPN_WIDTH-1] ierat_iu3_epn_q; + wire [0:`REQ_STATE_WIDTH-1] ierat_iu3_state_d; + wire [0:`REQ_STATE_WIDTH-1] ierat_iu3_state_q; + wire [0:`PID_WIDTH-1] ierat_iu3_pid_d; + wire [0:`PID_WIDTH-1] ierat_iu3_pid_q; + wire ierat_iu3_nonspec_d; + wire ierat_iu3_nonspec_q; + wire ierat_iu4_valid_d; + wire ierat_iu4_valid_q; + wire [0:`THDID_WIDTH-1] ierat_iu4_thdid_d; + wire [0:`THDID_WIDTH-1] ierat_iu4_thdid_q; + wire [0:`EPN_WIDTH-1] ierat_iu4_epn_d; + wire [0:`EPN_WIDTH-1] ierat_iu4_epn_q; + wire [0:`REQ_STATE_WIDTH-1] ierat_iu4_state_d; + wire [0:`REQ_STATE_WIDTH-1] ierat_iu4_state_q; + wire [0:`PID_WIDTH-1] ierat_iu4_pid_d; + wire [0:`PID_WIDTH-1] ierat_iu4_pid_q; + wire ierat_iu4_nonspec_d; + wire ierat_iu4_nonspec_q; + wire ierat_iu5_valid_d; + wire ierat_iu5_valid_q; + wire [0:`THDID_WIDTH-1] ierat_iu5_thdid_d; + wire [0:`THDID_WIDTH-1] ierat_iu5_thdid_q; + wire [0:`EPN_WIDTH-1] ierat_iu5_epn_d; + wire [0:`EPN_WIDTH-1] ierat_iu5_epn_q; + wire [0:`REQ_STATE_WIDTH-1] ierat_iu5_state_d; + wire [0:`REQ_STATE_WIDTH-1] ierat_iu5_state_q; + wire [0:`PID_WIDTH-1] ierat_iu5_pid_d; + wire [0:`PID_WIDTH-1] ierat_iu5_pid_q; + wire ierat_iu5_nonspec_d; + wire ierat_iu5_nonspec_q; + wire [0:`THDID_WIDTH-1] ierat_iu3_flush_d; + wire [0:`THDID_WIDTH-1] ierat_iu3_flush_q; + wire [0:`THDID_WIDTH-1] xu_mm_ierat_flush_d; + wire [0:`THDID_WIDTH-1] xu_mm_ierat_flush_q; + wire [0:`THDID_WIDTH-1] xu_mm_ierat_miss_d; + wire [0:`THDID_WIDTH-1] xu_mm_ierat_miss_q; + wire [0:1] ierat_inptr_d; + wire [0:1] ierat_inptr_q; + wire [0:1] ierat_outptr_d; + wire [0:1] ierat_outptr_q; + wire tlb_seq_ierat_req_d; + wire tlb_seq_ierat_req_q; + wire derat_req0_valid_d; + wire derat_req0_valid_q; + wire [0:`THDID_WIDTH-1] derat_req0_thdid_d; + wire [0:`THDID_WIDTH-1] derat_req0_thdid_q; + wire [0:`EPN_WIDTH-1] derat_req0_epn_d; + wire [0:`EPN_WIDTH-1] derat_req0_epn_q; + wire [0:`REQ_STATE_WIDTH-1] derat_req0_state_d; + wire [0:`REQ_STATE_WIDTH-1] derat_req0_state_q; + wire [0:1] derat_req0_ttype_d; + wire [0:1] derat_req0_ttype_q; + wire [0:`PID_WIDTH-1] derat_req0_pid_d; + wire [0:`PID_WIDTH-1] derat_req0_pid_q; + wire [0:`LPID_WIDTH-1] derat_req0_lpid_d; + wire [0:`LPID_WIDTH-1] derat_req0_lpid_q; + wire [0:1] derat_req0_dup_d; + wire [0:1] derat_req0_dup_q; + wire [0:`ITAG_SIZE_ENC-1] derat_req0_itag_d; + wire [0:`ITAG_SIZE_ENC-1] derat_req0_itag_q; + wire [0:`EMQ_ENTRIES-1] derat_req0_emq_d; + wire [0:`EMQ_ENTRIES-1] derat_req0_emq_q; + wire derat_req0_nonspec_d; + wire derat_req0_nonspec_q; + wire derat_req1_valid_d; + wire derat_req1_valid_q; + wire [0:`THDID_WIDTH-1] derat_req1_thdid_d; + wire [0:`THDID_WIDTH-1] derat_req1_thdid_q; + wire [0:`EPN_WIDTH-1] derat_req1_epn_d; + wire [0:`EPN_WIDTH-1] derat_req1_epn_q; + wire [0:`REQ_STATE_WIDTH-1] derat_req1_state_d; + wire [0:`REQ_STATE_WIDTH-1] derat_req1_state_q; + wire [0:1] derat_req1_ttype_d; + wire [0:1] derat_req1_ttype_q; + wire [0:`PID_WIDTH-1] derat_req1_pid_d; + wire [0:`PID_WIDTH-1] derat_req1_pid_q; + wire [0:`LPID_WIDTH-1] derat_req1_lpid_d; + wire [0:`LPID_WIDTH-1] derat_req1_lpid_q; + wire [0:1] derat_req1_dup_d; + wire [0:1] derat_req1_dup_q; + wire [0:`ITAG_SIZE_ENC-1] derat_req1_itag_d; + wire [0:`ITAG_SIZE_ENC-1] derat_req1_itag_q; + wire [0:`EMQ_ENTRIES-1] derat_req1_emq_d; + wire [0:`EMQ_ENTRIES-1] derat_req1_emq_q; + wire derat_req1_nonspec_d; + wire derat_req1_nonspec_q; + wire derat_req2_valid_d; + wire derat_req2_valid_q; + wire [0:`THDID_WIDTH-1] derat_req2_thdid_d; + wire [0:`THDID_WIDTH-1] derat_req2_thdid_q; + wire [0:`EPN_WIDTH-1] derat_req2_epn_d; + wire [0:`EPN_WIDTH-1] derat_req2_epn_q; + wire [0:`REQ_STATE_WIDTH-1] derat_req2_state_d; + wire [0:`REQ_STATE_WIDTH-1] derat_req2_state_q; + wire [0:1] derat_req2_ttype_d; + wire [0:1] derat_req2_ttype_q; + wire [0:`PID_WIDTH-1] derat_req2_pid_d; + wire [0:`PID_WIDTH-1] derat_req2_pid_q; + wire [0:`LPID_WIDTH-1] derat_req2_lpid_d; + wire [0:`LPID_WIDTH-1] derat_req2_lpid_q; + wire [0:1] derat_req2_dup_d; + wire [0:1] derat_req2_dup_q; + wire [0:`ITAG_SIZE_ENC-1] derat_req2_itag_d; + wire [0:`ITAG_SIZE_ENC-1] derat_req2_itag_q; + wire [0:`EMQ_ENTRIES-1] derat_req2_emq_d; + wire [0:`EMQ_ENTRIES-1] derat_req2_emq_q; + wire derat_req2_nonspec_d; + wire derat_req2_nonspec_q; + wire derat_req3_valid_d; + wire derat_req3_valid_q; + wire [0:`THDID_WIDTH-1] derat_req3_thdid_d; + wire [0:`THDID_WIDTH-1] derat_req3_thdid_q; + wire [0:`EPN_WIDTH-1] derat_req3_epn_d; + wire [0:`EPN_WIDTH-1] derat_req3_epn_q; + wire [0:`REQ_STATE_WIDTH-1] derat_req3_state_d; + wire [0:`REQ_STATE_WIDTH-1] derat_req3_state_q; + wire [0:1] derat_req3_ttype_d; + wire [0:1] derat_req3_ttype_q; + wire [0:`PID_WIDTH-1] derat_req3_pid_d; + wire [0:`PID_WIDTH-1] derat_req3_pid_q; + wire [0:`LPID_WIDTH-1] derat_req3_lpid_d; + wire [0:`LPID_WIDTH-1] derat_req3_lpid_q; + wire [0:1] derat_req3_dup_d; + wire [0:1] derat_req3_dup_q; + wire [0:`ITAG_SIZE_ENC-1] derat_req3_itag_d; + wire [0:`ITAG_SIZE_ENC-1] derat_req3_itag_q; + wire [0:`EMQ_ENTRIES-1] derat_req3_emq_d; + wire [0:`EMQ_ENTRIES-1] derat_req3_emq_q; + wire derat_req3_nonspec_d; + wire derat_req3_nonspec_q; + wire derat_ex4_valid_d; + wire derat_ex4_valid_q; + wire [0:`THDID_WIDTH-1] derat_ex4_thdid_d; + wire [0:`THDID_WIDTH-1] derat_ex4_thdid_q; + wire [0:`EPN_WIDTH-1] derat_ex4_epn_d; + wire [0:`EPN_WIDTH-1] derat_ex4_epn_q; + wire [0:`REQ_STATE_WIDTH-1] derat_ex4_state_d; + wire [0:`REQ_STATE_WIDTH-1] derat_ex4_state_q; + wire [0:1] derat_ex4_ttype_d; + wire [0:1] derat_ex4_ttype_q; + wire [0:`PID_WIDTH-1] derat_ex4_pid_d; + wire [0:`PID_WIDTH-1] derat_ex4_pid_q; + wire [0:`LPID_WIDTH-1] derat_ex4_lpid_d; + wire [0:`LPID_WIDTH-1] derat_ex4_lpid_q; + wire [0:`ITAG_SIZE_ENC-1] derat_ex4_itag_d; + wire [0:`ITAG_SIZE_ENC-1] derat_ex4_itag_q; + wire [0:`EMQ_ENTRIES-1] derat_ex4_emq_d; + wire [0:`EMQ_ENTRIES-1] derat_ex4_emq_q; + wire derat_ex4_nonspec_d; + wire derat_ex4_nonspec_q; + wire derat_ex5_valid_d; + wire derat_ex5_valid_q; + wire [0:`THDID_WIDTH-1] derat_ex5_thdid_d; + wire [0:`THDID_WIDTH-1] derat_ex5_thdid_q; + wire [0:`EPN_WIDTH-1] derat_ex5_epn_d; + wire [0:`EPN_WIDTH-1] derat_ex5_epn_q; + wire [0:`REQ_STATE_WIDTH-1] derat_ex5_state_d; + wire [0:`REQ_STATE_WIDTH-1] derat_ex5_state_q; + wire [0:1] derat_ex5_ttype_d; + wire [0:1] derat_ex5_ttype_q; + wire [0:`PID_WIDTH-1] derat_ex5_pid_d; + wire [0:`PID_WIDTH-1] derat_ex5_pid_q; + wire [0:`LPID_WIDTH-1] derat_ex5_lpid_d; + wire [0:`LPID_WIDTH-1] derat_ex5_lpid_q; + wire [0:`ITAG_SIZE_ENC-1] derat_ex5_itag_d; + wire [0:`ITAG_SIZE_ENC-1] derat_ex5_itag_q; + wire [0:`EMQ_ENTRIES-1] derat_ex5_emq_d; + wire [0:`EMQ_ENTRIES-1] derat_ex5_emq_q; + wire derat_ex5_nonspec_d; + wire derat_ex5_nonspec_q; + wire derat_ex6_valid_d; + wire derat_ex6_valid_q; + wire [0:`THDID_WIDTH-1] derat_ex6_thdid_d; + wire [0:`THDID_WIDTH-1] derat_ex6_thdid_q; + wire [0:`EPN_WIDTH-1] derat_ex6_epn_d; + wire [0:`EPN_WIDTH-1] derat_ex6_epn_q; + wire [0:`REQ_STATE_WIDTH-1] derat_ex6_state_d; + wire [0:`REQ_STATE_WIDTH-1] derat_ex6_state_q; + wire [0:1] derat_ex6_ttype_d; + wire [0:1] derat_ex6_ttype_q; + wire [0:`PID_WIDTH-1] derat_ex6_pid_d; + wire [0:`PID_WIDTH-1] derat_ex6_pid_q; + wire [0:`LPID_WIDTH-1] derat_ex6_lpid_d; + wire [0:`LPID_WIDTH-1] derat_ex6_lpid_q; + wire [0:`ITAG_SIZE_ENC-1] derat_ex6_itag_d; + wire [0:`ITAG_SIZE_ENC-1] derat_ex6_itag_q; + wire [0:`EMQ_ENTRIES-1] derat_ex6_emq_d; + wire [0:`EMQ_ENTRIES-1] derat_ex6_emq_q; + wire derat_ex6_nonspec_d; + wire derat_ex6_nonspec_q; + wire [0:1] derat_inptr_d; + wire [0:1] derat_inptr_q; + wire [0:1] derat_outptr_d; + wire [0:1] derat_outptr_q; + wire tlb_seq_derat_req_d; + wire tlb_seq_derat_req_q; + wire [0:31] spare_q; + // logic signals + wire [0:`PID_WIDTH-1] ierat_req_pid_mux; + wire [0:`THDID_WIDTH-1] tlb_req_quiesce_b; + + (* analysis_not_referenced="true" *) + wire [0:16] unused_dc; + + // Pervasive + wire pc_sg_1; + wire pc_sg_0; + wire pc_func_sl_thold_1; + wire pc_func_sl_thold_0; + wire pc_func_sl_thold_0_b; + wire pc_func_slp_sl_thold_1; + wire pc_func_slp_sl_thold_0; + wire pc_func_slp_sl_thold_0_b; + wire pc_func_sl_force; + wire pc_func_slp_sl_force; + wire [0:scan_right] siv; + wire [0:scan_right] sov; + + //!! Bugspray Include: mmq_tlb_req; + //--------------------------------------------------------------------- + // Logic + //--------------------------------------------------------------------- + //--------------------------------------------------------------------- + // Common stuff for erat-only and tlb + //--------------------------------------------------------------------- + + // not quiesced + assign tlb_req_quiesce_b[0:`THDID_WIDTH - 1] = ({`THDID_WIDTH{ierat_req0_valid_q}} & ierat_req0_thdid_q[0:`THDID_WIDTH - 1]) | + ({`THDID_WIDTH{ierat_req1_valid_q}} & ierat_req1_thdid_q[0:`THDID_WIDTH - 1]) | + ({`THDID_WIDTH{ierat_req2_valid_q}} & ierat_req2_thdid_q[0:`THDID_WIDTH - 1]) | + ({`THDID_WIDTH{ierat_req3_valid_q}} & ierat_req3_thdid_q[0:`THDID_WIDTH - 1]) | + ({`THDID_WIDTH{derat_req0_valid_q}} & derat_req0_thdid_q[0:`THDID_WIDTH - 1]) | + ({`THDID_WIDTH{derat_req1_valid_q}} & derat_req1_thdid_q[0:`THDID_WIDTH - 1]) | + ({`THDID_WIDTH{derat_req2_valid_q}} & derat_req2_thdid_q[0:`THDID_WIDTH - 1]) | + ({`THDID_WIDTH{derat_req3_valid_q}} & derat_req3_thdid_q[0:`THDID_WIDTH - 1]) | + ({`THDID_WIDTH{derat_ex4_valid_q}} & derat_ex4_thdid_q[0:`THDID_WIDTH - 1]) | + ({`THDID_WIDTH{derat_ex5_valid_q}} & derat_ex5_thdid_q[0:`THDID_WIDTH - 1]) | + ({`THDID_WIDTH{derat_ex6_valid_q}} & derat_ex6_thdid_q[0:`THDID_WIDTH - 1]) | + ({`THDID_WIDTH{ierat_iu3_valid_q}} & ierat_iu3_thdid_q[0:`THDID_WIDTH - 1]) | + ({`THDID_WIDTH{ierat_iu4_valid_q}} & ierat_iu4_thdid_q[0:`THDID_WIDTH - 1]) | + ({`THDID_WIDTH{ierat_iu5_valid_q}} & ierat_iu5_thdid_q[0:`THDID_WIDTH - 1]); + + assign tlb_req_quiesce = (~tlb_req_quiesce_b); + assign xu_mm_ierat_flush_d = xu_mm_ierat_flush; + assign xu_mm_ierat_miss_d = xu_mm_ierat_miss; + // iu pipe for non-speculative ierat flush processing + assign ierat_iu3_flush_d = iu_mm_ierat_flush; + assign ierat_iu3_valid_d = iu_mm_ierat_req; + assign ierat_iu4_valid_d = ((ierat_iu3_valid_q == 1'b1 & |(ierat_iu3_thdid_q & (~(ierat_iu3_flush_q)) & (~(xu_mm_ierat_flush_q))) == 1'b1)) ? 1'b1 : + 1'b0; + assign ierat_iu5_valid_d = ((ierat_iu4_valid_q == 1'b1 & |(ierat_iu4_thdid_q & (~(ierat_iu3_flush_q)) & (~(xu_mm_ierat_flush_q))) == 1'b1)) ? 1'b1 : + 1'b0; + assign ierat_iu3_thdid_d = iu_mm_ierat_thdid; + assign ierat_iu3_state_d = iu_mm_ierat_state; + assign ierat_iu3_pid_d = iu_mm_ierat_tid; + + generate + if (`RS_DATA_WIDTH == 64) + begin : gen64_iu3_epn + assign ierat_iu3_epn_d = iu_mm_ierat_epn; + end + endgenerate + generate + if (`RS_DATA_WIDTH < 64) + begin : gen32_iu3_epn + assign ierat_iu3_epn_d = {1'b0, iu_mm_ierat_epn[64 - `RS_DATA_WIDTH:51]}; + end + endgenerate + assign ierat_iu4_thdid_d = ierat_iu3_thdid_q; + assign ierat_iu4_epn_d = ierat_iu3_epn_q; + assign ierat_iu4_state_d = ierat_iu3_state_q; + assign ierat_iu4_pid_d = ierat_iu3_pid_q; + assign ierat_iu5_thdid_d = ierat_iu4_thdid_q; + assign ierat_iu5_epn_d = ierat_iu4_epn_q; + assign ierat_iu5_state_d = ierat_iu4_state_q; + assign ierat_iu5_pid_d = ierat_iu4_pid_q; + assign ierat_iu3_nonspec_d = iu_mm_ierat_req_nonspec; + assign ierat_iu4_nonspec_d = ierat_iu3_nonspec_q; + assign ierat_iu5_nonspec_d = ierat_iu4_nonspec_q; + + // ierat request queue logic pointers + assign ierat_inptr_d = (ierat_inptr_q == 2'b00 & ierat_req1_valid_q == 1'b0 & ierat_iu5_valid_q == 1'b1) ? 2'b01 : + (ierat_inptr_q == 2'b00 & ierat_req2_valid_q == 1'b0 & ierat_iu5_valid_q == 1'b1) ? 2'b10 : + (ierat_inptr_q == 2'b00 & ierat_req3_valid_q == 1'b0 & ierat_iu5_valid_q == 1'b1) ? 2'b11 : + (ierat_inptr_q == 2'b01 & ierat_req2_valid_q == 1'b0 & ierat_iu5_valid_q == 1'b1) ? 2'b10 : + (ierat_inptr_q == 2'b01 & ierat_req3_valid_q == 1'b0 & ierat_iu5_valid_q == 1'b1) ? 2'b11 : + (ierat_inptr_q == 2'b01 & ierat_req0_valid_q == 1'b0 & ierat_iu5_valid_q == 1'b1) ? 2'b00 : + (ierat_inptr_q == 2'b10 & ierat_req3_valid_q == 1'b0 & ierat_iu5_valid_q == 1'b1) ? 2'b11 : + (ierat_inptr_q == 2'b10 & ierat_req0_valid_q == 1'b0 & ierat_iu5_valid_q == 1'b1) ? 2'b00 : + (ierat_inptr_q == 2'b10 & ierat_req1_valid_q == 1'b0 & ierat_iu5_valid_q == 1'b1) ? 2'b01 : + (ierat_inptr_q == 2'b11 & ierat_req0_valid_q == 1'b0 & ierat_iu5_valid_q == 1'b1) ? 2'b00 : + (ierat_inptr_q == 2'b11 & ierat_req1_valid_q == 1'b0 & ierat_iu5_valid_q == 1'b1) ? 2'b01 : + (ierat_inptr_q == 2'b11 & ierat_req2_valid_q == 1'b0 & ierat_iu5_valid_q == 1'b1) ? 2'b10 : + (ierat_req_taken == 1'b1) ? ierat_outptr_q : + ierat_inptr_q; + + assign ierat_outptr_d = (ierat_outptr_q == 2'b00 & ierat_req0_valid_q == 1'b1 & ierat_req_taken == 1'b1) ? 2'b01 : + (ierat_outptr_q == 2'b01 & ierat_req1_valid_q == 1'b1 & ierat_req_taken == 1'b1) ? 2'b10 : + (ierat_outptr_q == 2'b10 & ierat_req2_valid_q == 1'b1 & ierat_req_taken == 1'b1) ? 2'b11 : + (ierat_outptr_q == 2'b11 & ierat_req3_valid_q == 1'b1 & ierat_req_taken == 1'b1) ? 2'b00 : + (ierat_outptr_q == 2'b00 & ierat_req0_valid_q == 1'b0 & ierat_req1_valid_q == 1'b1) ? 2'b01 : + (ierat_outptr_q == 2'b00 & ierat_req0_valid_q == 1'b0 & ierat_req1_valid_q == 1'b0 & ierat_req2_valid_q == 1'b1) ? 2'b10 : + (ierat_outptr_q == 2'b00 & ierat_req0_valid_q == 1'b0 & ierat_req1_valid_q == 1'b0 & ierat_req2_valid_q == 1'b0 & ierat_req3_valid_q == 1'b1) ? 2'b11 : + (ierat_outptr_q == 2'b01 & ierat_req1_valid_q == 1'b0 & ierat_req2_valid_q == 1'b1) ? 2'b10 : + (ierat_outptr_q == 2'b01 & ierat_req1_valid_q == 1'b0 & ierat_req2_valid_q == 1'b0 & ierat_req3_valid_q == 1'b1) ? 2'b11 : + (ierat_outptr_q == 2'b01 & ierat_req1_valid_q == 1'b0 & ierat_req2_valid_q == 1'b0 & ierat_req3_valid_q == 1'b0 & ierat_req0_valid_q == 1'b1) ? 2'b00 : + (ierat_outptr_q == 2'b10 & ierat_req2_valid_q == 1'b0 & ierat_req3_valid_q == 1'b1) ? 2'b11 : + (ierat_outptr_q == 2'b10 & ierat_req2_valid_q == 1'b0 & ierat_req3_valid_q == 1'b0 & ierat_req0_valid_q == 1'b1) ? 2'b00 : + (ierat_outptr_q == 2'b10 & ierat_req2_valid_q == 1'b0 & ierat_req3_valid_q == 1'b0 & ierat_req0_valid_q == 1'b0 & ierat_req1_valid_q == 1'b1) ? 2'b01 : + (ierat_outptr_q == 2'b11 & ierat_req3_valid_q == 1'b0 & ierat_req0_valid_q == 1'b1) ? 2'b00 : + (ierat_outptr_q == 2'b11 & ierat_req3_valid_q == 1'b0 & ierat_req0_valid_q == 1'b0 & ierat_req1_valid_q == 1'b1) ? 2'b01 : + (ierat_outptr_q == 2'b11 & ierat_req3_valid_q == 1'b0 & ierat_req0_valid_q == 1'b0 & ierat_req1_valid_q == 1'b0 & ierat_req2_valid_q == 1'b1) ? 2'b10 : + ierat_outptr_q; + + assign tlb_seq_ierat_req_d = (((ierat_outptr_q == 2'b00 & ierat_req0_valid_q == 1'b1 & |(ierat_req0_thdid_q & (~(xu_mm_ierat_flush_q))) == 1'b1) | (ierat_outptr_q == 2'b01 & ierat_req1_valid_q == 1'b1 & |(ierat_req1_thdid_q & (~(xu_mm_ierat_flush_q))) == 1'b1) | (ierat_outptr_q == 2'b10 & ierat_req2_valid_q == 1'b1 & |(ierat_req2_thdid_q & (~(xu_mm_ierat_flush_q))) == 1'b1) | (ierat_outptr_q == 2'b11 & ierat_req3_valid_q == 1'b1 & |(ierat_req3_thdid_q & (~(xu_mm_ierat_flush_q))) == 1'b1))) ? 1'b1 : + 1'b0; + assign tlb_seq_ierat_req = tlb_seq_ierat_req_q; + // i-erat queue valid bit is ierat_req_valid_q + // tlb_cmp_ierat_dup_val bits 0:3 are req_tag5_match, 4 is tag5 hit_reload, 5 is stretched hit_reload, 6 is ierat iu5 stage dup + assign ierat_req0_valid_d = ((ierat_iu5_valid_q == 1'b1 & |(ierat_iu5_thdid_q & (~(ierat_iu3_flush_q)) & (~(xu_mm_ierat_flush_q))) == 1'b1 & ierat_req0_valid_q == 1'b0 & ierat_inptr_q == 2'b00)) ? 1'b1 : + ((ierat_req_taken == 1'b1 & ierat_req0_valid_q == 1'b1 & ierat_outptr_q == 2'b00)) ? 1'b0 : + ((tlb_cmp_ierat_dup_val[0] == 1'b1 & tlb_cmp_ierat_dup_val[4] == 1'b1)) ? 1'b0 : + ierat_req0_valid_q; + assign ierat_req0_nonspec_d = ((ierat_iu5_valid_q == 1'b1 & |(ierat_iu5_thdid_q & (~(ierat_iu3_flush_q)) & (~(xu_mm_ierat_flush_q))) == 1'b1 & ierat_req0_valid_q == 1'b0 & ierat_inptr_q == 2'b00)) ? ierat_iu5_nonspec_q : + ((ierat_req_taken == 1'b1 & ierat_req0_valid_q == 1'b1 & ierat_outptr_q == 2'b00)) ? 1'b0 : + ((tlb_cmp_ierat_dup_val[0] == 1'b1 & tlb_cmp_ierat_dup_val[4] == 1'b1)) ? 1'b0 : + ierat_req0_nonspec_q; + assign ierat_req0_thdid_d[0:3] = ((ierat_iu5_valid_q == 1'b1 & ierat_req0_valid_q == 1'b0 & ierat_inptr_q == 2'b00)) ? ierat_iu5_thdid_q : + ierat_req0_thdid_q[0:3]; + assign ierat_req0_epn_d = ((ierat_iu5_valid_q == 1'b1 & ierat_req0_valid_q == 1'b0 & ierat_inptr_q == 2'b00)) ? ierat_iu5_epn_q : + ierat_req0_epn_q; + assign ierat_req0_state_d = ((ierat_iu5_valid_q == 1'b1 & ierat_req0_valid_q == 1'b0 & ierat_inptr_q == 2'b00)) ? ierat_iu5_state_q : + ierat_req0_state_q; + assign ierat_req0_pid_d = ((ierat_iu5_valid_q == 1'b1 & ierat_req0_valid_q == 1'b0 & ierat_inptr_q == 2'b00)) ? ierat_iu5_pid_q : + ierat_req0_pid_q; + assign ierat_req0_dup_d[0] = 1'b0; + assign ierat_req0_dup_d[1] = ((ierat_req_taken == 1'b1 & ierat_req0_valid_q == 1'b1 & ierat_outptr_q == 2'b00)) ? 1'b0 : + ((ierat_iu5_valid_q == 1'b1 & ierat_req0_valid_q == 1'b0 & ierat_inptr_q == 2'b00)) ? tlb_cmp_ierat_dup_val[6] : + ((ierat_req0_valid_q == 1'b1 & ierat_req0_dup_q[1] == 1'b0 & tlb_cmp_ierat_dup_val[4] == 1'b0 & tlb_cmp_ierat_dup_val[5] == 1'b1)) ? tlb_cmp_ierat_dup_val[0] : + ierat_req0_dup_q[1]; + assign ierat_req1_valid_d = ((ierat_iu5_valid_q == 1'b1 & |(ierat_iu5_thdid_q & (~(ierat_iu3_flush_q)) & (~(xu_mm_ierat_flush_q))) == 1'b1 & ierat_req1_valid_q == 1'b0 & ierat_inptr_q == 2'b01)) ? 1'b1 : + ((ierat_req_taken == 1'b1 & ierat_req1_valid_q == 1'b1 & ierat_outptr_q == 2'b01)) ? 1'b0 : + ((tlb_cmp_ierat_dup_val[1] == 1'b1 & tlb_cmp_ierat_dup_val[4] == 1'b1)) ? 1'b0 : + ierat_req1_valid_q; + assign ierat_req1_nonspec_d = ((ierat_iu5_valid_q == 1'b1 & |(ierat_iu5_thdid_q & (~(ierat_iu3_flush_q)) & (~(xu_mm_ierat_flush_q))) == 1'b1 & ierat_req1_valid_q == 1'b0 & ierat_inptr_q == 2'b01)) ? ierat_iu5_nonspec_q : + ((ierat_req_taken == 1'b1 & ierat_req1_valid_q == 1'b1 & ierat_outptr_q == 2'b01)) ? 1'b0 : + ((tlb_cmp_ierat_dup_val[1] == 1'b1 & tlb_cmp_ierat_dup_val[4] == 1'b1)) ? 1'b0 : + ierat_req1_nonspec_q; + assign ierat_req1_thdid_d[0:3] = ((ierat_iu5_valid_q == 1'b1 & ierat_req1_valid_q == 1'b0 & ierat_inptr_q == 2'b01)) ? ierat_iu5_thdid_q : + ierat_req1_thdid_q[0:3]; + assign ierat_req1_epn_d = ((ierat_iu5_valid_q == 1'b1 & ierat_req1_valid_q == 1'b0 & ierat_inptr_q == 2'b01)) ? ierat_iu5_epn_q : + ierat_req1_epn_q; + assign ierat_req1_state_d = ((ierat_iu5_valid_q == 1'b1 & ierat_req1_valid_q == 1'b0 & ierat_inptr_q == 2'b01)) ? ierat_iu5_state_q : + ierat_req1_state_q; + assign ierat_req1_pid_d = ((ierat_iu5_valid_q == 1'b1 & ierat_req1_valid_q == 1'b0 & ierat_inptr_q == 2'b01)) ? ierat_iu5_pid_q : + ierat_req1_pid_q; + assign ierat_req1_dup_d[0] = 1'b0; + assign ierat_req1_dup_d[1] = ((ierat_req_taken == 1'b1 & ierat_req1_valid_q == 1'b1 & ierat_outptr_q == 2'b01)) ? 1'b0 : + ((ierat_iu5_valid_q == 1'b1 & ierat_req1_valid_q == 1'b0 & ierat_inptr_q == 2'b01)) ? tlb_cmp_ierat_dup_val[6] : + ((ierat_req1_valid_q == 1'b1 & ierat_req1_dup_q[1] == 1'b0 & tlb_cmp_ierat_dup_val[4] == 1'b0 & tlb_cmp_ierat_dup_val[5] == 1'b1)) ? tlb_cmp_ierat_dup_val[1] : + ierat_req1_dup_q[1]; + assign ierat_req2_valid_d = ((ierat_iu5_valid_q == 1'b1 & |(ierat_iu5_thdid_q & (~(ierat_iu3_flush_q)) & (~(xu_mm_ierat_flush_q))) == 1'b1 & ierat_req2_valid_q == 1'b0 & ierat_inptr_q == 2'b10)) ? 1'b1 : + ((ierat_req_taken == 1'b1 & ierat_req2_valid_q == 1'b1 & ierat_outptr_q == 2'b10)) ? 1'b0 : + ((tlb_cmp_ierat_dup_val[2] == 1'b1 & tlb_cmp_ierat_dup_val[4] == 1'b1)) ? 1'b0 : + ierat_req2_valid_q; + assign ierat_req2_nonspec_d = ((ierat_iu5_valid_q == 1'b1 & |(ierat_iu5_thdid_q & (~(ierat_iu3_flush_q)) & (~(xu_mm_ierat_flush_q))) == 1'b1 & ierat_req2_valid_q == 1'b0 & ierat_inptr_q == 2'b10)) ? ierat_iu5_nonspec_q : + ((ierat_req_taken == 1'b1 & ierat_req2_valid_q == 1'b1 & ierat_outptr_q == 2'b10)) ? 1'b0 : + ((tlb_cmp_ierat_dup_val[2] == 1'b1 & tlb_cmp_ierat_dup_val[4] == 1'b1)) ? 1'b0 : + ierat_req2_nonspec_q; + assign ierat_req2_thdid_d[0:3] = ((ierat_iu5_valid_q == 1'b1 & ierat_req2_valid_q == 1'b0 & ierat_inptr_q == 2'b10)) ? ierat_iu5_thdid_q : + ierat_req2_thdid_q[0:3]; + assign ierat_req2_epn_d = ((ierat_iu5_valid_q == 1'b1 & ierat_req2_valid_q == 1'b0 & ierat_inptr_q == 2'b10)) ? ierat_iu5_epn_q : + ierat_req2_epn_q; + assign ierat_req2_state_d = ((ierat_iu5_valid_q == 1'b1 & ierat_req2_valid_q == 1'b0 & ierat_inptr_q == 2'b10)) ? ierat_iu5_state_q : + ierat_req2_state_q; + assign ierat_req2_pid_d = ((ierat_iu5_valid_q == 1'b1 & ierat_req2_valid_q == 1'b0 & ierat_inptr_q == 2'b10)) ? ierat_iu5_pid_q : + ierat_req2_pid_q; + assign ierat_req2_dup_d[0] = 1'b0; + assign ierat_req2_dup_d[1] = ((ierat_req_taken == 1'b1 & ierat_req2_valid_q == 1'b1 & ierat_outptr_q == 2'b10)) ? 1'b0 : + ((ierat_iu5_valid_q == 1'b1 & ierat_req2_valid_q == 1'b0 & ierat_inptr_q == 2'b10)) ? tlb_cmp_ierat_dup_val[6] : + ((ierat_req2_valid_q == 1'b1 & ierat_req2_dup_q[1] == 1'b0 & tlb_cmp_ierat_dup_val[4] == 1'b0 & tlb_cmp_ierat_dup_val[5] == 1'b1)) ? tlb_cmp_ierat_dup_val[2] : + ierat_req2_dup_q[1]; + assign ierat_req3_valid_d = ((ierat_iu5_valid_q == 1'b1 & |(ierat_iu5_thdid_q & (~(ierat_iu3_flush_q)) & (~(xu_mm_ierat_flush_q))) == 1'b1 & ierat_req3_valid_q == 1'b0 & ierat_inptr_q == 2'b11)) ? 1'b1 : + ((ierat_req_taken == 1'b1 & ierat_req3_valid_q == 1'b1 & ierat_outptr_q == 2'b11)) ? 1'b0 : + ((tlb_cmp_ierat_dup_val[3] == 1'b1 & tlb_cmp_ierat_dup_val[4] == 1'b1)) ? 1'b0 : + ierat_req3_valid_q; + assign ierat_req3_nonspec_d = ((ierat_iu5_valid_q == 1'b1 & |(ierat_iu5_thdid_q & (~(ierat_iu3_flush_q)) & (~(xu_mm_ierat_flush_q))) == 1'b1 & ierat_req3_valid_q == 1'b0 & ierat_inptr_q == 2'b11)) ? ierat_iu5_nonspec_q : + ((ierat_req_taken == 1'b1 & ierat_req3_valid_q == 1'b1 & ierat_outptr_q == 2'b11)) ? 1'b0 : + ((tlb_cmp_ierat_dup_val[3] == 1'b1 & tlb_cmp_ierat_dup_val[4] == 1'b1)) ? 1'b0 : + ierat_req3_nonspec_q; + assign ierat_req3_thdid_d[0:3] = ((ierat_iu5_valid_q == 1'b1 & ierat_req3_valid_q == 1'b0 & ierat_inptr_q == 2'b11)) ? ierat_iu5_thdid_q : + ierat_req3_thdid_q[0:3]; + assign ierat_req3_epn_d = ((ierat_iu5_valid_q == 1'b1 & ierat_req3_valid_q == 1'b0 & ierat_inptr_q == 2'b11)) ? ierat_iu5_epn_q : + ierat_req3_epn_q; + assign ierat_req3_state_d = ((ierat_iu5_valid_q == 1'b1 & ierat_req3_valid_q == 1'b0 & ierat_inptr_q == 2'b11)) ? ierat_iu5_state_q : + ierat_req3_state_q; + assign ierat_req3_pid_d = ((ierat_iu5_valid_q == 1'b1 & ierat_req3_valid_q == 1'b0 & ierat_inptr_q == 2'b11)) ? ierat_iu5_pid_q : + ierat_req3_pid_q; + assign ierat_req3_dup_d[0] = 1'b0; + assign ierat_req3_dup_d[1] = ((ierat_req_taken == 1'b1 & ierat_req3_valid_q == 1'b1 & ierat_outptr_q == 2'b11)) ? 1'b0 : + ((ierat_iu5_valid_q == 1'b1 & ierat_req3_valid_q == 1'b0 & ierat_inptr_q == 2'b11)) ? tlb_cmp_ierat_dup_val[6] : + ((ierat_req3_valid_q == 1'b1 & ierat_req3_dup_q[1] == 1'b0 & tlb_cmp_ierat_dup_val[4] == 1'b0 & tlb_cmp_ierat_dup_val[5] == 1'b1)) ? tlb_cmp_ierat_dup_val[3] : + ierat_req3_dup_q[1]; +`ifdef MM_THREADS2 + assign ierat_req_pid_mux = (pid0 & {`PID_WIDTH{iu_mm_ierat_thdid[0]}}) | (pid1 & {`PID_WIDTH{iu_mm_ierat_thdid[1]}}); +`else + assign ierat_req_pid_mux = (pid0 & {`PID_WIDTH{iu_mm_ierat_thdid[0]}}); +`endif + // xu pipe for non-speculative derat flush processing + assign derat_ex4_valid_d = xu_mm_derat_req; + assign derat_ex5_valid_d = derat_ex4_valid_q; + assign derat_ex6_valid_d = derat_ex5_valid_q; + + generate + if (`RS_DATA_WIDTH == 64) + begin : gen64_ex4_epn + assign derat_ex4_epn_d = xu_mm_derat_epn; + end + endgenerate + + generate + if (`RS_DATA_WIDTH < 64) + begin : gen32_ex4_epn + assign derat_ex4_epn_d = {1'b0, xu_mm_derat_epn[64 - `RS_DATA_WIDTH:51]}; + end + endgenerate + + assign derat_ex4_thdid_d = xu_mm_derat_thdid; + assign derat_ex4_state_d = xu_mm_derat_state; + assign derat_ex4_ttype_d = xu_mm_derat_ttype; + assign derat_ex4_pid_d = xu_mm_derat_tid; + assign derat_ex4_lpid_d = xu_mm_derat_lpid; + assign derat_ex4_itag_d = lq_mm_derat_req_itag; + assign derat_ex4_emq_d = lq_mm_derat_req_emq; + assign derat_ex4_nonspec_d = lq_mm_derat_req_nonspec; + assign derat_ex5_thdid_d = derat_ex4_thdid_q; + assign derat_ex5_epn_d = derat_ex4_epn_q; + assign derat_ex5_state_d = derat_ex4_state_q; + assign derat_ex5_ttype_d = derat_ex4_ttype_q; + assign derat_ex5_pid_d = derat_ex4_pid_q; + assign derat_ex5_itag_d = derat_ex4_itag_q; + assign derat_ex5_emq_d = derat_ex4_emq_q; + assign derat_ex5_nonspec_d = derat_ex4_nonspec_q; + assign derat_ex6_thdid_d = derat_ex5_thdid_q; + assign derat_ex6_epn_d = derat_ex5_epn_q; + assign derat_ex6_state_d = derat_ex5_state_q; + assign derat_ex6_ttype_d = derat_ex5_ttype_q; + assign derat_ex6_pid_d = derat_ex5_pid_q; + assign derat_ex6_itag_d = derat_ex5_itag_q; + assign derat_ex6_emq_d = derat_ex5_emq_q; + assign derat_ex6_nonspec_d = derat_ex5_nonspec_q; + // use derat lpid for external pid ops + assign derat_ex5_lpid_d = (derat_ex4_valid_q == 1'b1 & derat_ex4_ttype_q[0] == 1'b1) ? derat_ex4_lpid_q : + lpidr; + assign derat_ex6_lpid_d = (derat_ex5_valid_q == 1'b1 & derat_ex5_ttype_q[0] == 1'b1) ? derat_ex5_lpid_q : + lpidr; + + // derat request queue logic pointers + assign derat_inptr_d = (derat_inptr_q == 2'b00 & derat_req1_valid_q == 1'b0 & derat_ex6_valid_q == 1'b1) ? 2'b01 : + (derat_inptr_q == 2'b00 & derat_req2_valid_q == 1'b0 & derat_ex6_valid_q == 1'b1) ? 2'b10 : + (derat_inptr_q == 2'b00 & derat_req3_valid_q == 1'b0 & derat_ex6_valid_q == 1'b1) ? 2'b11 : + (derat_inptr_q == 2'b01 & derat_req2_valid_q == 1'b0 & derat_ex6_valid_q == 1'b1) ? 2'b10 : + (derat_inptr_q == 2'b01 & derat_req3_valid_q == 1'b0 & derat_ex6_valid_q == 1'b1) ? 2'b11 : + (derat_inptr_q == 2'b01 & derat_req0_valid_q == 1'b0 & derat_ex6_valid_q == 1'b1) ? 2'b00 : + (derat_inptr_q == 2'b10 & derat_req3_valid_q == 1'b0 & derat_ex6_valid_q == 1'b1) ? 2'b11 : + (derat_inptr_q == 2'b10 & derat_req0_valid_q == 1'b0 & derat_ex6_valid_q == 1'b1) ? 2'b00 : + (derat_inptr_q == 2'b10 & derat_req1_valid_q == 1'b0 & derat_ex6_valid_q == 1'b1) ? 2'b01 : + (derat_inptr_q == 2'b11 & derat_req0_valid_q == 1'b0 & derat_ex6_valid_q == 1'b1) ? 2'b00 : + (derat_inptr_q == 2'b11 & derat_req1_valid_q == 1'b0 & derat_ex6_valid_q == 1'b1) ? 2'b01 : + (derat_inptr_q == 2'b11 & derat_req2_valid_q == 1'b0 & derat_ex6_valid_q == 1'b1) ? 2'b10 : + (derat_req_taken == 1'b1) ? derat_outptr_q : + derat_inptr_q; + + assign derat_outptr_d = (derat_outptr_q == 2'b00 & derat_req0_valid_q == 1'b1 & derat_req_taken == 1'b1) ? 2'b01 : + (derat_outptr_q == 2'b01 & derat_req1_valid_q == 1'b1 & derat_req_taken == 1'b1) ? 2'b10 : + (derat_outptr_q == 2'b10 & derat_req2_valid_q == 1'b1 & derat_req_taken == 1'b1) ? 2'b11 : + (derat_outptr_q == 2'b11 & derat_req3_valid_q == 1'b1 & derat_req_taken == 1'b1) ? 2'b00 : + (derat_outptr_q == 2'b00 & derat_req0_valid_q == 1'b0 & derat_req1_valid_q == 1'b1) ? 2'b01 : + (derat_outptr_q == 2'b00 & derat_req0_valid_q == 1'b0 & derat_req1_valid_q == 1'b0 & derat_req2_valid_q == 1'b1) ? 2'b10 : + (derat_outptr_q == 2'b00 & derat_req0_valid_q == 1'b0 & derat_req1_valid_q == 1'b0 & derat_req2_valid_q == 1'b0 & derat_req3_valid_q == 1'b1) ? 2'b11 : + (derat_outptr_q == 2'b01 & derat_req1_valid_q == 1'b0 & derat_req2_valid_q == 1'b1) ? 2'b10 : + (derat_outptr_q == 2'b01 & derat_req1_valid_q == 1'b0 & derat_req2_valid_q == 1'b0 & derat_req3_valid_q == 1'b1) ? 2'b11 : + (derat_outptr_q == 2'b01 & derat_req1_valid_q == 1'b0 & derat_req2_valid_q == 1'b0 & derat_req3_valid_q == 1'b0 & derat_req0_valid_q == 1'b1) ? 2'b00 : + (derat_outptr_q == 2'b10 & derat_req2_valid_q == 1'b0 & derat_req3_valid_q == 1'b1) ? 2'b11 : + (derat_outptr_q == 2'b10 & derat_req2_valid_q == 1'b0 & derat_req3_valid_q == 1'b0 & derat_req0_valid_q == 1'b1) ? 2'b00 : + (derat_outptr_q == 2'b10 & derat_req2_valid_q == 1'b0 & derat_req3_valid_q == 1'b0 & derat_req0_valid_q == 1'b0 & derat_req1_valid_q == 1'b1) ? 2'b01 : + (derat_outptr_q == 2'b11 & derat_req3_valid_q == 1'b0 & derat_req0_valid_q == 1'b1) ? 2'b00 : + (derat_outptr_q == 2'b11 & derat_req3_valid_q == 1'b0 & derat_req0_valid_q == 1'b0 & derat_req1_valid_q == 1'b1) ? 2'b01 : + (derat_outptr_q == 2'b11 & derat_req3_valid_q == 1'b0 & derat_req0_valid_q == 1'b0 & derat_req1_valid_q == 1'b0 & derat_req2_valid_q == 1'b1) ? 2'b10 : + derat_outptr_q; + + assign tlb_seq_derat_req_d = (((derat_outptr_q == 2'b00 & derat_req0_valid_q == 1'b1) | (derat_outptr_q == 2'b01 & derat_req1_valid_q == 1'b1) | (derat_outptr_q == 2'b10 & derat_req2_valid_q == 1'b1) | (derat_outptr_q == 2'b11 & derat_req3_valid_q == 1'b1))) ? 1'b1 : + 1'b0; + assign tlb_seq_derat_req = tlb_seq_derat_req_q; + // d-erat queue valid bit is derat_req_valid_q + // tlb_cmp_derat_dup_val : in std_ulogic_vector(0 to 6); -- bit 4 hit/miss pulse, 5 is stretched hit/miss, 6 is ex6 dup + assign derat_req0_valid_d = ((derat_ex6_valid_q == 1'b1 & derat_req0_valid_q == 1'b0 & derat_inptr_q == 2'b00)) ? 1'b1 : + ((derat_req_taken == 1'b1 & derat_req0_valid_q == 1'b1 & derat_outptr_q == 2'b00)) ? 1'b0 : + ((tlb_cmp_derat_dup_val[0] == 1'b1 & tlb_cmp_derat_dup_val[4] == 1'b1)) ? 1'b0 : + derat_req0_valid_q; + assign derat_req0_thdid_d[0:3] = ((derat_ex6_valid_q == 1'b1 & derat_req0_valid_q == 1'b0 & derat_inptr_q == 2'b00)) ? derat_ex6_thdid_q : + derat_req0_thdid_q[0:3]; + assign derat_req0_epn_d = ((derat_ex6_valid_q == 1'b1 & derat_req0_valid_q == 1'b0 & derat_inptr_q == 2'b00)) ? derat_ex6_epn_q : + derat_req0_epn_q; + assign derat_req0_state_d = ((derat_ex6_valid_q == 1'b1 & derat_req0_valid_q == 1'b0 & derat_inptr_q == 2'b00)) ? derat_ex6_state_q : + derat_req0_state_q; + assign derat_req0_ttype_d = ((derat_ex6_valid_q == 1'b1 & derat_req0_valid_q == 1'b0 & derat_inptr_q == 2'b00)) ? derat_ex6_ttype_q : + derat_req0_ttype_q; + assign derat_req0_pid_d = ((derat_ex6_valid_q == 1'b1 & derat_req0_valid_q == 1'b0 & derat_inptr_q == 2'b00)) ? derat_ex6_pid_q : + derat_req0_pid_q; + assign derat_req0_lpid_d = ((derat_ex6_valid_q == 1'b1 & derat_req0_valid_q == 1'b0 & derat_inptr_q == 2'b00)) ? derat_ex6_lpid_q : + derat_req0_lpid_q; + assign derat_req0_dup_d[0] = 1'b0; + assign derat_req0_dup_d[1] = ((derat_req_taken == 1'b1 & derat_req0_valid_q == 1'b1 & derat_outptr_q == 2'b00)) ? 1'b0 : + ((derat_ex6_valid_q == 1'b1 & derat_req0_valid_q == 1'b0 & derat_inptr_q == 2'b00)) ? tlb_cmp_derat_dup_val[6] : + ((derat_req0_valid_q == 1'b1 & derat_req0_dup_q[1] == 1'b0 & tlb_cmp_derat_dup_val[4] == 1'b0 & tlb_cmp_derat_dup_val[5] == 1'b1)) ? tlb_cmp_derat_dup_val[0] : + derat_req0_dup_q[1]; + assign derat_req0_itag_d = ((derat_ex6_valid_q == 1'b1 & derat_req0_valid_q == 1'b0 & derat_inptr_q == 2'b00)) ? derat_ex6_itag_q : + derat_req0_itag_q; + assign derat_req0_emq_d = ((derat_ex6_valid_q == 1'b1 & derat_req0_valid_q == 1'b0 & derat_inptr_q == 2'b00)) ? derat_ex6_emq_q : + derat_req0_emq_q; + assign derat_req0_nonspec_d = ((derat_ex6_valid_q == 1'b1 & derat_req0_valid_q == 1'b0 & derat_inptr_q == 2'b00)) ? derat_ex6_nonspec_q : + ((derat_req_taken == 1'b1 & derat_req0_valid_q == 1'b1 & derat_outptr_q == 2'b00)) ? 1'b0 : + ((tlb_cmp_derat_dup_val[0] == 1'b1 & tlb_cmp_derat_dup_val[4] == 1'b1)) ? 1'b0 : + derat_req0_nonspec_q; + assign derat_req1_valid_d = ((derat_ex6_valid_q == 1'b1 & derat_req1_valid_q == 1'b0 & derat_inptr_q == 2'b01)) ? 1'b1 : + ((derat_req_taken == 1'b1 & derat_req1_valid_q == 1'b1 & derat_outptr_q == 2'b01)) ? 1'b0 : + ((tlb_cmp_derat_dup_val[1] == 1'b1 & tlb_cmp_derat_dup_val[4] == 1'b1)) ? 1'b0 : + derat_req1_valid_q; + assign derat_req1_thdid_d[0:3] = ((derat_ex6_valid_q == 1'b1 & derat_req1_valid_q == 1'b0 & derat_inptr_q == 2'b01)) ? derat_ex6_thdid_q : + derat_req1_thdid_q[0:3]; + assign derat_req1_epn_d = ((derat_ex6_valid_q == 1'b1 & derat_req1_valid_q == 1'b0 & derat_inptr_q == 2'b01)) ? derat_ex6_epn_q : + derat_req1_epn_q; + assign derat_req1_state_d = ((derat_ex6_valid_q == 1'b1 & derat_req1_valid_q == 1'b0 & derat_inptr_q == 2'b01)) ? derat_ex6_state_q : + derat_req1_state_q; + assign derat_req1_ttype_d = ((derat_ex6_valid_q == 1'b1 & derat_req1_valid_q == 1'b0 & derat_inptr_q == 2'b01)) ? derat_ex6_ttype_q : + derat_req1_ttype_q; + assign derat_req1_pid_d = ((derat_ex6_valid_q == 1'b1 & derat_req1_valid_q == 1'b0 & derat_inptr_q == 2'b01)) ? derat_ex6_pid_q : + derat_req1_pid_q; + assign derat_req1_lpid_d = ((derat_ex6_valid_q == 1'b1 & derat_req1_valid_q == 1'b0 & derat_inptr_q == 2'b01)) ? derat_ex6_lpid_q : + derat_req1_lpid_q; + assign derat_req1_dup_d[0] = 1'b0; + assign derat_req1_dup_d[1] = ((derat_req_taken == 1'b1 & derat_req1_valid_q == 1'b1 & derat_outptr_q == 2'b01)) ? 1'b0 : + ((derat_ex6_valid_q == 1'b1 & derat_req1_valid_q == 1'b0 & derat_inptr_q == 2'b01)) ? tlb_cmp_derat_dup_val[6] : + ((derat_req1_valid_q == 1'b1 & derat_req1_dup_q[1] == 1'b0 & tlb_cmp_derat_dup_val[4] == 1'b0 & tlb_cmp_derat_dup_val[5] == 1'b1)) ? tlb_cmp_derat_dup_val[1] : + derat_req1_dup_q[1]; + assign derat_req1_itag_d = ((derat_ex6_valid_q == 1'b1 & derat_req1_valid_q == 1'b0 & derat_inptr_q == 2'b01)) ? derat_ex6_itag_q : + derat_req1_itag_q; + assign derat_req1_emq_d = ((derat_ex6_valid_q == 1'b1 & derat_req1_valid_q == 1'b0 & derat_inptr_q == 2'b01)) ? derat_ex6_emq_q : + derat_req1_emq_q; + assign derat_req1_nonspec_d = ((derat_ex6_valid_q == 1'b1 & derat_req1_valid_q == 1'b0 & derat_inptr_q == 2'b01)) ? derat_ex6_nonspec_q : + ((derat_req_taken == 1'b1 & derat_req1_valid_q == 1'b1 & derat_outptr_q == 2'b01)) ? 1'b0 : + ((tlb_cmp_derat_dup_val[1] == 1'b1 & tlb_cmp_derat_dup_val[4] == 1'b1)) ? 1'b0 : + derat_req1_nonspec_q; + assign derat_req2_valid_d = ((derat_ex6_valid_q == 1'b1 & derat_req2_valid_q == 1'b0 & derat_inptr_q == 2'b10)) ? 1'b1 : + ((derat_req_taken == 1'b1 & derat_req2_valid_q == 1'b1 & derat_outptr_q == 2'b10)) ? 1'b0 : + ((tlb_cmp_derat_dup_val[2] == 1'b1 & tlb_cmp_derat_dup_val[4] == 1'b1)) ? 1'b0 : + derat_req2_valid_q; + assign derat_req2_thdid_d[0:3] = ((derat_ex6_valid_q == 1'b1 & derat_req2_valid_q == 1'b0 & derat_inptr_q == 2'b10)) ? derat_ex6_thdid_q : + derat_req2_thdid_q[0:3]; + assign derat_req2_epn_d = ((derat_ex6_valid_q == 1'b1 & derat_req2_valid_q == 1'b0 & derat_inptr_q == 2'b10)) ? derat_ex6_epn_q : + derat_req2_epn_q; + assign derat_req2_state_d = ((derat_ex6_valid_q == 1'b1 & derat_req2_valid_q == 1'b0 & derat_inptr_q == 2'b10)) ? derat_ex6_state_q : + derat_req2_state_q; + assign derat_req2_ttype_d = ((derat_ex6_valid_q == 1'b1 & derat_req2_valid_q == 1'b0 & derat_inptr_q == 2'b10)) ? derat_ex6_ttype_q : + derat_req2_ttype_q; + assign derat_req2_pid_d = ((derat_ex6_valid_q == 1'b1 & derat_req2_valid_q == 1'b0 & derat_inptr_q == 2'b10)) ? derat_ex6_pid_q : + derat_req2_pid_q; + assign derat_req2_lpid_d = ((derat_ex6_valid_q == 1'b1 & derat_req2_valid_q == 1'b0 & derat_inptr_q == 2'b10)) ? derat_ex6_lpid_q : + derat_req2_lpid_q; + assign derat_req2_dup_d[0] = 1'b0; + assign derat_req2_dup_d[1] = ((derat_req_taken == 1'b1 & derat_req2_valid_q == 1'b1 & derat_outptr_q == 2'b10)) ? 1'b0 : + ((derat_ex6_valid_q == 1'b1 & derat_req2_valid_q == 1'b0 & derat_inptr_q == 2'b10)) ? tlb_cmp_derat_dup_val[6] : + ((derat_req2_valid_q == 1'b1 & derat_req2_dup_q[1] == 1'b0 & tlb_cmp_derat_dup_val[4] == 1'b0 & tlb_cmp_derat_dup_val[5] == 1'b1)) ? tlb_cmp_derat_dup_val[2] : + derat_req2_dup_q[1]; + assign derat_req2_itag_d = ((derat_ex6_valid_q == 1'b1 & derat_req2_valid_q == 1'b0 & derat_inptr_q == 2'b10)) ? derat_ex6_itag_q : + derat_req2_itag_q; + assign derat_req2_emq_d = ((derat_ex6_valid_q == 1'b1 & derat_req2_valid_q == 1'b0 & derat_inptr_q == 2'b10)) ? derat_ex6_emq_q : + derat_req2_emq_q; + assign derat_req2_nonspec_d = ((derat_ex6_valid_q == 1'b1 & derat_req2_valid_q == 1'b0 & derat_inptr_q == 2'b10)) ? derat_ex6_nonspec_q : + ((derat_req_taken == 1'b1 & derat_req2_valid_q == 1'b1 & derat_outptr_q == 2'b10)) ? 1'b0 : + ((tlb_cmp_derat_dup_val[2] == 1'b1 & tlb_cmp_derat_dup_val[4] == 1'b1)) ? 1'b0 : + derat_req2_nonspec_q; + assign derat_req3_valid_d = ((derat_ex6_valid_q == 1'b1 & derat_req3_valid_q == 1'b0 & derat_inptr_q == 2'b11)) ? 1'b1 : + ((derat_req_taken == 1'b1 & derat_req3_valid_q == 1'b1 & derat_outptr_q == 2'b11)) ? 1'b0 : + ((tlb_cmp_derat_dup_val[3] == 1'b1 & tlb_cmp_derat_dup_val[4] == 1'b1)) ? 1'b0 : + derat_req3_valid_q; + assign derat_req3_thdid_d[0:3] = ((derat_ex6_valid_q == 1'b1 & derat_req3_valid_q == 1'b0 & derat_inptr_q == 2'b11)) ? derat_ex6_thdid_q : + derat_req3_thdid_q[0:3]; + assign derat_req3_epn_d = ((derat_ex6_valid_q == 1'b1 & derat_req3_valid_q == 1'b0 & derat_inptr_q == 2'b11)) ? derat_ex6_epn_q : + derat_req3_epn_q; + assign derat_req3_state_d = ((derat_ex6_valid_q == 1'b1 & derat_req3_valid_q == 1'b0 & derat_inptr_q == 2'b11)) ? derat_ex6_state_q : + derat_req3_state_q; + assign derat_req3_ttype_d = ((derat_ex6_valid_q == 1'b1 & derat_req3_valid_q == 1'b0 & derat_inptr_q == 2'b11)) ? derat_ex6_ttype_q : + derat_req3_ttype_q; + assign derat_req3_pid_d = ((derat_ex6_valid_q == 1'b1 & derat_req3_valid_q == 1'b0 & derat_inptr_q == 2'b11)) ? derat_ex6_pid_q : + derat_req3_pid_q; + assign derat_req3_lpid_d = ((derat_ex6_valid_q == 1'b1 & derat_req3_valid_q == 1'b0 & derat_inptr_q == 2'b11)) ? derat_ex6_lpid_q : + derat_req3_lpid_q; + assign derat_req3_dup_d[0] = 1'b0; + assign derat_req3_dup_d[1] = ((derat_req_taken == 1'b1 & derat_req3_valid_q == 1'b1 & derat_outptr_q == 2'b11)) ? 1'b0 : + ((derat_ex6_valid_q == 1'b1 & derat_req3_valid_q == 1'b0 & derat_inptr_q == 2'b11)) ? tlb_cmp_derat_dup_val[6] : + ((derat_req3_valid_q == 1'b1 & derat_req3_dup_q[1] == 1'b0 & tlb_cmp_derat_dup_val[4] == 1'b0 & tlb_cmp_derat_dup_val[5] == 1'b1)) ? tlb_cmp_derat_dup_val[3] : + derat_req3_dup_q[1]; + assign derat_req3_itag_d = ((derat_ex6_valid_q == 1'b1 & derat_req3_valid_q == 1'b0 & derat_inptr_q == 2'b11)) ? derat_ex6_itag_q : + derat_req3_itag_q; + assign derat_req3_emq_d = ((derat_ex6_valid_q == 1'b1 & derat_req3_valid_q == 1'b0 & derat_inptr_q == 2'b11)) ? derat_ex6_emq_q : + derat_req3_emq_q; + assign derat_req3_nonspec_d = ((derat_ex6_valid_q == 1'b1 & derat_req3_valid_q == 1'b0 & derat_inptr_q == 2'b11)) ? derat_ex6_nonspec_q : + ((derat_req_taken == 1'b1 & derat_req3_valid_q == 1'b1 & derat_outptr_q == 2'b11)) ? 1'b0 : + ((tlb_cmp_derat_dup_val[3] == 1'b1 & tlb_cmp_derat_dup_val[4] == 1'b1)) ? 1'b0 : + derat_req3_nonspec_q; + //--------------------------------------------------------------------- + // output assignments + //--------------------------------------------------------------------- + assign ierat_req_epn = ((ierat_outptr_q == 2'b01)) ? ierat_req1_epn_q : + ((ierat_outptr_q == 2'b10)) ? ierat_req2_epn_q : + ((ierat_outptr_q == 2'b11)) ? ierat_req3_epn_q : + ierat_req0_epn_q; + assign ierat_req_pid = ((ierat_outptr_q == 2'b01)) ? ierat_req1_pid_q : + ((ierat_outptr_q == 2'b10)) ? ierat_req2_pid_q : + ((ierat_outptr_q == 2'b11)) ? ierat_req3_pid_q : + ierat_req0_pid_q; + assign ierat_req_state = ((ierat_outptr_q == 2'b01)) ? ierat_req1_state_q : + ((ierat_outptr_q == 2'b10)) ? ierat_req2_state_q : + ((ierat_outptr_q == 2'b11)) ? ierat_req3_state_q : + ierat_req0_state_q; + assign ierat_req_thdid = ((ierat_outptr_q == 2'b01)) ? ierat_req1_thdid_q[0:`THDID_WIDTH - 1] : + ((ierat_outptr_q == 2'b10)) ? ierat_req2_thdid_q[0:`THDID_WIDTH - 1] : + ((ierat_outptr_q == 2'b11)) ? ierat_req3_thdid_q[0:`THDID_WIDTH - 1] : + ierat_req0_thdid_q[0:`THDID_WIDTH - 1]; + assign ierat_req_dup = ((ierat_outptr_q == 2'b01)) ? ierat_req1_dup_q[0:1] : + ((ierat_outptr_q == 2'b10)) ? ierat_req2_dup_q[0:1] : + ((ierat_outptr_q == 2'b11)) ? ierat_req3_dup_q[0:1] : + ierat_req0_dup_q[0:1]; + assign ierat_req_nonspec = ((ierat_outptr_q == 2'b01)) ? ierat_req1_nonspec_q : + ((ierat_outptr_q == 2'b10)) ? ierat_req2_nonspec_q : + ((ierat_outptr_q == 2'b11)) ? ierat_req3_nonspec_q : + ierat_req0_nonspec_q; + assign derat_req_epn = ((derat_outptr_q == 2'b01)) ? derat_req1_epn_q : + ((derat_outptr_q == 2'b10)) ? derat_req2_epn_q : + ((derat_outptr_q == 2'b11)) ? derat_req3_epn_q : + derat_req0_epn_q; + assign derat_req_pid = ((derat_outptr_q == 2'b01)) ? derat_req1_pid_q : + ((derat_outptr_q == 2'b10)) ? derat_req2_pid_q : + ((derat_outptr_q == 2'b11)) ? derat_req3_pid_q : + derat_req0_pid_q; + assign derat_req_lpid = ((derat_outptr_q == 2'b01)) ? derat_req1_lpid_q : + ((derat_outptr_q == 2'b10)) ? derat_req2_lpid_q : + ((derat_outptr_q == 2'b11)) ? derat_req3_lpid_q : + derat_req0_lpid_q; + assign derat_req_state = ((derat_outptr_q == 2'b01)) ? derat_req1_state_q : + ((derat_outptr_q == 2'b10)) ? derat_req2_state_q : + ((derat_outptr_q == 2'b11)) ? derat_req3_state_q : + derat_req0_state_q; + assign derat_req_ttype = ((derat_outptr_q == 2'b01)) ? derat_req1_ttype_q : + ((derat_outptr_q == 2'b10)) ? derat_req2_ttype_q : + ((derat_outptr_q == 2'b11)) ? derat_req3_ttype_q : + derat_req0_ttype_q; + assign derat_req_thdid = ((derat_outptr_q == 2'b01)) ? derat_req1_thdid_q[0:`THDID_WIDTH - 1] : + ((derat_outptr_q == 2'b10)) ? derat_req2_thdid_q[0:`THDID_WIDTH - 1] : + ((derat_outptr_q == 2'b11)) ? derat_req3_thdid_q[0:`THDID_WIDTH - 1] : + derat_req0_thdid_q[0:`THDID_WIDTH - 1]; + assign derat_req_dup = ((derat_outptr_q == 2'b01)) ? derat_req1_dup_q[0:1] : + ((derat_outptr_q == 2'b10)) ? derat_req2_dup_q[0:1] : + ((derat_outptr_q == 2'b11)) ? derat_req3_dup_q[0:1] : + derat_req0_dup_q[0:1]; + assign derat_req_itag = ((derat_outptr_q == 2'b01)) ? derat_req1_itag_q : + ((derat_outptr_q == 2'b10)) ? derat_req2_itag_q : + ((derat_outptr_q == 2'b11)) ? derat_req3_itag_q : + derat_req0_itag_q; + assign derat_req_emq = ((derat_outptr_q == 2'b01)) ? derat_req1_emq_q : + ((derat_outptr_q == 2'b10)) ? derat_req2_emq_q : + ((derat_outptr_q == 2'b11)) ? derat_req3_emq_q : + derat_req0_emq_q; + assign derat_req_nonspec = ((derat_outptr_q == 2'b01)) ? derat_req1_nonspec_q : + ((derat_outptr_q == 2'b10)) ? derat_req2_nonspec_q : + ((derat_outptr_q == 2'b11)) ? derat_req3_nonspec_q : + derat_req0_nonspec_q; + assign ierat_req0_pid = ierat_req0_pid_q; + assign ierat_req0_gs = ierat_req0_state_q[1]; + assign ierat_req0_as = ierat_req0_state_q[2]; + assign ierat_req0_epn = ierat_req0_epn_q; + assign ierat_req0_thdid = ierat_req0_thdid_q; + assign ierat_req0_valid = ierat_req0_valid_q; + assign ierat_req0_nonspec = ierat_req0_nonspec_q; + assign ierat_req1_pid = ierat_req1_pid_q; + assign ierat_req1_gs = ierat_req1_state_q[1]; + assign ierat_req1_as = ierat_req1_state_q[2]; + assign ierat_req1_epn = ierat_req1_epn_q; + assign ierat_req1_thdid = ierat_req1_thdid_q; + assign ierat_req1_valid = ierat_req1_valid_q; + assign ierat_req1_nonspec = ierat_req1_nonspec_q; + assign ierat_req2_pid = ierat_req2_pid_q; + assign ierat_req2_gs = ierat_req2_state_q[1]; + assign ierat_req2_as = ierat_req2_state_q[2]; + assign ierat_req2_epn = ierat_req2_epn_q; + assign ierat_req2_thdid = ierat_req2_thdid_q; + assign ierat_req2_valid = ierat_req2_valid_q; + assign ierat_req2_nonspec = ierat_req2_nonspec_q; + assign ierat_req3_pid = ierat_req3_pid_q; + assign ierat_req3_gs = ierat_req3_state_q[1]; + assign ierat_req3_as = ierat_req3_state_q[2]; + assign ierat_req3_epn = ierat_req3_epn_q; + assign ierat_req3_thdid = ierat_req3_thdid_q; + assign ierat_req3_valid = ierat_req3_valid_q; + assign ierat_req3_nonspec = ierat_req3_nonspec_q; + assign ierat_iu4_pid = ierat_iu4_pid_q; + assign ierat_iu4_gs = ierat_iu4_state_q[1]; + assign ierat_iu4_as = ierat_iu4_state_q[2]; + assign ierat_iu4_epn = ierat_iu4_epn_q; + assign ierat_iu4_thdid = ierat_iu4_thdid_q; + assign ierat_iu4_valid = ierat_iu4_valid_q; + assign derat_req0_lpid = derat_req0_lpid_q; + assign derat_req0_pid = derat_req0_pid_q; + assign derat_req0_gs = derat_req0_state_q[1]; + assign derat_req0_as = derat_req0_state_q[2]; + assign derat_req0_epn = derat_req0_epn_q; + assign derat_req0_thdid = derat_req0_thdid_q; + assign derat_req0_emq = derat_req0_emq_q; + assign derat_req0_valid = derat_req0_valid_q; + assign derat_req0_nonspec = derat_req0_nonspec_q; + assign derat_req1_lpid = derat_req1_lpid_q; + assign derat_req1_pid = derat_req1_pid_q; + assign derat_req1_gs = derat_req1_state_q[1]; + assign derat_req1_as = derat_req1_state_q[2]; + assign derat_req1_epn = derat_req1_epn_q; + assign derat_req1_thdid = derat_req1_thdid_q; + assign derat_req1_emq = derat_req1_emq_q; + assign derat_req1_valid = derat_req1_valid_q; + assign derat_req1_nonspec = derat_req1_nonspec_q; + assign derat_req2_lpid = derat_req2_lpid_q; + assign derat_req2_pid = derat_req2_pid_q; + assign derat_req2_gs = derat_req2_state_q[1]; + assign derat_req2_as = derat_req2_state_q[2]; + assign derat_req2_epn = derat_req2_epn_q; + assign derat_req2_thdid = derat_req2_thdid_q; + assign derat_req2_emq = derat_req2_emq_q; + assign derat_req2_valid = derat_req2_valid_q; + assign derat_req2_nonspec = derat_req2_nonspec_q; + assign derat_req3_lpid = derat_req3_lpid_q; + assign derat_req3_pid = derat_req3_pid_q; + assign derat_req3_gs = derat_req3_state_q[1]; + assign derat_req3_as = derat_req3_state_q[2]; + assign derat_req3_epn = derat_req3_epn_q; + assign derat_req3_thdid = derat_req3_thdid_q; + assign derat_req3_emq = derat_req3_emq_q; + assign derat_req3_valid = derat_req3_valid_q; + assign derat_req3_nonspec = derat_req3_nonspec_q; + assign derat_ex5_lpid = derat_ex5_lpid_q; + assign derat_ex5_pid = derat_ex5_pid_q; + assign derat_ex5_gs = derat_ex5_state_q[1]; + assign derat_ex5_as = derat_ex5_state_q[2]; + assign derat_ex5_epn = derat_ex5_epn_q; + assign derat_ex5_thdid = derat_ex5_thdid_q; + assign derat_ex5_valid = derat_ex5_valid_q; + assign tlb_req_dbg_ierat_iu5_valid_q = ierat_iu5_valid_q; + assign tlb_req_dbg_ierat_iu5_thdid[0] = ierat_iu5_thdid_q[2] | ierat_iu5_thdid_q[3]; + assign tlb_req_dbg_ierat_iu5_thdid[1] = ierat_iu5_thdid_q[1] | ierat_iu5_thdid_q[3]; + assign tlb_req_dbg_ierat_iu5_state_q = ierat_iu5_state_q; + assign tlb_req_dbg_ierat_inptr_q = ierat_inptr_q; + assign tlb_req_dbg_ierat_outptr_q = ierat_outptr_q; + assign tlb_req_dbg_ierat_req_valid_q = {ierat_req0_valid_q, ierat_req1_valid_q, ierat_req2_valid_q, ierat_req3_valid_q}; + assign tlb_req_dbg_ierat_req_nonspec_q = {ierat_req0_nonspec_q, ierat_req1_nonspec_q, ierat_req2_nonspec_q, ierat_req3_nonspec_q}; + assign tlb_req_dbg_ierat_req_thdid[0] = ierat_req0_thdid_q[2] | ierat_req0_thdid_q[3]; + assign tlb_req_dbg_ierat_req_thdid[1] = ierat_req0_thdid_q[1] | ierat_req0_thdid_q[3]; + assign tlb_req_dbg_ierat_req_thdid[2] = ierat_req1_thdid_q[2] | ierat_req1_thdid_q[3]; + assign tlb_req_dbg_ierat_req_thdid[3] = ierat_req1_thdid_q[1] | ierat_req1_thdid_q[3]; + assign tlb_req_dbg_ierat_req_thdid[4] = ierat_req2_thdid_q[2] | ierat_req2_thdid_q[3]; + assign tlb_req_dbg_ierat_req_thdid[5] = ierat_req2_thdid_q[1] | ierat_req2_thdid_q[3]; + assign tlb_req_dbg_ierat_req_thdid[6] = ierat_req3_thdid_q[2] | ierat_req3_thdid_q[3]; + assign tlb_req_dbg_ierat_req_thdid[7] = ierat_req3_thdid_q[1] | ierat_req3_thdid_q[3]; + assign tlb_req_dbg_ierat_req_dup_q = {ierat_req0_dup_q[1], ierat_req1_dup_q[1], ierat_req2_dup_q[1], ierat_req3_dup_q[1]}; + assign tlb_req_dbg_derat_ex6_valid_q = derat_ex6_valid_q; + assign tlb_req_dbg_derat_ex6_thdid[0] = derat_ex6_thdid_q[2] | derat_ex6_thdid_q[3]; + assign tlb_req_dbg_derat_ex6_thdid[1] = derat_ex6_thdid_q[1] | derat_ex6_thdid_q[3]; + assign tlb_req_dbg_derat_ex6_state_q = derat_ex6_state_q; + assign tlb_req_dbg_derat_inptr_q = derat_inptr_q; + assign tlb_req_dbg_derat_outptr_q = derat_outptr_q; + assign tlb_req_dbg_derat_req_valid_q = {derat_req0_valid_q, derat_req1_valid_q, derat_req2_valid_q, derat_req3_valid_q}; + assign tlb_req_dbg_derat_req_thdid[0] = derat_req0_thdid_q[2] | derat_req0_thdid_q[3]; + assign tlb_req_dbg_derat_req_thdid[1] = derat_req0_thdid_q[1] | derat_req0_thdid_q[3]; + assign tlb_req_dbg_derat_req_thdid[2] = derat_req1_thdid_q[2] | derat_req1_thdid_q[3]; + assign tlb_req_dbg_derat_req_thdid[3] = derat_req1_thdid_q[1] | derat_req1_thdid_q[3]; + assign tlb_req_dbg_derat_req_thdid[4] = derat_req2_thdid_q[2] | derat_req2_thdid_q[3]; + assign tlb_req_dbg_derat_req_thdid[5] = derat_req2_thdid_q[1] | derat_req2_thdid_q[3]; + assign tlb_req_dbg_derat_req_thdid[6] = derat_req3_thdid_q[2] | derat_req3_thdid_q[3]; + assign tlb_req_dbg_derat_req_thdid[7] = derat_req3_thdid_q[1] | derat_req3_thdid_q[3]; + assign tlb_req_dbg_derat_req_ttype_q[0:1] = derat_req0_ttype_q[0:1]; + assign tlb_req_dbg_derat_req_ttype_q[2:3] = derat_req1_ttype_q[0:1]; + assign tlb_req_dbg_derat_req_ttype_q[4:5] = derat_req2_ttype_q[0:1]; + assign tlb_req_dbg_derat_req_ttype_q[6:7] = derat_req3_ttype_q[0:1]; + assign tlb_req_dbg_derat_req_dup_q = {derat_req0_dup_q[1], derat_req1_dup_q[1], derat_req2_dup_q[1], derat_req3_dup_q[1]}; + // unused spare signal assignments + assign unused_dc[0] = |(lcb_delay_lclkr_dc[1:4]); + assign unused_dc[1] = |(lcb_mpw1_dc_b[1:4]); + assign unused_dc[2] = pc_func_sl_force; + assign unused_dc[3] = pc_func_sl_thold_0_b; + assign unused_dc[4] = tc_scan_dis_dc_b; + assign unused_dc[5] = tc_scan_diag_dc; + assign unused_dc[6] = tc_lbist_en_dc; + assign unused_dc[7] = |(ierat_req_pid_mux); + assign unused_dc[8] = 1'b0; + assign unused_dc[9] = 1'b0; + assign unused_dc[10] = tlb_seq_ierat_done; + assign unused_dc[11] = tlb_seq_derat_done; + assign unused_dc[12] = mmucr2_act_override; + assign unused_dc[13] = |(xu_mm_ierat_miss_q); + assign unused_dc[14] = |(xu_ex3_flush); + assign unused_dc[15] = |(xu_mm_ex4_flush); + assign unused_dc[16] = |(xu_mm_ex5_flush); + + //--------------------------------------------------------------------- + // Latches + //--------------------------------------------------------------------- + // ierat miss request latches + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ierat_req0_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_req0_valid_offset]), + .scout(sov[ierat_req0_valid_offset]), + .din(ierat_req0_valid_d), + .dout(ierat_req0_valid_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ierat_req0_nonspec_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_req0_nonspec_offset]), + .scout(sov[ierat_req0_nonspec_offset]), + .din(ierat_req0_nonspec_d), + .dout(ierat_req0_nonspec_q) + ); + + tri_rlmreg_p #(.WIDTH(`THDID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_req0_thdid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_req0_thdid_offset:ierat_req0_thdid_offset + `THDID_WIDTH - 1]), + .scout(sov[ierat_req0_thdid_offset:ierat_req0_thdid_offset + `THDID_WIDTH - 1]), + .din(ierat_req0_thdid_d[0:`THDID_WIDTH - 1]), + .dout(ierat_req0_thdid_q[0:`THDID_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`EPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_req0_epn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_req0_epn_offset:ierat_req0_epn_offset + `EPN_WIDTH - 1]), + .scout(sov[ierat_req0_epn_offset:ierat_req0_epn_offset + `EPN_WIDTH - 1]), + .din(ierat_req0_epn_d[0:`EPN_WIDTH - 1]), + .dout(ierat_req0_epn_q[0:`EPN_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`REQ_STATE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_req0_state_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_req0_state_offset:ierat_req0_state_offset + `REQ_STATE_WIDTH - 1]), + .scout(sov[ierat_req0_state_offset:ierat_req0_state_offset + `REQ_STATE_WIDTH - 1]), + .din(ierat_req0_state_d[0:`REQ_STATE_WIDTH - 1]), + .dout(ierat_req0_state_q[0:`REQ_STATE_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_req0_pid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_req0_pid_offset:ierat_req0_pid_offset + `PID_WIDTH - 1]), + .scout(sov[ierat_req0_pid_offset:ierat_req0_pid_offset + `PID_WIDTH - 1]), + .din(ierat_req0_pid_d[0:`PID_WIDTH - 1]), + .dout(ierat_req0_pid_q[0:`PID_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ierat_req0_dup_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_req0_dup_offset:ierat_req0_dup_offset + 2 - 1]), + .scout(sov[ierat_req0_dup_offset:ierat_req0_dup_offset + 2 - 1]), + .din(ierat_req0_dup_d), + .dout(ierat_req0_dup_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ierat_req1_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_req1_valid_offset]), + .scout(sov[ierat_req1_valid_offset]), + .din(ierat_req1_valid_d), + .dout(ierat_req1_valid_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ierat_req1_nonspec_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_req1_nonspec_offset]), + .scout(sov[ierat_req1_nonspec_offset]), + .din(ierat_req1_nonspec_d), + .dout(ierat_req1_nonspec_q) + ); + + tri_rlmreg_p #(.WIDTH(`THDID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_req1_thdid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_req1_thdid_offset:ierat_req1_thdid_offset + `THDID_WIDTH - 1]), + .scout(sov[ierat_req1_thdid_offset:ierat_req1_thdid_offset + `THDID_WIDTH - 1]), + .din(ierat_req1_thdid_d[0:`THDID_WIDTH - 1]), + .dout(ierat_req1_thdid_q[0:`THDID_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`EPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_req1_epn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_req1_epn_offset:ierat_req1_epn_offset + `EPN_WIDTH - 1]), + .scout(sov[ierat_req1_epn_offset:ierat_req1_epn_offset + `EPN_WIDTH - 1]), + .din(ierat_req1_epn_d[0:`EPN_WIDTH - 1]), + .dout(ierat_req1_epn_q[0:`EPN_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`REQ_STATE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_req1_state_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_req1_state_offset:ierat_req1_state_offset + `REQ_STATE_WIDTH - 1]), + .scout(sov[ierat_req1_state_offset:ierat_req1_state_offset + `REQ_STATE_WIDTH - 1]), + .din(ierat_req1_state_d[0:`REQ_STATE_WIDTH - 1]), + .dout(ierat_req1_state_q[0:`REQ_STATE_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_req1_pid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_req1_pid_offset:ierat_req1_pid_offset + `PID_WIDTH - 1]), + .scout(sov[ierat_req1_pid_offset:ierat_req1_pid_offset + `PID_WIDTH - 1]), + .din(ierat_req1_pid_d[0:`PID_WIDTH - 1]), + .dout(ierat_req1_pid_q[0:`PID_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ierat_req1_dup_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_req1_dup_offset:ierat_req1_dup_offset + 2 - 1]), + .scout(sov[ierat_req1_dup_offset:ierat_req1_dup_offset + 2 - 1]), + .din(ierat_req1_dup_d), + .dout(ierat_req1_dup_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ierat_req2_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_req2_valid_offset]), + .scout(sov[ierat_req2_valid_offset]), + .din(ierat_req2_valid_d), + .dout(ierat_req2_valid_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ierat_req2_nonspec_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_req2_nonspec_offset]), + .scout(sov[ierat_req2_nonspec_offset]), + .din(ierat_req2_nonspec_d), + .dout(ierat_req2_nonspec_q) + ); + + tri_rlmreg_p #(.WIDTH(`THDID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_req2_thdid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_req2_thdid_offset:ierat_req2_thdid_offset + `THDID_WIDTH - 1]), + .scout(sov[ierat_req2_thdid_offset:ierat_req2_thdid_offset + `THDID_WIDTH - 1]), + .din(ierat_req2_thdid_d[0:`THDID_WIDTH - 1]), + .dout(ierat_req2_thdid_q[0:`THDID_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`EPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_req2_epn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_req2_epn_offset:ierat_req2_epn_offset + `EPN_WIDTH - 1]), + .scout(sov[ierat_req2_epn_offset:ierat_req2_epn_offset + `EPN_WIDTH - 1]), + .din(ierat_req2_epn_d[0:`EPN_WIDTH - 1]), + .dout(ierat_req2_epn_q[0:`EPN_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`REQ_STATE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_req2_state_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_req2_state_offset:ierat_req2_state_offset + `REQ_STATE_WIDTH - 1]), + .scout(sov[ierat_req2_state_offset:ierat_req2_state_offset + `REQ_STATE_WIDTH - 1]), + .din(ierat_req2_state_d[0:`REQ_STATE_WIDTH - 1]), + .dout(ierat_req2_state_q[0:`REQ_STATE_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_req2_pid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_req2_pid_offset:ierat_req2_pid_offset + `PID_WIDTH - 1]), + .scout(sov[ierat_req2_pid_offset:ierat_req2_pid_offset + `PID_WIDTH - 1]), + .din(ierat_req2_pid_d[0:`PID_WIDTH - 1]), + .dout(ierat_req2_pid_q[0:`PID_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ierat_req2_dup_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_req2_dup_offset:ierat_req2_dup_offset + 2 - 1]), + .scout(sov[ierat_req2_dup_offset:ierat_req2_dup_offset + 2 - 1]), + .din(ierat_req2_dup_d), + .dout(ierat_req2_dup_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ierat_req3_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_req3_valid_offset]), + .scout(sov[ierat_req3_valid_offset]), + .din(ierat_req3_valid_d), + .dout(ierat_req3_valid_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ierat_req3_nonspec_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_req3_nonspec_offset]), + .scout(sov[ierat_req3_nonspec_offset]), + .din(ierat_req3_nonspec_d), + .dout(ierat_req3_nonspec_q) + ); + + tri_rlmreg_p #(.WIDTH(`THDID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_req3_thdid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_req3_thdid_offset:ierat_req3_thdid_offset + `THDID_WIDTH - 1]), + .scout(sov[ierat_req3_thdid_offset:ierat_req3_thdid_offset + `THDID_WIDTH - 1]), + .din(ierat_req3_thdid_d[0:`THDID_WIDTH - 1]), + .dout(ierat_req3_thdid_q[0:`THDID_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`EPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_req3_epn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_req3_epn_offset:ierat_req3_epn_offset + `EPN_WIDTH - 1]), + .scout(sov[ierat_req3_epn_offset:ierat_req3_epn_offset + `EPN_WIDTH - 1]), + .din(ierat_req3_epn_d[0:`EPN_WIDTH - 1]), + .dout(ierat_req3_epn_q[0:`EPN_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`REQ_STATE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_req3_state_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_req3_state_offset:ierat_req3_state_offset + `REQ_STATE_WIDTH - 1]), + .scout(sov[ierat_req3_state_offset:ierat_req3_state_offset + `REQ_STATE_WIDTH - 1]), + .din(ierat_req3_state_d[0:`REQ_STATE_WIDTH - 1]), + .dout(ierat_req3_state_q[0:`REQ_STATE_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_req3_pid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_req3_pid_offset:ierat_req3_pid_offset + `PID_WIDTH - 1]), + .scout(sov[ierat_req3_pid_offset:ierat_req3_pid_offset + `PID_WIDTH - 1]), + .din(ierat_req3_pid_d[0:`PID_WIDTH - 1]), + .dout(ierat_req3_pid_q[0:`PID_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ierat_req3_dup_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_req3_dup_offset:ierat_req3_dup_offset + 2 - 1]), + .scout(sov[ierat_req3_dup_offset:ierat_req3_dup_offset + 2 - 1]), + .din(ierat_req3_dup_d), + .dout(ierat_req3_dup_q) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ierat_inptr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_inptr_offset:ierat_inptr_offset + 2 - 1]), + .scout(sov[ierat_inptr_offset:ierat_inptr_offset + 2 - 1]), + .din(ierat_inptr_d), + .dout(ierat_inptr_q) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ierat_outptr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_outptr_offset:ierat_outptr_offset + 2 - 1]), + .scout(sov[ierat_outptr_offset:ierat_outptr_offset + 2 - 1]), + .din(ierat_outptr_d), + .dout(ierat_outptr_q) + ); + + tri_rlmreg_p #(.WIDTH(`THDID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_iu3_flush_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_iu3_flush_offset:ierat_iu3_flush_offset + `THDID_WIDTH - 1]), + .scout(sov[ierat_iu3_flush_offset:ierat_iu3_flush_offset + `THDID_WIDTH - 1]), + .din(ierat_iu3_flush_d), + .dout(ierat_iu3_flush_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_seq_ierat_req_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[tlb_seq_ierat_req_offset]), + .scout(sov[tlb_seq_ierat_req_offset]), + .din(tlb_seq_ierat_req_d), + .dout(tlb_seq_ierat_req_q) + ); + + tri_rlmreg_p #(.WIDTH(`THDID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) xu_mm_ierat_flush_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[xu_mm_ierat_flush_offset:xu_mm_ierat_flush_offset + `THDID_WIDTH - 1]), + .scout(sov[xu_mm_ierat_flush_offset:xu_mm_ierat_flush_offset + `THDID_WIDTH - 1]), + .din(xu_mm_ierat_flush_d), + .dout(xu_mm_ierat_flush_q) + ); + + tri_rlmreg_p #(.WIDTH(`THDID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) xu_mm_ierat_miss_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[xu_mm_ierat_miss_offset:xu_mm_ierat_miss_offset + `THDID_WIDTH - 1]), + .scout(sov[xu_mm_ierat_miss_offset:xu_mm_ierat_miss_offset + `THDID_WIDTH - 1]), + .din(xu_mm_ierat_miss_d), + .dout(xu_mm_ierat_miss_q) + ); + // ierat miss request latches + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ierat_iu3_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_iu3_valid_offset]), + .scout(sov[ierat_iu3_valid_offset]), + .din(ierat_iu3_valid_d), + .dout(ierat_iu3_valid_q) + ); + + tri_rlmreg_p #(.WIDTH(`THDID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_iu3_thdid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_iu3_thdid_offset:ierat_iu3_thdid_offset + `THDID_WIDTH - 1]), + .scout(sov[ierat_iu3_thdid_offset:ierat_iu3_thdid_offset + `THDID_WIDTH - 1]), + .din(ierat_iu3_thdid_d[0:`THDID_WIDTH - 1]), + .dout(ierat_iu3_thdid_q[0:`THDID_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`EPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_iu3_epn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_iu3_epn_offset:ierat_iu3_epn_offset + `EPN_WIDTH - 1]), + .scout(sov[ierat_iu3_epn_offset:ierat_iu3_epn_offset + `EPN_WIDTH - 1]), + .din(ierat_iu3_epn_d[0:`EPN_WIDTH - 1]), + .dout(ierat_iu3_epn_q[0:`EPN_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`REQ_STATE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_iu3_state_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_iu3_state_offset:ierat_iu3_state_offset + `REQ_STATE_WIDTH - 1]), + .scout(sov[ierat_iu3_state_offset:ierat_iu3_state_offset + `REQ_STATE_WIDTH - 1]), + .din(ierat_iu3_state_d[0:`REQ_STATE_WIDTH - 1]), + .dout(ierat_iu3_state_q[0:`REQ_STATE_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_iu3_pid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_iu3_pid_offset:ierat_iu3_pid_offset + `PID_WIDTH - 1]), + .scout(sov[ierat_iu3_pid_offset:ierat_iu3_pid_offset + `PID_WIDTH - 1]), + .din(ierat_iu3_pid_d[0:`PID_WIDTH - 1]), + .dout(ierat_iu3_pid_q[0:`PID_WIDTH - 1]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ierat_iu3_nonspec_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_iu3_nonspec_offset]), + .scout(sov[ierat_iu3_nonspec_offset]), + .din(ierat_iu3_nonspec_d), + .dout(ierat_iu3_nonspec_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ierat_iu4_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_iu4_valid_offset]), + .scout(sov[ierat_iu4_valid_offset]), + .din(ierat_iu4_valid_d), + .dout(ierat_iu4_valid_q) + ); + + tri_rlmreg_p #(.WIDTH(`THDID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_iu4_thdid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_iu4_thdid_offset:ierat_iu4_thdid_offset + `THDID_WIDTH - 1]), + .scout(sov[ierat_iu4_thdid_offset:ierat_iu4_thdid_offset + `THDID_WIDTH - 1]), + .din(ierat_iu4_thdid_d[0:`THDID_WIDTH - 1]), + .dout(ierat_iu4_thdid_q[0:`THDID_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`EPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_iu4_epn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_iu4_epn_offset:ierat_iu4_epn_offset + `EPN_WIDTH - 1]), + .scout(sov[ierat_iu4_epn_offset:ierat_iu4_epn_offset + `EPN_WIDTH - 1]), + .din(ierat_iu4_epn_d[0:`EPN_WIDTH - 1]), + .dout(ierat_iu4_epn_q[0:`EPN_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`REQ_STATE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_iu4_state_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_iu4_state_offset:ierat_iu4_state_offset + `REQ_STATE_WIDTH - 1]), + .scout(sov[ierat_iu4_state_offset:ierat_iu4_state_offset + `REQ_STATE_WIDTH - 1]), + .din(ierat_iu4_state_d[0:`REQ_STATE_WIDTH - 1]), + .dout(ierat_iu4_state_q[0:`REQ_STATE_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_iu4_pid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_iu4_pid_offset:ierat_iu4_pid_offset + `PID_WIDTH - 1]), + .scout(sov[ierat_iu4_pid_offset:ierat_iu4_pid_offset + `PID_WIDTH - 1]), + .din(ierat_iu4_pid_d[0:`PID_WIDTH - 1]), + .dout(ierat_iu4_pid_q[0:`PID_WIDTH - 1]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ierat_iu4_nonspec_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_iu4_nonspec_offset]), + .scout(sov[ierat_iu4_nonspec_offset]), + .din(ierat_iu4_nonspec_d), + .dout(ierat_iu4_nonspec_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ierat_iu5_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_iu5_valid_offset]), + .scout(sov[ierat_iu5_valid_offset]), + .din(ierat_iu5_valid_d), + .dout(ierat_iu5_valid_q) + ); + + tri_rlmreg_p #(.WIDTH(`THDID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_iu5_thdid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_iu5_thdid_offset:ierat_iu5_thdid_offset + `THDID_WIDTH - 1]), + .scout(sov[ierat_iu5_thdid_offset:ierat_iu5_thdid_offset + `THDID_WIDTH - 1]), + .din(ierat_iu5_thdid_d[0:`THDID_WIDTH - 1]), + .dout(ierat_iu5_thdid_q[0:`THDID_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`EPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_iu5_epn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_iu5_epn_offset:ierat_iu5_epn_offset + `EPN_WIDTH - 1]), + .scout(sov[ierat_iu5_epn_offset:ierat_iu5_epn_offset + `EPN_WIDTH - 1]), + .din(ierat_iu5_epn_d[0:`EPN_WIDTH - 1]), + .dout(ierat_iu5_epn_q[0:`EPN_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`REQ_STATE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_iu5_state_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_iu5_state_offset:ierat_iu5_state_offset + `REQ_STATE_WIDTH - 1]), + .scout(sov[ierat_iu5_state_offset:ierat_iu5_state_offset + `REQ_STATE_WIDTH - 1]), + .din(ierat_iu5_state_d[0:`REQ_STATE_WIDTH - 1]), + .dout(ierat_iu5_state_q[0:`REQ_STATE_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_iu5_pid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_iu5_pid_offset:ierat_iu5_pid_offset + `PID_WIDTH - 1]), + .scout(sov[ierat_iu5_pid_offset:ierat_iu5_pid_offset + `PID_WIDTH - 1]), + .din(ierat_iu5_pid_d[0:`PID_WIDTH - 1]), + .dout(ierat_iu5_pid_q[0:`PID_WIDTH - 1]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ierat_iu5_nonspec_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[ierat_iu5_nonspec_offset]), + .scout(sov[ierat_iu5_nonspec_offset]), + .din(ierat_iu5_nonspec_d), + .dout(ierat_iu5_nonspec_q) + ); + // derat miss request latches + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) derat_req0_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_req0_valid_offset]), + .scout(sov[derat_req0_valid_offset]), + .din(derat_req0_valid_d), + .dout(derat_req0_valid_q) + ); + + tri_rlmreg_p #(.WIDTH(`THDID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_req0_thdid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_req0_thdid_offset:derat_req0_thdid_offset + `THDID_WIDTH - 1]), + .scout(sov[derat_req0_thdid_offset:derat_req0_thdid_offset + `THDID_WIDTH - 1]), + .din(derat_req0_thdid_d[0:`THDID_WIDTH - 1]), + .dout(derat_req0_thdid_q[0:`THDID_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`EPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_req0_epn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_req0_epn_offset:derat_req0_epn_offset + `EPN_WIDTH - 1]), + .scout(sov[derat_req0_epn_offset:derat_req0_epn_offset + `EPN_WIDTH - 1]), + .din(derat_req0_epn_d[0:`EPN_WIDTH - 1]), + .dout(derat_req0_epn_q[0:`EPN_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`REQ_STATE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_req0_state_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_req0_state_offset:derat_req0_state_offset + `REQ_STATE_WIDTH - 1]), + .scout(sov[derat_req0_state_offset:derat_req0_state_offset + `REQ_STATE_WIDTH - 1]), + .din(derat_req0_state_d[0:`REQ_STATE_WIDTH - 1]), + .dout(derat_req0_state_q[0:`REQ_STATE_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) derat_req0_ttype_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_req0_ttype_offset:derat_req0_ttype_offset + 2 - 1]), + .scout(sov[derat_req0_ttype_offset:derat_req0_ttype_offset + 2 - 1]), + .din(derat_req0_ttype_d), + .dout(derat_req0_ttype_q) + ); + + tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_req0_pid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_req0_pid_offset:derat_req0_pid_offset + `PID_WIDTH - 1]), + .scout(sov[derat_req0_pid_offset:derat_req0_pid_offset + `PID_WIDTH - 1]), + .din(derat_req0_pid_d[0:`PID_WIDTH - 1]), + .dout(derat_req0_pid_q[0:`PID_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_req0_lpid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_req0_lpid_offset:derat_req0_lpid_offset + `LPID_WIDTH - 1]), + .scout(sov[derat_req0_lpid_offset:derat_req0_lpid_offset + `LPID_WIDTH - 1]), + .din(derat_req0_lpid_d[0:`LPID_WIDTH - 1]), + .dout(derat_req0_lpid_q[0:`LPID_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) derat_req0_dup_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_req0_dup_offset:derat_req0_dup_offset + 2 - 1]), + .scout(sov[derat_req0_dup_offset:derat_req0_dup_offset + 2 - 1]), + .din(derat_req0_dup_d), + .dout(derat_req0_dup_q) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) derat_req0_itag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_req0_itag_offset:derat_req0_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[derat_req0_itag_offset:derat_req0_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(derat_req0_itag_d), + .dout(derat_req0_itag_q) + ); + + tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) derat_req0_emq_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_req0_emq_offset:derat_req0_emq_offset + `EMQ_ENTRIES - 1]), + .scout(sov[derat_req0_emq_offset:derat_req0_emq_offset + `EMQ_ENTRIES - 1]), + .din(derat_req0_emq_d), + .dout(derat_req0_emq_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) derat_req0_nonspec_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_req0_nonspec_offset]), + .scout(sov[derat_req0_nonspec_offset]), + .din(derat_req0_nonspec_d), + .dout(derat_req0_nonspec_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) derat_req1_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_req1_valid_offset]), + .scout(sov[derat_req1_valid_offset]), + .din(derat_req1_valid_d), + .dout(derat_req1_valid_q) + ); + + tri_rlmreg_p #(.WIDTH(`THDID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_req1_thdid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_req1_thdid_offset:derat_req1_thdid_offset + `THDID_WIDTH - 1]), + .scout(sov[derat_req1_thdid_offset:derat_req1_thdid_offset + `THDID_WIDTH - 1]), + .din(derat_req1_thdid_d[0:`THDID_WIDTH - 1]), + .dout(derat_req1_thdid_q[0:`THDID_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`EPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_req1_epn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_req1_epn_offset:derat_req1_epn_offset + `EPN_WIDTH - 1]), + .scout(sov[derat_req1_epn_offset:derat_req1_epn_offset + `EPN_WIDTH - 1]), + .din(derat_req1_epn_d[0:`EPN_WIDTH - 1]), + .dout(derat_req1_epn_q[0:`EPN_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`REQ_STATE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_req1_state_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_req1_state_offset:derat_req1_state_offset + `REQ_STATE_WIDTH - 1]), + .scout(sov[derat_req1_state_offset:derat_req1_state_offset + `REQ_STATE_WIDTH - 1]), + .din(derat_req1_state_d[0:`REQ_STATE_WIDTH - 1]), + .dout(derat_req1_state_q[0:`REQ_STATE_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) derat_req1_ttype_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_req1_ttype_offset:derat_req1_ttype_offset + 2 - 1]), + .scout(sov[derat_req1_ttype_offset:derat_req1_ttype_offset + 2 - 1]), + .din(derat_req1_ttype_d), + .dout(derat_req1_ttype_q) + ); + + tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_req1_pid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_req1_pid_offset:derat_req1_pid_offset + `PID_WIDTH - 1]), + .scout(sov[derat_req1_pid_offset:derat_req1_pid_offset + `PID_WIDTH - 1]), + .din(derat_req1_pid_d[0:`PID_WIDTH - 1]), + .dout(derat_req1_pid_q[0:`PID_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_req1_lpid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_req1_lpid_offset:derat_req1_lpid_offset + `LPID_WIDTH - 1]), + .scout(sov[derat_req1_lpid_offset:derat_req1_lpid_offset + `LPID_WIDTH - 1]), + .din(derat_req1_lpid_d[0:`LPID_WIDTH - 1]), + .dout(derat_req1_lpid_q[0:`LPID_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) derat_req1_dup_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_req1_dup_offset:derat_req1_dup_offset + 2 - 1]), + .scout(sov[derat_req1_dup_offset:derat_req1_dup_offset + 2 - 1]), + .din(derat_req1_dup_d), + .dout(derat_req1_dup_q) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) derat_req1_itag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_req1_itag_offset:derat_req1_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[derat_req1_itag_offset:derat_req1_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(derat_req1_itag_d), + .dout(derat_req1_itag_q) + ); + + tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) derat_req1_emq_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_req1_emq_offset:derat_req1_emq_offset + `EMQ_ENTRIES - 1]), + .scout(sov[derat_req1_emq_offset:derat_req1_emq_offset + `EMQ_ENTRIES - 1]), + .din(derat_req1_emq_d), + .dout(derat_req1_emq_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) derat_req1_nonspec_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_req1_nonspec_offset]), + .scout(sov[derat_req1_nonspec_offset]), + .din(derat_req1_nonspec_d), + .dout(derat_req1_nonspec_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) derat_req2_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_req2_valid_offset]), + .scout(sov[derat_req2_valid_offset]), + .din(derat_req2_valid_d), + .dout(derat_req2_valid_q) + ); + + tri_rlmreg_p #(.WIDTH(`THDID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_req2_thdid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_req2_thdid_offset:derat_req2_thdid_offset + `THDID_WIDTH - 1]), + .scout(sov[derat_req2_thdid_offset:derat_req2_thdid_offset + `THDID_WIDTH - 1]), + .din(derat_req2_thdid_d[0:`THDID_WIDTH - 1]), + .dout(derat_req2_thdid_q[0:`THDID_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`EPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_req2_epn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_req2_epn_offset:derat_req2_epn_offset + `EPN_WIDTH - 1]), + .scout(sov[derat_req2_epn_offset:derat_req2_epn_offset + `EPN_WIDTH - 1]), + .din(derat_req2_epn_d[0:`EPN_WIDTH - 1]), + .dout(derat_req2_epn_q[0:`EPN_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`REQ_STATE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_req2_state_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_req2_state_offset:derat_req2_state_offset + `REQ_STATE_WIDTH - 1]), + .scout(sov[derat_req2_state_offset:derat_req2_state_offset + `REQ_STATE_WIDTH - 1]), + .din(derat_req2_state_d[0:`REQ_STATE_WIDTH - 1]), + .dout(derat_req2_state_q[0:`REQ_STATE_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) derat_req2_ttype_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_req2_ttype_offset:derat_req2_ttype_offset + 2 - 1]), + .scout(sov[derat_req2_ttype_offset:derat_req2_ttype_offset + 2 - 1]), + .din(derat_req2_ttype_d), + .dout(derat_req2_ttype_q) + ); + + tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_req2_pid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_req2_pid_offset:derat_req2_pid_offset + `PID_WIDTH - 1]), + .scout(sov[derat_req2_pid_offset:derat_req2_pid_offset + `PID_WIDTH - 1]), + .din(derat_req2_pid_d[0:`PID_WIDTH - 1]), + .dout(derat_req2_pid_q[0:`PID_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_req2_lpid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_req2_lpid_offset:derat_req2_lpid_offset + `LPID_WIDTH - 1]), + .scout(sov[derat_req2_lpid_offset:derat_req2_lpid_offset + `LPID_WIDTH - 1]), + .din(derat_req2_lpid_d[0:`LPID_WIDTH - 1]), + .dout(derat_req2_lpid_q[0:`LPID_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) derat_req2_dup_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_req2_dup_offset:derat_req2_dup_offset + 2 - 1]), + .scout(sov[derat_req2_dup_offset:derat_req2_dup_offset + 2 - 1]), + .din(derat_req2_dup_d), + .dout(derat_req2_dup_q) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) derat_req2_itag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_req2_itag_offset:derat_req2_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[derat_req2_itag_offset:derat_req2_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(derat_req2_itag_d), + .dout(derat_req2_itag_q) + ); + + tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) derat_req2_emq_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_req2_emq_offset:derat_req2_emq_offset + `EMQ_ENTRIES - 1]), + .scout(sov[derat_req2_emq_offset:derat_req2_emq_offset + `EMQ_ENTRIES - 1]), + .din(derat_req2_emq_d), + .dout(derat_req2_emq_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) derat_req2_nonspec_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_req2_nonspec_offset]), + .scout(sov[derat_req2_nonspec_offset]), + .din(derat_req2_nonspec_d), + .dout(derat_req2_nonspec_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) derat_req3_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_req3_valid_offset]), + .scout(sov[derat_req3_valid_offset]), + .din(derat_req3_valid_d), + .dout(derat_req3_valid_q) + ); + + tri_rlmreg_p #(.WIDTH(`THDID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_req3_thdid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_req3_thdid_offset:derat_req3_thdid_offset + `THDID_WIDTH - 1]), + .scout(sov[derat_req3_thdid_offset:derat_req3_thdid_offset + `THDID_WIDTH - 1]), + .din(derat_req3_thdid_d[0:`THDID_WIDTH - 1]), + .dout(derat_req3_thdid_q[0:`THDID_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`EPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_req3_epn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_req3_epn_offset:derat_req3_epn_offset + `EPN_WIDTH - 1]), + .scout(sov[derat_req3_epn_offset:derat_req3_epn_offset + `EPN_WIDTH - 1]), + .din(derat_req3_epn_d[0:`EPN_WIDTH - 1]), + .dout(derat_req3_epn_q[0:`EPN_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`REQ_STATE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_req3_state_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_req3_state_offset:derat_req3_state_offset + `REQ_STATE_WIDTH - 1]), + .scout(sov[derat_req3_state_offset:derat_req3_state_offset + `REQ_STATE_WIDTH - 1]), + .din(derat_req3_state_d[0:`REQ_STATE_WIDTH - 1]), + .dout(derat_req3_state_q[0:`REQ_STATE_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) derat_req3_ttype_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_req3_ttype_offset:derat_req3_ttype_offset + 2 - 1]), + .scout(sov[derat_req3_ttype_offset:derat_req3_ttype_offset + 2 - 1]), + .din(derat_req3_ttype_d), + .dout(derat_req3_ttype_q) + ); + + tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_req3_pid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_req3_pid_offset:derat_req3_pid_offset + `PID_WIDTH - 1]), + .scout(sov[derat_req3_pid_offset:derat_req3_pid_offset + `PID_WIDTH - 1]), + .din(derat_req3_pid_d[0:`PID_WIDTH - 1]), + .dout(derat_req3_pid_q[0:`PID_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_req3_lpid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_req3_lpid_offset:derat_req3_lpid_offset + `LPID_WIDTH - 1]), + .scout(sov[derat_req3_lpid_offset:derat_req3_lpid_offset + `LPID_WIDTH - 1]), + .din(derat_req3_lpid_d[0:`LPID_WIDTH - 1]), + .dout(derat_req3_lpid_q[0:`LPID_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) derat_req3_dup_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_req3_dup_offset:derat_req3_dup_offset + 2 - 1]), + .scout(sov[derat_req3_dup_offset:derat_req3_dup_offset + 2 - 1]), + .din(derat_req3_dup_d), + .dout(derat_req3_dup_q) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) derat_req3_itag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_req3_itag_offset:derat_req3_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[derat_req3_itag_offset:derat_req3_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(derat_req3_itag_d), + .dout(derat_req3_itag_q) + ); + + tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) derat_req3_emq_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_req3_emq_offset:derat_req3_emq_offset + `EMQ_ENTRIES - 1]), + .scout(sov[derat_req3_emq_offset:derat_req3_emq_offset + `EMQ_ENTRIES - 1]), + .din(derat_req3_emq_d), + .dout(derat_req3_emq_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) derat_req3_nonspec_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_req3_nonspec_offset]), + .scout(sov[derat_req3_nonspec_offset]), + .din(derat_req3_nonspec_d), + .dout(derat_req3_nonspec_q) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) derat_inptr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_inptr_offset:derat_inptr_offset + 2 - 1]), + .scout(sov[derat_inptr_offset:derat_inptr_offset + 2 - 1]), + .din(derat_inptr_d), + .dout(derat_inptr_q) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) derat_outptr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_outptr_offset:derat_outptr_offset + 2 - 1]), + .scout(sov[derat_outptr_offset:derat_outptr_offset + 2 - 1]), + .din(derat_outptr_d), + .dout(derat_outptr_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_seq_derat_req_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[tlb_seq_derat_req_offset]), + .scout(sov[tlb_seq_derat_req_offset]), + .din(tlb_seq_derat_req_d), + .dout(tlb_seq_derat_req_q) + ); + // derat miss request latches + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) derat_ex4_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_ex4_valid_offset]), + .scout(sov[derat_ex4_valid_offset]), + .din(derat_ex4_valid_d), + .dout(derat_ex4_valid_q) + ); + + tri_rlmreg_p #(.WIDTH(`THDID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_ex4_thdid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_ex4_thdid_offset:derat_ex4_thdid_offset + `THDID_WIDTH - 1]), + .scout(sov[derat_ex4_thdid_offset:derat_ex4_thdid_offset + `THDID_WIDTH - 1]), + .din(derat_ex4_thdid_d[0:`THDID_WIDTH - 1]), + .dout(derat_ex4_thdid_q[0:`THDID_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`EPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_ex4_epn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_ex4_epn_offset:derat_ex4_epn_offset + `EPN_WIDTH - 1]), + .scout(sov[derat_ex4_epn_offset:derat_ex4_epn_offset + `EPN_WIDTH - 1]), + .din(derat_ex4_epn_d[0:`EPN_WIDTH - 1]), + .dout(derat_ex4_epn_q[0:`EPN_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`REQ_STATE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_ex4_state_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_ex4_state_offset:derat_ex4_state_offset + `REQ_STATE_WIDTH - 1]), + .scout(sov[derat_ex4_state_offset:derat_ex4_state_offset + `REQ_STATE_WIDTH - 1]), + .din(derat_ex4_state_d[0:`REQ_STATE_WIDTH - 1]), + .dout(derat_ex4_state_q[0:`REQ_STATE_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) derat_ex4_ttype_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_ex4_ttype_offset:derat_ex4_ttype_offset + 2 - 1]), + .scout(sov[derat_ex4_ttype_offset:derat_ex4_ttype_offset + 2 - 1]), + .din(derat_ex4_ttype_d), + .dout(derat_ex4_ttype_q) + ); + + tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_ex4_pid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_ex4_pid_offset:derat_ex4_pid_offset + `PID_WIDTH - 1]), + .scout(sov[derat_ex4_pid_offset:derat_ex4_pid_offset + `PID_WIDTH - 1]), + .din(derat_ex4_pid_d[0:`PID_WIDTH - 1]), + .dout(derat_ex4_pid_q[0:`PID_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_ex4_lpid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_ex4_lpid_offset:derat_ex4_lpid_offset + `LPID_WIDTH - 1]), + .scout(sov[derat_ex4_lpid_offset:derat_ex4_lpid_offset + `LPID_WIDTH - 1]), + .din(derat_ex4_lpid_d[0:`LPID_WIDTH - 1]), + .dout(derat_ex4_lpid_q[0:`LPID_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) derat_ex4_itag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_ex4_itag_offset:derat_ex4_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[derat_ex4_itag_offset:derat_ex4_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(derat_ex4_itag_d), + .dout(derat_ex4_itag_q) + ); + + tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) derat_ex4_emq_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_ex4_emq_offset:derat_ex4_emq_offset + `EMQ_ENTRIES - 1]), + .scout(sov[derat_ex4_emq_offset:derat_ex4_emq_offset + `EMQ_ENTRIES - 1]), + .din(derat_ex4_emq_d), + .dout(derat_ex4_emq_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) derat_ex4_nonspec_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_ex4_nonspec_offset]), + .scout(sov[derat_ex4_nonspec_offset]), + .din(derat_ex4_nonspec_d), + .dout(derat_ex4_nonspec_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) derat_ex5_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_ex5_valid_offset]), + .scout(sov[derat_ex5_valid_offset]), + .din(derat_ex5_valid_d), + .dout(derat_ex5_valid_q) + ); + + tri_rlmreg_p #(.WIDTH(`THDID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_ex5_thdid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_ex5_thdid_offset:derat_ex5_thdid_offset + `THDID_WIDTH - 1]), + .scout(sov[derat_ex5_thdid_offset:derat_ex5_thdid_offset + `THDID_WIDTH - 1]), + .din(derat_ex5_thdid_d[0:`THDID_WIDTH - 1]), + .dout(derat_ex5_thdid_q[0:`THDID_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`EPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_ex5_epn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_ex5_epn_offset:derat_ex5_epn_offset + `EPN_WIDTH - 1]), + .scout(sov[derat_ex5_epn_offset:derat_ex5_epn_offset + `EPN_WIDTH - 1]), + .din(derat_ex5_epn_d[0:`EPN_WIDTH - 1]), + .dout(derat_ex5_epn_q[0:`EPN_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`REQ_STATE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_ex5_state_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_ex5_state_offset:derat_ex5_state_offset + `REQ_STATE_WIDTH - 1]), + .scout(sov[derat_ex5_state_offset:derat_ex5_state_offset + `REQ_STATE_WIDTH - 1]), + .din(derat_ex5_state_d[0:`REQ_STATE_WIDTH - 1]), + .dout(derat_ex5_state_q[0:`REQ_STATE_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) derat_ex5_ttype_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_ex5_ttype_offset:derat_ex5_ttype_offset + 2 - 1]), + .scout(sov[derat_ex5_ttype_offset:derat_ex5_ttype_offset + 2 - 1]), + .din(derat_ex5_ttype_d), + .dout(derat_ex5_ttype_q) + ); + + tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_ex5_pid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_ex5_pid_offset:derat_ex5_pid_offset + `PID_WIDTH - 1]), + .scout(sov[derat_ex5_pid_offset:derat_ex5_pid_offset + `PID_WIDTH - 1]), + .din(derat_ex5_pid_d[0:`PID_WIDTH - 1]), + .dout(derat_ex5_pid_q[0:`PID_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_ex5_lpid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_ex5_lpid_offset:derat_ex5_lpid_offset + `LPID_WIDTH - 1]), + .scout(sov[derat_ex5_lpid_offset:derat_ex5_lpid_offset + `LPID_WIDTH - 1]), + .din(derat_ex5_lpid_d[0:`LPID_WIDTH - 1]), + .dout(derat_ex5_lpid_q[0:`LPID_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) derat_ex5_itag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_ex5_itag_offset:derat_ex5_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[derat_ex5_itag_offset:derat_ex5_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(derat_ex5_itag_d), + .dout(derat_ex5_itag_q) + ); + + tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) derat_ex5_emq_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_ex5_emq_offset:derat_ex5_emq_offset + `EMQ_ENTRIES - 1]), + .scout(sov[derat_ex5_emq_offset:derat_ex5_emq_offset + `EMQ_ENTRIES - 1]), + .din(derat_ex5_emq_d), + .dout(derat_ex5_emq_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) derat_ex5_nonspec_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_ex5_nonspec_offset]), + .scout(sov[derat_ex5_nonspec_offset]), + .din(derat_ex5_nonspec_d), + .dout(derat_ex5_nonspec_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) derat_ex6_valid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_ex6_valid_offset]), + .scout(sov[derat_ex6_valid_offset]), + .din(derat_ex6_valid_d), + .dout(derat_ex6_valid_q) + ); + + tri_rlmreg_p #(.WIDTH(`THDID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_ex6_thdid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_ex6_thdid_offset:derat_ex6_thdid_offset + `THDID_WIDTH - 1]), + .scout(sov[derat_ex6_thdid_offset:derat_ex6_thdid_offset + `THDID_WIDTH - 1]), + .din(derat_ex6_thdid_d[0:`THDID_WIDTH - 1]), + .dout(derat_ex6_thdid_q[0:`THDID_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`EPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_ex6_epn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_ex6_epn_offset:derat_ex6_epn_offset + `EPN_WIDTH - 1]), + .scout(sov[derat_ex6_epn_offset:derat_ex6_epn_offset + `EPN_WIDTH - 1]), + .din(derat_ex6_epn_d[0:`EPN_WIDTH - 1]), + .dout(derat_ex6_epn_q[0:`EPN_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`REQ_STATE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_ex6_state_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_ex6_state_offset:derat_ex6_state_offset + `REQ_STATE_WIDTH - 1]), + .scout(sov[derat_ex6_state_offset:derat_ex6_state_offset + `REQ_STATE_WIDTH - 1]), + .din(derat_ex6_state_d[0:`REQ_STATE_WIDTH - 1]), + .dout(derat_ex6_state_q[0:`REQ_STATE_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) derat_ex6_ttype_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_ex6_ttype_offset:derat_ex6_ttype_offset + 2 - 1]), + .scout(sov[derat_ex6_ttype_offset:derat_ex6_ttype_offset + 2 - 1]), + .din(derat_ex6_ttype_d), + .dout(derat_ex6_ttype_q) + ); + + tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_ex6_pid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_ex6_pid_offset:derat_ex6_pid_offset + `PID_WIDTH - 1]), + .scout(sov[derat_ex6_pid_offset:derat_ex6_pid_offset + `PID_WIDTH - 1]), + .din(derat_ex6_pid_d[0:`PID_WIDTH - 1]), + .dout(derat_ex6_pid_q[0:`PID_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_ex6_lpid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_ex6_lpid_offset:derat_ex6_lpid_offset + `LPID_WIDTH - 1]), + .scout(sov[derat_ex6_lpid_offset:derat_ex6_lpid_offset + `LPID_WIDTH - 1]), + .din(derat_ex6_lpid_d[0:`LPID_WIDTH - 1]), + .dout(derat_ex6_lpid_q[0:`LPID_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) derat_ex6_itag_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_ex6_itag_offset:derat_ex6_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[derat_ex6_itag_offset:derat_ex6_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(derat_ex6_itag_d), + .dout(derat_ex6_itag_q) + ); + + tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) derat_ex6_emq_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_ex6_emq_offset:derat_ex6_emq_offset + `EMQ_ENTRIES - 1]), + .scout(sov[derat_ex6_emq_offset:derat_ex6_emq_offset + `EMQ_ENTRIES - 1]), + .din(derat_ex6_emq_d), + .dout(derat_ex6_emq_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) derat_ex6_nonspec_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[derat_ex6_nonspec_offset]), + .scout(sov[derat_ex6_nonspec_offset]), + .din(derat_ex6_nonspec_d), + .dout(derat_ex6_nonspec_q) + ); + + tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) spare_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_ccr2_notlb_b), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv[spare_offset:spare_offset + 32 - 1]), + .scout(sov[spare_offset:spare_offset + 32 - 1]), + .din(spare_q), + .dout(spare_q) + ); + + //------------------------------------------------ + // thold/sg latches + //------------------------------------------------ + + tri_plat #(.WIDTH(3)) perv_2to1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ccflush_dc), + .din( {pc_func_sl_thold_2, pc_func_slp_sl_thold_2, pc_sg_2} ), + .q( {pc_func_sl_thold_1, pc_func_slp_sl_thold_1, pc_sg_1} ) + ); + + tri_plat #(.WIDTH(3)) perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ccflush_dc), + .din( {pc_func_sl_thold_1, pc_func_slp_sl_thold_1, pc_sg_1} ), + .q( {pc_func_sl_thold_0, pc_func_slp_sl_thold_0, pc_sg_0} ) + ); + + tri_lcbor perv_lcbor_func_sl( + .clkoff_b(lcb_clkoff_dc_b), + .thold(pc_func_sl_thold_0), + .sg(pc_sg_0), + .act_dis(lcb_act_dis_dc), + .force_t(pc_func_sl_force), + .thold_b(pc_func_sl_thold_0_b) + ); + + tri_lcbor perv_lcbor_func_slp_sl( + .clkoff_b(lcb_clkoff_dc_b), + .thold(pc_func_slp_sl_thold_0), + .sg(pc_sg_0), + .act_dis(lcb_act_dis_dc), + .force_t(pc_func_slp_sl_force), + .thold_b(pc_func_slp_sl_thold_0_b) + ); + + //--------------------------------------------------------------------- + // Scan + //--------------------------------------------------------------------- + assign siv[0:scan_right] = {sov[1:scan_right], ac_func_scan_in}; + assign ac_func_scan_out = sov[0]; + +endmodule diff --git a/dev/verilog/work/mmu_a2o.vh b/dev/verilog/work/mmu_a2o.vh new file mode 100755 index 0000000..de2decf --- /dev/null +++ b/dev/verilog/work/mmu_a2o.vh @@ -0,0 +1,244 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +// *!**************************************************************** +// *! FILENAME : mmu_a2o.vh +// *! DESCRIPTION : Constants for a2o mmu +// *! CONTENTS : +// *! +// *!**************************************************************** + +`ifndef _mmu_a2o_vh_ +`define _mmu_a2o_vh_ +`define EXPAND_TYPE 2 // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) +`define EXPAND_TLB_TYPE 2 // 0 = erat-only, 1 = tlb logic, 2 = tlb array + +// Use this line for A2o core. Comment out for A2i design. +`define A2O +// comment out this line to compile for erat-only mode +`define TLB +// uncomment this line to compile for category E.MF (Embedded.MMU Freescale) +`define CAT_EMF +// uncomment this line to compile for category E.LRAT (Embedded.Logical to Real Address Translate) +`define CAT_LRAT +// uncomment this line to compile for category E.PT (Embedded.Page Table) +`define CAT_EPT +// uncomment this line to compile for wait on completion exception taken before spr updates occur +`define WAIT_UPDATES + +// Use this line for 2 mmu h/w thread. Comment out for 1 thread design. +`define MM_THREADS2 + +// set this variable for internal thread-wise generates +`ifdef MM_THREADS2 + `define MM_THREADS 2 + `define MM_THREADS_POOL_ENC 1 +`else + `define MM_THREADS 1 + `define MM_THREADS_POOL_ENC 0 +`endif + + + +`define THDID_WIDTH 4 // this is a pre-defined tag field width +`define PID_WIDTH 14 +`define PID_WIDTH_ERAT 8 +`define LPID_WIDTH 8 +`define T_WIDTH 3 +`define CLASS_WIDTH 2 +`define EXTCLASS_WIDTH 2 +`define TLBSEL_WIDTH 2 +`define EPN_WIDTH 52 +`define VPN_WIDTH 61 +`define ERAT_CAM_DATA_WIDTH 75 +`define ERAT_ARY_DATA_WIDTH 73 +`define ERAT_REL_DATA_WIDTH 132 +`define WS_WIDTH 2 +`define RS_IS_WIDTH 9 +`define RA_ENTRY_WIDTH 12 +`define RS_DATA_WIDTH 64 +`define DATA_OUT_WIDTH 64 +`define ERROR_WIDTH 3 +`define TLB_NUM_ENTRY 512 +`define TLB_NUM_ENTRY_LOG2 9 +`define TLB_WAYS 4 +`define TLB_ADDR_WIDTH 7 +`define TLB_WAY_WIDTH 168 +`define TLB_WORD_WIDTH 84 +`define TLB_SEQ_WIDTH 6 +`define POR_SEQ_WIDTH 3 +`define WATERMARK_WIDTH 4 +`define EPTR_WIDTH 4 +`define LRU_WIDTH 16 +`define MMUCR0_WIDTH 20 +`define MMUCR1_WIDTH 32 +`define MMUCR2_WIDTH 32 +`define MMUCR3_WIDTH 15 +`define SPR_CTL_WIDTH 3 +`define SPR_ETID_WIDTH 2 +`define SPR_ADDR_WIDTH 10 +`define SPR_DATA_WIDTH 64 +`define DEBUG_TRIGGER_WIDTH 12 +`define PERF_EVENT_WIDTH 4 // events per thread +`define REAL_ADDR_WIDTH 42 +`define RPN_WIDTH 30 // real_addr_WIDTH-12 +`define PTE_WIDTH 64 // page table entry +`define CHECK_PARITY 1 + +`ifdef A2O +`define DEBUG_TRACE_WIDTH 32 +`define ITAG_SIZE_ENC 7 +`define EMQ_ENTRIES 4 +`define TLB_TAG_WIDTH 122 +`define MESR1_WIDTH 24 // 4 x 6 bits, 1 of 64 events +`define MESR2_WIDTH 24 +`define PERF_MUX_WIDTH 64 // events per bus bit +`else +`define DEBUG_TRACE_WIDTH 88 +`define TLB_TAG_WIDTH 110 +`define MESR1_WIDTH 20 // 4 x 5 bits, 1 of 32 events +`define MESR2_WIDTH 20 +`define PERF_MUX_WIDTH 32 // events per bus bit +`endif + +//tlb_tagx_d <= ([0:51] epn & +// [52:65] pid & +// [66:67] IS & +// [68:69] Class & +// [70:73] state (pr,gs,as,cm) & +// [74:77] thdid & +// [78:81] size & +// [82:83] derat_miss/ierat_miss & +// [84:85] tlbsx/tlbsrx & +// [86:87] inval_snoop/tlbre & +// [88:89] tlbwe/ptereload & +// [90:97] lpid & +// [98] indirect +// [99] atsel & +// [100:102] esel & +// [103:105] hes/wq(0:1) & +// [106:107] lrat/pt & +// [108] record form +// [109] endflag +`define tagpos_epn 0 +`define tagpos_pid 52 // 14 bits +`define tagpos_is 66 +`define tagpos_class 68 +`define tagpos_state 70 // state: 0:pr 1:gs 2:as 3:cm +`define tagpos_thdid 74 +`define tagpos_size 78 +`define tagpos_type 82 // derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload +`define tagpos_lpid 90 +`define tagpos_ind 98 +`define tagpos_atsel 99 +`define tagpos_esel 100 +`define tagpos_hes 103 +`define tagpos_wq 104 +`define tagpos_lrat 106 +`define tagpos_pt 107 +`define tagpos_recform 108 +`define tagpos_endflag 109 +`ifdef A2O +`define tagpos_itag 110 +`define tagpos_nonspec 117 +`define tagpos_emq 118 +`endif + +// derat,ierat,tlbsx,tlbsrx,snoop,tlbre,tlbwe,ptereload +`define tagpos_type_derat `tagpos_type +`define tagpos_type_ierat `tagpos_type+1 +`define tagpos_type_tlbsx `tagpos_type+2 +`define tagpos_type_tlbsrx `tagpos_type+3 +`define tagpos_type_snoop `tagpos_type+4 +`define tagpos_type_tlbre `tagpos_type+5 +`define tagpos_type_tlbwe `tagpos_type+6 +`define tagpos_type_ptereload `tagpos_type+7 +// state: 0:pr 1:gs 2:as 3:cm +`define tagpos_pr `tagpos_state +`define tagpos_gs `tagpos_state+1 +`define tagpos_as `tagpos_state+2 +`define tagpos_cm `tagpos_state+3 + +`define waypos_epn 0 +`define waypos_size 52 +`define waypos_thdid 56 +`define waypos_class 60 +`define waypos_extclass 62 +`define waypos_lpid 66 +`define waypos_xbit 84 +`define waypos_tstmode4k 85 +`define waypos_rpn 88 +`define waypos_rc 118 +`define waypos_wlc 120 +`define waypos_resvattr 122 +`define waypos_vf 123 +`define waypos_ind 124 +`define waypos_ubits 125 +`define waypos_wimge 129 +`define waypos_usxwr 134 +`define waypos_gs 140 +`define waypos_ts 141 +`define waypos_tid 144 // 14 bits + +`define eratpos_epn 0 +`define eratpos_x 52 +`define eratpos_size 53 +`define eratpos_v 56 +`define eratpos_thdid 57 +`define eratpos_class 61 +`define eratpos_extclass 63 +`define eratpos_wren 65 +`define eratpos_rpnrsvd 66 +`define eratpos_rpn 70 +`define eratpos_r 100 +`define eratpos_c 101 +`define eratpos_relsoon 102 +`define eratpos_wlc 103 +`define eratpos_resvattr 105 +`define eratpos_vf 106 +`define eratpos_ubits 107 +`define eratpos_wimge 111 +`define eratpos_usxwr 116 +`define eratpos_gs 122 +`define eratpos_ts 123 +`define eratpos_tid 124 // 8 bits + +`define ptepos_rpn 0 +`define ptepos_wimge 40 +`define ptepos_r 45 +`define ptepos_ubits 46 +`define ptepos_sw0 50 +`define ptepos_c 51 +`define ptepos_size 52 +`define ptepos_usxwr 56 +`define ptepos_sw1 62 +`define ptepos_valid 63 + + +// Do NOT add any defines below this line +`endif //_mmu_a2o_vh_ diff --git a/dev/verilog/work/pcq.v b/dev/verilog/work/pcq.v new file mode 100755 index 0000000..b006632 --- /dev/null +++ b/dev/verilog/work/pcq.v @@ -0,0 +1,793 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +// +// Description: Pervasive Core Unit +// +//***************************************************************************** + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" + +module pcq( +// Include model build parameters +`include "tri_a2o.vh" + + // inout vdd, + // inout gnd, + (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) // nclk + input [0:`NCLK_WIDTH-1] nclk, + //SCOM and Register Interfaces + // SCOM Satellite + input [0:3] an_ac_scom_sat_id, + input an_ac_scom_dch, + input an_ac_scom_cch, + output ac_an_scom_dch, + output ac_an_scom_cch, + // Slow SPR + input slowspr_val_in, + input slowspr_rw_in, + input [0:1] slowspr_etid_in, + input [0:9] slowspr_addr_in, + input [64-`GPR_WIDTH:63] slowspr_data_in, + input slowspr_done_in, + input [0:`THREADS-1] cp_flush, + output slowspr_val_out, + output slowspr_rw_out, + output [0:1] slowspr_etid_out, + output [0:9] slowspr_addr_out, + output [64-`GPR_WIDTH:63] slowspr_data_out, + output slowspr_done_out, + + //FIR and Error Signals + output [0:`THREADS-1] ac_an_special_attn, + output [0:2] ac_an_checkstop, + output [0:2] ac_an_local_checkstop, + output [0:2] ac_an_recov_err, + output ac_an_trace_error, + output ac_an_livelock_active, + input an_ac_checkstop, + input [0:`THREADS-1] fu_pc_err_regfile_parity, + input [0:`THREADS-1] fu_pc_err_regfile_ue, + input iu_pc_err_icache_parity, + input iu_pc_err_icachedir_parity, + input iu_pc_err_icachedir_multihit, + input iu_pc_err_ierat_parity, + input iu_pc_err_ierat_multihit, + input iu_pc_err_btb_parity, + input [0:`THREADS-1] iu_pc_err_cpArray_parity, + input [0:`THREADS-1] iu_pc_err_ucode_illegal, + input [0:`THREADS-1] iu_pc_err_mchk_disabled, + input [0:`THREADS-1] iu_pc_err_debug_event, + input lq_pc_err_dcache_parity, + input lq_pc_err_dcachedir_ldp_parity, + input lq_pc_err_dcachedir_stp_parity, + input lq_pc_err_dcachedir_ldp_multihit, + input lq_pc_err_dcachedir_stp_multihit, + input lq_pc_err_derat_parity, + input lq_pc_err_derat_multihit, + input lq_pc_err_l2intrf_ecc, + input lq_pc_err_l2intrf_ue, + input lq_pc_err_invld_reld, + input lq_pc_err_l2credit_overrun, + input [0:`THREADS-1] lq_pc_err_regfile_parity, + input [0:`THREADS-1] lq_pc_err_regfile_ue, + input lq_pc_err_prefetcher_parity, + input lq_pc_err_relq_parity, + input mm_pc_err_tlb_parity, + input mm_pc_err_tlb_multihit, + input mm_pc_err_tlb_lru_parity, + input mm_pc_err_local_snoop_reject, + input [0:`THREADS-1] xu_pc_err_sprg_ecc, + input [0:`THREADS-1] xu_pc_err_sprg_ue, + input [0:`THREADS-1] xu_pc_err_regfile_parity, + input [0:`THREADS-1] xu_pc_err_regfile_ue, + input [0:`THREADS-1] xu_pc_err_llbust_attempt, + input [0:`THREADS-1] xu_pc_err_llbust_failed, + input [0:`THREADS-1] xu_pc_err_wdt_reset, + input [0:`THREADS-1] iu_pc_err_attention_instr, + output pc_iu_inj_icache_parity, + output pc_iu_inj_icachedir_parity, + output pc_iu_inj_icachedir_multihit, + output pc_lq_inj_dcache_parity, + output pc_lq_inj_dcachedir_ldp_parity, + output pc_lq_inj_dcachedir_stp_parity, + output pc_lq_inj_dcachedir_ldp_multihit, + output pc_lq_inj_dcachedir_stp_multihit, + output pc_lq_inj_prefetcher_parity, + output pc_lq_inj_relq_parity, + output [0:`THREADS-1] pc_xu_inj_sprg_ecc, + output [0:`THREADS-1] pc_fx0_inj_regfile_parity, + output [0:`THREADS-1] pc_fx1_inj_regfile_parity, + output [0:`THREADS-1] pc_lq_inj_regfile_parity, + output [0:`THREADS-1] pc_fu_inj_regfile_parity, + output [0:`THREADS-1] pc_xu_inj_llbust_attempt, + output [0:`THREADS-1] pc_xu_inj_llbust_failed, + output [0:`THREADS-1] pc_iu_inj_cpArray_parity, + // Unit quiesce and credit status bits + input [0:`THREADS-1] iu_pc_quiesce, + input [0:`THREADS-1] iu_pc_icache_quiesce, + input [0:`THREADS-1] lq_pc_ldq_quiesce, + input [0:`THREADS-1] lq_pc_stq_quiesce, + input [0:`THREADS-1] lq_pc_pfetch_quiesce, + input [0:`THREADS-1] mm_pc_tlb_req_quiesce, + input [0:`THREADS-1] mm_pc_tlb_ctl_quiesce, + input [0:`THREADS-1] mm_pc_htw_quiesce, + input [0:`THREADS-1] mm_pc_inval_quiesce, + input [0:`THREADS-1] iu_pc_fx0_credit_ok, + input [0:`THREADS-1] iu_pc_fx1_credit_ok, + input [0:`THREADS-1] iu_pc_axu0_credit_ok, + input [0:`THREADS-1] iu_pc_axu1_credit_ok, + input [0:`THREADS-1] iu_pc_lq_credit_ok, + input [0:`THREADS-1] iu_pc_sq_credit_ok, + //Debug Functions + // RAM Command/Data + output [0:31] pc_iu_ram_instr, + output [0:3] pc_iu_ram_instr_ext, + output [0:`THREADS-1] pc_iu_ram_active, + output pc_iu_ram_execute, + input iu_pc_ram_done, + input iu_pc_ram_interrupt, + input iu_pc_ram_unsupported, + output [0:`THREADS-1] pc_xu_ram_active, + input xu_pc_ram_data_val, + input [64-`GPR_WIDTH:63] xu_pc_ram_data, + output [0:`THREADS-1] pc_fu_ram_active, + input fu_pc_ram_data_val, + input [0:63] fu_pc_ram_data, + output [0:`THREADS-1] pc_lq_ram_active, + input lq_pc_ram_data_val, + input [64-`GPR_WIDTH:63] lq_pc_ram_data, + output pc_xu_msrovride_enab, + output pc_xu_msrovride_pr, + output pc_xu_msrovride_gs, + output pc_xu_msrovride_de, + output pc_iu_ram_force_cmplt, + output [0:`THREADS-1] pc_iu_ram_flush_thread, + // THRCTL + PCCR0 Registers + input [0:`THREADS-1] xu_pc_running, + input [0:`THREADS-1] iu_pc_stop_dbg_event, + input [0:`THREADS-1] xu_pc_stop_dnh_instr, + input [0:`THREADS-1] iu_pc_step_done, + output [0:`THREADS-1] pc_iu_stop, + output [0:`THREADS-1] pc_iu_step, + output pc_xu_extirpts_dis_on_stop, + output pc_xu_timebase_dis_on_stop, + output pc_xu_decrem_dis_on_stop, + input an_ac_debug_stop, + output [0:3*`THREADS-1] pc_iu_dbg_action, + output [0:`THREADS-1] pc_iu_spr_dbcr0_edm, + output [0:`THREADS-1] pc_xu_spr_dbcr0_edm, + + //Trace/Debug Bus + output [0:31] debug_bus_out, + input [0:31] debug_bus_in, + input [0:3] coretrace_ctrls_in, + output [0:3] coretrace_ctrls_out, + // Debug Select Register outputs to units for debug grouping + output pc_iu_trace_bus_enable, + output pc_fu_trace_bus_enable, + output pc_rv_trace_bus_enable, + output pc_mm_trace_bus_enable, + output pc_xu_trace_bus_enable, + output pc_lq_trace_bus_enable, + output [0:10] pc_iu_debug_mux1_ctrls, + output [0:10] pc_iu_debug_mux2_ctrls, + output [0:10] pc_fu_debug_mux_ctrls, + output [0:10] pc_rv_debug_mux_ctrls, + output [0:10] pc_mm_debug_mux_ctrls, + output [0:10] pc_xu_debug_mux_ctrls, + output [0:10] pc_lq_debug_mux1_ctrls, + output [0:10] pc_lq_debug_mux2_ctrls, + + //Performance event mux controls + output [0:39] pc_rv_event_mux_ctrls, + output pc_iu_event_bus_enable, + output pc_fu_event_bus_enable, + output pc_rv_event_bus_enable, + output pc_mm_event_bus_enable, + output pc_xu_event_bus_enable, + output pc_lq_event_bus_enable, + output [0:2] pc_iu_event_count_mode, + output [0:2] pc_fu_event_count_mode, + output [0:2] pc_rv_event_count_mode, + output [0:2] pc_mm_event_count_mode, + output [0:2] pc_xu_event_count_mode, + output [0:2] pc_lq_event_count_mode, + output pc_lq_event_bus_seldbghi, + output pc_lq_event_bus_seldbglo, + output pc_iu_instr_trace_mode, + output pc_iu_instr_trace_tid, + output pc_lq_instr_trace_mode, + output pc_lq_instr_trace_tid, + output pc_xu_instr_trace_mode, + output pc_xu_instr_trace_tid, + input [0:`THREADS-1] xu_pc_perfmon_alert, + output [0:`THREADS-1] pc_xu_spr_cesr1_pmae, + + //Reset related + output pc_lq_init_reset, + output pc_iu_init_reset, + + //Power Management + output [0:`THREADS-1] ac_an_pm_thread_running, + input [0:`THREADS-1] an_ac_pm_thread_stop, + input [0:`THREADS-1] an_ac_pm_fetch_halt, + output [0:`THREADS-1] pc_iu_pm_fetch_halt, + output ac_an_power_managed, + output ac_an_rvwinkle_mode, + output pc_xu_pm_hold_thread, + input [0:1] xu_pc_spr_ccr0_pme, + input [0:`THREADS-1] xu_pc_spr_ccr0_we, + + //Clock, Test, and LCB Controls + input an_ac_gsd_test_enable_dc, + input an_ac_gsd_test_acmode_dc, + input an_ac_ccflush_dc, + input an_ac_ccenable_dc, + input an_ac_lbist_en_dc, + input an_ac_lbist_ip_dc, + input an_ac_lbist_ac_mode_dc, + input an_ac_scan_diag_dc, + input an_ac_scan_dis_dc_b, + // Thold input to clock control macro + input an_ac_rtim_sl_thold_7, + input an_ac_func_sl_thold_7, + input an_ac_func_nsl_thold_7, + input an_ac_ary_nsl_thold_7, + input an_ac_sg_7, + input an_ac_fce_7, + input [0:8] an_ac_scan_type_dc, + // Thold outputs to clock staging + output pc_rp_ccflush_out_dc, + output pc_rp_gptr_sl_thold_4, + output pc_rp_time_sl_thold_4, + output pc_rp_repr_sl_thold_4, + output pc_rp_abst_sl_thold_4, + output pc_rp_abst_slp_sl_thold_4, + output pc_rp_regf_sl_thold_4, + output pc_rp_regf_slp_sl_thold_4, + output pc_rp_func_sl_thold_4, + output pc_rp_func_slp_sl_thold_4, + output pc_rp_cfg_sl_thold_4, + output pc_rp_cfg_slp_sl_thold_4, + output pc_rp_func_nsl_thold_4, + output pc_rp_func_slp_nsl_thold_4, + output pc_rp_ary_nsl_thold_4, + output pc_rp_ary_slp_nsl_thold_4, + output pc_rp_rtim_sl_thold_4, + output pc_rp_sg_4, + output pc_rp_fce_4, + // + output pc_fu_ccflush_dc, + output pc_fu_gptr_sl_thold_3, + output pc_fu_time_sl_thold_3, + output pc_fu_repr_sl_thold_3, + output pc_fu_abst_sl_thold_3, + output pc_fu_abst_slp_sl_thold_3, + output [0:1] pc_fu_func_sl_thold_3, + output [0:1] pc_fu_func_slp_sl_thold_3, + output pc_fu_cfg_sl_thold_3, + output pc_fu_cfg_slp_sl_thold_3, + output pc_fu_func_nsl_thold_3, + output pc_fu_func_slp_nsl_thold_3, + output pc_fu_ary_nsl_thold_3, + output pc_fu_ary_slp_nsl_thold_3, + output [0:1] pc_fu_sg_3, + output pc_fu_fce_3, + + //Scanning + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) // scan_in + input gptr_scan_in, + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) // scan_in + input ccfg_scan_in, + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) // scan_in + input bcfg_scan_in, + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) // scan_in + input dcfg_scan_in, + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) // scan_in + input [0:1] func_scan_in, + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) // scan_out + output gptr_scan_out, + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) // scan_out + output ccfg_scan_out, + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) // scan_out + output bcfg_scan_out, + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) // scan_out + output dcfg_scan_out, + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) // scan_out + output [0:1] func_scan_out +); + + +//===================================================================== +// Signal Declarations +//===================================================================== +//--------------------------------------------------------------------- +// Basic/Misc Signals + wire ct_db_func_scan_out; + wire db_ss_func_scan_out; + wire lcbctrl_gptr_scan_out; + // Misc Controls + wire [0:`THREADS-1] ct_rg_power_managed; + wire ct_ck_pm_raise_tholds; + wire ct_ck_pm_ccflush_disable; + wire rg_ct_dis_pwr_savings; + wire rg_ck_fast_xstop; + wire ct_rg_hold_during_init; + // SRAMD data and load pulse + wire rg_rg_load_sramd; + wire [0:63] rg_rg_sramd_din; + // Clock Controls + wire d_mode_dc; + wire clkoff_dc_b; + wire act_dis_dc; + wire [0:4] delay_lclkr_dc; + wire [0:4] mpw1_dc_b; + wire mpw2_dc_b; + wire pc_pc_ccflush_dc; + wire pc_pc_gptr_sl_thold_0; + wire pc_pc_func_sl_thold_0; + wire pc_pc_func_slp_sl_thold_0; + wire pc_pc_cfg_sl_thold_0; + wire pc_pc_cfg_slp_sl_thold_0; + wire pc_pc_sg_0; + // Trace bus signals + wire sp_rg_trace_bus_enable; + wire rg_db_trace_bus_enable; + wire [0:10] rg_db_debug_mux_ctrls; + wire [0:11] rg_db_dbg_scom; + wire [0:24] rg_db_dbg_thrctls; + wire [0:15] rg_db_dbg_ram; + wire [0:27] rg_db_dbg_fir0_err; + wire [0:19] rg_db_dbg_fir1_err; + wire [0:19] rg_db_dbg_fir2_err; + wire [0:14] rg_db_dbg_fir_misc; + wire [0:14] ct_db_dbg_ctrls; + wire [0:7] rg_db_dbg_spr; + + wire vdd; + wire gnd; + +(* analysis_not_referenced="true" *) + wire unused_signals; + assign unused_signals = (|{1'b0, 1'b0}); + + assign vdd = 1'b1; + assign gnd = 1'b0; + +//!! Bugspray Include: pcq; + +//===================================================================== +// Start of PCQ Module Instantiations +//===================================================================== + + pcq_regs pcq_regs( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .scan_dis_dc_b(an_ac_scan_dis_dc_b), + .lcb_clkoff_dc_b(clkoff_dc_b), + .lcb_d_mode_dc(d_mode_dc), + .lcb_mpw1_dc_b(mpw1_dc_b[0]), + .lcb_mpw2_dc_b(mpw2_dc_b), + .lcb_delay_lclkr_dc(delay_lclkr_dc[0]), + .lcb_act_dis_dc(act_dis_dc), + .lcb_func_slp_sl_thold_0(pc_pc_func_slp_sl_thold_0), + .lcb_cfg_sl_thold_0(pc_pc_cfg_sl_thold_0), + .lcb_cfg_slp_sl_thold_0(pc_pc_cfg_slp_sl_thold_0), + .lcb_sg_0(pc_pc_sg_0), + .ccfg_scan_in(ccfg_scan_in), + .bcfg_scan_in(bcfg_scan_in), + .dcfg_scan_in(dcfg_scan_in), + .func_scan_in(func_scan_in[0]), + .ccfg_scan_out(ccfg_scan_out), + .bcfg_scan_out(bcfg_scan_out), + .dcfg_scan_out(dcfg_scan_out), + .func_scan_out(func_scan_out[0]), + //SCOM Satellite interface + .an_ac_scom_sat_id(an_ac_scom_sat_id), + .an_ac_scom_dch(an_ac_scom_dch), + .an_ac_scom_cch(an_ac_scom_cch), + .ac_an_scom_dch(ac_an_scom_dch), + .ac_an_scom_cch(ac_an_scom_cch), + //Error Related + .ac_an_special_attn(ac_an_special_attn), + .ac_an_checkstop(ac_an_checkstop), + .ac_an_local_checkstop(ac_an_local_checkstop), + .ac_an_recov_err(ac_an_recov_err), + .ac_an_trace_error(ac_an_trace_error), + .ac_an_livelock_active(ac_an_livelock_active), + .an_ac_checkstop(an_ac_checkstop), + .rg_ck_fast_xstop(rg_ck_fast_xstop), + .fu_pc_err_regfile_parity(fu_pc_err_regfile_parity), + .fu_pc_err_regfile_ue(fu_pc_err_regfile_ue), + .iu_pc_err_icache_parity(iu_pc_err_icache_parity), + .iu_pc_err_icachedir_parity(iu_pc_err_icachedir_parity), + .iu_pc_err_icachedir_multihit(iu_pc_err_icachedir_multihit), + .iu_pc_err_ierat_parity(iu_pc_err_ierat_parity), + .iu_pc_err_ierat_multihit(iu_pc_err_ierat_multihit), + .iu_pc_err_btb_parity(iu_pc_err_btb_parity), + .iu_pc_err_cpArray_parity(iu_pc_err_cpArray_parity), + .iu_pc_err_ucode_illegal(iu_pc_err_ucode_illegal), + .iu_pc_err_mchk_disabled(iu_pc_err_mchk_disabled), + .iu_pc_err_debug_event(iu_pc_err_debug_event), + .lq_pc_err_dcache_parity(lq_pc_err_dcache_parity), + .lq_pc_err_dcachedir_ldp_parity(lq_pc_err_dcachedir_ldp_parity), + .lq_pc_err_dcachedir_stp_parity(lq_pc_err_dcachedir_stp_parity), + .lq_pc_err_dcachedir_ldp_multihit(lq_pc_err_dcachedir_ldp_multihit), + .lq_pc_err_dcachedir_stp_multihit(lq_pc_err_dcachedir_stp_multihit), + .lq_pc_err_derat_parity(lq_pc_err_derat_parity), + .lq_pc_err_derat_multihit(lq_pc_err_derat_multihit), + .lq_pc_err_l2intrf_ecc(lq_pc_err_l2intrf_ecc), + .lq_pc_err_l2intrf_ue(lq_pc_err_l2intrf_ue), + .lq_pc_err_invld_reld(lq_pc_err_invld_reld), + .lq_pc_err_l2credit_overrun(lq_pc_err_l2credit_overrun), + .lq_pc_err_regfile_parity(lq_pc_err_regfile_parity), + .lq_pc_err_regfile_ue(lq_pc_err_regfile_ue), + .lq_pc_err_prefetcher_parity(lq_pc_err_prefetcher_parity), + .lq_pc_err_relq_parity(lq_pc_err_relq_parity), + .mm_pc_err_tlb_parity(mm_pc_err_tlb_parity), + .mm_pc_err_tlb_multihit(mm_pc_err_tlb_multihit), + .mm_pc_err_tlb_lru_parity(mm_pc_err_tlb_lru_parity), + .mm_pc_err_local_snoop_reject(mm_pc_err_local_snoop_reject), + .xu_pc_err_sprg_ecc(xu_pc_err_sprg_ecc), + .xu_pc_err_sprg_ue(xu_pc_err_sprg_ue), + .xu_pc_err_regfile_parity(xu_pc_err_regfile_parity), + .xu_pc_err_regfile_ue(xu_pc_err_regfile_ue), + .xu_pc_err_llbust_attempt(xu_pc_err_llbust_attempt), + .xu_pc_err_llbust_failed(xu_pc_err_llbust_failed), + .xu_pc_err_wdt_reset(xu_pc_err_wdt_reset), + .iu_pc_err_attention_instr(iu_pc_err_attention_instr), + .pc_iu_inj_icache_parity(pc_iu_inj_icache_parity), + .pc_iu_inj_icachedir_parity(pc_iu_inj_icachedir_parity), + .pc_iu_inj_icachedir_multihit(pc_iu_inj_icachedir_multihit), + .pc_lq_inj_dcache_parity(pc_lq_inj_dcache_parity), + .pc_lq_inj_dcachedir_ldp_parity(pc_lq_inj_dcachedir_ldp_parity), + .pc_lq_inj_dcachedir_stp_parity(pc_lq_inj_dcachedir_stp_parity), + .pc_lq_inj_dcachedir_ldp_multihit(pc_lq_inj_dcachedir_ldp_multihit), + .pc_lq_inj_dcachedir_stp_multihit(pc_lq_inj_dcachedir_stp_multihit), + .pc_lq_inj_prefetcher_parity(pc_lq_inj_prefetcher_parity), + .pc_lq_inj_relq_parity(pc_lq_inj_relq_parity), + .pc_xu_inj_sprg_ecc(pc_xu_inj_sprg_ecc), + .pc_fx0_inj_regfile_parity(pc_fx0_inj_regfile_parity), + .pc_fx1_inj_regfile_parity(pc_fx1_inj_regfile_parity), + .pc_lq_inj_regfile_parity(pc_lq_inj_regfile_parity), + .pc_fu_inj_regfile_parity(pc_fu_inj_regfile_parity), + .pc_xu_inj_llbust_attempt(pc_xu_inj_llbust_attempt), + .pc_xu_inj_llbust_failed(pc_xu_inj_llbust_failed), + .pc_iu_inj_cpArray_parity(pc_iu_inj_cpArray_parity), + // Unit quiesce and credit status bits + .iu_pc_quiesce(iu_pc_quiesce), + .iu_pc_icache_quiesce(iu_pc_icache_quiesce), + .lq_pc_ldq_quiesce(lq_pc_ldq_quiesce), + .lq_pc_stq_quiesce(lq_pc_stq_quiesce), + .lq_pc_pfetch_quiesce(lq_pc_pfetch_quiesce), + .mm_pc_tlb_req_quiesce(mm_pc_tlb_req_quiesce), + .mm_pc_tlb_ctl_quiesce(mm_pc_tlb_ctl_quiesce), + .mm_pc_htw_quiesce(mm_pc_htw_quiesce), + .mm_pc_inval_quiesce(mm_pc_inval_quiesce), + .iu_pc_fx0_credit_ok(iu_pc_fx0_credit_ok), + .iu_pc_fx1_credit_ok(iu_pc_fx1_credit_ok), + .iu_pc_axu0_credit_ok(iu_pc_axu0_credit_ok), + .iu_pc_axu1_credit_ok(iu_pc_axu1_credit_ok), + .iu_pc_lq_credit_ok(iu_pc_lq_credit_ok), + .iu_pc_sq_credit_ok(iu_pc_sq_credit_ok), + //RAMC+RAMD + .pc_iu_ram_instr(pc_iu_ram_instr), + .pc_iu_ram_instr_ext(pc_iu_ram_instr_ext), + .pc_iu_ram_active(pc_iu_ram_active), + .pc_iu_ram_execute(pc_iu_ram_execute), + .iu_pc_ram_done(iu_pc_ram_done), + .iu_pc_ram_interrupt(iu_pc_ram_interrupt), + .iu_pc_ram_unsupported(iu_pc_ram_unsupported), + .pc_xu_ram_active(pc_xu_ram_active), + .xu_pc_ram_data_val(xu_pc_ram_data_val), + .xu_pc_ram_data(xu_pc_ram_data), + .pc_fu_ram_active(pc_fu_ram_active), + .fu_pc_ram_data_val(fu_pc_ram_data_val), + .fu_pc_ram_data(fu_pc_ram_data), + .pc_lq_ram_active(pc_lq_ram_active), + .lq_pc_ram_data_val(lq_pc_ram_data_val), + .lq_pc_ram_data(lq_pc_ram_data), + .pc_xu_msrovride_enab(pc_xu_msrovride_enab), + .pc_xu_msrovride_pr(pc_xu_msrovride_pr), + .pc_xu_msrovride_gs(pc_xu_msrovride_gs), + .pc_xu_msrovride_de(pc_xu_msrovride_de), + .pc_iu_ram_force_cmplt(pc_iu_ram_force_cmplt), + .pc_iu_ram_flush_thread(pc_iu_ram_flush_thread), + .rg_rg_load_sramd(rg_rg_load_sramd), + .rg_rg_sramd_din(rg_rg_sramd_din), + //THRCTL + PCCR0 Registers + .ac_an_pm_thread_running(ac_an_pm_thread_running), + .pc_iu_stop(pc_iu_stop), + .pc_iu_step(pc_iu_step), + .pc_iu_dbg_action(pc_iu_dbg_action), + .pc_iu_spr_dbcr0_edm(pc_iu_spr_dbcr0_edm), + .pc_xu_spr_dbcr0_edm(pc_xu_spr_dbcr0_edm), + .xu_pc_running(xu_pc_running), + .iu_pc_stop_dbg_event(iu_pc_stop_dbg_event), + .xu_pc_stop_dnh_instr(xu_pc_stop_dnh_instr), + .iu_pc_step_done(iu_pc_step_done), + .an_ac_pm_thread_stop(an_ac_pm_thread_stop), + .an_ac_pm_fetch_halt(an_ac_pm_fetch_halt), + .pc_iu_pm_fetch_halt(pc_iu_pm_fetch_halt), + .ct_rg_power_managed(ct_rg_power_managed), + .ct_rg_hold_during_init(ct_rg_hold_during_init), + .an_ac_debug_stop(an_ac_debug_stop), + .pc_xu_extirpts_dis_on_stop(pc_xu_extirpts_dis_on_stop), + .pc_xu_timebase_dis_on_stop(pc_xu_timebase_dis_on_stop), + .pc_xu_decrem_dis_on_stop(pc_xu_decrem_dis_on_stop), + .rg_ct_dis_pwr_savings(rg_ct_dis_pwr_savings), + //Debug Registers + .sp_rg_trace_bus_enable(sp_rg_trace_bus_enable), + .rg_db_trace_bus_enable(rg_db_trace_bus_enable), + .pc_iu_trace_bus_enable(pc_iu_trace_bus_enable), + .pc_fu_trace_bus_enable(pc_fu_trace_bus_enable), + .pc_rv_trace_bus_enable(pc_rv_trace_bus_enable), + .pc_mm_trace_bus_enable(pc_mm_trace_bus_enable), + .pc_xu_trace_bus_enable(pc_xu_trace_bus_enable), + .pc_lq_trace_bus_enable(pc_lq_trace_bus_enable), + .rg_db_debug_mux_ctrls(rg_db_debug_mux_ctrls), + .pc_iu_debug_mux1_ctrls(pc_iu_debug_mux1_ctrls), + .pc_iu_debug_mux2_ctrls(pc_iu_debug_mux2_ctrls), + .pc_fu_debug_mux_ctrls(pc_fu_debug_mux_ctrls), + .pc_rv_debug_mux_ctrls(pc_rv_debug_mux_ctrls), + .pc_mm_debug_mux_ctrls(pc_mm_debug_mux_ctrls), + .pc_xu_debug_mux_ctrls(pc_xu_debug_mux_ctrls), + .pc_lq_debug_mux1_ctrls(pc_lq_debug_mux1_ctrls), + .pc_lq_debug_mux2_ctrls(pc_lq_debug_mux2_ctrls), + //Trace Signals + .dbg_scom(rg_db_dbg_scom), + .dbg_thrctls(rg_db_dbg_thrctls), + .dbg_ram(rg_db_dbg_ram), + .dbg_fir0_err(rg_db_dbg_fir0_err), + .dbg_fir1_err(rg_db_dbg_fir1_err), + .dbg_fir2_err(rg_db_dbg_fir2_err), + .dbg_fir_misc(rg_db_dbg_fir_misc) + ); + + pcq_ctrl pcq_ctrl( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .scan_dis_dc_b(an_ac_scan_dis_dc_b), + .lcb_clkoff_dc_b(clkoff_dc_b), + .lcb_mpw1_dc_b(mpw1_dc_b[1]), + .lcb_mpw2_dc_b(mpw2_dc_b), + .lcb_delay_lclkr_dc(delay_lclkr_dc[1]), + .lcb_act_dis_dc(act_dis_dc), + .pc_pc_func_slp_sl_thold_0(pc_pc_func_slp_sl_thold_0), + .pc_pc_sg_0(pc_pc_sg_0), + .func_scan_in(func_scan_in[1]), + .func_scan_out(ct_db_func_scan_out), + //Stop/Start/Reset + .pc_lq_init_reset(pc_lq_init_reset), + .pc_iu_init_reset(pc_iu_init_reset), + .ct_rg_hold_during_init(ct_rg_hold_during_init), + //Power Management + .ct_rg_power_managed(ct_rg_power_managed), + .ac_an_power_managed(ac_an_power_managed), + .ac_an_rvwinkle_mode(ac_an_rvwinkle_mode), + .pc_xu_pm_hold_thread(pc_xu_pm_hold_thread), + .ct_ck_pm_ccflush_disable(ct_ck_pm_ccflush_disable), + .ct_ck_pm_raise_tholds(ct_ck_pm_raise_tholds), + .rg_ct_dis_pwr_savings(rg_ct_dis_pwr_savings), + .xu_pc_spr_ccr0_pme(xu_pc_spr_ccr0_pme), + .xu_pc_spr_ccr0_we(xu_pc_spr_ccr0_we), + //Trace/Trigger Signals + .dbg_ctrls(ct_db_dbg_ctrls) + ); + + pcq_dbg pcq_dbg( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .scan_dis_dc_b(an_ac_scan_dis_dc_b), + .lcb_clkoff_dc_b(clkoff_dc_b), + .lcb_mpw1_dc_b(mpw1_dc_b[2]), + .lcb_mpw2_dc_b(mpw2_dc_b), + .lcb_delay_lclkr_dc(delay_lclkr_dc[2]), + .lcb_act_dis_dc(act_dis_dc), + .pc_pc_func_slp_sl_thold_0(pc_pc_func_slp_sl_thold_0), + .pc_pc_sg_0(pc_pc_sg_0), + .func_scan_in(ct_db_func_scan_out), + .func_scan_out(db_ss_func_scan_out), + //Trace/Trigger Bus + .debug_bus_out(debug_bus_out), + .debug_bus_in(debug_bus_in), + .rg_db_trace_bus_enable(rg_db_trace_bus_enable), + .rg_db_debug_mux_ctrls(rg_db_debug_mux_ctrls), + .coretrace_ctrls_in(coretrace_ctrls_in), + .coretrace_ctrls_out(coretrace_ctrls_out), + //PC Unit internal debug signals + .rg_db_dbg_scom(rg_db_dbg_scom), + .rg_db_dbg_thrctls(rg_db_dbg_thrctls), + .rg_db_dbg_ram(rg_db_dbg_ram), + .rg_db_dbg_fir0_err(rg_db_dbg_fir0_err), + .rg_db_dbg_fir1_err(rg_db_dbg_fir1_err), + .rg_db_dbg_fir2_err(rg_db_dbg_fir2_err), + .rg_db_dbg_fir_misc(rg_db_dbg_fir_misc), + .ct_db_dbg_ctrls(ct_db_dbg_ctrls), + .rg_db_dbg_spr(rg_db_dbg_spr) + ); + + pcq_spr pcq_spr( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .scan_dis_dc_b(an_ac_scan_dis_dc_b), + .lcb_clkoff_dc_b(clkoff_dc_b), + .lcb_mpw1_dc_b(mpw1_dc_b[0]), + .lcb_mpw2_dc_b(mpw2_dc_b), + .lcb_delay_lclkr_dc(delay_lclkr_dc[0]), + .lcb_act_dis_dc(act_dis_dc), + .pc_pc_func_sl_thold_0(pc_pc_func_sl_thold_0), + .pc_pc_sg_0(pc_pc_sg_0), + .func_scan_in(db_ss_func_scan_out), + .func_scan_out(func_scan_out[1]), + // slowSPR Interface + .slowspr_val_in(slowspr_val_in), + .slowspr_rw_in(slowspr_rw_in), + .slowspr_etid_in(slowspr_etid_in), + .slowspr_addr_in(slowspr_addr_in), + .slowspr_data_in(slowspr_data_in[64 - `GPR_WIDTH:63]), + .slowspr_done_in(slowspr_done_in), + .cp_flush(cp_flush), + .slowspr_val_out(slowspr_val_out), + .slowspr_rw_out(slowspr_rw_out), + .slowspr_etid_out(slowspr_etid_out), + .slowspr_addr_out(slowspr_addr_out), + .slowspr_data_out(slowspr_data_out[64 - `GPR_WIDTH:63]), + .slowspr_done_out(slowspr_done_out), + // Event Mux Controls + .pc_rv_event_mux_ctrls(pc_rv_event_mux_ctrls), + // CESR1 Controls + .pc_iu_event_bus_enable(pc_iu_event_bus_enable), + .pc_fu_event_bus_enable(pc_fu_event_bus_enable), + .pc_rv_event_bus_enable(pc_rv_event_bus_enable), + .pc_mm_event_bus_enable(pc_mm_event_bus_enable), + .pc_xu_event_bus_enable(pc_xu_event_bus_enable), + .pc_lq_event_bus_enable(pc_lq_event_bus_enable), + .pc_iu_event_count_mode(pc_iu_event_count_mode), + .pc_fu_event_count_mode(pc_fu_event_count_mode), + .pc_rv_event_count_mode(pc_rv_event_count_mode), + .pc_mm_event_count_mode(pc_mm_event_count_mode), + .pc_xu_event_count_mode(pc_xu_event_count_mode), + .pc_lq_event_count_mode(pc_lq_event_count_mode), + .sp_rg_trace_bus_enable(sp_rg_trace_bus_enable), + .pc_iu_instr_trace_mode(pc_iu_instr_trace_mode), + .pc_iu_instr_trace_tid(pc_iu_instr_trace_tid), + .pc_lq_instr_trace_mode(pc_lq_instr_trace_mode), + .pc_lq_instr_trace_tid(pc_lq_instr_trace_tid), + .pc_xu_instr_trace_mode(pc_xu_instr_trace_mode), + .pc_xu_instr_trace_tid(pc_xu_instr_trace_tid), + .pc_lq_event_bus_seldbghi(pc_lq_event_bus_seldbghi), + .pc_lq_event_bus_seldbglo(pc_lq_event_bus_seldbglo), + .xu_pc_perfmon_alert(xu_pc_perfmon_alert), + .pc_xu_spr_cesr1_pmae(pc_xu_spr_cesr1_pmae), + // SRAMD data and load pulse + .rg_rg_load_sramd(rg_rg_load_sramd), + .rg_rg_sramd_din(rg_rg_sramd_din), + // Debug + .dbg_spr(rg_db_dbg_spr) + ); + + pcq_clks pcq_clks( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .rtim_sl_thold_7(an_ac_rtim_sl_thold_7), + .func_sl_thold_7(an_ac_func_sl_thold_7), + .func_nsl_thold_7(an_ac_func_nsl_thold_7), + .ary_nsl_thold_7(an_ac_ary_nsl_thold_7), + .sg_7(an_ac_sg_7), + .fce_7(an_ac_fce_7), + .gsd_test_enable_dc(an_ac_gsd_test_enable_dc), + .gsd_test_acmode_dc(an_ac_gsd_test_acmode_dc), + .ccflush_dc(an_ac_ccflush_dc), + .ccenable_dc(an_ac_ccenable_dc), + .scan_type_dc(an_ac_scan_type_dc), + .lbist_en_dc(an_ac_lbist_en_dc), + .lbist_ip_dc(an_ac_lbist_ip_dc), + .rg_ck_fast_xstop(rg_ck_fast_xstop), + .ct_ck_pm_ccflush_disable(ct_ck_pm_ccflush_disable), + .ct_ck_pm_raise_tholds(ct_ck_pm_raise_tholds), + // --Thold outputs to the units + .pc_pc_ccflush_out_dc(pc_rp_ccflush_out_dc), + .pc_pc_gptr_sl_thold_4(pc_rp_gptr_sl_thold_4), + .pc_pc_time_sl_thold_4(pc_rp_time_sl_thold_4), + .pc_pc_repr_sl_thold_4(pc_rp_repr_sl_thold_4), + .pc_pc_abst_sl_thold_4(pc_rp_abst_sl_thold_4), + .pc_pc_abst_slp_sl_thold_4(pc_rp_abst_slp_sl_thold_4), + .pc_pc_regf_sl_thold_4(pc_rp_regf_sl_thold_4), + .pc_pc_regf_slp_sl_thold_4(pc_rp_regf_slp_sl_thold_4), + .pc_pc_func_sl_thold_4(pc_rp_func_sl_thold_4), + .pc_pc_func_slp_sl_thold_4(pc_rp_func_slp_sl_thold_4), + .pc_pc_cfg_sl_thold_4(pc_rp_cfg_sl_thold_4), + .pc_pc_cfg_slp_sl_thold_4(pc_rp_cfg_slp_sl_thold_4), + .pc_pc_func_nsl_thold_4(pc_rp_func_nsl_thold_4), + .pc_pc_func_slp_nsl_thold_4(pc_rp_func_slp_nsl_thold_4), + .pc_pc_ary_nsl_thold_4(pc_rp_ary_nsl_thold_4), + .pc_pc_ary_slp_nsl_thold_4(pc_rp_ary_slp_nsl_thold_4), + .pc_pc_rtim_sl_thold_4(pc_rp_rtim_sl_thold_4), + .pc_pc_sg_4(pc_rp_sg_4), + .pc_pc_fce_4(pc_rp_fce_4), + .pc_fu_ccflush_dc(pc_fu_ccflush_dc), + .pc_fu_gptr_sl_thold_3(pc_fu_gptr_sl_thold_3), + .pc_fu_time_sl_thold_3(pc_fu_time_sl_thold_3), + .pc_fu_repr_sl_thold_3(pc_fu_repr_sl_thold_3), + .pc_fu_abst_sl_thold_3(pc_fu_abst_sl_thold_3), + .pc_fu_abst_slp_sl_thold_3(pc_fu_abst_slp_sl_thold_3), + .pc_fu_func_sl_thold_3(pc_fu_func_sl_thold_3), + .pc_fu_func_slp_sl_thold_3(pc_fu_func_slp_sl_thold_3), + .pc_fu_cfg_sl_thold_3(pc_fu_cfg_sl_thold_3), + .pc_fu_cfg_slp_sl_thold_3(pc_fu_cfg_slp_sl_thold_3), + .pc_fu_func_nsl_thold_3(pc_fu_func_nsl_thold_3), + .pc_fu_func_slp_nsl_thold_3(pc_fu_func_slp_nsl_thold_3), + .pc_fu_ary_nsl_thold_3(pc_fu_ary_nsl_thold_3), + .pc_fu_ary_slp_nsl_thold_3(pc_fu_ary_slp_nsl_thold_3), + .pc_fu_sg_3(pc_fu_sg_3), + .pc_fu_fce_3(pc_fu_fce_3), + .pc_pc_ccflush_dc(pc_pc_ccflush_dc), + .pc_pc_gptr_sl_thold_0(pc_pc_gptr_sl_thold_0), + .pc_pc_func_sl_thold_0(pc_pc_func_sl_thold_0), + .pc_pc_func_slp_sl_thold_0(pc_pc_func_slp_sl_thold_0), + .pc_pc_cfg_sl_thold_0(pc_pc_cfg_sl_thold_0), + .pc_pc_cfg_slp_sl_thold_0(pc_pc_cfg_slp_sl_thold_0), + .pc_pc_sg_0(pc_pc_sg_0) + ); + + +//===================================================================== +// LCBCNTL Macro +//===================================================================== + tri_lcbcntl_mac lcbctrl( + .vdd(vdd), + .gnd(gnd), + .sg(pc_pc_sg_0), + .nclk(nclk), + .scan_in(gptr_scan_in), + .scan_diag_dc(an_ac_scan_diag_dc), + .thold(pc_pc_gptr_sl_thold_0), + .clkoff_dc_b(clkoff_dc_b), + .delay_lclkr_dc(delay_lclkr_dc[0:4]), + .act_dis_dc(), + .d_mode_dc(d_mode_dc), + .mpw1_dc_b(mpw1_dc_b[0:4]), + .mpw2_dc_b(mpw2_dc_b), + .scan_out(lcbctrl_gptr_scan_out) + ); + + // Forcing act_dis pin on all tri_lcbor components to 0. + // Using logic signal connected to LCB ACT pin to control if latch held or updated. + assign act_dis_dc = 1'b0; + + +endmodule diff --git a/dev/verilog/work/pcq_clks.v b/dev/verilog/work/pcq_clks.v new file mode 100755 index 0000000..68ca9e0 --- /dev/null +++ b/dev/verilog/work/pcq_clks.v @@ -0,0 +1,271 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +// +// Description: Pervasive Core LCB Controls +// +//***************************************************************************** + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" + +module pcq_clks( +// Include model build parameters +`include "tri_a2o.vh" + + inout vdd, + inout gnd, + input [0:`NCLK_WIDTH-1] nclk, + input rtim_sl_thold_7, + input func_sl_thold_7, + input func_nsl_thold_7, + input ary_nsl_thold_7, + input sg_7, + input fce_7, + input gsd_test_enable_dc, + input gsd_test_acmode_dc, + input ccflush_dc, + input ccenable_dc, + input lbist_en_dc, + input lbist_ip_dc, + input rg_ck_fast_xstop, + input ct_ck_pm_ccflush_disable, + input ct_ck_pm_raise_tholds, + input [0:8] scan_type_dc, + // --Thold + control outputs to the units + output pc_pc_ccflush_out_dc, + output pc_pc_gptr_sl_thold_4, + output pc_pc_time_sl_thold_4, + output pc_pc_repr_sl_thold_4, + output pc_pc_abst_sl_thold_4, + output pc_pc_abst_slp_sl_thold_4, + output pc_pc_regf_sl_thold_4, + output pc_pc_regf_slp_sl_thold_4, + output pc_pc_func_sl_thold_4, + output pc_pc_func_slp_sl_thold_4, + output pc_pc_cfg_sl_thold_4, + output pc_pc_cfg_slp_sl_thold_4, + output pc_pc_func_nsl_thold_4, + output pc_pc_func_slp_nsl_thold_4, + output pc_pc_ary_nsl_thold_4, + output pc_pc_ary_slp_nsl_thold_4, + output pc_pc_rtim_sl_thold_4, + output pc_pc_sg_4, + output pc_pc_fce_4, + // Thold + control signals used by fu + output pc_fu_ccflush_dc, + output pc_fu_gptr_sl_thold_3, + output pc_fu_time_sl_thold_3, + output pc_fu_repr_sl_thold_3, + output pc_fu_abst_sl_thold_3, + output pc_fu_abst_slp_sl_thold_3, + output [0:1] pc_fu_func_sl_thold_3, + output [0:1] pc_fu_func_slp_sl_thold_3, + output pc_fu_cfg_sl_thold_3, + output pc_fu_cfg_slp_sl_thold_3, + output pc_fu_func_nsl_thold_3, + output pc_fu_func_slp_nsl_thold_3, + output pc_fu_ary_nsl_thold_3, + output pc_fu_ary_slp_nsl_thold_3, + output [0:1] pc_fu_sg_3, + output pc_fu_fce_3, + // Thold + control signals used in pcq + output pc_pc_ccflush_dc, + output pc_pc_gptr_sl_thold_0, + output pc_pc_func_sl_thold_0, + output pc_pc_func_slp_sl_thold_0, + output pc_pc_cfg_sl_thold_0, + output pc_pc_cfg_slp_sl_thold_0, + output pc_pc_sg_0 +); + + +//===================================================================== +// Signal Declarations +//===================================================================== + wire rtim_sl_thold_6; + wire func_sl_thold_6; + wire func_nsl_thold_6; + wire ary_nsl_thold_6; + wire sg_6; + wire fce_6; + wire ccflush_out_dc; + wire gptr_sl_thold_5; + wire time_sl_thold_5; + wire repr_sl_thold_5; + wire abst_sl_thold_5; + wire abst_slp_sl_thold_5; + wire regf_sl_thold_5; + wire regf_slp_sl_thold_5; + wire func_sl_thold_5; + wire func_slp_sl_thold_5; + wire cfg_sl_thold_5; + wire cfg_slp_sl_thold_5; + wire func_nsl_thold_5; + wire func_slp_nsl_thold_5; + wire ary_nsl_thold_5; + wire ary_slp_nsl_thold_5; + wire rtim_sl_thold_5; + wire sg_5; + wire fce_5; + + +//===================================================================== +// Clock Control and Staging Logic +//===================================================================== + pcq_clks_ctrl clkctrl( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .rtim_sl_thold_6(rtim_sl_thold_6), + .func_sl_thold_6(func_sl_thold_6), + .func_nsl_thold_6(func_nsl_thold_6), + .ary_nsl_thold_6(ary_nsl_thold_6), + .sg_6(sg_6), + .fce_6(fce_6), + .gsd_test_enable_dc(gsd_test_enable_dc), + .gsd_test_acmode_dc(gsd_test_acmode_dc), + .ccflush_dc(ccflush_dc), + .ccenable_dc(ccenable_dc), + .scan_type_dc(scan_type_dc), + .lbist_en_dc(lbist_en_dc), + .lbist_ip_dc(lbist_ip_dc), + .rg_ck_fast_xstop(rg_ck_fast_xstop), + .ct_ck_pm_ccflush_disable(ct_ck_pm_ccflush_disable), + .ct_ck_pm_raise_tholds(ct_ck_pm_raise_tholds), + // --Thold + control outputs to the units + .ccflush_out_dc(ccflush_out_dc), + .gptr_sl_thold_5(gptr_sl_thold_5), + .time_sl_thold_5(time_sl_thold_5), + .repr_sl_thold_5(repr_sl_thold_5), + .cfg_sl_thold_5(cfg_sl_thold_5), + .cfg_slp_sl_thold_5(cfg_slp_sl_thold_5), + .abst_sl_thold_5(abst_sl_thold_5), + .abst_slp_sl_thold_5(abst_slp_sl_thold_5), + .regf_sl_thold_5(regf_sl_thold_5), + .regf_slp_sl_thold_5(regf_slp_sl_thold_5), + .func_sl_thold_5(func_sl_thold_5), + .func_slp_sl_thold_5(func_slp_sl_thold_5), + .func_nsl_thold_5(func_nsl_thold_5), + .func_slp_nsl_thold_5(func_slp_nsl_thold_5), + .ary_nsl_thold_5(ary_nsl_thold_5), + .ary_slp_nsl_thold_5(ary_slp_nsl_thold_5), + .rtim_sl_thold_5(rtim_sl_thold_5), + .sg_5(sg_5), + .fce_5(fce_5) + ); + + + pcq_clks_stg clkstg( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .ccflush_out_dc(ccflush_out_dc), + .gptr_sl_thold_5(gptr_sl_thold_5), + .time_sl_thold_5(time_sl_thold_5), + .repr_sl_thold_5(repr_sl_thold_5), + .cfg_sl_thold_5(cfg_sl_thold_5), + .cfg_slp_sl_thold_5(cfg_slp_sl_thold_5), + .abst_sl_thold_5(abst_sl_thold_5), + .abst_slp_sl_thold_5(abst_slp_sl_thold_5), + .regf_sl_thold_5(regf_sl_thold_5), + .regf_slp_sl_thold_5(regf_slp_sl_thold_5), + .func_sl_thold_5(func_sl_thold_5), + .func_slp_sl_thold_5(func_slp_sl_thold_5), + .func_nsl_thold_5(func_nsl_thold_5), + .func_slp_nsl_thold_5(func_slp_nsl_thold_5), + .ary_nsl_thold_5(ary_nsl_thold_5), + .ary_slp_nsl_thold_5(ary_slp_nsl_thold_5), + .rtim_sl_thold_5(rtim_sl_thold_5), + .sg_5(sg_5), + .fce_5(fce_5), + // Thold + control outputs to the units + .pc_pc_ccflush_out_dc(pc_pc_ccflush_out_dc), + .pc_pc_gptr_sl_thold_4(pc_pc_gptr_sl_thold_4), + .pc_pc_time_sl_thold_4(pc_pc_time_sl_thold_4), + .pc_pc_repr_sl_thold_4(pc_pc_repr_sl_thold_4), + .pc_pc_abst_sl_thold_4(pc_pc_abst_sl_thold_4), + .pc_pc_abst_slp_sl_thold_4(pc_pc_abst_slp_sl_thold_4), + .pc_pc_regf_sl_thold_4(pc_pc_regf_sl_thold_4), + .pc_pc_regf_slp_sl_thold_4(pc_pc_regf_slp_sl_thold_4), + .pc_pc_func_sl_thold_4(pc_pc_func_sl_thold_4), + .pc_pc_func_slp_sl_thold_4(pc_pc_func_slp_sl_thold_4), + .pc_pc_cfg_sl_thold_4(pc_pc_cfg_sl_thold_4), + .pc_pc_cfg_slp_sl_thold_4(pc_pc_cfg_slp_sl_thold_4), + .pc_pc_func_nsl_thold_4(pc_pc_func_nsl_thold_4), + .pc_pc_func_slp_nsl_thold_4(pc_pc_func_slp_nsl_thold_4), + .pc_pc_ary_nsl_thold_4(pc_pc_ary_nsl_thold_4), + .pc_pc_ary_slp_nsl_thold_4(pc_pc_ary_slp_nsl_thold_4), + .pc_pc_rtim_sl_thold_4(pc_pc_rtim_sl_thold_4), + .pc_pc_sg_4(pc_pc_sg_4), + .pc_pc_fce_4(pc_pc_fce_4), + // Thold + control signals used by fu + .pc_fu_ccflush_dc(pc_fu_ccflush_dc), + .pc_fu_gptr_sl_thold_3(pc_fu_gptr_sl_thold_3), + .pc_fu_time_sl_thold_3(pc_fu_time_sl_thold_3), + .pc_fu_repr_sl_thold_3(pc_fu_repr_sl_thold_3), + .pc_fu_abst_sl_thold_3(pc_fu_abst_sl_thold_3), + .pc_fu_abst_slp_sl_thold_3(pc_fu_abst_slp_sl_thold_3), + .pc_fu_func_sl_thold_3(pc_fu_func_sl_thold_3), + .pc_fu_func_slp_sl_thold_3(pc_fu_func_slp_sl_thold_3), + .pc_fu_cfg_sl_thold_3(pc_fu_cfg_sl_thold_3), + .pc_fu_cfg_slp_sl_thold_3(pc_fu_cfg_slp_sl_thold_3), + .pc_fu_func_nsl_thold_3(pc_fu_func_nsl_thold_3), + .pc_fu_func_slp_nsl_thold_3(pc_fu_func_slp_nsl_thold_3), + .pc_fu_ary_nsl_thold_3(pc_fu_ary_nsl_thold_3), + .pc_fu_ary_slp_nsl_thold_3(pc_fu_ary_slp_nsl_thold_3), + .pc_fu_sg_3(pc_fu_sg_3), + .pc_fu_fce_3(pc_fu_fce_3), + // PC Unit thold + control signals + .pc_pc_ccflush_dc(pc_pc_ccflush_dc), + .pc_pc_gptr_sl_thold_0(pc_pc_gptr_sl_thold_0), + .pc_pc_func_sl_thold_0(pc_pc_func_sl_thold_0), + .pc_pc_func_slp_sl_thold_0(pc_pc_func_slp_sl_thold_0), + .pc_pc_cfg_sl_thold_0(pc_pc_cfg_sl_thold_0), + .pc_pc_cfg_slp_sl_thold_0(pc_pc_cfg_slp_sl_thold_0), + .pc_pc_sg_0(pc_pc_sg_0) + ); + + + + tri_plat #(.WIDTH(6)) lvl7to6_plat( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(ccflush_dc), + + .din({rtim_sl_thold_7, func_sl_thold_7, func_nsl_thold_7, + ary_nsl_thold_7, sg_7, fce_7}), + + .q( {rtim_sl_thold_6, func_sl_thold_6, func_nsl_thold_6, + ary_nsl_thold_6, sg_6, fce_6}) + ); + + +endmodule diff --git a/dev/verilog/work/pcq_clks_ctrl.v b/dev/verilog/work/pcq_clks_ctrl.v new file mode 100755 index 0000000..239fd00 --- /dev/null +++ b/dev/verilog/work/pcq_clks_ctrl.v @@ -0,0 +1,245 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +// +// Description: Pervasive Core LCB Control Component +// +//***************************************************************************** + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" + +module pcq_clks_ctrl( +// Include model build parameters +`include "tri_a2o.vh" + + inout vdd, + inout gnd, + input [0:`NCLK_WIDTH-1] nclk, + input rtim_sl_thold_6, + input func_sl_thold_6, + input func_nsl_thold_6, + input ary_nsl_thold_6, + input sg_6, + input fce_6, + input gsd_test_enable_dc, + input gsd_test_acmode_dc, + input ccflush_dc, + input ccenable_dc, + input lbist_en_dc, + input lbist_ip_dc, + input rg_ck_fast_xstop, + input ct_ck_pm_ccflush_disable, + input ct_ck_pm_raise_tholds, + input [0:8] scan_type_dc, + // --Thold + control outputs to the units + output ccflush_out_dc, + output gptr_sl_thold_5, + output time_sl_thold_5, + output repr_sl_thold_5, + output cfg_sl_thold_5, + output cfg_slp_sl_thold_5, + output abst_sl_thold_5, + output abst_slp_sl_thold_5, + output regf_sl_thold_5, + output regf_slp_sl_thold_5, + output func_sl_thold_5, + output func_slp_sl_thold_5, + output func_nsl_thold_5, + output func_slp_nsl_thold_5, + output ary_nsl_thold_5, + output ary_slp_nsl_thold_5, + output rtim_sl_thold_5, + output sg_5, + output fce_5 +); + + +//===================================================================== +// Signal Declarations +//===================================================================== + + // Scan ring select decodes for scan_type_dc vector + parameter SCANTYPE_SIZE = 9; // Use bits 0:8 of scan_type vector + + parameter SCANTYPE_FUNC = 0; + parameter SCANTYPE_MODE = 1; + parameter SCANTYPE_CCFG = 2; + parameter SCANTYPE_GPTR = 2; + parameter SCANTYPE_REGF = 3; + parameter SCANTYPE_FUSE = 3; + parameter SCANTYPE_LBST = 4; + parameter SCANTYPE_ABST = 5; + parameter SCANTYPE_REPR = 6; + parameter SCANTYPE_TIME = 7; + parameter SCANTYPE_BNDY = 8; + parameter SCANTYPE_FARY = 9; + + wire fast_xstop_gated_staged; + wire fce_in; + wire sg_in; + wire ary_nsl_thold; + wire func_nsl_thold; + wire rtim_sl_thold; + wire func_sl_thold; + wire gptr_sl_thold_in; + wire time_sl_thold_in; + wire repr_sl_thold_in; + wire rtim_sl_thold_in; + wire cfg_run_sl_thold_in; + wire cfg_slp_sl_thold_in; + wire abst_run_sl_thold_in; + wire abst_slp_sl_thold_in; + wire regf_run_sl_thold_in; + wire regf_slp_sl_thold_in; + wire func_run_sl_thold_in; + wire func_slp_sl_thold_in; + wire func_run_nsl_thold_in; + wire func_slp_nsl_thold_in; + wire ary_run_nsl_thold_in; + wire ary_slp_nsl_thold_in; + wire pm_ccflush_disable_dc; + wire ccflush_out_dc_int; + wire testdc; + wire thold_overide_ctrl; + wire [0:SCANTYPE_SIZE-1] scan_type_b; + +(* analysis_not_referenced="true" *) + wire unused_signals; + assign unused_signals = (scan_type_b[2] | scan_type_b[4] | (|scan_type_b[6:8]) | lbist_ip_dc); + + +//!! Bugspray Include: pcq_clks_ctrl; + + +//===================================================================== +// Clock Control Logic +//===================================================================== + // detect test dc mode + assign testdc = gsd_test_enable_dc & (~gsd_test_acmode_dc); + + // enable sg/fce before latching + assign sg_in = sg_6 & ccenable_dc; + assign fce_in = fce_6 & ccenable_dc; + + // scan chain type + assign scan_type_b = ({SCANTYPE_SIZE {sg_in}} & (~scan_type_dc)); + + // setup for xx_thold_6 inputs + assign thold_overide_ctrl = fast_xstop_gated_staged & (~sg_in) & (~lbist_en_dc) & (~gsd_test_enable_dc); + + assign rtim_sl_thold = rtim_sl_thold_6; + assign func_sl_thold = func_sl_thold_6 | thold_overide_ctrl; + assign func_nsl_thold = func_nsl_thold_6 | thold_overide_ctrl; + assign ary_nsl_thold = ary_nsl_thold_6 | thold_overide_ctrl; + + // setup for plat flush control signals + // Active when power_management enabled (PM_Sleep_enable or PM_RVW_enable active) + // If plats were in flush mode, forces plats to be clocked again for power-savings. + assign pm_ccflush_disable_dc = ct_ck_pm_ccflush_disable; + + assign ccflush_out_dc_int = ccflush_dc & ((~pm_ccflush_disable_dc) | lbist_en_dc | testdc); + assign ccflush_out_dc = ccflush_out_dc_int; + + + // OR and MUX of thold signals + // scan only: stop if not scanning, not part of LBIST, hence no sg_in here + assign gptr_sl_thold_in = func_sl_thold | (~scan_type_dc[SCANTYPE_GPTR]) | (~ccenable_dc); + + // scan only: stop if not scanning, not part of LBIST, hence no sg_in here + assign time_sl_thold_in = func_sl_thold | (~scan_type_dc[SCANTYPE_TIME]) | (~ccenable_dc); + + // scan only: stop if not scanning, not part of LBIST, hence no sg_in here + assign repr_sl_thold_in = func_sl_thold | (~scan_type_dc[SCANTYPE_REPR]) | (~ccenable_dc); + + assign cfg_run_sl_thold_in = func_sl_thold | scan_type_b[SCANTYPE_MODE] | (ct_ck_pm_raise_tholds & (~sg_in) & (~lbist_en_dc) & (~gsd_test_enable_dc)); + + assign cfg_slp_sl_thold_in = func_sl_thold | scan_type_b[SCANTYPE_MODE]; + + assign abst_run_sl_thold_in = func_sl_thold | scan_type_b[SCANTYPE_ABST] | (ct_ck_pm_raise_tholds & (~sg_in) & (~lbist_en_dc) & (~gsd_test_enable_dc)); + + assign abst_slp_sl_thold_in = func_sl_thold | scan_type_b[SCANTYPE_ABST]; + + assign regf_run_sl_thold_in = func_sl_thold | scan_type_b[SCANTYPE_REGF] | (ct_ck_pm_raise_tholds & (~sg_in) & (~lbist_en_dc) & (~gsd_test_enable_dc)); + + assign regf_slp_sl_thold_in = func_sl_thold | scan_type_b[SCANTYPE_REGF]; + + assign func_run_sl_thold_in = func_sl_thold | scan_type_b[SCANTYPE_FUNC] | (ct_ck_pm_raise_tholds & (~sg_in) & (~lbist_en_dc) & (~gsd_test_enable_dc)); + + assign func_slp_sl_thold_in = func_sl_thold | scan_type_b[SCANTYPE_FUNC]; + + assign func_run_nsl_thold_in = func_nsl_thold | (ct_ck_pm_raise_tholds & (~fce_in) & (~lbist_en_dc) & (~gsd_test_enable_dc)); + + assign func_slp_nsl_thold_in = func_nsl_thold; + + assign ary_run_nsl_thold_in = ary_nsl_thold | (ct_ck_pm_raise_tholds & (~fce_in) & (~lbist_en_dc) & (~gsd_test_enable_dc)); + + assign ary_slp_nsl_thold_in = ary_nsl_thold; + + assign rtim_sl_thold_in = rtim_sl_thold; + + + // PLAT staging/redrive + tri_plat #(.WIDTH(1)) fast_stop_staging( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(ccflush_out_dc_int), + .din(rg_ck_fast_xstop), + .q(fast_xstop_gated_staged) + ); + + tri_plat #(.WIDTH(2)) sg_fce_plat( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(ccflush_out_dc_int), + .din({sg_in, fce_in}), + .q ({sg_5, fce_5 }) + ); + + tri_plat #(.WIDTH(16)) thold_plat( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(ccflush_out_dc_int), + + .din({gptr_sl_thold_in, time_sl_thold_in, repr_sl_thold_in, cfg_run_sl_thold_in, + cfg_slp_sl_thold_in, abst_run_sl_thold_in, abst_slp_sl_thold_in, regf_run_sl_thold_in, + regf_slp_sl_thold_in, func_run_sl_thold_in, func_slp_sl_thold_in, func_run_nsl_thold_in, + func_slp_nsl_thold_in, ary_run_nsl_thold_in, ary_slp_nsl_thold_in, rtim_sl_thold_in}), + + .q ({gptr_sl_thold_5, time_sl_thold_5, repr_sl_thold_5, cfg_sl_thold_5, + cfg_slp_sl_thold_5, abst_sl_thold_5, abst_slp_sl_thold_5, regf_sl_thold_5, + regf_slp_sl_thold_5, func_sl_thold_5, func_slp_sl_thold_5, func_nsl_thold_5, + func_slp_nsl_thold_5, ary_nsl_thold_5, ary_slp_nsl_thold_5, rtim_sl_thold_5}) + ); + + +endmodule diff --git a/dev/verilog/work/pcq_clks_stg.v b/dev/verilog/work/pcq_clks_stg.v new file mode 100755 index 0000000..16b3eb5 --- /dev/null +++ b/dev/verilog/work/pcq_clks_stg.v @@ -0,0 +1,431 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +// +// Description: Pervasive Core LCB Staging +// +//***************************************************************************** + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" + +module pcq_clks_stg( +// Include model build parameters +`include "tri_a2o.vh" + + inout vdd, + inout gnd, + input [0:`NCLK_WIDTH-1] nclk, + input ccflush_out_dc, + input gptr_sl_thold_5, + input time_sl_thold_5, + input repr_sl_thold_5, + input cfg_sl_thold_5, + input cfg_slp_sl_thold_5, + input abst_sl_thold_5, + input abst_slp_sl_thold_5, + input regf_sl_thold_5, + input regf_slp_sl_thold_5, + input func_sl_thold_5, + input func_slp_sl_thold_5, + input func_nsl_thold_5, + input func_slp_nsl_thold_5, + input ary_nsl_thold_5, + input ary_slp_nsl_thold_5, + input rtim_sl_thold_5, + input sg_5, + input fce_5, + // Thold + control outputs to the units + output pc_pc_ccflush_out_dc, + output pc_pc_gptr_sl_thold_4, + output pc_pc_time_sl_thold_4, + output pc_pc_repr_sl_thold_4, + output pc_pc_abst_sl_thold_4, + output pc_pc_abst_slp_sl_thold_4, + output pc_pc_regf_sl_thold_4, + output pc_pc_regf_slp_sl_thold_4, + output pc_pc_func_sl_thold_4, + output pc_pc_func_slp_sl_thold_4, + output pc_pc_cfg_sl_thold_4, + output pc_pc_cfg_slp_sl_thold_4, + output pc_pc_func_nsl_thold_4, + output pc_pc_func_slp_nsl_thold_4, + output pc_pc_ary_nsl_thold_4, + output pc_pc_ary_slp_nsl_thold_4, + output pc_pc_rtim_sl_thold_4, + output pc_pc_sg_4, + output pc_pc_fce_4, + // Thold + control signals used by fu + output pc_fu_ccflush_dc, + output pc_fu_gptr_sl_thold_3, + output pc_fu_time_sl_thold_3, + output pc_fu_repr_sl_thold_3, + output pc_fu_abst_sl_thold_3, + output pc_fu_abst_slp_sl_thold_3, + output [0:1] pc_fu_func_sl_thold_3, + output [0:1] pc_fu_func_slp_sl_thold_3, + output pc_fu_cfg_sl_thold_3, + output pc_fu_cfg_slp_sl_thold_3, + output pc_fu_func_nsl_thold_3, + output pc_fu_func_slp_nsl_thold_3, + output pc_fu_ary_nsl_thold_3, + output pc_fu_ary_slp_nsl_thold_3, + output [0:1] pc_fu_sg_3, + output pc_fu_fce_3, + // Thold + control signals used in pcq + output pc_pc_ccflush_dc, + output pc_pc_gptr_sl_thold_0, + output pc_pc_func_sl_thold_0, + output pc_pc_func_slp_sl_thold_0, + output pc_pc_cfg_sl_thold_0, + output pc_pc_cfg_slp_sl_thold_0, + output pc_pc_sg_0 +); + + +//===================================================================== +// Signal Declarations +//===================================================================== + wire pc_pc_gptr_sl_thold_4_int; + wire pc_pc_time_sl_thold_4_int; + wire pc_pc_repr_sl_thold_4_int; + wire pc_pc_abst_sl_thold_4_int; + wire pc_pc_abst_slp_sl_thold_4_int; + wire pc_pc_regf_sl_thold_4_int; + wire pc_pc_regf_slp_sl_thold_4_int; + wire pc_pc_func_sl_thold_4_int; + wire pc_pc_func_slp_sl_thold_4_int; + wire pc_pc_cfg_sl_thold_4_int; + wire pc_pc_cfg_slp_sl_thold_4_int; + wire pc_pc_func_nsl_thold_4_int; + wire pc_pc_func_slp_nsl_thold_4_int; + wire pc_pc_ary_nsl_thold_4_int; + wire pc_pc_ary_slp_nsl_thold_4_int; + wire pc_pc_rtim_sl_thold_4_int; + wire pc_pc_sg_4_int; + wire pc_pc_fce_4_int; + + wire pc_pc_gptr_sl_thold_3; + wire pc_pc_abst_sl_thold_3; + wire pc_pc_func_sl_thold_3; + wire pc_pc_func_slp_sl_thold_3; + wire pc_pc_cfg_slp_sl_thold_3; + wire pc_pc_cfg_sl_thold_3; + wire pc_pc_sg_3; + wire pc_pc_gptr_sl_thold_2; + wire pc_pc_abst_sl_thold_2; + wire pc_pc_func_sl_thold_2; + wire pc_pc_func_slp_sl_thold_2; + wire pc_pc_cfg_slp_sl_thold_2; + wire pc_pc_cfg_sl_thold_2; + wire pc_pc_sg_2; + wire pc_pc_gptr_sl_thold_1; + wire pc_pc_abst_sl_thold_1; + wire pc_pc_func_sl_thold_1; + wire pc_pc_func_slp_sl_thold_1; + wire pc_pc_cfg_slp_sl_thold_1; + wire pc_pc_cfg_sl_thold_1; + wire pc_pc_sg_1; + + +//===================================================================== +// LCB control signals staged/redriven to other units +//===================================================================== + assign pc_pc_ccflush_out_dc = ccflush_out_dc; + assign pc_pc_ccflush_dc = ccflush_out_dc; + assign pc_fu_ccflush_dc = ccflush_out_dc; + + + // Start of thold/SG/FCE staging (level 5 to level 3) + tri_plat #(.WIDTH(18)) lvl5to4_plat( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(ccflush_out_dc), + + .din({gptr_sl_thold_5, time_sl_thold_5, repr_sl_thold_5, + rtim_sl_thold_5, abst_sl_thold_5, abst_slp_sl_thold_5, + regf_sl_thold_5, regf_slp_sl_thold_5, func_sl_thold_5, + func_slp_sl_thold_5, cfg_sl_thold_5, cfg_slp_sl_thold_5, + func_nsl_thold_5, func_slp_nsl_thold_5, ary_nsl_thold_5, + ary_slp_nsl_thold_5, sg_5, fce_5}), + + .q( {pc_pc_gptr_sl_thold_4_int, pc_pc_time_sl_thold_4_int, pc_pc_repr_sl_thold_4_int, + pc_pc_rtim_sl_thold_4_int, pc_pc_abst_sl_thold_4_int, pc_pc_abst_slp_sl_thold_4_int, + pc_pc_regf_sl_thold_4_int, pc_pc_regf_slp_sl_thold_4_int, pc_pc_func_sl_thold_4_int, + pc_pc_func_slp_sl_thold_4_int, pc_pc_cfg_sl_thold_4_int, pc_pc_cfg_slp_sl_thold_4_int, + pc_pc_func_nsl_thold_4_int, pc_pc_func_slp_nsl_thold_4_int, pc_pc_ary_nsl_thold_4_int, + pc_pc_ary_slp_nsl_thold_4_int, pc_pc_sg_4_int, pc_pc_fce_4_int}) + ); + + + // Level 4 staging goes to the pervasive repower logic + assign pc_pc_gptr_sl_thold_4 = pc_pc_gptr_sl_thold_4_int; + assign pc_pc_time_sl_thold_4 = pc_pc_time_sl_thold_4_int; + assign pc_pc_repr_sl_thold_4 = pc_pc_repr_sl_thold_4_int; + assign pc_pc_abst_sl_thold_4 = pc_pc_abst_sl_thold_4_int; + assign pc_pc_abst_slp_sl_thold_4 = pc_pc_abst_slp_sl_thold_4_int; + assign pc_pc_regf_sl_thold_4 = pc_pc_regf_sl_thold_4_int; + assign pc_pc_regf_slp_sl_thold_4 = pc_pc_regf_slp_sl_thold_4_int; + assign pc_pc_func_sl_thold_4 = pc_pc_func_sl_thold_4_int; + assign pc_pc_func_slp_sl_thold_4 = pc_pc_func_slp_sl_thold_4_int; + assign pc_pc_cfg_sl_thold_4 = pc_pc_cfg_sl_thold_4_int; + assign pc_pc_cfg_slp_sl_thold_4 = pc_pc_cfg_slp_sl_thold_4_int; + assign pc_pc_func_nsl_thold_4 = pc_pc_func_nsl_thold_4_int; + assign pc_pc_func_slp_nsl_thold_4 = pc_pc_func_slp_nsl_thold_4_int; + assign pc_pc_ary_nsl_thold_4 = pc_pc_ary_nsl_thold_4_int; + assign pc_pc_ary_slp_nsl_thold_4 = pc_pc_ary_slp_nsl_thold_4_int; + assign pc_pc_rtim_sl_thold_4 = pc_pc_rtim_sl_thold_4_int; + assign pc_pc_sg_4 = pc_pc_sg_4_int; + assign pc_pc_fce_4 = pc_pc_fce_4_int; + + + // FU clock control staging: level 4 to 3 + tri_plat #(.WIDTH(18)) fu_clkstg_4to3( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(ccflush_out_dc), + + .din({pc_pc_gptr_sl_thold_4_int, pc_pc_time_sl_thold_4_int, pc_pc_repr_sl_thold_4_int, + pc_pc_abst_sl_thold_4_int, pc_pc_abst_slp_sl_thold_4_int, pc_pc_func_sl_thold_4_int, + pc_pc_func_sl_thold_4_int, pc_pc_func_slp_sl_thold_4_int, pc_pc_func_slp_sl_thold_4_int, + pc_pc_cfg_sl_thold_4_int, pc_pc_cfg_slp_sl_thold_4_int, pc_pc_func_nsl_thold_4_int, + pc_pc_func_slp_nsl_thold_4_int, pc_pc_ary_nsl_thold_4_int, pc_pc_ary_slp_nsl_thold_4_int, + pc_pc_sg_4_int, pc_pc_sg_4_int, pc_pc_fce_4_int }), + + .q( {pc_fu_gptr_sl_thold_3, pc_fu_time_sl_thold_3, pc_fu_repr_sl_thold_3, + pc_fu_abst_sl_thold_3, pc_fu_abst_slp_sl_thold_3, pc_fu_func_sl_thold_3[0], + pc_fu_func_sl_thold_3[1], pc_fu_func_slp_sl_thold_3[0], pc_fu_func_slp_sl_thold_3[1], + pc_fu_cfg_sl_thold_3, pc_fu_cfg_slp_sl_thold_3, pc_fu_func_nsl_thold_3, + pc_fu_func_slp_nsl_thold_3, pc_fu_ary_nsl_thold_3, pc_fu_ary_slp_nsl_thold_3, + pc_fu_sg_3[0], pc_fu_sg_3[1], pc_fu_fce_3 }) + ); + + + // PC clock control staging: level 4 to 3 + tri_plat #(.WIDTH(6)) pc_lvl4to3( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(ccflush_out_dc), + + .din({pc_pc_func_sl_thold_4_int, pc_pc_func_slp_sl_thold_4_int, pc_pc_cfg_sl_thold_4_int, + pc_pc_cfg_slp_sl_thold_4_int, pc_pc_gptr_sl_thold_4_int, pc_pc_sg_4_int}), + + .q( {pc_pc_func_sl_thold_3, pc_pc_func_slp_sl_thold_3, pc_pc_cfg_sl_thold_3, + pc_pc_cfg_slp_sl_thold_3, pc_pc_gptr_sl_thold_3, pc_pc_sg_3}) + ); + // End of thold/SG/FCE staging (level 5 to level 3) + +//===================================================================== +// thold/SG staging (level 3 to level 0) for PC units +//===================================================================== + //---------------------------------------------------- + // FUNC (RUN) + //---------------------------------------------------- + tri_plat #(.WIDTH(1)) func_3_2( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(ccflush_out_dc), + .din(pc_pc_func_sl_thold_3), + .q(pc_pc_func_sl_thold_2) + ); + + tri_plat #(.WIDTH(1)) func_2_1( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(ccflush_out_dc), + .din(pc_pc_func_sl_thold_2), + .q(pc_pc_func_sl_thold_1) + ); + + tri_plat #(.WIDTH(1)) func_1_0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(ccflush_out_dc), + .din(pc_pc_func_sl_thold_1), + .q(pc_pc_func_sl_thold_0) + ); + + //---------------------------------------------------- + // FUNC (SLEEP) + //---------------------------------------------------- + tri_plat #(.WIDTH(1)) func_slp_3_2( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(ccflush_out_dc), + .din(pc_pc_func_slp_sl_thold_3), + .q(pc_pc_func_slp_sl_thold_2) + ); + + tri_plat #(.WIDTH(1)) func_slp_2_1( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(ccflush_out_dc), + .din(pc_pc_func_slp_sl_thold_2), + .q(pc_pc_func_slp_sl_thold_1) + ); + + tri_plat #(.WIDTH(1)) func_slp_1_0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(ccflush_out_dc), + .din(pc_pc_func_slp_sl_thold_1), + .q(pc_pc_func_slp_sl_thold_0) + ); + + //---------------------------------------------------- + // CFG (RUN) + //---------------------------------------------------- + tri_plat #(.WIDTH(1)) cfg_3_2( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(ccflush_out_dc), + .din(pc_pc_cfg_sl_thold_3), + .q(pc_pc_cfg_sl_thold_2) + ); + + tri_plat #(.WIDTH(1)) cfg_2_1( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(ccflush_out_dc), + .din(pc_pc_cfg_sl_thold_2), + .q(pc_pc_cfg_sl_thold_1) + ); + + tri_plat #(.WIDTH(1)) cfg_1_0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(ccflush_out_dc), + .din(pc_pc_cfg_sl_thold_1), + .q(pc_pc_cfg_sl_thold_0) + ); + + //---------------------------------------------------- + // CFG (SLEEP) + //---------------------------------------------------- + tri_plat #(.WIDTH(1)) cfg_slp_3_2( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(ccflush_out_dc), + .din(pc_pc_cfg_slp_sl_thold_3), + .q(pc_pc_cfg_slp_sl_thold_2) + ); + + tri_plat #(.WIDTH(1)) cfg_slp_2_1( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(ccflush_out_dc), + .din(pc_pc_cfg_slp_sl_thold_2), + .q(pc_pc_cfg_slp_sl_thold_1) + ); + + tri_plat #(.WIDTH(1)) cfg_slp_1_0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(ccflush_out_dc), + .din(pc_pc_cfg_slp_sl_thold_1), + .q(pc_pc_cfg_slp_sl_thold_0) + ); + + //---------------------------------------------------- + // GPTR + //---------------------------------------------------- + tri_plat #(.WIDTH(1)) gptr_3_2( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(ccflush_out_dc), + .din(pc_pc_gptr_sl_thold_3), + .q(pc_pc_gptr_sl_thold_2) + ); + + tri_plat #(.WIDTH(1)) gptr_2_1( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(ccflush_out_dc), + .din(pc_pc_gptr_sl_thold_2), + .q(pc_pc_gptr_sl_thold_1) + ); + + tri_plat #(.WIDTH(1)) gptr_1_0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(ccflush_out_dc), + .din(pc_pc_gptr_sl_thold_1), + .q(pc_pc_gptr_sl_thold_0) + ); + + //---------------------------------------------------- + // SG + //---------------------------------------------------- + tri_plat #(.WIDTH(1)) sg_3_2( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(ccflush_out_dc), + .din(pc_pc_sg_3), + .q(pc_pc_sg_2) + ); + + tri_plat #(.WIDTH(1)) sg_2_1( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(ccflush_out_dc), + .din(pc_pc_sg_2), + .q(pc_pc_sg_1) + ); + + tri_plat #(.WIDTH(1)) sg_1_0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(ccflush_out_dc), + .din(pc_pc_sg_1), + .q(pc_pc_sg_0) + ); + + +endmodule diff --git a/dev/verilog/work/pcq_ctrl.v b/dev/verilog/work/pcq_ctrl.v new file mode 100755 index 0000000..fd8fd78 --- /dev/null +++ b/dev/verilog/work/pcq_ctrl.v @@ -0,0 +1,415 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +// +// Description: Pervasive Core Thread Controls +// +//***************************************************************************** + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" + +module pcq_ctrl( +// Include model build parameters +`include "tri_a2o.vh" + + inout vdd, + inout gnd, + input [0:`NCLK_WIDTH-1] nclk, + input scan_dis_dc_b, + input lcb_clkoff_dc_b, + input lcb_mpw1_dc_b, + input lcb_mpw2_dc_b, + input lcb_delay_lclkr_dc, + input lcb_act_dis_dc, + input pc_pc_func_slp_sl_thold_0, + input pc_pc_sg_0, + input func_scan_in, + output func_scan_out, + // Reset Related + output pc_lq_init_reset, + output pc_iu_init_reset, + output ct_rg_hold_during_init, + // Power Management + output [0:`THREADS-1] ct_rg_power_managed, + output ac_an_power_managed, + output ac_an_rvwinkle_mode, + output pc_xu_pm_hold_thread, + output ct_ck_pm_ccflush_disable, + output ct_ck_pm_raise_tholds, + input rg_ct_dis_pwr_savings, + input [0:1] xu_pc_spr_ccr0_pme, + input [0:`THREADS-1] xu_pc_spr_ccr0_we, + // Trace/Trigger Signals + output [0:14] dbg_ctrls +); + + +//===================================================================== +// Signal Declarations +//===================================================================== + parameter INITACTIVE_SIZE = 1; + parameter HOLDCNTR_SIZE = 3; + parameter INITCNTR_SIZE = 9; + parameter INITERAT_SIZE = 1; + parameter PMCTRLS_T0_SIZE = 15; + parameter PMCTRLS_T1_SIZE = 2 * (`THREADS - 1); + parameter SPARECTRL_SIZE = 6; + + //--------------------------------------------------------------------- + // Scan Ring Ordering: + // start of func scan chain ordering + parameter INITACTIVE_OFFSET = 0; + parameter HOLDCNTR_OFFSET = INITACTIVE_OFFSET + INITACTIVE_SIZE; + parameter INITCNTR_OFFSET = HOLDCNTR_OFFSET + HOLDCNTR_SIZE; + parameter INITERAT_OFFSET = INITCNTR_OFFSET + INITCNTR_SIZE; + parameter PMCTRLS_T0_OFFSET = INITERAT_OFFSET + INITERAT_SIZE; + parameter PMCTRLS_T1_OFFSET = PMCTRLS_T0_OFFSET + PMCTRLS_T0_SIZE; + parameter SPARECTRL_OFFSET = PMCTRLS_T1_OFFSET + PMCTRLS_T1_SIZE; + parameter FUNC_RIGHT = SPARECTRL_OFFSET + SPARECTRL_SIZE - 1; + // end of func scan chain ordering + + //--------------------------------------------------------------------- + // Array Initialization Controls: + parameter HOLDCNT_IDLE = 0; + parameter HOLDCNT_DONE = 7; + parameter INITCNT_START = 15+(`INIT_BHT*496); // sets INITCNTR to 15 or 511 + parameter INITCNT_DONE = 0; + + //--------------------------------------------------------------------- + // Basic/Misc signals + wire tiup; + wire [0:FUNC_RIGHT] func_siv; + wire [0:FUNC_RIGHT] func_sov; + wire pc_pc_func_slp_sl_thold_0_b; + wire force_funcslp; + // Reset Signals + wire initcntr_enabled; + // Power management Signals + wire [0:1] spr_ccr0_pme_q; + wire [0:`THREADS-1] spr_ccr0_we_q; + wire pm_sleep_enable; + wire pm_rvw_enable; + wire [0:`THREADS-1] thread_stopped; + wire pmstate_q_anded; + // Latch definitions begin + wire [0:HOLDCNTR_SIZE-1] holdcntr_d; + wire [0:HOLDCNTR_SIZE-1] holdcntr_q; + wire [0:INITCNTR_SIZE-1] initcntr_d; + wire [0:INITCNTR_SIZE-1] initcntr_q; + wire init_active_d; + wire init_active_q; + wire initerat_d; + wire initerat_q; + wire pmstate_enab; + wire [0:`THREADS-1] pmstate_d; + wire [0:`THREADS-1] pmstate_q; + wire pmstate_all_d; + wire pmstate_all_q; + wire [0:7] pmclkctrl_dly_d; + wire [0:7] pmclkctrl_dly_q; + wire power_managed_d; + wire power_managed_q; + wire rvwinkled_d; + wire rvwinkled_q; + wire pm_ccflush_disable_int; + wire pm_raise_tholds_int; + wire [0:SPARECTRL_SIZE-1] spare_ctrl_wrapped_q; + + +//!! Bugspray Include: pcq_ctrl; + + assign tiup = 1'b1; + +//===================================================================== +// Reset State Machine +//===================================================================== + // HOLDCNTR: Delays start of array initialization for 7 cycles. Provides some time + // after clock start to ensure clock controls have propagated to LCBs. . + assign holdcntr_d = init_active_q == 1'b0 ? HOLDCNT_IDLE : + holdcntr_q == HOLDCNT_DONE ? HOLDCNT_DONE : + holdcntr_q + 3'b001; + + // Latch ACT control: Goes inactive once array initialization is over. + assign initcntr_enabled = init_active_q | (|holdcntr_q); + + + // INITCNTR: Initialized to a value; counts down while array init signal held active. + // Default time is 16 cycles, which is long enough for the ERATs to initialize. + // To initialize the BHT, the array init signal is kept active for 512 cycles. + // Controlled by `INIT_BHT (0=16 cycles; 1=512 cycles) + assign initcntr_d = holdcntr_q != HOLDCNT_DONE ? initcntr_q : + initcntr_q == INITCNT_DONE ? INITCNT_DONE : + initcntr_q - 9'b000000001; + + + // INITERAT: The initerat latch controls the init_reset signals to IU and XU. + // Goes active when HOLDCNTR=7, and shuts off when INITCNTR counts down to 0. + assign initerat_d = ( holdcntr_q < HOLDCNT_DONE-1) ? 1'b0 : + (|initcntr_q); + + + // INIT_ACTIVE: init_active_q initializes to '1'; cleared after INITCNTR counts down to 0. + assign init_active_d = (initcntr_q == INITCNT_DONE) ? 1'b0 : + init_active_q; + + +//===================================================================== +// Power Management Latches +//===================================================================== +// XU signals indicate when power-savings is enabled (sleep or rvw modes), and which +// THREADS are stopped. +// The pmstate latch tracks which THREADS are stopped when either power-savings mode +// is enabled. The rvwinkled latch only when pm_rvw_enable is set. +// If all THREADS are stopped when power-savings is enabled, then signals to the +// clock control macro will initiate power savings actions. These controls force +// ccflush_dc inactive to ensure all PLATs are clocking. After a delay period, the +// run tholds will be raised to stop clocks. +// When coming out of power-savings, the tholds will be disabled prior to deactivating +// ccflush_dc. + assign pm_sleep_enable = (~spr_ccr0_pme_q[0]) & spr_ccr0_pme_q[1]; + assign pm_rvw_enable = spr_ccr0_pme_q[0] & (~spr_ccr0_pme_q[1]); + assign thread_stopped = spr_ccr0_we_q; + + + assign pmstate_enab = (pm_sleep_enable | pm_rvw_enable) & (~initcntr_enabled); + assign pmstate_d = {`THREADS{pmstate_enab}} & thread_stopped[0:`THREADS - 1]; + + // Once all CCR0[WE] bits are set, pmstate_all_q is held active until pmclkctrl_dly_q(7). + // Forces an orderly sequence through PM controls, even if one thread wakes-up right away. + assign pmstate_q_anded = (&pmstate_q); + + assign pmstate_all_d = ((~pmclkctrl_dly_q[7]) & (pmstate_q_anded | pmstate_all_q)) | + (pmstate_q_anded & pmstate_all_q); + + assign power_managed_d = pmstate_all_d | pmclkctrl_dly_q[6]; + assign rvwinkled_d = (pmstate_all_d | pmclkctrl_dly_q[6]) & pm_rvw_enable; + + assign pmclkctrl_dly_d[0:7] = {pmstate_all_q, pmclkctrl_dly_q[0:6]}; + + +//===================================================================== +// Outputs +//===================================================================== + // Used as part of thread stop signal to XU. + // Keeps THREADS stopped until after the Reset SM completes count. + assign ct_rg_hold_during_init = init_active_q; + + // Init pulse to IU and XU to force initialization of IERAT, DERAT and BHT. + // IU also holds instruction fetch until init signal released. + assign pc_iu_init_reset = initerat_q; + assign pc_lq_init_reset = initerat_q; + + // To THRCTL[Tx_PM]; indicates core power-managed via software actions. + assign ct_rg_power_managed = pmstate_q[0:`THREADS - 1]; + + // Core in rvwinkle power-savings state. L2 can prepare for Chiplet power-down. + assign ac_an_rvwinkle_mode = rvwinkled_q; + // Core in power-savings state due to any combination of power-savings instructions + assign ac_an_power_managed = power_managed_q; + assign pc_xu_pm_hold_thread = power_managed_q; + + // Goes to clock controls to disable plat flush controls + assign pm_ccflush_disable_int = pmstate_all_q | pmclkctrl_dly_q[7]; + assign ct_ck_pm_ccflush_disable = pm_ccflush_disable_int & (~rg_ct_dis_pwr_savings); + // Goes to clock controls to activate run tholds + assign pm_raise_tholds_int = pmstate_all_q & pmclkctrl_dly_q[7]; + assign ct_ck_pm_raise_tholds = pm_raise_tholds_int & (~rg_ct_dis_pwr_savings); + + +//===================================================================== +// Trace/Trigger Signals +//===================================================================== + assign dbg_ctrls = { pmstate_q_anded, // 0 + pmstate_all_q, // 1 + power_managed_q, // 2 + rvwinkled_q, // 3 + pmclkctrl_dly_q[0:7], // 4:11 + rg_ct_dis_pwr_savings, // 12 + pm_ccflush_disable_int, // 13 + pm_raise_tholds_int // 14 + }; + + +//===================================================================== +// Latches +//===================================================================== + // func ring registers start + tri_rlmlatch_p #(.INIT(1)) initactive( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_pc_func_slp_sl_thold_0_b), + .sg(pc_pc_sg_0), + .force_t(force_funcslp), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(func_siv[ INITACTIVE_OFFSET]), + .scout(func_sov[INITACTIVE_OFFSET]), + .din(init_active_d), + .dout(init_active_q) + ); + + tri_rlmreg_p #(.WIDTH(HOLDCNTR_SIZE), .INIT(0)) holdcntr( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(initcntr_enabled), + .thold_b(pc_pc_func_slp_sl_thold_0_b), + .sg(pc_pc_sg_0), + .force_t(force_funcslp), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(func_siv[ HOLDCNTR_OFFSET:HOLDCNTR_OFFSET + HOLDCNTR_SIZE - 1]), + .scout(func_sov[HOLDCNTR_OFFSET:HOLDCNTR_OFFSET + HOLDCNTR_SIZE - 1]), + .din(holdcntr_d), + .dout(holdcntr_q) + ); + + tri_rlmreg_p #(.WIDTH(INITCNTR_SIZE), .INIT(INITCNT_START)) initcntr( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(initcntr_enabled), + .thold_b(pc_pc_func_slp_sl_thold_0_b), + .sg(pc_pc_sg_0), + .force_t(force_funcslp), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(func_siv[ INITCNTR_OFFSET:INITCNTR_OFFSET + INITCNTR_SIZE - 1]), + .scout(func_sov[INITCNTR_OFFSET:INITCNTR_OFFSET + INITCNTR_SIZE - 1]), + .din(initcntr_d), + .dout(initcntr_q) + ); + + tri_rlmlatch_p #(.INIT(0)) initerat( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(initcntr_enabled), + .thold_b(pc_pc_func_slp_sl_thold_0_b), + .sg(pc_pc_sg_0), + .force_t(force_funcslp), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(func_siv[ INITERAT_OFFSET]), + .scout(func_sov[INITERAT_OFFSET]), + .din(initerat_d), + .dout(initerat_q) + ); + + tri_rlmreg_p #(.WIDTH(PMCTRLS_T0_SIZE), .INIT(0)) pmctrls_t0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_pc_func_slp_sl_thold_0_b), + .sg(pc_pc_sg_0), + .force_t(force_funcslp), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(func_siv[ PMCTRLS_T0_OFFSET:PMCTRLS_T0_OFFSET + PMCTRLS_T0_SIZE - 1]), + .scout(func_sov[PMCTRLS_T0_OFFSET:PMCTRLS_T0_OFFSET + PMCTRLS_T0_SIZE - 1]), + + .din( {pmclkctrl_dly_d, xu_pc_spr_ccr0_pme, xu_pc_spr_ccr0_we[0], pmstate_d[0], + pmstate_all_d, rvwinkled_d, power_managed_d}), + + .dout({pmclkctrl_dly_q, spr_ccr0_pme_q, spr_ccr0_we_q[0], pmstate_q[0], + pmstate_all_q, rvwinkled_q, power_managed_q}) + ); + + generate + if (`THREADS > 1) + begin : T1_pmctrls + tri_rlmreg_p #(.WIDTH(PMCTRLS_T1_SIZE), .INIT(0)) pmctrls_t1( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_pc_func_slp_sl_thold_0_b), + .sg(pc_pc_sg_0), + .force_t(force_funcslp), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(func_siv[ PMCTRLS_T1_OFFSET:PMCTRLS_T1_OFFSET + PMCTRLS_T1_SIZE - 1]), + .scout(func_sov[PMCTRLS_T1_OFFSET:PMCTRLS_T1_OFFSET + PMCTRLS_T1_SIZE - 1]), + .din({xu_pc_spr_ccr0_we[1], pmstate_d[1]}), + .dout({spr_ccr0_we_q[1], pmstate_q[1]}) + ); + end + endgenerate + + + tri_rlmreg_p #(.WIDTH(SPARECTRL_SIZE), .INIT(0)) sparectrl( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_pc_func_slp_sl_thold_0_b), + .sg(pc_pc_sg_0), + .force_t(force_funcslp), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(func_siv[ SPARECTRL_OFFSET:SPARECTRL_OFFSET + SPARECTRL_SIZE - 1]), + .scout(func_sov[SPARECTRL_OFFSET:SPARECTRL_OFFSET + SPARECTRL_SIZE - 1]), + .din(spare_ctrl_wrapped_q), + .dout(spare_ctrl_wrapped_q) + ); + // func ring registers end + +//===================================================================== +// Thold/SG Staging +//===================================================================== + // func_slp lcbor + tri_lcbor lcbor_funcslp( + .clkoff_b(lcb_clkoff_dc_b), + .thold(pc_pc_func_slp_sl_thold_0), + .sg(pc_pc_sg_0), + .act_dis(lcb_act_dis_dc), + .force_t(force_funcslp), + .thold_b(pc_pc_func_slp_sl_thold_0_b) + ); + +//===================================================================== +// Scan Connections +//===================================================================== + // Func ring + assign func_siv[0:FUNC_RIGHT] = {func_scan_in, func_sov[0:FUNC_RIGHT - 1]}; + assign func_scan_out = func_sov[FUNC_RIGHT] & scan_dis_dc_b; + + +endmodule diff --git a/dev/verilog/work/pcq_dbg.v b/dev/verilog/work/pcq_dbg.v new file mode 100755 index 0000000..ed385e4 --- /dev/null +++ b/dev/verilog/work/pcq_dbg.v @@ -0,0 +1,443 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +// +// Description: Pervasive Core Debug/Event Bus Controls +// +//***************************************************************************** + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" + +module pcq_dbg( +// Include model build parameters +`include "tri_a2o.vh" + + inout vdd, + inout gnd, + input [0:`NCLK_WIDTH-1] nclk, + input scan_dis_dc_b, + input lcb_clkoff_dc_b, + input lcb_mpw1_dc_b, + input lcb_mpw2_dc_b, + input lcb_delay_lclkr_dc, + input lcb_act_dis_dc, + input pc_pc_func_slp_sl_thold_0, + input pc_pc_sg_0, + input func_scan_in, + output func_scan_out, + // Trace/Trigger Bus + output [0:31] debug_bus_out, + input [0:31] debug_bus_in, + input rg_db_trace_bus_enable, + input [0:10] rg_db_debug_mux_ctrls, + input [0:3] coretrace_ctrls_in, + output [0:3] coretrace_ctrls_out, + //PC Unit internal debug signals + input [0:11] rg_db_dbg_scom, + input [0:24] rg_db_dbg_thrctls, + input [0:15] rg_db_dbg_ram, + input [0:27] rg_db_dbg_fir0_err, + input [0:19] rg_db_dbg_fir1_err, + input [0:19] rg_db_dbg_fir2_err, + input [0:14] rg_db_dbg_fir_misc, + input [0:14] ct_db_dbg_ctrls, + input [0:7] rg_db_dbg_spr +); + + +//===================================================================== +// Signal Declarations +//===================================================================== + parameter RAMCTRL_SIZE = 2; + parameter SCMISC_SIZE = 7; + parameter FIRMISC_SIZE = 2; + parameter TRACEOUT_SIZE = 32; + parameter CORETRACE_SIZE = 4; + + //--------------------------------------------------------------------- + // Scan Ring Ordering: + // start of func scan chain ordering + parameter RAMCTRL_OFFSET = 0; + parameter SCMISC_OFFSET = RAMCTRL_OFFSET + RAMCTRL_SIZE; + parameter FIRMISC_OFFSET = SCMISC_OFFSET + SCMISC_SIZE; + parameter TRACEOUT_OFFSET = FIRMISC_OFFSET + FIRMISC_SIZE; + parameter CORETRACE_OFFSET = TRACEOUT_OFFSET + TRACEOUT_SIZE; + parameter FUNC_RIGHT = CORETRACE_OFFSET + CORETRACE_SIZE - 1; + // end of func scan chain ordering + + //--------------------------------------------------------------------- + // Basic/Misc signals + wire [0:FUNC_RIGHT] func_siv; + wire [0:FUNC_RIGHT] func_sov; + wire pc_pc_func_slp_sl_thold_0_b; + wire force_func; + + // Trace/Trigger/Event Mux signals + wire [0:TRACEOUT_SIZE-1] debug_group_0; + wire [0:TRACEOUT_SIZE-1] debug_group_1; + wire [0:TRACEOUT_SIZE-1] debug_group_2; + wire [0:TRACEOUT_SIZE-1] debug_group_3; + wire [0:TRACEOUT_SIZE-1] debug_group_4; + wire [0:TRACEOUT_SIZE-1] debug_group_5; + wire [0:TRACEOUT_SIZE-1] debug_group_6; + wire [0:TRACEOUT_SIZE-1] debug_group_7; + // Trace/Trigger input signals + wire [0:31] fir0_errors_q; + wire [0:31] fir1_errors_q; + wire [0:31] fir2_errors_q; + wire [0:2] fir_xstop_err_q; + wire [0:2] fir_lxstop_err_q; + wire [0:2] fir_recov_err_q; + wire fir0_recov_err_pulse_q; + wire fir1_recov_err_pulse_q; + wire fir2_recov_err_pulse_q; + wire fir_block_ram_mode_q; + wire [0:1] fir_xstop_per_thread_d; + wire [0:1] fir_xstop_per_thread_q; + // + wire scmisc_sc_act_d; + wire scmisc_sc_act_q; + wire scmisc_sc_req_q; + wire scmisc_sc_wr_q; + wire [0:5] scmisc_scaddr_predecode_d; + wire [0:5] scmisc_scaddr_predecode_q; + wire scmisc_scaddr_nvld_q; + wire scmisc_sc_wr_nvld_q; + wire scmisc_sc_rd_nvld_q; + // + wire ram_mode_q; + wire [0:1] ram_active_q; + wire ram_execute_q; + wire ram_msrovren_q; + wire ram_msrovrpr_q; + wire ram_msrovrgs_q; + wire ram_msrovrde_q; + wire ram_unsupported_q; + wire ram_instr_overrun_d; + wire ram_instr_overrun_q; + wire ram_interrupt_q; + wire ram_mode_xstop_d; + wire ram_mode_xstop_q; + wire ram_done_q; + wire ram_xu_ram_data_val_q; + wire ram_fu_ram_data_val_q; + wire ram_lq_ram_data_val_q; + // + wire regs_xstop_report_ovrid; + wire regs_dis_pwr_savings; + wire regs_dis_overrun_chks; + wire regs_maxRecErrCntrValue; + wire regs_ext_debug_stop_q; + wire [0:1] regs_spattn_data_q; + wire [0:1] regs_power_managed_q; + wire [0:1] regs_pm_thread_stop_q; + wire [0:1] regs_stop_dbg_event_q; + wire [0:1] regs_stop_dbg_dnh_q; + wire [0:1] regs_tx_stop_q; + wire [0:1] regs_thread_running_q; + wire [0:1] regs_tx_step_q; + wire [0:1] regs_tx_step_done_q; + wire [0:1] regs_tx_step_req_q; + // + wire ctrls_pmstate_q_anded; + wire ctrls_pmstate_all_q; + wire ctrls_power_managed_q; + wire ctrls_pm_rvwinkled_q; + wire [0:7] ctrls_pmclkctrl_dly_q; + wire ctrls_dis_pwr_sav_q; + wire ctrls_ccflush_dis_q; + wire ctrls_raise_tholds_q; + // + wire spr_cesr1_wren; + wire spr_sramd_wren; + wire [0:1] spr_perfmon_alert_q; + wire [0:1] spr_cesr1_is0_l2; + wire [0:1] spr_cesr1_is1_l2; + // Latch definitions begin + wire [0:TRACEOUT_SIZE-1] trace_data_out_d; + wire [0:TRACEOUT_SIZE-1] trace_data_out_q; + wire [0:3] coretrace_ctrls_out_d; + wire [0:3] coretrace_ctrls_out_q; + +//===================================================================== +// Trace/Trigger Bus - Sort out input debug signals +//===================================================================== + // FIR/Error related signals. + assign fir0_errors_q[0:31] = {rg_db_dbg_fir0_err, { 4 {1'b0}} }; + assign fir1_errors_q[0:31] = {rg_db_dbg_fir1_err, {12 {1'b0}} }; + assign fir2_errors_q[0:31] = {rg_db_dbg_fir2_err, {12 {1'b0}} }; + assign fir_xstop_err_q = rg_db_dbg_fir_misc[0:2]; + assign fir_lxstop_err_q = rg_db_dbg_fir_misc[3:5]; + assign fir_recov_err_q = rg_db_dbg_fir_misc[6:8]; + assign fir0_recov_err_pulse_q = rg_db_dbg_fir_misc[9]; + assign fir1_recov_err_pulse_q = rg_db_dbg_fir_misc[10]; + assign fir2_recov_err_pulse_q = rg_db_dbg_fir_misc[11]; + assign fir_block_ram_mode_q = rg_db_dbg_fir_misc[12]; + assign fir_xstop_per_thread_d = rg_db_dbg_fir_misc[13:14]; + // SCOM error; control signals + assign scmisc_sc_act_d = rg_db_dbg_scom[0]; + assign scmisc_sc_req_q = rg_db_dbg_scom[1]; + assign scmisc_sc_wr_q = rg_db_dbg_scom[2]; + assign scmisc_scaddr_predecode_d = rg_db_dbg_scom[3:8]; + assign scmisc_scaddr_nvld_q = rg_db_dbg_scom[9]; + assign scmisc_sc_wr_nvld_q = rg_db_dbg_scom[10]; + assign scmisc_sc_rd_nvld_q = rg_db_dbg_scom[11]; + // RAM control signals + assign ram_mode_q = rg_db_dbg_ram[0]; + assign ram_active_q = rg_db_dbg_ram[1:2]; + assign ram_execute_q = rg_db_dbg_ram[3]; + assign ram_msrovren_q = rg_db_dbg_ram[4]; + assign ram_msrovrpr_q = rg_db_dbg_ram[5]; + assign ram_msrovrgs_q = rg_db_dbg_ram[6]; + assign ram_msrovrde_q = rg_db_dbg_ram[7]; + assign ram_unsupported_q = rg_db_dbg_ram[8]; + assign ram_instr_overrun_d = rg_db_dbg_ram[9]; + assign ram_interrupt_q = rg_db_dbg_ram[10]; + assign ram_mode_xstop_d = rg_db_dbg_ram[11]; + assign ram_done_q = rg_db_dbg_ram[12]; + assign ram_xu_ram_data_val_q = rg_db_dbg_ram[13]; + assign ram_fu_ram_data_val_q = rg_db_dbg_ram[14]; + assign ram_lq_ram_data_val_q = rg_db_dbg_ram[15]; + // THRCTL and misc control signals + assign regs_xstop_report_ovrid = rg_db_dbg_thrctls[0]; + assign regs_dis_pwr_savings = rg_db_dbg_thrctls[1]; + assign regs_dis_overrun_chks = rg_db_dbg_thrctls[2]; + assign regs_maxRecErrCntrValue = rg_db_dbg_thrctls[3]; + assign regs_ext_debug_stop_q = rg_db_dbg_thrctls[4]; + assign regs_spattn_data_q = rg_db_dbg_thrctls[5:6]; + assign regs_power_managed_q = rg_db_dbg_thrctls[7:8]; + assign regs_pm_thread_stop_q = rg_db_dbg_thrctls[9:10]; + assign regs_stop_dbg_event_q = rg_db_dbg_thrctls[11:12]; + assign regs_stop_dbg_dnh_q = rg_db_dbg_thrctls[13:14]; + assign regs_tx_stop_q = rg_db_dbg_thrctls[15:16]; + assign regs_thread_running_q = rg_db_dbg_thrctls[17:18]; + assign regs_tx_step_q = rg_db_dbg_thrctls[19:20]; + assign regs_tx_step_done_q = rg_db_dbg_thrctls[21:22]; + assign regs_tx_step_req_q = rg_db_dbg_thrctls[23:24]; + // Power Management signals + assign ctrls_pmstate_q_anded = ct_db_dbg_ctrls[0]; + assign ctrls_pmstate_all_q = ct_db_dbg_ctrls[1]; + assign ctrls_power_managed_q = ct_db_dbg_ctrls[2]; + assign ctrls_pm_rvwinkled_q = ct_db_dbg_ctrls[3]; + assign ctrls_pmclkctrl_dly_q = ct_db_dbg_ctrls[4:11]; + assign ctrls_dis_pwr_sav_q = ct_db_dbg_ctrls[12]; + assign ctrls_ccflush_dis_q = ct_db_dbg_ctrls[13]; + assign ctrls_raise_tholds_q = ct_db_dbg_ctrls[14]; + // SPRs signals + assign spr_cesr1_wren = rg_db_dbg_spr[0]; + assign spr_sramd_wren = rg_db_dbg_spr[1]; + assign spr_perfmon_alert_q = rg_db_dbg_spr[2:3]; + assign spr_cesr1_is0_l2 = rg_db_dbg_spr[4:5]; + assign spr_cesr1_is1_l2 = rg_db_dbg_spr[6:7]; + + +//===================================================================== +// Trace/Trigger Bus - Form trace bus groups from input debug signals +//===================================================================== +// FIR0[32:59] errors not connected: max_recov_err_cntr_value (32), spare (59) +// FIR1[32:51] errors not connected: wdt_reset (45), debug_event (46), spare (47:51) +// FIR2[32:51] errors not connected: wdt_reset (45), debug_event (46), spare (47:51) + + assign debug_group_0[0:TRACEOUT_SIZE-1] = { fir0_errors_q[0:31] }; // 0:31 + + assign debug_group_1[0:TRACEOUT_SIZE-1] = { fir1_errors_q[0:31] }; // 0:31 + + assign debug_group_2[0:TRACEOUT_SIZE-1] = { fir2_errors_q[0:31] }; // 0:31 + + + assign debug_group_3[0:TRACEOUT_SIZE-1] = { + fir_recov_err_q[0:2], fir_xstop_err_q[0:2], fir_lxstop_err_q[0:2], fir_xstop_per_thread_q[0:1], // 0:15 + fir_block_ram_mode_q, fir0_recov_err_pulse_q, fir1_recov_err_pulse_q, fir2_recov_err_pulse_q, + scmisc_sc_act_q, scmisc_sc_req_q, scmisc_sc_wr_q, scmisc_scaddr_nvld_q, // 16:31 + scmisc_sc_wr_nvld_q, scmisc_sc_rd_nvld_q, scmisc_scaddr_predecode_q[0:5], 5'b00000 + }; + + assign debug_group_4[0:TRACEOUT_SIZE-1] = { + regs_maxRecErrCntrValue, regs_xstop_report_ovrid, regs_spattn_data_q[0:1], // 0:15 + regs_ext_debug_stop_q, regs_stop_dbg_event_q[0:1], regs_stop_dbg_dnh_q[0:1], + regs_pm_thread_stop_q[0:1], regs_thread_running_q[0:1], regs_power_managed_q[0:1], + regs_dis_pwr_savings, + regs_tx_stop_q[0:1], regs_tx_step_q[0:1], regs_tx_step_done_q[0:1], regs_tx_step_req_q[0:1], // 16:31 + spr_perfmon_alert_q[0:1], spr_cesr1_is0_l2[0:1], spr_cesr1_is1_l2[0:1], + spr_sramd_wren, spr_cesr1_wren + }; + + assign debug_group_5[0:TRACEOUT_SIZE-1] = { + ctrls_pmstate_q_anded, ctrls_pmstate_all_q, ctrls_power_managed_q, ctrls_pm_rvwinkled_q, // 0:15 + ctrls_pmclkctrl_dly_q[0:7], ctrls_dis_pwr_sav_q, ctrls_ccflush_dis_q, ctrls_raise_tholds_q, + regs_dis_overrun_chks, + ram_mode_q, ram_active_q[0:1], ram_execute_q, ram_done_q, ram_xu_ram_data_val_q, // 16:31 + ram_fu_ram_data_val_q, ram_lq_ram_data_val_q, ram_msrovren_q, ram_msrovrpr_q, ram_msrovrgs_q, + ram_msrovrde_q, ram_unsupported_q, ram_instr_overrun_q, ram_interrupt_q, ram_mode_xstop_q + }; + + assign debug_group_6[0:TRACEOUT_SIZE-1] = { {32 {1'b0}} }; + + assign debug_group_7[0:TRACEOUT_SIZE-1] = { {32 {1'b0}} }; + + +//===================================================================== +// Trace Bus Mux +//===================================================================== + tri_debug_mux8 debug_mux( + .select_bits(rg_db_debug_mux_ctrls), + .dbg_group0(debug_group_0), + .dbg_group1(debug_group_1), + .dbg_group2(debug_group_2), + .dbg_group3(debug_group_3), + .dbg_group4(debug_group_4), + .dbg_group5(debug_group_5), + .dbg_group6(debug_group_6), + .dbg_group7(debug_group_7), + .trace_data_in(debug_bus_in), + .trace_data_out(trace_data_out_d), + .coretrace_ctrls_in(coretrace_ctrls_in), + .coretrace_ctrls_out(coretrace_ctrls_out_d) + ); + +//===================================================================== +// Outputs +//===================================================================== + assign debug_bus_out = trace_data_out_q; + + assign coretrace_ctrls_out = coretrace_ctrls_out_q; + +//===================================================================== +// Latches +//===================================================================== + // func ring registers start + tri_rlmreg_p #(.WIDTH(RAMCTRL_SIZE), .INIT(0)) ramctrl( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rg_db_trace_bus_enable), + .thold_b(pc_pc_func_slp_sl_thold_0_b), + .sg(pc_pc_sg_0), + .force_t(force_func), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(func_siv[RAMCTRL_OFFSET:RAMCTRL_OFFSET + RAMCTRL_SIZE - 1]), + .scout(func_sov[RAMCTRL_OFFSET:RAMCTRL_OFFSET + RAMCTRL_SIZE - 1]), + .din( {ram_instr_overrun_d, ram_mode_xstop_d}), + .dout({ram_instr_overrun_q, ram_mode_xstop_q}) + ); + + tri_rlmreg_p #(.WIDTH(SCMISC_SIZE), .INIT(0)) scmisc( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rg_db_trace_bus_enable), + .thold_b(pc_pc_func_slp_sl_thold_0_b), + .sg(pc_pc_sg_0), + .force_t(force_func), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(func_siv[SCMISC_OFFSET:SCMISC_OFFSET + SCMISC_SIZE - 1]), + .scout(func_sov[SCMISC_OFFSET:SCMISC_OFFSET + SCMISC_SIZE - 1]), + .din( {scmisc_sc_act_d, scmisc_scaddr_predecode_d}), + .dout({scmisc_sc_act_q, scmisc_scaddr_predecode_q}) + ); + + tri_rlmreg_p #(.WIDTH(FIRMISC_SIZE), .INIT(0)) firmisc( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rg_db_trace_bus_enable), + .thold_b(pc_pc_func_slp_sl_thold_0_b), + .sg(pc_pc_sg_0), + .force_t(force_func), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(func_siv[FIRMISC_OFFSET:FIRMISC_OFFSET + FIRMISC_SIZE - 1]), + .scout(func_sov[FIRMISC_OFFSET:FIRMISC_OFFSET + FIRMISC_SIZE - 1]), + .din( fir_xstop_per_thread_d), + .dout(fir_xstop_per_thread_q) + ); + + tri_rlmreg_p #(.WIDTH(TRACEOUT_SIZE), .INIT(0)) traceout( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rg_db_trace_bus_enable), + .thold_b(pc_pc_func_slp_sl_thold_0_b), + .sg(pc_pc_sg_0), + .force_t(force_func), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(func_siv[TRACEOUT_OFFSET:TRACEOUT_OFFSET + TRACEOUT_SIZE - 1]), + .scout(func_sov[TRACEOUT_OFFSET:TRACEOUT_OFFSET + TRACEOUT_SIZE - 1]), + .din( trace_data_out_d), + .dout(trace_data_out_q) + ); + + tri_rlmreg_p #(.WIDTH(CORETRACE_SIZE), .INIT(0)) coretrace( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rg_db_trace_bus_enable), + .thold_b(pc_pc_func_slp_sl_thold_0_b), + .sg(pc_pc_sg_0), + .force_t(force_func), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(func_siv[CORETRACE_OFFSET:CORETRACE_OFFSET + CORETRACE_SIZE - 1]), + .scout(func_sov[CORETRACE_OFFSET:CORETRACE_OFFSET + CORETRACE_SIZE - 1]), + .din( coretrace_ctrls_out_d), + .dout(coretrace_ctrls_out_q) + ); + // func ring registers end + +//===================================================================== +// Thold/SG Staging +//===================================================================== + // func lcbor + tri_lcbor lcbor_func0( + .clkoff_b(lcb_clkoff_dc_b), + .thold(pc_pc_func_slp_sl_thold_0), + .sg(pc_pc_sg_0), + .act_dis(lcb_act_dis_dc), + .force_t(force_func), + .thold_b(pc_pc_func_slp_sl_thold_0_b) + ); + +//===================================================================== +// Scan Connections +//===================================================================== + // Func ring + assign func_siv[0:FUNC_RIGHT] = {func_scan_in, func_sov[0:FUNC_RIGHT - 1]}; + assign func_scan_out = func_sov[FUNC_RIGHT] & scan_dis_dc_b; + + +endmodule diff --git a/dev/verilog/work/pcq_local_fir2.v b/dev/verilog/work/pcq_local_fir2.v new file mode 100755 index 0000000..691e1bb --- /dev/null +++ b/dev/verilog/work/pcq_local_fir2.v @@ -0,0 +1,569 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +// +// Description: Generic Local FIR Component +// +//***************************************************************************** + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" + +module pcq_local_fir2( +// Include model build parameters +`include "tri_a2o.vh" + + nclk, + vdd, + gnd, + lcb_clkoff_dc_b, + lcb_mpw1_dc_b, + lcb_mpw2_dc_b, + lcb_delay_lclkr_dc, + lcb_act_dis_dc, + lcb_sg_0, + lcb_func_slp_sl_thold_0, + lcb_cfg_slp_sl_thold_0, + mode_scan_siv, + mode_scan_sov, + func_scan_siv, + func_scan_sov, + sys_xstop_in, + error_in, + xstop_err, + recov_err, + lxstop_mchk, + trace_error, + recov_reset, + fir_out, + act0_out, + act1_out, + mask_out, + sc_parity_error_inject, + sc_active, + sc_wr_q, + sc_addr_v, + sc_wdata, + sc_rdata, + fir_parity_check +); + + parameter WIDTH = 1; // this must be >=1 and <=64 + parameter IMPL_LXSTOP_MCHK = 1'b1; // generate local checkstop /machine check output + parameter USE_RECOV_RESET = 1'b0; // this adds a reset feature without the second wof register. + parameter [0:WIDTH-1] FIR_INIT = 1'b0; // init value for fir register; length = width ! + parameter [0:WIDTH-1] FIR_MASK_INIT = 1'b0; // init value for fir mask register; length = width ! + parameter FIR_MASK_PAR_INIT = 1'b0; // init value for fir mask register even parity + parameter [0:WIDTH-1] FIR_ACTION0_INIT = 1'b0; // init value for fir action0 register; length = width ! + parameter FIR_ACTION0_PAR_INIT = 1'b0; // init value for fir action0 register even parity + parameter [0:WIDTH-1] FIR_ACTION1_INIT = 1'b0; // init value for fir action1 register; length = width ! + parameter FIR_ACTION1_PAR_INIT = 1'b0; // init value for fir action1 register even parity + +//===================================================================== +// Port Definitions +//===================================================================== + // Global lines for clocking and scan control + input [0:`NCLK_WIDTH-1] nclk; + inout vdd; + inout gnd; + input lcb_clkoff_dc_b; //from lcb_cntl external to component + input lcb_mpw1_dc_b; //from lcb_cntl external to component + input lcb_mpw2_dc_b; //from lcb_cntl external to component + input lcb_delay_lclkr_dc; //from lcb_cntl external to component + input lcb_act_dis_dc; //from lcb_cntl external to component + input lcb_sg_0; + input lcb_func_slp_sl_thold_0; + input lcb_cfg_slp_sl_thold_0; + input [0:3*(WIDTH+1)+WIDTH-1] mode_scan_siv; // scan vector in + output [0:3*(WIDTH+1)+WIDTH-1] mode_scan_sov; // scan vector out + input [0:4] func_scan_siv; // scan vector in + output [0:4] func_scan_sov; // scan vector out + // External interface + input sys_xstop_in; // freeze FIR on system checkstop from chip GEM + input [0:WIDTH-1] error_in; // needs to be directly off a latch for timing + output xstop_err; // checkstop output to Global FIR + output recov_err; // recoverable output to Global FIR + output lxstop_mchk; // use ONLY if IMPL_LXSTOP_MCHK = true + output trace_error; // connect to error_input of closest trdata macro + input recov_reset; // only needed if USE_RECOV_RESET = true + output [0:WIDTH-1] fir_out; // output of current FIR state if needed + output [0:WIDTH-1] act0_out; // output of current FIR Act0 state if needed + output [0:WIDTH-1] act1_out; // output of current FIR Act1 state if needed + output [0:WIDTH-1] mask_out; // output of current FIR Mask state if needed + // SCOM register connections + input sc_parity_error_inject; // Force parity error + input sc_active; + input sc_wr_q; + input [0:8] sc_addr_v; + input [0:WIDTH-1] sc_wdata; + output [0:WIDTH-1] sc_rdata; + output [0:2] fir_parity_check; // Action0, Action1, Mask reg parity checks + +//===================================================================== +// Signal Declarations +//===================================================================== + // Clocks + wire func_d1clk; + wire func_d2clk; + wire [0:`NCLK_WIDTH-1] func_lclk; + wire mode_d1clk; + wire mode_d2clk; + wire [0:`NCLK_WIDTH-1] mode_lclk; + wire scom_mode_d1clk; + wire scom_mode_d2clk; + wire [0:`NCLK_WIDTH-1] scom_mode_lclk; + wire func_thold_b; + wire func_force; + wire mode_thold_b; + wire mode_force; + // FIR regs + wire [0:WIDTH-1] data_ones; + wire [0:WIDTH-1] or_fir; + wire [0:WIDTH-1] and_fir; + wire [0:WIDTH-1] or_mask; + wire [0:WIDTH-1] and_mask; + wire [0:WIDTH-1] fir_mask_in; + wire [0:WIDTH-1] fir_mask_lt; + wire [0:WIDTH-1] masked; + wire fir_mask_par_in; + wire fir_mask_par_lt; + wire fir_mask_par_err; + wire [0:WIDTH-1] fir_action0_in; + wire [0:WIDTH-1] fir_action0_lt; + wire fir_action0_par_in; + wire fir_action0_par_lt; + wire fir_action0_par_err; + wire [0:WIDTH-1] fir_action1_in; + wire [0:WIDTH-1] fir_action1_lt; + wire fir_action1_par_in; + wire fir_action1_par_lt; + wire fir_action1_par_err; + wire [0:WIDTH-1] fir_reset; + wire [0:WIDTH-1] error_input; + wire [0:WIDTH-1] fir_error_in_reef; + wire [0:WIDTH-1] fir_in; + wire [0:WIDTH-1] fir_lt; + wire fir_act; + wire block_fir; + wire or_fir_load; + wire and_fir_ones; + wire and_fir_load; + wire or_mask_load; + wire and_mask_ones; + wire and_mask_load; + // Error report + wire sys_xstop_lt; + wire recov_in; + wire recov_lt; + wire xstop_in; + wire xstop_lt; + wire trace_error_in; + wire trace_error_lt; + // Other + wire tieup; + // Scan chain hookups + wire [0:3*(WIDTH+1)+WIDTH-1] mode_si; + wire [0:3*(WIDTH+1)+WIDTH-1] mode_so; + wire [0:4] func_si; + wire [0:4] func_so; + +(* analysis_not_referenced="true" *) + wire unused_signals; + assign unused_signals = recov_reset | sc_addr_v[5]; + + + assign tieup = 1'b1; + assign data_ones = {WIDTH {1'b1}}; + +//****************************************************** +//* LCB driver, LCB and Register Instantiations +//****************************************************** + // functional ring regs; NOT power managed + tri_lcbor func_lcbor( + .clkoff_b(lcb_clkoff_dc_b), + .thold(lcb_func_slp_sl_thold_0), + .sg(lcb_sg_0), + .act_dis(lcb_act_dis_dc), + .force_t(func_force), + .thold_b(func_thold_b) + ); + + tri_lcbnd func_lcb( + .act(tieup), // not power managed + .vd(vdd), + .gd(gnd), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .nclk(nclk), + .force_t(func_force), + .sg(lcb_sg_0), + .thold_b(func_thold_b), + .d1clk(func_d1clk), + .d2clk(func_d2clk), + .lclk(func_lclk) + ); + + + // config ring regs; NOT power managed + tri_lcbor mode_lcbor( + .clkoff_b(lcb_clkoff_dc_b), + .thold(lcb_cfg_slp_sl_thold_0), + .sg(lcb_sg_0), + .act_dis(lcb_act_dis_dc), + .force_t(mode_force), + .thold_b(mode_thold_b) + ); + + assign fir_act = sc_active | (|error_in); + + tri_lcbnd mode_lcb( + .act(fir_act), // active during scom access or FIR error input + .vd(vdd), + .gd(gnd), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .nclk(nclk), + .force_t(mode_force), + .sg(lcb_sg_0), + .thold_b(mode_thold_b), + .d1clk(mode_d1clk), + .d2clk(mode_d2clk), + .lclk(mode_lclk) + ); + + tri_lcbnd scom_mode_lcb( + .act(sc_active), // active during scom access + .vd(vdd), + .gd(gnd), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .nclk(nclk), + .force_t(mode_force), + .sg(lcb_sg_0), + .thold_b(mode_thold_b), + .d1clk(scom_mode_d1clk), + .d2clk(scom_mode_d2clk), + .lclk(scom_mode_lclk) + ); + + //-------------------------------------------------------------------- + // Mode Registers + //-------------------------------------------------------------------- + tri_nlat_scan #(.WIDTH(WIDTH), .INIT(FIR_ACTION0_INIT)) fir_action0( + .vd(vdd), + .gd(gnd), + .d1clk(scom_mode_d1clk), + .d2clk(scom_mode_d2clk), + .lclk(scom_mode_lclk), + .scan_in( mode_si[0:WIDTH - 1]), + .scan_out(mode_so[0:WIDTH - 1]), + .din(fir_action0_in), + .q(fir_action0_lt) + ); + + tri_nlat_scan #(.WIDTH(1), .INIT(FIR_ACTION0_PAR_INIT)) fir_action0_par( + .vd(vdd), + .gd(gnd), + .d1clk(scom_mode_d1clk), + .d2clk(scom_mode_d2clk), + .lclk(scom_mode_lclk), + .scan_in( mode_si[WIDTH:WIDTH]), + .scan_out(mode_so[WIDTH:WIDTH]), + .din(fir_action0_par_in), + .q(fir_action0_par_lt) + ); + + tri_nlat_scan #(.WIDTH(WIDTH), .INIT(FIR_ACTION1_INIT)) fir_action1( + .vd(vdd), + .gd(gnd), + .d1clk(scom_mode_d1clk), + .d2clk(scom_mode_d2clk), + .lclk(scom_mode_lclk), + .scan_in( mode_si[(WIDTH + 1):(2*WIDTH)]), + .scan_out(mode_so[(WIDTH + 1):(2*WIDTH)]), + .din(fir_action1_in), + .q(fir_action1_lt) + ); + + tri_nlat_scan #(.WIDTH(1), .INIT(FIR_ACTION1_PAR_INIT)) fir_action1_par( + .vd(vdd), + .gd(gnd), + .d1clk(scom_mode_d1clk), + .d2clk(scom_mode_d2clk), + .lclk(scom_mode_lclk), + .scan_in( mode_si[(2*WIDTH + 1):(2*WIDTH + 1)]), + .scan_out(mode_so[(2*WIDTH + 1):(2*WIDTH + 1)]), + .din(fir_action1_par_in), + .q(fir_action1_par_lt) + ); + + tri_nlat_scan #(.WIDTH(WIDTH), .INIT(FIR_MASK_INIT)) fir_mask( + .vd(vdd), + .gd(gnd), + .d1clk(scom_mode_d1clk), + .d2clk(scom_mode_d2clk), + .lclk(scom_mode_lclk), + .scan_in( mode_si[(2*WIDTH + 2):(3*WIDTH + 1)]), + .scan_out(mode_so[(2*WIDTH + 2):(3*WIDTH + 1)]), + .din(fir_mask_in), + .q(fir_mask_lt) + ); + + tri_nlat_scan #(.WIDTH(1), .INIT(FIR_MASK_PAR_INIT)) fir_mask_par( + .vd(vdd), + .gd(gnd), + .d1clk(scom_mode_d1clk), + .d2clk(scom_mode_d2clk), + .lclk(scom_mode_lclk), + .scan_in( mode_si[(3*WIDTH + 2):(3*WIDTH + 2)]), + .scan_out(mode_so[(3*WIDTH + 2):(3*WIDTH + 2)]), + .din(fir_mask_par_in), + .q(fir_mask_par_lt) + ); + + tri_nlat_scan #(.WIDTH(WIDTH), .INIT(FIR_INIT)) fir( + .vd(vdd), + .gd(gnd), + .d1clk(mode_d1clk), + .d2clk(mode_d2clk), + .lclk(mode_lclk), + .scan_in( mode_si[(3*WIDTH + 3):(4*WIDTH + 2)]), + .scan_out(mode_so[(3*WIDTH + 3):(4*WIDTH + 2)]), + .din(fir_in), + .q(fir_lt) + ); + + + //-------------------------------------------------------------------- + // Func Registers with no power savings + //-------------------------------------------------------------------- + tri_nlat #(.WIDTH(1), .INIT(1'b0)) sys_xstop( + .vd(vdd), + .gd(gnd), + .d1clk(func_d1clk), + .d2clk(func_d2clk), + .lclk(func_lclk), + .scan_in(func_si[1]), + .scan_out(func_so[1]), + .din(sys_xstop_in), + .q(sys_xstop_lt) + ); + + tri_nlat #(.WIDTH(1), .INIT(1'b0)) recov( + .vd(vdd), + .gd(gnd), + .d1clk(func_d1clk), + .d2clk(func_d2clk), + .lclk(func_lclk), + .scan_in(func_si[2]), + .scan_out(func_so[2]), + .din(recov_in), + .q(recov_lt) + ); + + tri_nlat #(.WIDTH(1), .INIT(1'b0)) xstop( + .vd(vdd), + .gd(gnd), + .d1clk(func_d1clk), + .d2clk(func_d2clk), + .lclk(func_lclk), + .scan_in(func_si[3]), + .scan_out(func_so[3]), + .din(xstop_in), + .q(xstop_lt) + ); + + tri_nlat #(.WIDTH(1), .INIT(1'b0)) trace_err( + .vd(vdd), + .gd(gnd), + .d1clk(func_d1clk), + .d2clk(func_d2clk), + .lclk(func_lclk), + .scan_in(func_si[4]), + .scan_out(func_so[4]), + .din(trace_error_in), + .q(trace_error_lt) + ); + + +//****************************************************** +//* Optional Recovery Reset +//****************************************************** + generate + if (USE_RECOV_RESET == 1'b1) + begin : use_recov_reset_yes + assign fir_reset = (~({WIDTH {recov_reset}} & (~fir_action0_lt) & fir_action1_lt)); + end + endgenerate + + generate + if (USE_RECOV_RESET == 1'b0) + begin : use_recov_reset_no + assign fir_reset = {WIDTH {1'b1}}; + end + endgenerate + +//****************************************************** +//* FIR +//****************************************************** + // write to x'0' to write FIR directly + // write to x'1' to And-Mask FIR + // write to x'2' to Or-Mask FIR + assign or_fir_load = (sc_addr_v[0] | sc_addr_v[2]) & sc_wr_q; + assign and_fir_ones = (~((sc_addr_v[0] | sc_addr_v[1]) & sc_wr_q)); + assign and_fir_load = sc_addr_v[1] & sc_wr_q; + + assign or_fir = ({WIDTH {or_fir_load}} & sc_wdata); + assign and_fir = ({WIDTH {and_fir_load}} & sc_wdata) | ({WIDTH {and_fir_ones}} & data_ones); + + + assign fir_in = ({WIDTH {~block_fir}} & error_input) | or_fir | (fir_lt & and_fir & fir_reset); + + + assign fir_error_in_reef = error_in; // does a signal rename for the reef tool + assign error_input = fir_error_in_reef; + +//****************************************************** +//* FIR Mask +//****************************************************** + // write to x'6' to write FIR-MASK directly + // write to x'7' to And-Mask FIR-MASK + // write to x'8' to Or-Mask FIR-MASK + assign or_mask_load = (sc_addr_v[6] | sc_addr_v[8]) & sc_wr_q; + assign and_mask_ones = (~((sc_addr_v[6] | sc_addr_v[7]) & sc_wr_q)); + assign and_mask_load = sc_addr_v[7] & sc_wr_q; + + assign or_mask = ({WIDTH {or_mask_load}} & sc_wdata); + assign and_mask = ({WIDTH {and_mask_load}} & sc_wdata) | ({WIDTH {and_mask_ones}} & data_ones); + + + assign fir_mask_in = or_mask | (fir_mask_lt & and_mask); + + assign fir_mask_par_in = ((sc_wr_q & (|sc_addr_v[6:8])) == 1'b1) ? (^fir_mask_in) : fir_mask_par_lt; + + assign fir_mask_par_err = ((^fir_mask_lt) ^ fir_mask_par_lt) | (sc_wr_q & (|sc_addr_v[6:8]) & sc_parity_error_inject); + + assign masked = fir_mask_lt; + +//****************************************************** +//* Action Registers +//****************************************************** + // write to x'3' to write FIR-Action0 directly + assign fir_action0_in = ((sc_wr_q & sc_addr_v[3]) == 1'b1) ? sc_wdata : fir_action0_lt; + + assign fir_action0_par_in = ((sc_wr_q & sc_addr_v[3]) == 1'b1) ? (^fir_action0_in) : fir_action0_par_lt; + + assign fir_action0_par_err = ((^fir_action0_lt) ^ fir_action0_par_lt) | (sc_wr_q & sc_addr_v[3] & sc_parity_error_inject); + + + // write to x'4' to write FIR-Action1 directly + assign fir_action1_in = ((sc_wr_q & sc_addr_v[4]) == 1'b1) ? sc_wdata : fir_action1_lt; + + assign fir_action1_par_in = ((sc_wr_q & sc_addr_v[4]) == 1'b1) ? (^fir_action1_in) : fir_action1_par_lt; + + assign fir_action1_par_err = ((^fir_action1_lt) ^ fir_action1_par_lt) | (sc_wr_q & sc_addr_v[4] & sc_parity_error_inject); + +//****************************************************** +//* Summary +//****************************************************** + assign xstop_in = (|(fir_lt & fir_action0_lt & (~fir_action1_lt) & (~masked))); // fir_action = 10 + assign recov_in = (|(fir_lt & (~fir_action0_lt) & fir_action1_lt & (~masked))); // fir_action = 01 + + assign block_fir = xstop_lt | sys_xstop_lt; + + assign xstop_err = xstop_lt; + assign recov_err = recov_lt; + assign trace_error = trace_error_lt; + + assign fir_out = fir_lt; + assign act0_out = fir_action0_lt; + assign act1_out = fir_action1_lt; + assign mask_out = fir_mask_lt; + + assign fir_parity_check = {fir_action0_par_err, fir_action1_par_err, fir_mask_par_err}; + +//****************************************************** +//* SCOM read logic +//****************************************************** + assign sc_rdata = ({WIDTH {sc_addr_v[0]}} & fir_lt) | + ({WIDTH {sc_addr_v[3]}} & fir_action0_lt) | + ({WIDTH {sc_addr_v[4]}} & fir_action1_lt) | + ({WIDTH {sc_addr_v[6]}} & fir_mask_lt) ; + +//****************************************************** +//* Optional MCHK Enable Register and Output +//****************************************************** + generate + if (IMPL_LXSTOP_MCHK == 1'b1) + begin : mchkgen + wire lxstop_mchk_in; + wire lxstop_mchk_lt; + + assign lxstop_mchk_in = (|(fir_lt & fir_action0_lt & fir_action1_lt & (~masked))); // fir_action = 11 + assign lxstop_mchk = lxstop_mchk_lt; + + assign trace_error_in = xstop_in | recov_in | lxstop_mchk_in; + + tri_nlat #(.WIDTH(1), .INIT(1'b0)) mchk( + .d1clk(func_d1clk), + .vd(vdd), + .gd(gnd), + .lclk(func_lclk), + .d2clk(func_d2clk), + .scan_in(func_si[0]), + .scan_out(func_so[0]), + .din(lxstop_mchk_in), + .q(lxstop_mchk_lt) + ); + end + endgenerate + + generate + if (IMPL_LXSTOP_MCHK == 1'b0) + begin : nomchk + assign trace_error_in = xstop_in | recov_in; + assign lxstop_mchk = 1'b0; + assign func_so[0] = func_si[0]; + end + endgenerate + +//****************************************************** +// Scan Chain Connections +//****************************************************** + assign mode_si = mode_scan_siv; + assign mode_scan_sov = mode_so; + + assign func_si = func_scan_siv; + assign func_scan_sov = func_so; + + +endmodule diff --git a/dev/verilog/work/pcq_regs.v b/dev/verilog/work/pcq_regs.v new file mode 100755 index 0000000..546fc92 --- /dev/null +++ b/dev/verilog/work/pcq_regs.v @@ -0,0 +1,2412 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +// +// Description: Pervasive Core Registers + Error Reporting +// +//***************************************************************************** + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" + +module pcq_regs( +// Include model build parameters +`include "tri_a2o.vh" + + inout vdd, + inout gnd, + input [0:`NCLK_WIDTH-1] nclk, + input scan_dis_dc_b, + input lcb_clkoff_dc_b, + input lcb_d_mode_dc, + input lcb_mpw1_dc_b, + input lcb_mpw2_dc_b, + input lcb_delay_lclkr_dc, + input lcb_act_dis_dc, + input lcb_func_slp_sl_thold_0, + input lcb_cfg_sl_thold_0, + input lcb_cfg_slp_sl_thold_0, + input lcb_sg_0, + input ccfg_scan_in, + input bcfg_scan_in, + input dcfg_scan_in, + input func_scan_in, + output ccfg_scan_out, + output bcfg_scan_out, + output dcfg_scan_out, + output func_scan_out, + //SCOM Satellite Interface + input [0:3] an_ac_scom_sat_id, + input an_ac_scom_dch, + input an_ac_scom_cch, + output ac_an_scom_dch, + output ac_an_scom_cch, + //FIR and Error Signals + output [0:`THREADS-1] ac_an_special_attn, + output [0:2] ac_an_checkstop, + output [0:2] ac_an_local_checkstop, + output [0:2] ac_an_recov_err, + output ac_an_trace_error, + output rg_ck_fast_xstop, + output ac_an_livelock_active, + input an_ac_checkstop, + input [0:`THREADS-1] fu_pc_err_regfile_parity, + input [0:`THREADS-1] fu_pc_err_regfile_ue, + input iu_pc_err_icache_parity, + input iu_pc_err_icachedir_parity, + input iu_pc_err_icachedir_multihit, + input iu_pc_err_ierat_parity, + input iu_pc_err_ierat_multihit, + input iu_pc_err_btb_parity, + input [0:`THREADS-1] iu_pc_err_cpArray_parity, + input [0:`THREADS-1] iu_pc_err_ucode_illegal, + input [0:`THREADS-1] iu_pc_err_mchk_disabled, + input [0:`THREADS-1] iu_pc_err_debug_event, + input lq_pc_err_dcache_parity, + input lq_pc_err_dcachedir_ldp_parity, + input lq_pc_err_dcachedir_stp_parity, + input lq_pc_err_dcachedir_ldp_multihit, + input lq_pc_err_dcachedir_stp_multihit, + input lq_pc_err_derat_parity, + input lq_pc_err_derat_multihit, + input lq_pc_err_l2intrf_ecc, + input lq_pc_err_l2intrf_ue, + input lq_pc_err_invld_reld, + input lq_pc_err_l2credit_overrun, + input [0:`THREADS-1] lq_pc_err_regfile_parity, + input [0:`THREADS-1] lq_pc_err_regfile_ue, + input lq_pc_err_prefetcher_parity, + input lq_pc_err_relq_parity, + input mm_pc_err_tlb_parity, + input mm_pc_err_tlb_multihit, + input mm_pc_err_tlb_lru_parity, + input mm_pc_err_local_snoop_reject, + input [0:`THREADS-1] xu_pc_err_sprg_ecc, + input [0:`THREADS-1] xu_pc_err_sprg_ue, + input [0:`THREADS-1] xu_pc_err_regfile_parity, + input [0:`THREADS-1] xu_pc_err_regfile_ue, + input [0:`THREADS-1] xu_pc_err_llbust_attempt, + input [0:`THREADS-1] xu_pc_err_llbust_failed, + input [0:`THREADS-1] xu_pc_err_wdt_reset, + input [0:`THREADS-1] iu_pc_err_attention_instr, + output pc_iu_inj_icache_parity, + output pc_iu_inj_icachedir_parity, + output pc_iu_inj_icachedir_multihit, + output pc_lq_inj_dcache_parity, + output pc_lq_inj_dcachedir_ldp_parity, + output pc_lq_inj_dcachedir_stp_parity, + output pc_lq_inj_dcachedir_ldp_multihit, + output pc_lq_inj_dcachedir_stp_multihit, + output pc_lq_inj_prefetcher_parity, + output pc_lq_inj_relq_parity, + output [0:`THREADS-1] pc_xu_inj_sprg_ecc, + output [0:`THREADS-1] pc_fx0_inj_regfile_parity, + output [0:`THREADS-1] pc_fx1_inj_regfile_parity, + output [0:`THREADS-1] pc_lq_inj_regfile_parity, + output [0:`THREADS-1] pc_fu_inj_regfile_parity, + output [0:`THREADS-1] pc_xu_inj_llbust_attempt, + output [0:`THREADS-1] pc_xu_inj_llbust_failed, + output [0:`THREADS-1] pc_iu_inj_cpArray_parity, + // -- Unit quiesce and credit status bits + input [0:`THREADS-1] iu_pc_quiesce, + input [0:`THREADS-1] iu_pc_icache_quiesce, + input [0:`THREADS-1] lq_pc_ldq_quiesce, + input [0:`THREADS-1] lq_pc_stq_quiesce, + input [0:`THREADS-1] lq_pc_pfetch_quiesce, + input [0:`THREADS-1] mm_pc_tlb_req_quiesce, + input [0:`THREADS-1] mm_pc_tlb_ctl_quiesce, + input [0:`THREADS-1] mm_pc_htw_quiesce, + input [0:`THREADS-1] mm_pc_inval_quiesce, + input [0:`THREADS-1] iu_pc_fx0_credit_ok, + input [0:`THREADS-1] iu_pc_fx1_credit_ok, + input [0:`THREADS-1] iu_pc_axu0_credit_ok, + input [0:`THREADS-1] iu_pc_axu1_credit_ok, + input [0:`THREADS-1] iu_pc_lq_credit_ok, + input [0:`THREADS-1] iu_pc_sq_credit_ok, + //SCOM Register Interfaces + // -- RAM Command/Data + output [0:31] pc_iu_ram_instr, + output [0:3] pc_iu_ram_instr_ext, + output [0:`THREADS-1] pc_iu_ram_active, + output pc_iu_ram_execute, + input iu_pc_ram_done, + input iu_pc_ram_interrupt, + input iu_pc_ram_unsupported, + output [0:`THREADS-1] pc_xu_ram_active, + input xu_pc_ram_data_val, + input [64-`GPR_WIDTH:63] xu_pc_ram_data, + output [0:`THREADS-1] pc_fu_ram_active, + input fu_pc_ram_data_val, + input [0:63] fu_pc_ram_data, + output [0:`THREADS-1] pc_lq_ram_active, + input lq_pc_ram_data_val, + input [64-`GPR_WIDTH:63] lq_pc_ram_data, + output pc_xu_msrovride_enab, + output pc_xu_msrovride_pr, + output pc_xu_msrovride_gs, + output pc_xu_msrovride_de, + output pc_iu_ram_force_cmplt, + output [0:`THREADS-1] pc_iu_ram_flush_thread, + output rg_rg_load_sramd, + output [0:63] rg_rg_sramd_din, + // -- THRCTL + PCCR0 Register + output [0:`THREADS-1] ac_an_pm_thread_running, + output [0:`THREADS-1] pc_iu_stop, + output [0:`THREADS-1] pc_iu_step, + output [0:3*`THREADS-1] pc_iu_dbg_action, + output [0:`THREADS-1] pc_iu_spr_dbcr0_edm, + output [0:`THREADS-1] pc_xu_spr_dbcr0_edm, + input [0:`THREADS-1] xu_pc_running, + input [0:`THREADS-1] iu_pc_stop_dbg_event, + input [0:`THREADS-1] xu_pc_stop_dnh_instr, + input [0:`THREADS-1] iu_pc_step_done, + input [0:`THREADS-1] an_ac_pm_thread_stop, + input [0:`THREADS-1] an_ac_pm_fetch_halt, + output [0:`THREADS-1] pc_iu_pm_fetch_halt, + input [0:`THREADS-1] ct_rg_power_managed, + input ct_rg_hold_during_init, + input an_ac_debug_stop, + output pc_xu_extirpts_dis_on_stop, + output pc_xu_timebase_dis_on_stop, + output pc_xu_decrem_dis_on_stop, + output rg_ct_dis_pwr_savings, + // --Debug Select Register outputs to units for debug grouping + input sp_rg_trace_bus_enable, + output rg_db_trace_bus_enable, + output pc_iu_trace_bus_enable, + output pc_fu_trace_bus_enable, + output pc_rv_trace_bus_enable, + output pc_mm_trace_bus_enable, + output pc_xu_trace_bus_enable, + output pc_lq_trace_bus_enable, + output [0:10] rg_db_debug_mux_ctrls, + output [0:10] pc_iu_debug_mux1_ctrls, + output [0:10] pc_iu_debug_mux2_ctrls, + output [0:10] pc_fu_debug_mux_ctrls, + output [0:10] pc_rv_debug_mux_ctrls, + output [0:10] pc_mm_debug_mux_ctrls, + output [0:10] pc_xu_debug_mux_ctrls, + output [0:10] pc_lq_debug_mux1_ctrls, + output [0:10] pc_lq_debug_mux2_ctrls, + //Debug Signals to Trace Muxes + output [0:11] dbg_scom, + output [0:24] dbg_thrctls, + output [0:15] dbg_ram, + output [0:27] dbg_fir0_err, + output [0:19] dbg_fir1_err, + output [0:19] dbg_fir2_err, + output [0:14] dbg_fir_misc +); + + +//===================================================================== +// Signal Declarations +//===================================================================== + // ram registers + parameter RAMI_SIZE = 32; + parameter RAMC_SIZE = 23; + parameter RAMD_SIZE = 64; + parameter FU_RAM_DIN_SIZE = 64; + parameter XU_RAM_DIN_SIZE = `GPR_WIDTH + 1; + parameter LQ_RAM_DIN_SIZE = `GPR_WIDTH + 1; + // debug control registers + parameter THRCTL1_SIZE = 7 * `THREADS + 5; + parameter THRCTL2_SIZE = 8; + parameter PCCR0_SIZE = 3 * `THREADS + 12; + parameter RECERRCNTR_SIZE = 4; + parameter SPATTN_USED = 1 * `THREADS; +`ifdef THREADS1 + parameter SPATTN_PARITY_INIT = 1; +`else + parameter SPATTN_PARITY_INIT = 0; +`endif + // mux select registers + parameter ARDSR_SIZE = 22; + parameter IDSR_SIZE = 22; + parameter MPDSR_SIZE = 22; + parameter XDSR_SIZE = 11; + parameter LDSR_SIZE = 22; + // misc functions + parameter ERRINJ_SIZE = 23 + 9 * (`THREADS - 1); + parameter PARITY_SIZE = 1; + parameter SCOM_MISC_SIZE = 8; + parameter ERRDBG_T0_SIZE = 15; + parameter ERRDBG_T1_SIZE = 15 * (`THREADS - 1); + // repower/timing latches + parameter DCFG_STAGE1_SIZE = 4; + parameter BCFG_STAGE1_T0_SIZE = 8; + parameter BCFG_STAGE1_T1_SIZE = 7 * (`THREADS - 1); + parameter BCFG_STAGE2_T0_SIZE = 7; + parameter BCFG_STAGE2_T1_SIZE = 4 * (`THREADS - 1); + parameter FUNC_STAGE1_SIZE = 2; + parameter INJ_STAGE1_T0_SIZE = 18; + parameter INJ_STAGE1_T1_SIZE = 8; + parameter FUNC_STAGE3_SIZE = 17; + + //--------------------------------------------------------------------- + // Scan Ring Ordering: + // start of dcfg scan chain ordering + parameter ARDSR_OFFSET = 0; + parameter IDSR_OFFSET = ARDSR_OFFSET + ARDSR_SIZE; + parameter MPDSR_OFFSET = IDSR_OFFSET + IDSR_SIZE; + parameter XDSR_OFFSET = MPDSR_OFFSET + MPDSR_SIZE; + parameter LDSR_OFFSET = XDSR_OFFSET + XDSR_SIZE; + parameter PCCR0_OFFSET = LDSR_OFFSET + LDSR_SIZE; + parameter RECERRCNTR_OFFSET = PCCR0_OFFSET + PCCR0_SIZE; + parameter PCCR0_PAR_OFFSET = RECERRCNTR_OFFSET + RECERRCNTR_SIZE; + parameter DCFG_STAGE1_OFFSET = PCCR0_PAR_OFFSET + PARITY_SIZE; + parameter DCFG_RIGHT = DCFG_STAGE1_OFFSET + DCFG_STAGE1_SIZE - 1; + // end of dcfg scan chain ordering + // start of bcfg scan chain ordering + parameter SCOMMODE_OFFSET = 0; + parameter THRCTL1_OFFSET = SCOMMODE_OFFSET + 2; + parameter THRCTL2_OFFSET = THRCTL1_OFFSET + THRCTL1_SIZE; + parameter SPATTN_DATA_OFFSET = THRCTL2_OFFSET + THRCTL2_SIZE; + parameter SPATTN_MASK_OFFSET = SPATTN_DATA_OFFSET + SPATTN_USED; + parameter SPATTN_PAR_OFFSET = SPATTN_MASK_OFFSET + SPATTN_USED; + parameter BCFG_STAGE1_T0_OFFSET = SPATTN_PAR_OFFSET + PARITY_SIZE; + parameter BCFG_STAGE1_T1_OFFSET = BCFG_STAGE1_T0_OFFSET + BCFG_STAGE1_T0_SIZE; + parameter BCFG_STAGE2_T0_OFFSET = BCFG_STAGE1_T1_OFFSET + BCFG_STAGE1_T1_SIZE; + parameter BCFG_STAGE2_T1_OFFSET = BCFG_STAGE2_T0_OFFSET + BCFG_STAGE2_T0_SIZE; + parameter ERRDBG_T0_OFFSET = BCFG_STAGE2_T1_OFFSET + BCFG_STAGE2_T1_SIZE; + parameter ERRDBG_T1_OFFSET = ERRDBG_T0_OFFSET + ERRDBG_T0_SIZE; + parameter BCFG_RIGHT = ERRDBG_T1_OFFSET + ERRDBG_T1_SIZE - 1; + // end of bcfg scan chain ordering + // start of func scan chain ordering + parameter RAMI_OFFSET = 0; + parameter RAMC_OFFSET = RAMI_OFFSET + RAMI_SIZE; + parameter RAMD_OFFSET = RAMC_OFFSET + RAMC_SIZE; + parameter FU_RAM_DIN_OFFSET = RAMD_OFFSET + RAMD_SIZE; + parameter XU_RAM_DIN_OFFSET = FU_RAM_DIN_OFFSET + FU_RAM_DIN_SIZE; + parameter LQ_RAM_DIN_OFFSET = XU_RAM_DIN_OFFSET + XU_RAM_DIN_SIZE; + parameter ERRINJ_OFFSET = LQ_RAM_DIN_OFFSET + LQ_RAM_DIN_SIZE; + parameter SC_MISC_OFFSET = ERRINJ_OFFSET + ERRINJ_SIZE; + parameter SCADDR_DEC_OFFSET = SC_MISC_OFFSET + SCOM_MISC_SIZE; + parameter FUNC_STAGE1_OFFSET = SCADDR_DEC_OFFSET + 64; + parameter INJ_STAGE1_T0_OFFSET = FUNC_STAGE1_OFFSET + FUNC_STAGE1_SIZE; + parameter INJ_STAGE1_T1_OFFSET = INJ_STAGE1_T0_OFFSET + INJ_STAGE1_T0_SIZE; + parameter FUNC_STAGE3_OFFSET = INJ_STAGE1_T1_OFFSET + INJ_STAGE1_T1_SIZE; + parameter SCOMFUNC_OFFSET = FUNC_STAGE3_OFFSET + FUNC_STAGE3_SIZE; + parameter FUNC_RIGHT = SCOMFUNC_OFFSET + 177 - 1; + // end of func scan chain ordering + + //--------------------------------------------------------------------- + // start of scom register addresses + parameter SCOM_WIDTH = 64; + // 0000000000111111111122222222223333333333444444444455555555556666 + // 0123456789012345678901234567890123456789012345678901234567890123 + parameter USE_ADDR = 64'b1111111111111110111111111011100000000000111111111111111110011111; + parameter ADDR_IS_RDABLE = 64'b1001111001100110100110011010000000000000111001111001001000011111; + parameter ADDR_IS_WRABLE = 64'b1111101111111110111011111011100000000000111111111111111110011111; + // end of scom register addresses + + //--------------------------------------------------------------------- + // Clock+Scan signals + wire tidn; + wire tiup; + wire [0:31] tidn_32; + wire [0:BCFG_RIGHT] bcfg_siv; + wire [0:BCFG_RIGHT] bcfg_sov; + wire [0:DCFG_RIGHT] dcfg_siv; + wire [0:DCFG_RIGHT] dcfg_sov; + wire [0:FUNC_RIGHT] func_siv; + wire [0:FUNC_RIGHT] func_sov; + wire lcb_func_slp_sl_thold_0_b; + wire lcb_cfg_slp_sl_thold_0_b; + wire force_cfgslp; + wire force_funcslp; + wire cfgslp_d1clk; + wire cfgslp_d2clk; + wire [0:`NCLK_WIDTH-1] cfgslp_lclk; + wire cfg_slat_force; + wire cfg_slat_d2clk; + wire [0:`NCLK_WIDTH-1] cfg_slat_lclk; + wire cfg_slat_thold_b; + // SCOM satellite/decode signals + wire scom_cch_q; + wire scom_dch_q; + wire scom_act; + wire scom_local_act; + wire scom_wr_act; + wire sc_r_nw; + wire sc_ack; + wire [0:63] sc_rdata; + wire [0:63] sc_wdata; + wire [0:1] sc_ack_info; + wire sc_wparity_out; + wire sc_wparity; + wire scom_fsm_err; + wire scom_ack_err; + wire [0:5] scaddr_predecode; + wire [0:63] scaddr_dec_d; + wire [0:63] scaddr_v; + wire [0:63] andmask_ones; + wire sc_req_d; + wire sc_req_q; + wire sc_wr_d; + wire sc_wr_q; + wire [0:63] scaddr_v_d; + wire [0:63] scaddr_v_q; + wire scaddr_nvld_d; + wire scaddr_nvld_q; + wire sc_wr_nvld_d; + wire sc_wr_nvld_q; + wire sc_rd_nvld_d; + wire sc_rd_nvld_q; + // RAM related signals + wire [0:3] ramc_instr_in; + wire ramc_mode_in; + wire ramc_thread_in; + wire ramc_execute_in; + wire [0:3] ramc_msr_ovrid_in; + wire ramc_force_cmplt_in; + wire [0:1] ramc_force_flush_in; + wire [0:3] ramc_spare_in; + wire [0:4] ramc_status_in; + wire or_ramc_load; + wire and_ramc_ones; + wire and_ramc_load; + wire [0:63] or_ramc; + wire [0:63] and_ramc; + wire [0:RAMI_SIZE-1] rami_d; + wire [0:RAMI_SIZE-1] rami_q; + wire [0:63] rami_out; + wire [0:RAMC_SIZE-1] ramc_d; + wire [0:RAMC_SIZE-1] ramc_q; + wire [0:63] ramc_out; + wire [0:63] ramic_out; + wire [0:RAMD_SIZE-1] ramd_d; + wire [0:RAMD_SIZE-1] ramd_q; + wire [0:63] ramdh_out; + wire [0:63] ramdl_out; + wire rg_rg_ram_mode; + wire [0:64-`GPR_WIDTH] ramd_load_zeros; + wire [0:64] xu_ramd_load_data_d; + wire [0:64] xu_ramd_load_data_q; + wire [0:63] xu_ramd_load_data; + wire [0:63] fu_ramd_load_data_d; + wire [0:63] fu_ramd_load_data_q; + wire [0:64] lq_ramd_load_data_d; + wire [0:64] lq_ramd_load_data_q; + wire [0:63] lq_ramd_load_data; + wire xu_ram_data_val_q; + wire fu_ram_data_val_q; + wire lq_ram_data_val_q; + wire ram_mode_d; + wire ram_mode_q; + wire [0:`THREADS-1] ram_active_out; + wire [0:1] ram_active_d; + wire [0:1] ram_active_q; + wire ram_execute_d; + wire ram_execute_q; + wire ram_unsupported_q; + wire ram_interrupt_q; + wire ram_done_q; + wire ram_msrovren_d; + wire ram_msrovren_q; + wire ram_msrovrpr_d; + wire ram_msrovrpr_q; + wire ram_msrovrgs_d; + wire ram_msrovrgs_q; + wire ram_msrovrde_d; + wire ram_msrovrde_q; + wire ram_force_d; + wire ram_force_q; + wire [0:1] ram_flush_d; + wire [0:1] ram_flush_q; + wire load_sramd_d; + wire load_sramd_q; + wire [0:1] ramCmpltCntr_in; + wire [0:1] ramCmpltCntr_q; + wire rammed_thrd_running; + wire rammed_thrd_running_chk; + wire two_ram_executes_chk; + wire ram_mode_ends_wo_done_chk; + wire rammed_instr_overrun; + wire ramc_error_status; + // THRCTL related signals + wire or_thrctl_load; + wire and_thrctl_ones; + wire and_thrctl_load; + wire [0:63] or_thrctl; + wire [0:63] and_thrctl; + wire [0:63] thrctl_out; + wire [0:THRCTL1_SIZE-1] thrctl1_d; + wire [0:THRCTL1_SIZE-1] thrctl1_q; + wire [0:THRCTL2_SIZE-1] thrctl2_d; + wire [0:THRCTL2_SIZE-1] thrctl2_q; + wire [0:`THREADS-1] thrctl_stop_in; + wire [0:`THREADS-1] thrctl_step_in; + wire [0:`THREADS-1] thrctl_run_in; + wire thrctl_debug_stop_in; + wire [0:3+(4*(`THREADS-1))] thrctl_stop_summary_in; + wire [0:1] thrctl_spare1_in; + wire thrctl_step_ovrun_in; + wire thrctl_ramc_err_in; + wire [0:2] thrctl_misc_dbg_in; + wire [0:4] thrctl_spare2_in; + wire [0:`THREADS-1] tx_stop_d; + wire [0:`THREADS-1] tx_stop_q; + wire extirpts_dis_d; + wire extirpts_dis_q; + wire timebase_dis_d; + wire timebase_dis_q; + wire decrem_dis_d; + wire decrem_dis_q; + wire ext_debug_stop_q; + wire [0:`THREADS-1] external_debug_stop; + wire [0:`THREADS-1] stop_dbg_event_q; + wire [0:`THREADS-1] stop_dbg_dnh_q; + wire [0:`THREADS-1] stop_for_debug; + wire [0:`THREADS-1] pm_thread_stop_q; + wire [0:`THREADS-1] pm_fetch_halt_q; + wire [0:`THREADS-1] step_done_q; + wire [0:`THREADS-1] tx_step_d; + wire [0:`THREADS-1] tx_step_q; + wire [0:`THREADS-1] tx_step_req_d; + wire [0:`THREADS-1] tx_step_req_q; + wire [0:`THREADS-1] tx_step_val_d; + wire [0:`THREADS-1] tx_step_val_q; + wire [0:`THREADS-1] tx_step_overrun; + wire instr_step_overrun; + // PCCR0 related signals + wire or_pccr0_load; + wire and_pccr0_ones; + wire and_pccr0_load; + wire [0:63] or_pccr0; + wire [0:63] and_pccr0; + wire [0:63] pccr0_out; + wire pccr0_par_err; + wire [0:PCCR0_SIZE+4-1] pccr0_par_in; + wire [0:PCCR0_SIZE-1] pccr0_d; + wire [0:PCCR0_SIZE-1] pccr0_q; + wire [0:0] pccr0_par_d; + wire [0:0] pccr0_par_q; + wire debug_mode_d; + wire debug_mode_q; + wire debug_mode_act; + wire trace_bus_enable_d; + wire trace_bus_enable_q; + wire ram_enab_d; + wire ram_enab_q; + wire ram_enab_act; + wire ram_ctrl_act; + wire ram_data_act; + wire errinj_enab_d; + wire errinj_enab_q; + wire errinj_enab_act; + wire errinj_enab_scom_act; + wire rg_rg_xstop_report_ovride; + wire rg_rg_fast_xstop_enable; + wire rg_rg_dis_overrun_chks; + wire rg_rg_maxRecErrCntrValue; + wire rg_rg_gateRecErrCntr; + wire recErrCntr_pargen; + wire [0:3] incr_recErrCntr; + wire [0:3] recErrCntr_in; + wire [0:3] recErrCntr_q; + wire [0:7] pccr0_pervModes_in; + wire [0:3] pccr0_spare_in; + wire [0:3*`THREADS-1] pccr0_dbgActSel_in; + wire [0:`THREADS-1] pccr0_dba_active_d; + wire [0:`THREADS-1] pccr0_dba_active_q; + // spattn related signals + wire or_spattn_load; + wire and_spattn_ones; + wire and_spattn_load; + wire [0:63] or_spattn; + wire [0:63] and_spattn; + wire [0:63] spattn_out; + wire spattn_par_err; + wire [0:0] spattn_par_d; + wire [0:0] spattn_par_q; + wire [0:SPATTN_USED-1] spattn_data_d; + wire [0:SPATTN_USED-1] spattn_data_q; + wire [0:SPATTN_USED-1] spattn_mask_d; + wire [0:SPATTN_USED-1] spattn_mask_q; + wire [0:SPATTN_USED-1] spattn_out_masked; + wire [SPATTN_USED:15] spattn_unused; + wire [0:`THREADS-1] spattn_attn_instr_in; + wire [0:`THREADS-1] err_attention_instr_q; + // Debug related signals + wire [0:ARDSR_SIZE-1] ardsr_data_in; + wire [0:63] ardsr_out; + wire [0:ARDSR_SIZE-1] ardsr_d; + wire [0:ARDSR_SIZE-1] ardsr_q; + wire [0:IDSR_SIZE-1] idsr_data_in; + wire [0:63] idsr_out; + wire [0:IDSR_SIZE-1] idsr_d; + wire [0:IDSR_SIZE-1] idsr_q; + wire [0:MPDSR_SIZE-1] mpdsr_data_in; + wire [0:63] mpdsr_out; + wire [0:MPDSR_SIZE-1] mpdsr_d; + wire [0:MPDSR_SIZE-1] mpdsr_q; + wire [0:XDSR_SIZE-1] xdsr_data_in; + wire [0:63] xdsr_out; + wire [0:XDSR_SIZE-1] xdsr_d; + wire [0:XDSR_SIZE-1] xdsr_q; + wire [0:LDSR_SIZE-1] ldsr_data_in; + wire [0:63] ldsr_out; + wire [0:LDSR_SIZE-1] ldsr_d; + wire [0:LDSR_SIZE-1] ldsr_q; + // FIR + ERROR RELATed signals + wire [0:63] errinj_out; + wire [0:ERRINJ_SIZE-1] errinj_errtype_in; + wire [0:ERRINJ_SIZE-1] errinj_d; + wire [0:ERRINJ_SIZE-1] errinj_q; + wire rg_rg_ram_mode_xstop; + wire [0:`THREADS-1] rg_rg_xstop_err; + wire rg_rg_any_fir_xstop; + wire [0:1] scom_reg_par_checks; + wire scaddr_fir; + wire fir_func_si; + wire fir_func_so; + wire fir_mode_si; + wire fir_mode_so; + wire [0:63] fir_data_out; + wire [0:ERRINJ_SIZE-1] rg_rg_errinj_shutoff; + wire sc_parity_error_inj; + wire inj_icache_parity_d; + wire inj_icache_parity_q; + wire inj_icachedir_parity_d; + wire inj_icachedir_parity_q; + wire inj_icachedir_multihit_d; + wire inj_icachedir_multihit_q; + wire inj_dcache_parity_d; + wire inj_dcache_parity_q; + wire inj_dcachedir_ldp_parity_d; + wire inj_dcachedir_ldp_parity_q; + wire inj_dcachedir_stp_parity_d; + wire inj_dcachedir_stp_parity_q; + wire inj_dcachedir_ldp_multihit_d; + wire inj_dcachedir_ldp_multihit_q; + wire inj_dcachedir_stp_multihit_d; + wire inj_dcachedir_stp_multihit_q; + wire inj_prefetcher_parity_d; + wire inj_prefetcher_parity_q; + wire inj_relq_parity_d; + wire inj_relq_parity_q; + wire [0:`THREADS-1] inj_sprg_ecc_d; + wire [0:`THREADS-1] inj_sprg_ecc_q; + wire [0:`THREADS-1] inj_fx0regfile_parity_d; + wire [0:`THREADS-1] inj_fx0regfile_parity_q; + wire [0:`THREADS-1] inj_fx1regfile_parity_d; + wire [0:`THREADS-1] inj_fx1regfile_parity_q; + wire [0:`THREADS-1] inj_lqregfile_parity_d; + wire [0:`THREADS-1] inj_lqregfile_parity_q; + wire [0:`THREADS-1] inj_furegfile_parity_d; + wire [0:`THREADS-1] inj_furegfile_parity_q; + wire [0:`THREADS-1] inj_llbust_attempt_d; + wire [0:`THREADS-1] inj_llbust_attempt_q; + wire [0:`THREADS-1] inj_llbust_failed_d; + wire [0:`THREADS-1] inj_llbust_failed_q; + wire [0:`THREADS-1] inj_cpArray_parity_d; + wire [0:`THREADS-1] inj_cpArray_parity_q; + wire [0:ERRDBG_T0_SIZE-1] errDbg_t0_d; + wire [0:ERRDBG_T0_SIZE-1] errDbg_t0_q; + wire [0:ERRDBG_T1_SIZE-1] errDbg_t1_d; + wire [0:ERRDBG_T1_SIZE-1] errDbg_t1_q; + wire [0:31] errDbg_out; + // Miscellaneous signals + wire [0:1] dbg_ram_active_q; + wire [0:1] dbg_spattn_data_q; + wire [0:1] dbg_stop_dbg_event_q; + wire [0:1] dbg_stop_dbg_dnh_q; + wire [0:1] dbg_power_managed_q; + wire [0:1] dbg_pm_thread_stop_q; + wire [0:1] dbg_tx_stop_q; + wire [0:1] dbg_thread_running_q; + wire [0:1] dbg_tx_step_q; + wire [0:1] dbg_tx_step_done_q; + wire [0:1] dbg_tx_step_req_q; + wire ram_thread; + + +(* analysis_not_referenced="true" *) + wire unused_signals; + assign unused_signals = + (|{or_ramc[0:31], or_ramc[36:43], or_ramc[45], or_ramc[56:58], and_ramc[0:31], + and_ramc[36:43], and_ramc[45], and_ramc[47], and_ramc[53:54], and_ramc[56:58], + xu_ramd_load_data_q[0], lq_ramd_load_data_q[0], or_thrctl[0:31], or_thrctl[34:35], + or_thrctl[38:44], or_thrctl[48], and_thrctl[0:31], and_thrctl[34:35], and_thrctl[38:44], + and_thrctl[48], or_pccr0[0:31], or_pccr0[44:52], or_pccr0[56], or_pccr0[60:63], + and_pccr0[0:31], and_pccr0[44:52], and_pccr0[56], and_pccr0[60:63], or_spattn[0:31], + or_spattn[34:47], or_spattn[50:63], and_spattn[0:31], and_spattn[34:47], and_spattn[50:63], + sc_wparity + }); + + +//--------------------------------------------------------------------- +//!! Bugspray Include: pcq_regs; +// --## figtree_source pcq_regs.fig + + + assign tidn = 1'b0; + assign tidn_32 = {32 {1'b0}}; + assign tiup = 1'b1; + +//===================================================================== +// SCOM Satellite and Controls +//===================================================================== + tri_serial_scom2 #(.WIDTH(SCOM_WIDTH), .INTERNAL_ADDR_DECODE(1'b0), .PIPELINE_PARITYCHK(1'b0)) scomsat( + // Global lines for clocking and cop control + .nclk(nclk), + .vdd(vdd), + .gnd(gnd), + .scom_func_thold(lcb_func_slp_sl_thold_0), + .sg(lcb_sg_0), + .act_dis_dc(lcb_act_dis_dc), + .clkoff_dc_b(lcb_clkoff_dc_b), + .mpw1_dc_b(lcb_mpw1_dc_b), + .mpw2_dc_b(lcb_mpw2_dc_b), + .d_mode_dc(lcb_d_mode_dc), + .delay_lclkr_dc(lcb_delay_lclkr_dc), + .func_scan_in(func_siv[ SCOMFUNC_OFFSET:SCOMFUNC_OFFSET + SCOM_WIDTH + 2 * ((SCOM_WIDTH - 1)/16 + 1) + 104]), + .func_scan_out(func_sov[SCOMFUNC_OFFSET:SCOMFUNC_OFFSET + SCOM_WIDTH + 2 * ((SCOM_WIDTH - 1)/16 + 1) + 104]), + .dcfg_scan_dclk(cfg_slat_d2clk), + .dcfg_scan_lclk(cfg_slat_lclk), + .dcfg_d1clk(cfgslp_d1clk), + .dcfg_d2clk(cfgslp_d2clk), + .dcfg_lclk(cfgslp_lclk), + .dcfg_scan_in(bcfg_siv[ SCOMMODE_OFFSET:SCOMMODE_OFFSET + 1]), + .dcfg_scan_out(bcfg_sov[SCOMMODE_OFFSET:SCOMMODE_OFFSET + 1]), + //------------------------------------------------------------------- + // Global SCOM interface + //------------------------------------------------------------------- + .scom_local_act(scom_local_act), + // tie to VDD/GND to program the base address ranges + .sat_id(an_ac_scom_sat_id), + // global serial lines to top level of macro + .scom_dch_in(scom_dch_q), + .scom_cch_in(scom_cch_q), + .scom_dch_out(ac_an_scom_dch), + .scom_cch_out(ac_an_scom_cch), + //------------------------------------------------------------------- + // Internal SCOM interface to parallel registers + //------------------------------------------------------------------- + // address/control interface + .sc_req(sc_req_d), + .sc_ack(sc_ack), + .sc_ack_info(sc_ack_info), + .sc_r_nw(sc_r_nw), + .sc_addr(scaddr_predecode), + .sc_rdata(sc_rdata), + .sc_wdata(sc_wdata), + .sc_wparity(sc_wparity_out), + .scom_err(scom_fsm_err), + .fsm_reset(tidn) + ); + + tri_scom_addr_decode #(.USE_ADDR(USE_ADDR), .ADDR_IS_RDABLE(ADDR_IS_RDABLE), .ADDR_IS_WRABLE(ADDR_IS_WRABLE)) scaddr( + .sc_addr(scaddr_predecode), // binary coded scom address + .scaddr_dec(scaddr_dec_d), // one hot coded scom address, not latched + .sc_req(sc_req_d), // scom request + .sc_r_nw(sc_r_nw), // read / not write bit + .scaddr_nvld(scaddr_nvld_d), // scom address not valid; not latched + .sc_wr_nvld(sc_wr_nvld_d), // scom write not allowed, not latched + .sc_rd_nvld(sc_rd_nvld_d), // scom read not allowed, not latched + .vd(vdd), + .gd(gnd) + ); + + + assign scom_act = sc_req_d | sc_req_q | scom_local_act; + assign scom_wr_act = scom_act & sc_wr_q; + + assign sc_wr_d = (~sc_r_nw); + + assign scaddr_v_d = {SCOM_WIDTH {sc_req_d}} & scaddr_dec_d; + assign scaddr_v = scaddr_v_q; + + assign sc_ack = (sc_req_d & (~sc_r_nw)) | (sc_req_q & sc_r_nw); + + assign sc_ack_info = ({2 {(~sc_r_nw)}} & {(sc_wr_nvld_d | sc_rd_nvld_d), scaddr_nvld_d}) | + ({2 { sc_r_nw }} & {(sc_wr_nvld_q | sc_rd_nvld_q), scaddr_nvld_q}) ; + + assign scom_ack_err = (|sc_ack_info); + + assign sc_wparity = sc_wparity_out ^ sc_parity_error_inj; + + + //===================================================================== + // SCOM Register Writes + //===================================================================== + assign andmask_ones = {SCOM_WIDTH {1'b1}}; + + //--------------------------------------------------------------------- + // RAM Instruction Register ------------------------------------------- + // RAMIC RW address = 40 + // RAMI RW address = 41 + + assign rami_d[0:31] = ((scaddr_v[40] & sc_wr_q) == 1'b1) ? sc_wdata[0:31] : + ((scaddr_v[41] & sc_wr_q) == 1'b1) ? sc_wdata[32:63] : + rami_q[0:31]; + + assign rami_out = {tidn_32, rami_q[0:31]}; + + assign ramic_out = {rami_out[32:63], ramc_out[32:63]}; + + + //--------------------------------------------------------------------- + // RAM Control Register ----------------------------------------------- + // RAMIC RW address = 40 + // RAMC RW address = 42 + // RAMC WO with and-mask = 43 + // RAMC WO with or-mask = 44 + + assign or_ramc_load = (scaddr_v[40] | scaddr_v[42] | scaddr_v[44]) & sc_wr_q; + assign and_ramc_ones = (~((scaddr_v[40] | scaddr_v[42] | scaddr_v[43]) & sc_wr_q)); + assign and_ramc_load = scaddr_v[43] & sc_wr_q; + + assign or_ramc = {SCOM_WIDTH {or_ramc_load}} & sc_wdata; + assign and_ramc = ({SCOM_WIDTH {and_ramc_load}} & sc_wdata) | ({SCOM_WIDTH {and_ramc_ones}} & andmask_ones); + + // Instruction fields: set by SCOM; reset by SCOM + assign ramc_instr_in = or_ramc[32:35] | (ramc_out[32:35] & and_ramc[32:35]); + + // Mode bit: set by SCOM; reset by SCOM + assign ramc_mode_in = or_ramc[44] | (ramc_out[44] & and_ramc[44]); + + // Thread bit: set by SCOM; reset by SCOM + // Note: Bit 45 is unimplemented + assign ramc_thread_in = or_ramc[46] | (ramc_out[46] & and_ramc[46]); + + // Execute bit: not latched; pulsed by SCOM write + assign ramc_execute_in = or_ramc[47]; + + // MSR Override control bits: set by SCOM; reset by SCOM + assign ramc_msr_ovrid_in = or_ramc[48:51] | (ramc_out[48:51] & and_ramc[48:51]); + + // Force Ram Completion bit: set by SCOM; reset by SCOM + assign ramc_force_cmplt_in = or_ramc[52] | (ramc_out[52] & and_ramc[52]); + + // Force Flush bits: not latched; pulsed by SCOM write. + assign ramc_force_flush_in = or_ramc[53:54]; + + // Spare bits: set by SCOM; reset by SCOM + assign ramc_spare_in = or_ramc[55:58] | (ramc_out[55:58] & and_ramc[55:58]); + + // Unsupported bit: set by SCOM + iu Unsupported signal; reset by SCOM + assign ramc_status_in[0] = ram_unsupported_q | or_ramc[59] | (ramc_out[59] & and_ramc[59]); + + // Overrun bit: set by SCOM + rammed_instr_overrun signal; reset by SCOM + assign ramc_status_in[1] = rammed_instr_overrun | or_ramc[60] | (ramc_out[60] & and_ramc[60]); + + // Interrupt bit: set by SCOM + iu Interrupt signal; reset by SCOM + assign ramc_status_in[2] = ram_interrupt_q | or_ramc[61] | (ramc_out[61] & and_ramc[61]); + + // Checkstop bit: set by SCOM + Rammed `THREADS checkstop bit; reset by SCOM + assign ramc_status_in[3] = rg_rg_ram_mode_xstop | or_ramc[62] | (ramc_out[62] & and_ramc[62]); + + // Done bit: set by SCOM + iu Done signals; reset by SCOM + RAMC_execute + assign ramc_status_in[4] = ram_done_q | or_ramc[63] | (ramc_out[63] & and_ramc[63] & (~ramc_out[47])); + + assign ramc_d = {ramc_instr_in, ramc_mode_in, ramc_thread_in, ramc_execute_in, + ramc_msr_ovrid_in, ramc_force_cmplt_in, ramc_force_flush_in, ramc_spare_in, + ramc_status_in }; + + // Instr Exten Mode Thread+Exec MSR Overrides + assign ramc_out = {tidn_32, ramc_q[0:3], 8'h00, ramc_q[4], 1'b0, ramc_q[5:6], ramc_q[7:10], + // MSR Forces Spare Ltchs Status + ramc_q[11:13], ramc_q[14:17], ramc_q[18:22] }; + + // --------------------------- + // RAMC Controls and Overrun Checking Logic: + assign ram_mode_d = ram_enab_d & ramc_out[44]; + assign ram_thread = ramc_out[46]; + assign ram_execute_d = ram_mode_d & ramc_out[47] & (~rammed_instr_overrun); + + // ram_active_q set same time as ram_execute_q; cleared when IU activates ram_done_q. + assign ram_active_d[0] = (ram_execute_d & (~ram_thread)) | ((~ram_done_q) & ram_active_q[0]); + assign ram_active_d[1] = (ram_execute_d & ram_thread ) | ((~ram_done_q) & ram_active_q[1]); + + generate + if (`THREADS == 1) + begin : T1_RAMCTRL + assign rammed_thrd_running = (~ram_thread) & thrctl_out[40]; + assign ram_active_out = ram_active_q[0]; + end + endgenerate + generate + if (`THREADS == 2) + begin : T2_RAMCTRL + assign rammed_thrd_running = ((~ram_thread) & thrctl_out[40]) | (ram_thread & thrctl_out[41]); + assign ram_active_out = ram_active_q[0:1]; + end + endgenerate + + assign ramCmpltCntr_in = (ram_mode_d == 1'b0) ? 2'b00 : + (ram_execute_q == 1'b1) ? (ramCmpltCntr_q + 2'b01) : + (ram_done_q == 1'b1) ? (ramCmpltCntr_q - 2'b01) : + ramCmpltCntr_q[0:1]; + + // OVERRUN CHECK 1: RAMC[EXEC] pulses while the Rammed thread is still running + assign rammed_thrd_running_chk = ram_mode_d & ramc_out[47] & rammed_thrd_running; + // OVERRUN CHECK 2: Two consecutive ram_execute pulses without receiving a ram_done + assign two_ram_executes_chk = ramc_out[47] & (~ramCmpltCntr_q[0]) & ramCmpltCntr_q[1]; + // OVERRUN CHECK 3: Counter not cleared when ram_mode goes inactive. + assign ram_mode_ends_wo_done_chk = (~ram_mode_d) & ram_mode_q & (|ramCmpltCntr_q[0:1]); + // --------------------------- + assign rammed_instr_overrun = (rammed_thrd_running_chk | two_ram_executes_chk | ram_mode_ends_wo_done_chk) & (~rg_rg_dis_overrun_chks); + // --------------------------- + + // RAMC status summary signal; sets Ram "sticky" status bit in thread status register. + assign ramc_error_status = ram_unsupported_q | rammed_instr_overrun | ram_interrupt_q | rg_rg_ram_mode_xstop; + + + //--------------------------------------------------------------------- + // RAM Data Register ------------------------------------------------- + // RAMD R/W address = 45 + // RAMDH R/W address = 46 + // RAMDL R/W address = 47 + + assign fu_ramd_load_data_d = fu_pc_ram_data[0:63]; + + // For XU+LQ, adjusting size of RAM data when compiled as 32-bit core. + assign ramd_load_zeros = {65-`GPR_WIDTH {1'b0}}; + assign xu_ramd_load_data_d[0:64] = {ramd_load_zeros, xu_pc_ram_data[64-`GPR_WIDTH:63]}; + assign xu_ramd_load_data[0:63] = xu_ramd_load_data_q[1:64]; + + assign lq_ramd_load_data_d[0:64] = {ramd_load_zeros, lq_pc_ram_data[64-`GPR_WIDTH:63]}; + assign lq_ramd_load_data[0:63] = lq_ramd_load_data_q[1:64]; + + // Latch Ram data from SCOM, or FU/XU Ram data buses. + assign ramd_d[0:31] = ((scaddr_v[45] & sc_wr_q) == 1'b1) ? sc_wdata[0:31] : + ((scaddr_v[46] & sc_wr_q) == 1'b1) ? sc_wdata[32:63] : + (fu_ram_data_val_q == 1'b1) ? fu_ramd_load_data_q[0:31] : + (xu_ram_data_val_q == 1'b1) ? xu_ramd_load_data[0:31] : + (lq_ram_data_val_q == 1'b1) ? lq_ramd_load_data[0:31] : + ramd_q[0:31]; + + assign ramd_d[32:63] = ((scaddr_v[45] & sc_wr_q) == 1'b1) ? sc_wdata[32:63] : + ((scaddr_v[47] & sc_wr_q) == 1'b1) ? sc_wdata[32:63] : + (fu_ram_data_val_q == 1'b1) ? fu_ramd_load_data_q[32:63] : + (xu_ram_data_val_q == 1'b1) ? xu_ramd_load_data[32:63] : + (lq_ram_data_val_q == 1'b1) ? lq_ramd_load_data[32:63] : + ramd_q[32:63]; + + assign ramdh_out = {tidn_32, ramd_q[0:31]}; + + assign ramdl_out = {tidn_32, ramd_q[32:63]}; + + // SRAMD load pulse active 1 cycle after SCOM write to RAMD register address + assign load_sramd_d = sc_wr_q & (|scaddr_v[45:47]); + + + //--------------------------------------------------------------------- + // Thread Control Register + // THRCTL RW address = 48 + // THRCTL WO with and-mask = 49 + // THRCTL WO with or-mask = 50 + + assign or_thrctl_load = (scaddr_v[48] | scaddr_v[50]) & sc_wr_q; + assign and_thrctl_ones = (~((scaddr_v[48] | scaddr_v[49]) & sc_wr_q)); + assign and_thrctl_load = scaddr_v[49] & sc_wr_q; + + assign or_thrctl = {SCOM_WIDTH {or_thrctl_load}} & sc_wdata; + assign and_thrctl = ({SCOM_WIDTH {and_thrctl_load}} & sc_wdata) | ({SCOM_WIDTH {and_thrctl_ones}} & andmask_ones); + + assign stop_for_debug = stop_dbg_event_q | stop_dbg_dnh_q; + + // Stop bit: set by SCOM + misc stop signals; reset by SCOM + assign thrctl_stop_in = stop_for_debug[0:`THREADS-1] | rg_rg_xstop_err[0:`THREADS-1] | + err_attention_instr_q[0:`THREADS-1] | or_thrctl[32:32 + `THREADS-1] | + (thrctl_out[32:32 + `THREADS-1] & and_thrctl[32:32 + `THREADS-1]); + + // Step bit: set by SCOM; reset by SCOM or iu_pc_step_done + assign thrctl_step_in = or_thrctl[36:36 + `THREADS-1] | + (thrctl_out[36:36 + `THREADS-1] & and_thrctl[36:36 + `THREADS-1] & + (~tx_step_overrun[0:`THREADS-1]) & (~step_done_q[0:`THREADS - 1])); + + // Run bit: controlled by external status input + assign thrctl_run_in = xu_pc_running[0:`THREADS-1]; + + // Debug Stop Status bit: controlled by PCCR0[Enable Debug Stop] AND an_ac_debug_stop input signals + assign thrctl_debug_stop_in = external_debug_stop[0]; + + // Thread Stop Summary Status: PwrMgmt; XstopErr; DbgEvent; SpecAttn. + assign thrctl_stop_summary_in[0] = ct_rg_power_managed[0] | pm_fetch_halt_q[0] | pm_thread_stop_q[0]; + + assign thrctl_stop_summary_in[1:3] = {rg_rg_xstop_err[0], stop_for_debug[0], err_attention_instr_q[0]} | + or_thrctl[45:47] | (thrctl_out[45:47] & and_thrctl[45:47]); + + generate + if (`THREADS == 2) + begin : T2_STOP_REQ + assign thrctl_stop_summary_in[4] = ct_rg_power_managed[1] | pm_fetch_halt_q[1] | pm_thread_stop_q[1]; + + assign thrctl_stop_summary_in[5:7] = {rg_rg_xstop_err[1], stop_for_debug[1], err_attention_instr_q[1]} | + or_thrctl[49:51] | (thrctl_out[49:51] & and_thrctl[49:51]); + end + endgenerate + + // Misc Debug Ctrl bits: set by SCOM; reset by SCOM + assign thrctl_misc_dbg_in = or_thrctl[52:54] | (thrctl_out[52:54] & and_thrctl[52:54]); + + // Spare bits: set by SCOM; reset by SCOM + assign thrctl_spare2_in = or_thrctl[55:59] | (thrctl_out[55:59] & and_thrctl[55:59]); + + // Spare bits: set by SCOM; reset by SCOM + assign thrctl_spare1_in = or_thrctl[60:61] | (thrctl_out[60:61] & and_thrctl[60:61]); + + // InstrStep Overrun: set by SCOM + instr_step_overrun; reset by SCOM + assign thrctl_step_ovrun_in = instr_step_overrun | or_thrctl[62] | (thrctl_out[62] & and_thrctl[62]); + + // RAMC Error Status: set by SCOM + ramc_error_status signals; reset by SCOM + assign thrctl_ramc_err_in = ramc_error_status | or_thrctl[63] | (thrctl_out[63] & and_thrctl[63]); + + // THRCTL register inputs: thrctl1 is always enabled; thrctl2 updates when debug mode active + assign thrctl1_d = {thrctl_stop_in, thrctl_step_in, thrctl_run_in, thrctl_debug_stop_in, + thrctl_stop_summary_in, thrctl_spare1_in, thrctl_step_ovrun_in, thrctl_ramc_err_in}; + assign thrctl2_d = {thrctl_misc_dbg_in, thrctl_spare2_in}; + + // SCOM output - reserves unimplemented bit spacing when `THREADS set to 1 or 2 + generate + if (`THREADS == 1) + begin : T1_THRCTL + // Stop(32) Step(36) Run(40) DbgStopInp(43) + assign thrctl_out = {tidn_32, thrctl1_q[0], 3'b000, thrctl1_q[1], 3'b000, thrctl1_q[2], 2'b00, thrctl1_q[3], + // StopSumary(44:47) Dbg/Spares(52:59) Spare1(60:61) Error Stat (62:63) + thrctl1_q[4:7], 4'b0000, thrctl2_q[0:7], thrctl1_q[8:9], thrctl1_q[10:11]}; + end + endgenerate + generate + if (`THREADS == 2) + begin : T2_THRCTL + // Stop(32:33) Step(36:37) Run(40:41) DbgStopInp(43) + assign thrctl_out = {tidn_32, thrctl1_q[0:1], 2'b00, thrctl1_q[2:3], 2'b00, thrctl1_q[4:5], 1'b0, thrctl1_q[6], + // StopSum(44:51) Dbg/Spares(52:59) Spare1(60:61) Error Stat (62:63) + thrctl1_q[7:14], thrctl2_q[0:7], thrctl1_q[15:16], thrctl1_q[17:18]}; + end + endgenerate + + // --------------------------- + // InstrStep Controls and Overrun Checking Logic: + + // Its an overrun when there is a step_req rising edge pulse and THRCTL[Tx_RUN] is still active. + assign tx_step_req_d[0:`THREADS-1] = {`THREADS {debug_mode_d}} & thrctl_out[36:36 + `THREADS-1]; + assign tx_step_overrun[0:`THREADS-1] = tx_step_req_d & (~tx_step_req_q) & thrctl_out[40:40 + `THREADS-1] & + ~{`THREADS {rg_rg_dis_overrun_chks}}; + + // Latch tx_step_val_q when step_req rising edge pulse and THRCTL[Tx_RUN] is inactive. A step_done pulse resets latch. + // Requires debug_mode active to set latch. latch is cleared if debug_mode is dropped. + assign tx_step_val_d[0:`THREADS-1] = (tx_step_req_d & (~tx_step_req_q) & ((~thrctl_out[40:40 + `THREADS-1]) | + {`THREADS {rg_rg_dis_overrun_chks}})) | + ({`THREADS {debug_mode_d}} & (tx_step_val_q & (~step_done_q))); + + // THRCTL status bit + assign instr_step_overrun = (|tx_step_overrun[0:`THREADS-1]); + + + //--------------------------------------------------------------------- + // PC Unit Configuration Register 0 + // PCCR0 RW address = 51 + // PCCR0 WO with and-mask = 52 + // PCCR0 WO with or-mask = 53 + + assign or_pccr0_load = (scaddr_v[51] | scaddr_v[53]) & sc_wr_q; + assign and_pccr0_ones = (~((scaddr_v[51] | scaddr_v[52]) & sc_wr_q)); + assign and_pccr0_load = scaddr_v[52] & sc_wr_q; + + assign or_pccr0 = {SCOM_WIDTH {or_pccr0_load}} & sc_wdata; + assign and_pccr0 = ({SCOM_WIDTH {and_pccr0_load}} & sc_wdata) | ({SCOM_WIDTH {and_pccr0_ones}} & andmask_ones); + + // PCCR0(32:38) are pervasive modes and miscellaneous controls: set by SCOM; reset by SCOM + // 32 = Enable Debug mode + // 33 = Enable Ram mode + // 34 = Enable Error Inject mode + // 35 = Enable External Debug Stop + // 36 = Disable xstop reporting in Ram mode + // 37 = Enable fast clockstop + // 38 = Disable power savings + // 39 = Disable overrun checking + assign pccr0_pervModes_in = or_pccr0[32:39] | (pccr0_out[32:39] & and_pccr0[32:39]); + + // PCCR0(40:43) are spare bits: set by SCOM; reset by SCOM + assign pccr0_spare_in = or_pccr0[40:43] | (pccr0_out[40:43] & and_pccr0[40:43]); + + // PCCR0(48:51) is the Recoverable Error Counter + // Incremented when gated by a new recoverable error; PCCR0 parity recalculated. + assign incr_recErrCntr = recErrCntr_q[0:3] + 4'b0001; + assign recErrCntr_pargen = (^{incr_recErrCntr, pccr0_out[32:43], pccr0_out[53:59]}); + + assign recErrCntr_in = ((scaddr_v[51] & sc_wr_q) == 1'b1) ? sc_wdata[48:51] : + (rg_rg_gateRecErrCntr == 1'b1) ? incr_recErrCntr : + recErrCntr_q[0:3]; + + // PCCR0(T0=53:55, T1=57:59) Debug Action Selects: + assign pccr0_dbgActSel_in[0:2] = or_pccr0[53:55] | (pccr0_out[53:55] & and_pccr0[53:55]); + + generate + if (`THREADS == 2) + begin : T1_DBA + assign pccr0_dbgActSel_in[3:5] = or_pccr0[57:59] | (pccr0_out[57:59] & and_pccr0[57:59]); + end + endgenerate + + // Load Register + assign pccr0_d = {pccr0_pervModes_in, pccr0_spare_in, pccr0_dbgActSel_in}; + + // SCOM output - reserves locations for T1 DBA bits when `THREADS=2 + generate + if (`THREADS == 1) + begin : T1_PCCR0 + assign pccr0_out = {tidn_32, pccr0_q[0:11], 4'h0, recErrCntr_q, 1'b0, pccr0_q[12:14], 8'h00}; + end + endgenerate + generate + if (`THREADS == 2) + begin : T2_PCCR0 + assign pccr0_out = {tidn_32, pccr0_q[0:11], 4'h0, recErrCntr_q, 1'b0, pccr0_q[12:14], 1'b0, pccr0_q[15:17], 4'h0}; + end + endgenerate + + // Parity Bit + assign pccr0_par_in = {pccr0_d, recErrCntr_in[0:3]}; + + assign pccr0_par_d[0] = (sc_wr_q & (|scaddr_v[51:53]) == 1'b1) ? (^pccr0_par_in) : + (rg_rg_gateRecErrCntr == 1'b1) ? recErrCntr_pargen : + pccr0_par_q[0]; + + assign pccr0_par_err = ((^pccr0_out) ^ pccr0_par_q[0]) | (sc_wr_q & (|scaddr_v[51:53]) & sc_parity_error_inj); + + + //--------------------------------------------------------------------- + // Special Attention and Mask Register + // SPATTN RW address = 54 + // SPATTN WO with and-mask = 55 + // SPATTN WO with or-mask = 56 + + assign or_spattn_load = (scaddr_v[54] | scaddr_v[56]) & sc_wr_q; + assign and_spattn_ones = (~((scaddr_v[54] | scaddr_v[55]) & sc_wr_q)); + assign and_spattn_load = scaddr_v[55] & sc_wr_q; + + assign or_spattn = {SCOM_WIDTH {or_spattn_load}} & sc_wdata; + assign and_spattn = ({SCOM_WIDTH {and_spattn_load}} & sc_wdata) | ({SCOM_WIDTH {and_spattn_ones}} & andmask_ones); + + assign spattn_unused = {16-SPATTN_USED {1'b0}}; + + // Special Attention Data: + // attn_instr: Attention signal generated by attn instruction + assign spattn_attn_instr_in = or_spattn[32:32 + `THREADS-1] | err_attention_instr_q[0:`THREADS-1] | + (spattn_out[32:32 + `THREADS-1] & and_spattn[32:32 + `THREADS-1]); + + assign spattn_data_d = spattn_attn_instr_in; + + // Special Attention Mask: set by SCOM; reset by SCOM + assign spattn_mask_d = or_spattn[48:(48 + SPATTN_USED-1)] | + (spattn_out[48:(48 + SPATTN_USED-1)] & and_spattn[48:(48 + SPATTN_USED-1)]); + + // SCOM output: Reserves locations for T1 bits when `THREADS=1 + generate + if (`THREADS == 1) + begin : T1_SPATTN + assign spattn_out = {tidn_32, spattn_data_q, spattn_unused, spattn_mask_q, spattn_unused}; + end + endgenerate + generate + if (`THREADS == 2) + begin : T2_SPATTN + assign spattn_out = {tidn_32, spattn_data_q, spattn_unused, spattn_mask_q, spattn_unused}; + end + endgenerate + + // Parity Bit + assign spattn_par_d[0] = (sc_wr_q & (|scaddr_v[54:56])) == 1'b1 ? (^spattn_mask_d) : + spattn_par_q[0]; + + assign spattn_par_err = ((^spattn_mask_q) ^ spattn_par_q[0]) | (sc_wr_q & (|scaddr_v[54:56]) & sc_parity_error_inj); + + + //--------------------------------------------------------------------- + // Debug Select Registers + // ARDSR RW address = 59 + // IDSR RW address = 60 + // MPDSR RW address = 61 + // XDSR RW address = 62 + // LDSR RW address = 63 + + assign ardsr_data_in[0:10] = ((scaddr_v[59] & sc_wr_q) == 1'b1) ? sc_wdata[32:42] : ardsr_out[32:42]; + assign ardsr_data_in[11:21] = ((scaddr_v[59] & sc_wr_q) == 1'b1) ? sc_wdata[48:58] : ardsr_out[48:58]; + + assign ardsr_d = ardsr_data_in; + // AXU + RV debug mux controls + assign ardsr_out = {tidn_32, ardsr_q[0:10], 5'b00000, ardsr_q[11:21], 5'b00000 }; + + + assign idsr_data_in[0:10] = ((scaddr_v[60] & sc_wr_q) == 1'b1) ? sc_wdata[32:42] : idsr_out[32:42]; + assign idsr_data_in[11:21] = ((scaddr_v[60] & sc_wr_q) == 1'b1) ? sc_wdata[48:58] : idsr_out[48:58]; + + assign idsr_d = idsr_data_in; + // IU debug mux controls + assign idsr_out = {tidn_32, idsr_q[0:10], 5'b00000, idsr_q[11:21], 5'b00000 }; + + + assign mpdsr_data_in[0:10] = ((scaddr_v[61] & sc_wr_q) == 1'b1) ? sc_wdata[32:42] : mpdsr_out[32:42]; + assign mpdsr_data_in[11:21] = ((scaddr_v[61] & sc_wr_q) == 1'b1) ? sc_wdata[48:58] : mpdsr_out[48:58]; + + assign mpdsr_d = mpdsr_data_in; + // MMU + PC debug mux controls + assign mpdsr_out = {tidn_32, mpdsr_q[0:10], 5'b00000, mpdsr_q[11:21], 5'b00000 }; + + + assign xdsr_data_in[0:10] = ((scaddr_v[62] & sc_wr_q) == 1'b1) ? sc_wdata[32:42] : xdsr_out[32:42]; + + assign xdsr_d = xdsr_data_in; + // XU debug mux controls + assign xdsr_out = {tidn_32, xdsr_q[0:10], {21 {1'b0}} }; + + + assign ldsr_data_in[0:10] = ((scaddr_v[63] & sc_wr_q) == 1'b1) ? sc_wdata[32:42] : ldsr_out[32:42]; + assign ldsr_data_in[11:21] = ((scaddr_v[63] & sc_wr_q) == 1'b1) ? sc_wdata[48:58] : ldsr_out[48:58]; + + assign ldsr_d = ldsr_data_in; + // LSU debug mux controls + assign ldsr_out = {tidn_32, ldsr_q[0:10], 5'b00000, ldsr_q[11:21], 5'b00000 }; + + + //--------------------------------------------------------------------- + // Error Inject Register + // ERRINJ RW address = 9 + + assign errinj_errtype_in[0:22] = ((scaddr_v[9] & sc_wr_q) == 1'b1) ? sc_wdata[32:54] : + (errinj_out[32:54] & (~rg_rg_errinj_shutoff[0:22])) ; + + generate + if (`THREADS > 1) + begin : T1_ERRINJ + assign errinj_errtype_in[23:31] = ((scaddr_v[9] & sc_wr_q) == 1'b1) ? sc_wdata[55:63] : + (errinj_out[55:63] & (~rg_rg_errinj_shutoff[23:31])); + end + endgenerate + + assign errinj_d = errinj_errtype_in; + + generate + if (`THREADS == 1) + begin : T1_INJOUT + assign errinj_out = {tidn_32, errinj_q, 9'b000000000}; + end + endgenerate + generate + if (`THREADS == 2) + begin : T2_INJOUT + assign errinj_out = {tidn_32, errinj_q}; + end + endgenerate + +//===================================================================== +// SCOM Register Read +//===================================================================== + assign scaddr_fir = scaddr_v[0] | scaddr_v[3] | scaddr_v[4] | scaddr_v[6] | scaddr_v[5] | + scaddr_v[19] | scaddr_v[10] | scaddr_v[13] | scaddr_v[14] | scaddr_v[16] | + scaddr_v[20] | scaddr_v[23] | scaddr_v[24] | scaddr_v[26] ; + + + assign sc_rdata = ({SCOM_WIDTH {scaddr_v[40]}} & ramic_out) | + ({SCOM_WIDTH {scaddr_v[41]}} & rami_out) | + ({SCOM_WIDTH {scaddr_v[42]}} & ramc_out) | + ({SCOM_WIDTH {scaddr_v[45]}} & ramd_q[0:63]) | + ({SCOM_WIDTH {scaddr_v[46]}} & ramdh_out) | + ({SCOM_WIDTH {scaddr_v[47]}} & ramdl_out) | + ({SCOM_WIDTH {scaddr_v[48]}} & thrctl_out) | + ({SCOM_WIDTH {scaddr_v[51]}} & pccr0_out) | + ({SCOM_WIDTH {scaddr_v[54]}} & spattn_out) | + ({SCOM_WIDTH {scaddr_v[59]}} & ardsr_out) | + ({SCOM_WIDTH {scaddr_v[60]}} & idsr_out) | + ({SCOM_WIDTH {scaddr_v[61]}} & mpdsr_out) | + ({SCOM_WIDTH {scaddr_v[62]}} & xdsr_out) | + ({SCOM_WIDTH {scaddr_v[63]}} & ldsr_out) | + ({SCOM_WIDTH {scaddr_v[9] }} & errinj_out) | + ({SCOM_WIDTH {scaddr_fir }} & fir_data_out) ; + +//===================================================================== +// Output + Signal Assignments +//===================================================================== + // RAM Command Signals + assign pc_iu_ram_instr = rami_out[32:63]; + assign pc_iu_ram_instr_ext = ramc_out[32:35]; + assign pc_iu_ram_execute = ram_execute_q; + + assign pc_iu_ram_active = ram_active_out; + assign pc_xu_ram_active = ram_active_out; + assign pc_fu_ram_active = ram_active_out; + assign pc_lq_ram_active = ram_active_out; + + assign rg_rg_ram_mode = ram_mode_q; + + assign ram_msrovren_d = ram_mode_d & ramc_out[48]; + assign pc_xu_msrovride_enab = ram_msrovren_q; + + assign ram_msrovrpr_d = ram_mode_d & ramc_out[49]; + assign pc_xu_msrovride_pr = ram_msrovrpr_q; + + assign ram_msrovrgs_d = ram_mode_d & ramc_out[50]; + assign pc_xu_msrovride_gs = ram_msrovrgs_q; + + assign ram_msrovrde_d = ram_mode_d & ramc_out[51]; + assign pc_xu_msrovride_de = ram_msrovrde_q; + + assign ram_force_d = ram_mode_d & ramc_out[52]; + assign pc_iu_ram_force_cmplt = ram_force_q; + + assign ram_flush_d = {2 {ram_enab_d}} & ramc_out[53:54]; + + generate + if (`THREADS == 1) + begin : T1_RAMCTL + assign pc_iu_ram_flush_thread = ram_flush_q[0:0]; + end + endgenerate + generate + if (`THREADS == 2) + begin : T2_RAMCTL + assign pc_iu_ram_flush_thread = ram_flush_q[0:1]; + end + endgenerate + + assign rg_rg_load_sramd = load_sramd_q; + assign rg_rg_sramd_din = ramd_q[0:63]; + + //--------------------------------------------------------------------- + // Thread Control Signals + // an_ac_debug_stop, when enabled, forces all THREADS to stop + assign external_debug_stop = {`THREADS {pccr0_out[35] & ext_debug_stop_q}}; + + assign tx_stop_d = {`THREADS {ct_rg_hold_during_init}} | pm_thread_stop_q | + ((thrctl_out[32:32+`THREADS-1] | external_debug_stop[0:`THREADS-1]) & (~tx_step_val_q[0:`THREADS-1])); + + assign pc_iu_stop = tx_stop_q[0:`THREADS-1]; + + assign pc_iu_pm_fetch_halt = pm_fetch_halt_q[0:`THREADS-1]; + + // tx_step latch used to keep the pc_iu_stop and pc_iu_step changes synchronized. + assign tx_step_d = tx_step_val_q[0:`THREADS-1]; + assign pc_iu_step = tx_step_q[0:`THREADS-1]; + + assign ac_an_pm_thread_running = thrctl_out[40:40+`THREADS-1]; + + // Debug disables for external interrupts and Timers + assign extirpts_dis_d = debug_mode_d & thrctl_out[52]; + assign pc_xu_extirpts_dis_on_stop = extirpts_dis_q; + + assign timebase_dis_d = debug_mode_d & thrctl_out[53]; + assign pc_xu_timebase_dis_on_stop = timebase_dis_q; + + assign decrem_dis_d = debug_mode_d & thrctl_out[54]; + assign pc_xu_decrem_dis_on_stop = decrem_dis_q; + + //--------------------------------------------------------------------- + // PC Configuration Signals + assign trace_bus_enable_d = pccr0_out[32] | sp_rg_trace_bus_enable; + assign rg_db_trace_bus_enable = trace_bus_enable_q; + assign pc_iu_trace_bus_enable = trace_bus_enable_q; + assign pc_fu_trace_bus_enable = trace_bus_enable_q; + assign pc_rv_trace_bus_enable = trace_bus_enable_q; + assign pc_mm_trace_bus_enable = trace_bus_enable_q; + assign pc_xu_trace_bus_enable = trace_bus_enable_q; + assign pc_lq_trace_bus_enable = trace_bus_enable_q; + + // ACT control for latches gated with debug_mode. + assign debug_mode_d = pccr0_out[32]; + assign debug_mode_act = scom_wr_act | debug_mode_d | debug_mode_q; + + // ACT control for latches gated with ram_enable. + assign ram_enab_d = pccr0_out[33]; + assign ram_enab_act = ram_enab_d | ram_enab_q; + assign ram_ctrl_act = scom_wr_act | (|ramc_status_in); + assign ram_data_act = scom_wr_act | xu_ram_data_val_q | fu_ram_data_val_q | lq_ram_data_val_q; + + // ACT control for latches gated with errinj_enable. + assign errinj_enab_d = pccr0_out[34]; + assign errinj_enab_act = errinj_enab_d | errinj_enab_q; + assign errinj_enab_scom_act = errinj_enab_act | scom_wr_act; + + assign rg_rg_xstop_report_ovride = pccr0_out[36]; + + assign rg_rg_fast_xstop_enable = debug_mode_d & pccr0_out[37]; + + assign rg_ct_dis_pwr_savings = pccr0_out[38]; + + assign rg_rg_dis_overrun_chks = pccr0_out[39]; + + assign rg_rg_maxRecErrCntrValue = (&recErrCntr_q[0:3]); + + + generate + if (`THREADS == 1) + begin : T1_DBAOUT + assign pccr0_dba_active_d[0] = (|pccr0_out[53:55]); + + assign pc_iu_dbg_action = pccr0_out[53:55]; + assign pc_iu_spr_dbcr0_edm = pccr0_dba_active_q[0]; + assign pc_xu_spr_dbcr0_edm = pccr0_dba_active_q[0]; + end + endgenerate + generate + if (`THREADS == 2) + begin : T2_DBAOUT + assign pccr0_dba_active_d = { (|pccr0_out[53:55]), (|pccr0_out[57:59]) }; + + assign pc_iu_dbg_action = { pccr0_out[53:55], pccr0_out[57:59] }; + assign pc_iu_spr_dbcr0_edm = pccr0_dba_active_q[0:1]; + assign pc_xu_spr_dbcr0_edm = pccr0_dba_active_q[0:1]; + end + endgenerate + + //--------------------------------------------------------------------- + // Special Attention Signals + assign spattn_out_masked = spattn_data_q & (~spattn_mask_q); + + // Drive out special attention signals (thread specific) + assign ac_an_special_attn = spattn_out_masked[0:`THREADS-1]; + + //--------------------------------------------------------------------- + // Debug Select Controls + assign pc_iu_debug_mux1_ctrls = idsr_out[32:42]; + assign pc_iu_debug_mux2_ctrls = idsr_out[48:58]; + + assign pc_fu_debug_mux_ctrls = ardsr_out[32:42]; + assign pc_rv_debug_mux_ctrls = ardsr_out[48:58]; + + assign pc_mm_debug_mux_ctrls = mpdsr_out[32:42]; + assign rg_db_debug_mux_ctrls = mpdsr_out[48:58]; + + assign pc_xu_debug_mux_ctrls = xdsr_out[32:42]; + + assign pc_lq_debug_mux1_ctrls = ldsr_out[32:42]; + assign pc_lq_debug_mux2_ctrls = ldsr_out[48:58]; + + //--------------------------------------------------------------------- + // Error Injection Signals + assign inj_icache_parity_d = errinj_enab_d & errinj_out[32]; + assign inj_icachedir_parity_d = errinj_enab_d & errinj_out[33]; + assign inj_icachedir_multihit_d = errinj_enab_d & errinj_out[34]; + assign inj_dcache_parity_d = errinj_enab_d & errinj_out[35]; + assign inj_dcachedir_ldp_parity_d = errinj_enab_d & errinj_out[36]; + assign inj_dcachedir_stp_parity_d = errinj_enab_d & errinj_out[37]; + assign inj_dcachedir_ldp_multihit_d = errinj_enab_d & errinj_out[38]; + assign inj_dcachedir_stp_multihit_d = errinj_enab_d & errinj_out[39]; + assign inj_prefetcher_parity_d = errinj_enab_d & errinj_out[41]; + assign inj_relq_parity_d = errinj_enab_d & errinj_out[42]; + + assign inj_sprg_ecc_d[0] = errinj_enab_d & errinj_out[45]; + assign inj_fx0regfile_parity_d[0] = errinj_enab_d & errinj_out[46]; + assign inj_fx1regfile_parity_d[0] = errinj_enab_d & errinj_out[47]; + assign inj_lqregfile_parity_d[0] = errinj_enab_d & errinj_out[48]; + assign inj_furegfile_parity_d[0] = errinj_enab_d & errinj_out[49]; + assign inj_llbust_attempt_d[0] = errinj_enab_d & errinj_out[50]; + assign inj_llbust_failed_d[0] = errinj_enab_d & errinj_out[51]; + assign inj_cpArray_parity_d[0] = errinj_enab_d & errinj_out[52]; + + generate + if (`THREADS > 1) + begin : ERRINJOUT_2T + assign inj_sprg_ecc_d[1] = errinj_enab_d & errinj_out[55]; + assign inj_fx0regfile_parity_d[1] = errinj_enab_d & errinj_out[56]; + assign inj_fx1regfile_parity_d[1] = errinj_enab_d & errinj_out[57]; + assign inj_lqregfile_parity_d[1] = errinj_enab_d & errinj_out[58]; + assign inj_furegfile_parity_d[1] = errinj_enab_d & errinj_out[59]; + assign inj_llbust_attempt_d[1] = errinj_enab_d & errinj_out[60]; + assign inj_llbust_failed_d[1] = errinj_enab_d & errinj_out[61]; + assign inj_cpArray_parity_d[1] = errinj_enab_d & errinj_out[62]; + end + endgenerate + + assign pc_iu_inj_icache_parity = inj_icache_parity_q; + assign pc_iu_inj_icachedir_parity = inj_icachedir_parity_q; + assign pc_iu_inj_icachedir_multihit = inj_icachedir_multihit_q; + assign pc_lq_inj_dcache_parity = inj_dcache_parity_q; + assign pc_lq_inj_dcachedir_ldp_parity = inj_dcachedir_ldp_parity_q; + assign pc_lq_inj_dcachedir_stp_parity = inj_dcachedir_stp_parity_q; + assign pc_lq_inj_dcachedir_ldp_multihit = inj_dcachedir_ldp_multihit_q; + assign pc_lq_inj_dcachedir_stp_multihit = inj_dcachedir_stp_multihit_q; + assign sc_parity_error_inj = errinj_enab_d & errinj_out[40]; + assign pc_lq_inj_prefetcher_parity = inj_prefetcher_parity_q; + assign pc_lq_inj_relq_parity = inj_relq_parity_q; + + assign pc_xu_inj_sprg_ecc[0:`THREADS-1] = inj_sprg_ecc_q[0:`THREADS-1]; + assign pc_fx0_inj_regfile_parity[0:`THREADS-1] = inj_fx0regfile_parity_q[0:`THREADS-1]; + assign pc_fx1_inj_regfile_parity[0:`THREADS-1] = inj_fx1regfile_parity_q[0:`THREADS-1]; + assign pc_lq_inj_regfile_parity[0:`THREADS-1] = inj_lqregfile_parity_q[0:`THREADS-1]; + assign pc_fu_inj_regfile_parity[0:`THREADS-1] = inj_furegfile_parity_q[0:`THREADS-1]; + assign pc_xu_inj_llbust_attempt[0:`THREADS-1] = inj_llbust_attempt_q[0:`THREADS-1]; + assign pc_xu_inj_llbust_failed[0:`THREADS-1] = inj_llbust_failed_q[0:`THREADS-1]; + assign pc_iu_inj_cpArray_parity[0:`THREADS-1] = inj_cpArray_parity_q[0:`THREADS-1]; + + //--------------------------------------------------------------------- + // Error Debug Signals + assign errDbg_t0_d[0:ERRDBG_T0_SIZE-1] = { + iu_pc_quiesce[0], iu_pc_icache_quiesce[0], lq_pc_ldq_quiesce[0], + lq_pc_stq_quiesce[0], lq_pc_pfetch_quiesce[0], mm_pc_tlb_req_quiesce[0], + mm_pc_tlb_ctl_quiesce[0], mm_pc_htw_quiesce[0], mm_pc_inval_quiesce[0], + iu_pc_fx0_credit_ok[0], iu_pc_fx1_credit_ok[0], iu_pc_axu0_credit_ok[0], + iu_pc_axu1_credit_ok[0], iu_pc_lq_credit_ok[0], iu_pc_sq_credit_ok[0] + }; + + + generate + if (`THREADS == 1) + begin : ERRDBG_1T + assign errDbg_out = { errDbg_t0_q, {32-ERRDBG_T0_SIZE {1'b0}} }; + end + endgenerate + generate + if (`THREADS == 2) + begin : ERRDBG_2T + assign errDbg_out = { errDbg_t0_q, errDbg_t1_q, 2'b00 }; + + assign errDbg_t1_d[0:ERRDBG_T1_SIZE-1] = { + iu_pc_quiesce[1], iu_pc_icache_quiesce[1], lq_pc_ldq_quiesce[1], + lq_pc_stq_quiesce[1], lq_pc_pfetch_quiesce[1], mm_pc_tlb_req_quiesce[1], + mm_pc_tlb_ctl_quiesce[1], mm_pc_htw_quiesce[1], mm_pc_inval_quiesce[1], + iu_pc_fx0_credit_ok[1], iu_pc_fx1_credit_ok[1], iu_pc_axu0_credit_ok[1], + iu_pc_axu1_credit_ok[1], iu_pc_lq_credit_ok[1], iu_pc_sq_credit_ok[1] + }; + end + endgenerate + + +//===================================================================== +// FIR Related Registers and Error Reporting +//===================================================================== + pcq_regs_fir fir_regs( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .lcb_clkoff_dc_b(lcb_clkoff_dc_b), + .lcb_mpw1_dc_b(lcb_mpw1_dc_b), + .lcb_mpw2_dc_b(lcb_mpw2_dc_b), + .lcb_delay_lclkr_dc(lcb_delay_lclkr_dc), + .lcb_act_dis_dc(lcb_act_dis_dc), + .lcb_sg_0(lcb_sg_0), + .lcb_func_slp_sl_thold_0(lcb_func_slp_sl_thold_0), + .lcb_cfg_slp_sl_thold_0(lcb_cfg_slp_sl_thold_0), + .cfgslp_d1clk(cfgslp_d1clk), + .cfgslp_d2clk(cfgslp_d2clk), + .cfgslp_lclk(cfgslp_lclk), + .cfg_slat_d2clk(cfg_slat_d2clk), + .cfg_slat_lclk(cfg_slat_lclk), + .bcfg_scan_in(fir_mode_si), + .func_scan_in(fir_func_si), + .bcfg_scan_out(fir_mode_so), + .func_scan_out(fir_func_so), + // SCOM Satellite Interface + .sc_active(scom_wr_act), + .sc_wr_q(sc_wr_q), + .sc_addr_v(scaddr_v), + .sc_wdata(sc_wdata), + .sc_rdata(fir_data_out), + // FIR and Error Signals + .ac_an_checkstop(ac_an_checkstop), + .ac_an_local_checkstop(ac_an_local_checkstop), + .ac_an_recov_err(ac_an_recov_err), + .ac_an_trace_error(ac_an_trace_error), + .ac_an_livelock_active(ac_an_livelock_active), + .an_ac_checkstop(an_ac_checkstop), + .rg_rg_any_fir_xstop(rg_rg_any_fir_xstop), + .iu_pc_err_icache_parity(iu_pc_err_icache_parity), + .iu_pc_err_icachedir_parity(iu_pc_err_icachedir_parity), + .iu_pc_err_icachedir_multihit(iu_pc_err_icachedir_multihit), + .lq_pc_err_dcache_parity(lq_pc_err_dcache_parity), + .lq_pc_err_dcachedir_ldp_parity(lq_pc_err_dcachedir_ldp_parity), + .lq_pc_err_dcachedir_stp_parity(lq_pc_err_dcachedir_stp_parity), + .lq_pc_err_dcachedir_ldp_multihit(lq_pc_err_dcachedir_ldp_multihit), + .lq_pc_err_dcachedir_stp_multihit(lq_pc_err_dcachedir_stp_multihit), + .iu_pc_err_ierat_parity(iu_pc_err_ierat_parity), + .iu_pc_err_ierat_multihit(iu_pc_err_ierat_multihit), + .iu_pc_err_btb_parity(iu_pc_err_btb_parity), + .lq_pc_err_derat_parity(lq_pc_err_derat_parity), + .lq_pc_err_derat_multihit(lq_pc_err_derat_multihit), + .mm_pc_err_tlb_parity(mm_pc_err_tlb_parity), + .mm_pc_err_tlb_multihit(mm_pc_err_tlb_multihit), + .mm_pc_err_tlb_lru_parity(mm_pc_err_tlb_lru_parity), + .mm_pc_err_local_snoop_reject(mm_pc_err_local_snoop_reject), + .lq_pc_err_l2intrf_ecc(lq_pc_err_l2intrf_ecc), + .lq_pc_err_l2intrf_ue(lq_pc_err_l2intrf_ue), + .lq_pc_err_invld_reld(lq_pc_err_invld_reld), + .lq_pc_err_l2credit_overrun(lq_pc_err_l2credit_overrun), + .scom_reg_par_checks(scom_reg_par_checks), + .scom_sat_fsm_error(scom_fsm_err), + .scom_ack_error(scom_ack_err), + .lq_pc_err_prefetcher_parity(lq_pc_err_prefetcher_parity), + .lq_pc_err_relq_parity(lq_pc_err_relq_parity), + .xu_pc_err_sprg_ecc(xu_pc_err_sprg_ecc), + .xu_pc_err_sprg_ue(xu_pc_err_sprg_ue), + .xu_pc_err_regfile_parity(xu_pc_err_regfile_parity), + .xu_pc_err_regfile_ue(xu_pc_err_regfile_ue), + .lq_pc_err_regfile_parity(lq_pc_err_regfile_parity), + .lq_pc_err_regfile_ue(lq_pc_err_regfile_ue), + .fu_pc_err_regfile_parity(fu_pc_err_regfile_parity), + .fu_pc_err_regfile_ue(fu_pc_err_regfile_ue), + .iu_pc_err_cpArray_parity(iu_pc_err_cpArray_parity), + .iu_pc_err_ucode_illegal(iu_pc_err_ucode_illegal), + .iu_pc_err_mchk_disabled(iu_pc_err_mchk_disabled), + .xu_pc_err_llbust_attempt(xu_pc_err_llbust_attempt), + .xu_pc_err_llbust_failed(xu_pc_err_llbust_failed), + .xu_pc_err_wdt_reset(xu_pc_err_wdt_reset), + .iu_pc_err_debug_event(iu_pc_err_debug_event), + .rg_rg_ram_mode(rg_rg_ram_mode), + .rg_rg_ram_mode_xstop(rg_rg_ram_mode_xstop), + .rg_rg_xstop_report_ovride(rg_rg_xstop_report_ovride), + .rg_rg_xstop_err(rg_rg_xstop_err), + .sc_parity_error_inject(sc_parity_error_inj), + .rg_rg_errinj_shutoff(rg_rg_errinj_shutoff), + .rg_rg_maxRecErrCntrValue(rg_rg_maxRecErrCntrValue), + .rg_rg_gateRecErrCntr(rg_rg_gateRecErrCntr), + .errDbg_out(errDbg_out), + // Trace/Trigger Signals + .dbg_fir0_err(dbg_fir0_err), + .dbg_fir1_err(dbg_fir1_err), + .dbg_fir2_err(dbg_fir2_err), + .dbg_fir_misc(dbg_fir_misc) + ); + + assign scom_reg_par_checks = {pccr0_par_err, spattn_par_err}; + + assign rg_ck_fast_xstop = rg_rg_fast_xstop_enable & rg_rg_any_fir_xstop; + +//===================================================================== +// Trace/Trigger Signals +//===================================================================== + assign dbg_scom = { + scom_act, // 0 + sc_req_q, // 1 + sc_wr_q, // 2 + scaddr_predecode[0:5], // 3:8 + scaddr_nvld_q, // 9 + sc_wr_nvld_q, // 10 + sc_rd_nvld_q // 11 + }; + + + assign dbg_thrctls = { + rg_rg_xstop_report_ovride, // 0 + pccr0_out[38], // 1 (dis_pwr_savings) + rg_rg_dis_overrun_chks, // 2 + rg_rg_maxRecErrCntrValue, // 3 + ext_debug_stop_q, // 4 + dbg_spattn_data_q[0:1], // 5:6 + dbg_power_managed_q[0:1], // 7:8 + dbg_pm_thread_stop_q[0:1], // 9:10 + dbg_stop_dbg_event_q[0:1], // 11:12 + dbg_stop_dbg_dnh_q[0:1], // 13:14 + dbg_tx_stop_q[0:1], // 15:16 + dbg_thread_running_q[0:1], // 17:18 + dbg_tx_step_q[0:1], // 19:20 + dbg_tx_step_done_q[0:1], // 21:22 + dbg_tx_step_req_q[0:1] // 23:24 + }; + + + assign dbg_ram = { + ram_mode_q, // 0 + dbg_ram_active_q[0:1], // 1:2 + ram_execute_q, // 3 + ram_msrovren_q, // 4 + ram_msrovrpr_q, // 5 + ram_msrovrgs_q, // 6 + ram_msrovrde_q, // 7 + ram_unsupported_q, // 8 + rammed_instr_overrun, // 9 + ram_interrupt_q, // 10 + rg_rg_ram_mode_xstop, // 11 + ram_done_q, // 12 + xu_ram_data_val_q, // 13 + fu_ram_data_val_q, // 14 + lq_ram_data_val_q // 15 + }; + + + generate + if (`THREADS == 1) + begin : DBG_1T + assign dbg_ram_active_q = {ram_active_q[0], 1'b0}; + assign dbg_spattn_data_q = {err_attention_instr_q[0], 1'b0}; + assign dbg_power_managed_q = {ct_rg_power_managed[0], 1'b0}; + assign dbg_pm_thread_stop_q = {pm_thread_stop_q[0], 1'b0}; + assign dbg_stop_dbg_event_q = {stop_dbg_event_q[0], 1'b0}; + assign dbg_stop_dbg_dnh_q = {stop_dbg_dnh_q[0], 1'b0}; + assign dbg_tx_stop_q = {tx_stop_q[0], 1'b0}; + assign dbg_thread_running_q = {thrctl_out[40], 1'b0}; + assign dbg_tx_step_q = {tx_step_q[0], 1'b0}; + assign dbg_tx_step_done_q = {step_done_q[0], 1'b0}; + assign dbg_tx_step_req_q = {tx_step_req_q[0], 1'b0}; + end + else + begin : DBG_2T + assign dbg_ram_active_q = ram_active_q[0:1]; + assign dbg_spattn_data_q = err_attention_instr_q[0:1]; + assign dbg_power_managed_q = ct_rg_power_managed[0:1]; + assign dbg_pm_thread_stop_q = pm_thread_stop_q[0:1]; + assign dbg_stop_dbg_event_q = stop_dbg_event_q[0:1]; + assign dbg_stop_dbg_dnh_q = stop_dbg_dnh_q[0:1]; + assign dbg_tx_stop_q = tx_stop_q[0:1]; + assign dbg_thread_running_q = thrctl_out[40:40+`THREADS-1]; + assign dbg_tx_step_q = tx_step_q[0:1]; + assign dbg_tx_step_done_q = step_done_q[0:1]; + assign dbg_tx_step_req_q = tx_step_req_q[0:1]; + end + endgenerate + + +//===================================================================== +// Latches +//===================================================================== + // debug config ring registers start + tri_rlmreg_p #(.WIDTH(ARDSR_SIZE), .INIT(0)) axrv_dbgsel_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(scom_wr_act), + .thold_b(lcb_cfg_slp_sl_thold_0_b), + .sg(lcb_sg_0), + .force_t(force_cfgslp), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(dcfg_siv[ ARDSR_OFFSET:ARDSR_OFFSET + ARDSR_SIZE - 1]), + .scout(dcfg_sov[ARDSR_OFFSET:ARDSR_OFFSET + ARDSR_SIZE - 1]), + .din(ardsr_d), + .dout(ardsr_q) + ); + + tri_rlmreg_p #(.WIDTH(IDSR_SIZE), .INIT(0)) iu_dbgsel_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(scom_wr_act), + .thold_b(lcb_cfg_slp_sl_thold_0_b), + .sg(lcb_sg_0), + .force_t(force_cfgslp), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(dcfg_siv[ IDSR_OFFSET:IDSR_OFFSET + IDSR_SIZE - 1]), + .scout(dcfg_sov[IDSR_OFFSET:IDSR_OFFSET + IDSR_SIZE - 1]), + .din(idsr_d), + .dout(idsr_q) + ); + + tri_rlmreg_p #(.WIDTH(MPDSR_SIZE), .INIT(0)) mmpc_dbgsel_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(scom_wr_act), + .thold_b(lcb_cfg_slp_sl_thold_0_b), + .sg(lcb_sg_0), + .force_t(force_cfgslp), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(dcfg_siv[ MPDSR_OFFSET:MPDSR_OFFSET + MPDSR_SIZE - 1]), + .scout(dcfg_sov[MPDSR_OFFSET:MPDSR_OFFSET + MPDSR_SIZE - 1]), + .din(mpdsr_d), + .dout(mpdsr_q) + ); + + tri_rlmreg_p #(.WIDTH(XDSR_SIZE), .INIT(0)) xu_dbgsel_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(scom_wr_act), + .thold_b(lcb_cfg_slp_sl_thold_0_b), + .sg(lcb_sg_0), + .force_t(force_cfgslp), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(dcfg_siv[ XDSR_OFFSET:XDSR_OFFSET + XDSR_SIZE - 1]), + .scout(dcfg_sov[XDSR_OFFSET:XDSR_OFFSET + XDSR_SIZE - 1]), + .din(xdsr_d), + .dout(xdsr_q) + ); + + tri_rlmreg_p #(.WIDTH(LDSR_SIZE), .INIT(0)) lq_dbgsel_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(scom_wr_act), + .thold_b(lcb_cfg_slp_sl_thold_0_b), + .sg(lcb_sg_0), + .force_t(force_cfgslp), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(dcfg_siv[ LDSR_OFFSET:LDSR_OFFSET + LDSR_SIZE - 1]), + .scout(dcfg_sov[LDSR_OFFSET:LDSR_OFFSET + LDSR_SIZE - 1]), + .din(ldsr_d), + .dout(ldsr_q) + ); + + tri_rlmreg_p #(.WIDTH(PCCR0_SIZE), .INIT(0)) pccr0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(scom_wr_act), + .thold_b(lcb_cfg_slp_sl_thold_0_b), + .sg(lcb_sg_0), + .force_t(force_cfgslp), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(dcfg_siv[ PCCR0_OFFSET:PCCR0_OFFSET + PCCR0_SIZE - 1]), + .scout(dcfg_sov[PCCR0_OFFSET:PCCR0_OFFSET + PCCR0_SIZE - 1]), + .din(pccr0_d), + .dout(pccr0_q) + ); + + tri_rlmreg_p #(.WIDTH(RECERRCNTR_SIZE), .INIT(0)) rec_err_cntr( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(lcb_cfg_slp_sl_thold_0_b), + .sg(lcb_sg_0), + .force_t(force_cfgslp), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(dcfg_siv[ RECERRCNTR_OFFSET:RECERRCNTR_OFFSET + RECERRCNTR_SIZE - 1]), + .scout(dcfg_sov[RECERRCNTR_OFFSET:RECERRCNTR_OFFSET + RECERRCNTR_SIZE - 1]), + .din(recErrCntr_in), + .dout(recErrCntr_q) + ); + + tri_rlmreg_p #(.WIDTH(1), .INIT(0)) pccr0_par( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(lcb_cfg_slp_sl_thold_0_b), + .sg(lcb_sg_0), + .force_t(force_cfgslp), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(dcfg_siv[ PCCR0_PAR_OFFSET:PCCR0_PAR_OFFSET]), + .scout(dcfg_sov[PCCR0_PAR_OFFSET:PCCR0_PAR_OFFSET]), + .din(pccr0_par_d), + .dout(pccr0_par_q) + ); + + tri_rlmreg_p #(.WIDTH(DCFG_STAGE1_SIZE), .INIT(0)) dcfg_stage1( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(lcb_cfg_slp_sl_thold_0_b), + .sg(lcb_sg_0), + .force_t(force_cfgslp), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(dcfg_siv[ DCFG_STAGE1_OFFSET:DCFG_STAGE1_OFFSET + DCFG_STAGE1_SIZE - 1]), + .scout(dcfg_sov[DCFG_STAGE1_OFFSET:DCFG_STAGE1_OFFSET + DCFG_STAGE1_SIZE - 1]), + .din( {debug_mode_d, ram_enab_d, errinj_enab_d, trace_bus_enable_d }), + .dout({debug_mode_q, ram_enab_q, errinj_enab_q, trace_bus_enable_q }) + ); + // debug config ring registers end + + // boot config ring registers start + tri_rlmreg_p #(.WIDTH(THRCTL1_SIZE), .INIT(0)) thrctl1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(lcb_cfg_slp_sl_thold_0_b), + .sg(lcb_sg_0), + .force_t(force_cfgslp), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(bcfg_siv[ THRCTL1_OFFSET:THRCTL1_OFFSET + THRCTL1_SIZE - 1]), + .scout(bcfg_sov[THRCTL1_OFFSET:THRCTL1_OFFSET + THRCTL1_SIZE - 1]), + .din(thrctl1_d), + .dout(thrctl1_q) + ); + + tri_rlmreg_p #(.WIDTH(THRCTL2_SIZE), .INIT(0)) thrctl2_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(scom_wr_act), + .thold_b(lcb_cfg_slp_sl_thold_0_b), + .sg(lcb_sg_0), + .force_t(force_cfgslp), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(bcfg_siv[ THRCTL2_OFFSET:THRCTL2_OFFSET + THRCTL2_SIZE - 1]), + .scout(bcfg_sov[THRCTL2_OFFSET:THRCTL2_OFFSET + THRCTL2_SIZE - 1]), + .din(thrctl2_d), + .dout(thrctl2_q) + ); + + tri_rlmreg_p #(.WIDTH(SPATTN_USED), .INIT(0)) spattn_data_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(lcb_cfg_slp_sl_thold_0_b), + .sg(lcb_sg_0), + .force_t(force_cfgslp), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(bcfg_siv[ SPATTN_DATA_OFFSET:SPATTN_DATA_OFFSET + SPATTN_USED - 1]), + .scout(bcfg_sov[SPATTN_DATA_OFFSET:SPATTN_DATA_OFFSET + SPATTN_USED - 1]), + .din(spattn_data_d), + .dout(spattn_data_q) + ); + + tri_rlmreg_p #(.WIDTH(SPATTN_USED), .INIT({SPATTN_USED {1'b1}})) spattn_mask_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(scom_wr_act), + .thold_b(lcb_cfg_slp_sl_thold_0_b), + .sg(lcb_sg_0), + .force_t(force_cfgslp), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(bcfg_siv[ SPATTN_MASK_OFFSET:SPATTN_MASK_OFFSET + SPATTN_USED - 1]), + .scout(bcfg_sov[SPATTN_MASK_OFFSET:SPATTN_MASK_OFFSET + SPATTN_USED - 1]), + .din(spattn_mask_d), + .dout(spattn_mask_q) + ); + + tri_rlmreg_p #(.WIDTH(1), .INIT(SPATTN_PARITY_INIT)) spattn_par( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(scom_wr_act), + .thold_b(lcb_cfg_slp_sl_thold_0_b), + .sg(lcb_sg_0), + .force_t(force_cfgslp), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(bcfg_siv[ SPATTN_PAR_OFFSET:SPATTN_PAR_OFFSET]), + .scout(bcfg_sov[SPATTN_PAR_OFFSET:SPATTN_PAR_OFFSET]), + .din(spattn_par_d), + .dout(spattn_par_q) + ); + + tri_rlmreg_p #(.WIDTH(BCFG_STAGE1_T0_SIZE), .INIT(1)) bcfg_stage1_t0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(lcb_cfg_slp_sl_thold_0_b), + .sg(lcb_sg_0), + .force_t(force_cfgslp), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(bcfg_siv[ BCFG_STAGE1_T0_OFFSET:BCFG_STAGE1_T0_OFFSET + BCFG_STAGE1_T0_SIZE - 1]), + .scout(bcfg_sov[BCFG_STAGE1_T0_OFFSET:BCFG_STAGE1_T0_OFFSET + BCFG_STAGE1_T0_SIZE - 1]), + // Lowest order bit initializes to 1; add new bits on left side of vector + .din( {iu_pc_err_attention_instr[0], iu_pc_stop_dbg_event[0], + xu_pc_stop_dnh_instr[0], iu_pc_step_done[0], an_ac_pm_fetch_halt[0], + an_ac_pm_thread_stop[0], an_ac_debug_stop, tx_stop_d[0] }), + + .dout({err_attention_instr_q[0], stop_dbg_event_q[0], + stop_dbg_dnh_q[0], step_done_q[0], pm_fetch_halt_q[0], + pm_thread_stop_q[0], ext_debug_stop_q, tx_stop_q[0] }) + ); + + tri_ser_rlmreg_p #(.WIDTH(BCFG_STAGE2_T0_SIZE), .INIT(0)) bcfg_stage2_t0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(debug_mode_act), + .thold_b(lcb_cfg_slp_sl_thold_0_b), + .sg(lcb_sg_0), + .force_t(force_cfgslp), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(bcfg_siv[ BCFG_STAGE2_T0_OFFSET:BCFG_STAGE2_T0_OFFSET + BCFG_STAGE2_T0_SIZE - 1]), + .scout(bcfg_sov[BCFG_STAGE2_T0_OFFSET:BCFG_STAGE2_T0_OFFSET + BCFG_STAGE2_T0_SIZE - 1]), + + .din( {extirpts_dis_d, timebase_dis_d, decrem_dis_d, pccr0_dba_active_d[0], + tx_step_d[0], tx_step_req_d[0], tx_step_val_d[0] }), + + .dout({extirpts_dis_q, timebase_dis_q, decrem_dis_q, pccr0_dba_active_q[0], + tx_step_q[0], tx_step_req_q[0], tx_step_val_q[0] }) + ); + + tri_rlmreg_p #(.WIDTH(ERRDBG_T0_SIZE), .INIT(0)) errdbg_t0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(scom_act), + .thold_b(lcb_cfg_slp_sl_thold_0_b), + .sg(lcb_sg_0), + .force_t(force_cfgslp), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(bcfg_siv[ ERRDBG_T0_OFFSET:ERRDBG_T0_OFFSET + ERRDBG_T0_SIZE - 1]), + .scout(bcfg_sov[ERRDBG_T0_OFFSET:ERRDBG_T0_OFFSET + ERRDBG_T0_SIZE - 1]), + .din( errDbg_t0_d ), + .dout(errDbg_t0_q ) + ); + + generate + if (`THREADS > 1) + begin : T1_bcfg + + tri_rlmreg_p #(.WIDTH(BCFG_STAGE1_T1_SIZE), .INIT(1)) bcfg_stage1_t1( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(lcb_cfg_slp_sl_thold_0_b), + .sg(lcb_sg_0), + .force_t(force_cfgslp), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(bcfg_siv[ BCFG_STAGE1_T1_OFFSET:BCFG_STAGE1_T1_OFFSET + BCFG_STAGE1_T1_SIZE - 1]), + .scout(bcfg_sov[BCFG_STAGE1_T1_OFFSET:BCFG_STAGE1_T1_OFFSET + BCFG_STAGE1_T1_SIZE - 1]), + // Lowest order bit initializes to 1; add new bits on left side of vector + .din( {iu_pc_err_attention_instr[1], iu_pc_stop_dbg_event[1], + xu_pc_stop_dnh_instr[1], iu_pc_step_done[1], an_ac_pm_fetch_halt[1], + an_ac_pm_thread_stop[1], tx_stop_d[1] }), + + .dout({err_attention_instr_q[1], stop_dbg_event_q[1], + stop_dbg_dnh_q[1], step_done_q[1], pm_fetch_halt_q[1], + pm_thread_stop_q[1], tx_stop_q[1] }) + ); + + tri_ser_rlmreg_p #(.WIDTH(BCFG_STAGE2_T1_SIZE), .INIT(0)) bcfg_stage2_t1( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(debug_mode_act), + .thold_b(lcb_cfg_slp_sl_thold_0_b), + .sg(lcb_sg_0), + .force_t(force_cfgslp), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(bcfg_siv[ BCFG_STAGE2_T1_OFFSET:BCFG_STAGE2_T1_OFFSET + BCFG_STAGE2_T1_SIZE - 1]), + .scout(bcfg_sov[BCFG_STAGE2_T1_OFFSET:BCFG_STAGE2_T1_OFFSET + BCFG_STAGE2_T1_SIZE - 1]), + + .din( {tx_step_d[1], tx_step_req_d[1], tx_step_val_d[1], pccr0_dba_active_d[1] }), + + .dout({tx_step_q[1], tx_step_req_q[1], tx_step_val_q[1], pccr0_dba_active_q[1] }) + ); + + tri_rlmreg_p #(.WIDTH(ERRDBG_T1_SIZE), .INIT(0)) errdbg_t1( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(scom_act), + .thold_b(lcb_cfg_slp_sl_thold_0_b), + .sg(lcb_sg_0), + .force_t(force_cfgslp), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(bcfg_siv[ ERRDBG_T1_OFFSET:ERRDBG_T1_OFFSET + ERRDBG_T1_SIZE - 1]), + .scout(bcfg_sov[ERRDBG_T1_OFFSET:ERRDBG_T1_OFFSET + ERRDBG_T1_SIZE - 1]), + .din( errDbg_t1_d ), + .dout(errDbg_t1_q ) + ); + end + endgenerate + // boot config ring registers end + + // core config ring registers start + // NOTE: CCFG ring not used in PCQ; latch added for timing. + tri_slat_scan #(.WIDTH(1), .INIT(1'b0)) ccfg_repwr( + .vd(vdd), + .gd(gnd), + .dclk(cfg_slat_d2clk), + .lclk(cfg_slat_lclk), + .scan_in(ccfg_scan_in), + .scan_out(ccfg_scan_out) + ); + // core config ring registers end + + // func ring registers start + tri_rlmreg_p #(.WIDTH(RAMI_SIZE), .INIT(0)) rami_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(scom_wr_act), + .thold_b(lcb_func_slp_sl_thold_0_b), + .sg(lcb_sg_0), + .force_t(force_funcslp), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(func_siv[ RAMI_OFFSET:RAMI_OFFSET + RAMI_SIZE - 1]), + .scout(func_sov[RAMI_OFFSET:RAMI_OFFSET + RAMI_SIZE - 1]), + .din(rami_d), + .dout(rami_q) + ); + + + tri_rlmreg_p #(.WIDTH(RAMC_SIZE), .INIT(0)) ramc_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ram_ctrl_act), + .thold_b(lcb_func_slp_sl_thold_0_b), + .sg(lcb_sg_0), + .force_t(force_funcslp), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(func_siv[ RAMC_OFFSET:RAMC_OFFSET + RAMC_SIZE - 1]), + .scout(func_sov[RAMC_OFFSET:RAMC_OFFSET + RAMC_SIZE - 1]), + .din(ramc_d), + .dout(ramc_q) + ); + + + tri_rlmreg_p #(.WIDTH(RAMD_SIZE), .INIT(0)) ramd_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ram_data_act), + .thold_b(lcb_func_slp_sl_thold_0_b), + .sg(lcb_sg_0), + .force_t(force_funcslp), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(func_siv[ RAMD_OFFSET:RAMD_OFFSET + RAMD_SIZE - 1]), + .scout(func_sov[RAMD_OFFSET:RAMD_OFFSET + RAMD_SIZE - 1]), + .din(ramd_d), + .dout(ramd_q) + ); + + + tri_rlmreg_p #(.WIDTH(FU_RAM_DIN_SIZE), .INIT(0)) fu_ram_din( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(fu_pc_ram_data_val), + .thold_b(lcb_func_slp_sl_thold_0_b), + .sg(lcb_sg_0), + .force_t(force_funcslp), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(func_siv[ FU_RAM_DIN_OFFSET:FU_RAM_DIN_OFFSET + FU_RAM_DIN_SIZE - 1]), + .scout(func_sov[FU_RAM_DIN_OFFSET:FU_RAM_DIN_OFFSET + FU_RAM_DIN_SIZE - 1]), + .din(fu_ramd_load_data_d), + .dout(fu_ramd_load_data_q) + ); + + + tri_rlmreg_p #(.WIDTH(XU_RAM_DIN_SIZE), .INIT(0)) xu_ram_din( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_pc_ram_data_val), + .thold_b(lcb_func_slp_sl_thold_0_b), + .sg(lcb_sg_0), + .force_t(force_funcslp), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(func_siv[ XU_RAM_DIN_OFFSET:XU_RAM_DIN_OFFSET + XU_RAM_DIN_SIZE - 1]), + .scout(func_sov[XU_RAM_DIN_OFFSET:XU_RAM_DIN_OFFSET + XU_RAM_DIN_SIZE - 1]), + .din(xu_ramd_load_data_d), + .dout(xu_ramd_load_data_q) + ); + + + tri_rlmreg_p #(.WIDTH(LQ_RAM_DIN_SIZE), .INIT(0)) lq_ram_din( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(lq_pc_ram_data_val), + .thold_b(lcb_func_slp_sl_thold_0_b), + .sg(lcb_sg_0), + .force_t(force_funcslp), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(func_siv[ LQ_RAM_DIN_OFFSET:LQ_RAM_DIN_OFFSET + LQ_RAM_DIN_SIZE - 1]), + .scout(func_sov[LQ_RAM_DIN_OFFSET:LQ_RAM_DIN_OFFSET + LQ_RAM_DIN_SIZE - 1]), + .din(lq_ramd_load_data_d), + .dout(lq_ramd_load_data_q) + ); + + + tri_rlmreg_p #(.WIDTH(ERRINJ_SIZE), .INIT(0)) errinj_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(errinj_enab_scom_act), + .thold_b(lcb_func_slp_sl_thold_0_b), + .sg(lcb_sg_0), + .force_t(force_funcslp), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(func_siv[ ERRINJ_OFFSET:ERRINJ_OFFSET + ERRINJ_SIZE - 1]), + .scout(func_sov[ERRINJ_OFFSET:ERRINJ_OFFSET + ERRINJ_SIZE - 1]), + .din(errinj_d), + .dout(errinj_q) + ); + + + tri_ser_rlmreg_p #(.WIDTH(SCOM_MISC_SIZE), .INIT(0)) sc_misc( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(scom_act), + .thold_b(lcb_func_slp_sl_thold_0_b), + .sg(lcb_sg_0), + .force_t(force_funcslp), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(func_siv[ SC_MISC_OFFSET:SC_MISC_OFFSET + SCOM_MISC_SIZE - 1]), + .scout(func_sov[SC_MISC_OFFSET:SC_MISC_OFFSET + SCOM_MISC_SIZE - 1]), + + .din( {sc_req_d, scaddr_nvld_d, sc_wr_nvld_d, sc_rd_nvld_d, + sc_wr_d, ram_flush_d, load_sramd_d }), + + .dout({sc_req_q, scaddr_nvld_q, sc_wr_nvld_q, sc_rd_nvld_q, + sc_wr_q, ram_flush_q, load_sramd_q }) + ); + + tri_rlmreg_p #(.WIDTH(64), .INIT(0)) scaddr_dec( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(scom_act), + .thold_b(lcb_func_slp_sl_thold_0_b), + .sg(lcb_sg_0), + .force_t(force_funcslp), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(func_siv[ SCADDR_DEC_OFFSET:SCADDR_DEC_OFFSET + 64 - 1]), + .scout(func_sov[SCADDR_DEC_OFFSET:SCADDR_DEC_OFFSET + 64 - 1]), + .din(scaddr_v_d), + .dout(scaddr_v_q) + ); + + tri_rlmreg_p #(.WIDTH(FUNC_STAGE1_SIZE), .INIT(0)) func_stage1( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(lcb_func_slp_sl_thold_0_b), + .sg(lcb_sg_0), + .force_t(force_funcslp), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(func_siv[ FUNC_STAGE1_OFFSET:FUNC_STAGE1_OFFSET + FUNC_STAGE1_SIZE - 1]), + .scout(func_sov[FUNC_STAGE1_OFFSET:FUNC_STAGE1_OFFSET + FUNC_STAGE1_SIZE - 1]), + .din( {an_ac_scom_cch, an_ac_scom_dch }), + .dout({scom_cch_q, scom_dch_q }) + ); + + tri_ser_rlmreg_p #(.WIDTH(INJ_STAGE1_T0_SIZE), .INIT(0)) inj_stage1_t0( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(errinj_enab_act), + .thold_b(lcb_func_slp_sl_thold_0_b), + .sg(lcb_sg_0), + .force_t(force_funcslp), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(func_siv[ INJ_STAGE1_T0_OFFSET:INJ_STAGE1_T0_OFFSET + INJ_STAGE1_T0_SIZE - 1]), + .scout(func_sov[INJ_STAGE1_T0_OFFSET:INJ_STAGE1_T0_OFFSET + INJ_STAGE1_T0_SIZE - 1]), + + .din( {inj_icache_parity_d, inj_icachedir_parity_d, inj_icachedir_multihit_d, + inj_dcache_parity_d, inj_dcachedir_ldp_parity_d, inj_dcachedir_stp_parity_d, + inj_dcachedir_ldp_multihit_d, inj_dcachedir_stp_multihit_d, inj_prefetcher_parity_d, + inj_relq_parity_d, inj_sprg_ecc_d[0], inj_fx0regfile_parity_d[0], + inj_fx1regfile_parity_d[0], inj_lqregfile_parity_d[0], inj_furegfile_parity_d[0], + inj_llbust_attempt_d[0], inj_llbust_failed_d[0], inj_cpArray_parity_d[0] }), + + .dout({inj_icache_parity_q, inj_icachedir_parity_q, inj_icachedir_multihit_q, + inj_dcache_parity_q, inj_dcachedir_ldp_parity_q, inj_dcachedir_stp_parity_q, + inj_dcachedir_ldp_multihit_q, inj_dcachedir_stp_multihit_q, inj_prefetcher_parity_q, + inj_relq_parity_q, inj_sprg_ecc_q[0], inj_fx0regfile_parity_q[0], + inj_fx1regfile_parity_q[0], inj_lqregfile_parity_q[0], inj_furegfile_parity_q[0], + inj_llbust_attempt_q[0], inj_llbust_failed_q[0], inj_cpArray_parity_q[0] }) + + ); + + generate + if (`THREADS == 1) + begin : T1_INJSTG_BYP + assign func_sov[INJ_STAGE1_T1_OFFSET:INJ_STAGE1_T1_OFFSET + INJ_STAGE1_T1_SIZE - 1] = + func_siv[INJ_STAGE1_T1_OFFSET:INJ_STAGE1_T1_OFFSET + INJ_STAGE1_T1_SIZE - 1] ; + end + endgenerate + + generate + if (`THREADS > 1) + begin : T1_INJSTG + + tri_ser_rlmreg_p #(.WIDTH(INJ_STAGE1_T1_SIZE), .INIT(0)) inj_stage1_t1( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(errinj_enab_act), + .thold_b(lcb_func_slp_sl_thold_0_b), + .sg(lcb_sg_0), + .force_t(force_funcslp), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(func_siv[ INJ_STAGE1_T1_OFFSET:INJ_STAGE1_T1_OFFSET + INJ_STAGE1_T1_SIZE - 1]), + .scout(func_sov[INJ_STAGE1_T1_OFFSET:INJ_STAGE1_T1_OFFSET + INJ_STAGE1_T1_SIZE - 1]), + + .din( {inj_sprg_ecc_d[1], inj_fx0regfile_parity_d[1], inj_fx1regfile_parity_d[1], + inj_lqregfile_parity_d[1], inj_furegfile_parity_d[1], inj_llbust_attempt_d[1], + inj_llbust_failed_d[1], inj_cpArray_parity_d[1] }), + + .dout({inj_sprg_ecc_q[1], inj_fx0regfile_parity_q[1], inj_fx1regfile_parity_q[1], + inj_lqregfile_parity_q[1], inj_furegfile_parity_q[1], inj_llbust_attempt_q[1], + inj_llbust_failed_q[1], inj_cpArray_parity_q[1] }) + ); + end + endgenerate + + tri_ser_rlmreg_p #(.WIDTH(FUNC_STAGE3_SIZE), .INIT(0)) func_stage3( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(ram_enab_act), + .thold_b(lcb_func_slp_sl_thold_0_b), + .sg(lcb_sg_0), + .force_t(force_funcslp), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(func_siv[ FUNC_STAGE3_OFFSET:FUNC_STAGE3_OFFSET + FUNC_STAGE3_SIZE - 1]), + .scout(func_sov[FUNC_STAGE3_OFFSET:FUNC_STAGE3_OFFSET + FUNC_STAGE3_SIZE - 1]), + + .din( {ram_mode_d, ram_execute_d, ram_msrovren_d, ram_msrovrpr_d, + ram_msrovrgs_d, ram_msrovrde_d, ram_force_d, xu_pc_ram_data_val, + fu_pc_ram_data_val, lq_pc_ram_data_val, ram_active_d[0:1], iu_pc_ram_unsupported, + iu_pc_ram_interrupt, iu_pc_ram_done, ramCmpltCntr_in[0:1] }), + + .dout({ram_mode_q, ram_execute_q, ram_msrovren_q, ram_msrovrpr_q, + ram_msrovrgs_q, ram_msrovrde_q, ram_force_q, xu_ram_data_val_q, + fu_ram_data_val_q, lq_ram_data_val_q, ram_active_q[0:1], ram_unsupported_q, + ram_interrupt_q, ram_done_q, ramCmpltCntr_q[0:1] }) + ); + // func ring registers end + +//===================================================================== +// additional LCB Staging +//===================================================================== + // Config ring thold staging - power managaged + assign cfg_slat_thold_b = (~lcb_cfg_sl_thold_0); + assign cfg_slat_force = lcb_sg_0; + + tri_lcbs lcbs_cfg( + .vd(vdd), + .gd(gnd), + .delay_lclkr(lcb_delay_lclkr_dc), + .nclk(nclk), + .force_t(cfg_slat_force), + .thold_b(cfg_slat_thold_b), + .dclk(cfg_slat_d2clk), + .lclk(cfg_slat_lclk) + ); + + // Config ring thold staging - NOT power managed + tri_lcbor lcbor_cfgslp( + .clkoff_b(lcb_clkoff_dc_b), + .thold(lcb_cfg_slp_sl_thold_0), + .sg(lcb_sg_0), + .act_dis(lcb_act_dis_dc), + .force_t(force_cfgslp), + .thold_b(lcb_cfg_slp_sl_thold_0_b) + ); + + tri_lcbnd lcbn_cfgslp( + .vd(vdd), + .gd(gnd), + .act(tiup), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .nclk(nclk), + .force_t(force_cfgslp), + .sg(lcb_sg_0), + .thold_b(lcb_cfg_slp_sl_thold_0_b), + .d1clk(cfgslp_d1clk), + .d2clk(cfgslp_d2clk), + .lclk(cfgslp_lclk) + ); + + // Func ring thold staging - NOT power managed + tri_lcbor lcbor_funcslp( + .clkoff_b(lcb_clkoff_dc_b), + .thold(lcb_func_slp_sl_thold_0), + .sg(lcb_sg_0), + .act_dis(lcb_act_dis_dc), + .force_t(force_funcslp), + .thold_b(lcb_func_slp_sl_thold_0_b) + ); + +//===================================================================== +// Scan Connections +//===================================================================== + // Boot config ring + // includes latches in pcq_regs along with the pcq_regs_fir boot scan ring + assign bcfg_siv[0:BCFG_RIGHT] = {bcfg_scan_in, bcfg_sov[0:BCFG_RIGHT - 1]}; + assign fir_mode_si = bcfg_sov[BCFG_RIGHT]; + assign bcfg_scan_out = fir_mode_so & scan_dis_dc_b; + + // Func config ring + // includes latches in pcq_regs along with the pcq_regs_fir func scan ring + assign func_siv[0:FUNC_RIGHT] = {func_scan_in, func_sov[0:FUNC_RIGHT - 1]}; + assign fir_func_si = func_sov[FUNC_RIGHT]; + assign func_scan_out = fir_func_so & scan_dis_dc_b; + + // Debug config ring + // includes just pcq_regs latches + assign dcfg_siv[0:DCFG_RIGHT] = {dcfg_scan_in, dcfg_sov[0:DCFG_RIGHT - 1]}; + assign dcfg_scan_out = dcfg_sov[DCFG_RIGHT] & scan_dis_dc_b; + + +endmodule diff --git a/dev/verilog/work/pcq_regs_fir.v b/dev/verilog/work/pcq_regs_fir.v new file mode 100755 index 0000000..69f30e3 --- /dev/null +++ b/dev/verilog/work/pcq_regs_fir.v @@ -0,0 +1,990 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +// +// Description: Pervasive Core FIR + Error Reporting Function +// +//***************************************************************************** + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" + +module pcq_regs_fir( +// Include model build parameters +`include "tri_a2o.vh" + + inout vdd, + inout gnd, + input [0:`NCLK_WIDTH-1] nclk, + input lcb_clkoff_dc_b, + input lcb_mpw1_dc_b, + input lcb_mpw2_dc_b, + input lcb_delay_lclkr_dc, + input lcb_act_dis_dc, + input lcb_sg_0, + input lcb_func_slp_sl_thold_0, + input lcb_cfg_slp_sl_thold_0, + input cfgslp_d1clk, + input cfgslp_d2clk, + input [0:`NCLK_WIDTH-1] cfgslp_lclk, + input cfg_slat_d2clk, + input [0:`NCLK_WIDTH-1] cfg_slat_lclk, + input bcfg_scan_in, + output bcfg_scan_out, + input func_scan_in, + output func_scan_out, + // SCOM Satellite Interface + input sc_active, + input sc_wr_q, + input [0:63] sc_addr_v, + input [0:63] sc_wdata, + output [0:63] sc_rdata, + // FIR and Error Signals + output [0:2] ac_an_checkstop, + output [0:2] ac_an_local_checkstop, + output [0:2] ac_an_recov_err, + output ac_an_trace_error, + output rg_rg_any_fir_xstop, + output ac_an_livelock_active, + input an_ac_checkstop, + input iu_pc_err_icache_parity, + input iu_pc_err_icachedir_parity, + input iu_pc_err_icachedir_multihit, + input lq_pc_err_dcache_parity, + input lq_pc_err_dcachedir_ldp_parity, + input lq_pc_err_dcachedir_stp_parity, + input lq_pc_err_dcachedir_ldp_multihit, + input lq_pc_err_dcachedir_stp_multihit, + input iu_pc_err_ierat_parity, + input iu_pc_err_ierat_multihit, + input iu_pc_err_btb_parity, + input lq_pc_err_derat_parity, + input lq_pc_err_derat_multihit, + input mm_pc_err_tlb_parity, + input mm_pc_err_tlb_multihit, + input mm_pc_err_tlb_lru_parity, + input mm_pc_err_local_snoop_reject, + input lq_pc_err_l2intrf_ecc, + input lq_pc_err_l2intrf_ue, + input lq_pc_err_invld_reld, + input lq_pc_err_l2credit_overrun, + input [0:1] scom_reg_par_checks, + input scom_sat_fsm_error, + input scom_ack_error, + input lq_pc_err_prefetcher_parity, + input lq_pc_err_relq_parity, + input [0:`THREADS-1] xu_pc_err_sprg_ecc, + input [0:`THREADS-1] xu_pc_err_sprg_ue, + input [0:`THREADS-1] xu_pc_err_regfile_parity, + input [0:`THREADS-1] xu_pc_err_regfile_ue, + input [0:`THREADS-1] lq_pc_err_regfile_parity, + input [0:`THREADS-1] lq_pc_err_regfile_ue, + input [0:`THREADS-1] fu_pc_err_regfile_parity, + input [0:`THREADS-1] fu_pc_err_regfile_ue, + input [0:`THREADS-1] iu_pc_err_cpArray_parity, + input [0:`THREADS-1] iu_pc_err_ucode_illegal, + input [0:`THREADS-1] iu_pc_err_mchk_disabled, + input [0:`THREADS-1] xu_pc_err_llbust_attempt, + input [0:`THREADS-1] xu_pc_err_llbust_failed, + input [0:`THREADS-1] xu_pc_err_wdt_reset, + input [0:`THREADS-1] iu_pc_err_debug_event, + input rg_rg_ram_mode, + output rg_rg_ram_mode_xstop, + input rg_rg_xstop_report_ovride, + output [0:`THREADS-1] rg_rg_xstop_err, + input sc_parity_error_inject, + output [0:22+9*(`THREADS-1)] rg_rg_errinj_shutoff, + input rg_rg_maxRecErrCntrValue, + output rg_rg_gateRecErrCntr, + input [0:31] errDbg_out, + // Trace/Trigger Signals + output [0:27] dbg_fir0_err, + output [0:19] dbg_fir1_err, + output [0:19] dbg_fir2_err, + output [0:14] dbg_fir_misc +); + +//===================================================================== +// Signal Declarations +//===================================================================== + // FIR0 Init Values + parameter FIR0_WIDTH = 28; + parameter FIR0_INIT = 28'h0000000; + parameter FIR0MASK_INIT = 28'hFFFFFFF; + parameter FIR0MASK_PAR_INIT = 1'b0; + parameter FIR0ACT0_INIT = 28'h0000390; + parameter FIR0ACT0_PAR_INIT = 1'b0; + parameter FIR0ACT1_INIT = 28'hFFFFFFE; + parameter FIR0ACT1_PAR_INIT = 1'b1; + // FIR1 Init Values + parameter FIR1_WIDTH = 20; + parameter FIR1_INIT = 20'h00000; + parameter FIR1MASK_INIT = 20'hFFFFF; + parameter FIR1MASK_PAR_INIT = 1'b0; + parameter FIR1ACT0_INIT = 20'h55660; + parameter FIR1ACT0_PAR_INIT = 1'b0; + parameter FIR1ACT1_INIT = 20'hFFFE0; + parameter FIR1ACT1_PAR_INIT = 1'b1; + // FIR2 Init Values +`ifdef THREADS1 + parameter FIR2_WIDTH = 1; + parameter FIR2_INIT = 1'b0; + parameter FIR2MASK_INIT = 1'b1; + parameter FIR2MASK_PAR_INIT = 1'b1; + parameter FIR2ACT0_INIT = 1'b0; + parameter FIR2ACT0_PAR_INIT = 1'b0; + parameter FIR2ACT1_INIT = 1'b0; + parameter FIR2ACT1_PAR_INIT = 1'b0; +`else + parameter FIR2_WIDTH = 20; + parameter FIR2_INIT = 20'h00000; + parameter FIR2MASK_INIT = 20'hFFFFF; + parameter FIR2MASK_PAR_INIT = 1'b0; + parameter FIR2ACT0_INIT = 20'h55660; + parameter FIR2ACT0_PAR_INIT = 1'b0; + parameter FIR2ACT1_INIT = 20'hFFFE0; + parameter FIR2ACT1_PAR_INIT = 1'b1; +`endif + // Common Init Values + parameter SCPAR_ERR_RPT_WIDTH = 11; + parameter SCPAR_RPT_RESET_VALUE = 11'b00000000000; + parameter SCACK_ERR_RPT_WIDTH = 2; + parameter SCACK_RPT_RESET_VALUE = 2'b00; + parameter SCRDATA_SIZE = 64; + + // Scan Ring Ordering: + parameter FIR0_BCFG_SIZE = 3 * (FIR0_WIDTH + 1) + FIR0_WIDTH; + parameter FIR1_BCFG_SIZE = 3 * (FIR1_WIDTH + 1) + FIR1_WIDTH; + parameter FIR2_BCFG_SIZE = 3 * (FIR2_WIDTH + 1) + FIR2_WIDTH; + parameter FIR0_FUNC_SIZE = 5; + parameter FIR1_FUNC_SIZE = 5; + parameter FIR2_FUNC_SIZE = 5; + parameter ERROUT_FUNC_SIZE = 30; + // START OF BCFG SCAN CHAIN ORDERING + parameter BCFG_FIR0_OFFSET = 0; + parameter BCFG_FIR1_OFFSET = BCFG_FIR0_OFFSET + FIR0_BCFG_SIZE; + parameter BCFG_FIR2_OFFSET = BCFG_FIR1_OFFSET + FIR1_BCFG_SIZE; + parameter BCFG_ERPT1_HLD_OFFSET = BCFG_FIR2_OFFSET + FIR2_BCFG_SIZE; + parameter BCFG_ERPT1_MSK_OFFSET = BCFG_ERPT1_HLD_OFFSET + SCPAR_ERR_RPT_WIDTH; + parameter BCFG_ERPT2_HLD_OFFSET = BCFG_ERPT1_MSK_OFFSET + SCPAR_ERR_RPT_WIDTH; + parameter BCFG_ERPT2_MSK_OFFSET = BCFG_ERPT2_HLD_OFFSET + SCACK_ERR_RPT_WIDTH; + parameter BCFG_RIGHT = BCFG_ERPT2_MSK_OFFSET + SCACK_ERR_RPT_WIDTH - 1; + // END OF BCFG SCAN CHAIN ORDERING + // START OF FUNC SCAN CHAIN ORDERING + parameter FUNC_FIR0_OFFSET = 0; + parameter FUNC_FIR1_OFFSET = FUNC_FIR0_OFFSET + FIR0_FUNC_SIZE; + parameter FUNC_FIR2_OFFSET = FUNC_FIR1_OFFSET + FIR1_FUNC_SIZE; + parameter FUNC_ERROUT_OFFSET = FUNC_FIR2_OFFSET + FIR2_FUNC_SIZE; + parameter FUNC_F0ERR_OFFSET = FUNC_ERROUT_OFFSET + ERROUT_FUNC_SIZE; + parameter FUNC_F1ERR_OFFSET = FUNC_F0ERR_OFFSET + FIR0_WIDTH; + parameter FUNC_F2ERR_OFFSET = FUNC_F1ERR_OFFSET + FIR1_WIDTH; + parameter FUNC_RIGHT = FUNC_F2ERR_OFFSET + FIR2_WIDTH - 1; + // end of func scan chain ordering + + //--------------------------------------------------------------------- + // Basic/Misc signals + wire tidn; + wire tiup; + wire [0:31] tidn_32; + // Clocks + wire func_d1clk; + wire func_d2clk; + wire [0:`NCLK_WIDTH-1] func_lclk; + wire func_thold_b; + wire func_force; + // SCOM + wire [0:63] scomErr_errDbg_status; + wire [0:SCPAR_ERR_RPT_WIDTH-1] sc_reg_par_err_in; + wire [0:SCPAR_ERR_RPT_WIDTH-1] sc_reg_par_err_out; + wire [0:SCPAR_ERR_RPT_WIDTH-1] sc_reg_par_err_out_q; + wire [0:SCPAR_ERR_RPT_WIDTH-1] sc_reg_par_err_hold; + wire scom_reg_parity_err; + wire fir_regs_parity_err; + wire [0:SCACK_ERR_RPT_WIDTH-1] sc_reg_ack_err_in; + wire [0:SCACK_ERR_RPT_WIDTH-1] sc_reg_ack_err_out; + wire [0:SCACK_ERR_RPT_WIDTH-1] sc_reg_ack_err_out_q; + wire [0:SCACK_ERR_RPT_WIDTH-1] sc_reg_ack_err_hold; + wire scom_reg_ack_err; + // FIR0 + wire [0:FIR0_WIDTH-1] fir0_errors; + wire [0:FIR0_WIDTH-1] fir0_errors_q; + wire [0:FIR0_WIDTH-1] fir0_fir_out; + wire [0:FIR0_WIDTH-1] fir0_act0_out; + wire [0:FIR0_WIDTH-1] fir0_act1_out; + wire [0:FIR0_WIDTH-1] fir0_mask_out; + wire [0:FIR0_WIDTH-1] fir0_scrdata; + wire [0:31] fir0_fir_scom_out; + wire [0:31] fir0_act0_scom_out; + wire [0:31] fir0_act1_scom_out; + wire [0:31] fir0_mask_scom_out; + wire fir0_xstop_err; + wire fir0_recov_err; + wire fir0_lxstop_mchk; + wire fir0_trace_error; + wire fir0_block_on_checkstop; + wire [0:2] fir0_fir_parity_check; + wire [0:FIR0_WIDTH-1] fir0_recoverable_errors; + wire [0:1] fir0_recov_err_in; + wire [0:1] fir0_recov_err_q; + wire fir0_recov_err_pulse; + wire [32:32+FIR0_WIDTH-1] fir0_enabled_checkstops; + // FIR1 + wire [0:FIR1_WIDTH-1] fir1_errors; + wire [0:FIR1_WIDTH-1] fir1_errors_q; + wire [0:FIR1_WIDTH-1] fir1_fir_out; + wire [0:FIR1_WIDTH-1] fir1_act0_out; + wire [0:FIR1_WIDTH-1] fir1_act1_out; + wire [0:FIR1_WIDTH-1] fir1_mask_out; + wire [0:FIR1_WIDTH-1] fir1_scrdata; + wire [0:31] fir1_fir_scom_out; + wire [0:31] fir1_act0_scom_out; + wire [0:31] fir1_act1_scom_out; + wire [0:31] fir1_mask_scom_out; + wire fir1_xstop_err; + wire fir1_recov_err; + wire fir1_lxstop_mchk; + wire fir1_trace_error; + wire fir1_block_on_checkstop; + wire [0:2] fir1_fir_parity_check; + wire [0:FIR1_WIDTH-1] fir1_recoverable_errors; + wire [0:1] fir1_recov_err_in; + wire [0:1] fir1_recov_err_q; + wire fir1_recov_err_pulse; + wire [32:32+FIR1_WIDTH-1] fir1_enabled_checkstops; + // FIR2 + wire [0:FIR2_WIDTH-1] fir2_errors; + wire [0:FIR2_WIDTH-1] fir2_errors_q; + wire [0:FIR2_WIDTH-1] fir2_fir_out; + wire [0:FIR2_WIDTH-1] fir2_act0_out; + wire [0:FIR2_WIDTH-1] fir2_act1_out; + wire [0:FIR2_WIDTH-1] fir2_mask_out; + wire [0:FIR2_WIDTH-1] fir2_scrdata; + wire [0:31] fir2_fir_scom_out; + wire [0:31] fir2_act0_scom_out; + wire [0:31] fir2_act1_scom_out; + wire [0:31] fir2_mask_scom_out; + wire fir2_xstop_err; + wire fir2_recov_err; + wire fir2_lxstop_mchk; + wire fir2_trace_error; + wire fir2_block_on_checkstop; + wire [0:2] fir2_fir_parity_check; + wire [0:FIR2_WIDTH-1] fir2_recoverable_errors; + wire [0:1] fir2_recov_err_in; + wire [0:1] fir2_recov_err_q; + wire fir2_recov_err_pulse; + wire [32:32+FIR2_WIDTH-1] fir2_enabled_checkstops; + // Error Inject Shutoff + wire injoff_icache_parity; + wire injoff_icachedir_parity; + wire injoff_icachedir_multihit; + wire injoff_dcache_parity; + wire injoff_dcachedir_ldp_parity; + wire injoff_dcachedir_stp_parity; + wire injoff_dcachedir_ldp_multihit; + wire injoff_dcachedir_stp_multihit; + wire injoff_scomreg_parity; + wire injoff_prefetcher_parity; + wire injoff_relq_parity; + wire injoff_sprg_ecc_t0; + wire injoff_fx0regfile_par_t0; + wire injoff_fx1regfile_par_t0; + wire injoff_lqregfile_par_t0; + wire injoff_furegfile_par_t0; + wire injoff_cpArray_par_t0; + wire injoff_llbust_attempt_t0; + wire injoff_llbust_failed_t0; + wire injoff_sprg_ecc_t1; + wire injoff_fx0regfile_par_t1; + wire injoff_fx1regfile_par_t1; + wire injoff_lqregfile_par_t1; + wire injoff_furegfile_par_t1; + wire injoff_cpArray_par_t1; + wire injoff_llbust_attempt_t1; + wire injoff_llbust_failed_t1; + wire [0:22+9*(`THREADS-1)] error_inject_shutoff; + // MISC + wire [0:2] recov_err_int; + wire [0:2] xstop_err_int; + wire [0:2] xstop_err_q; + wire [0:2] xstop_out_d; + wire [0:2] xstop_out_q; + wire [0:2] lxstop_err_int; + wire [0:2] lxstop_out_d; + wire [0:2] lxstop_out_q; + wire xstop_err_common; + wire [0:`THREADS-1] xstop_err_per_thread; + wire [0:1] dbg_thread_xstop_err; + wire any_fir_xstop_int; + wire an_ac_checkstop_q; + wire maxRecErrCntrValue_errrpt; + wire block_xstop_in_ram_mode; + wire livelock_active_d; + wire livelock_active_q; + wire [0:BCFG_RIGHT] bcfg_siv; + wire [0:BCFG_RIGHT] bcfg_sov; + wire [0:FUNC_RIGHT] func_siv; + wire [0:FUNC_RIGHT] func_sov; + +(* analysis_not_referenced="true" *) + wire unused_signals; + assign unused_signals = ((|fir0_scrdata) | (|fir1_scrdata) | (|fir2_scrdata ) | fir0_recoverable_errors[0] | + sc_addr_v[9] | sc_addr_v[19] | (|sc_addr_v[29:63]) | (|sc_wdata[0:31])); + + + +//--------------------------------------------------------------------- +//!! Bugspray Include: pcq_regs_fir; + + + assign tiup = 1'b1; + assign tidn = 1'b0; + assign tidn_32 = {32{1'b0}}; + + +//===================================================================== +// FIR0 Instantiation +//===================================================================== + pcq_local_fir2 #( + .WIDTH(FIR0_WIDTH), + .IMPL_LXSTOP_MCHK(1'b1), + .USE_RECOV_RESET(1'b0), + .FIR_INIT(FIR0_INIT), + .FIR_MASK_INIT(FIR0MASK_INIT), + .FIR_MASK_PAR_INIT(FIR0MASK_PAR_INIT), + .FIR_ACTION0_INIT(FIR0ACT0_INIT), + .FIR_ACTION0_PAR_INIT(FIR0ACT0_PAR_INIT), + .FIR_ACTION1_INIT(FIR0ACT1_INIT), + .FIR_ACTION1_PAR_INIT(FIR0ACT1_PAR_INIT) + ) FIR0( + // Global lines for clocking and scan control + .nclk(nclk), + .vdd(vdd), + .gnd(gnd), + .lcb_clkoff_dc_b(lcb_clkoff_dc_b), + .lcb_mpw1_dc_b(lcb_mpw1_dc_b), + .lcb_mpw2_dc_b(lcb_mpw2_dc_b), + .lcb_delay_lclkr_dc(lcb_delay_lclkr_dc), + .lcb_act_dis_dc(lcb_act_dis_dc), + .lcb_sg_0(lcb_sg_0), + .lcb_func_slp_sl_thold_0(lcb_func_slp_sl_thold_0), // not power-managed + .lcb_cfg_slp_sl_thold_0(lcb_cfg_slp_sl_thold_0), // not power-managed + .mode_scan_siv(bcfg_siv[BCFG_FIR0_OFFSET:BCFG_FIR0_OFFSET + FIR0_BCFG_SIZE - 1]), + .mode_scan_sov(bcfg_sov[BCFG_FIR0_OFFSET:BCFG_FIR0_OFFSET + FIR0_BCFG_SIZE - 1]), + .func_scan_siv(func_siv[FUNC_FIR0_OFFSET:FUNC_FIR0_OFFSET + FIR0_FUNC_SIZE - 1]), + .func_scan_sov(func_sov[FUNC_FIR0_OFFSET:FUNC_FIR0_OFFSET + FIR0_FUNC_SIZE - 1]), + // external interface + .error_in(fir0_errors_q), // needs to be directly off a latch for timing + .xstop_err(fir0_xstop_err), // checkstop output to Global FIR + .recov_err(fir0_recov_err), // recoverable output to Global FIR + .lxstop_mchk(fir0_lxstop_mchk), // use ONLY if impl_lxstop_mchk = true + .trace_error(fir0_trace_error), // connect to error_input of closest trdata macro + .sys_xstop_in(fir0_block_on_checkstop), // freeze FIR on other checkstop errors + .recov_reset(tidn), // only needed if use_recov_reset = true + .fir_out(fir0_fir_out), // output of current FIR state if needed + .act0_out(fir0_act0_out), // output of current FIR ACT0 if needed + .act1_out(fir0_act1_out), // output of current FIR ACT1 if needed + .mask_out(fir0_mask_out), // output of current FIR MASK if needed + // scom register connections + .sc_parity_error_inject(sc_parity_error_inject), // Force parity error + .sc_active(sc_active), + .sc_wr_q(sc_wr_q), + .sc_addr_v(sc_addr_v[0:8]), + .sc_wdata(sc_wdata[32:32 + FIR0_WIDTH - 1]), + .sc_rdata(fir0_scrdata), + .fir_parity_check(fir0_fir_parity_check) + ); + + //--------------------------------------------------------------------- + // Error Input Facility + assign fir0_errors = { + maxRecErrCntrValue_errrpt, iu_pc_err_icache_parity, // 0:1 + iu_pc_err_icachedir_parity, iu_pc_err_icachedir_multihit, // 2:3 + lq_pc_err_dcache_parity, lq_pc_err_dcachedir_ldp_parity, // 4:5 + lq_pc_err_dcachedir_stp_parity, lq_pc_err_dcachedir_ldp_multihit, // 6:7 + lq_pc_err_dcachedir_stp_multihit, iu_pc_err_ierat_parity, // 8:9 + iu_pc_err_ierat_multihit, lq_pc_err_derat_parity, // 10:11 + lq_pc_err_derat_multihit, mm_pc_err_tlb_parity, // 12:13 + mm_pc_err_tlb_multihit, mm_pc_err_tlb_lru_parity, // 14:15 + mm_pc_err_local_snoop_reject, lq_pc_err_l2intrf_ecc, // 16:17 + lq_pc_err_l2intrf_ue, lq_pc_err_invld_reld, // 18:19 + lq_pc_err_l2credit_overrun, scom_reg_parity_err, // 20:21 + scom_reg_ack_err, fir_regs_parity_err, // 22:23 + lq_pc_err_prefetcher_parity, lq_pc_err_relq_parity, // 24:25 + iu_pc_err_btb_parity, fir0_errors_q[27] // 26:27 (spares: wrapback dout=>din) + }; + + //--------------------------------------------------------------------- + // Block FIR on checkstop (external input or from other FIRs) + assign fir0_block_on_checkstop = an_ac_checkstop_q | xstop_err_q[1] | xstop_err_q[2]; + + +//===================================================================== +// FIR1 Instantiation +//===================================================================== + pcq_local_fir2 #( + .WIDTH(FIR1_WIDTH), + .IMPL_LXSTOP_MCHK(1'b1), + .USE_RECOV_RESET(1'b0), + .FIR_INIT(FIR1_INIT), + .FIR_MASK_INIT(FIR1MASK_INIT), + .FIR_MASK_PAR_INIT(FIR1MASK_PAR_INIT), + .FIR_ACTION0_INIT(FIR1ACT0_INIT), + .FIR_ACTION0_PAR_INIT(FIR1ACT0_PAR_INIT), + .FIR_ACTION1_INIT(FIR1ACT1_INIT), + .FIR_ACTION1_PAR_INIT(FIR1ACT1_PAR_INIT) + ) FIR1( + // Global lines for clocking and scan control + .nclk(nclk), + .vdd(vdd), + .gnd(gnd), + .lcb_clkoff_dc_b(lcb_clkoff_dc_b), + .lcb_mpw1_dc_b(lcb_mpw1_dc_b), + .lcb_mpw2_dc_b(lcb_mpw2_dc_b), + .lcb_delay_lclkr_dc(lcb_delay_lclkr_dc), + .lcb_act_dis_dc(lcb_act_dis_dc), + .lcb_sg_0(lcb_sg_0), + .lcb_func_slp_sl_thold_0(lcb_func_slp_sl_thold_0), // not power-managed + .lcb_cfg_slp_sl_thold_0(lcb_cfg_slp_sl_thold_0), // not power-managed + .mode_scan_siv(bcfg_siv[BCFG_FIR1_OFFSET:BCFG_FIR1_OFFSET + FIR1_BCFG_SIZE - 1]), + .mode_scan_sov(bcfg_sov[BCFG_FIR1_OFFSET:BCFG_FIR1_OFFSET + FIR1_BCFG_SIZE - 1]), + .func_scan_siv(func_siv[FUNC_FIR1_OFFSET:FUNC_FIR1_OFFSET + FIR1_FUNC_SIZE - 1]), + .func_scan_sov(func_sov[FUNC_FIR1_OFFSET:FUNC_FIR1_OFFSET + FIR1_FUNC_SIZE - 1]), + // external interface + .error_in(fir1_errors_q), // needs to be directly off a latch for timing + .xstop_err(fir1_xstop_err), // checkstop output to Global FIR + .recov_err(fir1_recov_err), // recoverable output to Global FIR + .lxstop_mchk(fir1_lxstop_mchk), // use ONLY if impl_lxstop_mchk = true + .trace_error(fir1_trace_error), // connect to error_input of closest trdata macro + .sys_xstop_in(fir1_block_on_checkstop), // freeze FIR on other checkstop errors + .recov_reset(tidn), // only needed if use_recov_reset = true + .fir_out(fir1_fir_out), // output of current FIR state if needed + .act0_out(fir1_act0_out), // output of current FIR ACT0 if needed + .act1_out(fir1_act1_out), // output of current FIR ACT1 if needed + .mask_out(fir1_mask_out), // output of current FIR MASK if needed + // scom register connections + .sc_parity_error_inject(sc_parity_error_inject), // Force parity error + .sc_active(sc_active), + .sc_wr_q(sc_wr_q), + .sc_addr_v(sc_addr_v[10:18]), + .sc_wdata(sc_wdata[32:32 + FIR1_WIDTH - 1]), + .sc_rdata(fir1_scrdata), + .fir_parity_check(fir1_fir_parity_check) + ); + + //--------------------------------------------------------------------- + // Error Input Facility + assign fir1_errors = { + xu_pc_err_sprg_ecc[0], xu_pc_err_sprg_ue[0], // 0:1 + xu_pc_err_regfile_parity[0], xu_pc_err_regfile_ue[0], // 2:3 + lq_pc_err_regfile_parity[0], lq_pc_err_regfile_ue[0], // 4:5 + fu_pc_err_regfile_parity[0], fu_pc_err_regfile_ue[0], // 6:7 + iu_pc_err_cpArray_parity[0], iu_pc_err_ucode_illegal[0], // 8:9 + iu_pc_err_mchk_disabled[0], xu_pc_err_llbust_attempt[0], // 10:11 + xu_pc_err_llbust_failed[0], xu_pc_err_wdt_reset[0], // 12:13 + iu_pc_err_debug_event[0], fir1_errors_q[15:19] // 14:19 (spares: wrapback dout=>din) + }; + + //--------------------------------------------------------------------- + // Block FIR on checkstop (external input or from other FIRs) + assign fir1_block_on_checkstop = an_ac_checkstop_q | xstop_err_q[0] | xstop_err_q[2]; + + +//===================================================================== +// FIR2 Instantiation +//===================================================================== + pcq_local_fir2 #( + .WIDTH(FIR2_WIDTH), + .IMPL_LXSTOP_MCHK(1'b1), + .USE_RECOV_RESET(1'b0), + .FIR_INIT(FIR2_INIT), + .FIR_MASK_INIT(FIR2MASK_INIT), + .FIR_MASK_PAR_INIT(FIR2MASK_PAR_INIT), + .FIR_ACTION0_INIT(FIR2ACT0_INIT), + .FIR_ACTION0_PAR_INIT(FIR2ACT0_PAR_INIT), + .FIR_ACTION1_INIT(FIR2ACT1_INIT), + .FIR_ACTION1_PAR_INIT(FIR2ACT1_PAR_INIT) + ) FIR2( + // Global lines for clocking and scan control + .nclk(nclk), + .vdd(vdd), + .gnd(gnd), + .lcb_clkoff_dc_b(lcb_clkoff_dc_b), + .lcb_mpw1_dc_b(lcb_mpw1_dc_b), + .lcb_mpw2_dc_b(lcb_mpw2_dc_b), + .lcb_delay_lclkr_dc(lcb_delay_lclkr_dc), + .lcb_act_dis_dc(lcb_act_dis_dc), + .lcb_sg_0(lcb_sg_0), + .lcb_func_slp_sl_thold_0(lcb_func_slp_sl_thold_0), // not power-managed + .lcb_cfg_slp_sl_thold_0(lcb_cfg_slp_sl_thold_0), // not power-managed + .mode_scan_siv(bcfg_siv[BCFG_FIR2_OFFSET:BCFG_FIR2_OFFSET + FIR2_BCFG_SIZE - 1]), + .mode_scan_sov(bcfg_sov[BCFG_FIR2_OFFSET:BCFG_FIR2_OFFSET + FIR2_BCFG_SIZE - 1]), + .func_scan_siv(func_siv[FUNC_FIR2_OFFSET:FUNC_FIR2_OFFSET + FIR2_FUNC_SIZE - 1]), + .func_scan_sov(func_sov[FUNC_FIR2_OFFSET:FUNC_FIR2_OFFSET + FIR2_FUNC_SIZE - 1]), + // external interface + .error_in(fir2_errors_q), // needs to be directly off a latch for timing + .xstop_err(fir2_xstop_err), // checkstop output to Global FIR + .recov_err(fir2_recov_err), // recoverable output to Global FIR + .lxstop_mchk(fir2_lxstop_mchk), // use ONLY if impl_lxstop_mchk = true + .trace_error(fir2_trace_error), // connect to error_input of closest trdata macro + .sys_xstop_in(fir2_block_on_checkstop), // freeze FIR on other checkstop errors + .recov_reset(tidn), // only needed if use_recov_reset = true + .fir_out(fir2_fir_out), // output of current FIR state if needed + .act0_out(fir2_act0_out), // output of current FIR ACT0 if needed + .act1_out(fir2_act1_out), // output of current FIR ACT1 if needed + .mask_out(fir2_mask_out), // output of current FIR MASK if needed + // scom register connections + .sc_parity_error_inject(sc_parity_error_inject), // Force parity error + .sc_active(sc_active), + .sc_wr_q(sc_wr_q), + .sc_addr_v(sc_addr_v[20:28]), + .sc_wdata(sc_wdata[32:32 + FIR2_WIDTH - 1]), + .sc_rdata(fir2_scrdata), + .fir_parity_check(fir2_fir_parity_check) + ); + + //--------------------------------------------------------------------- + // Error Input Facility + generate + if (`THREADS == 1) + begin : FIR2ERR_1T + assign fir2_errors = 1'b0; + end + endgenerate + + generate + if (`THREADS == 2) + begin : FIR2ERR_2T + assign fir2_errors = { + xu_pc_err_sprg_ecc[1], xu_pc_err_sprg_ue[1], // 0:1 + xu_pc_err_regfile_parity[1], xu_pc_err_regfile_ue[1], // 2:3 + lq_pc_err_regfile_parity[1], lq_pc_err_regfile_ue[1], // 4:5 + fu_pc_err_regfile_parity[1], fu_pc_err_regfile_ue[1], // 6:7 + iu_pc_err_cpArray_parity[1], iu_pc_err_ucode_illegal[1], // 8:9 + iu_pc_err_mchk_disabled[1], xu_pc_err_llbust_attempt[1], // 10:11 + xu_pc_err_llbust_failed[1], xu_pc_err_wdt_reset[1], // 12:13 + iu_pc_err_debug_event[1], fir2_errors_q[15:19] // 14:19 (spares: wrapback dout=>din) + }; + end + endgenerate + + //--------------------------------------------------------------------- + // Block FIR on checkstop (external input or from other FIRs) + assign fir2_block_on_checkstop = an_ac_checkstop_q | xstop_err_q[0] | xstop_err_q[1]; + +//===================================================================== +// SCOM Register Read +//===================================================================== + assign scomErr_errDbg_status = { sc_reg_par_err_hold[0:SCPAR_ERR_RPT_WIDTH - 1], + sc_reg_ack_err_hold[0:SCACK_ERR_RPT_WIDTH - 1], + {32-(SCPAR_ERR_RPT_WIDTH+SCACK_ERR_RPT_WIDTH) {1'b0}}, + errDbg_out + }; + + assign fir0_fir_scom_out = {fir0_fir_out, {32-FIR0_WIDTH {1'b0}}}; + assign fir0_act0_scom_out = {fir0_act0_out, {32-FIR0_WIDTH {1'b0}}}; + assign fir0_act1_scom_out = {fir0_act1_out, {32-FIR0_WIDTH {1'b0}}}; + assign fir0_mask_scom_out = {fir0_mask_out, {32-FIR0_WIDTH {1'b0}}}; + + assign fir1_fir_scom_out = {fir1_fir_out, {32-FIR1_WIDTH {1'b0}}}; + assign fir1_act0_scom_out = {fir1_act0_out, {32-FIR1_WIDTH {1'b0}}}; + assign fir1_act1_scom_out = {fir1_act1_out, {32-FIR1_WIDTH {1'b0}}}; + assign fir1_mask_scom_out = {fir1_mask_out, {32-FIR1_WIDTH {1'b0}}}; + + assign fir2_fir_scom_out = {fir2_fir_out, {32-FIR2_WIDTH {1'b0}}}; + assign fir2_act0_scom_out = {fir2_act0_out, {32-FIR2_WIDTH {1'b0}}}; + assign fir2_act1_scom_out = {fir2_act1_out, {32-FIR2_WIDTH {1'b0}}}; + assign fir2_mask_scom_out = {fir2_mask_out, {32-FIR2_WIDTH {1'b0}}}; + + assign sc_rdata[0:SCRDATA_SIZE-1] = + ({SCRDATA_SIZE {sc_addr_v[0] }} & {tidn_32, fir0_fir_scom_out }) | + ({SCRDATA_SIZE {sc_addr_v[3] }} & {tidn_32, fir0_act0_scom_out}) | + ({SCRDATA_SIZE {sc_addr_v[4] }} & {tidn_32, fir0_act1_scom_out}) | + ({SCRDATA_SIZE {sc_addr_v[6] }} & {tidn_32, fir0_mask_scom_out}) | + ({SCRDATA_SIZE {sc_addr_v[10]}} & {tidn_32, fir1_fir_scom_out }) | + ({SCRDATA_SIZE {sc_addr_v[13]}} & {tidn_32, fir1_act0_scom_out}) | + ({SCRDATA_SIZE {sc_addr_v[14]}} & {tidn_32, fir1_act1_scom_out}) | + ({SCRDATA_SIZE {sc_addr_v[16]}} & {tidn_32, fir1_mask_scom_out}) | + ({SCRDATA_SIZE {sc_addr_v[20]}} & {tidn_32, fir2_fir_scom_out }) | + ({SCRDATA_SIZE {sc_addr_v[23]}} & {tidn_32, fir2_act0_scom_out}) | + ({SCRDATA_SIZE {sc_addr_v[24]}} & {tidn_32, fir2_act1_scom_out}) | + ({SCRDATA_SIZE {sc_addr_v[26]}} & {tidn_32, fir2_mask_scom_out}) | + ({SCRDATA_SIZE {sc_addr_v[5] }} & scomErr_errDbg_status) | + ({SCRDATA_SIZE {sc_addr_v[19]}} & {fir0_fir_scom_out, fir1_fir_scom_out}) ; + + +//===================================================================== +// Error Related Signals +//===================================================================== + // SCOM parity error reporting macro + assign sc_reg_par_err_in = {scom_reg_par_checks, fir0_fir_parity_check, fir1_fir_parity_check, fir2_fir_parity_check}; + + assign scom_reg_parity_err = (|sc_reg_par_err_out[0:1]); + assign fir_regs_parity_err = (|sc_reg_par_err_out[2:10]); + + tri_err_rpt #(.WIDTH(SCPAR_ERR_RPT_WIDTH), .MASK_RESET_VALUE(SCPAR_RPT_RESET_VALUE), .INLINE(1'b0)) scom_err( + // use to bundle error reporting checkers of the same exact type + .vd(vdd), + .gd(gnd), + .err_d1clk(cfgslp_d1clk), // CAUTION: if LCB uses powersavings, + .err_d2clk(cfgslp_d2clk), // errors must always get reported + .err_lclk(cfgslp_lclk), + .err_scan_in(bcfg_siv[ BCFG_ERPT1_HLD_OFFSET:BCFG_ERPT1_HLD_OFFSET + SCPAR_ERR_RPT_WIDTH - 1]), + .err_scan_out(bcfg_sov[BCFG_ERPT1_HLD_OFFSET:BCFG_ERPT1_HLD_OFFSET + SCPAR_ERR_RPT_WIDTH - 1]), + .mode_dclk(cfg_slat_d2clk), + .mode_lclk(cfg_slat_lclk), + .mode_scan_in(bcfg_siv[ BCFG_ERPT1_MSK_OFFSET:BCFG_ERPT1_MSK_OFFSET + SCPAR_ERR_RPT_WIDTH - 1]), + .mode_scan_out(bcfg_sov[BCFG_ERPT1_MSK_OFFSET:BCFG_ERPT1_MSK_OFFSET + SCPAR_ERR_RPT_WIDTH - 1]), + .err_in(sc_reg_par_err_in), + .err_out(sc_reg_par_err_out), + .hold_out(sc_reg_par_err_hold) + ); + + //--------------------------------------------------------------------- + // SCOM control error reporting macro + assign sc_reg_ack_err_in = {scom_ack_error, scom_sat_fsm_error}; + assign scom_reg_ack_err = (|sc_reg_ack_err_out); + + tri_err_rpt #(.WIDTH(SCACK_ERR_RPT_WIDTH), .MASK_RESET_VALUE(SCACK_RPT_RESET_VALUE), .INLINE(1'b0)) sc_ack_err( + // use to bundle error reporting checkers of the same exact type + .vd(vdd), + .gd(gnd), + .err_d1clk(cfgslp_d1clk), // CAUTION: if LCB uses powersavings, + .err_d2clk(cfgslp_d2clk), // errors must always get reported + .err_lclk(cfgslp_lclk), + .err_scan_in(bcfg_siv[ BCFG_ERPT2_HLD_OFFSET:BCFG_ERPT2_HLD_OFFSET + SCACK_ERR_RPT_WIDTH - 1]), + .err_scan_out(bcfg_sov[BCFG_ERPT2_HLD_OFFSET:BCFG_ERPT2_HLD_OFFSET + SCACK_ERR_RPT_WIDTH - 1]), + .mode_dclk(cfg_slat_d2clk), + .mode_lclk(cfg_slat_lclk), + .mode_scan_in(bcfg_siv[ BCFG_ERPT2_MSK_OFFSET:BCFG_ERPT2_MSK_OFFSET + SCACK_ERR_RPT_WIDTH - 1]), + .mode_scan_out(bcfg_sov[BCFG_ERPT2_MSK_OFFSET:BCFG_ERPT2_MSK_OFFSET + SCACK_ERR_RPT_WIDTH - 1]), + .err_in(sc_reg_ack_err_in), + .err_out(sc_reg_ack_err_out), + .hold_out(sc_reg_ack_err_hold) + ); + + //--------------------------------------------------------------------- + // Other error reporting macros + + tri_direct_err_rpt #(.WIDTH(1)) misc_dir_err( + .vd(vdd), + .gd(gnd), + .err_in(rg_rg_maxRecErrCntrValue), + .err_out(maxRecErrCntrValue_errrpt) + ); + + //--------------------------------------------------------------------- + // Error related facilities used in other functions + // FIR0 Errors that increment the recoverable error counter (Act0=0; Act1=1) + assign fir0_recoverable_errors = fir0_errors_q & (~fir0_act0_out) & fir0_act1_out & (~fir0_mask_out); + // Leaving maxRecErrCntrValue (FIR0(0)) out of input that gates recoverable error counter. + assign fir0_recov_err_in[0] = (|fir0_recoverable_errors[1:FIR0_WIDTH - 1]); + assign fir0_recov_err_in[1] = fir0_recov_err_q[0]; + // Only indicates 1 recoverable error pulse if error input active multiple cycles + assign fir0_recov_err_pulse = fir0_recov_err_q[0] & (~fir0_recov_err_q[1]); + + // FIR1 Errors that increment the recoverable error counter (Act0=0; Act1=1) + assign fir1_recoverable_errors = fir1_errors_q & (~fir1_act0_out) & fir1_act1_out & (~fir1_mask_out); + assign fir1_recov_err_in[0] = (|fir1_recoverable_errors); + assign fir1_recov_err_in[1] = fir1_recov_err_q[0]; + // Only indicates 1 recoverable error pulse if error input active multiple cycles + assign fir1_recov_err_pulse = fir1_recov_err_q[0] & (~fir1_recov_err_q[1]); + + // FIR2 Errors that increment the recoverable error counter (Act0=0; Act1=1) + assign fir2_recoverable_errors = fir2_errors_q & (~fir2_act0_out) & fir2_act1_out & (~fir2_mask_out); + assign fir2_recov_err_in[0] = (|fir2_recoverable_errors); + assign fir2_recov_err_in[1] = fir2_recov_err_q[0]; + // Only indicates 1 recoverable error pulse if error input active multiple cycles + assign fir2_recov_err_pulse = fir2_recov_err_q[0] & (~fir2_recov_err_q[1]); + + // Combined recoverable error signal from all the FIRs + assign recov_err_int = {fir0_recov_err, fir1_recov_err, fir2_recov_err}; + + // Enabled checkstop (system and local) errors used to stop failing thread (Act0=1; Act1=X) + assign fir0_enabled_checkstops = fir0_fir_out & fir0_act0_out & (~fir0_mask_out); + assign fir1_enabled_checkstops = fir1_fir_out & fir1_act0_out & (~fir1_mask_out); + assign fir2_enabled_checkstops = fir2_fir_out & fir2_act0_out & (~fir2_mask_out); + + //--------------------------------------------------------------------- + // Determines how errors will force failing thread(s) to stop if configured as checkstop: + // This is based on the error bit definition in each FIR (thread specific or per core). + // + // Per core FIR0 + // T0 FIR1 + // T1 FIR2 + // + assign xstop_err_common = (|fir0_enabled_checkstops); + + assign xstop_err_per_thread[0] = xstop_err_common | (|fir1_enabled_checkstops); + + generate + if (`THREADS == 2) + begin : THRDXSTOP_2T + assign xstop_err_per_thread[1] = xstop_err_common | (|fir2_enabled_checkstops); + end + endgenerate + + //--------------------------------------------------------------------- + // Report xstop + lxstop errors to Chiplet FIR. Can bypass in Ram mode if override signal active. + assign xstop_err_int[0:2] = {fir0_xstop_err, fir1_xstop_err, fir2_xstop_err}; + assign lxstop_err_int[0:2] = {fir0_lxstop_mchk, fir1_lxstop_mchk, fir2_lxstop_mchk}; + + assign any_fir_xstop_int = (|xstop_err_int[0:2]) | (|lxstop_err_int[0:2]); + + assign block_xstop_in_ram_mode = rg_rg_xstop_report_ovride & rg_rg_ram_mode; + assign xstop_out_d[0:2] = (block_xstop_in_ram_mode == 1'b0) ? xstop_err_int[0:2] : 3'b000 ; + assign lxstop_out_d[0:2] = (block_xstop_in_ram_mode == 1'b0) ? lxstop_err_int[0:2] : 3'b000 ; + + //--------------------------------------------------------------------- + // Error injection shutoff control signals + assign injoff_icache_parity = fir0_errors_q[1]; + assign injoff_icachedir_parity = fir0_errors_q[2]; + assign injoff_icachedir_multihit = fir0_errors_q[3]; + assign injoff_dcache_parity = fir0_errors_q[4]; + assign injoff_dcachedir_ldp_parity = fir0_errors_q[5]; + assign injoff_dcachedir_stp_parity = fir0_errors_q[6]; + assign injoff_dcachedir_ldp_multihit = fir0_errors_q[7]; + assign injoff_dcachedir_stp_multihit = fir0_errors_q[8]; + assign injoff_scomreg_parity = fir0_errors_q[21]; + assign injoff_prefetcher_parity = fir0_errors_q[24]; + assign injoff_relq_parity = fir0_errors_q[25]; + + assign injoff_sprg_ecc_t0 = fir1_errors_q[0]; + assign injoff_fx0regfile_par_t0 = fir1_errors_q[2]; + assign injoff_fx1regfile_par_t0 = fir1_errors_q[2]; + assign injoff_lqregfile_par_t0 = fir1_errors_q[4]; + assign injoff_furegfile_par_t0 = fir1_errors_q[6]; + assign injoff_cpArray_par_t0 = fir1_errors_q[8]; + assign injoff_llbust_attempt_t0 = fir1_errors_q[11]; + assign injoff_llbust_failed_t0 = fir1_errors_q[12]; + + assign error_inject_shutoff[0:22] = { + injoff_icache_parity, injoff_icachedir_parity, injoff_icachedir_multihit, // 0:2 + injoff_dcache_parity, injoff_dcachedir_ldp_parity, injoff_dcachedir_stp_parity, // 3:5 + injoff_dcachedir_ldp_multihit, injoff_dcachedir_stp_multihit, injoff_scomreg_parity, // 6:8 + injoff_prefetcher_parity, injoff_relq_parity, 2'b00, // 9:12 + injoff_sprg_ecc_t0, injoff_fx0regfile_par_t0, injoff_fx1regfile_par_t0, // 13:15 + injoff_lqregfile_par_t0, injoff_furegfile_par_t0, injoff_llbust_attempt_t0, // 16:18 + injoff_llbust_failed_t0, injoff_cpArray_par_t0, 2'b00 }; // 19:22 + + + generate + if (`THREADS == 1) + begin : ERRINJOFF_2T_BYP + assign injoff_sprg_ecc_t1 = 1'b0; + assign injoff_fx0regfile_par_t1 = 1'b0; + assign injoff_fx1regfile_par_t1 = 1'b0; + assign injoff_lqregfile_par_t1 = 1'b0; + assign injoff_furegfile_par_t1 = 1'b0; + assign injoff_llbust_attempt_t1 = 1'b0; + assign injoff_llbust_failed_t1 = 1'b0; + end + endgenerate + + generate + if (`THREADS > 1) + begin : ERRINJOFF_2T + assign injoff_sprg_ecc_t1 = fir2_errors_q[0]; + assign injoff_fx0regfile_par_t1 = fir2_errors_q[2]; + assign injoff_fx1regfile_par_t1 = fir2_errors_q[2]; + assign injoff_lqregfile_par_t1 = fir2_errors_q[4]; + assign injoff_furegfile_par_t1 = fir2_errors_q[6]; + assign injoff_cpArray_par_t1 = fir2_errors_q[8]; + assign injoff_llbust_attempt_t1 = fir2_errors_q[11]; + assign injoff_llbust_failed_t1 = fir2_errors_q[12]; + + assign error_inject_shutoff[23:31] = { + injoff_sprg_ecc_t1, injoff_fx0regfile_par_t1, injoff_fx1regfile_par_t1, // 23:25 + injoff_lqregfile_par_t1, injoff_furegfile_par_t1, injoff_llbust_attempt_t1, // 26:28 + injoff_llbust_failed_t1, injoff_cpArray_par_t1, 1'b0 }; // 29:31 + end + endgenerate + + //--------------------------------------------------------------------- + // Livelock error pulses; ORed together and sent to L2 hang detect logic. + assign livelock_active_d = (|xu_pc_err_llbust_attempt) | (|xu_pc_err_llbust_failed); + +//===================================================================== +// Output Assignments +//===================================================================== + assign ac_an_checkstop = xstop_out_q[0:2]; + + assign ac_an_local_checkstop = lxstop_out_q[0:2]; + + assign ac_an_recov_err = recov_err_int[0:2]; + + assign ac_an_trace_error = fir0_trace_error | fir1_trace_error | fir2_trace_error; + + assign rg_rg_xstop_err = xstop_err_per_thread[0:`THREADS - 1]; + + assign rg_rg_any_fir_xstop = any_fir_xstop_int; + + assign rg_rg_ram_mode_xstop = rg_rg_ram_mode & any_fir_xstop_int; + + assign rg_rg_errinj_shutoff = error_inject_shutoff; + + assign rg_rg_gateRecErrCntr = fir0_recov_err_pulse | fir1_recov_err_pulse | fir2_recov_err_pulse; + + assign ac_an_livelock_active = livelock_active_q; + +//===================================================================== +// Trace/Trigger Signals +//===================================================================== + assign dbg_fir0_err = fir0_errors_q; + + assign dbg_fir1_err = fir1_errors_q; + + + assign dbg_fir_misc = + { + xstop_err_int[0:2], // 0:2 + lxstop_err_int[0:2], // 3:5 + recov_err_int[0:2], // 6:8 + fir0_recov_err_pulse, // 9 + fir1_recov_err_pulse, // 10 + fir2_recov_err_pulse, // 11 + block_xstop_in_ram_mode, // 12 + dbg_thread_xstop_err[0:1] // 13:14 + }; + + + generate + if (`THREADS == 1) + begin : DBG_1T + assign dbg_fir2_err = {FIR1_WIDTH {1'b0}}; + assign dbg_thread_xstop_err = {xstop_err_per_thread[0], 1'b0}; + end + else + begin : DBG_2T + assign dbg_fir2_err = fir2_errors_q; + assign dbg_thread_xstop_err = xstop_err_per_thread[0:1]; + end + endgenerate + + +//===================================================================== +// Latches +//===================================================================== + tri_nlat_scan #(.WIDTH(ERROUT_FUNC_SIZE), .INIT({ERROUT_FUNC_SIZE {1'b0}})) error_out( + .d1clk(func_d1clk), + .vd(vdd), + .gd(gnd), + .lclk(func_lclk), + .d2clk(func_d2clk), + .scan_in(func_siv[ FUNC_ERROUT_OFFSET:FUNC_ERROUT_OFFSET + ERROUT_FUNC_SIZE - 1]), + .scan_out(func_sov[FUNC_ERROUT_OFFSET:FUNC_ERROUT_OFFSET + ERROUT_FUNC_SIZE - 1]), + + .din({xstop_err_int, xstop_out_d, lxstop_out_d, + fir0_recov_err_in, fir1_recov_err_in, fir2_recov_err_in, + an_ac_checkstop, sc_reg_par_err_out, sc_reg_ack_err_out, + livelock_active_d }), + + + .q( {xstop_err_q, xstop_out_q, lxstop_out_q, + fir0_recov_err_q, fir1_recov_err_q, fir2_recov_err_q, + an_ac_checkstop_q, sc_reg_par_err_out_q, sc_reg_ack_err_out_q, + livelock_active_q }) + ); + + tri_nlat_scan #(.WIDTH(FIR0_WIDTH), .INIT(FIR0_INIT)) f0err_out( + .d1clk(func_d1clk), + .vd(vdd), + .gd(gnd), + .lclk(func_lclk), + .d2clk(func_d2clk), + .scan_in(func_siv[ FUNC_F0ERR_OFFSET:FUNC_F0ERR_OFFSET + FIR0_WIDTH - 1]), + .scan_out(func_sov[FUNC_F0ERR_OFFSET:FUNC_F0ERR_OFFSET + FIR0_WIDTH - 1]), + .din(fir0_errors), + .q(fir0_errors_q) + ); + + tri_nlat_scan #(.WIDTH(FIR1_WIDTH), .INIT(FIR1_INIT)) f1err_out( + .d1clk(func_d1clk), + .vd(vdd), + .gd(gnd), + .lclk(func_lclk), + .d2clk(func_d2clk), + .scan_in(func_siv[ FUNC_F1ERR_OFFSET:FUNC_F1ERR_OFFSET + FIR1_WIDTH - 1]), + .scan_out(func_sov[FUNC_F1ERR_OFFSET:FUNC_F1ERR_OFFSET + FIR1_WIDTH - 1]), + .din(fir1_errors), + .q(fir1_errors_q) + ); + + tri_nlat_scan #(.WIDTH(FIR2_WIDTH), .INIT(FIR2_INIT)) f2err_out( + .d1clk(func_d1clk), + .vd(vdd), + .gd(gnd), + .lclk(func_lclk), + .d2clk(func_d2clk), + .scan_in(func_siv[ FUNC_F2ERR_OFFSET:FUNC_F2ERR_OFFSET + FIR2_WIDTH - 1]), + .scan_out(func_sov[FUNC_F2ERR_OFFSET:FUNC_F2ERR_OFFSET + FIR2_WIDTH - 1]), + .din(fir2_errors), + .q(fir2_errors_q) + ); + + //===================================================================== + // LCBs + //===================================================================== + // functional ring regs; NOT power managed + tri_lcbor func_lcbor( + .clkoff_b(lcb_clkoff_dc_b), + .thold(lcb_func_slp_sl_thold_0), + .sg(lcb_sg_0), + .act_dis(lcb_act_dis_dc), + .force_t(func_force), + .thold_b(func_thold_b) + ); + + tri_lcbnd func_lcb( + .act(tiup), // not power saved + .vd(vdd), + .gd(gnd), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .nclk(nclk), + .force_t(func_force), + .sg(lcb_sg_0), + .thold_b(func_thold_b), + .d1clk(func_d1clk), + .d2clk(func_d2clk), + .lclk(func_lclk) + ); + + //===================================================================== + // Scan Connections + //===================================================================== + assign bcfg_siv[0:BCFG_RIGHT] = {bcfg_scan_in, bcfg_sov[0:BCFG_RIGHT - 1]}; + assign bcfg_scan_out = bcfg_sov[BCFG_RIGHT]; + + assign func_siv[0:FUNC_RIGHT] = {func_scan_in, func_sov[0:FUNC_RIGHT - 1]}; + assign func_scan_out = func_sov[FUNC_RIGHT]; + + +endmodule diff --git a/dev/verilog/work/pcq_spr.v b/dev/verilog/work/pcq_spr.v new file mode 100755 index 0000000..a4c087f --- /dev/null +++ b/dev/verilog/work/pcq_spr.v @@ -0,0 +1,625 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +// +// Description: Pervasive Core SPRs and slowSPR Interface +// +//***************************************************************************** + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" + +module pcq_spr( +// Include model build parameters +`include "tri_a2o.vh" + + inout vdd, + inout gnd, + input [0:`NCLK_WIDTH-1] nclk, + // pervasive signals + input scan_dis_dc_b, + input lcb_clkoff_dc_b, + input lcb_mpw1_dc_b, + input lcb_mpw2_dc_b, + input lcb_delay_lclkr_dc, + input lcb_act_dis_dc, + input pc_pc_func_sl_thold_0, + input pc_pc_sg_0, + input func_scan_in, + output func_scan_out, + // slowSPR Interface + input slowspr_val_in, + input slowspr_rw_in, + input [0:1] slowspr_etid_in, + input [0:9] slowspr_addr_in, + input [64-`GPR_WIDTH:63] slowspr_data_in, + input slowspr_done_in, + input [0:`THREADS-1] cp_flush, + output slowspr_val_out, + output slowspr_rw_out, + output [0:1] slowspr_etid_out, + output [0:9] slowspr_addr_out, + output [64-`GPR_WIDTH:63] slowspr_data_out, + output slowspr_done_out, + // Event Mux Controls + output [0:39] pc_rv_event_mux_ctrls, + // CESR1 Controls + output pc_iu_event_bus_enable, + output pc_fu_event_bus_enable, + output pc_rv_event_bus_enable, + output pc_mm_event_bus_enable, + output pc_xu_event_bus_enable, + output pc_lq_event_bus_enable, + output [0:2] pc_iu_event_count_mode, + output [0:2] pc_fu_event_count_mode, + output [0:2] pc_rv_event_count_mode, + output [0:2] pc_mm_event_count_mode, + output [0:2] pc_xu_event_count_mode, + output [0:2] pc_lq_event_count_mode, + output sp_rg_trace_bus_enable, + output pc_iu_instr_trace_mode, + output pc_iu_instr_trace_tid, + output pc_lq_instr_trace_mode, + output pc_lq_instr_trace_tid, + output pc_xu_instr_trace_mode, + output pc_xu_instr_trace_tid, + output pc_lq_event_bus_seldbghi, + output pc_lq_event_bus_seldbglo, + input [0:`THREADS-1] xu_pc_perfmon_alert, + output [0:`THREADS-1] pc_xu_spr_cesr1_pmae, + // SRAMD data and load pulse + input rg_rg_load_sramd, + input [0:63] rg_rg_sramd_din, + // Trace/Trigger Signals + output [0:7] dbg_spr +); + + +//===================================================================== +// Signal Declarations +//===================================================================== + // Scan Ring Constants: + // Register sizes + parameter CESR1_SIZE = 12; + parameter CESR1_IS0_SIZE = 2; + parameter CESR1_IS1_SIZE = 2; + parameter RESR1_SIZE = 20; + parameter RESR2_SIZE = 20; + parameter SRAMD_SIZE = 64; + parameter MISC_SIZE = 2; + + // start of func scan chain ordering + parameter CP_FLUSH_OFFSET = 0; + parameter SLOWSPR_VAL_OFFSET = CP_FLUSH_OFFSET + `THREADS; + parameter SLOWSPR_RW_OFFSET = SLOWSPR_VAL_OFFSET + 1; + parameter SLOWSPR_ETID_OFFSET = SLOWSPR_RW_OFFSET + 1; + parameter SLOWSPR_ADDR_OFFSET = SLOWSPR_ETID_OFFSET + 2; + parameter SLOWSPR_DATA_OFFSET = SLOWSPR_ADDR_OFFSET + 10; + parameter SLOWSPR_DONE_OFFSET = SLOWSPR_DATA_OFFSET + `GPR_WIDTH; + parameter CESR1_OFFSET = SLOWSPR_DONE_OFFSET + 1; + parameter CESR1_IS0_OFFSET = CESR1_OFFSET + CESR1_SIZE; + parameter CESR1_IS1_OFFSET = CESR1_IS0_OFFSET + CESR1_IS0_SIZE; + parameter RESR1_OFFSET = CESR1_IS1_OFFSET + CESR1_IS1_SIZE; + parameter RESR2_OFFSET = RESR1_OFFSET + RESR1_SIZE; + parameter SRAMD_OFFSET = RESR2_OFFSET + RESR2_SIZE; + parameter MISC_OFFSET = SRAMD_OFFSET + SRAMD_SIZE; + parameter FUNC_RIGHT = MISC_OFFSET + MISC_SIZE - 1; + // end of func scan chain ordering + + parameter [32:63] CESR1_MASK = 32'b11111011110011110000000000000000; + parameter [32:63] EVENTMUX_32_MASK = 32'b11111111111111111111111111111111; + parameter [32:63] EVENTMUX_64_MASK = 32'b11111111111111111111000000000000; + parameter [32:63] EVENTMUX_128_MASK = 32'b11111111111111111111111100000000; + + //-------------------------- + // signals + //-------------------------- + wire [0:`THREADS-1] cp_flush_l2; + wire slowspr_val_d; + wire slowspr_val_l2; + wire slowspr_rw_d; + wire slowspr_rw_l2; + wire [0:1] slowspr_etid_d; + wire [0:1] slowspr_etid_l2; + wire [0:9] slowspr_addr_d; + wire [0:9] slowspr_addr_l2; + wire [64-`GPR_WIDTH:63] slowspr_data_d; + wire [64-`GPR_WIDTH:63] slowspr_data_l2; + wire slowspr_done_d; + wire slowspr_done_l2; + + wire pc_done_int; + wire [64-`GPR_WIDTH:63] pc_data_int; + wire [32:63] pc_reg_data; + + wire cesr1_sel; + wire cesr1_wren; + wire cesr1_rden; + wire [32:32+CESR1_SIZE-1] cesr1_d; + wire [32:32+CESR1_SIZE-1] cesr1_l2; + wire [32:63] cesr1_out; + // Instruction Sampling PMAE/PMAO latches + wire [0:1] cesr1_is_wren; + wire [0:1] cesr1_is0_d; + wire [0:1] cesr1_is0_l2; + wire [0:1] cesr1_is1_d; + wire [0:1] cesr1_is1_l2; + wire [0:1] perfmon_alert_din; + wire [0:1] perfmon_alert_q; + wire [0:1] update_is_ctrls; + + wire resr1_sel; + wire resr1_wren; + wire resr1_rden; + wire [32:32+RESR1_SIZE-1] resr1_d; + wire [32:32+RESR1_SIZE-1] resr1_l2; + wire [32:63] resr1_out; + + wire resr2_sel; + wire resr2_wren; + wire resr2_rden; + wire [32:32+RESR2_SIZE-1] resr2_d; + wire [32:32+RESR2_SIZE-1] resr2_l2; + wire [32:63] resr2_out; + + wire sramd_sel; + wire sramd_wren; + wire sramd_rden; + wire [0:SRAMD_SIZE-1] sramd_d; + wire [0:SRAMD_SIZE-1] sramd_l2; + wire [0:63] sramd_out; + + wire [0:3] slowspr_tid; + + // misc, pervasive signals + wire tiup; + wire pc_pc_func_sl_thold_0_b; + wire force_func; + wire [0:FUNC_RIGHT] func_siv; + wire [0:FUNC_RIGHT] func_sov; + + +(* analysis_not_referenced="true" *) + wire unused_signals; + assign unused_signals = (|slowspr_tid[2:3]); + + +//!! Bugspray Include: pcq_spr; + + + assign tiup = 1'b1; + +//===================================================================== +// Latches +//===================================================================== + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) cp_flush_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_pc_func_sl_thold_0_b), + .sg(pc_pc_sg_0), + .force_t(force_func), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(func_siv[CP_FLUSH_OFFSET:CP_FLUSH_OFFSET + `THREADS - 1]), + .scout(func_sov[CP_FLUSH_OFFSET:CP_FLUSH_OFFSET + `THREADS - 1]), + .din(cp_flush), + .dout(cp_flush_l2) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) slowspr_val_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_pc_func_sl_thold_0_b), + .sg(pc_pc_sg_0), + .force_t(force_func), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(func_siv[SLOWSPR_VAL_OFFSET]), + .scout(func_sov[SLOWSPR_VAL_OFFSET]), + .din(slowspr_val_d), + .dout(slowspr_val_l2) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) slowspr_rw_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(slowspr_val_d), + .thold_b(pc_pc_func_sl_thold_0_b), + .sg(pc_pc_sg_0), + .force_t(force_func), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(func_siv[SLOWSPR_RW_OFFSET]), + .scout(func_sov[SLOWSPR_RW_OFFSET]), + .din(slowspr_rw_d), + .dout(slowspr_rw_l2) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) slowspr_etid_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(slowspr_val_d), + .thold_b(pc_pc_func_sl_thold_0_b), + .sg(pc_pc_sg_0), + .force_t(force_func), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(func_siv[SLOWSPR_ETID_OFFSET:SLOWSPR_ETID_OFFSET + 2 - 1]), + .scout(func_sov[SLOWSPR_ETID_OFFSET:SLOWSPR_ETID_OFFSET + 2 - 1]), + .din(slowspr_etid_d), + .dout(slowspr_etid_l2) + ); + + tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) slowspr_addr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(slowspr_val_d), + .thold_b(pc_pc_func_sl_thold_0_b), + .sg(pc_pc_sg_0), + .force_t(force_func), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(func_siv[SLOWSPR_ADDR_OFFSET:SLOWSPR_ADDR_OFFSET + 10 - 1]), + .scout(func_sov[SLOWSPR_ADDR_OFFSET:SLOWSPR_ADDR_OFFSET + 10 - 1]), + .din(slowspr_addr_d), + .dout(slowspr_addr_l2) + ); + + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) slowspr_data_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(slowspr_val_d), + .thold_b(pc_pc_func_sl_thold_0_b), + .sg(pc_pc_sg_0), + .force_t(force_func), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(func_siv[SLOWSPR_DATA_OFFSET:SLOWSPR_DATA_OFFSET + `GPR_WIDTH - 1]), + .scout(func_sov[SLOWSPR_DATA_OFFSET:SLOWSPR_DATA_OFFSET + `GPR_WIDTH - 1]), + .din(slowspr_data_d), + .dout(slowspr_data_l2) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) slowspr_done_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_pc_func_sl_thold_0_b), + .sg(pc_pc_sg_0), + .force_t(force_func), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(func_siv[SLOWSPR_DONE_OFFSET]), + .scout(func_sov[SLOWSPR_DONE_OFFSET]), + .din(slowspr_done_d), + .dout(slowspr_done_l2) + ); + + tri_ser_rlmreg_p #(.WIDTH(CESR1_SIZE), .INIT(0)) cesr1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cesr1_wren), + .thold_b(pc_pc_func_sl_thold_0_b), + .sg(pc_pc_sg_0), + .force_t(force_func), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(func_siv[CESR1_OFFSET:CESR1_OFFSET + CESR1_SIZE - 1]), + .scout(func_sov[CESR1_OFFSET:CESR1_OFFSET + CESR1_SIZE - 1]), + .din(cesr1_d), + .dout(cesr1_l2) + ); + + tri_ser_rlmreg_p #(.WIDTH(CESR1_IS0_SIZE), .INIT(0)) cesr1_is0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cesr1_is_wren[0]), + .thold_b(pc_pc_func_sl_thold_0_b), + .sg(pc_pc_sg_0), + .force_t(force_func), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(func_siv[CESR1_IS0_OFFSET:CESR1_IS0_OFFSET + CESR1_IS0_SIZE - 1]), + .scout(func_sov[CESR1_IS0_OFFSET:CESR1_IS0_OFFSET + CESR1_IS0_SIZE - 1]), + .din(cesr1_is0_d), + .dout(cesr1_is0_l2) + ); + + tri_ser_rlmreg_p #(.WIDTH(CESR1_IS1_SIZE), .INIT(0)) cesr1_is1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cesr1_is_wren[1]), + .thold_b(pc_pc_func_sl_thold_0_b), + .sg(pc_pc_sg_0), + .force_t(force_func), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(func_siv[CESR1_IS1_OFFSET:CESR1_IS1_OFFSET + CESR1_IS1_SIZE - 1]), + .scout(func_sov[CESR1_IS1_OFFSET:CESR1_IS1_OFFSET + CESR1_IS1_SIZE - 1]), + .din(cesr1_is1_d), + .dout(cesr1_is1_l2) + ); + + tri_ser_rlmreg_p #(.WIDTH(RESR1_SIZE), .INIT(0)) resr1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(resr1_wren), + .thold_b(pc_pc_func_sl_thold_0_b), + .sg(pc_pc_sg_0), + .force_t(force_func), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(func_siv[RESR1_OFFSET:RESR1_OFFSET + RESR1_SIZE - 1]), + .scout(func_sov[RESR1_OFFSET:RESR1_OFFSET + RESR1_SIZE - 1]), + .din(resr1_d), + .dout(resr1_l2) + ); + + tri_ser_rlmreg_p #(.WIDTH(RESR2_SIZE), .INIT(0)) resr2_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(resr2_wren), + .thold_b(pc_pc_func_sl_thold_0_b), + .sg(pc_pc_sg_0), + .force_t(force_func), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(func_siv[RESR2_OFFSET:RESR2_OFFSET + RESR2_SIZE - 1]), + .scout(func_sov[RESR2_OFFSET:RESR2_OFFSET + RESR2_SIZE - 1]), + .din(resr2_d), + .dout(resr2_l2) + ); + + tri_ser_rlmreg_p #(.WIDTH(SRAMD_SIZE), .INIT(0)) sramd_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(sramd_wren), + .thold_b(pc_pc_func_sl_thold_0_b), + .sg(pc_pc_sg_0), + .force_t(force_func), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(func_siv[SRAMD_OFFSET:SRAMD_OFFSET + SRAMD_SIZE - 1]), + .scout(func_sov[SRAMD_OFFSET:SRAMD_OFFSET + SRAMD_SIZE - 1]), + .din(sramd_d), + .dout(sramd_l2) + ); + + tri_rlmreg_p #(.WIDTH(MISC_SIZE), .INIT(0)) misc_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_pc_func_sl_thold_0_b), + .sg(pc_pc_sg_0), + .force_t(force_func), + .delay_lclkr(lcb_delay_lclkr_dc), + .mpw1_b(lcb_mpw1_dc_b), + .mpw2_b(lcb_mpw2_dc_b), + .scin(func_siv[MISC_OFFSET:MISC_OFFSET + MISC_SIZE - 1]), + .scout(func_sov[MISC_OFFSET:MISC_OFFSET + MISC_SIZE - 1]), + .din(perfmon_alert_din), + .dout(perfmon_alert_q) + ); + +//===================================================================== +// inputs + staging +//===================================================================== + assign slowspr_val_d = slowspr_val_in & !(|(slowspr_tid[0:`THREADS-1] & cp_flush_l2)); + assign slowspr_rw_d = slowspr_rw_in; + assign slowspr_etid_d = slowspr_etid_in; + assign slowspr_addr_d = slowspr_addr_in; + assign slowspr_data_d = slowspr_data_in; + assign slowspr_done_d = slowspr_done_in; + +//===================================================================== +// Outputs +//===================================================================== + assign slowspr_tid = (slowspr_etid_in == 2'b00) ? 4'b1000 : + (slowspr_etid_in == 2'b01) ? 4'b0100 : + (slowspr_etid_in == 2'b10) ? 4'b0010 : + (slowspr_etid_in == 2'b11) ? 4'b0001 : + 4'b0000; + assign slowspr_val_out = slowspr_val_l2; + assign slowspr_rw_out = slowspr_rw_l2; + assign slowspr_etid_out = slowspr_etid_l2; + assign slowspr_addr_out = slowspr_addr_l2; + assign slowspr_data_out = slowspr_data_l2 | pc_data_int; + assign slowspr_done_out = slowspr_done_l2 | pc_done_int; + + assign pc_rv_event_mux_ctrls = {resr1_out[32:51], resr2_out[32:51]}; + + // CESR1 controls miscellaneous performance related functions: + // Event bus enable to all units. + assign pc_iu_event_bus_enable = cesr1_out[32]; + assign pc_fu_event_bus_enable = cesr1_out[32]; + assign pc_rv_event_bus_enable = cesr1_out[32]; + assign pc_mm_event_bus_enable = cesr1_out[32]; + assign pc_xu_event_bus_enable = cesr1_out[32]; + assign pc_lq_event_bus_enable = cesr1_out[32]; + // Count modes function to all units. + assign pc_iu_event_count_mode = cesr1_out[33:35]; + assign pc_fu_event_count_mode = cesr1_out[33:35]; + assign pc_rv_event_count_mode = cesr1_out[33:35]; + assign pc_mm_event_count_mode = cesr1_out[33:35]; + assign pc_xu_event_count_mode = cesr1_out[33:35]; + assign pc_lq_event_count_mode = cesr1_out[33:35]; + // Trace bus enable to all units (from pcq_regs). + assign sp_rg_trace_bus_enable = cesr1_out[36]; + // Select trace bits for event counting. + assign pc_lq_event_bus_seldbghi = cesr1_out[38]; + assign pc_lq_event_bus_seldbglo = cesr1_out[39]; + // Instruction tracing. + assign pc_iu_instr_trace_mode = cesr1_out[40]; + assign pc_iu_instr_trace_tid = cesr1_out[41]; + assign pc_lq_instr_trace_mode = cesr1_out[40]; + assign pc_lq_instr_trace_tid = cesr1_out[41]; + assign pc_xu_instr_trace_mode = cesr1_out[40]; + assign pc_xu_instr_trace_tid = cesr1_out[41]; + +//===================================================================== +// Instruction sampling +//===================================================================== + generate + if (`THREADS == 1) + begin : T1_INSTRSAMP + assign pc_xu_spr_cesr1_pmae = cesr1_is0_l2[0]; + assign perfmon_alert_din = {xu_pc_perfmon_alert[0], 1'b0}; + end + endgenerate + + generate + if (`THREADS == 2) + begin : T2_INSTRSAMP + assign pc_xu_spr_cesr1_pmae = {cesr1_is0_l2[0], cesr1_is1_l2[0]}; + assign perfmon_alert_din = xu_pc_perfmon_alert[0:1]; + end + endgenerate + +//===================================================================== +// register select +//===================================================================== + assign cesr1_sel = slowspr_val_l2 & slowspr_addr_l2 == 10'b1110010000; // 912 + assign resr1_sel = slowspr_val_l2 & slowspr_addr_l2 == 10'b1110011010; // 922 + assign resr2_sel = slowspr_val_l2 & slowspr_addr_l2 == 10'b1110011011; // 923 + assign sramd_sel = slowspr_val_l2 & slowspr_addr_l2 == 10'b1101111110; // 894 + + assign pc_done_int = cesr1_sel | resr1_sel | resr2_sel | sramd_sel; + +//===================================================================== +// register write +//===================================================================== + assign cesr1_wren = cesr1_sel & slowspr_rw_l2 == 1'b0; + assign resr1_wren = resr1_sel & slowspr_rw_l2 == 1'b0; + assign resr2_wren = resr2_sel & slowspr_rw_l2 == 1'b0; + assign sramd_wren = rg_rg_load_sramd; + + assign cesr1_d = CESR1_MASK[32:32 + CESR1_SIZE - 1] & slowspr_data_l2[32:32 + CESR1_SIZE - 1]; + assign resr1_d = EVENTMUX_64_MASK[32:32 + RESR1_SIZE - 1] & slowspr_data_l2[32:32 + RESR1_SIZE - 1]; + assign resr2_d = EVENTMUX_64_MASK[32:32 + RESR2_SIZE - 1] & slowspr_data_l2[32:32 + RESR2_SIZE - 1]; + assign sramd_d = rg_rg_sramd_din; + + // Instruction Sampling + assign update_is_ctrls = {(perfmon_alert_q[0] & cesr1_is0_l2[0]), (perfmon_alert_q[1] & cesr1_is1_l2[0])}; + assign cesr1_is_wren = {(cesr1_wren | update_is_ctrls[0]), (cesr1_wren | update_is_ctrls[1])}; + + assign cesr1_is0_d[0] = CESR1_MASK[44] & slowspr_data_l2[44] & (~update_is_ctrls[0]); // PMAE_T0 cleared on perfmon alert. + assign cesr1_is0_d[1] = (CESR1_MASK[45] & slowspr_data_l2[45] & (~update_is_ctrls[0])) | update_is_ctrls[0]; // PMAO_T0 set on perfmon alert. + assign cesr1_is1_d[0] = CESR1_MASK[46] & slowspr_data_l2[46] & (~update_is_ctrls[1]); // PMAE_T1 cleared on perfmon alert. + assign cesr1_is1_d[1] = (CESR1_MASK[47] & slowspr_data_l2[47] & (~update_is_ctrls[1])) | update_is_ctrls[1]; // PMAO_T1 set on perfmon alert. + +//===================================================================== +// register read +//===================================================================== + assign cesr1_rden = cesr1_sel & slowspr_rw_l2 == 1'b1; + assign resr1_rden = resr1_sel & slowspr_rw_l2 == 1'b1; + assign resr2_rden = resr2_sel & slowspr_rw_l2 == 1'b1; + assign sramd_rden = sramd_sel & slowspr_rw_l2 == 1'b1; + + assign cesr1_out[32:63] = {cesr1_l2, cesr1_is0_l2, cesr1_is1_l2, {64-(32+CESR1_SIZE+CESR1_IS0_SIZE+CESR1_IS1_SIZE){1'b0}} }; + assign resr1_out[32:63] = {resr1_l2, {64-(32+RESR1_SIZE){1'b0}} }; + assign resr2_out[32:63] = {resr2_l2, {64-(32+RESR2_SIZE){1'b0}} }; + assign sramd_out[0:63] = sramd_l2; + + assign pc_reg_data[32:63] = (cesr1_rden == 1'b1) ? cesr1_out : + (resr1_rden == 1'b1) ? resr1_out : + (resr2_rden == 1'b1) ? resr2_out : + (sramd_rden == 1'b1) ? sramd_out[32:63] : + {32{1'b0}}; + + generate + if (`GPR_WIDTH > 32) + begin : r64 + assign pc_data_int[0:31] = (sramd_rden == 1'b1) ? sramd_out[0:31] : + {32{1'b0}}; + end + endgenerate + assign pc_data_int[32:63] = pc_reg_data[32:63]; + + +//===================================================================== +// Trace/Trigger Signals +//===================================================================== + assign dbg_spr = { cesr1_wren, // 0 + sramd_wren, // 1 + perfmon_alert_q[0:1], // 2:3 + cesr1_is0_l2[0:1], // 4:5 + cesr1_is1_l2[0:1] // 6:7 + }; + +//===================================================================== +// Thold/SG Staging +//===================================================================== + // func_slp lcbor + tri_lcbor lcbor_funcslp( + .clkoff_b(lcb_clkoff_dc_b), + .thold(pc_pc_func_sl_thold_0), + .sg(pc_pc_sg_0), + .act_dis(lcb_act_dis_dc), + .force_t(force_func), + .thold_b(pc_pc_func_sl_thold_0_b) + ); + +//===================================================================== +// Scan Connections +//===================================================================== + // Func ring + assign func_siv[0:FUNC_RIGHT] = {func_scan_in, func_sov[0:FUNC_RIGHT - 1]}; + assign func_scan_out = func_sov[FUNC_RIGHT] & scan_dis_dc_b; + + +endmodule diff --git a/dev/verilog/work/rv.v b/dev/verilog/work/rv.v new file mode 100755 index 0000000..292555e --- /dev/null +++ b/dev/verilog/work/rv.v @@ -0,0 +1,2490 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +`timescale 1 ns / 1 ns + +//----------------------------------------------------------------------------------------------------- +// Title: rv.vhdl +// Desc: top level of Reservation station heirarchy. +// contains reservation stations for the three main fixed point functional units +// as well as the operand available scorecard and associated inline compare logic. +// +// Notes: +// All indexes are assumed to be physical register indices +// +// Interface to the fetcher is actual instruction, renamed physical register fields, 20 bits of ifar, and 20 bits of +// the bta. Lots of bits. +// +//----------------------------------------------------------------------------------------------------- + +(* recursive_synthesis="0" *) + +module rv( +`include "tri_a2o.vh" + + //------------------------------------------------------------------------------------------------------------ + // Instructions from IU + //------------------------------------------------------------------------------------------------------------ + input iu_rv_iu6_t0_i0_vld, + input iu_rv_iu6_t0_i0_rte_lq, + input iu_rv_iu6_t0_i0_rte_sq, + input iu_rv_iu6_t0_i0_rte_fx0, + input iu_rv_iu6_t0_i0_rte_fx1, + input iu_rv_iu6_t0_i0_rte_axu0, + input iu_rv_iu6_t0_i0_rte_axu1, + input iu_rv_iu6_t0_i0_act , + input [0:31] iu_rv_iu6_t0_i0_instr, + input [0:`EFF_IFAR_WIDTH-1] iu_rv_iu6_t0_i0_ifar, + input [0:2] iu_rv_iu6_t0_i0_ucode, + input iu_rv_iu6_t0_i0_2ucode, + input [0:`UCODE_ENTRIES_ENC-1] iu_rv_iu6_t0_i0_ucode_cnt, + input [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i0_itag, + input iu_rv_iu6_t0_i0_ord, + input iu_rv_iu6_t0_i0_cord, + input iu_rv_iu6_t0_i0_spec, + input iu_rv_iu6_t0_i0_t1_v, + input [0:2] iu_rv_iu6_t0_i0_t1_t, + input [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_t1_p, + input iu_rv_iu6_t0_i0_t2_v, + input [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_t2_p, + input [0:2] iu_rv_iu6_t0_i0_t2_t, + input iu_rv_iu6_t0_i0_t3_v, + input [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_t3_p, + input [0:2] iu_rv_iu6_t0_i0_t3_t, + input iu_rv_iu6_t0_i0_s1_v, + input [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_s1_p, + input [0:2] iu_rv_iu6_t0_i0_s1_t, + input iu_rv_iu6_t0_i0_s2_v, + input [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_s2_p, + input [0:2] iu_rv_iu6_t0_i0_s2_t, + input iu_rv_iu6_t0_i0_s3_v, + input [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_s3_p, + input [0:2] iu_rv_iu6_t0_i0_s3_t, + input [0:3] iu_rv_iu6_t0_i0_ilat, + input [0:`EFF_IFAR_WIDTH-1] iu_rv_iu6_t0_i0_bta, + input iu_rv_iu6_t0_i0_bta_val, + input iu_rv_iu6_t0_i0_br_pred, + input [0:`EFF_IFAR_WIDTH-1] iu_rv_iu6_t0_i0_fusion, + input [0:2] iu_rv_iu6_t0_i0_ls_ptr, + input [0:17] iu_rv_iu6_t0_i0_gshare, + input iu_rv_iu6_t0_i0_bh_update, + input iu_rv_iu6_t0_i0_isLoad, + input iu_rv_iu6_t0_i0_isStore, + input [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i0_s1_itag, + input [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i0_s2_itag, + input [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i0_s3_itag, + input iu_rv_iu6_t0_i1_vld, + input iu_rv_iu6_t0_i1_rte_lq, + input iu_rv_iu6_t0_i1_rte_sq, + input iu_rv_iu6_t0_i1_rte_fx0, + input iu_rv_iu6_t0_i1_rte_fx1, + input iu_rv_iu6_t0_i1_rte_axu0, + input iu_rv_iu6_t0_i1_rte_axu1, + input iu_rv_iu6_t0_i1_act , + input [0:31] iu_rv_iu6_t0_i1_instr, + input [0:`EFF_IFAR_WIDTH-1] iu_rv_iu6_t0_i1_ifar, + input [0:2] iu_rv_iu6_t0_i1_ucode, + input [0:`UCODE_ENTRIES_ENC-1] iu_rv_iu6_t0_i1_ucode_cnt, + input [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i1_itag, + input iu_rv_iu6_t0_i1_ord, + input iu_rv_iu6_t0_i1_cord, + input iu_rv_iu6_t0_i1_spec, + input iu_rv_iu6_t0_i1_t1_v, + input [0:2] iu_rv_iu6_t0_i1_t1_t, + input [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_t1_p, + input iu_rv_iu6_t0_i1_t2_v, + input [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_t2_p, + input [0:2] iu_rv_iu6_t0_i1_t2_t, + input iu_rv_iu6_t0_i1_t3_v, + input [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_t3_p, + input [0:2] iu_rv_iu6_t0_i1_t3_t, + input iu_rv_iu6_t0_i1_s1_v, + input [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_s1_p, + input [0:2] iu_rv_iu6_t0_i1_s1_t, + input iu_rv_iu6_t0_i1_s2_v, + input [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_s2_p, + input [0:2] iu_rv_iu6_t0_i1_s2_t, + input iu_rv_iu6_t0_i1_s3_v, + input [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_s3_p, + input [0:2] iu_rv_iu6_t0_i1_s3_t, + input [0:3] iu_rv_iu6_t0_i1_ilat, + input [0:`EFF_IFAR_WIDTH-1] iu_rv_iu6_t0_i1_bta, + input iu_rv_iu6_t0_i1_bta_val, + input iu_rv_iu6_t0_i1_br_pred, + input [0:`EFF_IFAR_WIDTH-1] iu_rv_iu6_t0_i1_fusion, + input [0:2] iu_rv_iu6_t0_i1_ls_ptr, + input [0:17] iu_rv_iu6_t0_i1_gshare, + input iu_rv_iu6_t0_i1_bh_update, + input iu_rv_iu6_t0_i1_isLoad, + input iu_rv_iu6_t0_i1_isStore, + input [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i1_s1_itag, + input [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i1_s2_itag, + input [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i1_s3_itag, + input iu_rv_iu6_t0_i1_s1_dep_hit, + input iu_rv_iu6_t0_i1_s2_dep_hit, + input iu_rv_iu6_t0_i1_s3_dep_hit, + input [0:`ITAG_SIZE_ENC-1] cp_t0_next_itag, + +`ifndef THREADS1 + + input iu_rv_iu6_t1_i0_vld, + input iu_rv_iu6_t1_i0_rte_lq, + input iu_rv_iu6_t1_i0_rte_sq, + input iu_rv_iu6_t1_i0_rte_fx0, + input iu_rv_iu6_t1_i0_rte_fx1, + input iu_rv_iu6_t1_i0_rte_axu0, + input iu_rv_iu6_t1_i0_rte_axu1, + input iu_rv_iu6_t1_i0_act , + input [0:31] iu_rv_iu6_t1_i0_instr, + input [0:`EFF_IFAR_WIDTH-1] iu_rv_iu6_t1_i0_ifar, + input [0:2] iu_rv_iu6_t1_i0_ucode, + input iu_rv_iu6_t1_i0_2ucode, + input [0:`UCODE_ENTRIES_ENC-1] iu_rv_iu6_t1_i0_ucode_cnt, + input [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i0_itag, + input iu_rv_iu6_t1_i0_ord, + input iu_rv_iu6_t1_i0_cord, + input iu_rv_iu6_t1_i0_spec, + input iu_rv_iu6_t1_i0_t1_v, + input [0:2] iu_rv_iu6_t1_i0_t1_t, + input [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_t1_p, + input iu_rv_iu6_t1_i0_t2_v, + input [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_t2_p, + input [0:2] iu_rv_iu6_t1_i0_t2_t, + input iu_rv_iu6_t1_i0_t3_v, + input [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_t3_p, + input [0:2] iu_rv_iu6_t1_i0_t3_t, + input iu_rv_iu6_t1_i0_s1_v, + input [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_s1_p, + input [0:2] iu_rv_iu6_t1_i0_s1_t, + input iu_rv_iu6_t1_i0_s2_v, + input [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_s2_p, + input [0:2] iu_rv_iu6_t1_i0_s2_t, + input iu_rv_iu6_t1_i0_s3_v, + input [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_s3_p, + input [0:2] iu_rv_iu6_t1_i0_s3_t, + input [0:3] iu_rv_iu6_t1_i0_ilat, + input [0:`EFF_IFAR_WIDTH-1] iu_rv_iu6_t1_i0_bta, + input iu_rv_iu6_t1_i0_bta_val, + input iu_rv_iu6_t1_i0_br_pred, + input [0:`EFF_IFAR_WIDTH-1] iu_rv_iu6_t1_i0_fusion, + input [0:2] iu_rv_iu6_t1_i0_ls_ptr, + input [0:17] iu_rv_iu6_t1_i0_gshare, + input iu_rv_iu6_t1_i0_bh_update, + input iu_rv_iu6_t1_i0_isLoad, + input iu_rv_iu6_t1_i0_isStore, + input [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i0_s1_itag, + input [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i0_s2_itag, + input [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i0_s3_itag, + + input iu_rv_iu6_t1_i1_vld, + input iu_rv_iu6_t1_i1_rte_lq, + input iu_rv_iu6_t1_i1_rte_sq, + input iu_rv_iu6_t1_i1_rte_fx0, + input iu_rv_iu6_t1_i1_rte_fx1, + input iu_rv_iu6_t1_i1_rte_axu0, + input iu_rv_iu6_t1_i1_rte_axu1, + input iu_rv_iu6_t1_i1_act , + input [0:31] iu_rv_iu6_t1_i1_instr, + input [0:`EFF_IFAR_WIDTH-1] iu_rv_iu6_t1_i1_ifar, + input [0:2] iu_rv_iu6_t1_i1_ucode, + input [0:`UCODE_ENTRIES_ENC-1] iu_rv_iu6_t1_i1_ucode_cnt, + input [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i1_itag, + input iu_rv_iu6_t1_i1_ord, + input iu_rv_iu6_t1_i1_cord, + input iu_rv_iu6_t1_i1_spec, + input iu_rv_iu6_t1_i1_t1_v, + input [0:2] iu_rv_iu6_t1_i1_t1_t, + input [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_t1_p, + input iu_rv_iu6_t1_i1_t2_v, + input [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_t2_p, + input [0:2] iu_rv_iu6_t1_i1_t2_t, + input iu_rv_iu6_t1_i1_t3_v, + input [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_t3_p, + input [0:2] iu_rv_iu6_t1_i1_t3_t, + input iu_rv_iu6_t1_i1_s1_v, + input [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_s1_p, + input [0:2] iu_rv_iu6_t1_i1_s1_t, + input iu_rv_iu6_t1_i1_s2_v, + input [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_s2_p, + input [0:2] iu_rv_iu6_t1_i1_s2_t, + input iu_rv_iu6_t1_i1_s3_v, + input [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_s3_p, + input [0:2] iu_rv_iu6_t1_i1_s3_t, + input [0:3] iu_rv_iu6_t1_i1_ilat, + input [0:`EFF_IFAR_WIDTH-1] iu_rv_iu6_t1_i1_bta, + input iu_rv_iu6_t1_i1_bta_val, + input iu_rv_iu6_t1_i1_br_pred, + input [0:`EFF_IFAR_WIDTH-1] iu_rv_iu6_t1_i1_fusion, + input [0:2] iu_rv_iu6_t1_i1_ls_ptr, + input [0:17] iu_rv_iu6_t1_i1_gshare, + input iu_rv_iu6_t1_i1_bh_update, + input iu_rv_iu6_t1_i1_isLoad, + input iu_rv_iu6_t1_i1_isStore, + input [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i1_s1_itag, + input [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i1_s2_itag, + input [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i1_s3_itag, + input iu_rv_iu6_t1_i1_s1_dep_hit, + input iu_rv_iu6_t1_i1_s2_dep_hit, + input iu_rv_iu6_t1_i1_s3_dep_hit, + + input [0:`ITAG_SIZE_ENC-1] cp_t1_next_itag, +`endif + + //------------------------------------------------------------------------------------------------------------ + // Credit Interface with IU + //------------------------------------------------------------------------------------------------------------ + output [0:`THREADS-1] rv_iu_lq_credit_free, + output [0:`THREADS-1] rv_iu_fx0_credit_free, + output [0:`THREADS-1] rv_iu_fx1_credit_free, + output [0:`THREADS-1] rv_iu_axu0_credit_free, + output [0:`THREADS-1] rv_iu_axu1_credit_free, + + //------------------------------------------------------------------------------------------------------------ + // Machine zap interface + //------------------------------------------------------------------------------------------------------------ + input [0:`THREADS-1] cp_flush, + + //------------------------------------------------------------------------------------------------------------ + // Interface to FX0 + //------------------------------------------------------------------------------------------------------------ + output [0:`THREADS-1] rv_fx0_vld, + output rv_fx0_s1_v, + output [0:`GPR_POOL_ENC-1] rv_fx0_s1_p, + output rv_fx0_s2_v, + output [0:`GPR_POOL_ENC-1] rv_fx0_s2_p, + output rv_fx0_s3_v, + output [0:`GPR_POOL_ENC-1] rv_fx0_s3_p, + + output [0:`ITAG_SIZE_ENC-1] rv_fx0_ex0_itag, + output [0:31] rv_fx0_ex0_instr, + output [62-`EFF_IFAR_WIDTH:61] rv_fx0_ex0_ifar, + output [0:2] rv_fx0_ex0_ucode, + output [0:`UCODE_ENTRIES_ENC-1] rv_fx0_ex0_ucode_cnt, + output rv_fx0_ex0_ord, + output rv_fx0_ex0_t1_v, + output [0:`GPR_POOL_ENC-1] rv_fx0_ex0_t1_p, + output [0:2] rv_fx0_ex0_t1_t, + output rv_fx0_ex0_t2_v, + output [0:`GPR_POOL_ENC-1] rv_fx0_ex0_t2_p, + output [0:2] rv_fx0_ex0_t2_t, + output rv_fx0_ex0_t3_v, + output [0:`GPR_POOL_ENC-1] rv_fx0_ex0_t3_p, + output [0:2] rv_fx0_ex0_t3_t, + output rv_fx0_ex0_s1_v, + output rv_fx0_ex0_s2_v, + output [0:2] rv_fx0_ex0_s2_t, + output rv_fx0_ex0_s3_v, + output [0:2] rv_fx0_ex0_s3_t, + output [0:19] rv_fx0_ex0_fusion, + output [62-`EFF_IFAR_WIDTH:61] rv_fx0_ex0_pred_bta, + output rv_fx0_ex0_bta_val, + output rv_fx0_ex0_br_pred, + output [0:2] rv_fx0_ex0_ls_ptr, + output [0:17] rv_fx0_ex0_gshare, + output rv_fx0_ex0_bh_update, + + input fx0_rv_ord_complete, + input [0:`ITAG_SIZE_ENC-1] fx0_rv_ord_itag, + input fx0_rv_hold_all, + + //------------------------------------------------------------------------------------------------------------ + // Interface to FX1 + //------------------------------------------------------------------------------------------------------------ + output [0:`THREADS-1] rv_fx1_vld, + output rv_fx1_s1_v, + output [0:`GPR_POOL_ENC-1] rv_fx1_s1_p, + output rv_fx1_s2_v, + output [0:`GPR_POOL_ENC-1] rv_fx1_s2_p, + output rv_fx1_s3_v, + output [0:`GPR_POOL_ENC-1] rv_fx1_s3_p, + + output [0:`ITAG_SIZE_ENC-1] rv_fx1_ex0_itag, + output [0:31] rv_fx1_ex0_instr, + output [0:2] rv_fx1_ex0_ucode, + output rv_fx1_ex0_t1_v, + output [0:`GPR_POOL_ENC-1] rv_fx1_ex0_t1_p, + output rv_fx1_ex0_t2_v, + output [0:`GPR_POOL_ENC-1] rv_fx1_ex0_t2_p, + output rv_fx1_ex0_t3_v, + output [0:`GPR_POOL_ENC-1] rv_fx1_ex0_t3_p, + output rv_fx1_ex0_s1_v, + output [0:2] rv_fx1_ex0_s3_t, + output rv_fx1_ex0_isStore, + + input fx1_rv_hold_all, + + //------------------------------------------------------------------------------------------------------------ + // Interface to LQ + //------------------------------------------------------------------------------------------------------------ + output [0:`THREADS-1] rv_lq_vld, + output rv_lq_isLoad, + + output [0:`ITAG_SIZE_ENC-1] rv_lq_ex0_itag, + output [0:31] rv_lq_ex0_instr, + output [0:2] rv_lq_ex0_ucode, + output [0:`UCODE_ENTRIES_ENC-1] rv_lq_ex0_ucode_cnt, + output rv_lq_ex0_spec, + output rv_lq_ex0_t1_v, + output [0:`GPR_POOL_ENC-1] rv_lq_ex0_t1_p, + output [0:`GPR_POOL_ENC-1] rv_lq_ex0_t3_p, + output rv_lq_ex0_s1_v, + output rv_lq_ex0_s2_v, + output [0:2] rv_lq_ex0_s2_t, + + input [0:`THREADS-1] lq_rv_itag0_vld, + input [0:`ITAG_SIZE_ENC-1] lq_rv_itag0, + input lq_rv_itag0_abort, + + input [0:`THREADS-1] lq_rv_itag1_vld, + input [0:`ITAG_SIZE_ENC-1] lq_rv_itag1, + input lq_rv_itag1_abort, + input lq_rv_itag1_restart, + input lq_rv_itag1_hold, + input lq_rv_itag1_cord, + + input [0:`THREADS-1] lq_rv_itag2_vld, + input [0:`ITAG_SIZE_ENC-1] lq_rv_itag2, + + input [0:`THREADS-1] lq_rv_clr_hold, + + input lq_rv_ord_complete, + input lq_rv_hold_all, + + output [0:`THREADS-1] rv_lq_rv1_i0_vld, + output rv_lq_rv1_i0_ucode_preissue, + output rv_lq_rv1_i0_2ucode, + output [0:`UCODE_ENTRIES_ENC-1] rv_lq_rv1_i0_ucode_cnt, + output [0:2] rv_lq_rv1_i0_s3_t, + output rv_lq_rv1_i0_isLoad, + output rv_lq_rv1_i0_isStore, + output [0:`ITAG_SIZE_ENC-1] rv_lq_rv1_i0_itag, + output rv_lq_rv1_i0_rte_lq, + output rv_lq_rv1_i0_rte_sq, + output [61-`PF_IAR_BITS+1:61] rv_lq_rv1_i0_ifar, + + output [0:`THREADS-1] rv_lq_rv1_i1_vld, + output rv_lq_rv1_i1_ucode_preissue, + output rv_lq_rv1_i1_2ucode, + output [0:`UCODE_ENTRIES_ENC-1] rv_lq_rv1_i1_ucode_cnt, + output [0:2] rv_lq_rv1_i1_s3_t, + output rv_lq_rv1_i1_isLoad, + output rv_lq_rv1_i1_isStore, + output [0:`ITAG_SIZE_ENC-1] rv_lq_rv1_i1_itag, + output rv_lq_rv1_i1_rte_lq, + output rv_lq_rv1_i1_rte_sq, + output [61-`PF_IAR_BITS+1:61] rv_lq_rv1_i1_ifar, + + output [0:`THREADS-1] rv_lq_rvs_empty, + + //------------------------------------------------------------------------------------------------------------ + // Interface to AXU0 + //------------------------------------------------------------------------------------------------------------ + output [0:`THREADS-1] rv_axu0_vld, + output rv_axu0_s1_v, + output [0:`GPR_POOL_ENC-1] rv_axu0_s1_p, + output rv_axu0_s2_v, + output [0:`GPR_POOL_ENC-1] rv_axu0_s2_p, + output rv_axu0_s3_v, + output [0:`GPR_POOL_ENC-1] rv_axu0_s3_p, + + output [0:`ITAG_SIZE_ENC-1] rv_axu0_ex0_itag, + output [0:31] rv_axu0_ex0_instr, + output [0:2] rv_axu0_ex0_ucode, + output rv_axu0_ex0_t1_v, + output [0:`GPR_POOL_ENC-1] rv_axu0_ex0_t1_p, + output [0:`GPR_POOL_ENC-1] rv_axu0_ex0_t2_p, + output [0:`GPR_POOL_ENC-1] rv_axu0_ex0_t3_p, + + input [0:`THREADS-1] axu0_rv_itag_vld, + input [0:`ITAG_SIZE_ENC-1] axu0_rv_itag, + input axu0_rv_itag_abort, + + input axu0_rv_ord_complete, + input axu0_rv_hold_all, + + //------------------------------------------------------------------------------------------------------------ + // Interface to AXU1 + //------------------------------------------------------------------------------------------------------------ + + input [0:`THREADS-1] axu1_rv_itag_vld, + input [0:`ITAG_SIZE_ENC-1] axu1_rv_itag, + input axu1_rv_itag_abort, + input axu1_rv_hold_all, + + //------------------------------------------------------------------------------------------------------------ + // Abort Mechanism + //------------------------------------------------------------------------------------------------------------ + input lq_rv_ex2_s1_abort, + input lq_rv_ex2_s2_abort, + input fx0_rv_ex2_s1_abort, + input fx0_rv_ex2_s2_abort, + input fx0_rv_ex2_s3_abort, + input fx1_rv_ex2_s1_abort, + input fx1_rv_ex2_s2_abort, + input fx1_rv_ex2_s3_abort, + input axu0_rv_ex2_s1_abort, + input axu0_rv_ex2_s2_abort, + input axu0_rv_ex2_s3_abort, + + //------------------------------------------------------------------------------------------------------------ + // Bypass Control + //------------------------------------------------------------------------------------------------------------ + //------------------------------------------------------------------- + // Interface with FXU0 + //------------------------------------------------------------------- + output [1:11] rv_fx0_ex0_s1_fx0_sel, + output [1:11] rv_fx0_ex0_s2_fx0_sel, + output [1:11] rv_fx0_ex0_s3_fx0_sel, + output [4:8] rv_fx0_ex0_s1_lq_sel, + output [4:8] rv_fx0_ex0_s2_lq_sel, + output [4:8] rv_fx0_ex0_s3_lq_sel, + output [1:6] rv_fx0_ex0_s1_fx1_sel, + output [1:6] rv_fx0_ex0_s2_fx1_sel, + output [1:6] rv_fx0_ex0_s3_fx1_sel, + + //------------------------------------------------------------------- + // Interface with LQ + //------------------------------------------------------------------- + output [2:12] rv_lq_ex0_s1_fx0_sel, + output [2:12] rv_lq_ex0_s2_fx0_sel, + output [4:8] rv_lq_ex0_s1_lq_sel, + output [4:8] rv_lq_ex0_s2_lq_sel, + output [2:7] rv_lq_ex0_s1_fx1_sel, + output [2:7] rv_lq_ex0_s2_fx1_sel, + + //------------------------------------------------------------------- + // Interface with FXU1 + //------------------------------------------------------------------- + output [1:11] rv_fx1_ex0_s1_fx0_sel, + output [1:11] rv_fx1_ex0_s2_fx0_sel, + output [1:11] rv_fx1_ex0_s3_fx0_sel, + output [4:8] rv_fx1_ex0_s1_lq_sel, + output [4:8] rv_fx1_ex0_s2_lq_sel, + output [4:8] rv_fx1_ex0_s3_lq_sel, + output [1:6] rv_fx1_ex0_s1_fx1_sel, + output [1:6] rv_fx1_ex0_s2_fx1_sel, + output [1:6] rv_fx1_ex0_s3_fx1_sel, + + output [2:3] rv_fx0_ex0_s1_rel_sel, + output [2:3] rv_fx0_ex0_s2_rel_sel, + output [2:3] rv_fx0_ex0_s3_rel_sel, + output [2:3] rv_lq_ex0_s1_rel_sel, + output [2:3] rv_lq_ex0_s2_rel_sel, + output [2:3] rv_fx1_ex0_s1_rel_sel, + output [2:3] rv_fx1_ex0_s2_rel_sel, + output [2:3] rv_fx1_ex0_s3_rel_sel, + + //------------------------------------------------------------------------------------------------------------ + // LQ Regfile + //------------------------------------------------------------------------------------------------------------ + // Write ports + input xu0_gpr_ex6_we, + input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] xu0_gpr_ex6_wa, + input [64-`GPR_WIDTH:63+(`GPR_WIDTH/8)] xu0_gpr_ex6_wd, + input xu1_gpr_ex3_we, + input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] xu1_gpr_ex3_wa, + input [64-`GPR_WIDTH:63+(`GPR_WIDTH/8)] xu1_gpr_ex3_wd, + + input lq_rv_gpr_ex6_we, + input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] lq_rv_gpr_ex6_wa, + input [64-`GPR_WIDTH:63+(`GPR_WIDTH/8)] lq_rv_gpr_ex6_wd, + + input lq_rv_gpr_rel_we, + input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] lq_rv_gpr_rel_wa, + input [64-`GPR_WIDTH:63+(`GPR_WIDTH/8)] lq_rv_gpr_rel_wd, + + // Read ports + output [64-`GPR_WIDTH:63+(`GPR_WIDTH/8)] rv_lq_gpr_ex1_r0d, + output [64-`GPR_WIDTH:63+(`GPR_WIDTH/8)] rv_lq_gpr_ex1_r1d, + + //------------------------------------------------------------------------------------------------------------ + // Debug and Perf + //------------------------------------------------------------------------------------------------------------ + input pc_rv_trace_bus_enable, + input [0:10] pc_rv_debug_mux_ctrls, + input pc_rv_event_bus_enable, + input [0:2] pc_rv_event_count_mode, + input [0:39] pc_rv_event_mux_ctrls, + input [0:4*`THREADS-1] rv_event_bus_in, + output [0:4*`THREADS-1] rv_event_bus_out, + output [0:31] debug_bus_out, + input [0:31] debug_bus_in, + input [0:3] coretrace_ctrls_in, + output [0:3] coretrace_ctrls_out, + input [0:`THREADS-1] spr_msr_gs, + input [0:`THREADS-1] spr_msr_pr, + //------------------------------------------------------------------------------------------------------------ + // Pervasive + //------------------------------------------------------------------------------------------------------------ + (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) // nclk + input[0:`NCLK_WIDTH-1] nclk, + + input rp_rv_ccflush_dc, + input rp_rv_func_sl_thold_3, + input rp_rv_gptr_sl_thold_3, + input rp_rv_sg_3, + input rp_rv_fce_3, + input an_ac_scan_diag_dc, + input an_ac_scan_dis_dc_b, + + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) // scan_in + input scan_in, + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) // scan_out + output scan_out + + ); + + wire [0:`THREADS*`ITAG_SIZE_ENC-1] cp_next_itag; + wire [0:`G_BRANCH_LEN-1] iu_rv_iu6_t0_i0_branch; + wire [0:`G_BRANCH_LEN-1] iu_rv_iu6_t0_i1_branch; +`ifndef THREADS1 + wire [0:`G_BRANCH_LEN-1] iu_rv_iu6_t1_i0_branch; + wire [0:`G_BRANCH_LEN-1] iu_rv_iu6_t1_i1_branch; +`endif + wire [0:`G_BRANCH_LEN-1] rv_fx0_ex0_branch; + + + wire [0:`THREADS-1] rv0_fx0_instr_i0_vld; + wire rv0_fx0_instr_i0_rte_fx0; + wire [0:31] rv0_fx0_instr_i0_instr; + wire [62-`EFF_IFAR_WIDTH:61] rv0_fx0_instr_i0_ifar; + wire [0:2] rv0_fx0_instr_i0_ucode; + wire [0:`UCODE_ENTRIES_ENC-1] rv0_fx0_instr_i0_ucode_cnt; + wire [0:`ITAG_SIZE_ENC-1] rv0_fx0_instr_i0_itag; + wire rv0_fx0_instr_i0_ord; + wire rv0_fx0_instr_i0_cord; + wire rv0_fx0_instr_i0_t1_v; + wire [0:`GPR_POOL_ENC-1] rv0_fx0_instr_i0_t1_p; + wire [0:2] rv0_fx0_instr_i0_t1_t; + wire rv0_fx0_instr_i0_t2_v; + wire [0:`GPR_POOL_ENC-1] rv0_fx0_instr_i0_t2_p; + wire [0:2] rv0_fx0_instr_i0_t2_t; + wire rv0_fx0_instr_i0_t3_v; + wire [0:`GPR_POOL_ENC-1] rv0_fx0_instr_i0_t3_p; + wire [0:2] rv0_fx0_instr_i0_t3_t; + wire rv0_fx0_instr_i0_s1_v; + wire [0:`GPR_POOL_ENC-1] rv0_fx0_instr_i0_s1_p; + wire [0:2] rv0_fx0_instr_i0_s1_t; + wire rv0_fx0_instr_i0_s2_v; + wire [0:`GPR_POOL_ENC-1] rv0_fx0_instr_i0_s2_p; + wire [0:2] rv0_fx0_instr_i0_s2_t; + wire rv0_fx0_instr_i0_s3_v; + wire [0:`GPR_POOL_ENC-1] rv0_fx0_instr_i0_s3_p; + wire [0:2] rv0_fx0_instr_i0_s3_t; + wire [0:3] rv0_fx0_instr_i0_ilat; + wire [0:`G_BRANCH_LEN-1] rv0_fx0_instr_i0_branch; + wire [0:3] rv0_fx0_instr_i0_spare; + wire rv0_fx0_instr_i0_is_brick; + wire [0:2] rv0_fx0_instr_i0_brick; + wire [0:`THREADS-1] rv0_fx0_instr_i1_vld; + wire rv0_fx0_instr_i1_rte_fx0; + wire [0:31] rv0_fx0_instr_i1_instr; + wire [62-`EFF_IFAR_WIDTH:61] rv0_fx0_instr_i1_ifar; + wire [0:2] rv0_fx0_instr_i1_ucode; + wire [0:`UCODE_ENTRIES_ENC-1] rv0_fx0_instr_i1_ucode_cnt; + wire [0:`ITAG_SIZE_ENC-1] rv0_fx0_instr_i1_itag; + wire rv0_fx0_instr_i1_ord; + wire rv0_fx0_instr_i1_cord; + wire rv0_fx0_instr_i1_t1_v; + wire [0:`GPR_POOL_ENC-1] rv0_fx0_instr_i1_t1_p; + wire [0:2] rv0_fx0_instr_i1_t1_t; + wire rv0_fx0_instr_i1_t2_v; + wire [0:`GPR_POOL_ENC-1] rv0_fx0_instr_i1_t2_p; + wire [0:2] rv0_fx0_instr_i1_t2_t; + wire rv0_fx0_instr_i1_t3_v; + wire [0:`GPR_POOL_ENC-1] rv0_fx0_instr_i1_t3_p; + wire [0:2] rv0_fx0_instr_i1_t3_t; + wire rv0_fx0_instr_i1_s1_v; + wire [0:`GPR_POOL_ENC-1] rv0_fx0_instr_i1_s1_p; + wire [0:2] rv0_fx0_instr_i1_s1_t; + wire rv0_fx0_instr_i1_s2_v; + wire [0:`GPR_POOL_ENC-1] rv0_fx0_instr_i1_s2_p; + wire [0:2] rv0_fx0_instr_i1_s2_t; + wire rv0_fx0_instr_i1_s3_v; + wire [0:`GPR_POOL_ENC-1] rv0_fx0_instr_i1_s3_p; + wire [0:2] rv0_fx0_instr_i1_s3_t; + wire [0:3] rv0_fx0_instr_i1_ilat; + wire [0:`G_BRANCH_LEN-1] rv0_fx0_instr_i1_branch; + wire [0:3] rv0_fx0_instr_i1_spare; + wire rv0_fx0_instr_i1_is_brick; + wire [0:2] rv0_fx0_instr_i1_brick; + wire rv0_fx0_instr_i0_s1_dep_hit; + wire [0:`ITAG_SIZE_ENC-1] rv0_fx0_instr_i0_s1_itag; + wire rv0_fx0_instr_i0_s2_dep_hit; + wire [0:`ITAG_SIZE_ENC-1] rv0_fx0_instr_i0_s2_itag; + wire rv0_fx0_instr_i0_s3_dep_hit; + wire [0:`ITAG_SIZE_ENC-1] rv0_fx0_instr_i0_s3_itag; + wire rv0_fx0_instr_i1_s1_dep_hit; + wire [0:`ITAG_SIZE_ENC-1] rv0_fx0_instr_i1_s1_itag; + wire rv0_fx0_instr_i1_s2_dep_hit; + wire [0:`ITAG_SIZE_ENC-1] rv0_fx0_instr_i1_s2_itag; + wire rv0_fx0_instr_i1_s3_dep_hit; + wire [0:`ITAG_SIZE_ENC-1] rv0_fx0_instr_i1_s3_itag; + wire [0:`THREADS-1] rv0_fx1_instr_i0_vld; + wire rv0_fx1_instr_i0_rte_fx1; + wire [0:31] rv0_fx1_instr_i0_instr; + wire [0:2] rv0_fx1_instr_i0_ucode; + wire [0:`ITAG_SIZE_ENC-1] rv0_fx1_instr_i0_itag; + wire rv0_fx1_instr_i0_t1_v; + wire [0:`GPR_POOL_ENC-1] rv0_fx1_instr_i0_t1_p; + wire rv0_fx1_instr_i0_t2_v; + wire [0:`GPR_POOL_ENC-1] rv0_fx1_instr_i0_t2_p; + wire rv0_fx1_instr_i0_t3_v; + wire [0:`GPR_POOL_ENC-1] rv0_fx1_instr_i0_t3_p; + wire rv0_fx1_instr_i0_s1_v; + wire [0:`GPR_POOL_ENC-1] rv0_fx1_instr_i0_s1_p; + wire [0:2] rv0_fx1_instr_i0_s1_t; + wire rv0_fx1_instr_i0_s2_v; + wire [0:`GPR_POOL_ENC-1] rv0_fx1_instr_i0_s2_p; + wire [0:2] rv0_fx1_instr_i0_s2_t; + wire rv0_fx1_instr_i0_s3_v; + wire [0:`GPR_POOL_ENC-1] rv0_fx1_instr_i0_s3_p; + wire [0:2] rv0_fx1_instr_i0_s3_t; + wire [0:3] rv0_fx1_instr_i0_ilat; + wire rv0_fx1_instr_i0_isStore; + wire [0:3] rv0_fx1_instr_i0_spare; + wire rv0_fx1_instr_i0_is_brick; + wire [0:2] rv0_fx1_instr_i0_brick; + wire [0:`THREADS-1] rv0_fx1_instr_i1_vld; + wire rv0_fx1_instr_i1_rte_fx1; + wire [0:31] rv0_fx1_instr_i1_instr; + wire [0:2] rv0_fx1_instr_i1_ucode; + wire [0:`ITAG_SIZE_ENC-1] rv0_fx1_instr_i1_itag; + wire rv0_fx1_instr_i1_t1_v; + wire [0:`GPR_POOL_ENC-1] rv0_fx1_instr_i1_t1_p; + wire rv0_fx1_instr_i1_t2_v; + wire [0:`GPR_POOL_ENC-1] rv0_fx1_instr_i1_t2_p; + wire rv0_fx1_instr_i1_t3_v; + wire [0:`GPR_POOL_ENC-1] rv0_fx1_instr_i1_t3_p; + wire rv0_fx1_instr_i1_s1_v; + wire [0:`GPR_POOL_ENC-1] rv0_fx1_instr_i1_s1_p; + wire [0:2] rv0_fx1_instr_i1_s1_t; + wire rv0_fx1_instr_i1_s2_v; + wire [0:`GPR_POOL_ENC-1] rv0_fx1_instr_i1_s2_p; + wire [0:2] rv0_fx1_instr_i1_s2_t; + wire rv0_fx1_instr_i1_s3_v; + wire [0:`GPR_POOL_ENC-1] rv0_fx1_instr_i1_s3_p; + wire [0:2] rv0_fx1_instr_i1_s3_t; + wire [0:3] rv0_fx1_instr_i1_ilat; + wire rv0_fx1_instr_i1_isStore; + wire [0:3] rv0_fx1_instr_i1_spare; + wire rv0_fx1_instr_i1_is_brick; + wire [0:2] rv0_fx1_instr_i1_brick; + wire rv0_fx1_instr_i0_s1_dep_hit; + wire [0:`ITAG_SIZE_ENC-1] rv0_fx1_instr_i0_s1_itag; + wire rv0_fx1_instr_i0_s2_dep_hit; + wire [0:`ITAG_SIZE_ENC-1] rv0_fx1_instr_i0_s2_itag; + wire rv0_fx1_instr_i0_s3_dep_hit; + wire [0:`ITAG_SIZE_ENC-1] rv0_fx1_instr_i0_s3_itag; + wire rv0_fx1_instr_i1_s1_dep_hit; + wire [0:`ITAG_SIZE_ENC-1] rv0_fx1_instr_i1_s1_itag; + wire rv0_fx1_instr_i1_s2_dep_hit; + wire [0:`ITAG_SIZE_ENC-1] rv0_fx1_instr_i1_s2_itag; + wire rv0_fx1_instr_i1_s3_dep_hit; + wire [0:`ITAG_SIZE_ENC-1] rv0_fx1_instr_i1_s3_itag; + wire [0:`THREADS-1] rv0_lq_instr_i0_vld; + wire rv0_lq_instr_i0_rte_lq; + wire [0:31] rv0_lq_instr_i0_instr; + wire [0:2] rv0_lq_instr_i0_ucode; + wire [0:`UCODE_ENTRIES_ENC-1] rv0_lq_instr_i0_ucode_cnt; + wire [0:`ITAG_SIZE_ENC-1] rv0_lq_instr_i0_itag; + wire rv0_lq_instr_i0_ord; + wire rv0_lq_instr_i0_cord; + wire rv0_lq_instr_i0_spec; + wire rv0_lq_instr_i0_t1_v; + wire [0:`GPR_POOL_ENC-1] rv0_lq_instr_i0_t1_p; + wire rv0_lq_instr_i0_t2_v; + wire [0:`GPR_POOL_ENC-1] rv0_lq_instr_i0_t2_p; + wire [0:2] rv0_lq_instr_i0_t2_t; + wire rv0_lq_instr_i0_t3_v; + wire [0:`GPR_POOL_ENC-1] rv0_lq_instr_i0_t3_p; + wire [0:2] rv0_lq_instr_i0_t3_t; + wire rv0_lq_instr_i0_s1_v; + wire [0:`GPR_POOL_ENC-1] rv0_lq_instr_i0_s1_p; + wire [0:2] rv0_lq_instr_i0_s1_t; + wire rv0_lq_instr_i0_s2_v; + wire [0:`GPR_POOL_ENC-1] rv0_lq_instr_i0_s2_p; + wire [0:2] rv0_lq_instr_i0_s2_t; + wire rv0_lq_instr_i0_isLoad; + wire [0:3] rv0_lq_instr_i0_spare; + wire rv0_lq_instr_i0_is_brick; + wire [0:2] rv0_lq_instr_i0_brick; + wire [0:`THREADS-1] rv0_lq_instr_i1_vld; + wire rv0_lq_instr_i1_rte_lq; + wire [0:31] rv0_lq_instr_i1_instr; + wire [0:2] rv0_lq_instr_i1_ucode; + wire [0:`UCODE_ENTRIES_ENC-1] rv0_lq_instr_i1_ucode_cnt; + wire [0:`ITAG_SIZE_ENC-1] rv0_lq_instr_i1_itag; + wire rv0_lq_instr_i1_ord; + wire rv0_lq_instr_i1_cord; + wire rv0_lq_instr_i1_spec; + wire rv0_lq_instr_i1_t1_v; + wire [0:`GPR_POOL_ENC-1] rv0_lq_instr_i1_t1_p; + wire rv0_lq_instr_i1_t2_v; + wire [0:`GPR_POOL_ENC-1] rv0_lq_instr_i1_t2_p; + wire [0:2] rv0_lq_instr_i1_t2_t; + wire rv0_lq_instr_i1_t3_v; + wire [0:`GPR_POOL_ENC-1] rv0_lq_instr_i1_t3_p; + wire [0:2] rv0_lq_instr_i1_t3_t; + wire rv0_lq_instr_i1_s1_v; + wire [0:`GPR_POOL_ENC-1] rv0_lq_instr_i1_s1_p; + wire [0:2] rv0_lq_instr_i1_s1_t; + wire rv0_lq_instr_i1_s2_v; + wire [0:`GPR_POOL_ENC-1] rv0_lq_instr_i1_s2_p; + wire [0:2] rv0_lq_instr_i1_s2_t; + wire rv0_lq_instr_i1_isLoad; + wire [0:3] rv0_lq_instr_i1_spare; + wire rv0_lq_instr_i1_is_brick; + wire [0:2] rv0_lq_instr_i1_brick; + wire rv0_lq_instr_i0_s1_dep_hit; + wire [0:`ITAG_SIZE_ENC-1] rv0_lq_instr_i0_s1_itag; + wire rv0_lq_instr_i0_s2_dep_hit; + wire [0:`ITAG_SIZE_ENC-1] rv0_lq_instr_i0_s2_itag; + wire rv0_lq_instr_i1_s1_dep_hit; + wire [0:`ITAG_SIZE_ENC-1] rv0_lq_instr_i1_s1_itag; + wire rv0_lq_instr_i1_s2_dep_hit; + wire [0:`ITAG_SIZE_ENC-1] rv0_lq_instr_i1_s2_itag; + wire [0:`THREADS-1] rv0_axu0_instr_i0_vld; + wire rv0_axu0_instr_i0_rte_axu0; + wire [0:31] rv0_axu0_instr_i0_instr; + wire [0:2] rv0_axu0_instr_i0_ucode; + wire [0:`ITAG_SIZE_ENC-1] rv0_axu0_instr_i0_itag; + wire rv0_axu0_instr_i0_ord; + wire rv0_axu0_instr_i0_cord; + wire rv0_axu0_instr_i0_t1_v; + wire [0:`GPR_POOL_ENC-1] rv0_axu0_instr_i0_t1_p; + wire [0:`GPR_POOL_ENC-1] rv0_axu0_instr_i0_t2_p; + wire [0:`GPR_POOL_ENC-1] rv0_axu0_instr_i0_t3_p; + wire rv0_axu0_instr_i0_s1_v; + wire [0:`GPR_POOL_ENC-1] rv0_axu0_instr_i0_s1_p; + wire rv0_axu0_instr_i0_s2_v; + wire [0:`GPR_POOL_ENC-1] rv0_axu0_instr_i0_s2_p; + wire rv0_axu0_instr_i0_s3_v; + wire [0:`GPR_POOL_ENC-1] rv0_axu0_instr_i0_s3_p; + wire rv0_axu0_instr_i0_isStore; + wire [0:3] rv0_axu0_instr_i0_spare; + wire [0:`THREADS-1] rv0_axu0_instr_i1_vld; + wire rv0_axu0_instr_i1_rte_axu0; + wire [0:31] rv0_axu0_instr_i1_instr; + wire [0:2] rv0_axu0_instr_i1_ucode; + wire [0:`ITAG_SIZE_ENC-1] rv0_axu0_instr_i1_itag; + wire rv0_axu0_instr_i1_ord; + wire rv0_axu0_instr_i1_cord; + wire rv0_axu0_instr_i1_t1_v; + wire [0:`GPR_POOL_ENC-1] rv0_axu0_instr_i1_t1_p; + wire [0:`GPR_POOL_ENC-1] rv0_axu0_instr_i1_t2_p; + wire [0:`GPR_POOL_ENC-1] rv0_axu0_instr_i1_t3_p; + wire rv0_axu0_instr_i1_s1_v; + wire [0:`GPR_POOL_ENC-1] rv0_axu0_instr_i1_s1_p; + wire rv0_axu0_instr_i1_s2_v; + wire [0:`GPR_POOL_ENC-1] rv0_axu0_instr_i1_s2_p; + wire rv0_axu0_instr_i1_s3_v; + wire [0:`GPR_POOL_ENC-1] rv0_axu0_instr_i1_s3_p; + wire rv0_axu0_instr_i1_isStore; + wire [0:3] rv0_axu0_instr_i1_spare; + wire rv0_axu0_instr_i0_s1_dep_hit; + wire [0:`ITAG_SIZE_ENC-1] rv0_axu0_instr_i0_s1_itag; + wire rv0_axu0_instr_i0_s2_dep_hit; + wire [0:`ITAG_SIZE_ENC-1] rv0_axu0_instr_i0_s2_itag; + wire rv0_axu0_instr_i0_s3_dep_hit; + wire [0:`ITAG_SIZE_ENC-1] rv0_axu0_instr_i0_s3_itag; + wire rv0_axu0_instr_i1_s1_dep_hit; + wire [0:`ITAG_SIZE_ENC-1] rv0_axu0_instr_i1_s1_itag; + wire rv0_axu0_instr_i1_s2_dep_hit; + wire [0:`ITAG_SIZE_ENC-1] rv0_axu0_instr_i1_s2_itag; + wire rv0_axu0_instr_i1_s3_dep_hit; + wire [0:`ITAG_SIZE_ENC-1] rv0_axu0_instr_i1_s3_itag; + + //------------------------------------------------------------------------------------------------------------ + // Itag busses and shadow + //------------------------------------------------------------------------------------------------------------ + + wire [0:`THREADS-1] fx0_rv_itag_vld; + wire fx0_rv_itag_abort; + wire [0:`ITAG_SIZE_ENC-1] fx0_rv_itag; + wire [0:`THREADS-1] fx0_rv_ext_itag_vld; + wire fx0_rv_ext_itag_abort; + wire [0:`ITAG_SIZE_ENC-1] fx0_rv_ext_itag; + + wire [0:`THREADS-1] fx1_rv_itag_vld; + wire fx1_rv_itag_abort; + wire [0:`ITAG_SIZE_ENC-1] fx1_rv_itag; + wire [0:`THREADS-1] fx1_rv_ext_itag_vld; + wire fx1_rv_ext_itag_abort; + wire [0:`ITAG_SIZE_ENC-1] fx1_rv_ext_itag; + + //------------------------------------------------------------------------------------------------------------ + // Bypass + //------------------------------------------------------------------------------------------------------------ + wire [0:`THREADS-1] rv_byp_fx0_vld; // FX0 Ports + wire [0:`ITAG_SIZE_ENC-1] rv_byp_fx0_itag; + wire [0:3] rv_byp_fx0_ilat; + wire rv_byp_fx0_ord; + wire rv_byp_fx0_t1_v; + wire [0:2] rv_byp_fx0_t1_t; + wire rv_byp_fx0_t2_v; + wire [0:2] rv_byp_fx0_t2_t; + wire rv_byp_fx0_t3_v; + wire [0:2] rv_byp_fx0_t3_t; + wire [0:2] rv_byp_fx0_s1_t; + wire [0:2] rv_byp_fx0_s2_t; + wire [0:2] rv_byp_fx0_s3_t; + wire [0:`THREADS-1] rv_byp_lq_vld; // LQ Ports + wire [0:`ITAG_SIZE_ENC-1] rv_byp_lq_itag; // LQ Ports + wire [0:`ITAG_SIZE_ENC-1] rv_byp_lq_ex0_s1_itag; + wire [0:`ITAG_SIZE_ENC-1] rv_byp_lq_ex0_s2_itag; + wire rv_byp_fx0_ex0_is_brick; + + wire rv_byp_lq_t1_v; + wire rv_byp_lq_t3_v; + wire [0:2] rv_byp_lq_t3_t; + wire rv_byp_lq_s1_v; + wire [0:`GPR_POOL_ENC-1] rv_byp_lq_s1_p; + wire [0:2] rv_byp_lq_s1_t; + wire rv_byp_lq_s2_v; + wire [0:`GPR_POOL_ENC-1] rv_byp_lq_s2_p; + wire [0:2] rv_byp_lq_s2_t; + wire [0:`THREADS-1] rv_byp_fx1_vld; // FX0 Ports + wire [0:`ITAG_SIZE_ENC-1] rv_byp_fx1_itag; + wire [0:3] rv_byp_fx1_ilat; + wire rv_byp_fx1_t1_v; + wire rv_byp_fx1_t2_v; + wire rv_byp_fx1_t3_v; + wire [0:2] rv_byp_fx1_s1_t; + wire [0:2] rv_byp_fx1_s2_t; + wire [0:2] rv_byp_fx1_s3_t; + + wire [0:`ITAG_SIZE_ENC-1] rv_byp_fx0_s1_itag; + wire [0:`ITAG_SIZE_ENC-1] rv_byp_fx0_s2_itag; + wire [0:`ITAG_SIZE_ENC-1] rv_byp_fx0_s3_itag; + + wire [0:`ITAG_SIZE_ENC-1] rv_byp_fx1_s1_itag; + wire [0:`ITAG_SIZE_ENC-1] rv_byp_fx1_s2_itag; + wire [0:`ITAG_SIZE_ENC-1] rv_byp_fx1_s3_itag; + wire rv_byp_fx1_ex0_isStore; + + wire [0:`THREADS-1] rv_byp_fx0_ilat0_vld; + wire [0:`THREADS-1] rv_byp_fx0_ilat1_vld; + wire [0:`THREADS-1] rv_byp_fx1_ilat0_vld; + wire [0:`THREADS-1] rv_byp_fx1_ilat1_vld; + + wire [0:`THREADS-1] rv1_fx0_ilat0_vld; + wire [0:`ITAG_SIZE_ENC-1] rv1_fx0_ilat0_itag; + wire [0:`THREADS-1] rv1_fx1_ilat0_vld; + wire [0:`ITAG_SIZE_ENC-1] rv1_fx1_ilat0_itag; + + wire [0:`THREADS-1] fx0_release_ord_hold; + wire [0:`THREADS-1] fx0_rv_ord_tid; + + wire [0:`THREADS-1] lq_rv_ext_itag0_vld; + wire lq_rv_ext_itag0_abort; + wire [0:`ITAG_SIZE_ENC-1] lq_rv_ext_itag0 ; + wire [0:`THREADS-1] lq_rv_ext_itag1_vld; + wire lq_rv_ext_itag1_abort; + wire [0:`ITAG_SIZE_ENC-1] lq_rv_ext_itag1 ; + wire [0:`THREADS-1] lq_rv_ext_itag2_vld; + wire [0:`ITAG_SIZE_ENC-1] lq_rv_ext_itag2 ; + + wire [0:`THREADS-1] axu0_rv_ext_itag_vld; + wire axu0_rv_ext_itag_abort; + wire [0:`ITAG_SIZE_ENC-1] axu0_rv_ext_itag; + wire [0:`THREADS-1] axu1_rv_ext_itag_vld; + wire axu1_rv_ext_itag_abort; + wire [0:`ITAG_SIZE_ENC-1] axu1_rv_ext_itag; + + wire [64-`GPR_WIDTH:77] w_data_in_1; + wire [64-`GPR_WIDTH:77] w_data_in_2; + wire [64-`GPR_WIDTH:77] w_data_in_3; + wire [64-`GPR_WIDTH:77] w_data_in_4; + (* analysis_not_referenced="<72:77>true" *) + wire [64-`GPR_WIDTH:77] r_data_out_1; + (* analysis_not_referenced="<72:77>true" *) + wire [64-`GPR_WIDTH:77] r_data_out_2; + + wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] rv_lq_gpr_s1_p; + wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] rv_lq_gpr_s2_p; + + wire lqrf_si; + (* analysis_not_referenced="true" *) + wire lqrf_so; + + wire [0:8*`THREADS-1] fx0_rvs_perf_bus; + wire [0:31] fx0_rvs_dbg_bus; + wire [0:8*`THREADS-1] fx1_rvs_perf_bus; + wire [0:31] fx1_rvs_dbg_bus; + wire [0:8*`THREADS-1] lq_rvs_perf_bus; + wire [0:31] lq_rvs_dbg_bus; + wire [0:8*`THREADS-1] axu0_rvs_perf_bus; + wire [0:31] axu0_rvs_dbg_bus; + + //todo review pervaice sigs. + wire func_sl_thold_1; + (* analysis_not_referenced="true" *) + wire fce_1; + wire sg_1; + wire clkoff_dc_b; + wire act_dis; + (* analysis_not_referenced="<1:9>true" *) + wire [0:9] delay_lclkr_dc; + (* analysis_not_referenced="<1:9>true" *) + wire [0:9] mpw1_dc_b; + wire mpw2_dc_b; + wire gptr_scan_in; + (* analysis_not_referenced="true" *) + wire gptr_scan_out; + + wire chip_b_sl_2_thold_0_b; + wire force_t; + wire d_mode; + (* analysis_not_referenced="true" *) + wire unused; + + // Scan Chain + parameter rv_deps_offset = 0; + parameter rv_fx0_rvs_offset = rv_deps_offset +1; + parameter rv_fx1_rvs_offset = rv_fx0_rvs_offset +1; + parameter rv_lq_rvs_offset = rv_fx1_rvs_offset +1; + parameter rv_axu0_rvs_offset = rv_lq_rvs_offset +1; + parameter rv_rf_byp_offset = rv_axu0_rvs_offset +1; + parameter perv_func_offset = rv_rf_byp_offset +1; + + + + parameter scan_right = perv_func_offset +1; + wire [0:scan_right-1] siv; + wire [0:scan_right-1] sov; + + //!! Bugspray Include: rv; + + wire vdd; + wire gnd; + assign vdd = 1'b1; + assign gnd = 1'b0; + + assign unused = axu1_rv_hold_all; + + //--------------------------------------------------------------------------------------------------------------- + + assign chip_b_sl_2_thold_0_b = (~func_sl_thold_1); + assign force_t = 1'b0; + assign d_mode = 1'b0; + + assign iu_rv_iu6_t0_i0_branch = {iu_rv_iu6_t0_i0_bta, + iu_rv_iu6_t0_i0_bta_val, + iu_rv_iu6_t0_i0_br_pred, + iu_rv_iu6_t0_i0_fusion, + iu_rv_iu6_t0_i0_ls_ptr, + iu_rv_iu6_t0_i0_gshare, + iu_rv_iu6_t0_i0_bh_update}; + assign iu_rv_iu6_t0_i1_branch = {iu_rv_iu6_t0_i1_bta, + iu_rv_iu6_t0_i1_bta_val, + iu_rv_iu6_t0_i1_br_pred, + iu_rv_iu6_t0_i1_fusion, + iu_rv_iu6_t0_i1_ls_ptr, + iu_rv_iu6_t0_i1_gshare, + iu_rv_iu6_t0_i1_bh_update}; + assign cp_next_itag[0:`ITAG_SIZE_ENC-1] = cp_t0_next_itag; + +`ifndef THREADS1 + assign iu_rv_iu6_t1_i0_branch = {iu_rv_iu6_t1_i0_bta, + iu_rv_iu6_t1_i0_bta_val, + iu_rv_iu6_t1_i0_br_pred, + iu_rv_iu6_t1_i0_fusion, + iu_rv_iu6_t1_i0_ls_ptr, + iu_rv_iu6_t1_i0_gshare, + iu_rv_iu6_t1_i0_bh_update}; + assign iu_rv_iu6_t1_i1_branch = {iu_rv_iu6_t1_i1_bta, + iu_rv_iu6_t1_i1_bta_val, + iu_rv_iu6_t1_i1_br_pred, + iu_rv_iu6_t1_i1_fusion, + iu_rv_iu6_t1_i1_ls_ptr, + iu_rv_iu6_t1_i1_gshare, + iu_rv_iu6_t1_i1_bh_update}; + assign cp_next_itag[`ITAG_SIZE_ENC:`THREADS*`ITAG_SIZE_ENC-1] = cp_t1_next_itag; + +`endif // `ifndef THREADS1 + + assign rv_fx0_ex0_pred_bta = rv_fx0_ex0_branch[0:`EFF_IFAR_WIDTH - 1]; + assign rv_fx0_ex0_bta_val = rv_fx0_ex0_branch[20]; + assign rv_fx0_ex0_br_pred = rv_fx0_ex0_branch[21]; + assign rv_fx0_ex0_fusion = rv_fx0_ex0_branch[22:22 + `EFF_IFAR_WIDTH - 1]; + assign rv_fx0_ex0_ls_ptr = rv_fx0_ex0_branch[42:44]; + assign rv_fx0_ex0_gshare = rv_fx0_ex0_branch[45:62]; + assign rv_fx0_ex0_bh_update = rv_fx0_ex0_branch[63]; + + //------------------------------------------------------------------------------------------------------------ + // Scorecards + //------------------------------------------------------------------------------------------------------------ + + + rv_deps + rv_deps0( + .iu_rv_iu6_t0_i0_vld(iu_rv_iu6_t0_i0_vld), + .iu_rv_iu6_t0_i0_rte_lq(iu_rv_iu6_t0_i0_rte_lq), + .iu_rv_iu6_t0_i0_rte_sq(iu_rv_iu6_t0_i0_rte_sq), + .iu_rv_iu6_t0_i0_rte_fx0(iu_rv_iu6_t0_i0_rte_fx0), + .iu_rv_iu6_t0_i0_rte_fx1(iu_rv_iu6_t0_i0_rte_fx1), + .iu_rv_iu6_t0_i0_rte_axu0(iu_rv_iu6_t0_i0_rte_axu0), + .iu_rv_iu6_t0_i0_rte_axu1(iu_rv_iu6_t0_i0_rte_axu1), + .iu_rv_iu6_t0_i0_act(iu_rv_iu6_t0_i0_act), + .iu_rv_iu6_t0_i0_instr(iu_rv_iu6_t0_i0_instr), + .iu_rv_iu6_t0_i0_ifar(iu_rv_iu6_t0_i0_ifar), + .iu_rv_iu6_t0_i0_ucode(iu_rv_iu6_t0_i0_ucode), + .iu_rv_iu6_t0_i0_2ucode(iu_rv_iu6_t0_i0_2ucode), + .iu_rv_iu6_t0_i0_ucode_cnt(iu_rv_iu6_t0_i0_ucode_cnt), + .iu_rv_iu6_t0_i0_itag(iu_rv_iu6_t0_i0_itag), + .iu_rv_iu6_t0_i0_ord(iu_rv_iu6_t0_i0_ord), + .iu_rv_iu6_t0_i0_cord(iu_rv_iu6_t0_i0_cord), + .iu_rv_iu6_t0_i0_spec(iu_rv_iu6_t0_i0_spec), + .iu_rv_iu6_t0_i0_t1_v(iu_rv_iu6_t0_i0_t1_v), + .iu_rv_iu6_t0_i0_t1_p(iu_rv_iu6_t0_i0_t1_p), + .iu_rv_iu6_t0_i0_t1_t(iu_rv_iu6_t0_i0_t1_t), + .iu_rv_iu6_t0_i0_t2_v(iu_rv_iu6_t0_i0_t2_v), + .iu_rv_iu6_t0_i0_t2_p(iu_rv_iu6_t0_i0_t2_p), + .iu_rv_iu6_t0_i0_t2_t(iu_rv_iu6_t0_i0_t2_t), + .iu_rv_iu6_t0_i0_t3_v(iu_rv_iu6_t0_i0_t3_v), + .iu_rv_iu6_t0_i0_t3_p(iu_rv_iu6_t0_i0_t3_p), + .iu_rv_iu6_t0_i0_t3_t(iu_rv_iu6_t0_i0_t3_t), + .iu_rv_iu6_t0_i0_s1_v(iu_rv_iu6_t0_i0_s1_v), + .iu_rv_iu6_t0_i0_s1_p(iu_rv_iu6_t0_i0_s1_p), + .iu_rv_iu6_t0_i0_s1_t(iu_rv_iu6_t0_i0_s1_t), + .iu_rv_iu6_t0_i0_s2_v(iu_rv_iu6_t0_i0_s2_v), + .iu_rv_iu6_t0_i0_s2_p(iu_rv_iu6_t0_i0_s2_p), + .iu_rv_iu6_t0_i0_s2_t(iu_rv_iu6_t0_i0_s2_t), + .iu_rv_iu6_t0_i0_s3_v(iu_rv_iu6_t0_i0_s3_v), + .iu_rv_iu6_t0_i0_s3_p(iu_rv_iu6_t0_i0_s3_p), + .iu_rv_iu6_t0_i0_s3_t(iu_rv_iu6_t0_i0_s3_t), + .iu_rv_iu6_t0_i0_ilat(iu_rv_iu6_t0_i0_ilat), + .iu_rv_iu6_t0_i0_isLoad(iu_rv_iu6_t0_i0_isLoad), + .iu_rv_iu6_t0_i0_isStore(iu_rv_iu6_t0_i0_isStore), + .iu_rv_iu6_t0_i0_branch(iu_rv_iu6_t0_i0_branch), + .iu_rv_iu6_t0_i0_s1_itag(iu_rv_iu6_t0_i0_s1_itag), + .iu_rv_iu6_t0_i0_s2_itag(iu_rv_iu6_t0_i0_s2_itag), + .iu_rv_iu6_t0_i0_s3_itag(iu_rv_iu6_t0_i0_s3_itag), + .iu_rv_iu6_t0_i1_vld(iu_rv_iu6_t0_i1_vld), + .iu_rv_iu6_t0_i1_rte_lq(iu_rv_iu6_t0_i1_rte_lq), + .iu_rv_iu6_t0_i1_rte_sq(iu_rv_iu6_t0_i1_rte_sq), + .iu_rv_iu6_t0_i1_rte_fx0(iu_rv_iu6_t0_i1_rte_fx0), + .iu_rv_iu6_t0_i1_rte_fx1(iu_rv_iu6_t0_i1_rte_fx1), + .iu_rv_iu6_t0_i1_rte_axu0(iu_rv_iu6_t0_i1_rte_axu0), + .iu_rv_iu6_t0_i1_rte_axu1(iu_rv_iu6_t0_i1_rte_axu1), + .iu_rv_iu6_t0_i1_act(iu_rv_iu6_t0_i1_act), + .iu_rv_iu6_t0_i1_instr(iu_rv_iu6_t0_i1_instr), + .iu_rv_iu6_t0_i1_ifar(iu_rv_iu6_t0_i1_ifar), + .iu_rv_iu6_t0_i1_ucode(iu_rv_iu6_t0_i1_ucode), + .iu_rv_iu6_t0_i1_ucode_cnt(iu_rv_iu6_t0_i1_ucode_cnt), + .iu_rv_iu6_t0_i1_itag(iu_rv_iu6_t0_i1_itag), + .iu_rv_iu6_t0_i1_ord(iu_rv_iu6_t0_i1_ord), + .iu_rv_iu6_t0_i1_cord(iu_rv_iu6_t0_i1_cord), + .iu_rv_iu6_t0_i1_spec(iu_rv_iu6_t0_i1_spec), + .iu_rv_iu6_t0_i1_t1_v(iu_rv_iu6_t0_i1_t1_v), + .iu_rv_iu6_t0_i1_t1_p(iu_rv_iu6_t0_i1_t1_p), + .iu_rv_iu6_t0_i1_t1_t(iu_rv_iu6_t0_i1_t1_t), + .iu_rv_iu6_t0_i1_t2_v(iu_rv_iu6_t0_i1_t2_v), + .iu_rv_iu6_t0_i1_t2_p(iu_rv_iu6_t0_i1_t2_p), + .iu_rv_iu6_t0_i1_t2_t(iu_rv_iu6_t0_i1_t2_t), + .iu_rv_iu6_t0_i1_t3_v(iu_rv_iu6_t0_i1_t3_v), + .iu_rv_iu6_t0_i1_t3_p(iu_rv_iu6_t0_i1_t3_p), + .iu_rv_iu6_t0_i1_t3_t(iu_rv_iu6_t0_i1_t3_t), + .iu_rv_iu6_t0_i1_s1_v(iu_rv_iu6_t0_i1_s1_v), + .iu_rv_iu6_t0_i1_s1_p(iu_rv_iu6_t0_i1_s1_p), + .iu_rv_iu6_t0_i1_s1_t(iu_rv_iu6_t0_i1_s1_t), + .iu_rv_iu6_t0_i1_s2_v(iu_rv_iu6_t0_i1_s2_v), + .iu_rv_iu6_t0_i1_s2_p(iu_rv_iu6_t0_i1_s2_p), + .iu_rv_iu6_t0_i1_s2_t(iu_rv_iu6_t0_i1_s2_t), + .iu_rv_iu6_t0_i1_s3_v(iu_rv_iu6_t0_i1_s3_v), + .iu_rv_iu6_t0_i1_s3_p(iu_rv_iu6_t0_i1_s3_p), + .iu_rv_iu6_t0_i1_s3_t(iu_rv_iu6_t0_i1_s3_t), + .iu_rv_iu6_t0_i1_ilat(iu_rv_iu6_t0_i1_ilat), + .iu_rv_iu6_t0_i1_isLoad(iu_rv_iu6_t0_i1_isLoad), + .iu_rv_iu6_t0_i1_isStore(iu_rv_iu6_t0_i1_isStore), + .iu_rv_iu6_t0_i1_branch(iu_rv_iu6_t0_i1_branch), + .iu_rv_iu6_t0_i1_s1_itag(iu_rv_iu6_t0_i1_s1_itag), + .iu_rv_iu6_t0_i1_s2_itag(iu_rv_iu6_t0_i1_s2_itag), + .iu_rv_iu6_t0_i1_s3_itag(iu_rv_iu6_t0_i1_s3_itag), + .iu_rv_iu6_t0_i1_s1_dep_hit(iu_rv_iu6_t0_i1_s1_dep_hit), + .iu_rv_iu6_t0_i1_s2_dep_hit(iu_rv_iu6_t0_i1_s2_dep_hit), + .iu_rv_iu6_t0_i1_s3_dep_hit(iu_rv_iu6_t0_i1_s3_dep_hit), +`ifndef THREADS1 + .iu_rv_iu6_t1_i0_vld(iu_rv_iu6_t1_i0_vld), + .iu_rv_iu6_t1_i0_rte_lq(iu_rv_iu6_t1_i0_rte_lq), + .iu_rv_iu6_t1_i0_rte_sq(iu_rv_iu6_t1_i0_rte_sq), + .iu_rv_iu6_t1_i0_rte_fx0(iu_rv_iu6_t1_i0_rte_fx0), + .iu_rv_iu6_t1_i0_rte_fx1(iu_rv_iu6_t1_i0_rte_fx1), + .iu_rv_iu6_t1_i0_rte_axu0(iu_rv_iu6_t1_i0_rte_axu0), + .iu_rv_iu6_t1_i0_rte_axu1(iu_rv_iu6_t1_i0_rte_axu1), + .iu_rv_iu6_t1_i0_act(iu_rv_iu6_t1_i0_act), + .iu_rv_iu6_t1_i0_instr(iu_rv_iu6_t1_i0_instr), + .iu_rv_iu6_t1_i0_ifar(iu_rv_iu6_t1_i0_ifar), + .iu_rv_iu6_t1_i0_ucode(iu_rv_iu6_t1_i0_ucode), + .iu_rv_iu6_t1_i0_2ucode(iu_rv_iu6_t1_i0_2ucode), + .iu_rv_iu6_t1_i0_ucode_cnt(iu_rv_iu6_t1_i0_ucode_cnt), + .iu_rv_iu6_t1_i0_itag(iu_rv_iu6_t1_i0_itag), + .iu_rv_iu6_t1_i0_ord(iu_rv_iu6_t1_i0_ord), + .iu_rv_iu6_t1_i0_cord(iu_rv_iu6_t1_i0_cord), + .iu_rv_iu6_t1_i0_spec(iu_rv_iu6_t1_i0_spec), + .iu_rv_iu6_t1_i0_t1_v(iu_rv_iu6_t1_i0_t1_v), + .iu_rv_iu6_t1_i0_t1_p(iu_rv_iu6_t1_i0_t1_p), + .iu_rv_iu6_t1_i0_t1_t(iu_rv_iu6_t1_i0_t1_t), + .iu_rv_iu6_t1_i0_t2_v(iu_rv_iu6_t1_i0_t2_v), + .iu_rv_iu6_t1_i0_t2_p(iu_rv_iu6_t1_i0_t2_p), + .iu_rv_iu6_t1_i0_t2_t(iu_rv_iu6_t1_i0_t2_t), + .iu_rv_iu6_t1_i0_t3_v(iu_rv_iu6_t1_i0_t3_v), + .iu_rv_iu6_t1_i0_t3_p(iu_rv_iu6_t1_i0_t3_p), + .iu_rv_iu6_t1_i0_t3_t(iu_rv_iu6_t1_i0_t3_t), + .iu_rv_iu6_t1_i0_s1_v(iu_rv_iu6_t1_i0_s1_v), + .iu_rv_iu6_t1_i0_s1_p(iu_rv_iu6_t1_i0_s1_p), + .iu_rv_iu6_t1_i0_s1_t(iu_rv_iu6_t1_i0_s1_t), + .iu_rv_iu6_t1_i0_s2_v(iu_rv_iu6_t1_i0_s2_v), + .iu_rv_iu6_t1_i0_s2_p(iu_rv_iu6_t1_i0_s2_p), + .iu_rv_iu6_t1_i0_s2_t(iu_rv_iu6_t1_i0_s2_t), + .iu_rv_iu6_t1_i0_s3_v(iu_rv_iu6_t1_i0_s3_v), + .iu_rv_iu6_t1_i0_s3_p(iu_rv_iu6_t1_i0_s3_p), + .iu_rv_iu6_t1_i0_s3_t(iu_rv_iu6_t1_i0_s3_t), + .iu_rv_iu6_t1_i0_ilat(iu_rv_iu6_t1_i0_ilat), + .iu_rv_iu6_t1_i0_isLoad(iu_rv_iu6_t1_i0_isLoad), + .iu_rv_iu6_t1_i0_isStore(iu_rv_iu6_t1_i0_isStore), + .iu_rv_iu6_t1_i0_branch(iu_rv_iu6_t1_i0_branch), + .iu_rv_iu6_t1_i0_s1_itag(iu_rv_iu6_t1_i0_s1_itag), + .iu_rv_iu6_t1_i0_s2_itag(iu_rv_iu6_t1_i0_s2_itag), + .iu_rv_iu6_t1_i0_s3_itag(iu_rv_iu6_t1_i0_s3_itag), + .iu_rv_iu6_t1_i1_vld(iu_rv_iu6_t1_i1_vld), + .iu_rv_iu6_t1_i1_rte_lq(iu_rv_iu6_t1_i1_rte_lq), + .iu_rv_iu6_t1_i1_rte_sq(iu_rv_iu6_t1_i1_rte_sq), + .iu_rv_iu6_t1_i1_rte_fx0(iu_rv_iu6_t1_i1_rte_fx0), + .iu_rv_iu6_t1_i1_rte_fx1(iu_rv_iu6_t1_i1_rte_fx1), + .iu_rv_iu6_t1_i1_rte_axu0(iu_rv_iu6_t1_i1_rte_axu0), + .iu_rv_iu6_t1_i1_rte_axu1(iu_rv_iu6_t1_i1_rte_axu1), + .iu_rv_iu6_t1_i1_act(iu_rv_iu6_t1_i1_act), + .iu_rv_iu6_t1_i1_instr(iu_rv_iu6_t1_i1_instr), + .iu_rv_iu6_t1_i1_ifar(iu_rv_iu6_t1_i1_ifar), + .iu_rv_iu6_t1_i1_ucode(iu_rv_iu6_t1_i1_ucode), + .iu_rv_iu6_t1_i1_ucode_cnt(iu_rv_iu6_t1_i1_ucode_cnt), + .iu_rv_iu6_t1_i1_itag(iu_rv_iu6_t1_i1_itag), + .iu_rv_iu6_t1_i1_ord(iu_rv_iu6_t1_i1_ord), + .iu_rv_iu6_t1_i1_cord(iu_rv_iu6_t1_i1_cord), + .iu_rv_iu6_t1_i1_spec(iu_rv_iu6_t1_i1_spec), + .iu_rv_iu6_t1_i1_t1_v(iu_rv_iu6_t1_i1_t1_v), + .iu_rv_iu6_t1_i1_t1_p(iu_rv_iu6_t1_i1_t1_p), + .iu_rv_iu6_t1_i1_t1_t(iu_rv_iu6_t1_i1_t1_t), + .iu_rv_iu6_t1_i1_t2_v(iu_rv_iu6_t1_i1_t2_v), + .iu_rv_iu6_t1_i1_t2_p(iu_rv_iu6_t1_i1_t2_p), + .iu_rv_iu6_t1_i1_t2_t(iu_rv_iu6_t1_i1_t2_t), + .iu_rv_iu6_t1_i1_t3_v(iu_rv_iu6_t1_i1_t3_v), + .iu_rv_iu6_t1_i1_t3_p(iu_rv_iu6_t1_i1_t3_p), + .iu_rv_iu6_t1_i1_t3_t(iu_rv_iu6_t1_i1_t3_t), + .iu_rv_iu6_t1_i1_s1_v(iu_rv_iu6_t1_i1_s1_v), + .iu_rv_iu6_t1_i1_s1_p(iu_rv_iu6_t1_i1_s1_p), + .iu_rv_iu6_t1_i1_s1_t(iu_rv_iu6_t1_i1_s1_t), + .iu_rv_iu6_t1_i1_s2_v(iu_rv_iu6_t1_i1_s2_v), + .iu_rv_iu6_t1_i1_s2_p(iu_rv_iu6_t1_i1_s2_p), + .iu_rv_iu6_t1_i1_s2_t(iu_rv_iu6_t1_i1_s2_t), + .iu_rv_iu6_t1_i1_s3_v(iu_rv_iu6_t1_i1_s3_v), + .iu_rv_iu6_t1_i1_s3_p(iu_rv_iu6_t1_i1_s3_p), + .iu_rv_iu6_t1_i1_s3_t(iu_rv_iu6_t1_i1_s3_t), + .iu_rv_iu6_t1_i1_ilat(iu_rv_iu6_t1_i1_ilat), + .iu_rv_iu6_t1_i1_isLoad(iu_rv_iu6_t1_i1_isLoad), + .iu_rv_iu6_t1_i1_isStore(iu_rv_iu6_t1_i1_isStore), + .iu_rv_iu6_t1_i1_branch(iu_rv_iu6_t1_i1_branch), + .iu_rv_iu6_t1_i1_s1_itag(iu_rv_iu6_t1_i1_s1_itag), + .iu_rv_iu6_t1_i1_s2_itag(iu_rv_iu6_t1_i1_s2_itag), + .iu_rv_iu6_t1_i1_s3_itag(iu_rv_iu6_t1_i1_s3_itag), + .iu_rv_iu6_t1_i1_s1_dep_hit(iu_rv_iu6_t1_i1_s1_dep_hit), + .iu_rv_iu6_t1_i1_s2_dep_hit(iu_rv_iu6_t1_i1_s2_dep_hit), + .iu_rv_iu6_t1_i1_s3_dep_hit(iu_rv_iu6_t1_i1_s3_dep_hit), +`endif + .cp_flush(cp_flush), + .fx0_rv_itag_vld(fx0_rv_itag_vld), + .fx0_rv_itag(fx0_rv_itag), + .fx1_rv_itag_vld(fx1_rv_itag_vld), + .fx1_rv_itag(fx1_rv_itag), + .lq_rv_itag0_vld(lq_rv_itag0_vld), + .lq_rv_itag0(lq_rv_itag0), + .lq_rv_itag1_vld(lq_rv_itag1_vld), + .lq_rv_itag1(lq_rv_itag1), + .lq_rv_itag2_vld(lq_rv_itag2_vld), + .lq_rv_itag2(lq_rv_itag2), + .axu0_rv_itag_vld(axu0_rv_itag_vld), + .axu0_rv_itag(axu0_rv_itag), + .axu1_rv_itag_vld(axu1_rv_itag_vld), + .axu1_rv_itag(axu1_rv_itag), + + .fx0_rv_itag_abort(fx0_rv_itag_abort), + .fx1_rv_itag_abort(fx1_rv_itag_abort), + .lq_rv_itag0_abort(lq_rv_itag0_abort), + .lq_rv_itag1_abort(lq_rv_itag1_abort), + .axu0_rv_itag_abort(axu0_rv_itag_abort), + .axu1_rv_itag_abort(axu1_rv_itag_abort), + + .rv0_fx0_instr_i0_vld(rv0_fx0_instr_i0_vld), + .rv0_fx0_instr_i0_rte_fx0(rv0_fx0_instr_i0_rte_fx0), + .rv0_fx0_instr_i0_instr(rv0_fx0_instr_i0_instr), + .rv0_fx0_instr_i0_ifar(rv0_fx0_instr_i0_ifar), + .rv0_fx0_instr_i0_ucode(rv0_fx0_instr_i0_ucode), + .rv0_fx0_instr_i0_ucode_cnt(rv0_fx0_instr_i0_ucode_cnt), + .rv0_fx0_instr_i0_itag(rv0_fx0_instr_i0_itag), + .rv0_fx0_instr_i0_ord(rv0_fx0_instr_i0_ord), + .rv0_fx0_instr_i0_cord(rv0_fx0_instr_i0_cord), + .rv0_fx0_instr_i0_t1_v(rv0_fx0_instr_i0_t1_v), + .rv0_fx0_instr_i0_t1_p(rv0_fx0_instr_i0_t1_p), + .rv0_fx0_instr_i0_t1_t(rv0_fx0_instr_i0_t1_t), + .rv0_fx0_instr_i0_t2_v(rv0_fx0_instr_i0_t2_v), + .rv0_fx0_instr_i0_t2_p(rv0_fx0_instr_i0_t2_p), + .rv0_fx0_instr_i0_t2_t(rv0_fx0_instr_i0_t2_t), + .rv0_fx0_instr_i0_t3_v(rv0_fx0_instr_i0_t3_v), + .rv0_fx0_instr_i0_t3_p(rv0_fx0_instr_i0_t3_p), + .rv0_fx0_instr_i0_t3_t(rv0_fx0_instr_i0_t3_t), + .rv0_fx0_instr_i0_s1_v(rv0_fx0_instr_i0_s1_v), + .rv0_fx0_instr_i0_s1_p(rv0_fx0_instr_i0_s1_p), + .rv0_fx0_instr_i0_s1_t(rv0_fx0_instr_i0_s1_t), + .rv0_fx0_instr_i0_s2_v(rv0_fx0_instr_i0_s2_v), + .rv0_fx0_instr_i0_s2_p(rv0_fx0_instr_i0_s2_p), + .rv0_fx0_instr_i0_s2_t(rv0_fx0_instr_i0_s2_t), + .rv0_fx0_instr_i0_s3_v(rv0_fx0_instr_i0_s3_v), + .rv0_fx0_instr_i0_s3_p(rv0_fx0_instr_i0_s3_p), + .rv0_fx0_instr_i0_s3_t(rv0_fx0_instr_i0_s3_t), + .rv0_fx0_instr_i0_ilat(rv0_fx0_instr_i0_ilat), + .rv0_fx0_instr_i0_branch(rv0_fx0_instr_i0_branch), + .rv0_fx0_instr_i0_spare(rv0_fx0_instr_i0_spare), + .rv0_fx0_instr_i0_is_brick(rv0_fx0_instr_i0_is_brick), + .rv0_fx0_instr_i0_brick(rv0_fx0_instr_i0_brick), + .rv0_fx0_instr_i1_vld(rv0_fx0_instr_i1_vld), + .rv0_fx0_instr_i1_rte_fx0(rv0_fx0_instr_i1_rte_fx0), + .rv0_fx0_instr_i1_instr(rv0_fx0_instr_i1_instr), + .rv0_fx0_instr_i1_ifar(rv0_fx0_instr_i1_ifar), + .rv0_fx0_instr_i1_ucode(rv0_fx0_instr_i1_ucode), + .rv0_fx0_instr_i1_ucode_cnt(rv0_fx0_instr_i1_ucode_cnt), + .rv0_fx0_instr_i1_itag(rv0_fx0_instr_i1_itag), + .rv0_fx0_instr_i1_ord(rv0_fx0_instr_i1_ord), + .rv0_fx0_instr_i1_cord(rv0_fx0_instr_i1_cord), + .rv0_fx0_instr_i1_t1_v(rv0_fx0_instr_i1_t1_v), + .rv0_fx0_instr_i1_t1_p(rv0_fx0_instr_i1_t1_p), + .rv0_fx0_instr_i1_t1_t(rv0_fx0_instr_i1_t1_t), + .rv0_fx0_instr_i1_t2_v(rv0_fx0_instr_i1_t2_v), + .rv0_fx0_instr_i1_t2_p(rv0_fx0_instr_i1_t2_p), + .rv0_fx0_instr_i1_t2_t(rv0_fx0_instr_i1_t2_t), + .rv0_fx0_instr_i1_t3_v(rv0_fx0_instr_i1_t3_v), + .rv0_fx0_instr_i1_t3_p(rv0_fx0_instr_i1_t3_p), + .rv0_fx0_instr_i1_t3_t(rv0_fx0_instr_i1_t3_t), + .rv0_fx0_instr_i1_s1_v(rv0_fx0_instr_i1_s1_v), + .rv0_fx0_instr_i1_s1_p(rv0_fx0_instr_i1_s1_p), + .rv0_fx0_instr_i1_s1_t(rv0_fx0_instr_i1_s1_t), + .rv0_fx0_instr_i1_s2_v(rv0_fx0_instr_i1_s2_v), + .rv0_fx0_instr_i1_s2_p(rv0_fx0_instr_i1_s2_p), + .rv0_fx0_instr_i1_s2_t(rv0_fx0_instr_i1_s2_t), + .rv0_fx0_instr_i1_s3_v(rv0_fx0_instr_i1_s3_v), + .rv0_fx0_instr_i1_s3_p(rv0_fx0_instr_i1_s3_p), + .rv0_fx0_instr_i1_s3_t(rv0_fx0_instr_i1_s3_t), + .rv0_fx0_instr_i1_ilat(rv0_fx0_instr_i1_ilat), + .rv0_fx0_instr_i1_branch(rv0_fx0_instr_i1_branch), + .rv0_fx0_instr_i1_spare(rv0_fx0_instr_i1_spare), + .rv0_fx0_instr_i1_is_brick(rv0_fx0_instr_i1_is_brick), + .rv0_fx0_instr_i1_brick(rv0_fx0_instr_i1_brick), + .rv0_fx0_instr_i0_s1_dep_hit(rv0_fx0_instr_i0_s1_dep_hit), + .rv0_fx0_instr_i0_s1_itag(rv0_fx0_instr_i0_s1_itag), + .rv0_fx0_instr_i0_s2_dep_hit(rv0_fx0_instr_i0_s2_dep_hit), + .rv0_fx0_instr_i0_s2_itag(rv0_fx0_instr_i0_s2_itag), + .rv0_fx0_instr_i0_s3_dep_hit(rv0_fx0_instr_i0_s3_dep_hit), + .rv0_fx0_instr_i0_s3_itag(rv0_fx0_instr_i0_s3_itag), + .rv0_fx0_instr_i1_s1_dep_hit(rv0_fx0_instr_i1_s1_dep_hit), + .rv0_fx0_instr_i1_s1_itag(rv0_fx0_instr_i1_s1_itag), + .rv0_fx0_instr_i1_s2_dep_hit(rv0_fx0_instr_i1_s2_dep_hit), + .rv0_fx0_instr_i1_s2_itag(rv0_fx0_instr_i1_s2_itag), + .rv0_fx0_instr_i1_s3_dep_hit(rv0_fx0_instr_i1_s3_dep_hit), + .rv0_fx0_instr_i1_s3_itag(rv0_fx0_instr_i1_s3_itag), + .rv0_fx1_instr_i0_vld(rv0_fx1_instr_i0_vld), + .rv0_fx1_instr_i0_rte_fx1(rv0_fx1_instr_i0_rte_fx1), + .rv0_fx1_instr_i0_instr(rv0_fx1_instr_i0_instr), + .rv0_fx1_instr_i0_ucode(rv0_fx1_instr_i0_ucode), + .rv0_fx1_instr_i0_itag(rv0_fx1_instr_i0_itag), + .rv0_fx1_instr_i0_t1_v(rv0_fx1_instr_i0_t1_v), + .rv0_fx1_instr_i0_t1_p(rv0_fx1_instr_i0_t1_p), + .rv0_fx1_instr_i0_t2_v(rv0_fx1_instr_i0_t2_v), + .rv0_fx1_instr_i0_t2_p(rv0_fx1_instr_i0_t2_p), + .rv0_fx1_instr_i0_t3_v(rv0_fx1_instr_i0_t3_v), + .rv0_fx1_instr_i0_t3_p(rv0_fx1_instr_i0_t3_p), + .rv0_fx1_instr_i0_s1_v(rv0_fx1_instr_i0_s1_v), + .rv0_fx1_instr_i0_s1_p(rv0_fx1_instr_i0_s1_p), + .rv0_fx1_instr_i0_s1_t(rv0_fx1_instr_i0_s1_t), + .rv0_fx1_instr_i0_s2_v(rv0_fx1_instr_i0_s2_v), + .rv0_fx1_instr_i0_s2_p(rv0_fx1_instr_i0_s2_p), + .rv0_fx1_instr_i0_s2_t(rv0_fx1_instr_i0_s2_t), + .rv0_fx1_instr_i0_s3_v(rv0_fx1_instr_i0_s3_v), + .rv0_fx1_instr_i0_s3_p(rv0_fx1_instr_i0_s3_p), + .rv0_fx1_instr_i0_s3_t(rv0_fx1_instr_i0_s3_t), + .rv0_fx1_instr_i0_ilat(rv0_fx1_instr_i0_ilat), + .rv0_fx1_instr_i0_isStore(rv0_fx1_instr_i0_isStore), + .rv0_fx1_instr_i0_spare(rv0_fx1_instr_i0_spare), + .rv0_fx1_instr_i0_is_brick(rv0_fx1_instr_i0_is_brick), + .rv0_fx1_instr_i0_brick(rv0_fx1_instr_i0_brick), + .rv0_fx1_instr_i1_vld(rv0_fx1_instr_i1_vld), + .rv0_fx1_instr_i1_rte_fx1(rv0_fx1_instr_i1_rte_fx1), + .rv0_fx1_instr_i1_instr(rv0_fx1_instr_i1_instr), + .rv0_fx1_instr_i1_ucode(rv0_fx1_instr_i1_ucode), + .rv0_fx1_instr_i1_itag(rv0_fx1_instr_i1_itag), + .rv0_fx1_instr_i1_t1_v(rv0_fx1_instr_i1_t1_v), + .rv0_fx1_instr_i1_t1_p(rv0_fx1_instr_i1_t1_p), + .rv0_fx1_instr_i1_t2_v(rv0_fx1_instr_i1_t2_v), + .rv0_fx1_instr_i1_t2_p(rv0_fx1_instr_i1_t2_p), + .rv0_fx1_instr_i1_t3_v(rv0_fx1_instr_i1_t3_v), + .rv0_fx1_instr_i1_t3_p(rv0_fx1_instr_i1_t3_p), + .rv0_fx1_instr_i1_s1_v(rv0_fx1_instr_i1_s1_v), + .rv0_fx1_instr_i1_s1_p(rv0_fx1_instr_i1_s1_p), + .rv0_fx1_instr_i1_s1_t(rv0_fx1_instr_i1_s1_t), + .rv0_fx1_instr_i1_s2_v(rv0_fx1_instr_i1_s2_v), + .rv0_fx1_instr_i1_s2_p(rv0_fx1_instr_i1_s2_p), + .rv0_fx1_instr_i1_s2_t(rv0_fx1_instr_i1_s2_t), + .rv0_fx1_instr_i1_s3_v(rv0_fx1_instr_i1_s3_v), + .rv0_fx1_instr_i1_s3_p(rv0_fx1_instr_i1_s3_p), + .rv0_fx1_instr_i1_s3_t(rv0_fx1_instr_i1_s3_t), + .rv0_fx1_instr_i1_ilat(rv0_fx1_instr_i1_ilat), + .rv0_fx1_instr_i1_isStore(rv0_fx1_instr_i1_isStore), + .rv0_fx1_instr_i1_spare(rv0_fx1_instr_i1_spare), + .rv0_fx1_instr_i1_is_brick(rv0_fx1_instr_i1_is_brick), + .rv0_fx1_instr_i1_brick(rv0_fx1_instr_i1_brick), + .rv0_fx1_instr_i0_s1_dep_hit(rv0_fx1_instr_i0_s1_dep_hit), + .rv0_fx1_instr_i0_s1_itag(rv0_fx1_instr_i0_s1_itag), + .rv0_fx1_instr_i0_s2_dep_hit(rv0_fx1_instr_i0_s2_dep_hit), + .rv0_fx1_instr_i0_s2_itag(rv0_fx1_instr_i0_s2_itag), + .rv0_fx1_instr_i0_s3_dep_hit(rv0_fx1_instr_i0_s3_dep_hit), + .rv0_fx1_instr_i0_s3_itag(rv0_fx1_instr_i0_s3_itag), + .rv0_fx1_instr_i1_s1_dep_hit(rv0_fx1_instr_i1_s1_dep_hit), + .rv0_fx1_instr_i1_s1_itag(rv0_fx1_instr_i1_s1_itag), + .rv0_fx1_instr_i1_s2_dep_hit(rv0_fx1_instr_i1_s2_dep_hit), + .rv0_fx1_instr_i1_s2_itag(rv0_fx1_instr_i1_s2_itag), + .rv0_fx1_instr_i1_s3_dep_hit(rv0_fx1_instr_i1_s3_dep_hit), + .rv0_fx1_instr_i1_s3_itag(rv0_fx1_instr_i1_s3_itag), + .rv0_lq_instr_i0_vld(rv0_lq_instr_i0_vld), + .rv0_lq_instr_i0_rte_lq(rv0_lq_instr_i0_rte_lq), + .rv0_lq_instr_i0_instr(rv0_lq_instr_i0_instr), + .rv0_lq_instr_i0_ucode(rv0_lq_instr_i0_ucode), + .rv0_lq_instr_i0_ucode_cnt(rv0_lq_instr_i0_ucode_cnt), + .rv0_lq_instr_i0_itag(rv0_lq_instr_i0_itag), + .rv0_lq_instr_i0_ord(rv0_lq_instr_i0_ord), + .rv0_lq_instr_i0_cord(rv0_lq_instr_i0_cord), + .rv0_lq_instr_i0_spec(rv0_lq_instr_i0_spec), + .rv0_lq_instr_i0_t1_v(rv0_lq_instr_i0_t1_v), + .rv0_lq_instr_i0_t1_p(rv0_lq_instr_i0_t1_p), + .rv0_lq_instr_i0_t2_v(rv0_lq_instr_i0_t2_v), + .rv0_lq_instr_i0_t2_p(rv0_lq_instr_i0_t2_p), + .rv0_lq_instr_i0_t2_t(rv0_lq_instr_i0_t2_t), + .rv0_lq_instr_i0_t3_v(rv0_lq_instr_i0_t3_v), + .rv0_lq_instr_i0_t3_p(rv0_lq_instr_i0_t3_p), + .rv0_lq_instr_i0_t3_t(rv0_lq_instr_i0_t3_t), + .rv0_lq_instr_i0_s1_v(rv0_lq_instr_i0_s1_v), + .rv0_lq_instr_i0_s1_p(rv0_lq_instr_i0_s1_p), + .rv0_lq_instr_i0_s1_t(rv0_lq_instr_i0_s1_t), + .rv0_lq_instr_i0_s2_v(rv0_lq_instr_i0_s2_v), + .rv0_lq_instr_i0_s2_p(rv0_lq_instr_i0_s2_p), + .rv0_lq_instr_i0_s2_t(rv0_lq_instr_i0_s2_t), + .rv0_lq_instr_i0_isLoad(rv0_lq_instr_i0_isLoad), + .rv0_lq_instr_i0_spare(rv0_lq_instr_i0_spare), + .rv0_lq_instr_i0_is_brick(rv0_lq_instr_i0_is_brick), + .rv0_lq_instr_i0_brick(rv0_lq_instr_i0_brick), + .rv0_lq_instr_i1_vld(rv0_lq_instr_i1_vld), + .rv0_lq_instr_i1_rte_lq(rv0_lq_instr_i1_rte_lq), + .rv0_lq_instr_i1_instr(rv0_lq_instr_i1_instr), + .rv0_lq_instr_i1_ucode(rv0_lq_instr_i1_ucode), + .rv0_lq_instr_i1_ucode_cnt(rv0_lq_instr_i1_ucode_cnt), + .rv0_lq_instr_i1_itag(rv0_lq_instr_i1_itag), + .rv0_lq_instr_i1_ord(rv0_lq_instr_i1_ord), + .rv0_lq_instr_i1_cord(rv0_lq_instr_i1_cord), + .rv0_lq_instr_i1_spec(rv0_lq_instr_i1_spec), + .rv0_lq_instr_i1_t1_v(rv0_lq_instr_i1_t1_v), + .rv0_lq_instr_i1_t1_p(rv0_lq_instr_i1_t1_p), + .rv0_lq_instr_i1_t2_v(rv0_lq_instr_i1_t2_v), + .rv0_lq_instr_i1_t2_p(rv0_lq_instr_i1_t2_p), + .rv0_lq_instr_i1_t2_t(rv0_lq_instr_i1_t2_t), + .rv0_lq_instr_i1_t3_v(rv0_lq_instr_i1_t3_v), + .rv0_lq_instr_i1_t3_p(rv0_lq_instr_i1_t3_p), + .rv0_lq_instr_i1_t3_t(rv0_lq_instr_i1_t3_t), + .rv0_lq_instr_i1_s1_v(rv0_lq_instr_i1_s1_v), + .rv0_lq_instr_i1_s1_p(rv0_lq_instr_i1_s1_p), + .rv0_lq_instr_i1_s1_t(rv0_lq_instr_i1_s1_t), + .rv0_lq_instr_i1_s2_v(rv0_lq_instr_i1_s2_v), + .rv0_lq_instr_i1_s2_p(rv0_lq_instr_i1_s2_p), + .rv0_lq_instr_i1_s2_t(rv0_lq_instr_i1_s2_t), + .rv0_lq_instr_i1_isLoad(rv0_lq_instr_i1_isLoad), + .rv0_lq_instr_i1_spare(rv0_lq_instr_i1_spare), + .rv0_lq_instr_i1_is_brick(rv0_lq_instr_i1_is_brick), + .rv0_lq_instr_i1_brick(rv0_lq_instr_i1_brick), + .rv0_lq_instr_i0_s1_dep_hit(rv0_lq_instr_i0_s1_dep_hit), + .rv0_lq_instr_i0_s1_itag(rv0_lq_instr_i0_s1_itag), + .rv0_lq_instr_i0_s2_dep_hit(rv0_lq_instr_i0_s2_dep_hit), + .rv0_lq_instr_i0_s2_itag(rv0_lq_instr_i0_s2_itag), + .rv0_lq_instr_i1_s1_dep_hit(rv0_lq_instr_i1_s1_dep_hit), + .rv0_lq_instr_i1_s1_itag(rv0_lq_instr_i1_s1_itag), + .rv0_lq_instr_i1_s2_dep_hit(rv0_lq_instr_i1_s2_dep_hit), + .rv0_lq_instr_i1_s2_itag(rv0_lq_instr_i1_s2_itag), + .rv0_axu0_instr_i0_vld(rv0_axu0_instr_i0_vld), + .rv0_axu0_instr_i0_rte_axu0(rv0_axu0_instr_i0_rte_axu0), + .rv0_axu0_instr_i0_instr(rv0_axu0_instr_i0_instr), + .rv0_axu0_instr_i0_ucode(rv0_axu0_instr_i0_ucode), + .rv0_axu0_instr_i0_itag(rv0_axu0_instr_i0_itag), + .rv0_axu0_instr_i0_ord(rv0_axu0_instr_i0_ord), + .rv0_axu0_instr_i0_cord(rv0_axu0_instr_i0_cord), + .rv0_axu0_instr_i0_t1_v(rv0_axu0_instr_i0_t1_v), + .rv0_axu0_instr_i0_t1_p(rv0_axu0_instr_i0_t1_p), + .rv0_axu0_instr_i0_t2_p(rv0_axu0_instr_i0_t2_p), + .rv0_axu0_instr_i0_t3_p(rv0_axu0_instr_i0_t3_p), + .rv0_axu0_instr_i0_s1_v(rv0_axu0_instr_i0_s1_v), + .rv0_axu0_instr_i0_s1_p(rv0_axu0_instr_i0_s1_p), + .rv0_axu0_instr_i0_s2_v(rv0_axu0_instr_i0_s2_v), + .rv0_axu0_instr_i0_s2_p(rv0_axu0_instr_i0_s2_p), + .rv0_axu0_instr_i0_s3_v(rv0_axu0_instr_i0_s3_v), + .rv0_axu0_instr_i0_s3_p(rv0_axu0_instr_i0_s3_p), + .rv0_axu0_instr_i0_isStore(rv0_axu0_instr_i0_isStore), + .rv0_axu0_instr_i0_spare(rv0_axu0_instr_i0_spare), + .rv0_axu0_instr_i1_vld(rv0_axu0_instr_i1_vld), + .rv0_axu0_instr_i1_rte_axu0(rv0_axu0_instr_i1_rte_axu0), + .rv0_axu0_instr_i1_instr(rv0_axu0_instr_i1_instr), + .rv0_axu0_instr_i1_ucode(rv0_axu0_instr_i1_ucode), + .rv0_axu0_instr_i1_itag(rv0_axu0_instr_i1_itag), + .rv0_axu0_instr_i1_ord(rv0_axu0_instr_i1_ord), + .rv0_axu0_instr_i1_cord(rv0_axu0_instr_i1_cord), + .rv0_axu0_instr_i1_t1_v(rv0_axu0_instr_i1_t1_v), + .rv0_axu0_instr_i1_t1_p(rv0_axu0_instr_i1_t1_p), + .rv0_axu0_instr_i1_t2_p(rv0_axu0_instr_i1_t2_p), + .rv0_axu0_instr_i1_t3_p(rv0_axu0_instr_i1_t3_p), + .rv0_axu0_instr_i1_s1_v(rv0_axu0_instr_i1_s1_v), + .rv0_axu0_instr_i1_s1_p(rv0_axu0_instr_i1_s1_p), + .rv0_axu0_instr_i1_s2_v(rv0_axu0_instr_i1_s2_v), + .rv0_axu0_instr_i1_s2_p(rv0_axu0_instr_i1_s2_p), + .rv0_axu0_instr_i1_s3_v(rv0_axu0_instr_i1_s3_v), + .rv0_axu0_instr_i1_s3_p(rv0_axu0_instr_i1_s3_p), + .rv0_axu0_instr_i1_isStore(rv0_axu0_instr_i1_isStore), + .rv0_axu0_instr_i1_spare(rv0_axu0_instr_i1_spare), + .rv0_axu0_instr_i0_s1_dep_hit(rv0_axu0_instr_i0_s1_dep_hit), + .rv0_axu0_instr_i0_s1_itag(rv0_axu0_instr_i0_s1_itag), + .rv0_axu0_instr_i0_s2_dep_hit(rv0_axu0_instr_i0_s2_dep_hit), + .rv0_axu0_instr_i0_s2_itag(rv0_axu0_instr_i0_s2_itag), + .rv0_axu0_instr_i0_s3_dep_hit(rv0_axu0_instr_i0_s3_dep_hit), + .rv0_axu0_instr_i0_s3_itag(rv0_axu0_instr_i0_s3_itag), + .rv0_axu0_instr_i1_s1_dep_hit(rv0_axu0_instr_i1_s1_dep_hit), + .rv0_axu0_instr_i1_s1_itag(rv0_axu0_instr_i1_s1_itag), + .rv0_axu0_instr_i1_s2_dep_hit(rv0_axu0_instr_i1_s2_dep_hit), + .rv0_axu0_instr_i1_s2_itag(rv0_axu0_instr_i1_s2_itag), + .rv0_axu0_instr_i1_s3_dep_hit(rv0_axu0_instr_i1_s3_dep_hit), + .rv0_axu0_instr_i1_s3_itag(rv0_axu0_instr_i1_s3_itag), + + .rv_lq_rv1_i0_vld(rv_lq_rv1_i0_vld), + .rv_lq_rv1_i0_ucode_preissue(rv_lq_rv1_i0_ucode_preissue), + .rv_lq_rv1_i0_2ucode(rv_lq_rv1_i0_2ucode), + .rv_lq_rv1_i0_ucode_cnt(rv_lq_rv1_i0_ucode_cnt), + .rv_lq_rv1_i0_s3_t(rv_lq_rv1_i0_s3_t), + .rv_lq_rv1_i0_isLoad(rv_lq_rv1_i0_isLoad), + .rv_lq_rv1_i0_isStore(rv_lq_rv1_i0_isStore), + .rv_lq_rv1_i0_itag(rv_lq_rv1_i0_itag), + .rv_lq_rv1_i0_rte_lq(rv_lq_rv1_i0_rte_lq), + .rv_lq_rv1_i0_rte_sq(rv_lq_rv1_i0_rte_sq), + .rv_lq_rv1_i0_ifar(rv_lq_rv1_i0_ifar), + + .rv_lq_rv1_i1_vld(rv_lq_rv1_i1_vld), + .rv_lq_rv1_i1_ucode_preissue(rv_lq_rv1_i1_ucode_preissue), + .rv_lq_rv1_i1_2ucode(rv_lq_rv1_i1_2ucode), + .rv_lq_rv1_i1_ucode_cnt(rv_lq_rv1_i1_ucode_cnt), + .rv_lq_rv1_i1_s3_t(rv_lq_rv1_i1_s3_t), + .rv_lq_rv1_i1_isLoad(rv_lq_rv1_i1_isLoad), + .rv_lq_rv1_i1_isStore(rv_lq_rv1_i1_isStore), + .rv_lq_rv1_i1_itag(rv_lq_rv1_i1_itag), + .rv_lq_rv1_i1_rte_lq(rv_lq_rv1_i1_rte_lq), + .rv_lq_rv1_i1_rte_sq(rv_lq_rv1_i1_rte_sq), + .rv_lq_rv1_i1_ifar(rv_lq_rv1_i1_ifar), + + + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .func_sl_thold_1(func_sl_thold_1), + .sg_1(sg_1), + .clkoff_b(clkoff_dc_b), + .act_dis(act_dis), + .ccflush_dc(rp_rv_ccflush_dc), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr_dc[0]), + .mpw1_b(mpw1_dc_b[0]), + .mpw2_b(mpw2_dc_b), + .scan_in(siv[rv_deps_offset]), + .scan_out(sov[rv_deps_offset]) + ); + + // Outputs + + //------------------------------------------------------------------------------------------------------------ + // Reservation Stations + //------------------------------------------------------------------------------------------------------------ + + //------------------------------------------------------------------------------------------------------------ + // fx0 reservation station + //------------------------------------------------------------------------------------------------------------ + + + rv_fx0_rvs + fx0_rvs( + .rv0_instr_i0_vld(rv0_fx0_instr_i0_vld), + .rv0_instr_i0_rte_fx0(rv0_fx0_instr_i0_rte_fx0), + .rv0_instr_i1_vld(rv0_fx0_instr_i1_vld), + .rv0_instr_i1_rte_fx0(rv0_fx0_instr_i1_rte_fx0), + .rv0_instr_i0_instr(rv0_fx0_instr_i0_instr), + .rv0_instr_i0_ifar(rv0_fx0_instr_i0_ifar), + .rv0_instr_i0_ucode(rv0_fx0_instr_i0_ucode), + .rv0_instr_i0_ucode_cnt(rv0_fx0_instr_i0_ucode_cnt), + .rv0_instr_i0_itag(rv0_fx0_instr_i0_itag), + .rv0_instr_i0_ord(rv0_fx0_instr_i0_ord), + .rv0_instr_i0_cord(rv0_fx0_instr_i0_cord), + .rv0_instr_i0_t1_v(rv0_fx0_instr_i0_t1_v), + .rv0_instr_i0_t1_p(rv0_fx0_instr_i0_t1_p), + .rv0_instr_i0_t1_t(rv0_fx0_instr_i0_t1_t), + .rv0_instr_i0_t2_v(rv0_fx0_instr_i0_t2_v), + .rv0_instr_i0_t2_p(rv0_fx0_instr_i0_t2_p), + .rv0_instr_i0_t2_t(rv0_fx0_instr_i0_t2_t), + .rv0_instr_i0_t3_v(rv0_fx0_instr_i0_t3_v), + .rv0_instr_i0_t3_p(rv0_fx0_instr_i0_t3_p), + .rv0_instr_i0_t3_t(rv0_fx0_instr_i0_t3_t), + .rv0_instr_i0_s1_v(rv0_fx0_instr_i0_s1_v), + .rv0_instr_i0_s1_p(rv0_fx0_instr_i0_s1_p), + .rv0_instr_i0_s1_t(rv0_fx0_instr_i0_s1_t), + .rv0_instr_i0_s2_v(rv0_fx0_instr_i0_s2_v), + .rv0_instr_i0_s2_p(rv0_fx0_instr_i0_s2_p), + .rv0_instr_i0_s2_t(rv0_fx0_instr_i0_s2_t), + .rv0_instr_i0_s3_v(rv0_fx0_instr_i0_s3_v), + .rv0_instr_i0_s3_p(rv0_fx0_instr_i0_s3_p), + .rv0_instr_i0_s3_t(rv0_fx0_instr_i0_s3_t), + .rv0_instr_i0_ilat(rv0_fx0_instr_i0_ilat), + .rv0_instr_i0_spare(rv0_fx0_instr_i0_spare), + .rv0_instr_i0_is_brick(rv0_fx0_instr_i0_is_brick), + .rv0_instr_i0_brick(rv0_fx0_instr_i0_brick), + .rv0_instr_i0_branch(rv0_fx0_instr_i0_branch), + .rv0_instr_i1_instr(rv0_fx0_instr_i1_instr), + .rv0_instr_i1_ifar(rv0_fx0_instr_i1_ifar), + .rv0_instr_i1_ucode(rv0_fx0_instr_i1_ucode), + .rv0_instr_i1_ucode_cnt(rv0_fx0_instr_i1_ucode_cnt), + .rv0_instr_i1_itag(rv0_fx0_instr_i1_itag), + .rv0_instr_i1_ord(rv0_fx0_instr_i1_ord), + .rv0_instr_i1_cord(rv0_fx0_instr_i1_cord), + .rv0_instr_i1_t1_v(rv0_fx0_instr_i1_t1_v), + .rv0_instr_i1_t1_p(rv0_fx0_instr_i1_t1_p), + .rv0_instr_i1_t1_t(rv0_fx0_instr_i1_t1_t), + .rv0_instr_i1_t2_v(rv0_fx0_instr_i1_t2_v), + .rv0_instr_i1_t2_p(rv0_fx0_instr_i1_t2_p), + .rv0_instr_i1_t2_t(rv0_fx0_instr_i1_t2_t), + .rv0_instr_i1_t3_v(rv0_fx0_instr_i1_t3_v), + .rv0_instr_i1_t3_p(rv0_fx0_instr_i1_t3_p), + .rv0_instr_i1_t3_t(rv0_fx0_instr_i1_t3_t), + .rv0_instr_i1_s1_v(rv0_fx0_instr_i1_s1_v), + .rv0_instr_i1_s1_p(rv0_fx0_instr_i1_s1_p), + .rv0_instr_i1_s1_t(rv0_fx0_instr_i1_s1_t), + .rv0_instr_i1_s2_v(rv0_fx0_instr_i1_s2_v), + .rv0_instr_i1_s2_p(rv0_fx0_instr_i1_s2_p), + .rv0_instr_i1_s2_t(rv0_fx0_instr_i1_s2_t), + .rv0_instr_i1_s3_v(rv0_fx0_instr_i1_s3_v), + .rv0_instr_i1_s3_p(rv0_fx0_instr_i1_s3_p), + .rv0_instr_i1_s3_t(rv0_fx0_instr_i1_s3_t), + .rv0_instr_i1_ilat(rv0_fx0_instr_i1_ilat), + .rv0_instr_i1_spare(rv0_fx0_instr_i1_spare), + .rv0_instr_i1_is_brick(rv0_fx0_instr_i1_is_brick), + .rv0_instr_i1_brick(rv0_fx0_instr_i1_brick), + .rv0_instr_i1_branch(rv0_fx0_instr_i1_branch), + .rv0_instr_i0_s1_dep_hit(rv0_fx0_instr_i0_s1_dep_hit), + .rv0_instr_i0_s1_itag(rv0_fx0_instr_i0_s1_itag), + .rv0_instr_i0_s2_dep_hit(rv0_fx0_instr_i0_s2_dep_hit), + .rv0_instr_i0_s2_itag(rv0_fx0_instr_i0_s2_itag), + .rv0_instr_i0_s3_dep_hit(rv0_fx0_instr_i0_s3_dep_hit), + .rv0_instr_i0_s3_itag(rv0_fx0_instr_i0_s3_itag), + .rv0_instr_i1_s1_dep_hit(rv0_fx0_instr_i1_s1_dep_hit), + .rv0_instr_i1_s1_itag(rv0_fx0_instr_i1_s1_itag), + .rv0_instr_i1_s2_dep_hit(rv0_fx0_instr_i1_s2_dep_hit), + .rv0_instr_i1_s2_itag(rv0_fx0_instr_i1_s2_itag), + .rv0_instr_i1_s3_dep_hit(rv0_fx0_instr_i1_s3_dep_hit), + .rv0_instr_i1_s3_itag(rv0_fx0_instr_i1_s3_itag), + .rv_iu_fx0_credit_free(rv_iu_fx0_credit_free), + .cp_flush(cp_flush), + .cp_next_itag(cp_next_itag), + + .rv_byp_fx0_vld(rv_byp_fx0_vld), + .rv_byp_fx0_itag(rv_byp_fx0_itag), + .rv_byp_fx0_ord(rv_byp_fx0_ord), + .rv_byp_fx0_t1_v(rv_byp_fx0_t1_v), + .rv_byp_fx0_t1_t(rv_byp_fx0_t1_t), + .rv_byp_fx0_t2_v(rv_byp_fx0_t2_v), + .rv_byp_fx0_t2_t(rv_byp_fx0_t2_t), + .rv_byp_fx0_t3_v(rv_byp_fx0_t3_v), + .rv_byp_fx0_t3_t(rv_byp_fx0_t3_t), + .rv_byp_fx0_s1_t(rv_byp_fx0_s1_t), + .rv_byp_fx0_s2_t(rv_byp_fx0_s2_t), + .rv_byp_fx0_s3_t(rv_byp_fx0_s3_t), + .rv_byp_fx0_ilat(rv_byp_fx0_ilat), + .rv_byp_fx0_ex0_is_brick(rv_byp_fx0_ex0_is_brick), + + .rv_fx0_vld(rv_fx0_vld), + .rv_fx0_s1_v(rv_fx0_s1_v), + .rv_fx0_s1_p(rv_fx0_s1_p), + .rv_fx0_s2_v(rv_fx0_s2_v), + .rv_fx0_s2_p(rv_fx0_s2_p), + .rv_fx0_s3_v(rv_fx0_s3_v), + .rv_fx0_s3_p(rv_fx0_s3_p), + + .rv_fx0_ex0_itag(rv_fx0_ex0_itag), + .rv_fx0_ex0_ifar(rv_fx0_ex0_ifar), + .rv_fx0_ex0_instr(rv_fx0_ex0_instr), + .rv_fx0_ex0_ucode(rv_fx0_ex0_ucode), + .rv_fx0_ex0_ucode_cnt(rv_fx0_ex0_ucode_cnt), + .rv_fx0_ex0_ord(rv_fx0_ex0_ord), + .rv_fx0_ex0_t1_v(rv_fx0_ex0_t1_v), + .rv_fx0_ex0_t1_p(rv_fx0_ex0_t1_p), + .rv_fx0_ex0_t1_t(rv_fx0_ex0_t1_t), + .rv_fx0_ex0_t2_v(rv_fx0_ex0_t2_v), + .rv_fx0_ex0_t2_p(rv_fx0_ex0_t2_p), + .rv_fx0_ex0_t2_t(rv_fx0_ex0_t2_t), + .rv_fx0_ex0_t3_v(rv_fx0_ex0_t3_v), + .rv_fx0_ex0_t3_p(rv_fx0_ex0_t3_p), + .rv_fx0_ex0_t3_t(rv_fx0_ex0_t3_t), + .rv_fx0_ex0_s1_v(rv_fx0_ex0_s1_v), + .rv_fx0_ex0_s2_v(rv_fx0_ex0_s2_v), + .rv_fx0_ex0_s2_t(rv_fx0_ex0_s2_t), + .rv_fx0_ex0_s3_v(rv_fx0_ex0_s3_v), + .rv_fx0_ex0_s3_t(rv_fx0_ex0_s3_t), + .rv_fx0_ex0_branch(rv_fx0_ex0_branch), + + .rv_byp_fx0_s1_itag(rv_byp_fx0_s1_itag), + .rv_byp_fx0_s2_itag(rv_byp_fx0_s2_itag), + .rv_byp_fx0_s3_itag(rv_byp_fx0_s3_itag), + + .fx0_rv_itag_vld(fx0_rv_itag_vld), + .fx0_rv_itag(fx0_rv_itag), + .fx1_rv_itag_vld(fx1_rv_itag_vld), + .fx1_rv_itag(fx1_rv_itag), + .axu0_rv_ext_itag_vld(axu0_rv_ext_itag_vld), + .axu0_rv_ext_itag(axu0_rv_ext_itag), + .axu1_rv_ext_itag_vld(axu1_rv_ext_itag_vld), + .axu1_rv_ext_itag(axu1_rv_ext_itag), + .lq_rv_ext_itag0_vld(lq_rv_ext_itag0_vld), + .lq_rv_ext_itag0(lq_rv_ext_itag0), + .lq_rv_ext_itag1_vld(lq_rv_ext_itag1_vld), + .lq_rv_ext_itag1(lq_rv_ext_itag1), + .lq_rv_ext_itag2_vld(lq_rv_ext_itag2_vld), + .lq_rv_ext_itag2(lq_rv_ext_itag2), + + .lq_rv_itag1_vld(lq_rv_itag1_vld), + .lq_rv_itag1(lq_rv_itag1), + .lq_rv_itag1_restart(lq_rv_itag1_restart), + .lq_rv_itag1_hold(lq_rv_itag1_hold), + .lq_rv_clr_hold(lq_rv_clr_hold), + + .fx0_rv_ex2_s1_abort(fx0_rv_ex2_s1_abort), + .fx0_rv_ex2_s2_abort(fx0_rv_ex2_s2_abort), + .fx0_rv_ex2_s3_abort(fx0_rv_ex2_s3_abort), + + .fx0_rv_itag_abort(fx0_rv_itag_abort), + .fx1_rv_itag_abort(fx1_rv_itag_abort), + .lq_rv_ext_itag0_abort(lq_rv_ext_itag0_abort), + .lq_rv_ext_itag1_abort(lq_rv_ext_itag1_abort), + .axu0_rv_ext_itag_abort(axu0_rv_ext_itag_abort), + .axu1_rv_ext_itag_abort(axu1_rv_ext_itag_abort), + + .fx0_rv_ord_complete(fx0_release_ord_hold), + .fx0_rv_ord_tid(fx0_rv_ord_tid), + .fx0_rv_hold_all(fx0_rv_hold_all), + .rv_byp_fx0_ilat0_vld(rv_byp_fx0_ilat0_vld), + .rv_byp_fx0_ilat1_vld(rv_byp_fx0_ilat1_vld), + .rv1_fx0_ilat0_vld(rv1_fx0_ilat0_vld), + .rv1_fx0_ilat0_itag(rv1_fx0_ilat0_itag), + .rv1_fx1_ilat0_vld(rv1_fx1_ilat0_vld), + .rv1_fx1_ilat0_itag(rv1_fx1_ilat0_itag), + .fx0_rvs_perf_bus(fx0_rvs_perf_bus), + .fx0_rvs_dbg_bus(fx0_rvs_dbg_bus), + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .func_sl_thold_1(func_sl_thold_1), + .sg_1(sg_1), + .clkoff_b(clkoff_dc_b), + .act_dis(act_dis), + .ccflush_dc(rp_rv_ccflush_dc), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr_dc[0]), + .mpw1_b(mpw1_dc_b[0]), + .mpw2_b(mpw2_dc_b), + .scan_in(siv[rv_fx0_rvs_offset]), + .scan_out(sov[rv_fx0_rvs_offset]) + ); + + //------------------------------------------------------------------------------------------------------------ + // fx1 reservation station + //------------------------------------------------------------------------------------------------------------ + + + rv_fx1_rvs + fx1_rvs( + .rv0_instr_i0_vld(rv0_fx1_instr_i0_vld), + .rv0_instr_i0_rte_fx1(rv0_fx1_instr_i0_rte_fx1), + .rv0_instr_i1_vld(rv0_fx1_instr_i1_vld), + .rv0_instr_i1_rte_fx1(rv0_fx1_instr_i1_rte_fx1), + .rv0_instr_i0_instr(rv0_fx1_instr_i0_instr), + .rv0_instr_i0_ucode(rv0_fx1_instr_i0_ucode), + .rv0_instr_i0_itag(rv0_fx1_instr_i0_itag), + .rv0_instr_i0_t1_v(rv0_fx1_instr_i0_t1_v), + .rv0_instr_i0_t1_p(rv0_fx1_instr_i0_t1_p), + .rv0_instr_i0_t2_v(rv0_fx1_instr_i0_t2_v), + .rv0_instr_i0_t2_p(rv0_fx1_instr_i0_t2_p), + .rv0_instr_i0_t3_v(rv0_fx1_instr_i0_t3_v), + .rv0_instr_i0_t3_p(rv0_fx1_instr_i0_t3_p), + .rv0_instr_i0_s1_v(rv0_fx1_instr_i0_s1_v), + .rv0_instr_i0_s1_p(rv0_fx1_instr_i0_s1_p), + .rv0_instr_i0_s1_t(rv0_fx1_instr_i0_s1_t), + .rv0_instr_i0_s2_v(rv0_fx1_instr_i0_s2_v), + .rv0_instr_i0_s2_p(rv0_fx1_instr_i0_s2_p), + .rv0_instr_i0_s2_t(rv0_fx1_instr_i0_s2_t), + .rv0_instr_i0_s3_v(rv0_fx1_instr_i0_s3_v), + .rv0_instr_i0_s3_p(rv0_fx1_instr_i0_s3_p), + .rv0_instr_i0_s3_t(rv0_fx1_instr_i0_s3_t), + .rv0_instr_i0_ilat(rv0_fx1_instr_i0_ilat), + .rv0_instr_i0_isStore(rv0_fx1_instr_i0_isStore), + .rv0_instr_i0_spare(rv0_fx1_instr_i0_spare), + .rv0_instr_i0_is_brick(rv0_fx1_instr_i0_is_brick), + .rv0_instr_i0_brick(rv0_fx1_instr_i0_brick), + .rv0_instr_i1_instr(rv0_fx1_instr_i1_instr), + .rv0_instr_i1_ucode(rv0_fx1_instr_i1_ucode), + .rv0_instr_i1_itag(rv0_fx1_instr_i1_itag), + .rv0_instr_i1_t1_v(rv0_fx1_instr_i1_t1_v), + .rv0_instr_i1_t1_p(rv0_fx1_instr_i1_t1_p), + .rv0_instr_i1_t2_v(rv0_fx1_instr_i1_t2_v), + .rv0_instr_i1_t2_p(rv0_fx1_instr_i1_t2_p), + .rv0_instr_i1_t3_v(rv0_fx1_instr_i1_t3_v), + .rv0_instr_i1_t3_p(rv0_fx1_instr_i1_t3_p), + .rv0_instr_i1_s1_v(rv0_fx1_instr_i1_s1_v), + .rv0_instr_i1_s1_p(rv0_fx1_instr_i1_s1_p), + .rv0_instr_i1_s1_t(rv0_fx1_instr_i1_s1_t), + .rv0_instr_i1_s2_v(rv0_fx1_instr_i1_s2_v), + .rv0_instr_i1_s2_p(rv0_fx1_instr_i1_s2_p), + .rv0_instr_i1_s2_t(rv0_fx1_instr_i1_s2_t), + .rv0_instr_i1_s3_v(rv0_fx1_instr_i1_s3_v), + .rv0_instr_i1_s3_p(rv0_fx1_instr_i1_s3_p), + .rv0_instr_i1_s3_t(rv0_fx1_instr_i1_s3_t), + .rv0_instr_i1_ilat(rv0_fx1_instr_i1_ilat), + .rv0_instr_i1_isStore(rv0_fx1_instr_i1_isStore), + .rv0_instr_i1_spare(rv0_fx1_instr_i1_spare), + .rv0_instr_i1_is_brick(rv0_fx1_instr_i1_is_brick), + .rv0_instr_i1_brick(rv0_fx1_instr_i1_brick), + .rv0_instr_i0_s1_dep_hit(rv0_fx1_instr_i0_s1_dep_hit), + .rv0_instr_i0_s1_itag(rv0_fx1_instr_i0_s1_itag), + .rv0_instr_i0_s2_dep_hit(rv0_fx1_instr_i0_s2_dep_hit), + .rv0_instr_i0_s2_itag(rv0_fx1_instr_i0_s2_itag), + .rv0_instr_i0_s3_dep_hit(rv0_fx1_instr_i0_s3_dep_hit), + .rv0_instr_i0_s3_itag(rv0_fx1_instr_i0_s3_itag), + .rv0_instr_i1_s1_dep_hit(rv0_fx1_instr_i1_s1_dep_hit), + .rv0_instr_i1_s1_itag(rv0_fx1_instr_i1_s1_itag), + .rv0_instr_i1_s2_dep_hit(rv0_fx1_instr_i1_s2_dep_hit), + .rv0_instr_i1_s2_itag(rv0_fx1_instr_i1_s2_itag), + .rv0_instr_i1_s3_dep_hit(rv0_fx1_instr_i1_s3_dep_hit), + .rv0_instr_i1_s3_itag(rv0_fx1_instr_i1_s3_itag), + .rv_iu_fx1_credit_free(rv_iu_fx1_credit_free), + .cp_flush(cp_flush), + + .rv_byp_fx1_vld(rv_byp_fx1_vld), + .rv_byp_fx1_itag(rv_byp_fx1_itag), + .rv_byp_fx1_t1_v(rv_byp_fx1_t1_v), + .rv_byp_fx1_t2_v(rv_byp_fx1_t2_v), + .rv_byp_fx1_t3_v(rv_byp_fx1_t3_v), + .rv_byp_fx1_s1_t(rv_byp_fx1_s1_t), + .rv_byp_fx1_s2_t(rv_byp_fx1_s2_t), + .rv_byp_fx1_s3_t(rv_byp_fx1_s3_t), + .rv_byp_fx1_ilat(rv_byp_fx1_ilat), + .rv_byp_fx1_ex0_isStore(rv_byp_fx1_ex0_isStore), + + .rv_fx1_vld(rv_fx1_vld), + .rv_fx1_s1_v(rv_fx1_s1_v), + .rv_fx1_s1_p(rv_fx1_s1_p), + .rv_fx1_s2_v(rv_fx1_s2_v), + .rv_fx1_s2_p(rv_fx1_s2_p), + .rv_fx1_s3_v(rv_fx1_s3_v), + .rv_fx1_s3_p(rv_fx1_s3_p), + + .rv_fx1_ex0_itag(rv_fx1_ex0_itag), + .rv_fx1_ex0_instr(rv_fx1_ex0_instr), + .rv_fx1_ex0_ucode(rv_fx1_ex0_ucode), + .rv_fx1_ex0_t1_v(rv_fx1_ex0_t1_v), + .rv_fx1_ex0_t1_p(rv_fx1_ex0_t1_p), + .rv_fx1_ex0_t2_v(rv_fx1_ex0_t2_v), + .rv_fx1_ex0_t2_p(rv_fx1_ex0_t2_p), + .rv_fx1_ex0_t3_v(rv_fx1_ex0_t3_v), + .rv_fx1_ex0_t3_p(rv_fx1_ex0_t3_p), + .rv_fx1_ex0_s1_v(rv_fx1_ex0_s1_v), + .rv_fx1_ex0_s3_t(rv_fx1_ex0_s3_t), + .rv_fx1_ex0_isStore(rv_fx1_ex0_isStore), + + .rv_byp_fx1_s1_itag(rv_byp_fx1_s1_itag), + .rv_byp_fx1_s2_itag(rv_byp_fx1_s2_itag), + .rv_byp_fx1_s3_itag(rv_byp_fx1_s3_itag), + + .fx1_rv_ex2_s1_abort(fx1_rv_ex2_s1_abort), + .fx1_rv_ex2_s2_abort(fx1_rv_ex2_s2_abort), + .fx1_rv_ex2_s3_abort(fx1_rv_ex2_s3_abort), + + .fx0_rv_itag_vld(fx0_rv_itag_vld), + .fx0_rv_itag(fx0_rv_itag), + .fx1_rv_itag_vld(fx1_rv_itag_vld), + .fx1_rv_itag(fx1_rv_itag), + .axu0_rv_ext_itag_vld(axu0_rv_ext_itag_vld), + .axu0_rv_ext_itag(axu0_rv_ext_itag), + .axu1_rv_ext_itag_vld(axu1_rv_ext_itag_vld), + .axu1_rv_ext_itag(axu1_rv_ext_itag), + .lq_rv_ext_itag0_vld(lq_rv_ext_itag0_vld), + .lq_rv_ext_itag0(lq_rv_ext_itag0), + .lq_rv_ext_itag1_vld(lq_rv_ext_itag1_vld), + .lq_rv_ext_itag1(lq_rv_ext_itag1), + .lq_rv_ext_itag2_vld(lq_rv_ext_itag2_vld), + .lq_rv_ext_itag2(lq_rv_ext_itag2), + + .lq_rv_itag1_vld(lq_rv_itag1_vld), + .lq_rv_itag1(lq_rv_itag1), + .lq_rv_itag1_restart(lq_rv_itag1_restart), + .lq_rv_itag1_hold(lq_rv_itag1_hold), + .lq_rv_clr_hold(lq_rv_clr_hold), + + .fx0_rv_itag_abort(fx0_rv_itag_abort), + .fx1_rv_itag_abort(fx1_rv_itag_abort), + .lq_rv_ext_itag0_abort(lq_rv_ext_itag0_abort), + .lq_rv_ext_itag1_abort(lq_rv_ext_itag1_abort), + .axu0_rv_ext_itag_abort(axu0_rv_ext_itag_abort), + .axu1_rv_ext_itag_abort(axu1_rv_ext_itag_abort), + + .fx1_rv_hold_all(fx1_rv_hold_all), + .rv_byp_fx1_ilat0_vld(rv_byp_fx1_ilat0_vld), + .rv_byp_fx1_ilat1_vld(rv_byp_fx1_ilat1_vld), + .rv1_fx0_ilat0_vld(rv1_fx0_ilat0_vld), + .rv1_fx0_ilat0_itag(rv1_fx0_ilat0_itag), + .rv1_fx1_ilat0_vld(rv1_fx1_ilat0_vld), + .rv1_fx1_ilat0_itag(rv1_fx1_ilat0_itag), + .fx1_rvs_perf_bus(fx1_rvs_perf_bus), + .fx1_rvs_dbg_bus(fx1_rvs_dbg_bus), + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .func_sl_thold_1(func_sl_thold_1), + .sg_1(sg_1), + .clkoff_b(clkoff_dc_b), + .act_dis(act_dis), + .ccflush_dc(rp_rv_ccflush_dc), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr_dc[0]), + .mpw1_b(mpw1_dc_b[0]), + .mpw2_b(mpw2_dc_b), + .scan_in(siv[rv_fx1_rvs_offset]), + .scan_out(sov[rv_fx1_rvs_offset]) + ); + + //------------------------------------------------------------------------------------------------------------ + // lq reservation station + //------------------------------------------------------------------------------------------------------------ + + + rv_lq_rvs + lq0_rvs( + .rv0_instr_i0_vld(rv0_lq_instr_i0_vld), + .rv0_instr_i0_rte(rv0_lq_instr_i0_rte_lq), + .rv0_instr_i1_vld(rv0_lq_instr_i1_vld), + .rv0_instr_i1_rte(rv0_lq_instr_i1_rte_lq), + .rv0_instr_i0_instr(rv0_lq_instr_i0_instr), + .rv0_instr_i0_ucode(rv0_lq_instr_i0_ucode), + .rv0_instr_i0_ucode_cnt(rv0_lq_instr_i0_ucode_cnt), + .rv0_instr_i0_itag(rv0_lq_instr_i0_itag), + .rv0_instr_i0_ord(rv0_lq_instr_i0_ord), + .rv0_instr_i0_cord(rv0_lq_instr_i0_cord), + .rv0_instr_i0_spec(rv0_lq_instr_i0_spec), + .rv0_instr_i0_t1_v(rv0_lq_instr_i0_t1_v), + .rv0_instr_i0_t1_p(rv0_lq_instr_i0_t1_p), + .rv0_instr_i0_t2_v(rv0_lq_instr_i0_t2_v), + .rv0_instr_i0_t2_p(rv0_lq_instr_i0_t2_p), + .rv0_instr_i0_t2_t(rv0_lq_instr_i0_t2_t), + .rv0_instr_i0_t3_v(rv0_lq_instr_i0_t3_v), + .rv0_instr_i0_t3_p(rv0_lq_instr_i0_t3_p), + .rv0_instr_i0_t3_t(rv0_lq_instr_i0_t3_t), + .rv0_instr_i0_s1_v(rv0_lq_instr_i0_s1_v), + .rv0_instr_i0_s1_p(rv0_lq_instr_i0_s1_p), + .rv0_instr_i0_s1_t(rv0_lq_instr_i0_s1_t), + .rv0_instr_i0_s2_v(rv0_lq_instr_i0_s2_v), + .rv0_instr_i0_s2_p(rv0_lq_instr_i0_s2_p), + .rv0_instr_i0_s2_t(rv0_lq_instr_i0_s2_t), + .rv0_instr_i0_isLoad(rv0_lq_instr_i0_isLoad), + .rv0_instr_i0_spare(rv0_lq_instr_i0_spare), + .rv0_instr_i0_is_brick(rv0_lq_instr_i0_is_brick), + .rv0_instr_i0_brick(rv0_lq_instr_i0_brick), + .rv0_instr_i1_instr(rv0_lq_instr_i1_instr), + .rv0_instr_i1_ucode(rv0_lq_instr_i1_ucode), + .rv0_instr_i1_ucode_cnt(rv0_lq_instr_i1_ucode_cnt), + .rv0_instr_i1_itag(rv0_lq_instr_i1_itag), + .rv0_instr_i1_ord(rv0_lq_instr_i1_ord), + .rv0_instr_i1_cord(rv0_lq_instr_i1_cord), + .rv0_instr_i1_spec(rv0_lq_instr_i1_spec), + .rv0_instr_i1_t1_v(rv0_lq_instr_i1_t1_v), + .rv0_instr_i1_t1_p(rv0_lq_instr_i1_t1_p), + .rv0_instr_i1_t2_v(rv0_lq_instr_i1_t2_v), + .rv0_instr_i1_t2_p(rv0_lq_instr_i1_t2_p), + .rv0_instr_i1_t2_t(rv0_lq_instr_i1_t2_t), + .rv0_instr_i1_t3_v(rv0_lq_instr_i1_t3_v), + .rv0_instr_i1_t3_p(rv0_lq_instr_i1_t3_p), + .rv0_instr_i1_t3_t(rv0_lq_instr_i1_t3_t), + .rv0_instr_i1_s1_v(rv0_lq_instr_i1_s1_v), + .rv0_instr_i1_s1_p(rv0_lq_instr_i1_s1_p), + .rv0_instr_i1_s1_t(rv0_lq_instr_i1_s1_t), + .rv0_instr_i1_s2_v(rv0_lq_instr_i1_s2_v), + .rv0_instr_i1_s2_p(rv0_lq_instr_i1_s2_p), + .rv0_instr_i1_s2_t(rv0_lq_instr_i1_s2_t), + .rv0_instr_i1_isLoad(rv0_lq_instr_i1_isLoad), + .rv0_instr_i1_spare(rv0_lq_instr_i1_spare), + .rv0_instr_i1_is_brick(rv0_lq_instr_i1_is_brick), + .rv0_instr_i1_brick(rv0_lq_instr_i1_brick), + .rv0_instr_i0_s1_dep_hit(rv0_lq_instr_i0_s1_dep_hit), + .rv0_instr_i0_s1_itag(rv0_lq_instr_i0_s1_itag), + .rv0_instr_i0_s2_dep_hit(rv0_lq_instr_i0_s2_dep_hit), + .rv0_instr_i0_s2_itag(rv0_lq_instr_i0_s2_itag), + .rv0_instr_i1_s1_dep_hit(rv0_lq_instr_i1_s1_dep_hit), + .rv0_instr_i1_s1_itag(rv0_lq_instr_i1_s1_itag), + .rv0_instr_i1_s2_dep_hit(rv0_lq_instr_i1_s2_dep_hit), + .rv0_instr_i1_s2_itag(rv0_lq_instr_i1_s2_itag), + .rv_iu_lq_credit_free(rv_iu_lq_credit_free), + + .cp_flush(cp_flush), + .cp_next_itag(cp_next_itag), + + .rv_lq_vld(rv_byp_lq_vld), + .rv_lq_itag(rv_byp_lq_itag), + .rv_lq_t1_v(rv_byp_lq_t1_v), + .rv_lq_t3_v(rv_byp_lq_t3_v), + .rv_lq_t3_t(rv_byp_lq_t3_t), + .rv_lq_s1_v(rv_byp_lq_s1_v), + .rv_lq_s1_t(rv_byp_lq_s1_t), + .rv_lq_s1_p(rv_byp_lq_s1_p), + .rv_lq_s2_v(rv_byp_lq_s2_v), + .rv_lq_s2_t(rv_byp_lq_s2_t), + .rv_lq_s2_p(rv_byp_lq_s2_p), + .rv_lq_isLoad(rv_lq_isLoad), + .rv_lq_ex0_s1_itag(rv_byp_lq_ex0_s1_itag), + .rv_lq_ex0_s2_itag(rv_byp_lq_ex0_s2_itag), + + .rv_lq_ex0_itag(rv_lq_ex0_itag), + .rv_lq_ex0_instr(rv_lq_ex0_instr), + .rv_lq_ex0_ucode(rv_lq_ex0_ucode), + .rv_lq_ex0_ucode_cnt(rv_lq_ex0_ucode_cnt), + .rv_lq_ex0_spec(rv_lq_ex0_spec), + .rv_lq_ex0_t1_v(rv_lq_ex0_t1_v), + .rv_lq_ex0_t1_p(rv_lq_ex0_t1_p), + .rv_lq_ex0_t3_p(rv_lq_ex0_t3_p), + .rv_lq_ex0_s1_v(rv_lq_ex0_s1_v), + .rv_lq_ex0_s2_v(rv_lq_ex0_s2_v), + .rv_lq_ex0_s2_t(rv_lq_ex0_s2_t), + .rv_lq_rvs_empty(rv_lq_rvs_empty), + + .lq_rv_ex2_s1_abort(lq_rv_ex2_s1_abort), + .lq_rv_ex2_s2_abort(lq_rv_ex2_s2_abort), + + .fx0_rv_ext_itag_vld(fx0_rv_ext_itag_vld), + .fx0_rv_ext_itag(fx0_rv_ext_itag), + .fx1_rv_ext_itag_vld(fx1_rv_ext_itag_vld), + .fx1_rv_ext_itag(fx1_rv_ext_itag), + .axu0_rv_ext_itag_vld(axu0_rv_ext_itag_vld), + .axu0_rv_ext_itag(axu0_rv_ext_itag), + .axu1_rv_ext_itag_vld(axu1_rv_ext_itag_vld), + .axu1_rv_ext_itag(axu1_rv_ext_itag), + + .lq_rv_itag0_vld(lq_rv_itag0_vld), + .lq_rv_itag0(lq_rv_itag0), + .lq_rv_itag1_vld(lq_rv_itag1_vld), + .lq_rv_itag1(lq_rv_itag1), + .lq_rv_itag1_restart(lq_rv_itag1_restart), + .lq_rv_itag1_hold(lq_rv_itag1_hold), + .lq_rv_itag1_cord(lq_rv_itag1_cord), + .lq_rv_itag2_vld(lq_rv_itag2_vld), + .lq_rv_itag2(lq_rv_itag2), + .lq_rv_clr_hold(lq_rv_clr_hold), + .lq_rv_ord_complete(lq_rv_ord_complete), + .lq_rv_hold_all(lq_rv_hold_all), + + .fx0_rv_ext_itag_abort(fx0_rv_ext_itag_abort), + .fx1_rv_ext_itag_abort(fx1_rv_ext_itag_abort), + .lq_rv_itag0_abort(lq_rv_itag0_abort), + .lq_rv_itag1_abort(lq_rv_itag1_abort), + .axu0_rv_ext_itag_abort(axu0_rv_ext_itag_abort), + .axu1_rv_ext_itag_abort(axu1_rv_ext_itag_abort), + + .lq_rv_ext_itag0_vld(lq_rv_ext_itag0_vld), + .lq_rv_ext_itag0_abort(lq_rv_ext_itag0_abort), + .lq_rv_ext_itag0(lq_rv_ext_itag0), + .lq_rv_ext_itag1_vld(lq_rv_ext_itag1_vld), + .lq_rv_ext_itag1_abort(lq_rv_ext_itag1_abort), + .lq_rv_ext_itag1(lq_rv_ext_itag1), + .lq_rv_ext_itag2_vld(lq_rv_ext_itag2_vld), + .lq_rv_ext_itag2(lq_rv_ext_itag2), + .lq_rvs_perf_bus(lq_rvs_perf_bus), + .lq_rvs_dbg_bus(lq_rvs_dbg_bus), + + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .func_sl_thold_1(func_sl_thold_1), + .sg_1(sg_1), + .clkoff_b(clkoff_dc_b), + .act_dis(act_dis), + .ccflush_dc(rp_rv_ccflush_dc), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr_dc[0]), + .mpw1_b(mpw1_dc_b[0]), + .mpw2_b(mpw2_dc_b), + .scan_in(siv[rv_lq_rvs_offset]), + .scan_out(sov[rv_lq_rvs_offset]) + ); + + // Bypass + assign rv_lq_vld = rv_byp_lq_vld; + + //------------------------------------------------------------------------------------------------------------ + // sq reservation station + //------------------------------------------------------------------------------------------------------------ + + //------------------------------------------------------------------------------------------------------------ + // br reservation station + //------------------------------------------------------------------------------------------------------------ + + //------------------------------------------------------------------------------------------------------------ + // axu0 reservation station + //------------------------------------------------------------------------------------------------------------ + + + rv_axu0_rvs + axu0_rvs( + .rv0_instr_i0_vld(rv0_axu0_instr_i0_vld), + .rv0_instr_i0_rte_axu0(rv0_axu0_instr_i0_rte_axu0), + .rv0_instr_i1_vld(rv0_axu0_instr_i1_vld), + .rv0_instr_i1_rte_axu0(rv0_axu0_instr_i1_rte_axu0), + .rv0_instr_i0_instr(rv0_axu0_instr_i0_instr), + .rv0_instr_i0_ucode(rv0_axu0_instr_i0_ucode), + .rv0_instr_i0_itag(rv0_axu0_instr_i0_itag), + .rv0_instr_i0_ord(rv0_axu0_instr_i0_ord), + .rv0_instr_i0_cord(rv0_axu0_instr_i0_cord), + .rv0_instr_i0_t1_v(rv0_axu0_instr_i0_t1_v), + .rv0_instr_i0_t1_p(rv0_axu0_instr_i0_t1_p), + .rv0_instr_i0_t2_p(rv0_axu0_instr_i0_t2_p), + .rv0_instr_i0_t3_p(rv0_axu0_instr_i0_t3_p), + .rv0_instr_i0_s1_v(rv0_axu0_instr_i0_s1_v), + .rv0_instr_i0_s1_p(rv0_axu0_instr_i0_s1_p), + .rv0_instr_i0_s2_v(rv0_axu0_instr_i0_s2_v), + .rv0_instr_i0_s2_p(rv0_axu0_instr_i0_s2_p), + .rv0_instr_i0_s3_v(rv0_axu0_instr_i0_s3_v), + .rv0_instr_i0_s3_p(rv0_axu0_instr_i0_s3_p), + .rv0_instr_i0_spare(rv0_axu0_instr_i0_spare), + .rv0_instr_i0_isStore(rv0_axu0_instr_i0_isStore), + .rv0_instr_i1_instr(rv0_axu0_instr_i1_instr), + .rv0_instr_i1_ucode(rv0_axu0_instr_i1_ucode), + .rv0_instr_i1_itag(rv0_axu0_instr_i1_itag), + .rv0_instr_i1_ord(rv0_axu0_instr_i1_ord), + .rv0_instr_i1_cord(rv0_axu0_instr_i1_cord), + .rv0_instr_i1_t1_v(rv0_axu0_instr_i1_t1_v), + .rv0_instr_i1_t1_p(rv0_axu0_instr_i1_t1_p), + .rv0_instr_i1_t2_p(rv0_axu0_instr_i1_t2_p), + .rv0_instr_i1_t3_p(rv0_axu0_instr_i1_t3_p), + .rv0_instr_i1_s1_v(rv0_axu0_instr_i1_s1_v), + .rv0_instr_i1_s1_p(rv0_axu0_instr_i1_s1_p), + .rv0_instr_i1_s2_v(rv0_axu0_instr_i1_s2_v), + .rv0_instr_i1_s2_p(rv0_axu0_instr_i1_s2_p), + .rv0_instr_i1_s3_v(rv0_axu0_instr_i1_s3_v), + .rv0_instr_i1_s3_p(rv0_axu0_instr_i1_s3_p), + .rv0_instr_i1_isStore(rv0_axu0_instr_i1_isStore), + .rv0_instr_i1_spare(rv0_axu0_instr_i1_spare), + .rv0_instr_i0_s1_dep_hit(rv0_axu0_instr_i0_s1_dep_hit), + .rv0_instr_i0_s1_itag(rv0_axu0_instr_i0_s1_itag), + .rv0_instr_i0_s2_dep_hit(rv0_axu0_instr_i0_s2_dep_hit), + .rv0_instr_i0_s2_itag(rv0_axu0_instr_i0_s2_itag), + .rv0_instr_i0_s3_dep_hit(rv0_axu0_instr_i0_s3_dep_hit), + .rv0_instr_i0_s3_itag(rv0_axu0_instr_i0_s3_itag), + .rv0_instr_i1_s1_dep_hit(rv0_axu0_instr_i1_s1_dep_hit), + .rv0_instr_i1_s1_itag(rv0_axu0_instr_i1_s1_itag), + .rv0_instr_i1_s2_dep_hit(rv0_axu0_instr_i1_s2_dep_hit), + .rv0_instr_i1_s2_itag(rv0_axu0_instr_i1_s2_itag), + .rv0_instr_i1_s3_dep_hit(rv0_axu0_instr_i1_s3_dep_hit), + .rv0_instr_i1_s3_itag(rv0_axu0_instr_i1_s3_itag), + .rv_iu_axu0_credit_free(rv_iu_axu0_credit_free), + .axu0_rv_ord_complete(axu0_rv_ord_complete), + .axu0_rv_hold_all(axu0_rv_hold_all), + .cp_flush(cp_flush), + .cp_next_itag(cp_next_itag), + .rv_axu0_vld(rv_axu0_vld), + .rv_axu0_s1_v(rv_axu0_s1_v), + .rv_axu0_s1_p(rv_axu0_s1_p), + .rv_axu0_s2_v(rv_axu0_s2_v), + .rv_axu0_s2_p(rv_axu0_s2_p), + .rv_axu0_s3_v(rv_axu0_s3_v), + .rv_axu0_s3_p(rv_axu0_s3_p), + + .rv_axu0_ex0_itag(rv_axu0_ex0_itag), + .rv_axu0_ex0_instr(rv_axu0_ex0_instr), + .rv_axu0_ex0_ucode(rv_axu0_ex0_ucode), + .rv_axu0_ex0_t1_v(rv_axu0_ex0_t1_v), + .rv_axu0_ex0_t1_p(rv_axu0_ex0_t1_p), + .rv_axu0_ex0_t2_p(rv_axu0_ex0_t2_p), + .rv_axu0_ex0_t3_p(rv_axu0_ex0_t3_p), + + .fx0_rv_ext_itag_vld(fx0_rv_ext_itag_vld), + .fx0_rv_ext_itag(fx0_rv_ext_itag), + .fx1_rv_ext_itag_vld(fx1_rv_ext_itag_vld), + .fx1_rv_ext_itag(fx1_rv_ext_itag), + .axu0_rv_itag_vld(axu0_rv_itag_vld), + .axu0_rv_itag(axu0_rv_itag), + .axu1_rv_itag_vld(axu1_rv_itag_vld), + .axu1_rv_itag(axu1_rv_itag), + .lq_rv_ext_itag0_vld(lq_rv_ext_itag0_vld), + .lq_rv_ext_itag0(lq_rv_ext_itag0), + + .lq_rv_itag1_vld(lq_rv_itag1_vld), + .lq_rv_itag1(lq_rv_itag1), + .lq_rv_itag1_restart(lq_rv_itag1_restart), + .lq_rv_itag1_hold(lq_rv_itag1_hold), + .lq_rv_ext_itag1_vld(lq_rv_ext_itag1_vld), + .lq_rv_ext_itag1(lq_rv_ext_itag1), + .lq_rv_ext_itag2_vld(lq_rv_ext_itag2_vld), + .lq_rv_ext_itag2(lq_rv_ext_itag2), + .lq_rv_clr_hold(lq_rv_clr_hold), + + .axu0_rv_ex2_s1_abort(axu0_rv_ex2_s1_abort), + .axu0_rv_ex2_s2_abort(axu0_rv_ex2_s2_abort), + .axu0_rv_ex2_s3_abort(axu0_rv_ex2_s3_abort), + + .fx0_rv_ext_itag_abort(fx0_rv_ext_itag_abort), + .fx1_rv_ext_itag_abort(fx1_rv_ext_itag_abort), + .lq_rv_ext_itag0_abort(lq_rv_ext_itag0_abort), + .lq_rv_ext_itag1_abort(lq_rv_ext_itag1_abort), + .axu0_rv_itag_abort(axu0_rv_itag_abort), + .axu1_rv_itag_abort(axu1_rv_itag_abort), + + .axu0_rv_ext_itag_vld(axu0_rv_ext_itag_vld), + .axu0_rv_ext_itag(axu0_rv_ext_itag), + .axu0_rv_ext_itag_abort(axu0_rv_ext_itag_abort), + .axu0_rvs_perf_bus(axu0_rvs_perf_bus), + .axu0_rvs_dbg_bus(axu0_rvs_dbg_bus), + + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .func_sl_thold_1(func_sl_thold_1), + .sg_1(sg_1), + .clkoff_b(clkoff_dc_b), + .act_dis(act_dis), + .ccflush_dc(rp_rv_ccflush_dc), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr_dc[0]), + .mpw1_b(mpw1_dc_b[0]), + .mpw2_b(mpw2_dc_b), + .scan_in(siv[rv_axu0_rvs_offset]), + .scan_out(sov[rv_axu0_rvs_offset]) + ); + + //------------------------------------------------------------------------------------------------------------ + // axu1 reservation station + //------------------------------------------------------------------------------------------------------------ + // reserved + assign rv_iu_axu1_credit_free = {`THREADS{1'b0}}; + + assign axu1_rv_ext_itag_vld = axu1_rv_itag_vld; + assign axu1_rv_ext_itag = axu1_rv_itag; + assign axu1_rv_ext_itag_abort = axu1_rv_itag_abort; + + //------------------------------------------------------------------------------------------------------------ + // LQ Regfile + //------------------------------------------------------------------------------------------------------------ + assign w_data_in_1 = {xu0_gpr_ex6_wd[64 - `GPR_WIDTH:63 + (`GPR_WIDTH/8)], 6'b000000}; + assign w_data_in_2 = {lq_rv_gpr_ex6_wd[64 - `GPR_WIDTH:63 + (`GPR_WIDTH/8)], 6'b000000}; + assign w_data_in_3 = {lq_rv_gpr_rel_wd[64 - `GPR_WIDTH:63 + (`GPR_WIDTH/8)], 6'b000000}; + assign w_data_in_4 = {xu1_gpr_ex3_wd[64 - `GPR_WIDTH:63 + (`GPR_WIDTH/8)], 6'b000000}; + + assign rv_lq_gpr_ex1_r0d = r_data_out_1[64 - `GPR_WIDTH:63 + (`GPR_WIDTH/8)]; + assign rv_lq_gpr_ex1_r1d = r_data_out_2[64 - `GPR_WIDTH:63 + (`GPR_WIDTH/8)]; + + generate + if (`THREADS == 2) + begin : tp2 + assign rv_lq_gpr_s1_p = {rv_byp_lq_s1_p, rv_byp_lq_vld[1]}; + assign rv_lq_gpr_s2_p = {rv_byp_lq_s2_p, rv_byp_lq_vld[1]}; + end + endgenerate + + generate + if (`THREADS == 1) + begin : tp1 + assign rv_lq_gpr_s1_p = rv_byp_lq_s1_p; + assign rv_lq_gpr_s2_p = rv_byp_lq_s2_p; + end + endgenerate + + tri_144x78_2r4w + lqrf( + .nclk(nclk), + .vdd(vdd), + .gnd(gnd), + .delay_lclkr_dc(delay_lclkr_dc[0]), + .mpw1_dc_b(mpw1_dc_b[0]), + .mpw2_dc_b(mpw2_dc_b), + .func_sl_force(force_t), + .func_sl_thold_0_b(chip_b_sl_2_thold_0_b), + .func_slp_sl_force(force_t), + .func_slp_sl_thold_0_b(chip_b_sl_2_thold_0_b), + .sg_0(sg_1), + .scan_in(lqrf_si), + .scan_out(lqrf_so), + .r_late_en_1(rv_byp_lq_s1_v), + .r_addr_in_1(rv_lq_gpr_s1_p), + .r_data_out_1(r_data_out_1), + .r_late_en_2(rv_byp_lq_s2_v), + .r_addr_in_2(rv_lq_gpr_s2_p), + .r_data_out_2(r_data_out_2), + .w_late_en_1(xu0_gpr_ex6_we), + .w_addr_in_1(xu0_gpr_ex6_wa), + .w_data_in_1(w_data_in_1), + .w_late_en_2(lq_rv_gpr_ex6_we), + .w_addr_in_2(lq_rv_gpr_ex6_wa), + .w_data_in_2(w_data_in_2), + .w_late_en_3(lq_rv_gpr_rel_we), + .w_addr_in_3(lq_rv_gpr_rel_wa), + .w_data_in_3(w_data_in_3), + .w_late_en_4(xu1_gpr_ex3_we), + .w_addr_in_4(xu1_gpr_ex3_wa), + .w_data_in_4(w_data_in_4) + ); + + //------------------------------------------------------------------------------------------------------------ + // RF GPR Bypass Control + //------------------------------------------------------------------------------------------------------------ + + rv_rf_byp + rf_byp( + .cp_flush(cp_flush), + .rv_byp_fx0_vld(rv_byp_fx0_vld), + .rv_byp_fx0_itag(rv_byp_fx0_itag), + .rv_byp_fx0_ilat(rv_byp_fx0_ilat), + .rv_byp_fx0_ord(rv_byp_fx0_ord), + .rv_byp_fx0_t1_v(rv_byp_fx0_t1_v), + .rv_byp_fx0_t1_t(rv_byp_fx0_t1_t), + .rv_byp_fx0_t2_v(rv_byp_fx0_t2_v), + .rv_byp_fx0_t2_t(rv_byp_fx0_t2_t), + .rv_byp_fx0_t3_v(rv_byp_fx0_t3_v), + .rv_byp_fx0_t3_t(rv_byp_fx0_t3_t), + .rv_byp_fx0_s1_t(rv_byp_fx0_s1_t), + .rv_byp_fx0_s2_t(rv_byp_fx0_s2_t), + .rv_byp_fx0_s3_t(rv_byp_fx0_s3_t), + .rv_byp_fx0_ex0_is_brick(rv_byp_fx0_ex0_is_brick), + .rv_byp_lq_vld(rv_byp_lq_vld), + .rv_byp_lq_t1_v(rv_byp_lq_t1_v), + .rv_byp_lq_t3_v(rv_byp_lq_t3_v), + .rv_byp_lq_t3_t(rv_byp_lq_t3_t), + .rv_byp_lq_s1_t(rv_byp_lq_s1_t), + .rv_byp_lq_s2_t(rv_byp_lq_s2_t), + .rv_byp_lq_ex0_s1_itag(rv_byp_lq_ex0_s1_itag), + .rv_byp_lq_ex0_s2_itag(rv_byp_lq_ex0_s2_itag), + .rv_byp_fx1_vld(rv_byp_fx1_vld), + .rv_byp_fx1_itag(rv_byp_fx1_itag), + .rv_byp_fx1_ilat(rv_byp_fx1_ilat), + .rv_byp_fx1_t1_v(rv_byp_fx1_t1_v), + .rv_byp_fx1_t2_v(rv_byp_fx1_t2_v), + .rv_byp_fx1_t3_v(rv_byp_fx1_t3_v), + .rv_byp_fx1_s1_t(rv_byp_fx1_s1_t), + .rv_byp_fx1_s2_t(rv_byp_fx1_s2_t), + .rv_byp_fx1_s3_t(rv_byp_fx1_s3_t), + .rv_byp_fx1_ex0_isStore(rv_byp_fx1_ex0_isStore), + .rv_fx0_ex0_s1_fx0_sel(rv_fx0_ex0_s1_fx0_sel), + .rv_fx0_ex0_s2_fx0_sel(rv_fx0_ex0_s2_fx0_sel), + .rv_fx0_ex0_s3_fx0_sel(rv_fx0_ex0_s3_fx0_sel), + .rv_fx0_ex0_s1_lq_sel(rv_fx0_ex0_s1_lq_sel), + .rv_fx0_ex0_s2_lq_sel(rv_fx0_ex0_s2_lq_sel), + .rv_fx0_ex0_s3_lq_sel(rv_fx0_ex0_s3_lq_sel), + .rv_fx0_ex0_s1_fx1_sel(rv_fx0_ex0_s1_fx1_sel), + .rv_fx0_ex0_s2_fx1_sel(rv_fx0_ex0_s2_fx1_sel), + .rv_fx0_ex0_s3_fx1_sel(rv_fx0_ex0_s3_fx1_sel), + .rv_lq_ex0_s1_fx0_sel(rv_lq_ex0_s1_fx0_sel), + .rv_lq_ex0_s2_fx0_sel(rv_lq_ex0_s2_fx0_sel), + .rv_lq_ex0_s1_lq_sel(rv_lq_ex0_s1_lq_sel), + .rv_lq_ex0_s2_lq_sel(rv_lq_ex0_s2_lq_sel), + .rv_lq_ex0_s1_fx1_sel(rv_lq_ex0_s1_fx1_sel), + .rv_lq_ex0_s2_fx1_sel(rv_lq_ex0_s2_fx1_sel), + .rv_fx1_ex0_s1_fx0_sel(rv_fx1_ex0_s1_fx0_sel), + .rv_fx1_ex0_s2_fx0_sel(rv_fx1_ex0_s2_fx0_sel), + .rv_fx1_ex0_s3_fx0_sel(rv_fx1_ex0_s3_fx0_sel), + .rv_fx1_ex0_s1_lq_sel(rv_fx1_ex0_s1_lq_sel), + .rv_fx1_ex0_s2_lq_sel(rv_fx1_ex0_s2_lq_sel), + .rv_fx1_ex0_s3_lq_sel(rv_fx1_ex0_s3_lq_sel), + .rv_fx1_ex0_s1_fx1_sel(rv_fx1_ex0_s1_fx1_sel), + .rv_fx1_ex0_s2_fx1_sel(rv_fx1_ex0_s2_fx1_sel), + .rv_fx1_ex0_s3_fx1_sel(rv_fx1_ex0_s3_fx1_sel), + + .rv_fx0_ex0_s1_rel_sel(rv_fx0_ex0_s1_rel_sel), + .rv_fx0_ex0_s2_rel_sel(rv_fx0_ex0_s2_rel_sel), + .rv_fx0_ex0_s3_rel_sel(rv_fx0_ex0_s3_rel_sel), + .rv_lq_ex0_s1_rel_sel(rv_lq_ex0_s1_rel_sel), + .rv_lq_ex0_s2_rel_sel(rv_lq_ex0_s2_rel_sel), + .rv_fx1_ex0_s1_rel_sel(rv_fx1_ex0_s1_rel_sel), + .rv_fx1_ex0_s2_rel_sel(rv_fx1_ex0_s2_rel_sel), + .rv_fx1_ex0_s3_rel_sel(rv_fx1_ex0_s3_rel_sel), + + //------------------------------------------------------------------- + // FX0 RV Release + //------------------------------------------------------------------- + .fx0_rv_itag_vld(fx0_rv_itag_vld), + .fx0_rv_itag_abort(fx0_rv_itag_abort), + .fx0_rv_itag(fx0_rv_itag), + .fx0_rv_ext_itag_vld(fx0_rv_ext_itag_vld), + .fx0_rv_ext_itag_abort(fx0_rv_ext_itag_abort), + .fx0_rv_ext_itag(fx0_rv_ext_itag), + + .fx0_rv_ord_complete(fx0_rv_ord_complete), + .fx0_rv_ord_itag(fx0_rv_ord_itag), + + .rv_fx0_s1_itag(rv_byp_fx0_s1_itag), + .rv_fx0_s2_itag(rv_byp_fx0_s2_itag), + .rv_fx0_s3_itag(rv_byp_fx0_s3_itag), + + .rv_byp_fx0_ilat0_vld(rv_byp_fx0_ilat0_vld), + .rv_byp_fx1_ilat0_vld(rv_byp_fx1_ilat0_vld), + .rv_byp_fx0_ilat1_vld(rv_byp_fx0_ilat1_vld), + .rv_byp_fx1_ilat1_vld(rv_byp_fx1_ilat1_vld), + .fx0_release_ord_hold(fx0_release_ord_hold), + .fx0_rv_ord_tid(fx0_rv_ord_tid), + + .fx0_rv_ex2_s1_abort(fx0_rv_ex2_s1_abort), + .fx0_rv_ex2_s2_abort(fx0_rv_ex2_s2_abort), + .fx0_rv_ex2_s3_abort(fx0_rv_ex2_s3_abort), + + //------------------------------------------------------------------- + // FX1 RV Release + //------------------------------------------------------------------- + .fx1_rv_itag_vld(fx1_rv_itag_vld), + .fx1_rv_itag_abort(fx1_rv_itag_abort), + .fx1_rv_itag(fx1_rv_itag), + .fx1_rv_ext_itag_vld(fx1_rv_ext_itag_vld), + .fx1_rv_ext_itag_abort(fx1_rv_ext_itag_abort), + .fx1_rv_ext_itag(fx1_rv_ext_itag), + + .rv_fx1_s1_itag(rv_byp_fx1_s1_itag), + .rv_fx1_s2_itag(rv_byp_fx1_s2_itag), + .rv_fx1_s3_itag(rv_byp_fx1_s3_itag), + + .fx1_rv_ex2_s1_abort(fx1_rv_ex2_s1_abort), + .fx1_rv_ex2_s2_abort(fx1_rv_ex2_s2_abort), + .fx1_rv_ex2_s3_abort(fx1_rv_ex2_s3_abort), + + //------------------------------------------------------------------- + // LQ RV Release + //------------------------------------------------------------------- + .rv_byp_lq_itag(rv_byp_lq_itag), + + //------------------------------------------------------------------- + // LQ RV REL Release + //------------------------------------------------------------------- + .lq_rv_itag2_vld(lq_rv_itag2_vld), + .lq_rv_itag2(lq_rv_itag2), + + //------------------------------------------------------------------- + // Pervasive + //------------------------------------------------------------------- + .nclk(nclk), + .vdd(vdd), + .gnd(gnd), + + .func_sl_thold_1(func_sl_thold_1), + .sg_1(sg_1), + .clkoff_b(clkoff_dc_b), + .act_dis(act_dis), + .ccflush_dc(rp_rv_ccflush_dc), + .delay_lclkr(delay_lclkr_dc[0]), + .mpw1_b(mpw1_dc_b[0]), + .mpw2_b(mpw2_dc_b), + + .scan_in(siv[rv_rf_byp_offset]), + .scan_out(sov[rv_rf_byp_offset]) + ); + + //------------------------------------------------------------------------------------------------------------ + // RV Pervasive + //------------------------------------------------------------------------------------------------------------ + + rv_perv + prv( + .nclk(nclk), + .vdd(vdd), + .gnd(gnd), + .rp_rv_ccflush_dc(rp_rv_ccflush_dc), + .rp_rv_func_sl_thold_3(rp_rv_func_sl_thold_3), + .rp_rv_gptr_sl_thold_3(rp_rv_gptr_sl_thold_3), + .rp_rv_sg_3(rp_rv_sg_3), + .rp_rv_fce_3(rp_rv_fce_3), + .an_ac_scan_diag_dc(an_ac_scan_diag_dc), + .an_ac_scan_dis_dc_b(an_ac_scan_dis_dc_b), + .func_sl_thold_1(func_sl_thold_1), + .fce_1(fce_1), + .sg_1(sg_1), + .clkoff_dc_b(clkoff_dc_b), + .act_dis(act_dis), + .d_mode(d_mode), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .gptr_scan_in(gptr_scan_in), + .gptr_scan_out(gptr_scan_out), + .scan_in(siv[perv_func_offset]), + .scan_out(sov[perv_func_offset]), + + .fx0_rvs_perf_bus(fx0_rvs_perf_bus), + .fx0_rvs_dbg_bus(fx0_rvs_dbg_bus), + .fx1_rvs_perf_bus(fx1_rvs_perf_bus), + .fx1_rvs_dbg_bus(fx1_rvs_dbg_bus), + .lq_rvs_perf_bus(lq_rvs_perf_bus), + .lq_rvs_dbg_bus(lq_rvs_dbg_bus), + .axu0_rvs_perf_bus(axu0_rvs_perf_bus), + .axu0_rvs_dbg_bus(axu0_rvs_dbg_bus), + .pc_rv_trace_bus_enable(pc_rv_trace_bus_enable), + .pc_rv_debug_mux_ctrls(pc_rv_debug_mux_ctrls), + .pc_rv_event_bus_enable(pc_rv_event_bus_enable), + .pc_rv_event_count_mode(pc_rv_event_count_mode), + .pc_rv_event_mux_ctrls(pc_rv_event_mux_ctrls), + .rv_event_bus_in(rv_event_bus_in), + .rv_event_bus_out(rv_event_bus_out), + .spr_msr_gs(spr_msr_gs), + .spr_msr_pr(spr_msr_pr), + .debug_bus_out(debug_bus_out), + .coretrace_ctrls_out(coretrace_ctrls_out), + .debug_bus_in(debug_bus_in), + .coretrace_ctrls_in(coretrace_ctrls_in) + + ); + + //todo + assign lqrf_si = 1'b0; + assign gptr_scan_in = 1'b0; + + assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in}; + assign scan_out = sov[0]; + +endmodule // rv diff --git a/dev/verilog/work/rv_axu0_rvs.v b/dev/verilog/work/rv_axu0_rvs.v new file mode 100755 index 0000000..c8cad30 --- /dev/null +++ b/dev/verilog/work/rv_axu0_rvs.v @@ -0,0 +1,991 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//----------------------------------------------------------------------------------------------------- +// Title: rv_axu0_rvs.vhdl +// Desc: LQ Reservation Station +// +//----------------------------------------------------------------------------------------------------- + +module rv_axu0_rvs( +`include "tri_a2o.vh" + + //------------------------------------------------------------------------------------------------------------ + // Instructions from RV_DEP + //------------------------------------------------------------------------------------------------------------ + input [0:`THREADS-1] rv0_instr_i0_vld, + input rv0_instr_i0_rte_axu0, + input [0:`THREADS-1] rv0_instr_i1_vld, + input rv0_instr_i1_rte_axu0, + + input [0:31] rv0_instr_i0_instr, + input [0:2] rv0_instr_i0_ucode, + input [0:`ITAG_SIZE_ENC-1] rv0_instr_i0_itag, + input rv0_instr_i0_ord, + input rv0_instr_i0_cord, + input rv0_instr_i0_t1_v, + input [0:`GPR_POOL_ENC-1] rv0_instr_i0_t1_p, + input [0:`GPR_POOL_ENC-1] rv0_instr_i0_t2_p, + input [0:`GPR_POOL_ENC-1] rv0_instr_i0_t3_p, + input rv0_instr_i0_s1_v, + input [0:`GPR_POOL_ENC-1] rv0_instr_i0_s1_p, + input rv0_instr_i0_s2_v, + input [0:`GPR_POOL_ENC-1] rv0_instr_i0_s2_p, + input rv0_instr_i0_s3_v, + input [0:`GPR_POOL_ENC-1] rv0_instr_i0_s3_p, + input rv0_instr_i0_isStore, + input [0:3] rv0_instr_i0_spare, + + input [0:31] rv0_instr_i1_instr, + input [0:2] rv0_instr_i1_ucode, + input [0:`ITAG_SIZE_ENC-1] rv0_instr_i1_itag, + input rv0_instr_i1_ord, + input rv0_instr_i1_cord, + input rv0_instr_i1_t1_v, + input [0:`GPR_POOL_ENC-1] rv0_instr_i1_t1_p, + input [0:`GPR_POOL_ENC-1] rv0_instr_i1_t2_p, + input [0:`GPR_POOL_ENC-1] rv0_instr_i1_t3_p, + input rv0_instr_i1_s1_v, + input [0:`GPR_POOL_ENC-1] rv0_instr_i1_s1_p, + input rv0_instr_i1_s2_v, + input [0:`GPR_POOL_ENC-1] rv0_instr_i1_s2_p, + input rv0_instr_i1_s3_v, + input [0:`GPR_POOL_ENC-1] rv0_instr_i1_s3_p, + input rv0_instr_i1_isStore, + input [0:3] rv0_instr_i1_spare, + + input rv0_instr_i0_s1_dep_hit, + input [0:`ITAG_SIZE_ENC-1] rv0_instr_i0_s1_itag, + input rv0_instr_i0_s2_dep_hit, + input [0:`ITAG_SIZE_ENC-1] rv0_instr_i0_s2_itag, + input rv0_instr_i0_s3_dep_hit, + input [0:`ITAG_SIZE_ENC-1] rv0_instr_i0_s3_itag, + + input rv0_instr_i1_s1_dep_hit, + input [0:`ITAG_SIZE_ENC-1] rv0_instr_i1_s1_itag, + input rv0_instr_i1_s2_dep_hit, + input [0:`ITAG_SIZE_ENC-1] rv0_instr_i1_s2_itag, + input rv0_instr_i1_s3_dep_hit, + input [0:`ITAG_SIZE_ENC-1] rv0_instr_i1_s3_itag, + + //------------------------------------------------------------------------------------------------------------ + // Credit Interface with IU + //------------------------------------------------------------------------------------------------------------ + output [0:`THREADS-1] rv_iu_axu0_credit_free, + + //------------------------------------------------------------------------------------------------------------ + // Machine zap interface + //------------------------------------------------------------------------------------------------------------ + input [0:`THREADS-1] cp_flush, + input [0:`THREADS*`ITAG_SIZE_ENC-1] cp_next_itag, + + //------------------------------------------------------------------------------------------------------------ + // Interface to axu0 + //------------------------------------------------------------------------------------------------------------ + output [0:`THREADS-1] rv_axu0_vld, + output rv_axu0_s1_v, + output [0:`GPR_POOL_ENC-1] rv_axu0_s1_p, + output rv_axu0_s2_v, + output [0:`GPR_POOL_ENC-1] rv_axu0_s2_p, + output rv_axu0_s3_v, + output [0:`GPR_POOL_ENC-1] rv_axu0_s3_p, + + output [0:`ITAG_SIZE_ENC-1] rv_axu0_ex0_itag, + output [0:31] rv_axu0_ex0_instr, + output [0:2] rv_axu0_ex0_ucode, + output rv_axu0_ex0_t1_v, + output [0:`GPR_POOL_ENC-1] rv_axu0_ex0_t1_p, + output [0:`GPR_POOL_ENC-1] rv_axu0_ex0_t2_p, + output [0:`GPR_POOL_ENC-1] rv_axu0_ex0_t3_p, + + input axu0_rv_ord_complete, + input axu0_rv_hold_all, + + //------------------------------------------------------------------------------------------------------------ + // RV Release bus + //------------------------------------------------------------------------------------------------------------ + + input axu0_rv_ex2_s1_abort, + input axu0_rv_ex2_s2_abort, + input axu0_rv_ex2_s3_abort, + + input fx0_rv_ext_itag_abort, + input fx1_rv_ext_itag_abort, + input lq_rv_ext_itag0_abort, + input lq_rv_ext_itag1_abort, + input axu0_rv_itag_abort, + input axu1_rv_itag_abort, + + input [0:`THREADS-1] fx0_rv_ext_itag_vld, + input [0:`ITAG_SIZE_ENC-1] fx0_rv_ext_itag, + + input [0:`THREADS-1] fx1_rv_ext_itag_vld, + input [0:`ITAG_SIZE_ENC-1] fx1_rv_ext_itag, + + input [0:`THREADS-1] axu0_rv_itag_vld, + input [0:`ITAG_SIZE_ENC-1] axu0_rv_itag, + + input [0:`THREADS-1] axu1_rv_itag_vld, + input [0:`ITAG_SIZE_ENC-1] axu1_rv_itag, + + input [0:`THREADS-1] lq_rv_ext_itag0_vld, + input [0:`ITAG_SIZE_ENC-1] lq_rv_ext_itag0, + + input [0:`THREADS-1] lq_rv_itag1_vld, + input [0:`ITAG_SIZE_ENC-1] lq_rv_itag1, + input lq_rv_itag1_restart, + input lq_rv_itag1_hold, + input [0:`THREADS-1] lq_rv_ext_itag1_vld, + input [0:`ITAG_SIZE_ENC-1] lq_rv_ext_itag1, + + input [0:`THREADS-1] lq_rv_ext_itag2_vld, + input [0:`ITAG_SIZE_ENC-1] lq_rv_ext_itag2, + + input [0:`THREADS-1] lq_rv_clr_hold, + + output [0:`THREADS-1] axu0_rv_ext_itag_vld, + output axu0_rv_ext_itag_abort, + output [0:`ITAG_SIZE_ENC-1] axu0_rv_ext_itag, + + //------------------------------------------------------------------------------------------------------------ + // Pervasive + //------------------------------------------------------------------------------------------------------------ + output [0:8*`THREADS-1] axu0_rvs_perf_bus, + output [0:31] axu0_rvs_dbg_bus, + + inout vdd, + inout gnd, + (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) // nclk + input [0:`NCLK_WIDTH-1] nclk, + input func_sl_thold_1, + input sg_1, + input clkoff_b, + input act_dis, + input ccflush_dc, + input d_mode, + input delay_lclkr, + input mpw1_b, + input mpw2_b, + input scan_in, + + output scan_out + ); + + + + parameter num_itag_busses_g = 7; + + //------------------------------------------------------------------------------------------------------------ + // RV AXU0 RVS INSTR ISSUE + //------------------------------------------------------------------------------------------------------------ + parameter rvaxu0_ex0_start = 0; + + parameter rvaxu0_instr_start = rvaxu0_ex0_start; + parameter rvaxu0_instr_stop = (rvaxu0_instr_start + (32)) - 1; + parameter rvaxu0_ucode_start = rvaxu0_instr_stop + 1; + parameter rvaxu0_ucode_stop = (rvaxu0_ucode_start + (3)) - 1; + parameter rvaxu0_t1_v_start = rvaxu0_ucode_stop + 1; + parameter rvaxu0_t1_v_stop = (rvaxu0_t1_v_start + (1)) - 1; + parameter rvaxu0_t1_p_start = rvaxu0_t1_v_stop + 1; + parameter rvaxu0_t1_p_stop = (rvaxu0_t1_p_start + (`GPR_POOL_ENC)) - 1; + parameter rvaxu0_t2_p_start = rvaxu0_t1_p_stop + 1; + parameter rvaxu0_t2_p_stop = (rvaxu0_t2_p_start + (`GPR_POOL_ENC)) - 1; + parameter rvaxu0_t3_p_start = rvaxu0_t2_p_stop + 1; + parameter rvaxu0_t3_p_stop = (rvaxu0_t3_p_start + (`GPR_POOL_ENC)) - 1; + parameter rvaxu0_spare_start = rvaxu0_t3_p_stop + 1; + parameter rvaxu0_spare_stop = (rvaxu0_spare_start + (4)) - 1; + + parameter rvaxu0_ex0_end = rvaxu0_spare_stop; + + parameter rvaxu0_ex0_size = rvaxu0_ex0_end + 1; + + parameter rvaxu0_start = 0; + parameter rvaxu0_s1_v_start = rvaxu0_start; + parameter rvaxu0_s1_v_stop = (rvaxu0_s1_v_start + (1)) - 1; + parameter rvaxu0_s1_p_start = rvaxu0_s1_v_stop + 1; + parameter rvaxu0_s1_p_stop = (rvaxu0_s1_p_start + (`GPR_POOL_ENC)) - 1; + parameter rvaxu0_s2_v_start = rvaxu0_s1_p_stop + 1; + parameter rvaxu0_s2_v_stop = (rvaxu0_s2_v_start + (1)) - 1; + parameter rvaxu0_s2_p_start = rvaxu0_s2_v_stop + 1; + parameter rvaxu0_s2_p_stop = (rvaxu0_s2_p_start + (`GPR_POOL_ENC)) - 1; + parameter rvaxu0_s3_v_start = rvaxu0_s2_p_stop + 1; + parameter rvaxu0_s3_v_stop = (rvaxu0_s3_v_start + (1)) - 1; + parameter rvaxu0_s3_p_start = rvaxu0_s3_v_stop + 1; + parameter rvaxu0_s3_p_stop = (rvaxu0_s3_p_start + (`GPR_POOL_ENC)) - 1; + + parameter rvaxu0_end = rvaxu0_s3_p_stop; + + parameter rvaxu0_size = rvaxu0_end + 1; + + + //------------------------------------------------------------------------------------------------------------ + // Pervasive + //------------------------------------------------------------------------------------------------------------ + + wire tiup; + wire [0:`THREADS-1] cp_flush_q; + + //------------------------------------------------------------------------------------------------------------ + // RV0 + //------------------------------------------------------------------------------------------------------------ + wire rv0_instr_i0_rte; + wire rv0_instr_i1_rte; + + //------------------------------------------------------------------------------------------------------------ + // RV1 + //------------------------------------------------------------------------------------------------------------ + wire [rvaxu0_start:rvaxu0_end] rv0_instr_i0_dat; + wire [rvaxu0_start:rvaxu0_end] rv0_instr_i1_dat; + wire [rvaxu0_ex0_start:rvaxu0_ex0_end] rv0_instr_i0_dat_ex0; + wire [rvaxu0_ex0_start:rvaxu0_ex0_end] rv0_instr_i1_dat_ex0; + + wire rv0_instr_i0_spec; + wire rv0_instr_i1_spec; + + wire rv0_instr_i0_is_brick; + wire [0:2] rv0_instr_i0_brick; + wire [0:3] rv0_instr_i0_ilat; + wire rv0_instr_i1_is_brick; + wire [0:2] rv0_instr_i1_brick; + wire [0:3] rv0_instr_i1_ilat; + + wire rv0_i0_s1_v; + wire rv0_i0_s2_v; + wire rv0_i1_s1_v; + wire rv0_i1_s2_v; + wire rv0_i0_s1_dep_hit; + wire rv0_i0_s2_dep_hit; + wire rv0_i1_s1_dep_hit; + wire rv0_i1_s2_dep_hit; + + //------------------------------------------------------------------------------------------------------------ + // RV2 + //------------------------------------------------------------------------------------------------------------ + wire [0:`THREADS-1] rv1_other_ilat0_vld; + wire [0:`ITAG_SIZE_ENC-1] rv1_other_ilat0_itag; + + wire [rvaxu0_start:rvaxu0_end] rv1_instr_dat; + wire [0:`THREADS-1] rv1_instr_v; + wire rv1_instr_ord; + (* analysis_not_referenced="true" *) + wire rv1_instr_spec; + wire [0:`ITAG_SIZE_ENC-1] rv1_instr_itag; + (* analysis_not_referenced="true" *) + wire [0:`ITAG_SIZE_ENC-1] rv1_instr_s1_itag; + (* analysis_not_referenced="true" *) + wire [0:`ITAG_SIZE_ENC-1] rv1_instr_s2_itag; + (* analysis_not_referenced="true" *) + wire [0:`ITAG_SIZE_ENC-1] rv1_instr_s3_itag; + (* analysis_not_referenced="<54:57>true" *) + wire [rvaxu0_ex0_start:rvaxu0_ex0_end] ex0_instr_dat; + wire [0:`THREADS-1] ex1_credit_free; + + wire ex0_ord_d; + wire ex0_ord_q; + wire [0:`THREADS-1] ex1_ord_vld_d; + wire [0:`THREADS-1] ex1_ord_vld_q; + wire [0:`THREADS-1] ex2_ord_vld_d; + wire [0:`THREADS-1] ex2_ord_vld_q; + wire [0:`THREADS-1] ex3_ord_flush_d; + wire [0:`THREADS-1] ex3_ord_flush_q; + + //------------------------------------------------------------------------------------------------------------ + // EX0 + //------------------------------------------------------------------------------------------------------------ + + wire rv_ex0_act; + + wire [0:`THREADS-1] ex0_vld_d; + wire [0:`ITAG_SIZE_ENC-1] ex0_itag_d; + + wire [0:`THREADS-1] ex0_vld_q; + wire [0:`ITAG_SIZE_ENC-1] ex0_itag_q; + + //------------------------------------------------------------------------------------------------------------ + // Itag busses and shadow + //------------------------------------------------------------------------------------------------------------ + + wire [0:`THREADS-1] lq_rv_itag1_rst_vld; + wire [0:`ITAG_SIZE_ENC-1] lq_rv_itag1_rst; + + wire [0:`THREADS-1] q_ord_complete; + wire [0:`THREADS-1] ex3_ord_flush; + + wire lq_rv_itag1_cord; + + wire [0:`THREADS*`ITAG_SIZE_ENC-1] cp_next_itag_q; + + + //------------------------------------------------------------------------------------------------------------ + // Scan Chains + //------------------------------------------------------------------------------------------------------------ + + parameter rvs_offset = 0 + 0; + parameter cp_flush_offset = rvs_offset + 1; + parameter ex0_ord_offset = cp_flush_offset + `THREADS; + parameter ex1_ord_vld_offset = ex0_ord_offset + 1; + parameter ex2_ord_vld_offset = ex1_ord_vld_offset + `THREADS; + parameter ex3_ord_flush_offset = ex2_ord_vld_offset + `THREADS; + parameter ex0_vld_offset = ex3_ord_flush_offset + `THREADS; + parameter ex0_itag_offset = ex0_vld_offset + `THREADS; + parameter axu0_rv_itag_vld_offset = ex0_itag_offset + `ITAG_SIZE_ENC; + parameter axu0_rv_itag_abort_offset = axu0_rv_itag_vld_offset + `THREADS; + parameter axu0_rv_itag_offset = axu0_rv_itag_abort_offset + 1; + parameter cp_next_itag_offset = axu0_rv_itag_offset + `ITAG_SIZE_ENC; + + parameter scan_right = cp_next_itag_offset + `THREADS * `ITAG_SIZE_ENC; + wire [0:scan_right-1] siv; + wire [0:scan_right-1] sov; + + wire func_sl_thold_0; + wire func_sl_thold_0_b; + wire sg_0; + wire force_t; + + //unused + (* analysis_not_referenced="true" *) + wire [0:`THREADS-1] q_ord_tid; + (* analysis_not_referenced="true" *) + wire [0:`THREADS-1] rv1_other_ilat0_vld_out; + (* analysis_not_referenced="true" *) + wire [0:`ITAG_SIZE_ENC-1] rv1_other_ilat0_itag_out; + (* analysis_not_referenced="true" *) + wire [0:3] rv1_instr_ilat; + (* analysis_not_referenced="true" *) + wire [0:`THREADS-1] rv1_instr_ilat0_vld; + (* analysis_not_referenced="true" *) + wire [0:`THREADS-1] rv1_instr_ilat1_vld; + (* analysis_not_referenced="true" *) + wire rvs_empty; + (* analysis_not_referenced="true" *) + wire rv1_instr_is_brick; + + + //------------------------------------------------------------------------------------------------------------ + // Pervasive + //------------------------------------------------------------------------------------------------------------ + assign tiup = 1'b1; + + //------------------------------------------------------------------------------------------------------------ + // RV Entry + //------------------------------------------------------------------------------------------------------------ + + //Don't hit on cracked store GPR valids + assign rv0_i0_s1_v = rv0_instr_i0_s1_v & ~rv0_instr_i0_isStore; + assign rv0_i0_s2_v = rv0_instr_i0_s2_v & ~rv0_instr_i0_isStore; + assign rv0_i0_s1_dep_hit = rv0_instr_i0_s1_dep_hit & ~rv0_instr_i0_isStore; + assign rv0_i0_s2_dep_hit = rv0_instr_i0_s2_dep_hit & ~rv0_instr_i0_isStore; + + assign rv0_i1_s1_v = rv0_instr_i1_s1_v & ~rv0_instr_i1_isStore; + assign rv0_i1_s2_v = rv0_instr_i1_s2_v & ~rv0_instr_i1_isStore; + assign rv0_i1_s1_dep_hit = rv0_instr_i1_s1_dep_hit & ~rv0_instr_i1_isStore; + assign rv0_i1_s2_dep_hit = rv0_instr_i1_s2_dep_hit & ~rv0_instr_i1_isStore; + + assign rv0_instr_i0_dat = { + rv0_i0_s1_v, + rv0_instr_i0_s1_p, + rv0_i0_s2_v, + rv0_instr_i0_s2_p, + rv0_instr_i0_s3_v, + rv0_instr_i0_s3_p}; + + assign rv0_instr_i0_dat_ex0 = {rv0_instr_i0_instr, + rv0_instr_i0_ucode, + rv0_instr_i0_t1_v, + rv0_instr_i0_t1_p, + rv0_instr_i0_t2_p, + rv0_instr_i0_t3_p, + rv0_instr_i0_spare}; + + assign rv0_instr_i1_dat = { + rv0_i1_s1_v, + rv0_instr_i1_s1_p, + rv0_i1_s2_v, + rv0_instr_i1_s2_p, + rv0_instr_i1_s3_v, + rv0_instr_i1_s3_p}; + + assign rv0_instr_i1_dat_ex0 = {rv0_instr_i1_instr, + rv0_instr_i1_ucode, + rv0_instr_i1_t1_v, + rv0_instr_i1_t1_p, + rv0_instr_i1_t2_p, + rv0_instr_i1_t3_p, + rv0_instr_i1_spare}; + + + //------------------------------------------------------------------------------------------------------------ + // axu0 Reservation Stations + //------------------------------------------------------------------------------------------------------------ + assign rv0_instr_i0_spec = 1'b0; + assign rv0_instr_i0_is_brick = 1'b0; + assign rv0_instr_i0_brick = {3{1'b0}}; + assign rv0_instr_i0_ilat = {4{1'b1}}; + assign rv0_instr_i1_spec = 1'b0; + assign rv0_instr_i1_is_brick = 1'b0; + assign rv0_instr_i1_brick = {3{1'b0}}; + assign rv0_instr_i1_ilat = {4{1'b1}}; + + assign lq_rv_itag1_cord = 1'b0; + + assign rv1_other_ilat0_vld = {`THREADS{1'b0}}; + assign rv1_other_ilat0_itag = {`ITAG_SIZE_ENC{1'b0}}; + + assign q_ord_complete = {`THREADS{axu0_rv_ord_complete}} | ex3_ord_flush; + + assign rv0_instr_i0_rte = rv0_instr_i0_rte_axu0; + assign rv0_instr_i1_rte = rv0_instr_i1_rte_axu0; + + + rv_station #(.q_dat_width_g(rvaxu0_size), .q_dat_ex0_width_g(rvaxu0_ex0_size), .q_num_entries_g(`RV_AXU0_ENTRIES), .q_itag_busses_g(num_itag_busses_g), .q_noilat0_g(1'b1), .q_brick_g(1'b0)) + rvs( + .cp_flush(cp_flush), + .cp_next_itag(cp_next_itag_q), + + .rv0_instr_i0_vld(rv0_instr_i0_vld), + .rv0_instr_i0_rte(rv0_instr_i0_rte), + .rv0_instr_i1_vld(rv0_instr_i1_vld), + .rv0_instr_i1_rte(rv0_instr_i1_rte), + + .rv0_instr_i0_dat(rv0_instr_i0_dat), + .rv0_instr_i0_dat_ex0(rv0_instr_i0_dat_ex0), + .rv0_instr_i0_itag(rv0_instr_i0_itag), + .rv0_instr_i0_ord(rv0_instr_i0_ord), + .rv0_instr_i0_cord(rv0_instr_i0_cord), + .rv0_instr_i0_spec(rv0_instr_i0_spec), + .rv0_instr_i0_s1_dep_hit(rv0_i0_s1_dep_hit), + .rv0_instr_i0_s1_itag(rv0_instr_i0_s1_itag), + .rv0_instr_i0_s2_dep_hit(rv0_i0_s2_dep_hit), + .rv0_instr_i0_s2_itag(rv0_instr_i0_s2_itag), + .rv0_instr_i0_s3_dep_hit(rv0_instr_i0_s3_dep_hit), + .rv0_instr_i0_s3_itag(rv0_instr_i0_s3_itag), + .rv0_instr_i0_is_brick(rv0_instr_i0_is_brick), + .rv0_instr_i0_brick(rv0_instr_i0_brick), + .rv0_instr_i0_ilat(rv0_instr_i0_ilat), + .rv0_instr_i0_s1_v(rv0_i0_s1_v), + .rv0_instr_i0_s2_v(rv0_i0_s2_v), + .rv0_instr_i0_s3_v(rv0_instr_i0_s3_v), + + .rv0_instr_i1_dat(rv0_instr_i1_dat), + .rv0_instr_i1_dat_ex0(rv0_instr_i1_dat_ex0), + .rv0_instr_i1_itag(rv0_instr_i1_itag), + .rv0_instr_i1_ord(rv0_instr_i1_ord), + .rv0_instr_i1_cord(rv0_instr_i1_cord), + .rv0_instr_i1_spec(rv0_instr_i1_spec), + .rv0_instr_i1_s1_dep_hit(rv0_i1_s1_dep_hit), + .rv0_instr_i1_s1_itag(rv0_instr_i1_s1_itag), + .rv0_instr_i1_s2_dep_hit(rv0_i1_s2_dep_hit), + .rv0_instr_i1_s2_itag(rv0_instr_i1_s2_itag), + .rv0_instr_i1_s3_dep_hit(rv0_instr_i1_s3_dep_hit), + .rv0_instr_i1_s3_itag(rv0_instr_i1_s3_itag), + .rv0_instr_i1_is_brick(rv0_instr_i1_is_brick), + .rv0_instr_i1_brick(rv0_instr_i1_brick), + .rv0_instr_i1_ilat(rv0_instr_i1_ilat), + .rv0_instr_i1_s1_v(rv0_i1_s1_v), + .rv0_instr_i1_s2_v(rv0_i1_s2_v), + .rv0_instr_i1_s3_v(rv0_instr_i1_s3_v), + + .rv1_instr_vld(rv1_instr_v), + .rv1_instr_dat(rv1_instr_dat), + .rv1_instr_ord(rv1_instr_ord), + .rv1_instr_spec(rv1_instr_spec), + .rv1_instr_itag(rv1_instr_itag), + .rv1_instr_s1_itag(rv1_instr_s1_itag), + .rv1_instr_s2_itag(rv1_instr_s2_itag), + .rv1_instr_s3_itag(rv1_instr_s3_itag), + .rv1_instr_is_brick(rv1_instr_is_brick), + .ex0_instr_dat(ex0_instr_dat), + .ex1_credit_free(ex1_credit_free), + + .rv1_other_ilat0_vld(rv1_other_ilat0_vld), + .rv1_other_ilat0_itag(rv1_other_ilat0_itag), + .q_ord_tid(q_ord_tid), + .rv1_other_ilat0_vld_out(rv1_other_ilat0_vld_out), + .rv1_other_ilat0_itag_out(rv1_other_ilat0_itag_out), + .rv1_instr_ilat(rv1_instr_ilat), + .rv1_instr_ilat0_vld(rv1_instr_ilat0_vld), + .rv1_instr_ilat1_vld(rv1_instr_ilat1_vld), + .rvs_empty(rvs_empty), + .rvs_perf_bus(axu0_rvs_perf_bus), + .rvs_dbg_bus(axu0_rvs_dbg_bus), + + .q_hold_all(axu0_rv_hold_all), + .q_ord_complete(q_ord_complete), + + .fx0_rv_itag (fx0_rv_ext_itag), + .fx1_rv_itag (fx1_rv_ext_itag), + .lq_rv_itag0 (lq_rv_ext_itag0), + .lq_rv_itag1 (lq_rv_ext_itag1), + .lq_rv_itag2 (lq_rv_ext_itag2), + .axu0_rv_itag (axu0_rv_itag), + .axu1_rv_itag (axu1_rv_itag), + .fx0_rv_itag_vld (fx0_rv_ext_itag_vld), + .fx1_rv_itag_vld (fx1_rv_ext_itag_vld), + .lq_rv_itag0_vld (lq_rv_ext_itag0_vld), + .lq_rv_itag1_vld (lq_rv_ext_itag1_vld), + .lq_rv_itag2_vld (lq_rv_ext_itag2_vld), + .axu0_rv_itag_vld (axu0_rv_itag_vld), + .axu1_rv_itag_vld (axu1_rv_itag_vld), + .fx0_rv_itag_abort (fx0_rv_ext_itag_abort), + .fx1_rv_itag_abort (fx1_rv_ext_itag_abort), + .lq_rv_itag0_abort (lq_rv_ext_itag0_abort), + .lq_rv_itag1_abort (lq_rv_ext_itag1_abort), + .axu0_rv_itag_abort (axu0_rv_itag_abort), + .axu1_rv_itag_abort (axu1_rv_itag_abort), + + .xx_rv_ex2_s1_abort(axu0_rv_ex2_s1_abort), + .xx_rv_ex2_s2_abort(axu0_rv_ex2_s2_abort), + .xx_rv_ex2_s3_abort(axu0_rv_ex2_s3_abort), + + + .lq_rv_itag1_restart(lq_rv_itag1_restart), + .lq_rv_itag1_hold(lq_rv_itag1_hold), + .lq_rv_itag1_cord(lq_rv_itag1_cord), + .lq_rv_itag1_rst_vld(lq_rv_itag1_rst_vld), + .lq_rv_itag1_rst(lq_rv_itag1_rst), + .lq_rv_clr_hold(lq_rv_clr_hold), + + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .sg_1(sg_1), + .func_sl_thold_1(func_sl_thold_1), + .ccflush_dc(ccflush_dc), + .act_dis(act_dis), + .clkoff_b(clkoff_b), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scan_in(siv[rvs_offset]), + .scan_out(sov[rvs_offset]) + ); + + assign rv_iu_axu0_credit_free = ex1_credit_free; + assign rv_axu0_vld = rv1_instr_v; + + assign rv_axu0_s1_v = rv1_instr_dat[rvaxu0_s1_v_start]; + assign rv_axu0_s1_p = rv1_instr_dat[rvaxu0_s1_p_start:rvaxu0_s1_p_stop]; + assign rv_axu0_s2_v = rv1_instr_dat[rvaxu0_s2_v_start]; + assign rv_axu0_s2_p = rv1_instr_dat[rvaxu0_s2_p_start:rvaxu0_s2_p_stop]; + assign rv_axu0_s3_v = rv1_instr_dat[rvaxu0_s3_v_start]; + assign rv_axu0_s3_p = rv1_instr_dat[rvaxu0_s3_p_start:rvaxu0_s3_p_stop]; + + assign ex0_vld_d = rv1_instr_v & (~cp_flush_q); + assign ex0_itag_d = rv1_instr_itag; + assign rv_axu0_ex0_instr = ex0_instr_dat[rvaxu0_instr_start:rvaxu0_instr_stop]; + assign rv_axu0_ex0_ucode = ex0_instr_dat[rvaxu0_ucode_start:rvaxu0_ucode_stop]; + assign rv_axu0_ex0_t1_v = ex0_instr_dat[rvaxu0_t1_v_start]; + assign rv_axu0_ex0_t1_p = ex0_instr_dat[rvaxu0_t1_p_start:rvaxu0_t1_p_stop]; + assign rv_axu0_ex0_t2_p = ex0_instr_dat[rvaxu0_t2_p_start:rvaxu0_t2_p_stop]; + assign rv_axu0_ex0_t3_p = ex0_instr_dat[rvaxu0_t3_p_start:rvaxu0_t3_p_stop]; + + assign rv_ex0_act = |(rv1_instr_v); + + assign rv_axu0_ex0_itag = ex0_itag_q; + + //------------------------------------------------------------------------------------------------------------ + // Itag busses + //------------------------------------------------------------------------------------------------------------ + + // Restart Itag and Valid from LQ. This is separate because it could be early (not latched) + assign lq_rv_itag1_rst_vld = lq_rv_itag1_vld; + assign lq_rv_itag1_rst = lq_rv_itag1; + + + + + assign ex0_ord_d = rv1_instr_ord; + assign ex1_ord_vld_d = {`THREADS{ex0_ord_q}} & ex0_vld_q & (~cp_flush_q); + assign ex2_ord_vld_d = ex1_ord_vld_q & (~cp_flush_q); + assign ex3_ord_flush_d = ex2_ord_vld_q & {`THREADS{(axu0_rv_ex2_s1_abort | axu0_rv_ex2_s2_abort | axu0_rv_ex2_s3_abort )}} ; + assign ex3_ord_flush = ex3_ord_flush_q & (~cp_flush_q); + + //------------------------------------------------------------------------------------------------------------ + // Pipeline Latches + //------------------------------------------------------------------------------------------------------------ + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) cp_flush_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[cp_flush_offset:cp_flush_offset + `THREADS - 1]), + .scout(sov[cp_flush_offset:cp_flush_offset + `THREADS - 1]), + .din(cp_flush), + .dout(cp_flush_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) ex0_ord_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rv_ex0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[ex0_ord_offset]), + .scout(sov[ex0_ord_offset]), + .din(ex0_ord_d), + .dout(ex0_ord_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) ex1_ord_vld_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[ex1_ord_vld_offset:ex1_ord_vld_offset + `THREADS - 1]), + .scout(sov[ex1_ord_vld_offset:ex1_ord_vld_offset + `THREADS - 1]), + .din(ex1_ord_vld_d), + .dout(ex1_ord_vld_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) ex2_ord_vld_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[ex2_ord_vld_offset:ex2_ord_vld_offset + `THREADS - 1]), + .scout(sov[ex2_ord_vld_offset:ex2_ord_vld_offset + `THREADS - 1]), + .din(ex2_ord_vld_d), + .dout(ex2_ord_vld_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) ex3_ord_flush_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[ex3_ord_flush_offset:ex3_ord_flush_offset + `THREADS - 1]), + .scout(sov[ex3_ord_flush_offset:ex3_ord_flush_offset + `THREADS - 1]), + .din(ex3_ord_flush_d), + .dout(ex3_ord_flush_q) + ); + + + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) ex0_vld_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[ex0_vld_offset:ex0_vld_offset + `THREADS - 1]), + .scout(sov[ex0_vld_offset:ex0_vld_offset + `THREADS - 1]), + .din(ex0_vld_d), + .dout(ex0_vld_q) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) ex0_itag_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rv_ex0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[ex0_itag_offset:ex0_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[ex0_itag_offset:ex0_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(ex0_itag_d), + .dout(ex0_itag_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) axu0_rv_itag_vld_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[axu0_rv_itag_vld_offset:axu0_rv_itag_vld_offset + `THREADS - 1]), + .scout(sov[axu0_rv_itag_vld_offset:axu0_rv_itag_vld_offset + `THREADS - 1]), + .din(axu0_rv_itag_vld), + .dout(axu0_rv_ext_itag_vld) + ); + + tri_rlmlatch_p #( .INIT(0)) axu0_rv_itag_abort_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[axu0_rv_itag_abort_offset]), + .scout(sov[axu0_rv_itag_abort_offset]), + .din(axu0_rv_itag_abort), + .dout(axu0_rv_ext_itag_abort) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) axu0_rv_itag_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[axu0_rv_itag_offset:axu0_rv_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[axu0_rv_itag_offset:axu0_rv_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(axu0_rv_itag), + .dout(axu0_rv_ext_itag) + ); + +/* + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) lq_rv_itag0_vld_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[lq_rv_itag0_vld_offset:lq_rv_itag0_vld_offset + `THREADS - 1]), + .scout(sov[lq_rv_itag0_vld_offset:lq_rv_itag0_vld_offset + `THREADS - 1]), + .din(lq_rv_itag0_vld_d), + .dout(lq_rv_itag0_vld_q) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) lq_rv_itag0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[lq_rv_itag0_offset:lq_rv_itag0_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[lq_rv_itag0_offset:lq_rv_itag0_offset + `ITAG_SIZE_ENC - 1]), + .din(lq_rv_itag0), + .dout(lq_rv_itag0_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) lq_rv_itag0_spec_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[lq_rv_itag0_spec_offset]), + .scout(sov[lq_rv_itag0_spec_offset]), + .din(lq_rv_itag0_spec), + .dout(lq_rv_itag0_spec_q) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) lq_rv_itag1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[lq_rv_itag1_offset:lq_rv_itag1_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[lq_rv_itag1_offset:lq_rv_itag1_offset + `ITAG_SIZE_ENC - 1]), + .din(lq_rv_itag1), + .dout(lq_rv_itag1_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) lq_rv_itag2_vld_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[lq_rv_itag2_vld_offset:lq_rv_itag2_vld_offset + `THREADS - 1]), + .scout(sov[lq_rv_itag2_vld_offset:lq_rv_itag2_vld_offset + `THREADS - 1]), + .din(lq_rv_itag2_vld_d), + .dout(lq_rv_itag2_vld_q) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) lq_rv_itag2_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[lq_rv_itag2_offset:lq_rv_itag2_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[lq_rv_itag2_offset:lq_rv_itag2_offset + `ITAG_SIZE_ENC - 1]), + .din(lq_rv_itag2), + .dout(lq_rv_itag2_q) + ); + */ + tri_rlmreg_p #(.WIDTH(`THREADS*`ITAG_SIZE_ENC), .INIT(0)) + cp_next_itag_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[cp_next_itag_offset :cp_next_itag_offset + `THREADS*`ITAG_SIZE_ENC-1]), + .scout(sov[cp_next_itag_offset:cp_next_itag_offset + `THREADS*`ITAG_SIZE_ENC-1]), + .din(cp_next_itag), + .dout(cp_next_itag_q) + ); + + + //------------------------------------------------------------------------------------------------------------ + // Scan Connections + //------------------------------------------------------------------------------------------------------------ + + assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in}; + assign scan_out = sov[0]; + + //----------------------------------------------- + // pervasive + //----------------------------------------------- + + + tri_plat #(.WIDTH(2)) perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(ccflush_dc), + .din({func_sl_thold_1, sg_1}), + .q({func_sl_thold_0, sg_0}) + ); + + + tri_lcbor perv_lcbor( + .clkoff_b(clkoff_b), + .thold(func_sl_thold_0), + .sg(sg_0), + .act_dis(act_dis), + .force_t(force_t), + .thold_b(func_sl_thold_0_b) + ); + +endmodule // rv_axu0_rvs diff --git a/dev/verilog/work/rv_barf.v b/dev/verilog/work/rv_barf.v new file mode 100755 index 0000000..467e7a2 --- /dev/null +++ b/dev/verilog/work/rv_barf.v @@ -0,0 +1,269 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//----------------------------------------------------------------------------------------------------- +// Title: rv_station12.vhdl +// Desc: Paramaterizable reservation station +//----------------------------------------------------------------------------------------------------- +module rv_barf( + w0_dat, + w0_addr, + w0_en, + w1_dat, + w1_addr, + w1_en, + w_act, + r0_addr, + r0_dat, + vdd, + gnd, + nclk, + sg_1, + func_sl_thold_1, + ccflush_dc, + act_dis, + clkoff_b, + d_mode, + delay_lclkr, + mpw1_b, + mpw2_b, + scan_in, + scan_out + ); +`include "tri_a2o.vh" + + parameter q_dat_width_g = 137; + parameter q_num_entries_g = 16; + parameter q_barf_enc_g=4; + + + input [0:q_dat_width_g-1] w0_dat; + input [0:q_barf_enc_g-1] w0_addr; + input w0_en; + + input [0:q_dat_width_g-1] w1_dat; + input [0:q_barf_enc_g-1] w1_addr; + input w1_en; + + input [0:q_num_entries_g-1] w_act; + + input [0:q_barf_enc_g-1] r0_addr; + output [0:q_dat_width_g-1] r0_dat; + + // pervasive + inout vdd; + inout gnd; + input [0:`NCLK_WIDTH-1] nclk; + input sg_1; + input func_sl_thold_1; + input ccflush_dc; + input act_dis; + input clkoff_b; + input d_mode; + input delay_lclkr; + input mpw1_b; + input mpw2_b; + input scan_in; + + output scan_out; + + + //------------------------------------------------------------------------------------------------------- + // Type definitions + //------------------------------------------------------------------------------------------------------- + + + //------------------------------------------------------------------------------------------------------- + // Functions + //------------------------------------------------------------------------------------------------------- + + + //------------------------------------------------------------------- + // Signals + //------------------------------------------------------------------- + wire [0:q_num_entries_g-1] sg_0; + wire [0:q_num_entries_g-1] func_sl_thold_0; + wire [0:q_num_entries_g-1] func_sl_thold_0_b; + wire [0:q_num_entries_g-1] force_t; + + wire [0:q_num_entries_g-1] q_entry_load0; + wire [0:q_num_entries_g-1] q_entry_load1; + wire [0:q_num_entries_g-1] q_entry_hold; + wire [0:q_num_entries_g-1] q_entry_read; + wire [0:q_num_entries_g-1] q_read_dat[0:q_dat_width_g-1]; + + wire [0:q_num_entries_g-1] q_dat_act; + wire [0:q_dat_width_g-1] q_dat_d[0:q_num_entries_g-1]; + wire [0:q_dat_width_g-1] q_dat_q[0:q_num_entries_g-1]; + + //------------------------------------------------------------------- + // Scanchain + //------------------------------------------------------------------- + parameter q_dat_offset = 0; + parameter scan_right = q_dat_offset + q_num_entries_g * q_dat_width_g; + wire [0:scan_right-1] siv; + wire [0:scan_right-1] sov; + + //------------------------------------------------------------------------------------------------------- + // Notes + //------------------------------------------------------------------------------------------------------- + // + + //------------------------------------------------------------------------------------------------------- + // misc + //------------------------------------------------------------------------------------------------------- + + //------------------------------------------------------------------------------------------------------- + // Latch write data + //------------------------------------------------------------------------------------------------------- + + //------------------------------------------------------------------------------------------------------- + // Write aoi + //------------------------------------------------------------------------------------------------------- + + generate + begin : xhdl1 + genvar n; + for (n = 0; n <= (q_num_entries_g - 1); n = n + 1) + begin : q_dat_gen + wire [0:q_barf_enc_g-1] id= n; + + assign q_entry_load0[n] = (w0_addr == id) & w0_en; + assign q_entry_load1[n] = (w1_addr == id) & w1_en; + assign q_entry_hold[n] = (~q_entry_load0[n]) & (~q_entry_load1[n]); + assign q_dat_d[n] = (w0_dat & {q_dat_width_g{q_entry_load0[n]}}) | + (w1_dat & {q_dat_width_g{q_entry_load1[n]}}) | + (q_dat_q[n] & {q_dat_width_g{q_entry_hold[n]}}); //feedback + assign q_dat_act[n] = w_act[n]; + + end + end + endgenerate + + //------------------------------------------------------------------------------------------------------- + // Read Mux + //------------------------------------------------------------------------------------------------------- + + generate + begin : xhdl1r + genvar n, b; + for (n = 0; n <= (q_num_entries_g - 1); n = n + 1) + begin : rgene + wire [0:q_barf_enc_g-1] idd= n; + //onehot addr + assign q_entry_read[n] = (r0_addr == idd); + + for (b = 0; b <= (q_dat_width_g - 1); b = b + 1) + begin : rgenb + //AND + assign q_read_dat[b][n] = q_dat_q[n][b] & q_entry_read[n]; + end + + end + end + endgenerate + + generate + begin : xhdl1o + genvar b; + for (b = 0; b <= (q_dat_width_g - 1); b = b + 1) + begin : rgeneo + //OR + assign r0_dat[b] = |(q_read_dat[b]); + + end + end + endgenerate + + + //------------------------------------------------------------------------------------------------------- + // storage elements + //------------------------------------------------------------------------------------------------------- + generate + begin : xhdl2 + genvar n; + for (n = 0; n <= q_num_entries_g - 1; n = n + 1) + begin : q_x_q_gen + + tri_plat #(.WIDTH(2)) + perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(ccflush_dc), + .din({func_sl_thold_1, sg_1}), + .q({func_sl_thold_0[n], sg_0[n]}) + ); + + + tri_lcbor + perv_lcbor( + .clkoff_b(clkoff_b), + .thold(func_sl_thold_0[n]), + .sg(sg_0[n]), + .act_dis(act_dis), + .force_t(force_t[n]), + .thold_b(func_sl_thold_0_b[n]) + ); + + + tri_rlmreg_p #(.WIDTH(q_dat_width_g), .INIT(0)) + q_dat_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(q_dat_act[n]), + .thold_b(func_sl_thold_0_b[n]), + .sg(sg_0[n]), + .force_t(force_t[n]), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[q_dat_offset + q_dat_width_g * n:q_dat_offset + q_dat_width_g * (n + 1) - 1]), + .scout(sov[q_dat_offset + q_dat_width_g * n:q_dat_offset + q_dat_width_g * (n + 1) - 1]), + .din(q_dat_d[n]), + .dout(q_dat_q[n]) + ); + end + end + endgenerate + + //--------------------------------------------------------------------- + // Scan + //--------------------------------------------------------------------- + assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in}; + assign scan_out = sov[0]; + +endmodule + + + + diff --git a/dev/verilog/work/rv_cmpitag.v b/dev/verilog/work/rv_cmpitag.v new file mode 100755 index 0000000..fbdbc5d --- /dev/null +++ b/dev/verilog/work/rv_cmpitag.v @@ -0,0 +1,280 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: Mapped Itag Compare +// +//***************************************************************************** + +module rv_cmpitag( + vld, + itag, + vld_ary, + itag_ary, + abort, + hit_clear, + hit_abort + ); +`include "tri_a2o.vh" + parameter q_itag_busses_g = 7; + input [0:`THREADS-1] vld; + input [0:`ITAG_SIZE_ENC-1] itag; + input [0:(q_itag_busses_g*`THREADS)-1] vld_ary; + input [0:(q_itag_busses_g*`ITAG_SIZE_ENC)-1] itag_ary; + input [0:q_itag_busses_g-1] abort; + output hit_clear; + output hit_abort; + + + wire [0:7] valid; + wire [0:7] itag_xor[0:7]; + wire [0:3] itag_andl10_b; + wire [0:3] itag_andl11_b; + wire [0:3] itag_andl12_b; + wire [0:3] itag_andl13_b; + wire [0:3] itag_andl14_b; + wire [0:3] itag_andl15_b; + wire [0:3] itag_andl16_b; + wire [0:3] itag_andl17_b; + + wire [0:1] itag_andl20; + wire [0:1] itag_andl21; + wire [0:1] itag_andl22; + wire [0:1] itag_andl23; + wire [0:1] itag_andl24; + wire [0:1] itag_andl25; + wire [0:1] itag_andl26; + wire [0:1] itag_andl27; + + wire [0:7] itagc_andl3_b; + wire [0:3] itagc_orl4; + wire [0:1] itagc_orl5_b; + wire itagc_orl6; + + wire [0:7] itaga_andl3_b; + wire [0:3] itaga_orl4; + wire [0:1] itaga_orl5_b; + wire itaga_orl6; + + wire [0:7] itag_abort; + wire [0:7] itag_abort_b; + + (* analysis_not_referenced="true" *) + wire unused; + + //------------------------------------------------------------------------------------------------------- + // Total Logic: XOR + 6 levels + //------------------------------------------------------------------------------------------------------- + + generate + begin : xhdl0 + genvar n; + for (n = 0; n <= 5; n = n + 1) + begin : q_valid_gen + assign valid[n] = |(vld_ary[n*`THREADS:n*`THREADS+`THREADS-1] & vld); + + assign itag_xor[n] = {~(itag ^ itag_ary[n*`ITAG_SIZE_ENC:n*`ITAG_SIZE_ENC+`ITAG_SIZE_ENC-1]), valid[n]}; + end + end + endgenerate + + //------------------------------------------------------------------------------------------------------- + // XOR ITAG Compares + //------------------------------------------------------------------------------------------------------- + + assign itag_abort[0:5] = abort[0:5]; + + generate + if (q_itag_busses_g == 6) + begin : l1xor_gen6 + assign itag_xor[6] = {8{1'b0}}; + assign itag_xor[7] = {8{1'b0}}; + assign valid[6] = 1'b0; + assign valid[7] = 1'b0; + assign itag_abort[6] = 1'b0; + assign itag_abort[7] = 1'b0; + end + endgenerate + generate + if (q_itag_busses_g == 7) + begin : l1xor_gen7 + assign itag_xor[6] = {~(itag ^ itag_ary[6*`ITAG_SIZE_ENC:6*`ITAG_SIZE_ENC+`ITAG_SIZE_ENC-1]), valid[6]}; + assign itag_xor[7] = {8{1'b0}}; + assign valid[6] = |(vld_ary[6*`THREADS:6*`THREADS+`THREADS-1] & vld); + assign valid[7] = 1'b0; + assign itag_abort[6] = abort[6]; + assign itag_abort[7] = 1'b0; + + assign unused = valid[7] ; + end + endgenerate + generate + if (q_itag_busses_g == 8) + begin : l1xor_gen8 + assign itag_xor[6] = {~(itag ^ itag_ary[6*`ITAG_SIZE_ENC:6*`ITAG_SIZE_ENC+`ITAG_SIZE_ENC-1]), valid[6]}; + assign itag_xor[7] = {~(itag ^ itag_ary[7*`ITAG_SIZE_ENC:7*`ITAG_SIZE_ENC+`ITAG_SIZE_ENC-1]), valid[7]}; + + assign valid[6] = |(vld_ary[6*`THREADS:6*`THREADS+`THREADS-1] & vld); + assign valid[7] = |(vld_ary[7*`THREADS:7*`THREADS+`THREADS-1] & vld); + + assign itag_abort[6] = abort[6]; + assign itag_abort[7] = abort[7]; + + end + endgenerate + + assign itag_abort_b = ~itag_abort; + + //------------------------------------------------------------------------------------------------------- + // AND Tree. 8 groups of 8, 3 levels each + //------------------------------------------------------------------------------------------------------- + + // Level 1 + assign itag_andl10_b[0] = ~(itag_xor[0][0] & itag_xor[0][1]); + assign itag_andl10_b[1] = ~(itag_xor[0][2] & itag_xor[0][3]); + assign itag_andl10_b[2] = ~(itag_xor[0][4] & itag_xor[0][5]); + assign itag_andl10_b[3] = ~(itag_xor[0][6] & itag_xor[0][7]); + + assign itag_andl11_b[0] = ~(itag_xor[1][0] & itag_xor[1][1]); + assign itag_andl11_b[1] = ~(itag_xor[1][2] & itag_xor[1][3]); + assign itag_andl11_b[2] = ~(itag_xor[1][4] & itag_xor[1][5]); + assign itag_andl11_b[3] = ~(itag_xor[1][6] & itag_xor[1][7]); + + assign itag_andl12_b[0] = ~(itag_xor[2][0] & itag_xor[2][1]); + assign itag_andl12_b[1] = ~(itag_xor[2][2] & itag_xor[2][3]); + assign itag_andl12_b[2] = ~(itag_xor[2][4] & itag_xor[2][5]); + assign itag_andl12_b[3] = ~(itag_xor[2][6] & itag_xor[2][7]); + + assign itag_andl13_b[0] = ~(itag_xor[3][0] & itag_xor[3][1]); + assign itag_andl13_b[1] = ~(itag_xor[3][2] & itag_xor[3][3]); + assign itag_andl13_b[2] = ~(itag_xor[3][4] & itag_xor[3][5]); + assign itag_andl13_b[3] = ~(itag_xor[3][6] & itag_xor[3][7]); + + assign itag_andl14_b[0] = ~(itag_xor[4][0] & itag_xor[4][1]); + assign itag_andl14_b[1] = ~(itag_xor[4][2] & itag_xor[4][3]); + assign itag_andl14_b[2] = ~(itag_xor[4][4] & itag_xor[4][5]); + assign itag_andl14_b[3] = ~(itag_xor[4][6] & itag_xor[4][7]); + + assign itag_andl15_b[0] = ~(itag_xor[5][0] & itag_xor[5][1]); + assign itag_andl15_b[1] = ~(itag_xor[5][2] & itag_xor[5][3]); + assign itag_andl15_b[2] = ~(itag_xor[5][4] & itag_xor[5][5]); + assign itag_andl15_b[3] = ~(itag_xor[5][6] & itag_xor[5][7]); + + assign itag_andl16_b[0] = ~(itag_xor[6][0] & itag_xor[6][1]); + assign itag_andl16_b[1] = ~(itag_xor[6][2] & itag_xor[6][3]); + assign itag_andl16_b[2] = ~(itag_xor[6][4] & itag_xor[6][5]); + assign itag_andl16_b[3] = ~(itag_xor[6][6] & itag_xor[6][7]); + + assign itag_andl17_b[0] = ~(itag_xor[7][0] & itag_xor[7][1]); + assign itag_andl17_b[1] = ~(itag_xor[7][2] & itag_xor[7][3]); + assign itag_andl17_b[2] = ~(itag_xor[7][4] & itag_xor[7][5]); + assign itag_andl17_b[3] = ~(itag_xor[7][6] & itag_xor[7][7]); + + // Level 2 + assign itag_andl20[0] = ~(itag_andl10_b[0] | itag_andl10_b[1]); + assign itag_andl20[1] = ~(itag_andl10_b[2] | itag_andl10_b[3]); + + assign itag_andl21[0] = ~(itag_andl11_b[0] | itag_andl11_b[1]); + assign itag_andl21[1] = ~(itag_andl11_b[2] | itag_andl11_b[3]); + + assign itag_andl22[0] = ~(itag_andl12_b[0] | itag_andl12_b[1]); + assign itag_andl22[1] = ~(itag_andl12_b[2] | itag_andl12_b[3]); + + assign itag_andl23[0] = ~(itag_andl13_b[0] | itag_andl13_b[1]); + assign itag_andl23[1] = ~(itag_andl13_b[2] | itag_andl13_b[3]); + + assign itag_andl24[0] = ~(itag_andl14_b[0] | itag_andl14_b[1]); + assign itag_andl24[1] = ~(itag_andl14_b[2] | itag_andl14_b[3]); + + assign itag_andl25[0] = ~(itag_andl15_b[0] | itag_andl15_b[1]); + assign itag_andl25[1] = ~(itag_andl15_b[2] | itag_andl15_b[3]); + + assign itag_andl26[0] = ~(itag_andl16_b[0] | itag_andl16_b[1]); + assign itag_andl26[1] = ~(itag_andl16_b[2] | itag_andl16_b[3]); + + assign itag_andl27[0] = ~(itag_andl17_b[0] | itag_andl17_b[1]); + assign itag_andl27[1] = ~(itag_andl17_b[2] | itag_andl17_b[3]); + + // Level 3 - sneak in the abort here + assign itagc_andl3_b[0] = ~(itag_andl20[0] & itag_andl20[1] & itag_abort_b[0]); + assign itagc_andl3_b[1] = ~(itag_andl21[0] & itag_andl21[1] & itag_abort_b[1]); + assign itagc_andl3_b[2] = ~(itag_andl22[0] & itag_andl22[1] & itag_abort_b[2]); + assign itagc_andl3_b[3] = ~(itag_andl23[0] & itag_andl23[1] & itag_abort_b[3]); + assign itagc_andl3_b[4] = ~(itag_andl24[0] & itag_andl24[1] & itag_abort_b[4]); + assign itagc_andl3_b[5] = ~(itag_andl25[0] & itag_andl25[1] & itag_abort_b[5]); + assign itagc_andl3_b[6] = ~(itag_andl26[0] & itag_andl26[1] & itag_abort_b[6]); + assign itagc_andl3_b[7] = ~(itag_andl27[0] & itag_andl27[1] & itag_abort_b[7]); + + // Level 3 - sneak in the abort here + assign itaga_andl3_b[0] = ~(itag_andl20[0] & itag_andl20[1] & itag_abort[0]); + assign itaga_andl3_b[1] = ~(itag_andl21[0] & itag_andl21[1] & itag_abort[1]); + assign itaga_andl3_b[2] = ~(itag_andl22[0] & itag_andl22[1] & itag_abort[2]); + assign itaga_andl3_b[3] = ~(itag_andl23[0] & itag_andl23[1] & itag_abort[3]); + assign itaga_andl3_b[4] = ~(itag_andl24[0] & itag_andl24[1] & itag_abort[4]); + assign itaga_andl3_b[5] = ~(itag_andl25[0] & itag_andl25[1] & itag_abort[5]); + assign itaga_andl3_b[6] = ~(itag_andl26[0] & itag_andl26[1] & itag_abort[6]); + assign itaga_andl3_b[7] = ~(itag_andl27[0] & itag_andl27[1] & itag_abort[7]); + + //------------------------------------------------------------------------------------------------------- + // CLEAR OR Tree. 8 groups. Coming in inverted. 3 more levels + //------------------------------------------------------------------------------------------------------- + // Level 4 + assign itagc_orl4[0] = ~(itagc_andl3_b[0] & itagc_andl3_b[1]); + assign itagc_orl4[1] = ~(itagc_andl3_b[2] & itagc_andl3_b[3]); + assign itagc_orl4[2] = ~(itagc_andl3_b[4] & itagc_andl3_b[5]); + assign itagc_orl4[3] = ~(itagc_andl3_b[6] & itagc_andl3_b[7]); + + // Level 5 + assign itagc_orl5_b[0] = ~(itagc_orl4[0] | itagc_orl4[1]); + assign itagc_orl5_b[1] = ~(itagc_orl4[2] | itagc_orl4[3]); + + // Level 6 + assign itagc_orl6 = ~(itagc_orl5_b[0] & itagc_orl5_b[1]); + + assign hit_clear = itagc_orl6; + + //------------------------------------------------------------------------------------------------------- + // ABORT OR Tree. 8 groups. Coming in inverted. 3 more levels + //------------------------------------------------------------------------------------------------------- + // Level 4 + assign itaga_orl4[0] = ~(itaga_andl3_b[0] & itaga_andl3_b[1]); + assign itaga_orl4[1] = ~(itaga_andl3_b[2] & itaga_andl3_b[3]); + assign itaga_orl4[2] = ~(itaga_andl3_b[4] & itaga_andl3_b[5]); + assign itaga_orl4[3] = ~(itaga_andl3_b[6] & itaga_andl3_b[7]); + + // Level 5 + assign itaga_orl5_b[0] = ~(itaga_orl4[0] | itaga_orl4[1]); + assign itaga_orl5_b[1] = ~(itaga_orl4[2] | itaga_orl4[3]); + + // Level 6 + assign itaga_orl6 = ~(itaga_orl5_b[0] & itaga_orl5_b[1]); + + assign hit_abort = itaga_orl6; + +endmodule // rv_cmpitag diff --git a/dev/verilog/work/rv_decode.v b/dev/verilog/work/rv_decode.v new file mode 100755 index 0000000..73b2675 --- /dev/null +++ b/dev/verilog/work/rv_decode.v @@ -0,0 +1,124 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// VHDL 1076 Macro Expander C version 07/11/00 +// job was run on Tue Mar 29 10:19:33 2011 + +//*************************************************************************************************** +//* +//* TITLE: +//* +//* NAME: rv_decode.vhdl +//* +//*************************************************************************************************** +module rv_decode( + instr, + is_brick, + brick_cycles +); + input [0:31] instr; + + output is_brick; + output [0:2] brick_cycles; + //@@ Signal Declarations + wire [1:8] RV_INSTRUCTION_DECODER_PT; + wire [0:5] instr_0_5; + wire [0:10] instr_21_31; + (* analysis_not_referenced="true" *) + wire unused; + + assign unused = |instr[6:20] | instr_21_31[10]; + + //@@ START OF EXECUTABLE CODE FOR RTL + + assign instr_0_5 = instr[0:5]; + assign instr_21_31 = instr[21:31]; + +//table_start +//?TABLE rv_instruction_decoder LISTING(final) OPTIMIZE PARMS(ON-SET); +//*INPUTS*===============*OUTPUTS*==========* +//| | | +//| instr_0_5 | is_brick | +//| | instr_21_31 | | brick_cycles | +//| | | | | | | +//| | | | | | | +//| | | | | | | +//| | | | | | | +//| | | | | | | +//| | | | | | | +//| | | | | | | +//| | | | | | | +//| | | | | | | +//| | | | | | | +//| | | | | | | +//| | | | | | | +//| | | 1 | | | | +//| 012345 01234567890 | | 012 | +//*TYPE*=================+==================+ +//| SSSSSS SSSSSSSSSSS | P PPP | INSTR +//*TERMS*=*=*============+==================+ +//| 000111 ........... | 1 000 | mulli 2 +//| 011111 0011101001. | 1 001 | mulld 3 +//| 011111 1011101001. | 1 010 | mulldo 4 +//| 011111 .001001001. | 1 010 | mulhd 4 +//| 011111 .000001001. | 1 010 | mulhdu 4 +//| 011111 1100110011. | 1 000 | erativax 2 +//| 011111 0011010100. | 1 000 | ldawx +//| 011111 0010100110. | 1 000 | dcbtls +//| 011111 0010000110. | 1 000 | dcbtstls +//| 011111 0000110100. | 1 000 | lbarx +//| 011111 0001010100. | 1 000 | ldarx +//| 011111 0001110100. | 1 000 | lharx +//| 011111 0000010100. | 1 000 | lwarx +//*END*==================+==================+ +//?TABLE END rv_instruction_decoder ; +//table_end + + +//assign_start + + assign RV_INSTRUCTION_DECODER_PT[1] = (({instr_0_5[0], instr_0_5[1], instr_0_5[2], instr_0_5[3], instr_0_5[4], instr_0_5[5], instr_21_31[0], instr_21_31[1], instr_21_31[2], instr_21_31[3], instr_21_31[4], instr_21_31[5], instr_21_31[6], instr_21_31[7], instr_21_31[8], instr_21_31[9]}) == 16'b0111111100110011); + assign RV_INSTRUCTION_DECODER_PT[2] = (({instr_0_5[0], instr_0_5[1], instr_0_5[2], instr_0_5[3], instr_0_5[4], instr_0_5[5], instr_21_31[0], instr_21_31[1], instr_21_31[2], instr_21_31[3], instr_21_31[5], instr_21_31[6], instr_21_31[7], instr_21_31[8], instr_21_31[9]}) == 15'b011111001000110); + assign RV_INSTRUCTION_DECODER_PT[3] = (({instr_0_5[0], instr_0_5[1], instr_0_5[2], instr_0_5[3], instr_0_5[4], instr_0_5[5], instr_21_31[0], instr_21_31[1], instr_21_31[2], instr_21_31[3], instr_21_31[4], instr_21_31[5], instr_21_31[6], instr_21_31[7], instr_21_31[8], instr_21_31[9]}) == 16'b0111111011101001); + assign RV_INSTRUCTION_DECODER_PT[4] = (({instr_0_5[0], instr_0_5[1], instr_0_5[2], instr_0_5[3], instr_0_5[4], instr_0_5[5], instr_21_31[0], instr_21_31[1], instr_21_31[2], instr_21_31[3], instr_21_31[4], instr_21_31[5], instr_21_31[6], instr_21_31[7], instr_21_31[8], instr_21_31[9]}) == 16'b0111110011101001); + assign RV_INSTRUCTION_DECODER_PT[5] = (({instr_0_5[0], instr_0_5[1], instr_0_5[2], instr_0_5[3], instr_0_5[4], instr_0_5[5], instr_21_31[0], instr_21_31[1], instr_21_31[2], instr_21_31[5], instr_21_31[6], instr_21_31[7], instr_21_31[8], instr_21_31[9]}) == 14'b01111100010100); + assign RV_INSTRUCTION_DECODER_PT[6] = (({instr_0_5[0], instr_0_5[1], instr_0_5[2], instr_0_5[3], instr_0_5[4], instr_0_5[5], instr_21_31[0], instr_21_31[1], instr_21_31[3], instr_21_31[4], instr_21_31[5], instr_21_31[6], instr_21_31[7], instr_21_31[8], instr_21_31[9]}) == 15'b011111001010100); + assign RV_INSTRUCTION_DECODER_PT[7] = (({instr_0_5[0], instr_0_5[1], instr_0_5[2], instr_0_5[3], instr_0_5[4], instr_0_5[5], instr_21_31[1], instr_21_31[2], instr_21_31[4], instr_21_31[5], instr_21_31[6], instr_21_31[7], instr_21_31[8], instr_21_31[9]}) == 14'b01111100001001); + assign RV_INSTRUCTION_DECODER_PT[8] = (({instr_0_5[0], instr_0_5[1], instr_0_5[2], instr_0_5[3], instr_0_5[4], instr_0_5[5]}) == 6'b000111); + // Table RV_INSTRUCTION_DECODER Signal Assignments for Outputs + assign is_brick = (RV_INSTRUCTION_DECODER_PT[1] | RV_INSTRUCTION_DECODER_PT[2] | RV_INSTRUCTION_DECODER_PT[3] | RV_INSTRUCTION_DECODER_PT[4] | RV_INSTRUCTION_DECODER_PT[5] | RV_INSTRUCTION_DECODER_PT[6] | RV_INSTRUCTION_DECODER_PT[7] | RV_INSTRUCTION_DECODER_PT[8]); + assign brick_cycles[0] = (1'b0); + assign brick_cycles[1] = (RV_INSTRUCTION_DECODER_PT[3] | RV_INSTRUCTION_DECODER_PT[7]); + assign brick_cycles[2] = (RV_INSTRUCTION_DECODER_PT[4]); + +//assign_end + +endmodule + diff --git a/dev/verilog/work/rv_dep.v b/dev/verilog/work/rv_dep.v new file mode 100755 index 0000000..b3caa82 --- /dev/null +++ b/dev/verilog/work/rv_dep.v @@ -0,0 +1,506 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" + +//----------------------------------------------------------------------------------------------------- +// Title: rv_dep.vhdl +// Desc: Holds the dependency scorecards and second level of itag muxing. +// +//----------------------------------------------------------------------------------------------------- + +module rv_dep( + + //------------------------------------------------------------------------------------------------------------ + // IU Control + //------------------------------------------------------------------------------------------------------------ + input iu_xx_zap, + input rv0_i0_act, + input rv0_i1_act, + + //------------------------------------------------------------------------------------------------------------ + // Instruction Sources + //------------------------------------------------------------------------------------------------------------ + input rv0_instr_i0_vld, + input rv0_instr_i0_t1_v, + input rv0_instr_i0_t2_v, + input rv0_instr_i0_t3_v, + input [0:`ITAG_SIZE_ENC-1] rv0_instr_i0_itag, + + input rv0_instr_i0_s1_v, + input [0:`ITAG_SIZE_ENC-1] rv0_instr_i0_s1_itag, + input rv0_instr_i0_s2_v, + input [0:`ITAG_SIZE_ENC-1] rv0_instr_i0_s2_itag, + input rv0_instr_i0_s3_v, + input [0:`ITAG_SIZE_ENC-1] rv0_instr_i0_s3_itag, + + input rv0_instr_i1_vld, + input rv0_instr_i1_t1_v, + input rv0_instr_i1_t2_v, + input rv0_instr_i1_t3_v, + input [0:`ITAG_SIZE_ENC-1] rv0_instr_i1_itag, + + input rv0_instr_i1_s1_v, + input [0:`ITAG_SIZE_ENC-1] rv0_instr_i1_s1_itag, + input rv0_instr_i1_s2_v, + input [0:`ITAG_SIZE_ENC-1] rv0_instr_i1_s2_itag, + input rv0_instr_i1_s3_v, + input [0:`ITAG_SIZE_ENC-1] rv0_instr_i1_s3_itag, + + //------------------------------------------------------------------------------------------------------------ + // ITAG Busses + //------------------------------------------------------------------------------------------------------------ + input fx0_rv_itag_vld, + input [0:`ITAG_SIZE_ENC-1] fx0_rv_itag, + input fx1_rv_itag_vld, + input [0:`ITAG_SIZE_ENC-1] fx1_rv_itag, + input lq_rv_itag0_vld, + input [0:`ITAG_SIZE_ENC-1] lq_rv_itag0, + input lq_rv_itag1_vld, + input [0:`ITAG_SIZE_ENC-1] lq_rv_itag1, + input lq_rv_itag2_vld, + input [0:`ITAG_SIZE_ENC-1] lq_rv_itag2, + input axu0_rv_itag_vld, + input [0:`ITAG_SIZE_ENC-1] axu0_rv_itag, + input axu1_rv_itag_vld, + input [0:`ITAG_SIZE_ENC-1] axu1_rv_itag, + + input fx0_rv_itag_abort, + input fx1_rv_itag_abort, + input lq_rv_itag0_abort, + input lq_rv_itag1_abort, + input axu0_rv_itag_abort, + input axu1_rv_itag_abort, + + //------------------------------------------------------------------------------------------------------------ + // Source Hit Information + //------------------------------------------------------------------------------------------------------------ + output rv0_instr_i0_s1_dep_hit, + output rv0_instr_i0_s2_dep_hit, + output rv0_instr_i0_s3_dep_hit, + + output rv0_instr_i1_s1_dep_hit, + output rv0_instr_i1_s2_dep_hit, + output rv0_instr_i1_s3_dep_hit, + + //------------------------------------------------------------------------------------------------------------ + // Pervasive + //------------------------------------------------------------------------------------------------------------ + inout vdd, + inout gnd, + (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) // nclk + input [0:`NCLK_WIDTH-1] nclk, + + input func_sl_thold_1, + input sg_1, + input clkoff_b, + input act_dis, + input ccflush_dc, + + input d_mode, + input delay_lclkr, + input mpw1_b, + input mpw2_b, + input scan_in, + output scan_out + ); + + //------------------------------------------------------------------------------------------------------------ + // Misc + //------------------------------------------------------------------------------------------------------------ + wire tiup; + + parameter zero = 0; + + //------------------------------------------------------------------------------------------------------------ + // Input Latches + //------------------------------------------------------------------------------------------------------------ + wire rv0_sc_act; + wire [0:6] xx_rv_itag_v_d; + wire [0:6] xx_rv_itag_v_q; + wire [0:6] xx_rv_itag_abort_d; + wire [0:6] xx_rv_itag_abort_q; + wire [0:`ITAG_SIZE_ENC-2-1] xx_rv_itag_ary0_d; + wire [0:`ITAG_SIZE_ENC-2-1] xx_rv_itag_ary1_d; + wire [0:`ITAG_SIZE_ENC-2-1] xx_rv_itag_ary2_d; + wire [0:`ITAG_SIZE_ENC-2-1] xx_rv_itag_ary3_d; + wire [0:`ITAG_SIZE_ENC-2-1] xx_rv_itag_ary4_d; + wire [0:`ITAG_SIZE_ENC-2-1] xx_rv_itag_ary5_d; + wire [0:`ITAG_SIZE_ENC-2-1] xx_rv_itag_ary6_d; + wire [0:`ITAG_SIZE_ENC-2-1] xx_rv_itag_ary0_q; + wire [0:`ITAG_SIZE_ENC-2-1] xx_rv_itag_ary1_q; + wire [0:`ITAG_SIZE_ENC-2-1] xx_rv_itag_ary2_q; + wire [0:`ITAG_SIZE_ENC-2-1] xx_rv_itag_ary3_q; + wire [0:`ITAG_SIZE_ENC-2-1] xx_rv_itag_ary4_q; + wire [0:`ITAG_SIZE_ENC-2-1] xx_rv_itag_ary5_q; + wire [0:`ITAG_SIZE_ENC-2-1] xx_rv_itag_ary6_q; + + //------------------------------------------------------------------------------------------------------------ + // GPR PRF Scorecard Signals + //------------------------------------------------------------------------------------------------------------ + + wire i0_target_v; + wire i1_target_v; + + wire rv0_instr_i0_s1_dep_hit_v; + wire rv0_instr_i0_s2_dep_hit_v; + wire rv0_instr_i0_s3_dep_hit_v; + wire rv0_instr_i1_s1_dep_hit_v; + wire rv0_instr_i1_s2_dep_hit_v; + wire rv0_instr_i1_s3_dep_hit_v; + + //------------------------------------------------------------------------------------------------------------ + // Scan + //------------------------------------------------------------------------------------------------------------ + parameter scorecard_offset = 0; + parameter xx_rv_itag_v_offset = scorecard_offset + 1; + parameter xx_rv_itag_abort_offset = xx_rv_itag_v_offset + 7; + parameter xx_rv_itag_ary0_offset = xx_rv_itag_abort_offset + 7; + parameter xx_rv_itag_ary1_offset = xx_rv_itag_ary0_offset + `ITAG_SIZE_ENC-2; + parameter xx_rv_itag_ary2_offset = xx_rv_itag_ary1_offset + `ITAG_SIZE_ENC-2; + parameter xx_rv_itag_ary3_offset = xx_rv_itag_ary2_offset + `ITAG_SIZE_ENC-2; + parameter xx_rv_itag_ary4_offset = xx_rv_itag_ary3_offset + `ITAG_SIZE_ENC-2; + parameter xx_rv_itag_ary5_offset = xx_rv_itag_ary4_offset + `ITAG_SIZE_ENC-2; + parameter xx_rv_itag_ary6_offset = xx_rv_itag_ary5_offset + `ITAG_SIZE_ENC-2; + + parameter scan_right = xx_rv_itag_ary6_offset + `ITAG_SIZE_ENC-2; + wire [0:scan_right-1] siv; + wire [0:scan_right-1] sov; + + wire func_sl_thold_0; + wire func_sl_thold_0_b; + wire sg_0; + wire force_t; + (* analysis_not_referenced="true" *) + wire unused; + + assign rv0_sc_act = rv0_i0_act | rv0_i1_act | (|xx_rv_itag_v_q) | (|iu_xx_zap); + + //------------------------------------------------------------------------------------------------------------ + // GPR PRF Scorecard + //------------------------------------------------------------------------------------------------------------ + + assign i0_target_v = rv0_instr_i0_vld & (rv0_instr_i0_t1_v | rv0_instr_i0_t2_v | rv0_instr_i0_t3_v); + assign i1_target_v = rv0_instr_i1_vld & (rv0_instr_i1_t1_v | rv0_instr_i1_t2_v | rv0_instr_i1_t3_v); + + + //num_entries_enc_g => ``GPR_POOL_ENC, + rv_dep_scard #(.num_entries_g(2 ** (`ITAG_SIZE_ENC - 2)), .itag_width_enc_g(`ITAG_SIZE_ENC - 2) ) sc( + .iu_xx_zap(iu_xx_zap), + .rv0_sc_act(rv0_sc_act), + + .ta_v(i0_target_v), + .ta_itag(rv0_instr_i0_itag[2:`ITAG_SIZE_ENC - 1]), + + .tb_v(i1_target_v), + .tb_itag(rv0_instr_i1_itag[2:`ITAG_SIZE_ENC - 1]), + + .xx_rv_itag_v(xx_rv_itag_v_q), + .xx_rv_itag_abort(xx_rv_itag_abort_q), + .xx_rv_itag_ary0(xx_rv_itag_ary0_q), + .xx_rv_itag_ary1(xx_rv_itag_ary1_q), + .xx_rv_itag_ary2(xx_rv_itag_ary2_q), + .xx_rv_itag_ary3(xx_rv_itag_ary3_q), + .xx_rv_itag_ary4(xx_rv_itag_ary4_q), + .xx_rv_itag_ary5(xx_rv_itag_ary5_q), + .xx_rv_itag_ary6(xx_rv_itag_ary6_q), + + .i0_s1_itag(rv0_instr_i0_s1_itag[2:`ITAG_SIZE_ENC - 1]), + .i0_s2_itag(rv0_instr_i0_s2_itag[2:`ITAG_SIZE_ENC - 1]), + .i0_s3_itag(rv0_instr_i0_s3_itag[2:`ITAG_SIZE_ENC - 1]), + .i1_s1_itag(rv0_instr_i1_s1_itag[2:`ITAG_SIZE_ENC - 1]), + .i1_s2_itag(rv0_instr_i1_s2_itag[2:`ITAG_SIZE_ENC - 1]), + .i1_s3_itag(rv0_instr_i1_s3_itag[2:`ITAG_SIZE_ENC - 1]), + .i0_s1_itag_v(rv0_instr_i0_s1_dep_hit_v), + .i0_s2_itag_v(rv0_instr_i0_s2_dep_hit_v), + .i0_s3_itag_v(rv0_instr_i0_s3_dep_hit_v), + .i1_s1_itag_v(rv0_instr_i1_s1_dep_hit_v), + .i1_s2_itag_v(rv0_instr_i1_s2_dep_hit_v), + .i1_s3_itag_v(rv0_instr_i1_s3_dep_hit_v), + + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .chip_b_sl_sg_0_t(sg_0), + .chip_b_sl_2_thold_0_b(func_sl_thold_0_b), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scan_in(siv[scorecard_offset]), + .scan_out(sov[scorecard_offset]) + ); + + assign rv0_instr_i0_s1_dep_hit = rv0_instr_i0_s1_dep_hit_v & (rv0_instr_i0_s1_v & ~rv0_instr_i0_s1_itag[1]); + assign rv0_instr_i0_s2_dep_hit = rv0_instr_i0_s2_dep_hit_v & (rv0_instr_i0_s2_v & ~rv0_instr_i0_s2_itag[1]); + assign rv0_instr_i0_s3_dep_hit = rv0_instr_i0_s3_dep_hit_v & (rv0_instr_i0_s3_v & ~rv0_instr_i0_s3_itag[1]); + + assign rv0_instr_i1_s1_dep_hit = rv0_instr_i1_s1_dep_hit_v & (rv0_instr_i1_s1_v & ~rv0_instr_i1_s1_itag[1]); + assign rv0_instr_i1_s2_dep_hit = rv0_instr_i1_s2_dep_hit_v & (rv0_instr_i1_s2_v & ~rv0_instr_i1_s2_itag[1]); + assign rv0_instr_i1_s3_dep_hit = rv0_instr_i1_s3_dep_hit_v & (rv0_instr_i1_s3_v & ~rv0_instr_i1_s3_itag[1]); + + //------------------------------------------------------------------------------------------------------------ + // Misc + //------------------------------------------------------------------------------------------------------------ + assign tiup = 1'b1; + + //------------------------------------------------------------------------------------------------------------ + // Release/Abort Busses + //------------------------------------------------------------------------------------------------------------ + assign xx_rv_itag_v_d[0] = fx0_rv_itag_vld & ~(iu_xx_zap); + assign xx_rv_itag_v_d[1] = fx1_rv_itag_vld & ~(iu_xx_zap); + assign xx_rv_itag_v_d[2] = lq_rv_itag0_vld & ~(iu_xx_zap); + assign xx_rv_itag_v_d[3] = lq_rv_itag1_vld & ~(iu_xx_zap); + assign xx_rv_itag_v_d[4] = lq_rv_itag2_vld & ~(iu_xx_zap); + assign xx_rv_itag_v_d[5] = axu0_rv_itag_vld & ~(iu_xx_zap); + assign xx_rv_itag_v_d[6] = axu1_rv_itag_vld & ~(iu_xx_zap); + + assign xx_rv_itag_ary0_d = fx0_rv_itag[2:`ITAG_SIZE_ENC - 1]; + assign xx_rv_itag_ary1_d = fx1_rv_itag[2:`ITAG_SIZE_ENC - 1]; + assign xx_rv_itag_ary2_d = lq_rv_itag0[2:`ITAG_SIZE_ENC - 1]; + assign xx_rv_itag_ary3_d = lq_rv_itag1[2:`ITAG_SIZE_ENC - 1]; + assign xx_rv_itag_ary4_d = lq_rv_itag2[2:`ITAG_SIZE_ENC - 1]; + assign xx_rv_itag_ary5_d = axu0_rv_itag[2:`ITAG_SIZE_ENC - 1]; + assign xx_rv_itag_ary6_d = axu1_rv_itag[2:`ITAG_SIZE_ENC - 1]; + + assign xx_rv_itag_abort_d[0] = fx0_rv_itag_abort; + assign xx_rv_itag_abort_d[1] = fx1_rv_itag_abort; + assign xx_rv_itag_abort_d[2] = lq_rv_itag0_abort; + assign xx_rv_itag_abort_d[3] = lq_rv_itag1_abort; + assign xx_rv_itag_abort_d[4] = 1'b0; + assign xx_rv_itag_abort_d[5] = axu0_rv_itag_abort; + assign xx_rv_itag_abort_d[6] = axu1_rv_itag_abort; + + + + //------------------------------------------------------------------------------------------------------------ + // Latches + //------------------------------------------------------------------------------------------------------------ + + + tri_rlmreg_p #(.WIDTH(7), .INIT(0) ) xx_rv_itag_v_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[xx_rv_itag_v_offset:xx_rv_itag_v_offset + 7 - 1]), + .scout(sov[xx_rv_itag_v_offset:xx_rv_itag_v_offset + 7 - 1]), + .din(xx_rv_itag_v_d), + .dout(xx_rv_itag_v_q) + ); + tri_rlmreg_p #(.WIDTH(7), .INIT(0) ) xx_rv_itag_abort_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[xx_rv_itag_abort_offset:xx_rv_itag_abort_offset + 7 - 1]), + .scout(sov[xx_rv_itag_abort_offset:xx_rv_itag_abort_offset + 7 - 1]), + .din(xx_rv_itag_abort_d), + .dout(xx_rv_itag_abort_q) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC-2), .INIT(0)) xx_rv_itag_ary0_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin( siv[xx_rv_itag_ary0_offset :xx_rv_itag_ary0_offset + `ITAG_SIZE_ENC-2 - 1]), + .scout(sov[xx_rv_itag_ary0_offset :xx_rv_itag_ary0_offset + `ITAG_SIZE_ENC-2 - 1]), + .din(xx_rv_itag_ary0_d), + .dout(xx_rv_itag_ary0_q) + ); + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC-2), .INIT(0)) xx_rv_itag_ary1_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin( siv[xx_rv_itag_ary1_offset :xx_rv_itag_ary1_offset + `ITAG_SIZE_ENC-2 - 1]), + .scout(sov[xx_rv_itag_ary1_offset :xx_rv_itag_ary1_offset + `ITAG_SIZE_ENC-2 - 1]), + .din(xx_rv_itag_ary1_d), + .dout(xx_rv_itag_ary1_q) + ); + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC-2), .INIT(0)) xx_rv_itag_ary2_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin( siv[xx_rv_itag_ary2_offset :xx_rv_itag_ary2_offset + `ITAG_SIZE_ENC-2 - 1]), + .scout(sov[xx_rv_itag_ary2_offset :xx_rv_itag_ary2_offset + `ITAG_SIZE_ENC-2 - 1]), + .din(xx_rv_itag_ary2_d), + .dout(xx_rv_itag_ary2_q) + ); + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC-2), .INIT(0)) xx_rv_itag_ary3_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin( siv[xx_rv_itag_ary3_offset :xx_rv_itag_ary3_offset + `ITAG_SIZE_ENC-2 - 1]), + .scout(sov[xx_rv_itag_ary3_offset :xx_rv_itag_ary3_offset + `ITAG_SIZE_ENC-2 - 1]), + .din(xx_rv_itag_ary3_d), + .dout(xx_rv_itag_ary3_q) + ); + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC-2), .INIT(0)) xx_rv_itag_ary4_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin( siv[xx_rv_itag_ary4_offset :xx_rv_itag_ary4_offset + `ITAG_SIZE_ENC-2 - 1]), + .scout(sov[xx_rv_itag_ary4_offset :xx_rv_itag_ary4_offset + `ITAG_SIZE_ENC-2 - 1]), + .din(xx_rv_itag_ary4_d), + .dout(xx_rv_itag_ary4_q) + ); + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC-2), .INIT(0)) xx_rv_itag_ary5_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin( siv[xx_rv_itag_ary5_offset :xx_rv_itag_ary5_offset + `ITAG_SIZE_ENC-2 - 1]), + .scout(sov[xx_rv_itag_ary5_offset :xx_rv_itag_ary5_offset + `ITAG_SIZE_ENC-2 - 1]), + .din(xx_rv_itag_ary5_d), + .dout(xx_rv_itag_ary5_q) + ); + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC-2), .INIT(0)) xx_rv_itag_ary6_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin( siv[xx_rv_itag_ary6_offset :xx_rv_itag_ary6_offset + `ITAG_SIZE_ENC-2 - 1]), + .scout(sov[xx_rv_itag_ary6_offset :xx_rv_itag_ary6_offset + `ITAG_SIZE_ENC-2 - 1]), + .din(xx_rv_itag_ary6_d), + .dout(xx_rv_itag_ary6_q) + ); + + + + //--------------------------------------------------------------------- + // Scan + //--------------------------------------------------------------------- + assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in}; + assign scan_out = sov[0]; + + //----------------------------------------------- + // pervasive + //----------------------------------------------- + + + tri_plat #(.WIDTH(2)) perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(ccflush_dc), + .din({func_sl_thold_1,sg_1}), + .q({func_sl_thold_0,sg_0}) + ); + + + tri_lcbor perv_lcbor( + .clkoff_b(clkoff_b), + .thold(func_sl_thold_0), + .sg(sg_0), + .act_dis(act_dis), + .force_t(force_t), + .thold_b(func_sl_thold_0_b) + ); + + //----------------------------------------------- + // unused signals + //----------------------------------------------- + assign unused = rv0_instr_i0_s1_itag[0] | rv0_instr_i0_s2_itag[0] | rv0_instr_i0_s3_itag[0] | + rv0_instr_i1_s1_itag[0] | rv0_instr_i1_s2_itag[0] | rv0_instr_i1_s3_itag[0] | + |rv0_instr_i0_itag[0:1] | |rv0_instr_i1_itag[0:1] | + |fx0_rv_itag[0:1] | |fx1_rv_itag[0:1] | |lq_rv_itag0[0:1] | |lq_rv_itag1[0:1] | |lq_rv_itag2[0:1] | |axu0_rv_itag[0:1] | |axu1_rv_itag[0:1] ; + + + +endmodule diff --git a/dev/verilog/work/rv_dep_scard.v b/dev/verilog/work/rv_dep_scard.v new file mode 100755 index 0000000..05812f7 --- /dev/null +++ b/dev/verilog/work/rv_dep_scard.v @@ -0,0 +1,295 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +`timescale 1 ns / 1 ns + +//----------------------------------------------------------------------------------------------------- +// Title: rv_dep_scard.vhdl +// Desc: Itag based score card +// +// Notes: +// All indexes are assumed to be ITAG indices +// +// +//----------------------------------------------------------------------------------------------------- +module rv_dep_scard( + iu_xx_zap, + rv0_sc_act, + ta_v, + ta_itag, + tb_v, + tb_itag, + xx_rv_itag_v, + xx_rv_itag_abort, + xx_rv_itag_ary0, + xx_rv_itag_ary1, + xx_rv_itag_ary2, + xx_rv_itag_ary3, + xx_rv_itag_ary4, + xx_rv_itag_ary5, + xx_rv_itag_ary6, + i0_s1_itag, + i0_s1_itag_v, + i0_s2_itag, + i0_s2_itag_v, + i0_s3_itag, + i0_s3_itag_v, + i1_s1_itag, + i1_s1_itag_v, + i1_s2_itag, + i1_s2_itag_v, + i1_s3_itag, + i1_s3_itag_v, + vdd, + gnd, + nclk, + chip_b_sl_sg_0_t, + chip_b_sl_2_thold_0_b, + force_t, + d_mode, + delay_lclkr, + mpw1_b, + mpw2_b, + scan_in, + scan_out +); + + + `include "tri_a2o.vh" + + parameter num_entries_g = 32; + parameter itag_width_enc_g = 6; + + + //------------------------------------------------------------------------------------------------------------ + // IU Control + //------------------------------------------------------------------------------------------------------------ + input iu_xx_zap; + input rv0_sc_act; + + //------------------------------------------------------------------------------------------------------------ + // Target interface + //------------------------------------------------------------------------------------------------------------ + input ta_v; + input [0:itag_width_enc_g-1] ta_itag; + + input tb_v; + input [0:itag_width_enc_g-1] tb_itag; + + //------------------------------------------------------------------------------------------------------------ + // Itag Compare and Reset Valid Interface + //------------------------------------------------------------------------------------------------------------ + input [0:6] xx_rv_itag_v; + input [0:6] xx_rv_itag_abort; + input [0:itag_width_enc_g-1] xx_rv_itag_ary0; + input [0:itag_width_enc_g-1] xx_rv_itag_ary1; + input [0:itag_width_enc_g-1] xx_rv_itag_ary2; + input [0:itag_width_enc_g-1] xx_rv_itag_ary3; + input [0:itag_width_enc_g-1] xx_rv_itag_ary4; + input [0:itag_width_enc_g-1] xx_rv_itag_ary5; + input [0:itag_width_enc_g-1] xx_rv_itag_ary6; + + //------------------------------------------------------------------------------------------------------------ + // Itag Mux(s) + //------------------------------------------------------------------------------------------------------------ + input [0:itag_width_enc_g-1] i0_s1_itag; + output i0_s1_itag_v; + + input [0:itag_width_enc_g-1] i0_s2_itag; + output i0_s2_itag_v; + + input [0:itag_width_enc_g-1] i0_s3_itag; + output i0_s3_itag_v; + + input [0:itag_width_enc_g-1] i1_s1_itag; + output i1_s1_itag_v; + + input [0:itag_width_enc_g-1] i1_s2_itag; + output i1_s2_itag_v; + + input [0:itag_width_enc_g-1] i1_s3_itag; + output i1_s3_itag_v; + + //------------------------------------------------------------------------------------------------------------ + // Pervasive + //------------------------------------------------------------------------------------------------------------ + inout vdd; + inout gnd; + (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) // nclk + input [0:`NCLK_WIDTH-1] nclk; + input chip_b_sl_sg_0_t; + input chip_b_sl_2_thold_0_b; + input force_t; + input d_mode; + input delay_lclkr; + input mpw1_b; + input mpw2_b; + input scan_in; + output scan_out; + + //!! Bugspray Include: rv_dep_scard ; + + //------------------------------------------------------------------------------------------------------------ + // typedefs and constants + //------------------------------------------------------------------------------------------------------------ + + //------------------------------------------------------------------------------------------------------------ + // Select and mux signals + //------------------------------------------------------------------------------------------------------------ + wire [0:num_entries_g-1] i0_s1_itag_v_gated; + wire [0:num_entries_g-1] i0_s2_itag_v_gated; + wire [0:num_entries_g-1] i0_s3_itag_v_gated; + wire [0:num_entries_g-1] i1_s1_itag_v_gated; + wire [0:num_entries_g-1] i1_s2_itag_v_gated; + wire [0:num_entries_g-1] i1_s3_itag_v_gated; + + //------------------------------------------------------------------------------------------------------------ + // Storage + //------------------------------------------------------------------------------------------------------------ + wire [0:num_entries_g-1] scorecard_d; + wire [0:num_entries_g-1] scorecard_q; + + wire [0:num_entries_g-1] score_ta_match; + wire [0:num_entries_g-1] score_tb_match; + wire [0:num_entries_g-1] itag_ary0_match; + wire [0:num_entries_g-1] itag_ary1_match; + wire [0:num_entries_g-1] itag_ary2_match; + wire [0:num_entries_g-1] itag_ary3_match; + wire [0:num_entries_g-1] itag_ary4_match; + wire [0:num_entries_g-1] itag_ary5_match; + wire [0:num_entries_g-1] itag_ary6_match; + wire [0:num_entries_g-1] score_set; + wire [0:num_entries_g-1] score_reset; + + //------------------------------------------------------------------------------------------------------------ + // Scan + //------------------------------------------------------------------------------------------------------------ + `define scorecard_offset 0 + + `define scan_right `scorecard_offset + num_entries_g + wire [0:`scan_right-1] siv; + wire [0:`scan_right-1] sov; + + //------------------------------------------------------------------------------------------------------------ + // Set the target if t_v is valid and clear the valid if any of the target busses match + //------------------------------------------------------------------------------------------------------------ + + generate + begin : xhdl1 + genvar i; + for (i = 0; i <= num_entries_g - 1; i = i + 1) + begin : g0 + wire [0:itag_width_enc_g-1] id = i; + assign score_ta_match[i] = (ta_v & (id == ta_itag)); + assign score_tb_match[i] = (tb_v & (id == tb_itag)); + + assign itag_ary0_match[i] = (id == xx_rv_itag_ary0); + assign itag_ary1_match[i] = (id == xx_rv_itag_ary1); + assign itag_ary2_match[i] = (id == xx_rv_itag_ary2); + assign itag_ary3_match[i] = (id == xx_rv_itag_ary3); + assign itag_ary4_match[i] = (id == xx_rv_itag_ary4); + assign itag_ary5_match[i] = (id == xx_rv_itag_ary5); + assign itag_ary6_match[i] = (id == xx_rv_itag_ary6); + + assign score_reset[i] = (xx_rv_itag_v[0] & ~xx_rv_itag_abort[0] & itag_ary0_match[i]) | + (xx_rv_itag_v[1] & ~xx_rv_itag_abort[1] & itag_ary1_match[i]) | + (xx_rv_itag_v[2] & ~xx_rv_itag_abort[2] & itag_ary2_match[i]) | + (xx_rv_itag_v[3] & ~xx_rv_itag_abort[3] & itag_ary3_match[i]) | + (xx_rv_itag_v[4] & ~xx_rv_itag_abort[4] & itag_ary4_match[i]) | + (xx_rv_itag_v[5] & ~xx_rv_itag_abort[5] & itag_ary5_match[i]) | + (xx_rv_itag_v[6] & ~xx_rv_itag_abort[6] & itag_ary6_match[i]) ; + assign score_set[i] = (xx_rv_itag_v[0] & xx_rv_itag_abort[0] & itag_ary0_match[i]) | + (xx_rv_itag_v[1] & xx_rv_itag_abort[1] & itag_ary1_match[i]) | + (xx_rv_itag_v[2] & xx_rv_itag_abort[2] & itag_ary2_match[i]) | + (xx_rv_itag_v[3] & xx_rv_itag_abort[3] & itag_ary3_match[i]) | + (xx_rv_itag_v[4] & xx_rv_itag_abort[4] & itag_ary4_match[i]) | + (xx_rv_itag_v[5] & xx_rv_itag_abort[5] & itag_ary5_match[i]) | + (xx_rv_itag_v[6] & xx_rv_itag_abort[6] & itag_ary6_match[i]) ; + + + assign scorecard_d[i] = (score_ta_match[i] | score_tb_match[i] | score_set[i] | scorecard_q[i]) & (~score_reset[i]) & (~iu_xx_zap); + end + end + endgenerate + + //------------------------------------------------------------------------------------------------------------ + // Mux out the itag + //------------------------------------------------------------------------------------------------------------ + generate + begin : xhdl2 + genvar i; + for (i = 0; i <= num_entries_g - 1; i = i + 1) + begin : g1 + wire [0:itag_width_enc_g-1] id = i; + assign i0_s1_itag_v_gated[i] = (scorecard_q[i]) & (i0_s1_itag == id); + assign i0_s2_itag_v_gated[i] = (scorecard_q[i]) & (i0_s2_itag == id); + assign i0_s3_itag_v_gated[i] = (scorecard_q[i]) & (i0_s3_itag == id); + assign i1_s1_itag_v_gated[i] = (scorecard_q[i]) & (i1_s1_itag == id); + assign i1_s2_itag_v_gated[i] = (scorecard_q[i]) & (i1_s2_itag == id); + assign i1_s3_itag_v_gated[i] = (scorecard_q[i]) & (i1_s3_itag == id); + end + end + endgenerate + assign i0_s1_itag_v = |(i0_s1_itag_v_gated); + assign i0_s2_itag_v = |(i0_s2_itag_v_gated); + assign i0_s3_itag_v = |(i0_s3_itag_v_gated); + assign i1_s1_itag_v = |(i1_s1_itag_v_gated); + assign i1_s2_itag_v = |(i1_s2_itag_v_gated); + assign i1_s3_itag_v = |(i1_s3_itag_v_gated); + + //------------------------------------------------------------------------------------------------------------ + // Storage Elements + //------------------------------------------------------------------------------------------------------------ + + tri_rlmreg_p #(.WIDTH(num_entries_g), .INIT(0) ) scorecard_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rv0_sc_act), + .thold_b(chip_b_sl_2_thold_0_b), + .sg(chip_b_sl_sg_0_t), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[`scorecard_offset :`scorecard_offset + num_entries_g - 1]), + .scout(sov[`scorecard_offset :`scorecard_offset + num_entries_g - 1]), + .din(scorecard_d), + .dout(scorecard_q) + ); + + //--------------------------------------------------------------------- + // Scan + //--------------------------------------------------------------------- + assign siv[0:`scan_right-1] = {sov[1:`scan_right-1], scan_in}; + assign scan_out = sov[0]; + +endmodule + diff --git a/dev/verilog/work/rv_deps.v b/dev/verilog/work/rv_deps.v new file mode 100755 index 0000000..0494309 --- /dev/null +++ b/dev/verilog/work/rv_deps.v @@ -0,0 +1,6402 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// ********************************************************************* +// +// This is the ENTITY for rv_deps +// +// ********************************************************************* + +module rv_deps( + +`include "tri_a2o.vh" + + //------------------------------------------------------------------------------------------------------------ + // Instructions from IU + //------------------------------------------------------------------------------------------------------------ + input iu_rv_iu6_t0_i0_vld, + input iu_rv_iu6_t0_i0_rte_lq, + input iu_rv_iu6_t0_i0_rte_sq, + input iu_rv_iu6_t0_i0_rte_fx0, + input iu_rv_iu6_t0_i0_rte_fx1, + input iu_rv_iu6_t0_i0_rte_axu0, + input iu_rv_iu6_t0_i0_rte_axu1, + input iu_rv_iu6_t0_i0_act , + input [0:31] iu_rv_iu6_t0_i0_instr, + input [0:`EFF_IFAR_WIDTH-1] iu_rv_iu6_t0_i0_ifar, + input [0:2] iu_rv_iu6_t0_i0_ucode, + input iu_rv_iu6_t0_i0_2ucode, + input [0:`UCODE_ENTRIES_ENC-1] iu_rv_iu6_t0_i0_ucode_cnt, + input [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i0_itag, + input iu_rv_iu6_t0_i0_ord, + input iu_rv_iu6_t0_i0_cord, + input iu_rv_iu6_t0_i0_spec, + input iu_rv_iu6_t0_i0_t1_v, + input [0:2] iu_rv_iu6_t0_i0_t1_t, + input [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_t1_p, + input iu_rv_iu6_t0_i0_t2_v, + input [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_t2_p, + input [0:2] iu_rv_iu6_t0_i0_t2_t, + input iu_rv_iu6_t0_i0_t3_v, + input [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_t3_p, + input [0:2] iu_rv_iu6_t0_i0_t3_t, + input iu_rv_iu6_t0_i0_s1_v, + input [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_s1_p, + input [0:2] iu_rv_iu6_t0_i0_s1_t, + input iu_rv_iu6_t0_i0_s2_v, + input [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_s2_p, + input [0:2] iu_rv_iu6_t0_i0_s2_t, + input iu_rv_iu6_t0_i0_s3_v, + input [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i0_s3_p, + input [0:2] iu_rv_iu6_t0_i0_s3_t, + input [0:3] iu_rv_iu6_t0_i0_ilat, + input [0:`G_BRANCH_LEN-1] iu_rv_iu6_t0_i0_branch, + input iu_rv_iu6_t0_i0_isLoad, + input iu_rv_iu6_t0_i0_isStore, + input [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i0_s1_itag, + input [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i0_s2_itag, + input [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i0_s3_itag, + + input iu_rv_iu6_t0_i1_vld, + input iu_rv_iu6_t0_i1_rte_lq, + input iu_rv_iu6_t0_i1_rte_sq, + input iu_rv_iu6_t0_i1_rte_fx0, + input iu_rv_iu6_t0_i1_rte_fx1, + input iu_rv_iu6_t0_i1_rte_axu0, + input iu_rv_iu6_t0_i1_rte_axu1, + input iu_rv_iu6_t0_i1_act , + input [0:31] iu_rv_iu6_t0_i1_instr, + input [0:`EFF_IFAR_WIDTH-1] iu_rv_iu6_t0_i1_ifar, + input [0:2] iu_rv_iu6_t0_i1_ucode, + input [0:`UCODE_ENTRIES_ENC-1] iu_rv_iu6_t0_i1_ucode_cnt, + input [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i1_itag, + input iu_rv_iu6_t0_i1_ord, + input iu_rv_iu6_t0_i1_cord, + input iu_rv_iu6_t0_i1_spec, + input iu_rv_iu6_t0_i1_t1_v, + input [0:2] iu_rv_iu6_t0_i1_t1_t, + input [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_t1_p, + input iu_rv_iu6_t0_i1_t2_v, + input [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_t2_p, + input [0:2] iu_rv_iu6_t0_i1_t2_t, + input iu_rv_iu6_t0_i1_t3_v, + input [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_t3_p, + input [0:2] iu_rv_iu6_t0_i1_t3_t, + input iu_rv_iu6_t0_i1_s1_v, + input [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_s1_p, + input [0:2] iu_rv_iu6_t0_i1_s1_t, + input iu_rv_iu6_t0_i1_s2_v, + input [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_s2_p, + input [0:2] iu_rv_iu6_t0_i1_s2_t, + input iu_rv_iu6_t0_i1_s3_v, + input [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_s3_p, + input [0:2] iu_rv_iu6_t0_i1_s3_t, + input [0:3] iu_rv_iu6_t0_i1_ilat, + input [0:`G_BRANCH_LEN-1] iu_rv_iu6_t0_i1_branch, + input iu_rv_iu6_t0_i1_isLoad, + input iu_rv_iu6_t0_i1_isStore, + input [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i1_s1_itag, + input [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i1_s2_itag, + input [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i1_s3_itag, + input iu_rv_iu6_t0_i1_s1_dep_hit, + input iu_rv_iu6_t0_i1_s2_dep_hit, + input iu_rv_iu6_t0_i1_s3_dep_hit, + +`ifndef THREADS1 + + input iu_rv_iu6_t1_i0_vld, + input iu_rv_iu6_t1_i0_rte_lq, + input iu_rv_iu6_t1_i0_rte_sq, + input iu_rv_iu6_t1_i0_rte_fx0, + input iu_rv_iu6_t1_i0_rte_fx1, + input iu_rv_iu6_t1_i0_rte_axu0, + input iu_rv_iu6_t1_i0_rte_axu1, + input iu_rv_iu6_t1_i0_act , + input [0:31] iu_rv_iu6_t1_i0_instr, + input [0:`EFF_IFAR_WIDTH-1] iu_rv_iu6_t1_i0_ifar, + input [0:2] iu_rv_iu6_t1_i0_ucode, + input iu_rv_iu6_t1_i0_2ucode, + input [0:`UCODE_ENTRIES_ENC-1] iu_rv_iu6_t1_i0_ucode_cnt, + input [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i0_itag, + input iu_rv_iu6_t1_i0_ord, + input iu_rv_iu6_t1_i0_cord, + input iu_rv_iu6_t1_i0_spec, + input iu_rv_iu6_t1_i0_t1_v, + input [0:2] iu_rv_iu6_t1_i0_t1_t, + input [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_t1_p, + input iu_rv_iu6_t1_i0_t2_v, + input [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_t2_p, + input [0:2] iu_rv_iu6_t1_i0_t2_t, + input iu_rv_iu6_t1_i0_t3_v, + input [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_t3_p, + input [0:2] iu_rv_iu6_t1_i0_t3_t, + input iu_rv_iu6_t1_i0_s1_v, + input [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_s1_p, + input [0:2] iu_rv_iu6_t1_i0_s1_t, + input iu_rv_iu6_t1_i0_s2_v, + input [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_s2_p, + input [0:2] iu_rv_iu6_t1_i0_s2_t, + input iu_rv_iu6_t1_i0_s3_v, + input [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i0_s3_p, + input [0:2] iu_rv_iu6_t1_i0_s3_t, + input [0:3] iu_rv_iu6_t1_i0_ilat, + input [0:`G_BRANCH_LEN-1] iu_rv_iu6_t1_i0_branch, + input iu_rv_iu6_t1_i0_isLoad, + input iu_rv_iu6_t1_i0_isStore, + input [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i0_s1_itag, + input [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i0_s2_itag, + input [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i0_s3_itag, + + input iu_rv_iu6_t1_i1_vld, + input iu_rv_iu6_t1_i1_rte_lq, + input iu_rv_iu6_t1_i1_rte_sq, + input iu_rv_iu6_t1_i1_rte_fx0, + input iu_rv_iu6_t1_i1_rte_fx1, + input iu_rv_iu6_t1_i1_rte_axu0, + input iu_rv_iu6_t1_i1_rte_axu1, + input iu_rv_iu6_t1_i1_act , + input [0:31] iu_rv_iu6_t1_i1_instr, + input [0:`EFF_IFAR_WIDTH-1] iu_rv_iu6_t1_i1_ifar, + input [0:2] iu_rv_iu6_t1_i1_ucode, + input [0:`UCODE_ENTRIES_ENC-1] iu_rv_iu6_t1_i1_ucode_cnt, + input [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i1_itag, + input iu_rv_iu6_t1_i1_ord, + input iu_rv_iu6_t1_i1_cord, + input iu_rv_iu6_t1_i1_spec, + input iu_rv_iu6_t1_i1_t1_v, + input [0:2] iu_rv_iu6_t1_i1_t1_t, + input [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_t1_p, + input iu_rv_iu6_t1_i1_t2_v, + input [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_t2_p, + input [0:2] iu_rv_iu6_t1_i1_t2_t, + input iu_rv_iu6_t1_i1_t3_v, + input [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_t3_p, + input [0:2] iu_rv_iu6_t1_i1_t3_t, + input iu_rv_iu6_t1_i1_s1_v, + input [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_s1_p, + input [0:2] iu_rv_iu6_t1_i1_s1_t, + input iu_rv_iu6_t1_i1_s2_v, + input [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_s2_p, + input [0:2] iu_rv_iu6_t1_i1_s2_t, + input iu_rv_iu6_t1_i1_s3_v, + input [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_s3_p, + input [0:2] iu_rv_iu6_t1_i1_s3_t, + input [0:3] iu_rv_iu6_t1_i1_ilat, + input [0:`G_BRANCH_LEN-1] iu_rv_iu6_t1_i1_branch, + input iu_rv_iu6_t1_i1_isLoad, + input iu_rv_iu6_t1_i1_isStore, + input [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i1_s1_itag, + input [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i1_s2_itag, + input [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i1_s3_itag, + input iu_rv_iu6_t1_i1_s1_dep_hit, + input iu_rv_iu6_t1_i1_s2_dep_hit, + input iu_rv_iu6_t1_i1_s3_dep_hit, + +`endif + + //------------------------------------------------------------------------------------------------------------ + // Machine zap interface + //------------------------------------------------------------------------------------------------------------ + input [0:`THREADS-1] cp_flush, + + //------------------------------------------------------------------------------------------------------------ + // ITAG Busses + //------------------------------------------------------------------------------------------------------------ + input [0:`THREADS-1] fx0_rv_itag_vld, + input [0:`ITAG_SIZE_ENC-1] fx0_rv_itag, + input [0:`THREADS-1] fx1_rv_itag_vld, + input [0:`ITAG_SIZE_ENC-1] fx1_rv_itag, + input [0:`THREADS-1] lq_rv_itag0_vld, + input [0:`ITAG_SIZE_ENC-1] lq_rv_itag0, + input [0:`THREADS-1] lq_rv_itag1_vld, + input [0:`ITAG_SIZE_ENC-1] lq_rv_itag1, + input [0:`THREADS-1] lq_rv_itag2_vld, + input [0:`ITAG_SIZE_ENC-1] lq_rv_itag2, + input [0:`THREADS-1] axu0_rv_itag_vld, + input [0:`ITAG_SIZE_ENC-1] axu0_rv_itag, + input [0:`THREADS-1] axu1_rv_itag_vld, + input [0:`ITAG_SIZE_ENC-1] axu1_rv_itag, + + input fx0_rv_itag_abort, + input fx1_rv_itag_abort, + input lq_rv_itag0_abort, + input lq_rv_itag1_abort, + input axu0_rv_itag_abort, + input axu1_rv_itag_abort, + + + //------------------------------------------------------------------------------------------------------------ + // fx0 Outputs + //------------------------------------------------------------------------------------------------------------ + output [0:`THREADS-1] rv0_fx0_instr_i0_vld, + output rv0_fx0_instr_i0_rte_fx0, + + output [0:31] rv0_fx0_instr_i0_instr, + output [62-`EFF_IFAR_WIDTH:61] rv0_fx0_instr_i0_ifar, + output [0:2] rv0_fx0_instr_i0_ucode, + output [0:`UCODE_ENTRIES_ENC-1] rv0_fx0_instr_i0_ucode_cnt, + output [0:`ITAG_SIZE_ENC-1] rv0_fx0_instr_i0_itag, + output rv0_fx0_instr_i0_ord, + output rv0_fx0_instr_i0_cord, + output rv0_fx0_instr_i0_t1_v, + output [0:`GPR_POOL_ENC-1] rv0_fx0_instr_i0_t1_p, + output [0:2] rv0_fx0_instr_i0_t1_t, + output rv0_fx0_instr_i0_t2_v, + output [0:`GPR_POOL_ENC-1] rv0_fx0_instr_i0_t2_p, + output [0:2] rv0_fx0_instr_i0_t2_t, + output rv0_fx0_instr_i0_t3_v, + output [0:`GPR_POOL_ENC-1] rv0_fx0_instr_i0_t3_p, + output [0:2] rv0_fx0_instr_i0_t3_t, + output rv0_fx0_instr_i0_s1_v, + output [0:`GPR_POOL_ENC-1] rv0_fx0_instr_i0_s1_p, + output [0:2] rv0_fx0_instr_i0_s1_t, + output rv0_fx0_instr_i0_s2_v, + output [0:`GPR_POOL_ENC-1] rv0_fx0_instr_i0_s2_p, + output [0:2] rv0_fx0_instr_i0_s2_t, + output rv0_fx0_instr_i0_s3_v, + output [0:`GPR_POOL_ENC-1] rv0_fx0_instr_i0_s3_p, + output [0:2] rv0_fx0_instr_i0_s3_t, + output [0:3] rv0_fx0_instr_i0_ilat, + output [0:`G_BRANCH_LEN-1] rv0_fx0_instr_i0_branch, + output [0:3] rv0_fx0_instr_i0_spare, + output rv0_fx0_instr_i0_is_brick, + output [0:2] rv0_fx0_instr_i0_brick, + + output [0:`THREADS-1] rv0_fx0_instr_i1_vld, + output rv0_fx0_instr_i1_rte_fx0, + output [0:31] rv0_fx0_instr_i1_instr, + output [62-`EFF_IFAR_WIDTH:61] rv0_fx0_instr_i1_ifar, + output [0:2] rv0_fx0_instr_i1_ucode, + output [0:`UCODE_ENTRIES_ENC-1] rv0_fx0_instr_i1_ucode_cnt, + output [0:`ITAG_SIZE_ENC-1] rv0_fx0_instr_i1_itag, + output rv0_fx0_instr_i1_ord, + output rv0_fx0_instr_i1_cord, + output rv0_fx0_instr_i1_t1_v, + output [0:`GPR_POOL_ENC-1] rv0_fx0_instr_i1_t1_p, + output [0:2] rv0_fx0_instr_i1_t1_t, + output rv0_fx0_instr_i1_t2_v, + output [0:`GPR_POOL_ENC-1] rv0_fx0_instr_i1_t2_p, + output [0:2] rv0_fx0_instr_i1_t2_t, + output rv0_fx0_instr_i1_t3_v, + output [0:`GPR_POOL_ENC-1] rv0_fx0_instr_i1_t3_p, + output [0:2] rv0_fx0_instr_i1_t3_t, + output rv0_fx0_instr_i1_s1_v, + output [0:`GPR_POOL_ENC-1] rv0_fx0_instr_i1_s1_p, + output [0:2] rv0_fx0_instr_i1_s1_t, + output rv0_fx0_instr_i1_s2_v, + output [0:`GPR_POOL_ENC-1] rv0_fx0_instr_i1_s2_p, + output [0:2] rv0_fx0_instr_i1_s2_t, + output rv0_fx0_instr_i1_s3_v, + output [0:`GPR_POOL_ENC-1] rv0_fx0_instr_i1_s3_p, + output [0:2] rv0_fx0_instr_i1_s3_t, + output [0:3] rv0_fx0_instr_i1_ilat, + output [0:`G_BRANCH_LEN-1] rv0_fx0_instr_i1_branch, + output [0:3] rv0_fx0_instr_i1_spare, + output rv0_fx0_instr_i1_is_brick, + output [0:2] rv0_fx0_instr_i1_brick, + + output rv0_fx0_instr_i0_s1_dep_hit, + output [0:`ITAG_SIZE_ENC-1] rv0_fx0_instr_i0_s1_itag, + output rv0_fx0_instr_i0_s2_dep_hit, + output [0:`ITAG_SIZE_ENC-1] rv0_fx0_instr_i0_s2_itag, + output rv0_fx0_instr_i0_s3_dep_hit, + output [0:`ITAG_SIZE_ENC-1] rv0_fx0_instr_i0_s3_itag, + + output rv0_fx0_instr_i1_s1_dep_hit, + output [0:`ITAG_SIZE_ENC-1] rv0_fx0_instr_i1_s1_itag, + output rv0_fx0_instr_i1_s2_dep_hit, + output [0:`ITAG_SIZE_ENC-1] rv0_fx0_instr_i1_s2_itag, + output rv0_fx0_instr_i1_s3_dep_hit, + output [0:`ITAG_SIZE_ENC-1] rv0_fx0_instr_i1_s3_itag, + + //------------------------------------------------------------------------------------------------------------ + // fx1 Outputs + //------------------------------------------------------------------------------------------------------------ + output [0:`THREADS-1] rv0_fx1_instr_i0_vld, + output rv0_fx1_instr_i0_rte_fx1, + + output [0:31] rv0_fx1_instr_i0_instr, + output [0:2] rv0_fx1_instr_i0_ucode, + output [0:`ITAG_SIZE_ENC-1] rv0_fx1_instr_i0_itag, + output rv0_fx1_instr_i0_t1_v, + output [0:`GPR_POOL_ENC-1] rv0_fx1_instr_i0_t1_p, + output rv0_fx1_instr_i0_t2_v, + output [0:`GPR_POOL_ENC-1] rv0_fx1_instr_i0_t2_p, + output rv0_fx1_instr_i0_t3_v, + output [0:`GPR_POOL_ENC-1] rv0_fx1_instr_i0_t3_p, + output rv0_fx1_instr_i0_s1_v, + output [0:`GPR_POOL_ENC-1] rv0_fx1_instr_i0_s1_p, + output [0:2] rv0_fx1_instr_i0_s1_t, + output rv0_fx1_instr_i0_s2_v, + output [0:`GPR_POOL_ENC-1] rv0_fx1_instr_i0_s2_p, + output [0:2] rv0_fx1_instr_i0_s2_t, + output rv0_fx1_instr_i0_s3_v, + output [0:`GPR_POOL_ENC-1] rv0_fx1_instr_i0_s3_p, + output [0:2] rv0_fx1_instr_i0_s3_t, + output [0:3] rv0_fx1_instr_i0_ilat, + output rv0_fx1_instr_i0_isStore, + output [0:3] rv0_fx1_instr_i0_spare, + output rv0_fx1_instr_i0_is_brick, + output [0:2] rv0_fx1_instr_i0_brick, + + output [0:`THREADS-1] rv0_fx1_instr_i1_vld, + output rv0_fx1_instr_i1_rte_fx1, + output [0:31] rv0_fx1_instr_i1_instr, + output [0:2] rv0_fx1_instr_i1_ucode, + output [0:`ITAG_SIZE_ENC-1] rv0_fx1_instr_i1_itag, + output rv0_fx1_instr_i1_t1_v, + output [0:`GPR_POOL_ENC-1] rv0_fx1_instr_i1_t1_p, + output rv0_fx1_instr_i1_t2_v, + output [0:`GPR_POOL_ENC-1] rv0_fx1_instr_i1_t2_p, + output rv0_fx1_instr_i1_t3_v, + output [0:`GPR_POOL_ENC-1] rv0_fx1_instr_i1_t3_p, + output rv0_fx1_instr_i1_s1_v, + output [0:`GPR_POOL_ENC-1] rv0_fx1_instr_i1_s1_p, + output [0:2] rv0_fx1_instr_i1_s1_t, + output rv0_fx1_instr_i1_s2_v, + output [0:`GPR_POOL_ENC-1] rv0_fx1_instr_i1_s2_p, + output [0:2] rv0_fx1_instr_i1_s2_t, + output rv0_fx1_instr_i1_s3_v, + output [0:`GPR_POOL_ENC-1] rv0_fx1_instr_i1_s3_p, + output [0:2] rv0_fx1_instr_i1_s3_t, + output [0:3] rv0_fx1_instr_i1_ilat, + output rv0_fx1_instr_i1_isStore, + output [0:3] rv0_fx1_instr_i1_spare, + output rv0_fx1_instr_i1_is_brick, + output [0:2] rv0_fx1_instr_i1_brick, + + output rv0_fx1_instr_i0_s1_dep_hit, + output [0:`ITAG_SIZE_ENC-1] rv0_fx1_instr_i0_s1_itag, + output rv0_fx1_instr_i0_s2_dep_hit, + output [0:`ITAG_SIZE_ENC-1] rv0_fx1_instr_i0_s2_itag, + output rv0_fx1_instr_i0_s3_dep_hit, + output [0:`ITAG_SIZE_ENC-1] rv0_fx1_instr_i0_s3_itag, + + output rv0_fx1_instr_i1_s1_dep_hit, + output [0:`ITAG_SIZE_ENC-1] rv0_fx1_instr_i1_s1_itag, + output rv0_fx1_instr_i1_s2_dep_hit, + output [0:`ITAG_SIZE_ENC-1] rv0_fx1_instr_i1_s2_itag, + output rv0_fx1_instr_i1_s3_dep_hit, + output [0:`ITAG_SIZE_ENC-1] rv0_fx1_instr_i1_s3_itag, + + //------------------------------------------------------------------------------------------------------------ + // lq Outputs + //------------------------------------------------------------------------------------------------------------ + output [0:`THREADS-1] rv0_lq_instr_i0_vld, + output rv0_lq_instr_i0_rte_lq, + + output [0:31] rv0_lq_instr_i0_instr, + output [0:2] rv0_lq_instr_i0_ucode, + output [0:`UCODE_ENTRIES_ENC-1] rv0_lq_instr_i0_ucode_cnt, + output [0:`ITAG_SIZE_ENC-1] rv0_lq_instr_i0_itag, + output rv0_lq_instr_i0_ord, + output rv0_lq_instr_i0_cord, + output rv0_lq_instr_i0_spec, + output rv0_lq_instr_i0_t1_v, + output [0:`GPR_POOL_ENC-1] rv0_lq_instr_i0_t1_p, + output rv0_lq_instr_i0_t2_v, + output [0:`GPR_POOL_ENC-1] rv0_lq_instr_i0_t2_p, + output [0:2] rv0_lq_instr_i0_t2_t, + output rv0_lq_instr_i0_t3_v, + output [0:`GPR_POOL_ENC-1] rv0_lq_instr_i0_t3_p, + output [0:2] rv0_lq_instr_i0_t3_t, + output rv0_lq_instr_i0_s1_v, + output [0:`GPR_POOL_ENC-1] rv0_lq_instr_i0_s1_p, + output [0:2] rv0_lq_instr_i0_s1_t, + output rv0_lq_instr_i0_s2_v, + output [0:`GPR_POOL_ENC-1] rv0_lq_instr_i0_s2_p, + output [0:2] rv0_lq_instr_i0_s2_t, + output rv0_lq_instr_i0_isLoad, + output [0:3] rv0_lq_instr_i0_spare, + output rv0_lq_instr_i0_is_brick, + output [0:2] rv0_lq_instr_i0_brick, + + output [0:`THREADS-1] rv0_lq_instr_i1_vld, + output rv0_lq_instr_i1_rte_lq, + output [0:31] rv0_lq_instr_i1_instr, + output [0:2] rv0_lq_instr_i1_ucode, + output [0:`UCODE_ENTRIES_ENC-1] rv0_lq_instr_i1_ucode_cnt, + output [0:`ITAG_SIZE_ENC-1] rv0_lq_instr_i1_itag, + output rv0_lq_instr_i1_ord, + output rv0_lq_instr_i1_cord, + output rv0_lq_instr_i1_spec, + output rv0_lq_instr_i1_t1_v, + output [0:`GPR_POOL_ENC-1] rv0_lq_instr_i1_t1_p, + output rv0_lq_instr_i1_t2_v, + output [0:`GPR_POOL_ENC-1] rv0_lq_instr_i1_t2_p, + output [0:2] rv0_lq_instr_i1_t2_t, + output rv0_lq_instr_i1_t3_v, + output [0:`GPR_POOL_ENC-1] rv0_lq_instr_i1_t3_p, + output [0:2] rv0_lq_instr_i1_t3_t, + output rv0_lq_instr_i1_s1_v, + output [0:`GPR_POOL_ENC-1] rv0_lq_instr_i1_s1_p, + output [0:2] rv0_lq_instr_i1_s1_t, + output rv0_lq_instr_i1_s2_v, + output [0:`GPR_POOL_ENC-1] rv0_lq_instr_i1_s2_p, + output [0:2] rv0_lq_instr_i1_s2_t, + output rv0_lq_instr_i1_isLoad, + output [0:3] rv0_lq_instr_i1_spare, + output rv0_lq_instr_i1_is_brick, + output [0:2] rv0_lq_instr_i1_brick, + + output [0:`THREADS-1] rv_lq_rv1_i0_vld, + output rv_lq_rv1_i0_ucode_preissue, + output rv_lq_rv1_i0_2ucode, + output [0:`UCODE_ENTRIES_ENC-1] rv_lq_rv1_i0_ucode_cnt, + output [0:2] rv_lq_rv1_i0_s3_t, + output rv_lq_rv1_i0_isLoad, + output rv_lq_rv1_i0_isStore, + output [0:`ITAG_SIZE_ENC-1] rv_lq_rv1_i0_itag, + output rv_lq_rv1_i0_rte_lq, + output rv_lq_rv1_i0_rte_sq, + output [61-`PF_IAR_BITS+1:61] rv_lq_rv1_i0_ifar, + + output [0:`THREADS-1] rv_lq_rv1_i1_vld, + output rv_lq_rv1_i1_ucode_preissue, + output rv_lq_rv1_i1_2ucode, + output [0:`UCODE_ENTRIES_ENC-1] rv_lq_rv1_i1_ucode_cnt, + output [0:2] rv_lq_rv1_i1_s3_t, + output rv_lq_rv1_i1_isLoad, + output rv_lq_rv1_i1_isStore, + output [0:`ITAG_SIZE_ENC-1] rv_lq_rv1_i1_itag, + output rv_lq_rv1_i1_rte_lq, + output rv_lq_rv1_i1_rte_sq, + output [61-`PF_IAR_BITS+1:61] rv_lq_rv1_i1_ifar, + + output rv0_lq_instr_i0_s1_dep_hit, + output [0:`ITAG_SIZE_ENC-1] rv0_lq_instr_i0_s1_itag, + output rv0_lq_instr_i0_s2_dep_hit, + output [0:`ITAG_SIZE_ENC-1] rv0_lq_instr_i0_s2_itag, + + output rv0_lq_instr_i1_s1_dep_hit, + output [0:`ITAG_SIZE_ENC-1] rv0_lq_instr_i1_s1_itag, + output rv0_lq_instr_i1_s2_dep_hit, + output [0:`ITAG_SIZE_ENC-1] rv0_lq_instr_i1_s2_itag, + + //------------------------------------------------------------------------------------------------------------ + // axu0 Outputs + //------------------------------------------------------------------------------------------------------------ + output [0:`THREADS-1] rv0_axu0_instr_i0_vld, + output rv0_axu0_instr_i0_rte_axu0, + + output [0:31] rv0_axu0_instr_i0_instr, + output [0:2] rv0_axu0_instr_i0_ucode, + output [0:`ITAG_SIZE_ENC-1] rv0_axu0_instr_i0_itag, + output rv0_axu0_instr_i0_ord, + output rv0_axu0_instr_i0_cord, + output rv0_axu0_instr_i0_t1_v, + output [0:`GPR_POOL_ENC-1] rv0_axu0_instr_i0_t1_p, + output [0:`GPR_POOL_ENC-1] rv0_axu0_instr_i0_t2_p, + output [0:`GPR_POOL_ENC-1] rv0_axu0_instr_i0_t3_p, + output rv0_axu0_instr_i0_s1_v, + output [0:`GPR_POOL_ENC-1] rv0_axu0_instr_i0_s1_p, + output rv0_axu0_instr_i0_s2_v, + output [0:`GPR_POOL_ENC-1] rv0_axu0_instr_i0_s2_p, + output rv0_axu0_instr_i0_s3_v, + output [0:`GPR_POOL_ENC-1] rv0_axu0_instr_i0_s3_p, + output rv0_axu0_instr_i0_isStore, + output [0:3] rv0_axu0_instr_i0_spare, + + output [0:`THREADS-1] rv0_axu0_instr_i1_vld, + output rv0_axu0_instr_i1_rte_axu0, + output [0:31] rv0_axu0_instr_i1_instr, + output [0:2] rv0_axu0_instr_i1_ucode, + output [0:`ITAG_SIZE_ENC-1] rv0_axu0_instr_i1_itag, + output rv0_axu0_instr_i1_ord, + output rv0_axu0_instr_i1_cord, + output rv0_axu0_instr_i1_t1_v, + output [0:`GPR_POOL_ENC-1] rv0_axu0_instr_i1_t1_p, + output [0:`GPR_POOL_ENC-1] rv0_axu0_instr_i1_t2_p, + output [0:`GPR_POOL_ENC-1] rv0_axu0_instr_i1_t3_p, + output rv0_axu0_instr_i1_s1_v, + output [0:`GPR_POOL_ENC-1] rv0_axu0_instr_i1_s1_p, + output rv0_axu0_instr_i1_s2_v, + output [0:`GPR_POOL_ENC-1] rv0_axu0_instr_i1_s2_p, + output rv0_axu0_instr_i1_s3_v, + output [0:`GPR_POOL_ENC-1] rv0_axu0_instr_i1_s3_p, + output rv0_axu0_instr_i1_isStore, + output [0:3] rv0_axu0_instr_i1_spare, + + output rv0_axu0_instr_i0_s1_dep_hit, + output [0:`ITAG_SIZE_ENC-1] rv0_axu0_instr_i0_s1_itag, + output rv0_axu0_instr_i0_s2_dep_hit, + output [0:`ITAG_SIZE_ENC-1] rv0_axu0_instr_i0_s2_itag, + output rv0_axu0_instr_i0_s3_dep_hit, + output [0:`ITAG_SIZE_ENC-1] rv0_axu0_instr_i0_s3_itag, + + output rv0_axu0_instr_i1_s1_dep_hit, + output [0:`ITAG_SIZE_ENC-1] rv0_axu0_instr_i1_s1_itag, + output rv0_axu0_instr_i1_s2_dep_hit, + output [0:`ITAG_SIZE_ENC-1] rv0_axu0_instr_i1_s2_itag, + output rv0_axu0_instr_i1_s3_dep_hit, + output [0:`ITAG_SIZE_ENC-1] rv0_axu0_instr_i1_s3_itag, + + //------------------------------------------------------------------------------------------------------------ + // Pervasive + //------------------------------------------------------------------------------------------------------------ + inout vdd, + inout gnd, + (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) // nclk + input [0:`NCLK_WIDTH-1] nclk, + + input func_sl_thold_1, + input sg_1, + input clkoff_b, + input act_dis, + input ccflush_dc, + + input d_mode, + input delay_lclkr, + input mpw1_b, + input mpw2_b, + input scan_in, + + output scan_out + + ); + + //!! Bugspray Include: rv_deps ; + + + wire tiup; + wire [0:`THREADS-1] iu_xx_zap; + + + wire iu6_t0_i0_act; + wire iu6_t0_i1_act; + wire rv0_t0_i0_act; + wire rv0_t0_i1_act; + + + wire rv0_t0_i0_vld_d; + wire rv0_t0_i0_rte_lq_d; + wire rv0_t0_i0_rte_sq_d; + wire rv0_t0_i0_rte_fx0_d; + wire rv0_t0_i0_rte_fx1_d; + wire rv0_t0_i0_rte_axu0_d; + wire rv0_t0_i0_rte_axu1_d; + wire [0:31] rv0_t0_i0_instr_d; + wire [62-`EFF_IFAR_WIDTH:61] rv0_t0_i0_ifar_d; + wire [0:2] rv0_t0_i0_ucode_d; + wire rv0_t0_i0_2ucode_d; + wire [0:`UCODE_ENTRIES_ENC-1] rv0_t0_i0_ucode_cnt_d; + wire [0:`ITAG_SIZE_ENC-1] rv0_t0_i0_itag_d; + wire rv0_t0_i0_ord_d; + wire rv0_t0_i0_cord_d; + wire rv0_t0_i0_spec_d; + wire rv0_t0_i0_t1_v_d; + wire [0:`GPR_POOL_ENC-1] rv0_t0_i0_t1_p_d; + wire [0:2] rv0_t0_i0_t1_t_d; + wire rv0_t0_i0_t2_v_d; + wire [0:`GPR_POOL_ENC-1] rv0_t0_i0_t2_p_d; + wire [0:2] rv0_t0_i0_t2_t_d; + wire rv0_t0_i0_t3_v_d; + wire [0:`GPR_POOL_ENC-1] rv0_t0_i0_t3_p_d; + wire [0:2] rv0_t0_i0_t3_t_d; + wire rv0_t0_i0_s1_v_d; + wire [0:`GPR_POOL_ENC-1] rv0_t0_i0_s1_p_d; + wire [0:2] rv0_t0_i0_s1_t_d; + wire rv0_t0_i0_s2_v_d; + wire [0:`GPR_POOL_ENC-1] rv0_t0_i0_s2_p_d; + wire [0:2] rv0_t0_i0_s2_t_d; + wire rv0_t0_i0_s3_v_d; + wire [0:`GPR_POOL_ENC-1] rv0_t0_i0_s3_p_d; + wire [0:2] rv0_t0_i0_s3_t_d; + wire [0:3] rv0_t0_i0_ilat_d; + wire [0:`G_BRANCH_LEN-1] rv0_t0_i0_branch_d; + wire rv0_t0_i0_isLoad_d; + wire rv0_t0_i0_isStore_d; + wire [0:`ITAG_SIZE_ENC-1] rv0_t0_i0_s1_itag_d; + wire [0:`ITAG_SIZE_ENC-1] rv0_t0_i0_s2_itag_d; + wire [0:`ITAG_SIZE_ENC-1] rv0_t0_i0_s3_itag_d; + wire [0:3] rv0_t0_i0_spare_d; + + wire rv0_t0_i1_vld_d; + wire rv0_t0_i1_rte_lq_d; + wire rv0_t0_i1_rte_sq_d; + wire rv0_t0_i1_rte_fx0_d; + wire rv0_t0_i1_rte_fx1_d; + wire rv0_t0_i1_rte_axu0_d; + wire rv0_t0_i1_rte_axu1_d; + wire [0:31] rv0_t0_i1_instr_d; + wire [62-`EFF_IFAR_WIDTH:61] rv0_t0_i1_ifar_d; + wire [0:2] rv0_t0_i1_ucode_d; + wire [0:`UCODE_ENTRIES_ENC-1] rv0_t0_i1_ucode_cnt_d; + wire [0:`ITAG_SIZE_ENC-1] rv0_t0_i1_itag_d; + wire rv0_t0_i1_ord_d; + wire rv0_t0_i1_cord_d; + wire rv0_t0_i1_spec_d; + wire rv0_t0_i1_t1_v_d; + wire [0:`GPR_POOL_ENC-1] rv0_t0_i1_t1_p_d; + wire [0:2] rv0_t0_i1_t1_t_d; + wire rv0_t0_i1_t2_v_d; + wire [0:`GPR_POOL_ENC-1] rv0_t0_i1_t2_p_d; + wire [0:2] rv0_t0_i1_t2_t_d; + wire rv0_t0_i1_t3_v_d; + wire [0:`GPR_POOL_ENC-1] rv0_t0_i1_t3_p_d; + wire [0:2] rv0_t0_i1_t3_t_d; + wire rv0_t0_i1_s1_v_d; + wire [0:`GPR_POOL_ENC-1] rv0_t0_i1_s1_p_d; + wire [0:2] rv0_t0_i1_s1_t_d; + wire rv0_t0_i1_s2_v_d; + wire [0:`GPR_POOL_ENC-1] rv0_t0_i1_s2_p_d; + wire [0:2] rv0_t0_i1_s2_t_d; + wire rv0_t0_i1_s3_v_d; + wire [0:`GPR_POOL_ENC-1] rv0_t0_i1_s3_p_d; + wire [0:2] rv0_t0_i1_s3_t_d; + wire [0:3] rv0_t0_i1_ilat_d; + wire [0:`G_BRANCH_LEN-1] rv0_t0_i1_branch_d; + wire rv0_t0_i1_isLoad_d; + wire rv0_t0_i1_isStore_d; + wire [0:`ITAG_SIZE_ENC-1] rv0_t0_i1_s1_itag_d; + wire [0:`ITAG_SIZE_ENC-1] rv0_t0_i1_s2_itag_d; + wire [0:`ITAG_SIZE_ENC-1] rv0_t0_i1_s3_itag_d; + wire rv0_t0_i1_s1_dep_hit_d; + wire rv0_t0_i1_s2_dep_hit_d; + wire rv0_t0_i1_s3_dep_hit_d; + + wire [0:3] rv0_t0_i1_spare_d; + + wire rv0_t0_i0_vld_q; + wire rv0_t0_i0_rte_lq_q; + wire rv0_t0_i0_rte_sq_q; + wire rv0_t0_i0_rte_fx0_q; + wire rv0_t0_i0_rte_fx1_q; + wire rv0_t0_i0_rte_axu0_q; + (* analysis_not_referenced="true" *) + wire rv0_t0_i0_rte_axu1_q; + wire [0:31] rv0_t0_i0_instr_q; + wire [62-`EFF_IFAR_WIDTH:61] rv0_t0_i0_ifar_q; + wire [0:2] rv0_t0_i0_ucode_q; + wire rv0_t0_i0_2ucode_q; + wire [0:`UCODE_ENTRIES_ENC-1] rv0_t0_i0_ucode_cnt_q; + wire [0:`ITAG_SIZE_ENC-1] rv0_t0_i0_itag_q; + wire rv0_t0_i0_ord_q; + wire rv0_t0_i0_cord_q; + wire rv0_t0_i0_spec_q; + wire rv0_t0_i0_t1_v_q; + wire [0:`GPR_POOL_ENC-1] rv0_t0_i0_t1_p_q; + wire [0:2] rv0_t0_i0_t1_t_q; + wire rv0_t0_i0_t2_v_q; + wire [0:`GPR_POOL_ENC-1] rv0_t0_i0_t2_p_q; + wire [0:2] rv0_t0_i0_t2_t_q; + wire rv0_t0_i0_t3_v_q; + wire [0:`GPR_POOL_ENC-1] rv0_t0_i0_t3_p_q; + wire [0:2] rv0_t0_i0_t3_t_q; + wire rv0_t0_i0_s1_v_q; + wire [0:`GPR_POOL_ENC-1] rv0_t0_i0_s1_p_q; + wire [0:2] rv0_t0_i0_s1_t_q; + wire rv0_t0_i0_s2_v_q; + wire [0:`GPR_POOL_ENC-1] rv0_t0_i0_s2_p_q; + wire [0:2] rv0_t0_i0_s2_t_q; + wire rv0_t0_i0_s3_v_q; + wire [0:`GPR_POOL_ENC-1] rv0_t0_i0_s3_p_q; + wire [0:2] rv0_t0_i0_s3_t_q; + wire [0:3] rv0_t0_i0_ilat_q; + wire [0:`G_BRANCH_LEN-1] rv0_t0_i0_branch_q; + wire rv0_t0_i0_isLoad_q; + wire rv0_t0_i0_isStore_q; + wire [0:`ITAG_SIZE_ENC-1] rv0_t0_i0_s1_itag_q; + wire [0:`ITAG_SIZE_ENC-1] rv0_t0_i0_s2_itag_q; + wire [0:`ITAG_SIZE_ENC-1] rv0_t0_i0_s3_itag_q; + wire [0:3] rv0_t0_i0_spare_q; + + wire rv0_t0_i1_vld_q; + wire rv0_t0_i1_rte_lq_q; + wire rv0_t0_i1_rte_sq_q; + wire rv0_t0_i1_rte_fx0_q; + wire rv0_t0_i1_rte_fx1_q; + wire rv0_t0_i1_rte_axu0_q; + (* analysis_not_referenced="true" *) + wire rv0_t0_i1_rte_axu1_q; + wire [0:31] rv0_t0_i1_instr_q; + wire [62-`EFF_IFAR_WIDTH:61] rv0_t0_i1_ifar_q; + wire [0:2] rv0_t0_i1_ucode_q; + wire [0:`UCODE_ENTRIES_ENC-1] rv0_t0_i1_ucode_cnt_q; + wire [0:`ITAG_SIZE_ENC-1] rv0_t0_i1_itag_q; + wire rv0_t0_i1_ord_q; + wire rv0_t0_i1_cord_q; + wire rv0_t0_i1_spec_q; + wire rv0_t0_i1_t1_v_q; + wire [0:`GPR_POOL_ENC-1] rv0_t0_i1_t1_p_q; + wire [0:2] rv0_t0_i1_t1_t_q; + wire rv0_t0_i1_t2_v_q; + wire [0:`GPR_POOL_ENC-1] rv0_t0_i1_t2_p_q; + wire [0:2] rv0_t0_i1_t2_t_q; + wire rv0_t0_i1_t3_v_q; + wire [0:`GPR_POOL_ENC-1] rv0_t0_i1_t3_p_q; + wire [0:2] rv0_t0_i1_t3_t_q; + wire rv0_t0_i1_s1_v_q; + wire [0:`GPR_POOL_ENC-1] rv0_t0_i1_s1_p_q; + wire [0:2] rv0_t0_i1_s1_t_q; + wire rv0_t0_i1_s2_v_q; + wire [0:`GPR_POOL_ENC-1] rv0_t0_i1_s2_p_q; + wire [0:2] rv0_t0_i1_s2_t_q; + wire rv0_t0_i1_s3_v_q; + wire [0:`GPR_POOL_ENC-1] rv0_t0_i1_s3_p_q; + wire [0:2] rv0_t0_i1_s3_t_q; + wire [0:3] rv0_t0_i1_ilat_q; + wire [0:`G_BRANCH_LEN-1] rv0_t0_i1_branch_q; + wire rv0_t0_i1_isLoad_q; + wire rv0_t0_i1_isStore_q; + wire [0:`ITAG_SIZE_ENC-1] rv0_t0_i1_s1_itag_q; + wire [0:`ITAG_SIZE_ENC-1] rv0_t0_i1_s2_itag_q; + wire [0:`ITAG_SIZE_ENC-1] rv0_t0_i1_s3_itag_q; + wire rv0_t0_i1_s1_dep_hit_q; + wire rv0_t0_i1_s2_dep_hit_q; + wire rv0_t0_i1_s3_dep_hit_q; + wire [0:3] rv0_t0_i1_spare_q; + + + + wire rv0_t0_i0_is_brick; + wire [0:2] rv0_t0_i0_brick; + wire rv0_t0_i1_is_brick; + wire [0:2] rv0_t0_i1_brick; + + wire [0:3] rv0_t0_i0_ilat; + wire [0:3] rv0_t0_i1_ilat; + +`ifndef THREADS1 + wire iu6_t1_i0_act; + wire iu6_t1_i1_act; + wire rv0_t1_i0_act; + wire rv0_t1_i1_act; + + + wire rv0_t1_i0_vld_d; + wire rv0_t1_i0_rte_lq_d; + wire rv0_t1_i0_rte_sq_d; + wire rv0_t1_i0_rte_fx0_d; + wire rv0_t1_i0_rte_fx1_d; + wire rv0_t1_i0_rte_axu0_d; + wire rv0_t1_i0_rte_axu1_d; + wire [0:31] rv0_t1_i0_instr_d; + wire [62-`EFF_IFAR_WIDTH:61] rv0_t1_i0_ifar_d; + wire [0:2] rv0_t1_i0_ucode_d; + wire rv0_t1_i0_2ucode_d; + wire [0:`UCODE_ENTRIES_ENC-1] rv0_t1_i0_ucode_cnt_d; + wire [0:`ITAG_SIZE_ENC-1] rv0_t1_i0_itag_d; + wire rv0_t1_i0_ord_d; + wire rv0_t1_i0_cord_d; + wire rv0_t1_i0_spec_d; + wire rv0_t1_i0_t1_v_d; + wire [0:`GPR_POOL_ENC-1] rv0_t1_i0_t1_p_d; + wire [0:2] rv0_t1_i0_t1_t_d; + wire rv0_t1_i0_t2_v_d; + wire [0:`GPR_POOL_ENC-1] rv0_t1_i0_t2_p_d; + wire [0:2] rv0_t1_i0_t2_t_d; + wire rv0_t1_i0_t3_v_d; + wire [0:`GPR_POOL_ENC-1] rv0_t1_i0_t3_p_d; + wire [0:2] rv0_t1_i0_t3_t_d; + wire rv0_t1_i0_s1_v_d; + wire [0:`GPR_POOL_ENC-1] rv0_t1_i0_s1_p_d; + wire [0:2] rv0_t1_i0_s1_t_d; + wire rv0_t1_i0_s2_v_d; + wire [0:`GPR_POOL_ENC-1] rv0_t1_i0_s2_p_d; + wire [0:2] rv0_t1_i0_s2_t_d; + wire rv0_t1_i0_s3_v_d; + wire [0:`GPR_POOL_ENC-1] rv0_t1_i0_s3_p_d; + wire [0:2] rv0_t1_i0_s3_t_d; + wire [0:3] rv0_t1_i0_ilat_d; + wire [0:`G_BRANCH_LEN-1] rv0_t1_i0_branch_d; + wire rv0_t1_i0_isLoad_d; + wire rv0_t1_i0_isStore_d; + wire [0:`ITAG_SIZE_ENC-1] rv0_t1_i0_s1_itag_d; + wire [0:`ITAG_SIZE_ENC-1] rv0_t1_i0_s2_itag_d; + wire [0:`ITAG_SIZE_ENC-1] rv0_t1_i0_s3_itag_d; + wire [0:3] rv0_t1_i0_spare_d; + + wire rv0_t1_i1_vld_d; + wire rv0_t1_i1_rte_lq_d; + wire rv0_t1_i1_rte_sq_d; + wire rv0_t1_i1_rte_fx0_d; + wire rv0_t1_i1_rte_fx1_d; + wire rv0_t1_i1_rte_axu0_d; + wire rv0_t1_i1_rte_axu1_d; + wire [0:31] rv0_t1_i1_instr_d; + wire [62-`EFF_IFAR_WIDTH:61] rv0_t1_i1_ifar_d; + wire [0:2] rv0_t1_i1_ucode_d; + wire [0:`UCODE_ENTRIES_ENC-1] rv0_t1_i1_ucode_cnt_d; + wire [0:`ITAG_SIZE_ENC-1] rv0_t1_i1_itag_d; + wire rv0_t1_i1_ord_d; + wire rv0_t1_i1_cord_d; + wire rv0_t1_i1_spec_d; + wire rv0_t1_i1_t1_v_d; + wire [0:`GPR_POOL_ENC-1] rv0_t1_i1_t1_p_d; + wire [0:2] rv0_t1_i1_t1_t_d; + wire rv0_t1_i1_t2_v_d; + wire [0:`GPR_POOL_ENC-1] rv0_t1_i1_t2_p_d; + wire [0:2] rv0_t1_i1_t2_t_d; + wire rv0_t1_i1_t3_v_d; + wire [0:`GPR_POOL_ENC-1] rv0_t1_i1_t3_p_d; + wire [0:2] rv0_t1_i1_t3_t_d; + wire rv0_t1_i1_s1_v_d; + wire [0:`GPR_POOL_ENC-1] rv0_t1_i1_s1_p_d; + wire [0:2] rv0_t1_i1_s1_t_d; + wire rv0_t1_i1_s2_v_d; + wire [0:`GPR_POOL_ENC-1] rv0_t1_i1_s2_p_d; + wire [0:2] rv0_t1_i1_s2_t_d; + wire rv0_t1_i1_s3_v_d; + wire [0:`GPR_POOL_ENC-1] rv0_t1_i1_s3_p_d; + wire [0:2] rv0_t1_i1_s3_t_d; + wire [0:3] rv0_t1_i1_ilat_d; + wire [0:`G_BRANCH_LEN-1] rv0_t1_i1_branch_d; + wire rv0_t1_i1_isLoad_d; + wire rv0_t1_i1_isStore_d; + wire [0:`ITAG_SIZE_ENC-1] rv0_t1_i1_s1_itag_d; + wire [0:`ITAG_SIZE_ENC-1] rv0_t1_i1_s2_itag_d; + wire [0:`ITAG_SIZE_ENC-1] rv0_t1_i1_s3_itag_d; + wire rv0_t1_i1_s1_dep_hit_d; + wire rv0_t1_i1_s2_dep_hit_d; + wire rv0_t1_i1_s3_dep_hit_d; + wire [0:3] rv0_t1_i1_spare_d; + + wire rv0_t1_i0_vld_q; + wire rv0_t1_i0_rte_lq_q; + wire rv0_t1_i0_rte_sq_q; + wire rv0_t1_i0_rte_fx0_q; + wire rv0_t1_i0_rte_fx1_q; + wire rv0_t1_i0_rte_axu0_q; + (* analysis_not_referenced="true" *) + wire rv0_t1_i0_rte_axu1_q; + wire [0:31] rv0_t1_i0_instr_q; + wire [62-`EFF_IFAR_WIDTH:61] rv0_t1_i0_ifar_q; + wire [0:2] rv0_t1_i0_ucode_q; + wire rv0_t1_i0_2ucode_q; + wire [0:`UCODE_ENTRIES_ENC-1] rv0_t1_i0_ucode_cnt_q; + wire [0:`ITAG_SIZE_ENC-1] rv0_t1_i0_itag_q; + wire rv0_t1_i0_ord_q; + wire rv0_t1_i0_cord_q; + wire rv0_t1_i0_spec_q; + wire rv0_t1_i0_t1_v_q; + wire [0:`GPR_POOL_ENC-1] rv0_t1_i0_t1_p_q; + wire [0:2] rv0_t1_i0_t1_t_q; + wire rv0_t1_i0_t2_v_q; + wire [0:`GPR_POOL_ENC-1] rv0_t1_i0_t2_p_q; + wire [0:2] rv0_t1_i0_t2_t_q; + wire rv0_t1_i0_t3_v_q; + wire [0:`GPR_POOL_ENC-1] rv0_t1_i0_t3_p_q; + wire [0:2] rv0_t1_i0_t3_t_q; + wire rv0_t1_i0_s1_v_q; + wire [0:`GPR_POOL_ENC-1] rv0_t1_i0_s1_p_q; + wire [0:2] rv0_t1_i0_s1_t_q; + wire rv0_t1_i0_s2_v_q; + wire [0:`GPR_POOL_ENC-1] rv0_t1_i0_s2_p_q; + wire [0:2] rv0_t1_i0_s2_t_q; + wire rv0_t1_i0_s3_v_q; + wire [0:`GPR_POOL_ENC-1] rv0_t1_i0_s3_p_q; + wire [0:2] rv0_t1_i0_s3_t_q; + wire [0:3] rv0_t1_i0_ilat_q; + wire [0:`G_BRANCH_LEN-1] rv0_t1_i0_branch_q; + wire rv0_t1_i0_isLoad_q; + wire rv0_t1_i0_isStore_q; + wire [0:`ITAG_SIZE_ENC-1] rv0_t1_i0_s1_itag_q; + wire [0:`ITAG_SIZE_ENC-1] rv0_t1_i0_s2_itag_q; + wire [0:`ITAG_SIZE_ENC-1] rv0_t1_i0_s3_itag_q; + wire [0:3] rv0_t1_i0_spare_q; + + wire rv0_t1_i1_vld_q; + wire rv0_t1_i1_rte_lq_q; + wire rv0_t1_i1_rte_sq_q; + wire rv0_t1_i1_rte_fx0_q; + wire rv0_t1_i1_rte_fx1_q; + wire rv0_t1_i1_rte_axu0_q; + (* analysis_not_referenced="true" *) + wire rv0_t1_i1_rte_axu1_q; + wire [0:31] rv0_t1_i1_instr_q; + wire [62-`EFF_IFAR_WIDTH:61] rv0_t1_i1_ifar_q; + wire [0:2] rv0_t1_i1_ucode_q; + wire [0:`UCODE_ENTRIES_ENC-1] rv0_t1_i1_ucode_cnt_q; + wire [0:`ITAG_SIZE_ENC-1] rv0_t1_i1_itag_q; + wire rv0_t1_i1_ord_q; + wire rv0_t1_i1_cord_q; + wire rv0_t1_i1_spec_q; + wire rv0_t1_i1_t1_v_q; + wire [0:`GPR_POOL_ENC-1] rv0_t1_i1_t1_p_q; + wire [0:2] rv0_t1_i1_t1_t_q; + wire rv0_t1_i1_t2_v_q; + wire [0:`GPR_POOL_ENC-1] rv0_t1_i1_t2_p_q; + wire [0:2] rv0_t1_i1_t2_t_q; + wire rv0_t1_i1_t3_v_q; + wire [0:`GPR_POOL_ENC-1] rv0_t1_i1_t3_p_q; + wire [0:2] rv0_t1_i1_t3_t_q; + wire rv0_t1_i1_s1_v_q; + wire [0:`GPR_POOL_ENC-1] rv0_t1_i1_s1_p_q; + wire [0:2] rv0_t1_i1_s1_t_q; + wire rv0_t1_i1_s2_v_q; + wire [0:`GPR_POOL_ENC-1] rv0_t1_i1_s2_p_q; + wire [0:2] rv0_t1_i1_s2_t_q; + wire rv0_t1_i1_s3_v_q; + wire [0:`GPR_POOL_ENC-1] rv0_t1_i1_s3_p_q; + wire [0:2] rv0_t1_i1_s3_t_q; + wire [0:3] rv0_t1_i1_ilat_q; + wire [0:`G_BRANCH_LEN-1] rv0_t1_i1_branch_q; + wire rv0_t1_i1_isLoad_q; + wire rv0_t1_i1_isStore_q; + wire [0:`ITAG_SIZE_ENC-1] rv0_t1_i1_s1_itag_q; + wire [0:`ITAG_SIZE_ENC-1] rv0_t1_i1_s2_itag_q; + wire [0:`ITAG_SIZE_ENC-1] rv0_t1_i1_s3_itag_q; + wire rv0_t1_i1_s1_dep_hit_q; + wire rv0_t1_i1_s2_dep_hit_q; + wire rv0_t1_i1_s3_dep_hit_q; + wire [0:3] rv0_t1_i1_spare_q; + + + wire rv0_t1_i0_is_brick; + wire [0:2] rv0_t1_i0_brick; + wire rv0_t1_i1_is_brick; + wire [0:2] rv0_t1_i1_brick; + + wire [0:3] rv0_t1_i0_ilat; + wire [0:3] rv0_t1_i1_ilat; + +`endif + + wire rv0_lq_instr_i0_s3_v; + wire [0:5] rv0_lq_instr_i0_s3_p; + wire force_t; + + wire [0:`THREADS-1] rv0_instr_i0_flushed_d; + wire [0:`THREADS-1] rv0_instr_i1_flushed_d; + wire [0:`THREADS-1] rv0_instr_i0_flushed_q; + wire [0:`THREADS-1] rv0_instr_i1_flushed_q; + + + wire [0:`THREADS-1] rv0_instr_i0_dep_val; + wire [0:`THREADS-1] rv0_instr_i1_dep_val; + + wire [0:`THREADS-1] rv0_instr_i0_s1_dep_hit; + wire [0:`THREADS-1] rv0_instr_i0_s2_dep_hit; + wire [0:`THREADS-1] rv0_instr_i0_s3_dep_hit; + wire [0:`THREADS-1] rv0_instr_i1_s1_dep_hit; + wire [0:`THREADS-1] rv0_instr_i1_s2_dep_hit; + wire [0:`THREADS-1] rv0_instr_i1_s3_dep_hit; + + wire [0:`THREADS-1] rv0_instr_i1_local_s1_dep_hit; + wire [0:`THREADS-1] rv0_instr_i1_local_s2_dep_hit; + wire [0:`THREADS-1] rv0_instr_i1_local_s3_dep_hit; + wire [0:`THREADS-1] rv0_instr_i1_s1_dep_hit_loc; + wire [0:`THREADS-1] rv0_instr_i1_s2_dep_hit_loc; + wire [0:`THREADS-1] rv0_instr_i1_s3_dep_hit_loc; + + wire [0:`ITAG_SIZE_ENC-1] rv0_instr_i1_s1_itag_loc[0:`THREADS-1]; + wire [0:`ITAG_SIZE_ENC-1] rv0_instr_i1_s2_itag_loc[0:`THREADS-1]; + wire [0:`ITAG_SIZE_ENC-1] rv0_instr_i1_s3_itag_loc[0:`THREADS-1]; + + + wire [0:`THREADS-1] rv1_lq_instr_i0_vld_d; + wire [0:`THREADS-1] rv1_lq_instr_i1_vld_d; + wire [0:`THREADS-1] rv1_lq_instr_i0_vld_q; + wire [0:`THREADS-1] rv1_lq_instr_i1_vld_q; + + wire rv1_lq_instr_i0_rte_lq_d; + wire rv1_lq_instr_i0_rte_sq_d; + wire rv1_lq_instr_i0_rte_lq_q; + wire rv1_lq_instr_i0_rte_sq_q; + wire rv1_lq_instr_i1_rte_lq_d; + wire rv1_lq_instr_i1_rte_sq_d; + wire rv1_lq_instr_i1_rte_lq_q; + wire rv1_lq_instr_i1_rte_sq_q; + + wire [61-`PF_IAR_BITS+1:61] rv0_lq_instr_i0_ifar; + wire [61-`PF_IAR_BITS+1:61] rv0_lq_instr_i1_ifar; + wire [61-`PF_IAR_BITS+1:61] rv1_lq_instr_i0_ifar_d; + wire [61-`PF_IAR_BITS+1:61] rv1_lq_instr_i1_ifar_d; + wire [61-`PF_IAR_BITS+1:61] rv1_lq_instr_i0_ifar_q; + wire [61-`PF_IAR_BITS+1:61] rv1_lq_instr_i1_ifar_q; + + wire [0: `ITAG_SIZE_ENC-1] rv1_lq_instr_i0_itag_d; + wire [0:2] rv1_lq_instr_i0_ucode_d; + wire rv1_lq_instr_i0_ucode_preissue_d; + wire [0:`UCODE_ENTRIES_ENC-1] rv1_lq_instr_i0_ucode_cnt_d; + wire rv1_lq_instr_i0_2ucode_d; + wire [0:2] rv1_lq_instr_i0_s3_t_d; + wire rv1_lq_instr_i0_isLoad_d; + wire rv1_lq_instr_i0_isStore_d; + wire [0: `ITAG_SIZE_ENC-1] rv1_lq_instr_i1_itag_d; + wire [0:2] rv1_lq_instr_i1_ucode_d; + wire rv1_lq_instr_i1_ucode_preissue_d; + wire [0:`UCODE_ENTRIES_ENC-1] rv1_lq_instr_i1_ucode_cnt_d; + wire rv1_lq_instr_i1_2ucode_d; + wire [0:2] rv1_lq_instr_i1_s3_t_d; + wire rv1_lq_instr_i1_isLoad_d; + wire rv1_lq_instr_i1_isStore_d; + wire [0: `ITAG_SIZE_ENC-1] rv1_lq_instr_i0_itag_q; + wire rv1_lq_instr_i0_ucode_preissue_q; + wire [0:`UCODE_ENTRIES_ENC-1] rv1_lq_instr_i0_ucode_cnt_q; + wire rv1_lq_instr_i0_2ucode_q; + wire [0:2] rv1_lq_instr_i0_s3_t_q; + wire rv1_lq_instr_i0_isLoad_q; + wire rv1_lq_instr_i0_isStore_q; + wire [0: `ITAG_SIZE_ENC-1] rv1_lq_instr_i1_itag_q; + wire rv1_lq_instr_i1_ucode_preissue_q; + wire [0:`UCODE_ENTRIES_ENC-1] rv1_lq_instr_i1_ucode_cnt_q; + wire rv1_lq_instr_i1_2ucode_q; + wire [0:2] rv1_lq_instr_i1_s3_t_q; + wire rv1_lq_instr_i1_isLoad_q; + wire rv1_lq_instr_i1_isStore_q; + + + wire func_sl_thold_0; + wire func_sl_thold_0_b; + wire sg_0; + +`ifndef THREADS1 + wire [0:2] rv0_fx0_i0_sel; + wire [0:2] rv0_fx0_i1_sel; + wire [0:2] rv0_fx1_i0_sel; + wire [0:2] rv0_fx1_i1_sel; + wire [0:2] rv0_lq_i0_sel; + wire [0:2] rv0_lq_i1_sel; + wire [0:2] rv0_axu0_i0_sel; + wire [0:2] rv0_axu0_i1_sel; +`endif + + + parameter cp_flush_offset = 0 + 0; + + parameter dep0_offset = cp_flush_offset + `THREADS; + parameter rv0_t0_i0_vld_offset = dep0_offset + 1; + parameter rv0_t0_i0_rte_lq_offset = rv0_t0_i0_vld_offset + 1; + parameter rv0_t0_i0_rte_sq_offset = rv0_t0_i0_rte_lq_offset + 1; + parameter rv0_t0_i0_rte_fx0_offset = rv0_t0_i0_rte_sq_offset + 1; + parameter rv0_t0_i0_rte_fx1_offset = rv0_t0_i0_rte_fx0_offset + 1; + parameter rv0_t0_i0_rte_axu0_offset = rv0_t0_i0_rte_fx1_offset + 1; + parameter rv0_t0_i0_rte_axu1_offset = rv0_t0_i0_rte_axu0_offset + 1; + parameter rv0_t0_i0_instr_offset = rv0_t0_i0_rte_axu1_offset + 1; + parameter rv0_t0_i0_ifar_offset = rv0_t0_i0_instr_offset + 32; + parameter rv0_t0_i0_ucode_offset = rv0_t0_i0_ifar_offset + `EFF_IFAR_WIDTH; + parameter rv0_t0_i0_2ucode_offset = rv0_t0_i0_ucode_offset + 3; + parameter rv0_t0_i0_ucode_cnt_offset = rv0_t0_i0_2ucode_offset + 1; + parameter rv0_t0_i0_itag_offset = rv0_t0_i0_ucode_cnt_offset + `UCODE_ENTRIES_ENC; + parameter rv0_t0_i0_ord_offset = rv0_t0_i0_itag_offset + `ITAG_SIZE_ENC; + parameter rv0_t0_i0_cord_offset = rv0_t0_i0_ord_offset + 1; + parameter rv0_t0_i0_spec_offset = rv0_t0_i0_cord_offset + 1; + parameter rv0_t0_i0_t1_v_offset = rv0_t0_i0_spec_offset + 1; + parameter rv0_t0_i0_t1_p_offset = rv0_t0_i0_t1_v_offset + 1; + parameter rv0_t0_i0_t1_t_offset = rv0_t0_i0_t1_p_offset + `GPR_POOL_ENC; + parameter rv0_t0_i0_t2_v_offset = rv0_t0_i0_t1_t_offset + 3; + parameter rv0_t0_i0_t2_p_offset = rv0_t0_i0_t2_v_offset + 1; + parameter rv0_t0_i0_t2_t_offset = rv0_t0_i0_t2_p_offset + `GPR_POOL_ENC; + parameter rv0_t0_i0_t3_v_offset = rv0_t0_i0_t2_t_offset + 3; + parameter rv0_t0_i0_t3_p_offset = rv0_t0_i0_t3_v_offset + 1; + parameter rv0_t0_i0_t3_t_offset = rv0_t0_i0_t3_p_offset + `GPR_POOL_ENC; + parameter rv0_t0_i0_s1_v_offset = rv0_t0_i0_t3_t_offset + 3; + parameter rv0_t0_i0_s1_p_offset = rv0_t0_i0_s1_v_offset + 1; + parameter rv0_t0_i0_s1_t_offset = rv0_t0_i0_s1_p_offset + `GPR_POOL_ENC; + parameter rv0_t0_i0_s2_v_offset = rv0_t0_i0_s1_t_offset + 3; + parameter rv0_t0_i0_s2_p_offset = rv0_t0_i0_s2_v_offset + 1; + parameter rv0_t0_i0_s2_t_offset = rv0_t0_i0_s2_p_offset + `GPR_POOL_ENC; + parameter rv0_t0_i0_s3_v_offset = rv0_t0_i0_s2_t_offset + 3; + parameter rv0_t0_i0_s3_p_offset = rv0_t0_i0_s3_v_offset + 1; + parameter rv0_t0_i0_s3_t_offset = rv0_t0_i0_s3_p_offset + `GPR_POOL_ENC; + parameter rv0_t0_i0_s1_itag_offset = rv0_t0_i0_s3_t_offset + 3; + parameter rv0_t0_i0_s2_itag_offset = rv0_t0_i0_s1_itag_offset + `ITAG_SIZE_ENC; + parameter rv0_t0_i0_s3_itag_offset = rv0_t0_i0_s2_itag_offset + `ITAG_SIZE_ENC; + parameter rv0_t0_i0_ilat_offset = rv0_t0_i0_s3_itag_offset + `ITAG_SIZE_ENC; + parameter rv0_t0_i0_branch_offset = rv0_t0_i0_ilat_offset + 4; + parameter rv0_t0_i0_isLoad_offset = rv0_t0_i0_branch_offset + `G_BRANCH_LEN; + parameter rv0_t0_i0_isStore_offset = rv0_t0_i0_isLoad_offset + 1; + parameter rv0_t0_i0_spare_offset = rv0_t0_i0_isStore_offset + 1; + + parameter rv0_t0_i1_vld_offset = rv0_t0_i0_spare_offset + 4; + parameter rv0_t0_i1_rte_lq_offset = rv0_t0_i1_vld_offset + 1; + parameter rv0_t0_i1_rte_sq_offset = rv0_t0_i1_rte_lq_offset + 1; + parameter rv0_t0_i1_rte_fx0_offset = rv0_t0_i1_rte_sq_offset + 1; + parameter rv0_t0_i1_rte_fx1_offset = rv0_t0_i1_rte_fx0_offset + 1; + parameter rv0_t0_i1_rte_axu0_offset = rv0_t0_i1_rte_fx1_offset + 1; + parameter rv0_t0_i1_rte_axu1_offset = rv0_t0_i1_rte_axu0_offset + 1; + parameter rv0_t0_i1_instr_offset = rv0_t0_i1_rte_axu1_offset + 1; + parameter rv0_t0_i1_ifar_offset = rv0_t0_i1_instr_offset + 32; + parameter rv0_t0_i1_ucode_offset = rv0_t0_i1_ifar_offset + `EFF_IFAR_WIDTH; + parameter rv0_t0_i1_ucode_cnt_offset = rv0_t0_i1_ucode_offset + 3; + parameter rv0_t0_i1_itag_offset = rv0_t0_i1_ucode_cnt_offset + `UCODE_ENTRIES_ENC; + parameter rv0_t0_i1_ord_offset = rv0_t0_i1_itag_offset + `ITAG_SIZE_ENC; + parameter rv0_t0_i1_cord_offset = rv0_t0_i1_ord_offset + 1; + parameter rv0_t0_i1_spec_offset = rv0_t0_i1_cord_offset + 1; + parameter rv0_t0_i1_t1_v_offset = rv0_t0_i1_spec_offset + 1; + parameter rv0_t0_i1_t1_p_offset = rv0_t0_i1_t1_v_offset + 1; + parameter rv0_t0_i1_t1_t_offset = rv0_t0_i1_t1_p_offset + `GPR_POOL_ENC; + parameter rv0_t0_i1_t2_v_offset = rv0_t0_i1_t1_t_offset + 3; + parameter rv0_t0_i1_t2_p_offset = rv0_t0_i1_t2_v_offset + 1; + parameter rv0_t0_i1_t2_t_offset = rv0_t0_i1_t2_p_offset + `GPR_POOL_ENC; + parameter rv0_t0_i1_t3_v_offset = rv0_t0_i1_t2_t_offset + 3; + parameter rv0_t0_i1_t3_p_offset = rv0_t0_i1_t3_v_offset + 1; + parameter rv0_t0_i1_t3_t_offset = rv0_t0_i1_t3_p_offset + `GPR_POOL_ENC; + parameter rv0_t0_i1_s1_v_offset = rv0_t0_i1_t3_t_offset + 3; + parameter rv0_t0_i1_s1_p_offset = rv0_t0_i1_s1_v_offset + 1; + parameter rv0_t0_i1_s1_t_offset = rv0_t0_i1_s1_p_offset + `GPR_POOL_ENC; + parameter rv0_t0_i1_s2_v_offset = rv0_t0_i1_s1_t_offset + 3; + parameter rv0_t0_i1_s2_p_offset = rv0_t0_i1_s2_v_offset + 1; + parameter rv0_t0_i1_s2_t_offset = rv0_t0_i1_s2_p_offset + `GPR_POOL_ENC; + parameter rv0_t0_i1_s3_v_offset = rv0_t0_i1_s2_t_offset + 3; + parameter rv0_t0_i1_s3_p_offset = rv0_t0_i1_s3_v_offset + 1; + parameter rv0_t0_i1_s3_t_offset = rv0_t0_i1_s3_p_offset + `GPR_POOL_ENC; + parameter rv0_t0_i1_s1_itag_offset = rv0_t0_i1_s3_t_offset + 3; + parameter rv0_t0_i1_s2_itag_offset = rv0_t0_i1_s1_itag_offset + `ITAG_SIZE_ENC; + parameter rv0_t0_i1_s3_itag_offset = rv0_t0_i1_s2_itag_offset + `ITAG_SIZE_ENC; + parameter rv0_t0_i1_s1_dep_hit_offset = rv0_t0_i1_s3_itag_offset + `ITAG_SIZE_ENC; + parameter rv0_t0_i1_s2_dep_hit_offset = rv0_t0_i1_s1_dep_hit_offset + 1; + parameter rv0_t0_i1_s3_dep_hit_offset = rv0_t0_i1_s2_dep_hit_offset + 1; + parameter rv0_t0_i1_ilat_offset = rv0_t0_i1_s3_dep_hit_offset + 1; + parameter rv0_t0_i1_branch_offset = rv0_t0_i1_ilat_offset + 4; + parameter rv0_t0_i1_isLoad_offset = rv0_t0_i1_branch_offset + `G_BRANCH_LEN; + parameter rv0_t0_i1_isStore_offset = rv0_t0_i1_isLoad_offset + 1; + parameter rv0_t0_i1_spare_offset = rv0_t0_i1_isStore_offset + 1; + +`ifndef THREADS1 + parameter dep1_offset = rv0_t0_i1_spare_offset + 4; + parameter rv0_t1_i0_vld_offset = dep1_offset + 1; + parameter rv0_t1_i0_rte_lq_offset = rv0_t1_i0_vld_offset + 1; + parameter rv0_t1_i0_rte_sq_offset = rv0_t1_i0_rte_lq_offset + 1; + parameter rv0_t1_i0_rte_fx0_offset = rv0_t1_i0_rte_sq_offset + 1; + parameter rv0_t1_i0_rte_fx1_offset = rv0_t1_i0_rte_fx0_offset + 1; + parameter rv0_t1_i0_rte_axu0_offset = rv0_t1_i0_rte_fx1_offset + 1; + parameter rv0_t1_i0_rte_axu1_offset = rv0_t1_i0_rte_axu0_offset + 1; + parameter rv0_t1_i0_instr_offset = rv0_t1_i0_rte_axu1_offset + 1; + parameter rv0_t1_i0_ifar_offset = rv0_t1_i0_instr_offset + 32; + parameter rv0_t1_i0_ucode_offset = rv0_t1_i0_ifar_offset + `EFF_IFAR_WIDTH; + parameter rv0_t1_i0_2ucode_offset = rv0_t1_i0_ucode_offset + 3; + parameter rv0_t1_i0_ucode_cnt_offset = rv0_t1_i0_2ucode_offset + 1; + parameter rv0_t1_i0_itag_offset = rv0_t1_i0_ucode_cnt_offset + `UCODE_ENTRIES_ENC; + parameter rv0_t1_i0_ord_offset = rv0_t1_i0_itag_offset + `ITAG_SIZE_ENC; + parameter rv0_t1_i0_cord_offset = rv0_t1_i0_ord_offset + 1; + parameter rv0_t1_i0_spec_offset = rv0_t1_i0_cord_offset + 1; + parameter rv0_t1_i0_t1_v_offset = rv0_t1_i0_spec_offset + 1; + parameter rv0_t1_i0_t1_p_offset = rv0_t1_i0_t1_v_offset + 1; + parameter rv0_t1_i0_t1_t_offset = rv0_t1_i0_t1_p_offset + `GPR_POOL_ENC; + parameter rv0_t1_i0_t2_v_offset = rv0_t1_i0_t1_t_offset + 3; + parameter rv0_t1_i0_t2_p_offset = rv0_t1_i0_t2_v_offset + 1; + parameter rv0_t1_i0_t2_t_offset = rv0_t1_i0_t2_p_offset + `GPR_POOL_ENC; + parameter rv0_t1_i0_t3_v_offset = rv0_t1_i0_t2_t_offset + 3; + parameter rv0_t1_i0_t3_p_offset = rv0_t1_i0_t3_v_offset + 1; + parameter rv0_t1_i0_t3_t_offset = rv0_t1_i0_t3_p_offset + `GPR_POOL_ENC; + parameter rv0_t1_i0_s1_v_offset = rv0_t1_i0_t3_t_offset + 3; + parameter rv0_t1_i0_s1_p_offset = rv0_t1_i0_s1_v_offset + 1; + parameter rv0_t1_i0_s1_t_offset = rv0_t1_i0_s1_p_offset + `GPR_POOL_ENC; + parameter rv0_t1_i0_s2_v_offset = rv0_t1_i0_s1_t_offset + 3; + parameter rv0_t1_i0_s2_p_offset = rv0_t1_i0_s2_v_offset + 1; + parameter rv0_t1_i0_s2_t_offset = rv0_t1_i0_s2_p_offset + `GPR_POOL_ENC; + parameter rv0_t1_i0_s3_v_offset = rv0_t1_i0_s2_t_offset + 3; + parameter rv0_t1_i0_s3_p_offset = rv0_t1_i0_s3_v_offset + 1; + parameter rv0_t1_i0_s3_t_offset = rv0_t1_i0_s3_p_offset + `GPR_POOL_ENC; + parameter rv0_t1_i0_s1_itag_offset = rv0_t1_i0_s3_t_offset + 3; + parameter rv0_t1_i0_s2_itag_offset = rv0_t1_i0_s1_itag_offset + `ITAG_SIZE_ENC; + parameter rv0_t1_i0_s3_itag_offset = rv0_t1_i0_s2_itag_offset + `ITAG_SIZE_ENC; + parameter rv0_t1_i0_ilat_offset = rv0_t1_i0_s3_itag_offset + `ITAG_SIZE_ENC; + parameter rv0_t1_i0_branch_offset = rv0_t1_i0_ilat_offset + 4; + parameter rv0_t1_i0_isLoad_offset = rv0_t1_i0_branch_offset + `G_BRANCH_LEN; + parameter rv0_t1_i0_isStore_offset = rv0_t1_i0_isLoad_offset + 1; + parameter rv0_t1_i0_spare_offset = rv0_t1_i0_isStore_offset + 1; + + parameter rv0_t1_i1_vld_offset = rv0_t1_i0_spare_offset + 4; + parameter rv0_t1_i1_rte_lq_offset = rv0_t1_i1_vld_offset + 1; + parameter rv0_t1_i1_rte_sq_offset = rv0_t1_i1_rte_lq_offset + 1; + parameter rv0_t1_i1_rte_fx0_offset = rv0_t1_i1_rte_sq_offset + 1; + parameter rv0_t1_i1_rte_fx1_offset = rv0_t1_i1_rte_fx0_offset + 1; + parameter rv0_t1_i1_rte_axu0_offset = rv0_t1_i1_rte_fx1_offset + 1; + parameter rv0_t1_i1_rte_axu1_offset = rv0_t1_i1_rte_axu0_offset + 1; + parameter rv0_t1_i1_instr_offset = rv0_t1_i1_rte_axu1_offset + 1; + parameter rv0_t1_i1_ifar_offset = rv0_t1_i1_instr_offset + 32; + parameter rv0_t1_i1_ucode_offset = rv0_t1_i1_ifar_offset + `EFF_IFAR_WIDTH; + parameter rv0_t1_i1_ucode_cnt_offset = rv0_t1_i1_ucode_offset + 3; + parameter rv0_t1_i1_itag_offset = rv0_t1_i1_ucode_cnt_offset + `UCODE_ENTRIES_ENC; + parameter rv0_t1_i1_ord_offset = rv0_t1_i1_itag_offset + `ITAG_SIZE_ENC; + parameter rv0_t1_i1_cord_offset = rv0_t1_i1_ord_offset + 1; + parameter rv0_t1_i1_spec_offset = rv0_t1_i1_cord_offset + 1; + parameter rv0_t1_i1_t1_v_offset = rv0_t1_i1_spec_offset + 1; + parameter rv0_t1_i1_t1_p_offset = rv0_t1_i1_t1_v_offset + 1; + parameter rv0_t1_i1_t1_t_offset = rv0_t1_i1_t1_p_offset + `GPR_POOL_ENC; + parameter rv0_t1_i1_t2_v_offset = rv0_t1_i1_t1_t_offset + 3; + parameter rv0_t1_i1_t2_p_offset = rv0_t1_i1_t2_v_offset + 1; + parameter rv0_t1_i1_t2_t_offset = rv0_t1_i1_t2_p_offset + `GPR_POOL_ENC; + parameter rv0_t1_i1_t3_v_offset = rv0_t1_i1_t2_t_offset + 3; + parameter rv0_t1_i1_t3_p_offset = rv0_t1_i1_t3_v_offset + 1; + parameter rv0_t1_i1_t3_t_offset = rv0_t1_i1_t3_p_offset + `GPR_POOL_ENC; + parameter rv0_t1_i1_s1_v_offset = rv0_t1_i1_t3_t_offset + 3; + parameter rv0_t1_i1_s1_p_offset = rv0_t1_i1_s1_v_offset + 1; + parameter rv0_t1_i1_s1_t_offset = rv0_t1_i1_s1_p_offset + `GPR_POOL_ENC; + parameter rv0_t1_i1_s2_v_offset = rv0_t1_i1_s1_t_offset + 3; + parameter rv0_t1_i1_s2_p_offset = rv0_t1_i1_s2_v_offset + 1; + parameter rv0_t1_i1_s2_t_offset = rv0_t1_i1_s2_p_offset + `GPR_POOL_ENC; + parameter rv0_t1_i1_s3_v_offset = rv0_t1_i1_s2_t_offset + 3; + parameter rv0_t1_i1_s3_p_offset = rv0_t1_i1_s3_v_offset + 1; + parameter rv0_t1_i1_s3_t_offset = rv0_t1_i1_s3_p_offset + `GPR_POOL_ENC; + parameter rv0_t1_i1_s1_itag_offset = rv0_t1_i1_s3_t_offset + 3; + parameter rv0_t1_i1_s2_itag_offset = rv0_t1_i1_s1_itag_offset + `ITAG_SIZE_ENC; + parameter rv0_t1_i1_s3_itag_offset = rv0_t1_i1_s2_itag_offset + `ITAG_SIZE_ENC; + parameter rv0_t1_i1_s1_dep_hit_offset = rv0_t1_i1_s3_itag_offset + `ITAG_SIZE_ENC; + parameter rv0_t1_i1_s2_dep_hit_offset = rv0_t1_i1_s1_dep_hit_offset + 1; + parameter rv0_t1_i1_s3_dep_hit_offset = rv0_t1_i1_s2_dep_hit_offset + 1; + parameter rv0_t1_i1_ilat_offset = rv0_t1_i1_s3_dep_hit_offset + 1; + parameter rv0_t1_i1_branch_offset = rv0_t1_i1_ilat_offset + 4; + parameter rv0_t1_i1_isLoad_offset = rv0_t1_i1_branch_offset + `G_BRANCH_LEN; + parameter rv0_t1_i1_isStore_offset = rv0_t1_i1_isLoad_offset + 1; + parameter rv0_t1_i1_spare_offset = rv0_t1_i1_isStore_offset + 1; + + + parameter rv0_instr_i0_flushed_offset = rv0_t1_i1_spare_offset + 4; +`else + + parameter rv0_instr_i0_flushed_offset = rv0_t0_i1_spare_offset + 4; +`endif + + parameter rv0_instr_i1_flushed_offset = rv0_instr_i0_flushed_offset + `THREADS; + parameter rv1_lq_instr_i0_vld_offset = rv0_instr_i1_flushed_offset + `THREADS; + parameter rv1_lq_instr_i0_rte_lq_offset = rv1_lq_instr_i0_vld_offset + `THREADS; + parameter rv1_lq_instr_i0_rte_sq_offset = rv1_lq_instr_i0_rte_lq_offset + 1; + parameter rv1_lq_instr_i0_ucode_preissue_offset = rv1_lq_instr_i0_rte_sq_offset + 1; + parameter rv1_lq_instr_i0_2ucode_offset = rv1_lq_instr_i0_ucode_preissue_offset + 1; + parameter rv1_lq_instr_i0_ucode_cnt_offset = rv1_lq_instr_i0_2ucode_offset + 1; + parameter rv1_lq_instr_i0_s3_t_offset = rv1_lq_instr_i0_ucode_cnt_offset + `UCODE_ENTRIES_ENC; + parameter rv1_lq_instr_i0_isLoad_offset = rv1_lq_instr_i0_s3_t_offset + 3; + parameter rv1_lq_instr_i0_isStore_offset = rv1_lq_instr_i0_isLoad_offset + 1; + parameter rv1_lq_instr_i0_itag_offset = rv1_lq_instr_i0_isStore_offset + 1; + parameter rv1_lq_instr_i0_ifar_offset = rv1_lq_instr_i0_itag_offset+ `ITAG_SIZE_ENC; + + parameter rv1_lq_instr_i1_vld_offset = rv1_lq_instr_i0_ifar_offset + `PF_IAR_BITS; + parameter rv1_lq_instr_i1_rte_lq_offset = rv1_lq_instr_i1_vld_offset + `THREADS; + parameter rv1_lq_instr_i1_rte_sq_offset = rv1_lq_instr_i1_rte_lq_offset + 1; + parameter rv1_lq_instr_i1_ucode_preissue_offset = rv1_lq_instr_i1_rte_sq_offset + 1; + parameter rv1_lq_instr_i1_2ucode_offset = rv1_lq_instr_i1_ucode_preissue_offset + 1; + parameter rv1_lq_instr_i1_ucode_cnt_offset = rv1_lq_instr_i1_2ucode_offset + 1; + parameter rv1_lq_instr_i1_s3_t_offset = rv1_lq_instr_i1_ucode_cnt_offset + `UCODE_ENTRIES_ENC; + parameter rv1_lq_instr_i1_isLoad_offset = rv1_lq_instr_i1_s3_t_offset + 3; + parameter rv1_lq_instr_i1_isStore_offset = rv1_lq_instr_i1_isLoad_offset + 1; + parameter rv1_lq_instr_i1_itag_offset = rv1_lq_instr_i1_isStore_offset + 1; + parameter rv1_lq_instr_i1_ifar_offset = rv1_lq_instr_i1_itag_offset+ `ITAG_SIZE_ENC; + + parameter scan_right = rv1_lq_instr_i1_ifar_offset + `PF_IAR_BITS; + wire [0:scan_right-1] siv; + wire [0:scan_right-1] sov; + + //------------------------------------------------------------------------------------------------------------ + // Misc + //------------------------------------------------------------------------------------------------------------ + assign tiup = 1'b1; + + //------------------------------------------------------------------------------------------------------------ + // Inputs Thread 0 + //------------------------------------------------------------------------------------------------------------ + + assign iu6_t0_i0_act = iu_rv_iu6_t0_i0_act; + assign iu6_t0_i1_act = iu_rv_iu6_t0_i1_act; + + assign rv0_t0_i0_act = rv0_t0_i0_vld_q; + assign rv0_t0_i1_act = rv0_t0_i1_vld_q; + + assign rv0_t0_i0_vld_d = iu_rv_iu6_t0_i0_vld; + assign rv0_instr_i0_flushed_d[0] = iu_rv_iu6_t0_i0_vld & iu_xx_zap[0]; + assign rv0_t0_i0_rte_lq_d = iu_rv_iu6_t0_i0_rte_lq & iu_rv_iu6_t0_i0_vld; + assign rv0_t0_i0_rte_sq_d = iu_rv_iu6_t0_i0_rte_sq & iu_rv_iu6_t0_i0_vld; + assign rv0_t0_i0_rte_fx0_d = iu_rv_iu6_t0_i0_rte_fx0 & iu_rv_iu6_t0_i0_vld; + assign rv0_t0_i0_rte_fx1_d = iu_rv_iu6_t0_i0_rte_fx1 & iu_rv_iu6_t0_i0_vld; + assign rv0_t0_i0_rte_axu0_d = iu_rv_iu6_t0_i0_rte_axu0 & iu_rv_iu6_t0_i0_vld; + assign rv0_t0_i0_rte_axu1_d = iu_rv_iu6_t0_i0_rte_axu1 & iu_rv_iu6_t0_i0_vld; + assign rv0_t0_i0_instr_d = iu_rv_iu6_t0_i0_instr; + assign rv0_t0_i0_ifar_d = iu_rv_iu6_t0_i0_ifar; + assign rv0_t0_i0_ucode_d = iu_rv_iu6_t0_i0_ucode; + assign rv0_t0_i0_2ucode_d = iu_rv_iu6_t0_i0_2ucode; + assign rv0_t0_i0_ucode_cnt_d = iu_rv_iu6_t0_i0_ucode_cnt; + assign rv0_t0_i0_itag_d = iu_rv_iu6_t0_i0_itag; + assign rv0_t0_i0_ord_d = iu_rv_iu6_t0_i0_ord; + assign rv0_t0_i0_cord_d = iu_rv_iu6_t0_i0_cord; + assign rv0_t0_i0_spec_d = iu_rv_iu6_t0_i0_spec; + assign rv0_t0_i0_t1_v_d = iu_rv_iu6_t0_i0_t1_v; + assign rv0_t0_i0_t1_p_d = iu_rv_iu6_t0_i0_t1_p; + assign rv0_t0_i0_t1_t_d = iu_rv_iu6_t0_i0_t1_t; + assign rv0_t0_i0_t2_v_d = iu_rv_iu6_t0_i0_t2_v; + assign rv0_t0_i0_t2_p_d = iu_rv_iu6_t0_i0_t2_p; + assign rv0_t0_i0_t2_t_d = iu_rv_iu6_t0_i0_t2_t; + assign rv0_t0_i0_t3_v_d = iu_rv_iu6_t0_i0_t3_v; + assign rv0_t0_i0_t3_p_d = iu_rv_iu6_t0_i0_t3_p; + assign rv0_t0_i0_t3_t_d = iu_rv_iu6_t0_i0_t3_t; + assign rv0_t0_i0_s1_v_d = iu_rv_iu6_t0_i0_s1_v; + assign rv0_t0_i0_s1_p_d = iu_rv_iu6_t0_i0_s1_p; + assign rv0_t0_i0_s1_t_d = iu_rv_iu6_t0_i0_s1_t; + assign rv0_t0_i0_s2_v_d = iu_rv_iu6_t0_i0_s2_v; + assign rv0_t0_i0_s2_p_d = iu_rv_iu6_t0_i0_s2_p; + assign rv0_t0_i0_s2_t_d = iu_rv_iu6_t0_i0_s2_t; + assign rv0_t0_i0_s3_v_d = iu_rv_iu6_t0_i0_s3_v; + assign rv0_t0_i0_s3_p_d = iu_rv_iu6_t0_i0_s3_p; + assign rv0_t0_i0_s3_t_d = iu_rv_iu6_t0_i0_s3_t; + assign rv0_t0_i0_ilat_d = iu_rv_iu6_t0_i0_ilat; + assign rv0_t0_i0_branch_d = iu_rv_iu6_t0_i0_branch; + assign rv0_t0_i0_isLoad_d = iu_rv_iu6_t0_i0_isLoad; + assign rv0_t0_i0_isStore_d = iu_rv_iu6_t0_i0_isStore; + assign rv0_t0_i0_s1_itag_d = iu_rv_iu6_t0_i0_s1_itag; + assign rv0_t0_i0_s2_itag_d = iu_rv_iu6_t0_i0_s2_itag; + assign rv0_t0_i0_s3_itag_d = iu_rv_iu6_t0_i0_s3_itag; + + assign rv0_t0_i1_vld_d = iu_rv_iu6_t0_i1_vld; + assign rv0_instr_i1_flushed_d[0] = iu_rv_iu6_t0_i1_vld & iu_xx_zap[0]; + assign rv0_t0_i1_rte_lq_d = iu_rv_iu6_t0_i1_rte_lq & iu_rv_iu6_t0_i1_vld; + assign rv0_t0_i1_rte_sq_d = iu_rv_iu6_t0_i1_rte_sq & iu_rv_iu6_t0_i1_vld; + assign rv0_t0_i1_rte_fx0_d = iu_rv_iu6_t0_i1_rte_fx0 & iu_rv_iu6_t0_i1_vld; + assign rv0_t0_i1_rte_fx1_d = iu_rv_iu6_t0_i1_rte_fx1 & iu_rv_iu6_t0_i1_vld; + assign rv0_t0_i1_rte_axu0_d = iu_rv_iu6_t0_i1_rte_axu0 & iu_rv_iu6_t0_i1_vld; + assign rv0_t0_i1_rte_axu1_d = iu_rv_iu6_t0_i1_rte_axu1 & iu_rv_iu6_t0_i1_vld; + assign rv0_t0_i1_instr_d = iu_rv_iu6_t0_i1_instr; + assign rv0_t0_i1_ifar_d = iu_rv_iu6_t0_i1_ifar; + assign rv0_t0_i1_ucode_d = iu_rv_iu6_t0_i1_ucode; + assign rv0_t0_i1_ucode_cnt_d = iu_rv_iu6_t0_i1_ucode_cnt; + assign rv0_t0_i1_itag_d = iu_rv_iu6_t0_i1_itag; + assign rv0_t0_i1_ord_d = iu_rv_iu6_t0_i1_ord; + assign rv0_t0_i1_cord_d = iu_rv_iu6_t0_i1_cord; + assign rv0_t0_i1_spec_d = iu_rv_iu6_t0_i1_spec; + assign rv0_t0_i1_t1_v_d = iu_rv_iu6_t0_i1_t1_v; + assign rv0_t0_i1_t1_p_d = iu_rv_iu6_t0_i1_t1_p; + assign rv0_t0_i1_t1_t_d = iu_rv_iu6_t0_i1_t1_t; + assign rv0_t0_i1_t2_v_d = iu_rv_iu6_t0_i1_t2_v; + assign rv0_t0_i1_t2_p_d = iu_rv_iu6_t0_i1_t2_p; + assign rv0_t0_i1_t2_t_d = iu_rv_iu6_t0_i1_t2_t; + assign rv0_t0_i1_t3_v_d = iu_rv_iu6_t0_i1_t3_v; + assign rv0_t0_i1_t3_p_d = iu_rv_iu6_t0_i1_t3_p; + assign rv0_t0_i1_t3_t_d = iu_rv_iu6_t0_i1_t3_t; + assign rv0_t0_i1_s1_v_d = iu_rv_iu6_t0_i1_s1_v; + assign rv0_t0_i1_s1_p_d = iu_rv_iu6_t0_i1_s1_p; + assign rv0_t0_i1_s1_t_d = iu_rv_iu6_t0_i1_s1_t; + assign rv0_t0_i1_s2_v_d = iu_rv_iu6_t0_i1_s2_v; + assign rv0_t0_i1_s2_p_d = iu_rv_iu6_t0_i1_s2_p; + assign rv0_t0_i1_s2_t_d = iu_rv_iu6_t0_i1_s2_t; + assign rv0_t0_i1_s3_v_d = iu_rv_iu6_t0_i1_s3_v; + assign rv0_t0_i1_s3_p_d = iu_rv_iu6_t0_i1_s3_p; + assign rv0_t0_i1_s3_t_d = iu_rv_iu6_t0_i1_s3_t; + assign rv0_t0_i1_ilat_d = iu_rv_iu6_t0_i1_ilat; + assign rv0_t0_i1_branch_d = iu_rv_iu6_t0_i1_branch; + assign rv0_t0_i1_isLoad_d = iu_rv_iu6_t0_i1_isLoad; + assign rv0_t0_i1_isStore_d = iu_rv_iu6_t0_i1_isStore; + assign rv0_t0_i1_s1_itag_d = iu_rv_iu6_t0_i1_s1_itag; + assign rv0_t0_i1_s2_itag_d = iu_rv_iu6_t0_i1_s2_itag; + assign rv0_t0_i1_s3_itag_d = iu_rv_iu6_t0_i1_s3_itag; + assign rv0_t0_i1_s1_dep_hit_d = iu_rv_iu6_t0_i1_s1_dep_hit; + assign rv0_t0_i1_s2_dep_hit_d = iu_rv_iu6_t0_i1_s2_dep_hit; + assign rv0_t0_i1_s3_dep_hit_d = iu_rv_iu6_t0_i1_s3_dep_hit; + +`ifndef THREADS1 + //------------------------------------------------------------------------------------------------------------ + // Inputs Thread 0 + //------------------------------------------------------------------------------------------------------------ + + assign iu6_t1_i0_act = iu_rv_iu6_t1_i0_act; + assign iu6_t1_i1_act = iu_rv_iu6_t1_i1_act; + + assign rv0_t1_i0_act = rv0_t1_i0_vld_q; + assign rv0_t1_i1_act = rv0_t1_i1_vld_q; + + assign rv0_t1_i0_vld_d = iu_rv_iu6_t1_i0_vld; + assign rv0_instr_i0_flushed_d[1] = iu_rv_iu6_t1_i0_vld & iu_xx_zap[1]; + assign rv0_t1_i0_rte_lq_d = iu_rv_iu6_t1_i0_rte_lq & iu_rv_iu6_t1_i0_vld; + assign rv0_t1_i0_rte_sq_d = iu_rv_iu6_t1_i0_rte_sq & iu_rv_iu6_t1_i0_vld; + assign rv0_t1_i0_rte_fx0_d = iu_rv_iu6_t1_i0_rte_fx0 & iu_rv_iu6_t1_i0_vld; + assign rv0_t1_i0_rte_fx1_d = iu_rv_iu6_t1_i0_rte_fx1 & iu_rv_iu6_t1_i0_vld; + assign rv0_t1_i0_rte_axu0_d = iu_rv_iu6_t1_i0_rte_axu0 & iu_rv_iu6_t1_i0_vld; + assign rv0_t1_i0_rte_axu1_d = iu_rv_iu6_t1_i0_rte_axu1 & iu_rv_iu6_t1_i0_vld; + assign rv0_t1_i0_instr_d = iu_rv_iu6_t1_i0_instr; + assign rv0_t1_i0_ifar_d = iu_rv_iu6_t1_i0_ifar; + assign rv0_t1_i0_ucode_d = iu_rv_iu6_t1_i0_ucode; + assign rv0_t1_i0_2ucode_d = iu_rv_iu6_t1_i0_2ucode; + assign rv0_t1_i0_ucode_cnt_d = iu_rv_iu6_t1_i0_ucode_cnt; + assign rv0_t1_i0_itag_d = iu_rv_iu6_t1_i0_itag; + assign rv0_t1_i0_ord_d = iu_rv_iu6_t1_i0_ord; + assign rv0_t1_i0_cord_d = iu_rv_iu6_t1_i0_cord; + assign rv0_t1_i0_spec_d = iu_rv_iu6_t1_i0_spec; + assign rv0_t1_i0_t1_v_d = iu_rv_iu6_t1_i0_t1_v; + assign rv0_t1_i0_t1_p_d = iu_rv_iu6_t1_i0_t1_p; + assign rv0_t1_i0_t1_t_d = iu_rv_iu6_t1_i0_t1_t; + assign rv0_t1_i0_t2_v_d = iu_rv_iu6_t1_i0_t2_v; + assign rv0_t1_i0_t2_p_d = iu_rv_iu6_t1_i0_t2_p; + assign rv0_t1_i0_t2_t_d = iu_rv_iu6_t1_i0_t2_t; + assign rv0_t1_i0_t3_v_d = iu_rv_iu6_t1_i0_t3_v; + assign rv0_t1_i0_t3_p_d = iu_rv_iu6_t1_i0_t3_p; + assign rv0_t1_i0_t3_t_d = iu_rv_iu6_t1_i0_t3_t; + assign rv0_t1_i0_s1_v_d = iu_rv_iu6_t1_i0_s1_v; + assign rv0_t1_i0_s1_p_d = iu_rv_iu6_t1_i0_s1_p; + assign rv0_t1_i0_s1_t_d = iu_rv_iu6_t1_i0_s1_t; + assign rv0_t1_i0_s2_v_d = iu_rv_iu6_t1_i0_s2_v; + assign rv0_t1_i0_s2_p_d = iu_rv_iu6_t1_i0_s2_p; + assign rv0_t1_i0_s2_t_d = iu_rv_iu6_t1_i0_s2_t; + assign rv0_t1_i0_s3_v_d = iu_rv_iu6_t1_i0_s3_v; + assign rv0_t1_i0_s3_p_d = iu_rv_iu6_t1_i0_s3_p; + assign rv0_t1_i0_s3_t_d = iu_rv_iu6_t1_i0_s3_t; + assign rv0_t1_i0_ilat_d = iu_rv_iu6_t1_i0_ilat; + assign rv0_t1_i0_branch_d = iu_rv_iu6_t1_i0_branch; + assign rv0_t1_i0_isLoad_d = iu_rv_iu6_t1_i0_isLoad; + assign rv0_t1_i0_isStore_d = iu_rv_iu6_t1_i0_isStore; + assign rv0_t1_i0_s1_itag_d = iu_rv_iu6_t1_i0_s1_itag; + assign rv0_t1_i0_s2_itag_d = iu_rv_iu6_t1_i0_s2_itag; + assign rv0_t1_i0_s3_itag_d = iu_rv_iu6_t1_i0_s3_itag; + + assign rv0_t1_i1_vld_d = iu_rv_iu6_t1_i1_vld; + assign rv0_instr_i1_flushed_d[1] = iu_rv_iu6_t1_i1_vld & iu_xx_zap[1]; + assign rv0_t1_i1_rte_lq_d = iu_rv_iu6_t1_i1_rte_lq & iu_rv_iu6_t1_i1_vld; + assign rv0_t1_i1_rte_sq_d = iu_rv_iu6_t1_i1_rte_sq & iu_rv_iu6_t1_i1_vld; + assign rv0_t1_i1_rte_fx0_d = iu_rv_iu6_t1_i1_rte_fx0 & iu_rv_iu6_t1_i1_vld; + assign rv0_t1_i1_rte_fx1_d = iu_rv_iu6_t1_i1_rte_fx1 & iu_rv_iu6_t1_i1_vld; + assign rv0_t1_i1_rte_axu0_d = iu_rv_iu6_t1_i1_rte_axu0 & iu_rv_iu6_t1_i1_vld; + assign rv0_t1_i1_rte_axu1_d = iu_rv_iu6_t1_i1_rte_axu1 & iu_rv_iu6_t1_i1_vld; + assign rv0_t1_i1_instr_d = iu_rv_iu6_t1_i1_instr; + assign rv0_t1_i1_ifar_d = iu_rv_iu6_t1_i1_ifar; + assign rv0_t1_i1_ucode_d = iu_rv_iu6_t1_i1_ucode; + assign rv0_t1_i1_ucode_cnt_d = iu_rv_iu6_t1_i1_ucode_cnt; + assign rv0_t1_i1_itag_d = iu_rv_iu6_t1_i1_itag; + assign rv0_t1_i1_ord_d = iu_rv_iu6_t1_i1_ord; + assign rv0_t1_i1_cord_d = iu_rv_iu6_t1_i1_cord; + assign rv0_t1_i1_spec_d = iu_rv_iu6_t1_i1_spec; + assign rv0_t1_i1_t1_v_d = iu_rv_iu6_t1_i1_t1_v; + assign rv0_t1_i1_t1_p_d = iu_rv_iu6_t1_i1_t1_p; + assign rv0_t1_i1_t1_t_d = iu_rv_iu6_t1_i1_t1_t; + assign rv0_t1_i1_t2_v_d = iu_rv_iu6_t1_i1_t2_v; + assign rv0_t1_i1_t2_p_d = iu_rv_iu6_t1_i1_t2_p; + assign rv0_t1_i1_t2_t_d = iu_rv_iu6_t1_i1_t2_t; + assign rv0_t1_i1_t3_v_d = iu_rv_iu6_t1_i1_t3_v; + assign rv0_t1_i1_t3_p_d = iu_rv_iu6_t1_i1_t3_p; + assign rv0_t1_i1_t3_t_d = iu_rv_iu6_t1_i1_t3_t; + assign rv0_t1_i1_s1_v_d = iu_rv_iu6_t1_i1_s1_v; + assign rv0_t1_i1_s1_p_d = iu_rv_iu6_t1_i1_s1_p; + assign rv0_t1_i1_s1_t_d = iu_rv_iu6_t1_i1_s1_t; + assign rv0_t1_i1_s2_v_d = iu_rv_iu6_t1_i1_s2_v; + assign rv0_t1_i1_s2_p_d = iu_rv_iu6_t1_i1_s2_p; + assign rv0_t1_i1_s2_t_d = iu_rv_iu6_t1_i1_s2_t; + assign rv0_t1_i1_s3_v_d = iu_rv_iu6_t1_i1_s3_v; + assign rv0_t1_i1_s3_p_d = iu_rv_iu6_t1_i1_s3_p; + assign rv0_t1_i1_s3_t_d = iu_rv_iu6_t1_i1_s3_t; + assign rv0_t1_i1_ilat_d = iu_rv_iu6_t1_i1_ilat; + assign rv0_t1_i1_branch_d = iu_rv_iu6_t1_i1_branch; + assign rv0_t1_i1_isLoad_d = iu_rv_iu6_t1_i1_isLoad; + assign rv0_t1_i1_isStore_d = iu_rv_iu6_t1_i1_isStore; + assign rv0_t1_i1_s1_itag_d = iu_rv_iu6_t1_i1_s1_itag; + assign rv0_t1_i1_s2_itag_d = iu_rv_iu6_t1_i1_s2_itag; + assign rv0_t1_i1_s3_itag_d = iu_rv_iu6_t1_i1_s3_itag; + assign rv0_t1_i1_s1_dep_hit_d = iu_rv_iu6_t1_i1_s1_dep_hit; + assign rv0_t1_i1_s2_dep_hit_d = iu_rv_iu6_t1_i1_s2_dep_hit; + assign rv0_t1_i1_s3_dep_hit_d = iu_rv_iu6_t1_i1_s3_dep_hit; +`endif // `ifndef THREADS1 + + + //------------------------------------------------------------------------------------------------------------ + // RV0 + //------------------------------------------------------------------------------------------------------------ + + assign rv0_instr_i0_dep_val[0] = rv0_t0_i0_vld_q & (~rv0_instr_i0_flushed_q[0]); + assign rv0_instr_i1_dep_val[0] = rv0_t0_i1_vld_q & (~rv0_instr_i1_flushed_q[0]); + + + rv_dep + rv_dep0( + .iu_xx_zap(iu_xx_zap[0]), + .rv0_i0_act(rv0_t0_i0_act), + .rv0_i1_act(rv0_t0_i1_act), + + .rv0_instr_i0_vld(rv0_instr_i0_dep_val[0]), + .rv0_instr_i0_t1_v(rv0_t0_i0_t1_v_q), + .rv0_instr_i0_t2_v(rv0_t0_i0_t2_v_q), + .rv0_instr_i0_t3_v(rv0_t0_i0_t3_v_q), + .rv0_instr_i0_itag(rv0_t0_i0_itag_q), + + .rv0_instr_i0_s1_v (rv0_t0_i0_s1_v_q), + .rv0_instr_i0_s1_itag(rv0_t0_i0_s1_itag_q), + .rv0_instr_i0_s2_v (rv0_t0_i0_s2_v_q), + .rv0_instr_i0_s2_itag(rv0_t0_i0_s2_itag_q), + .rv0_instr_i0_s3_v (rv0_t0_i0_s3_v_q), + .rv0_instr_i0_s3_itag(rv0_t0_i0_s3_itag_q), + + .rv0_instr_i1_vld(rv0_instr_i1_dep_val[0]), + .rv0_instr_i1_t1_v(rv0_t0_i1_t1_v_q), + .rv0_instr_i1_t2_v(rv0_t0_i1_t2_v_q), + .rv0_instr_i1_t3_v(rv0_t0_i1_t3_v_q), + .rv0_instr_i1_itag(rv0_t0_i1_itag_q), + + .rv0_instr_i1_s1_v (rv0_t0_i1_s1_v_q), + .rv0_instr_i1_s1_itag(rv0_t0_i1_s1_itag_q), + .rv0_instr_i1_s2_v (rv0_t0_i1_s2_v_q), + .rv0_instr_i1_s2_itag(rv0_t0_i1_s2_itag_q), + .rv0_instr_i1_s3_v (rv0_t0_i1_s3_v_q), + .rv0_instr_i1_s3_itag(rv0_t0_i1_s3_itag_q), + + .fx0_rv_itag_vld(fx0_rv_itag_vld[0]), + .fx0_rv_itag(fx0_rv_itag), + .fx1_rv_itag_vld(fx1_rv_itag_vld[0]), + .fx1_rv_itag(fx1_rv_itag), + .lq_rv_itag0_vld(lq_rv_itag0_vld[0]), + .lq_rv_itag0(lq_rv_itag0), + .lq_rv_itag1_vld(lq_rv_itag1_vld[0]), + .lq_rv_itag1(lq_rv_itag1), + .lq_rv_itag2_vld(lq_rv_itag2_vld[0]), + .lq_rv_itag2(lq_rv_itag2), + .axu0_rv_itag_vld(axu0_rv_itag_vld[0]), + .axu0_rv_itag(axu0_rv_itag), + .axu1_rv_itag_vld(axu1_rv_itag_vld[0]), + .axu1_rv_itag(axu1_rv_itag), + + .fx0_rv_itag_abort (fx0_rv_itag_abort), + .fx1_rv_itag_abort (fx1_rv_itag_abort), + .lq_rv_itag0_abort (lq_rv_itag0_abort), + .lq_rv_itag1_abort (lq_rv_itag1_abort), + .axu0_rv_itag_abort (axu0_rv_itag_abort), + .axu1_rv_itag_abort (axu1_rv_itag_abort), + + .rv0_instr_i0_s1_dep_hit(rv0_instr_i0_s1_dep_hit[0]), + .rv0_instr_i0_s2_dep_hit(rv0_instr_i0_s2_dep_hit[0]), + .rv0_instr_i0_s3_dep_hit(rv0_instr_i0_s3_dep_hit[0]), + + .rv0_instr_i1_s1_dep_hit(rv0_instr_i1_s1_dep_hit[0]), + .rv0_instr_i1_s2_dep_hit(rv0_instr_i1_s2_dep_hit[0]), + .rv0_instr_i1_s3_dep_hit(rv0_instr_i1_s3_dep_hit[0]), + + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .sg_1(sg_1), + .func_sl_thold_1(func_sl_thold_1), + .clkoff_b(clkoff_b), + .act_dis(act_dis), + .ccflush_dc(ccflush_dc), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scan_in(siv[dep0_offset]), + .scan_out(sov[dep0_offset]) + ); + + + rv_decode + dec_t0i0( + .instr(rv0_t0_i0_instr_q), + + .is_brick(rv0_t0_i0_is_brick), + .brick_cycles(rv0_t0_i0_brick) + ); + + + rv_decode + dec_t0i1( + .instr(rv0_t0_i1_instr_q), + + .is_brick(rv0_t0_i1_is_brick), + .brick_cycles(rv0_t0_i1_brick) + ); + + // side checking of instruction b sources against instruction a targets + assign rv0_instr_i1_local_s1_dep_hit[0] = rv0_t0_i1_s1_v_q & rv0_t0_i1_s1_dep_hit_q ; + assign rv0_instr_i1_local_s2_dep_hit[0] = rv0_t0_i1_s2_v_q & rv0_t0_i1_s2_dep_hit_q ; + assign rv0_instr_i1_local_s3_dep_hit[0] = rv0_t0_i1_s3_v_q & rv0_t0_i1_s3_dep_hit_q ; + + assign rv0_t0_i0_ilat = rv0_t0_i0_ilat_q | {4{(~(rv0_t0_i0_t1_v_q | rv0_t0_i0_t2_v_q | rv0_t0_i0_t3_v_q))}}; + assign rv0_t0_i1_ilat = rv0_t0_i1_ilat_q | {4{(~(rv0_t0_i1_t1_v_q | rv0_t0_i1_t2_v_q | rv0_t0_i1_t3_v_q))}}; + + assign rv0_instr_i1_s1_itag_loc[0] = rv0_t0_i1_s1_itag_q; + assign rv0_instr_i1_s2_itag_loc[0] = rv0_t0_i1_s2_itag_q; + assign rv0_instr_i1_s3_itag_loc[0] = rv0_t0_i1_s3_itag_q; + +`ifndef THREADS1 + + assign rv0_instr_i0_dep_val[1] = rv0_t1_i0_vld_q & (~rv0_instr_i0_flushed_q[1]); + assign rv0_instr_i1_dep_val[1] = rv0_t1_i1_vld_q & (~rv0_instr_i1_flushed_q[1]); + + rv_dep + rv_dep1( + .iu_xx_zap(iu_xx_zap[1]), + .rv0_i0_act(rv0_t1_i0_act), + .rv0_i1_act(rv0_t1_i1_act), + + .rv0_instr_i0_vld(rv0_instr_i0_dep_val[1]), + .rv0_instr_i0_t1_v(rv0_t1_i0_t1_v_q), + .rv0_instr_i0_t2_v(rv0_t1_i0_t2_v_q), + .rv0_instr_i0_t3_v(rv0_t1_i0_t3_v_q), + .rv0_instr_i0_itag(rv0_t1_i0_itag_q), + + .rv0_instr_i0_s1_v (rv0_t1_i0_s1_v_q), + .rv0_instr_i0_s1_itag(rv0_t1_i0_s1_itag_q), + .rv0_instr_i0_s2_v (rv0_t1_i0_s2_v_q), + .rv0_instr_i0_s2_itag(rv0_t1_i0_s2_itag_q), + .rv0_instr_i0_s3_v (rv0_t1_i0_s3_v_q), + .rv0_instr_i0_s3_itag(rv0_t1_i0_s3_itag_q), + + .rv0_instr_i1_vld(rv0_instr_i1_dep_val[1]), + .rv0_instr_i1_t1_v(rv0_t1_i1_t1_v_q), + .rv0_instr_i1_t2_v(rv0_t1_i1_t2_v_q), + .rv0_instr_i1_t3_v(rv0_t1_i1_t3_v_q), + .rv0_instr_i1_itag(rv0_t1_i1_itag_q), + + .rv0_instr_i1_s1_v (rv0_t1_i1_s1_v_q), + .rv0_instr_i1_s1_itag(rv0_t1_i1_s1_itag_q), + .rv0_instr_i1_s2_v (rv0_t1_i1_s2_v_q), + .rv0_instr_i1_s2_itag(rv0_t1_i1_s2_itag_q), + .rv0_instr_i1_s3_v (rv0_t1_i1_s3_v_q), + .rv0_instr_i1_s3_itag(rv0_t1_i1_s3_itag_q), + + .fx0_rv_itag_vld(fx0_rv_itag_vld[1]), + .fx0_rv_itag(fx0_rv_itag), + .fx1_rv_itag_vld(fx1_rv_itag_vld[1]), + .fx1_rv_itag(fx1_rv_itag), + .lq_rv_itag0_vld(lq_rv_itag0_vld[1]), + .lq_rv_itag0(lq_rv_itag0), + .lq_rv_itag1_vld(lq_rv_itag1_vld[1]), + .lq_rv_itag1(lq_rv_itag1), + .lq_rv_itag2_vld(lq_rv_itag2_vld[1]), + .lq_rv_itag2(lq_rv_itag2), + .axu0_rv_itag_vld(axu0_rv_itag_vld[1]), + .axu0_rv_itag(axu0_rv_itag), + .axu1_rv_itag_vld(axu1_rv_itag_vld[1]), + .axu1_rv_itag(axu1_rv_itag), + + .fx0_rv_itag_abort (fx0_rv_itag_abort), + .fx1_rv_itag_abort (fx1_rv_itag_abort), + .lq_rv_itag0_abort (lq_rv_itag0_abort), + .lq_rv_itag1_abort (lq_rv_itag1_abort), + .axu0_rv_itag_abort (axu0_rv_itag_abort), + .axu1_rv_itag_abort (axu1_rv_itag_abort), + + .rv0_instr_i0_s1_dep_hit(rv0_instr_i0_s1_dep_hit[1]), + .rv0_instr_i0_s2_dep_hit(rv0_instr_i0_s2_dep_hit[1]), + .rv0_instr_i0_s3_dep_hit(rv0_instr_i0_s3_dep_hit[1]), + + .rv0_instr_i1_s1_dep_hit(rv0_instr_i1_s1_dep_hit[1]), + .rv0_instr_i1_s2_dep_hit(rv0_instr_i1_s2_dep_hit[1]), + .rv0_instr_i1_s3_dep_hit(rv0_instr_i1_s3_dep_hit[1]), + + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .sg_1(sg_1), + .func_sl_thold_1(func_sl_thold_1), + .clkoff_b(clkoff_b), + .act_dis(act_dis), + .ccflush_dc(ccflush_dc), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scan_in(siv[dep1_offset]), + .scan_out(sov[dep1_offset]) + ); + + + rv_decode + dec_t1i0( + .instr(rv0_t1_i0_instr_q), + + .is_brick(rv0_t1_i0_is_brick), + .brick_cycles(rv0_t1_i0_brick) + ); + + + rv_decode + dec_t1i1( + .instr(rv0_t1_i1_instr_q), + + .is_brick(rv0_t1_i1_is_brick), + .brick_cycles(rv0_t1_i1_brick) + ); + + // side checking of instruction b sources against instruction a targets + assign rv0_instr_i1_local_s1_dep_hit[1] = rv0_t1_i1_s1_v_q & rv0_t1_i1_s1_dep_hit_q ; + assign rv0_instr_i1_local_s2_dep_hit[1] = rv0_t1_i1_s2_v_q & rv0_t1_i1_s2_dep_hit_q ; + assign rv0_instr_i1_local_s3_dep_hit[1] = rv0_t1_i1_s3_v_q & rv0_t1_i1_s3_dep_hit_q ; + + assign rv0_t1_i0_ilat = rv0_t1_i0_ilat_q | {4{(~(rv0_t1_i0_t1_v_q | rv0_t1_i0_t2_v_q | rv0_t1_i0_t3_v_q))}}; + assign rv0_t1_i1_ilat = rv0_t1_i1_ilat_q | {4{(~(rv0_t1_i1_t1_v_q | rv0_t1_i1_t2_v_q | rv0_t1_i1_t3_v_q))}}; + + assign rv0_instr_i1_s1_itag_loc[1] = rv0_t1_i1_s1_itag_q; //todo remove + assign rv0_instr_i1_s2_itag_loc[1] = rv0_t1_i1_s2_itag_q; + assign rv0_instr_i1_s3_itag_loc[1] = rv0_t1_i1_s3_itag_q; + +`endif // `ifndef THREADS1 + + + assign rv0_instr_i1_s1_dep_hit_loc = rv0_instr_i1_s1_dep_hit | rv0_instr_i1_local_s1_dep_hit; + assign rv0_instr_i1_s2_dep_hit_loc = rv0_instr_i1_s2_dep_hit | rv0_instr_i1_local_s2_dep_hit; + assign rv0_instr_i1_s3_dep_hit_loc = rv0_instr_i1_s3_dep_hit | rv0_instr_i1_local_s3_dep_hit; + + + + //------------------------------------------------------------------------------------------------------------ + // FX0 RV0 + //------------------------------------------------------------------------------------------------------------ + generate + if (`THREADS == 1) + begin : t1 + assign rv0_fx0_instr_i0_vld = rv0_t0_i0_vld_q; + assign rv0_fx0_instr_i0_rte_fx0 = rv0_t0_i0_rte_fx0_q; + assign rv0_fx0_instr_i1_vld = rv0_t0_i1_vld_q; + assign rv0_fx0_instr_i1_rte_fx0 = rv0_t0_i1_rte_fx0_q; + + assign rv0_fx0_instr_i0_s1_dep_hit = rv0_instr_i0_s1_dep_hit[0]; + assign rv0_fx0_instr_i0_s2_dep_hit = rv0_instr_i0_s2_dep_hit[0]; + assign rv0_fx0_instr_i0_s3_dep_hit = rv0_instr_i0_s3_dep_hit[0]; + assign rv0_fx0_instr_i0_s1_itag = rv0_t0_i0_s1_itag_q; + assign rv0_fx0_instr_i0_s2_itag = rv0_t0_i0_s2_itag_q; + assign rv0_fx0_instr_i0_s3_itag = rv0_t0_i0_s3_itag_q; + assign rv0_fx0_instr_i1_s1_dep_hit = rv0_instr_i1_s1_dep_hit_loc[0]; + assign rv0_fx0_instr_i1_s2_dep_hit = rv0_instr_i1_s2_dep_hit_loc[0]; + assign rv0_fx0_instr_i1_s3_dep_hit = rv0_instr_i1_s3_dep_hit_loc[0]; + assign rv0_fx0_instr_i1_s1_itag = rv0_instr_i1_s1_itag_loc[0]; + assign rv0_fx0_instr_i1_s2_itag = rv0_instr_i1_s2_itag_loc[0]; + assign rv0_fx0_instr_i1_s3_itag = rv0_instr_i1_s3_itag_loc[0]; + //------------------------------------------------------------------------------------------------------------ + // FX0 RV1 + //------------------------------------------------------------------------------------------------------------ + assign rv0_fx0_instr_i0_instr = rv0_t0_i0_instr_q; + assign rv0_fx0_instr_i0_ifar = rv0_t0_i0_ifar_q; + assign rv0_fx0_instr_i0_ucode = rv0_t0_i0_ucode_q; + assign rv0_fx0_instr_i0_ucode_cnt = rv0_t0_i0_ucode_cnt_q; + assign rv0_fx0_instr_i0_itag = rv0_t0_i0_itag_q; + assign rv0_fx0_instr_i0_ord = rv0_t0_i0_ord_q; + assign rv0_fx0_instr_i0_cord = rv0_t0_i0_cord_q; + + assign rv0_fx0_instr_i0_t1_v = rv0_t0_i0_t1_v_q; + assign rv0_fx0_instr_i0_t1_p = rv0_t0_i0_t1_p_q; + assign rv0_fx0_instr_i0_t1_t = rv0_t0_i0_t1_t_q; + assign rv0_fx0_instr_i0_t2_v = rv0_t0_i0_t2_v_q; + assign rv0_fx0_instr_i0_t2_p = rv0_t0_i0_t2_p_q; + assign rv0_fx0_instr_i0_t2_t = rv0_t0_i0_t2_t_q; + assign rv0_fx0_instr_i0_t3_v = rv0_t0_i0_t3_v_q; + assign rv0_fx0_instr_i0_t3_p = rv0_t0_i0_t3_p_q; + assign rv0_fx0_instr_i0_t3_t = rv0_t0_i0_t3_t_q; + + assign rv0_fx0_instr_i0_s1_v = rv0_t0_i0_s1_v_q; + assign rv0_fx0_instr_i0_s1_p = rv0_t0_i0_s1_p_q; + assign rv0_fx0_instr_i0_s1_t = rv0_t0_i0_s1_t_q; + assign rv0_fx0_instr_i0_s2_v = rv0_t0_i0_s2_v_q; + assign rv0_fx0_instr_i0_s2_p = rv0_t0_i0_s2_p_q; + assign rv0_fx0_instr_i0_s2_t = rv0_t0_i0_s2_t_q; + assign rv0_fx0_instr_i0_s3_v = rv0_t0_i0_s3_v_q; + assign rv0_fx0_instr_i0_s3_p = rv0_t0_i0_s3_p_q; + assign rv0_fx0_instr_i0_s3_t = rv0_t0_i0_s3_t_q; + + assign rv0_fx0_instr_i0_ilat = rv0_t0_i0_ilat; + assign rv0_fx0_instr_i0_branch = rv0_t0_i0_branch_q; + assign rv0_fx0_instr_i0_spare = rv0_t0_i0_spare_q; + assign rv0_fx0_instr_i0_is_brick = rv0_t0_i0_is_brick; + assign rv0_fx0_instr_i0_brick = rv0_t0_i0_brick; + + assign rv0_fx0_instr_i1_instr = rv0_t0_i1_instr_q; + assign rv0_fx0_instr_i1_ifar = rv0_t0_i1_ifar_q; + assign rv0_fx0_instr_i1_ucode = rv0_t0_i1_ucode_q; + assign rv0_fx0_instr_i1_ucode_cnt = rv0_t0_i1_ucode_cnt_q; + assign rv0_fx0_instr_i1_itag = rv0_t0_i1_itag_q; + assign rv0_fx0_instr_i1_ord = rv0_t0_i1_ord_q; + assign rv0_fx0_instr_i1_cord = rv0_t0_i1_cord_q; + + assign rv0_fx0_instr_i1_t1_v = rv0_t0_i1_t1_v_q; + assign rv0_fx0_instr_i1_t1_p = rv0_t0_i1_t1_p_q; + assign rv0_fx0_instr_i1_t1_t = rv0_t0_i1_t1_t_q; + assign rv0_fx0_instr_i1_t2_v = rv0_t0_i1_t2_v_q; + assign rv0_fx0_instr_i1_t2_p = rv0_t0_i1_t2_p_q; + assign rv0_fx0_instr_i1_t2_t = rv0_t0_i1_t2_t_q; + assign rv0_fx0_instr_i1_t3_v = rv0_t0_i1_t3_v_q; + assign rv0_fx0_instr_i1_t3_p = rv0_t0_i1_t3_p_q; + assign rv0_fx0_instr_i1_t3_t = rv0_t0_i1_t3_t_q; + + assign rv0_fx0_instr_i1_s1_v = rv0_t0_i1_s1_v_q; + assign rv0_fx0_instr_i1_s1_p = rv0_t0_i1_s1_p_q; + assign rv0_fx0_instr_i1_s1_t = rv0_t0_i1_s1_t_q; + assign rv0_fx0_instr_i1_s2_v = rv0_t0_i1_s2_v_q; + assign rv0_fx0_instr_i1_s2_p = rv0_t0_i1_s2_p_q; + assign rv0_fx0_instr_i1_s2_t = rv0_t0_i1_s2_t_q; + assign rv0_fx0_instr_i1_s3_v = rv0_t0_i1_s3_v_q; + assign rv0_fx0_instr_i1_s3_p = rv0_t0_i1_s3_p_q; + assign rv0_fx0_instr_i1_s3_t = rv0_t0_i1_s3_t_q; + + assign rv0_fx0_instr_i1_ilat = rv0_t0_i1_ilat; + assign rv0_fx0_instr_i1_branch = rv0_t0_i1_branch_q; + assign rv0_fx0_instr_i1_spare = rv0_t0_i1_spare_q; + assign rv0_fx0_instr_i1_is_brick = rv0_t0_i1_is_brick; + assign rv0_fx0_instr_i1_brick = rv0_t0_i1_brick; + + //------------------------------------------------------------------------------------------------------------ + // fx1 RV0 + //------------------------------------------------------------------------------------------------------------ + assign rv0_fx1_instr_i0_vld = rv0_t0_i0_vld_q; + assign rv0_fx1_instr_i0_rte_fx1 = rv0_t0_i0_rte_fx1_q; + assign rv0_fx1_instr_i1_vld = rv0_t0_i1_vld_q; + assign rv0_fx1_instr_i1_rte_fx1 = rv0_t0_i1_rte_fx1_q; + + assign rv0_fx1_instr_i0_s1_dep_hit = rv0_instr_i0_s1_dep_hit[0]; + assign rv0_fx1_instr_i0_s2_dep_hit = rv0_instr_i0_s2_dep_hit[0]; + assign rv0_fx1_instr_i0_s3_dep_hit = rv0_instr_i0_s3_dep_hit[0]; + assign rv0_fx1_instr_i0_s1_itag = rv0_t0_i0_s1_itag_q; + assign rv0_fx1_instr_i0_s2_itag = rv0_t0_i0_s2_itag_q; + assign rv0_fx1_instr_i0_s3_itag = rv0_t0_i0_s3_itag_q; + assign rv0_fx1_instr_i1_s1_dep_hit = rv0_instr_i1_s1_dep_hit_loc[0]; + assign rv0_fx1_instr_i1_s2_dep_hit = rv0_instr_i1_s2_dep_hit_loc[0]; + assign rv0_fx1_instr_i1_s3_dep_hit = rv0_instr_i1_s3_dep_hit_loc[0]; + assign rv0_fx1_instr_i1_s1_itag = rv0_instr_i1_s1_itag_loc[0]; + assign rv0_fx1_instr_i1_s2_itag = rv0_instr_i1_s2_itag_loc[0]; + assign rv0_fx1_instr_i1_s3_itag = rv0_instr_i1_s3_itag_loc[0]; + //------------------------------------------------------------------------------------------------------------ + // fx1 RV1 + //------------------------------------------------------------------------------------------------------------ + assign rv0_fx1_instr_i0_instr = rv0_t0_i0_instr_q; + assign rv0_fx1_instr_i0_ucode = rv0_t0_i0_ucode_q; + assign rv0_fx1_instr_i0_itag = rv0_t0_i0_itag_q; + + assign rv0_fx1_instr_i0_t1_v = rv0_t0_i0_t1_v_q; + assign rv0_fx1_instr_i0_t1_p = rv0_t0_i0_t1_p_q; + assign rv0_fx1_instr_i0_t2_v = rv0_t0_i0_t2_v_q; + assign rv0_fx1_instr_i0_t2_p = rv0_t0_i0_t2_p_q; + assign rv0_fx1_instr_i0_t3_v = rv0_t0_i0_t3_v_q; + assign rv0_fx1_instr_i0_t3_p = rv0_t0_i0_t3_p_q; + + assign rv0_fx1_instr_i0_s1_v = rv0_t0_i0_s1_v_q; + assign rv0_fx1_instr_i0_s1_p = rv0_t0_i0_s1_p_q; + assign rv0_fx1_instr_i0_s1_t = rv0_t0_i0_s1_t_q; + assign rv0_fx1_instr_i0_s2_v = rv0_t0_i0_s2_v_q; + assign rv0_fx1_instr_i0_s2_p = rv0_t0_i0_s2_p_q; + assign rv0_fx1_instr_i0_s2_t = rv0_t0_i0_s2_t_q; + assign rv0_fx1_instr_i0_s3_v = rv0_t0_i0_s3_v_q; + assign rv0_fx1_instr_i0_s3_p = rv0_t0_i0_s3_p_q; + assign rv0_fx1_instr_i0_s3_t = rv0_t0_i0_s3_t_q; + + assign rv0_fx1_instr_i0_ilat = rv0_t0_i0_ilat; + assign rv0_fx1_instr_i0_isStore = rv0_t0_i0_isStore_q; + assign rv0_fx1_instr_i0_spare = rv0_t0_i0_spare_q; + assign rv0_fx1_instr_i0_is_brick = rv0_t0_i0_is_brick; + assign rv0_fx1_instr_i0_brick = rv0_t0_i0_brick; + + assign rv0_fx1_instr_i1_instr = rv0_t0_i1_instr_q; + assign rv0_fx1_instr_i1_ucode = rv0_t0_i1_ucode_q; + assign rv0_fx1_instr_i1_itag = rv0_t0_i1_itag_q; + + assign rv0_fx1_instr_i1_t1_v = rv0_t0_i1_t1_v_q; + assign rv0_fx1_instr_i1_t1_p = rv0_t0_i1_t1_p_q; + assign rv0_fx1_instr_i1_t2_v = rv0_t0_i1_t2_v_q; + assign rv0_fx1_instr_i1_t2_p = rv0_t0_i1_t2_p_q; + assign rv0_fx1_instr_i1_t3_v = rv0_t0_i1_t3_v_q; + assign rv0_fx1_instr_i1_t3_p = rv0_t0_i1_t3_p_q; + + assign rv0_fx1_instr_i1_s1_v = rv0_t0_i1_s1_v_q; + assign rv0_fx1_instr_i1_s1_p = rv0_t0_i1_s1_p_q; + assign rv0_fx1_instr_i1_s1_t = rv0_t0_i1_s1_t_q; + assign rv0_fx1_instr_i1_s2_v = rv0_t0_i1_s2_v_q; + assign rv0_fx1_instr_i1_s2_p = rv0_t0_i1_s2_p_q; + assign rv0_fx1_instr_i1_s2_t = rv0_t0_i1_s2_t_q; + assign rv0_fx1_instr_i1_s3_v = rv0_t0_i1_s3_v_q; + assign rv0_fx1_instr_i1_s3_p = rv0_t0_i1_s3_p_q; + assign rv0_fx1_instr_i1_s3_t = rv0_t0_i1_s3_t_q; + + assign rv0_fx1_instr_i1_ilat = rv0_t0_i1_ilat; + assign rv0_fx1_instr_i1_isStore = rv0_t0_i1_isStore_q; + assign rv0_fx1_instr_i1_spare = rv0_t0_i1_spare_q; + assign rv0_fx1_instr_i1_is_brick = rv0_t0_i1_is_brick; + assign rv0_fx1_instr_i1_brick = rv0_t0_i1_brick; + + //------------------------------------------------------------------------------------------------------------ + // lq RV0 + //------------------------------------------------------------------------------------------------------------ + assign rv0_lq_instr_i0_vld = rv0_t0_i0_vld_q; + assign rv0_lq_instr_i0_rte_lq = rv0_t0_i0_rte_lq_q; + assign rv0_lq_instr_i1_vld = rv0_t0_i1_vld_q; + assign rv0_lq_instr_i1_rte_lq = rv0_t0_i1_rte_lq_q; + + assign rv0_lq_instr_i0_s1_dep_hit = rv0_instr_i0_s1_dep_hit[0]; + assign rv0_lq_instr_i0_s2_dep_hit = rv0_instr_i0_s2_dep_hit[0]; + assign rv0_lq_instr_i0_s1_itag = rv0_t0_i0_s1_itag_q; + assign rv0_lq_instr_i0_s2_itag = rv0_t0_i0_s2_itag_q; + assign rv0_lq_instr_i1_s1_dep_hit = rv0_instr_i1_s1_dep_hit_loc[0]; + assign rv0_lq_instr_i1_s2_dep_hit = rv0_instr_i1_s2_dep_hit_loc[0]; + assign rv0_lq_instr_i1_s1_itag = rv0_instr_i1_s1_itag_loc[0]; + assign rv0_lq_instr_i1_s2_itag = rv0_instr_i1_s2_itag_loc[0]; + //------------------------------------------------------------------------------------------------------------ + // lq RV1 + //------------------------------------------------------------------------------------------------------------ + + assign rv1_lq_instr_i0_vld_d = rv0_t0_i0_vld_q; + assign rv1_lq_instr_i1_vld_d = rv0_t0_i1_vld_q; + + assign rv1_lq_instr_i0_rte_lq_d = rv0_t0_i0_rte_lq_q; + assign rv1_lq_instr_i1_rte_lq_d = rv0_t0_i1_rte_lq_q; + + assign rv1_lq_instr_i0_rte_sq_d = rv0_t0_i0_rte_sq_q; + assign rv1_lq_instr_i1_rte_sq_d = rv0_t0_i1_rte_sq_q; + + assign rv0_lq_instr_i0_instr = rv0_t0_i0_instr_q; + assign rv0_lq_instr_i0_ifar = rv0_t0_i0_ifar_q[61 - `PF_IAR_BITS + 1:61]; + assign rv1_lq_instr_i0_ucode_d = rv0_t0_i0_ucode_q; + assign rv1_lq_instr_i0_2ucode_d = rv0_t0_i0_2ucode_q; + assign rv1_lq_instr_i0_ucode_cnt_d = rv0_t0_i0_ucode_cnt_q; + assign rv1_lq_instr_i0_itag_d = rv0_t0_i0_itag_q; + assign rv0_lq_instr_i0_ord = rv0_t0_i0_ord_q; + assign rv0_lq_instr_i0_cord = rv0_t0_i0_cord_q; + assign rv0_lq_instr_i0_spec = rv0_t0_i0_spec_q; + + assign rv0_lq_instr_i0_t1_v = rv0_t0_i0_t1_v_q; + assign rv0_lq_instr_i0_t1_p = rv0_t0_i0_t1_p_q; + assign rv0_lq_instr_i0_t2_v = rv0_t0_i0_t2_v_q; + assign rv0_lq_instr_i0_t2_p = rv0_t0_i0_t2_p_q; + assign rv0_lq_instr_i0_t2_t = rv0_t0_i0_t2_t_q; + assign rv0_lq_instr_i0_t3_v = rv0_t0_i0_t3_v_q; + assign rv0_lq_instr_i0_t3_p = rv0_t0_i0_t3_p_q; + assign rv0_lq_instr_i0_t3_t = rv0_t0_i0_t3_t_q; + + assign rv0_lq_instr_i0_s1_v = rv0_t0_i0_s1_v_q; + assign rv0_lq_instr_i0_s1_p = rv0_t0_i0_s1_p_q; + assign rv0_lq_instr_i0_s1_t = rv0_t0_i0_s1_t_q; + assign rv0_lq_instr_i0_s2_v = rv0_t0_i0_s2_v_q; + assign rv0_lq_instr_i0_s2_p = rv0_t0_i0_s2_p_q; + assign rv0_lq_instr_i0_s2_t = rv0_t0_i0_s2_t_q; + assign rv0_lq_instr_i0_s3_v = rv0_t0_i0_s3_v_q; + assign rv0_lq_instr_i0_s3_p = rv0_t0_i0_s3_p_q; + assign rv1_lq_instr_i0_s3_t_d = rv0_t0_i0_s3_t_q; + + assign rv1_lq_instr_i0_isLoad_d = rv0_t0_i0_isLoad_q; + assign rv1_lq_instr_i0_isStore_d = rv0_t0_i0_isStore_q; + assign rv0_lq_instr_i0_spare = rv0_t0_i0_spare_q; + assign rv0_lq_instr_i0_is_brick = rv0_t0_i0_is_brick; + assign rv0_lq_instr_i0_brick = rv0_t0_i0_brick; + + assign rv0_lq_instr_i1_instr = rv0_t0_i1_instr_q; + assign rv0_lq_instr_i1_ifar = rv0_t0_i1_ifar_q[61 - `PF_IAR_BITS + 1:61]; + assign rv1_lq_instr_i1_ucode_d = rv0_t0_i1_ucode_q; + assign rv1_lq_instr_i1_2ucode_d = 1'b0; + assign rv1_lq_instr_i1_ucode_cnt_d = rv0_t0_i1_ucode_cnt_q; + assign rv1_lq_instr_i1_itag_d = rv0_t0_i1_itag_q; + assign rv0_lq_instr_i1_ord = rv0_t0_i1_ord_q; + assign rv0_lq_instr_i1_cord = rv0_t0_i1_cord_q; + assign rv0_lq_instr_i1_spec = rv0_t0_i1_spec_q; + + assign rv0_lq_instr_i1_t1_v = rv0_t0_i1_t1_v_q; + assign rv0_lq_instr_i1_t1_p = rv0_t0_i1_t1_p_q; + assign rv0_lq_instr_i1_t2_v = rv0_t0_i1_t2_v_q; + assign rv0_lq_instr_i1_t2_p = rv0_t0_i1_t2_p_q; + assign rv0_lq_instr_i1_t2_t = rv0_t0_i1_t2_t_q; + assign rv0_lq_instr_i1_t3_v = rv0_t0_i1_t3_v_q; + assign rv0_lq_instr_i1_t3_p = rv0_t0_i1_t3_p_q; + assign rv0_lq_instr_i1_t3_t = rv0_t0_i1_t3_t_q; + + assign rv0_lq_instr_i1_s1_v = rv0_t0_i1_s1_v_q; + assign rv0_lq_instr_i1_s1_p = rv0_t0_i1_s1_p_q; + assign rv0_lq_instr_i1_s1_t = rv0_t0_i1_s1_t_q; + assign rv0_lq_instr_i1_s2_v = rv0_t0_i1_s2_v_q; + assign rv0_lq_instr_i1_s2_p = rv0_t0_i1_s2_p_q; + assign rv0_lq_instr_i1_s2_t = rv0_t0_i1_s2_t_q; + assign rv1_lq_instr_i1_s3_t_d = rv0_t0_i1_s3_t_q; + + assign rv1_lq_instr_i1_isLoad_d = rv0_t0_i1_isLoad_q; + assign rv1_lq_instr_i1_isStore_d = rv0_t0_i1_isStore_q; + assign rv0_lq_instr_i1_spare = rv0_t0_i1_spare_q; + assign rv0_lq_instr_i1_is_brick = rv0_t0_i1_is_brick; + assign rv0_lq_instr_i1_brick = rv0_t0_i1_brick; + + //------------------------------------------------------------------------------------------------------------ + // axu0 RV0 + //------------------------------------------------------------------------------------------------------------ + assign rv0_axu0_instr_i0_vld = rv0_t0_i0_vld_q; + assign rv0_axu0_instr_i0_rte_axu0 = rv0_t0_i0_rte_axu0_q; + assign rv0_axu0_instr_i1_vld = rv0_t0_i1_vld_q; + assign rv0_axu0_instr_i1_rte_axu0 = rv0_t0_i1_rte_axu0_q; + + assign rv0_axu0_instr_i0_s1_dep_hit = rv0_instr_i0_s1_dep_hit[0]; + assign rv0_axu0_instr_i0_s2_dep_hit = rv0_instr_i0_s2_dep_hit[0]; + assign rv0_axu0_instr_i0_s3_dep_hit = rv0_instr_i0_s3_dep_hit[0]; + assign rv0_axu0_instr_i0_s1_itag = rv0_t0_i0_s1_itag_q; + assign rv0_axu0_instr_i0_s2_itag = rv0_t0_i0_s2_itag_q; + assign rv0_axu0_instr_i0_s3_itag = rv0_t0_i0_s3_itag_q; + assign rv0_axu0_instr_i1_s1_dep_hit = rv0_instr_i1_s1_dep_hit_loc[0]; + assign rv0_axu0_instr_i1_s2_dep_hit = rv0_instr_i1_s2_dep_hit_loc[0]; + assign rv0_axu0_instr_i1_s3_dep_hit = rv0_instr_i1_s3_dep_hit_loc[0]; + assign rv0_axu0_instr_i1_s1_itag = rv0_instr_i1_s1_itag_loc[0]; + assign rv0_axu0_instr_i1_s2_itag = rv0_instr_i1_s2_itag_loc[0]; + assign rv0_axu0_instr_i1_s3_itag = rv0_instr_i1_s3_itag_loc[0]; + //------------------------------------------------------------------------------------------------------------ + // axu0 RV1 + //------------------------------------------------------------------------------------------------------------ + assign rv0_axu0_instr_i0_instr = rv0_t0_i0_instr_q; + assign rv0_axu0_instr_i0_ucode = rv0_t0_i0_ucode_q; + assign rv0_axu0_instr_i0_itag = rv0_t0_i0_itag_q; + assign rv0_axu0_instr_i0_ord = rv0_t0_i0_ord_q; + assign rv0_axu0_instr_i0_cord = rv0_t0_i0_cord_q; + + assign rv0_axu0_instr_i0_t1_v = rv0_t0_i0_t1_v_q; + assign rv0_axu0_instr_i0_t1_p = rv0_t0_i0_t1_p_q; + assign rv0_axu0_instr_i0_t2_p = rv0_t0_i0_t2_p_q; + assign rv0_axu0_instr_i0_t3_p = rv0_t0_i0_t3_p_q; + + assign rv0_axu0_instr_i0_s1_v = rv0_t0_i0_s1_v_q; + assign rv0_axu0_instr_i0_s1_p = rv0_t0_i0_s1_p_q; + assign rv0_axu0_instr_i0_s2_v = rv0_t0_i0_s2_v_q; + assign rv0_axu0_instr_i0_s2_p = rv0_t0_i0_s2_p_q; + assign rv0_axu0_instr_i0_s3_v = rv0_t0_i0_s3_v_q; + assign rv0_axu0_instr_i0_s3_p = rv0_t0_i0_s3_p_q; + + assign rv0_axu0_instr_i0_isStore = rv0_t0_i0_isStore_q; + assign rv0_axu0_instr_i0_spare = rv0_t0_i0_spare_q; + + assign rv0_axu0_instr_i1_instr = rv0_t0_i1_instr_q; + assign rv0_axu0_instr_i1_ucode = rv0_t0_i1_ucode_q; + assign rv0_axu0_instr_i1_itag = rv0_t0_i1_itag_q; + assign rv0_axu0_instr_i1_ord = rv0_t0_i1_ord_q; + assign rv0_axu0_instr_i1_cord = rv0_t0_i1_cord_q; + + assign rv0_axu0_instr_i1_t1_v = rv0_t0_i1_t1_v_q; + assign rv0_axu0_instr_i1_t1_p = rv0_t0_i1_t1_p_q; + assign rv0_axu0_instr_i1_t2_p = rv0_t0_i1_t2_p_q; + assign rv0_axu0_instr_i1_t3_p = rv0_t0_i1_t3_p_q; + + assign rv0_axu0_instr_i1_s1_v = rv0_t0_i1_s1_v_q; + assign rv0_axu0_instr_i1_s1_p = rv0_t0_i1_s1_p_q; + assign rv0_axu0_instr_i1_s2_v = rv0_t0_i1_s2_v_q; + assign rv0_axu0_instr_i1_s2_p = rv0_t0_i1_s2_p_q; + assign rv0_axu0_instr_i1_s3_v = rv0_t0_i1_s3_v_q; + assign rv0_axu0_instr_i1_s3_p = rv0_t0_i1_s3_p_q; + + assign rv0_axu0_instr_i1_isStore = rv0_t0_i1_isStore_q; + assign rv0_axu0_instr_i1_spare = rv0_t0_i1_spare_q; + end + endgenerate + + // t1 : + + //------------------------------------------------------------------------------------------------------------ + // FX0 RVS -- Thread0 Thread1 -- + //------------------------------------------------------------------------------------------------------------ + // I0 I1 I0(0) I1(0) I0(1) I1(1) --- + // (-----, -----) <= ( 0, 0, 0, 0) + // (-----, I1(1)) <= ( 0, 0, 0, 1) + // (I0(1), -----) <= ( 0, 0, 1, 0) + // (I0(1), I1(1)) <= ( 0, 0, 1, 1) + // (-----, I1(0)) <= ( 0, 1, 0, 0) + // (I1(0), I1(1)) <= ( 0, 1, 0, 1) + // (I1(0), I0(1)) <= ( 0, 1, 1, 0) + // (I0(0), -----) <= ( 1, 0, 0, 0) + // (I0(0), I1(1)) <= ( 1, 0, 0, 1) + // (I0(0), I0(1)) <= ( 1, 0, 1, 0) + // (I0(0), I1(0)) <= ( 1, 1, 0, 0) + + //------------------------------------------------------------------------------------------------------------ + // -- Thread0 Thread1 -- + //------------------------------------------------------------------------------------------------------------ + // -- I0(0) I1(0) I0(1) I1(1) --- + // fx0_i0: x x x + // fx0_i1 x x x + + //------------------------------------------------------------------------------------------------------------ + // FX0 RV0 + //------------------------------------------------------------------------------------------------------------ +`ifndef THREADS1 + + assign rv0_fx0_i0_sel[0] = rv0_t0_i0_rte_fx0_q; + assign rv0_fx0_i0_sel[1] = rv0_t0_i1_rte_fx0_q & (rv0_t1_i0_rte_fx0_q | rv0_t1_i1_rte_fx0_q); + assign rv0_fx0_i0_sel[2] = rv0_t1_i0_rte_fx0_q & (~rv0_t0_i0_rte_fx0_q) & (~rv0_t0_i1_rte_fx0_q); + assign rv0_fx0_i1_sel[0] = rv0_t0_i1_rte_fx0_q & (~rv0_t1_i0_rte_fx0_q) & (~rv0_t1_i1_rte_fx0_q); + assign rv0_fx0_i1_sel[1] = rv0_t1_i0_rte_fx0_q & (rv0_t0_i0_rte_fx0_q | rv0_t0_i1_rte_fx0_q); + assign rv0_fx0_i1_sel[2] = rv0_t1_i1_rte_fx0_q; + + assign rv0_fx0_instr_i0_vld = {((rv0_fx0_i0_sel[0] & rv0_t0_i0_vld_q) | (rv0_fx0_i0_sel[1] & rv0_t0_i1_vld_q)), (rv0_fx0_i0_sel[2] & rv0_t1_i0_vld_q)}; + assign rv0_fx0_instr_i1_vld = {(rv0_fx0_i1_sel[0] & rv0_t0_i1_vld_q), ((rv0_fx0_i1_sel[1] & rv0_t1_i0_vld_q) | (rv0_fx0_i1_sel[2] & rv0_t1_i1_vld_q))}; + + assign rv0_fx0_instr_i0_rte_fx0 = |(rv0_fx0_i0_sel); + + assign rv0_fx0_instr_i1_rte_fx0 = |(rv0_fx0_i1_sel); + + assign rv0_fx0_instr_i0_s1_dep_hit = (rv0_instr_i0_s1_dep_hit[0] & rv0_fx0_i0_sel[0]) | (rv0_instr_i1_s1_dep_hit_loc[0] & rv0_fx0_i0_sel[1]) | (rv0_instr_i0_s1_dep_hit[1] & rv0_fx0_i0_sel[2]); + assign rv0_fx0_instr_i0_s2_dep_hit = (rv0_instr_i0_s2_dep_hit[0] & rv0_fx0_i0_sel[0]) | (rv0_instr_i1_s2_dep_hit_loc[0] & rv0_fx0_i0_sel[1]) | (rv0_instr_i0_s2_dep_hit[1] & rv0_fx0_i0_sel[2]); + assign rv0_fx0_instr_i0_s3_dep_hit = (rv0_instr_i0_s3_dep_hit[0] & rv0_fx0_i0_sel[0]) | (rv0_instr_i1_s3_dep_hit_loc[0] & rv0_fx0_i0_sel[1]) | (rv0_instr_i0_s3_dep_hit[1] & rv0_fx0_i0_sel[2]); + + assign rv0_fx0_instr_i0_s1_itag = (rv0_t0_i0_s1_itag_q & {`ITAG_SIZE_ENC{rv0_fx0_i0_sel[0]}}) | (rv0_instr_i1_s1_itag_loc[0] & {`ITAG_SIZE_ENC{rv0_fx0_i0_sel[1]}}) | (rv0_t1_i0_s1_itag_q & {`ITAG_SIZE_ENC{rv0_fx0_i0_sel[2]}}); + assign rv0_fx0_instr_i0_s2_itag = (rv0_t0_i0_s2_itag_q & {`ITAG_SIZE_ENC{rv0_fx0_i0_sel[0]}}) | (rv0_instr_i1_s2_itag_loc[0] & {`ITAG_SIZE_ENC{rv0_fx0_i0_sel[1]}}) | (rv0_t1_i0_s2_itag_q & {`ITAG_SIZE_ENC{rv0_fx0_i0_sel[2]}}); + assign rv0_fx0_instr_i0_s3_itag = (rv0_t0_i0_s3_itag_q & {`ITAG_SIZE_ENC{rv0_fx0_i0_sel[0]}}) | (rv0_instr_i1_s3_itag_loc[0] & {`ITAG_SIZE_ENC{rv0_fx0_i0_sel[1]}}) | (rv0_t1_i0_s3_itag_q & {`ITAG_SIZE_ENC{rv0_fx0_i0_sel[2]}}); + + assign rv0_fx0_instr_i1_s1_dep_hit = (rv0_instr_i1_s1_dep_hit_loc[0] & rv0_fx0_i1_sel[0]) | (rv0_instr_i0_s1_dep_hit[1] & rv0_fx0_i1_sel[1]) | (rv0_instr_i1_s1_dep_hit_loc[1] & rv0_fx0_i1_sel[2]); + assign rv0_fx0_instr_i1_s2_dep_hit = (rv0_instr_i1_s2_dep_hit_loc[0] & rv0_fx0_i1_sel[0]) | (rv0_instr_i0_s2_dep_hit[1] & rv0_fx0_i1_sel[1]) | (rv0_instr_i1_s2_dep_hit_loc[1] & rv0_fx0_i1_sel[2]); + assign rv0_fx0_instr_i1_s3_dep_hit = (rv0_instr_i1_s3_dep_hit_loc[0] & rv0_fx0_i1_sel[0]) | (rv0_instr_i0_s3_dep_hit[1] & rv0_fx0_i1_sel[1]) | (rv0_instr_i1_s3_dep_hit_loc[1] & rv0_fx0_i1_sel[2]); + assign rv0_fx0_instr_i1_s1_itag = (rv0_instr_i1_s1_itag_loc[0] & {`ITAG_SIZE_ENC{rv0_fx0_i1_sel[0]}}) | (rv0_t1_i0_s1_itag_q & {`ITAG_SIZE_ENC{rv0_fx0_i1_sel[1]}}) | (rv0_instr_i1_s1_itag_loc[1] & {`ITAG_SIZE_ENC{rv0_fx0_i1_sel[2]}}); + assign rv0_fx0_instr_i1_s2_itag = (rv0_instr_i1_s2_itag_loc[0] & {`ITAG_SIZE_ENC{rv0_fx0_i1_sel[0]}}) | (rv0_t1_i0_s2_itag_q & {`ITAG_SIZE_ENC{rv0_fx0_i1_sel[1]}}) | (rv0_instr_i1_s2_itag_loc[1] & {`ITAG_SIZE_ENC{rv0_fx0_i1_sel[2]}}); + assign rv0_fx0_instr_i1_s3_itag = (rv0_instr_i1_s3_itag_loc[0] & {`ITAG_SIZE_ENC{rv0_fx0_i1_sel[0]}}) | (rv0_t1_i0_s3_itag_q & {`ITAG_SIZE_ENC{rv0_fx0_i1_sel[1]}}) | (rv0_instr_i1_s3_itag_loc[1] & {`ITAG_SIZE_ENC{rv0_fx0_i1_sel[2]}}); + + //------------------------------------------------------------------------------------------------------------ + // FX0 RV1 + //------------------------------------------------------------------------------------------------------------ + + assign rv0_fx0_instr_i0_instr = (rv0_t0_i0_instr_q & {32{rv0_fx0_i0_sel[0]}}) | (rv0_t0_i1_instr_q & {32{rv0_fx0_i0_sel[1]}}) | (rv0_t1_i0_instr_q & {32{rv0_fx0_i0_sel[2]}}); + assign rv0_fx0_instr_i0_ifar = (rv0_t0_i0_ifar_q & {`EFF_IFAR_WIDTH{rv0_fx0_i0_sel[0]}}) | (rv0_t0_i1_ifar_q & {`EFF_IFAR_WIDTH{rv0_fx0_i0_sel[1]}}) | (rv0_t1_i0_ifar_q & {`EFF_IFAR_WIDTH{rv0_fx0_i0_sel[2]}}); + assign rv0_fx0_instr_i0_ucode = (rv0_t0_i0_ucode_q & {3{rv0_fx0_i0_sel[0]}}) | (rv0_t0_i1_ucode_q & {3{rv0_fx0_i0_sel[1]}}) | (rv0_t1_i0_ucode_q & {3{rv0_fx0_i0_sel[2]}}); + assign rv0_fx0_instr_i0_ucode_cnt = (rv0_t0_i0_ucode_cnt_q & {`UCODE_ENTRIES_ENC{rv0_fx0_i0_sel[0]}}) | (rv0_t0_i1_ucode_cnt_q & {`UCODE_ENTRIES_ENC{rv0_fx0_i0_sel[1]}}) | (rv0_t1_i0_ucode_cnt_q & {`UCODE_ENTRIES_ENC{rv0_fx0_i0_sel[2]}}); + assign rv0_fx0_instr_i0_itag = (rv0_t0_i0_itag_q & {`ITAG_SIZE_ENC{rv0_fx0_i0_sel[0]}}) | (rv0_t0_i1_itag_q & {`ITAG_SIZE_ENC{rv0_fx0_i0_sel[1]}}) | (rv0_t1_i0_itag_q & {`ITAG_SIZE_ENC{rv0_fx0_i0_sel[2]}}); + assign rv0_fx0_instr_i0_ord = (rv0_t0_i0_ord_q & rv0_fx0_i0_sel[0]) | ( rv0_t0_i1_ord_q & rv0_fx0_i0_sel[1]) | (rv0_t1_i0_ord_q & rv0_fx0_i0_sel[2]); + assign rv0_fx0_instr_i0_cord = (rv0_t0_i0_cord_q & rv0_fx0_i0_sel[0]) | (rv0_t0_i1_cord_q & rv0_fx0_i0_sel[1]) | (rv0_t1_i0_cord_q & rv0_fx0_i0_sel[2]); + + assign rv0_fx0_instr_i0_t1_v = (rv0_t0_i0_t1_v_q & rv0_fx0_i0_sel[0]) | (rv0_t0_i1_t1_v_q & rv0_fx0_i0_sel[1]) | (rv0_t1_i0_t1_v_q & rv0_fx0_i0_sel[2]); + assign rv0_fx0_instr_i0_t1_p = (rv0_t0_i0_t1_p_q & {`GPR_POOL_ENC{rv0_fx0_i0_sel[0]}}) | (rv0_t0_i1_t1_p_q & {`GPR_POOL_ENC{rv0_fx0_i0_sel[1]}}) | (rv0_t1_i0_t1_p_q & {`GPR_POOL_ENC{rv0_fx0_i0_sel[2]}}); + assign rv0_fx0_instr_i0_t1_t = (rv0_t0_i0_t1_t_q & {3{rv0_fx0_i0_sel[0]}}) | (rv0_t0_i1_t1_t_q & {3{rv0_fx0_i0_sel[1]}}) | (rv0_t1_i0_t1_t_q & {3{rv0_fx0_i0_sel[2]}}); + assign rv0_fx0_instr_i0_t2_v = (rv0_t0_i0_t2_v_q & rv0_fx0_i0_sel[0]) | (rv0_t0_i1_t2_v_q & rv0_fx0_i0_sel[1]) | (rv0_t1_i0_t2_v_q & rv0_fx0_i0_sel[2]); + assign rv0_fx0_instr_i0_t2_p = (rv0_t0_i0_t2_p_q & {`GPR_POOL_ENC{rv0_fx0_i0_sel[0]}}) | (rv0_t0_i1_t2_p_q & {`GPR_POOL_ENC{rv0_fx0_i0_sel[1]}}) | (rv0_t1_i0_t2_p_q & {`GPR_POOL_ENC{rv0_fx0_i0_sel[2]}}); + assign rv0_fx0_instr_i0_t2_t = (rv0_t0_i0_t2_t_q & {3{rv0_fx0_i0_sel[0]}}) | (rv0_t0_i1_t2_t_q & {3{rv0_fx0_i0_sel[1]}}) | (rv0_t1_i0_t2_t_q & {3{rv0_fx0_i0_sel[2]}}); + assign rv0_fx0_instr_i0_t3_v = (rv0_t0_i0_t3_v_q & rv0_fx0_i0_sel[0]) | (rv0_t0_i1_t3_v_q & rv0_fx0_i0_sel[1]) | (rv0_t1_i0_t3_v_q & rv0_fx0_i0_sel[2]); + assign rv0_fx0_instr_i0_t3_p = (rv0_t0_i0_t3_p_q & {`GPR_POOL_ENC{rv0_fx0_i0_sel[0]}}) | (rv0_t0_i1_t3_p_q & {`GPR_POOL_ENC{rv0_fx0_i0_sel[1]}}) | (rv0_t1_i0_t3_p_q & {`GPR_POOL_ENC{rv0_fx0_i0_sel[2]}}); + assign rv0_fx0_instr_i0_t3_t = (rv0_t0_i0_t3_t_q & {3{rv0_fx0_i0_sel[0]}}) | (rv0_t0_i1_t3_t_q & {3{rv0_fx0_i0_sel[1]}}) | (rv0_t1_i0_t3_t_q & {3{rv0_fx0_i0_sel[2]}}); + + assign rv0_fx0_instr_i0_s1_v = (rv0_t0_i0_s1_v_q & rv0_fx0_i0_sel[0]) | (rv0_t0_i1_s1_v_q & rv0_fx0_i0_sel[1]) | (rv0_t1_i0_s1_v_q & rv0_fx0_i0_sel[2]); + assign rv0_fx0_instr_i0_s1_p = (rv0_t0_i0_s1_p_q & {`GPR_POOL_ENC{rv0_fx0_i0_sel[0]}}) | (rv0_t0_i1_s1_p_q & {`GPR_POOL_ENC{rv0_fx0_i0_sel[1]}}) | (rv0_t1_i0_s1_p_q & {`GPR_POOL_ENC{rv0_fx0_i0_sel[2]}}); + assign rv0_fx0_instr_i0_s1_t = (rv0_t0_i0_s1_t_q & {3{rv0_fx0_i0_sel[0]}}) | (rv0_t0_i1_s1_t_q & {3{rv0_fx0_i0_sel[1]}}) | (rv0_t1_i0_s1_t_q & {3{rv0_fx0_i0_sel[2]}}); + assign rv0_fx0_instr_i0_s2_v = (rv0_t0_i0_s2_v_q & rv0_fx0_i0_sel[0]) | (rv0_t0_i1_s2_v_q & rv0_fx0_i0_sel[1]) | (rv0_t1_i0_s2_v_q & rv0_fx0_i0_sel[2]); + assign rv0_fx0_instr_i0_s2_p = (rv0_t0_i0_s2_p_q & {`GPR_POOL_ENC{rv0_fx0_i0_sel[0]}}) | (rv0_t0_i1_s2_p_q & {`GPR_POOL_ENC{rv0_fx0_i0_sel[1]}}) | (rv0_t1_i0_s2_p_q & {`GPR_POOL_ENC{rv0_fx0_i0_sel[2]}}); + assign rv0_fx0_instr_i0_s2_t = (rv0_t0_i0_s2_t_q & {3{rv0_fx0_i0_sel[0]}}) | (rv0_t0_i1_s2_t_q & {3{rv0_fx0_i0_sel[1]}}) | (rv0_t1_i0_s2_t_q & {3{rv0_fx0_i0_sel[2]}}); + assign rv0_fx0_instr_i0_s3_v = (rv0_t0_i0_s3_v_q & rv0_fx0_i0_sel[0]) | (rv0_t0_i1_s3_v_q & rv0_fx0_i0_sel[1]) | (rv0_t1_i0_s3_v_q & rv0_fx0_i0_sel[2]); + assign rv0_fx0_instr_i0_s3_p = (rv0_t0_i0_s3_p_q & {`GPR_POOL_ENC{rv0_fx0_i0_sel[0]}}) | (rv0_t0_i1_s3_p_q & {`GPR_POOL_ENC{rv0_fx0_i0_sel[1]}}) | (rv0_t1_i0_s3_p_q & {`GPR_POOL_ENC{rv0_fx0_i0_sel[2]}}); + assign rv0_fx0_instr_i0_s3_t = (rv0_t0_i0_s3_t_q & {3{rv0_fx0_i0_sel[0]}}) | (rv0_t0_i1_s3_t_q & {3{rv0_fx0_i0_sel[1]}}) | (rv0_t1_i0_s3_t_q & {3{rv0_fx0_i0_sel[2]}}); + + assign rv0_fx0_instr_i0_ilat = (rv0_t0_i0_ilat & {4{rv0_fx0_i0_sel[0]}}) | (rv0_t0_i1_ilat & {4{rv0_fx0_i0_sel[1]}}) | (rv0_t1_i0_ilat & {4{rv0_fx0_i0_sel[2]}}); + assign rv0_fx0_instr_i0_branch = (rv0_t0_i0_branch_q & {`G_BRANCH_LEN{rv0_fx0_i0_sel[0]}}) | (rv0_t0_i1_branch_q & {`G_BRANCH_LEN{rv0_fx0_i0_sel[1]}}) | (rv0_t1_i0_branch_q & {`G_BRANCH_LEN{rv0_fx0_i0_sel[2]}}); + assign rv0_fx0_instr_i0_spare = (rv0_t0_i0_spare_q & {4{rv0_fx0_i0_sel[0]}}) | (rv0_t0_i1_spare_q & {4{rv0_fx0_i0_sel[1]}}) | (rv0_t1_i0_spare_q & {4{rv0_fx0_i0_sel[2]}}); + assign rv0_fx0_instr_i0_is_brick = (rv0_t0_i0_is_brick & rv0_fx0_i0_sel[0]) | (rv0_t0_i1_is_brick & rv0_fx0_i0_sel[1]) | (rv0_t1_i0_is_brick & rv0_fx0_i0_sel[2]); + assign rv0_fx0_instr_i0_brick = (rv0_t0_i0_brick & {3{rv0_fx0_i0_sel[0]}}) | (rv0_t0_i1_brick & {3{rv0_fx0_i0_sel[1]}}) | (rv0_t1_i0_brick & {3{rv0_fx0_i0_sel[2]}}); + + + assign rv0_fx0_instr_i1_instr = (rv0_t0_i1_instr_q & {32{rv0_fx0_i1_sel[0]}}) | (rv0_t1_i0_instr_q & {32{rv0_fx0_i1_sel[1]}}) | (rv0_t1_i1_instr_q & {32{rv0_fx0_i1_sel[2]}}); + assign rv0_fx0_instr_i1_ifar = (rv0_t0_i1_ifar_q & {`EFF_IFAR_WIDTH{rv0_fx0_i1_sel[0]}}) | (rv0_t1_i0_ifar_q & {`EFF_IFAR_WIDTH{rv0_fx0_i1_sel[1]}}) | (rv0_t1_i1_ifar_q & {`EFF_IFAR_WIDTH{rv0_fx0_i1_sel[2]}}); + assign rv0_fx0_instr_i1_ucode = (rv0_t0_i1_ucode_q & {3{rv0_fx0_i1_sel[0]}}) | (rv0_t1_i0_ucode_q & {3{rv0_fx0_i1_sel[1]}}) | (rv0_t1_i1_ucode_q & {3{rv0_fx0_i1_sel[2]}}); + assign rv0_fx0_instr_i1_ucode_cnt = (rv0_t0_i1_ucode_cnt_q & {`UCODE_ENTRIES_ENC{rv0_fx0_i1_sel[0]}}) | (rv0_t1_i0_ucode_cnt_q & {`UCODE_ENTRIES_ENC{rv0_fx0_i1_sel[1]}}) | (rv0_t1_i1_ucode_cnt_q & {`UCODE_ENTRIES_ENC{rv0_fx0_i1_sel[2]}}); + assign rv0_fx0_instr_i1_itag = (rv0_t0_i1_itag_q & {`ITAG_SIZE_ENC{rv0_fx0_i1_sel[0]}}) | (rv0_t1_i0_itag_q & {`ITAG_SIZE_ENC{rv0_fx0_i1_sel[1]}}) | (rv0_t1_i1_itag_q & {`ITAG_SIZE_ENC{rv0_fx0_i1_sel[2]}}); + assign rv0_fx0_instr_i1_ord = (rv0_t0_i1_ord_q & rv0_fx0_i1_sel[0]) | ( rv0_t1_i0_ord_q & rv0_fx0_i1_sel[1]) | (rv0_t1_i1_ord_q & rv0_fx0_i1_sel[2]); + assign rv0_fx0_instr_i1_cord = (rv0_t0_i1_cord_q & rv0_fx0_i1_sel[0]) | (rv0_t1_i0_cord_q & rv0_fx0_i1_sel[1]) | (rv0_t1_i1_cord_q & rv0_fx0_i1_sel[2]); + + assign rv0_fx0_instr_i1_t1_v = (rv0_t0_i1_t1_v_q & rv0_fx0_i1_sel[0]) | (rv0_t1_i0_t1_v_q & rv0_fx0_i1_sel[1]) | (rv0_t1_i1_t1_v_q & rv0_fx0_i1_sel[2]); + assign rv0_fx0_instr_i1_t1_p = (rv0_t0_i1_t1_p_q & {`GPR_POOL_ENC{rv0_fx0_i1_sel[0]}}) | (rv0_t1_i0_t1_p_q & {`GPR_POOL_ENC{rv0_fx0_i1_sel[1]}}) | (rv0_t1_i1_t1_p_q & {`GPR_POOL_ENC{rv0_fx0_i1_sel[2]}}); + assign rv0_fx0_instr_i1_t1_t = (rv0_t0_i1_t1_t_q & {3{rv0_fx0_i1_sel[0]}}) | (rv0_t1_i0_t1_t_q & {3{rv0_fx0_i1_sel[1]}}) | (rv0_t1_i1_t1_t_q & {3{rv0_fx0_i1_sel[2]}}); + assign rv0_fx0_instr_i1_t2_v = (rv0_t0_i1_t2_v_q & rv0_fx0_i1_sel[0]) | (rv0_t1_i0_t2_v_q & rv0_fx0_i1_sel[1]) | (rv0_t1_i1_t2_v_q & rv0_fx0_i1_sel[2]); + assign rv0_fx0_instr_i1_t2_p = (rv0_t0_i1_t2_p_q & {`GPR_POOL_ENC{rv0_fx0_i1_sel[0]}}) | (rv0_t1_i0_t2_p_q & {`GPR_POOL_ENC{rv0_fx0_i1_sel[1]}}) | (rv0_t1_i1_t2_p_q & {`GPR_POOL_ENC{rv0_fx0_i1_sel[2]}}); + assign rv0_fx0_instr_i1_t2_t = (rv0_t0_i1_t2_t_q & {3{rv0_fx0_i1_sel[0]}}) | (rv0_t1_i0_t2_t_q & {3{rv0_fx0_i1_sel[1]}}) | (rv0_t1_i1_t2_t_q & {3{rv0_fx0_i1_sel[2]}}); + assign rv0_fx0_instr_i1_t3_v = (rv0_t0_i1_t3_v_q & rv0_fx0_i1_sel[0]) | (rv0_t1_i0_t3_v_q & rv0_fx0_i1_sel[1]) | (rv0_t1_i1_t3_v_q & rv0_fx0_i1_sel[2]); + assign rv0_fx0_instr_i1_t3_p = (rv0_t0_i1_t3_p_q & {`GPR_POOL_ENC{rv0_fx0_i1_sel[0]}}) | (rv0_t1_i0_t3_p_q & {`GPR_POOL_ENC{rv0_fx0_i1_sel[1]}}) | (rv0_t1_i1_t3_p_q & {`GPR_POOL_ENC{rv0_fx0_i1_sel[2]}}); + assign rv0_fx0_instr_i1_t3_t = (rv0_t0_i1_t3_t_q & {3{rv0_fx0_i1_sel[0]}}) | (rv0_t1_i0_t3_t_q & {3{rv0_fx0_i1_sel[1]}}) | (rv0_t1_i1_t3_t_q & {3{rv0_fx0_i1_sel[2]}}); + + assign rv0_fx0_instr_i1_s1_v = (rv0_t0_i1_s1_v_q & rv0_fx0_i1_sel[0]) | (rv0_t1_i0_s1_v_q & rv0_fx0_i1_sel[1]) | (rv0_t1_i1_s1_v_q & rv0_fx0_i1_sel[2]); + assign rv0_fx0_instr_i1_s1_p = (rv0_t0_i1_s1_p_q & {`GPR_POOL_ENC{rv0_fx0_i1_sel[0]}}) | (rv0_t1_i0_s1_p_q & {`GPR_POOL_ENC{rv0_fx0_i1_sel[1]}}) | (rv0_t1_i1_s1_p_q & {`GPR_POOL_ENC{rv0_fx0_i1_sel[2]}}); + assign rv0_fx0_instr_i1_s1_t = (rv0_t0_i1_s1_t_q & {3{rv0_fx0_i1_sel[0]}}) | (rv0_t1_i0_s1_t_q & {3{rv0_fx0_i1_sel[1]}}) | (rv0_t1_i1_s1_t_q & {3{rv0_fx0_i1_sel[2]}}); + assign rv0_fx0_instr_i1_s2_v = (rv0_t0_i1_s2_v_q & rv0_fx0_i1_sel[0]) | (rv0_t1_i0_s2_v_q & rv0_fx0_i1_sel[1]) | (rv0_t1_i1_s2_v_q & rv0_fx0_i1_sel[2]); + assign rv0_fx0_instr_i1_s2_p = (rv0_t0_i1_s2_p_q & {`GPR_POOL_ENC{rv0_fx0_i1_sel[0]}}) | (rv0_t1_i0_s2_p_q & {`GPR_POOL_ENC{rv0_fx0_i1_sel[1]}}) | (rv0_t1_i1_s2_p_q & {`GPR_POOL_ENC{rv0_fx0_i1_sel[2]}}); + assign rv0_fx0_instr_i1_s2_t = (rv0_t0_i1_s2_t_q & {3{rv0_fx0_i1_sel[0]}}) | (rv0_t1_i0_s2_t_q & {3{rv0_fx0_i1_sel[1]}}) | (rv0_t1_i1_s2_t_q & {3{rv0_fx0_i1_sel[2]}}); + assign rv0_fx0_instr_i1_s3_v = (rv0_t0_i1_s3_v_q & rv0_fx0_i1_sel[0]) | (rv0_t1_i0_s3_v_q & rv0_fx0_i1_sel[1]) | (rv0_t1_i1_s3_v_q & rv0_fx0_i1_sel[2]); + assign rv0_fx0_instr_i1_s3_p = (rv0_t0_i1_s3_p_q & {`GPR_POOL_ENC{rv0_fx0_i1_sel[0]}}) | (rv0_t1_i0_s3_p_q & {`GPR_POOL_ENC{rv0_fx0_i1_sel[1]}}) | (rv0_t1_i1_s3_p_q & {`GPR_POOL_ENC{rv0_fx0_i1_sel[2]}}); + assign rv0_fx0_instr_i1_s3_t = (rv0_t0_i1_s3_t_q & {3{rv0_fx0_i1_sel[0]}}) | (rv0_t1_i0_s3_t_q & {3{rv0_fx0_i1_sel[1]}}) | (rv0_t1_i1_s3_t_q & {3{rv0_fx0_i1_sel[2]}}); + + assign rv0_fx0_instr_i1_ilat = (rv0_t0_i1_ilat & {4{rv0_fx0_i1_sel[0]}}) | (rv0_t1_i0_ilat & {4{rv0_fx0_i1_sel[1]}}) | (rv0_t1_i1_ilat & {4{rv0_fx0_i1_sel[2]}}); + assign rv0_fx0_instr_i1_branch = (rv0_t0_i1_branch_q & {`G_BRANCH_LEN{rv0_fx0_i1_sel[0]}}) | (rv0_t1_i0_branch_q & {`G_BRANCH_LEN{rv0_fx0_i1_sel[1]}}) | (rv0_t1_i1_branch_q & {`G_BRANCH_LEN{rv0_fx0_i1_sel[2]}}); + assign rv0_fx0_instr_i1_spare = (rv0_t0_i1_spare_q & {4{rv0_fx0_i1_sel[0]}}) | (rv0_t1_i0_spare_q & {4{rv0_fx0_i1_sel[1]}}) | (rv0_t1_i1_spare_q & {4{rv0_fx0_i1_sel[2]}}); + assign rv0_fx0_instr_i1_is_brick = (rv0_t0_i1_is_brick & rv0_fx0_i1_sel[0]) | (rv0_t1_i0_is_brick & rv0_fx0_i1_sel[1]) | (rv0_t1_i1_is_brick & rv0_fx0_i1_sel[2]); + assign rv0_fx0_instr_i1_brick = (rv0_t0_i1_brick & {3{rv0_fx0_i1_sel[0]}}) | (rv0_t1_i0_brick & {3{rv0_fx0_i1_sel[1]}}) | (rv0_t1_i1_brick & {3{rv0_fx0_i1_sel[2]}}); + + + + //------------------------------------------------------------------------------------------------------------ + // fx1 RV0 + //------------------------------------------------------------------------------------------------------------ + //------------------------------------------------------------------------------------------------------------ + // FX0 RVS -- Thread0 Thread1 -- + //------------------------------------------------------------------------------------------------------------ + // I0 I1 I0(0) I1(0) I0(1) I1(1) --- + // (-----, -----) <= ( 0, 0, 0, 0) + // (-----, I1(1)) <= ( 0, 0, 0, 1) + // (I0(1), -----) <= ( 0, 0, 1, 0) + // (I0(1), I1(1)) <= ( 0, 0, 1, 1) + // (-----, I1(0)) <= ( 0, 1, 0, 0) + // (I1(0), I1(1)) <= ( 0, 1, 0, 1) + // (I1(0), I0(1)) <= ( 0, 1, 1, 0) + // (I0(0), -----) <= ( 1, 0, 0, 0) + // (I0(0), I1(1)) <= ( 1, 0, 0, 1) + // (I0(0), I0(1)) <= ( 1, 0, 1, 0) + // (I0(0), I1(0)) <= ( 1, 1, 0, 0) + + //------------------------------------------------------------------------------------------------------------ + // -- Thread0 Thread1 -- + //------------------------------------------------------------------------------------------------------------ + // -- I0(0) I1(0) I0(1) I1(1) --- + // fx0_i0: x x x + // fx0_i1 x x x + + assign rv0_fx1_i0_sel[0] = rv0_t0_i0_rte_fx1_q; + assign rv0_fx1_i0_sel[1] = rv0_t0_i1_rte_fx1_q & (rv0_t1_i0_rte_fx1_q | rv0_t1_i1_rte_fx1_q); + assign rv0_fx1_i0_sel[2] = rv0_t1_i0_rte_fx1_q & (~rv0_t0_i0_rte_fx1_q) & (~rv0_t0_i1_rte_fx1_q); + assign rv0_fx1_i1_sel[0] = rv0_t0_i1_rte_fx1_q & (~rv0_t1_i0_rte_fx1_q) & (~rv0_t1_i1_rte_fx1_q); + assign rv0_fx1_i1_sel[1] = rv0_t1_i0_rte_fx1_q & (rv0_t0_i0_rte_fx1_q | rv0_t0_i1_rte_fx1_q); + assign rv0_fx1_i1_sel[2] = rv0_t1_i1_rte_fx1_q; + + assign rv0_fx1_instr_i0_vld = {((rv0_fx1_i0_sel[0] & rv0_t0_i0_vld_q) | (rv0_fx1_i0_sel[1] & rv0_t0_i1_vld_q)), (rv0_fx1_i0_sel[2] & rv0_t1_i0_vld_q)}; + assign rv0_fx1_instr_i1_vld = {(rv0_fx1_i1_sel[0] & rv0_t0_i1_vld_q), ((rv0_fx1_i1_sel[1] & rv0_t1_i0_vld_q) | (rv0_fx1_i1_sel[2] & rv0_t1_i1_vld_q))}; + + assign rv0_fx1_instr_i0_rte_fx1 = |(rv0_fx1_i0_sel); + + assign rv0_fx1_instr_i1_rte_fx1 = |(rv0_fx1_i1_sel); + + assign rv0_fx1_instr_i0_s1_dep_hit = (rv0_instr_i0_s1_dep_hit[0] & rv0_fx1_i0_sel[0]) | (rv0_instr_i1_s1_dep_hit_loc[0] & rv0_fx1_i0_sel[1]) | (rv0_instr_i0_s1_dep_hit[1] & rv0_fx1_i0_sel[2]); + assign rv0_fx1_instr_i0_s2_dep_hit = (rv0_instr_i0_s2_dep_hit[0] & rv0_fx1_i0_sel[0]) | (rv0_instr_i1_s2_dep_hit_loc[0] & rv0_fx1_i0_sel[1]) | (rv0_instr_i0_s2_dep_hit[1] & rv0_fx1_i0_sel[2]); + assign rv0_fx1_instr_i0_s3_dep_hit = (rv0_instr_i0_s3_dep_hit[0] & rv0_fx1_i0_sel[0]) | (rv0_instr_i1_s3_dep_hit_loc[0] & rv0_fx1_i0_sel[1]) | (rv0_instr_i0_s3_dep_hit[1] & rv0_fx1_i0_sel[2]); + + assign rv0_fx1_instr_i0_s1_itag = (rv0_t0_i0_s1_itag_q & {`ITAG_SIZE_ENC{rv0_fx1_i0_sel[0]}}) | (rv0_instr_i1_s1_itag_loc[0] & {`ITAG_SIZE_ENC{rv0_fx1_i0_sel[1]}}) | (rv0_t1_i0_s1_itag_q & {`ITAG_SIZE_ENC{rv0_fx1_i0_sel[2]}}); + assign rv0_fx1_instr_i0_s2_itag = (rv0_t0_i0_s2_itag_q & {`ITAG_SIZE_ENC{rv0_fx1_i0_sel[0]}}) | (rv0_instr_i1_s2_itag_loc[0] & {`ITAG_SIZE_ENC{rv0_fx1_i0_sel[1]}}) | (rv0_t1_i0_s2_itag_q & {`ITAG_SIZE_ENC{rv0_fx1_i0_sel[2]}}); + assign rv0_fx1_instr_i0_s3_itag = (rv0_t0_i0_s3_itag_q & {`ITAG_SIZE_ENC{rv0_fx1_i0_sel[0]}}) | (rv0_instr_i1_s3_itag_loc[0] & {`ITAG_SIZE_ENC{rv0_fx1_i0_sel[1]}}) | (rv0_t1_i0_s3_itag_q & {`ITAG_SIZE_ENC{rv0_fx1_i0_sel[2]}}); + + assign rv0_fx1_instr_i1_s1_dep_hit = (rv0_instr_i1_s1_dep_hit_loc[0] & rv0_fx1_i1_sel[0]) | (rv0_instr_i0_s1_dep_hit[1] & rv0_fx1_i1_sel[1]) | (rv0_instr_i1_s1_dep_hit_loc[1] & rv0_fx1_i1_sel[2]); + assign rv0_fx1_instr_i1_s2_dep_hit = (rv0_instr_i1_s2_dep_hit_loc[0] & rv0_fx1_i1_sel[0]) | (rv0_instr_i0_s2_dep_hit[1] & rv0_fx1_i1_sel[1]) | (rv0_instr_i1_s2_dep_hit_loc[1] & rv0_fx1_i1_sel[2]); + assign rv0_fx1_instr_i1_s3_dep_hit = (rv0_instr_i1_s3_dep_hit_loc[0] & rv0_fx1_i1_sel[0]) | (rv0_instr_i0_s3_dep_hit[1] & rv0_fx1_i1_sel[1]) | (rv0_instr_i1_s3_dep_hit_loc[1] & rv0_fx1_i1_sel[2]); + assign rv0_fx1_instr_i1_s1_itag = (rv0_instr_i1_s1_itag_loc[0] & {`ITAG_SIZE_ENC{rv0_fx1_i1_sel[0]}}) | (rv0_t1_i0_s1_itag_q & {`ITAG_SIZE_ENC{rv0_fx1_i1_sel[1]}}) | (rv0_instr_i1_s1_itag_loc[1] & {`ITAG_SIZE_ENC{rv0_fx1_i1_sel[2]}}); + assign rv0_fx1_instr_i1_s2_itag = (rv0_instr_i1_s2_itag_loc[0] & {`ITAG_SIZE_ENC{rv0_fx1_i1_sel[0]}}) | (rv0_t1_i0_s2_itag_q & {`ITAG_SIZE_ENC{rv0_fx1_i1_sel[1]}}) | (rv0_instr_i1_s2_itag_loc[1] & {`ITAG_SIZE_ENC{rv0_fx1_i1_sel[2]}}); + assign rv0_fx1_instr_i1_s3_itag = (rv0_instr_i1_s3_itag_loc[0] & {`ITAG_SIZE_ENC{rv0_fx1_i1_sel[0]}}) | (rv0_t1_i0_s3_itag_q & {`ITAG_SIZE_ENC{rv0_fx1_i1_sel[1]}}) | (rv0_instr_i1_s3_itag_loc[1] & {`ITAG_SIZE_ENC{rv0_fx1_i1_sel[2]}}); + + //------------------------------------------------------------------------------------------------------------ + // FX1 RV1 + //------------------------------------------------------------------------------------------------------------ + + assign rv0_fx1_instr_i0_instr = (rv0_t0_i0_instr_q & {32{rv0_fx1_i0_sel[0]}}) | (rv0_t0_i1_instr_q & {32{rv0_fx1_i0_sel[1]}}) | (rv0_t1_i0_instr_q & {32{rv0_fx1_i0_sel[2]}}); + assign rv0_fx1_instr_i0_ucode = (rv0_t0_i0_ucode_q & {3{rv0_fx1_i0_sel[0]}}) | (rv0_t0_i1_ucode_q & {3{rv0_fx1_i0_sel[1]}}) | (rv0_t1_i0_ucode_q & {3{rv0_fx1_i0_sel[2]}}); + assign rv0_fx1_instr_i0_itag = (rv0_t0_i0_itag_q & {`ITAG_SIZE_ENC{rv0_fx1_i0_sel[0]}}) | (rv0_t0_i1_itag_q & {`ITAG_SIZE_ENC{rv0_fx1_i0_sel[1]}}) | (rv0_t1_i0_itag_q & {`ITAG_SIZE_ENC{rv0_fx1_i0_sel[2]}}); + + assign rv0_fx1_instr_i0_t1_v = (rv0_t0_i0_t1_v_q & rv0_fx1_i0_sel[0]) | (rv0_t0_i1_t1_v_q & rv0_fx1_i0_sel[1]) | (rv0_t1_i0_t1_v_q & rv0_fx1_i0_sel[2]); + assign rv0_fx1_instr_i0_t1_p = (rv0_t0_i0_t1_p_q & {`GPR_POOL_ENC{rv0_fx1_i0_sel[0]}}) | (rv0_t0_i1_t1_p_q & {`GPR_POOL_ENC{rv0_fx1_i0_sel[1]}}) | (rv0_t1_i0_t1_p_q & {`GPR_POOL_ENC{rv0_fx1_i0_sel[2]}}); + assign rv0_fx1_instr_i0_t2_v = (rv0_t0_i0_t2_v_q & rv0_fx1_i0_sel[0]) | (rv0_t0_i1_t2_v_q & rv0_fx1_i0_sel[1]) | (rv0_t1_i0_t2_v_q & rv0_fx1_i0_sel[2]); + assign rv0_fx1_instr_i0_t2_p = (rv0_t0_i0_t2_p_q & {`GPR_POOL_ENC{rv0_fx1_i0_sel[0]}}) | (rv0_t0_i1_t2_p_q & {`GPR_POOL_ENC{rv0_fx1_i0_sel[1]}}) | (rv0_t1_i0_t2_p_q & {`GPR_POOL_ENC{rv0_fx1_i0_sel[2]}}); + assign rv0_fx1_instr_i0_t3_v = (rv0_t0_i0_t3_v_q & rv0_fx1_i0_sel[0]) | (rv0_t0_i1_t3_v_q & rv0_fx1_i0_sel[1]) | (rv0_t1_i0_t3_v_q & rv0_fx1_i0_sel[2]); + assign rv0_fx1_instr_i0_t3_p = (rv0_t0_i0_t3_p_q & {`GPR_POOL_ENC{rv0_fx1_i0_sel[0]}}) | (rv0_t0_i1_t3_p_q & {`GPR_POOL_ENC{rv0_fx1_i0_sel[1]}}) | (rv0_t1_i0_t3_p_q & {`GPR_POOL_ENC{rv0_fx1_i0_sel[2]}}); + + assign rv0_fx1_instr_i0_s1_v = (rv0_t0_i0_s1_v_q & rv0_fx1_i0_sel[0]) | (rv0_t0_i1_s1_v_q & rv0_fx1_i0_sel[1]) | (rv0_t1_i0_s1_v_q & rv0_fx1_i0_sel[2]); + assign rv0_fx1_instr_i0_s1_p = (rv0_t0_i0_s1_p_q & {`GPR_POOL_ENC{rv0_fx1_i0_sel[0]}}) | (rv0_t0_i1_s1_p_q & {`GPR_POOL_ENC{rv0_fx1_i0_sel[1]}}) | (rv0_t1_i0_s1_p_q & {`GPR_POOL_ENC{rv0_fx1_i0_sel[2]}}); + assign rv0_fx1_instr_i0_s1_t = (rv0_t0_i0_s1_t_q & {3{rv0_fx1_i0_sel[0]}}) | (rv0_t0_i1_s1_t_q & {3{rv0_fx1_i0_sel[1]}}) | (rv0_t1_i0_s1_t_q & {3{rv0_fx1_i0_sel[2]}}); + assign rv0_fx1_instr_i0_s2_v = (rv0_t0_i0_s2_v_q & rv0_fx1_i0_sel[0]) | (rv0_t0_i1_s2_v_q & rv0_fx1_i0_sel[1]) | (rv0_t1_i0_s2_v_q & rv0_fx1_i0_sel[2]); + assign rv0_fx1_instr_i0_s2_p = (rv0_t0_i0_s2_p_q & {`GPR_POOL_ENC{rv0_fx1_i0_sel[0]}}) | (rv0_t0_i1_s2_p_q & {`GPR_POOL_ENC{rv0_fx1_i0_sel[1]}}) | (rv0_t1_i0_s2_p_q & {`GPR_POOL_ENC{rv0_fx1_i0_sel[2]}}); + assign rv0_fx1_instr_i0_s2_t = (rv0_t0_i0_s2_t_q & {3{rv0_fx1_i0_sel[0]}}) | (rv0_t0_i1_s2_t_q & {3{rv0_fx1_i0_sel[1]}}) | (rv0_t1_i0_s2_t_q & {3{rv0_fx1_i0_sel[2]}}); + assign rv0_fx1_instr_i0_s3_v = (rv0_t0_i0_s3_v_q & rv0_fx1_i0_sel[0]) | (rv0_t0_i1_s3_v_q & rv0_fx1_i0_sel[1]) | (rv0_t1_i0_s3_v_q & rv0_fx1_i0_sel[2]); + assign rv0_fx1_instr_i0_s3_p = (rv0_t0_i0_s3_p_q & {`GPR_POOL_ENC{rv0_fx1_i0_sel[0]}}) | (rv0_t0_i1_s3_p_q & {`GPR_POOL_ENC{rv0_fx1_i0_sel[1]}}) | (rv0_t1_i0_s3_p_q & {`GPR_POOL_ENC{rv0_fx1_i0_sel[2]}}); + assign rv0_fx1_instr_i0_s3_t = (rv0_t0_i0_s3_t_q & {3{rv0_fx1_i0_sel[0]}}) | (rv0_t0_i1_s3_t_q & {3{rv0_fx1_i0_sel[1]}}) | (rv0_t1_i0_s3_t_q & {3{rv0_fx1_i0_sel[2]}}); + + assign rv0_fx1_instr_i0_ilat = (rv0_t0_i0_ilat & {4{rv0_fx1_i0_sel[0]}}) | (rv0_t0_i1_ilat & {4{rv0_fx1_i0_sel[1]}}) | (rv0_t1_i0_ilat & {4{rv0_fx1_i0_sel[2]}}); + assign rv0_fx1_instr_i0_isStore = (rv0_t0_i0_isStore_q & rv0_fx1_i0_sel[0]) | (rv0_t0_i1_isStore_q & rv0_fx1_i0_sel[1]) | (rv0_t1_i0_isStore_q & rv0_fx1_i0_sel[2]); + assign rv0_fx1_instr_i0_spare = (rv0_t0_i0_spare_q & {4{rv0_fx1_i0_sel[0]}}) | (rv0_t0_i1_spare_q & {4{rv0_fx1_i0_sel[1]}}) | (rv0_t1_i0_spare_q & {4{rv0_fx1_i0_sel[2]}}); + assign rv0_fx1_instr_i0_is_brick = (rv0_t0_i0_is_brick & rv0_fx1_i0_sel[0]) | (rv0_t0_i1_is_brick & rv0_fx1_i0_sel[1]) | (rv0_t1_i0_is_brick & rv0_fx1_i0_sel[2]); + assign rv0_fx1_instr_i0_brick = (rv0_t0_i0_brick & {3{rv0_fx1_i0_sel[0]}}) | (rv0_t0_i1_brick & {3{rv0_fx1_i0_sel[1]}}) | (rv0_t1_i0_brick & {3{rv0_fx1_i0_sel[2]}}); + + + assign rv0_fx1_instr_i1_instr = (rv0_t0_i1_instr_q & {32{rv0_fx1_i1_sel[0]}}) | (rv0_t1_i0_instr_q & {32{rv0_fx1_i1_sel[1]}}) | (rv0_t1_i1_instr_q & {32{rv0_fx1_i1_sel[2]}}); + assign rv0_fx1_instr_i1_ucode = (rv0_t0_i1_ucode_q & {3{rv0_fx1_i1_sel[0]}}) | (rv0_t1_i0_ucode_q & {3{rv0_fx1_i1_sel[1]}}) | (rv0_t1_i1_ucode_q & {3{rv0_fx1_i1_sel[2]}}); + assign rv0_fx1_instr_i1_itag = (rv0_t0_i1_itag_q & {`ITAG_SIZE_ENC{rv0_fx1_i1_sel[0]}}) | (rv0_t1_i0_itag_q & {`ITAG_SIZE_ENC{rv0_fx1_i1_sel[1]}}) | (rv0_t1_i1_itag_q & {`ITAG_SIZE_ENC{rv0_fx1_i1_sel[2]}}); + + assign rv0_fx1_instr_i1_t1_v = (rv0_t0_i1_t1_v_q & rv0_fx1_i1_sel[0]) | (rv0_t1_i0_t1_v_q & rv0_fx1_i1_sel[1]) | (rv0_t1_i1_t1_v_q & rv0_fx1_i1_sel[2]); + assign rv0_fx1_instr_i1_t1_p = (rv0_t0_i1_t1_p_q & {`GPR_POOL_ENC{rv0_fx1_i1_sel[0]}}) | (rv0_t1_i0_t1_p_q & {`GPR_POOL_ENC{rv0_fx1_i1_sel[1]}}) | (rv0_t1_i1_t1_p_q & {`GPR_POOL_ENC{rv0_fx1_i1_sel[2]}}); + assign rv0_fx1_instr_i1_t2_v = (rv0_t0_i1_t2_v_q & rv0_fx1_i1_sel[0]) | (rv0_t1_i0_t2_v_q & rv0_fx1_i1_sel[1]) | (rv0_t1_i1_t2_v_q & rv0_fx1_i1_sel[2]); + assign rv0_fx1_instr_i1_t2_p = (rv0_t0_i1_t2_p_q & {`GPR_POOL_ENC{rv0_fx1_i1_sel[0]}}) | (rv0_t1_i0_t2_p_q & {`GPR_POOL_ENC{rv0_fx1_i1_sel[1]}}) | (rv0_t1_i1_t2_p_q & {`GPR_POOL_ENC{rv0_fx1_i1_sel[2]}}); + assign rv0_fx1_instr_i1_t3_v = (rv0_t0_i1_t3_v_q & rv0_fx1_i1_sel[0]) | (rv0_t1_i0_t3_v_q & rv0_fx1_i1_sel[1]) | (rv0_t1_i1_t3_v_q & rv0_fx1_i1_sel[2]); + assign rv0_fx1_instr_i1_t3_p = (rv0_t0_i1_t3_p_q & {`GPR_POOL_ENC{rv0_fx1_i1_sel[0]}}) | (rv0_t1_i0_t3_p_q & {`GPR_POOL_ENC{rv0_fx1_i1_sel[1]}}) | (rv0_t1_i1_t3_p_q & {`GPR_POOL_ENC{rv0_fx1_i1_sel[2]}}); + + assign rv0_fx1_instr_i1_s1_v = (rv0_t0_i1_s1_v_q & rv0_fx1_i1_sel[0]) | (rv0_t1_i0_s1_v_q & rv0_fx1_i1_sel[1]) | (rv0_t1_i1_s1_v_q & rv0_fx1_i1_sel[2]); + assign rv0_fx1_instr_i1_s1_p = (rv0_t0_i1_s1_p_q & {`GPR_POOL_ENC{rv0_fx1_i1_sel[0]}}) | (rv0_t1_i0_s1_p_q & {`GPR_POOL_ENC{rv0_fx1_i1_sel[1]}}) | (rv0_t1_i1_s1_p_q & {`GPR_POOL_ENC{rv0_fx1_i1_sel[2]}}); + assign rv0_fx1_instr_i1_s1_t = (rv0_t0_i1_s1_t_q & {3{rv0_fx1_i1_sel[0]}}) | (rv0_t1_i0_s1_t_q & {3{rv0_fx1_i1_sel[1]}}) | (rv0_t1_i1_s1_t_q & {3{rv0_fx1_i1_sel[2]}}); + assign rv0_fx1_instr_i1_s2_v = (rv0_t0_i1_s2_v_q & rv0_fx1_i1_sel[0]) | (rv0_t1_i0_s2_v_q & rv0_fx1_i1_sel[1]) | (rv0_t1_i1_s2_v_q & rv0_fx1_i1_sel[2]); + assign rv0_fx1_instr_i1_s2_p = (rv0_t0_i1_s2_p_q & {`GPR_POOL_ENC{rv0_fx1_i1_sel[0]}}) | (rv0_t1_i0_s2_p_q & {`GPR_POOL_ENC{rv0_fx1_i1_sel[1]}}) | (rv0_t1_i1_s2_p_q & {`GPR_POOL_ENC{rv0_fx1_i1_sel[2]}}); + assign rv0_fx1_instr_i1_s2_t = (rv0_t0_i1_s2_t_q & {3{rv0_fx1_i1_sel[0]}}) | (rv0_t1_i0_s2_t_q & {3{rv0_fx1_i1_sel[1]}}) | (rv0_t1_i1_s2_t_q & {3{rv0_fx1_i1_sel[2]}}); + assign rv0_fx1_instr_i1_s3_v = (rv0_t0_i1_s3_v_q & rv0_fx1_i1_sel[0]) | (rv0_t1_i0_s3_v_q & rv0_fx1_i1_sel[1]) | (rv0_t1_i1_s3_v_q & rv0_fx1_i1_sel[2]); + assign rv0_fx1_instr_i1_s3_p = (rv0_t0_i1_s3_p_q & {`GPR_POOL_ENC{rv0_fx1_i1_sel[0]}}) | (rv0_t1_i0_s3_p_q & {`GPR_POOL_ENC{rv0_fx1_i1_sel[1]}}) | (rv0_t1_i1_s3_p_q & {`GPR_POOL_ENC{rv0_fx1_i1_sel[2]}}); + assign rv0_fx1_instr_i1_s3_t = (rv0_t0_i1_s3_t_q & {3{rv0_fx1_i1_sel[0]}}) | (rv0_t1_i0_s3_t_q & {3{rv0_fx1_i1_sel[1]}}) | (rv0_t1_i1_s3_t_q & {3{rv0_fx1_i1_sel[2]}}); + + assign rv0_fx1_instr_i1_ilat = (rv0_t0_i1_ilat & {4{rv0_fx1_i1_sel[0]}}) | (rv0_t1_i0_ilat & {4{rv0_fx1_i1_sel[1]}}) | (rv0_t1_i1_ilat & {4{rv0_fx1_i1_sel[2]}}); + assign rv0_fx1_instr_i1_isStore = (rv0_t0_i1_isStore_q & rv0_fx1_i1_sel[0]) | (rv0_t1_i0_isStore_q & rv0_fx1_i1_sel[1]) | (rv0_t1_i1_isStore_q & rv0_fx1_i1_sel[2]); + assign rv0_fx1_instr_i1_spare = (rv0_t0_i1_spare_q & {4{rv0_fx1_i1_sel[0]}}) | (rv0_t1_i0_spare_q & {4{rv0_fx1_i1_sel[1]}}) | (rv0_t1_i1_spare_q & {4{rv0_fx1_i1_sel[2]}}); + assign rv0_fx1_instr_i1_is_brick = (rv0_t0_i1_is_brick & rv0_fx1_i1_sel[0]) | (rv0_t1_i0_is_brick & rv0_fx1_i1_sel[1]) | (rv0_t1_i1_is_brick & rv0_fx1_i1_sel[2]); + assign rv0_fx1_instr_i1_brick = (rv0_t0_i1_brick & {3{rv0_fx1_i1_sel[0]}}) | (rv0_t1_i0_brick & {3{rv0_fx1_i1_sel[1]}}) | (rv0_t1_i1_brick & {3{rv0_fx1_i1_sel[2]}}); + + + + + + //------------------------------------------------------------------------------------------------------------ + // lq RV0 + //------------------------------------------------------------------------------------------------------------ + + + assign rv0_lq_i0_sel[0] = rv0_t0_i0_rte_lq_q; + assign rv0_lq_i0_sel[1] = rv0_t0_i1_rte_lq_q & (rv0_t1_i0_rte_lq_q | rv0_t1_i1_rte_lq_q); + assign rv0_lq_i0_sel[2] = rv0_t1_i0_rte_lq_q & (~rv0_t0_i0_rte_lq_q) & (~rv0_t0_i1_rte_lq_q); + assign rv0_lq_i1_sel[0] = rv0_t0_i1_rte_lq_q & (~rv0_t1_i0_rte_lq_q) & (~rv0_t1_i1_rte_lq_q); + assign rv0_lq_i1_sel[1] = rv0_t1_i0_rte_lq_q & (rv0_t0_i0_rte_lq_q | rv0_t0_i1_rte_lq_q); + assign rv0_lq_i1_sel[2] = rv0_t1_i1_rte_lq_q; + + assign rv1_lq_instr_i0_vld_d = {((rv0_lq_i0_sel[0] & rv0_t0_i0_vld_q) | (rv0_lq_i0_sel[1] & rv0_t0_i1_vld_q)), (rv0_lq_i0_sel[2] & rv0_t1_i0_vld_q)}; + assign rv1_lq_instr_i1_vld_d = {(rv0_lq_i1_sel[0] & rv0_t0_i1_vld_q), ((rv0_lq_i1_sel[1] & rv0_t1_i0_vld_q) | (rv0_lq_i1_sel[2] & rv0_t1_i1_vld_q))}; + + assign rv0_lq_instr_i0_vld = rv1_lq_instr_i0_vld_d; + assign rv0_lq_instr_i1_vld = rv1_lq_instr_i1_vld_d; + + assign rv1_lq_instr_i0_rte_lq_d = |(rv0_lq_i0_sel); + assign rv1_lq_instr_i1_rte_lq_d = |(rv0_lq_i1_sel); + + assign rv0_lq_instr_i0_rte_lq = rv1_lq_instr_i0_rte_lq_d; + assign rv0_lq_instr_i1_rte_lq = rv1_lq_instr_i1_rte_lq_d; + + assign rv1_lq_instr_i0_rte_sq_d = (rv0_t0_i0_rte_sq_q & rv0_lq_i0_sel[0]) | (rv0_t0_i1_rte_sq_q & rv0_lq_i0_sel[1]) | (rv0_t1_i0_rte_sq_q & rv0_lq_i0_sel[2]); + assign rv1_lq_instr_i1_rte_sq_d = (rv0_t0_i1_rte_sq_q & rv0_lq_i1_sel[0]) | (rv0_t1_i0_rte_sq_q & rv0_lq_i1_sel[1]) | (rv0_t1_i1_rte_sq_q & rv0_lq_i1_sel[2]); + + assign rv0_lq_instr_i0_s1_dep_hit = (rv0_instr_i0_s1_dep_hit[0] & rv0_lq_i0_sel[0]) | (rv0_instr_i1_s1_dep_hit_loc[0] & rv0_lq_i0_sel[1]) | (rv0_instr_i0_s1_dep_hit[1] & rv0_lq_i0_sel[2]); + assign rv0_lq_instr_i0_s2_dep_hit = (rv0_instr_i0_s2_dep_hit[0] & rv0_lq_i0_sel[0]) | (rv0_instr_i1_s2_dep_hit_loc[0] & rv0_lq_i0_sel[1]) | (rv0_instr_i0_s2_dep_hit[1] & rv0_lq_i0_sel[2]); + + assign rv0_lq_instr_i0_s1_itag = (rv0_t0_i0_s1_itag_q & {`ITAG_SIZE_ENC{rv0_lq_i0_sel[0]}}) | (rv0_instr_i1_s1_itag_loc[0] & {`ITAG_SIZE_ENC{rv0_lq_i0_sel[1]}}) | (rv0_t1_i0_s1_itag_q & {`ITAG_SIZE_ENC{rv0_lq_i0_sel[2]}}); + assign rv0_lq_instr_i0_s2_itag = (rv0_t0_i0_s2_itag_q & {`ITAG_SIZE_ENC{rv0_lq_i0_sel[0]}}) | (rv0_instr_i1_s2_itag_loc[0] & {`ITAG_SIZE_ENC{rv0_lq_i0_sel[1]}}) | (rv0_t1_i0_s2_itag_q & {`ITAG_SIZE_ENC{rv0_lq_i0_sel[2]}}); + + assign rv0_lq_instr_i1_s1_dep_hit = (rv0_instr_i1_s1_dep_hit_loc[0] & rv0_lq_i1_sel[0]) | (rv0_instr_i0_s1_dep_hit[1] & rv0_lq_i1_sel[1]) | (rv0_instr_i1_s1_dep_hit_loc[1] & rv0_lq_i1_sel[2]); + assign rv0_lq_instr_i1_s2_dep_hit = (rv0_instr_i1_s2_dep_hit_loc[0] & rv0_lq_i1_sel[0]) | (rv0_instr_i0_s2_dep_hit[1] & rv0_lq_i1_sel[1]) | (rv0_instr_i1_s2_dep_hit_loc[1] & rv0_lq_i1_sel[2]); + assign rv0_lq_instr_i1_s1_itag = (rv0_instr_i1_s1_itag_loc[0] & {`ITAG_SIZE_ENC{rv0_lq_i1_sel[0]}}) | (rv0_t1_i0_s1_itag_q & {`ITAG_SIZE_ENC{rv0_lq_i1_sel[1]}}) | (rv0_instr_i1_s1_itag_loc[1] & {`ITAG_SIZE_ENC{rv0_lq_i1_sel[2]}}); + assign rv0_lq_instr_i1_s2_itag = (rv0_instr_i1_s2_itag_loc[0] & {`ITAG_SIZE_ENC{rv0_lq_i1_sel[0]}}) | (rv0_t1_i0_s2_itag_q & {`ITAG_SIZE_ENC{rv0_lq_i1_sel[1]}}) | (rv0_instr_i1_s2_itag_loc[1] & {`ITAG_SIZE_ENC{rv0_lq_i1_sel[2]}}); + + //------------------------------------------------------------------------------------------------------------ + // lq RV1 + //------------------------------------------------------------------------------------------------------------ + + + assign rv0_lq_instr_i0_instr = (rv0_t0_i0_instr_q & {32{rv0_lq_i0_sel[0]}}) | (rv0_t0_i1_instr_q & {32{rv0_lq_i0_sel[1]}}) | (rv0_t1_i0_instr_q & {32{rv0_lq_i0_sel[2]}}); + assign rv0_lq_instr_i0_ifar = (rv0_t0_i0_ifar_q[61 - `PF_IAR_BITS + 1:61] & {`PF_IAR_BITS{rv0_lq_i0_sel[0]}}) | (rv0_t0_i1_ifar_q[61 - `PF_IAR_BITS + 1:61] & {`PF_IAR_BITS{rv0_lq_i0_sel[1]}}) | (rv0_t1_i0_ifar_q[61 - `PF_IAR_BITS + 1:61] & {`PF_IAR_BITS{rv0_lq_i0_sel[2]}}); + assign rv1_lq_instr_i0_ucode_d = (rv0_t0_i0_ucode_q & {3{rv0_lq_i0_sel[0]}}) | (rv0_t0_i1_ucode_q & {3{rv0_lq_i0_sel[1]}}) | (rv0_t1_i0_ucode_q & {3{rv0_lq_i0_sel[2]}}); + assign rv1_lq_instr_i0_2ucode_d = (rv0_t0_i0_2ucode_q & rv0_lq_i0_sel[0]) | (rv0_t1_i0_2ucode_q & rv0_lq_i0_sel[2]); // No i1_2ucode + assign rv1_lq_instr_i0_ucode_cnt_d = (rv0_t0_i0_ucode_cnt_q & {`UCODE_ENTRIES_ENC{rv0_lq_i0_sel[0]}}) | (rv0_t0_i1_ucode_cnt_q & {`UCODE_ENTRIES_ENC{rv0_lq_i0_sel[1]}}) | (rv0_t1_i0_ucode_cnt_q & {`UCODE_ENTRIES_ENC{rv0_lq_i0_sel[2]}}); + assign rv1_lq_instr_i0_itag_d = (rv0_t0_i0_itag_q & {`ITAG_SIZE_ENC{rv0_lq_i0_sel[0]}}) | (rv0_t0_i1_itag_q & {`ITAG_SIZE_ENC{rv0_lq_i0_sel[1]}}) | (rv0_t1_i0_itag_q & {`ITAG_SIZE_ENC{rv0_lq_i0_sel[2]}}); + assign rv0_lq_instr_i0_ord = (rv0_t0_i0_ord_q & rv0_lq_i0_sel[0]) | ( rv0_t0_i1_ord_q & rv0_lq_i0_sel[1]) | (rv0_t1_i0_ord_q & rv0_lq_i0_sel[2]); + assign rv0_lq_instr_i0_cord = (rv0_t0_i0_cord_q & rv0_lq_i0_sel[0]) | (rv0_t0_i1_cord_q & rv0_lq_i0_sel[1]) | (rv0_t1_i0_cord_q & rv0_lq_i0_sel[2]); + assign rv0_lq_instr_i0_spec = (rv0_t0_i0_spec_q & rv0_lq_i0_sel[0]) | (rv0_t0_i1_spec_q & rv0_lq_i0_sel[1]) | (rv0_t1_i0_spec_q & rv0_lq_i0_sel[2]); + + assign rv0_lq_instr_i0_t1_v = (rv0_t0_i0_t1_v_q & rv0_lq_i0_sel[0]) | (rv0_t0_i1_t1_v_q & rv0_lq_i0_sel[1]) | (rv0_t1_i0_t1_v_q & rv0_lq_i0_sel[2]); + assign rv0_lq_instr_i0_t1_p = (rv0_t0_i0_t1_p_q & {`GPR_POOL_ENC{rv0_lq_i0_sel[0]}}) | (rv0_t0_i1_t1_p_q & {`GPR_POOL_ENC{rv0_lq_i0_sel[1]}}) | (rv0_t1_i0_t1_p_q & {`GPR_POOL_ENC{rv0_lq_i0_sel[2]}}); + assign rv0_lq_instr_i0_t2_v = (rv0_t0_i0_t2_v_q & rv0_lq_i0_sel[0]) | (rv0_t0_i1_t2_v_q & rv0_lq_i0_sel[1]) | (rv0_t1_i0_t2_v_q & rv0_lq_i0_sel[2]); + assign rv0_lq_instr_i0_t2_p = (rv0_t0_i0_t2_p_q & {`GPR_POOL_ENC{rv0_lq_i0_sel[0]}}) | (rv0_t0_i1_t2_p_q & {`GPR_POOL_ENC{rv0_lq_i0_sel[1]}}) | (rv0_t1_i0_t2_p_q & {`GPR_POOL_ENC{rv0_lq_i0_sel[2]}}); + assign rv0_lq_instr_i0_t2_t = (rv0_t0_i0_t2_t_q & {3{rv0_lq_i0_sel[0]}}) | (rv0_t0_i1_t2_t_q & {3{rv0_lq_i0_sel[1]}}) | (rv0_t1_i0_t2_t_q & {3{rv0_lq_i0_sel[2]}}); + assign rv0_lq_instr_i0_t3_v = (rv0_t0_i0_t3_v_q & rv0_lq_i0_sel[0]) | (rv0_t0_i1_t3_v_q & rv0_lq_i0_sel[1]) | (rv0_t1_i0_t3_v_q & rv0_lq_i0_sel[2]); + assign rv0_lq_instr_i0_t3_p = (rv0_t0_i0_t3_p_q & {`GPR_POOL_ENC{rv0_lq_i0_sel[0]}}) | (rv0_t0_i1_t3_p_q & {`GPR_POOL_ENC{rv0_lq_i0_sel[1]}}) | (rv0_t1_i0_t3_p_q & {`GPR_POOL_ENC{rv0_lq_i0_sel[2]}}); + assign rv0_lq_instr_i0_t3_t = (rv0_t0_i0_t3_t_q & {3{rv0_lq_i0_sel[0]}}) | (rv0_t0_i1_t3_t_q & {3{rv0_lq_i0_sel[1]}}) | (rv0_t1_i0_t3_t_q & {3{rv0_lq_i0_sel[2]}}); + + assign rv0_lq_instr_i0_s1_v = (rv0_t0_i0_s1_v_q & rv0_lq_i0_sel[0]) | (rv0_t0_i1_s1_v_q & rv0_lq_i0_sel[1]) | (rv0_t1_i0_s1_v_q & rv0_lq_i0_sel[2]); + assign rv0_lq_instr_i0_s1_p = (rv0_t0_i0_s1_p_q & {`GPR_POOL_ENC{rv0_lq_i0_sel[0]}}) | (rv0_t0_i1_s1_p_q & {`GPR_POOL_ENC{rv0_lq_i0_sel[1]}}) | (rv0_t1_i0_s1_p_q & {`GPR_POOL_ENC{rv0_lq_i0_sel[2]}}); + assign rv0_lq_instr_i0_s1_t = (rv0_t0_i0_s1_t_q & {3{rv0_lq_i0_sel[0]}}) | (rv0_t0_i1_s1_t_q & {3{rv0_lq_i0_sel[1]}}) | (rv0_t1_i0_s1_t_q & {3{rv0_lq_i0_sel[2]}}); + assign rv0_lq_instr_i0_s2_v = (rv0_t0_i0_s2_v_q & rv0_lq_i0_sel[0]) | (rv0_t0_i1_s2_v_q & rv0_lq_i0_sel[1]) | (rv0_t1_i0_s2_v_q & rv0_lq_i0_sel[2]); + assign rv0_lq_instr_i0_s2_p = (rv0_t0_i0_s2_p_q & {`GPR_POOL_ENC{rv0_lq_i0_sel[0]}}) | (rv0_t0_i1_s2_p_q & {`GPR_POOL_ENC{rv0_lq_i0_sel[1]}}) | (rv0_t1_i0_s2_p_q & {`GPR_POOL_ENC{rv0_lq_i0_sel[2]}}); + assign rv0_lq_instr_i0_s2_t = (rv0_t0_i0_s2_t_q & {3{rv0_lq_i0_sel[0]}}) | (rv0_t0_i1_s2_t_q & {3{rv0_lq_i0_sel[1]}}) | (rv0_t1_i0_s2_t_q & {3{rv0_lq_i0_sel[2]}}); + assign rv1_lq_instr_i0_s3_t_d = (rv0_t0_i0_s3_t_q & {3{rv0_lq_i0_sel[0]}}) | (rv0_t0_i1_s3_t_q & {3{rv0_lq_i0_sel[1]}}) | (rv0_t1_i0_s3_t_q & {3{rv0_lq_i0_sel[2]}}); + + assign rv1_lq_instr_i0_isLoad_d = (rv0_t0_i0_isLoad_q & rv0_lq_i0_sel[0]) | (rv0_t0_i1_isLoad_q & rv0_lq_i0_sel[1]) | (rv0_t1_i0_isLoad_q & rv0_lq_i0_sel[2]); + assign rv1_lq_instr_i0_isStore_d = (rv0_t0_i0_isStore_q & rv0_lq_i0_sel[0]) | (rv0_t0_i1_isStore_q & rv0_lq_i0_sel[1]) | (rv0_t1_i0_isStore_q & rv0_lq_i0_sel[2]); + assign rv0_lq_instr_i0_spare = (rv0_t0_i0_spare_q & {4{rv0_lq_i0_sel[0]}}) | (rv0_t0_i1_spare_q & {4{rv0_lq_i0_sel[1]}}) | (rv0_t1_i0_spare_q & {4{rv0_lq_i0_sel[2]}}); + assign rv0_lq_instr_i0_is_brick = (rv0_t0_i0_is_brick & rv0_lq_i0_sel[0]) | (rv0_t0_i1_is_brick & rv0_lq_i0_sel[1]) | (rv0_t1_i0_is_brick & rv0_lq_i0_sel[2]); + assign rv0_lq_instr_i0_brick = (rv0_t0_i0_brick & {3{rv0_lq_i0_sel[0]}}) | (rv0_t0_i1_brick & {3{rv0_lq_i0_sel[1]}}) | (rv0_t1_i0_brick & {3{rv0_lq_i0_sel[2]}}); + + + assign rv0_lq_instr_i1_instr = (rv0_t0_i1_instr_q & {32{rv0_lq_i1_sel[0]}}) | (rv0_t1_i0_instr_q & {32{rv0_lq_i1_sel[1]}}) | (rv0_t1_i1_instr_q & {32{rv0_lq_i1_sel[2]}}); + assign rv0_lq_instr_i1_ifar = (rv0_t0_i1_ifar_q[61 - `PF_IAR_BITS + 1:61] & {`PF_IAR_BITS{rv0_lq_i1_sel[0]}}) | (rv0_t1_i0_ifar_q[61 - `PF_IAR_BITS + 1:61] & {`PF_IAR_BITS{rv0_lq_i1_sel[1]}}) | (rv0_t1_i1_ifar_q[61 - `PF_IAR_BITS + 1:61] & {`PF_IAR_BITS{rv0_lq_i1_sel[2]}}); + assign rv1_lq_instr_i1_ucode_d = (rv0_t0_i1_ucode_q & {3{rv0_lq_i1_sel[0]}}) | (rv0_t1_i0_ucode_q & {3{rv0_lq_i1_sel[1]}}) | (rv0_t1_i1_ucode_q & {3{rv0_lq_i1_sel[2]}}); + assign rv1_lq_instr_i1_2ucode_d = (rv0_t1_i0_2ucode_q & rv0_lq_i1_sel[1]) ; + assign rv1_lq_instr_i1_ucode_cnt_d = (rv0_t0_i1_ucode_cnt_q & {`UCODE_ENTRIES_ENC{rv0_lq_i1_sel[0]}}) | (rv0_t1_i0_ucode_cnt_q & {`UCODE_ENTRIES_ENC{rv0_lq_i1_sel[1]}}) | (rv0_t1_i1_ucode_cnt_q & {`UCODE_ENTRIES_ENC{rv0_lq_i1_sel[2]}}); + assign rv1_lq_instr_i1_itag_d = (rv0_t0_i1_itag_q & {`ITAG_SIZE_ENC{rv0_lq_i1_sel[0]}}) | (rv0_t1_i0_itag_q & {`ITAG_SIZE_ENC{rv0_lq_i1_sel[1]}}) | (rv0_t1_i1_itag_q & {`ITAG_SIZE_ENC{rv0_lq_i1_sel[2]}}); + assign rv0_lq_instr_i1_ord = (rv0_t0_i1_ord_q & rv0_lq_i1_sel[0]) | ( rv0_t1_i0_ord_q & rv0_lq_i1_sel[1]) | (rv0_t1_i1_ord_q & rv0_lq_i1_sel[2]); + assign rv0_lq_instr_i1_cord = (rv0_t0_i1_cord_q & rv0_lq_i1_sel[0]) | (rv0_t1_i0_cord_q & rv0_lq_i1_sel[1]) | (rv0_t1_i1_cord_q & rv0_lq_i1_sel[2]); + assign rv0_lq_instr_i1_spec = (rv0_t0_i1_spec_q & rv0_lq_i1_sel[0]) | (rv0_t1_i0_spec_q & rv0_lq_i1_sel[1]) | (rv0_t1_i1_spec_q & rv0_lq_i1_sel[2]); + + assign rv0_lq_instr_i1_t1_v = (rv0_t0_i1_t1_v_q & rv0_lq_i1_sel[0]) | (rv0_t1_i0_t1_v_q & rv0_lq_i1_sel[1]) | (rv0_t1_i1_t1_v_q & rv0_lq_i1_sel[2]); + assign rv0_lq_instr_i1_t1_p = (rv0_t0_i1_t1_p_q & {`GPR_POOL_ENC{rv0_lq_i1_sel[0]}}) | (rv0_t1_i0_t1_p_q & {`GPR_POOL_ENC{rv0_lq_i1_sel[1]}}) | (rv0_t1_i1_t1_p_q & {`GPR_POOL_ENC{rv0_lq_i1_sel[2]}}); + assign rv0_lq_instr_i1_t2_v = (rv0_t0_i1_t2_v_q & rv0_lq_i1_sel[0]) | (rv0_t1_i0_t2_v_q & rv0_lq_i1_sel[1]) | (rv0_t1_i1_t2_v_q & rv0_lq_i1_sel[2]); + assign rv0_lq_instr_i1_t2_p = (rv0_t0_i1_t2_p_q & {`GPR_POOL_ENC{rv0_lq_i1_sel[0]}}) | (rv0_t1_i0_t2_p_q & {`GPR_POOL_ENC{rv0_lq_i1_sel[1]}}) | (rv0_t1_i1_t2_p_q & {`GPR_POOL_ENC{rv0_lq_i1_sel[2]}}); + assign rv0_lq_instr_i1_t2_t = (rv0_t0_i1_t2_t_q & {3{rv0_lq_i1_sel[0]}}) | (rv0_t1_i0_t2_t_q & {3{rv0_lq_i1_sel[1]}}) | (rv0_t1_i1_t2_t_q & {3{rv0_lq_i1_sel[2]}}); + assign rv0_lq_instr_i1_t3_v = (rv0_t0_i1_t3_v_q & rv0_lq_i1_sel[0]) | (rv0_t1_i0_t3_v_q & rv0_lq_i1_sel[1]) | (rv0_t1_i1_t3_v_q & rv0_lq_i1_sel[2]); + assign rv0_lq_instr_i1_t3_p = (rv0_t0_i1_t3_p_q & {`GPR_POOL_ENC{rv0_lq_i1_sel[0]}}) | (rv0_t1_i0_t3_p_q & {`GPR_POOL_ENC{rv0_lq_i1_sel[1]}}) | (rv0_t1_i1_t3_p_q & {`GPR_POOL_ENC{rv0_lq_i1_sel[2]}}); + assign rv0_lq_instr_i1_t3_t = (rv0_t0_i1_t3_t_q & {3{rv0_lq_i1_sel[0]}}) | (rv0_t1_i0_t3_t_q & {3{rv0_lq_i1_sel[1]}}) | (rv0_t1_i1_t3_t_q & {3{rv0_lq_i1_sel[2]}}); + + assign rv0_lq_instr_i1_s1_v = (rv0_t0_i1_s1_v_q & rv0_lq_i1_sel[0]) | (rv0_t1_i0_s1_v_q & rv0_lq_i1_sel[1]) | (rv0_t1_i1_s1_v_q & rv0_lq_i1_sel[2]); + assign rv0_lq_instr_i1_s1_p = (rv0_t0_i1_s1_p_q & {`GPR_POOL_ENC{rv0_lq_i1_sel[0]}}) | (rv0_t1_i0_s1_p_q & {`GPR_POOL_ENC{rv0_lq_i1_sel[1]}}) | (rv0_t1_i1_s1_p_q & {`GPR_POOL_ENC{rv0_lq_i1_sel[2]}}); + assign rv0_lq_instr_i1_s1_t = (rv0_t0_i1_s1_t_q & {3{rv0_lq_i1_sel[0]}}) | (rv0_t1_i0_s1_t_q & {3{rv0_lq_i1_sel[1]}}) | (rv0_t1_i1_s1_t_q & {3{rv0_lq_i1_sel[2]}}); + assign rv0_lq_instr_i1_s2_v = (rv0_t0_i1_s2_v_q & rv0_lq_i1_sel[0]) | (rv0_t1_i0_s2_v_q & rv0_lq_i1_sel[1]) | (rv0_t1_i1_s2_v_q & rv0_lq_i1_sel[2]); + assign rv0_lq_instr_i1_s2_p = (rv0_t0_i1_s2_p_q & {`GPR_POOL_ENC{rv0_lq_i1_sel[0]}}) | (rv0_t1_i0_s2_p_q & {`GPR_POOL_ENC{rv0_lq_i1_sel[1]}}) | (rv0_t1_i1_s2_p_q & {`GPR_POOL_ENC{rv0_lq_i1_sel[2]}}); + assign rv0_lq_instr_i1_s2_t = (rv0_t0_i1_s2_t_q & {3{rv0_lq_i1_sel[0]}}) | (rv0_t1_i0_s2_t_q & {3{rv0_lq_i1_sel[1]}}) | (rv0_t1_i1_s2_t_q & {3{rv0_lq_i1_sel[2]}}); + assign rv1_lq_instr_i1_s3_t_d = (rv0_t0_i1_s3_t_q & {3{rv0_lq_i1_sel[0]}}) | (rv0_t1_i0_s3_t_q & {3{rv0_lq_i1_sel[1]}}) | (rv0_t1_i1_s3_t_q & {3{rv0_lq_i1_sel[2]}}); + + assign rv1_lq_instr_i1_isLoad_d = (rv0_t0_i1_isLoad_q & rv0_lq_i1_sel[0]) | (rv0_t1_i0_isLoad_q & rv0_lq_i1_sel[1]) | (rv0_t1_i1_isLoad_q & rv0_lq_i1_sel[2]); + assign rv1_lq_instr_i1_isStore_d = (rv0_t0_i1_isStore_q & rv0_lq_i1_sel[0]) | (rv0_t1_i0_isStore_q & rv0_lq_i1_sel[1]) | (rv0_t1_i1_isStore_q & rv0_lq_i1_sel[2]); + assign rv0_lq_instr_i1_spare = (rv0_t0_i1_spare_q & {4{rv0_lq_i1_sel[0]}}) | (rv0_t1_i0_spare_q & {4{rv0_lq_i1_sel[1]}}) | (rv0_t1_i1_spare_q & {4{rv0_lq_i1_sel[2]}}); + assign rv0_lq_instr_i1_is_brick = (rv0_t0_i1_is_brick & rv0_lq_i1_sel[0]) | (rv0_t1_i0_is_brick & rv0_lq_i1_sel[1]) | (rv0_t1_i1_is_brick & rv0_lq_i1_sel[2]); + assign rv0_lq_instr_i1_brick = (rv0_t0_i1_brick & {3{rv0_lq_i1_sel[0]}}) | (rv0_t1_i0_brick & {3{rv0_lq_i1_sel[1]}}) | (rv0_t1_i1_brick & {3{rv0_lq_i1_sel[2]}}); + + + + //------------------------------------------------------------------------------------------------------------ + // axu0 RV0 + //------------------------------------------------------------------------------------------------------------ + assign rv0_axu0_i0_sel[0] = rv0_t0_i0_rte_axu0_q; + assign rv0_axu0_i0_sel[1] = rv0_t0_i1_rte_axu0_q & (rv0_t1_i0_rte_axu0_q | rv0_t1_i1_rte_axu0_q); + assign rv0_axu0_i0_sel[2] = rv0_t1_i0_rte_axu0_q & (~rv0_t0_i0_rte_axu0_q) & (~rv0_t0_i1_rte_axu0_q); + assign rv0_axu0_i1_sel[0] = rv0_t0_i1_rte_axu0_q & (~rv0_t1_i0_rte_axu0_q) & (~rv0_t1_i1_rte_axu0_q); + assign rv0_axu0_i1_sel[1] = rv0_t1_i0_rte_axu0_q & (rv0_t0_i0_rte_axu0_q | rv0_t0_i1_rte_axu0_q); + assign rv0_axu0_i1_sel[2] = rv0_t1_i1_rte_axu0_q; + + assign rv0_axu0_instr_i0_vld = {((rv0_axu0_i0_sel[0] & rv0_t0_i0_vld_q) | (rv0_axu0_i0_sel[1] & rv0_t0_i1_vld_q)), (rv0_axu0_i0_sel[2] & rv0_t1_i0_vld_q)}; + assign rv0_axu0_instr_i1_vld = {(rv0_axu0_i1_sel[0] & rv0_t0_i1_vld_q), ((rv0_axu0_i1_sel[1] & rv0_t1_i0_vld_q) | (rv0_axu0_i1_sel[2] & rv0_t1_i1_vld_q))}; + + assign rv0_axu0_instr_i0_rte_axu0 = |(rv0_axu0_i0_sel); + + assign rv0_axu0_instr_i1_rte_axu0 = |(rv0_axu0_i1_sel); + + assign rv0_axu0_instr_i0_s1_dep_hit = (rv0_instr_i0_s1_dep_hit[0] & rv0_axu0_i0_sel[0]) | (rv0_instr_i1_s1_dep_hit_loc[0] & rv0_axu0_i0_sel[1]) | (rv0_instr_i0_s1_dep_hit[1] & rv0_axu0_i0_sel[2]); + assign rv0_axu0_instr_i0_s2_dep_hit = (rv0_instr_i0_s2_dep_hit[0] & rv0_axu0_i0_sel[0]) | (rv0_instr_i1_s2_dep_hit_loc[0] & rv0_axu0_i0_sel[1]) | (rv0_instr_i0_s2_dep_hit[1] & rv0_axu0_i0_sel[2]); + assign rv0_axu0_instr_i0_s3_dep_hit = (rv0_instr_i0_s3_dep_hit[0] & rv0_axu0_i0_sel[0]) | (rv0_instr_i1_s3_dep_hit_loc[0] & rv0_axu0_i0_sel[1]) | (rv0_instr_i0_s3_dep_hit[1] & rv0_axu0_i0_sel[2]); + + assign rv0_axu0_instr_i0_s1_itag = (rv0_t0_i0_s1_itag_q & {`ITAG_SIZE_ENC{rv0_axu0_i0_sel[0]}}) | (rv0_instr_i1_s1_itag_loc[0] & {`ITAG_SIZE_ENC{rv0_axu0_i0_sel[1]}}) | (rv0_t1_i0_s1_itag_q & {`ITAG_SIZE_ENC{rv0_axu0_i0_sel[2]}}); + assign rv0_axu0_instr_i0_s2_itag = (rv0_t0_i0_s2_itag_q & {`ITAG_SIZE_ENC{rv0_axu0_i0_sel[0]}}) | (rv0_instr_i1_s2_itag_loc[0] & {`ITAG_SIZE_ENC{rv0_axu0_i0_sel[1]}}) | (rv0_t1_i0_s2_itag_q & {`ITAG_SIZE_ENC{rv0_axu0_i0_sel[2]}}); + assign rv0_axu0_instr_i0_s3_itag = (rv0_t0_i0_s3_itag_q & {`ITAG_SIZE_ENC{rv0_axu0_i0_sel[0]}}) | (rv0_instr_i1_s3_itag_loc[0] & {`ITAG_SIZE_ENC{rv0_axu0_i0_sel[1]}}) | (rv0_t1_i0_s3_itag_q & {`ITAG_SIZE_ENC{rv0_axu0_i0_sel[2]}}); + + assign rv0_axu0_instr_i1_s1_dep_hit = (rv0_instr_i1_s1_dep_hit_loc[0] & rv0_axu0_i1_sel[0]) | (rv0_instr_i0_s1_dep_hit[1] & rv0_axu0_i1_sel[1]) | (rv0_instr_i1_s1_dep_hit_loc[1] & rv0_axu0_i1_sel[2]); + assign rv0_axu0_instr_i1_s2_dep_hit = (rv0_instr_i1_s2_dep_hit_loc[0] & rv0_axu0_i1_sel[0]) | (rv0_instr_i0_s2_dep_hit[1] & rv0_axu0_i1_sel[1]) | (rv0_instr_i1_s2_dep_hit_loc[1] & rv0_axu0_i1_sel[2]); + assign rv0_axu0_instr_i1_s3_dep_hit = (rv0_instr_i1_s3_dep_hit_loc[0] & rv0_axu0_i1_sel[0]) | (rv0_instr_i0_s3_dep_hit[1] & rv0_axu0_i1_sel[1]) | (rv0_instr_i1_s3_dep_hit_loc[1] & rv0_axu0_i1_sel[2]); + assign rv0_axu0_instr_i1_s1_itag = (rv0_instr_i1_s1_itag_loc[0] & {`ITAG_SIZE_ENC{rv0_axu0_i1_sel[0]}}) | (rv0_t1_i0_s1_itag_q & {`ITAG_SIZE_ENC{rv0_axu0_i1_sel[1]}}) | (rv0_instr_i1_s1_itag_loc[1] & {`ITAG_SIZE_ENC{rv0_axu0_i1_sel[2]}}); + assign rv0_axu0_instr_i1_s2_itag = (rv0_instr_i1_s2_itag_loc[0] & {`ITAG_SIZE_ENC{rv0_axu0_i1_sel[0]}}) | (rv0_t1_i0_s2_itag_q & {`ITAG_SIZE_ENC{rv0_axu0_i1_sel[1]}}) | (rv0_instr_i1_s2_itag_loc[1] & {`ITAG_SIZE_ENC{rv0_axu0_i1_sel[2]}}); + assign rv0_axu0_instr_i1_s3_itag = (rv0_instr_i1_s3_itag_loc[0] & {`ITAG_SIZE_ENC{rv0_axu0_i1_sel[0]}}) | (rv0_t1_i0_s3_itag_q & {`ITAG_SIZE_ENC{rv0_axu0_i1_sel[1]}}) | (rv0_instr_i1_s3_itag_loc[1] & {`ITAG_SIZE_ENC{rv0_axu0_i1_sel[2]}}); + + //------------------------------------------------------------------------------------------------------------ + // AXU0 RV1 + //------------------------------------------------------------------------------------------------------------ + + assign rv0_axu0_instr_i0_instr = (rv0_t0_i0_instr_q & {32{rv0_axu0_i0_sel[0]}}) | (rv0_t0_i1_instr_q & {32{rv0_axu0_i0_sel[1]}}) | (rv0_t1_i0_instr_q & {32{rv0_axu0_i0_sel[2]}}); + assign rv0_axu0_instr_i0_ucode = (rv0_t0_i0_ucode_q & {3{rv0_axu0_i0_sel[0]}}) | (rv0_t0_i1_ucode_q & {3{rv0_axu0_i0_sel[1]}}) | (rv0_t1_i0_ucode_q & {3{rv0_axu0_i0_sel[2]}}); + assign rv0_axu0_instr_i0_itag = (rv0_t0_i0_itag_q & {`ITAG_SIZE_ENC{rv0_axu0_i0_sel[0]}}) | (rv0_t0_i1_itag_q & {`ITAG_SIZE_ENC{rv0_axu0_i0_sel[1]}}) | (rv0_t1_i0_itag_q & {`ITAG_SIZE_ENC{rv0_axu0_i0_sel[2]}}); + assign rv0_axu0_instr_i0_ord = (rv0_t0_i0_ord_q & rv0_axu0_i0_sel[0]) | ( rv0_t0_i1_ord_q & rv0_axu0_i0_sel[1]) | (rv0_t1_i0_ord_q & rv0_axu0_i0_sel[2]); + assign rv0_axu0_instr_i0_cord = (rv0_t0_i0_cord_q & rv0_axu0_i0_sel[0]) | (rv0_t0_i1_cord_q & rv0_axu0_i0_sel[1]) | (rv0_t1_i0_cord_q & rv0_axu0_i0_sel[2]); + assign rv0_axu0_instr_i0_isStore = (rv0_t0_i0_isStore_q & rv0_axu0_i0_sel[0]) | (rv0_t0_i1_isStore_q & rv0_axu0_i0_sel[1]) | (rv0_t1_i0_isStore_q & rv0_axu0_i0_sel[2]); + + assign rv0_axu0_instr_i0_t1_v = (rv0_t0_i0_t1_v_q & rv0_axu0_i0_sel[0]) | (rv0_t0_i1_t1_v_q & rv0_axu0_i0_sel[1]) | (rv0_t1_i0_t1_v_q & rv0_axu0_i0_sel[2]); + assign rv0_axu0_instr_i0_t1_p = (rv0_t0_i0_t1_p_q & {`GPR_POOL_ENC{rv0_axu0_i0_sel[0]}}) | (rv0_t0_i1_t1_p_q & {`GPR_POOL_ENC{rv0_axu0_i0_sel[1]}}) | (rv0_t1_i0_t1_p_q & {`GPR_POOL_ENC{rv0_axu0_i0_sel[2]}}); + assign rv0_axu0_instr_i0_t2_p = (rv0_t0_i0_t2_p_q & {`GPR_POOL_ENC{rv0_axu0_i0_sel[0]}}) | (rv0_t0_i1_t2_p_q & {`GPR_POOL_ENC{rv0_axu0_i0_sel[1]}}) | (rv0_t1_i0_t2_p_q & {`GPR_POOL_ENC{rv0_axu0_i0_sel[2]}}); + assign rv0_axu0_instr_i0_t3_p = (rv0_t0_i0_t3_p_q & {`GPR_POOL_ENC{rv0_axu0_i0_sel[0]}}) | (rv0_t0_i1_t3_p_q & {`GPR_POOL_ENC{rv0_axu0_i0_sel[1]}}) | (rv0_t1_i0_t3_p_q & {`GPR_POOL_ENC{rv0_axu0_i0_sel[2]}}); + + assign rv0_axu0_instr_i0_s1_v = (rv0_t0_i0_s1_v_q & rv0_axu0_i0_sel[0]) | (rv0_t0_i1_s1_v_q & rv0_axu0_i0_sel[1]) | (rv0_t1_i0_s1_v_q & rv0_axu0_i0_sel[2]); + assign rv0_axu0_instr_i0_s1_p = (rv0_t0_i0_s1_p_q & {`GPR_POOL_ENC{rv0_axu0_i0_sel[0]}}) | (rv0_t0_i1_s1_p_q & {`GPR_POOL_ENC{rv0_axu0_i0_sel[1]}}) | (rv0_t1_i0_s1_p_q & {`GPR_POOL_ENC{rv0_axu0_i0_sel[2]}}); + assign rv0_axu0_instr_i0_s2_v = (rv0_t0_i0_s2_v_q & rv0_axu0_i0_sel[0]) | (rv0_t0_i1_s2_v_q & rv0_axu0_i0_sel[1]) | (rv0_t1_i0_s2_v_q & rv0_axu0_i0_sel[2]); + assign rv0_axu0_instr_i0_s2_p = (rv0_t0_i0_s2_p_q & {`GPR_POOL_ENC{rv0_axu0_i0_sel[0]}}) | (rv0_t0_i1_s2_p_q & {`GPR_POOL_ENC{rv0_axu0_i0_sel[1]}}) | (rv0_t1_i0_s2_p_q & {`GPR_POOL_ENC{rv0_axu0_i0_sel[2]}}); + assign rv0_axu0_instr_i0_s3_v = (rv0_t0_i0_s3_v_q & rv0_axu0_i0_sel[0]) | (rv0_t0_i1_s3_v_q & rv0_axu0_i0_sel[1]) | (rv0_t1_i0_s3_v_q & rv0_axu0_i0_sel[2]); + assign rv0_axu0_instr_i0_s3_p = (rv0_t0_i0_s3_p_q & {`GPR_POOL_ENC{rv0_axu0_i0_sel[0]}}) | (rv0_t0_i1_s3_p_q & {`GPR_POOL_ENC{rv0_axu0_i0_sel[1]}}) | (rv0_t1_i0_s3_p_q & {`GPR_POOL_ENC{rv0_axu0_i0_sel[2]}}); + + assign rv0_axu0_instr_i0_spare = (rv0_t0_i0_spare_q & {4{rv0_axu0_i0_sel[0]}}) | (rv0_t0_i1_spare_q & {4{rv0_axu0_i0_sel[1]}}) | (rv0_t1_i0_spare_q & {4{rv0_axu0_i0_sel[2]}}); + + + assign rv0_axu0_instr_i1_instr = (rv0_t0_i1_instr_q & {32{rv0_axu0_i1_sel[0]}}) | (rv0_t1_i0_instr_q & {32{rv0_axu0_i1_sel[1]}}) | (rv0_t1_i1_instr_q & {32{rv0_axu0_i1_sel[2]}}); + assign rv0_axu0_instr_i1_ucode = (rv0_t0_i1_ucode_q & {3{rv0_axu0_i1_sel[0]}}) | (rv0_t1_i0_ucode_q & {3{rv0_axu0_i1_sel[1]}}) | (rv0_t1_i1_ucode_q & {3{rv0_axu0_i1_sel[2]}}); + assign rv0_axu0_instr_i1_itag = (rv0_t0_i1_itag_q & {`ITAG_SIZE_ENC{rv0_axu0_i1_sel[0]}}) | (rv0_t1_i0_itag_q & {`ITAG_SIZE_ENC{rv0_axu0_i1_sel[1]}}) | (rv0_t1_i1_itag_q & {`ITAG_SIZE_ENC{rv0_axu0_i1_sel[2]}}); + assign rv0_axu0_instr_i1_ord = (rv0_t0_i1_ord_q & rv0_axu0_i1_sel[0]) | ( rv0_t1_i0_ord_q & rv0_axu0_i1_sel[1]) | (rv0_t1_i1_ord_q & rv0_axu0_i1_sel[2]); + assign rv0_axu0_instr_i1_cord = (rv0_t0_i1_cord_q & rv0_axu0_i1_sel[0]) | (rv0_t1_i0_cord_q & rv0_axu0_i1_sel[1]) | (rv0_t1_i1_cord_q & rv0_axu0_i1_sel[2]); + assign rv0_axu0_instr_i1_isStore = (rv0_t0_i1_isStore_q & rv0_axu0_i1_sel[0]) | (rv0_t1_i0_isStore_q & rv0_axu0_i1_sel[1]) | (rv0_t1_i1_isStore_q & rv0_axu0_i1_sel[2]); + + assign rv0_axu0_instr_i1_t1_v = (rv0_t0_i1_t1_v_q & rv0_axu0_i1_sel[0]) | (rv0_t1_i0_t1_v_q & rv0_axu0_i1_sel[1]) | (rv0_t1_i1_t1_v_q & rv0_axu0_i1_sel[2]); + assign rv0_axu0_instr_i1_t1_p = (rv0_t0_i1_t1_p_q & {`GPR_POOL_ENC{rv0_axu0_i1_sel[0]}}) | (rv0_t1_i0_t1_p_q & {`GPR_POOL_ENC{rv0_axu0_i1_sel[1]}}) | (rv0_t1_i1_t1_p_q & {`GPR_POOL_ENC{rv0_axu0_i1_sel[2]}}); + assign rv0_axu0_instr_i1_t2_p = (rv0_t0_i1_t2_p_q & {`GPR_POOL_ENC{rv0_axu0_i1_sel[0]}}) | (rv0_t1_i0_t2_p_q & {`GPR_POOL_ENC{rv0_axu0_i1_sel[1]}}) | (rv0_t1_i1_t2_p_q & {`GPR_POOL_ENC{rv0_axu0_i1_sel[2]}}); + assign rv0_axu0_instr_i1_t3_p = (rv0_t0_i1_t3_p_q & {`GPR_POOL_ENC{rv0_axu0_i1_sel[0]}}) | (rv0_t1_i0_t3_p_q & {`GPR_POOL_ENC{rv0_axu0_i1_sel[1]}}) | (rv0_t1_i1_t3_p_q & {`GPR_POOL_ENC{rv0_axu0_i1_sel[2]}}); + + assign rv0_axu0_instr_i1_s1_v = (rv0_t0_i1_s1_v_q & rv0_axu0_i1_sel[0]) | (rv0_t1_i0_s1_v_q & rv0_axu0_i1_sel[1]) | (rv0_t1_i1_s1_v_q & rv0_axu0_i1_sel[2]); + assign rv0_axu0_instr_i1_s1_p = (rv0_t0_i1_s1_p_q & {`GPR_POOL_ENC{rv0_axu0_i1_sel[0]}}) | (rv0_t1_i0_s1_p_q & {`GPR_POOL_ENC{rv0_axu0_i1_sel[1]}}) | (rv0_t1_i1_s1_p_q & {`GPR_POOL_ENC{rv0_axu0_i1_sel[2]}}); + assign rv0_axu0_instr_i1_s2_v = (rv0_t0_i1_s2_v_q & rv0_axu0_i1_sel[0]) | (rv0_t1_i0_s2_v_q & rv0_axu0_i1_sel[1]) | (rv0_t1_i1_s2_v_q & rv0_axu0_i1_sel[2]); + assign rv0_axu0_instr_i1_s2_p = (rv0_t0_i1_s2_p_q & {`GPR_POOL_ENC{rv0_axu0_i1_sel[0]}}) | (rv0_t1_i0_s2_p_q & {`GPR_POOL_ENC{rv0_axu0_i1_sel[1]}}) | (rv0_t1_i1_s2_p_q & {`GPR_POOL_ENC{rv0_axu0_i1_sel[2]}}); + assign rv0_axu0_instr_i1_s3_v = (rv0_t0_i1_s3_v_q & rv0_axu0_i1_sel[0]) | (rv0_t1_i0_s3_v_q & rv0_axu0_i1_sel[1]) | (rv0_t1_i1_s3_v_q & rv0_axu0_i1_sel[2]); + assign rv0_axu0_instr_i1_s3_p = (rv0_t0_i1_s3_p_q & {`GPR_POOL_ENC{rv0_axu0_i1_sel[0]}}) | (rv0_t1_i0_s3_p_q & {`GPR_POOL_ENC{rv0_axu0_i1_sel[1]}}) | (rv0_t1_i1_s3_p_q & {`GPR_POOL_ENC{rv0_axu0_i1_sel[2]}}); + + assign rv0_axu0_instr_i1_spare = (rv0_t0_i1_spare_q & {4{rv0_axu0_i1_sel[0]}}) | (rv0_t1_i0_spare_q & {4{rv0_axu0_i1_sel[1]}}) | (rv0_t1_i1_spare_q & {4{rv0_axu0_i1_sel[2]}}); + + +`endif // `ifndef THREADS1 + + + + //------------------------------------------------------------------------------------------------------------ + // Dep Hit Outputs + //------------------------------------------------------------------------------------------------------------ + + + //------------------------------------------------------------------------------------------------------------ + // LQ RV1 outputs for sq + //------------------------------------------------------------------------------------------------------------ + + assign rv0_lq_instr_i0_ucode = rv1_lq_instr_i0_ucode_d; + assign rv0_lq_instr_i0_ucode_cnt = rv1_lq_instr_i0_ucode_cnt_d; + assign rv0_lq_instr_i0_itag = rv1_lq_instr_i0_itag_d; + assign rv0_lq_instr_i0_isLoad = rv1_lq_instr_i0_isLoad_d; + + assign rv0_lq_instr_i1_ucode = rv1_lq_instr_i1_ucode_d; + assign rv0_lq_instr_i1_ucode_cnt = rv1_lq_instr_i1_ucode_cnt_d; + assign rv0_lq_instr_i1_itag = rv1_lq_instr_i1_itag_d; + assign rv0_lq_instr_i1_isLoad = rv1_lq_instr_i1_isLoad_d; + + assign rv1_lq_instr_i0_ucode_preissue_d = rv1_lq_instr_i0_ucode_d[1]; + assign rv1_lq_instr_i0_ifar_d = rv0_lq_instr_i0_ifar; + + assign rv_lq_rv1_i0_vld = rv1_lq_instr_i0_vld_q; + assign rv_lq_rv1_i0_rte_lq = rv1_lq_instr_i0_rte_lq_q; + assign rv_lq_rv1_i0_rte_sq = rv1_lq_instr_i0_rte_sq_q; + assign rv_lq_rv1_i0_ucode_preissue = rv1_lq_instr_i0_ucode_preissue_q; + assign rv_lq_rv1_i0_2ucode = rv1_lq_instr_i0_2ucode_q; + assign rv_lq_rv1_i0_ucode_cnt = rv1_lq_instr_i0_ucode_cnt_q; + assign rv_lq_rv1_i0_s3_t = rv1_lq_instr_i0_s3_t_q; + assign rv_lq_rv1_i0_isLoad = rv1_lq_instr_i0_isLoad_q; + assign rv_lq_rv1_i0_isStore = rv1_lq_instr_i0_isStore_q; + assign rv_lq_rv1_i0_itag = rv1_lq_instr_i0_itag_q; + assign rv_lq_rv1_i0_ifar = rv1_lq_instr_i0_ifar_q; + + assign rv1_lq_instr_i1_ucode_preissue_d = rv1_lq_instr_i1_ucode_d[1]; + assign rv1_lq_instr_i1_ifar_d = rv0_lq_instr_i1_ifar; + + assign rv_lq_rv1_i1_vld = rv1_lq_instr_i1_vld_q; + assign rv_lq_rv1_i1_rte_lq = rv1_lq_instr_i1_rte_lq_q; + assign rv_lq_rv1_i1_rte_sq = rv1_lq_instr_i1_rte_sq_q; + assign rv_lq_rv1_i1_ucode_preissue = rv1_lq_instr_i1_ucode_preissue_q; + assign rv_lq_rv1_i1_2ucode = rv1_lq_instr_i1_2ucode_q; + assign rv_lq_rv1_i1_ucode_cnt = rv1_lq_instr_i1_ucode_cnt_q; + assign rv_lq_rv1_i1_s3_t = rv1_lq_instr_i1_s3_t_q; + assign rv_lq_rv1_i1_isLoad = rv1_lq_instr_i1_isLoad_q; + assign rv_lq_rv1_i1_isStore = rv1_lq_instr_i1_isStore_q; + assign rv_lq_rv1_i1_itag = rv1_lq_instr_i1_itag_q; + assign rv_lq_rv1_i1_ifar = rv1_lq_instr_i1_ifar_q; + + + + + + + + //------------------------------------------------------------------------------------------------------------ + // Storage Elements RV0 + //------------------------------------------------------------------------------------------------------------ + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) cp_flush_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[cp_flush_offset:cp_flush_offset + `THREADS-1]), + .scout(sov[cp_flush_offset:cp_flush_offset + `THREADS-1]), + .din(cp_flush), + .dout(iu_xx_zap) + ); + + tri_rlmlatch_p #(.INIT(0)) rv0_t0_i0_vld_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i0_vld_offset]), + .scout(sov[rv0_t0_i0_vld_offset]), + .din(rv0_t0_i0_vld_d), + .dout(rv0_t0_i0_vld_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t0_i0_rte_lq_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i0_rte_lq_offset ]), + .scout(sov[rv0_t0_i0_rte_lq_offset ]), + .din(rv0_t0_i0_rte_lq_d), + .dout(rv0_t0_i0_rte_lq_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t0_i0_rte_sq_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i0_rte_sq_offset ]), + .scout(sov[rv0_t0_i0_rte_sq_offset ]), + .din(rv0_t0_i0_rte_sq_d), + .dout(rv0_t0_i0_rte_sq_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t0_i0_rte_fx0_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i0_rte_fx0_offset ]), + .scout(sov[rv0_t0_i0_rte_fx0_offset ]), + .din(rv0_t0_i0_rte_fx0_d), + .dout(rv0_t0_i0_rte_fx0_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t0_i0_rte_fx1_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i0_rte_fx1_offset ]), + .scout(sov[rv0_t0_i0_rte_fx1_offset ]), + .din(rv0_t0_i0_rte_fx1_d), + .dout(rv0_t0_i0_rte_fx1_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t0_i0_rte_axu0_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i0_rte_axu0_offset ]), + .scout(sov[rv0_t0_i0_rte_axu0_offset ]), + .din(rv0_t0_i0_rte_axu0_d), + .dout(rv0_t0_i0_rte_axu0_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t0_i0_rte_axu1_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i0_rte_axu1_offset ]), + .scout(sov[rv0_t0_i0_rte_axu1_offset ]), + .din(rv0_t0_i0_rte_axu1_d), + .dout(rv0_t0_i0_rte_axu1_q) + ); + + + tri_rlmreg_p #(.WIDTH(32), .INIT(0)) rv0_t0_i0_instr_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i0_instr_offset :rv0_t0_i0_instr_offset + 31 ]), + .scout(sov[rv0_t0_i0_instr_offset :rv0_t0_i0_instr_offset + 31 ]), + .din(rv0_t0_i0_instr_d), + .dout(rv0_t0_i0_instr_q) + ); + + + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) rv0_t0_i0_ifar_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i0_ifar_offset :rv0_t0_i0_ifar_offset + `EFF_IFAR_WIDTH - 1 ]), + .scout(sov[rv0_t0_i0_ifar_offset :rv0_t0_i0_ifar_offset + `EFF_IFAR_WIDTH - 1 ]), + .din(rv0_t0_i0_ifar_d), + .dout(rv0_t0_i0_ifar_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t0_i0_ucode_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i0_ucode_offset :rv0_t0_i0_ucode_offset + 3 - 1 ]), + .scout(sov[rv0_t0_i0_ucode_offset :rv0_t0_i0_ucode_offset + 3 - 1 ]), + .din(rv0_t0_i0_ucode_d), + .dout(rv0_t0_i0_ucode_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t0_i0_2ucode_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i0_2ucode_offset ]), + .scout(sov[rv0_t0_i0_2ucode_offset ]), + .din(rv0_t0_i0_2ucode_d), + .dout(rv0_t0_i0_2ucode_q) + ); + + + tri_rlmreg_p #(.WIDTH(`UCODE_ENTRIES_ENC), .INIT(0)) rv0_t0_i0_ucode_cnt_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i0_ucode_cnt_offset :rv0_t0_i0_ucode_cnt_offset + `UCODE_ENTRIES_ENC - 1 ]), + .scout(sov[rv0_t0_i0_ucode_cnt_offset :rv0_t0_i0_ucode_cnt_offset + `UCODE_ENTRIES_ENC - 1 ]), + .din(rv0_t0_i0_ucode_cnt_d), + .dout(rv0_t0_i0_ucode_cnt_q) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) rv0_t0_i0_itag_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i0_itag_offset :rv0_t0_i0_itag_offset + `ITAG_SIZE_ENC - 1 ]), + .scout(sov[rv0_t0_i0_itag_offset :rv0_t0_i0_itag_offset + `ITAG_SIZE_ENC - 1 ]), + .din(rv0_t0_i0_itag_d), + .dout(rv0_t0_i0_itag_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t0_i0_ord_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i0_ord_offset ]), + .scout(sov[rv0_t0_i0_ord_offset ]), + .din(rv0_t0_i0_ord_d), + .dout(rv0_t0_i0_ord_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t0_i0_cord_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i0_cord_offset ]), + .scout(sov[rv0_t0_i0_cord_offset ]), + .din(rv0_t0_i0_cord_d), + .dout(rv0_t0_i0_cord_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t0_i0_spec_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i0_spec_offset ]), + .scout(sov[rv0_t0_i0_spec_offset ]), + .din(rv0_t0_i0_spec_d), + .dout(rv0_t0_i0_spec_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t0_i0_t1_v_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i0_t1_v_offset ]), + .scout(sov[rv0_t0_i0_t1_v_offset ]), + .din(rv0_t0_i0_t1_v_d), + .dout(rv0_t0_i0_t1_v_q) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) rv0_t0_i0_t1_p_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i0_t1_p_offset :rv0_t0_i0_t1_p_offset + `GPR_POOL_ENC - 1 ]), + .scout(sov[rv0_t0_i0_t1_p_offset :rv0_t0_i0_t1_p_offset + `GPR_POOL_ENC - 1 ]), + .din(rv0_t0_i0_t1_p_d), + .dout(rv0_t0_i0_t1_p_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t0_i0_t1_t_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i0_t1_t_offset :rv0_t0_i0_t1_t_offset + 3 - 1 ]), + .scout(sov[rv0_t0_i0_t1_t_offset :rv0_t0_i0_t1_t_offset + 3 - 1 ]), + .din(rv0_t0_i0_t1_t_d), + .dout(rv0_t0_i0_t1_t_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t0_i0_t2_v_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i0_t2_v_offset ]), + .scout(sov[rv0_t0_i0_t2_v_offset ]), + .din(rv0_t0_i0_t2_v_d), + .dout(rv0_t0_i0_t2_v_q) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) rv0_t0_i0_t2_p_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i0_t2_p_offset :rv0_t0_i0_t2_p_offset + `GPR_POOL_ENC - 1 ]), + .scout(sov[rv0_t0_i0_t2_p_offset :rv0_t0_i0_t2_p_offset + `GPR_POOL_ENC - 1 ]), + .din(rv0_t0_i0_t2_p_d), + .dout(rv0_t0_i0_t2_p_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t0_i0_t2_t_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i0_t2_t_offset :rv0_t0_i0_t2_t_offset + 3 - 1 ]), + .scout(sov[rv0_t0_i0_t2_t_offset :rv0_t0_i0_t2_t_offset + 3 - 1 ]), + .din(rv0_t0_i0_t2_t_d), + .dout(rv0_t0_i0_t2_t_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t0_i0_t3_v_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i0_t3_v_offset ]), + .scout(sov[rv0_t0_i0_t3_v_offset ]), + .din(rv0_t0_i0_t3_v_d), + .dout(rv0_t0_i0_t3_v_q) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) rv0_t0_i0_t3_p_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i0_t3_p_offset :rv0_t0_i0_t3_p_offset + `GPR_POOL_ENC - 1 ]), + .scout(sov[rv0_t0_i0_t3_p_offset :rv0_t0_i0_t3_p_offset + `GPR_POOL_ENC - 1 ]), + .din(rv0_t0_i0_t3_p_d), + .dout(rv0_t0_i0_t3_p_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t0_i0_t3_t_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i0_t3_t_offset :rv0_t0_i0_t3_t_offset + 3 - 1 ]), + .scout(sov[rv0_t0_i0_t3_t_offset :rv0_t0_i0_t3_t_offset + 3 - 1 ]), + .din(rv0_t0_i0_t3_t_d), + .dout(rv0_t0_i0_t3_t_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t0_i0_s1_v_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i0_s1_v_offset ]), + .scout(sov[rv0_t0_i0_s1_v_offset ]), + .din(rv0_t0_i0_s1_v_d), + .dout(rv0_t0_i0_s1_v_q) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) rv0_t0_i0_s1_p_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i0_s1_p_offset :rv0_t0_i0_s1_p_offset + `GPR_POOL_ENC - 1 ]), + .scout(sov[rv0_t0_i0_s1_p_offset :rv0_t0_i0_s1_p_offset + `GPR_POOL_ENC - 1 ]), + .din(rv0_t0_i0_s1_p_d), + .dout(rv0_t0_i0_s1_p_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t0_i0_s1_t_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i0_s1_t_offset :rv0_t0_i0_s1_t_offset + 3 - 1 ]), + .scout(sov[rv0_t0_i0_s1_t_offset :rv0_t0_i0_s1_t_offset + 3 - 1 ]), + .din(rv0_t0_i0_s1_t_d), + .dout(rv0_t0_i0_s1_t_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t0_i0_s2_v_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i0_s2_v_offset ]), + .scout(sov[rv0_t0_i0_s2_v_offset ]), + .din(rv0_t0_i0_s2_v_d), + .dout(rv0_t0_i0_s2_v_q) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) rv0_t0_i0_s2_p_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i0_s2_p_offset :rv0_t0_i0_s2_p_offset + `GPR_POOL_ENC - 1 ]), + .scout(sov[rv0_t0_i0_s2_p_offset :rv0_t0_i0_s2_p_offset + `GPR_POOL_ENC - 1 ]), + .din(rv0_t0_i0_s2_p_d), + .dout(rv0_t0_i0_s2_p_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t0_i0_s2_t_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i0_s2_t_offset :rv0_t0_i0_s2_t_offset + 3 - 1 ]), + .scout(sov[rv0_t0_i0_s2_t_offset :rv0_t0_i0_s2_t_offset + 3 - 1 ]), + .din(rv0_t0_i0_s2_t_d), + .dout(rv0_t0_i0_s2_t_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t0_i0_s3_v_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i0_s3_v_offset ]), + .scout(sov[rv0_t0_i0_s3_v_offset ]), + .din(rv0_t0_i0_s3_v_d), + .dout(rv0_t0_i0_s3_v_q) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) rv0_t0_i0_s3_p_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i0_s3_p_offset :rv0_t0_i0_s3_p_offset + `GPR_POOL_ENC - 1 ]), + .scout(sov[rv0_t0_i0_s3_p_offset :rv0_t0_i0_s3_p_offset + `GPR_POOL_ENC - 1 ]), + .din(rv0_t0_i0_s3_p_d), + .dout(rv0_t0_i0_s3_p_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t0_i0_s3_t_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i0_s3_t_offset :rv0_t0_i0_s3_t_offset + 3 - 1 ]), + .scout(sov[rv0_t0_i0_s3_t_offset :rv0_t0_i0_s3_t_offset + 3 - 1 ]), + .din(rv0_t0_i0_s3_t_d), + .dout(rv0_t0_i0_s3_t_q) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) rv0_t0_i0_s1_itag_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i0_s1_itag_offset :rv0_t0_i0_s1_itag_offset + `ITAG_SIZE_ENC - 1 ]), + .scout(sov[rv0_t0_i0_s1_itag_offset :rv0_t0_i0_s1_itag_offset + `ITAG_SIZE_ENC - 1 ]), + .din(rv0_t0_i0_s1_itag_d), + .dout(rv0_t0_i0_s1_itag_q) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) rv0_t0_i0_s2_itag_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i0_s2_itag_offset :rv0_t0_i0_s2_itag_offset + `ITAG_SIZE_ENC - 1 ]), + .scout(sov[rv0_t0_i0_s2_itag_offset :rv0_t0_i0_s2_itag_offset + `ITAG_SIZE_ENC - 1 ]), + .din(rv0_t0_i0_s2_itag_d), + .dout(rv0_t0_i0_s2_itag_q) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) rv0_t0_i0_s3_itag_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i0_s3_itag_offset :rv0_t0_i0_s3_itag_offset + `ITAG_SIZE_ENC - 1 ]), + .scout(sov[rv0_t0_i0_s3_itag_offset :rv0_t0_i0_s3_itag_offset + `ITAG_SIZE_ENC - 1 ]), + .din(rv0_t0_i0_s3_itag_d), + .dout(rv0_t0_i0_s3_itag_q) + ); + + + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) rv0_t0_i0_ilat_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i0_ilat_offset :rv0_t0_i0_ilat_offset + 4 - 1 ]), + .scout(sov[rv0_t0_i0_ilat_offset :rv0_t0_i0_ilat_offset + 4 - 1 ]), + .din(rv0_t0_i0_ilat_d), + .dout(rv0_t0_i0_ilat_q) + ); + + + tri_rlmreg_p #(.WIDTH(`G_BRANCH_LEN), .INIT(0)) rv0_t0_i0_branch_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i0_branch_offset :rv0_t0_i0_branch_offset + `G_BRANCH_LEN - 1 ]), + .scout(sov[rv0_t0_i0_branch_offset :rv0_t0_i0_branch_offset + `G_BRANCH_LEN - 1 ]), + .din(rv0_t0_i0_branch_d), + .dout(rv0_t0_i0_branch_q) + ); + + tri_rlmlatch_p #(.INIT(0)) rv0_t0_i0_isLoad_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i0_isLoad_offset ]), + .scout(sov[rv0_t0_i0_isLoad_offset ]), + .din(rv0_t0_i0_isLoad_d), + .dout(rv0_t0_i0_isLoad_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t0_i0_isStore_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i0_isStore_offset ]), + .scout(sov[rv0_t0_i0_isStore_offset ]), + .din(rv0_t0_i0_isStore_d), + .dout(rv0_t0_i0_isStore_q) + ); + + assign rv0_t0_i0_spare_d = 4'b0000; + + + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) rv0_t0_i0_spare_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i0_spare_offset :rv0_t0_i0_spare_offset + 4 - 1 ]), + .scout(sov[rv0_t0_i0_spare_offset :rv0_t0_i0_spare_offset + 4 - 1 ]), + .din(rv0_t0_i0_spare_d), + .dout(rv0_t0_i0_spare_q) + ); + + //t0_i1 + tri_rlmlatch_p #( .INIT(0)) rv0_t0_i1_vld_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i1_vld_offset]), + .scout(sov[rv0_t0_i1_vld_offset]), + .din(rv0_t0_i1_vld_d), + .dout(rv0_t0_i1_vld_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t0_i1_rte_lq_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i1_rte_lq_offset ]), + .scout(sov[rv0_t0_i1_rte_lq_offset ]), + .din(rv0_t0_i1_rte_lq_d), + .dout(rv0_t0_i1_rte_lq_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t0_i1_rte_sq_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i1_rte_sq_offset ]), + .scout(sov[rv0_t0_i1_rte_sq_offset ]), + .din(rv0_t0_i1_rte_sq_d), + .dout(rv0_t0_i1_rte_sq_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t0_i1_rte_fx0_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i1_rte_fx0_offset ]), + .scout(sov[rv0_t0_i1_rte_fx0_offset ]), + .din(rv0_t0_i1_rte_fx0_d), + .dout(rv0_t0_i1_rte_fx0_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t0_i1_rte_fx1_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i1_rte_fx1_offset ]), + .scout(sov[rv0_t0_i1_rte_fx1_offset ]), + .din(rv0_t0_i1_rte_fx1_d), + .dout(rv0_t0_i1_rte_fx1_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t0_i1_rte_axu0_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i1_rte_axu0_offset ]), + .scout(sov[rv0_t0_i1_rte_axu0_offset ]), + .din(rv0_t0_i1_rte_axu0_d), + .dout(rv0_t0_i1_rte_axu0_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t0_i1_rte_axu1_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i1_rte_axu1_offset ]), + .scout(sov[rv0_t0_i1_rte_axu1_offset ]), + .din(rv0_t0_i1_rte_axu1_d), + .dout(rv0_t0_i1_rte_axu1_q) + ); + + + tri_rlmreg_p #(.WIDTH(32), .INIT(0)) rv0_t0_i1_instr_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i1_instr_offset :rv0_t0_i1_instr_offset + 31 ]), + .scout(sov[rv0_t0_i1_instr_offset :rv0_t0_i1_instr_offset + 31 ]), + .din(rv0_t0_i1_instr_d), + .dout(rv0_t0_i1_instr_q) + ); + + + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) rv0_t0_i1_ifar_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i1_ifar_offset :rv0_t0_i1_ifar_offset + `EFF_IFAR_WIDTH - 1 ]), + .scout(sov[rv0_t0_i1_ifar_offset :rv0_t0_i1_ifar_offset + `EFF_IFAR_WIDTH - 1 ]), + .din(rv0_t0_i1_ifar_d), + .dout(rv0_t0_i1_ifar_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t0_i1_ucode_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i1_ucode_offset :rv0_t0_i1_ucode_offset + 3 - 1 ]), + .scout(sov[rv0_t0_i1_ucode_offset :rv0_t0_i1_ucode_offset + 3 - 1 ]), + .din(rv0_t0_i1_ucode_d), + .dout(rv0_t0_i1_ucode_q) + ); + + + + + tri_rlmreg_p #(.WIDTH(`UCODE_ENTRIES_ENC), .INIT(0)) rv0_t0_i1_ucode_cnt_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i1_ucode_cnt_offset :rv0_t0_i1_ucode_cnt_offset + `UCODE_ENTRIES_ENC - 1 ]), + .scout(sov[rv0_t0_i1_ucode_cnt_offset :rv0_t0_i1_ucode_cnt_offset + `UCODE_ENTRIES_ENC - 1 ]), + .din(rv0_t0_i1_ucode_cnt_d), + .dout(rv0_t0_i1_ucode_cnt_q) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) rv0_t0_i1_itag_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i1_itag_offset :rv0_t0_i1_itag_offset + `ITAG_SIZE_ENC - 1 ]), + .scout(sov[rv0_t0_i1_itag_offset :rv0_t0_i1_itag_offset + `ITAG_SIZE_ENC - 1 ]), + .din(rv0_t0_i1_itag_d), + .dout(rv0_t0_i1_itag_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t0_i1_ord_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i1_ord_offset ]), + .scout(sov[rv0_t0_i1_ord_offset ]), + .din(rv0_t0_i1_ord_d), + .dout(rv0_t0_i1_ord_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t0_i1_cord_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i1_cord_offset ]), + .scout(sov[rv0_t0_i1_cord_offset ]), + .din(rv0_t0_i1_cord_d), + .dout(rv0_t0_i1_cord_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t0_i1_spec_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i1_spec_offset ]), + .scout(sov[rv0_t0_i1_spec_offset ]), + .din(rv0_t0_i1_spec_d), + .dout(rv0_t0_i1_spec_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t0_i1_t1_v_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i1_t1_v_offset ]), + .scout(sov[rv0_t0_i1_t1_v_offset ]), + .din(rv0_t0_i1_t1_v_d), + .dout(rv0_t0_i1_t1_v_q) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) rv0_t0_i1_t1_p_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i1_t1_p_offset :rv0_t0_i1_t1_p_offset + `GPR_POOL_ENC - 1 ]), + .scout(sov[rv0_t0_i1_t1_p_offset :rv0_t0_i1_t1_p_offset + `GPR_POOL_ENC - 1 ]), + .din(rv0_t0_i1_t1_p_d), + .dout(rv0_t0_i1_t1_p_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t0_i1_t1_t_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i1_t1_t_offset :rv0_t0_i1_t1_t_offset + 3 - 1 ]), + .scout(sov[rv0_t0_i1_t1_t_offset :rv0_t0_i1_t1_t_offset + 3 - 1 ]), + .din(rv0_t0_i1_t1_t_d), + .dout(rv0_t0_i1_t1_t_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t0_i1_t2_v_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i1_t2_v_offset ]), + .scout(sov[rv0_t0_i1_t2_v_offset ]), + .din(rv0_t0_i1_t2_v_d), + .dout(rv0_t0_i1_t2_v_q) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) rv0_t0_i1_t2_p_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i1_t2_p_offset :rv0_t0_i1_t2_p_offset + `GPR_POOL_ENC - 1 ]), + .scout(sov[rv0_t0_i1_t2_p_offset :rv0_t0_i1_t2_p_offset + `GPR_POOL_ENC - 1 ]), + .din(rv0_t0_i1_t2_p_d), + .dout(rv0_t0_i1_t2_p_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t0_i1_t2_t_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i1_t2_t_offset :rv0_t0_i1_t2_t_offset + 3 - 1 ]), + .scout(sov[rv0_t0_i1_t2_t_offset :rv0_t0_i1_t2_t_offset + 3 - 1 ]), + .din(rv0_t0_i1_t2_t_d), + .dout(rv0_t0_i1_t2_t_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t0_i1_t3_v_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i1_t3_v_offset ]), + .scout(sov[rv0_t0_i1_t3_v_offset ]), + .din(rv0_t0_i1_t3_v_d), + .dout(rv0_t0_i1_t3_v_q) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) rv0_t0_i1_t3_p_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i1_t3_p_offset :rv0_t0_i1_t3_p_offset + `GPR_POOL_ENC - 1 ]), + .scout(sov[rv0_t0_i1_t3_p_offset :rv0_t0_i1_t3_p_offset + `GPR_POOL_ENC - 1 ]), + .din(rv0_t0_i1_t3_p_d), + .dout(rv0_t0_i1_t3_p_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t0_i1_t3_t_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i1_t3_t_offset :rv0_t0_i1_t3_t_offset + 3 - 1 ]), + .scout(sov[rv0_t0_i1_t3_t_offset :rv0_t0_i1_t3_t_offset + 3 - 1 ]), + .din(rv0_t0_i1_t3_t_d), + .dout(rv0_t0_i1_t3_t_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t0_i1_s1_v_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i1_s1_v_offset ]), + .scout(sov[rv0_t0_i1_s1_v_offset ]), + .din(rv0_t0_i1_s1_v_d), + .dout(rv0_t0_i1_s1_v_q) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) rv0_t0_i1_s1_p_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i1_s1_p_offset :rv0_t0_i1_s1_p_offset + `GPR_POOL_ENC - 1 ]), + .scout(sov[rv0_t0_i1_s1_p_offset :rv0_t0_i1_s1_p_offset + `GPR_POOL_ENC - 1 ]), + .din(rv0_t0_i1_s1_p_d), + .dout(rv0_t0_i1_s1_p_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t0_i1_s1_t_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i1_s1_t_offset :rv0_t0_i1_s1_t_offset + 3 - 1 ]), + .scout(sov[rv0_t0_i1_s1_t_offset :rv0_t0_i1_s1_t_offset + 3 - 1 ]), + .din(rv0_t0_i1_s1_t_d), + .dout(rv0_t0_i1_s1_t_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t0_i1_s2_v_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i1_s2_v_offset ]), + .scout(sov[rv0_t0_i1_s2_v_offset ]), + .din(rv0_t0_i1_s2_v_d), + .dout(rv0_t0_i1_s2_v_q) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) rv0_t0_i1_s2_p_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i1_s2_p_offset :rv0_t0_i1_s2_p_offset + `GPR_POOL_ENC - 1 ]), + .scout(sov[rv0_t0_i1_s2_p_offset :rv0_t0_i1_s2_p_offset + `GPR_POOL_ENC - 1 ]), + .din(rv0_t0_i1_s2_p_d), + .dout(rv0_t0_i1_s2_p_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t0_i1_s2_t_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i1_s2_t_offset :rv0_t0_i1_s2_t_offset + 3 - 1 ]), + .scout(sov[rv0_t0_i1_s2_t_offset :rv0_t0_i1_s2_t_offset + 3 - 1 ]), + .din(rv0_t0_i1_s2_t_d), + .dout(rv0_t0_i1_s2_t_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t0_i1_s3_v_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i1_s3_v_offset ]), + .scout(sov[rv0_t0_i1_s3_v_offset ]), + .din(rv0_t0_i1_s3_v_d), + .dout(rv0_t0_i1_s3_v_q) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) rv0_t0_i1_s3_p_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i1_s3_p_offset :rv0_t0_i1_s3_p_offset + `GPR_POOL_ENC - 1 ]), + .scout(sov[rv0_t0_i1_s3_p_offset :rv0_t0_i1_s3_p_offset + `GPR_POOL_ENC - 1 ]), + .din(rv0_t0_i1_s3_p_d), + .dout(rv0_t0_i1_s3_p_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t0_i1_s3_t_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i1_s3_t_offset :rv0_t0_i1_s3_t_offset + 3 - 1 ]), + .scout(sov[rv0_t0_i1_s3_t_offset :rv0_t0_i1_s3_t_offset + 3 - 1 ]), + .din(rv0_t0_i1_s3_t_d), + .dout(rv0_t0_i1_s3_t_q) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) + rv0_t0_i1_s1_itag_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i1_s1_itag_offset :rv0_t0_i1_s1_itag_offset + `ITAG_SIZE_ENC - 1 ]), + .scout(sov[rv0_t0_i1_s1_itag_offset :rv0_t0_i1_s1_itag_offset + `ITAG_SIZE_ENC - 1 ]), + .din(rv0_t0_i1_s1_itag_d), + .dout(rv0_t0_i1_s1_itag_q) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) + rv0_t0_i1_s2_itag_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i1_s2_itag_offset :rv0_t0_i1_s2_itag_offset + `ITAG_SIZE_ENC - 1 ]), + .scout(sov[rv0_t0_i1_s2_itag_offset :rv0_t0_i1_s2_itag_offset + `ITAG_SIZE_ENC - 1 ]), + .din(rv0_t0_i1_s2_itag_d), + .dout(rv0_t0_i1_s2_itag_q) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) + rv0_t0_i1_s3_itag_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i1_s3_itag_offset :rv0_t0_i1_s3_itag_offset + `ITAG_SIZE_ENC - 1 ]), + .scout(sov[rv0_t0_i1_s3_itag_offset :rv0_t0_i1_s3_itag_offset + `ITAG_SIZE_ENC - 1 ]), + .din(rv0_t0_i1_s3_itag_d), + .dout(rv0_t0_i1_s3_itag_q) + ); + tri_rlmlatch_p #(.INIT(0)) + rv0_t0_i1_s1_dep_hit_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i1_s1_dep_hit_offset ]), + .scout(sov[rv0_t0_i1_s1_dep_hit_offset ]), + .din(rv0_t0_i1_s1_dep_hit_d), + .dout(rv0_t0_i1_s1_dep_hit_q) + ); + + tri_rlmlatch_p #(.INIT(0)) + rv0_t0_i1_s2_dep_hit_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i1_s2_dep_hit_offset ]), + .scout(sov[rv0_t0_i1_s2_dep_hit_offset ]), + .din(rv0_t0_i1_s2_dep_hit_d), + .dout(rv0_t0_i1_s2_dep_hit_q) + ); + + tri_rlmlatch_p #(.INIT(0)) + rv0_t0_i1_s3_dep_hit_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i1_s3_dep_hit_offset ]), + .scout(sov[rv0_t0_i1_s3_dep_hit_offset ]), + .din(rv0_t0_i1_s3_dep_hit_d), + .dout(rv0_t0_i1_s3_dep_hit_q) + ); + + + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) + rv0_t0_i1_ilat_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i1_ilat_offset :rv0_t0_i1_ilat_offset + 4 - 1 ]), + .scout(sov[rv0_t0_i1_ilat_offset :rv0_t0_i1_ilat_offset + 4 - 1 ]), + .din(rv0_t0_i1_ilat_d), + .dout(rv0_t0_i1_ilat_q) + ); + + + tri_rlmreg_p #(.WIDTH(`G_BRANCH_LEN), .INIT(0)) + rv0_t0_i1_branch_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i1_branch_offset :rv0_t0_i1_branch_offset + `G_BRANCH_LEN - 1 ]), + .scout(sov[rv0_t0_i1_branch_offset :rv0_t0_i1_branch_offset + `G_BRANCH_LEN - 1 ]), + .din(rv0_t0_i1_branch_d), + .dout(rv0_t0_i1_branch_q) + ); + + tri_rlmlatch_p #(.INIT(0)) rv0_t0_i1_isLoad_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i1_isLoad_offset ]), + .scout(sov[rv0_t0_i1_isLoad_offset ]), + .din(rv0_t0_i1_isLoad_d), + .dout(rv0_t0_i1_isLoad_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t0_i1_isStore_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i1_isStore_offset ]), + .scout(sov[rv0_t0_i1_isStore_offset ]), + .din(rv0_t0_i1_isStore_d), + .dout(rv0_t0_i1_isStore_q) + ); + + assign rv0_t0_i1_spare_d = 4'b0000; + + + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) rv0_t0_i1_spare_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t0_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t0_i1_spare_offset :rv0_t0_i1_spare_offset + 4 - 1 ]), + .scout(sov[rv0_t0_i1_spare_offset :rv0_t0_i1_spare_offset + 4 - 1 ]), + .din(rv0_t0_i1_spare_d), + .dout(rv0_t0_i1_spare_q) + ); + + + //------------------------------------------------------------------------------------------------------------ + // // Storage Elements RV1 + //------------------------------------------------------------------------------------------------------------ + + + + //t0_i1 +`ifndef THREADS1 + tri_rlmlatch_p #(.INIT(0)) rv0_t1_i0_vld_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i0_vld_offset]), + .scout(sov[rv0_t1_i0_vld_offset]), + .din(rv0_t1_i0_vld_d), + .dout(rv0_t1_i0_vld_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t1_i0_rte_lq_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i0_rte_lq_offset ]), + .scout(sov[rv0_t1_i0_rte_lq_offset ]), + .din(rv0_t1_i0_rte_lq_d), + .dout(rv0_t1_i0_rte_lq_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t1_i0_rte_sq_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i0_rte_sq_offset ]), + .scout(sov[rv0_t1_i0_rte_sq_offset ]), + .din(rv0_t1_i0_rte_sq_d), + .dout(rv0_t1_i0_rte_sq_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t1_i0_rte_fx0_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i0_rte_fx0_offset ]), + .scout(sov[rv0_t1_i0_rte_fx0_offset ]), + .din(rv0_t1_i0_rte_fx0_d), + .dout(rv0_t1_i0_rte_fx0_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t1_i0_rte_fx1_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i0_rte_fx1_offset ]), + .scout(sov[rv0_t1_i0_rte_fx1_offset ]), + .din(rv0_t1_i0_rte_fx1_d), + .dout(rv0_t1_i0_rte_fx1_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t1_i0_rte_axu0_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i0_rte_axu0_offset ]), + .scout(sov[rv0_t1_i0_rte_axu0_offset ]), + .din(rv0_t1_i0_rte_axu0_d), + .dout(rv0_t1_i0_rte_axu0_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t1_i0_rte_axu1_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i0_rte_axu1_offset ]), + .scout(sov[rv0_t1_i0_rte_axu1_offset ]), + .din(rv0_t1_i0_rte_axu1_d), + .dout(rv0_t1_i0_rte_axu1_q) + ); + + + tri_rlmreg_p #(.WIDTH(32), .INIT(0)) rv0_t1_i0_instr_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i0_instr_offset :rv0_t1_i0_instr_offset + 31 ]), + .scout(sov[rv0_t1_i0_instr_offset :rv0_t1_i0_instr_offset + 31 ]), + .din(rv0_t1_i0_instr_d), + .dout(rv0_t1_i0_instr_q) + ); + + + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) rv0_t1_i0_ifar_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i0_ifar_offset :rv0_t1_i0_ifar_offset + `EFF_IFAR_WIDTH - 1 ]), + .scout(sov[rv0_t1_i0_ifar_offset :rv0_t1_i0_ifar_offset + `EFF_IFAR_WIDTH - 1 ]), + .din(rv0_t1_i0_ifar_d), + .dout(rv0_t1_i0_ifar_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t1_i0_ucode_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i0_ucode_offset :rv0_t1_i0_ucode_offset + 3 - 1 ]), + .scout(sov[rv0_t1_i0_ucode_offset :rv0_t1_i0_ucode_offset + 3 - 1 ]), + .din(rv0_t1_i0_ucode_d), + .dout(rv0_t1_i0_ucode_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t1_i0_2ucode_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i0_2ucode_offset ]), + .scout(sov[rv0_t1_i0_2ucode_offset ]), + .din(rv0_t1_i0_2ucode_d), + .dout(rv0_t1_i0_2ucode_q) + ); + + + tri_rlmreg_p #(.WIDTH(`UCODE_ENTRIES_ENC), .INIT(0)) rv0_t1_i0_ucode_cnt_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i0_ucode_cnt_offset :rv0_t1_i0_ucode_cnt_offset + `UCODE_ENTRIES_ENC - 1 ]), + .scout(sov[rv0_t1_i0_ucode_cnt_offset :rv0_t1_i0_ucode_cnt_offset + `UCODE_ENTRIES_ENC - 1 ]), + .din(rv0_t1_i0_ucode_cnt_d), + .dout(rv0_t1_i0_ucode_cnt_q) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) rv0_t1_i0_itag_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i0_itag_offset :rv0_t1_i0_itag_offset + `ITAG_SIZE_ENC - 1 ]), + .scout(sov[rv0_t1_i0_itag_offset :rv0_t1_i0_itag_offset + `ITAG_SIZE_ENC - 1 ]), + .din(rv0_t1_i0_itag_d), + .dout(rv0_t1_i0_itag_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t1_i0_ord_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i0_ord_offset ]), + .scout(sov[rv0_t1_i0_ord_offset ]), + .din(rv0_t1_i0_ord_d), + .dout(rv0_t1_i0_ord_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t1_i0_cord_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i0_cord_offset ]), + .scout(sov[rv0_t1_i0_cord_offset ]), + .din(rv0_t1_i0_cord_d), + .dout(rv0_t1_i0_cord_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t1_i0_spec_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i0_spec_offset ]), + .scout(sov[rv0_t1_i0_spec_offset ]), + .din(rv0_t1_i0_spec_d), + .dout(rv0_t1_i0_spec_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t1_i0_t1_v_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i0_t1_v_offset ]), + .scout(sov[rv0_t1_i0_t1_v_offset ]), + .din(rv0_t1_i0_t1_v_d), + .dout(rv0_t1_i0_t1_v_q) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) rv0_t1_i0_t1_p_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i0_t1_p_offset :rv0_t1_i0_t1_p_offset + `GPR_POOL_ENC - 1 ]), + .scout(sov[rv0_t1_i0_t1_p_offset :rv0_t1_i0_t1_p_offset + `GPR_POOL_ENC - 1 ]), + .din(rv0_t1_i0_t1_p_d), + .dout(rv0_t1_i0_t1_p_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t1_i0_t1_t_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i0_t1_t_offset :rv0_t1_i0_t1_t_offset + 3 - 1 ]), + .scout(sov[rv0_t1_i0_t1_t_offset :rv0_t1_i0_t1_t_offset + 3 - 1 ]), + .din(rv0_t1_i0_t1_t_d), + .dout(rv0_t1_i0_t1_t_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t1_i0_t2_v_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i0_t2_v_offset ]), + .scout(sov[rv0_t1_i0_t2_v_offset ]), + .din(rv0_t1_i0_t2_v_d), + .dout(rv0_t1_i0_t2_v_q) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) rv0_t1_i0_t2_p_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i0_t2_p_offset :rv0_t1_i0_t2_p_offset + `GPR_POOL_ENC - 1 ]), + .scout(sov[rv0_t1_i0_t2_p_offset :rv0_t1_i0_t2_p_offset + `GPR_POOL_ENC - 1 ]), + .din(rv0_t1_i0_t2_p_d), + .dout(rv0_t1_i0_t2_p_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t1_i0_t2_t_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i0_t2_t_offset :rv0_t1_i0_t2_t_offset + 3 - 1 ]), + .scout(sov[rv0_t1_i0_t2_t_offset :rv0_t1_i0_t2_t_offset + 3 - 1 ]), + .din(rv0_t1_i0_t2_t_d), + .dout(rv0_t1_i0_t2_t_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t1_i0_t3_v_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i0_t3_v_offset ]), + .scout(sov[rv0_t1_i0_t3_v_offset ]), + .din(rv0_t1_i0_t3_v_d), + .dout(rv0_t1_i0_t3_v_q) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) rv0_t1_i0_t3_p_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i0_t3_p_offset :rv0_t1_i0_t3_p_offset + `GPR_POOL_ENC - 1 ]), + .scout(sov[rv0_t1_i0_t3_p_offset :rv0_t1_i0_t3_p_offset + `GPR_POOL_ENC - 1 ]), + .din(rv0_t1_i0_t3_p_d), + .dout(rv0_t1_i0_t3_p_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t1_i0_t3_t_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i0_t3_t_offset :rv0_t1_i0_t3_t_offset + 3 - 1 ]), + .scout(sov[rv0_t1_i0_t3_t_offset :rv0_t1_i0_t3_t_offset + 3 - 1 ]), + .din(rv0_t1_i0_t3_t_d), + .dout(rv0_t1_i0_t3_t_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t1_i0_s1_v_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i0_s1_v_offset ]), + .scout(sov[rv0_t1_i0_s1_v_offset ]), + .din(rv0_t1_i0_s1_v_d), + .dout(rv0_t1_i0_s1_v_q) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) rv0_t1_i0_s1_p_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i0_s1_p_offset :rv0_t1_i0_s1_p_offset + `GPR_POOL_ENC - 1 ]), + .scout(sov[rv0_t1_i0_s1_p_offset :rv0_t1_i0_s1_p_offset + `GPR_POOL_ENC - 1 ]), + .din(rv0_t1_i0_s1_p_d), + .dout(rv0_t1_i0_s1_p_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t1_i0_s1_t_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i0_s1_t_offset :rv0_t1_i0_s1_t_offset + 3 - 1 ]), + .scout(sov[rv0_t1_i0_s1_t_offset :rv0_t1_i0_s1_t_offset + 3 - 1 ]), + .din(rv0_t1_i0_s1_t_d), + .dout(rv0_t1_i0_s1_t_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t1_i0_s2_v_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i0_s2_v_offset ]), + .scout(sov[rv0_t1_i0_s2_v_offset ]), + .din(rv0_t1_i0_s2_v_d), + .dout(rv0_t1_i0_s2_v_q) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) rv0_t1_i0_s2_p_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i0_s2_p_offset :rv0_t1_i0_s2_p_offset + `GPR_POOL_ENC - 1 ]), + .scout(sov[rv0_t1_i0_s2_p_offset :rv0_t1_i0_s2_p_offset + `GPR_POOL_ENC - 1 ]), + .din(rv0_t1_i0_s2_p_d), + .dout(rv0_t1_i0_s2_p_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t1_i0_s2_t_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i0_s2_t_offset :rv0_t1_i0_s2_t_offset + 3 - 1 ]), + .scout(sov[rv0_t1_i0_s2_t_offset :rv0_t1_i0_s2_t_offset + 3 - 1 ]), + .din(rv0_t1_i0_s2_t_d), + .dout(rv0_t1_i0_s2_t_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t1_i0_s3_v_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i0_s3_v_offset ]), + .scout(sov[rv0_t1_i0_s3_v_offset ]), + .din(rv0_t1_i0_s3_v_d), + .dout(rv0_t1_i0_s3_v_q) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) rv0_t1_i0_s3_p_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i0_s3_p_offset :rv0_t1_i0_s3_p_offset + `GPR_POOL_ENC - 1 ]), + .scout(sov[rv0_t1_i0_s3_p_offset :rv0_t1_i0_s3_p_offset + `GPR_POOL_ENC - 1 ]), + .din(rv0_t1_i0_s3_p_d), + .dout(rv0_t1_i0_s3_p_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t1_i0_s3_t_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i0_s3_t_offset :rv0_t1_i0_s3_t_offset + 3 - 1 ]), + .scout(sov[rv0_t1_i0_s3_t_offset :rv0_t1_i0_s3_t_offset + 3 - 1 ]), + .din(rv0_t1_i0_s3_t_d), + .dout(rv0_t1_i0_s3_t_q) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) rv0_t1_i0_s1_itag_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i0_s1_itag_offset :rv0_t1_i0_s1_itag_offset + `ITAG_SIZE_ENC - 1 ]), + .scout(sov[rv0_t1_i0_s1_itag_offset :rv0_t1_i0_s1_itag_offset + `ITAG_SIZE_ENC - 1 ]), + .din(rv0_t1_i0_s1_itag_d), + .dout(rv0_t1_i0_s1_itag_q) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) rv0_t1_i0_s2_itag_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i0_s2_itag_offset :rv0_t1_i0_s2_itag_offset + `ITAG_SIZE_ENC - 1 ]), + .scout(sov[rv0_t1_i0_s2_itag_offset :rv0_t1_i0_s2_itag_offset + `ITAG_SIZE_ENC - 1 ]), + .din(rv0_t1_i0_s2_itag_d), + .dout(rv0_t1_i0_s2_itag_q) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) rv0_t1_i0_s3_itag_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i0_s3_itag_offset :rv0_t1_i0_s3_itag_offset + `ITAG_SIZE_ENC - 1 ]), + .scout(sov[rv0_t1_i0_s3_itag_offset :rv0_t1_i0_s3_itag_offset + `ITAG_SIZE_ENC - 1 ]), + .din(rv0_t1_i0_s3_itag_d), + .dout(rv0_t1_i0_s3_itag_q) + ); + + + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) rv0_t1_i0_ilat_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i0_ilat_offset :rv0_t1_i0_ilat_offset + 4 - 1 ]), + .scout(sov[rv0_t1_i0_ilat_offset :rv0_t1_i0_ilat_offset + 4 - 1 ]), + .din(rv0_t1_i0_ilat_d), + .dout(rv0_t1_i0_ilat_q) + ); + + + tri_rlmreg_p #(.WIDTH(`G_BRANCH_LEN), .INIT(0)) rv0_t1_i0_branch_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i0_branch_offset :rv0_t1_i0_branch_offset + `G_BRANCH_LEN - 1 ]), + .scout(sov[rv0_t1_i0_branch_offset :rv0_t1_i0_branch_offset + `G_BRANCH_LEN - 1 ]), + .din(rv0_t1_i0_branch_d), + .dout(rv0_t1_i0_branch_q) + ); + + tri_rlmlatch_p #(.INIT(0)) rv0_t1_i0_isLoad_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i0_isLoad_offset ]), + .scout(sov[rv0_t1_i0_isLoad_offset ]), + .din(rv0_t1_i0_isLoad_d), + .dout(rv0_t1_i0_isLoad_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t1_i0_isStore_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i0_isStore_offset ]), + .scout(sov[rv0_t1_i0_isStore_offset ]), + .din(rv0_t1_i0_isStore_d), + .dout(rv0_t1_i0_isStore_q) + ); + + assign rv0_t1_i0_spare_d = 4'b0000; + + + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) rv0_t1_i0_spare_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i0_spare_offset :rv0_t1_i0_spare_offset + 4 - 1 ]), + .scout(sov[rv0_t1_i0_spare_offset :rv0_t1_i0_spare_offset + 4 - 1 ]), + .din(rv0_t1_i0_spare_d), + .dout(rv0_t1_i0_spare_q) + ); + + //t1_i1 + tri_rlmlatch_p #( .INIT(0)) rv0_t1_i1_vld_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i1_vld_offset]), + .scout(sov[rv0_t1_i1_vld_offset]), + .din(rv0_t1_i1_vld_d), + .dout(rv0_t1_i1_vld_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t1_i1_rte_lq_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i1_rte_lq_offset ]), + .scout(sov[rv0_t1_i1_rte_lq_offset ]), + .din(rv0_t1_i1_rte_lq_d), + .dout(rv0_t1_i1_rte_lq_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t1_i1_rte_sq_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i1_rte_sq_offset ]), + .scout(sov[rv0_t1_i1_rte_sq_offset ]), + .din(rv0_t1_i1_rte_sq_d), + .dout(rv0_t1_i1_rte_sq_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t1_i1_rte_fx0_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i1_rte_fx0_offset ]), + .scout(sov[rv0_t1_i1_rte_fx0_offset ]), + .din(rv0_t1_i1_rte_fx0_d), + .dout(rv0_t1_i1_rte_fx0_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t1_i1_rte_fx1_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i1_rte_fx1_offset ]), + .scout(sov[rv0_t1_i1_rte_fx1_offset ]), + .din(rv0_t1_i1_rte_fx1_d), + .dout(rv0_t1_i1_rte_fx1_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t1_i1_rte_axu0_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i1_rte_axu0_offset ]), + .scout(sov[rv0_t1_i1_rte_axu0_offset ]), + .din(rv0_t1_i1_rte_axu0_d), + .dout(rv0_t1_i1_rte_axu0_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t1_i1_rte_axu1_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i1_rte_axu1_offset ]), + .scout(sov[rv0_t1_i1_rte_axu1_offset ]), + .din(rv0_t1_i1_rte_axu1_d), + .dout(rv0_t1_i1_rte_axu1_q) + ); + + + tri_rlmreg_p #(.WIDTH(32), .INIT(0)) rv0_t1_i1_instr_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i1_instr_offset :rv0_t1_i1_instr_offset + 31 ]), + .scout(sov[rv0_t1_i1_instr_offset :rv0_t1_i1_instr_offset + 31 ]), + .din(rv0_t1_i1_instr_d), + .dout(rv0_t1_i1_instr_q) + ); + + + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) rv0_t1_i1_ifar_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i1_ifar_offset :rv0_t1_i1_ifar_offset + `EFF_IFAR_WIDTH - 1 ]), + .scout(sov[rv0_t1_i1_ifar_offset :rv0_t1_i1_ifar_offset + `EFF_IFAR_WIDTH - 1 ]), + .din(rv0_t1_i1_ifar_d), + .dout(rv0_t1_i1_ifar_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t1_i1_ucode_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i1_ucode_offset :rv0_t1_i1_ucode_offset + 3 - 1 ]), + .scout(sov[rv0_t1_i1_ucode_offset :rv0_t1_i1_ucode_offset + 3 - 1 ]), + .din(rv0_t1_i1_ucode_d), + .dout(rv0_t1_i1_ucode_q) + ); + + + + + tri_rlmreg_p #(.WIDTH(`UCODE_ENTRIES_ENC), .INIT(0)) rv0_t1_i1_ucode_cnt_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i1_ucode_cnt_offset :rv0_t1_i1_ucode_cnt_offset + `UCODE_ENTRIES_ENC - 1 ]), + .scout(sov[rv0_t1_i1_ucode_cnt_offset :rv0_t1_i1_ucode_cnt_offset + `UCODE_ENTRIES_ENC - 1 ]), + .din(rv0_t1_i1_ucode_cnt_d), + .dout(rv0_t1_i1_ucode_cnt_q) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) rv0_t1_i1_itag_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i1_itag_offset :rv0_t1_i1_itag_offset + `ITAG_SIZE_ENC - 1 ]), + .scout(sov[rv0_t1_i1_itag_offset :rv0_t1_i1_itag_offset + `ITAG_SIZE_ENC - 1 ]), + .din(rv0_t1_i1_itag_d), + .dout(rv0_t1_i1_itag_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t1_i1_ord_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i1_ord_offset ]), + .scout(sov[rv0_t1_i1_ord_offset ]), + .din(rv0_t1_i1_ord_d), + .dout(rv0_t1_i1_ord_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t1_i1_cord_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i1_cord_offset ]), + .scout(sov[rv0_t1_i1_cord_offset ]), + .din(rv0_t1_i1_cord_d), + .dout(rv0_t1_i1_cord_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t1_i1_spec_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i1_spec_offset ]), + .scout(sov[rv0_t1_i1_spec_offset ]), + .din(rv0_t1_i1_spec_d), + .dout(rv0_t1_i1_spec_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t1_i1_t1_v_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i1_t1_v_offset ]), + .scout(sov[rv0_t1_i1_t1_v_offset ]), + .din(rv0_t1_i1_t1_v_d), + .dout(rv0_t1_i1_t1_v_q) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) rv0_t1_i1_t1_p_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i1_t1_p_offset :rv0_t1_i1_t1_p_offset + `GPR_POOL_ENC - 1 ]), + .scout(sov[rv0_t1_i1_t1_p_offset :rv0_t1_i1_t1_p_offset + `GPR_POOL_ENC - 1 ]), + .din(rv0_t1_i1_t1_p_d), + .dout(rv0_t1_i1_t1_p_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t1_i1_t1_t_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i1_t1_t_offset :rv0_t1_i1_t1_t_offset + 3 - 1 ]), + .scout(sov[rv0_t1_i1_t1_t_offset :rv0_t1_i1_t1_t_offset + 3 - 1 ]), + .din(rv0_t1_i1_t1_t_d), + .dout(rv0_t1_i1_t1_t_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t1_i1_t2_v_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i1_t2_v_offset ]), + .scout(sov[rv0_t1_i1_t2_v_offset ]), + .din(rv0_t1_i1_t2_v_d), + .dout(rv0_t1_i1_t2_v_q) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) rv0_t1_i1_t2_p_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i1_t2_p_offset :rv0_t1_i1_t2_p_offset + `GPR_POOL_ENC - 1 ]), + .scout(sov[rv0_t1_i1_t2_p_offset :rv0_t1_i1_t2_p_offset + `GPR_POOL_ENC - 1 ]), + .din(rv0_t1_i1_t2_p_d), + .dout(rv0_t1_i1_t2_p_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t1_i1_t2_t_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i1_t2_t_offset :rv0_t1_i1_t2_t_offset + 3 - 1 ]), + .scout(sov[rv0_t1_i1_t2_t_offset :rv0_t1_i1_t2_t_offset + 3 - 1 ]), + .din(rv0_t1_i1_t2_t_d), + .dout(rv0_t1_i1_t2_t_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t1_i1_t3_v_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i1_t3_v_offset ]), + .scout(sov[rv0_t1_i1_t3_v_offset ]), + .din(rv0_t1_i1_t3_v_d), + .dout(rv0_t1_i1_t3_v_q) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) rv0_t1_i1_t3_p_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i1_t3_p_offset :rv0_t1_i1_t3_p_offset + `GPR_POOL_ENC - 1 ]), + .scout(sov[rv0_t1_i1_t3_p_offset :rv0_t1_i1_t3_p_offset + `GPR_POOL_ENC - 1 ]), + .din(rv0_t1_i1_t3_p_d), + .dout(rv0_t1_i1_t3_p_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t1_i1_t3_t_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i1_t3_t_offset :rv0_t1_i1_t3_t_offset + 3 - 1 ]), + .scout(sov[rv0_t1_i1_t3_t_offset :rv0_t1_i1_t3_t_offset + 3 - 1 ]), + .din(rv0_t1_i1_t3_t_d), + .dout(rv0_t1_i1_t3_t_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t1_i1_s1_v_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i1_s1_v_offset ]), + .scout(sov[rv0_t1_i1_s1_v_offset ]), + .din(rv0_t1_i1_s1_v_d), + .dout(rv0_t1_i1_s1_v_q) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) rv0_t1_i1_s1_p_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i1_s1_p_offset :rv0_t1_i1_s1_p_offset + `GPR_POOL_ENC - 1 ]), + .scout(sov[rv0_t1_i1_s1_p_offset :rv0_t1_i1_s1_p_offset + `GPR_POOL_ENC - 1 ]), + .din(rv0_t1_i1_s1_p_d), + .dout(rv0_t1_i1_s1_p_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t1_i1_s1_t_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i1_s1_t_offset :rv0_t1_i1_s1_t_offset + 3 - 1 ]), + .scout(sov[rv0_t1_i1_s1_t_offset :rv0_t1_i1_s1_t_offset + 3 - 1 ]), + .din(rv0_t1_i1_s1_t_d), + .dout(rv0_t1_i1_s1_t_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t1_i1_s2_v_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i1_s2_v_offset ]), + .scout(sov[rv0_t1_i1_s2_v_offset ]), + .din(rv0_t1_i1_s2_v_d), + .dout(rv0_t1_i1_s2_v_q) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) rv0_t1_i1_s2_p_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i1_s2_p_offset :rv0_t1_i1_s2_p_offset + `GPR_POOL_ENC - 1 ]), + .scout(sov[rv0_t1_i1_s2_p_offset :rv0_t1_i1_s2_p_offset + `GPR_POOL_ENC - 1 ]), + .din(rv0_t1_i1_s2_p_d), + .dout(rv0_t1_i1_s2_p_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t1_i1_s2_t_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i1_s2_t_offset :rv0_t1_i1_s2_t_offset + 3 - 1 ]), + .scout(sov[rv0_t1_i1_s2_t_offset :rv0_t1_i1_s2_t_offset + 3 - 1 ]), + .din(rv0_t1_i1_s2_t_d), + .dout(rv0_t1_i1_s2_t_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t1_i1_s3_v_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i1_s3_v_offset ]), + .scout(sov[rv0_t1_i1_s3_v_offset ]), + .din(rv0_t1_i1_s3_v_d), + .dout(rv0_t1_i1_s3_v_q) + ); + + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) rv0_t1_i1_s3_p_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i1_s3_p_offset :rv0_t1_i1_s3_p_offset + `GPR_POOL_ENC - 1 ]), + .scout(sov[rv0_t1_i1_s3_p_offset :rv0_t1_i1_s3_p_offset + `GPR_POOL_ENC - 1 ]), + .din(rv0_t1_i1_s3_p_d), + .dout(rv0_t1_i1_s3_p_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t1_i1_s3_t_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i1_s3_t_offset :rv0_t1_i1_s3_t_offset + 3 - 1 ]), + .scout(sov[rv0_t1_i1_s3_t_offset :rv0_t1_i1_s3_t_offset + 3 - 1 ]), + .din(rv0_t1_i1_s3_t_d), + .dout(rv0_t1_i1_s3_t_q) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) rv0_t1_i1_s1_itag_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i1_s1_itag_offset :rv0_t1_i1_s1_itag_offset + `ITAG_SIZE_ENC - 1 ]), + .scout(sov[rv0_t1_i1_s1_itag_offset :rv0_t1_i1_s1_itag_offset + `ITAG_SIZE_ENC - 1 ]), + .din(rv0_t1_i1_s1_itag_d), + .dout(rv0_t1_i1_s1_itag_q) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) rv0_t1_i1_s2_itag_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i1_s2_itag_offset :rv0_t1_i1_s2_itag_offset + `ITAG_SIZE_ENC - 1 ]), + .scout(sov[rv0_t1_i1_s2_itag_offset :rv0_t1_i1_s2_itag_offset + `ITAG_SIZE_ENC - 1 ]), + .din(rv0_t1_i1_s2_itag_d), + .dout(rv0_t1_i1_s2_itag_q) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) rv0_t1_i1_s3_itag_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i1_s3_itag_offset :rv0_t1_i1_s3_itag_offset + `ITAG_SIZE_ENC - 1 ]), + .scout(sov[rv0_t1_i1_s3_itag_offset :rv0_t1_i1_s3_itag_offset + `ITAG_SIZE_ENC - 1 ]), + .din(rv0_t1_i1_s3_itag_d), + .dout(rv0_t1_i1_s3_itag_q) + ); + + tri_rlmlatch_p #(.INIT(0)) + rv0_t1_i1_s1_dep_hit_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i1_s1_dep_hit_offset ]), + .scout(sov[rv0_t1_i1_s1_dep_hit_offset ]), + .din(rv0_t1_i1_s1_dep_hit_d), + .dout(rv0_t1_i1_s1_dep_hit_q) + ); + + tri_rlmlatch_p #(.INIT(0)) + rv0_t1_i1_s2_dep_hit_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i1_s2_dep_hit_offset ]), + .scout(sov[rv0_t1_i1_s2_dep_hit_offset ]), + .din(rv0_t1_i1_s2_dep_hit_d), + .dout(rv0_t1_i1_s2_dep_hit_q) + ); + + tri_rlmlatch_p #(.INIT(0)) + rv0_t1_i1_s3_dep_hit_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i1_s3_dep_hit_offset ]), + .scout(sov[rv0_t1_i1_s3_dep_hit_offset ]), + .din(rv0_t1_i1_s3_dep_hit_d), + .dout(rv0_t1_i1_s3_dep_hit_q) + ); + + + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) rv0_t1_i1_ilat_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i1_ilat_offset :rv0_t1_i1_ilat_offset + 4 - 1 ]), + .scout(sov[rv0_t1_i1_ilat_offset :rv0_t1_i1_ilat_offset + 4 - 1 ]), + .din(rv0_t1_i1_ilat_d), + .dout(rv0_t1_i1_ilat_q) + ); + + + tri_rlmreg_p #(.WIDTH(`G_BRANCH_LEN), .INIT(0)) rv0_t1_i1_branch_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i1_branch_offset :rv0_t1_i1_branch_offset + `G_BRANCH_LEN - 1 ]), + .scout(sov[rv0_t1_i1_branch_offset :rv0_t1_i1_branch_offset + `G_BRANCH_LEN - 1 ]), + .din(rv0_t1_i1_branch_d), + .dout(rv0_t1_i1_branch_q) + ); + + tri_rlmlatch_p #(.INIT(0)) rv0_t1_i1_isLoad_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i1_isLoad_offset ]), + .scout(sov[rv0_t1_i1_isLoad_offset ]), + .din(rv0_t1_i1_isLoad_d), + .dout(rv0_t1_i1_isLoad_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) rv0_t1_i1_isStore_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i1_isStore_offset ]), + .scout(sov[rv0_t1_i1_isStore_offset ]), + .din(rv0_t1_i1_isStore_d), + .dout(rv0_t1_i1_isStore_q) + ); + + assign rv0_t1_i1_spare_d = 4'b0000; + + + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) rv0_t1_i1_spare_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu6_t1_i1_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_t1_i1_spare_offset :rv0_t1_i1_spare_offset + 4 - 1 ]), + .scout(sov[rv0_t1_i1_spare_offset :rv0_t1_i1_spare_offset + 4 - 1 ]), + .din(rv0_t1_i1_spare_d), + .dout(rv0_t1_i1_spare_q) + ); + + + + + +`endif + + + + //------------------------------------------------------------------------------------------------------------ + // // Misc + //------------------------------------------------------------------------------------------------------------ + + + //------------------------------------------------------------------------------------------------------------ + // Dep Hit latches (replicated per unit) + //------------------------------------------------------------------------------------------------------------ + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) + rv0_instr_i0_flushed_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_instr_i0_flushed_offset:rv0_instr_i0_flushed_offset + `THREADS - 1]), + .scout(sov[rv0_instr_i0_flushed_offset:rv0_instr_i0_flushed_offset + `THREADS - 1]), + .din(rv0_instr_i0_flushed_d), + .dout(rv0_instr_i0_flushed_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) + rv0_instr_i1_flushed_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv0_instr_i1_flushed_offset:rv0_instr_i1_flushed_offset + `THREADS - 1]), + .scout(sov[rv0_instr_i1_flushed_offset:rv0_instr_i1_flushed_offset + `THREADS - 1]), + .din(rv0_instr_i1_flushed_d), + .dout(rv0_instr_i1_flushed_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) + rv1_lq_instr_i0_vld_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv1_lq_instr_i0_vld_offset:rv1_lq_instr_i0_vld_offset + `THREADS - 1]), + .scout(sov[rv1_lq_instr_i0_vld_offset:rv1_lq_instr_i0_vld_offset + `THREADS - 1]), + .din(rv1_lq_instr_i0_vld_d), + .dout(rv1_lq_instr_i0_vld_q) + ); + + + + tri_rlmlatch_p #(.INIT(0)) +rv1_lq_instr_i0_rte_lq_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv1_lq_instr_i0_rte_lq_offset]), + .scout(sov[rv1_lq_instr_i0_rte_lq_offset]), + .din(rv1_lq_instr_i0_rte_lq_d), + .dout(rv1_lq_instr_i0_rte_lq_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) +rv1_lq_instr_i0_rte_sq_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv1_lq_instr_i0_rte_sq_offset]), + .scout(sov[rv1_lq_instr_i0_rte_sq_offset]), + .din(rv1_lq_instr_i0_rte_sq_d), + .dout(rv1_lq_instr_i0_rte_sq_q) + ); + + tri_rlmlatch_p #(.INIT(0)) + rv1_lq_instr_i0_ucode_preissue_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv1_lq_instr_i0_ucode_preissue_offset]), + .scout(sov[rv1_lq_instr_i0_ucode_preissue_offset]), + .din(rv1_lq_instr_i0_ucode_preissue_d), + .dout(rv1_lq_instr_i0_ucode_preissue_q) + ); + tri_rlmlatch_p #(.INIT(0)) + rv1_lq_instr_i0_2ucode_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv1_lq_instr_i0_2ucode_offset]), + .scout(sov[rv1_lq_instr_i0_2ucode_offset]), + .din(rv1_lq_instr_i0_2ucode_d), + .dout(rv1_lq_instr_i0_2ucode_q) + ); + + tri_rlmreg_p #(.INIT(0), .WIDTH(`UCODE_ENTRIES_ENC)) + rv1_lq_instr_i0_ucode_cnt_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv1_lq_instr_i0_ucode_cnt_offset:rv1_lq_instr_i0_ucode_cnt_offset+`UCODE_ENTRIES_ENC-1]), + .scout(sov[rv1_lq_instr_i0_ucode_cnt_offset:rv1_lq_instr_i0_ucode_cnt_offset+`UCODE_ENTRIES_ENC-1]), + .din(rv1_lq_instr_i0_ucode_cnt_d), + .dout(rv1_lq_instr_i0_ucode_cnt_q) + ); + + tri_rlmreg_p #(.INIT(0), .WIDTH(3)) + rv1_lq_instr_i0_s3_t_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv1_lq_instr_i0_s3_t_offset:rv1_lq_instr_i0_s3_t_offset+3-1]), + .scout(sov[rv1_lq_instr_i0_s3_t_offset:rv1_lq_instr_i0_s3_t_offset+3-1]), + .din(rv1_lq_instr_i0_s3_t_d), + .dout(rv1_lq_instr_i0_s3_t_q) + ); + + tri_rlmlatch_p #(.INIT(0)) + rv1_lq_instr_i0_isLoad_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv1_lq_instr_i0_isLoad_offset]), + .scout(sov[rv1_lq_instr_i0_isLoad_offset]), + .din(rv1_lq_instr_i0_isLoad_d), + .dout(rv1_lq_instr_i0_isLoad_q) + ); + tri_rlmlatch_p #(.INIT(0)) + rv1_lq_instr_i0_isStore_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv1_lq_instr_i0_isStore_offset]), + .scout(sov[rv1_lq_instr_i0_isStore_offset]), + .din(rv1_lq_instr_i0_isStore_d), + .dout(rv1_lq_instr_i0_isStore_q) + ); + + tri_rlmreg_p #(.INIT(0), .WIDTH(`ITAG_SIZE_ENC)) + rv1_lq_instr_i0_itag_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv1_lq_instr_i0_itag_offset:rv1_lq_instr_i0_itag_offset+`ITAG_SIZE_ENC-1]), + .scout(sov[rv1_lq_instr_i0_itag_offset:rv1_lq_instr_i0_itag_offset+`ITAG_SIZE_ENC-1]), + .din(rv1_lq_instr_i0_itag_d), + .dout(rv1_lq_instr_i0_itag_q) + ); + + tri_rlmreg_p #(.INIT(0), .WIDTH(`PF_IAR_BITS)) + rv1_lq_instr_i0_ifar_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv1_lq_instr_i0_ifar_offset:rv1_lq_instr_i0_ifar_offset+`PF_IAR_BITS-1]), + .scout(sov[rv1_lq_instr_i0_ifar_offset:rv1_lq_instr_i0_ifar_offset+`PF_IAR_BITS-1]), + .din(rv1_lq_instr_i0_ifar_d), + .dout(rv1_lq_instr_i0_ifar_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) +rv1_lq_instr_i1_vld_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv1_lq_instr_i1_vld_offset:rv1_lq_instr_i1_vld_offset + `THREADS - 1]), + .scout(sov[rv1_lq_instr_i1_vld_offset:rv1_lq_instr_i1_vld_offset + `THREADS - 1]), + .din(rv1_lq_instr_i1_vld_d), + .dout(rv1_lq_instr_i1_vld_q) + ); + + + + tri_rlmlatch_p #(.INIT(0)) + rv1_lq_instr_i1_rte_lq_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv1_lq_instr_i1_rte_lq_offset]), + .scout(sov[rv1_lq_instr_i1_rte_lq_offset]), + .din(rv1_lq_instr_i1_rte_lq_d), + .dout(rv1_lq_instr_i1_rte_lq_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) +rv1_lq_instr_i1_rte_sq_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv1_lq_instr_i1_rte_sq_offset]), + .scout(sov[rv1_lq_instr_i1_rte_sq_offset]), + .din(rv1_lq_instr_i1_rte_sq_d), + .dout(rv1_lq_instr_i1_rte_sq_q) + ); + + tri_rlmlatch_p #(.INIT(0)) + rv1_lq_instr_i1_ucode_preissue_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv1_lq_instr_i1_ucode_preissue_offset]), + .scout(sov[rv1_lq_instr_i1_ucode_preissue_offset]), + .din(rv1_lq_instr_i1_ucode_preissue_d), + .dout(rv1_lq_instr_i1_ucode_preissue_q) + ); + tri_rlmlatch_p #(.INIT(0)) + rv1_lq_instr_i1_2ucode_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv1_lq_instr_i1_2ucode_offset]), + .scout(sov[rv1_lq_instr_i1_2ucode_offset]), + .din(rv1_lq_instr_i1_2ucode_d), + .dout(rv1_lq_instr_i1_2ucode_q) + ); + + tri_rlmreg_p #(.INIT(0), .WIDTH(`UCODE_ENTRIES_ENC)) + rv1_lq_instr_i1_ucode_cnt_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv1_lq_instr_i1_ucode_cnt_offset:rv1_lq_instr_i1_ucode_cnt_offset+`UCODE_ENTRIES_ENC-1]), + .scout(sov[rv1_lq_instr_i1_ucode_cnt_offset:rv1_lq_instr_i1_ucode_cnt_offset+`UCODE_ENTRIES_ENC-1]), + .din(rv1_lq_instr_i1_ucode_cnt_d), + .dout(rv1_lq_instr_i1_ucode_cnt_q) + ); + + tri_rlmreg_p #(.INIT(0), .WIDTH(3)) + rv1_lq_instr_i1_s3_t_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv1_lq_instr_i1_s3_t_offset:rv1_lq_instr_i1_s3_t_offset+3-1]), + .scout(sov[rv1_lq_instr_i1_s3_t_offset:rv1_lq_instr_i1_s3_t_offset+3-1]), + .din(rv1_lq_instr_i1_s3_t_d), + .dout(rv1_lq_instr_i1_s3_t_q) + ); + + tri_rlmlatch_p #(.INIT(0)) + rv1_lq_instr_i1_isLoad_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv1_lq_instr_i1_isLoad_offset]), + .scout(sov[rv1_lq_instr_i1_isLoad_offset]), + .din(rv1_lq_instr_i1_isLoad_d), + .dout(rv1_lq_instr_i1_isLoad_q) + ); + tri_rlmlatch_p #(.INIT(0)) + rv1_lq_instr_i1_isStore_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv1_lq_instr_i1_isStore_offset]), + .scout(sov[rv1_lq_instr_i1_isStore_offset]), + .din(rv1_lq_instr_i1_isStore_d), + .dout(rv1_lq_instr_i1_isStore_q) + ); + + tri_rlmreg_p #(.INIT(0), .WIDTH(`ITAG_SIZE_ENC)) + rv1_lq_instr_i1_itag_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv1_lq_instr_i1_itag_offset:rv1_lq_instr_i1_itag_offset+`ITAG_SIZE_ENC-1]), + .scout(sov[rv1_lq_instr_i1_itag_offset:rv1_lq_instr_i1_itag_offset+`ITAG_SIZE_ENC-1]), + .din(rv1_lq_instr_i1_itag_d), + .dout(rv1_lq_instr_i1_itag_q) + ); + + tri_rlmreg_p #(.INIT(0), .WIDTH(`PF_IAR_BITS)) + rv1_lq_instr_i1_ifar_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rv1_lq_instr_i1_ifar_offset:rv1_lq_instr_i1_ifar_offset+`PF_IAR_BITS-1]), + .scout(sov[rv1_lq_instr_i1_ifar_offset:rv1_lq_instr_i1_ifar_offset+`PF_IAR_BITS-1]), + .din(rv1_lq_instr_i1_ifar_d), + .dout(rv1_lq_instr_i1_ifar_q) + ); + + + //--------------------------------------------------------------------- + // Scan + //--------------------------------------------------------------------- + assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in}; + assign scan_out = sov[0]; + + //----------------------------------------------- + // pervasive + //----------------------------------------------- + + + tri_plat #(.WIDTH(2)) perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(ccflush_dc), + .din({func_sl_thold_1,sg_1}), + .q({func_sl_thold_0,sg_0}) + ); + + + tri_lcbor perv_lcbor( + .clkoff_b(clkoff_b), + .thold(func_sl_thold_0), + .sg(sg_0), + .act_dis(act_dis), + .force_t(force_t), + .thold_b(func_sl_thold_0_b) + ); + + +endmodule diff --git a/dev/verilog/work/rv_fx0_rvs.v b/dev/verilog/work/rv_fx0_rvs.v new file mode 100755 index 0000000..b6abd12 --- /dev/null +++ b/dev/verilog/work/rv_fx0_rvs.v @@ -0,0 +1,1078 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//----------------------------------------------------------------------------------------------------- +// Title: rv_fx0_rvs.vhdl +// Desc: LQ Reservation Station +// +//----------------------------------------------------------------------------------------------------- + +module rv_fx0_rvs( +`include "tri_a2o.vh" + + //------------------------------------------------------------------------------------------------------------ + // Instructions from RV_DEP + //------------------------------------------------------------------------------------------------------------ + input [0:`THREADS-1] rv0_instr_i0_vld, + input rv0_instr_i0_rte_fx0, + input [0:`THREADS-1] rv0_instr_i1_vld, + input rv0_instr_i1_rte_fx0, + + input [0:31] rv0_instr_i0_instr, + input [62-`EFF_IFAR_WIDTH:61] rv0_instr_i0_ifar, + input [0:2] rv0_instr_i0_ucode, + input [0:`UCODE_ENTRIES_ENC-1] rv0_instr_i0_ucode_cnt, + input [0:`ITAG_SIZE_ENC-1] rv0_instr_i0_itag, + input rv0_instr_i0_ord, + input rv0_instr_i0_cord, + input rv0_instr_i0_t1_v, + input [0:`GPR_POOL_ENC-1] rv0_instr_i0_t1_p, + input [0:2] rv0_instr_i0_t1_t, + input rv0_instr_i0_t2_v, + input [0:`GPR_POOL_ENC-1] rv0_instr_i0_t2_p, + input [0:2] rv0_instr_i0_t2_t, + input rv0_instr_i0_t3_v, + input [0:`GPR_POOL_ENC-1] rv0_instr_i0_t3_p, + input [0:2] rv0_instr_i0_t3_t, + input rv0_instr_i0_s1_v, + input [0:`GPR_POOL_ENC-1] rv0_instr_i0_s1_p, + input [0:2] rv0_instr_i0_s1_t, + input rv0_instr_i0_s2_v, + input [0:`GPR_POOL_ENC-1] rv0_instr_i0_s2_p, + input [0:2] rv0_instr_i0_s2_t, + input rv0_instr_i0_s3_v, + input [0:`GPR_POOL_ENC-1] rv0_instr_i0_s3_p, + input [0:2] rv0_instr_i0_s3_t, + input [0:3] rv0_instr_i0_ilat, + input [0:3] rv0_instr_i0_spare, + input rv0_instr_i0_is_brick, + input [0:2] rv0_instr_i0_brick, + input [0:`G_BRANCH_LEN-1] rv0_instr_i0_branch, + + input [0:31] rv0_instr_i1_instr, + input [62-`EFF_IFAR_WIDTH:61] rv0_instr_i1_ifar, + input [0:2] rv0_instr_i1_ucode, + input [0:`UCODE_ENTRIES_ENC-1] rv0_instr_i1_ucode_cnt, + input [0:`ITAG_SIZE_ENC-1] rv0_instr_i1_itag, + input rv0_instr_i1_ord, + input rv0_instr_i1_cord, + input rv0_instr_i1_t1_v, + input [0:`GPR_POOL_ENC-1] rv0_instr_i1_t1_p, + input [0:2] rv0_instr_i1_t1_t, + input rv0_instr_i1_t2_v, + input [0:`GPR_POOL_ENC-1] rv0_instr_i1_t2_p, + input [0:2] rv0_instr_i1_t2_t, + input rv0_instr_i1_t3_v, + input [0:`GPR_POOL_ENC-1] rv0_instr_i1_t3_p, + input [0:2] rv0_instr_i1_t3_t, + input rv0_instr_i1_s1_v, + input [0:`GPR_POOL_ENC-1] rv0_instr_i1_s1_p, + input [0:2] rv0_instr_i1_s1_t, + input rv0_instr_i1_s2_v, + input [0:`GPR_POOL_ENC-1] rv0_instr_i1_s2_p, + input [0:2] rv0_instr_i1_s2_t, + input rv0_instr_i1_s3_v, + input [0:`GPR_POOL_ENC-1] rv0_instr_i1_s3_p, + input [0:2] rv0_instr_i1_s3_t, + input [0:3] rv0_instr_i1_ilat, + input [0:3] rv0_instr_i1_spare, + input rv0_instr_i1_is_brick, + input [0:2] rv0_instr_i1_brick, + input [0:`G_BRANCH_LEN-1] rv0_instr_i1_branch, + + input rv0_instr_i0_s1_dep_hit, + input [0:`ITAG_SIZE_ENC-1] rv0_instr_i0_s1_itag, + input rv0_instr_i0_s2_dep_hit, + input [0:`ITAG_SIZE_ENC-1] rv0_instr_i0_s2_itag, + input rv0_instr_i0_s3_dep_hit, + input [0:`ITAG_SIZE_ENC-1] rv0_instr_i0_s3_itag, + + input rv0_instr_i1_s1_dep_hit, + input [0:`ITAG_SIZE_ENC-1] rv0_instr_i1_s1_itag, + input rv0_instr_i1_s2_dep_hit, + input [0:`ITAG_SIZE_ENC-1] rv0_instr_i1_s2_itag, + input rv0_instr_i1_s3_dep_hit, + input [0:`ITAG_SIZE_ENC-1] rv0_instr_i1_s3_itag, + + //------------------------------------------------------------------------------------------------------------ + // Credit Interface with IU + //------------------------------------------------------------------------------------------------------------ + output [0:`THREADS-1] rv_iu_fx0_credit_free, + + //------------------------------------------------------------------------------------------------------------ + // Machine zap interface + //------------------------------------------------------------------------------------------------------------ + input [0:`THREADS-1] cp_flush, + input [0:`THREADS*`ITAG_SIZE_ENC-1] cp_next_itag, + + //------------------------------------------------------------------------------------------------------------ + // Interface to FX0 + //------------------------------------------------------------------------------------------------------------ + output [0:`THREADS-1] rv_byp_fx0_vld, + output [0:`ITAG_SIZE_ENC-1] rv_byp_fx0_itag, + output rv_byp_fx0_ord, + output rv_byp_fx0_t1_v, + output [0:2] rv_byp_fx0_t1_t, + output rv_byp_fx0_t2_v, + output [0:2] rv_byp_fx0_t2_t, + output rv_byp_fx0_t3_v, + output [0:2] rv_byp_fx0_t3_t, + output [0:2] rv_byp_fx0_s1_t, + output [0:2] rv_byp_fx0_s2_t, + output [0:2] rv_byp_fx0_s3_t, + output [0:3] rv_byp_fx0_ilat, + + output [0:`THREADS-1] rv_fx0_vld, + output rv_fx0_s1_v, + output [0:`GPR_POOL_ENC-1] rv_fx0_s1_p, + output rv_fx0_s2_v, + output [0:`GPR_POOL_ENC-1] rv_fx0_s2_p, + output rv_fx0_s3_v, + output [0:`GPR_POOL_ENC-1] rv_fx0_s3_p, + + output [0:`ITAG_SIZE_ENC-1] rv_fx0_ex0_itag, + output [0:31] rv_fx0_ex0_instr, + output [62-`EFF_IFAR_WIDTH:61] rv_fx0_ex0_ifar, + output [0:2] rv_fx0_ex0_ucode, + output [0:`UCODE_ENTRIES_ENC-1] rv_fx0_ex0_ucode_cnt, + output rv_fx0_ex0_ord, + output rv_fx0_ex0_t1_v, + output [0:`GPR_POOL_ENC-1] rv_fx0_ex0_t1_p, + output [0:2] rv_fx0_ex0_t1_t, + output rv_fx0_ex0_t2_v, + output [0:`GPR_POOL_ENC-1] rv_fx0_ex0_t2_p, + output [0:2] rv_fx0_ex0_t2_t, + output rv_fx0_ex0_t3_v, + output [0:`GPR_POOL_ENC-1] rv_fx0_ex0_t3_p, + output [0:2] rv_fx0_ex0_t3_t, + output rv_fx0_ex0_s1_v, + output rv_fx0_ex0_s2_v, + output [0:2] rv_fx0_ex0_s2_t, + output rv_fx0_ex0_s3_v, + output [0:2] rv_fx0_ex0_s3_t, + output [0:`G_BRANCH_LEN-1] rv_fx0_ex0_branch, + + output [0:`ITAG_SIZE_ENC-1] rv_byp_fx0_s1_itag, + output [0:`ITAG_SIZE_ENC-1] rv_byp_fx0_s2_itag, + output [0:`ITAG_SIZE_ENC-1] rv_byp_fx0_s3_itag, + output rv_byp_fx0_ex0_is_brick, + + //------------------------------------------------------------------------------------------------------------ + // RV Release bus + //------------------------------------------------------------------------------------------------------------ + + input fx0_rv_ex2_s1_abort, + input fx0_rv_ex2_s2_abort, + input fx0_rv_ex2_s3_abort, + + + input fx0_rv_itag_abort, + input fx1_rv_itag_abort, + input lq_rv_ext_itag0_abort, + input lq_rv_ext_itag1_abort, + input axu1_rv_ext_itag_abort, + input axu0_rv_ext_itag_abort, + + input [0:`THREADS-1] fx0_rv_itag_vld, + input [0:`ITAG_SIZE_ENC-1] fx0_rv_itag, + + input [0:`THREADS-1] fx1_rv_itag_vld, + input [0:`ITAG_SIZE_ENC-1] fx1_rv_itag, + + input [0:`THREADS-1] axu0_rv_ext_itag_vld, + input [0:`ITAG_SIZE_ENC-1] axu0_rv_ext_itag, + + input [0:`THREADS-1] axu1_rv_ext_itag_vld, + input [0:`ITAG_SIZE_ENC-1] axu1_rv_ext_itag, + + input [0:`THREADS-1] lq_rv_ext_itag0_vld, + input [0:`ITAG_SIZE_ENC-1] lq_rv_ext_itag0, + + input [0:`THREADS-1] lq_rv_itag1_vld, + input [0:`ITAG_SIZE_ENC-1] lq_rv_itag1, + input lq_rv_itag1_restart, + input lq_rv_itag1_hold, + input [0:`THREADS-1] lq_rv_ext_itag1_vld, + input [0:`ITAG_SIZE_ENC-1] lq_rv_ext_itag1, + + input [0:`THREADS-1] lq_rv_ext_itag2_vld, + input [0:`ITAG_SIZE_ENC-1] lq_rv_ext_itag2, + + input [0:`THREADS-1] lq_rv_clr_hold, + + input [0:`THREADS-1] fx0_rv_ord_complete, + input fx0_rv_hold_all, + output [0:`THREADS-1] fx0_rv_ord_tid, + + output [0:`THREADS-1] rv_byp_fx0_ilat0_vld, + output [0:`THREADS-1] rv_byp_fx0_ilat1_vld, + + input [0:`THREADS-1] rv1_fx1_ilat0_vld, + input [0:`ITAG_SIZE_ENC-1] rv1_fx1_ilat0_itag, + output [0:`THREADS-1] rv1_fx0_ilat0_vld, + output [0:`ITAG_SIZE_ENC-1] rv1_fx0_ilat0_itag, + + //------------------------------------------------------------------------------------------------------------ + // Pervasive + //------------------------------------------------------------------------------------------------------------ + output [0:8*`THREADS-1] fx0_rvs_perf_bus, + output [0:31] fx0_rvs_dbg_bus, + inout vdd, + inout gnd, + (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) // nclk + input [0:`NCLK_WIDTH-1] nclk, + input func_sl_thold_1, + input sg_1, + input clkoff_b, + input act_dis, + input ccflush_dc, + input d_mode, + input delay_lclkr, + input mpw1_b, + input mpw2_b, + input scan_in, + + output scan_out + + + ); + + parameter num_itag_busses_g = 7; + + + //------------------------------------------------------------------------------------------------------------ + // RV FX0 RVS INSTR ISSUE + //------------------------------------------------------------------------------------------------------------ + parameter rvfx0_ex0_start = 0; + parameter rvfx0_instr_start = rvfx0_ex0_start; + parameter rvfx0_instr_stop = (rvfx0_instr_start + (32)) - 1; + parameter rvfx0_ifar_start = rvfx0_instr_stop + 1; + parameter rvfx0_ifar_stop = (rvfx0_ifar_start + (`EFF_IFAR_WIDTH)) - 1; + parameter rvfx0_ucode_start = rvfx0_ifar_stop + 1; + parameter rvfx0_ucode_stop = (rvfx0_ucode_start + (3)) - 1; + parameter rvfx0_ucode_cnt_start = rvfx0_ucode_stop + 1; + parameter rvfx0_ucode_cnt_stop = (rvfx0_ucode_cnt_start + (`UCODE_ENTRIES_ENC)) - 1; + parameter rvfx0_t1_p_start = rvfx0_ucode_cnt_stop + 1; + parameter rvfx0_t1_p_stop = (rvfx0_t1_p_start + (`GPR_POOL_ENC)) - 1; + parameter rvfx0_t2_p_start = rvfx0_t1_p_stop + 1; + parameter rvfx0_t2_p_stop = (rvfx0_t2_p_start + (`GPR_POOL_ENC)) - 1; + parameter rvfx0_t3_p_start = rvfx0_t2_p_stop + 1; + parameter rvfx0_t3_p_stop = (rvfx0_t3_p_start + (`GPR_POOL_ENC)) - 1; + parameter rvfx0_branch_start = rvfx0_t3_p_stop + 1; + parameter rvfx0_branch_stop = (rvfx0_branch_start + (`G_BRANCH_LEN)) - 1; + parameter rvfx0_spare_start = rvfx0_branch_stop + 1; + parameter rvfx0_spare_stop = (rvfx0_spare_start + (4)) - 1; + + parameter rvfx0_ex0_end = rvfx0_spare_stop; + + parameter rvfx0_ex0_size = rvfx0_ex0_end + 1; + + + parameter rvfx0_start = 0; + parameter rvfx0_t1_v_start = rvfx0_start; + parameter rvfx0_t1_v_stop = (rvfx0_t1_v_start + (1)) - 1; + parameter rvfx0_t1_t_start = rvfx0_t1_v_stop + 1; + parameter rvfx0_t1_t_stop = (rvfx0_t1_t_start + (3)) - 1; + parameter rvfx0_t2_v_start = rvfx0_t1_t_stop + 1; + parameter rvfx0_t2_v_stop = (rvfx0_t2_v_start + (1)) - 1; + parameter rvfx0_t2_t_start = rvfx0_t2_v_stop + 1; + parameter rvfx0_t2_t_stop = (rvfx0_t2_t_start + (3)) - 1; + parameter rvfx0_t3_v_start = rvfx0_t2_t_stop + 1; + parameter rvfx0_t3_v_stop = (rvfx0_t3_v_start + (1)) - 1; + parameter rvfx0_t3_t_start = rvfx0_t3_v_stop + 1; + parameter rvfx0_t3_t_stop = (rvfx0_t3_t_start + (3)) - 1; + parameter rvfx0_s1_v_start = rvfx0_t3_t_stop + 1; + parameter rvfx0_s1_v_stop = (rvfx0_s1_v_start + (1)) - 1; + parameter rvfx0_s1_p_start = rvfx0_s1_v_stop + 1; + parameter rvfx0_s1_p_stop = (rvfx0_s1_p_start + (`GPR_POOL_ENC)) - 1; + parameter rvfx0_s1_t_start = rvfx0_s1_p_stop + 1; + parameter rvfx0_s1_t_stop = (rvfx0_s1_t_start + (3)) - 1; + parameter rvfx0_s2_v_start = rvfx0_s1_t_stop + 1; + parameter rvfx0_s2_v_stop = (rvfx0_s2_v_start + (1)) - 1; + parameter rvfx0_s2_p_start = rvfx0_s2_v_stop + 1; + parameter rvfx0_s2_p_stop = (rvfx0_s2_p_start + (`GPR_POOL_ENC)) - 1; + parameter rvfx0_s2_t_start = rvfx0_s2_p_stop + 1; + parameter rvfx0_s2_t_stop = (rvfx0_s2_t_start + (3)) - 1; + parameter rvfx0_s3_v_start = rvfx0_s2_t_stop + 1; + parameter rvfx0_s3_v_stop = (rvfx0_s3_v_start + (1)) - 1; + parameter rvfx0_s3_p_start = rvfx0_s3_v_stop + 1; + parameter rvfx0_s3_p_stop = (rvfx0_s3_p_start + (`GPR_POOL_ENC)) - 1; + parameter rvfx0_s3_t_start = rvfx0_s3_p_stop + 1; + parameter rvfx0_s3_t_stop = (rvfx0_s3_t_start + (3)) - 1; + + parameter rvfx0_end = rvfx0_s3_t_stop; + + parameter rvfx0_size = rvfx0_end + 1; + + //------------------------------------------------------------------------------------------------------------ + // Pervasive + //------------------------------------------------------------------------------------------------------------ + + + wire tiup; + + //------------------------------------------------------------------------------------------------------------ + // RV1 + //------------------------------------------------------------------------------------------------------------ + wire [rvfx0_start:rvfx0_end] rv0_instr_i0_dat; + wire [rvfx0_start:rvfx0_end] rv0_instr_i1_dat; + wire [rvfx0_ex0_start:rvfx0_ex0_end] rv0_instr_i0_dat_ex0; + wire [rvfx0_ex0_start:rvfx0_ex0_end] rv0_instr_i1_dat_ex0; + + wire rv0_instr_i0_spec; + wire rv0_instr_i1_spec; + + //------------------------------------------------------------------------------------------------------------ + // RV2 + //------------------------------------------------------------------------------------------------------------ + wire [rvfx0_start:rvfx0_end] rv1_instr_dat; + wire [0:`THREADS-1] rv1_instr_v; + wire rv1_instr_ord; + (* analysis_not_referenced="true" *) + wire rv1_instr_spec; + wire [0:`THREADS-1] rv1_instr_ilat0_vld; + wire [0:`THREADS-1] rv1_instr_ilat1_vld; + wire [0:3] rv1_instr_ilat; + wire [0:`ITAG_SIZE_ENC-1] rv1_instr_itag; + wire [0:`ITAG_SIZE_ENC-1] rv1_instr_s1_itag; + wire [0:`ITAG_SIZE_ENC-1] rv1_instr_s2_itag; + wire [0:`ITAG_SIZE_ENC-1] rv1_instr_s3_itag; + wire rv1_instr_is_brick; + wire [0:`THREADS-1] ex1_credit_free; + + //------------------------------------------------------------------------------------------------------------ + // EX0 + //------------------------------------------------------------------------------------------------------------ + wire rv_ex0_act; + + (* analysis_not_referenced="<140:143>true" *) + wire [rvfx0_ex0_start:rvfx0_ex0_end] ex0_instr_dat; + + wire [0:`ITAG_SIZE_ENC-1] ex0_itag_d; + wire ex0_ord_d; + wire ex0_is_brick_d; + wire ex0_t1_v_d; + wire [0:2] ex0_t1_t_d; + wire ex0_t2_v_d; + wire [0:2] ex0_t2_t_d; + wire ex0_t3_v_d; + wire [0:2] ex0_t3_t_d; + wire ex0_s1_v_d; + wire ex0_s2_v_d; + wire [0:2] ex0_s2_t_d; + wire ex0_s3_v_d; + wire [0:2] ex0_s3_t_d; + + wire [0:`ITAG_SIZE_ENC-1] ex0_itag_q; + wire ex0_ord_q; + wire ex0_is_brick_q; + wire ex0_t1_v_q; + wire [0:2] ex0_t1_t_q; + wire ex0_t2_v_q; + wire [0:2] ex0_t2_t_q; + wire ex0_t3_v_q; + wire [0:2] ex0_t3_t_q; + wire ex0_s1_v_q; + wire ex0_s2_v_q; + wire [0:2] ex0_s2_t_q; + wire ex0_s3_v_q; + wire [0:2] ex0_s3_t_q; + + //------------------------------------------------------------------------------------------------------------ + // Itag busses and shadow + //------------------------------------------------------------------------------------------------------------ + + wire [0:`THREADS-1] lq_rv_itag1_rst_vld; + wire [0:`ITAG_SIZE_ENC-1] lq_rv_itag1_rst; + + wire [0:`THREADS*`ITAG_SIZE_ENC-1] cp_next_itag_q; + + (* analysis_not_referenced="true" *) + wire rvs_empty; + + //------------------------------------------------------------------------------------------------------------ + // Scan Chains + //------------------------------------------------------------------------------------------------------------ + parameter rvs_offset = 0 + 0; + parameter ex0_is_brick_offset = rvs_offset + 1; + parameter ex0_itag_offset = ex0_is_brick_offset + 1; + parameter ex0_ord_offset = ex0_itag_offset + `ITAG_SIZE_ENC; + parameter ex0_t1_v_offset = ex0_ord_offset + 1; + parameter ex0_t1_t_offset = ex0_t1_v_offset + 1; + parameter ex0_t2_v_offset = ex0_t1_t_offset + 3; + parameter ex0_t2_t_offset = ex0_t2_v_offset + 1; + parameter ex0_t3_v_offset = ex0_t2_t_offset + 3; + parameter ex0_t3_t_offset = ex0_t3_v_offset + 1; + parameter ex0_s1_v_offset = ex0_t3_t_offset + 3; + parameter ex0_s2_v_offset = ex0_s1_v_offset + 1; + parameter ex0_s2_t_offset = ex0_s2_v_offset + 1; + parameter ex0_s3_v_offset = ex0_s2_t_offset + 3; + parameter ex0_s3_t_offset = ex0_s3_v_offset + 1; + + parameter cp_next_itag_offset = ex0_s3_t_offset + 3; + + parameter scan_right = cp_next_itag_offset + `THREADS * `ITAG_SIZE_ENC; + wire [0:scan_right-1] siv; + wire [0:scan_right-1] sov; + + wire func_sl_thold_0; + wire func_sl_thold_0_b; + wire sg_0; + wire force_t; + + wire lq_rv_itag1_cord; + + //!! Bugspray Include: rv_fx0_rvs; + + //------------------------------------------------------------------------------------------------------------ + // Pervasive + //------------------------------------------------------------------------------------------------------------ + assign tiup = 1'b1; + + + + //------------------------------------------------------------------------------------------------------------ + // RV Entry + //------------------------------------------------------------------------------------------------------------ + + + assign rv0_instr_i0_dat = { + rv0_instr_i0_t1_v, + rv0_instr_i0_t1_t, + rv0_instr_i0_t2_v, + rv0_instr_i0_t2_t, + rv0_instr_i0_t3_v, + rv0_instr_i0_t3_t, + rv0_instr_i0_s1_v, + rv0_instr_i0_s1_p, + rv0_instr_i0_s1_t, + rv0_instr_i0_s2_v, + rv0_instr_i0_s2_p, + rv0_instr_i0_s2_t, + rv0_instr_i0_s3_v, + rv0_instr_i0_s3_p, + rv0_instr_i0_s3_t }; + + assign rv0_instr_i0_dat_ex0 = { + rv0_instr_i0_instr, + rv0_instr_i0_ifar, + rv0_instr_i0_ucode, + rv0_instr_i0_ucode_cnt, + rv0_instr_i0_t1_p, + rv0_instr_i0_t2_p, + rv0_instr_i0_t3_p, + rv0_instr_i0_branch, + rv0_instr_i0_spare}; + + assign rv0_instr_i1_dat = { + rv0_instr_i1_t1_v, + rv0_instr_i1_t1_t, + rv0_instr_i1_t2_v, + rv0_instr_i1_t2_t, + rv0_instr_i1_t3_v, + rv0_instr_i1_t3_t, + rv0_instr_i1_s1_v, + rv0_instr_i1_s1_p, + rv0_instr_i1_s1_t, + rv0_instr_i1_s2_v, + rv0_instr_i1_s2_p, + rv0_instr_i1_s2_t, + rv0_instr_i1_s3_v, + rv0_instr_i1_s3_p, + rv0_instr_i1_s3_t }; + + assign rv0_instr_i1_dat_ex0 = { + rv0_instr_i1_instr, + rv0_instr_i1_ifar, + rv0_instr_i1_ucode, + rv0_instr_i1_ucode_cnt, + rv0_instr_i1_t1_p, + rv0_instr_i1_t2_p, + rv0_instr_i1_t3_p, + rv0_instr_i1_branch, + rv0_instr_i1_spare}; + + //------------------------------------------------------------------------------------------------------------ + // FX0 Reservation Stations + //------------------------------------------------------------------------------------------------------------ + assign rv0_instr_i0_spec = 1'b0; + assign rv0_instr_i1_spec = 1'b0; + + assign lq_rv_itag1_cord = 1'b0; + + rv_station #( .q_dat_width_g(rvfx0_size), .q_dat_ex0_width_g(rvfx0_ex0_size), .q_num_entries_g(`RV_FX0_ENTRIES), .q_itag_busses_g(num_itag_busses_g) ) + rvs( + .cp_flush(cp_flush), + .cp_next_itag(cp_next_itag_q), + + .rv0_instr_i0_vld(rv0_instr_i0_vld), + .rv0_instr_i0_rte(rv0_instr_i0_rte_fx0), + .rv0_instr_i1_vld(rv0_instr_i1_vld), + .rv0_instr_i1_rte(rv0_instr_i1_rte_fx0), + + .rv0_instr_i0_dat(rv0_instr_i0_dat), + .rv0_instr_i0_dat_ex0(rv0_instr_i0_dat_ex0), + .rv0_instr_i0_itag(rv0_instr_i0_itag), + .rv0_instr_i0_ord(rv0_instr_i0_ord), + .rv0_instr_i0_cord(rv0_instr_i0_cord), + .rv0_instr_i0_spec(rv0_instr_i0_spec), + .rv0_instr_i0_s1_dep_hit(rv0_instr_i0_s1_dep_hit), //swap + .rv0_instr_i0_s1_itag(rv0_instr_i0_s1_itag), //swap + .rv0_instr_i0_s2_dep_hit(rv0_instr_i0_s2_dep_hit), + .rv0_instr_i0_s2_itag(rv0_instr_i0_s2_itag), + .rv0_instr_i0_s3_dep_hit(rv0_instr_i0_s3_dep_hit), + .rv0_instr_i0_s3_itag(rv0_instr_i0_s3_itag), + .rv0_instr_i0_is_brick(rv0_instr_i0_is_brick), + .rv0_instr_i0_brick(rv0_instr_i0_brick), + .rv0_instr_i0_ilat(rv0_instr_i0_ilat), + .rv0_instr_i0_s1_v(rv0_instr_i0_s1_v), //swap + .rv0_instr_i0_s2_v(rv0_instr_i0_s2_v), + .rv0_instr_i0_s3_v(rv0_instr_i0_s3_v), + + .rv0_instr_i1_dat(rv0_instr_i1_dat), + .rv0_instr_i1_dat_ex0(rv0_instr_i1_dat_ex0), + .rv0_instr_i1_itag(rv0_instr_i1_itag), + .rv0_instr_i1_ord(rv0_instr_i1_ord), + .rv0_instr_i1_cord(rv0_instr_i1_cord), + .rv0_instr_i1_spec(rv0_instr_i1_spec), + .rv0_instr_i1_s1_dep_hit(rv0_instr_i1_s1_dep_hit), //swap + .rv0_instr_i1_s1_itag(rv0_instr_i1_s1_itag), //swap + .rv0_instr_i1_s2_dep_hit(rv0_instr_i1_s2_dep_hit), + .rv0_instr_i1_s2_itag(rv0_instr_i1_s2_itag), + .rv0_instr_i1_s3_dep_hit(rv0_instr_i1_s3_dep_hit), + .rv0_instr_i1_s3_itag(rv0_instr_i1_s3_itag), + .rv0_instr_i1_is_brick(rv0_instr_i1_is_brick), + .rv0_instr_i1_brick(rv0_instr_i1_brick), + .rv0_instr_i1_ilat(rv0_instr_i1_ilat), + .rv0_instr_i1_s1_v(rv0_instr_i1_s1_v), //swap + .rv0_instr_i1_s2_v(rv0_instr_i1_s2_v), + .rv0_instr_i1_s3_v(rv0_instr_i1_s3_v), + + .rv1_instr_vld(rv1_instr_v), + .rv1_instr_dat(rv1_instr_dat), + .rv1_instr_ord(rv1_instr_ord), + .rv1_instr_spec(rv1_instr_spec), + .rv1_instr_itag(rv1_instr_itag), + .rv1_instr_ilat(rv1_instr_ilat), + .rv1_instr_ilat0_vld(rv1_instr_ilat0_vld), + .rv1_instr_ilat1_vld(rv1_instr_ilat1_vld), + .rv1_instr_s1_itag(rv1_instr_s1_itag), + .rv1_instr_s2_itag(rv1_instr_s2_itag), + .rv1_instr_s3_itag(rv1_instr_s3_itag), + .rv1_instr_is_brick(rv1_instr_is_brick), + .ex0_instr_dat(ex0_instr_dat), + .ex1_credit_free(ex1_credit_free), + + .rv1_other_ilat0_vld(rv1_fx1_ilat0_vld), + .rv1_other_ilat0_itag(rv1_fx1_ilat0_itag), + .rv1_other_ilat0_vld_out(rv1_fx0_ilat0_vld), + .rv1_other_ilat0_itag_out(rv1_fx0_ilat0_itag), + + .q_hold_all(fx0_rv_hold_all), + .q_ord_complete(fx0_rv_ord_complete), + .q_ord_tid(fx0_rv_ord_tid), + + .fx0_rv_itag (fx0_rv_itag), + .fx1_rv_itag (fx1_rv_itag), + .lq_rv_itag0 (lq_rv_ext_itag0), + .lq_rv_itag1 (lq_rv_ext_itag1), + .lq_rv_itag2 (lq_rv_ext_itag2), + .axu0_rv_itag (axu0_rv_ext_itag), + .axu1_rv_itag (axu1_rv_ext_itag), + .fx0_rv_itag_vld (fx0_rv_itag_vld), + .fx1_rv_itag_vld (fx1_rv_itag_vld), + .lq_rv_itag0_vld (lq_rv_ext_itag0_vld), + .lq_rv_itag1_vld (lq_rv_ext_itag1_vld), + .lq_rv_itag2_vld (lq_rv_ext_itag2_vld), + .axu0_rv_itag_vld (axu0_rv_ext_itag_vld), + .axu1_rv_itag_vld (axu1_rv_ext_itag_vld), + .fx0_rv_itag_abort (fx0_rv_itag_abort), + .fx1_rv_itag_abort (fx1_rv_itag_abort), + .lq_rv_itag0_abort (lq_rv_ext_itag0_abort), + .lq_rv_itag1_abort (lq_rv_ext_itag1_abort), + .axu0_rv_itag_abort (axu0_rv_ext_itag_abort), + .axu1_rv_itag_abort (axu1_rv_ext_itag_abort), + + .xx_rv_ex2_s1_abort(fx0_rv_ex2_s1_abort), + .xx_rv_ex2_s2_abort(fx0_rv_ex2_s2_abort), + .xx_rv_ex2_s3_abort(fx0_rv_ex2_s3_abort), + + .lq_rv_itag1_restart(lq_rv_itag1_restart), + .lq_rv_itag1_hold(lq_rv_itag1_hold), + .lq_rv_itag1_cord(lq_rv_itag1_cord), + .lq_rv_itag1_rst_vld(lq_rv_itag1_rst_vld), + .lq_rv_itag1_rst(lq_rv_itag1_rst), + .lq_rv_clr_hold(lq_rv_clr_hold), + + .rvs_perf_bus(fx0_rvs_perf_bus), + .rvs_dbg_bus(fx0_rvs_dbg_bus), + .rvs_empty(rvs_empty), + + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .sg_1(sg_1), + .func_sl_thold_1(func_sl_thold_1), + .ccflush_dc(ccflush_dc), + .act_dis(act_dis), + .clkoff_b(clkoff_b), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scan_in(siv[rvs_offset]), + .scan_out(sov[rvs_offset]) + ); + + assign rv_iu_fx0_credit_free = ex1_credit_free; + + assign rv_fx0_vld = rv1_instr_v; + assign rv_fx0_s1_v = rv1_instr_dat[rvfx0_s1_v_start]; + assign rv_fx0_s1_p = rv1_instr_dat[rvfx0_s1_p_start:rvfx0_s1_p_stop]; + assign rv_fx0_s2_v = rv1_instr_dat[rvfx0_s2_v_start]; + assign rv_fx0_s2_p = rv1_instr_dat[rvfx0_s2_p_start:rvfx0_s2_p_stop]; + assign rv_fx0_s3_v = rv1_instr_dat[rvfx0_s3_v_start]; + assign rv_fx0_s3_p = rv1_instr_dat[rvfx0_s3_p_start:rvfx0_s3_p_stop]; + + assign rv_byp_fx0_vld = rv1_instr_v; + + //RV2 Outputs + assign rv_byp_fx0_ord = rv1_instr_ord; + assign rv_byp_fx0_itag = rv1_instr_itag; + assign rv_byp_fx0_ilat = rv1_instr_ilat; + assign rv_byp_fx0_s1_itag = rv1_instr_s1_itag; + assign rv_byp_fx0_s2_itag = rv1_instr_s2_itag; + assign rv_byp_fx0_s3_itag = rv1_instr_s3_itag; + + //RV2 to Bypass + assign rv_byp_fx0_t1_v = rv1_instr_dat[rvfx0_t1_v_start]; + assign rv_byp_fx0_t1_t = rv1_instr_dat[rvfx0_t1_t_start:rvfx0_t1_t_stop]; + assign rv_byp_fx0_t2_v = rv1_instr_dat[rvfx0_t2_v_start]; + assign rv_byp_fx0_t2_t = rv1_instr_dat[rvfx0_t2_t_start:rvfx0_t2_t_stop]; + assign rv_byp_fx0_t3_v = rv1_instr_dat[rvfx0_t3_v_start]; + assign rv_byp_fx0_t3_t = rv1_instr_dat[rvfx0_t3_t_start:rvfx0_t3_t_stop]; + assign rv_byp_fx0_s1_t = rv1_instr_dat[rvfx0_s1_t_start:rvfx0_s1_t_stop]; + assign rv_byp_fx0_s2_t = rv1_instr_dat[rvfx0_s2_t_start:rvfx0_s2_t_stop]; + assign rv_byp_fx0_s3_t = rv1_instr_dat[rvfx0_s3_t_start:rvfx0_s3_t_stop]; + assign rv_byp_fx0_ilat0_vld = rv1_instr_ilat0_vld; + assign rv_byp_fx0_ilat1_vld = rv1_instr_ilat1_vld; + + //EX0 Outputs + assign ex0_ord_d = rv1_instr_ord; + assign ex0_itag_d = rv1_instr_itag; + assign ex0_is_brick_d = rv1_instr_is_brick; + + assign ex0_t1_v_d = rv1_instr_dat[rvfx0_t1_v_start]; + assign ex0_t1_t_d = rv1_instr_dat[rvfx0_t1_t_start:rvfx0_t1_t_stop]; + assign ex0_t2_v_d = rv1_instr_dat[rvfx0_t2_v_start]; + assign ex0_t2_t_d = rv1_instr_dat[rvfx0_t2_t_start:rvfx0_t2_t_stop]; + assign ex0_t3_v_d = rv1_instr_dat[rvfx0_t3_v_start]; + assign ex0_t3_t_d = rv1_instr_dat[rvfx0_t3_t_start:rvfx0_t3_t_stop]; + assign ex0_s1_v_d = rv1_instr_dat[rvfx0_s1_v_start]; + assign ex0_s2_v_d = rv1_instr_dat[rvfx0_s2_v_start]; + assign ex0_s2_t_d = rv1_instr_dat[rvfx0_s2_t_start:rvfx0_s2_t_stop]; + assign ex0_s3_v_d = rv1_instr_dat[rvfx0_s3_v_start]; + assign ex0_s3_t_d = rv1_instr_dat[rvfx0_s3_t_start:rvfx0_s3_t_stop]; + + assign rv_ex0_act = |(rv1_instr_v); + + assign rv_fx0_ex0_instr = ex0_instr_dat[rvfx0_instr_start:rvfx0_instr_stop]; + assign rv_fx0_ex0_ifar = ex0_instr_dat[rvfx0_ifar_start:rvfx0_ifar_stop]; + assign rv_fx0_ex0_ucode = ex0_instr_dat[rvfx0_ucode_start:rvfx0_ucode_stop]; + assign rv_fx0_ex0_ucode_cnt = ex0_instr_dat[rvfx0_ucode_cnt_start:rvfx0_ucode_cnt_stop]; + assign rv_fx0_ex0_t1_p = ex0_instr_dat[rvfx0_t1_p_start:rvfx0_t1_p_stop]; + assign rv_fx0_ex0_t2_p = ex0_instr_dat[rvfx0_t2_p_start:rvfx0_t2_p_stop]; + assign rv_fx0_ex0_t3_p = ex0_instr_dat[rvfx0_t3_p_start:rvfx0_t3_p_stop]; + assign rv_fx0_ex0_branch = ex0_instr_dat[rvfx0_branch_start:rvfx0_branch_stop]; + + assign rv_fx0_ex0_ord = ex0_ord_q; + assign rv_fx0_ex0_itag = ex0_itag_q; + assign rv_fx0_ex0_t1_v = ex0_t1_v_q; + assign rv_fx0_ex0_t1_t = ex0_t1_t_q; + assign rv_fx0_ex0_t2_v = ex0_t2_v_q; + assign rv_fx0_ex0_t2_t = ex0_t2_t_q; + assign rv_fx0_ex0_t3_v = ex0_t3_v_q; + assign rv_fx0_ex0_t3_t = ex0_t3_t_q; + assign rv_fx0_ex0_s1_v = ex0_s1_v_q; + assign rv_fx0_ex0_s2_v = ex0_s2_v_q; + assign rv_fx0_ex0_s2_t = ex0_s2_t_q; + assign rv_fx0_ex0_s3_v = ex0_s3_v_q; + assign rv_fx0_ex0_s3_t = ex0_s3_t_q; + assign rv_byp_fx0_ex0_is_brick = ex0_is_brick_q; + + //------------------------------------------------------------------------------------------------------------ + // Itag busses + //------------------------------------------------------------------------------------------------------------ + + + // Restart Itag and Valid from LQ. This is separate because it could be early (not latched) + assign lq_rv_itag1_rst_vld = lq_rv_itag1_vld; + assign lq_rv_itag1_rst = lq_rv_itag1; + + //------------------------------------------------------------------------------------------------------------ + // Pipeline Latches + //------------------------------------------------------------------------------------------------------------ + + tri_rlmlatch_p #(.INIT(0) ) + ex0_is_brick_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[ex0_is_brick_offset]), + .scout(sov[ex0_is_brick_offset]), + .din(ex0_is_brick_d), + .dout(ex0_is_brick_q) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0) ) + ex0_itag_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[ex0_itag_offset:ex0_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[ex0_itag_offset:ex0_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(ex0_itag_d), + .dout(ex0_itag_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) + ex0_ord_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rv_ex0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[ex0_ord_offset]), + .scout(sov[ex0_ord_offset]), + .din(ex0_ord_d), + .dout(ex0_ord_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) + ex0_t1_v_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rv_ex0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[ex0_t1_v_offset]), + .scout(sov[ex0_t1_v_offset]), + .din(ex0_t1_v_d), + .dout(ex0_t1_v_q) + ); + + + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) + ex0_t1_t_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rv_ex0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[ex0_t1_t_offset:ex0_t1_t_offset + 3 - 1]), + .scout(sov[ex0_t1_t_offset:ex0_t1_t_offset + 3 - 1]), + .din(ex0_t1_t_d), + .dout(ex0_t1_t_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) + ex0_t2_v_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rv_ex0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[ex0_t2_v_offset]), + .scout(sov[ex0_t2_v_offset]), + .din(ex0_t2_v_d), + .dout(ex0_t2_v_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) + ex0_t2_t_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rv_ex0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[ex0_t2_t_offset:ex0_t2_t_offset + 3 - 1]), + .scout(sov[ex0_t2_t_offset:ex0_t2_t_offset + 3 - 1]), + .din(ex0_t2_t_d), + .dout(ex0_t2_t_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) + ex0_t3_v_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rv_ex0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[ex0_t3_v_offset]), + .scout(sov[ex0_t3_v_offset]), + .din(ex0_t3_v_d), + .dout(ex0_t3_v_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) + ex0_t3_t_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rv_ex0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[ex0_t3_t_offset:ex0_t3_t_offset + 3 - 1]), + .scout(sov[ex0_t3_t_offset:ex0_t3_t_offset + 3 - 1]), + .din(ex0_t3_t_d), + .dout(ex0_t3_t_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) + ex0_s1_v_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rv_ex0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[ex0_s1_v_offset]), + .scout(sov[ex0_s1_v_offset]), + .din(ex0_s1_v_d), + .dout(ex0_s1_v_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) + ex0_s2_v_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rv_ex0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[ex0_s2_v_offset]), + .scout(sov[ex0_s2_v_offset]), + .din(ex0_s2_v_d), + .dout(ex0_s2_v_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) + ex0_s2_t_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rv_ex0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[ex0_s2_t_offset:ex0_s2_t_offset + 3 - 1]), + .scout(sov[ex0_s2_t_offset:ex0_s2_t_offset + 3 - 1]), + .din(ex0_s2_t_d), + .dout(ex0_s2_t_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) + ex0_s3_v_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rv_ex0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[ex0_s3_v_offset]), + .scout(sov[ex0_s3_v_offset]), + .din(ex0_s3_v_d), + .dout(ex0_s3_v_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) + ex0_s3_t_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rv_ex0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[ex0_s3_t_offset:ex0_s3_t_offset + 3 - 1]), + .scout(sov[ex0_s3_t_offset:ex0_s3_t_offset + 3 - 1]), + .din(ex0_s3_t_d), + .dout(ex0_s3_t_q) + ); + + + + tri_rlmreg_p #(.WIDTH(`THREADS*`ITAG_SIZE_ENC), .INIT(0)) + cp_next_itag_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[cp_next_itag_offset :cp_next_itag_offset + `THREADS*`ITAG_SIZE_ENC-1]), + .scout(sov[cp_next_itag_offset:cp_next_itag_offset + `THREADS*`ITAG_SIZE_ENC-1]), + .din(cp_next_itag), + .dout(cp_next_itag_q) + ); + + //------------------------------------------------------------------------------------------------------------ + // Scan Connections + //------------------------------------------------------------------------------------------------------------ + + assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in}; + assign scan_out = sov[0]; + + //----------------------------------------------- + // pervasive + //----------------------------------------------- + + + tri_plat #(.WIDTH(2)) + perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(ccflush_dc), + .din({func_sl_thold_1, sg_1}), + .q({func_sl_thold_0, sg_0}) + ); + + + tri_lcbor + perv_lcbor( + .clkoff_b(clkoff_b), + .thold(func_sl_thold_0), + .sg(sg_0), + .act_dis(act_dis), + .force_t(force_t), + .thold_b(func_sl_thold_0_b) + ); + +endmodule diff --git a/dev/verilog/work/rv_fx1_rvs.v b/dev/verilog/work/rv_fx1_rvs.v new file mode 100755 index 0000000..ff26526 --- /dev/null +++ b/dev/verilog/work/rv_fx1_rvs.v @@ -0,0 +1,847 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//----------------------------------------------------------------------------------------------------- +// Title: rv_fx1_rvs.vhdl +// Desc: LQ Reservation Station +// +//----------------------------------------------------------------------------------------------------- + +module rv_fx1_rvs( +`include "tri_a2o.vh" + + + //------------------------------------------------------------------------------------------------------------ + // Instructions from RV_DEP + //------------------------------------------------------------------------------------------------------------ + input [0:`THREADS-1] rv0_instr_i0_vld, + input rv0_instr_i0_rte_fx1, + input [0:`THREADS-1] rv0_instr_i1_vld, + input rv0_instr_i1_rte_fx1, + + input [0:31] rv0_instr_i0_instr, + input [0:2] rv0_instr_i0_ucode, + input [0:`ITAG_SIZE_ENC-1] rv0_instr_i0_itag, + input rv0_instr_i0_t1_v, + input [0:`GPR_POOL_ENC-1] rv0_instr_i0_t1_p, + input rv0_instr_i0_t2_v, + input [0:`GPR_POOL_ENC-1] rv0_instr_i0_t2_p, + input rv0_instr_i0_t3_v, + input [0:`GPR_POOL_ENC-1] rv0_instr_i0_t3_p, + input rv0_instr_i0_s1_v, + input [0:`GPR_POOL_ENC-1] rv0_instr_i0_s1_p, + input [0:2] rv0_instr_i0_s1_t, + input rv0_instr_i0_s2_v, + input [0:`GPR_POOL_ENC-1] rv0_instr_i0_s2_p, + input [0:2] rv0_instr_i0_s2_t, + input rv0_instr_i0_s3_v, + input [0:`GPR_POOL_ENC-1] rv0_instr_i0_s3_p, + input [0:2] rv0_instr_i0_s3_t, + input [0:3] rv0_instr_i0_ilat, + input rv0_instr_i0_isStore, + input [0:3] rv0_instr_i0_spare, + input rv0_instr_i0_is_brick, + input [0:2] rv0_instr_i0_brick, + + input [0:31] rv0_instr_i1_instr, + input [0:2] rv0_instr_i1_ucode, + input [0:`ITAG_SIZE_ENC-1] rv0_instr_i1_itag, + input rv0_instr_i1_t1_v, + input [0:`GPR_POOL_ENC-1] rv0_instr_i1_t1_p, + input rv0_instr_i1_t2_v, + input [0:`GPR_POOL_ENC-1] rv0_instr_i1_t2_p, + input rv0_instr_i1_t3_v, + input [0:`GPR_POOL_ENC-1] rv0_instr_i1_t3_p, + input rv0_instr_i1_s1_v, + input [0:`GPR_POOL_ENC-1] rv0_instr_i1_s1_p, + input [0:2] rv0_instr_i1_s1_t, + input rv0_instr_i1_s2_v, + input [0:`GPR_POOL_ENC-1] rv0_instr_i1_s2_p, + input [0:2] rv0_instr_i1_s2_t, + input rv0_instr_i1_s3_v, + input [0:`GPR_POOL_ENC-1] rv0_instr_i1_s3_p, + input [0:2] rv0_instr_i1_s3_t, + input [0:3] rv0_instr_i1_ilat, + input rv0_instr_i1_isStore, + input [0:3] rv0_instr_i1_spare, + input rv0_instr_i1_is_brick, + input [0:2] rv0_instr_i1_brick, + + + input rv0_instr_i0_s1_dep_hit, + input [0:`ITAG_SIZE_ENC-1] rv0_instr_i0_s1_itag, + input rv0_instr_i0_s2_dep_hit, + input [0:`ITAG_SIZE_ENC-1] rv0_instr_i0_s2_itag, + input rv0_instr_i0_s3_dep_hit, + input [0:`ITAG_SIZE_ENC-1] rv0_instr_i0_s3_itag, + + input rv0_instr_i1_s1_dep_hit, + input [0:`ITAG_SIZE_ENC-1] rv0_instr_i1_s1_itag, + input rv0_instr_i1_s2_dep_hit, + input [0:`ITAG_SIZE_ENC-1] rv0_instr_i1_s2_itag, + input rv0_instr_i1_s3_dep_hit, + input [0:`ITAG_SIZE_ENC-1] rv0_instr_i1_s3_itag, + + //------------------------------------------------------------------------------------------------------------ + // Credit Interface with IU + //------------------------------------------------------------------------------------------------------------ + output [0:`THREADS-1] rv_iu_fx1_credit_free, + + //------------------------------------------------------------------------------------------------------------ + // Machine zap interface + //------------------------------------------------------------------------------------------------------------ + input [0:`THREADS-1] cp_flush, + + //------------------------------------------------------------------------------------------------------------ + // Interface to fx1 + //------------------------------------------------------------------------------------------------------------ + output [0:`THREADS-1] rv_fx1_vld, + output rv_fx1_s1_v, + output [0:`GPR_POOL_ENC-1] rv_fx1_s1_p, + output rv_fx1_s2_v, + output [0:`GPR_POOL_ENC-1] rv_fx1_s2_p, + output rv_fx1_s3_v, + output [0:`GPR_POOL_ENC-1] rv_fx1_s3_p, + + output [0:`THREADS-1] rv_byp_fx1_vld, + output [0:`ITAG_SIZE_ENC-1] rv_byp_fx1_itag, + output rv_byp_fx1_t1_v, + output rv_byp_fx1_t2_v, + output rv_byp_fx1_t3_v, + output [0:2] rv_byp_fx1_s1_t, + output [0:2] rv_byp_fx1_s2_t, + output [0:2] rv_byp_fx1_s3_t, + output [0:3] rv_byp_fx1_ilat, + output rv_byp_fx1_ex0_isStore, + + output [0:`ITAG_SIZE_ENC-1] rv_fx1_ex0_itag, + output [0:31] rv_fx1_ex0_instr, + output [0:2] rv_fx1_ex0_ucode, + output rv_fx1_ex0_t1_v, + output [0:`GPR_POOL_ENC-1] rv_fx1_ex0_t1_p, + output rv_fx1_ex0_t2_v, + output [0:`GPR_POOL_ENC-1] rv_fx1_ex0_t2_p, + output rv_fx1_ex0_t3_v, + output [0:`GPR_POOL_ENC-1] rv_fx1_ex0_t3_p, + output rv_fx1_ex0_s1_v, + output [0:2] rv_fx1_ex0_s3_t, + output rv_fx1_ex0_isStore, + + output [0:`ITAG_SIZE_ENC-1] rv_byp_fx1_s1_itag, + output [0:`ITAG_SIZE_ENC-1] rv_byp_fx1_s2_itag, + output [0:`ITAG_SIZE_ENC-1] rv_byp_fx1_s3_itag, + + //------------------------------------------------------------------------------------------------------------ + // RV Release bus + //------------------------------------------------------------------------------------------------------------ + + input fx1_rv_ex2_s1_abort, + input fx1_rv_ex2_s2_abort, + input fx1_rv_ex2_s3_abort, + + input fx0_rv_itag_abort, + input fx1_rv_itag_abort, + input lq_rv_ext_itag0_abort, + input lq_rv_ext_itag1_abort, + input axu1_rv_ext_itag_abort, + input axu0_rv_ext_itag_abort, + + + input [0:`THREADS-1] fx0_rv_itag_vld, + input [0:`ITAG_SIZE_ENC-1] fx0_rv_itag, + + input [0:`THREADS-1] fx1_rv_itag_vld, + input [0:`ITAG_SIZE_ENC-1] fx1_rv_itag, + + input [0:`THREADS-1] axu0_rv_ext_itag_vld, + input [0:`ITAG_SIZE_ENC-1] axu0_rv_ext_itag, + + input [0:`THREADS-1] axu1_rv_ext_itag_vld, + input [0:`ITAG_SIZE_ENC-1] axu1_rv_ext_itag, + + input [0:`THREADS-1] lq_rv_ext_itag0_vld, + input [0:`ITAG_SIZE_ENC-1] lq_rv_ext_itag0, + + input [0:`THREADS-1] lq_rv_itag1_vld, + input [0:`ITAG_SIZE_ENC-1] lq_rv_itag1, + input lq_rv_itag1_restart, + input lq_rv_itag1_hold, + input [0:`THREADS-1] lq_rv_ext_itag1_vld, + input [0:`ITAG_SIZE_ENC-1] lq_rv_ext_itag1, + + input [0:`THREADS-1] lq_rv_ext_itag2_vld, + input [0:`ITAG_SIZE_ENC-1] lq_rv_ext_itag2, + + input [0:`THREADS-1] lq_rv_clr_hold, + + input fx1_rv_hold_all, + + output [0:`THREADS-1] rv_byp_fx1_ilat0_vld, + output [0:`THREADS-1] rv_byp_fx1_ilat1_vld, + + input [0:`THREADS-1] rv1_fx0_ilat0_vld, + input [0:`ITAG_SIZE_ENC-1] rv1_fx0_ilat0_itag, + output [0:`THREADS-1] rv1_fx1_ilat0_vld, + output [0:`ITAG_SIZE_ENC-1] rv1_fx1_ilat0_itag, + + //------------------------------------------------------------------------------------------------------------ + // Pervasive + //------------------------------------------------------------------------------------------------------------ + output [0:8*`THREADS-1] fx1_rvs_perf_bus, + output [0:31] fx1_rvs_dbg_bus, + + inout vdd, + inout gnd, + (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) // nclk + input [0:`NCLK_WIDTH-1] nclk, + input func_sl_thold_1, + input sg_1, + input clkoff_b, + input act_dis, + input ccflush_dc, + input d_mode, + input delay_lclkr, + input mpw1_b, + input mpw2_b, + input scan_in, + + output scan_out + + ); + + parameter num_itag_busses_g = 7; + + + + //------------------------------------------------------------------------------------------------------------ + // RV FX1 RVS INSTR ISSUE + //------------------------------------------------------------------------------------------------------------ + parameter rvfx1_ex0_start = 0; + + parameter rvfx1_instr_start = rvfx1_ex0_start; + parameter rvfx1_instr_stop = (rvfx1_instr_start + (32)) - 1; + parameter rvfx1_ucode_start = rvfx1_instr_stop + 1; + parameter rvfx1_ucode_stop = (rvfx1_ucode_start + (3)) - 1; + parameter rvfx1_t1_p_start = rvfx1_ucode_stop + 1; + parameter rvfx1_t1_p_stop = (rvfx1_t1_p_start + (`GPR_POOL_ENC)) - 1; + parameter rvfx1_t2_p_start = rvfx1_t1_p_stop + 1; + parameter rvfx1_t2_p_stop = (rvfx1_t2_p_start + (`GPR_POOL_ENC)) - 1; + parameter rvfx1_t3_p_start = rvfx1_t2_p_stop + 1; + parameter rvfx1_t3_p_stop = (rvfx1_t3_p_start + (`GPR_POOL_ENC)) - 1; + parameter rvfx1_isStore_start = rvfx1_t3_p_stop + 1; + parameter rvfx1_isStore_stop = (rvfx1_isStore_start + (1)) - 1; + parameter rvfx1_spare_start = rvfx1_isStore_stop + 1; + parameter rvfx1_spare_stop = (rvfx1_spare_start + (4)) - 1; + parameter rvfx1_ex0_end = rvfx1_spare_stop; + + parameter rvfx1_ex0_size = rvfx1_ex0_end + 1; + + + + parameter rvfx1_start = 0; + + parameter rvfx1_t1_v_start = rvfx1_start; + parameter rvfx1_t1_v_stop = (rvfx1_t1_v_start + (1)) - 1; + parameter rvfx1_t2_v_start = rvfx1_t1_v_stop + 1; + parameter rvfx1_t2_v_stop = (rvfx1_t2_v_start + (1)) - 1; + parameter rvfx1_t3_v_start = rvfx1_t2_v_stop + 1; + parameter rvfx1_t3_v_stop = (rvfx1_t3_v_start + (1)) - 1; + parameter rvfx1_s1_v_start = rvfx1_t3_v_stop + 1; + parameter rvfx1_s1_v_stop = (rvfx1_s1_v_start + (1)) - 1; + parameter rvfx1_s1_p_start = rvfx1_s1_v_stop + 1; + parameter rvfx1_s1_p_stop = (rvfx1_s1_p_start + (`GPR_POOL_ENC)) - 1; + parameter rvfx1_s1_t_start = rvfx1_s1_p_stop + 1; + parameter rvfx1_s1_t_stop = (rvfx1_s1_t_start + (3)) - 1; + parameter rvfx1_s2_v_start = rvfx1_s1_t_stop + 1; + parameter rvfx1_s2_v_stop = (rvfx1_s2_v_start + (1)) - 1; + parameter rvfx1_s2_p_start = rvfx1_s2_v_stop + 1; + parameter rvfx1_s2_p_stop = (rvfx1_s2_p_start + (`GPR_POOL_ENC)) - 1; + parameter rvfx1_s2_t_start = rvfx1_s2_p_stop + 1; + parameter rvfx1_s2_t_stop = (rvfx1_s2_t_start + (3)) - 1; + parameter rvfx1_s3_v_start = rvfx1_s2_t_stop + 1; + parameter rvfx1_s3_v_stop = (rvfx1_s3_v_start + (1)) - 1; + parameter rvfx1_s3_p_start = rvfx1_s3_v_stop + 1; + parameter rvfx1_s3_p_stop = (rvfx1_s3_p_start + (`GPR_POOL_ENC)) - 1; + parameter rvfx1_s3_t_start = rvfx1_s3_p_stop + 1; + parameter rvfx1_s3_t_stop = (rvfx1_s3_t_start + (3)) - 1; + + parameter rvfx1_end = rvfx1_s3_t_stop; + + parameter rvfx1_size = rvfx1_end + 1; + + + //------------------------------------------------------------------------------------------------------------ + // Pervasive + //------------------------------------------------------------------------------------------------------------ + + //------------------------------------------------------------------------------------------------------------ + // RV1 + //------------------------------------------------------------------------------------------------------------ + wire [rvfx1_start:rvfx1_end] rv0_instr_i0_dat; + wire [rvfx1_start:rvfx1_end] rv0_instr_i1_dat; + + wire [rvfx1_ex0_start:rvfx1_ex0_end] rv0_instr_i0_dat_ex0; + wire [rvfx1_ex0_start:rvfx1_ex0_end] rv0_instr_i1_dat_ex0; + + wire rv0_instr_i0_ord; + wire rv0_instr_i0_cord; + wire rv0_instr_i0_spec; + wire rv0_instr_i1_ord; + wire rv0_instr_i1_cord; + wire rv0_instr_i1_spec; + wire rv0_i0_s1_v; + wire [0:`GPR_POOL_ENC-1] rv0_i0_s1_p; + wire [0:2] rv0_i0_s1_t; + wire rv0_i1_s1_v; + wire [0:`GPR_POOL_ENC-1] rv0_i1_s1_p; + wire [0:2] rv0_i1_s1_t; + wire rv0_i0_s1_dep_hit; + wire [0:`ITAG_SIZE_ENC-1] rv0_i0_s1_itag; + wire rv0_i1_s1_dep_hit; + wire [0:`ITAG_SIZE_ENC-1] rv0_i1_s1_itag; + + wire [0:`THREADS-1] fx1_rv_ord_complete; + + //------------------------------------------------------------------------------------------------------------ + // RV2 + //------------------------------------------------------------------------------------------------------------ + wire [rvfx1_start:rvfx1_end] rv1_instr_dat; + wire [0:`THREADS-1] rv1_instr_v; + wire [0:`THREADS-1] rv1_instr_ilat0_vld; + wire [0:`THREADS-1] rv1_instr_ilat1_vld; + wire [0:3] rv1_instr_ilat; + wire [0:`ITAG_SIZE_ENC-1] rv1_instr_itag; + wire [0:`ITAG_SIZE_ENC-1] rv1_instr_s1_itag; + wire [0:`ITAG_SIZE_ENC-1] rv1_instr_s2_itag; + wire [0:`ITAG_SIZE_ENC-1] rv1_instr_s3_itag; + wire [0:`THREADS-1] ex1_credit_free; + + //------------------------------------------------------------------------------------------------------------ + // EX0 + //------------------------------------------------------------------------------------------------------------ + wire rv_ex0_act; + (* analysis_not_referenced="<54:57>true" *) + wire [rvfx1_ex0_start:rvfx1_ex0_end] ex0_instr_dat; + + wire [0:`ITAG_SIZE_ENC-1] ex0_itag_d; + wire ex0_t1_v_d; + wire ex0_t2_v_d; + wire ex0_t3_v_d; + wire ex0_s1_v_d; + wire [0:2] ex0_s3_t_d; + + wire [0:`ITAG_SIZE_ENC-1] ex0_itag_q; + wire ex0_t1_v_q; + wire ex0_t2_v_q; + wire ex0_t3_v_q; + wire ex0_s1_v_q; + wire [0:2] ex0_s3_t_q; + + //------------------------------------------------------------------------------------------------------------ + // Itag busses and shadow + //------------------------------------------------------------------------------------------------------------ + + wire [0:`THREADS-1] lq_rv_itag1_rst_vld; + wire [0:`ITAG_SIZE_ENC-1] lq_rv_itag1_rst; + + wire [0:`THREADS*`ITAG_SIZE_ENC-1] cp_next_itag; + + //------------------------------------------------------------------------------------------------------------ + // Scan Chains + //------------------------------------------------------------------------------------------------------------ + + parameter rvs_offset = 0 + 0; + parameter ex0_itag_offset = rvs_offset + 1; + parameter ex0_t1_v_offset = ex0_itag_offset + `ITAG_SIZE_ENC; + parameter ex0_t2_v_offset = ex0_t1_v_offset + 1; + parameter ex0_t3_v_offset = ex0_t2_v_offset + 1; + parameter ex0_s1_v_offset = ex0_t3_v_offset + 1; + parameter ex0_s3_t_offset = ex0_s1_v_offset + 1; + + parameter scan_right = ex0_s3_t_offset + 3; + wire [0:scan_right-1] siv; + wire [0:scan_right-1] sov; + + wire func_sl_thold_0; + wire func_sl_thold_0_b; + wire sg_0; + wire force_t; + + wire lq_rv_itag1_cord; + + // Unused Nets + (* analysis_not_referenced="true" *) + wire [0:`THREADS-1] q_ord_tid; + (* analysis_not_referenced="true" *) + wire rvs_empty; + (* analysis_not_referenced="true" *) + wire rv1_instr_is_brick; + (* analysis_not_referenced="true" *) + wire rv1_instr_ord; + (* analysis_not_referenced="true" *) + wire rv1_instr_spec; + + //!! Bugspray Include: rv_fx1_rvs; + + //------------------------------------------------------------------------------------------------------------ + // Pervasive + //------------------------------------------------------------------------------------------------------------ + + //------------------------------------------------------------------------------------------------------------ + // Store Source Swizzle + //------------------------------------------------------------------------------------------------------------ + assign rv0_i0_s1_v = (rv0_instr_i0_isStore == 1'b1) ? rv0_instr_i0_s3_v : + rv0_instr_i0_s1_v; + assign rv0_i0_s1_p = (rv0_instr_i0_isStore == 1'b1) ? rv0_instr_i0_s3_p : + rv0_instr_i0_s1_p; + assign rv0_i0_s1_t = (rv0_instr_i0_isStore == 1'b1) ? rv0_instr_i0_s3_t : + rv0_instr_i0_s1_t; + assign rv0_i0_s1_dep_hit = (rv0_instr_i0_isStore == 1'b1) ? rv0_instr_i0_s3_dep_hit : + rv0_instr_i0_s1_dep_hit; + assign rv0_i0_s1_itag = (rv0_instr_i0_isStore == 1'b1) ? rv0_instr_i0_s3_itag : + rv0_instr_i0_s1_itag; + + assign rv0_i1_s1_v = (rv0_instr_i1_isStore == 1'b1) ? rv0_instr_i1_s3_v : + rv0_instr_i1_s1_v; + assign rv0_i1_s1_p = (rv0_instr_i1_isStore == 1'b1) ? rv0_instr_i1_s3_p : + rv0_instr_i1_s1_p; + assign rv0_i1_s1_t = (rv0_instr_i1_isStore == 1'b1) ? rv0_instr_i1_s3_t : + rv0_instr_i1_s1_t; + assign rv0_i1_s1_dep_hit = (rv0_instr_i1_isStore == 1'b1) ? rv0_instr_i1_s3_dep_hit : + rv0_instr_i1_s1_dep_hit; + assign rv0_i1_s1_itag = (rv0_instr_i1_isStore == 1'b1) ? rv0_instr_i1_s3_itag : + rv0_instr_i1_s1_itag; + + //------------------------------------------------------------------------------------------------------------ + // RV Entry + //------------------------------------------------------------------------------------------------------------ + + assign rv0_instr_i0_dat = {(rv0_instr_i0_t1_v & (~rv0_instr_i0_isStore)), + (rv0_instr_i0_t2_v & (~rv0_instr_i0_isStore)), + (rv0_instr_i0_t3_v & (~rv0_instr_i0_isStore)), + rv0_i0_s1_v, + rv0_i0_s1_p, + rv0_i0_s1_t, + rv0_instr_i0_s2_v, + rv0_instr_i0_s2_p, + rv0_instr_i0_s2_t, + rv0_instr_i0_s3_v, + rv0_instr_i0_s3_p, + rv0_instr_i0_s3_t}; + + assign rv0_instr_i0_dat_ex0 = {rv0_instr_i0_instr, + rv0_instr_i0_ucode, + rv0_instr_i0_t1_p, + rv0_instr_i0_t2_p, + rv0_instr_i0_t3_p, + rv0_instr_i0_isStore, + rv0_instr_i0_spare}; + + assign rv0_instr_i1_dat = {(rv0_instr_i1_t1_v & (~rv0_instr_i1_isStore)), + (rv0_instr_i1_t2_v & (~rv0_instr_i1_isStore)), + (rv0_instr_i1_t3_v & (~rv0_instr_i1_isStore)), + rv0_i1_s1_v, + rv0_i1_s1_p, + rv0_i1_s1_t, + rv0_instr_i1_s2_v, + rv0_instr_i1_s2_p, + rv0_instr_i1_s2_t, + rv0_instr_i1_s3_v, + rv0_instr_i1_s3_p, + rv0_instr_i1_s3_t}; + + assign rv0_instr_i1_dat_ex0 = {rv0_instr_i1_instr, + rv0_instr_i1_ucode, + rv0_instr_i1_t1_p, + rv0_instr_i1_t2_p, + rv0_instr_i1_t3_p, + rv0_instr_i1_isStore, + rv0_instr_i1_spare}; + + //------------------------------------------------------------------------------------------------------------ + // fx1 Reservation Stations + //------------------------------------------------------------------------------------------------------------ + assign rv0_instr_i0_ord = 1'b0; + assign rv0_instr_i0_cord = 1'b0; + assign rv0_instr_i0_spec = 1'b0; + assign rv0_instr_i1_ord = 1'b0; + assign rv0_instr_i1_cord = 1'b0; + assign rv0_instr_i1_spec = 1'b0; + + assign lq_rv_itag1_cord = 1'b0; + assign fx1_rv_ord_complete = {`THREADS{1'b0}}; + + assign cp_next_itag = {`THREADS*`ITAG_SIZE_ENC{1'b0}}; + + + + rv_station #( .q_dat_width_g(rvfx1_size), .q_dat_ex0_width_g(rvfx1_ex0_size), .q_num_entries_g(`RV_FX1_ENTRIES), .q_itag_busses_g(num_itag_busses_g), .q_brick_g(1'b0)) + rvs( + .cp_flush(cp_flush), + .cp_next_itag(cp_next_itag), + + .rv0_instr_i0_vld(rv0_instr_i0_vld), + .rv0_instr_i0_rte(rv0_instr_i0_rte_fx1), + .rv0_instr_i1_vld(rv0_instr_i1_vld), + .rv0_instr_i1_rte(rv0_instr_i1_rte_fx1), + + .rv0_instr_i0_dat(rv0_instr_i0_dat), + .rv0_instr_i0_dat_ex0(rv0_instr_i0_dat_ex0), + .rv0_instr_i0_itag(rv0_instr_i0_itag), + .rv0_instr_i0_ord(rv0_instr_i0_ord), + .rv0_instr_i0_cord(rv0_instr_i0_cord), + .rv0_instr_i0_spec(rv0_instr_i0_spec), + .rv0_instr_i0_s1_dep_hit(rv0_i0_s1_dep_hit), + .rv0_instr_i0_s1_itag(rv0_i0_s1_itag), + .rv0_instr_i0_s2_dep_hit(rv0_instr_i0_s2_dep_hit), + .rv0_instr_i0_s2_itag(rv0_instr_i0_s2_itag), + .rv0_instr_i0_s3_dep_hit(rv0_instr_i0_s3_dep_hit), + .rv0_instr_i0_s3_itag(rv0_instr_i0_s3_itag), + .rv0_instr_i0_is_brick(rv0_instr_i0_is_brick), + .rv0_instr_i0_brick(rv0_instr_i0_brick), + .rv0_instr_i0_ilat(rv0_instr_i0_ilat), + .rv0_instr_i0_s1_v(rv0_i0_s1_v), //swap + .rv0_instr_i0_s2_v(rv0_instr_i0_s2_v), + .rv0_instr_i0_s3_v(rv0_instr_i0_s3_v), + + .rv0_instr_i1_dat(rv0_instr_i1_dat), + .rv0_instr_i1_dat_ex0(rv0_instr_i1_dat_ex0), + .rv0_instr_i1_itag(rv0_instr_i1_itag), + .rv0_instr_i1_ord(rv0_instr_i1_ord), + .rv0_instr_i1_cord(rv0_instr_i1_cord), + .rv0_instr_i1_spec(rv0_instr_i1_spec), + .rv0_instr_i1_s1_dep_hit(rv0_i1_s1_dep_hit), + .rv0_instr_i1_s1_itag(rv0_i1_s1_itag), + .rv0_instr_i1_s2_dep_hit(rv0_instr_i1_s2_dep_hit), + .rv0_instr_i1_s2_itag(rv0_instr_i1_s2_itag), + .rv0_instr_i1_s3_dep_hit(rv0_instr_i1_s3_dep_hit), + .rv0_instr_i1_s3_itag(rv0_instr_i1_s3_itag), + .rv0_instr_i1_is_brick(rv0_instr_i1_is_brick), + .rv0_instr_i1_brick(rv0_instr_i1_brick), + .rv0_instr_i1_ilat(rv0_instr_i1_ilat), + .rv0_instr_i1_s1_v(rv0_i1_s1_v), //swap + .rv0_instr_i1_s2_v(rv0_instr_i1_s2_v), + .rv0_instr_i1_s3_v(rv0_instr_i1_s3_v), + + .rv1_instr_vld(rv1_instr_v), + .rv1_instr_dat(rv1_instr_dat), + .rv1_instr_ord(rv1_instr_ord), + .rv1_instr_spec(rv1_instr_spec), + .rv1_instr_itag(rv1_instr_itag), + .rv1_instr_ilat(rv1_instr_ilat), + .rv1_instr_ilat0_vld(rv1_instr_ilat0_vld), + .rv1_instr_ilat1_vld(rv1_instr_ilat1_vld), + .rv1_instr_s1_itag(rv1_instr_s1_itag), + .rv1_instr_s2_itag(rv1_instr_s2_itag), + .rv1_instr_s3_itag(rv1_instr_s3_itag), + .ex0_instr_dat(ex0_instr_dat), + .ex1_credit_free(ex1_credit_free), + .rv1_instr_is_brick(rv1_instr_is_brick), + + .rv1_other_ilat0_vld(rv1_fx0_ilat0_vld), + .rv1_other_ilat0_itag(rv1_fx0_ilat0_itag), + .rv1_other_ilat0_vld_out(rv1_fx1_ilat0_vld), + .rv1_other_ilat0_itag_out(rv1_fx1_ilat0_itag), + + .q_hold_all(fx1_rv_hold_all), + .q_ord_complete(fx1_rv_ord_complete), + + .fx0_rv_itag (fx0_rv_itag), + .fx1_rv_itag (fx1_rv_itag), + .lq_rv_itag0 (lq_rv_ext_itag0), + .lq_rv_itag1 (lq_rv_ext_itag1), + .lq_rv_itag2 (lq_rv_ext_itag2), + .axu0_rv_itag (axu0_rv_ext_itag), + .axu1_rv_itag (axu1_rv_ext_itag), + .fx0_rv_itag_vld (fx0_rv_itag_vld), + .fx1_rv_itag_vld (fx1_rv_itag_vld), + .lq_rv_itag0_vld (lq_rv_ext_itag0_vld), + .lq_rv_itag1_vld (lq_rv_ext_itag1_vld), + .lq_rv_itag2_vld (lq_rv_ext_itag2_vld), + .axu0_rv_itag_vld (axu0_rv_ext_itag_vld), + .axu1_rv_itag_vld (axu1_rv_ext_itag_vld), + .fx0_rv_itag_abort (fx0_rv_itag_abort), + .fx1_rv_itag_abort (fx1_rv_itag_abort), + .lq_rv_itag0_abort (lq_rv_ext_itag0_abort), + .lq_rv_itag1_abort (lq_rv_ext_itag1_abort), + .axu0_rv_itag_abort (axu0_rv_ext_itag_abort), + .axu1_rv_itag_abort (axu1_rv_ext_itag_abort), + + .xx_rv_ex2_s1_abort(fx1_rv_ex2_s1_abort), + .xx_rv_ex2_s2_abort(fx1_rv_ex2_s2_abort), + .xx_rv_ex2_s3_abort(fx1_rv_ex2_s3_abort), + + .lq_rv_itag1_restart(lq_rv_itag1_restart), + .lq_rv_itag1_hold(lq_rv_itag1_hold), + .lq_rv_itag1_cord(lq_rv_itag1_cord), + .lq_rv_itag1_rst_vld(lq_rv_itag1_rst_vld), + .lq_rv_itag1_rst(lq_rv_itag1_rst), + .lq_rv_clr_hold(lq_rv_clr_hold), + + .rvs_perf_bus(fx1_rvs_perf_bus), + .rvs_dbg_bus(fx1_rvs_dbg_bus), + .q_ord_tid(q_ord_tid), + .rvs_empty(rvs_empty), + + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .sg_1(sg_1), + .func_sl_thold_1(func_sl_thold_1), + .ccflush_dc(ccflush_dc), + .act_dis(act_dis), + .clkoff_b(clkoff_b), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scan_in(siv[rvs_offset]), + .scan_out(sov[rvs_offset]) + ); + + assign rv_iu_fx1_credit_free = ex1_credit_free; + + assign rv_fx1_vld = rv1_instr_v; + assign rv_fx1_s1_v = rv1_instr_dat[rvfx1_s1_v_start]; + assign rv_fx1_s1_p = rv1_instr_dat[rvfx1_s1_p_start:rvfx1_s1_p_stop]; + assign rv_fx1_s2_v = rv1_instr_dat[rvfx1_s2_v_start]; + assign rv_fx1_s2_p = rv1_instr_dat[rvfx1_s2_p_start:rvfx1_s2_p_stop]; + assign rv_fx1_s3_v = rv1_instr_dat[rvfx1_s3_v_start]; + assign rv_fx1_s3_p = rv1_instr_dat[rvfx1_s3_p_start:rvfx1_s3_p_stop]; + + assign rv_byp_fx1_vld = rv1_instr_v; + assign rv_byp_fx1_itag = rv1_instr_itag; + + assign rv_byp_fx1_s1_itag = rv1_instr_s1_itag; + assign rv_byp_fx1_s2_itag = rv1_instr_s2_itag; + assign rv_byp_fx1_s3_itag = rv1_instr_s3_itag; + + assign rv_byp_fx1_t1_v = rv1_instr_dat[rvfx1_t1_v_start]; + assign rv_byp_fx1_t2_v = rv1_instr_dat[rvfx1_t2_v_start]; + assign rv_byp_fx1_t3_v = rv1_instr_dat[rvfx1_t3_v_start]; + assign rv_byp_fx1_s1_t = rv1_instr_dat[rvfx1_s1_t_start:rvfx1_s1_t_stop]; + assign rv_byp_fx1_s2_t = rv1_instr_dat[rvfx1_s2_t_start:rvfx1_s2_t_stop]; + assign rv_byp_fx1_s3_t = rv1_instr_dat[rvfx1_s3_t_start:rvfx1_s3_t_stop]; + assign rv_byp_fx1_ilat = rv1_instr_ilat; + assign rv_byp_fx1_ilat0_vld = rv1_instr_ilat0_vld; + assign rv_byp_fx1_ilat1_vld = rv1_instr_ilat1_vld; + + assign rv_ex0_act = |(rv1_instr_v); + + assign rv_fx1_ex0_instr = ex0_instr_dat[rvfx1_instr_start:rvfx1_instr_stop]; + assign rv_fx1_ex0_ucode = ex0_instr_dat[rvfx1_ucode_start:rvfx1_ucode_stop]; + assign rv_fx1_ex0_t1_p = ex0_instr_dat[rvfx1_t1_p_start:rvfx1_t1_p_stop]; + assign rv_fx1_ex0_t2_p = ex0_instr_dat[rvfx1_t2_p_start:rvfx1_t2_p_stop]; + assign rv_fx1_ex0_t3_p = ex0_instr_dat[rvfx1_t3_p_start:rvfx1_t3_p_stop]; + assign rv_byp_fx1_ex0_isStore = ex0_instr_dat[rvfx1_isStore_start]; + assign rv_fx1_ex0_isStore = ex0_instr_dat[rvfx1_isStore_start]; + + assign ex0_itag_d = rv1_instr_itag; + assign ex0_t1_v_d = rv1_instr_dat[rvfx1_t1_v_start]; + assign ex0_t2_v_d = rv1_instr_dat[rvfx1_t2_v_start]; + assign ex0_t3_v_d = rv1_instr_dat[rvfx1_t3_v_start]; + assign ex0_s1_v_d = rv1_instr_dat[rvfx1_s1_v_start]; + assign ex0_s3_t_d = rv1_instr_dat[rvfx1_s3_t_start:rvfx1_s3_t_stop]; + + assign rv_fx1_ex0_itag = ex0_itag_q; + assign rv_fx1_ex0_t1_v = ex0_t1_v_q; + assign rv_fx1_ex0_t2_v = ex0_t2_v_q; + assign rv_fx1_ex0_t3_v = ex0_t3_v_q; + assign rv_fx1_ex0_s1_v = ex0_s1_v_q; + assign rv_fx1_ex0_s3_t = ex0_s3_t_q; + + //------------------------------------------------------------------------------------------------------------ + // Itag busses + //------------------------------------------------------------------------------------------------------------ + + // Restart Itag and Valid from LQ. This is separate because it could be early (not latched) + assign lq_rv_itag1_rst_vld = lq_rv_itag1_vld; + assign lq_rv_itag1_rst = lq_rv_itag1; + + //------------------------------------------------------------------------------------------------------------ + // Pipeline Latches + //------------------------------------------------------------------------------------------------------------ + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) + ex0_itag_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rv_ex0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[ex0_itag_offset:ex0_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[ex0_itag_offset:ex0_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(ex0_itag_d), + .dout(ex0_itag_q) + ); + + + + tri_rlmlatch_p #(.INIT(0)) + ex0_t1_v_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rv_ex0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[ex0_t1_v_offset]), + .scout(sov[ex0_t1_v_offset]), + .din(ex0_t1_v_d), + .dout(ex0_t1_v_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) + ex0_t2_v_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rv_ex0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[ex0_t2_v_offset]), + .scout(sov[ex0_t2_v_offset]), + .din(ex0_t2_v_d), + .dout(ex0_t2_v_q) + ); + + + + tri_rlmlatch_p #(.INIT(0)) ex0_t3_v_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rv_ex0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[ex0_t3_v_offset]), + .scout(sov[ex0_t3_v_offset]), + .din(ex0_t3_v_d), + .dout(ex0_t3_v_q) + ); + + + + tri_rlmlatch_p #(.INIT(0)) ex0_s1_v_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rv_ex0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[ex0_s1_v_offset]), + .scout(sov[ex0_s1_v_offset]), + .din(ex0_s1_v_d), + .dout(ex0_s1_v_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) ex0_s3_t_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rv_ex0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[ex0_s3_t_offset:ex0_s3_t_offset + 3 - 1]), + .scout(sov[ex0_s3_t_offset:ex0_s3_t_offset + 3 - 1]), + .din(ex0_s3_t_d), + .dout(ex0_s3_t_q) + ); + + + + + //------------------------------------------------------------------------------------------------------------ + // Scan Connections + //------------------------------------------------------------------------------------------------------------ + + assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in}; + assign scan_out = sov[0]; + + //----------------------------------------------- + // pervasive + //----------------------------------------------- + + + tri_plat #(.WIDTH(2)) + perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(ccflush_dc), + .din({func_sl_thold_1, sg_1}), + .q({func_sl_thold_0, sg_0}) + ); + + + tri_lcbor + perv_lcbor( + .clkoff_b(clkoff_b), + .thold(func_sl_thold_0), + .sg(sg_0), + .act_dis(act_dis), + .force_t(force_t), + .thold_b(func_sl_thold_0_b) + ); + +endmodule diff --git a/dev/verilog/work/rv_lq_rvs.v b/dev/verilog/work/rv_lq_rvs.v new file mode 100755 index 0000000..d0c4159 --- /dev/null +++ b/dev/verilog/work/rv_lq_rvs.v @@ -0,0 +1,1075 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//----------------------------------------------------------------------------------------------------- +// Title: rv_lq_rvs.vhdl +// Desc: LQ Reservation Station +// +//----------------------------------------------------------------------------------------------------- + +module rv_lq_rvs( +`include "tri_a2o.vh" + + //------------------------------------------------------------------------------------------------------------ + // Instructions from RV_DEP + //------------------------------------------------------------------------------------------------------------ + input [0:`THREADS-1] rv0_instr_i0_vld, + input rv0_instr_i0_rte, + input [0:31] rv0_instr_i0_instr, + input [0:2] rv0_instr_i0_ucode, + input [0:`UCODE_ENTRIES_ENC-1] rv0_instr_i0_ucode_cnt, + input [0:`ITAG_SIZE_ENC-1] rv0_instr_i0_itag, + input rv0_instr_i0_ord, + input rv0_instr_i0_cord, + input rv0_instr_i0_spec, + input rv0_instr_i0_t1_v, + input [0:`GPR_POOL_ENC-1] rv0_instr_i0_t1_p, + input rv0_instr_i0_t2_v, + input [0:`GPR_POOL_ENC-1] rv0_instr_i0_t2_p, + input [0:2] rv0_instr_i0_t2_t, + input rv0_instr_i0_t3_v, + input [0:`GPR_POOL_ENC-1] rv0_instr_i0_t3_p, + input [0:2] rv0_instr_i0_t3_t, + input rv0_instr_i0_s1_v, + input [0:`GPR_POOL_ENC-1] rv0_instr_i0_s1_p, + input [0:2] rv0_instr_i0_s1_t, + input rv0_instr_i0_s2_v, + input [0:`GPR_POOL_ENC-1] rv0_instr_i0_s2_p, + input [0:2] rv0_instr_i0_s2_t, + input rv0_instr_i0_isLoad, + input [0:3] rv0_instr_i0_spare, + input rv0_instr_i0_is_brick, + input [0:2] rv0_instr_i0_brick, + + input [0:`THREADS-1] rv0_instr_i1_vld, + input rv0_instr_i1_rte, + input [0:31] rv0_instr_i1_instr, + input [0:2] rv0_instr_i1_ucode, + input [0:`UCODE_ENTRIES_ENC-1] rv0_instr_i1_ucode_cnt, + input [0:`ITAG_SIZE_ENC-1] rv0_instr_i1_itag, + input rv0_instr_i1_ord, + input rv0_instr_i1_cord, + input rv0_instr_i1_spec, + input rv0_instr_i1_t1_v, + input [0:`GPR_POOL_ENC-1] rv0_instr_i1_t1_p, + input rv0_instr_i1_t2_v, + input [0:`GPR_POOL_ENC-1] rv0_instr_i1_t2_p, + input [0:2] rv0_instr_i1_t2_t, + input rv0_instr_i1_t3_v, + input [0:`GPR_POOL_ENC-1] rv0_instr_i1_t3_p, + input [0:2] rv0_instr_i1_t3_t, + input rv0_instr_i1_s1_v, + input [0:`GPR_POOL_ENC-1] rv0_instr_i1_s1_p, + input [0:2] rv0_instr_i1_s1_t, + input rv0_instr_i1_s2_v, + input [0:`GPR_POOL_ENC-1] rv0_instr_i1_s2_p, + input [0:2] rv0_instr_i1_s2_t, + input rv0_instr_i1_isLoad, + input [0:3] rv0_instr_i1_spare, + input rv0_instr_i1_is_brick, + input [0:2] rv0_instr_i1_brick, + + input rv0_instr_i0_s1_dep_hit, + input [0:`ITAG_SIZE_ENC-1] rv0_instr_i0_s1_itag, + input rv0_instr_i0_s2_dep_hit, + input [0:`ITAG_SIZE_ENC-1] rv0_instr_i0_s2_itag, + + input rv0_instr_i1_s1_dep_hit, + input [0:`ITAG_SIZE_ENC-1] rv0_instr_i1_s1_itag, + input rv0_instr_i1_s2_dep_hit, + input [0:`ITAG_SIZE_ENC-1] rv0_instr_i1_s2_itag, + + //------------------------------------------------------------------------------------------------------------ + // Credit Interface with IU + //------------------------------------------------------------------------------------------------------------ + output [0:`THREADS-1] rv_iu_lq_credit_free, + + //------------------------------------------------------------------------------------------------------------ + // Machine zap interface + //------------------------------------------------------------------------------------------------------------ + input [0:`THREADS-1] cp_flush, + input [0:`THREADS*`ITAG_SIZE_ENC-1] cp_next_itag, + + //------------------------------------------------------------------------------------------------------------ + // Interface to LQ + //------------------------------------------------------------------------------------------------------------ + output [0:`THREADS-1] rv_lq_vld, + output [0:`ITAG_SIZE_ENC-1] rv_lq_itag, + output rv_lq_isLoad, + + output rv_lq_t1_v, + output rv_lq_t3_v, + output [0:2] rv_lq_t3_t, + + output rv_lq_s1_v, + output [0:`GPR_POOL_ENC-1] rv_lq_s1_p, + output [0:2] rv_lq_s1_t, + output rv_lq_s2_v, + output [0:`GPR_POOL_ENC-1] rv_lq_s2_p, + output [0:2] rv_lq_s2_t, + + output [0:`ITAG_SIZE_ENC-1] rv_lq_ex0_s1_itag, + output [0:`ITAG_SIZE_ENC-1] rv_lq_ex0_s2_itag, + + output [0:`ITAG_SIZE_ENC-1] rv_lq_ex0_itag, + output [0:31] rv_lq_ex0_instr, + output [0:2] rv_lq_ex0_ucode, + output [0:`UCODE_ENTRIES_ENC-1] rv_lq_ex0_ucode_cnt, + output rv_lq_ex0_spec, + + output rv_lq_ex0_t1_v, + output [0:`GPR_POOL_ENC-1] rv_lq_ex0_t1_p, + output [0:`GPR_POOL_ENC-1] rv_lq_ex0_t3_p, + output rv_lq_ex0_s1_v, + output rv_lq_ex0_s2_v, + output [0:2] rv_lq_ex0_s2_t, + + output [0:`THREADS-1] rv_lq_rvs_empty, + + //------------------------------------------------------------------------------------------------------------ + // RV Release bus + //------------------------------------------------------------------------------------------------------------ + + input lq_rv_ex2_s1_abort, + input lq_rv_ex2_s2_abort, + + + input fx0_rv_ext_itag_abort, + input fx1_rv_ext_itag_abort, + input lq_rv_itag0_abort, + input lq_rv_itag1_abort, + input axu0_rv_ext_itag_abort, + input axu1_rv_ext_itag_abort, + + input [0:`THREADS-1] fx0_rv_ext_itag_vld, + input [0:`ITAG_SIZE_ENC-1] fx0_rv_ext_itag, + + input [0:`THREADS-1] fx1_rv_ext_itag_vld, + input [0:`ITAG_SIZE_ENC-1] fx1_rv_ext_itag, + + input [0:`THREADS-1] axu0_rv_ext_itag_vld, + input [0:`ITAG_SIZE_ENC-1] axu0_rv_ext_itag, + + input [0:`THREADS-1] axu1_rv_ext_itag_vld, + input [0:`ITAG_SIZE_ENC-1] axu1_rv_ext_itag, + + input [0:`THREADS-1] lq_rv_itag0_vld, + input [0:`ITAG_SIZE_ENC-1] lq_rv_itag0, + + input [0:`THREADS-1] lq_rv_itag1_vld, + input [0:`ITAG_SIZE_ENC-1] lq_rv_itag1, + input lq_rv_itag1_restart, + input lq_rv_itag1_hold, + input lq_rv_itag1_cord, + + input [0:`THREADS-1] lq_rv_itag2_vld, + input [0:`ITAG_SIZE_ENC-1] lq_rv_itag2, + + input [0:`THREADS-1] lq_rv_clr_hold, + + input lq_rv_ord_complete, + input lq_rv_hold_all, + + // Latched releases for stations requiring additional delay + output [0:`THREADS-1] lq_rv_ext_itag0_vld, + output [0:`THREADS-1] lq_rv_ext_itag1_vld, + output [0:`THREADS-1] lq_rv_ext_itag2_vld, + + output lq_rv_ext_itag0_abort, + output lq_rv_ext_itag1_abort, + + output [0:`ITAG_SIZE_ENC-1] lq_rv_ext_itag0, + output [0:`ITAG_SIZE_ENC-1] lq_rv_ext_itag1, + output [0:`ITAG_SIZE_ENC-1] lq_rv_ext_itag2, + + + //------------------------------------------------------------------------------------------------------------ + // Pervasive + //------------------------------------------------------------------------------------------------------------ + output [0:8*`THREADS-1] lq_rvs_perf_bus, + output [0:31] lq_rvs_dbg_bus, + + inout vdd, + inout gnd, + (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) // nclk + input [0:`NCLK_WIDTH-1] nclk, + + input func_sl_thold_1, + input sg_1, + input clkoff_b, + input act_dis, + input ccflush_dc, + input d_mode, + input delay_lclkr, + input mpw1_b, + input mpw2_b, + input scan_in, + + output scan_out + + ); + + parameter num_itag_busses_g = 7; + + + + + //------------------------------------------------------------------------------------------------------------ + // RV LQ RVS INSTR ISSUE + //------------------------------------------------------------------------------------------------------------ + parameter rvlq_ex0_start = 0; + + parameter rvlq_instr_start = rvlq_ex0_start; + parameter rvlq_instr_stop = (rvlq_instr_start + (32)) - 1; + parameter rvlq_ucode_start = rvlq_instr_stop + 1; + parameter rvlq_ucode_stop = (rvlq_ucode_start + (3)) - 1; + parameter rvlq_ucode_cnt_start = rvlq_ucode_stop + 1; + parameter rvlq_ucode_cnt_stop = (rvlq_ucode_cnt_start + (`UCODE_ENTRIES_ENC)) - 1; + parameter rvlq_t1_p_start = rvlq_ucode_cnt_stop + 1; + parameter rvlq_t1_p_stop = (rvlq_t1_p_start + (`GPR_POOL_ENC)) - 1; + parameter rvlq_t3_p_start = rvlq_t1_p_stop + 1; + parameter rvlq_t3_p_stop = (rvlq_t3_p_start + (`GPR_POOL_ENC)) - 1; + parameter rvlq_spare_start = rvlq_t3_p_stop + 1; + parameter rvlq_spare_stop = (rvlq_spare_start + (4)) - 1; + + parameter rvlq_ex0_end = rvlq_spare_stop; + + parameter rvlq_ex0_size = rvlq_ex0_end + 1; + + parameter rvlq_start = 0; + parameter rvlq_t1_v_start = rvlq_start; + parameter rvlq_t1_v_stop = (rvlq_t1_v_start + (1)) - 1; + parameter rvlq_t3_v_start = rvlq_t1_v_stop + 1; + parameter rvlq_t3_v_stop = (rvlq_t3_v_start + (1)) - 1; + parameter rvlq_t3_t_start = rvlq_t3_v_stop + 1; + parameter rvlq_t3_t_stop = (rvlq_t3_t_start + (3)) - 1; + parameter rvlq_s1_v_start = rvlq_t3_t_stop + 1; + parameter rvlq_s1_v_stop = (rvlq_s1_v_start + (1)) - 1; + parameter rvlq_s1_p_start = rvlq_s1_v_stop + 1; + parameter rvlq_s1_p_stop = (rvlq_s1_p_start + (`GPR_POOL_ENC)) - 1; + parameter rvlq_s1_t_start = rvlq_s1_p_stop + 1; + parameter rvlq_s1_t_stop = (rvlq_s1_t_start + (3)) - 1; + parameter rvlq_s2_v_start = rvlq_s1_t_stop + 1; + parameter rvlq_s2_v_stop = (rvlq_s2_v_start + (1)) - 1; + parameter rvlq_s2_p_start = rvlq_s2_v_stop + 1; + parameter rvlq_s2_p_stop = (rvlq_s2_p_start + (`GPR_POOL_ENC)) - 1; + parameter rvlq_s2_t_start = rvlq_s2_p_stop + 1; + parameter rvlq_s2_t_stop = (rvlq_s2_t_start + (3)) - 1; + parameter rvlq_isLoad_start = rvlq_s2_t_stop + 1; + parameter rvlq_isLoad_stop = (rvlq_isLoad_start + (1)) - 1; + + parameter rvlq_end = rvlq_isLoad_stop; + + parameter rvlq_size = rvlq_end + 1; + + //------------------------------------------------------------------------------------------------------------ + // Pervasive + //------------------------------------------------------------------------------------------------------------ + + + + wire tiup; + + wire [rvlq_start:rvlq_end] rv0_instr_i0_dat; + wire [rvlq_start:rvlq_end] rv0_instr_i1_dat; + wire [rvlq_ex0_start:rvlq_ex0_end] rv0_instr_i0_dat_ex0; + wire [rvlq_ex0_start:rvlq_ex0_end] rv0_instr_i1_dat_ex0; + + wire [0:3] rv0_instr_i0_ilat; + wire [0:3] rv0_instr_i1_ilat; + + wire rv0_instr_i0_s3_dep_hit; + wire [0:`ITAG_SIZE_ENC-1] rv0_instr_i0_s3_itag; + wire rv0_instr_i1_s3_dep_hit; + wire [0:`ITAG_SIZE_ENC-1] rv0_instr_i1_s3_itag; + wire lq_rv_ex2_s3_abort; + wire rv0_instr_i0_s3_v; + wire rv0_instr_i1_s3_v; + + wire rv0_i0_t3_v; + wire [0:`GPR_POOL_ENC-1] rv0_i0_t3_p; + wire [0:2] rv0_i0_t3_t; + wire rv0_i1_t3_v; + wire [0:`GPR_POOL_ENC-1] rv0_i1_t3_p; + wire [0:2] rv0_i1_t3_t; + + //------------------------------------------------------------------------------------------------------------ + // RV2 + //------------------------------------------------------------------------------------------------------------ + + wire [rvlq_start:rvlq_end] rv1_instr_dat; + wire [0:`THREADS-1] rv1_instr_v; + wire rv1_instr_spec; + (* analysis_not_referenced="true" *) + wire [0:3] rv1_instr_ilat; + wire [0:`ITAG_SIZE_ENC-1] rv1_instr_itag; + wire [0:`ITAG_SIZE_ENC-1] rv1_instr_s1_itag; + wire [0:`ITAG_SIZE_ENC-1] rv1_instr_s2_itag; + (* analysis_not_referenced="true" *) + wire [0:`ITAG_SIZE_ENC-1] rv1_instr_s3_itag; + wire [0:`THREADS-1] ex1_credit_free; + (* analysis_not_referenced="true" *) + wire rv1_instr_is_brick; + + + wire [0:`THREADS-1] rv1_other_ilat0_vld; + wire [0:`ITAG_SIZE_ENC-1] rv1_other_ilat0_itag; + (* analysis_not_referenced="true" *) + wire [0:`THREADS-1] rv1_instr_ilat0_vld; + (* analysis_not_referenced="true" *) + wire [0:`THREADS-1] rv1_instr_ilat1_vld; + + //------------------------------------------------------------------------------------------------------------ + // EX0 + //------------------------------------------------------------------------------------------------------------ + wire rv_ex0_act; + + (* analysis_not_referenced="<50:53>true" *) + wire [rvlq_ex0_start:rvlq_ex0_end] ex0_instr_dat; + wire [0:`ITAG_SIZE_ENC-1] ex0_s1_itag_d; + wire [0:`ITAG_SIZE_ENC-1] ex0_s2_itag_d; + wire [0:`ITAG_SIZE_ENC-1] ex0_itag_d; + wire ex0_spec_d; + wire ex0_t1_v_d; + wire ex0_s1_v_d; + wire ex0_s2_v_d; + wire [0:2] ex0_s2_t_d; + + wire [0:`ITAG_SIZE_ENC-1] ex0_s1_itag_q; + wire [0:`ITAG_SIZE_ENC-1] ex0_s2_itag_q; + wire [0:`ITAG_SIZE_ENC-1] ex0_itag_q; + wire ex0_spec_q; + wire ex0_t1_v_q; + wire ex0_s1_v_q; + wire ex0_s2_v_q; + wire [0:2] ex0_s2_t_q; + + //------------------------------------------------------------------------------------------------------------ + // Itag busses and shadow + //------------------------------------------------------------------------------------------------------------ + + wire [0:`THREADS-1] lq_rv_itag1_rst_vld; + wire [0:`ITAG_SIZE_ENC-1] lq_rv_itag1_rst; + + wire [0:`THREADS-1] q_ord_complete; + + wire [0:`THREADS-1] lq_rv_ext_itag0_vld_d; + wire [0:`THREADS-1] lq_rv_ext_itag1_vld_d; + wire [0:`THREADS-1] lq_rv_ext_itag2_vld_d; + + wire [0:`THREADS*`ITAG_SIZE_ENC-1] cp_next_itag_q; + wire [0:`THREADS-1] cp_flush_q; + + wire [0:`THREADS-1] rvs_empty; + + //------------------------------------------------------------------------------------------------------------ + // Scan Chains + //------------------------------------------------------------------------------------------------------------ + parameter rvs_offset = 0 + 0; + parameter cp_flush_offset = rvs_offset + 1; + parameter ex0_s1_itag_offset = cp_flush_offset + `THREADS; + parameter ex0_s2_itag_offset = ex0_s1_itag_offset + `ITAG_SIZE_ENC; + parameter ex0_itag_offset = ex0_s2_itag_offset + `ITAG_SIZE_ENC; + parameter ex0_spec_offset = ex0_itag_offset + `ITAG_SIZE_ENC; + parameter ex0_t1_v_offset = ex0_spec_offset + 1; + parameter ex0_s1_v_offset = ex0_t1_v_offset + 1; + parameter ex0_s2_v_offset = ex0_s1_v_offset + 1; + parameter ex0_s2_t_offset = ex0_s2_v_offset + 1; + parameter lq_rv_ext_itag0_vld_offset = ex0_s2_t_offset + 3; + parameter lq_rv_ext_itag0_abort_offset = lq_rv_ext_itag0_vld_offset + `THREADS; + parameter lq_rv_ext_itag0_offset = lq_rv_ext_itag0_abort_offset +1; + parameter lq_rv_ext_itag1_vld_offset = lq_rv_ext_itag0_offset + `ITAG_SIZE_ENC; + parameter lq_rv_ext_itag1_abort_offset = lq_rv_ext_itag1_vld_offset + `THREADS; + parameter lq_rv_ext_itag1_offset = lq_rv_ext_itag1_abort_offset +1; + parameter lq_rv_ext_itag2_vld_offset = lq_rv_ext_itag1_offset + `ITAG_SIZE_ENC; + parameter lq_rv_ext_itag2_offset = lq_rv_ext_itag2_vld_offset +`THREADS; + + parameter cp_next_itag_offset = lq_rv_ext_itag2_offset + `ITAG_SIZE_ENC; + + parameter scan_right = cp_next_itag_offset + `THREADS * `ITAG_SIZE_ENC; + wire [0:scan_right-1] siv; + wire [0:scan_right-1] sov; + + wire func_sl_thold_0; + wire func_sl_thold_0_b; + wire sg_0; + wire force_t; + + //Unused Nets + (* analysis_not_referenced="true" *) + wire [0:`THREADS-1] q_ord_tid; + (* analysis_not_referenced="true" *) + wire [0:`THREADS-1] rv1_other_ilat0_vld_out; + (* analysis_not_referenced="true" *) + wire [0:`ITAG_SIZE_ENC-1] rv1_other_ilat0_itag_out; + (* analysis_not_referenced="true" *) + wire rv1_instr_ord; + + + //!! Bugspray Include: rv_lq_rvs; + + //------------------------------------------------------------------------------------------------------------ + // Pervasive + //------------------------------------------------------------------------------------------------------------ + assign tiup = 1'b1; + + // Floating point loads were the only target that used t2, so combining with t3 to save latches + assign rv0_i0_t3_v = rv0_instr_i0_t2_v | rv0_instr_i0_t3_v; + assign rv0_i0_t3_p = (rv0_instr_i0_t2_v == 1'b1) ? rv0_instr_i0_t2_p : + rv0_instr_i0_t3_p; + assign rv0_i0_t3_t = (rv0_instr_i0_t2_v == 1'b1) ? rv0_instr_i0_t2_t : + rv0_instr_i0_t3_t; + + assign rv0_i1_t3_v = rv0_instr_i1_t2_v | rv0_instr_i1_t3_v; + assign rv0_i1_t3_p = (rv0_instr_i1_t2_v == 1'b1) ? rv0_instr_i1_t2_p : + rv0_instr_i1_t3_p; + assign rv0_i1_t3_t = (rv0_instr_i1_t2_v == 1'b1) ? rv0_instr_i1_t2_t : + rv0_instr_i1_t3_t; + + //------------------------------------------------------------------------------------------------------------ + // RV Entry + //------------------------------------------------------------------------------------------------------------ + + assign rv0_instr_i0_dat = { + rv0_instr_i0_t1_v, + rv0_i0_t3_v, + rv0_i0_t3_t, + rv0_instr_i0_s1_v, + rv0_instr_i0_s1_p, + rv0_instr_i0_s1_t, + rv0_instr_i0_s2_v, + rv0_instr_i0_s2_p, + rv0_instr_i0_s2_t, + rv0_instr_i0_isLoad}; + + assign rv0_instr_i0_dat_ex0 = { + rv0_instr_i0_instr, + rv0_instr_i0_ucode, + rv0_instr_i0_ucode_cnt, + rv0_instr_i0_t1_p, + rv0_i0_t3_p, + rv0_instr_i0_spare}; + + assign rv0_instr_i1_dat = { + rv0_instr_i1_t1_v, + rv0_i1_t3_v, + rv0_i1_t3_t, + rv0_instr_i1_s1_v, + rv0_instr_i1_s1_p, + rv0_instr_i1_s1_t, + rv0_instr_i1_s2_v, + rv0_instr_i1_s2_p, + rv0_instr_i1_s2_t, + rv0_instr_i1_isLoad}; + + assign rv0_instr_i1_dat_ex0 = { + rv0_instr_i1_instr, + rv0_instr_i1_ucode, + rv0_instr_i1_ucode_cnt, + rv0_instr_i1_t1_p, + rv0_i1_t3_p, + rv0_instr_i1_spare}; + + + + //------------------------------------------------------------------------------------------------------------ + // LQ Reservation Stations + //------------------------------------------------------------------------------------------------------------ + + assign rv0_instr_i0_ilat = {4{1'b1}}; + assign rv0_instr_i1_ilat = {4{1'b1}}; + + assign rv0_instr_i0_s3_dep_hit = 1'b0; + assign rv0_instr_i0_s3_itag = {`ITAG_SIZE_ENC{1'b0}}; + assign rv0_instr_i1_s3_dep_hit = 1'b0; + assign rv0_instr_i1_s3_itag = {`ITAG_SIZE_ENC{1'b0}}; + assign lq_rv_ex2_s3_abort = 1'b0; + assign rv0_instr_i0_s3_v = 1'b0; + assign rv0_instr_i1_s3_v = 1'b0; + + assign rv1_other_ilat0_vld = {`THREADS{1'b0}}; + assign rv1_other_ilat0_itag = {`ITAG_SIZE_ENC{1'b0}}; + // AXU uses the ext fx rel bus, so it doesn't need the cancel + + assign q_ord_complete = {`THREADS{lq_rv_ord_complete}}; + + rv_station #( .q_dat_width_g(rvlq_size), .q_dat_ex0_width_g(rvlq_ex0_size), .q_num_entries_g(`RV_LQ_ENTRIES), .q_barf_enc_g(5), .q_lq_g(1'b1), .q_itag_busses_g(num_itag_busses_g), .q_noilat0_g(1'b1)) + rvs( + .cp_flush(cp_flush), + .cp_next_itag(cp_next_itag_q), + .rv0_instr_i0_vld(rv0_instr_i0_vld), + .rv0_instr_i0_rte(rv0_instr_i0_rte), + .rv0_instr_i1_vld(rv0_instr_i1_vld), + .rv0_instr_i1_rte(rv0_instr_i1_rte), + + .rv0_instr_i0_dat(rv0_instr_i0_dat), + .rv0_instr_i0_dat_ex0(rv0_instr_i0_dat_ex0), + .rv0_instr_i0_itag(rv0_instr_i0_itag), + .rv0_instr_i0_ord(rv0_instr_i0_ord), + .rv0_instr_i0_cord(rv0_instr_i0_cord), + .rv0_instr_i0_spec(rv0_instr_i0_spec), + .rv0_instr_i0_s1_dep_hit(rv0_instr_i0_s1_dep_hit), + .rv0_instr_i0_s1_itag(rv0_instr_i0_s1_itag), + .rv0_instr_i0_s2_dep_hit(rv0_instr_i0_s2_dep_hit), + .rv0_instr_i0_s2_itag(rv0_instr_i0_s2_itag), + .rv0_instr_i0_s3_dep_hit(rv0_instr_i0_s3_dep_hit), + .rv0_instr_i0_s3_itag(rv0_instr_i0_s3_itag), + .rv0_instr_i0_is_brick(rv0_instr_i0_is_brick), + .rv0_instr_i0_brick(rv0_instr_i0_brick), + .rv0_instr_i0_ilat(rv0_instr_i0_ilat), + .rv0_instr_i0_s1_v(rv0_instr_i0_s1_v), + .rv0_instr_i0_s2_v(rv0_instr_i0_s2_v), + .rv0_instr_i0_s3_v(rv0_instr_i0_s3_v), + + .rv0_instr_i1_dat(rv0_instr_i1_dat), + .rv0_instr_i1_dat_ex0(rv0_instr_i1_dat_ex0), + .rv0_instr_i1_itag(rv0_instr_i1_itag), + .rv0_instr_i1_ord(rv0_instr_i1_ord), + .rv0_instr_i1_cord(rv0_instr_i1_cord), + .rv0_instr_i1_spec(rv0_instr_i1_spec), + .rv0_instr_i1_s1_dep_hit(rv0_instr_i1_s1_dep_hit), + .rv0_instr_i1_s1_itag(rv0_instr_i1_s1_itag), + .rv0_instr_i1_s2_dep_hit(rv0_instr_i1_s2_dep_hit), + .rv0_instr_i1_s2_itag(rv0_instr_i1_s2_itag), + .rv0_instr_i1_s3_dep_hit(rv0_instr_i1_s3_dep_hit), + .rv0_instr_i1_s3_itag(rv0_instr_i1_s3_itag), + .rv0_instr_i1_is_brick(rv0_instr_i1_is_brick), + .rv0_instr_i1_brick(rv0_instr_i1_brick), + .rv0_instr_i1_ilat(rv0_instr_i1_ilat), + .rv0_instr_i1_s1_v(rv0_instr_i1_s1_v), + .rv0_instr_i1_s2_v(rv0_instr_i1_s2_v), + .rv0_instr_i1_s3_v(rv0_instr_i1_s3_v), + + .rv1_instr_vld(rv1_instr_v), + .rv1_instr_dat(rv1_instr_dat), + .rv1_instr_spec(rv1_instr_spec), + .rv1_instr_itag(rv1_instr_itag), + .rv1_instr_ilat(rv1_instr_ilat), + .rv1_instr_s1_itag(rv1_instr_s1_itag), + .rv1_instr_s2_itag(rv1_instr_s2_itag), + .rv1_instr_s3_itag(rv1_instr_s3_itag), + .rv1_instr_is_brick(rv1_instr_is_brick), + .ex0_instr_dat(ex0_instr_dat), + .ex1_credit_free(ex1_credit_free), + .rvs_empty(rvs_empty), + .rvs_perf_bus(lq_rvs_perf_bus), + .rvs_dbg_bus(lq_rvs_dbg_bus), + + .fx0_rv_itag (fx0_rv_ext_itag), + .fx1_rv_itag (fx1_rv_ext_itag), + .lq_rv_itag0 (lq_rv_itag0), + .lq_rv_itag1 (lq_rv_itag1), + .lq_rv_itag2 (lq_rv_itag2), + .axu0_rv_itag (axu0_rv_ext_itag), + .axu1_rv_itag (axu1_rv_ext_itag), + .fx0_rv_itag_vld (fx0_rv_ext_itag_vld), + .fx1_rv_itag_vld (fx1_rv_ext_itag_vld), + .lq_rv_itag0_vld (lq_rv_itag0_vld), + .lq_rv_itag1_vld (lq_rv_itag1_vld), + .lq_rv_itag2_vld (lq_rv_itag2_vld), + .axu0_rv_itag_vld (axu0_rv_ext_itag_vld), + .axu1_rv_itag_vld (axu1_rv_ext_itag_vld), + .fx0_rv_itag_abort (fx0_rv_ext_itag_abort), + .fx1_rv_itag_abort (fx1_rv_ext_itag_abort), + .lq_rv_itag0_abort (lq_rv_itag0_abort), + .lq_rv_itag1_abort (lq_rv_itag1_abort), + .axu0_rv_itag_abort (axu0_rv_ext_itag_abort), + .axu1_rv_itag_abort (axu1_rv_ext_itag_abort), + + .xx_rv_ex2_s1_abort(lq_rv_ex2_s1_abort), + .xx_rv_ex2_s2_abort(lq_rv_ex2_s2_abort), + .xx_rv_ex2_s3_abort(lq_rv_ex2_s3_abort), + + .rv1_other_ilat0_vld(rv1_other_ilat0_vld), + .rv1_other_ilat0_itag(rv1_other_ilat0_itag), + .rv1_instr_ilat0_vld(rv1_instr_ilat0_vld), + .rv1_instr_ilat1_vld(rv1_instr_ilat1_vld), + + .q_hold_all(lq_rv_hold_all), + .q_ord_complete(q_ord_complete), + .q_ord_tid(q_ord_tid), + .rv1_other_ilat0_vld_out(rv1_other_ilat0_vld_out), + .rv1_other_ilat0_itag_out(rv1_other_ilat0_itag_out), + .rv1_instr_ord(rv1_instr_ord), + + .lq_rv_itag1_restart(lq_rv_itag1_restart), + .lq_rv_itag1_hold(lq_rv_itag1_hold), + .lq_rv_itag1_cord(lq_rv_itag1_cord), + .lq_rv_itag1_rst_vld(lq_rv_itag1_rst_vld), + .lq_rv_itag1_rst(lq_rv_itag1_rst), + .lq_rv_clr_hold(lq_rv_clr_hold), + + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .sg_1(sg_1), + .func_sl_thold_1(func_sl_thold_1), + .ccflush_dc(ccflush_dc), + .act_dis(act_dis), + .clkoff_b(clkoff_b), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scan_in(siv[rvs_offset]), + .scan_out(sov[rvs_offset]) + ); + + assign rv_iu_lq_credit_free = ex1_credit_free; + assign rv_lq_rvs_empty = rvs_empty; + + assign rv_lq_vld = rv1_instr_v; + + assign rv_lq_itag = rv1_instr_itag; + assign rv_lq_isLoad = rv1_instr_dat[rvlq_isLoad_start]; + + assign rv_lq_t1_v = rv1_instr_dat[rvlq_t1_v_start]; + assign rv_lq_t3_v = rv1_instr_dat[rvlq_t3_v_start]; + assign rv_lq_t3_t = rv1_instr_dat[rvlq_t3_t_start:rvlq_t3_t_stop]; + assign rv_lq_s1_v = rv1_instr_dat[rvlq_s1_v_start]; + assign rv_lq_s1_p = rv1_instr_dat[rvlq_s1_p_start:rvlq_s1_p_stop]; + assign rv_lq_s1_t = rv1_instr_dat[rvlq_s1_t_start:rvlq_s1_t_stop]; + assign rv_lq_s2_v = rv1_instr_dat[rvlq_s2_v_start]; + assign rv_lq_s2_p = rv1_instr_dat[rvlq_s2_p_start:rvlq_s2_p_stop]; + assign rv_lq_s2_t = rv1_instr_dat[rvlq_s2_t_start:rvlq_s2_t_stop]; + + assign ex0_itag_d = rv1_instr_itag; + assign ex0_spec_d = rv1_instr_spec; + assign ex0_t1_v_d = rv1_instr_dat[rvlq_t1_v_start]; + assign ex0_s1_v_d = rv1_instr_dat[rvlq_s1_v_start]; + assign ex0_s2_v_d = rv1_instr_dat[rvlq_s2_v_start]; + assign ex0_s2_t_d = rv1_instr_dat[rvlq_s2_t_start:rvlq_s2_t_stop]; + assign ex0_s1_itag_d = rv1_instr_s1_itag; + assign ex0_s2_itag_d = rv1_instr_s2_itag; + + assign rv_ex0_act = |(rv1_instr_v); + + + assign rv_lq_ex0_instr = ex0_instr_dat[rvlq_instr_start:rvlq_instr_stop]; + assign rv_lq_ex0_ucode = ex0_instr_dat[rvlq_ucode_start:rvlq_ucode_stop]; + assign rv_lq_ex0_ucode_cnt = ex0_instr_dat[rvlq_ucode_cnt_start:rvlq_ucode_cnt_stop]; + assign rv_lq_ex0_t1_p = ex0_instr_dat[rvlq_t1_p_start:rvlq_t1_p_stop]; + assign rv_lq_ex0_t3_p = ex0_instr_dat[rvlq_t3_p_start:rvlq_t3_p_stop]; + + assign rv_lq_ex0_itag = ex0_itag_q; + assign rv_lq_ex0_spec = ex0_spec_q; + + assign rv_lq_ex0_t1_v = ex0_t1_v_q; + assign rv_lq_ex0_s1_v = ex0_s1_v_q; + assign rv_lq_ex0_s2_v = ex0_s2_v_q; + assign rv_lq_ex0_s2_t = ex0_s2_t_q; + assign rv_lq_ex0_s1_itag = ex0_s1_itag_q; + assign rv_lq_ex0_s2_itag = ex0_s2_itag_q; + + //------------------------------------------------------------------------------------------------------------ + // Itag busses + //------------------------------------------------------------------------------------------------------------ + + assign lq_rv_ext_itag0_vld_d = lq_rv_itag0_vld & ~cp_flush_q; + assign lq_rv_ext_itag1_vld_d = lq_rv_itag1_vld & ~cp_flush_q; + assign lq_rv_ext_itag2_vld_d = lq_rv_itag2_vld & ~cp_flush_q; + + + + // Restart Itag and Valid from LQ. This is separate because it could be early (not latched) + assign lq_rv_itag1_rst_vld = lq_rv_itag1_vld; + assign lq_rv_itag1_rst = lq_rv_itag1; + + //------------------------------------------------------------------------------------------------------------ + // Pipeline Latches + //------------------------------------------------------------------------------------------------------------ + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0) ) + cp_flush_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[cp_flush_offset:cp_flush_offset + `THREADS - 1]), + .scout(sov[cp_flush_offset:cp_flush_offset + `THREADS - 1]), + .din(cp_flush), + .dout(cp_flush_q) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) ex0_s1_itag_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rv_ex0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[ex0_s1_itag_offset:ex0_s1_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[ex0_s1_itag_offset:ex0_s1_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(ex0_s1_itag_d), + .dout(ex0_s1_itag_q) + ); + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) ex0_s2_itag_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rv_ex0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[ex0_s2_itag_offset:ex0_s2_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[ex0_s2_itag_offset:ex0_s2_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(ex0_s2_itag_d), + .dout(ex0_s2_itag_q) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) ex0_itag_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rv_ex0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[ex0_itag_offset:ex0_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[ex0_itag_offset:ex0_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(ex0_itag_d), + .dout(ex0_itag_q) + ); + + + + tri_rlmlatch_p #(.INIT(0)) ex0_spec_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rv_ex0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[ex0_spec_offset]), + .scout(sov[ex0_spec_offset]), + .din(ex0_spec_d), + .dout(ex0_spec_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) ex0_t1_v_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rv_ex0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[ex0_t1_v_offset]), + .scout(sov[ex0_t1_v_offset]), + .din(ex0_t1_v_d), + .dout(ex0_t1_v_q) + ); + + tri_rlmlatch_p #(.INIT(0)) ex0_s1_v_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rv_ex0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[ex0_s1_v_offset]), + .scout(sov[ex0_s1_v_offset]), + .din(ex0_s1_v_d), + .dout(ex0_s1_v_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) ex0_s2_v_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rv_ex0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[ex0_s2_v_offset]), + .scout(sov[ex0_s2_v_offset]), + .din(ex0_s2_v_d), + .dout(ex0_s2_v_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) ex0_s2_t_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(rv_ex0_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[ex0_s2_t_offset:ex0_s2_t_offset + 3 - 1]), + .scout(sov[ex0_s2_t_offset:ex0_s2_t_offset + 3 - 1]), + .din(ex0_s2_t_d), + .dout(ex0_s2_t_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) lq_rv_ext_itag0_vld_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[lq_rv_ext_itag0_vld_offset:lq_rv_ext_itag0_vld_offset + `THREADS - 1]), + .scout(sov[lq_rv_ext_itag0_vld_offset:lq_rv_ext_itag0_vld_offset + `THREADS - 1]), + .din(lq_rv_ext_itag0_vld_d), + .dout(lq_rv_ext_itag0_vld) + ); + tri_rlmlatch_p #(.INIT(0)) lq_rv_ext_itag0_abort_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[lq_rv_ext_itag0_abort_offset]), + .scout(sov[lq_rv_ext_itag0_abort_offset]), + .din(lq_rv_itag0_abort), + .dout(lq_rv_ext_itag0_abort) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) lq_rv_ext_itag0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[lq_rv_ext_itag0_offset:lq_rv_ext_itag0_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[lq_rv_ext_itag0_offset:lq_rv_ext_itag0_offset + `ITAG_SIZE_ENC - 1]), + .din(lq_rv_itag0), + .dout(lq_rv_ext_itag0) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) lq_rv_ext_itag1_vld_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[lq_rv_ext_itag1_vld_offset:lq_rv_ext_itag1_vld_offset + `THREADS - 1]), + .scout(sov[lq_rv_ext_itag1_vld_offset:lq_rv_ext_itag1_vld_offset + `THREADS - 1]), + .din(lq_rv_ext_itag1_vld_d), + .dout(lq_rv_ext_itag1_vld) + ); + tri_rlmlatch_p #(.INIT(0)) lq_rv_ext_itag1_abort_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[lq_rv_ext_itag1_abort_offset]), + .scout(sov[lq_rv_ext_itag1_abort_offset]), + .din(lq_rv_itag1_abort), + .dout(lq_rv_ext_itag1_abort) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) lq_rv_ext_itag1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[lq_rv_ext_itag1_offset:lq_rv_ext_itag1_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[lq_rv_ext_itag1_offset:lq_rv_ext_itag1_offset + `ITAG_SIZE_ENC - 1]), + .din(lq_rv_itag1), + .dout(lq_rv_ext_itag1) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) lq_rv_ext_itag2_vld_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[lq_rv_ext_itag2_vld_offset:lq_rv_ext_itag2_vld_offset + `THREADS - 1]), + .scout(sov[lq_rv_ext_itag2_vld_offset:lq_rv_ext_itag2_vld_offset + `THREADS - 1]), + .din(lq_rv_ext_itag2_vld_d), + .dout(lq_rv_ext_itag2_vld) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) lq_rv_ext_itag2_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[lq_rv_ext_itag2_offset:lq_rv_ext_itag2_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[lq_rv_ext_itag2_offset:lq_rv_ext_itag2_offset + `ITAG_SIZE_ENC - 1]), + .din(lq_rv_itag2), + .dout(lq_rv_ext_itag2) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS*`ITAG_SIZE_ENC), .INIT(0)) + cp_next_itag_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[cp_next_itag_offset :cp_next_itag_offset + `THREADS*`ITAG_SIZE_ENC-1]), + .scout(sov[cp_next_itag_offset:cp_next_itag_offset + `THREADS*`ITAG_SIZE_ENC-1]), + .din(cp_next_itag), + .dout(cp_next_itag_q) + ); + + + //------------------------------------------------------------------------------------------------------------ + // Scan Connections + //------------------------------------------------------------------------------------------------------------ + + assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in}; + assign scan_out = sov[0]; + + //----------------------------------------------- + // pervasive + //----------------------------------------------- + + + tri_plat #(.WIDTH(2)) + perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(ccflush_dc), + .din({func_sl_thold_1, sg_1}), + .q({func_sl_thold_0 ,sg_0}) + ); + + + tri_lcbor + perv_lcbor( + .clkoff_b(clkoff_b), + .thold(func_sl_thold_0), + .sg(sg_0), + .act_dis(act_dis), + .force_t(force_t), + .thold_b(func_sl_thold_0_b) + ); + + +endmodule // rv_lq_rvs diff --git a/dev/verilog/work/rv_perv.v b/dev/verilog/work/rv_perv.v new file mode 100755 index 0000000..ecb0974 --- /dev/null +++ b/dev/verilog/work/rv_perv.v @@ -0,0 +1,524 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// ********************************************************************* +// +// This is the ENTITY for rv_perv +// +// ********************************************************************* + +module rv_perv( // 0 = ibm umbra, 1 = xilinx, 2 = ibm mpg +`include "tri_a2o.vh" + + inout vdd, + inout gnd, + (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) // nclk + input [0:`NCLK_WIDTH-1] nclk, + + input rp_rv_ccflush_dc, + input rp_rv_func_sl_thold_3, + input rp_rv_gptr_sl_thold_3, + input rp_rv_sg_3, + input rp_rv_fce_3, + input an_ac_scan_diag_dc, + input an_ac_scan_dis_dc_b, + + input d_mode, + + output func_sl_thold_1, + output fce_1, + output sg_1, + + output clkoff_dc_b, + output act_dis, + output [0:9] delay_lclkr_dc, + output [0:9] mpw1_dc_b, + output mpw2_dc_b, + input gptr_scan_in, + output gptr_scan_out, + input scan_in, + output scan_out, + + //------------------------------------------------------------------------------------------------------------ + // Debug and Perf + //------------------------------------------------------------------------------------------------------------ + input [0:8*`THREADS-1] fx0_rvs_perf_bus, + input [0:31] fx0_rvs_dbg_bus, + input [0:8*`THREADS-1] fx1_rvs_perf_bus, + input [0:31] fx1_rvs_dbg_bus, + input [0:8*`THREADS-1] lq_rvs_perf_bus, + input [0:31] lq_rvs_dbg_bus, + input [0:8*`THREADS-1] axu0_rvs_perf_bus, + input [0:31] axu0_rvs_dbg_bus, + + input [0:`THREADS-1] spr_msr_gs, + input [0:`THREADS-1] spr_msr_pr, + + input pc_rv_trace_bus_enable, + input [0:10] pc_rv_debug_mux_ctrls, + input pc_rv_event_bus_enable, + input [0:2] pc_rv_event_count_mode, + input [0:39] pc_rv_event_mux_ctrls, + input [0:4*`THREADS-1] rv_event_bus_in, + output [0:4*`THREADS-1] rv_event_bus_out, + output [0:31] debug_bus_out, + input [0:31] debug_bus_in, + input [0:3] coretrace_ctrls_in, + output [0:3] coretrace_ctrls_out + ); + + wire func_sl_thold_2; + wire gptr_sl_thold_2; + + wire sg_2; + wire fce_2; + + wire gptr_sl_thold_1; + wire func_sl_thold_1_int; + wire sg_1_int; + + wire gptr_sl_thold_0; + wire func_sl_thold_0; + + wire force_t; + + wire sg_0; + wire gptr_sio; + wire [0:9] prv_delay_lclkr_dc; + wire [0:9] prv_mpw1_dc_b; + wire prv_mpw2_dc_b; + wire prv_act_dis; + wire prv_clkoff_dc_b; + + // Debug and Perf + wire trc_act; + wire evt_act; + wire delay_lclkr; + wire mpw1_b; + wire mpw2_b; + + wire [0:31] debug_bus_mux; + wire [0:3] coretrace_ctrls_mux; + + wire [0:10] debug_mux_ctrls; + wire [0:39] event_mux_ctrls; + wire [0:2] event_count_mode; + wire [0:`THREADS-1] spr_msr_gs_q; + wire [0:`THREADS-1] spr_msr_pr_q; + wire [0:`THREADS-1] event_en; + + wire [0:32*`THREADS-1] event_bus_in; + wire [0:4*`THREADS-1] event_bus_d; + wire [0:4*`THREADS-1] event_bus_q; + + + + wire [0:31] dbg_group0; + wire [0:31] dbg_group1; + wire [0:31] dbg_group2; + wire [0:31] dbg_group3; + + // Unused Signals + (* analysis_not_referenced="TRUE" *) + wire act0_dis_dc; + (* analysis_not_referenced="TRUE" *) + wire d0_mode_dc; + (* analysis_not_referenced="TRUE" *) + wire clkoff1_dc_b; + (* analysis_not_referenced="TRUE" *) + wire act1_dis_dc; + (* analysis_not_referenced="TRUE" *) + wire d1_mode_dc; + (* analysis_not_referenced="TRUE" *) + wire nc_mpw2_dc_b; + (* analysis_not_referenced="TRUE" *) + wire unused; + + wire func_sl_thold_0_b = 0; // wtf: dangling test sig + + + //------------------------------------------------------------------------------------------------------------ + // Scan Chains + //------------------------------------------------------------------------------------------------------------ + parameter debug_bus_offset = 0 + 0; + parameter debug_mux_offset = debug_bus_offset + 32; + parameter event_bus_offset = debug_mux_offset + 11; + parameter event_count_offset = event_bus_offset + 4*`THREADS; + parameter spr_msr_gs_offset = event_count_offset + 3; + parameter spr_msr_pr_offset = spr_msr_gs_offset + `THREADS; + parameter event_mux_ctrls_offset = spr_msr_pr_offset + `THREADS; + parameter coretrace_ctrls_offset = event_mux_ctrls_offset + 40; + + parameter scan_right = coretrace_ctrls_offset + 4; + wire [0:scan_right-1] siv; + wire [0:scan_right-1] sov; + + assign unused = an_ac_scan_dis_dc_b ; + + + tri_plat #(.WIDTH(4)) + perv_3to2_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(rp_rv_ccflush_dc), + .din({rp_rv_func_sl_thold_3, rp_rv_gptr_sl_thold_3, rp_rv_sg_3, rp_rv_fce_3}), + .q({func_sl_thold_2, gptr_sl_thold_2, sg_2, fce_2}) + ); + + + tri_plat #(.WIDTH(4)) + perv_2to1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(rp_rv_ccflush_dc), + .din({func_sl_thold_2, gptr_sl_thold_2, sg_2, fce_2}), + .q({func_sl_thold_1_int, gptr_sl_thold_1, sg_1_int, fce_1}) + ); + + assign func_sl_thold_1 = func_sl_thold_1_int; + assign sg_1 = sg_1_int; + + + tri_plat #(.WIDTH(3)) + perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(rp_rv_ccflush_dc), + .din({gptr_sl_thold_1 , func_sl_thold_1_int, sg_1_int}), + .q({gptr_sl_thold_0, func_sl_thold_0, sg_0}) + ); + + tri_lcbor + perv_lcbor( + .clkoff_b(prv_clkoff_dc_b), + .thold(func_sl_thold_0), + .sg(sg_0), + .act_dis(prv_act_dis), + .force_t(force_t), + .thold_b(func_sl_thold_0_b) + ); + + // Pipeline mapping of mpw1_b and delay_lclkr + // RF0 + // RF1 0 + // EX1 1 + // EX2 2 + // EX3 3 + // EX4 4 + // EX5 5 + // EX6 6 + // EX7 7 + + + tri_lcbcntl_mac + perv_lcbctrl0( + .vdd(vdd), + .gnd(gnd), + .sg(sg_0), + .nclk(nclk), + .scan_in(gptr_scan_in), + .scan_diag_dc(an_ac_scan_diag_dc), + .thold(gptr_sl_thold_0), + .clkoff_dc_b(prv_clkoff_dc_b), + .delay_lclkr_dc(prv_delay_lclkr_dc[0:4]), + .act_dis_dc(act0_dis_dc), + .d_mode_dc(d0_mode_dc), + .mpw1_dc_b(prv_mpw1_dc_b[0:4]), + .mpw2_dc_b(prv_mpw2_dc_b), + .scan_out(gptr_sio) + ); + + + tri_lcbcntl_mac + perv_lcbctrl1( + .vdd(vdd), + .gnd(gnd), + .sg(sg_0), + .nclk(nclk), + .scan_in(gptr_sio), + .scan_diag_dc(an_ac_scan_diag_dc), + .thold(gptr_sl_thold_0), + .clkoff_dc_b(clkoff1_dc_b), + .delay_lclkr_dc(prv_delay_lclkr_dc[5:9]), + .act_dis_dc(act1_dis_dc), + .d_mode_dc(d1_mode_dc), + .mpw1_dc_b(prv_mpw1_dc_b[5:9]), + .mpw2_dc_b(nc_mpw2_dc_b), + .scan_out(gptr_scan_out) + ); + + //Outputs + assign delay_lclkr_dc[0:9] = prv_delay_lclkr_dc[0:9]; + assign mpw1_dc_b[0:9] = prv_mpw1_dc_b[0:9]; + assign mpw2_dc_b = prv_mpw2_dc_b; + + //never disable act pins, they are used functionally + assign prv_act_dis = 1'b0; + assign act_dis = prv_act_dis; + assign clkoff_dc_b = prv_clkoff_dc_b; + + + //------------------------------------------------------------------------------------------------------------ + // Perf bus + //------------------------------------------------------------------------------------------------------------ + + assign event_en = ( spr_msr_pr_q & {`THREADS{event_count_mode[0]}}) | //-- User + ((~spr_msr_pr_q) & spr_msr_gs_q & {`THREADS{event_count_mode[1]}}) | //-- Guest Supervisor + ((~spr_msr_pr_q) & (~spr_msr_gs_q) & {`THREADS{event_count_mode[2]}}); //-- Hypervisor + + assign event_bus_in[ 0: 7] = fx0_rvs_perf_bus[0:7] & {8{event_en[0]}}; + assign event_bus_in[ 8:15] = fx1_rvs_perf_bus[0:7] & {8{event_en[0]}}; + assign event_bus_in[16:23] = lq_rvs_perf_bus[0:7] & {8{event_en[0]}}; + assign event_bus_in[24:31] = axu0_rvs_perf_bus[0:7] & {8{event_en[0]}}; + + + tri_event_mux1t #(.EVENTS_IN(32), .EVENTS_OUT(4)) + event_mux0( + .vd(vdd), + .gd(gnd), + .event_bus_in(rv_event_bus_in[0:3]), + .event_bus_out(event_bus_d[0:3]), + .unit_events_in(event_bus_in[1:31]), + .select_bits(event_mux_ctrls[0:19]) + ); + +`ifndef THREADS1 + + assign event_bus_in[32:39] = fx0_rvs_perf_bus[8:15] & {8{event_en[1]}}; + assign event_bus_in[40:47] = fx1_rvs_perf_bus[8:15] & {8{event_en[1]}}; + assign event_bus_in[48:55] = lq_rvs_perf_bus[8:15] & {8{event_en[1]}}; + assign event_bus_in[56:63] = axu0_rvs_perf_bus[8:15] & {8{event_en[1]}}; + + tri_event_mux1t #(.EVENTS_IN(32), .EVENTS_OUT(4)) + event_mux1( + .vd(vdd), + .gd(gnd), + .event_bus_in(rv_event_bus_in[4:7]), + .event_bus_out(event_bus_d[4:7]), + .unit_events_in(event_bus_in[32:63]), + .select_bits(event_mux_ctrls[20:39]) + ); +`endif + + assign rv_event_bus_out = event_bus_q; + + + //------------------------------------------------------------------------------------------------------------ + // Debug bus + //------------------------------------------------------------------------------------------------------------ + + assign dbg_group0 = fx0_rvs_dbg_bus[0:31] ; + assign dbg_group1 = fx1_rvs_dbg_bus[0:31] ; + assign dbg_group2 = lq_rvs_dbg_bus[0:31] ; + assign dbg_group3 = axu0_rvs_dbg_bus[0:31] ; + + tri_debug_mux4 #(.DBG_WIDTH(32)) + dbg_mux( + .select_bits(debug_mux_ctrls), + .trace_data_in(debug_bus_in), + .dbg_group0(dbg_group0), + .dbg_group1(dbg_group1), + .dbg_group2(dbg_group2), + .dbg_group3(dbg_group3), + .trace_data_out(debug_bus_mux), + .coretrace_ctrls_in(coretrace_ctrls_in), + .coretrace_ctrls_out(coretrace_ctrls_mux) + ); + + + //------------------------------------------------------------------------------------------------------------ + // Latches + //------------------------------------------------------------------------------------------------------------ + assign trc_act = pc_rv_trace_bus_enable; + assign evt_act = pc_rv_event_bus_enable; + assign delay_lclkr = prv_delay_lclkr_dc[0]; + assign mpw1_b = prv_mpw1_dc_b[0]; + assign mpw2_b = prv_mpw2_dc_b; + + tri_rlmreg_p #(.WIDTH(32), .INIT(0)) + debug_bus_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(trc_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[debug_bus_offset:debug_bus_offset + 32 - 1]), + .scout(sov[debug_bus_offset:debug_bus_offset + 32 - 1]), + .din(debug_bus_mux), + .dout(debug_bus_out) + ); + tri_rlmreg_p #(.WIDTH(11), .INIT(0)) + debug_mux_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(trc_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[debug_mux_offset:debug_mux_offset + 11 - 1]), + .scout(sov[debug_mux_offset:debug_mux_offset + 11 - 1]), + .din(pc_rv_debug_mux_ctrls), + .dout(debug_mux_ctrls) + ); + tri_rlmreg_p #(.WIDTH(4*`THREADS), .INIT(0)) + event_bus_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(evt_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[event_bus_offset:event_bus_offset + 4*`THREADS - 1]), + .scout(sov[event_bus_offset:event_bus_offset + 4*`THREADS - 1]), + .din(event_bus_d), + .dout(event_bus_q) + ); + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) + event_count_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(evt_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[event_count_offset:event_count_offset + 3 - 1]), + .scout(sov[event_count_offset:event_count_offset + 3 - 1]), + .din(pc_rv_event_count_mode), + .dout(event_count_mode) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) + spr_msr_gs_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(evt_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[spr_msr_gs_offset:spr_msr_gs_offset + `THREADS - 1]), + .scout(sov[spr_msr_gs_offset:spr_msr_gs_offset + `THREADS - 1]), + .din(spr_msr_gs), + .dout(spr_msr_gs_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) + spr_msr_pr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(evt_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[spr_msr_pr_offset:spr_msr_pr_offset + `THREADS - 1]), + .scout(sov[spr_msr_pr_offset:spr_msr_pr_offset + `THREADS - 1]), + .din(spr_msr_pr), + .dout(spr_msr_pr_q) + ); + tri_rlmreg_p #(.WIDTH(40), .INIT(0)) + event_mux_ctrls_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(evt_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[event_mux_ctrls_offset:event_mux_ctrls_offset + 40 - 1]), + .scout(sov[event_mux_ctrls_offset:event_mux_ctrls_offset + 40 - 1]), + .din(pc_rv_event_mux_ctrls), + .dout(event_mux_ctrls) + ); + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) + core_trace_ctrls_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(trc_act), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[coretrace_ctrls_offset:coretrace_ctrls_offset + 4 - 1]), + .scout(sov[coretrace_ctrls_offset:coretrace_ctrls_offset + 4 - 1]), + .din(coretrace_ctrls_mux), + .dout(coretrace_ctrls_out) + ); + + + + + //------------------------------------------------------------------------------------------------------------ + // Scan Connections + //------------------------------------------------------------------------------------------------------------ + + assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in}; + assign scan_out = sov[0]; + + +endmodule diff --git a/dev/verilog/work/rv_pri.v b/dev/verilog/work/rv_pri.v new file mode 100755 index 0000000..3efb203 --- /dev/null +++ b/dev/verilog/work/rv_pri.v @@ -0,0 +1,120 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: Prioritizer +// +//***************************************************************************** + +module rv_pri( + cond, + pri + ); + parameter size = 32; + input [0:size-1] cond; + output [0:size-1] pri; + + parameter s = size - 1; + wire [0:s] or_l1; + wire [0:s] or_l2; + wire [0:s] or_l3; + wire [0:s] or_l4; + wire [0:s] or_l5; + (* analysis_not_referenced="true" *) + wire or_cond; + + + // Odd Numbered Levels are inverted + + assign or_l1[0] = (~cond[0]); + assign or_l1[1:s] = ~(cond[0:s - 1] | cond[1:s]); + + generate + if (s >= 2) + begin : or_l2_gen0 + assign or_l2[0:1] = (~or_l1[0:1]); + assign or_l2[2:s] = ~(or_l1[2:s] & or_l1[0:s - 2]); + end + endgenerate + generate + if (s < 2) + begin : or_l2_gen1 + assign or_l2 = (~or_l1); + end + endgenerate + + generate + if (s >= 4) + begin : or_l3_gen0 + assign or_l3[0:3] = (~or_l2[0:3]); + assign or_l3[4:s] = ~(or_l2[4:s] | or_l2[0:s - 4]); + end + endgenerate + generate + if (s < 4) + begin : or_l3_gen1 + assign or_l3 = (~or_l2); + end + endgenerate + + generate + if (s >= 8) + begin : or_l4_gen0 + assign or_l4[0:7] = (~or_l3[0:7]); + assign or_l4[8:s] = ~(or_l3[8:s] & or_l3[0:s - 8]); + end + endgenerate + generate + if (s < 8) + begin : or_l4_gen1 + assign or_l4 = (~or_l3); + end + endgenerate + + generate + if (s >= 16) + begin : or_l5_gen0 + assign or_l5[0:15] = (~or_l4[0:15]); + assign or_l5[16:s] = ~(or_l4[16:s] | or_l4[0:s - 16]); + end + endgenerate + generate + if (s < 16) + begin : or_l5_gen1 + assign or_l5 = (~or_l4); + end + endgenerate + + //assert size > 32 report "Maximum Size of 32 Exceeded!" severity error; + + assign pri[0] = cond[0]; + assign pri[1:s] = cond[1:s] & or_l5[0:s - 1]; + assign or_cond = (~or_l5[s]); + +endmodule // rv_pri diff --git a/dev/verilog/work/rv_primux.v b/dev/verilog/work/rv_primux.v new file mode 100755 index 0000000..f0d3c0c --- /dev/null +++ b/dev/verilog/work/rv_primux.v @@ -0,0 +1,354 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: Prioritizer +// +//***************************************************************************** + +module rv_primux( + cond, + din, + dout + ); + + parameter q_num_entries_g = 16; + parameter q_dat_width_g = 7; + input [0:q_num_entries_g-1] cond; + input [0:q_dat_width_g*q_num_entries_g-1] din; + output [0:q_dat_width_g-1] dout; + + + + wire [0:q_dat_width_g-1] q_dat_l1[0:7]; + wire [0:q_dat_width_g-1] q_dat_l1a[0:7]; + wire [0:q_dat_width_g-1] q_dat_l1b[0:7]; + wire [0:q_dat_width_g-1] q_dat_l2[0:3]; + wire [0:q_dat_width_g-1] q_dat_l2a[0:3]; + wire [0:q_dat_width_g-1] q_dat_l2b[0:3]; + wire [0:q_dat_width_g-1] q_dat_l4[0:1]; + wire [0:q_dat_width_g-1] q_dat_l4a[0:1]; + wire [0:q_dat_width_g-1] q_dat_l4b[0:1]; + wire [0:q_dat_width_g-1] q_dat_l8a; + wire [0:q_dat_width_g-1] q_dat_l8b; + wire [0:q_dat_width_g-1] q_dat_l8; + + wire [1:7] selval1_b; + wire [0:7] selpri1; + wire [0:7] selpri1_b; + wire [1:3] selval2; + wire [0:3] selpri2; + wire [0:3] selpri2_b; + wire [1:1] selval4_b; + wire [0:1] selpri4; + wire [0:1] selpri4_b; + wire selpri8; + wire selpri8_b; + + (* analysis_not_referenced="true" *) + wire selpri1_unused; + (* analysis_not_referenced="true" *) + wire selpri1_b_unused; + (* analysis_not_referenced="true" *) + wire [0:q_dat_width_g-1] q_dat_l1_unused; + (* analysis_not_referenced="true" *) + wire cond_unused; + + genvar n; + + parameter aryoff = q_dat_width_g; + + assign cond_unused = cond[0]; + tri_nor2 selval1_b1(selval1_b[1], cond[2], cond[3]); + tri_nor2 selval1_b2(selval1_b[2], cond[4], cond[5]); + tri_nor2 selval1_b3(selval1_b[3], cond[6], cond[7]); + + generate + if (q_num_entries_g == 8) + begin : selval1_gen08 + assign selval1_b[4] = 1'b1; + assign selval1_b[5] = 1'b1; + assign selval1_b[6] = 1'b1; + assign selval1_b[7] = 1'b1; + end + endgenerate + generate + if (q_num_entries_g == 12) + begin : selval1_gen0 + tri_nor2 selval1_b4(selval1_b[4], cond[8], cond[9]); + tri_nor2 selval1_b5(selval1_b[5], cond[10], cond[11]); + assign selval1_b[6] = 1'b1; + assign selval1_b[7] = 1'b1; + end + endgenerate + generate + if (q_num_entries_g == 16) + begin : selval1_gen1 + tri_nor2 selval1_b4(selval1_b[4], cond[8], cond[9]); + tri_nor2 selval1_b5(selval1_b[5], cond[10], cond[11]); + tri_nor2 selval1_b6(selval1_b[6], cond[12], cond[13]); + tri_nor2 selval1_b7(selval1_b[7], cond[14], cond[15]); + end + endgenerate + + tri_inv selpri1_b0( selpri1_b[0], cond[1]); + tri_inv selpri1_b1( selpri1_b[1], cond[3]); + tri_inv selpri1_b2( selpri1_b[2], cond[5]); + tri_inv selpri1_b3( selpri1_b[3], cond[7]); + generate + if (q_num_entries_g == 8) + begin : selpri1_gen08 + assign selpri1_b[4] = 1'b1; + assign selpri1_b[5] = 1'b1; + assign selpri1_b[6] = 1'b1; + assign selpri1_b[7] = 1'b1; + assign selpri1_b_unused = selpri1_b[4] | selpri1_b[5] | selpri1_b[6] | selpri1_b[7] ; + end + endgenerate + generate + if (q_num_entries_g == 12) + begin : selpri1_gen0 + tri_inv selpri1_b4( selpri1_b[4], cond[9]); + tri_inv selpri1_b5( selpri1_b[5], cond[11]); + assign selpri1_b[6] = 1'b1; + assign selpri1_b[7] = 1'b1; + assign selpri1_b_unused = selpri1_b[6] | selpri1_b[7] ; + end + endgenerate + generate + if (q_num_entries_g == 16) + begin : selpri1_gen1 + tri_inv selpri1_b4( selpri1_b[4], cond[9]); + tri_inv selpri1_b5( selpri1_b[5], cond[11]); + tri_inv selpri1_b6( selpri1_b[6], cond[13]); + tri_inv selpri1_b7( selpri1_b[7], cond[15]); + assign selpri1_b_unused =1'b0; + end + endgenerate + + tri_inv selpri1_0( selpri1[0], selpri1_b[0]); + tri_inv selpri1_1( selpri1[1], selpri1_b[1]); + tri_inv selpri1_2( selpri1[2], selpri1_b[2]); + tri_inv selpri1_3( selpri1[3], selpri1_b[3]); + generate + if (q_num_entries_g == 8) + begin : selpri1_gen0b8 + assign selpri1[4] = 1'b0; + assign selpri1[5] = 1'b0; + assign selpri1[6] = 1'b0; + assign selpri1[7] = 1'b0; + assign selpri1_unused = selpri1[4] | selpri1[5] | selpri1[6] | selpri1[7] ; + end + endgenerate + generate + if (q_num_entries_g == 12) + begin : selpri1_gen0b + tri_inv selpri1_4( selpri1[4], selpri1_b[4]); + tri_inv selpri1_5( selpri1[5], selpri1_b[5]); + assign selpri1[6] = 1'b0; + assign selpri1[7] = 1'b0; + assign selpri1_unused = selpri1[6] | selpri1[7]; + end + endgenerate + generate + if (q_num_entries_g == 16) + begin : selpri1_gen1b + tri_inv selpri1_4( selpri1[4], selpri1_b[4]); + tri_inv selpri1_5( selpri1[5], selpri1_b[5]); + tri_inv selpri1_6( selpri1[6], selpri1_b[6]); + tri_inv selpri1_7( selpri1[7], selpri1_b[7]); + + assign selpri1_unused=1'b0; + + end + endgenerate + + tri_nand2 selval21(selval2[1], selval1_b[2], selval1_b[3]); + tri_nand2 selval22(selval2[2], selval1_b[4], selval1_b[5]); + tri_nand2 selval23(selval2[3], selval1_b[6], selval1_b[7]); + + assign selpri2[0] = (~selval1_b[1]); + assign selpri2[1] = (~selval1_b[3]); + assign selpri2[2] = (~selval1_b[5]); + assign selpri2[3] = (~selval1_b[7]); + assign selpri2_b[0] = selval1_b[1]; + assign selpri2_b[1] = selval1_b[3]; + assign selpri2_b[2] = selval1_b[5]; + assign selpri2_b[3] = selval1_b[7]; + + tri_nor2 selval4_b1(selval4_b[1], selval2[2], selval2[3]); + + assign selpri4_b[0] = (~selval2[1]); + assign selpri4_b[1] = (~selval2[3]); + assign selpri4[0] = selval2[1]; + assign selpri4[1] = selval2[3]; + + assign selpri8 = (~selval4_b[1]); + assign selpri8_b = selval4_b[1]; + + //------------------------------------------------------------------------------------------------------- + // Instruction Muxing + //------------------------------------------------------------------------------------------------------- + generate + begin : xhdl + for (n = 0; n <= (q_dat_width_g - 1); n = n + 1) + begin : gendat + + // Level 1 + // 01 23 45 67 89 1011 1213 1415 + tri_nand2 q_dat_l1a0(q_dat_l1a[0][n], din[0*aryoff+n], selpri1_b[0]); + tri_nand2 q_dat_l1b0(q_dat_l1b[0][n], din[1*aryoff+n], selpri1[0]); + tri_nand2 #(.BTR("NAND2_X3M_A9TH")) q_dat_l10(q_dat_l1[0][n], q_dat_l1a[0][n], q_dat_l1b[0][n]); + + tri_nand2 q_dat_l1a1(q_dat_l1a[1][n], din[2*aryoff+n], selpri1_b[1]); + tri_nand2 q_dat_l1b1(q_dat_l1b[1][n], din[3*aryoff+n], selpri1[1]); + tri_nand2 #(.BTR("NAND2_X3M_A9TH")) q_dat_l11(q_dat_l1[1][n], q_dat_l1a[1][n], q_dat_l1b[1][n]); + + tri_nand2 q_dat_l1a2(q_dat_l1a[2][n], din[4*aryoff+n], selpri1_b[2]); + tri_nand2 q_dat_l1b2(q_dat_l1b[2][n], din[5*aryoff+n], selpri1[2]); + tri_nand2 #(.BTR("NAND2_X3M_A9TH")) q_dat_l12(q_dat_l1[2][n], q_dat_l1a[2][n], q_dat_l1b[2][n]); + + tri_nand2 q_dat_l1a3(q_dat_l1a[3][n], din[6*aryoff+n], selpri1_b[3]); + tri_nand2 q_dat_l1b3(q_dat_l1b[3][n], din[7*aryoff+n], selpri1[3]); + tri_nand2 #(.BTR("NAND2_X3M_A9TH")) q_dat_l13(q_dat_l1[3][n], q_dat_l1a[3][n], q_dat_l1b[3][n]); + + + //generate + if (q_num_entries_g == 8) + begin : l1_gen8 + assign q_dat_l1a[4][n] = 1'b0; + assign q_dat_l1b[4][n] = 1'b0; + assign q_dat_l1[4][n] = 1'b0; + + assign q_dat_l1a[5][n] = 1'b0; + assign q_dat_l1b[5][n] = 1'b0; + assign q_dat_l1[5][n] = 1'b0; + + assign q_dat_l1a[6][n] = 1'b0; + assign q_dat_l1b[6][n] = 1'b0; + assign q_dat_l1[6][n] = 1'b0; + + assign q_dat_l1a[7][n] = 1'b0; + assign q_dat_l1b[7][n] = 1'b0; + assign q_dat_l1[7][n] = 1'b0; + + assign q_dat_l1_unused[n] = (|q_dat_l1a[4][n]) | (|q_dat_l1a[5][n]) | (|q_dat_l1a[6][n]) | (|q_dat_l1a[7][n]) | + (|q_dat_l1b[4][n]) | (|q_dat_l1b[5][n]) | (|q_dat_l1b[6][n]) | (|q_dat_l1b[7][n]) | + (|q_dat_l1[4][n]) | (|q_dat_l1[5][n]) | (|q_dat_l1[6][n]) | (|q_dat_l1[7][n]) ; + end + //endgenerate + //generate + if (q_num_entries_g == 12) + begin : l1_gen12 + tri_nand2 q_dat_l1a4(q_dat_l1a[4][n], din[8*aryoff+n], selpri1_b[4]); + tri_nand2 q_dat_l1b4(q_dat_l1b[4][n], din[9*aryoff+n], selpri1[4]); + tri_nand2 #(.BTR("NAND2_X3M_A9TH")) q_dat_l14(q_dat_l1[4][n], q_dat_l1a[4][n], q_dat_l1b[4][n]); + + tri_nand2 q_dat_l1a5(q_dat_l1a[5][n], din[10*aryoff+n], selpri1_b[5]); + tri_nand2 q_dat_l1b5(q_dat_l1b[5][n], din[11*aryoff+n], selpri1[5]); + tri_nand2 #(.BTR("NAND2_X3M_A9TH")) q_dat_l15(q_dat_l1[5][n], q_dat_l1a[5][n], q_dat_l1b[5][n]); + + assign q_dat_l1a[6][n] = 1'b0; + assign q_dat_l1b[6][n] = 1'b0; + assign q_dat_l1[6][n] = 1'b0; + + assign q_dat_l1a[7][n] = 1'b0; + assign q_dat_l1b[7][n] = 1'b0; + assign q_dat_l1[7][n] = 1'b0; + + assign q_dat_l1_unused[n] = (|q_dat_l1a[6][n]) | (|q_dat_l1a[7][n]) | + (|q_dat_l1b[6][n]) | (|q_dat_l1b[7][n]) | + (|q_dat_l1[6][n]) | (|q_dat_l1[7][n]) ; + end + //endgenerate + //generate + if (q_num_entries_g == 16) + begin : l1_gen16 + + tri_nand2 q_dat_l1a4(q_dat_l1a[4][n], din[8*aryoff+n], selpri1_b[4]); + tri_nand2 q_dat_l1b4(q_dat_l1b[4][n], din[9*aryoff+n], selpri1[4]); + tri_nand2 q_dat_l14(q_dat_l1[4][n], q_dat_l1a[4][n], q_dat_l1b[4][n]); + + tri_nand2 q_dat_l1a5(q_dat_l1a[5][n], din[10*aryoff+n], selpri1_b[5]); + tri_nand2 q_dat_l1b5(q_dat_l1b[5][n], din[11*aryoff+n], selpri1[5]); + tri_nand2 #(.BTR("NAND2_X3M_A9TH")) q_dat_l15(q_dat_l1[5][n], q_dat_l1a[5][n], q_dat_l1b[5][n]); + + tri_nand2 q_dat_l1a6(q_dat_l1a[6][n], din[12*aryoff+n], selpri1_b[6]); + tri_nand2 q_dat_l1b6(q_dat_l1b[6][n], din[13*aryoff+n], selpri1[6]); + tri_nand2 #(.BTR("NAND2_X3M_A9TH")) q_dat_l16(q_dat_l1[6][n], q_dat_l1a[6][n], q_dat_l1b[6][n]); + + tri_nand2 q_dat_l1a7(q_dat_l1a[7][n], din[14*aryoff+n], selpri1_b[7]); + tri_nand2 q_dat_l1b7(q_dat_l1b[7][n], din[15*aryoff+n], selpri1[7]); + tri_nand2 #(.BTR("NAND2_X3M_A9TH")) q_dat_l17(q_dat_l1[7][n], q_dat_l1a[7][n], q_dat_l1b[7][n]); + + assign q_dat_l1_unused[n]=1'b0; + end + //endgenerate + end + end + endgenerate + + + // Level 2 + // 0123 4567 891011 12131415 + tri_nand2 #(.WIDTH(q_dat_width_g), .BTR("NAND2_X3M_A9TH")) q_dat_l2a0(q_dat_l2a[0], q_dat_l1[0], {q_dat_width_g{selpri2_b[0]}}); + tri_nand2 #(.WIDTH(q_dat_width_g), .BTR("NAND2_X3M_A9TH")) q_dat_l2b0(q_dat_l2b[0], q_dat_l1[1], {q_dat_width_g{selpri2[0]}}); + tri_nand2 #(.WIDTH(q_dat_width_g), .BTR("NAND2_X3M_A9TH")) q_dat_l20(q_dat_l2[0], q_dat_l2a[0], q_dat_l2b[0]); + + tri_nand2 #(.WIDTH(q_dat_width_g), .BTR("NAND2_X3M_A9TH")) q_dat_l2a1(q_dat_l2a[1], q_dat_l1[2], {q_dat_width_g{selpri2_b[1]}}); + tri_nand2 #(.WIDTH(q_dat_width_g), .BTR("NAND2_X3M_A9TH")) q_dat_l2b1(q_dat_l2b[1], q_dat_l1[3], {q_dat_width_g{selpri2[1]}}); + tri_nand2 #(.WIDTH(q_dat_width_g), .BTR("NAND2_X3M_A9TH")) q_dat_l21(q_dat_l2[1], q_dat_l2a[1], q_dat_l2b[1]); + + tri_nand2 #(.WIDTH(q_dat_width_g), .BTR("NAND2_X3M_A9TH")) q_dat_l2a2(q_dat_l2a[2], q_dat_l1[4], {q_dat_width_g{selpri2_b[2]}}); + tri_nand2 #(.WIDTH(q_dat_width_g), .BTR("NAND2_X3M_A9TH")) q_dat_l2b2(q_dat_l2b[2], q_dat_l1[5], {q_dat_width_g{selpri2[2]}}); + tri_nand2 #(.WIDTH(q_dat_width_g), .BTR("NAND2_X3M_A9TH")) q_dat_l22(q_dat_l2[2], q_dat_l2a[2], q_dat_l2b[2]); + + tri_nand2 #(.WIDTH(q_dat_width_g), .BTR("NAND2_X3M_A9TH")) q_dat_l2a3(q_dat_l2a[3], q_dat_l1[6], {q_dat_width_g{selpri2_b[3]}}); + tri_nand2 #(.WIDTH(q_dat_width_g), .BTR("NAND2_X3M_A9TH")) q_dat_l2b3(q_dat_l2b[3], q_dat_l1[7], {q_dat_width_g{selpri2[3]}}); + tri_nand2 #(.WIDTH(q_dat_width_g), .BTR("NAND2_X3M_A9TH")) q_dat_l23(q_dat_l2[3], q_dat_l2a[3], q_dat_l2b[3]); + + // Level 4 + // 01234567 89101112131415 + tri_nand2 #(.WIDTH(q_dat_width_g), .BTR("NAND2_X3M_A9TH")) q_dat_l4a0(q_dat_l4a[0], q_dat_l2[0], {q_dat_width_g{selpri4_b[0]}}); + tri_nand2 #(.WIDTH(q_dat_width_g), .BTR("NAND2_X3M_A9TH")) q_dat_l4b0(q_dat_l4b[0], q_dat_l2[1], {q_dat_width_g{selpri4[0]}}); + tri_nand2 #(.WIDTH(q_dat_width_g), .BTR("NAND2_X4M_A9TH")) q_dat_l40(q_dat_l4[0], q_dat_l4a[0], q_dat_l4b[0]); + + tri_nand2 #(.WIDTH(q_dat_width_g), .BTR("NAND2_X3M_A9TH")) q_dat_l4a1(q_dat_l4a[1], q_dat_l2[2], {q_dat_width_g{selpri4_b[1]}}); + tri_nand2 #(.WIDTH(q_dat_width_g), .BTR("NAND2_X3M_A9TH")) q_dat_l4b1(q_dat_l4b[1], q_dat_l2[3], {q_dat_width_g{selpri4[1]}}); + tri_nand2 #(.WIDTH(q_dat_width_g), .BTR("NAND2_X4M_A9TH")) q_dat_l41(q_dat_l4[1], q_dat_l4a[1], q_dat_l4b[1]); + + // Level 8 + // 0123456789101112131415 + tri_nand2 #(.WIDTH(q_dat_width_g), .BTR("NAND2_X6M_A9TH")) q_dat_l8a0(q_dat_l8a, q_dat_l4[0], {q_dat_width_g{selpri8_b}}); + tri_nand2 #(.WIDTH(q_dat_width_g), .BTR("NAND2_X6M_A9TH")) q_dat_l8b0(q_dat_l8b, q_dat_l4[1], {q_dat_width_g{selpri8}}); + tri_nand2 #(.WIDTH(q_dat_width_g), .BTR("NAND2_X8M_A9TH")) q_dat_180( q_dat_l8, q_dat_l8a, q_dat_l8b); + + assign dout = q_dat_l8; + +endmodule // rv_primux diff --git a/dev/verilog/work/rv_prisel.v b/dev/verilog/work/rv_prisel.v new file mode 100755 index 0000000..24566ee --- /dev/null +++ b/dev/verilog/work/rv_prisel.v @@ -0,0 +1,348 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: Prioritizer +// +//***************************************************************************** + +module rv_prisel( + cond, + din, + dout + ); + + parameter q_num_entries_g = 16; + parameter q_dat_width_g = 7; + input [0:q_num_entries_g-1] cond; + input [0:q_dat_width_g*q_num_entries_g-1] din; + output [0:q_dat_width_g-1] dout; + + + + wire [0:q_dat_width_g-1] q_dat_l1[0:7]; + wire [0:q_dat_width_g-1] q_dat_l1a[0:7]; + wire [0:q_dat_width_g-1] q_dat_l1b[0:7]; + wire [0:q_dat_width_g-1] q_dat_l2[0:3]; + wire [0:q_dat_width_g-1] q_dat_l2a[0:3]; + wire [0:q_dat_width_g-1] q_dat_l2b[0:3]; + wire [0:q_dat_width_g-1] q_dat_l4[0:1]; + wire [0:q_dat_width_g-1] q_dat_l4a[0:1]; + wire [0:q_dat_width_g-1] q_dat_l4b[0:1]; + wire [0:q_dat_width_g-1] q_dat_l8a; + wire [0:q_dat_width_g-1] q_dat_l8b; + wire [0:q_dat_width_g-1] q_dat_l8; + + wire [0:7] selval1_b; + wire [0:7] selpri1; + wire [0:7] selpri1_b; + wire [0:3] selval2; + wire [0:3] selpri2; + wire [0:3] selpri2_b; + wire [0:1] selval4_b; + wire [0:1] selpri4; + wire [0:1] selpri4_b; + wire selval8; + wire selpri8; + wire selpri8_b; + + (* analysis_not_referenced="true" *) + wire selpri1_unused; + (* analysis_not_referenced="true" *) + wire selpri1_b_unused; + (* analysis_not_referenced="true" *) + wire q_dat_l1_unused; + + + parameter aryoff = q_dat_width_g; + + + assign selval1_b[0] = ~(cond[0] | cond[1]); + assign selval1_b[1] = ~(cond[2] | cond[3]); + assign selval1_b[2] = ~(cond[4] | cond[5]); + assign selval1_b[3] = ~(cond[6] | cond[7]); + generate + if (q_num_entries_g == 8) + begin : selval1_gen08 + assign selval1_b[4] = 1'b1; + assign selval1_b[5] = 1'b1; + assign selval1_b[6] = 1'b1; + assign selval1_b[7] = 1'b1; + end + endgenerate + generate + if (q_num_entries_g == 12) + begin : selval1_gen0 + assign selval1_b[4] = ~(cond[8] | cond[9]); + assign selval1_b[5] = ~(cond[10] | cond[11]); + assign selval1_b[6] = 1'b1; + assign selval1_b[7] = 1'b1; + end + endgenerate + generate + if (q_num_entries_g == 16) + begin : selval1_gen1 + assign selval1_b[4] = ~(cond[8] | cond[9]); + assign selval1_b[5] = ~(cond[10] | cond[11]); + assign selval1_b[6] = ~(cond[12] | cond[13]); + assign selval1_b[7] = ~(cond[14] | cond[15]); + end + endgenerate + + assign selpri1_b[0] = (~cond[1]); + assign selpri1_b[1] = (~cond[3]); + assign selpri1_b[2] = (~cond[5]); + assign selpri1_b[3] = (~cond[7]); + generate + if (q_num_entries_g == 8) + begin : selpri1_gen08 + assign selpri1_b[4] = 1'b1; + assign selpri1_b[5] = 1'b1; + assign selpri1_b[6] = 1'b1; + assign selpri1_b[7] = 1'b1; + assign selpri1_b_unused = selpri1_b[4] | selpri1_b[5] | selpri1_b[6] | selpri1_b[7] ; + end + endgenerate + generate + if (q_num_entries_g == 12) + begin : selpri1_gen0 + assign selpri1_b[4] = (~cond[9]); + assign selpri1_b[5] = (~cond[11]); + assign selpri1_b[6] = 1'b1; + assign selpri1_b[7] = 1'b1; + assign selpri1_b_unused = selpri1_b[6] | selpri1_b[7] ; + end + endgenerate + generate + if (q_num_entries_g == 16) + begin : selpri1_gen1 + assign selpri1_b[4] = (~cond[9]); + assign selpri1_b[5] = (~cond[11]); + assign selpri1_b[6] = (~cond[13]); + assign selpri1_b[7] = (~cond[15]); + assign selpri1_b_unused =1'b0; + end + endgenerate + + assign selpri1[0] = cond[1]; + assign selpri1[1] = cond[3]; + assign selpri1[2] = cond[5]; + assign selpri1[3] = cond[7]; + generate + if (q_num_entries_g == 8) + begin : selpri1_gen0b8 + assign selpri1[4] = 1'b0; + assign selpri1[5] = 1'b0; + assign selpri1[6] = 1'b0; + assign selpri1[7] = 1'b0; + assign selpri1_unused = selpri1[4] | selpri1[5] | selpri1[6] | selpri1[7] ; + end + endgenerate + generate + if (q_num_entries_g == 12) + begin : selpri1_gen0b + assign selpri1[4] = cond[9]; + assign selpri1[5] = cond[11]; + assign selpri1[6] = 1'b0; + assign selpri1[7] = 1'b0; + assign selpri1_unused = selpri1[6] | selpri1[7]; + end + endgenerate + generate + if (q_num_entries_g == 16) + begin : selpri1_gen1b + assign selpri1[4] = cond[9]; + assign selpri1[5] = cond[11]; + assign selpri1[6] = cond[13]; + assign selpri1[7] = cond[15]; + + assign selpri1_unused=1'b0; + + end + endgenerate + + assign selval2[0] = ~(selval1_b[0] & selval1_b[1]); + assign selval2[1] = ~(selval1_b[2] & selval1_b[3]); + assign selval2[2] = ~(selval1_b[4] & selval1_b[5]); + assign selval2[3] = ~(selval1_b[6] & selval1_b[7]); + + assign selpri2[0] = (~selval1_b[1]); + assign selpri2[1] = (~selval1_b[3]); + assign selpri2[2] = (~selval1_b[5]); + assign selpri2[3] = (~selval1_b[7]); + assign selpri2_b[0] = selval1_b[1]; + assign selpri2_b[1] = selval1_b[3]; + assign selpri2_b[2] = selval1_b[5]; + assign selpri2_b[3] = selval1_b[7]; + + assign selval4_b[0] = ~(selval2[0] | selval2[1]); + assign selval4_b[1] = ~(selval2[2] | selval2[3]); + assign selpri4_b[0] = (~selval2[1]); + assign selpri4_b[1] = (~selval2[3]); + assign selpri4[0] = selval2[1]; + assign selpri4[1] = selval2[3]; + + assign selval8 = ~(selval4_b[0] & selval4_b[1]); + assign selpri8 = (~selval4_b[1]); + assign selpri8_b = selval4_b[1]; + + //------------------------------------------------------------------------------------------------------- + // Instruction Muxing + //------------------------------------------------------------------------------------------------------- + + // Level 1 + // 01 23 45 67 89 1011 1213 1415 + assign q_dat_l1a[0] = ~(din[0*aryoff:0*aryoff+aryoff-1] & {q_dat_width_g{selpri1_b[0]}}); + assign q_dat_l1b[0] = ~(din[1*aryoff:1*aryoff+aryoff-1] & {q_dat_width_g{selpri1[0]}}); + assign q_dat_l1[0] = ~(q_dat_l1a[0] & q_dat_l1b[0]); + + assign q_dat_l1a[1] = ~(din[2*aryoff:2*aryoff+aryoff-1] & {q_dat_width_g{selpri1_b[1]}}); + assign q_dat_l1b[1] = ~(din[3*aryoff:3*aryoff+aryoff-1] & {q_dat_width_g{selpri1[1]}}); + assign q_dat_l1[1] = ~(q_dat_l1a[1] & q_dat_l1b[1]); + + assign q_dat_l1a[2] = ~(din[4*aryoff:4*aryoff+aryoff-1] & {q_dat_width_g{selpri1_b[2]}}); + assign q_dat_l1b[2] = ~(din[5*aryoff:5*aryoff+aryoff-1] & {q_dat_width_g{selpri1[2]}}); + assign q_dat_l1[2] = ~(q_dat_l1a[2] & q_dat_l1b[2]); + + assign q_dat_l1a[3] = ~(din[6*aryoff:6*aryoff+aryoff-1] & {q_dat_width_g{selpri1_b[3]}}); + assign q_dat_l1b[3] = ~(din[7*aryoff:7*aryoff+aryoff-1] & {q_dat_width_g{selpri1[3]}}); + assign q_dat_l1[3] = ~(q_dat_l1a[3] & q_dat_l1b[3]); + + + generate + if (q_num_entries_g == 8) + begin : l1_gen8 + assign q_dat_l1a[4] = {q_dat_width_g{1'b0}}; + assign q_dat_l1b[4] = {q_dat_width_g{1'b0}}; + assign q_dat_l1[4] = {q_dat_width_g{1'b0}}; + + assign q_dat_l1a[5] = {q_dat_width_g{1'b0}}; + assign q_dat_l1b[5] = {q_dat_width_g{1'b0}}; + assign q_dat_l1[5] = {q_dat_width_g{1'b0}}; + + assign q_dat_l1a[6] = {q_dat_width_g{1'b0}}; + assign q_dat_l1b[6] = {q_dat_width_g{1'b0}}; + assign q_dat_l1[6] = {q_dat_width_g{1'b0}}; + + assign q_dat_l1a[7] = {q_dat_width_g{1'b0}}; + assign q_dat_l1b[7] = {q_dat_width_g{1'b0}}; + assign q_dat_l1[7] = {q_dat_width_g{1'b0}}; + + assign q_dat_l1_unused = (|q_dat_l1a[4]) | (|q_dat_l1a[5]) | (|q_dat_l1a[6]) | (|q_dat_l1a[7]) | + (|q_dat_l1b[4]) | (|q_dat_l1b[5]) | (|q_dat_l1b[6]) | (|q_dat_l1b[7]) | + (|q_dat_l1[4]) | (|q_dat_l1[5]) | (|q_dat_l1[6]) | (|q_dat_l1[7]) ; + + end + endgenerate + generate + if (q_num_entries_g == 12) + begin : l1_gen12 + assign q_dat_l1a[4] = ~(din[8*aryoff:8*aryoff+aryoff-1] & {q_dat_width_g{selpri1_b[4]}}); + assign q_dat_l1b[4] = ~(din[9*aryoff:9*aryoff+aryoff-1] & {q_dat_width_g{selpri1[4]}}); + assign q_dat_l1[4] = ~(q_dat_l1a[4] & q_dat_l1b[4]); + + assign q_dat_l1a[5] = ~(din[10*aryoff:10*aryoff+aryoff-1] & {q_dat_width_g{selpri1_b[5]}}); + assign q_dat_l1b[5] = ~(din[11*aryoff:11*aryoff+aryoff-1] & {q_dat_width_g{selpri1[5]}}); + assign q_dat_l1[5] = ~(q_dat_l1a[5] & q_dat_l1b[5]); + + assign q_dat_l1a[6] = {q_dat_width_g{1'b0}}; + assign q_dat_l1b[6] = {q_dat_width_g{1'b0}}; + assign q_dat_l1[6] = {q_dat_width_g{1'b0}}; + + assign q_dat_l1a[7] = {q_dat_width_g{1'b0}}; + assign q_dat_l1b[7] = {q_dat_width_g{1'b0}}; + assign q_dat_l1[7] = {q_dat_width_g{1'b0}}; + + assign q_dat_l1_unused = (|q_dat_l1a[6]) | (|q_dat_l1a[7]) | + (|q_dat_l1b[6]) | (|q_dat_l1b[7]) | + (|q_dat_l1[6]) | (|q_dat_l1[7]) ; + end + endgenerate + generate + if (q_num_entries_g == 16) + begin : l1_gen16 + + assign q_dat_l1a[4] = ~(din[8*aryoff:8*aryoff+aryoff-1] & {q_dat_width_g{selpri1_b[4]}}); + assign q_dat_l1b[4] = ~(din[9*aryoff:9*aryoff+aryoff-1] & {q_dat_width_g{selpri1[4]}}); + assign q_dat_l1[4] = ~(q_dat_l1a[4] & q_dat_l1b[4]); + + assign q_dat_l1a[5] = ~(din[10*aryoff:10*aryoff+aryoff-1] & {q_dat_width_g{selpri1_b[5]}}); + assign q_dat_l1b[5] = ~(din[11*aryoff:11*aryoff+aryoff-1] & {q_dat_width_g{selpri1[5]}}); + assign q_dat_l1[5] = ~(q_dat_l1a[5] & q_dat_l1b[5]); + + assign q_dat_l1a[6] = ~(din[12*aryoff:12*aryoff+aryoff-1] & {q_dat_width_g{selpri1_b[6]}}); + assign q_dat_l1b[6] = ~(din[13*aryoff:13*aryoff+aryoff-1] & {q_dat_width_g{selpri1[6]}}); + assign q_dat_l1[6] = ~(q_dat_l1a[6] & q_dat_l1b[6]); + + assign q_dat_l1a[7] = ~(din[14*aryoff:14*aryoff+aryoff-1] & {q_dat_width_g{selpri1_b[7]}}); + assign q_dat_l1b[7] = ~(din[15*aryoff:15*aryoff+aryoff-1] & {q_dat_width_g{selpri1[7]}}); + assign q_dat_l1[7] = ~(q_dat_l1a[7] & q_dat_l1b[7]); + + assign q_dat_l1_unused = 1'b0; + + end + endgenerate + + // Level 2 + // 0123 4567 891011 12131415 + assign q_dat_l2a[0] = ~(q_dat_l1[0] & {q_dat_width_g{selpri2_b[0]}}); + assign q_dat_l2b[0] = ~(q_dat_l1[1] & {q_dat_width_g{selpri2[0]}}); + assign q_dat_l2[0] = ~(q_dat_l2a[0] & q_dat_l2b[0]); + + assign q_dat_l2a[1] = ~(q_dat_l1[2] & {q_dat_width_g{selpri2_b[1]}}); + assign q_dat_l2b[1] = ~(q_dat_l1[3] & {q_dat_width_g{selpri2[1]}}); + assign q_dat_l2[1] = ~(q_dat_l2a[1] & q_dat_l2b[1]); + + assign q_dat_l2a[2] = ~(q_dat_l1[4] & {q_dat_width_g{selpri2_b[2]}}); + assign q_dat_l2b[2] = ~(q_dat_l1[5] & {q_dat_width_g{selpri2[2]}}); + assign q_dat_l2[2] = ~(q_dat_l2a[2] & q_dat_l2b[2]); + + assign q_dat_l2a[3] = ~(q_dat_l1[6] & {q_dat_width_g{selpri2_b[3]}}); + assign q_dat_l2b[3] = ~(q_dat_l1[7] & {q_dat_width_g{selpri2[3]}}); + assign q_dat_l2[3] = ~(q_dat_l2a[3] & q_dat_l2b[3]); + + // Level 4 + // 01234567 89101112131415 + assign q_dat_l4a[0] = ~(q_dat_l2[0] & {q_dat_width_g{selpri4_b[0]}}); + assign q_dat_l4b[0] = ~(q_dat_l2[1] & {q_dat_width_g{selpri4[0]}}); + assign q_dat_l4[0] = ~(q_dat_l4a[0] & q_dat_l4b[0]); + + assign q_dat_l4a[1] = ~(q_dat_l2[2] & {q_dat_width_g{selpri4_b[1]}}); + assign q_dat_l4b[1] = ~(q_dat_l2[3] & {q_dat_width_g{selpri4[1]}}); + assign q_dat_l4[1] = ~(q_dat_l4a[1] & q_dat_l4b[1]); + + // Level 8 + // 0123456789101112131415 + assign q_dat_l8a = ~(q_dat_l4[0] & {q_dat_width_g{selpri8_b}}); + assign q_dat_l8b = ~(q_dat_l4[1] & {q_dat_width_g{selpri8}}); + assign q_dat_l8 = ~(q_dat_l8a & q_dat_l8b); + + assign dout = q_dat_l8 & {q_dat_width_g{selval8}}; + +endmodule // rv_prisel diff --git a/dev/verilog/work/rv_rf_byp.v b/dev/verilog/work/rv_rf_byp.v new file mode 100755 index 0000000..f1eaae0 --- /dev/null +++ b/dev/verilog/work/rv_rf_byp.v @@ -0,0 +1,3463 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: A2O Bypass Control +// +//***************************************************************************** + +module rv_rf_byp( + +`include "tri_a2o.vh" + + //------------------------------------------------------------------- + // Completion flush + //------------------------------------------------------------------- + input [0:`THREADS-1] cp_flush, + + //------------------------------------------------------------------- + // Interface with RV + //------------------------------------------------------------------- + input [0:`THREADS-1] rv_byp_fx0_vld, // FX0 Ports + input [0:`ITAG_SIZE_ENC-1] rv_byp_fx0_itag, + input [0:3] rv_byp_fx0_ilat, + input rv_byp_fx0_ord, + input rv_byp_fx0_t1_v, + input [0:2] rv_byp_fx0_t1_t, + input rv_byp_fx0_t2_v, + input [0:2] rv_byp_fx0_t2_t, + input rv_byp_fx0_t3_v, + input [0:2] rv_byp_fx0_t3_t, + input [0:2] rv_byp_fx0_s1_t, + input [0:2] rv_byp_fx0_s2_t, + input [0:2] rv_byp_fx0_s3_t, + input rv_byp_fx0_ex0_is_brick, + + input [0:`THREADS-1] rv_byp_fx0_ilat0_vld, + input [0:`THREADS-1] rv_byp_fx0_ilat1_vld, + + input [0:`THREADS-1] rv_byp_lq_vld, // LQ Ports + input rv_byp_lq_t1_v, + input rv_byp_lq_t3_v, + input [0:2] rv_byp_lq_t3_t, + input [0:2] rv_byp_lq_s1_t, + input [0:2] rv_byp_lq_s2_t, + input [0:`ITAG_SIZE_ENC-1] rv_byp_lq_ex0_s1_itag, + input [0:`ITAG_SIZE_ENC-1] rv_byp_lq_ex0_s2_itag, + input [0:`THREADS-1] rv_byp_fx1_vld, // FX1 Ports + input [0:`ITAG_SIZE_ENC-1] rv_byp_fx1_itag, + (* analysis_not_referenced="<0>true" *) + input [0:3] rv_byp_fx1_ilat, + input rv_byp_fx1_t1_v, + input rv_byp_fx1_t2_v, + input rv_byp_fx1_t3_v, + input [0:2] rv_byp_fx1_s1_t, + input [0:2] rv_byp_fx1_s2_t, + input [0:2] rv_byp_fx1_s3_t, + input rv_byp_fx1_ex0_isStore, + input [0:`THREADS-1] rv_byp_fx1_ilat0_vld, + input [0:`THREADS-1] rv_byp_fx1_ilat1_vld, + + //------------------------------------------------------------------- + // Interface with FXU0 + //------------------------------------------------------------------- + output [1:11] rv_fx0_ex0_s1_fx0_sel, + output [1:11] rv_fx0_ex0_s2_fx0_sel, + output [1:11] rv_fx0_ex0_s3_fx0_sel, + output [4:8] rv_fx0_ex0_s1_lq_sel, + output [4:8] rv_fx0_ex0_s2_lq_sel, + output [4:8] rv_fx0_ex0_s3_lq_sel, + output [1:6] rv_fx0_ex0_s1_fx1_sel, + output [1:6] rv_fx0_ex0_s2_fx1_sel, + output [1:6] rv_fx0_ex0_s3_fx1_sel, + + //------------------------------------------------------------------- + // Interface with LQ + //------------------------------------------------------------------- + output [2:12] rv_lq_ex0_s1_fx0_sel, + output [2:12] rv_lq_ex0_s2_fx0_sel, + output [4:8] rv_lq_ex0_s1_lq_sel, + output [4:8] rv_lq_ex0_s2_lq_sel, + output [2:7] rv_lq_ex0_s1_fx1_sel, + output [2:7] rv_lq_ex0_s2_fx1_sel, + + //------------------------------------------------------------------- + // Interface with FXU1 + //------------------------------------------------------------------- + output [1:11] rv_fx1_ex0_s1_fx0_sel, + output [1:11] rv_fx1_ex0_s2_fx0_sel, + output [1:11] rv_fx1_ex0_s3_fx0_sel, + output [4:8] rv_fx1_ex0_s1_lq_sel, + output [4:8] rv_fx1_ex0_s2_lq_sel, + output [4:8] rv_fx1_ex0_s3_lq_sel, + output [1:6] rv_fx1_ex0_s1_fx1_sel, + output [1:6] rv_fx1_ex0_s2_fx1_sel, + output [1:6] rv_fx1_ex0_s3_fx1_sel, + + output [2:3] rv_fx0_ex0_s1_rel_sel, + output [2:3] rv_fx0_ex0_s2_rel_sel, + output [2:3] rv_fx0_ex0_s3_rel_sel, + output [2:3] rv_lq_ex0_s1_rel_sel, + output [2:3] rv_lq_ex0_s2_rel_sel, + output [2:3] rv_fx1_ex0_s1_rel_sel, + output [2:3] rv_fx1_ex0_s2_rel_sel, + output [2:3] rv_fx1_ex0_s3_rel_sel, + + //------------------------------------------------------------------- + // FX0 RV Release / Spec Flush + //------------------------------------------------------------------- + output [0:`THREADS-1] fx0_rv_itag_vld, + output fx0_rv_itag_abort, + output [0:`ITAG_SIZE_ENC-1] fx0_rv_itag, + output [0:`THREADS-1] fx0_release_ord_hold, + + output [0:`THREADS-1] fx0_rv_ext_itag_vld, + output fx0_rv_ext_itag_abort, + output [0:`ITAG_SIZE_ENC-1] fx0_rv_ext_itag, + + input fx0_rv_ord_complete, + input [0:`THREADS-1] fx0_rv_ord_tid, + input [0:`ITAG_SIZE_ENC-1] fx0_rv_ord_itag, + + input [0:`ITAG_SIZE_ENC-1] rv_fx0_s1_itag, + input [0:`ITAG_SIZE_ENC-1] rv_fx0_s2_itag, + input [0:`ITAG_SIZE_ENC-1] rv_fx0_s3_itag, + + input fx0_rv_ex2_s1_abort, + input fx0_rv_ex2_s2_abort, + input fx0_rv_ex2_s3_abort, + + //------------------------------------------------------------------- + // FX1 RV Release / Spec Flush + //------------------------------------------------------------------- + output [0:`THREADS-1] fx1_rv_itag_vld, + output fx1_rv_itag_abort, + output [0:`ITAG_SIZE_ENC-1] fx1_rv_itag, + + output [0:`THREADS-1] fx1_rv_ext_itag_vld, + output fx1_rv_ext_itag_abort, + output [0:`ITAG_SIZE_ENC-1] fx1_rv_ext_itag, + + + input [0:`ITAG_SIZE_ENC-1] rv_fx1_s1_itag, + input [0:`ITAG_SIZE_ENC-1] rv_fx1_s2_itag, + input [0:`ITAG_SIZE_ENC-1] rv_fx1_s3_itag, + + input fx1_rv_ex2_s1_abort, + input fx1_rv_ex2_s2_abort, + input fx1_rv_ex2_s3_abort, + + //------------------------------------------------------------------- + // LQ Release and Restart + //------------------------------------------------------------------- + input [0:`ITAG_SIZE_ENC-1] rv_byp_lq_itag, + + input [0:`THREADS-1] lq_rv_itag2_vld, + input [0:`ITAG_SIZE_ENC-1] lq_rv_itag2, + + //------------------------------------------------------------------- + // Clocks & Power + //------------------------------------------------------------------- + (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) // nclk + input [0:`NCLK_WIDTH-1] nclk, + inout vdd, + inout gnd, + + //------------------------------------------------------------------- + // Pervasive + //------------------------------------------------------------------- + input func_sl_thold_1, + input sg_1, + input clkoff_b, + input act_dis, + input ccflush_dc, + input delay_lclkr, + input mpw1_b, + input mpw2_b, + input scan_in, + + output scan_out + ); + + + + //------------------------------------------------------------------------------------------------------------ + // Pervasive + //------------------------------------------------------------------------------------------------------------ + parameter tiup = 1'b1; + parameter tidn = 1'b0; + + parameter elmnt_width = 3 + `THREADS; // Valid (1) + max_pool_enc (6) + Type (3) = 10, or max_pool_enc + 4 + + + //------------------------------------------------------------------- + // Signals + //------------------------------------------------------------------- + wire d_mode; + wire [0:2] rv_byp_fx1_t2_t; + wire [0:2] rv_byp_fx1_t3_t; + + wire [1:11] fx0_ex0_s1_fx0_sel; + wire [1:11] fx0_ex0_s2_fx0_sel; + wire [1:11] fx0_ex0_s3_fx0_sel; + wire [1:11] fxu0_s1_fxu0_itag_match; + wire [1:11] fxu0_s2_fxu0_itag_match; + wire [1:11] fxu0_s3_fxu0_itag_match; + wire [1:6] fx0_ex0_s1_fx1_sel; + wire [1:6] fx0_ex0_s2_fx1_sel; + wire [1:6] fx0_ex0_s3_fx1_sel; + wire [1:6] fxu0_s1_fxu1_itag_match; + wire [1:6] fxu0_s2_fxu1_itag_match; + wire [1:6] fxu0_s3_fxu1_itag_match; + wire [4:8] fxu0_s1_lq_itag_match; + wire [4:8] fxu0_s2_lq_itag_match; + wire [4:8] fxu0_s3_lq_itag_match; + wire [1:11] fxu0_s1_fxu0_t1_match; + wire [1:11] fxu0_s1_fxu0_t2_match; + wire [1:11] fxu0_s1_fxu0_t3_match; + wire [1:11] fxu0_s2_fxu0_t1_match; + wire [1:11] fxu0_s2_fxu0_t2_match; + wire [1:11] fxu0_s2_fxu0_t3_match; + wire [1:11] fxu0_s3_fxu0_t1_match; + wire [1:11] fxu0_s3_fxu0_t2_match; + wire [1:11] fxu0_s3_fxu0_t3_match; + wire [4:8] fxu0_s1_lq_t1_match; + wire [4:8] fxu0_s1_lq_t2_match; + wire [4:8] fxu0_s1_lq_t3_match; + wire [4:8] fxu0_s2_lq_t1_match; + wire [4:8] fxu0_s2_lq_t2_match; + wire [4:8] fxu0_s2_lq_t3_match; + wire [4:8] fxu0_s3_lq_t1_match; + wire [4:8] fxu0_s3_lq_t2_match; + wire [4:8] fxu0_s3_lq_t3_match; + wire [1:6] fxu0_s1_fxu1_t1_match; + wire [1:6] fxu0_s1_fxu1_t2_match; + wire [1:6] fxu0_s1_fxu1_t3_match; + wire [1:6] fxu0_s2_fxu1_t1_match; + wire [1:6] fxu0_s2_fxu1_t2_match; + wire [1:6] fxu0_s2_fxu1_t3_match; + wire [1:6] fxu0_s3_fxu1_t1_match; + wire [1:6] fxu0_s3_fxu1_t2_match; + wire [1:6] fxu0_s3_fxu1_t3_match; + + wire [2:12] lq_ex0_s1_fx0_sel; + wire [2:12] lq_ex0_s2_fx0_sel; + wire [2:12] lq_s1_fxu0_itag_match; + wire [2:12] lq_s2_fxu0_itag_match; + wire [2:7] lq_s1_fxu1_itag_match; + wire [2:7] lq_s2_fxu1_itag_match; + wire [4:8] lq_s1_lq_itag_match; + wire [4:8] lq_s2_lq_itag_match; + wire [2:12] lq_s1_fxu0_t1_match; + wire [2:12] lq_s1_fxu0_t2_match; + wire [2:12] lq_s1_fxu0_t3_match; + wire [2:12] lq_s2_fxu0_t1_match; + wire [2:12] lq_s2_fxu0_t2_match; + wire [2:12] lq_s2_fxu0_t3_match; + wire [4:8] lq_s1_lq_t1_match; + wire [4:8] lq_s1_lq_t2_match; + wire [4:8] lq_s1_lq_t3_match; + wire [4:8] lq_s2_lq_t1_match; + wire [4:8] lq_s2_lq_t2_match; + wire [4:8] lq_s2_lq_t3_match; + wire [2:7] lq_ex0_s1_fx1_sel; + wire [2:7] lq_ex0_s2_fx1_sel; + wire [2:7] lq_s1_fxu1_t1_match; + wire [2:7] lq_s1_fxu1_t2_match; + wire [2:7] lq_s1_fxu1_t3_match; + wire [2:7] lq_s2_fxu1_t1_match; + wire [2:7] lq_s2_fxu1_t2_match; + wire [2:7] lq_s2_fxu1_t3_match; + wire [1:11] fx1_ex0_s1_fx0_sel; + wire [1:11] fx1_ex0_s2_fx0_sel; + wire [1:11] fx1_ex0_s3_fx0_sel; + wire [1:11] fxu1_s1_fxu0_itag_match; + wire [1:11] fxu1_s2_fxu0_itag_match; + wire [1:11] fxu1_s3_fxu0_itag_match; + wire [1:6] fx1_ex0_s1_fx1_sel; + wire [1:6] fx1_ex0_s2_fx1_sel; + wire [1:6] fx1_ex0_s3_fx1_sel; + wire [1:6] fxu1_s1_fxu1_itag_match; + wire [1:6] fxu1_s2_fxu1_itag_match; + wire [1:6] fxu1_s3_fxu1_itag_match; + wire [4:8] fxu1_s1_lq_itag_match; + wire [4:8] fxu1_s2_lq_itag_match; + wire [4:8] fxu1_s3_lq_itag_match; + wire [1:11] fxu1_s1_fxu0_t1_match; + wire [1:11] fxu1_s1_fxu0_t2_match; + wire [1:11] fxu1_s1_fxu0_t3_match; + wire [1:11] fxu1_s2_fxu0_t1_match; + wire [1:11] fxu1_s2_fxu0_t2_match; + wire [1:11] fxu1_s2_fxu0_t3_match; + wire [1:11] fxu1_s3_fxu0_t1_match; + wire [1:11] fxu1_s3_fxu0_t2_match; + wire [1:11] fxu1_s3_fxu0_t3_match; + wire [4:8] fxu1_s1_lq_t1_match; + wire [4:8] fxu1_s1_lq_t2_match; + wire [4:8] fxu1_s1_lq_t3_match; + wire [4:8] fxu1_s2_lq_t1_match; + wire [4:8] fxu1_s2_lq_t2_match; + wire [4:8] fxu1_s2_lq_t3_match; + wire [4:8] fxu1_s3_lq_t1_match; + wire [4:8] fxu1_s3_lq_t2_match; + wire [4:8] fxu1_s3_lq_t3_match; + wire [1:6] fxu1_s1_fxu1_t1_match; + wire [1:6] fxu1_s1_fxu1_t2_match; + wire [1:6] fxu1_s1_fxu1_t3_match; + wire [1:6] fxu1_s2_fxu1_t1_match; + wire [1:6] fxu1_s2_fxu1_t2_match; + wire [1:6] fxu1_s2_fxu1_t3_match; + wire [1:6] fxu1_s3_fxu1_t1_match; + wire [1:6] fxu1_s3_fxu1_t2_match; + wire [1:6] fxu1_s3_fxu1_t3_match; + + wire [2:3] fxu0_s1_rel_itag_match; + wire [2:3] fxu0_s2_rel_itag_match; + wire [2:3] fxu0_s3_rel_itag_match; + wire [2:3] fxu0_s1_rel_match; + wire [2:3] fxu0_s2_rel_match; + wire [2:3] fxu0_s3_rel_match; + wire [2:3] fxu1_s1_rel_itag_match; + wire [2:3] fxu1_s2_rel_itag_match; + wire [2:3] fxu1_s3_rel_itag_match; + wire [2:3] fxu1_s1_rel_match; + wire [2:3] fxu1_s2_rel_match; + wire [2:3] fxu1_s3_rel_match; + wire [2:3] lq_s1_rel_itag_match; + wire [2:3] lq_s2_rel_itag_match; + wire [2:3] lq_s1_rel_match; + wire [2:3] lq_s2_rel_match; + + wire fx0_rv1_ilat_match; + wire fx0_ex0_fast_match; + wire fx0_ex0_ilat_match; + wire fx0_ex1_ilat_match; + wire fx0_ex2_ilat_match; + wire fx0_ex3_ilat_match; + wire fx0_ex4_ilat_match; + + wire [0:9] fx0_ex0_sched_rel; + wire [0:9] fx0_ex0_sched_rel_pri; + wire fx0_rv1_ilat0; + wire fx0_sched_rel_rv; + wire fx0_sched_rel_rv_ilat0; + wire fx0_sched_rel_ex0_fast; + wire fx0_ex0_stq_pipe_val; + wire fx0_insert_ord; + + wire fx0_ex2_abort; + wire fx0_rel_itag_abort_d; + wire fx0_rel_itag_abort_q; + wire fx0_ext_rel_itag_abort_d; + wire fx0_ext_rel_itag_abort_q; + wire fx0_rv_itag_abort_int; + wire [3:4] fx0_abort_d; + wire [3:4] fx0_abort_q; + + wire fx1_ex2_abort; + wire fx1_rel_itag_abort_d; + wire fx1_rel_itag_abort_q; + wire fx1_ext_rel_itag_abort_d; + wire fx1_ext_rel_itag_abort_q; + wire fx1_rv_itag_abort_int; + wire [3:4] fx1_abort_d; + wire [3:4] fx1_abort_q; + + + wire fx1_rv1_ilat_match; + wire fx1_ex0_fast_match; + wire fx1_ex0_ilat_match; + wire fx1_ex1_ilat_match; + wire fx1_ex2_ilat_match; + wire fx1_ex3_ilat_match; + + wire [0:4] fx1_ex0_sched_rel; + wire [0:4] fx1_ex0_sched_rel_pri; + wire fx1_rv1_ilat0; + wire fx1_sched_rel_rv; + wire fx1_sched_rel_rv_ilat0; + wire fx1_sched_rel_ex0_fast; + wire fx1_ex0_stq_pipe_val; + + wire [0:`ITAG_SIZE_ENC-1] fx0_ex0_s1_itag_q; + wire [0:`ITAG_SIZE_ENC-1] fx0_ex0_s2_itag_q; + wire [0:`ITAG_SIZE_ENC-1] fx0_ex0_s3_itag_q; + + + wire [0:`ITAG_SIZE_ENC-1] fx1_ex0_s1_itag_q; + wire [0:`ITAG_SIZE_ENC-1] fx1_ex0_s2_itag_q; + wire [0:`ITAG_SIZE_ENC-1] fx1_ex0_s3_itag_q; + + //------------------------------------------------------------------- + // Latches + //-------------------------------------------------------------------\ + //FX0 + wire [0:12] fx0_act; + + wire [0:`THREADS-1] fx0_vld_d[0:11]; + wire [0:`THREADS-1] fx0_vld_q[0:11]; + wire [0:`ITAG_SIZE_ENC-1] fx0_itag_d[0:12]; + wire [0:`ITAG_SIZE_ENC-1] fx0_itag_q[0:12]; + wire [0:`THREADS-1] fx1_vld_d[0:6]; + wire [0:`THREADS-1] fx1_vld_q[0:6]; + wire [0:`ITAG_SIZE_ENC-1] fx1_itag_d[0:7]; + wire [0:`ITAG_SIZE_ENC-1] fx1_itag_q[0:7]; + + wire [0:3] fx0_ex0_ilat_d; + wire [0:3] fx0_ex1_ilat_d; + wire [0:3] fx0_ex2_ilat_d; + wire [0:3] fx0_ex3_ilat_d; + wire [0:3] fx0_ex4_ilat_d; + wire [0:3] fx0_ex5_ilat_d; + wire [0:3] fx0_ex6_ilat_d; + wire [0:3] fx0_ex7_ilat_d; + wire [0:3] fx0_ex8_ilat_d; + wire [0:3] fx0_ex0_ilat_q; + wire [0:3] fx0_ex1_ilat_q; + wire [0:3] fx0_ex2_ilat_q; + wire [0:3] fx0_ex3_ilat_q; + wire [0:3] fx0_ex4_ilat_q; + wire [0:3] fx0_ex5_ilat_q; + wire [0:3] fx0_ex6_ilat_q; + wire [0:3] fx0_ex7_ilat_q; + wire [0:3] fx0_ex8_ilat_q; + + wire [1:7] fx0_is_brick_d; + wire [1:7] fx0_is_brick_q; + + wire fx0_ex5_mult_recirc; + wire fx0_ex6_mult_recirc; + wire fx0_ex7_mult_recirc; + wire fx0_mult_recirc; + wire fx0_ex5_recircd_d; + wire fx0_ex5_recircd_q; + wire fx0_ex6_recircd_d; + wire fx0_ex6_recircd_q; + wire fx0_ex7_recircd_d; + wire fx0_ex7_recircd_q; + + wire [0:`THREADS-1] fx0_rel_itag_vld_d; + wire [0:`THREADS-1] fx0_rel_itag_vld_q; + wire [0:`ITAG_SIZE_ENC-1] fx0_rel_itag_d; + wire [0:`ITAG_SIZE_ENC-1] fx0_rel_itag_q; + + wire [0:`THREADS-1] fx0_ext_rel_itag_vld_d; + wire [0:`THREADS-1] fx0_ext_rel_itag_vld_q; + wire [0:`ITAG_SIZE_ENC-1] fx0_ext_rel_itag_d; + wire [0:`ITAG_SIZE_ENC-1] fx0_ext_rel_itag_q; + wire fx0_ext_itag0_sel_d; + wire fx0_ext_itag0_sel_q; + wire fx0_ext_ilat_gt_1_need_rel; + wire [0:`THREADS-1] fx0_rv_itag_vld_int; + wire [0:`ITAG_SIZE_ENC-1] fx0_rv_itag_int; + + wire [0:4] fx0_need_rel_d; + wire [0:4] fx0_need_rel_q; + + wire [0:`THREADS-1] fx0_ex3_ord_rel_d; + wire [0:`THREADS-1] fx0_ex4_ord_rel_d; + wire [0:`THREADS-1] fx0_ex5_ord_rel_d; + wire [0:`THREADS-1] fx0_ex6_ord_rel_d; + wire [0:`THREADS-1] fx0_ex7_ord_rel_d; + wire [0:`THREADS-1] fx0_ex8_ord_rel_d; + wire [0:`THREADS-1] fx0_ex3_ord_rel_q; + wire [0:`THREADS-1] fx0_ex4_ord_rel_q; + wire [0:`THREADS-1] fx0_ex5_ord_rel_q; + wire [0:`THREADS-1] fx0_ex6_ord_rel_q; + wire [0:`THREADS-1] fx0_ex7_ord_rel_q; + wire [0:`THREADS-1] fx0_ex8_ord_rel_q; + wire [0:`THREADS-1] fx0_release_ord_hold_d; + wire [0:`THREADS-1] fx0_release_ord_hold_q; + + wire [0:`THREADS-1] ex3_ord_flush; + + wire fx0_ex0_ord_d; + wire fx0_ex1_ord_d; + wire fx0_ex2_ord_d; + wire fx0_ex3_ord_flush_d; + wire fx0_ex0_ord_q; + wire fx0_ex1_ord_q; + wire fx0_ex2_ord_q; + wire fx0_ex3_ord_flush_q; + + wire fx0_sched_rel_pri_or_d; + wire fx0_sched_rel_pri_or_q; + + //FX1 + wire [0:7] fx1_act; + + wire [0:2] fx1_ex0_ilat_d; + wire [0:2] fx1_ex1_ilat_d; + wire [0:2] fx1_ex2_ilat_d; + wire [0:2] fx1_ex3_ilat_d; + wire [0:2] fx1_ex4_ilat_d; + wire [0:2] fx1_ex5_ilat_d; + wire [0:2] fx1_ex6_ilat_d; + wire [0:2] fx1_ex0_ilat_q; + wire [0:2] fx1_ex1_ilat_q; + wire [0:2] fx1_ex2_ilat_q; + wire [0:2] fx1_ex3_ilat_q; + wire [0:2] fx1_ex4_ilat_q; + wire [0:2] fx1_ex5_ilat_q; + wire [0:2] fx1_ex6_ilat_q; + + wire [0:`THREADS-1] fx1_rel_itag_vld_d; + wire [0:`THREADS-1] fx1_rel_itag_vld_q; + wire [0:`ITAG_SIZE_ENC-1] fx1_rel_itag_d; + wire [0:`ITAG_SIZE_ENC-1] fx1_rel_itag_q; + wire [0:`THREADS-1] fx1_ext_rel_itag_vld_d; + wire [0:`THREADS-1] fx1_ext_rel_itag_vld_q; + wire [0:`ITAG_SIZE_ENC-1] fx1_ext_rel_itag_d; + wire [0:`ITAG_SIZE_ENC-1] fx1_ext_rel_itag_q; + wire fx1_ext_itag0_sel_d; + wire fx1_ext_itag0_sel_q; + wire fx1_ext_ilat_gt_1_need_rel; + wire [0:`THREADS-1] fx1_rv_itag_vld_int; + wire [0:`ITAG_SIZE_ENC-1] fx1_rv_itag_int; + + wire fx1_ex0_need_rel_d; + wire fx1_ex1_need_rel_d; + wire fx1_ex2_need_rel_d; + wire fx1_ex3_need_rel_d; + + wire fx1_ex0_need_rel_q; + wire fx1_ex1_need_rel_q; + wire fx1_ex2_need_rel_q; + wire fx1_ex3_need_rel_q; + + wire fx1_ex1_stq_pipe_d; + wire fx1_ex2_stq_pipe_d; + wire fx1_ex1_stq_pipe_q; + wire fx1_ex2_stq_pipe_q; + + wire fx1_sched_rel_pri_or_d; + wire fx1_sched_rel_pri_or_q; + + + wire [0:elmnt_width-1] fxu0_t1_d[0:12]; // FXU0 Targets + wire [0:elmnt_width-1] fxu0_t2_d[0:12]; + wire [0:elmnt_width-1] fxu0_t3_d[0:12]; + wire [0:elmnt_width-1] fxu0_s1_d; // FXU0 Sources + wire [0:elmnt_width-1] fxu0_s2_d; + wire [0:elmnt_width-1] fxu0_s3_d; + wire [0:elmnt_width-1] fxu0_t1_q[0:12]; // FXU0 Targets + wire [0:elmnt_width-1] fxu0_t2_q[0:12]; + wire [0:elmnt_width-1] fxu0_t3_q[0:12]; + wire [0:elmnt_width-1] fxu0_s1_q; // FXU0 Sources + wire [0:elmnt_width-1] fxu0_s2_q; + wire [0:elmnt_width-1] fxu0_s3_q; + wire [0:elmnt_width-1] lq_t1_d[0:8]; // LQ Targets + wire [0:elmnt_width-1] lq_t3_d[0:8]; + wire [0:elmnt_width-1] lq_s1_d; // Lq Sources + wire [0:elmnt_width-1] lq_s2_d; + wire [0:elmnt_width-1] lq_t1_q[0:8]; // LQ Targets + wire [0:elmnt_width-1] lq_t3_q[0:8]; + wire [0:elmnt_width-1] lq_s1_q; // Lq Sources + wire [0:elmnt_width-1] lq_s2_q; + wire [0:elmnt_width-1] fxu1_t1_d[0:7]; // FXU1 Targets + wire [0:elmnt_width-1] fxu1_t2_d[0:7]; + wire [0:elmnt_width-1] fxu1_t3_d[0:7]; + wire [0:elmnt_width-1] fxu1_s1_d; // FXU1 Sources + wire [0:elmnt_width-1] fxu1_s2_d; + wire [0:elmnt_width-1] fxu1_s3_d; + wire [0:elmnt_width-1] fxu1_t1_q[0:7]; // FXU1 Targets + wire [0:elmnt_width-1] fxu1_t2_q[0:7]; + wire [0:elmnt_width-1] fxu1_t3_q[0:7]; + wire [0:elmnt_width-1] fxu1_s1_q; // FXU1 Sources + wire [0:elmnt_width-1] fxu1_s2_q; + wire [0:elmnt_width-1] fxu1_s3_q; + + + wire [0:`THREADS-1] rel_vld_d[0:3]; + wire [0:`THREADS-1] rel_vld_q[0:3]; + wire [0:`ITAG_SIZE_ENC-1] rel_itag_d[0:3]; + wire [0:`ITAG_SIZE_ENC-1] rel_itag_q[0:3]; + + wire [0:`THREADS-1] cp_flush_q; + + + wire [0:8] lq_act; + wire [0:`THREADS-1] lq_vld_d[0:7]; + wire [0:`THREADS-1] lq_vld_q[0:7]; + wire [0:`ITAG_SIZE_ENC-1] lq_itag_d[0:8]; + wire [0:`ITAG_SIZE_ENC-1] lq_itag_q[0:8]; + + wire fx0_byp_rdy_nxt_0; + wire [0:`THREADS-1] fx0_byp_rdy_nxt[0:11]; + wire fx1_byp_rdy_nxt_0; + wire [0:`THREADS-1] fx1_byp_rdy_nxt[0:6]; + + //------------------------------------------------------------------- + // Scanchain + //------------------------------------------------------------------- + parameter fxu0_t1_offset = 0; + parameter fxu0_t2_offset = fxu0_t1_offset + elmnt_width * (13); + parameter fxu0_t3_offset = fxu0_t2_offset + elmnt_width * (13); + parameter fxu0_s1_offset = fxu0_t3_offset + elmnt_width * (13); + parameter fxu0_s2_offset = fxu0_s1_offset + elmnt_width; + parameter fxu0_s3_offset = fxu0_s2_offset + elmnt_width; + parameter lq_t1_offset = fxu0_s3_offset + elmnt_width; + parameter lq_t3_offset = lq_t1_offset + elmnt_width * (9); + parameter lq_s1_offset = lq_t3_offset + elmnt_width * (9); + parameter lq_s2_offset = lq_s1_offset + elmnt_width; + parameter fxu1_t1_offset = lq_s2_offset + elmnt_width; + parameter fxu1_t2_offset = fxu1_t1_offset + elmnt_width * (8); + parameter fxu1_t3_offset = fxu1_t2_offset + elmnt_width * (8); + parameter fxu1_s1_offset = fxu1_t3_offset + elmnt_width * (8); + parameter fxu1_s2_offset = fxu1_s1_offset + elmnt_width; + parameter fxu1_s3_offset = fxu1_s2_offset + elmnt_width; + + parameter rel_vld_offset = fxu1_s3_offset + elmnt_width; + parameter rel_itag_offset = rel_vld_offset + `THREADS * (4); + parameter cp_flush_offset = rel_itag_offset + `ITAG_SIZE_ENC * (4); + + //fx0 release + parameter fx0_is_brick_offset = cp_flush_offset + `THREADS; + parameter fx0_vld_offset = fx0_is_brick_offset+7; + + parameter fx0_itag_offset = fx0_vld_offset + `THREADS * (12); + + parameter fx0_ex0_ilat_offset = fx0_itag_offset + `ITAG_SIZE_ENC * (13); + parameter fx0_ex1_ilat_offset = fx0_ex0_ilat_offset + 4; + parameter fx0_ex2_ilat_offset = fx0_ex1_ilat_offset + 4; + parameter fx0_ex3_ilat_offset = fx0_ex2_ilat_offset + 4; + parameter fx0_ex4_ilat_offset = fx0_ex3_ilat_offset + 4; + parameter fx0_ex5_ilat_offset = fx0_ex4_ilat_offset + 4; + parameter fx0_ex6_ilat_offset = fx0_ex5_ilat_offset + 4; + parameter fx0_ex7_ilat_offset = fx0_ex6_ilat_offset + 4; + parameter fx0_ex8_ilat_offset = fx0_ex7_ilat_offset + 4; + + parameter fx0_rel_itag_vld_offset = fx0_ex8_ilat_offset + 4; + parameter fx0_rel_itag_offset = fx0_rel_itag_vld_offset + `THREADS; + parameter fx0_ext_rel_itag_vld_offset = fx0_rel_itag_offset + `ITAG_SIZE_ENC; + parameter fx0_ext_rel_itag_offset = fx0_ext_rel_itag_vld_offset + `THREADS; + parameter fx0_ext_itag0_sel_offset = fx0_ext_rel_itag_offset + `ITAG_SIZE_ENC; + + parameter fx0_need_rel_offset = fx0_ext_itag0_sel_offset + 1; + + parameter fx0_ex3_ord_rel_offset = fx0_need_rel_offset + 5; + parameter fx0_ex4_ord_rel_offset = fx0_ex3_ord_rel_offset + `THREADS; + parameter fx0_ex5_ord_rel_offset = fx0_ex4_ord_rel_offset + `THREADS; + parameter fx0_ex6_ord_rel_offset = fx0_ex5_ord_rel_offset + `THREADS; + parameter fx0_ex7_ord_rel_offset = fx0_ex6_ord_rel_offset + `THREADS; + parameter fx0_ex8_ord_rel_offset = fx0_ex7_ord_rel_offset + `THREADS; + parameter fx0_release_ord_hold_offset = fx0_ex8_ord_rel_offset + `THREADS; + + parameter fx0_ex0_ord_offset = fx0_release_ord_hold_offset + `THREADS; + parameter fx0_ex1_ord_offset = fx0_ex0_ord_offset + 1; + parameter fx0_ex2_ord_offset = fx0_ex1_ord_offset + 1; + parameter fx0_ex3_ord_flush_offset = fx0_ex2_ord_offset + 1; + parameter fx0_sched_rel_pri_or_offset = fx0_ex3_ord_flush_offset + 1; + + parameter fx0_rel_itag_abort_offset = fx0_sched_rel_pri_or_offset + 1; + parameter fx0_ext_rel_itag_abort_offset = fx0_rel_itag_abort_offset + 1; + parameter fx0_ex5_recircd_offset = fx0_ext_rel_itag_abort_offset + 1; + parameter fx0_ex6_recircd_offset = fx0_ex5_recircd_offset + 1; + parameter fx0_ex7_recircd_offset = fx0_ex6_recircd_offset + 1; + parameter fx0_abort_offset = fx0_ex7_recircd_offset + 1; + + //fx1 release + parameter fx1_vld_offset = fx0_abort_offset + 2;//3:4 + + parameter fx1_itag_offset = fx1_vld_offset + `THREADS * (7); + + parameter fx1_ex0_ilat_offset = fx1_itag_offset + `ITAG_SIZE_ENC * (8); + parameter fx1_ex1_ilat_offset = fx1_ex0_ilat_offset + 3; + parameter fx1_ex2_ilat_offset = fx1_ex1_ilat_offset + 3; + parameter fx1_ex3_ilat_offset = fx1_ex2_ilat_offset + 3; + parameter fx1_ex4_ilat_offset = fx1_ex3_ilat_offset + 3; + parameter fx1_ex5_ilat_offset = fx1_ex4_ilat_offset + 3; + parameter fx1_ex6_ilat_offset = fx1_ex5_ilat_offset + 3; + + parameter fx1_rel_itag_vld_offset = fx1_ex6_ilat_offset + 3; + parameter fx1_rel_itag_offset = fx1_rel_itag_vld_offset + `THREADS; + parameter fx1_ext_rel_itag_vld_offset = fx1_rel_itag_offset + `ITAG_SIZE_ENC; + parameter fx1_ext_rel_itag_offset = fx1_ext_rel_itag_vld_offset + `THREADS; + parameter fx1_ext_itag0_sel_offset = fx1_ext_rel_itag_offset + `ITAG_SIZE_ENC; + + parameter fx1_ex0_need_rel_offset = fx1_ext_itag0_sel_offset + 1; + parameter fx1_ex1_need_rel_offset = fx1_ex0_need_rel_offset + 1; + parameter fx1_ex2_need_rel_offset = fx1_ex1_need_rel_offset + 1; + parameter fx1_ex3_need_rel_offset = fx1_ex2_need_rel_offset + 1; + + parameter fx1_ex1_stq_pipe_offset = fx1_ex3_need_rel_offset + 1; + parameter fx1_ex2_stq_pipe_offset = fx1_ex1_stq_pipe_offset + 1; + + parameter fx1_sched_rel_pri_or_offset = fx1_ex2_stq_pipe_offset + 1; + + parameter fx1_rel_itag_abort_offset = fx1_sched_rel_pri_or_offset + 1; + parameter fx1_ext_rel_itag_abort_offset = fx1_rel_itag_abort_offset + 1; + parameter fx1_abort_offset = fx1_ext_rel_itag_abort_offset + 1; + + parameter fx0_ex0_s1_itag_offset = fx1_abort_offset + 2;//3:4 + parameter fx0_ex0_s2_itag_offset = fx0_ex0_s1_itag_offset + `ITAG_SIZE_ENC; + parameter fx0_ex0_s3_itag_offset = fx0_ex0_s2_itag_offset + `ITAG_SIZE_ENC; + + //fx1 spec flush + parameter fx1_ex0_s1_itag_offset = fx0_ex0_s3_itag_offset + `ITAG_SIZE_ENC; + parameter fx1_ex0_s2_itag_offset = fx1_ex0_s1_itag_offset + `ITAG_SIZE_ENC; + parameter fx1_ex0_s3_itag_offset = fx1_ex0_s2_itag_offset + `ITAG_SIZE_ENC; + + parameter lq_vld_offset = fx1_ex0_s3_itag_offset + `ITAG_SIZE_ENC; + parameter lq_itag_offset = lq_vld_offset + `THREADS * (8); + parameter scan_right = lq_itag_offset + `ITAG_SIZE_ENC * (9); + + wire [0:scan_right-1] siv; + wire [0:scan_right-1] sov; + + wire func_sl_thold_0; + wire func_sl_thold_0_b; + wire sg_0; + wire force_t; + + //!! Bugspray Include: rv_rf_byp; + + assign d_mode = 1'b0; + + assign rv_byp_fx1_t2_t = `xer_t; + assign rv_byp_fx1_t3_t = `cr_t; + + //---------------------------------------------------------------------------------------------------------------------------------------- + // Concatenate Relevant signals + //---------------------------------------------------------------------------------------------------------------------------------------- + + //Determine if we have a muliplier recirculation + assign fx0_ex5_mult_recirc = (fx0_ex5_ilat_q == 4'b0101) & fx0_is_brick_q[5] & |(fxu0_t1_q[5][0:`THREADS-1]) & ~fx0_ex5_recircd_q; + assign fx0_ex6_mult_recirc = (fx0_ex6_ilat_q == 4'b0110) & fx0_is_brick_q[6] & |(fxu0_t1_q[6][0:`THREADS-1]) & ~fx0_ex6_recircd_q; + assign fx0_ex7_mult_recirc = (fx0_ex7_ilat_q == 4'b0111) & fx0_is_brick_q[7] & |(fxu0_t1_q[7][0:`THREADS-1]) & ~fx0_ex7_recircd_q; + assign fx0_mult_recirc = fx0_ex5_mult_recirc | fx0_ex6_mult_recirc | fx0_ex7_mult_recirc ; + + assign fx0_ex5_recircd_d = fx0_mult_recirc; + assign fx0_ex6_recircd_d = fx0_ex5_recircd_q; + assign fx0_ex7_recircd_d = fx0_ex6_recircd_q; + + + // Valid, not flushed & Target/Source & Type (T1/S1 always GPR) + assign fxu0_t1_d[0] = {(rv_byp_fx0_vld & (~(cp_flush_q)) & {`THREADS{rv_byp_fx0_t1_v & fx0_byp_rdy_nxt_0}}), rv_byp_fx0_t1_t}; + assign fxu0_t2_d[0] = {(rv_byp_fx0_vld & (~(cp_flush_q)) & {`THREADS{rv_byp_fx0_t2_v & fx0_byp_rdy_nxt_0}}), rv_byp_fx0_t2_t}; + assign fxu0_t3_d[0] = {(rv_byp_fx0_vld & (~(cp_flush_q)) & {`THREADS{rv_byp_fx0_t3_v & fx0_byp_rdy_nxt_0}}), rv_byp_fx0_t3_t}; + assign fxu0_s1_d = {(rv_byp_fx0_vld & (~(cp_flush_q))), rv_byp_fx0_s1_t}; + assign fxu0_s2_d = {(rv_byp_fx0_vld & (~(cp_flush_q))), rv_byp_fx0_s2_t}; + assign fxu0_s3_d = {(rv_byp_fx0_vld & (~(cp_flush_q))), rv_byp_fx0_s3_t}; + assign lq_t1_d[0] = {(rv_byp_lq_vld & (~(cp_flush_q)) & {`THREADS{rv_byp_lq_t1_v}}), `gpr_t}; + assign lq_t3_d[0] = {(rv_byp_lq_vld & (~(cp_flush_q)) & {`THREADS{rv_byp_lq_t3_v}}), rv_byp_lq_t3_t}; + assign lq_s1_d = {(rv_byp_lq_vld & (~(cp_flush_q))), rv_byp_lq_s1_t}; + assign lq_s2_d = {(rv_byp_lq_vld & (~(cp_flush_q))), rv_byp_lq_s2_t}; + assign fxu1_t1_d[0] = {(rv_byp_fx1_vld & (~(cp_flush_q)) & {`THREADS{rv_byp_fx1_t1_v & fx1_byp_rdy_nxt_0}}), `gpr_t}; + assign fxu1_t2_d[0] = {(rv_byp_fx1_vld & (~(cp_flush_q)) & {`THREADS{rv_byp_fx1_t2_v & fx1_byp_rdy_nxt_0}}), rv_byp_fx1_t2_t}; + assign fxu1_t3_d[0] = {(rv_byp_fx1_vld & (~(cp_flush_q)) & {`THREADS{rv_byp_fx1_t3_v & fx1_byp_rdy_nxt_0}}), rv_byp_fx1_t3_t}; + assign fxu1_s1_d = {(rv_byp_fx1_vld & (~(cp_flush_q))), rv_byp_fx1_s1_t}; + assign fxu1_s2_d = {(rv_byp_fx1_vld & (~(cp_flush_q))), rv_byp_fx1_s2_t}; + assign fxu1_s3_d = {(rv_byp_fx1_vld & (~(cp_flush_q))), rv_byp_fx1_s3_t}; + + generate + begin : xhdl1 + genvar i; + for (i = 1; i <= 4; i = i + 1) + begin : fxu0_pipe_t_gen + assign fxu0_t1_d[i] = {((fxu0_t1_q[i - 1][0:`THREADS - 1] | fx0_byp_rdy_nxt[i-1]) & (~(cp_flush_q))), fxu0_t1_q[i - 1][`THREADS:elmnt_width - 1]}; + assign fxu0_t2_d[i] = {((fxu0_t2_q[i - 1][0:`THREADS - 1] | fx0_byp_rdy_nxt[i-1]) & (~(cp_flush_q))), fxu0_t2_q[i - 1][`THREADS:elmnt_width - 1]}; + assign fxu0_t3_d[i] = {((fxu0_t3_q[i - 1][0:`THREADS - 1] | fx0_byp_rdy_nxt[i-1]) & (~(cp_flush_q))), fxu0_t3_q[i - 1][`THREADS:elmnt_width - 1]}; + end + end + endgenerate + // Multiplier Recirc + assign fxu0_t1_d[5] = (({((fxu0_t1_q[4][0:`THREADS - 1] | fx0_byp_rdy_nxt[4]) & (~(cp_flush_q))), fxu0_t1_q[4][`THREADS:elmnt_width - 1]}) & ({elmnt_width{~fx0_mult_recirc}})) | + (({((fxu0_t1_q[5][0:`THREADS - 1] | fx0_byp_rdy_nxt[5]) & (~(cp_flush_q))), fxu0_t1_q[5][`THREADS:elmnt_width - 1]}) & ({elmnt_width{fx0_ex5_mult_recirc}})) | + (({((fxu0_t1_q[6][0:`THREADS - 1] | fx0_byp_rdy_nxt[6]) & (~(cp_flush_q))), fxu0_t1_q[6][`THREADS:elmnt_width - 1]}) & ({elmnt_width{fx0_ex6_mult_recirc}})) | + (({((fxu0_t1_q[7][0:`THREADS - 1] | fx0_byp_rdy_nxt[7]) & (~(cp_flush_q))), fxu0_t1_q[7][`THREADS:elmnt_width - 1]}) & ({elmnt_width{fx0_ex7_mult_recirc}})) ; + assign fxu0_t2_d[5] = (({((fxu0_t2_q[4][0:`THREADS - 1] | fx0_byp_rdy_nxt[4]) & (~(cp_flush_q))), fxu0_t2_q[4][`THREADS:elmnt_width - 1]}) & ({elmnt_width{~fx0_mult_recirc}})) | + (({((fxu0_t2_q[5][0:`THREADS - 1] | fx0_byp_rdy_nxt[5]) & (~(cp_flush_q))), fxu0_t2_q[5][`THREADS:elmnt_width - 1]}) & ({elmnt_width{fx0_ex5_mult_recirc}})) | + (({((fxu0_t2_q[6][0:`THREADS - 1] | fx0_byp_rdy_nxt[6]) & (~(cp_flush_q))), fxu0_t2_q[6][`THREADS:elmnt_width - 1]}) & ({elmnt_width{fx0_ex6_mult_recirc}})) | + (({((fxu0_t2_q[7][0:`THREADS - 1] | fx0_byp_rdy_nxt[7]) & (~(cp_flush_q))), fxu0_t2_q[7][`THREADS:elmnt_width - 1]}) & ({elmnt_width{fx0_ex7_mult_recirc}})) ; + assign fxu0_t3_d[5] = (({((fxu0_t3_q[4][0:`THREADS - 1] | fx0_byp_rdy_nxt[4]) & (~(cp_flush_q))), fxu0_t3_q[4][`THREADS:elmnt_width - 1]}) & ({elmnt_width{~fx0_mult_recirc}})) | + (({((fxu0_t3_q[5][0:`THREADS - 1] | fx0_byp_rdy_nxt[5]) & (~(cp_flush_q))), fxu0_t3_q[5][`THREADS:elmnt_width - 1]}) & ({elmnt_width{fx0_ex5_mult_recirc}})) | + (({((fxu0_t3_q[6][0:`THREADS - 1] | fx0_byp_rdy_nxt[6]) & (~(cp_flush_q))), fxu0_t3_q[6][`THREADS:elmnt_width - 1]}) & ({elmnt_width{fx0_ex6_mult_recirc}})) | + (({((fxu0_t3_q[7][0:`THREADS - 1] | fx0_byp_rdy_nxt[7]) & (~(cp_flush_q))), fxu0_t3_q[7][`THREADS:elmnt_width - 1]}) & ({elmnt_width{fx0_ex7_mult_recirc}})) ; + + + generate + begin : xhdla + genvar i; + for (i = 6; i <= 12; i = i + 1) + begin : fxu0_pipe_t_gen + assign fxu0_t1_d[i] = {((fxu0_t1_q[i - 1][0:`THREADS - 1] | fx0_byp_rdy_nxt[i-1]) & (~(cp_flush_q))), fxu0_t1_q[i - 1][`THREADS:elmnt_width - 1]}; + assign fxu0_t2_d[i] = {((fxu0_t2_q[i - 1][0:`THREADS - 1] | fx0_byp_rdy_nxt[i-1]) & (~(cp_flush_q))), fxu0_t2_q[i - 1][`THREADS:elmnt_width - 1]}; + assign fxu0_t3_d[i] = {((fxu0_t3_q[i - 1][0:`THREADS - 1] | fx0_byp_rdy_nxt[i-1]) & (~(cp_flush_q))), fxu0_t3_q[i - 1][`THREADS:elmnt_width - 1]}; + end + end + endgenerate + + generate + begin : xhdl3 + genvar i; + for (i = 1; i <= 8; i = i + 1) + begin : lq_pipe_t_gen + assign lq_t1_d[i] = {(lq_t1_q[i - 1][0:`THREADS - 1] & (~(cp_flush_q))), lq_t1_q[i - 1][`THREADS:elmnt_width - 1]}; + assign lq_t3_d[i] = {(lq_t3_q[i - 1][0:`THREADS - 1] & (~(cp_flush_q))), lq_t3_q[i - 1][`THREADS:elmnt_width - 1]}; + end + end + endgenerate + + generate + begin : xhdl4 + genvar i; + for (i = 1; i <= 7; i = i + 1) + begin : fxu1_pipe_t_gen + assign fxu1_t1_d[i] = {((fxu1_t1_q[i - 1][0:`THREADS - 1] | fx1_byp_rdy_nxt[i-1]) & (~(cp_flush_q))), fxu1_t1_q[i - 1][`THREADS:elmnt_width - 1]}; + assign fxu1_t2_d[i] = {((fxu1_t2_q[i - 1][0:`THREADS - 1] | fx1_byp_rdy_nxt[i-1]) & (~(cp_flush_q))), fxu1_t2_q[i - 1][`THREADS:elmnt_width - 1]}; + assign fxu1_t3_d[i] = {((fxu1_t3_q[i - 1][0:`THREADS - 1] | fx1_byp_rdy_nxt[i-1]) & (~(cp_flush_q))), fxu1_t3_q[i - 1][`THREADS:elmnt_width - 1]}; + end + end + endgenerate + + assign rel_vld_d[0] = (lq_rv_itag2_vld & (~(cp_flush_q))); + assign rel_itag_d[0] = lq_rv_itag2; + generate + begin : xhdl5 + genvar i; + for (i = 1; i <= 3; i = i + 1) + begin : rel_pipe_t_gen + assign rel_vld_d[i] = (rel_vld_q[i - 1] & (~(cp_flush_q))); + assign rel_itag_d[i] = rel_itag_q[i - 1]; + end + end + endgenerate + + //---------------------------------------------------------------------------------------------------------------------------------------- + // FXU0 Compares + //---------------------------------------------------------------------------------------------------------------------------------------- + generate + begin : xhdl6 + genvar i; + for (i = 1; i <= 11; i = i + 1) + begin : comp_fxu0_fxu0 + assign fxu0_s1_fxu0_itag_match[i] = fx0_ex0_s1_itag_q == fx0_itag_q[i]; + assign fxu0_s2_fxu0_itag_match[i] = fx0_ex0_s2_itag_q == fx0_itag_q[i]; + assign fxu0_s3_fxu0_itag_match[i] = fx0_ex0_s3_itag_q == fx0_itag_q[i]; + assign fxu0_s1_fxu0_t1_match[i] = (fxu0_s1_q == fxu0_t1_q[i]) & fxu0_s1_fxu0_itag_match[i]; // Source 1 w/ FXU0 T1 Pipe + assign fxu0_s1_fxu0_t2_match[i] = (fxu0_s1_q == fxu0_t2_q[i]) & fxu0_s1_fxu0_itag_match[i]; // Source 1 w/ FXU0 T2 Pipe + assign fxu0_s1_fxu0_t3_match[i] = (fxu0_s1_q == fxu0_t3_q[i]) & fxu0_s1_fxu0_itag_match[i]; // Source 1 w/ FXU0 T3 Pipe + assign fxu0_s2_fxu0_t1_match[i] = (fxu0_s2_q == fxu0_t1_q[i]) & fxu0_s2_fxu0_itag_match[i]; // Source 2 w/ FXU0 T1 Pipe + assign fxu0_s2_fxu0_t2_match[i] = (fxu0_s2_q == fxu0_t2_q[i]) & fxu0_s2_fxu0_itag_match[i]; // Source 2 w/ FXU0 T2 Pipe + assign fxu0_s2_fxu0_t3_match[i] = (fxu0_s2_q == fxu0_t3_q[i]) & fxu0_s2_fxu0_itag_match[i]; // Source 2 w/ FXU0 T3 Pipe + assign fxu0_s3_fxu0_t1_match[i] = (fxu0_s3_q == fxu0_t1_q[i]) & fxu0_s3_fxu0_itag_match[i]; // Source 3 w/ FXU0 T1 Pipe + assign fxu0_s3_fxu0_t2_match[i] = (fxu0_s3_q == fxu0_t2_q[i]) & fxu0_s3_fxu0_itag_match[i]; // Source 3 w/ FXU0 T2 Pipe + assign fxu0_s3_fxu0_t3_match[i] = (fxu0_s3_q == fxu0_t3_q[i]) & fxu0_s3_fxu0_itag_match[i]; // Source 3 w/ FXU0 T3 Pipe + end + end + endgenerate + + generate + begin : xhd7 + genvar i; + for (i = 4; i <= 8; i = i + 1) + begin : comp_fxu0_lq + assign fxu0_s1_lq_itag_match[i] = fx0_ex0_s1_itag_q == lq_itag_q[i]; + assign fxu0_s2_lq_itag_match[i] = fx0_ex0_s2_itag_q == lq_itag_q[i]; + assign fxu0_s3_lq_itag_match[i] = fx0_ex0_s3_itag_q == lq_itag_q[i]; + assign fxu0_s1_lq_t1_match[i] = (fxu0_s1_q == lq_t1_q[i]) & fxu0_s1_lq_itag_match[i]; // Source 1 w/ LQ T1 Pipe + assign fxu0_s1_lq_t2_match[i] = 1'b0; // Source 1 w/ LQ T2 Pipe + assign fxu0_s1_lq_t3_match[i] = (fxu0_s1_q == lq_t3_q[i]) & fxu0_s1_lq_itag_match[i]; // Source 1 w/ LQ T3 Pipe + assign fxu0_s2_lq_t1_match[i] = (fxu0_s2_q == lq_t1_q[i]) & fxu0_s2_lq_itag_match[i]; // Source 2 w/ LQ T1 Pipe + assign fxu0_s2_lq_t2_match[i] = 1'b0; // Source 2 w/ LQ T2 Pipe + assign fxu0_s2_lq_t3_match[i] = (fxu0_s2_q == lq_t3_q[i]) & fxu0_s2_lq_itag_match[i]; // Source 2 w/ LQ T3 Pipe + assign fxu0_s3_lq_t1_match[i] = (fxu0_s3_q == lq_t1_q[i]) & fxu0_s3_lq_itag_match[i]; // Source 3 w/ LQ T1 Pipe + assign fxu0_s3_lq_t2_match[i] = 1'b0; // Source 3 w/ LQ T2 Pipe + assign fxu0_s3_lq_t3_match[i] = (fxu0_s3_q == lq_t3_q[i]) & fxu0_s3_lq_itag_match[i]; // Source 3 w/ LQ T3 Pipe + end + end + endgenerate + + generate + begin : xhdl8 + genvar i; + for (i = 1; i <= 6 ; i = i + 1) + begin : comp_fxu0_fxu1 + assign fxu0_s1_fxu1_itag_match[i] = fx0_ex0_s1_itag_q == fx1_itag_q[i]; + assign fxu0_s2_fxu1_itag_match[i] = fx0_ex0_s2_itag_q == fx1_itag_q[i]; + assign fxu0_s3_fxu1_itag_match[i] = fx0_ex0_s3_itag_q == fx1_itag_q[i]; + assign fxu0_s1_fxu1_t1_match[i] = (fxu0_s1_q == fxu1_t1_q[i]) & fxu0_s1_fxu1_itag_match[i]; // Source 1 w/ FXU1 T1 Pipe + assign fxu0_s1_fxu1_t2_match[i] = (fxu0_s1_q == fxu1_t2_q[i]) & fxu0_s1_fxu1_itag_match[i]; // Source 1 w/ FXU1 T2 Pipe + assign fxu0_s1_fxu1_t3_match[i] = (fxu0_s1_q == fxu1_t3_q[i]) & fxu0_s1_fxu1_itag_match[i]; // Source 1 w/ FXU1 T3 Pipe + assign fxu0_s2_fxu1_t1_match[i] = (fxu0_s2_q == fxu1_t1_q[i]) & fxu0_s2_fxu1_itag_match[i]; // Source 2 w/ FXU1 T1 Pipe + assign fxu0_s2_fxu1_t2_match[i] = (fxu0_s2_q == fxu1_t2_q[i]) & fxu0_s2_fxu1_itag_match[i]; // Source 2 w/ FXU1 T2 Pipe + assign fxu0_s2_fxu1_t3_match[i] = (fxu0_s2_q == fxu1_t3_q[i]) & fxu0_s2_fxu1_itag_match[i]; // Source 2 w/ FXU1 T3 Pipe + assign fxu0_s3_fxu1_t1_match[i] = (fxu0_s3_q == fxu1_t1_q[i]) & fxu0_s3_fxu1_itag_match[i]; // Source 3 w/ FXU1 T1 Pipe + assign fxu0_s3_fxu1_t2_match[i] = (fxu0_s3_q == fxu1_t2_q[i]) & fxu0_s3_fxu1_itag_match[i]; // Source 3 w/ FXU1 T2 Pipe + assign fxu0_s3_fxu1_t3_match[i] = (fxu0_s3_q == fxu1_t3_q[i]) & fxu0_s3_fxu1_itag_match[i]; // Source 3 w/ FXU1 T3 Pipe + end + end + endgenerate + + generate + begin : xhdl9 + genvar i; + for (i = 2; i <= 3; i = i + 1) + begin : comp_fxu0_rel + assign fxu0_s1_rel_itag_match[i] = fx0_ex0_s1_itag_q == rel_itag_q[i]; + assign fxu0_s2_rel_itag_match[i] = fx0_ex0_s2_itag_q == rel_itag_q[i]; + assign fxu0_s3_rel_itag_match[i] = fx0_ex0_s3_itag_q == rel_itag_q[i]; + assign fxu0_s1_rel_match[i] = (fxu0_s1_q == ({rel_vld_q[i], `gpr_t})) & fxu0_s1_rel_itag_match[i]; // Source 1 w/ rel T1 Pipe + assign fxu0_s2_rel_match[i] = (fxu0_s2_q == ({rel_vld_q[i], `gpr_t})) & fxu0_s2_rel_itag_match[i]; // Source 1 w/ rel T1 Pipe + assign fxu0_s3_rel_match[i] = (fxu0_s3_q == ({rel_vld_q[i], `gpr_t})) & fxu0_s3_rel_itag_match[i]; // Source 1 w/ rel T1 Pipe + end + end + endgenerate + + //---------------------------------------------------------------------------------------------------------------------------------------- + // Assign Outputs to FXU0 - Fastest back2back is 1->6 (4 bubbles) + //----------------------------------------------------------------------------------------------------------------------------------------. + assign fx0_ex0_s1_fx0_sel[1:11] = fxu0_s1_fxu0_t1_match | fxu0_s1_fxu0_t2_match | fxu0_s1_fxu0_t3_match; + assign fx0_ex0_s2_fx0_sel[1:11] = fxu0_s2_fxu0_t1_match | fxu0_s2_fxu0_t2_match | fxu0_s2_fxu0_t3_match; + assign fx0_ex0_s3_fx0_sel[1:11] = fxu0_s3_fxu0_t1_match | fxu0_s3_fxu0_t2_match | fxu0_s3_fxu0_t3_match; + rv_pri #(.size(11)) fx0_s1_fx0 (.cond(fx0_ex0_s1_fx0_sel), .pri(rv_fx0_ex0_s1_fx0_sel)); + rv_pri #(.size(11)) fx0_s2_fx0 (.cond(fx0_ex0_s2_fx0_sel), .pri(rv_fx0_ex0_s2_fx0_sel)); + rv_pri #(.size(11)) fx0_s3_fx0 (.cond(fx0_ex0_s3_fx0_sel), .pri(rv_fx0_ex0_s3_fx0_sel)); + + // No pri necessary for 4:8 + assign rv_fx0_ex0_s1_lq_sel[4:8] = fxu0_s1_lq_t1_match | fxu0_s1_lq_t2_match | fxu0_s1_lq_t3_match; + assign rv_fx0_ex0_s2_lq_sel[4:8] = fxu0_s2_lq_t1_match | fxu0_s2_lq_t2_match | fxu0_s2_lq_t3_match; + assign rv_fx0_ex0_s3_lq_sel[4:8] = fxu0_s3_lq_t1_match | fxu0_s3_lq_t2_match | fxu0_s3_lq_t3_match; + + assign fx0_ex0_s1_fx1_sel[1:6] = fxu0_s1_fxu1_t1_match | fxu0_s1_fxu1_t2_match | fxu0_s1_fxu1_t3_match; + assign fx0_ex0_s2_fx1_sel[1:6] = fxu0_s2_fxu1_t1_match | fxu0_s2_fxu1_t2_match | fxu0_s2_fxu1_t3_match; + assign fx0_ex0_s3_fx1_sel[1:6] = fxu0_s3_fxu1_t1_match | fxu0_s3_fxu1_t2_match | fxu0_s3_fxu1_t3_match; + assign rv_fx0_ex0_s1_fx1_sel[1:5] = fx0_ex0_s1_fx1_sel[1:5]; + assign rv_fx0_ex0_s2_fx1_sel[1:5] = fx0_ex0_s2_fx1_sel[1:5]; + assign rv_fx0_ex0_s3_fx1_sel[1:5] = fx0_ex0_s3_fx1_sel[1:5]; + assign rv_fx0_ex0_s1_fx1_sel[6] = fx0_ex0_s1_fx1_sel[6] & ~fx0_ex0_s1_fx1_sel[1]; + assign rv_fx0_ex0_s2_fx1_sel[6] = fx0_ex0_s2_fx1_sel[6] & ~fx0_ex0_s2_fx1_sel[1]; + assign rv_fx0_ex0_s3_fx1_sel[6] = fx0_ex0_s3_fx1_sel[6] & ~fx0_ex0_s3_fx1_sel[1]; + + assign rv_fx0_ex0_s1_rel_sel[2:3] = fxu0_s1_rel_match; + assign rv_fx0_ex0_s2_rel_sel[2:3] = fxu0_s2_rel_match; + assign rv_fx0_ex0_s3_rel_sel[2:3] = fxu0_s3_rel_match; + + //---------------------------------------------------------------------------------------------------------------------------------------- + // LQ Compares + //---------------------------------------------------------------------------------------------------------------------------------------- + generate + begin : xhdl10 + genvar i; + for (i = 2; i <= 12; i = i + 1) + begin : comp_lq_fxu0 + assign lq_s1_fxu0_itag_match[i] = rv_byp_lq_ex0_s1_itag == fx0_itag_q[i]; + assign lq_s2_fxu0_itag_match[i] = rv_byp_lq_ex0_s2_itag == fx0_itag_q[i]; + assign lq_s1_fxu0_t1_match[i] = (lq_s1_q == fxu0_t1_q[i]) & lq_s1_fxu0_itag_match[i]; // Source 1 w/ FXU0 T1 Pipe + assign lq_s1_fxu0_t2_match[i] = (lq_s1_q == fxu0_t2_q[i]) & lq_s1_fxu0_itag_match[i]; // Source 1 w/ FXU0 T2 Pipe + assign lq_s1_fxu0_t3_match[i] = (lq_s1_q == fxu0_t3_q[i]) & lq_s1_fxu0_itag_match[i]; // Source 1 w/ FXU0 T3 Pipe + assign lq_s2_fxu0_t1_match[i] = (lq_s2_q == fxu0_t1_q[i]) & lq_s2_fxu0_itag_match[i]; // Source 2 w/ FXU0 T1 Pipe + assign lq_s2_fxu0_t2_match[i] = (lq_s2_q == fxu0_t2_q[i]) & lq_s2_fxu0_itag_match[i]; // Source 2 w/ FXU0 T2 Pipe + assign lq_s2_fxu0_t3_match[i] = (lq_s2_q == fxu0_t3_q[i]) & lq_s2_fxu0_itag_match[i]; // Source 2 w/ FXU0 T3 Pipe + end + end + endgenerate + + generate + begin : xhdl11 + genvar i; + for (i = 4; i <= 8; i = i + 1) + begin : comp_lq_lq + assign lq_s1_lq_itag_match[i] = rv_byp_lq_ex0_s1_itag == lq_itag_q[i]; + assign lq_s2_lq_itag_match[i] = rv_byp_lq_ex0_s2_itag == lq_itag_q[i]; + assign lq_s1_lq_t1_match[i] = (lq_s1_q == lq_t1_q[i]) & lq_s1_lq_itag_match[i]; // Source 1 w/ LQ T1 Pipe + assign lq_s1_lq_t2_match[i] = 1'b0; // Source 1 w/ LQ T2 Pipe + assign lq_s1_lq_t3_match[i] = (lq_s1_q == lq_t3_q[i]) & lq_s1_lq_itag_match[i]; // Source 1 w/ LQ T3 Pipe + assign lq_s2_lq_t1_match[i] = (lq_s2_q == lq_t1_q[i]) & lq_s2_lq_itag_match[i]; // Source 2 w/ LQ T1 Pipe + assign lq_s2_lq_t2_match[i] = 1'b0; // Source 2 w/ LQ T2 Pipe + assign lq_s2_lq_t3_match[i] = (lq_s2_q == lq_t3_q[i]) & lq_s2_lq_itag_match[i]; // Source 2 w/ LQ T3 Pipe + end + end + endgenerate + + generate + begin : xhdl12 + genvar i; + for (i = 2; i <= 7; i = i + 1) + begin : comp_lq_fxu1 + assign lq_s1_fxu1_itag_match[i] = rv_byp_lq_ex0_s1_itag == fx1_itag_q[i]; + assign lq_s2_fxu1_itag_match[i] = rv_byp_lq_ex0_s2_itag == fx1_itag_q[i]; + assign lq_s1_fxu1_t1_match[i] = (lq_s1_q == fxu1_t1_q[i]) & lq_s1_fxu1_itag_match[i]; // Source 1 w/ FXU1 T1 Pipe + assign lq_s1_fxu1_t2_match[i] = (lq_s1_q == fxu1_t2_q[i]) & lq_s1_fxu1_itag_match[i]; // Source 1 w/ FXU1 T2 Pipe + assign lq_s1_fxu1_t3_match[i] = (lq_s1_q == fxu1_t3_q[i]) & lq_s1_fxu1_itag_match[i]; // Source 1 w/ FXU1 T3 Pipe + assign lq_s2_fxu1_t1_match[i] = (lq_s2_q == fxu1_t1_q[i]) & lq_s2_fxu1_itag_match[i]; // Source 2 w/ FXU1 T1 Pipe + assign lq_s2_fxu1_t2_match[i] = (lq_s2_q == fxu1_t2_q[i]) & lq_s2_fxu1_itag_match[i]; // Source 2 w/ FXU1 T2 Pipe + assign lq_s2_fxu1_t3_match[i] = (lq_s2_q == fxu1_t3_q[i]) & lq_s2_fxu1_itag_match[i]; // Source 2 w/ FXU1 T3 Pipe + end + end + endgenerate + + generate + begin : xhdl13 + genvar i; + for (i = 2; i <= 3 ; i = i + 1) + begin : comp_lq_rel + assign lq_s1_rel_itag_match[i] = rv_byp_lq_ex0_s1_itag == rel_itag_q[i]; + assign lq_s2_rel_itag_match[i] = rv_byp_lq_ex0_s2_itag == rel_itag_q[i]; + assign lq_s1_rel_match[i] = (lq_s1_q == ({rel_vld_q[i], `gpr_t})) & lq_s1_rel_itag_match[i]; // Source 1 w/ rel T1 Pipe + assign lq_s2_rel_match[i] = (lq_s2_q == ({rel_vld_q[i], `gpr_t})) & lq_s2_rel_itag_match[i]; // Source 1 w/ rel T1 Pipe + end + end + endgenerate + + //---------------------------------------------------------------------------------------------------------------------------------------- + // Assign Outputs to LQ -- Remove last bit, that is for write-back case + //----------------------------------------------------------------------------------------------------------------------------------------. + assign lq_ex0_s1_fx0_sel[2:12] = lq_s1_fxu0_t1_match | lq_s1_fxu0_t2_match | lq_s1_fxu0_t3_match; + assign lq_ex0_s2_fx0_sel[2:12] = lq_s2_fxu0_t1_match | lq_s2_fxu0_t2_match | lq_s2_fxu0_t3_match; + rv_pri #(.size(11)) lq_s1_fx0 (.cond(lq_ex0_s1_fx0_sel), .pri(rv_lq_ex0_s1_fx0_sel)); + rv_pri #(.size(11)) lq_s2_fx0 (.cond(lq_ex0_s2_fx0_sel), .pri(rv_lq_ex0_s2_fx0_sel)); + + assign rv_lq_ex0_s1_lq_sel[4:8] = lq_s1_lq_t1_match | lq_s1_lq_t2_match | lq_s1_lq_t3_match; + assign rv_lq_ex0_s2_lq_sel[4:8] = lq_s2_lq_t1_match | lq_s2_lq_t2_match | lq_s2_lq_t3_match; + + assign lq_ex0_s1_fx1_sel[2:7] = lq_s1_fxu1_t1_match | lq_s1_fxu1_t2_match | lq_s1_fxu1_t3_match; + assign lq_ex0_s2_fx1_sel[2:7] = lq_s2_fxu1_t1_match | lq_s2_fxu1_t2_match | lq_s2_fxu1_t3_match; + assign rv_lq_ex0_s1_fx1_sel[2:6] = lq_ex0_s1_fx1_sel[2:6]; + assign rv_lq_ex0_s2_fx1_sel[2:6] = lq_ex0_s2_fx1_sel[2:6]; + assign rv_lq_ex0_s1_fx1_sel[7] = lq_ex0_s1_fx1_sel[7] & ~lq_ex0_s1_fx1_sel[2]; + assign rv_lq_ex0_s2_fx1_sel[7] = lq_ex0_s2_fx1_sel[7] & ~lq_ex0_s2_fx1_sel[2]; + + assign rv_lq_ex0_s1_rel_sel[2:3] = lq_s1_rel_match; + assign rv_lq_ex0_s2_rel_sel[2:3] = lq_s2_rel_match; + + //---------------------------------------------------------------------------------------------------------------------------------------- + // BR Compares + //---------------------------------------------------------------------------------------------------------------------------------------- + //---------------------------------------------------------------------------------------------------------------------------------------- + // Assign Outputs to BR -- Remove last bit, that is for write-back case + //----------------------------------------------------------------------------------------------------------------------------------------. + + //---------------------------------------------------------------------------------------------------------------------------------------- + // FXU1 Compares + //---------------------------------------------------------------------------------------------------------------------------------------- + generate + begin : xhdl14 + genvar i; + for (i = 1; i <= 11; i = i + 1) + begin : comp_fxu1_fxu0 + assign fxu1_s1_fxu0_itag_match[i] = fx1_ex0_s1_itag_q == fx0_itag_q[i]; + assign fxu1_s2_fxu0_itag_match[i] = fx1_ex0_s2_itag_q == fx0_itag_q[i]; + assign fxu1_s3_fxu0_itag_match[i] = fx1_ex0_s3_itag_q == fx0_itag_q[i]; + assign fxu1_s1_fxu0_t1_match[i] = (fxu1_s1_q == fxu0_t1_q[i]) & fxu1_s1_fxu0_itag_match[i]; // Source 1 w/ FXU0 T1 Pipe + assign fxu1_s1_fxu0_t2_match[i] = (fxu1_s1_q == fxu0_t2_q[i]) & fxu1_s1_fxu0_itag_match[i]; // Source 1 w/ FXU0 T2 Pipe + assign fxu1_s1_fxu0_t3_match[i] = (fxu1_s1_q == fxu0_t3_q[i]) & fxu1_s1_fxu0_itag_match[i]; // Source 1 w/ FXU0 T3 Pipe + assign fxu1_s2_fxu0_t1_match[i] = (fxu1_s2_q == fxu0_t1_q[i]) & fxu1_s2_fxu0_itag_match[i]; // Source 2 w/ FXU0 T1 Pipe + assign fxu1_s2_fxu0_t2_match[i] = (fxu1_s2_q == fxu0_t2_q[i]) & fxu1_s2_fxu0_itag_match[i]; // Source 2 w/ FXU0 T2 Pipe + assign fxu1_s2_fxu0_t3_match[i] = (fxu1_s2_q == fxu0_t3_q[i]) & fxu1_s2_fxu0_itag_match[i]; // Source 2 w/ FXU0 T3 Pipe + assign fxu1_s3_fxu0_t1_match[i] = (fxu1_s3_q == fxu0_t1_q[i]) & fxu1_s3_fxu0_itag_match[i]; // Source 3 w/ FXU0 T1 Pipe + assign fxu1_s3_fxu0_t2_match[i] = (fxu1_s3_q == fxu0_t2_q[i]) & fxu1_s3_fxu0_itag_match[i]; // Source 3 w/ FXU0 T2 Pipe + assign fxu1_s3_fxu0_t3_match[i] = (fxu1_s3_q == fxu0_t3_q[i]) & fxu1_s3_fxu0_itag_match[i]; // Source 3 w/ FXU0 T3 Pipe + end + end + endgenerate + + generate + begin : xhdl15 + genvar i; + for (i = 4; i <= 8; i = i + 1) + begin : comp_fxu1_lq + assign fxu1_s1_lq_itag_match[i] = fx1_ex0_s1_itag_q == lq_itag_q[i]; + assign fxu1_s2_lq_itag_match[i] = fx1_ex0_s2_itag_q == lq_itag_q[i]; + assign fxu1_s3_lq_itag_match[i] = fx1_ex0_s3_itag_q == lq_itag_q[i]; + assign fxu1_s1_lq_t1_match[i] = (fxu1_s1_q == lq_t1_q[i]) & fxu1_s1_lq_itag_match[i]; // Source 1 w/ LQ T1 Pipe + assign fxu1_s1_lq_t2_match[i] = 1'b0; // Source 1 w/ LQ T2 Pipe + assign fxu1_s1_lq_t3_match[i] = (fxu1_s1_q == lq_t3_q[i]) & fxu1_s1_lq_itag_match[i]; // Source 1 w/ LQ T3 Pipe + assign fxu1_s2_lq_t1_match[i] = (fxu1_s2_q == lq_t1_q[i]) & fxu1_s2_lq_itag_match[i]; // Source 2 w/ LQ T1 Pipe + assign fxu1_s2_lq_t2_match[i] = 1'b0; // Source 2 w/ LQ T2 pipe + assign fxu1_s2_lq_t3_match[i] = (fxu1_s2_q == lq_t3_q[i]) & fxu1_s2_lq_itag_match[i]; // Source 2 w/ LQ T3 Pipe + assign fxu1_s3_lq_t1_match[i] = (fxu1_s3_q == lq_t1_q[i]) & fxu1_s3_lq_itag_match[i]; // Source 3 w/ LQ T1 Pipe + assign fxu1_s3_lq_t2_match[i] = 1'b0; // Source 3 w/ LQ T2 Pipe + assign fxu1_s3_lq_t3_match[i] = (fxu1_s3_q == lq_t3_q[i]) & fxu1_s3_lq_itag_match[i]; // Source 3 w/ LQ T3 Pipe + end + end + endgenerate + + generate + begin : xhdl16 + genvar i; + for (i = 1; i <= 6; i = i + 1) + begin : comp_fxu1_fxu1 + assign fxu1_s1_fxu1_itag_match[i] = fx1_ex0_s1_itag_q == fx1_itag_q[i]; + assign fxu1_s2_fxu1_itag_match[i] = fx1_ex0_s2_itag_q == fx1_itag_q[i]; + assign fxu1_s3_fxu1_itag_match[i] = fx1_ex0_s3_itag_q == fx1_itag_q[i]; + assign fxu1_s1_fxu1_t1_match[i] = (fxu1_s1_q == fxu1_t1_q[i]) & fxu1_s1_fxu1_itag_match[i]; // Source 1 w/ FXU1 T1 Pipe + assign fxu1_s1_fxu1_t2_match[i] = (fxu1_s1_q == fxu1_t2_q[i]) & fxu1_s1_fxu1_itag_match[i]; // Source 1 w/ FXU1 T2 Pipe + assign fxu1_s1_fxu1_t3_match[i] = (fxu1_s1_q == fxu1_t3_q[i]) & fxu1_s1_fxu1_itag_match[i]; // Source 1 w/ FXU1 T3 Pipe + assign fxu1_s2_fxu1_t1_match[i] = (fxu1_s2_q == fxu1_t1_q[i]) & fxu1_s2_fxu1_itag_match[i]; // Source 2 w/ FXU1 T1 Pipe + assign fxu1_s2_fxu1_t2_match[i] = (fxu1_s2_q == fxu1_t2_q[i]) & fxu1_s2_fxu1_itag_match[i]; // Source 2 w/ FXU1 T2 Pipe + assign fxu1_s2_fxu1_t3_match[i] = (fxu1_s2_q == fxu1_t3_q[i]) & fxu1_s2_fxu1_itag_match[i]; // Source 2 w/ FXU1 T3 Pipe + assign fxu1_s3_fxu1_t1_match[i] = (fxu1_s3_q == fxu1_t1_q[i]) & fxu1_s3_fxu1_itag_match[i]; // Source 3 w/ FXU1 T1 Pipe + assign fxu1_s3_fxu1_t2_match[i] = (fxu1_s3_q == fxu1_t2_q[i]) & fxu1_s3_fxu1_itag_match[i]; // Source 3 w/ FXU1 T2 Pipe + assign fxu1_s3_fxu1_t3_match[i] = (fxu1_s3_q == fxu1_t3_q[i]) & fxu1_s3_fxu1_itag_match[i]; // Source 3 w/ FXU1 T3 Pipe + end + end + endgenerate + + generate + begin : xhdl17 + genvar i; + for (i = 2; i <= 3 ; i = i + 1) + begin : comp_fxu1_rel + assign fxu1_s1_rel_itag_match[i] = fx1_ex0_s1_itag_q == rel_itag_q[i]; + assign fxu1_s2_rel_itag_match[i] = fx1_ex0_s2_itag_q == rel_itag_q[i]; + assign fxu1_s3_rel_itag_match[i] = fx1_ex0_s3_itag_q == rel_itag_q[i]; + assign fxu1_s1_rel_match[i] = (fxu1_s1_q == ({rel_vld_q[i], `gpr_t})) & fxu1_s1_rel_itag_match[i]; // Source 1 w/ rel T1 Pipe + assign fxu1_s2_rel_match[i] = (fxu1_s2_q == ({rel_vld_q[i], `gpr_t})) & fxu1_s2_rel_itag_match[i]; // Source 1 w/ rel T1 Pipe + assign fxu1_s3_rel_match[i] = (fxu1_s3_q == ({rel_vld_q[i], `gpr_t})) & fxu1_s3_rel_itag_match[i]; // Source 1 w/ rel T1 Pipe + end + end + endgenerate + + //---------------------------------------------------------------------------------------------------------------------------------------- + // Assign Outputs to FXU1 -- Remove last bit, that is for write-back case + //----------------------------------------------------------------------------------------------------------------------------------------. + assign fx1_ex0_s1_fx0_sel[1:11] = fxu1_s1_fxu0_t1_match | fxu1_s1_fxu0_t2_match | fxu1_s1_fxu0_t3_match; + assign fx1_ex0_s2_fx0_sel[1:11] = fxu1_s2_fxu0_t1_match | fxu1_s2_fxu0_t2_match | fxu1_s2_fxu0_t3_match; + assign fx1_ex0_s3_fx0_sel[1:11] = fxu1_s3_fxu0_t1_match | fxu1_s3_fxu0_t2_match | fxu1_s3_fxu0_t3_match; + rv_pri #(.size(11)) fx1_s1_fx0 (.cond(fx1_ex0_s1_fx0_sel), .pri(rv_fx1_ex0_s1_fx0_sel)); + rv_pri #(.size(11)) fx1_s2_fx0 (.cond(fx1_ex0_s2_fx0_sel), .pri(rv_fx1_ex0_s2_fx0_sel)); + rv_pri #(.size(11)) fx1_s3_fx0 (.cond(fx1_ex0_s3_fx0_sel), .pri(rv_fx1_ex0_s3_fx0_sel)); + + assign rv_fx1_ex0_s1_lq_sel[4:8] = fxu1_s1_lq_t1_match | fxu1_s1_lq_t2_match | fxu1_s1_lq_t3_match; + assign rv_fx1_ex0_s2_lq_sel[4:8] = fxu1_s2_lq_t1_match | fxu1_s2_lq_t2_match | fxu1_s2_lq_t3_match; + assign rv_fx1_ex0_s3_lq_sel[4:8] = fxu1_s3_lq_t1_match | fxu1_s3_lq_t2_match | fxu1_s3_lq_t3_match; + + assign fx1_ex0_s1_fx1_sel[1:6] = fxu1_s1_fxu1_t1_match | fxu1_s1_fxu1_t2_match | fxu1_s1_fxu1_t3_match; + assign fx1_ex0_s2_fx1_sel[1:6] = fxu1_s2_fxu1_t1_match | fxu1_s2_fxu1_t2_match | fxu1_s2_fxu1_t3_match; + assign fx1_ex0_s3_fx1_sel[1:6] = fxu1_s3_fxu1_t1_match | fxu1_s3_fxu1_t2_match | fxu1_s3_fxu1_t3_match; + assign rv_fx1_ex0_s1_fx1_sel[1:5] = fx1_ex0_s1_fx1_sel[1:5]; + assign rv_fx1_ex0_s2_fx1_sel[1:5] = fx1_ex0_s2_fx1_sel[1:5]; + assign rv_fx1_ex0_s3_fx1_sel[1:5] = fx1_ex0_s3_fx1_sel[1:5]; + assign rv_fx1_ex0_s1_fx1_sel[6] = fx1_ex0_s1_fx1_sel[6] & ~fx1_ex0_s1_fx1_sel[1]; + assign rv_fx1_ex0_s2_fx1_sel[6] = fx1_ex0_s2_fx1_sel[6] & ~fx1_ex0_s2_fx1_sel[1]; + assign rv_fx1_ex0_s3_fx1_sel[6] = fx1_ex0_s3_fx1_sel[6] & ~fx1_ex0_s3_fx1_sel[1]; + + assign rv_fx1_ex0_s1_rel_sel = fxu1_s1_rel_match; + assign rv_fx1_ex0_s2_rel_sel = fxu1_s2_rel_match; + assign rv_fx1_ex0_s3_rel_sel = fxu1_s3_rel_match; + + //---------------------------------------------------------------------------------------------------------------------------------------- + // FX0 RV Release, based on ilat + //---------------------------------------------------------------------------------------------------------------------------------------- + assign fx0_ex2_abort = (fx0_rv_ex2_s1_abort | fx0_rv_ex2_s2_abort | fx0_rv_ex2_s3_abort) & |(fx0_vld_q[2]) ; + + assign fx0_act[0] = |(rv_byp_fx0_vld); + assign fx0_act[1] = |(fx0_vld_q[0]); + assign fx0_act[2] = |(fx0_vld_q[1]); + assign fx0_act[3] = |(fx0_vld_q[2]) | fx0_insert_ord; + assign fx0_act[4] = |(fx0_vld_q[3]); + assign fx0_act[5] = |(fx0_vld_q[4]) | fx0_mult_recirc; + assign fx0_act[6] = |(fx0_vld_q[5]); + assign fx0_act[7] = |(fx0_vld_q[6]); + assign fx0_act[8] = |(fx0_vld_q[7]); + assign fx0_act[9] = |(fx0_vld_q[8]); + assign fx0_act[10] = |(fx0_vld_q[9]); + assign fx0_act[11] = |(fx0_vld_q[10]); + assign fx0_act[12] = |(fx0_vld_q[11]); + + assign fx0_vld_d[0] = rv_byp_fx0_vld & (~(cp_flush_q)); + assign fx0_vld_d[1] = fx0_vld_q[0] & (~cp_flush_q); + assign fx0_vld_d[2] = fx0_vld_q[1] & (~cp_flush_q); + assign fx0_vld_d[3] = (fx0_vld_q[2] | ({`THREADS{fx0_insert_ord}} & fx0_rv_ord_tid)) & (~cp_flush_q); + assign fx0_vld_d[4] = fx0_vld_q[3] & (~cp_flush_q); + assign fx0_vld_d[5] = ((fx0_vld_q[4] & {`THREADS{~fx0_mult_recirc}}) | + (fx0_vld_q[5] & {`THREADS{fx0_ex5_mult_recirc}}) | + (fx0_vld_q[6] & {`THREADS{fx0_ex6_mult_recirc}}) | + (fx0_vld_q[7] & {`THREADS{fx0_ex7_mult_recirc}}) ) & (~cp_flush_q); + assign fx0_vld_d[6] = fx0_vld_q[5] & (~cp_flush_q); + assign fx0_vld_d[7] = fx0_vld_q[6] & (~cp_flush_q); + assign fx0_vld_d[8] = fx0_vld_q[7] & (~cp_flush_q); + assign fx0_vld_d[9] = fx0_vld_q[8] & (~cp_flush_q); + assign fx0_vld_d[10] = fx0_vld_q[9] & (~cp_flush_q); + assign fx0_vld_d[11] = fx0_vld_q[10] & (~cp_flush_q); + + assign fx0_is_brick_d[1] = rv_byp_fx0_ex0_is_brick; + assign fx0_is_brick_d[2] = fx0_is_brick_q[1]; + assign fx0_is_brick_d[3] = fx0_is_brick_q[2]; + assign fx0_is_brick_d[4] = fx0_is_brick_q[3]; + assign fx0_is_brick_d[5] = fx0_is_brick_q[4]; + assign fx0_is_brick_d[6] = fx0_is_brick_q[5]; + assign fx0_is_brick_d[7] = fx0_is_brick_q[6]; + + + assign fx0_abort_d[3] = fx0_ex2_abort; + assign fx0_abort_d[4] = fx0_abort_q[3]; + + // Itag Pipe + assign fx0_itag_d[0] = rv_byp_fx0_itag; + assign fx0_itag_d[1] = fx0_itag_q[0]; + assign fx0_itag_d[2] = fx0_itag_q[1]; + assign fx0_itag_d[3] = (fx0_itag_q[2] & {`ITAG_SIZE_ENC{(~fx0_insert_ord)}}) | (fx0_rv_ord_itag & {`ITAG_SIZE_ENC{fx0_insert_ord}}); + assign fx0_itag_d[4] = fx0_itag_q[3]; + assign fx0_itag_d[5] = (fx0_itag_q[4] & {`ITAG_SIZE_ENC{(~fx0_mult_recirc)}}) | + (fx0_itag_q[5] & {`ITAG_SIZE_ENC{( fx0_ex5_mult_recirc)}}) | + (fx0_itag_q[6] & {`ITAG_SIZE_ENC{( fx0_ex6_mult_recirc)}}) | + (fx0_itag_q[7] & {`ITAG_SIZE_ENC{( fx0_ex7_mult_recirc)}}) ; + + generate + begin : xhdl18i + genvar i; + for (i = 6; i <= 12; i = i + 1) + begin : fxu0_itag_d_gen + assign fx0_itag_d[i] = fx0_itag_q[i-1]; + end + end + endgenerate + + // Ilat Pipe + assign fx0_ex0_ilat_d = rv_byp_fx0_ilat; + assign fx0_ex1_ilat_d = fx0_ex0_ilat_q; + assign fx0_ex2_ilat_d = fx0_ex1_ilat_q ; + assign fx0_ex3_ilat_d = fx0_ex2_ilat_q & {4{(~fx0_insert_ord)}}; + assign fx0_ex4_ilat_d = fx0_ex3_ilat_q & ~{4{fx0_ex3_ord_flush_q & (fx0_ex3_ilat_q != 4'b1111)}}; //If ordered was aborted, release asap (unless it is ilat F) + assign fx0_ex5_ilat_d = fx0_ex4_ilat_q; + assign fx0_ex6_ilat_d = fx0_ex5_ilat_q; + assign fx0_ex7_ilat_d = fx0_ex6_ilat_q; + assign fx0_ex8_ilat_d = fx0_ex7_ilat_q; + + // Match instruction latency with their location in the pipeline + assign fx0_rv1_ilat_match = |(rv_byp_fx0_ilat0_vld | rv_byp_fx0_ilat1_vld); //ilat 0 or 1 + + assign fx0_ex0_fast_match = ((fx0_ex0_ilat_q <= 4'b0010)); + assign fx0_ex0_ilat_match = ((fx0_ex0_ilat_q <= 4'b0011)); + assign fx0_ex1_ilat_match = ((fx0_ex1_ilat_q <= 4'b0100)); + assign fx0_ex2_ilat_match = (fx0_ex2_ilat_q <= 4'b0101); + assign fx0_ex3_ilat_match = (fx0_ex3_ilat_q <= 4'b0110) | (fx0_ex3_ord_flush_q & (fx0_ex3_ilat_q != 4'b1111)); + + assign fx0_ex4_ilat_match = (fx0_ex4_ilat_q <= 4'b0111); + + //Store data can't be bypassed (updates) + assign fx0_ex0_stq_pipe_val = 1'b0; + + // Intructions are in correct pipeline stage to allow dependent op release, and they have not been released yet + assign fx0_ex0_sched_rel[9] = (fx0_ex0_ilat_match & fx0_need_rel_q[0] & (~(fx0_sched_rel_ex0_fast | fx0_ex0_stq_pipe_val)) & (~|(fx0_vld_q[0] & cp_flush_q))); + assign fx0_ex0_sched_rel[8] = fx0_ex1_ilat_match & fx0_need_rel_q[1] & ~|(fx0_vld_q[1] & cp_flush_q); + assign fx0_ex0_sched_rel[7] = fx0_ex2_ilat_match & fx0_need_rel_q[2] & ~|(fx0_vld_q[2] & cp_flush_q); + assign fx0_ex0_sched_rel[6] = fx0_ex3_ilat_match & fx0_need_rel_q[3] & ~|(fx0_vld_q[3] & cp_flush_q); + assign fx0_ex0_sched_rel[5] = fx0_ex4_ilat_match & fx0_need_rel_q[4] & ~|(fx0_vld_q[4] & cp_flush_q); //need this case to kill ord rel when cmplt same cycle as flush + assign fx0_ex0_sched_rel[4] = 1'b0; + assign fx0_ex0_sched_rel[3] = 1'b0; + assign fx0_ex0_sched_rel[2] = 1'b0; + assign fx0_ex0_sched_rel[1] = 1'b0; + assign fx0_ex0_sched_rel[0] = 1'b0; + + + assign fx0_byp_rdy_nxt_0 = |rv_byp_fx0_ilat0_vld ; + assign fx0_byp_rdy_nxt[0] = {`THREADS{ (fx0_ex0_ilat_q == 4'b0001) }} & fx0_vld_q[0]; + assign fx0_byp_rdy_nxt[1] = {`THREADS{ (fx0_ex1_ilat_q == 4'b0010) }} & fx0_vld_q[1]; + assign fx0_byp_rdy_nxt[2] = {`THREADS{ (fx0_ex2_ilat_q == 4'b0011) }} & fx0_vld_q[2]; + assign fx0_byp_rdy_nxt[3] = {`THREADS{ (fx0_ex3_ilat_q == 4'b0100) }} & fx0_vld_q[3]; + assign fx0_byp_rdy_nxt[4] = {`THREADS{ (fx0_ex4_ilat_q == 4'b0101) }} & fx0_vld_q[4]; + assign fx0_byp_rdy_nxt[5] = {`THREADS{ (fx0_ex5_ilat_q == 4'b0110) }} & fx0_vld_q[5]; + assign fx0_byp_rdy_nxt[6] = {`THREADS{ (fx0_ex6_ilat_q == 4'b0111) }} & fx0_vld_q[6]; + assign fx0_byp_rdy_nxt[7] = {`THREADS{ (fx0_ex7_ilat_q == 4'b1000) }} & fx0_vld_q[7]; + assign fx0_byp_rdy_nxt[8] = {`THREADS{ (fx0_ex8_ilat_q == 4'b1001) }} & fx0_vld_q[8]; + assign fx0_byp_rdy_nxt[9] = {`THREADS{ 1'b0}}; + assign fx0_byp_rdy_nxt[10] = {`THREADS{1'b0}}; + assign fx0_byp_rdy_nxt[11] = {`THREADS{1'b0}}; + + + // Prioritize. EX6 gets highest priority (Will be latched) + + rv_pri #(.size(10)) fx0_release_pri( + .cond(fx0_ex0_sched_rel), + .pri(fx0_ex0_sched_rel_pri) + ); + + // Use prioritized schedule to determine which stage to release itag/vld out of (Will be latched) + assign fx0_rel_itag_d = + (fx0_itag_q[4] & {`ITAG_SIZE_ENC{fx0_ex0_sched_rel_pri[5]}}) | + (fx0_itag_q[3] & {`ITAG_SIZE_ENC{fx0_ex0_sched_rel_pri[6]}}) | + (fx0_itag_q[2] & {`ITAG_SIZE_ENC{fx0_ex0_sched_rel_pri[7]}}) | + (fx0_itag_q[1] & {`ITAG_SIZE_ENC{fx0_ex0_sched_rel_pri[8]}}) | + (fx0_itag_q[0] & {`ITAG_SIZE_ENC{fx0_ex0_sched_rel_pri[9]}}); + + + assign fx0_rel_itag_vld_d = ( + (fx0_vld_q[4] & {`THREADS{fx0_ex0_sched_rel_pri[5]}}) | + (fx0_vld_q[3] & {`THREADS{fx0_ex0_sched_rel_pri[6]}}) | + (fx0_vld_q[2] & {`THREADS{fx0_ex0_sched_rel_pri[7]}}) | + (fx0_vld_q[1] & {`THREADS{fx0_ex0_sched_rel_pri[8]}}) | + (fx0_vld_q[0] & {`THREADS{fx0_ex0_sched_rel_pri[9]}}) ) & ~cp_flush_q; + + assign fx0_rel_itag_abort_d = + (fx0_abort_q[4] & fx0_ex0_sched_rel_pri[5]) | + (fx0_abort_q[3] & fx0_ex0_sched_rel_pri[6]) ; + + // | and invert in this cycle so select for outbound mux is fast + assign fx0_sched_rel_pri_or_d = (~|(fx0_ex0_sched_rel_pri)); + + // Check fast releases released? + assign fx0_sched_rel_rv = fx0_rv1_ilat_match & fx0_sched_rel_pri_or_q & (~fx0_sched_rel_ex0_fast); + assign fx0_rv1_ilat0 = |(rv_byp_fx0_ilat0_vld); + assign fx0_sched_rel_rv_ilat0 = fx0_rv1_ilat0 & fx0_sched_rel_pri_or_q & (~fx0_sched_rel_ex0_fast); + + assign fx0_sched_rel_ex0_fast = fx0_ex0_fast_match & |(fx0_vld_q[0] ) & fx0_sched_rel_pri_or_q & fx0_need_rel_q[0]; + + // Pipeline to keep track of instructions that have not been released yet + assign fx0_need_rel_d[0] = |(rv_byp_fx0_vld & (~cp_flush_q)) & (~fx0_sched_rel_rv) & (~rv_byp_fx0_ord); + assign fx0_need_rel_d[1] = (fx0_need_rel_q[0] & (~(fx0_ex0_sched_rel_pri[9] | fx0_sched_rel_ex0_fast | fx0_ex0_stq_pipe_val)) & (~|(fx0_vld_q[0] & cp_flush_q))) ; + assign fx0_need_rel_d[2] = fx0_need_rel_q[1] & (~fx0_ex0_sched_rel_pri[8]) & (~|(cp_flush_q & fx0_vld_q[1])); + assign fx0_need_rel_d[3] = ((fx0_need_rel_q[2] & (~fx0_ex0_sched_rel_pri[7])) | (fx0_insert_ord | fx0_ex2_abort)) & (~|(cp_flush_q & fx0_vld_q[2])); + assign fx0_need_rel_d[4] = fx0_need_rel_q[3] & (~fx0_ex0_sched_rel_pri[6]) & (~|(cp_flush_q & fx0_vld_q[3])); + + // 0 bubble case (need to do it last to handle quick dependency turnaround, after the latch for timing) + // Send itag off priority queue to release dependent ops + assign fx0_rv_itag_int = ({fx0_sched_rel_rv, fx0_sched_rel_ex0_fast} == 2'b10) ? rv_byp_fx0_itag : // 1 bubble case + ({fx0_sched_rel_rv, fx0_sched_rel_ex0_fast} == 2'b01) ? fx0_itag_q[0] : + fx0_rel_itag_q; + + assign fx0_rv_itag_vld_int = ({fx0_sched_rel_rv, fx0_sched_rel_ex0_fast} == 2'b10) ? rv_byp_fx0_vld : + ({fx0_sched_rel_rv, fx0_sched_rel_ex0_fast} == 2'b01) ? fx0_vld_q[0] : + fx0_rel_itag_vld_q; + + assign fx0_rv_itag_abort_int = fx0_rel_itag_abort_q & ~(fx0_sched_rel_rv | fx0_sched_rel_ex0_fast); + + assign fx0_rv_itag = fx0_rv_itag_int; + assign fx0_rv_itag_vld = fx0_rv_itag_vld_int; + assign fx0_rv_itag_abort = fx0_rv_itag_abort_int; + + assign fx0_ext_rel_itag_d = fx0_rv_itag_int; + assign fx0_ext_rel_itag_vld_d = fx0_rv_itag_vld_int & {`THREADS{~(fx0_ext_itag0_sel_d)}} & ~cp_flush_q; + assign fx0_ext_rel_itag_abort_d = fx0_rv_itag_abort_int; + + // ilat0 can go only if theres a slot + assign fx0_ext_itag0_sel_d = fx0_sched_rel_rv_ilat0 & (~fx0_ext_ilat_gt_1_need_rel); + assign fx0_ext_ilat_gt_1_need_rel = |(fx0_ext_rel_itag_vld_q) & (~(fx0_ext_itag0_sel_q)); + + assign fx0_rv_ext_itag = ((fx0_sched_rel_rv_ilat0 & (~fx0_ext_ilat_gt_1_need_rel)) == 1'b1) ? rv_byp_fx0_itag : + fx0_ext_rel_itag_q; + + assign fx0_rv_ext_itag_vld = ((fx0_sched_rel_rv_ilat0 & (~fx0_ext_ilat_gt_1_need_rel)) == 1'b1) ? rv_byp_fx0_vld : //ex2 + fx0_ext_rel_itag_vld_q; + + assign fx0_rv_ext_itag_abort = fx0_ext_rel_itag_abort_q & ~(fx0_sched_rel_rv_ilat0 & (~fx0_ext_ilat_gt_1_need_rel)); + + assign fx0_insert_ord = fx0_rv_ord_complete & (~|(fx0_rv_ord_tid & cp_flush_q)); + + + //Ordered release goes with the dep release + assign fx0_ex3_ord_rel_d = {`THREADS{fx0_rv_ord_complete}} & fx0_rv_ord_tid & (~cp_flush_q); + assign fx0_ex4_ord_rel_d = fx0_ex3_ord_rel_q & (~cp_flush_q) & {`THREADS{(~fx0_ex0_sched_rel_pri[6])}}; + assign fx0_ex5_ord_rel_d = fx0_ex4_ord_rel_q & (~cp_flush_q) & {`THREADS{(~fx0_ex0_sched_rel_pri[5])}}; + assign fx0_ex6_ord_rel_d = fx0_ex5_ord_rel_q & (~cp_flush_q) & {`THREADS{(~fx0_ex0_sched_rel_pri[4])}}; + assign fx0_ex7_ord_rel_d = fx0_ex6_ord_rel_q & (~cp_flush_q) & {`THREADS{(~fx0_ex0_sched_rel_pri[3])}}; + assign fx0_ex8_ord_rel_d = fx0_ex7_ord_rel_q & (~cp_flush_q) & {`THREADS{(~fx0_ex0_sched_rel_pri[2])}}; + + assign fx0_release_ord_hold_d = ( + (fx0_vld_q[8] & fx0_ex8_ord_rel_q & {`THREADS{fx0_ex0_sched_rel_pri[1]}}) | + (fx0_vld_q[7] & fx0_ex7_ord_rel_q & {`THREADS{fx0_ex0_sched_rel_pri[2]}}) | + (fx0_vld_q[6] & fx0_ex6_ord_rel_q & {`THREADS{fx0_ex0_sched_rel_pri[3]}}) | + (fx0_vld_q[5] & fx0_ex5_ord_rel_q & {`THREADS{fx0_ex0_sched_rel_pri[4]}}) | + (fx0_vld_q[4] & fx0_ex4_ord_rel_q & {`THREADS{fx0_ex0_sched_rel_pri[5]}}) | + (fx0_vld_q[3] & fx0_ex3_ord_rel_q & {`THREADS{fx0_ex0_sched_rel_pri[6]}}) | ex3_ord_flush) & (~cp_flush_q); + + assign fx0_release_ord_hold = fx0_release_ord_hold_q; + + // If an ordered op gets a spec_flush, release the ord_hold (but not the dependency release bus) + assign ex3_ord_flush = ({`THREADS{fx0_ex3_ord_flush_q}} & fx0_vld_q[3]); + + assign fx0_ex0_ord_d = rv_byp_fx0_ord; + assign fx0_ex1_ord_d = fx0_ex0_ord_q; + assign fx0_ex2_ord_d = fx0_ex1_ord_q; + assign fx0_ex3_ord_flush_d = fx0_ex2_ord_q & fx0_ex2_abort ; + + //---------------------------------------------------------------------------------------------------------------------------------------- + // FX1 RV Release, based on ilat + //---------------------------------------------------------------------------------------------------------------------------------------- + assign fx1_ex2_abort = (fx1_rv_ex2_s1_abort | fx1_rv_ex2_s2_abort | fx1_rv_ex2_s3_abort) & ~fx1_ex2_stq_pipe_q & |(fx1_vld_q[2]); + + assign fx1_act[0] = |(rv_byp_fx1_vld); + assign fx1_act[1] = |(fx1_vld_q[0]); + assign fx1_act[2] = |(fx1_vld_q[1]); + assign fx1_act[3] = |(fx1_vld_q[2]); + assign fx1_act[4] = |(fx1_vld_q[3]); + assign fx1_act[5] = |(fx1_vld_q[4]); + assign fx1_act[6] = |(fx1_vld_q[5]); + assign fx1_act[7] = |(fx1_vld_q[6]); + + assign fx1_itag_d[0] = rv_byp_fx1_itag; + assign fx1_vld_d[0] = rv_byp_fx1_vld & (~cp_flush_q); + generate + begin : xhdl19v + genvar i; + for (i = 1; i <= 6; i = i + 1) + begin : fxu1_vld_d_gen + assign fx1_vld_d[i] = fx1_vld_q[i - 1] & (~cp_flush_q); + end + end + endgenerate + generate + begin : xhdl19 + genvar i; + for (i = 1; i <= 7; i = i + 1) + begin : fxu1_itag_d_gen + assign fx1_itag_d[i] = fx1_itag_q[i - 1]; + end + end + endgenerate + + assign fx1_abort_d[3] = fx1_ex2_abort; + assign fx1_abort_d[4] = fx1_abort_q[3]; + + // Ilat Pipe + assign fx1_ex0_ilat_d = rv_byp_fx1_ilat[1:3]; + assign fx1_ex1_ilat_d = fx1_ex0_ilat_q; + assign fx1_ex2_ilat_d = fx1_ex1_ilat_q; + assign fx1_ex3_ilat_d = fx1_ex2_ilat_q; + assign fx1_ex4_ilat_d = fx1_ex3_ilat_q; + assign fx1_ex5_ilat_d = fx1_ex4_ilat_q; + assign fx1_ex6_ilat_d = fx1_ex5_ilat_q; + + // Match instruction latency with their location in the pipeline + assign fx1_rv1_ilat_match = |(rv_byp_fx1_ilat0_vld | rv_byp_fx1_ilat1_vld); //ilat 0 or 1 + assign fx1_ex0_fast_match = (fx1_ex0_ilat_q <= 3'b010); + assign fx1_ex0_ilat_match = (fx1_ex0_ilat_q <= 3'b011); + assign fx1_ex1_ilat_match = (fx1_ex1_ilat_q <= 3'b100); + assign fx1_ex2_ilat_match = (fx1_ex2_ilat_q <= 3'b101); + assign fx1_ex3_ilat_match = (fx1_ex3_ilat_q <= 3'b110); + + //Store Data. Don't release, or abort on the release bus + assign fx1_ex0_stq_pipe_val = rv_byp_fx1_ex0_isStore; + assign fx1_ex1_stq_pipe_d = fx1_ex0_stq_pipe_val; + assign fx1_ex2_stq_pipe_d = fx1_ex1_stq_pipe_q; + + // Intructions are in correct pipeline stage to allow dependent op release, and they have not been released yet + assign fx1_ex0_sched_rel[4] = (fx1_ex0_ilat_match & fx1_ex0_need_rel_q & (~(fx1_sched_rel_ex0_fast | fx1_ex0_stq_pipe_val)) & (~|(fx1_vld_q[0] & cp_flush_q ))); + assign fx1_ex0_sched_rel[3] = fx1_ex1_ilat_match & fx1_ex1_need_rel_q & (~|(fx1_vld_q[1] & cp_flush_q )); + assign fx1_ex0_sched_rel[2] = fx1_ex2_ilat_match & fx1_ex2_need_rel_q & (~|(fx1_vld_q[2] & cp_flush_q )); + assign fx1_ex0_sched_rel[1] = fx1_ex3_ilat_match & fx1_ex3_need_rel_q & (~|(fx1_vld_q[3] & cp_flush_q )); + assign fx1_ex0_sched_rel[0] = 1'b0; + + assign fx1_byp_rdy_nxt_0 = |rv_byp_fx1_ilat0_vld ; + assign fx1_byp_rdy_nxt[0] = {`THREADS{ (fx1_ex0_ilat_q == 3'b001) }} & fx1_vld_q[0]; + assign fx1_byp_rdy_nxt[1] = {`THREADS{ (fx1_ex1_ilat_q == 3'b010) }} & fx1_vld_q[1]; + assign fx1_byp_rdy_nxt[2] = {`THREADS{ (fx1_ex2_ilat_q == 3'b011) & ~fx1_ex2_stq_pipe_q }} & fx1_vld_q[2]; + assign fx1_byp_rdy_nxt[3] = {`THREADS{ (fx1_ex3_ilat_q == 3'b100) }} & fx1_vld_q[3]; + assign fx1_byp_rdy_nxt[4] = {`THREADS{ (fx1_ex4_ilat_q == 3'b101) }} & fx1_vld_q[4]; + assign fx1_byp_rdy_nxt[5] = {`THREADS{ (fx1_ex5_ilat_q == 3'b110) }} & fx1_vld_q[5]; + assign fx1_byp_rdy_nxt[6] = {`THREADS{ (fx1_ex6_ilat_q == 3'b111) }} & fx1_vld_q[6]; + + // Prioritize. EX6 gets highest priority (Will be latched) + + rv_pri #(.size(5)) fx1_release_pri( + .cond(fx1_ex0_sched_rel), + .pri(fx1_ex0_sched_rel_pri) + ); + + // Use prioritized schedule to determine which stage to release itag/vld out of (Will be latched) + assign fx1_rel_itag_d = (fx1_itag_q[4] & {`ITAG_SIZE_ENC{fx1_ex0_sched_rel_pri[0]}}) | + (fx1_itag_q[3] & {`ITAG_SIZE_ENC{fx1_ex0_sched_rel_pri[1]}}) | + (fx1_itag_q[2] & {`ITAG_SIZE_ENC{fx1_ex0_sched_rel_pri[2]}}) | + (fx1_itag_q[1] & {`ITAG_SIZE_ENC{fx1_ex0_sched_rel_pri[3]}}) | + (fx1_itag_q[0] & {`ITAG_SIZE_ENC{fx1_ex0_sched_rel_pri[4]}}); // when "10000", + + assign fx1_rel_itag_vld_d = ((fx1_vld_q[4] & {`THREADS{fx1_ex0_sched_rel_pri[0]}}) | + (fx1_vld_q[3] & {`THREADS{fx1_ex0_sched_rel_pri[1]}}) | + (fx1_vld_q[2] & {`THREADS{fx1_ex0_sched_rel_pri[2]}}) | + (fx1_vld_q[1] & {`THREADS{fx1_ex0_sched_rel_pri[3]}}) | + (fx1_vld_q[0] & {`THREADS{fx1_ex0_sched_rel_pri[4]}}) ) & ~cp_flush_q; // when "10000", + + assign fx1_rel_itag_abort_d = (fx1_abort_q[4] & fx1_ex0_sched_rel_pri[0]) | + (fx1_abort_q[3] & fx1_ex0_sched_rel_pri[1]) ; + + // | and invert in this cycle so select for outbound mux is fast + assign fx1_sched_rel_pri_or_d = (~|(fx1_ex0_sched_rel_pri)); + + // Check fast releases released? + assign fx1_sched_rel_rv = fx1_rv1_ilat_match & fx1_sched_rel_pri_or_q & (~fx1_sched_rel_ex0_fast); + assign fx1_rv1_ilat0 = |(rv_byp_fx1_ilat0_vld); + assign fx1_sched_rel_rv_ilat0 = fx1_rv1_ilat0 & fx1_sched_rel_pri_or_q & (~fx1_sched_rel_ex0_fast); + + assign fx1_sched_rel_ex0_fast = fx1_ex0_fast_match & |(fx1_vld_q[0]) & fx1_sched_rel_pri_or_q & fx1_ex0_need_rel_q; + + // Pipeline to keep track of instructions that have not been released yet + assign fx1_ex0_need_rel_d = |(rv_byp_fx1_vld & (~cp_flush_q)) & (~fx1_sched_rel_rv); + assign fx1_ex1_need_rel_d = (fx1_ex0_need_rel_q & (~(fx1_ex0_sched_rel_pri[4] | fx1_sched_rel_ex0_fast | fx1_ex0_stq_pipe_val)) & (~|(fx1_vld_q[0] & cp_flush_q ))) ; + + assign fx1_ex2_need_rel_d = fx1_ex1_need_rel_q & (~fx1_ex0_sched_rel_pri[3]) & (~|(fx1_vld_q[1] & cp_flush_q)); + assign fx1_ex3_need_rel_d = ((fx1_ex2_need_rel_q & (~fx1_ex0_sched_rel_pri[2])) | fx1_ex2_abort) & (~|(fx1_vld_q[2] & cp_flush_q)); + + // 0 bubble case (need to do it last to handle quick dependency turnaround, after the latch for timing) + // Send itag off priority queue to release dependent ops + assign fx1_rv_itag_int = ({fx1_sched_rel_rv, fx1_sched_rel_ex0_fast} == 2'b10) ? rv_byp_fx1_itag : // 1 bubble case + ({fx1_sched_rel_rv, fx1_sched_rel_ex0_fast} == 2'b01) ? fx1_itag_q[0] : + fx1_rel_itag_q; + assign fx1_rv_itag_vld_int = ({fx1_sched_rel_rv, fx1_sched_rel_ex0_fast} == 2'b10) ? rv_byp_fx1_vld : + ({fx1_sched_rel_rv, fx1_sched_rel_ex0_fast} == 2'b01) ? fx1_vld_q[0] : + fx1_rel_itag_vld_q; + assign fx1_rv_itag_abort_int = fx1_rel_itag_abort_q & ~(fx1_sched_rel_rv | fx1_sched_rel_ex0_fast); + + assign fx1_rv_itag = fx1_rv_itag_int; + assign fx1_rv_itag_vld = fx1_rv_itag_vld_int; + assign fx1_rv_itag_abort = fx1_rv_itag_abort_int; + + assign fx1_ext_rel_itag_d = fx1_rv_itag_int; + assign fx1_ext_rel_itag_vld_d = fx1_rv_itag_vld_int & {`THREADS{~( fx1_ext_itag0_sel_d)}} & ~cp_flush_q; + assign fx1_ext_rel_itag_abort_d = fx1_rv_itag_abort_int; + + // ilat0 can go only if theres a slot + assign fx1_ext_itag0_sel_d = fx1_sched_rel_rv_ilat0 & (~fx1_ext_ilat_gt_1_need_rel); + assign fx1_ext_ilat_gt_1_need_rel = |(fx1_ext_rel_itag_vld_q) & (~(fx1_ext_itag0_sel_q)); + + assign fx1_rv_ext_itag_vld = ((fx1_sched_rel_rv_ilat0 & (~fx1_ext_ilat_gt_1_need_rel)) == 1'b1) ? rv_byp_fx1_vld : //ex2 + fx1_ext_rel_itag_vld_q; + + assign fx1_rv_ext_itag = ((fx1_sched_rel_rv_ilat0 & (~fx1_ext_ilat_gt_1_need_rel)) == 1'b1) ? rv_byp_fx1_itag : + fx1_ext_rel_itag_q; + assign fx1_rv_ext_itag_abort = fx1_ext_rel_itag_abort_q & ~(fx1_sched_rel_rv_ilat0 & (~fx1_ext_ilat_gt_1_need_rel)); + + + assign lq_itag_d[0] = rv_byp_lq_itag; + generate + begin : xhdl20 + genvar i; + for (i = 1; i <= 8; i = i + 1) + begin : lq_itag_d_gen + assign lq_itag_d[i] = lq_itag_q[i - 1]; + end + end + endgenerate + + assign lq_act[0] = |(rv_byp_lq_vld); + assign lq_act[1] = |(lq_vld_q[0]); + assign lq_act[2] = |(lq_vld_q[1]); + assign lq_act[3] = |(lq_vld_q[2]); + assign lq_act[4] = |(lq_vld_q[3]); + assign lq_act[5] = |(lq_vld_q[4]); + assign lq_act[6] = |(lq_vld_q[5]); + assign lq_act[7] = |(lq_vld_q[6]); + assign lq_act[8] = |(lq_vld_q[7]); + + assign lq_vld_d[0] = rv_byp_lq_vld; + assign lq_vld_d[1] = lq_vld_q[0]; + assign lq_vld_d[2] = lq_vld_q[1]; + assign lq_vld_d[3] = lq_vld_q[2]; + assign lq_vld_d[4] = lq_vld_q[3]; + assign lq_vld_d[5] = lq_vld_q[4]; + assign lq_vld_d[6] = lq_vld_q[5]; + assign lq_vld_d[7] = lq_vld_q[6]; + + + + + //------------------------------------------------------------------- + // Latches + //------------------------------------------------------------------- + generate + begin : xhdl21 + genvar i; + for (i = 0; i <= 12; i = i + 1) + begin : fxu0_t1_gen + + tri_rlmreg_p #(.WIDTH(elmnt_width), .INIT(0), .NEEDS_SRESET(1)) + fxu0_t1_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[(fxu0_t1_offset + (elmnt_width * i)):(fxu0_t1_offset + (elmnt_width * i) + (elmnt_width - 1))]), + .scout(sov[(fxu0_t1_offset + (elmnt_width * i)):(fxu0_t1_offset + (elmnt_width * i) + (elmnt_width - 1))]), + .din(fxu0_t1_d[i]), + .dout(fxu0_t1_q[i]) + ); + end + end + endgenerate + + generate + begin : xhdl22 + genvar i; + for (i = 0; i <= 12; i = i + 1) + begin : fxu0_t2_gen + + tri_rlmreg_p #(.WIDTH(elmnt_width), .INIT(0), .NEEDS_SRESET(1)) + fxu0_t2_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[(fxu0_t2_offset + (elmnt_width * i)):(fxu0_t2_offset + (elmnt_width * i) + (elmnt_width - 1))]), + .scout(sov[(fxu0_t2_offset + (elmnt_width * i)):(fxu0_t2_offset + (elmnt_width * i) + (elmnt_width - 1))]), + .din(fxu0_t2_d[i]), + .dout(fxu0_t2_q[i]) + ); + end + end + endgenerate + + generate + begin + genvar i; + for (i = 0; i <= 12; i = i + 1) + begin : fxu0_t3_gen + + tri_rlmreg_p #(.WIDTH(elmnt_width), .INIT(0), .NEEDS_SRESET(1)) + fxu0_t3_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[(fxu0_t3_offset + (elmnt_width * i)):(fxu0_t3_offset + (elmnt_width * i) + (elmnt_width - 1))]), + .scout(sov[(fxu0_t3_offset + (elmnt_width * i)):(fxu0_t3_offset + (elmnt_width * i) + (elmnt_width - 1))]), + .din(fxu0_t3_d[i]), + .dout(fxu0_t3_q[i]) + ); + end + end + endgenerate + + tri_rlmreg_p #(.WIDTH(elmnt_width), .INIT(0), .NEEDS_SRESET(1)) + fxu0_s1_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(fx0_act[0]), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fxu0_s1_offset:fxu0_s1_offset + elmnt_width - 1]), + .scout(sov[fxu0_s1_offset:fxu0_s1_offset + elmnt_width - 1]), + .din(fxu0_s1_d), + .dout(fxu0_s1_q) + ); + + tri_rlmreg_p #(.WIDTH(elmnt_width), .INIT(0), .NEEDS_SRESET(1)) + fxu0_s2_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(fx0_act[0]), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fxu0_s2_offset:fxu0_s2_offset + elmnt_width - 1]), + .scout(sov[fxu0_s2_offset:fxu0_s2_offset + elmnt_width - 1]), + .din(fxu0_s2_d), + .dout(fxu0_s2_q) + ); + + tri_rlmreg_p #(.WIDTH(elmnt_width), .INIT(0), .NEEDS_SRESET(1)) + fxu0_s3_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(fx0_act[0]), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fxu0_s3_offset:fxu0_s3_offset + elmnt_width - 1]), + .scout(sov[fxu0_s3_offset:fxu0_s3_offset + elmnt_width - 1]), + .din(fxu0_s3_d), + .dout(fxu0_s3_q) + ); + + generate + begin : xhdl24 + genvar i; + for (i = 0; i <= 8; i = i + 1) + begin : lq_t1_gen + + tri_rlmreg_p #(.WIDTH(elmnt_width), .INIT(0), .NEEDS_SRESET(1)) + lq_t1_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[(lq_t1_offset + (elmnt_width * i)):(lq_t1_offset + (elmnt_width * i) + (elmnt_width - 1))]), + .scout(sov[(lq_t1_offset + (elmnt_width * i)):(lq_t1_offset + (elmnt_width * i) + (elmnt_width - 1))]), + .din(lq_t1_d[i]), + .dout(lq_t1_q[i]) + ); + end + end + endgenerate + + + generate + begin : xhdl26 + genvar i; + for (i = 0; i <= 8; i = i + 1) + begin : lq_t3_gen + + tri_rlmreg_p #(.WIDTH(elmnt_width), .INIT(0), .NEEDS_SRESET(1)) + lq_t3_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[(lq_t3_offset + (elmnt_width * i)):(lq_t3_offset + (elmnt_width * i) + (elmnt_width - 1))]), + .scout(sov[(lq_t3_offset + (elmnt_width * i)):(lq_t3_offset + (elmnt_width * i) + (elmnt_width - 1))]), + .din(lq_t3_d[i]), + .dout(lq_t3_q[i]) + ); + end + end + endgenerate + + tri_rlmreg_p #(.WIDTH(elmnt_width), .INIT(0), .NEEDS_SRESET(1)) + lq_s1_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lq_s1_offset:lq_s1_offset + elmnt_width - 1]), + .scout(sov[lq_s1_offset:lq_s1_offset + elmnt_width - 1]), + .din(lq_s1_d), + .dout(lq_s1_q) + ); + + tri_rlmreg_p #(.WIDTH(elmnt_width), .INIT(0), .NEEDS_SRESET(1)) + lq_s2_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lq_s2_offset:lq_s2_offset + elmnt_width - 1]), + .scout(sov[lq_s2_offset:lq_s2_offset + elmnt_width - 1]), + .din(lq_s2_d), + .dout(lq_s2_q) + ); + + generate + begin : xhdl27 + genvar i; + for (i = 0; i <= 7; i = i + 1) + begin : fxu1_t1_gen + + tri_rlmreg_p #(.WIDTH(elmnt_width), .INIT(0), .NEEDS_SRESET(1)) + fxu1_t1_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[(fxu1_t1_offset + (elmnt_width * i)):(fxu1_t1_offset + (elmnt_width * i) + (elmnt_width - 1))]), + .scout(sov[(fxu1_t1_offset + (elmnt_width * i)):(fxu1_t1_offset + (elmnt_width * i) + (elmnt_width - 1))]), + .din(fxu1_t1_d[i]), + .dout(fxu1_t1_q[i]) + ); + end + end + endgenerate + + generate + begin : xhdl28 + genvar i; + for (i = 0; i <= 7; i = i + 1) + begin : fxu1_t2_gen + + tri_rlmreg_p #(.WIDTH(elmnt_width), .INIT(0), .NEEDS_SRESET(1)) + fxu1_t2_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[(fxu1_t2_offset + (elmnt_width * i)):(fxu1_t2_offset + (elmnt_width * i) + (elmnt_width - 1))]), + .scout(sov[(fxu1_t2_offset + (elmnt_width * i)):(fxu1_t2_offset + (elmnt_width * i) + (elmnt_width - 1))]), + .din(fxu1_t2_d[i]), + .dout(fxu1_t2_q[i]) + ); + end + end + endgenerate + + generate + begin : xhdl29 + genvar i; + for (i = 0; i <= 7; i = i + 1) + begin : fxu1_t3_gen + + tri_rlmreg_p #(.WIDTH(elmnt_width), .INIT(0), .NEEDS_SRESET(1)) + fxu1_t3_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[(fxu1_t3_offset + (elmnt_width * i)):(fxu1_t3_offset + (elmnt_width * i) + (elmnt_width - 1))]), + .scout(sov[(fxu1_t3_offset + (elmnt_width * i)):(fxu1_t3_offset + (elmnt_width * i) + (elmnt_width - 1))]), + .din(fxu1_t3_d[i]), + .dout(fxu1_t3_q[i]) + ); + end + end + endgenerate + + tri_rlmreg_p #(.WIDTH(elmnt_width), .INIT(0), .NEEDS_SRESET(1)) + fxu1_s1_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(fx1_act[0]), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fxu1_s1_offset:fxu1_s1_offset + elmnt_width - 1]), + .scout(sov[fxu1_s1_offset:fxu1_s1_offset + elmnt_width - 1]), + .din(fxu1_s1_d), + .dout(fxu1_s1_q) + ); + + tri_rlmreg_p #(.WIDTH(elmnt_width), .INIT(0), .NEEDS_SRESET(1)) + fxu1_s2_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(fx1_act[0]), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fxu1_s2_offset:fxu1_s2_offset + elmnt_width - 1]), + .scout(sov[fxu1_s2_offset:fxu1_s2_offset + elmnt_width - 1]), + .din(fxu1_s2_d), + .dout(fxu1_s2_q) + ); + + tri_rlmreg_p #(.WIDTH(elmnt_width), .INIT(0), .NEEDS_SRESET(1)) + fxu1_s3_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(fx1_act[0]), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fxu1_s3_offset:fxu1_s3_offset + elmnt_width - 1]), + .scout(sov[fxu1_s3_offset:fxu1_s3_offset + elmnt_width - 1]), + .din(fxu1_s3_d), + .dout(fxu1_s3_q) + ); + + generate + begin : xhdl77 + genvar i; + for (i = 0; i <= 3 ; i = i + 1) + begin : rel_gen + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) + rel_vld_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rel_vld_offset + (`THREADS * i):(rel_vld_offset + (`THREADS * i) + (`THREADS - 1))]), + .scout(sov[rel_vld_offset + (`THREADS * i):(rel_vld_offset + (`THREADS * i) + (`THREADS - 1))]), + .din(rel_vld_d[i]), + .dout(rel_vld_q[i]) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) + rel_itag_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[rel_itag_offset + (`ITAG_SIZE_ENC * i):(rel_itag_offset + (`ITAG_SIZE_ENC * i) + (`ITAG_SIZE_ENC - 1))]), + .scout(sov[rel_itag_offset + (`ITAG_SIZE_ENC * i):(rel_itag_offset + (`ITAG_SIZE_ENC * i) + (`ITAG_SIZE_ENC - 1))]), + .din(rel_itag_d[i]), + .dout(rel_itag_q[i]) + ); + end + end + endgenerate + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) + cp_flush_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[cp_flush_offset:cp_flush_offset + `THREADS - 1]), + .scout(sov[cp_flush_offset:cp_flush_offset + `THREADS - 1]), + .din(cp_flush), + .dout(cp_flush_q) + ); + + generate + begin : xhdl78b + genvar i; + for (i = 1; i <= 7; i = i + 1) + begin : fxu0_itagv_gen + + tri_rlmlatch_p #(.INIT(0)) + fx0_is_brick_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(fx0_act[i]), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx0_is_brick_offset +i-1 ]), + .scout(sov[fx0_is_brick_offset +i-1 ]), + .din(fx0_is_brick_d[i]), + .dout(fx0_is_brick_q[i]) + ); + + end + end + endgenerate + generate + begin : xhdl78v + genvar i; + for (i = 0; i <= 11; i = i + 1) + begin : fxu0_itagv_gen + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) + fx0_vld_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx0_vld_offset + (`THREADS * i):(fx0_vld_offset + (`THREADS * i) + `THREADS - 1)]), + .scout(sov[fx0_vld_offset + (`THREADS * i):(fx0_vld_offset + (`THREADS * i) + `THREADS - 1)]), + .din(fx0_vld_d[i]), + .dout(fx0_vld_q[i]) + ); + + end + end + endgenerate + generate + begin : xhdl78i + genvar i; + for (i = 0; i <= 12; i = i + 1) + begin : fxu0_itag_gen + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) + fx0_itag_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(fx0_act[i]), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[(fx0_itag_offset + (`ITAG_SIZE_ENC * i)):(fx0_itag_offset + (`ITAG_SIZE_ENC * i) + (`ITAG_SIZE_ENC - 1))]), + .scout(sov[(fx0_itag_offset + (`ITAG_SIZE_ENC * i)):(fx0_itag_offset + (`ITAG_SIZE_ENC * i) + (`ITAG_SIZE_ENC - 1))]), + .din(fx0_itag_d[i]), + .dout(fx0_itag_q[i]) + ); + end + end + endgenerate + + + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) + fx0_ex0_ilat_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(fx0_act[0]), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx0_ex0_ilat_offset:fx0_ex0_ilat_offset + 4 - 1]), + .scout(sov[fx0_ex0_ilat_offset:fx0_ex0_ilat_offset + 4 - 1]), + .din(fx0_ex0_ilat_d), + .dout(fx0_ex0_ilat_q) + ); + + + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) + fx0_ex1_ilat_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(fx0_act[1]), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx0_ex1_ilat_offset:fx0_ex1_ilat_offset + 4 - 1]), + .scout(sov[fx0_ex1_ilat_offset:fx0_ex1_ilat_offset + 4 - 1]), + .din(fx0_ex1_ilat_d), + .dout(fx0_ex1_ilat_q) + ); + + + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) + fx0_ex2_ilat_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(fx0_act[2]), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx0_ex2_ilat_offset:fx0_ex2_ilat_offset + 4 - 1]), + .scout(sov[fx0_ex2_ilat_offset:fx0_ex2_ilat_offset + 4 - 1]), + .din(fx0_ex2_ilat_d), + .dout(fx0_ex2_ilat_q) + ); + + + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) + fx0_ex3_ilat_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(fx0_act[3]), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx0_ex3_ilat_offset:fx0_ex3_ilat_offset + 4 - 1]), + .scout(sov[fx0_ex3_ilat_offset:fx0_ex3_ilat_offset + 4 - 1]), + .din(fx0_ex3_ilat_d), + .dout(fx0_ex3_ilat_q) + ); + + + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) + fx0_ex4_ilat_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(fx0_act[4]), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx0_ex4_ilat_offset:fx0_ex4_ilat_offset + 4 - 1]), + .scout(sov[fx0_ex4_ilat_offset:fx0_ex4_ilat_offset + 4 - 1]), + .din(fx0_ex4_ilat_d), + .dout(fx0_ex4_ilat_q) + ); + + + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) + fx0_ex5_ilat_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(fx0_act[5]), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx0_ex5_ilat_offset:fx0_ex5_ilat_offset + 4 - 1]), + .scout(sov[fx0_ex5_ilat_offset:fx0_ex5_ilat_offset + 4 - 1]), + .din(fx0_ex5_ilat_d), + .dout(fx0_ex5_ilat_q) + ); + + + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) + fx0_ex6_ilat_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(fx0_act[6]), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx0_ex6_ilat_offset:fx0_ex6_ilat_offset + 4 - 1]), + .scout(sov[fx0_ex6_ilat_offset:fx0_ex6_ilat_offset + 4 - 1]), + .din(fx0_ex6_ilat_d), + .dout(fx0_ex6_ilat_q) + ); + + + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) + fx0_ex7_ilat_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(fx0_act[7]), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx0_ex7_ilat_offset:fx0_ex7_ilat_offset + 4 - 1]), + .scout(sov[fx0_ex7_ilat_offset:fx0_ex7_ilat_offset + 4 - 1]), + .din(fx0_ex7_ilat_d), + .dout(fx0_ex7_ilat_q) + ); + + + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) + fx0_ex8_ilat_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(fx0_act[8]), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx0_ex8_ilat_offset:fx0_ex8_ilat_offset + 4 - 1]), + .scout(sov[fx0_ex8_ilat_offset:fx0_ex8_ilat_offset + 4 - 1]), + .din(fx0_ex8_ilat_d), + .dout(fx0_ex8_ilat_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) + fx0_rel_itag_vld_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx0_rel_itag_vld_offset:fx0_rel_itag_vld_offset + `THREADS - 1]), + .scout(sov[fx0_rel_itag_vld_offset:fx0_rel_itag_vld_offset + `THREADS - 1]), + .din(fx0_rel_itag_vld_d), + .dout(fx0_rel_itag_vld_q) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) + fx0_rel_itag_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx0_rel_itag_offset:fx0_rel_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[fx0_rel_itag_offset:fx0_rel_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(fx0_rel_itag_d), + .dout(fx0_rel_itag_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) + fx0_ext_rel_itag_vld_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx0_ext_rel_itag_vld_offset:fx0_ext_rel_itag_vld_offset + `THREADS - 1]), + .scout(sov[fx0_ext_rel_itag_vld_offset:fx0_ext_rel_itag_vld_offset + `THREADS - 1]), + .din(fx0_ext_rel_itag_vld_d), + .dout(fx0_ext_rel_itag_vld_q) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) + fx0_ext_rel_itag_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx0_ext_rel_itag_offset:fx0_ext_rel_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[fx0_ext_rel_itag_offset:fx0_ext_rel_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(fx0_ext_rel_itag_d), + .dout(fx0_ext_rel_itag_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) + fx0_ext_itag0_sel_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx0_ext_itag0_sel_offset]), + .scout(sov[fx0_ext_itag0_sel_offset]), + .din(fx0_ext_itag0_sel_d), + .dout(fx0_ext_itag0_sel_q) + ); + + + tri_rlmreg_p #(.WIDTH(5), .INIT(0)) + fx0_need_rel_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx0_need_rel_offset:fx0_need_rel_offset + 5 - 1]), + .scout(sov[fx0_need_rel_offset:fx0_need_rel_offset + 5 - 1]), + .din(fx0_need_rel_d), + .dout(fx0_need_rel_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) + fx0_ex3_ord_rel_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx0_ex3_ord_rel_offset:fx0_ex3_ord_rel_offset + `THREADS - 1]), + .scout(sov[fx0_ex3_ord_rel_offset:fx0_ex3_ord_rel_offset + `THREADS - 1]), + .din(fx0_ex3_ord_rel_d), + .dout(fx0_ex3_ord_rel_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) + fx0_ex4_ord_rel_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx0_ex4_ord_rel_offset:fx0_ex4_ord_rel_offset + `THREADS - 1]), + .scout(sov[fx0_ex4_ord_rel_offset:fx0_ex4_ord_rel_offset + `THREADS - 1]), + .din(fx0_ex4_ord_rel_d), + .dout(fx0_ex4_ord_rel_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) + fx0_ex5_ord_rel_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx0_ex5_ord_rel_offset:fx0_ex5_ord_rel_offset + `THREADS - 1]), + .scout(sov[fx0_ex5_ord_rel_offset:fx0_ex5_ord_rel_offset + `THREADS - 1]), + .din(fx0_ex5_ord_rel_d), + .dout(fx0_ex5_ord_rel_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) + fx0_ex6_ord_rel_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx0_ex6_ord_rel_offset:fx0_ex6_ord_rel_offset + `THREADS - 1]), + .scout(sov[fx0_ex6_ord_rel_offset:fx0_ex6_ord_rel_offset + `THREADS - 1]), + .din(fx0_ex6_ord_rel_d), + .dout(fx0_ex6_ord_rel_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) + fx0_ex7_ord_rel_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx0_ex7_ord_rel_offset:fx0_ex7_ord_rel_offset + `THREADS - 1]), + .scout(sov[fx0_ex7_ord_rel_offset:fx0_ex7_ord_rel_offset + `THREADS - 1]), + .din(fx0_ex7_ord_rel_d), + .dout(fx0_ex7_ord_rel_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) + fx0_ex8_ord_rel_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx0_ex8_ord_rel_offset:fx0_ex8_ord_rel_offset + `THREADS - 1]), + .scout(sov[fx0_ex8_ord_rel_offset:fx0_ex8_ord_rel_offset + `THREADS - 1]), + .din(fx0_ex8_ord_rel_d), + .dout(fx0_ex8_ord_rel_q) + ); + + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) + fx0_release_ord_hold_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx0_release_ord_hold_offset:fx0_release_ord_hold_offset + `THREADS - 1]), + .scout(sov[fx0_release_ord_hold_offset:fx0_release_ord_hold_offset + `THREADS - 1]), + .din(fx0_release_ord_hold_d), + .dout(fx0_release_ord_hold_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) + fx0_ex0_ord_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(fx0_act[0]), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx0_ex0_ord_offset]), + .scout(sov[fx0_ex0_ord_offset]), + .din(fx0_ex0_ord_d), + .dout(fx0_ex0_ord_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) + fx0_ex1_ord_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(fx0_act[1]), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx0_ex1_ord_offset]), + .scout(sov[fx0_ex1_ord_offset]), + .din(fx0_ex1_ord_d), + .dout(fx0_ex1_ord_q) + ); + + tri_rlmlatch_p #(.INIT(0)) + fx0_ex2_ord_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(fx0_act[2]), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx0_ex2_ord_offset]), + .scout(sov[fx0_ex2_ord_offset]), + .din(fx0_ex2_ord_d), + .dout(fx0_ex2_ord_q) + ); + tri_rlmlatch_p #(.INIT(0)) + fx0_ex3_ord_flush_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(fx0_act[3]), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx0_ex3_ord_flush_offset]), + .scout(sov[fx0_ex3_ord_flush_offset]), + .din(fx0_ex3_ord_flush_d), + .dout(fx0_ex3_ord_flush_q) + ); + + tri_rlmlatch_p #(.INIT(0)) + fx0_sched_rel_pri_or_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx0_sched_rel_pri_or_offset]), + .scout(sov[fx0_sched_rel_pri_or_offset]), + .din(fx0_sched_rel_pri_or_d), + .dout(fx0_sched_rel_pri_or_q) + ); + tri_rlmlatch_p #(.INIT(0)) + fx0_rel_itag_abort_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx0_rel_itag_abort_offset]), + .scout(sov[fx0_rel_itag_abort_offset]), + .din(fx0_rel_itag_abort_d), + .dout(fx0_rel_itag_abort_q) + ); + + tri_rlmlatch_p #(.INIT(0)) + fx0_ext_rel_itag_abort_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx0_ext_rel_itag_abort_offset]), + .scout(sov[fx0_ext_rel_itag_abort_offset]), + .din(fx0_ext_rel_itag_abort_d), + .dout(fx0_ext_rel_itag_abort_q) + ); + tri_rlmlatch_p #(.INIT(0)) + fx0_ex5_recircd_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx0_ex5_recircd_offset]), + .scout(sov[fx0_ex5_recircd_offset]), + .din(fx0_ex5_recircd_d), + .dout(fx0_ex5_recircd_q) + ); + tri_rlmlatch_p #(.INIT(0)) + fx0_ex6_recircd_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx0_ex6_recircd_offset]), + .scout(sov[fx0_ex6_recircd_offset]), + .din(fx0_ex6_recircd_d), + .dout(fx0_ex6_recircd_q) + ); + tri_rlmlatch_p #(.INIT(0)) + fx0_ex7_recircd_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx0_ex7_recircd_offset]), + .scout(sov[fx0_ex7_recircd_offset]), + .din(fx0_ex7_recircd_d), + .dout(fx0_ex7_recircd_q) + ); + + generate + begin : xab0 + genvar i; + for (i = 3; i <= 4; i = i + 1) + begin : fx0xab + + tri_rlmlatch_p #(.INIT(0)) + fx0_abort_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(fx0_act[i]), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx0_abort_offset+i-3]), + .scout(sov[fx0_abort_offset+i-3]), + .din(fx0_abort_d[i]), + .dout(fx0_abort_q[i]) + ); + + end // block: fx0xab + end // block: xab0 + endgenerate + + + generate + begin : xhdl70v + genvar i; + for (i = 0; i <= 6; i = i + 1) + begin : fxu1_vld_gen + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) + fx1_vld_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx1_vld_offset + (`THREADS * i):(fx1_vld_offset + (`THREADS * i) + `THREADS - 1)]), + .scout(sov[fx1_vld_offset + (`THREADS * i):(fx1_vld_offset + (`THREADS * i) + `THREADS - 1)]), + .din(fx1_vld_d[i]), + .dout(fx1_vld_q[i]) + ); + + end + end + endgenerate + + generate + begin : xhdl70 + genvar i; + for (i = 0; i <= 7; i = i + 1) + + begin : fxu1_itag_gen + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) + fx1_itag_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(fx1_act[i]), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[(fx1_itag_offset + (`ITAG_SIZE_ENC * i)):(fx1_itag_offset + (`ITAG_SIZE_ENC * i) + (`ITAG_SIZE_ENC - 1))]), + .scout(sov[(fx1_itag_offset + (`ITAG_SIZE_ENC * i)):(fx1_itag_offset + (`ITAG_SIZE_ENC * i) + (`ITAG_SIZE_ENC - 1))]), + .din(fx1_itag_d[i]), + .dout(fx1_itag_q[i]) + ); + end + end + endgenerate + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) + fx1_ex0_ilat_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(fx1_act[0]), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx1_ex0_ilat_offset:fx1_ex0_ilat_offset + 3 - 1]), + .scout(sov[fx1_ex0_ilat_offset:fx1_ex0_ilat_offset + 3 - 1]), + .din(fx1_ex0_ilat_d), + .dout(fx1_ex0_ilat_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) + fx1_ex1_ilat_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(fx1_act[1]), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx1_ex1_ilat_offset:fx1_ex1_ilat_offset + 3 - 1]), + .scout(sov[fx1_ex1_ilat_offset:fx1_ex1_ilat_offset + 3 - 1]), + .din(fx1_ex1_ilat_d), + .dout(fx1_ex1_ilat_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) + fx1_ex2_ilat_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(fx1_act[2]), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx1_ex2_ilat_offset:fx1_ex2_ilat_offset + 3 - 1]), + .scout(sov[fx1_ex2_ilat_offset:fx1_ex2_ilat_offset + 3 - 1]), + .din(fx1_ex2_ilat_d), + .dout(fx1_ex2_ilat_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) + fx1_ex3_ilat_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(fx1_act[3]), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx1_ex3_ilat_offset:fx1_ex3_ilat_offset + 3 - 1]), + .scout(sov[fx1_ex3_ilat_offset:fx1_ex3_ilat_offset + 3 - 1]), + .din(fx1_ex3_ilat_d), + .dout(fx1_ex3_ilat_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) + fx1_ex4_ilat_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(fx1_act[4]), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx1_ex4_ilat_offset:fx1_ex4_ilat_offset + 3 - 1]), + .scout(sov[fx1_ex4_ilat_offset:fx1_ex4_ilat_offset + 3 - 1]), + .din(fx1_ex4_ilat_d), + .dout(fx1_ex4_ilat_q) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) + fx1_ex5_ilat_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(fx1_act[5]), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx1_ex5_ilat_offset:fx1_ex5_ilat_offset + 3 - 1]), + .scout(sov[fx1_ex5_ilat_offset:fx1_ex5_ilat_offset + 3 - 1]), + .din(fx1_ex5_ilat_d), + .dout(fx1_ex5_ilat_q) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) + fx1_ex6_ilat_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(fx1_act[6]), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx1_ex6_ilat_offset:fx1_ex6_ilat_offset + 3 - 1]), + .scout(sov[fx1_ex6_ilat_offset:fx1_ex6_ilat_offset + 3 - 1]), + .din(fx1_ex6_ilat_d), + .dout(fx1_ex6_ilat_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) + fx1_rel_itag_vld_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx1_rel_itag_vld_offset:fx1_rel_itag_vld_offset + `THREADS - 1]), + .scout(sov[fx1_rel_itag_vld_offset:fx1_rel_itag_vld_offset + `THREADS - 1]), + .din(fx1_rel_itag_vld_d), + .dout(fx1_rel_itag_vld_q) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) + fx1_rel_itag_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx1_rel_itag_offset:fx1_rel_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[fx1_rel_itag_offset:fx1_rel_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(fx1_rel_itag_d), + .dout(fx1_rel_itag_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) + fx1_ext_rel_itag_vld_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx1_ext_rel_itag_vld_offset:fx1_ext_rel_itag_vld_offset + `THREADS - 1]), + .scout(sov[fx1_ext_rel_itag_vld_offset:fx1_ext_rel_itag_vld_offset + `THREADS - 1]), + .din(fx1_ext_rel_itag_vld_d), + .dout(fx1_ext_rel_itag_vld_q) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) + fx1_ext_rel_itag_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx1_ext_rel_itag_offset:fx1_ext_rel_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[fx1_ext_rel_itag_offset:fx1_ext_rel_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(fx1_ext_rel_itag_d), + .dout(fx1_ext_rel_itag_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) + fx1_ext_itag0_sel_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx1_ext_itag0_sel_offset]), + .scout(sov[fx1_ext_itag0_sel_offset]), + .din(fx1_ext_itag0_sel_d), + .dout(fx1_ext_itag0_sel_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) + fx1_ex0_need_rel_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx1_ex0_need_rel_offset]), + .scout(sov[fx1_ex0_need_rel_offset]), + .din(fx1_ex0_need_rel_d), + .dout(fx1_ex0_need_rel_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) + fx1_ex1_need_rel_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx1_ex1_need_rel_offset]), + .scout(sov[fx1_ex1_need_rel_offset]), + .din(fx1_ex1_need_rel_d), + .dout(fx1_ex1_need_rel_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) + fx1_ex2_need_rel_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx1_ex2_need_rel_offset]), + .scout(sov[fx1_ex2_need_rel_offset]), + .din(fx1_ex2_need_rel_d), + .dout(fx1_ex2_need_rel_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) + fx1_ex3_need_rel_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx1_ex3_need_rel_offset]), + .scout(sov[fx1_ex3_need_rel_offset]), + .din(fx1_ex3_need_rel_d), + .dout(fx1_ex3_need_rel_q) + ); + + tri_rlmlatch_p #(.INIT(0)) + fx1_ex1_stq_pipe_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx1_ex1_stq_pipe_offset]), + .scout(sov[fx1_ex1_stq_pipe_offset]), + .din(fx1_ex1_stq_pipe_d), + .dout(fx1_ex1_stq_pipe_q) + ); + tri_rlmlatch_p #(.INIT(0)) + fx1_ex2_stq_pipe_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx1_ex2_stq_pipe_offset]), + .scout(sov[fx1_ex2_stq_pipe_offset]), + .din(fx1_ex2_stq_pipe_d), + .dout(fx1_ex2_stq_pipe_q) + ); + + tri_rlmlatch_p #(.INIT(0)) + fx1_sched_rel_pri_or_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx1_sched_rel_pri_or_offset]), + .scout(sov[fx1_sched_rel_pri_or_offset]), + .din(fx1_sched_rel_pri_or_d), + .dout(fx1_sched_rel_pri_or_q) + ); + + tri_rlmlatch_p #(.INIT(0)) + fx1_rel_itag_abort_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx1_rel_itag_abort_offset]), + .scout(sov[fx1_rel_itag_abort_offset]), + .din(fx1_rel_itag_abort_d), + .dout(fx1_rel_itag_abort_q) + ); + + tri_rlmlatch_p #(.INIT(0)) + fx1_ext_rel_itag_abort_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx1_ext_rel_itag_abort_offset]), + .scout(sov[fx1_ext_rel_itag_abort_offset]), + .din(fx1_ext_rel_itag_abort_d), + .dout(fx1_ext_rel_itag_abort_q) + ); + + generate + begin : xab1 + genvar i; + for (i = 3; i <= 4; i = i + 1) + begin : fx1xab + + tri_rlmlatch_p #(.INIT(0)) + fx0_abort_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(fx1_act[i]), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx1_abort_offset+i-3]), + .scout(sov[fx1_abort_offset+i-3]), + .din(fx1_abort_d[i]), + .dout(fx1_abort_q[i]) + ); + + end // block: fx0xab + end // block: xab0 + endgenerate + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) + fx0_ex0_s1_itag_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(fx0_act[0]), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx0_ex0_s1_itag_offset:fx0_ex0_s1_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[fx0_ex0_s1_itag_offset:fx0_ex0_s1_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(rv_fx0_s1_itag), + .dout(fx0_ex0_s1_itag_q) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) + fx0_ex0_s2_itag_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(fx0_act[0]), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx0_ex0_s2_itag_offset:fx0_ex0_s2_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[fx0_ex0_s2_itag_offset:fx0_ex0_s2_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(rv_fx0_s2_itag), + .dout(fx0_ex0_s2_itag_q) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) + fx0_ex0_s3_itag_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(fx0_act[0]), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx0_ex0_s3_itag_offset:fx0_ex0_s3_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[fx0_ex0_s3_itag_offset:fx0_ex0_s3_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(rv_fx0_s3_itag), + .dout(fx0_ex0_s3_itag_q) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) + fx1_ex0_s1_itag_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(fx1_act[0]), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx1_ex0_s1_itag_offset:fx1_ex0_s1_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[fx1_ex0_s1_itag_offset:fx1_ex0_s1_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(rv_fx1_s1_itag), + .dout(fx1_ex0_s1_itag_q) + ); + + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) + fx1_ex0_s2_itag_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(fx1_act[0]), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx1_ex0_s2_itag_offset:fx1_ex0_s2_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[fx1_ex0_s2_itag_offset:fx1_ex0_s2_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(rv_fx1_s2_itag), + .dout(fx1_ex0_s2_itag_q) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) + fx1_ex0_s3_itag_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(fx1_act[0]), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fx1_ex0_s3_itag_offset:fx1_ex0_s3_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[fx1_ex0_s3_itag_offset:fx1_ex0_s3_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(rv_fx1_s3_itag), + .dout(fx1_ex0_s3_itag_q) + ); + + generate + begin : xhdl80 + genvar i; + for (i = 0; i <= 7; i = i + 1) + begin : lq_vld_gen + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) + lq_vld_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[(lq_vld_offset + (`THREADS * i)):(lq_vld_offset + (`THREADS * i) + (`THREADS - 1))]), + .scout(sov[(lq_vld_offset + (`THREADS * i)):(lq_vld_offset + (`THREADS * i) + (`THREADS - 1))]), + .din(lq_vld_d[i]), + .dout(lq_vld_q[i]) + ); + end + end + endgenerate + + generate + begin : xhdl81 + genvar i; + for (i = 0; i <= `LQ_LOAD_PIPE_END; i = i + 1) + begin : lq_itag_gen + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) + lq_itag_reg( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(lq_act[i]), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[(lq_itag_offset + (`ITAG_SIZE_ENC * i)):(lq_itag_offset + (`ITAG_SIZE_ENC * i) + (`ITAG_SIZE_ENC - 1))]), + .scout(sov[(lq_itag_offset + (`ITAG_SIZE_ENC * i)):(lq_itag_offset + (`ITAG_SIZE_ENC * i) + (`ITAG_SIZE_ENC - 1))]), + .din(lq_itag_d[i]), + .dout(lq_itag_q[i]) + ); + end + end + endgenerate + + + + assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in}; + assign scan_out = sov[0]; + + //----------------------------------------------- + // pervasive + //----------------------------------------------- + + + tri_plat #(.WIDTH(2)) perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(ccflush_dc), + .din({func_sl_thold_1, sg_1}), + .q({func_sl_thold_0, sg_0}) + ); + + + tri_lcbor + perv_lcbor( + .clkoff_b(clkoff_b), + .thold(func_sl_thold_0), + .sg(sg_0), + .act_dis(act_dis), + .force_t(force_t), + .thold_b(func_sl_thold_0_b) + ); + +endmodule // rv_rf_byp diff --git a/dev/verilog/work/rv_rpri.v b/dev/verilog/work/rv_rpri.v new file mode 100755 index 0000000..d41bb1d --- /dev/null +++ b/dev/verilog/work/rv_rpri.v @@ -0,0 +1,117 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: Prioritizer +// +//***************************************************************************** + +module rv_rpri( + cond, + pri + ); + parameter size = 32; + input [0:size-1] cond; + output [0:size-1] pri; + + parameter s = size - 1; + wire [0:s] or_l1; + wire [0:s] or_l2; + wire [0:s] or_l3; + wire [0:s] or_l4; + (* analysis_not_referenced="<0>true" *) + wire [0:s] or_l5; + + // Odd Numbered Levels are inverted + + assign or_l1[s] = (~cond[s]); + assign or_l1[0:s - 1] = ~(cond[0:s - 1] | cond[1:s]); + + generate + if (s >= 2) + begin : or_l2_gen0 + assign or_l2[s - 1:s] = (~or_l1[s - 1:s]); + assign or_l2[0:s - 2] = ~(or_l1[2:s] & or_l1[0:s - 2]); + end + endgenerate + generate + if (s < 2) + begin : or_l2_gen1 + assign or_l2 = (~or_l1); + end + endgenerate + + generate + if (s >= 4) + begin : or_l3_gen0 + assign or_l3[s - 3:s] = (~or_l2[s - 3:s]); + assign or_l3[0:s - 4] = ~(or_l2[4:s] | or_l2[0:s - 4]); + end + endgenerate + generate + if (s < 4) + begin : or_l3_gen1 + assign or_l3 = (~or_l2); + end + endgenerate + + generate + if (s >= 8) + begin : or_l4_gen0 + assign or_l4[s - 7:s] = (~or_l3[s - 7:s]); + assign or_l4[0:s - 8] = ~(or_l3[8:s] & or_l3[0:s - 8]); + end + endgenerate + generate + if (s < 8) + begin : or_l4_gen1 + assign or_l4 = (~or_l3); + end + endgenerate + + generate + if (s >= 16) + begin : or_l5_gen0 + assign or_l5[s - 15:s] = (~or_l4[s - 15:s]); + assign or_l5[0:s - 16] = ~{or_l4[16:s] | or_l4[0:s - 16]}; + end + endgenerate + generate + if (s < 16) + begin : or_l5_gen1 + assign or_l5 = (~or_l4); + end + endgenerate + + //assert size > 32 report "Maximum Size of 32 Exceeded!" severity error; + + assign pri[s] = cond[s]; + assign pri[0:s - 1] = cond[0:s - 1] & or_l5[1:s]; + +endmodule diff --git a/dev/verilog/work/rv_station.v b/dev/verilog/work/rv_station.v new file mode 100755 index 0000000..de46e8b --- /dev/null +++ b/dev/verilog/work/rv_station.v @@ -0,0 +1,3359 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//---------------------------------------------------------------------------------------------------- +// Title: rv_station.vhdl +// Desc: Parameterizable reservation station +//----------------------------------------------------------------------------------------------------- +module rv_station( + + + cp_flush, + cp_next_itag, + rv0_instr_i0_vld, + rv0_instr_i0_rte, + rv0_instr_i1_vld, + rv0_instr_i1_rte, + rv0_instr_i0_dat, + rv0_instr_i0_dat_ex0, + rv0_instr_i0_itag, + rv0_instr_i0_ord, + rv0_instr_i0_cord, + rv0_instr_i0_spec, + rv0_instr_i0_s1_v, + rv0_instr_i0_s1_dep_hit, + rv0_instr_i0_s1_itag, + rv0_instr_i0_s2_v, + rv0_instr_i0_s2_dep_hit, + rv0_instr_i0_s2_itag, + rv0_instr_i0_s3_v, + rv0_instr_i0_s3_dep_hit, + rv0_instr_i0_s3_itag, + rv0_instr_i0_is_brick, + rv0_instr_i0_brick, + rv0_instr_i0_ilat, + rv0_instr_i1_dat, + rv0_instr_i1_dat_ex0, + rv0_instr_i1_itag, + rv0_instr_i1_ord, + rv0_instr_i1_cord, + rv0_instr_i1_spec, + rv0_instr_i1_s1_v, + rv0_instr_i1_s1_dep_hit, + rv0_instr_i1_s1_itag, + rv0_instr_i1_s2_v, + rv0_instr_i1_s2_dep_hit, + rv0_instr_i1_s2_itag, + rv0_instr_i1_s3_v, + rv0_instr_i1_s3_dep_hit, + rv0_instr_i1_s3_itag, + rv0_instr_i1_is_brick, + rv0_instr_i1_brick, + rv0_instr_i1_ilat, + + fx0_rv_itag_vld, + fx0_rv_itag, + fx1_rv_itag_vld, + fx1_rv_itag, + axu0_rv_itag_vld, + axu0_rv_itag, + axu1_rv_itag_vld, + axu1_rv_itag, + lq_rv_itag0_vld, + lq_rv_itag0, + lq_rv_itag1_vld, + lq_rv_itag1, + lq_rv_itag2_vld, + lq_rv_itag2, + + fx0_rv_itag_abort, + fx1_rv_itag_abort, + axu0_rv_itag_abort, + axu1_rv_itag_abort, + lq_rv_itag0_abort, + lq_rv_itag1_abort, + + lq_rv_itag1_restart, + lq_rv_itag1_hold, + lq_rv_itag1_cord, + lq_rv_itag1_rst_vld, + lq_rv_itag1_rst, + lq_rv_clr_hold, + + xx_rv_ex2_s1_abort, + xx_rv_ex2_s2_abort, + xx_rv_ex2_s3_abort, + + q_hold_all, + q_ord_complete, + q_ord_tid, + rv1_other_ilat0_vld, + rv1_other_ilat0_itag, + rv1_other_ilat0_vld_out, + rv1_other_ilat0_itag_out, + rv1_instr_vld, + rv1_instr_dat, + rv1_instr_spec, + rv1_instr_ord, + rv1_instr_is_brick, + rv1_instr_itag, + rv1_instr_ilat, + rv1_instr_ilat0_vld, + rv1_instr_ilat1_vld, + rv1_instr_s1_itag, + rv1_instr_s2_itag, + rv1_instr_s3_itag, + ex0_instr_dat, + ex1_credit_free, + rvs_empty, + rvs_perf_bus, + rvs_dbg_bus, + vdd, + gnd, + nclk, + sg_1, + func_sl_thold_1, + ccflush_dc, + act_dis, + clkoff_b, + d_mode, + delay_lclkr, + mpw1_b, + mpw2_b, + scan_in, + scan_out + ); +`include "tri_a2o.vh" + + parameter q_dat_width_g = 80; + parameter q_dat_ex0_width_g = 60; + parameter q_num_entries_g = 12; + parameter q_barf_enc_g = 4; + parameter q_itag_busses_g = 7; // 2 fx, 3 lq, 2 axu + parameter q_ord_g = 1; // ordered Logic + parameter q_cord_g = 1; // Completion Ordered ordered Logic + parameter q_brick_g = 1'b1; // Brick Logic + parameter q_lq_g=0; + parameter q_noilat0_g=0; + + + input [0:`THREADS-1] cp_flush; + input [0:(`THREADS*`ITAG_SIZE_ENC)-1] cp_next_itag; + + input [0:`THREADS-1] rv0_instr_i0_vld; + input rv0_instr_i0_rte; + input [0:`THREADS-1] rv0_instr_i1_vld; + input rv0_instr_i1_rte; + + input [0:q_dat_width_g-1] rv0_instr_i0_dat; + input [0:q_dat_ex0_width_g-1] rv0_instr_i0_dat_ex0; + input [0:`ITAG_SIZE_ENC-1] rv0_instr_i0_itag; + input rv0_instr_i0_ord; + input rv0_instr_i0_cord; + input rv0_instr_i0_spec; + input rv0_instr_i0_s1_v; + input rv0_instr_i0_s1_dep_hit; + input [0:`ITAG_SIZE_ENC-1] rv0_instr_i0_s1_itag; + input rv0_instr_i0_s2_v; + input rv0_instr_i0_s2_dep_hit; + input [0:`ITAG_SIZE_ENC-1] rv0_instr_i0_s2_itag; + input rv0_instr_i0_s3_v; + input rv0_instr_i0_s3_dep_hit; + input [0:`ITAG_SIZE_ENC-1] rv0_instr_i0_s3_itag; + input rv0_instr_i0_is_brick; + input [0:2] rv0_instr_i0_brick; + input [0:3] rv0_instr_i0_ilat; + + input [0:q_dat_width_g-1] rv0_instr_i1_dat; + input [0:q_dat_ex0_width_g-1] rv0_instr_i1_dat_ex0; + input [0:`ITAG_SIZE_ENC-1] rv0_instr_i1_itag; + input rv0_instr_i1_ord; + input rv0_instr_i1_cord; + input rv0_instr_i1_spec; + input rv0_instr_i1_s1_v; + input rv0_instr_i1_s1_dep_hit; + input [0:`ITAG_SIZE_ENC-1] rv0_instr_i1_s1_itag; + input rv0_instr_i1_s2_v; + input rv0_instr_i1_s2_dep_hit; + input [0:`ITAG_SIZE_ENC-1] rv0_instr_i1_s2_itag; + input rv0_instr_i1_s3_v; + input rv0_instr_i1_s3_dep_hit; + input [0:`ITAG_SIZE_ENC-1] rv0_instr_i1_s3_itag; + input rv0_instr_i1_is_brick; + input [0:2] rv0_instr_i1_brick; + input [0:3] rv0_instr_i1_ilat; + + input [0:`THREADS-1] fx0_rv_itag_vld; + input [0:`ITAG_SIZE_ENC-1] fx0_rv_itag; + input [0:`THREADS-1] fx1_rv_itag_vld; + input [0:`ITAG_SIZE_ENC-1] fx1_rv_itag; + input [0:`THREADS-1] axu0_rv_itag_vld; + input [0:`ITAG_SIZE_ENC-1] axu0_rv_itag; + input [0:`THREADS-1] axu1_rv_itag_vld; + input [0:`ITAG_SIZE_ENC-1] axu1_rv_itag; + input [0:`THREADS-1] lq_rv_itag0_vld; + input [0:`ITAG_SIZE_ENC-1] lq_rv_itag0; + input [0:`THREADS-1] lq_rv_itag1_vld; + input [0:`ITAG_SIZE_ENC-1] lq_rv_itag1; + input [0:`THREADS-1] lq_rv_itag2_vld; + input [0:`ITAG_SIZE_ENC-1] lq_rv_itag2; + + input fx0_rv_itag_abort; + input fx1_rv_itag_abort; + input axu0_rv_itag_abort; + input axu1_rv_itag_abort; + input lq_rv_itag0_abort; + input lq_rv_itag1_abort; + + + input lq_rv_itag1_restart; + input lq_rv_itag1_hold; + input lq_rv_itag1_cord; + input [0:`THREADS-1] lq_rv_itag1_rst_vld; + input [0:`ITAG_SIZE_ENC-1] lq_rv_itag1_rst; + input [0:`THREADS-1] lq_rv_clr_hold; + + input xx_rv_ex2_s1_abort; + input xx_rv_ex2_s2_abort; + input xx_rv_ex2_s3_abort; + + input q_hold_all; + input [0:`THREADS-1] q_ord_complete; + output [0:`THREADS-1] q_ord_tid; + + input [0:`THREADS-1] rv1_other_ilat0_vld; + input [0:`ITAG_SIZE_ENC-1] rv1_other_ilat0_itag; + output [0:`THREADS-1] rv1_other_ilat0_vld_out; + output [0:`ITAG_SIZE_ENC-1] rv1_other_ilat0_itag_out; + + output [0:`THREADS-1] rv1_instr_vld; + output [0:q_dat_width_g-1] rv1_instr_dat; + output rv1_instr_spec; + output rv1_instr_ord; + output [0:`ITAG_SIZE_ENC-1] rv1_instr_itag; + output [0:3] rv1_instr_ilat; + output [0:`THREADS-1] rv1_instr_ilat0_vld; + output [0:`THREADS-1] rv1_instr_ilat1_vld; + output [0:`ITAG_SIZE_ENC-1] rv1_instr_s1_itag; + output [0:`ITAG_SIZE_ENC-1] rv1_instr_s2_itag; + output [0:`ITAG_SIZE_ENC-1] rv1_instr_s3_itag; + output rv1_instr_is_brick; + output [0:q_dat_ex0_width_g-1] ex0_instr_dat; + output [0:`THREADS-1] ex1_credit_free; + output [0:`THREADS-1] rvs_empty; + output [0:8*`THREADS-1] rvs_perf_bus; + output [0:31] rvs_dbg_bus; + + + // pervasive + inout vdd; + inout gnd; + (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) // nclk + input [0:`NCLK_WIDTH-1] nclk; + input sg_1; + input func_sl_thold_1; + input ccflush_dc; + input act_dis; + input clkoff_b; + input d_mode; + input delay_lclkr; + input mpw1_b; + input mpw2_b; + input scan_in; + + output scan_out; + + + + //------------------------------------------------------------------------------------------------------- + // Type definitions + //------------------------------------------------------------------------------------------------------- + parameter q_ilat_width_g = 4; + + + + + wire [0:`THREADS-1] flush; + wire [0:`THREADS-1] flush2; + + wire sg_0; + wire func_sl_thold_0; + wire func_sl_thold_0_b; + wire force_t; + + wire rv0_load1; + wire rv0_load2; + wire rv0_load1_instr_select; + wire rv0_instr_i0_flushed; + wire rv0_instr_i1_flushed; + + wire rv0_instr_i0_s1_rdy; + wire rv0_instr_i0_s2_rdy; + wire rv0_instr_i0_s3_rdy; + wire rv0_instr_i1_s1_rdy; + wire rv0_instr_i1_s2_rdy; + wire rv0_instr_i1_s3_rdy; + + wire rv0_i0_s1_itag_clear; + wire rv0_i0_s2_itag_clear; + wire rv0_i0_s3_itag_clear; + wire rv0_i1_s1_itag_clear; + wire rv0_i1_s2_itag_clear; + wire rv0_i1_s3_itag_clear; + + wire rv0_i0_s1_itag_abort; + wire rv0_i0_s2_itag_abort; + wire rv0_i0_s3_itag_abort; + wire rv0_i1_s1_itag_abort; + wire rv0_i1_s2_itag_abort; + wire rv0_i1_s3_itag_abort; + + wire [0:`THREADS-1] rv0_instr_i0_tid; + wire [0:`THREADS-1] rv0_instr_i1_tid; + + wire lq_rv_itag1_restart_q; + wire lq_rv_itag1_hold_q; + wire lq_rv_itag1_cord_q; + wire [0:`THREADS-1] lq_rv_clr_hold_q; + wire [0:`THREADS-1] lq_rv_itag1_rst_vld_q; + wire [0:`ITAG_SIZE_ENC-1] lq_rv_itag1_rst_q; + + + // reservation station entry elements + wire [0:q_num_entries_g-1] q_ev_b; + wire [0:q_num_entries_g-1] q_ev_d; + wire [0:q_num_entries_g-1] q_ev_q; + wire [0:q_num_entries_g-1] q_ord_d; + wire [0:q_num_entries_g-1] q_ord_q; + wire [0:q_num_entries_g-1] q_cord_d; + wire [0:q_num_entries_g-1] q_cord_q; + wire [0:`ITAG_SIZE_ENC-1] q_itag_d[0:q_num_entries_g-1]; + wire [0:`ITAG_SIZE_ENC-1] q_itag_q[0:q_num_entries_g-1]; + wire [0:q_num_entries_g-1] q_is_brick_d; + wire [0:q_num_entries_g-1] q_is_brick_q; + wire [0:`THREADS-1] q_tid_d[0:q_num_entries_g-1]; + wire [0:`THREADS-1] q_tid_q[0:q_num_entries_g-1]; + wire [0:2] q_brick_d[0:q_num_entries_g-1]; + wire [0:2] q_brick_q[0:q_num_entries_g-1]; + wire [0:3] q_ilat_d[0:q_num_entries_g-1]; + wire [0:3] q_ilat_q[0:q_num_entries_g-1]; + wire [0:q_num_entries_g-1] q_spec_d; + wire [0:q_num_entries_g-1] q_spec_q; + wire [0:q_num_entries_g-1] q_s1_v_d; + wire [0:q_num_entries_g-1] q_s1_v_q; + wire [0:`ITAG_SIZE_ENC-1] q_s1_itag_d[0:q_num_entries_g-1]; + wire [0:`ITAG_SIZE_ENC-1] q_s1_itag_q[0:q_num_entries_g-1]; + wire [0:q_num_entries_g-1] q_s2_v_d; + wire [0:q_num_entries_g-1] q_s2_v_q; + wire [0:`ITAG_SIZE_ENC-1] q_s2_itag_d[0:q_num_entries_g-1]; + wire [0:`ITAG_SIZE_ENC-1] q_s2_itag_q[0:q_num_entries_g-1]; + wire [0:q_num_entries_g-1] q_s3_v_d; + wire [0:q_num_entries_g-1] q_s3_v_q; + wire [0:`ITAG_SIZE_ENC-1] q_s3_itag_d[0:q_num_entries_g-1]; + wire [0:`ITAG_SIZE_ENC-1] q_s3_itag_q[0:q_num_entries_g-1]; + wire [0:q_num_entries_g-1] q_s1_rdy_d; + wire [0:q_num_entries_g-1] q_s1_rdy_q; + wire [0:q_num_entries_g-1] q_s2_rdy_d; + wire [0:q_num_entries_g-1] q_s2_rdy_q; + wire [0:q_num_entries_g-1] q_s3_rdy_d; + wire [0:q_num_entries_g-1] q_s3_rdy_q; + wire [0:q_num_entries_g-1] q_rdy_d; + wire [0:q_num_entries_g-1] q_rdy_q; + wire [0:q_num_entries_g-1] q_rdy_qb; + wire [0:q_num_entries_g-1] q_issued_d; + wire [0:q_num_entries_g-1] q_issued_q; + wire [0:q_num_entries_g-1] q_e_miss_d; + wire [0:q_num_entries_g-1] q_e_miss_q; + wire [0:q_dat_width_g-1] q_dat_d[0:q_num_entries_g-1]; + wire [0:q_dat_width_g-1] q_dat_q[0:q_num_entries_g-1]; + wire [0:q_num_entries_g-1] q_flushed_d; + wire [0:q_num_entries_g-1] q_flushed_q; + wire [0:q_num_entries_g-1] q_flushed_nxt; + + // reservation station set/clr/nxt signals + wire [0:q_num_entries_g-1] q_ev_clr; + wire [0:q_num_entries_g-1] q_ev_nxt; + wire [0:q_num_entries_g-1] q_ord_nxt; + wire [0:q_num_entries_g-1] q_cord_set; + wire [0:q_num_entries_g-1] q_cord_nxt; + wire [0:q_num_entries_g-1] q_spec_clr; + wire [0:q_num_entries_g-1] q_spec_nxt; + wire [0:q_num_entries_g-1] q_sx_rdy_nxt; + wire [0:q_num_entries_g-1] q_s1_rdy_sets; + wire [0:q_num_entries_g-1] q_s2_rdy_sets; + wire [0:q_num_entries_g-1] q_s3_rdy_sets; + wire [0:q_num_entries_g-1] q_s1_rdy_setf; + wire [0:q_num_entries_g-1] q_s2_rdy_setf; + wire [0:q_num_entries_g-1] q_s3_rdy_setf; + wire [0:q_num_entries_g-1] q_s1_rdy_clr; + wire [0:q_num_entries_g-1] q_s1_rdy_nxt; + wire [0:q_num_entries_g-1] q_s2_rdy_clr; + wire [0:q_num_entries_g-1] q_s2_rdy_nxt; + wire [0:q_num_entries_g-1] q_s3_rdy_clr; + wire [0:q_num_entries_g-1] q_s3_rdy_nxt; + wire q_i0_s_rdy; + wire q_i1_s_rdy; + wire [0:q_num_entries_g-1] q_rdy_set; + wire [0:q_num_entries_g-1] q_rdy_nxt; + wire [4:q_num_entries_g-1] q_issued_set; + wire [4:q_num_entries_g-1] q_issued_clr; + wire [0:q_num_entries_g-1] q_issued_nxt; + wire [0:q_num_entries_g-1] q_e_miss_set; + wire [0:q_num_entries_g-1] q_e_miss_clr; + wire [0:q_num_entries_g-1] q_e_miss_nxt; + + // itag match signals + wire [0:q_num_entries_g-1] q_lq_itag_match; + wire [0:q_num_entries_g-1] q_ilat0_match_s1; + wire [0:q_num_entries_g-1] q_ilat0_match_s2; + wire [0:q_num_entries_g-1] q_ilat0_match_s3; + wire [0:q_num_entries_g-1] q_other_ilat0_match_s1; + wire [0:q_num_entries_g-1] q_other_ilat0_match_s2; + wire [0:q_num_entries_g-1] q_other_ilat0_match_s3; + wire [0:q_num_entries_g-1] q_xx_itag_clear_s1; + wire [0:q_num_entries_g-1] q_xx_itag_clear_s2; + wire [0:q_num_entries_g-1] q_xx_itag_clear_s3; + wire [0:q_num_entries_g-1] q_xx_itag_abort_s1; + wire [0:q_num_entries_g-1] q_xx_itag_abort_s2; + wire [0:q_num_entries_g-1] q_xx_itag_abort_s3; + + // entry rdy/select/etc signals + wire [4:q_num_entries_g-1] q_entry_rdy; + wire [4:q_num_entries_g-1] q_entry_rdy_l1_b; + wire [4:q_num_entries_g-1] q_entry_rdy_l2a; + wire [4:q_num_entries_g-1] q_entry_rdy_l2b; + wire [4:q_num_entries_g-1] q_entry_rdy_l2c; + + wire [4:q_num_entries_g-1] q_entry_rdy_pri; + wire [4:q_num_entries_g-1] q_entry_select; + wire [0:q_num_entries_g-1] q_entry_or_tree; + wire [0:q_num_entries_g-1] q_entry_and_tree; + + wire [0:`THREADS-1] q_entry_ilat0[4:q_num_entries_g-1]; + wire [0:`THREADS-1] q_entry_ilat1[4:q_num_entries_g-1]; + wire [0:q_dat_width_g-1] q_instr_dat; + wire [0:`THREADS-1] q_instr_vld; + wire [0:`THREADS-1] q_instr_ilat0_vld; + wire [0:`THREADS-1] q_instr_ilat0_vld_l1a_b; + wire [0:`THREADS-1] q_instr_ilat0_vld_l1b_b; + wire [0:`THREADS-1] q_instr_ilat0_vld_rp; + wire [0:`THREADS-1] q_instr_ilat1_vld; + wire q_instr_is_brick; + wire [0:2] q_instr_brick; + wire [0:`ITAG_SIZE_ENC-1] q_instr_itag; + wire [0:`ITAG_SIZE_ENC-1] q_instr_itag_rp; + wire [0:`ITAG_SIZE_ENC-1] q_instr_itag_l1a_b; + wire [0:`ITAG_SIZE_ENC-1] q_instr_itag_l1b_b; + wire [0:`ITAG_SIZE_ENC-1] q_instr_s1_itag; + wire [0:`ITAG_SIZE_ENC-1] q_instr_s2_itag; + wire [0:`ITAG_SIZE_ENC-1] q_instr_s3_itag; + wire [0:`THREADS-1] q_instr_ilat0; + wire [0:`THREADS-1] q_instr_ilat1; + wire [0:`THREADS-1] q_tid_vld; + // hold signals + wire q_hold_all_d; + wire q_hold_all_q; + wire [0:`THREADS-1] q_ord_completed; + wire [0:`THREADS-1] q_hold_ord_d; + wire [0:`THREADS-1] q_hold_ord_q; + wire q_hold_brick_d; + wire q_hold_brick_q; + wire q_hold_brick; + wire [0:2] q_hold_brick_cnt_d; + wire [0:2] q_hold_brick_cnt_q; + wire [0:`THREADS-1] q_hold_ord_set; + wire q_cord_match; + wire [0:`ITAG_SIZE_ENC-1] q_cp_next_itag; + + //credit release + wire [0:q_num_entries_g-1] q_credit_d; + wire [0:q_num_entries_g-1] q_credit_q; + wire [0:q_num_entries_g-1] q_credit_nxt; + wire [0:q_num_entries_g-1] q_credit_rdy; + wire [0:q_num_entries_g-1] q_credit_set; + wire [0:q_num_entries_g-1] q_credit_clr; + wire [0:q_num_entries_g-1] q_credit_take; + wire [0:q_num_entries_g-1] q_credit_ex3; + wire [0:q_num_entries_g-1] q_credit_ex6; + wire [0:q_num_entries_g-1] q_credit_flush; + + wire [0:`THREADS-1] ex1_credit_free_d; + wire [0:`THREADS-1] ex1_credit_free_q; + + wire [0:`THREADS-1] q_entry_tvld[0:q_num_entries_g-1]; + wire [0:q_num_entries_g-1] q_entry_tvld_rev[0:`THREADS-1]; + wire [0:`THREADS-1] rvs_empty_d; + wire [0:`THREADS-1] rvs_empty_q; + + //load/shift signals + wire [0:q_num_entries_g-1] q_entry_load; + wire [0:q_num_entries_g-1] q_entry_load2; + wire [0:q_num_entries_g-1] q_entry_load_i0; + wire [0:q_num_entries_g-1] q_entry_load_i1; + wire [0:q_num_entries_g-1] q_entry_shift; + wire [0:q_num_entries_g-1] q_entry_hold; + wire [0:q_num_entries_g-1] q_cord_act; + wire [0:q_num_entries_g-1] q_dat_act; + wire [0:q_num_entries_g-1] q_e_miss_act; + + wire [0:3] issued_addr; + wire [0:q_num_entries_g-1] issued_shift[0:3]; + wire [0:3] issued_addr_d[0:4]; + wire [0:3] issued_addr_q[0:4]; + wire [0:`THREADS-1] issued_vld_d[0:4]; + wire [0:`THREADS-1] issued_vld_q[0:4]; + wire xx_rv_ex2_abort; + wire xx_rv_ex3_abort; + wire xx_rv_ex4_abort; + + + wire [0:q_num_entries_g-1] ex3_instr_issued; + wire [0:q_num_entries_g-1] ex4_instr_issued; + (* analysis_not_referenced="<0:3>true" *) + wire [0:q_num_entries_g-1] ex4_instr_aborted; + + wire w0_en; + wire w1_en; + wire [0:q_num_entries_g] w_act; + + wire [0:`THREADS-1] rv0_w0_en; + wire [0:`THREADS-1] rv0_w1_en; + wire [0:`THREADS-1] barf_ev_d[0:q_num_entries_g]; + wire [0:`THREADS-1] barf_ev_q[0:q_num_entries_g]; + wire [0:q_num_entries_g] barf_w0_ev_b; + wire [0:q_num_entries_g] barf_w1_ev_b; + wire [0:q_num_entries_g] barf_w0_or_tree; + wire [0:q_num_entries_g] barf_w1_or_tree; + wire [0:q_num_entries_g] rv0_w0_addr; + wire [0:q_num_entries_g] rv0_w1_addr; + wire [0:q_barf_enc_g-1] rv0_w0_addr_enc; + wire [0:q_barf_enc_g-1] rv0_w1_addr_enc; + wire [0:q_barf_enc_g-1] ex0_barf_addr_d; + wire [0:q_barf_enc_g-1] ex0_barf_addr_q; + wire [0:q_barf_enc_g-1] barf_clr_addr; + wire [0:q_num_entries_g] q_barf_clr; + wire [0:q_barf_enc_g-1] q_barf_addr_d[0:q_num_entries_g-1]; + wire [0:q_barf_enc_g-1] q_barf_addr_q[0:q_num_entries_g-1]; + + wire [0:`THREADS-1] xx_rv_rel_vld_d[0:q_itag_busses_g-1]; + wire [0:`THREADS-1] xx_rv_rel_vld_q[0:q_itag_busses_g-1]; + wire [0:q_itag_busses_g-1] xx_rv_abort_d; + wire [0:q_itag_busses_g-1] xx_rv_abort_q; + wire [0:`ITAG_SIZE_ENC-1] xx_rv_rel_itag_d[0:q_itag_busses_g-1]; + wire [0:`ITAG_SIZE_ENC-1] xx_rv_rel_itag_q[0:q_itag_busses_g-1]; + + wire [4*q_dat_width_g:q_dat_width_g*q_num_entries_g-1] q_dat_ary; + wire [4*`THREADS:`THREADS*q_num_entries_g-1] q_tid_ary; + wire [4*3:3*q_num_entries_g-1] q_brick_ary; + wire [4*`THREADS:`THREADS*q_num_entries_g-1] q_ilat0_ary; + wire [4*`THREADS:`THREADS*q_num_entries_g-1] q_ilat1_ary; + wire [4*`ITAG_SIZE_ENC:`ITAG_SIZE_ENC*q_num_entries_g-1] q_itag_ary; + wire [4*`ITAG_SIZE_ENC:`ITAG_SIZE_ENC*q_num_entries_g-1] q_s1_itag_ary; + wire [4*`ITAG_SIZE_ENC:`ITAG_SIZE_ENC*q_num_entries_g-1] q_s2_itag_ary; + wire [4*`ITAG_SIZE_ENC:`ITAG_SIZE_ENC*q_num_entries_g-1] q_s3_itag_ary; + wire [4*q_ilat_width_g:q_ilat_width_g*q_num_entries_g-1] q_ilat_ary; + wire [4*q_barf_enc_g:q_barf_enc_g*q_num_entries_g-1] q_barf_addr_ary; + wire [0 :q_barf_enc_g*q_num_entries_g-1] q_barf_clr_addr_ary; + wire [0:`THREADS*q_num_entries_g-1] q_tid_full_ary; + + wire [0:q_itag_busses_g*`THREADS-1] xx_rv_itag_vld_ary; + wire [0:q_itag_busses_g*(`ITAG_SIZE_ENC)-1] xx_rv_itag_ary; + + wire [0:8*`THREADS-1] perf_bus_d; + wire [0:8*`THREADS-1] perf_bus_q; + + wire [0:31] dbg_bus_d; + wire [0:31] dbg_bus_q; + + (* analysis_not_referenced="true" *) + wire no_lq_unused; + (* analysis_not_referenced="true" *) + wire brick_unused; + (* analysis_not_referenced="true" *) + wire [0:q_num_entries_g-1] brickn_unused; + + wire tiup; + + //------------------------------------------------------------------- + // Scanchain + //------------------------------------------------------------------- + parameter barf_offset = 0; + parameter barf_ev_offset = barf_offset + 1; + parameter ex0_barf_addr_offset = barf_ev_offset + (q_num_entries_g+1)* `THREADS; + parameter issued_vld_offset =ex0_barf_addr_offset + q_barf_enc_g; + parameter issued_addr_offset =issued_vld_offset + 5*`THREADS; + parameter xx_rv_ex3_abort_offset = issued_addr_offset + 5*4; + parameter xx_rv_ex4_abort_offset = xx_rv_ex3_abort_offset + 1; + parameter flush_reg_offset = xx_rv_ex4_abort_offset + 1; + parameter flush2_reg_offset = flush_reg_offset + `THREADS; + parameter q_dat_offset = flush2_reg_offset + `THREADS; + parameter q_itag_offset = q_dat_offset + q_num_entries_g * q_dat_width_g; + parameter q_brick_offset = q_itag_offset + q_num_entries_g * `ITAG_SIZE_ENC; + parameter q_ilat_offset = q_brick_offset + q_num_entries_g * 3; + parameter q_barf_addr_offset = q_ilat_offset + q_num_entries_g * 4; + parameter q_tid_offset = q_barf_addr_offset + q_num_entries_g * q_barf_enc_g; + parameter q_s1_itag_offset = q_tid_offset + q_num_entries_g * `THREADS; + parameter q_s2_itag_offset = q_s1_itag_offset + q_num_entries_g * `ITAG_SIZE_ENC; + parameter q_s3_itag_offset = q_s2_itag_offset + q_num_entries_g * `ITAG_SIZE_ENC; + parameter lq_rv_itag1_restart_offset = q_s3_itag_offset + q_num_entries_g * `ITAG_SIZE_ENC; + parameter lq_rv_itag1_hold_offset = lq_rv_itag1_restart_offset + 1; + parameter lq_rv_itag1_cord_offset = lq_rv_itag1_hold_offset + 1; + parameter lq_rv_clr_hold_offset = lq_rv_itag1_cord_offset + 1; + parameter lq_rv_itag1_rst_vld_offset = lq_rv_clr_hold_offset + `THREADS; + parameter lq_rv_itag1_rst_offset = lq_rv_itag1_rst_vld_offset + `THREADS; + parameter xx_rv_rel_vld_offset = lq_rv_itag1_rst_offset + `ITAG_SIZE_ENC; + parameter xx_rv_rel_itag_offset = xx_rv_rel_vld_offset + q_itag_busses_g * `THREADS; + parameter xx_rv_abort_offset = xx_rv_rel_itag_offset + q_itag_busses_g * `ITAG_SIZE_ENC; + parameter q_ev_offset = xx_rv_abort_offset + q_itag_busses_g; + parameter q_flushed_offset = q_ev_offset + q_num_entries_g; + parameter q_credit_offset = q_flushed_offset + q_num_entries_g; + parameter ex1_credit_free_offset = q_credit_offset + q_num_entries_g; + parameter rvs_empty_offset = ex1_credit_free_offset + `THREADS; + parameter q_ord_offset = rvs_empty_offset + `THREADS; + parameter q_cord_offset = q_ord_offset + q_num_entries_g; + parameter q_is_brick_offset = q_cord_offset + q_num_entries_g; + parameter q_spec_offset = q_is_brick_offset + q_num_entries_g; + parameter q_s1_v_offset = q_spec_offset + q_num_entries_g; + parameter q_s2_v_offset = q_s1_v_offset + q_num_entries_g; + parameter q_s3_v_offset = q_s2_v_offset + q_num_entries_g; + parameter q_s1_rdy_offset = q_s3_v_offset + q_num_entries_g; + parameter q_s2_rdy_offset = q_s1_rdy_offset + q_num_entries_g; + parameter q_s3_rdy_offset = q_s2_rdy_offset + q_num_entries_g; + parameter q_rdy_offset = q_s3_rdy_offset + q_num_entries_g; + parameter q_issued_offset = q_rdy_offset + q_num_entries_g; + parameter q_e_miss_offset = q_issued_offset + q_num_entries_g; + parameter q_hold_all_offset = q_e_miss_offset + q_num_entries_g; + parameter q_hold_ord_offset = q_hold_all_offset + 1; + parameter q_hold_brick_offset = q_hold_ord_offset + `THREADS; + parameter q_hold_brick_cnt_offset = q_hold_brick_offset + 1; + parameter perf_bus_offset = q_hold_brick_cnt_offset + 3; + parameter dbg_bus_offset = perf_bus_offset + 8*`THREADS; + + parameter scan_right = dbg_bus_offset + 32; + + wire [0:scan_right-1] siv; + wire [0:scan_right-1] sov; + + genvar n; + genvar t; + genvar i; + + + + //------------------------------------------------------------------------------------------------------- + // Bugspray + //------------------------------------------------------------------------------------------------------- + //!! Bugspray Include: rv_station; + + //------------------------------------------------------------------------------------------------------- + // misc + //------------------------------------------------------------------------------------------------------- + assign tiup = 1'b1; + + //------------------------------------------------------------------------------------------------------- + // Barf array. Data not needed until EX0 + //------------------------------------------------------------------------------------------------------- + + + rv_barf #(.q_dat_width_g(q_dat_ex0_width_g), .q_num_entries_g(q_num_entries_g+1), .q_barf_enc_g(q_barf_enc_g) ) + barf( + .w0_dat(rv0_instr_i0_dat_ex0), + .w0_addr(rv0_w0_addr_enc), + .w0_en(w0_en), + .w1_dat(rv0_instr_i1_dat_ex0), + .w1_addr(rv0_w1_addr_enc), + .w1_en(w1_en), + .w_act(w_act), + .r0_addr(ex0_barf_addr_q), + .r0_dat(ex0_instr_dat), + .nclk(nclk), + .vdd(vdd), + .gnd(gnd), + .sg_1(sg_1), + .func_sl_thold_1(func_sl_thold_1), + .ccflush_dc(ccflush_dc), + .act_dis(act_dis), + .clkoff_b(clkoff_b), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .scan_in(siv[barf_offset]), + .scan_out(sov[barf_offset]) + ); + + assign rv0_w0_en = {`THREADS{rv0_instr_i0_rte}} & rv0_instr_i0_vld & ~({`THREADS{&flush2}}) ; + assign rv0_w1_en = {`THREADS{rv0_instr_i1_rte}} & rv0_instr_i1_vld & ~({`THREADS{&flush2}}) ; + + assign w0_en = |rv0_w0_en; + assign w1_en = |rv0_w1_en; + assign w_act = (rv0_w0_addr | rv0_w1_addr) & {q_num_entries_g+1{(rv0_instr_i0_rte | rv0_instr_i1_rte)}}; + + + generate + begin : xhdlbbar + for (n = 0; n <= (q_num_entries_g ); n = n + 1) + begin : genaddr + wire [0:q_barf_enc_g-1] id=n; + + assign barf_w0_ev_b[n] = ~(|(barf_ev_q[n])); + assign barf_w1_ev_b[n] = ~(|(barf_ev_q[n])); + + assign barf_w0_or_tree[n] = |(barf_w0_ev_b[n:q_num_entries_g]); + assign barf_w1_or_tree[n] = |(barf_w1_ev_b[0:n]); + + //Mark the entry valid if it was written + assign barf_ev_d[n] = ((rv0_w0_en & {`THREADS{rv0_w0_addr[n]}}) | + (rv0_w1_en & {`THREADS{rv0_w1_addr[n]}}) | + (barf_ev_q[n] & ~{`THREADS{q_barf_clr[n]}}) ) & ~({`THREADS{&flush}}) ; + + //Clear logic + assign q_barf_clr[n] = |q_credit_rdy & (barf_clr_addr==id); + + + end // block: genaddr + if(q_num_entries_g==12) + begin : baenc12 + assign rv0_w0_addr_enc[0]= rv0_w0_addr[ 8]|rv0_w0_addr[ 9]|rv0_w0_addr[10]|rv0_w0_addr[11]|rv0_w0_addr[12]; + assign rv0_w0_addr_enc[1]= rv0_w0_addr[ 4]|rv0_w0_addr[ 5]|rv0_w0_addr[ 6]|rv0_w0_addr[ 7]|rv0_w0_addr[12]; + assign rv0_w0_addr_enc[2]= rv0_w0_addr[ 2]|rv0_w0_addr[ 3]|rv0_w0_addr[ 6]|rv0_w0_addr[ 7]| + rv0_w0_addr[10]|rv0_w0_addr[11]; + assign rv0_w0_addr_enc[3]= rv0_w0_addr[ 1]|rv0_w0_addr[ 3]|rv0_w0_addr[ 5]|rv0_w0_addr[ 7]| + rv0_w0_addr[ 9]|rv0_w0_addr[11]; + assign rv0_w1_addr_enc[0]= rv0_w1_addr[ 8]|rv0_w1_addr[ 9]|rv0_w1_addr[10]|rv0_w1_addr[11]|rv0_w1_addr[12]; + assign rv0_w1_addr_enc[1]= rv0_w1_addr[ 4]|rv0_w1_addr[ 5]|rv0_w1_addr[ 6]|rv0_w1_addr[ 7]|rv0_w1_addr[12]; + assign rv0_w1_addr_enc[2]= rv0_w1_addr[ 2]|rv0_w1_addr[ 3]|rv0_w1_addr[ 6]|rv0_w1_addr[ 7]| + rv0_w1_addr[10]|rv0_w1_addr[11]; + assign rv0_w1_addr_enc[3]= rv0_w1_addr[ 1]|rv0_w1_addr[ 3]|rv0_w1_addr[ 5]|rv0_w1_addr[ 7]| + rv0_w1_addr[ 9]|rv0_w1_addr[11]; + end + else + begin : baenc16 + assign rv0_w0_addr_enc[0]= rv0_w0_addr[16]; + assign rv0_w0_addr_enc[1]= rv0_w0_addr[ 8]|rv0_w0_addr[ 9]|rv0_w0_addr[10]|rv0_w0_addr[11]| + rv0_w0_addr[12]|rv0_w0_addr[13]|rv0_w0_addr[14]|rv0_w0_addr[15]; + assign rv0_w0_addr_enc[2]= rv0_w0_addr[ 4]|rv0_w0_addr[ 5]|rv0_w0_addr[ 6]|rv0_w0_addr[ 7]| + rv0_w0_addr[12]|rv0_w0_addr[13]|rv0_w0_addr[14]|rv0_w0_addr[15]; + assign rv0_w0_addr_enc[3]= rv0_w0_addr[ 2]|rv0_w0_addr[ 3]|rv0_w0_addr[ 6]|rv0_w0_addr[ 7]| + rv0_w0_addr[10]|rv0_w0_addr[11]|rv0_w0_addr[14]|rv0_w0_addr[15]; + assign rv0_w0_addr_enc[4]= rv0_w0_addr[ 1]|rv0_w0_addr[ 3]|rv0_w0_addr[ 5]|rv0_w0_addr[ 7]| + rv0_w0_addr[ 9]|rv0_w0_addr[11]|rv0_w0_addr[13]|rv0_w0_addr[15]; + assign rv0_w1_addr_enc[0]= rv0_w1_addr[16]; + assign rv0_w1_addr_enc[1]= rv0_w1_addr[ 8]|rv0_w1_addr[ 9]|rv0_w1_addr[10]|rv0_w1_addr[11]| + rv0_w1_addr[12]|rv0_w1_addr[13]|rv0_w1_addr[14]|rv0_w1_addr[15]; + assign rv0_w1_addr_enc[2]= rv0_w1_addr[ 4]|rv0_w1_addr[ 5]|rv0_w1_addr[ 6]|rv0_w1_addr[ 7]| + rv0_w1_addr[12]|rv0_w1_addr[13]|rv0_w1_addr[14]|rv0_w1_addr[15]; + assign rv0_w1_addr_enc[3]= rv0_w1_addr[ 2]|rv0_w1_addr[ 3]|rv0_w1_addr[ 6]|rv0_w1_addr[ 7]| + rv0_w1_addr[10]|rv0_w1_addr[11]|rv0_w1_addr[14]|rv0_w1_addr[15]; + assign rv0_w1_addr_enc[4]= rv0_w1_addr[ 1]|rv0_w1_addr[ 3]|rv0_w1_addr[ 5]|rv0_w1_addr[ 7]| + rv0_w1_addr[ 9]|rv0_w1_addr[11]|rv0_w1_addr[13]|rv0_w1_addr[15]; + end + + end + endgenerate + assign rv0_w0_addr[0] = barf_w0_or_tree[0] & ~barf_w0_or_tree[1]; + assign rv0_w1_addr[0] = barf_w1_or_tree[0]; + generate + begin : xhdlbbar2 + for (n = 1; n <= (q_num_entries_g - 1); n = n + 1) + begin : genaddr2 + + assign rv0_w0_addr[n] = barf_w0_or_tree[n] & ~barf_w0_or_tree[n+1]; + assign rv0_w1_addr[n] = barf_w1_or_tree[n] & ~barf_w1_or_tree[n-1]; + + end + end + endgenerate + assign rv0_w0_addr[q_num_entries_g] = barf_w0_or_tree[q_num_entries_g]; + assign rv0_w1_addr[q_num_entries_g] = barf_w1_or_tree[q_num_entries_g] & ~barf_w1_or_tree[q_num_entries_g-1]; + + //------------------------------------------------------------------------------------------------------- + // Compute instruction bus controls in RV0 + //------------------------------------------------------------------------------------------------------- + assign rv0_load1 = (rv0_instr_i0_rte | rv0_instr_i1_rte ) & (~(&(flush)) & ~(&(flush2))); + assign rv0_load2 = (rv0_instr_i0_rte & rv0_instr_i1_rte ) & (~(&(flush)) & ~(&(flush2))); + assign rv0_load1_instr_select = (rv0_instr_i1_rte ) & (~rv0_load2); + + + assign rv0_instr_i0_tid = rv0_instr_i0_vld; + assign rv0_instr_i1_tid = rv0_instr_i1_vld; + + assign rv0_instr_i0_flushed = |(rv0_instr_i0_vld & (flush | flush2)); + assign rv0_instr_i1_flushed = |(rv0_instr_i1_vld & (flush | flush2)); + + + //------------------------------------------------------------------------------------------------------- + // generation of logic to manage the q ev (entry valid) bits. + //------------------------------------------------------------------------------------------------------- + assign q_ev_d[0] = (q_entry_load_i1[0]) | (q_entry_load_i0[0]) | (1'b0 & q_entry_shift[0]) | (q_ev_nxt[0] & q_entry_hold[0]); + + generate + begin : xhdl1 + for (n = 1; n <= (q_num_entries_g - 1); n = n + 1) + begin : q_ev_gen + assign q_ev_d[n] = (q_entry_load_i1[n]) | (q_entry_load_i0[n]) | (q_ev_nxt[n - 1] & q_entry_shift[n]) | (q_ev_nxt[n] & q_entry_hold[n]); + end + end + endgenerate + + generate + begin : xhdl2 + for (n = 0; n <= (q_num_entries_g - 1); n = n + 1) + begin : q_ev_nxt_gen + assign q_ev_clr[n] = q_credit_take[n] | &(flush); + + assign q_ev_nxt[n] = q_ev_q[n] & (~q_ev_clr[n]); + end + end + endgenerate + + + //------------------------------------------------------------------------------------------------------- + // generation of the itag for this entry's cmd + //------------------------------------------------------------------------------------------------------- + assign q_itag_d[0] = (rv0_instr_i1_itag & {`ITAG_SIZE_ENC{q_entry_load_i1[0]}}) | + (rv0_instr_i0_itag & {`ITAG_SIZE_ENC{q_entry_load_i0[0]}}) | + (q_itag_q[0] & {`ITAG_SIZE_ENC{q_entry_hold[0]}}); + + generate + begin : xhdl7 + for (n = 1; n <= (q_num_entries_g - 1); n = n + 1) + begin : q_itag_gen + assign q_itag_d[n] = (rv0_instr_i1_itag & {`ITAG_SIZE_ENC{q_entry_load_i1[n]}}) | + (rv0_instr_i0_itag & {`ITAG_SIZE_ENC{q_entry_load_i0[n]}}) | + (q_itag_q[n - 1] & {`ITAG_SIZE_ENC{q_entry_shift[n]}}) | + (q_itag_q[n] & {`ITAG_SIZE_ENC{q_entry_hold[n]}}); + end + end + endgenerate + + + //------------------------------------------------------------------------------------------------------- + // generation of the tid for this entry's cmd + //------------------------------------------------------------------------------------------------------- + + assign q_tid_d[0] = ({`THREADS{q_entry_load_i1[0]}} & rv0_instr_i1_tid ) | + ({`THREADS{q_entry_load_i0[0]}} & rv0_instr_i0_tid ) | + ({`THREADS{q_entry_hold[0]}} & q_tid_q[0]); + generate + begin : xhdl10 + for (n = 1; n <= (q_num_entries_g - 1); n = n + 1) + begin : q_tid_gen + assign q_tid_d[n] = ({`THREADS{q_entry_load_i1[n]}} & rv0_instr_i1_tid ) | + ({`THREADS{q_entry_load_i0[n]}} & rv0_instr_i0_tid ) | + ({`THREADS{q_entry_shift[n]}} & q_tid_q[n - 1] ) | + ({`THREADS{q_entry_hold[n]}} & q_tid_q[n]); + end + end + endgenerate + + //------------------------------------------------------------------------------------------------------- + // generation of the flush for this entry's cmd + //------------------------------------------------------------------------------------------------------- + assign q_flushed_d[0] = (rv0_instr_i1_flushed & q_entry_load_i1[0]) | (rv0_instr_i0_flushed & q_entry_load_i0[0]) | (q_flushed_nxt[0] & q_entry_hold[0]); + + generate + begin : xhdl11 + for (n = 1; n <= (q_num_entries_g - 1); n = n + 1) + begin : q_flushed_gen + assign q_flushed_d[n] = (rv0_instr_i1_flushed & q_entry_load_i1[n]) | + (rv0_instr_i0_flushed & q_entry_load_i0[n]) | + (q_flushed_nxt[n - 1] & q_entry_shift[n]) | + (q_flushed_nxt[n] & q_entry_hold[n]); + end + end + endgenerate + + generate + begin : xhdl12 + for (n = 0; n <= (q_num_entries_g - 1); n = n + 1) + begin : q_flushed_nxt_gen + assign q_flushed_nxt[n] = q_ev_q[n] & |(q_tid_q[n] & ({`THREADS{q_flushed_q[n]}} | flush)); + end + end + endgenerate + + + //------------------------------------------------------------------------------------------------------- + // Save the ex0 indirect address + //------------------------------------------------------------------------------------------------------- + assign q_barf_addr_d[0] = (rv0_w0_addr_enc & {q_barf_enc_g{q_entry_load_i0[0]}}) | + (rv0_w1_addr_enc & {q_barf_enc_g{q_entry_load_i1[0]}}) | + (q_barf_addr_q[0] & {q_barf_enc_g{q_entry_hold[0]}}); + + generate + begin : xhdl11b + for (n = 1; n <= (q_num_entries_g - 1); n = n + 1) + begin : q_barf_addr_gen + assign q_barf_addr_d[n] = (rv0_w0_addr_enc & {q_barf_enc_g{q_entry_load_i0[n]}}) | + (rv0_w1_addr_enc & {q_barf_enc_g{q_entry_load_i1[n]}}) | + (q_barf_addr_q[n - 1] & {q_barf_enc_g{q_entry_shift[n]}}) | + (q_barf_addr_q[n] & {q_barf_enc_g{q_entry_hold[n]}}); + end + end + endgenerate + + //------------------------------------------------------------------------------------------------------- + // ILAT + //------------------------------------------------------------------------------------------------------- + + assign q_ilat_d[0] = ({q_ilat_width_g{q_entry_load_i1[0]}} & rv0_instr_i1_ilat ) | + ({q_ilat_width_g{q_entry_load_i0[0]}} & rv0_instr_i0_ilat ) | + ({q_ilat_width_g{q_entry_hold[0]}} & q_ilat_q[0]); + generate + begin : xhdl13 + for (n = 1; n <= (q_num_entries_g - 1); n = n + 1) + begin : q_ilat_gen + assign q_ilat_d[n] = ({q_ilat_width_g{q_entry_load_i1[n]}} & rv0_instr_i1_ilat ) | + ({q_ilat_width_g{q_entry_load_i0[n]}} & rv0_instr_i0_ilat ) | + ({q_ilat_width_g{q_entry_shift[n]}} & q_ilat_q[n - 1] ) | + ({q_ilat_width_g{q_entry_hold[n]}} & q_ilat_q[n]); + end + end + endgenerate + + + //------------------------------------------------------------------------------------------------------- + // generation of logic for the source valid fields that are present in each reservation station entry + //------------------------------------------------------------------------------------------------------- + assign q_s1_v_d[0] = (rv0_instr_i1_s1_v & q_entry_load_i1[0]) | + (rv0_instr_i0_s1_v & q_entry_load_i0[0]) | + (q_s1_v_q[0] & q_entry_hold[0]); + + assign q_s2_v_d[0] = (rv0_instr_i1_s2_v & q_entry_load_i1[0]) | + (rv0_instr_i0_s2_v & q_entry_load_i0[0]) | + (q_s2_v_q[0] & q_entry_hold[0]); + + assign q_s3_v_d[0] = (rv0_instr_i1_s3_v & q_entry_load_i1[0]) | + (rv0_instr_i0_s3_v & q_entry_load_i0[0]) | + (q_s3_v_q[0] & q_entry_hold[0]); + + generate + begin : xhdl16 + for (n = 1; n <= (q_num_entries_g - 1); n = n + 1) + begin : q_sv_gen + assign q_s1_v_d[n] = (rv0_instr_i1_s1_v & q_entry_load_i1[n]) | + (rv0_instr_i0_s1_v & q_entry_load_i0[n]) | + (q_s1_v_q[n - 1] & q_entry_shift[n]) | + (q_s1_v_q[n] & q_entry_hold[n]); + + assign q_s2_v_d[n] = (rv0_instr_i1_s2_v & q_entry_load_i1[n]) | + (rv0_instr_i0_s2_v & q_entry_load_i0[n]) | + (q_s2_v_q[n - 1] & q_entry_shift[n]) | + (q_s2_v_q[n] & q_entry_hold[n]); + + assign q_s3_v_d[n] = (rv0_instr_i1_s3_v & q_entry_load_i1[n]) | + (rv0_instr_i0_s3_v & q_entry_load_i0[n]) | + (q_s3_v_q[n - 1] & q_entry_shift[n]) | + (q_s3_v_q[n] & q_entry_hold[n]); + end + end + endgenerate + + //------------------------------------------------------------------------------------------------------- + // generation of logic for the dependent itags + //------------------------------------------------------------------------------------------------------- + + assign q_s1_itag_d[0] = (rv0_instr_i1_s1_itag & {`ITAG_SIZE_ENC{q_entry_load_i1[0]}}) | + (rv0_instr_i0_s1_itag & {`ITAG_SIZE_ENC{q_entry_load_i0[0]}}) | + (q_s1_itag_q[0] & {`ITAG_SIZE_ENC{q_entry_hold[0]}}); + + assign q_s2_itag_d[0] = (rv0_instr_i1_s2_itag & {`ITAG_SIZE_ENC{q_entry_load_i1[0]}}) | + (rv0_instr_i0_s2_itag & {`ITAG_SIZE_ENC{q_entry_load_i0[0]}}) | + (q_s2_itag_q[0] & {`ITAG_SIZE_ENC{q_entry_hold[0]}}); + + assign q_s3_itag_d[0] = (rv0_instr_i1_s3_itag & {`ITAG_SIZE_ENC{q_entry_load_i1[0]}}) | + (rv0_instr_i0_s3_itag & {`ITAG_SIZE_ENC{q_entry_load_i0[0]}}) | + (q_s3_itag_q[0] & {`ITAG_SIZE_ENC{q_entry_hold[0]}}); + + generate + begin : xhdl17 + for (n = 1; n <= (q_num_entries_g - 1); n = n + 1) + begin : q_sitag_gen + + assign q_s1_itag_d[n] = (rv0_instr_i1_s1_itag & {`ITAG_SIZE_ENC{q_entry_load_i1[n]}}) | + (rv0_instr_i0_s1_itag & {`ITAG_SIZE_ENC{q_entry_load_i0[n]}}) | + (q_s1_itag_q[n-1] & {`ITAG_SIZE_ENC{q_entry_shift[n]}}) | + (q_s1_itag_q[n] & {`ITAG_SIZE_ENC{q_entry_hold[n]}}); + + assign q_s2_itag_d[n] = (rv0_instr_i1_s2_itag & {`ITAG_SIZE_ENC{q_entry_load_i1[n]}}) | + (rv0_instr_i0_s2_itag & {`ITAG_SIZE_ENC{q_entry_load_i0[n]}}) | + (q_s2_itag_q[n-1] & {`ITAG_SIZE_ENC{q_entry_shift[n]}}) | + (q_s2_itag_q[n] & {`ITAG_SIZE_ENC{q_entry_hold[n]}}); + + assign q_s3_itag_d[n] = (rv0_instr_i1_s3_itag & {`ITAG_SIZE_ENC{q_entry_load_i1[n]}}) | + (rv0_instr_i0_s3_itag & {`ITAG_SIZE_ENC{q_entry_load_i0[n]}}) | + (q_s3_itag_q[n-1] & {`ITAG_SIZE_ENC{q_entry_shift[n]}}) | + (q_s3_itag_q[n] & {`ITAG_SIZE_ENC{q_entry_hold[n]}}); + + end + end + endgenerate + + //------------------------------------------------------------------------------------------------------- + // generation of source rdy logic + //-------------------------------------------------------------------------------------------------------lol + + assign q_s1_rdy_d[0] = (rv0_instr_i1_s1_rdy & q_entry_load_i1[0]) | + (rv0_instr_i0_s1_rdy & q_entry_load_i0[0]) | + (q_s1_rdy_nxt[0] & q_entry_hold[0] ); + assign q_s2_rdy_d[0] = (rv0_instr_i1_s2_rdy & q_entry_load_i1[0]) | + (rv0_instr_i0_s2_rdy & q_entry_load_i0[0]) | + (q_s2_rdy_nxt[0] & q_entry_hold[0] ); + assign q_s3_rdy_d[0] = (rv0_instr_i1_s3_rdy & q_entry_load_i1[0]) | + (rv0_instr_i0_s3_rdy & q_entry_load_i0[0]) | + (q_s3_rdy_nxt[0] & q_entry_hold[0] ); + + + generate + begin : xhdl20 + for (n = 1; n <= (q_num_entries_g - 1); n = n + 1) + begin : q_srdy_gen + assign q_s1_rdy_d[n] = (rv0_instr_i1_s1_rdy & q_entry_load_i1[n]) | + (rv0_instr_i0_s1_rdy & q_entry_load_i0[n]) | + (q_s1_rdy_nxt[n - 1] & q_entry_shift[n]) | + (q_s1_rdy_nxt[n] & q_entry_hold[n]); + assign q_s2_rdy_d[n] = (rv0_instr_i1_s2_rdy & q_entry_load_i1[n]) | + (rv0_instr_i0_s2_rdy & q_entry_load_i0[n]) | + (q_s2_rdy_nxt[n - 1] & q_entry_shift[n]) | + (q_s2_rdy_nxt[n] & q_entry_hold[n]); + assign q_s3_rdy_d[n] = (rv0_instr_i1_s3_rdy & q_entry_load_i1[n]) | + (rv0_instr_i0_s3_rdy & q_entry_load_i0[n]) | + (q_s3_rdy_nxt[n - 1] & q_entry_shift[n]) | + (q_s3_rdy_nxt[n] & q_entry_hold[n]); + end + end + endgenerate + + generate + begin : xhdl21 + for (n = 0; n <= (q_num_entries_g - 1); n = n + 1) + begin : q_srdy_nxt_gen + assign q_s1_rdy_setf[n] = (q_other_ilat0_match_s1[n] | q_ilat0_match_s1[n]); + assign q_s2_rdy_setf[n] = (q_other_ilat0_match_s2[n] | q_ilat0_match_s2[n]); + assign q_s3_rdy_setf[n] = (q_other_ilat0_match_s3[n] | q_ilat0_match_s3[n]); + assign q_s1_rdy_sets[n] = q_xx_itag_clear_s1[n] | q_s1_rdy_q[n] | ~q_s1_v_q[n]; + assign q_s2_rdy_sets[n] = q_xx_itag_clear_s2[n] | q_s2_rdy_q[n] | ~q_s2_v_q[n]; + assign q_s3_rdy_sets[n] = q_xx_itag_clear_s3[n] | q_s3_rdy_q[n] | ~q_s3_v_q[n]; + + assign q_s1_rdy_clr[n] = q_xx_itag_abort_s1[n] & q_s1_v_q[n]; + assign q_s2_rdy_clr[n] = q_xx_itag_abort_s2[n] & q_s2_v_q[n] ; + assign q_s3_rdy_clr[n] = q_xx_itag_abort_s3[n] & q_s3_v_q[n]; + + assign q_s1_rdy_nxt[n] = ((q_s1_rdy_setf[n] | q_s1_rdy_sets[n]) & (~q_s1_rdy_clr[n]) ) ; + assign q_s2_rdy_nxt[n] = ((q_s2_rdy_setf[n] | q_s2_rdy_sets[n]) & (~q_s2_rdy_clr[n]) ) ; + assign q_s3_rdy_nxt[n] = ((q_s3_rdy_setf[n] | q_s3_rdy_sets[n]) & (~q_s3_rdy_clr[n]) ) ; + + assign q_sx_rdy_nxt[n] = q_s1_rdy_nxt[n] & q_s2_rdy_nxt[n] & q_s3_rdy_nxt[n] ; + + end + end + endgenerate + + //------------------------------------------------------------------------------------------------------- + // generation of rdy logic + //------------------------------------------------------------------------------------------------------- + + assign q_i0_s_rdy = (rv0_instr_i0_s1_rdy) & (rv0_instr_i0_s2_rdy) & (rv0_instr_i0_s3_rdy) & ~(rv0_instr_i0_ord | rv0_instr_i0_cord | rv0_instr_i0_flushed); + assign q_i1_s_rdy = (rv0_instr_i1_s1_rdy) & (rv0_instr_i1_s2_rdy) & (rv0_instr_i1_s3_rdy) & ~(rv0_instr_i1_ord | rv0_instr_i1_cord | rv0_instr_i1_flushed); + + assign q_rdy_d[0] = (q_i1_s_rdy & q_entry_load_i1[0]) | + (q_i0_s_rdy & q_entry_load_i0[0]) | + (q_entry_hold[0] & q_rdy_nxt[0]); + + generate + begin : xhdl22 + for (n = 1; n <= (q_num_entries_g - 1); n = n + 1) + begin : q_rdy_gen + assign q_rdy_d[n] = (q_i1_s_rdy & q_entry_load_i1[n]) | + (q_i0_s_rdy & q_entry_load_i0[n]) | + (q_rdy_nxt[n - 1] & q_entry_shift[n]) | + (q_rdy_nxt[n] & q_entry_hold[n]); + end + end + endgenerate + + generate + begin : xhdl23 + for (n = 0; n <= (q_num_entries_g - 2); n = n + 1) + begin : q_rdy_nxt_gen + assign q_rdy_set[n] = ( (~q_e_miss_nxt[n])) & + ((~q_ord_q[n])) & ((~(q_cord_q[n] | q_cord_nxt[n]))) & + (~q_issued_nxt[n]) & (~q_flushed_nxt[n]) & q_ev_nxt[n]; + + assign q_rdy_nxt[n] = q_rdy_set[n] & q_sx_rdy_nxt[n]; + + end + end + endgenerate + + //Last Entry + assign q_rdy_set[q_num_entries_g - 1] = (~q_e_miss_nxt[q_num_entries_g - 1]) & + ((~q_ord_q[q_num_entries_g - 1]) | (q_ord_q[q_num_entries_g - 1] & ~(|(q_hold_ord_q)))) & + ((~q_cord_nxt[q_num_entries_g - 1]) | (q_cord_q[q_num_entries_g - 1] & q_cord_match)) & + (~q_issued_nxt[q_num_entries_g - 1]) & (~q_flushed_nxt[q_num_entries_g - 1]) & q_ev_nxt[q_num_entries_g - 1]; + + + assign q_rdy_nxt[q_num_entries_g - 1] = q_rdy_set[q_num_entries_g - 1] & q_sx_rdy_nxt[q_num_entries_g - 1]; + + + //------------------------------------------------------------------------------------------------------- + // generation of issued logic + //------------------------------------------------------------------------------------------------------- + assign q_issued_nxt[0:3] = 4'b0; + assign q_issued_d[0:3] = 4'b0; + + assign q_issued_d[4] = q_issued_nxt[4] & q_entry_hold[4]; + + generate + begin : xhdl24 + for (n = 5; n <= (q_num_entries_g - 1); n = n + 1) + begin : q_issued_gen + + assign q_issued_d[n] = (q_issued_nxt[n - 1] & q_entry_shift[n]) | + (q_issued_nxt[n] & q_entry_hold[n]); + end + end + endgenerate + + // If its not ready, its not issued nxt + generate + begin : xhdl25 + for (n = 4; n <= (q_num_entries_g - 1); n = n + 1) + begin : q_issued_nxt_gen + assign q_issued_set[n] = q_entry_select[n]; + + assign q_issued_clr[n] = (q_lq_itag_match[n] & q_spec_q[n] & lq_rv_itag1_restart_q) | + ((q_e_miss_q[n] | q_e_miss_nxt[n]) & q_spec_q[n]) | + (ex4_instr_aborted[n] ); + + assign q_issued_nxt[n] = (q_issued_q[n] | q_issued_set[n]) & (~q_issued_clr[n]); + end + end + endgenerate + + + //------------------------------------------------------------------------------------------------------- + // generation of the data field that is present in each reservation station entry + //------------------------------------------------------------------------------------------------------- + assign q_dat_d[0] = (rv0_instr_i1_dat & {q_dat_width_g{q_entry_load_i1[0]}}) | + (rv0_instr_i0_dat & {q_dat_width_g{q_entry_load_i0[0]}}) | + ({q_dat_width_g{1'b0}} & {q_dat_width_g{q_entry_shift[0]}}) | + (q_dat_q[0] & {q_dat_width_g{q_entry_hold[0]}}); //feedback + + generate + begin : xhdl28 + for (n = 1; n <= (q_num_entries_g - 1); n = n + 1) + begin : q_dat_gen + assign q_dat_d[n] = (rv0_instr_i1_dat & {q_dat_width_g{q_entry_load_i1[n]}}) | + (rv0_instr_i0_dat & {q_dat_width_g{q_entry_load_i0[n]}}) | + (q_dat_q[n - 1] & {q_dat_width_g{q_entry_shift[n]}}) | + (q_dat_q[n] & {q_dat_width_g{q_entry_hold[n]}}); //feedback + end + end + endgenerate + + //------------------------------------------------------------------------------------------------------- + // generation of q_entry_rdy logic. These are used after prioritization as mux selects to remove entries + //------------------------------------------------------------------------------------------------------- + generate + begin : xhdl29 + for (n = 4; n <= (q_num_entries_g - 1); n = n + 1) + begin : q_entry_rdy_gen + assign q_entry_rdy[n] = q_rdy_q[n] ; + + end + end + endgenerate + + // q_entry_rdy Fanout Tree + assign q_entry_rdy_l1_b = (~q_entry_rdy); + assign q_entry_rdy_l2a = (~q_entry_rdy_l1_b); + assign q_entry_rdy_l2b = (~q_entry_rdy_l1_b); + assign q_entry_rdy_l2c = (~q_entry_rdy_l1_b); + + //------------------------------------------------------------------------------------------------------- + // generation of ilat0 compare for zero bypass cases. Do it early for timing + //------------------------------------------------------------------------------------------------------- + generate + begin : xhdl30 + for (n = 4; n <= (q_num_entries_g - 1); n = n + 1) + begin : q_entry_ilat0_gen + assign q_entry_ilat0[n] = q_tid_q[n] & {`THREADS{(q_ilat_q[n] == 4'b0000) }}; + end + end + endgenerate + + generate + begin : xhdl31 + for (n = 4; n <= (q_num_entries_g - 1); n = n + 1) + begin : q_entry_ilat1_gen + assign q_entry_ilat1[n] = q_tid_q[n] & {`THREADS{(q_ilat_q[n] == 4'b0001) }}; + end + end + endgenerate + + //------------------------------------------------------------------------------------------------------- + // generation of q_entry_rdy_pri logic. These are the gates that represent the prioritization + // The prioritized result is gated with hold in order to be able to prevent an instruction + // from being selected + //------------------------------------------------------------------------------------------------------- + + rv_rpri #(.size(q_num_entries_g-4)) + q_rdy_pri( + .cond(q_entry_rdy), + .pri(q_entry_rdy_pri) + ); + + assign q_entry_select = ~(q_hold_all_q | q_hold_brick) ? q_entry_rdy_pri : {q_num_entries_g-4{1'b0}}; + + generate + begin : dat_extnd + for (n = 4; n <= (q_num_entries_g - 1); n = n + 1) + begin : dat_extnda + assign q_dat_ary[n*q_dat_width_g:(n+1)*q_dat_width_g-1] = q_dat_q[n]; + + end + end + endgenerate + + rv_primux #(.q_dat_width_g(q_dat_width_g), .q_num_entries_g(q_num_entries_g-4)) + q_dat_mux( + .cond(q_entry_rdy_l2c), + .din(q_dat_ary), + .dout(q_instr_dat) + ); + assign rv1_instr_dat = q_instr_dat; + + + generate + begin : tid_extnd + for (n = 4; n <= (q_num_entries_g - 1); n = n + 1) + begin : tid_extnda + assign q_tid_ary[n*`THREADS:(n+1)*`THREADS-1] = q_tid_q[n]; + + end + end + endgenerate + rv_prisel #(.q_dat_width_g(`THREADS), .q_num_entries_g(q_num_entries_g-4)) + q_vld_mux( + .cond(q_entry_rdy_l2b), + .din(q_tid_ary), + .dout(q_tid_vld) + ); + assign q_instr_vld = q_tid_vld & {`THREADS{(~(q_hold_all_q | q_hold_brick))}}; + assign rv1_instr_vld = q_instr_vld; + + assign q_instr_is_brick = |(q_entry_select & q_is_brick_q[4:q_num_entries_g-1]); + assign rv1_instr_is_brick = |(q_entry_rdy_pri & q_is_brick_q[4:q_num_entries_g-1]); + + generate + begin : brick_extnd + for (n = 4; n <= (q_num_entries_g - 1); n = n + 1) + begin : brick_extnda + assign q_brick_ary[n*3:(n+1)*3-1] = q_brick_q[n]; + + end + end + endgenerate + rv_primux #(.q_dat_width_g(3), .q_num_entries_g(q_num_entries_g-4)) + q_brick_mux( + .cond(q_entry_rdy_pri), + .din(q_brick_ary), + .dout(q_instr_brick) + ); + + assign rv1_instr_ord = |(q_entry_rdy_pri & q_ord_q[4:q_num_entries_g-1]); + + assign rv1_other_ilat0_vld_out = ~q_instr_ilat0_vld_l1a_b; + assign rv1_other_ilat0_itag_out = ~q_instr_itag_l1a_b; + + //------------------------------------------------------------------------------------------------------- + generate + begin : ilat0_extnd + for (n = 4; n <= (q_num_entries_g - 1); n = n + 1) + begin : ilat0_extnda + assign q_ilat0_ary[n*`THREADS:(n+1)*`THREADS-1] = q_entry_ilat0[n]; + + end + end + endgenerate + rv_prisel #(.q_dat_width_g(`THREADS), .q_num_entries_g(q_num_entries_g-4)) + q_ilat0_vld_mux( + .cond(q_entry_rdy_l2b), + .din(q_ilat0_ary), + .dout(q_instr_ilat0) + ); + + assign q_instr_ilat0_vld_rp = q_instr_ilat0 & q_instr_vld; + tri_inv #(.WIDTH(`THREADS)) q_itagvrp_l1a (q_instr_ilat0_vld_l1a_b, q_instr_ilat0_vld_rp); //ilat0_out + tri_inv #(.WIDTH(`THREADS)) q_itagvrp_l1b (q_instr_ilat0_vld_l1b_b, q_instr_ilat0_vld_rp); //everything else + + assign q_instr_ilat0_vld = ~q_instr_ilat0_vld_l1b_b; + + assign rv1_instr_ilat0_vld = q_instr_ilat0_vld; + + //------------------------------------------------------------------------------------------------------- + generate + begin : ilat1_extnd + for (n = 4; n <= (q_num_entries_g - 1); n = n + 1) + begin : ilat1_extnda + assign q_ilat1_ary[n*`THREADS:(n+1)*`THREADS-1] = q_entry_ilat1[n]; + + end + end + endgenerate + rv_prisel #(.q_dat_width_g(`THREADS), .q_num_entries_g(q_num_entries_g-4)) + q_ilat1_vld_mux( + .cond(q_entry_rdy_l2b), + .din(q_ilat1_ary), + .dout(q_instr_ilat1) + ); + + assign q_instr_ilat1_vld = q_instr_ilat1 & q_instr_vld; + assign rv1_instr_ilat1_vld = q_instr_ilat1_vld; + + //------------------------------------------------------------------------------------------------------- + generate + begin : itag_extnd + for (n = 4; n <= (q_num_entries_g - 1); n = n + 1) + begin : itag_extnda + assign q_itag_ary[n*`ITAG_SIZE_ENC:(n+1)*`ITAG_SIZE_ENC-1] = q_itag_q[n]; + + end + end + endgenerate + rv_primux #(.q_dat_width_g(`ITAG_SIZE_ENC), .q_num_entries_g(q_num_entries_g-4)) + q_itag_mux( + .cond(q_entry_rdy_l2b), + .din(q_itag_ary), + .dout(q_instr_itag_rp) + ); + + tri_inv #(.WIDTH(`ITAG_SIZE_ENC)) q_itagrp_l1a (q_instr_itag_l1a_b, q_instr_itag_rp); //ilat0_out + tri_inv #(.WIDTH(`ITAG_SIZE_ENC)) q_itagrp_l1b (q_instr_itag_l1b_b, q_instr_itag_rp); //everything else + + assign q_instr_itag = ~q_instr_itag_l1b_b; + + assign rv1_instr_itag = q_instr_itag; + + + //------------------------------------------------------------------------------------------------------- + generate + begin : s1_itag_extnd + for (n = 4; n <= (q_num_entries_g - 1); n = n + 1) + begin : s1_itag_extnda + assign q_s1_itag_ary[n*`ITAG_SIZE_ENC:(n+1)*`ITAG_SIZE_ENC-1] = q_s1_itag_q[n]; + + end + end + endgenerate + rv_primux #(.q_dat_width_g(`ITAG_SIZE_ENC), .q_num_entries_g(q_num_entries_g-4)) + q_s1_itag_mux( + .cond(q_entry_rdy_l2a), + .din(q_s1_itag_ary), + .dout(q_instr_s1_itag) + ); + assign rv1_instr_s1_itag = q_instr_s1_itag; + + //------------------------------------------------------------------------------------------------------- + generate + begin : s2_itag_extnd + for (n = 4; n <= (q_num_entries_g - 1); n = n + 1) + begin : s2_itag_extnda + assign q_s2_itag_ary[n*`ITAG_SIZE_ENC:(n+1)*`ITAG_SIZE_ENC-1] = q_s2_itag_q[n]; + + end + end + endgenerate + + rv_primux #(.q_dat_width_g(`ITAG_SIZE_ENC), .q_num_entries_g(q_num_entries_g-4)) + q_s2_itag_mux( + .cond(q_entry_rdy_l2a), + .din(q_s2_itag_ary), + .dout(q_instr_s2_itag) + ); + assign rv1_instr_s2_itag = q_instr_s2_itag; + + //------------------------------------------------------------------------------------------------------- + generate + begin : s3_itag_extnd + for (n = 4; n <= (q_num_entries_g - 1); n = n + 1) + begin : s3_itag_extnda + assign q_s3_itag_ary[n*`ITAG_SIZE_ENC:(n+1)*`ITAG_SIZE_ENC-1] = q_s3_itag_q[n]; + + end + end + endgenerate + + rv_primux #(.q_dat_width_g(`ITAG_SIZE_ENC), .q_num_entries_g(q_num_entries_g-4)) + q_s3_itag_mux( + .cond(q_entry_rdy_l2a), + .din(q_s3_itag_ary), + .dout(q_instr_s3_itag) + ); + assign rv1_instr_s3_itag = q_instr_s3_itag; + + //------------------------------------------------------------------------------------------------------- + generate + begin : ilat_extnd + for (n = 4; n <= (q_num_entries_g - 1); n = n + 1) + begin : ilat_extnda + assign q_ilat_ary[n*q_ilat_width_g:(n+1)*q_ilat_width_g-1] = q_ilat_q[n]; + + end + end + endgenerate + + rv_primux #(.q_dat_width_g(q_ilat_width_g), .q_num_entries_g(q_num_entries_g-4)) + q_ilat_mux( + .cond(q_entry_rdy_l2c), + .din(q_ilat_ary), + .dout(rv1_instr_ilat) + ); + + //------------------------------------------------------------------------------------------------------- + generate + begin : ba_extnd + for (n = 4; n <= (q_num_entries_g - 1); n = n + 1) + begin : ba_extnda + assign q_barf_addr_ary[n*q_barf_enc_g:(n+1)*q_barf_enc_g-1] = q_barf_addr_q[n]; + + end + end + endgenerate + generate + begin : ba_extndc + for (n = 0; n <= (q_num_entries_g - 1); n = n + 1) + begin : ba_extndac + assign q_barf_clr_addr_ary[n*q_barf_enc_g:(n+1)*q_barf_enc_g-1] = q_barf_addr_q[n]; + + end + end + endgenerate + + rv_primux #(.q_dat_width_g(q_barf_enc_g), .q_num_entries_g(q_num_entries_g-4)) + q_barf_addr_mux( + .cond(q_entry_rdy_l2c), + .din(q_barf_addr_ary), + .dout(ex0_barf_addr_d) + ); + + rv_primux #(.q_dat_width_g(q_barf_enc_g), .q_num_entries_g(q_num_entries_g)) + barf_clr_addr_mux( + .cond(q_credit_rdy), + .din(q_barf_clr_addr_ary), + .dout(barf_clr_addr) + ); + + + //------------------------------------------------------------------------------------------------------- + // Hold Logic (ordered / cordered) + //------------------------------------------------------------------------------------------------------- + + assign q_hold_all_d = q_hold_all; + assign q_ord_completed = q_ord_complete | (flush & q_hold_ord_q); + assign q_hold_ord_set = q_tid_q[q_num_entries_g - 1] & {`THREADS{q_ord_q[q_num_entries_g - 1] & q_entry_select[q_num_entries_g - 1]}}; //and not q_cord_q(q_num_entries_g-1); --cord + + assign q_hold_ord_d = (q_hold_ord_set | (q_hold_ord_q & (~q_hold_ord_set))) & (~q_ord_completed) & (~flush); + + // The ordered TID, needed for itag release + assign q_ord_tid = q_hold_ord_q; + + + generate + if (`THREADS == 1) + begin : q_cp_next_gen1 + assign q_cp_next_itag = cp_next_itag; + end + endgenerate + generate + if (`THREADS == 2) + begin : q_cp_next_gen2 + assign q_cp_next_itag = ({`ITAG_SIZE_ENC{q_tid_q[q_num_entries_g - 1][0]}} & cp_next_itag[0:`ITAG_SIZE_ENC-1]) | + ({`ITAG_SIZE_ENC{q_tid_q[q_num_entries_g - 1][1]}} & cp_next_itag[`ITAG_SIZE_ENC:`THREADS*`ITAG_SIZE_ENC-1]); + end + endgenerate + + // Completion Ordered logic, optimize out if not used == todo MAKE THREADED + generate + if (q_cord_g == 1) + begin : q_cord1_g_gen + assign q_cord_match = (q_cp_next_itag == q_itag_q[q_num_entries_g - 1]) & q_ev_q[q_num_entries_g - 1]; + + assign q_cord_d[0] = (q_entry_load_i1[0] & rv0_instr_i1_cord ) | + (q_entry_load_i0[0] & rv0_instr_i0_cord ) | + (q_entry_hold[0] & q_cord_nxt[0]); + begin : xhdl5 + for (n = 1; n <= (q_num_entries_g - 1); n = n + 1) + begin : q_cord_gen + assign q_cord_d[n] = (q_entry_load_i1[n] & rv0_instr_i1_cord ) | + (q_entry_load_i0[n] & rv0_instr_i0_cord ) | + (q_entry_shift[n] & q_cord_nxt[n - 1] ) | + (q_entry_hold[n] & q_cord_nxt[n]) ; + + end + end + begin : xhdl6 + for (n = 0; n <= (q_num_entries_g - 1); n = n + 1) + begin : q_cord_nxt_gen + assign q_cord_set[n] = q_lq_itag_match[n] & lq_rv_itag1_cord_q; + assign q_cord_nxt[n] = q_cord_q[n] | q_cord_set[n]; + + tri_rlmlatch_p #(.INIT(0)) + q_cord_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(q_cord_act[n]), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[q_cord_offset + n]), + .scout(sov[q_cord_offset + n]), + .din(q_cord_d[n]), + .dout(q_cord_q[n]) + ); + + end + end + + end + endgenerate + generate + if (q_cord_g == 0) + begin : q_cord0_g_gen + assign q_cord_match = 1'b0; + begin : xhdl6b + for (n = 0; n <= (q_num_entries_g - 1); n = n + 1) + begin : q_cord0_nxt_gen + assign q_cord_d[n]=1'b0; + assign q_cord_q[n]=1'b0; + assign q_cord_nxt[n]=1'b0; + assign sov[q_cord_offset + n] = siv[q_cord_offset + n]; + end + end + + end + endgenerate + + //------------------------------------------------------------------------------------------------------- + // generation of the ordered bit that is present in each reservation station entry + //------------------------------------------------------------------------------------------------------- + generate + if (q_ord_g == 1) + begin : q_ord1_g_gen + + assign q_ord_d[0] = (q_entry_load_i1[0] & rv0_instr_i1_ord ) | + (q_entry_load_i0[0] & rv0_instr_i0_ord ) | + (q_entry_hold[0] & q_ord_nxt[0]); + begin : xhdl3 + for (n = 1; n <= (q_num_entries_g - 1); n = n + 1) + begin : q_ord_gen + assign q_ord_d[n] = (q_entry_load_i1[n] & rv0_instr_i1_ord ) | + (q_entry_load_i0[n] & rv0_instr_i0_ord ) | + (q_entry_shift[n] & q_ord_nxt[n - 1] ) | + (q_entry_hold[n] & q_ord_nxt[n]) ; + + end + end + + begin : xhdl4 + for (n = 0; n <= (q_num_entries_g - 1); n = n + 1) + begin : q_ord_nxt_gen + assign q_ord_nxt[n] = q_ord_q[n]; + + tri_rlmlatch_p #(.INIT(0)) + q_ord_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(q_dat_act[n]), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[q_ord_offset + n]), + .scout(sov[q_ord_offset + n]), + .din(q_ord_d[n]), + .dout(q_ord_q[n]) + ); + + end + end + end + endgenerate + generate + if (q_ord_g == 0) + begin : q_ord0_g_gen + //generate + begin : xhdl3b + for (n = 0; n <= (q_num_entries_g - 1); n = n + 1) + begin : q_ord0_gen + + assign q_ord_d[n]=1'b0; + assign q_ord_q[n]=1'b0; + assign q_ord_nxt[n]=1'b0; + + assign sov[q_ord_offset + n] = siv[q_ord_offset + n]; + + end + end + //endgenerate + + end + endgenerate + + //------------------------------------------------------------------------------------------------------- + // LQ Only. This logic is only needed in the LQ RVS + //------------------------------------------------------------------------------------------------------- + generate + if (q_lq_g) + begin : q_lq1_g_gen + + assign no_lq_unused = 1'b0; + + //------------------------------------------------------------------------------------------------------- + // generation of the speculative bit for this entry's cmd + //------------------------------------------------------------------------------------------------------- + + assign q_spec_d[0] = (q_entry_load_i1[0] & rv0_instr_i1_spec ) | + (q_entry_load_i0[0] & rv0_instr_i0_spec ) | + (q_entry_hold[0] & q_spec_nxt[0]); + begin : xhdl14 + for (n = 1; n <= (q_num_entries_g - 1); n = n + 1) + begin : q_spec_gen + assign q_spec_d[n] = (q_entry_load_i1[n] & rv0_instr_i1_spec ) | + (q_entry_load_i0[n] & rv0_instr_i0_spec ) | + (q_entry_shift[n] & q_spec_nxt[n - 1] ) | + (q_entry_hold[n] & q_spec_nxt[n] ); + end + end + begin : xhdl15 + for (n = 0; n <= (q_num_entries_g - 1); n = n + 1) + begin : q_spec_nxt_gen + assign q_spec_clr[n] = q_lq_itag_match[n] & (~q_e_miss_nxt[n]) & (~lq_rv_itag1_restart_q); + assign q_spec_nxt[n] = q_spec_q[n] & (~q_spec_clr[n]); + + tri_rlmlatch_p #(.INIT(0)) + q_spec_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[q_spec_offset + n]), + .scout(sov[q_spec_offset + n]), + .din(q_spec_d[n]), + .dout(q_spec_q[n]) + ); + end + end + + assign rv1_instr_spec = |(q_entry_rdy_pri & q_spec_q[4:q_num_entries_g-1]); + + //------------------------------------------------------------------------------------------------------- + // generation of erat miss logic + //------------------------------------------------------------------------------------------------------- + + assign q_e_miss_d[0] = q_e_miss_nxt[0] & q_entry_hold[0]; + begin : xhdl26 + for (n = 1; n <= (q_num_entries_g - 1); n = n + 1) + begin : q_e_miss_gen + + assign q_e_miss_d[n] = (q_e_miss_nxt[n - 1] & q_entry_shift[n]) | + (q_e_miss_nxt[n] & q_entry_hold[n]); + end + end + begin : xhdl27 + for (n = 0; n <= (q_num_entries_g - 1); n = n + 1) + begin : q_e_miss_nxt_gen + assign q_e_miss_set[n] = q_lq_itag_match[n] & lq_rv_itag1_hold_q; + assign q_e_miss_clr[n] = |(lq_rv_clr_hold_q & q_tid_q[n]); + assign q_e_miss_nxt[n] = (q_e_miss_q[n] | q_e_miss_set[n]) & (~q_e_miss_clr[n]); + + tri_rlmlatch_p #(.INIT(0)) q_e_miss_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(q_e_miss_act[n]), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[q_e_miss_offset + n]), + .scout(sov[q_e_miss_offset + n]), + .din(q_e_miss_d[n]), + .dout(q_e_miss_q[n]) + ); + + end + end + + tri_rlmlatch_p #(.INIT(0)) + lq_rv_itag1_restart_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[lq_rv_itag1_restart_offset]), + .scout(sov[lq_rv_itag1_restart_offset]), + .din(lq_rv_itag1_restart), + .dout(lq_rv_itag1_restart_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) + lq_rv_itag1_hold_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[lq_rv_itag1_hold_offset]), + .scout(sov[lq_rv_itag1_hold_offset]), + .din(lq_rv_itag1_hold), + .dout(lq_rv_itag1_hold_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) + lq_rv_itag1_cord_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[lq_rv_itag1_cord_offset]), + .scout(sov[lq_rv_itag1_cord_offset]), + .din(lq_rv_itag1_cord), + .dout(lq_rv_itag1_cord_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) + lq_rv_clr_hold_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[lq_rv_clr_hold_offset:lq_rv_clr_hold_offset + `THREADS - 1]), + .scout(sov[lq_rv_clr_hold_offset:lq_rv_clr_hold_offset + `THREADS - 1]), + .din(lq_rv_clr_hold), + .dout(lq_rv_clr_hold_q) + ); + + + end + endgenerate + generate + if (!(q_lq_g)) + begin : q_lq0_g_gen + + assign rv1_instr_spec = 1'b0; + assign q_spec_clr = {q_num_entries_g{1'b0}}; + assign q_spec_nxt = {q_num_entries_g{1'b0}}; + assign q_spec_d = {q_num_entries_g{1'b0}}; + assign q_spec_q = {q_num_entries_g{1'b0}}; + assign sov[q_spec_offset:q_spec_offset+q_num_entries_g-1] = siv[q_spec_offset:q_spec_offset+q_num_entries_g-1]; + + assign q_e_miss_set = {q_num_entries_g{1'b0}}; + assign q_e_miss_clr = {q_num_entries_g{1'b0}}; + assign q_e_miss_nxt = {q_num_entries_g{1'b0}}; + assign q_e_miss_d = {q_num_entries_g{1'b0}}; + assign q_e_miss_q = {q_num_entries_g{1'b0}}; + assign sov[q_e_miss_offset:q_e_miss_offset+q_num_entries_g-1] = siv[q_e_miss_offset:q_e_miss_offset+q_num_entries_g-1]; + + assign no_lq_unused = |q_spec_clr | |q_spec_nxt | |q_spec_d | |q_spec_q | + |q_e_miss_d | |q_e_miss_q[0:3] | |q_e_miss_set | |q_e_miss_clr | lq_rv_itag1_hold_q | |q_e_miss_act | + rv0_instr_i0_spec | rv0_instr_i1_spec | lq_rv_itag1_restart | lq_rv_itag1_hold | lq_rv_itag1_cord | |lq_rv_clr_hold; + + + assign lq_rv_itag1_restart_q = 1'b0; + assign lq_rv_itag1_hold_q = 1'b0; + assign lq_rv_itag1_cord_q = 1'b0; + assign lq_rv_clr_hold_q = {`THREADS{1'b0}}; + + assign sov[lq_rv_itag1_restart_offset]= siv[lq_rv_itag1_restart_offset]; + assign sov[lq_rv_itag1_hold_offset] = siv[lq_rv_itag1_hold_offset]; + assign sov[lq_rv_itag1_cord_offset] = siv[lq_rv_itag1_cord_offset]; + assign sov[lq_rv_clr_hold_offset:lq_rv_clr_hold_offset + `THREADS - 1] = siv[lq_rv_clr_hold_offset:lq_rv_clr_hold_offset + `THREADS - 1]; + + + end + endgenerate + + + //------------------------------------------------------------------------------------------------------- + // Brick. Kills all valids, late gate - optimize out if not used + //------------------------------------------------------------------------------------------------------- + generate + if (q_brick_g == 1'b1) + begin : q_brick1_g_gen + + + assign q_hold_brick_cnt_d = ((q_instr_is_brick == 1'b1)) ? q_instr_brick : + ((q_hold_brick_q == 1'b0)) ? q_hold_brick_cnt_q : + q_hold_brick_cnt_q - 3'b001; + assign q_hold_brick_d = ((q_instr_is_brick == 1'b1)) ? 1'b1 : + ((q_hold_brick_cnt_q == 3'b000)) ? 1'b0 : + q_hold_brick_q; + + assign q_hold_brick = q_hold_brick_q; + assign brick_unused = 1'b0; + assign brickn_unused = {q_num_entries_g{1'b0}}; + + + //------------------------------------------------------------------------------------------------------- + // generation of the brick info for this entry's cmd + //------------------------------------------------------------------------------------------------------- + + assign q_is_brick_d[0] = (q_entry_load_i1[0] & rv0_instr_i1_is_brick ) | + (q_entry_load_i0[0] & rv0_instr_i0_is_brick ) | + (q_entry_hold[0] & q_is_brick_q[0]); + begin : xhdl8 + for (n = 1; n <= (q_num_entries_g - 1); n = n + 1) + begin : q_is_brick_gen + assign q_is_brick_d[n] = (q_entry_load_i1[n] & rv0_instr_i1_is_brick ) | + (q_entry_load_i0[n] & rv0_instr_i0_is_brick ) | + (q_entry_shift[n] & q_is_brick_q[n - 1] ) | + (q_entry_hold[n] & q_is_brick_q[n]); + + end + end + assign q_brick_d[0] = ({3{q_entry_load_i1[0]}} & rv0_instr_i1_brick ) | + ({3{q_entry_load_i0[0]}} & rv0_instr_i0_brick ) | + ({3{q_entry_hold[0]}} & q_brick_q[0]); + begin : xhdl9 + for (n = 1; n <= (q_num_entries_g - 1); n = n + 1) + begin : q_brick_gen + assign q_brick_d[n] = ({3{q_entry_load_i1[n]}} & rv0_instr_i1_brick ) | + ({3{q_entry_load_i0[n]}} & rv0_instr_i0_brick ) | + ({3{q_entry_shift[n]}} & q_brick_q[n - 1] ) | + ({3{q_entry_hold[n]}} & q_brick_q[n]); + end + end + + tri_rlmlatch_p #(.INIT(0)) + q_hold_brick_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[q_hold_brick_offset]), + .scout(sov[q_hold_brick_offset]), + .din(q_hold_brick_d), + .dout(q_hold_brick_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) + q_hold_brick_cnt_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[q_hold_brick_cnt_offset:q_hold_brick_cnt_offset + 3 - 1]), + .scout(sov[q_hold_brick_cnt_offset:q_hold_brick_cnt_offset + 3 - 1]), + .din(q_hold_brick_cnt_d), + .dout(q_hold_brick_cnt_q) + ); + + begin : xhdl9b + for (n = 0; n <= (q_num_entries_g - 1); n = n + 1) + begin : q_bricklat_gen + tri_rlmlatch_p #(.INIT(0)) + q_is_brick_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(q_dat_act[n]), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[q_is_brick_offset + n]), + .scout(sov[q_is_brick_offset + n]), + .din(q_is_brick_d[n]), + .dout(q_is_brick_q[n]) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) + q_brick_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[q_brick_offset + 3 * n:q_brick_offset + 3 * (n + 1) - 1]), + .scout(sov[q_brick_offset + 3 * n:q_brick_offset + 3 * (n + 1) - 1]), + .din(q_brick_d[n]), + .dout(q_brick_q[n]) + ); + end // block: q_bricklat_gen + end // block: xhdl9b + end // block: q_brick1_g_gen + endgenerate + + generate + if (q_brick_g == 1'b0) + begin : q_brick0_g_gen + assign q_hold_brick = 1'b0; + assign sov[q_hold_brick_offset] = siv[q_hold_brick_offset]; + assign sov[q_hold_brick_cnt_offset:q_hold_brick_cnt_offset + 3 - 1] = siv[q_hold_brick_cnt_offset:q_hold_brick_cnt_offset + 3 - 1]; + + assign q_hold_brick_cnt_d = 3'b0; + assign q_hold_brick_cnt_q = 3'b0; + assign q_hold_brick_d = 1'b0; + assign q_hold_brick_q = 1'b0; + + assign brick_unused = q_hold_brick | |q_hold_brick_cnt_d | |q_hold_brick_cnt_q | q_hold_brick_d | q_hold_brick_q | q_instr_is_brick | + rv0_instr_i0_is_brick | |rv0_instr_i0_brick | rv0_instr_i1_is_brick | |rv0_instr_i1_brick | |q_instr_brick; + + begin : xhdl9b + for (n = 0; n <= (q_num_entries_g - 1); n = n + 1) + begin : q_brick_gen0 + + assign q_brick_d[n] = 3'b0; + assign q_brick_q[n] = 3'b0; + assign q_is_brick_d[n] = 1'b0; + assign q_is_brick_q[n] = 1'b0; + assign sov[q_is_brick_offset + n] = siv[q_is_brick_offset + n]; + assign sov[q_brick_offset + 3 * n:q_brick_offset + 3 * (n + 1) - 1]=siv[q_brick_offset + 3 * n:q_brick_offset + 3 * (n + 1) - 1]; + assign brickn_unused[n] = |q_brick_d[n] | |q_brick_q[n] | q_is_brick_d[n] | q_is_brick_q[n] ; + + + end + end + + end + endgenerate + + //------------------------------------------------------------------------------------------------------- + // Generate Q load and shift signals. + // q_entry_shift is gated when either q_entry_load or q_entry_load2 is active to create one hot + // mux controls. q_entry_or_tree is simply an or tree starting at the first ready entry from + // the bottom of the q. + //------------------------------------------------------------------------------------------------------- + assign q_ev_b = (~q_ev_q); + + generate + begin : xhdl32 + for (n = 0; n <= (q_num_entries_g - 1); n = n + 1) + begin : q_or_gen + assign q_entry_or_tree[n] = |(q_ev_b[n:q_num_entries_g - 1]); + end + end + endgenerate + + generate + begin : xhdl33 + for (n = 0; n <= (q_num_entries_g - 1); n = n + 1) + begin : q_and_gen + assign q_entry_and_tree[n] = &(q_ev_b[0:n]); + end + end + endgenerate + + generate + begin : xhdl34 + for (n = 0; n <= (q_num_entries_g - 1); n = n + 1) + begin : q_entry_shift_gen + assign q_entry_shift[n] = q_entry_or_tree[n] & (~(q_entry_load[n] | q_entry_load2[n])); + end + end + endgenerate + + assign q_entry_load[0] = (rv0_load1 & (~q_entry_or_tree[0]) & q_entry_and_tree[0] & (~q_entry_and_tree[1])) | + (rv0_load1 & q_entry_or_tree[0] & (~q_entry_and_tree[0]) & 1'b1) | + (rv0_load1 & q_entry_or_tree[0] & q_entry_and_tree[0] & (~q_entry_or_tree[1])); + + + generate + begin : xhdl35 + for (n = 1; n <= (q_num_entries_g - 2); n = n + 1) + begin : q_load_gen + // special case + assign q_entry_load[n] = (rv0_load1 & (~q_entry_or_tree[n]) & q_entry_and_tree[n] & (~q_entry_and_tree[n + 1])) | + (rv0_load1 & q_entry_or_tree[n] & (~q_entry_and_tree[n]) & q_entry_and_tree[n - 1]) | + (rv0_load1 & q_entry_or_tree[n] & q_entry_and_tree[n] & (~q_entry_or_tree[n + 1])); + end + end + endgenerate + + + assign q_entry_load[q_num_entries_g - 1] = (rv0_load1 & (~q_entry_or_tree[q_num_entries_g - 1]) & q_entry_and_tree[q_num_entries_g - 1] & (~1'b0)) | + (rv0_load1 & q_entry_or_tree[q_num_entries_g - 1] & (~1'b0) & q_entry_and_tree[q_num_entries_g - 2]); + + generate + begin : xhdl36 + for (n = 0; n <= (q_num_entries_g - 2); n = n + 1) + begin : q_entry_load2_gen + assign q_entry_load2[n] = rv0_load2 & q_entry_load[n + 1]; + end + end + endgenerate + assign q_entry_load2[q_num_entries_g - 1] = 1'b0; + + generate + begin : xhdl37 + for (n = 0; n <= (q_num_entries_g - 1); n = n + 1) + begin : q_hold_gen + assign q_entry_hold[n] = (~(q_entry_load[n] | q_entry_load2[n] | q_entry_shift[n])); + + assign q_entry_load_i0[n] = (q_entry_load[n] & (~rv0_load1_instr_select)); + assign q_entry_load_i1[n] = q_entry_load2[n] | (q_entry_load[n] & rv0_load1_instr_select); + end + end + endgenerate + + //------------------------------------------------------------------------------------------------------- + // generation of Clock gating + //------------------------------------------------------------------------------------------------------- + + assign q_dat_act[0] = (rv0_instr_i0_rte | rv0_instr_i1_rte); + + assign q_e_miss_act[0] = (rv0_instr_i0_rte | rv0_instr_i1_rte) | + |(lq_rv_itag1_rst_vld_q | lq_rv_clr_hold_q); //itag1 clrhold + assign q_cord_act[0] = (rv0_instr_i0_rte | rv0_instr_i1_rte) | |(lq_rv_itag1_rst_vld_q); + + generate + begin : xhdl38 + for (n = 1; n <= (q_num_entries_g - 1); n = n + 1) + begin : q_act_gen + assign q_dat_act[n] = ((rv0_instr_i0_rte | rv0_instr_i1_rte) | q_ev_q[n - 1]); + + assign q_e_miss_act[n] = ((rv0_instr_i0_rte | rv0_instr_i1_rte) | q_ev_q[n - 1]) | + |(lq_rv_itag1_rst_vld_q | + lq_rv_clr_hold_q); //itag1 clrhold + assign q_cord_act[n] = ((rv0_instr_i0_rte | rv0_instr_i1_rte) | q_ev_q[n - 1]) | |(lq_rv_itag1_rst_vld_q); + end + end + endgenerate + + //------------------------------------------------------------------------------------------------------- + // generation of Credit Logic, with spec trickle + //------------------------------------------------------------------------------------------------------- + + assign q_credit_d[0] = (q_credit_nxt[0] & q_entry_hold[0]) & ~(&(flush)); + + generate + begin : xhdl39 + for (n = 1; n <= (q_num_entries_g - 1); n = n + 1) + begin : q_credit_gen + assign q_credit_d[n] = + ((q_credit_nxt[n - 1] & q_entry_shift[n]) | + (q_credit_nxt[n] & q_entry_hold[n])) & ~(&(flush)); + end + end + endgenerate + + generate + begin : xhdl40 + for (n = 0; n <= (q_num_entries_g - 1); n = n + 1) + begin : q_credit_nxt_gen + + + assign q_credit_ex3[n] = (ex3_instr_issued[n] & ~xx_rv_ex3_abort & ~q_spec_q[n]) ; + assign q_credit_ex6[n] = (q_lq_itag_match[n] & q_spec_q[n] & ~lq_rv_itag1_restart_q) ; + assign q_credit_flush[n] = q_flushed_q[n]; + + assign q_credit_set[n] = q_ev_q[n] & (q_credit_ex3[n] | q_credit_ex6[n] | q_credit_flush[n]); + assign q_credit_clr[n] = q_credit_take[n] | (&(flush)); + + assign q_credit_rdy[n] = ( q_credit_q[n] | q_credit_set[n]) ; + + assign q_credit_nxt[n] = ( q_credit_q[n] | q_credit_set[n]) & ~q_credit_clr[n]; + + + end + end + endgenerate + + + + rv_rpri #(.size(q_num_entries_g)) + q_credit_pri( + .cond(q_credit_rdy), + .pri(q_credit_take) + ); + + generate + begin : tid_extndf + for (n = 0; n <= (q_num_entries_g - 1); n = n + 1) + begin : tid_extndaf + assign q_tid_full_ary[n*`THREADS:(n+1)*`THREADS-1] = q_tid_q[n]; + + end + end + endgenerate + + rv_prisel #(.q_dat_width_g(`THREADS), .q_num_entries_g(q_num_entries_g)) + q_credit_mux( + .cond(q_credit_rdy), + .din(q_tid_full_ary), + .dout(ex1_credit_free_d) + ); + + generate + begin : xhdl41 + for (t = 0; t <= (`THREADS - 1); t = t + 1) + begin : ex1_credit_gen + assign ex1_credit_free[t] = ex1_credit_free_q[t] & ~(&(flush2)); + end + end + endgenerate + + //------------------------------------------------------------------------------------------------------- + // RVS Empty + //------------------------------------------------------------------------------------------------------- + + generate + begin : xhdl43 + for (n = 0; n <= (q_num_entries_g - 1); n = n + 1) + begin : q_entry_tvld_gen + assign q_entry_tvld[n] = {`THREADS{q_ev_q[n]}} & q_tid_q[n]; + + begin : xhdl42 + for (t = 0; t <= (`THREADS - 1); t = t + 1) + begin : q_tvld_rev_gen + assign q_entry_tvld_rev[t][n] = q_entry_tvld[n][t]; + end + end + end + end + endgenerate + + generate + begin : xhdl44 + for (t = 0; t <= (`THREADS - 1); t = t + 1) + begin : rvs_empty_gen + assign rvs_empty_d[t] = (~(|(q_entry_tvld_rev[t]) | + rv0_instr_i0_vld[t] | rv0_instr_i0_vld[t] )); + end + end + endgenerate + + assign rvs_empty = rvs_empty_q; + + //------------------------------------------------------------------------------------------------------- + // Abort + //------------------------------------------------------------------------------------------------------- + + assign xx_rv_ex2_abort = xx_rv_ex2_s1_abort | xx_rv_ex2_s2_abort | xx_rv_ex2_s3_abort ; + + assign issued_vld_d[0] = q_instr_vld & ~flush; + assign issued_vld_d[1] = issued_vld_q[0] & ~flush; + assign issued_vld_d[2] = issued_vld_q[1] & ~flush; + assign issued_vld_d[3] = issued_vld_q[2] & ~flush; + assign issued_vld_d[4] = issued_vld_q[3] & ~flush; + + // Is the entry being shifted? We only shift down, ignore last shift + + generate + begin : xiaenc + // Encode the issued entry address to save latches + if(q_num_entries_g==12) + begin : ia12 + assign issued_addr[0]= q_entry_select[ 8]|q_entry_select[ 9]|q_entry_select[10]|q_entry_select[11]; + assign issued_addr[1]= q_entry_select[ 4]|q_entry_select[ 5]|q_entry_select[ 6]|q_entry_select[ 7]; + assign issued_addr[2]= q_entry_select[ 6]|q_entry_select[ 7]| + q_entry_select[10]|q_entry_select[11]; + assign issued_addr[3]= q_entry_select[ 5]|q_entry_select[ 7]| + q_entry_select[ 9]|q_entry_select[11]; + end + else + begin : ia16 + assign issued_addr[0]= q_entry_select[ 8]|q_entry_select[ 9]|q_entry_select[10]|q_entry_select[11]| + q_entry_select[12]|q_entry_select[13]|q_entry_select[14]|q_entry_select[15]; + assign issued_addr[1]= q_entry_select[ 4]|q_entry_select[ 5]|q_entry_select[ 6]|q_entry_select[ 7]| + q_entry_select[12]|q_entry_select[13]|q_entry_select[14]|q_entry_select[15]; + assign issued_addr[2]= q_entry_select[ 6]|q_entry_select[ 7]| + q_entry_select[10]|q_entry_select[11]|q_entry_select[14]|q_entry_select[15]; + assign issued_addr[3]= q_entry_select[ 5]|q_entry_select[ 7]| + q_entry_select[ 9]|q_entry_select[11]|q_entry_select[13]|q_entry_select[15]; + end + + // Is the entry being shifted? We only shift down, ignore last shift + assign issued_addr_d[0] = (|(q_entry_select[4:q_num_entries_g-2] & q_entry_shift[5:q_num_entries_g-1])) ? (issued_addr + 4'b0001) : issued_addr; + + for (i = 0; i <= q_num_entries_g-2; i = i + 1) + begin : ias + wire [0:3] idi = i; + assign issued_shift[0][i] = (issued_addr_q[0] == idi) & q_entry_shift[i+1]; + assign issued_shift[1][i] = (issued_addr_q[1] == idi) & q_entry_shift[i+1]; + assign issued_shift[2][i] = (issued_addr_q[2] == idi) & q_entry_shift[i+1]; + assign issued_shift[3][i] = (issued_addr_q[3] == idi) & q_entry_shift[i+1]; + + end + //last entry never shifted + assign issued_shift[0][q_num_entries_g-1] = 1'b0; + assign issued_shift[1][q_num_entries_g-1] = 1'b0; + assign issued_shift[2][q_num_entries_g-1] = 1'b0; + assign issued_shift[3][q_num_entries_g-1] = 1'b0; + + assign issued_addr_d[1] = (|issued_shift[0]) ? (issued_addr_q[0] + 4'b0001) : issued_addr_q[0]; + assign issued_addr_d[2] = (|issued_shift[1]) ? (issued_addr_q[1] + 4'b0001) : issued_addr_q[1]; + assign issued_addr_d[3] = (|issued_shift[2]) ? (issued_addr_q[2] + 4'b0001) : issued_addr_q[2]; + assign issued_addr_d[4] = (|issued_shift[3]) ? (issued_addr_q[3] + 4'b0001) : issued_addr_q[3]; + + + for (n = 0; n <= q_num_entries_g-1; n = n + 1) + begin : iasa + wire [0:3] ent = n; + + assign ex3_instr_issued[n] = (issued_addr_q[3] == ent) & |issued_vld_q[3]; + assign ex4_instr_issued[n] = (issued_addr_q[4] == ent) & |issued_vld_q[4]; + + end // block: iasa + + end + endgenerate + + //Delay clear for a cycle to line up better with abort reset for perf + assign ex4_instr_aborted = {q_num_entries_g{( xx_rv_ex4_abort) }} & ex4_instr_issued; + + + + + //------------------------------------------------------------------------------------------------------- + // generation of itag match logic + //------------------------------------------------------------------------------------------------------- + + assign xx_rv_rel_vld_d[0] = fx0_rv_itag_vld; + assign xx_rv_rel_vld_d[1] = fx1_rv_itag_vld; + assign xx_rv_rel_vld_d[2] = lq_rv_itag0_vld; + assign xx_rv_rel_vld_d[3] = lq_rv_itag1_vld; + assign xx_rv_rel_vld_d[4] = lq_rv_itag2_vld; + assign xx_rv_rel_vld_d[5] = axu0_rv_itag_vld; + assign xx_rv_rel_vld_d[6] = axu1_rv_itag_vld; + + assign xx_rv_abort_d[0] = fx0_rv_itag_abort; + assign xx_rv_abort_d[1] = fx1_rv_itag_abort; + assign xx_rv_abort_d[2] = lq_rv_itag0_abort; + assign xx_rv_abort_d[3] = lq_rv_itag1_abort; + assign xx_rv_abort_d[4] = 1'b0; + assign xx_rv_abort_d[5] = axu0_rv_itag_abort; + assign xx_rv_abort_d[6] = axu1_rv_itag_abort; + + assign xx_rv_rel_itag_d[0] = {fx0_rv_itag[0:`ITAG_SIZE_ENC-1]}; + assign xx_rv_rel_itag_d[1] = {fx1_rv_itag[0:`ITAG_SIZE_ENC-1]}; + assign xx_rv_rel_itag_d[2] = {lq_rv_itag0[0:`ITAG_SIZE_ENC-1]}; + assign xx_rv_rel_itag_d[3] = {lq_rv_itag1[0:`ITAG_SIZE_ENC-1]}; + assign xx_rv_rel_itag_d[4] = {lq_rv_itag2[0:`ITAG_SIZE_ENC-1]}; + assign xx_rv_rel_itag_d[5] = {axu0_rv_itag[0:`ITAG_SIZE_ENC-1]}; + assign xx_rv_rel_itag_d[6] = {axu1_rv_itag[0:`ITAG_SIZE_ENC-1]}; + + + //Vectorize to pass to cmpitag + assign xx_rv_itag_vld_ary[0*`THREADS:0*`THREADS+`THREADS-1] = xx_rv_rel_vld_q[0] ; + assign xx_rv_itag_vld_ary[1*`THREADS:1*`THREADS+`THREADS-1] = xx_rv_rel_vld_q[1] ; + assign xx_rv_itag_vld_ary[2*`THREADS:2*`THREADS+`THREADS-1] = xx_rv_rel_vld_q[2] ; + assign xx_rv_itag_vld_ary[3*`THREADS:3*`THREADS+`THREADS-1] = xx_rv_rel_vld_q[3]; + assign xx_rv_itag_vld_ary[4*`THREADS:4*`THREADS+`THREADS-1] = xx_rv_rel_vld_q[4]; + assign xx_rv_itag_vld_ary[5*`THREADS:5*`THREADS+`THREADS-1] = xx_rv_rel_vld_q[5]; + assign xx_rv_itag_vld_ary[6*`THREADS:6*`THREADS+`THREADS-1] = xx_rv_rel_vld_q[6]; + + assign xx_rv_itag_ary[0*(`ITAG_SIZE_ENC):0*(`ITAG_SIZE_ENC)+(`ITAG_SIZE_ENC)-1] = xx_rv_rel_itag_q[0] ; + assign xx_rv_itag_ary[1*(`ITAG_SIZE_ENC):1*(`ITAG_SIZE_ENC)+(`ITAG_SIZE_ENC)-1] = xx_rv_rel_itag_q[1] ; + assign xx_rv_itag_ary[2*(`ITAG_SIZE_ENC):2*(`ITAG_SIZE_ENC)+(`ITAG_SIZE_ENC)-1] = xx_rv_rel_itag_q[2] ; + assign xx_rv_itag_ary[3*(`ITAG_SIZE_ENC):3*(`ITAG_SIZE_ENC)+(`ITAG_SIZE_ENC)-1] = xx_rv_rel_itag_q[3] ; + assign xx_rv_itag_ary[4*(`ITAG_SIZE_ENC):4*(`ITAG_SIZE_ENC)+(`ITAG_SIZE_ENC)-1] = xx_rv_rel_itag_q[4] ; + assign xx_rv_itag_ary[5*(`ITAG_SIZE_ENC):5*(`ITAG_SIZE_ENC)+(`ITAG_SIZE_ENC)-1] = xx_rv_rel_itag_q[5] ; + assign xx_rv_itag_ary[6*(`ITAG_SIZE_ENC):6*(`ITAG_SIZE_ENC)+(`ITAG_SIZE_ENC)-1] = xx_rv_rel_itag_q[6] ; + + generate + begin : xhdl45 + for (n = 0; n <= (q_num_entries_g - 1); n = n + 1) + begin : q_itag_match_gen + // Zero Bubble from my FX release + assign q_ilat0_match_s1[n] = (q_instr_ilat0_vld == q_tid_q[n]) & (q_s1_itag_q[n] == q_instr_itag); + assign q_ilat0_match_s2[n] = (q_instr_ilat0_vld == q_tid_q[n]) & (q_s2_itag_q[n] == q_instr_itag); + assign q_ilat0_match_s3[n] = (q_instr_ilat0_vld == q_tid_q[n]) & (q_s3_itag_q[n] == q_instr_itag); + + // Zero Bubble from other FX release + assign q_other_ilat0_match_s1[n] = (rv1_other_ilat0_vld == q_tid_q[n]) & (q_s1_itag_q[n] == rv1_other_ilat0_itag); + assign q_other_ilat0_match_s2[n] = (rv1_other_ilat0_vld == q_tid_q[n]) & (q_s2_itag_q[n] == rv1_other_ilat0_itag); + assign q_other_ilat0_match_s3[n] = (rv1_other_ilat0_vld == q_tid_q[n]) & (q_s3_itag_q[n] == rv1_other_ilat0_itag); + + // All itag matches except other ilat0 + + assign q_lq_itag_match[n] = |(lq_rv_itag1_rst_vld_q & q_tid_q[n]) & (q_itag_q[n] == lq_rv_itag1_rst_q); + + rv_cmpitag #(.q_itag_busses_g(q_itag_busses_g)) + q_s1_itag_cmp( + .vld(q_tid_q[n]), + .itag(q_s1_itag_q[n]), + .vld_ary(xx_rv_itag_vld_ary), + .itag_ary(xx_rv_itag_ary), + .abort(xx_rv_abort_q), + .hit_clear(q_xx_itag_clear_s1[n]), + .hit_abort(q_xx_itag_abort_s1[n]) + ); + + rv_cmpitag #( .q_itag_busses_g(q_itag_busses_g)) + q_s2_itag_cmp( + .vld(q_tid_q[n]), + .itag(q_s2_itag_q[n]), + .vld_ary(xx_rv_itag_vld_ary), + .itag_ary(xx_rv_itag_ary), + .abort(xx_rv_abort_q), + .hit_clear(q_xx_itag_clear_s2[n]), + .hit_abort(q_xx_itag_abort_s2[n]) + ); + + rv_cmpitag #( .q_itag_busses_g(q_itag_busses_g)) + q_s3_itag_cmp( + .vld(q_tid_q[n]), + .itag(q_s3_itag_q[n]), + .vld_ary(xx_rv_itag_vld_ary), + .itag_ary(xx_rv_itag_ary), + .abort(xx_rv_abort_q), + .hit_clear(q_xx_itag_clear_s3[n]), + .hit_abort(q_xx_itag_abort_s3[n]) + ); + + end + end + endgenerate + + rv_cmpitag #( .q_itag_busses_g(q_itag_busses_g)) + i0_s1_itag_cmp( + .vld(rv0_instr_i0_tid), + .itag(rv0_instr_i0_s1_itag), + .vld_ary(xx_rv_itag_vld_ary), + .itag_ary(xx_rv_itag_ary), + .abort(xx_rv_abort_q), + .hit_clear(rv0_i0_s1_itag_clear), + .hit_abort(rv0_i0_s1_itag_abort) //unused + ); + + rv_cmpitag #( .q_itag_busses_g(q_itag_busses_g)) + i0_s2_itag_cmp( + .vld(rv0_instr_i0_tid), + .itag(rv0_instr_i0_s2_itag), + .vld_ary(xx_rv_itag_vld_ary), + .itag_ary(xx_rv_itag_ary), + .abort(xx_rv_abort_q), + .hit_clear(rv0_i0_s2_itag_clear), + .hit_abort(rv0_i0_s2_itag_abort) //unused + ); + + rv_cmpitag #( .q_itag_busses_g(q_itag_busses_g)) + i0_s3_itag_cmp( + .vld(rv0_instr_i0_tid), + .itag(rv0_instr_i0_s3_itag), + .vld_ary(xx_rv_itag_vld_ary), + .itag_ary(xx_rv_itag_ary), + .abort(xx_rv_abort_q), + .hit_clear(rv0_i0_s3_itag_clear), + .hit_abort(rv0_i0_s3_itag_abort) //unused + ); + + + // rv0_*_s?_dep_hit will only be on for a souce valid, so don't need to gate that here (except for the abort, which is faster) + assign rv0_instr_i0_s1_rdy = ~((rv0_instr_i0_s1_dep_hit & ~(rv0_i0_s1_itag_clear )) | (rv0_i0_s1_itag_abort & rv0_instr_i0_s1_v)); + assign rv0_instr_i0_s2_rdy = ~((rv0_instr_i0_s2_dep_hit & ~(rv0_i0_s2_itag_clear )) | (rv0_i0_s2_itag_abort & rv0_instr_i0_s2_v)); + assign rv0_instr_i0_s3_rdy = ~((rv0_instr_i0_s3_dep_hit & ~(rv0_i0_s3_itag_clear )) | (rv0_i0_s3_itag_abort & rv0_instr_i0_s3_v)); + + + rv_cmpitag #( .q_itag_busses_g(q_itag_busses_g)) + i1_s1_itag_cmp( + .vld(rv0_instr_i1_tid), + .itag(rv0_instr_i1_s1_itag), + .vld_ary(xx_rv_itag_vld_ary), + .itag_ary(xx_rv_itag_ary), + .abort(xx_rv_abort_q), + .hit_clear(rv0_i1_s1_itag_clear), + .hit_abort(rv0_i1_s1_itag_abort) + ); + + rv_cmpitag #( .q_itag_busses_g(q_itag_busses_g)) + i1_s2_itag_cmp( + .vld(rv0_instr_i1_tid), + .itag(rv0_instr_i1_s2_itag), + .vld_ary(xx_rv_itag_vld_ary), + .itag_ary(xx_rv_itag_ary), + .abort(xx_rv_abort_q), + .hit_clear(rv0_i1_s2_itag_clear), + .hit_abort(rv0_i1_s2_itag_abort) + ); + + rv_cmpitag #( .q_itag_busses_g(q_itag_busses_g)) + i1_s3_itag_cmp( + .vld(rv0_instr_i1_tid), + .itag(rv0_instr_i1_s3_itag), + .vld_ary(xx_rv_itag_vld_ary), + .itag_ary(xx_rv_itag_ary), + .abort(xx_rv_abort_q), + .hit_clear(rv0_i1_s3_itag_clear), + .hit_abort(rv0_i1_s3_itag_abort) + ); + + assign rv0_instr_i1_s1_rdy = ~((rv0_instr_i1_s1_dep_hit & ~(rv0_i1_s1_itag_clear )) | (rv0_i1_s1_itag_abort & rv0_instr_i1_s1_v)); + assign rv0_instr_i1_s2_rdy = ~((rv0_instr_i1_s2_dep_hit & ~(rv0_i1_s2_itag_clear )) | (rv0_i1_s2_itag_abort & rv0_instr_i1_s2_v)); + assign rv0_instr_i1_s3_rdy = ~((rv0_instr_i1_s3_dep_hit & ~(rv0_i1_s3_itag_clear )) | (rv0_i1_s3_itag_abort & rv0_instr_i1_s3_v)); + + //------------------------------------------------------------------------------------------------------- + // Perf Counters + //------------------------------------------------------------------------------------------------------- + // 0 RV Empty + // 1 RV Issued OoO + // 2 RV Above watermark + // 3 RV Instr Issued + // 4 Ordered Hold + // 5 Cord Hold + // 6 Dep Hold + // 7 Instr Aborted + + assign perf_bus_d[0] = &(rvs_empty_q); + assign perf_bus_d[1] = issued_vld_q[0][0]; //todo, not right + assign perf_bus_d[2] = |(q_ev_q[0:4]); + assign perf_bus_d[3] = issued_vld_q[0][0]; + assign perf_bus_d[4] = q_entry_tvld_rev[0][q_num_entries_g-1] & ~q_issued_q[q_num_entries_g-1] & q_ord_q[q_num_entries_g-1] & |q_hold_ord_q; + assign perf_bus_d[5] = q_entry_tvld_rev[0][q_num_entries_g-1] & ~q_issued_q[q_num_entries_g-1] & q_cord_q[q_num_entries_g-1] & ~q_cord_match; + assign perf_bus_d[6] = |(q_entry_tvld_rev[0] & ~q_issued_q & ~q_rdy_q); + assign perf_bus_d[7] = xx_rv_ex3_abort & issued_vld_q[3][0]; + +`ifndef THREADS1 + + assign perf_bus_d[8] = &(rvs_empty_q); + assign perf_bus_d[9] = issued_vld_q[0][1]; //todo, not right + assign perf_bus_d[10] = |(q_ev_q[0:4]); + assign perf_bus_d[11] = issued_vld_q[0][1]; + assign perf_bus_d[12] = q_entry_tvld_rev[1][q_num_entries_g-1] & ~q_issued_q[q_num_entries_g-1] & q_ord_q[q_num_entries_g-1] & |q_hold_ord_q; + assign perf_bus_d[13] = q_entry_tvld_rev[1][q_num_entries_g-1] & ~q_issued_q[q_num_entries_g-1] & q_cord_q[q_num_entries_g-1] & ~q_cord_match; + assign perf_bus_d[14] = |(q_entry_tvld_rev[1] & ~q_issued_q & ~q_rdy_q); + assign perf_bus_d[15] = xx_rv_ex3_abort & issued_vld_q[3][1]; + +`endif + + assign rvs_perf_bus = perf_bus_q; + + assign dbg_bus_d = 32'b0; + assign rvs_dbg_bus = dbg_bus_q; + + + //------------------------------------------------------------------------------------------------------- + // storage elements + //------------------------------------------------------------------------------------------------------- + + + tri_rlmreg_p #(.WIDTH(q_barf_enc_g), .INIT(0)) + ex0_barf_addr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[ex0_barf_addr_offset:ex0_barf_addr_offset + q_barf_enc_g - 1]), + .scout(sov[ex0_barf_addr_offset:ex0_barf_addr_offset + q_barf_enc_g - 1]), + .din(ex0_barf_addr_d), + .dout(ex0_barf_addr_q) + ); + + generate + begin : x5ia4 + for (n = 0; n <= 4 ; n = n + 1) + begin : isa_gen + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) + issued_vld_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[issued_vld_offset + `THREADS*n:issued_vld_offset + `THREADS*(n+1) - 1]), + .scout(sov[issued_vld_offset + `THREADS*n:issued_vld_offset + `THREADS*(n+1) - 1]), + .din(issued_vld_d[n]), + .dout(issued_vld_q[n]) + ); + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) + issued_addr_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[issued_addr_offset + 4*n:issued_addr_offset + 4*(n+1) - 1]), + .scout(sov[issued_addr_offset + 4*n:issued_addr_offset + 4*(n+1) - 1]), + .din(issued_addr_d[n]), + .dout(issued_addr_q[n]) + ); + end // block: q_bev_gen + end // block: xhdl555 + endgenerate + + tri_rlmlatch_p #( .INIT(0)) + xx_rv_ex3_abort_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[xx_rv_ex3_abort_offset]), + .scout(sov[xx_rv_ex3_abort_offset]), + .din(xx_rv_ex2_abort), + .dout(xx_rv_ex3_abort) + ); + tri_rlmlatch_p #( .INIT(0)) + xx_rv_ex4_abort_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[xx_rv_ex4_abort_offset]), + .scout(sov[xx_rv_ex4_abort_offset]), + .din(xx_rv_ex3_abort), + .dout(xx_rv_ex4_abort) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) + flush_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[flush_reg_offset:flush_reg_offset + `THREADS - 1]), + .scout(sov[flush_reg_offset:flush_reg_offset + `THREADS - 1]), + .din(cp_flush), + .dout(flush) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) + flush2_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[flush2_reg_offset:flush2_reg_offset + `THREADS - 1]), + .scout(sov[flush2_reg_offset:flush2_reg_offset + `THREADS - 1]), + .din(flush), + .dout(flush2) + ); + + + + generate + begin : xhdl555 + for (n = 0; n <= q_num_entries_g ; n = n + 1) + begin : q_bev_gen + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) + barf_ev_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[barf_ev_offset + `THREADS*n:barf_ev_offset + `THREADS*(n+1) - 1]), + .scout(sov[barf_ev_offset + `THREADS*n:barf_ev_offset + `THREADS*(n+1) - 1]), + .din(barf_ev_d[n]), + .dout(barf_ev_q[n]) + ); + end // block: q_bev_gen + end // block: xhdl555 + endgenerate + + generate + begin : xhdl5xx + for (n = 0; n < q_itag_busses_g ; n = n + 1) + begin : xx_gen + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) + xx_rv_rel_vld_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[xx_rv_rel_vld_offset + `THREADS*n:xx_rv_rel_vld_offset + `THREADS*(n+1) - 1]), + .scout(sov[xx_rv_rel_vld_offset + `THREADS*n:xx_rv_rel_vld_offset + `THREADS*(n+1) - 1]), + .din(xx_rv_rel_vld_d[n]), + .dout(xx_rv_rel_vld_q[n]) + ); + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) + xx_rv_rel_itag_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[xx_rv_rel_itag_offset + (`ITAG_SIZE_ENC)*n:xx_rv_rel_itag_offset + (`ITAG_SIZE_ENC)*(n+1) - 1]), + .scout(sov[xx_rv_rel_itag_offset + (`ITAG_SIZE_ENC)*n:xx_rv_rel_itag_offset + (`ITAG_SIZE_ENC)*(n+1) - 1]), + .din(xx_rv_rel_itag_d[n]), + .dout(xx_rv_rel_itag_q[n]) + ); + end // block: q_bev_gen + end // block: xhdl555 + endgenerate + + tri_rlmreg_p #(.WIDTH(q_itag_busses_g), .INIT(0)) + xx_rv_abort_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[xx_rv_abort_offset:xx_rv_abort_offset + q_itag_busses_g - 1]), + .scout(sov[xx_rv_abort_offset:xx_rv_abort_offset + q_itag_busses_g - 1]), + .din(xx_rv_abort_d), + .dout(xx_rv_abort_q) + ); + + generate + begin : xhdl999 + for (n = 0; n <= q_num_entries_g - 1; n = n + 1) + begin : q_x_q_gen + + tri_rlmreg_p #(.WIDTH(q_dat_width_g), .INIT(0)) + q_dat_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(q_dat_act[n]), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[q_dat_offset + q_dat_width_g * n:q_dat_offset + q_dat_width_g * (n + 1) - 1]), + .scout(sov[q_dat_offset + q_dat_width_g * n:q_dat_offset + q_dat_width_g * (n + 1) - 1]), + .din(q_dat_d[n]), + .dout(q_dat_q[n]) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) + q_itag_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(q_dat_act[n]), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[q_itag_offset + `ITAG_SIZE_ENC * n:q_itag_offset + `ITAG_SIZE_ENC * (n + 1) - 1]), + .scout(sov[q_itag_offset + `ITAG_SIZE_ENC * n:q_itag_offset + `ITAG_SIZE_ENC * (n + 1) - 1]), + .din(q_itag_d[n]), + .dout(q_itag_q[n]) + ); + + + + + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) + q_ilat_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(q_dat_act[n]), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[q_ilat_offset + 4 * n:q_ilat_offset + 4 * (n + 1) - 1]), + .scout(sov[q_ilat_offset + 4 * n:q_ilat_offset + 4 * (n + 1) - 1]), + .din(q_ilat_d[n]), + .dout(q_ilat_q[n]) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) + q_tid_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(q_dat_act[n]), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[q_tid_offset + `THREADS * n:q_tid_offset + `THREADS * (n + 1) - 1]), + .scout(sov[q_tid_offset + `THREADS * n:q_tid_offset + `THREADS * (n + 1) - 1]), + .din(q_tid_d[n]), + .dout(q_tid_q[n]) + ); + tri_rlmreg_p #(.WIDTH(q_barf_enc_g), .INIT(0)) + q_bard_addr_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(q_dat_act[n]), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[q_barf_addr_offset + q_barf_enc_g* n:q_barf_addr_offset + q_barf_enc_g* (n + 1) - 1]), + .scout(sov[q_barf_addr_offset + q_barf_enc_g* n:q_barf_addr_offset + q_barf_enc_g* (n + 1) - 1]), + .din(q_barf_addr_d[n]), + .dout(q_barf_addr_q[n]) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) + q_s1_itag_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(q_dat_act[n]), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[q_s1_itag_offset + `ITAG_SIZE_ENC * n:q_s1_itag_offset + `ITAG_SIZE_ENC * (n + 1) - 1]), + .scout(sov[q_s1_itag_offset + `ITAG_SIZE_ENC * n:q_s1_itag_offset + `ITAG_SIZE_ENC * (n + 1) - 1]), + .din(q_s1_itag_d[n]), + .dout(q_s1_itag_q[n]) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) + q_s2_itag_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(q_dat_act[n]), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[q_s2_itag_offset + `ITAG_SIZE_ENC * n:q_s2_itag_offset + `ITAG_SIZE_ENC * (n + 1) - 1]), + .scout(sov[q_s2_itag_offset + `ITAG_SIZE_ENC * n:q_s2_itag_offset + `ITAG_SIZE_ENC * (n + 1) - 1]), + .din(q_s2_itag_d[n]), + .dout(q_s2_itag_q[n]) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) + q_s3_itag_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(q_dat_act[n]), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[q_s3_itag_offset + `ITAG_SIZE_ENC * n:q_s3_itag_offset + `ITAG_SIZE_ENC * (n + 1) - 1]), + .scout(sov[q_s3_itag_offset + `ITAG_SIZE_ENC * n:q_s3_itag_offset + `ITAG_SIZE_ENC * (n + 1) - 1]), + .din(q_s3_itag_d[n]), + .dout(q_s3_itag_q[n]) + ); + + + tri_rlmlatch_p #(.INIT(0)) + q_s1_v_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(q_dat_act[n]), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[q_s1_v_offset + n]), + .scout(sov[q_s1_v_offset + n]), + .din(q_s1_v_d[n]), + .dout(q_s1_v_q[n]) + ); + + + tri_rlmlatch_p #(.INIT(0)) + q_s2_v_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(q_dat_act[n]), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[q_s2_v_offset + n]), + .scout(sov[q_s2_v_offset + n]), + .din(q_s2_v_d[n]), + .dout(q_s2_v_q[n]) + ); + + + tri_rlmlatch_p #(.INIT(0)) + q_s3_v_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(q_dat_act[n]), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[q_s3_v_offset + n]), + .scout(sov[q_s3_v_offset + n]), + .din(q_s3_v_d[n]), + .dout(q_s3_v_q[n]) + ); + + + tri_rlmlatch_p #(.INIT(0)) + q_issued_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[q_issued_offset + n]), + .scout(sov[q_issued_offset + n]), + .din(q_issued_d[n]), + .dout(q_issued_q[n]) + ); + + tri_rlmlatch_p #(.INIT(0)) + q_s1_rdy_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[q_s1_rdy_offset + n]), + .scout(sov[q_s1_rdy_offset + n]), + .din(q_s1_rdy_d[n]), + .dout(q_s1_rdy_q[n]) + ); + + + tri_rlmlatch_p #(.INIT(0)) + q_s2_rdy_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[q_s2_rdy_offset + n]), + .scout(sov[q_s2_rdy_offset + n]), + .din(q_s2_rdy_d[n]), + .dout(q_s2_rdy_q[n]) + ); + + + tri_rlmlatch_p #(.INIT(0)) + q_s3_rdy_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[q_s3_rdy_offset + n]), + .scout(sov[q_s3_rdy_offset + n]), + .din(q_s3_rdy_d[n]), + .dout(q_s3_rdy_q[n]) + ); + + end + end + endgenerate + + + // Issueable + generate + begin : xhdl999i + for (n = 0; n <= q_num_entries_g - 1; n = n + 1) + begin : q_x_q_gen + + + tri_rlmlatch_p #(.INIT(0)) + q_rdy_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[q_rdy_offset + n]), + .scout(sov[q_rdy_offset + n]), + .din(q_rdy_d[n]), + .dout(q_rdy_q[n]) + ); + assign q_rdy_qb[n] = ~q_rdy_q[n]; + + end + end + endgenerate + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) + lq_rv_itag1_rst_vld_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[lq_rv_itag1_rst_vld_offset:lq_rv_itag1_rst_vld_offset + `THREADS - 1]), + .scout(sov[lq_rv_itag1_rst_vld_offset:lq_rv_itag1_rst_vld_offset + `THREADS - 1]), + .din(lq_rv_itag1_rst_vld), + .dout(lq_rv_itag1_rst_vld_q) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) + lq_rv_itag1_rst_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[lq_rv_itag1_rst_offset:lq_rv_itag1_rst_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[lq_rv_itag1_rst_offset:lq_rv_itag1_rst_offset + `ITAG_SIZE_ENC - 1]), + .din(lq_rv_itag1_rst), + .dout(lq_rv_itag1_rst_q) + ); + + + + tri_rlmreg_p #(.WIDTH(q_num_entries_g), .INIT(0)) + q_ev_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[q_ev_offset:q_ev_offset + q_num_entries_g - 1]), + .scout(sov[q_ev_offset:q_ev_offset + q_num_entries_g - 1]), + .din(q_ev_d), + .dout(q_ev_q) + ); + + + tri_rlmreg_p #(.WIDTH(q_num_entries_g), .INIT(0)) + q_flushed_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[q_flushed_offset:q_flushed_offset + q_num_entries_g - 1]), + .scout(sov[q_flushed_offset:q_flushed_offset + q_num_entries_g - 1]), + .din(q_flushed_d), + .dout(q_flushed_q) + ); + + + tri_rlmreg_p #(.WIDTH(q_num_entries_g), .INIT(0)) + q_credit_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[q_credit_offset:q_credit_offset + q_num_entries_g - 1]), + .scout(sov[q_credit_offset:q_credit_offset + q_num_entries_g - 1]), + .din(q_credit_d), + .dout(q_credit_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) + ex1_credit_free_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[ex1_credit_free_offset:ex1_credit_free_offset + `THREADS - 1]), + .scout(sov[ex1_credit_free_offset:ex1_credit_free_offset + `THREADS - 1]), + .din(ex1_credit_free_d), + .dout(ex1_credit_free_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) + rvs_empty_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[rvs_empty_offset:rvs_empty_offset + `THREADS - 1]), + .scout(sov[rvs_empty_offset:rvs_empty_offset + `THREADS - 1]), + .din(rvs_empty_d), + .dout(rvs_empty_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) + q_hold_all_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[q_hold_all_offset]), + .scout(sov[q_hold_all_offset]), + .din(q_hold_all_d), + .dout(q_hold_all_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) + q_hold_ord_q_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[q_hold_ord_offset:q_hold_ord_offset + `THREADS - 1]), + .scout(sov[q_hold_ord_offset:q_hold_ord_offset + `THREADS - 1]), + .din(q_hold_ord_d), + .dout(q_hold_ord_q) + ); + + tri_rlmreg_p #(.WIDTH(8*`THREADS), .INIT(0)) + perf_bus_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[perf_bus_offset:perf_bus_offset + 8*`THREADS - 1]), + .scout(sov[perf_bus_offset:perf_bus_offset + 8*`THREADS - 1]), + .din(perf_bus_d), + .dout(perf_bus_q) + ); + + tri_rlmreg_p #(.WIDTH(32), .INIT(0)) + dbg_bus_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .d_mode(d_mode), + .scin(siv[dbg_bus_offset:dbg_bus_offset + 32 - 1]), + .scout(sov[dbg_bus_offset:dbg_bus_offset + 32 - 1]), + .din(dbg_bus_d), + .dout(dbg_bus_q) + ); + + + + //--------------------------------------------------------------------- + // Scan + //--------------------------------------------------------------------- + assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in}; + assign scan_out = sov[0]; + + //----------------------------------------------- + // pervasive + //----------------------------------------------- + + + tri_plat #(.WIDTH(2)) + perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(ccflush_dc), + .din({func_sl_thold_1, sg_1}), + .q({func_sl_thold_0, sg_0}) + ); + + + tri_lcbor + perv_lcbor( + .clkoff_b(clkoff_b), + .thold(func_sl_thold_0), + .sg(sg_0), + .act_dis(act_dis), + .force_t(force_t), + .thold_b(func_sl_thold_0_b) + ); + + +endmodule diff --git a/dev/verilog/work/xu.v b/dev/verilog/work/xu.v new file mode 100755 index 0000000..034e15e --- /dev/null +++ b/dev/verilog/work/xu.v @@ -0,0 +1,1980 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +// Description: Dual Execution Unit +// +//***************************************************************************** + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" +(* recursive_synthesis="0" *) +module xu( + //------------------------------------------------------------------- + // Clocks & Power + //------------------------------------------------------------------- + (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) // nclk + input [0:`NCLK_WIDTH-1] nclk, + + //------------------------------------------------------------------- + // Pervasive + //------------------------------------------------------------------- + input pc_xu_ccflush_dc, + input clkoff_dc_b, + input d_mode_dc, + input delay_lclkr_dc, + input mpw1_dc_b, + input mpw2_dc_b, + input func_sl_force, + input func_sl_thold_0_b, + input func_slp_sl_thold_0_b, + input sg_0, + input fce_0, + (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) // scan_in + input scan_in, + (* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) // scan_out + output scan_out, + + output xu_pc_ram_done, + output [64-`GPR_WIDTH:63] xu_pc_ram_data, + + //------------------------------------------------------------------- + // CP Flush Interface + //------------------------------------------------------------------- + input [0:`THREADS-1] cp_flush, + input [62-`EFF_IFAR_ARCH : 61-`EFF_IFAR_WIDTH] iu_br_t0_flush_ifar, + input [0:`ITAG_SIZE_ENC-1] cp_next_itag_t0, + `ifndef THREADS1 + input [62-`EFF_IFAR_ARCH : 61-`EFF_IFAR_WIDTH] iu_br_t1_flush_ifar, + input [0:`ITAG_SIZE_ENC-1] cp_next_itag_t1, + `endif + + //------------------------------------------------------------------- + // BR Interface with CP + //------------------------------------------------------------------- + output [0:`THREADS-1] br_iu_execute_vld, + output [0:`ITAG_SIZE_ENC-1] br_iu_itag, + output br_iu_taken, + output [62-`EFF_IFAR_ARCH:61] br_iu_bta, + output [0:17] br_iu_gshare, + output [0:2] br_iu_ls_ptr, + output [62-`EFF_IFAR_WIDTH:61] br_iu_ls_data, + output br_iu_ls_update, + output [0:`THREADS-1] br_iu_redirect, + output [0:3] br_iu_perf_events, + + //------------------------------------------------------------------- + // RV->XU0 Issue + //------------------------------------------------------------------- + input [0:`THREADS-1] rv_xu0_vld, + input rv_xu0_s1_v, + input [0:`GPR_POOL_ENC-1] rv_xu0_s1_p, + input rv_xu0_s2_v, + input [0:`GPR_POOL_ENC-1] rv_xu0_s2_p, + input rv_xu0_s3_v, + input [0:`GPR_POOL_ENC-1] rv_xu0_s3_p, + input rv_xu0_ex0_ord, + input [0:19] rv_xu0_ex0_fusion, + input [0:31] rv_xu0_ex0_instr, + input [62-`EFF_IFAR_WIDTH:61] rv_xu0_ex0_ifar, + input [0:`ITAG_SIZE_ENC-1] rv_xu0_ex0_itag, + input [0:2] rv_xu0_ex0_ucode, + input rv_xu0_ex0_bta_val, + input [62-`EFF_IFAR_WIDTH:61] rv_xu0_ex0_pred_bta, + input rv_xu0_ex0_pred, + input [0:2] rv_xu0_ex0_ls_ptr, + input rv_xu0_ex0_bh_update, + input [0:17] rv_xu0_ex0_gshare, + input rv_xu0_ex0_s1_v, + input rv_xu0_ex0_s2_v, + input [0:2] rv_xu0_ex0_s2_t, + input rv_xu0_ex0_s3_v, + input [0:2] rv_xu0_ex0_s3_t, + input rv_xu0_ex0_t1_v, + input [0:`GPR_POOL_ENC-1] rv_xu0_ex0_t1_p, + input [0:2] rv_xu0_ex0_t1_t, + input rv_xu0_ex0_t2_v, + input [0:`GPR_POOL_ENC-1] rv_xu0_ex0_t2_p, + input [0:2] rv_xu0_ex0_t2_t, + input rv_xu0_ex0_t3_v, + input [0:`GPR_POOL_ENC-1] rv_xu0_ex0_t3_p, + input [0:2] rv_xu0_ex0_t3_t, + input [0:`THREADS-1] rv_xu0_ex0_spec_flush, + input [0:`THREADS-1] rv_xu0_ex1_spec_flush, + input [0:`THREADS-1] rv_xu0_ex2_spec_flush, + input [1:11] rv_xu0_s1_fxu0_sel, + input [1:11] rv_xu0_s2_fxu0_sel, + input [2:11] rv_xu0_s3_fxu0_sel, + input [1:6] rv_xu0_s1_fxu1_sel, + input [1:6] rv_xu0_s2_fxu1_sel, + input [2:6] rv_xu0_s3_fxu1_sel, + input [4:8] rv_xu0_s1_lq_sel, + input [4:8] rv_xu0_s2_lq_sel, + input [4:8] rv_xu0_s3_lq_sel, + input [2:3] rv_xu0_s1_rel_sel, + input [2:3] rv_xu0_s2_rel_sel, + + output xu0_rv_ord_complete, + output [0:`ITAG_SIZE_ENC-1] xu0_rv_ord_itag, + output xu0_rv_hold_all, + + //------------------------------------------------------------------- + // External Bypass Inputs + //------------------------------------------------------------------- + input lq_xu_ex5_act, + input lq_xu_ex5_abort, + input [(128-`STQ_DATA_SIZE):127] lq_xu_ex5_rt, + input [64-`GPR_WIDTH:63] lq_xu_ex5_data, + input [64-`GPR_WIDTH:63] iu_xu_ex5_data, + input [0:3] lq_xu_ex5_cr, + + //------------------------------------------------------------------- + // MMU/ERATs + //------------------------------------------------------------------- + output xu_iu_ord_ready, + output xu_iu_act, + output [0:`THREADS-1] xu_iu_val, + output xu_iu_is_eratre, + output xu_iu_is_eratwe, + output xu_iu_is_eratsx, + output xu_iu_is_eratilx, + output xu_iu_is_erativax, + output [0:1] xu_iu_ws, + output [0:2] xu_iu_t, + output [0:8] xu_iu_rs_is, + output [0:3] xu_iu_ra_entry, + output [64-`GPR_WIDTH:51] xu_iu_rb, + output [64-`GPR_WIDTH:63] xu_iu_rs_data, + input iu_xu_ord_read_done, + input iu_xu_ord_write_done, + input iu_xu_ord_n_flush_req, + input iu_xu_ord_par_err, + + output xu_lq_ord_ready, + output xu_lq_act, + output [0:`THREADS-1] xu_lq_val, + output xu_lq_hold_req, + output xu_lq_is_eratre, + output xu_lq_is_eratwe, + output xu_lq_is_eratsx, + output xu_lq_is_eratilx, + output [0:1] xu_lq_ws, + output [0:2] xu_lq_t, + output [0:8] xu_lq_rs_is, + output [0:4] xu_lq_ra_entry, + output [64-`GPR_WIDTH:51] xu_lq_rb, + output [64-`GPR_WIDTH:63] xu_lq_rs_data, + input lq_xu_ord_read_done, + input lq_xu_ord_write_done, + input lq_xu_ord_n_flush_req, + input lq_xu_ord_par_err, + + output xu_mm_ord_ready, + output xu_mm_act, + output [0:`THREADS-1] xu_mm_val, + output [0:`ITAG_SIZE_ENC-1] xu_mm_itag, + output xu_mm_is_tlbre, + output xu_mm_is_tlbwe, + output xu_mm_is_tlbsx, + output xu_mm_is_tlbsxr, + output xu_mm_is_tlbsrx, + output xu_mm_is_tlbivax, + output xu_mm_is_tlbilx, + output [0:11] xu_mm_ra_entry, + output [64-`GPR_WIDTH:63] xu_mm_rb, + input [0:`ITAG_SIZE_ENC-1] mm_xu_itag, + input mm_xu_ord_n_flush_req, + input mm_xu_ord_read_done, + input mm_xu_ord_write_done, + input mm_xu_tlb_miss, + input mm_xu_lrat_miss, + input mm_xu_tlb_inelig, + input mm_xu_pt_fault, + input mm_xu_hv_priv, + input mm_xu_illeg_instr, + input mm_xu_tlb_multihit, + input mm_xu_tlb_par_err, + input mm_xu_lru_par_err, + input mm_xu_local_snoop_reject, + input [0:1] mm_xu_mmucr0_tlbsel_t0, + `ifndef THREADS1 + input [0:1] mm_xu_mmucr0_tlbsel_t1, + `endif + input mm_xu_tlbwe_binv, + input mm_xu_cr0_eq, + input mm_xu_cr0_eq_valid, + + //------------------------------------------------------------------- + // External Bypass Outputs + //------------------------------------------------------------------- + output xu0_lq_ex3_act, + output xu0_lq_ex3_abort, + output [64-`GPR_WIDTH:63] xu0_lq_ex3_rt, + output [64-`GPR_WIDTH:63] xu0_lq_ex4_rt, + output xu0_lq_ex6_act, + output [64-`GPR_WIDTH:63] xu0_lq_ex6_rt, + + //------------------------------------------------------------------- + // XU0 Completion + //------------------------------------------------------------------- + output [0:`THREADS-1] xu0_iu_execute_vld, + output [0:`ITAG_SIZE_ENC-1] xu0_iu_itag, + output [0:`THREADS-1] xu0_iu_mtiar, + output xu0_iu_exception_val, + output [0:4] xu0_iu_exception, + output xu0_iu_n_flush, + output xu0_iu_np1_flush, + output xu0_iu_flush2ucode, + output [0:3] xu0_iu_perf_events, + output [62-`EFF_IFAR_ARCH:61] xu0_iu_bta, + output [0:`THREADS-1] xu_iu_pri_val, + output [0:2] xu_iu_pri, + output [0:`THREADS-1] xu_iu_ucode_xer_val, + output [3:9] xu_iu_ucode_xer, + + output xu1_rv_ex2_s1_abort, + output xu1_rv_ex2_s2_abort, + output xu1_rv_ex2_s3_abort, + //------------------------------------------------------------------- + // Slow SPRs + //------------------------------------------------------------------- + input xu_slowspr_val_in, + input xu_slowspr_rw_in, + input [64-`GPR_WIDTH:63] xu_slowspr_data_in, + input xu_slowspr_done_in, + + //------------------------------------------------------------------- + // RV->XU1 Issue + //------------------------------------------------------------------- + input [0:`THREADS-1] rv_xu1_vld, + input rv_xu1_s1_v, + input [0:`GPR_POOL_ENC-1] rv_xu1_s1_p, + input rv_xu1_s2_v, + input [0:`GPR_POOL_ENC-1] rv_xu1_s2_p, + input rv_xu1_s3_v, + input [0:`GPR_POOL_ENC-1] rv_xu1_s3_p, + input [0:31] rv_xu1_ex0_instr, + input [0:`ITAG_SIZE_ENC-1] rv_xu1_ex0_itag, + input rv_xu1_ex0_isstore, + input [1:1] rv_xu1_ex0_ucode, + input rv_xu1_ex0_t1_v, + input [0:`GPR_POOL_ENC-1] rv_xu1_ex0_t1_p, + input rv_xu1_ex0_t2_v, + input [0:`GPR_POOL_ENC-1] rv_xu1_ex0_t2_p, + input rv_xu1_ex0_t3_v, + input [0:`GPR_POOL_ENC-1] rv_xu1_ex0_t3_p, + input rv_xu1_ex0_s1_v, + input [0:2] rv_xu1_ex0_s3_t, + input [0:`THREADS-1] rv_xu1_ex0_spec_flush, + input [0:`THREADS-1] rv_xu1_ex1_spec_flush, + input [0:`THREADS-1] rv_xu1_ex2_spec_flush, + input [1:11] rv_xu1_s1_fxu0_sel, + input [1:11] rv_xu1_s2_fxu0_sel, + input [2:11] rv_xu1_s3_fxu0_sel, + input [1:6] rv_xu1_s1_fxu1_sel, + input [1:6] rv_xu1_s2_fxu1_sel, + input [2:6] rv_xu1_s3_fxu1_sel, + input [4:8] rv_xu1_s1_lq_sel, + input [4:8] rv_xu1_s2_lq_sel, + input [4:8] rv_xu1_s3_lq_sel, + input [2:3] rv_xu1_s1_rel_sel, + input [2:3] rv_xu1_s2_rel_sel, + + //------------------------------------------------------------------- + // Store Interface + //------------------------------------------------------------------- + output [0:`THREADS-1] xu1_lq_ex2_stq_val, + output [0:`ITAG_SIZE_ENC-1] xu1_lq_ex2_stq_itag, + output [1:4] xu1_lq_ex2_stq_size, + output xu1_lq_ex3_illeg_lswx, + output xu1_lq_ex3_strg_noop, + output [(64-`GPR_WIDTH)/8:7] xu1_lq_ex2_stq_dvc1_cmp, + output [(64-`GPR_WIDTH)/8:7] xu1_lq_ex2_stq_dvc2_cmp, + + //------------------------------------------------------------------- + // XU1 Completion + //------------------------------------------------------------------- + output [0:`THREADS-1] xu1_iu_execute_vld, + output [0:`ITAG_SIZE_ENC-1] xu1_iu_itag, + + output xu0_rv_ex2_s1_abort, + output xu0_rv_ex2_s2_abort, + output xu0_rv_ex2_s3_abort, + //------------------------------------------------------------------- + // External Bypass Outputs + //------------------------------------------------------------------- + output xu1_lq_ex3_act, + output xu1_lq_ex3_abort, + output [64-`GPR_WIDTH:63] xu1_lq_ex3_rt, + + //------------------------------------------------------------------- + // Unit Write Ports + //------------------------------------------------------------------- + output xu0_gpr_ex6_we, + output [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] xu0_gpr_ex6_wa, + output [64-`GPR_WIDTH:63+`GPR_WIDTH/8] xu0_gpr_ex6_wd, + output xu1_gpr_ex3_we, + output [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] xu1_gpr_ex3_wa, + output [64-`GPR_WIDTH:63+`GPR_WIDTH/8] xu1_gpr_ex3_wd, + + input lq_xu_gpr_ex5_we, + input [0:`AXU_SPARE_ENC+`GPR_POOL_ENC+`THREADS_POOL_ENC-1] lq_xu_gpr_ex5_wa, + input lq_xu_gpr_rel_we, + input [0:`AXU_SPARE_ENC+`GPR_POOL_ENC+`THREADS_POOL_ENC-1] lq_xu_gpr_rel_wa, + input [(128-`STQ_DATA_SIZE):127+`STQ_DATA_SIZE/8] lq_xu_gpr_rel_wd, + + input lq_xu_cr_ex5_we, + input [0:`CR_POOL_ENC+`THREADS_POOL_ENC-1] lq_xu_cr_ex5_wa, + input lq_xu_cr_l2_we, + input [0:`CR_POOL_ENC+`THREADS_POOL_ENC-1] lq_xu_cr_l2_wa, + input [0:3] lq_xu_cr_l2_wd, + input axu_xu_cr_w0e, + input [0:`CR_POOL_ENC+`THREADS_POOL_ENC-1] axu_xu_cr_w0a, + input [0:3] axu_xu_cr_w0d, + + input [0:`XER_POOL_ENC-1] iu_rf_xer_p_t0, + `ifndef THREADS1 + input [0:`XER_POOL_ENC-1] iu_rf_xer_p_t1, + `endif + output [0:`THREADS-1] xer_lq_cp_rd, + + //------------------------------------------------------------------- + // AXU Pass Thru Interface + //------------------------------------------------------------------- + input [59:63] lq_xu_axu_ex4_addr, + input lq_xu_axu_ex5_we, + input lq_xu_axu_ex5_le, + output [59:63] xu_axu_lq_ex4_addr, + output xu_axu_lq_ex5_we, + output xu_axu_lq_ex5_le, + output [0:`AXU_SPARE_ENC+`GPR_POOL_ENC+`THREADS_POOL_ENC-1] xu_axu_lq_ex5_wa, + output [(128-`STQ_DATA_SIZE):127] xu_axu_lq_ex5_wd, + output xu_axu_lq_ex5_abort, + + input lq_xu_axu_rel_we, + input lq_xu_axu_rel_le, + output xu_axu_lq_rel_we, + output xu_axu_lq_rel_le, + output [0:`AXU_SPARE_ENC+`GPR_POOL_ENC+`THREADS_POOL_ENC-1] xu_axu_lq_rel_wa, + output [(128-`STQ_DATA_SIZE):128+((`STQ_DATA_SIZE-1)/8)] xu_axu_lq_rel_wd, + + input [0:`THREADS-1] axu_xu_lq_ex_stq_val, + input [0:`ITAG_SIZE_ENC-1] axu_xu_lq_ex_stq_itag, + input [128-`STQ_DATA_SIZE:127] axu_xu_lq_exp1_stq_data, + output [0:`THREADS-1] xu_lq_axu_ex_stq_val, + output [0:`ITAG_SIZE_ENC-1] xu_lq_axu_ex_stq_itag, + output [128-`STQ_DATA_SIZE:127] xu_lq_axu_exp1_stq_data, + + // Interrupt Interface + input [0:`THREADS-1] iu_xu_rfi, + input [0:`THREADS-1] iu_xu_rfgi, + input [0:`THREADS-1] iu_xu_rfci, + input [0:`THREADS-1] iu_xu_rfmci, + input [0:`THREADS-1] iu_xu_act, + input [0:`THREADS-1] iu_xu_int, + input [0:`THREADS-1] iu_xu_gint, + input [0:`THREADS-1] iu_xu_cint, + input [0:`THREADS-1] iu_xu_mcint, + input [0:`THREADS-1] iu_xu_dear_update, + input [0:`THREADS-1] iu_xu_dbsr_update, + input [0:`THREADS-1] iu_xu_esr_update, + input [0:`THREADS-1] iu_xu_force_gsrr, + input [0:`THREADS-1] iu_xu_dbsr_ude, + input [0:`THREADS-1] iu_xu_dbsr_ide, + output [0:`THREADS-1] xu_iu_dbsr_ide, + + input [62-`EFF_IFAR_ARCH:61] iu_xu_nia_t0, + input [0:16] iu_xu_esr_t0, + input [0:14] iu_xu_mcsr_t0, + input [0:18] iu_xu_dbsr_t0, + input [64-`GPR_WIDTH:63] iu_xu_dear_t0, + output [62-`EFF_IFAR_ARCH:61] xu_iu_rest_ifar_t0, + + `ifndef THREADS1 + input [62-`EFF_IFAR_ARCH:61] iu_xu_nia_t1, + input [0:16] iu_xu_esr_t1, + input [0:14] iu_xu_mcsr_t1, + input [0:18] iu_xu_dbsr_t1, + input [64-`GPR_WIDTH:63] iu_xu_dear_t1, + output [62-`EFF_IFAR_ARCH:61] xu_iu_rest_ifar_t1, + `endif + + // Async Interrupt Request Interface + output [0:`THREADS-1] xu_iu_external_mchk, + output [0:`THREADS-1] xu_iu_ext_interrupt, + output [0:`THREADS-1] xu_iu_dec_interrupt, + output [0:`THREADS-1] xu_iu_udec_interrupt, + output [0:`THREADS-1] xu_iu_perf_interrupt, + output [0:`THREADS-1] xu_iu_fit_interrupt, + output [0:`THREADS-1] xu_iu_crit_interrupt, + output [0:`THREADS-1] xu_iu_wdog_interrupt, + output [0:`THREADS-1] xu_iu_gwdog_interrupt, + output [0:`THREADS-1] xu_iu_gfit_interrupt, + output [0:`THREADS-1] xu_iu_gdec_interrupt, + output [0:`THREADS-1] xu_iu_dbell_interrupt, + output [0:`THREADS-1] xu_iu_cdbell_interrupt, + output [0:`THREADS-1] xu_iu_gdbell_interrupt, + output [0:`THREADS-1] xu_iu_gcdbell_interrupt, + output [0:`THREADS-1] xu_iu_gmcdbell_interrupt, + input [0:`THREADS-1] iu_xu_dbell_taken, + input [0:`THREADS-1] iu_xu_cdbell_taken, + input [0:`THREADS-1] iu_xu_gdbell_taken, + input [0:`THREADS-1] iu_xu_gcdbell_taken, + input [0:`THREADS-1] iu_xu_gmcdbell_taken, + + // Doorbell Interrupts + input lq_xu_dbell_val, + input [0:4] lq_xu_dbell_type, + input lq_xu_dbell_brdcast, + input lq_xu_dbell_lpid_match, + input [50:63] lq_xu_dbell_pirtag, + + // Slow SPR Out + output xu_slowspr_val_out, + output xu_slowspr_rw_out, + output [0:1] xu_slowspr_etid_out, + output [11:20] xu_slowspr_addr_out, + output [64-`GPR_WIDTH:63] xu_slowspr_data_out, + + // Trap + output [0:`THREADS-1] xu_iu_fp_precise, + // Run State + input pc_xu_pm_hold_thread, + input [0:`THREADS-1] iu_xu_stop, + output [0:`THREADS-1] xu_pc_running, + output [0:`THREADS-1] xu_iu_run_thread, + output [0:`THREADS-1] xu_iu_single_instr_mode, + output [0:`THREADS-1] xu_iu_raise_iss_pri, + output [0:`THREADS-1] xu_iu_np1_async_flush, + input [0:`THREADS-1] iu_xu_async_complete, + input iu_xu_credits_returned, + output [0:`THREADS-1] xu_pc_spr_ccr0_we, + output [0:`THREADS-1] xu_pc_stop_dnh_instr, + input [0:`THREADS-1] iu_xu_quiesce, + input [0:`THREADS-1] iu_xu_icache_quiesce, + input [0:`THREADS-1] lq_xu_quiesce, + input [0:`THREADS-1] mm_xu_quiesce, + input [0:`THREADS-1] bx_xu_quiesce, + + // PCCR0 Controls + input pc_xu_extirpts_dis_on_stop, + input pc_xu_timebase_dis_on_stop, + input pc_xu_decrem_dis_on_stop, + + // MSR Override + input [0:`THREADS-1] pc_xu_ram_active, + output [0:`THREADS-1] xu_iu_msrovride_enab, + input pc_xu_msrovride_enab, + input pc_xu_msrovride_pr, + input pc_xu_msrovride_gs, + input pc_xu_msrovride_de, + // SIAR + input [0:`THREADS-1] pc_xu_spr_cesr1_pmae, + output [0:`THREADS-1] xu_pc_perfmon_alert, + + // LiveLock + input [0:`THREADS-1] iu_xu_instr_cpl, + output [0:`THREADS-1] xu_pc_err_llbust_attempt, + output [0:`THREADS-1] xu_pc_err_llbust_failed, + + // Resets + input pc_xu_reset_wd_complete, + input pc_xu_reset_1_complete, + input pc_xu_reset_2_complete, + input pc_xu_reset_3_complete, + output ac_tc_reset_1_request, + output ac_tc_reset_2_request, + output ac_tc_reset_3_request, + output ac_tc_reset_wd_request, + + // Err Inject + input [0:`THREADS-1] pc_xu_inj_llbust_attempt, + input [0:`THREADS-1] pc_xu_inj_llbust_failed, + input [0:`THREADS-1] pc_xu_inj_wdt_reset, + output [0:`THREADS-1] xu_pc_err_wdt_reset, + + // Parity Errors + input [0:`THREADS-1] pc_xu_inj_sprg_ecc, + output [0:`THREADS-1] xu_pc_err_sprg_ecc, + output [0:`THREADS-1] xu_pc_err_sprg_ue, + + // PERF + input [0:2] pc_xu_event_count_mode, + input pc_xu_event_bus_enable, + input [0:4*`THREADS-1] xu_event_bus_in, + output [0:4*`THREADS-1] xu_event_bus_out, + + // Debug + input [0:10] pc_xu_debug_mux_ctrls, + input [0:31] xu_debug_bus_in, + output [0:31] xu_debug_bus_out, + input [0:3] xu_coretrace_ctrls_in, + output [0:3] xu_coretrace_ctrls_out, + + // SPRs + input [54:61] an_ac_coreid, + input [32:35] an_ac_chipid_dc, + input [8:15] spr_pvr_version_dc, + input [12:15] spr_pvr_revision_dc, + input [16:19] spr_pvr_revision_minor_dc, + input [0:`THREADS-1] an_ac_ext_interrupt, + input [0:`THREADS-1] an_ac_crit_interrupt, + input [0:`THREADS-1] an_ac_perf_interrupt, + input [0:`THREADS-1] an_ac_reservation_vld, + input an_ac_tb_update_pulse, + input an_ac_tb_update_enable, + input [0:`THREADS-1] an_ac_sleep_en, + input [0:`THREADS-1] an_ac_hang_pulse, + output [0:`THREADS-1] ac_tc_machine_check, + input [0:`THREADS-1] an_ac_external_mchk, + input pc_xu_instr_trace_mode, + input [0:1] pc_xu_instr_trace_tid, + input [0:`THREADS-1] spr_dbcr0_edm, + output [0:3] spr_xucr0_clkg_ctl, + output [0:`THREADS-1] xu_iu_iac1_en, + output [0:`THREADS-1] xu_iu_iac2_en, + output [0:`THREADS-1] xu_iu_iac3_en, + output [0:`THREADS-1] xu_iu_iac4_en, + input lq_xu_spr_xucr0_cslc_xuop, + input lq_xu_spr_xucr0_cslc_binv, + input lq_xu_spr_xucr0_clo, + input lq_xu_spr_xucr0_cul, + output [0:`THREADS-1] spr_epcr_extgs, + output [0:`THREADS-1] spr_epcr_icm, + output [0:`THREADS-1] spr_epcr_gicm, + output [0:`THREADS-1] spr_msr_de, + output [0:`THREADS-1] spr_msr_pr, + output [0:`THREADS-1] spr_msr_is, + output [0:`THREADS-1] spr_msr_cm, + output [0:`THREADS-1] spr_msr_gs, + output [0:`THREADS-1] spr_msr_ee, + output [0:`THREADS-1] spr_msr_ce, + output [0:`THREADS-1] spr_msr_me, + output [0:`THREADS-1] spr_msr_fe0, + output [0:`THREADS-1] spr_msr_fe1, + output xu_lsu_spr_xucr0_clfc, + output [0:1] xu_pc_spr_ccr0_pme, + output spr_ccr2_en_dcr, + output spr_ccr2_en_trace, + output [0:8] spr_ccr2_ifratsc, + output spr_ccr2_ifrat, + output [0:8] spr_ccr2_dfratsc, + output spr_ccr2_dfrat, + output spr_ccr2_ucode_dis, + output [0:3] spr_ccr2_ap, + output spr_ccr2_en_ditc, + output spr_ccr2_en_icswx, + output spr_ccr2_notlb, + output spr_ccr2_en_pc, + output [0:3] spr_xucr0_trace_um, + output xu_lsu_spr_xucr0_mbar_ack, + output xu_lsu_spr_xucr0_tlbsync, + output spr_xucr0_cls, + output xu_lsu_spr_xucr0_aflsta, + output spr_xucr0_mddp, + output xu_lsu_spr_xucr0_cred, + output xu_lsu_spr_xucr0_rel, + output spr_xucr0_mdcp, + output xu_lsu_spr_xucr0_flsta, + output xu_lsu_spr_xucr0_l2siw, + output xu_lsu_spr_xucr0_flh2l2, + output xu_lsu_spr_xucr0_dcdis, + output xu_lsu_spr_xucr0_wlk, + output [0:`THREADS-1] spr_dbcr0_idm, + output [0:`THREADS-1] spr_dbcr0_icmp, + output [0:`THREADS-1] spr_dbcr0_brt, + output [0:`THREADS-1] spr_dbcr0_irpt, + output [0:`THREADS-1] spr_dbcr0_trap, + output [0:2*`THREADS-1] spr_dbcr0_dac1, + output [0:2*`THREADS-1] spr_dbcr0_dac2, + output [0:`THREADS-1] spr_dbcr0_ret, + output [0:2*`THREADS-1] spr_dbcr0_dac3, + output [0:2*`THREADS-1] spr_dbcr0_dac4, + output [0:`THREADS-1] spr_dbcr1_iac12m, + output [0:`THREADS-1] spr_dbcr1_iac34m, + output [0:`THREADS-1] spr_epcr_dtlbgs, + output [0:`THREADS-1] spr_epcr_itlbgs, + output [0:`THREADS-1] spr_epcr_dsigs, + output [0:`THREADS-1] spr_epcr_isigs, + output [0:`THREADS-1] spr_epcr_duvd, + output [0:`THREADS-1] spr_epcr_dgtmi, + output [0:`THREADS-1] xu_mm_spr_epcr_dmiuh, + output [0:`THREADS-1] spr_msr_ucle, + output [0:`THREADS-1] spr_msr_spv, + output [0:`THREADS-1] spr_msr_fp, + output [0:`THREADS-1] spr_msr_ds, + output [0:`THREADS-1] spr_msrp_uclep, + output spr_xucr4_mmu_mchk, + output spr_xucr4_mddmh, + + input an_ac_scan_dis_dc_b, + input an_ac_scan_diag_dc, + + // BOLT-ON + input bo_enable_2, // general bolt-on enable + input pc_xu_bo_reset, // reset + input pc_xu_bo_unload, // unload sticky bits + input pc_xu_bo_repair, // execute sticky bit decode + input pc_xu_bo_shdata, // shift data for timing write and diag loop + input pc_xu_bo_select, // select for mask and hier writes + output xu_pc_bo_fail, // fail/no-fix reg + output xu_pc_bo_diagout, + // ABIST + input an_ac_lbist_ary_wrt_thru_dc, + input pc_xu_abist_ena_dc, + input pc_xu_abist_g8t_wenb, + input [4:9] pc_xu_abist_waddr_0, + input [0:3] pc_xu_abist_di_0, + input pc_xu_abist_g8t1p_renb_0, + input [4:9] pc_xu_abist_raddr_0, + input pc_xu_abist_wl32_comp_ena, + input pc_xu_abist_raw_dc_b, + input [0:3] pc_xu_abist_g8t_dcomp, + input pc_xu_abist_g8t_bw_1, + input pc_xu_abist_g8t_bw_0, + + input pc_xu_trace_bus_enable +); + + //!! Bugspray Include: xu; + + // Power signals + wire vdd; + wire gnd; + assign vdd = 1'b1; + assign gnd = 1'b0; + + localparam AXU_TARGET_ENC = `AXU_SPARE_ENC + `GPR_POOL_ENC + `THREADS_POOL_ENC; + + // Latches + wire xu_pc_ram_done_q, xu_pc_ram_done_d ; // input=>xu_pc_ram_done_d ,act=>1'b1 + wire [64-`GPR_WIDTH:63] xu_pc_ram_data_q, xu_pc_ram_data_d ; // input=>xu_pc_ram_data_d ,act=>xu_pc_ram_done_d + wire lq_xu_gpr_ex6_we_q, lq_xu_gpr_ex6_we_d ; // input=>lq_xu_gpr_ex6_we_d ,act=>1'b1 + wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] lq_xu_gpr_ex6_wa_q, lq_xu_gpr_ex6_wa_d ; // input=>lq_xu_gpr_ex6_wa_d ,act=>lq_xu_ex5_act + wire [64-`GPR_WIDTH:63] lq_xu_gpr_ex6_wd_q, lq_xu_gpr_ex6_wd_d ; // input=>lq_xu_gpr_ex6_wd_d ,act=>lq_xu_ex5_act + // Scanchain + localparam xu_pc_ram_done_offset = 16+`THREADS; + localparam xu_pc_ram_data_offset = xu_pc_ram_done_offset + 1; + localparam lq_xu_gpr_ex6_we_offset = xu_pc_ram_data_offset + `GPR_WIDTH; + localparam lq_xu_gpr_ex6_wa_offset = lq_xu_gpr_ex6_we_offset + 1; + localparam lq_xu_gpr_ex6_wd_offset = lq_xu_gpr_ex6_wa_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC; + localparam scan_right = lq_xu_gpr_ex6_wd_offset + `GPR_WIDTH; + wire [0:scan_right-1] siv; + wire [0:scan_right-1] sov; + // Signals + wire [64-`GPR_WIDTH:63] gpr_xu0_ex1_r1d; + wire [64-`GPR_WIDTH:63] gpr_xu0_ex1_r2d; + wire [0:9] xer_xu0_ex1_r2d; + wire [0:9] xer_xu0_ex1_r3d; + wire [0:3] cr_xu0_ex1_r1d; + wire [0:3] cr_xu0_ex1_r2d; + wire [0:3] cr_xu0_ex1_r3d; + wire [64-`GPR_WIDTH:63] lr_xu0_ex1_r1d; + wire [64-`GPR_WIDTH:63] lr_xu0_ex1_r2d; + wire [64-`GPR_WIDTH:63] ctr_xu0_ex1_r2d; + wire xu0_xu1_ex3_act; + wire xu1_xu0_ex3_act; + wire [64-`GPR_WIDTH:63] xu1_xu0_ex2_rt; + wire [64-`GPR_WIDTH:63] xu1_xu0_ex3_rt; + wire [64-`GPR_WIDTH:63] xu1_xu0_ex4_rt; + wire [64-`GPR_WIDTH:63] xu1_xu0_ex5_rt; + wire [64-`GPR_WIDTH:63] xu0_xu1_ex2_rt; + wire [64-`GPR_WIDTH:63] xu0_xu1_ex3_rt; + wire [64-`GPR_WIDTH:63] xu0_xu1_ex4_rt; + wire [64-`GPR_WIDTH:63] xu0_xu1_ex5_rt; + wire [64-`GPR_WIDTH:63] xu0_xu1_ex6_rt; + wire [64-`GPR_WIDTH:63] xu0_xu1_ex7_rt; + wire [64-`GPR_WIDTH:63] xu0_xu1_ex8_rt; + wire [64-`GPR_WIDTH:63] xu0_xu1_ex6_lq_rt; + wire [64-`GPR_WIDTH:63] xu0_xu1_ex7_lq_rt; + wire [64-`GPR_WIDTH:63] xu0_xu1_ex8_lq_rt; + wire [64-`GPR_WIDTH:63] spr_xu_ex4_rd_data; + wire [64-`GPR_WIDTH:63] xu_spr_ex2_rs1; + wire [0:3] xu1_xu0_ex3_cr; + wire [0:9] xu1_xu0_ex3_xer; + wire [0:3] xu0_xu1_ex3_cr; + wire [0:3] xu0_xu1_ex4_cr; + wire [0:3] xu0_xu1_ex6_cr; + wire [0:9] xu0_xu1_ex3_xer; + wire [0:9] xu0_xu1_ex4_xer; + wire [0:9] xu0_xu1_ex6_xer; + wire xu0_gpr_ex6_we_int; + wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] xu0_gpr_ex6_wa_int; + wire [64-`GPR_WIDTH:65+`GPR_WIDTH/8] xu0_gpr_ex6_wd_int; + wire xu0_xer_ex6_we; + wire [0:`XER_POOL_ENC+`THREADS_POOL_ENC-1] xu0_xer_ex6_wa; + wire [0:9] xu0_xer_ex6_w0d; + wire xu0_cr_ex6_we; + wire [0:`CR_POOL_ENC+`THREADS_POOL_ENC-1] xu0_cr_ex6_wa; + wire [0:3] xu0_cr_ex6_w0d; + wire xu0_ctr_ex4_we; + wire [0:`CTR_POOL_ENC+`THREADS_POOL_ENC-1] xu0_ctr_ex4_wa; + wire [64-`GPR_WIDTH:63] xu0_ctr_ex4_w0d; + wire xu0_lr_ex4_we; + wire [0:`BR_POOL_ENC+`THREADS_POOL_ENC-1] xu0_lr_ex4_wa; + wire [64-`GPR_WIDTH:63] xu0_lr_ex4_w0d; + wire spr_xu_ord_read_done; + wire spr_xu_ord_write_done; + wire spr_dec_ex4_spr_hypv; + wire spr_dec_ex4_spr_illeg; + wire spr_dec_ex4_spr_priv; + wire spr_dec_ex4_np1_flush; + wire [0:`THREADS-1] spr_msr_cm_int; + wire [0:`THREADS-1] spr_msr_gs_int; + wire [0:`THREADS-1] spr_msr_pr_int; + wire [0:`THREADS-1] spr_epcr_dgtmi_int; + wire spr_ccr2_notlb_int; + wire [64-`GPR_WIDTH:63] gpr_xu1_ex1_r1d; + wire [64-`GPR_WIDTH:63] gpr_xu1_ex1_r2d; + wire [0:9] xer_xu1_ex1_r3d; + wire [0:3] cr_xu1_ex1_r3d; + wire xu1_gpr_ex3_we_int; + wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] xu1_gpr_ex3_wa_int; + wire [64-`GPR_WIDTH:65+`GPR_WIDTH/8] xu1_gpr_ex3_wd_int; + wire xu1_xer_ex3_we; + wire [0:`XER_POOL_ENC+`THREADS_POOL_ENC-1] xu1_xer_ex3_wa; + wire [0:9] xu1_xer_ex3_w0d; + wire xu1_cr_ex3_we; + wire [0:`CR_POOL_ENC+`THREADS_POOL_ENC-1] xu1_cr_ex3_wa; + wire [0:3] xu1_cr_ex3_w0d; + wire spr_ccr2_en_attn; + wire spr_ccr4_en_dnh; + wire spr_ccr2_en_pc_int; + wire func_sl_thold_0,func_slp_sl_thold_0; + wire [0:10] spr_debug_mux_ctrls; + wire [0:31] spr_debug_data_in; + wire [0:31] spr_debug_data_out; + wire [0:11] spr_trigger_data_in; + wire [0:11] spr_trigger_data_out; + wire xu_spr_ord_ready; + wire xu_spr_ord_flush; + wire xu0_pc_ram_done; + wire xu1_pc_ram_done; + wire [64-`GPR_WIDTH:63] xu0_pc_ram_data; + wire [64-`GPR_WIDTH:63] xu1_pc_ram_data; + wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] rv_xu0_s1_p_int; + wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] rv_xu0_s2_p_int; + wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] rv_xu0_s3_p_int; + wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] rv_xu1_s1_p_int; + wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] rv_xu1_s2_p_int; + wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] rv_xu1_s3_p_int; + wire [0:`GPR_WIDTH/8-1] lq_xu_gpr_ex6_par; + wire [(64-`GPR_WIDTH):66+(`GPR_WIDTH/8-1)] lq_xu_gpr_ex6_wd_int; + wire [0:3] lq_xu_cr_ex5_wd; + wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] lq_xu_gpr_rel_wa_int; + wire [(64-`GPR_WIDTH):66+(`GPR_WIDTH/8-1)] lq_xu_gpr_rel_wd_int; + wire [0:9] xer_lq_cp_r0d; + wire [0:9] xer_lq_cp_r1d; + wire [0:`XER_POOL_ENC+`THREADS_POOL_ENC-1] iu_rf_xer_t0_p_int; + wire [0:`XER_POOL_ENC+`THREADS_POOL_ENC-1] iu_rf_xer_t1_p_int; + wire rv_xu0_s3_gpr_v; + `ifndef THREADS1 + wire [64-`GPR_WIDTH:63] spr_dvc1_t1; + wire [64-`GPR_WIDTH:63] spr_dvc2_t1; + `endif + wire [64-`GPR_WIDTH:63] spr_dvc1_t0; + wire [64-`GPR_WIDTH:63] spr_dvc2_t0; + wire xu1_xu0_ex2_abort; + wire xu0_xu1_ex2_abort; + wire xu0_xu1_ex6_abort; + wire [0:`THREADS-1] div_spr_running; + wire [0:`THREADS-1] mul_spr_running; + wire [0:31] spr_xesr1; + wire [0:31] spr_xesr2; + wire [0:`THREADS-1] perf_event_en; + + wire [0:31] xu0_debug_bus_in; + wire [0:31] xu0_debug_bus_out; + wire [0:3] xu0_coretrace_ctrls_in; + wire [0:3] xu0_coretrace_ctrls_out; + wire [0:31] xu1_debug_bus_in; + wire [0:31] xu1_debug_bus_out; + wire [0:3] xu1_coretrace_ctrls_in; + wire [0:3] xu1_coretrace_ctrls_out; + + + wire tiup; + + //<> + assign func_slp_sl_thold_0 = ~func_slp_sl_thold_0_b; + assign func_sl_thold_0 = ~func_sl_thold_0_b; + assign spr_debug_mux_ctrls = {11{1'b0}}; + assign spr_debug_data_in = {32{1'b0}}; + //<> + + assign tiup = 1'b1; + + `ifdef THREADS1 + assign iu_rf_xer_t0_p_int = iu_rf_xer_p_t0; + assign iu_rf_xer_t1_p_int = {`XER_POOL_ENC+`THREADS_POOL_ENC{1'b0}}; + assign xer_lq_cp_rd = xer_lq_cp_r0d[0:0]; + `else + assign iu_rf_xer_t0_p_int = {iu_rf_xer_p_t0, 1'b0}; + assign iu_rf_xer_t1_p_int = {iu_rf_xer_p_t1, 1'b1}; + assign xer_lq_cp_rd = {xer_lq_cp_r0d[0], xer_lq_cp_r1d[0]}; + `endif + + assign spr_msr_cm = spr_msr_cm_int; + assign spr_msr_gs = spr_msr_gs_int; + assign spr_msr_pr = spr_msr_pr_int; + assign spr_epcr_dgtmi = spr_epcr_dgtmi_int; + assign spr_ccr2_notlb = spr_ccr2_notlb_int; + assign spr_ccr2_en_pc = spr_ccr2_en_pc_int; + + assign xu0_gpr_ex6_we = xu0_gpr_ex6_we_int; + assign xu0_gpr_ex6_wa = xu0_gpr_ex6_wa_int; + assign xu0_gpr_ex6_wd = xu0_gpr_ex6_wd_int[64 - `GPR_WIDTH:63 + `GPR_WIDTH/8]; // Fix me + assign xu1_gpr_ex3_we = xu1_gpr_ex3_we_int; + assign xu1_gpr_ex3_wa = xu1_gpr_ex3_wa_int; + assign xu1_gpr_ex3_wd = xu1_gpr_ex3_wd_int[64 - `GPR_WIDTH:63 + `GPR_WIDTH/8]; // Fix me + + //------------------------------------------------------------------- + // LQ Load Hit GPR Update + //------------------------------------------------------------------- + assign lq_xu_gpr_ex6_we_d = lq_xu_gpr_ex5_we; + assign lq_xu_gpr_ex6_wa_d = lq_xu_gpr_ex5_wa[AXU_TARGET_ENC - (`GPR_POOL_ENC + `THREADS_POOL_ENC):AXU_TARGET_ENC - 1]; + assign lq_xu_gpr_ex6_wd_d = lq_xu_ex5_rt[128 - `GPR_WIDTH:127]; + + generate begin : parGen + genvar b; + for (b=0;b<=`GPR_WIDTH/8-1;b=b+1) + begin : parGen + assign lq_xu_gpr_ex6_par[b] = ^(lq_xu_gpr_ex6_wd_q[(64 - `GPR_WIDTH) + b * 8:(64 - `GPR_WIDTH) + (b * 8) + 7]); + end + end + endgenerate + + assign lq_xu_gpr_ex6_wd_int = {lq_xu_gpr_ex6_wd_q, lq_xu_gpr_ex6_par, 2'b10}; + + //------------------------------------------------------------------- + // LQ Reload GPR Update + //------------------------------------------------------------------- + // GPR Reload Write Address + assign lq_xu_gpr_rel_wa_int = lq_xu_gpr_rel_wa[AXU_TARGET_ENC-(`GPR_POOL_ENC+`THREADS_POOL_ENC):AXU_TARGET_ENC-1]; + // GPR Reload Write Data + assign lq_xu_gpr_rel_wd_int[(64-`GPR_WIDTH):63] = lq_xu_gpr_rel_wd[(128-`GPR_WIDTH):127]; + // GPR Reload Write Data Parity + assign lq_xu_gpr_rel_wd_int[64:63+`GPR_WIDTH/8] = lq_xu_gpr_rel_wd[`STQ_DATA_SIZE+`STQ_DATA_SIZE/8-`GPR_WIDTH/8:`STQ_DATA_SIZE+`STQ_DATA_SIZE/8-1]; + assign lq_xu_gpr_rel_wd_int[65+(`GPR_WIDTH/8-1):66+(`GPR_WIDTH/8-1)] = 2'b11; + + // LQ CR Data + assign lq_xu_cr_ex5_wd = lq_xu_ex5_cr; + + assign xu_pc_ram_done_d = xu0_pc_ram_done | xu1_pc_ram_done; + assign xu_pc_ram_data_d = (xu0_pc_ram_done == 1'b1) ? xu0_pc_ram_data : + xu1_pc_ram_data; + + assign xu_pc_ram_done = xu_pc_ram_done_q; + assign xu_pc_ram_data = xu_pc_ram_data_q; + + assign xu0_lq_ex3_act = xu0_xu1_ex3_act; + assign xu1_lq_ex3_act = xu1_xu0_ex3_act; + + `ifdef THREADS1 + assign rv_xu0_s1_p_int = rv_xu0_s1_p; + assign rv_xu0_s2_p_int = rv_xu0_s2_p; + assign rv_xu0_s3_p_int = rv_xu0_s3_p; + assign rv_xu1_s1_p_int = rv_xu1_s1_p; + assign rv_xu1_s2_p_int = rv_xu1_s2_p; + assign rv_xu1_s3_p_int = rv_xu1_s3_p; + `else + assign rv_xu0_s1_p_int ={rv_xu0_s1_p, rv_xu0_vld[1]}; + assign rv_xu0_s2_p_int ={rv_xu0_s2_p, rv_xu0_vld[1]}; + assign rv_xu0_s3_p_int ={rv_xu0_s3_p, rv_xu0_vld[1]}; + assign rv_xu1_s1_p_int ={rv_xu1_s1_p, rv_xu1_vld[1]}; + assign rv_xu1_s2_p_int ={rv_xu1_s2_p, rv_xu1_vld[1]}; + assign rv_xu1_s3_p_int ={rv_xu1_s3_p, rv_xu1_vld[1]}; + `endif + + assign rv_xu0_s3_gpr_v = |(rv_xu0_vld) & rv_xu0_s3_v; + + //------------------------------------------------------------------- + // AXU Pass Thru Interface + //------------------------------------------------------------------- + assign xu_axu_lq_ex4_addr = lq_xu_axu_ex4_addr; + assign xu_axu_lq_ex5_we = lq_xu_axu_ex5_we; + assign xu_axu_lq_ex5_le = lq_xu_axu_ex5_le; + assign xu_axu_lq_ex5_wa = lq_xu_gpr_ex5_wa; + assign xu_axu_lq_ex5_wd = lq_xu_ex5_rt; + assign xu_axu_lq_ex5_abort = lq_xu_ex5_abort; + + assign xu_axu_lq_rel_we = lq_xu_axu_rel_we; + assign xu_axu_lq_rel_le = lq_xu_axu_rel_le; + assign xu_axu_lq_rel_wa = lq_xu_gpr_rel_wa; + assign xu_axu_lq_rel_wd = lq_xu_gpr_rel_wd; + + assign xu_lq_axu_ex_stq_val = axu_xu_lq_ex_stq_val; + assign xu_lq_axu_ex_stq_itag = axu_xu_lq_ex_stq_itag; + assign xu_lq_axu_exp1_stq_data = axu_xu_lq_exp1_stq_data; + + + //------------------------------------------------------------------- + // Debug Bus Wrap + //------------------------------------------------------------------- + assign xu0_debug_bus_in = xu_debug_bus_in; + assign xu0_coretrace_ctrls_in = xu_coretrace_ctrls_in; + + assign xu1_debug_bus_in = xu0_debug_bus_out; + assign xu1_coretrace_ctrls_in = xu0_coretrace_ctrls_out; + + assign xu_debug_bus_out = xu1_debug_bus_out; + assign xu_coretrace_ctrls_out = xu1_coretrace_ctrls_out; + + + xu0 xu0( + .nclk(nclk), + .vdd(vdd), + .gnd(gnd), + .pc_xu_ccflush_dc(pc_xu_ccflush_dc), + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .func_sl_force(func_sl_force), + .func_sl_thold_0_b(func_sl_thold_0_b), + .sg_0(sg_0), + .scan_in(siv[0]), + .scan_out(sov[0]), + .xu0_pc_ram_done(xu0_pc_ram_done), + .cp_flush(cp_flush), + .iu_br_t0_flush_ifar(iu_br_t0_flush_ifar), + .cp_next_itag_t0(cp_next_itag_t0), + `ifndef THREADS1 + .iu_br_t1_flush_ifar(iu_br_t1_flush_ifar), + .cp_next_itag_t1(cp_next_itag_t1), + `endif + .br_iu_execute_vld(br_iu_execute_vld), + .br_iu_itag(br_iu_itag), + .br_iu_taken(br_iu_taken), + .br_iu_bta(br_iu_bta), + .br_iu_gshare(br_iu_gshare), + .br_iu_ls_ptr(br_iu_ls_ptr), + .br_iu_ls_data(br_iu_ls_data), + .br_iu_ls_update(br_iu_ls_update), + .br_iu_redirect(br_iu_redirect), + .br_iu_perf_events(br_iu_perf_events), + .rv_xu0_vld(rv_xu0_vld), + .rv_xu0_ex0_ord(rv_xu0_ex0_ord), + .rv_xu0_ex0_fusion(rv_xu0_ex0_fusion), + .rv_xu0_ex0_instr(rv_xu0_ex0_instr), + .rv_xu0_ex0_ifar(rv_xu0_ex0_ifar), + .rv_xu0_ex0_itag(rv_xu0_ex0_itag), + .rv_xu0_ex0_ucode(rv_xu0_ex0_ucode), + .rv_xu0_ex0_bta_val(rv_xu0_ex0_bta_val), + .rv_xu0_ex0_pred_bta(rv_xu0_ex0_pred_bta), + .rv_xu0_ex0_pred(rv_xu0_ex0_pred), + .rv_xu0_ex0_ls_ptr(rv_xu0_ex0_ls_ptr), + .rv_xu0_ex0_bh_update(rv_xu0_ex0_bh_update), + .rv_xu0_ex0_gshare(rv_xu0_ex0_gshare), + .rv_xu0_ex0_s1_v(rv_xu0_ex0_s1_v), + .rv_xu0_ex0_s2_v(rv_xu0_ex0_s2_v), + .rv_xu0_ex0_s2_t(rv_xu0_ex0_s2_t), + .rv_xu0_ex0_s3_v(rv_xu0_ex0_s3_v), + .rv_xu0_ex0_s3_t(rv_xu0_ex0_s3_t), + .rv_xu0_ex0_t1_v(rv_xu0_ex0_t1_v), + .rv_xu0_ex0_t1_p(rv_xu0_ex0_t1_p), + .rv_xu0_ex0_t1_t(rv_xu0_ex0_t1_t), + .rv_xu0_ex0_t2_v(rv_xu0_ex0_t2_v), + .rv_xu0_ex0_t2_p(rv_xu0_ex0_t2_p), + .rv_xu0_ex0_t2_t(rv_xu0_ex0_t2_t), + .rv_xu0_ex0_t3_v(rv_xu0_ex0_t3_v), + .rv_xu0_ex0_t3_p(rv_xu0_ex0_t3_p), + .rv_xu0_ex0_t3_t(rv_xu0_ex0_t3_t), + .rv_xu0_ex0_spec_flush(rv_xu0_ex0_spec_flush), + .rv_xu0_ex1_spec_flush(rv_xu0_ex1_spec_flush), + .rv_xu0_ex2_spec_flush(rv_xu0_ex2_spec_flush), + .rv_xu0_s1_fxu0_sel(rv_xu0_s1_fxu0_sel), + .rv_xu0_s2_fxu0_sel(rv_xu0_s2_fxu0_sel), + .rv_xu0_s3_fxu0_sel(rv_xu0_s3_fxu0_sel), + .rv_xu0_s1_fxu1_sel(rv_xu0_s1_fxu1_sel), + .rv_xu0_s2_fxu1_sel(rv_xu0_s2_fxu1_sel), + .rv_xu0_s3_fxu1_sel(rv_xu0_s3_fxu1_sel), + .rv_xu0_s1_lq_sel(rv_xu0_s1_lq_sel), + .rv_xu0_s2_lq_sel(rv_xu0_s2_lq_sel), + .rv_xu0_s3_lq_sel(rv_xu0_s3_lq_sel), + .rv_xu0_s1_rel_sel(rv_xu0_s1_rel_sel), + .rv_xu0_s2_rel_sel(rv_xu0_s2_rel_sel), + .xu0_rv_ord_complete(xu0_rv_ord_complete), + .xu0_rv_ord_itag(xu0_rv_ord_itag), + .xu0_rv_hold_all(xu0_rv_hold_all), + .gpr_xu0_ex1_r1d(gpr_xu0_ex1_r1d), + .gpr_xu0_ex1_r2d(gpr_xu0_ex1_r2d), + .xer_xu0_ex1_r2d(xer_xu0_ex1_r2d), + .xer_xu0_ex1_r3d(xer_xu0_ex1_r3d), + .cr_xu0_ex1_r1d(cr_xu0_ex1_r1d), + .cr_xu0_ex1_r2d(cr_xu0_ex1_r2d), + .cr_xu0_ex1_r3d(cr_xu0_ex1_r3d), + .lr_xu0_ex1_r1d(lr_xu0_ex1_r1d), + .lr_xu0_ex1_r2d(lr_xu0_ex1_r2d), + .ctr_xu0_ex1_r2d(ctr_xu0_ex1_r2d), + .xu0_xu1_ex3_act(xu0_xu1_ex3_act), + .xu1_xu0_ex3_act(xu1_xu0_ex3_act), + .lq_xu_ex5_act(lq_xu_ex5_act), + .xu1_xu0_ex2_abort(xu1_xu0_ex2_abort), + .xu1_xu0_ex2_rt(xu1_xu0_ex2_rt), + .xu1_xu0_ex3_rt(xu1_xu0_ex3_rt), + .xu1_xu0_ex4_rt(xu1_xu0_ex4_rt), + .xu1_xu0_ex5_rt(xu1_xu0_ex5_rt), + .lq_xu_ex5_abort(lq_xu_ex5_abort), + .lq_xu_ex5_rt(lq_xu_ex5_rt), + .lq_xu_ex5_data(lq_xu_ex5_data), + .lq_xu_rel_act(lq_xu_gpr_rel_we), + .lq_xu_rel_rt(lq_xu_gpr_rel_wd_int[(64-`GPR_WIDTH):63]), + .iu_xu_ex5_data(iu_xu_ex5_data), + .spr_xu_ex4_rd_data(spr_xu_ex4_rd_data), + .xu_spr_ex2_rs1(xu_spr_ex2_rs1), + .lq_xu_ex5_cr(lq_xu_ex5_cr), + .xu1_xu0_ex3_cr(xu1_xu0_ex3_cr), + .xu1_xu0_ex3_xer(xu1_xu0_ex3_xer), + .xu_iu_ord_ready(xu_iu_ord_ready), + .xu_iu_act(xu_iu_act), + .xu_iu_val(xu_iu_val), + .xu_iu_is_eratre(xu_iu_is_eratre), + .xu_iu_is_eratwe(xu_iu_is_eratwe), + .xu_iu_is_eratsx(xu_iu_is_eratsx), + .xu_iu_is_eratilx(xu_iu_is_eratilx), + .xu_iu_is_erativax(xu_iu_is_erativax), + .xu_iu_ws(xu_iu_ws), + .xu_iu_t(xu_iu_t), + .xu_iu_rs_is(xu_iu_rs_is), + .xu_iu_ra_entry(xu_iu_ra_entry), + .xu_iu_rb(xu_iu_rb), + .xu_iu_rs_data(xu_iu_rs_data), + .iu_xu_ord_read_done(iu_xu_ord_read_done), + .iu_xu_ord_write_done(iu_xu_ord_write_done), + .iu_xu_ord_n_flush_req(iu_xu_ord_n_flush_req), + .iu_xu_ord_par_err(iu_xu_ord_par_err), + .xu_lq_ord_ready(xu_lq_ord_ready), + .xu_lq_act(xu_lq_act), + .xu_lq_val(xu_lq_val), + .xu_lq_hold_req(xu_lq_hold_req), + .xu_lq_is_eratre(xu_lq_is_eratre), + .xu_lq_is_eratwe(xu_lq_is_eratwe), + .xu_lq_is_eratsx(xu_lq_is_eratsx), + .xu_lq_is_eratilx(xu_lq_is_eratilx), + .xu_lq_ws(xu_lq_ws), + .xu_lq_t(xu_lq_t), + .xu_lq_rs_is(xu_lq_rs_is), + .xu_lq_ra_entry(xu_lq_ra_entry), + .xu_lq_rb(xu_lq_rb), + .xu_lq_rs_data(xu_lq_rs_data), + .lq_xu_ord_read_done(lq_xu_ord_read_done), + .lq_xu_ord_write_done(lq_xu_ord_write_done), + .lq_xu_ord_n_flush_req(lq_xu_ord_n_flush_req), + .lq_xu_ord_par_err(lq_xu_ord_par_err), + .xu_mm_ord_ready(xu_mm_ord_ready), + .xu_mm_act(xu_mm_act), + .xu_mm_val(xu_mm_val), + .xu_mm_itag(xu_mm_itag), + .xu_mm_is_tlbre(xu_mm_is_tlbre), + .xu_mm_is_tlbwe(xu_mm_is_tlbwe), + .xu_mm_is_tlbsx(xu_mm_is_tlbsx), + .xu_mm_is_tlbsxr(xu_mm_is_tlbsxr), + .xu_mm_is_tlbsrx(xu_mm_is_tlbsrx), + .xu_mm_is_tlbivax(xu_mm_is_tlbivax), + .xu_mm_is_tlbilx(xu_mm_is_tlbilx), + .xu_mm_ra_entry(xu_mm_ra_entry), + .xu_mm_rb(xu_mm_rb), + .mm_xu_itag(mm_xu_itag), + .mm_xu_ord_n_flush_req(mm_xu_ord_n_flush_req), + .mm_xu_ord_read_done(mm_xu_ord_read_done), + .mm_xu_ord_write_done(mm_xu_ord_write_done), + .mm_xu_tlb_miss(mm_xu_tlb_miss), + .mm_xu_lrat_miss(mm_xu_lrat_miss), + .mm_xu_tlb_inelig(mm_xu_tlb_inelig), + .mm_xu_pt_fault(mm_xu_pt_fault), + .mm_xu_hv_priv(mm_xu_hv_priv), + .mm_xu_illeg_instr(mm_xu_illeg_instr), + .mm_xu_tlb_multihit(mm_xu_tlb_multihit), + .mm_xu_tlb_par_err(mm_xu_tlb_par_err), + .mm_xu_lru_par_err(mm_xu_lru_par_err), + .mm_xu_local_snoop_reject(mm_xu_local_snoop_reject), + .mm_xu_mmucr0_tlbsel_t0(mm_xu_mmucr0_tlbsel_t0), + `ifndef THREADS1 + .mm_xu_mmucr0_tlbsel_t1(mm_xu_mmucr0_tlbsel_t1), + `endif + .mm_xu_tlbwe_binv(mm_xu_tlbwe_binv), + .mm_xu_cr0_eq(mm_xu_cr0_eq), // for record forms + .mm_xu_cr0_eq_valid(mm_xu_cr0_eq_valid), // for record forms + .xu_spr_ord_ready(xu_spr_ord_ready), + .xu_spr_ord_flush(xu_spr_ord_flush), + .xu0_xu1_ex2_abort(xu0_xu1_ex2_abort), + .xu0_xu1_ex6_abort(xu0_xu1_ex6_abort), + .xu0_lq_ex3_abort(xu0_lq_ex3_abort), + .xu0_xu1_ex2_rt(xu0_xu1_ex2_rt), + .xu0_xu1_ex3_rt(xu0_xu1_ex3_rt), + .xu0_xu1_ex4_rt(xu0_xu1_ex4_rt), + .xu0_xu1_ex5_rt(xu0_xu1_ex5_rt), + .xu0_xu1_ex6_rt(xu0_xu1_ex6_rt), + .xu0_xu1_ex7_rt(xu0_xu1_ex7_rt), + .xu0_xu1_ex8_rt(xu0_xu1_ex8_rt), + .xu0_xu1_ex6_lq_rt(xu0_xu1_ex6_lq_rt), + .xu0_xu1_ex7_lq_rt(xu0_xu1_ex7_lq_rt), + .xu0_xu1_ex8_lq_rt(xu0_xu1_ex8_lq_rt), + .xu0_lq_ex3_rt(xu0_lq_ex3_rt), + .xu0_lq_ex4_rt(xu0_lq_ex4_rt), + .xu0_lq_ex6_act(xu0_lq_ex6_act), + .xu0_lq_ex6_rt(xu0_lq_ex6_rt), + .xu0_pc_ram_data(xu0_pc_ram_data), + .xu0_xu1_ex3_cr(xu0_xu1_ex3_cr), + .xu0_xu1_ex4_cr(xu0_xu1_ex4_cr), + .xu0_xu1_ex6_cr(xu0_xu1_ex6_cr), + .xu0_xu1_ex3_xer(xu0_xu1_ex3_xer), + .xu0_xu1_ex4_xer(xu0_xu1_ex4_xer), + .xu0_xu1_ex6_xer(xu0_xu1_ex6_xer), + .xu0_rv_ex2_s1_abort(xu0_rv_ex2_s1_abort), + .xu0_rv_ex2_s2_abort(xu0_rv_ex2_s2_abort), + .xu0_rv_ex2_s3_abort(xu0_rv_ex2_s3_abort), + .xu0_gpr_ex6_we(xu0_gpr_ex6_we_int), + .xu0_gpr_ex6_wa(xu0_gpr_ex6_wa_int), + .xu0_gpr_ex6_wd(xu0_gpr_ex6_wd_int), + .xu0_xer_ex6_we(xu0_xer_ex6_we), + .xu0_xer_ex6_wa(xu0_xer_ex6_wa), + .xu0_xer_ex6_w0d(xu0_xer_ex6_w0d), + .xu0_cr_ex6_we(xu0_cr_ex6_we), + .xu0_cr_ex6_wa(xu0_cr_ex6_wa), + .xu0_cr_ex6_w0d(xu0_cr_ex6_w0d), + .xu0_ctr_ex4_we(xu0_ctr_ex4_we), + .xu0_ctr_ex4_wa(xu0_ctr_ex4_wa), + .xu0_ctr_ex4_w0d(xu0_ctr_ex4_w0d), + .xu0_lr_ex4_we(xu0_lr_ex4_we), + .xu0_lr_ex4_wa(xu0_lr_ex4_wa), + .xu0_lr_ex4_w0d(xu0_lr_ex4_w0d), + .xu0_iu_execute_vld(xu0_iu_execute_vld), + .xu0_iu_itag(xu0_iu_itag), + .xu0_iu_mtiar(xu0_iu_mtiar), + .xu0_iu_exception_val(xu0_iu_exception_val), + .xu0_iu_exception(xu0_iu_exception), + .xu0_iu_n_flush(xu0_iu_n_flush), + .xu0_iu_np1_flush(xu0_iu_np1_flush), + .xu0_iu_flush2ucode(xu0_iu_flush2ucode), + .xu0_iu_perf_events(xu0_iu_perf_events), + .xu0_iu_bta(xu0_iu_bta), + .xu_iu_np1_async_flush(xu_iu_np1_async_flush), + .iu_xu_async_complete(iu_xu_async_complete), + .iu_xu_credits_returned(iu_xu_credits_returned), + .xu_iu_pri_val(xu_iu_pri_val), + .xu_iu_pri(xu_iu_pri), + .spr_xu_ord_read_done(spr_xu_ord_read_done), + .spr_xu_ord_write_done(spr_xu_ord_write_done), + .spr_dec_ex4_spr_hypv(spr_dec_ex4_spr_hypv), + .spr_dec_ex4_spr_illeg(spr_dec_ex4_spr_illeg), + .spr_dec_ex4_spr_priv(spr_dec_ex4_spr_priv), + .spr_dec_ex4_np1_flush(spr_dec_ex4_np1_flush), + .xu_slowspr_val_in(xu_slowspr_val_in), + .xu_slowspr_rw_in(xu_slowspr_rw_in), + .xu_slowspr_data_in(xu_slowspr_data_in), + .xu_slowspr_done_in(xu_slowspr_done_in), + .spr_msr_cm(spr_msr_cm_int), + .spr_msr_gs(spr_msr_gs_int), + .spr_msr_pr(spr_msr_pr_int), + .spr_epcr_dgtmi(spr_epcr_dgtmi_int), + .spr_ccr2_notlb(spr_ccr2_notlb_int), + .spr_ccr2_en_attn(spr_ccr2_en_attn), + .spr_ccr4_en_dnh(spr_ccr4_en_dnh), + .spr_ccr2_en_pc(spr_ccr2_en_pc_int), + .spr_xesr1(spr_xesr1), + .spr_xesr2(spr_xesr2), + .perf_event_en(perf_event_en), + .pc_xu_ram_active(pc_xu_ram_active), + .div_spr_running(div_spr_running), + .mul_spr_running(mul_spr_running), + .pc_xu_debug_mux_ctrls(pc_xu_debug_mux_ctrls), + .xu0_debug_bus_in(xu0_debug_bus_in), + .xu0_debug_bus_out(xu0_debug_bus_out), + .xu0_coretrace_ctrls_in(xu0_coretrace_ctrls_in), + .xu0_coretrace_ctrls_out(xu0_coretrace_ctrls_out) + ); + + + xu1 xu1( + .nclk(nclk), + .vdd(vdd), + .gnd(gnd), + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .func_sl_force(func_sl_force), + .func_sl_thold_0_b(func_sl_thold_0_b), + .sg_0(sg_0), + .scan_in(siv[1]), + .scan_out(sov[1]), + .xu1_pc_ram_done(xu1_pc_ram_done), + .xu1_pc_ram_data(xu1_pc_ram_data), + .xu0_xu1_ex3_act(xu0_xu1_ex3_act), + .lq_xu_ex5_act(lq_xu_ex5_act), + .spr_msr_cm(spr_msr_cm_int), // 0=> 0, + .cp_flush(cp_flush), + .rv_xu1_vld(rv_xu1_vld), + .rv_xu1_ex0_instr(rv_xu1_ex0_instr), + .rv_xu1_ex0_itag(rv_xu1_ex0_itag), + .rv_xu1_ex0_isstore(rv_xu1_ex0_isstore), + .rv_xu1_ex0_ucode(rv_xu1_ex0_ucode), + .rv_xu1_s1_v(rv_xu1_s1_v), + .rv_xu1_s2_v(rv_xu1_s2_v), + .rv_xu1_s3_v(rv_xu1_s3_v), + .rv_xu1_ex0_t1_v(rv_xu1_ex0_t1_v), + .rv_xu1_ex0_t1_p(rv_xu1_ex0_t1_p), + .rv_xu1_ex0_t2_v(rv_xu1_ex0_t2_v), + .rv_xu1_ex0_t2_p(rv_xu1_ex0_t2_p), + .rv_xu1_ex0_t3_v(rv_xu1_ex0_t3_v), + .rv_xu1_ex0_t3_p(rv_xu1_ex0_t3_p), + .rv_xu1_ex0_s1_v(rv_xu1_ex0_s1_v), + .rv_xu1_ex0_s3_t(rv_xu1_ex0_s3_t), + .rv_xu1_ex0_spec_flush(rv_xu1_ex0_spec_flush), + .rv_xu1_ex1_spec_flush(rv_xu1_ex1_spec_flush), + .rv_xu1_ex2_spec_flush(rv_xu1_ex2_spec_flush), + .rv_xu1_s1_fxu0_sel(rv_xu1_s1_fxu0_sel), + .rv_xu1_s2_fxu0_sel(rv_xu1_s2_fxu0_sel), + .rv_xu1_s3_fxu0_sel(rv_xu1_s3_fxu0_sel), + .rv_xu1_s1_fxu1_sel(rv_xu1_s1_fxu1_sel), + .rv_xu1_s2_fxu1_sel(rv_xu1_s2_fxu1_sel), + .rv_xu1_s3_fxu1_sel(rv_xu1_s3_fxu1_sel), + .rv_xu1_s1_lq_sel(rv_xu1_s1_lq_sel), + .rv_xu1_s2_lq_sel(rv_xu1_s2_lq_sel), + .rv_xu1_s3_lq_sel(rv_xu1_s3_lq_sel), + .rv_xu1_s1_rel_sel(rv_xu1_s1_rel_sel), + .rv_xu1_s2_rel_sel(rv_xu1_s2_rel_sel), + .xu1_lq_ex2_stq_val(xu1_lq_ex2_stq_val), + .xu1_lq_ex2_stq_itag(xu1_lq_ex2_stq_itag), + .xu1_lq_ex2_stq_size(xu1_lq_ex2_stq_size), + .xu1_lq_ex3_illeg_lswx(xu1_lq_ex3_illeg_lswx), + .xu1_lq_ex3_strg_noop(xu1_lq_ex3_strg_noop), + .xu1_lq_ex2_stq_dvc1_cmp(xu1_lq_ex2_stq_dvc1_cmp), + .xu1_lq_ex2_stq_dvc2_cmp(xu1_lq_ex2_stq_dvc2_cmp), + .xu1_iu_execute_vld(xu1_iu_execute_vld), + .xu1_iu_itag(xu1_iu_itag), + .xu_iu_ucode_xer_val(xu_iu_ucode_xer_val), + .xu_iu_ucode_xer(xu_iu_ucode_xer), + .xu1_rv_ex2_s1_abort(xu1_rv_ex2_s1_abort), + .xu1_rv_ex2_s2_abort(xu1_rv_ex2_s2_abort), + .xu1_rv_ex2_s3_abort(xu1_rv_ex2_s3_abort), + .gpr_xu1_ex1_r1d(gpr_xu1_ex1_r1d), + .gpr_xu1_ex1_r2d(gpr_xu1_ex1_r2d), + .xer_xu1_ex1_r3d(xer_xu1_ex1_r3d), + .cr_xu1_ex1_r3d(cr_xu1_ex1_r3d), + .xu1_xu0_ex3_act(xu1_xu0_ex3_act), + .xu0_xu1_ex2_abort(xu0_xu1_ex2_abort), + .xu0_xu1_ex6_abort(xu0_xu1_ex6_abort), + .lq_xu_ex5_abort(lq_xu_ex5_abort), + .xu1_xu0_ex2_abort(xu1_xu0_ex2_abort), + .xu1_lq_ex3_abort(xu1_lq_ex3_abort), + .xu0_xu1_ex2_rt(xu0_xu1_ex2_rt), + .xu0_xu1_ex3_rt(xu0_xu1_ex3_rt), + .xu0_xu1_ex4_rt(xu0_xu1_ex4_rt), + .xu0_xu1_ex5_rt(xu0_xu1_ex5_rt), + .xu0_xu1_ex6_rt(xu0_xu1_ex6_rt), + .xu0_xu1_ex7_rt(xu0_xu1_ex7_rt), + .xu0_xu1_ex8_rt(xu0_xu1_ex8_rt), + .xu0_xu1_ex6_lq_rt(xu0_xu1_ex6_lq_rt), + .xu0_xu1_ex7_lq_rt(xu0_xu1_ex7_lq_rt), + .xu0_xu1_ex8_lq_rt(xu0_xu1_ex8_lq_rt), + .lq_xu_ex5_rt(lq_xu_ex5_rt), + .lq_xu_rel_act(lq_xu_gpr_rel_we), + .lq_xu_rel_rt(lq_xu_gpr_rel_wd_int[(64-`GPR_WIDTH):63]), + .lq_xu_ex5_cr(lq_xu_ex5_cr), + .xu0_xu1_ex3_cr(xu0_xu1_ex3_cr), + .xu0_xu1_ex4_cr(xu0_xu1_ex4_cr), + .xu0_xu1_ex6_cr(xu0_xu1_ex6_cr), + .xu0_xu1_ex3_xer(xu0_xu1_ex3_xer), + .xu0_xu1_ex4_xer(xu0_xu1_ex4_xer), + .xu0_xu1_ex6_xer(xu0_xu1_ex6_xer), + .xu1_xu0_ex2_rt(xu1_xu0_ex2_rt), + .xu1_xu0_ex3_rt(xu1_xu0_ex3_rt), + .xu1_xu0_ex4_rt(xu1_xu0_ex4_rt), + .xu1_xu0_ex5_rt(xu1_xu0_ex5_rt), + .xu1_lq_ex3_rt(xu1_lq_ex3_rt), + .xu1_xu0_ex3_cr(xu1_xu0_ex3_cr), + .xu1_xu0_ex3_xer(xu1_xu0_ex3_xer), + .xu1_gpr_ex3_we(xu1_gpr_ex3_we_int), + .xu1_gpr_ex3_wa(xu1_gpr_ex3_wa_int), + .xu1_gpr_ex3_wd(xu1_gpr_ex3_wd_int), + .xu1_xer_ex3_we(xu1_xer_ex3_we), + .xu1_xer_ex3_wa(xu1_xer_ex3_wa), + .xu1_xer_ex3_w0d(xu1_xer_ex3_w0d), + .xu1_cr_ex3_we(xu1_cr_ex3_we), + .xu1_cr_ex3_wa(xu1_cr_ex3_wa), + .xu1_cr_ex3_w0d(xu1_cr_ex3_w0d), + .pc_xu_ram_active(pc_xu_ram_active), + `ifndef THREADS1 + .spr_dvc1_t1(spr_dvc1_t1), + .spr_dvc2_t1(spr_dvc2_t1), + `endif + .spr_dvc1_t0(spr_dvc1_t0), + .spr_dvc2_t0(spr_dvc2_t0), + .pc_xu_debug_mux_ctrls(pc_xu_debug_mux_ctrls), + .xu1_debug_bus_in(xu1_debug_bus_in), + .xu1_debug_bus_out(xu1_debug_bus_out), + .xu1_coretrace_ctrls_in(xu1_coretrace_ctrls_in), + .xu1_coretrace_ctrls_out(xu1_coretrace_ctrls_out) + ); + + + xu_rf #(.WIDTH(4), .PAR_WIDTH(1), .POOL_ENC(`CR_POOL_ENC + `THREADS_POOL_ENC), .POOL(`CR_POOL * `THREADS), .RD_PORTS(4), .WR_PORTS(5), .BYPASS(1)) cr( + .nclk(nclk), + .vdd(vdd), + .gnd(gnd), + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .func_sl_force(func_sl_force), + .func_sl_thold_0_b(func_sl_thold_0_b), + .func_nsl_force(func_sl_force), + .func_nsl_thold_0_b(func_sl_thold_0_b), + .sg_0(sg_0), + .scan_in(siv[2]), + .scan_out(sov[2]), + .r0e_e(rv_xu0_s1_v), + .r0e(rv_xu0_s1_v), + .r0a(rv_xu0_s1_p_int[`GPR_POOL_ENC-`CR_POOL_ENC:`GPR_POOL_ENC+`THREADS_POOL_ENC-1]), + .r0d(cr_xu0_ex1_r1d), + .r1e_e(rv_xu0_s2_v), + .r1e(rv_xu0_s2_v), + .r1a(rv_xu0_s2_p_int[`GPR_POOL_ENC-`CR_POOL_ENC:`GPR_POOL_ENC+`THREADS_POOL_ENC-1]), + .r1d(cr_xu0_ex1_r2d), + .r2e_e(rv_xu0_s3_v), + .r2e(rv_xu0_s3_v), + .r2a(rv_xu0_s3_p_int[`GPR_POOL_ENC-`CR_POOL_ENC:`GPR_POOL_ENC+`THREADS_POOL_ENC-1]), + .r2d(cr_xu0_ex1_r3d), + .r3e_e(rv_xu1_s3_v), + .r3e(rv_xu1_s3_v), + .r3a(rv_xu1_s3_p_int[`GPR_POOL_ENC-`CR_POOL_ENC:`GPR_POOL_ENC+`THREADS_POOL_ENC-1]), + .r3d(cr_xu1_ex1_r3d), + .w0e_e(xu0_cr_ex6_we), + .w0e(xu0_cr_ex6_we), + .w0a(xu0_cr_ex6_wa), + .w0d(xu0_cr_ex6_w0d), + .w1e_e(xu1_cr_ex3_we), + .w1e(xu1_cr_ex3_we), + .w1a(xu1_cr_ex3_wa), + .w1d(xu1_cr_ex3_w0d), + .w2e_e(lq_xu_cr_ex5_we), + .w2e(lq_xu_cr_ex5_we), + .w2a(lq_xu_cr_ex5_wa), + .w2d(lq_xu_cr_ex5_wd), + .w3e_e(lq_xu_cr_l2_we), + .w3e(lq_xu_cr_l2_we), + .w3a(lq_xu_cr_l2_wa), + .w3d(lq_xu_cr_l2_wd), + .w4e_e(axu_xu_cr_w0e), + .w4e(axu_xu_cr_w0e), + .w4a(axu_xu_cr_w0a), + .w4d(axu_xu_cr_w0d) + ); + + + xu_rf #(.WIDTH(10), .PAR_WIDTH(2), .POOL_ENC(`XER_POOL_ENC + `THREADS_POOL_ENC), .POOL(`XER_POOL * `THREADS), .RD_PORTS(3 + `THREADS), .WR_PORTS(2), .BYPASS(1)) xer( + .nclk(nclk), + .vdd(vdd), + .gnd(gnd), + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .func_sl_force(func_sl_force), + .func_sl_thold_0_b(func_sl_thold_0_b), + .func_nsl_force(func_sl_force), + .func_nsl_thold_0_b(func_sl_thold_0_b), + .sg_0(sg_0), + .scan_in(siv[3]), + .scan_out(sov[3]), + .r0e_e(rv_xu0_s2_v), + .r0e(rv_xu0_s2_v), + .r0a(rv_xu0_s2_p_int[`GPR_POOL_ENC-`XER_POOL_ENC:`GPR_POOL_ENC+`THREADS_POOL_ENC-1]), + .r0d(xer_xu0_ex1_r2d), + .r1e_e(rv_xu0_s3_v), + .r1e(rv_xu0_s3_v), + .r1a(rv_xu0_s3_p_int[`GPR_POOL_ENC-`XER_POOL_ENC:`GPR_POOL_ENC+`THREADS_POOL_ENC-1]), + .r1d(xer_xu0_ex1_r3d), + .r2e_e(rv_xu1_s3_v), + .r2e(rv_xu1_s3_v), + .r2a(rv_xu1_s3_p_int[`GPR_POOL_ENC-`XER_POOL_ENC:`GPR_POOL_ENC+`THREADS_POOL_ENC-1]), + .r2d(xer_xu1_ex1_r3d), + .r3e_e(tiup), + .r3e(tiup), + .r3a(iu_rf_xer_t0_p_int), + .r3d(xer_lq_cp_r0d), + .r4e_e(tiup), + .r4e(tiup), + .r4a(iu_rf_xer_t1_p_int), + .r4d(xer_lq_cp_r1d), + .w0e_e(xu0_xer_ex6_we), + .w0e(xu0_xer_ex6_we), + .w0a(xu0_xer_ex6_wa), + .w0d(xu0_xer_ex6_w0d), + .w1e_e(xu1_xer_ex3_we), + .w1e(xu1_xer_ex3_we), + .w1a(xu1_xer_ex3_wa), + .w1d(xu1_xer_ex3_w0d), + .w2e(1'b0), + .w3e(1'b0), + .w4e(1'b0) + ); + + + xu_rf #(.WIDTH(`GPR_WIDTH), .PAR_WIDTH(`GPR_WIDTH/8), .POOL_ENC(`BR_POOL_ENC + `THREADS_POOL_ENC), .POOL(`BR_POOL * `THREADS), .RD_PORTS(2), .WR_PORTS(1), .BYPASS(1)) lr( + .nclk(nclk), + .vdd(vdd), + .gnd(gnd), + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .func_sl_force(func_sl_force), + .func_sl_thold_0_b(func_sl_thold_0_b), + .func_nsl_force(func_sl_force), + .func_nsl_thold_0_b(func_sl_thold_0_b), + .sg_0(sg_0), + .scan_in(siv[4]), + .scan_out(sov[4]), + .r0e_e(rv_xu0_s1_v), + .r0e(rv_xu0_s1_v), + .r0a(rv_xu0_s1_p_int[`GPR_POOL_ENC-`BR_POOL_ENC:`GPR_POOL_ENC+`THREADS_POOL_ENC-1]), + .r0d(lr_xu0_ex1_r1d), + .r1e_e(rv_xu0_s2_v), + .r1e(rv_xu0_s2_v), + .r1a(rv_xu0_s2_p_int[`GPR_POOL_ENC-`BR_POOL_ENC:`GPR_POOL_ENC+`THREADS_POOL_ENC-1]), + .r1d(lr_xu0_ex1_r2d), + .w0e_e(xu0_lr_ex4_we), + .w0e(xu0_lr_ex4_we), + .w0a(xu0_lr_ex4_wa), + .w0d(xu0_lr_ex4_w0d), + .w1e(1'b0), + .w2e(1'b0), + .w3e(1'b0), + .w4e(1'b0) + ); + + + xu_rf #(.WIDTH(`GPR_WIDTH), .PAR_WIDTH(`GPR_WIDTH/8), .POOL_ENC(`CTR_POOL_ENC + `THREADS_POOL_ENC), .POOL(`CTR_POOL * `THREADS), .RD_PORTS(1), .WR_PORTS(1), .BYPASS(1)) ctr( + .nclk(nclk), + .vdd(vdd), + .gnd(gnd), + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .func_sl_force(func_sl_force), + .func_sl_thold_0_b(func_sl_thold_0_b), + .func_nsl_force(func_sl_force), + .func_nsl_thold_0_b(func_sl_thold_0_b), + .sg_0(sg_0), + .scan_in(siv[5]), + .scan_out(sov[5]), + .r0e_e(rv_xu0_s2_v), + .r0e(rv_xu0_s2_v), + .r0a(rv_xu0_s2_p_int[`GPR_POOL_ENC-`CTR_POOL_ENC:`GPR_POOL_ENC+`THREADS_POOL_ENC-1]), + .r0d(ctr_xu0_ex1_r2d), + .w0e_e(xu0_ctr_ex4_we), + .w0e(xu0_ctr_ex4_we), + .w0a(xu0_ctr_ex4_wa), + .w0d(xu0_ctr_ex4_w0d), + .w1e(1'b0), + .w2e(1'b0), + .w3e(1'b0), + .w4e(1'b0) + ); + + + xu_gpr gpr( + .nclk(nclk), + .vdd(vdd), + .gnd(gnd), + .pc_xu_ccflush_dc(pc_xu_ccflush_dc), + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .func_sl_force(func_sl_force), + .func_sl_thold_0_b(func_sl_thold_0_b), + .sg_0(sg_0), + .scan_in(siv[6]), + .scan_out(sov[6]), + .r0e(rv_xu0_s1_v), + .r0a(rv_xu0_s1_p_int), + .r0d(gpr_xu0_ex1_r1d), + .r1e(rv_xu0_s2_v), + .r1a(rv_xu0_s2_p_int), + .r1d(gpr_xu0_ex1_r2d), + .r2e(rv_xu1_s1_v), + .r2a(rv_xu1_s1_p_int), + .r2d(gpr_xu1_ex1_r1d), + .r3e(rv_xu1_s2_v), + .r3a(rv_xu1_s2_p_int), + .r3d(gpr_xu1_ex1_r2d), + .r4e(rv_xu0_s3_gpr_v), + .r4t_q(rv_xu0_ex0_s3_t), + .r4a(rv_xu0_s3_p_int), + .r0_pe(), + .r1_pe(), + .r2_pe(), + .r3_pe(), + .w0e(xu0_gpr_ex6_we_int), + .w0a(xu0_gpr_ex6_wa_int), + .w0d(xu0_gpr_ex6_wd_int), + .w1e(xu1_gpr_ex3_we_int), + .w1a(xu1_gpr_ex3_wa_int), + .w1d(xu1_gpr_ex3_wd_int), + .w2e(lq_xu_gpr_ex6_we_q), + .w2a(lq_xu_gpr_ex6_wa_q), + .w2d(lq_xu_gpr_ex6_wd_int), + .w3e(lq_xu_gpr_rel_we), + .w3a(lq_xu_gpr_rel_wa_int), + .w3d(lq_xu_gpr_rel_wd_int) + ); + + + xu_spr #(.hvmode(1), .a2mode(1)) spr( + .nclk(nclk), + + // CHIP IO + .an_ac_chipid_dc(an_ac_chipid_dc), + .an_ac_coreid(an_ac_coreid), + .spr_pvr_version_dc(spr_pvr_version_dc), + .spr_pvr_revision_dc(spr_pvr_revision_dc), + .spr_pvr_revision_minor_dc(spr_pvr_revision_minor_dc), + .an_ac_ext_interrupt(an_ac_ext_interrupt), + .an_ac_crit_interrupt(an_ac_crit_interrupt), + .an_ac_perf_interrupt(an_ac_perf_interrupt), + .an_ac_reservation_vld(an_ac_reservation_vld), + .an_ac_tb_update_pulse(an_ac_tb_update_pulse), + .an_ac_tb_update_enable(an_ac_tb_update_enable), + .an_ac_sleep_en(an_ac_sleep_en), + .an_ac_hang_pulse(an_ac_hang_pulse), + .ac_tc_machine_check(ac_tc_machine_check), + .an_ac_external_mchk(an_ac_external_mchk), + .pc_xu_instr_trace_mode(pc_xu_instr_trace_mode), + .pc_xu_instr_trace_tid(pc_xu_instr_trace_tid), + + .an_ac_scan_dis_dc_b(an_ac_scan_dis_dc_b), + .an_ac_scan_diag_dc(an_ac_scan_diag_dc), + .pc_xu_ccflush_dc(pc_xu_ccflush_dc), + .clkoff_dc_b(clkoff_dc_b), + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .func_sl_thold_2(func_sl_thold_0), + .func_slp_sl_thold_2(func_slp_sl_thold_0), + .func_nsl_thold_2(func_sl_thold_0), + .func_slp_nsl_thold_2(func_slp_sl_thold_0), + .cfg_sl_thold_2(func_sl_thold_0), + .cfg_slp_sl_thold_2(func_slp_sl_thold_0), + .ary_nsl_thold_2(func_sl_thold_0), + .time_sl_thold_2(func_sl_thold_0), + .abst_sl_thold_2(func_sl_thold_0), + .repr_sl_thold_2(func_sl_thold_0), + .gptr_sl_thold_2(func_sl_thold_0), + .bolt_sl_thold_2(func_sl_thold_0), + .sg_2(sg_0), + .fce_2(fce_0), + .func_scan_in(siv[7:8 + `THREADS]), + .func_scan_out(sov[7:8 + `THREADS]), + .bcfg_scan_in(siv[9 + `THREADS]), + .bcfg_scan_out(sov[9 + `THREADS]), + .ccfg_scan_in(siv[10 + `THREADS]), + .ccfg_scan_out(sov[10 + `THREADS]), + .dcfg_scan_in(siv[11 + `THREADS]), + .dcfg_scan_out(sov[11 + `THREADS]), + .time_scan_in(siv[12 + `THREADS]), + .time_scan_out(sov[12 + `THREADS]), + .abst_scan_in(siv[13 + `THREADS]), + .abst_scan_out(sov[13 + `THREADS]), + .repr_scan_in(siv[14 + `THREADS]), + .repr_scan_out(sov[14 + `THREADS]), + .gptr_scan_in(siv[15 + `THREADS]), + .gptr_scan_out(sov[15 + `THREADS]), + + // Decode + .rv_xu_vld(rv_xu0_vld), + .rv_xu_ex0_ord(rv_xu0_ex0_ord), + .rv_xu_ex0_instr(rv_xu0_ex0_instr), + .rv_xu_ex0_ifar(rv_xu0_ex0_ifar), + + .spr_xu_ord_read_done(spr_xu_ord_read_done), + .spr_xu_ord_write_done(spr_xu_ord_write_done), + .xu_spr_ord_ready(xu_spr_ord_ready), + .xu_spr_ord_flush(xu_spr_ord_flush), + .cp_flush(cp_flush), + + // Read Data + .spr_xu_ex4_rd_data(spr_xu_ex4_rd_data), + + // Write Data + .xu_spr_ex2_rs1(xu_spr_ex2_rs1), + + // Interrupt Interface + .iu_xu_rfi(iu_xu_rfi), + .iu_xu_rfgi(iu_xu_rfgi), + .iu_xu_rfci(iu_xu_rfci), + .iu_xu_rfmci(iu_xu_rfmci), + .iu_xu_act(iu_xu_act), + .iu_xu_int(iu_xu_int), + .iu_xu_gint(iu_xu_gint), + .iu_xu_cint(iu_xu_cint), + .iu_xu_mcint(iu_xu_mcint), + .iu_xu_dear_update(iu_xu_dear_update), + .iu_xu_dbsr_update(iu_xu_dbsr_update), + .iu_xu_esr_update(iu_xu_esr_update), + .iu_xu_force_gsrr(iu_xu_force_gsrr), + .iu_xu_dbsr_ude(iu_xu_dbsr_ude), + .iu_xu_dbsr_ide(iu_xu_dbsr_ide), + .xu_iu_dbsr_ide(xu_iu_dbsr_ide), + + .iu_xu_nia_t0(iu_xu_nia_t0), + .iu_xu_esr_t0(iu_xu_esr_t0), + .iu_xu_mcsr_t0(iu_xu_mcsr_t0), + .iu_xu_dbsr_t0(iu_xu_dbsr_t0), + .iu_xu_dear_t0(iu_xu_dear_t0), + .xu_iu_rest_ifar_t0(xu_iu_rest_ifar_t0), + `ifndef THREADS1 + .iu_xu_nia_t1(iu_xu_nia_t1), + .iu_xu_esr_t1(iu_xu_esr_t1), + .iu_xu_mcsr_t1(iu_xu_mcsr_t1), + .iu_xu_dbsr_t1(iu_xu_dbsr_t1), + .iu_xu_dear_t1(iu_xu_dear_t1), + .xu_iu_rest_ifar_t1(xu_iu_rest_ifar_t1), + `endif + + // Async Interrupt Req Interface + .xu_iu_external_mchk(xu_iu_external_mchk), + .xu_iu_ext_interrupt(xu_iu_ext_interrupt), + .xu_iu_dec_interrupt(xu_iu_dec_interrupt), + .xu_iu_udec_interrupt(xu_iu_udec_interrupt), + .xu_iu_perf_interrupt(xu_iu_perf_interrupt), + .xu_iu_fit_interrupt(xu_iu_fit_interrupt), + .xu_iu_crit_interrupt(xu_iu_crit_interrupt), + .xu_iu_wdog_interrupt(xu_iu_wdog_interrupt), + .xu_iu_gwdog_interrupt(xu_iu_gwdog_interrupt), + .xu_iu_gfit_interrupt(xu_iu_gfit_interrupt), + .xu_iu_gdec_interrupt(xu_iu_gdec_interrupt), + .xu_iu_dbell_interrupt(xu_iu_dbell_interrupt), + .xu_iu_cdbell_interrupt(xu_iu_cdbell_interrupt), + .xu_iu_gdbell_interrupt(xu_iu_gdbell_interrupt), + .xu_iu_gcdbell_interrupt(xu_iu_gcdbell_interrupt), + .xu_iu_gmcdbell_interrupt(xu_iu_gmcdbell_interrupt), + .iu_xu_dbell_taken(iu_xu_dbell_taken), + .iu_xu_cdbell_taken(iu_xu_cdbell_taken), + .iu_xu_gdbell_taken(iu_xu_gdbell_taken), + .iu_xu_gcdbell_taken(iu_xu_gcdbell_taken), + .iu_xu_gmcdbell_taken(iu_xu_gmcdbell_taken), + + // DBELL Int + .lq_xu_dbell_val(lq_xu_dbell_val), + .lq_xu_dbell_type(lq_xu_dbell_type), + .lq_xu_dbell_brdcast(lq_xu_dbell_brdcast), + .lq_xu_dbell_lpid_match(lq_xu_dbell_lpid_match), + .lq_xu_dbell_pirtag(lq_xu_dbell_pirtag), + + // Slow SPR Bus + .xu_slowspr_val_out(xu_slowspr_val_out), + .xu_slowspr_rw_out(xu_slowspr_rw_out), + .xu_slowspr_etid_out(xu_slowspr_etid_out), + .xu_slowspr_addr_out(xu_slowspr_addr_out), + .xu_slowspr_data_out(xu_slowspr_data_out), + .ac_an_dcr_act(), + .ac_an_dcr_val(), + .ac_an_dcr_read(), + .ac_an_dcr_user(), + .ac_an_dcr_etid(), + .ac_an_dcr_addr(), + .ac_an_dcr_data(), + + // DCR Bus + + // Trap + .xu_iu_fp_precise(xu_iu_fp_precise), + .spr_dec_ex4_spr_hypv(spr_dec_ex4_spr_hypv), + .spr_dec_ex4_spr_illeg(spr_dec_ex4_spr_illeg), + .spr_dec_ex4_spr_priv(spr_dec_ex4_spr_priv), + .spr_dec_ex4_np1_flush(spr_dec_ex4_np1_flush), + + // Run State + .pc_xu_pm_hold_thread(pc_xu_pm_hold_thread), + .iu_xu_stop(iu_xu_stop), + .xu_pc_running(xu_pc_running), + .xu_iu_run_thread(xu_iu_run_thread), + .xu_iu_single_instr_mode(xu_iu_single_instr_mode), + .xu_iu_raise_iss_pri(xu_iu_raise_iss_pri), + .xu_pc_spr_ccr0_we(xu_pc_spr_ccr0_we), + .xu_pc_stop_dnh_instr(xu_pc_stop_dnh_instr), + + // Quiesce + .iu_xu_icache_quiesce(iu_xu_icache_quiesce), + .iu_xu_quiesce(iu_xu_quiesce), + .lq_xu_quiesce(lq_xu_quiesce), + .mm_xu_quiesce(mm_xu_quiesce), + .bx_xu_quiesce(bx_xu_quiesce), + + // PCCR0 + .pc_xu_extirpts_dis_on_stop(pc_xu_extirpts_dis_on_stop), + .pc_xu_timebase_dis_on_stop(pc_xu_timebase_dis_on_stop), + .pc_xu_decrem_dis_on_stop(pc_xu_decrem_dis_on_stop), + + // MSR Override + .pc_xu_ram_active(pc_xu_ram_active), + .xu_iu_msrovride_enab(xu_iu_msrovride_enab), + .pc_xu_msrovride_enab(pc_xu_msrovride_enab), + .pc_xu_msrovride_pr(pc_xu_msrovride_pr), + .pc_xu_msrovride_gs(pc_xu_msrovride_gs), + .pc_xu_msrovride_de(pc_xu_msrovride_de), + // SIAR + .pc_xu_spr_cesr1_pmae(pc_xu_spr_cesr1_pmae), + .xu_pc_perfmon_alert(xu_pc_perfmon_alert), + + // LiveLock + .iu_xu_instr_cpl(iu_xu_instr_cpl), + .xu_pc_err_llbust_attempt(xu_pc_err_llbust_attempt), + .xu_pc_err_llbust_failed(xu_pc_err_llbust_failed), + + // Resets + .pc_xu_reset_wd_complete(pc_xu_reset_wd_complete), + .pc_xu_reset_1_complete(pc_xu_reset_1_complete), + .pc_xu_reset_2_complete(pc_xu_reset_2_complete), + .pc_xu_reset_3_complete(pc_xu_reset_3_complete), + .ac_tc_reset_1_request(ac_tc_reset_1_request), + .ac_tc_reset_2_request(ac_tc_reset_2_request), + .ac_tc_reset_3_request(ac_tc_reset_3_request), + .ac_tc_reset_wd_request(ac_tc_reset_wd_request), + + // Err Inject + .pc_xu_inj_llbust_attempt(pc_xu_inj_llbust_attempt), + .pc_xu_inj_llbust_failed(pc_xu_inj_llbust_failed), + .pc_xu_inj_wdt_reset(pc_xu_inj_wdt_reset), + .xu_pc_err_wdt_reset(xu_pc_err_wdt_reset), + + // Parity + .pc_xu_inj_sprg_ecc(pc_xu_inj_sprg_ecc), + .xu_pc_err_sprg_ecc(xu_pc_err_sprg_ecc), + .xu_pc_err_sprg_ue(xu_pc_err_sprg_ue), + // Perf + .pc_xu_event_count_mode(pc_xu_event_count_mode), + .pc_xu_event_bus_enable(pc_xu_event_bus_enable), + .xu_event_bus_in(xu_event_bus_in), + .xu_event_bus_out(xu_event_bus_out), + .div_spr_running(div_spr_running), + .mul_spr_running(mul_spr_running), + + // SPRs + .spr_xesr1(spr_xesr1), + .spr_xesr2(spr_xesr2), + .perf_event_en(perf_event_en), + .spr_dbcr0_edm(spr_dbcr0_edm), + .spr_xucr0_clkg_ctl(spr_xucr0_clkg_ctl), + .xu_iu_iac1_en(xu_iu_iac1_en), + .xu_iu_iac2_en(xu_iu_iac2_en), + .xu_iu_iac3_en(xu_iu_iac3_en), + .xu_iu_iac4_en(xu_iu_iac4_en), + .lq_xu_spr_xucr0_cslc_xuop(lq_xu_spr_xucr0_cslc_xuop), + .lq_xu_spr_xucr0_cslc_binv(lq_xu_spr_xucr0_cslc_binv), + .lq_xu_spr_xucr0_clo(lq_xu_spr_xucr0_clo), + .lq_xu_spr_xucr0_cul(lq_xu_spr_xucr0_cul), + .spr_epcr_extgs(spr_epcr_extgs), + .spr_epcr_icm(spr_epcr_icm), + .spr_epcr_gicm(spr_epcr_gicm), + .spr_msr_de(spr_msr_de), + .spr_msr_pr(spr_msr_pr_int), + .spr_msr_is(spr_msr_is), + .spr_msr_cm(spr_msr_cm_int), + .spr_msr_gs(spr_msr_gs_int), + .spr_msr_ee(spr_msr_ee), + .spr_msr_ce(spr_msr_ce), + .spr_msr_me(spr_msr_me), + .spr_msr_fe0(spr_msr_fe0), + .spr_msr_fe1(spr_msr_fe1), + .spr_ccr2_en_pc(spr_ccr2_en_pc_int), + .xu_lsu_spr_xucr0_clfc(xu_lsu_spr_xucr0_clfc), + .xu_pc_spr_ccr0_pme(xu_pc_spr_ccr0_pme), + .spr_ccr2_en_dcr(spr_ccr2_en_dcr), + .spr_ccr2_en_trace(spr_ccr2_en_trace), + .spr_ccr2_ifratsc(spr_ccr2_ifratsc), + .spr_ccr2_ifrat(spr_ccr2_ifrat), + .spr_ccr2_dfratsc(spr_ccr2_dfratsc), + .spr_ccr2_dfrat(spr_ccr2_dfrat), + .spr_ccr2_ucode_dis(spr_ccr2_ucode_dis), + .spr_ccr2_ap(spr_ccr2_ap), + .spr_ccr2_en_attn(spr_ccr2_en_attn), + .spr_ccr4_en_dnh(spr_ccr4_en_dnh), + .spr_ccr2_en_ditc(spr_ccr2_en_ditc), + .spr_ccr2_en_icswx(spr_ccr2_en_icswx), + .spr_ccr2_notlb(spr_ccr2_notlb_int), + .spr_xucr0_trace_um(spr_xucr0_trace_um), + .xu_lsu_spr_xucr0_mbar_ack(xu_lsu_spr_xucr0_mbar_ack), + .xu_lsu_spr_xucr0_tlbsync(xu_lsu_spr_xucr0_tlbsync), + .spr_xucr0_cls(spr_xucr0_cls), + .xu_lsu_spr_xucr0_aflsta(xu_lsu_spr_xucr0_aflsta), + .spr_xucr0_mddp(spr_xucr0_mddp), + .xu_lsu_spr_xucr0_cred(xu_lsu_spr_xucr0_cred), + .xu_lsu_spr_xucr0_rel(xu_lsu_spr_xucr0_rel), + .spr_xucr0_mdcp(spr_xucr0_mdcp), + .xu_lsu_spr_xucr0_flsta(xu_lsu_spr_xucr0_flsta), + .xu_lsu_spr_xucr0_l2siw(xu_lsu_spr_xucr0_l2siw), + .xu_lsu_spr_xucr0_flh2l2(xu_lsu_spr_xucr0_flh2l2), + .xu_lsu_spr_xucr0_dcdis(xu_lsu_spr_xucr0_dcdis), + .xu_lsu_spr_xucr0_wlk(xu_lsu_spr_xucr0_wlk), + .spr_dbcr0_idm(spr_dbcr0_idm), + .spr_dbcr0_icmp(spr_dbcr0_icmp), + .spr_dbcr0_brt(spr_dbcr0_brt), + .spr_dbcr0_irpt(spr_dbcr0_irpt), + .spr_dbcr0_trap(spr_dbcr0_trap), + .spr_dbcr0_dac1(spr_dbcr0_dac1), + .spr_dbcr0_dac2(spr_dbcr0_dac2), + .spr_dbcr0_ret(spr_dbcr0_ret), + .spr_dbcr0_dac3(spr_dbcr0_dac3), + .spr_dbcr0_dac4(spr_dbcr0_dac4), + .spr_dbcr1_iac12m(spr_dbcr1_iac12m), + .spr_dbcr1_iac34m(spr_dbcr1_iac34m), + .spr_epcr_dtlbgs(spr_epcr_dtlbgs), + .spr_epcr_itlbgs(spr_epcr_itlbgs), + .spr_epcr_dsigs(spr_epcr_dsigs), + .spr_epcr_isigs(spr_epcr_isigs), + .spr_epcr_duvd(spr_epcr_duvd), + .spr_epcr_dgtmi(spr_epcr_dgtmi_int), + .xu_mm_spr_epcr_dmiuh(xu_mm_spr_epcr_dmiuh), + .spr_msr_ucle(spr_msr_ucle), + .spr_msr_spv(spr_msr_spv), + .spr_msr_fp(spr_msr_fp), + .spr_msr_ds(spr_msr_ds), + .spr_msrp_uclep(spr_msrp_uclep), + .spr_xucr4_mmu_mchk(spr_xucr4_mmu_mchk), + .spr_xucr4_mddmh(spr_xucr4_mddmh), + `ifndef THREADS1 + .spr_dvc1_t1(spr_dvc1_t1), + .spr_dvc2_t1(spr_dvc2_t1), + `endif + .spr_dvc1_t0(spr_dvc1_t0), + .spr_dvc2_t0(spr_dvc2_t0), + + // BOLT-ON + .bo_enable_2(bo_enable_2), // general bolt-on enable + .pc_xu_bo_reset(pc_xu_bo_reset), // reset + .pc_xu_bo_unload(pc_xu_bo_unload), // unload sticky bits + .pc_xu_bo_repair(pc_xu_bo_repair), // execute sticky bit decode + .pc_xu_bo_shdata(pc_xu_bo_shdata), // shift data for timing write and diag loop + .pc_xu_bo_select(pc_xu_bo_select), // select for mask and hier writes + .xu_pc_bo_fail(xu_pc_bo_fail), // fail/no-fix reg + .xu_pc_bo_diagout(xu_pc_bo_diagout), + // ABIST + .an_ac_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc), + .pc_xu_abist_ena_dc(pc_xu_abist_ena_dc), + .pc_xu_abist_g8t_wenb(pc_xu_abist_g8t_wenb), + .pc_xu_abist_waddr_0(pc_xu_abist_waddr_0), + .pc_xu_abist_di_0(pc_xu_abist_di_0), + .pc_xu_abist_g8t1p_renb_0(pc_xu_abist_g8t1p_renb_0), + .pc_xu_abist_raddr_0(pc_xu_abist_raddr_0), + .pc_xu_abist_wl32_comp_ena(pc_xu_abist_wl32_comp_ena), + .pc_xu_abist_raw_dc_b(pc_xu_abist_raw_dc_b), + .pc_xu_abist_g8t_dcomp(pc_xu_abist_g8t_dcomp), + .pc_xu_abist_g8t_bw_1(pc_xu_abist_g8t_bw_1), + .pc_xu_abist_g8t_bw_0(pc_xu_abist_g8t_bw_0), + + // Debug + .pc_xu_trace_bus_enable(pc_xu_trace_bus_enable), + .spr_debug_mux_ctrls(spr_debug_mux_ctrls), + .spr_debug_data_in(spr_debug_data_in), + .spr_debug_data_out(spr_debug_data_out), + + // Power + .vcs(vdd), + .vdd(vdd), + .gnd(gnd) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_pc_ram_done_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[xu_pc_ram_done_offset]), + .scout(sov[xu_pc_ram_done_offset]), + .din(xu_pc_ram_done_d), + .dout(xu_pc_ram_done_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) xu_pc_ram_data_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(xu_pc_ram_done_d), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[xu_pc_ram_data_offset : xu_pc_ram_data_offset + `GPR_WIDTH-1]), + .scout(sov[xu_pc_ram_data_offset : xu_pc_ram_data_offset + `GPR_WIDTH-1]), + .din(xu_pc_ram_data_d), + .dout(xu_pc_ram_data_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq_xu_gpr_ex6_we_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lq_xu_gpr_ex6_we_offset]), + .scout(sov[lq_xu_gpr_ex6_we_offset]), + .din(lq_xu_gpr_ex6_we_d), + .dout(lq_xu_gpr_ex6_we_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) lq_xu_gpr_ex6_wa_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(lq_xu_ex5_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[lq_xu_gpr_ex6_wa_offset : lq_xu_gpr_ex6_wa_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC-1]), + .scout(sov[lq_xu_gpr_ex6_wa_offset : lq_xu_gpr_ex6_wa_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC-1]), + .din(lq_xu_gpr_ex6_wa_d), + .dout(lq_xu_gpr_ex6_wa_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) lq_xu_gpr_ex6_wd_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(lq_xu_ex5_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[lq_xu_gpr_ex6_wd_offset : lq_xu_gpr_ex6_wd_offset + `GPR_WIDTH-1]), + .scout(sov[lq_xu_gpr_ex6_wd_offset : lq_xu_gpr_ex6_wd_offset + `GPR_WIDTH-1]), + .din(lq_xu_gpr_ex6_wd_d), + .dout(lq_xu_gpr_ex6_wd_q) + ); + + assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in}; + assign scan_out = sov[0]; + + +endmodule diff --git a/dev/verilog/work/xu0.v b/dev/verilog/work/xu0.v new file mode 100755 index 0000000..5f5013a --- /dev/null +++ b/dev/verilog/work/xu0.v @@ -0,0 +1,1172 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: Simple Execution Unit +// +//***************************************************************************** +`include "tri_a2o.vh" + +module xu0 +( + //------------------------------------------------------------------- + // Clocks & Power + //------------------------------------------------------------------- + input [0:`NCLK_WIDTH-1] nclk, + inout vdd, + inout gnd, + + //------------------------------------------------------------------- + // Pervasive + //------------------------------------------------------------------- + input pc_xu_ccflush_dc, + input d_mode_dc, + input delay_lclkr_dc, + input mpw1_dc_b, + input mpw2_dc_b, + input func_sl_force, + input func_sl_thold_0_b, + input sg_0, + input scan_in, + output scan_out, + + output xu0_pc_ram_done, + + //------------------------------------------------------------------- + // Interface with CP + //------------------------------------------------------------------- + input [0:`THREADS-1] cp_flush, + input [62-`EFF_IFAR_ARCH : 61-`EFF_IFAR_WIDTH] iu_br_t0_flush_ifar, + input [0:`ITAG_SIZE_ENC-1] cp_next_itag_t0, + `ifndef THREADS1 + input [62-`EFF_IFAR_ARCH : 61-`EFF_IFAR_WIDTH] iu_br_t1_flush_ifar, + input [0:`ITAG_SIZE_ENC-1] cp_next_itag_t1, + `endif + + //------------------------------------------------------------------- + // BR's Interface with CP + //------------------------------------------------------------------- + output [0:`THREADS-1] br_iu_execute_vld, + output [0:`ITAG_SIZE_ENC-1] br_iu_itag, + output br_iu_taken, + output [62-`EFF_IFAR_ARCH:61] br_iu_bta, + output [0:17] br_iu_gshare, + output [0:2] br_iu_ls_ptr, + output [62-`EFF_IFAR_WIDTH:61] br_iu_ls_data, + output br_iu_ls_update, + output [0:`THREADS-1] br_iu_redirect, + output [0:3] br_iu_perf_events, + + //------------------------------------------------------------------- + // Interface with RV + //------------------------------------------------------------------- + input [0:`THREADS-1] rv_xu0_vld, + input rv_xu0_ex0_ord, + input [0:19] rv_xu0_ex0_fusion, + input [0:31] rv_xu0_ex0_instr, + input [62-`EFF_IFAR_WIDTH:61] rv_xu0_ex0_ifar, + input [0:`ITAG_SIZE_ENC-1] rv_xu0_ex0_itag, + input [0:2] rv_xu0_ex0_ucode, + input rv_xu0_ex0_bta_val, + input [62-`EFF_IFAR_WIDTH:61] rv_xu0_ex0_pred_bta, + input rv_xu0_ex0_pred, + input [0:2] rv_xu0_ex0_ls_ptr, + input rv_xu0_ex0_bh_update, + input [0:17] rv_xu0_ex0_gshare, + input rv_xu0_ex0_s1_v, + input rv_xu0_ex0_s2_v, + input [0:2] rv_xu0_ex0_s2_t, + input rv_xu0_ex0_s3_v, + input [0:2] rv_xu0_ex0_s3_t, + input rv_xu0_ex0_t1_v, + input [0:`GPR_POOL_ENC-1] rv_xu0_ex0_t1_p, + input [0:2] rv_xu0_ex0_t1_t, + input rv_xu0_ex0_t2_v, + input [0:`GPR_POOL_ENC-1] rv_xu0_ex0_t2_p, + input [0:2] rv_xu0_ex0_t2_t, + input rv_xu0_ex0_t3_v, + input [0:`GPR_POOL_ENC-1] rv_xu0_ex0_t3_p, + input [0:2] rv_xu0_ex0_t3_t, + input [0:`THREADS-1] rv_xu0_ex0_spec_flush, + input [0:`THREADS-1] rv_xu0_ex1_spec_flush, + input [0:`THREADS-1] rv_xu0_ex2_spec_flush, + input [1:11] rv_xu0_s1_fxu0_sel, + input [1:11] rv_xu0_s2_fxu0_sel, + input [2:11] rv_xu0_s3_fxu0_sel, + input [1:6] rv_xu0_s1_fxu1_sel, + input [1:6] rv_xu0_s2_fxu1_sel, + input [2:6] rv_xu0_s3_fxu1_sel, + input [4:8] rv_xu0_s1_lq_sel, + input [4:8] rv_xu0_s2_lq_sel, + input [4:8] rv_xu0_s3_lq_sel, + input [2:3] rv_xu0_s1_rel_sel, + input [2:3] rv_xu0_s2_rel_sel, + + output xu0_rv_ord_complete, + output [0:`ITAG_SIZE_ENC-1] xu0_rv_ord_itag, + output xu0_rv_hold_all, + //------------------------------------------------------------------- + // Bypass Inputs + //------------------------------------------------------------------- + // Regfile Data + input [64-`GPR_WIDTH:63] gpr_xu0_ex1_r1d, + input [64-`GPR_WIDTH:63] gpr_xu0_ex1_r2d, + input [0:9] xer_xu0_ex1_r2d, + input [0:9] xer_xu0_ex1_r3d, + input [0:3] cr_xu0_ex1_r1d, + input [0:3] cr_xu0_ex1_r2d, + input [0:3] cr_xu0_ex1_r3d, + input [64-`GPR_WIDTH:63] lr_xu0_ex1_r1d, + input [64-`GPR_WIDTH:63] lr_xu0_ex1_r2d, + input [64-`GPR_WIDTH:63] ctr_xu0_ex1_r2d, + + // External Bypass + output xu0_xu1_ex3_act, + input xu1_xu0_ex3_act, + input lq_xu_ex5_act, + + input xu1_xu0_ex2_abort, + input [64-`GPR_WIDTH:63] xu1_xu0_ex2_rt, + input [64-`GPR_WIDTH:63] xu1_xu0_ex3_rt, + input [64-`GPR_WIDTH:63] xu1_xu0_ex4_rt, + input [64-`GPR_WIDTH:63] xu1_xu0_ex5_rt, + input lq_xu_ex5_abort, + input [64-`GPR_WIDTH:63] lq_xu_ex5_rt, + input lq_xu_rel_act, + input [64-`GPR_WIDTH:63] lq_xu_rel_rt, + input [64-`GPR_WIDTH:63] lq_xu_ex5_data, + input [64-`GPR_WIDTH:63] iu_xu_ex5_data, + + input [64-`GPR_WIDTH:63] spr_xu_ex4_rd_data, + output [64-`GPR_WIDTH:63] xu_spr_ex2_rs1, + + // CR + input [0:3] lq_xu_ex5_cr, + input [0:3] xu1_xu0_ex3_cr, + // XER + input [0:9] xu1_xu0_ex3_xer, + + //------------------------------------------------------------------- + // Interface with MMU / ERATs + //------------------------------------------------------------------- + output xu_iu_ord_ready, + output xu_iu_act, + output [0:`THREADS-1] xu_iu_val, + output xu_iu_is_eratre, + output xu_iu_is_eratwe, + output xu_iu_is_eratsx, + output xu_iu_is_eratilx, + output xu_iu_is_erativax, + output [0:1] xu_iu_ws, + output [0:2] xu_iu_t, + output [0:8] xu_iu_rs_is, + output [0:3] xu_iu_ra_entry, + output [64-`GPR_WIDTH:51] xu_iu_rb, + output [64-`GPR_WIDTH:63] xu_iu_rs_data, + input iu_xu_ord_read_done, + input iu_xu_ord_write_done, + input iu_xu_ord_n_flush_req, + input iu_xu_ord_par_err, + + output xu_lq_ord_ready, + output xu_lq_act, + output [0:`THREADS-1] xu_lq_val, + output xu_lq_hold_req, + output xu_lq_is_eratre, + output xu_lq_is_eratwe, + output xu_lq_is_eratsx, + output xu_lq_is_eratilx, + output [0:1] xu_lq_ws, + output [0:2] xu_lq_t, + output [0:8] xu_lq_rs_is, + output [0:4] xu_lq_ra_entry, + output [64-`GPR_WIDTH:51] xu_lq_rb, + output [64-`GPR_WIDTH:63] xu_lq_rs_data, + input lq_xu_ord_read_done, + input lq_xu_ord_write_done, + input lq_xu_ord_n_flush_req, + input lq_xu_ord_par_err, + + output xu_mm_ord_ready, + output xu_mm_act, + output [0:`THREADS-1] xu_mm_val, + output [0:`ITAG_SIZE_ENC-1] xu_mm_itag, + output xu_mm_is_tlbre, + output xu_mm_is_tlbwe, + output xu_mm_is_tlbsx, + output xu_mm_is_tlbsxr, + output xu_mm_is_tlbsrx, + output xu_mm_is_tlbivax, + output xu_mm_is_tlbilx, + output [0:11] xu_mm_ra_entry, + output [64-`GPR_WIDTH:63] xu_mm_rb, + input [0:`ITAG_SIZE_ENC-1] mm_xu_itag, + input mm_xu_ord_n_flush_req, + input mm_xu_ord_read_done, + input mm_xu_ord_write_done, + input mm_xu_tlb_miss, + input mm_xu_lrat_miss, + input mm_xu_tlb_inelig, + input mm_xu_pt_fault, + input mm_xu_hv_priv, + input mm_xu_illeg_instr, + input mm_xu_tlb_multihit, + input mm_xu_tlb_par_err, + input mm_xu_lru_par_err, + input mm_xu_local_snoop_reject, + input [0:1] mm_xu_mmucr0_tlbsel_t0, + `ifndef THREADS1 + input [0:1] mm_xu_mmucr0_tlbsel_t1, + `endif + input mm_xu_tlbwe_binv, + input mm_xu_cr0_eq, // for record forms + input mm_xu_cr0_eq_valid, // for record forms + + output xu_spr_ord_ready, + output xu_spr_ord_flush, + //------------------------------------------------------------------- + // Bypass Outputs + //------------------------------------------------------------------- + output xu0_xu1_ex2_abort, + output xu0_xu1_ex6_abort, + output xu0_lq_ex3_abort, + output [64-`GPR_WIDTH:63] xu0_xu1_ex2_rt, + output [64-`GPR_WIDTH:63] xu0_xu1_ex3_rt, + output [64-`GPR_WIDTH:63] xu0_xu1_ex4_rt, + output [64-`GPR_WIDTH:63] xu0_xu1_ex5_rt, + output [64-`GPR_WIDTH:63] xu0_xu1_ex6_rt, + output [64-`GPR_WIDTH:63] xu0_xu1_ex7_rt, + output [64-`GPR_WIDTH:63] xu0_xu1_ex8_rt, + output [64-`GPR_WIDTH:63] xu0_xu1_ex6_lq_rt, + output [64-`GPR_WIDTH:63] xu0_xu1_ex7_lq_rt, + output [64-`GPR_WIDTH:63] xu0_xu1_ex8_lq_rt, + output [64-`GPR_WIDTH:63] xu0_lq_ex3_rt, + output [64-`GPR_WIDTH:63] xu0_lq_ex4_rt, + output xu0_lq_ex6_act, + output [64-`GPR_WIDTH:63] xu0_lq_ex6_rt, + output [64-`GPR_WIDTH:63] xu0_pc_ram_data, + + // CR + output [0:3] xu0_xu1_ex3_cr, + output [0:3] xu0_xu1_ex4_cr, + output [0:3] xu0_xu1_ex6_cr, + + // XER + output [0:9] xu0_xu1_ex3_xer, + output [0:9] xu0_xu1_ex4_xer, + output [0:9] xu0_xu1_ex6_xer, + + // Abort + output xu0_rv_ex2_s1_abort, + output xu0_rv_ex2_s2_abort, + output xu0_rv_ex2_s3_abort, + + //------------------------------------------------------------------- + // Target Outputs + //------------------------------------------------------------------- + output xu0_gpr_ex6_we, + output [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] xu0_gpr_ex6_wa, + output [64-`GPR_WIDTH:65+`GPR_WIDTH/8] xu0_gpr_ex6_wd, + + output xu0_xer_ex6_we, + output [0:`XER_POOL_ENC+`THREADS_POOL_ENC-1] xu0_xer_ex6_wa, + output [0:9] xu0_xer_ex6_w0d, + + output xu0_cr_ex6_we, + output [0:`CR_POOL_ENC+`THREADS_POOL_ENC-1] xu0_cr_ex6_wa, + output [0:3] xu0_cr_ex6_w0d, + + output xu0_ctr_ex4_we, + output [0:`CTR_POOL_ENC+`THREADS_POOL_ENC-1] xu0_ctr_ex4_wa, + output [64-`GPR_WIDTH:63] xu0_ctr_ex4_w0d, + + output xu0_lr_ex4_we, + output [0:`BR_POOL_ENC+`THREADS_POOL_ENC-1] xu0_lr_ex4_wa, + output [64-`GPR_WIDTH:63] xu0_lr_ex4_w0d, + + //------------------------------------------------------------------- + // Interface with IU + //------------------------------------------------------------------- + output [0:`THREADS-1] xu0_iu_execute_vld, + output [0:`ITAG_SIZE_ENC-1] xu0_iu_itag, + output [0:`THREADS-1] xu0_iu_mtiar, + output xu0_iu_exception_val, + output [0:4] xu0_iu_exception, + output xu0_iu_n_flush, + output xu0_iu_np1_flush, + output xu0_iu_flush2ucode, + output [0:3] xu0_iu_perf_events, + output [62-`EFF_IFAR_ARCH:61] xu0_iu_bta, + output [0:`THREADS-1] xu_iu_np1_async_flush, + input [0:`THREADS-1] iu_xu_async_complete, + input iu_xu_credits_returned, + output [0:`THREADS-1] xu_iu_pri_val, + output [0:2] xu_iu_pri, + + //------------------------------------------------------------------- + // Interface with SPR + //------------------------------------------------------------------- + input spr_xu_ord_read_done, + input spr_xu_ord_write_done, + input spr_dec_ex4_spr_hypv, + input spr_dec_ex4_spr_illeg, + input spr_dec_ex4_spr_priv, + input spr_dec_ex4_np1_flush, + output [0:`THREADS-1] div_spr_running, + output [0:`THREADS-1] mul_spr_running, + + //------------------------------------------------------------------- + // SlowSPRs + //------------------------------------------------------------------- + input xu_slowspr_val_in, + input xu_slowspr_rw_in, + input [64-`GPR_WIDTH:63] xu_slowspr_data_in, + input xu_slowspr_done_in, + + //------------------------------------------------------------------- + // SPRs + //------------------------------------------------------------------- + input [0:`THREADS-1] spr_msr_cm, + input [0:`THREADS-1] spr_msr_gs, + input [0:`THREADS-1] spr_msr_pr, + input [0:`THREADS-1] spr_epcr_dgtmi, + input spr_ccr2_notlb, + input spr_ccr2_en_attn, + input spr_ccr4_en_dnh, + input spr_ccr2_en_pc, + input [0:31] spr_xesr1, + input [0:31] spr_xesr2, + input [0:`THREADS-1] perf_event_en, + + // Debug + input [0:10] pc_xu_debug_mux_ctrls, + input [0:31] xu0_debug_bus_in, + output [0:31] xu0_debug_bus_out, + input [0:3] xu0_coretrace_ctrls_in, + output [0:3] xu0_coretrace_ctrls_out, + + input [0:`THREADS-1] pc_xu_ram_active +); + + //!! bugspray include: xu0_byp; + + localparam scan_right = 8; + wire [0:scan_right-1] siv; + wire [0:scan_right-1] sov; + // Signals + wire dec_byp_ex0_act; + wire [64-`GPR_WIDTH:63] dec_byp_ex1_imm; + wire [24:25] dec_byp_ex1_instr; + wire dec_byp_ex0_rs2_sel_imm; + wire dec_byp_ex0_rs1_sel_zero; + wire dec_byp_ex1_is_mflr; + wire dec_byp_ex1_is_mfxer; + wire dec_byp_ex1_is_mtxer; + wire dec_byp_ex1_is_mfcr_sel; + wire [0:7] dec_byp_ex1_is_mfcr; + wire [0:7] dec_byp_ex1_is_mtcr; + wire dec_byp_ex1_is_mfctr; + wire dec_byp_ex3_is_mtspr; + wire [2:3] dec_byp_ex1_cr_sel; + wire [2:3] dec_byp_ex1_xer_sel; + wire alu_dec_ex3_trap_val; + wire dec_byp_ex5_ord_sel; + wire dec_byp_ex3_mtiar; + wire dec_pop_ex1_act; + wire dec_alu_ex1_act; + wire [0:31] dec_alu_ex1_instr; + wire dec_alu_ex1_sel_isel; + wire [0:`GPR_WIDTH/8-1] dec_alu_ex1_add_rs1_inv; + wire [0:1] dec_alu_ex2_add_ci_sel; + wire dec_alu_ex1_sel_trap; + wire dec_alu_ex1_sel_cmpl; + wire dec_alu_ex1_sel_cmp; + wire dec_alu_ex1_msb_64b_sel; + wire dec_alu_ex1_xer_ov_en; + wire dec_alu_ex1_xer_ca_en; + wire [64-`GPR_WIDTH:63] alu_byp_ex2_add_rt; + wire [64-`GPR_WIDTH:63] alu_byp_ex3_rt; + wire [0:3] alu_byp_ex3_cr; + wire [0:9] alu_byp_ex3_xer; + wire [64-`GPR_WIDTH:63] byp_alu_ex2_rs1; + wire [64-`GPR_WIDTH:63] byp_alu_ex2_rs2; + wire byp_alu_ex2_cr_bit; + wire [0:9] byp_alu_ex2_xer; + wire [64-`GPR_WIDTH:63] byp_pop_ex2_rs1; + wire [64-`GPR_WIDTH:63] byp_cnt_ex2_rs1; + wire [64-`GPR_WIDTH:63] byp_div_ex2_rs1; + wire [64-`GPR_WIDTH:63] byp_div_ex2_rs2; + wire [0:9] byp_div_ex2_xer; + wire [0:`GPR_WIDTH-1] byp_mul_ex2_rs1; + wire [0:`GPR_WIDTH-1] byp_mul_ex2_rs2; + wire byp_mul_ex2_abort; + wire [0:9] byp_mul_ex2_xer; + wire [32:63] byp_dlm_ex2_rs1; + wire [32:63] byp_dlm_ex2_rs2; + wire [0:2] byp_dlm_ex2_xer; + wire br_byp_ex3_lr_we; + wire [64-`GPR_WIDTH:63] br_byp_ex3_lr_wd; + wire br_byp_ex3_ctr_we; + wire [64-`GPR_WIDTH:63] br_byp_ex3_ctr_wd; + wire br_byp_ex3_cr_we; + wire [0:3] br_byp_ex3_cr_wd; + wire [64-`GPR_WIDTH:63] div_byp_ex4_rt; + wire div_byp_ex4_done; + wire [0:9] div_byp_ex4_xer; + wire [0:3] div_byp_ex4_cr; + wire [0:7] dec_div_ex1_div_ctr; + wire [0:`THREADS-1] dec_div_ex1_div_val; + wire dec_div_ex1_div_act; + wire dec_div_ex1_div_sign; + wire dec_div_ex1_div_size; + wire dec_div_ex1_div_extd; + wire dec_div_ex1_div_recform; + wire dec_div_ex1_xer_ov_update; + wire dec_mul_ex1_mul_recform; + wire [0:`THREADS-1] dec_mul_ex1_mul_val; + wire dec_mul_ex1_mul_ord; + wire dec_mul_ex1_mul_ret; + wire dec_mul_ex1_mul_sign; + wire dec_mul_ex1_mul_size; + wire dec_mul_ex1_mul_imm; + wire dec_mul_ex1_xer_ov_update; + wire mul_byp_ex5_ord_done; + wire mul_byp_ex5_done; + wire mul_byp_ex5_abort; + wire [64-`GPR_WIDTH:63] mul_byp_ex6_rt; + wire [0:9] mul_byp_ex6_xer; + wire [0:3] mul_byp_ex6_cr; + wire [0:3] byp_br_ex3_cr; + wire [0:3] byp_br_ex2_cr1; + wire [0:3] byp_br_ex2_cr2; + wire [0:3] byp_br_ex2_cr3; + wire [64-`GPR_WIDTH:63] byp_br_ex2_lr1; + wire [64-`GPR_WIDTH:63] byp_br_ex2_lr2; + wire [64-`GPR_WIDTH:63] byp_br_ex2_ctr; + wire ex1_spr_msr_cm; + wire ex4_spr_msr_cm; + wire [0:`THREADS-1] br_dec_ex3_execute_vld; + wire dec_byp_ex1_rs_capt; + wire dec_byp_ex1_ra_capt; + wire mul_dec_ex6_ord_done; + wire div_dec_ex4_done; + wire [64-`GPR_WIDTH:63] pop_byp_ex4_rt; + wire [57:63] cnt_byp_ex2_rt; + wire [56:63] prm_byp_ex2_rt; + wire [25:25] dec_cnt_ex2_instr; + wire dec_byp_ex4_pop_done; + wire dec_byp_ex3_cnt_done; + wire dec_byp_ex3_prm_done; + wire dec_byp_ex3_dlm_done; + wire dec_br_ex0_act; + wire [60:63] dlm_byp_ex2_rt; + wire [0:9] dlm_byp_ex2_xer; + wire [0:3] dlm_byp_ex2_cr; + wire dec_bcd_ex1_val; + wire dec_bcd_ex1_is_addg6s; + wire dec_bcd_ex1_is_cdtbcd; + wire [64-`GPR_WIDTH:63] byp_bcd_ex2_rs1; + wire [64-`GPR_WIDTH:63] byp_bcd_ex2_rs2; + wire [64-`GPR_WIDTH:63] bcd_byp_ex3_rt; + wire bcd_byp_ex3_done; + wire [0:`THREADS-1] dec_ord_flush; + wire dec_byp_ex4_hpriv; + wire [0:31] dec_byp_ex4_instr; + wire byp_dec_ex2_abort; + + assign mul_dec_ex6_ord_done = mul_byp_ex5_ord_done; + assign div_dec_ex4_done = div_byp_ex4_done; + + assign xu0_debug_bus_out = xu0_debug_bus_in; + assign xu0_coretrace_ctrls_out = xu0_coretrace_ctrls_in; + + + xu_alu alu( + .nclk(nclk), + .vdd(vdd), + .gnd(gnd), + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .func_sl_force(func_sl_force), + .func_sl_thold_0_b(func_sl_thold_0_b), + .sg_0(sg_0), + .scan_in(siv[0]), + .scan_out(sov[0]), + .dec_alu_ex1_act(dec_alu_ex1_act), + .dec_alu_ex1_instr(dec_alu_ex1_instr), + .dec_alu_ex1_sel_isel(dec_alu_ex1_sel_isel), + .dec_alu_ex1_add_rs1_inv(dec_alu_ex1_add_rs1_inv), + .dec_alu_ex2_add_ci_sel(dec_alu_ex2_add_ci_sel), + .dec_alu_ex1_sel_trap(dec_alu_ex1_sel_trap), + .dec_alu_ex1_sel_cmpl(dec_alu_ex1_sel_cmpl), + .dec_alu_ex1_sel_cmp(dec_alu_ex1_sel_cmp), + .dec_alu_ex1_msb_64b_sel(dec_alu_ex1_msb_64b_sel), + .dec_alu_ex1_xer_ov_en(dec_alu_ex1_xer_ov_en), + .dec_alu_ex1_xer_ca_en(dec_alu_ex1_xer_ca_en), + .byp_alu_ex2_rs1(byp_alu_ex2_rs1), + .byp_alu_ex2_rs2(byp_alu_ex2_rs2), + .byp_alu_ex2_cr_bit(byp_alu_ex2_cr_bit), + .byp_alu_ex2_xer(byp_alu_ex2_xer), + .alu_byp_ex2_add_rt(alu_byp_ex2_add_rt), + .alu_byp_ex3_rt(alu_byp_ex3_rt), + .alu_byp_ex3_cr(alu_byp_ex3_cr), + .alu_byp_ex3_xer(alu_byp_ex3_xer), + .alu_dec_ex3_trap_val(alu_dec_ex3_trap_val) + ); + + + tri_st_popcnt pop( + .nclk(nclk), + .vdd(vdd), + .gnd(gnd), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .d_mode_dc(d_mode_dc), + .func_sl_force(func_sl_force), + .func_sl_thold_0_b(func_sl_thold_0_b), + .sg_0(sg_0), + .scan_in(siv[1]), + .scan_out(sov[1]), + .ex1_act(dec_pop_ex1_act), + .ex1_instr(dec_alu_ex1_instr[22:23]), + .ex2_popcnt_rs1(byp_pop_ex2_rs1), + .ex4_popcnt_rt(pop_byp_ex4_rt) + ); + + + tri_st_cntlz cnt( + .dword(dec_cnt_ex2_instr[25]), + .a(byp_cnt_ex2_rs1), + .y(cnt_byp_ex2_rt) + ); + + generate begin : bperm + genvar i; + for (i=0;i<=7;i=i+1) begin : bprm_bit + xu0_bprm bperm_bit( + .a(byp_alu_ex2_rs2), + .s(byp_alu_ex2_rs1[8 * i + 0:8 * i + 7]), + .y(prm_byp_ex2_rt[56 + i]) + ); + end + end + endgenerate + + + xu0_bcd bcd( + .nclk(nclk), + .vdd(vdd), + .gnd(gnd), + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .func_sl_force(func_sl_force), + .func_sl_thold_0_b(func_sl_thold_0_b), + .sg_0(sg_0), + .scan_in(siv[2]), + .scan_out(sov[2]), + .dec_bcd_ex1_val(dec_bcd_ex1_val), + .dec_bcd_ex1_is_addg6s(dec_bcd_ex1_is_addg6s), + .dec_bcd_ex1_is_cdtbcd(dec_bcd_ex1_is_cdtbcd), + .byp_bcd_ex2_rs1(byp_bcd_ex2_rs1), + .byp_bcd_ex2_rs2(byp_bcd_ex2_rs2), + .bcd_byp_ex3_rt(bcd_byp_ex3_rt), + .bcd_byp_ex3_done(bcd_byp_ex3_done) + ); + + + xu0_dlmzb dlm( + .byp_dlm_ex2_rs1(byp_dlm_ex2_rs1), + .byp_dlm_ex2_rs2(byp_dlm_ex2_rs2), + .byp_dlm_ex2_xer(byp_dlm_ex2_xer), + .dlm_byp_ex2_xer(dlm_byp_ex2_xer), + .dlm_byp_ex2_cr(dlm_byp_ex2_cr), + .dlm_byp_ex2_rt(dlm_byp_ex2_rt) + ); + + + xu0_div_r4 div( + .nclk(nclk), + .vdd(vdd), + .gnd(gnd), + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .func_sl_force(func_sl_force), + .func_sl_thold_0_b(func_sl_thold_0_b), + .sg_0(sg_0), + .scan_in(siv[3]), + .scan_out(sov[3]), + .dec_div_ex1_div_ctr(dec_div_ex1_div_ctr), + .dec_div_ex1_div_act(dec_div_ex1_div_act), + .dec_div_ex1_div_val(dec_div_ex1_div_val), + .dec_div_ex1_div_sign(dec_div_ex1_div_sign), + .dec_div_ex1_div_size(dec_div_ex1_div_size), + .dec_div_ex1_div_extd(dec_div_ex1_div_extd), + .dec_div_ex1_div_recform(dec_div_ex1_div_recform), + .dec_div_ex1_xer_ov_update(dec_div_ex1_xer_ov_update), + .byp_div_ex2_rs1(byp_div_ex2_rs1), + .byp_div_ex2_rs2(byp_div_ex2_rs2), + .byp_div_ex2_xer(byp_div_ex2_xer), + .cp_flush(dec_ord_flush), + .div_byp_ex4_rt(div_byp_ex4_rt), + .div_byp_ex4_done(div_byp_ex4_done), + .div_byp_ex4_xer(div_byp_ex4_xer), + .div_byp_ex4_cr(div_byp_ex4_cr), + .ex1_spr_msr_cm(ex1_spr_msr_cm), + .div_spr_running(div_spr_running) + ); + + + tri_st_mult mult( + .nclk(nclk), + .vdd(vdd), + .gnd(gnd), + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .func_sl_force(func_sl_force), + .func_sl_thold_0_b(func_sl_thold_0_b), + .sg_0(sg_0), + .scan_in(siv[4]), + .scan_out(sov[4]), + .dec_mul_ex1_mul_recform(dec_mul_ex1_mul_recform), + .dec_mul_ex1_mul_val(dec_mul_ex1_mul_val), + .dec_mul_ex1_mul_ord(dec_mul_ex1_mul_ord), + .dec_mul_ex1_mul_ret(dec_mul_ex1_mul_ret), + .dec_mul_ex1_mul_sign(dec_mul_ex1_mul_sign), + .dec_mul_ex1_mul_size(dec_mul_ex1_mul_size), + .dec_mul_ex1_mul_imm(dec_mul_ex1_mul_imm), + .dec_mul_ex1_xer_ov_update(dec_mul_ex1_xer_ov_update), + .cp_flush(cp_flush), + .ex1_spr_msr_cm(ex1_spr_msr_cm), + .byp_mul_ex2_rs1(byp_mul_ex2_rs1), + .byp_mul_ex2_rs2(byp_mul_ex2_rs2), + .byp_mul_ex2_abort(byp_mul_ex2_abort), + .byp_mul_ex2_xer(byp_mul_ex2_xer), + .mul_byp_ex5_abort(mul_byp_ex5_abort), + .mul_byp_ex6_rt(mul_byp_ex6_rt), + .mul_byp_ex6_xer(mul_byp_ex6_xer), + .mul_byp_ex6_cr(mul_byp_ex6_cr), + .mul_byp_ex5_ord_done(mul_byp_ex5_ord_done), + .mul_byp_ex5_done(mul_byp_ex5_done), + .mul_spr_running(mul_spr_running) + ); + + + xu0_br br( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .pc_br_func_sl_thold_2(1'b0), //<> + .pc_br_sg_2(1'b1), //<> + .clkoff_b(1'b1), //<> + .act_dis(1'b0), //<> + .tc_ac_ccflush_dc(pc_xu_ccflush_dc), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .scan_in(siv[5]), + .scan_out(sov[5]), + .rv_br_vld(rv_xu0_vld), + .rv_br_ex0_fusion(rv_xu0_ex0_fusion[0]), + .rv_br_ex0_instr(rv_xu0_ex0_instr), + .rv_br_ex0_ifar(rv_xu0_ex0_ifar), + .rv_br_ex0_itag(rv_xu0_ex0_itag), + .rv_br_ex0_t2_p(rv_xu0_ex0_t2_p), + .rv_br_ex0_t3_p(rv_xu0_ex0_t3_p), + .rv_br_ex0_bta_val(rv_xu0_ex0_bta_val), + .rv_br_ex0_pred_bta(rv_xu0_ex0_pred_bta), + .rv_br_ex0_pred(rv_xu0_ex0_pred), + .rv_br_ex0_ls_ptr(rv_xu0_ex0_ls_ptr), + .rv_br_ex0_bh_update(rv_xu0_ex0_bh_update), + .rv_br_ex0_gshare(rv_xu0_ex0_gshare), + .rv_br_ex0_spec_flush(rv_xu0_ex0_spec_flush), + .rv_br_ex1_spec_flush(rv_xu0_ex1_spec_flush), + .dec_br_ex0_act(dec_br_ex0_act), + .bp_br_ex2_abort(byp_dec_ex2_abort), + .byp_br_ex2_cr1(byp_br_ex2_cr1), + .byp_br_ex2_cr2(byp_br_ex2_cr2), + .byp_br_ex2_cr3(byp_br_ex2_cr3), + .byp_br_ex2_lr1(byp_br_ex2_lr1), + .byp_br_ex2_lr2(byp_br_ex2_lr2), + .byp_br_ex2_ctr(byp_br_ex2_ctr), + .mux_br_ex3_cr(byp_br_ex3_cr), + .br_lr_we(br_byp_ex3_lr_we), + .br_lr_wd(br_byp_ex3_lr_wd), + .br_ctr_we(br_byp_ex3_ctr_we), + .br_ctr_wd(br_byp_ex3_ctr_wd), + .br_cr_we(br_byp_ex3_cr_we), + .br_cr_wd(br_byp_ex3_cr_wd), + .br_iu_execute_vld(br_iu_execute_vld), + .br_iu_itag(br_iu_itag), + .br_iu_taken(br_iu_taken), + .br_iu_bta(br_iu_bta), + .br_iu_gshare(br_iu_gshare), + .br_iu_ls_ptr(br_iu_ls_ptr), + .br_iu_ls_data(br_iu_ls_data), + .br_iu_ls_update(br_iu_ls_update), + .br_iu_redirect(br_iu_redirect), + .br_iu_perf_events(br_iu_perf_events), + .perf_event_en(perf_event_en), + .spr_xesr2(spr_xesr2), + .spr_msr_cm(spr_msr_cm), //<> + .br_dec_ex3_execute_vld(br_dec_ex3_execute_vld), + .iu_br_t0_flush_ifar(iu_br_t0_flush_ifar), + `ifndef THREADS1 + .iu_br_t1_flush_ifar(iu_br_t1_flush_ifar), + `endif + .iu_br_flush(cp_flush) + ); + + + xu0_byp byp( + .nclk(nclk), + .vdd(vdd), + .gnd(gnd), + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .func_sl_force(func_sl_force), + .func_sl_thold_0_b(func_sl_thold_0_b), + .sg_0(sg_0), + .scan_in(siv[6]), + .scan_out(sov[6]), + .ex4_spr_msr_cm(ex4_spr_msr_cm), + .dec_byp_ex0_act(dec_byp_ex0_act), + .xu1_xu0_ex3_act(xu1_xu0_ex3_act), + .lq_xu_ex5_act(lq_xu_ex5_act), + .dec_byp_ex1_imm(dec_byp_ex1_imm), + .dec_byp_ex1_instr(dec_byp_ex1_instr), + .dec_byp_ex1_is_mflr(dec_byp_ex1_is_mflr), + .dec_byp_ex1_is_mfxer(dec_byp_ex1_is_mfxer), + .dec_byp_ex1_is_mtxer(dec_byp_ex1_is_mtxer), + .dec_byp_ex1_is_mfcr_sel(dec_byp_ex1_is_mfcr_sel), + .dec_byp_ex1_is_mfcr(dec_byp_ex1_is_mfcr), + .dec_byp_ex1_is_mtcr(dec_byp_ex1_is_mtcr), + .dec_byp_ex1_is_mfctr(dec_byp_ex1_is_mfctr), + .dec_byp_ex3_is_mtspr(dec_byp_ex3_is_mtspr), + .dec_byp_ex1_cr_sel(dec_byp_ex1_cr_sel), + .dec_byp_ex1_xer_sel(dec_byp_ex1_xer_sel), + .dec_byp_ex1_rs_capt(dec_byp_ex1_rs_capt), + .dec_byp_ex1_ra_capt(dec_byp_ex1_ra_capt), + .dec_byp_ex0_rs2_sel_imm(dec_byp_ex0_rs2_sel_imm), + .dec_byp_ex0_rs1_sel_zero(dec_byp_ex0_rs1_sel_zero), + .dec_byp_ex3_mtiar(dec_byp_ex3_mtiar), + .dec_byp_ex4_hpriv(dec_byp_ex4_hpriv), + .dec_byp_ex4_instr(dec_byp_ex4_instr), + .dec_byp_ex5_ord_sel(dec_byp_ex5_ord_sel), + .rv_xu0_ex0_s1_v(rv_xu0_ex0_s1_v), + .rv_xu0_ex0_s2_v(rv_xu0_ex0_s2_v), + .rv_xu0_ex0_s3_v(rv_xu0_ex0_s3_v), + .rv_xu0_s1_fxu0_sel(rv_xu0_s1_fxu0_sel), + .rv_xu0_s2_fxu0_sel(rv_xu0_s2_fxu0_sel), + .rv_xu0_s3_fxu0_sel(rv_xu0_s3_fxu0_sel), + .rv_xu0_s1_fxu1_sel(rv_xu0_s1_fxu1_sel), + .rv_xu0_s2_fxu1_sel(rv_xu0_s2_fxu1_sel), + .rv_xu0_s3_fxu1_sel(rv_xu0_s3_fxu1_sel), + .rv_xu0_s1_lq_sel(rv_xu0_s1_lq_sel), + .rv_xu0_s2_lq_sel(rv_xu0_s2_lq_sel), + .rv_xu0_s3_lq_sel(rv_xu0_s3_lq_sel), + .rv_xu0_s1_rel_sel(rv_xu0_s1_rel_sel), + .rv_xu0_s2_rel_sel(rv_xu0_s2_rel_sel), + .gpr_xu0_ex1_r1d(gpr_xu0_ex1_r1d), + .gpr_xu0_ex1_r2d(gpr_xu0_ex1_r2d), + .xer_xu0_ex1_r2d(xer_xu0_ex1_r2d), + .xer_xu0_ex1_r3d(xer_xu0_ex1_r3d), + .cr_xu0_ex1_r1d(cr_xu0_ex1_r1d), + .cr_xu0_ex1_r2d(cr_xu0_ex1_r2d), + .cr_xu0_ex1_r3d(cr_xu0_ex1_r3d), + .lr_xu0_ex1_r1d(lr_xu0_ex1_r1d), + .lr_xu0_ex1_r2d(lr_xu0_ex1_r2d), + .ctr_xu0_ex1_r2d(ctr_xu0_ex1_r2d), + .xu1_xu0_ex2_abort(xu1_xu0_ex2_abort), + .xu1_xu0_ex2_rt(xu1_xu0_ex2_rt), + .xu1_xu0_ex3_rt(xu1_xu0_ex3_rt), + .xu1_xu0_ex4_rt(xu1_xu0_ex4_rt), + .xu1_xu0_ex5_rt(xu1_xu0_ex5_rt), + .lq_xu_ex5_abort(lq_xu_ex5_abort), + .lq_xu_ex5_rt(lq_xu_ex5_rt), + .lq_xu_rel_act(lq_xu_rel_act), + .lq_xu_rel_rt(lq_xu_rel_rt), + .lq_xu_ex5_data(lq_xu_ex5_data), + .lq_xu_ex5_cr(lq_xu_ex5_cr), + .xu1_xu0_ex3_cr(xu1_xu0_ex3_cr), + .xu1_xu0_ex3_xer(xu1_xu0_ex3_xer), + .alu_byp_ex2_add_rt(alu_byp_ex2_add_rt), + .alu_byp_ex3_rt(alu_byp_ex3_rt), + .alu_byp_ex3_cr(alu_byp_ex3_cr), + .alu_byp_ex3_xer(alu_byp_ex3_xer), + .br_byp_ex3_lr_we(br_byp_ex3_lr_we), + .br_byp_ex3_lr_wd(br_byp_ex3_lr_wd), + .br_byp_ex3_ctr_we(br_byp_ex3_ctr_we), + .br_byp_ex3_ctr_wd(br_byp_ex3_ctr_wd), + .br_byp_ex3_cr_we(br_byp_ex3_cr_we), + .br_byp_ex3_cr_wd(br_byp_ex3_cr_wd), + .spr_xu_ord_write_done(spr_xu_ord_write_done), + .spr_xu_ex4_rd_data(spr_xu_ex4_rd_data), + .xu_spr_ex2_rs1(xu_spr_ex2_rs1), + .xu_slowspr_val_in(xu_slowspr_val_in), + .xu_slowspr_rw_in(xu_slowspr_rw_in), + .xu_slowspr_data_in(xu_slowspr_data_in), + .xu_slowspr_done_in(xu_slowspr_done_in), + .div_byp_ex4_done(div_byp_ex4_done), + .div_byp_ex4_rt(div_byp_ex4_rt), + .div_byp_ex4_xer(div_byp_ex4_xer), + .div_byp_ex4_cr(div_byp_ex4_cr), + .mul_byp_ex5_ord_done(mul_byp_ex5_ord_done), + .mul_byp_ex5_done(mul_byp_ex5_done), + .mul_byp_ex5_abort(mul_byp_ex5_abort), + .mul_byp_ex6_rt(mul_byp_ex6_rt), + .mul_byp_ex6_xer(mul_byp_ex6_xer), + .mul_byp_ex6_cr(mul_byp_ex6_cr), + .dec_byp_ex4_pop_done(dec_byp_ex4_pop_done), + .dec_byp_ex3_cnt_done(dec_byp_ex3_cnt_done), + .dec_byp_ex3_prm_done(dec_byp_ex3_prm_done), + .dec_byp_ex3_dlm_done(dec_byp_ex3_dlm_done), + .bcd_byp_ex3_done(bcd_byp_ex3_done), + .pop_byp_ex4_rt(pop_byp_ex4_rt), + .cnt_byp_ex2_rt(cnt_byp_ex2_rt), + .prm_byp_ex2_rt(prm_byp_ex2_rt), + .dlm_byp_ex2_rt(dlm_byp_ex2_rt), + .dlm_byp_ex2_xer(dlm_byp_ex2_xer), + .dlm_byp_ex2_cr(dlm_byp_ex2_cr), + .bcd_byp_ex3_rt(bcd_byp_ex3_rt), + .iu_xu_ord_write_done(iu_xu_ord_write_done), + .iu_xu_ex5_data(iu_xu_ex5_data), + .lq_xu_ord_write_done(lq_xu_ord_write_done), + .mm_xu_cr0_eq(mm_xu_cr0_eq), + .mm_xu_cr0_eq_valid(mm_xu_cr0_eq_valid), + .xu0_iu_bta(xu0_iu_bta), + .xu_iu_rs_is(xu_iu_rs_is), + .xu_iu_ra_entry(xu_iu_ra_entry), + .xu_iu_rb(xu_iu_rb), + .xu_iu_rs_data(xu_iu_rs_data), + .xu_lq_rs_is(xu_lq_rs_is), + .xu_lq_ra_entry(xu_lq_ra_entry), + .xu_lq_rb(xu_lq_rb), + .xu_lq_rs_data(xu_lq_rs_data), + .xu_mm_ra_entry(xu_mm_ra_entry), + .xu_mm_rb(xu_mm_rb), + .xu0_xu1_ex2_abort(xu0_xu1_ex2_abort), + .xu0_xu1_ex6_abort(xu0_xu1_ex6_abort), + .xu0_lq_ex3_abort(xu0_lq_ex3_abort), + .xu0_xu1_ex2_rt(xu0_xu1_ex2_rt), + .xu0_xu1_ex3_rt(xu0_xu1_ex3_rt), + .xu0_xu1_ex4_rt(xu0_xu1_ex4_rt), + .xu0_xu1_ex5_rt(xu0_xu1_ex5_rt), + .xu0_xu1_ex6_rt(xu0_xu1_ex6_rt), + .xu0_xu1_ex7_rt(xu0_xu1_ex7_rt), + .xu0_xu1_ex8_rt(xu0_xu1_ex8_rt), + .xu0_xu1_ex6_lq_rt(xu0_xu1_ex6_lq_rt), + .xu0_xu1_ex7_lq_rt(xu0_xu1_ex7_lq_rt), + .xu0_xu1_ex8_lq_rt(xu0_xu1_ex8_lq_rt), + .xu0_lq_ex3_rt(xu0_lq_ex3_rt), + .xu0_lq_ex4_rt(xu0_lq_ex4_rt), + .xu0_lq_ex6_act(xu0_lq_ex6_act), + .xu0_lq_ex6_rt(xu0_lq_ex6_rt), + .xu0_pc_ram_data(xu0_pc_ram_data), + .xu0_xu1_ex3_cr(xu0_xu1_ex3_cr), + .xu0_xu1_ex4_cr(xu0_xu1_ex4_cr), + .xu0_xu1_ex6_cr(xu0_xu1_ex6_cr), + .xu0_xu1_ex3_xer(xu0_xu1_ex3_xer), + .xu0_xu1_ex4_xer(xu0_xu1_ex4_xer), + .xu0_xu1_ex6_xer(xu0_xu1_ex6_xer), + .byp_alu_ex2_rs1(byp_alu_ex2_rs1), + .byp_alu_ex2_rs2(byp_alu_ex2_rs2), + .byp_alu_ex2_cr_bit(byp_alu_ex2_cr_bit), + .byp_alu_ex2_xer(byp_alu_ex2_xer), + .byp_pop_ex2_rs1(byp_pop_ex2_rs1), + .byp_cnt_ex2_rs1(byp_cnt_ex2_rs1), + .byp_div_ex2_rs1(byp_div_ex2_rs1), + .byp_div_ex2_rs2(byp_div_ex2_rs2), + .byp_div_ex2_xer(byp_div_ex2_xer), + .byp_mul_ex2_rs1(byp_mul_ex2_rs1), + .byp_mul_ex2_rs2(byp_mul_ex2_rs2), + .byp_mul_ex2_abort(byp_mul_ex2_abort), + .byp_mul_ex2_xer(byp_mul_ex2_xer), + .byp_dlm_ex2_rs1(byp_dlm_ex2_rs1), + .byp_dlm_ex2_rs2(byp_dlm_ex2_rs2), + .byp_dlm_ex2_xer(byp_dlm_ex2_xer), + .byp_bcd_ex2_rs1(byp_bcd_ex2_rs1), + .byp_bcd_ex2_rs2(byp_bcd_ex2_rs2), + .byp_br_ex3_cr(byp_br_ex3_cr), + .byp_br_ex2_cr1(byp_br_ex2_cr1), + .byp_br_ex2_cr2(byp_br_ex2_cr2), + .byp_br_ex2_cr3(byp_br_ex2_cr3), + .byp_br_ex2_lr1(byp_br_ex2_lr1), + .byp_br_ex2_lr2(byp_br_ex2_lr2), + .byp_br_ex2_ctr(byp_br_ex2_ctr), + .xu0_rv_ex2_s1_abort(xu0_rv_ex2_s1_abort), + .xu0_rv_ex2_s2_abort(xu0_rv_ex2_s2_abort), + .xu0_rv_ex2_s3_abort(xu0_rv_ex2_s3_abort), + .byp_dec_ex2_abort(byp_dec_ex2_abort), + .xu0_gpr_ex6_wd(xu0_gpr_ex6_wd), + .xu0_xer_ex6_w0d(xu0_xer_ex6_w0d), + .xu0_cr_ex6_w0d(xu0_cr_ex6_w0d), + .xu0_ctr_ex4_w0d(xu0_ctr_ex4_w0d), + .xu0_lr_ex4_w0d(xu0_lr_ex4_w0d) + ); + + + xu0_dec dec( + .nclk(nclk), + .vdd(vdd), + .gnd(gnd), + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .func_sl_force(func_sl_force), + .func_sl_thold_0_b(func_sl_thold_0_b), + .sg_0(sg_0), + .scan_in(siv[7]), + .scan_out(sov[7]), + .cp_flush(cp_flush), + .cp_next_itag_t0(cp_next_itag_t0), + `ifndef THREADS1 + .cp_next_itag_t1(cp_next_itag_t1), + `endif + .dec_ex0_flush(), + .dec_ex1_flush(), + .dec_ex2_flush(), + .dec_ex3_flush(), + .dec_cp_flush(), + .rv_xu0_vld(rv_xu0_vld), + .rv_xu0_ex0_ord(rv_xu0_ex0_ord), + .rv_xu0_ex0_fusion(rv_xu0_ex0_fusion), + .rv_xu0_ex0_instr(rv_xu0_ex0_instr), + .rv_xu0_ex0_itag(rv_xu0_ex0_itag), + .rv_xu0_ex0_ucode(rv_xu0_ex0_ucode), + .rv_xu0_ex0_s1_v(rv_xu0_ex0_s1_v), + .rv_xu0_ex0_s2_v(rv_xu0_ex0_s2_v), + .rv_xu0_ex0_s2_t(rv_xu0_ex0_s2_t), + .rv_xu0_ex0_s3_v(rv_xu0_ex0_s3_v), + .rv_xu0_ex0_s3_t(rv_xu0_ex0_s3_t), + .rv_xu0_ex0_t1_v(rv_xu0_ex0_t1_v), + .rv_xu0_ex0_t1_p(rv_xu0_ex0_t1_p), + .rv_xu0_ex0_t1_t(rv_xu0_ex0_t1_t), + .rv_xu0_ex0_t2_v(rv_xu0_ex0_t2_v), + .rv_xu0_ex0_t2_p(rv_xu0_ex0_t2_p), + .rv_xu0_ex0_t2_t(rv_xu0_ex0_t2_t), + .rv_xu0_ex0_t3_v(rv_xu0_ex0_t3_v), + .rv_xu0_ex0_t3_p(rv_xu0_ex0_t3_p), + .rv_xu0_ex0_t3_t(rv_xu0_ex0_t3_t), + .rv_xu0_ex0_spec_flush(rv_xu0_ex0_spec_flush), + .rv_xu0_ex1_spec_flush(rv_xu0_ex1_spec_flush), + .rv_xu0_ex2_spec_flush(rv_xu0_ex2_spec_flush), + .xu0_rv_ord_complete(xu0_rv_ord_complete), + .xu0_rv_ord_itag(xu0_rv_ord_itag), + .xu0_rv_hold_all(xu0_rv_hold_all), + .xu0_iu_execute_vld(xu0_iu_execute_vld), + .xu0_iu_itag(xu0_iu_itag), + .xu0_iu_mtiar(xu0_iu_mtiar), + .xu0_iu_exception_val(xu0_iu_exception_val), + .xu0_iu_exception(xu0_iu_exception), + .xu0_iu_n_flush(xu0_iu_n_flush), + .xu0_iu_np1_flush(xu0_iu_np1_flush), + .xu0_iu_flush2ucode(xu0_iu_flush2ucode), + .xu0_iu_perf_events(xu0_iu_perf_events), + .xu0_pc_ram_done(xu0_pc_ram_done), + .xu_iu_np1_async_flush(xu_iu_np1_async_flush), + .iu_xu_async_complete(iu_xu_async_complete), + .iu_xu_credits_returned(iu_xu_credits_returned), + .xu_iu_pri_val(xu_iu_pri_val), + .xu_iu_pri(xu_iu_pri), + .dec_pop_ex1_act(dec_pop_ex1_act), + .dec_alu_ex1_act(dec_alu_ex1_act), + .dec_alu_ex1_instr(dec_alu_ex1_instr), + .dec_alu_ex1_sel_isel(dec_alu_ex1_sel_isel), + .dec_alu_ex1_add_rs1_inv(dec_alu_ex1_add_rs1_inv), + .dec_alu_ex2_add_ci_sel(dec_alu_ex2_add_ci_sel), + .dec_alu_ex1_sel_trap(dec_alu_ex1_sel_trap), + .dec_alu_ex1_sel_cmpl(dec_alu_ex1_sel_cmpl), + .dec_alu_ex1_sel_cmp(dec_alu_ex1_sel_cmp), + .dec_alu_ex1_msb_64b_sel(dec_alu_ex1_msb_64b_sel), + .dec_alu_ex1_xer_ov_en(dec_alu_ex1_xer_ov_en), + .dec_alu_ex1_xer_ca_en(dec_alu_ex1_xer_ca_en), + .alu_dec_ex3_trap_val(alu_dec_ex3_trap_val), + .xu0_xu1_ex3_act(xu0_xu1_ex3_act), + .dec_mul_ex1_mul_recform(dec_mul_ex1_mul_recform), + .dec_mul_ex1_mul_val(dec_mul_ex1_mul_val), + .dec_mul_ex1_mul_ord(dec_mul_ex1_mul_ord), + .dec_mul_ex1_mul_ret(dec_mul_ex1_mul_ret), + .dec_mul_ex1_mul_sign(dec_mul_ex1_mul_sign), + .dec_mul_ex1_mul_size(dec_mul_ex1_mul_size), + .dec_mul_ex1_mul_imm(dec_mul_ex1_mul_imm), + .dec_mul_ex1_xer_ov_update(dec_mul_ex1_xer_ov_update), + .mul_dec_ex6_ord_done(mul_dec_ex6_ord_done), + .dec_ord_flush(dec_ord_flush), + .dec_div_ex1_div_ctr(dec_div_ex1_div_ctr), + .dec_div_ex1_div_act(dec_div_ex1_div_act), + .dec_div_ex1_div_val(dec_div_ex1_div_val), + .dec_div_ex1_div_sign(dec_div_ex1_div_sign), + .dec_div_ex1_div_size(dec_div_ex1_div_size), + .dec_div_ex1_div_extd(dec_div_ex1_div_extd), + .dec_div_ex1_div_recform(dec_div_ex1_div_recform), + .dec_div_ex1_xer_ov_update(dec_div_ex1_xer_ov_update), + .div_dec_ex4_done(div_dec_ex4_done), + .spr_xu_ord_read_done(spr_xu_ord_read_done), + .spr_xu_ord_write_done(spr_xu_ord_write_done), + .spr_dec_ex4_spr_hypv(spr_dec_ex4_spr_hypv), + .spr_dec_ex4_spr_illeg(spr_dec_ex4_spr_illeg), + .spr_dec_ex4_spr_priv(spr_dec_ex4_spr_priv), + .spr_dec_ex4_np1_flush(spr_dec_ex4_np1_flush), + .xu_slowspr_val_in(xu_slowspr_val_in), + .xu_slowspr_rw_in(xu_slowspr_rw_in), + .dec_bcd_ex1_val(dec_bcd_ex1_val), + .dec_bcd_ex1_is_addg6s(dec_bcd_ex1_is_addg6s), + .dec_bcd_ex1_is_cdtbcd(dec_bcd_ex1_is_cdtbcd), + .byp_dec_ex2_abort(byp_dec_ex2_abort), + .dec_byp_ex0_act(dec_byp_ex0_act), + .dec_byp_ex1_imm(dec_byp_ex1_imm), + .dec_byp_ex1_instr(dec_byp_ex1_instr), + .dec_byp_ex0_rs2_sel_imm(dec_byp_ex0_rs2_sel_imm), + .dec_byp_ex0_rs1_sel_zero(dec_byp_ex0_rs1_sel_zero), + .dec_byp_ex1_is_mflr(dec_byp_ex1_is_mflr), + .dec_byp_ex1_is_mfxer(dec_byp_ex1_is_mfxer), + .dec_byp_ex1_is_mtxer(dec_byp_ex1_is_mtxer), + .dec_byp_ex1_is_mfcr_sel(dec_byp_ex1_is_mfcr_sel), + .dec_byp_ex1_is_mfcr(dec_byp_ex1_is_mfcr), + .dec_byp_ex1_is_mtcr(dec_byp_ex1_is_mtcr), + .dec_byp_ex1_is_mfctr(dec_byp_ex1_is_mfctr), + .dec_byp_ex3_is_mtspr(dec_byp_ex3_is_mtspr), + .dec_byp_ex1_cr_sel(dec_byp_ex1_cr_sel), + .dec_byp_ex1_xer_sel(dec_byp_ex1_xer_sel), + .dec_byp_ex1_rs_capt(dec_byp_ex1_rs_capt), + .dec_byp_ex1_ra_capt(dec_byp_ex1_ra_capt), + .dec_byp_ex3_mtiar(dec_byp_ex3_mtiar), + .dec_byp_ex5_ord_sel(dec_byp_ex5_ord_sel), + .dec_byp_ex4_pop_done(dec_byp_ex4_pop_done), + .dec_byp_ex3_cnt_done(dec_byp_ex3_cnt_done), + .dec_byp_ex3_prm_done(dec_byp_ex3_prm_done), + .dec_byp_ex3_dlm_done(dec_byp_ex3_dlm_done), + .dec_byp_ex4_hpriv(dec_byp_ex4_hpriv), + .dec_byp_ex4_instr(dec_byp_ex4_instr), + .dec_cnt_ex2_instr(dec_cnt_ex2_instr), + .dec_br_ex0_act(dec_br_ex0_act), + .br_dec_ex3_execute_vld(br_dec_ex3_execute_vld), + .xu0_gpr_ex6_we(xu0_gpr_ex6_we), + .xu0_gpr_ex6_wa(xu0_gpr_ex6_wa), + .xu0_xer_ex6_we(xu0_xer_ex6_we), + .xu0_xer_ex6_wa(xu0_xer_ex6_wa), + .xu0_cr_ex6_we(xu0_cr_ex6_we), + .xu0_cr_ex6_wa(xu0_cr_ex6_wa), + .xu0_ctr_ex4_we(xu0_ctr_ex4_we), + .xu0_ctr_ex4_wa(xu0_ctr_ex4_wa), + .xu0_lr_ex4_we(xu0_lr_ex4_we), + .xu0_lr_ex4_wa(xu0_lr_ex4_wa), + .xu_iu_ord_ready(xu_iu_ord_ready), + .xu_iu_act(xu_iu_act), + .xu_iu_val(xu_iu_val), + .xu_iu_is_eratre(xu_iu_is_eratre), + .xu_iu_is_eratwe(xu_iu_is_eratwe), + .xu_iu_is_eratsx(xu_iu_is_eratsx), + .xu_iu_is_eratilx(xu_iu_is_eratilx), + .xu_iu_is_erativax(xu_iu_is_erativax), + .xu_iu_ws(xu_iu_ws), + .xu_iu_t(xu_iu_t), + .iu_xu_ord_read_done(iu_xu_ord_read_done), + .iu_xu_ord_write_done(iu_xu_ord_write_done), + .iu_xu_ord_n_flush_req(iu_xu_ord_n_flush_req), + .iu_xu_ord_par_err(iu_xu_ord_par_err), + .xu_lq_ord_ready(xu_lq_ord_ready), + .xu_lq_act(xu_lq_act), + .xu_lq_val(xu_lq_val), + .xu_lq_hold_req(xu_lq_hold_req), + .xu_lq_is_eratre(xu_lq_is_eratre), + .xu_lq_is_eratwe(xu_lq_is_eratwe), + .xu_lq_is_eratsx(xu_lq_is_eratsx), + .xu_lq_is_eratilx(xu_lq_is_eratilx), + .xu_lq_ws(xu_lq_ws), + .xu_lq_t(xu_lq_t), + .lq_xu_ord_read_done(lq_xu_ord_read_done), + .lq_xu_ord_write_done(lq_xu_ord_write_done), + .lq_xu_ord_n_flush_req(lq_xu_ord_n_flush_req), + .lq_xu_ord_par_err(lq_xu_ord_par_err), + .xu_mm_ord_ready(xu_mm_ord_ready), + .xu_mm_act(xu_mm_act), + .xu_mm_val(xu_mm_val), + .xu_mm_itag(xu_mm_itag), + .xu_mm_is_tlbre(xu_mm_is_tlbre), + .xu_mm_is_tlbwe(xu_mm_is_tlbwe), + .xu_mm_is_tlbsx(xu_mm_is_tlbsx), + .xu_mm_is_tlbsxr(xu_mm_is_tlbsxr), + .xu_mm_is_tlbsrx(xu_mm_is_tlbsrx), + .xu_mm_is_tlbivax(xu_mm_is_tlbivax), + .xu_mm_is_tlbilx(xu_mm_is_tlbilx), + .mm_xu_itag(mm_xu_itag), + .mm_xu_ord_n_flush_req(mm_xu_ord_n_flush_req), + .mm_xu_ord_read_done(mm_xu_ord_read_done), + .mm_xu_ord_write_done(mm_xu_ord_write_done), + .mm_xu_tlb_miss(mm_xu_tlb_miss), + .mm_xu_lrat_miss(mm_xu_lrat_miss), + .mm_xu_tlb_inelig(mm_xu_tlb_inelig), + .mm_xu_pt_fault(mm_xu_pt_fault), + .mm_xu_hv_priv(mm_xu_hv_priv), + .mm_xu_illeg_instr(mm_xu_illeg_instr), + .mm_xu_tlb_multihit(mm_xu_tlb_multihit), + .mm_xu_tlb_par_err(mm_xu_tlb_par_err), + .mm_xu_lru_par_err(mm_xu_lru_par_err), + .mm_xu_local_snoop_reject(mm_xu_local_snoop_reject), + .mm_xu_mmucr0_tlbsel_t0(mm_xu_mmucr0_tlbsel_t0), + `ifndef THREADS1 + .mm_xu_mmucr0_tlbsel_t1(mm_xu_mmucr0_tlbsel_t1), + `endif + .mm_xu_tlbwe_binv(mm_xu_tlbwe_binv), + .xu_spr_ord_flush(xu_spr_ord_flush), + .xu_spr_ord_ready(xu_spr_ord_ready), + .ex1_spr_msr_cm(ex1_spr_msr_cm), + .ex4_spr_msr_cm(ex4_spr_msr_cm), + .spr_msr_cm(spr_msr_cm), + .spr_msr_gs(spr_msr_gs), + .spr_msr_pr(spr_msr_pr), + .spr_epcr_dgtmi(spr_epcr_dgtmi), + .spr_ccr2_notlb(spr_ccr2_notlb), + .spr_ccr2_en_attn(spr_ccr2_en_attn), + .spr_ccr4_en_dnh(spr_ccr4_en_dnh), + .spr_ccr2_en_pc(spr_ccr2_en_pc), + .spr_xesr1(spr_xesr1), + .perf_event_en(perf_event_en), + .pc_xu_ram_active(pc_xu_ram_active) + ); + + assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in}; + assign scan_out = sov[0]; + + +endmodule diff --git a/dev/verilog/work/xu0_bcd.v b/dev/verilog/work/xu0_bcd.v new file mode 100755 index 0000000..f8a8e89 --- /dev/null +++ b/dev/verilog/work/xu0_bcd.v @@ -0,0 +1,301 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//***************************************************************************** +// Description: XU BCD Assist Instructions +// +//***************************************************************************** +`include "tri_a2o.vh" + +module xu0_bcd( + // Clocks + input [0:`NCLK_WIDTH-1] nclk, + + // Power + inout vdd, + inout gnd, + + // Pervasive + input d_mode_dc, + input delay_lclkr_dc, + input mpw1_dc_b, + input mpw2_dc_b, + input func_sl_force, + input func_sl_thold_0_b, + input sg_0, + input scan_in, + output scan_out, + + // Decode Inputs + input dec_bcd_ex1_val, + input dec_bcd_ex1_is_addg6s, + input dec_bcd_ex1_is_cdtbcd, + + // Source Data + input [64-`GPR_WIDTH:63] byp_bcd_ex2_rs1, + input [64-`GPR_WIDTH:63] byp_bcd_ex2_rs2, + + // Target Data + output [64-`GPR_WIDTH:63] bcd_byp_ex3_rt, + output bcd_byp_ex3_done +); + + // Latches + wire ex2_val_q; // input=>dec_bcd_ex1_val ,act=>1'b1 + wire ex2_is_addg6s_q; // input=>dec_bcd_ex1_is_addg6s ,act=>dec_bcd_ex1_val + wire ex2_is_cdtbcd_q; // input=>dec_bcd_ex1_is_cdtbcd ,act=>dec_bcd_ex1_val + wire [64-`GPR_WIDTH:63] ex3_bcd_rt_q; // input=>ex2_bcd_rt ,act=>ex2_val_q + wire [64-`GPR_WIDTH:63] ex2_bcd_rt; + wire ex3_val_q; // input=>ex2_val_q ,act=>1'b1 + // Scanchains + localparam ex2_val_offset = 0; + localparam ex2_is_addg6s_offset = ex2_val_offset + 1; + localparam ex2_is_cdtbcd_offset = ex2_is_addg6s_offset + 1; + localparam ex3_bcd_rt_offset = ex2_is_cdtbcd_offset + 1; + localparam ex3_val_offset = ex3_bcd_rt_offset + `GPR_WIDTH; + localparam scan_right = ex3_val_offset + 1; + wire [0:scan_right-1] siv; + wire [0:scan_right-1] sov; + wire [0:63] g0; + wire [0:63] g1; + wire [0:63] g2; + wire [0:63] g3; + wire [0:63] g4; + wire [0:63] g5; + wire [0:63] g6; + wire [0:62] p0; + wire [0:61] p1; + wire [0:59] p2; + wire [0:55] p3; + wire [0:47] p4; + wire [0:31] p5; + wire [0:63] ex2_bcdtd_rt; + wire [0:63] ex2_dtbcd_rt; + wire [0:63] ex2_sixes_rt; + + (* analysis_not_referenced="true" *) + wire unused; + + // BCD to DPD + + xu0_bcd_bcdtd bcdtd00( + .a(byp_bcd_ex2_rs1[8:19]), + .y(ex2_bcdtd_rt[12:21]) + ); + + xu0_bcd_bcdtd bcdtd01( + .a(byp_bcd_ex2_rs1[20:31]), + .y(ex2_bcdtd_rt[22:31]) + ); + + xu0_bcd_bcdtd bcdtd10( + .a(byp_bcd_ex2_rs1[40:51]), + .y(ex2_bcdtd_rt[44:53]) + ); + + xu0_bcd_bcdtd bcdtd11( + .a(byp_bcd_ex2_rs1[52:63]), + .y(ex2_bcdtd_rt[54:63]) + ); + assign ex2_bcdtd_rt[0:11] = {12{1'b0}}; + assign ex2_bcdtd_rt[32:43] = {12{1'b0}}; + + // DPD to BCD + + xu0_bcd_dtbcd dtbcd00( + .a(byp_bcd_ex2_rs1[12:21]), + .y(ex2_dtbcd_rt[8:19]) + ); + + xu0_bcd_dtbcd dtbcd01( + .a(byp_bcd_ex2_rs1[22:31]), + .y(ex2_dtbcd_rt[20:31]) + ); + + xu0_bcd_dtbcd dtbcd10( + .a(byp_bcd_ex2_rs1[44:53]), + .y(ex2_dtbcd_rt[40:51]) + ); + + xu0_bcd_dtbcd dtbcd11( + .a(byp_bcd_ex2_rs1[54:63]), + .y(ex2_dtbcd_rt[52:63]) + ); + assign ex2_dtbcd_rt[0:7] = {8{1'b0}}; + assign ex2_dtbcd_rt[32:39] = {8{1'b0}}; + + // ADDG6S + assign p0[00:62] = byp_bcd_ex2_rs1[00:62] ^ byp_bcd_ex2_rs2[00:62]; + assign g0[00:63] = byp_bcd_ex2_rs1[00:63] & byp_bcd_ex2_rs2[00:63]; + // L1 (1) + assign g1[00:62] = (p0[00:62] & g0[01:63]) | g0[00:62]; + assign g1[63:63] = g0[63:63]; + assign p1[00:61] = p0[00:61] & p0[01:62]; + // L2 (2) + assign g2[00:61] = (p1[00:61] & g1[02:63]) | g1[00:61]; + assign g2[62:63] = g1[62:63]; + assign p2[00:59] = p1[00:59] & p1[02:61]; + // L3 (4) + assign g3[00:59] = (p2[00:59] & g2[04:63]) | g2[00:59]; + assign g3[60:63] = g2[60:63]; + assign p3[00:55] = p2[00:55] & p2[04:59]; + // L4 (8) + assign g4[00:55] = (p3[00:55] & g3[08:63]) | g3[00:55]; + assign g4[56:63] = g3[56:63]; + assign p4[00:47] = p3[00:47] & p3[08:55]; + // L5 (16) + assign g5[00:47] = (p4[00:47] & g4[16:63]) | g4[00:47]; + assign g5[48:63] = g4[48:63]; + assign p5[00:31] = p4[00:31] & p4[16:47]; + // L6 (32) + assign g6[00:31] = (p5[00:31] & g5[32:63]) | g5[00:31]; + assign g6[32:63] = g5[32:63]; + + generate + genvar b; + for (b = 0; b <= 15; b = b + 1) + begin : nibble + assign ex2_sixes_rt[4 * b:4 * b + 3] = (g6[b * 4] == 1'b0) ? 4'b0110 : + 4'b0000; + end + endgenerate + //!! bugspray include: tri_a2o.bil + //!! %for(i=0;i<16;++i) + //!! [count; scenarios.addg6s_n%(i)_0 ; bugclk] : (pri2) <= ex2_val_q and ex2_is_addg6s_q and not g6(%(i*4)); + //!! [count; scenarios.addg6s_n%(i)_1 ; bugclk] : (pri2) <= ex2_val_q and ex2_is_addg6s_q and g6(%(i*4)); + //!! %end + + assign ex2_bcd_rt = ({ex2_is_addg6s_q, ex2_is_cdtbcd_q} == 2'b10) ? ex2_sixes_rt : + ({ex2_is_addg6s_q, ex2_is_cdtbcd_q} == 2'b01) ? ex2_dtbcd_rt : + ex2_bcdtd_rt; + assign bcd_byp_ex3_rt = ex3_bcd_rt_q; + assign bcd_byp_ex3_done = ex3_val_q; + + + // Latches + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_val_offset]), + .scout(sov[ex2_val_offset]), + .din(dec_bcd_ex1_val), + .dout(ex2_val_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_is_addg6s_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(dec_bcd_ex1_val), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_is_addg6s_offset]), + .scout(sov[ex2_is_addg6s_offset]), + .din(dec_bcd_ex1_is_addg6s), + .dout(ex2_is_addg6s_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_is_cdtbcd_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(dec_bcd_ex1_val), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_is_cdtbcd_offset]), + .scout(sov[ex2_is_cdtbcd_offset]), + .din(dec_bcd_ex1_is_cdtbcd), + .dout(ex2_is_cdtbcd_q) + ); + + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex3_bcd_rt_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_val_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_bcd_rt_offset:ex3_bcd_rt_offset + `GPR_WIDTH - 1]), + .scout(sov[ex3_bcd_rt_offset:ex3_bcd_rt_offset + `GPR_WIDTH - 1]), + .din(ex2_bcd_rt), + .dout(ex3_bcd_rt_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_val_offset]), + .scout(sov[ex3_val_offset]), + .din(ex2_val_q), + .dout(ex3_val_q) + ); + + assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in}; + assign scan_out = sov[0]; + + assign unused = (|g6[1:3]) | (|g6[5:7]) | (|g6[9:11]) | (|g6[13:15]) | (|g6[17:19]) | (|g6[21:23]) | (|g6[25:27]) | + (|g6[29:31]) | (|g6[33:35]) | (|g6[37:39]) | (|g6[41:43]) | (|g6[45:47]) | (|g6[49:51]) | (|g6[53:55]) | + (|g6[57:59]) | (|g6[61:63]); + + +endmodule diff --git a/dev/verilog/work/xu0_bcd_bcdtd.v b/dev/verilog/work/xu0_bcd_bcdtd.v new file mode 100755 index 0000000..e6b5fab --- /dev/null +++ b/dev/verilog/work/xu0_bcd_bcdtd.v @@ -0,0 +1,52 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//***************************************************************************** +// Description: XU BCD to DPD Conversion +// +//***************************************************************************** + +module xu0_bcd_bcdtd( + input [0:11] a, + output [0:9] y +); + + assign y[0] = (a[5] & a[0] & a[8] & (~a[4])) | (a[9] & a[0] & (~a[8])) | (a[1] & (~a[0])); + assign y[1] = (a[6] & a[0] & a[8] & (~a[4])) | (a[10] & a[0] & (~a[8])) | (a[2] & (~a[0])); + assign y[2] = a[3]; + assign y[3] = (a[9] & (~a[0]) & a[4] & (~a[8])) | (a[5] & (~a[8]) & (~a[4])) | (a[5] & (~a[0]) & (~a[4])) | (a[4] & a[8]); + assign y[4] = (a[10] & (~a[0]) & a[4] & (~a[8])) | (a[6] & (~a[8]) & (~a[4])) | (a[6] & (~a[0]) & (~a[4])) | (a[0] & a[8]); + assign y[5] = a[7]; + assign y[6] = a[0] | a[4] | a[8]; + assign y[7] = ((~a[4]) & a[9] & (~a[8])) | (a[4] & a[8]) | a[0]; + assign y[8] = ((~a[0]) & a[10] & (~a[8])) | (a[0] & a[8]) | a[4]; + assign y[9] = a[11]; + +endmodule diff --git a/dev/verilog/work/xu0_bcd_dtbcd.v b/dev/verilog/work/xu0_bcd_dtbcd.v new file mode 100755 index 0000000..e2894e1 --- /dev/null +++ b/dev/verilog/work/xu0_bcd_dtbcd.v @@ -0,0 +1,54 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//***************************************************************************** +// Description: XU DPD to BCD Conversion +// +//***************************************************************************** + +module xu0_bcd_dtbcd( + input [0:9] a, + output [0:11] y +); + + assign y[0] = ((~a[3]) & a[6] & a[7]) | (a[4] & a[6] & a[7] & a[3]) | (a[6] & a[7] & (~a[8])); + assign y[1] = (a[0] & a[3] & a[8] & (~a[4])) | (a[0] & (~a[7])) | (a[0] & (~a[6])); + assign y[2] = (a[1] & a[3] & a[8] & (~a[4])) | (a[1] & (~a[7])) | (a[1] & (~a[6])); + assign y[3] = a[2]; + assign y[4] = (a[6] & (~a[7]) & a[8]) | (a[3] & a[6] & a[7] & a[8]) | ((~a[4]) & a[6] & a[8] & a[7]); + assign y[5] = (a[0] & a[4] & a[6] & a[7] & a[8] & (~a[3])) | (a[3] & (~a[8]) & a[6]) | (a[3] & (~a[6])); + assign y[6] = (a[1] & a[4] & a[7] & a[6] & a[8] & (~a[3])) | (a[4] & (~a[8]) & a[6]) | (a[4] & (~a[6])); + assign y[7] = a[5]; + assign y[8] = (a[4] & a[6] & a[7] & a[8]) | (a[3] & a[6] & a[7] & a[8]) | (a[6] & (~a[7]) & (~a[8])); + assign y[9] = (a[0] & (~a[3]) & (~a[4]) & a[7] & a[6]) | (a[3] & a[6] & (~a[7]) & a[8]) | (a[0] & a[7] & (~a[8]) & a[6]) | (a[7] & (~a[6])); + assign y[10] = (a[1] & (~a[3]) & (~a[4]) & a[6] & a[7]) | (a[4] & a[6] & (~a[7]) & a[8]) | (a[1] & a[6] & a[7] & (~a[8])) | (a[8] & (~a[6])); + assign y[11] = a[9]; + +endmodule diff --git a/dev/verilog/work/xu0_bprm.v b/dev/verilog/work/xu0_bprm.v new file mode 100755 index 0000000..9472e14 --- /dev/null +++ b/dev/verilog/work/xu0_bprm.v @@ -0,0 +1,79 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//***************************************************************************** +// Description: XU Bit Permute +// +//***************************************************************************** +module xu0_bprm( + a, + s, + y +); +// IOs +input [0:63] a; +input [0:7] s; +output y; +// Signals +wire [0:7] mh; +wire [0:7] ml; +wire [0:63] a1; +wire [0:63] a2; + +assign mh[0:7] = (s[0:4] == 5'b00000) ? 8'b10000000 : + (s[0:4] == 5'b00001) ? 8'b01000000 : + (s[0:4] == 5'b00010) ? 8'b00100000 : + (s[0:4] == 5'b00011) ? 8'b00010000 : + (s[0:4] == 5'b00100) ? 8'b00001000 : + (s[0:4] == 5'b00101) ? 8'b00000100 : + (s[0:4] == 5'b00110) ? 8'b00000010 : + (s[0:4] == 5'b00111) ? 8'b00000001 : + 8'b00000000 ; + +assign ml[0:7] = (s[5:7] == 3'b000) ? 8'b10000000 : + (s[5:7] == 3'b001) ? 8'b01000000 : + (s[5:7] == 3'b010) ? 8'b00100000 : + (s[5:7] == 3'b011) ? 8'b00010000 : + (s[5:7] == 3'b100) ? 8'b00001000 : + (s[5:7] == 3'b101) ? 8'b00000100 : + (s[5:7] == 3'b110) ? 8'b00000010 : + 8'b00000001; + +genvar i; +generate for (i=0; i<=7; i=i+1) + begin : msk + assign a1[8*i:8*i+7] = a[8*i:8*i+7] & ml[0:7]; + assign a2[8*i:8*i+7] = a1[8*i:8*i+7] & {8{mh[i]}}; + end +endgenerate + +assign y = |a2; + +endmodule diff --git a/dev/verilog/work/xu0_br.v b/dev/verilog/work/xu0_br.v new file mode 100755 index 0000000..35f529e --- /dev/null +++ b/dev/verilog/work/xu0_br.v @@ -0,0 +1,2843 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//******************************************************************** +//* +//* TITLE: Branch Unit +//* +//* NAME: xu0_br.vhdl +//* +//********************************************************************* +`include "tri_a2o.vh" + + +module xu0_br( + vdd, + gnd, + nclk, + pc_br_func_sl_thold_2, + pc_br_sg_2, + clkoff_b, + act_dis, + tc_ac_ccflush_dc, + d_mode, + delay_lclkr, + mpw1_b, + mpw2_b, + scan_in, + scan_out, + rv_br_vld, + rv_br_ex0_fusion, + rv_br_ex0_instr, + rv_br_ex0_ifar, + rv_br_ex0_itag, + rv_br_ex0_t2_p, + rv_br_ex0_t3_p, + rv_br_ex0_bta_val, + rv_br_ex0_pred_bta, + rv_br_ex0_pred, + rv_br_ex0_ls_ptr, + rv_br_ex0_gshare, + rv_br_ex0_bh_update, + rv_br_ex0_spec_flush, + rv_br_ex1_spec_flush, + bp_br_ex2_abort, + dec_br_ex0_act, + byp_br_ex2_cr1, + byp_br_ex2_cr2, + byp_br_ex2_cr3, + byp_br_ex2_lr1, + byp_br_ex2_lr2, + byp_br_ex2_ctr, + mux_br_ex3_cr, + br_lr_we, + br_lr_wd, + br_ctr_we, + br_ctr_wd, + br_cr_we, + br_cr_wd, + br_iu_execute_vld, + br_iu_itag, + br_iu_taken, + br_iu_bta, + br_iu_ls_ptr, + br_iu_ls_data, + br_iu_ls_update, + br_iu_gshare, + br_iu_perf_events, + br_iu_redirect, + perf_event_en, + spr_xesr2, + spr_msr_cm, + br_dec_ex3_execute_vld, + iu_br_t0_flush_ifar, +`ifndef THREADS1 + iu_br_t1_flush_ifar, +`endif + iu_br_flush +); +// parameter `EXPAND_TYPE = 2; +// parameter `THREADS = 2; +// parameter `EFF_IFAR_ARCH = 62; +// parameter `EFF_IFAR_WIDTH = 20; +// parameter `GPR_WIDTH = 64; +// parameter `ITAG_SIZE_ENC = 7; +// parameter `GPR_POOL_ENC = 6; +// parameter `CTR_POOL_ENC = 3; +// parameter `CR_POOL_ENC = 5; +// parameter `LR_POOL_ENC = 3; + // pervasive + inout vdd; + inout gnd; + input [0:`NCLK_WIDTH-1] nclk; + input pc_br_func_sl_thold_2; + input pc_br_sg_2; + input clkoff_b; + input act_dis; + input tc_ac_ccflush_dc; + input d_mode; + input delay_lclkr; + input mpw1_b; + input mpw2_b; + input scan_in; + output scan_out; + + input [0:`THREADS-1] rv_br_vld; + input rv_br_ex0_fusion; + input [0:31] rv_br_ex0_instr; + input [62-`EFF_IFAR_WIDTH:61] rv_br_ex0_ifar; + input [0:`ITAG_SIZE_ENC-1] rv_br_ex0_itag; + input [0:`GPR_POOL_ENC-1] rv_br_ex0_t2_p; + input [0:`GPR_POOL_ENC-1] rv_br_ex0_t3_p; + input rv_br_ex0_bta_val; + input [62-`EFF_IFAR_WIDTH:61] rv_br_ex0_pred_bta; + input rv_br_ex0_pred; + input [0:2] rv_br_ex0_ls_ptr; + input [0:17] rv_br_ex0_gshare; + input rv_br_ex0_bh_update; + input [0:`THREADS-1] rv_br_ex0_spec_flush; + input [0:`THREADS-1] rv_br_ex1_spec_flush; + input bp_br_ex2_abort; + + input dec_br_ex0_act; + input [0:3] byp_br_ex2_cr1; + input [0:3] byp_br_ex2_cr2; + input [0:3] byp_br_ex2_cr3; + input [64-`GPR_WIDTH:63] byp_br_ex2_lr1; + input [64-`GPR_WIDTH:63] byp_br_ex2_lr2; + input [64-`GPR_WIDTH:63] byp_br_ex2_ctr; + input [0:3] mux_br_ex3_cr; + + output br_lr_we; + output [64-`GPR_WIDTH:63] br_lr_wd; + output br_ctr_we; + output [64-`GPR_WIDTH:63] br_ctr_wd; + output br_cr_we; + output [0:3] br_cr_wd; + + output [0:`THREADS-1] br_iu_execute_vld; + output [0:`ITAG_SIZE_ENC-1] br_iu_itag; + output br_iu_taken; + output [62-`EFF_IFAR_ARCH:61] br_iu_bta; + output [0:2] br_iu_ls_ptr; + output [62-`EFF_IFAR_WIDTH:61] br_iu_ls_data; + output br_iu_ls_update; + output [0:17] br_iu_gshare; + output [0:3] br_iu_perf_events; + + //early branch flush support + output [0:`THREADS-1] br_iu_redirect; + + input [0:`THREADS-1] perf_event_en; + input [0:31] spr_xesr2; + + input [0:`THREADS-1] spr_msr_cm; + + output [0:`THREADS-1] br_dec_ex3_execute_vld; + + input [0:`THREADS-1] iu_br_flush; + + input [62-`EFF_IFAR_ARCH : 61-`EFF_IFAR_WIDTH] iu_br_t0_flush_ifar; +`ifndef THREADS1 + input [62-`EFF_IFAR_ARCH : 61-`EFF_IFAR_WIDTH] iu_br_t1_flush_ifar; +`endif + + wire tiup; + wire tidn; + + wire [0:3] ex3_cr1; + wire [0:3] ex3_cr2; + wire [0:3] ex3_cr3_branch; + wire [0:3] ex3_cr3_logical; + wire [64-`GPR_WIDTH:63] ex3_ctr; + wire [64-`GPR_WIDTH:63] ex3_lr; + + wire [0:3] ex3_cr1_d; + wire [0:3] ex3_cr2_d; + wire [0:3] ex3_cr3_d; + wire [64-`GPR_WIDTH:63] ex3_ctr_d; + wire [64-`GPR_WIDTH:63] ex3_lr1_d; + wire [64-`GPR_WIDTH:63] ex3_lr2_d; + + wire [0:3] ex3_cr1_q; + wire [0:3] ex3_cr2_q; + wire [0:3] ex3_cr3_q; + wire [64-`GPR_WIDTH:63] ex3_ctr_q; + wire [64-`GPR_WIDTH:63] ex3_lr1_q; + wire [64-`GPR_WIDTH:63] ex3_lr2_q; + + wire [0:`THREADS-1] ex0_vld_d; // input=>rv_br_vld ,act=>tiup + wire [0:`THREADS-1] ex0_vld_q; // input=>rv_br_vld ,act=>tiup + + wire ex1_act; + wire [0:`THREADS-1] ex1_vld_d; + wire [0:`THREADS-1] ex1_vld_q; + wire ex1_fusion_d; + wire ex1_fusion_q; + wire [0:31] ex1_instr_d; + wire [0:31] ex1_instr_q; + wire [62-`EFF_IFAR_WIDTH:61] ex1_ifar_d; + wire [62-`EFF_IFAR_WIDTH:61] ex1_ifar_q; + wire [0:`ITAG_SIZE_ENC-1] ex1_itag_d; + wire [0:`ITAG_SIZE_ENC-1] ex1_itag_q; + wire [0:`LR_POOL_ENC-1] ex1_lr_wa_d; + wire [0:`LR_POOL_ENC-1] ex1_lr_wa_q; + wire [0:`CTR_POOL_ENC-1] ex1_ctr_wa_d; + wire [0:`CTR_POOL_ENC-1] ex1_ctr_wa_q; + wire [0:`CR_POOL_ENC-1] ex1_cr_wa_d; + wire [0:`CR_POOL_ENC-1] ex1_cr_wa_q; + + wire ex2_act; + wire [0:`THREADS-1] ex2_vld_d; + wire [0:`THREADS-1] ex2_vld_q; + wire ex2_slow_d; + wire ex2_slow_q; + wire ex2_fusion_d; + wire ex2_fusion_q; + wire [0:31] ex2_instr_d; + wire [0:31] ex2_instr_q; + wire [62-`EFF_IFAR_WIDTH:61] ex2_ifar_d; + wire [62-`EFF_IFAR_WIDTH:61] ex2_ifar_q; + wire [0:`ITAG_SIZE_ENC-1] ex2_itag_d; + wire [0:`ITAG_SIZE_ENC-1] ex2_itag_q; + wire [0:`LR_POOL_ENC-1] ex2_lr_wa_d; + wire [0:`LR_POOL_ENC-1] ex2_lr_wa_q; + wire [0:`CTR_POOL_ENC-1] ex2_ctr_wa_d; + wire [0:`CTR_POOL_ENC-1] ex2_ctr_wa_q; + wire [0:`CR_POOL_ENC-1] ex2_cr_wa_d; + wire [0:`CR_POOL_ENC-1] ex2_cr_wa_q; + + wire ex3_act; + wire [0:`THREADS-1] ex3_vld_d; + wire [0:`THREADS-1] ex3_vld_q; + wire ex3_slow_d; + wire ex3_slow_q; + wire ex3_fusion_d; + wire ex3_fusion_q; + wire [6:31] ex3_instr_d; + wire [6:31] ex3_instr_q; + wire [62-`EFF_IFAR_WIDTH:61] ex3_ifar_d; + wire [62-`EFF_IFAR_WIDTH:61] ex3_ifar_q; + wire [0:`ITAG_SIZE_ENC-1] ex3_itag_d; + wire [0:`ITAG_SIZE_ENC-1] ex3_itag_q; + wire [0:`LR_POOL_ENC-1] ex3_lr_wa_d; + wire [0:`LR_POOL_ENC-1] ex3_lr_wa_q; + wire [0:`CTR_POOL_ENC-1] ex3_ctr_wa_d; + wire [0:`CTR_POOL_ENC-1] ex3_ctr_wa_q; + wire [0:`CR_POOL_ENC-1] ex3_cr_wa_d; + wire [0:`CR_POOL_ENC-1] ex3_cr_wa_q; + wire ex3_is_b_d; + wire ex3_is_b_q; + wire ex3_is_bc_d; + wire ex3_is_bc_q; + wire ex3_is_bclr_d; + wire ex3_is_bclr_q; + wire ex3_is_bcctr_d; + wire ex3_is_bcctr_q; + wire ex3_is_bctar_d; + wire ex3_is_bctar_q; + wire ex3_is_mcrf_d; + wire ex3_is_mcrf_q; + wire ex3_is_crand_d; + wire ex3_is_crand_q; + wire ex3_is_crandc_d; + wire ex3_is_crandc_q; + wire ex3_is_creqv_d; + wire ex3_is_creqv_q; + wire ex3_is_crnand_d; + wire ex3_is_crnand_q; + wire ex3_is_crnor_d; + wire ex3_is_crnor_q; + wire ex3_is_cror_d; + wire ex3_is_cror_q; + wire ex3_is_crorc_d; + wire ex3_is_crorc_q; + wire ex3_is_crxor_d; + wire ex3_is_crxor_q; + wire [62-`EFF_IFAR_ARCH : 61-`EFF_IFAR_WIDTH] br_upper_ifar_d[0:`THREADS-1]; + wire [62-`EFF_IFAR_ARCH : 61-`EFF_IFAR_WIDTH] br_upper_ifar_q[0:`THREADS-1]; + wire [62-`EFF_IFAR_ARCH : 61-`EFF_IFAR_WIDTH] br_upper_ifar_mux[0:`THREADS-1]; + + wire ex4_act; + wire [0:`THREADS-1] ex4_vld_d; + wire [0:`THREADS-1] ex4_vld_q; + wire ex4_slow_d; + wire ex4_slow_q; + wire [0:`ITAG_SIZE_ENC-1] ex4_itag_d; + wire [0:`ITAG_SIZE_ENC-1] ex4_itag_q; + wire [0:`LR_POOL_ENC-1] ex4_lr_wa_d; + wire [0:`LR_POOL_ENC-1] ex4_lr_wa_q; + wire [0:`CTR_POOL_ENC-1] ex4_ctr_wa_d; + wire [0:`CTR_POOL_ENC-1] ex4_ctr_wa_q; + wire [0:`CR_POOL_ENC-1] ex4_cr_wa_d; + wire [0:`CR_POOL_ENC-1] ex4_cr_wa_q; + wire ex4_taken_d; + wire ex4_taken_q; + wire [62-`EFF_IFAR_ARCH:61] ex4_bta_d; + wire [62-`EFF_IFAR_ARCH:61] ex4_bta_q; + wire ex4_lr_we_d; + wire ex4_lr_we_q; + wire [64-`GPR_WIDTH:63] ex4_lr_wd_d; + wire [64-`GPR_WIDTH:63] ex4_lr_wd_q; + wire ex4_ctr_we_d; + wire ex4_ctr_we_q; + wire [64-`GPR_WIDTH:63] ex4_ctr_wd_d; + wire [64-`GPR_WIDTH:63] ex4_ctr_wd_q; + wire ex4_cr_we_d; + wire ex4_cr_we_q; + wire [0:3] ex4_cr_wd_d; + wire [0:3] ex4_cr_wd_q; + wire [0:`THREADS-1] spr_msr_cm_q; + + wire [0:4] ex3_bo; + wire [0:4] ex3_bi; + wire [62-`EFF_IFAR_ARCH:61] ex3_bd; + wire ex3_aa; + wire ex3_lk; + wire [0:1] ex3_bh; + wire ex3_getNIA; + + wire [62-`EFF_IFAR_ARCH:61] ex2_bd; + wire [62-`EFF_IFAR_ARCH:61] ex2_li; + wire ex2_aa; + + wire ex3_ctr_one; + wire ex3_ctr_one_b; + wire ex3_cr_bit; + wire ex3_br_taken; + + wire [62-`EFF_IFAR_ARCH:61] ex3_bta; + wire [62-`EFF_IFAR_ARCH:61] ex3_nia; + + wire [62-`EFF_IFAR_ARCH:61] ex2_abs; + wire [62-`EFF_IFAR_ARCH:61] ex2_ifar; + wire [62-`EFF_IFAR_ARCH:61] ex2_off; + wire [62-`EFF_IFAR_ARCH:61] ex2_bta; + wire [62-`EFF_IFAR_ARCH:61] ex2_nia; + wire [62-`EFF_IFAR_ARCH:61] ex2_nia_pre; + wire [62-`EFF_IFAR_ARCH:61] ex3_bta_pre; + wire [62-`EFF_IFAR_ARCH:61] ex3_bta_d; + wire [62-`EFF_IFAR_ARCH:61] ex3_bta_q; + wire [62-`EFF_IFAR_ARCH:61] ex3_nia_d; + wire [62-`EFF_IFAR_ARCH:61] ex3_nia_q; + + wire [0:4] ex3_bt; + wire [0:4] ex3_ba; + wire [0:4] ex3_bb; + + wire ex3_cra; + wire ex3_crb; + wire ex3_crt; + + wire ex3_crand; + wire ex3_crandc; + wire ex3_creqv; + wire ex3_crnand; + wire ex3_crnor; + wire ex3_cror; + wire ex3_crorc; + wire ex3_crxor; + + wire ex1_pred_d; + wire ex1_pred_q; + wire ex1_bta_val_d; + wire ex1_bta_val_q; + wire [62-`EFF_IFAR_WIDTH:61] ex1_pred_bta_d; + wire [62-`EFF_IFAR_WIDTH:61] ex1_pred_bta_q; + wire ex2_pred_d; + wire ex2_pred_q; + wire ex2_bta_val_d; + wire ex2_bta_val_q; + wire [62-`EFF_IFAR_WIDTH:61] ex2_pred_bta_d; + wire [62-`EFF_IFAR_WIDTH:61] ex2_pred_bta_q; + wire ex3_pred_d; + wire ex3_pred_q; + wire ex3_bta_val_d; + wire ex3_bta_val_q; + wire [62-`EFF_IFAR_WIDTH:61] ex3_pred_bta_d; + wire [62-`EFF_IFAR_WIDTH:61] ex3_pred_bta_q; + wire [0:`THREADS-1] ex4_redirect_d; + wire [0:`THREADS-1] ex4_redirect_q; + + wire ex3_ls_push; + wire ex3_ls_pop; + wire ex3_ls_unpop; + wire ex3_gshare_shift; + + wire [0:17] ex1_gshare_d; + wire [0:17] ex1_gshare_q; + wire [0:17] ex2_gshare_d; + wire [0:17] ex2_gshare_q; + wire [0:17] ex3_gshare_d; + wire [0:17] ex3_gshare_q; + wire [0:17] ex4_gshare_d; + wire [0:17] ex4_gshare_q; + wire ex1_bh_update_d; + wire ex1_bh_update_q; + wire ex2_bh_update_d; + wire ex2_bh_update_q; + wire ex3_bh_update_d; + wire ex3_bh_update_q; + + wire [0:2] ex1_ls_ptr_d; + wire [0:2] ex1_ls_ptr_q; + wire [0:2] ex2_ls_ptr_d; + wire [0:2] ex2_ls_ptr_q; + wire [0:2] ex3_ls_ptr_d; + wire [0:2] ex3_ls_ptr_q; + wire [0:2] ex4_ls_ptr_d; + wire [0:2] ex4_ls_ptr_q; + wire [62-`EFF_IFAR_WIDTH:61] ex4_ls_data_d; + wire [62-`EFF_IFAR_WIDTH:61] ex4_ls_data_q; + wire ex4_ls_update_d; + wire ex4_ls_update_q; + + wire [0:`THREADS-1] ex3_itag_priority; + wire [0:`ITAG_SIZE_ENC-1] ex4_itag_saved_d[0:`THREADS-1]; + wire [0:`ITAG_SIZE_ENC-1] ex4_itag_saved_q[0:`THREADS-1]; + wire [0:`THREADS-1] ex4_itag_saved_val_d; + wire [0:`THREADS-1] ex4_itag_saved_val_q; + + wire [0:`THREADS-1] iu_br_flush_d; + wire [0:`THREADS-1] iu_br_flush_q; + wire [62-`EFF_IFAR_ARCH : 61-`EFF_IFAR_WIDTH] iu_br_flush_ifar_d[0:`THREADS-1]; + wire [62-`EFF_IFAR_ARCH : 61-`EFF_IFAR_WIDTH] iu_br_flush_ifar_q[0:`THREADS-1]; + + wire [0:`THREADS-1] ex0_vld; + + wire [0:3] ex4_perf_event_d; // wired OR + wire [0:3] ex4_perf_event_q; + + // scan chains + + parameter ex0_vld_offset = 0; + parameter iu_br_flush_offset = ex0_vld_offset + `THREADS; + parameter iu_br_flush_ifar_offset = iu_br_flush_offset + `THREADS; + parameter ex4_itag_saved_offset = iu_br_flush_ifar_offset + `THREADS * (`EFF_IFAR_ARCH-`EFF_IFAR_WIDTH); + parameter ex4_itag_saved_val_offset = ex4_itag_saved_offset + `THREADS * `ITAG_SIZE_ENC; + parameter ex3_cr1_offset = ex4_itag_saved_val_offset + `THREADS; + parameter ex3_cr2_offset = ex3_cr1_offset + 4; + parameter ex3_cr3_offset = ex3_cr2_offset + 4; + parameter ex3_ctr_offset = ex3_cr3_offset + 4; + parameter ex3_lr1_offset = ex3_ctr_offset + (-1+`GPR_WIDTH+1); + parameter ex3_lr2_offset = ex3_lr1_offset + (-1+`GPR_WIDTH+1); + parameter ex1_vld_offset = ex3_lr2_offset + (-1+`GPR_WIDTH+1); + parameter ex1_fusion_offset = ex1_vld_offset + `THREADS; + parameter ex1_instr_offset = ex1_fusion_offset + 1; + parameter ex1_ifar_offset = ex1_instr_offset + 32; + parameter ex1_itag_offset = ex1_ifar_offset + (-1+`EFF_IFAR_WIDTH+1); + parameter ex1_lr_wa_offset = ex1_itag_offset + `ITAG_SIZE_ENC; + parameter ex1_cr_wa_offset = ex1_lr_wa_offset + `LR_POOL_ENC; + parameter ex1_ctr_wa_offset = ex1_cr_wa_offset + `CR_POOL_ENC; + parameter ex1_pred_offset = ex1_ctr_wa_offset + `CTR_POOL_ENC; + parameter ex1_bta_val_offset = ex1_pred_offset + 1; + parameter ex1_pred_bta_offset = ex1_bta_val_offset + 1; + parameter ex1_bh_update_offset = ex1_pred_bta_offset + (-1+`EFF_IFAR_WIDTH+1); + parameter ex1_gshare_offset = ex1_bh_update_offset + 1; + parameter ex1_ls_ptr_offset = ex1_gshare_offset + 18; + parameter ex2_vld_offset = ex1_ls_ptr_offset + 3; + parameter ex2_slow_offset = ex2_vld_offset + `THREADS; + parameter ex2_fusion_offset = ex2_slow_offset + 1; + parameter ex2_instr_offset = ex2_fusion_offset + 1; + parameter ex2_ifar_offset = ex2_instr_offset + 32; + parameter ex2_itag_offset = ex2_ifar_offset + (-1+`EFF_IFAR_WIDTH+1); + parameter ex2_lr_wa_offset = ex2_itag_offset + `ITAG_SIZE_ENC; + parameter ex2_cr_wa_offset = ex2_lr_wa_offset + `LR_POOL_ENC; + parameter ex2_ctr_wa_offset = ex2_cr_wa_offset + `CR_POOL_ENC; + parameter ex2_pred_offset = ex2_ctr_wa_offset + `CTR_POOL_ENC; + parameter ex2_bta_val_offset = ex2_pred_offset + 1; + parameter ex2_pred_bta_offset = ex2_bta_val_offset + 1; + parameter ex2_bh_update_offset = ex2_pred_bta_offset + (-1+`EFF_IFAR_WIDTH+1); + parameter ex2_gshare_offset = ex2_bh_update_offset + 1; + parameter ex2_ls_ptr_offset = ex2_gshare_offset + 18; + parameter ex3_vld_offset = ex2_ls_ptr_offset + 3; + parameter ex3_slow_offset = ex3_vld_offset + `THREADS; + parameter ex3_fusion_offset = ex3_slow_offset + 1; + parameter ex3_instr_offset = ex3_fusion_offset + 1; + parameter ex3_ifar_offset = ex3_instr_offset + 26; + parameter ex3_bta_offset = ex3_ifar_offset + (-1+`EFF_IFAR_WIDTH+1); + parameter ex3_nia_offset = ex3_bta_offset + (-1+`EFF_IFAR_ARCH+1); + parameter ex3_itag_offset = ex3_nia_offset + (-1+`EFF_IFAR_ARCH+1); + parameter ex3_lr_wa_offset = ex3_itag_offset + `ITAG_SIZE_ENC; + parameter ex3_cr_wa_offset = ex3_lr_wa_offset + `LR_POOL_ENC; + parameter ex3_ctr_wa_offset = ex3_cr_wa_offset + `CR_POOL_ENC; + parameter ex3_pred_offset = ex3_ctr_wa_offset + `CTR_POOL_ENC; + parameter ex3_bta_val_offset = ex3_pred_offset + 1; + parameter ex3_pred_bta_offset = ex3_bta_val_offset + 1; + parameter ex3_bh_update_offset = ex3_pred_bta_offset + (-1+`EFF_IFAR_WIDTH+1); + parameter ex3_gshare_offset = ex3_bh_update_offset + 1; + parameter ex3_ls_ptr_offset = ex3_gshare_offset + 18; + parameter ex3_is_b_offset = ex3_ls_ptr_offset + 3; + parameter ex3_is_bc_offset = ex3_is_b_offset + 1; + parameter ex3_is_bclr_offset = ex3_is_bc_offset + 1; + parameter ex3_is_bcctr_offset = ex3_is_bclr_offset + 1; + parameter ex3_is_bctar_offset = ex3_is_bcctr_offset + 1; + parameter ex3_is_mcrf_offset = ex3_is_bctar_offset + 1; + parameter ex3_is_crand_offset = ex3_is_mcrf_offset + 1; + parameter ex3_is_crandc_offset = ex3_is_crand_offset + 1; + parameter ex3_is_creqv_offset = ex3_is_crandc_offset + 1; + parameter ex3_is_crnand_offset = ex3_is_creqv_offset + 1; + parameter ex3_is_crnor_offset = ex3_is_crnand_offset + 1; + parameter ex3_is_cror_offset = ex3_is_crnor_offset + 1; + parameter ex3_is_crorc_offset = ex3_is_cror_offset + 1; + parameter ex3_is_crxor_offset = ex3_is_crorc_offset + 1; + parameter br_upper_ifar_offset = ex3_is_crxor_offset + 1; + parameter ex4_vld_offset = br_upper_ifar_offset + `THREADS * (`EFF_IFAR_ARCH-`EFF_IFAR_WIDTH); + parameter ex4_slow_offset = ex4_vld_offset + `THREADS; + parameter ex4_itag_offset = ex4_slow_offset + 1; + parameter ex4_lr_wa_offset = ex4_itag_offset + `ITAG_SIZE_ENC; + parameter ex4_cr_wa_offset = ex4_lr_wa_offset + `LR_POOL_ENC; + parameter ex4_ctr_wa_offset = ex4_cr_wa_offset + `CR_POOL_ENC; + parameter ex4_taken_offset = ex4_ctr_wa_offset + `CTR_POOL_ENC; + parameter ex4_bta_offset = ex4_taken_offset + 1; + parameter ex4_gshare_offset = ex4_bta_offset + (-1+`EFF_IFAR_ARCH+1); + parameter ex4_ls_ptr_offset = ex4_gshare_offset + 18; + parameter ex4_ls_data_offset = ex4_ls_ptr_offset + 3; + parameter ex4_ls_update_offset = ex4_ls_data_offset + (-1+`EFF_IFAR_WIDTH+1); + parameter ex4_redirect_offset = ex4_ls_update_offset + 1; + parameter ex4_lr_we_offset = ex4_redirect_offset + `THREADS; + parameter ex4_lr_wd_offset = ex4_lr_we_offset + 1; + parameter ex4_cr_we_offset = ex4_lr_wd_offset + (-1+`GPR_WIDTH+1); + parameter ex4_cr_wd_offset = ex4_cr_we_offset + 1; + parameter ex4_perf_event_offset = ex4_cr_wd_offset + 4; + parameter spr_msr_cm_offset = ex4_perf_event_offset + 4; + parameter ex4_ctr_we_offset = spr_msr_cm_offset + `THREADS; + parameter ex4_ctr_wd_offset = ex4_ctr_we_offset + 1; + parameter scan_right = ex4_ctr_wd_offset + (-1+`GPR_WIDTH+1); + + wire [0:scan_right-1] siv; + wire [0:scan_right-1] sov; + + wire func_sl_thold_1; + wire func_sl_thold_0; + wire func_sl_thold_0_b; + wire sg_1; + wire sg_0; + wire force_t; + + //!! Bugspray Include: xu0_br; + wire d_mode_dc, mpw1_dc_b, mpw2_dc_b, delay_lclkr_dc; + assign d_mode_dc = 0; + assign mpw1_dc_b = 0; + assign mpw2_dc_b = 0; + assign delay_lclkr_dc = 0; + + assign tiup = 1'b1; + assign tidn = 1'b0; + + assign iu_br_flush_d = iu_br_flush; + assign iu_br_flush_ifar_d[0] = iu_br_t0_flush_ifar; +`ifndef THREADS1 + assign iu_br_flush_ifar_d[1] = iu_br_t1_flush_ifar; +`endif + + assign ex0_vld_d = rv_br_vld & (~iu_br_flush_q); + + // Kill valid and act's for non branch ops +assign ex0_vld = (dec_br_ex0_act ? ex0_vld_q : `THREADS'b0 ); + +assign ex1_vld_d = (rv_br_ex0_fusion | |(ex1_vld_q) ? ex0_vld & (~iu_br_flush_q) & (~rv_br_ex0_spec_flush) : `THREADS'b0 ); + assign ex1_act = |(ex0_vld & (~iu_br_flush_q)); + assign ex1_fusion_d = rv_br_ex0_fusion; + assign ex1_instr_d = rv_br_ex0_instr; + assign ex1_ifar_d = rv_br_ex0_ifar; + assign ex1_itag_d = rv_br_ex0_itag; + assign ex1_lr_wa_d = rv_br_ex0_t3_p[`GPR_POOL_ENC - `LR_POOL_ENC:`GPR_POOL_ENC - 1]; + assign ex1_ctr_wa_d = rv_br_ex0_t2_p[`GPR_POOL_ENC - `CTR_POOL_ENC:`GPR_POOL_ENC - 1]; + assign ex1_cr_wa_d = rv_br_ex0_t3_p[`GPR_POOL_ENC - `CR_POOL_ENC:`GPR_POOL_ENC - 1]; + assign ex1_pred_d = rv_br_ex0_pred; + assign ex1_bta_val_d = rv_br_ex0_bta_val; + assign ex1_pred_bta_d = rv_br_ex0_pred_bta; + assign ex1_ls_ptr_d = rv_br_ex0_ls_ptr; + assign ex1_bh_update_d = rv_br_ex0_bh_update; + assign ex1_gshare_d = rv_br_ex0_gshare; + + assign ex2_vld_d = (|(ex1_vld_q) == 1'b1) ? ex1_vld_q & (~iu_br_flush_q) & (~rv_br_ex1_spec_flush) : + (rv_br_ex0_fusion == 1'b0) ? ex0_vld & (~iu_br_flush_q) & (~rv_br_ex0_spec_flush) : + `THREADS'b0; + assign ex2_act = |((ex0_vld | ex1_vld_q) & (~iu_br_flush_q)); + assign ex2_slow_d = (|(ex1_vld_q) == 1'b1) ? 1'b1 : + 1'b0; + assign ex2_fusion_d = (|(ex1_vld_q) == 1'b1) ? ex1_fusion_q : + rv_br_ex0_fusion; + assign ex2_instr_d = (|(ex1_vld_q) == 1'b1) ? ex1_instr_q : + rv_br_ex0_instr; + assign ex2_ifar_d = (|(ex1_vld_q) == 1'b1) ? ex1_ifar_q : + rv_br_ex0_ifar; + assign ex2_itag_d = (|(ex1_vld_q) == 1'b1) ? ex1_itag_q : + rv_br_ex0_itag; + assign ex2_lr_wa_d = (|(ex1_vld_q) == 1'b1) ? ex1_lr_wa_q : + rv_br_ex0_t3_p[`GPR_POOL_ENC - `LR_POOL_ENC:`GPR_POOL_ENC - 1]; + assign ex2_ctr_wa_d = (|(ex1_vld_q) == 1'b1) ? ex1_ctr_wa_q : + rv_br_ex0_t2_p[`GPR_POOL_ENC - `CTR_POOL_ENC:`GPR_POOL_ENC - 1]; + assign ex2_cr_wa_d = (|(ex1_vld_q) == 1'b1) ? ex1_cr_wa_q : + rv_br_ex0_t3_p[`GPR_POOL_ENC - `CR_POOL_ENC:`GPR_POOL_ENC - 1]; + assign ex2_pred_d = (|(ex1_vld_q) == 1'b1) ? ex1_pred_q : + rv_br_ex0_pred; + assign ex2_bta_val_d = (|(ex1_vld_q) == 1'b1) ? ex1_bta_val_q : + rv_br_ex0_bta_val; + assign ex2_pred_bta_d = (|(ex1_vld_q) == 1'b1) ? ex1_pred_bta_q : + rv_br_ex0_pred_bta; + assign ex2_ls_ptr_d = (|(ex1_vld_q) == 1'b1) ? ex1_ls_ptr_q : + rv_br_ex0_ls_ptr; + assign ex2_bh_update_d = (|(ex1_vld_q) == 1'b1) ? ex1_bh_update_q : + rv_br_ex0_bh_update; + assign ex2_gshare_d = (|(ex1_vld_q) == 1'b1) ? ex1_gshare_q : + rv_br_ex0_gshare; + + assign ex3_vld_d = (ex2_slow_q == 1'b1) ? ex2_vld_q & (~iu_br_flush_q) & {`THREADS{(~bp_br_ex2_abort)}}: + ex2_vld_q & (~iu_br_flush_q) & (~rv_br_ex1_spec_flush); + assign ex3_act = |(ex2_vld_q & (~iu_br_flush_q)); + assign ex3_slow_d = ex2_slow_q; + assign ex3_fusion_d = ex2_fusion_q; + assign ex3_instr_d[6:31] = ex2_instr_q[6:31]; + assign ex3_ifar_d = ex2_ifar_q; + assign ex3_itag_d = ex2_itag_q; + assign ex3_lr_wa_d = ex2_lr_wa_q; + assign ex3_ctr_wa_d = ex2_ctr_wa_q; + assign ex3_cr_wa_d = ex2_cr_wa_q; + assign ex3_pred_d = ex2_pred_q; + assign ex3_bta_val_d = ex2_bta_val_q; + assign ex3_pred_bta_d = ex2_pred_bta_q; + assign ex3_ls_ptr_d = ex2_ls_ptr_q; + assign ex3_bh_update_d = ex2_bh_update_q; + assign ex3_gshare_d = ex2_gshare_q; + + assign ex4_vld_d = (ex3_slow_q & (ex3_is_b_q | ex3_is_bc_q | ex3_is_bclr_q | ex3_is_bcctr_q | ex3_is_bctar_q | ex3_is_crand_q | ex3_is_crandc_q | ex3_is_creqv_q | ex3_is_crnand_q | ex3_is_crnor_q | ex3_is_cror_q | ex3_is_crorc_q | ex3_is_crxor_q | ex3_is_mcrf_q) ? ex3_vld_q & (~iu_br_flush_q) : + (ex3_is_b_q | ex3_is_bc_q | ex3_is_bclr_q | ex3_is_bcctr_q | ex3_is_bctar_q | ex3_is_crand_q | ex3_is_crandc_q | ex3_is_creqv_q | ex3_is_crnand_q | ex3_is_crnor_q | ex3_is_cror_q | ex3_is_crorc_q | ex3_is_crxor_q | ex3_is_mcrf_q) ? ex3_vld_q & (~iu_br_flush_q) & {`THREADS{(~bp_br_ex2_abort)}} : + `THREADS'b0 ); + + assign ex4_act = |(ex4_vld_d); + assign ex4_slow_d = ex3_slow_q; + assign ex4_itag_d = ex3_itag_q; + assign ex4_lr_wa_d = ex3_lr_wa_q; + assign ex4_ctr_wa_d = ex3_ctr_wa_q; + assign ex4_cr_wa_d = ex3_cr_wa_q; + + assign br_iu_execute_vld = ex4_vld_q; + assign br_iu_itag = ex4_itag_q; + assign br_iu_taken = ex4_taken_q; + assign br_iu_bta = ex4_bta_q; + assign br_iu_redirect = ex4_redirect_q; + + assign br_iu_gshare = ex4_gshare_q; + assign br_iu_ls_ptr = ex4_ls_ptr_q; + assign br_iu_ls_data = ex4_ls_data_q; + assign br_iu_ls_update = ex4_ls_update_q; + + assign br_lr_we = (ex3_slow_q == 1'b1) ? ex4_lr_we_d : + (ex4_slow_q == 1'b0) ? ex4_lr_we_q : + 1'b0; + assign br_lr_wd = (ex3_slow_q == 1'b1) ? ex4_lr_wd_d : + ex4_lr_wd_q; + assign br_ctr_we = (ex3_slow_q == 1'b1) ? ex4_ctr_we_d : + (ex4_slow_q == 1'b0) ? ex4_ctr_we_q : + 1'b0; + assign br_ctr_wd = (ex3_slow_q == 1'b1) ? ex4_ctr_wd_d : + ex4_ctr_wd_q; + assign br_cr_we = (ex3_slow_q == 1'b1) ? ex4_cr_we_d : + (ex4_slow_q == 1'b0) ? ex4_cr_we_q : + 1'b0; + assign br_cr_wd = (ex3_slow_q == 1'b1) ? ex4_cr_wd_d : + ex4_cr_wd_q; + + assign br_dec_ex3_execute_vld = (ex3_slow_q == 1'b1) ? ex4_vld_d : + (ex4_slow_q == 1'b0) ? ex4_vld_q : + `THREADS'b0; + //----------------------------------------------- + // SPR bypass + //----------------------------------------------- + + assign ex3_cr1_d = byp_br_ex2_cr1; + assign ex3_cr2_d = byp_br_ex2_cr2; + assign ex3_cr3_d = byp_br_ex2_cr3; + assign ex3_ctr_d = byp_br_ex2_ctr; + assign ex3_lr1_d = byp_br_ex2_lr1; + assign ex3_lr2_d = byp_br_ex2_lr2; + + assign ex3_cr1 = (ex3_slow_q == 1'b1) ? ex3_cr1_q : + ex3_cr1_d; + assign ex3_cr2 = (ex3_slow_q == 1'b1) ? ex3_cr2_q : + ex3_cr2_d; + assign ex3_cr3_branch = (ex3_fusion_q == 1'b1) ? mux_br_ex3_cr : + (ex3_slow_q == 1'b1) ? ex3_cr3_q : + ex3_cr3_d; + assign ex3_cr3_logical = (ex3_slow_q == 1'b1) ? ex3_cr3_q : + ex3_cr3_d; + assign ex3_ctr = (ex3_slow_q == 1'b1) ? ex3_ctr_q : + ex3_ctr_d; + assign ex3_lr = (ex3_fusion_q == 1'b1) ? ex3_lr2_q : + (ex3_slow_q == 1'b1) ? ex3_lr1_q : + ex3_lr1_d; + + //----------------------------------------------- + // decode branch instruction + //----------------------------------------------- + + assign ex3_is_b_d = ex2_instr_q[0:5] == 6'b010010; // 18 + assign ex3_is_bc_d = ex2_instr_q[0:5] == 6'b010000; // 16 + assign ex3_is_bclr_d = ex2_instr_q[0:5] == 6'b010011 & ex2_instr_q[21:30] == 10'b0000010000; // 19/16 + assign ex3_is_bcctr_d = ex2_instr_q[0:5] == 6'b010011 & ex2_instr_q[21:30] == 10'b1000010000; // 19/528 + assign ex3_is_bctar_d = ex2_instr_q[0:5] == 6'b010011 & ex2_instr_q[21:30] == 10'b1000110000; // 19/560 + assign ex3_is_mcrf_d = ex2_instr_q[0:5] == 6'b010011 & ex2_instr_q[21:30] == 10'b0000000000; // 19/0 + + assign ex3_bo[0:4] = ex3_instr_q[6:10]; + assign ex3_bi[0:4] = ex3_instr_q[11:15]; + + assign ex3_bd[62-`EFF_IFAR_ARCH:47] = {`EFF_IFAR_ARCH-14{ex3_instr_q[16]}}; + assign ex3_bd[48:61] = ex3_instr_q[16:29]; + + assign ex3_aa = ex3_instr_q[30]; + assign ex3_lk = ex3_instr_q[31]; + assign ex3_bh[0:1] = ex3_instr_q[19:20]; + + assign ex3_getNIA = ex3_is_bc_q == 1'b1 & ex3_bo[0:4] == 5'b10100 & ex3_bi[0:4] == 5'b11111 & ex3_bd[62 - `EFF_IFAR_ARCH:61] == 1 & ex3_aa == 1'b0 & ex3_lk == 1'b1; + + //do addition in ex2 for timing + assign ex2_bd[62 - `EFF_IFAR_ARCH:47] = {`EFF_IFAR_ARCH-14{ex2_instr_q[16]}}; + assign ex2_bd[48:61] = ex2_instr_q[16:29]; + + assign ex2_li[62 - `EFF_IFAR_ARCH:37] = {`EFF_IFAR_ARCH-24{ex2_instr_q[6]}}; + assign ex2_li[38:61] = ex2_instr_q[6:29]; + + assign ex2_aa = ex2_instr_q[30]; + + //----------------------------------------------- + // calculate branch direction + //----------------------------------------------- + + assign ex3_ctr_one = (~|(ex3_ctr[64 - `GPR_WIDTH:62])) & ex3_ctr[63]; + assign ex3_ctr_one_b = (~ex3_ctr_one); + + assign ex3_cr_bit = (ex3_cr3_branch[0] & ex3_bi[3:4] == 2'b00) | (ex3_cr3_branch[1] & ex3_bi[3:4] == 2'b01) | (ex3_cr3_branch[2] & ex3_bi[3:4] == 2'b10) | (ex3_cr3_branch[3] & ex3_bi[3:4] == 2'b11); + + assign ex3_br_taken = (ex3_bo[2] | (ex3_ctr_one_b ^ ex3_bo[3])) & (ex3_bo[0] | (ex3_cr_bit ~^ ex3_bo[1])); + + assign ex4_taken_d = ex3_is_b_q | ((ex3_is_bc_q | ex3_is_bclr_q | ex3_is_bcctr_q | ex3_is_bctar_q) & ex3_br_taken); + + //----------------------------------------------- + // calculate branch target address + //----------------------------------------------- + + assign ex2_abs = (ex3_is_b_d == 1'b1) ? ex2_li : + ex2_bd; + + generate + begin : xhdl1 + genvar i; + for (i = 0; i <= `THREADS - 1; i = i + 1) + begin : thread_ifar + if (i == 0) + begin : i0 + assign br_upper_ifar_mux[i] = (ex2_vld_q[i] ? br_upper_ifar_q[i] : {`EFF_IFAR_ARCH-`EFF_IFAR_WIDTH{1'b0}} ); + end + + if (i > 0) + begin : i1 + assign br_upper_ifar_mux[i] = (ex2_vld_q[i] ? br_upper_ifar_q[i] : {`EFF_IFAR_ARCH-`EFF_IFAR_WIDTH{1'b0}} ) | br_upper_ifar_mux[i - 1]; + end + end + end + endgenerate + + assign ex2_ifar = {br_upper_ifar_mux[`THREADS - 1], ex2_ifar_q[62 - `EFF_IFAR_WIDTH:61]}; + + assign ex2_off = ex2_abs + ex2_ifar; + + assign ex2_bta = (ex2_aa == 1'b1) ? ex2_abs : + ex2_off; + + assign ex2_nia_pre = ex2_ifar + 1; + + generate + begin : xhdl2 + genvar i; + for (i = (62 - `EFF_IFAR_ARCH); i <= 61; i = i + 1) + begin : ex3NIAMask + if (i < 32) + begin : R0 + assign ex2_nia[i] = (|(ex2_vld_q & spr_msr_cm_q) & ex2_nia_pre[i]); + end + if (i >= 32) + begin : R1 + assign ex2_nia[i] = ex2_nia_pre[i]; + end + end +end +endgenerate + +assign ex3_bta_d = ex2_bta; +assign ex3_nia_d = ex2_nia; + +assign ex3_bta_pre = (ex3_is_bclr_q == 1'b1 ? ex3_lr[62 - `EFF_IFAR_ARCH:61] : 0 ) | (ex3_is_bcctr_q == 1'b1 ? ex3_ctr[62 - `EFF_IFAR_ARCH:61] : 0 ) | (ex3_is_bctar_q == 1'b1 ? ex3_lr[62 - `EFF_IFAR_ARCH:61] : 0 ) | (ex3_is_b_q == 1'b1 | ex3_is_bc_q == 1'b1 ? ex3_bta_q[62 - `EFF_IFAR_ARCH:61] : 0 ); + +generate + begin : xhdl3 + genvar i; + for (i = (62 - `EFF_IFAR_ARCH); i <= 61; i = i + 1) + begin : ex3BTAMask + if (i < 32) + begin : R0 + assign ex3_bta[i] = (|(ex3_vld_q & spr_msr_cm_q) & ex3_bta_pre[i]); + end + if (i >= 32) + begin : R1 + assign ex3_bta[i] = ex3_bta_pre[i]; + end +end +end +endgenerate + + assign ex4_bta_d = (ex4_taken_d == 1'b1 ? ex3_bta[62 - `EFF_IFAR_ARCH:61] : 0 ) | (ex4_taken_d == 1'b0 ? ex3_nia_q[62 - `EFF_IFAR_ARCH:61] : 0 ); + +assign ex3_nia = ex3_nia_q; + +//----------------------------------------------- +// early branch redirect +//----------------------------------------------- + +generate +begin : xhdl4 + genvar i; + for (i = 0; i <= (`THREADS - 1); i = i + 1) + begin : br_thread + + assign ex4_redirect_d[i] = ex3_itag_priority[i] & (~iu_br_flush_q[i]) & ((ex4_taken_d ^ ex3_pred_q) | (ex4_taken_d & ex3_pred_q & (ex3_bta[62 - `EFF_IFAR_ARCH:61 - `EFF_IFAR_WIDTH] != br_upper_ifar_q[i])) | (ex4_taken_d & ex3_pred_q & ex3_bta_val_q & (ex3_bta != {br_upper_ifar_q[i], ex3_pred_bta_q}))); + + assign ex3_itag_priority[i] = (ex3_vld_q[i] & ~(bp_br_ex2_abort & ~ex3_slow_q)) & ((ex3_itag_q[0] == ex4_itag_saved_q[i][0] & ex3_itag_q[1:`ITAG_SIZE_ENC - 1] < ex4_itag_saved_q[i][1:`ITAG_SIZE_ENC - 1]) | (ex3_itag_q[0] != ex4_itag_saved_q[i][0] & ex3_itag_q[1:`ITAG_SIZE_ENC - 1] > ex4_itag_saved_q[i][1:`ITAG_SIZE_ENC - 1]) | ((~ex4_itag_saved_val_q[i]))); + + assign ex4_itag_saved_d[i] = (ex4_redirect_d[i] == 1'b1) ? ex3_itag_q : + ex4_itag_saved_q[i]; + + assign ex4_itag_saved_val_d[i] = (iu_br_flush_q[i] == 1'b1) ? 1'b0 : + (ex4_redirect_d[i] == 1'b1) ? 1'b1 : + ex4_itag_saved_val_q[i]; + + assign br_upper_ifar_d[i] = iu_br_flush_ifar_q[i]; + + end +end +endgenerate + +//----------------------------------------------- +// link stack repair +//----------------------------------------------- + +assign ex3_ls_push = |(ex4_vld_d) & ex4_taken_d & (~ex3_is_bclr_q) & ex3_lk & (~ex3_getNIA); +assign ex3_ls_pop = |(ex4_vld_d) & ex4_taken_d & ex3_is_bclr_q & ex3_bh[0:1] == 2'b00; +assign ex3_ls_unpop = |(ex4_vld_d) & (~ex4_taken_d) & ex3_is_bclr_q & ex3_bh[0:1] == 2'b00; + +assign ex4_ls_ptr_d[0:2] = (ex3_ls_push == 1'b1 & ex3_ls_pop == 1'b0) ? ex3_ls_ptr_q[0:2] + 3'b001 : + (ex3_ls_push == 1'b0 & ex3_ls_pop == 1'b1) ? ex3_ls_ptr_q[0:2] - 3'b001 : + ex3_ls_ptr_q[0:2]; + +assign ex4_ls_data_d = (ex3_ls_unpop == 1'b1) ? ex3_pred_bta_q : + ex3_nia[62 - `EFF_IFAR_WIDTH:61]; + +assign ex4_ls_update_d = ex3_ls_push | ex3_ls_unpop; + +//----------------------------------------------- +// gshare repair +//----------------------------------------------- + +assign ex4_gshare_d[0:2] = (|(ex4_vld_d)) & (ex4_taken_d | (ex3_ifar_q[60:61] == 2'b11)) ? {ex4_taken_d, ex3_gshare_q[0:1]} : + ex3_gshare_q[0:2]; + +assign ex4_gshare_d[3:9] = (|(ex4_vld_d) & (ex4_taken_d | (ex3_ifar_q[60:61] == 2'b11)) & ex3_gshare_q[14:15] == 2'b11) ? ({ex3_gshare_q[2], 2'b00, ex3_gshare_q[3:6]}) : + (|(ex4_vld_d) & (ex4_taken_d | (ex3_ifar_q[60:61] == 2'b11)) & ex3_gshare_q[14:15] == 2'b10) ? ({ex3_gshare_q[2], 1'b0, ex3_gshare_q[3:7]}) : + (|(ex4_vld_d) & (ex4_taken_d | (ex3_ifar_q[60:61] == 2'b11)) & ex3_gshare_q[14:15] == 2'b01) ? ({ex3_gshare_q[2], ex3_gshare_q[3:8]}) : + (|(ex4_vld_d) & (ex4_taken_d | (ex3_ifar_q[60:61] == 2'b11)) & ex3_gshare_q[14:15] == 2'b00) ? ({ ex3_gshare_q[3:9]}) : + ex3_gshare_q[3:9]; + + +assign ex4_gshare_d[10:15] = (|(ex4_vld_d)) & (ex4_taken_d | (ex3_ifar_q[60:61] == 2'b11)) ? {ex3_gshare_q[16:17], ex3_gshare_q[10:13]} : + ex3_gshare_q[10:15]; + +assign ex4_gshare_d[16:17] = (|(ex4_vld_d)) & (ex4_taken_d | (ex3_ifar_q[60:61] == 2'b11)) ? 2'b00 : + ex3_gshare_q[16:17]; + + +//----------------------------------------------- +// update registers +//----------------------------------------------- + +assign ex4_lr_we_d = |(ex4_vld_d) & (ex3_is_b_q | ex3_is_bc_q | ex3_is_bclr_q | ex3_is_bcctr_q | ex3_is_bctar_q) & ex3_lk; +assign ex4_lr_wd_d = {ex3_nia[64 - `GPR_WIDTH:61], 2'b00}; + +assign ex4_ctr_we_d = |(ex4_vld_d) & (ex3_is_bc_q | ex3_is_bclr_q | ex3_is_bcctr_q | ex3_is_bctar_q) & (~ex3_bo[2]); +assign ex4_ctr_wd_d = ex3_ctr[64 - `GPR_WIDTH:63] - 1; + +//----------------------------------------------- +// decode logical instruction +//----------------------------------------------- + +assign ex3_is_crand_d = ex2_instr_q[0:5] == 6'b010011 & ex2_instr_q[21:30] == 10'b0100000001; // 19/257 +assign ex3_is_crandc_d = ex2_instr_q[0:5] == 6'b010011 & ex2_instr_q[21:30] == 10'b0010000001; // 19/129 +assign ex3_is_creqv_d = ex2_instr_q[0:5] == 6'b010011 & ex2_instr_q[21:30] == 10'b0100100001; // 19/289 +assign ex3_is_crnand_d = ex2_instr_q[0:5] == 6'b010011 & ex2_instr_q[21:30] == 10'b0011100001; // 19/225 +assign ex3_is_crnor_d = ex2_instr_q[0:5] == 6'b010011 & ex2_instr_q[21:30] == 10'b0000100001; // 19/33 +assign ex3_is_cror_d = ex2_instr_q[0:5] == 6'b010011 & ex2_instr_q[21:30] == 10'b0111000001; // 19/449 +assign ex3_is_crorc_d = ex2_instr_q[0:5] == 6'b010011 & ex2_instr_q[21:30] == 10'b0110100001; // 19/417 +assign ex3_is_crxor_d = ex2_instr_q[0:5] == 6'b010011 & ex2_instr_q[21:30] == 10'b0011000001; // 19/193 + +//----------------------------------------------- +// calculate condition +//----------------------------------------------- + +assign ex3_bt[0:4] = ex3_instr_q[6:10]; +assign ex3_ba[0:4] = ex3_instr_q[11:15]; +assign ex3_bb[0:4] = ex3_instr_q[16:20]; + +assign ex3_cra = (ex3_cr3_logical[0] & ex3_ba[3:4] == 2'b00) | (ex3_cr3_logical[1] & ex3_ba[3:4] == 2'b01) | (ex3_cr3_logical[2] & ex3_ba[3:4] == 2'b10) | (ex3_cr3_logical[3] & ex3_ba[3:4] == 2'b11); + +assign ex3_crb = (ex3_cr2[0] & ex3_bb[3:4] == 2'b00) | (ex3_cr2[1] & ex3_bb[3:4] == 2'b01) | (ex3_cr2[2] & ex3_bb[3:4] == 2'b10) | (ex3_cr2[3] & ex3_bb[3:4] == 2'b11); + +assign ex3_crand = ex3_cra & ex3_crb; +assign ex3_crandc = ex3_cra & (~ex3_crb); +assign ex3_creqv = ex3_cra ~^ ex3_crb; +assign ex3_crnand = ~(ex3_cra & ex3_crb); +assign ex3_crnor = ~(ex3_cra | ex3_crb); +assign ex3_cror = ex3_cra | ex3_crb; +assign ex3_crorc = ex3_cra | (~ex3_crb); +assign ex3_crxor = ex3_cra ^ ex3_crb; + +assign ex3_crt = (ex3_crand & ex3_is_crand_q) | (ex3_crandc & ex3_is_crandc_q) | (ex3_creqv & ex3_is_creqv_q) | (ex3_crnand & ex3_is_crnand_q) | (ex3_crnor & ex3_is_crnor_q) | (ex3_cror & ex3_is_cror_q) | (ex3_crorc & ex3_is_crorc_q) | (ex3_crxor & ex3_is_crxor_q); + +//----------------------------------------------- +// update registers +//----------------------------------------------- + +assign ex4_cr_we_d = |(ex4_vld_d) & (ex3_is_crand_q | ex3_is_crandc_q | ex3_is_creqv_q | ex3_is_crnand_q | ex3_is_crnor_q | ex3_is_cror_q | ex3_is_crorc_q | ex3_is_crxor_q | ex3_is_mcrf_q); + +assign ex4_cr_wd_d[0] = (ex3_is_mcrf_q == 1'b1) ? ex3_cr3_logical[0] : + (ex3_bt[3:4] == 2'b00) ? ex3_crt : + ex3_cr1[0]; +assign ex4_cr_wd_d[1] = (ex3_is_mcrf_q == 1'b1) ? ex3_cr3_logical[1] : + (ex3_bt[3:4] == 2'b01) ? ex3_crt : + ex3_cr1[1]; +assign ex4_cr_wd_d[2] = (ex3_is_mcrf_q == 1'b1) ? ex3_cr3_logical[2] : + (ex3_bt[3:4] == 2'b10) ? ex3_crt : + ex3_cr1[2]; +assign ex4_cr_wd_d[3] = (ex3_is_mcrf_q == 1'b1) ? ex3_cr3_logical[3] : + (ex3_bt[3:4] == 2'b11) ? ex3_crt : + ex3_cr1[3]; + + + +//----------------------------------------------- +// performance events +//----------------------------------------------- + +assign br_iu_perf_events = ex4_perf_event_q; + +//perf events +//1: all instructions executed +//2: all branches executed +//3: mispredicted branch direction +//4: taken branches +//5: mispredicted branch target (within current address range) +//6: mispredicted branch target (outside current address range) + +generate begin : perf_event + genvar t,e; + for (e=0;e<=3;e=e+1) begin : thread + for (t=0;t<=`THREADS-1;t=t+1) begin : thread + assign ex4_perf_event_d[e] = + +(spr_xesr2[4*e+16*t:4*e+16*t+3] == 4'd1 ? (perf_event_en[t] & ex4_vld_d[t]) : 1'b0) | +(spr_xesr2[4*e+16*t:4*e+16*t+3] == 4'd2 ? (perf_event_en[t] & ex4_vld_d[t] & (ex3_is_b_q | ex3_is_bc_q | ex3_is_bclr_q | ex3_is_bcctr_q | ex3_is_bctar_q)) : 1'b0) | +(spr_xesr2[4*e+16*t:4*e+16*t+3] == 4'd3 ? (perf_event_en[t] & ex4_redirect_d[t] & (ex4_taken_d ^ ex3_pred_q)) : 1'b0) | +(spr_xesr2[4*e+16*t:4*e+16*t+3] == 4'd4 ? (perf_event_en[t] & ex4_vld_d[t] & ex4_taken_d) : 1'b0) | +(spr_xesr2[4*e+16*t:4*e+16*t+3] == 4'd5 ? (perf_event_en[t] & ex4_redirect_d[t] & (ex4_taken_d & ex3_pred_q & (ex3_bta[62 - `EFF_IFAR_ARCH:61 - `EFF_IFAR_WIDTH] == br_upper_ifar_q[t]))) : 1'b0) | +(spr_xesr2[4*e+16*t:4*e+16*t+3] == 4'd6 ? (perf_event_en[t] & ex4_redirect_d[t] & (ex4_taken_d & ex3_pred_q & (ex3_bta[62 - `EFF_IFAR_ARCH:61 - `EFF_IFAR_WIDTH] != br_upper_ifar_q[t]))) : 1'b0); + end + end +end +endgenerate + +//----------------------------------------------- +// latches +//----------------------------------------------- + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) ex0_vld_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex0_vld_offset:ex0_vld_offset + `THREADS - 1]), + .scout(sov[ex0_vld_offset:ex0_vld_offset + `THREADS - 1]), + .din(ex0_vld_d), + .dout(ex0_vld_q) +); + + +tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu_br_flush_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[iu_br_flush_offset:iu_br_flush_offset + `THREADS - 1]), + .scout(sov[iu_br_flush_offset:iu_br_flush_offset + `THREADS - 1]), + .din(iu_br_flush_d), + .dout(iu_br_flush_q) +); + +generate + begin : xhdl5 + genvar i; + for (i = 0; i <= `THREADS - 1; i = i + 1) + begin : thread_regs + + + tri_rlmreg_p #(.WIDTH((`EFF_IFAR_ARCH-`EFF_IFAR_WIDTH)), .INIT(0)) iu_br_flush_ifar_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(iu_br_flush[i]), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[iu_br_flush_ifar_offset + i * (`EFF_IFAR_ARCH-`EFF_IFAR_WIDTH):iu_br_flush_ifar_offset + (i + 1) * (`EFF_IFAR_ARCH-`EFF_IFAR_WIDTH) - 1]), + .scout(sov[iu_br_flush_ifar_offset + i * (`EFF_IFAR_ARCH-`EFF_IFAR_WIDTH):iu_br_flush_ifar_offset + (i + 1) * (`EFF_IFAR_ARCH-`EFF_IFAR_WIDTH) - 1]), + .din(iu_br_flush_ifar_d[i]), + .dout(iu_br_flush_ifar_q[i]) + ); + + genvar n; + for (n = 0; n < (`EFF_IFAR_ARCH-`EFF_IFAR_WIDTH); n = n + 1) + begin : q_depth_gen + if((62-`EFF_IFAR_ARCH+n) > 31) + tri_rlmlatch_p #(.INIT(1), .NEEDS_SRESET(1)) br_upper_ifar_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(iu_br_flush_q[i]), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[br_upper_ifar_offset + i*(`EFF_IFAR_ARCH-`EFF_IFAR_WIDTH) + n]), + .scout(sov[br_upper_ifar_offset + i*(`EFF_IFAR_ARCH-`EFF_IFAR_WIDTH) + n]), + .din(br_upper_ifar_d[i][(62-`EFF_IFAR_ARCH+n)]), + .dout(br_upper_ifar_q[i][(62-`EFF_IFAR_ARCH+n)]) + ); + else + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) br_upper_ifar_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(iu_br_flush_q[i]), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[br_upper_ifar_offset + i*(`EFF_IFAR_ARCH-`EFF_IFAR_WIDTH) + n]), + .scout(sov[br_upper_ifar_offset + i*(`EFF_IFAR_ARCH-`EFF_IFAR_WIDTH) + n]), + .din(br_upper_ifar_d[i][(62-`EFF_IFAR_ARCH+n)]), + .dout(br_upper_ifar_q[i][(62-`EFF_IFAR_ARCH+n)]) + ); + end + + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) ex4_itag_saved_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex4_itag_saved_offset + i * `ITAG_SIZE_ENC:ex4_itag_saved_offset + (i + 1) * `ITAG_SIZE_ENC - 1]), + .scout(sov[ex4_itag_saved_offset + i * `ITAG_SIZE_ENC:ex4_itag_saved_offset + (i + 1) * `ITAG_SIZE_ENC - 1]), + .din(ex4_itag_saved_d[i]), + .dout(ex4_itag_saved_q[i]) + ); + end + end + endgenerate + + + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) ex3_cr1_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex3_cr1_offset:ex3_cr1_offset + 4 - 1]), + .scout(sov[ex3_cr1_offset:ex3_cr1_offset + 4 - 1]), + .din(ex3_cr1_d), + .dout(ex3_cr1_q) + ); + + + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) ex3_cr2_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex3_cr2_offset:ex3_cr2_offset + 4 - 1]), + .scout(sov[ex3_cr2_offset:ex3_cr2_offset + 4 - 1]), + .din(ex3_cr2_d), + .dout(ex3_cr2_q) + ); + + + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) ex3_cr3_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex3_cr3_offset:ex3_cr3_offset + 4 - 1]), + .scout(sov[ex3_cr3_offset:ex3_cr3_offset + 4 - 1]), + .din(ex3_cr3_d), + .dout(ex3_cr3_q) + ); + + + tri_rlmreg_p #(.WIDTH((-1+`GPR_WIDTH+1)), .INIT(0)) ex3_ctr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex3_ctr_offset:ex3_ctr_offset + (-1+`GPR_WIDTH+1) - 1]), + .scout(sov[ex3_ctr_offset:ex3_ctr_offset + (-1+`GPR_WIDTH+1) - 1]), + .din(ex3_ctr_d), + .dout(ex3_ctr_q) + ); + + tri_rlmreg_p #(.WIDTH((-1+`GPR_WIDTH+1)), .INIT(0)) ex3_lr1_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex3_lr1_offset:ex3_lr1_offset + (-1+`GPR_WIDTH+1) - 1]), + .scout(sov[ex3_lr1_offset:ex3_lr1_offset + (-1+`GPR_WIDTH+1) - 1]), + .din(ex3_lr1_d), + .dout(ex3_lr1_q) + ); + + + tri_rlmreg_p #(.WIDTH((-1+`GPR_WIDTH+1)), .INIT(0)) ex3_lr2_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex3_lr2_offset:ex3_lr2_offset + (-1+`GPR_WIDTH+1) - 1]), + .scout(sov[ex3_lr2_offset:ex3_lr2_offset + (-1+`GPR_WIDTH+1) - 1]), + .din(ex3_lr2_d), + .dout(ex3_lr2_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) ex1_vld_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex1_vld_offset:ex1_vld_offset + `THREADS - 1]), + .scout(sov[ex1_vld_offset:ex1_vld_offset + `THREADS - 1]), + .din(ex1_vld_d), + .dout(ex1_vld_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) ex1_fusion_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex1_fusion_offset]), + .scout(sov[ex1_fusion_offset]), + .din(ex1_fusion_d), + .dout(ex1_fusion_q) + ); + + + tri_rlmreg_p #(.WIDTH(32), .INIT(0)) ex1_instr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex1_instr_offset:ex1_instr_offset + 32 - 1]), + .scout(sov[ex1_instr_offset:ex1_instr_offset + 32 - 1]), + .din(ex1_instr_d), + .dout(ex1_instr_q) + ); + + + tri_rlmreg_p #(.WIDTH((-1+`EFF_IFAR_WIDTH+1)), .INIT(0)) ex1_ifar_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex1_ifar_offset:ex1_ifar_offset + (-1+`EFF_IFAR_WIDTH+1) - 1]), + .scout(sov[ex1_ifar_offset:ex1_ifar_offset + (-1+`EFF_IFAR_WIDTH+1) - 1]), + .din(ex1_ifar_d), + .dout(ex1_ifar_q) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) ex1_itag_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex1_itag_offset:ex1_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[ex1_itag_offset:ex1_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(ex1_itag_d), + .dout(ex1_itag_q) + ); + + + tri_rlmreg_p #(.WIDTH(`LR_POOL_ENC), .INIT(0)) ex1_lr_wa_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex1_lr_wa_offset:ex1_lr_wa_offset + `LR_POOL_ENC - 1]), + .scout(sov[ex1_lr_wa_offset:ex1_lr_wa_offset + `LR_POOL_ENC - 1]), + .din(ex1_lr_wa_d), + .dout(ex1_lr_wa_q) + ); + + + tri_rlmreg_p #(.WIDTH(`CTR_POOL_ENC), .INIT(0)) ex1_ctr_wa_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex1_ctr_wa_offset:ex1_ctr_wa_offset + `CTR_POOL_ENC - 1]), + .scout(sov[ex1_ctr_wa_offset:ex1_ctr_wa_offset + `CTR_POOL_ENC - 1]), + .din(ex1_ctr_wa_d), + .dout(ex1_ctr_wa_q) + ); + + + tri_rlmreg_p #(.WIDTH(`CR_POOL_ENC), .INIT(0)) ex1_cr_wa_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex1_cr_wa_offset:ex1_cr_wa_offset + `CR_POOL_ENC - 1]), + .scout(sov[ex1_cr_wa_offset:ex1_cr_wa_offset + `CR_POOL_ENC - 1]), + .din(ex1_cr_wa_d), + .dout(ex1_cr_wa_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) ex1_pred_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex1_pred_offset]), + .scout(sov[ex1_pred_offset]), + .din(ex1_pred_d), + .dout(ex1_pred_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) ex1_bta_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex1_bta_val_offset]), + .scout(sov[ex1_bta_val_offset]), + .din(ex1_bta_val_d), + .dout(ex1_bta_val_q) + ); + + + tri_rlmreg_p #(.WIDTH((-1+`EFF_IFAR_WIDTH+1)), .INIT(0)) ex1_pred_bta_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex1_pred_bta_offset:ex1_pred_bta_offset + (-1+`EFF_IFAR_WIDTH+1) - 1]), + .scout(sov[ex1_pred_bta_offset:ex1_pred_bta_offset + (-1+`EFF_IFAR_WIDTH+1) - 1]), + .din(ex1_pred_bta_d), + .dout(ex1_pred_bta_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) ex1_ls_ptr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex1_ls_ptr_offset:ex1_ls_ptr_offset + 3 - 1]), + .scout(sov[ex1_ls_ptr_offset:ex1_ls_ptr_offset + 3 - 1]), + .din(ex1_ls_ptr_d), + .dout(ex1_ls_ptr_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) ex1_bh_update_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex1_bh_update_offset]), + .scout(sov[ex1_bh_update_offset]), + .din(ex1_bh_update_d), + .dout(ex1_bh_update_q) + ); + + + tri_rlmreg_p #(.WIDTH(18), .INIT(0)) ex1_gshare_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex1_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex1_gshare_offset:ex1_gshare_offset + 18 - 1]), + .scout(sov[ex1_gshare_offset:ex1_gshare_offset + 18 - 1]), + .din(ex1_gshare_d), + .dout(ex1_gshare_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) ex2_vld_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex2_vld_offset:ex2_vld_offset + `THREADS - 1]), + .scout(sov[ex2_vld_offset:ex2_vld_offset + `THREADS - 1]), + .din(ex2_vld_d), + .dout(ex2_vld_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) ex2_slow_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex2_slow_offset]), + .scout(sov[ex2_slow_offset]), + .din(ex2_slow_d), + .dout(ex2_slow_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) ex2_fusion_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex2_fusion_offset]), + .scout(sov[ex2_fusion_offset]), + .din(ex2_fusion_d), + .dout(ex2_fusion_q) + ); + + + tri_rlmreg_p #(.WIDTH(32), .INIT(0)) ex2_instr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex2_instr_offset:ex2_instr_offset + 32 - 1]), + .scout(sov[ex2_instr_offset:ex2_instr_offset + 32 - 1]), + .din(ex2_instr_d), + .dout(ex2_instr_q) + ); + + + tri_rlmreg_p #(.WIDTH((-1+`EFF_IFAR_WIDTH+1)), .INIT(0)) ex2_ifar_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex2_ifar_offset:ex2_ifar_offset + (-1+`EFF_IFAR_WIDTH+1) - 1]), + .scout(sov[ex2_ifar_offset:ex2_ifar_offset + (-1+`EFF_IFAR_WIDTH+1) - 1]), + .din(ex2_ifar_d), + .dout(ex2_ifar_q) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) ex2_itag_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex2_itag_offset:ex2_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[ex2_itag_offset:ex2_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(ex2_itag_d), + .dout(ex2_itag_q) + ); + + + tri_rlmreg_p #(.WIDTH(`LR_POOL_ENC), .INIT(0)) ex2_lr_wa_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex2_lr_wa_offset:ex2_lr_wa_offset + `LR_POOL_ENC - 1]), + .scout(sov[ex2_lr_wa_offset:ex2_lr_wa_offset + `LR_POOL_ENC - 1]), + .din(ex2_lr_wa_d), + .dout(ex2_lr_wa_q) + ); + + + tri_rlmreg_p #(.WIDTH(`CTR_POOL_ENC), .INIT(0)) ex2_ctr_wa_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex2_ctr_wa_offset:ex2_ctr_wa_offset + `CTR_POOL_ENC - 1]), + .scout(sov[ex2_ctr_wa_offset:ex2_ctr_wa_offset + `CTR_POOL_ENC - 1]), + .din(ex2_ctr_wa_d), + .dout(ex2_ctr_wa_q) + ); + + + tri_rlmreg_p #(.WIDTH(`CR_POOL_ENC), .INIT(0)) ex2_cr_wa_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex2_cr_wa_offset:ex2_cr_wa_offset + `CR_POOL_ENC - 1]), + .scout(sov[ex2_cr_wa_offset:ex2_cr_wa_offset + `CR_POOL_ENC - 1]), + .din(ex2_cr_wa_d), + .dout(ex2_cr_wa_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) ex2_pred_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex2_pred_offset]), + .scout(sov[ex2_pred_offset]), + .din(ex2_pred_d), + .dout(ex2_pred_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) ex2_bta_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex2_bta_val_offset]), + .scout(sov[ex2_bta_val_offset]), + .din(ex2_bta_val_d), + .dout(ex2_bta_val_q) + ); + + + tri_rlmreg_p #(.WIDTH((-1+`EFF_IFAR_WIDTH+1)), .INIT(0)) ex2_pred_bta_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex2_pred_bta_offset:ex2_pred_bta_offset + (-1+`EFF_IFAR_WIDTH+1) - 1]), + .scout(sov[ex2_pred_bta_offset:ex2_pred_bta_offset + (-1+`EFF_IFAR_WIDTH+1) - 1]), + .din(ex2_pred_bta_d), + .dout(ex2_pred_bta_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) ex2_ls_ptr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex2_ls_ptr_offset:ex2_ls_ptr_offset + 3 - 1]), + .scout(sov[ex2_ls_ptr_offset:ex2_ls_ptr_offset + 3 - 1]), + .din(ex2_ls_ptr_d), + .dout(ex2_ls_ptr_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) ex2_bh_update_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex2_bh_update_offset]), + .scout(sov[ex2_bh_update_offset]), + .din(ex2_bh_update_d), + .dout(ex2_bh_update_q) + ); + + + tri_rlmreg_p #(.WIDTH(18), .INIT(0)) ex2_gshare_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex2_gshare_offset:ex2_gshare_offset + 18 - 1]), + .scout(sov[ex2_gshare_offset:ex2_gshare_offset + 18 - 1]), + .din(ex2_gshare_d), + .dout(ex2_gshare_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) ex3_vld_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex3_vld_offset:ex3_vld_offset + `THREADS - 1]), + .scout(sov[ex3_vld_offset:ex3_vld_offset + `THREADS - 1]), + .din(ex3_vld_d), + .dout(ex3_vld_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) ex3_slow_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex3_slow_offset]), + .scout(sov[ex3_slow_offset]), + .din(ex3_slow_d), + .dout(ex3_slow_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) ex3_fusion_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex3_fusion_offset]), + .scout(sov[ex3_fusion_offset]), + .din(ex3_fusion_d), + .dout(ex3_fusion_q) + ); + + + tri_rlmreg_p #(.WIDTH(26), .INIT(0)) ex3_instr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex3_instr_offset:ex3_instr_offset + 26 - 1]), + .scout(sov[ex3_instr_offset:ex3_instr_offset + 26 - 1]), + .din(ex3_instr_d), + .dout(ex3_instr_q) + ); + + + tri_rlmreg_p #(.WIDTH((-1+`EFF_IFAR_WIDTH+1)), .INIT(0)) ex3_ifar_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex3_ifar_offset:ex3_ifar_offset + (-1+`EFF_IFAR_WIDTH+1) - 1]), + .scout(sov[ex3_ifar_offset:ex3_ifar_offset + (-1+`EFF_IFAR_WIDTH+1) - 1]), + .din(ex3_ifar_d), + .dout(ex3_ifar_q) + ); + + + tri_rlmreg_p #(.WIDTH((-1+`EFF_IFAR_ARCH+1)), .INIT(0)) ex3_bta_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex3_bta_offset:ex3_bta_offset + (-1+`EFF_IFAR_ARCH+1) - 1]), + .scout(sov[ex3_bta_offset:ex3_bta_offset + (-1+`EFF_IFAR_ARCH+1) - 1]), + .din(ex3_bta_d), + .dout(ex3_bta_q) + ); + + + tri_rlmreg_p #(.WIDTH((-1+`EFF_IFAR_ARCH+1)), .INIT(0)) ex3_nia_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex3_nia_offset:ex3_nia_offset + (-1+`EFF_IFAR_ARCH+1) - 1]), + .scout(sov[ex3_nia_offset:ex3_nia_offset + (-1+`EFF_IFAR_ARCH+1) - 1]), + .din(ex3_nia_d), + .dout(ex3_nia_q) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) ex3_itag_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex3_itag_offset:ex3_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[ex3_itag_offset:ex3_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(ex3_itag_d), + .dout(ex3_itag_q) + ); + + + tri_rlmreg_p #(.WIDTH(`LR_POOL_ENC), .INIT(0)) ex3_lr_wa_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex3_lr_wa_offset:ex3_lr_wa_offset + `LR_POOL_ENC - 1]), + .scout(sov[ex3_lr_wa_offset:ex3_lr_wa_offset + `LR_POOL_ENC - 1]), + .din(ex3_lr_wa_d), + .dout(ex3_lr_wa_q) + ); + + + tri_rlmreg_p #(.WIDTH(`CTR_POOL_ENC), .INIT(0)) ex3_ctr_wa_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex3_ctr_wa_offset:ex3_ctr_wa_offset + `CTR_POOL_ENC - 1]), + .scout(sov[ex3_ctr_wa_offset:ex3_ctr_wa_offset + `CTR_POOL_ENC - 1]), + .din(ex3_ctr_wa_d), + .dout(ex3_ctr_wa_q) + ); + + + tri_rlmreg_p #(.WIDTH(`CR_POOL_ENC), .INIT(0)) ex3_cr_wa_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex3_cr_wa_offset:ex3_cr_wa_offset + `CR_POOL_ENC - 1]), + .scout(sov[ex3_cr_wa_offset:ex3_cr_wa_offset + `CR_POOL_ENC - 1]), + .din(ex3_cr_wa_d), + .dout(ex3_cr_wa_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) ex3_is_b_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex3_is_b_offset]), + .scout(sov[ex3_is_b_offset]), + .din(ex3_is_b_d), + .dout(ex3_is_b_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) ex3_is_bc_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex3_is_bc_offset]), + .scout(sov[ex3_is_bc_offset]), + .din(ex3_is_bc_d), + .dout(ex3_is_bc_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) ex3_is_bclr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex3_is_bclr_offset]), + .scout(sov[ex3_is_bclr_offset]), + .din(ex3_is_bclr_d), + .dout(ex3_is_bclr_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) ex3_is_bcctr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex3_is_bcctr_offset]), + .scout(sov[ex3_is_bcctr_offset]), + .din(ex3_is_bcctr_d), + .dout(ex3_is_bcctr_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) ex3_is_bctar_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex3_is_bctar_offset]), + .scout(sov[ex3_is_bctar_offset]), + .din(ex3_is_bctar_d), + .dout(ex3_is_bctar_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) ex3_pred_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex3_pred_offset]), + .scout(sov[ex3_pred_offset]), + .din(ex3_pred_d), + .dout(ex3_pred_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) ex3_bta_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex3_bta_val_offset]), + .scout(sov[ex3_bta_val_offset]), + .din(ex3_bta_val_d), + .dout(ex3_bta_val_q) + ); + + + tri_rlmreg_p #(.WIDTH((-1+`EFF_IFAR_WIDTH+1)), .INIT(0)) ex3_pred_bta_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex3_pred_bta_offset:ex3_pred_bta_offset + (-1+`EFF_IFAR_WIDTH+1) - 1]), + .scout(sov[ex3_pred_bta_offset:ex3_pred_bta_offset + (-1+`EFF_IFAR_WIDTH+1) - 1]), + .din(ex3_pred_bta_d), + .dout(ex3_pred_bta_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) ex3_ls_ptr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex3_ls_ptr_offset:ex3_ls_ptr_offset + 3 - 1]), + .scout(sov[ex3_ls_ptr_offset:ex3_ls_ptr_offset + 3 - 1]), + .din(ex3_ls_ptr_d), + .dout(ex3_ls_ptr_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) ex3_bh_update_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex3_bh_update_offset]), + .scout(sov[ex3_bh_update_offset]), + .din(ex3_bh_update_d), + .dout(ex3_bh_update_q) + ); + + + tri_rlmreg_p #(.WIDTH(18), .INIT(0)) ex3_gshare_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex3_gshare_offset:ex3_gshare_offset + 18 - 1]), + .scout(sov[ex3_gshare_offset:ex3_gshare_offset + 18 - 1]), + .din(ex3_gshare_d), + .dout(ex3_gshare_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) ex3_is_mcrf_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex3_is_mcrf_offset]), + .scout(sov[ex3_is_mcrf_offset]), + .din(ex3_is_mcrf_d), + .dout(ex3_is_mcrf_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) ex3_is_crand_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex3_is_crand_offset]), + .scout(sov[ex3_is_crand_offset]), + .din(ex3_is_crand_d), + .dout(ex3_is_crand_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) ex3_is_crandc_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex3_is_crandc_offset]), + .scout(sov[ex3_is_crandc_offset]), + .din(ex3_is_crandc_d), + .dout(ex3_is_crandc_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) ex3_is_creqv_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex3_is_creqv_offset]), + .scout(sov[ex3_is_creqv_offset]), + .din(ex3_is_creqv_d), + .dout(ex3_is_creqv_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) ex3_is_crnand_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex3_is_crnand_offset]), + .scout(sov[ex3_is_crnand_offset]), + .din(ex3_is_crnand_d), + .dout(ex3_is_crnand_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) ex3_is_crnor_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex3_is_crnor_offset]), + .scout(sov[ex3_is_crnor_offset]), + .din(ex3_is_crnor_d), + .dout(ex3_is_crnor_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) ex3_is_cror_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex3_is_cror_offset]), + .scout(sov[ex3_is_cror_offset]), + .din(ex3_is_cror_d), + .dout(ex3_is_cror_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) ex3_is_crorc_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex3_is_crorc_offset]), + .scout(sov[ex3_is_crorc_offset]), + .din(ex3_is_crorc_d), + .dout(ex3_is_crorc_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) ex3_is_crxor_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex3_is_crxor_offset]), + .scout(sov[ex3_is_crxor_offset]), + .din(ex3_is_crxor_d), + .dout(ex3_is_crxor_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) ex4_vld_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex4_vld_offset:ex4_vld_offset + `THREADS - 1]), + .scout(sov[ex4_vld_offset:ex4_vld_offset + `THREADS - 1]), + .din(ex4_vld_d), + .dout(ex4_vld_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) ex4_slow_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex4_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex4_slow_offset]), + .scout(sov[ex4_slow_offset]), + .din(ex4_slow_d), + .dout(ex4_slow_q) + ); + + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) ex4_itag_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex4_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex4_itag_offset:ex4_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[ex4_itag_offset:ex4_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(ex4_itag_d), + .dout(ex4_itag_q) + ); + + + tri_rlmreg_p #(.WIDTH(`LR_POOL_ENC), .INIT(0)) ex4_lr_wa_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex4_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex4_lr_wa_offset:ex4_lr_wa_offset + `LR_POOL_ENC - 1]), + .scout(sov[ex4_lr_wa_offset:ex4_lr_wa_offset + `LR_POOL_ENC - 1]), + .din(ex4_lr_wa_d), + .dout(ex4_lr_wa_q) + ); + + + tri_rlmreg_p #(.WIDTH(`CTR_POOL_ENC), .INIT(0)) ex4_ctr_wa_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex4_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex4_ctr_wa_offset:ex4_ctr_wa_offset + `CTR_POOL_ENC - 1]), + .scout(sov[ex4_ctr_wa_offset:ex4_ctr_wa_offset + `CTR_POOL_ENC - 1]), + .din(ex4_ctr_wa_d), + .dout(ex4_ctr_wa_q) + ); + + + tri_rlmreg_p #(.WIDTH(`CR_POOL_ENC), .INIT(0)) ex4_cr_wa_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex4_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex4_cr_wa_offset:ex4_cr_wa_offset + `CR_POOL_ENC - 1]), + .scout(sov[ex4_cr_wa_offset:ex4_cr_wa_offset + `CR_POOL_ENC - 1]), + .din(ex4_cr_wa_d), + .dout(ex4_cr_wa_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) ex4_taken_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex4_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex4_taken_offset]), + .scout(sov[ex4_taken_offset]), + .din(ex4_taken_d), + .dout(ex4_taken_q) + ); + + + tri_rlmreg_p #(.WIDTH((-1+`EFF_IFAR_ARCH+1)), .INIT(0)) ex4_bta_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex4_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex4_bta_offset:ex4_bta_offset + (-1+`EFF_IFAR_ARCH+1) - 1]), + .scout(sov[ex4_bta_offset:ex4_bta_offset + (-1+`EFF_IFAR_ARCH+1) - 1]), + .din(ex4_bta_d), + .dout(ex4_bta_q) + ); + + tri_rlmreg_p #(.WIDTH(18), .INIT(0)) ex4_gshare_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex4_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex4_gshare_offset:ex4_gshare_offset + 18 - 1]), + .scout(sov[ex4_gshare_offset:ex4_gshare_offset + 18 - 1]), + .din(ex4_gshare_d), + .dout(ex4_gshare_q) + ); + + + tri_rlmreg_p #(.WIDTH(3), .INIT(0)) ex4_ls_ptr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex4_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex4_ls_ptr_offset:ex4_ls_ptr_offset + 3 - 1]), + .scout(sov[ex4_ls_ptr_offset:ex4_ls_ptr_offset + 3 - 1]), + .din(ex4_ls_ptr_d), + .dout(ex4_ls_ptr_q) + ); + + + tri_rlmreg_p #(.WIDTH((-1+`EFF_IFAR_WIDTH+1)), .INIT(0)) ex4_ls_data_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex4_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex4_ls_data_offset:ex4_ls_data_offset + (-1+`EFF_IFAR_WIDTH+1) - 1]), + .scout(sov[ex4_ls_data_offset:ex4_ls_data_offset + (-1+`EFF_IFAR_WIDTH+1) - 1]), + .din(ex4_ls_data_d), + .dout(ex4_ls_data_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) ex4_ls_update_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex4_act), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex4_ls_update_offset]), + .scout(sov[ex4_ls_update_offset]), + .din(ex4_ls_update_d), + .dout(ex4_ls_update_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) ex4_redirect_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex4_redirect_offset:ex4_redirect_offset + `THREADS - 1]), + .scout(sov[ex4_redirect_offset:ex4_redirect_offset + `THREADS - 1]), + .din(ex4_redirect_d), + .dout(ex4_redirect_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) ex4_itag_saved_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex4_itag_saved_val_offset:ex4_itag_saved_val_offset + `THREADS - 1]), + .scout(sov[ex4_itag_saved_val_offset:ex4_itag_saved_val_offset + `THREADS - 1]), + .din(ex4_itag_saved_val_d), + .dout(ex4_itag_saved_val_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) ex4_lr_we_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex4_lr_we_offset]), + .scout(sov[ex4_lr_we_offset]), + .din(ex4_lr_we_d), + .dout(ex4_lr_we_q) + ); + + + tri_rlmreg_p #(.WIDTH((-1+`GPR_WIDTH+1)), .INIT(0)) ex4_lr_wd_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex4_lr_we_d), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex4_lr_wd_offset:ex4_lr_wd_offset + (-1+`GPR_WIDTH+1) - 1]), + .scout(sov[ex4_lr_wd_offset:ex4_lr_wd_offset + (-1+`GPR_WIDTH+1) - 1]), + .din(ex4_lr_wd_d), + .dout(ex4_lr_wd_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) ex4_ctr_we_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex4_ctr_we_offset]), + .scout(sov[ex4_ctr_we_offset]), + .din(ex4_ctr_we_d), + .dout(ex4_ctr_we_q) + ); + + + tri_rlmreg_p #(.WIDTH((-1+`GPR_WIDTH+1)), .INIT(0)) ex4_ctr_wd_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex4_ctr_we_d), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex4_ctr_wd_offset:ex4_ctr_wd_offset + (-1+`GPR_WIDTH+1) - 1]), + .scout(sov[ex4_ctr_wd_offset:ex4_ctr_wd_offset + (-1+`GPR_WIDTH+1) - 1]), + .din(ex4_ctr_wd_d), + .dout(ex4_ctr_wd_q) + ); + + + tri_rlmlatch_p #(.INIT(0)) ex4_cr_we_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex4_cr_we_offset]), + .scout(sov[ex4_cr_we_offset]), + .din(ex4_cr_we_d), + .dout(ex4_cr_we_q) + ); + + + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) ex4_cr_wd_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex4_cr_we_d), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex4_cr_wd_offset:ex4_cr_wd_offset + 4 - 1]), + .scout(sov[ex4_cr_wd_offset:ex4_cr_wd_offset + 4 - 1]), + .din(ex4_cr_wd_d), + .dout(ex4_cr_wd_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0)) ex4_perf_event( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[ex4_perf_event_offset:ex4_perf_event_offset + 4 - 1]), + .scout(sov[ex4_perf_event_offset:ex4_perf_event_offset + 4 - 1]), + .din(ex4_perf_event_d), + .dout(ex4_perf_event_q) + ); + + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) spr_msr_cm_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .force_t(force_t), + .scin(siv[spr_msr_cm_offset:spr_msr_cm_offset + `THREADS - 1]), + .scout(sov[spr_msr_cm_offset:spr_msr_cm_offset + `THREADS - 1]), + .din(spr_msr_cm), + .dout(spr_msr_cm_q) + ); + + //----------------------------------------------- + // pervasive + //----------------------------------------------- + + tri_plat #(.WIDTH(2)) perv_2to1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + .din({pc_br_func_sl_thold_2,pc_br_sg_2}), + .q({func_sl_thold_1,sg_1}) + ); + + + tri_plat #(.WIDTH(2)) perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ac_ccflush_dc), + .din({func_sl_thold_1,sg_1}), + .q({func_sl_thold_0,sg_0}) + ); + + tri_lcbor perv_lcbor( + .clkoff_b(clkoff_b), + .thold(func_sl_thold_0), + .sg(sg_0), + .act_dis(act_dis), + .force_t(force_t), + .thold_b(func_sl_thold_0_b) + ); + + //----------------------------------------------- + // scan + //----------------------------------------------- + assign siv[0:scan_right - 1] = {sov[1:scan_right - 1], scan_in}; + assign scan_out = sov[0]; + + +endmodule diff --git a/dev/verilog/work/xu0_byp.v b/dev/verilog/work/xu0_byp.v new file mode 100755 index 0000000..50d8730 --- /dev/null +++ b/dev/verilog/work/xu0_byp.v @@ -0,0 +1,2720 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" + +module xu0_byp( + //------------------------------------------------------------------- + // Clocks & Power + //------------------------------------------------------------------- + input [0:`NCLK_WIDTH-1] nclk, + inout vdd, + inout gnd, + + //------------------------------------------------------------------- + // Pervasive + //------------------------------------------------------------------- + input d_mode_dc, + input [0:0] delay_lclkr_dc, + input [0:0] mpw1_dc_b, + input mpw2_dc_b, + input func_sl_force, + input func_sl_thold_0_b, + input sg_0, + input scan_in, + output scan_out, + + input ex4_spr_msr_cm, + + //------------------------------------------------------------------- + // Decode Interface + //------------------------------------------------------------------- + input dec_byp_ex0_act, + input xu1_xu0_ex3_act, + input lq_xu_ex5_act, + + input [64-`GPR_WIDTH:63] dec_byp_ex1_imm, + + input [24:25] dec_byp_ex1_instr, + + input dec_byp_ex1_is_mflr, + input dec_byp_ex1_is_mfxer, + input dec_byp_ex1_is_mtxer, + input dec_byp_ex1_is_mfcr_sel, + input [0:7] dec_byp_ex1_is_mfcr, + input [0:7] dec_byp_ex1_is_mtcr, + input dec_byp_ex1_is_mfctr, + input dec_byp_ex3_is_mtspr, + + input [2:3] dec_byp_ex1_cr_sel, + input [2:3] dec_byp_ex1_xer_sel, + + input dec_byp_ex1_rs_capt, + input dec_byp_ex1_ra_capt, + + input dec_byp_ex0_rs2_sel_imm, + input dec_byp_ex0_rs1_sel_zero, + + input dec_byp_ex3_mtiar, + input dec_byp_ex5_ord_sel, + + //------------------------------------------------------------------- + // RV + //------------------------------------------------------------------- + input rv_xu0_ex0_s1_v, + input rv_xu0_ex0_s2_v, + input rv_xu0_ex0_s3_v, + + //------------------------------------------------------------------- + // Interface with Bypass Controller + //------------------------------------------------------------------- + input [1:11] rv_xu0_s1_fxu0_sel, + input [1:11] rv_xu0_s2_fxu0_sel, + input [2:11] rv_xu0_s3_fxu0_sel, + input [1:6] rv_xu0_s1_fxu1_sel, + input [1:6] rv_xu0_s2_fxu1_sel, + input [2:6] rv_xu0_s3_fxu1_sel, + input [4:8] rv_xu0_s1_lq_sel, + input [4:8] rv_xu0_s2_lq_sel, + input [4:8] rv_xu0_s3_lq_sel, + input [2:3] rv_xu0_s1_rel_sel, + input [2:3] rv_xu0_s2_rel_sel, + + //------------------------------------------------------------------- + // Bypass Inputs + //------------------------------------------------------------------- + // Regfile Data + input [64-`GPR_WIDTH:63] gpr_xu0_ex1_r1d, + input [64-`GPR_WIDTH:63] gpr_xu0_ex1_r2d, + input [0:9] xer_xu0_ex1_r2d, + input [0:9] xer_xu0_ex1_r3d, + input [0:3] cr_xu0_ex1_r1d, + input [0:3] cr_xu0_ex1_r2d, + input [0:3] cr_xu0_ex1_r3d, + input [64-`GPR_WIDTH:63] lr_xu0_ex1_r1d, + input [64-`GPR_WIDTH:63] lr_xu0_ex1_r2d, + input [64-`GPR_WIDTH:63] ctr_xu0_ex1_r2d, + + // External Bypass + input xu1_xu0_ex2_abort, + input [64-`GPR_WIDTH:63] xu1_xu0_ex2_rt, + input [64-`GPR_WIDTH:63] xu1_xu0_ex3_rt, + input [64-`GPR_WIDTH:63] xu1_xu0_ex4_rt, + input [64-`GPR_WIDTH:63] xu1_xu0_ex5_rt, + input lq_xu_ex5_abort, + input [64-`GPR_WIDTH:63] lq_xu_ex5_data, + input [64-`GPR_WIDTH:63] lq_xu_ex5_rt, + input [64-`GPR_WIDTH:63] lq_xu_rel_rt, + input lq_xu_rel_act, + + // CR + input [0:3] lq_xu_ex5_cr, + input [0:3] xu1_xu0_ex3_cr, + // XER + input [0:9] xu1_xu0_ex3_xer, + + // Internal Bypass + input [64-`GPR_WIDTH:63] alu_byp_ex2_add_rt, + input [64-`GPR_WIDTH:63] alu_byp_ex3_rt, + // CR + input [0:3] alu_byp_ex3_cr, + // XER + input [0:9] alu_byp_ex3_xer, + + // BR + input br_byp_ex3_lr_we, + input [64-`GPR_WIDTH:63] br_byp_ex3_lr_wd, + input br_byp_ex3_ctr_we, + input [64-`GPR_WIDTH:63] br_byp_ex3_ctr_wd, + input br_byp_ex3_cr_we, + input [0:3] br_byp_ex3_cr_wd, + + //------------------------------------------------------------------- + // SPR Interface + //------------------------------------------------------------------- + input spr_xu_ord_write_done, + input [64-`GPR_WIDTH:63] spr_xu_ex4_rd_data, + output [64-`GPR_WIDTH:63] xu_spr_ex2_rs1, + + input xu_slowspr_val_in, + input xu_slowspr_rw_in, + input [64-`GPR_WIDTH:63] xu_slowspr_data_in, + input xu_slowspr_done_in, + + //------------------------------------------------------------------- + // Div Interfaces + //------------------------------------------------------------------- + input div_byp_ex4_done, + input [64-`GPR_WIDTH:63] div_byp_ex4_rt, + input [0:9] div_byp_ex4_xer, + input [0:3] div_byp_ex4_cr, + + //------------------------------------------------------------------- + // Mul Interfaces + //------------------------------------------------------------------- + input mul_byp_ex5_ord_done, + input mul_byp_ex5_done, + input mul_byp_ex5_abort, + input [64-`GPR_WIDTH:63] mul_byp_ex6_rt, + input [0:9] mul_byp_ex6_xer, + input [0:3] mul_byp_ex6_cr, + + //------------------------------------------------------------------- + // ERAT Interfaces + //------------------------------------------------------------------- + input iu_xu_ord_write_done, + input [64-`GPR_WIDTH:63] iu_xu_ex5_data, + input lq_xu_ord_write_done, + + //------------------------------------------------------------------- + // popcnt / cntlz / dlmzb / bcd + //------------------------------------------------------------------- + input dec_byp_ex4_hpriv, + input [0:31] dec_byp_ex4_instr, + input dec_byp_ex4_pop_done, + input dec_byp_ex3_cnt_done, + input dec_byp_ex3_prm_done, + input dec_byp_ex3_dlm_done, + input bcd_byp_ex3_done, + + input [64-`GPR_WIDTH:63] pop_byp_ex4_rt, + input [57:63] cnt_byp_ex2_rt, + input [56:63] prm_byp_ex2_rt, + input [60:63] dlm_byp_ex2_rt, + input [0:9] dlm_byp_ex2_xer, + input [0:3] dlm_byp_ex2_cr, + input [64-`GPR_WIDTH:63] bcd_byp_ex3_rt, + + //------------------------------------------------------------------- + // MMU Interfaces + //------------------------------------------------------------------- + input mm_xu_cr0_eq, // for record forms + input mm_xu_cr0_eq_valid, // for record forms + + output [0:8] xu_iu_rs_is, + output [0:3] xu_iu_ra_entry, + output [64-`GPR_WIDTH:51] xu_iu_rb, + output [64-`GPR_WIDTH:63] xu_iu_rs_data, + + output [0:8] xu_lq_rs_is, + output [0:4] xu_lq_ra_entry, + output [64-`GPR_WIDTH:51] xu_lq_rb, + output [64-`GPR_WIDTH:63] xu_lq_rs_data, + + output [0:11] xu_mm_ra_entry, + output [64-`GPR_WIDTH:63] xu_mm_rb, + + //------------------------------------------------------------------- + // Bypass Outputs + //------------------------------------------------------------------- + output xu0_xu1_ex2_abort, + output xu0_xu1_ex6_abort, + output xu0_lq_ex3_abort, + + output [64-`GPR_WIDTH:63] xu0_xu1_ex2_rt, + output [64-`GPR_WIDTH:63] xu0_xu1_ex3_rt, + output [64-`GPR_WIDTH:63] xu0_xu1_ex4_rt, + output [64-`GPR_WIDTH:63] xu0_xu1_ex5_rt, + output [64-`GPR_WIDTH:63] xu0_xu1_ex6_rt, + output [64-`GPR_WIDTH:63] xu0_xu1_ex7_rt, + output [64-`GPR_WIDTH:63] xu0_xu1_ex8_rt, + output [64-`GPR_WIDTH:63] xu0_xu1_ex6_lq_rt, + output [64-`GPR_WIDTH:63] xu0_xu1_ex7_lq_rt, + output [64-`GPR_WIDTH:63] xu0_xu1_ex8_lq_rt, + + output [64-`GPR_WIDTH:63] xu0_lq_ex3_rt, + output [64-`GPR_WIDTH:63] xu0_lq_ex4_rt, + output xu0_lq_ex6_act, + output [64-`GPR_WIDTH:63] xu0_lq_ex6_rt, + output [64-`GPR_WIDTH:63] xu0_pc_ram_data, + + // CR + output [0:3] xu0_xu1_ex3_cr, + output [0:3] xu0_xu1_ex4_cr, + output [0:3] xu0_xu1_ex6_cr, + + // XER + output [0:9] xu0_xu1_ex3_xer, + output [0:9] xu0_xu1_ex4_xer, + output [0:9] xu0_xu1_ex6_xer, + + //------------------------------------------------------------------- + // Source Outputs + //------------------------------------------------------------------- + output [64-`GPR_WIDTH:63] byp_alu_ex2_rs1, // Source Data + output [64-`GPR_WIDTH:63] byp_alu_ex2_rs2, + output byp_alu_ex2_cr_bit, // CR bit for isel + output [0:9] byp_alu_ex2_xer, + + output [64-`GPR_WIDTH:63] byp_pop_ex2_rs1, + output [64-`GPR_WIDTH:63] byp_cnt_ex2_rs1, + + output [64-`GPR_WIDTH:63] byp_div_ex2_rs1, + output [64-`GPR_WIDTH:63] byp_div_ex2_rs2, + output [0:9] byp_div_ex2_xer, + + output [0:`GPR_WIDTH-1] byp_mul_ex2_rs1, + output [0:`GPR_WIDTH-1] byp_mul_ex2_rs2, + output byp_mul_ex2_abort, + output [0:9] byp_mul_ex2_xer, + + output [32:63] byp_dlm_ex2_rs1, + output [32:63] byp_dlm_ex2_rs2, + output [0:2] byp_dlm_ex2_xer, + + output [64-`GPR_WIDTH:63] byp_bcd_ex2_rs1, + output [64-`GPR_WIDTH:63] byp_bcd_ex2_rs2, + + output [0:3] byp_br_ex3_cr, + output [0:3] byp_br_ex2_cr1, + output [0:3] byp_br_ex2_cr2, + output [0:3] byp_br_ex2_cr3, + + output [64-`GPR_WIDTH:63] byp_br_ex2_lr1, + output [64-`GPR_WIDTH:63] byp_br_ex2_lr2, + + output [64-`GPR_WIDTH:63] byp_br_ex2_ctr, + + output xu0_rv_ex2_s1_abort, + output xu0_rv_ex2_s2_abort, + output xu0_rv_ex2_s3_abort, + output byp_dec_ex2_abort, + + //------------------------------------------------------------------- + // Target Outputs + //------------------------------------------------------------------- + output [62-`EFF_IFAR_ARCH:61] xu0_iu_bta, + output [64-`GPR_WIDTH:65+`GPR_WIDTH/8] xu0_gpr_ex6_wd, + output [0:9] xu0_xer_ex6_w0d, + output [0:3] xu0_cr_ex6_w0d, + output [64-`GPR_WIDTH:63] xu0_ctr_ex4_w0d, + output [64-`GPR_WIDTH:63] xu0_lr_ex4_w0d +); + + localparam DEX0 = 0; + localparam DEX1 = 0; + localparam DEX2 = 0; + localparam DEX3 = 0; + localparam DEX4 = 0; + localparam DEX5 = 0; + localparam DEX6 = 0; + localparam DEX7 = 0; + localparam DEX8 = 0; + localparam DX = 0; + // Latches + wire [1:7] exx_xu0_act_q, exx_xu0_act_d ; // input=>exx_xu0_act_d ,act=>1'b1 + wire [6:8] exx_lq_act_q, exx_lq_act_d ; // input=>exx_lq_act_d ,act=>1'b1 + wire ex1_s1_v_q ; // input=>rv_xu0_ex0_s1_v ,act=>1'b1 + wire ex1_s2_v_q ; // input=>rv_xu0_ex0_s2_v ,act=>1'b1 + wire ex1_s3_v_q ; // input=>rv_xu0_ex0_s3_v ,act=>1'b1 + wire [0:7] ex1_gpr_s1_xu0_sel_q[2:8] ; // input=>{8{ex0_gpr_s1_xu0_sel[i-1]}} ,act=>exx_xu0_act[0] + wire [0:7] ex1_gpr_s2_xu0_sel_q[2:8] ; // input=>{8{ex0_gpr_s2_xu0_sel[i-1]}} ,act=>exx_xu0_act[0] + wire [0:7] ex1_gpr_s1_xu1_sel_q[2:5] ; // input=>{8{ex0_gpr_s1_xu1_sel[i-1]}} ,act=>exx_xu0_act[0] + wire [0:7] ex1_gpr_s2_xu1_sel_q[2:5] ; // input=>{8{ex0_gpr_s2_xu1_sel[i-1]}} ,act=>exx_xu0_act[0] + wire [0:7] ex1_gpr_s1_lq_sel_q[5:8] ; // input=>{8{ex0_gpr_s1_lq_sel[i-1]}} ,act=>exx_xu0_act[0] + wire [0:7] ex1_gpr_s2_lq_sel_q[5:8] ; // input=>{8{ex0_gpr_s2_lq_sel[i-1]}} ,act=>exx_xu0_act[0] + wire [0:7] ex1_gpr_s2_imm_sel_q ; // input=>{8{dec_byp_ex0_rs2_sel_imm}} ,act=>exx_xu0_act[0] + wire [0:2] ex1_spr_s1_xu0_sel_q[3:6] ; // input=>{3{rv_xu0_s1_fxu0_sel[i-1]}} ,act=>exx_xu0_act[0] + wire [0:0] ex1_spr_s1_xu1_sel_q[3:3] ; // input=>{1{rv_xu0_s1_fxu1_sel[i-1]}} ,act=>exx_xu0_act[0] + wire [0:0] ex1_spr_s1_lq_sel_q[5:6] ; // input=>{1{rv_xu0_s1_lq_sel[i-1]}} ,act=>exx_xu0_act[0] + wire [0:5] ex1_spr_s2_xu0_sel_q[3:6] ; // input=>{6{rv_xu0_s2_fxu0_sel[i-1]}} ,act=>exx_xu0_act[0] + wire [0:1] ex1_spr_s2_xu1_sel_q[3:3] ; // input=>{2{rv_xu0_s2_fxu1_sel[i-1]}} ,act=>exx_xu0_act[0] + wire [0:0] ex1_spr_s2_lq_sel_q[5:6] ; // input=>{1{rv_xu0_s2_lq_sel[i-1]}} ,act=>exx_xu0_act[0] + wire [0:1] ex1_spr_s3_xu0_sel_q[3:8] ; // input=>{2{rv_xu0_s3_fxu0_sel[i-1]}} ,act=>exx_xu0_act[0] + wire [0:1] ex1_spr_s3_xu1_sel_q[3:5] ; // input=>{2{rv_xu0_s3_fxu1_sel[i-1]}} ,act=>exx_xu0_act[0] + wire [0:0] ex1_spr_s3_lq_sel_q[5:6] ; // input=>{1{rv_xu0_s3_lq_sel[i-1]}} ,act=>exx_xu0_act[0] + wire [0:7] ex1_gpr_s1_rel_sel_q[3:4] ; // input=>{8{ex0_gpr_s1_rel_sel[i-1]}} ,act=>exx_xu0_act[0] + wire [0:7] ex1_gpr_s2_rel_sel_q[3:4] ; // input=>{8{ex0_gpr_s2_rel_sel[i-1]}} ,act=>exx_xu0_act[0] + wire [0:7] ex1_gpr_s1_reg_sel_q ; // input=>{8{ex0_gpr_s1_reg_sel}} ,act=>ex0_xu0_ivax_act + wire [0:7] ex1_gpr_s2_reg_sel_q ; // input=>{8{ex0_gpr_s2_reg_sel}} ,act=>exx_xu0_act[0] + wire [0:2] ex1_spr_s1_reg_sel_q ; // input=>{3{ex0_spr_s1_reg_sel}} ,act=>exx_xu0_act[0] + wire [0:5] ex1_spr_s2_reg_sel_q ; // input=>{6{ex0_spr_s2_reg_sel}} ,act=>exx_xu0_act[0] + wire [0:1] ex1_spr_s3_reg_sel_q ; // input=>{2{ex0_spr_s3_reg_sel}} ,act=>exx_xu0_act[0] + wire [9:9] ex1_abt_s1_lq_sel_q ; // input=>ex0_gpr_s1_lq_sel[8] ,act=>exx_xu0_act[0] + wire [9:9] ex1_abt_s2_lq_sel_q ; // input=>ex0_gpr_s2_lq_sel[8] ,act=>exx_xu0_act[0] + wire [7:9] ex1_abt_s3_lq_sel_q ; // input=>rv_xu0_s3_lq_sel[6:8] ,act=>exx_xu0_act[0] + wire [6:7] ex1_abt_s1_xu1_sel_q ; // input=>ex0_gpr_s1_xu1_sel[5:6] ,act=>exx_xu0_act[0] + wire [6:7] ex1_abt_s2_xu1_sel_q ; // input=>ex0_gpr_s2_xu1_sel[5:6] ,act=>exx_xu0_act[0] + wire [6:7] ex1_abt_s3_xu1_sel_q ; // input=>rv_xu0_s3_fxu1_sel[5:6] ,act=>exx_xu0_act[0] + wire [9:12] ex1_abt_s1_xu0_sel_q ; // input=>ex0_gpr_s1_xu0_sel[8:11] ,act=>exx_xu0_act[0] + wire [9:12] ex1_abt_s2_xu0_sel_q ; // input=>ex0_gpr_s2_xu0_sel[8:11] ,act=>exx_xu0_act[0] + wire [9:12] ex1_abt_s3_xu0_sel_q ; // input=>rv_xu0_s3_fxu0_sel[8:11] ,act=>exx_xu0_act[0] + wire ex2_is_mflr_q ; // input=>dec_byp_ex1_is_mflr ,act=>exx_xu0_act[1] + wire ex2_is_mfxer_q ; // input=>dec_byp_ex1_is_mfxer ,act=>exx_xu0_act[1] + wire ex2_is_mtxer_q ; // input=>dec_byp_ex1_is_mtxer ,act=>exx_xu0_act[1] + wire ex2_is_mfcr_sel_q ; // input=>dec_byp_ex1_is_mfcr_sel ,act=>exx_xu0_act[1] + wire [0:7] ex2_is_mfcr_q ; // input=>dec_byp_ex1_is_mfcr ,act=>exx_xu0_act[1] + wire [0:7] ex2_is_mtcr_q ; // input=>dec_byp_ex1_is_mtcr ,act=>exx_xu0_act[1] + wire ex2_is_mfctr_q ; // input=>dec_byp_ex1_is_mfctr ,act=>exx_xu0_act[1] + wire ex3_is_mtxer_q ; // input=>ex2_is_mtxer_q ,act=>exx_xu0_act[2] + wire [64-`GPR_WIDTH:63] ex4_xu0_rt_q, ex3_xu0_rt_nobyp ; // input=>ex3_xu0_rt_nobyp ,act=>exx_xu0_act[3] + wire [64-`GPR_WIDTH:63] ex5_xu0_rt_q, ex4_xu0_rt_nobyp ; // input=>ex4_xu0_rt_nobyp ,act=>exx_xu0_act[4] + wire [64-`GPR_WIDTH:63] ex6_xu0_rt_q, ex5_xu0_rt ; // input=>ex5_xu0_rt ,act=>exx_xu0_act[5] + wire [64-`GPR_WIDTH:63] ex7_xu0_rt_q, ex6_xu0_rt ; // input=>ex6_xu0_rt ,act=>exx_xu0_act[6] + wire [64-`GPR_WIDTH:63] ex8_xu0_rt_q ; // input=>ex7_xu0_rt_q ,act=>exx_xu0_act[7] + wire [64-`GPR_WIDTH:63] ex6_lq_rt_q ; // input=>lq_xu_ex5_rt ,act=>exx_lq_act[5] + wire [64-`GPR_WIDTH:63] ex7_lq_rt_q ; // input=>ex6_lq_rt_q ,act=>exx_lq_act[6] + wire [64-`GPR_WIDTH:63] ex8_lq_rt_q ; // input=>ex7_lq_rt_q ,act=>exx_lq_act[7] + wire [0:3] ex4_xu0_cr_q, ex3_xu0_cr ; // input=>ex3_xu0_cr ,act=>exx_xu0_act[3] + wire [0:3] ex5_xu0_cr_q ; // input=>ex4_xu0_cr_q ,act=>exx_xu0_act[4] + wire [0:3] ex6_xu0_cr_q, ex5_xu0_cr ; // input=>ex5_xu0_cr ,act=>exx_xu0_act[5] + wire [0:3] ex6_lq_cr_q ; // input=>lq_xu_ex5_cr ,act=>exx_lq_act[5] + wire [0:9] ex4_xu0_xer_q, ex3_xu0_xer2 ; // input=>ex3_xu0_xer2 ,act=>exx_xu0_act[3] + wire [0:9] ex5_xu0_xer_q ; // input=>ex4_xu0_xer_q ,act=>exx_xu0_act[4] + wire [0:9] ex6_xu0_xer_q, ex5_xu0_xer ; // input=>ex5_xu0_xer ,act=>exx_xu0_act[5] + wire [64-`GPR_WIDTH:63] ex4_xu0_ctr_q, ex3_xu0_ctr ; // input=>ex3_xu0_ctr ,act=>ex3_xu0_ctr_act + wire [64-`GPR_WIDTH:63] ex4_xu0_lr_q, ex3_xu0_lr ; // input=>ex3_xu0_lr ,act=>ex3_xu0_lr_act + wire [64-`GPR_WIDTH:63] ex2_rs1_q, ex1_rs1 ; // input=>ex1_rs1 ,act=>ex1_xu0_ivax_act + wire [64-`GPR_WIDTH:63] ex2_rs2_q, ex1_rs2 ; // input=>ex1_rs2 ,act=>exx_xu0_act[1] + wire [0:3] ex2_cr1_q, ex1_cr1 ; // input=>ex1_cr1 ,act=>exx_xu0_act[1] + wire [0:3] ex2_cr2_q, ex1_cr2 ; // input=>ex1_cr2 ,act=>exx_xu0_act[1] + wire [0:3] ex2_cr3_q, ex1_cr3 ; // input=>ex1_cr3 ,act=>exx_xu0_act[1] + wire ex2_cr_bit_q, ex1_cr_bit ; // input=>ex1_cr_bit ,act=>exx_xu0_act[1] + wire [0:9] ex2_xer2_q, ex1_xer2 ; // input=>ex1_xer2 ,act=>exx_xu0_act[1] + wire [0:9] ex2_xer3_q, ex1_xer3 ; // input=>ex1_xer3 ,act=>exx_xu0_act[1] + wire [0:0] ex3_xer3_q ; // input=>ex2_xer3_q[0:0] ,act=>exx_xu0_act[2] + wire [64-`GPR_WIDTH:63] ex2_lr1_q, ex1_lr1 ; // input=>ex1_lr1 ,act=>exx_xu0_act[1] + wire [64-`GPR_WIDTH:63] ex2_lr2_q, ex1_lr2 ; // input=>ex1_lr2 ,act=>exx_xu0_act[1] + wire [64-`GPR_WIDTH:63] ex2_ctr2_q, ex1_ctr2 ; // input=>ex1_ctr2 ,act=>exx_xu0_act[1] + wire [2:3] ex2_cr_sel_q ; // input=>dec_byp_ex1_cr_sel ,act=>exx_xu0_act[1] + wire [2:3] ex2_xer_sel_q ; // input=>dec_byp_ex1_xer_sel ,act=>exx_xu0_act[1] + wire [64-`GPR_WIDTH:63] ex3_rs1_q ; // input=>ex2_rs1_q ,act=>exx_xu0_act[2] + wire ex3_mfspr_sel_q, ex2_mfspr_sel ; // input=>ex2_mfspr_sel ,act=>exx_xu0_act[2] + wire [64-`GPR_WIDTH:63] ex3_mfspr_rt_q, ex2_mfspr_rt ; // input=>ex2_mfspr_rt ,act=>ex2_mfspr_act + wire [64-`GPR_WIDTH:63] ord_rt_data_q, ord_rt_data_d ; // input=>ord_rt_data_d ,act=>ord_data_act + wire [0:3] ord_cr_data_q, ord_cr_data_d ; // input=>ord_cr_data_d ,act=>ord_data_act + wire [0:9] ord_xer_data_q, ord_xer_data_d ; // input=>ord_xer_data_d ,act=>ord_data_act + wire ex2_rs_capt_q ; // input=>dec_byp_ex1_rs_capt ,act=>1'b1 + wire ex2_ra_capt_q ; // input=>dec_byp_ex1_ra_capt ,act=>1'b1 + wire ex3_ra_capt_q ; // input=>ex2_ra_capt_q ,act=>1'b1 + wire ex4_ra_capt_q ; // input=>ex3_ra_capt_q ,act=>1'b1 + wire [52:63] ex2_rs2_noimm_q ; // input=>ex1_rs2_noimm[52:63] ,act=>exx_xu0_act[1] + wire [0:3] ex3_mtcr_q, ex2_mtcr ; // input=>ex2_mtcr ,act=>exx_xu0_act[2] + wire ex3_mtcr_sel_q, ex2_mtcr_sel ; // input=>ex2_mtcr_sel ,act=>exx_xu0_act[2] + wire [0:8] mm_rs_is_q, mm_rs_is_d ; // input=>mm_rs_is_d ,act=>ex2_rs_capt_q + wire [0:11] mm_ra_entry_q, mm_ra_entry_d ; // input=>mm_ra_entry_d ,act=>ex2_ra_capt_q + wire [64-`GPR_WIDTH:63] mm_data_q, mm_data_d ; // input=>mm_data_d ,act=>ex4_ra_capt_q + wire [57:63] ex3_cnt_rt_q ; // input=>cnt_byp_ex2_rt ,act=>exx_xu0_act[2] + wire [56:63] ex3_prm_rt_q ; // input=>prm_byp_ex2_rt ,act=>exx_xu0_act[2] + wire [60:63] ex3_dlm_rt_q ; // input=>dlm_byp_ex2_rt ,act=>exx_xu0_act[2] + wire [0:9] ex3_dlm_xer_q ; // input=>dlm_byp_ex2_xer ,act=>exx_xu0_act[2] + wire [0:3] ex3_dlm_cr_q ; // input=>dlm_byp_ex2_cr ,act=>exx_xu0_act[2] + wire [0:0] ex6_mul_ord_done_q ; // input=>{1{mul_byp_ex5_ord_done}} ,act=>1'b1 + wire ex6_mul_abort_q ; // input=>mul_byp_ex5_abort ,act=>1'b1 + wire [0:8] ex6_mul_done_q ; // input=>{9{mul_byp_ex5_done}} ,act=>1'b1 + wire [2:12] exx_xu0_abort_q, exx_xu0_abort_d ; // input=>exx_xu0_abort_d ,act=>1'b1 + wire [3:7] exx_xu1_abort_q, exx_xu1_abort_d ; // input=>exx_xu1_abort_d ,act=>1'b1 + wire [6:9] exx_lq_abort_q, exx_lq_abort_d ; // input=>exx_lq_abort_d ,act=>1'b1 + wire ex2_rs1_abort_q ; // input=>ex1_rs1_abort ,act=>1'b1 + wire ex2_rs2_abort_q ; // input=>ex1_rs2_abort ,act=>1'b1 + wire ex2_rs3_abort_q ; // input=>ex1_rs3_abort ,act=>1'b1 + wire exx_rel3_act_q ; // input=>lq_xu_rel_act ,act=>1'b1 + wire [64-`GPR_WIDTH:63] exx_rel3_rt_q ; // input=>lq_xu_rel_rt ,act=>lq_xu_rel_act + wire [64-`GPR_WIDTH:63] exx_rel4_rt_q ; // input=>exx_rel3_rt_q ,act=>exx_rel3_act_q + // Scanchain + localparam exx_xu0_act_offset = 0; + localparam exx_lq_act_offset = exx_xu0_act_offset + 7; + localparam ex1_s1_v_offset = exx_lq_act_offset + 3; + localparam ex1_s2_v_offset = ex1_s1_v_offset + 1; + localparam ex1_s3_v_offset = ex1_s2_v_offset + 1; + localparam ex1_gpr_s1_xu0_sel_offset = ex1_s3_v_offset + 1; + localparam ex1_gpr_s2_xu0_sel_offset = ex1_gpr_s1_xu0_sel_offset + 8*7; + localparam ex1_gpr_s1_xu1_sel_offset = ex1_gpr_s2_xu0_sel_offset + 8*7; + localparam ex1_gpr_s2_xu1_sel_offset = ex1_gpr_s1_xu1_sel_offset + 8*4; + localparam ex1_gpr_s1_lq_sel_offset = ex1_gpr_s2_xu1_sel_offset + 8*4; + localparam ex1_gpr_s2_lq_sel_offset = ex1_gpr_s1_lq_sel_offset + 8*4; + localparam ex1_gpr_s2_imm_sel_offset = ex1_gpr_s2_lq_sel_offset + 8*4; + localparam ex1_spr_s1_xu0_sel_offset = ex1_gpr_s2_imm_sel_offset + 8; + localparam ex1_spr_s1_xu1_sel_offset = ex1_spr_s1_xu0_sel_offset + 3*4; + localparam ex1_spr_s1_lq_sel_offset = ex1_spr_s1_xu1_sel_offset + 1*1; + localparam ex1_spr_s2_xu0_sel_offset = ex1_spr_s1_lq_sel_offset + 1*2; + localparam ex1_spr_s2_xu1_sel_offset = ex1_spr_s2_xu0_sel_offset + 6*4; + localparam ex1_spr_s2_lq_sel_offset = ex1_spr_s2_xu1_sel_offset + 2*1; + localparam ex1_spr_s3_xu0_sel_offset = ex1_spr_s2_lq_sel_offset + 1*2; + localparam ex1_spr_s3_xu1_sel_offset = ex1_spr_s3_xu0_sel_offset + 2*6; + localparam ex1_spr_s3_lq_sel_offset = ex1_spr_s3_xu1_sel_offset + 2*3; + localparam ex1_gpr_s1_rel_sel_offset = ex1_spr_s3_lq_sel_offset + 1*2; + localparam ex1_gpr_s2_rel_sel_offset = ex1_gpr_s1_rel_sel_offset + 8*2; + localparam ex1_gpr_s1_reg_sel_offset = ex1_gpr_s2_rel_sel_offset + 8*2; + localparam ex1_gpr_s2_reg_sel_offset = ex1_gpr_s1_reg_sel_offset + 8; + localparam ex1_spr_s1_reg_sel_offset = ex1_gpr_s2_reg_sel_offset + 8; + localparam ex1_spr_s2_reg_sel_offset = ex1_spr_s1_reg_sel_offset + 3; + localparam ex1_spr_s3_reg_sel_offset = ex1_spr_s2_reg_sel_offset + 6; + localparam ex1_abt_s1_lq_sel_offset = ex1_spr_s3_reg_sel_offset + 2; + localparam ex1_abt_s2_lq_sel_offset = ex1_abt_s1_lq_sel_offset + 1; + localparam ex1_abt_s3_lq_sel_offset = ex1_abt_s2_lq_sel_offset + 1; + localparam ex1_abt_s1_xu1_sel_offset = ex1_abt_s3_lq_sel_offset + 3; + localparam ex1_abt_s2_xu1_sel_offset = ex1_abt_s1_xu1_sel_offset + 2; + localparam ex1_abt_s3_xu1_sel_offset = ex1_abt_s2_xu1_sel_offset + 2; + localparam ex1_abt_s1_xu0_sel_offset = ex1_abt_s3_xu1_sel_offset + 2; + localparam ex1_abt_s2_xu0_sel_offset = ex1_abt_s1_xu0_sel_offset + 4; + localparam ex1_abt_s3_xu0_sel_offset = ex1_abt_s2_xu0_sel_offset + 4; + localparam ex2_is_mflr_offset = ex1_abt_s3_xu0_sel_offset + 4; + localparam ex2_is_mfxer_offset = ex2_is_mflr_offset + 1; + localparam ex2_is_mtxer_offset = ex2_is_mfxer_offset + 1; + localparam ex2_is_mfcr_sel_offset = ex2_is_mtxer_offset + 1; + localparam ex2_is_mfcr_offset = ex2_is_mfcr_sel_offset + 1; + localparam ex2_is_mtcr_offset = ex2_is_mfcr_offset + 8; + localparam ex2_is_mfctr_offset = ex2_is_mtcr_offset + 8; + localparam ex3_is_mtxer_offset = ex2_is_mfctr_offset + 1; + localparam ex4_xu0_rt_offset = ex3_is_mtxer_offset + 1; + localparam ex5_xu0_rt_offset = ex4_xu0_rt_offset + `GPR_WIDTH; + localparam ex6_xu0_rt_offset = ex5_xu0_rt_offset + `GPR_WIDTH; + localparam ex7_xu0_rt_offset = ex6_xu0_rt_offset + `GPR_WIDTH; + localparam ex8_xu0_rt_offset = ex7_xu0_rt_offset + `GPR_WIDTH; + localparam ex6_lq_rt_offset = ex8_xu0_rt_offset + `GPR_WIDTH; + localparam ex7_lq_rt_offset = ex6_lq_rt_offset + `GPR_WIDTH; + localparam ex8_lq_rt_offset = ex7_lq_rt_offset + `GPR_WIDTH; + localparam ex4_xu0_cr_offset = ex8_lq_rt_offset + `GPR_WIDTH; + localparam ex5_xu0_cr_offset = ex4_xu0_cr_offset + 4; + localparam ex6_xu0_cr_offset = ex5_xu0_cr_offset + 4; + localparam ex6_lq_cr_offset = ex6_xu0_cr_offset + 4; + localparam ex4_xu0_xer_offset = ex6_lq_cr_offset + 4; + localparam ex5_xu0_xer_offset = ex4_xu0_xer_offset + 10; + localparam ex6_xu0_xer_offset = ex5_xu0_xer_offset + 10; + localparam ex4_xu0_ctr_offset = ex6_xu0_xer_offset + 10; + localparam ex4_xu0_lr_offset = ex4_xu0_ctr_offset + `GPR_WIDTH; + localparam ex2_rs1_offset = ex4_xu0_lr_offset + `GPR_WIDTH; + localparam ex2_rs2_offset = ex2_rs1_offset + `GPR_WIDTH; + localparam ex2_cr1_offset = ex2_rs2_offset + `GPR_WIDTH; + localparam ex2_cr2_offset = ex2_cr1_offset + 4; + localparam ex2_cr3_offset = ex2_cr2_offset + 4; + localparam ex2_cr_bit_offset = ex2_cr3_offset + 4; + localparam ex2_xer2_offset = ex2_cr_bit_offset + 1; + localparam ex2_xer3_offset = ex2_xer2_offset + 10; + localparam ex3_xer3_offset = ex2_xer3_offset + 10; + localparam ex2_lr1_offset = ex3_xer3_offset + 1; + localparam ex2_lr2_offset = ex2_lr1_offset + `GPR_WIDTH; + localparam ex2_ctr2_offset = ex2_lr2_offset + `GPR_WIDTH; + localparam ex2_cr_sel_offset = ex2_ctr2_offset + `GPR_WIDTH; + localparam ex2_xer_sel_offset = ex2_cr_sel_offset + 2; + localparam ex3_rs1_offset = ex2_xer_sel_offset + 2; + localparam ex3_mfspr_sel_offset = ex3_rs1_offset + `GPR_WIDTH; + localparam ex3_mfspr_rt_offset = ex3_mfspr_sel_offset + 1; + localparam ord_rt_data_offset = ex3_mfspr_rt_offset + `GPR_WIDTH; + localparam ord_cr_data_offset = ord_rt_data_offset + `GPR_WIDTH; + localparam ord_xer_data_offset = ord_cr_data_offset + 4; + localparam ex2_rs_capt_offset = ord_xer_data_offset + 10; + localparam ex2_ra_capt_offset = ex2_rs_capt_offset + 1; + localparam ex3_ra_capt_offset = ex2_ra_capt_offset + 1; + localparam ex4_ra_capt_offset = ex3_ra_capt_offset + 1; + localparam ex2_rs2_noimm_offset = ex4_ra_capt_offset + 1; + localparam ex3_mtcr_offset = ex2_rs2_noimm_offset + 12; + localparam ex3_mtcr_sel_offset = ex3_mtcr_offset + 4; + localparam mm_rs_is_offset = ex3_mtcr_sel_offset + 1; + localparam mm_ra_entry_offset = mm_rs_is_offset + 9; + localparam mm_data_offset = mm_ra_entry_offset + 12; + localparam ex3_cnt_rt_offset = mm_data_offset + `GPR_WIDTH; + localparam ex3_prm_rt_offset = ex3_cnt_rt_offset + 7; + localparam ex3_dlm_rt_offset = ex3_prm_rt_offset + 8; + localparam ex3_dlm_xer_offset = ex3_dlm_rt_offset + 4; + localparam ex3_dlm_cr_offset = ex3_dlm_xer_offset + 10; + localparam ex6_mul_ord_done_offset = ex3_dlm_cr_offset + 4; + localparam ex6_mul_abort_offset = ex6_mul_ord_done_offset + 1; + localparam ex6_mul_done_offset = ex6_mul_abort_offset + 1; + localparam exx_xu0_abort_offset = ex6_mul_done_offset + 9; + localparam exx_xu1_abort_offset = exx_xu0_abort_offset + 11; + localparam exx_lq_abort_offset = exx_xu1_abort_offset + 5; + localparam ex2_rs1_abort_offset = exx_lq_abort_offset + 4; + localparam ex2_rs2_abort_offset = ex2_rs1_abort_offset + 1; + localparam ex2_rs3_abort_offset = ex2_rs2_abort_offset + 1; + localparam exx_rel3_act_offset = ex2_rs3_abort_offset + 1; + localparam exx_rel3_rt_offset = exx_rel3_act_offset + 1; + localparam exx_rel4_rt_offset = exx_rel3_rt_offset + `GPR_WIDTH; + localparam scan_right = exx_rel4_rt_offset + `GPR_WIDTH; + wire [0:scan_right-1] siv; + wire [0:scan_right-1] sov; + (* analysis_not_referenced="<8:63>true" *) + wire [0:63] tidn = 64'b0; + // Signals + wire [0:8-1] exx_xu0_act; + wire [5:9-1] exx_lq_act; + wire ex0_gpr_s1_reg_sel; + wire ex0_spr_s1_reg_sel; + wire ex0_gpr_s2_reg_sel; + wire ex0_spr_s2_reg_sel; + wire ex0_spr_s3_reg_sel; + wire [1:11] ex0_gpr_s1_xu0_sel; + wire [1:11] ex0_gpr_s2_xu0_sel; + wire [1:6] ex0_gpr_s1_xu1_sel; + wire [1:6] ex0_gpr_s2_xu1_sel; + wire [4:8] ex0_gpr_s1_lq_sel; + wire [4:8] ex0_gpr_s2_lq_sel; + wire [2:3] ex0_gpr_s1_rel_sel; + wire [2:3] ex0_gpr_s2_rel_sel; + wire ex0_gpr_rs1_sel_zero_b; + wire ord_sel_slowspr; + wire ord_sel_ones; + wire ord_data_act; + wire [0:3] iu_ord_cr; + wire [0:3] lq_ord_cr; + wire [0:3] mm_ord_cr; + wire [0:3] ex2_cr; + wire [0:9] ex2_xer; + wire [64-`GPR_WIDTH:63] ex2_mfcr_rt; + wire [64-`GPR_WIDTH:63] ex2_mfxer_rt; + wire [0:3] ex3_alu2_cr; + wire [64-`GPR_WIDTH:63] ex1_rs2_noimm; + wire [8-`GPR_WIDTH/8:7] ex6_parity; + wire [0:9] ex3_mtxer; + wire [0:3] ex6_xu0_cr; + wire [0:9] ex6_xu0_xer; + wire [64-`GPR_WIDTH:63] ex3_cnt_rt; + wire [64-`GPR_WIDTH:63] ex3_prm_rt; + wire [64-`GPR_WIDTH:63] ex3_dlm_rt; + wire [0:3] ex3_xu0_cr2, ex3_xu0_cr3; + wire [0:3] ex3_cnt_cr; + wire ex3_cnt_zero; + wire [64-`GPR_WIDTH:63] ex3_xu0_rt_nobyp2; + wire [64-`GPR_WIDTH:63] ex3_xu0_rt_nobyp3; + wire [64-`GPR_WIDTH:63] ex3_xu0_rt_nobyp4; + wire [64-`GPR_WIDTH:63] ex3_xu0_rt_nobyp5; + wire [0:9] ex3_xu0_xer; + wire ex2_mfspr_act; + wire ex3_xu0_lr_act; + wire ex3_xu0_ctr_act; + wire ex0_xu0_ivax_act; + wire ex1_xu0_ivax_act; + wire [0:31] xu0_iu_bta_int; + wire ex1_abort; + wire ex1_rs1_abort, ex1_rs2_noimm_abort; + wire ex1_rs2_abort; + wire ex1_rs3_abort; + wire ex6_xu0_abort; + + //<> Check XU0 vs XU1 everywhere (incl. clock gates, esp. muxes) + + //------------------------------------------------------------------------------------------ + // Zero/Immediate Logic for GPRs + //------------------------------------------------------------------------------------------ + assign ex0_gpr_s1_xu0_sel = ex0_gpr_rs1_sel_zero_b==1'b1 ? rv_xu0_s1_fxu0_sel : tidn[1:11]; + assign ex0_gpr_s1_xu1_sel = ex0_gpr_rs1_sel_zero_b==1'b1 ? rv_xu0_s1_fxu1_sel : tidn[1:6]; + assign ex0_gpr_s1_lq_sel = ex0_gpr_rs1_sel_zero_b==1'b1 ? rv_xu0_s1_lq_sel : tidn[4:8]; + assign ex0_gpr_s1_rel_sel = ex0_gpr_rs1_sel_zero_b==1'b1 ? rv_xu0_s1_rel_sel : tidn[2:3]; + + assign ex0_gpr_s2_xu0_sel = rv_xu0_s2_fxu0_sel; + assign ex0_gpr_s2_xu1_sel = rv_xu0_s2_fxu1_sel; + assign ex0_gpr_s2_lq_sel = rv_xu0_s2_lq_sel; + assign ex0_gpr_s2_rel_sel = rv_xu0_s2_rel_sel; + + // TEMP Hopefully fold this into rf_byp + assign ex0_gpr_s1_reg_sel = ~|rv_xu0_s1_fxu0_sel[1:7] & ~|rv_xu0_s1_fxu1_sel[1:4] & ~|rv_xu0_s1_lq_sel[4:7] & ~|rv_xu0_s1_rel_sel & ex0_gpr_rs1_sel_zero_b; + assign ex0_gpr_s2_reg_sel = ~|rv_xu0_s2_fxu0_sel[1:7] & ~|rv_xu0_s2_fxu1_sel[1:4] & ~|rv_xu0_s2_lq_sel[4:7] & ~|rv_xu0_s2_rel_sel; + assign ex0_spr_s1_reg_sel = ~|rv_xu0_s1_fxu0_sel[2:5] & ~|rv_xu0_s1_fxu1_sel[2:2] & ~|rv_xu0_s1_lq_sel[4:5]; + assign ex0_spr_s2_reg_sel = ~|rv_xu0_s2_fxu0_sel[2:5] & ~|rv_xu0_s2_fxu1_sel[2:2] & ~|rv_xu0_s2_lq_sel[4:5]; + assign ex0_spr_s3_reg_sel = ~|rv_xu0_s3_fxu0_sel[2:5] & ~|rv_xu0_s3_fxu1_sel[2:2] & ~|rv_xu0_s3_lq_sel[4:5]; + + assign ex0_gpr_rs1_sel_zero_b = ~dec_byp_ex0_rs1_sel_zero; + + //------------------------------------------------------------------------------------------ + // GPR Bypass + //------------------------------------------------------------------------------------------ + assign ex1_rs1 = (alu_byp_ex2_add_rt & fanout(ex1_gpr_s1_xu0_sel_q[2], `GPR_WIDTH)) | + (ex3_xu0_rt_nobyp & fanout(ex1_gpr_s1_xu0_sel_q[3], `GPR_WIDTH)) | + (ex4_xu0_rt_q & fanout(ex1_gpr_s1_xu0_sel_q[4], `GPR_WIDTH)) | + (ex5_xu0_rt_q & fanout(ex1_gpr_s1_xu0_sel_q[5], `GPR_WIDTH)) | + (ex6_xu0_rt & fanout(ex1_gpr_s1_xu0_sel_q[6], `GPR_WIDTH)) | + (ex7_xu0_rt_q & fanout(ex1_gpr_s1_xu0_sel_q[7], `GPR_WIDTH)) | + (ex8_xu0_rt_q & fanout(ex1_gpr_s1_xu0_sel_q[8], `GPR_WIDTH)) | + (xu1_xu0_ex2_rt & fanout(ex1_gpr_s1_xu1_sel_q[2], `GPR_WIDTH)) | + (xu1_xu0_ex3_rt & fanout(ex1_gpr_s1_xu1_sel_q[3], `GPR_WIDTH)) | + (xu1_xu0_ex4_rt & fanout(ex1_gpr_s1_xu1_sel_q[4], `GPR_WIDTH)) | + (xu1_xu0_ex5_rt & fanout(ex1_gpr_s1_xu1_sel_q[5], `GPR_WIDTH)) | + (lq_xu_ex5_rt & fanout(ex1_gpr_s1_lq_sel_q[5], `GPR_WIDTH)) | + (ex6_lq_rt_q & fanout(ex1_gpr_s1_lq_sel_q[6], `GPR_WIDTH)) | + (ex7_lq_rt_q & fanout(ex1_gpr_s1_lq_sel_q[7], `GPR_WIDTH)) | + (ex8_lq_rt_q & fanout(ex1_gpr_s1_lq_sel_q[8], `GPR_WIDTH)) | + (exx_rel3_rt_q & fanout(ex1_gpr_s1_rel_sel_q[3], `GPR_WIDTH)) | + (exx_rel4_rt_q & fanout(ex1_gpr_s1_rel_sel_q[4], `GPR_WIDTH)) | + (gpr_xu0_ex1_r1d & fanout(ex1_gpr_s1_reg_sel_q[0:7], `GPR_WIDTH)); + + assign ex1_rs2 = (dec_byp_ex1_imm & fanout(ex1_gpr_s2_imm_sel_q, `GPR_WIDTH)) | + (ex1_rs2_noimm & ~fanout(ex1_gpr_s2_imm_sel_q, `GPR_WIDTH)); + + assign ex1_rs2_noimm = + (alu_byp_ex2_add_rt & fanout(ex1_gpr_s2_xu0_sel_q[2], `GPR_WIDTH)) | + (ex3_xu0_rt_nobyp & fanout(ex1_gpr_s2_xu0_sel_q[3], `GPR_WIDTH)) | + (ex4_xu0_rt_q & fanout(ex1_gpr_s2_xu0_sel_q[4], `GPR_WIDTH)) | + (ex5_xu0_rt_q & fanout(ex1_gpr_s2_xu0_sel_q[5], `GPR_WIDTH)) | + (ex6_xu0_rt & fanout(ex1_gpr_s2_xu0_sel_q[6], `GPR_WIDTH)) | + (ex7_xu0_rt_q & fanout(ex1_gpr_s2_xu0_sel_q[7], `GPR_WIDTH)) | + (ex8_xu0_rt_q & fanout(ex1_gpr_s2_xu0_sel_q[8], `GPR_WIDTH)) | + (xu1_xu0_ex2_rt & fanout(ex1_gpr_s2_xu1_sel_q[2], `GPR_WIDTH)) | + (xu1_xu0_ex3_rt & fanout(ex1_gpr_s2_xu1_sel_q[3], `GPR_WIDTH)) | + (xu1_xu0_ex4_rt & fanout(ex1_gpr_s2_xu1_sel_q[4], `GPR_WIDTH)) | + (xu1_xu0_ex5_rt & fanout(ex1_gpr_s2_xu1_sel_q[5], `GPR_WIDTH)) | + (lq_xu_ex5_rt & fanout(ex1_gpr_s2_lq_sel_q[5], `GPR_WIDTH)) | + (ex6_lq_rt_q & fanout(ex1_gpr_s2_lq_sel_q[6], `GPR_WIDTH)) | + (ex7_lq_rt_q & fanout(ex1_gpr_s2_lq_sel_q[7], `GPR_WIDTH)) | + (ex8_lq_rt_q & fanout(ex1_gpr_s2_lq_sel_q[8], `GPR_WIDTH)) | + (exx_rel3_rt_q & fanout(ex1_gpr_s2_rel_sel_q[3], `GPR_WIDTH)) | + (exx_rel4_rt_q & fanout(ex1_gpr_s2_rel_sel_q[4], `GPR_WIDTH)) | + (gpr_xu0_ex1_r2d & fanout(ex1_gpr_s2_reg_sel_q[0:7], `GPR_WIDTH)); + + //------------------------------------------------------------------------------------------ + // Abort Bypass + //------------------------------------------------------------------------------------------ + assign ex6_xu0_abort = (exx_xu0_abort_q[6] & ~ex6_mul_done_q[8]) | + (ex6_mul_abort_q & ex6_mul_done_q[8]) ; + + assign exx_xu0_abort_d[2:6] = {ex1_abort, exx_xu0_abort_q[2:5]}; + assign exx_xu0_abort_d[7] = ex6_xu0_abort; + assign exx_xu0_abort_d[8:12] = exx_xu0_abort_q[7:11]; + + assign exx_xu1_abort_d = {xu1_xu0_ex2_abort, exx_xu1_abort_q[3:6]}; + assign exx_lq_abort_d = {lq_xu_ex5_abort, exx_lq_abort_q[6:8]}; + + assign ex1_abort = ex1_rs1_abort | ex1_rs2_abort | ex1_rs3_abort; + + assign ex1_rs1_abort = exx_xu0_act[1] & ex1_s1_v_q & + ((exx_xu0_abort_q[2] & ex1_gpr_s1_xu0_sel_q[2][0]) | + (exx_xu0_abort_q[3] & ex1_gpr_s1_xu0_sel_q[3][0]) | + (exx_xu0_abort_q[4] & ex1_gpr_s1_xu0_sel_q[4][0]) | + (exx_xu0_abort_q[5] & ex1_gpr_s1_xu0_sel_q[5][0]) | + (ex6_xu0_abort & ex1_gpr_s1_xu0_sel_q[6][0]) | //mul abort + (exx_xu0_abort_q[7] & ex1_gpr_s1_xu0_sel_q[7][0]) | + (exx_xu0_abort_q[8] & ex1_gpr_s1_xu0_sel_q[8][0]) | + (exx_xu0_abort_q[9] & ex1_abt_s1_xu0_sel_q[9] ) | + (exx_xu0_abort_q[10] & ex1_abt_s1_xu0_sel_q[10] ) | + (exx_xu0_abort_q[11] & ex1_abt_s1_xu0_sel_q[11] ) | + (exx_xu0_abort_q[12] & ex1_abt_s1_xu0_sel_q[12] ) | + (xu1_xu0_ex2_abort & ex1_gpr_s1_xu1_sel_q[2][0]) | + (exx_xu1_abort_q[3] & ex1_gpr_s1_xu1_sel_q[3][0]) | + (exx_xu1_abort_q[4] & ex1_gpr_s1_xu1_sel_q[4][0]) | + (exx_xu1_abort_q[5] & ex1_gpr_s1_xu1_sel_q[5][0]) | + (exx_xu1_abort_q[6] & ex1_abt_s1_xu1_sel_q[6]) | + (exx_xu1_abort_q[7] & ex1_abt_s1_xu1_sel_q[7]) | + (lq_xu_ex5_abort & ex1_gpr_s1_lq_sel_q[5][0]) | + (exx_lq_abort_q[6] & ex1_gpr_s1_lq_sel_q[6][0]) | + (exx_lq_abort_q[7] & ex1_gpr_s1_lq_sel_q[7][0]) | + (exx_lq_abort_q[8] & ex1_gpr_s1_lq_sel_q[8][0]) | + (exx_lq_abort_q[9] & ex1_abt_s1_lq_sel_q[9]) | + (1'b0 & ex1_gpr_s1_reg_sel_q[0])); + + assign ex1_rs2_abort = exx_xu0_act[1] & ex1_s2_v_q & + (ex1_rs2_noimm_abort ); + + assign ex1_rs2_noimm_abort = + ((exx_xu0_abort_q[2] & ex1_gpr_s2_xu0_sel_q[2][0]) | + (exx_xu0_abort_q[3] & ex1_gpr_s2_xu0_sel_q[3][0]) | + (exx_xu0_abort_q[4] & ex1_gpr_s2_xu0_sel_q[4][0]) | + (exx_xu0_abort_q[5] & ex1_gpr_s2_xu0_sel_q[5][0]) | + (ex6_xu0_abort & ex1_gpr_s2_xu0_sel_q[6][0]) | + (exx_xu0_abort_q[7] & ex1_gpr_s2_xu0_sel_q[7][0]) | + (exx_xu0_abort_q[8] & ex1_gpr_s2_xu0_sel_q[8][0]) | + (exx_xu0_abort_q[9] & ex1_abt_s2_xu0_sel_q[9] ) | + (exx_xu0_abort_q[10] & ex1_abt_s2_xu0_sel_q[10] ) | + (exx_xu0_abort_q[11] & ex1_abt_s2_xu0_sel_q[11] ) | + (exx_xu0_abort_q[12] & ex1_abt_s2_xu0_sel_q[12] ) | + (xu1_xu0_ex2_abort & ex1_gpr_s2_xu1_sel_q[2][0]) | + (exx_xu1_abort_q[3] & ex1_gpr_s2_xu1_sel_q[3][0]) | + (exx_xu1_abort_q[4] & ex1_gpr_s2_xu1_sel_q[4][0]) | + (exx_xu1_abort_q[5] & ex1_gpr_s2_xu1_sel_q[5][0]) | + (exx_xu1_abort_q[6] & ex1_abt_s2_xu1_sel_q[6]) | + (exx_xu1_abort_q[7] & ex1_abt_s2_xu1_sel_q[7]) | + (lq_xu_ex5_abort & ex1_gpr_s2_lq_sel_q[5][0]) | + (exx_lq_abort_q[6] & ex1_gpr_s2_lq_sel_q[6][0]) | + (exx_lq_abort_q[7] & ex1_gpr_s2_lq_sel_q[7][0]) | + (exx_lq_abort_q[8] & ex1_gpr_s2_lq_sel_q[8][0]) | + (exx_lq_abort_q[9] & ex1_abt_s2_lq_sel_q[9])); + + + assign ex1_rs3_abort = exx_xu0_act[1] & ex1_s3_v_q & + ((exx_xu0_abort_q[3] & ex1_spr_s3_xu0_sel_q[3][0]) | + (exx_xu0_abort_q[4] & ex1_spr_s3_xu0_sel_q[4][0]) | + (exx_xu0_abort_q[5] & ex1_spr_s3_xu0_sel_q[5][0]) | + (ex6_xu0_abort & ex1_spr_s3_xu0_sel_q[6][0]) | + (exx_xu0_abort_q[7] & ex1_spr_s3_xu0_sel_q[7][0]) | + (exx_xu0_abort_q[8] & ex1_spr_s3_xu0_sel_q[8][0]) | + (exx_xu0_abort_q[9] & ex1_abt_s3_xu0_sel_q[9] ) | + (exx_xu0_abort_q[10] & ex1_abt_s3_xu0_sel_q[10] ) | + (exx_xu0_abort_q[11] & ex1_abt_s3_xu0_sel_q[11] ) | + (exx_xu0_abort_q[12] & ex1_abt_s3_xu0_sel_q[12] ) | + (exx_xu1_abort_q[3] & ex1_spr_s3_xu1_sel_q[3][0]) | + (exx_xu1_abort_q[4] & ex1_spr_s3_xu1_sel_q[4][0]) | + (exx_xu1_abort_q[5] & ex1_spr_s3_xu1_sel_q[5][0]) | + (exx_xu1_abort_q[6] & ex1_abt_s3_xu1_sel_q[6]) | + (exx_xu1_abort_q[7] & ex1_abt_s3_xu1_sel_q[7]) | + (lq_xu_ex5_abort & ex1_spr_s3_lq_sel_q[5][0]) | + (exx_lq_abort_q[6] & ex1_spr_s3_lq_sel_q[6][0]) | + (exx_lq_abort_q[7] & ex1_abt_s3_lq_sel_q[7]) | + (exx_lq_abort_q[8] & ex1_abt_s3_lq_sel_q[8]) | + (exx_lq_abort_q[9] & ex1_abt_s3_lq_sel_q[9])); + + //------------------------------------------------------------------------------------------ + // CR Bypass + //------------------------------------------------------------------------------------------ + assign ex1_cr1 = + (ex3_xu0_cr & {4{ex1_spr_s1_xu0_sel_q[3][0]}}) | + (ex4_xu0_cr_q & {4{ex1_spr_s1_xu0_sel_q[4][0]}}) | + (ex5_xu0_cr_q & {4{ex1_spr_s1_xu0_sel_q[5][0]}}) | + (ex6_xu0_cr & {4{ex1_spr_s1_xu0_sel_q[6][0]}}) | + (xu1_xu0_ex3_cr & {4{ex1_spr_s1_xu1_sel_q[3][0]}}) | + (lq_xu_ex5_cr & {4{ex1_spr_s1_lq_sel_q[5][0]}}) | + (ex6_lq_cr_q & {4{ex1_spr_s1_lq_sel_q[6][0]}}) | + (cr_xu0_ex1_r1d & {4{ex1_spr_s1_reg_sel_q[0]}}); + + assign ex1_cr2 = + (ex3_xu0_cr & {4{ex1_spr_s2_xu0_sel_q[3][0]}}) | + (ex4_xu0_cr_q & {4{ex1_spr_s2_xu0_sel_q[4][0]}}) | + (ex5_xu0_cr_q & {4{ex1_spr_s2_xu0_sel_q[5][0]}}) | + (ex6_xu0_cr & {4{ex1_spr_s2_xu0_sel_q[6][0]}}) | + (xu1_xu0_ex3_cr & {4{ex1_spr_s2_xu1_sel_q[3][0]}}) | + (lq_xu_ex5_cr & {4{ex1_spr_s2_lq_sel_q[5][0]}}) | + (ex6_lq_cr_q & {4{ex1_spr_s2_lq_sel_q[6][0]}}) | + (cr_xu0_ex1_r2d & {4{ex1_spr_s2_reg_sel_q[0]}}); + + assign ex1_cr3 = + (ex3_xu0_cr & {4{ex1_spr_s3_xu0_sel_q[3][0]}}) | + (ex4_xu0_cr_q & {4{ex1_spr_s3_xu0_sel_q[4][0]}}) | + (ex5_xu0_cr_q & {4{ex1_spr_s3_xu0_sel_q[5][0]}}) | + (ex6_xu0_cr & {4{ex1_spr_s3_xu0_sel_q[6][0]}}) | + (xu1_xu0_ex3_cr & {4{ex1_spr_s3_xu1_sel_q[3][0]}}) | + (lq_xu_ex5_cr & {4{ex1_spr_s3_lq_sel_q[5][0]}}) | + (ex6_lq_cr_q & {4{ex1_spr_s3_lq_sel_q[6][0]}}) | + (cr_xu0_ex1_r3d & {4{ex1_spr_s3_reg_sel_q[0]}}); + + assign ex1_cr_bit = (dec_byp_ex1_instr[24:25] == 2'b11) ? ex1_cr3[3] : + (dec_byp_ex1_instr[24:25] == 2'b10) ? ex1_cr3[2] : + (dec_byp_ex1_instr[24:25] == 2'b01) ? ex1_cr3[1] : + ex1_cr3[0]; + + assign ex2_cr = + (ex2_cr2_q & {4{ex2_cr_sel_q[2]}}) | + (ex2_cr3_q & {4{ex2_cr_sel_q[3]}}); + + //------------------------------------------------------------------------------------------ + // XER Bypass + //------------------------------------------------------------------------------------------ + assign ex1_xer2 = + (ex3_xu0_xer2 & {10{ex1_spr_s2_xu0_sel_q[3][1]}}) | + (ex4_xu0_xer_q & {10{ex1_spr_s2_xu0_sel_q[4][1]}}) | + (ex5_xu0_xer_q & {10{ex1_spr_s2_xu0_sel_q[5][1]}}) | + (ex6_xu0_xer & {10{ex1_spr_s2_xu0_sel_q[6][1]}}) | + (xu1_xu0_ex3_xer & {10{ex1_spr_s2_xu1_sel_q[3][1]}}) | + (xer_xu0_ex1_r2d & {10{ex1_spr_s2_reg_sel_q[1]}}); + + assign ex1_xer3 = + (ex3_xu0_xer2 & {10{ex1_spr_s3_xu0_sel_q[3][1]}}) | + (ex4_xu0_xer_q & {10{ex1_spr_s3_xu0_sel_q[4][1]}}) | + (ex5_xu0_xer_q & {10{ex1_spr_s3_xu0_sel_q[5][1]}}) | + (ex6_xu0_xer & {10{ex1_spr_s3_xu0_sel_q[6][1]}}) | + (xu1_xu0_ex3_xer & {10{ex1_spr_s3_xu1_sel_q[3][1]}}) | + (xer_xu0_ex1_r3d & {10{ex1_spr_s3_reg_sel_q[1]}}); + + assign ex2_xer = + (ex2_xer2_q & {10{ex2_xer_sel_q[2]}}) | + (ex2_xer3_q & {10{ex2_xer_sel_q[3]}}); + + //------------------------------------------------------------------------------------------ + // LR Bypass + //------------------------------------------------------------------------------------------ + assign ex1_lr1 = + (ex3_xu0_lr & fanout2(ex1_spr_s1_xu0_sel_q[3][1:2], `GPR_WIDTH)) | + (ex4_xu0_lr_q & fanout2(ex1_spr_s1_xu0_sel_q[4][1:2], `GPR_WIDTH)) | + (lr_xu0_ex1_r1d & fanout2(ex1_spr_s1_xu0_sel_q[5][1:2], `GPR_WIDTH)) | + (lr_xu0_ex1_r1d & fanout2(ex1_spr_s1_xu0_sel_q[6][1:2], `GPR_WIDTH)) | + (lr_xu0_ex1_r1d & fanout2(ex1_spr_s1_reg_sel_q[1:2], `GPR_WIDTH)); + + assign ex1_lr2 = + (ex3_xu0_lr & fanout2(ex1_spr_s2_xu0_sel_q[3][2:3], `GPR_WIDTH)) | + (ex4_xu0_lr_q & fanout2(ex1_spr_s2_xu0_sel_q[4][2:3], `GPR_WIDTH)) | + (lr_xu0_ex1_r2d & fanout2(ex1_spr_s2_xu0_sel_q[5][2:3], `GPR_WIDTH)) | + (lr_xu0_ex1_r2d & fanout2(ex1_spr_s2_xu0_sel_q[6][2:3], `GPR_WIDTH)) | + (lr_xu0_ex1_r2d & fanout2(ex1_spr_s2_reg_sel_q[2:3], `GPR_WIDTH)); + + //------------------------------------------------------------------------------------------ + // CTR Bypass + //------------------------------------------------------------------------------------------ + assign ex1_ctr2 = + (ex3_xu0_ctr & fanout2(ex1_spr_s2_xu0_sel_q[3][4:5], `GPR_WIDTH)) | + (ex4_xu0_ctr_q & fanout2(ex1_spr_s2_xu0_sel_q[4][4:5], `GPR_WIDTH)) | + (ctr_xu0_ex1_r2d & fanout2(ex1_spr_s2_xu0_sel_q[5][4:5], `GPR_WIDTH)) | + (ctr_xu0_ex1_r2d & fanout2(ex1_spr_s2_xu0_sel_q[6][4:5], `GPR_WIDTH)) | + (ctr_xu0_ex1_r2d & fanout2(ex1_spr_s2_reg_sel_q[4:5], `GPR_WIDTH)); + + //------------------------------------------------------------------------------------------ + // Ordered Data + //------------------------------------------------------------------------------------------ + assign ord_sel_slowspr = xu_slowspr_val_in & xu_slowspr_rw_in & xu_slowspr_done_in; + assign ord_sel_ones = xu_slowspr_val_in & xu_slowspr_rw_in & ~xu_slowspr_done_in; + + assign iu_ord_cr = {2'b0, iu_xu_ex5_data[51], 1'b0}; + assign lq_ord_cr = {2'b0, lq_xu_ex5_data[51], 1'b0}; + assign mm_ord_cr = {2'b0, mm_xu_cr0_eq, 1'b0}; + + assign ord_data_act = ord_sel_ones | + ord_sel_slowspr | + spr_xu_ord_write_done | + iu_xu_ord_write_done | + lq_xu_ord_write_done | + div_byp_ex4_done | + ex6_mul_ord_done_q[0] | + dec_byp_ex3_mtiar | + mm_xu_cr0_eq_valid; + + assign ord_rt_data_d = {`GPR_WIDTH{ord_sel_ones}} | + (xu_slowspr_data_in & {`GPR_WIDTH{ord_sel_slowspr}}) | + (spr_xu_ex4_rd_data & {`GPR_WIDTH{spr_xu_ord_write_done}}) | + (iu_xu_ex5_data & {`GPR_WIDTH{iu_xu_ord_write_done}}) | + (lq_xu_ex5_data & {`GPR_WIDTH{lq_xu_ord_write_done}}) | + (div_byp_ex4_rt & {`GPR_WIDTH{div_byp_ex4_done}}) | + (mul_byp_ex6_rt & {`GPR_WIDTH{ex6_mul_ord_done_q[0]}}) | + (alu_byp_ex3_rt & {`GPR_WIDTH{dec_byp_ex3_mtiar}}); + + assign ord_cr_data_d = + (div_byp_ex4_cr & {4{div_byp_ex4_done}}) | + (mul_byp_ex6_cr & {4{ex6_mul_ord_done_q[0]}}) | + (iu_ord_cr & {4{iu_xu_ord_write_done}}) | + (lq_ord_cr & {4{lq_xu_ord_write_done}}) | + (mm_ord_cr & {4{mm_xu_cr0_eq_valid}}); + + assign ord_xer_data_d = + (div_byp_ex4_xer & {10{div_byp_ex4_done}}) | + (mul_byp_ex6_xer & {10{ex6_mul_ord_done_q[0]}}); + + //------------------------------------------------------------------------------------------ + // EX2 Pipeline Muxing + //------------------------------------------------------------------------------------------ + generate + if (`GPR_WIDTH > 32) + begin : pad64 + assign ex2_mfcr_rt[64-`GPR_WIDTH:31] = {32{1'b0}}; + assign ex2_mfxer_rt[64-`GPR_WIDTH:31] = {32{1'b0}}; + end + endgenerate + + assign ex2_mfcr_rt[32:63] = { (ex2_cr & {4{ex2_is_mfcr_q[0]}}), + (ex2_cr & {4{ex2_is_mfcr_q[1]}}), + (ex2_cr & {4{ex2_is_mfcr_q[2]}}), + (ex2_cr & {4{ex2_is_mfcr_q[3]}}), + (ex2_cr & {4{ex2_is_mfcr_q[4]}}), + (ex2_cr & {4{ex2_is_mfcr_q[5]}}), + (ex2_cr & {4{ex2_is_mfcr_q[6]}}), + (ex2_cr & {4{ex2_is_mfcr_q[7]}})}; + + assign ex2_mfxer_rt[32:63] = {ex2_xer[0:2], 20'h00000, 2'b00, ex2_xer[3:9]}; + + assign ex2_mfspr_rt = ex2_mfcr_rt | + (ex2_mfxer_rt & {`GPR_WIDTH{ex2_is_mfxer_q}}) | + (ex2_lr1_q & {`GPR_WIDTH{ex2_is_mflr_q}}) | + (ex2_ctr2_q & {`GPR_WIDTH{ex2_is_mfctr_q}}); + + assign ex2_mfspr_sel = ex2_is_mfcr_sel_q | ex2_is_mfxer_q | ex2_is_mflr_q | ex2_is_mfctr_q; + assign ex2_mfspr_act = exx_xu0_act[2] & ex2_mfspr_sel; + + //------------------------------------------------------------------------------------------ + // EX3 Pipeline Muxing + //------------------------------------------------------------------------------------------ + assign ex3_cnt_zero = ~|ex3_cnt_rt_q; + + assign ex3_cnt_cr = {1'b0, ~ex3_cnt_zero, ex3_cnt_zero, ex3_xer3_q[0]}; + + assign ex3_cnt_rt = {57'b0, ex3_cnt_rt_q}; + assign ex3_prm_rt = {56'b0, ex3_prm_rt_q}; + assign ex3_dlm_rt = {60'b0, ex3_dlm_rt_q}; + + assign ex2_mtcr_sel = |ex2_is_mtcr_q; + + assign ex3_mtxer = {ex3_rs1_q[32:34], ex3_rs1_q[57:63]}; + + assign ex2_mtcr = + (ex2_rs1_q[32:35] & {4{ex2_is_mtcr_q[0]}}) | + (ex2_rs1_q[36:39] & {4{ex2_is_mtcr_q[1]}}) | + (ex2_rs1_q[40:43] & {4{ex2_is_mtcr_q[2]}}) | + (ex2_rs1_q[44:47] & {4{ex2_is_mtcr_q[3]}}) | + (ex2_rs1_q[48:51] & {4{ex2_is_mtcr_q[4]}}) | + (ex2_rs1_q[52:55] & {4{ex2_is_mtcr_q[5]}}) | + (ex2_rs1_q[56:59] & {4{ex2_is_mtcr_q[6]}}) | + (ex2_rs1_q[60:63] & {4{ex2_is_mtcr_q[7]}}); + + assign ex3_xu0_rt_nobyp5 = + (alu_byp_ex3_rt & ~{`GPR_WIDTH{ex3_mfspr_sel_q}}) | + (ex3_mfspr_rt_q & {`GPR_WIDTH{ex3_mfspr_sel_q}}); + + assign ex3_xu0_rt_nobyp4 = + (ex3_xu0_rt_nobyp5 & ~{`GPR_WIDTH{dec_byp_ex3_dlm_done}}) | + (ex3_dlm_rt & {`GPR_WIDTH{dec_byp_ex3_dlm_done}}); + + assign ex3_xu0_rt_nobyp3 = + (ex3_xu0_rt_nobyp4 & ~{`GPR_WIDTH{dec_byp_ex3_cnt_done}}) | + (ex3_cnt_rt & {`GPR_WIDTH{dec_byp_ex3_cnt_done}}); + + assign ex3_xu0_rt_nobyp2 = + (ex3_xu0_rt_nobyp3 & ~{`GPR_WIDTH{bcd_byp_ex3_done}}) | + (bcd_byp_ex3_rt & {`GPR_WIDTH{bcd_byp_ex3_done}}); + + assign ex3_xu0_rt_nobyp = + (ex3_xu0_rt_nobyp2 & ~{`GPR_WIDTH{dec_byp_ex3_prm_done}}) | + (ex3_prm_rt & {`GPR_WIDTH{dec_byp_ex3_prm_done}}); + + assign ex3_xu0_lr = + (br_byp_ex3_lr_wd & {`GPR_WIDTH{br_byp_ex3_lr_we}}) | + (ex3_rs1_q & ~{`GPR_WIDTH{br_byp_ex3_lr_we}}); + + assign ex3_xu0_ctr = + (br_byp_ex3_ctr_wd & {`GPR_WIDTH{br_byp_ex3_ctr_we}}) | + (ex3_rs1_q & ~{`GPR_WIDTH{br_byp_ex3_ctr_we}}); + + assign ex3_xu0_lr_act = exx_xu0_act[3] & (br_byp_ex3_lr_we | dec_byp_ex3_is_mtspr); + assign ex3_xu0_ctr_act = exx_xu0_act[3] & (br_byp_ex3_ctr_we | dec_byp_ex3_is_mtspr); + + assign ex3_alu2_cr = ex3_mtcr_sel_q == 1'b1 ? ex3_mtcr_q : alu_byp_ex3_cr; + assign ex3_xu0_xer = ex3_is_mtxer_q == 1'b1 ? ex3_mtxer : alu_byp_ex3_xer; + assign ex3_xu0_xer2 = dec_byp_ex3_dlm_done == 1'b1 ? ex3_dlm_xer_q : ex3_xu0_xer; + + assign ex3_xu0_cr3 = br_byp_ex3_cr_we == 1'b1 ? br_byp_ex3_cr_wd : ex3_alu2_cr; + assign ex3_xu0_cr2 = dec_byp_ex3_dlm_done == 1'b1 ? ex3_dlm_cr_q : ex3_xu0_cr3; + assign ex3_xu0_cr = dec_byp_ex3_cnt_done == 1'b1 ? ex3_cnt_cr : ex3_xu0_cr2; + + //------------------------------------------------------------------------------------------ + // EX4 Pipeline Muxing + //------------------------------------------------------------------------------------------ + + assign ex4_xu0_rt_nobyp = + (ex4_xu0_rt_q & ~{`GPR_WIDTH{dec_byp_ex4_pop_done}}) | + (pop_byp_ex4_rt & {`GPR_WIDTH{dec_byp_ex4_pop_done}}); + + //------------------------------------------------------------------------------------------ + // EX5 Pipeline Muxing + //------------------------------------------------------------------------------------------ + assign ex5_xu0_rt = + (ex5_xu0_rt_q & ~{`GPR_WIDTH{dec_byp_ex5_ord_sel}}) | + (ord_rt_data_q & {`GPR_WIDTH{dec_byp_ex5_ord_sel}}); + + assign ex5_xu0_cr = + (ex5_xu0_cr_q & ~{4{dec_byp_ex5_ord_sel}}) | + (ord_cr_data_q & {4{dec_byp_ex5_ord_sel}}); + + assign ex5_xu0_xer = + (ex5_xu0_xer_q & ~{10{dec_byp_ex5_ord_sel}}) | + (ord_xer_data_q & {10{dec_byp_ex5_ord_sel}}); + + //------------------------------------------------------------------------------------------ + // EX6 Pipeline Muxing + //------------------------------------------------------------------------------------------ + assign ex6_xu0_rt = + (ex6_xu0_rt_q & ~fanout(ex6_mul_done_q[0:7],`GPR_WIDTH)) | + (mul_byp_ex6_rt & fanout(ex6_mul_done_q[0:7],`GPR_WIDTH)); + + assign ex6_xu0_cr = + (ex6_xu0_cr_q & ~{4{ex6_mul_done_q[8]}}) | + (mul_byp_ex6_cr & {4{ex6_mul_done_q[8]}}); + + assign ex6_xu0_xer = + (ex6_xu0_xer_q & ~{10{ex6_mul_done_q[8]}}) | + (mul_byp_ex6_xer & {10{ex6_mul_done_q[8]}}); + + //------------------------------------------------------------------------------------------ + // MMU/Erat Interface Data Capture + //------------------------------------------------------------------------------------------ + // Special clock gates for erativax + assign ex0_xu0_ivax_act = exx_xu0_act[0] | dec_byp_ex1_rs_capt; + assign ex1_xu0_ivax_act = exx_xu0_act[1] | dec_byp_ex1_rs_capt; + + assign mm_rs_is_d = ex2_rs1_q[55:63]; + + assign mm_ra_entry_d = ex2_rs2_noimm_q[52:63]; + + generate + if (`GPR_WIDTH > 32) + begin : mm_cm_mask + assign mm_data_d[64 - `GPR_WIDTH:31] = ex4_xu0_rt_q[64-`GPR_WIDTH:31] & {32{ ex4_spr_msr_cm}}; + end + endgenerate + assign mm_data_d[32:63] = ex4_xu0_rt_q[32:63]; + + assign xu_iu_rs_is = mm_rs_is_q; + assign xu_iu_ra_entry = mm_ra_entry_q[8:11]; + assign xu_iu_rb = mm_data_q[64-`GPR_WIDTH:51]; + assign xu_iu_rs_data = mm_data_q; + + assign xu_lq_rs_is = mm_rs_is_q; + assign xu_lq_ra_entry = mm_ra_entry_q[7:11]; + assign xu_lq_rb = mm_data_q[64-`GPR_WIDTH:51]; + assign xu_lq_rs_data = mm_data_q; + + assign xu_mm_ra_entry = mm_ra_entry_q; + assign xu_mm_rb = mm_data_q; + + //------------------------------------------------------------------------------------------ + // Parity Gen + //------------------------------------------------------------------------------------------ + generate begin : parity_gen + genvar i; + for (i = 8-`GPR_WIDTH/8; i <= 7; i = i + 1) + begin : parity_loop + assign ex6_parity[i] = ^(ex6_xu0_rt[8 * i:8 * i + 7]); + end + end + endgenerate + + //------------------------------------------------------------------------------------------ + // IO / Buffering + //------------------------------------------------------------------------------------------ + // GPR + assign byp_alu_ex2_rs1 = ex2_rs1_q; + assign byp_alu_ex2_rs2 = ex2_rs2_q; + assign byp_pop_ex2_rs1 = ex2_rs1_q; + assign byp_cnt_ex2_rs1 = ex2_rs1_q; + assign byp_div_ex2_rs1 = ex2_rs1_q; + assign byp_div_ex2_rs2 = ex2_rs2_q; + assign byp_mul_ex2_rs1 = ex2_rs1_q; + assign byp_mul_ex2_rs2 = ex2_rs2_q; + assign byp_mul_ex2_abort = exx_xu0_abort_q[2]; + assign byp_dlm_ex2_rs1 = ex2_rs1_q[32:63]; + assign byp_dlm_ex2_rs2 = ex2_rs2_q[32:63]; + assign byp_bcd_ex2_rs1 = ex2_rs1_q; + assign byp_bcd_ex2_rs2 = ex2_rs2_q; + assign xu0_gpr_ex6_wd = {ex6_xu0_rt, ex6_parity, 2'b00}; + + assign xu0_xu1_ex2_rt = alu_byp_ex2_add_rt; + assign xu0_xu1_ex3_rt = ex3_xu0_rt_nobyp; + assign xu0_xu1_ex4_rt = ex4_xu0_rt_q; + assign xu0_xu1_ex5_rt = ex5_xu0_rt_q; + assign xu0_xu1_ex6_rt = ex6_xu0_rt; + + assign xu0_xu1_ex7_rt = ex7_xu0_rt_q; + assign xu0_xu1_ex8_rt = ex8_xu0_rt_q; + assign xu0_xu1_ex6_lq_rt = ex6_lq_rt_q; + assign xu0_xu1_ex7_lq_rt = ex7_lq_rt_q; + assign xu0_xu1_ex8_lq_rt = ex8_lq_rt_q; + + assign xu0_lq_ex3_rt = alu_byp_ex3_rt; + assign xu0_lq_ex4_rt = ex4_xu0_rt_q; + assign xu0_lq_ex6_act = exx_xu0_act[6]; + assign xu0_lq_ex6_rt = ex6_xu0_rt; + assign xu0_pc_ram_data = ex6_xu0_rt; + assign xu_spr_ex2_rs1 = ex2_rs1_q; + + assign xu0_xu1_ex2_abort = exx_xu0_abort_q[2]; + assign xu0_xu1_ex6_abort = ex6_xu0_abort; + assign xu0_lq_ex3_abort = exx_xu0_abort_q[3]; + + assign xu0_iu_bta_int = dec_byp_ex4_hpriv == 1'b1 ? dec_byp_ex4_instr : ord_rt_data_q[30:61]; + assign xu0_iu_bta = {ord_rt_data_q[62-`EFF_IFAR_ARCH:29], xu0_iu_bta_int}; + + // CR + assign byp_alu_ex2_cr_bit = ex2_cr_bit_q; + assign xu0_cr_ex6_w0d = ex6_xu0_cr; + assign xu0_xu1_ex3_cr = ex3_xu0_cr; + assign xu0_xu1_ex4_cr = ex4_xu0_cr_q; + assign xu0_xu1_ex6_cr = ex6_xu0_cr; + assign byp_br_ex3_cr = ex3_alu2_cr; + assign byp_br_ex2_cr1 = ex2_cr1_q; + assign byp_br_ex2_cr2 = ex2_cr2_q; + assign byp_br_ex2_cr3 = ex2_cr3_q; + + // XER + assign byp_alu_ex2_xer = ex2_xer3_q; + assign byp_div_ex2_xer = ex2_xer3_q; + assign byp_mul_ex2_xer = ex2_xer3_q; + assign byp_dlm_ex2_xer = ex2_xer3_q[0:2]; + assign xu0_xer_ex6_w0d = ex6_xu0_xer; + assign xu0_xu1_ex3_xer = ex3_xu0_xer2; + assign xu0_xu1_ex4_xer = ex4_xu0_xer_q; + assign xu0_xu1_ex6_xer = ex6_xu0_xer; + + // LR + assign byp_br_ex2_lr1 = ex2_lr1_q; + assign byp_br_ex2_lr2 = ex2_lr2_q; + assign xu0_lr_ex4_w0d = ex4_xu0_lr_q; + + // CTR + assign byp_br_ex2_ctr = ex2_ctr2_q; + assign xu0_ctr_ex4_w0d = ex4_xu0_ctr_q; + + // Abort + assign xu0_rv_ex2_s1_abort = ex2_rs1_abort_q; + assign xu0_rv_ex2_s2_abort = ex2_rs2_abort_q; + assign xu0_rv_ex2_s3_abort = ex2_rs3_abort_q; + assign byp_dec_ex2_abort = ex2_rs1_abort_q | ex2_rs2_abort_q | ex2_rs3_abort_q; + + //------------------------------------------------------------------------------------------ + // Clock Gating + //------------------------------------------------------------------------------------------ + assign exx_xu0_act = {dec_byp_ex0_act, exx_xu0_act_q[1:4], (exx_xu0_act_q[5] | dec_byp_ex5_ord_sel), (exx_xu0_act_q[6] | ex6_mul_done_q[8]), exx_xu0_act_q[7]}; + assign exx_lq_act = {lq_xu_ex5_act, exx_lq_act_q[6:8]}; + + assign exx_xu0_act_d[1:7] = exx_xu0_act[0:6]; + assign exx_lq_act_d[6:8] = exx_lq_act[5:7]; + + + //------------------------------------------------------------------------------------------ + // Latches + //------------------------------------------------------------------------------------------ + tri_rlmreg_p #(.WIDTH(7), .OFFSET(1),.INIT(0), .NEEDS_SRESET(1)) exx_xu0_act_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[exx_xu0_act_offset : exx_xu0_act_offset + 7-1]), + .scout(sov[exx_xu0_act_offset : exx_xu0_act_offset + 7-1]), + .din(exx_xu0_act_d), + .dout(exx_xu0_act_q) + ); + tri_rlmreg_p #(.WIDTH(3), .OFFSET(6),.INIT(0), .NEEDS_SRESET(1)) exx_lq_act_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[exx_lq_act_offset : exx_lq_act_offset + 3-1]), + .scout(sov[exx_lq_act_offset : exx_lq_act_offset + 3-1]), + .din(exx_lq_act_d), + .dout(exx_lq_act_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_s1_v_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_s1_v_offset]), + .scout(sov[ex1_s1_v_offset]), + .din(rv_xu0_ex0_s1_v), + .dout(ex1_s1_v_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_s2_v_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_s2_v_offset]), + .scout(sov[ex1_s2_v_offset]), + .din(rv_xu0_ex0_s2_v), + .dout(ex1_s2_v_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_s3_v_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_s3_v_offset]), + .scout(sov[ex1_s3_v_offset]), + .din(rv_xu0_ex0_s3_v), + .dout(ex1_s3_v_q) + ); +generate begin : ex1_gpr_s1_xu0_sel_gen + genvar i; + for (i=2;i<=8;i=i+1) begin : ex1_gpr_s1_xu0_sel_entry + tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s1_xu0_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_gpr_s1_xu0_sel_offset + (i-2)*8 : ex1_gpr_s1_xu0_sel_offset + (i-2+1)*8-1]), + .scout(sov[ex1_gpr_s1_xu0_sel_offset + (i-2)*8 : ex1_gpr_s1_xu0_sel_offset + (i-2+1)*8-1]), + .din({8{ex0_gpr_s1_xu0_sel[i-1]}}), + .dout(ex1_gpr_s1_xu0_sel_q[i]) + ); + end +end +endgenerate +generate begin : ex1_gpr_s2_xu0_sel_gen + genvar i; + for (i=2;i<=8;i=i+1) begin : ex1_gpr_s2_xu0_sel_entry + tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s2_xu0_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_gpr_s2_xu0_sel_offset + (i-2)*8 : ex1_gpr_s2_xu0_sel_offset + (i-2+1)*8-1]), + .scout(sov[ex1_gpr_s2_xu0_sel_offset + (i-2)*8 : ex1_gpr_s2_xu0_sel_offset + (i-2+1)*8-1]), + .din({8{ex0_gpr_s2_xu0_sel[i-1]}}), + .dout(ex1_gpr_s2_xu0_sel_q[i]) + ); + end +end +endgenerate +generate begin : ex1_gpr_s1_xu1_sel_gen + genvar i; + for (i=2;i<=5;i=i+1) begin : ex1_gpr_s1_xu1_sel_entry + tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s1_xu1_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_gpr_s1_xu1_sel_offset + (i-2)*8 : ex1_gpr_s1_xu1_sel_offset + (i-2+1)*8-1]), + .scout(sov[ex1_gpr_s1_xu1_sel_offset + (i-2)*8 : ex1_gpr_s1_xu1_sel_offset + (i-2+1)*8-1]), + .din({8{ex0_gpr_s1_xu1_sel[i-1]}}), + .dout(ex1_gpr_s1_xu1_sel_q[i]) + ); + end +end +endgenerate +generate begin : ex1_gpr_s2_xu1_sel_gen + genvar i; + for (i=2;i<=5;i=i+1) begin : ex1_gpr_s2_xu1_sel_entry + tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s2_xu1_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_gpr_s2_xu1_sel_offset + (i-2)*8 : ex1_gpr_s2_xu1_sel_offset + (i-2+1)*8-1]), + .scout(sov[ex1_gpr_s2_xu1_sel_offset + (i-2)*8 : ex1_gpr_s2_xu1_sel_offset + (i-2+1)*8-1]), + .din({8{ex0_gpr_s2_xu1_sel[i-1]}}), + .dout(ex1_gpr_s2_xu1_sel_q[i]) + ); + end +end +endgenerate +generate begin : ex1_gpr_s1_lq_sel_gen + genvar i; + for (i=5;i<=8;i=i+1) begin : ex1_gpr_s1_lq_sel_entry + tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s1_lq_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_gpr_s1_lq_sel_offset + (i-5)*8 : ex1_gpr_s1_lq_sel_offset + (i-5+1)*8-1]), + .scout(sov[ex1_gpr_s1_lq_sel_offset + (i-5)*8 : ex1_gpr_s1_lq_sel_offset + (i-5+1)*8-1]), + .din({8{ex0_gpr_s1_lq_sel[i-1]}}), + .dout(ex1_gpr_s1_lq_sel_q[i]) + ); + end +end +endgenerate +generate begin : ex1_gpr_s2_lq_sel_gen + genvar i; + for (i=5;i<=8;i=i+1) begin : ex1_gpr_s2_lq_sel_entry + tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s2_lq_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_gpr_s2_lq_sel_offset + (i-5)*8 : ex1_gpr_s2_lq_sel_offset + (i-5+1)*8-1]), + .scout(sov[ex1_gpr_s2_lq_sel_offset + (i-5)*8 : ex1_gpr_s2_lq_sel_offset + (i-5+1)*8-1]), + .din({8{ex0_gpr_s2_lq_sel[i-1]}}), + .dout(ex1_gpr_s2_lq_sel_q[i]) + ); + end +end +endgenerate + tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s2_imm_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_gpr_s2_imm_sel_offset : ex1_gpr_s2_imm_sel_offset + 8-1]), + .scout(sov[ex1_gpr_s2_imm_sel_offset : ex1_gpr_s2_imm_sel_offset + 8-1]), + .din({8{dec_byp_ex0_rs2_sel_imm}}), + .dout(ex1_gpr_s2_imm_sel_q) + ); +generate begin : ex1_spr_s1_xu0_sel_gen + genvar i; + for (i=3;i<=6;i=i+1) begin : ex1_spr_s1_xu0_sel_entry + tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_spr_s1_xu0_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_spr_s1_xu0_sel_offset + (i-3)*3 : ex1_spr_s1_xu0_sel_offset + (i-3+1)*3-1]), + .scout(sov[ex1_spr_s1_xu0_sel_offset + (i-3)*3 : ex1_spr_s1_xu0_sel_offset + (i-3+1)*3-1]), + .din({3{rv_xu0_s1_fxu0_sel[i-1]}}), + .dout(ex1_spr_s1_xu0_sel_q[i]) + ); + end +end +endgenerate +generate begin : ex1_spr_s1_xu1_sel_gen + genvar i; + for (i=3;i<=3;i=i+1) begin : ex1_spr_s1_xu1_sel_entry + tri_rlmreg_p #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_spr_s1_xu1_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_spr_s1_xu1_sel_offset + (i-3)*1 : ex1_spr_s1_xu1_sel_offset + (i-3+1)*1-1]), + .scout(sov[ex1_spr_s1_xu1_sel_offset + (i-3)*1 : ex1_spr_s1_xu1_sel_offset + (i-3+1)*1-1]), + .din({1{rv_xu0_s1_fxu1_sel[i-1]}}), + .dout(ex1_spr_s1_xu1_sel_q[i]) + ); + end +end +endgenerate +generate begin : ex1_spr_s1_lq_sel_gen + genvar i; + for (i=5;i<=6;i=i+1) begin : ex1_spr_s1_lq_sel_entry + tri_rlmreg_p #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_spr_s1_lq_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_spr_s1_lq_sel_offset + (i-5)*1 : ex1_spr_s1_lq_sel_offset + (i-5+1)*1-1]), + .scout(sov[ex1_spr_s1_lq_sel_offset + (i-5)*1 : ex1_spr_s1_lq_sel_offset + (i-5+1)*1-1]), + .din({1{rv_xu0_s1_lq_sel[i-1]}}), + .dout(ex1_spr_s1_lq_sel_q[i]) + ); + end +end +endgenerate +generate begin : ex1_spr_s2_xu0_sel_gen + genvar i; + for (i=3;i<=6;i=i+1) begin : ex1_spr_s2_xu0_sel_entry + tri_rlmreg_p #(.WIDTH(6), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_spr_s2_xu0_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_spr_s2_xu0_sel_offset + (i-3)*6 : ex1_spr_s2_xu0_sel_offset + (i-3+1)*6-1]), + .scout(sov[ex1_spr_s2_xu0_sel_offset + (i-3)*6 : ex1_spr_s2_xu0_sel_offset + (i-3+1)*6-1]), + .din({6{rv_xu0_s2_fxu0_sel[i-1]}}), + .dout(ex1_spr_s2_xu0_sel_q[i]) + ); + end +end +endgenerate +generate begin : ex1_spr_s2_xu1_sel_gen + genvar i; + for (i=3;i<=3;i=i+1) begin : ex1_spr_s2_xu1_sel_entry + tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_spr_s2_xu1_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_spr_s2_xu1_sel_offset + (i-3)*2 : ex1_spr_s2_xu1_sel_offset + (i-3+1)*2-1]), + .scout(sov[ex1_spr_s2_xu1_sel_offset + (i-3)*2 : ex1_spr_s2_xu1_sel_offset + (i-3+1)*2-1]), + .din({2{rv_xu0_s2_fxu1_sel[i-1]}}), + .dout(ex1_spr_s2_xu1_sel_q[i]) + ); + end +end +endgenerate +generate begin : ex1_spr_s2_lq_sel_gen + genvar i; + for (i=5;i<=6;i=i+1) begin : ex1_spr_s2_lq_sel_entry + tri_rlmreg_p #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_spr_s2_lq_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_spr_s2_lq_sel_offset + (i-5)*1 : ex1_spr_s2_lq_sel_offset + (i-5+1)*1-1]), + .scout(sov[ex1_spr_s2_lq_sel_offset + (i-5)*1 : ex1_spr_s2_lq_sel_offset + (i-5+1)*1-1]), + .din({1{rv_xu0_s2_lq_sel[i-1]}}), + .dout(ex1_spr_s2_lq_sel_q[i]) + ); + end +end +endgenerate +generate begin : ex1_spr_s3_xu0_sel_gen + genvar i; + for (i=3;i<=8;i=i+1) begin : ex1_spr_s3_xu0_sel_entry + tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_spr_s3_xu0_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_spr_s3_xu0_sel_offset + (i-3)*2 : ex1_spr_s3_xu0_sel_offset + (i-3+1)*2-1]), + .scout(sov[ex1_spr_s3_xu0_sel_offset + (i-3)*2 : ex1_spr_s3_xu0_sel_offset + (i-3+1)*2-1]), + .din({2{rv_xu0_s3_fxu0_sel[i-1]}}), + .dout(ex1_spr_s3_xu0_sel_q[i]) + ); + end +end +endgenerate +generate begin : ex1_spr_s3_xu1_sel_gen + genvar i; + for (i=3;i<=5;i=i+1) begin : ex1_spr_s3_xu1_sel_entry + tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_spr_s3_xu1_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_spr_s3_xu1_sel_offset + (i-3)*2 : ex1_spr_s3_xu1_sel_offset + (i-3+1)*2-1]), + .scout(sov[ex1_spr_s3_xu1_sel_offset + (i-3)*2 : ex1_spr_s3_xu1_sel_offset + (i-3+1)*2-1]), + .din({2{rv_xu0_s3_fxu1_sel[i-1]}}), + .dout(ex1_spr_s3_xu1_sel_q[i]) + ); + end +end +endgenerate +generate begin : ex1_spr_s3_lq_sel_gen + genvar i; + for (i=5;i<=6;i=i+1) begin : ex1_spr_s3_lq_sel_entry + tri_rlmreg_p #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_spr_s3_lq_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_spr_s3_lq_sel_offset + (i-5)*1 : ex1_spr_s3_lq_sel_offset + (i-5+1)*1-1]), + .scout(sov[ex1_spr_s3_lq_sel_offset + (i-5)*1 : ex1_spr_s3_lq_sel_offset + (i-5+1)*1-1]), + .din({1{rv_xu0_s3_lq_sel[i-1]}}), + .dout(ex1_spr_s3_lq_sel_q[i]) + ); + end +end +endgenerate +generate begin : ex1_gpr_s1_rel_sel_gen + genvar i; + for (i=3;i<=4;i=i+1) begin : ex1_gpr_s1_rel_sel_entry + tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s1_rel_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_gpr_s1_rel_sel_offset + (i-3)*8 : ex1_gpr_s1_rel_sel_offset + (i-3+1)*8-1]), + .scout(sov[ex1_gpr_s1_rel_sel_offset + (i-3)*8 : ex1_gpr_s1_rel_sel_offset + (i-3+1)*8-1]), + .din({8{ex0_gpr_s1_rel_sel[i-1]}}), + .dout(ex1_gpr_s1_rel_sel_q[i]) + ); + end +end +endgenerate +generate begin : ex1_gpr_s2_rel_sel_gen + genvar i; + for (i=3;i<=4;i=i+1) begin : ex1_gpr_s2_rel_sel_entry + tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s2_rel_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_gpr_s2_rel_sel_offset + (i-3)*8 : ex1_gpr_s2_rel_sel_offset + (i-3+1)*8-1]), + .scout(sov[ex1_gpr_s2_rel_sel_offset + (i-3)*8 : ex1_gpr_s2_rel_sel_offset + (i-3+1)*8-1]), + .din({8{ex0_gpr_s2_rel_sel[i-1]}}), + .dout(ex1_gpr_s2_rel_sel_q[i]) + ); + end +end +endgenerate + tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s1_reg_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ex0_xu0_ivax_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_gpr_s1_reg_sel_offset : ex1_gpr_s1_reg_sel_offset + 8-1]), + .scout(sov[ex1_gpr_s1_reg_sel_offset : ex1_gpr_s1_reg_sel_offset + 8-1]), + .din({8{ex0_gpr_s1_reg_sel}}), + .dout(ex1_gpr_s1_reg_sel_q) + ); + tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s2_reg_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_gpr_s2_reg_sel_offset : ex1_gpr_s2_reg_sel_offset + 8-1]), + .scout(sov[ex1_gpr_s2_reg_sel_offset : ex1_gpr_s2_reg_sel_offset + 8-1]), + .din({8{ex0_gpr_s2_reg_sel}}), + .dout(ex1_gpr_s2_reg_sel_q) + ); + tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_spr_s1_reg_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_spr_s1_reg_sel_offset : ex1_spr_s1_reg_sel_offset + 3-1]), + .scout(sov[ex1_spr_s1_reg_sel_offset : ex1_spr_s1_reg_sel_offset + 3-1]), + .din({3{ex0_spr_s1_reg_sel}}), + .dout(ex1_spr_s1_reg_sel_q) + ); + tri_rlmreg_p #(.WIDTH(6), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_spr_s2_reg_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_spr_s2_reg_sel_offset : ex1_spr_s2_reg_sel_offset + 6-1]), + .scout(sov[ex1_spr_s2_reg_sel_offset : ex1_spr_s2_reg_sel_offset + 6-1]), + .din({6{ex0_spr_s2_reg_sel}}), + .dout(ex1_spr_s2_reg_sel_q) + ); + tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_spr_s3_reg_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_spr_s3_reg_sel_offset : ex1_spr_s3_reg_sel_offset + 2-1]), + .scout(sov[ex1_spr_s3_reg_sel_offset : ex1_spr_s3_reg_sel_offset + 2-1]), + .din({2{ex0_spr_s3_reg_sel}}), + .dout(ex1_spr_s3_reg_sel_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_abt_s1_lq_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_abt_s1_lq_sel_offset]), + .scout(sov[ex1_abt_s1_lq_sel_offset]), + .din(ex0_gpr_s1_lq_sel[8]), + .dout(ex1_abt_s1_lq_sel_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_abt_s2_lq_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_abt_s2_lq_sel_offset]), + .scout(sov[ex1_abt_s2_lq_sel_offset]), + .din(ex0_gpr_s2_lq_sel[8]), + .dout(ex1_abt_s2_lq_sel_q) + ); + tri_rlmreg_p #(.WIDTH(3), .OFFSET(7),.INIT(0), .NEEDS_SRESET(1)) ex1_abt_s3_lq_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_abt_s3_lq_sel_offset : ex1_abt_s3_lq_sel_offset + 3-1]), + .scout(sov[ex1_abt_s3_lq_sel_offset : ex1_abt_s3_lq_sel_offset + 3-1]), + .din(rv_xu0_s3_lq_sel[6:8]), + .dout(ex1_abt_s3_lq_sel_q) + ); + tri_rlmreg_p #(.WIDTH(2), .OFFSET(6),.INIT(0), .NEEDS_SRESET(1)) ex1_abt_s1_xu1_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_abt_s1_xu1_sel_offset : ex1_abt_s1_xu1_sel_offset + 2-1]), + .scout(sov[ex1_abt_s1_xu1_sel_offset : ex1_abt_s1_xu1_sel_offset + 2-1]), + .din(ex0_gpr_s1_xu1_sel[5:6]), + .dout(ex1_abt_s1_xu1_sel_q) + ); + tri_rlmreg_p #(.WIDTH(2), .OFFSET(6),.INIT(0), .NEEDS_SRESET(1)) ex1_abt_s2_xu1_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_abt_s2_xu1_sel_offset : ex1_abt_s2_xu1_sel_offset + 2-1]), + .scout(sov[ex1_abt_s2_xu1_sel_offset : ex1_abt_s2_xu1_sel_offset + 2-1]), + .din(ex0_gpr_s2_xu1_sel[5:6]), + .dout(ex1_abt_s2_xu1_sel_q) + ); + tri_rlmreg_p #(.WIDTH(2), .OFFSET(6),.INIT(0), .NEEDS_SRESET(1)) ex1_abt_s3_xu1_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_abt_s3_xu1_sel_offset : ex1_abt_s3_xu1_sel_offset + 2-1]), + .scout(sov[ex1_abt_s3_xu1_sel_offset : ex1_abt_s3_xu1_sel_offset + 2-1]), + .din(rv_xu0_s3_fxu1_sel[5:6]), + .dout(ex1_abt_s3_xu1_sel_q) + ); + tri_rlmreg_p #(.WIDTH(4), .OFFSET(9),.INIT(0), .NEEDS_SRESET(1)) ex1_abt_s1_xu0_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_abt_s1_xu0_sel_offset : ex1_abt_s1_xu0_sel_offset + 4-1]), + .scout(sov[ex1_abt_s1_xu0_sel_offset : ex1_abt_s1_xu0_sel_offset + 4-1]), + .din(ex0_gpr_s1_xu0_sel[8:11]), + .dout(ex1_abt_s1_xu0_sel_q) + ); + tri_rlmreg_p #(.WIDTH(4), .OFFSET(9),.INIT(0), .NEEDS_SRESET(1)) ex1_abt_s2_xu0_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_abt_s2_xu0_sel_offset : ex1_abt_s2_xu0_sel_offset + 4-1]), + .scout(sov[ex1_abt_s2_xu0_sel_offset : ex1_abt_s2_xu0_sel_offset + 4-1]), + .din(ex0_gpr_s2_xu0_sel[8:11]), + .dout(ex1_abt_s2_xu0_sel_q) + ); + tri_rlmreg_p #(.WIDTH(4), .OFFSET(9),.INIT(0), .NEEDS_SRESET(1)) ex1_abt_s3_xu0_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_abt_s3_xu0_sel_offset : ex1_abt_s3_xu0_sel_offset + 4-1]), + .scout(sov[ex1_abt_s3_xu0_sel_offset : ex1_abt_s3_xu0_sel_offset + 4-1]), + .din(rv_xu0_s3_fxu0_sel[8:11]), + .dout(ex1_abt_s3_xu0_sel_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_is_mflr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_is_mflr_offset]), + .scout(sov[ex2_is_mflr_offset]), + .din(dec_byp_ex1_is_mflr), + .dout(ex2_is_mflr_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_is_mfxer_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_is_mfxer_offset]), + .scout(sov[ex2_is_mfxer_offset]), + .din(dec_byp_ex1_is_mfxer), + .dout(ex2_is_mfxer_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_is_mtxer_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_is_mtxer_offset]), + .scout(sov[ex2_is_mtxer_offset]), + .din(dec_byp_ex1_is_mtxer), + .dout(ex2_is_mtxer_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_is_mfcr_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_is_mfcr_sel_offset]), + .scout(sov[ex2_is_mfcr_sel_offset]), + .din(dec_byp_ex1_is_mfcr_sel), + .dout(ex2_is_mfcr_sel_q) + ); + tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_is_mfcr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_is_mfcr_offset : ex2_is_mfcr_offset + 8-1]), + .scout(sov[ex2_is_mfcr_offset : ex2_is_mfcr_offset + 8-1]), + .din(dec_byp_ex1_is_mfcr), + .dout(ex2_is_mfcr_q) + ); + tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_is_mtcr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_is_mtcr_offset : ex2_is_mtcr_offset + 8-1]), + .scout(sov[ex2_is_mtcr_offset : ex2_is_mtcr_offset + 8-1]), + .din(dec_byp_ex1_is_mtcr), + .dout(ex2_is_mtcr_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_is_mfctr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_is_mfctr_offset]), + .scout(sov[ex2_is_mfctr_offset]), + .din(dec_byp_ex1_is_mfctr), + .dout(ex2_is_mfctr_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_is_mtxer_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_is_mtxer_offset]), + .scout(sov[ex3_is_mtxer_offset]), + .din(ex2_is_mtxer_q), + .dout(ex3_is_mtxer_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex4_xu0_rt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[3]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex4_xu0_rt_offset : ex4_xu0_rt_offset + `GPR_WIDTH-1]), + .scout(sov[ex4_xu0_rt_offset : ex4_xu0_rt_offset + `GPR_WIDTH-1]), + .din(ex3_xu0_rt_nobyp), + .dout(ex4_xu0_rt_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex5_xu0_rt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[4]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), + .mpw1_b(mpw1_dc_b[DEX5]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex5_xu0_rt_offset : ex5_xu0_rt_offset + `GPR_WIDTH-1]), + .scout(sov[ex5_xu0_rt_offset : ex5_xu0_rt_offset + `GPR_WIDTH-1]), + .din(ex4_xu0_rt_nobyp), + .dout(ex5_xu0_rt_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex6_xu0_rt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[5]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX6]), + .mpw1_b(mpw1_dc_b[DEX6]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex6_xu0_rt_offset : ex6_xu0_rt_offset + `GPR_WIDTH-1]), + .scout(sov[ex6_xu0_rt_offset : ex6_xu0_rt_offset + `GPR_WIDTH-1]), + .din(ex5_xu0_rt), + .dout(ex6_xu0_rt_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex7_xu0_rt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[6]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX7]), + .mpw1_b(mpw1_dc_b[DEX7]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex7_xu0_rt_offset : ex7_xu0_rt_offset + `GPR_WIDTH-1]), + .scout(sov[ex7_xu0_rt_offset : ex7_xu0_rt_offset + `GPR_WIDTH-1]), + .din(ex6_xu0_rt), + .dout(ex7_xu0_rt_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex8_xu0_rt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[7]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX8]), + .mpw1_b(mpw1_dc_b[DEX8]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex8_xu0_rt_offset : ex8_xu0_rt_offset + `GPR_WIDTH-1]), + .scout(sov[ex8_xu0_rt_offset : ex8_xu0_rt_offset + `GPR_WIDTH-1]), + .din(ex7_xu0_rt_q), + .dout(ex8_xu0_rt_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex6_lq_rt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_lq_act[5]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX6]), + .mpw1_b(mpw1_dc_b[DEX6]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex6_lq_rt_offset : ex6_lq_rt_offset + `GPR_WIDTH-1]), + .scout(sov[ex6_lq_rt_offset : ex6_lq_rt_offset + `GPR_WIDTH-1]), + .din(lq_xu_ex5_rt), + .dout(ex6_lq_rt_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex7_lq_rt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_lq_act[6]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX7]), + .mpw1_b(mpw1_dc_b[DEX7]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex7_lq_rt_offset : ex7_lq_rt_offset + `GPR_WIDTH-1]), + .scout(sov[ex7_lq_rt_offset : ex7_lq_rt_offset + `GPR_WIDTH-1]), + .din(ex6_lq_rt_q), + .dout(ex7_lq_rt_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex8_lq_rt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_lq_act[7]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX8]), + .mpw1_b(mpw1_dc_b[DEX8]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex8_lq_rt_offset : ex8_lq_rt_offset + `GPR_WIDTH-1]), + .scout(sov[ex8_lq_rt_offset : ex8_lq_rt_offset + `GPR_WIDTH-1]), + .din(ex7_lq_rt_q), + .dout(ex8_lq_rt_q) + ); + tri_rlmreg_p #(.WIDTH(4), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_xu0_cr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[3]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex4_xu0_cr_offset : ex4_xu0_cr_offset + 4-1]), + .scout(sov[ex4_xu0_cr_offset : ex4_xu0_cr_offset + 4-1]), + .din(ex3_xu0_cr), + .dout(ex4_xu0_cr_q) + ); + tri_rlmreg_p #(.WIDTH(4), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex5_xu0_cr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[4]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), + .mpw1_b(mpw1_dc_b[DEX5]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex5_xu0_cr_offset : ex5_xu0_cr_offset + 4-1]), + .scout(sov[ex5_xu0_cr_offset : ex5_xu0_cr_offset + 4-1]), + .din(ex4_xu0_cr_q), + .dout(ex5_xu0_cr_q) + ); + tri_rlmreg_p #(.WIDTH(4), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex6_xu0_cr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[5]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX6]), + .mpw1_b(mpw1_dc_b[DEX6]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex6_xu0_cr_offset : ex6_xu0_cr_offset + 4-1]), + .scout(sov[ex6_xu0_cr_offset : ex6_xu0_cr_offset + 4-1]), + .din(ex5_xu0_cr), + .dout(ex6_xu0_cr_q) + ); + tri_rlmreg_p #(.WIDTH(4), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex6_lq_cr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_lq_act[5]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX6]), + .mpw1_b(mpw1_dc_b[DEX6]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex6_lq_cr_offset : ex6_lq_cr_offset + 4-1]), + .scout(sov[ex6_lq_cr_offset : ex6_lq_cr_offset + 4-1]), + .din(lq_xu_ex5_cr), + .dout(ex6_lq_cr_q) + ); + tri_rlmreg_p #(.WIDTH(10), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_xu0_xer_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[3]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex4_xu0_xer_offset : ex4_xu0_xer_offset + 10-1]), + .scout(sov[ex4_xu0_xer_offset : ex4_xu0_xer_offset + 10-1]), + .din(ex3_xu0_xer2), + .dout(ex4_xu0_xer_q) + ); + tri_rlmreg_p #(.WIDTH(10), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex5_xu0_xer_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[4]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), + .mpw1_b(mpw1_dc_b[DEX5]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex5_xu0_xer_offset : ex5_xu0_xer_offset + 10-1]), + .scout(sov[ex5_xu0_xer_offset : ex5_xu0_xer_offset + 10-1]), + .din(ex4_xu0_xer_q), + .dout(ex5_xu0_xer_q) + ); + tri_rlmreg_p #(.WIDTH(10), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex6_xu0_xer_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[5]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX6]), + .mpw1_b(mpw1_dc_b[DEX6]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex6_xu0_xer_offset : ex6_xu0_xer_offset + 10-1]), + .scout(sov[ex6_xu0_xer_offset : ex6_xu0_xer_offset + 10-1]), + .din(ex5_xu0_xer), + .dout(ex6_xu0_xer_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex4_xu0_ctr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ex3_xu0_ctr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex4_xu0_ctr_offset : ex4_xu0_ctr_offset + `GPR_WIDTH-1]), + .scout(sov[ex4_xu0_ctr_offset : ex4_xu0_ctr_offset + `GPR_WIDTH-1]), + .din(ex3_xu0_ctr), + .dout(ex4_xu0_ctr_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex4_xu0_lr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ex3_xu0_lr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex4_xu0_lr_offset : ex4_xu0_lr_offset + `GPR_WIDTH-1]), + .scout(sov[ex4_xu0_lr_offset : ex4_xu0_lr_offset + `GPR_WIDTH-1]), + .din(ex3_xu0_lr), + .dout(ex4_xu0_lr_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex2_rs1_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ex1_xu0_ivax_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_rs1_offset : ex2_rs1_offset + `GPR_WIDTH-1]), + .scout(sov[ex2_rs1_offset : ex2_rs1_offset + `GPR_WIDTH-1]), + .din(ex1_rs1), + .dout(ex2_rs1_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex2_rs2_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_rs2_offset : ex2_rs2_offset + `GPR_WIDTH-1]), + .scout(sov[ex2_rs2_offset : ex2_rs2_offset + `GPR_WIDTH-1]), + .din(ex1_rs2), + .dout(ex2_rs2_q) + ); + tri_rlmreg_p #(.WIDTH(4), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_cr1_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_cr1_offset : ex2_cr1_offset + 4-1]), + .scout(sov[ex2_cr1_offset : ex2_cr1_offset + 4-1]), + .din(ex1_cr1), + .dout(ex2_cr1_q) + ); + tri_rlmreg_p #(.WIDTH(4), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_cr2_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_cr2_offset : ex2_cr2_offset + 4-1]), + .scout(sov[ex2_cr2_offset : ex2_cr2_offset + 4-1]), + .din(ex1_cr2), + .dout(ex2_cr2_q) + ); + tri_rlmreg_p #(.WIDTH(4), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_cr3_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_cr3_offset : ex2_cr3_offset + 4-1]), + .scout(sov[ex2_cr3_offset : ex2_cr3_offset + 4-1]), + .din(ex1_cr3), + .dout(ex2_cr3_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_cr_bit_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_cr_bit_offset]), + .scout(sov[ex2_cr_bit_offset]), + .din(ex1_cr_bit), + .dout(ex2_cr_bit_q) + ); + tri_rlmreg_p #(.WIDTH(10), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_xer2_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_xer2_offset : ex2_xer2_offset + 10-1]), + .scout(sov[ex2_xer2_offset : ex2_xer2_offset + 10-1]), + .din(ex1_xer2), + .dout(ex2_xer2_q) + ); + tri_rlmreg_p #(.WIDTH(10), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_xer3_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_xer3_offset : ex2_xer3_offset + 10-1]), + .scout(sov[ex2_xer3_offset : ex2_xer3_offset + 10-1]), + .din(ex1_xer3), + .dout(ex2_xer3_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_xer3_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_xer3_offset]), + .scout(sov[ex3_xer3_offset]), + .din(ex2_xer3_q[0:0]), + .dout(ex3_xer3_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex2_lr1_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_lr1_offset : ex2_lr1_offset + `GPR_WIDTH-1]), + .scout(sov[ex2_lr1_offset : ex2_lr1_offset + `GPR_WIDTH-1]), + .din(ex1_lr1), + .dout(ex2_lr1_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex2_lr2_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_lr2_offset : ex2_lr2_offset + `GPR_WIDTH-1]), + .scout(sov[ex2_lr2_offset : ex2_lr2_offset + `GPR_WIDTH-1]), + .din(ex1_lr2), + .dout(ex2_lr2_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex2_ctr2_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_ctr2_offset : ex2_ctr2_offset + `GPR_WIDTH-1]), + .scout(sov[ex2_ctr2_offset : ex2_ctr2_offset + `GPR_WIDTH-1]), + .din(ex1_ctr2), + .dout(ex2_ctr2_q) + ); + tri_rlmreg_p #(.WIDTH(2), .OFFSET(2),.INIT(0), .NEEDS_SRESET(1)) ex2_cr_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_cr_sel_offset : ex2_cr_sel_offset + 2-1]), + .scout(sov[ex2_cr_sel_offset : ex2_cr_sel_offset + 2-1]), + .din(dec_byp_ex1_cr_sel), + .dout(ex2_cr_sel_q) + ); + tri_rlmreg_p #(.WIDTH(2), .OFFSET(2),.INIT(0), .NEEDS_SRESET(1)) ex2_xer_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_xer_sel_offset : ex2_xer_sel_offset + 2-1]), + .scout(sov[ex2_xer_sel_offset : ex2_xer_sel_offset + 2-1]), + .din(dec_byp_ex1_xer_sel), + .dout(ex2_xer_sel_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex3_rs1_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex3_rs1_offset : ex3_rs1_offset + `GPR_WIDTH-1]), + .scout(sov[ex3_rs1_offset : ex3_rs1_offset + `GPR_WIDTH-1]), + .din(ex2_rs1_q), + .dout(ex3_rs1_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_mfspr_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_mfspr_sel_offset]), + .scout(sov[ex3_mfspr_sel_offset]), + .din(ex2_mfspr_sel), + .dout(ex3_mfspr_sel_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex3_mfspr_rt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ex2_mfspr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex3_mfspr_rt_offset : ex3_mfspr_rt_offset + `GPR_WIDTH-1]), + .scout(sov[ex3_mfspr_rt_offset : ex3_mfspr_rt_offset + `GPR_WIDTH-1]), + .din(ex2_mfspr_rt), + .dout(ex3_mfspr_rt_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ord_rt_data_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ord_data_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ord_rt_data_offset : ord_rt_data_offset + `GPR_WIDTH-1]), + .scout(sov[ord_rt_data_offset : ord_rt_data_offset + `GPR_WIDTH-1]), + .din(ord_rt_data_d), + .dout(ord_rt_data_q) + ); + tri_rlmreg_p #(.WIDTH(4), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ord_cr_data_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ord_data_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ord_cr_data_offset : ord_cr_data_offset + 4-1]), + .scout(sov[ord_cr_data_offset : ord_cr_data_offset + 4-1]), + .din(ord_cr_data_d), + .dout(ord_cr_data_q) + ); + tri_rlmreg_p #(.WIDTH(10), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ord_xer_data_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ord_data_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ord_xer_data_offset : ord_xer_data_offset + 10-1]), + .scout(sov[ord_xer_data_offset : ord_xer_data_offset + 10-1]), + .din(ord_xer_data_d), + .dout(ord_xer_data_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_rs_capt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_rs_capt_offset]), + .scout(sov[ex2_rs_capt_offset]), + .din(dec_byp_ex1_rs_capt), + .dout(ex2_rs_capt_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ra_capt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_ra_capt_offset]), + .scout(sov[ex2_ra_capt_offset]), + .din(dec_byp_ex1_ra_capt), + .dout(ex2_ra_capt_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_ra_capt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_ra_capt_offset]), + .scout(sov[ex3_ra_capt_offset]), + .din(ex2_ra_capt_q), + .dout(ex3_ra_capt_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_ra_capt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_ra_capt_offset]), + .scout(sov[ex4_ra_capt_offset]), + .din(ex3_ra_capt_q), + .dout(ex4_ra_capt_q) + ); + tri_rlmreg_p #(.WIDTH(12), .OFFSET(52),.INIT(0), .NEEDS_SRESET(1)) ex2_rs2_noimm_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_rs2_noimm_offset : ex2_rs2_noimm_offset + 12-1]), + .scout(sov[ex2_rs2_noimm_offset : ex2_rs2_noimm_offset + 12-1]), + .din(ex1_rs2_noimm[52:63]), + .dout(ex2_rs2_noimm_q) + ); + tri_rlmreg_p #(.WIDTH(4), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex3_mtcr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex3_mtcr_offset : ex3_mtcr_offset + 4-1]), + .scout(sov[ex3_mtcr_offset : ex3_mtcr_offset + 4-1]), + .din(ex2_mtcr), + .dout(ex3_mtcr_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_mtcr_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_mtcr_sel_offset]), + .scout(sov[ex3_mtcr_sel_offset]), + .din(ex2_mtcr_sel), + .dout(ex3_mtcr_sel_q) + ); + tri_rlmreg_p #(.WIDTH(9), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) mm_rs_is_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ex2_rs_capt_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[mm_rs_is_offset : mm_rs_is_offset + 9-1]), + .scout(sov[mm_rs_is_offset : mm_rs_is_offset + 9-1]), + .din(mm_rs_is_d), + .dout(mm_rs_is_q) + ); + tri_rlmreg_p #(.WIDTH(12), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) mm_ra_entry_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ex2_ra_capt_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[mm_ra_entry_offset : mm_ra_entry_offset + 12-1]), + .scout(sov[mm_ra_entry_offset : mm_ra_entry_offset + 12-1]), + .din(mm_ra_entry_d), + .dout(mm_ra_entry_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) mm_data_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ex4_ra_capt_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[mm_data_offset : mm_data_offset + `GPR_WIDTH-1]), + .scout(sov[mm_data_offset : mm_data_offset + `GPR_WIDTH-1]), + .din(mm_data_d), + .dout(mm_data_q) + ); + tri_rlmreg_p #(.WIDTH(7), .OFFSET(57),.INIT(0), .NEEDS_SRESET(1)) ex3_cnt_rt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex3_cnt_rt_offset : ex3_cnt_rt_offset + 7-1]), + .scout(sov[ex3_cnt_rt_offset : ex3_cnt_rt_offset + 7-1]), + .din(cnt_byp_ex2_rt), + .dout(ex3_cnt_rt_q) + ); + tri_rlmreg_p #(.WIDTH(8), .OFFSET(56),.INIT(0), .NEEDS_SRESET(1)) ex3_prm_rt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex3_prm_rt_offset : ex3_prm_rt_offset + 8-1]), + .scout(sov[ex3_prm_rt_offset : ex3_prm_rt_offset + 8-1]), + .din(prm_byp_ex2_rt), + .dout(ex3_prm_rt_q) + ); + tri_rlmreg_p #(.WIDTH(4), .OFFSET(60),.INIT(0), .NEEDS_SRESET(1)) ex3_dlm_rt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex3_dlm_rt_offset : ex3_dlm_rt_offset + 4-1]), + .scout(sov[ex3_dlm_rt_offset : ex3_dlm_rt_offset + 4-1]), + .din(dlm_byp_ex2_rt), + .dout(ex3_dlm_rt_q) + ); + tri_rlmreg_p #(.WIDTH(10), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex3_dlm_xer_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex3_dlm_xer_offset : ex3_dlm_xer_offset + 10-1]), + .scout(sov[ex3_dlm_xer_offset : ex3_dlm_xer_offset + 10-1]), + .din(dlm_byp_ex2_xer), + .dout(ex3_dlm_xer_q) + ); + tri_rlmreg_p #(.WIDTH(4), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex3_dlm_cr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex3_dlm_cr_offset : ex3_dlm_cr_offset + 4-1]), + .scout(sov[ex3_dlm_cr_offset : ex3_dlm_cr_offset + 4-1]), + .din(dlm_byp_ex2_cr), + .dout(ex3_dlm_cr_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_mul_ord_done_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX6]), + .mpw1_b(mpw1_dc_b[DEX6]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_mul_ord_done_offset]), + .scout(sov[ex6_mul_ord_done_offset]), + .din({1{mul_byp_ex5_ord_done}}), + .dout(ex6_mul_ord_done_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_mul_abort_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX6]), + .mpw1_b(mpw1_dc_b[DEX6]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_mul_abort_offset]), + .scout(sov[ex6_mul_abort_offset]), + .din(mul_byp_ex5_abort), + .dout(ex6_mul_abort_q) + ); + tri_rlmreg_p #(.WIDTH(9), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex6_mul_done_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX6]), + .mpw1_b(mpw1_dc_b[DEX6]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex6_mul_done_offset : ex6_mul_done_offset + 9-1]), + .scout(sov[ex6_mul_done_offset : ex6_mul_done_offset + 9-1]), + .din({9{mul_byp_ex5_done}}), + .dout(ex6_mul_done_q) + ); + tri_rlmreg_p #(.WIDTH(11), .OFFSET(2),.INIT(0), .NEEDS_SRESET(1)) exx_xu0_abort_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[exx_xu0_abort_offset : exx_xu0_abort_offset + 11-1]), + .scout(sov[exx_xu0_abort_offset : exx_xu0_abort_offset + 11-1]), + .din(exx_xu0_abort_d), + .dout(exx_xu0_abort_q) + ); + tri_rlmreg_p #(.WIDTH(5), .OFFSET(3),.INIT(0), .NEEDS_SRESET(1)) exx_xu1_abort_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[exx_xu1_abort_offset : exx_xu1_abort_offset + 5-1]), + .scout(sov[exx_xu1_abort_offset : exx_xu1_abort_offset + 5-1]), + .din(exx_xu1_abort_d), + .dout(exx_xu1_abort_q) + ); + tri_rlmreg_p #(.WIDTH(4), .OFFSET(6),.INIT(0), .NEEDS_SRESET(1)) exx_lq_abort_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[exx_lq_abort_offset : exx_lq_abort_offset + 4-1]), + .scout(sov[exx_lq_abort_offset : exx_lq_abort_offset + 4-1]), + .din(exx_lq_abort_d), + .dout(exx_lq_abort_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_rs1_abort_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_rs1_abort_offset]), + .scout(sov[ex2_rs1_abort_offset]), + .din(ex1_rs1_abort), + .dout(ex2_rs1_abort_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_rs2_abort_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_rs2_abort_offset]), + .scout(sov[ex2_rs2_abort_offset]), + .din(ex1_rs2_abort), + .dout(ex2_rs2_abort_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_rs3_abort_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_rs3_abort_offset]), + .scout(sov[ex2_rs3_abort_offset]), + .din(ex1_rs3_abort), + .dout(ex2_rs3_abort_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) exx_rel3_act_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[exx_rel3_act_offset]), + .scout(sov[exx_rel3_act_offset]), + .din(lq_xu_rel_act), + .dout(exx_rel3_act_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) exx_rel3_rt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(lq_xu_rel_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[exx_rel3_rt_offset : exx_rel3_rt_offset + `GPR_WIDTH-1]), + .scout(sov[exx_rel3_rt_offset : exx_rel3_rt_offset + `GPR_WIDTH-1]), + .din(lq_xu_rel_rt), + .dout(exx_rel3_rt_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) exx_rel4_rt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_rel3_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[exx_rel4_rt_offset : exx_rel4_rt_offset + `GPR_WIDTH-1]), + .scout(sov[exx_rel4_rt_offset : exx_rel4_rt_offset + `GPR_WIDTH-1]), + .din(exx_rel3_rt_q), + .dout(exx_rel4_rt_q) + ); + + assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in}; + assign scan_out = sov[0]; + + function [0:`GPR_WIDTH-1] fanout; + input [0:7] a; + input integer s; + integer t; + begin + for (t=0;t<`GPR_WIDTH;t=t+1) + begin : loop + fanout[t] = a[t % 8]; + end + end + endfunction + + function [0:`GPR_WIDTH-1] fanout2; + input [0:1] a; + input integer s; + integer t; + begin + for (t=0;t<`GPR_WIDTH;t=t+1) + begin : loop + fanout2[t] = a[t % 2]; + end + end + endfunction + +endmodule diff --git a/dev/verilog/work/xu0_dec.v b/dev/verilog/work/xu0_dec.v new file mode 100755 index 0000000..a6d9021 --- /dev/null +++ b/dev/verilog/work/xu0_dec.v @@ -0,0 +1,5005 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: FXU Decode +// +//***************************************************************************** + +`include "tri_a2o.vh" + +module xu0_dec( + //------------------------------------------------------------------- + // Clocks & Power + //------------------------------------------------------------------- + input [0:`NCLK_WIDTH-1] nclk, + inout vdd, + inout gnd, + + //------------------------------------------------------------------- + // Pervasive + //------------------------------------------------------------------- + input d_mode_dc, + input [0:0] delay_lclkr_dc, + input [0:0] mpw1_dc_b, + input mpw2_dc_b, + input func_sl_force, + input func_sl_thold_0_b, + input sg_0, + input scan_in, + output scan_out, + + //------------------------------------------------------------------- + // Interface with CP + //------------------------------------------------------------------- + input [0:`THREADS-1] cp_flush, + input [0:`ITAG_SIZE_ENC-1] cp_next_itag_t0, + `ifndef THREADS1 + input [0:`ITAG_SIZE_ENC-1] cp_next_itag_t1, + `endif + + output [0:`THREADS-1] dec_ex0_flush, + output [0:`THREADS-1] dec_ex1_flush, + output [0:`THREADS-1] dec_ex2_flush, + output [0:`THREADS-1] dec_ex3_flush, + output [0:`THREADS-1] dec_cp_flush, + + //------------------------------------------------------------------- + // Interface with RV + //------------------------------------------------------------------- + input [0:`THREADS-1] rv_xu0_vld, + input rv_xu0_ex0_ord, + input [0:19] rv_xu0_ex0_fusion, + input [0:31] rv_xu0_ex0_instr, + input [0:`ITAG_SIZE_ENC-1] rv_xu0_ex0_itag, + input [0:2] rv_xu0_ex0_ucode, + input rv_xu0_ex0_s1_v, + input rv_xu0_ex0_s2_v, + input [0:2] rv_xu0_ex0_s2_t, + input rv_xu0_ex0_s3_v, + input [0:2] rv_xu0_ex0_s3_t, + input rv_xu0_ex0_t1_v, + input [0:`GPR_POOL_ENC-1] rv_xu0_ex0_t1_p, + input [0:2] rv_xu0_ex0_t1_t, + input rv_xu0_ex0_t2_v, + input [0:`GPR_POOL_ENC-1] rv_xu0_ex0_t2_p, + input [0:2] rv_xu0_ex0_t2_t, + input rv_xu0_ex0_t3_v, + input [0:`GPR_POOL_ENC-1] rv_xu0_ex0_t3_p, + input [0:2] rv_xu0_ex0_t3_t, + input [0:`THREADS-1] rv_xu0_ex0_spec_flush, + input [0:`THREADS-1] rv_xu0_ex1_spec_flush, + input [0:`THREADS-1] rv_xu0_ex2_spec_flush, + + output xu0_rv_ord_complete, + output [0:`ITAG_SIZE_ENC-1] xu0_rv_ord_itag, + output xu0_rv_hold_all, + + //------------------------------------------------------------------- + // Interface with IU + //------------------------------------------------------------------- + output [0:`THREADS-1] xu0_iu_execute_vld, + output [0:`ITAG_SIZE_ENC-1] xu0_iu_itag, + output [0:`THREADS-1] xu0_iu_mtiar, + output xu0_iu_exception_val, + output [0:4] xu0_iu_exception, + output xu0_iu_n_flush, + output xu0_iu_np1_flush, + output xu0_iu_flush2ucode, + output [0:3] xu0_iu_perf_events, + + output [0:`THREADS-1] xu_iu_np1_async_flush, + input [0:`THREADS-1] iu_xu_async_complete, + input iu_xu_credits_returned, + + output xu0_pc_ram_done, + + output [0:`THREADS-1] xu_iu_pri_val, + output [0:2] xu_iu_pri, + + //------------------------------------------------------------------- + // Interface with ALU + //------------------------------------------------------------------- + output dec_pop_ex1_act, + output dec_alu_ex1_act, + output [0:31] dec_alu_ex1_instr, + output dec_alu_ex1_sel_isel, + output [0:`GPR_WIDTH/8-1] dec_alu_ex1_add_rs1_inv, + output [0:1] dec_alu_ex2_add_ci_sel, + output dec_alu_ex1_sel_trap, + output dec_alu_ex1_sel_cmpl, + output dec_alu_ex1_sel_cmp, + output dec_alu_ex1_msb_64b_sel, + output dec_alu_ex1_xer_ov_en, + output dec_alu_ex1_xer_ca_en, + input alu_dec_ex3_trap_val, + output xu0_xu1_ex3_act, + + //------------------------------------------------------------------- + // Interface with MUL + //------------------------------------------------------------------- + output dec_mul_ex1_mul_recform, + output [0:`THREADS-1] dec_mul_ex1_mul_val, + output dec_mul_ex1_mul_ord, + output dec_mul_ex1_mul_ret, + output dec_mul_ex1_mul_sign, + output dec_mul_ex1_mul_size, + output dec_mul_ex1_mul_imm, + output dec_mul_ex1_xer_ov_update, + input mul_dec_ex6_ord_done, + + output [0:`THREADS-1] dec_ord_flush, + + //------------------------------------------------------------------- + // Interface with DIV + //------------------------------------------------------------------- + output [0:7] dec_div_ex1_div_ctr, + output dec_div_ex1_div_act, + output [0:`THREADS-1] dec_div_ex1_div_val, + output dec_div_ex1_div_sign, + output dec_div_ex1_div_size, + output dec_div_ex1_div_extd, + output dec_div_ex1_div_recform, + output dec_div_ex1_xer_ov_update, + input div_dec_ex4_done, + + //------------------------------------------------------------------- + // Interface with SPR + //------------------------------------------------------------------- + input spr_xu_ord_read_done, + input spr_xu_ord_write_done, + input spr_dec_ex4_spr_hypv, + input spr_dec_ex4_spr_illeg, + input spr_dec_ex4_spr_priv, + input spr_dec_ex4_np1_flush, + + input xu_slowspr_val_in, + input xu_slowspr_rw_in, + + //------------------------------------------------------------------- + // Interface with BCD + //------------------------------------------------------------------- + output dec_bcd_ex1_val, + output dec_bcd_ex1_is_addg6s, + output dec_bcd_ex1_is_cdtbcd, + + //------------------------------------------------------------------- + // Interface with BYP + //------------------------------------------------------------------- + input byp_dec_ex2_abort, + output dec_byp_ex0_act, + output [64-`GPR_WIDTH:63] dec_byp_ex1_imm, + output [24:25] dec_byp_ex1_instr, + output dec_byp_ex0_rs2_sel_imm, + output dec_byp_ex0_rs1_sel_zero, + + output dec_byp_ex1_is_mflr, + output dec_byp_ex1_is_mfxer, + output dec_byp_ex1_is_mtxer, + output dec_byp_ex1_is_mfcr_sel, + output [0:7] dec_byp_ex1_is_mfcr, + output [0:7] dec_byp_ex1_is_mtcr, + output dec_byp_ex1_is_mfctr, + output [2:3] dec_byp_ex1_cr_sel, + output [2:3] dec_byp_ex1_xer_sel, + output dec_byp_ex1_rs_capt, + output dec_byp_ex1_ra_capt, + + output dec_byp_ex3_mtiar, + output dec_byp_ex5_ord_sel, + output dec_byp_ex4_pop_done, + output dec_byp_ex3_cnt_done, + output dec_byp_ex3_prm_done, + output dec_byp_ex3_dlm_done, + output [25:25] dec_cnt_ex2_instr, + + output dec_byp_ex4_hpriv, + output [0:31] dec_byp_ex4_instr, + + output dec_byp_ex3_is_mtspr, + output dec_br_ex0_act, + + //------------------------------------------------------------------- + // Interface with BR + //------------------------------------------------------------------- + input [0:`THREADS-1] br_dec_ex3_execute_vld, + + //------------------------------------------------------------------- + // Interface with Regfiles + //------------------------------------------------------------------- + output xu0_gpr_ex6_we, + output [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] xu0_gpr_ex6_wa, + + output xu0_xer_ex6_we, + output [0:`XER_POOL_ENC+`THREADS_POOL_ENC-1] xu0_xer_ex6_wa, + + output xu0_cr_ex6_we, + output [0:`CR_POOL_ENC+`THREADS_POOL_ENC-1] xu0_cr_ex6_wa, + + output xu0_ctr_ex4_we, + output [0:`CTR_POOL_ENC+`THREADS_POOL_ENC-1] xu0_ctr_ex4_wa, + + output xu0_lr_ex4_we, + output [0:`BR_POOL_ENC+`THREADS_POOL_ENC-1] xu0_lr_ex4_wa, + + //------------------------------------------------------------------- + // Interface with MMU / ERATs + //------------------------------------------------------------------- + output xu_iu_ord_ready, + output xu_iu_act, + output [0:`THREADS-1] xu_iu_val, + output xu_iu_is_eratre, + output xu_iu_is_eratwe, + output xu_iu_is_eratsx, + output xu_iu_is_eratilx, + output xu_iu_is_erativax, + output [0:1] xu_iu_ws, + output [0:2] xu_iu_t, + input iu_xu_ord_read_done, + input iu_xu_ord_write_done, + input iu_xu_ord_n_flush_req, + input iu_xu_ord_par_err, + + output xu_lq_ord_ready, + output xu_lq_act, + output [0:`THREADS-1] xu_lq_val, + output xu_lq_hold_req, + output xu_lq_is_eratre, + output xu_lq_is_eratwe, + output xu_lq_is_eratsx, + output xu_lq_is_eratilx, + output [0:1] xu_lq_ws, + output [0:2] xu_lq_t, + input lq_xu_ord_read_done, + input lq_xu_ord_write_done, + input lq_xu_ord_n_flush_req, + input lq_xu_ord_par_err, + + + output xu_mm_ord_ready, + output xu_mm_act, + output [0:`THREADS-1] xu_mm_val, + output [0:`ITAG_SIZE_ENC-1] xu_mm_itag, + output xu_mm_is_tlbre, + output xu_mm_is_tlbwe, + output xu_mm_is_tlbsx, + output xu_mm_is_tlbsxr, + output xu_mm_is_tlbsrx, + output xu_mm_is_tlbivax, + output xu_mm_is_tlbilx, + input [0:`ITAG_SIZE_ENC-1] mm_xu_itag, + input mm_xu_ord_n_flush_req, + input mm_xu_ord_read_done, + input mm_xu_ord_write_done, + input mm_xu_tlb_miss, + input mm_xu_lrat_miss, + input mm_xu_tlb_inelig, + input mm_xu_pt_fault, + input mm_xu_hv_priv, + input mm_xu_illeg_instr, + input mm_xu_tlb_multihit, + input mm_xu_tlb_par_err, + input mm_xu_lru_par_err, + input mm_xu_local_snoop_reject, + + input [0:1] mm_xu_mmucr0_tlbsel_t0, + `ifndef THREADS1 + input [0:1] mm_xu_mmucr0_tlbsel_t1, + `endif + input mm_xu_tlbwe_binv, + + //------------------------------------------------------------------- + // SPRs + //------------------------------------------------------------------- + output xu_spr_ord_flush, + output xu_spr_ord_ready, + output ex1_spr_msr_cm, + output ex4_spr_msr_cm, + + input [0:`THREADS-1] spr_msr_cm, + input [0:`THREADS-1] spr_msr_gs, + input [0:`THREADS-1] spr_msr_pr, + input [0:`THREADS-1] spr_epcr_dgtmi, + input spr_ccr2_notlb, + input spr_ccr2_en_attn, + input spr_ccr4_en_dnh, + input spr_ccr2_en_pc, + input [0:31] spr_xesr1, + input [0:`THREADS-1] perf_event_en, + + input [0:`THREADS-1] pc_xu_ram_active +); + + localparam tiup = 1'b1; + localparam tidn = 1'b0; + localparam XER_LEFT = `GPR_POOL_ENC-`XER_POOL_ENC; + localparam CR_LEFT = `GPR_POOL_ENC-`CR_POOL_ENC; + + // Latches + wire [1:5] exx_act_q, exx_act_d ; // input=>exx_act_d ,act=>1'b1 + wire ex1_s2_v_q ; // input=>rv_xu0_ex0_s2_v ,act=>exx_act[0] + wire [0:2] ex1_s2_t_q ; // input=>rv_xu0_ex0_s2_t ,act=>exx_act[0] + wire ex1_s3_v_q ; // input=>rv_xu0_ex0_s3_v ,act=>exx_act[0] + wire [0:2] ex1_s3_t_q ; // input=>rv_xu0_ex0_s3_t ,act=>exx_act[0] + wire [0:2] ex1_t1_t_q ; // input=>rv_xu0_ex0_t1_t ,act=>exx_act[0] + wire [0:2] ex1_t2_t_q ; // input=>rv_xu0_ex0_t2_t ,act=>exx_act[0] + wire [0:2] ex1_t3_t_q ; // input=>rv_xu0_ex0_t3_t ,act=>exx_act[0] + wire ex1_t1_v_q ; // input=>rv_xu0_ex0_t1_v ,act=>exx_act[0] + wire ex1_t2_v_q ; // input=>rv_xu0_ex0_t2_v ,act=>exx_act[0] + wire ex1_t3_v_q ; // input=>rv_xu0_ex0_t3_v ,act=>exx_act[0] + wire [0:`GPR_POOL_ENC-1] ex1_t1_p_q ; // input=>rv_xu0_ex0_t1_p ,act=>exx_act[0] + wire [0:`XER_POOL_ENC-1] ex1_t2_p_q ; // input=>rv_xu0_ex0_t2_p[XER_LEFT:`GPR_POOL_ENC-1] ,act=>exx_act[0] + wire [0:`CR_POOL_ENC-1] ex1_t3_p_q ; // input=>rv_xu0_ex0_t3_p[CR_LEFT:`GPR_POOL_ENC-1] ,act=>exx_act[0] + wire [0:31] ex1_instr_q, ex0_instr ; // input=>ex0_instr ,act=>exx_act[0] + wire [0:2] ex1_ucode_q ; // input=>rv_xu0_ex0_ucode ,act=>exx_act[0] + wire [0:`ITAG_SIZE_ENC-1] ex1_itag_q ; // input=>rv_xu0_ex0_itag ,act=>exx_act[0] + wire [0:1] ex2_add_ci_sel_q, ex1_add_ci_sel ; // input=>ex1_add_ci_sel ,act=>exx_act[1] + wire [0:`ITAG_SIZE_ENC-1] ex2_itag_q ; // input=>ex1_itag_q ,act=>exx_act[1] + wire [0:`GPR_POOL_ENC-1] ex2_t1_p_q ; // input=>ex1_t1_p_q ,act=>exx_act[1] + wire [0:`XER_POOL_ENC-1] ex2_t2_p_q ; // input=>ex1_t2_p_q ,act=>exx_act[1] + wire [0:`CR_POOL_ENC-1] ex2_t3_p_q ; // input=>ex1_t3_p_q ,act=>exx_act[1] + wire [0:`GPR_POOL_ENC-1] ex3_t1_p_q ; // input=>ex2_t1_p_q ,act=>exx_act[2] + wire [0:`XER_POOL_ENC-1] ex3_t2_p_q ; // input=>ex2_t2_p_q ,act=>exx_act[2] + wire [0:`CR_POOL_ENC-1] ex3_t3_p_q ; // input=>ex2_t3_p_q ,act=>exx_act[2] + wire [0:`ITAG_SIZE_ENC-1] ex3_itag_q ; // input=>ex2_itag_q ,act=>exx_act[2] + wire [0:`ITAG_SIZE_ENC-1] ex4_itag_q, ex3_itag ; // input=>ex3_itag ,act=>exx_act[3] + wire [0:`THREADS-1] cp_flush_q ; // input=>cp_flush ,act=>1'b1 + wire [0:`THREADS-1] ex0_val_q, rv2_val ; // input=>rv2_val ,act=>1'b1 + wire [0:`THREADS-1] ex1_val_q, ex0_val ; // input=>ex0_val ,act=>1'b1 + wire [0:`THREADS-1] ex2_val_q, ex1_val ; // input=>ex1_val ,act=>1'b1 + wire [0:`THREADS-1] ex3_val_q, ex2_val ; // input=>ex2_val ,act=>1'b1 + wire [0:`THREADS-1] ex4_val_q, ex3_val ; // input=>ex3_val ,act=>1'b1 + wire [0:`THREADS-1] ex5_val_q, ex4_val ; // input=>ex4_val ,act=>1'b1 + wire [0:`THREADS-1] ex6_val_q, ex5_val ; // input=>ex5_val ,act=>1'b1 + wire [0:`THREADS-1] ex1_ord_val_q, ex0_ord_val ; // input=>ex0_ord_val ,act=>1'b1 + wire [0:`THREADS-1] ex2_ord_val_q, ex1_ord_val ; // input=>ex1_ord_val ,act=>1'b1 + wire [0:`THREADS-1] ex3_ord_val_q, ex2_ord_val ; // input=>ex2_ord_val ,act=>1'b1 + wire [0:`THREADS-1] ex4_ord_val_q, ex3_ord_val ; // input=>ex3_ord_val ,act=>1'b1 + wire [0:`THREADS-1] spr_msr_cm_q ; // input=>spr_msr_cm ,act=>1'b1 + wire [0:`THREADS-1] spr_msr_gs_q ; // input=>spr_msr_gs ,act=>1'b1 + wire [0:`THREADS-1] spr_msr_pr_q ; // input=>spr_msr_pr ,act=>1'b1 + wire [0:`THREADS-1] spr_epcr_dgtmi_q ; // input=>spr_epcr_dgtmi ,act=>1'b1 + wire spr_ccr2_notlb_q ; // input=>spr_ccr2_notlb ,act=>1'b1 + wire [0:`THREADS-1] ex4_br_val_q ; // input=>br_dec_ex3_execute_vld ,act=>1'b1 + wire ex1_ord_q, ex0_ord ; // input=>ex0_ord ,act=>1'b1 + wire ex2_ord_q ; // input=>ex1_ord_q ,act=>1'b1 + wire ex3_ord_q ; // input=>ex2_ord_q ,act=>exx_act[2] + wire ex2_t1_v_q ; // input=>ex2_t1_v_q ,act=>exx_act[1] + wire ex2_t2_v_q ; // input=>ex1_t2_v_q ,act=>exx_act[1] + wire ex2_t3_v_q ; // input=>ex1_t3_v_q ,act=>exx_act[1] + wire [0:2] ex2_t1_t_q ; // input=>ex1_t1_t_q ,act=>exx_act[1] + wire [0:2] ex2_t2_t_q ; // input=>ex1_t2_t_q ,act=>exx_act[1] + wire [0:2] ex2_t3_t_q ; // input=>ex1_t3_t_q ,act=>exx_act[1] + wire ex3_t1_v_q ; // input=>ex2_t1_v_q ,act=>exx_act[2] + wire ex3_t2_v_q ; // input=>ex2_t2_v_q ,act=>exx_act[2] + wire ex3_t3_v_q ; // input=>ex2_t3_v_q ,act=>exx_act[2] + wire [0:2] ex3_t1_t_q ; // input=>ex2_t1_t_q ,act=>exx_act[2] + wire [0:2] ex3_t2_t_q ; // input=>ex2_t2_t_q ,act=>exx_act[2] + wire [0:2] ex3_t3_t_q ; // input=>ex2_t3_t_q ,act=>exx_act[2] + wire ex4_t1_v_q ; // input=>ex3_t1_v_q ,act=>exx_act[3] + wire ex4_t2_v_q ; // input=>ex3_t2_v_q ,act=>exx_act[3] + wire ex4_t3_v_q ; // input=>ex3_t3_v_q ,act=>exx_act[3] + wire [0:2] ex4_t1_t_q ; // input=>ex3_t1_t_q ,act=>exx_act[3] + wire [0:2] ex4_t2_t_q ; // input=>ex3_t2_t_q ,act=>exx_act[3] + wire [0:2] ex4_t3_t_q ; // input=>ex3_t3_t_q ,act=>exx_act[3] + wire [0:`GPR_POOL_ENC-1] ex4_t1_p_q ; // input=>ex3_t1_p_q ,act=>exx_act[3] + wire [XER_LEFT:`GPR_POOL_ENC-1] ex4_t2_p_q ; // input=>ex3_t2_p_q ,act=>exx_act[3] + wire [CR_LEFT:`GPR_POOL_ENC-1] ex4_t3_p_q ; // input=>ex3_t3_p_q ,act=>exx_act[3] + wire ex5_t1_v_q ; // input=>ex4_t1_v_q ,act=>exx_act[4] + wire ex5_t2_v_q ; // input=>ex4_t2_v_q ,act=>exx_act[4] + wire ex5_t3_v_q ; // input=>ex4_t3_v_q ,act=>exx_act[4] + wire [0:2] ex5_t1_t_q ; // input=>ex4_t1_t_q ,act=>exx_act[4] + wire [0:2] ex5_t2_t_q ; // input=>ex4_t2_t_q ,act=>exx_act[4] + wire [0:2] ex5_t3_t_q ; // input=>ex4_t3_t_q ,act=>exx_act[4] + wire [0:`GPR_POOL_ENC-1] ex5_t1_p_q ; // input=>ex4_t1_p_q ,act=>exx_act[4] + wire [XER_LEFT:`GPR_POOL_ENC-1] ex5_t2_p_q ; // input=>ex4_t2_p_q ,act=>exx_act[4] + wire [CR_LEFT:`GPR_POOL_ENC-1] ex5_t3_p_q ; // input=>ex4_t3_p_q ,act=>exx_act[4] + wire ex5_ord_t1_v_q ; // input=>ex4_t1_v_q ,act=>ex4_ord_act + wire ex5_ord_t2_v_q ; // input=>ex4_t2_v_q ,act=>ex4_ord_act + wire ex5_ord_t3_v_q ; // input=>ex4_t3_v_q ,act=>ex4_ord_act + wire [0:2] ex5_ord_t1_t_q ; // input=>ex4_t1_t_q ,act=>ex4_ord_act + wire [0:2] ex5_ord_t2_t_q ; // input=>ex4_t2_t_q ,act=>ex4_ord_act + wire [0:2] ex5_ord_t3_t_q ; // input=>ex4_t3_t_q ,act=>ex4_ord_act + wire [0:`GPR_POOL_ENC-1] ex5_ord_t1_p_q ; // input=>ex4_t1_p_q ,act=>ex4_ord_act + wire [XER_LEFT:`GPR_POOL_ENC-1] ex5_ord_t2_p_q ; // input=>ex4_t2_p_q ,act=>ex4_ord_act + wire [CR_LEFT:`GPR_POOL_ENC-1] ex5_ord_t3_p_q ; // input=>ex4_t3_p_q ,act=>ex4_ord_act + wire ex6_gpr_we_q, ex5_gpr_we ; // input=>ex5_gpr_we ,act=>1'b1 + wire ex6_xer_we_q, ex5_xer_we ; // input=>ex5_xer_we ,act=>1'b1 + wire ex6_cr_we_q, ex5_cr_we ; // input=>ex5_cr_we ,act=>1'b1 + wire [CR_LEFT:`GPR_POOL_ENC-1] ex6_cr_wa_q, ex5_cr_wa ; // input=>ex5_cr_wa ,act=>exx_act[5] + wire ex4_ctr_we_q, ex3_ctr_we ; // input=>ex3_ctr_we ,act=>1'b1 + wire ex4_lr_we_q, ex3_lr_we ; // input=>ex3_lr_we ,act=>1'b1 + wire [0:`GPR_POOL_ENC-1] ex6_t1_p_q, ex5_t1_p ; // input=>ex5_t1_p ,act=>exx_act[5] + wire [XER_LEFT:`GPR_POOL_ENC-1] ex6_t2_p_q, ex5_t2_p ; // input=>ex5_t2_p ,act=>exx_act[5] + wire spr_ccr2_en_attn_q ; // input=>spr_ccr2_en_attn ,act=>1'b1 + wire spr_ccr4_en_dnh_q ; // input=>spr_ccr4_en_dnh ,act=>1'b1 + wire spr_ccr2_en_pc_q ; // input=>spr_ccr2_en_pc ,act=>1'b1 + wire [0:`THREADS-1] ex2_ord_tid_q ; // input=>ex1_ord_val_q ,act=>ex1_ord_act + wire [0:`ITAG_SIZE_ENC-1] ex2_ord_itag_q ; // input=>ex1_itag_q ,act=>ex1_ord_act + wire ex2_ord_is_eratre_q ; // input=>ex1_is_eratre ,act=>ex1_ord_act + wire ex2_ord_is_eratwe_q ; // input=>ex1_is_eratwe ,act=>ex1_ord_act + wire ex2_ord_is_eratsx_q ; // input=>ex1_is_eratsx ,act=>ex1_ord_act + wire ex2_ord_is_eratilx_q ; // input=>ex1_is_eratilx ,act=>ex1_ord_act + wire ex2_ord_is_erativax_q ; // input=>ex1_is_erativax ,act=>ex1_ord_act + wire ex2_ord_is_tlbre_q ; // input=>ex1_is_tlbre ,act=>ex1_ord_act + wire ex2_ord_is_tlbwe_q ; // input=>ex1_is_tlbwe ,act=>ex1_ord_act + wire ex2_ord_is_tlbsx_q ; // input=>ex1_is_tlbsx ,act=>ex1_ord_act + wire ex2_ord_is_tlbsxr_q ; // input=>ex1_is_tlbsxr ,act=>ex1_ord_act + wire ex2_ord_is_tlbsrx_q ; // input=>ex1_is_tlbsrx ,act=>ex1_ord_act + wire ex2_ord_is_tlbivax_q ; // input=>ex1_is_tlbivax ,act=>ex1_ord_act + wire ex2_ord_is_tlbilx_q ; // input=>ex1_is_tlbilx ,act=>ex1_ord_act + wire [19:20] ex2_ord_tlb_ws_q ; // input=>ex1_instr_q[19:20] ,act=>ex1_ord_act + wire [8:10] ex2_ord_tlb_t_q ; // input=>ex1_instr_q[8:10] ,act=>ex1_ord_act + wire ex2_priv_excep_q, ex1_priv_excep ; // input=>ex1_priv_excep ,act=>exx_act[1] + wire ex2_hyp_priv_excep_q, ex1_hyp_priv_excep ; // input=>ex1_hyp_priv_excep ,act=>exx_act[1] + wire ex2_illegal_op_q, ex1_illegal_op ; // input=>ex1_illegal_op ,act=>exx_act[1] + wire ex2_flush2ucode_q, ex1_flush2ucode ; // input=>ex1_flush2ucode ,act=>1'b1 + wire ex2_tlb_illeg_q, ex1_tlb_illeg ; // input=>ex1_tlb_illeg ,act=>exx_act[1] + wire ex3_priv_excep_q ; // input=>ex2_priv_excep_q ,act=>exx_act[2] + wire ex3_hyp_priv_excep_q ; // input=>ex2_hyp_priv_excep_q ,act=>exx_act[2] + wire ex3_illegal_op_q ; // input=>ex2_illegal_op_q ,act=>exx_act[2] + wire ex3_flush2ucode_q, ex2_flush2ucode ; // input=>ex2_flush2ucode ,act=>1'b1 + wire ex4_flush2ucode_q, ex3_flush2ucode ; // input=>ex3_flush2ucode ,act=>1'b1 + wire ex1_ord_complete_q, ex0_ord_complete ; // input=>ex0_ord_complete ,act=>1'b1 + wire ex2_ord_complete_q, ex1_ord_complete ; // input=>ex1_ord_complete ,act=>1'b1 + wire ex3_ord_complete_q, ex2_ord_complete ; // input=>ex2_ord_complete ,act=>1'b1 + wire ex4_ord_complete_q, ex3_ord_complete ; // input=>ex3_ord_complete ,act=>1'b1 + wire ex5_ord_complete_q, ex4_ord_complete ; // input=>ex4_ord_complete ,act=>1'b1 + wire ex6_ord_complete_q, ex5_ord_complete ; // input=>ex5_ord_complete ,act=>1'b1 + wire [0:2] xu_iu_pri_q, xu_iu_pri_d ; // input=>xu_iu_pri_d ,act=>ex1_ord_act + wire [0:`THREADS-1] xu_iu_pri_val_q, xu_iu_pri_val_d ; // input=>xu_iu_pri_val_d ,act=>1'b1 + wire xu_iu_hold_val_q, xu_iu_hold_val_d ; // input=>xu_iu_hold_val_d ,act=>1'b1 + wire xu_lq_hold_val_q, xu_lq_hold_val_d ; // input=>xu_lq_hold_val_d ,act=>1'b1 + wire xu_mm_hold_val_q, xu_mm_hold_val_d ; // input=>xu_mm_hold_val_d ,act=>1'b1 + wire xu_iu_val_q, xu_iu_val_d ; // input=>xu_iu_val_d ,act=>1'b1 + wire xu_lq_val_q, xu_lq_val_d ; // input=>xu_lq_val_d ,act=>1'b1 + wire xu_mm_val_q, xu_mm_val_d ; // input=>xu_mm_val_d ,act=>1'b1 + wire [0:`THREADS-1] xu_iu_val_2_q, xu_iu_val_2_d ; // input=>xu_iu_val_2_d ,act=>1'b1 + wire [0:`THREADS-1] xu_lq_val_2_q, xu_lq_val_2_d ; // input=>xu_lq_val_2_d ,act=>1'b1 + wire [0:`THREADS-1] xu_mm_val_2_q, xu_mm_val_2_d ; // input=>xu_mm_val_2_d ,act=>1'b1 + wire ord_tlb_miss_q, ord_tlb_miss_d ; // input=>ord_tlb_miss_d ,act=>ord_outstanding_act + wire ord_lrat_miss_q, ord_lrat_miss_d ; // input=>ord_lrat_miss_d ,act=>ord_outstanding_act + wire ord_tlb_inelig_q, ord_tlb_inelig_d ; // input=>ord_tlb_inelig_d ,act=>ord_outstanding_act + wire ord_pt_fault_q, ord_pt_fault_d ; // input=>ord_pt_fault_d ,act=>ord_outstanding_act + wire ord_hv_priv_q, ord_hv_priv_d ; // input=>ord_hv_priv_d ,act=>ord_outstanding_act + wire ord_illeg_mmu_q, ord_illeg_mmu_d ; // input=>ord_illeg_mmu_d ,act=>ord_outstanding_act + wire ord_lq_flush_q, ord_lq_flush_d ; // input=>ord_lq_flush_d ,act=>ord_outstanding_act + wire ord_spr_priv_q, ord_spr_priv_d ; // input=>ord_spr_priv_d ,act=>ord_outstanding_act + wire ord_spr_illegal_spr_q, ord_spr_illegal_spr_d ; // input=>ord_spr_illegal_spr_d ,act=>ord_outstanding_act + wire ord_hyp_priv_spr_q, ord_hyp_priv_spr_d ; // input=>ord_hyp_priv_spr_d ,act=>ord_outstanding_act + wire ord_ex3_np1_flush_q, ord_ex3_np1_flush_d ; // input=>ord_ex3_np1_flush_d ,act=>ord_outstanding_act + wire ord_ill_tlb_q, ord_ill_tlb_d ; // input=>ord_ill_tlb_d ,act=>ord_outstanding_act + wire ord_priv_q, ord_priv_d ; // input=>ord_priv_d ,act=>ord_outstanding_act + wire ord_hyp_priv_q, ord_hyp_priv_d ; // input=>ord_hyp_priv_d ,act=>ord_outstanding_act + wire ord_hold_lq_q, ord_hold_lq_d ; // input=>ord_hold_lq_d ,act=>ord_outstanding_act + wire ord_outstanding_q, ord_outstanding_d ; // input=>ord_outstanding_d ,act=>ord_outstanding_act + wire ord_flushed_q, ord_flushed_d ; // input=>ord_flushed_d ,act=>ord_outstanding_act + wire ord_done_q, ord_done_d ; // input=>ord_done_d ,act=>1'b1 + wire ord_mmu_req_sent_q, ord_mmu_req_sent_d ; // input=>ord_mmu_req_sent_d ,act=>ord_outstanding_act + wire ord_core_block_q, ord_core_block_d ; // input=>ord_core_block_d ,act=>ord_outstanding_act + wire ord_ierat_par_err_q, ord_ierat_par_err_d ; // input=>ord_ierat_par_err_d ,act=>ord_outstanding_act + wire ord_derat_par_err_q, ord_derat_par_err_d ; // input=>ord_derat_par_err_d ,act=>ord_outstanding_act + wire ord_tlb_multihit_q, ord_tlb_multihit_d ; // input=>ord_tlb_multihit_d ,act=>ord_outstanding_act + wire ord_tlb_par_err_q, ord_tlb_par_err_d ; // input=>ord_tlb_par_err_d ,act=>ord_outstanding_act + wire ord_tlb_lru_par_err_q, ord_tlb_lru_par_err_d ; // input=>ord_tlb_lru_par_err_d ,act=>ord_outstanding_act + wire ord_local_snoop_reject_q, ord_local_snoop_reject_d ; // input=>ord_local_snoop_reject_d ,act=>ord_outstanding_act + wire [0:1] mmu_ord_n_flush_req_q, mmu_ord_n_flush_req_d ; // input=>mmu_ord_n_flush_req_d ,act=>1'b1 + wire [0:1] iu_ord_n_flush_req_q, iu_ord_n_flush_req_d ; // input=>iu_ord_n_flush_req_d ,act=>1'b1 + wire [0:1] lq_ord_n_flush_req_q, lq_ord_n_flush_req_d ; // input=>lq_ord_n_flush_req_d ,act=>1'b1 + wire ex4_np1_flush_q, ex3_np1_flush ; // input=>ex3_np1_flush ,act=>1'b1 + wire ex4_n_flush_q, ex3_n_flush ; // input=>ex3_n_flush ,act=>1'b1 + wire ex4_excep_val_q, ex3_excep_val ; // input=>ex3_excep_val ,act=>1'b1 + wire [0:4] ex4_excep_vector_q, ex3_excep_vector ; // input=>ex3_excep_vector ,act=>1'b1 + wire [0:2] ex2_ucode_q ; // input=>ex1_ucode_q ,act=>exx_act[1] + wire ex2_is_ehpriv_q, ex1_is_ehpriv ; // input=>ex1_is_ehpriv ,act=>exx_act[1] + wire ex3_is_ehpriv_q ; // input=>ex2_is_ehpriv_q ,act=>exx_act[2] + wire ex2_is_mtiar_q ; // input=>ex1_is_mtiar ,act=>exx_act[1] + wire ex3_mtiar_sel_q, ex2_mtiar_sel ; // input=>ex2_mtiar_sel ,act=>1'b1 + wire ord_mtiar_q, ord_mtiar_d ; // input=>ord_mtiar_d ,act=>1'b1 + wire [0:31] ord_instr_q, ord_instr_d ; // input=>ord_instr_d ,act=>ex1_ord_valid + wire ex2_is_erativax_q ; // input=>ex1_is_erativax ,act=>ex1_ord_act + wire [0:`THREADS-1] xu0_iu_mtiar_q, xu0_iu_mtiar_d ; // input=>xu0_iu_mtiar_d ,act=>1'b1 + wire ord_is_cp_next_q, ord_is_cp_next ; // input=>ord_is_cp_next ,act=>1'b1 + wire ord_flush_1_q ; // input=>ord_spec_flush ,act=>1'b1 + wire ord_flush_2_q ; // input=>ord_flush_1_q ,act=>1'b1 + wire [0:1] spr_mmucr0_tlbsel_q[0:`THREADS-1], spr_mmucr0_tlbsel_d[0:`THREADS-1] ; // input=>spr_mmucr0_tlbsel_d ,act=>1'b1 + wire mm_xu_tlbwe_binv_q ; // input=>mm_xu_tlbwe_binv ,act=>1'b1 + wire [0:31] ex2_instr_q ; // input=>ex1_instr_q ,act=>exx_act[1] + wire [0:31] ex3_instr_q ; // input=>ex2_instr_q ,act=>exx_act[2] + wire [0:31] ex4_instr_q ; // input=>ex3_instr_q ,act=>exx_act[3] + wire ex4_hpriv_q, ex3_hpriv ; // input=>ex3_hpriv ,act=>1'b1 + wire ex2_any_popcnt_q, ex1_any_popcnt ; // input=>ex1_any_popcnt ,act=>exx_act[1] + wire ex3_any_popcnt_q ; // input=>ex2_any_popcnt_q ,act=>exx_act[2] + wire ex4_any_popcnt_q ; // input=>ex3_any_popcnt_q ,act=>exx_act[3] + wire ex2_any_cntlz_q, ex1_any_cntlz ; // input=>ex1_any_cntlz ,act=>exx_act[1] + wire ex3_any_cntlz_q ; // input=>ex2_any_cntlz_q ,act=>exx_act[2] + wire ex2_is_bpermd_q ; // input=>ex1_is_bpermd ,act=>exx_act[1] + wire ex3_is_bpermd_q ; // input=>ex2_is_bpermd_q ,act=>exx_act[2] + wire ex2_is_dlmzb_q ; // input=>ex1_is_dlmzb ,act=>exx_act[1] + wire ex3_is_dlmzb_q ; // input=>ex2_is_dlmzb_q ,act=>exx_act[2] + wire ex2_mul_multicyc_q, ex1_mul_multicyc ; // input=>ex1_mul_multicyc ,act=>1'b1 + wire ex3_mul_multicyc_q ; // input=>ex2_mul_multicyc_q ,act=>1'b1 + wire ex2_mul_2c_q, ex1_mul_2c ; // input=>ex1_mul_2c ,act=>1'b1 + wire ex2_mul_3c_q, ex1_mul_3c ; // input=>ex1_mul_3c ,act=>1'b1 + wire ex2_mul_4c_q, ex1_mul_4c ; // input=>ex1_mul_4c ,act=>1'b1 + wire ex3_mul_2c_q ; // input=>ex2_mul_2c_q ,act=>1'b1 + wire ex3_mul_3c_q ; // input=>ex2_mul_3c_q ,act=>1'b1 + wire ex3_mul_4c_q ; // input=>ex2_mul_4c_q ,act=>1'b1 + wire ex4_mul_2c_q, ex4_mul_2c_d ; // input=>ex4_mul_2c_d ,act=>1'b1 + wire ex4_mul_3c_q, ex4_mul_3c_d ; // input=>ex4_mul_3c_d ,act=>1'b1 + wire ex4_mul_4c_q, ex4_mul_4c_d ; // input=>ex4_mul_4c_d ,act=>1'b1 + wire ex5_mul_3c_q, ex5_mul_3c_d ; // input=>ex5_mul_3c_d ,act=>1'b1 + wire ex5_mul_4c_q, ex5_mul_4c_d ; // input=>ex5_mul_4c_d ,act=>1'b1 + wire ex6_mul_4c_q, ex6_mul_4c_d ; // input=>ex6_mul_4c_d ,act=>1'b1 + wire [0:`THREADS-1] exx_mul_tid_q, exx_mul_tid_d ; // input=>exx_mul_tid_d ,act=>1'b1 + wire ex2_is_mtspr_q ; // input=>ex1_is_mtspr ,act=>exx_act[1] + wire ex3_is_mtspr_q ; // input=>ex2_is_mtspr_q ,act=>exx_act[2] + wire ex6_ram_active_q, ex6_ram_active_d ; // input=>ex6_ram_active_d ,act=>1'b1 + wire [0:`THREADS-1] ex6_tid_q, ex6_tid_d ; // input=>ex6_tid_d ,act=>1'b1 + wire [0:`THREADS-1] ex1_spec_flush_q ; // input=>rv_xu0_ex0_spec_flush ,act=>1'b1 + wire [0:`THREADS-1] ex2_spec_flush_q ; // input=>rv_xu0_ex1_spec_flush ,act=>1'b1 + wire [0:`THREADS-1] ex3_spec_flush_q ; // input=>rv_xu0_ex2_spec_flush ,act=>1'b1 + wire [0:`THREADS-1] ord_async_flush_before_q, ord_async_flush_before_d ; // input=>ord_async_flush_before_d ,act=>1'b1 + wire [0:`THREADS-1] ord_async_flush_after_q, ord_async_flush_after_d ; // input=>ord_async_flush_after_d ,act=>1'b1 + wire ord_async_credit_wait_q, ord_async_credit_wait_d ; // input=>ord_async_credit_wait_d ,act=>1'b1 + wire [0:`THREADS-1] async_flush_req_q, async_flush_req_d ; // input=>async_flush_req_d ,act=>1'b1 + wire [0:`THREADS-1] async_flush_req_2_q ; // input=>async_flush_req_q ,act=>1'b1 + wire [0:`THREADS-1] iu_async_complete_q ; // input=>iu_xu_async_complete ,act=>1'b1 + wire iu_xu_credits_returned_q ; // input=>iu_xu_credits_returned ,act=>1'b1 + wire ex2_any_mfspr_q, ex1_any_mfspr ; // input=>ex1_any_mfspr ,act=>exx_act[1] + wire ex3_any_mfspr_q, ex2_any_mfspr ; // input=>ex2_any_mfspr ,act=>exx_act[2] + wire ex2_any_mtspr_q, ex1_any_mtspr ; // input=>ex1_any_mtspr ,act=>exx_act[1] + wire ex3_any_mtspr_q, ex2_any_mtspr ; // input=>ex2_any_mtspr ,act=>exx_act[2] + wire [0:3] ex4_perf_event_q ; // input=>ex3_perf_event ,act=>exx_act[3] + wire ord_any_mfspr_q ; // input=>ex1_any_mfspr ,act=>ex1_ord_act + wire ord_any_mtspr_q ; // input=>ex1_any_mtspr ,act=>ex1_ord_act + wire [0:5] ord_timer_q, ord_timer_d ; // input=>ord_timer_d ,act=>ord_outstanding_act + wire [0:1] ord_timeout_q, ord_timeout_d ; // input=>ord_timeout_d ,act=>1'b1 + // Scanchain + localparam exx_act_offset = 0; + localparam ex1_s2_v_offset = exx_act_offset + 5; + localparam ex1_s2_t_offset = ex1_s2_v_offset + 1; + localparam ex1_s3_v_offset = ex1_s2_t_offset + 3; + localparam ex1_s3_t_offset = ex1_s3_v_offset + 1; + localparam ex1_t1_t_offset = ex1_s3_t_offset + 3; + localparam ex1_t2_t_offset = ex1_t1_t_offset + 3; + localparam ex1_t3_t_offset = ex1_t2_t_offset + 3; + localparam ex1_t1_v_offset = ex1_t3_t_offset + 3; + localparam ex1_t2_v_offset = ex1_t1_v_offset + 1; + localparam ex1_t3_v_offset = ex1_t2_v_offset + 1; + localparam ex1_t1_p_offset = ex1_t3_v_offset + 1; + localparam ex1_t2_p_offset = ex1_t1_p_offset + `GPR_POOL_ENC; + localparam ex1_t3_p_offset = ex1_t2_p_offset + `XER_POOL_ENC; + localparam ex1_instr_offset = ex1_t3_p_offset + `CR_POOL_ENC; + localparam ex1_ucode_offset = ex1_instr_offset + 32; + localparam ex1_itag_offset = ex1_ucode_offset + 3; + localparam ex2_add_ci_sel_offset = ex1_itag_offset + `ITAG_SIZE_ENC; + localparam ex2_itag_offset = ex2_add_ci_sel_offset + 2; + localparam ex2_t1_p_offset = ex2_itag_offset + `ITAG_SIZE_ENC; + localparam ex2_t2_p_offset = ex2_t1_p_offset + `GPR_POOL_ENC; + localparam ex2_t3_p_offset = ex2_t2_p_offset + `XER_POOL_ENC; + localparam ex3_t1_p_offset = ex2_t3_p_offset + `CR_POOL_ENC; + localparam ex3_t2_p_offset = ex3_t1_p_offset + `GPR_POOL_ENC; + localparam ex3_t3_p_offset = ex3_t2_p_offset + `XER_POOL_ENC; + localparam ex3_itag_offset = ex3_t3_p_offset + `CR_POOL_ENC; + localparam ex4_itag_offset = ex3_itag_offset + `ITAG_SIZE_ENC; + localparam cp_flush_offset = ex4_itag_offset + `ITAG_SIZE_ENC; + localparam ex0_val_offset = cp_flush_offset + `THREADS; + localparam ex1_val_offset = ex0_val_offset + `THREADS; + localparam ex2_val_offset = ex1_val_offset + `THREADS; + localparam ex3_val_offset = ex2_val_offset + `THREADS; + localparam ex4_val_offset = ex3_val_offset + `THREADS; + localparam ex5_val_offset = ex4_val_offset + `THREADS; + localparam ex6_val_offset = ex5_val_offset + `THREADS; + localparam ex1_ord_val_offset = ex6_val_offset + `THREADS; + localparam ex2_ord_val_offset = ex1_ord_val_offset + `THREADS; + localparam ex3_ord_val_offset = ex2_ord_val_offset + `THREADS; + localparam ex4_ord_val_offset = ex3_ord_val_offset + `THREADS; + localparam spr_msr_cm_offset = ex4_ord_val_offset + `THREADS; + localparam spr_msr_gs_offset = spr_msr_cm_offset + `THREADS; + localparam spr_msr_pr_offset = spr_msr_gs_offset + `THREADS; + localparam spr_epcr_dgtmi_offset = spr_msr_pr_offset + `THREADS; + localparam spr_ccr2_notlb_offset = spr_epcr_dgtmi_offset + `THREADS; + localparam ex4_br_val_offset = spr_ccr2_notlb_offset + 1; + localparam ex1_ord_offset = ex4_br_val_offset + `THREADS; + localparam ex2_ord_offset = ex1_ord_offset + 1; + localparam ex3_ord_offset = ex2_ord_offset + 1; + localparam ex2_t1_v_offset = ex3_ord_offset + 1; + localparam ex2_t2_v_offset = ex2_t1_v_offset + 1; + localparam ex2_t3_v_offset = ex2_t2_v_offset + 1; + localparam ex2_t1_t_offset = ex2_t3_v_offset + 1; + localparam ex2_t2_t_offset = ex2_t1_t_offset + 3; + localparam ex2_t3_t_offset = ex2_t2_t_offset + 3; + localparam ex3_t1_v_offset = ex2_t3_t_offset + 3; + localparam ex3_t2_v_offset = ex3_t1_v_offset + 1; + localparam ex3_t3_v_offset = ex3_t2_v_offset + 1; + localparam ex3_t1_t_offset = ex3_t3_v_offset + 1; + localparam ex3_t2_t_offset = ex3_t1_t_offset + 3; + localparam ex3_t3_t_offset = ex3_t2_t_offset + 3; + localparam ex4_t1_v_offset = ex3_t3_t_offset + 3; + localparam ex4_t2_v_offset = ex4_t1_v_offset + 1; + localparam ex4_t3_v_offset = ex4_t2_v_offset + 1; + localparam ex4_t1_t_offset = ex4_t3_v_offset + 1; + localparam ex4_t2_t_offset = ex4_t1_t_offset + 3; + localparam ex4_t3_t_offset = ex4_t2_t_offset + 3; + localparam ex4_t1_p_offset = ex4_t3_t_offset + 3; + localparam ex4_t2_p_offset = ex4_t1_p_offset + `GPR_POOL_ENC; + localparam ex4_t3_p_offset = ex4_t2_p_offset + -XER_LEFT+`GPR_POOL_ENC; + localparam ex5_t1_v_offset = ex4_t3_p_offset + -CR_LEFT+`GPR_POOL_ENC; + localparam ex5_t2_v_offset = ex5_t1_v_offset + 1; + localparam ex5_t3_v_offset = ex5_t2_v_offset + 1; + localparam ex5_t1_t_offset = ex5_t3_v_offset + 1; + localparam ex5_t2_t_offset = ex5_t1_t_offset + 3; + localparam ex5_t3_t_offset = ex5_t2_t_offset + 3; + localparam ex5_t1_p_offset = ex5_t3_t_offset + 3; + localparam ex5_t2_p_offset = ex5_t1_p_offset + `GPR_POOL_ENC; + localparam ex5_t3_p_offset = ex5_t2_p_offset + -XER_LEFT+`GPR_POOL_ENC; + localparam ex5_ord_t1_v_offset = ex5_t3_p_offset + -CR_LEFT+`GPR_POOL_ENC; + localparam ex5_ord_t2_v_offset = ex5_ord_t1_v_offset + 1; + localparam ex5_ord_t3_v_offset = ex5_ord_t2_v_offset + 1; + localparam ex5_ord_t1_t_offset = ex5_ord_t3_v_offset + 1; + localparam ex5_ord_t2_t_offset = ex5_ord_t1_t_offset + 3; + localparam ex5_ord_t3_t_offset = ex5_ord_t2_t_offset + 3; + localparam ex5_ord_t1_p_offset = ex5_ord_t3_t_offset + 3; + localparam ex5_ord_t2_p_offset = ex5_ord_t1_p_offset + `GPR_POOL_ENC; + localparam ex5_ord_t3_p_offset = ex5_ord_t2_p_offset + -XER_LEFT+`GPR_POOL_ENC; + localparam ex6_gpr_we_offset = ex5_ord_t3_p_offset + -CR_LEFT+`GPR_POOL_ENC; + localparam ex6_xer_we_offset = ex6_gpr_we_offset + 1; + localparam ex6_cr_we_offset = ex6_xer_we_offset + 1; + localparam ex6_cr_wa_offset = ex6_cr_we_offset + 1; + localparam ex4_ctr_we_offset = ex6_cr_wa_offset + -CR_LEFT+`GPR_POOL_ENC; + localparam ex4_lr_we_offset = ex4_ctr_we_offset + 1; + localparam ex6_t1_p_offset = ex4_lr_we_offset + 1; + localparam ex6_t2_p_offset = ex6_t1_p_offset + `GPR_POOL_ENC; + localparam spr_ccr2_en_attn_offset = ex6_t2_p_offset + -XER_LEFT+`GPR_POOL_ENC; + localparam spr_ccr4_en_dnh_offset = spr_ccr2_en_attn_offset + 1; + localparam spr_ccr2_en_pc_offset = spr_ccr4_en_dnh_offset + 1; + localparam ex2_ord_tid_offset = spr_ccr2_en_pc_offset + 1; + localparam ex2_ord_itag_offset = ex2_ord_tid_offset + `THREADS; + localparam ex2_ord_is_eratre_offset = ex2_ord_itag_offset + `ITAG_SIZE_ENC; + localparam ex2_ord_is_eratwe_offset = ex2_ord_is_eratre_offset + 1; + localparam ex2_ord_is_eratsx_offset = ex2_ord_is_eratwe_offset + 1; + localparam ex2_ord_is_eratilx_offset = ex2_ord_is_eratsx_offset + 1; + localparam ex2_ord_is_erativax_offset = ex2_ord_is_eratilx_offset + 1; + localparam ex2_ord_is_tlbre_offset = ex2_ord_is_erativax_offset + 1; + localparam ex2_ord_is_tlbwe_offset = ex2_ord_is_tlbre_offset + 1; + localparam ex2_ord_is_tlbsx_offset = ex2_ord_is_tlbwe_offset + 1; + localparam ex2_ord_is_tlbsxr_offset = ex2_ord_is_tlbsx_offset + 1; + localparam ex2_ord_is_tlbsrx_offset = ex2_ord_is_tlbsxr_offset + 1; + localparam ex2_ord_is_tlbivax_offset = ex2_ord_is_tlbsrx_offset + 1; + localparam ex2_ord_is_tlbilx_offset = ex2_ord_is_tlbivax_offset + 1; + localparam ex2_ord_tlb_ws_offset = ex2_ord_is_tlbilx_offset + 1; + localparam ex2_ord_tlb_t_offset = ex2_ord_tlb_ws_offset + 2; + localparam ex2_priv_excep_offset = ex2_ord_tlb_t_offset + 3; + localparam ex2_hyp_priv_excep_offset = ex2_priv_excep_offset + 1; + localparam ex2_illegal_op_offset = ex2_hyp_priv_excep_offset + 1; + localparam ex2_flush2ucode_offset = ex2_illegal_op_offset + 1; + localparam ex2_tlb_illeg_offset = ex2_flush2ucode_offset + 1; + localparam ex3_priv_excep_offset = ex2_tlb_illeg_offset + 1; + localparam ex3_hyp_priv_excep_offset = ex3_priv_excep_offset + 1; + localparam ex3_illegal_op_offset = ex3_hyp_priv_excep_offset + 1; + localparam ex3_flush2ucode_offset = ex3_illegal_op_offset + 1; + localparam ex4_flush2ucode_offset = ex3_flush2ucode_offset + 1; + localparam ex1_ord_complete_offset = ex4_flush2ucode_offset + 1; + localparam ex2_ord_complete_offset = ex1_ord_complete_offset + 1; + localparam ex3_ord_complete_offset = ex2_ord_complete_offset + 1; + localparam ex4_ord_complete_offset = ex3_ord_complete_offset + 1; + localparam ex5_ord_complete_offset = ex4_ord_complete_offset + 1; + localparam ex6_ord_complete_offset = ex5_ord_complete_offset + 1; + localparam xu_iu_pri_offset = ex6_ord_complete_offset + 1; + localparam xu_iu_pri_val_offset = xu_iu_pri_offset + 3; + localparam xu_iu_hold_val_offset = xu_iu_pri_val_offset + `THREADS; + localparam xu_lq_hold_val_offset = xu_iu_hold_val_offset + 1; + localparam xu_mm_hold_val_offset = xu_lq_hold_val_offset + 1; + localparam xu_iu_val_offset = xu_mm_hold_val_offset + 1; + localparam xu_lq_val_offset = xu_iu_val_offset + 1; + localparam xu_mm_val_offset = xu_lq_val_offset + 1; + localparam xu_iu_val_2_offset = xu_mm_val_offset + 1; + localparam xu_lq_val_2_offset = xu_iu_val_2_offset + `THREADS; + localparam xu_mm_val_2_offset = xu_lq_val_2_offset + `THREADS; + localparam ord_tlb_miss_offset = xu_mm_val_2_offset + `THREADS; + localparam ord_lrat_miss_offset = ord_tlb_miss_offset + 1; + localparam ord_tlb_inelig_offset = ord_lrat_miss_offset + 1; + localparam ord_pt_fault_offset = ord_tlb_inelig_offset + 1; + localparam ord_hv_priv_offset = ord_pt_fault_offset + 1; + localparam ord_illeg_mmu_offset = ord_hv_priv_offset + 1; + localparam ord_lq_flush_offset = ord_illeg_mmu_offset + 1; + localparam ord_spr_priv_offset = ord_lq_flush_offset + 1; + localparam ord_spr_illegal_spr_offset = ord_spr_priv_offset + 1; + localparam ord_hyp_priv_spr_offset = ord_spr_illegal_spr_offset + 1; + localparam ord_ex3_np1_flush_offset = ord_hyp_priv_spr_offset + 1; + localparam ord_ill_tlb_offset = ord_ex3_np1_flush_offset + 1; + localparam ord_priv_offset = ord_ill_tlb_offset + 1; + localparam ord_hyp_priv_offset = ord_priv_offset + 1; + localparam ord_hold_lq_offset = ord_hyp_priv_offset + 1; + localparam ord_outstanding_offset = ord_hold_lq_offset + 1; + localparam ord_flushed_offset = ord_outstanding_offset + 1; + localparam ord_done_offset = ord_flushed_offset + 1; + localparam ord_mmu_req_sent_offset = ord_done_offset + 1; + localparam ord_core_block_offset = ord_mmu_req_sent_offset + 1; + localparam ord_ierat_par_err_offset = ord_core_block_offset + 1; + localparam ord_derat_par_err_offset = ord_ierat_par_err_offset + 1; + localparam ord_tlb_multihit_offset = ord_derat_par_err_offset + 1; + localparam ord_tlb_par_err_offset = ord_tlb_multihit_offset + 1; + localparam ord_tlb_lru_par_err_offset = ord_tlb_par_err_offset + 1; + localparam ord_local_snoop_reject_offset = ord_tlb_lru_par_err_offset + 1; + localparam mmu_ord_n_flush_req_offset = ord_local_snoop_reject_offset + 1; + localparam iu_ord_n_flush_req_offset = mmu_ord_n_flush_req_offset + 2; + localparam lq_ord_n_flush_req_offset = iu_ord_n_flush_req_offset + 2; + localparam ex4_np1_flush_offset = lq_ord_n_flush_req_offset + 2; + localparam ex4_n_flush_offset = ex4_np1_flush_offset + 1; + localparam ex4_excep_val_offset = ex4_n_flush_offset + 1; + localparam ex4_excep_vector_offset = ex4_excep_val_offset + 1; + localparam ex2_ucode_offset = ex4_excep_vector_offset + 5; + localparam ex2_is_ehpriv_offset = ex2_ucode_offset + 3; + localparam ex3_is_ehpriv_offset = ex2_is_ehpriv_offset + 1; + localparam ex2_is_mtiar_offset = ex3_is_ehpriv_offset + 1; + localparam ex3_mtiar_sel_offset = ex2_is_mtiar_offset + 1; + localparam ord_mtiar_offset = ex3_mtiar_sel_offset + 1; + localparam ord_instr_offset = ord_mtiar_offset + 1; + localparam ex2_is_erativax_offset = ord_instr_offset + 32; + localparam xu0_iu_mtiar_offset = ex2_is_erativax_offset + 1; + localparam ord_is_cp_next_offset = xu0_iu_mtiar_offset + `THREADS; + localparam ord_flush_1_offset = ord_is_cp_next_offset + 1; + localparam ord_flush_2_offset = ord_flush_1_offset + 1; + localparam spr_mmucr0_tlbsel_offset = ord_flush_2_offset + 1; + localparam mm_xu_tlbwe_binv_offset = spr_mmucr0_tlbsel_offset + `THREADS*2; + localparam ex2_instr_offset = mm_xu_tlbwe_binv_offset + 1; + localparam ex3_instr_offset = ex2_instr_offset + 32; + localparam ex4_instr_offset = ex3_instr_offset + 32; + localparam ex4_hpriv_offset = ex4_instr_offset + 32; + localparam ex2_any_popcnt_offset = ex4_hpriv_offset + 1; + localparam ex3_any_popcnt_offset = ex2_any_popcnt_offset + 1; + localparam ex4_any_popcnt_offset = ex3_any_popcnt_offset + 1; + localparam ex2_any_cntlz_offset = ex4_any_popcnt_offset + 1; + localparam ex3_any_cntlz_offset = ex2_any_cntlz_offset + 1; + localparam ex2_is_bpermd_offset = ex3_any_cntlz_offset + 1; + localparam ex3_is_bpermd_offset = ex2_is_bpermd_offset + 1; + localparam ex2_is_dlmzb_offset = ex3_is_bpermd_offset + 1; + localparam ex3_is_dlmzb_offset = ex2_is_dlmzb_offset + 1; + localparam ex2_mul_multicyc_offset = ex3_is_dlmzb_offset + 1; + localparam ex3_mul_multicyc_offset = ex2_mul_multicyc_offset + 1; + localparam ex2_mul_2c_offset = ex3_mul_multicyc_offset + 1; + localparam ex2_mul_3c_offset = ex2_mul_2c_offset + 1; + localparam ex2_mul_4c_offset = ex2_mul_3c_offset + 1; + localparam ex3_mul_2c_offset = ex2_mul_4c_offset + 1; + localparam ex3_mul_3c_offset = ex3_mul_2c_offset + 1; + localparam ex3_mul_4c_offset = ex3_mul_3c_offset + 1; + localparam ex4_mul_2c_offset = ex3_mul_4c_offset + 1; + localparam ex4_mul_3c_offset = ex4_mul_2c_offset + 1; + localparam ex4_mul_4c_offset = ex4_mul_3c_offset + 1; + localparam ex5_mul_3c_offset = ex4_mul_4c_offset + 1; + localparam ex5_mul_4c_offset = ex5_mul_3c_offset + 1; + localparam ex6_mul_4c_offset = ex5_mul_4c_offset + 1; + localparam exx_mul_tid_offset = ex6_mul_4c_offset + 1; + localparam ex2_is_mtspr_offset = exx_mul_tid_offset + `THREADS; + localparam ex3_is_mtspr_offset = ex2_is_mtspr_offset + 1; + localparam ex6_ram_active_offset = ex3_is_mtspr_offset + 1; + localparam ex6_tid_offset = ex6_ram_active_offset + 1; + localparam ex1_spec_flush_offset = ex6_tid_offset + `THREADS; + localparam ex2_spec_flush_offset = ex1_spec_flush_offset + `THREADS; + localparam ex3_spec_flush_offset = ex2_spec_flush_offset + `THREADS; + localparam ord_async_flush_before_offset = ex3_spec_flush_offset + `THREADS; + localparam ord_async_flush_after_offset = ord_async_flush_before_offset + `THREADS; + localparam ord_async_credit_wait_offset = ord_async_flush_after_offset + `THREADS; + localparam async_flush_req_offset = ord_async_credit_wait_offset + 1; + localparam async_flush_req_2_offset = async_flush_req_offset + `THREADS; + localparam iu_async_complete_offset = async_flush_req_2_offset + `THREADS; + localparam iu_xu_credits_returned_offset = iu_async_complete_offset + `THREADS; + localparam ex2_any_mfspr_offset = iu_xu_credits_returned_offset + 1; + localparam ex3_any_mfspr_offset = ex2_any_mfspr_offset + 1; + localparam ex2_any_mtspr_offset = ex3_any_mfspr_offset + 1; + localparam ex3_any_mtspr_offset = ex2_any_mtspr_offset + 1; + localparam ex4_perf_event_offset = ex3_any_mtspr_offset + 1; + localparam ord_any_mfspr_offset = ex4_perf_event_offset + 4; + localparam ord_any_mtspr_offset = ord_any_mfspr_offset + 1; + localparam ord_timer_offset = ord_any_mtspr_offset + 1; + localparam ord_timeout_offset = ord_timer_offset + 6; + localparam scan_right = ord_timeout_offset + 2; + localparam DEX0 = 0; + localparam DEX1 = 0; + localparam DEX2 = 0; + localparam DEX3 = 0; + localparam DEX4 = 0; + localparam DEX5 = 0; + localparam DEX6 = 0; + localparam DEX7 = 0; + localparam DEX8 = 0; + localparam DX = 0; + wire [0:scan_right-1] siv; + wire [0:scan_right-1] sov; + // Signals + wire [0:5] exx_act; + wire ex0_is_b, ex0_is_bc, ex0_is_addi, ex0_is_addic, ex0_is_addicr, ex0_is_addme, + ex0_is_addis, ex0_is_addze, ex0_is_andir, ex0_is_andisr, ex0_is_cmpi, ex0_is_cmpli, + ex0_is_mulli, ex0_is_neg, ex0_is_ori, ex0_is_oris, ex0_is_subfic, ex0_is_subfze, + ex0_is_twi, ex0_is_tdi, ex0_is_xori, ex0_is_xoris, ex0_is_subfme, + ex0_is_mtcrf, ex0_is_mtmsr, ex0_is_mtspr, ex0_is_wrtee, + ex0_is_wrteei, ex0_is_eratwe, ex0_is_erativax, ex0_is_eratsx; + wire ex1_opcode_is_31, ex1_opcode_is_19, ex1_opcode_is_0; + wire ex1_is_adde, ex1_is_addi, ex1_is_addic, ex1_is_addicr, ex1_is_addis, ex1_is_addme, + ex1_is_addze, ex1_is_andir, ex1_is_andisr, ex1_is_cmp, ex1_is_cmpi, ex1_is_cmpl, + ex1_is_cmpli, ex1_is_neg, ex1_is_ori, ex1_is_mulldo, ex1_is_dnh, + ex1_is_mulhd, ex1_is_mulhdu, ex1_is_mulhw, ex1_is_mulhwu, ex1_is_mulld, ex1_is_attn, + ex1_is_mulli, ex1_is_mullw, ex1_is_divd, ex1_is_divdu, ex1_is_divw, ex1_is_divwu, + ex1_is_divwe, ex1_is_divweu, ex1_is_divde, ex1_is_divdeu, ex1_is_mflr, ex1_is_mfxer, + ex1_is_mfctr, ex1_is_mfcr, ex1_is_mtcrf, ex1_is_mtiar, ex1_is_eratilx, ex1_is_erativax, + ex1_is_eratre, ex1_is_eratsx, ex1_is_eratwe, ex1_is_tlbilx, ex1_is_tlbivax, ex1_is_tlbre, + ex1_is_tlbsx, ex1_is_tlbsxr, ex1_is_tlbsrx, ex1_is_mtxer, ex1_is_tlbwe, ex1_is_mftar, + ex1_is_bc, ex1_is_wrtee, ex1_is_wrteei, ex1_is_mtmsr, ex1_is_mtspr, ex1_is_msgclr, + ex1_is_oris, ex1_is_subf, + ex1_is_subfc, ex1_is_subfe, ex1_is_subfic, ex1_is_subfme, ex1_is_subfze, ex1_is_td, + ex1_is_tdi, ex1_is_tw, ex1_is_twi, ex1_is_xori, ex1_is_xoris, ex1_is_isel, + ex1_is_pri1, ex1_is_pri2, ex1_is_pri3, ex1_is_pri4, ex1_is_pri5, ex1_is_pri6, + ex1_is_pri7, ex1_is_add, ex1_is_addc, ex1_is_srad, ex1_is_sradi, ex1_is_sraw, + ex1_is_srawi, ex1_is_popcntb, ex1_is_popcntw, ex1_is_popcntd, ex1_is_cntlzw, ex1_is_cntlzd, + ex1_is_bpermd, ex1_is_dlmzb, ex1_is_addg6s, ex1_is_cdtbcd, ex1_is_cbcdtd, ex1_is_mfspr, + ex1_is_mfmsr, ex1_is_mftb; + wire [0:`THREADS-1] ex0_flush; + wire [0:`THREADS-1] ex1_flush; + wire [0:`THREADS-1] ex2_flush; + wire [0:`THREADS-1] ex3_flush; + wire ord_flush; + wire ex1_ord_valid; + wire ex2_ord_valid; +// wire ex3_ord_valid; + wire ex1_valid; + wire ex3_valid; +// wire ex4_valid; + wire ex5_valid; + wire ex6_valid; + wire ex1_add_rs1_inv; + wire ex1_any_trap; + wire ex1_any_cmpl; + wire ex1_any_cmp; + wire ex1_alu_cmp; + wire ex1_any_tw; + wire ex1_any_td; + wire ex1_force_64b_cmp; + wire ex1_force_32b_cmp; + wire ex0_use_imm; + wire ex1_imm_size; + wire ex1_imm_signext; + wire ex1_shift_imm; + wire ex1_zero_imm; + wire ex1_ones_imm; + wire [6:31] ex1_extd_imm; + wire [64-`GPR_WIDTH:63] ex1_shifted_imm; + wire ex1_tlb_illeg_ws; + wire ex1_tlb_illeg_ws2; + wire ex1_tlb_illeg_ws3; + wire ex1_tlb_illeg_t; + wire ex1_tlb_illeg_sel; + wire [0:`THREADS-1] ex6_val; + wire ex1_mul_val; + wire ex1_div_val; + wire [0:2] ex1_div_ctr_sel; + wire ex5_t1_v; + wire ex5_t2_v; + wire ex5_t3_v; + wire [0:2] ex5_t1_t; + wire [0:2] ex5_t2_t; + wire [0:2] ex5_t3_t; + wire ex4_ord_act; + wire ex1_ord_act; + wire ex5_cr1_we; + wire ex5_cr3_we; + wire [CR_LEFT:`GPR_POOL_ENC-1] ex5_t3_p; + wire ex1_spr_msr_cm_int; + wire ord_write_gpr; + wire ord_read_gpr; + wire mmu_ord_itag_match; + wire ord_other; + wire spr_ord_done; + wire ex1_any_pri; + wire [0:`THREADS-1] xu_iu_pri_val_int; + wire ex2_ord_erat_val; + wire ex2_ord_mmu_val; + wire [0:16] ex3_excep_cond; + wire [0:16] ex3_excep_pri; + wire mmu_error; + wire ex3_ord_np1_flush; + wire cp_flush_ord; + wire cp_flush_ord_tid; + wire ex6_ord_complete; + wire [0:`THREADS-1] ex1_tid; + wire ord_spec_flush; + wire ex1_ord_capt; + wire ex0_mul_insert; + wire ex3_mul_insert; + wire [0:`THREADS-1] ex2_ord_cp_next_cmp; + wire [0:1] ex0_tlbsel; + wire [0:1] ex1_tlbsel; + wire [0:1] ex2_tlbsel; + wire ex0_rs1_sel_zero_trm1; + wire ex1_is_credit_wait; + wire ex1_async_flush_before; + wire ex1_async_flush_after; + wire [0:`THREADS-1] ord_async_flush_before_set; + wire [0:`THREADS-1] ord_async_flush_after_set; + wire ord_async_credit_wait_set; + wire ord_async_done; + wire ex0_opcode_is_19; + wire ex0_opcode_is_31; + wire [0:`THREADS-1] ex3_tid; + wire [0:3] ex3_perf_event; + wire ord_outstanding_act; + wire ord_waiting; + + wire unused; + + //!! Bugspray Include: xu0_dec; + + //------------------------------------------------------------------------- + // Valids / Act + //------------------------------------------------------------------------- + assign dec_ex0_flush = ex0_flush; + assign dec_ex1_flush = ex1_flush; + assign dec_ex2_flush = ex2_flush; + assign dec_ex3_flush = ex3_flush; + assign dec_cp_flush = cp_flush_q; + + assign ex0_flush = cp_flush_q; + assign ex1_flush = cp_flush_q | ex1_spec_flush_q; + assign ex2_flush = cp_flush_q | ex2_spec_flush_q | {`THREADS{byp_dec_ex2_abort}}; + assign ex3_flush = cp_flush_q | ex3_spec_flush_q; + + assign rv2_val = rv_xu0_vld & ~cp_flush_q; + assign ex0_val = ex0_val_q & ~ex0_flush & ~{`THREADS{rv_xu0_ex0_ord}}; + assign ex1_val = ex1_val_q & ~ex1_flush; + assign ex2_val = ex2_val_q & ~ex2_flush; + assign ex3_val =(ex3_val_q & ~ex3_flush & ~{`THREADS{ex3_mul_multicyc_q}}) | (exx_mul_tid_q & {`THREADS{ex3_mul_insert}}); + assign ex4_val = ex4_val_q & ~cp_flush_q; + assign ex5_val = ex5_val_q & ~cp_flush_q; + assign ex6_val = ex6_val_q & ~cp_flush_q; + + assign exx_mul_tid_d = ex3_mul_multicyc_q ? ex3_val_q : exx_mul_tid_q; + + assign ex0_ord_val = ex0_val_q & ~ex0_flush & {`THREADS{rv_xu0_ex0_ord}}; + assign ex1_ord_val = ex1_ord_val_q & ~ex1_flush; + assign ex2_ord_val = ex2_ord_val_q & ~ex2_flush; + assign ex3_ord_val = ex3_ord_val_q & ~ex3_flush; + + // This is used for clock gating later... rs/ra_capt + assign ex0_ord = |ex0_val_q & rv_xu0_ex0_ord; + + assign ex1_valid = |(ex1_val); + assign ex3_valid = |(ex3_val); + assign ex5_valid = |(ex5_val); + assign ex6_valid = |(ex6_val); + + assign ex1_ord_act = ex1_ord_q; + + assign ex4_ord_act = |(ex4_ord_val_q); + + assign ex1_ord_valid = |(ex1_ord_val); + assign ex2_ord_valid = |(ex2_ord_val); + + assign cp_flush_ord_tid = |(cp_flush_q & ex2_ord_tid_q); + + assign cp_flush_ord = ord_outstanding_q & cp_flush_ord_tid; + + assign ord_spec_flush = |(ex1_spec_flush_q & ex1_ord_val_q) | + |(ex2_spec_flush_q & ex2_ord_val_q) | + |(ex3_spec_flush_q & ex3_ord_val_q) | + (byp_dec_ex2_abort & |ex2_ord_val_q); + + assign ord_flush = ord_spec_flush | cp_flush_ord; + + assign dec_ord_flush = {`THREADS{ord_flush}}; + + assign xu_spr_ord_flush = ord_spec_flush; + + assign exx_act[0] = |(ex0_val_q); + assign exx_act[1] = exx_act_q[1]; + assign exx_act[2] = exx_act_q[2] | ex2_ord_complete_q; + assign exx_act[3] = exx_act_q[3] | ex3_mul_insert; + assign exx_act[4] = exx_act_q[4]; + assign exx_act[5] = exx_act_q[5]; + + assign exx_act_d[1:5] = exx_act[0:4]; + + assign xu0_xu1_ex3_act = exx_act_q[3]; + + assign dec_br_ex0_act = ex0_opcode_is_19 | ex0_is_b | ex0_is_bc | rv_xu0_ex0_fusion[0]; + + assign ex1_spr_msr_cm_int = |((ex1_val_q | ex1_ord_val_q) & spr_msr_cm_q); + assign ex1_spr_msr_cm = ex1_spr_msr_cm_int; + assign ex4_spr_msr_cm = |((ex4_val_q | ex4_ord_val_q) & spr_msr_cm_q); + + //------------------------------------------------------------------------- + // ALU control logic + //------------------------------------------------------------------------- + assign dec_pop_ex1_act = exx_act[1]; + assign dec_alu_ex1_act = exx_act[1]; + assign dec_alu_ex1_instr = ex1_instr_q; + assign dec_alu_ex1_sel_isel = ex1_is_isel; + assign dec_alu_ex2_add_ci_sel = ex2_add_ci_sel_q; + assign dec_alu_ex1_add_rs1_inv = {`GPR_WIDTH/8{ex1_add_rs1_inv}}; + assign dec_alu_ex1_sel_trap = ex1_any_trap; + assign dec_alu_ex1_sel_cmpl = ex1_any_cmpl; + assign dec_alu_ex1_sel_cmp = ex1_any_cmp; + assign dec_byp_ex0_act = exx_act[0]; + assign dec_byp_ex1_instr = ex1_instr_q[24:25]; + assign dec_byp_ex3_is_mtspr = ex3_is_mtspr_q; + assign dec_byp_ex0_rs1_sel_zero = ex0_rs1_sel_zero_trm1 | (ex0_is_eratsx & ~ex0_tlbsel[1]); + + // CI uses XER[CA] + assign ex0_rs1_sel_zero_trm1 = (|ex1_ord_val_q & ex1_is_erativax) ? ~ex1_s3_v_q : ~rv_xu0_ex0_s1_v; + + assign ex1_add_ci_sel[0] = ex1_is_adde | ex1_is_addme | ex1_is_addze | + ex1_is_subfme | ex1_is_subfze | ex1_is_subfe; + // CI uses 1 + assign ex1_add_ci_sel[1] = ex1_is_subf | ex1_is_subfc | ex1_is_subfic | + ex1_is_neg | ex1_alu_cmp | ex1_any_trap; + + assign ex1_add_rs1_inv = ex1_add_ci_sel[1] | + ex1_is_subfme | ex1_is_subfze | ex1_is_subfe; + + assign ex1_any_tw = ex1_is_tw | ex1_is_twi; + assign ex1_any_td = ex1_is_td | ex1_is_tdi; + + assign ex1_any_trap = ex1_any_tw | ex1_any_td; + + assign ex1_any_cmp = ex1_is_cmp | ex1_is_cmpi; + + assign ex1_any_cmpl = ex1_is_cmpl | ex1_is_cmpli; + + assign ex1_alu_cmp = ex1_any_cmp | ex1_any_cmpl; + + // Traps, Compares and back invalidates operate regardless of msr[cm] + assign ex1_force_64b_cmp = ex1_any_td | (ex1_alu_cmp & ex1_instr_q[10]); + assign ex1_force_32b_cmp = ex1_any_tw | (ex1_alu_cmp & ~ex1_instr_q[10]); + + assign dec_alu_ex1_msb_64b_sel = (ex1_spr_msr_cm_int & ~ex1_force_32b_cmp) | ex1_force_64b_cmp; + + assign dec_alu_ex1_xer_ca_en = ex1_is_addc | ex1_is_addic | ex1_is_addicr | + ex1_is_adde | ex1_is_addme | ex1_is_addze | + ex1_is_subfc | ex1_is_subfic | ex1_is_subfme | + ex1_is_subfe | ex1_is_subfze | ex1_is_srad | + ex1_is_sradi | ex1_is_sraw | ex1_is_srawi ; + + assign dec_alu_ex1_xer_ov_en = ex1_instr_q[21] & ( + ex1_is_add | ex1_is_addc | ex1_is_adde | + ex1_is_addme | ex1_is_addze | ex1_is_subf | + ex1_is_subfc | ex1_is_subfe | ex1_is_subfme | + ex1_is_subfze | ex1_is_neg); + + assign ex1_any_popcnt = ex1_is_popcntb | ex1_is_popcntw | ex1_is_popcntd; + + assign ex1_any_cntlz = ex1_is_cntlzw | ex1_is_cntlzd; + + assign dec_byp_ex4_pop_done = ex4_any_popcnt_q; + assign dec_byp_ex3_cnt_done = ex3_any_cntlz_q; + assign dec_byp_ex3_prm_done = ex3_is_bpermd_q; + assign dec_byp_ex3_dlm_done = ex3_is_dlmzb_q; + assign dec_cnt_ex2_instr = ex2_instr_q[25:25]; + + //---------------------------------------------------------------------------------------------------------------------------------------- + // Immediate Logic + //---------------------------------------------------------------------------------------------------------------------------------------- + // Determine what ops use immediate: + assign ex0_use_imm = ex0_is_b | ex0_is_bc | ex0_is_addi | ex0_is_addic | ex0_is_addicr | ex0_is_addme | + ex0_is_addis | ex0_is_addze | ex0_is_andir | ex0_is_andisr | ex0_is_cmpi | ex0_is_cmpli | + ex0_is_mulli | ex0_is_neg | ex0_is_ori | ex0_is_oris | ex0_is_subfic | ex0_is_subfze | + ex0_is_twi | ex0_is_tdi | ex0_is_xori | ex0_is_xoris | ex0_is_subfme | ex0_is_mtcrf | + ex0_is_mtmsr | ex0_is_mtspr | ex0_is_wrteei | ex0_is_wrtee | ex0_is_eratwe; + + // Determine ops that use 15 bit immediate + assign ex1_imm_size = ex1_is_addi | ex1_is_addis | ex1_is_subfic | ex1_is_addic | ex1_is_addicr | ex1_is_mulli | + ex1_is_ori | ex1_is_oris | ex1_is_andir | ex1_is_andisr | ex1_is_xori | ex1_is_xoris | + ex1_is_bc | ex1_is_cmpli | ex1_is_cmpi | ex1_is_twi | ex1_is_tdi | ex1_is_wrteei; + + // Determine ops that use sign-extended immediate + assign ex1_imm_signext = ex1_is_addi | ex1_is_addis | ex1_is_subfic | ex1_is_addic | ex1_is_addicr | ex1_is_mulli | + ex1_is_bc | ex1_is_cmpi | ex1_is_twi | ex1_is_tdi; + + assign ex1_shift_imm = ex1_is_addis | ex1_is_oris | ex1_is_andisr | ex1_is_xoris; // Immediate needs to be shifted + + assign ex1_zero_imm = ex1_is_mtcrf | ex1_is_mtmsr | ex1_is_mtspr | ex1_is_wrtee | ex1_is_neg | ex1_is_addze | + ex1_is_subfze | ex1_is_eratwe | ex1_is_mtiar; // Immediate should be zeroed + + assign ex1_ones_imm = ex1_is_addme | ex1_is_subfme; // Immediate should be all ones + + assign ex1_extd_imm = ({ex1_imm_size, ex1_imm_signext} == 2'b11) ? {{10{ex1_instr_q[16]}}, ex1_instr_q[16:31]} : + ({ex1_imm_size, ex1_imm_signext} == 2'b10) ? {10'b0, ex1_instr_q[16:31]} : + ex1_instr_q[6:31]; + + assign ex1_shifted_imm = (ex1_shift_imm == 1'b0) ? {{`GPR_WIDTH-26{ex1_extd_imm[6]}} , ex1_extd_imm} : + {{`GPR_WIDTH-32{ex1_extd_imm[15]}}, ex1_extd_imm[16:31], 16'b0}; + + // Immediate tied down or tied up as needed + assign dec_byp_ex1_imm = (ex1_shifted_imm & {`GPR_WIDTH{~ex1_zero_imm}}) | {`GPR_WIDTH{ex1_ones_imm}}; + + assign dec_byp_ex0_rs2_sel_imm = ex0_use_imm; + + //------------------------------------------------------------------------- + // TLB Illegal Ops + //------------------------------------------------------------------------- + // WS>3 is reserved + assign ex1_tlb_illeg_ws = (ex1_is_eratwe | ex1_is_eratre) & ex1_instr_q[16:18] != 3'b000; + // WS=2 is reserved in 64b mode + assign ex1_tlb_illeg_ws2 = (ex1_is_eratwe | ex1_is_eratre) & ex1_instr_q[19:20] == 2'b10 & ex1_spr_msr_cm_int; + // WS=3 is reserved for eratwe when targeting anything other than erats + assign ex1_tlb_illeg_ws3 = ex1_is_eratwe & ex1_instr_q[19:20] == 2'b11 & ex1_tlbsel[0] == 1'b0; + // T=2 is reserved + assign ex1_tlb_illeg_t = ex1_is_tlbilx & ex1_instr_q[8:10] == 3'b010; + // Target other than erats is illegid for some erat ops, and all tlb ops illegid when no TLB is present + assign ex1_tlb_illeg_sel = ((ex1_is_tlbwe | ex1_is_tlbre | ex1_is_tlbsx | ex1_is_tlbsxr | ex1_is_tlbsrx | ex1_is_tlbilx | ex1_is_tlbivax) & spr_ccr2_notlb_q) | + ((ex1_is_eratwe | ex1_is_eratre | ex1_is_eratsx) & (~ex1_tlbsel[0])) | + ((ex1_is_erativax) & (~spr_ccr2_notlb_q)); // erativax illegid in TLB mode, use tlbivax + + assign ex1_tlb_illeg = ex1_tlb_illeg_ws | ex1_tlb_illeg_ws2 | ex1_tlb_illeg_ws3 | ex1_tlb_illeg_sel | ex1_tlb_illeg_t; + + //------------------------------------------------------------------------- + // Multiply Decode + //------------------------------------------------------------------------- + assign dec_mul_ex1_mul_val = (ex1_ord_val | ex1_val) & {`THREADS{ex1_mul_val}}; + + assign ex1_mul_val = ex1_is_mulhw | ex1_is_mulhwu | ex1_is_mullw | ex1_is_mulhd | + ex1_is_mulhdu | ex1_is_mulld | ex1_is_mulldo | ex1_is_mulli ; + + assign dec_mul_ex1_mul_ord = ex1_ord_q; + assign dec_mul_ex1_mul_recform = ex1_instr_q[31] & ( + ex1_is_mulhd | ex1_is_mulhdu | ex1_is_mulhw | ex1_is_mulhwu | + ex1_is_mulld | ex1_is_mulldo | ex1_is_mullw); + + assign dec_mul_ex1_mul_ret = ex1_is_mulhw | ex1_is_mulhwu | ex1_is_mulhd | ex1_is_mulhdu; + assign dec_mul_ex1_mul_size = ex1_is_mulld | ex1_is_mulldo | ex1_is_mulhd | ex1_is_mulhdu | ex1_is_mulli; + assign dec_mul_ex1_mul_sign = ~(ex1_is_mulhdu | ex1_is_mulhwu); + assign dec_mul_ex1_mul_imm = ex1_is_mulli; + + assign dec_mul_ex1_xer_ov_update = (ex1_is_mulld | ex1_is_mulldo | ex1_is_mullw) & ex1_instr_q[21]; + + assign ex1_mul_2c = ex1_valid & ex1_is_mulli; + assign ex1_mul_3c = ex1_valid & ex1_is_mulld; + assign ex1_mul_4c = ex1_valid & (ex1_is_mulldo | ex1_is_mulhd | ex1_is_mulhdu); + assign ex1_mul_multicyc = ex1_mul_2c | ex1_mul_3c | ex1_mul_4c; + + assign ex4_mul_2c_d = ex3_mul_2c_q & |(ex3_val_q & ~ex3_flush); + assign ex4_mul_3c_d = ex3_mul_3c_q & |(ex3_val_q & ~ex3_flush); + assign ex4_mul_4c_d = ex3_mul_4c_q & |(ex3_val_q & ~ex3_flush); + + assign ex5_mul_3c_d = ex4_mul_3c_q & |(exx_mul_tid_q & ~cp_flush_q); + assign ex5_mul_4c_d = ex4_mul_4c_q & |(exx_mul_tid_q & ~cp_flush_q); + + assign ex6_mul_4c_d = ex5_mul_4c_q & |(exx_mul_tid_q & ~cp_flush_q); + + assign ex0_mul_insert = ex1_mul_2c | ex2_mul_3c_q | ex3_mul_4c_q; + assign ex3_mul_insert = (ex4_mul_2c_q | ex5_mul_3c_q | ex6_mul_4c_q) & |(exx_mul_tid_q & ~cp_flush_q); + + //-------------------------------------------------------------------------- + // DIV control logic + //-------------------------------------------------------------------------- + assign dec_div_ex1_div_act = |(ex1_ord_val_q) & ex1_div_val; + + assign dec_div_ex1_div_val = ex1_ord_val & {`THREADS{ex1_div_val}}; + + assign ex1_div_val =(ex1_is_divd | ex1_is_divdu | ex1_is_divw | ex1_is_divwu | + ex1_is_divde | ex1_is_divdeu | ex1_is_divwe | ex1_is_divweu); + + assign dec_div_ex1_div_sign = ex1_is_divw | ex1_is_divd | ex1_is_divwe | ex1_is_divde; + + assign dec_div_ex1_div_size = ex1_is_divd | ex1_is_divdu | ex1_is_divde | ex1_is_divdeu; + + assign dec_div_ex1_div_extd = ex1_is_divde | ex1_is_divdeu | ex1_is_divwe | ex1_is_divweu; + + assign dec_div_ex1_div_recform =(ex1_is_divd | ex1_is_divdu | ex1_is_divw | ex1_is_divwu | + ex1_is_divde | ex1_is_divdeu | ex1_is_divwe | ex1_is_divweu) & ex1_instr_q[31]; + + assign dec_div_ex1_div_ctr = (ex1_div_ctr_sel == 3'b100) ? 8'b01000010 : + (ex1_div_ctr_sel == 3'b010) ? 8'b00100010 : + (ex1_div_ctr_sel == 3'b001) ? 8'b00010010 : + 8'b00000000 ; + assign ex1_div_ctr_sel[0] = ex1_is_divde | ex1_is_divdeu; + assign ex1_div_ctr_sel[1] = ex1_is_divd | ex1_is_divdu | ex1_is_divwe | ex1_is_divweu; + assign ex1_div_ctr_sel[2] = ex1_is_divw | ex1_is_divwu; + + assign dec_div_ex1_xer_ov_update =(ex1_is_divd | ex1_is_divde | ex1_is_divdeu | ex1_is_divdu | + ex1_is_divw | ex1_is_divwe | ex1_is_divweu | ex1_is_divwu) & ex1_instr_q[21]; + + //-------------------------------------------------------------------------- + // BCD control logic + //-------------------------------------------------------------------------- + assign dec_bcd_ex1_val = ex1_valid & (ex1_is_cdtbcd | ex1_is_cbcdtd | ex1_is_addg6s); + assign dec_bcd_ex1_is_addg6s = ex1_is_addg6s; + assign dec_bcd_ex1_is_cdtbcd = ex1_is_cdtbcd; + + //-------------------------------------------------------------------------- + // mt/mf bypassed SPRs + //-------------------------------------------------------------------------- + assign dec_byp_ex1_is_mflr = ex1_is_mflr | ex1_is_mftar; + assign dec_byp_ex1_is_mfxer = ex1_is_mfxer; + assign dec_byp_ex1_is_mtxer = ex1_is_mtxer; + assign dec_byp_ex1_is_mfctr = ex1_is_mfctr; + assign dec_byp_ex1_is_mfcr = ex1_instr_q[12:19] & {8{ex1_is_mfcr}}; + assign dec_byp_ex1_is_mtcr = ex1_instr_q[12:19] & {8{ex1_is_mtcrf}}; + assign dec_byp_ex1_is_mfcr_sel = ex1_is_mfcr; // A2i compatability + + assign dec_byp_ex1_cr_sel[2] = ex1_s2_v_q & (ex1_s2_t_q == `cr_t); + assign dec_byp_ex1_cr_sel[3] = ex1_s3_v_q & (ex1_s3_t_q == `cr_t); + assign dec_byp_ex1_xer_sel[2] = ex1_s2_v_q & (ex1_s2_t_q == `xer_t); + assign dec_byp_ex1_xer_sel[3] = ex1_s3_v_q & (ex1_s3_t_q == `xer_t); + + //------------------------------------------------------------------------- + // Privilege Levels + //------------------------------------------------------------------------- + assign ex1_tid = ex1_val_q | ex1_ord_val_q; + + assign ex1_priv_excep = ( ex1_is_eratilx | ex1_is_erativax | ex1_is_eratre | ex1_is_eratsx | + ex1_is_eratwe | ex1_is_tlbilx | ex1_is_tlbivax | ex1_is_tlbre | + ex1_is_tlbwe | ex1_is_tlbsrx | ex1_is_tlbsx | ex1_is_tlbsxr ) & |(ex1_tid & spr_msr_pr_q); + + assign ex1_hyp_priv_excep=(ex1_is_eratilx | ex1_is_erativax | ex1_is_eratre | ex1_is_eratsx | + ex1_is_eratwe | ex1_is_tlbsx | ex1_is_tlbsxr | ex1_is_tlbivax | ex1_is_tlbre | + ((ex1_is_tlbwe | ex1_is_tlbsrx | ex1_is_tlbilx) & |(ex1_tid & spr_epcr_dgtmi_q))) + & |(ex1_tid & (spr_msr_pr_q | spr_msr_gs_q)); + + assign ex1_illegal_op = (ex1_is_attn & ~spr_ccr2_en_attn_q) | + (ex1_is_dnh & ~spr_ccr4_en_dnh_q) ; + + assign ex1_flush2ucode = ex1_is_mtcrf & + ~((ex1_instr_q[12:19] == 8'b10000000) | (ex1_instr_q[12:19] == 8'b01000000) | + (ex1_instr_q[12:19] == 8'b00100000) | (ex1_instr_q[12:19] == 8'b00010000) | + (ex1_instr_q[12:19] == 8'b00001000) | (ex1_instr_q[12:19] == 8'b00000100) | + (ex1_instr_q[12:19] == 8'b00000010) | (ex1_instr_q[12:19] == 8'b00000001) | + (ex1_instr_q[12:19] == 8'b00000000)); + + //-------------------------------------------------------------------------- + // Ordered + //-------------------------------------------------------------------------- + // 1008 CCR0 + assign ex1_async_flush_after = ex1_is_mtspr & ((ex1_instr_q[11:20] == 10'b1000011111) | // 1008 CCR0 + (ex1_instr_q[11:20] == 10'b1011101101)); // 439 TENC + + assign ex1_async_flush_before = ex1_is_eratilx | ex1_is_tlbilx | ex1_is_tlbivax | (ex1_is_tlbwe & mm_xu_tlbwe_binv_q) | (ex1_is_mtspr & (ex1_instr_q[11:20] == 10'b1011011111 | // XUCR0 + ex1_instr_q[11:20] == 10'b1000011001 | // cpcr0 816 + ex1_instr_q[11:20] == 10'b1000111001 | // cpcr1 817 + ex1_instr_q[11:20] == 10'b1001011001 | // cpcr2 818 + ex1_instr_q[11:20] == 10'b1010011001 | // cpcr3 820 + ex1_instr_q[11:20] == 10'b1010111001 | // cpcr4 821 + ex1_instr_q[11:20] == 10'b1011011001 )); // cpcr5 822 + + assign ex1_is_credit_wait = (ex1_is_mtspr & (ex1_instr_q[11:20] == 10'b1011011111 | // XUCR0 + ex1_instr_q[11:20] == 10'b1000011001 | // cpcr0 816 + ex1_instr_q[11:20] == 10'b1000111001 | // cpcr1 817 + ex1_instr_q[11:20] == 10'b1001011001 | // cpcr2 818 + ex1_instr_q[11:20] == 10'b1010011001 | // cpcr3 820 + ex1_instr_q[11:20] == 10'b1010111001 | // cpcr4 821 + ex1_instr_q[11:20] == 10'b1011011001 )); // cpcr5 822 + + assign ex2_mtiar_sel = ex2_ord_valid & ex2_is_mtiar_q; + + assign dec_byp_ex3_mtiar = ex3_mtiar_sel_q; + + assign ex1_any_pri = ex1_is_pri1 | ex1_is_pri2 | ex1_is_pri3 | ex1_is_pri4 | ex1_is_pri5 | ex1_is_pri6 | ex1_is_pri7; + + assign xu_iu_pri_val = xu_iu_pri_val_int; + assign xu_iu_pri_val_int = xu_iu_pri_val_q & {`THREADS{ord_is_cp_next_q}}; + + assign xu_iu_pri_val_d = ((ex1_ord_val & {`THREADS{ex1_any_pri}}) | xu_iu_pri_val_q) & ~xu_iu_pri_val_int & ~cp_flush_q; + + assign xu_iu_pri = xu_iu_pri_q; + assign xu_iu_pri_d = (3'b001 & {3{(ex1_ord_capt & ex1_is_pri1)}}) | + (3'b010 & {3{(ex1_ord_capt & ex1_is_pri2)}}) | + (3'b011 & {3{(ex1_ord_capt & ex1_is_pri3)}}) | + (3'b100 & {3{(ex1_ord_capt & ex1_is_pri4)}}) | + (3'b101 & {3{(ex1_ord_capt & ex1_is_pri5)}}) | + (3'b110 & {3{(ex1_ord_capt & ex1_is_pri6)}}) | + (3'b111 & {3{(ex1_ord_capt & ex1_is_pri7)}}); + + assign ex2_ord_erat_val = (ex2_ord_is_eratre_q | ex2_ord_is_eratwe_q | ex2_ord_is_eratsx_q) & ~(ex2_priv_excep_q | ex2_hyp_priv_excep_q | ex2_tlb_illeg_q); + + assign ex2_ord_mmu_val = (ex2_ord_is_tlbre_q | ex2_ord_is_tlbwe_q | ex2_ord_is_tlbsx_q | + ex2_ord_is_tlbsxr_q | ex2_ord_is_tlbsrx_q | ex2_ord_is_tlbilx_q | + ex2_ord_is_tlbivax_q | ex2_ord_is_eratilx_q | ex2_ord_is_erativax_q) & (~(ex2_priv_excep_q | ex2_hyp_priv_excep_q | ex2_tlb_illeg_q)); + + assign xu_iu_hold_val_d = (ex2_ord_valid == 1'b1) ? (ex2_tlbsel == 2'b10 & ex2_ord_erat_val) : xu_iu_hold_val_q & ~ord_mmu_req_sent_q; + assign xu_lq_hold_val_d = (ex2_ord_valid == 1'b1) ? (ex2_tlbsel == 2'b11 & ex2_ord_erat_val) : xu_lq_hold_val_q & ~ord_mmu_req_sent_q; + assign xu_mm_hold_val_d = (ex2_ord_valid == 1'b1) ? (ex2_ord_mmu_val) : xu_mm_hold_val_q & ~ord_mmu_req_sent_q; + + // Data is ready by EX5. + assign ord_mmu_req_sent_d = (xu_iu_val_d | xu_lq_val_d | xu_mm_val_d) & ord_outstanding_q & ord_is_cp_next_q; + + // mmu_ord_n_flush_req_q is mmu busy, so just retry tlb op again. + // iu_ord_n_flush_req_q is eratsx collision with I$ back_inv or tlb reload, so just retry erat op again. + // lq_ord_n_flush_req_q is spare/future use for now because derat has arbiter for collisions. + assign xu_iu_val_d = (xu_iu_hold_val_q & ord_outstanding_q & ord_is_cp_next_q & ~ord_mmu_req_sent_q & ~cp_flush_ord_tid) | iu_ord_n_flush_req_q[1]; + assign xu_lq_val_d = (xu_lq_hold_val_q & ord_outstanding_q & ord_is_cp_next_q & ~ord_mmu_req_sent_q & ~cp_flush_ord_tid) | lq_ord_n_flush_req_q[1]; + assign xu_mm_val_d = (xu_mm_hold_val_q & ord_outstanding_q & ord_is_cp_next_q & ~ord_mmu_req_sent_q & ~cp_flush_ord_tid) | mmu_ord_n_flush_req_q[1]; + + assign xu_iu_act = xu_iu_val_q; + assign xu_lq_act = xu_lq_val_q; + assign xu_mm_act = xu_mm_val_q; + + assign xu_iu_val_2_d = ex2_ord_tid_q & {`THREADS{xu_iu_val_q}} & ~cp_flush_q; + assign xu_lq_val_2_d = ex2_ord_tid_q & {`THREADS{xu_lq_val_q}} & ~cp_flush_q; + assign xu_mm_val_2_d = ex2_ord_tid_q & {`THREADS{xu_mm_val_q}} & ~cp_flush_q; + + assign xu_iu_val = xu_iu_val_2_q; + assign xu_lq_val = xu_lq_val_2_q; + assign xu_mm_val = xu_mm_val_2_q; + + assign xu_mm_itag = ex2_ord_itag_q; + assign xu_lq_hold_req = ord_hold_lq_q; + + assign xu_iu_ord_ready = ord_is_cp_next_q; + assign xu_lq_ord_ready = ord_is_cp_next_q; + assign xu_mm_ord_ready = ord_is_cp_next_q; + assign xu_spr_ord_ready = ord_is_cp_next_q; + + assign ex2_ord_cp_next_cmp[0] = (cp_next_itag_t0 == ex2_ord_itag_q) & ex2_ord_tid_q[0]; + `ifndef THREADS1 + assign ex2_ord_cp_next_cmp[1] = (cp_next_itag_t1 == ex2_ord_itag_q) & ex2_ord_tid_q[1]; + `endif + + + assign ord_async_flush_before_set = ~ex1_ord_val_q & {`THREADS{(ex1_ord_valid & ex1_async_flush_before)}}; + assign ord_async_flush_before_d = (ord_async_flush_before_set | ord_async_flush_before_q) & ~(iu_async_complete_q | {`THREADS{ord_flush}}); + + assign ord_async_flush_after_set = ~ex1_ord_val_q & {`THREADS{(ex1_ord_valid & ex1_async_flush_after)}}; + assign ord_async_flush_after_d = (ord_async_flush_after_set | ord_async_flush_after_q) & ~(iu_async_complete_q | {`THREADS{ord_flush}}); + + assign ord_async_credit_wait_set = ex1_ord_valid & ex1_is_credit_wait; + assign ord_async_credit_wait_d = (ord_async_credit_wait_set | ord_async_credit_wait_q) & ~(iu_xu_credits_returned_q | ord_flush); + + assign xu_iu_np1_async_flush = async_flush_req_q & ~async_flush_req_2_q; + + assign async_flush_req_d = (ord_async_flush_after_q & {`THREADS{|ex2_ord_cp_next_cmp & ord_done_q}}) | + (ord_async_flush_before_q & {`THREADS{|ex2_ord_cp_next_cmp}}); + + assign ord_is_cp_next = |ex2_ord_cp_next_cmp & ord_outstanding_q & ~((|ord_async_flush_before_q) | ord_async_credit_wait_q); + + assign mmu_ord_itag_match = (mm_xu_itag == ex2_ord_itag_q) & ord_outstanding_q; + + assign spr_ord_done = spr_xu_ord_write_done | spr_xu_ord_read_done | xu_slowspr_val_in; + + assign ex1_ord_capt = |(ex1_ord_val_q); + + assign ord_instr_d = ex1_instr_q; + assign ord_mtiar_d = ((ex2_ord_valid & ex2_is_mtiar_q) | ord_mtiar_q ) & ~ex1_ord_capt; + assign ord_tlb_miss_d = ((mm_xu_tlb_miss & mmu_ord_itag_match) | ord_tlb_miss_q ) & ~ex1_ord_capt; + assign ord_lrat_miss_d = ((mm_xu_lrat_miss & mmu_ord_itag_match) | ord_lrat_miss_q ) & ~ex1_ord_capt; + assign ord_tlb_inelig_d = ((mm_xu_tlb_inelig & mmu_ord_itag_match) | ord_tlb_inelig_q ) & ~ex1_ord_capt; + assign ord_pt_fault_d = ((mm_xu_pt_fault & mmu_ord_itag_match) | ord_pt_fault_q ) & ~ex1_ord_capt; + assign ord_hv_priv_d = ((mm_xu_hv_priv & mmu_ord_itag_match) | ord_hv_priv_q ) & ~ex1_ord_capt; + assign ord_illeg_mmu_d = (mm_xu_illeg_instr | ord_illeg_mmu_q ) & ~ex1_ord_capt; + assign ord_lq_flush_d = (lq_xu_ord_n_flush_req | ord_lq_flush_q ) & ~ex1_ord_capt; + assign ord_spr_priv_d = ((spr_dec_ex4_spr_priv & spr_ord_done) | ord_spr_priv_q ) & ~ex1_ord_capt; + assign ord_spr_illegal_spr_d = ((spr_dec_ex4_spr_illeg & spr_ord_done) | + (ex2_ord_valid & ex2_illegal_op_q) | ord_spr_illegal_spr_q) & ~ex1_ord_capt; + assign ord_hyp_priv_spr_d = ((spr_dec_ex4_spr_hypv & spr_ord_done) | ord_hyp_priv_spr_q ) & ~ex1_ord_capt; + assign ord_ex3_np1_flush_d = ((spr_dec_ex4_np1_flush & spr_ord_done) | ord_ex3_np1_flush_q) & ~ex1_ord_capt; + assign ord_ill_tlb_d = ((ex2_ord_valid & ex2_tlb_illeg_q) | ord_ill_tlb_q ) & ~ex1_ord_capt; + assign ord_priv_d = ((ex2_ord_valid & ex2_priv_excep_q) | ord_priv_q ) & ~ex1_ord_capt; + assign ord_hyp_priv_d = ((ex2_ord_valid & ex2_hyp_priv_excep_q) | ord_hyp_priv_q ) & ~ex1_ord_capt; + + assign ord_ierat_par_err_d = (((iu_xu_ord_read_done | iu_xu_ord_write_done) & iu_xu_ord_par_err) | ord_ierat_par_err_q) & ~ex1_ord_capt; + assign ord_derat_par_err_d = (((lq_xu_ord_read_done | lq_xu_ord_write_done) & lq_xu_ord_par_err) | ord_derat_par_err_q) & ~ex1_ord_capt; + assign ord_tlb_multihit_d = ((mmu_ord_itag_match & mm_xu_tlb_multihit) | ord_tlb_multihit_q) & ~ex1_ord_capt; + assign ord_tlb_par_err_d = ((mmu_ord_itag_match & mm_xu_tlb_par_err) | ord_tlb_par_err_q) & ~ex1_ord_capt; + assign ord_tlb_lru_par_err_d = ((mmu_ord_itag_match & mm_xu_lru_par_err) | ord_tlb_lru_par_err_q) & ~ex1_ord_capt; + assign ord_local_snoop_reject_d=((mmu_ord_itag_match & mm_xu_local_snoop_reject) | ord_local_snoop_reject_q)& ~ex1_ord_capt; + + + // Don't hold the lq off for core-blocker instructions + assign ord_hold_lq_d = ((mmu_ord_n_flush_req_q[0] & ~ord_core_block_q) | ord_hold_lq_q ) & ~ex1_ord_capt & ord_outstanding_q; + + assign mmu_error = (mm_xu_tlb_miss | mm_xu_lrat_miss | mm_xu_tlb_inelig | mm_xu_pt_fault | mm_xu_hv_priv | mm_xu_illeg_instr) & mmu_ord_itag_match; + + assign mmu_ord_n_flush_req_d = {(mm_xu_ord_n_flush_req & mmu_ord_itag_match & ord_outstanding_q), mmu_ord_n_flush_req_q[0]}; + assign iu_ord_n_flush_req_d = {(iu_xu_ord_n_flush_req & ord_outstanding_q), iu_ord_n_flush_req_q[0]}; + assign lq_ord_n_flush_req_d = {(lq_xu_ord_n_flush_req & ord_outstanding_q), lq_ord_n_flush_req_q[0]}; + + assign ord_outstanding_act = (|ex1_ord_val_q) | ord_outstanding_q | ex1_ord_complete_q | + ex2_ord_complete_q | + ex3_ord_complete_q | + ex4_ord_complete_q | + ex5_ord_complete_q | + ex6_ord_complete_q ; + + assign ord_outstanding_d = (ex1_ord_valid | ord_outstanding_q) & ~(ex0_ord_complete | ord_flush); + + assign ord_done_d = ((ord_outstanding_q & (ord_write_gpr | ord_read_gpr | ord_other)) | ord_done_q) & ~ex0_ord_complete & ~cp_flush_ord; + + assign ord_flushed_d = (~ex1_ord_valid & ord_flushed_q) | (ord_flush & ord_outstanding_q); + + assign ord_async_done = ~(|(ord_async_flush_before_q | ord_async_flush_after_q) | ord_async_credit_wait_q); + + assign ord_waiting = ord_outstanding_q & ord_done_q & ord_async_done; + + assign ord_timer_d = ord_waiting ? (ord_timer_q + 6'd1) : 6'd0; + + assign ord_timeout_d[0] = ord_timer_q == 6'b111111; + assign ord_timeout_d[1] = ord_timeout_q[0]; + + assign xu0_rv_hold_all = |ord_timeout_q; + + assign ex0_ord_complete = ord_waiting & ~|ex0_val_q & ~ex0_mul_insert & ~cp_flush_ord; + assign ex1_ord_complete = ex1_ord_complete_q & ~cp_flush_ord_tid; + assign ex2_ord_complete = ex2_ord_complete_q & ~cp_flush_ord_tid; + assign ex3_ord_complete = ex3_ord_complete_q & ~cp_flush_ord_tid; + assign ex4_ord_complete = ex4_ord_complete_q & ~cp_flush_ord_tid; + assign ex5_ord_complete = ex5_ord_complete_q & ~cp_flush_ord_tid; + assign ex6_ord_complete = ex6_ord_complete_q & ~cp_flush_ord_tid; + + assign ord_other = ord_ill_tlb_q | ord_priv_q | ord_hyp_priv_q | ord_illeg_mmu_q | ord_ierat_par_err_q | + ord_derat_par_err_q | ord_tlb_multihit_q | ord_tlb_par_err_q | ord_tlb_lru_par_err_q | ord_local_snoop_reject_q; + + assign ord_write_gpr = ((xu_slowspr_val_in & xu_slowspr_rw_in) | // SlowSPR Read + spr_xu_ord_write_done | // FastSPR Read + iu_xu_ord_read_done | // IU IERAT read + lq_xu_ord_read_done | // LQ DERAT read + (mm_xu_ord_read_done & (~mm_xu_ord_n_flush_req | mmu_error)) | // MMU read + div_dec_ex4_done | // Divide + mul_dec_ex6_ord_done // Mult + ) & ~cp_flush_ord_tid; + + assign ord_read_gpr = ((xu_slowspr_val_in & ~xu_slowspr_rw_in) | // SlowSPR Write + spr_xu_ord_read_done | // FastSPR Write + iu_xu_ord_write_done | // IU IERAT Write + (mm_xu_ord_write_done & (~mm_xu_ord_n_flush_req | mmu_error)) | // MMU read + lq_xu_ord_write_done | // LQ DERAT Write + lq_xu_ord_n_flush_req | // + |xu_iu_pri_val_int // + ) & ~cp_flush_ord_tid; + + + assign dec_byp_ex1_rs_capt = ex1_ord_q | (|ex2_ord_val_q & ex2_is_erativax_q); + assign dec_byp_ex1_ra_capt = ex1_ord_q; + assign dec_byp_ex5_ord_sel = ex5_ord_complete_q; + + assign xu0_rv_ord_complete = ex2_ord_complete; + assign xu0_rv_ord_itag = ex2_ord_itag_q; + + assign ex3_hpriv = |(ex3_excep_cond[9:11]); + assign dec_byp_ex4_hpriv = ex4_hpriv_q; + assign dec_byp_ex4_instr = (ex4_instr_q & {32{~ex4_ord_complete}}) | + (ord_instr_q & {32{ ex4_ord_complete}}); + + // TLB Parity Error 0 + // TLB LRU Parity 1 + // TLB Multihit 2 + // IERAT parity 3 + // DERAT parity 4 + // Program XU sourced illegal instruction type 5 + // Program SPR sourced illegal SPR 6 + // Program SPR sourced priviledged SPR 7 + // Program XU sourced priviledged instruction 8 + // Hypervisor Priviledge Priviledged SPR 9 + // Hypervisor Priviledge ehpriv instruction 10 + // Hypervisor Priviledge XU sourced priviledged 11 + // TLB Ineligile 12 + // MMU illegal Mas 13 + // Program Trap Instruction 14 + // LRAT Miss 15 + + assign ex3_excep_cond[0] = ex3_ord_complete & ord_tlb_par_err_q; + assign ex3_excep_cond[1] = ex3_ord_complete & ord_tlb_lru_par_err_q; + assign ex3_excep_cond[2] = ex3_ord_complete & ord_tlb_multihit_q; + assign ex3_excep_cond[3] = ex3_ord_complete & ord_ierat_par_err_q; + assign ex3_excep_cond[4] = ex3_ord_complete & ord_derat_par_err_q; + assign ex3_excep_cond[5] =(ex3_valid & ex3_illegal_op_q) | + (ex3_ord_complete & ord_ill_tlb_q); + assign ex3_excep_cond[6] = ex3_ord_complete & ord_spr_illegal_spr_q; + assign ex3_excep_cond[7] =(ex3_valid & ex3_priv_excep_q) | + (ex3_ord_complete & ord_priv_q); + assign ex3_excep_cond[8] = ex3_ord_complete & ord_spr_priv_q; + assign ex3_excep_cond[9] = ex3_ord_complete & ord_hyp_priv_spr_q; + assign ex3_excep_cond[10]= ex3_valid & ex3_is_ehpriv_q; + assign ex3_excep_cond[11]=(ex3_valid & ex3_hyp_priv_excep_q) | + (ex3_ord_complete & (ord_hyp_priv_q | ord_hv_priv_q)); + assign ex3_excep_cond[12]= ex3_ord_complete & ord_tlb_inelig_q; + assign ex3_excep_cond[13]= ex3_ord_complete & ord_illeg_mmu_q; + assign ex3_excep_cond[14]= ex3_valid & alu_dec_ex3_trap_val; + assign ex3_excep_cond[15]= ex3_ord_complete & ord_lrat_miss_q; + assign ex3_excep_cond[16]= ex3_ord_complete & ord_local_snoop_reject_q; + + + + assign ex3_ord_np1_flush = ex3_ord_complete & ord_ex3_np1_flush_q; + + tri_pri #(.SIZE(17)) excep_pri( + .cond(ex3_excep_cond), + .pri(ex3_excep_pri), + .or_cond(ex3_excep_val) + ); + + assign ex3_excep_vector = (5'd0 & {5{ex3_excep_pri[0]}}) | + (5'd1 & {5{ex3_excep_pri[1]}}) | + (5'd2 & {5{ex3_excep_pri[2]}}) | + (5'd3 & {5{ex3_excep_pri[3]}}) | + (5'd4 & {5{ex3_excep_pri[4]}}) | + (5'd5 & {5{ex3_excep_pri[5]}}) | + (5'd6 & {5{ex3_excep_pri[6]}}) | + (5'd7 & {5{ex3_excep_pri[7]}}) | + (5'd8 & {5{ex3_excep_pri[8]}}) | + (5'd9 & {5{ex3_excep_pri[9]}}) | + (5'd10 & {5{ex3_excep_pri[10]}})| + (5'd11 & {5{ex3_excep_pri[11]}})| + (5'd12 & {5{ex3_excep_pri[12]}})| + (5'd13 & {5{ex3_excep_pri[13]}})| + (5'd14 & {5{ex3_excep_pri[14]}})| + (5'd15 & {5{ex3_excep_pri[15]}})| + (5'd16 & {5{ex3_excep_pri[16]}}); + + assign ex3_n_flush = ex3_excep_val | ex3_flush2ucode; + assign ex3_np1_flush = ex3_ord_np1_flush; + + assign ex2_flush2ucode = ex2_flush2ucode_q & ex2_ucode_q != 3'b010; + assign ex3_flush2ucode = ex3_flush2ucode_q & ~ex3_ord_complete; + + assign xu0_iu_exception_val = ex4_excep_val_q; + assign xu0_iu_exception = ex4_excep_vector_q; + assign xu0_iu_n_flush = ex4_n_flush_q; + assign xu0_iu_np1_flush = ex4_np1_flush_q; + assign xu0_iu_flush2ucode = ex4_flush2ucode_q; + assign xu0_iu_perf_events = ex4_perf_event_q; + + assign xu_iu_is_eratre = ex2_ord_is_eratre_q; + assign xu_iu_is_eratwe = ex2_ord_is_eratwe_q; + assign xu_iu_is_eratsx = ex2_ord_is_eratsx_q; + assign xu_iu_is_eratilx = ex2_ord_is_eratilx_q; + assign xu_iu_is_erativax = ex2_ord_is_erativax_q; + assign xu_iu_ws = ex2_ord_tlb_ws_q; + assign xu_iu_t = ex2_ord_tlb_t_q; + + assign xu_lq_is_eratre = ex2_ord_is_eratre_q; + assign xu_lq_is_eratwe = ex2_ord_is_eratwe_q; + assign xu_lq_is_eratsx = ex2_ord_is_eratsx_q; + assign xu_lq_is_eratilx = ex2_ord_is_eratilx_q; + assign xu_lq_ws = ex2_ord_tlb_ws_q; + assign xu_lq_t = ex2_ord_tlb_t_q; + + assign xu_mm_is_tlbre = ex2_ord_is_tlbre_q; + assign xu_mm_is_tlbwe = ex2_ord_is_tlbwe_q; + assign xu_mm_is_tlbsx = ex2_ord_is_tlbsx_q; + assign xu_mm_is_tlbsxr = ex2_ord_is_tlbsxr_q; + assign xu_mm_is_tlbsrx = ex2_ord_is_tlbsrx_q; + assign xu_mm_is_tlbivax = ex2_ord_is_tlbivax_q; + assign xu_mm_is_tlbilx = ex2_ord_is_tlbilx_q; + + + `ifdef THREADS1 + assign spr_mmucr0_tlbsel_d[0] = mm_xu_mmucr0_tlbsel_t0; + + assign ex0_tlbsel = ex0_val_q[0]==1'b1 ? spr_mmucr0_tlbsel_q[0] : + 2'b00; + + assign ex1_tlbsel = ex1_ord_val[0]==1'b1 ? spr_mmucr0_tlbsel_q[0] : + 2'b00; + + assign ex2_tlbsel = ex2_ord_tid_q[0]==1'b1 ? spr_mmucr0_tlbsel_q[0] : + 2'b00; + + `else + assign spr_mmucr0_tlbsel_d[0] = mm_xu_mmucr0_tlbsel_t0; + assign spr_mmucr0_tlbsel_d[1] = mm_xu_mmucr0_tlbsel_t1; + + assign ex0_tlbsel = ex0_val_q[1]==1'b1 ? spr_mmucr0_tlbsel_q[1] : + ex0_val_q[0]==1'b1 ? spr_mmucr0_tlbsel_q[0] : + 2'b00; + + assign ex1_tlbsel = ex1_ord_val[1]==1'b1 ? spr_mmucr0_tlbsel_q[1] : + ex1_ord_val[0]==1'b1 ? spr_mmucr0_tlbsel_q[0] : + 2'b00; + + assign ex2_tlbsel = ex2_ord_tid_q[1]==1'b1 ? spr_mmucr0_tlbsel_q[1] : + ex2_ord_tid_q[0]==1'b1 ? spr_mmucr0_tlbsel_q[0] : + 2'b00; + `endif + + + //------------------------------------------------------------------------- + // Write Enables + //------------------------------------------------------------------------- + + assign ex5_t1_v = (ex5_ord_complete_q == 1'b1) ? ex5_ord_t1_v_q : ex5_t1_v_q; + assign ex5_t1_t = (ex5_ord_complete_q == 1'b1) ? ex5_ord_t1_t_q : ex5_t1_t_q; + assign ex5_t1_p = (ex5_ord_complete_q == 1'b1) ? ex5_ord_t1_p_q : ex5_t1_p_q; + assign ex5_t2_v = (ex5_ord_complete_q == 1'b1) ? ex5_ord_t2_v_q : ex5_t2_v_q; + assign ex5_t2_t = (ex5_ord_complete_q == 1'b1) ? ex5_ord_t2_t_q : ex5_t2_t_q; + assign ex5_t2_p = (ex5_ord_complete_q == 1'b1) ? ex5_ord_t2_p_q : ex5_t2_p_q; + assign ex5_t3_v = (ex5_ord_complete_q == 1'b1) ? ex5_ord_t3_v_q : ex5_t3_v_q; + assign ex5_t3_t = (ex5_ord_complete_q == 1'b1) ? ex5_ord_t3_t_q : ex5_t3_t_q; + assign ex5_t3_p = (ex5_ord_complete_q == 1'b1) ? ex5_ord_t3_p_q : ex5_t3_p_q; + assign ex3_itag = (ex3_ord_complete == 1'b1) ? ex2_ord_itag_q : ex3_itag_q; + assign ex6_tid_d = (ex5_ord_complete_q == 1'b1) ? ex2_ord_tid_q : ex5_val_q; + + assign ex5_cr1_we = ex5_t1_v & (ex5_t1_t == `cr_t); + assign ex5_cr3_we = ex5_t3_v & (ex5_t3_t == `cr_t); + + assign ex5_cr_we = (ex5_valid | ex5_ord_complete) & (ex5_cr1_we | ex5_cr3_we); + assign ex5_gpr_we = (ex5_valid | ex5_ord_complete) & ex5_t1_v & (ex5_t1_t == `gpr_t); + assign ex5_xer_we = (ex5_valid | ex5_ord_complete) & ex5_t2_v & (ex5_t2_t == `xer_t); + + assign ex3_ctr_we = ex3_valid & ex3_t2_v_q & (ex3_t2_t_q == `ctr_t); + assign ex3_lr_we = ex3_valid & ex3_t3_v_q & (ex3_t3_t_q == `lr_t); + + assign ex5_cr_wa = (ex5_t1_p[`GPR_POOL_ENC-`CR_POOL_ENC:`GPR_POOL_ENC-1] & {`CR_POOL_ENC{ex5_cr1_we}}) | + (ex5_t3_p[`GPR_POOL_ENC-`CR_POOL_ENC:`GPR_POOL_ENC-1] & {`CR_POOL_ENC{ex5_cr3_we}}); + + assign xu0_gpr_ex6_we = ex6_gpr_we_q; + assign xu0_xer_ex6_we = ex6_xer_we_q; + assign xu0_cr_ex6_we = ex6_cr_we_q; + assign xu0_ctr_ex4_we = ex4_ctr_we_q; + assign xu0_lr_ex4_we = ex4_lr_we_q; + + assign xu0_iu_mtiar_d[0] = ex2_ord_tid_q[0] & ex3_ord_complete & ord_mtiar_q; + `ifdef THREADS1 + assign xu0_gpr_ex6_wa = ex6_t1_p_q[0:`GPR_POOL_ENC-1]; + assign xu0_xer_ex6_wa = ex6_t2_p_q[`GPR_POOL_ENC-`XER_POOL_ENC:`GPR_POOL_ENC-1]; + assign xu0_cr_ex6_wa = ex6_cr_wa_q[`GPR_POOL_ENC-`CR_POOL_ENC:`GPR_POOL_ENC-1]; + assign xu0_ctr_ex4_wa = ex4_t2_p_q[`GPR_POOL_ENC-`CTR_POOL_ENC:`GPR_POOL_ENC-1]; + assign xu0_lr_ex4_wa = ex4_t3_p_q[`GPR_POOL_ENC-`BR_POOL_ENC:`GPR_POOL_ENC-1]; + `else + assign xu0_gpr_ex6_wa = {ex6_t1_p_q[0:`GPR_POOL_ENC-1] ,ex6_tid_q[1]}; + assign xu0_xer_ex6_wa = {ex6_t2_p_q[`GPR_POOL_ENC-`XER_POOL_ENC:`GPR_POOL_ENC-1] ,ex6_tid_q[1]}; + assign xu0_cr_ex6_wa = {ex6_cr_wa_q[`GPR_POOL_ENC-`CR_POOL_ENC:`GPR_POOL_ENC-1] ,ex6_tid_q[1]}; + assign xu0_ctr_ex4_wa = {ex4_t2_p_q[`GPR_POOL_ENC-`CTR_POOL_ENC:`GPR_POOL_ENC-1] ,ex4_val_q[1]}; + assign xu0_lr_ex4_wa = {ex4_t3_p_q[`GPR_POOL_ENC-`BR_POOL_ENC:`GPR_POOL_ENC-1] ,ex4_val_q[1]}; + assign xu0_iu_mtiar_d[1] = ex2_ord_tid_q[1] & ex3_ord_complete & ord_mtiar_q; + `endif + + + assign xu0_iu_execute_vld = (ex4_val | (ex2_ord_tid_q & {`THREADS{ex4_ord_complete}})) & ~ex4_br_val_q; + assign xu0_iu_itag = ex4_itag_q; + + assign xu0_iu_mtiar = xu0_iu_mtiar_q; + + assign ex6_ram_active_d = |(ex6_tid_d & pc_xu_ram_active); + + assign xu0_pc_ram_done = (ex6_valid | ex6_ord_complete) & ex6_ram_active_q; + + //------------------------------------------------------------------------- + // Perf Events + //------------------------------------------------------------------------- + assign ex1_any_mfspr = ex1_is_mfspr | ex1_is_mfmsr | ex1_is_mftb | ex1_is_mfcr; + assign ex1_any_mtspr = ex1_is_mtspr | ex1_is_mtmsr | ex1_is_mtcrf | ex1_is_wrtee | ex1_is_wrteei; + + assign ex2_any_mfspr = ex2_ord_complete_q ? ord_any_mfspr_q : ex2_any_mfspr_q; + assign ex2_any_mtspr = ex2_ord_complete_q ? ord_any_mtspr_q : ex2_any_mtspr_q; + + assign ex3_tid = (ex3_val_q | (ex2_ord_tid_q & {`THREADS{ex3_ord_complete_q}})); + + generate begin : perf_event + genvar t,e; + for (e=0;e<=3;e=e+1) begin : thread + for (t=0;t<=`THREADS-1;t=t+1) begin : thread + assign ex3_perf_event[e] = (spr_xesr1[4*e+16*t:4*e+16*t+3] == 4'd10 ? (ex3_tid[t] & perf_event_en[t] & ex3_any_mfspr_q) : 1'b0) | + (spr_xesr1[4*e+16*t:4*e+16*t+3] == 4'd11 ? (ex3_tid[t] & perf_event_en[t] & ex3_any_mtspr_q) : 1'b0) ; + end + end + end + endgenerate + + //------------------------------------------------------------------------- + // Decode + //------------------------------------------------------------------------- + + assign ex0_instr[0:5] = (rv_xu0_ex0_fusion[0:2] == 3'b100) ? 6'b011111 : + (rv_xu0_ex0_fusion[0:2] == 3'b101) ? 6'b001011 : + (rv_xu0_ex0_fusion[0:2] == 3'b110) ? 6'b011111 : + (rv_xu0_ex0_fusion[0:2] == 3'b111) ? 6'b001010 : + rv_xu0_ex0_instr[0:5]; + + assign ex0_instr[6:9] = (rv_xu0_ex0_fusion[0] == 1'b1) ? 4'b0000 : + rv_xu0_ex0_instr[6:9]; + + assign ex0_instr[10] = (rv_xu0_ex0_fusion[0] == 1'b1) ? rv_xu0_ex0_fusion[3] : + rv_xu0_ex0_instr[10]; + + assign ex0_instr[11:15] = (rv_xu0_ex0_fusion[0] == 1'b1) ? 5'b00000 : + rv_xu0_ex0_instr[11:15]; + + assign ex0_instr[16:20] = (rv_xu0_ex0_fusion[0:2] == 3'b100) ? 5'b00000 : + (rv_xu0_ex0_fusion[0:2] == 3'b101) ? rv_xu0_ex0_fusion[4:8] : + (rv_xu0_ex0_fusion[0:2] == 3'b110) ? 5'b00000 : + (rv_xu0_ex0_fusion[0:2] == 3'b111) ? rv_xu0_ex0_fusion[4:8] : + rv_xu0_ex0_instr[16:20]; + + assign ex0_instr[21:30] = (rv_xu0_ex0_fusion[0:2] == 3'b100) ? 10'b0000000000 : + (rv_xu0_ex0_fusion[0:2] == 3'b101) ? rv_xu0_ex0_fusion[9:18] : + (rv_xu0_ex0_fusion[0:2] == 3'b110) ? 10'b0000100000 : + (rv_xu0_ex0_fusion[0:2] == 3'b111) ? rv_xu0_ex0_fusion[9:18] : + rv_xu0_ex0_instr[21:30]; + + // Kill the opcode31 if fusion is on, so I don't get a false decode. + assign ex0_instr[31] = (rv_xu0_ex0_fusion[0:2] == 3'b100) ? 1'b0 : + (rv_xu0_ex0_fusion[0:2] == 3'b101) ? rv_xu0_ex0_fusion[19] : + (rv_xu0_ex0_fusion[0:2] == 3'b110) ? 1'b0 : + (rv_xu0_ex0_fusion[0:2] == 3'b111) ? rv_xu0_ex0_fusion[19] : + rv_xu0_ex0_instr[31]; + + assign ex0_opcode_is_31 = (rv_xu0_ex0_instr[0:5] == 6'b011111) & (rv_xu0_ex0_fusion[0] == 1'b0); + assign ex0_opcode_is_19 = (rv_xu0_ex0_instr[0:5] == 6'b010011); + + assign ex0_is_b = ( rv_xu0_ex0_instr[0:5] == 6'b010010) ? 1'b1 : 1'b0; + assign ex0_is_bc = ( ex0_instr[0:5] == 6'b010000) ? 1'b1 : 1'b0; + assign ex0_is_addi = ( rv_xu0_ex0_instr[0:5] == 6'b001110) ? 1'b1 : 1'b0; + assign ex0_is_addic = ( rv_xu0_ex0_instr[0:5] == 6'b001100) ? 1'b1 : 1'b0; + assign ex0_is_addicr = ( rv_xu0_ex0_instr[0:5] == 6'b001101) ? 1'b1 : 1'b0; + assign ex0_is_addme = (ex0_opcode_is_31 & rv_xu0_ex0_instr[22:30] == 9'b011101010) ? 1'b1 : 1'b0; + assign ex0_is_addis = ( rv_xu0_ex0_instr[0:5] == 6'b001111) ? 1'b1 : 1'b0; + assign ex0_is_addze = (ex0_opcode_is_31 & rv_xu0_ex0_instr[22:30] == 9'b011001010) ? 1'b1 : 1'b0; + assign ex0_is_andir = ( rv_xu0_ex0_instr[0:5] == 6'b011100) ? 1'b1 : 1'b0; + assign ex0_is_andisr = ( rv_xu0_ex0_instr[0:5] == 6'b011101) ? 1'b1 : 1'b0; + assign ex0_is_cmpi = ( ex0_instr[0:5] == 6'b001011) ? 1'b1 : 1'b0; + assign ex0_is_cmpli = ( ex0_instr[0:5] == 6'b001010) ? 1'b1 : 1'b0; + assign ex0_is_mulli = ( rv_xu0_ex0_instr[0:5] == 6'b000111) ? 1'b1 : 1'b0; + assign ex0_is_neg = (ex0_opcode_is_31 & rv_xu0_ex0_instr[22:30] == 9'b001101000) ? 1'b1 : 1'b0; + assign ex0_is_ori = ( rv_xu0_ex0_instr[0:5] == 6'b011000) ? 1'b1 : 1'b0; + assign ex0_is_oris = ( rv_xu0_ex0_instr[0:5] == 6'b011001) ? 1'b1 : 1'b0; + assign ex0_is_subfic = ( rv_xu0_ex0_instr[0:5] == 6'b001000) ? 1'b1 : 1'b0; + assign ex0_is_subfze = (ex0_opcode_is_31 & rv_xu0_ex0_instr[22:30] == 9'b011001000) ? 1'b1 : 1'b0; + assign ex0_is_twi = ( rv_xu0_ex0_instr[0:5] == 6'b000011) ? 1'b1 : 1'b0; + assign ex0_is_tdi = ( rv_xu0_ex0_instr[0:5] == 6'b000010) ? 1'b1 : 1'b0; + assign ex0_is_xori = ( rv_xu0_ex0_instr[0:5] == 6'b011010) ? 1'b1 : 1'b0; + assign ex0_is_xoris = ( rv_xu0_ex0_instr[0:5] == 6'b011011) ? 1'b1 : 1'b0; + assign ex0_is_subfme = (ex0_opcode_is_31 & rv_xu0_ex0_instr[22:30] == 9'b011101000) ? 1'b1 : 1'b0; + assign ex0_is_mtcrf = (ex0_opcode_is_31 & rv_xu0_ex0_instr[21:30] == 10'b0010010000) ? 1'b1 : 1'b0; + assign ex0_is_mtmsr = (ex0_opcode_is_31 & rv_xu0_ex0_instr[21:30] == 10'b0010010010) ? 1'b1 : 1'b0; + assign ex0_is_mtspr = (ex0_opcode_is_31 & rv_xu0_ex0_instr[21:30] == 10'b0111010011) ? 1'b1 : 1'b0; + assign ex0_is_wrtee = (ex0_opcode_is_31 & rv_xu0_ex0_instr[21:30] == 10'b0010000011) ? 1'b1 : 1'b0; + assign ex0_is_wrteei = (ex0_opcode_is_31 & rv_xu0_ex0_instr[21:30] == 10'b0010100011) ? 1'b1 : 1'b0; + assign ex0_is_eratwe = (ex0_opcode_is_31 & rv_xu0_ex0_instr[21:30] == 10'b0011010011) ? 1'b1 : 1'b0; + assign ex0_is_erativax = (ex0_opcode_is_31 & rv_xu0_ex0_instr[21:30] == 10'b1100110011) ? 1'b1 : 1'b0; + assign ex0_is_eratsx = (ex0_opcode_is_31 & rv_xu0_ex0_instr[21:30] == 10'b0010010011) ? 1'b1 : 1'b0; + + assign ex1_opcode_is_0 = ex1_instr_q[0:5] == 6'b000000; + assign ex1_opcode_is_19 = ex1_instr_q[0:5] == 6'b010011; + assign ex1_opcode_is_31 = ex1_instr_q[0:5] == 6'b011111; + + assign ex1_is_add = (ex1_opcode_is_31 & ex1_instr_q[22:30] == 9'b100001010) ? 1'b1 : 1'b0; + assign ex1_is_addc = (ex1_opcode_is_31 & ex1_instr_q[22:30] == 9'b000001010) ? 1'b1 : 1'b0; + assign ex1_is_adde = (ex1_opcode_is_31 & ex1_instr_q[22:30] == 9'b010001010) ? 1'b1 : 1'b0; + assign ex1_is_addi = ( ex1_instr_q[0:5] == 6'b001110) ? 1'b1 : 1'b0; + assign ex1_is_addic = ( ex1_instr_q[0:5] == 6'b001100) ? 1'b1 : 1'b0; + assign ex1_is_addicr = ( ex1_instr_q[0:5] == 6'b001101) ? 1'b1 : 1'b0; + assign ex1_is_addis = ( ex1_instr_q[0:5] == 6'b001111) ? 1'b1 : 1'b0; + assign ex1_is_addme = (ex1_opcode_is_31 & ex1_instr_q[22:30] == 9'b011101010) ? 1'b1 : 1'b0; + assign ex1_is_addze = (ex1_opcode_is_31 & ex1_instr_q[22:30] == 9'b011001010) ? 1'b1 : 1'b0; + assign ex1_is_andir = ( ex1_instr_q[0:5] == 6'b011100) ? 1'b1 : 1'b0; + assign ex1_is_andisr = ( ex1_instr_q[0:5] == 6'b011101) ? 1'b1 : 1'b0; + assign ex1_is_addg6s = (ex1_opcode_is_31 & ex1_instr_q[22:30] == 9'b001001010) ? 1'b1 : 1'b0; + assign ex1_is_attn = (ex1_opcode_is_0 & ex1_instr_q[21:30] == 10'b0100000000) ? 1'b1 : 1'b0; + assign ex1_is_bc = ( ex1_instr_q[0:5] == 6'b010000) ? 1'b1 : 1'b0; + assign ex1_is_bpermd = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0011111100) ? 1'b1 : 1'b0; + assign ex1_is_cdtbcd = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0100011010) ? 1'b1 : 1'b0; + assign ex1_is_cbcdtd = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0100111010) ? 1'b1 : 1'b0; + assign ex1_is_cmp = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0000000000) ? 1'b1 : 1'b0; + assign ex1_is_cmpi = ( ex1_instr_q[0:5] == 6'b001011) ? 1'b1 : 1'b0; + assign ex1_is_cmpl = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0000100000) ? 1'b1 : 1'b0; + assign ex1_is_cmpli = ( ex1_instr_q[0:5] == 6'b001010) ? 1'b1 : 1'b0; + assign ex1_is_cntlzw = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0000011010) ? 1'b1 : 1'b0; + assign ex1_is_cntlzd = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0000111010) ? 1'b1 : 1'b0; + assign ex1_is_divd = (ex1_opcode_is_31 & ex1_instr_q[22:30] == 9'b111101001) ? 1'b1 : 1'b0; + assign ex1_is_divdu = (ex1_opcode_is_31 & ex1_instr_q[22:30] == 9'b111001001) ? 1'b1 : 1'b0; + assign ex1_is_divw = (ex1_opcode_is_31 & ex1_instr_q[22:30] == 9'b111101011) ? 1'b1 : 1'b0; + assign ex1_is_divwu = (ex1_opcode_is_31 & ex1_instr_q[22:30] == 9'b111001011) ? 1'b1 : 1'b0; + assign ex1_is_divwe = (ex1_opcode_is_31 & ex1_instr_q[22:30] == 9'b110101011) ? 1'b1 : 1'b0; + assign ex1_is_divweu = (ex1_opcode_is_31 & ex1_instr_q[22:30] == 9'b110001011) ? 1'b1 : 1'b0; + assign ex1_is_divde = (ex1_opcode_is_31 & ex1_instr_q[22:30] == 9'b110101001) ? 1'b1 : 1'b0; + assign ex1_is_divdeu = (ex1_opcode_is_31 & ex1_instr_q[22:30] == 9'b110001001) ? 1'b1 : 1'b0; + assign ex1_is_dlmzb = (ex1_opcode_is_31 & ex1_instr_q[22:30] == 9'b001001110) ? 1'b1 : 1'b0; + assign ex1_is_dnh = (ex1_opcode_is_19 & ex1_instr_q[21:30] == 10'b0011000110) ? 1'b1 : 1'b0; + assign ex1_is_ehpriv = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0100001110) ? 1'b1 : 1'b0; + assign ex1_is_eratilx = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0000110011) ? 1'b1 : 1'b0; + assign ex1_is_erativax = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b1100110011) ? 1'b1 : 1'b0; + assign ex1_is_eratre = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0010110011) ? 1'b1 : 1'b0; + assign ex1_is_eratsx = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0010010011) ? 1'b1 : 1'b0; + assign ex1_is_eratwe = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0011010011) ? 1'b1 : 1'b0; + assign ex1_is_isel = (ex1_opcode_is_31 & ex1_instr_q[26:30] == 5'b01111) ? 1'b1 : 1'b0; + assign ex1_is_mtxer = (ex1_opcode_is_31 & ex1_instr_q[11:30] == 20'b00001000000111010011) ? 1'b1 : 1'b0; + assign ex1_is_mfxer = (ex1_opcode_is_31 & ex1_instr_q[11:30] == 20'b00001000000101010011) ? 1'b1 : 1'b0; + assign ex1_is_mflr = (ex1_opcode_is_31 & ex1_instr_q[11:30] == 20'b01000000000101010011) ? 1'b1 : 1'b0; + assign ex1_is_mftar = (ex1_opcode_is_31 & ex1_instr_q[11:30] == 20'b01111110010101010011) ? 1'b1 : 1'b0; + assign ex1_is_mfctr = (ex1_opcode_is_31 & ex1_instr_q[11:30] == 20'b01001000000101010011) ? 1'b1 : 1'b0; + assign ex1_is_msgclr = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0011101110) ? 1'b1 : 1'b0; + assign ex1_is_mtiar = (ex1_opcode_is_31 & ex1_instr_q[11:30] == 20'b10010110110111010011) ? 1'b1 : 1'b0; + assign ex1_is_mfcr = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0000010011) ? 1'b1 : 1'b0; + assign ex1_is_mtcrf = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0010010000) ? 1'b1 : 1'b0; + assign ex1_is_mtmsr = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0010010010) ? 1'b1 : 1'b0; + assign ex1_is_mtspr = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0111010011) ? 1'b1 : 1'b0; + assign ex1_is_mulhd = (ex1_opcode_is_31 & ex1_instr_q[22:30] == 9'b001001001) ? 1'b1 : 1'b0; + assign ex1_is_mulhdu = (ex1_opcode_is_31 & ex1_instr_q[22:30] == 9'b000001001) ? 1'b1 : 1'b0; + assign ex1_is_mulhw = (ex1_opcode_is_31 & ex1_instr_q[22:30] == 9'b001001011) ? 1'b1 : 1'b0; + assign ex1_is_mulhwu = (ex1_opcode_is_31 & ex1_instr_q[22:30] == 9'b000001011) ? 1'b1 : 1'b0; + assign ex1_is_mulld = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0011101001) ? 1'b1 : 1'b0; + assign ex1_is_mulldo = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b1011101001) ? 1'b1 : 1'b0; + assign ex1_is_mulli = ( ex1_instr_q[0:5] == 6'b000111) ? 1'b1 : 1'b0; + assign ex1_is_mullw = (ex1_opcode_is_31 & ex1_instr_q[22:30] == 9'b011101011) ? 1'b1 : 1'b0; + assign ex1_is_neg = (ex1_opcode_is_31 & ex1_instr_q[22:30] == 9'b001101000) ? 1'b1 : 1'b0; + assign ex1_is_ori = ( ex1_instr_q[0:5] == 6'b011000) ? 1'b1 : 1'b0; + assign ex1_is_oris = ( ex1_instr_q[0:5] == 6'b011001) ? 1'b1 : 1'b0; + assign ex1_is_popcntb = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0001111010) ? 1'b1 : 1'b0; + assign ex1_is_popcntw = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0101111010) ? 1'b1 : 1'b0; + assign ex1_is_popcntd = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0111111010) ? 1'b1 : 1'b0; + assign ex1_is_srad = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b1100011010) ? 1'b1 : 1'b0; + assign ex1_is_sradi = (ex1_opcode_is_31 & ex1_instr_q[21:29] == 9'b110011101) ? 1'b1 : 1'b0; + assign ex1_is_sraw = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b1100011000) ? 1'b1 : 1'b0; + assign ex1_is_srawi = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b1100111000) ? 1'b1 : 1'b0; + assign ex1_is_subf = (ex1_opcode_is_31 & ex1_instr_q[22:30] == 9'b000101000) ? 1'b1 : 1'b0; + assign ex1_is_subfc = (ex1_opcode_is_31 & ex1_instr_q[22:30] == 9'b000001000) ? 1'b1 : 1'b0; + assign ex1_is_subfe = (ex1_opcode_is_31 & ex1_instr_q[22:30] == 9'b010001000) ? 1'b1 : 1'b0; + assign ex1_is_subfic = ( ex1_instr_q[0:5] == 6'b001000) ? 1'b1 : 1'b0; + assign ex1_is_subfme = (ex1_opcode_is_31 & ex1_instr_q[22:30] == 9'b011101000) ? 1'b1 : 1'b0; + assign ex1_is_subfze = (ex1_opcode_is_31 & ex1_instr_q[22:30] == 9'b011001000) ? 1'b1 : 1'b0; + assign ex1_is_tlbilx = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0000010010) ? 1'b1 : 1'b0; + assign ex1_is_tlbivax = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b1100010010) ? 1'b1 : 1'b0; + assign ex1_is_tlbre = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b1110110010) ? 1'b1 : 1'b0; + assign ex1_is_tlbsx = (ex1_opcode_is_31 & ex1_instr_q[21:31] == 11'b11100100100) ? 1'b1 : 1'b0; + assign ex1_is_tlbsxr = (ex1_opcode_is_31 & ex1_instr_q[21:31] == 11'b11100100101) ? 1'b1 : 1'b0; + assign ex1_is_tlbsrx = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b1101010010) ? 1'b1 : 1'b0; + assign ex1_is_tlbwe = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b1111010010) ? 1'b1 : 1'b0; + assign ex1_is_td = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0001000100) ? 1'b1 : 1'b0; + assign ex1_is_tdi = ( ex1_instr_q[0:5] == 6'b000010) ? 1'b1 : 1'b0; + assign ex1_is_tw = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0000000100) ? 1'b1 : 1'b0; + assign ex1_is_twi = ( ex1_instr_q[0:5] == 6'b000011) ? 1'b1 : 1'b0; + assign ex1_is_wrtee = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0010000011) ? 1'b1 : 1'b0; + assign ex1_is_wrteei = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0010100011) ? 1'b1 : 1'b0; + assign ex1_is_xori = ( ex1_instr_q[0:5] == 6'b011010) ? 1'b1 : 1'b0; + assign ex1_is_xoris = ( ex1_instr_q[0:5] == 6'b011011) ? 1'b1 : 1'b0; + assign ex1_is_mfspr = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0101010011) ? 1'b1 : 1'b0; // 31/339 + assign ex1_is_mfmsr = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0001010011) ? 1'b1 : 1'b0; // 31/083 + assign ex1_is_mftb = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0101110011) ? 1'b1 : 1'b0; // 31/371 + + + assign ex1_is_pri1 = (ex1_opcode_is_31 & ex1_instr_q[6:31] == 26'b11111111111111101101111000) ? 1'b1 : 1'b0; + assign ex1_is_pri2 = (ex1_opcode_is_31 & ex1_instr_q[6:31] == 26'b00001000010000101101111000) ? 1'b1 : 1'b0; + assign ex1_is_pri3 = (ex1_opcode_is_31 & ex1_instr_q[6:31] == 26'b00110001100011001101111000) ? 1'b1 : 1'b0; + assign ex1_is_pri4 = (ex1_opcode_is_31 & ex1_instr_q[6:31] == 26'b00010000100001001101111000) ? 1'b1 : 1'b0; + assign ex1_is_pri5 = (ex1_opcode_is_31 & ex1_instr_q[6:31] == 26'b00101001010010101101111000) ? 1'b1 : 1'b0; + assign ex1_is_pri6 = (ex1_opcode_is_31 & ex1_instr_q[6:31] == 26'b00011000110001101101111000) ? 1'b1 : 1'b0; + assign ex1_is_pri7 = (ex1_opcode_is_31 & ex1_instr_q[6:31] == 26'b00111001110011101101111000) ? 1'b1 : 1'b0; + + //------------------------------------------------------------------------------------------ + // Latches + //------------------------------------------------------------------------------------------ + tri_rlmreg_p #(.WIDTH(5), .OFFSET(1),.INIT(0), .NEEDS_SRESET(1)) exx_act_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[exx_act_offset : exx_act_offset + 5-1]), + .scout(sov[exx_act_offset : exx_act_offset + 5-1]), + .din(exx_act_d), + .dout(exx_act_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_s2_v_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_s2_v_offset]), + .scout(sov[ex1_s2_v_offset]), + .din(rv_xu0_ex0_s2_v), + .dout(ex1_s2_v_q) + ); + tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_s2_t_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_s2_t_offset : ex1_s2_t_offset + 3-1]), + .scout(sov[ex1_s2_t_offset : ex1_s2_t_offset + 3-1]), + .din(rv_xu0_ex0_s2_t), + .dout(ex1_s2_t_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_s3_v_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_s3_v_offset]), + .scout(sov[ex1_s3_v_offset]), + .din(rv_xu0_ex0_s3_v), + .dout(ex1_s3_v_q) + ); + tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_s3_t_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_s3_t_offset : ex1_s3_t_offset + 3-1]), + .scout(sov[ex1_s3_t_offset : ex1_s3_t_offset + 3-1]), + .din(rv_xu0_ex0_s3_t), + .dout(ex1_s3_t_q) + ); + tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_t1_t_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_t1_t_offset : ex1_t1_t_offset + 3-1]), + .scout(sov[ex1_t1_t_offset : ex1_t1_t_offset + 3-1]), + .din(rv_xu0_ex0_t1_t), + .dout(ex1_t1_t_q) + ); + tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_t2_t_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_t2_t_offset : ex1_t2_t_offset + 3-1]), + .scout(sov[ex1_t2_t_offset : ex1_t2_t_offset + 3-1]), + .din(rv_xu0_ex0_t2_t), + .dout(ex1_t2_t_q) + ); + tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_t3_t_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_t3_t_offset : ex1_t3_t_offset + 3-1]), + .scout(sov[ex1_t3_t_offset : ex1_t3_t_offset + 3-1]), + .din(rv_xu0_ex0_t3_t), + .dout(ex1_t3_t_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_t1_v_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_t1_v_offset]), + .scout(sov[ex1_t1_v_offset]), + .din(rv_xu0_ex0_t1_v), + .dout(ex1_t1_v_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_t2_v_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_t2_v_offset]), + .scout(sov[ex1_t2_v_offset]), + .din(rv_xu0_ex0_t2_v), + .dout(ex1_t2_v_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_t3_v_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_t3_v_offset]), + .scout(sov[ex1_t3_v_offset]), + .din(rv_xu0_ex0_t3_v), + .dout(ex1_t3_v_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_t1_p_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_t1_p_offset : ex1_t1_p_offset + `GPR_POOL_ENC-1]), + .scout(sov[ex1_t1_p_offset : ex1_t1_p_offset + `GPR_POOL_ENC-1]), + .din(rv_xu0_ex0_t1_p), + .dout(ex1_t1_p_q) + ); + tri_rlmreg_p #(.WIDTH(`XER_POOL_ENC), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_t2_p_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_t2_p_offset : ex1_t2_p_offset + `XER_POOL_ENC-1]), + .scout(sov[ex1_t2_p_offset : ex1_t2_p_offset + `XER_POOL_ENC-1]), + .din(rv_xu0_ex0_t2_p[XER_LEFT:`GPR_POOL_ENC-1]), + .dout(ex1_t2_p_q) + ); + tri_rlmreg_p #(.WIDTH(`CR_POOL_ENC), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_t3_p_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_t3_p_offset : ex1_t3_p_offset + `CR_POOL_ENC-1]), + .scout(sov[ex1_t3_p_offset : ex1_t3_p_offset + `CR_POOL_ENC-1]), + .din(rv_xu0_ex0_t3_p[CR_LEFT:`GPR_POOL_ENC-1]), + .dout(ex1_t3_p_q) + ); + tri_rlmreg_p #(.WIDTH(32), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_instr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_instr_offset : ex1_instr_offset + 32-1]), + .scout(sov[ex1_instr_offset : ex1_instr_offset + 32-1]), + .din(ex0_instr), + .dout(ex1_instr_q) + ); + tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_ucode_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_ucode_offset : ex1_ucode_offset + 3-1]), + .scout(sov[ex1_ucode_offset : ex1_ucode_offset + 3-1]), + .din(rv_xu0_ex0_ucode), + .dout(ex1_ucode_q) + ); + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_itag_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_itag_offset : ex1_itag_offset + `ITAG_SIZE_ENC-1]), + .scout(sov[ex1_itag_offset : ex1_itag_offset + `ITAG_SIZE_ENC-1]), + .din(rv_xu0_ex0_itag), + .dout(ex1_itag_q) + ); + tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_add_ci_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_add_ci_sel_offset : ex2_add_ci_sel_offset + 2-1]), + .scout(sov[ex2_add_ci_sel_offset : ex2_add_ci_sel_offset + 2-1]), + .din(ex1_add_ci_sel), + .dout(ex2_add_ci_sel_q) + ); + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_itag_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_itag_offset : ex2_itag_offset + `ITAG_SIZE_ENC-1]), + .scout(sov[ex2_itag_offset : ex2_itag_offset + `ITAG_SIZE_ENC-1]), + .din(ex1_itag_q), + .dout(ex2_itag_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_t1_p_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_t1_p_offset : ex2_t1_p_offset + `GPR_POOL_ENC-1]), + .scout(sov[ex2_t1_p_offset : ex2_t1_p_offset + `GPR_POOL_ENC-1]), + .din(ex1_t1_p_q), + .dout(ex2_t1_p_q) + ); + tri_rlmreg_p #(.WIDTH(`XER_POOL_ENC), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_t2_p_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_t2_p_offset : ex2_t2_p_offset + `XER_POOL_ENC-1]), + .scout(sov[ex2_t2_p_offset : ex2_t2_p_offset + `XER_POOL_ENC-1]), + .din(ex1_t2_p_q), + .dout(ex2_t2_p_q) + ); + tri_rlmreg_p #(.WIDTH(`CR_POOL_ENC), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_t3_p_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_t3_p_offset : ex2_t3_p_offset + `CR_POOL_ENC-1]), + .scout(sov[ex2_t3_p_offset : ex2_t3_p_offset + `CR_POOL_ENC-1]), + .din(ex1_t3_p_q), + .dout(ex2_t3_p_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex3_t1_p_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex3_t1_p_offset : ex3_t1_p_offset + `GPR_POOL_ENC-1]), + .scout(sov[ex3_t1_p_offset : ex3_t1_p_offset + `GPR_POOL_ENC-1]), + .din(ex2_t1_p_q), + .dout(ex3_t1_p_q) + ); + tri_rlmreg_p #(.WIDTH(`XER_POOL_ENC), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex3_t2_p_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex3_t2_p_offset : ex3_t2_p_offset + `XER_POOL_ENC-1]), + .scout(sov[ex3_t2_p_offset : ex3_t2_p_offset + `XER_POOL_ENC-1]), + .din(ex2_t2_p_q), + .dout(ex3_t2_p_q) + ); + tri_rlmreg_p #(.WIDTH(`CR_POOL_ENC), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex3_t3_p_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex3_t3_p_offset : ex3_t3_p_offset + `CR_POOL_ENC-1]), + .scout(sov[ex3_t3_p_offset : ex3_t3_p_offset + `CR_POOL_ENC-1]), + .din(ex2_t3_p_q), + .dout(ex3_t3_p_q) + ); + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex3_itag_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex3_itag_offset : ex3_itag_offset + `ITAG_SIZE_ENC-1]), + .scout(sov[ex3_itag_offset : ex3_itag_offset + `ITAG_SIZE_ENC-1]), + .din(ex2_itag_q), + .dout(ex3_itag_q) + ); + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_itag_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[3]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex4_itag_offset : ex4_itag_offset + `ITAG_SIZE_ENC-1]), + .scout(sov[ex4_itag_offset : ex4_itag_offset + `ITAG_SIZE_ENC-1]), + .din(ex3_itag), + .dout(ex4_itag_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) cp_flush_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[cp_flush_offset : cp_flush_offset + `THREADS-1]), + .scout(sov[cp_flush_offset : cp_flush_offset + `THREADS-1]), + .din(cp_flush), + .dout(cp_flush_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex0_val_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX0]), + .mpw1_b(mpw1_dc_b[DEX0]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex0_val_offset : ex0_val_offset + `THREADS-1]), + .scout(sov[ex0_val_offset : ex0_val_offset + `THREADS-1]), + .din(rv2_val), + .dout(ex0_val_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_val_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_val_offset : ex1_val_offset + `THREADS-1]), + .scout(sov[ex1_val_offset : ex1_val_offset + `THREADS-1]), + .din(ex0_val), + .dout(ex1_val_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_val_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_val_offset : ex2_val_offset + `THREADS-1]), + .scout(sov[ex2_val_offset : ex2_val_offset + `THREADS-1]), + .din(ex1_val), + .dout(ex2_val_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex3_val_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex3_val_offset : ex3_val_offset + `THREADS-1]), + .scout(sov[ex3_val_offset : ex3_val_offset + `THREADS-1]), + .din(ex2_val), + .dout(ex3_val_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_val_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex4_val_offset : ex4_val_offset + `THREADS-1]), + .scout(sov[ex4_val_offset : ex4_val_offset + `THREADS-1]), + .din(ex3_val), + .dout(ex4_val_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex5_val_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), + .mpw1_b(mpw1_dc_b[DEX5]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex5_val_offset : ex5_val_offset + `THREADS-1]), + .scout(sov[ex5_val_offset : ex5_val_offset + `THREADS-1]), + .din(ex4_val), + .dout(ex5_val_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex6_val_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX6]), + .mpw1_b(mpw1_dc_b[DEX6]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex6_val_offset : ex6_val_offset + `THREADS-1]), + .scout(sov[ex6_val_offset : ex6_val_offset + `THREADS-1]), + .din(ex5_val), + .dout(ex6_val_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_ord_val_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_ord_val_offset : ex1_ord_val_offset + `THREADS-1]), + .scout(sov[ex1_ord_val_offset : ex1_ord_val_offset + `THREADS-1]), + .din(ex0_ord_val), + .dout(ex1_ord_val_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_ord_val_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_ord_val_offset : ex2_ord_val_offset + `THREADS-1]), + .scout(sov[ex2_ord_val_offset : ex2_ord_val_offset + `THREADS-1]), + .din(ex1_ord_val), + .dout(ex2_ord_val_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex3_ord_val_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex3_ord_val_offset : ex3_ord_val_offset + `THREADS-1]), + .scout(sov[ex3_ord_val_offset : ex3_ord_val_offset + `THREADS-1]), + .din(ex2_ord_val), + .dout(ex3_ord_val_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_ord_val_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex4_ord_val_offset : ex4_ord_val_offset + `THREADS-1]), + .scout(sov[ex4_ord_val_offset : ex4_ord_val_offset + `THREADS-1]), + .din(ex3_ord_val), + .dout(ex4_ord_val_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) spr_msr_cm_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[spr_msr_cm_offset : spr_msr_cm_offset + `THREADS-1]), + .scout(sov[spr_msr_cm_offset : spr_msr_cm_offset + `THREADS-1]), + .din(spr_msr_cm), + .dout(spr_msr_cm_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) spr_msr_gs_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[spr_msr_gs_offset : spr_msr_gs_offset + `THREADS-1]), + .scout(sov[spr_msr_gs_offset : spr_msr_gs_offset + `THREADS-1]), + .din(spr_msr_gs), + .dout(spr_msr_gs_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) spr_msr_pr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[spr_msr_pr_offset : spr_msr_pr_offset + `THREADS-1]), + .scout(sov[spr_msr_pr_offset : spr_msr_pr_offset + `THREADS-1]), + .din(spr_msr_pr), + .dout(spr_msr_pr_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) spr_epcr_dgtmi_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[spr_epcr_dgtmi_offset : spr_epcr_dgtmi_offset + `THREADS-1]), + .scout(sov[spr_epcr_dgtmi_offset : spr_epcr_dgtmi_offset + `THREADS-1]), + .din(spr_epcr_dgtmi), + .dout(spr_epcr_dgtmi_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_ccr2_notlb_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_ccr2_notlb_offset]), + .scout(sov[spr_ccr2_notlb_offset]), + .din(spr_ccr2_notlb), + .dout(spr_ccr2_notlb_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_br_val_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex4_br_val_offset : ex4_br_val_offset + `THREADS-1]), + .scout(sov[ex4_br_val_offset : ex4_br_val_offset + `THREADS-1]), + .din(br_dec_ex3_execute_vld), + .dout(ex4_br_val_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_ord_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_ord_offset]), + .scout(sov[ex1_ord_offset]), + .din(ex0_ord), + .dout(ex1_ord_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ord_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_ord_offset]), + .scout(sov[ex2_ord_offset]), + .din(ex1_ord_q), + .dout(ex2_ord_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_ord_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_ord_offset]), + .scout(sov[ex3_ord_offset]), + .din(ex2_ord_q), + .dout(ex3_ord_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_t1_v_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_t1_v_offset]), + .scout(sov[ex2_t1_v_offset]), + .din(ex1_t1_v_q), + .dout(ex2_t1_v_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_t2_v_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_t2_v_offset]), + .scout(sov[ex2_t2_v_offset]), + .din(ex1_t2_v_q), + .dout(ex2_t2_v_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_t3_v_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_t3_v_offset]), + .scout(sov[ex2_t3_v_offset]), + .din(ex1_t3_v_q), + .dout(ex2_t3_v_q) + ); + tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_t1_t_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_t1_t_offset : ex2_t1_t_offset + 3-1]), + .scout(sov[ex2_t1_t_offset : ex2_t1_t_offset + 3-1]), + .din(ex1_t1_t_q), + .dout(ex2_t1_t_q) + ); + tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_t2_t_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_t2_t_offset : ex2_t2_t_offset + 3-1]), + .scout(sov[ex2_t2_t_offset : ex2_t2_t_offset + 3-1]), + .din(ex1_t2_t_q), + .dout(ex2_t2_t_q) + ); + tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_t3_t_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_t3_t_offset : ex2_t3_t_offset + 3-1]), + .scout(sov[ex2_t3_t_offset : ex2_t3_t_offset + 3-1]), + .din(ex1_t3_t_q), + .dout(ex2_t3_t_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_t1_v_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_t1_v_offset]), + .scout(sov[ex3_t1_v_offset]), + .din(ex2_t1_v_q), + .dout(ex3_t1_v_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_t2_v_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_t2_v_offset]), + .scout(sov[ex3_t2_v_offset]), + .din(ex2_t2_v_q), + .dout(ex3_t2_v_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_t3_v_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_t3_v_offset]), + .scout(sov[ex3_t3_v_offset]), + .din(ex2_t3_v_q), + .dout(ex3_t3_v_q) + ); + tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex3_t1_t_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex3_t1_t_offset : ex3_t1_t_offset + 3-1]), + .scout(sov[ex3_t1_t_offset : ex3_t1_t_offset + 3-1]), + .din(ex2_t1_t_q), + .dout(ex3_t1_t_q) + ); + tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex3_t2_t_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex3_t2_t_offset : ex3_t2_t_offset + 3-1]), + .scout(sov[ex3_t2_t_offset : ex3_t2_t_offset + 3-1]), + .din(ex2_t2_t_q), + .dout(ex3_t2_t_q) + ); + tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex3_t3_t_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex3_t3_t_offset : ex3_t3_t_offset + 3-1]), + .scout(sov[ex3_t3_t_offset : ex3_t3_t_offset + 3-1]), + .din(ex2_t3_t_q), + .dout(ex3_t3_t_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_t1_v_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[3]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_t1_v_offset]), + .scout(sov[ex4_t1_v_offset]), + .din(ex3_t1_v_q), + .dout(ex4_t1_v_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_t2_v_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[3]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_t2_v_offset]), + .scout(sov[ex4_t2_v_offset]), + .din(ex3_t2_v_q), + .dout(ex4_t2_v_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_t3_v_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[3]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_t3_v_offset]), + .scout(sov[ex4_t3_v_offset]), + .din(ex3_t3_v_q), + .dout(ex4_t3_v_q) + ); + tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_t1_t_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[3]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex4_t1_t_offset : ex4_t1_t_offset + 3-1]), + .scout(sov[ex4_t1_t_offset : ex4_t1_t_offset + 3-1]), + .din(ex3_t1_t_q), + .dout(ex4_t1_t_q) + ); + tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_t2_t_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[3]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex4_t2_t_offset : ex4_t2_t_offset + 3-1]), + .scout(sov[ex4_t2_t_offset : ex4_t2_t_offset + 3-1]), + .din(ex3_t2_t_q), + .dout(ex4_t2_t_q) + ); + tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_t3_t_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[3]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex4_t3_t_offset : ex4_t3_t_offset + 3-1]), + .scout(sov[ex4_t3_t_offset : ex4_t3_t_offset + 3-1]), + .din(ex3_t3_t_q), + .dout(ex4_t3_t_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_t1_p_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[3]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex4_t1_p_offset : ex4_t1_p_offset + `GPR_POOL_ENC-1]), + .scout(sov[ex4_t1_p_offset : ex4_t1_p_offset + `GPR_POOL_ENC-1]), + .din(ex3_t1_p_q), + .dout(ex4_t1_p_q) + ); + tri_rlmreg_p #(.WIDTH(-XER_LEFT+`GPR_POOL_ENC), .OFFSET(XER_LEFT),.INIT(0), .NEEDS_SRESET(1)) ex4_t2_p_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[3]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex4_t2_p_offset : ex4_t2_p_offset + -XER_LEFT+`GPR_POOL_ENC-1]), + .scout(sov[ex4_t2_p_offset : ex4_t2_p_offset + -XER_LEFT+`GPR_POOL_ENC-1]), + .din(ex3_t2_p_q), + .dout(ex4_t2_p_q) + ); + tri_rlmreg_p #(.WIDTH(-CR_LEFT+`GPR_POOL_ENC), .OFFSET(CR_LEFT),.INIT(0), .NEEDS_SRESET(1)) ex4_t3_p_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[3]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex4_t3_p_offset : ex4_t3_p_offset + -CR_LEFT+`GPR_POOL_ENC-1]), + .scout(sov[ex4_t3_p_offset : ex4_t3_p_offset + -CR_LEFT+`GPR_POOL_ENC-1]), + .din(ex3_t3_p_q), + .dout(ex4_t3_p_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_t1_v_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[4]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), + .mpw1_b(mpw1_dc_b[DEX5]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_t1_v_offset]), + .scout(sov[ex5_t1_v_offset]), + .din(ex4_t1_v_q), + .dout(ex5_t1_v_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_t2_v_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[4]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), + .mpw1_b(mpw1_dc_b[DEX5]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_t2_v_offset]), + .scout(sov[ex5_t2_v_offset]), + .din(ex4_t2_v_q), + .dout(ex5_t2_v_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_t3_v_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[4]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), + .mpw1_b(mpw1_dc_b[DEX5]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_t3_v_offset]), + .scout(sov[ex5_t3_v_offset]), + .din(ex4_t3_v_q), + .dout(ex5_t3_v_q) + ); + tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex5_t1_t_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[4]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), + .mpw1_b(mpw1_dc_b[DEX5]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex5_t1_t_offset : ex5_t1_t_offset + 3-1]), + .scout(sov[ex5_t1_t_offset : ex5_t1_t_offset + 3-1]), + .din(ex4_t1_t_q), + .dout(ex5_t1_t_q) + ); + tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex5_t2_t_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[4]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), + .mpw1_b(mpw1_dc_b[DEX5]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex5_t2_t_offset : ex5_t2_t_offset + 3-1]), + .scout(sov[ex5_t2_t_offset : ex5_t2_t_offset + 3-1]), + .din(ex4_t2_t_q), + .dout(ex5_t2_t_q) + ); + tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex5_t3_t_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[4]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), + .mpw1_b(mpw1_dc_b[DEX5]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex5_t3_t_offset : ex5_t3_t_offset + 3-1]), + .scout(sov[ex5_t3_t_offset : ex5_t3_t_offset + 3-1]), + .din(ex4_t3_t_q), + .dout(ex5_t3_t_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex5_t1_p_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[4]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), + .mpw1_b(mpw1_dc_b[DEX5]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex5_t1_p_offset : ex5_t1_p_offset + `GPR_POOL_ENC-1]), + .scout(sov[ex5_t1_p_offset : ex5_t1_p_offset + `GPR_POOL_ENC-1]), + .din(ex4_t1_p_q), + .dout(ex5_t1_p_q) + ); + tri_rlmreg_p #(.WIDTH(-XER_LEFT+`GPR_POOL_ENC), .OFFSET(XER_LEFT),.INIT(0), .NEEDS_SRESET(1)) ex5_t2_p_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[4]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), + .mpw1_b(mpw1_dc_b[DEX5]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex5_t2_p_offset : ex5_t2_p_offset + -XER_LEFT+`GPR_POOL_ENC-1]), + .scout(sov[ex5_t2_p_offset : ex5_t2_p_offset + -XER_LEFT+`GPR_POOL_ENC-1]), + .din(ex4_t2_p_q), + .dout(ex5_t2_p_q) + ); + tri_rlmreg_p #(.WIDTH(-CR_LEFT+`GPR_POOL_ENC), .OFFSET(CR_LEFT),.INIT(0), .NEEDS_SRESET(1)) ex5_t3_p_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[4]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), + .mpw1_b(mpw1_dc_b[DEX5]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex5_t3_p_offset : ex5_t3_p_offset + -CR_LEFT+`GPR_POOL_ENC-1]), + .scout(sov[ex5_t3_p_offset : ex5_t3_p_offset + -CR_LEFT+`GPR_POOL_ENC-1]), + .din(ex4_t3_p_q), + .dout(ex5_t3_p_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_ord_t1_v_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ex4_ord_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), + .mpw1_b(mpw1_dc_b[DEX5]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_ord_t1_v_offset]), + .scout(sov[ex5_ord_t1_v_offset]), + .din(ex4_t1_v_q), + .dout(ex5_ord_t1_v_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_ord_t2_v_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ex4_ord_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), + .mpw1_b(mpw1_dc_b[DEX5]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_ord_t2_v_offset]), + .scout(sov[ex5_ord_t2_v_offset]), + .din(ex4_t2_v_q), + .dout(ex5_ord_t2_v_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_ord_t3_v_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ex4_ord_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), + .mpw1_b(mpw1_dc_b[DEX5]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_ord_t3_v_offset]), + .scout(sov[ex5_ord_t3_v_offset]), + .din(ex4_t3_v_q), + .dout(ex5_ord_t3_v_q) + ); + tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex5_ord_t1_t_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ex4_ord_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), + .mpw1_b(mpw1_dc_b[DEX5]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex5_ord_t1_t_offset : ex5_ord_t1_t_offset + 3-1]), + .scout(sov[ex5_ord_t1_t_offset : ex5_ord_t1_t_offset + 3-1]), + .din(ex4_t1_t_q), + .dout(ex5_ord_t1_t_q) + ); + tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex5_ord_t2_t_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ex4_ord_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), + .mpw1_b(mpw1_dc_b[DEX5]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex5_ord_t2_t_offset : ex5_ord_t2_t_offset + 3-1]), + .scout(sov[ex5_ord_t2_t_offset : ex5_ord_t2_t_offset + 3-1]), + .din(ex4_t2_t_q), + .dout(ex5_ord_t2_t_q) + ); + tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex5_ord_t3_t_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ex4_ord_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), + .mpw1_b(mpw1_dc_b[DEX5]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex5_ord_t3_t_offset : ex5_ord_t3_t_offset + 3-1]), + .scout(sov[ex5_ord_t3_t_offset : ex5_ord_t3_t_offset + 3-1]), + .din(ex4_t3_t_q), + .dout(ex5_ord_t3_t_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex5_ord_t1_p_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ex4_ord_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), + .mpw1_b(mpw1_dc_b[DEX5]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex5_ord_t1_p_offset : ex5_ord_t1_p_offset + `GPR_POOL_ENC-1]), + .scout(sov[ex5_ord_t1_p_offset : ex5_ord_t1_p_offset + `GPR_POOL_ENC-1]), + .din(ex4_t1_p_q), + .dout(ex5_ord_t1_p_q) + ); + tri_rlmreg_p #(.WIDTH(-XER_LEFT+`GPR_POOL_ENC), .OFFSET(XER_LEFT),.INIT(0), .NEEDS_SRESET(1)) ex5_ord_t2_p_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ex4_ord_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), + .mpw1_b(mpw1_dc_b[DEX5]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex5_ord_t2_p_offset : ex5_ord_t2_p_offset + -XER_LEFT+`GPR_POOL_ENC-1]), + .scout(sov[ex5_ord_t2_p_offset : ex5_ord_t2_p_offset + -XER_LEFT+`GPR_POOL_ENC-1]), + .din(ex4_t2_p_q), + .dout(ex5_ord_t2_p_q) + ); + tri_rlmreg_p #(.WIDTH(-CR_LEFT+`GPR_POOL_ENC), .OFFSET(CR_LEFT),.INIT(0), .NEEDS_SRESET(1)) ex5_ord_t3_p_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ex4_ord_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), + .mpw1_b(mpw1_dc_b[DEX5]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex5_ord_t3_p_offset : ex5_ord_t3_p_offset + -CR_LEFT+`GPR_POOL_ENC-1]), + .scout(sov[ex5_ord_t3_p_offset : ex5_ord_t3_p_offset + -CR_LEFT+`GPR_POOL_ENC-1]), + .din(ex4_t3_p_q), + .dout(ex5_ord_t3_p_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_gpr_we_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX6]), + .mpw1_b(mpw1_dc_b[DEX6]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_gpr_we_offset]), + .scout(sov[ex6_gpr_we_offset]), + .din(ex5_gpr_we), + .dout(ex6_gpr_we_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_xer_we_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX6]), + .mpw1_b(mpw1_dc_b[DEX6]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_xer_we_offset]), + .scout(sov[ex6_xer_we_offset]), + .din(ex5_xer_we), + .dout(ex6_xer_we_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_cr_we_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX6]), + .mpw1_b(mpw1_dc_b[DEX6]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_cr_we_offset]), + .scout(sov[ex6_cr_we_offset]), + .din(ex5_cr_we), + .dout(ex6_cr_we_q) + ); + tri_rlmreg_p #(.WIDTH(-CR_LEFT+`GPR_POOL_ENC), .OFFSET(CR_LEFT),.INIT(0), .NEEDS_SRESET(1)) ex6_cr_wa_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[5]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX6]), + .mpw1_b(mpw1_dc_b[DEX6]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex6_cr_wa_offset : ex6_cr_wa_offset + -CR_LEFT+`GPR_POOL_ENC-1]), + .scout(sov[ex6_cr_wa_offset : ex6_cr_wa_offset + -CR_LEFT+`GPR_POOL_ENC-1]), + .din(ex5_cr_wa), + .dout(ex6_cr_wa_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_ctr_we_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_ctr_we_offset]), + .scout(sov[ex4_ctr_we_offset]), + .din(ex3_ctr_we), + .dout(ex4_ctr_we_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_lr_we_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_lr_we_offset]), + .scout(sov[ex4_lr_we_offset]), + .din(ex3_lr_we), + .dout(ex4_lr_we_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex6_t1_p_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[5]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX6]), + .mpw1_b(mpw1_dc_b[DEX6]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex6_t1_p_offset : ex6_t1_p_offset + `GPR_POOL_ENC-1]), + .scout(sov[ex6_t1_p_offset : ex6_t1_p_offset + `GPR_POOL_ENC-1]), + .din(ex5_t1_p), + .dout(ex6_t1_p_q) + ); + tri_rlmreg_p #(.WIDTH(-XER_LEFT+`GPR_POOL_ENC), .OFFSET(XER_LEFT),.INIT(0), .NEEDS_SRESET(1)) ex6_t2_p_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[5]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX6]), + .mpw1_b(mpw1_dc_b[DEX6]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex6_t2_p_offset : ex6_t2_p_offset + -XER_LEFT+`GPR_POOL_ENC-1]), + .scout(sov[ex6_t2_p_offset : ex6_t2_p_offset + -XER_LEFT+`GPR_POOL_ENC-1]), + .din(ex5_t2_p), + .dout(ex6_t2_p_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_ccr2_en_attn_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_ccr2_en_attn_offset]), + .scout(sov[spr_ccr2_en_attn_offset]), + .din(spr_ccr2_en_attn), + .dout(spr_ccr2_en_attn_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_ccr4_en_dnh_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_ccr4_en_dnh_offset]), + .scout(sov[spr_ccr4_en_dnh_offset]), + .din(spr_ccr4_en_dnh), + .dout(spr_ccr4_en_dnh_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_ccr2_en_pc_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_ccr2_en_pc_offset]), + .scout(sov[spr_ccr2_en_pc_offset]), + .din(spr_ccr2_en_pc), + .dout(spr_ccr2_en_pc_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_ord_tid_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ex1_ord_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_ord_tid_offset : ex2_ord_tid_offset + `THREADS-1]), + .scout(sov[ex2_ord_tid_offset : ex2_ord_tid_offset + `THREADS-1]), + .din(ex1_ord_val_q), + .dout(ex2_ord_tid_q) + ); + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_ord_itag_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ex1_ord_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_ord_itag_offset : ex2_ord_itag_offset + `ITAG_SIZE_ENC-1]), + .scout(sov[ex2_ord_itag_offset : ex2_ord_itag_offset + `ITAG_SIZE_ENC-1]), + .din(ex1_itag_q), + .dout(ex2_ord_itag_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ord_is_eratre_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ex1_ord_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_ord_is_eratre_offset]), + .scout(sov[ex2_ord_is_eratre_offset]), + .din(ex1_is_eratre), + .dout(ex2_ord_is_eratre_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ord_is_eratwe_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ex1_ord_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_ord_is_eratwe_offset]), + .scout(sov[ex2_ord_is_eratwe_offset]), + .din(ex1_is_eratwe), + .dout(ex2_ord_is_eratwe_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ord_is_eratsx_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ex1_ord_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_ord_is_eratsx_offset]), + .scout(sov[ex2_ord_is_eratsx_offset]), + .din(ex1_is_eratsx), + .dout(ex2_ord_is_eratsx_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ord_is_eratilx_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ex1_ord_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_ord_is_eratilx_offset]), + .scout(sov[ex2_ord_is_eratilx_offset]), + .din(ex1_is_eratilx), + .dout(ex2_ord_is_eratilx_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ord_is_erativax_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ex1_ord_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_ord_is_erativax_offset]), + .scout(sov[ex2_ord_is_erativax_offset]), + .din(ex1_is_erativax), + .dout(ex2_ord_is_erativax_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ord_is_tlbre_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ex1_ord_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_ord_is_tlbre_offset]), + .scout(sov[ex2_ord_is_tlbre_offset]), + .din(ex1_is_tlbre), + .dout(ex2_ord_is_tlbre_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ord_is_tlbwe_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ex1_ord_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_ord_is_tlbwe_offset]), + .scout(sov[ex2_ord_is_tlbwe_offset]), + .din(ex1_is_tlbwe), + .dout(ex2_ord_is_tlbwe_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ord_is_tlbsx_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ex1_ord_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_ord_is_tlbsx_offset]), + .scout(sov[ex2_ord_is_tlbsx_offset]), + .din(ex1_is_tlbsx), + .dout(ex2_ord_is_tlbsx_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ord_is_tlbsxr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ex1_ord_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_ord_is_tlbsxr_offset]), + .scout(sov[ex2_ord_is_tlbsxr_offset]), + .din(ex1_is_tlbsxr), + .dout(ex2_ord_is_tlbsxr_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ord_is_tlbsrx_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ex1_ord_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_ord_is_tlbsrx_offset]), + .scout(sov[ex2_ord_is_tlbsrx_offset]), + .din(ex1_is_tlbsrx), + .dout(ex2_ord_is_tlbsrx_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ord_is_tlbivax_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ex1_ord_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_ord_is_tlbivax_offset]), + .scout(sov[ex2_ord_is_tlbivax_offset]), + .din(ex1_is_tlbivax), + .dout(ex2_ord_is_tlbivax_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ord_is_tlbilx_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ex1_ord_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_ord_is_tlbilx_offset]), + .scout(sov[ex2_ord_is_tlbilx_offset]), + .din(ex1_is_tlbilx), + .dout(ex2_ord_is_tlbilx_q) + ); + tri_rlmreg_p #(.WIDTH(2), .OFFSET(19),.INIT(0), .NEEDS_SRESET(1)) ex2_ord_tlb_ws_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ex1_ord_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_ord_tlb_ws_offset : ex2_ord_tlb_ws_offset + 2-1]), + .scout(sov[ex2_ord_tlb_ws_offset : ex2_ord_tlb_ws_offset + 2-1]), + .din(ex1_instr_q[19:20]), + .dout(ex2_ord_tlb_ws_q) + ); + tri_rlmreg_p #(.WIDTH(3), .OFFSET(8),.INIT(0), .NEEDS_SRESET(1)) ex2_ord_tlb_t_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ex1_ord_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_ord_tlb_t_offset : ex2_ord_tlb_t_offset + 3-1]), + .scout(sov[ex2_ord_tlb_t_offset : ex2_ord_tlb_t_offset + 3-1]), + .din(ex1_instr_q[8:10]), + .dout(ex2_ord_tlb_t_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_priv_excep_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_priv_excep_offset]), + .scout(sov[ex2_priv_excep_offset]), + .din(ex1_priv_excep), + .dout(ex2_priv_excep_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_hyp_priv_excep_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_hyp_priv_excep_offset]), + .scout(sov[ex2_hyp_priv_excep_offset]), + .din(ex1_hyp_priv_excep), + .dout(ex2_hyp_priv_excep_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_illegal_op_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_illegal_op_offset]), + .scout(sov[ex2_illegal_op_offset]), + .din(ex1_illegal_op), + .dout(ex2_illegal_op_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_flush2ucode_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_flush2ucode_offset]), + .scout(sov[ex2_flush2ucode_offset]), + .din(ex1_flush2ucode), + .dout(ex2_flush2ucode_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_tlb_illeg_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_tlb_illeg_offset]), + .scout(sov[ex2_tlb_illeg_offset]), + .din(ex1_tlb_illeg), + .dout(ex2_tlb_illeg_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_priv_excep_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_priv_excep_offset]), + .scout(sov[ex3_priv_excep_offset]), + .din(ex2_priv_excep_q), + .dout(ex3_priv_excep_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_hyp_priv_excep_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_hyp_priv_excep_offset]), + .scout(sov[ex3_hyp_priv_excep_offset]), + .din(ex2_hyp_priv_excep_q), + .dout(ex3_hyp_priv_excep_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_illegal_op_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_illegal_op_offset]), + .scout(sov[ex3_illegal_op_offset]), + .din(ex2_illegal_op_q), + .dout(ex3_illegal_op_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_flush2ucode_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_flush2ucode_offset]), + .scout(sov[ex3_flush2ucode_offset]), + .din(ex2_flush2ucode), + .dout(ex3_flush2ucode_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_flush2ucode_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_flush2ucode_offset]), + .scout(sov[ex4_flush2ucode_offset]), + .din(ex3_flush2ucode), + .dout(ex4_flush2ucode_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_ord_complete_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_ord_complete_offset]), + .scout(sov[ex1_ord_complete_offset]), + .din(ex0_ord_complete), + .dout(ex1_ord_complete_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ord_complete_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_ord_complete_offset]), + .scout(sov[ex2_ord_complete_offset]), + .din(ex1_ord_complete), + .dout(ex2_ord_complete_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_ord_complete_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_ord_complete_offset]), + .scout(sov[ex3_ord_complete_offset]), + .din(ex2_ord_complete), + .dout(ex3_ord_complete_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_ord_complete_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_ord_complete_offset]), + .scout(sov[ex4_ord_complete_offset]), + .din(ex3_ord_complete), + .dout(ex4_ord_complete_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_ord_complete_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), + .mpw1_b(mpw1_dc_b[DEX5]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_ord_complete_offset]), + .scout(sov[ex5_ord_complete_offset]), + .din(ex4_ord_complete), + .dout(ex5_ord_complete_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_ord_complete_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX6]), + .mpw1_b(mpw1_dc_b[DEX6]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_ord_complete_offset]), + .scout(sov[ex6_ord_complete_offset]), + .din(ex5_ord_complete), + .dout(ex6_ord_complete_q) + ); + tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) xu_iu_pri_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ex1_ord_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[xu_iu_pri_offset : xu_iu_pri_offset + 3-1]), + .scout(sov[xu_iu_pri_offset : xu_iu_pri_offset + 3-1]), + .din(xu_iu_pri_d), + .dout(xu_iu_pri_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) xu_iu_pri_val_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[xu_iu_pri_val_offset : xu_iu_pri_val_offset + `THREADS-1]), + .scout(sov[xu_iu_pri_val_offset : xu_iu_pri_val_offset + `THREADS-1]), + .din(xu_iu_pri_val_d), + .dout(xu_iu_pri_val_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_iu_hold_val_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[xu_iu_hold_val_offset]), + .scout(sov[xu_iu_hold_val_offset]), + .din(xu_iu_hold_val_d), + .dout(xu_iu_hold_val_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_lq_hold_val_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[xu_lq_hold_val_offset]), + .scout(sov[xu_lq_hold_val_offset]), + .din(xu_lq_hold_val_d), + .dout(xu_lq_hold_val_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_mm_hold_val_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[xu_mm_hold_val_offset]), + .scout(sov[xu_mm_hold_val_offset]), + .din(xu_mm_hold_val_d), + .dout(xu_mm_hold_val_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_iu_val_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[xu_iu_val_offset]), + .scout(sov[xu_iu_val_offset]), + .din(xu_iu_val_d), + .dout(xu_iu_val_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_lq_val_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[xu_lq_val_offset]), + .scout(sov[xu_lq_val_offset]), + .din(xu_lq_val_d), + .dout(xu_lq_val_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_mm_val_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[xu_mm_val_offset]), + .scout(sov[xu_mm_val_offset]), + .din(xu_mm_val_d), + .dout(xu_mm_val_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) xu_iu_val_2_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[xu_iu_val_2_offset : xu_iu_val_2_offset + `THREADS-1]), + .scout(sov[xu_iu_val_2_offset : xu_iu_val_2_offset + `THREADS-1]), + .din(xu_iu_val_2_d), + .dout(xu_iu_val_2_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) xu_lq_val_2_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[xu_lq_val_2_offset : xu_lq_val_2_offset + `THREADS-1]), + .scout(sov[xu_lq_val_2_offset : xu_lq_val_2_offset + `THREADS-1]), + .din(xu_lq_val_2_d), + .dout(xu_lq_val_2_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) xu_mm_val_2_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[xu_mm_val_2_offset : xu_mm_val_2_offset + `THREADS-1]), + .scout(sov[xu_mm_val_2_offset : xu_mm_val_2_offset + `THREADS-1]), + .din(xu_mm_val_2_d), + .dout(xu_mm_val_2_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_tlb_miss_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ord_outstanding_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ord_tlb_miss_offset]), + .scout(sov[ord_tlb_miss_offset]), + .din(ord_tlb_miss_d), + .dout(ord_tlb_miss_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_lrat_miss_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ord_outstanding_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ord_lrat_miss_offset]), + .scout(sov[ord_lrat_miss_offset]), + .din(ord_lrat_miss_d), + .dout(ord_lrat_miss_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_tlb_inelig_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ord_outstanding_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ord_tlb_inelig_offset]), + .scout(sov[ord_tlb_inelig_offset]), + .din(ord_tlb_inelig_d), + .dout(ord_tlb_inelig_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_pt_fault_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ord_outstanding_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ord_pt_fault_offset]), + .scout(sov[ord_pt_fault_offset]), + .din(ord_pt_fault_d), + .dout(ord_pt_fault_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_hv_priv_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ord_outstanding_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ord_hv_priv_offset]), + .scout(sov[ord_hv_priv_offset]), + .din(ord_hv_priv_d), + .dout(ord_hv_priv_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_illeg_mmu_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ord_outstanding_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ord_illeg_mmu_offset]), + .scout(sov[ord_illeg_mmu_offset]), + .din(ord_illeg_mmu_d), + .dout(ord_illeg_mmu_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_lq_flush_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ord_outstanding_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ord_lq_flush_offset]), + .scout(sov[ord_lq_flush_offset]), + .din(ord_lq_flush_d), + .dout(ord_lq_flush_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_spr_priv_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ord_outstanding_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ord_spr_priv_offset]), + .scout(sov[ord_spr_priv_offset]), + .din(ord_spr_priv_d), + .dout(ord_spr_priv_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_spr_illegal_spr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ord_outstanding_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ord_spr_illegal_spr_offset]), + .scout(sov[ord_spr_illegal_spr_offset]), + .din(ord_spr_illegal_spr_d), + .dout(ord_spr_illegal_spr_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_hyp_priv_spr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ord_outstanding_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ord_hyp_priv_spr_offset]), + .scout(sov[ord_hyp_priv_spr_offset]), + .din(ord_hyp_priv_spr_d), + .dout(ord_hyp_priv_spr_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_ex3_np1_flush_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ord_outstanding_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ord_ex3_np1_flush_offset]), + .scout(sov[ord_ex3_np1_flush_offset]), + .din(ord_ex3_np1_flush_d), + .dout(ord_ex3_np1_flush_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_ill_tlb_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ord_outstanding_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ord_ill_tlb_offset]), + .scout(sov[ord_ill_tlb_offset]), + .din(ord_ill_tlb_d), + .dout(ord_ill_tlb_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_priv_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ord_priv_offset]), + .scout(sov[ord_priv_offset]), + .din(ord_priv_d), + .dout(ord_priv_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_hyp_priv_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ord_hyp_priv_offset]), + .scout(sov[ord_hyp_priv_offset]), + .din(ord_hyp_priv_d), + .dout(ord_hyp_priv_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_hold_lq_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ord_outstanding_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ord_hold_lq_offset]), + .scout(sov[ord_hold_lq_offset]), + .din(ord_hold_lq_d), + .dout(ord_hold_lq_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_outstanding_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ord_outstanding_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ord_outstanding_offset]), + .scout(sov[ord_outstanding_offset]), + .din(ord_outstanding_d), + .dout(ord_outstanding_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_flushed_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ord_outstanding_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ord_flushed_offset]), + .scout(sov[ord_flushed_offset]), + .din(ord_flushed_d), + .dout(ord_flushed_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_done_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ord_done_offset]), + .scout(sov[ord_done_offset]), + .din(ord_done_d), + .dout(ord_done_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_mmu_req_sent_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ord_outstanding_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ord_mmu_req_sent_offset]), + .scout(sov[ord_mmu_req_sent_offset]), + .din(ord_mmu_req_sent_d), + .dout(ord_mmu_req_sent_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_core_block_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ord_outstanding_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ord_core_block_offset]), + .scout(sov[ord_core_block_offset]), + .din(ord_core_block_d), + .dout(ord_core_block_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_ierat_par_err_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ord_outstanding_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ord_ierat_par_err_offset]), + .scout(sov[ord_ierat_par_err_offset]), + .din(ord_ierat_par_err_d), + .dout(ord_ierat_par_err_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_derat_par_err_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ord_outstanding_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ord_derat_par_err_offset]), + .scout(sov[ord_derat_par_err_offset]), + .din(ord_derat_par_err_d), + .dout(ord_derat_par_err_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_tlb_multihit_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ord_outstanding_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ord_tlb_multihit_offset]), + .scout(sov[ord_tlb_multihit_offset]), + .din(ord_tlb_multihit_d), + .dout(ord_tlb_multihit_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_tlb_par_err_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ord_outstanding_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ord_tlb_par_err_offset]), + .scout(sov[ord_tlb_par_err_offset]), + .din(ord_tlb_par_err_d), + .dout(ord_tlb_par_err_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_tlb_lru_par_err_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ord_outstanding_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ord_tlb_lru_par_err_offset]), + .scout(sov[ord_tlb_lru_par_err_offset]), + .din(ord_tlb_lru_par_err_d), + .dout(ord_tlb_lru_par_err_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_local_snoop_reject_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ord_outstanding_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ord_local_snoop_reject_offset]), + .scout(sov[ord_local_snoop_reject_offset]), + .din(ord_local_snoop_reject_d), + .dout(ord_local_snoop_reject_q) + ); + tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) mmu_ord_n_flush_req_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[mmu_ord_n_flush_req_offset : mmu_ord_n_flush_req_offset + 2-1]), + .scout(sov[mmu_ord_n_flush_req_offset : mmu_ord_n_flush_req_offset + 2-1]), + .din(mmu_ord_n_flush_req_d), + .dout(mmu_ord_n_flush_req_q) + ); + tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) iu_ord_n_flush_req_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[iu_ord_n_flush_req_offset : iu_ord_n_flush_req_offset + 2-1]), + .scout(sov[iu_ord_n_flush_req_offset : iu_ord_n_flush_req_offset + 2-1]), + .din(iu_ord_n_flush_req_d), + .dout(iu_ord_n_flush_req_q) + ); + tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) lq_ord_n_flush_req_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[lq_ord_n_flush_req_offset : lq_ord_n_flush_req_offset + 2-1]), + .scout(sov[lq_ord_n_flush_req_offset : lq_ord_n_flush_req_offset + 2-1]), + .din(lq_ord_n_flush_req_d), + .dout(lq_ord_n_flush_req_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_np1_flush_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_np1_flush_offset]), + .scout(sov[ex4_np1_flush_offset]), + .din(ex3_np1_flush), + .dout(ex4_np1_flush_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_n_flush_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_n_flush_offset]), + .scout(sov[ex4_n_flush_offset]), + .din(ex3_n_flush), + .dout(ex4_n_flush_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_excep_val_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_excep_val_offset]), + .scout(sov[ex4_excep_val_offset]), + .din(ex3_excep_val), + .dout(ex4_excep_val_q) + ); + tri_rlmreg_p #(.WIDTH(5), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_excep_vector_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex4_excep_vector_offset : ex4_excep_vector_offset + 5-1]), + .scout(sov[ex4_excep_vector_offset : ex4_excep_vector_offset + 5-1]), + .din(ex3_excep_vector), + .dout(ex4_excep_vector_q) + ); + tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_ucode_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_ucode_offset : ex2_ucode_offset + 3-1]), + .scout(sov[ex2_ucode_offset : ex2_ucode_offset + 3-1]), + .din(ex1_ucode_q), + .dout(ex2_ucode_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_is_ehpriv_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_is_ehpriv_offset]), + .scout(sov[ex2_is_ehpriv_offset]), + .din(ex1_is_ehpriv), + .dout(ex2_is_ehpriv_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_is_ehpriv_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_is_ehpriv_offset]), + .scout(sov[ex3_is_ehpriv_offset]), + .din(ex2_is_ehpriv_q), + .dout(ex3_is_ehpriv_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_is_mtiar_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_is_mtiar_offset]), + .scout(sov[ex2_is_mtiar_offset]), + .din(ex1_is_mtiar), + .dout(ex2_is_mtiar_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_mtiar_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_mtiar_sel_offset]), + .scout(sov[ex3_mtiar_sel_offset]), + .din(ex2_mtiar_sel), + .dout(ex3_mtiar_sel_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_mtiar_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ord_mtiar_offset]), + .scout(sov[ord_mtiar_offset]), + .din(ord_mtiar_d), + .dout(ord_mtiar_q) + ); + tri_rlmreg_p #(.WIDTH(32), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ord_instr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ex1_ord_valid), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ord_instr_offset : ord_instr_offset + 32-1]), + .scout(sov[ord_instr_offset : ord_instr_offset + 32-1]), + .din(ord_instr_d), + .dout(ord_instr_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_is_erativax_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ex1_ord_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_is_erativax_offset]), + .scout(sov[ex2_is_erativax_offset]), + .din(ex1_is_erativax), + .dout(ex2_is_erativax_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) xu0_iu_mtiar_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[xu0_iu_mtiar_offset : xu0_iu_mtiar_offset + `THREADS-1]), + .scout(sov[xu0_iu_mtiar_offset : xu0_iu_mtiar_offset + `THREADS-1]), + .din(xu0_iu_mtiar_d), + .dout(xu0_iu_mtiar_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_is_cp_next_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ord_is_cp_next_offset]), + .scout(sov[ord_is_cp_next_offset]), + .din(ord_is_cp_next), + .dout(ord_is_cp_next_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_flush_1_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ord_flush_1_offset]), + .scout(sov[ord_flush_1_offset]), + .din(ord_spec_flush), + .dout(ord_flush_1_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_flush_2_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ord_flush_2_offset]), + .scout(sov[ord_flush_2_offset]), + .din(ord_flush_1_q), + .dout(ord_flush_2_q) + ); +generate begin : spr_mmucr0_tlbsel_gen + genvar i; + for (i=0;i<`THREADS;i=i+1) begin : spr_mmucr0_tlbsel_entry + tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) spr_mmucr0_tlbsel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[spr_mmucr0_tlbsel_offset + (i)*2 : spr_mmucr0_tlbsel_offset + (i+1)*2-1]), + .scout(sov[spr_mmucr0_tlbsel_offset + (i)*2 : spr_mmucr0_tlbsel_offset + (i+1)*2-1]), + .din(spr_mmucr0_tlbsel_d[i]), + .dout(spr_mmucr0_tlbsel_q[i]) + ); + end +end +endgenerate + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mm_xu_tlbwe_binv_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[mm_xu_tlbwe_binv_offset]), + .scout(sov[mm_xu_tlbwe_binv_offset]), + .din(mm_xu_tlbwe_binv), + .dout(mm_xu_tlbwe_binv_q) + ); + tri_rlmreg_p #(.WIDTH(32), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_instr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_instr_offset : ex2_instr_offset + 32-1]), + .scout(sov[ex2_instr_offset : ex2_instr_offset + 32-1]), + .din(ex1_instr_q), + .dout(ex2_instr_q) + ); + tri_rlmreg_p #(.WIDTH(32), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex3_instr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex3_instr_offset : ex3_instr_offset + 32-1]), + .scout(sov[ex3_instr_offset : ex3_instr_offset + 32-1]), + .din(ex2_instr_q), + .dout(ex3_instr_q) + ); + tri_rlmreg_p #(.WIDTH(32), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_instr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[3]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex4_instr_offset : ex4_instr_offset + 32-1]), + .scout(sov[ex4_instr_offset : ex4_instr_offset + 32-1]), + .din(ex3_instr_q), + .dout(ex4_instr_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_hpriv_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_hpriv_offset]), + .scout(sov[ex4_hpriv_offset]), + .din(ex3_hpriv), + .dout(ex4_hpriv_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_any_popcnt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_any_popcnt_offset]), + .scout(sov[ex2_any_popcnt_offset]), + .din(ex1_any_popcnt), + .dout(ex2_any_popcnt_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_any_popcnt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_any_popcnt_offset]), + .scout(sov[ex3_any_popcnt_offset]), + .din(ex2_any_popcnt_q), + .dout(ex3_any_popcnt_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_any_popcnt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[3]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_any_popcnt_offset]), + .scout(sov[ex4_any_popcnt_offset]), + .din(ex3_any_popcnt_q), + .dout(ex4_any_popcnt_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_any_cntlz_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_any_cntlz_offset]), + .scout(sov[ex2_any_cntlz_offset]), + .din(ex1_any_cntlz), + .dout(ex2_any_cntlz_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_any_cntlz_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_any_cntlz_offset]), + .scout(sov[ex3_any_cntlz_offset]), + .din(ex2_any_cntlz_q), + .dout(ex3_any_cntlz_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_is_bpermd_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_is_bpermd_offset]), + .scout(sov[ex2_is_bpermd_offset]), + .din(ex1_is_bpermd), + .dout(ex2_is_bpermd_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_is_bpermd_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_is_bpermd_offset]), + .scout(sov[ex3_is_bpermd_offset]), + .din(ex2_is_bpermd_q), + .dout(ex3_is_bpermd_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_is_dlmzb_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_is_dlmzb_offset]), + .scout(sov[ex2_is_dlmzb_offset]), + .din(ex1_is_dlmzb), + .dout(ex2_is_dlmzb_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_is_dlmzb_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_is_dlmzb_offset]), + .scout(sov[ex3_is_dlmzb_offset]), + .din(ex2_is_dlmzb_q), + .dout(ex3_is_dlmzb_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_mul_multicyc_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_mul_multicyc_offset]), + .scout(sov[ex2_mul_multicyc_offset]), + .din(ex1_mul_multicyc), + .dout(ex2_mul_multicyc_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_mul_multicyc_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_mul_multicyc_offset]), + .scout(sov[ex3_mul_multicyc_offset]), + .din(ex2_mul_multicyc_q), + .dout(ex3_mul_multicyc_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_mul_2c_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_mul_2c_offset]), + .scout(sov[ex2_mul_2c_offset]), + .din(ex1_mul_2c), + .dout(ex2_mul_2c_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_mul_3c_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_mul_3c_offset]), + .scout(sov[ex2_mul_3c_offset]), + .din(ex1_mul_3c), + .dout(ex2_mul_3c_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_mul_4c_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_mul_4c_offset]), + .scout(sov[ex2_mul_4c_offset]), + .din(ex1_mul_4c), + .dout(ex2_mul_4c_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_mul_2c_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_mul_2c_offset]), + .scout(sov[ex3_mul_2c_offset]), + .din(ex2_mul_2c_q), + .dout(ex3_mul_2c_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_mul_3c_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_mul_3c_offset]), + .scout(sov[ex3_mul_3c_offset]), + .din(ex2_mul_3c_q), + .dout(ex3_mul_3c_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_mul_4c_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_mul_4c_offset]), + .scout(sov[ex3_mul_4c_offset]), + .din(ex2_mul_4c_q), + .dout(ex3_mul_4c_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_mul_2c_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_mul_2c_offset]), + .scout(sov[ex4_mul_2c_offset]), + .din(ex4_mul_2c_d), + .dout(ex4_mul_2c_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_mul_3c_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_mul_3c_offset]), + .scout(sov[ex4_mul_3c_offset]), + .din(ex4_mul_3c_d), + .dout(ex4_mul_3c_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_mul_4c_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_mul_4c_offset]), + .scout(sov[ex4_mul_4c_offset]), + .din(ex4_mul_4c_d), + .dout(ex4_mul_4c_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_mul_3c_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), + .mpw1_b(mpw1_dc_b[DEX5]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_mul_3c_offset]), + .scout(sov[ex5_mul_3c_offset]), + .din(ex5_mul_3c_d), + .dout(ex5_mul_3c_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_mul_4c_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), + .mpw1_b(mpw1_dc_b[DEX5]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_mul_4c_offset]), + .scout(sov[ex5_mul_4c_offset]), + .din(ex5_mul_4c_d), + .dout(ex5_mul_4c_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_mul_4c_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX6]), + .mpw1_b(mpw1_dc_b[DEX6]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_mul_4c_offset]), + .scout(sov[ex6_mul_4c_offset]), + .din(ex6_mul_4c_d), + .dout(ex6_mul_4c_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) exx_mul_tid_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[exx_mul_tid_offset : exx_mul_tid_offset + `THREADS-1]), + .scout(sov[exx_mul_tid_offset : exx_mul_tid_offset + `THREADS-1]), + .din(exx_mul_tid_d), + .dout(exx_mul_tid_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_is_mtspr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_is_mtspr_offset]), + .scout(sov[ex2_is_mtspr_offset]), + .din(ex1_is_mtspr), + .dout(ex2_is_mtspr_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_is_mtspr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_is_mtspr_offset]), + .scout(sov[ex3_is_mtspr_offset]), + .din(ex2_is_mtspr_q), + .dout(ex3_is_mtspr_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_ram_active_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX6]), + .mpw1_b(mpw1_dc_b[DEX6]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex6_ram_active_offset]), + .scout(sov[ex6_ram_active_offset]), + .din(ex6_ram_active_d), + .dout(ex6_ram_active_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex6_tid_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX6]), + .mpw1_b(mpw1_dc_b[DEX6]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex6_tid_offset : ex6_tid_offset + `THREADS-1]), + .scout(sov[ex6_tid_offset : ex6_tid_offset + `THREADS-1]), + .din(ex6_tid_d), + .dout(ex6_tid_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_spec_flush_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_spec_flush_offset : ex1_spec_flush_offset + `THREADS-1]), + .scout(sov[ex1_spec_flush_offset : ex1_spec_flush_offset + `THREADS-1]), + .din(rv_xu0_ex0_spec_flush), + .dout(ex1_spec_flush_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_spec_flush_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_spec_flush_offset : ex2_spec_flush_offset + `THREADS-1]), + .scout(sov[ex2_spec_flush_offset : ex2_spec_flush_offset + `THREADS-1]), + .din(rv_xu0_ex1_spec_flush), + .dout(ex2_spec_flush_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex3_spec_flush_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex3_spec_flush_offset : ex3_spec_flush_offset + `THREADS-1]), + .scout(sov[ex3_spec_flush_offset : ex3_spec_flush_offset + `THREADS-1]), + .din(rv_xu0_ex2_spec_flush), + .dout(ex3_spec_flush_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ord_async_flush_before_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ord_async_flush_before_offset : ord_async_flush_before_offset + `THREADS-1]), + .scout(sov[ord_async_flush_before_offset : ord_async_flush_before_offset + `THREADS-1]), + .din(ord_async_flush_before_d), + .dout(ord_async_flush_before_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ord_async_flush_after_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ord_async_flush_after_offset : ord_async_flush_after_offset + `THREADS-1]), + .scout(sov[ord_async_flush_after_offset : ord_async_flush_after_offset + `THREADS-1]), + .din(ord_async_flush_after_d), + .dout(ord_async_flush_after_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_async_credit_wait_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ord_async_credit_wait_offset]), + .scout(sov[ord_async_credit_wait_offset]), + .din(ord_async_credit_wait_d), + .dout(ord_async_credit_wait_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) async_flush_req_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[async_flush_req_offset : async_flush_req_offset + `THREADS-1]), + .scout(sov[async_flush_req_offset : async_flush_req_offset + `THREADS-1]), + .din(async_flush_req_d), + .dout(async_flush_req_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) async_flush_req_2_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[async_flush_req_2_offset : async_flush_req_2_offset + `THREADS-1]), + .scout(sov[async_flush_req_2_offset : async_flush_req_2_offset + `THREADS-1]), + .din(async_flush_req_q), + .dout(async_flush_req_2_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) iu_async_complete_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[iu_async_complete_offset : iu_async_complete_offset + `THREADS-1]), + .scout(sov[iu_async_complete_offset : iu_async_complete_offset + `THREADS-1]), + .din(iu_xu_async_complete), + .dout(iu_async_complete_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_xu_credits_returned_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[iu_xu_credits_returned_offset]), + .scout(sov[iu_xu_credits_returned_offset]), + .din(iu_xu_credits_returned), + .dout(iu_xu_credits_returned_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_any_mfspr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_any_mfspr_offset]), + .scout(sov[ex2_any_mfspr_offset]), + .din(ex1_any_mfspr), + .dout(ex2_any_mfspr_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_any_mfspr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_any_mfspr_offset]), + .scout(sov[ex3_any_mfspr_offset]), + .din(ex2_any_mfspr), + .dout(ex3_any_mfspr_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_any_mtspr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_any_mtspr_offset]), + .scout(sov[ex2_any_mtspr_offset]), + .din(ex1_any_mtspr), + .dout(ex2_any_mtspr_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_any_mtspr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_any_mtspr_offset]), + .scout(sov[ex3_any_mtspr_offset]), + .din(ex2_any_mtspr), + .dout(ex3_any_mtspr_q) + ); + tri_rlmreg_p #(.WIDTH(4), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_perf_event_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[3]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex4_perf_event_offset : ex4_perf_event_offset + 4-1]), + .scout(sov[ex4_perf_event_offset : ex4_perf_event_offset + 4-1]), + .din(ex3_perf_event), + .dout(ex4_perf_event_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_any_mfspr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ex1_ord_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ord_any_mfspr_offset]), + .scout(sov[ord_any_mfspr_offset]), + .din(ex1_any_mfspr), + .dout(ord_any_mfspr_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_any_mtspr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ex1_ord_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ord_any_mtspr_offset]), + .scout(sov[ord_any_mtspr_offset]), + .din(ex1_any_mtspr), + .dout(ord_any_mtspr_q) + ); + tri_rlmreg_p #(.WIDTH(6), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ord_timer_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ord_outstanding_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ord_timer_offset : ord_timer_offset + 6-1]), + .scout(sov[ord_timer_offset : ord_timer_offset + 6-1]), + .din(ord_timer_d), + .dout(ord_timer_q) + ); + tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ord_timeout_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ord_timeout_offset : ord_timeout_offset + 2-1]), + .scout(sov[ord_timeout_offset : ord_timeout_offset + 2-1]), + .din(ord_timeout_d), + .dout(ord_timeout_q) + ); + + assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in}; + assign scan_out = sov[0]; + + assign unused = |{rv_xu0_ex0_t2_p[0:1],rv_xu0_ex0_t3_p[0]}; + assign ord_core_block_d = 1'b0; + +endmodule diff --git a/dev/verilog/work/xu0_div_r4.v b/dev/verilog/work/xu0_div_r4.v new file mode 100755 index 0000000..d2d0283 --- /dev/null +++ b/dev/verilog/work/xu0_div_r4.v @@ -0,0 +1,2042 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: XU Divide +// +//***************************************************************************** + +`include "tri_a2o.vh" + +module xu0_div_r4( + // Clocks + input [0:`NCLK_WIDTH-1] nclk, + + // Power + inout vdd, + inout gnd, + + // Pervasive + input d_mode_dc, + input delay_lclkr_dc, + input mpw1_dc_b, + input mpw2_dc_b, + input func_sl_force, + input func_sl_thold_0_b, + input sg_0, + input scan_in, + output scan_out, + + // Decode Inputs + input [0:7] dec_div_ex1_div_ctr, + input dec_div_ex1_div_act, + input [0:`THREADS-1] dec_div_ex1_div_val, + input dec_div_ex1_div_sign, // 0: Unsigned, 1: Signed + input dec_div_ex1_div_size, // 0: 32x32, 1: 64x64 + input dec_div_ex1_div_extd, // 0: regular, 1: extended + input dec_div_ex1_div_recform, + input dec_div_ex1_xer_ov_update, + + // Source Data + input [64-`GPR_WIDTH:63] byp_div_ex2_rs1, // NUM/DIVIDEND/RA + input [64-`GPR_WIDTH:63] byp_div_ex2_rs2, // DEN/DIVISOR /RB + input [0:9] byp_div_ex2_xer, + + // Flush cycle counter + input [0:`THREADS-1] cp_flush, + + // Target Data + output [64-`GPR_WIDTH:63] div_byp_ex4_rt, + output div_byp_ex4_done, + + // Overflow + output [0:9] div_byp_ex4_xer, + + // Record form + output [0:3] div_byp_ex4_cr, + + // CM + input ex1_spr_msr_cm, + + output [0:`THREADS-1] div_spr_running +); + + localparam msb = 64 - `GPR_WIDTH; + // Latches + wire [0:`THREADS-1] perf_divrunning_q, perf_divrunning_d; + wire [0:7] ex2_div_ctr_q; + wire ex2_div_val_q; + wire ex2_div_sign_q; + wire ex2_div_size_q; + wire ex2_div_extd_q; + wire ex2_div_recform_q; + wire ex2_xer_ov_update_q; + wire ex3_div_val_q; + wire ex3_cycle_act_d; + wire ex3_cycle_act_q; + wire [0:7] ex3_cycles_d; + wire [0:7] ex3_cycles_q; + wire [msb:65] ex3_denom_d; + wire [msb:65] ex3_denom_q; + wire [msb:65] ex3_dmask_d; + wire [msb:65] ex3_dmask_q; + wire [msb:65] ex3_dmask_q2; + + wire ex3_div_ovf_q; + wire ex3_xer_ov_update_q; + wire ex3_div_recform_q; + wire ex3_div_size_q; + wire ex3_div_sign_q; + wire ex3_div_extd_q; + wire ex3_2s_rslt_q; + wire ex3_div_done_q; + wire ex4_div_val_q; + wire ex4_cycle_watch_d; + wire ex4_cycle_watch_q; + wire ex4_quot_watch_d; + wire ex4_quot_watch_q; + wire ex4_quot_watch_d_old; + wire ex4_div_ovf_d; + wire ex4_div_ovf_q; + wire ex4_xer_ov_update_q; + wire ex4_div_done_d; + wire ex4_div_done_q; + wire ex5_div_done_d; + wire ex5_div_done_q; + wire [msb:63] ex4_quotient_d; + wire [msb:63] ex4_quotient_q; + wire ex4_div_recform_q; + wire ex4_div_size_q; + wire ex4_2s_rslt_q; + wire [msb:63] ex4_div_rt_d; + wire [msb:63] ex4_div_rt_q; + wire ex3_numer_eq_zero_q; + wire ex3_numer_eq_zero_d; + wire ex3_div_ovf_cond3; + wire ex4_div_ovf_cond3_q; + wire ex2_spr_msr_cm_q; + wire [0:9] xersrc_q; + wire [0:`THREADS-1] cp_flush_q; //input=>cp_flush + wire [0:`THREADS-1] ex2_div_tid_q; //input=>ex1_div_tid + wire [0:`THREADS-1] ex1_div_tid; + wire [0:`THREADS-1] ex3_div_tid_q; //input=>ex2_div_tid_q + wire ex2_cycles_sel0; + wire ex2_cycles_sel1; + wire ex2_cycles_sel2; + wire ex3_oddshift_d; + wire ex3_oddshift_q; + wire ex3_oddshift; + wire ex3_oddshift_set; + wire ex3_oddshift_done; + wire ex2_div_cnt_done; + wire ex2_div_cnt_almost_done; + wire ex2_div_almost_done; + wire ex3_denom_shift_ctrl; + wire ex3_denom_shift_ctrl0; + wire ex3_denom_shift_ctrl1; + wire ex3_denom_shift_ctrl2; + wire ex3_dmask_shift_ctrl0; + wire ex3_dmask_shift_ctrl1; + wire ex3_dmask_shift_ctrl2; + wire ex3_divrunning_d; + wire ex3_divrunning_q; + wire ex3_divrunning; + wire ex3_divrunning_set; + wire ex4_divrunning_act_d; + wire ex4_divrunning_act_q; + wire divrunning_act; + wire ex4_divrunning_act_set; + + wire [msb:66] ex3_lev0_csaout_sum; + wire [msb:66] ex3_lev0_csaout_carry; + wire [msb:66] ex3_lev0_csaoutsh_sum; + wire [msb:66] ex3_lev0_csaoutsh_carry; + + wire [msb:66] ex3_lev0_csaout_carryout; + wire [msb:66] ex3_lev0_csaout_carryout_oddshift; + wire [msb:66] ex3_lev1_csaout_sum; + wire [msb:66] ex3_lev1_csaout_carry; + wire [msb:66] ex3_lev2_csaout_sum; + wire [msb:66] ex3_lev2_csaout_carry; + wire [msb:66] ex3_lev3_csaout_sum; + wire [msb:66] ex3_lev3_csaout_carry; + wire [msb:66] ex3_lev1_csaout_carryout; + wire [msb:66] ex3_lev2_csaout_carryout; + wire [msb:66] ex3_lev3_csaout_carryout; + wire [msb:66] ex3_lev22_csaout_carryout; + wire [msb:66] ex3_lev22_csaout_sum; + wire [msb:66] ex3_lev22_csaout_carry; + + wire [msb:66] ex3_numer_d; + wire [msb:66] ex3_numer_q; + wire [msb:66] ex3_PR_sum_d; + wire [msb:66] ex3_PR_sum_q; + wire [msb:66] ex3_PR_carry_d; + wire [msb:66] ex3_PR_carry_q; + wire [msb:66] ex3_PR_sum_shift; + wire [msb:66] ex3_PR_sum_final; + wire [msb:66] ex3_PR_carry_shift; + wire [msb:66] ex3_PR_carry_final; + wire [msb:66] ex3_PR_sum_q_shifted; + wire [msb:66] ex3_PR_carry_q_shifted; + wire ex3_quotient_ovf_cond4; + wire ex3_quotient_ovf_cond4_wd; + wire ex3_quotient_ovf_cond4_dw; + + wire ex3_PR_shiftctrl1; + wire ex3_PR_shiftctrl2; + wire ex3_PR_shiftctrl3; + wire ex3_q_bit0; + wire ex3_q_bit0_cin; + wire ex3_q_bit1; + wire ex3_q_bit1_cin; + wire ex3_q_bit2; + wire ex3_q_bit2_cin; + wire ex3_q_bit3; + wire ex3_q_bit3_cin; + wire [0:1] ex3_q_bit22_sel; + wire ex3_nq_bit0; + wire ex3_nq_bit1; + wire ex3_nq_bit2; + wire ex3_nq_bit3; + wire ex3_q_bit22; + wire ex3_nq_bit22; + wire [msb:63] ex4_div_rt; + wire [msb:63] ex3_Qin_lev0; + wire [msb:63] ex3_QMin_lev0; + wire [msb:63] ex3_Qin_lev1; + wire [msb:63] ex3_QMin_lev1; + wire ex3_Qin_lev0_sel0; + wire ex3_Qin_lev0_sel1; + wire ex3_QMin_lev0_sel0; + wire ex3_QMin_lev0_sel1; + wire ex3_QMin_lev0_sel2; + wire ex3_Qin_lev1_sel0; + wire ex3_Qin_lev1_sel1; + wire ex3_Qin_lev1_sel2; + wire ex3_Qin_lev1_selinit; + wire ex3_QMin_lev1_sel0; + wire ex3_QMin_lev1_sel1; + wire ex3_QMin_lev1_sel2; + wire ex3_QMin_lev1_selinit; + wire [0:3] ex3_sum4; + wire [0:3] ex3_sum4addres; + wire [0:3] ex3_sum4_lev1; + wire [0:3] ex3_sum4_lev2; + wire [0:3] ex3_sum4_lev3; + wire ex3_lev0_selD; + wire ex3_lev0_selnD; + wire ex3_lev0_sel0; + wire ex3_lev22_selD; + wire ex3_lev22_selnD; + wire ex3_lev22_sel0; + wire [msb:65] ex3_denomQ_lev0; + wire [msb:65] ex3_denomQ_lev22; + wire ex3_Q_sel0; + wire ex3_Q_sel1; + wire ex3_Q_sel2; + wire [msb:63] ex3_Q_q; + wire [msb:63] ex3_Q_d; + wire [msb:63] ex3_QM_q; + wire [msb:63] ex3_QM_d; + wire [msb:66] ex3_add_rslt; + wire ex3_add_rslt_sign_d; + wire ex3_add_rslt_sign_q; + wire ex3_quotient_correction; + wire ex4_quotient_correction; + wire [msb:63] ex4_div_rt_op1; + wire [msb:63] ex4_div_rt_op2; + wire ex4_addop_sel0; + wire ex4_addop_sel1; + wire ex4_addop_sel2; + wire ex4_addop_sel3; + + (* analysis_not_referenced="true" *) + wire unused; + + // Scanchains + localparam ex2_div_ctr_offset = 0; + localparam ex2_div_val_offset = ex2_div_ctr_offset + 8; + localparam ex2_div_sign_offset = ex2_div_val_offset + 1; + localparam ex2_div_size_offset = ex2_div_sign_offset + 1; + localparam ex2_div_extd_offset = ex2_div_size_offset + 1; + localparam ex2_div_recform_offset = ex2_div_extd_offset + 1; + localparam ex2_xer_ov_update_offset = ex2_div_recform_offset + 1; + localparam ex3_div_val_offset = ex2_xer_ov_update_offset + 1; + localparam ex3_cycle_act_offset = ex3_div_val_offset + 1; + localparam ex3_cycles_offset = ex3_cycle_act_offset + 1; + localparam ex3_denom_offset = ex3_cycles_offset + 8; + localparam ex3_numer_offset = ex3_denom_offset + (65-msb+1); + + localparam ex3_PR_sum_offset = ex3_numer_offset + (66-msb+1); + localparam ex3_PR_carry_offset = ex3_PR_sum_offset + (66-msb+1); + localparam ex3_Q_offset = ex3_PR_carry_offset + (66-msb+1); + localparam ex3_QM_offset = ex3_Q_offset + (63-msb+1); + localparam ex3_oddshift_offset = ex3_QM_offset + (63-msb+1); + localparam ex3_divrunning_offset = ex3_oddshift_offset + 1; + localparam ex4_divrunning_act_offset = ex3_divrunning_offset + 1; + localparam ex3_divflush_1d_offset = ex4_divrunning_act_offset + 1; + localparam ex4_divflush_2d_offset = ex3_divflush_1d_offset + 1; + + localparam ex3_add_rslt_sign_offset = ex4_divflush_2d_offset + 1; + localparam ex4_quotient_correction_offset = ex3_add_rslt_sign_offset + 1; + localparam ex3_dmask_offset = ex4_quotient_correction_offset + 1; + + localparam ex3_div_ovf_offset = ex3_dmask_offset + (65-msb+1); + localparam ex3_xer_ov_update_offset = ex3_div_ovf_offset + 1; + localparam ex3_div_recform_offset = ex3_xer_ov_update_offset + 1; + localparam ex3_div_size_offset = ex3_div_recform_offset + 1; + localparam ex3_div_sign_offset = ex3_div_size_offset + 1; + localparam ex3_div_extd_offset = ex3_div_sign_offset + 1; + localparam ex3_2s_rslt_offset = ex3_div_extd_offset + 1; + localparam ex3_div_done_offset = ex3_2s_rslt_offset + 1; + localparam ex4_div_val_offset = ex3_div_done_offset + 1; + localparam ex4_cycle_watch_offset = ex4_div_val_offset + 1; + localparam ex4_quot_watch_offset = ex4_cycle_watch_offset + 1; + localparam ex4_div_ovf_offset = ex4_quot_watch_offset + 1; + localparam ex4_xer_ov_update_offset = ex4_div_ovf_offset + 1; + localparam ex4_div_done_offset = ex4_xer_ov_update_offset + 1; + localparam ex5_div_done_offset = ex4_div_done_offset + 1; + localparam ex4_quotient_offset = ex5_div_done_offset + 1; + localparam ex4_div_recform_offset = ex4_quotient_offset + (63-msb+1); + localparam ex4_div_size_offset = ex4_div_recform_offset + 1; + localparam ex4_2s_rslt_offset = ex4_div_size_offset + 1; + localparam ex4_div_rt_offset = ex4_2s_rslt_offset + 1; + localparam ex3_numer_eq_zero_offset = ex4_div_rt_offset + (63-msb+1); + localparam ex4_div_ovf_cond3_offset = ex3_numer_eq_zero_offset + 1; + localparam ex2_spr_msr_cm_offset = ex4_div_ovf_cond3_offset + 1; + localparam xersrc_offset = ex2_spr_msr_cm_offset + 1; + localparam cp_flush_offset = xersrc_offset + 10; + localparam ex2_div_tid_offset = cp_flush_offset + `THREADS; + localparam ex3_div_tid_offset = ex2_div_tid_offset + `THREADS; + localparam perf_divrunning_offset = ex3_div_tid_offset + `THREADS; + localparam scan_right = perf_divrunning_offset + `THREADS; + + wire [0:scan_right-1] sov; + wire [0:scan_right-1] siv; + // Signals + wire [msb:65] ex3_denom_norm; + + wire [msb:63] ex2_denom; + wire [msb:63] ex2_numer; + wire [msb:65] mask; + wire [msb:66] ex3_sub_rslt; + wire ex2_div_done; + wire ex2_num_cmp0_lo_nomsb; + wire ex2_num_cmp0_hi_nomsb; + wire ex2_num_cmp0_lo; + wire ex2_num_cmp0_hi; + wire ex2_den_cmp0_lo; + wire ex2_den_cmp0_hi; + wire ex2_den_cmp1_lo; + wire ex2_den_cmp1_hi; + wire ex4_qot_cmp0_lo; + wire ex4_qot_cmp0_hi; + wire ex2_div_ovf_cond1_wd; + wire ex2_div_ovf_cond1_dw; + wire ex2_div_ovf_cond1; + wire ex2_div_ovf_cond2; + wire ex3_div_ovf_cond4; + wire ex3_rslt_sign; + wire ex3_den_eq_num; + wire ex3_den_gte_num; + wire ex2_div_ovf; + wire [msb:63] ex2_divsrc_0; + wire [msb:63] ex2_divsrc_0_2s; + wire [msb:63] ex2_divsrc_1; + wire [msb:63] ex2_divsrc_1_2s; + wire ex2_2s_rslt; + wire ex2_src0_sign; + wire ex2_src1_sign; + + wire ex4_cmp0_undef; + wire ex4_cmp0_eq; + wire ex4_cmp0_gt; + wire ex4_cmp0_lt; + wire [msb:63] ex4_quotient_2s; + wire [0:7] ex3_cycles_din; + wire ex3_cycles_gt_64; + wire ex3_cycles_gt_32; + wire ex4_lt; + wire [msb:65] ex3_denom_rot; + wire [msb:65] ex3_denom_rot2; + wire ex1_div_val; + wire ex1_div_v; + wire ex2_div_val; + wire div_flush; + wire div_flush_1d; + wire div_flush_2d; + wire tiup; + wire tidn; + + //-------------------------------------------------------------- + //!! Bugspray Include: xu0_div_r4; + + + + + // def divide(num,den,size): + // q = 0 + // m = pow(2,size)-1 + // cycle = size+1 + // + // # Normalize + // p = m + // + // while cycle>0: + // r = den & p + // if r == 0: + // break + // den = rotR1(den,size) + // p = p>>1 + // cycle -= 1 + // + // den = ((~den + 1) & m) | 2**size + // size = size + 1 + // m = pow(2,size)-1 + // + // # Divide + // while cycle>0: + // # Subtract + // a = (num+den) & m + // if signbit(a,size)==0: # Positive + // q = rotL1(q,size,m) | 1 # 0b...x | 0b0001 = 0b...1 + // num = rotL1(a,size,m) + // else: + // q = rotL1(q,size,m) & -2 # 0b...x & 0b1110 = 0b...0 + // num = rotL1(num,size,m) + // cycle -= 1 + // return q + + assign tiup = 1'b1; + assign tidn = 1'b0; + //------------------------------------------------------------------- + // Summary example, divd + //------------------------------------------------------------------- + // ex2_cycles_din=33 ex1_div_val=1 + // ex2_cycles_din=32 ex2_denom_q contains the unnormalized denominator + // and ex2_denom_shift_ctrl* indicates if it will need to be rotated + // + // when the denominator is finished shifting, ex2_denom_shift_ctrl=0 and + // quotient bits will start showing up in ex2_Qin_lev1 + // if the denominator needed to be shifted by an odd amount, ex2_cycles_din will be held + // for an extra cycle. The last cycle it will be repeated is when ex2_denom_shift_ctrl1=1 + // + // + // + // ex2_cycles_din=33 (first cycle that ex2_denom_shift_ctrl is on?) + // + // ex2_cycles_din=1 ex1_div_almost_done=1. this is the last cycle that the algorithm can be working in + // ex2_Q_d contains the quotient before correction for 2's comp and off-by-one. + // ex2_PR_sum_q should contain the intermediate sum or the original numerator + // in this cycle (such as in the case of a long denom rotate) + // also denominator rotation should be finished, and ex2_denom_q must contain the normalized denominator + // + // ex2_cycles_din=0 the final remainder is summed in this cycle to determine if a quotient correction + // is needed. ex3_quotient_d contains the intermediate result + // ex2_quotient_correction is the result of the remainder sum + // + // ex2_cycles_din=0-1 (one cycle after) ex3_div_rt_d is the result of the quotient corrected/2's comp result. + // ex3_div_rt_op2 contains the correction value + // ex3_quotient_q contains the unadjusted quotient (not 2's comp yet, not quotient corrected) + // + // ex2_cycles_din=0-2 (two cycles after) ex3_div_rt contains the result, and ex3_div_done_q=1 + // ex3_div_rt_q contains the result before overflow gating + // + + //------------------------------------------------------------------- + // unused + //------------------------------------------------------------------- + assign unused = |( {ex3_lev0_sel0, + ex3_lev0_csaout_carryout[0], + ex3_lev0_csaout_carryout_oddshift, + ex3_lev1_csaout_sum[4], + ex3_lev1_csaout_sum[6:66], + ex3_lev1_csaout_carryout[0], + ex3_lev1_csaout_carry[4], + ex3_lev1_csaout_carry[6:66], + ex3_lev2_csaout_sum[4], + ex3_lev2_csaout_sum[6:66], + ex3_lev2_csaout_carryout[0], + ex3_lev2_csaout_carry[4], + ex3_lev2_csaout_carry[6:66], + ex3_lev3_csaout_sum[4], + ex3_lev3_csaout_sum[6:66], + ex3_lev3_csaout_carryout[0], + ex3_lev3_csaout_carry[4], + ex3_lev3_csaout_carry[6:66], + ex3_lev22_sel0, + ex3_lev22_csaout_carryout[0], + ex3_add_rslt[1:66], + ex3_sub_rslt[1:66], + ex4_quot_watch_d_old, + div_flush_2d, + ex3_add_rslt_sign_q, + ex4_div_recform_q, + ex3_div_tid_q + }); + + //------------------------------------------------------------------- + // Initialize cycle counter + //------------------------------------------------------------------- + assign ex1_div_val = |(dec_div_ex1_div_val & (~cp_flush)); + assign ex1_div_v = |(dec_div_ex1_div_val); + + assign ex1_div_tid = dec_div_ex1_div_val; + + assign ex2_div_val = ex2_div_val_q & (~div_flush); + + // ATW div_flush was originally using ex3_div_tid, which is not upated early enough. + // Some signal used were ex2 stage, so div_tid was not yet updated + // Changed to use EX2 signal, and clock gated ex2_div_tid_q latch + assign div_flush = |(ex2_div_tid_q & cp_flush_q); + + assign ex2_cycles_sel0 = ex2_div_val; + assign ex2_cycles_sel1 = (ex3_oddshift_set | ((ex2_div_cnt_almost_done) & ex3_denom_shift_ctrl)) & (~ex2_div_val); + assign ex2_cycles_sel2 = (~(ex3_oddshift_set | ((ex2_div_cnt_almost_done) & ex3_denom_shift_ctrl))) & (~ex2_div_val); + + // init + assign ex3_cycles_din = (ex2_div_ctr_q & {8{ex2_cycles_sel0}}) | + (ex3_cycles_q & {8{ex2_cycles_sel1}}) | + ((ex3_cycles_q - 8'b00000001) & {8{ex2_cycles_sel2}}); // hold for odd cases + // decrement + + // Clear counter if the divide was flushed + assign ex3_cycles_d = div_flush==1'b0 ? ex3_cycles_din : 8'b0; + + assign ex3_cycle_act_d = ex2_div_val | (ex3_cycle_act_q & ~ex3_div_done_q & |ex3_cycles_q); + + assign ex2_div_cnt_done = (ex3_cycles_q == 8'b00000001) ? 1'b1 : 1'b0; + assign ex2_div_cnt_almost_done = (ex3_cycles_q == 8'b00000010) ? 1'b1 : 1'b0; + + assign ex2_div_done = ex2_div_cnt_done & (~ex3_denom_shift_ctrl1) & (~div_flush); + assign ex2_div_almost_done = ex2_div_cnt_almost_done & (~ex3_denom_shift_ctrl1) & (~div_flush); + + assign ex4_div_done_d = ex3_div_done_q & (~div_flush); + + assign div_byp_ex4_done = ex4_div_done_q; + + assign ex5_div_done_d = ex4_div_done_q; + + //------------------------------------------------------------------- + // 2's complement negative operands for signed divide + //------------------------------------------------------------------- + assign ex2_divsrc_0_2s = (~byp_div_ex2_rs1) + 1; + assign ex2_divsrc_1_2s = (~byp_div_ex2_rs2) + 1; + + // Need to 2's complement the result if one of the operands is negative + generate + if (`GPR_WIDTH == 64) + begin : div_64b_2scomp + + assign ex2_2s_rslt = (ex2_div_size_q == 1'b1) ? (byp_div_ex2_rs1[0] ^ byp_div_ex2_rs2[0]) & ex2_div_sign_q : + (byp_div_ex2_rs1[32] ^ byp_div_ex2_rs2[32]) & ex2_div_sign_q; + + assign ex2_src0_sign = (ex2_div_size_q == 1'b1) ? byp_div_ex2_rs1[0] : + byp_div_ex2_rs1[32]; + assign ex2_src1_sign = (ex2_div_size_q == 1'b1) ? byp_div_ex2_rs2[0] : + byp_div_ex2_rs2[32]; + end + endgenerate + generate + if (`GPR_WIDTH == 32) + begin : div_32b_2scomp + assign ex2_2s_rslt = (byp_div_ex2_rs1[32] ^ byp_div_ex2_rs2[32]) & ex2_div_sign_q; + assign ex2_src0_sign = byp_div_ex2_rs1[32]; + assign ex2_src1_sign = byp_div_ex2_rs2[32]; + end + endgenerate + + assign ex2_divsrc_0 = ((ex2_div_sign_q & ex2_src0_sign) == 1'b1) ? ex2_divsrc_0_2s : + byp_div_ex2_rs1; + + //------------------------------------------------------------------- + // Fixup Operands for Word/DW Mode + //------------------------------------------------------------------- + assign ex2_divsrc_1 = ((ex2_div_sign_q & ex2_src1_sign) == 1'b1) ? ex2_divsrc_1_2s : + byp_div_ex2_rs2; + + generate + if (`GPR_WIDTH == 64) + begin : div_setup_64b + + assign ex2_denom[0:31] = (ex2_div_size_q == 1'b1) ? ex2_divsrc_1[0:31] : ex2_divsrc_1[32:63]; + assign ex2_denom[32:63] = (ex2_div_size_q == 1'b1) ? ex2_divsrc_1[32:63] : 32'b0; + + assign ex2_numer[0:31] = (ex2_div_size_q == 1'b1) ? ex2_divsrc_0[0:31] : ex2_divsrc_0[32:63]; + assign ex2_numer[32:63] = (ex2_div_size_q == 1'b1) ? ex2_divsrc_0[32:63] : 32'b0; + + assign mask = {{34{1'b1}}, {32{ex2_div_size_q}}}; + + // Rotate just the upper 32 for word mode + + assign ex3_denom_rot[0] = (ex2_div_size_q == 1'b1) ? ex3_denom_q[65] : ex3_denom_q[33]; + assign ex3_denom_rot[1:33] = ex3_denom_q[msb:32]; + assign ex3_denom_rot[34:65] = (ex3_div_size_q == 1'b1) ? ex3_denom_q[33:64] : 32'b0; + + assign ex3_denom_rot2[0] = (ex2_div_size_q == 1'b1) ? ex3_denom_q[64] : ex3_denom_q[32]; + + assign ex3_denom_rot2[1] = (ex2_div_size_q == 1'b1) ? ex3_denom_q[65] : ex3_denom_q[33]; + assign ex3_denom_rot2[2:33] = ex3_denom_q[msb:31]; + assign ex3_denom_rot2[34:65]= (ex3_div_size_q == 1'b1) ? ex3_denom_q[32:63] : 32'b0; + end + endgenerate + + generate + if (`GPR_WIDTH == 32) + begin : div_setup_32b + assign ex2_denom = ex2_divsrc_1; + assign ex2_numer = ex2_divsrc_0; + + assign mask = {65-msb{1'b1}}; + + assign ex3_denom_rot = {ex3_denom_q[65], ex3_denom_q[msb:64]}; + assign ex3_denom_rot2 = {ex3_denom_q[64], ex3_denom_q[65], ex3_denom_q[msb:63]}; + end + endgenerate + + //------------------------------------------------------------------- + // Normalize Denominator + //------------------------------------------------------------------- + // Grab denominator from bypass, shift until normalized, then hold. + + // Mask + + assign ex3_dmask_shift_ctrl0 = ex2_div_val_q; + assign ex3_dmask_shift_ctrl1 = ex3_denom_shift_ctrl1 & (~ex2_div_val_q); + assign ex3_dmask_shift_ctrl2 = ex3_denom_shift_ctrl2 & (~ex2_div_val_q); + + assign ex3_dmask_d = (mask & {66-msb{ex3_dmask_shift_ctrl0}}) | + ({1'b0, ex3_dmask_q[msb:64]} & {66-msb{ex3_dmask_shift_ctrl1}}) | + ({2'b00, ex3_dmask_q[msb:63]} & {66-msb{ex3_dmask_shift_ctrl2}}); + + assign ex3_dmask_q2 = (({ex3_dmask_q[msb:64], 1'b0}) & {66-msb{ ex2_div_size_q}}) | + (({ex3_dmask_q[msb:32], 1'b0, 32'd0}) & {66-msb{(~ex2_div_size_q)}}); // still can shift one more + + assign ex3_denom_shift_ctrl = ex3_denom_shift_ctrl1 | ex3_denom_shift_ctrl2; + assign ex3_denom_shift_ctrl0 = (~ex3_denom_shift_ctrl); + assign ex3_denom_shift_ctrl1 = ((ex3_denom_q[65] & ex3_dmask_q[65] & ex2_div_size_q) | (ex3_denom_q[33] & ex3_dmask_q[33] & (~ex2_div_size_q))) & (~ex3_denom_shift_ctrl2); + assign ex3_denom_shift_ctrl2 = |(ex3_denom_q & ex3_dmask_q2); + + // don't shift + assign ex3_denom_norm = (ex3_denom_q & {66-msb{ex3_denom_shift_ctrl0}}) | + (ex3_denom_rot & {66-msb{ex3_denom_shift_ctrl1}}) | + (ex3_denom_rot2 & {66-msb{ex3_denom_shift_ctrl2}}); // rotate 1 right + // rotate 2 right + + assign ex3_denom_d = (ex2_div_val_q == 1'b1) ? {2'b00, ex2_denom} : + ex3_denom_norm; + assign ex3_oddshift_set = ex3_denom_shift_ctrl1 & ex3_divrunning; + assign ex3_oddshift_d = (ex3_oddshift_set | ex3_oddshift_q) & (~(ex4_div_done_q | div_flush)); + assign ex3_oddshift = ex3_oddshift_q; + + assign ex3_divrunning_set = ex2_div_val_q; + assign ex3_divrunning_d = (ex3_divrunning_set | ex3_divrunning_q) & (~(ex3_div_done_q | div_flush)); + assign ex3_divrunning = ex3_divrunning_q; + + assign perf_divrunning_d = dec_div_ex1_div_val | (perf_divrunning_q & ~({`THREADS{ex2_div_done}} | cp_flush_q)); + + assign div_spr_running = perf_divrunning_q; + + assign ex4_divrunning_act_set = ex1_div_v; + assign ex4_divrunning_act_d = ex4_divrunning_act_set | (ex4_divrunning_act_q & (~ex5_div_done_q)); + assign divrunning_act = ex4_divrunning_act_q; + + //------------------------------------------------------------------- + // Load the numerator upon init, or shift by 1 if odd, 2 if even + //------------------------------------------------------------------- + + assign ex3_PR_sum_d = (ex2_div_val_q == 1'b1) ? {3'b000, ex2_numer} : // hold if the denom is being normalized + ex3_PR_sum_shift; + assign ex3_PR_shiftctrl1 = ex3_denom_shift_ctrl; + assign ex3_PR_shiftctrl2 = (~(ex3_oddshift_done)) & (~ex3_denom_shift_ctrl); + assign ex3_PR_shiftctrl3 = ex3_oddshift_done & (~ex3_denom_shift_ctrl); + + // oddshift + assign ex3_PR_sum_shift = (ex3_lev0_csaoutsh_sum[msb:66] & {67-msb{ex3_PR_shiftctrl3}}) | + (ex3_PR_sum_final[msb:66] & {67-msb{ex3_PR_shiftctrl2}}) | + (ex3_PR_sum_q[msb:66] & {67-msb{ex3_PR_shiftctrl1}}); // dividing + // hold if normalizing + + assign ex3_PR_carry_d = (ex2_div_val_q == 1'b1) ? {67-msb{1'b0}} : // oddshift + ex3_PR_carry_shift; + assign ex3_PR_carry_shift = (ex3_lev0_csaoutsh_carry[msb:66] & {67-msb{ex3_PR_shiftctrl3}}) | + (ex3_PR_carry_final[msb:66] & {67-msb{ex3_PR_shiftctrl2}}) | + (ex3_PR_carry_q[msb:66] & {67-msb{ex3_PR_shiftctrl1}}); // hold if normalizing + + //------------------------------------------------------------------- + // Initial 4-bit add and quotient select + //------------------------------------------------------------------- + + assign ex3_sum4addres = ex3_PR_sum_q[msb + 0:msb + 3] + ex3_PR_carry_q[msb + 0:msb + 3]; + + assign ex3_sum4 = ex3_sum4addres; + + assign ex3_q_bit0_cin = ex3_PR_sum_q[msb + 5] | ex3_PR_carry_q[msb + 5]; + + assign ex3_q_bit0 = (ex3_sum4 == 4'b0000) ? ex3_q_bit0_cin : + (ex3_sum4 == 4'b0001) ? 1'b1 : + (ex3_sum4 == 4'b0010) ? 1'b1 : + (ex3_sum4 == 4'b0011) ? 1'b1 : + (ex3_sum4 == 4'b0100) ? 1'b1 : + (ex3_sum4 == 4'b0101) ? 1'b1 : + (ex3_sum4 == 4'b0110) ? 1'b1 : + (ex3_sum4 == 4'b0111) ? 1'b1 : + 1'b0; + + //------------------------------------------------------------------- + // on-the-fly quotient digit conversion logic for level 0 + //------------------------------------------------------------------- + // Qin=(Q & q) if q >= 0. Qin=(QM & 1) if q < 0 + + assign ex3_nq_bit0 = (ex3_sum4 == 4'b1000) ? 1'b1 : + (ex3_sum4 == 4'b1001) ? 1'b1 : + (ex3_sum4 == 4'b1010) ? 1'b1 : + (ex3_sum4 == 4'b1011) ? 1'b1 : + (ex3_sum4 == 4'b1100) ? 1'b1 : + (ex3_sum4 == 4'b1101) ? 1'b1 : + (ex3_sum4 == 4'b1110) ? 1'b1 : + 1'b0; + assign ex3_Qin_lev0_sel0 = ex3_q_bit0 | ((~ex3_nq_bit0)); + assign ex3_Qin_lev0_sel1 = ex3_nq_bit0; + + assign ex3_Qin_lev0[msb:63] = (({ex3_Q_q[msb + 1:63], ex3_q_bit0}) & {`GPR_WIDTH{ex3_Qin_lev0_sel0}}) | (({ex3_QM_q[msb + 1:63], 1'b1}) & {`GPR_WIDTH{ex3_Qin_lev0_sel1}}); + + // QMin=(Q & 0) if q > 0. QMin=(QM & 0) if q < 0. QMin=(QM & 1) if q = 0 + assign ex3_QMin_lev0_sel0 = ex3_q_bit0; + assign ex3_QMin_lev0_sel1 = ex3_nq_bit0; + assign ex3_QMin_lev0_sel2 = (~(ex3_nq_bit0 | ex3_q_bit0)); + + assign ex3_QMin_lev0[msb:63] = (({ex3_Q_q[msb + 1:63], 1'b0}) & {`GPR_WIDTH{ex3_QMin_lev0_sel0}}) | + (({ex3_QM_q[msb + 1:63], 1'b0}) & {`GPR_WIDTH{ex3_QMin_lev0_sel1}}) | + (({ex3_QM_q[msb + 1:63], 1'b1}) & {`GPR_WIDTH{ex3_QMin_lev0_sel2}}); + + //------------------------------------------------------------------- + // Initial Denominator mux and 3:2 CSA + //------------------------------------------------------------------- + + assign ex3_PR_sum_q_shifted = {ex3_PR_sum_q[msb + 1:66], 1'b0}; + assign ex3_PR_carry_q_shifted = {ex3_PR_carry_q[msb + 1:66], 1'b0}; + + assign ex3_lev0_selD = ex3_nq_bit0 & (~ex3_q_bit0); + assign ex3_lev0_selnD = ex3_q_bit0 & (~ex3_nq_bit0); + assign ex3_lev0_sel0 = (~ex3_q_bit0) & (~ex3_nq_bit0); + + assign ex3_denomQ_lev0 = ((~ex3_denom_q) & {66-msb{ex3_lev0_selnD}}) | (ex3_denom_q & {66-msb{ex3_lev0_selD}}); + + assign ex3_lev0_csaoutsh_sum = {ex3_lev0_selnD, ex3_denomQ_lev0} ^ ex3_PR_sum_q_shifted ^ ex3_PR_carry_q_shifted; + + assign ex3_lev0_csaout_carryout = (({ex3_lev0_selnD, ex3_denomQ_lev0}) & ex3_PR_sum_q_shifted) | (({ex3_lev0_selnD, ex3_denomQ_lev0}) & ex3_PR_carry_q_shifted) | (ex3_PR_sum_q_shifted & ex3_PR_carry_q_shifted); + + assign ex3_lev0_csaout_carryout_oddshift = (({ex3_lev0_selnD, ex3_denomQ_lev0}) & ex3_PR_sum_q) | (({ex3_lev0_selnD, ex3_denomQ_lev0}) & ex3_PR_carry_q) | (ex3_PR_sum_q & ex3_PR_carry_q); + + assign ex3_lev0_csaoutsh_carry[msb:66] = {ex3_lev0_csaout_carryout[msb + 1:66], ex3_lev0_selnD}; + + // todo above: the selnD tacked on at the end needs to go into the middle for the word case? + + //------------------------------------------------------------------- + // Pick -d, 0, +d + //------------------------------------------------------------------- + // neg d, +q ======================================================== + assign ex3_lev1_csaout_sum = ({1'b1, (~ex3_denom_q)}) ^ ex3_PR_sum_q_shifted ^ ex3_PR_carry_q_shifted; + + assign ex3_lev1_csaout_carryout = (({1'b1, (~ex3_denom_q)}) & ex3_PR_sum_q_shifted) | (({1'b1, (~ex3_denom_q)}) & ex3_PR_carry_q_shifted) | (ex3_PR_sum_q_shifted & ex3_PR_carry_q_shifted); + + assign ex3_lev1_csaout_carry[msb:66] = {ex3_lev1_csaout_carryout[msb + 1:66], 1'b1}; + + assign ex3_sum4_lev1 = ex3_lev1_csaout_sum[msb + 0:msb + 3] + ex3_lev1_csaout_carry[msb + 0:msb + 3]; + + assign ex3_q_bit1_cin = ex3_lev1_csaout_sum[msb + 5] | ex3_lev1_csaout_carry[msb + 5]; + + assign ex3_q_bit1 = (ex3_sum4_lev1 == 4'b0000) ? ex3_q_bit1_cin : + (ex3_sum4_lev1 == 4'b0001) ? 1'b1 : + (ex3_sum4_lev1 == 4'b0010) ? 1'b1 : + (ex3_sum4_lev1 == 4'b0011) ? 1'b1 : + (ex3_sum4_lev1 == 4'b0100) ? 1'b1 : + (ex3_sum4_lev1 == 4'b0101) ? 1'b1 : + (ex3_sum4_lev1 == 4'b0110) ? 1'b1 : + (ex3_sum4_lev1 == 4'b0111) ? 1'b1 : + 1'b0; + + // zero =========================================================== + assign ex3_nq_bit1 = (ex3_sum4_lev1 == 4'b1000) ? 1'b1 : + (ex3_sum4_lev1 == 4'b1001) ? 1'b1 : + (ex3_sum4_lev1 == 4'b1010) ? 1'b1 : + (ex3_sum4_lev1 == 4'b1011) ? 1'b1 : + (ex3_sum4_lev1 == 4'b1100) ? 1'b1 : + (ex3_sum4_lev1 == 4'b1101) ? 1'b1 : + (ex3_sum4_lev1 == 4'b1110) ? 1'b1 : + 1'b0; + assign ex3_lev2_csaout_sum = ex3_PR_sum_q_shifted ^ ex3_PR_carry_q_shifted; + + assign ex3_lev2_csaout_carryout = (ex3_PR_sum_q_shifted & ex3_PR_carry_q_shifted); + + assign ex3_lev2_csaout_carry[msb:66] = {ex3_lev2_csaout_carryout[msb + 1:66], 1'b0}; + + assign ex3_sum4_lev2 = ex3_lev2_csaout_sum[msb + 0:msb + 3] + ex3_lev2_csaout_carry[msb + 0:msb + 3]; + + assign ex3_q_bit2_cin = ex3_lev2_csaout_sum[msb + 5] | ex3_lev2_csaout_carry[msb + 5]; + + assign ex3_q_bit2 = (ex3_sum4_lev2 == 4'b0000) ? ex3_q_bit2_cin : + (ex3_sum4_lev2 == 4'b0001) ? 1'b1 : + (ex3_sum4_lev2 == 4'b0010) ? 1'b1 : + (ex3_sum4_lev2 == 4'b0011) ? 1'b1 : + (ex3_sum4_lev2 == 4'b0100) ? 1'b1 : + (ex3_sum4_lev2 == 4'b0101) ? 1'b1 : + (ex3_sum4_lev2 == 4'b0110) ? 1'b1 : + (ex3_sum4_lev2 == 4'b0111) ? 1'b1 : + 1'b0; + + // pos d, -q ======================================================= + assign ex3_nq_bit2 = (ex3_sum4_lev2 == 4'b1000) ? 1'b1 : + (ex3_sum4_lev2 == 4'b1001) ? 1'b1 : + (ex3_sum4_lev2 == 4'b1010) ? 1'b1 : + (ex3_sum4_lev2 == 4'b1011) ? 1'b1 : + (ex3_sum4_lev2 == 4'b1100) ? 1'b1 : + (ex3_sum4_lev2 == 4'b1101) ? 1'b1 : + (ex3_sum4_lev2 == 4'b1110) ? 1'b1 : + 1'b0; + assign ex3_lev3_csaout_sum = ({1'b0, ex3_denom_q}) ^ ex3_PR_sum_q_shifted ^ ex3_PR_carry_q_shifted; + + assign ex3_lev3_csaout_carryout = (({1'b0, ex3_denom_q}) & ex3_PR_sum_q_shifted) | (({1'b0, ex3_denom_q}) & ex3_PR_carry_q_shifted) | (ex3_PR_sum_q_shifted & ex3_PR_carry_q_shifted); + + assign ex3_lev3_csaout_carry[msb:66] = {ex3_lev3_csaout_carryout[msb + 1:66], 1'b0}; + + assign ex3_sum4_lev3 = ex3_lev3_csaout_sum[msb + 0:msb + 3] + ex3_lev3_csaout_carry[msb + 0:msb + 3]; + + assign ex3_q_bit3_cin = ex3_lev3_csaout_sum[msb + 5] | ex3_lev3_csaout_carry[msb + 5]; + + assign ex3_q_bit3 = (ex3_sum4_lev3 == 4'b0000) ? ex3_q_bit3_cin : + (ex3_sum4_lev3 == 4'b0001) ? 1'b1 : + (ex3_sum4_lev3 == 4'b0010) ? 1'b1 : + (ex3_sum4_lev3 == 4'b0011) ? 1'b1 : + (ex3_sum4_lev3 == 4'b0100) ? 1'b1 : + (ex3_sum4_lev3 == 4'b0101) ? 1'b1 : + (ex3_sum4_lev3 == 4'b0110) ? 1'b1 : + (ex3_sum4_lev3 == 4'b0111) ? 1'b1 : + 1'b0; + + //------------------------------------------------------------------- + // Mux between these three to get the next quotient bit + //------------------------------------------------------------------- + assign ex3_nq_bit3 = (ex3_sum4_lev3 == 4'b1000) ? 1'b1 : + (ex3_sum4_lev3 == 4'b1001) ? 1'b1 : + (ex3_sum4_lev3 == 4'b1010) ? 1'b1 : + (ex3_sum4_lev3 == 4'b1011) ? 1'b1 : + (ex3_sum4_lev3 == 4'b1100) ? 1'b1 : + (ex3_sum4_lev3 == 4'b1101) ? 1'b1 : + (ex3_sum4_lev3 == 4'b1110) ? 1'b1 : + 1'b0; + assign ex3_q_bit22_sel = {ex3_q_bit0, ex3_nq_bit0}; + + assign ex3_q_bit22 = (ex3_q_bit22_sel == 2'b10) ? ex3_q_bit1 : + (ex3_q_bit22_sel == 2'b00) ? ex3_q_bit2 : + (ex3_q_bit22_sel == 2'b01) ? ex3_q_bit3 : + 1'b0; + + //------------------------------------------------------------------- + // Final Denominator mux and 3:2 CSA + //------------------------------------------------------------------- + // shift left by 1 again + assign ex3_nq_bit22 = (ex3_q_bit22_sel == 2'b10) ? ex3_nq_bit1 : + (ex3_q_bit22_sel == 2'b00) ? ex3_nq_bit2 : + (ex3_q_bit22_sel == 2'b01) ? ex3_nq_bit3 : + 1'b0; + assign ex3_lev0_csaout_sum[msb:66] = {ex3_lev0_csaoutsh_sum[msb + 1:66], 1'b0}; + assign ex3_lev0_csaout_carry[msb:66] = {ex3_lev0_csaoutsh_carry[msb + 1:66], 1'b0}; + + assign ex3_lev22_selD = ex3_nq_bit22 & (~ex3_q_bit22); + assign ex3_lev22_selnD = ex3_q_bit22 & (~ex3_nq_bit22); + assign ex3_lev22_sel0 = (~ex3_q_bit22) & (~ex3_nq_bit22); + + assign ex3_denomQ_lev22 = ((~ex3_denom_q) & {66-msb{ex3_lev22_selnD}}) | (ex3_denom_q & {66-msb{ex3_lev22_selD}}); + + assign ex3_lev22_csaout_sum = ({ex3_lev22_selnD, ex3_denomQ_lev22}) ^ ex3_lev0_csaout_sum ^ ex3_lev0_csaout_carry; + + assign ex3_lev22_csaout_carryout = (({ex3_lev22_selnD, ex3_denomQ_lev22}) & ex3_lev0_csaout_sum) | (({ex3_lev22_selnD, ex3_denomQ_lev22}) & ex3_lev0_csaout_carry) | (ex3_lev0_csaout_sum & ex3_lev0_csaout_carry); + + assign ex3_lev22_csaout_carry[msb:66] = {ex3_lev22_csaout_carryout[msb + 1:66], ex3_lev22_selnD}; + + assign ex3_PR_sum_final = ex3_lev22_csaout_sum; + assign ex3_PR_carry_final = ex3_lev22_csaout_carry; + + //------------------------------------------------------------------- + // on-the-fly quotient digit conversion logic + //------------------------------------------------------------------- + // Qin=(Q & q) if q >= 0. Qin=(QM & 1) if q < 0 + assign ex3_oddshift_done = ex3_oddshift & ex2_div_almost_done; + + assign ex3_Qin_lev1_sel0 = (ex3_q_bit22 | ((~ex3_nq_bit22))) & (~ex2_div_val_q) & (~(ex3_oddshift_done)); // todo: is there a better way to clear this? + assign ex3_Qin_lev1_sel1 = ex3_nq_bit22 & (~ex2_div_val_q) & (~(ex3_oddshift_done)); + assign ex3_Qin_lev1_sel2 = (ex3_oddshift_done) & (~ex2_div_val_q); + assign ex3_Qin_lev1_selinit = ex2_div_val_q; // initial state + + assign ex3_Qin_lev1[msb:63] = (({ex3_Qin_lev0[msb + 1:63], ex3_q_bit22}) & {`GPR_WIDTH{ex3_Qin_lev1_sel0}}) | (({ex3_QMin_lev0[msb + 1:63], 1'b1}) & {`GPR_WIDTH{ex3_Qin_lev1_sel1}}) | ((ex3_Qin_lev0[msb:63]) & {`GPR_WIDTH{ex3_Qin_lev1_sel2}}) | (`GPR_WIDTH'b0 & {`GPR_WIDTH{ex3_Qin_lev1_selinit}}); // just pass through for oddshifts + + assign ex3_quotient_ovf_cond4_wd = (ex3_Q_q[msb + 32] & ex3_Qin_lev0_sel0) | (ex3_QM_q[msb + 32] & ex3_Qin_lev0_sel1) | (ex3_Qin_lev0[msb + 32] & ex3_Qin_lev1_sel0) | (ex3_QMin_lev0[msb + 32] & ex3_Qin_lev1_sel1); // shifted out of lev0 + + // cond4 bug. dont know if overflow until the last cycle. + assign ex3_quotient_ovf_cond4_dw = (ex3_Q_q[msb] & ex3_Qin_lev0_sel0) | (ex3_QM_q[msb] & ex3_Qin_lev0_sel1) | (ex3_Qin_lev0[msb] & ex3_Qin_lev1_sel0) | (ex3_QMin_lev0[msb] & ex3_Qin_lev1_sel1); // shifted out of lev0 + // may also need to gate this with ex2_denom_shift_ctrl* + // may also need to undo for the quotient correction case + + // QMin=(Q & 0) if q > 0. QMin=(QM & 0) if q < 0. QMin=(QM & 1) if q = 0 + assign ex3_quotient_ovf_cond4 = (ex3_div_size_q == 1'b1) ? ex3_quotient_ovf_cond4_dw : + ex3_quotient_ovf_cond4_wd; + assign ex3_QMin_lev1_sel0 = ex3_q_bit22 & (~ex2_div_val_q); + assign ex3_QMin_lev1_sel1 = ex3_nq_bit22 & (~ex2_div_val_q); + assign ex3_QMin_lev1_sel2 = ((~(ex3_nq_bit22 | ex3_q_bit22))) & (~ex2_div_val_q); + assign ex3_QMin_lev1_selinit = ex2_div_val_q; + + assign ex3_QMin_lev1[msb:63] = (({ex3_Qin_lev0[msb + 1:63], 1'b0}) & {`GPR_WIDTH{ex3_QMin_lev1_sel0}}) | (({ex3_QMin_lev0[msb + 1:63], 1'b0}) & {`GPR_WIDTH{ex3_QMin_lev1_sel1}}) | (({ex3_QMin_lev0[msb + 1:63], 1'b1}) & {`GPR_WIDTH{ex3_QMin_lev1_sel2}}) | (`GPR_WIDTH'b0 & {`GPR_WIDTH{ex3_QMin_lev1_selinit}}); + + assign ex3_Q_d = (ex3_Qin_lev1 & {`GPR_WIDTH{ex3_denom_shift_ctrl0}}) | + ({`GPR_WIDTH{tidn}} & {`GPR_WIDTH{ex3_denom_shift_ctrl}}); + + assign ex3_QM_d = (ex3_QMin_lev1 & {64-msb{ex3_denom_shift_ctrl0}}) | + (({ex3_QM_q[msb + 1:63], 1'b1}) & {64-msb{ex3_denom_shift_ctrl1}}) | + (({ex3_QM_q[msb + 2:63], 2'b11}) & {64-msb{ex3_denom_shift_ctrl2}}); + + //------------------------------------------------------------------- + // final quotient correction: if the sign of the remainder != sign of the numerator, subtract 1 from the quotient, and + // add 1 dividend to the remainder + //------------------------------------------------------------------- + + // add the final sum and carry to get the real remainder + assign ex3_add_rslt[msb:66] = ex3_PR_sum_q[msb:66] + ex3_PR_carry_q[msb:66]; + + assign ex3_add_rslt_sign_d = ex3_add_rslt[msb]; + + assign ex3_quotient_correction = ex3_add_rslt_sign_d; + + //------------------------------------------------------------------- + // Adder + //------------------------------------------------------------------- + assign ex3_numer_d = (ex2_div_val_q == 1'b1) ? {3'b000, ex2_numer} : + ex3_numer_q; + assign ex3_sub_rslt = ex3_numer_q - {1'b0, ex3_denom_q}; + + //------------------------------------------------------------------- + // Quotient + //------------------------------------------------------------------- + + assign ex3_Q_sel0 = ex3_div_val_q; + assign ex3_Q_sel1 = ((~ex2_div_done) | ex2_div_almost_done) & (~ex3_div_val_q); // was ex1_div_almost_done and not ex2_div_val_q; + assign ex3_Q_sel2 = ex2_div_done & (~ex3_div_val_q); + + assign ex4_quotient_d = ({`GPR_WIDTH{tidn}} & {`GPR_WIDTH{ex3_Q_sel0}}) | + (ex3_Q_d & {`GPR_WIDTH{ex3_Q_sel1}}) | + (ex4_quotient_q & {`GPR_WIDTH{ex3_Q_sel2}}); // latch the quotient while the remainder is summed + + // 2's complement quotient if necessary for signed divide + assign ex4_quotient_2s = (~ex4_quotient_q); + + assign ex4_div_rt_op1 = (ex4_2s_rslt_q == 1'b1) ? ex4_quotient_2s : // 00 + ex4_quotient_q; + assign ex4_addop_sel0 = (~ex4_2s_rslt_q) & (~ex4_quotient_correction); + assign ex4_addop_sel1 = ex4_2s_rslt_q & (~ex4_quotient_correction); // 10 + assign ex4_addop_sel2 = (~ex4_2s_rslt_q) & ex4_quotient_correction; // 01 + assign ex4_addop_sel3 = ex4_2s_rslt_q & ex4_quotient_correction; // 11 + + // 0x00000000 + // 0xFFFFFFFF + assign ex4_div_rt_op2 = ( {`GPR_WIDTH{1'b0}} & {64-msb{ex4_addop_sel0}}) | + ({{`GPR_WIDTH-1{1'b0}},1'b1} & {64-msb{ex4_addop_sel1}}) | + ( {`GPR_WIDTH{1'b1}} & {64-msb{ex4_addop_sel2}}) | + ({{`GPR_WIDTH-2{1'b0}},2'b10} & {64-msb{ex4_addop_sel3}}); // 0x00000001 + // 0x00000002 + + //------------------------------------------------------------------- + // Return quotient + //------------------------------------------------------------------- + assign ex4_div_rt_d = ex4_div_rt_op1 + ex4_div_rt_op2; + + // Return Zero for all undefined cases + assign ex3_rslt_sign = (ex3_div_size_q == 1'b1) ? ex4_div_rt_d[msb] : + ex4_div_rt_d[32]; + generate + if (`GPR_WIDTH == 64) + begin : div_rslt_64b + assign ex4_div_rt[0:31] = (~(ex4_div_ovf_q | ~ex4_div_size_q))==1'b1 ? ex4_div_rt_q[0:31] : 32'b0; + end + endgenerate + assign ex4_div_rt[32:63] = (~(ex4_div_ovf_q))==1'b1 ? ex4_div_rt_q[32:63] : 32'b0; + + assign div_byp_ex4_rt = ex4_div_rt; + + // Divide Undefined/Overflow Conditions + // ------------------------------------------------------------------------------ + // | Cond 1 | Cond 2 | Cond 3 | Cond 4 | + // -----------------------------------------------------------------------------+ + // | 0x8000... / -1 | / 0 | RA >= RB | Result doesn't | + // | | | | fit in 32/64 bits | + // -----------------------------------------------------------------------------+ + // divw | X | X | | | + // divwu | | X | | | + // divwe | X | X | | X | + // divweu | | X | X | | + // divd | X | X | | | + // divdu | | X | | | + // divde | X | X | | X | + // divdeu | | X | X | | + // -----------------------------------------------------------------------------+ + + assign ex2_num_cmp0_lo_nomsb = (~|(byp_div_ex2_rs1[33:63])); + assign ex2_den_cmp0_lo = (~|(byp_div_ex2_rs2[32:63])); + assign ex2_den_cmp1_lo = &(byp_div_ex2_rs2[32:63]); + assign ex4_qot_cmp0_lo = (~|(ex4_div_rt_q[32:63])); + assign ex2_num_cmp0_lo = (~byp_div_ex2_rs1[32]) & ex2_num_cmp0_lo_nomsb; + assign ex2_div_ovf_cond1_wd = byp_div_ex2_rs1[32] & ex2_num_cmp0_lo_nomsb & ex2_den_cmp1_lo; + + generate + if (`GPR_WIDTH == 64) + begin : div_64b_oflow + assign ex2_num_cmp0_hi_nomsb = (~|(byp_div_ex2_rs1[1:31])); + assign ex2_den_cmp0_hi = (~|(byp_div_ex2_rs2[0:31])); + assign ex2_den_cmp1_hi = &(byp_div_ex2_rs2[0:31]); + assign ex4_qot_cmp0_hi = (~|(ex4_div_rt_q[0:31])); + assign ex2_num_cmp0_hi = (~byp_div_ex2_rs1[0]) & ex2_num_cmp0_hi_nomsb; + assign ex2_div_ovf_cond1_dw = byp_div_ex2_rs1[0] & ex2_num_cmp0_hi_nomsb & (~byp_div_ex2_rs1[32]) & ex2_num_cmp0_lo_nomsb & ex2_den_cmp1_lo & ex2_den_cmp1_hi; + end + endgenerate + + generate + if (`GPR_WIDTH == 32) + begin : div_32b_oflow + assign ex2_num_cmp0_hi_nomsb = 1'b1; + assign ex2_den_cmp0_hi = 1'b1; + assign ex2_den_cmp1_hi = 1'b1; + assign ex2_div_ovf_cond1_dw = 1'b1; + assign ex2_num_cmp0_hi = 1'b1; + assign ex4_qot_cmp0_hi = 1'b1; + end + endgenerate + + assign ex2_div_ovf_cond1 = (ex2_div_size_q == 1'b1) ? ex2_div_ovf_cond1_dw : + ex2_div_ovf_cond1_wd; + assign ex2_div_ovf_cond2 = ex2_den_cmp0_lo & (ex2_den_cmp0_hi | (~ex2_div_size_q)); + + assign ex2_div_ovf = (ex2_div_ovf_cond1 & ex2_div_sign_q) | ex2_div_ovf_cond2; + + // Condition 3 + assign ex3_den_eq_num = &(ex3_denom_q ~^ ex3_numer_q[msb + 1:66]); + assign ex3_den_gte_num = (~(ex3_sub_rslt[msb])) | ex3_den_eq_num; + assign ex3_div_ovf_cond3 = ex3_den_gte_num & (~ex3_div_sign_q) & ex3_div_extd_q; + + // Condition 4 + // Need to watch quotient for first 65 cycles of divde, 33 cycles of divwe + assign ex3_cycles_gt_64 = ((ex3_cycles_q > 8'd35)) ? 1'b1 : + 1'b0; + assign ex3_cycles_gt_32 = ((ex3_cycles_q > 8'd19)) ? 1'b1 : + 1'b0; + + // If any bit is pushed during the watch period, flag overflow + assign ex4_cycle_watch_d = (ex3_div_size_q == 1'b1) ? ex3_cycles_gt_64 : + ex3_cycles_gt_32; + assign ex4_quot_watch_d_old = (ex4_quot_watch_q | (ex4_cycle_watch_q & ex4_quotient_q[63])) & (~ex4_div_val_q); + assign ex4_quot_watch_d = (ex4_quot_watch_q | (ex3_quotient_ovf_cond4 & (~ex2_div_done))) & (~ex4_div_val_q); + + assign ex3_numer_eq_zero_d = ex2_num_cmp0_lo & (ex2_num_cmp0_hi | (~ex2_div_size_q)); + + // overflow out of 32/64 bits + assign ex3_div_ovf_cond4 = ex4_quot_watch_q | ((ex3_rslt_sign ^ ex3_2s_rslt_q) & (~ex3_numer_eq_zero_q)) | (ex3_rslt_sign & ex3_numer_eq_zero_q); // result sign differs from expected, numerator not equal to zero + // result sign is negative , numerator equal to zero + + assign ex4_div_ovf_d = ex3_div_ovf_q | ex4_div_ovf_cond3_q | (ex3_div_ovf_cond4 & (ex3_div_sign_q & ex3_div_extd_q)); + + assign div_byp_ex4_xer[0] = (ex4_xer_ov_update_q == 1'b1) ? ex4_div_ovf_q | xersrc_q[0] : + xersrc_q[0]; + + assign div_byp_ex4_xer[1] = (ex4_xer_ov_update_q == 1'b1) ? ex4_div_ovf_q : + xersrc_q[1]; + assign div_byp_ex4_xer[2:9] = xersrc_q[2:9]; + + //------------------------------------------------------------------- + // Record forms + //------------------------------------------------------------------- + // Overflow Cases + assign ex4_cmp0_undef = ex4_div_ovf_q | ((~ex4_div_size_q) & ex2_spr_msr_cm_q); // Word op in 64b mode + + assign ex4_lt = (ex2_spr_msr_cm_q == 1'b1) ? ex4_div_rt_q[msb] : + ex4_div_rt_q[32]; + assign ex4_cmp0_eq = (ex4_qot_cmp0_lo & (ex4_qot_cmp0_hi | (~ex2_spr_msr_cm_q))) & (~ex4_cmp0_undef); + + assign ex4_cmp0_lt = ex4_lt & (~ex4_cmp0_eq) & (~ex4_cmp0_undef); + assign ex4_cmp0_gt = (~ex4_lt) & (~ex4_cmp0_eq) & (~ex4_cmp0_undef); + + assign div_byp_ex4_cr = {ex4_cmp0_lt, ex4_cmp0_gt, ex4_cmp0_eq, (xersrc_q[0] | (ex4_div_ovf_q & ex4_xer_ov_update_q))}; + + + //------------------------------------------------------------------- + // Latches + //------------------------------------------------------------------- + //mark_unused(xersrc_q[1])mark_unused(ex4_div_recform_q) + tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex2_div_ctr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(dec_div_ex1_div_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_div_ctr_offset:ex2_div_ctr_offset + 8 - 1]), + .scout(sov[ex2_div_ctr_offset:ex2_div_ctr_offset + 8 - 1]), + .din(dec_div_ex1_div_ctr), + .dout(ex2_div_ctr_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_div_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_div_val_offset]), + .scout(sov[ex2_div_val_offset]), + .din(ex1_div_val), + .dout(ex2_div_val_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_div_sign_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(dec_div_ex1_div_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_div_sign_offset]), + .scout(sov[ex2_div_sign_offset]), + .din(dec_div_ex1_div_sign), + .dout(ex2_div_sign_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_div_size_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(dec_div_ex1_div_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_div_size_offset]), + .scout(sov[ex2_div_size_offset]), + .din(dec_div_ex1_div_size), + .dout(ex2_div_size_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_div_extd_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(dec_div_ex1_div_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_div_extd_offset]), + .scout(sov[ex2_div_extd_offset]), + .din(dec_div_ex1_div_extd), + .dout(ex2_div_extd_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_div_recform_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(dec_div_ex1_div_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_div_recform_offset]), + .scout(sov[ex2_div_recform_offset]), + .din(dec_div_ex1_div_recform), + .dout(ex2_div_recform_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_xer_ov_update_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(dec_div_ex1_div_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_xer_ov_update_offset]), + .scout(sov[ex2_xer_ov_update_offset]), + .din(dec_div_ex1_xer_ov_update), + .dout(ex2_xer_ov_update_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_div_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_div_val_offset]), + .scout(sov[ex3_div_val_offset]), + .din(ex2_div_val_q), + .dout(ex3_div_val_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_cycle_act_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_cycle_act_offset]), + .scout(sov[ex3_cycle_act_offset]), + .din(ex3_cycle_act_d), + .dout(ex3_cycle_act_q) + ); + + tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex3_cycles_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_cycle_act_d), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_cycles_offset:ex3_cycles_offset + 8 - 1]), + .scout(sov[ex3_cycles_offset:ex3_cycles_offset + 8 - 1]), + .din(ex3_cycles_d), + .dout(ex3_cycles_q) + ); + + tri_rlmreg_p #(.WIDTH((65-msb+1)), .INIT(0), .NEEDS_SRESET(1)) ex3_denom_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(divrunning_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_denom_offset:ex3_denom_offset + (65-msb+1) - 1]), + .scout(sov[ex3_denom_offset:ex3_denom_offset + (65-msb+1) - 1]), + .din(ex3_denom_d), + .dout(ex3_denom_q) + ); + + tri_rlmreg_p #(.WIDTH((66-msb+1)), .INIT(0), .NEEDS_SRESET(1)) ex3_numer_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(divrunning_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_numer_offset:ex3_numer_offset + (66-msb+1) - 1]), + .scout(sov[ex3_numer_offset:ex3_numer_offset + (66-msb+1) - 1]), + .din(ex3_numer_d), + .dout(ex3_numer_q) + ); + + // begin r4 latches + + + tri_rlmreg_p #(.WIDTH((66-msb+1)), .INIT(0), .NEEDS_SRESET(1)) ex3_PR_sum_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(divrunning_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_PR_sum_offset:ex3_PR_sum_offset + (66-msb+1) - 1]), + .scout(sov[ex3_PR_sum_offset:ex3_PR_sum_offset + (66-msb+1) - 1]), + .din(ex3_PR_sum_d), + .dout(ex3_PR_sum_q) + ); + + + tri_rlmreg_p #(.WIDTH((66-msb+1)), .INIT(0), .NEEDS_SRESET(1)) ex3_PR_carry_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(divrunning_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_PR_carry_offset:ex3_PR_carry_offset + (66-msb+1) - 1]), + .scout(sov[ex3_PR_carry_offset:ex3_PR_carry_offset + (66-msb+1) - 1]), + .din(ex3_PR_carry_d), + .dout(ex3_PR_carry_q) + ); + + tri_rlmreg_p #(.WIDTH((63-msb+1)), .INIT(0), .NEEDS_SRESET(1)) ex3_Q_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(divrunning_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_Q_offset:ex3_Q_offset + (63-msb+1) - 1]), + .scout(sov[ex3_Q_offset:ex3_Q_offset + (63-msb+1) - 1]), + .din(ex3_Q_d), + .dout(ex3_Q_q) + ); + + tri_rlmreg_p #(.WIDTH((63-msb+1)), .INIT(0), .NEEDS_SRESET(1)) ex3_QM_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(divrunning_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_QM_offset:ex3_QM_offset + (63-msb+1) - 1]), + .scout(sov[ex3_QM_offset:ex3_QM_offset + (63-msb+1) - 1]), + .din(ex3_QM_d), + .dout(ex3_QM_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_oddshift_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(divrunning_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_oddshift_offset]), + .scout(sov[ex3_oddshift_offset]), + .din(ex3_oddshift_d), + .dout(ex3_oddshift_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_divrunning_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_divrunning_offset]), + .scout(sov[ex3_divrunning_offset]), + .din(ex3_divrunning_d), + .dout(ex3_divrunning_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_divrunning_act_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_divrunning_act_offset]), + .scout(sov[ex4_divrunning_act_offset]), + .din(ex4_divrunning_act_d), + .dout(ex4_divrunning_act_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_divflush_1d_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_divflush_1d_offset]), + .scout(sov[ex3_divflush_1d_offset]), + .din(div_flush), + .dout(div_flush_1d) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_divflush_2d_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_divflush_2d_offset]), + .scout(sov[ex4_divflush_2d_offset]), + .din(div_flush_1d), + .dout(div_flush_2d) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_add_rslt_sign_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_add_rslt_sign_offset]), + .scout(sov[ex3_add_rslt_sign_offset]), + .din(ex3_add_rslt_sign_d), + .dout(ex3_add_rslt_sign_q) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_quotient_correction_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_quotient_correction_offset]), + .scout(sov[ex4_quotient_correction_offset]), + .din(ex3_quotient_correction), + .dout(ex4_quotient_correction) + ); + + tri_rlmreg_p #(.WIDTH((65-msb+1)), .INIT(0), .NEEDS_SRESET(1)) ex3_dmask_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(divrunning_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_dmask_offset:ex3_dmask_offset + (65-msb+1) - 1]), + .scout(sov[ex3_dmask_offset:ex3_dmask_offset + (65-msb+1) - 1]), + .din(ex3_dmask_d), + .dout(ex3_dmask_q) + ); + // end r4 latches + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_div_ovf_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_div_val_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_div_ovf_offset]), + .scout(sov[ex3_div_ovf_offset]), + .din(ex2_div_ovf), + .dout(ex3_div_ovf_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_xer_ov_update_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_xer_ov_update_offset]), + .scout(sov[ex3_xer_ov_update_offset]), + .din(ex2_xer_ov_update_q), + .dout(ex3_xer_ov_update_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_div_recform_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_div_recform_offset]), + .scout(sov[ex3_div_recform_offset]), + .din(ex2_div_recform_q), + .dout(ex3_div_recform_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_div_size_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_div_val_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_div_size_offset]), + .scout(sov[ex3_div_size_offset]), + .din(ex2_div_size_q), + .dout(ex3_div_size_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_div_sign_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_div_val_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_div_sign_offset]), + .scout(sov[ex3_div_sign_offset]), + .din(ex2_div_sign_q), + .dout(ex3_div_sign_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_div_extd_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_div_val_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_div_extd_offset]), + .scout(sov[ex3_div_extd_offset]), + .din(ex2_div_extd_q), + .dout(ex3_div_extd_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_2s_rslt_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_div_val_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_2s_rslt_offset]), + .scout(sov[ex3_2s_rslt_offset]), + .din(ex2_2s_rslt), + .dout(ex3_2s_rslt_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_div_done_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_div_done_offset]), + .scout(sov[ex3_div_done_offset]), + .din(ex2_div_done), + .dout(ex3_div_done_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_div_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_div_val_offset]), + .scout(sov[ex4_div_val_offset]), + .din(ex3_div_val_q), + .dout(ex4_div_val_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_cycle_watch_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_cycle_watch_offset]), + .scout(sov[ex4_cycle_watch_offset]), + .din(ex4_cycle_watch_d), + .dout(ex4_cycle_watch_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_quot_watch_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_quot_watch_offset]), + .scout(sov[ex4_quot_watch_offset]), + .din(ex4_quot_watch_d), + .dout(ex4_quot_watch_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_div_ovf_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_div_ovf_offset]), + .scout(sov[ex4_div_ovf_offset]), + .din(ex4_div_ovf_d), + .dout(ex4_div_ovf_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_xer_ov_update_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_xer_ov_update_offset]), + .scout(sov[ex4_xer_ov_update_offset]), + .din(ex3_xer_ov_update_q), + .dout(ex4_xer_ov_update_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_div_done_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_div_done_offset]), + .scout(sov[ex4_div_done_offset]), + .din(ex4_div_done_d), + .dout(ex4_div_done_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_div_done_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex5_div_done_offset]), + .scout(sov[ex5_div_done_offset]), + .din(ex5_div_done_d), + .dout(ex5_div_done_q) + ); + + tri_rlmreg_p #(.WIDTH((63-msb+1)), .INIT(0), .NEEDS_SRESET(1)) ex4_quotient_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(divrunning_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_quotient_offset:ex4_quotient_offset + (63-msb+1) - 1]), + .scout(sov[ex4_quotient_offset:ex4_quotient_offset + (63-msb+1) - 1]), + .din(ex4_quotient_d), + .dout(ex4_quotient_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_div_recform_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_div_recform_offset]), + .scout(sov[ex4_div_recform_offset]), + .din(ex3_div_recform_q), + .dout(ex4_div_recform_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_div_size_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_div_size_offset]), + .scout(sov[ex4_div_size_offset]), + .din(ex3_div_size_q), + .dout(ex4_div_size_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_2s_rslt_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_2s_rslt_offset]), + .scout(sov[ex4_2s_rslt_offset]), + .din(ex3_2s_rslt_q), + .dout(ex4_2s_rslt_q) + ); + + tri_rlmreg_p #(.WIDTH((63-msb+1)), .INIT(0), .NEEDS_SRESET(1)) ex4_div_rt_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(divrunning_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_div_rt_offset:ex4_div_rt_offset + (63-msb+1) - 1]), + .scout(sov[ex4_div_rt_offset:ex4_div_rt_offset + (63-msb+1) - 1]), + .din(ex4_div_rt_d), + .dout(ex4_div_rt_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_div_ovf_cond3_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex3_div_val_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_div_ovf_cond3_offset]), + .scout(sov[ex4_div_ovf_cond3_offset]), + .din(ex3_div_ovf_cond3), + .dout(ex4_div_ovf_cond3_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_spr_msr_cm_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(dec_div_ex1_div_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_spr_msr_cm_offset]), + .scout(sov[ex2_spr_msr_cm_offset]), + .din(ex1_spr_msr_cm), + .dout(ex2_spr_msr_cm_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_numer_eq_zero_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_div_val_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_numer_eq_zero_offset]), + .scout(sov[ex3_numer_eq_zero_offset]), + .din(ex3_numer_eq_zero_d), + .dout(ex3_numer_eq_zero_q) + ); + + tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) xersrc_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_div_val_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[xersrc_offset:xersrc_offset + 10 - 1]), + .scout(sov[xersrc_offset:xersrc_offset + 10 - 1]), + .din(byp_div_ex2_xer), + .dout(xersrc_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) cp_flush_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[cp_flush_offset:cp_flush_offset + `THREADS - 1]), + .scout(sov[cp_flush_offset:cp_flush_offset + `THREADS - 1]), + .din(cp_flush), + .dout(cp_flush_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex2_div_tid_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(dec_div_ex1_div_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_div_tid_offset:ex2_div_tid_offset + `THREADS - 1]), + .scout(sov[ex2_div_tid_offset:ex2_div_tid_offset + `THREADS - 1]), + .din(ex1_div_tid), + .dout(ex2_div_tid_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex3_div_tid_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_div_val_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_div_tid_offset:ex3_div_tid_offset + `THREADS - 1]), + .scout(sov[ex3_div_tid_offset:ex3_div_tid_offset + `THREADS - 1]), + .din(ex2_div_tid_q), + .dout(ex3_div_tid_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) perf_divrunning_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[perf_divrunning_offset : perf_divrunning_offset + `THREADS-1]), + .scout(sov[perf_divrunning_offset : perf_divrunning_offset + `THREADS-1]), + .din(perf_divrunning_d), + .dout(perf_divrunning_q) + ); + + assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in}; + assign scan_out = sov[0]; + +endmodule diff --git a/dev/verilog/work/xu0_dlmzb.v b/dev/verilog/work/xu0_dlmzb.v new file mode 100755 index 0000000..3c3b952 --- /dev/null +++ b/dev/verilog/work/xu0_dlmzb.v @@ -0,0 +1,91 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +//***************************************************************************** +// Description: XU Determine Leftmost Zero Byte +// +//***************************************************************************** + +module xu0_dlmzb( + // Inputs + input [32:63] byp_dlm_ex2_rs1, + input [32:63] byp_dlm_ex2_rs2, + input [0:2] byp_dlm_ex2_xer, + + // Outputs + output [0:9] dlm_byp_ex2_xer, + output [0:3] dlm_byp_ex2_cr, + output [60:63] dlm_byp_ex2_rt +); + + + wire [0:7] a; + wire [0:7] a0; + wire [0:7] a1; + wire [0:7] a2; + wire [0:3] y; + + // Null == 0 + assign a[0] = |(byp_dlm_ex2_rs1[32:39]); + assign a[1] = |(byp_dlm_ex2_rs1[40:47]); + assign a[2] = |(byp_dlm_ex2_rs1[48:55]); + assign a[3] = |(byp_dlm_ex2_rs1[56:63]); + assign a[4] = |(byp_dlm_ex2_rs2[32:39]); + assign a[5] = |(byp_dlm_ex2_rs2[40:47]); + assign a[6] = |(byp_dlm_ex2_rs2[48:55]); + assign a[7] = |(byp_dlm_ex2_rs2[56:63]); + + assign a0[1:7] = a[0:6] & a[1:7]; + assign a1[2:7] = a0[0:5] & a0[2:7]; + assign a2[4:7] = a1[0:3] & a1[4:7]; + + assign a0[0:0] = a[0:0]; + assign a1[0:1] = a0[0:1]; + assign a2[0:3] = a1[0:3]; + + assign y = (a2[0:7] == 8'b00000000) ? 4'b0001 : // Null in last 4B + (a2[0:7] == 8'b10000000) ? 4'b0010 : + (a2[0:7] == 8'b11000000) ? 4'b0011 : + (a2[0:7] == 8'b11100000) ? 4'b0100 : + (a2[0:7] == 8'b11110000) ? 4'b0101 : + (a2[0:7] == 8'b11111000) ? 4'b0110 : + (a2[0:7] == 8'b11111100) ? 4'b0111 : + 4'b1000; + + assign dlm_byp_ex2_cr[0] = (~a2[7]) & a2[3]; + assign dlm_byp_ex2_cr[1] = (~a2[7]) & (~a2[3]); // Null in first 4B + assign dlm_byp_ex2_cr[2] = a2[7]; // Null not found + assign dlm_byp_ex2_cr[3] = byp_dlm_ex2_xer[0]; // SO Copy + + assign dlm_byp_ex2_xer = {byp_dlm_ex2_xer[0:2], 3'b000, y[0:3]}; + + assign dlm_byp_ex2_rt = y; + +endmodule diff --git a/dev/verilog/work/xu1.v b/dev/verilog/work/xu1.v new file mode 100755 index 0000000..c750369 --- /dev/null +++ b/dev/verilog/work/xu1.v @@ -0,0 +1,465 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: Simple Execution Unit +// +//***************************************************************************** +`include "tri_a2o.vh" + +module xu1( + //------------------------------------------------------------------- + // Clocks & Power + //------------------------------------------------------------------- + input [0:`NCLK_WIDTH-1] nclk, + inout vdd, + inout gnd, + + //------------------------------------------------------------------- + // Pervasive + //------------------------------------------------------------------- + input d_mode_dc, + input delay_lclkr_dc, + input mpw1_dc_b, + input mpw2_dc_b, + input func_sl_force, + input func_sl_thold_0_b, + input sg_0, + input scan_in, + output scan_out, + + output xu1_pc_ram_done, + output [64-`GPR_WIDTH:63] xu1_pc_ram_data, + + input xu0_xu1_ex3_act, + input lq_xu_ex5_act, + + //------------------------------------------------------------------- + // Interface with SPR + //------------------------------------------------------------------- + input [0:`THREADS-1] spr_msr_cm, // 0: 32 bit mode, 1: 64 bit mode + + //------------------------------------------------------------------- + // Interface with CP + //------------------------------------------------------------------- + input [0:`THREADS-1] cp_flush, + + //------------------------------------------------------------------- + // Interface with RV + //------------------------------------------------------------------- + input [0:`THREADS-1] rv_xu1_vld, + input rv_xu1_s1_v, + input rv_xu1_s2_v, + input rv_xu1_s3_v, + input [0:31] rv_xu1_ex0_instr, + input [0:`ITAG_SIZE_ENC-1] rv_xu1_ex0_itag, + input rv_xu1_ex0_isstore, + input [1:1] rv_xu1_ex0_ucode, + input rv_xu1_ex0_t1_v, + input [0:`GPR_POOL_ENC-1] rv_xu1_ex0_t1_p, + input rv_xu1_ex0_t2_v, + input [0:`GPR_POOL_ENC-1] rv_xu1_ex0_t2_p, + input rv_xu1_ex0_t3_v, + input [0:`GPR_POOL_ENC-1] rv_xu1_ex0_t3_p, + input rv_xu1_ex0_s1_v, + input [0:2] rv_xu1_ex0_s3_t, + input [0:`THREADS-1] rv_xu1_ex0_spec_flush, + input [0:`THREADS-1] rv_xu1_ex1_spec_flush, + input [0:`THREADS-1] rv_xu1_ex2_spec_flush, + + //------------------------------------------------------------------- + // Interface with Bypass Controller + //------------------------------------------------------------------- + input [1:11] rv_xu1_s1_fxu0_sel, + input [1:11] rv_xu1_s2_fxu0_sel, + input [2:11] rv_xu1_s3_fxu0_sel, + input [1:6] rv_xu1_s1_fxu1_sel, + input [1:6] rv_xu1_s2_fxu1_sel, + input [2:6] rv_xu1_s3_fxu1_sel, + input [4:8] rv_xu1_s1_lq_sel, + input [4:8] rv_xu1_s2_lq_sel, + input [4:8] rv_xu1_s3_lq_sel, + input [2:3] rv_xu1_s1_rel_sel, + input [2:3] rv_xu1_s2_rel_sel, + + //------------------------------------------------------------------- + // Interface with LQ + //------------------------------------------------------------------- + output [0:`THREADS-1] xu1_lq_ex2_stq_val, + output [0:`ITAG_SIZE_ENC-1] xu1_lq_ex2_stq_itag, + output [1:4] xu1_lq_ex2_stq_size, + output xu1_lq_ex3_illeg_lswx, + output xu1_lq_ex3_strg_noop, + output [(64-`GPR_WIDTH)/8:7] xu1_lq_ex2_stq_dvc1_cmp, + output [(64-`GPR_WIDTH)/8:7] xu1_lq_ex2_stq_dvc2_cmp, + + //------------------------------------------------------------------- + // Interface with IU + //------------------------------------------------------------------- + output [0:`THREADS-1] xu1_iu_execute_vld, + output [0:`ITAG_SIZE_ENC-1] xu1_iu_itag, + + output [0:`THREADS-1] xu_iu_ucode_xer_val, + output [3:9] xu_iu_ucode_xer, + + output xu1_rv_ex2_s1_abort, + output xu1_rv_ex2_s2_abort, + output xu1_rv_ex2_s3_abort, + //------------------------------------------------------------------- + // Bypass Inputs + //------------------------------------------------------------------- + // Regfile Data + input [64-`GPR_WIDTH:63] gpr_xu1_ex1_r1d, + input [64-`GPR_WIDTH:63] gpr_xu1_ex1_r2d, + input [0:9] xer_xu1_ex1_r3d, + input [0:3] cr_xu1_ex1_r3d, + // External Bypass + input xu0_xu1_ex2_abort, + input xu0_xu1_ex6_abort, + input lq_xu_ex5_abort, + input [64-`GPR_WIDTH:63] xu0_xu1_ex2_rt, + input [64-`GPR_WIDTH:63] xu0_xu1_ex3_rt, + input [64-`GPR_WIDTH:63] xu0_xu1_ex4_rt, + input [64-`GPR_WIDTH:63] xu0_xu1_ex5_rt, + input [64-`GPR_WIDTH:63] xu0_xu1_ex6_rt, + input [64-`GPR_WIDTH:63] xu0_xu1_ex7_rt, + input [64-`GPR_WIDTH:63] xu0_xu1_ex8_rt, + input [64-`GPR_WIDTH:63] xu0_xu1_ex6_lq_rt, + input [64-`GPR_WIDTH:63] xu0_xu1_ex7_lq_rt, + input [64-`GPR_WIDTH:63] xu0_xu1_ex8_lq_rt, + input [64-`GPR_WIDTH:63] lq_xu_ex5_rt, + input [64-`GPR_WIDTH:63] lq_xu_rel_rt, + input lq_xu_rel_act, + // CR + input [0:3] lq_xu_ex5_cr, + input [0:3] xu0_xu1_ex3_cr, + input [0:3] xu0_xu1_ex4_cr, + input [0:3] xu0_xu1_ex6_cr, + // XER + input [0:9] xu0_xu1_ex3_xer, + input [0:9] xu0_xu1_ex4_xer, + input [0:9] xu0_xu1_ex6_xer, + //------------------------------------------------------------------- + // Bypass Outputs + //------------------------------------------------------------------- + output xu1_xu0_ex3_act, + output xu1_xu0_ex2_abort, + output xu1_lq_ex3_abort, + output [64-`GPR_WIDTH:63] xu1_xu0_ex2_rt, + output [64-`GPR_WIDTH:63] xu1_xu0_ex3_rt, + output [64-`GPR_WIDTH:63] xu1_xu0_ex4_rt, + output [64-`GPR_WIDTH:63] xu1_xu0_ex5_rt, + output [64-`GPR_WIDTH:63] xu1_lq_ex3_rt, + // CR + output [0:3] xu1_xu0_ex3_cr, + // XER + output [0:9] xu1_xu0_ex3_xer, + + //------------------------------------------------------------------- + // Interface with Regfiles + //------------------------------------------------------------------- + output xu1_gpr_ex3_we, + output [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] xu1_gpr_ex3_wa, + output [64-`GPR_WIDTH:65+`GPR_WIDTH/8] xu1_gpr_ex3_wd, + + output xu1_xer_ex3_we, + output [0:`XER_POOL_ENC+`THREADS_POOL_ENC-1] xu1_xer_ex3_wa, + output [0:9] xu1_xer_ex3_w0d, + + output xu1_cr_ex3_we, + output [0:`CR_POOL_ENC+`THREADS_POOL_ENC-1] xu1_cr_ex3_wa, + output [0:3] xu1_cr_ex3_w0d, + + input [0:`THREADS-1] pc_xu_ram_active, + `ifndef THREADS1 + input [64-`GPR_WIDTH:63] spr_dvc1_t1, + input [64-`GPR_WIDTH:63] spr_dvc2_t1, + `endif + input [64-`GPR_WIDTH:63] spr_dvc1_t0, + input [64-`GPR_WIDTH:63] spr_dvc2_t0, + + // Debug + input [0:10] pc_xu_debug_mux_ctrls, + input [0:31] xu1_debug_bus_in, + output [0:31] xu1_debug_bus_out, + input [0:3] xu1_coretrace_ctrls_in, + output [0:3] xu1_coretrace_ctrls_out +); + //!! Bugspray Include: xu1_byp; + + localparam scan_right = 3; + wire [0:scan_right-1] siv; + wire [0:scan_right-1] sov; + // Signals + wire byp_dec_ex2_abort; + wire dec_byp_ex0_act; + wire [64-`GPR_WIDTH:63] dec_byp_ex1_imm; + wire [24:25] dec_byp_ex1_instr; + wire dec_byp_ex0_rs2_sel_imm; + wire dec_byp_ex0_rs1_sel_zero; + wire [0:`THREADS-1] dec_byp_ex2_tid; + wire [(64-`GPR_WIDTH)/8:7] dec_byp_ex2_dvc_mask; + + wire dec_alu_ex1_act; + wire [0:31] dec_alu_ex1_instr; + wire dec_alu_ex1_sel_isel; + wire [0:`GPR_WIDTH/8-1] dec_alu_ex1_add_rs1_inv; + wire [0:1] dec_alu_ex2_add_ci_sel; + wire dec_alu_ex1_sel_trap; + wire dec_alu_ex1_sel_cmpl; + wire dec_alu_ex1_sel_cmp; + wire dec_alu_ex1_msb_64b_sel; + wire dec_alu_ex1_xer_ov_en; + wire dec_alu_ex1_xer_ca_en; + + wire [64-`GPR_WIDTH:63] alu_byp_ex2_add_rt; + wire [64-`GPR_WIDTH:63] alu_byp_ex3_rt; + wire [0:3] alu_byp_ex3_cr; + wire [0:9] alu_byp_ex3_xer; + wire [64-`GPR_WIDTH:63] byp_alu_ex2_rs1; + wire [64-`GPR_WIDTH:63] byp_alu_ex2_rs2; + wire byp_alu_ex2_cr_bit; + wire [0:9] byp_alu_ex2_xer; + wire [3:9] byp_dec_ex2_xer; + + assign xu1_debug_bus_out = xu1_debug_bus_in; + assign xu1_coretrace_ctrls_out = xu1_coretrace_ctrls_in; + + + xu_alu alu( + .nclk(nclk), + .vdd(vdd), + .gnd(gnd), + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .func_sl_force(func_sl_force), + .func_sl_thold_0_b(func_sl_thold_0_b), + .sg_0(sg_0), + .scan_in(siv[0]), + .scan_out(sov[0]), + .dec_alu_ex1_act(dec_alu_ex1_act), + .dec_alu_ex1_instr(dec_alu_ex1_instr), + .dec_alu_ex1_sel_isel(dec_alu_ex1_sel_isel), + .dec_alu_ex1_add_rs1_inv(dec_alu_ex1_add_rs1_inv), + .dec_alu_ex2_add_ci_sel(dec_alu_ex2_add_ci_sel), + .dec_alu_ex1_sel_trap(dec_alu_ex1_sel_trap), + .dec_alu_ex1_sel_cmpl(dec_alu_ex1_sel_cmpl), + .dec_alu_ex1_sel_cmp(dec_alu_ex1_sel_cmp), + .dec_alu_ex1_msb_64b_sel(dec_alu_ex1_msb_64b_sel), + .dec_alu_ex1_xer_ov_en(dec_alu_ex1_xer_ov_en), + .dec_alu_ex1_xer_ca_en(dec_alu_ex1_xer_ca_en), + .byp_alu_ex2_rs1(byp_alu_ex2_rs1), + .byp_alu_ex2_rs2(byp_alu_ex2_rs2), + .byp_alu_ex2_cr_bit(byp_alu_ex2_cr_bit), + .byp_alu_ex2_xer(byp_alu_ex2_xer), + .alu_byp_ex2_add_rt(alu_byp_ex2_add_rt), + .alu_byp_ex3_rt(alu_byp_ex3_rt), + .alu_byp_ex3_cr(alu_byp_ex3_cr), + .alu_byp_ex3_xer(alu_byp_ex3_xer), + .alu_dec_ex3_trap_val() + ); + + + xu1_byp byp( + .nclk(nclk), + .vdd(vdd), + .gnd(gnd), + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .func_sl_force(func_sl_force), + .func_sl_thold_0_b(func_sl_thold_0_b), + .sg_0(sg_0), + .scan_in(siv[1]), + .scan_out(sov[1]), + .dec_byp_ex0_act(dec_byp_ex0_act), + .byp_dec_ex2_abort(byp_dec_ex2_abort), + .xu0_xu1_ex3_act(xu0_xu1_ex3_act), + .lq_xu_ex5_act(lq_xu_ex5_act), + .dec_byp_ex1_imm(dec_byp_ex1_imm), + .dec_byp_ex1_instr(dec_byp_ex1_instr), + .dec_byp_ex0_rs2_sel_imm(dec_byp_ex0_rs2_sel_imm), + .dec_byp_ex0_rs1_sel_zero(dec_byp_ex0_rs1_sel_zero), + .dec_byp_ex2_tid(dec_byp_ex2_tid), + .dec_byp_ex2_dvc_mask(dec_byp_ex2_dvc_mask), + .rv_xu1_s1_v(rv_xu1_s1_v), + .rv_xu1_s2_v(rv_xu1_s2_v), + .rv_xu1_s3_v(rv_xu1_s3_v), + .rv_xu1_s1_fxu0_sel(rv_xu1_s1_fxu0_sel), + .rv_xu1_s2_fxu0_sel(rv_xu1_s2_fxu0_sel), + .rv_xu1_s3_fxu0_sel(rv_xu1_s3_fxu0_sel), + .rv_xu1_s1_fxu1_sel(rv_xu1_s1_fxu1_sel), + .rv_xu1_s2_fxu1_sel(rv_xu1_s2_fxu1_sel), + .rv_xu1_s3_fxu1_sel(rv_xu1_s3_fxu1_sel), + .rv_xu1_s1_lq_sel(rv_xu1_s1_lq_sel), + .rv_xu1_s2_lq_sel(rv_xu1_s2_lq_sel), + .rv_xu1_s3_lq_sel(rv_xu1_s3_lq_sel), + .rv_xu1_s1_rel_sel(rv_xu1_s1_rel_sel), + .rv_xu1_s2_rel_sel(rv_xu1_s2_rel_sel), + .gpr_xu1_ex1_r1d(gpr_xu1_ex1_r1d), + .gpr_xu1_ex1_r2d(gpr_xu1_ex1_r2d), + .xer_xu1_ex1_r3d(xer_xu1_ex1_r3d), + .cr_xu1_ex1_r3d(cr_xu1_ex1_r3d), + .xu0_xu1_ex2_abort(xu0_xu1_ex2_abort), + .xu0_xu1_ex6_abort(xu0_xu1_ex6_abort), + .xu0_xu1_ex2_rt(xu0_xu1_ex2_rt), + .xu0_xu1_ex3_rt(xu0_xu1_ex3_rt), + .xu0_xu1_ex4_rt(xu0_xu1_ex4_rt), + .xu0_xu1_ex5_rt(xu0_xu1_ex5_rt), + .xu0_xu1_ex6_rt(xu0_xu1_ex6_rt), + .xu0_xu1_ex7_rt(xu0_xu1_ex7_rt), + .xu0_xu1_ex8_rt(xu0_xu1_ex8_rt), + .xu0_xu1_ex6_lq_rt(xu0_xu1_ex6_lq_rt), + .xu0_xu1_ex7_lq_rt(xu0_xu1_ex7_lq_rt), + .xu0_xu1_ex8_lq_rt(xu0_xu1_ex8_lq_rt), + .lq_xu_ex5_abort(lq_xu_ex5_abort), + .lq_xu_ex5_rt(lq_xu_ex5_rt), + .lq_xu_rel_act(lq_xu_rel_act), + .lq_xu_rel_rt(lq_xu_rel_rt), + .lq_xu_ex5_cr(lq_xu_ex5_cr), + .xu0_xu1_ex3_cr(xu0_xu1_ex3_cr), + .xu0_xu1_ex4_cr(xu0_xu1_ex4_cr), + .xu0_xu1_ex6_cr(xu0_xu1_ex6_cr), + .xu0_xu1_ex3_xer(xu0_xu1_ex3_xer), + .xu0_xu1_ex4_xer(xu0_xu1_ex4_xer), + .xu0_xu1_ex6_xer(xu0_xu1_ex6_xer), + .alu_byp_ex2_add_rt(alu_byp_ex2_add_rt), + .alu_byp_ex3_rt(alu_byp_ex3_rt), + .alu_byp_ex3_cr(alu_byp_ex3_cr), + .alu_byp_ex3_xer(alu_byp_ex3_xer), + .xu1_xu0_ex2_abort(xu1_xu0_ex2_abort), + .xu1_lq_ex3_abort(xu1_lq_ex3_abort), + .xu1_xu0_ex2_rt(xu1_xu0_ex2_rt), + .xu1_xu0_ex3_rt(xu1_xu0_ex3_rt), + .xu1_xu0_ex4_rt(xu1_xu0_ex4_rt), + .xu1_xu0_ex5_rt(xu1_xu0_ex5_rt), + .xu1_lq_ex3_rt(xu1_lq_ex3_rt), + .xu1_pc_ram_data(xu1_pc_ram_data), + .xu1_xu0_ex3_cr(xu1_xu0_ex3_cr), + .xu1_xu0_ex3_xer(xu1_xu0_ex3_xer), + .byp_alu_ex2_rs1(byp_alu_ex2_rs1), + .byp_alu_ex2_rs2(byp_alu_ex2_rs2), + .byp_alu_ex2_cr_bit(byp_alu_ex2_cr_bit), + .byp_alu_ex2_xer(byp_alu_ex2_xer), + .byp_dec_ex2_xer(byp_dec_ex2_xer), + .xu_iu_ucode_xer(xu_iu_ucode_xer), + .xu1_rv_ex2_s1_abort(xu1_rv_ex2_s1_abort), + .xu1_rv_ex2_s2_abort(xu1_rv_ex2_s2_abort), + .xu1_rv_ex2_s3_abort(xu1_rv_ex2_s3_abort), + .xu1_gpr_ex3_wd(xu1_gpr_ex3_wd), + .xu1_xer_ex3_w0d(xu1_xer_ex3_w0d), + .xu1_cr_ex3_w0d(xu1_cr_ex3_w0d), + .xu1_lq_ex2_stq_dvc1_cmp(xu1_lq_ex2_stq_dvc1_cmp), + .xu1_lq_ex2_stq_dvc2_cmp(xu1_lq_ex2_stq_dvc2_cmp), + `ifndef THREADS1 + .spr_dvc1_t1(spr_dvc1_t1), + .spr_dvc2_t1(spr_dvc2_t1), + `endif + .spr_dvc1_t0(spr_dvc1_t0), + .spr_dvc2_t0(spr_dvc2_t0) + ); + + + xu1_dec dec( + .nclk(nclk), + .vdd(vdd), + .gnd(gnd), + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .func_sl_force(func_sl_force), + .func_sl_thold_0_b(func_sl_thold_0_b), + .sg_0(sg_0), + .scan_in(siv[2]), + .scan_out(sov[2]), + .spr_msr_cm(spr_msr_cm), // 0=> 0, + .cp_flush(cp_flush), + .rv_xu1_vld(rv_xu1_vld), + .rv_xu1_ex0_instr(rv_xu1_ex0_instr), + .rv_xu1_ex0_itag(rv_xu1_ex0_itag), + .rv_xu1_ex0_isstore(rv_xu1_ex0_isstore), + .rv_xu1_ex0_ucode(rv_xu1_ex0_ucode), + .rv_xu1_ex0_t1_v(rv_xu1_ex0_t1_v), + .rv_xu1_ex0_t1_p(rv_xu1_ex0_t1_p), + .rv_xu1_ex0_t2_v(rv_xu1_ex0_t2_v), + .rv_xu1_ex0_t2_p(rv_xu1_ex0_t2_p), + .rv_xu1_ex0_t3_v(rv_xu1_ex0_t3_v), + .rv_xu1_ex0_t3_p(rv_xu1_ex0_t3_p), + .rv_xu1_ex0_s1_v(rv_xu1_ex0_s1_v), + .rv_xu1_ex0_s3_t(rv_xu1_ex0_s3_t), + .rv_xu1_ex0_spec_flush(rv_xu1_ex0_spec_flush), + .rv_xu1_ex1_spec_flush(rv_xu1_ex1_spec_flush), + .rv_xu1_ex2_spec_flush(rv_xu1_ex2_spec_flush), + .xu1_lq_ex2_stq_val(xu1_lq_ex2_stq_val), + .xu1_lq_ex2_stq_itag(xu1_lq_ex2_stq_itag), + .xu1_lq_ex2_stq_size(xu1_lq_ex2_stq_size), + .xu1_lq_ex3_illeg_lswx(xu1_lq_ex3_illeg_lswx), + .xu1_lq_ex3_strg_noop(xu1_lq_ex3_strg_noop), + .xu1_iu_execute_vld(xu1_iu_execute_vld), + .xu1_iu_itag(xu1_iu_itag), + .xu_iu_ucode_xer_val(xu_iu_ucode_xer_val), + .xu1_pc_ram_done(xu1_pc_ram_done), + .dec_alu_ex1_act(dec_alu_ex1_act), + .dec_alu_ex1_instr(dec_alu_ex1_instr), + .dec_alu_ex1_sel_isel(dec_alu_ex1_sel_isel), + .dec_alu_ex1_add_rs1_inv(dec_alu_ex1_add_rs1_inv), + .dec_alu_ex2_add_ci_sel(dec_alu_ex2_add_ci_sel), + .dec_alu_ex1_sel_trap(dec_alu_ex1_sel_trap), + .dec_alu_ex1_sel_cmpl(dec_alu_ex1_sel_cmpl), + .dec_alu_ex1_sel_cmp(dec_alu_ex1_sel_cmp), + .dec_alu_ex1_msb_64b_sel(dec_alu_ex1_msb_64b_sel), + .dec_alu_ex1_xer_ov_en(dec_alu_ex1_xer_ov_en), + .dec_alu_ex1_xer_ca_en(dec_alu_ex1_xer_ca_en), + .xu1_xu0_ex3_act(xu1_xu0_ex3_act), + .dec_byp_ex0_act(dec_byp_ex0_act), + .byp_dec_ex2_abort(byp_dec_ex2_abort), + .dec_byp_ex1_imm(dec_byp_ex1_imm), + .dec_byp_ex1_instr(dec_byp_ex1_instr), + .dec_byp_ex0_rs2_sel_imm(dec_byp_ex0_rs2_sel_imm), + .dec_byp_ex0_rs1_sel_zero(dec_byp_ex0_rs1_sel_zero), + .dec_byp_ex2_tid(dec_byp_ex2_tid), + .dec_byp_ex2_dvc_mask(dec_byp_ex2_dvc_mask), + .byp_dec_ex2_xer(byp_dec_ex2_xer), + .xu1_gpr_ex3_we(xu1_gpr_ex3_we), + .xu1_gpr_ex3_wa(xu1_gpr_ex3_wa), + .xu1_xer_ex3_we(xu1_xer_ex3_we), + .xu1_xer_ex3_wa(xu1_xer_ex3_wa), + .xu1_cr_ex3_we(xu1_cr_ex3_we), + .xu1_cr_ex3_wa(xu1_cr_ex3_wa), + .pc_xu_ram_active(pc_xu_ram_active) + ); + + assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in}; + assign scan_out = sov[0]; + +endmodule diff --git a/dev/verilog/work/xu1_byp.v b/dev/verilog/work/xu1_byp.v new file mode 100755 index 0000000..2ce0e39 --- /dev/null +++ b/dev/verilog/work/xu1_byp.v @@ -0,0 +1,1368 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" + +module xu1_byp( + //------------------------------------------------------------------- + // Clocks & Power + //------------------------------------------------------------------- + input [0:`NCLK_WIDTH-1] nclk, + inout vdd, + inout gnd, + + //------------------------------------------------------------------- + // Pervasive + //------------------------------------------------------------------- + input d_mode_dc, + input [0:0] delay_lclkr_dc, + input [0:0] mpw1_dc_b, + input mpw2_dc_b, + input func_sl_force, + input func_sl_thold_0_b, + input sg_0, + input scan_in, + output scan_out, + + //------------------------------------------------------------------- + // Decode Interface + //------------------------------------------------------------------- + input dec_byp_ex0_act, + input xu0_xu1_ex3_act, + input lq_xu_ex5_act, + + input [64-`GPR_WIDTH:63] dec_byp_ex1_imm, + + input [0:`THREADS-1] dec_byp_ex2_tid, + input [(64-`GPR_WIDTH)/8:7] dec_byp_ex2_dvc_mask, + input [24:25] dec_byp_ex1_instr, + + input dec_byp_ex0_rs2_sel_imm, + input dec_byp_ex0_rs1_sel_zero, + + //------------------------------------------------------------------- + // RV + //------------------------------------------------------------------- + input rv_xu1_s1_v, + input rv_xu1_s2_v, + input rv_xu1_s3_v, + + //------------------------------------------------------------------- + // Interface with Bypass Controller + //------------------------------------------------------------------- + input [1:11] rv_xu1_s1_fxu0_sel, + input [1:11] rv_xu1_s2_fxu0_sel, + input [2:11] rv_xu1_s3_fxu0_sel, + input [1:6] rv_xu1_s1_fxu1_sel, + input [1:6] rv_xu1_s2_fxu1_sel, + input [2:6] rv_xu1_s3_fxu1_sel, + input [4:8] rv_xu1_s1_lq_sel, + input [4:8] rv_xu1_s2_lq_sel, + input [4:8] rv_xu1_s3_lq_sel, + input [2:3] rv_xu1_s1_rel_sel, + input [2:3] rv_xu1_s2_rel_sel, + + //------------------------------------------------------------------- + // Bypass Inputs + //------------------------------------------------------------------- + // Regfile Data + input [64-`GPR_WIDTH:63] gpr_xu1_ex1_r1d, + input [64-`GPR_WIDTH:63] gpr_xu1_ex1_r2d, + input [0:9] xer_xu1_ex1_r3d, + input [0:3] cr_xu1_ex1_r3d, + + // External Bypass + input xu0_xu1_ex2_abort, + input xu0_xu1_ex6_abort, + input [64-`GPR_WIDTH:63] xu0_xu1_ex2_rt, + input [64-`GPR_WIDTH:63] xu0_xu1_ex3_rt, + input [64-`GPR_WIDTH:63] xu0_xu1_ex4_rt, + input [64-`GPR_WIDTH:63] xu0_xu1_ex5_rt, + input [64-`GPR_WIDTH:63] xu0_xu1_ex6_rt, + input [64-`GPR_WIDTH:63] xu0_xu1_ex7_rt, + input [64-`GPR_WIDTH:63] xu0_xu1_ex8_rt, + input [64-`GPR_WIDTH:63] xu0_xu1_ex6_lq_rt, + input [64-`GPR_WIDTH:63] xu0_xu1_ex7_lq_rt, + input [64-`GPR_WIDTH:63] xu0_xu1_ex8_lq_rt, + + input lq_xu_ex5_abort, + input [64-`GPR_WIDTH:63] lq_xu_ex5_rt, + input [64-`GPR_WIDTH:63] lq_xu_rel_rt, + input lq_xu_rel_act, + + // CR + input [0:3] lq_xu_ex5_cr, + input [0:3] xu0_xu1_ex3_cr, + input [0:3] xu0_xu1_ex4_cr, + input [0:3] xu0_xu1_ex6_cr, + // XER + input [0:9] xu0_xu1_ex3_xer, + input [0:9] xu0_xu1_ex4_xer, + input [0:9] xu0_xu1_ex6_xer, + + // Internal Bypass + input [64-`GPR_WIDTH:63] alu_byp_ex2_add_rt, + input [64-`GPR_WIDTH:63] alu_byp_ex3_rt, + // CR + input [0:3] alu_byp_ex3_cr, + // XER + input [0:9] alu_byp_ex3_xer, + + //------------------------------------------------------------------- + // Bypass Outputs + //------------------------------------------------------------------- + output xu1_xu0_ex2_abort, + output xu1_lq_ex3_abort, + output [64-`GPR_WIDTH:63] xu1_xu0_ex2_rt, + output [64-`GPR_WIDTH:63] xu1_xu0_ex3_rt, + output [64-`GPR_WIDTH:63] xu1_xu0_ex4_rt, + output [64-`GPR_WIDTH:63] xu1_xu0_ex5_rt, + output [64-`GPR_WIDTH:63] xu1_lq_ex3_rt, + output [64-`GPR_WIDTH:63] xu1_pc_ram_data, + + // CR + output [0:3] xu1_xu0_ex3_cr, + + // XER + output [0:9] xu1_xu0_ex3_xer, + + //------------------------------------------------------------------- + // Source Outputs + //------------------------------------------------------------------- + output [64-`GPR_WIDTH:63] byp_alu_ex2_rs1, // Source Data + output [64-`GPR_WIDTH:63] byp_alu_ex2_rs2, + + output byp_alu_ex2_cr_bit, // CR bit for isel + output [0:9] byp_alu_ex2_xer, + output [3:9] byp_dec_ex2_xer, + + output [3:9] xu_iu_ucode_xer, + + output xu1_rv_ex2_s1_abort, + output xu1_rv_ex2_s2_abort, + output xu1_rv_ex2_s3_abort, + output byp_dec_ex2_abort, + + //------------------------------------------------------------------- + // Target Outputs + //------------------------------------------------------------------- + output [64-`GPR_WIDTH:65+`GPR_WIDTH/8] xu1_gpr_ex3_wd, + output [0:9] xu1_xer_ex3_w0d, + output [0:3] xu1_cr_ex3_w0d, + + output [(64-`GPR_WIDTH)/8:7] xu1_lq_ex2_stq_dvc1_cmp, + output [(64-`GPR_WIDTH)/8:7] xu1_lq_ex2_stq_dvc2_cmp, + //------------------------------------------------------------------- + // SPR + //------------------------------------------------------------------- + `ifndef THREADS1 + input [64-`GPR_WIDTH:63] spr_dvc1_t1, + input [64-`GPR_WIDTH:63] spr_dvc2_t1, + `endif + input [64-`GPR_WIDTH:63] spr_dvc1_t0, + input [64-`GPR_WIDTH:63] spr_dvc2_t0 +); + + localparam DEX0 = 0; + localparam DEX1 = 0; + localparam DEX2 = 0; + localparam DEX3 = 0; + localparam DEX4 = 0; + localparam DEX5 = 0; + localparam DEX6 = 0; + localparam DWR = 0; + localparam DX = 0; + // Latches + wire [4:7] exx_xu0_act_q, exx_xu0_act_d ; // input=>exx_xu0_act_d ,act=>1'b1 + wire [1:6] exx_xu1_act_q, exx_xu1_act_d ; // input=>exx_xu1_act_d ,act=>1'b1 + wire [6:8] exx_lq_act_q, exx_lq_act_d ; // input=>exx_lq_act_d ,act=>1'b1 + wire ex0_s1_v_q ; // input=>rv_xu1_s1_v ,act=>1'b1 + wire ex0_s2_v_q ; // input=>rv_xu1_s2_v ,act=>1'b1 + wire ex0_s3_v_q ; // input=>rv_xu1_s3_v ,act=>1'b1 + wire ex1_s1_v_q ; // input=>ex0_s1_v_q ,act=>1'b1 + wire ex1_s2_v_q ; // input=>ex0_s2_v_q ,act=>1'b1 + wire ex1_s3_v_q ; // input=>ex0_s3_v_q ,act=>1'b1 + wire [0:7] ex1_gpr_s1_xu0_sel_q[2:8] ; // input=>{8{ex0_gpr_s1_xu0_sel[i-1]}} ,act=>exx_xu1_act[0] + wire [0:7] ex1_gpr_s2_xu0_sel_q[2:8] ; // input=>{8{ex0_gpr_s2_xu0_sel[i-1]}} ,act=>exx_xu1_act[0] + wire [0:7] ex1_gpr_s1_xu1_sel_q[2:5] ; // input=>{8{ex0_gpr_s1_xu1_sel[i-1]}} ,act=>exx_xu1_act[0] + wire [0:7] ex1_gpr_s2_xu1_sel_q[2:5] ; // input=>{8{ex0_gpr_s2_xu1_sel[i-1]}} ,act=>exx_xu1_act[0] + wire [0:7] ex1_gpr_s1_lq_sel_q[5:8] ; // input=>{8{ex0_gpr_s1_lq_sel[i-1]}} ,act=>exx_xu1_act[0] + wire [0:7] ex1_gpr_s2_lq_sel_q[5:8] ; // input=>{8{ex0_gpr_s2_lq_sel[i-1]}} ,act=>exx_xu1_act[0] + wire [0:7] ex1_gpr_s2_imm_sel_q ; // input=>{8{dec_byp_ex0_rs2_sel_imm}} ,act=>exx_xu1_act[0] + wire [0:0] ex1_spr_s3_xu0_sel_q[3:8] ; // input=>rv_xu1_s3_fxu0_sel[i-1] ,act=>exx_xu1_act[0] + wire [0:0] ex1_spr_s3_xu1_sel_q[3:5] ; // input=>rv_xu1_s3_fxu1_sel[i-1] ,act=>exx_xu1_act[0] + wire [0:0] ex1_spr_s3_lq_sel_q[5:6] ; // input=>rv_xu1_s3_lq_sel[i-1] ,act=>exx_xu1_act[0] + wire [0:7] ex1_gpr_s1_rel_sel_q[3:4] ; // input=>{8{ex0_gpr_s1_rel_sel[i-1]}} ,act=>exx_xu1_act[0] + wire [0:7] ex1_gpr_s2_rel_sel_q[3:4] ; // input=>{8{ex0_gpr_s2_rel_sel[i-1]}} ,act=>exx_xu1_act[0] + wire [0:7] ex1_gpr_s1_reg_sel_q ; // input=>{8{ex0_gpr_s1_reg_sel}} ,act=>exx_xu1_act[0] + wire [0:7] ex1_gpr_s2_reg_sel_q ; // input=>{8{ex0_gpr_s2_reg_sel}} ,act=>exx_xu1_act[0] + wire [0:1] ex1_spr_s3_reg_sel_q ; // input=>{2{ex0_spr_s3_reg_sel}} ,act=>exx_xu1_act[0] + wire [9:9] ex1_abt_s1_lq_sel_q ; // input=>ex0_gpr_s1_lq_sel[8] ,act=>exx_xu1_act[0] + wire [9:9] ex1_abt_s2_lq_sel_q ; // input=>ex0_gpr_s2_lq_sel[8] ,act=>exx_xu1_act[0] + wire [7:9] ex1_abt_s3_lq_sel_q ; // input=>rv_xu1_s3_lq_sel[6:8] ,act=>exx_xu1_act[0] + wire [6:7] ex1_abt_s1_xu1_sel_q ; // input=>ex0_gpr_s1_xu1_sel[5:6] ,act=>exx_xu1_act[0] + wire [6:7] ex1_abt_s2_xu1_sel_q ; // input=>ex0_gpr_s2_xu1_sel[5:6] ,act=>exx_xu1_act[0] + wire [6:7] ex1_abt_s3_xu1_sel_q ; // input=>rv_xu1_s3_fxu1_sel[5:6] ,act=>exx_xu1_act[0] + wire [9:12] ex1_abt_s1_xu0_sel_q ; // input=>ex0_gpr_s1_xu0_sel[8:11] ,act=>exx_xu1_act[0] + wire [9:12] ex1_abt_s2_xu0_sel_q ; // input=>ex0_gpr_s2_xu0_sel[8:11] ,act=>exx_xu1_act[0] + wire [9:12] ex1_abt_s3_xu0_sel_q ; // input=>rv_xu1_s3_fxu0_sel[8:11] ,act=>exx_xu1_act[0] + wire [64-`GPR_WIDTH:63] ex4_xu1_rt_q ; // input=>alu_byp_ex3_rt ,act=>exx_xu1_act[3] + wire [64-`GPR_WIDTH:63] ex5_xu1_rt_q ; // input=>ex4_xu1_rt_q ,act=>exx_xu1_act[4] + wire [0:3] ex5_xu0_cr_q ; // input=>xu0_xu1_ex4_cr ,act=>exx_xu0_act[4] +// wire [0:3] ex6_xu0_cr_q ; // input=>ex5_xu0_cr_q ,act=>exx_xu0_act[5] + wire [0:3] ex6_lq_cr_q ; // input=>lq_xu_ex5_cr ,act=>exx_lq_act[5] + wire [0:9] ex5_xu0_xer_q ; // input=>xu0_xu1_ex4_xer ,act=>exx_xu0_act[4] +// wire [0:9] ex6_xu0_xer_q ; // input=>ex5_xu0_xer_q ,act=>exx_xu0_act[5] + wire [64-`GPR_WIDTH:63] ex2_rs1_q, ex1_rs1 ; // input=>ex1_rs1 ,act=>exx_xu1_act[1] + wire [64-`GPR_WIDTH:63] ex2_rs2_q, ex1_rs2 ; // input=>ex1_rs2 ,act=>exx_xu1_act[1] + wire ex2_cr_bit_q, ex1_cr_bit ; // input=>ex1_cr_bit ,act=>exx_xu1_act[1] + wire [0:9] ex2_xer3_q, ex1_xer3 ; // input=>ex1_xer3 ,act=>exx_xu1_act[1] + wire [3:12] exx_xu0_abort_q, exx_xu0_abort_d ; // input=>exx_xu0_abort_d ,act=>1'b1 + wire [2:7] exx_xu1_abort_q, exx_xu1_abort_d ; // input=>exx_xu1_abort_d ,act=>1'b1 + wire [6:9] exx_lq_abort_q, exx_lq_abort_d ; // input=>exx_lq_abort_d ,act=>1'b1 + wire ex2_rs1_abort_q ; // input=>ex1_rs1_abort ,act=>1'b1 + wire ex2_rs2_abort_q ; // input=>ex1_rs2_abort ,act=>1'b1 + wire ex2_rs3_abort_q ; // input=>ex1_rs3_abort ,act=>1'b1 + wire exx_rel3_act_q ; // input=>lq_xu_rel_act ,act=>1'b1 + wire [64-`GPR_WIDTH:63] exx_rel3_rt_q ; // input=>lq_xu_rel_rt ,act=>lq_xu_rel_act + wire [64-`GPR_WIDTH:63] exx_rel4_rt_q ; // input=>exx_rel3_rt_q ,act=>exx_rel3_act_q + localparam exx_xu0_act_offset = 0; + localparam exx_xu1_act_offset = exx_xu0_act_offset + 4; + localparam exx_lq_act_offset = exx_xu1_act_offset + 6; + localparam ex0_s1_v_offset = exx_lq_act_offset + 3; + localparam ex0_s2_v_offset = ex0_s1_v_offset + 1; + localparam ex0_s3_v_offset = ex0_s2_v_offset + 1; + localparam ex1_s1_v_offset = ex0_s3_v_offset + 1; + localparam ex1_s2_v_offset = ex1_s1_v_offset + 1; + localparam ex1_s3_v_offset = ex1_s2_v_offset + 1; + localparam ex1_gpr_s1_xu0_sel_offset = ex1_s3_v_offset + 1; + localparam ex1_gpr_s2_xu0_sel_offset = ex1_gpr_s1_xu0_sel_offset + 8*7; + localparam ex1_gpr_s1_xu1_sel_offset = ex1_gpr_s2_xu0_sel_offset + 8*7; + localparam ex1_gpr_s2_xu1_sel_offset = ex1_gpr_s1_xu1_sel_offset + 8*4; + localparam ex1_gpr_s1_lq_sel_offset = ex1_gpr_s2_xu1_sel_offset + 8*4; + localparam ex1_gpr_s2_lq_sel_offset = ex1_gpr_s1_lq_sel_offset + 8*4; + localparam ex1_gpr_s2_imm_sel_offset = ex1_gpr_s2_lq_sel_offset + 8*4; + localparam ex1_spr_s3_xu0_sel_offset = ex1_gpr_s2_imm_sel_offset + 8; + localparam ex1_spr_s3_xu1_sel_offset = ex1_spr_s3_xu0_sel_offset + 1*6; + localparam ex1_spr_s3_lq_sel_offset = ex1_spr_s3_xu1_sel_offset + 1*3; + localparam ex1_gpr_s1_rel_sel_offset = ex1_spr_s3_lq_sel_offset + 1*2; + localparam ex1_gpr_s2_rel_sel_offset = ex1_gpr_s1_rel_sel_offset + 8*2; + localparam ex1_gpr_s1_reg_sel_offset = ex1_gpr_s2_rel_sel_offset + 8*2; + localparam ex1_gpr_s2_reg_sel_offset = ex1_gpr_s1_reg_sel_offset + 8; + localparam ex1_spr_s3_reg_sel_offset = ex1_gpr_s2_reg_sel_offset + 8; + localparam ex1_abt_s1_lq_sel_offset = ex1_spr_s3_reg_sel_offset + 2; + localparam ex1_abt_s2_lq_sel_offset = ex1_abt_s1_lq_sel_offset + 1; + localparam ex1_abt_s3_lq_sel_offset = ex1_abt_s2_lq_sel_offset + 1; + localparam ex1_abt_s1_xu1_sel_offset = ex1_abt_s3_lq_sel_offset + 3; + localparam ex1_abt_s2_xu1_sel_offset = ex1_abt_s1_xu1_sel_offset + 2; + localparam ex1_abt_s3_xu1_sel_offset = ex1_abt_s2_xu1_sel_offset + 2; + localparam ex1_abt_s1_xu0_sel_offset = ex1_abt_s3_xu1_sel_offset + 2; + localparam ex1_abt_s2_xu0_sel_offset = ex1_abt_s1_xu0_sel_offset + 4; + localparam ex1_abt_s3_xu0_sel_offset = ex1_abt_s2_xu0_sel_offset + 4; + localparam ex4_xu1_rt_offset = ex1_abt_s3_xu0_sel_offset + 4; + localparam ex5_xu1_rt_offset = ex4_xu1_rt_offset + `GPR_WIDTH; + localparam ex5_xu0_cr_offset = ex5_xu1_rt_offset + `GPR_WIDTH; + localparam ex6_lq_cr_offset = ex5_xu0_cr_offset + 4; + localparam ex5_xu0_xer_offset = ex6_lq_cr_offset + 4; + localparam ex2_rs1_offset = ex5_xu0_xer_offset + 10; + localparam ex2_rs2_offset = ex2_rs1_offset + `GPR_WIDTH; + localparam ex2_cr_bit_offset = ex2_rs2_offset + `GPR_WIDTH; + localparam ex2_xer3_offset = ex2_cr_bit_offset + 1; + localparam exx_xu0_abort_offset = ex2_xer3_offset + 10; + localparam exx_xu1_abort_offset = exx_xu0_abort_offset + 10; + localparam exx_lq_abort_offset = exx_xu1_abort_offset + 6; + localparam ex2_rs1_abort_offset = exx_lq_abort_offset + 4; + localparam ex2_rs2_abort_offset = ex2_rs1_abort_offset + 1; + localparam ex2_rs3_abort_offset = ex2_rs2_abort_offset + 1; + localparam exx_rel3_act_offset = ex2_rs3_abort_offset + 1; + localparam exx_rel3_rt_offset = exx_rel3_act_offset + 1; + localparam exx_rel4_rt_offset = exx_rel3_rt_offset + `GPR_WIDTH; + localparam scan_right = exx_rel4_rt_offset + `GPR_WIDTH; + wire [0:scan_right-1] siv; + wire [0:scan_right-1] sov; + // Signals + wire [0:6] exx_xu1_act; + wire [3:7] exx_xu0_act; + wire [5:8] exx_lq_act; + wire [1:11] ex0_gpr_s1_xu0_sel; + wire [1:11] ex0_gpr_s2_xu0_sel; + wire [1:6] ex0_gpr_s1_xu1_sel; + wire [1:6] ex0_gpr_s2_xu1_sel; + wire [4:8] ex0_gpr_s1_lq_sel; + wire [4:8] ex0_gpr_s2_lq_sel; + wire [2:3] ex0_gpr_s1_rel_sel; + wire [2:3] ex0_gpr_s2_rel_sel; + wire ex0_gpr_rs2_sel_imm_b; + wire ex0_gpr_rs1_sel_zero_b; + wire ex0_gpr_s1_reg_sel; + wire ex0_gpr_s2_reg_sel; + wire ex0_spr_s3_reg_sel; + wire [0:3] ex1_cr3; + wire [64-`GPR_WIDTH:63] ex1_rs2_noimm; + wire [8-`GPR_WIDTH/8:7] ex3_parity; + wire [8-`GPR_WIDTH/8:7] ex2_stq_dvc1_t0_cmpr; + wire [8-`GPR_WIDTH/8:7] ex2_stq_dvc2_t0_cmpr; + wire [8-`GPR_WIDTH/8:7] ex2_stq_dvc1_t1_cmpr; + wire [8-`GPR_WIDTH/8:7] ex2_stq_dvc2_t1_cmpr; + wire ex1_abort; + wire ex1_rs1_abort, ex1_rs2_noimm_abort; + wire ex1_rs2_abort; + wire ex1_rs3_abort; + + (* analysis_not_referenced="<8:63>true" *) + wire [0:63] tidn = 64'b0; + + //------------------------------------------------------------------------------------------ + // Zero/Immediate Logic for GPRs + //------------------------------------------------------------------------------------------ + assign ex0_gpr_s1_xu0_sel = ex0_gpr_rs1_sel_zero_b==1'b1 ? rv_xu1_s1_fxu0_sel : tidn[1:11]; + assign ex0_gpr_s1_xu1_sel = ex0_gpr_rs1_sel_zero_b==1'b1 ? rv_xu1_s1_fxu1_sel : tidn[1:6]; + assign ex0_gpr_s1_lq_sel = ex0_gpr_rs1_sel_zero_b==1'b1 ? rv_xu1_s1_lq_sel : tidn[4:8]; + assign ex0_gpr_s1_rel_sel = ex0_gpr_rs1_sel_zero_b==1'b1 ? rv_xu1_s1_rel_sel : tidn[2:3]; + + assign ex0_gpr_s2_xu0_sel = rv_xu1_s2_fxu0_sel; + assign ex0_gpr_s2_xu1_sel = rv_xu1_s2_fxu1_sel; + assign ex0_gpr_s2_lq_sel = rv_xu1_s2_lq_sel ; + assign ex0_gpr_s2_rel_sel = rv_xu1_s2_rel_sel ; + + // TEMP Hopefully fold this into rf_byp + assign ex0_gpr_s1_reg_sel = ~|rv_xu1_s1_fxu0_sel[1:7] & ~|rv_xu1_s1_fxu1_sel[1:4] & ~|rv_xu1_s1_lq_sel[4:7] & ~|rv_xu1_s1_rel_sel & ex0_gpr_rs1_sel_zero_b; + assign ex0_gpr_s2_reg_sel = ~|rv_xu1_s2_fxu0_sel[1:7] & ~|rv_xu1_s2_fxu1_sel[1:4] & ~|rv_xu1_s2_lq_sel[4:7] & ~|rv_xu1_s2_rel_sel; + assign ex0_spr_s3_reg_sel = ~|rv_xu1_s3_fxu0_sel[2:5] & ~|rv_xu1_s3_fxu1_sel[2:2] & ~|rv_xu1_s3_lq_sel[4:5]; + + assign ex0_gpr_rs2_sel_imm_b = ~dec_byp_ex0_rs2_sel_imm; + assign ex0_gpr_rs1_sel_zero_b = ~dec_byp_ex0_rs1_sel_zero; + + //------------------------------------------------------------------------------------------ + // GPR Bypass + //------------------------------------------------------------------------------------------ + assign ex1_rs1 = (alu_byp_ex2_add_rt & fanout(ex1_gpr_s1_xu1_sel_q[2], `GPR_WIDTH)) | + (alu_byp_ex3_rt & fanout(ex1_gpr_s1_xu1_sel_q[3], `GPR_WIDTH)) | + (ex4_xu1_rt_q & fanout(ex1_gpr_s1_xu1_sel_q[4], `GPR_WIDTH)) | + (ex5_xu1_rt_q & fanout(ex1_gpr_s1_xu1_sel_q[5], `GPR_WIDTH)) | + (xu0_xu1_ex2_rt & fanout(ex1_gpr_s1_xu0_sel_q[2], `GPR_WIDTH)) | + (xu0_xu1_ex3_rt & fanout(ex1_gpr_s1_xu0_sel_q[3], `GPR_WIDTH)) | + (xu0_xu1_ex4_rt & fanout(ex1_gpr_s1_xu0_sel_q[4], `GPR_WIDTH)) | + (xu0_xu1_ex5_rt & fanout(ex1_gpr_s1_xu0_sel_q[5], `GPR_WIDTH)) | + (xu0_xu1_ex6_rt & fanout(ex1_gpr_s1_xu0_sel_q[6], `GPR_WIDTH)) | + (xu0_xu1_ex7_rt & fanout(ex1_gpr_s1_xu0_sel_q[7], `GPR_WIDTH)) | + (xu0_xu1_ex8_rt & fanout(ex1_gpr_s1_xu0_sel_q[8], `GPR_WIDTH)) | + (lq_xu_ex5_rt & fanout(ex1_gpr_s1_lq_sel_q[5], `GPR_WIDTH)) | + (xu0_xu1_ex6_lq_rt & fanout(ex1_gpr_s1_lq_sel_q[6], `GPR_WIDTH)) | + (xu0_xu1_ex7_lq_rt & fanout(ex1_gpr_s1_lq_sel_q[7], `GPR_WIDTH)) | + (xu0_xu1_ex8_lq_rt & fanout(ex1_gpr_s1_lq_sel_q[8], `GPR_WIDTH)) | + (exx_rel3_rt_q & fanout(ex1_gpr_s1_rel_sel_q[3], `GPR_WIDTH)) | + (exx_rel4_rt_q & fanout(ex1_gpr_s1_rel_sel_q[4], `GPR_WIDTH)) | + (gpr_xu1_ex1_r1d & fanout(ex1_gpr_s1_reg_sel_q, `GPR_WIDTH)); + + + assign ex1_rs2 = (dec_byp_ex1_imm & fanout(ex1_gpr_s2_imm_sel_q, `GPR_WIDTH)) | + (ex1_rs2_noimm & (~fanout(ex1_gpr_s2_imm_sel_q, `GPR_WIDTH))); + + assign ex1_rs2_noimm = + (alu_byp_ex2_add_rt & fanout(ex1_gpr_s2_xu1_sel_q[2], `GPR_WIDTH)) | + (alu_byp_ex3_rt & fanout(ex1_gpr_s2_xu1_sel_q[3], `GPR_WIDTH)) | + (ex4_xu1_rt_q & fanout(ex1_gpr_s2_xu1_sel_q[4], `GPR_WIDTH)) | + (ex5_xu1_rt_q & fanout(ex1_gpr_s2_xu1_sel_q[5], `GPR_WIDTH)) | + (xu0_xu1_ex2_rt & fanout(ex1_gpr_s2_xu0_sel_q[2], `GPR_WIDTH)) | + (xu0_xu1_ex3_rt & fanout(ex1_gpr_s2_xu0_sel_q[3], `GPR_WIDTH)) | + (xu0_xu1_ex4_rt & fanout(ex1_gpr_s2_xu0_sel_q[4], `GPR_WIDTH)) | + (xu0_xu1_ex5_rt & fanout(ex1_gpr_s2_xu0_sel_q[5], `GPR_WIDTH)) | + (xu0_xu1_ex6_rt & fanout(ex1_gpr_s2_xu0_sel_q[6], `GPR_WIDTH)) | + (xu0_xu1_ex7_rt & fanout(ex1_gpr_s2_xu0_sel_q[7], `GPR_WIDTH)) | + (xu0_xu1_ex8_rt & fanout(ex1_gpr_s2_xu0_sel_q[8], `GPR_WIDTH)) | + (lq_xu_ex5_rt & fanout(ex1_gpr_s2_lq_sel_q[5], `GPR_WIDTH)) | + (xu0_xu1_ex6_lq_rt & fanout(ex1_gpr_s2_lq_sel_q[6], `GPR_WIDTH)) | + (xu0_xu1_ex7_lq_rt & fanout(ex1_gpr_s2_lq_sel_q[7], `GPR_WIDTH)) | + (xu0_xu1_ex8_lq_rt & fanout(ex1_gpr_s2_lq_sel_q[8], `GPR_WIDTH)) | + (exx_rel3_rt_q & fanout(ex1_gpr_s2_rel_sel_q[3], `GPR_WIDTH)) | + (exx_rel4_rt_q & fanout(ex1_gpr_s2_rel_sel_q[4], `GPR_WIDTH)) | + (gpr_xu1_ex1_r2d & fanout(ex1_gpr_s2_reg_sel_q, `GPR_WIDTH)); + + + + //------------------------------------------------------------------------------------------ + // Abort Bypass + //------------------------------------------------------------------------------------------ + assign exx_xu0_abort_d[3:6] = {xu0_xu1_ex2_abort, exx_xu0_abort_q[3:5]}; + assign exx_xu0_abort_d[7] = xu0_xu1_ex6_abort; + assign exx_xu0_abort_d[8:12] = exx_xu0_abort_q[7:11]; + + assign exx_xu1_abort_d = {ex1_abort, exx_xu1_abort_q[2:6]}; + assign exx_lq_abort_d = {lq_xu_ex5_abort, exx_lq_abort_q[6:8]}; + + assign ex1_abort = ex1_rs1_abort | ex1_rs2_abort | ex1_rs3_abort; + + assign ex1_rs1_abort = exx_xu1_act[1] & ex1_s1_v_q & + ((exx_xu1_abort_q[2] & ex1_gpr_s1_xu1_sel_q[2][0]) | + (exx_xu1_abort_q[3] & ex1_gpr_s1_xu1_sel_q[3][0]) | + (exx_xu1_abort_q[4] & ex1_gpr_s1_xu1_sel_q[4][0]) | + (exx_xu1_abort_q[5] & ex1_gpr_s1_xu1_sel_q[5][0]) | + (exx_xu1_abort_q[6] & ex1_abt_s1_xu1_sel_q[6]) | + (exx_xu1_abort_q[7] & ex1_abt_s1_xu1_sel_q[7]) | + (xu0_xu1_ex2_abort & ex1_gpr_s1_xu0_sel_q[2][0]) | + (exx_xu0_abort_q[3] & ex1_gpr_s1_xu0_sel_q[3][0]) | + (exx_xu0_abort_q[4] & ex1_gpr_s1_xu0_sel_q[4][0]) | + (exx_xu0_abort_q[5] & ex1_gpr_s1_xu0_sel_q[5][0]) | + (xu0_xu1_ex6_abort & ex1_gpr_s1_xu0_sel_q[6][0]) | //mul abort + (exx_xu0_abort_q[7] & ex1_gpr_s1_xu0_sel_q[7][0]) | + (exx_xu0_abort_q[8] & ex1_gpr_s1_xu0_sel_q[8][0]) | + (exx_xu0_abort_q[9] & ex1_abt_s1_xu0_sel_q[9] ) | + (exx_xu0_abort_q[10] & ex1_abt_s1_xu0_sel_q[10] ) | + (exx_xu0_abort_q[11] & ex1_abt_s1_xu0_sel_q[11] ) | + (exx_xu0_abort_q[12] & ex1_abt_s1_xu0_sel_q[12] ) | + (lq_xu_ex5_abort & ex1_gpr_s1_lq_sel_q[5][0]) | + (exx_lq_abort_q[6] & ex1_gpr_s1_lq_sel_q[6][0]) | + (exx_lq_abort_q[7] & ex1_gpr_s1_lq_sel_q[7][0]) | + (exx_lq_abort_q[8] & ex1_gpr_s1_lq_sel_q[8][0]) | + (exx_lq_abort_q[9] & ex1_abt_s1_lq_sel_q[9] )); + + assign ex1_rs2_abort = exx_xu1_act[1] & ex1_s2_v_q & + (ex1_rs2_noimm_abort); + + assign ex1_rs2_noimm_abort = + (exx_xu1_abort_q[2] & ex1_gpr_s2_xu1_sel_q[2][0]) | + (exx_xu1_abort_q[3] & ex1_gpr_s2_xu1_sel_q[3][0]) | + (exx_xu1_abort_q[4] & ex1_gpr_s2_xu1_sel_q[4][0]) | + (exx_xu1_abort_q[5] & ex1_gpr_s2_xu1_sel_q[5][0]) | + (exx_xu1_abort_q[6] & ex1_abt_s2_xu1_sel_q[6]) | + (exx_xu1_abort_q[7] & ex1_abt_s2_xu1_sel_q[7]) | + (xu0_xu1_ex2_abort & ex1_gpr_s2_xu0_sel_q[2][0]) | + (exx_xu0_abort_q[3] & ex1_gpr_s2_xu0_sel_q[3][0]) | + (exx_xu0_abort_q[4] & ex1_gpr_s2_xu0_sel_q[4][0]) | + (exx_xu0_abort_q[5] & ex1_gpr_s2_xu0_sel_q[5][0]) | + (xu0_xu1_ex6_abort & ex1_gpr_s2_xu0_sel_q[6][0]) | + (exx_xu0_abort_q[7] & ex1_gpr_s2_xu0_sel_q[7][0]) | + (exx_xu0_abort_q[8] & ex1_gpr_s2_xu0_sel_q[8][0]) | + (exx_xu0_abort_q[9] & ex1_abt_s2_xu0_sel_q[9] ) | + (exx_xu0_abort_q[10] & ex1_abt_s2_xu0_sel_q[10] ) | + (exx_xu0_abort_q[11] & ex1_abt_s2_xu0_sel_q[11] ) | + (exx_xu0_abort_q[12] & ex1_abt_s2_xu0_sel_q[12] ) | + (lq_xu_ex5_abort & ex1_gpr_s2_lq_sel_q[5][0]) | + (exx_lq_abort_q[6] & ex1_gpr_s2_lq_sel_q[6][0]) | + (exx_lq_abort_q[7] & ex1_gpr_s2_lq_sel_q[7][0]) | + (exx_lq_abort_q[8] & ex1_gpr_s2_lq_sel_q[8][0]) | + (exx_lq_abort_q[9] & ex1_abt_s2_lq_sel_q[9] ); + + + assign ex1_rs3_abort = exx_xu1_act[1] & ex1_s3_v_q & + ((exx_xu1_abort_q[3] & ex1_spr_s3_xu1_sel_q[3]) | + (exx_xu1_abort_q[4] & ex1_spr_s3_xu1_sel_q[4]) | + (exx_xu1_abort_q[5] & ex1_spr_s3_xu1_sel_q[5]) | + (exx_xu1_abort_q[6] & ex1_abt_s3_xu1_sel_q[6]) | + (exx_xu1_abort_q[7] & ex1_abt_s3_xu1_sel_q[7]) | + (exx_xu0_abort_q[3] & ex1_spr_s3_xu0_sel_q[3]) | + (exx_xu0_abort_q[4] & ex1_spr_s3_xu0_sel_q[4]) | + (exx_xu0_abort_q[5] & ex1_spr_s3_xu0_sel_q[5]) | + (xu0_xu1_ex6_abort & ex1_spr_s3_xu0_sel_q[6]) | + (exx_xu0_abort_q[7] & ex1_spr_s3_xu0_sel_q[7]) | + (exx_xu0_abort_q[8] & ex1_spr_s3_xu0_sel_q[8]) | + (exx_xu0_abort_q[9] & ex1_abt_s3_xu0_sel_q[9] ) | + (exx_xu0_abort_q[10] & ex1_abt_s3_xu0_sel_q[10] ) | + (exx_xu0_abort_q[11] & ex1_abt_s3_xu0_sel_q[11] ) | + (exx_xu0_abort_q[12] & ex1_abt_s3_xu0_sel_q[12] ) | + (lq_xu_ex5_abort & ex1_spr_s3_lq_sel_q[5]) | + (exx_lq_abort_q[6] & ex1_spr_s3_lq_sel_q[6]) | + (exx_lq_abort_q[7] & ex1_abt_s3_lq_sel_q[7]) | + (exx_lq_abort_q[8] & ex1_abt_s3_lq_sel_q[8]) | + (exx_lq_abort_q[9] & ex1_abt_s3_lq_sel_q[9]) ); + + //------------------------------------------------------------------------------------------ + // CR Bypass + //------------------------------------------------------------------------------------------ + assign ex1_cr3 = (alu_byp_ex3_cr & {4{ex1_spr_s3_xu1_sel_q[3]}}) | + (xu0_xu1_ex3_cr & {4{ex1_spr_s3_xu0_sel_q[3]}}) | + (xu0_xu1_ex4_cr & {4{ex1_spr_s3_xu0_sel_q[4]}}) | + (ex5_xu0_cr_q & {4{ex1_spr_s3_xu0_sel_q[5]}}) | + (xu0_xu1_ex6_cr & {4{ex1_spr_s3_xu0_sel_q[6]}}) | + (lq_xu_ex5_cr & {4{ex1_spr_s3_lq_sel_q[5]}}) | + (ex6_lq_cr_q & {4{ex1_spr_s3_lq_sel_q[6]}}) | + (cr_xu1_ex1_r3d & {4{ex1_spr_s3_reg_sel_q[0]}}); + + //------------------------------------------------------------------------------------------ + // XER Bypass + //------------------------------------------------------------------------------------------ + assign ex1_cr_bit = (dec_byp_ex1_instr[24:25] == 2'b11) ? ex1_cr3[3] : + (dec_byp_ex1_instr[24:25] == 2'b10) ? ex1_cr3[2] : + (dec_byp_ex1_instr[24:25] == 2'b01) ? ex1_cr3[1] : + ex1_cr3[0]; + + assign ex1_xer3 = + (alu_byp_ex3_xer & {10{ex1_spr_s3_xu1_sel_q[3]}}) | + (xu0_xu1_ex3_xer & {10{ex1_spr_s3_xu0_sel_q[3]}}) | + (xu0_xu1_ex4_xer & {10{ex1_spr_s3_xu0_sel_q[4]}}) | + (ex5_xu0_xer_q & {10{ex1_spr_s3_xu0_sel_q[5]}}) | + (xu0_xu1_ex6_xer & {10{ex1_spr_s3_xu0_sel_q[6]}}) | + (xer_xu1_ex1_r3d & {10{ex1_spr_s3_reg_sel_q[1]}}); + + //------------------------------------------------------------------------------------------ + // Parity Gen + //------------------------------------------------------------------------------------------ + generate begin : ex3ParGen + genvar i; + for (i=8-`GPR_WIDTH/8;i<=7;i=i+1) begin : ex3ParGen + assign ex3_parity[i] = ^(alu_byp_ex3_rt[8*i:8*i+7]); + end + end + endgenerate + + //------------------------------------------------------------------------------------------ + // DVC Compare + //------------------------------------------------------------------------------------------ +`ifdef THREADS1 + + generate begin : dvc_1t + genvar b; + for (b=(64-`GPR_WIDTH)/8;b<=7;b=b+1) begin : dvc_byte + assign ex2_stq_dvc1_t0_cmpr[b] = (spr_dvc1_t0[8*b:8*b+7] == ex2_rs1_q[8*b:8*b+7]); + assign ex2_stq_dvc2_t0_cmpr[b] = (spr_dvc2_t0[8*b:8*b+7] == ex2_rs1_q[8*b:8*b+7]); + + assign xu1_lq_ex2_stq_dvc1_cmp[b] = ex2_stq_dvc1_t0_cmpr[b] & dec_byp_ex2_dvc_mask[b] & dec_byp_ex2_tid[0]; + assign xu1_lq_ex2_stq_dvc2_cmp[b] = ex2_stq_dvc2_t0_cmpr[b] & dec_byp_ex2_dvc_mask[b] & dec_byp_ex2_tid[0]; + end + end + endgenerate + `endif + + +`ifndef THREADS1 +generate begin : dvc_2t + + genvar b; + for (b=(64-`GPR_WIDTH)/8;b<=7;b=b+1) begin : dvc_byte + assign ex2_stq_dvc1_t0_cmpr[b] = (spr_dvc1_t0[8*b:8*b+7] == ex2_rs1_q[8*b:8*b+7]); + assign ex2_stq_dvc2_t0_cmpr[b] = (spr_dvc2_t0[8*b:8*b+7] == ex2_rs1_q[8*b:8*b+7]); + assign ex2_stq_dvc1_t1_cmpr[b] = (spr_dvc1_t1[8*b:8*b+7] == ex2_rs1_q[8*b:8*b+7]); + assign ex2_stq_dvc2_t1_cmpr[b] = (spr_dvc2_t1[8*b:8*b+7] == ex2_rs1_q[8*b:8*b+7]); + + assign xu1_lq_ex2_stq_dvc1_cmp[b] = ((ex2_stq_dvc1_t0_cmpr[b] & dec_byp_ex2_tid[0]) | + (ex2_stq_dvc1_t1_cmpr[b] & dec_byp_ex2_tid[1])) & dec_byp_ex2_dvc_mask[b]; + assign xu1_lq_ex2_stq_dvc2_cmp[b] = ((ex2_stq_dvc2_t0_cmpr[b] & dec_byp_ex2_tid[0]) | + (ex2_stq_dvc2_t1_cmpr[b] & dec_byp_ex2_tid[1])) & dec_byp_ex2_dvc_mask[b]; + end + end + endgenerate +`endif +//------------------------------------------------------------------------------------------ + // IO / Buffering + //------------------------------------------------------------------------------------------ + // GPR + assign byp_alu_ex2_rs1 = ex2_rs1_q; + assign byp_alu_ex2_rs2 = ex2_rs2_q; + assign xu1_gpr_ex3_wd = {alu_byp_ex3_rt, ex3_parity, 2'b01}; + + assign xu1_xu0_ex2_abort = exx_xu1_abort_q[2]; + assign xu1_lq_ex3_abort = exx_xu1_abort_q[3]; + assign xu1_xu0_ex2_rt = alu_byp_ex2_add_rt; + assign xu1_xu0_ex3_rt = alu_byp_ex3_rt; + assign xu1_xu0_ex4_rt = ex4_xu1_rt_q; + assign xu1_xu0_ex5_rt = ex5_xu1_rt_q; + assign xu1_lq_ex3_rt = alu_byp_ex3_rt; + assign xu1_pc_ram_data = alu_byp_ex3_rt; + + // CR + assign byp_alu_ex2_cr_bit = ex2_cr_bit_q; + assign xu1_cr_ex3_w0d = alu_byp_ex3_cr; + assign xu1_xu0_ex3_cr = alu_byp_ex3_cr; + + // XER + assign xu_iu_ucode_xer = ex2_xer3_q[3:9]; + assign byp_alu_ex2_xer = ex2_xer3_q; + assign byp_dec_ex2_xer = ex2_xer3_q[3:9]; + assign xu1_xer_ex3_w0d = alu_byp_ex3_xer; + assign xu1_xu0_ex3_xer = alu_byp_ex3_xer; + + // Abort + assign xu1_rv_ex2_s1_abort = ex2_rs1_abort_q; + assign xu1_rv_ex2_s2_abort = ex2_rs2_abort_q; + assign xu1_rv_ex2_s3_abort = ex2_rs3_abort_q; + assign byp_dec_ex2_abort = ex2_rs1_abort_q | ex2_rs2_abort_q | ex2_rs3_abort_q; + + //------------------------------------------------------------------------------------------ + // Clock Gating + //------------------------------------------------------------------------------------------ + assign exx_xu1_act = {dec_byp_ex0_act, exx_xu1_act_q[1:6]}; + assign exx_xu0_act = {xu0_xu1_ex3_act, exx_xu0_act_q[4:7]}; + assign exx_lq_act = {lq_xu_ex5_act, exx_lq_act_q[6:8]}; + + assign exx_xu1_act_d[1:6] = exx_xu1_act[0:5]; + assign exx_xu0_act_d[4:7] = exx_xu0_act[3:6]; + assign exx_lq_act_d[6:8] = exx_lq_act[5:7]; + + //------------------------------------------------------------------------------------------ + // Latches + //------------------------------------------------------------------------------------------ + tri_rlmreg_p #(.WIDTH(4), .OFFSET(4),.INIT(0), .NEEDS_SRESET(1)) exx_xu0_act_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[exx_xu0_act_offset : exx_xu0_act_offset + 4-1]), + .scout(sov[exx_xu0_act_offset : exx_xu0_act_offset + 4-1]), + .din(exx_xu0_act_d), + .dout(exx_xu0_act_q) + ); + tri_rlmreg_p #(.WIDTH(6), .OFFSET(1),.INIT(0), .NEEDS_SRESET(1)) exx_xu1_act_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[exx_xu1_act_offset : exx_xu1_act_offset + 6-1]), + .scout(sov[exx_xu1_act_offset : exx_xu1_act_offset + 6-1]), + .din(exx_xu1_act_d), + .dout(exx_xu1_act_q) + ); + tri_rlmreg_p #(.WIDTH(3), .OFFSET(6),.INIT(0), .NEEDS_SRESET(1)) exx_lq_act_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[exx_lq_act_offset : exx_lq_act_offset + 3-1]), + .scout(sov[exx_lq_act_offset : exx_lq_act_offset + 3-1]), + .din(exx_lq_act_d), + .dout(exx_lq_act_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_s1_v_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX0]), + .mpw1_b(mpw1_dc_b[DEX0]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_s1_v_offset]), + .scout(sov[ex0_s1_v_offset]), + .din(rv_xu1_s1_v), + .dout(ex0_s1_v_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_s2_v_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX0]), + .mpw1_b(mpw1_dc_b[DEX0]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_s2_v_offset]), + .scout(sov[ex0_s2_v_offset]), + .din(rv_xu1_s2_v), + .dout(ex0_s2_v_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_s3_v_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX0]), + .mpw1_b(mpw1_dc_b[DEX0]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_s3_v_offset]), + .scout(sov[ex0_s3_v_offset]), + .din(rv_xu1_s3_v), + .dout(ex0_s3_v_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_s1_v_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_s1_v_offset]), + .scout(sov[ex1_s1_v_offset]), + .din(ex0_s1_v_q), + .dout(ex1_s1_v_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_s2_v_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_s2_v_offset]), + .scout(sov[ex1_s2_v_offset]), + .din(ex0_s2_v_q), + .dout(ex1_s2_v_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_s3_v_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_s3_v_offset]), + .scout(sov[ex1_s3_v_offset]), + .din(ex0_s3_v_q), + .dout(ex1_s3_v_q) + ); +generate begin : ex1_gpr_s1_xu0_sel_gen + genvar i; + for (i=2;i<=8;i=i+1) begin : ex1_gpr_s1_xu0_sel_entry + tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s1_xu0_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu1_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_gpr_s1_xu0_sel_offset + (i-2)*8 : ex1_gpr_s1_xu0_sel_offset + (i-2+1)*8-1]), + .scout(sov[ex1_gpr_s1_xu0_sel_offset + (i-2)*8 : ex1_gpr_s1_xu0_sel_offset + (i-2+1)*8-1]), + .din({8{ex0_gpr_s1_xu0_sel[i-1]}}), + .dout(ex1_gpr_s1_xu0_sel_q[i]) + ); + end +end +endgenerate +generate begin : ex1_gpr_s2_xu0_sel_gen + genvar i; + for (i=2;i<=8;i=i+1) begin : ex1_gpr_s2_xu0_sel_entry + tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s2_xu0_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu1_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_gpr_s2_xu0_sel_offset + (i-2)*8 : ex1_gpr_s2_xu0_sel_offset + (i-2+1)*8-1]), + .scout(sov[ex1_gpr_s2_xu0_sel_offset + (i-2)*8 : ex1_gpr_s2_xu0_sel_offset + (i-2+1)*8-1]), + .din({8{ex0_gpr_s2_xu0_sel[i-1]}}), + .dout(ex1_gpr_s2_xu0_sel_q[i]) + ); + end +end +endgenerate +generate begin : ex1_gpr_s1_xu1_sel_gen + genvar i; + for (i=2;i<=5;i=i+1) begin : ex1_gpr_s1_xu1_sel_entry + tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s1_xu1_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu1_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_gpr_s1_xu1_sel_offset + (i-2)*8 : ex1_gpr_s1_xu1_sel_offset + (i-2+1)*8-1]), + .scout(sov[ex1_gpr_s1_xu1_sel_offset + (i-2)*8 : ex1_gpr_s1_xu1_sel_offset + (i-2+1)*8-1]), + .din({8{ex0_gpr_s1_xu1_sel[i-1]}}), + .dout(ex1_gpr_s1_xu1_sel_q[i]) + ); + end +end +endgenerate +generate begin : ex1_gpr_s2_xu1_sel_gen + genvar i; + for (i=2;i<=5;i=i+1) begin : ex1_gpr_s2_xu1_sel_entry + tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s2_xu1_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu1_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_gpr_s2_xu1_sel_offset + (i-2)*8 : ex1_gpr_s2_xu1_sel_offset + (i-2+1)*8-1]), + .scout(sov[ex1_gpr_s2_xu1_sel_offset + (i-2)*8 : ex1_gpr_s2_xu1_sel_offset + (i-2+1)*8-1]), + .din({8{ex0_gpr_s2_xu1_sel[i-1]}}), + .dout(ex1_gpr_s2_xu1_sel_q[i]) + ); + end +end +endgenerate +generate begin : ex1_gpr_s1_lq_sel_gen + genvar i; + for (i=5;i<=8;i=i+1) begin : ex1_gpr_s1_lq_sel_entry + tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s1_lq_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu1_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_gpr_s1_lq_sel_offset + (i-5)*8 : ex1_gpr_s1_lq_sel_offset + (i-5+1)*8-1]), + .scout(sov[ex1_gpr_s1_lq_sel_offset + (i-5)*8 : ex1_gpr_s1_lq_sel_offset + (i-5+1)*8-1]), + .din({8{ex0_gpr_s1_lq_sel[i-1]}}), + .dout(ex1_gpr_s1_lq_sel_q[i]) + ); + end +end +endgenerate +generate begin : ex1_gpr_s2_lq_sel_gen + genvar i; + for (i=5;i<=8;i=i+1) begin : ex1_gpr_s2_lq_sel_entry + tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s2_lq_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu1_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_gpr_s2_lq_sel_offset + (i-5)*8 : ex1_gpr_s2_lq_sel_offset + (i-5+1)*8-1]), + .scout(sov[ex1_gpr_s2_lq_sel_offset + (i-5)*8 : ex1_gpr_s2_lq_sel_offset + (i-5+1)*8-1]), + .din({8{ex0_gpr_s2_lq_sel[i-1]}}), + .dout(ex1_gpr_s2_lq_sel_q[i]) + ); + end +end +endgenerate + tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s2_imm_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu1_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_gpr_s2_imm_sel_offset : ex1_gpr_s2_imm_sel_offset + 8-1]), + .scout(sov[ex1_gpr_s2_imm_sel_offset : ex1_gpr_s2_imm_sel_offset + 8-1]), + .din({8{dec_byp_ex0_rs2_sel_imm}}), + .dout(ex1_gpr_s2_imm_sel_q) + ); +generate begin : ex1_spr_s3_xu0_sel_gen + genvar i; + for (i=3;i<=8;i=i+1) begin : ex1_spr_s3_xu0_sel_entry + tri_rlmreg_p #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_spr_s3_xu0_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu1_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_spr_s3_xu0_sel_offset + (i-3)*1 : ex1_spr_s3_xu0_sel_offset + (i-3+1)*1-1]), + .scout(sov[ex1_spr_s3_xu0_sel_offset + (i-3)*1 : ex1_spr_s3_xu0_sel_offset + (i-3+1)*1-1]), + .din(rv_xu1_s3_fxu0_sel[i-1]), + .dout(ex1_spr_s3_xu0_sel_q[i]) + ); + end +end +endgenerate +generate begin : ex1_spr_s3_xu1_sel_gen + genvar i; + for (i=3;i<=5;i=i+1) begin : ex1_spr_s3_xu1_sel_entry + tri_rlmreg_p #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_spr_s3_xu1_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu1_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_spr_s3_xu1_sel_offset + (i-3)*1 : ex1_spr_s3_xu1_sel_offset + (i-3+1)*1-1]), + .scout(sov[ex1_spr_s3_xu1_sel_offset + (i-3)*1 : ex1_spr_s3_xu1_sel_offset + (i-3+1)*1-1]), + .din(rv_xu1_s3_fxu1_sel[i-1]), + .dout(ex1_spr_s3_xu1_sel_q[i]) + ); + end +end +endgenerate +generate begin : ex1_spr_s3_lq_sel_gen + genvar i; + for (i=5;i<=6;i=i+1) begin : ex1_spr_s3_lq_sel_entry + tri_rlmreg_p #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_spr_s3_lq_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu1_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_spr_s3_lq_sel_offset + (i-5)*1 : ex1_spr_s3_lq_sel_offset + (i-5+1)*1-1]), + .scout(sov[ex1_spr_s3_lq_sel_offset + (i-5)*1 : ex1_spr_s3_lq_sel_offset + (i-5+1)*1-1]), + .din(rv_xu1_s3_lq_sel[i-1]), + .dout(ex1_spr_s3_lq_sel_q[i]) + ); + end +end +endgenerate +generate begin : ex1_gpr_s1_rel_sel_gen + genvar i; + for (i=3;i<=4;i=i+1) begin : ex1_gpr_s1_rel_sel_entry + tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s1_rel_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu1_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_gpr_s1_rel_sel_offset + (i-3)*8 : ex1_gpr_s1_rel_sel_offset + (i-3+1)*8-1]), + .scout(sov[ex1_gpr_s1_rel_sel_offset + (i-3)*8 : ex1_gpr_s1_rel_sel_offset + (i-3+1)*8-1]), + .din({8{ex0_gpr_s1_rel_sel[i-1]}}), + .dout(ex1_gpr_s1_rel_sel_q[i]) + ); + end +end +endgenerate +generate begin : ex1_gpr_s2_rel_sel_gen + genvar i; + for (i=3;i<=4;i=i+1) begin : ex1_gpr_s2_rel_sel_entry + tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s2_rel_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu1_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_gpr_s2_rel_sel_offset + (i-3)*8 : ex1_gpr_s2_rel_sel_offset + (i-3+1)*8-1]), + .scout(sov[ex1_gpr_s2_rel_sel_offset + (i-3)*8 : ex1_gpr_s2_rel_sel_offset + (i-3+1)*8-1]), + .din({8{ex0_gpr_s2_rel_sel[i-1]}}), + .dout(ex1_gpr_s2_rel_sel_q[i]) + ); + end +end +endgenerate + tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s1_reg_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu1_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_gpr_s1_reg_sel_offset : ex1_gpr_s1_reg_sel_offset + 8-1]), + .scout(sov[ex1_gpr_s1_reg_sel_offset : ex1_gpr_s1_reg_sel_offset + 8-1]), + .din({8{ex0_gpr_s1_reg_sel}}), + .dout(ex1_gpr_s1_reg_sel_q) + ); + tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s2_reg_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu1_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_gpr_s2_reg_sel_offset : ex1_gpr_s2_reg_sel_offset + 8-1]), + .scout(sov[ex1_gpr_s2_reg_sel_offset : ex1_gpr_s2_reg_sel_offset + 8-1]), + .din({8{ex0_gpr_s2_reg_sel}}), + .dout(ex1_gpr_s2_reg_sel_q) + ); + tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_spr_s3_reg_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu1_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_spr_s3_reg_sel_offset : ex1_spr_s3_reg_sel_offset + 2-1]), + .scout(sov[ex1_spr_s3_reg_sel_offset : ex1_spr_s3_reg_sel_offset + 2-1]), + .din({2{ex0_spr_s3_reg_sel}}), + .dout(ex1_spr_s3_reg_sel_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_abt_s1_lq_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu1_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_abt_s1_lq_sel_offset]), + .scout(sov[ex1_abt_s1_lq_sel_offset]), + .din(ex0_gpr_s1_lq_sel[8]), + .dout(ex1_abt_s1_lq_sel_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_abt_s2_lq_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu1_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_abt_s2_lq_sel_offset]), + .scout(sov[ex1_abt_s2_lq_sel_offset]), + .din(ex0_gpr_s2_lq_sel[8]), + .dout(ex1_abt_s2_lq_sel_q) + ); + tri_rlmreg_p #(.WIDTH(3), .OFFSET(7),.INIT(0), .NEEDS_SRESET(1)) ex1_abt_s3_lq_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu1_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_abt_s3_lq_sel_offset : ex1_abt_s3_lq_sel_offset + 3-1]), + .scout(sov[ex1_abt_s3_lq_sel_offset : ex1_abt_s3_lq_sel_offset + 3-1]), + .din(rv_xu1_s3_lq_sel[6:8]), + .dout(ex1_abt_s3_lq_sel_q) + ); + tri_rlmreg_p #(.WIDTH(2), .OFFSET(6),.INIT(0), .NEEDS_SRESET(1)) ex1_abt_s1_xu1_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu1_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_abt_s1_xu1_sel_offset : ex1_abt_s1_xu1_sel_offset + 2-1]), + .scout(sov[ex1_abt_s1_xu1_sel_offset : ex1_abt_s1_xu1_sel_offset + 2-1]), + .din(ex0_gpr_s1_xu1_sel[5:6]), + .dout(ex1_abt_s1_xu1_sel_q) + ); + tri_rlmreg_p #(.WIDTH(2), .OFFSET(6),.INIT(0), .NEEDS_SRESET(1)) ex1_abt_s2_xu1_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu1_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_abt_s2_xu1_sel_offset : ex1_abt_s2_xu1_sel_offset + 2-1]), + .scout(sov[ex1_abt_s2_xu1_sel_offset : ex1_abt_s2_xu1_sel_offset + 2-1]), + .din(ex0_gpr_s2_xu1_sel[5:6]), + .dout(ex1_abt_s2_xu1_sel_q) + ); + tri_rlmreg_p #(.WIDTH(2), .OFFSET(6),.INIT(0), .NEEDS_SRESET(1)) ex1_abt_s3_xu1_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu1_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_abt_s3_xu1_sel_offset : ex1_abt_s3_xu1_sel_offset + 2-1]), + .scout(sov[ex1_abt_s3_xu1_sel_offset : ex1_abt_s3_xu1_sel_offset + 2-1]), + .din(rv_xu1_s3_fxu1_sel[5:6]), + .dout(ex1_abt_s3_xu1_sel_q) + ); + tri_rlmreg_p #(.WIDTH(4), .OFFSET(9),.INIT(0), .NEEDS_SRESET(1)) ex1_abt_s1_xu0_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu1_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_abt_s1_xu0_sel_offset : ex1_abt_s1_xu0_sel_offset + 4-1]), + .scout(sov[ex1_abt_s1_xu0_sel_offset : ex1_abt_s1_xu0_sel_offset + 4-1]), + .din(ex0_gpr_s1_xu0_sel[8:11]), + .dout(ex1_abt_s1_xu0_sel_q) + ); + tri_rlmreg_p #(.WIDTH(4), .OFFSET(9),.INIT(0), .NEEDS_SRESET(1)) ex1_abt_s2_xu0_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu1_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_abt_s2_xu0_sel_offset : ex1_abt_s2_xu0_sel_offset + 4-1]), + .scout(sov[ex1_abt_s2_xu0_sel_offset : ex1_abt_s2_xu0_sel_offset + 4-1]), + .din(ex0_gpr_s2_xu0_sel[8:11]), + .dout(ex1_abt_s2_xu0_sel_q) + ); + tri_rlmreg_p #(.WIDTH(4), .OFFSET(9),.INIT(0), .NEEDS_SRESET(1)) ex1_abt_s3_xu0_sel_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu1_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_abt_s3_xu0_sel_offset : ex1_abt_s3_xu0_sel_offset + 4-1]), + .scout(sov[ex1_abt_s3_xu0_sel_offset : ex1_abt_s3_xu0_sel_offset + 4-1]), + .din(rv_xu1_s3_fxu0_sel[8:11]), + .dout(ex1_abt_s3_xu0_sel_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex4_xu1_rt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu1_act[3]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex4_xu1_rt_offset : ex4_xu1_rt_offset + `GPR_WIDTH-1]), + .scout(sov[ex4_xu1_rt_offset : ex4_xu1_rt_offset + `GPR_WIDTH-1]), + .din(alu_byp_ex3_rt), + .dout(ex4_xu1_rt_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex5_xu1_rt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu1_act[4]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), + .mpw1_b(mpw1_dc_b[DEX5]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex5_xu1_rt_offset : ex5_xu1_rt_offset + `GPR_WIDTH-1]), + .scout(sov[ex5_xu1_rt_offset : ex5_xu1_rt_offset + `GPR_WIDTH-1]), + .din(ex4_xu1_rt_q), + .dout(ex5_xu1_rt_q) + ); + tri_rlmreg_p #(.WIDTH(4), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex5_xu0_cr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[4]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), + .mpw1_b(mpw1_dc_b[DEX5]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex5_xu0_cr_offset : ex5_xu0_cr_offset + 4-1]), + .scout(sov[ex5_xu0_cr_offset : ex5_xu0_cr_offset + 4-1]), + .din(xu0_xu1_ex4_cr), + .dout(ex5_xu0_cr_q) + ); + tri_rlmreg_p #(.WIDTH(4), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex6_lq_cr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_lq_act[5]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX6]), + .mpw1_b(mpw1_dc_b[DEX6]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex6_lq_cr_offset : ex6_lq_cr_offset + 4-1]), + .scout(sov[ex6_lq_cr_offset : ex6_lq_cr_offset + 4-1]), + .din(lq_xu_ex5_cr), + .dout(ex6_lq_cr_q) + ); + tri_rlmreg_p #(.WIDTH(10), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex5_xu0_xer_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu0_act[4]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), + .mpw1_b(mpw1_dc_b[DEX5]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex5_xu0_xer_offset : ex5_xu0_xer_offset + 10-1]), + .scout(sov[ex5_xu0_xer_offset : ex5_xu0_xer_offset + 10-1]), + .din(xu0_xu1_ex4_xer), + .dout(ex5_xu0_xer_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex2_rs1_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu1_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_rs1_offset : ex2_rs1_offset + `GPR_WIDTH-1]), + .scout(sov[ex2_rs1_offset : ex2_rs1_offset + `GPR_WIDTH-1]), + .din(ex1_rs1), + .dout(ex2_rs1_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex2_rs2_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu1_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_rs2_offset : ex2_rs2_offset + `GPR_WIDTH-1]), + .scout(sov[ex2_rs2_offset : ex2_rs2_offset + `GPR_WIDTH-1]), + .din(ex1_rs2), + .dout(ex2_rs2_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_cr_bit_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu1_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_cr_bit_offset]), + .scout(sov[ex2_cr_bit_offset]), + .din(ex1_cr_bit), + .dout(ex2_cr_bit_q) + ); + tri_rlmreg_p #(.WIDTH(10), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_xer3_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_xu1_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_xer3_offset : ex2_xer3_offset + 10-1]), + .scout(sov[ex2_xer3_offset : ex2_xer3_offset + 10-1]), + .din(ex1_xer3), + .dout(ex2_xer3_q) + ); + tri_rlmreg_p #(.WIDTH(10), .OFFSET(3),.INIT(0), .NEEDS_SRESET(1)) exx_xu0_abort_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[exx_xu0_abort_offset : exx_xu0_abort_offset + 10-1]), + .scout(sov[exx_xu0_abort_offset : exx_xu0_abort_offset + 10-1]), + .din(exx_xu0_abort_d), + .dout(exx_xu0_abort_q) + ); + tri_rlmreg_p #(.WIDTH(6), .OFFSET(2),.INIT(0), .NEEDS_SRESET(1)) exx_xu1_abort_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[exx_xu1_abort_offset : exx_xu1_abort_offset + 6-1]), + .scout(sov[exx_xu1_abort_offset : exx_xu1_abort_offset + 6-1]), + .din(exx_xu1_abort_d), + .dout(exx_xu1_abort_q) + ); + tri_rlmreg_p #(.WIDTH(4), .OFFSET(6),.INIT(0), .NEEDS_SRESET(1)) exx_lq_abort_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[exx_lq_abort_offset : exx_lq_abort_offset + 4-1]), + .scout(sov[exx_lq_abort_offset : exx_lq_abort_offset + 4-1]), + .din(exx_lq_abort_d), + .dout(exx_lq_abort_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_rs1_abort_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_rs1_abort_offset]), + .scout(sov[ex2_rs1_abort_offset]), + .din(ex1_rs1_abort), + .dout(ex2_rs1_abort_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_rs2_abort_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_rs2_abort_offset]), + .scout(sov[ex2_rs2_abort_offset]), + .din(ex1_rs2_abort), + .dout(ex2_rs2_abort_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_rs3_abort_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_rs3_abort_offset]), + .scout(sov[ex2_rs3_abort_offset]), + .din(ex1_rs3_abort), + .dout(ex2_rs3_abort_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) exx_rel3_act_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[exx_rel3_act_offset]), + .scout(sov[exx_rel3_act_offset]), + .din(lq_xu_rel_act), + .dout(exx_rel3_act_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) exx_rel3_rt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(lq_xu_rel_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[exx_rel3_rt_offset : exx_rel3_rt_offset + `GPR_WIDTH-1]), + .scout(sov[exx_rel3_rt_offset : exx_rel3_rt_offset + `GPR_WIDTH-1]), + .din(lq_xu_rel_rt), + .dout(exx_rel3_rt_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) exx_rel4_rt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_rel3_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[exx_rel4_rt_offset : exx_rel4_rt_offset + `GPR_WIDTH-1]), + .scout(sov[exx_rel4_rt_offset : exx_rel4_rt_offset + `GPR_WIDTH-1]), + .din(exx_rel3_rt_q), + .dout(exx_rel4_rt_q) + ); + + assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in}; + assign scan_out = sov[0]; + + + function [0:`GPR_WIDTH-1] fanout; + input [0:7] a; + input integer s; + integer t; + begin + for (t=0;t<`GPR_WIDTH;t=t+1) + begin : loop + fanout[t] = a[t % 8]; + end + end + endfunction + +endmodule diff --git a/dev/verilog/work/xu1_dec.v b/dev/verilog/work/xu1_dec.v new file mode 100755 index 0000000..29f94b9 --- /dev/null +++ b/dev/verilog/work/xu1_dec.v @@ -0,0 +1,1454 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: FXU Decode +// +//***************************************************************************** + +`include "tri_a2o.vh" + +module xu1_dec( + //------------------------------------------------------------------- + // Clocks & Power + //------------------------------------------------------------------- + input [0:`NCLK_WIDTH-1] nclk, + inout vdd, + inout gnd, + + //------------------------------------------------------------------- + // Pervasive + //------------------------------------------------------------------- + input d_mode_dc, + input delay_lclkr_dc, + input mpw1_dc_b, + input mpw2_dc_b, + input func_sl_force, + input func_sl_thold_0_b, + input sg_0, + input scan_in, + output scan_out, + + //------------------------------------------------------------------- + // Interface with SPR + //------------------------------------------------------------------- + input [0:`THREADS-1] spr_msr_cm, // 0: 32 bit mode, 1: 64 bit mode + + //------------------------------------------------------------------- + // Interface with CP + //------------------------------------------------------------------- + input [0:`THREADS-1] cp_flush, + + //------------------------------------------------------------------- + // Interface with RV + //------------------------------------------------------------------- + input [0:`THREADS-1] rv_xu1_vld, + input [0:31] rv_xu1_ex0_instr, + input [0:`ITAG_SIZE_ENC-1] rv_xu1_ex0_itag, + input rv_xu1_ex0_isstore, + input [1:1] rv_xu1_ex0_ucode, + input rv_xu1_ex0_t1_v, + input [0:`GPR_POOL_ENC-1] rv_xu1_ex0_t1_p, + input rv_xu1_ex0_t2_v, + input [0:`GPR_POOL_ENC-1] rv_xu1_ex0_t2_p, + input rv_xu1_ex0_t3_v, + input [0:`GPR_POOL_ENC-1] rv_xu1_ex0_t3_p, + input rv_xu1_ex0_s1_v, + input [0:2] rv_xu1_ex0_s3_t, + input [0:`THREADS-1] rv_xu1_ex0_spec_flush, + input [0:`THREADS-1] rv_xu1_ex1_spec_flush, + input [0:`THREADS-1] rv_xu1_ex2_spec_flush, + + //------------------------------------------------------------------- + // Interface with LQ + //------------------------------------------------------------------- + output [0:`THREADS-1] xu1_lq_ex2_stq_val, + output [0:`ITAG_SIZE_ENC-1] xu1_lq_ex2_stq_itag, + output [1:4] xu1_lq_ex2_stq_size, + output xu1_lq_ex3_illeg_lswx, + output xu1_lq_ex3_strg_noop, + + //------------------------------------------------------------------- + // Interface with IU + //------------------------------------------------------------------- + output [0:`THREADS-1] xu1_iu_execute_vld, + output [0:`ITAG_SIZE_ENC-1] xu1_iu_itag, + + output xu1_pc_ram_done, + + output [0:`THREADS-1] xu_iu_ucode_xer_val, + + //------------------------------------------------------------------- + // Interface with ALU + //------------------------------------------------------------------- + output dec_alu_ex1_act, + output [0:31] dec_alu_ex1_instr, + output dec_alu_ex1_sel_isel, + output [0:`GPR_WIDTH/8-1] dec_alu_ex1_add_rs1_inv, + output [0:1] dec_alu_ex2_add_ci_sel, + output dec_alu_ex1_sel_trap, + output dec_alu_ex1_sel_cmpl, + output dec_alu_ex1_sel_cmp, + output dec_alu_ex1_msb_64b_sel, + output dec_alu_ex1_xer_ov_en, + output dec_alu_ex1_xer_ca_en, + output xu1_xu0_ex3_act, + + //------------------------------------------------------------------- + // Interface with BYP + //------------------------------------------------------------------- + input byp_dec_ex2_abort, + output dec_byp_ex2_val, + output dec_byp_ex0_act, + output [64-`GPR_WIDTH:63] dec_byp_ex1_imm, + output [24:25] dec_byp_ex1_instr, + output dec_byp_ex0_rs2_sel_imm, + output dec_byp_ex0_rs1_sel_zero, + output [0:`THREADS-1] dec_byp_ex2_tid, + output [(64-`GPR_WIDTH)/8:7] dec_byp_ex2_dvc_mask, + + input [3:9] byp_dec_ex2_xer, + + //------------------------------------------------------------------- + // Interface with Regfiles + //------------------------------------------------------------------- + output xu1_gpr_ex3_we, + output [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] xu1_gpr_ex3_wa, + output xu1_xer_ex3_we, + output [0:`XER_POOL_ENC+`THREADS_POOL_ENC-1] xu1_xer_ex3_wa, + output xu1_cr_ex3_we, + output [0:`CR_POOL_ENC+`THREADS_POOL_ENC-1] xu1_cr_ex3_wa, + + input [0:`THREADS-1] pc_xu_ram_active +); + localparam xer_pool_l = `GPR_POOL_ENC-`XER_POOL_ENC; + localparam cr_pool_l = `GPR_POOL_ENC-`CR_POOL_ENC; + // Latches + wire [1:3] exx_act_q, exx_act_d ; // input=>exx_act_d ,act=>1'b1 + wire [0:2] ex1_s3_type_q ; // input=>rv_xu1_ex0_s3_t ,act=>exx_act[0] + wire ex1_t1_v_q ; // input=>rv_xu1_ex0_t1_v ,act=>exx_act[0] + wire ex1_t2_v_q ; // input=>rv_xu1_ex0_t2_v ,act=>exx_act[0] + wire ex1_t3_v_q ; // input=>rv_xu1_ex0_t3_v ,act=>exx_act[0] + wire [0:`GPR_POOL_ENC-1] ex1_t1_p_q ; // input=>rv_xu1_ex0_t1_p ,act=>exx_act[0] + wire [0:`XER_POOL_ENC-1] ex1_t2_p_q ; // input=>rv_xu1_ex0_t2_p[`GPR_POOL_ENC-`XER_POOL_ENC:`GPR_POOL_ENC-1] ,act=>exx_act(0) + wire [0:`CR_POOL_ENC-1] ex1_t3_p_q ; // input=>rv_xu1_ex0_t3_p[`GPR_POOL_ENC-`CR_POOL_ENC:`GPR_POOL_ENC-1] ,act=>exx_act(0) + wire [0:31] ex1_instr_q ; // input=>rv_xu1_ex0_instr ,act=>exx_act[0] + wire [1:1] ex1_ucode_q ; // input=>rv_xu1_ex0_ucode[1:1] ,act=>exx_act[0] + wire [0:`ITAG_SIZE_ENC-1] ex1_itag_q ; // input=>rv_xu1_ex0_itag ,act=>exx_act[0] + wire [0:1] ex2_add_ci_sel_q, ex1_add_ci_sel ; // input=>ex1_add_ci_sel ,act=>exx_act[1] + wire [0:`ITAG_SIZE_ENC-1] ex2_itag_q ; // input=>ex1_itag_q ,act=>exx_act[1] + wire [0:`GPR_POOL_ENC-1] ex2_t1_p_q ; // input=>ex1_t1_p_q ,act=>exx_act[1] + wire [xer_pool_l:`GPR_POOL_ENC-1] ex2_t2_p_q ; // input=>ex1_t2_p_q ,act=>exx_act[1] + wire [cr_pool_l:`GPR_POOL_ENC-1] ex2_t3_p_q ; // input=>ex1_t3_p_q ,act=>exx_act[1] + wire [6:20] ex2_instr_q ; // input=>ex1_instr_q[6:20] ,act=>exx_act[1] + wire ex2_gpr_we_q, ex1_gpr_we ; // input=>ex1_gpr_we ,act=>exx_act[1] + wire ex2_xer_we_q, ex1_xer_we ; // input=>ex1_xer_we ,act=>exx_act[1] + wire ex2_cr_we_q, ex1_cr_we ; // input=>ex1_cr_we ,act=>exx_act[1] + wire [1:4] ex2_opsize_q, ex1_opsize ; // input=>ex1_opsize ,act=>exx_act[1] + wire ex2_is_lswx_q ; // input=>ex1_is_lswx ,act=>exx_act[1] + wire ex2_is_stswx_q ; // input=>ex1_is_stswx ,act=>exx_act[1] + wire [0:`GPR_POOL_ENC-1] ex3_t1_p_q ; // input=>ex2_t1_p_q ,act=>exx_act[2] + wire [xer_pool_l:`GPR_POOL_ENC-1] ex3_t2_p_q ; // input=>ex2_t2_p_q ,act=>exx_act[2] + wire [cr_pool_l:`GPR_POOL_ENC-1] ex3_t3_p_q ; // input=>ex2_t3_p_q ,act=>exx_act[2] + wire [0:`ITAG_SIZE_ENC-1] ex3_itag_q ; // input=>ex2_itag_q ,act=>exx_act[2] + wire ex3_gpr_we_q, ex2_gpr_we ; // input=>ex2_gpr_we ,act=>1'b1 + wire ex3_xer_we_q, ex2_xer_we ; // input=>ex2_xer_we ,act=>1'b1 + wire ex3_cr_we_q, ex2_cr_we ; // input=>ex2_cr_we ,act=>1'b1 + wire ex3_illeg_lswx_q, ex2_illeg_lswx ; // input=>ex2_illeg_lswx ,act=>exx_act[2] + wire ex3_strg_noop_q, ex2_strg_noop ; // input=>ex2_strg_noop ,act=>exx_act[2] + wire [0:`THREADS-1] cp_flush_q ; // input=>cp_flush ,act=>1'b1 + wire [0:`THREADS-1] ex0_val_q, rv2_val ; // input=>rv2_val ,act=>1'b1 + wire [0:`THREADS-1] ex1_val_q, ex0_val ; // input=>ex0_val ,act=>1'b1 + wire [0:`THREADS-1] ex2_val_q, ex1_val ; // input=>ex1_val ,act=>1'b1 + wire [0:`THREADS-1] ex3_val_q, ex2_val ; // input=>ex2_val ,act=>1'b1 + wire [0:`THREADS-1] ex2_stq_val_q, ex1_stq_val ; // input=>ex1_stq_val ,act=>1'b1 + wire ex2_xer_val_q, ex1_xer_val ; // input=>ex1_xer_val ,act=>exx_act[1] + wire [0:`THREADS-1] msr_cm_q ; // input=>spr_msr_cm ,act=>1'b1 + wire ex3_ram_active_q, ex3_ram_active_d ; // input=>ex3_ram_active_d ,act=>1'b1 + wire [(64-`GPR_WIDTH)/8:7] ex2_dvc_mask_q ; // input=>ex1_dvc_mask[(64-`GPR_WIDTH)/8:7] ,act=>exx_act[1] + // Scanchain + localparam exx_act_offset = 0; + localparam ex1_s3_type_offset = exx_act_offset + 3; + localparam ex1_t1_v_offset = ex1_s3_type_offset + 3; + localparam ex1_t2_v_offset = ex1_t1_v_offset + 1; + localparam ex1_t3_v_offset = ex1_t2_v_offset + 1; + localparam ex1_t1_p_offset = ex1_t3_v_offset + 1; + localparam ex1_t2_p_offset = ex1_t1_p_offset + `GPR_POOL_ENC; + localparam ex1_t3_p_offset = ex1_t2_p_offset + `XER_POOL_ENC; + localparam ex1_instr_offset = ex1_t3_p_offset + `CR_POOL_ENC; + localparam ex1_ucode_offset = ex1_instr_offset + 32; + localparam ex1_itag_offset = ex1_ucode_offset + 1; + localparam ex2_add_ci_sel_offset = ex1_itag_offset + `ITAG_SIZE_ENC; + localparam ex2_itag_offset = ex2_add_ci_sel_offset + 2; + localparam ex2_t1_p_offset = ex2_itag_offset + `ITAG_SIZE_ENC; + localparam ex2_t2_p_offset = ex2_t1_p_offset + `GPR_POOL_ENC; + localparam ex2_t3_p_offset = ex2_t2_p_offset + `XER_POOL_ENC; + localparam ex2_instr_offset = ex2_t3_p_offset + `CR_POOL_ENC; + localparam ex2_gpr_we_offset = ex2_instr_offset + 15; + localparam ex2_xer_we_offset = ex2_gpr_we_offset + 1; + localparam ex2_cr_we_offset = ex2_xer_we_offset + 1; + localparam ex2_opsize_offset = ex2_cr_we_offset + 1; + localparam ex2_is_lswx_offset = ex2_opsize_offset + 4; + localparam ex2_is_stswx_offset = ex2_is_lswx_offset + 1; + localparam ex3_t1_p_offset = ex2_is_stswx_offset + 1; + localparam ex3_t2_p_offset = ex3_t1_p_offset + `GPR_POOL_ENC; + localparam ex3_t3_p_offset = ex3_t2_p_offset + `XER_POOL_ENC; + localparam ex3_itag_offset = ex3_t3_p_offset + `CR_POOL_ENC; + localparam ex3_gpr_we_offset = ex3_itag_offset + `ITAG_SIZE_ENC; + localparam ex3_xer_we_offset = ex3_gpr_we_offset + 1; + localparam ex3_cr_we_offset = ex3_xer_we_offset + 1; + localparam ex3_illeg_lswx_offset = ex3_cr_we_offset + 1; + localparam ex3_strg_noop_offset = ex3_illeg_lswx_offset + 1; + localparam cp_flush_offset = ex3_strg_noop_offset + 1; + localparam ex0_val_offset = cp_flush_offset + `THREADS; + localparam ex1_val_offset = ex0_val_offset + `THREADS; + localparam ex2_val_offset = ex1_val_offset + `THREADS; + localparam ex3_val_offset = ex2_val_offset + `THREADS; + localparam ex2_stq_val_offset = ex3_val_offset + `THREADS; + localparam ex2_xer_val_offset = ex2_stq_val_offset + `THREADS; + localparam msr_cm_offset = ex2_xer_val_offset + 1; + localparam ex3_ram_active_offset = msr_cm_offset + `THREADS; + localparam ex2_dvc_mask_offset = ex3_ram_active_offset + 1; + localparam scan_right = ex2_dvc_mask_offset + `GPR_WIDTH/8; + wire [0:scan_right-1] siv; + wire [0:scan_right-1] sov; + + // Signals + wire [0:3] exx_act; + wire ex1_add_rs1_inv; + wire ex1_any_trap; + wire ex1_any_cmpl; + wire ex1_any_cmp; + wire ex1_alu_cmp; + wire ex1_any_tw; + wire ex1_any_td; + wire ex1_force_64b_cmp; + wire ex1_force_32b_cmp; + wire ex0_use_imm; + wire ex1_imm_size; + wire ex1_imm_signext; + wire ex1_shift_imm; + wire ex1_zero_imm; + wire ex1_ones_imm; + wire [0:15] ex1_16b_imm; + wire [6:31] ex1_extd_imm; + wire [64-`GPR_WIDTH:63] ex1_shifted_imm; + wire ex1_any_store; + wire ex1_drop_preissue; + wire [0:`THREADS-1] ex2_stq_val; + wire [0:`THREADS-1] ex3_val; + wire ex3_valid; + wire ex2_valid; + wire [0:7] ex2_num_bytes; + wire [0:7] ex2_num_bytes_plus3; + wire [0:5] ex2_num_regs; + wire [0:5] ex2_lower_bnd; + wire [0:5] ex2_upper_bnd; + wire [0:5] ex2_upper_bnd_wrap; + wire ex2_range_wrap; + wire ex2_ra_in_rng_nowrap; + wire ex2_ra_in_rng_wrap; + wire ex2_ra_in_rng; + wire ex2_rb_in_rng_nowrap; + wire ex2_rb_in_rng_wrap; + wire ex2_rb_in_rng; + wire ex2_ra_eq_rt; + wire ex2_rb_eq_rt; + wire [0:7] ex1_dvc_mask; + + wire ex0_opcode_is_31; + wire ex0_is_addi; + wire ex0_is_addic; + wire ex0_is_addicr; + wire ex0_is_addme; + wire ex0_is_addis; + wire ex0_is_addze; + wire ex0_is_andir; + wire ex0_is_andisr; + wire ex0_is_cmpi; + wire ex0_is_cmpli; + wire ex0_is_neg; + wire ex0_is_ori; + wire ex0_is_oris; + wire ex0_is_subfic; + wire ex0_is_subfze; + wire ex0_is_twi; + wire ex0_is_tdi; + wire ex0_is_xori; + wire ex0_is_xoris; + wire ex0_is_subfme; + + wire ex1_opcode_is_62; + wire ex1_opcode_is_31; + wire ex1_is_adde; + wire ex1_is_addi; + wire ex1_is_addic; + wire ex1_is_addicr; + wire ex1_is_addis; + wire ex1_is_addme; + wire ex1_is_addze; + wire ex1_is_andir; + wire ex1_is_andisr; + wire ex1_is_cmp; + wire ex1_is_cmpi; + wire ex1_is_cmpl; + wire ex1_is_cmpli; + wire ex1_is_icswepx; + wire ex1_is_icswx; + wire ex1_is_lswx; + wire ex1_is_neg; + wire ex1_is_ori; + wire ex1_is_oris; + wire ex1_is_stb; + wire ex1_is_stbepx; + wire ex1_is_stbcrx; + wire ex1_is_stbu; + wire ex1_is_stbux; + wire ex1_is_stbx; + wire ex1_is_std; + wire ex1_is_stdbrx; + wire ex1_is_stdcrx; + wire ex1_is_stdepx; + wire ex1_is_stdu; + wire ex1_is_stdux; + wire ex1_is_stdx; + wire ex1_is_sth; + wire ex1_is_sthbrx; + wire ex1_is_sthcrx; + wire ex1_is_sthepx; + wire ex1_is_sthu; + wire ex1_is_sthux; + wire ex1_is_sthx; + wire ex1_is_stmw; + wire ex1_is_stswi; + wire ex1_is_stswx; + wire ex1_is_stw; + wire ex1_is_stwbrx; + wire ex1_is_stwcrx; + wire ex1_is_stwepx; + wire ex1_is_stwu; + wire ex1_is_stwux; + wire ex1_is_stwx; + wire ex1_is_subf; + wire ex1_is_subfc; + wire ex1_is_subfe; + wire ex1_is_subfic; + wire ex1_is_subfme; + wire ex1_is_subfze; + wire ex1_is_td; + wire ex1_is_tdi; + wire ex1_is_tw; + wire ex1_is_twi; + wire ex1_is_xori; + wire ex1_is_xoris; + wire ex1_is_isel; + wire ex1_is_add; + wire ex1_is_addc; + wire ex1_is_srad; + wire ex1_is_sradi; + wire ex1_is_sraw; + wire ex1_is_srawi; + wire ex1_is_mfdp; + wire ex1_is_mfdpx; + (* analysis_not_referenced="true" *) + wire unused; + + //!! Bugspray Include: xu1_dec; + + //------------------------------------------------------------------------- + // Valids / Act + //------------------------------------------------------------------------- + + assign rv2_val = rv_xu1_vld & ~ cp_flush_q; + assign ex0_val = ex0_val_q & ~(cp_flush_q | rv_xu1_ex0_spec_flush); + assign ex1_val = ex1_val_q & ~(cp_flush_q | rv_xu1_ex1_spec_flush) & {`THREADS{~ex1_any_store}}; + assign ex2_val = ex2_val_q & ~(cp_flush_q | rv_xu1_ex2_spec_flush | {`THREADS{byp_dec_ex2_abort}}); + assign ex3_val = ex3_val_q & ~ cp_flush_q; + assign ex2_valid = |ex2_val; + assign ex3_valid = |ex3_val; + + assign ex1_stq_val = ex1_val_q & ~(cp_flush_q | rv_xu1_ex1_spec_flush) & {`THREADS{(ex1_any_store & ~ex1_drop_preissue)}}; + assign ex2_stq_val = ex2_stq_val_q & ~(cp_flush_q | rv_xu1_ex2_spec_flush | {`THREADS{byp_dec_ex2_abort}}); + + assign exx_act[0] = |ex0_val_q; + assign exx_act[1] = exx_act_q[1]; + assign exx_act[2] = exx_act_q[2]; + assign exx_act[3] = exx_act_q[3]; + + assign exx_act_d[1:3] = exx_act[0:2]; + + assign xu1_xu0_ex3_act = exx_act[3]; + + //------------------------------------------------------------------------- + // ALU control logic + //------------------------------------------------------------------------- + assign dec_alu_ex1_act = exx_act[1]; + assign dec_alu_ex1_instr = ex1_instr_q; + assign dec_alu_ex1_sel_isel = ex1_is_isel; + assign dec_alu_ex2_add_ci_sel = ex2_add_ci_sel_q; + assign dec_alu_ex1_add_rs1_inv = {`GPR_WIDTH/8{ex1_add_rs1_inv}}; + assign dec_alu_ex1_sel_trap = ex1_any_trap; + assign dec_alu_ex1_sel_cmpl = ex1_any_cmpl; + assign dec_alu_ex1_sel_cmp = ex1_any_cmp; + assign dec_byp_ex0_act = exx_act[0]; + assign dec_byp_ex2_val = |ex2_val; + assign dec_byp_ex1_instr = ex1_instr_q[24:25]; + assign dec_byp_ex0_rs1_sel_zero = (~rv_xu1_ex0_s1_v); + assign dec_byp_ex2_tid = ex2_stq_val_q; + + // CI uses XER[CA] + assign ex1_add_ci_sel[0] = ex1_is_adde | ex1_is_addme | ex1_is_addze | ex1_is_subfme | ex1_is_subfze | ex1_is_subfe; + // CI uses 1 + assign ex1_add_ci_sel[1] = ex1_is_subf | ex1_is_subfc | ex1_is_subfic | ex1_is_neg | ex1_alu_cmp | ex1_any_trap; + + assign ex1_add_rs1_inv = ex1_add_ci_sel[1] | ex1_is_subfme | ex1_is_subfze | ex1_is_subfe; + + assign ex1_any_tw = ex1_is_tw | ex1_is_twi; + assign ex1_any_td = ex1_is_td | ex1_is_tdi; + + assign ex1_any_trap = ex1_any_tw | ex1_any_td; + + assign ex1_any_cmp = ex1_is_cmp | ex1_is_cmpi; + + assign ex1_any_cmpl = ex1_is_cmpl | ex1_is_cmpli; + + assign ex1_alu_cmp = ex1_any_cmp | ex1_any_cmpl; + + // Traps, Compares and back invalidates operate regardless of msr[cm] + assign ex1_force_64b_cmp = ex1_any_td | (ex1_alu_cmp & ex1_instr_q[10]); + assign ex1_force_32b_cmp = ex1_any_tw | (ex1_alu_cmp & ~ex1_instr_q[10]); + + assign dec_alu_ex1_msb_64b_sel = (|(ex1_val_q & msr_cm_q) & ~ex1_force_32b_cmp) | ex1_force_64b_cmp; + + assign dec_alu_ex1_xer_ca_en = ex1_is_addc | ex1_is_addic | ex1_is_addicr | ex1_is_adde | ex1_is_addme | ex1_is_addze | + ex1_is_subfc | ex1_is_subfic | ex1_is_subfme | ex1_is_subfe | ex1_is_subfze | + ex1_is_srad | ex1_is_sradi | ex1_is_sraw | ex1_is_srawi; + + assign dec_alu_ex1_xer_ov_en = ex1_instr_q[21] & ( + ex1_is_add | ex1_is_addc | ex1_is_adde | ex1_is_addme | ex1_is_addze | + ex1_is_subf | ex1_is_subfc | ex1_is_subfe | ex1_is_subfme | ex1_is_subfze | ex1_is_neg); + + //---------------------------------------------------------------------------------------------------------------------------------------- + // Immediate Logic + //---------------------------------------------------------------------------------------------------------------------------------------- + // Determine what ops use immediate: + // Branches, Arith/Logical/Other Immediate forms, Loads/Stores, SPR Instructions + assign ex0_use_imm = ex0_is_addi | ex0_is_addic | ex0_is_addicr | ex0_is_addme | ex0_is_addis | ex0_is_addze | + ex0_is_andir | ex0_is_andisr | ex0_is_cmpi | ex0_is_cmpli | ex0_is_neg | ex0_is_ori | ex0_is_oris | + ex0_is_subfic | ex0_is_subfze | ex0_is_twi | ex0_is_tdi | ex0_is_xori | ex0_is_xoris | ex0_is_subfme | + rv_xu1_ex0_isstore; + + // Determine ops that use 15 bit immediate + assign ex1_imm_size = ex1_is_addi | ex1_is_addis | ex1_is_subfic | ex1_is_addic | ex1_is_addicr | + ex1_is_stb | ex1_is_ori | ex1_is_oris | ex1_is_andir | ex1_is_andisr | + ex1_is_xori | ex1_is_xoris | ex1_is_sth | ex1_is_stw | ex1_is_stbu | + ex1_is_sthu | ex1_is_stwu | ex1_is_stdu | ex1_is_std | ex1_is_stmw | + ex1_is_cmpli | ex1_is_cmpi | ex1_is_twi | ex1_is_tdi; + + // Determine ops that use sign-extended immediate + assign ex1_imm_signext = ex1_is_addi | ex1_is_addis | ex1_is_subfic | ex1_is_addic | ex1_is_addicr | + ex1_is_sth | ex1_is_stw | ex1_is_stbu | ex1_is_sthu | ex1_is_stwu | + ex1_is_stdu | ex1_is_std | ex1_is_stmw | ex1_is_stb | ex1_is_cmpi | + ex1_is_twi | ex1_is_tdi; + + assign ex1_shift_imm = ex1_is_addis | ex1_is_oris | ex1_is_andisr | ex1_is_xoris; // Immediate needs to be shifted + assign ex1_zero_imm = ex1_is_neg | ex1_is_addze | ex1_is_subfze | ex1_any_store; + assign ex1_ones_imm = ex1_is_addme | ex1_is_subfme; // Immediate should be all ones + + assign ex1_16b_imm = ((ex1_is_std | ex1_is_stdu) == 1'b0) ? ex1_instr_q[16:31] : {ex1_instr_q[16:29], 2'b0}; + + assign ex1_extd_imm = ({ex1_imm_size, ex1_imm_signext} == 2'b11) ? {{10{ex1_16b_imm[0]}}, ex1_16b_imm} : + ({ex1_imm_size, ex1_imm_signext} == 2'b10) ? { 10'b0, ex1_16b_imm} : + ex1_instr_q[6:31]; + + // Immediate tied down or tied up as needed + assign ex1_shifted_imm = (ex1_shift_imm == 1'b0) ? {{`GPR_WIDTH-26{ex1_extd_imm[6]}}, ex1_extd_imm} : + {{`GPR_WIDTH-32{ex1_extd_imm[15]}}, ex1_extd_imm[16:31], 16'b0}; + + assign dec_byp_ex1_imm = ex1_shifted_imm & {`GPR_WIDTH{~ex1_zero_imm}} | {`GPR_WIDTH{ex1_ones_imm}}; + + assign dec_byp_ex0_rs2_sel_imm = ex0_use_imm; + + //------------------------------------------------------------------------- + // Store Pipe control logic + //------------------------------------------------------------------------- + assign ex1_opsize[1] = ex1_is_std | ex1_is_stdbrx | ex1_is_stdcrx | ex1_is_stdu | ex1_is_stdux | ex1_is_stdx | ex1_is_stdepx; + assign ex1_opsize[2] = ex1_is_stw | ex1_is_stwbrx | ex1_is_stwcrx | ex1_is_stwu | ex1_is_stwux | ex1_is_stwx | ex1_is_stwepx; + assign ex1_opsize[3] = ex1_is_sth | ex1_is_sthbrx | ex1_is_sthcrx | ex1_is_sthu | ex1_is_sthux | ex1_is_sthx | ex1_is_sthepx; + assign ex1_opsize[4] = ex1_is_stb | ex1_is_stbu | ex1_is_stbux | ex1_is_stbx | ex1_is_stbepx | ex1_is_stbcrx; + + assign ex1_any_store = ex1_is_std | ex1_is_stdbrx | ex1_is_stdcrx | ex1_is_stdu | ex1_is_stdux | ex1_is_stdx | ex1_is_stdepx | + ex1_is_stw | ex1_is_stwbrx | ex1_is_stwcrx | ex1_is_stwu | ex1_is_stwux | ex1_is_stwx | ex1_is_stwepx | + ex1_is_sth | ex1_is_sthbrx | ex1_is_sthcrx | ex1_is_sthu | ex1_is_sthux | ex1_is_sthx | ex1_is_sthepx | + ex1_is_stswx | ex1_is_stswi | ex1_is_stb | ex1_is_stbu | ex1_is_stbux | ex1_is_stbx | ex1_is_stbepx | + ex1_is_stbcrx | ex1_is_lswx | ex1_is_icswx | ex1_is_icswepx | ex1_is_mfdp | ex1_is_mfdpx; + + assign ex1_drop_preissue = (ex1_ucode_q[1] & ~(ex1_s3_type_q == 3'b100)) | ex1_is_mfdp | ex1_is_mfdpx; // DITC temp hack + assign ex1_xer_val = ex1_ucode_q[1] & (ex1_s3_type_q == 3'b100); + + assign xu1_lq_ex2_stq_val = ex2_stq_val; + assign xu1_lq_ex2_stq_itag = ex2_itag_q; + assign xu1_lq_ex2_stq_size = ex2_opsize_q; + assign xu1_lq_ex3_illeg_lswx = ex3_illeg_lswx_q; + assign xu1_lq_ex3_strg_noop = ex3_strg_noop_q; + + assign ex1_dvc_mask = (8'h01 & {8{ex1_opsize[4]}}) | + (8'h03 & {8{ex1_opsize[3]}}) | + (8'h0F & {8{ex1_opsize[2]}}) | + (8'hFF & {8{ex1_opsize[1]}}) ; + + assign dec_byp_ex2_dvc_mask = ex2_dvc_mask_q; + + // XER Report to Ucode Engine + // LSU can't update XER, so spec flushes not a problem here. XER will still be correct. + assign xu_iu_ucode_xer_val = ex2_xer_val_q==1'b1 ? (ex2_stq_val_q & ~{`THREADS{byp_dec_ex2_abort}}) : `THREADS'b0; + + //------------------------------------------------------------------------- + // Illegal LSWX Detection + //------------------------------------------------------------------------------ + assign ex2_num_bytes = {1'b0, byp_dec_ex2_xer[3:9]}; + assign ex2_num_bytes_plus3 = ex2_num_bytes + 8'd3; + assign ex2_num_regs = ex2_num_bytes_plus3[0:5]; // Add 3, shift right 2 = ceiling(num_bytes/4) + assign ex2_lower_bnd = {1'b0, ex2_instr_q[6:10]}; // Target of LSWX instruction + assign ex2_upper_bnd = ex2_lower_bnd + ex2_num_regs; + assign ex2_upper_bnd_wrap = {1'b0, ex2_upper_bnd[1:5]}; + assign ex2_range_wrap = ex2_upper_bnd[0]; // When upper bound is past GPR 31 + + // RA in range + assign ex2_ra_in_rng_nowrap = (({1'b0, ex2_instr_q[11:15]}) >= ex2_lower_bnd) & (({1'b0, ex2_instr_q[11:15]}) < ex2_upper_bnd); + assign ex2_ra_in_rng_wrap = (({1'b0, ex2_instr_q[11:15]}) < ex2_upper_bnd_wrap); + assign ex2_ra_in_rng = (ex2_ra_in_rng_nowrap) | (ex2_ra_in_rng_wrap & ex2_range_wrap); + + // RB in range + assign ex2_rb_in_rng_nowrap = (({1'b0, ex2_instr_q[16:20]}) >= ex2_lower_bnd) & (({1'b0, ex2_instr_q[16:20]}) < ex2_upper_bnd); + assign ex2_rb_in_rng_wrap = (({1'b0, ex2_instr_q[16:20]}) < ex2_upper_bnd_wrap); + assign ex2_rb_in_rng = (ex2_rb_in_rng_nowrap) | (ex2_rb_in_rng_wrap & ex2_range_wrap); + assign ex2_ra_eq_rt = (ex2_instr_q[11:15] == ex2_instr_q[6:10]); + assign ex2_rb_eq_rt = (ex2_instr_q[16:20] == ex2_instr_q[6:10]); + assign ex2_illeg_lswx = ex2_is_lswx_q & (ex2_ra_in_rng | ex2_rb_in_rng | ex2_ra_eq_rt | ex2_rb_eq_rt); + assign ex2_strg_noop = (ex2_is_lswx_q | ex2_is_stswx_q) & ~|byp_dec_ex2_xer; + + //------------------------------------------------------------------------- + // Write Enables + //------------------------------------------------------------------------- + assign ex1_gpr_we = ex1_t1_v_q; + assign ex1_xer_we = ex1_t2_v_q; + assign ex1_cr_we = ex1_t3_v_q; + + assign ex2_gpr_we = ex2_valid & ex2_gpr_we_q; + assign ex2_xer_we = ex2_valid & ex2_xer_we_q; + assign ex2_cr_we = ex2_valid & ex2_cr_we_q; + + assign xu1_gpr_ex3_we = ex3_gpr_we_q; + assign xu1_xer_ex3_we = ex3_xer_we_q; + assign xu1_cr_ex3_we = ex3_cr_we_q; + + `ifdef THREADS1 + assign xu1_gpr_ex3_wa = ex3_t1_p_q; + assign xu1_xer_ex3_wa = ex3_t2_p_q; + assign xu1_cr_ex3_wa = ex3_t3_p_q; + `else + assign xu1_gpr_ex3_wa = {ex3_t1_p_q,ex3_val_q[1]}; + assign xu1_xer_ex3_wa = {ex3_t2_p_q,ex3_val_q[1]}; + assign xu1_cr_ex3_wa = {ex3_t3_p_q,ex3_val_q[1]}; + `endif + + assign xu1_iu_execute_vld = ex3_val; + assign xu1_iu_itag = ex3_itag_q; + + assign ex3_ram_active_d = |(ex2_val_q & pc_xu_ram_active); + + assign xu1_pc_ram_done = ex3_valid & ex3_ram_active_q; + + //------------------------------------------------------------------------- + // Decode + //------------------------------------------------------------------------- + assign ex0_opcode_is_31 = rv_xu1_ex0_instr[0:5] == 6'b011111; + + assign ex0_is_addi = rv_xu1_ex0_instr[0:5] == 6'b001110; + assign ex0_is_addic = rv_xu1_ex0_instr[0:5] == 6'b001100; + assign ex0_is_addicr = rv_xu1_ex0_instr[0:5] == 6'b001101; + assign ex0_is_addme = ex0_opcode_is_31 & rv_xu1_ex0_instr[22:30] == 9'b011101010; + assign ex0_is_addis = rv_xu1_ex0_instr[0:5] == 6'b001111; + assign ex0_is_addze = ex0_opcode_is_31 & rv_xu1_ex0_instr[22:30] == 9'b011001010; + assign ex0_is_andir = rv_xu1_ex0_instr[0:5] == 6'b011100; + assign ex0_is_andisr = rv_xu1_ex0_instr[0:5] == 6'b011101; + assign ex0_is_cmpi = rv_xu1_ex0_instr[0:5] == 6'b001011; + assign ex0_is_cmpli = rv_xu1_ex0_instr[0:5] == 6'b001010; + assign ex0_is_neg = ex0_opcode_is_31 & rv_xu1_ex0_instr[22:30] == 9'b001101000; + assign ex0_is_ori = rv_xu1_ex0_instr[0:5] == 6'b011000; + assign ex0_is_oris = rv_xu1_ex0_instr[0:5] == 6'b011001; + assign ex0_is_subfic = rv_xu1_ex0_instr[0:5] == 6'b001000; + assign ex0_is_subfze = ex0_opcode_is_31 & rv_xu1_ex0_instr[22:30] == 9'b011001000; + assign ex0_is_twi = rv_xu1_ex0_instr[0:5] == 6'b000011; + assign ex0_is_tdi = rv_xu1_ex0_instr[0:5] == 6'b000010; + assign ex0_is_xori = rv_xu1_ex0_instr[0:5] == 6'b011010; + assign ex0_is_xoris = rv_xu1_ex0_instr[0:5] == 6'b011011; + assign ex0_is_subfme = ex0_opcode_is_31 & rv_xu1_ex0_instr[22:30] == 9'b011101000; + + assign ex1_opcode_is_62 = ex1_instr_q[0:5] == 6'b111110; + assign ex1_opcode_is_31 = ex1_instr_q[0:5] == 6'b011111; + + assign ex1_is_add = ex1_opcode_is_31 & ex1_instr_q[22:30] == 9'b100001010; // 31/266 + assign ex1_is_addc = ex1_opcode_is_31 & ex1_instr_q[22:30] == 9'b000001010; // 31/10 + assign ex1_is_adde = ex1_opcode_is_31 & ex1_instr_q[22:30] == 9'b010001010; // 31/138 + assign ex1_is_addi = ex1_instr_q[0:5] == 6'b001110; // 14 + assign ex1_is_addic = ex1_instr_q[0:5] == 6'b001100; // 12 + assign ex1_is_addicr = ex1_instr_q[0:5] == 6'b001101; // 13 + assign ex1_is_addis = ex1_instr_q[0:5] == 6'b001111; // 15 + assign ex1_is_addme = ex1_opcode_is_31 & ex1_instr_q[22:30] == 9'b011101010; // 31/234 + assign ex1_is_addze = ex1_opcode_is_31 & ex1_instr_q[22:30] == 9'b011001010; // 31/202 + assign ex1_is_andir = ex1_instr_q[0:5] == 6'b011100; // 28 + assign ex1_is_andisr = ex1_instr_q[0:5] == 6'b011101; // 29 + assign ex1_is_cmp = ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0000000000; // 31/0 + assign ex1_is_cmpi = ex1_instr_q[0:5] == 6'b001011; // 11 + assign ex1_is_cmpl = ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0000100000; // 31/32 + assign ex1_is_cmpli = ex1_instr_q[0:5] == 6'b001010; // 10 + assign ex1_is_icswx = ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0110010110; // 31/406 + assign ex1_is_icswepx = ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b1110110110; // 31/950 + assign ex1_is_isel = ex1_opcode_is_31 & ex1_instr_q[26:30] == 5'b01111; // 31/15 + assign ex1_is_lswx = ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b1000010101; // 31/533 + assign ex1_is_mfdp = ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0000100011; // 31/35 + assign ex1_is_mfdpx = ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0000000011; // 31/3 + assign ex1_is_neg = ex1_opcode_is_31 & ex1_instr_q[22:30] == 9'b001101000; // 31/104 + assign ex1_is_ori = ex1_instr_q[0:5] == 6'b011000; // 24 + assign ex1_is_oris = ex1_instr_q[0:5] == 6'b011001; // 25 + assign ex1_is_srad = ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b1100011010; // 31/794 + assign ex1_is_sradi = ex1_opcode_is_31 & ex1_instr_q[21:29] == 9'b110011101; // 31/413 + assign ex1_is_sraw = ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b1100011000; // 31/792 + assign ex1_is_srawi = ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b1100111000; // 31/824 + assign ex1_is_stb = ex1_instr_q[0:5] == 6'b100110; // 38 + assign ex1_is_stbcrx = ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b1010110110; // 31/694 + assign ex1_is_stbepx = ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0011011111; // 31/223 + assign ex1_is_stbu = ex1_instr_q[0:5] == 6'b100111; // 39 + assign ex1_is_stbux = ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0011110111; // 31/247 + assign ex1_is_stbx = ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0011010111; // 31/215 + assign ex1_is_std = ex1_opcode_is_62 & ex1_instr_q[30:31] == 2'b00; // 62/0 + assign ex1_is_stdbrx = ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b1010010100; // 31/660 + assign ex1_is_stdcrx = ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0011010110; // 31/214 + assign ex1_is_stdepx = ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0010011101; // 31/157 + assign ex1_is_stdu = ex1_opcode_is_62 & ex1_instr_q[30:31] == 2'b01; // 62/1 + assign ex1_is_stdux = ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0010110101; // 31/181 + assign ex1_is_stdx = ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0010010101; // 31/149 + assign ex1_is_sth = ex1_instr_q[0:5] == 6'b101100; // 44 + assign ex1_is_sthu = ex1_instr_q[0:5] == 6'b101101; // 45 + assign ex1_is_sthux = ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0110110111; // 31/439 + assign ex1_is_sthx = ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0110010111; // 31/407 + assign ex1_is_sthbrx = ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b1110010110; // 31/918 + assign ex1_is_sthcrx = ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b1011010110; // 31/726 + assign ex1_is_sthepx = ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0110011111; // 31/415 + assign ex1_is_stmw = ex1_instr_q[0:5] == 6'b101111; // 47 + assign ex1_is_stswi = ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b1011010101; // 31/725 + assign ex1_is_stswx = ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b1010010101; // 31/661 + assign ex1_is_stw = ex1_instr_q[0:5] == 6'b100100; // 36 + assign ex1_is_stwbrx = ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b1010010110; // 31/662 + assign ex1_is_stwcrx = ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0010010110; // 31/150 + assign ex1_is_stwepx = ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0010011111; // 31/159 + assign ex1_is_stwu = ex1_instr_q[0:5] == 6'b100101; // 37 + assign ex1_is_stwux = ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0010110111; // 31/183 + assign ex1_is_stwx = ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0010010111; // 31/151 + assign ex1_is_subf = ex1_opcode_is_31 & ex1_instr_q[22:30] == 9'b000101000; // 31/40 + assign ex1_is_subfc = ex1_opcode_is_31 & ex1_instr_q[22:30] == 9'b000001000; // 31/8 + assign ex1_is_subfe = ex1_opcode_is_31 & ex1_instr_q[22:30] == 9'b010001000; // 31/136 + assign ex1_is_subfic = ex1_instr_q[0:5] == 6'b001000; // 8 + assign ex1_is_subfme = ex1_opcode_is_31 & ex1_instr_q[22:30] == 9'b011101000; // 31/232 + assign ex1_is_subfze = ex1_opcode_is_31 & ex1_instr_q[22:30] == 9'b011001000; // 31/200 + assign ex1_is_td = ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0001000100; // 31/68 + assign ex1_is_tdi = ex1_instr_q[0:5] == 6'b000010; // 2 + assign ex1_is_tw = ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0000000100; // 31/4 + assign ex1_is_twi = ex1_instr_q[0:5] == 6'b000011; // 3 + assign ex1_is_xori = ex1_instr_q[0:5] == 6'b011010; // 26 + assign ex1_is_xoris = ex1_instr_q[0:5] == 6'b011011; // 27 + + //------------------------------------------------------------------------------------------ + // Latches + //------------------------------------------------------------------------------------------ + + tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) exx_act_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[exx_act_offset:exx_act_offset + 3 - 1]), + .scout(sov[exx_act_offset:exx_act_offset + 3 - 1]), + .din(exx_act_d), + .dout(exx_act_q) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex1_s3_type_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(exx_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_s3_type_offset:ex1_s3_type_offset + 3 - 1]), + .scout(sov[ex1_s3_type_offset:ex1_s3_type_offset + 3 - 1]), + .din(rv_xu1_ex0_s3_t), + .dout(ex1_s3_type_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_t1_v_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(exx_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_t1_v_offset]), + .scout(sov[ex1_t1_v_offset]), + .din(rv_xu1_ex0_t1_v), + .dout(ex1_t1_v_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_t2_v_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(exx_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_t2_v_offset]), + .scout(sov[ex1_t2_v_offset]), + .din(rv_xu1_ex0_t2_v), + .dout(ex1_t2_v_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_t3_v_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(exx_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_t3_v_offset]), + .scout(sov[ex1_t3_v_offset]), + .din(rv_xu1_ex0_t3_v), + .dout(ex1_t3_v_q) + ); + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) ex1_t1_p_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(exx_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_t1_p_offset:ex1_t1_p_offset + `GPR_POOL_ENC - 1]), + .scout(sov[ex1_t1_p_offset:ex1_t1_p_offset + `GPR_POOL_ENC - 1]), + .din(rv_xu1_ex0_t1_p), + .dout(ex1_t1_p_q) + ); + + tri_rlmreg_p #(.WIDTH(`XER_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) ex1_t2_p_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(exx_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_t2_p_offset:ex1_t2_p_offset + `XER_POOL_ENC - 1]), + .scout(sov[ex1_t2_p_offset:ex1_t2_p_offset + `XER_POOL_ENC - 1]), + .din(rv_xu1_ex0_t2_p[`GPR_POOL_ENC-`XER_POOL_ENC:`GPR_POOL_ENC-1]), + .dout(ex1_t2_p_q) + ); + + tri_rlmreg_p #(.WIDTH(`CR_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) ex1_t3_p_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(exx_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_t3_p_offset:ex1_t3_p_offset + `CR_POOL_ENC - 1]), + .scout(sov[ex1_t3_p_offset:ex1_t3_p_offset + `CR_POOL_ENC - 1]), + .din(rv_xu1_ex0_t3_p[`GPR_POOL_ENC-`CR_POOL_ENC:`GPR_POOL_ENC-1]), + .dout(ex1_t3_p_q) + ); + + tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) ex1_instr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(exx_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_instr_offset:ex1_instr_offset + 32 - 1]), + .scout(sov[ex1_instr_offset:ex1_instr_offset + 32 - 1]), + .din(rv_xu1_ex0_instr), + .dout(ex1_instr_q) + ); + + tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex1_ucode_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(exx_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_ucode_offset:ex1_ucode_offset + 1 - 1]), + .scout(sov[ex1_ucode_offset:ex1_ucode_offset + 1 - 1]), + .din(rv_xu1_ex0_ucode[1:1]), + .dout(ex1_ucode_q) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex1_itag_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(exx_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_itag_offset:ex1_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[ex1_itag_offset:ex1_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(rv_xu1_ex0_itag), + .dout(ex1_itag_q) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex2_add_ci_sel_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_add_ci_sel_offset:ex2_add_ci_sel_offset + 2 - 1]), + .scout(sov[ex2_add_ci_sel_offset:ex2_add_ci_sel_offset + 2 - 1]), + .din(ex1_add_ci_sel), + .dout(ex2_add_ci_sel_q) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex2_itag_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_itag_offset:ex2_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[ex2_itag_offset:ex2_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(ex1_itag_q), + .dout(ex2_itag_q) + ); + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) ex2_t1_p_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_t1_p_offset:ex2_t1_p_offset + `GPR_POOL_ENC - 1]), + .scout(sov[ex2_t1_p_offset:ex2_t1_p_offset + `GPR_POOL_ENC - 1]), + .din(ex1_t1_p_q), + .dout(ex2_t1_p_q) + ); + + tri_rlmreg_p #(.WIDTH(`XER_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) ex2_t2_p_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_t2_p_offset :ex2_t2_p_offset + `XER_POOL_ENC- 1]), + .scout(sov[ex2_t2_p_offset:ex2_t2_p_offset + `XER_POOL_ENC- 1]), + .din(ex1_t2_p_q), + .dout(ex2_t2_p_q) + ); + + tri_rlmreg_p #(.WIDTH(`CR_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) ex2_t3_p_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_t3_p_offset :ex2_t3_p_offset + `CR_POOL_ENC - 1]), + .scout(sov[ex2_t3_p_offset:ex2_t3_p_offset + `CR_POOL_ENC - 1]), + .din(ex1_t3_p_q), + .dout(ex2_t3_p_q) + ); + + tri_rlmreg_p #(.WIDTH(15), .INIT(0), .NEEDS_SRESET(1)) ex2_instr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_instr_offset:ex2_instr_offset + 15 - 1]), + .scout(sov[ex2_instr_offset:ex2_instr_offset + 15 - 1]), + .din(ex1_instr_q[6:20]), + .dout(ex2_instr_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_gpr_we_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_gpr_we_offset]), + .scout(sov[ex2_gpr_we_offset]), + .din(ex1_gpr_we), + .dout(ex2_gpr_we_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_xer_we_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_xer_we_offset]), + .scout(sov[ex2_xer_we_offset]), + .din(ex1_xer_we), + .dout(ex2_xer_we_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_cr_we_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_cr_we_offset]), + .scout(sov[ex2_cr_we_offset]), + .din(ex1_cr_we), + .dout(ex2_cr_we_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ex2_opsize_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_opsize_offset:ex2_opsize_offset + 4 - 1]), + .scout(sov[ex2_opsize_offset:ex2_opsize_offset + 4 - 1]), + .din(ex1_opsize), + .dout(ex2_opsize_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_is_lswx_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_is_lswx_offset]), + .scout(sov[ex2_is_lswx_offset]), + .din(ex1_is_lswx), + .dout(ex2_is_lswx_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_is_stswx_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_is_stswx_offset]), + .scout(sov[ex2_is_stswx_offset]), + .din(ex1_is_stswx), + .dout(ex2_is_stswx_q) + ); + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) ex3_t1_p_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_t1_p_offset:ex3_t1_p_offset + `GPR_POOL_ENC - 1]), + .scout(sov[ex3_t1_p_offset:ex3_t1_p_offset + `GPR_POOL_ENC - 1]), + .din(ex2_t1_p_q), + .dout(ex3_t1_p_q) + ); + + tri_rlmreg_p #(.WIDTH(`XER_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) ex3_t2_p_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_t2_p_offset :ex3_t2_p_offset + `XER_POOL_ENC- 1]), + .scout(sov[ex3_t2_p_offset:ex3_t2_p_offset + `XER_POOL_ENC- 1]), + .din(ex2_t2_p_q[xer_pool_l:`GPR_POOL_ENC-1]), + .dout(ex3_t2_p_q) + ); + + tri_rlmreg_p #(.WIDTH(`CR_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) ex3_t3_p_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_t3_p_offset :ex3_t3_p_offset + `CR_POOL_ENC- 1]), + .scout(sov[ex3_t3_p_offset:ex3_t3_p_offset + `CR_POOL_ENC- 1]), + .din(ex2_t3_p_q[cr_pool_l:`GPR_POOL_ENC-1]), + .dout(ex3_t3_p_q) + ); + + tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex3_itag_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_itag_offset:ex3_itag_offset + `ITAG_SIZE_ENC - 1]), + .scout(sov[ex3_itag_offset:ex3_itag_offset + `ITAG_SIZE_ENC - 1]), + .din(ex2_itag_q), + .dout(ex3_itag_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_gpr_we_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_gpr_we_offset]), + .scout(sov[ex3_gpr_we_offset]), + .din(ex2_gpr_we), + .dout(ex3_gpr_we_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_xer_we_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_xer_we_offset]), + .scout(sov[ex3_xer_we_offset]), + .din(ex2_xer_we), + .dout(ex3_xer_we_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_cr_we_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_cr_we_offset]), + .scout(sov[ex3_cr_we_offset]), + .din(ex2_cr_we), + .dout(ex3_cr_we_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_illeg_lswx_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_illeg_lswx_offset]), + .scout(sov[ex3_illeg_lswx_offset]), + .din(ex2_illeg_lswx), + .dout(ex3_illeg_lswx_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_strg_noop_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_strg_noop_offset]), + .scout(sov[ex3_strg_noop_offset]), + .din(ex2_strg_noop), + .dout(ex3_strg_noop_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) cp_flush_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[cp_flush_offset:cp_flush_offset + `THREADS - 1]), + .scout(sov[cp_flush_offset:cp_flush_offset + `THREADS - 1]), + .din(cp_flush), + .dout(cp_flush_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex0_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex0_val_offset:ex0_val_offset + `THREADS - 1]), + .scout(sov[ex0_val_offset:ex0_val_offset + `THREADS - 1]), + .din(rv2_val), + .dout(ex0_val_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex1_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_val_offset:ex1_val_offset + `THREADS - 1]), + .scout(sov[ex1_val_offset:ex1_val_offset + `THREADS - 1]), + .din(ex0_val), + .dout(ex1_val_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex2_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_val_offset:ex2_val_offset + `THREADS - 1]), + .scout(sov[ex2_val_offset:ex2_val_offset + `THREADS - 1]), + .din(ex1_val), + .dout(ex2_val_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex3_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_val_offset:ex3_val_offset + `THREADS - 1]), + .scout(sov[ex3_val_offset:ex3_val_offset + `THREADS - 1]), + .din(ex2_val), + .dout(ex3_val_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex2_stq_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_stq_val_offset:ex2_stq_val_offset + `THREADS - 1]), + .scout(sov[ex2_stq_val_offset:ex2_stq_val_offset + `THREADS - 1]), + .din(ex1_stq_val), + .dout(ex2_stq_val_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_xer_val_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_xer_val_offset]), + .scout(sov[ex2_xer_val_offset]), + .din(ex1_xer_val), + .dout(ex2_xer_val_q) + ); + + tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) msr_cm_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[msr_cm_offset:msr_cm_offset + `THREADS - 1]), + .scout(sov[msr_cm_offset:msr_cm_offset + `THREADS - 1]), + .din(spr_msr_cm), + .dout(msr_cm_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_ram_active_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_ram_active_offset]), + .scout(sov[ex3_ram_active_offset]), + .din(ex3_ram_active_d), + .dout(ex3_ram_active_q) + ); + + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH/8), .INIT(0), .NEEDS_SRESET(1)) ex2_dvc_mask_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_dvc_mask_offset:ex2_dvc_mask_offset + `GPR_WIDTH/8-1]), + .scout(sov[ex2_dvc_mask_offset:ex2_dvc_mask_offset + `GPR_WIDTH/8-1]), + .din(ex1_dvc_mask[(64-`GPR_WIDTH)/8:7]), + .dout(ex2_dvc_mask_q) + ); + + assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in}; + assign scan_out = sov[0]; + + assign unused = |{ex2_num_bytes_plus3[6:7], rv_xu1_ex0_t2_p[0:1], rv_xu1_ex0_t3_p[0]}; + +endmodule diff --git a/dev/verilog/work/xu_alu.v b/dev/verilog/work/xu_alu.v new file mode 100755 index 0000000..5ac5f7c --- /dev/null +++ b/dev/verilog/work/xu_alu.v @@ -0,0 +1,555 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: XU_FX ALU Top +// +//***************************************************************************** +`include "tri_a2o.vh" +module xu_alu( + //------------------------------------------------------------------- + // Clocks & Power + //------------------------------------------------------------------- + input [0:`NCLK_WIDTH-1] nclk, + inout vdd, + inout gnd, + + //------------------------------------------------------------------- + // Pervasive + //------------------------------------------------------------------- + input d_mode_dc, + input delay_lclkr_dc, + input mpw1_dc_b, + input mpw2_dc_b, + input func_sl_force, + input func_sl_thold_0_b, + input sg_0, + input scan_in, + output scan_out, + + //------------------------------------------------------------------- + // Decode Interface + //------------------------------------------------------------------- + input dec_alu_ex1_act, + input [0:31] dec_alu_ex1_instr, + input dec_alu_ex1_sel_isel, // Critical! + input [0:`GPR_WIDTH/8-1] dec_alu_ex1_add_rs1_inv, + input [0:1] dec_alu_ex2_add_ci_sel, + input dec_alu_ex1_sel_trap, + input dec_alu_ex1_sel_cmpl, + input dec_alu_ex1_sel_cmp, + input dec_alu_ex1_msb_64b_sel, + input dec_alu_ex1_xer_ov_en, + input dec_alu_ex1_xer_ca_en, + + //------------------------------------------------------------------- + // Bypass Inputs + //------------------------------------------------------------------- + input [64-`GPR_WIDTH:63] byp_alu_ex2_rs1, // Source Data + input [64-`GPR_WIDTH:63] byp_alu_ex2_rs2, + input byp_alu_ex2_cr_bit, // CR bit for isel + input [0:9] byp_alu_ex2_xer, + + //------------------------------------------------------------------- + // Bypass Outputs + //------------------------------------------------------------------- + output [64-`GPR_WIDTH:63] alu_byp_ex2_add_rt, + output [64-`GPR_WIDTH:63] alu_byp_ex3_rt, + output [0:3] alu_byp_ex3_cr, + output [0:9] alu_byp_ex3_xer, + + output alu_dec_ex3_trap_val +); + + localparam msb = 64 - `GPR_WIDTH; + // Latches + wire ex2_act_q; // input=>dec_alu_ex1_act ,act=>1'b1 + wire ex2_sel_isel_q; // input=>dec_alu_ex1_sel_isel ,act=>dec_alu_ex1_act + wire ex2_msb_64b_sel_q; // input=>dec_alu_ex1_msb_64b_sel ,act=>dec_alu_ex1_act + wire ex2_sel_trap_q; // input=>dec_alu_ex1_sel_trap ,act=>dec_alu_ex1_act + wire ex2_sel_cmpl_q; // input=>dec_alu_ex1_sel_cmpl ,act=>dec_alu_ex1_act + wire ex2_sel_cmp_q; // input=>dec_alu_ex1_sel_cmp ,act=>dec_alu_ex1_act + wire [6:10] ex2_instr_6to10_q; // input=>dec_alu_ex1_instr(6 to 10) ,act=>dec_alu_ex1_act + wire ex2_xer_ov_en_q; // input=>dec_alu_ex1_xer_ov_en ,act=>dec_alu_ex1_act + wire ex2_xer_ca_en_q; // input=>dec_alu_ex1_xer_ca_en ,act=>dec_alu_ex1_act + wire ex3_add_ca_q; // input=>ex2_add_ca ,act=>ex2_act_q + wire ex2_add_ca; + wire ex3_add_ovf_q; // input=>ex2_add_ovf ,act=>ex2_act_q + wire ex2_add_ovf; + wire ex3_sel_rot_log_q; // input=>ex2_sel_rot_log ,act=>ex2_act_q + wire ex2_sel_rot_log; + wire [0:9] ex3_xer_q; // input=>byp_alu_ex2_xer(0 to 9) ,act=>ex2_act_q + wire ex3_xer_ov_en_q; // input=>ex2_xer_ov_en_q ,act=>ex2_act_q + wire ex3_xer_ca_en_q; // input=>ex2_xer_ca_en_q ,act=>ex2_act_q + // Scanchains + localparam ex2_act_offset = 3; + localparam ex2_sel_isel_offset = ex2_act_offset + 1; + localparam ex2_msb_64b_sel_offset = ex2_sel_isel_offset + 1; + localparam ex2_sel_trap_offset = ex2_msb_64b_sel_offset + 1; + localparam ex2_sel_cmpl_offset = ex2_sel_trap_offset + 1; + localparam ex2_sel_cmp_offset = ex2_sel_cmpl_offset + 1; + localparam ex2_instr_6to10_offset = ex2_sel_cmp_offset + 1; + localparam ex2_xer_ov_en_offset = ex2_instr_6to10_offset + 5; + localparam ex2_xer_ca_en_offset = ex2_xer_ov_en_offset + 1; + localparam ex3_add_ca_offset = ex2_xer_ca_en_offset + 1; + localparam ex3_add_ovf_offset = ex3_add_ca_offset + 1; + localparam ex3_sel_rot_log_offset = ex3_add_ovf_offset + 1; + localparam ex3_xer_offset = ex3_sel_rot_log_offset + 1; + localparam ex3_xer_ov_en_offset = ex3_xer_offset + 10; + localparam ex3_xer_ca_en_offset = ex3_xer_ov_en_offset + 1; + localparam scan_right = ex3_xer_ca_en_offset + 1; + wire [0:scan_right-1] siv; + wire [0:scan_right-1] sov; + + //!! bugspray include: xu_alu.bil; + + + // Signals + wire [msb:63] ex2_add_rs1; + wire [msb:63] ex2_add_rs2; + wire [msb:63] ex2_rot_rs0_b; + wire [msb:63] ex2_rot_rs1_b; + wire [msb:63] ex2_add_rt; + wire [msb:63] ex3_alu_rt; + wire ex3_rot_ca; + wire ex3_alu_ca; + wire ex2_add_ci; + wire [0:3] ex2_isel_fcn; + wire [0:3] ex2_isel_type; + wire ex3_alu_so; + + //--------------------------------------------------------------- + // Source Buffering + //--------------------------------------------------------------- + assign ex2_add_rs1 = byp_alu_ex2_rs1; + assign ex2_add_rs2 = byp_alu_ex2_rs2; + + assign ex2_rot_rs0_b = (~byp_alu_ex2_rs1); + assign ex2_rot_rs1_b = (~byp_alu_ex2_rs2); + + //--------------------------------------------------------------- + // Target Muxing/Buffering + //--------------------------------------------------------------- + assign alu_byp_ex3_rt = ex3_alu_rt; + + assign ex3_alu_ca = (ex3_sel_rot_log_q == 1'b1) ? ex3_rot_ca : + ex3_add_ca_q; + assign alu_byp_ex3_cr[3] = ex3_alu_so; + assign alu_byp_ex3_xer[0] = ex3_alu_so; + + assign ex3_alu_so = (ex3_xer_ov_en_q == 1'b1) ? ex3_add_ovf_q | ex3_xer_q[0] : + ex3_xer_q[0]; + + assign alu_byp_ex3_xer[1] = (ex3_xer_ov_en_q == 1'b1) ? ex3_add_ovf_q : + ex3_xer_q[1]; + + assign alu_byp_ex3_xer[2] = (ex3_xer_ca_en_q == 1'b1) ? ex3_alu_ca : + ex3_xer_q[2]; + assign alu_byp_ex3_xer[3:9] = ex3_xer_q[3:9]; + + assign alu_byp_ex2_add_rt = ex2_add_rt; + + //--------------------------------------------------------------- + // Add + //--------------------------------------------------------------- + + xu_alu_add add( + .nclk(nclk), + .vdd(vdd), + .gnd(gnd), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .func_sl_force(func_sl_force), + .func_sl_thold_0_b(func_sl_thold_0_b), + .sg_0(sg_0), + .scan_in(siv[0]), + .scan_out(sov[0]), + .ex1_act(dec_alu_ex1_act), + .ex2_msb_64b_sel(ex2_msb_64b_sel_q), + .dec_alu_ex1_add_rs1_inv(dec_alu_ex1_add_rs1_inv), + .dec_alu_ex2_add_ci(ex2_add_ci), + .ex2_rs1(ex2_add_rs1), + .ex2_rs2(ex2_add_rs2), + .ex2_add_rt(ex2_add_rt), + .ex2_add_ovf(ex2_add_ovf), + .ex2_add_ca(ex2_add_ca) + ); + + //--------------------------------------------------------------- + // Rotate / Logical + //--------------------------------------------------------------- + assign ex2_add_ci = (dec_alu_ex2_add_ci_sel == 2'b10) ? byp_alu_ex2_xer[2] : + (dec_alu_ex2_add_ci_sel == 2'b01) ? 1'b1 : + 1'b0; + + tri_st_rot rot( + .nclk(nclk), + .vdd(vdd), + .gnd(gnd), + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .func_sl_force(func_sl_force), + .func_sl_thold_0_b(func_sl_thold_0_b), + .sg_0(sg_0), + .scan_in(siv[1]), + .scan_out(sov[1]), + .ex1_act(dec_alu_ex1_act), + .ex1_instr(dec_alu_ex1_instr), + .ex2_isel_fcn(ex2_isel_fcn), + .ex2_sel_rot_log(ex2_sel_rot_log), + // Source Inputs + .ex2_rs0_b(ex2_rot_rs0_b), + .ex2_rs1_b(ex2_rot_rs1_b), + // Other ALU Inputs for muxing + .ex2_alu_rt(ex2_add_rt), + // EX3 Bypass Tap + .ex3_rt(ex3_alu_rt), + .ex2_log_rt(), + // EX2 Bypass Tap (logicals only) + .ex3_xer_ca(ex3_rot_ca), + .ex3_cr_eq() + ); + + assign ex2_isel_type = {1'b0, (~(byp_alu_ex2_cr_bit)), byp_alu_ex2_cr_bit, 1'b1}; + assign ex2_isel_fcn = ex2_sel_isel_q==1'b1 ? ex2_isel_type : 4'b0; + + //--------------------------------------------------------------- + // Compare / Trap + //--------------------------------------------------------------- + + xu_alu_cmp cmp( + .nclk(nclk), + .vdd(vdd), + .gnd(gnd), + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .func_sl_force(func_sl_force), + .func_sl_thold_0_b(func_sl_thold_0_b), + .sg_0(sg_0), + .scan_in(siv[2]), + .scan_out(sov[2]), + .ex2_act(ex2_act_q), + .ex1_msb_64b_sel(dec_alu_ex1_msb_64b_sel), + .ex2_instr(ex2_instr_6to10_q), + .ex2_sel_trap(ex2_sel_trap_q), + .ex2_sel_cmpl(ex2_sel_cmpl_q), + .ex2_sel_cmp(ex2_sel_cmp_q), + .ex2_rs1_00(ex2_add_rs1[msb]), + .ex2_rs1_32(ex2_add_rs1[32]), + .ex2_rs2_00(ex2_add_rs2[msb]), + .ex2_rs2_32(ex2_add_rs2[32]), + .ex3_alu_rt(ex3_alu_rt), + .ex3_add_ca(ex3_add_ca_q), + .ex3_alu_cr(alu_byp_ex3_cr[0:2]), + .ex3_trap_val(alu_dec_ex3_trap_val) + ); + + //--------------------------------------------------------------- + // Latches + //--------------------------------------------------------------- + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_act_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_act_offset]), + .scout(sov[ex2_act_offset]), + .din(dec_alu_ex1_act), + .dout(ex2_act_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sel_isel_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(dec_alu_ex1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_sel_isel_offset]), + .scout(sov[ex2_sel_isel_offset]), + .din(dec_alu_ex1_sel_isel), + .dout(ex2_sel_isel_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_msb_64b_sel_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(dec_alu_ex1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_msb_64b_sel_offset]), + .scout(sov[ex2_msb_64b_sel_offset]), + .din(dec_alu_ex1_msb_64b_sel), + .dout(ex2_msb_64b_sel_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sel_trap_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(dec_alu_ex1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_sel_trap_offset]), + .scout(sov[ex2_sel_trap_offset]), + .din(dec_alu_ex1_sel_trap), + .dout(ex2_sel_trap_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sel_cmpl_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(dec_alu_ex1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_sel_cmpl_offset]), + .scout(sov[ex2_sel_cmpl_offset]), + .din(dec_alu_ex1_sel_cmpl), + .dout(ex2_sel_cmpl_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sel_cmp_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(dec_alu_ex1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_sel_cmp_offset]), + .scout(sov[ex2_sel_cmp_offset]), + .din(dec_alu_ex1_sel_cmp), + .dout(ex2_sel_cmp_q) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) ex2_instr_6to10_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(dec_alu_ex1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_instr_6to10_offset:ex2_instr_6to10_offset + 5 - 1]), + .scout(sov[ex2_instr_6to10_offset:ex2_instr_6to10_offset + 5 - 1]), + .din(dec_alu_ex1_instr[6:10]), + .dout(ex2_instr_6to10_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_xer_ov_en_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(dec_alu_ex1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_xer_ov_en_offset]), + .scout(sov[ex2_xer_ov_en_offset]), + .din(dec_alu_ex1_xer_ov_en), + .dout(ex2_xer_ov_en_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_xer_ca_en_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(dec_alu_ex1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_xer_ca_en_offset]), + .scout(sov[ex2_xer_ca_en_offset]), + .din(dec_alu_ex1_xer_ca_en), + .dout(ex2_xer_ca_en_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_add_ca_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_add_ca_offset]), + .scout(sov[ex3_add_ca_offset]), + .din(ex2_add_ca), + .dout(ex3_add_ca_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_add_ovf_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_add_ovf_offset]), + .scout(sov[ex3_add_ovf_offset]), + .din(ex2_add_ovf), + .dout(ex3_add_ovf_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_sel_rot_log_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_sel_rot_log_offset]), + .scout(sov[ex3_sel_rot_log_offset]), + .din(ex2_sel_rot_log), + .dout(ex3_sel_rot_log_q) + ); + + tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) ex3_xer_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_xer_offset:ex3_xer_offset + 10 - 1]), + .scout(sov[ex3_xer_offset:ex3_xer_offset + 10 - 1]), + .din(byp_alu_ex2_xer[0:9]), + .dout(ex3_xer_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_xer_ov_en_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_xer_ov_en_offset]), + .scout(sov[ex3_xer_ov_en_offset]), + .din(ex2_xer_ov_en_q), + .dout(ex3_xer_ov_en_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_xer_ca_en_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_act_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_xer_ca_en_offset]), + .scout(sov[ex3_xer_ca_en_offset]), + .din(ex2_xer_ca_en_q), + .dout(ex3_xer_ca_en_q) + ); + + assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in}; + assign scan_out = sov[0]; + +endmodule diff --git a/dev/verilog/work/xu_alu_add.v b/dev/verilog/work/xu_alu_add.v new file mode 100755 index 0000000..c569f79 --- /dev/null +++ b/dev/verilog/work/xu_alu_add.v @@ -0,0 +1,206 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: XU Adder +// +//***************************************************************************** +`include "tri_a2o.vh" +module xu_alu_add +( + //------------------------------------------------------------------- + // Clocks & Power + //------------------------------------------------------------------- + input [0:`NCLK_WIDTH-1] nclk, + inout vdd, + inout gnd, + + //------------------------------------------------------------------- + // Pervasive + //------------------------------------------------------------------- + input delay_lclkr_dc, + input mpw1_dc_b, + input mpw2_dc_b, + input func_sl_force, + input func_sl_thold_0_b, + input sg_0, + input scan_in, + output scan_out, + + //------------------------------------------------------------------- + // Decode Interface + //------------------------------------------------------------------- + input ex1_act, + input ex2_msb_64b_sel, + input [0:`GPR_WIDTH/8-1] dec_alu_ex1_add_rs1_inv, + input dec_alu_ex2_add_ci, + + //------------------------------------------------------------------- + // Bypass Interface + //------------------------------------------------------------------- + input [64-`GPR_WIDTH:63] ex2_rs1, + input [64-`GPR_WIDTH:63] ex2_rs2, + + //------------------------------------------------------------------- + // Target Data + //------------------------------------------------------------------- + (* NO_MODIFICATION="TRUE" *) // ex2_add_rt + // NET_DATA="PLANES=/C1 C2/" // ex2_add_rt + output [64-`GPR_WIDTH:63] ex2_add_rt, // Add result + (* NO_MODIFICATION="TRUE" *) // ex2_add_ovf + output ex2_add_ovf, // Add overflow + // Add carry + output ex2_add_ca +); + + + localparam msb = 64-`GPR_WIDTH; + // Latches + wire [64-`GPR_WIDTH:63] ex2_rs1_inv_b_q; //input=>ex1_rs1_inv, act=>ex1_act + wire [64-`GPR_WIDTH:63] ex1_rs1_inv; + // Scanchain + localparam ex2_rs1_inv_b_offset = 0; + localparam scan_right = ex2_rs1_inv_b_offset + `GPR_WIDTH; + wire [0:scan_right-1] siv; + wire [0:scan_right-1] sov; + // Signals + wire [0:`NCLK_WIDTH-1] ex1_rs0_inv_lclk; + wire ex1_rs0_inv_d1clk; + wire ex1_rs0_inv_d2clk; + wire [64-`GPR_WIDTH:63] ex2_rs1_b; + wire [64-`GPR_WIDTH:63] ex2_rs2_b; + wire [64-`GPR_WIDTH:63] ex2_x_b; + wire [64-`GPR_WIDTH:63] ex2_y; + wire [64-`GPR_WIDTH:63] ex2_y_b; + wire ex2_aop_00; + wire ex2_aop_32; + wire ex2_bop_00; + wire ex2_bop_32; + (* NO_MODIFICATION="TRUE" *) // ex2_sgn00_32 + wire ex2_sgn00_32; + wire ex2_sgn11_32; + (* NO_MODIFICATION="TRUE" *) // ex2_sgn00_64 + wire ex2_sgn00_64; + wire ex2_sgn11_64; + wire ex2_cout_32; + wire ex2_cout_00; + (* NO_MODIFICATION="TRUE" *) // ex2_ovf32_00_b + wire ex2_ovf32_00_b; + wire ex2_ovf32_11_b; + (* NO_MODIFICATION="TRUE" *) // ex2_ovf64_00_b + wire ex2_ovf64_00_b; + wire ex2_ovf64_11_b; + wire [64-`GPR_WIDTH:63] ex2_add_rslt; + wire [64-`GPR_WIDTH:63] ex2_rs1_inv_q; + + generate + genvar i; + for (i=0; i<`GPR_WIDTH; i=i+1) begin : ex1_rs1_inv_gen + assign ex1_rs1_inv[i] = dec_alu_ex1_add_rs1_inv[i % (`GPR_WIDTH/8)]; + end + endgenerate + + assign ex2_rs1_inv_q = (~ex2_rs1_inv_b_q); + + assign ex2_rs1_b = (~ex2_rs1); + assign ex2_rs2_b = (~ex2_rs2); + + assign ex2_x_b = ex2_rs1_b ^ ex2_rs1_inv_q; // xor2_x2m --w=12 + + assign ex2_y = (~ex2_rs2_b); // inv_x1m --w=4 + assign ex2_y_b = (~ex2_y); // inv_x2m --w=4 + + assign ex2_aop_00 = (~ex2_x_b[msb]); + assign ex2_aop_32 = (~ex2_x_b[32]); + assign ex2_bop_00 = (~ex2_y_b[msb]); + assign ex2_bop_32 = (~ex2_y_b[32]); + + tri_st_add csa( + .x_b(ex2_x_b), + .y_b(ex2_y_b), + .ci(dec_alu_ex2_add_ci), + .sum(ex2_add_rslt), + .cout_32(ex2_cout_32), + .cout_0(ex2_cout_00) + ); + + assign ex2_add_rt = ex2_add_rslt; + + // Overflow occurs when the sign bit of the inputs differs from the sign of the result + assign ex2_sgn00_32 = (~ex2_msb_64b_sel) & (~ex2_aop_32) & (~ex2_bop_32); + assign ex2_sgn11_32 = (~ex2_msb_64b_sel) & ex2_aop_32 & ex2_bop_32; + assign ex2_sgn00_64 = ex2_msb_64b_sel & (~ex2_aop_00) & (~ex2_bop_00); + assign ex2_sgn11_64 = ex2_msb_64b_sel & ex2_aop_00 & ex2_bop_00; + + assign ex2_ovf32_00_b = (~(ex2_add_rslt[32] & ex2_sgn00_32)); + assign ex2_ovf32_11_b = (~((~ex2_add_rslt[32]) & ex2_sgn11_32)); + assign ex2_ovf64_00_b = (~(ex2_add_rslt[msb] & ex2_sgn00_64)); + assign ex2_ovf64_11_b = (~((~ex2_add_rslt[msb]) & ex2_sgn11_64)); + + assign ex2_add_ovf = (~(ex2_ovf64_00_b & ex2_ovf64_11_b & ex2_ovf32_00_b & ex2_ovf32_11_b)); + + //------------------------------------------------------------------- + // Latch instances + //------------------------------------------------------------------- + + assign ex2_add_ca = (ex2_msb_64b_sel == 1'b1) ? ex2_cout_00 : ex2_cout_32; + + tri_lcbnd ex1_rs0_inv_lcb( + .vd(vdd), + .gd(gnd), + .act(ex1_act), + .nclk(nclk), + .force_t(func_sl_force), + .thold_b(func_sl_thold_0_b), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .sg(sg_0), + .lclk(ex1_rs0_inv_lclk), + .d1clk(ex1_rs0_inv_d1clk), + .d2clk(ex1_rs0_inv_d2clk) + ); + + tri_inv_nlats #(.WIDTH(`GPR_WIDTH), .BTR("NLI0001_X1_A12TH"), .INIT(0)) ex1_rs0_inv_b_latch( + .vd(vdd), + .gd(gnd), + .lclk(ex1_rs0_inv_lclk), + .d1clk(ex1_rs0_inv_d1clk), + .d2clk(ex1_rs0_inv_d2clk), + .scanin(siv[ex2_rs1_inv_b_offset:ex2_rs1_inv_b_offset + `GPR_WIDTH - 1]), + .scanout(sov[ex2_rs1_inv_b_offset:ex2_rs1_inv_b_offset + `GPR_WIDTH - 1]), + .d(ex1_rs1_inv), + .qb(ex2_rs1_inv_b_q) + ); + + assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in}; + assign scan_out = sov[0]; + + +endmodule diff --git a/dev/verilog/work/xu_alu_cmp.v b/dev/verilog/work/xu_alu_cmp.v new file mode 100755 index 0000000..7ba95ca --- /dev/null +++ b/dev/verilog/work/xu_alu_cmp.v @@ -0,0 +1,334 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: XU ALU Compare +// +//***************************************************************************** +`include "tri_a2o.vh" +module xu_alu_cmp( + // Clocks + input [0:`NCLK_WIDTH-1] nclk, + + // Power + inout vdd, + inout gnd, + + // Pervasive + input d_mode_dc, + input delay_lclkr_dc, + input mpw1_dc_b, + input mpw2_dc_b, + input func_sl_force, + input func_sl_thold_0_b, + input sg_0, + input scan_in, + output scan_out, + + input ex2_act, + + input ex1_msb_64b_sel, + + input [6:10] ex2_instr, + input ex2_sel_trap, + input ex2_sel_cmpl, + input ex2_sel_cmp, + + input ex2_rs1_00, + input ex2_rs1_32, + + input ex2_rs2_00, + input ex2_rs2_32, + + input [64-`GPR_WIDTH:63] ex3_alu_rt, + input ex3_add_ca, + + output [0:2] ex3_alu_cr, + + output ex3_trap_val +); + localparam msb = 64 - `GPR_WIDTH; + // Latches + wire ex2_msb_64b_sel_q; // input=>ex1_msb_64b_sel ,act=>1'b1 + wire ex3_msb_64b_sel_q; // input=>ex2_msb_64b_sel_q ,act=>ex2_act + wire ex3_diff_sign_q; // input=>ex2_diff_sign ,act=>ex2_act + wire ex2_diff_sign; + wire ex3_rs1_trm1_q; // input=>ex2_rs1_trm1 ,act=>ex2_act + wire ex2_rs1_trm1; + wire ex3_rs2_trm1_q; // input=>ex2_rs2_trm1 ,act=>ex2_act + wire ex2_rs2_trm1; + wire [6:10] ex3_instr_q; // input=>ex2_instr ,act=>ex2_act + wire ex3_sel_trap_q; // input=>ex2_sel_trap ,act=>ex2_act + wire ex3_sel_cmpl_q; // input=>ex2_sel_cmpl ,act=>ex2_act + wire ex3_sel_cmp_q; // input=>ex2_sel_cmp ,act=>ex2_act + // Scanchains + localparam ex2_msb_64b_sel_offset = 0; + localparam ex3_msb_64b_sel_offset = ex2_msb_64b_sel_offset + 1; + localparam ex3_diff_sign_offset = ex3_msb_64b_sel_offset + 1; + localparam ex3_rs1_trm1_offset = ex3_diff_sign_offset + 1; + localparam ex3_rs2_trm1_offset = ex3_rs1_trm1_offset + 1; + localparam ex3_instr_offset = ex3_rs2_trm1_offset + 1; + localparam ex3_sel_trap_offset = ex3_instr_offset + 5; + localparam ex3_sel_cmpl_offset = ex3_sel_trap_offset + 1; + localparam ex3_sel_cmp_offset = ex3_sel_cmpl_offset + 1; + localparam scan_right = ex3_sel_cmp_offset + 1; + wire [0:scan_right-1] siv; + wire [0:scan_right-1] sov; + // Signals + wire ex3_cmp0_hi; + wire ex3_cmp0_lo; + wire ex3_cmp0_eq; + wire ex2_rs1_msb; + wire ex2_rs2_msb; + wire ex3_rt_msb; + wire ex3_rslt_gt_s; + wire ex3_rslt_lt_s; + wire ex3_rslt_gt_u; + wire ex3_rslt_lt_u; + wire ex3_cmp_eq; + wire ex3_cmp_gt; + wire ex3_cmp_lt; + wire ex3_sign_cmp; + + + tri_st_or3232 or3232( + .d(ex3_alu_rt), + .or_hi_b(ex3_cmp0_hi), + .or_lo_b(ex3_cmp0_lo) + ); + + assign ex2_rs1_msb = (ex2_msb_64b_sel_q == 1'b1) ? ex2_rs1_00 : ex2_rs1_32; + + assign ex2_rs2_msb = (ex2_msb_64b_sel_q == 1'b1) ? ex2_rs2_00 : ex2_rs2_32; + + assign ex3_rt_msb = (ex3_msb_64b_sel_q == 1'b1) ? ex3_alu_rt[msb] : ex3_alu_rt[32]; + + // If the signs are different, then we immediately know if one is bigger than the other. + // but only look at this in case of compare instructions + assign ex3_cmp0_eq = (ex3_msb_64b_sel_q == 1'b1) ? (ex3_cmp0_lo & ex3_cmp0_hi) : ex3_cmp0_lo; + + assign ex2_diff_sign = (ex2_rs1_msb ^ ex2_rs2_msb) & (ex2_sel_cmpl | ex2_sel_cmp | ex2_sel_trap); + + // In case the sigs are not different, we need some more logic + // Look at adder carry out for compares (need to be able to check over flow case) + // Look at sign bit for record forms (overflow is ignored, ie two positives equal a negative.) + + assign ex3_sign_cmp = ((ex3_sel_cmpl_q | ex3_sel_cmp_q | ex3_sel_trap_q) == 1'b1) ? ex3_add_ca : ex3_rt_msb; + assign ex2_rs1_trm1 = ex2_rs1_msb & ex2_diff_sign; + assign ex2_rs2_trm1 = ex2_rs2_msb & ex2_diff_sign; + + // Signed compare + assign ex3_rslt_gt_s = (ex3_rs2_trm1_q | (~ex3_sign_cmp & ~ex3_diff_sign_q)); // RS2 < RS1 + assign ex3_rslt_lt_s = (ex3_rs1_trm1_q | ( ex3_sign_cmp & ~ex3_diff_sign_q)); // RS2 > RS1 + // Unsigned compare + assign ex3_rslt_gt_u = (ex3_rs1_trm1_q | (~ex3_sign_cmp & ~ex3_diff_sign_q)); // RS2 < RS1 + assign ex3_rslt_lt_u = (ex3_rs2_trm1_q | ( ex3_sign_cmp & ~ex3_diff_sign_q)); // RS2 > RS1 + + assign ex3_cmp_eq = ex3_cmp0_eq; + assign ex3_cmp_gt = ((~ex3_sel_cmpl_q & ex3_rslt_gt_s) | (ex3_sel_cmpl_q & ex3_rslt_gt_u)) & (~ex3_cmp0_eq); + assign ex3_cmp_lt = ((~ex3_sel_cmpl_q & ex3_rslt_lt_s) | (ex3_sel_cmpl_q & ex3_rslt_lt_u)) & (~ex3_cmp0_eq); + + // CR Field for Add, Logical, Rotate + assign ex3_alu_cr = {ex3_cmp_lt, ex3_cmp_gt, ex3_cmp_eq}; + + // Trap logic + assign ex3_trap_val = ex3_sel_trap_q & + ((ex3_instr_q[6] & (~ex3_cmp_eq) & ex3_rslt_lt_s) | + (ex3_instr_q[7] & (~ex3_cmp_eq) & ex3_rslt_gt_s) | + (ex3_instr_q[8] & ex3_cmp_eq) | + (ex3_instr_q[9] & (~ex3_cmp_eq) & ex3_rslt_lt_u) | + (ex3_instr_q[10] & (~ex3_cmp_eq) & ex3_rslt_gt_u)); + + // Latch Instances + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_msb_64b_sel_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_msb_64b_sel_offset]), + .scout(sov[ex2_msb_64b_sel_offset]), + .din(ex1_msb_64b_sel), + .dout(ex2_msb_64b_sel_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_msb_64b_sel_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_msb_64b_sel_offset]), + .scout(sov[ex3_msb_64b_sel_offset]), + .din(ex2_msb_64b_sel_q), + .dout(ex3_msb_64b_sel_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_diff_sign_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_diff_sign_offset]), + .scout(sov[ex3_diff_sign_offset]), + .din(ex2_diff_sign), + .dout(ex3_diff_sign_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_rs1_trm1_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_rs1_trm1_offset]), + .scout(sov[ex3_rs1_trm1_offset]), + .din(ex2_rs1_trm1), + .dout(ex3_rs1_trm1_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_rs2_trm1_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_rs2_trm1_offset]), + .scout(sov[ex3_rs2_trm1_offset]), + .din(ex2_rs2_trm1), + .dout(ex3_rs2_trm1_q) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) ex3_instr_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_instr_offset:ex3_instr_offset + 5 - 1]), + .scout(sov[ex3_instr_offset:ex3_instr_offset + 5 - 1]), + .din(ex2_instr), + .dout(ex3_instr_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_sel_trap_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_sel_trap_offset]), + .scout(sov[ex3_sel_trap_offset]), + .din(ex2_sel_trap), + .dout(ex3_sel_trap_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_sel_cmpl_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_sel_cmpl_offset]), + .scout(sov[ex3_sel_cmpl_offset]), + .din(ex2_sel_cmpl), + .dout(ex3_sel_cmpl_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_sel_cmp_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(ex2_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_sel_cmp_offset]), + .scout(sov[ex3_sel_cmp_offset]), + .din(ex2_sel_cmp), + .dout(ex3_sel_cmp_q) + ); + + assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in}; + assign scan_out = sov[0]; + +endmodule diff --git a/dev/verilog/work/xu_fctr.v b/dev/verilog/work/xu_fctr.v new file mode 100755 index 0000000..2ff030a --- /dev/null +++ b/dev/verilog/work/xu_fctr.v @@ -0,0 +1,135 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: XU CPL - Configurable Flush Delay Counter +// +//***************************************************************************** +`include "tri_a2o.vh" + +module xu_fctr +#( + parameter CLOCKGATE = 1, + parameter PASSTHRU = 1, + parameter DELAY_WIDTH = 4, + parameter WIDTH = 2 +) +( + input [0:`NCLK_WIDTH-1] nclk, + + input force_t, + input thold_b, + input sg, + input d_mode, + input delay_lclkr, + input mpw1_b, + input mpw2_b, + + input scin, + output scout, + + input [0:WIDTH-1] din, + output [0:WIDTH-1] dout, + input [0:DELAY_WIDTH-1] delay, + + inout vdd, + inout gnd +); + + + // Latches + wire [0:DELAY_WIDTH-1] delay_q[0:WIDTH-1]; + wire [0:DELAY_WIDTH-1] delay_d[0:WIDTH-1]; + // Scanchains + localparam delay_offset = 0; + localparam scan_right = delay_offset + DELAY_WIDTH*WIDTH; + wire [0:scan_right-1] siv; + wire [0:scan_right-1] sov; + // Signals + wire [0:WIDTH-1] set; + wire [0:WIDTH-1] zero_b; + wire [0:WIDTH-1] act; + + generate + genvar t; + for (t=0;t<=WIDTH-1;t=t+1) + begin : threads_gen + wire [0:DELAY_WIDTH-1] delay_m1; + + assign set[t] = din[t]; + assign zero_b[t] = |(delay_q[t]); + assign delay_m1 = delay_q[t] - {{DELAY_WIDTH-1{1'b0}},1'b1}; + + if (CLOCKGATE == 0) begin : clockgate_0 + assign act[t] = set[t] | zero_b[t]; + + assign delay_d[t] = ({set[t], zero_b[t]} == 2'b11) ? delay : + ({set[t], zero_b[t]} == 2'b10) ? delay : + ({set[t], zero_b[t]} == 2'b01) ? delay_m1 : + delay_q[t]; + end + if (CLOCKGATE == 1) begin : clockgate_1 + assign act[t] = set[t] | zero_b[t]; + + assign delay_d[t] = (set[t] == 1'b1) ? delay : + delay_m1; + end + + if (PASSTHRU == 1)begin : PASSTHRU_gen_1 + assign dout[t] = zero_b[t] | din[t]; + end + if (PASSTHRU == 0) begin : PASSTHRU_gen_0 + assign dout[t] = zero_b[t]; + end + + + tri_rlmreg_p #(.WIDTH(DELAY_WIDTH), .INIT(0), .NEEDS_SRESET(1)) delay_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(act[t]), + .force_t(force_t), + .d_mode(d_mode), + .delay_lclkr(delay_lclkr), + .mpw1_b(mpw1_b), + .mpw2_b(mpw2_b), + .thold_b(thold_b), + .sg(sg), + .scin(siv[delay_offset+DELAY_WIDTH*t:delay_offset+DELAY_WIDTH*(t+1)-1]), + .scout(sov[delay_offset+DELAY_WIDTH*t:delay_offset+DELAY_WIDTH*(t+1)-1]), + .din(delay_d[t]), + .dout(delay_q[t]) + ); + end + endgenerate + +assign siv[0:scan_right - 1] = {sov[1:scan_right - 1], scin}; +assign scout = sov[0]; + +endmodule diff --git a/dev/verilog/work/xu_gpr.v b/dev/verilog/work/xu_gpr.v new file mode 100755 index 0000000..21e8ba5 --- /dev/null +++ b/dev/verilog/work/xu_gpr.v @@ -0,0 +1,271 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: XU_FX ALU Top +// +//***************************************************************************** +`include "tri_a2o.vh" +module xu_gpr( + //------------------------------------------------------------------- + // Clocks & Power + //------------------------------------------------------------------- + input [0:`NCLK_WIDTH-1] nclk, + inout vdd, + inout gnd, + + //------------------------------------------------------------------- + // Pervasive + //------------------------------------------------------------------- + input pc_xu_ccflush_dc, + input d_mode_dc, + input delay_lclkr_dc, + input mpw1_dc_b, + input mpw2_dc_b, + input func_sl_force, + input func_sl_thold_0_b, + input sg_0, + input scan_in, + output scan_out, + + //------------------------------------------------------------------- + // Read Ports + //------------------------------------------------------------------- + input r0e, + input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r0a, + output [64-`GPR_WIDTH:63] r0d, + input r1e, + input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r1a, + output [64-`GPR_WIDTH:63] r1d, + input r2e, + input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r2a, + output [64-`GPR_WIDTH:63] r2d, + input r3e, + input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r3a, + output [64-`GPR_WIDTH:63] r3d, + + // Special Port for 3src instructions- erativax + input r4e, + input [0:2] r4t_q, + input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r4a, + + output r0_pe, + output r1_pe, + output r2_pe, + output r3_pe, + //------------------------------------------------------------------- + // Write ports + //------------------------------------------------------------------- + input w0e, + input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w0a, + input [64-`GPR_WIDTH:65+`GPR_WIDTH/8] w0d, + input w1e, + input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w1a, + input [64-`GPR_WIDTH:65+`GPR_WIDTH/8] w1d, + input w2e, + input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w2a, + input [64-`GPR_WIDTH:65+`GPR_WIDTH/8] w2d, + input w3e, + input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w3a, + input [64-`GPR_WIDTH:65+`GPR_WIDTH/8] w3d +); + + // Latches + wire r4e_q; // input=>r4e ,act=>1'b1 + wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r4a_q; // input=>r4a ,act=>1'b1 + // Scanchain + localparam r4e_offset = 2; + localparam r4a_offset = r4e_offset + 1; + localparam scan_right = r4a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC; + wire [0:scan_right-1] siv; + wire [0:scan_right-1] sov; + // Signals + wire [64-`GPR_WIDTH:77] w0d_int; + wire [64-`GPR_WIDTH:77] w1d_int; + wire [64-`GPR_WIDTH:77] w2d_int; + wire [64-`GPR_WIDTH:77] w3d_int; + wire [64-`GPR_WIDTH:77] r0d_int; + wire [64-`GPR_WIDTH:77] r1d_int; + wire [64-`GPR_WIDTH:77] r2d_int; + wire [64-`GPR_WIDTH:77] r3d_int; + wire [0:`GPR_WIDTH/8-1] r0d_par; + wire [0:`GPR_WIDTH/8-1] r1d_par; + wire [0:`GPR_WIDTH/8-1] r2d_par; + wire [0:`GPR_WIDTH/8-1] r3d_par; + wire r0e_int; + wire r4e_sel; + wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r0a_int; + + assign r4e_sel = r4e_q & ~|r4t_q; + + assign r0e_int = r4e_sel | r0e; + + assign r0a_int = (r4e_sel == 1'b1) ? r4a_q : r0a; + + assign r0d = r0d_int[64 - `GPR_WIDTH:63]; + assign r1d = r1d_int[64 - `GPR_WIDTH:63]; + assign r2d = r2d_int[64 - `GPR_WIDTH:63]; + assign r3d = r3d_int[64 - `GPR_WIDTH:63]; + + assign w0d_int[64 - `GPR_WIDTH:65 + `GPR_WIDTH/8] = w0d; + assign w0d_int[66 + `GPR_WIDTH/8:77] = {4{1'b0}}; + assign w1d_int[64 - `GPR_WIDTH:65 + `GPR_WIDTH/8] = w1d; + assign w1d_int[66 + `GPR_WIDTH/8:77] = {4{1'b0}}; + assign w2d_int[64 - `GPR_WIDTH:65 + `GPR_WIDTH/8] = w2d; + assign w2d_int[66 + `GPR_WIDTH/8:77] = {4{1'b0}}; + assign w3d_int[64 - `GPR_WIDTH:65 + `GPR_WIDTH/8] = w3d; + assign w3d_int[66 + `GPR_WIDTH/8:77] = {4{1'b0}}; + + generate + genvar i; + for (i = 0; i <= `GPR_WIDTH/8 - 1; i = i + 1) + begin : parity + assign r0d_par[i] = ^(r0d_int[8 * i:8 * i + 7]); + assign r1d_par[i] = ^(r1d_int[8 * i:8 * i + 7]); + assign r2d_par[i] = ^(r2d_int[8 * i:8 * i + 7]); + assign r3d_par[i] = ^(r3d_int[8 * i:8 * i + 7]); + end + endgenerate + + assign r0_pe = r0e & (r0d_par != r0d_int[64:63 + `GPR_WIDTH/8]); + assign r1_pe = r1e & (r1d_par != r1d_int[64:63 + `GPR_WIDTH/8]); + assign r2_pe = r2e & (r2d_par != r2d_int[64:63 + `GPR_WIDTH/8]); + assign r3_pe = r3e & (r3d_par != r3d_int[64:63 + `GPR_WIDTH/8]); + + + tri_144x78_2r4w gpr0( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .func_sl_force(func_sl_force), + .func_sl_thold_0_b(func_sl_thold_0_b), + .func_slp_sl_force(func_sl_force), + .func_slp_sl_thold_0_b(func_sl_thold_0_b), + .sg_0(sg_0), + .scan_in(siv[0]), + .scan_out(sov[0]), + .r_late_en_1(r0e_int), + .r_addr_in_1(r0a_int), + .r_data_out_1(r0d_int), + .r_late_en_2(r1e), + .r_addr_in_2(r1a), + .r_data_out_2(r1d_int), + .w_late_en_1(w0e), + .w_addr_in_1(w0a), + .w_data_in_1(w0d_int), + .w_late_en_2(w1e), + .w_addr_in_2(w1a), + .w_data_in_2(w1d_int), + .w_late_en_3(w2e), + .w_addr_in_3(w2a), + .w_data_in_3(w2d_int), + .w_late_en_4(w3e), + .w_addr_in_4(w3a), + .w_data_in_4(w3d_int) + ); + + + tri_144x78_2r4w gpr1( + .vdd(vdd), + .gnd(gnd), + .nclk(nclk), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .func_sl_force(func_sl_force), + .func_sl_thold_0_b(func_sl_thold_0_b), + .func_slp_sl_force(func_sl_force), + .func_slp_sl_thold_0_b(func_sl_thold_0_b), + .sg_0(sg_0), + .scan_in(siv[1]), + .scan_out(sov[1]), + .r_late_en_1(r2e), + .r_addr_in_1(r2a), + .r_data_out_1(r2d_int), + .r_late_en_2(r3e), + .r_addr_in_2(r3a), + .r_data_out_2(r3d_int), + .w_late_en_1(w0e), + .w_addr_in_1(w0a), + .w_data_in_1(w0d_int), + .w_late_en_2(w1e), + .w_addr_in_2(w1a), + .w_data_in_2(w1d_int), + .w_late_en_3(w2e), + .w_addr_in_3(w2a), + .w_data_in_3(w2d_int), + .w_late_en_4(w3e), + .w_addr_in_4(w3a), + .w_data_in_4(w3d_int) + ); + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) r4e_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[r4e_offset]), + .scout(sov[r4e_offset]), + .din(r4e), + .dout(r4e_q) + ); + + tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) r4a_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[r4a_offset:r4a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]), + .scout(sov[r4a_offset:r4a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]), + .din(r4a), + .dout(r4a_q) + ); + + assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in}; + assign scan_out = sov[0]; + +endmodule diff --git a/dev/verilog/work/xu_rf.v b/dev/verilog/work/xu_rf.v new file mode 100755 index 0000000..889891f --- /dev/null +++ b/dev/verilog/work/xu_rf.v @@ -0,0 +1,1132 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: Register File Array +// +//***************************************************************************** + +`include "tri_a2o.vh" + +module xu_rf +#( + parameter PAR_WIDTH = 1, + parameter WIDTH = 8, + parameter POOL_ENC = 5, + parameter POOL = 24, + parameter RD_PORTS = 1, + parameter WR_PORTS = 1, + parameter BYPASS = 1 +) +( + //------------------------------------------------------------------- + // Clocks & Power + //------------------------------------------------------------------- + (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) // nclk + input [0:`NCLK_WIDTH-1] nclk, + inout vdd, + inout gnd, + + //------------------------------------------------------------------- + // Pervasive + //------------------------------------------------------------------- + input d_mode_dc, + input delay_lclkr_dc, + input mpw1_dc_b, + input mpw2_dc_b, + input func_sl_force, + input func_sl_thold_0_b, + input func_nsl_force, + input func_nsl_thold_0_b, + input sg_0, + input scan_in, + output scan_out, + + //------------------------------------------------------------------- + // Read Ports + //------------------------------------------------------------------- + input r0e_e, + input r0e, + input [0:POOL_ENC-1] r0a, + output [0:WIDTH-1] r0d, + + input r1e_e, + input r1e, + input [0:POOL_ENC-1] r1a, + output [0:WIDTH-1] r1d, + + input r2e_e, + input r2e, + input [0:POOL_ENC-1] r2a, + output [0:WIDTH-1] r2d, + + input r3e_e, + input r3e, + input [0:POOL_ENC-1] r3a, + output [0:WIDTH-1] r3d, + + input r4e_e, + input r4e, + input [0:POOL_ENC-1] r4a, + output [0:WIDTH-1] r4d, + + //------------------------------------------------------------------- + // Write ports + //------------------------------------------------------------------- + input w0e_e, + input w0e, + input [0:POOL_ENC-1] w0a, + input [0:WIDTH-1] w0d, + + input w1e_e, + input w1e, + input [0:POOL_ENC-1] w1a, + input [0:WIDTH-1] w1d, + + input w2e_e, + input w2e, + input [0:POOL_ENC-1] w2a, + input [0:WIDTH-1] w2d, + + input w3e_e, + input w3e, + input [0:POOL_ENC-1] w3a, + input [0:WIDTH-1] w3d, + + input w4e_e, + input w4e, + input [0:POOL_ENC-1] w4a, + + input [0:WIDTH-1] w4d +); + + localparam USE_R0 = {31'b0,(RD_PORTS > 0)}; + localparam USE_R1 = {31'b0,(RD_PORTS > 1)}; + localparam USE_R2 = {31'b0,(RD_PORTS > 2)}; + localparam USE_R3 = {31'b0,(RD_PORTS > 3)}; + localparam USE_R4 = {31'b0,(RD_PORTS > 4)}; + localparam USE_W0 = {31'b0,(WR_PORTS > 0)}; + localparam USE_W1 = {31'b0,(WR_PORTS > 1)}; + localparam USE_W2 = {31'b0,(WR_PORTS > 2)}; + localparam USE_W3 = {31'b0,(WR_PORTS > 3)}; + localparam USE_W4 = {31'b0,(WR_PORTS > 4)}; + + wire [0:WIDTH-1] reg_q[0:POOL-1]; + + reg [0:WIDTH-1] reg_d[0:POOL-1] ; // input=>par_d[r] ,act=>reg_act[r] + wire r0e_q ; // input=>r0e ,act=>1'b1 + wire [0:POOL_ENC-1] r0a_q ; // input=>r0a ,act=>r0e_e + wire [0:WIDTH-1] r0d_q, r0d_d ; // input=>r0d ,act=>r0e_q + wire r1e_q ; // input=>r1e ,act=>1'b1 + wire [0:POOL_ENC-1] r1a_q ; // input=>r1a ,act=>r1e_e + wire [0:WIDTH-1] r1d_q, r1d_d ; // input=>r1d ,act=>r1e_q + wire r2e_q ; // input=>r2e ,act=>1'b1 + wire [0:POOL_ENC-1] r2a_q ; // input=>r2a ,act=>r2e_e + wire [0:WIDTH-1] r2d_q, r2d_d ; // input=>r2d ,act=>r2e_q + wire r3e_q ; // input=>r3e ,act=>1'b1 + wire [0:POOL_ENC-1] r3a_q ; // input=>r3a ,act=>r3e_e + wire [0:WIDTH-1] r3d_q, r3d_d ; // input=>r3d ,act=>r3e_q + wire r4e_q ; // input=>r4e ,act=>1'b1 + wire [0:POOL_ENC-1] r4a_q ; // input=>r4a ,act=>r4e_e + wire [0:WIDTH-1] r4d_q, r4d_d ; // input=>r4d ,act=>r4e_q + wire w0e_q ; // input=>w0e ,act=>1'b1 + wire [0:POOL_ENC-1] w0a_q ; // input=>w0a ,act=>w0e_e + wire [0:WIDTH-1] w0d_q ; // input=>w0d ,act=>w0e_e + wire w1e_q ; // input=>w1e ,act=>1'b1 + wire [0:POOL_ENC-1] w1a_q ; // input=>w1a ,act=>w1e_e + wire [0:WIDTH-1] w1d_q ; // input=>w1d ,act=>w1e_e + wire w2e_q ; // input=>w2e ,act=>1'b1 + wire [0:POOL_ENC-1] w2a_q ; // input=>w2a ,act=>w2e_e + wire [0:WIDTH-1] w2d_q ; // input=>w2d ,act=>w2e_e + wire w3e_q ; // input=>w3e ,act=>1'b1 + wire [0:POOL_ENC-1] w3a_q ; // input=>w3a ,act=>w3e_e + wire [0:WIDTH-1] w3d_q ; // input=>w3d ,act=>w3e_e + wire w4e_q ; // input=>w4e ,act=>1'b1 + wire [0:POOL_ENC-1] w4a_q ; // input=>w4a ,act=>w4e_e + wire [0:WIDTH-1] w4d_q ; // input=>w4d ,act=>w4e_e + // Scanchain + localparam reg_offset = 0; + localparam r0e_offset = reg_offset + WIDTH*POOL; + localparam r0a_offset = r0e_offset + 1 * USE_R0; + localparam r0d_offset = r0a_offset + POOL_ENC * USE_R0; + localparam r1e_offset = r0d_offset + WIDTH * USE_R0; + localparam r1a_offset = r1e_offset + 1 * USE_R1; + localparam r1d_offset = r1a_offset + POOL_ENC * USE_R1; + localparam r2e_offset = r1d_offset + WIDTH * USE_R1; + localparam r2a_offset = r2e_offset + 1 * USE_R2; + localparam r2d_offset = r2a_offset + POOL_ENC * USE_R2; + localparam r3e_offset = r2d_offset + WIDTH * USE_R2; + localparam r3a_offset = r3e_offset + 1 * USE_R3; + localparam r3d_offset = r3a_offset + POOL_ENC * USE_R3; + localparam r4e_offset = r3d_offset + WIDTH * USE_R3; + localparam r4a_offset = r4e_offset + 1 * USE_R4; + localparam r4d_offset = r4a_offset + POOL_ENC * USE_R4; + localparam w0e_offset = r4d_offset + WIDTH * USE_R4; + localparam w0a_offset = w0e_offset + 1 * USE_W0; + localparam w0d_offset = w0a_offset + POOL_ENC * USE_W0; + localparam w1e_offset = w0d_offset + WIDTH * USE_W0; + localparam w1a_offset = w1e_offset + 1 * USE_W1; + localparam w1d_offset = w1a_offset + POOL_ENC * USE_W1; + localparam w2e_offset = w1d_offset + WIDTH * USE_W1; + localparam w2a_offset = w2e_offset + 1 * USE_W2; + localparam w2d_offset = w2a_offset + POOL_ENC * USE_W2; + localparam w3e_offset = w2d_offset + WIDTH * USE_W2; + localparam w3a_offset = w3e_offset + 1 * USE_W3; + localparam w3d_offset = w3a_offset + POOL_ENC * USE_W3; + localparam w4e_offset = w3d_offset + WIDTH * USE_W3; + localparam w4a_offset = w4e_offset + 1 * USE_W4; + localparam w4d_offset = w4a_offset + POOL_ENC * USE_W4; + localparam scan_right = w4d_offset + WIDTH * USE_W4; + wire [0:scan_right-1] siv; + wire [0:scan_right-1] sov; + // Signals + reg [0:POOL-1] reg_act; + reg [0:WIDTH-1] r0d_array; + reg [0:WIDTH-1] r1d_array; + reg [0:WIDTH-1] r2d_array; + reg [0:WIDTH-1] r3d_array; + reg [0:WIDTH-1] r4d_array; + + (* analysis_not_assigned="true" *) + (* analysis_not_referenced="true" *) + wire [0:7] unused; + + //!! Bugspray Include: xu_rf; + +always @* +begin: write + integer i; + reg_act = 0; + + for (i=0;i<=POOL-1;i=i+1) + begin + reg_d[i] = reg_q[i]; + + if (w0e_q == 1'b1 & {{32-POOL_ENC{1'b0}},w0a_q} == i) + begin + reg_act[i] = 1'b1; + reg_d[i] = w0d_q; + end + + if (w1e_q == 1'b1 & {{32-POOL_ENC{1'b0}},w1a_q} == i) + begin + reg_act[i] = 1'b1; + reg_d[i] = w1d_q; + end + + if (w2e_q == 1'b1 & {{32-POOL_ENC{1'b0}},w2a_q} == i) + begin + reg_act[i] = 1'b1; + reg_d[i] = w2d_q; + end + + if (w3e_q == 1'b1 & {{32-POOL_ENC{1'b0}},w3a_q} == i) + begin + reg_act[i] = 1'b1; + reg_d[i] = w3d_q; + end + + if (w4e_q == 1'b1 & {{32-POOL_ENC{1'b0}},w4a_q} == i) + begin + reg_act[i] = 1'b1; + reg_d[i] = w4d_q; + end + end + +end + + +always @* +begin: read + integer i; + r0d_array = 0; + r1d_array = 0; + r2d_array = 0; + r3d_array = 0; + r4d_array = 0; + + for (i=0;i<=POOL-1;i=i+1) + begin + if (USE_R0 == 1 & {{32-POOL_ENC{1'b0}},r0a_q} == i) + begin + r0d_array = reg_q[i]; + end + if (USE_R1 == 1 & {{32-POOL_ENC{1'b0}},r1a_q} == i) + begin + r1d_array = reg_q[i]; + end + if (USE_R2 == 1 & {{32-POOL_ENC{1'b0}},r2a_q} == i) + begin + r2d_array = reg_q[i]; + end + if (USE_R3 == 1 & {{32-POOL_ENC{1'b0}},r3a_q} == i) + begin + r3d_array = reg_q[i]; + end + if (USE_R4 == 1 & {{32-POOL_ENC{1'b0}},r4a_q} == i) + begin + r4d_array = reg_q[i]; + end + end +end + +// BYPASS + +generate + if (BYPASS == 1) + begin : read_bypass + wire [0:10] r0_byp_sel; + wire [0:10] r1_byp_sel; + wire [0:10] r2_byp_sel; + wire [0:10] r3_byp_sel; + wire [0:10] r4_byp_sel; + assign r0_byp_sel[0] = w0e_q & (w0a_q == r0a_q); + assign r0_byp_sel[1] = w1e_q & (w1a_q == r0a_q); + assign r0_byp_sel[2] = w2e_q & (w2a_q == r0a_q); + assign r0_byp_sel[3] = w3e_q & (w3a_q == r0a_q); + assign r0_byp_sel[4] = w4e_q & (w4a_q == r0a_q); + assign r0_byp_sel[5] = w0e & (w0a == r0a_q); + assign r0_byp_sel[6] = w1e & (w1a == r0a_q); + assign r0_byp_sel[7] = w2e & (w2a == r0a_q); + assign r0_byp_sel[8] = w3e & (w3a == r0a_q); + assign r0_byp_sel[9] = w4e & (w4a == r0a_q); + assign r0_byp_sel[10] = (~|(r0_byp_sel[0:9])); + + assign r0d_d = (w0d_q & {WIDTH{r0_byp_sel[0]}}) | + (w1d_q & {WIDTH{r0_byp_sel[1]}}) | + (w2d_q & {WIDTH{r0_byp_sel[2]}}) | + (w3d_q & {WIDTH{r0_byp_sel[3]}}) | + (w4d_q & {WIDTH{r0_byp_sel[4]}}) | + (w0d & {WIDTH{r0_byp_sel[5]}}) | + (w1d & {WIDTH{r0_byp_sel[6]}}) | + (w2d & {WIDTH{r0_byp_sel[7]}}) | + (w3d & {WIDTH{r0_byp_sel[8]}}) | + (w4d & {WIDTH{r0_byp_sel[9]}}) | + (r0d_array & {WIDTH{r0_byp_sel[10]}}); + + assign r1_byp_sel[0] = w0e_q & (w0a_q == r1a_q); + assign r1_byp_sel[1] = w1e_q & (w1a_q == r1a_q); + assign r1_byp_sel[2] = w2e_q & (w2a_q == r1a_q); + assign r1_byp_sel[3] = w3e_q & (w3a_q == r1a_q); + assign r1_byp_sel[4] = w4e_q & (w4a_q == r1a_q); + assign r1_byp_sel[5] = w0e & (w0a == r1a_q); + assign r1_byp_sel[6] = w1e & (w1a == r1a_q); + assign r1_byp_sel[7] = w2e & (w2a == r1a_q); + assign r1_byp_sel[8] = w3e & (w3a == r1a_q); + assign r1_byp_sel[9] = w4e & (w4a == r1a_q); + assign r1_byp_sel[10] = (~|(r1_byp_sel[0:9])); + + assign r1d_d = (w0d_q & {WIDTH{r1_byp_sel[0]}}) | + (w1d_q & {WIDTH{r1_byp_sel[1]}}) | + (w2d_q & {WIDTH{r1_byp_sel[2]}}) | + (w3d_q & {WIDTH{r1_byp_sel[3]}}) | + (w4d_q & {WIDTH{r1_byp_sel[4]}}) | + (w0d & {WIDTH{r1_byp_sel[5]}}) | + (w1d & {WIDTH{r1_byp_sel[6]}}) | + (w2d & {WIDTH{r1_byp_sel[7]}}) | + (w3d & {WIDTH{r1_byp_sel[8]}}) | + (w4d & {WIDTH{r1_byp_sel[9]}}) | + (r1d_array & {WIDTH{r1_byp_sel[10]}}); + + assign r2_byp_sel[0] = w0e_q & (w0a_q == r2a_q); + assign r2_byp_sel[1] = w1e_q & (w1a_q == r2a_q); + assign r2_byp_sel[2] = w2e_q & (w2a_q == r2a_q); + assign r2_byp_sel[3] = w3e_q & (w3a_q == r2a_q); + assign r2_byp_sel[4] = w4e_q & (w4a_q == r2a_q); + assign r2_byp_sel[5] = w0e & (w0a == r2a_q); + assign r2_byp_sel[6] = w1e & (w1a == r2a_q); + assign r2_byp_sel[7] = w2e & (w2a == r2a_q); + assign r2_byp_sel[8] = w3e & (w3a == r2a_q); + assign r2_byp_sel[9] = w4e & (w4a == r2a_q); + assign r2_byp_sel[10] = (~|(r2_byp_sel[0:9])); + + assign r2d_d = (w0d_q & {WIDTH{r2_byp_sel[0]}}) | + (w1d_q & {WIDTH{r2_byp_sel[1]}}) | + (w2d_q & {WIDTH{r2_byp_sel[2]}}) | + (w3d_q & {WIDTH{r2_byp_sel[3]}}) | + (w4d_q & {WIDTH{r2_byp_sel[4]}}) | + (w0d & {WIDTH{r2_byp_sel[5]}}) | + (w1d & {WIDTH{r2_byp_sel[6]}}) | + (w2d & {WIDTH{r2_byp_sel[7]}}) | + (w3d & {WIDTH{r2_byp_sel[8]}}) | + (w4d & {WIDTH{r2_byp_sel[9]}}) | + (r2d_array & {WIDTH{r2_byp_sel[10]}}); + + assign r3_byp_sel[0] = w0e_q & (w0a_q == r3a_q); + assign r3_byp_sel[1] = w1e_q & (w1a_q == r3a_q); + assign r3_byp_sel[2] = w2e_q & (w2a_q == r3a_q); + assign r3_byp_sel[3] = w3e_q & (w3a_q == r3a_q); + assign r3_byp_sel[4] = w4e_q & (w4a_q == r3a_q); + assign r3_byp_sel[5] = w0e & (w0a == r3a_q); + assign r3_byp_sel[6] = w1e & (w1a == r3a_q); + assign r3_byp_sel[7] = w2e & (w2a == r3a_q); + assign r3_byp_sel[8] = w3e & (w3a == r3a_q); + assign r3_byp_sel[9] = w4e & (w4a == r3a_q); + assign r3_byp_sel[10] = (~|(r3_byp_sel[0:9])); + + assign r3d_d = (w0d_q & {WIDTH{r3_byp_sel[0]}}) | + (w1d_q & {WIDTH{r3_byp_sel[1]}}) | + (w2d_q & {WIDTH{r3_byp_sel[2]}}) | + (w3d_q & {WIDTH{r3_byp_sel[3]}}) | + (w4d_q & {WIDTH{r3_byp_sel[4]}}) | + (w0d & {WIDTH{r3_byp_sel[5]}}) | + (w1d & {WIDTH{r3_byp_sel[6]}}) | + (w2d & {WIDTH{r3_byp_sel[7]}}) | + (w3d & {WIDTH{r3_byp_sel[8]}}) | + (w4d & {WIDTH{r3_byp_sel[9]}}) | + (r3d_array & {WIDTH{r3_byp_sel[10]}}); + + assign r4_byp_sel[0] = w0e_q & (w0a_q == r4a_q); + assign r4_byp_sel[1] = w1e_q & (w1a_q == r4a_q); + assign r4_byp_sel[2] = w2e_q & (w2a_q == r4a_q); + assign r4_byp_sel[3] = w3e_q & (w3a_q == r4a_q); + assign r4_byp_sel[4] = w4e_q & (w4a_q == r4a_q); + assign r4_byp_sel[5] = w0e & (w0a == r4a_q); + assign r4_byp_sel[6] = w1e & (w1a == r4a_q); + assign r4_byp_sel[7] = w2e & (w2a == r4a_q); + assign r4_byp_sel[8] = w3e & (w3a == r4a_q); + assign r4_byp_sel[9] = w4e & (w4a == r4a_q); + assign r4_byp_sel[10] = (~|(r4_byp_sel[0:9])); + + assign r4d_d = (w0d_q & {WIDTH{r4_byp_sel[0]}}) | + (w1d_q & {WIDTH{r4_byp_sel[1]}}) | + (w2d_q & {WIDTH{r4_byp_sel[2]}}) | + (w3d_q & {WIDTH{r4_byp_sel[3]}}) | + (w4d_q & {WIDTH{r4_byp_sel[4]}}) | + (w0d & {WIDTH{r4_byp_sel[5]}}) | + (w1d & {WIDTH{r4_byp_sel[6]}}) | + (w2d & {WIDTH{r4_byp_sel[7]}}) | + (w3d & {WIDTH{r4_byp_sel[8]}}) | + (w4d & {WIDTH{r4_byp_sel[9]}}) | + (r4d_array & {WIDTH{r4_byp_sel[10]}}); + + end +endgenerate + +generate + if (BYPASS == 0) + begin : read_nobypass + assign r0d_d = r0d_array; + assign r1d_d = r1d_array; + assign r2d_d = r2d_array; + assign r3d_d = r3d_array; + assign r4d_d = r4d_array; + end +endgenerate + +assign r0d = r0d_q; +assign r1d = r1d_q; +assign r2d = r2d_q; +assign r3d = r3d_q; +assign r4d = r4d_q; + +generate + genvar r; + for (r=0;r<=POOL-1;r=r+1) + begin : entry + tri_regk #(.WIDTH(WIDTH), .INIT(0), .NEEDS_SRESET(1)) reg_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(reg_act[r]), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[reg_offset+r*WIDTH:reg_offset+(r+1)*WIDTH-1]), + .scout(sov[reg_offset+r*WIDTH:reg_offset+(r+1)*WIDTH-1]), + .din(reg_d[r]), + .dout(reg_q[r]) + ); + end +endgenerate + + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) r0e_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[r0e_offset]), + .scout(sov[r0e_offset]), + .din(r0e), + .dout(r0e_q) + ); + + tri_rlmreg_p #(.WIDTH(POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) r0a_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(r0e_e), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[r0a_offset:r0a_offset + POOL_ENC - 1]), + .scout(sov[r0a_offset:r0a_offset + POOL_ENC - 1]), + .din(r0a), + .dout(r0a_q) + ); + + tri_rlmreg_p #(.WIDTH(WIDTH), .INIT(0), .NEEDS_SRESET(1)) r0d_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(r0e_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[r0d_offset:r0d_offset + WIDTH - 1]), + .scout(sov[r0d_offset:r0d_offset + WIDTH - 1]), + .din(r0d_d), + .dout(r0d_q) + ); + + generate + if (RD_PORTS > 1) + begin : r1_gen1 + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) r1e_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[r1e_offset]), + .scout(sov[r1e_offset]), + .din(r1e), + .dout(r1e_q) + ); + + tri_rlmreg_p #(.WIDTH(POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) r1a_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(r1e_e), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[r1a_offset:r1a_offset + POOL_ENC - 1]), + .scout(sov[r1a_offset:r1a_offset + POOL_ENC - 1]), + .din(r1a), + .dout(r1a_q) + ); + + tri_rlmreg_p #(.WIDTH(WIDTH), .INIT(0), .NEEDS_SRESET(1)) r1d_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(r1e_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[r1d_offset:r1d_offset + WIDTH - 1]), + .scout(sov[r1d_offset:r1d_offset + WIDTH - 1]), + .din(r1d_d), + .dout(r1d_q) + ); + end + endgenerate + generate + if (RD_PORTS > 2) + begin : r2_gen1 + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) r2e_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[r2e_offset]), + .scout(sov[r2e_offset]), + .din(r2e), + .dout(r2e_q) + ); + + tri_rlmreg_p #(.WIDTH(POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) r2a_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(r2e_e), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[r2a_offset:r2a_offset + POOL_ENC - 1]), + .scout(sov[r2a_offset:r2a_offset + POOL_ENC - 1]), + .din(r2a), + .dout(r2a_q) + ); + + tri_rlmreg_p #(.WIDTH(WIDTH), .INIT(0), .NEEDS_SRESET(1)) r2d_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(r2e_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[r2d_offset:r2d_offset + WIDTH - 1]), + .scout(sov[r2d_offset:r2d_offset + WIDTH - 1]), + .din(r2d_d), + .dout(r2d_q) + ); + end + endgenerate + generate + if (RD_PORTS > 3) + begin : r3_gen1 + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) r3e_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[r3e_offset]), + .scout(sov[r3e_offset]), + .din(r3e), + .dout(r3e_q) + ); + + tri_rlmreg_p #(.WIDTH(POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) r3a_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(r3e_e), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[r3a_offset:r3a_offset + POOL_ENC - 1]), + .scout(sov[r3a_offset:r3a_offset + POOL_ENC - 1]), + .din(r3a), + .dout(r3a_q) + ); + + tri_rlmreg_p #(.WIDTH(WIDTH), .INIT(0), .NEEDS_SRESET(1)) r3d_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(r3e_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[r3d_offset:r3d_offset + WIDTH - 1]), + .scout(sov[r3d_offset:r3d_offset + WIDTH - 1]), + .din(r3d_d), + .dout(r3d_q) + ); + end + endgenerate + generate + if (RD_PORTS > 4) + begin : r4_gen1 + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) r4e_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[r4e_offset]), + .scout(sov[r4e_offset]), + .din(r4e), + .dout(r4e_q) + ); + + tri_rlmreg_p #(.WIDTH(POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) r4a_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(r4e_e), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[r4a_offset:r4a_offset + POOL_ENC - 1]), + .scout(sov[r4a_offset:r4a_offset + POOL_ENC - 1]), + .din(r4a), + .dout(r4a_q) + ); + + tri_rlmreg_p #(.WIDTH(WIDTH), .INIT(0), .NEEDS_SRESET(1)) r4d_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(r4e_q), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[r4d_offset:r4d_offset + WIDTH - 1]), + .scout(sov[r4d_offset:r4d_offset + WIDTH - 1]), + .din(r4d_d), + .dout(r4d_q) + ); + end + endgenerate + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) w0e_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[w0e_offset]), + .scout(sov[w0e_offset]), + .din(w0e), + .dout(w0e_q) + ); + + tri_rlmreg_p #(.WIDTH(POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) w0a_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(w0e_e), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[w0a_offset:w0a_offset + POOL_ENC - 1]), + .scout(sov[w0a_offset:w0a_offset + POOL_ENC - 1]), + .din(w0a), + .dout(w0a_q) + ); + + tri_rlmreg_p #(.WIDTH(WIDTH), .INIT(0), .NEEDS_SRESET(1)) w0d_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(w0e_e), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[w0d_offset:w0d_offset + WIDTH - 1]), + .scout(sov[w0d_offset:w0d_offset + WIDTH - 1]), + .din(w0d), + .dout(w0d_q) + ); + generate + if (WR_PORTS > 1) + begin : w1_gen1 + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) w1e_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[w1e_offset]), + .scout(sov[w1e_offset]), + .din(w1e), + .dout(w1e_q) + ); + + tri_rlmreg_p #(.WIDTH(POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) w1a_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(w1e_e), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[w1a_offset:w1a_offset + POOL_ENC - 1]), + .scout(sov[w1a_offset:w1a_offset + POOL_ENC - 1]), + .din(w1a), + .dout(w1a_q) + ); + + tri_rlmreg_p #(.WIDTH(WIDTH), .INIT(0), .NEEDS_SRESET(1)) w1d_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(w1e_e), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[w1d_offset:w1d_offset + WIDTH - 1]), + .scout(sov[w1d_offset:w1d_offset + WIDTH - 1]), + .din(w1d), + .dout(w1d_q) + ); + end + endgenerate + generate + if (WR_PORTS > 2) + begin : w2_gen1 + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) w2e_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[w2e_offset]), + .scout(sov[w2e_offset]), + .din(w2e), + .dout(w2e_q) + ); + + tri_rlmreg_p #(.WIDTH(POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) w2a_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(w2e_e), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[w2a_offset:w2a_offset + POOL_ENC - 1]), + .scout(sov[w2a_offset:w2a_offset + POOL_ENC - 1]), + .din(w2a), + .dout(w2a_q) + ); + + tri_rlmreg_p #(.WIDTH(WIDTH), .INIT(0), .NEEDS_SRESET(1)) w2d_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(w2e_e), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[w2d_offset:w2d_offset + WIDTH - 1]), + .scout(sov[w2d_offset:w2d_offset + WIDTH - 1]), + .din(w2d), + .dout(w2d_q) + ); + end + endgenerate + generate + if (WR_PORTS > 3) + begin : w3_gen1 + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) w3e_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[w3e_offset]), + .scout(sov[w3e_offset]), + .din(w3e), + .dout(w3e_q) + ); + + tri_rlmreg_p #(.WIDTH(POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) w3a_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(w3e_e), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[w3a_offset:w3a_offset + POOL_ENC - 1]), + .scout(sov[w3a_offset:w3a_offset + POOL_ENC - 1]), + .din(w3a), + .dout(w3a_q) + ); + + tri_rlmreg_p #(.WIDTH(WIDTH), .INIT(0), .NEEDS_SRESET(1)) w3d_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(w3e_e), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[w3d_offset:w3d_offset + WIDTH - 1]), + .scout(sov[w3d_offset:w3d_offset + WIDTH - 1]), + .din(w3d), + .dout(w3d_q) + ); + end + endgenerate + generate + if (WR_PORTS > 4) + begin : w4_gen1 + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) w4e_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[w4e_offset]), + .scout(sov[w4e_offset]), + .din(w4e), + .dout(w4e_q) + ); + + tri_rlmreg_p #(.WIDTH(POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) w4a_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(w4e_e), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[w4a_offset:w4a_offset + POOL_ENC - 1]), + .scout(sov[w4a_offset:w4a_offset + POOL_ENC - 1]), + .din(w4a), + .dout(w4a_q) + ); + + tri_rlmreg_p #(.WIDTH(WIDTH), .INIT(0), .NEEDS_SRESET(1)) w4d_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(w4e_e), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[w4d_offset:w4d_offset + WIDTH - 1]), + .scout(sov[w4d_offset:w4d_offset + WIDTH - 1]), + .din(w4d), + .dout(w4d_q) + ); + end + endgenerate + + generate + if (RD_PORTS <= 1) + begin : r1_gen0 + assign r1e_q = 0; + assign r1a_q = 0; + assign r1d_q = 0; + assign unused[0] = (|r1d_d) | (|r1e) | (|r1a) | (|r1e_e) | (|r1e_q); + end + endgenerate + generate + if (RD_PORTS <= 2) + begin : r2_gen0 + assign r2e_q = 0; + assign r2a_q = 0; + assign r2d_q = 0; + assign unused[1] = (|r2d_d) | (|r2e) | (|r2a) | (|r2e_e) | (|r2e_q); + end + endgenerate + generate + if (RD_PORTS <= 3) + begin : r3_gen0 + assign r3e_q = 0; + assign r3a_q = 0; + assign r3d_q = 0; + assign unused[2] = (|r3d_d) | (|r3e) | (|r3a) | (|r3e_e) | (|r3e_q); + end + endgenerate + generate + if (RD_PORTS <= 4) + begin : r4_gen0 + assign r4e_q = 0; + assign r4a_q = 0; + assign r4d_q = 0; + assign unused[3] = (|r4d_d) | (|r4e) | (|r4a) | (|r4e_e) | (|r4e_q); + end + endgenerate + + generate + if (WR_PORTS <= 1) + begin : w1_gen0 + assign w1e_q = 0; + assign w1a_q = 0; + assign w1d_q = 0; + assign unused[4] = |w1e_e; + end + endgenerate + generate + if (WR_PORTS <= 2) + begin : w2_gen0 + assign w2e_q = 0; + assign w2a_q = 0; + assign w2d_q = 0; + assign unused[5] = |w2e_e; + end + endgenerate + generate + if (WR_PORTS <= 3) + begin : w3_gen0 + assign w3e_q = 0; + assign w3a_q = 0; + assign w3d_q = 0; + assign unused[6] = |w3e_e; + end + endgenerate + generate + if (WR_PORTS <= 4) + begin : w4_gen0 + assign w4e_q = 0; + assign w4a_q = 0; + assign w4d_q = 0; + assign unused[7] = |w4e_e; + end + endgenerate + +assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in}; +assign scan_out = sov[0]; + +endmodule diff --git a/dev/verilog/work/xu_spr.v b/dev/verilog/work/xu_spr.v new file mode 100755 index 0000000..c194315 --- /dev/null +++ b/dev/verilog/work/xu_spr.v @@ -0,0 +1,1850 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: XU SPR - Wrapper +// +//***************************************************************************** +`include "tri_a2o.vh" +module xu_spr +#( + parameter hvmode = 1, + parameter a2mode = 1 +)( + input [0:`NCLK_WIDTH-1] nclk, + + // CHIP IO + input [54:61] an_ac_coreid, + input [32:35] an_ac_chipid_dc, + input [8:15] spr_pvr_version_dc, + input [12:15] spr_pvr_revision_dc, + input [16:19] spr_pvr_revision_minor_dc, + input [0:`THREADS-1] an_ac_ext_interrupt, + input [0:`THREADS-1] an_ac_crit_interrupt, + input [0:`THREADS-1] an_ac_perf_interrupt, + input [0:`THREADS-1] an_ac_reservation_vld, + input an_ac_tb_update_pulse, + input an_ac_tb_update_enable, + input [0:`THREADS-1] an_ac_sleep_en, + input [0:`THREADS-1] an_ac_hang_pulse, + output [0:`THREADS-1] ac_tc_machine_check, + input [0:`THREADS-1] an_ac_external_mchk, + input pc_xu_instr_trace_mode, + input [0:1] pc_xu_instr_trace_tid, + + input an_ac_scan_dis_dc_b, + input an_ac_scan_diag_dc, + input pc_xu_ccflush_dc, + input clkoff_dc_b, + input d_mode_dc, + input delay_lclkr_dc, + input mpw1_dc_b, + input mpw2_dc_b, + input func_sl_thold_2, + input func_slp_sl_thold_2, + input func_nsl_thold_2, + input func_slp_nsl_thold_2, + input cfg_sl_thold_2, + input cfg_slp_sl_thold_2, + input ary_nsl_thold_2, + input time_sl_thold_2, + input abst_sl_thold_2, + input repr_sl_thold_2, + input gptr_sl_thold_2, + input bolt_sl_thold_2, + input sg_2, + input fce_2, + input [0:`THREADS+1] func_scan_in, + output [0:`THREADS+1] func_scan_out, + input bcfg_scan_in, + output bcfg_scan_out, + input ccfg_scan_in, + output ccfg_scan_out, + input dcfg_scan_in, + output dcfg_scan_out, + input time_scan_in, + output time_scan_out, + input abst_scan_in, + output abst_scan_out, + input repr_scan_in, + output repr_scan_out, + input gptr_scan_in, + output gptr_scan_out, + + // Decode + input [0:`THREADS-1] rv_xu_vld, + input rv_xu_ex0_ord, + input [0:31] rv_xu_ex0_instr, + input [62-`EFF_IFAR_WIDTH:61] rv_xu_ex0_ifar, + + output spr_xu_ord_read_done, + output spr_xu_ord_write_done, + input xu_spr_ord_ready, + input xu_spr_ord_flush, + input [0:`THREADS-1] cp_flush, + + // Read Data + output [64-`GPR_WIDTH:63] spr_xu_ex4_rd_data, + + // Write Data + input [64-`GPR_WIDTH:63] xu_spr_ex2_rs1, + + // Interrupt Interface + input [0:`THREADS-1] iu_xu_rfi, + input [0:`THREADS-1] iu_xu_rfgi, + input [0:`THREADS-1] iu_xu_rfci, + input [0:`THREADS-1] iu_xu_rfmci, + input [0:`THREADS-1] iu_xu_act, + input [0:`THREADS-1] iu_xu_int, + input [0:`THREADS-1] iu_xu_gint, + input [0:`THREADS-1] iu_xu_cint, + input [0:`THREADS-1] iu_xu_mcint, + input [0:`THREADS-1] iu_xu_dear_update, + input [0:`THREADS-1] iu_xu_dbsr_update, + input [0:`THREADS-1] iu_xu_esr_update, + input [0:`THREADS-1] iu_xu_force_gsrr, + input [0:`THREADS-1] iu_xu_dbsr_ude, + input [0:`THREADS-1] iu_xu_dbsr_ide, + output [0:`THREADS-1] xu_iu_dbsr_ide, + + input [62-`EFF_IFAR_ARCH:61] iu_xu_nia_t0, + input [0:16] iu_xu_esr_t0, + input [0:14] iu_xu_mcsr_t0, + input [0:18] iu_xu_dbsr_t0, + input [64-`GPR_WIDTH:63] iu_xu_dear_t0, + output [62-`EFF_IFAR_ARCH:61] xu_iu_rest_ifar_t0, + + `ifndef THREADS1 + input [62-`EFF_IFAR_ARCH:61] iu_xu_nia_t1, + input [0:16] iu_xu_esr_t1, + input [0:14] iu_xu_mcsr_t1, + input [0:18] iu_xu_dbsr_t1, + input [64-`GPR_WIDTH:63] iu_xu_dear_t1, + output [62-`EFF_IFAR_ARCH:61] xu_iu_rest_ifar_t1, + `endif + + // Async Interrupt Req Interface + output [0:`THREADS-1] xu_iu_external_mchk, + output [0:`THREADS-1] xu_iu_ext_interrupt, + output [0:`THREADS-1] xu_iu_dec_interrupt, + output [0:`THREADS-1] xu_iu_udec_interrupt, + output [0:`THREADS-1] xu_iu_perf_interrupt, + output [0:`THREADS-1] xu_iu_fit_interrupt, + output [0:`THREADS-1] xu_iu_crit_interrupt, + output [0:`THREADS-1] xu_iu_wdog_interrupt, + output [0:`THREADS-1] xu_iu_gwdog_interrupt, + output [0:`THREADS-1] xu_iu_gfit_interrupt, + output [0:`THREADS-1] xu_iu_gdec_interrupt, + output [0:`THREADS-1] xu_iu_dbell_interrupt, + output [0:`THREADS-1] xu_iu_cdbell_interrupt, + output [0:`THREADS-1] xu_iu_gdbell_interrupt, + output [0:`THREADS-1] xu_iu_gcdbell_interrupt, + output [0:`THREADS-1] xu_iu_gmcdbell_interrupt, + input [0:`THREADS-1] iu_xu_dbell_taken, + input [0:`THREADS-1] iu_xu_cdbell_taken, + input [0:`THREADS-1] iu_xu_gdbell_taken, + input [0:`THREADS-1] iu_xu_gcdbell_taken, + input [0:`THREADS-1] iu_xu_gmcdbell_taken, + + // DBELL Int + input lq_xu_dbell_val, + input [0:4] lq_xu_dbell_type, + input lq_xu_dbell_brdcast, + input lq_xu_dbell_lpid_match, + input [50:63] lq_xu_dbell_pirtag, + + // Slow SPR Bus + output xu_slowspr_val_out, + output xu_slowspr_rw_out, + output [0:1] xu_slowspr_etid_out, + output [11:20] xu_slowspr_addr_out, + output [64-`GPR_WIDTH:63] xu_slowspr_data_out, + + // DCR Bus + output ac_an_dcr_act, + output ac_an_dcr_val, + output ac_an_dcr_read, + output ac_an_dcr_user, + output [0:1] ac_an_dcr_etid, + output [11:20] ac_an_dcr_addr, + output [64-`GPR_WIDTH:63] ac_an_dcr_data, + + // Trap + output [0:`THREADS-1] xu_iu_fp_precise, + output spr_dec_ex4_spr_hypv, + output spr_dec_ex4_spr_illeg, + output spr_dec_ex4_spr_priv, + output spr_dec_ex4_np1_flush, + + // Run State + input pc_xu_pm_hold_thread, + input [0:`THREADS-1] iu_xu_stop, + output [0:`THREADS-1] xu_pc_running, + output [0:`THREADS-1] xu_iu_run_thread, + output [0:`THREADS-1] xu_iu_single_instr_mode, + output [0:`THREADS-1] xu_iu_raise_iss_pri, + output [0:`THREADS-1] xu_pc_spr_ccr0_we, + output [0:1] xu_pc_spr_ccr0_pme, + output [0:`THREADS-1] xu_pc_stop_dnh_instr, + + // Quiesce + input [0:`THREADS-1] iu_xu_quiesce, + input [0:`THREADS-1] iu_xu_icache_quiesce, + input [0:`THREADS-1] lq_xu_quiesce, + input [0:`THREADS-1] mm_xu_quiesce, + input [0:`THREADS-1] bx_xu_quiesce, + + // PCCR0 + input pc_xu_extirpts_dis_on_stop, + input pc_xu_timebase_dis_on_stop, + input pc_xu_decrem_dis_on_stop, + + // PERF + input [0:2] pc_xu_event_count_mode, + input pc_xu_event_bus_enable, + input [0:4*`THREADS-1] xu_event_bus_in, + output [0:4*`THREADS-1] xu_event_bus_out, + input [0:`THREADS-1] div_spr_running, + input [0:`THREADS-1] mul_spr_running, + + // MSR Override + input [0:`THREADS-1] pc_xu_ram_active, + input pc_xu_msrovride_enab, + input pc_xu_msrovride_pr, + input pc_xu_msrovride_gs, + input pc_xu_msrovride_de, + + // SIAR + input [0:`THREADS-1] pc_xu_spr_cesr1_pmae, + output [0:`THREADS-1] xu_pc_perfmon_alert, + + + // LiveLock + input [0:`THREADS-1] iu_xu_instr_cpl, + output [0:`THREADS-1] xu_pc_err_llbust_attempt, + output [0:`THREADS-1] xu_pc_err_llbust_failed, + + // Resets + input pc_xu_reset_wd_complete, + input pc_xu_reset_1_complete, + input pc_xu_reset_2_complete, + input pc_xu_reset_3_complete, + output ac_tc_reset_1_request, + output ac_tc_reset_2_request, + output ac_tc_reset_3_request, + output ac_tc_reset_wd_request, + + // Err Inject + input [0:`THREADS-1] pc_xu_inj_llbust_attempt, + input [0:`THREADS-1] pc_xu_inj_llbust_failed, + input [0:`THREADS-1] pc_xu_inj_wdt_reset, + output [0:`THREADS-1] xu_pc_err_wdt_reset, + + // Parity + input [0:`THREADS-1] pc_xu_inj_sprg_ecc, + output [0:`THREADS-1] xu_pc_err_sprg_ecc, + output [0:`THREADS-1] xu_pc_err_sprg_ue, + + // SPRs + output [0:`THREADS-1] xu_iu_msrovride_enab, + + input [0:`THREADS-1] spr_dbcr0_edm, + output [0:3] spr_xucr0_clkg_ctl, + output [0:`THREADS-1] xu_iu_iac1_en, + output [0:`THREADS-1] xu_iu_iac2_en, + output [0:`THREADS-1] xu_iu_iac3_en, + output [0:`THREADS-1] xu_iu_iac4_en, + input lq_xu_spr_xucr0_cslc_xuop, + input lq_xu_spr_xucr0_cslc_binv, + input lq_xu_spr_xucr0_clo, + input lq_xu_spr_xucr0_cul, + output [0:`THREADS-1] spr_epcr_extgs, + output [0:`THREADS-1] spr_epcr_icm, + output [0:`THREADS-1] spr_epcr_gicm, + output [0:`THREADS-1] spr_msr_de, + output [0:`THREADS-1] spr_msr_pr, + output [0:`THREADS-1] spr_msr_is, + output [0:`THREADS-1] spr_msr_cm, + output [0:`THREADS-1] spr_msr_gs, + output [0:`THREADS-1] spr_msr_ee, + output [0:`THREADS-1] spr_msr_ce, + output [0:`THREADS-1] spr_msr_me, + output [0:`THREADS-1] spr_msr_fe0, + output [0:`THREADS-1] spr_msr_fe1, + output spr_ccr2_en_pc, + output spr_ccr4_en_dnh, + output xu_lsu_spr_xucr0_clfc, + `ifndef THREADS1 + output [64-`GPR_WIDTH:63] spr_dvc1_t1, + output [64-`GPR_WIDTH:63] spr_dvc2_t1, + `endif + output [64-`GPR_WIDTH:63] spr_dvc1_t0, + output [64-`GPR_WIDTH:63] spr_dvc2_t0, + output [0:31] spr_xesr1, + output [0:31] spr_xesr2, + output [0:`THREADS-1] perf_event_en, + + output spr_ccr2_en_dcr, + output spr_ccr2_en_trace, + output [0:8] spr_ccr2_ifratsc, + output spr_ccr2_ifrat, + output [0:8] spr_ccr2_dfratsc, + output spr_ccr2_dfrat, + output spr_ccr2_ucode_dis, + output [0:3] spr_ccr2_ap, + output spr_ccr2_en_attn, + output spr_ccr2_en_ditc, + output spr_ccr2_en_icswx, + output spr_ccr2_notlb, + output [0:3] spr_xucr0_trace_um, + output xu_lsu_spr_xucr0_mbar_ack, + output xu_lsu_spr_xucr0_tlbsync, + output spr_xucr0_cls, + output xu_lsu_spr_xucr0_aflsta, + output spr_xucr0_mddp, + output xu_lsu_spr_xucr0_cred, + output xu_lsu_spr_xucr0_rel, + output spr_xucr0_mdcp, + output xu_lsu_spr_xucr0_flsta, + output xu_lsu_spr_xucr0_l2siw, + output xu_lsu_spr_xucr0_flh2l2, + output xu_lsu_spr_xucr0_dcdis, + output xu_lsu_spr_xucr0_wlk, + output spr_xucr4_mmu_mchk, + output spr_xucr4_mddmh, + output [0:`THREADS-1] spr_dbcr0_idm, + output [0:`THREADS-1] spr_dbcr0_icmp, + output [0:`THREADS-1] spr_dbcr0_brt, + output [0:`THREADS-1] spr_dbcr0_irpt, + output [0:`THREADS-1] spr_dbcr0_trap, + output [0:2*`THREADS-1] spr_dbcr0_dac1, + output [0:2*`THREADS-1] spr_dbcr0_dac2, + output [0:`THREADS-1] spr_dbcr0_ret, + output [0:2*`THREADS-1] spr_dbcr0_dac3, + output [0:2*`THREADS-1] spr_dbcr0_dac4, + output [0:`THREADS-1] spr_dbcr1_iac12m, + output [0:`THREADS-1] spr_dbcr1_iac34m, + output [0:`THREADS-1] spr_epcr_dtlbgs, + output [0:`THREADS-1] spr_epcr_itlbgs, + output [0:`THREADS-1] spr_epcr_dsigs, + output [0:`THREADS-1] spr_epcr_isigs, + output [0:`THREADS-1] spr_epcr_duvd, + output [0:`THREADS-1] spr_epcr_dgtmi, + output [0:`THREADS-1] xu_mm_spr_epcr_dmiuh, + output [0:`THREADS-1] spr_msr_ucle, + output [0:`THREADS-1] spr_msr_spv, + output [0:`THREADS-1] spr_msr_fp, + output [0:`THREADS-1] spr_msr_ds, + output [0:`THREADS-1] spr_msrp_uclep, + + // BOLT-ON + input bo_enable_2, + input pc_xu_bo_reset, + input pc_xu_bo_unload, + input pc_xu_bo_repair, + input pc_xu_bo_shdata, + input pc_xu_bo_select, + output xu_pc_bo_fail, + output xu_pc_bo_diagout, + // ABIST + input an_ac_lbist_ary_wrt_thru_dc, + input pc_xu_abist_ena_dc, + input pc_xu_abist_g8t_wenb, + input [4:9] pc_xu_abist_waddr_0, + input [0:3] pc_xu_abist_di_0, + input pc_xu_abist_g8t1p_renb_0, + input [4:9] pc_xu_abist_raddr_0, + input pc_xu_abist_wl32_comp_ena, + input pc_xu_abist_raw_dc_b, + input [0:3] pc_xu_abist_g8t_dcomp, + input pc_xu_abist_g8t_bw_1, + input pc_xu_abist_g8t_bw_0, + + // Debug + input pc_xu_trace_bus_enable, + input [0:10] spr_debug_mux_ctrls, + input [0:31] spr_debug_data_in, + output [0:31] spr_debug_data_out, + + // Power + inout vcs, + inout vdd, + inout gnd +); + + wire reset_1_request_q, reset_1_request_d ; + wire reset_2_request_q, reset_2_request_d ; + wire reset_3_request_q, reset_3_request_d ; + wire reset_wd_request_q, reset_wd_request_d ; + wire [62-`EFF_IFAR_ARCH:61] int_rest_ifar_q[0:`THREADS-1],int_rest_ifar_d [0:`THREADS-1]; // input=>int_rest_ifar_d , act=>int_rest_act + wire trace_bus_enable_q ; // input=>pc_xu_trace_bus_enable , act=>1'b1 , scan=>Y, sleep=>Y, needs_sreset=>1 + wire [0:10] debug_mux_ctrls_q ; // input=>spr_debug_mux_ctrls , act=>trace_bus_enable_q , scan=>Y, sleep=>Y, needs_sreset=>1 + wire [0:31] debug_data_out_q, debug_data_out_d ; // input=>debug_data_out_d , act=>trace_bus_enable_q , scan=>Y, sleep=>Y, needs_sreset=>1 + + // Scanchains + localparam reset_1_request_offset = 0; + localparam reset_2_request_offset = reset_1_request_offset + 1; + localparam reset_3_request_offset = reset_2_request_offset + 1; + localparam reset_wd_request_offset = reset_3_request_offset + 1; + localparam int_rest_ifar_offset = reset_wd_request_offset + 1; + localparam trace_bus_enable_offset = int_rest_ifar_offset + `THREADS*`EFF_IFAR_ARCH; + localparam debug_mux_ctrls_offset = trace_bus_enable_offset + 1; + localparam debug_data_out_offset = debug_mux_ctrls_offset + 11; + localparam xu_spr_cspr_offset = debug_data_out_offset + 32; + localparam scan_right = xu_spr_cspr_offset + 1; + wire [0:scan_right-1] siv; + wire [0:scan_right-1] sov; + // ABST Latches + wire abist_g8t_wenb_q ; // input=>pc_xu_abist_g8t_wenb , act=>pc_xu_abist_ena_dc + wire [4:9] abist_waddr_0_q ; // input=>pc_xu_abist_waddr_0 , act=>pc_xu_abist_ena_dc + wire [0:3] abist_di_0_q ; // input=>pc_xu_abist_di_0 , act=>pc_xu_abist_ena_dc + wire abist_g8t1p_renb_0_q ; // input=>pc_xu_abist_g8t1p_renb_0,act=>pc_xu_abist_ena_dc + wire [4:9] abist_raddr_0_q ; // input=>pc_xu_abist_raddr_0 , act=>pc_xu_abist_ena_dc + wire abist_wl32_comp_ena_q ; // input=>pc_xu_abist_wl32_comp_ena, act=>pc_xu_abist_ena_dc + wire [0:3] abist_g8t_dcomp_q ; // input=>pc_xu_abist_g8t_dcomp , act=>pc_xu_abist_ena_dc + wire abist_g8t_bw_1_q ; // input=>pc_xu_abist_g8t_bw_1 , act=>pc_xu_abist_ena_dc + wire abist_g8t_bw_0_q ; // input=>pc_xu_abist_g8t_bw_0 , act=>pc_xu_abist_ena_dc + // Scanchains + localparam xu_spr_aspr_offset_abst = 1; + localparam abist_g8t_wenb_offset_abst = xu_spr_aspr_offset_abst + 1; + localparam abist_waddr_0_offset_abst = abist_g8t_wenb_offset_abst + 1; + localparam abist_di_0_offset_abst = abist_waddr_0_offset_abst + 6; + localparam abist_g8t1p_renb_0_offset_abst = abist_di_0_offset_abst + 4; + localparam abist_raddr_0_offset_abst = abist_g8t1p_renb_0_offset_abst + 1; + localparam abist_wl32_comp_ena_offset_abst = abist_raddr_0_offset_abst + 6; + localparam abist_g8t_dcomp_offset_abst = abist_wl32_comp_ena_offset_abst + 1; + localparam abist_g8t_bw_1_offset_abst = abist_g8t_dcomp_offset_abst + 4; + localparam abist_g8t_bw_0_offset_abst = abist_g8t_bw_1_offset_abst + 1; + localparam scan_right_abst = abist_g8t_bw_0_offset_abst + 2; + // Scanchain Repower + wire [0:scan_right_abst-1] siv_abst; + wire [0:scan_right_abst-1] sov_abst; + wire [0:2] siv_bcfg; + wire [0:2] sov_bcfg; + wire [0:`THREADS+2] siv_ccfg; + wire [0:`THREADS+2] sov_ccfg; + wire [0:`THREADS+2] siv_dcfg; + wire [0:`THREADS+2] sov_dcfg; + wire [0:2] siv_time; + wire [0:2] sov_time; + wire [0:2] siv_gptr; + wire [0:2] sov_gptr; + wire [0:2] siv_repr; + wire [0:2] sov_repr; + wire [0:`THREADS+1] func_scan_rpwr_in; + wire [0:`THREADS+1] func_scan_rpwr_out; + wire [0:`THREADS+1] func_scan_gate_out; + // Signals + wire g8t_clkoff_dc_b; + wire g8t_d_mode_dc; + wire [0:4] g8t_mpw1_dc_b; + wire g8t_mpw2_dc_b; + wire [0:4] g8t_delay_lclkr_dc; + wire func_slp_nsl_thold_1; + wire func_nsl_thold_1; + wire func_slp_sl_thold_1; + wire func_sl_thold_1; + wire time_sl_thold_1; + wire abst_sl_thold_1; + wire repr_sl_thold_1; + wire gptr_sl_thold_1; + wire bolt_sl_thold_1; + wire ary_nsl_thold_1; + wire cfg_sl_thold_1; + wire cfg_slp_sl_thold_1; + wire fce_1; + wire sg_1; + wire func_slp_nsl_thold_0; + wire [0:`THREADS] func_nsl_thold_0; + wire [0:`THREADS] func_slp_sl_thold_0; + wire [0:`THREADS] func_sl_thold_0; + wire [0:`THREADS] cfg_sl_thold_0; + wire cfg_slp_sl_thold_0; + wire [0:`THREADS] fce_0; + wire [0:`THREADS] sg_0; + wire cfg_slp_sl_force; + wire cfg_slp_sl_thold_0_b; + wire bcfg_slp_sl_force; + wire bcfg_slp_sl_thold_0_b; + wire ccfg_slp_sl_force; + wire ccfg_slp_sl_thold_0_b; + wire [0:`THREADS] cfg_sl_force; + wire [0:`THREADS] cfg_sl_thold_0_b; + wire [0:0] bcfg_sl_force; + wire [0:0] bcfg_sl_thold_0_b; + wire [0:`THREADS] ccfg_sl_force; + wire [0:`THREADS] ccfg_sl_thold_0_b; + wire [0:`THREADS] dcfg_sl_force; + wire [0:`THREADS] dcfg_sl_thold_0_b; + wire [0:`THREADS] func_sl_force; + wire [0:`THREADS] func_sl_thold_0_b; + wire [0:`THREADS] func_slp_sl_force; + wire [0:`THREADS] func_slp_sl_thold_0_b; + wire [0:`THREADS] func_nsl_force; + wire [0:`THREADS] func_nsl_thold_0_b; + wire func_slp_nsl_force; + wire func_slp_nsl_thold_0_b; + wire repr_sl_thold_0; + wire gptr_sl_thold_0; + wire bolt_sl_thold_0; + wire time_sl_thold_0; + wire abst_sl_force; + wire abst_sl_thold_0; + wire abst_sl_thold_0_b; + wire ary_nsl_thold_0; + wire so_force; + wire abst_so_thold_0_b; + wire bcfg_so_thold_0_b; + wire ccfg_so_thold_0_b; + wire dcfg_so_thold_0_b; + wire time_so_thold_0_b; + wire repr_so_thold_0_b; + wire gptr_so_thold_0_b; + wire func_so_thold_0_b; + wire [0:31] cspr_tspr_ex1_instr; + wire [0:`THREADS-1] cspr_tspr_ex2_tid; + wire [0:9] cspr_tspr_timebase_taps; + wire [0:`GPR_WIDTH*`THREADS-1]tspr_cspr_ex3_tspr_rt; + wire [0:`THREADS-1] tspr_cspr_illeg_mtspr_b; + wire [0:`THREADS-1] tspr_cspr_illeg_mfspr_b; + wire [0:`THREADS-1] tspr_cspr_hypv_mtspr; + wire [0:`THREADS-1] tspr_cspr_hypv_mfspr; + wire [0:`THREADS-1] tspr_cspr_freeze_timers; + wire cspr_aspr_ex3_we; + wire [0:5] cspr_aspr_ex3_waddr; + wire cspr_aspr_ex1_re; + wire [0:5] cspr_aspr_ex1_raddr; + wire [64-`GPR_WIDTH:72-(64/`GPR_WIDTH)] aspr_cspr_ex2_rdata; + wire [0:`THREADS-1] cspr_tspr_msrovride_en; + wire [0:`THREADS-1] cspr_tspr_ram_active; + wire [0:`THREADS-1] tspr_epcr_extgs; + wire [0:`THREADS-1] tspr_msr_pr; + wire [0:`THREADS-1] tspr_msr_is; + wire [0:`THREADS-1] tspr_epcr_icm; + wire [0:`THREADS-1] tspr_epcr_gicm; + wire [0:`THREADS-1] tspr_msr_cm; + wire [0:`THREADS-1] tspr_msr_de; + wire [0:`THREADS-1] tspr_msr_gs; + wire [0:`THREADS-1] tspr_msr_ee; + wire [0:`THREADS-1] tspr_msr_ce; + wire [0:`THREADS-1] tspr_msr_me; + wire [0:`THREADS-1] tspr_msr_fe0; + wire [0:`THREADS-1] tspr_msr_fe1; + wire cspr_ccr2_en_pc; + wire [0:`THREADS-1] tspr_fp_precise; + wire [0:`THREADS-1] cspr_tspr_llen; + wire [0:`THREADS-1] cspr_tspr_llpri; + wire [0:`THREADS-1] tspr_cspr_lldet; + wire [0:`THREADS-1] tspr_cspr_llpulse; + wire [0:`THREADS-1] cspr_tspr_dec_dbg_dis; + wire [0:`THREADS-1] reset_1_request; + wire [0:`THREADS-1] reset_2_request; + wire [0:`THREADS-1] reset_3_request; + wire [0:`THREADS-1] reset_wd_request; + wire [0:`THREADS-1] cspr_tspr_crit_mask; + wire [0:`THREADS-1] cspr_tspr_sleep_mask; + wire [0:`THREADS-1] cspr_tspr_ext_mask; + wire [0:`THREADS-1] cspr_tspr_dec_mask; + wire [0:`THREADS-1] cspr_tspr_fit_mask; + wire [0:`THREADS-1] cspr_tspr_wdog_mask; + wire [0:`THREADS-1] cspr_tspr_udec_mask; + wire [0:`THREADS-1] cspr_tspr_perf_mask; + wire [0:`THREADS-1] tspr_cspr_pm_wake_up; + wire [0:3*`THREADS-1] tspr_cspr_async_int; + wire reset_wd_complete; + wire reset_1_complete; + wire reset_2_complete; + wire reset_3_complete; + wire timer_update; + wire [50:63] cspr_tspr_dbell_pirtag; + wire cspr_ccr4_en_dnh; + wire [0:`THREADS-1] tspr_cspr_gpir_match; + wire [64-`GPR_WIDTH:63] ex2_spr_wd; + wire [64-`GPR_WIDTH:64+8-(64/`GPR_WIDTH)] ex3_spr_wd; + wire [0:`THREADS-1] cspr_tspr_ex3_spr_we; + wire cspr_tspr_rf1_act; + wire [0:4] cspr_xucr0_clkg_ctl; + wire [0:`THREADS-1] int_rest_act; + wire [0:`THREADS-1] instr_trace_mode; + wire [0:`THREADS-1] tspr_cspr_ex2_np1_flush; + wire [62-`EFF_IFAR_WIDTH:61] ex2_ifar; + wire [0:`THREADS-1] flush; + wire [0:12*`THREADS-1] tspr_debug; + wire [0:39] cspr_debug0; + wire [0:63] cspr_debug1; + wire [0:31] dbg_group0; + wire [0:31] dbg_group1; + wire [0:31] dbg_group2; + wire [0:31] dbg_group3; + wire [0:11] trg_group0; + wire [0:11] trg_group1; + wire [0:11] trg_group2; + wire [0:11] trg_group3; + + wire [62-`EFF_IFAR_ARCH:61] iu_xu_nia [0:`THREADS-1]; + wire [0:16] iu_xu_esr [0:`THREADS-1]; + wire [0:14] iu_xu_mcsr [0:`THREADS-1]; + wire [0:18] iu_xu_dbsr [0:`THREADS-1]; + wire [64-`GPR_WIDTH:63] iu_xu_dear [0:`THREADS-1]; + wire [64-`GPR_WIDTH:63] spr_dvc1 [0:`THREADS-1]; + wire [64-`GPR_WIDTH:63] spr_dvc2 [0:`THREADS-1]; + wire act_dis = 1'b0; + + //!! Bugspray Include: xu_spr; + //## figtree_source: xu_spr.fig; + + assign iu_xu_nia[0] = iu_xu_nia_t0; + assign iu_xu_esr[0] = iu_xu_esr_t0; + assign iu_xu_mcsr[0] = iu_xu_mcsr_t0; + assign iu_xu_dbsr[0] = iu_xu_dbsr_t0; + assign iu_xu_dear[0] = iu_xu_dear_t0; + assign xu_iu_rest_ifar_t0 = int_rest_ifar_q[0]; + assign spr_dvc1_t0 = spr_dvc1[0]; + assign spr_dvc2_t0 = spr_dvc2[0]; + `ifndef THREADS1 + assign iu_xu_nia[1] = iu_xu_nia_t1; + assign iu_xu_esr[1] = iu_xu_esr_t1; + assign iu_xu_mcsr[1] = iu_xu_mcsr_t1; + assign iu_xu_dbsr[1] = iu_xu_dbsr_t1; + assign iu_xu_dear[1] = iu_xu_dear_t1; + assign xu_iu_rest_ifar_t1 = int_rest_ifar_q[1]; + assign spr_dvc1_t1 = spr_dvc1[1]; + assign spr_dvc2_t1 = spr_dvc2[1]; + `endif + + + assign spr_epcr_extgs = tspr_epcr_extgs; + assign spr_epcr_icm = tspr_epcr_icm; + assign spr_epcr_gicm = tspr_epcr_gicm; + assign spr_msr_de = tspr_msr_de; + assign spr_msr_pr = tspr_msr_pr; + assign spr_msr_is = tspr_msr_is; + assign spr_msr_cm = tspr_msr_cm; + assign spr_msr_gs = tspr_msr_gs; + assign spr_msr_ee = tspr_msr_ee; + assign spr_msr_ce = tspr_msr_ce; + assign spr_msr_me = tspr_msr_me; + assign spr_msr_fe0 = tspr_msr_fe0; + assign spr_msr_fe1 = tspr_msr_fe1; + assign xu_iu_fp_precise = tspr_fp_precise; + assign reset_1_request_d = |(reset_1_request); + assign reset_2_request_d = |(reset_2_request); + assign reset_3_request_d = |(reset_3_request); + assign reset_wd_request_d = |(reset_wd_request); + assign ac_tc_reset_1_request = reset_1_request_q; + assign ac_tc_reset_2_request = reset_2_request_q; + assign ac_tc_reset_3_request = reset_3_request_q; + assign ac_tc_reset_wd_request = reset_wd_request_q; + assign spr_xucr0_clkg_ctl = cspr_xucr0_clkg_ctl[0:3]; + assign ex2_spr_wd = xu_spr_ex2_rs1; + assign spr_ccr2_en_pc = cspr_ccr2_en_pc; + assign spr_ccr4_en_dnh = cspr_ccr4_en_dnh; + assign flush = cp_flush | {`THREADS{xu_spr_ord_flush}}; + + + xu_spr_cspr #(.hvmode(hvmode), .a2mode(a2mode)) xu_spr_cspr( + .nclk(nclk), + // CHIP IO + .an_ac_sleep_en(an_ac_sleep_en), + .an_ac_reservation_vld(an_ac_reservation_vld), + .an_ac_tb_update_enable(an_ac_tb_update_enable), + .an_ac_tb_update_pulse(an_ac_tb_update_pulse), + .an_ac_coreid(an_ac_coreid), + .an_ac_chipid_dc(an_ac_chipid_dc), + .pc_xu_instr_trace_mode(pc_xu_instr_trace_mode), + .pc_xu_instr_trace_tid(pc_xu_instr_trace_tid), + .instr_trace_mode(instr_trace_mode), + .spr_pvr_version_dc(spr_pvr_version_dc), + .spr_pvr_revision_dc(spr_pvr_revision_dc), + .spr_pvr_revision_minor_dc(spr_pvr_revision_minor_dc), + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .bcfg_sl_force(bcfg_sl_force[0]), + .bcfg_sl_thold_0_b(bcfg_sl_thold_0_b[0]), + .bcfg_slp_sl_force(bcfg_slp_sl_force), + .bcfg_slp_sl_thold_0_b(bcfg_slp_sl_thold_0_b), + .ccfg_sl_force(ccfg_sl_force[0]), + .ccfg_sl_thold_0_b(ccfg_sl_thold_0_b[0]), + .ccfg_slp_sl_force(ccfg_slp_sl_force), + .ccfg_slp_sl_thold_0_b(ccfg_slp_sl_thold_0_b), + .dcfg_sl_force(dcfg_sl_force[0]), + .dcfg_sl_thold_0_b(dcfg_sl_thold_0_b[0]), + .func_sl_force(func_sl_force[0]), + .func_sl_thold_0_b(func_sl_thold_0_b[0]), + .func_slp_sl_force(func_slp_sl_force[0]), + .func_slp_sl_thold_0_b(func_slp_sl_thold_0_b[0]), + + .func_nsl_force(func_nsl_force[0]), + .func_nsl_thold_0_b(func_nsl_thold_0_b[0]), + + .sg_0(sg_0[0]), + .scan_in({func_scan_rpwr_in[`THREADS],siv[xu_spr_cspr_offset]}), + .scan_out({func_scan_rpwr_out[`THREADS],sov[xu_spr_cspr_offset]}), + .bcfg_scan_in(siv_bcfg[1]), + .bcfg_scan_out(sov_bcfg[1]), + .ccfg_scan_in(siv_ccfg[1]), + .ccfg_scan_out(sov_ccfg[1]), + .dcfg_scan_in(siv_dcfg[1]), + .dcfg_scan_out(sov_dcfg[1]), + .cspr_tspr_rf1_act(cspr_tspr_rf1_act), + // Decode + .rv_xu_vld(rv_xu_vld), + .rv_xu_ex0_ord(rv_xu_ex0_ord), + .rv_xu_ex0_instr(rv_xu_ex0_instr), + .rv_xu_ex0_ifar(rv_xu_ex0_ifar), + .ex2_ifar(ex2_ifar), + + .spr_xu_ord_read_done(spr_xu_ord_read_done), + .spr_xu_ord_write_done(spr_xu_ord_write_done), + .xu_spr_ord_ready(xu_spr_ord_ready), + .flush(flush), + + // Read Data + .tspr_cspr_ex3_tspr_rt(tspr_cspr_ex3_tspr_rt), + .spr_xu_ex4_rd_data(spr_xu_ex4_rd_data), + // Write Data + .xu_spr_ex2_rs1(xu_spr_ex2_rs1), + .cspr_tspr_ex3_spr_we(cspr_tspr_ex3_spr_we), + .ex3_spr_wd_out(ex3_spr_wd), + // SPRT Interface + .cspr_tspr_ex1_instr(cspr_tspr_ex1_instr), + .cspr_tspr_ex2_tid(cspr_tspr_ex2_tid), + + .cspr_tspr_timebase_taps(cspr_tspr_timebase_taps), + .timer_update(timer_update), + .cspr_tspr_dec_dbg_dis(cspr_tspr_dec_dbg_dis), + // Illegal SPR + .tspr_cspr_illeg_mtspr_b(tspr_cspr_illeg_mtspr_b), + .tspr_cspr_illeg_mfspr_b(tspr_cspr_illeg_mfspr_b), + .tspr_cspr_hypv_mtspr(tspr_cspr_hypv_mtspr), + .tspr_cspr_hypv_mfspr(tspr_cspr_hypv_mfspr), + // Array SPRs + .cspr_aspr_ex3_we(cspr_aspr_ex3_we), + .cspr_aspr_ex3_waddr(cspr_aspr_ex3_waddr), + .cspr_aspr_ex1_re(cspr_aspr_ex1_re), + .cspr_aspr_ex1_raddr(cspr_aspr_ex1_raddr), + .aspr_cspr_ex2_rdata(aspr_cspr_ex2_rdata[64 - `GPR_WIDTH:72 - (64/`GPR_WIDTH)]), + // Slow SPR Bus + .xu_slowspr_val_out(xu_slowspr_val_out), + .xu_slowspr_rw_out(xu_slowspr_rw_out), + .xu_slowspr_etid_out(xu_slowspr_etid_out), + .xu_slowspr_addr_out(xu_slowspr_addr_out), + .xu_slowspr_data_out(xu_slowspr_data_out), + // DCR Bus + .ac_an_dcr_act(ac_an_dcr_act), + .ac_an_dcr_val(ac_an_dcr_val), + .ac_an_dcr_read(ac_an_dcr_read), + .ac_an_dcr_user(ac_an_dcr_user), + .ac_an_dcr_etid(ac_an_dcr_etid), + .ac_an_dcr_addr(ac_an_dcr_addr), + .ac_an_dcr_data(ac_an_dcr_data), + // Trap + .spr_dec_ex4_spr_hypv(spr_dec_ex4_spr_hypv), + .spr_dec_ex4_spr_illeg(spr_dec_ex4_spr_illeg), + .spr_dec_ex4_spr_priv(spr_dec_ex4_spr_priv), + .spr_dec_ex4_np1_flush(spr_dec_ex4_np1_flush), + // Run State + .pc_xu_pm_hold_thread(pc_xu_pm_hold_thread), + .iu_xu_stop(iu_xu_stop), + .xu_iu_run_thread(xu_iu_run_thread), + .xu_pc_spr_ccr0_we(xu_pc_spr_ccr0_we), + .xu_pc_spr_ccr0_pme(xu_pc_spr_ccr0_pme), + // Quiesce + .iu_xu_quiesce(iu_xu_quiesce), + .iu_xu_icache_quiesce(iu_xu_icache_quiesce), + .lq_xu_quiesce(lq_xu_quiesce), + .mm_xu_quiesce(mm_xu_quiesce), + .bx_xu_quiesce(bx_xu_quiesce), + .xu_pc_running(xu_pc_running), + // PCCR0 + .pc_xu_extirpts_dis_on_stop(pc_xu_extirpts_dis_on_stop), + .pc_xu_timebase_dis_on_stop(pc_xu_timebase_dis_on_stop), + .pc_xu_decrem_dis_on_stop(pc_xu_decrem_dis_on_stop), + // .PERF(PERF), + .pc_xu_event_count_mode(pc_xu_event_count_mode), + .pc_xu_event_bus_enable(pc_xu_event_bus_enable), + .xu_event_bus_in(xu_event_bus_in), + .xu_event_bus_out(xu_event_bus_out), + .div_spr_running(div_spr_running), + .mul_spr_running(mul_spr_running), + // MSR Override + .pc_xu_ram_active(pc_xu_ram_active), + .pc_xu_msrovride_enab(pc_xu_msrovride_enab), + .cspr_tspr_msrovride_en(cspr_tspr_msrovride_en), + .cspr_tspr_ram_active(cspr_tspr_ram_active), + .xu_iu_msrovride_enab(xu_iu_msrovride_enab), + // LiveLock + .cspr_tspr_llen(cspr_tspr_llen), + .cspr_tspr_llpri(cspr_tspr_llpri), + .tspr_cspr_lldet(tspr_cspr_lldet), + .tspr_cspr_llpulse(tspr_cspr_llpulse), + // Reset + .pc_xu_reset_wd_complete(pc_xu_reset_wd_complete), + .pc_xu_reset_1_complete(pc_xu_reset_1_complete), + .pc_xu_reset_2_complete(pc_xu_reset_2_complete), + .pc_xu_reset_3_complete(pc_xu_reset_3_complete), + .reset_wd_complete(reset_wd_complete), + .reset_1_complete(reset_1_complete), + .reset_2_complete(reset_2_complete), + .reset_3_complete(reset_3_complete), + // Async Interrupt Req Interface + .cspr_tspr_sleep_mask(cspr_tspr_sleep_mask), + .cspr_tspr_crit_mask(cspr_tspr_crit_mask), + .cspr_tspr_ext_mask(cspr_tspr_ext_mask), + .cspr_tspr_dec_mask(cspr_tspr_dec_mask), + .cspr_tspr_fit_mask(cspr_tspr_fit_mask), + .cspr_tspr_wdog_mask(cspr_tspr_wdog_mask), + .cspr_tspr_udec_mask(cspr_tspr_udec_mask), + .cspr_tspr_perf_mask(cspr_tspr_perf_mask), + .tspr_cspr_pm_wake_up(tspr_cspr_pm_wake_up), + // DBELL + .xu_iu_dbell_interrupt(xu_iu_dbell_interrupt), + .xu_iu_cdbell_interrupt(xu_iu_cdbell_interrupt), + .xu_iu_gdbell_interrupt(xu_iu_gdbell_interrupt), + .xu_iu_gcdbell_interrupt(xu_iu_gcdbell_interrupt), + .xu_iu_gmcdbell_interrupt(xu_iu_gmcdbell_interrupt), + .iu_xu_dbell_taken(iu_xu_dbell_taken), + .iu_xu_cdbell_taken(iu_xu_cdbell_taken), + .iu_xu_gdbell_taken(iu_xu_gdbell_taken), + .iu_xu_gcdbell_taken(iu_xu_gcdbell_taken), + .iu_xu_gmcdbell_taken(iu_xu_gmcdbell_taken), + .cspr_tspr_dbell_pirtag(cspr_tspr_dbell_pirtag), + .tspr_cspr_gpir_match(tspr_cspr_gpir_match), + .lq_xu_dbell_val(lq_xu_dbell_val), + .lq_xu_dbell_type(lq_xu_dbell_type), + .lq_xu_dbell_brdcast(lq_xu_dbell_brdcast), + .lq_xu_dbell_lpid_match(lq_xu_dbell_lpid_match), + .lq_xu_dbell_pirtag(lq_xu_dbell_pirtag), + // Parity + .pc_xu_inj_sprg_ecc(pc_xu_inj_sprg_ecc), + .xu_pc_err_sprg_ecc(xu_pc_err_sprg_ecc), + .xu_pc_err_sprg_ue(xu_pc_err_sprg_ue), + // Debug + .tspr_cspr_freeze_timers(tspr_cspr_freeze_timers), + .tspr_cspr_async_int(tspr_cspr_async_int), + .tspr_cspr_ex2_np1_flush(tspr_cspr_ex2_np1_flush), + // SPRs + .lq_xu_spr_xucr0_cslc_xuop(lq_xu_spr_xucr0_cslc_xuop), + .lq_xu_spr_xucr0_cslc_binv(lq_xu_spr_xucr0_cslc_binv), + .lq_xu_spr_xucr0_clo(lq_xu_spr_xucr0_clo), + .lq_xu_spr_xucr0_cul(lq_xu_spr_xucr0_cul), + .tspr_msr_gs(tspr_msr_gs), + .tspr_msr_pr(tspr_msr_pr), + .tspr_msr_ee(tspr_msr_ee), + .tspr_msr_ce(tspr_msr_ce), + .tspr_msr_me(tspr_msr_me), + .cspr_xucr0_clkg_ctl(cspr_xucr0_clkg_ctl), + .cspr_ccr2_en_pc(cspr_ccr2_en_pc), + .cspr_ccr4_en_dnh(cspr_ccr4_en_dnh), + .xu_lsu_spr_xucr0_clfc(xu_lsu_spr_xucr0_clfc), + .spr_xesr1(spr_xesr1), + .spr_xesr2(spr_xesr2), + .perf_event_en(perf_event_en), + .spr_ccr2_en_dcr(spr_ccr2_en_dcr), + .spr_ccr2_en_trace(spr_ccr2_en_trace), + .spr_ccr2_ifratsc(spr_ccr2_ifratsc), + .spr_ccr2_ifrat(spr_ccr2_ifrat), + .spr_ccr2_dfratsc(spr_ccr2_dfratsc), + .spr_ccr2_dfrat(spr_ccr2_dfrat), + .spr_ccr2_ucode_dis(spr_ccr2_ucode_dis), + .spr_ccr2_ap(spr_ccr2_ap), + .spr_ccr2_en_attn(spr_ccr2_en_attn), + .spr_ccr2_en_ditc(spr_ccr2_en_ditc), + .spr_ccr2_en_icswx(spr_ccr2_en_icswx), + .spr_ccr2_notlb(spr_ccr2_notlb), + .spr_xucr0_trace_um(spr_xucr0_trace_um), + .xu_lsu_spr_xucr0_mbar_ack(xu_lsu_spr_xucr0_mbar_ack), + .xu_lsu_spr_xucr0_tlbsync(xu_lsu_spr_xucr0_tlbsync), + .spr_xucr0_cls(spr_xucr0_cls), + .xu_lsu_spr_xucr0_aflsta(xu_lsu_spr_xucr0_aflsta), + .spr_xucr0_mddp(spr_xucr0_mddp), + .xu_lsu_spr_xucr0_cred(xu_lsu_spr_xucr0_cred), + .xu_lsu_spr_xucr0_rel(xu_lsu_spr_xucr0_rel), + .spr_xucr0_mdcp(spr_xucr0_mdcp), + .xu_lsu_spr_xucr0_flsta(xu_lsu_spr_xucr0_flsta), + .xu_lsu_spr_xucr0_l2siw(xu_lsu_spr_xucr0_l2siw), + .xu_lsu_spr_xucr0_flh2l2(xu_lsu_spr_xucr0_flh2l2), + .xu_lsu_spr_xucr0_dcdis(xu_lsu_spr_xucr0_dcdis), + .xu_lsu_spr_xucr0_wlk(xu_lsu_spr_xucr0_wlk), + .spr_xucr4_mmu_mchk(spr_xucr4_mmu_mchk), + .spr_xucr4_mddmh(spr_xucr4_mddmh), + .cspr_debug0(cspr_debug0), + .cspr_debug1(cspr_debug1), + // Power + .vdd(vdd), + .gnd(gnd) + ); + + generate + begin : threads + genvar t; + for (t = 0; t <= `THREADS - 1; t = t + 1) + begin : thread + + xu_spr_tspr #(.hvmode(hvmode), .a2mode(a2mode)) xu_spr_tspr( + .nclk(nclk), + // CHIP IO + .an_ac_ext_interrupt(an_ac_ext_interrupt[t]), + .an_ac_crit_interrupt(an_ac_crit_interrupt[t]), + .an_ac_perf_interrupt(an_ac_perf_interrupt[t]), + .an_ac_hang_pulse(an_ac_hang_pulse[t]), + .ac_tc_machine_check(ac_tc_machine_check[t]), + .an_ac_external_mchk(an_ac_external_mchk[t]), + .instr_trace_mode(instr_trace_mode[t]), + // Act + .d_mode_dc(d_mode_dc), + .delay_lclkr_dc(delay_lclkr_dc), + .mpw1_dc_b(mpw1_dc_b), + .mpw2_dc_b(mpw2_dc_b), + .func_sl_force(func_sl_force[1 + t]), + .func_sl_thold_0_b(func_sl_thold_0_b[1 + t]), + .func_nsl_force(func_nsl_force[1 + t]), + .func_nsl_thold_0_b(func_nsl_thold_0_b[1 + t]), + .func_slp_sl_force(func_slp_sl_force[1 + t]), + .func_slp_sl_thold_0_b(func_slp_sl_thold_0_b[1 + t]), + .ccfg_sl_force(ccfg_sl_force[1 + t]), + .ccfg_sl_thold_0_b(ccfg_sl_thold_0_b[1 + t]), + .dcfg_sl_force(dcfg_sl_force[1 + t]), + .dcfg_sl_thold_0_b(dcfg_sl_thold_0_b[1 + t]), + .sg_0(sg_0[1 + t]), + .scan_in(func_scan_rpwr_in[t]), + .scan_out(func_scan_rpwr_out[t]), + .ccfg_scan_in(siv_ccfg[2 + t]), + .ccfg_scan_out(sov_ccfg[2 + t]), + .dcfg_scan_in(siv_dcfg[2 + t]), + .dcfg_scan_out(sov_dcfg[2 + t]), + .cspr_tspr_rf1_act(cspr_tspr_rf1_act), + // Read Interface + .cspr_tspr_ex1_instr(cspr_tspr_ex1_instr), + .cspr_tspr_ex2_tid(cspr_tspr_ex2_tid[t]), + .tspr_cspr_ex3_tspr_rt(tspr_cspr_ex3_tspr_rt[`GPR_WIDTH * t:`GPR_WIDTH * (t + 1) - 1]), + // Write Interface + .ex2_spr_wd(ex2_spr_wd), + .ex3_spr_we(cspr_tspr_ex3_spr_we[t]), + + .cspr_tspr_dec_dbg_dis(cspr_tspr_dec_dbg_dis[t]), + // Illegal SPR + .tspr_cspr_illeg_mtspr_b(tspr_cspr_illeg_mtspr_b[t]), + .tspr_cspr_illeg_mfspr_b(tspr_cspr_illeg_mfspr_b[t]), + .tspr_cspr_hypv_mtspr(tspr_cspr_hypv_mtspr[t]), + .tspr_cspr_hypv_mfspr(tspr_cspr_hypv_mfspr[t]), + // Interrupt Interface + .iu_xu_rfi(iu_xu_rfi[t]), + .iu_xu_rfgi(iu_xu_rfgi[t]), + .iu_xu_rfci(iu_xu_rfci[t]), + .iu_xu_rfmci(iu_xu_rfmci[t]), + .iu_xu_act(iu_xu_act[t]), + .iu_xu_int(iu_xu_int[t]), + .iu_xu_gint(iu_xu_gint[t]), + .iu_xu_cint(iu_xu_cint[t]), + .iu_xu_mcint(iu_xu_mcint[t]), + .iu_xu_nia(iu_xu_nia[t]), + .iu_xu_esr(iu_xu_esr[t]), + .iu_xu_mcsr(iu_xu_mcsr[t]), + .iu_xu_dbsr(iu_xu_dbsr[t]), + .iu_xu_dear(iu_xu_dear[t]), + .iu_xu_dear_update(iu_xu_dear_update[t]), + .iu_xu_dbsr_update(iu_xu_dbsr_update[t]), + .iu_xu_esr_update(iu_xu_esr_update[t]), + .iu_xu_force_gsrr(iu_xu_force_gsrr[t]), + .iu_xu_dbsr_ude(iu_xu_dbsr_ude[t]), + .iu_xu_dbsr_ide(iu_xu_dbsr_ide[t]), + .xu_iu_dbsr_ide(xu_iu_dbsr_ide[t]), + .int_rest_act(int_rest_act[t]), + .int_rest_ifar(int_rest_ifar_d[t]), + .ex2_ifar(ex2_ifar), + // Async Interrupt Req Interface + .xu_iu_external_mchk(xu_iu_external_mchk[t]), + .xu_iu_ext_interrupt(xu_iu_ext_interrupt[t]), + .xu_iu_dec_interrupt(xu_iu_dec_interrupt[t]), + .xu_iu_udec_interrupt(xu_iu_udec_interrupt[t]), + .xu_iu_perf_interrupt(xu_iu_perf_interrupt[t]), + .xu_iu_fit_interrupt(xu_iu_fit_interrupt[t]), + .xu_iu_crit_interrupt(xu_iu_crit_interrupt[t]), + .xu_iu_wdog_interrupt(xu_iu_wdog_interrupt[t]), + .xu_iu_gwdog_interrupt(xu_iu_gwdog_interrupt[t]), + .xu_iu_gfit_interrupt(xu_iu_gfit_interrupt[t]), + .xu_iu_gdec_interrupt(xu_iu_gdec_interrupt[t]), + .cspr_tspr_sleep_mask(cspr_tspr_sleep_mask), + .cspr_tspr_crit_mask(cspr_tspr_crit_mask[t]), + .cspr_tspr_ext_mask(cspr_tspr_ext_mask[t]), + .cspr_tspr_dec_mask(cspr_tspr_dec_mask[t]), + .cspr_tspr_fit_mask(cspr_tspr_fit_mask[t]), + .cspr_tspr_wdog_mask(cspr_tspr_wdog_mask[t]), + .cspr_tspr_udec_mask(cspr_tspr_udec_mask[t]), + .cspr_tspr_perf_mask(cspr_tspr_perf_mask[t]), + .tspr_cspr_pm_wake_up(tspr_cspr_pm_wake_up[t]), + .tspr_cspr_async_int(tspr_cspr_async_int[3 * t:3 * (t + 1) - 1]), + // DBELL Int + .cspr_tspr_dbell_pirtag(cspr_tspr_dbell_pirtag), + .tspr_cspr_gpir_match(tspr_cspr_gpir_match[t]), + .cspr_tspr_timebase_taps(cspr_tspr_timebase_taps), + .tspr_cspr_ex2_np1_flush(tspr_cspr_ex2_np1_flush[t]), + .timer_update(timer_update), + // Debug + .xu_iu_iac1_en(xu_iu_iac1_en[t]), + .xu_iu_iac2_en(xu_iu_iac2_en[t]), + .xu_iu_iac3_en(xu_iu_iac3_en[t]), + .xu_iu_iac4_en(xu_iu_iac4_en[t]), + .tspr_cspr_freeze_timers(tspr_cspr_freeze_timers[t]), + // Run State + .xu_iu_single_instr_mode(xu_iu_single_instr_mode[t]), + .xu_iu_raise_iss_pri(xu_iu_raise_iss_pri[t]), + .xu_pc_stop_dnh_instr(xu_pc_stop_dnh_instr[t]), + // LiveLock + .iu_xu_instr_cpl(iu_xu_instr_cpl[t]), + .cspr_tspr_llen(cspr_tspr_llen[t]), + .cspr_tspr_llpri(cspr_tspr_llpri[t]), + .tspr_cspr_lldet(tspr_cspr_lldet[t]), + .tspr_cspr_llpulse(tspr_cspr_llpulse[t]), + .xu_pc_err_llbust_attempt(xu_pc_err_llbust_attempt[t]), + .xu_pc_err_llbust_failed(xu_pc_err_llbust_failed[t]), + .pc_xu_inj_llbust_attempt(pc_xu_inj_llbust_attempt[t]), + .pc_xu_inj_llbust_failed(pc_xu_inj_llbust_failed[t]), + .pc_xu_inj_wdt_reset(pc_xu_inj_wdt_reset[t]), + // Resets + .reset_wd_complete(reset_wd_complete), + .reset_1_complete(reset_1_complete), + .reset_2_complete(reset_2_complete), + .reset_3_complete(reset_3_complete), + .reset_1_request(reset_1_request[t]), + .reset_2_request(reset_2_request[t]), + .reset_3_request(reset_3_request[t]), + .reset_wd_request(reset_wd_request[t]), + .xu_pc_err_wdt_reset(xu_pc_err_wdt_reset[t]), + // MSR Override + .cspr_tspr_ram_active(cspr_tspr_ram_active[t]), + .cspr_tspr_msrovride_en(cspr_tspr_msrovride_en[t]), + .pc_xu_msrovride_pr(pc_xu_msrovride_pr), + .pc_xu_msrovride_gs(pc_xu_msrovride_gs), + .pc_xu_msrovride_de(pc_xu_msrovride_de), + // SIAR + .pc_xu_spr_cesr1_pmae(pc_xu_spr_cesr1_pmae[t]), + .xu_pc_perfmon_alert(xu_pc_perfmon_alert[t]), + // SPRs + .spr_dbcr0_edm(spr_dbcr0_edm[t]), + .tspr_epcr_icm(tspr_epcr_icm[t]), + .tspr_epcr_gicm(tspr_epcr_gicm[t]), + .tspr_epcr_extgs(tspr_epcr_extgs[t]), + .tspr_fp_precise(tspr_fp_precise[t]), + .tspr_msr_de(tspr_msr_de[t]), + .tspr_msr_pr(tspr_msr_pr[t]), + .tspr_msr_is(tspr_msr_is[t]), + .tspr_msr_cm(tspr_msr_cm[t]), + .tspr_msr_gs(tspr_msr_gs[t]), + .tspr_msr_ee(tspr_msr_ee[t]), + .tspr_msr_ce(tspr_msr_ce[t]), + .tspr_msr_me(tspr_msr_me[t]), + .tspr_msr_fe0(tspr_msr_fe0[t]), + .tspr_msr_fe1(tspr_msr_fe1[t]), + .cspr_xucr0_clkg_ctl(cspr_xucr0_clkg_ctl[4:4]), + .cspr_ccr4_en_dnh(cspr_ccr4_en_dnh), + .spr_dvc1(spr_dvc1[t]), + .spr_dvc2(spr_dvc2[t]), + .spr_dbcr0_idm(spr_dbcr0_idm[t]), + .spr_dbcr0_icmp(spr_dbcr0_icmp[t]), + .spr_dbcr0_brt(spr_dbcr0_brt[t]), + .spr_dbcr0_irpt(spr_dbcr0_irpt[t]), + .spr_dbcr0_trap(spr_dbcr0_trap[t]), + .spr_dbcr0_dac1(spr_dbcr0_dac1[2*t : 2*(t+1)-1]), + .spr_dbcr0_dac2(spr_dbcr0_dac2[2*t : 2*(t+1)-1]), + .spr_dbcr0_ret(spr_dbcr0_ret[t]), + .spr_dbcr0_dac3(spr_dbcr0_dac3[2*t : 2*(t+1)-1]), + .spr_dbcr0_dac4(spr_dbcr0_dac4[2*t : 2*(t+1)-1]), + .spr_dbcr1_iac12m(spr_dbcr1_iac12m[t]), + .spr_dbcr1_iac34m(spr_dbcr1_iac34m[t]), + .spr_epcr_dtlbgs(spr_epcr_dtlbgs[t]), + .spr_epcr_itlbgs(spr_epcr_itlbgs[t]), + .spr_epcr_dsigs(spr_epcr_dsigs[t]), + .spr_epcr_isigs(spr_epcr_isigs[t]), + .spr_epcr_duvd(spr_epcr_duvd[t]), + .spr_epcr_dgtmi(spr_epcr_dgtmi[t]), + .xu_mm_spr_epcr_dmiuh(xu_mm_spr_epcr_dmiuh[t]), + .spr_msr_ucle(spr_msr_ucle[t]), + .spr_msr_spv(spr_msr_spv[t]), + .spr_msr_fp(spr_msr_fp[t]), + .spr_msr_ds(spr_msr_ds[t]), + .spr_msrp_uclep(spr_msrp_uclep[t]), + .tspr_debug(tspr_debug[12 * t:12 * (t + 1) - 1]), + // Power + .vdd(vdd), + .gnd(gnd) + ); + end + end + endgenerate + + + tri_64x72_1r1w xu_spr_aspr( + .vdd(vdd), + .vcs(vcs), + .gnd(gnd), + .nclk(nclk), + .sg_0(sg_0[0]), + .abst_sl_thold_0(abst_sl_thold_0), + .ary_nsl_thold_0(ary_nsl_thold_0), + .time_sl_thold_0(time_sl_thold_0), + .repr_sl_thold_0(repr_sl_thold_0), + // Reads + .rd0_act(cspr_aspr_ex1_re), + .rd0_adr(cspr_aspr_ex1_raddr), + .do0(aspr_cspr_ex2_rdata), + // Writes + .wr_act(cspr_aspr_ex3_we), + .wr_adr(cspr_aspr_ex3_waddr), + .di(ex3_spr_wd), + // Scan + .abst_scan_in(siv_abst[xu_spr_aspr_offset_abst]), + .abst_scan_out(sov_abst[xu_spr_aspr_offset_abst]), + .time_scan_in(siv_time[1]), + .time_scan_out(sov_time[1]), + .repr_scan_in(siv_repr[1]), + .repr_scan_out(sov_repr[1]), + // Misc Pervasive + .scan_dis_dc_b(an_ac_scan_dis_dc_b), + .scan_diag_dc(an_ac_scan_diag_dc), + .ccflush_dc(pc_xu_ccflush_dc), + .clkoff_dc_b(g8t_clkoff_dc_b), + .d_mode_dc(g8t_d_mode_dc), + .mpw1_dc_b(g8t_mpw1_dc_b), + .mpw2_dc_b(g8t_mpw2_dc_b), + .delay_lclkr_dc(g8t_delay_lclkr_dc), + // BOLT-ON + .lcb_bolt_sl_thold_0(bolt_sl_thold_0), + .pc_bo_enable_2(bo_enable_2), // general bolt-on enable + .pc_bo_reset(pc_xu_bo_reset), // reset + .pc_bo_unload(pc_xu_bo_unload), // unload sticky bits + .pc_bo_repair(pc_xu_bo_repair), // execute sticky bit decode + .pc_bo_shdata(pc_xu_bo_shdata), // shift data for timing write and diag loop + .pc_bo_select(pc_xu_bo_select), // select for mask and hier writes + .bo_pc_failout(xu_pc_bo_fail), // fail/no-fix reg + .bo_pc_diagloop(xu_pc_bo_diagout), + .tri_lcb_mpw1_dc_b(mpw1_dc_b), + .tri_lcb_mpw2_dc_b(mpw2_dc_b), + .tri_lcb_delay_lclkr_dc(delay_lclkr_dc), + .tri_lcb_clkoff_dc_b(clkoff_dc_b), + .tri_lcb_act_dis_dc(act_dis), + // ABIST + .abist_bw_odd(abist_g8t_bw_1_q), + .abist_bw_even(abist_g8t_bw_0_q), + .tc_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc), + .abist_ena_1(pc_xu_abist_ena_dc), + .wr_abst_act(abist_g8t_wenb_q), + .abist_wr_adr(abist_waddr_0_q), + .abist_di(abist_di_0_q), + .rd0_abst_act(abist_g8t1p_renb_0_q), + .abist_rd0_adr(abist_raddr_0_q), + .abist_g8t_rd0_comp_ena(abist_wl32_comp_ena_q), + .abist_raw_dc_b(pc_xu_abist_raw_dc_b), + .obs0_abist_cmp(abist_g8t_dcomp_q) + ); + + + tri_debug_mux4 xu_debug_mux( + .select_bits(debug_mux_ctrls_q), + .trace_data_in(spr_debug_data_in), + .dbg_group0(dbg_group0), + .dbg_group1(dbg_group1), + .dbg_group2(dbg_group2), + .dbg_group3(dbg_group3), + .trace_data_out(debug_data_out_d) + ); + + assign dbg_group0 = {32{1'b0}}; + assign dbg_group1 = {32{1'b0}}; + assign dbg_group2 = {32{1'b0}}; + assign dbg_group3 = {32{1'b0}}; + + assign spr_debug_data_out = debug_data_out_q; + + // FUNC Latch Instances + + tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) reset_1_request_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_nsl_force[0]), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b[0]), + .sg(sg_0[0]), + .scin( siv[reset_1_request_offset]), + .scout(sov[reset_1_request_offset]), + .din(reset_1_request_d), + .dout(reset_1_request_q) + ); + + tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) reset_2_request_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_nsl_force[0]), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b[0]), + .sg(sg_0[0]), + .scin( siv[reset_2_request_offset]), + .scout(sov[reset_2_request_offset]), + .din(reset_2_request_d), + .dout(reset_2_request_q) + ); + + tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) reset_3_request_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_nsl_force[0]), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b[0]), + .sg(sg_0[0]), + .scin( siv[reset_3_request_offset]), + .scout(sov[reset_3_request_offset]), + .din(reset_3_request_d), + .dout(reset_3_request_q) + ); + + tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) reset_wd_request_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(1'b1), + .force_t(func_nsl_force[0]), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b[0]), + .sg(sg_0[0]), + .scin( siv[reset_wd_request_offset]), + .scout(sov[reset_wd_request_offset]), + .din(reset_wd_request_d), + .dout(reset_wd_request_q) + ); + generate + begin : int_rest_ifar_latch_gen + genvar r; + for (r = 0; r <= `THREADS-1; r = r + 1) + begin : thread + + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0), .NEEDS_SRESET(1)) int_rest_ifar_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(int_rest_act[r]), + .force_t(func_sl_force[0]), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b[0]), + .sg(sg_0[0]), + .scin(siv [int_rest_ifar_offset+r*`EFF_IFAR_ARCH:int_rest_ifar_offset+(r+1)*`EFF_IFAR_ARCH-1]), + .scout(sov[int_rest_ifar_offset+r*`EFF_IFAR_ARCH:int_rest_ifar_offset+(r+1)*`EFF_IFAR_ARCH-1]), + .din(int_rest_ifar_d[r]), + .dout(int_rest_ifar_q[r]) + ); + end + end + endgenerate + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) trace_bus_enable_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force[0]), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b[0]), + .sg(sg_0[0]), + .scin(siv[trace_bus_enable_offset]), + .scout(sov[trace_bus_enable_offset]), + .din(pc_xu_trace_bus_enable), + .dout(trace_bus_enable_q) + ); + tri_rlmreg_p #(.WIDTH(11), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) debug_mux_ctrls_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(trace_bus_enable_q), + .force_t(func_slp_sl_force[0]), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b[0]), + .sg(sg_0[0]), + .scin (siv[debug_mux_ctrls_offset : debug_mux_ctrls_offset + 11-1]), + .scout(sov[debug_mux_ctrls_offset : debug_mux_ctrls_offset + 11-1]), + .din(spr_debug_mux_ctrls), + .dout(debug_mux_ctrls_q) + ); + tri_rlmreg_p #(.WIDTH(32), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) debug_data_out_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(trace_bus_enable_q), + .force_t(func_slp_sl_force[0]), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b[0]), + .sg(sg_0[0]), + .scin (siv[debug_data_out_offset : debug_data_out_offset + 31]), + .scout(sov[debug_data_out_offset : debug_data_out_offset + 31]), + .din(debug_data_out_d), + .dout(debug_data_out_q) + ); + + // ABST Latch Instances + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) abist_g8t_wenb_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(pc_xu_abist_ena_dc), + .force_t(abst_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(abst_sl_thold_0_b), + .sg(sg_0[0]), + .scin(siv_abst[abist_g8t_wenb_offset_abst]), + .scout(sov_abst[abist_g8t_wenb_offset_abst]), + .din(pc_xu_abist_g8t_wenb), + .dout(abist_g8t_wenb_q) + ); + + tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) abist_waddr_0_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(pc_xu_abist_ena_dc), + .force_t(abst_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(abst_sl_thold_0_b), + .sg(sg_0[0]), + .scin(siv_abst[abist_waddr_0_offset_abst:abist_waddr_0_offset_abst + 6 - 1]), + .scout(sov_abst[abist_waddr_0_offset_abst:abist_waddr_0_offset_abst + 6 - 1]), + .din(pc_xu_abist_waddr_0), + .dout(abist_waddr_0_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) abist_di_0_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(pc_xu_abist_ena_dc), + .force_t(abst_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(abst_sl_thold_0_b), + .sg(sg_0[0]), + .scin(siv_abst[abist_di_0_offset_abst:abist_di_0_offset_abst + 4 - 1]), + .scout(sov_abst[abist_di_0_offset_abst:abist_di_0_offset_abst + 4 - 1]), + .din(pc_xu_abist_di_0), + .dout(abist_di_0_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) abist_g8t1p_renb_0_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(pc_xu_abist_ena_dc), + .force_t(abst_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(abst_sl_thold_0_b), + .sg(sg_0[0]), + .scin(siv_abst[abist_g8t1p_renb_0_offset_abst]), + .scout(sov_abst[abist_g8t1p_renb_0_offset_abst]), + .din(pc_xu_abist_g8t1p_renb_0), + .dout(abist_g8t1p_renb_0_q) + ); + + tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) abist_raddr_0_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(pc_xu_abist_ena_dc), + .force_t(abst_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(abst_sl_thold_0_b), + .sg(sg_0[0]), + .scin(siv_abst[abist_raddr_0_offset_abst:abist_raddr_0_offset_abst + 6 - 1]), + .scout(sov_abst[abist_raddr_0_offset_abst:abist_raddr_0_offset_abst + 6 - 1]), + .din(pc_xu_abist_raddr_0), + .dout(abist_raddr_0_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) abist_wl32_comp_ena_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(pc_xu_abist_ena_dc), + .force_t(abst_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(abst_sl_thold_0_b), + .sg(sg_0[0]), + .scin(siv_abst[abist_wl32_comp_ena_offset_abst]), + .scout(sov_abst[abist_wl32_comp_ena_offset_abst]), + .din(pc_xu_abist_wl32_comp_ena), + .dout(abist_wl32_comp_ena_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) abist_g8t_dcomp_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(pc_xu_abist_ena_dc), + .force_t(abst_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(abst_sl_thold_0_b), + .sg(sg_0[0]), + .scin(siv_abst[abist_g8t_dcomp_offset_abst:abist_g8t_dcomp_offset_abst + 4 - 1]), + .scout(sov_abst[abist_g8t_dcomp_offset_abst:abist_g8t_dcomp_offset_abst + 4 - 1]), + .din(pc_xu_abist_g8t_dcomp), + .dout(abist_g8t_dcomp_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) abist_g8t_bw_1_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(pc_xu_abist_ena_dc), + .force_t(abst_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(abst_sl_thold_0_b), + .sg(sg_0[0]), + .scin(siv_abst[abist_g8t_bw_1_offset_abst]), + .scout(sov_abst[abist_g8t_bw_1_offset_abst]), + .din(pc_xu_abist_g8t_bw_1), + .dout(abist_g8t_bw_1_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) abist_g8t_bw_0_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(pc_xu_abist_ena_dc), + .force_t(abst_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc), + .mpw1_b(mpw1_dc_b), + .mpw2_b(mpw2_dc_b), + .thold_b(abst_sl_thold_0_b), + .sg(sg_0[0]), + .scin(siv_abst[abist_g8t_bw_0_offset_abst]), + .scout(sov_abst[abist_g8t_bw_0_offset_abst]), + .din(pc_xu_abist_g8t_bw_0), + .dout(abist_g8t_bw_0_q) + ); + + tri_regs #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) abst_scan_in_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .force_t(so_force), + .delay_lclkr(delay_lclkr_dc), + .thold_b(abst_so_thold_0_b), + .scin(siv_abst[0:0]), + .scout(sov_abst[0:0]) + ); + + tri_regs #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) abst_scan_out_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .force_t(so_force), + .delay_lclkr(delay_lclkr_dc), + .thold_b(abst_so_thold_0_b), + .scin(siv_abst[scan_right_abst-1:scan_right_abst-1]), + .scout(sov_abst[scan_right_abst-1:scan_right_abst-1]) + ); + + tri_regs #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) bcfg_scan_in_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .force_t(so_force), + .delay_lclkr(delay_lclkr_dc), + .thold_b(bcfg_so_thold_0_b), + .scin(siv_bcfg[0:0]), + .scout(sov_bcfg[0:0]) + ); + + tri_regs #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) bcfg_scan_out_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .force_t(so_force), + .delay_lclkr(delay_lclkr_dc), + .thold_b(bcfg_so_thold_0_b), + .scin(siv_bcfg[2:2]), + .scout(sov_bcfg[2:2]) + ); + + tri_regs #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ccfg_scan_in_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .force_t(so_force), + .delay_lclkr(delay_lclkr_dc), + .thold_b(ccfg_so_thold_0_b), + .scin(siv_ccfg[0:0]), + .scout(sov_ccfg[0:0]) + ); + + tri_regs #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ccfg_scan_out_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .force_t(so_force), + .delay_lclkr(delay_lclkr_dc), + .thold_b(ccfg_so_thold_0_b), + .scin(siv_ccfg[`THREADS+2:`THREADS+2]), + .scout(sov_ccfg[`THREADS+2:`THREADS+2]) + ); + + tri_regs #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) dcfg_scan_in_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .force_t(so_force), + .delay_lclkr(delay_lclkr_dc), + .thold_b(dcfg_so_thold_0_b), + .scin(siv_dcfg[0:0]), + .scout(sov_dcfg[0:0]) + ); + + tri_regs #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) dcfg_scan_out_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .force_t(so_force), + .delay_lclkr(delay_lclkr_dc), + .thold_b(dcfg_so_thold_0_b), + .scin(siv_dcfg[`THREADS+2:`THREADS+2]), + .scout(sov_dcfg[`THREADS+2:`THREADS+2]) + ); + + tri_regs #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) time_scan_in_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .force_t(so_force), + .delay_lclkr(delay_lclkr_dc), + .thold_b(time_so_thold_0_b), + .scin(siv_time[0:0]), + .scout(sov_time[0:0]) + ); + + tri_regs #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) time_scan_out_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .force_t(so_force), + .delay_lclkr(delay_lclkr_dc), + .thold_b(time_so_thold_0_b), + .scin(siv_time[2:2]), + .scout(sov_time[2:2]) + ); + + tri_regs #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) repr_scan_in_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .force_t(so_force), + .delay_lclkr(delay_lclkr_dc), + .thold_b(repr_so_thold_0_b), + .scin(siv_repr[0:0]), + .scout(sov_repr[0:0]) + ); + + tri_regs #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) repr_scan_out_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .force_t(so_force), + .delay_lclkr(delay_lclkr_dc), + .thold_b(repr_so_thold_0_b), + .scin(siv_repr[2:2]), + .scout(sov_repr[2:2]) + ); + + tri_regs #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) gptr_scan_in_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .force_t(so_force), + .delay_lclkr(1'b1), + .thold_b(gptr_so_thold_0_b), + .scin(siv_gptr[0:0]), + .scout(sov_gptr[0:0]) + ); + + tri_regs #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) gptr_scan_out_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .force_t(so_force), + .delay_lclkr(1'b1), + .thold_b(gptr_so_thold_0_b), + .scin(siv_gptr[2:2]), + .scout(sov_gptr[2:2]) + ); + + tri_regs #(.WIDTH((`THREADS+2)), .INIT(0), .NEEDS_SRESET(1)) func_scan_in_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .force_t(so_force), + .delay_lclkr(delay_lclkr_dc), + .thold_b(func_so_thold_0_b), + .scin(func_scan_in), + .scout(func_scan_rpwr_in) + ); + + tri_regs #(.WIDTH((`THREADS+2)), .INIT(0), .NEEDS_SRESET(1)) func_scan_out_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .force_t(so_force), + .delay_lclkr(delay_lclkr_dc), + .thold_b(func_so_thold_0_b), + .scin(func_scan_rpwr_out), + .scout(func_scan_gate_out) + ); + + //----------------------------------------------- + // Pervasive + //----------------------------------------------- + + tri_lcbcntl_array_mac lcbctrl_g8t( + .vdd(vdd), + .gnd(gnd), + .sg(sg_0[0]), + .nclk(nclk), + .scan_diag_dc(an_ac_scan_diag_dc), + .thold(gptr_sl_thold_0), + .clkoff_dc_b(g8t_clkoff_dc_b), + .delay_lclkr_dc(g8t_delay_lclkr_dc[0:4]), + .act_dis_dc(), + .d_mode_dc(g8t_d_mode_dc), + .mpw1_dc_b(g8t_mpw1_dc_b[0:4]), + .mpw2_dc_b(g8t_mpw2_dc_b), + .scan_in(siv_gptr[1]), + .scan_out(sov_gptr[1]) + ); + + + tri_plat #(.WIDTH(1)) perv_2to1_reg_00 (.din(func_slp_sl_thold_2 ),.q(func_slp_sl_thold_1 ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_2to1_reg_01 (.din(func_sl_thold_2 ),.q(func_sl_thold_1 ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_2to1_reg_02 (.din(func_slp_nsl_thold_2 ),.q(func_slp_nsl_thold_1 ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_2to1_reg_03 (.din(func_nsl_thold_2 ),.q(func_nsl_thold_1 ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_2to1_reg_04 (.din(time_sl_thold_2 ),.q(time_sl_thold_1 ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_2to1_reg_05 (.din(repr_sl_thold_2 ),.q(repr_sl_thold_1 ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_2to1_reg_06 (.din(gptr_sl_thold_2 ),.q(gptr_sl_thold_1 ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_2to1_reg_07 (.din(bolt_sl_thold_2 ),.q(bolt_sl_thold_1 ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_2to1_reg_08 (.din(abst_sl_thold_2 ),.q(abst_sl_thold_1 ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_2to1_reg_09 (.din(ary_nsl_thold_2 ),.q(ary_nsl_thold_1 ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_2to1_reg_10 (.din(cfg_sl_thold_2 ),.q(cfg_sl_thold_1 ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_2to1_reg_11 (.din(cfg_slp_sl_thold_2 ),.q(cfg_slp_sl_thold_1 ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_2to1_reg_12 (.din(sg_2 ),.q(sg_1 ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_2to1_reg_13 (.din(fce_2 ),.q(fce_1 ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); + + generate + begin : perv_1to0_reg_gen + genvar t; + for (t = 0; t <= `THREADS; t = t + 1) + begin : thread + + tri_plat #(.WIDTH(1)) perv_1to0_reg_0 (.din(func_slp_sl_thold_1),.q(func_slp_sl_thold_0[t] ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_1to0_reg_1 (.din(func_sl_thold_1 ),.q(func_sl_thold_0[t] ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_1to0_reg_2 (.din(func_nsl_thold_1 ),.q(func_nsl_thold_0[t] ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_1to0_reg_3 (.din(cfg_sl_thold_1 ),.q(cfg_sl_thold_0[t] ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_1to0_reg_4 (.din(sg_1 ),.q(sg_0[t] ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_1to0_reg_5 (.din(fce_1 ),.q(fce_0[t] ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); + + + tri_lcbor perv_lcbor_cfg_sl( + .clkoff_b(clkoff_dc_b), + .thold(cfg_sl_thold_0[t]), + .sg(sg_0[t]), + .act_dis(act_dis), + .force_t(cfg_sl_force[t]), + .thold_b(cfg_sl_thold_0_b[t]) + ); + + + tri_lcbor perv_lcbor_func_sl( + .clkoff_b(clkoff_dc_b), + .thold(func_sl_thold_0[t]), + .sg(sg_0[t]), + .act_dis(act_dis), + .force_t(func_sl_force[t]), + .thold_b(func_sl_thold_0_b[t]) + ); + + + tri_lcbor perv_lcbor_func_slp_sl( + .clkoff_b(clkoff_dc_b), + .thold(func_slp_sl_thold_0[t]), + .sg(sg_0[t]), + .act_dis(act_dis), + .force_t(func_slp_sl_force[t]), + .thold_b(func_slp_sl_thold_0_b[t]) + ); + + + tri_lcbor perv_lcbor_func_nsl( + .clkoff_b(clkoff_dc_b), + .thold(func_nsl_thold_0[t]), + .sg(fce_0[t]), + .act_dis(act_dis), + .force_t(func_nsl_force[t]), + .thold_b(func_nsl_thold_0_b[t]) + ); + end + end + endgenerate + + assign ccfg_sl_force = cfg_sl_force; + assign ccfg_sl_thold_0_b = cfg_sl_thold_0_b; + assign dcfg_sl_force[0:`THREADS] = cfg_sl_force[0:`THREADS]; + assign dcfg_sl_thold_0_b[0:`THREADS] = cfg_sl_thold_0_b[0:`THREADS]; + + assign bcfg_sl_force[0] = cfg_sl_force[0]; + assign bcfg_sl_thold_0_b[0] = cfg_sl_thold_0_b[0]; + + assign bcfg_slp_sl_force = cfg_slp_sl_force; + assign bcfg_slp_sl_thold_0_b = cfg_slp_sl_thold_0_b; + assign ccfg_slp_sl_force = cfg_slp_sl_force; + assign ccfg_slp_sl_thold_0_b = cfg_slp_sl_thold_0_b; + + + tri_lcbor perv_lcbor_cfg_slp_sl( + .clkoff_b(clkoff_dc_b), + .thold(cfg_slp_sl_thold_0), + .sg(sg_0[0]), + .act_dis(act_dis), + .force_t(cfg_slp_sl_force), + .thold_b(cfg_slp_sl_thold_0_b) + ); + + + tri_lcbor perv_lcbor_func_slp_nsl( + .clkoff_b(clkoff_dc_b), + .thold(func_slp_nsl_thold_0), + .sg(fce_0[0]), + .act_dis(act_dis), + .force_t(func_slp_nsl_force), + .thold_b(func_slp_nsl_thold_0_b) + ); + + + tri_plat #(.WIDTH(1)) perv_1to0_reg_0 (.din(abst_sl_thold_1 ),.q(abst_sl_thold_0 ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_1to0_reg_1 (.din(ary_nsl_thold_1 ),.q(ary_nsl_thold_0 ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_1to0_reg_2 (.din(time_sl_thold_1 ),.q(time_sl_thold_0 ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_1to0_reg_3 (.din(repr_sl_thold_1 ),.q(repr_sl_thold_0 ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_1to0_reg_4 (.din(gptr_sl_thold_1 ),.q(gptr_sl_thold_0 ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_1to0_reg_5 (.din(bolt_sl_thold_1 ),.q(bolt_sl_thold_0 ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_1to0_reg_6 (.din(func_slp_nsl_thold_1 ),.q(func_slp_nsl_thold_0 ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_1to0_reg_7 (.din(cfg_slp_sl_thold_1 ),.q(cfg_slp_sl_thold_0 ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); + + + tri_lcbor perv_lcbor_abst_sl( + .clkoff_b(clkoff_dc_b), + .thold(abst_sl_thold_0), + .sg(sg_0[0]), + .act_dis(act_dis), + .force_t(abst_sl_force), + .thold_b(abst_sl_thold_0_b) + ); + + assign so_force = sg_0[0]; + assign abst_so_thold_0_b = (~abst_sl_thold_0); + assign bcfg_so_thold_0_b = (~cfg_sl_thold_0[0]); + assign ccfg_so_thold_0_b = (~cfg_sl_thold_0[0]); + assign dcfg_so_thold_0_b = (~cfg_sl_thold_0[0]); + assign time_so_thold_0_b = (~time_sl_thold_0); + assign repr_so_thold_0_b = (~repr_sl_thold_0); + assign gptr_so_thold_0_b = (~gptr_sl_thold_0); + assign func_so_thold_0_b = (~func_sl_thold_0[0]); + + assign func_scan_out = an_ac_scan_dis_dc_b==1'b1 ? func_scan_gate_out : {`THREADS+2{1'b0}}; + + assign siv[0:scan_right-1] = {sov[1:scan_right-1], func_scan_rpwr_in[`THREADS + 1]}; + assign func_scan_rpwr_out[`THREADS + 1] = sov[0]; + + assign siv_abst[0:scan_right_abst-1] = {sov_abst[1:scan_right_abst-1], abst_scan_in}; + assign abst_scan_out = sov_abst[0] & an_ac_scan_dis_dc_b; + + assign siv_bcfg[0:2] = {sov_bcfg[1:2], bcfg_scan_in}; + assign bcfg_scan_out = sov_bcfg[0] & an_ac_scan_dis_dc_b; + + assign siv_ccfg[0:`THREADS+2] = {sov_ccfg[1:`THREADS+2], ccfg_scan_in}; + assign ccfg_scan_out = sov_ccfg[0] & an_ac_scan_dis_dc_b; + + assign siv_dcfg[0:`THREADS+2] = {sov_dcfg[1:`THREADS+2], dcfg_scan_in}; + assign dcfg_scan_out = sov_dcfg[0] & an_ac_scan_dis_dc_b; + + assign siv_time[0:2] = {sov_time[1:2], time_scan_in}; + assign time_scan_out = sov_time[0] & an_ac_scan_dis_dc_b; + + assign siv_repr[0:2] = {sov_repr[1:2], repr_scan_in}; + assign repr_scan_out = sov_repr[0] & an_ac_scan_dis_dc_b; + + assign siv_gptr[0:2] = {sov_gptr[1:2], gptr_scan_in}; + assign gptr_scan_out = sov_gptr[0] & an_ac_scan_dis_dc_b; + +endmodule diff --git a/dev/verilog/work/xu_spr_cspr.v b/dev/verilog/work/xu_spr_cspr.v new file mode 100755 index 0000000..2213bd7 --- /dev/null +++ b/dev/verilog/work/xu_spr_cspr.v @@ -0,0 +1,4970 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: XU SPR - per core registers & array +// +//***************************************************************************** +`include "tri_a2o.vh" +module xu_spr_cspr +#( + parameter hvmode = 1, + parameter a2mode = 1, + parameter spr_xucr0_init = 1120 +)( + input [0:`NCLK_WIDTH-1] nclk, + + // CHIP IO + input [0:`THREADS-1] an_ac_reservation_vld, + input an_ac_tb_update_enable, + input an_ac_tb_update_pulse, + input [0:`THREADS-1] an_ac_sleep_en, + input [54:61] an_ac_coreid, + input [32:35] an_ac_chipid_dc, + input [8:15] spr_pvr_version_dc, + input [12:15] spr_pvr_revision_dc, + input [16:19] spr_pvr_revision_minor_dc, + input pc_xu_instr_trace_mode, + input [0:1] pc_xu_instr_trace_tid, + output [0:`THREADS-1] instr_trace_mode, + + input d_mode_dc, + input [0:0] delay_lclkr_dc, + input [0:0] mpw1_dc_b, + input mpw2_dc_b, + + input bcfg_sl_force, + input bcfg_sl_thold_0_b, + input bcfg_slp_sl_force, + input bcfg_slp_sl_thold_0_b, + input ccfg_sl_force, + input ccfg_sl_thold_0_b, + input ccfg_slp_sl_force, + input ccfg_slp_sl_thold_0_b, + input dcfg_sl_force, + input dcfg_sl_thold_0_b, + input func_sl_force, + input func_sl_thold_0_b, + input func_slp_sl_force, + input func_slp_sl_thold_0_b, + input func_nsl_force, + input func_nsl_thold_0_b, + input sg_0, + input [0:1] scan_in, + output [0:1] scan_out, + input bcfg_scan_in, + output bcfg_scan_out, + input ccfg_scan_in, + output ccfg_scan_out, + input dcfg_scan_in, + output dcfg_scan_out, + + output cspr_tspr_rf1_act, + + // Decode + input [0:`THREADS-1] rv_xu_vld, + input rv_xu_ex0_ord, + input [0:31] rv_xu_ex0_instr, + input [62-`EFF_IFAR_WIDTH:61] rv_xu_ex0_ifar, + output [62-`EFF_IFAR_WIDTH:61] ex2_ifar, + + output spr_xu_ord_read_done, + output spr_xu_ord_write_done, + input xu_spr_ord_ready, + input [0:`THREADS-1] flush, + + // Read Data + input [0:`GPR_WIDTH*`THREADS-1] tspr_cspr_ex3_tspr_rt, + output [64-`GPR_WIDTH:63] spr_xu_ex4_rd_data, + + // Write Data + input [64-`GPR_WIDTH:63] xu_spr_ex2_rs1, + output [0:`THREADS-1] cspr_tspr_ex3_spr_we, + output [64-`GPR_WIDTH:64+8-(64/`GPR_WIDTH)] ex3_spr_wd_out, + + // SPRT Interface + output [0:`THREADS-1] cspr_tspr_ex2_tid, + output [0:31] cspr_tspr_ex1_instr, + output [0:`THREADS-1] cspr_tspr_dec_dbg_dis, + + // Illegal SPR + input [0:`THREADS-1] tspr_cspr_illeg_mtspr_b, + input [0:`THREADS-1] tspr_cspr_illeg_mfspr_b, + input [0:`THREADS-1] tspr_cspr_hypv_mtspr, + input [0:`THREADS-1] tspr_cspr_hypv_mfspr, + + // Array SPRs + output cspr_aspr_ex3_we, + output [0:5] cspr_aspr_ex3_waddr, + output cspr_aspr_ex1_re, + output [0:5] cspr_aspr_ex1_raddr, + input [64-`GPR_WIDTH:72-(64/`GPR_WIDTH)] aspr_cspr_ex2_rdata, + + // Slow SPR Bus + output xu_slowspr_val_out, + output xu_slowspr_rw_out, + output [0:1] xu_slowspr_etid_out, + output [11:20] xu_slowspr_addr_out, + output [64-`GPR_WIDTH:63] xu_slowspr_data_out, + + // DCR Bus + output ac_an_dcr_act, + output ac_an_dcr_val, + output ac_an_dcr_read, + output ac_an_dcr_user, + output [0:1] ac_an_dcr_etid, + output [11:20] ac_an_dcr_addr, + output [64-`GPR_WIDTH:63] ac_an_dcr_data, + + // Trap + output spr_dec_ex4_spr_hypv, + output spr_dec_ex4_spr_illeg, + output spr_dec_ex4_spr_priv, + output spr_dec_ex4_np1_flush, + + output [0:9] cspr_tspr_timebase_taps, + output timer_update, + + // Run State + input pc_xu_pm_hold_thread, + input [0:`THREADS-1] iu_xu_stop, + output [0:`THREADS-1] xu_iu_run_thread, + output [0:`THREADS-1] xu_pc_spr_ccr0_we, + output [0:1] xu_pc_spr_ccr0_pme, + + // Quiesce + input [0:`THREADS-1] iu_xu_quiesce, + input [0:`THREADS-1] iu_xu_icache_quiesce, + input [0:`THREADS-1] lq_xu_quiesce, + input [0:`THREADS-1] mm_xu_quiesce, + input [0:`THREADS-1] bx_xu_quiesce, + output [0:`THREADS-1] xu_pc_running, + + // PCCR0 + input pc_xu_extirpts_dis_on_stop, + input pc_xu_timebase_dis_on_stop, + input pc_xu_decrem_dis_on_stop, + + // PERF + input [0:2] pc_xu_event_count_mode, + input pc_xu_event_bus_enable, + input [0:4*`THREADS-1] xu_event_bus_in, + output [0:4*`THREADS-1] xu_event_bus_out, + input [0:`THREADS-1] div_spr_running, + input [0:`THREADS-1] mul_spr_running, + + + // MSR Override + input [0:`THREADS-1] pc_xu_ram_active, + input pc_xu_msrovride_enab, + output [0:`THREADS-1] cspr_tspr_msrovride_en, + output [0:`THREADS-1] cspr_tspr_ram_active, + + // LiveLock + output [0:`THREADS-1] cspr_tspr_llen, + output [0:`THREADS-1] cspr_tspr_llpri, + input [0:`THREADS-1] tspr_cspr_lldet, + input [0:`THREADS-1] tspr_cspr_llpulse, + + // Reset + input pc_xu_reset_wd_complete, + input pc_xu_reset_3_complete, + input pc_xu_reset_2_complete, + input pc_xu_reset_1_complete, + output reset_wd_complete, + output reset_3_complete, + output reset_2_complete, + output reset_1_complete, + + // Async Interrupt Masking + output [0:`THREADS-1] cspr_tspr_crit_mask, + output [0:`THREADS-1] cspr_tspr_ext_mask, + output [0:`THREADS-1] cspr_tspr_dec_mask, + output [0:`THREADS-1] cspr_tspr_fit_mask, + output [0:`THREADS-1] cspr_tspr_wdog_mask, + output [0:`THREADS-1] cspr_tspr_udec_mask, + output [0:`THREADS-1] cspr_tspr_perf_mask, + output cspr_tspr_sleep_mask, + + input [0:`THREADS-1] tspr_cspr_pm_wake_up, + + // More Async Interrupts + output [0:`THREADS-1] xu_iu_dbell_interrupt, + output [0:`THREADS-1] xu_iu_cdbell_interrupt, + output [0:`THREADS-1] xu_iu_gdbell_interrupt, + output [0:`THREADS-1] xu_iu_gcdbell_interrupt, + output [0:`THREADS-1] xu_iu_gmcdbell_interrupt, + input [0:`THREADS-1] iu_xu_dbell_taken, + input [0:`THREADS-1] iu_xu_cdbell_taken, + input [0:`THREADS-1] iu_xu_gdbell_taken, + input [0:`THREADS-1] iu_xu_gcdbell_taken, + input [0:`THREADS-1] iu_xu_gmcdbell_taken, + + // DBELL Int + input lq_xu_dbell_val, + input [0:4] lq_xu_dbell_type, + input lq_xu_dbell_brdcast, + input lq_xu_dbell_lpid_match, + input [50:63] lq_xu_dbell_pirtag, + output [50:63] cspr_tspr_dbell_pirtag, + input [0:`THREADS-1] tspr_cspr_gpir_match, + + // Parity + output [0:`THREADS-1] xu_pc_err_sprg_ecc, + output [0:`THREADS-1] xu_pc_err_sprg_ue, + input [0:`THREADS-1] pc_xu_inj_sprg_ecc, + + // Debug + input [0:`THREADS-1] tspr_cspr_freeze_timers, + input [0:3*`THREADS-1] tspr_cspr_async_int, + + input [0:`THREADS-1] tspr_cspr_ex2_np1_flush, + + output [0:`THREADS-1] xu_iu_msrovride_enab, + input lq_xu_spr_xucr0_cslc_xuop, + input lq_xu_spr_xucr0_cslc_binv, + input lq_xu_spr_xucr0_clo, + input lq_xu_spr_xucr0_cul, + output cspr_ccr2_en_pc, + output cspr_ccr4_en_dnh, + input [0:`THREADS-1] tspr_msr_ee, + input [0:`THREADS-1] tspr_msr_ce, + input [0:`THREADS-1] tspr_msr_me, + input [0:`THREADS-1] tspr_msr_gs, + input [0:`THREADS-1] tspr_msr_pr, + output [0:4] cspr_xucr0_clkg_ctl, + output xu_lsu_spr_xucr0_clfc, + output [0:31] spr_xesr1, + output [0:31] spr_xesr2, + output [0:`THREADS-1] perf_event_en, + output spr_ccr2_en_dcr, + output spr_ccr2_en_trace, + output [0:8] spr_ccr2_ifratsc, + output spr_ccr2_ifrat, + output [0:8] spr_ccr2_dfratsc, + output spr_ccr2_dfrat, + output spr_ccr2_ucode_dis, + output [0:3] spr_ccr2_ap, + output spr_ccr2_en_attn, + output spr_ccr2_en_ditc, + output spr_ccr2_en_icswx, + output spr_ccr2_notlb, + output [0:3] spr_xucr0_trace_um, + output xu_lsu_spr_xucr0_mbar_ack, + output xu_lsu_spr_xucr0_tlbsync, + output spr_xucr0_cls, + output xu_lsu_spr_xucr0_aflsta, + output spr_xucr0_mddp, + output xu_lsu_spr_xucr0_cred, + output xu_lsu_spr_xucr0_rel, + output spr_xucr0_mdcp, + output xu_lsu_spr_xucr0_flsta, + output xu_lsu_spr_xucr0_l2siw, + output xu_lsu_spr_xucr0_flh2l2, + output xu_lsu_spr_xucr0_dcdis, + output xu_lsu_spr_xucr0_wlk, + output spr_xucr4_mmu_mchk, + output spr_xucr4_mddmh, + + output [0:39] cspr_debug0, + output [0:63] cspr_debug1, + + // Power + inout vdd, + inout gnd +); + + localparam DEX0 = 0; + localparam DEX1 = 0; + localparam DEX2 = 0; + localparam DEX3 = 0; + localparam DEX4 = 0; + localparam DEX5 = 0; + localparam DEX6 = 0; + localparam DWR = 0; + localparam DX = 0; + localparam a2hvmode = ((a2mode + hvmode) % 1); + // Types + // SPR Registers + // SPR Registers + wire [62:63] ccr0_d, ccr0_q; + wire [40:63] ccr1_d, ccr1_q; + wire [32:63] ccr2_d, ccr2_q; + wire [63:63] ccr4_d, ccr4_q; + wire [32:63] tbl_d, tbl_q; + wire [32:63] tbu_d, tbu_q; + wire [64-(`THREADS):63] tens_d, tens_q; + wire [32:63] xesr1_d, xesr1_q; + wire [32:63] xesr2_d, xesr2_q; + wire [38:63] xucr0_d, xucr0_q; + wire [60:63] xucr4_d, xucr4_q; + // FUNC Scanchain + localparam ccr1_offset = 0; + localparam tbl_offset = ccr1_offset + 24; + localparam tbu_offset = tbl_offset + 32; + localparam xesr1_offset = tbu_offset + 32; + localparam xesr2_offset = xesr1_offset + 32; + localparam last_reg_offset = xesr2_offset + 32; + // BCFG Scanchain + localparam ccr0_offset_bcfg = 0; + localparam tens_offset_bcfg = ccr0_offset_bcfg + 2; + localparam last_reg_offset_bcfg = tens_offset_bcfg + `THREADS; + // CCFG Scanchain + localparam ccr2_offset_ccfg = 0; + localparam ccr4_offset_ccfg = ccr2_offset_ccfg + 32; + localparam xucr0_offset_ccfg = ccr4_offset_ccfg + 1; + localparam last_reg_offset_ccfg = xucr0_offset_ccfg + 26; + // DCFG Scanchain + localparam xucr4_offset_dcfg = 0; + localparam last_reg_offset_dcfg = xucr4_offset_dcfg + 4; + // Latches + wire [1:4] exx_act_q, exx_act_d ; // input=>exx_act_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] ex0_val_q, rv2_val ; // input=>rv2_val , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] ex1_val_q, ex0_val ; // input=>ex0_val , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire ex1_aspr_act_q, ex1_aspr_act_d ; // input=>ex1_aspr_act_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:1] ex1_aspr_tid_q, ex1_aspr_tid_d ; // input=>ex1_aspr_tid_d , act=>exx_act[0] , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:1] ex1_tid_q, ex0_tid ; // input=>ex0_tid , act=>exx_act[0] , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:31] ex1_instr_q ; // input=>rv_xu_ex0_instr , act=>exx_act[0] , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:0] ex1_msr_gs_q, ex1_msr_gs_d ; // input=>ex1_msr_gs_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] ex2_val_q, ex1_val ; // input=>ex1_val , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire ex2_val_rd_q, ex2_val_rd_d ; // input=>ex2_val_rd_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire ex2_val_wr_q, ex2_val_wr_d ; // input=>ex2_val_wr_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:1] ex2_tid_q ; // input=>ex1_tid_q , act=>exx_act[1] , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:3] ex2_aspr_addr_q, ex1_aspr_addr ; // input=>ex1_aspr_addr , act=>exx_act[1] , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire ex2_is_mfspr_q, ex1_is_mfspr ; // input=>ex1_is_mfspr , act=>exx_act[1] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire ex2_is_mftb_q, ex1_is_mftb ; // input=>ex1_is_mftb , act=>exx_act[1] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire ex2_is_mtmsr_q, ex2_is_mtmsr_d ; // input=>ex1_is_mtmsr , act=>exx_act[1] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire ex2_is_mtspr_q, ex1_is_mtspr ; // input=>ex1_is_mtspr , act=>exx_act[1] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire ex2_is_wait_q, ex1_is_wait ; // input=>ex1_is_wait , act=>exx_act[1] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire ex2_priv_instr_q, ex1_priv_instr ; // input=>ex1_priv_instr , act=>exx_act[1] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire ex2_hypv_instr_q, ex1_hypv_instr ; // input=>ex1_hypv_instr , act=>exx_act[1] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire [9:10] ex2_wait_wc_q ; // input=>ex1_instr_q[9:10] , act=>exx_act[1] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire ex2_is_msgclr_q, ex1_is_msgclr ; // input=>ex1_is_msgclr , act=>exx_act[1] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire [11:20] ex2_instr_q, ex2_instr_d ; // input=>ex2_instr_d , act=>exx_act[1] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:0] ex2_msr_gs_q ; // input=>ex1_msr_gs_q , act=>1'b1 , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire ex2_tenc_we_q, ex1_tenc_we ; // input=>ex1_tenc_we , act=>exx_act[1] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire ex2_ccr0_we_q, ex1_ccr0_we ; // input=>ex1_ccr0_we , act=>exx_act[1] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire [2-`GPR_WIDTH/32:1] ex2_aspr_re_q, ex1_aspr_re ; // input=>ex1_aspr_re , act=>exx_act[1] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire ex2_dnh_q, ex1_dnh ; // input=>ex1_dnh , act=>exx_act[1] + wire [0:`THREADS-1] ex3_val_q, ex2_val ; // input=>ex2_val , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire ex3_val_rd_q, ex3_val_rd_d ; // input=>ex3_val_rd_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire ex3_sspr_wr_val_q, ex2_sspr_wr_val ; // input=>ex2_sspr_wr_val , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire ex3_sspr_rd_val_q, ex2_sspr_rd_val ; // input=>ex2_sspr_rd_val , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire ex3_spr_we_q, ex3_spr_we_d ; // input=>ex3_spr_we_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire ex3_aspr_we_q, ex3_aspr_we_d ; // input=>ex3_aspr_we_d , act=>exx_act[2] , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:3] ex3_aspr_addr_q, ex3_aspr_addr_d ; // input=>ex3_aspr_addr_d , act=>ex2_aspr_addr_act , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:1] ex3_tid_q ; // input=>ex2_tid_q , act=>exx_act[2] , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [64-`GPR_WIDTH:72-(64/`GPR_WIDTH)] ex3_aspr_rdata_q, ex3_aspr_rdata_d ; // input=>ex3_aspr_rdata_d , act=>exx_act_data[2], scan=>Y, sleep=>N, ring=>func, needs_sreset=>1, size=>`GPR_WIDTH+8 + wire ex3_is_mtspr_q ; // input=>ex2_is_mtspr_q , act=>exx_act[2] , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [9:10] ex3_wait_wc_q ; // input=>ex2_wait_wc_q , act=>exx_act[2] , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire ex3_is_msgclr_q ; // input=>ex2_is_msgclr_q , act=>exx_act[2] , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [11:20] ex3_instr_q, ex3_instr_d ; // input=>ex3_instr_d , act=>exx_act[2] , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [64-`GPR_WIDTH:63] ex3_cspr_rt_q, ex2_cspr_rt ; // input=>ex2_cspr_rt , act=>exx_act_data[2], scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire ex3_hypv_spr_q, ex3_hypv_spr_d ; // input=>ex3_hypv_spr_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire ex3_illeg_spr_q, ex3_illeg_spr_d ; // input=>ex3_illeg_spr_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire ex3_priv_spr_q, ex3_priv_spr_d ; // input=>ex3_priv_spr_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [64-`GPR_WIDTH:64+8-(64/`GPR_WIDTH)] ex3_rt_q, ex3_rt_d ; // input=>ex3_rt_d , act=>ex3_rt_act , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1, size=>`GPR_WIDTH+8 + wire ex3_wait_q ; // input=>ex2_is_wait_q , act=>exx_act[2] , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:3] ex3_aspr_ce_addr_q ; // input=>ex2_aspr_addr_q , act=>exx_act[2] , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [2-`GPR_WIDTH/32:1] ex3_aspr_re_q ; // input=>ex2_aspr_re_q , act=>exx_act[2] , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] ex4_val_q ; // input=>ex3_val , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [2-`GPR_WIDTH/32:1] ex4_aspr_re_q ; // input=>ex3_aspr_re_q , act=>exx_act[3] , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [64-`GPR_WIDTH:63] ex4_spr_rt_q, ex3_spr_rt ; // input=>ex3_spr_rt , act=>exx_act_data[3], scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [64-`GPR_WIDTH:63] ex4_corr_rdata_q, ex3_corr_rdata ; // input=>ex3_corr_rdata , act=>exx_act_data[3], scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:`GPR_WIDTH/8] ex4_sprg_ce_q, ex4_sprg_ce_d ; // input=>ex4_sprg_ce_d , act=>1'b1 , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:3] ex4_aspr_ce_addr_q ; // input=>ex3_aspr_ce_addr_q , act=>ex3_sprg_ce , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire ex4_hypv_spr_q ; // input=>ex3_hypv_spr_q , act=>exx_act[3] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire ex4_illeg_spr_q ; // input=>ex3_illeg_spr_q , act=>exx_act[3] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire ex4_priv_spr_q ; // input=>ex3_priv_spr_q , act=>exx_act[3] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire ex4_np1_flush_q, ex4_np1_flush_d ; // input=>ex4_np1_flush_d , act=>exx_act[3] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] ex5_sprg_ce_q, ex4_sprg_ce ; // input=>ex4_sprg_ce , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire ex4_sprg_ue_q, ex4_sprg_ue_d ; // input=>ex4_sprg_ue_d , act=>1'b1 , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] ex5_sprg_ue_q, ex4_sprg_ue ; // input=>ex4_sprg_ue , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] cpl_dbell_taken_q ; // input=>iu_xu_dbell_taken , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] cpl_cdbell_taken_q ; // input=>iu_xu_cdbell_taken , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] cpl_gdbell_taken_q ; // input=>iu_xu_gdbell_taken , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] cpl_gcdbell_taken_q ; // input=>iu_xu_gcdbell_taken , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] cpl_gmcdbell_taken_q ; // input=>iu_xu_gmcdbell_taken , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire set_xucr0_cslc_q, set_xucr0_cslc_d ; // input=>set_xucr0_cslc_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire set_xucr0_cul_q, set_xucr0_cul_d ; // input=>set_xucr0_cul_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire set_xucr0_clo_q, set_xucr0_clo_d ; // input=>set_xucr0_clo_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire ex3_np1_flush_q, ex3_np1_flush_d ; // input=>ex3_np1_flush_d , act=>exx_act[2] , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] running_q, running_d ; // input=>running_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] llpri_q, llpri_d ; // input=>llpri_d , act=>llpri_inc , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1, init=>2**(``THREADS-1) + wire [0:`THREADS-1] dec_dbg_dis_q, dec_dbg_dis_d ; // input=>dec_dbg_dis_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire tb_dbg_dis_q, tb_dbg_dis_d ; // input=>tb_dbg_dis_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire tb_act_q, tb_act_d ; // input=>tb_act_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] ext_dbg_dis_q, ext_dbg_dis_d ; // input=>ext_dbg_dis_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire msrovride_enab_q ; // input=>pc_xu_msrovride_enab , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] waitimpl_val_q, waitimpl_val_d ; // input=>waitimpl_val_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] waitrsv_val_q, waitrsv_val_d ; // input=>waitrsv_val_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] an_ac_reservation_vld_q ; // input=>an_ac_reservation_vld , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] an_ac_sleep_en_q ; // input=>an_ac_sleep_en , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [54:61] an_ac_coreid_q ; // input=>an_ac_coreid , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire tb_update_enable_q ; // input=>an_ac_tb_update_enable , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire tb_update_pulse_q ; // input=>an_ac_tb_update_pulse , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire tb_update_pulse_1_q ; // input=>tb_update_pulse_q , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire pc_xu_reset_wd_complete_q ; // input=>pc_xu_reset_wd_complete , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire pc_xu_reset_3_complete_q ; // input=>pc_xu_reset_3_complete , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire pc_xu_reset_2_complete_q ; // input=>pc_xu_reset_2_complete , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire pc_xu_reset_1_complete_q ; // input=>pc_xu_reset_1_complete , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire lq_xu_dbell_val_q ; // input=>lq_xu_dbell_val , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:4] lq_xu_dbell_type_q ; // input=>lq_xu_dbell_type , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire lq_xu_dbell_brdcast_q ; // input=>lq_xu_dbell_brdcast , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire lq_xu_dbell_lpid_match_q ; // input=>lq_xu_dbell_lpid_match , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [50:63] lq_xu_dbell_pirtag_q ; // input=>lq_xu_dbell_pirtag , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] dbell_present_q, dbell_present_d ; // input=>dbell_present_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] cdbell_present_q, cdbell_present_d ; // input=>cdbell_present_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] gdbell_present_q, gdbell_present_d ; // input=>gdbell_present_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] gcdbell_present_q, gcdbell_present_d ; // input=>gcdbell_present_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] gmcdbell_present_q, gmcdbell_present_d ; // input=>gmcdbell_present_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire xucr0_clfc_q, xucr0_clfc_d ; // input=>xucr0_clfc_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] iu_run_thread_q, iu_run_thread_d ; // input=>iu_run_thread_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] inj_sprg_ecc_q ; // input=>pc_xu_inj_sprg_ecc , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] dbell_interrupt_q, dbell_interrupt ; // input=>dbell_interrupt , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] cdbell_interrupt_q, cdbell_interrupt ; // input=>cdbell_interrupt , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] gdbell_interrupt_q, gdbell_interrupt ; // input=>gdbell_interrupt , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] gcdbell_interrupt_q, gcdbell_interrupt ; // input=>gcdbell_interrupt , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] gmcdbell_interrupt_q, gmcdbell_interrupt ; // input=>gmcdbell_interrupt , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] iu_quiesce_q ; // input=>iu_xu_quiesce , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] iu_icache_quiesce_q ; // input=>iu_xu_icache_quiesce , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] lsu_quiesce_q ; // input=>lq_xu_quiesce , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] mm_quiesce_q ; // input=>mm_xu_quiesce , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] bx_quiesce_q ; // input=>bx_xu_quiesce , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] quiesce_q, quiesce_d ; // input=>quiesce_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] quiesced_q, quiesced_d ; // input=>quiesced_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire instr_trace_mode_q ; // input=>pc_xu_instr_trace_mode , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:1] instr_trace_tid_q ; // input=>pc_xu_instr_trace_tid , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire timer_update_q ; // input=>timer_update_int , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire spr_xu_ord_read_done_q, spr_xu_ord_read_done_d ; // input=>spr_xu_ord_read_done_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire spr_xu_ord_write_done_q, spr_xu_ord_write_done_d ; // input=>spr_xu_ord_write_done_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire xu_spr_ord_ready_q ; // input=>xu_spr_ord_ready , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire ex4_sspr_val_q ; // input=>ex3_sspr_val , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] flush_q ; // input=>flush , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [62-`EFF_IFAR_WIDTH:61] ex1_ifar_q ; // input=>rv_xu_ex0_ifar , act=>exx_act[0] , scan=>Y, sleep=>N, needs_sreset=>1 + wire [62-`EFF_IFAR_WIDTH:61] ex2_ifar_q ; // input=>ex1_ifar_q , act=>exx_act[1] , scan=>Y, sleep=>N, needs_sreset=>1 + wire [0:`THREADS-1] ram_active_q ; // input=>pc_xu_ram_active , act=>1'b1 + wire [0:4] timer_div_q, timer_div_d ; // input=>timer_div_d , act=>timer_div_act , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] msrovride_enab_2_q, msrovride_enab ; // input=>msrovride_enab , act=>1'b1 + wire [0:`THREADS-1] msrovride_enab_3_q ; // input=>msrovride_enab_2_q , act=>1'b1 + wire ex3_wait_flush_q, ex3_wait_flush_d ; // input=>ex3_wait_flush_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire ex4_wait_flush_q, ex4_wait_flush_d ; // input=>ex4_wait_flush_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire pc_xu_pm_hold_thread_q ; // input=>pc_xu_pm_hold_thread , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire power_savings_on_q, power_savings_on_d ; // input=>power_savings_on_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:4*`THREADS-1] perf_event_bus_q, perf_event_bus_d ; // input=>perf_event_bus_d , act=>pc_xu_event_bus_enable , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] perf_event_en_q, perf_event_en_d ; // input=>perf_event_en_d , act=>pc_xu_event_bus_enable , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:15] spare_0_q, spare_0_d ; // input=>spare_0_d , act=>1'b1 , + // Scanchains + localparam exx_act_offset = last_reg_offset; + localparam ex0_val_offset = exx_act_offset + 4; + localparam ex1_val_offset = ex0_val_offset + `THREADS; + localparam ex1_aspr_act_offset = ex1_val_offset + `THREADS; + localparam ex1_aspr_tid_offset = ex1_aspr_act_offset + 1; + localparam ex1_tid_offset = ex1_aspr_tid_offset + 2; + localparam ex1_instr_offset = ex1_tid_offset + 2; + localparam ex1_msr_gs_offset = ex1_instr_offset + 32; + localparam ex2_val_offset = ex1_msr_gs_offset + 1; + localparam ex2_val_rd_offset = ex2_val_offset + `THREADS; + localparam ex2_val_wr_offset = ex2_val_rd_offset + 1; + localparam ex2_tid_offset = ex2_val_wr_offset + 1; + localparam ex2_aspr_addr_offset = ex2_tid_offset + 2; + localparam ex2_is_mfspr_offset = ex2_aspr_addr_offset + 4; + localparam ex2_is_mftb_offset = ex2_is_mfspr_offset + 1; + localparam ex2_is_mtmsr_offset = ex2_is_mftb_offset + 1; + localparam ex2_is_mtspr_offset = ex2_is_mtmsr_offset + 1; + localparam ex2_is_wait_offset = ex2_is_mtspr_offset + 1; + localparam ex2_priv_instr_offset = ex2_is_wait_offset + 1; + localparam ex2_hypv_instr_offset = ex2_priv_instr_offset + 1; + localparam ex2_wait_wc_offset = ex2_hypv_instr_offset + 1; + localparam ex2_is_msgclr_offset = ex2_wait_wc_offset + 2; + localparam ex2_instr_offset = ex2_is_msgclr_offset + 1; + localparam ex2_msr_gs_offset = ex2_instr_offset + 10; + localparam ex2_tenc_we_offset = ex2_msr_gs_offset + 1; + localparam ex2_ccr0_we_offset = ex2_tenc_we_offset + 1; + localparam ex2_aspr_re_offset = ex2_ccr0_we_offset + 1; + localparam ex2_dnh_offset = ex2_aspr_re_offset + `GPR_WIDTH/32; + localparam ex3_val_offset = ex2_dnh_offset + 1; + localparam ex3_val_rd_offset = ex3_val_offset + `THREADS; + localparam ex3_sspr_wr_val_offset = ex3_val_rd_offset + 1; + localparam ex3_sspr_rd_val_offset = ex3_sspr_wr_val_offset + 1; + localparam ex3_spr_we_offset = ex3_sspr_rd_val_offset + 1; + localparam ex3_aspr_we_offset = ex3_spr_we_offset + 1; + localparam ex3_aspr_addr_offset = ex3_aspr_we_offset + 1; + localparam ex3_tid_offset = ex3_aspr_addr_offset + 4; + localparam ex3_aspr_rdata_offset = ex3_tid_offset + 2; + localparam ex3_is_mtspr_offset = ex3_aspr_rdata_offset + `GPR_WIDTH+8; + localparam ex3_wait_wc_offset = ex3_is_mtspr_offset + 1; + localparam ex3_is_msgclr_offset = ex3_wait_wc_offset + 2; + localparam ex3_instr_offset = ex3_is_msgclr_offset + 1; + localparam ex3_cspr_rt_offset = ex3_instr_offset + 10; + localparam ex3_hypv_spr_offset = ex3_cspr_rt_offset + `GPR_WIDTH; + localparam ex3_illeg_spr_offset = ex3_hypv_spr_offset + 1; + localparam ex3_priv_spr_offset = ex3_illeg_spr_offset + 1; + localparam ex3_rt_offset = ex3_priv_spr_offset + 1; + localparam ex3_wait_offset = ex3_rt_offset + `GPR_WIDTH+8; + localparam ex3_aspr_ce_addr_offset = ex3_wait_offset + 1; + localparam ex3_aspr_re_offset = ex3_aspr_ce_addr_offset + 4; + localparam ex4_val_offset = ex3_aspr_re_offset + `GPR_WIDTH/32; + localparam ex4_aspr_re_offset = ex4_val_offset + `THREADS; + localparam ex4_spr_rt_offset = ex4_aspr_re_offset + `GPR_WIDTH/32; + localparam ex4_corr_rdata_offset = ex4_spr_rt_offset + `GPR_WIDTH; + localparam ex4_sprg_ce_offset = ex4_corr_rdata_offset + `GPR_WIDTH; + localparam ex4_aspr_ce_addr_offset = ex4_sprg_ce_offset + `GPR_WIDTH/8+1; + localparam ex4_hypv_spr_offset = ex4_aspr_ce_addr_offset + 4; + localparam ex4_illeg_spr_offset = ex4_hypv_spr_offset + 1; + localparam ex4_priv_spr_offset = ex4_illeg_spr_offset + 1; + localparam ex4_np1_flush_offset = ex4_priv_spr_offset + 1; + localparam ex5_sprg_ce_offset = ex4_np1_flush_offset + 1; + localparam ex4_sprg_ue_offset = ex5_sprg_ce_offset + `THREADS; + localparam ex5_sprg_ue_offset = ex4_sprg_ue_offset + 1; + localparam cpl_dbell_taken_offset = ex5_sprg_ue_offset + `THREADS; + localparam cpl_cdbell_taken_offset = cpl_dbell_taken_offset + `THREADS; + localparam cpl_gdbell_taken_offset = cpl_cdbell_taken_offset + `THREADS; + localparam cpl_gcdbell_taken_offset = cpl_gdbell_taken_offset + `THREADS; + localparam cpl_gmcdbell_taken_offset = cpl_gcdbell_taken_offset + `THREADS; + localparam set_xucr0_cslc_offset = cpl_gmcdbell_taken_offset + `THREADS; + localparam set_xucr0_cul_offset = set_xucr0_cslc_offset + 1; + localparam set_xucr0_clo_offset = set_xucr0_cul_offset + 1; + localparam ex3_np1_flush_offset = set_xucr0_clo_offset + 1; + localparam running_offset = ex3_np1_flush_offset + 1; + localparam llpri_offset = running_offset + `THREADS; + localparam dec_dbg_dis_offset = llpri_offset + `THREADS; + localparam tb_dbg_dis_offset = dec_dbg_dis_offset + `THREADS; + localparam tb_act_offset = tb_dbg_dis_offset + 1; + localparam ext_dbg_dis_offset = tb_act_offset + 1; + localparam msrovride_enab_offset = ext_dbg_dis_offset + `THREADS; + localparam waitimpl_val_offset = msrovride_enab_offset + 1; + localparam waitrsv_val_offset = waitimpl_val_offset + `THREADS; + localparam an_ac_reservation_vld_offset = waitrsv_val_offset + `THREADS; + localparam an_ac_sleep_en_offset = an_ac_reservation_vld_offset + `THREADS; + localparam an_ac_coreid_offset = an_ac_sleep_en_offset + `THREADS; + localparam tb_update_enable_offset = an_ac_coreid_offset + 8; + localparam tb_update_pulse_offset = tb_update_enable_offset + 1; + localparam tb_update_pulse_1_offset = tb_update_pulse_offset + 1; + localparam pc_xu_reset_wd_complete_offset = tb_update_pulse_1_offset + 1; + localparam pc_xu_reset_3_complete_offset = pc_xu_reset_wd_complete_offset + 1; + localparam pc_xu_reset_2_complete_offset = pc_xu_reset_3_complete_offset + 1; + localparam pc_xu_reset_1_complete_offset = pc_xu_reset_2_complete_offset + 1; + localparam lq_xu_dbell_val_offset = pc_xu_reset_1_complete_offset + 1; + localparam lq_xu_dbell_type_offset = lq_xu_dbell_val_offset + 1; + localparam lq_xu_dbell_brdcast_offset = lq_xu_dbell_type_offset + 5; + localparam lq_xu_dbell_lpid_match_offset = lq_xu_dbell_brdcast_offset + 1; + localparam lq_xu_dbell_pirtag_offset = lq_xu_dbell_lpid_match_offset + 1; + localparam dbell_present_offset = lq_xu_dbell_pirtag_offset + 14; + localparam cdbell_present_offset = dbell_present_offset + `THREADS; + localparam gdbell_present_offset = cdbell_present_offset + `THREADS; + localparam gcdbell_present_offset = gdbell_present_offset + `THREADS; + localparam gmcdbell_present_offset = gcdbell_present_offset + `THREADS; + localparam xucr0_clfc_offset = gmcdbell_present_offset + `THREADS; + localparam iu_run_thread_offset = xucr0_clfc_offset + 1; + localparam inj_sprg_ecc_offset = iu_run_thread_offset + `THREADS; + localparam dbell_interrupt_offset = inj_sprg_ecc_offset + `THREADS; + localparam cdbell_interrupt_offset = dbell_interrupt_offset + `THREADS; + localparam gdbell_interrupt_offset = cdbell_interrupt_offset + `THREADS; + localparam gcdbell_interrupt_offset = gdbell_interrupt_offset + `THREADS; + localparam gmcdbell_interrupt_offset = gcdbell_interrupt_offset + `THREADS; + localparam iu_quiesce_offset = gmcdbell_interrupt_offset + `THREADS; + localparam iu_icache_quiesce_offset = iu_quiesce_offset + `THREADS; + localparam lsu_quiesce_offset = iu_icache_quiesce_offset + `THREADS; + localparam mm_quiesce_offset = lsu_quiesce_offset + `THREADS; + localparam bx_quiesce_offset = mm_quiesce_offset + `THREADS; + localparam quiesce_offset = bx_quiesce_offset + `THREADS; + localparam quiesced_offset = quiesce_offset + `THREADS; + localparam instr_trace_mode_offset = quiesced_offset + `THREADS; + localparam instr_trace_tid_offset = instr_trace_mode_offset + 1; + localparam timer_update_offset = instr_trace_tid_offset + 2; + localparam spr_xu_ord_read_done_offset = timer_update_offset + 1; + localparam spr_xu_ord_write_done_offset = spr_xu_ord_read_done_offset + 1; + localparam xu_spr_ord_ready_offset = spr_xu_ord_write_done_offset + 1; + localparam ex4_sspr_val_offset = xu_spr_ord_ready_offset + 1; + localparam flush_offset = ex4_sspr_val_offset + 1; + localparam ex1_ifar_offset = flush_offset + `THREADS; + localparam ex2_ifar_offset = ex1_ifar_offset + `EFF_IFAR_WIDTH; + localparam ram_active_offset = ex2_ifar_offset + `EFF_IFAR_WIDTH; + localparam timer_div_offset = ram_active_offset + `THREADS; + localparam msrovride_enab_2_offset = timer_div_offset + 5; + localparam msrovride_enab_3_offset = msrovride_enab_2_offset + `THREADS; + localparam ex3_wait_flush_offset = msrovride_enab_3_offset + `THREADS; + localparam ex4_wait_flush_offset = ex3_wait_flush_offset + 1; + localparam pc_xu_pm_hold_thread_offset = ex4_wait_flush_offset + 1; + localparam power_savings_on_offset = pc_xu_pm_hold_thread_offset + 1; + localparam perf_event_bus_offset = power_savings_on_offset + 1; + localparam perf_event_en_offset = perf_event_bus_offset + 4*`THREADS; + localparam spare_0_offset = perf_event_en_offset + `THREADS; + localparam quiesced_ctr_offset = spare_0_offset + 16; + localparam scan_right = quiesced_ctr_offset + 1; + wire [0:scan_right-1] siv; + wire [0:scan_right-1] sov; + + + wire [0:`THREADS-1] ccr0_we_q, ccr0_we_d ; // input=>ccr0_we_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>bcfg, needs_sreset=>1 + localparam ccr0_we_offset_bcfg = last_reg_offset_bcfg; + localparam scan_right_bcfg = ccr0_we_offset_bcfg + `THREADS; + wire [0:scan_right_bcfg-1] siv_bcfg; + wire [0:scan_right_bcfg-1] sov_bcfg; + localparam scan_right_ccfg = last_reg_offset_ccfg; + wire [0:scan_right_ccfg-1] siv_ccfg; + wire [0:scan_right_ccfg-1] sov_ccfg; + localparam scan_right_dcfg = last_reg_offset_dcfg; + wire [0:scan_right_dcfg-1] siv_dcfg; + wire [0:scan_right_dcfg-1] sov_dcfg; + // Signals + wire [00:63] tidn; + wire [0:`NCLK_WIDTH-1] spare_0_lclk; + wire spare_0_d1clk; + wire spare_0_d2clk; + wire [00:63] tb; + wire ex1_opcode_is_31; + wire ex1_opcode_is_19; + wire ex1_is_mfcr; + wire ex1_is_mtcrf; + wire ex1_is_dnh; + wire ex1_is_mfmsr; + wire ex1_is_mtmsr; + wire ex3_sspr_val; + wire [0:`THREADS-1] ex2_tid; + wire ex2_illeg_mfspr; + wire ex2_illeg_mtspr; + wire ex2_illeg_mftb; + wire ex2_hypv_mfspr; + wire ex2_hypv_mtspr; + wire [11:20] ex1_instr; + wire [11:20] ex2_instr; + wire [11:20] ex3_instr; + wire ex2_slowspr_range_priv; + wire ex2_slowspr_range_hypv; + wire ex2_slowspr_range; + wire [0:`THREADS-1] ex2_wait_flush; + wire [0:`THREADS-1] ex2_ccr0_flush; + wire [0:`THREADS-1] ex2_tenc_flush; + wire [0:`THREADS-1] ex2_xucr0_flush; + wire [64-`GPR_WIDTH:63] ex3_tspr_rt; + wire [64-`GPR_WIDTH:63] ex3_cspr_rt; + wire [0:`THREADS-1] ex3_tid; + wire [64-`GPR_WIDTH:63] ex2_rt; + wire [64-`GPR_WIDTH:63] ex2_rt_inj; + wire llunmasked; + wire llmasked; + wire llpulse; + wire llpres; + wire llpri_inc; + wire [0:`THREADS-1] llmask; + wire [0:`THREADS-1] pm_wake_up; + wire [0:3] ccr0_we; + wire [0:`THREADS-1] ccr0_wen, ccr0_we_di; + wire dbell_pir_match; + wire [0:`THREADS-1] dbell_pir_thread; + wire [0:`THREADS-1] spr_ccr0_we_rev; + wire [0:`THREADS-1] spr_tens_ten_rev; + wire [0:`THREADS-1] set_dbell; + wire [0:`THREADS-1] clr_dbell; + wire [0:`THREADS-1] set_cdbell; + wire [0:`THREADS-1] clr_cdbell; + wire [0:`THREADS-1] set_gdbell; + wire [0:`THREADS-1] clr_gdbell; + wire [0:`THREADS-1] set_gcdbell; + wire [0:`THREADS-1] clr_gcdbell; + wire [0:`THREADS-1] set_gmcdbell; + wire [0:`THREADS-1] clr_gmcdbell; + wire tb_update_pulse; + wire [0:`THREADS-1] spr_tensr; + wire ex3_is_mtspr; + wire [0:63] tb_q; + wire [0:`THREADS-1] crit_mask; + wire [0:`THREADS-1] base_mask; + wire [0:`THREADS-1] dec_mask; + wire [0:`THREADS-1] fit_mask; + wire [0:`THREADS-1] ex3_wait; + wire [38:63] xucr0_di; + wire [64-`GPR_WIDTH:72-(64/`GPR_WIDTH)] ex2_eccgen_data; + wire [64:72-(64/`GPR_WIDTH)] ex2_eccgen_syn; + wire [64:72-(64/`GPR_WIDTH)] ex3_eccchk_syn; + wire [64:72-(64/`GPR_WIDTH)] ex3_eccchk_syn_b; + wire ex2_is_mfsspr_b; + wire encorr; + wire ex3_sprg_ce, ex3_sprg_ue; + wire ex2_aspr_we; + wire [64-`GPR_WIDTH:63] ex4_aspr_rt; + wire [0:`THREADS-1] quiesce_ctr_zero_b; + wire [0:`THREADS-1] quiesce_b_q; + wire [0:`THREADS-1] running; + wire timer_update_int; + wire [0:4] exx_act; + wire [1:3] exx_act_data; + wire ex0_act; + wire ex2_inj_ecc; + wire [32:47] version; + wire [48:63] revision; + wire [0:`THREADS-1] instr_trace_tid; + wire [0:`THREADS-1] ex3_val; + wire [0:3] ex2_aspr_addr; + wire ex1_spr_rd; + wire ex1_spr_wr; + wire flush_int; + wire ex2_flush; + wire ex3_flush; + wire ex1_valid; + wire ex1_is_wrtee; + wire ex1_is_wrteei; + wire ord_ready; + wire ex2_msr_pr; + wire ex2_msr_gs; + wire timer_div_act; + wire [0:4] timer_div; + wire ex3_spr_we; + wire ex2_aspr_addr_act; + wire ex3_rt_act; + wire [0:`THREADS-1] ex2_np1_flush; + wire power_savings_en, power_savings_on; + (* analysis_not_referenced="true" *) + wire unused_do_bits; + + // Data + wire [0:1] spr_ccr0_pme; + wire [0:3] spr_ccr0_we; + wire spr_ccr2_en_dcr_int; + wire spr_ccr2_en_pc; + wire spr_ccr4_en_dnh; + wire [0:`THREADS-1] spr_tens_ten; + wire [0:4] spr_xucr0_clkg_ctl; + wire spr_xucr0_tcs; + wire [0:1] spr_xucr4_tcd; + wire [62:63] ex3_ccr0_di; + wire [40:63] ex3_ccr1_di; + wire [32:63] ex3_ccr2_di; + wire [63:63] ex3_ccr4_di; + wire [32:63] ex3_tbl_di; + wire [32:63] ex3_tbu_di; + wire [64-(`THREADS):63] ex3_tens_di; + wire [32:63] ex3_xesr1_di; + wire [32:63] ex3_xesr2_di; + wire [38:63] ex3_xucr0_di; + wire [60:63] ex3_xucr4_di; + wire + ex1_gsprg0_re , ex1_gsprg1_re , ex1_gsprg2_re , ex1_gsprg3_re + , ex1_sprg0_re , ex1_sprg1_re , ex1_sprg2_re , ex1_sprg3_re + , ex1_sprg4_re , ex1_sprg5_re , ex1_sprg6_re , ex1_sprg7_re + , ex1_sprg8_re , ex1_vrsave_re ; + wire + ex1_gsprg0_rdec, ex1_gsprg1_rdec, ex1_gsprg2_rdec, ex1_gsprg3_rdec + , ex1_sprg0_rdec , ex1_sprg1_rdec , ex1_sprg2_rdec , ex1_sprg3_rdec + , ex1_sprg4_rdec , ex1_sprg5_rdec , ex1_sprg6_rdec , ex1_sprg7_rdec + , ex1_sprg8_rdec , ex1_vrsave_rdec; + wire ex2_sprg8_re; + wire + ex2_ccr0_re , ex2_ccr1_re , ex2_ccr2_re , ex2_ccr4_re + , ex2_cir_re , ex2_pir_re , ex2_pvr_re , ex2_tb_re + , ex2_tbu_re , ex2_tenc_re , ex2_tens_re , ex2_tensr_re + , ex2_tir_re , ex2_xesr1_re , ex2_xesr2_re , ex2_xucr0_re + , ex2_xucr4_re ; + wire + ex2_acop_re , ex2_axucr0_re , ex2_cpcr0_re , ex2_cpcr1_re + , ex2_cpcr2_re , ex2_cpcr3_re , ex2_cpcr4_re , ex2_cpcr5_re + , ex2_dac1_re , ex2_dac2_re , ex2_dac3_re , ex2_dac4_re + , ex2_dbcr2_re , ex2_dbcr3_re , ex2_dscr_re , ex2_dvc1_re + , ex2_dvc2_re , ex2_eheir_re , ex2_eplc_re , ex2_epsc_re + , ex2_eptcfg_re , ex2_givpr_re , ex2_hacop_re , ex2_iac1_re + , ex2_iac2_re , ex2_iac3_re , ex2_iac4_re , ex2_immr_re + , ex2_imr_re , ex2_iucr0_re , ex2_iucr1_re , ex2_iucr2_re + , ex2_iudbg0_re , ex2_iudbg1_re , ex2_iudbg2_re , ex2_iulfsr_re + , ex2_iullcr_re , ex2_ivpr_re , ex2_lesr1_re , ex2_lesr2_re + , ex2_lper_re , ex2_lperu_re , ex2_lpidr_re , ex2_lratcfg_re + , ex2_lratps_re , ex2_lsucr0_re , ex2_mas0_re , ex2_mas0_mas1_re + , ex2_mas1_re , ex2_mas2_re , ex2_mas2u_re , ex2_mas3_re + , ex2_mas4_re , ex2_mas5_re , ex2_mas5_mas6_re, ex2_mas6_re + , ex2_mas7_re , ex2_mas7_mas3_re, ex2_mas8_re , ex2_mas8_mas1_re + , ex2_mmucfg_re , ex2_mmucr0_re , ex2_mmucr1_re , ex2_mmucr2_re + , ex2_mmucr3_re , ex2_mmucsr0_re , ex2_pesr_re , ex2_pid_re + , ex2_ppr32_re , ex2_sramd_re , ex2_tlb0cfg_re , ex2_tlb0ps_re + , ex2_xucr2_re , ex2_xudbg0_re , ex2_xudbg1_re , ex2_xudbg2_re ; + wire + ex2_ccr0_we , ex2_ccr1_we , ex2_ccr2_we , ex2_ccr4_we + , ex2_tbl_we , ex2_tbu_we , ex2_tenc_we , ex2_tens_we + , ex2_trace_we , ex2_xesr1_we , ex2_xesr2_we , ex2_xucr0_we + , ex2_xucr4_we ; + wire + ex2_acop_we , ex2_axucr0_we , ex2_cpcr0_we , ex2_cpcr1_we + , ex2_cpcr2_we , ex2_cpcr3_we , ex2_cpcr4_we , ex2_cpcr5_we + , ex2_dac1_we , ex2_dac2_we , ex2_dac3_we , ex2_dac4_we + , ex2_dbcr2_we , ex2_dbcr3_we , ex2_dscr_we , ex2_dvc1_we + , ex2_dvc2_we , ex2_eheir_we , ex2_eplc_we , ex2_epsc_we + , ex2_givpr_we , ex2_hacop_we , ex2_iac1_we , ex2_iac2_we + , ex2_iac3_we , ex2_iac4_we , ex2_immr_we , ex2_imr_we + , ex2_iucr0_we , ex2_iucr1_we , ex2_iucr2_we , ex2_iudbg0_we + , ex2_iulfsr_we , ex2_iullcr_we , ex2_ivpr_we , ex2_lesr1_we + , ex2_lesr2_we , ex2_lper_we , ex2_lperu_we , ex2_lpidr_we + , ex2_lsucr0_we , ex2_mas0_we , ex2_mas0_mas1_we, ex2_mas1_we + , ex2_mas2_we , ex2_mas2u_we , ex2_mas3_we , ex2_mas4_we + , ex2_mas5_we , ex2_mas5_mas6_we, ex2_mas6_we , ex2_mas7_we + , ex2_mas7_mas3_we, ex2_mas8_we , ex2_mas8_mas1_we, ex2_mmucr0_we + , ex2_mmucr1_we , ex2_mmucr2_we , ex2_mmucr3_we , ex2_mmucsr0_we + , ex2_pesr_we , ex2_pid_we , ex2_ppr32_we , ex2_xucr2_we + , ex2_xudbg0_we ; + wire + ex2_gsprg0_we , ex2_gsprg1_we , ex2_gsprg2_we , ex2_gsprg3_we + , ex2_sprg0_we , ex2_sprg1_we , ex2_sprg2_we , ex2_sprg3_we + , ex2_sprg4_we , ex2_sprg5_we , ex2_sprg6_we , ex2_sprg7_we + , ex2_sprg8_we , ex2_vrsave_we ; + wire + ex2_ccr0_rdec , ex2_ccr1_rdec , ex2_ccr2_rdec , ex2_ccr4_rdec + , ex2_cir_rdec , ex2_pir_rdec , ex2_pvr_rdec , ex2_tb_rdec + , ex2_tbu_rdec , ex2_tenc_rdec , ex2_tens_rdec , ex2_tensr_rdec + , ex2_tir_rdec , ex2_xesr1_rdec , ex2_xesr2_rdec , ex2_xucr0_rdec + , ex2_xucr4_rdec ; + wire + ex2_acop_rdec , ex2_axucr0_rdec, ex2_cpcr0_rdec , ex2_cpcr1_rdec + , ex2_cpcr2_rdec , ex2_cpcr3_rdec , ex2_cpcr4_rdec , ex2_cpcr5_rdec + , ex2_dac1_rdec , ex2_dac2_rdec , ex2_dac3_rdec , ex2_dac4_rdec + , ex2_dbcr2_rdec , ex2_dbcr3_rdec , ex2_dscr_rdec , ex2_dvc1_rdec + , ex2_dvc2_rdec , ex2_eheir_rdec , ex2_eplc_rdec , ex2_epsc_rdec + , ex2_eptcfg_rdec, ex2_givpr_rdec , ex2_hacop_rdec , ex2_iac1_rdec + , ex2_iac2_rdec , ex2_iac3_rdec , ex2_iac4_rdec , ex2_immr_rdec + , ex2_imr_rdec , ex2_iucr0_rdec , ex2_iucr1_rdec , ex2_iucr2_rdec + , ex2_iudbg0_rdec, ex2_iudbg1_rdec, ex2_iudbg2_rdec, ex2_iulfsr_rdec + , ex2_iullcr_rdec, ex2_ivpr_rdec , ex2_lesr1_rdec , ex2_lesr2_rdec + , ex2_lper_rdec , ex2_lperu_rdec , ex2_lpidr_rdec , ex2_lratcfg_rdec + , ex2_lratps_rdec, ex2_lsucr0_rdec, ex2_mas0_rdec , ex2_mas0_mas1_rdec + , ex2_mas1_rdec , ex2_mas2_rdec , ex2_mas2u_rdec , ex2_mas3_rdec + , ex2_mas4_rdec , ex2_mas5_rdec , ex2_mas5_mas6_rdec, ex2_mas6_rdec + , ex2_mas7_rdec , ex2_mas7_mas3_rdec, ex2_mas8_rdec , ex2_mas8_mas1_rdec + , ex2_mmucfg_rdec, ex2_mmucr0_rdec, ex2_mmucr1_rdec, ex2_mmucr2_rdec + , ex2_mmucr3_rdec, ex2_mmucsr0_rdec, ex2_pesr_rdec , ex2_pid_rdec + , ex2_ppr32_rdec , ex2_sramd_rdec , ex2_tlb0cfg_rdec, ex2_tlb0ps_rdec + , ex2_xucr2_rdec , ex2_xudbg0_rdec, ex2_xudbg1_rdec, ex2_xudbg2_rdec; + wire + ex2_gsprg0_rdec, ex2_gsprg1_rdec, ex2_gsprg2_rdec, ex2_gsprg3_rdec + , ex2_sprg0_rdec , ex2_sprg1_rdec , ex2_sprg2_rdec , ex2_sprg3_rdec + , ex2_sprg4_rdec , ex2_sprg5_rdec , ex2_sprg6_rdec , ex2_sprg7_rdec + , ex2_sprg8_rdec , ex2_vrsave_rdec; + wire + ex2_ccr0_wdec , ex2_ccr1_wdec , ex2_ccr2_wdec , ex2_ccr4_wdec + , ex2_tbl_wdec , ex2_tbu_wdec , ex2_tenc_wdec , ex2_tens_wdec + , ex2_trace_wdec , ex2_xesr1_wdec , ex2_xesr2_wdec , ex2_xucr0_wdec + , ex2_xucr4_wdec ; + wire + ex2_gsprg0_wdec, ex2_gsprg1_wdec, ex2_gsprg2_wdec, ex2_gsprg3_wdec + , ex2_sprg0_wdec , ex2_sprg1_wdec , ex2_sprg2_wdec , ex2_sprg3_wdec + , ex2_sprg4_wdec , ex2_sprg5_wdec , ex2_sprg6_wdec , ex2_sprg7_wdec + , ex2_sprg8_wdec , ex2_vrsave_wdec; + wire + ex2_acop_wdec , ex2_axucr0_wdec, ex2_cpcr0_wdec , ex2_cpcr1_wdec + , ex2_cpcr2_wdec , ex2_cpcr3_wdec , ex2_cpcr4_wdec , ex2_cpcr5_wdec + , ex2_dac1_wdec , ex2_dac2_wdec , ex2_dac3_wdec , ex2_dac4_wdec + , ex2_dbcr2_wdec , ex2_dbcr3_wdec , ex2_dscr_wdec , ex2_dvc1_wdec + , ex2_dvc2_wdec , ex2_eheir_wdec , ex2_eplc_wdec , ex2_epsc_wdec + , ex2_givpr_wdec , ex2_hacop_wdec , ex2_iac1_wdec , ex2_iac2_wdec + , ex2_iac3_wdec , ex2_iac4_wdec , ex2_immr_wdec , ex2_imr_wdec + , ex2_iucr0_wdec , ex2_iucr1_wdec , ex2_iucr2_wdec , ex2_iudbg0_wdec + , ex2_iulfsr_wdec, ex2_iullcr_wdec, ex2_ivpr_wdec , ex2_lesr1_wdec + , ex2_lesr2_wdec , ex2_lper_wdec , ex2_lperu_wdec , ex2_lpidr_wdec + , ex2_lsucr0_wdec, ex2_mas0_wdec , ex2_mas0_mas1_wdec, ex2_mas1_wdec + , ex2_mas2_wdec , ex2_mas2u_wdec , ex2_mas3_wdec , ex2_mas4_wdec + , ex2_mas5_wdec , ex2_mas5_mas6_wdec, ex2_mas6_wdec , ex2_mas7_wdec + , ex2_mas7_mas3_wdec, ex2_mas8_wdec , ex2_mas8_mas1_wdec, ex2_mmucr0_wdec + , ex2_mmucr1_wdec, ex2_mmucr2_wdec, ex2_mmucr3_wdec, ex2_mmucsr0_wdec + , ex2_pesr_wdec , ex2_pid_wdec , ex2_ppr32_wdec , ex2_xucr2_wdec + , ex2_xudbg0_wdec; + wire + ex3_ccr0_we , ex3_ccr1_we , ex3_ccr2_we , ex3_ccr4_we + , ex3_tbl_we , ex3_tbu_we , ex3_tenc_we , ex3_tens_we + , ex3_xesr1_we , ex3_xesr2_we , ex3_xucr0_we , ex3_xucr4_we ; + wire + ex3_ccr0_wdec , ex3_ccr1_wdec , ex3_ccr2_wdec , ex3_ccr4_wdec + , ex3_tbl_wdec , ex3_tbu_wdec , ex3_tenc_wdec , ex3_tens_wdec + , ex3_xesr1_wdec , ex3_xesr2_wdec , ex3_xucr0_wdec , ex3_xucr4_wdec ; + wire + ccr0_act , ccr1_act , ccr2_act , ccr4_act + , cir_act , pir_act , pvr_act , tb_act + , tbl_act , tbu_act , tenc_act , tens_act + , tensr_act , tir_act , xesr1_act , xesr2_act + , xucr0_act , xucr4_act ; + wire [0:64] + ccr0_do , ccr1_do , ccr2_do , ccr4_do + , cir_do , pir_do , pvr_do , tb_do + , tbl_do , tbu_do , tenc_do , tens_do + , tensr_do , tir_do , xesr1_do , xesr2_do + , xucr0_do , xucr4_do ; + + + wire [64-`GPR_WIDTH:64+8-(64/`GPR_WIDTH)] ex3_spr_wd; + + wire xu_iu_ex3_sprg_ce, xu_iu_ex3_sprg_ue; + assign xu_iu_ex3_sprg_ce = 1'b0; + assign xu_iu_ex3_sprg_ue = 1'b0; + + //!! Bugspray Include: xu_spr_cspr; + //## figtree_source: xu_spr_cspr.fig; + + assign tidn = {64{1'b0}}; + + assign cspr_xucr0_clkg_ctl = spr_xucr0_clkg_ctl; + + assign ex1_aspr_act_d = ex0_act; + + assign ex0_act = |ex0_val_q & rv_xu_ex0_ord; + assign exx_act_d[1:4] = exx_act[0:3]; + + assign exx_act[0] = ex0_act; + assign exx_act[1] = exx_act_q[1]; + assign exx_act[2] = exx_act_q[2]; + assign exx_act[3] = exx_act_q[3] | ex3_spr_we_q; + assign exx_act[4] = exx_act_q[4]; + + // Needs to be on for loads and stores, for the DEAR... + assign exx_act_data[1] = exx_act[1]; + assign exx_act_data[2] = exx_act[2]; + assign exx_act_data[3] = exx_act[3]; + + assign cspr_tspr_rf1_act = exx_act[0]; + + // Decode + assign ex1_opcode_is_19 = ex1_instr_q[0:5] == 6'b010011; + assign ex1_opcode_is_31 = ex1_instr_q[0:5] == 6'b011111; + assign ex1_is_mfspr = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0101010011); // 31/339 + assign ex1_is_mtspr = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0111010011); // 31/467 + assign ex1_is_mfmsr = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0001010011); // 31/083 + assign ex1_is_mtmsr = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0010010010); // 31/146 + assign ex1_is_mftb = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0101110011); // 31/371 + assign ex1_is_wait = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0000111110); // 31/062 + assign ex1_is_msgclr = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0011101110); // 31/238 + assign ex1_is_wrtee = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0010000011); // 31/131 + assign ex1_is_wrteei = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0010100011); // 31/163 + assign ex1_is_mfcr = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0000010011); // 31/19 + assign ex1_is_mtcrf = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0010010000); // 31/144 + assign ex1_is_dnh = (ex1_opcode_is_19 & ex1_instr_q[21:30] == 10'b0011000110); // 19/198 + + assign ex1_priv_instr = ex1_is_mtmsr | ex1_is_mfmsr | ex1_is_wrtee | ex1_is_wrteei | ex1_is_msgclr; + + assign ex1_hypv_instr = ex1_is_msgclr; + + assign ex1_spr_rd = ex1_is_mfspr | ex1_is_mfmsr | ex1_is_mftb; + assign ex1_spr_wr = ex1_is_mtspr | ex1_is_mtmsr | ex1_is_wrtee | + ex1_is_wrteei | ex1_is_msgclr | ex1_is_wait | ex1_is_dnh; + + assign ex2_is_mtmsr_d = ex1_is_mtmsr | ex1_is_wrtee | ex1_is_wrteei; + + assign rv2_val = rv_xu_vld & (~flush_q); + assign ex0_val = ex0_val_q & (~flush_q) & {`THREADS{rv_xu_ex0_ord}}; + assign ex1_val = ex1_val_q & (~flush_q); + assign ex2_val = ex2_val_q & (~flush_q); + assign ex3_val = ex3_val_q & (~flush_q); + + assign ex1_valid = |(ex1_val); + + assign ex2_flush = |(ex2_tid & flush_q) & (ex2_val_rd_q | ex2_val_wr_q); + assign ex3_flush = |(ex3_tid & flush_q) & (ex3_val_rd_q | ex2_val_wr_q); + + // For CPCRs wait until quiesce + + wire ord_quiesce = &lsu_quiesce_q | ~(ex2_is_mtspr_q & (ex2_cpcr0_wdec | ex2_cpcr1_wdec | ex2_cpcr2_wdec | ex2_cpcr3_wdec | ex2_cpcr4_wdec | ex2_cpcr5_wdec)) | ex2_is_wait_q; + + // On exception, do not wait for ord_ready. No write will occur. + assign ord_ready = xu_spr_ord_ready_q | flush_int; + + assign flush_int = ex3_hypv_spr_q | ex3_illeg_spr_q | ex3_priv_spr_q; + + assign ex2_val_rd_d = ((ex1_valid & ex1_spr_rd) | ex2_val_rd_q) & ~ex2_flush & ~ex2_val_rd_q; + assign ex2_val_wr_d = ((ex1_valid & ex1_spr_wr) | (ex2_val_wr_q & ~ex2_flush & ~(ord_ready & ord_quiesce))); + + assign ex3_val_rd_d = ex2_val_rd_q & ~ex2_flush; + + assign ex3_spr_we_d = ex2_val_wr_q & ~ex2_flush & ord_ready & ord_quiesce; + assign ex3_spr_we = ex3_spr_we_q & ~flush_int; + assign cspr_tspr_ex3_spr_we = ex3_tid & {`THREADS{ex3_spr_we}}; + + assign ex3_sspr_val = ((ex3_spr_we & ex3_sspr_wr_val_q) | (ex3_val_rd_q & ex3_sspr_rd_val_q)) & (~(ex3_flush | flush_int)); + + assign spr_xu_ord_read_done_d = ex3_spr_we_q & (~ex3_sspr_wr_val_q | flush_int) & ~ex3_flush; + assign spr_xu_ord_write_done_d = ex3_val_rd_q & (~ex3_sspr_rd_val_q | flush_int) & ~ex3_flush; + + assign spr_xu_ord_write_done = spr_xu_ord_write_done_q & ~ex3_flush; + assign spr_xu_ord_read_done = spr_xu_ord_read_done_q & ~ex3_flush; + + assign ex1_instr = ex1_instr_q[11:20]; + assign ex2_instr_d = ex1_instr_q[11:20] & {10{(ex1_is_mfspr | ex1_is_mtspr | ex1_is_wrteei | ex1_is_mftb)}}; + assign ex2_instr = ex2_instr_q[11:20]; + assign ex3_instr_d = ex2_instr_q; // or gate(ex2_dcrn_q,ex2_dcr_val_q); + assign ex3_instr = ex3_instr_q[11:20]; + assign ex3_spr_wd = ex3_rt_q; + assign ex3_spr_wd_out = ex3_rt_q; + assign ex3_is_mtspr = ex3_is_mtspr_q; + assign ex2_ifar = ex2_ifar_q; + + assign ex3_wait = ex3_tid & {`THREADS{(ex3_spr_we & ex3_wait_q & ex3_wait_flush_q)}}; + + assign spr_tens_ten_rev = reverse_threads(spr_tens_ten); + assign spr_tensr = spr_tens_ten | reverse_threads(running); + assign spr_ccr0_we_rev = reverse_threads(spr_ccr0_we[4-`THREADS:3]); + +// Run State +assign quiesce_b_q = ~(quiesce_q & ~running_q); +assign quiesce_d = iu_quiesce_q & iu_icache_quiesce_q & lsu_quiesce_q & mm_quiesce_q & bx_quiesce_q; + +assign quiesced_d = quiesce_q & ~quiesce_ctr_zero_b; + +assign xu_pc_running = running; + +assign running = running_q | ~quiesced_q; +assign running_d = ~(iu_xu_stop | spr_ccr0_we_rev) & spr_tens_ten_rev; +assign iu_run_thread_d = (running_q & llmask) & ~{`THREADS{power_savings_on}}; +assign xu_iu_run_thread = iu_run_thread_q; + +assign ex1_tenc_we = (ex1_instr_q[11:20] == 10'b1011101101); // 439 +assign ex1_ccr0_we = (ex1_instr_q[11:20] == 10'b1000011111); // 1008 + +// Power Management Control +assign xu_pc_spr_ccr0_we = spr_ccr0_we_rev & quiesced_q; +assign xu_pc_spr_ccr0_pme = spr_ccr0_pme; + +assign power_savings_on = (power_savings_en | power_savings_on_q); + +assign power_savings_on_d = power_savings_on & ~(~pc_xu_pm_hold_thread & pc_xu_pm_hold_thread_q); + +assign power_savings_en = ^spr_ccr0_pme & // Power Management Enabled + &spr_ccr0_we_rev & // Wait Enable = 1 + &quiesced_q; // Core Quiesced + +// Wakeup Condition Masking + +// Reset the mask when running +// Set the mask on a valid wait instruction +// Otherwise hold + +// WAIT[WC](0) = Resume on Imp. Specific +// WAIT[WC](1) = Resume on no reservation +generate + begin : pm_wake_up_gen + genvar t; + for (t=0;t<=`THREADS-1;t=t+1) + begin : thread + assign waitimpl_val_d[t] = (ex3_wait[t] == 1'b1) ? ex3_wait_wc_q[9] : + (pm_wake_up[t] == 1'b1) ? 1'b0 : + waitimpl_val_q[t]; + + assign waitrsv_val_d[t] = (ex3_wait[t] == 1'b1) ? ex3_wait_wc_q[10] : + (pm_wake_up[t] == 1'b1) ? 1'b0 : + waitrsv_val_q[t]; + + // Block interrupts (mask=0) if: + // Stopped via (HW Debug and pc_xu_extirpts_dis_on_stop)=1 + // Stopped via TEN=0 + // Stopped via CCR0=1, unless overriden by CCR1=1 (and wait, if applicable) + assign crit_mask[t] = (~(ext_dbg_dis_q[t] | ~spr_tens_ten_rev[t] | (spr_ccr0_we_rev[t] & ~ccr1_q[60-6*t]))); + assign base_mask[t] = (~(ext_dbg_dis_q[t] | ~spr_tens_ten_rev[t] | (spr_ccr0_we_rev[t] & ~ccr1_q[61-6*t]))); + assign dec_mask[t] = (~(ext_dbg_dis_q[t] | ~spr_tens_ten_rev[t] | (spr_ccr0_we_rev[t] & ~ccr1_q[62-6*t]))); + assign fit_mask[t] = (~(ext_dbg_dis_q[t] | ~spr_tens_ten_rev[t] | (spr_ccr0_we_rev[t] & ~ccr1_q[63-6*t]))); + + assign cspr_tspr_crit_mask[t] = crit_mask[t]; + assign cspr_tspr_ext_mask[t] = base_mask[t]; + assign cspr_tspr_dec_mask[t] = dec_mask[t]; + assign cspr_tspr_fit_mask[t] = fit_mask[t]; + assign cspr_tspr_wdog_mask[t] = crit_mask[t]; + assign cspr_tspr_udec_mask[t] = dec_mask[t]; + assign cspr_tspr_perf_mask[t] = base_mask[t]; + + // Generate Conditional Wait flush + // Reservation Exists + assign ex2_wait_flush[t] = ex2_tid[t] & ex2_is_wait_q & // Unconditional Wait + ((ex2_wait_wc_q == 2'b00) | (ex2_wait_wc_q == 2'b01 & an_ac_reservation_vld_q[t] & (~ccr1_q[58-6*t])) | // Reservation Exists + (ex2_wait_wc_q == 2'b10 & an_ac_sleep_en_q[t] & (~ccr1_q[59-6*t]))); // Impl. Specific Exists (Sleep enabled) + + + assign ex2_ccr0_flush[t] = ex2_is_mtspr_q & ex2_ccr0_we_q & xu_spr_ex2_rs1[55-t] & xu_spr_ex2_rs1[63-t]; + + assign ex2_tenc_flush[t] = ex2_is_mtspr_q & ex2_tenc_we_q & xu_spr_ex2_rs1[63-t]; + + assign ex2_xucr0_flush[t] = ex2_is_mtspr_q & ex2_xucr0_wdec; + end + end + endgenerate + + assign cspr_tspr_sleep_mask = ~power_savings_on_q; + + assign pm_wake_up = (~an_ac_reservation_vld_q & waitrsv_val_q) | + (~an_ac_sleep_en_q & waitimpl_val_q) | + tspr_cspr_pm_wake_up | + dbell_interrupt_q | + cdbell_interrupt_q | + gdbell_interrupt_q | + gcdbell_interrupt_q | + gmcdbell_interrupt_q; + + // Debug Timer Disable + assign tb_dbg_dis_d = &iu_xu_stop & pc_xu_timebase_dis_on_stop; + assign dec_dbg_dis_d = iu_xu_stop & {`THREADS{pc_xu_decrem_dis_on_stop}}; + assign ext_dbg_dis_d = iu_xu_stop & {`THREADS{pc_xu_extirpts_dis_on_stop}}; + + // LiveLock Priority + assign cspr_tspr_llen = running_q; + assign cspr_tspr_llpri = llpri_q; + assign llpres = |(tspr_cspr_lldet); + assign llunmasked = |( llpri_q & tspr_cspr_lldet); + assign llmasked = |(~llpri_q & tspr_cspr_lldet); + assign llpulse = |( llpri_q & tspr_cspr_llpulse); + + // Increment the hang priority if: + // There is a hang present, but the priority is masking it. + // There is another hang present, and there is a hang pulse. + assign llpri_inc = (llpres & (~llunmasked)) | (llpulse & llmasked & llunmasked); + + generate + if (`THREADS == 1) + begin : tid1 + assign llpri_d = 1'b1; + assign ex0_tid = 2'b00; + assign ex2_tid = 1'b1; + assign ex3_tid = 1'b1; + assign instr_trace_tid = 1'b1; + end + endgenerate + generate + if (`THREADS == 2) + begin : tid2 + assign llpri_d = {llpri_q[`THREADS - 1], llpri_q[0:`THREADS - 2]}; + assign ex0_tid = {1'b0, ex0_val_q[1]}; + assign ex2_tid[0] = ~ex2_tid_q[0] & ~ex2_tid_q[1]; + assign ex2_tid[1] = ~ex2_tid_q[0] & ex2_tid_q[1]; + assign ex3_tid[0] = ~ex3_tid_q[0] & ~ex3_tid_q[1]; + assign ex3_tid[1] = ~ex3_tid_q[0] & ex3_tid_q[1]; + assign instr_trace_tid[0] = ~instr_trace_tid_q[0] & ~instr_trace_tid_q[1]; + assign instr_trace_tid[1] = ~instr_trace_tid_q[0] & instr_trace_tid_q[1]; + end + endgenerate + +assign llmask = (llpri_q & tspr_cspr_lldet) | ~{`THREADS{llpres}}; + +assign instr_trace_mode = instr_trace_tid & {`THREADS{instr_trace_mode_q}}; + +assign ex1_msr_gs_d = {1{|(tspr_msr_gs & ex0_val_q)}}; + +assign cspr_tspr_ram_active = ram_active_q; + +assign cspr_tspr_msrovride_en = msrovride_enab; +assign msrovride_enab = ram_active_q & {`THREADS{msrovride_enab_q}}; + +assign xu_iu_msrovride_enab = msrovride_enab_2_q | msrovride_enab_3_q; + +// Perf Events + +assign perf_event_en_d = ( tspr_msr_pr & {`THREADS{pc_xu_event_count_mode[0]}}) | // User + (~tspr_msr_pr & tspr_msr_gs & {`THREADS{pc_xu_event_count_mode[1]}}) | // Guest Supervisor + (~tspr_msr_pr & ~tspr_msr_gs & {`THREADS{pc_xu_event_count_mode[2]}}) ; // Hypervisor + + +wire [0:16*`THREADS-1] perf_events; +wire [0:0] core_event; + generate + begin : perf_count + genvar t; + for (t = 0; t <= `THREADS - 1; t = t + 1) + begin : thread + assign core_event = perf_event_en_q[t] & running[t]; + + assign perf_events[0+16*t] = core_event[0]; + assign perf_events[1+16*t] = perf_event_en_q[t] & running[t]; + assign perf_events[2+16*t] = perf_event_en_q[t] & tb_act_q; + assign perf_events[3+16*t] = perf_event_en_q[t] & waitrsv_val_q[t]; + assign perf_events[4+16*t] = perf_event_en_q[t] & tspr_cspr_async_int[0+3*t]; + assign perf_events[5+16*t] = perf_event_en_q[t] & tspr_cspr_async_int[1+3*t]; + assign perf_events[6+16*t] = perf_event_en_q[t] & tspr_cspr_async_int[2+3*t]; + assign perf_events[7+16*t] = perf_event_en_q[t] & (cpl_dbell_taken_q[t] | cpl_cdbell_taken_q[t] | cpl_gdbell_taken_q[t] | cpl_gcdbell_taken_q[t] | cpl_gmcdbell_taken_q[t]); + assign perf_events[8+16*t] = perf_event_en_q[t] & div_spr_running[t]; + assign perf_events[9+16*t] = perf_event_en_q[t] & mul_spr_running[t]; + assign perf_events[10+16*t:15+16*t] = 6'd0; + + tri_event_mux1t #(.EVENTS_IN(16),.EVENTS_OUT(4)) perf_mux ( + .unit_events_in(perf_events[1+16*t:15+16*t]), + .select_bits(xesr1_q[32+16*t:47+16*t]), + .event_bus_out(perf_event_bus_d[0+4*t:3+4*t]), + .event_bus_in(xu_event_bus_in[0+4*t:3+4*t]), + .vd(vdd),.gd(gnd)); + + end + end + endgenerate + assign xu_event_bus_out = perf_event_bus_q; + assign spr_xesr1 = xesr1_q; + assign spr_xesr2 = xesr2_q; + assign perf_event_en = perf_event_en_q; + + // SPR Input Control + // CIR + assign cir_act = 1'b0; + + // CCR0 + // CCR0[PME] + assign ccr0_act = ex3_ccr0_we; + assign ccr0_d = ex3_ccr0_di; + + // CCR0[WE] + // Generate Bit Mask + assign ccr0_wen = ex3_spr_wd[56-`THREADS:55] & {`THREADS{ex3_ccr0_we}}; + // Apply bit-Mask + assign ccr0_we_di = (ex3_spr_wd[64-`THREADS:63] & ccr0_wen[0:`THREADS-1]) | (ccr0_we_q[0:`THREADS-1] & (~ccr0_wen[0:`THREADS-1])); + // Update based upon wake-up + assign ccr0_we_d = (ccr0_we_di[0:`THREADS-1] | reverse_threads(ex3_wait[0:`THREADS-1])) & ~(reverse_threads(pm_wake_up[0:`THREADS-1])); + // Padded version + assign ccr0_we = {{4-`THREADS{1'b0}},ccr0_we_q}; + + + // CCR1 + assign ccr1_act = ex3_ccr1_we; + assign ccr1_d = ex3_ccr1_di; + + // CCR2 + assign ccr2_act = ex3_ccr2_we; + assign ccr2_d = ex3_ccr2_di; + + // CCR4 + assign ccr4_act = ex3_ccr4_we; + assign ccr4_d = ex3_ccr4_di; + + // PIR + assign pir_act = 1'b1; + + // PVR + assign pvr_act = 1'b1; + + assign version = {8'h00, spr_pvr_version_dc[8:15]}; + assign revision = {4'h0, spr_pvr_revision_dc[12:15], 4'h0, spr_pvr_revision_minor_dc[16:19]}; + + // TB + assign tb_update_pulse = (tb_update_pulse_q ^ tb_update_pulse_1_q); // Any Edge + + // Update on external signal selected by XUCR0[TCS] + assign timer_div_act = tb_update_enable_q & (tb_update_pulse | (~spr_xucr0_tcs)); + + assign timer_div_d = timer_div_q + 5'd1; + + assign timer_div = (timer_div_q ^ timer_div_d) & {5{timer_div_act}}; + + // Select timer clock divide + + assign timer_update_int = (spr_xucr4_tcd == 2'b00) ? timer_div[4] : + (spr_xucr4_tcd == 2'b01) ? timer_div[2] : + (spr_xucr4_tcd == 2'b10) ? timer_div[1] : + timer_div[0]; + assign timer_update = timer_update_q; + + // Not Stopped via HW DBG (if enabled) + assign tb_act_d = ~tb_dbg_dis_q & ~|tspr_cspr_freeze_timers & timer_update_int; // Timers not frozen due to debug event + + assign tb_act = tb_act_q; + assign tb_q = {tbu_q, tbl_q}; + assign tb = tb_q + 1; + + // TBL + assign tbl_act = tb_act | ex3_tbl_we; + assign tbl_d = (ex3_tbl_we == 1'b1) ? ex3_tbl_di : tb[32:63]; + + // TBU + assign tbu_act = tb_act | ex3_tbu_we; + assign tbu_d = (ex3_tbu_we == 1'b1) ? ex3_tbu_di : tb[0:31]; + + // TENC + assign tenc_act = 1'b1; + + // TENS + assign tens_act = ex3_tenc_we | ex3_tens_we; + assign tens_d = (ex3_tenc_we == 1'b1) ? (tens_q & ~ex3_tens_di) : (tens_q | ex3_tens_di); + + // TENSR + assign tensr_act = 1'b1; + + // TIR + assign tir_act = 1'b1; + + // XESR1 + assign xesr1_act = ex3_xesr1_we; + assign xesr1_d = ex3_xesr1_di; + + // XESR2 + assign xesr2_act = ex3_xesr2_we; + assign xesr2_d = ex3_xesr2_di; + + // XUCR0 + assign set_xucr0_cslc_d = lq_xu_spr_xucr0_cslc_xuop | lq_xu_spr_xucr0_cslc_binv; + assign set_xucr0_cul_d = lq_xu_spr_xucr0_cul; + assign set_xucr0_clo_d = lq_xu_spr_xucr0_clo; + + assign xucr0_act = ex3_xucr0_we | set_xucr0_cslc_q | set_xucr0_cul_q | set_xucr0_clo_q; + + assign xucr0_d = {xucr0_di[38:60], + (xucr0_di[61] | set_xucr0_cslc_q), + (xucr0_di[62] | set_xucr0_cul_q), + (xucr0_di[63] | set_xucr0_clo_q)}; + + assign xucr0_di = (ex3_xucr0_we == 1'b1) ? ex3_xucr0_di : xucr0_q; + + // XUCR4 + assign xucr4_act = ex3_xucr4_we; + assign xucr4_d = ex3_xucr4_di; + + // IO signal assignments + + // FIT LL WDOG + assign cspr_tspr_timebase_taps[8] = tbl_q[32 + 23]; // 9 x + assign cspr_tspr_timebase_taps[7] = tbl_q[32 + 11]; // 21 x + assign cspr_tspr_timebase_taps[6] = tbl_q[32 + 7]; // 25 x + assign cspr_tspr_timebase_taps[5] = tbl_q[32 + 21]; // 11 x x + assign cspr_tspr_timebase_taps[4] = tbl_q[32 + 17]; // 15 x x + assign cspr_tspr_timebase_taps[3] = tbl_q[32 + 13]; // 19 x x x + assign cspr_tspr_timebase_taps[2] = tbl_q[32 + 9]; // 23 x x x + assign cspr_tspr_timebase_taps[1] = tbl_q[32 + 5]; // 27 x x + assign cspr_tspr_timebase_taps[0] = tbl_q[32 + 1]; // 31 x + assign cspr_tspr_timebase_taps[9] = tbl_q[32 + 7]; // 29 x -- Replaced 1 for wdog + + assign cspr_tspr_ex2_tid = ex2_tid; + assign cspr_tspr_ex1_instr = ex1_instr_q; + assign cspr_tspr_dec_dbg_dis = dec_dbg_dis_q; + + assign reset_wd_complete = pc_xu_reset_wd_complete_q; + assign reset_3_complete = pc_xu_reset_3_complete_q; + assign reset_2_complete = pc_xu_reset_2_complete_q; + assign reset_1_complete = pc_xu_reset_1_complete_q; + + assign ex1_aspr_tid_d = ex0_tid; + + assign cspr_aspr_ex3_we = (ex3_spr_we & ex3_aspr_we_q) | |ex5_sprg_ce_q; + assign cspr_aspr_ex3_waddr = {ex3_aspr_addr_q, ex3_tid_q}; + assign cspr_aspr_ex1_re = ex1_aspr_re[1] & ex1_aspr_act_q; + assign cspr_aspr_ex1_raddr = {ex1_aspr_addr, ex1_aspr_tid_q}; + + assign xu_slowspr_val_out = ex4_sspr_val_q; + assign xu_slowspr_rw_out = (~ex3_is_mtspr_q); + assign xu_slowspr_etid_out = ex3_tid_q; + assign xu_slowspr_addr_out = {ex3_instr_q[16:20], ex3_instr_q[11:15]}; + assign xu_slowspr_data_out = ex3_spr_wd[64 - `GPR_WIDTH:63]; + + assign ac_an_dcr_act = 1'b0; + assign ac_an_dcr_val = 1'b0; + assign ac_an_dcr_read = 1'b0; + assign ac_an_dcr_user = 1'b0; + assign ac_an_dcr_etid = {2{1'b0}}; + assign ac_an_dcr_addr = {10{1'b0}}; + assign ac_an_dcr_data = {`GPR_WIDTH{1'b0}}; + + assign spr_dec_ex4_spr_hypv = ex4_hypv_spr_q; + assign spr_dec_ex4_spr_illeg = ex4_illeg_spr_q; + assign spr_dec_ex4_spr_priv = ex4_priv_spr_q; + assign spr_dec_ex4_np1_flush = ex4_np1_flush_q | ex4_wait_flush_q | (|ex4_sprg_ue); + + assign dbell_pir_match = (lq_xu_dbell_pirtag_q[50:61] == pir_do[51:62]); + + assign cspr_tspr_dbell_pirtag = lq_xu_dbell_pirtag_q; + + generate + begin : dbell + genvar t; + for (t=0;t<=`THREADS-1;t=t+1) + begin : thread + wire [0:1] tid = t; + + assign dbell_pir_thread[t] = lq_xu_dbell_pirtag_q[62:63] == tid; + + assign set_dbell[t] = lq_xu_dbell_val_q & lq_xu_dbell_type_q == 5'b00000 & lq_xu_dbell_lpid_match_q & (lq_xu_dbell_brdcast_q | (dbell_pir_match & dbell_pir_thread[t])); + assign set_cdbell[t] = lq_xu_dbell_val_q & lq_xu_dbell_type_q == 5'b00001 & lq_xu_dbell_lpid_match_q & (lq_xu_dbell_brdcast_q | (dbell_pir_match & dbell_pir_thread[t])); + assign set_gdbell[t] = lq_xu_dbell_val_q & lq_xu_dbell_type_q == 5'b00010 & lq_xu_dbell_lpid_match_q & (lq_xu_dbell_brdcast_q | tspr_cspr_gpir_match[t]); + assign set_gcdbell[t] = lq_xu_dbell_val_q & lq_xu_dbell_type_q == 5'b00011 & lq_xu_dbell_lpid_match_q & (lq_xu_dbell_brdcast_q | tspr_cspr_gpir_match[t]); + assign set_gmcdbell[t] = lq_xu_dbell_val_q & lq_xu_dbell_type_q == 5'b00100 & lq_xu_dbell_lpid_match_q & (lq_xu_dbell_brdcast_q | tspr_cspr_gpir_match[t]); + + assign clr_dbell[t] = ex3_spr_we & ex3_tid[t] & ex3_is_msgclr_q & (ex3_spr_wd[32:36] == 5'b00000); + assign clr_cdbell[t] = ex3_spr_we & ex3_tid[t] & ex3_is_msgclr_q & (ex3_spr_wd[32:36] == 5'b00001); + assign clr_gdbell[t] = ex3_spr_we & ex3_tid[t] & ex3_is_msgclr_q & (ex3_spr_wd[32:36] == 5'b00010); + assign clr_gcdbell[t] = ex3_spr_we & ex3_tid[t] & ex3_is_msgclr_q & (ex3_spr_wd[32:36] == 5'b00011); + assign clr_gmcdbell[t] = ex3_spr_we & ex3_tid[t] & ex3_is_msgclr_q & (ex3_spr_wd[32:36] == 5'b00100); + end + end + endgenerate + + assign dbell_present_d = set_dbell | (dbell_present_q & ~(clr_dbell | cpl_dbell_taken_q)); + assign cdbell_present_d = set_cdbell | (cdbell_present_q & ~(clr_cdbell | cpl_cdbell_taken_q)); + assign gdbell_present_d = set_gdbell | (gdbell_present_q & ~(clr_gdbell | cpl_gdbell_taken_q)); + assign gcdbell_present_d = set_gcdbell | (gcdbell_present_q & ~(clr_gcdbell | cpl_gcdbell_taken_q)); + assign gmcdbell_present_d = set_gmcdbell | (gmcdbell_present_q & ~(clr_gmcdbell | cpl_gmcdbell_taken_q)); + + assign dbell_interrupt = dbell_present_q & base_mask & (tspr_msr_ee | tspr_msr_gs); + assign cdbell_interrupt = cdbell_present_q & crit_mask & (tspr_msr_ce | tspr_msr_gs); + assign gdbell_interrupt = gdbell_present_q & base_mask & tspr_msr_ee & tspr_msr_gs; + assign gcdbell_interrupt = gcdbell_present_q & crit_mask & tspr_msr_ce & tspr_msr_gs; + assign gmcdbell_interrupt = gmcdbell_present_q & crit_mask & tspr_msr_me & tspr_msr_gs; + + assign xu_iu_dbell_interrupt = ~{`THREADS{power_savings_on_q}} & dbell_interrupt_q; + assign xu_iu_cdbell_interrupt = ~{`THREADS{power_savings_on_q}} & cdbell_interrupt_q; + assign xu_iu_gdbell_interrupt = ~{`THREADS{power_savings_on_q}} & gdbell_interrupt_q; + assign xu_iu_gcdbell_interrupt = ~{`THREADS{power_savings_on_q}} & gcdbell_interrupt_q; + assign xu_iu_gmcdbell_interrupt = ~{`THREADS{power_savings_on_q}} & gmcdbell_interrupt_q; + + // Debug + assign cspr_debug0 = {40{1'b0}}; + assign cspr_debug1 = {64{1'b0}}; + + // Array ECC Check + + assign ex3_aspr_rdata_d[64-`GPR_WIDTH] = aspr_cspr_ex2_rdata[64-`GPR_WIDTH]; + assign ex3_aspr_rdata_d[65-`GPR_WIDTH:72-(64/`GPR_WIDTH)] = aspr_cspr_ex2_rdata[65-`GPR_WIDTH:72-(64/`GPR_WIDTH)]; + + assign ex3_eccchk_syn_b = ~ex3_eccchk_syn; + + + tri_eccgen #(.REGSIZE(`GPR_WIDTH)) xu_spr_rd_eccgen( + .din(ex3_aspr_rdata_q), + .syn(ex3_eccchk_syn) + ); + + + tri_eccchk #(.REGSIZE(`GPR_WIDTH)) xu_spr_eccchk( + .din(ex3_aspr_rdata_q[64-`GPR_WIDTH:63]), + .encorr(encorr), + .nsyn(ex3_eccchk_syn_b), + .corrd(ex3_corr_rdata), + .sbe(ex3_sprg_ce), + .ue(ex3_sprg_ue) + ); + + assign encorr = 1'b1; + + assign ex4_sprg_ue_d = (|ex3_val_rd_q & |ex3_aspr_re_q & ex3_sprg_ue); + + assign ex4_sprg_ce_d = {`GPR_WIDTH/8+1{(|ex3_val_rd_q & |ex3_aspr_re_q & ex3_sprg_ce)}}; + + + tri_direct_err_rpt #(.WIDTH(`THREADS)) xu_spr_cspr_ce_err_rpt( + .vd(vdd), + .gd(gnd), + .err_in(ex5_sprg_ce_q), + .err_out(xu_pc_err_sprg_ecc) + ); + + tri_direct_err_rpt #(.WIDTH(`THREADS)) xu_spr_cspr_ue_err_rpt( + .vd(vdd), + .gd(gnd), + .err_in(ex5_sprg_ue_q), + .err_out(xu_pc_err_sprg_ue) + ); + + assign ex4_aspr_rt[32:63] = ex4_corr_rdata_q[32:63] & {32{ex4_aspr_re_q[1]}}; + generate + if (`GPR_WIDTH > 32) + begin : aspr_rt + assign ex4_aspr_rt[64-`GPR_WIDTH:31] = ex4_corr_rdata_q[64-`GPR_WIDTH:31] & {`GPR_WIDTH-32{ex4_aspr_re_q[0]}}; + end + endgenerate + + `ifdef THREADS1 + assign ex3_tspr_rt = tspr_cspr_ex3_tspr_rt; + `else + assign ex3_tspr_rt = tspr_cspr_ex3_tspr_rt[0:`GPR_WIDTH-1] | tspr_cspr_ex3_tspr_rt[`GPR_WIDTH:2*`GPR_WIDTH-1]; + `endif + + assign ex3_cspr_rt = ex3_cspr_rt_q & {`GPR_WIDTH{(~((ex3_sspr_wr_val_q | ex3_sspr_rd_val_q)))}}; + + assign ex3_spr_rt = ex3_tspr_rt | ex3_cspr_rt; + + assign spr_xu_ex4_rd_data = ex4_spr_rt_q | ex4_aspr_rt; + + // Fast SPR Read + generate + if (a2mode == 0 & hvmode == 0) + begin : readmux_00 + assign ex2_cspr_rt = + (ccr0_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr0_re }}) | + (ccr1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr1_re }}) | + (ccr2_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr2_re }}) | + (ccr4_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr4_re }}) | + (cir_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_cir_re }}) | + (pir_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_pir_re }}) | + (pvr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_pvr_re }}) | + (tb_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tb_re }}) | + (tbu_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tbu_re }}) | + (tenc_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tenc_re }}) | + (tens_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tens_re }}) | + (tensr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tensr_re }}) | + (tir_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tir_re }}) | + (xesr1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xesr1_re }}) | + (xesr2_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xesr2_re }}) | + (xucr0_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xucr0_re }}) | + (xucr4_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xucr4_re }}); + end + endgenerate + generate + if (a2mode == 0 & hvmode == 1) + begin : readmux_01 + assign ex2_cspr_rt = + (ccr0_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr0_re }}) | + (ccr1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr1_re }}) | + (ccr2_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr2_re }}) | + (ccr4_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr4_re }}) | + (cir_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_cir_re }}) | + (pir_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_pir_re }}) | + (pvr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_pvr_re }}) | + (tb_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tb_re }}) | + (tbu_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tbu_re }}) | + (tenc_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tenc_re }}) | + (tens_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tens_re }}) | + (tensr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tensr_re }}) | + (tir_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tir_re }}) | + (xesr1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xesr1_re }}) | + (xesr2_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xesr2_re }}) | + (xucr0_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xucr0_re }}) | + (xucr4_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xucr4_re }}); + end + endgenerate + generate + if (a2mode == 1 & hvmode == 0) + begin : readmux_10 + assign ex2_cspr_rt = + (ccr0_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr0_re }}) | + (ccr1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr1_re }}) | + (ccr2_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr2_re }}) | + (ccr4_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr4_re }}) | + (cir_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_cir_re }}) | + (pir_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_pir_re }}) | + (pvr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_pvr_re }}) | + (tb_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tb_re }}) | + (tbu_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tbu_re }}) | + (tenc_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tenc_re }}) | + (tens_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tens_re }}) | + (tensr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tensr_re }}) | + (tir_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tir_re }}) | + (xesr1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xesr1_re }}) | + (xesr2_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xesr2_re }}) | + (xucr0_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xucr0_re }}) | + (xucr4_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xucr4_re }}); + end + endgenerate + generate + if (a2mode == 1 & hvmode == 1) + begin : readmux_11 + assign ex2_cspr_rt = + (ccr0_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr0_re }}) | + (ccr1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr1_re }}) | + (ccr2_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr2_re }}) | + (ccr4_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr4_re }}) | + (cir_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_cir_re }}) | + (pir_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_pir_re }}) | + (pvr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_pvr_re }}) | + (tb_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tb_re }}) | + (tbu_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tbu_re }}) | + (tenc_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tenc_re }}) | + (tens_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tens_re }}) | + (tensr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tensr_re }}) | + (tir_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tir_re }}) | + (xesr1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xesr1_re }}) | + (xesr2_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xesr2_re }}) | + (xucr0_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xucr0_re }}) | + (xucr4_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xucr4_re }}); + end + endgenerate + + // Fast SPR Write + assign ex3_ccr0_wdec = (ex3_instr[11:20] == 10'b1000011111); // 1008 + assign ex3_ccr1_wdec = (ex3_instr[11:20] == 10'b1000111111); // 1009 + assign ex3_ccr2_wdec = (ex3_instr[11:20] == 10'b1001011111); // 1010 + assign ex3_ccr4_wdec = (ex3_instr[11:20] == 10'b1011011010); // 854 + assign ex3_tbl_wdec = (ex3_instr[11:20] == 10'b1110001000); // 284 + assign ex3_tbu_wdec = ((ex3_instr[11:20] == 10'b1110101000)); // 285 + assign ex3_tenc_wdec = (ex3_instr[11:20] == 10'b1011101101); // 439 + assign ex3_tens_wdec = (ex3_instr[11:20] == 10'b1011001101); // 438 + assign ex3_xesr1_wdec = (ex3_instr[11:20] == 10'b1011011100); // 918 + assign ex3_xesr2_wdec = (ex3_instr[11:20] == 10'b1011111100); // 919 + assign ex3_xucr0_wdec = (ex3_instr[11:20] == 10'b1011011111); // 1014 + assign ex3_xucr4_wdec = (ex3_instr[11:20] == 10'b1010111010); // 853 + assign ex3_ccr0_we = ex3_spr_we & ex3_is_mtspr & ex3_ccr0_wdec; + assign ex3_ccr1_we = ex3_spr_we & ex3_is_mtspr & ex3_ccr1_wdec; + assign ex3_ccr2_we = ex3_spr_we & ex3_is_mtspr & ex3_ccr2_wdec; + assign ex3_ccr4_we = ex3_spr_we & ex3_is_mtspr & ex3_ccr4_wdec; + assign ex3_tbl_we = ex3_spr_we & ex3_is_mtspr & ex3_tbl_wdec; + assign ex3_tbu_we = ex3_spr_we & ex3_is_mtspr & ex3_tbu_wdec; + assign ex3_tenc_we = ex3_spr_we & ex3_is_mtspr & ex3_tenc_wdec; + assign ex3_tens_we = ex3_spr_we & ex3_is_mtspr & ex3_tens_wdec; + assign ex3_xesr1_we = ex3_spr_we & ex3_is_mtspr & ex3_xesr1_wdec; + assign ex3_xesr2_we = ex3_spr_we & ex3_is_mtspr & ex3_xesr2_wdec; + assign ex3_xucr0_we = ex3_spr_we & ex3_is_mtspr & ex3_xucr0_wdec; + assign ex3_xucr4_we = ex3_spr_we & ex3_is_mtspr & ex3_xucr4_wdec; + + // Array Read + assign ex1_gsprg0_rdec = (ex1_instr[11:20] == 10'b1000001011); // 368 + assign ex1_gsprg1_rdec = (ex1_instr[11:20] == 10'b1000101011); // 369 + assign ex1_gsprg2_rdec = (ex1_instr[11:20] == 10'b1001001011); // 370 + assign ex1_gsprg3_rdec = (ex1_instr[11:20] == 10'b1001101011); // 371 + assign ex1_sprg0_rdec = (ex1_instr[11:20] == 10'b1000001000); // 272 + assign ex1_sprg1_rdec = (ex1_instr[11:20] == 10'b1000101000); // 273 + assign ex1_sprg2_rdec = (ex1_instr[11:20] == 10'b1001001000); // 274 + assign ex1_sprg3_rdec = ((ex1_instr[11:20] == 10'b1001101000) | // 275 + (ex1_instr[11:20] == 10'b0001101000)); // 259 + assign ex1_sprg4_rdec = ((ex1_instr[11:20] == 10'b1010001000) | // 276 + (ex1_instr[11:20] == 10'b0010001000)); // 260 + assign ex1_sprg5_rdec = ((ex1_instr[11:20] == 10'b1010101000) | // 277 + (ex1_instr[11:20] == 10'b0010101000)); // 261 + assign ex1_sprg6_rdec = ((ex1_instr[11:20] == 10'b1011001000) | // 278 + (ex1_instr[11:20] == 10'b0011001000)); // 262 + assign ex1_sprg7_rdec = ((ex1_instr[11:20] == 10'b1011101000) | // 279 + (ex1_instr[11:20] == 10'b0011101000)); // 263 + assign ex1_sprg8_rdec = (ex1_instr[11:20] == 10'b1110010010); // 604 + assign ex1_vrsave_rdec = (ex1_instr[11:20] == 10'b0000001000); // 256 + assign ex1_gsprg0_re = (ex1_gsprg0_rdec | (ex1_sprg0_rdec & ex1_msr_gs_q[0])); + assign ex1_gsprg1_re = (ex1_gsprg1_rdec | (ex1_sprg1_rdec & ex1_msr_gs_q[0])); + assign ex1_gsprg2_re = (ex1_gsprg2_rdec | (ex1_sprg2_rdec & ex1_msr_gs_q[0])); + assign ex1_gsprg3_re = (ex1_gsprg3_rdec | (ex1_sprg3_rdec & ex1_msr_gs_q[0])); + assign ex1_sprg0_re = ex1_sprg0_rdec & ~ex1_msr_gs_q[0]; + assign ex1_sprg1_re = ex1_sprg1_rdec & ~ex1_msr_gs_q[0]; + assign ex1_sprg2_re = ex1_sprg2_rdec & ~ex1_msr_gs_q[0]; + assign ex1_sprg3_re = ex1_sprg3_rdec & ~ex1_msr_gs_q[0]; + assign ex1_sprg4_re = ex1_sprg4_rdec; + assign ex1_sprg5_re = ex1_sprg5_rdec; + assign ex1_sprg6_re = ex1_sprg6_rdec; + assign ex1_sprg7_re = ex1_sprg7_rdec; + assign ex1_sprg8_re = ex1_sprg8_rdec; + assign ex1_vrsave_re = ex1_vrsave_rdec; + + assign ex1_aspr_re[1] = ex1_is_mfspr & ( + ex1_gsprg0_re | ex1_gsprg1_re | ex1_gsprg2_re + | ex1_gsprg3_re | ex1_sprg0_re | ex1_sprg1_re + | ex1_sprg2_re | ex1_sprg3_re | ex1_sprg4_re + | ex1_sprg5_re | ex1_sprg6_re | ex1_sprg7_re + | ex1_sprg8_re | ex1_vrsave_re ); + + generate + if (`GPR_WIDTH > 32) + begin : ex1_aspr_re0_gen + assign ex1_aspr_re[0] = ex1_aspr_re[1] & ~( + ex1_vrsave_re ); + end + endgenerate + + assign ex1_aspr_addr = + (4'b0000 & {4{ex1_gsprg0_re }}) | + (4'b0001 & {4{ex1_gsprg1_re }}) | + (4'b0010 & {4{ex1_gsprg2_re }}) | + (4'b0011 & {4{ex1_gsprg3_re }}) | + (4'b0100 & {4{ex1_sprg0_re }}) | + (4'b0101 & {4{ex1_sprg1_re }}) | + (4'b0110 & {4{ex1_sprg2_re }}) | + (4'b0111 & {4{ex1_sprg3_re }}) | + (4'b1000 & {4{ex1_sprg4_re }}) | + (4'b1001 & {4{ex1_sprg5_re }}) | + (4'b1010 & {4{ex1_sprg6_re }}) | + (4'b1011 & {4{ex1_sprg7_re }}) | + (4'b1100 & {4{ex1_sprg8_re }}) | + (4'b1101 & {4{ex1_vrsave_re }}); + + + // Array Writes + + // Generate ECC + assign ex2_inj_ecc = |(inj_sprg_ecc_q & ex2_tid) & ~ex4_sprg_ce_q[0]; + + assign ex3_aspr_addr_d = (ex4_sprg_ce_q[`GPR_WIDTH/8] == 1'b1) ? ex4_aspr_ce_addr_q : ex2_aspr_addr; + + + generate + genvar i; + for (i=0; i<`GPR_WIDTH; i=i+1) begin : ex2_rt_gen + assign ex2_rt[i] = (ex4_corr_rdata_q[i] & ex4_sprg_ce_q[i % (`GPR_WIDTH/8)]) | + (xu_spr_ex2_rs1[i] & ~ex4_sprg_ce_q[i % (`GPR_WIDTH/8)]) ; + end + endgenerate + + assign ex2_rt_inj[63] = ex2_rt[63] ^ ex2_inj_ecc; + assign ex2_rt_inj[64-`GPR_WIDTH:62] = ex2_rt[64 - `GPR_WIDTH:62]; + + assign ex2_eccgen_data = {ex2_rt, tidn[0:8 - (64/`GPR_WIDTH)]}; + + + tri_eccgen #(.REGSIZE(`GPR_WIDTH)) xu_spr_wr_eccgen( + .din(ex2_eccgen_data), + .syn(ex2_eccgen_syn) + ); + + assign ex2_is_mfsspr_b = ~ex2_sspr_rd_val; + + assign ex2_aspr_addr_act = exx_act_data[2] | ex4_sprg_ce_q[0]; + + assign ex3_rt_act = exx_act_data[2] | ex4_sprg_ce_q[0]; + assign ex3_rt_d = {(ex2_rt_inj & {`GPR_WIDTH{ex2_is_mfsspr_b}}), ex2_eccgen_syn}; + + assign ex4_sprg_ue = ex4_val_q & {`THREADS{ex4_sprg_ue_q}}; + assign ex4_sprg_ce = ex4_val_q & {`THREADS{ex4_sprg_ce_q[0]}}; + assign ex3_aspr_we_d = |(ex2_val) & ex2_aspr_we; + + assign ex2_aspr_we = ex2_is_mtspr_q & ( + ex2_gsprg0_we | ex2_gsprg1_we | ex2_gsprg2_we + | ex2_gsprg3_we | ex2_sprg0_we | ex2_sprg1_we + | ex2_sprg2_we | ex2_sprg3_we | ex2_sprg4_we + | ex2_sprg5_we | ex2_sprg6_we | ex2_sprg7_we + | ex2_sprg8_we | ex2_vrsave_we ); + + assign ex2_gsprg0_wdec = (ex2_instr[11:20] == 10'b1000001011); // 368 + assign ex2_gsprg1_wdec = (ex2_instr[11:20] == 10'b1000101011); // 369 + assign ex2_gsprg2_wdec = (ex2_instr[11:20] == 10'b1001001011); // 370 + assign ex2_gsprg3_wdec = (ex2_instr[11:20] == 10'b1001101011); // 371 + assign ex2_sprg0_wdec = (ex2_instr[11:20] == 10'b1000001000); // 272 + assign ex2_sprg1_wdec = (ex2_instr[11:20] == 10'b1000101000); // 273 + assign ex2_sprg2_wdec = (ex2_instr[11:20] == 10'b1001001000); // 274 + assign ex2_sprg3_wdec = ((ex2_instr[11:20] == 10'b1001101000)); // 275 + assign ex2_sprg4_wdec = ((ex2_instr[11:20] == 10'b1010001000)); // 276 + assign ex2_sprg5_wdec = ((ex2_instr[11:20] == 10'b1010101000)); // 277 + assign ex2_sprg6_wdec = ((ex2_instr[11:20] == 10'b1011001000)); // 278 + assign ex2_sprg7_wdec = ((ex2_instr[11:20] == 10'b1011101000)); // 279 + assign ex2_sprg8_wdec = (ex2_instr[11:20] == 10'b1110010010); // 604 + assign ex2_vrsave_wdec = (ex2_instr[11:20] == 10'b0000001000); // 256 + assign ex2_gsprg0_we = (ex2_gsprg0_wdec | (ex2_sprg0_wdec & ex2_msr_gs_q[0])); + assign ex2_gsprg1_we = (ex2_gsprg1_wdec | (ex2_sprg1_wdec & ex2_msr_gs_q[0])); + assign ex2_gsprg2_we = (ex2_gsprg2_wdec | (ex2_sprg2_wdec & ex2_msr_gs_q[0])); + assign ex2_gsprg3_we = (ex2_gsprg3_wdec | (ex2_sprg3_wdec & ex2_msr_gs_q[0])); + assign ex2_sprg0_we = ex2_sprg0_wdec & ~ex2_msr_gs_q[0]; + assign ex2_sprg1_we = ex2_sprg1_wdec & ~ex2_msr_gs_q[0]; + assign ex2_sprg2_we = ex2_sprg2_wdec & ~ex2_msr_gs_q[0]; + assign ex2_sprg3_we = ex2_sprg3_wdec & ~ex2_msr_gs_q[0]; + assign ex2_sprg4_we = ex2_sprg4_wdec; + assign ex2_sprg5_we = ex2_sprg5_wdec; + assign ex2_sprg6_we = ex2_sprg6_wdec; + assign ex2_sprg7_we = ex2_sprg7_wdec; + assign ex2_sprg8_we = ex2_sprg8_wdec; + assign ex2_vrsave_we = ex2_vrsave_wdec; + + assign ex2_aspr_addr = + (4'b0000 & {4{ex2_gsprg0_we }}) | + (4'b0001 & {4{ex2_gsprg1_we }}) | + (4'b0010 & {4{ex2_gsprg2_we }}) | + (4'b0011 & {4{ex2_gsprg3_we }}) | + (4'b0100 & {4{ex2_sprg0_we }}) | + (4'b0101 & {4{ex2_sprg1_we }}) | + (4'b0110 & {4{ex2_sprg2_we }}) | + (4'b0111 & {4{ex2_sprg3_we }}) | + (4'b1000 & {4{ex2_sprg4_we }}) | + (4'b1001 & {4{ex2_sprg5_we }}) | + (4'b1010 & {4{ex2_sprg6_we }}) | + (4'b1011 & {4{ex2_sprg7_we }}) | + (4'b1100 & {4{ex2_sprg8_we }}) | + (4'b1101 & {4{ex2_vrsave_we }}); + + // Slow SPR + assign ex2_acop_rdec = (ex2_instr[11:20] == 10'b1111100000); // 31 + assign ex2_axucr0_rdec = (ex2_instr[11:20] == 10'b1000011110); // 976 + assign ex2_cpcr0_rdec = (ex2_instr[11:20] == 10'b1000011001); // 816 + assign ex2_cpcr1_rdec = (ex2_instr[11:20] == 10'b1000111001); // 817 + assign ex2_cpcr2_rdec = (ex2_instr[11:20] == 10'b1001011001); // 818 + assign ex2_cpcr3_rdec = (ex2_instr[11:20] == 10'b1010011001); // 820 + assign ex2_cpcr4_rdec = (ex2_instr[11:20] == 10'b1010111001); // 821 + assign ex2_cpcr5_rdec = (ex2_instr[11:20] == 10'b1011011001); // 822 + assign ex2_dac1_rdec = (ex2_instr[11:20] == 10'b1110001001); // 316 + assign ex2_dac2_rdec = (ex2_instr[11:20] == 10'b1110101001); // 317 + assign ex2_dac3_rdec = (ex2_instr[11:20] == 10'b1000111010); // 849 + assign ex2_dac4_rdec = (ex2_instr[11:20] == 10'b1001011010); // 850 + assign ex2_dbcr2_rdec = (ex2_instr[11:20] == 10'b1011001001); // 310 + assign ex2_dbcr3_rdec = (ex2_instr[11:20] == 10'b1000011010); // 848 + assign ex2_dscr_rdec = (ex2_instr[11:20] == 10'b1000100000); // 17 + assign ex2_dvc1_rdec = (ex2_instr[11:20] == 10'b1111001001); // 318 + assign ex2_dvc2_rdec = (ex2_instr[11:20] == 10'b1111101001); // 319 + assign ex2_eheir_rdec = (ex2_instr[11:20] == 10'b1010000001); // 52 + assign ex2_eplc_rdec = (ex2_instr[11:20] == 10'b1001111101); // 947 + assign ex2_epsc_rdec = (ex2_instr[11:20] == 10'b1010011101); // 948 + assign ex2_eptcfg_rdec = (ex2_instr[11:20] == 10'b1111001010); // 350 + assign ex2_givpr_rdec = (ex2_instr[11:20] == 10'b1111101101); // 447 + assign ex2_hacop_rdec = (ex2_instr[11:20] == 10'b1111101010); // 351 + assign ex2_iac1_rdec = (ex2_instr[11:20] == 10'b1100001001); // 312 + assign ex2_iac2_rdec = (ex2_instr[11:20] == 10'b1100101001); // 313 + assign ex2_iac3_rdec = (ex2_instr[11:20] == 10'b1101001001); // 314 + assign ex2_iac4_rdec = (ex2_instr[11:20] == 10'b1101101001); // 315 + assign ex2_immr_rdec = (ex2_instr[11:20] == 10'b1000111011); // 881 + assign ex2_imr_rdec = (ex2_instr[11:20] == 10'b1000011011); // 880 + assign ex2_iucr0_rdec = (ex2_instr[11:20] == 10'b1001111111); // 1011 + assign ex2_iucr1_rdec = (ex2_instr[11:20] == 10'b1001111011); // 883 + assign ex2_iucr2_rdec = (ex2_instr[11:20] == 10'b1010011011); // 884 + assign ex2_iudbg0_rdec = (ex2_instr[11:20] == 10'b1100011011); // 888 + assign ex2_iudbg1_rdec = (ex2_instr[11:20] == 10'b1100111011); // 889 + assign ex2_iudbg2_rdec = (ex2_instr[11:20] == 10'b1101011011); // 890 + assign ex2_iulfsr_rdec = (ex2_instr[11:20] == 10'b1101111011); // 891 + assign ex2_iullcr_rdec = (ex2_instr[11:20] == 10'b1110011011); // 892 + assign ex2_ivpr_rdec = (ex2_instr[11:20] == 10'b1111100001); // 63 + assign ex2_lesr1_rdec = (ex2_instr[11:20] == 10'b1100011100); // 920 + assign ex2_lesr2_rdec = (ex2_instr[11:20] == 10'b1100111100); // 921 + assign ex2_lper_rdec = (ex2_instr[11:20] == 10'b1100000001); // 56 + assign ex2_lperu_rdec = (ex2_instr[11:20] == 10'b1100100001); // 57 + assign ex2_lpidr_rdec = (ex2_instr[11:20] == 10'b1001001010); // 338 + assign ex2_lratcfg_rdec = (ex2_instr[11:20] == 10'b1011001010); // 342 + assign ex2_lratps_rdec = (ex2_instr[11:20] == 10'b1011101010); // 343 + assign ex2_lsucr0_rdec = (ex2_instr[11:20] == 10'b1001111001); // 819 + assign ex2_mas0_rdec = (ex2_instr[11:20] == 10'b1000010011); // 624 + assign ex2_mas0_mas1_rdec = (ex2_instr[11:20] == 10'b1010101011); // 373 + assign ex2_mas1_rdec = (ex2_instr[11:20] == 10'b1000110011); // 625 + assign ex2_mas2_rdec = (ex2_instr[11:20] == 10'b1001010011); // 626 + assign ex2_mas2u_rdec = (ex2_instr[11:20] == 10'b1011110011); // 631 + assign ex2_mas3_rdec = (ex2_instr[11:20] == 10'b1001110011); // 627 + assign ex2_mas4_rdec = (ex2_instr[11:20] == 10'b1010010011); // 628 + assign ex2_mas5_rdec = (ex2_instr[11:20] == 10'b1001101010); // 339 + assign ex2_mas5_mas6_rdec = (ex2_instr[11:20] == 10'b1110001010); // 348 + assign ex2_mas6_rdec = (ex2_instr[11:20] == 10'b1011010011); // 630 + assign ex2_mas7_rdec = (ex2_instr[11:20] == 10'b1000011101); // 944 + assign ex2_mas7_mas3_rdec = (ex2_instr[11:20] == 10'b1010001011); // 372 + assign ex2_mas8_rdec = (ex2_instr[11:20] == 10'b1010101010); // 341 + assign ex2_mas8_mas1_rdec = (ex2_instr[11:20] == 10'b1110101010); // 349 + assign ex2_mmucfg_rdec = (ex2_instr[11:20] == 10'b1011111111); // 1015 + assign ex2_mmucr0_rdec = (ex2_instr[11:20] == 10'b1110011111); // 1020 + assign ex2_mmucr1_rdec = (ex2_instr[11:20] == 10'b1110111111); // 1021 + assign ex2_mmucr2_rdec = (ex2_instr[11:20] == 10'b1111011111); // 1022 + assign ex2_mmucr3_rdec = (ex2_instr[11:20] == 10'b1111111111); // 1023 + assign ex2_mmucsr0_rdec = (ex2_instr[11:20] == 10'b1010011111); // 1012 + assign ex2_pesr_rdec = (ex2_instr[11:20] == 10'b1110111011); // 893 + assign ex2_pid_rdec = (ex2_instr[11:20] == 10'b1000000001); // 48 + assign ex2_ppr32_rdec = (ex2_instr[11:20] == 10'b0001011100); // 898 + assign ex2_sramd_rdec = (ex2_instr[11:20] == 10'b1111011011); // 894 + assign ex2_tlb0cfg_rdec = (ex2_instr[11:20] == 10'b1000010101); // 688 + assign ex2_tlb0ps_rdec = (ex2_instr[11:20] == 10'b1100001010); // 344 + assign ex2_xucr2_rdec = (ex2_instr[11:20] == 10'b1100011111); // 1016 + assign ex2_xudbg0_rdec = (ex2_instr[11:20] == 10'b1010111011); // 885 + assign ex2_xudbg1_rdec = (ex2_instr[11:20] == 10'b1011011011); // 886 + assign ex2_xudbg2_rdec = (ex2_instr[11:20] == 10'b1011111011); // 887 + assign ex2_acop_re = ex2_acop_rdec; + assign ex2_axucr0_re = ex2_axucr0_rdec; + assign ex2_cpcr0_re = ex2_cpcr0_rdec; + assign ex2_cpcr1_re = ex2_cpcr1_rdec; + assign ex2_cpcr2_re = ex2_cpcr2_rdec; + assign ex2_cpcr3_re = ex2_cpcr3_rdec; + assign ex2_cpcr4_re = ex2_cpcr4_rdec; + assign ex2_cpcr5_re = ex2_cpcr5_rdec; + assign ex2_dac1_re = ex2_dac1_rdec; + assign ex2_dac2_re = ex2_dac2_rdec; + assign ex2_dac3_re = ex2_dac3_rdec; + assign ex2_dac4_re = ex2_dac4_rdec; + assign ex2_dbcr2_re = ex2_dbcr2_rdec; + assign ex2_dbcr3_re = ex2_dbcr3_rdec; + assign ex2_dscr_re = ex2_dscr_rdec; + assign ex2_dvc1_re = ex2_dvc1_rdec; + assign ex2_dvc2_re = ex2_dvc2_rdec; + assign ex2_eheir_re = ex2_eheir_rdec; + assign ex2_eplc_re = ex2_eplc_rdec; + assign ex2_epsc_re = ex2_epsc_rdec; + assign ex2_eptcfg_re = ex2_eptcfg_rdec; + assign ex2_givpr_re = ex2_givpr_rdec; + assign ex2_hacop_re = ex2_hacop_rdec; + assign ex2_iac1_re = ex2_iac1_rdec; + assign ex2_iac2_re = ex2_iac2_rdec; + assign ex2_iac3_re = ex2_iac3_rdec; + assign ex2_iac4_re = ex2_iac4_rdec; + assign ex2_immr_re = ex2_immr_rdec; + assign ex2_imr_re = ex2_imr_rdec; + assign ex2_iucr0_re = ex2_iucr0_rdec; + assign ex2_iucr1_re = ex2_iucr1_rdec; + assign ex2_iucr2_re = ex2_iucr2_rdec; + assign ex2_iudbg0_re = ex2_iudbg0_rdec; + assign ex2_iudbg1_re = ex2_iudbg1_rdec; + assign ex2_iudbg2_re = ex2_iudbg2_rdec; + assign ex2_iulfsr_re = ex2_iulfsr_rdec; + assign ex2_iullcr_re = ex2_iullcr_rdec; + assign ex2_ivpr_re = ex2_ivpr_rdec; + assign ex2_lesr1_re = ex2_lesr1_rdec; + assign ex2_lesr2_re = ex2_lesr2_rdec; + assign ex2_lper_re = ex2_lper_rdec; + assign ex2_lperu_re = ex2_lperu_rdec; + assign ex2_lpidr_re = ex2_lpidr_rdec; + assign ex2_lratcfg_re = ex2_lratcfg_rdec; + assign ex2_lratps_re = ex2_lratps_rdec; + assign ex2_lsucr0_re = ex2_lsucr0_rdec; + assign ex2_mas0_re = ex2_mas0_rdec; + assign ex2_mas0_mas1_re = ex2_mas0_mas1_rdec; + assign ex2_mas1_re = ex2_mas1_rdec; + assign ex2_mas2_re = ex2_mas2_rdec; + assign ex2_mas2u_re = ex2_mas2u_rdec; + assign ex2_mas3_re = ex2_mas3_rdec; + assign ex2_mas4_re = ex2_mas4_rdec; + assign ex2_mas5_re = ex2_mas5_rdec; + assign ex2_mas5_mas6_re = ex2_mas5_mas6_rdec; + assign ex2_mas6_re = ex2_mas6_rdec; + assign ex2_mas7_re = ex2_mas7_rdec; + assign ex2_mas7_mas3_re = ex2_mas7_mas3_rdec; + assign ex2_mas8_re = ex2_mas8_rdec; + assign ex2_mas8_mas1_re = ex2_mas8_mas1_rdec; + assign ex2_mmucfg_re = ex2_mmucfg_rdec; + assign ex2_mmucr0_re = ex2_mmucr0_rdec; + assign ex2_mmucr1_re = ex2_mmucr1_rdec; + assign ex2_mmucr2_re = ex2_mmucr2_rdec; + assign ex2_mmucr3_re = ex2_mmucr3_rdec; + assign ex2_mmucsr0_re = ex2_mmucsr0_rdec; + assign ex2_pesr_re = ex2_pesr_rdec; + assign ex2_pid_re = ex2_pid_rdec; + assign ex2_ppr32_re = ex2_ppr32_rdec; + assign ex2_sramd_re = ex2_sramd_rdec; + assign ex2_tlb0cfg_re = ex2_tlb0cfg_rdec; + assign ex2_tlb0ps_re = ex2_tlb0ps_rdec; + assign ex2_xucr2_re = ex2_xucr2_rdec; + assign ex2_xudbg0_re = ex2_xudbg0_rdec; + assign ex2_xudbg1_re = ex2_xudbg1_rdec; + assign ex2_xudbg2_re = ex2_xudbg2_rdec; + assign ex2_acop_wdec = ex2_acop_rdec; + assign ex2_axucr0_wdec = ex2_axucr0_rdec; + assign ex2_cpcr0_wdec = ex2_cpcr0_rdec; + assign ex2_cpcr1_wdec = ex2_cpcr1_rdec; + assign ex2_cpcr2_wdec = ex2_cpcr2_rdec; + assign ex2_cpcr3_wdec = ex2_cpcr3_rdec; + assign ex2_cpcr4_wdec = ex2_cpcr4_rdec; + assign ex2_cpcr5_wdec = ex2_cpcr5_rdec; + assign ex2_dac1_wdec = ex2_dac1_rdec; + assign ex2_dac2_wdec = ex2_dac2_rdec; + assign ex2_dac3_wdec = ex2_dac3_rdec; + assign ex2_dac4_wdec = ex2_dac4_rdec; + assign ex2_dbcr2_wdec = ex2_dbcr2_rdec; + assign ex2_dbcr3_wdec = ex2_dbcr3_rdec; + assign ex2_dscr_wdec = ex2_dscr_rdec; + assign ex2_dvc1_wdec = ex2_dvc1_rdec; + assign ex2_dvc2_wdec = ex2_dvc2_rdec; + assign ex2_eheir_wdec = ex2_eheir_rdec; + assign ex2_eplc_wdec = ex2_eplc_rdec; + assign ex2_epsc_wdec = ex2_epsc_rdec; + assign ex2_givpr_wdec = (ex2_instr[11:20] == 10'b1111101101); // 447 + assign ex2_hacop_wdec = (ex2_instr[11:20] == 10'b1111101010); // 351 + assign ex2_iac1_wdec = ex2_iac1_rdec; + assign ex2_iac2_wdec = ex2_iac2_rdec; + assign ex2_iac3_wdec = ex2_iac3_rdec; + assign ex2_iac4_wdec = ex2_iac4_rdec; + assign ex2_immr_wdec = ex2_immr_rdec; + assign ex2_imr_wdec = ex2_imr_rdec; + assign ex2_iucr0_wdec = ex2_iucr0_rdec; + assign ex2_iucr1_wdec = ex2_iucr1_rdec; + assign ex2_iucr2_wdec = ex2_iucr2_rdec; + assign ex2_iudbg0_wdec = ex2_iudbg0_rdec; + assign ex2_iulfsr_wdec = ex2_iulfsr_rdec; + assign ex2_iullcr_wdec = ex2_iullcr_rdec; + assign ex2_ivpr_wdec = ex2_ivpr_rdec; + assign ex2_lesr1_wdec = ex2_lesr1_rdec; + assign ex2_lesr2_wdec = ex2_lesr2_rdec; + assign ex2_lper_wdec = ex2_lper_rdec; + assign ex2_lperu_wdec = ex2_lperu_rdec; + assign ex2_lpidr_wdec = ex2_lpidr_rdec; + assign ex2_lsucr0_wdec = ex2_lsucr0_rdec; + assign ex2_mas0_wdec = ex2_mas0_rdec; + assign ex2_mas0_mas1_wdec = ex2_mas0_mas1_rdec; + assign ex2_mas1_wdec = ex2_mas1_rdec; + assign ex2_mas2_wdec = ex2_mas2_rdec; + assign ex2_mas2u_wdec = ex2_mas2u_rdec; + assign ex2_mas3_wdec = ex2_mas3_rdec; + assign ex2_mas4_wdec = ex2_mas4_rdec; + assign ex2_mas5_wdec = ex2_mas5_rdec; + assign ex2_mas5_mas6_wdec = ex2_mas5_mas6_rdec; + assign ex2_mas6_wdec = ex2_mas6_rdec; + assign ex2_mas7_wdec = ex2_mas7_rdec; + assign ex2_mas7_mas3_wdec = ex2_mas7_mas3_rdec; + assign ex2_mas8_wdec = ex2_mas8_rdec; + assign ex2_mas8_mas1_wdec = ex2_mas8_mas1_rdec; + assign ex2_mmucr0_wdec = ex2_mmucr0_rdec; + assign ex2_mmucr1_wdec = ex2_mmucr1_rdec; + assign ex2_mmucr2_wdec = ex2_mmucr2_rdec; + assign ex2_mmucr3_wdec = ex2_mmucr3_rdec; + assign ex2_mmucsr0_wdec = ex2_mmucsr0_rdec; + assign ex2_pesr_wdec = ex2_pesr_rdec; + assign ex2_pid_wdec = ex2_pid_rdec; + assign ex2_ppr32_wdec = ex2_ppr32_rdec; + assign ex2_xucr2_wdec = ex2_xucr2_rdec; + assign ex2_xudbg0_wdec = ex2_xudbg0_rdec; + assign ex2_acop_we = ex2_acop_wdec; + assign ex2_axucr0_we = ex2_axucr0_wdec; + assign ex2_cpcr0_we = ex2_cpcr0_wdec; + assign ex2_cpcr1_we = ex2_cpcr1_wdec; + assign ex2_cpcr2_we = ex2_cpcr2_wdec; + assign ex2_cpcr3_we = ex2_cpcr3_wdec; + assign ex2_cpcr4_we = ex2_cpcr4_wdec; + assign ex2_cpcr5_we = ex2_cpcr5_wdec; + assign ex2_dac1_we = ex2_dac1_wdec; + assign ex2_dac2_we = ex2_dac2_wdec; + assign ex2_dac3_we = ex2_dac3_wdec; + assign ex2_dac4_we = ex2_dac4_wdec; + assign ex2_dbcr2_we = ex2_dbcr2_wdec; + assign ex2_dbcr3_we = ex2_dbcr3_wdec; + assign ex2_dscr_we = ex2_dscr_wdec; + assign ex2_dvc1_we = ex2_dvc1_wdec; + assign ex2_dvc2_we = ex2_dvc2_wdec; + assign ex2_eheir_we = ex2_eheir_wdec; + assign ex2_eplc_we = ex2_eplc_wdec; + assign ex2_epsc_we = ex2_epsc_wdec; + assign ex2_givpr_we = ex2_givpr_wdec; + assign ex2_hacop_we = ex2_hacop_wdec; + assign ex2_iac1_we = ex2_iac1_wdec; + assign ex2_iac2_we = ex2_iac2_wdec; + assign ex2_iac3_we = ex2_iac3_wdec; + assign ex2_iac4_we = ex2_iac4_wdec; + assign ex2_immr_we = ex2_immr_wdec; + assign ex2_imr_we = ex2_imr_wdec; + assign ex2_iucr0_we = ex2_iucr0_wdec; + assign ex2_iucr1_we = ex2_iucr1_wdec; + assign ex2_iucr2_we = ex2_iucr2_wdec; + assign ex2_iudbg0_we = ex2_iudbg0_wdec; + assign ex2_iulfsr_we = ex2_iulfsr_wdec; + assign ex2_iullcr_we = ex2_iullcr_wdec; + assign ex2_ivpr_we = ex2_ivpr_wdec; + assign ex2_lesr1_we = ex2_lesr1_wdec; + assign ex2_lesr2_we = ex2_lesr2_wdec; + assign ex2_lper_we = ex2_lper_wdec; + assign ex2_lperu_we = ex2_lperu_wdec; + assign ex2_lpidr_we = ex2_lpidr_wdec; + assign ex2_lsucr0_we = ex2_lsucr0_wdec; + assign ex2_mas0_we = ex2_mas0_wdec; + assign ex2_mas0_mas1_we = ex2_mas0_mas1_wdec; + assign ex2_mas1_we = ex2_mas1_wdec; + assign ex2_mas2_we = ex2_mas2_wdec; + assign ex2_mas2u_we = ex2_mas2u_wdec; + assign ex2_mas3_we = ex2_mas3_wdec; + assign ex2_mas4_we = ex2_mas4_wdec; + assign ex2_mas5_we = ex2_mas5_wdec; + assign ex2_mas5_mas6_we = ex2_mas5_mas6_wdec; + assign ex2_mas6_we = ex2_mas6_wdec; + assign ex2_mas7_we = ex2_mas7_wdec; + assign ex2_mas7_mas3_we = ex2_mas7_mas3_wdec; + assign ex2_mas8_we = ex2_mas8_wdec; + assign ex2_mas8_mas1_we = ex2_mas8_mas1_wdec; + assign ex2_mmucr0_we = ex2_mmucr0_wdec; + assign ex2_mmucr1_we = ex2_mmucr1_wdec; + assign ex2_mmucr2_we = ex2_mmucr2_wdec; + assign ex2_mmucr3_we = ex2_mmucr3_wdec; + assign ex2_mmucsr0_we = ex2_mmucsr0_wdec; + assign ex2_pesr_we = ex2_pesr_wdec; + assign ex2_pid_we = ex2_pid_wdec; + assign ex2_ppr32_we = ex2_ppr32_wdec; + assign ex2_xucr2_we = ex2_xucr2_wdec; + assign ex2_xudbg0_we = ex2_xudbg0_wdec; + assign ex2_slowspr_range_hypv = ex2_instr[11] & ex2_instr[16:20] == 5'b11110; // 976-991 + assign ex2_slowspr_range_priv = ex2_instr[11] & ex2_instr[16:20] == 5'b11100 & (~(ex2_xesr1_rdec | ex2_xesr2_rdec)); // 912-927 except 918/919 + assign ex2_slowspr_range = ex2_slowspr_range_priv | ex2_slowspr_range_hypv; + + // mftb encode is only legal for tbr=268,269 -- "0110-01000" + assign ex2_illeg_mftb = ex2_is_mftb_q & (~(ex2_instr[11:14] == 4'b0110 & ex2_instr[16:20] == 5'b01000)); + + assign ex2_sspr_wr_val = ex2_is_mtspr_q & (ex2_slowspr_range | + ex2_acop_we | ex2_axucr0_we | ex2_cpcr0_we + | ex2_cpcr1_we | ex2_cpcr2_we | ex2_cpcr3_we + | ex2_cpcr4_we | ex2_cpcr5_we | ex2_dac1_we + | ex2_dac2_we | ex2_dac3_we | ex2_dac4_we + | ex2_dbcr2_we | ex2_dbcr3_we | ex2_dscr_we + | ex2_dvc1_we | ex2_dvc2_we | ex2_eheir_we + | ex2_eplc_we | ex2_epsc_we | ex2_givpr_we + | ex2_hacop_we | ex2_iac1_we | ex2_iac2_we + | ex2_iac3_we | ex2_iac4_we | ex2_immr_we + | ex2_imr_we | ex2_iucr0_we | ex2_iucr1_we + | ex2_iucr2_we | ex2_iudbg0_we | ex2_iulfsr_we + | ex2_iullcr_we | ex2_ivpr_we | ex2_lesr1_we + | ex2_lesr2_we | ex2_lper_we | ex2_lperu_we + | ex2_lpidr_we | ex2_lsucr0_we | ex2_mas0_we + | ex2_mas0_mas1_we | ex2_mas1_we | ex2_mas2_we + | ex2_mas2u_we | ex2_mas3_we | ex2_mas4_we + | ex2_mas5_we | ex2_mas5_mas6_we | ex2_mas6_we + | ex2_mas7_we | ex2_mas7_mas3_we | ex2_mas8_we + | ex2_mas8_mas1_we | ex2_mmucr0_we | ex2_mmucr1_we + | ex2_mmucr2_we | ex2_mmucr3_we | ex2_mmucsr0_we + | ex2_pesr_we | ex2_pid_we | ex2_ppr32_we + | ex2_xucr2_we | ex2_xudbg0_we ); + + assign ex2_sspr_rd_val = ex2_is_mfspr_q & (ex2_slowspr_range | + ex2_acop_re | ex2_axucr0_re | ex2_cpcr0_re + | ex2_cpcr1_re | ex2_cpcr2_re | ex2_cpcr3_re + | ex2_cpcr4_re | ex2_cpcr5_re | ex2_dac1_re + | ex2_dac2_re | ex2_dac3_re | ex2_dac4_re + | ex2_dbcr2_re | ex2_dbcr3_re | ex2_dscr_re + | ex2_dvc1_re | ex2_dvc2_re | ex2_eheir_re + | ex2_eplc_re | ex2_epsc_re | ex2_eptcfg_re + | ex2_givpr_re | ex2_hacop_re | ex2_iac1_re + | ex2_iac2_re | ex2_iac3_re | ex2_iac4_re + | ex2_immr_re | ex2_imr_re | ex2_iucr0_re + | ex2_iucr1_re | ex2_iucr2_re | ex2_iudbg0_re + | ex2_iudbg1_re | ex2_iudbg2_re | ex2_iulfsr_re + | ex2_iullcr_re | ex2_ivpr_re | ex2_lesr1_re + | ex2_lesr2_re | ex2_lper_re | ex2_lperu_re + | ex2_lpidr_re | ex2_lratcfg_re | ex2_lratps_re + | ex2_lsucr0_re | ex2_mas0_re | ex2_mas0_mas1_re + | ex2_mas1_re | ex2_mas2_re | ex2_mas2u_re + | ex2_mas3_re | ex2_mas4_re | ex2_mas5_re + | ex2_mas5_mas6_re | ex2_mas6_re | ex2_mas7_re + | ex2_mas7_mas3_re | ex2_mas8_re | ex2_mas8_mas1_re + | ex2_mmucfg_re | ex2_mmucr0_re | ex2_mmucr1_re + | ex2_mmucr2_re | ex2_mmucr3_re | ex2_mmucsr0_re + | ex2_pesr_re | ex2_pid_re | ex2_ppr32_re + | ex2_sramd_re | ex2_tlb0cfg_re | ex2_tlb0ps_re + | ex2_xucr2_re | ex2_xudbg0_re | ex2_xudbg1_re + | ex2_xudbg2_re ); + + // Illegal SPR checks + assign ex2_sprg8_re = ex2_sprg8_rdec; + assign ex2_gsprg0_rdec = (ex2_instr[11:20] == 10'b1000001011); // 368 + assign ex2_gsprg1_rdec = (ex2_instr[11:20] == 10'b1000101011); // 369 + assign ex2_gsprg2_rdec = (ex2_instr[11:20] == 10'b1001001011); // 370 + assign ex2_gsprg3_rdec = (ex2_instr[11:20] == 10'b1001101011); // 371 + assign ex2_sprg0_rdec = (ex2_instr[11:20] == 10'b1000001000); // 272 + assign ex2_sprg1_rdec = (ex2_instr[11:20] == 10'b1000101000); // 273 + assign ex2_sprg2_rdec = (ex2_instr[11:20] == 10'b1001001000); // 274 + assign ex2_sprg3_rdec = ((ex2_instr[11:20] == 10'b1001101000) | // 275 + (ex2_instr[11:20] == 10'b0001101000)); // 259 + assign ex2_sprg4_rdec = ((ex2_instr[11:20] == 10'b1010001000) | // 276 + (ex2_instr[11:20] == 10'b0010001000)); // 260 + assign ex2_sprg5_rdec = ((ex2_instr[11:20] == 10'b1010101000) | // 277 + (ex2_instr[11:20] == 10'b0010101000)); // 261 + assign ex2_sprg6_rdec = ((ex2_instr[11:20] == 10'b1011001000) | // 278 + (ex2_instr[11:20] == 10'b0011001000)); // 262 + assign ex2_sprg7_rdec = ((ex2_instr[11:20] == 10'b1011101000) | // 279 + (ex2_instr[11:20] == 10'b0011101000)); // 263 + assign ex2_sprg8_rdec = (ex2_instr[11:20] == 10'b1110010010); // 604 + assign ex2_vrsave_rdec = (ex2_instr[11:20] == 10'b0000001000); // 256 + assign ex2_ccr0_rdec = (ex2_instr[11:20] == 10'b1000011111); // 1008 + assign ex2_ccr1_rdec = (ex2_instr[11:20] == 10'b1000111111); // 1009 + assign ex2_ccr2_rdec = (ex2_instr[11:20] == 10'b1001011111); // 1010 + assign ex2_ccr4_rdec = (ex2_instr[11:20] == 10'b1011011010); // 854 + assign ex2_cir_rdec = (ex2_instr[11:20] == 10'b1101101000); // 283 + assign ex2_pir_rdec = (ex2_instr[11:20] == 10'b1111001000); // 286 + assign ex2_pvr_rdec = (ex2_instr[11:20] == 10'b1111101000); // 287 + assign ex2_tb_rdec = (ex2_instr[11:20] == 10'b0110001000); // 268 + assign ex2_tbu_rdec = ((ex2_instr[11:20] == 10'b0110101000)); // 269 + assign ex2_tenc_rdec = (ex2_instr[11:20] == 10'b1011101101); // 439 + assign ex2_tens_rdec = (ex2_instr[11:20] == 10'b1011001101); // 438 + assign ex2_tensr_rdec = (ex2_instr[11:20] == 10'b1010101101); // 437 + assign ex2_tir_rdec = (ex2_instr[11:20] == 10'b1111001101); // 446 + assign ex2_xesr1_rdec = (ex2_instr[11:20] == 10'b1011011100); // 918 + assign ex2_xesr2_rdec = (ex2_instr[11:20] == 10'b1011111100); // 919 + assign ex2_xucr0_rdec = (ex2_instr[11:20] == 10'b1011011111); // 1014 + assign ex2_xucr4_rdec = (ex2_instr[11:20] == 10'b1010111010); // 853 + assign ex2_ccr0_re = ex2_ccr0_rdec; + assign ex2_ccr1_re = ex2_ccr1_rdec; + assign ex2_ccr2_re = ex2_ccr2_rdec; + assign ex2_ccr4_re = ex2_ccr4_rdec; + assign ex2_cir_re = ex2_cir_rdec; + assign ex2_pir_re = ex2_pir_rdec & ~ex2_msr_gs_q[0]; + assign ex2_pvr_re = ex2_pvr_rdec; + assign ex2_tb_re = ex2_tb_rdec; + assign ex2_tbu_re = ex2_tbu_rdec; + assign ex2_tenc_re = ex2_tenc_rdec; + assign ex2_tens_re = ex2_tens_rdec; + assign ex2_tensr_re = ex2_tensr_rdec; + assign ex2_tir_re = ex2_tir_rdec; + assign ex2_xesr1_re = ex2_xesr1_rdec; + assign ex2_xesr2_re = ex2_xesr2_rdec; + assign ex2_xucr0_re = ex2_xucr0_rdec; + assign ex2_xucr4_re = ex2_xucr4_rdec; + assign ex2_ccr0_wdec = ex2_ccr0_rdec; + assign ex2_ccr1_wdec = ex2_ccr1_rdec; + assign ex2_ccr2_wdec = ex2_ccr2_rdec; + assign ex2_ccr4_wdec = ex2_ccr4_rdec; + assign ex2_tbl_wdec = (ex2_instr[11:20] == 10'b1110001000); // 284 + assign ex2_tbu_wdec = ((ex2_instr[11:20] == 10'b1110101000)); // 285 + assign ex2_tenc_wdec = ex2_tenc_rdec; + assign ex2_tens_wdec = ex2_tens_rdec; + assign ex2_trace_wdec = (ex2_instr[11:20] == 10'b0111011111); // 1006 + assign ex2_xesr1_wdec = ex2_xesr1_rdec; + assign ex2_xesr2_wdec = ex2_xesr2_rdec; + assign ex2_xucr0_wdec = ex2_xucr0_rdec; + assign ex2_xucr4_wdec = ex2_xucr4_rdec; + assign ex2_ccr0_we = ex2_ccr0_wdec; + assign ex2_ccr1_we = ex2_ccr1_wdec; + assign ex2_ccr2_we = ex2_ccr2_wdec; + assign ex2_ccr4_we = ex2_ccr4_wdec; + assign ex2_tbl_we = ex2_tbl_wdec; + assign ex2_tbu_we = ex2_tbu_wdec; + assign ex2_tenc_we = ex2_tenc_wdec; + assign ex2_tens_we = ex2_tens_wdec; + assign ex2_trace_we = ex2_trace_wdec; + assign ex2_xesr1_we = ex2_xesr1_wdec; + assign ex2_xesr2_we = ex2_xesr2_wdec; + assign ex2_xucr0_we = ex2_xucr0_wdec; + assign ex2_xucr4_we = ex2_xucr4_wdec; + + generate + if (a2mode == 0 & hvmode == 0) + begin : ill_spr_00 + + assign ex2_illeg_mfspr = ex2_is_mfspr_q & ~( + ex2_ccr0_rdec | ex2_ccr1_rdec | ex2_ccr2_rdec + | ex2_ccr4_rdec | ex2_cir_rdec | ex2_pir_rdec + | ex2_pvr_rdec | ex2_tb_rdec | ex2_tbu_rdec + | ex2_tenc_rdec | ex2_tens_rdec | ex2_tensr_rdec + | ex2_tir_rdec | ex2_xesr1_rdec | ex2_xesr2_rdec + | ex2_xucr0_rdec | ex2_xucr4_rdec | + ex2_sprg0_rdec | ex2_sprg1_rdec | ex2_sprg2_rdec + | ex2_sprg3_rdec | ex2_sprg4_rdec | ex2_sprg5_rdec + | ex2_sprg6_rdec | ex2_sprg7_rdec | ex2_sprg8_rdec + | ex2_vrsave_rdec | + ex2_axucr0_rdec | ex2_cpcr0_rdec | ex2_cpcr1_rdec + | ex2_cpcr2_rdec | ex2_cpcr3_rdec | ex2_cpcr4_rdec + | ex2_cpcr5_rdec | ex2_dac3_rdec | ex2_dac4_rdec + | ex2_dbcr3_rdec | ex2_dscr_rdec | ex2_eheir_rdec + | ex2_iac1_rdec | ex2_iac2_rdec | ex2_iucr0_rdec + | ex2_iucr1_rdec | ex2_iucr2_rdec | ex2_iudbg0_rdec + | ex2_iudbg1_rdec | ex2_iudbg2_rdec | ex2_iulfsr_rdec + | ex2_iullcr_rdec | ex2_ivpr_rdec | ex2_lesr1_rdec + | ex2_lesr2_rdec | ex2_lpidr_rdec | ex2_lsucr0_rdec + | ex2_pesr_rdec | ex2_pid_rdec | ex2_ppr32_rdec + | ex2_sramd_rdec | ex2_xucr2_rdec | ex2_xudbg0_rdec + | ex2_xudbg1_rdec | ex2_xudbg2_rdec | + ex2_slowspr_range | + |(tspr_cspr_illeg_mfspr_b & ex2_tid)); + + assign ex2_illeg_mtspr = ex2_is_mtspr_q & ~( + ex2_ccr0_wdec | ex2_ccr1_wdec | ex2_ccr2_wdec + | ex2_ccr4_wdec | ex2_tbl_wdec | ex2_tbu_wdec + | ex2_tenc_wdec | ex2_tens_wdec | ex2_trace_wdec + | ex2_xesr1_wdec | ex2_xesr2_wdec | ex2_xucr0_wdec + | ex2_xucr4_wdec | + ex2_sprg0_wdec | ex2_sprg1_wdec | ex2_sprg2_wdec + | ex2_sprg3_wdec | ex2_sprg4_wdec | ex2_sprg5_wdec + | ex2_sprg6_wdec | ex2_sprg7_wdec | ex2_sprg8_wdec + | ex2_vrsave_wdec | + ex2_axucr0_wdec | ex2_cpcr0_wdec | ex2_cpcr1_wdec + | ex2_cpcr2_wdec | ex2_cpcr3_wdec | ex2_cpcr4_wdec + | ex2_cpcr5_wdec | ex2_dac3_wdec | ex2_dac4_wdec + | ex2_dbcr3_wdec | ex2_dscr_wdec | ex2_eheir_wdec + | ex2_iac1_wdec | ex2_iac2_wdec | ex2_iucr0_wdec + | ex2_iucr1_wdec | ex2_iucr2_wdec | ex2_iudbg0_wdec + | ex2_iulfsr_wdec | ex2_iullcr_wdec | ex2_ivpr_wdec + | ex2_lesr1_wdec | ex2_lesr2_wdec | ex2_lpidr_wdec + | ex2_lsucr0_wdec | ex2_pesr_wdec | ex2_pid_wdec + | ex2_ppr32_wdec | ex2_xucr2_wdec | ex2_xudbg0_wdec | + ex2_slowspr_range | + |(tspr_cspr_illeg_mtspr_b & ex2_tid)); + + assign ex2_hypv_mfspr = ex2_is_mfspr_q & ( + ex2_ccr0_re | ex2_ccr1_re | ex2_ccr2_re + | ex2_ccr4_re | ex2_tenc_re | ex2_tens_re + | ex2_tensr_re | ex2_tir_re | ex2_xucr0_re + | ex2_xucr4_re | + ex2_sprg8_re | + ex2_axucr0_re | ex2_cpcr0_re | ex2_cpcr1_re + | ex2_cpcr2_re | ex2_cpcr3_re | ex2_cpcr4_re + | ex2_cpcr5_re | ex2_dac3_re | ex2_dac4_re + | ex2_dbcr3_re | ex2_eheir_re | ex2_iac1_re + | ex2_iac2_re | ex2_iucr0_re | ex2_iucr1_re + | ex2_iucr2_re | ex2_iudbg0_re | ex2_iudbg1_re + | ex2_iudbg2_re | ex2_iulfsr_re | ex2_iullcr_re + | ex2_ivpr_re | ex2_lpidr_re | ex2_lsucr0_re + | ex2_xucr2_re | ex2_xudbg0_re | ex2_xudbg1_re + | ex2_xudbg2_re | + ex2_slowspr_range_hypv | + |(tspr_cspr_hypv_mfspr & ex2_tid)); + + assign ex2_hypv_mtspr = ex2_is_mtspr_q & ( + ex2_ccr0_we | ex2_ccr1_we | ex2_ccr2_we + | ex2_ccr4_we | ex2_tbl_we | ex2_tbu_we + | ex2_tenc_we | ex2_tens_we | ex2_xucr0_we + | ex2_xucr4_we | + ex2_sprg8_we | + ex2_axucr0_we | ex2_cpcr0_we | ex2_cpcr1_we + | ex2_cpcr2_we | ex2_cpcr3_we | ex2_cpcr4_we + | ex2_cpcr5_we | ex2_dac3_we | ex2_dac4_we + | ex2_dbcr3_we | ex2_eheir_we | ex2_iac1_we + | ex2_iac2_we | ex2_iucr0_we | ex2_iucr1_we + | ex2_iucr2_we | ex2_iudbg0_we | ex2_iulfsr_we + | ex2_iullcr_we | ex2_ivpr_we | ex2_lpidr_we + | ex2_lsucr0_we | ex2_xucr2_we | ex2_xudbg0_we | + ex2_slowspr_range_hypv | + |(tspr_cspr_hypv_mtspr & ex2_tid)); + + end + endgenerate + + generate + if (a2mode == 0 & hvmode == 1) + begin : ill_spr_01 + assign ex2_illeg_mfspr = ex2_is_mfspr_q & ~( + ex2_ccr0_rdec | ex2_ccr1_rdec | ex2_ccr2_rdec + | ex2_ccr4_rdec | ex2_cir_rdec | ex2_pir_rdec + | ex2_pvr_rdec | ex2_tb_rdec | ex2_tbu_rdec + | ex2_tenc_rdec | ex2_tens_rdec | ex2_tensr_rdec + | ex2_tir_rdec | ex2_xesr1_rdec | ex2_xesr2_rdec + | ex2_xucr0_rdec | ex2_xucr4_rdec | + ex2_gsprg0_rdec | ex2_gsprg1_rdec | ex2_gsprg2_rdec + | ex2_gsprg3_rdec | ex2_sprg0_rdec | ex2_sprg1_rdec + | ex2_sprg2_rdec | ex2_sprg3_rdec | ex2_sprg4_rdec + | ex2_sprg5_rdec | ex2_sprg6_rdec | ex2_sprg7_rdec + | ex2_sprg8_rdec | ex2_vrsave_rdec | + ex2_axucr0_rdec | ex2_cpcr0_rdec | ex2_cpcr1_rdec + | ex2_cpcr2_rdec | ex2_cpcr3_rdec | ex2_cpcr4_rdec + | ex2_cpcr5_rdec | ex2_dac3_rdec | ex2_dac4_rdec + | ex2_dbcr3_rdec | ex2_dscr_rdec | ex2_eheir_rdec + | ex2_eplc_rdec | ex2_epsc_rdec | ex2_eptcfg_rdec + | ex2_givpr_rdec | ex2_hacop_rdec | ex2_iac1_rdec + | ex2_iac2_rdec | ex2_iucr0_rdec | ex2_iucr1_rdec + | ex2_iucr2_rdec | ex2_iudbg0_rdec | ex2_iudbg1_rdec + | ex2_iudbg2_rdec | ex2_iulfsr_rdec | ex2_iullcr_rdec + | ex2_ivpr_rdec | ex2_lesr1_rdec | ex2_lesr2_rdec + | ex2_lper_rdec | ex2_lperu_rdec | ex2_lpidr_rdec + | ex2_lratcfg_rdec | ex2_lratps_rdec | ex2_lsucr0_rdec + | ex2_mas0_rdec | ex2_mas0_mas1_rdec | ex2_mas1_rdec + | ex2_mas2_rdec | ex2_mas2u_rdec | ex2_mas3_rdec + | ex2_mas4_rdec | ex2_mas5_rdec | ex2_mas5_mas6_rdec + | ex2_mas6_rdec | ex2_mas7_rdec | ex2_mas7_mas3_rdec + | ex2_mas8_rdec | ex2_mas8_mas1_rdec | ex2_mmucfg_rdec + | ex2_mmucr3_rdec | ex2_mmucsr0_rdec | ex2_pesr_rdec + | ex2_pid_rdec | ex2_ppr32_rdec | ex2_sramd_rdec + | ex2_tlb0cfg_rdec | ex2_tlb0ps_rdec | ex2_xucr2_rdec + | ex2_xudbg0_rdec | ex2_xudbg1_rdec | ex2_xudbg2_rdec | + ex2_slowspr_range | + |(tspr_cspr_illeg_mfspr_b & ex2_tid)); + + assign ex2_illeg_mtspr = ex2_is_mtspr_q & ~( + ex2_ccr0_wdec | ex2_ccr1_wdec | ex2_ccr2_wdec + | ex2_ccr4_wdec | ex2_tbl_wdec | ex2_tbu_wdec + | ex2_tenc_wdec | ex2_tens_wdec | ex2_trace_wdec + | ex2_xesr1_wdec | ex2_xesr2_wdec | ex2_xucr0_wdec + | ex2_xucr4_wdec | + ex2_gsprg0_wdec | ex2_gsprg1_wdec | ex2_gsprg2_wdec + | ex2_gsprg3_wdec | ex2_sprg0_wdec | ex2_sprg1_wdec + | ex2_sprg2_wdec | ex2_sprg3_wdec | ex2_sprg4_wdec + | ex2_sprg5_wdec | ex2_sprg6_wdec | ex2_sprg7_wdec + | ex2_sprg8_wdec | ex2_vrsave_wdec | + ex2_axucr0_wdec | ex2_cpcr0_wdec | ex2_cpcr1_wdec + | ex2_cpcr2_wdec | ex2_cpcr3_wdec | ex2_cpcr4_wdec + | ex2_cpcr5_wdec | ex2_dac3_wdec | ex2_dac4_wdec + | ex2_dbcr3_wdec | ex2_dscr_wdec | ex2_eheir_wdec + | ex2_eplc_wdec | ex2_epsc_wdec | ex2_givpr_wdec + | ex2_hacop_wdec | ex2_iac1_wdec | ex2_iac2_wdec + | ex2_iucr0_wdec | ex2_iucr1_wdec | ex2_iucr2_wdec + | ex2_iudbg0_wdec | ex2_iulfsr_wdec | ex2_iullcr_wdec + | ex2_ivpr_wdec | ex2_lesr1_wdec | ex2_lesr2_wdec + | ex2_lper_wdec | ex2_lperu_wdec | ex2_lpidr_wdec + | ex2_lsucr0_wdec | ex2_mas0_wdec | ex2_mas0_mas1_wdec + | ex2_mas1_wdec | ex2_mas2_wdec | ex2_mas2u_wdec + | ex2_mas3_wdec | ex2_mas4_wdec | ex2_mas5_wdec + | ex2_mas5_mas6_wdec | ex2_mas6_wdec | ex2_mas7_wdec + | ex2_mas7_mas3_wdec | ex2_mas8_wdec | ex2_mas8_mas1_wdec + | ex2_mmucr3_wdec | ex2_mmucsr0_wdec | ex2_pesr_wdec + | ex2_pid_wdec | ex2_ppr32_wdec | ex2_xucr2_wdec + | ex2_xudbg0_wdec | + ex2_slowspr_range | + |(tspr_cspr_illeg_mtspr_b & ex2_tid)); + + assign ex2_hypv_mfspr = ex2_is_mfspr_q & ( + ex2_ccr0_re | ex2_ccr1_re | ex2_ccr2_re + | ex2_ccr4_re | ex2_tenc_re | ex2_tens_re + | ex2_tensr_re | ex2_tir_re | ex2_xucr0_re + | ex2_xucr4_re | + ex2_sprg8_re | + ex2_axucr0_re | ex2_cpcr0_re | ex2_cpcr1_re + | ex2_cpcr2_re | ex2_cpcr3_re | ex2_cpcr4_re + | ex2_cpcr5_re | ex2_dac3_re | ex2_dac4_re + | ex2_dbcr3_re | ex2_eheir_re | ex2_eptcfg_re + | ex2_iac1_re | ex2_iac2_re | ex2_iucr0_re + | ex2_iucr1_re | ex2_iucr2_re | ex2_iudbg0_re + | ex2_iudbg1_re | ex2_iudbg2_re | ex2_iulfsr_re + | ex2_iullcr_re | ex2_ivpr_re | ex2_lper_re + | ex2_lperu_re | ex2_lpidr_re | ex2_lratcfg_re + | ex2_lratps_re | ex2_lsucr0_re | ex2_mas5_re + | ex2_mas5_mas6_re | ex2_mas8_re | ex2_mas8_mas1_re + | ex2_mmucfg_re | ex2_mmucsr0_re | ex2_tlb0cfg_re + | ex2_tlb0ps_re | ex2_xucr2_re | ex2_xudbg0_re + | ex2_xudbg1_re | ex2_xudbg2_re | + ex2_slowspr_range_hypv | + |(tspr_cspr_hypv_mfspr & ex2_tid)); + + assign ex2_hypv_mtspr = ex2_is_mtspr_q & ( + ex2_ccr0_we | ex2_ccr1_we | ex2_ccr2_we + | ex2_ccr4_we | ex2_tbl_we | ex2_tbu_we + | ex2_tenc_we | ex2_tens_we | ex2_xucr0_we + | ex2_xucr4_we | + ex2_sprg8_we | + ex2_axucr0_we | ex2_cpcr0_we | ex2_cpcr1_we + | ex2_cpcr2_we | ex2_cpcr3_we | ex2_cpcr4_we + | ex2_cpcr5_we | ex2_dac3_we | ex2_dac4_we + | ex2_dbcr3_we | ex2_eheir_we | ex2_givpr_we + | ex2_hacop_we | ex2_iac1_we | ex2_iac2_we + | ex2_iucr0_we | ex2_iucr1_we | ex2_iucr2_we + | ex2_iudbg0_we | ex2_iulfsr_we | ex2_iullcr_we + | ex2_ivpr_we | ex2_lper_we | ex2_lperu_we + | ex2_lpidr_we | ex2_lsucr0_we | ex2_mas5_we + | ex2_mas5_mas6_we | ex2_mas8_we | ex2_mas8_mas1_we + | ex2_mmucsr0_we | ex2_xucr2_we | ex2_xudbg0_we | + ex2_slowspr_range_hypv | + |(tspr_cspr_hypv_mtspr & ex2_tid)); + + end + endgenerate + + generate + if (a2mode == 1 & hvmode == 0) + begin : ill_spr_10 + assign ex2_illeg_mfspr = ex2_is_mfspr_q & ~( + ex2_ccr0_rdec | ex2_ccr1_rdec | ex2_ccr2_rdec + | ex2_ccr4_rdec | ex2_cir_rdec | ex2_pir_rdec + | ex2_pvr_rdec | ex2_tb_rdec | ex2_tbu_rdec + | ex2_tenc_rdec | ex2_tens_rdec | ex2_tensr_rdec + | ex2_tir_rdec | ex2_xesr1_rdec | ex2_xesr2_rdec + | ex2_xucr0_rdec | ex2_xucr4_rdec | + ex2_sprg0_rdec | ex2_sprg1_rdec | ex2_sprg2_rdec + | ex2_sprg3_rdec | ex2_sprg4_rdec | ex2_sprg5_rdec + | ex2_sprg6_rdec | ex2_sprg7_rdec | ex2_sprg8_rdec + | ex2_vrsave_rdec | + ex2_acop_rdec | ex2_axucr0_rdec | ex2_cpcr0_rdec + | ex2_cpcr1_rdec | ex2_cpcr2_rdec | ex2_cpcr3_rdec + | ex2_cpcr4_rdec | ex2_cpcr5_rdec | ex2_dac1_rdec + | ex2_dac2_rdec | ex2_dac3_rdec | ex2_dac4_rdec + | ex2_dbcr2_rdec | ex2_dbcr3_rdec | ex2_dscr_rdec + | ex2_dvc1_rdec | ex2_dvc2_rdec | ex2_eheir_rdec + | ex2_iac1_rdec | ex2_iac2_rdec | ex2_iac3_rdec + | ex2_iac4_rdec | ex2_immr_rdec | ex2_imr_rdec + | ex2_iucr0_rdec | ex2_iucr1_rdec | ex2_iucr2_rdec + | ex2_iudbg0_rdec | ex2_iudbg1_rdec | ex2_iudbg2_rdec + | ex2_iulfsr_rdec | ex2_iullcr_rdec | ex2_ivpr_rdec + | ex2_lesr1_rdec | ex2_lesr2_rdec | ex2_lpidr_rdec + | ex2_lsucr0_rdec | ex2_mmucr0_rdec | ex2_mmucr1_rdec + | ex2_mmucr2_rdec | ex2_pesr_rdec | ex2_pid_rdec + | ex2_ppr32_rdec | ex2_sramd_rdec | ex2_xucr2_rdec + | ex2_xudbg0_rdec | ex2_xudbg1_rdec | ex2_xudbg2_rdec | + ex2_slowspr_range | + |(tspr_cspr_illeg_mfspr_b & ex2_tid)); + + assign ex2_illeg_mtspr = ex2_is_mtspr_q & ~( + ex2_ccr0_wdec | ex2_ccr1_wdec | ex2_ccr2_wdec + | ex2_ccr4_wdec | ex2_tbl_wdec | ex2_tbu_wdec + | ex2_tenc_wdec | ex2_tens_wdec | ex2_trace_wdec + | ex2_xesr1_wdec | ex2_xesr2_wdec | ex2_xucr0_wdec + | ex2_xucr4_wdec | + ex2_sprg0_wdec | ex2_sprg1_wdec | ex2_sprg2_wdec + | ex2_sprg3_wdec | ex2_sprg4_wdec | ex2_sprg5_wdec + | ex2_sprg6_wdec | ex2_sprg7_wdec | ex2_sprg8_wdec + | ex2_vrsave_wdec | + ex2_acop_wdec | ex2_axucr0_wdec | ex2_cpcr0_wdec + | ex2_cpcr1_wdec | ex2_cpcr2_wdec | ex2_cpcr3_wdec + | ex2_cpcr4_wdec | ex2_cpcr5_wdec | ex2_dac1_wdec + | ex2_dac2_wdec | ex2_dac3_wdec | ex2_dac4_wdec + | ex2_dbcr2_wdec | ex2_dbcr3_wdec | ex2_dscr_wdec + | ex2_dvc1_wdec | ex2_dvc2_wdec | ex2_eheir_wdec + | ex2_iac1_wdec | ex2_iac2_wdec | ex2_iac3_wdec + | ex2_iac4_wdec | ex2_immr_wdec | ex2_imr_wdec + | ex2_iucr0_wdec | ex2_iucr1_wdec | ex2_iucr2_wdec + | ex2_iudbg0_wdec | ex2_iulfsr_wdec | ex2_iullcr_wdec + | ex2_ivpr_wdec | ex2_lesr1_wdec | ex2_lesr2_wdec + | ex2_lpidr_wdec | ex2_lsucr0_wdec | ex2_mmucr0_wdec + | ex2_mmucr1_wdec | ex2_mmucr2_wdec | ex2_pesr_wdec + | ex2_pid_wdec | ex2_ppr32_wdec | ex2_xucr2_wdec + | ex2_xudbg0_wdec | + ex2_slowspr_range | + |(tspr_cspr_illeg_mtspr_b & ex2_tid)); + + assign ex2_hypv_mfspr = ex2_is_mfspr_q & ( + ex2_ccr0_re | ex2_ccr1_re | ex2_ccr2_re + | ex2_ccr4_re | ex2_tenc_re | ex2_tens_re + | ex2_tensr_re | ex2_tir_re | ex2_xucr0_re + | ex2_xucr4_re | + ex2_sprg8_re | + ex2_axucr0_re | ex2_cpcr0_re | ex2_cpcr1_re + | ex2_cpcr2_re | ex2_cpcr3_re | ex2_cpcr4_re + | ex2_cpcr5_re | ex2_dac1_re | ex2_dac2_re + | ex2_dac3_re | ex2_dac4_re | ex2_dbcr2_re + | ex2_dbcr3_re | ex2_dvc1_re | ex2_dvc2_re + | ex2_eheir_re | ex2_iac1_re | ex2_iac2_re + | ex2_iac3_re | ex2_iac4_re | ex2_immr_re + | ex2_imr_re | ex2_iucr0_re | ex2_iucr1_re + | ex2_iucr2_re | ex2_iudbg0_re | ex2_iudbg1_re + | ex2_iudbg2_re | ex2_iulfsr_re | ex2_iullcr_re + | ex2_ivpr_re | ex2_lpidr_re | ex2_lsucr0_re + | ex2_mmucr0_re | ex2_mmucr1_re | ex2_mmucr2_re + | ex2_xucr2_re | ex2_xudbg0_re | ex2_xudbg1_re + | ex2_xudbg2_re | + ex2_slowspr_range_hypv | + |(tspr_cspr_hypv_mfspr & ex2_tid)); + + assign ex2_hypv_mtspr = ex2_is_mtspr_q & ( + ex2_ccr0_we | ex2_ccr1_we | ex2_ccr2_we + | ex2_ccr4_we | ex2_tbl_we | ex2_tbu_we + | ex2_tenc_we | ex2_tens_we | ex2_xucr0_we + | ex2_xucr4_we | + ex2_sprg8_we | + ex2_axucr0_we | ex2_cpcr0_we | ex2_cpcr1_we + | ex2_cpcr2_we | ex2_cpcr3_we | ex2_cpcr4_we + | ex2_cpcr5_we | ex2_dac1_we | ex2_dac2_we + | ex2_dac3_we | ex2_dac4_we | ex2_dbcr2_we + | ex2_dbcr3_we | ex2_dvc1_we | ex2_dvc2_we + | ex2_eheir_we | ex2_iac1_we | ex2_iac2_we + | ex2_iac3_we | ex2_iac4_we | ex2_immr_we + | ex2_imr_we | ex2_iucr0_we | ex2_iucr1_we + | ex2_iucr2_we | ex2_iudbg0_we | ex2_iulfsr_we + | ex2_iullcr_we | ex2_ivpr_we | ex2_lpidr_we + | ex2_lsucr0_we | ex2_mmucr0_we | ex2_mmucr1_we + | ex2_mmucr2_we | ex2_xucr2_we | ex2_xudbg0_we | + ex2_slowspr_range_hypv | + |(tspr_cspr_hypv_mtspr & ex2_tid)); + end + endgenerate + + generate + if (a2mode == 1 & hvmode == 1) + begin : ill_spr_11 + assign ex2_illeg_mfspr = ex2_is_mfspr_q & ~( + ex2_ccr0_rdec | ex2_ccr1_rdec | ex2_ccr2_rdec + | ex2_ccr4_rdec | ex2_cir_rdec | ex2_pir_rdec + | ex2_pvr_rdec | ex2_tb_rdec | ex2_tbu_rdec + | ex2_tenc_rdec | ex2_tens_rdec | ex2_tensr_rdec + | ex2_tir_rdec | ex2_xesr1_rdec | ex2_xesr2_rdec + | ex2_xucr0_rdec | ex2_xucr4_rdec | + ex2_gsprg0_rdec | ex2_gsprg1_rdec | ex2_gsprg2_rdec + | ex2_gsprg3_rdec | ex2_sprg0_rdec | ex2_sprg1_rdec + | ex2_sprg2_rdec | ex2_sprg3_rdec | ex2_sprg4_rdec + | ex2_sprg5_rdec | ex2_sprg6_rdec | ex2_sprg7_rdec + | ex2_sprg8_rdec | ex2_vrsave_rdec | + ex2_acop_rdec | ex2_axucr0_rdec | ex2_cpcr0_rdec + | ex2_cpcr1_rdec | ex2_cpcr2_rdec | ex2_cpcr3_rdec + | ex2_cpcr4_rdec | ex2_cpcr5_rdec | ex2_dac1_rdec + | ex2_dac2_rdec | ex2_dac3_rdec | ex2_dac4_rdec + | ex2_dbcr2_rdec | ex2_dbcr3_rdec | ex2_dscr_rdec + | ex2_dvc1_rdec | ex2_dvc2_rdec | ex2_eheir_rdec + | ex2_eplc_rdec | ex2_epsc_rdec | ex2_eptcfg_rdec + | ex2_givpr_rdec | ex2_hacop_rdec | ex2_iac1_rdec + | ex2_iac2_rdec | ex2_iac3_rdec | ex2_iac4_rdec + | ex2_immr_rdec | ex2_imr_rdec | ex2_iucr0_rdec + | ex2_iucr1_rdec | ex2_iucr2_rdec | ex2_iudbg0_rdec + | ex2_iudbg1_rdec | ex2_iudbg2_rdec | ex2_iulfsr_rdec + | ex2_iullcr_rdec | ex2_ivpr_rdec | ex2_lesr1_rdec + | ex2_lesr2_rdec | ex2_lper_rdec | ex2_lperu_rdec + | ex2_lpidr_rdec | ex2_lratcfg_rdec | ex2_lratps_rdec + | ex2_lsucr0_rdec | ex2_mas0_rdec | ex2_mas0_mas1_rdec + | ex2_mas1_rdec | ex2_mas2_rdec | ex2_mas2u_rdec + | ex2_mas3_rdec | ex2_mas4_rdec | ex2_mas5_rdec + | ex2_mas5_mas6_rdec | ex2_mas6_rdec | ex2_mas7_rdec + | ex2_mas7_mas3_rdec | ex2_mas8_rdec | ex2_mas8_mas1_rdec + | ex2_mmucfg_rdec | ex2_mmucr0_rdec | ex2_mmucr1_rdec + | ex2_mmucr2_rdec | ex2_mmucr3_rdec | ex2_mmucsr0_rdec + | ex2_pesr_rdec | ex2_pid_rdec | ex2_ppr32_rdec + | ex2_sramd_rdec | ex2_tlb0cfg_rdec | ex2_tlb0ps_rdec + | ex2_xucr2_rdec | ex2_xudbg0_rdec | ex2_xudbg1_rdec + | ex2_xudbg2_rdec | + ex2_slowspr_range | + |(tspr_cspr_illeg_mfspr_b & ex2_tid)); + + assign ex2_illeg_mtspr = ex2_is_mtspr_q & ~( + ex2_ccr0_wdec | ex2_ccr1_wdec | ex2_ccr2_wdec + | ex2_ccr4_wdec | ex2_tbl_wdec | ex2_tbu_wdec + | ex2_tenc_wdec | ex2_tens_wdec | ex2_trace_wdec + | ex2_xesr1_wdec | ex2_xesr2_wdec | ex2_xucr0_wdec + | ex2_xucr4_wdec | + ex2_gsprg0_wdec | ex2_gsprg1_wdec | ex2_gsprg2_wdec + | ex2_gsprg3_wdec | ex2_sprg0_wdec | ex2_sprg1_wdec + | ex2_sprg2_wdec | ex2_sprg3_wdec | ex2_sprg4_wdec + | ex2_sprg5_wdec | ex2_sprg6_wdec | ex2_sprg7_wdec + | ex2_sprg8_wdec | ex2_vrsave_wdec | + ex2_acop_wdec | ex2_axucr0_wdec | ex2_cpcr0_wdec + | ex2_cpcr1_wdec | ex2_cpcr2_wdec | ex2_cpcr3_wdec + | ex2_cpcr4_wdec | ex2_cpcr5_wdec | ex2_dac1_wdec + | ex2_dac2_wdec | ex2_dac3_wdec | ex2_dac4_wdec + | ex2_dbcr2_wdec | ex2_dbcr3_wdec | ex2_dscr_wdec + | ex2_dvc1_wdec | ex2_dvc2_wdec | ex2_eheir_wdec + | ex2_eplc_wdec | ex2_epsc_wdec | ex2_givpr_wdec + | ex2_hacop_wdec | ex2_iac1_wdec | ex2_iac2_wdec + | ex2_iac3_wdec | ex2_iac4_wdec | ex2_immr_wdec + | ex2_imr_wdec | ex2_iucr0_wdec | ex2_iucr1_wdec + | ex2_iucr2_wdec | ex2_iudbg0_wdec | ex2_iulfsr_wdec + | ex2_iullcr_wdec | ex2_ivpr_wdec | ex2_lesr1_wdec + | ex2_lesr2_wdec | ex2_lper_wdec | ex2_lperu_wdec + | ex2_lpidr_wdec | ex2_lsucr0_wdec | ex2_mas0_wdec + | ex2_mas0_mas1_wdec | ex2_mas1_wdec | ex2_mas2_wdec + | ex2_mas2u_wdec | ex2_mas3_wdec | ex2_mas4_wdec + | ex2_mas5_wdec | ex2_mas5_mas6_wdec | ex2_mas6_wdec + | ex2_mas7_wdec | ex2_mas7_mas3_wdec | ex2_mas8_wdec + | ex2_mas8_mas1_wdec | ex2_mmucr0_wdec | ex2_mmucr1_wdec + | ex2_mmucr2_wdec | ex2_mmucr3_wdec | ex2_mmucsr0_wdec + | ex2_pesr_wdec | ex2_pid_wdec | ex2_ppr32_wdec + | ex2_xucr2_wdec | ex2_xudbg0_wdec | + ex2_slowspr_range | + |(tspr_cspr_illeg_mtspr_b & ex2_tid)); + + assign ex2_hypv_mfspr = ex2_is_mfspr_q & ( + ex2_ccr0_re | ex2_ccr1_re | ex2_ccr2_re + | ex2_ccr4_re | ex2_tenc_re | ex2_tens_re + | ex2_tensr_re | ex2_tir_re | ex2_xucr0_re + | ex2_xucr4_re | + ex2_sprg8_re | + ex2_axucr0_re | ex2_cpcr0_re | ex2_cpcr1_re + | ex2_cpcr2_re | ex2_cpcr3_re | ex2_cpcr4_re + | ex2_cpcr5_re | ex2_dac1_re | ex2_dac2_re + | ex2_dac3_re | ex2_dac4_re | ex2_dbcr2_re + | ex2_dbcr3_re | ex2_dvc1_re | ex2_dvc2_re + | ex2_eheir_re | ex2_eptcfg_re | ex2_iac1_re + | ex2_iac2_re | ex2_iac3_re | ex2_iac4_re + | ex2_immr_re | ex2_imr_re | ex2_iucr0_re + | ex2_iucr1_re | ex2_iucr2_re | ex2_iudbg0_re + | ex2_iudbg1_re | ex2_iudbg2_re | ex2_iulfsr_re + | ex2_iullcr_re | ex2_ivpr_re | ex2_lper_re + | ex2_lperu_re | ex2_lpidr_re | ex2_lratcfg_re + | ex2_lratps_re | ex2_lsucr0_re | ex2_mas5_re + | ex2_mas5_mas6_re | ex2_mas8_re | ex2_mas8_mas1_re + | ex2_mmucfg_re | ex2_mmucr0_re | ex2_mmucr1_re + | ex2_mmucr2_re | ex2_mmucsr0_re | ex2_tlb0cfg_re + | ex2_tlb0ps_re | ex2_xucr2_re | ex2_xudbg0_re + | ex2_xudbg1_re | ex2_xudbg2_re | + ex2_slowspr_range_hypv | + |(tspr_cspr_hypv_mfspr & ex2_tid)); + + assign ex2_hypv_mtspr = ex2_is_mtspr_q & ( + ex2_ccr0_we | ex2_ccr1_we | ex2_ccr2_we + | ex2_ccr4_we | ex2_tbl_we | ex2_tbu_we + | ex2_tenc_we | ex2_tens_we | ex2_xucr0_we + | ex2_xucr4_we | + ex2_sprg8_we | + ex2_axucr0_we | ex2_cpcr0_we | ex2_cpcr1_we + | ex2_cpcr2_we | ex2_cpcr3_we | ex2_cpcr4_we + | ex2_cpcr5_we | ex2_dac1_we | ex2_dac2_we + | ex2_dac3_we | ex2_dac4_we | ex2_dbcr2_we + | ex2_dbcr3_we | ex2_dvc1_we | ex2_dvc2_we + | ex2_eheir_we | ex2_givpr_we | ex2_hacop_we + | ex2_iac1_we | ex2_iac2_we | ex2_iac3_we + | ex2_iac4_we | ex2_immr_we | ex2_imr_we + | ex2_iucr0_we | ex2_iucr1_we | ex2_iucr2_we + | ex2_iudbg0_we | ex2_iulfsr_we | ex2_iullcr_we + | ex2_ivpr_we | ex2_lper_we | ex2_lperu_we + | ex2_lpidr_we | ex2_lsucr0_we | ex2_mas5_we + | ex2_mas5_mas6_we | ex2_mas8_we | ex2_mas8_mas1_we + | ex2_mmucr0_we | ex2_mmucr1_we | ex2_mmucr2_we + | ex2_mmucsr0_we | ex2_xucr2_we | ex2_xudbg0_we | + ex2_slowspr_range_hypv | + |(tspr_cspr_hypv_mtspr & ex2_tid)); + end + endgenerate + + assign ex1_dnh = ex1_valid & ex1_is_dnh & spr_ccr4_en_dnh; + + assign ex3_wait_flush_d = |ex2_wait_flush; + + assign ex2_np1_flush = (ex2_ccr0_flush | ex2_tenc_flush | ex2_xucr0_flush) & ex2_tid; + + assign ex3_np1_flush_d = (|tspr_cspr_ex2_np1_flush) | |(ex2_np1_flush) | ex2_dnh_q | (ex2_is_mtspr_q & (ex2_ccr2_wdec | ex2_cpcr0_wdec | ex2_cpcr1_wdec | ex2_cpcr2_wdec | ex2_cpcr3_wdec | ex2_cpcr4_wdec | ex2_cpcr5_wdec |ex2_pid_wdec | ex2_lpidr_wdec | ex2_mmucr1_wdec | ex2_xucr0_wdec | ex2_iucr2_wdec | ex2_mmucsr0_wdec)) | ex2_is_mtmsr_q; + + assign ex4_np1_flush_d = ex3_spr_we & ex3_np1_flush_q; + assign ex4_wait_flush_d = ex3_spr_we & ex3_wait_flush_q; + + assign ex2_msr_pr = |(ex2_tid & tspr_msr_pr); + assign ex2_msr_gs = |(ex2_tid & tspr_msr_gs); + + assign ex3_hypv_spr_d = (ex2_val_rd_q | ex2_val_wr_q) & (~ex2_msr_pr) & ex2_msr_gs & (ex2_hypv_mfspr | ex2_hypv_mtspr | ex2_hypv_instr_q); + + assign ex3_illeg_spr_d = (ex2_val_rd_q | ex2_val_wr_q) & (((ex2_illeg_mfspr | ex2_illeg_mtspr | ex2_illeg_mftb) & ~(ex2_instr_q[11] & ex2_msr_pr)) | (ex2_hypv_instr_q & ~spr_ccr2_en_pc)); + + assign ex3_priv_spr_d = (ex2_val_rd_q | ex2_val_wr_q) & ex2_msr_pr & ((ex2_instr_q[11] & (ex2_is_mtspr_q | ex2_is_mfspr_q)) | ex2_priv_instr_q); + + assign spr_ccr0_pme = ccr0_q[62:63]; + assign spr_ccr0_we = ccr0_we; + assign spr_ccr2_en_dcr = spr_ccr2_en_dcr_int; + assign spr_ccr2_en_dcr_int = ccr2_q[32]; + assign spr_ccr2_en_trace = ccr2_q[33]; + assign spr_ccr2_en_pc = ccr2_q[34]; + assign spr_ccr2_ifratsc = ccr2_q[35:43]; + assign spr_ccr2_ifrat = ccr2_q[44]; + assign spr_ccr2_dfratsc = ccr2_q[45:53]; + assign spr_ccr2_dfrat = ccr2_q[54]; + assign spr_ccr2_ucode_dis = ccr2_q[55]; + assign spr_ccr2_ap = ccr2_q[56:59]; + assign spr_ccr2_en_attn = ccr2_q[60]; + assign spr_ccr2_en_ditc = ccr2_q[61]; + assign spr_ccr2_en_icswx = ccr2_q[62]; + assign spr_ccr2_notlb = ccr2_q[63]; + assign spr_ccr4_en_dnh = ccr4_q[63]; + assign spr_tens_ten = tens_q[64-(`THREADS):63]; + assign spr_xucr0_clkg_ctl = xucr0_q[38:42]; + assign spr_xucr0_trace_um = xucr0_q[43:46]; + assign xu_lsu_spr_xucr0_mbar_ack = xucr0_q[47]; + assign xu_lsu_spr_xucr0_tlbsync = xucr0_q[48]; + assign spr_xucr0_cls = xucr0_q[49]; + assign xu_lsu_spr_xucr0_aflsta = xucr0_q[50]; + assign spr_xucr0_mddp = xucr0_q[51]; + assign xu_lsu_spr_xucr0_cred = xucr0_q[52]; + assign xu_lsu_spr_xucr0_rel = xucr0_q[53]; + assign spr_xucr0_mdcp = xucr0_q[54]; + assign spr_xucr0_tcs = xucr0_q[55]; + assign xu_lsu_spr_xucr0_flsta = xucr0_q[56]; + assign xu_lsu_spr_xucr0_l2siw = xucr0_q[57]; + assign xu_lsu_spr_xucr0_flh2l2 = xucr0_q[58]; + assign xu_lsu_spr_xucr0_dcdis = xucr0_q[59]; + assign xu_lsu_spr_xucr0_wlk = xucr0_q[60]; + assign spr_xucr4_mmu_mchk = xucr4_q[60]; + assign spr_xucr4_mddmh = xucr4_q[61]; + assign spr_xucr4_tcd = xucr4_q[62:63]; + assign xucr0_clfc_d = ex3_xucr0_we & ex3_spr_wd[63]; + assign xu_lsu_spr_xucr0_clfc = xucr0_clfc_q; + assign cspr_ccr2_en_pc = spr_ccr2_en_pc; + assign cspr_ccr4_en_dnh = spr_ccr4_en_dnh; + + // CCR0 + assign ex3_ccr0_di = { ex3_spr_wd[32:33] }; //PME + + assign ccr0_do = { tidn[0:0] , + tidn[0:31] , ///// + ccr0_q[62:63] , //PME + tidn[34:51] , ///// + 4'b0000 , //WEM + tidn[56:59] , ///// + ccr0_we }; //WE + // CCR1 + assign ex3_ccr1_di = { ex3_spr_wd[34:39] , //WC3 + ex3_spr_wd[42:47] , //WC2 + ex3_spr_wd[50:55] , //WC1 + ex3_spr_wd[58:63] }; //WC0 + + assign ccr1_do = { tidn[0:0] , + tidn[0:31] , ///// + tidn[32:33] , ///// + ccr1_q[40:45] , //WC3 + tidn[40:41] , ///// + ccr1_q[46:51] , //WC2 + tidn[48:49] , ///// + ccr1_q[52:57] , //WC1 + tidn[56:57] , ///// + ccr1_q[58:63] }; //WC0 + // CCR2 + assign ex3_ccr2_di = { ex3_spr_wd[32:32] , //EN_DCR + ex3_spr_wd[33:33] , //EN_TRACE + ex3_spr_wd[34:34] , //EN_PC + ex3_spr_wd[35:43] , //IFRATSC + ex3_spr_wd[44:44] , //IFRAT + ex3_spr_wd[45:53] , //DFRATSC + ex3_spr_wd[54:54] , //DFRAT + ex3_spr_wd[55:55] , //UCODE_DIS + ex3_spr_wd[56:59] , //AP + ex3_spr_wd[60:60] , //EN_ATTN + ex3_spr_wd[61:61] , //EN_DITC + ex3_spr_wd[62:62] , //EN_ICSWX + ex3_spr_wd[63:63] }; //NOTLB + + assign ccr2_do = { tidn[0:0] , + tidn[0:31] , ///// + ccr2_q[32:32] , //EN_DCR + ccr2_q[33:33] , //EN_TRACE + ccr2_q[34:34] , //EN_PC + ccr2_q[35:43] , //IFRATSC + ccr2_q[44:44] , //IFRAT + ccr2_q[45:53] , //DFRATSC + ccr2_q[54:54] , //DFRAT + ccr2_q[55:55] , //UCODE_DIS + ccr2_q[56:59] , //AP + ccr2_q[60:60] , //EN_ATTN + ccr2_q[61:61] , //EN_DITC + ccr2_q[62:62] , //EN_ICSWX + ccr2_q[63:63] }; //NOTLB + // CCR4 + assign ex3_ccr4_di = { ex3_spr_wd[63:63] }; //EN_DNH + + assign ccr4_do = { tidn[0:0] , + tidn[0:31] , ///// + tidn[32:62] , ///// + ccr4_q[63:63] }; //EN_DNH + // CIR + assign cir_do = { tidn[0:0] , + tidn[0:31] , ///// + an_ac_chipid_dc[32:35] , //ID + tidn[36:63] }; ///// + // PIR + assign pir_do = { tidn[0:0] , + tidn[0:31] , ///// + tidn[32:53] , ///// + an_ac_coreid_q[54:61] , //CID + ex2_tid_q[0:1] }; //TID + // PVR + assign pvr_do = { tidn[0:0] , + tidn[0:31] , ///// + version[32:47] , //VERSION + revision[48:63] }; //REVISION + // TB + assign tb_do = { tidn[0:0] , + tbu_q[32:63] , //TBU + tbl_q[32:63] }; //TBL + // TBL + assign ex3_tbl_di = { ex3_spr_wd[32:63] }; //TBL + + assign tbl_do = { tidn[0:0] , + tidn[0:31] , ///// + tbl_q[32:63] }; //TBL + // TBU + assign ex3_tbu_di = { ex3_spr_wd[32:63] }; //TBU + + assign tbu_do = { tidn[0:0] , + tidn[0:31] , ///// + tbu_q[32:63] }; //TBU + // TENC + assign tenc_do = { tidn[0:64-`THREADS] , + tens_q[64-`THREADS:63] }; //TEN + // TENS + assign ex3_tens_di = { ex3_spr_wd[64-(`THREADS):63] }; //TEN + + assign tens_do = { tidn[0:64-(`THREADS)] , + tens_q[64-(`THREADS):63] }; //TEN + // TENSR + assign tensr_do = { tidn[0:64-`THREADS] , + spr_tensr[0:`THREADS-1] }; //TENSR + // TIR + assign tir_do = { tidn[0:0] , + tidn[0:31] , ///// + tidn[32:61] , ///// + ex2_tid_q[0:1] }; //TID + // XESR1 + assign ex3_xesr1_di = { ex3_spr_wd[32:35] , //MUXSELEB0 + ex3_spr_wd[36:39] , //MUXSELEB1 + ex3_spr_wd[40:43] , //MUXSELEB2 + ex3_spr_wd[44:47] , //MUXSELEB3 + ex3_spr_wd[48:51] , //MUXSELEB4 + ex3_spr_wd[52:55] , //MUXSELEB5 + ex3_spr_wd[56:59] , //MUXSELEB6 + ex3_spr_wd[60:63] }; //MUXSELEB7 + + assign xesr1_do = { tidn[0:0] , + tidn[0:31] , ///// + xesr1_q[32:35] , //MUXSELEB0 + xesr1_q[36:39] , //MUXSELEB1 + xesr1_q[40:43] , //MUXSELEB2 + xesr1_q[44:47] , //MUXSELEB3 + xesr1_q[48:51] , //MUXSELEB4 + xesr1_q[52:55] , //MUXSELEB5 + xesr1_q[56:59] , //MUXSELEB6 + xesr1_q[60:63] }; //MUXSELEB7 + // XESR2 + assign ex3_xesr2_di = { ex3_spr_wd[32:35] , //MUXSELEB0 + ex3_spr_wd[36:39] , //MUXSELEB1 + ex3_spr_wd[40:43] , //MUXSELEB2 + ex3_spr_wd[44:47] , //MUXSELEB3 + ex3_spr_wd[48:51] , //MUXSELEB4 + ex3_spr_wd[52:55] , //MUXSELEB5 + ex3_spr_wd[56:59] , //MUXSELEB6 + ex3_spr_wd[60:63] }; //MUXSELEB7 + + assign xesr2_do = { tidn[0:0] , + tidn[0:31] , ///// + xesr2_q[32:35] , //MUXSELEB0 + xesr2_q[36:39] , //MUXSELEB1 + xesr2_q[40:43] , //MUXSELEB2 + xesr2_q[44:47] , //MUXSELEB3 + xesr2_q[48:51] , //MUXSELEB4 + xesr2_q[52:55] , //MUXSELEB5 + xesr2_q[56:59] , //MUXSELEB6 + xesr2_q[60:63] }; //MUXSELEB7 + // XUCR0 + assign ex3_xucr0_di = { ex3_spr_wd[32:36] , //CLKG_CTL + ex3_spr_wd[37:40] , //TRACE_UM + ex3_spr_wd[41:41] , //MBAR_ACK + ex3_spr_wd[42:42] , //TLBSYNC + xucr0_q[49:49] , //CLS + ex3_spr_wd[49:49] , //AFLSTA + ex3_spr_wd[50:50] , //MDDP + ex3_spr_wd[51:51] , //CRED + xucr0_q[53:53] , //REL + ex3_spr_wd[53:53] , //MDCP + ex3_spr_wd[54:54] , //TCS + ex3_spr_wd[55:55] , //FLSTA + xucr0_q[57:57] , //L2SIW + xucr0_q[58:58] , //FLH2L2 + ex3_spr_wd[58:58] , //DCDIS + ex3_spr_wd[59:59] , //WLK + ex3_spr_wd[60:60] , //CSLC + ex3_spr_wd[61:61] , //CUL + ex3_spr_wd[62:62] }; //CLO + + assign xucr0_do = { tidn[0:0] , + tidn[0:31] , ///// + xucr0_q[38:42] , //CLKG_CTL + xucr0_q[43:46] , //TRACE_UM + xucr0_q[47:47] , //MBAR_ACK + xucr0_q[48:48] , //TLBSYNC + tidn[43:47] , ///// + xucr0_q[49:49] , //CLS + xucr0_q[50:50] , //AFLSTA + xucr0_q[51:51] , //MDDP + xucr0_q[52:52] , //CRED + xucr0_q[53:53] , //REL + xucr0_q[54:54] , //MDCP + xucr0_q[55:55] , //TCS + xucr0_q[56:56] , //FLSTA + xucr0_q[57:57] , //L2SIW + xucr0_q[58:58] , //FLH2L2 + xucr0_q[59:59] , //DCDIS + xucr0_q[60:60] , //WLK + xucr0_q[61:61] , //CSLC + xucr0_q[62:62] , //CUL + xucr0_q[63:63] , //CLO + 1'b0 }; //CLFC + // XUCR4 + assign ex3_xucr4_di = { ex3_spr_wd[46:46] , //MMU_MCHK + ex3_spr_wd[47:47] , //MDDMH + ex3_spr_wd[56:57] }; //TCD + + assign xucr4_do = { tidn[0:0] , + tidn[0:31] , ///// + tidn[32:45] , ///// + xucr4_q[60:60] , //MMU_MCHK + xucr4_q[61:61] , //MDDMH + tidn[48:55] , ///// + xucr4_q[62:63] , //TCD + tidn[58:63] }; ///// + + // Unused Signals + assign unused_do_bits = |{ + ccr0_do[0:64-`GPR_WIDTH] + ,ccr1_do[0:64-`GPR_WIDTH] + ,ccr2_do[0:64-`GPR_WIDTH] + ,ccr4_do[0:64-`GPR_WIDTH] + ,cir_do[0:64-`GPR_WIDTH] + ,pir_do[0:64-`GPR_WIDTH] + ,pvr_do[0:64-`GPR_WIDTH] + ,tb_do[0:64-`GPR_WIDTH] + ,tbl_do[0:64-`GPR_WIDTH] + ,tbu_do[0:64-`GPR_WIDTH] + ,tenc_do[0:64-`GPR_WIDTH] + ,tens_do[0:64-`GPR_WIDTH] + ,tensr_do[0:64-`GPR_WIDTH] + ,tir_do[0:64-`GPR_WIDTH] + ,xesr1_do[0:64-`GPR_WIDTH] + ,xesr2_do[0:64-`GPR_WIDTH] + ,xucr0_do[0:64-`GPR_WIDTH] + ,xucr4_do[0:64-`GPR_WIDTH] + }; + + tri_ser_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ccr0_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(ccr0_act), + .force_t(bcfg_slp_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(bcfg_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv_bcfg[ccr0_offset_bcfg:ccr0_offset_bcfg + 2 - 1]), + .scout(sov_bcfg[ccr0_offset_bcfg:ccr0_offset_bcfg + 2 - 1]), + .din(ccr0_d), + .dout(ccr0_q) + ); + tri_ser_rlmreg_p #(.WIDTH(24), .INIT(3994575), .NEEDS_SRESET(1)) ccr1_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(ccr1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ccr1_offset:ccr1_offset + 24 - 1]), + .scout(sov[ccr1_offset:ccr1_offset + 24 - 1]), + .din(ccr1_d), + .dout(ccr1_q) + ); + tri_ser_rlmreg_p #(.WIDTH(32), .INIT(1), .NEEDS_SRESET(1)) ccr2_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(ccr2_act), + .force_t(ccfg_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(ccfg_sl_thold_0_b), + .sg(sg_0), + .scin(siv_ccfg[ccr2_offset_ccfg:ccr2_offset_ccfg + 32 - 1]), + .scout(sov_ccfg[ccr2_offset_ccfg:ccr2_offset_ccfg + 32 - 1]), + .din(ccr2_d), + .dout(ccr2_q) + ); + tri_ser_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ccr4_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(ccr4_act), + .force_t(ccfg_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(ccfg_sl_thold_0_b), + .sg(sg_0), + .scin(siv_ccfg[ccr4_offset_ccfg:ccr4_offset_ccfg + 1 - 1]), + .scout(sov_ccfg[ccr4_offset_ccfg:ccr4_offset_ccfg + 1 - 1]), + .din(ccr4_d), + .dout(ccr4_q) + ); + tri_ser_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) tbl_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(tbl_act), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[tbl_offset:tbl_offset + 32 - 1]), + .scout(sov[tbl_offset:tbl_offset + 32 - 1]), + .din(tbl_d), + .dout(tbl_q) + ); + tri_ser_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) tbu_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(tbu_act), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[tbu_offset:tbu_offset + 32 - 1]), + .scout(sov[tbu_offset:tbu_offset + 32 - 1]), + .din(tbu_d), + .dout(tbu_q) + ); + tri_ser_rlmreg_p #(.WIDTH(`THREADS), .INIT(1), .NEEDS_SRESET(1)) tens_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(tens_act), + .force_t(bcfg_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(bcfg_sl_thold_0_b), + .sg(sg_0), + .scin(siv_bcfg[tens_offset_bcfg:tens_offset_bcfg + `THREADS - 1]), + .scout(sov_bcfg[tens_offset_bcfg:tens_offset_bcfg + `THREADS - 1]), + .din(tens_d), + .dout(tens_q) + ); + tri_ser_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) xesr1_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(xesr1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[xesr1_offset:xesr1_offset + 32 - 1]), + .scout(sov[xesr1_offset:xesr1_offset + 32 - 1]), + .din(xesr1_d), + .dout(xesr1_q) + ); + tri_ser_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) xesr2_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(xesr2_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[xesr2_offset:xesr2_offset + 32 - 1]), + .scout(sov[xesr2_offset:xesr2_offset + 32 - 1]), + .din(xesr2_d), + .dout(xesr2_q) + ); + tri_ser_rlmreg_p #(.WIDTH(26), .INIT((spr_xucr0_init)), .NEEDS_SRESET(1)) xucr0_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(xucr0_act), + .force_t(ccfg_slp_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(ccfg_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv_ccfg[xucr0_offset_ccfg:xucr0_offset_ccfg + 26 - 1]), + .scout(sov_ccfg[xucr0_offset_ccfg:xucr0_offset_ccfg + 26 - 1]), + .din(xucr0_d), + .dout(xucr0_q) + ); + tri_ser_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) xucr4_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(xucr4_act), + .force_t(dcfg_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(dcfg_sl_thold_0_b), + .sg(sg_0), + .scin(siv_dcfg[xucr4_offset_dcfg:xucr4_offset_dcfg + 4 - 1]), + .scout(sov_dcfg[xucr4_offset_dcfg:xucr4_offset_dcfg + 4 - 1]), + .din(xucr4_d), + .dout(xucr4_q) + ); + + + + // Latch Instances + tri_rlmreg_p #(.WIDTH(4), .OFFSET(1),.INIT(0), .NEEDS_SRESET(1)) exx_act_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[exx_act_offset : exx_act_offset + 4-1]), + .scout(sov[exx_act_offset : exx_act_offset + 4-1]), + .din(exx_act_d), + .dout(exx_act_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex0_val_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX0]), + .mpw1_b(mpw1_dc_b[DEX0]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex0_val_offset : ex0_val_offset + `THREADS-1]), + .scout(sov[ex0_val_offset : ex0_val_offset + `THREADS-1]), + .din(rv2_val), + .dout(ex0_val_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_val_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_val_offset : ex1_val_offset + `THREADS-1]), + .scout(sov[ex1_val_offset : ex1_val_offset + `THREADS-1]), + .din(ex0_val), + .dout(ex1_val_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_aspr_act_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_aspr_act_offset]), + .scout(sov[ex1_aspr_act_offset]), + .din(ex1_aspr_act_d), + .dout(ex1_aspr_act_q) + ); + tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_aspr_tid_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_aspr_tid_offset : ex1_aspr_tid_offset + 2-1]), + .scout(sov[ex1_aspr_tid_offset : ex1_aspr_tid_offset + 2-1]), + .din(ex1_aspr_tid_d), + .dout(ex1_aspr_tid_q) + ); + tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_tid_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_tid_offset : ex1_tid_offset + 2-1]), + .scout(sov[ex1_tid_offset : ex1_tid_offset + 2-1]), + .din(ex0_tid), + .dout(ex1_tid_q) + ); + tri_rlmreg_p #(.WIDTH(32), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_instr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_instr_offset : ex1_instr_offset + 32-1]), + .scout(sov[ex1_instr_offset : ex1_instr_offset + 32-1]), + .din(rv_xu_ex0_instr), + .dout(ex1_instr_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_msr_gs_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_msr_gs_offset]), + .scout(sov[ex1_msr_gs_offset]), + .din(ex1_msr_gs_d), + .dout(ex1_msr_gs_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_val_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_val_offset : ex2_val_offset + `THREADS-1]), + .scout(sov[ex2_val_offset : ex2_val_offset + `THREADS-1]), + .din(ex1_val), + .dout(ex2_val_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_val_rd_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_val_rd_offset]), + .scout(sov[ex2_val_rd_offset]), + .din(ex2_val_rd_d), + .dout(ex2_val_rd_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_val_wr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_val_wr_offset]), + .scout(sov[ex2_val_wr_offset]), + .din(ex2_val_wr_d), + .dout(ex2_val_wr_q) + ); + tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_tid_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_tid_offset : ex2_tid_offset + 2-1]), + .scout(sov[ex2_tid_offset : ex2_tid_offset + 2-1]), + .din(ex1_tid_q), + .dout(ex2_tid_q) + ); + tri_rlmreg_p #(.WIDTH(4), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_aspr_addr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_aspr_addr_offset : ex2_aspr_addr_offset + 4-1]), + .scout(sov[ex2_aspr_addr_offset : ex2_aspr_addr_offset + 4-1]), + .din(ex1_aspr_addr), + .dout(ex2_aspr_addr_q) + ); + tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_is_mfspr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_is_mfspr_offset]), + .scout(sov[ex2_is_mfspr_offset]), + .din(ex1_is_mfspr), + .dout(ex2_is_mfspr_q) + ); + tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_is_mftb_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_is_mftb_offset]), + .scout(sov[ex2_is_mftb_offset]), + .din(ex1_is_mftb), + .dout(ex2_is_mftb_q) + ); + tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_is_mtmsr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_is_mtmsr_offset]), + .scout(sov[ex2_is_mtmsr_offset]), + .din(ex2_is_mtmsr_d), + .dout(ex2_is_mtmsr_q) + ); + tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_is_mtspr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_is_mtspr_offset]), + .scout(sov[ex2_is_mtspr_offset]), + .din(ex1_is_mtspr), + .dout(ex2_is_mtspr_q) + ); + tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_is_wait_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_is_wait_offset]), + .scout(sov[ex2_is_wait_offset]), + .din(ex1_is_wait), + .dout(ex2_is_wait_q) + ); + tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_priv_instr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_priv_instr_offset]), + .scout(sov[ex2_priv_instr_offset]), + .din(ex1_priv_instr), + .dout(ex2_priv_instr_q) + ); + tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_hypv_instr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_hypv_instr_offset]), + .scout(sov[ex2_hypv_instr_offset]), + .din(ex1_hypv_instr), + .dout(ex2_hypv_instr_q) + ); + tri_regk #(.WIDTH(2), .OFFSET(9),.INIT(0), .NEEDS_SRESET(1)) ex2_wait_wc_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_wait_wc_offset : ex2_wait_wc_offset + 2-1]), + .scout(sov[ex2_wait_wc_offset : ex2_wait_wc_offset + 2-1]), + .din(ex1_instr_q[9:10]), + .dout(ex2_wait_wc_q) + ); + tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_is_msgclr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_is_msgclr_offset]), + .scout(sov[ex2_is_msgclr_offset]), + .din(ex1_is_msgclr), + .dout(ex2_is_msgclr_q) + ); + tri_regk #(.WIDTH(10), .OFFSET(11),.INIT(0), .NEEDS_SRESET(1)) ex2_instr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_instr_offset : ex2_instr_offset + 10-1]), + .scout(sov[ex2_instr_offset : ex2_instr_offset + 10-1]), + .din(ex2_instr_d), + .dout(ex2_instr_q) + ); + tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_msr_gs_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_msr_gs_offset]), + .scout(sov[ex2_msr_gs_offset]), + .din(ex1_msr_gs_q), + .dout(ex2_msr_gs_q) + ); + tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_tenc_we_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_tenc_we_offset]), + .scout(sov[ex2_tenc_we_offset]), + .din(ex1_tenc_we), + .dout(ex2_tenc_we_q) + ); + tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_ccr0_we_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_ccr0_we_offset]), + .scout(sov[ex2_ccr0_we_offset]), + .din(ex1_ccr0_we), + .dout(ex2_ccr0_we_q) + ); + tri_regk #(.WIDTH(`GPR_WIDTH/32), .OFFSET(2-`GPR_WIDTH/32),.INIT(0), .NEEDS_SRESET(1)) ex2_aspr_re_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_aspr_re_offset : ex2_aspr_re_offset + `GPR_WIDTH/32-1]), + .scout(sov[ex2_aspr_re_offset : ex2_aspr_re_offset + `GPR_WIDTH/32-1]), + .din(ex1_aspr_re), + .dout(ex2_aspr_re_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_dnh_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_dnh_offset]), + .scout(sov[ex2_dnh_offset]), + .din(ex1_dnh), + .dout(ex2_dnh_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex3_val_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex3_val_offset : ex3_val_offset + `THREADS-1]), + .scout(sov[ex3_val_offset : ex3_val_offset + `THREADS-1]), + .din(ex2_val), + .dout(ex3_val_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_val_rd_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_val_rd_offset]), + .scout(sov[ex3_val_rd_offset]), + .din(ex3_val_rd_d), + .dout(ex3_val_rd_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_sspr_wr_val_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_sspr_wr_val_offset]), + .scout(sov[ex3_sspr_wr_val_offset]), + .din(ex2_sspr_wr_val), + .dout(ex3_sspr_wr_val_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_sspr_rd_val_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_sspr_rd_val_offset]), + .scout(sov[ex3_sspr_rd_val_offset]), + .din(ex2_sspr_rd_val), + .dout(ex3_sspr_rd_val_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_spr_we_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_spr_we_offset]), + .scout(sov[ex3_spr_we_offset]), + .din(ex3_spr_we_d), + .dout(ex3_spr_we_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_aspr_we_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_aspr_we_offset]), + .scout(sov[ex3_aspr_we_offset]), + .din(ex3_aspr_we_d), + .dout(ex3_aspr_we_q) + ); + tri_rlmreg_p #(.WIDTH(4), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex3_aspr_addr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ex2_aspr_addr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex3_aspr_addr_offset : ex3_aspr_addr_offset + 4-1]), + .scout(sov[ex3_aspr_addr_offset : ex3_aspr_addr_offset + 4-1]), + .din(ex3_aspr_addr_d), + .dout(ex3_aspr_addr_q) + ); + tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex3_tid_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex3_tid_offset : ex3_tid_offset + 2-1]), + .scout(sov[ex3_tid_offset : ex3_tid_offset + 2-1]), + .din(ex2_tid_q), + .dout(ex3_tid_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+8), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex3_aspr_rdata_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act_data[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex3_aspr_rdata_offset : ex3_aspr_rdata_offset + `GPR_WIDTH+8-1]), + .scout(sov[ex3_aspr_rdata_offset : ex3_aspr_rdata_offset + `GPR_WIDTH+8-1]), + .din(ex3_aspr_rdata_d), + .dout(ex3_aspr_rdata_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_is_mtspr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_is_mtspr_offset]), + .scout(sov[ex3_is_mtspr_offset]), + .din(ex2_is_mtspr_q), + .dout(ex3_is_mtspr_q) + ); + tri_rlmreg_p #(.WIDTH(2), .OFFSET(9),.INIT(0), .NEEDS_SRESET(1)) ex3_wait_wc_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex3_wait_wc_offset : ex3_wait_wc_offset + 2-1]), + .scout(sov[ex3_wait_wc_offset : ex3_wait_wc_offset + 2-1]), + .din(ex2_wait_wc_q), + .dout(ex3_wait_wc_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_is_msgclr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_is_msgclr_offset]), + .scout(sov[ex3_is_msgclr_offset]), + .din(ex2_is_msgclr_q), + .dout(ex3_is_msgclr_q) + ); + tri_rlmreg_p #(.WIDTH(10), .OFFSET(11),.INIT(0), .NEEDS_SRESET(1)) ex3_instr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex3_instr_offset : ex3_instr_offset + 10-1]), + .scout(sov[ex3_instr_offset : ex3_instr_offset + 10-1]), + .din(ex3_instr_d), + .dout(ex3_instr_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex3_cspr_rt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act_data[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex3_cspr_rt_offset : ex3_cspr_rt_offset + `GPR_WIDTH-1]), + .scout(sov[ex3_cspr_rt_offset : ex3_cspr_rt_offset + `GPR_WIDTH-1]), + .din(ex2_cspr_rt), + .dout(ex3_cspr_rt_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_hypv_spr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_hypv_spr_offset]), + .scout(sov[ex3_hypv_spr_offset]), + .din(ex3_hypv_spr_d), + .dout(ex3_hypv_spr_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_illeg_spr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_illeg_spr_offset]), + .scout(sov[ex3_illeg_spr_offset]), + .din(ex3_illeg_spr_d), + .dout(ex3_illeg_spr_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_priv_spr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_priv_spr_offset]), + .scout(sov[ex3_priv_spr_offset]), + .din(ex3_priv_spr_d), + .dout(ex3_priv_spr_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+8), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex3_rt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ex3_rt_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex3_rt_offset : ex3_rt_offset + `GPR_WIDTH+8-1]), + .scout(sov[ex3_rt_offset : ex3_rt_offset + `GPR_WIDTH+8-1]), + .din(ex3_rt_d), + .dout(ex3_rt_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_wait_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_wait_offset]), + .scout(sov[ex3_wait_offset]), + .din(ex2_is_wait_q), + .dout(ex3_wait_q) + ); + tri_rlmreg_p #(.WIDTH(4), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex3_aspr_ce_addr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex3_aspr_ce_addr_offset : ex3_aspr_ce_addr_offset + 4-1]), + .scout(sov[ex3_aspr_ce_addr_offset : ex3_aspr_ce_addr_offset + 4-1]), + .din(ex2_aspr_addr_q), + .dout(ex3_aspr_ce_addr_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH/32), .OFFSET(2-`GPR_WIDTH/32),.INIT(0), .NEEDS_SRESET(1)) ex3_aspr_re_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex3_aspr_re_offset : ex3_aspr_re_offset + `GPR_WIDTH/32-1]), + .scout(sov[ex3_aspr_re_offset : ex3_aspr_re_offset + `GPR_WIDTH/32-1]), + .din(ex2_aspr_re_q), + .dout(ex3_aspr_re_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_val_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex4_val_offset : ex4_val_offset + `THREADS-1]), + .scout(sov[ex4_val_offset : ex4_val_offset + `THREADS-1]), + .din(ex3_val), + .dout(ex4_val_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH/32), .OFFSET(2-`GPR_WIDTH/32),.INIT(0), .NEEDS_SRESET(1)) ex4_aspr_re_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[3]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex4_aspr_re_offset : ex4_aspr_re_offset + `GPR_WIDTH/32-1]), + .scout(sov[ex4_aspr_re_offset : ex4_aspr_re_offset + `GPR_WIDTH/32-1]), + .din(ex3_aspr_re_q), + .dout(ex4_aspr_re_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex4_spr_rt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act_data[3]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex4_spr_rt_offset : ex4_spr_rt_offset + `GPR_WIDTH-1]), + .scout(sov[ex4_spr_rt_offset : ex4_spr_rt_offset + `GPR_WIDTH-1]), + .din(ex3_spr_rt), + .dout(ex4_spr_rt_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex4_corr_rdata_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act_data[3]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex4_corr_rdata_offset : ex4_corr_rdata_offset + `GPR_WIDTH-1]), + .scout(sov[ex4_corr_rdata_offset : ex4_corr_rdata_offset + `GPR_WIDTH-1]), + .din(ex3_corr_rdata), + .dout(ex4_corr_rdata_q) + ); + tri_regk #(.WIDTH(`GPR_WIDTH/8+1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_sprg_ce_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin (siv[ex4_sprg_ce_offset : ex4_sprg_ce_offset + `GPR_WIDTH/8+1-1]), + .scout(sov[ex4_sprg_ce_offset : ex4_sprg_ce_offset + `GPR_WIDTH/8+1-1]), + .din(ex4_sprg_ce_d), + .dout(ex4_sprg_ce_q) + ); + tri_regk #(.WIDTH(4), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_aspr_ce_addr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ex3_sprg_ce), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin (siv[ex4_aspr_ce_addr_offset : ex4_aspr_ce_addr_offset + 4-1]), + .scout(sov[ex4_aspr_ce_addr_offset : ex4_aspr_ce_addr_offset + 4-1]), + .din(ex3_aspr_ce_addr_q), + .dout(ex4_aspr_ce_addr_q) + ); + tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_hypv_spr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[3]), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_hypv_spr_offset]), + .scout(sov[ex4_hypv_spr_offset]), + .din(ex3_hypv_spr_q), + .dout(ex4_hypv_spr_q) + ); + tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_illeg_spr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[3]), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_illeg_spr_offset]), + .scout(sov[ex4_illeg_spr_offset]), + .din(ex3_illeg_spr_q), + .dout(ex4_illeg_spr_q) + ); + tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_priv_spr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[3]), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_priv_spr_offset]), + .scout(sov[ex4_priv_spr_offset]), + .din(ex3_priv_spr_q), + .dout(ex4_priv_spr_q) + ); + tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_np1_flush_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[3]), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_np1_flush_offset]), + .scout(sov[ex4_np1_flush_offset]), + .din(ex4_np1_flush_d), + .dout(ex4_np1_flush_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex5_sprg_ce_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), + .mpw1_b(mpw1_dc_b[DEX5]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex5_sprg_ce_offset : ex5_sprg_ce_offset + `THREADS-1]), + .scout(sov[ex5_sprg_ce_offset : ex5_sprg_ce_offset + `THREADS-1]), + .din(ex4_sprg_ce), + .dout(ex5_sprg_ce_q) + ); + tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_sprg_ue_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_sprg_ue_offset]), + .scout(sov[ex4_sprg_ue_offset]), + .din(ex4_sprg_ue_d), + .dout(ex4_sprg_ue_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex5_sprg_ue_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), + .mpw1_b(mpw1_dc_b[DEX5]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex5_sprg_ue_offset : ex5_sprg_ue_offset + `THREADS-1]), + .scout(sov[ex5_sprg_ue_offset : ex5_sprg_ue_offset + `THREADS-1]), + .din(ex4_sprg_ue), + .dout(ex5_sprg_ue_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) cpl_dbell_taken_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[cpl_dbell_taken_offset : cpl_dbell_taken_offset + `THREADS-1]), + .scout(sov[cpl_dbell_taken_offset : cpl_dbell_taken_offset + `THREADS-1]), + .din(iu_xu_dbell_taken), + .dout(cpl_dbell_taken_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) cpl_cdbell_taken_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[cpl_cdbell_taken_offset : cpl_cdbell_taken_offset + `THREADS-1]), + .scout(sov[cpl_cdbell_taken_offset : cpl_cdbell_taken_offset + `THREADS-1]), + .din(iu_xu_cdbell_taken), + .dout(cpl_cdbell_taken_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) cpl_gdbell_taken_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[cpl_gdbell_taken_offset : cpl_gdbell_taken_offset + `THREADS-1]), + .scout(sov[cpl_gdbell_taken_offset : cpl_gdbell_taken_offset + `THREADS-1]), + .din(iu_xu_gdbell_taken), + .dout(cpl_gdbell_taken_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) cpl_gcdbell_taken_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[cpl_gcdbell_taken_offset : cpl_gcdbell_taken_offset + `THREADS-1]), + .scout(sov[cpl_gcdbell_taken_offset : cpl_gcdbell_taken_offset + `THREADS-1]), + .din(iu_xu_gcdbell_taken), + .dout(cpl_gcdbell_taken_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) cpl_gmcdbell_taken_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[cpl_gmcdbell_taken_offset : cpl_gmcdbell_taken_offset + `THREADS-1]), + .scout(sov[cpl_gmcdbell_taken_offset : cpl_gmcdbell_taken_offset + `THREADS-1]), + .din(iu_xu_gmcdbell_taken), + .dout(cpl_gmcdbell_taken_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) set_xucr0_cslc_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[set_xucr0_cslc_offset]), + .scout(sov[set_xucr0_cslc_offset]), + .din(set_xucr0_cslc_d), + .dout(set_xucr0_cslc_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) set_xucr0_cul_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[set_xucr0_cul_offset]), + .scout(sov[set_xucr0_cul_offset]), + .din(set_xucr0_cul_d), + .dout(set_xucr0_cul_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) set_xucr0_clo_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[set_xucr0_clo_offset]), + .scout(sov[set_xucr0_clo_offset]), + .din(set_xucr0_clo_d), + .dout(set_xucr0_clo_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_np1_flush_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_np1_flush_offset]), + .scout(sov[ex3_np1_flush_offset]), + .din(ex3_np1_flush_d), + .dout(ex3_np1_flush_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) running_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[running_offset : running_offset + `THREADS-1]), + .scout(sov[running_offset : running_offset + `THREADS-1]), + .din(running_d), + .dout(running_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(2**(`THREADS-1)), .NEEDS_SRESET(1)) llpri_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(llpri_inc), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[llpri_offset : llpri_offset + `THREADS-1]), + .scout(sov[llpri_offset : llpri_offset + `THREADS-1]), + .din(llpri_d), + .dout(llpri_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) dec_dbg_dis_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[dec_dbg_dis_offset : dec_dbg_dis_offset + `THREADS-1]), + .scout(sov[dec_dbg_dis_offset : dec_dbg_dis_offset + `THREADS-1]), + .din(dec_dbg_dis_d), + .dout(dec_dbg_dis_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tb_dbg_dis_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[tb_dbg_dis_offset]), + .scout(sov[tb_dbg_dis_offset]), + .din(tb_dbg_dis_d), + .dout(tb_dbg_dis_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tb_act_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[tb_act_offset]), + .scout(sov[tb_act_offset]), + .din(tb_act_d), + .dout(tb_act_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ext_dbg_dis_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ext_dbg_dis_offset : ext_dbg_dis_offset + `THREADS-1]), + .scout(sov[ext_dbg_dis_offset : ext_dbg_dis_offset + `THREADS-1]), + .din(ext_dbg_dis_d), + .dout(ext_dbg_dis_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) msrovride_enab_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[msrovride_enab_offset]), + .scout(sov[msrovride_enab_offset]), + .din(pc_xu_msrovride_enab), + .dout(msrovride_enab_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) waitimpl_val_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[waitimpl_val_offset : waitimpl_val_offset + `THREADS-1]), + .scout(sov[waitimpl_val_offset : waitimpl_val_offset + `THREADS-1]), + .din(waitimpl_val_d), + .dout(waitimpl_val_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) waitrsv_val_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[waitrsv_val_offset : waitrsv_val_offset + `THREADS-1]), + .scout(sov[waitrsv_val_offset : waitrsv_val_offset + `THREADS-1]), + .din(waitrsv_val_d), + .dout(waitrsv_val_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) an_ac_reservation_vld_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[an_ac_reservation_vld_offset : an_ac_reservation_vld_offset + `THREADS-1]), + .scout(sov[an_ac_reservation_vld_offset : an_ac_reservation_vld_offset + `THREADS-1]), + .din(an_ac_reservation_vld), + .dout(an_ac_reservation_vld_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) an_ac_sleep_en_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[an_ac_sleep_en_offset : an_ac_sleep_en_offset + `THREADS-1]), + .scout(sov[an_ac_sleep_en_offset : an_ac_sleep_en_offset + `THREADS-1]), + .din(an_ac_sleep_en), + .dout(an_ac_sleep_en_q) + ); + tri_rlmreg_p #(.WIDTH(8), .OFFSET(54),.INIT(0), .NEEDS_SRESET(1)) an_ac_coreid_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[an_ac_coreid_offset : an_ac_coreid_offset + 8-1]), + .scout(sov[an_ac_coreid_offset : an_ac_coreid_offset + 8-1]), + .din(an_ac_coreid), + .dout(an_ac_coreid_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tb_update_enable_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[tb_update_enable_offset]), + .scout(sov[tb_update_enable_offset]), + .din(an_ac_tb_update_enable), + .dout(tb_update_enable_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tb_update_pulse_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[tb_update_pulse_offset]), + .scout(sov[tb_update_pulse_offset]), + .din(an_ac_tb_update_pulse), + .dout(tb_update_pulse_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tb_update_pulse_1_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[tb_update_pulse_1_offset]), + .scout(sov[tb_update_pulse_1_offset]), + .din(tb_update_pulse_q), + .dout(tb_update_pulse_1_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pc_xu_reset_wd_complete_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[pc_xu_reset_wd_complete_offset]), + .scout(sov[pc_xu_reset_wd_complete_offset]), + .din(pc_xu_reset_wd_complete), + .dout(pc_xu_reset_wd_complete_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pc_xu_reset_3_complete_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[pc_xu_reset_3_complete_offset]), + .scout(sov[pc_xu_reset_3_complete_offset]), + .din(pc_xu_reset_3_complete), + .dout(pc_xu_reset_3_complete_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pc_xu_reset_2_complete_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[pc_xu_reset_2_complete_offset]), + .scout(sov[pc_xu_reset_2_complete_offset]), + .din(pc_xu_reset_2_complete), + .dout(pc_xu_reset_2_complete_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pc_xu_reset_1_complete_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[pc_xu_reset_1_complete_offset]), + .scout(sov[pc_xu_reset_1_complete_offset]), + .din(pc_xu_reset_1_complete), + .dout(pc_xu_reset_1_complete_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq_xu_dbell_val_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lq_xu_dbell_val_offset]), + .scout(sov[lq_xu_dbell_val_offset]), + .din(lq_xu_dbell_val), + .dout(lq_xu_dbell_val_q) + ); + tri_rlmreg_p #(.WIDTH(5), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) lq_xu_dbell_type_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[lq_xu_dbell_type_offset : lq_xu_dbell_type_offset + 5-1]), + .scout(sov[lq_xu_dbell_type_offset : lq_xu_dbell_type_offset + 5-1]), + .din(lq_xu_dbell_type), + .dout(lq_xu_dbell_type_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq_xu_dbell_brdcast_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lq_xu_dbell_brdcast_offset]), + .scout(sov[lq_xu_dbell_brdcast_offset]), + .din(lq_xu_dbell_brdcast), + .dout(lq_xu_dbell_brdcast_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq_xu_dbell_lpid_match_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lq_xu_dbell_lpid_match_offset]), + .scout(sov[lq_xu_dbell_lpid_match_offset]), + .din(lq_xu_dbell_lpid_match), + .dout(lq_xu_dbell_lpid_match_q) + ); + tri_rlmreg_p #(.WIDTH(14), .OFFSET(50),.INIT(0), .NEEDS_SRESET(1)) lq_xu_dbell_pirtag_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[lq_xu_dbell_pirtag_offset : lq_xu_dbell_pirtag_offset + 14-1]), + .scout(sov[lq_xu_dbell_pirtag_offset : lq_xu_dbell_pirtag_offset + 14-1]), + .din(lq_xu_dbell_pirtag), + .dout(lq_xu_dbell_pirtag_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) dbell_present_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[dbell_present_offset : dbell_present_offset + `THREADS-1]), + .scout(sov[dbell_present_offset : dbell_present_offset + `THREADS-1]), + .din(dbell_present_d), + .dout(dbell_present_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) cdbell_present_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[cdbell_present_offset : cdbell_present_offset + `THREADS-1]), + .scout(sov[cdbell_present_offset : cdbell_present_offset + `THREADS-1]), + .din(cdbell_present_d), + .dout(cdbell_present_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) gdbell_present_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[gdbell_present_offset : gdbell_present_offset + `THREADS-1]), + .scout(sov[gdbell_present_offset : gdbell_present_offset + `THREADS-1]), + .din(gdbell_present_d), + .dout(gdbell_present_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) gcdbell_present_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[gcdbell_present_offset : gcdbell_present_offset + `THREADS-1]), + .scout(sov[gcdbell_present_offset : gcdbell_present_offset + `THREADS-1]), + .din(gcdbell_present_d), + .dout(gcdbell_present_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) gmcdbell_present_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[gmcdbell_present_offset : gmcdbell_present_offset + `THREADS-1]), + .scout(sov[gmcdbell_present_offset : gmcdbell_present_offset + `THREADS-1]), + .din(gmcdbell_present_d), + .dout(gmcdbell_present_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xucr0_clfc_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[xucr0_clfc_offset]), + .scout(sov[xucr0_clfc_offset]), + .din(xucr0_clfc_d), + .dout(xucr0_clfc_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) iu_run_thread_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[iu_run_thread_offset : iu_run_thread_offset + `THREADS-1]), + .scout(sov[iu_run_thread_offset : iu_run_thread_offset + `THREADS-1]), + .din(iu_run_thread_d), + .dout(iu_run_thread_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) inj_sprg_ecc_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[inj_sprg_ecc_offset : inj_sprg_ecc_offset + `THREADS-1]), + .scout(sov[inj_sprg_ecc_offset : inj_sprg_ecc_offset + `THREADS-1]), + .din(pc_xu_inj_sprg_ecc), + .dout(inj_sprg_ecc_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) dbell_interrupt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[dbell_interrupt_offset : dbell_interrupt_offset + `THREADS-1]), + .scout(sov[dbell_interrupt_offset : dbell_interrupt_offset + `THREADS-1]), + .din(dbell_interrupt), + .dout(dbell_interrupt_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) cdbell_interrupt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[cdbell_interrupt_offset : cdbell_interrupt_offset + `THREADS-1]), + .scout(sov[cdbell_interrupt_offset : cdbell_interrupt_offset + `THREADS-1]), + .din(cdbell_interrupt), + .dout(cdbell_interrupt_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) gdbell_interrupt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[gdbell_interrupt_offset : gdbell_interrupt_offset + `THREADS-1]), + .scout(sov[gdbell_interrupt_offset : gdbell_interrupt_offset + `THREADS-1]), + .din(gdbell_interrupt), + .dout(gdbell_interrupt_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) gcdbell_interrupt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[gcdbell_interrupt_offset : gcdbell_interrupt_offset + `THREADS-1]), + .scout(sov[gcdbell_interrupt_offset : gcdbell_interrupt_offset + `THREADS-1]), + .din(gcdbell_interrupt), + .dout(gcdbell_interrupt_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) gmcdbell_interrupt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[gmcdbell_interrupt_offset : gmcdbell_interrupt_offset + `THREADS-1]), + .scout(sov[gmcdbell_interrupt_offset : gmcdbell_interrupt_offset + `THREADS-1]), + .din(gmcdbell_interrupt), + .dout(gmcdbell_interrupt_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) iu_quiesce_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[iu_quiesce_offset : iu_quiesce_offset + `THREADS-1]), + .scout(sov[iu_quiesce_offset : iu_quiesce_offset + `THREADS-1]), + .din(iu_xu_quiesce), + .dout(iu_quiesce_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) iu_icache_quiesce_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[iu_icache_quiesce_offset : iu_icache_quiesce_offset + `THREADS-1]), + .scout(sov[iu_icache_quiesce_offset : iu_icache_quiesce_offset + `THREADS-1]), + .din(iu_xu_icache_quiesce), + .dout(iu_icache_quiesce_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) lsu_quiesce_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[lsu_quiesce_offset : lsu_quiesce_offset + `THREADS-1]), + .scout(sov[lsu_quiesce_offset : lsu_quiesce_offset + `THREADS-1]), + .din(lq_xu_quiesce), + .dout(lsu_quiesce_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) mm_quiesce_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[mm_quiesce_offset : mm_quiesce_offset + `THREADS-1]), + .scout(sov[mm_quiesce_offset : mm_quiesce_offset + `THREADS-1]), + .din(mm_xu_quiesce), + .dout(mm_quiesce_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) bx_quiesce_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[bx_quiesce_offset : bx_quiesce_offset + `THREADS-1]), + .scout(sov[bx_quiesce_offset : bx_quiesce_offset + `THREADS-1]), + .din(bx_xu_quiesce), + .dout(bx_quiesce_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) quiesce_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[quiesce_offset : quiesce_offset + `THREADS-1]), + .scout(sov[quiesce_offset : quiesce_offset + `THREADS-1]), + .din(quiesce_d), + .dout(quiesce_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) quiesced_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[quiesced_offset : quiesced_offset + `THREADS-1]), + .scout(sov[quiesced_offset : quiesced_offset + `THREADS-1]), + .din(quiesced_d), + .dout(quiesced_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) instr_trace_mode_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[instr_trace_mode_offset]), + .scout(sov[instr_trace_mode_offset]), + .din(pc_xu_instr_trace_mode), + .dout(instr_trace_mode_q) + ); + tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) instr_trace_tid_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[instr_trace_tid_offset : instr_trace_tid_offset + 2-1]), + .scout(sov[instr_trace_tid_offset : instr_trace_tid_offset + 2-1]), + .din(pc_xu_instr_trace_tid), + .dout(instr_trace_tid_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) timer_update_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[timer_update_offset]), + .scout(sov[timer_update_offset]), + .din(timer_update_int), + .dout(timer_update_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xu_ord_read_done_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_xu_ord_read_done_offset]), + .scout(sov[spr_xu_ord_read_done_offset]), + .din(spr_xu_ord_read_done_d), + .dout(spr_xu_ord_read_done_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xu_ord_write_done_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_xu_ord_write_done_offset]), + .scout(sov[spr_xu_ord_write_done_offset]), + .din(spr_xu_ord_write_done_d), + .dout(spr_xu_ord_write_done_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_spr_ord_ready_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[xu_spr_ord_ready_offset]), + .scout(sov[xu_spr_ord_ready_offset]), + .din(xu_spr_ord_ready), + .dout(xu_spr_ord_ready_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_sspr_val_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_sspr_val_offset]), + .scout(sov[ex4_sspr_val_offset]), + .din(ex3_sspr_val), + .dout(ex4_sspr_val_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) flush_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[flush_offset : flush_offset + `THREADS-1]), + .scout(sov[flush_offset : flush_offset + `THREADS-1]), + .din(flush), + .dout(flush_q) + ); + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .OFFSET(62-`EFF_IFAR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex1_ifar_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_ifar_offset : ex1_ifar_offset + `EFF_IFAR_WIDTH-1]), + .scout(sov[ex1_ifar_offset : ex1_ifar_offset + `EFF_IFAR_WIDTH-1]), + .din(rv_xu_ex0_ifar), + .dout(ex1_ifar_q) + ); + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .OFFSET(62-`EFF_IFAR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex2_ifar_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_ifar_offset : ex2_ifar_offset + `EFF_IFAR_WIDTH-1]), + .scout(sov[ex2_ifar_offset : ex2_ifar_offset + `EFF_IFAR_WIDTH-1]), + .din(ex1_ifar_q), + .dout(ex2_ifar_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ram_active_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ram_active_offset : ram_active_offset + `THREADS-1]), + .scout(sov[ram_active_offset : ram_active_offset + `THREADS-1]), + .din(pc_xu_ram_active), + .dout(ram_active_q) + ); + tri_rlmreg_p #(.WIDTH(5), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) timer_div_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(timer_div_act), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[timer_div_offset : timer_div_offset + 5-1]), + .scout(sov[timer_div_offset : timer_div_offset + 5-1]), + .din(timer_div_d), + .dout(timer_div_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) msrovride_enab_2_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[msrovride_enab_2_offset : msrovride_enab_2_offset + `THREADS-1]), + .scout(sov[msrovride_enab_2_offset : msrovride_enab_2_offset + `THREADS-1]), + .din(msrovride_enab), + .dout(msrovride_enab_2_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) msrovride_enab_3_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[msrovride_enab_3_offset : msrovride_enab_3_offset + `THREADS-1]), + .scout(sov[msrovride_enab_3_offset : msrovride_enab_3_offset + `THREADS-1]), + .din(msrovride_enab_2_q), + .dout(msrovride_enab_3_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_wait_flush_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex3_wait_flush_offset]), + .scout(sov[ex3_wait_flush_offset]), + .din(ex3_wait_flush_d), + .dout(ex3_wait_flush_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_wait_flush_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex4_wait_flush_offset]), + .scout(sov[ex4_wait_flush_offset]), + .din(ex4_wait_flush_d), + .dout(ex4_wait_flush_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pc_xu_pm_hold_thread_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[pc_xu_pm_hold_thread_offset]), + .scout(sov[pc_xu_pm_hold_thread_offset]), + .din(pc_xu_pm_hold_thread), + .dout(pc_xu_pm_hold_thread_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) power_savings_on_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[power_savings_on_offset]), + .scout(sov[power_savings_on_offset]), + .din(power_savings_on_d), + .dout(power_savings_on_q) + ); + tri_rlmreg_p #(.WIDTH(4*`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) perf_event_bus_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(pc_xu_event_bus_enable), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[perf_event_bus_offset : perf_event_bus_offset + 4*`THREADS-1]), + .scout(sov[perf_event_bus_offset : perf_event_bus_offset + 4*`THREADS-1]), + .din(perf_event_bus_d), + .dout(perf_event_bus_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) perf_event_en_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(pc_xu_event_bus_enable), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[perf_event_en_offset : perf_event_en_offset + `THREADS-1]), + .scout(sov[perf_event_en_offset : perf_event_en_offset + `THREADS-1]), + .din(perf_event_en_d), + .dout(perf_event_en_q) + ); + + + tri_lcbnd spare_0_lcb( + .vd(vdd), + .gd(gnd), + .act(1'b1), + .nclk(nclk), + .force_t(func_sl_force), + .thold_b(func_sl_thold_0_b), + .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), + .mpw2_b(mpw2_dc_b), + .sg(sg_0), + .lclk(spare_0_lclk), + .d1clk(spare_0_d1clk), + .d2clk(spare_0_d2clk) + ); + + tri_inv_nlats #(.WIDTH(16), .BTR("NLI0001_X2_A12TH"), .INIT(0)) spare_0_latch( + .vd(vdd), + .gd(gnd), + .lclk(spare_0_lclk), + .d1clk(spare_0_d1clk), + .d2clk(spare_0_d2clk), + .scanin(siv[spare_0_offset:spare_0_offset + 16 - 1]), + .scanout(sov[spare_0_offset:spare_0_offset + 16 - 1]), + .d(spare_0_d), + .qb(spare_0_q) + ); + assign spare_0_d = (~spare_0_q); + + xu_fctr #(.WIDTH(`THREADS), .PASSTHRU(0), .DELAY_WIDTH(4), .CLOCKGATE(1)) quiesced_fctr( + .nclk(nclk), + .vdd(vdd), + .gnd(gnd), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[quiesced_ctr_offset]), + .scout(sov[quiesced_ctr_offset]), + .delay(4'b1111), + .din(quiesce_b_q), + .dout(quiesce_ctr_zero_b) + ); + + + tri_ser_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ccr0_we_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(bcfg_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(bcfg_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv_bcfg[ccr0_we_offset_bcfg : ccr0_we_offset_bcfg + `THREADS-1]), + .scout(sov_bcfg[ccr0_we_offset_bcfg : ccr0_we_offset_bcfg + `THREADS-1]), + .din(ccr0_we_d), + .dout(ccr0_we_q) + ); + + + + assign siv[0:399] = {sov[1:399], scan_in[0]}; + assign scan_out[0] = sov[0]; + + assign siv[400:scan_right-1] = {sov[401:scan_right-1], scan_in[1]}; + assign scan_out[1] = sov[400]; + + generate + // BCFG + if (scan_right_bcfg > 1) + begin : bcfg_l + assign siv_bcfg[0:scan_right_bcfg - 1] = {sov_bcfg[1:scan_right_bcfg-1], bcfg_scan_in}; + assign bcfg_scan_out = sov_bcfg[0]; + end + if (scan_right_bcfg == 1) + begin : bcfg_s + assign siv_bcfg[0] = bcfg_scan_in; + assign bcfg_scan_out = sov_bcfg[0]; + end + if (scan_right_bcfg == 0) + begin : bcfg_z + assign bcfg_scan_out = bcfg_scan_in; + end + // CCFG + if (scan_right_ccfg > 1) + begin : ccfg_l + assign siv_ccfg[0:scan_right_ccfg - 1] = {sov_ccfg[1:scan_right_ccfg - 1], ccfg_scan_in}; + assign ccfg_scan_out = sov_ccfg[0]; + end + if (scan_right_ccfg == 1) + begin : ccfg_s + assign siv_ccfg[0] = ccfg_scan_in; + assign ccfg_scan_out = sov_ccfg[0]; + end + if (scan_right_ccfg == 0) + begin : ccfg_z + assign ccfg_scan_out = ccfg_scan_in; + end + // DCFG + if (scan_right_dcfg > 1) + begin : dcfg_l + assign siv_dcfg[0:scan_right_dcfg - 1] = {sov_dcfg[1:scan_right_dcfg - 1], dcfg_scan_in}; + assign dcfg_scan_out = sov_dcfg[0]; + end + if (scan_right_dcfg == 1) + begin : dcfg_s + assign siv_dcfg[0] = dcfg_scan_in; + assign dcfg_scan_out = sov_dcfg[0]; + end + if (scan_right_dcfg == 0) + begin : dcfg_z + assign dcfg_scan_out = dcfg_scan_in; + end + endgenerate + + + function [0:`THREADS-1] reverse_threads; + input [0:`THREADS-1] a; + integer t; + begin + for (t=0;t<`THREADS;t=t+1) + begin : threads_loop + reverse_threads[t] = a[`THREADS-1-t]; + end + end + endfunction + + +endmodule diff --git a/dev/verilog/work/xu_spr_tspr.v b/dev/verilog/work/xu_spr_tspr.v new file mode 100755 index 0000000..3d0b3c5 --- /dev/null +++ b/dev/verilog/work/xu_spr_tspr.v @@ -0,0 +1,4551 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: XU SPR - per thread register slice +// +//***************************************************************************** +`include "tri_a2o.vh" +module xu_spr_tspr +#( + parameter hvmode = 1, + parameter a2mode = 1 +)( + input [0:`NCLK_WIDTH-1] nclk, + + // CHIP IO + input an_ac_ext_interrupt, + input an_ac_crit_interrupt, + input an_ac_perf_interrupt, + input an_ac_hang_pulse, + output ac_tc_machine_check, + input an_ac_external_mchk, + input instr_trace_mode, + + input d_mode_dc, + input [0:0] delay_lclkr_dc, + input [0:0] mpw1_dc_b, + input mpw2_dc_b, + input ccfg_sl_force, + input ccfg_sl_thold_0_b, + input dcfg_sl_force, + input dcfg_sl_thold_0_b, + input func_sl_force, + input func_sl_thold_0_b, + input func_slp_sl_force, + input func_slp_sl_thold_0_b, + input func_nsl_force, + input func_nsl_thold_0_b, + input sg_0, + input scan_in, + output scan_out, + input ccfg_scan_in, + output ccfg_scan_out, + input dcfg_scan_in, + output dcfg_scan_out, + + input cspr_tspr_rf1_act, + + // Read Interface + input [0:31] cspr_tspr_ex1_instr, + input cspr_tspr_ex2_tid, + output [64-`GPR_WIDTH:63] tspr_cspr_ex3_tspr_rt, + + // Write Interface + input [64-`GPR_WIDTH:63] ex2_spr_wd, + input ex3_spr_we, + + input cspr_tspr_dec_dbg_dis, + + // Illegal SPR + output tspr_cspr_illeg_mtspr_b, + output tspr_cspr_illeg_mfspr_b, + output tspr_cspr_hypv_mtspr, + output tspr_cspr_hypv_mfspr, + + // Interrupt Interface + input iu_xu_rfi, + input iu_xu_rfgi, + input iu_xu_rfci, + input iu_xu_rfmci, + input iu_xu_act, + input iu_xu_int, + input iu_xu_gint, + input iu_xu_cint, + input iu_xu_mcint, + input [62-`EFF_IFAR_ARCH:61] iu_xu_nia, + input [0:16] iu_xu_esr, + input [0:14] iu_xu_mcsr, + input [0:18] iu_xu_dbsr, + input [64-`GPR_WIDTH:63] iu_xu_dear, + input iu_xu_dear_update, + input iu_xu_dbsr_update, + input iu_xu_esr_update, + input iu_xu_force_gsrr, + input iu_xu_dbsr_ude, + input iu_xu_dbsr_ide, + output xu_iu_dbsr_ide, + output int_rest_act, + output [62-`EFF_IFAR_ARCH:61] int_rest_ifar, + input [62-`EFF_IFAR_WIDTH:61] ex2_ifar, + + // Async Interrupt Req Interface + output xu_iu_external_mchk, + output xu_iu_ext_interrupt, + output xu_iu_dec_interrupt, + output xu_iu_udec_interrupt, + output xu_iu_perf_interrupt, + output xu_iu_fit_interrupt, + output xu_iu_crit_interrupt, + output xu_iu_wdog_interrupt, + output xu_iu_gwdog_interrupt, + output xu_iu_gfit_interrupt, + output xu_iu_gdec_interrupt, + + input cspr_tspr_sleep_mask, + input cspr_tspr_crit_mask, + input cspr_tspr_wdog_mask, + input cspr_tspr_dec_mask, + input cspr_tspr_udec_mask, + input cspr_tspr_perf_mask, + input cspr_tspr_fit_mask, + input cspr_tspr_ext_mask, + + output tspr_cspr_pm_wake_up, + output [0:2] tspr_cspr_async_int, + + output tspr_cspr_ex2_np1_flush, + + // DBELL Int + input [50:63] cspr_tspr_dbell_pirtag, + output tspr_cspr_gpir_match, + + input [0:9] cspr_tspr_timebase_taps, + input timer_update, + + // Debug + output xu_iu_iac1_en, + output xu_iu_iac2_en, + output xu_iu_iac3_en, + output xu_iu_iac4_en, + output tspr_cspr_freeze_timers, + + // Run State + output xu_iu_single_instr_mode, + output xu_iu_raise_iss_pri, + output xu_pc_stop_dnh_instr, + + // LiveLock + input iu_xu_instr_cpl, + input cspr_tspr_llen, + input cspr_tspr_llpri, + output tspr_cspr_lldet, + output tspr_cspr_llpulse, + output xu_pc_err_llbust_attempt, + output xu_pc_err_llbust_failed, + input pc_xu_inj_llbust_attempt, + input pc_xu_inj_llbust_failed, + + // Resets + input pc_xu_inj_wdt_reset, + input reset_wd_complete, + input reset_1_complete, + input reset_2_complete, + input reset_3_complete, + output reset_1_request, + output reset_2_request, + output reset_3_request, + output reset_wd_request, + output xu_pc_err_wdt_reset, + + // MSR Override + input cspr_tspr_ram_active, + input cspr_tspr_msrovride_en, + input pc_xu_msrovride_pr, + input pc_xu_msrovride_gs, + input pc_xu_msrovride_de, + + // SIAR + input pc_xu_spr_cesr1_pmae, + output xu_pc_perfmon_alert, + + // SPRs + input spr_dbcr0_edm, + output tspr_epcr_icm, + output tspr_epcr_gicm, + output tspr_msr_de, + output tspr_msr_cm, + output tspr_msr_pr, + output tspr_msr_is, + output tspr_msr_gs, + output tspr_msr_ee, + output tspr_msr_ce, + output tspr_msr_me, + output tspr_msr_fe0, + output tspr_msr_fe1, + output tspr_fp_precise, + output tspr_epcr_extgs, + input [4:4] cspr_xucr0_clkg_ctl, + input cspr_ccr4_en_dnh, + output [0:`GPR_WIDTH-1] spr_dvc1, + output [0:`GPR_WIDTH-1] spr_dvc2, + output spr_dbcr0_idm, + output spr_dbcr0_icmp, + output spr_dbcr0_brt, + output spr_dbcr0_irpt, + output spr_dbcr0_trap, + output [0:1] spr_dbcr0_dac1, + output [0:1] spr_dbcr0_dac2, + output spr_dbcr0_ret, + output [0:1] spr_dbcr0_dac3, + output [0:1] spr_dbcr0_dac4, + output spr_dbcr1_iac12m, + output spr_dbcr1_iac34m, + output spr_epcr_dtlbgs, + output spr_epcr_itlbgs, + output spr_epcr_dsigs, + output spr_epcr_isigs, + output spr_epcr_duvd, + output spr_epcr_dgtmi, + output xu_mm_spr_epcr_dmiuh, + output spr_msr_ucle, + output spr_msr_spv, + output spr_msr_fp, + output spr_msr_ds, + output spr_msrp_uclep, + + output [0:11] tspr_debug, + + // Power + inout vdd, + inout gnd +); + + localparam DEX2 = 0; + localparam DEX3 = 0; + localparam DEX4 = 0; + localparam DEX5 = 0; + localparam DEX6 = 0; + localparam DWR = 0; + localparam DX = 0; + // SPR Bit Constants + localparam MSR_CM = 50; + localparam MSR_GS = 51; + localparam MSR_UCLE = 52; + localparam MSR_SPV = 53; + localparam MSR_CE = 54; + localparam MSR_EE = 55; + localparam MSR_PR = 56; + localparam MSR_FP = 57; + localparam MSR_ME = 58; + localparam MSR_FE0 = 59; + localparam MSR_DE = 60; + localparam MSR_FE1 = 61; + localparam MSR_IS = 62; + localparam MSR_DS = 63; + localparam MSRP_UCLEP = 62; + localparam MSRP_DEP = 63; + // SPR Registers + wire [62:63] ccr3_d, ccr3_q; + wire [64-(`EFF_IFAR_ARCH):63] csrr0_d, csrr0_q; + wire [50:63] csrr1_d, csrr1_q; + wire [43:63] dbcr0_d, dbcr0_q; + wire [46:63] dbcr1_d, dbcr1_q; + wire [44:63] dbsr_d, dbsr_q; + wire [64-(`GPR_WIDTH):63] dear_d, dear_q; + wire [32:63] dec_d, dec_q; + wire [32:63] decar_d, decar_q; + wire [49:63] dnhdr_d, dnhdr_q; + wire [54:63] epcr_d, epcr_q; + wire [47:63] esr_d, esr_q; + wire [64-(`GPR_WIDTH):63] gdear_d, gdear_q; + wire [32:63] gdec_d, gdec_q; + wire [32:63] gdecar_d, gdecar_q; + wire [47:63] gesr_d, gesr_q; + wire [32:63] gpir_d, gpir_q; + wire [64-(`EFF_IFAR_ARCH):63] gsrr0_d, gsrr0_q; + wire [50:63] gsrr1_d, gsrr1_q; + wire [54:63] gtcr_d, gtcr_q; + wire [60:63] gtsr_d, gtsr_q; + wire [49:63] mcsr_d, mcsr_q; + wire [64-(`EFF_IFAR_ARCH):63] mcsrr0_d, mcsrr0_q; + wire [50:63] mcsrr1_d, mcsrr1_q; + wire [50:63] msr_d, msr_q; + wire [62:63] msrp_d, msrp_q; + wire [62-(`EFF_IFAR_ARCH):63] siar_d, siar_q; + wire [64-(`EFF_IFAR_ARCH):63] srr0_d, srr0_q; + wire [50:63] srr1_d, srr1_q; + wire [52:63] tcr_d, tcr_q; + wire [59:63] tsr_d, tsr_q; + wire [32:63] udec_d, udec_q; + wire [59:63] xucr1_d, xucr1_q; + wire [64-(`GPR_WIDTH):63] dvc1_d; + wire [64-(`GPR_WIDTH):63] dvc1_q; + wire [64-(`GPR_WIDTH):63] dvc2_d; + wire [64-(`GPR_WIDTH):63] dvc2_q; + // FUNC Scanchain + localparam csrr0_offset = 0; + localparam csrr1_offset = csrr0_offset + `EFF_IFAR_ARCH*a2mode; + localparam dbcr1_offset = csrr1_offset + 14*a2mode; + localparam dbsr_offset = dbcr1_offset + 18; + localparam dear_offset = dbsr_offset + 20; + localparam dec_offset = dear_offset + `GPR_WIDTH; + localparam decar_offset = dec_offset + 32; + localparam epcr_offset = decar_offset + 32*a2mode; + localparam esr_offset = epcr_offset + 10*hvmode; + localparam gdear_offset = esr_offset + 17; + localparam gdec_offset = gdear_offset + `GPR_WIDTH*hvmode; + localparam gdecar_offset = gdec_offset + 32*hvmode; + localparam gesr_offset = gdecar_offset + 32*hvmode; + localparam gpir_offset = gesr_offset + 17*hvmode; + localparam gsrr0_offset = gpir_offset + 32*hvmode; + localparam gsrr1_offset = gsrr0_offset + `EFF_IFAR_ARCH*hvmode; + localparam gtcr_offset = gsrr1_offset + 14*hvmode; + localparam gtsr_offset = gtcr_offset + 10*hvmode; + localparam mcsr_offset = gtsr_offset + 4*hvmode; + localparam mcsrr0_offset = mcsr_offset + 15*a2mode; + localparam mcsrr1_offset = mcsrr0_offset + `EFF_IFAR_ARCH*a2mode; + localparam msrp_offset = mcsrr1_offset + 14*a2mode; + localparam siar_offset = msrp_offset + 2*hvmode; + localparam srr0_offset = siar_offset + `EFF_IFAR_ARCH+2; + localparam srr1_offset = srr0_offset + `EFF_IFAR_ARCH; + localparam tcr_offset = srr1_offset + 14; + localparam tsr_offset = tcr_offset + 12*a2mode; + localparam udec_offset = tsr_offset + 5*a2mode; + localparam last_reg_offset = udec_offset + 32*a2mode; + // BCFG Scanchain + localparam last_reg_offset_bcfg = 1; + // CCFG Scanchain + localparam ccr3_offset_ccfg = 0; + localparam msr_offset_ccfg = ccr3_offset_ccfg + 2; + localparam xucr1_offset_ccfg = msr_offset_ccfg + 14; + localparam last_reg_offset_ccfg = xucr1_offset_ccfg + 5; + // DCFG Scanchain + localparam dbcr0_offset_dcfg = 0; + localparam dnhdr_offset_dcfg = dbcr0_offset_dcfg + 21; + localparam last_reg_offset_dcfg = dnhdr_offset_dcfg + 15; + // Latches + wire iu_xu_act_q ; // input=>iu_xu_act , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [1:2] exx_act_q, exx_act_d ; // input=>exx_act_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire ex2_is_mfmsr_q, ex1_is_mfmsr ; // input=>ex1_is_mfmsr , act=>exx_act(1) , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire ex2_wrtee_q, ex1_is_wrtee ; // input=>ex1_is_wrtee , act=>exx_act(1) , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire ex2_wrteei_q, ex1_is_wrteei ; // input=>ex1_is_wrteei , act=>exx_act(1) , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire ex2_dnh_q, ex1_is_dnh ; // input=>ex1_is_dnh , act=>exx_act(1) , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire ex2_is_mtmsr_q, ex1_is_mtmsr ; // input=>ex1_is_mtmsr , act=>exx_act(1) , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire ex2_is_mtspr_q, ex1_is_mtspr ; // input=>ex1_is_mtspr , act=>exx_act(1) , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire [6:20] ex2_instr_q, ex2_instr_d ; // input=>ex2_instr_d , act=>exx_act(1) , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire ex3_is_mtspr_q ; // input=>ex2_is_mtspr_q , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [6:20] ex3_instr_q ; // input=>ex2_instr_q , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire ex3_wrtee_q ; // input=>ex2_wrtee_q , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire ex3_wrteei_q ; // input=>ex2_wrteei_q , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire ex3_dnh_q ; // input=>ex2_dnh_q , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire ex3_is_mtmsr_q ; // input=>ex2_is_mtmsr_q , act=>exx_act(2) , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire iu_rfi_q ; // input=>iu_xu_rfi , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire iu_rfgi_q ; // input=>iu_xu_rfgi , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire iu_rfci_q ; // input=>iu_xu_rfci , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire iu_rfmci_q ; // input=>iu_xu_rfmci , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire iu_int_q ; // input=>iu_xu_int , act=>iu_int_act , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire iu_gint_q ; // input=>iu_xu_gint , act=>iu_int_act , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire iu_cint_q ; // input=>iu_xu_cint , act=>iu_int_act , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire iu_mcint_q ; // input=>iu_xu_mcint , act=>iu_int_act , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [64-`GPR_WIDTH:63] iu_dear_q ; // input=>iu_xu_dear , act=>iu_xu_dear_update , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [62-`EFF_IFAR_ARCH:61] iu_nia_q ; // input=>iu_xu_nia , act=>iu_nia_act , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:16] iu_esr_q ; // input=>iu_xu_esr , act=>iu_xu_esr_update , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:14] iu_mcsr_q ; // input=>iu_xu_mcsr , act=>iu_int_act , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:18] iu_dbsr_q ; // input=>iu_xu_dbsr , act=>iu_xu_dbsr_update , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire iu_dear_update_q ; // input=>iu_xu_dear_update , act=>iu_int_act , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire iu_dbsr_update_q ; // input=>iu_xu_dbsr_update , act=>iu_int_act , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire iu_esr_update_q ; // input=>iu_xu_esr_update , act=>iu_int_act , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire iu_force_gsrr_q ; // input=>iu_xu_force_gsrr , act=>iu_int_act , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire iu_dbsr_ude_q ; // input=>iu_xu_dbsr_ude , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire iu_dbsr_ide_q ; // input=>iu_xu_dbsr_ide , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [64-`GPR_WIDTH:63] ex3_spr_wd_q ; // input=>ex2_spr_wd , act=>exx_act_data(2), scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:`GPR_WIDTH/8-1] ex3_tid_rpwr_q, ex3_tid_rpwr_d ; // input=>ex3_tid_rpwr_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [64-`GPR_WIDTH:63] ex3_tspr_rt_q, ex3_tspr_rt_d ; // input=>ex3_tspr_rt_d , act=>exx_act_data(2), scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire fit_tb_tap_q, fit_tb_tap_d ; // input=>fit_tb_tap_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire wdog_tb_tap_q, wdog_tb_tap_d ; // input=>wdog_tb_tap_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire gfit_tb_tap_q, gfit_tb_tap_d ; // input=>gfit_tb_tap_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire gwdog_tb_tap_q, gwdog_tb_tap_d ; // input=>gwdog_tb_tap_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:3] hang_pulse_q, hang_pulse_d ; // input=>hang_pulse_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire lltap_q, lltap_d ; // input=>lltap_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:1] llcnt_q, llcnt_d ; // input=>llcnt_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire msrovride_pr_q ; // input=>pc_xu_msrovride_pr , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire msrovride_gs_q ; // input=>pc_xu_msrovride_gs , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire msrovride_de_q ; // input=>pc_xu_msrovride_de , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire an_ac_ext_interrupt_q ; // input=>an_ac_ext_interrupt , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire an_ac_crit_interrupt_q ; // input=>an_ac_crit_interrupt , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire an_ac_perf_interrupt_q ; // input=>an_ac_perf_interrupt , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire an_ac_perf_interrupt2_q ; // input=>an_ac_perf_interrupt_q , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:2] mux_msr_gs_q, mux_msr_gs_d ; // input=>mux_msr_gs_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:0] mux_msr_pr_q, mux_msr_pr_d ; // input=>mux_msr_pr_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire err_llbust_attempt_q, err_llbust_attempt_d ; // input=>err_llbust_attempt_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire err_llbust_failed_q, err_llbust_failed_d ; // input=>err_llbust_failed_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire inj_llbust_attempt_q ; // input=>pc_xu_inj_llbust_attempt , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire inj_llbust_failed_q ; // input=>pc_xu_inj_llbust_failed , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire an_ac_external_mchk_q ; // input=>an_ac_external_mchk , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire mchk_interrupt_q, mchk_interrupt ; // input=>mchk_interrupt , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire crit_interrupt_q, crit_interrupt ; // input=>crit_interrupt , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire wdog_interrupt_q, wdog_interrupt ; // input=>wdog_interrupt , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire dec_interrupt_q, dec_interrupt ; // input=>dec_interrupt , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire udec_interrupt_q, udec_interrupt ; // input=>udec_interrupt , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire perf_interrupt_q, perf_interrupt ; // input=>perf_interrupt , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire fit_interrupt_q, fit_interrupt ; // input=>fit_interrupt , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire ext_interrupt_q, ext_interrupt ; // input=>ext_interrupt , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire gwdog_interrupt_q, gwdog_interrupt ; // input=>gwdog_interrupt , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire gdec_interrupt_q, gdec_interrupt ; // input=>gdec_interrupt , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire gfit_interrupt_q, gfit_interrupt ; // input=>gfit_interrupt , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire single_instr_mode_q, single_instr_mode_d ; // input=>single_instr_mode_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire single_instr_mode_2_q ; // input=>single_instr_mode_q , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire machine_check_q, machine_check_d ; // input=>machine_check_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire raise_iss_pri_q, raise_iss_pri_d ; // input=>raise_iss_pri_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire raise_iss_pri_2_q ; // input=>raise_iss_pri_q , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire pc_xu_inj_wdt_reset_q ; // input=>pc_xu_inj_wdt_reset , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire err_wdt_reset_q, err_wdt_reset_d ; // input=>err_wdt_reset_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire ram_active_q ; // input=>cspr_tspr_ram_active , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:9] timebase_taps_q ; // input=>cspr_tspr_timebase_taps , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:1] dbsr_mrr_q,dbsr_mrr_d ; // input=>dbsr_mrr_d , act=>dbsr_mrr_act, scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:1] tsr_wrs_q,tsr_wrs_d ; // input=>tsr_wrs_d , act=>tsr_wrs_act , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire iac1_en_q,iac1_en_d ; // input=>iac1_en_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire iac2_en_q,iac2_en_d ; // input=>iac2_en_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire iac3_en_q,iac3_en_d ; // input=>iac3_en_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire iac4_en_q,iac4_en_d ; // input=>iac4_en_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire ex3_dnh_val_q ; // input=>ex3_dnh , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire an_ac_perf_interrupt_edge_q ; // input=>an_ac_perf_interrupt_edge , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:15] spare_0_q, spare_0_d ; // input=>spare_0_d , act=>1'b1, + // Scanchain + localparam dvc1_offset = last_reg_offset; + localparam dvc2_offset = dvc1_offset + `GPR_WIDTH * a2mode; + localparam iu_xu_act_offset = dvc2_offset + `GPR_WIDTH * a2mode; + localparam exx_act_offset = iu_xu_act_offset + 1; + localparam ex2_is_mfmsr_offset = exx_act_offset + 2; + localparam ex2_wrtee_offset = ex2_is_mfmsr_offset + 1; + localparam ex2_wrteei_offset = ex2_wrtee_offset + 1; + localparam ex2_dnh_offset = ex2_wrteei_offset + 1; + localparam ex2_is_mtmsr_offset = ex2_dnh_offset + 1; + localparam ex2_is_mtspr_offset = ex2_is_mtmsr_offset + 1; + localparam ex2_instr_offset = ex2_is_mtspr_offset + 1; + localparam ex3_is_mtspr_offset = ex2_instr_offset + 15; + localparam ex3_instr_offset = ex3_is_mtspr_offset + 1; + localparam ex3_wrtee_offset = ex3_instr_offset + 15; + localparam ex3_wrteei_offset = ex3_wrtee_offset + 1; + localparam ex3_dnh_offset = ex3_wrteei_offset + 1; + localparam ex3_is_mtmsr_offset = ex3_dnh_offset + 1; + localparam iu_rfi_offset = ex3_is_mtmsr_offset + 1; + localparam iu_rfgi_offset = iu_rfi_offset + 1; + localparam iu_rfci_offset = iu_rfgi_offset + 1; + localparam iu_rfmci_offset = iu_rfci_offset + 1; + localparam iu_int_offset = iu_rfmci_offset + 1; + localparam iu_gint_offset = iu_int_offset + 1; + localparam iu_cint_offset = iu_gint_offset + 1; + localparam iu_mcint_offset = iu_cint_offset + 1; + localparam iu_dear_offset = iu_mcint_offset + 1; + localparam iu_nia_offset = iu_dear_offset + `GPR_WIDTH; + localparam iu_esr_offset = iu_nia_offset + `EFF_IFAR_ARCH; + localparam iu_mcsr_offset = iu_esr_offset + 17; + localparam iu_dbsr_offset = iu_mcsr_offset + 15; + localparam iu_dear_update_offset = iu_dbsr_offset + 19; + localparam iu_dbsr_update_offset = iu_dear_update_offset + 1; + localparam iu_esr_update_offset = iu_dbsr_update_offset + 1; + localparam iu_force_gsrr_offset = iu_esr_update_offset + 1; + localparam iu_dbsr_ude_offset = iu_force_gsrr_offset + 1; + localparam iu_dbsr_ide_offset = iu_dbsr_ude_offset + 1; + localparam ex3_spr_wd_offset = iu_dbsr_ide_offset + 1; + localparam ex3_tid_rpwr_offset = ex3_spr_wd_offset + `GPR_WIDTH; + localparam ex3_tspr_rt_offset = ex3_tid_rpwr_offset + `GPR_WIDTH/8; + localparam fit_tb_tap_offset = ex3_tspr_rt_offset + `GPR_WIDTH; + localparam wdog_tb_tap_offset = fit_tb_tap_offset + 1; + localparam gfit_tb_tap_offset = wdog_tb_tap_offset + 1; + localparam gwdog_tb_tap_offset = gfit_tb_tap_offset + 1; + localparam hang_pulse_offset = gwdog_tb_tap_offset + 1; + localparam lltap_offset = hang_pulse_offset + 4; + localparam llcnt_offset = lltap_offset + 1; + localparam msrovride_pr_offset = llcnt_offset + 2; + localparam msrovride_gs_offset = msrovride_pr_offset + 1; + localparam msrovride_de_offset = msrovride_gs_offset + 1; + localparam an_ac_ext_interrupt_offset = msrovride_de_offset + 1; + localparam an_ac_crit_interrupt_offset = an_ac_ext_interrupt_offset + 1; + localparam an_ac_perf_interrupt_offset = an_ac_crit_interrupt_offset + 1; + localparam an_ac_perf_interrupt2_offset = an_ac_perf_interrupt_offset + 1; + localparam mux_msr_gs_offset = an_ac_perf_interrupt2_offset + 1; + localparam mux_msr_pr_offset = mux_msr_gs_offset + 3; + localparam err_llbust_attempt_offset = mux_msr_pr_offset + 1; + localparam err_llbust_failed_offset = err_llbust_attempt_offset + 1; + localparam inj_llbust_attempt_offset = err_llbust_failed_offset + 1; + localparam inj_llbust_failed_offset = inj_llbust_attempt_offset + 1; + localparam an_ac_external_mchk_offset = inj_llbust_failed_offset + 1; + localparam mchk_interrupt_offset = an_ac_external_mchk_offset + 1; + localparam crit_interrupt_offset = mchk_interrupt_offset + 1; + localparam wdog_interrupt_offset = crit_interrupt_offset + 1; + localparam dec_interrupt_offset = wdog_interrupt_offset + 1; + localparam udec_interrupt_offset = dec_interrupt_offset + 1; + localparam perf_interrupt_offset = udec_interrupt_offset + 1; + localparam fit_interrupt_offset = perf_interrupt_offset + 1; + localparam ext_interrupt_offset = fit_interrupt_offset + 1; + localparam gwdog_interrupt_offset = ext_interrupt_offset + 1; + localparam gdec_interrupt_offset = gwdog_interrupt_offset + 1; + localparam gfit_interrupt_offset = gdec_interrupt_offset + 1; + localparam single_instr_mode_offset = gfit_interrupt_offset + 1; + localparam single_instr_mode_2_offset = single_instr_mode_offset + 1; + localparam machine_check_offset = single_instr_mode_2_offset + 1; + localparam raise_iss_pri_offset = machine_check_offset + 1; + localparam raise_iss_pri_2_offset = raise_iss_pri_offset + 1; + localparam pc_xu_inj_wdt_reset_offset = raise_iss_pri_2_offset + 1; + localparam err_wdt_reset_offset = pc_xu_inj_wdt_reset_offset + 1; + localparam ram_active_offset = err_wdt_reset_offset + 1; + localparam timebase_taps_offset = ram_active_offset + 1; + localparam dbsr_mrr_offset = timebase_taps_offset + 10; + localparam tsr_wrs_offset = dbsr_mrr_offset + 2; + localparam iac1_en_offset = tsr_wrs_offset + 2; + localparam iac2_en_offset = iac1_en_offset + 1; + localparam iac3_en_offset = iac2_en_offset + 1; + localparam iac4_en_offset = iac3_en_offset + 1; + localparam ex3_dnh_val_offset = iac4_en_offset + 1; + localparam an_ac_perf_interrupt_edge_offset = ex3_dnh_val_offset + 1; + localparam spare_0_offset = an_ac_perf_interrupt_edge_offset + 1; + localparam scan_right = spare_0_offset + 16; + wire [0:scan_right-1] siv; + wire [0:scan_right-1] sov; + localparam scan_right_ccfg = last_reg_offset_ccfg; + wire [0:scan_right_ccfg-1] siv_ccfg; + wire [0:scan_right_ccfg-1] sov_ccfg; + localparam scan_right_dcfg = last_reg_offset_dcfg; + wire [0:scan_right_dcfg-1] siv_dcfg; + wire [0:scan_right_dcfg-1] sov_dcfg; + // Signals + wire [00:63] tidn; + wire [0:`NCLK_WIDTH-1] spare_0_lclk; + wire spare_0_d1clk; + wire spare_0_d2clk; + wire ex1_opcode_is_31; + wire ex1_opcode_is_19; + wire [11:20] ex2_instr; + wire ex2_is_mfmsr; + wire ex1_is_mfspr; + wire ex3_is_mtspr; + wire [11:20] ex3_instr; + wire ex3_is_mtmsr; + wire iu_any_int; + wire iu_any_hint; + wire [50:63] ex3_msr_di2; + wire [50:63] ex3_msr_mask; + wire [50:63] ex3_msr_mux; + wire [50:63] ex3_msr_in; + wire [50:63] ex3_csrr1_d; + wire [50:63] ex3_mcsrr1_d; + wire [50:63] ex3_gsrr1_d; + wire [50:63] ex3_srr1_d; + wire [50:63] iu_rfgi_msr; + wire ex3_dec_zero; + wire ex3_dec_upper_zero; + wire ex3_gdec_zero; + wire ex3_gdec_upper_zero; + wire ex3_udec_zero; + wire ex3_udec_upper_zero; + wire ex3_set_tsr_udis; + wire ex3_set_tsr_dis; + wire ex3_set_tsr_fis; + wire ex3_set_tsr_wis; + wire ex3_set_tsr_enw; + wire [59:63] ex3_set_tsr; + wire ex3_set_gtsr_dis; + wire ex3_set_gtsr_fis; + wire ex3_set_gtsr_wis; + wire ex3_set_gtsr_enw; + wire [60:63] ex3_set_gtsr; + wire [64-`GPR_WIDTH:63] ex3_spr_wd; + wire wdog_pulse; + wire gwdog_pulse; + wire lltbtap; + wire llpulse; + wire llreset; + wire [0:1] llstate; + wire set_dbsr_ide; + wire [44:63] set_dbsr; + wire gdec_running; + wire dec_running; + wire udec_running; + wire dbcr0_freeze_timers; + wire dbsr_event; + wire mux_msr_gs; + wire mux_msr_pr; + wire hang_pulse; + wire [64-(`GPR_WIDTH):63] dear_di; + wire ex2_srr0_re2; + wire ex2_gsrr0_re2; + wire ex2_csrr0_re2; + wire ex2_mcsrr0_re2; + wire [1:4] iac_us_en; + wire [1:4] iac_er_en; + wire udec_en; + wire ex3_wrteei; + wire ex3_wrtee; + wire [0:1] reset_complete; + wire wdog_reset_1; + wire wdog_reset_2; + wire wdog_reset_3; + wire [0:9] tb_tap_edge; + wire [1:2] exx_act; + wire [1:2] exx_act_data; + wire iu_int_act; + wire dbsr_mrr_act; + wire tsr_wrs_act; + wire reset_complete_act; + wire ex3_gint_nia_sel; + wire [62-`EFF_IFAR_ARCH:61] ex2_iar; + wire [62-`EFF_IFAR_ARCH:61] ex2_iar_p4; + wire [62-(`EFF_IFAR_ARCH):63] siar_di; + wire [44:63] dbsr_di; + wire mux_msr_de; + wire iu_nia_act; + wire ex3_dnh; + wire [60:63] gtsr_di; + wire an_ac_perf_interrupt_edge; + wire dvc1_act; + wire dvc2_act; + (* analysis_not_referenced="true" *) + wire unused_do_bits; + + // Data + wire spr_ccr3_en_eepri; + wire spr_ccr3_si; + wire spr_csrr1_cm; + wire [0:1] spr_dbcr0_rst; + wire spr_dbcr0_iac1; + wire spr_dbcr0_iac2; + wire spr_dbcr0_iac3; + wire spr_dbcr0_iac4; + wire spr_dbcr0_ft; + wire [0:1] spr_dbcr1_iac1us; + wire [0:1] spr_dbcr1_iac1er; + wire [0:1] spr_dbcr1_iac2us; + wire [0:1] spr_dbcr1_iac2er; + wire [0:1] spr_dbcr1_iac3us; + wire [0:1] spr_dbcr1_iac3er; + wire [0:1] spr_dbcr1_iac4us; + wire [0:1] spr_dbcr1_iac4er; + wire spr_dbsr_ide; + wire spr_epcr_extgs; + wire spr_epcr_icm; + wire spr_epcr_gicm; + wire spr_gsrr1_cm; + wire [0:1] spr_gtcr_wp; + wire [0:1] spr_gtcr_wrc; + wire spr_gtcr_wie; + wire spr_gtcr_die; + wire [0:1] spr_gtcr_fp; + wire spr_gtcr_fie; + wire spr_gtcr_are; + wire spr_gtsr_enw; + wire spr_gtsr_wis; + wire spr_gtsr_dis; + wire spr_gtsr_fis; + wire spr_mcsrr1_cm; + wire spr_msr_cm; + wire spr_msr_gs; + wire spr_msr_ce; + wire spr_msr_ee; + wire spr_msr_pr; + wire spr_msr_me; + wire spr_msr_fe0; + wire spr_msr_de; + wire spr_msr_fe1; + wire spr_msr_is; + wire spr_srr1_cm; + wire [0:1] spr_tcr_wp; + wire [0:1] spr_tcr_wrc; + wire spr_tcr_wie; + wire spr_tcr_die; + wire [0:1] spr_tcr_fp; + wire spr_tcr_fie; + wire spr_tcr_are; + wire spr_tcr_udie; + wire spr_tcr_ud; + wire spr_tsr_enw; + wire spr_tsr_wis; + wire spr_tsr_dis; + wire spr_tsr_fis; + wire spr_tsr_udis; + wire [0:2] spr_xucr1_ll_tb_sel; + wire spr_xucr1_ll_sel; + wire spr_xucr1_ll_en; + wire [62:63] ex3_ccr3_di; + wire [64-(`EFF_IFAR_ARCH):63] ex3_csrr0_di; + wire [50:63] ex3_csrr1_di; + wire [43:63] ex3_dbcr0_di; + wire [46:63] ex3_dbcr1_di; + wire [44:63] ex3_dbsr_di; + wire [64-(`GPR_WIDTH):63] ex3_dear_di; + wire [32:63] ex3_dec_di; + wire [32:63] ex3_decar_di; + wire [49:63] ex3_dnhdr_di; + wire [54:63] ex3_epcr_di; + wire [47:63] ex3_esr_di; + wire [64-(`GPR_WIDTH):63] ex3_gdear_di; + wire [32:63] ex3_gdec_di; + wire [32:63] ex3_gdecar_di; + wire [47:63] ex3_gesr_di; + wire [32:63] ex3_gpir_di; + wire [64-(`EFF_IFAR_ARCH):63] ex3_gsrr0_di; + wire [50:63] ex3_gsrr1_di; + wire [54:63] ex3_gtcr_di; + wire [60:63] ex3_gtsr_di; + wire [49:63] ex3_mcsr_di; + wire [64-(`EFF_IFAR_ARCH):63] ex3_mcsrr0_di; + wire [50:63] ex3_mcsrr1_di; + wire [50:63] ex3_msr_di; + wire [62:63] ex3_msrp_di; + wire [62-(`EFF_IFAR_ARCH):63] ex3_siar_di; + wire [64-(`EFF_IFAR_ARCH):63] ex3_srr0_di; + wire [50:63] ex3_srr1_di; + wire [52:63] ex3_tcr_di; + wire [59:63] ex3_tsr_di; + wire [32:63] ex3_udec_di; + wire [59:63] ex3_xucr1_di; + wire + ex2_ccr3_rdec , ex2_csrr0_rdec , ex2_csrr1_rdec , ex2_dbcr0_rdec + , ex2_dbcr1_rdec , ex2_dbsr_rdec , ex2_dear_rdec , ex2_dec_rdec + , ex2_decar_rdec , ex2_dnhdr_rdec , ex2_epcr_rdec , ex2_esr_rdec + , ex2_gdear_rdec , ex2_gdec_rdec , ex2_gdecar_rdec, ex2_gesr_rdec + , ex2_gpir_rdec , ex2_gsrr0_rdec , ex2_gsrr1_rdec , ex2_gtcr_rdec + , ex2_gtsr_rdec , ex2_iar_rdec , ex2_mcsr_rdec , ex2_mcsrr0_rdec + , ex2_mcsrr1_rdec, ex2_msrp_rdec , ex2_siar_rdec , ex2_srr0_rdec + , ex2_srr1_rdec , ex2_tcr_rdec , ex2_tsr_rdec , ex2_udec_rdec + , ex2_xucr1_rdec ; + wire + ex2_ccr3_re , ex2_csrr0_re , ex2_csrr1_re , ex2_dbcr0_re + , ex2_dbcr1_re , ex2_dbsr_re , ex2_dear_re , ex2_dec_re + , ex2_decar_re , ex2_dnhdr_re , ex2_epcr_re , ex2_esr_re + , ex2_gdear_re , ex2_gdec_re , ex2_gdecar_re , ex2_gesr_re + , ex2_gpir_re , ex2_gsrr0_re , ex2_gsrr1_re , ex2_gtcr_re + , ex2_gtsr_re , ex2_iar_re , ex2_mcsr_re , ex2_mcsrr0_re + , ex2_mcsrr1_re , ex2_msrp_re , ex2_siar_re , ex2_srr0_re + , ex2_srr1_re , ex2_tcr_re , ex2_tsr_re , ex2_udec_re + , ex2_xucr1_re ; + wire ex2_pir_rdec; + wire + ex2_ccr3_we , ex2_csrr0_we , ex2_csrr1_we , ex2_dbcr0_we + , ex2_dbcr1_we , ex2_dbsr_we , ex2_dbsrwr_we , ex2_dear_we + , ex2_dec_we , ex2_decar_we , ex2_dnhdr_we , ex2_epcr_we + , ex2_esr_we , ex2_gdear_we , ex2_gdec_we , ex2_gdecar_we + , ex2_gesr_we , ex2_gpir_we , ex2_gsrr0_we , ex2_gsrr1_we + , ex2_gtcr_we , ex2_gtsr_we , ex2_gtsrwr_we , ex2_iar_we + , ex2_mcsr_we , ex2_mcsrr0_we , ex2_mcsrr1_we , ex2_msrp_we + , ex2_siar_we , ex2_srr0_we , ex2_srr1_we , ex2_tcr_we + , ex2_tsr_we , ex2_udec_we , ex2_xucr1_we ; + wire + ex2_ccr3_wdec , ex2_csrr0_wdec , ex2_csrr1_wdec , ex2_dbcr0_wdec + , ex2_dbcr1_wdec , ex2_dbsr_wdec , ex2_dbsrwr_wdec, ex2_dear_wdec + , ex2_dec_wdec , ex2_decar_wdec , ex2_dnhdr_wdec , ex2_epcr_wdec + , ex2_esr_wdec , ex2_gdear_wdec , ex2_gdec_wdec , ex2_gdecar_wdec + , ex2_gesr_wdec , ex2_gpir_wdec , ex2_gsrr0_wdec , ex2_gsrr1_wdec + , ex2_gtcr_wdec , ex2_gtsr_wdec , ex2_gtsrwr_wdec, ex2_iar_wdec + , ex2_mcsr_wdec , ex2_mcsrr0_wdec, ex2_mcsrr1_wdec, ex2_msrp_wdec + , ex2_siar_wdec , ex2_srr0_wdec , ex2_srr1_wdec , ex2_tcr_wdec + , ex2_tsr_wdec , ex2_udec_wdec , ex2_xucr1_wdec ; + wire + ex3_ccr3_we , ex3_csrr0_we , ex3_csrr1_we , ex3_dbcr0_we + , ex3_dbcr1_we , ex3_dbsr_we , ex3_dbsrwr_we , ex3_dear_we + , ex3_dec_we , ex3_decar_we , ex3_dnhdr_we , ex3_epcr_we + , ex3_esr_we , ex3_gdear_we , ex3_gdec_we , ex3_gdecar_we + , ex3_gesr_we , ex3_gpir_we , ex3_gsrr0_we , ex3_gsrr1_we + , ex3_gtcr_we , ex3_gtsr_we , ex3_gtsrwr_we , ex3_iar_we + , ex3_mcsr_we , ex3_mcsrr0_we , ex3_mcsrr1_we , ex3_msr_we + , ex3_msrp_we , ex3_siar_we , ex3_srr0_we , ex3_srr1_we + , ex3_tcr_we , ex3_tsr_we , ex3_udec_we , ex3_xucr1_we ; + wire + ex3_ccr3_wdec , ex3_csrr0_wdec , ex3_csrr1_wdec , ex3_dbcr0_wdec + , ex3_dbcr1_wdec , ex3_dbsr_wdec , ex3_dbsrwr_wdec, ex3_dear_wdec + , ex3_dec_wdec , ex3_decar_wdec , ex3_dnhdr_wdec , ex3_epcr_wdec + , ex3_esr_wdec , ex3_gdear_wdec , ex3_gdec_wdec , ex3_gdecar_wdec + , ex3_gesr_wdec , ex3_gpir_wdec , ex3_gsrr0_wdec , ex3_gsrr1_wdec + , ex3_gtcr_wdec , ex3_gtsr_wdec , ex3_gtsrwr_wdec, ex3_iar_wdec + , ex3_mcsr_wdec , ex3_mcsrr0_wdec, ex3_mcsrr1_wdec, ex3_msr_wdec + , ex3_msrp_wdec , ex3_siar_wdec , ex3_srr0_wdec , ex3_srr1_wdec + , ex3_tcr_wdec , ex3_tsr_wdec , ex3_udec_wdec , ex3_xucr1_wdec ; + wire + ccr3_act , csrr0_act , csrr1_act , dbcr0_act + , dbcr1_act , dbsr_act , dear_act , dec_act + , decar_act , dnhdr_act , epcr_act , esr_act + , gdear_act , gdec_act , gdecar_act , gesr_act + , gpir_act , gsrr0_act , gsrr1_act , gtcr_act + , gtsr_act , iar_act , mcsr_act , mcsrr0_act + , mcsrr1_act , msr_act , msrp_act , siar_act + , srr0_act , srr1_act , tcr_act , tsr_act + , udec_act , xucr1_act ; + wire [0:64] + ccr3_do , csrr0_do , csrr1_do , dbcr0_do + , dbcr1_do , dbsr_do , dear_do , dec_do + , decar_do , dnhdr_do , epcr_do , esr_do + , gdear_do , gdec_do , gdecar_do , gesr_do + , gpir_do , gsrr0_do , gsrr1_do , gtcr_do + , gtsr_do , iar_do , mcsr_do , mcsrr0_do + , mcsrr1_do , msr_do , msrp_do , siar_do + , srr0_do , srr1_do , tcr_do , tsr_do + , udec_do , xucr1_do ; + + wire unused; + //!! Bugspray Include: xu_spr_tspr; + //## figtree_source: xu_spr_tspr.fig; + + assign tidn = {64{1'b0}}; + + assign exx_act_d = {cspr_tspr_rf1_act, exx_act[1:1]}; + + assign exx_act[1] = exx_act_q[1]; + assign exx_act[2] = exx_act_q[2]; + + assign exx_act_data[1] = exx_act[1]; + assign exx_act_data[2] = exx_act[2]; + + assign iu_int_act = iu_xu_act | iu_xu_act_q | cspr_xucr0_clkg_ctl[4]; + + // Decode + assign ex1_opcode_is_19 = cspr_tspr_ex1_instr[0:5] == 6'b010011; + assign ex1_opcode_is_31 = cspr_tspr_ex1_instr[0:5] == 6'b011111; + assign ex1_is_mfspr = (ex1_opcode_is_31 & cspr_tspr_ex1_instr[21:30] == 10'b0101010011); // 31/339 + assign ex1_is_mtspr = (ex1_opcode_is_31 & cspr_tspr_ex1_instr[21:30] == 10'b0111010011); // 31/467 + assign ex1_is_mfmsr = (ex1_opcode_is_31 & cspr_tspr_ex1_instr[21:30] == 10'b0001010011); // 31/083 + assign ex1_is_mtmsr = (ex1_opcode_is_31 & cspr_tspr_ex1_instr[21:30] == 10'b0010010010); // 31/146 + assign ex1_is_wrtee = (ex1_opcode_is_31 & cspr_tspr_ex1_instr[21:30] == 10'b0010000011); // 31/131 + assign ex1_is_wrteei = (ex1_opcode_is_31 & cspr_tspr_ex1_instr[21:30] == 10'b0010100011); // 31/163 + assign ex1_is_dnh = (ex1_opcode_is_19 & cspr_tspr_ex1_instr[21:30] == 10'b0011000110); // 19/198 + + assign ex2_instr_d = (ex1_is_mfspr | ex1_is_mtspr | ex1_is_wrteei | ex1_is_dnh)==1'b1 ? cspr_tspr_ex1_instr[6:20] : 15'b0; + + assign ex2_instr = ex2_instr_q[11:20]; + assign ex2_is_mfmsr = ex2_is_mfmsr_q; + + assign ex3_is_mtspr = ex3_is_mtspr_q; + assign ex3_instr = ex3_instr_q[11:20]; + assign ex3_is_mtmsr = ex3_is_mtmsr_q; + assign ex3_spr_wd = ex3_spr_wd_q; + + assign iu_any_int = iu_int_q | iu_cint_q | iu_mcint_q | iu_gint_q; + assign iu_any_hint = iu_int_q | iu_cint_q | iu_mcint_q; + assign ex3_wrteei = ex3_spr_we & ex3_wrteei_q; + assign ex3_wrtee = ex3_spr_we & ex3_wrtee_q; + assign ex3_dnh = ex3_spr_we & ex3_dnh_q & cspr_ccr4_en_dnh; + assign xu_pc_stop_dnh_instr = ex3_dnh_val_q; + + assign ex3_tid_rpwr_d = {`GPR_WIDTH/8{cspr_tspr_ex2_tid}}; + + assign tb_tap_edge = cspr_tspr_timebase_taps & (~timebase_taps_q); + + assign iu_nia_act = iu_int_act | ex1_is_mfspr | an_ac_perf_interrupt_edge; + + assign ex2_iar_p4 = {iu_nia_q[62-`EFF_IFAR_ARCH:61-`EFF_IFAR_WIDTH],ex2_ifar[62-`EFF_IFAR_WIDTH:61]} + `EFF_IFAR_ARCH'd1; + + // SPR Input Control + // CCR3 + assign ex2_iar[62-`EFF_IFAR_ARCH:61] = (ram_active_q == 1'b1) ? iu_nia_q[62 - `EFF_IFAR_ARCH:61] : + {(ex2_iar_p4[62-`EFF_IFAR_ARCH:31] & {32{spr_msr_cm}}),ex2_iar_p4[32:61]}; + assign ccr3_act = ex3_ccr3_we; + assign ccr3_d = ex3_ccr3_di; + + // CSRR0 + assign csrr0_act = ex3_csrr0_we | iu_cint_q; + + // CSRR1 + assign csrr0_d = (iu_cint_q == 1'b1) ? iu_nia_q : ex3_csrr0_di; + assign csrr1_act = ex3_csrr1_we | iu_cint_q; + + generate + if (`GPR_WIDTH == 64) + begin : csrr1_gen_64 + assign ex3_csrr1_d = ex3_csrr1_di; + end + endgenerate + generate + if (`GPR_WIDTH == 32) + begin : csrr1_gen_32 + assign ex3_csrr1_d[MSR_CM] = 1'b0; + assign ex3_csrr1_d[MSR_GS:MSR_DS] = ex3_csrr1_di[MSR_GS:MSR_DS]; + end + endgenerate + + assign csrr1_d = (iu_cint_q == 1'b1) ? msr_q : ex3_csrr1_d; + + // DBCR0 + assign dbcr0_act = ex3_dbcr0_we; + assign dbcr0_d = ex3_dbcr0_di; + + // DBCR1 + assign dbcr1_act = ex3_dbcr1_we; + assign dbcr1_d = ex3_dbcr1_di; + + // DBSR + assign reset_complete_act = |(reset_complete); + + assign dbsr_mrr_act = reset_complete_act | ex3_dbsr_we | ex3_dbsrwr_we; + + assign dbsr_mrr_d = (reset_complete_act == 1'b1) ? reset_complete : + (ex3_dbsrwr_we == 1'b1) ? ex3_spr_wd[34:35] : + (dbsr_mrr_q & (~ex3_spr_wd[34:35])); + + assign dbsr_act = ex3_dbsr_we | ex3_dbsrwr_we | iu_dbsr_update_q | iu_dbsr_ude_q; + + // BRT and ICMP event can never set IDE. + assign set_dbsr_ide = ((iu_dbsr_q[0] | |iu_dbsr_q[3:18]) & ~msr_q[60]) | iu_dbsr_ide_q; + assign set_dbsr = {set_dbsr_ide, (iu_dbsr_q[0] | iu_dbsr_ude_q), iu_dbsr_q[1:18]}; + + assign dbsr_d = dbsr_di | (set_dbsr & {20{(iu_dbsr_update_q | iu_dbsr_ude_q)}}); + assign dbsr_di = (ex3_dbsrwr_we == 1'b1) ? ex3_dbsr_di : + (ex3_dbsr_we == 1'b1) ? (dbsr_q & (~ex3_dbsr_di)) : + dbsr_q; + + // DEAR + assign dear_act = ex3_dear_we | (iu_dear_update_q & ~iu_gint_q); + + assign dear_di = (iu_dear_update_q == 1'b1) ? iu_dear_q : ex3_dear_di; + assign dear_d = dear_di; + + // DVC1 (shadow) + assign dvc1_act = 1'b0; + assign dvc1_d = ex3_spr_wd[64 - (`GPR_WIDTH):63]; + + // DVC2 (shadow) + assign dvc2_act = 1'b0; + assign dvc2_d = ex3_spr_wd[64 - (`GPR_WIDTH):63]; + + // GDEAR + assign gdear_act = ex3_gdear_we | (iu_dear_update_q & iu_gint_q); + + assign gdear_d = dear_di; + + // DEC + assign dec_running = timer_update & ~(~spr_tcr_are & ex3_dec_zero) & ~cspr_tspr_dec_dbg_dis & ~dbcr0_freeze_timers; + + assign dec_act = ex3_dec_we | dec_running; + + assign dec_d = (ex3_dec_we == 1'b1) ? ex3_dec_di : + ((ex3_set_tsr_dis & spr_tcr_are) == 1'b1) ? decar_q : + dec_q - 1; + + // GDEC + assign gdec_running = timer_update & ~(~spr_gtcr_are & ex3_gdec_zero) & ~cspr_tspr_dec_dbg_dis & ~dbcr0_freeze_timers; + + assign gdec_act = ex3_gdec_we | gdec_running; + + assign gdec_d = (ex3_gdec_we == 1'b1) ? ex3_gdec_di : + ((ex3_set_gtsr_dis & spr_gtcr_are) == 1'b1) ? gdecar_q : + gdec_q - 1; + + // UDEC + assign udec_running = timer_update & ~ex3_udec_zero & ~cspr_tspr_dec_dbg_dis & ~dbcr0_freeze_timers; + + assign udec_act = ex3_udec_we | udec_running; + + assign udec_d = (ex3_udec_we == 1'b1) ? ex3_udec_di : udec_q - 1; + + // DECAR + assign decar_act = ex3_decar_we; + assign decar_d = ex3_decar_di; + + // DECAR + assign gdecar_act = ex3_gdecar_we; + assign gdecar_d = ex3_gdecar_di; + + // DNHDR + assign dnhdr_act = ex3_dnhdr_we | ex3_dnh; + assign dnhdr_d = (ex3_dnh_q == 1'b1) ? ex3_instr_q[6:20] : ex3_dnhdr_di; + + // EPCR + assign epcr_act = ex3_epcr_we; + assign epcr_d = ex3_epcr_di; + + // ESR + assign esr_act = ex3_esr_we | (iu_esr_update_q & iu_int_q); + + assign esr_d = (iu_esr_update_q == 1'b1) ? iu_esr_q : + (ex3_esr_we == 1'b1) ? ex3_esr_di : + esr_q; + + // GESR + assign gesr_act = ex3_gesr_we | (iu_esr_update_q & iu_gint_q); + + assign gesr_d = (iu_esr_update_q == 1'b1) ? iu_esr_q : + (ex3_gesr_we == 1'b1) ? ex3_gesr_di : + gesr_q; + + // GPIR + assign gpir_act = ex3_gpir_we; + assign gpir_d = ex3_gpir_di; + + // IAR + assign iar_act = ex3_iar_we; + + // MCSR + assign mcsr_act = ex3_mcsr_we | iu_mcint_q; + + assign mcsr_d = (iu_mcint_q == 1'b1) ? iu_mcsr_q : + (ex3_mcsr_we == 1'b1) ? ex3_mcsr_di : + mcsr_q; + + // MCSRR0 + assign mcsrr0_act = ex3_mcsrr0_we | iu_mcint_q; + + // MCSRR1 + assign mcsrr0_d = (iu_mcint_q == 1'b1) ? iu_nia_q : ex3_mcsrr0_di; + assign mcsrr1_act = ex3_mcsrr1_we | iu_mcint_q; + + generate + if (`GPR_WIDTH == 64) + begin : mcsrr1_gen_64 + assign ex3_mcsrr1_d = ex3_mcsrr1_di; + end + endgenerate + generate + if (`GPR_WIDTH == 32) + begin : mcsrr1_gen_32 + assign ex3_mcsrr1_d[MSR_CM] = 1'b0; + assign ex3_mcsrr1_d[MSR_GS:MSR_DS] = ex3_mcsrr1_di[MSR_GS:MSR_DS]; + end + endgenerate + + // MSR + assign mcsrr1_d = (iu_mcint_q == 1'b1) ? msr_q : ex3_mcsrr1_d; + assign msr_act = ex3_wrteei | ex3_wrtee | iu_any_hint | iu_gint_q | iu_rfi_q | iu_rfgi_q | iu_rfci_q | iu_rfmci_q | ex3_msr_we; + + // CM GS UCLE SPV CE EE PR FP ME FE0 DE FE1 IS DS + // 50 51 52 53 54 55 56 57 58 59 60 61 62 63 + // X X MSRP + + assign ex3_msr_di2[MSR_UCLE] = ((msrp_q[MSRP_UCLEP] & msr_q[MSR_GS]) == 1'b1) ? msr_q[MSR_UCLE] : ex3_msr_di[MSR_UCLE]; + assign ex3_msr_di2[MSR_DE] = ((msrp_q[MSRP_DEP] & msr_q[MSR_GS]) == 1'b1) ? msr_q[MSR_DE] : ex3_msr_di[MSR_DE]; + assign ex3_msr_di2[MSR_CM] = ex3_msr_di[MSR_CM]; + assign ex3_msr_di2[MSR_GS] = ex3_msr_di[MSR_GS] | msr_q[MSR_GS]; + assign ex3_msr_di2[MSR_SPV:MSR_FE0] = ex3_msr_di[MSR_SPV:MSR_FE0]; + assign ex3_msr_di2[MSR_FE1:MSR_DS] = ex3_msr_di[MSR_FE1:MSR_DS]; + + // 0 leave unchanged + // 1 clear + assign ex3_msr_mask[MSR_CM] = 1'b0; // CM + assign ex3_msr_mask[MSR_GS] = iu_any_hint; // GS + assign ex3_msr_mask[MSR_UCLE] = iu_any_hint | (iu_gint_q & (~msrp_q[MSRP_UCLEP])); // UCLE + assign ex3_msr_mask[MSR_SPV] = iu_any_int; // SPV + assign ex3_msr_mask[MSR_CE] = iu_mcint_q | iu_cint_q; // CE + assign ex3_msr_mask[MSR_EE] = iu_any_int; // EE + assign ex3_msr_mask[MSR_PR:MSR_FP] = {2{iu_any_int}}; // PR,FP + assign ex3_msr_mask[MSR_ME] = iu_mcint_q; // ME + assign ex3_msr_mask[MSR_FE0] = iu_any_int; // FE0 + assign ex3_msr_mask[MSR_DE] = iu_mcint_q | iu_cint_q; // DE + assign ex3_msr_mask[MSR_FE1:MSR_DS] = {3{iu_any_int}}; // FE1,IS,DS + + assign ex3_msr_mux = ({iu_rfi_q, iu_rfgi_q, iu_rfci_q, iu_rfmci_q, ex3_msr_we} == 5'b10000) ? srr1_q : + ({iu_rfi_q, iu_rfgi_q, iu_rfci_q, iu_rfmci_q, ex3_msr_we} == 5'b01000) ? iu_rfgi_msr : + ({iu_rfi_q, iu_rfgi_q, iu_rfci_q, iu_rfmci_q, ex3_msr_we} == 5'b00100) ? csrr1_q : + ({iu_rfi_q, iu_rfgi_q, iu_rfci_q, iu_rfmci_q, ex3_msr_we} == 5'b00010) ? mcsrr1_q : + ({iu_rfi_q, iu_rfgi_q, iu_rfci_q, iu_rfmci_q, ex3_msr_we} == 5'b00001) ? ex3_msr_di2 : + msr_q; + assign ex3_msr_in[51:54] = ex3_msr_mux[51:54]; + assign ex3_msr_in[56:63] = ex3_msr_mux[56:63]; + + assign ex3_msr_in[MSR_CM] = ({iu_any_hint, iu_gint_q} == 2'b10) ? spr_epcr_icm : + ({iu_any_hint, iu_gint_q} == 2'b01) ? spr_epcr_gicm : + ex3_msr_mux[MSR_CM]; + + assign ex3_msr_in[MSR_EE] = ({ex3_wrteei, ex3_wrtee} == 2'b10) ? ex3_instr_q[16] : + ({ex3_wrteei, ex3_wrtee} == 2'b01) ? ex3_spr_wd[48] : + ex3_msr_mux[MSR_EE]; + generate + if (`GPR_WIDTH == 64) + begin : msr_gen_64 + assign msr_d = ex3_msr_in & ~ex3_msr_mask; + end + endgenerate + generate + if (`GPR_WIDTH == 32) + begin : msr_gen_32 + assign msr_d[MSR_CM] = 1'b0; + assign msr_d[MSR_GS:MSR_DS] = ex3_msr_in[MSR_GS:MSR_DS] & ~ex3_msr_mask[MSR_GS:MSR_DS]; + end + endgenerate + + // rfgi msr + assign iu_rfgi_msr[MSR_CM] = gsrr1_q[MSR_CM]; + assign iu_rfgi_msr[MSR_SPV:MSR_FE0] = gsrr1_q[MSR_SPV:MSR_FE0]; + assign iu_rfgi_msr[MSR_FE1:MSR_DS] = gsrr1_q[MSR_FE1:MSR_DS]; + assign iu_rfgi_msr[MSR_GS] = ((msr_q[MSR_GS]) == 1'b1) ? msr_q[MSR_GS] : gsrr1_q[MSR_GS]; + assign iu_rfgi_msr[MSR_UCLE] = ((msrp_q[MSRP_UCLEP] & msr_q[MSR_GS]) == 1'b1) ? msr_q[MSR_UCLE] : gsrr1_q[MSR_UCLE]; + assign iu_rfgi_msr[MSR_DE] = ((msrp_q[MSRP_DEP] & msr_q[MSR_GS]) == 1'b1) ? msr_q[MSR_DE] : gsrr1_q[MSR_DE]; + + // MSRP + assign msrp_act = ex3_msrp_we; + assign msrp_d = ex3_msrp_di; + + // SIAR + assign an_ac_perf_interrupt_edge = (an_ac_perf_interrupt_q & (~an_ac_perf_interrupt2_q)); + assign xu_pc_perfmon_alert = an_ac_perf_interrupt_edge_q; + + assign siar_act = ex3_siar_we | (an_ac_perf_interrupt_edge_q & pc_xu_spr_cesr1_pmae); + + assign siar_di = {iu_nia_q, spr_msr_gs, spr_msr_pr}; + + assign siar_d = (an_ac_perf_interrupt_edge_q == 1'b1) ? siar_di : ex3_siar_di; + + // SRR0 + assign srr0_act = ex3_srr0_we | (iu_int_q & ~iu_force_gsrr_q); + + // SRR1 + assign srr1_act = ex3_srr1_we | (iu_int_q & ~iu_force_gsrr_q); + assign srr0_d = (iu_int_q == 1'b1) ? iu_nia_q : ex3_srr0_di; + + generate + if (`GPR_WIDTH == 64) + begin : srr1_gen_64 + assign ex3_srr1_d = ex3_srr1_di; + end + endgenerate + generate + if (`GPR_WIDTH == 32) + begin : srr1_gen_32 + assign ex3_srr1_d[MSR_CM] = 1'b0; + assign ex3_srr1_d[MSR_GS:MSR_DS] = ex3_srr1_di[MSR_GS:MSR_DS]; + end + endgenerate + + // GSRR0 + assign srr1_d = (iu_int_q == 1'b1) ? msr_q : ex3_srr1_d; + assign ex3_gint_nia_sel = iu_gint_q | (iu_int_q & iu_force_gsrr_q); + + assign gsrr0_act = ex3_gsrr0_we | ex3_gint_nia_sel; + + // GSRR1 + assign gsrr1_act = ex3_gsrr1_we | ex3_gint_nia_sel; + assign gsrr0_d = (ex3_gint_nia_sel == 1'b1) ? iu_nia_q : ex3_gsrr0_di; + + generate + if (`GPR_WIDTH == 64) + begin : gsrr1_gen_64 + assign ex3_gsrr1_d = ex3_gsrr1_di; + end + endgenerate + generate + if (`GPR_WIDTH == 32) + begin : gsrr1_gen_32 + assign ex3_gsrr1_d[MSR_CM] = 1'b0; + assign ex3_gsrr1_d[MSR_GS:MSR_DS] = ex3_gsrr1_di[MSR_GS:MSR_DS]; + end + endgenerate + + assign gsrr1_d = (ex3_gint_nia_sel == 1'b1) ? msr_q : ex3_gsrr1_d; + + // TCR + assign tcr_act = ex3_tcr_we; + assign tcr_d = ex3_tcr_di; + + // GTCR + assign gtcr_act = ex3_gtcr_we; + assign gtcr_d = ex3_gtcr_di; + + // TSR + assign tsr_wrs_act = (reset_wd_complete & reset_complete_act) | ex3_tsr_we; + + assign tsr_wrs_d = ((reset_wd_complete & reset_complete_act) == 1'b1) ? reset_complete : (tsr_wrs_q & (~ex3_spr_wd[34:35])); + + assign tsr_act = 1'b1; + + assign tsr_d = ex3_set_tsr | (tsr_q & ~(ex3_tsr_di & {5{ex3_tsr_we}})); + + // GTSR + assign gtsr_act = 1'b1; + + assign gtsr_di = gtsr_q & ~(ex3_gtsr_di & {4{ex3_gtsr_we}}); + + assign gtsr_d = ex3_set_gtsr | ((ex3_gtsrwr_we == 1'b1) ? ex3_gtsr_di : gtsr_di); + + // XUCR1 + assign xucr1_act = ex3_xucr1_we; + assign xucr1_d = ex3_xucr1_di; + + // LiveLock Buster! + // assign cspr_tspr_timebase_taps[8] = tbl_q[32 + 23]; // 9 x + // assign cspr_tspr_timebase_taps[7] = tbl_q[32 + 11]; // 21 x + // assign cspr_tspr_timebase_taps[6] = tbl_q[32 + 7]; // 25 x + // assign cspr_tspr_timebase_taps[5] = tbl_q[32 + 21]; // 11 x x + // assign cspr_tspr_timebase_taps[4] = tbl_q[32 + 17]; // 15 x x + // assign cspr_tspr_timebase_taps[3] = tbl_q[32 + 13]; // 19 x x x + // assign cspr_tspr_timebase_taps[2] = tbl_q[32 + 9]; // 23 x x x + // assign cspr_tspr_timebase_taps[1] = tbl_q[32 + 5]; // 27 x x + // assign cspr_tspr_timebase_taps[0] = tbl_q[32 + 1]; // 31 x + // assign cspr_tspr_timebase_taps[9] = tbl_q[32 + 7]; // 29 x -- Replaced 1 for wdog + + assign lltbtap = (spr_xucr1_ll_tb_sel == 3'b000) ? tb_tap_edge[8] : // 9 + (spr_xucr1_ll_tb_sel == 3'b001) ? tb_tap_edge[5] : // 11 + (spr_xucr1_ll_tb_sel == 3'b010) ? tb_tap_edge[4] : // 15 + (spr_xucr1_ll_tb_sel == 3'b011) ? tb_tap_edge[3] : // 19 + (spr_xucr1_ll_tb_sel == 3'b100) ? tb_tap_edge[7] : // 21 + (spr_xucr1_ll_tb_sel == 3'b101) ? tb_tap_edge[2] : // 23 + (spr_xucr1_ll_tb_sel == 3'b110) ? tb_tap_edge[6] : // 25 + tb_tap_edge[1]; // 27 + + assign hang_pulse_d = {an_ac_hang_pulse, hang_pulse_q[0:2]}; + assign hang_pulse = hang_pulse_q[2] & (~hang_pulse_q[3]); + + assign lltap_d = (spr_xucr1_ll_sel == 1'b1) ? hang_pulse : lltbtap; // Stop if counter == "10" + + // Gate off if disabled + assign llpulse = ~llcnt_q[0] & cspr_tspr_llen & spr_xucr1_ll_en & lltap_q; // Don't pulse if stopped + + assign llreset = (iu_xu_instr_cpl & ~((inj_llbust_attempt_q & ~llcnt_q[0]) | inj_llbust_failed_q)) | ~cspr_tspr_llen; + + assign llcnt_d = ({llpulse, llreset} == 2'b01) ? 2'b00 : + ({llpulse, llreset} == 2'b11) ? 2'b00 : + ({llpulse, llreset} == 2'b10) ? llcnt_q + 2'd1 : + llcnt_q; + + assign tspr_cspr_lldet = llcnt_q[0] & spr_xucr1_ll_en; + assign tspr_cspr_llpulse = llpulse; + + assign llstate[0] = llcnt_q[0]; + assign llstate[1] = llcnt_q[1] | (llcnt_q[0] & (~cspr_tspr_llpri)); + + // Raise the priority for threads that are in livelock + // Raise the priroity for threads with EE=0 + assign raise_iss_pri_d = (~spr_msr_ee & spr_ccr3_en_eepri) | (llcnt_q[0] & cspr_tspr_llpri & spr_xucr1_ll_en); + assign xu_iu_raise_iss_pri = raise_iss_pri_2_q; + + assign err_llbust_attempt_d = llstate[0] & ~llstate[1]; + assign err_llbust_failed_d = llstate[0] & cspr_tspr_llen & spr_xucr1_ll_en & lltap_q & cspr_tspr_llpri; + + + tri_direct_err_rpt #(.WIDTH(2)) xu_spr_tspr_llbust_err_rpt( + .vd(vdd), + .gd(gnd), + .err_in({err_llbust_attempt_q, err_llbust_failed_q}), + .err_out({xu_pc_err_llbust_attempt, xu_pc_err_llbust_failed}) + ); + + // Decrementer Logic + assign ex3_dec_upper_zero = ~|dec_q[32:62]; + assign ex3_set_tsr_dis = dec_running & ex3_dec_upper_zero & dec_q[63]; + assign ex3_dec_zero = ex3_dec_upper_zero & ~dec_q[63]; + + assign ex3_gdec_upper_zero = ~|gdec_q[32:62]; + assign ex3_set_gtsr_dis = gdec_running & ex3_gdec_upper_zero & gdec_q[63]; + assign ex3_gdec_zero = ex3_gdec_upper_zero & ~gdec_q[63]; + + assign ex3_udec_upper_zero = ~|udec_q[32:62]; + assign ex3_set_tsr_udis = udec_running & ex3_udec_upper_zero & udec_q[63]; + assign ex3_udec_zero = ex3_udec_upper_zero & ~udec_q[63]; + + // Fixed Interval Timer logic + + assign fit_tb_tap_d = (spr_tcr_fp == 2'b00) ? tb_tap_edge[5] : + (spr_tcr_fp == 2'b01) ? tb_tap_edge[4] : + (spr_tcr_fp == 2'b10) ? tb_tap_edge[3] : + tb_tap_edge[2]; + assign ex3_set_tsr_fis = fit_tb_tap_q; + + assign gfit_tb_tap_d = (spr_gtcr_fp == 2'b00) ? tb_tap_edge[5] : + (spr_gtcr_fp == 2'b01) ? tb_tap_edge[4] : + (spr_gtcr_fp == 2'b10) ? tb_tap_edge[3] : + tb_tap_edge[2]; + assign ex3_set_gtsr_fis = gfit_tb_tap_q; + + // Watchdog Timer Logic + + assign wdog_tb_tap_d = (spr_tcr_wp == 2'b00) ? tb_tap_edge[3] : + (spr_tcr_wp == 2'b01) ? tb_tap_edge[2] : + (spr_tcr_wp == 2'b10) ? tb_tap_edge[9] : + tb_tap_edge[0]; + + assign wdog_pulse = wdog_tb_tap_q | pc_xu_inj_wdt_reset_q; + + assign gwdog_tb_tap_d = (spr_gtcr_wp == 2'b00) ? tb_tap_edge[3] : + (spr_gtcr_wp == 2'b01) ? tb_tap_edge[2] : + (spr_gtcr_wp == 2'b10) ? tb_tap_edge[9] : + tb_tap_edge[0]; + + assign gwdog_pulse = gwdog_tb_tap_q | pc_xu_inj_wdt_reset_q; + + assign ex3_set_tsr_enw = wdog_pulse & ~spr_tsr_enw; + assign ex3_set_tsr_wis = wdog_pulse & spr_tsr_enw & (~spr_tsr_wis); + + assign ex3_set_tsr = {ex3_set_tsr_enw, ex3_set_tsr_wis, ex3_set_tsr_dis, ex3_set_tsr_fis, ex3_set_tsr_udis}; + + assign ex3_set_gtsr_enw = gwdog_pulse & (~spr_gtsr_enw); + assign ex3_set_gtsr_wis = gwdog_pulse & spr_gtsr_enw & (~spr_gtsr_wis); + + assign ex3_set_gtsr = {ex3_set_gtsr_enw, ex3_set_gtsr_wis, ex3_set_gtsr_dis, ex3_set_gtsr_fis}; + + // Resets + assign reset_complete = (reset_3_complete == 1'b1) ? 2'b11 : + (reset_2_complete == 1'b1) ? 2'b10 : + (reset_1_complete == 1'b1) ? 2'b01 : + 2'b00; + + assign wdog_reset_1 = spr_tsr_enw & spr_tsr_wis & (spr_tcr_wrc == 2'b01); + assign wdog_reset_2 = spr_tsr_enw & spr_tsr_wis & (spr_tcr_wrc == 2'b10); + assign wdog_reset_3 = spr_tsr_enw & spr_tsr_wis & (spr_tcr_wrc == 2'b11); + assign reset_wd_request = spr_tsr_enw & spr_tsr_wis & ~(spr_tcr_wrc == 2'b00); + + assign reset_1_request = wdog_reset_1 | (spr_dbcr0_rst == 2'b01); + assign reset_2_request = wdog_reset_2 | (spr_dbcr0_rst == 2'b10); + assign reset_3_request = wdog_reset_3 | (spr_dbcr0_rst == 2'b11); + assign err_wdt_reset_d = (spr_tsr_enw & spr_tsr_wis) & |(spr_tcr_wrc); + + + tri_direct_err_rpt #(.WIDTH(1)) xu_spr_tspr_wdt_err_rpt( + .vd(vdd), + .gd(gnd), + .err_in(err_wdt_reset_q), + .err_out(xu_pc_err_wdt_reset) + ); + + // DBCR0[FT] Freeze timers + assign dbcr0_freeze_timers = spr_dbcr0_ft & (spr_dbsr_ide | dbsr_event); + assign tspr_cspr_freeze_timers = dbcr0_freeze_timers; + + // Debug Enables + + assign iac_us_en[1] = ((~spr_dbcr1_iac1us[0]) & (~spr_dbcr1_iac1us[1])) | (spr_dbcr1_iac1us[0] & (spr_dbcr1_iac1us[1] ~^ spr_msr_pr)); + assign iac_us_en[2] = ((~spr_dbcr1_iac2us[0]) & (~spr_dbcr1_iac2us[1])) | (spr_dbcr1_iac2us[0] & (spr_dbcr1_iac2us[1] ~^ spr_msr_pr)); + assign iac_us_en[3] = ((~spr_dbcr1_iac3us[0]) & (~spr_dbcr1_iac3us[1])) | (spr_dbcr1_iac3us[0] & (spr_dbcr1_iac3us[1] ~^ spr_msr_pr)); + assign iac_us_en[4] = ((~spr_dbcr1_iac4us[0]) & (~spr_dbcr1_iac4us[1])) | (spr_dbcr1_iac4us[0] & (spr_dbcr1_iac4us[1] ~^ spr_msr_pr)); + assign iac_er_en[1] = ((~spr_dbcr1_iac1er[0]) & (~spr_dbcr1_iac1er[1])) | (spr_dbcr1_iac1er[0] & (spr_dbcr1_iac1er[1] ~^ spr_msr_is)); + assign iac_er_en[2] = ((~spr_dbcr1_iac2er[0]) & (~spr_dbcr1_iac2er[1])) | (spr_dbcr1_iac2er[0] & (spr_dbcr1_iac2er[1] ~^ spr_msr_is)); + assign iac_er_en[3] = ((~spr_dbcr1_iac3er[0]) & (~spr_dbcr1_iac3er[1])) | (spr_dbcr1_iac3er[0] & (spr_dbcr1_iac3er[1] ~^ spr_msr_is)); + assign iac_er_en[4] = ((~spr_dbcr1_iac4er[0]) & (~spr_dbcr1_iac4er[1])) | (spr_dbcr1_iac4er[0] & (spr_dbcr1_iac4er[1] ~^ spr_msr_is)); + + assign iac1_en_d = spr_dbcr0_iac1 & iac_us_en[1] & iac_er_en[1]; + assign iac2_en_d = spr_dbcr0_iac2 & iac_us_en[2] & iac_er_en[2]; + assign iac3_en_d = spr_dbcr0_iac3 & iac_us_en[3] & iac_er_en[3]; + assign iac4_en_d = spr_dbcr0_iac4 & iac_us_en[4] & iac_er_en[4]; + assign xu_iu_iac1_en = iac1_en_q; + assign xu_iu_iac2_en = iac2_en_q; + assign xu_iu_iac3_en = iac3_en_q; + assign xu_iu_iac4_en = iac4_en_q; + + // Async Interrupts + assign xu_iu_crit_interrupt = cspr_tspr_sleep_mask & crit_interrupt_q; + assign xu_iu_gwdog_interrupt = cspr_tspr_sleep_mask & gwdog_interrupt_q; + assign xu_iu_wdog_interrupt = cspr_tspr_sleep_mask & wdog_interrupt_q; + assign xu_iu_gdec_interrupt = cspr_tspr_sleep_mask & gdec_interrupt_q; + assign xu_iu_dec_interrupt = cspr_tspr_sleep_mask & dec_interrupt_q; + assign xu_iu_udec_interrupt = cspr_tspr_sleep_mask & udec_interrupt_q; + assign xu_iu_perf_interrupt = cspr_tspr_sleep_mask & perf_interrupt_q; + assign xu_iu_fit_interrupt = cspr_tspr_sleep_mask & fit_interrupt_q; + assign xu_iu_gfit_interrupt = cspr_tspr_sleep_mask & gfit_interrupt_q; + assign xu_iu_ext_interrupt = cspr_tspr_sleep_mask & ext_interrupt_q; + assign xu_iu_external_mchk = cspr_tspr_sleep_mask & mchk_interrupt_q; + + assign mchk_interrupt = cspr_tspr_crit_mask & an_ac_external_mchk_q & (spr_msr_gs | spr_msr_me); + assign crit_interrupt = cspr_tspr_crit_mask & an_ac_crit_interrupt_q & (spr_msr_gs | spr_msr_ce); + assign wdog_interrupt = cspr_tspr_wdog_mask & spr_tsr_wis & (spr_msr_gs | spr_msr_ce) & spr_tcr_wie; + assign dec_interrupt = cspr_tspr_dec_mask & spr_tsr_dis & (spr_msr_gs | spr_msr_ee) & spr_tcr_die; + assign udec_interrupt = cspr_tspr_udec_mask & spr_tsr_udis & (spr_msr_gs | spr_msr_ee) & spr_tcr_udie; + assign perf_interrupt = cspr_tspr_perf_mask & an_ac_perf_interrupt_q & (spr_msr_gs | spr_msr_ee); + assign fit_interrupt = cspr_tspr_fit_mask & spr_tsr_fis & (spr_msr_gs | spr_msr_ee) & spr_tcr_fie; + assign ext_interrupt = cspr_tspr_ext_mask & an_ac_ext_interrupt_q & ((spr_epcr_extgs & spr_msr_gs & spr_msr_ee) | (~spr_epcr_extgs & (spr_msr_gs | spr_msr_ee))); + + assign gwdog_interrupt = cspr_tspr_wdog_mask & spr_gtsr_wis & (spr_msr_gs & spr_msr_ce) & spr_gtcr_wie; + assign gdec_interrupt = cspr_tspr_dec_mask & spr_gtsr_dis & (spr_msr_gs & spr_msr_ee) & spr_gtcr_die; + assign gfit_interrupt = cspr_tspr_fit_mask & spr_gtsr_fis & (spr_msr_gs & spr_msr_ee) & spr_gtcr_fie; + + assign tspr_cspr_pm_wake_up = mchk_interrupt_q | + crit_interrupt_q | + wdog_interrupt_q | + dec_interrupt_q | + udec_interrupt_q | + perf_interrupt_q | + fit_interrupt_q | + ext_interrupt_q | + gwdog_interrupt_q | + gdec_interrupt_q | + gfit_interrupt_q; + + assign tspr_cspr_async_int = {an_ac_ext_interrupt_q, an_ac_crit_interrupt_q, an_ac_perf_interrupt_q}; + + assign tspr_cspr_gpir_match = cspr_tspr_dbell_pirtag == gpir_do[51:64]; + + // MSR Override + + assign mux_msr_pr = (cspr_tspr_msrovride_en == 1'b1) ? msrovride_pr_q : spr_msr_pr; + assign mux_msr_gs = (cspr_tspr_msrovride_en == 1'b1) ? msrovride_gs_q : spr_msr_gs; + assign mux_msr_de = (cspr_tspr_msrovride_en == 1'b1) ? msrovride_de_q : spr_msr_de; + + assign mux_msr_gs_d = {3{mux_msr_gs}}; + assign mux_msr_pr_d = {1{mux_msr_pr}}; + + assign udec_en = ram_active_q | spr_tcr_ud; + + generate + if (`EFF_IFAR_ARCH > 30) + begin : int_rest_ifar_gen + assign int_rest_ifar[62-`EFF_IFAR_ARCH:31] = (srr0_q[64-`EFF_IFAR_ARCH:33] & {`EFF_IFAR_ARCH-30{(iu_rfi_q & spr_srr1_cm)}}) | + (gsrr0_q[64-`EFF_IFAR_ARCH:33] & {`EFF_IFAR_ARCH-30{(iu_rfgi_q & spr_gsrr1_cm)}}) | + (csrr0_q[64-`EFF_IFAR_ARCH:33] & {`EFF_IFAR_ARCH-30{(iu_rfci_q & spr_csrr1_cm)}}) | + (mcsrr0_q[64-`EFF_IFAR_ARCH:33] & {`EFF_IFAR_ARCH-30{(iu_rfmci_q & spr_mcsrr1_cm)}}) ; + end + endgenerate + assign int_rest_ifar[32:61] = (srr0_q[34:63] & {30{iu_rfi_q}}) | + (gsrr0_q[34:63] & {30{iu_rfgi_q}}) | + (csrr0_q[34:63] & {30{iu_rfci_q}}) | + (mcsrr0_q[34:63] & {30{iu_rfmci_q}}); + + assign int_rest_act = iu_rfi_q | iu_rfgi_q | iu_rfci_q | iu_rfmci_q; + + // IO signal assignments + assign tspr_epcr_icm = spr_epcr_icm; + assign tspr_epcr_gicm = spr_epcr_gicm; + assign tspr_msr_de = mux_msr_de; + assign tspr_msr_cm = spr_msr_cm; + assign tspr_msr_is = spr_msr_is; + assign tspr_msr_gs = mux_msr_gs_q[2]; + assign tspr_msr_pr = mux_msr_pr_q[0]; + assign tspr_msr_ee = spr_msr_ee; + assign tspr_msr_ce = spr_msr_ce; + assign tspr_msr_me = spr_msr_me; + assign tspr_msr_fe0 = spr_msr_fe0; + assign tspr_msr_fe1 = spr_msr_fe1; + assign tspr_fp_precise = spr_msr_fe0 | spr_msr_fe1; + assign tspr_epcr_extgs = spr_epcr_extgs; + assign dbsr_event = |(dbsr_q[45:63]); + assign xu_iu_dbsr_ide = spr_dbsr_ide & dbsr_event & spr_msr_de & dbcr0_q[43] & ~(epcr_q[59] & ~spr_msr_gs & ~spr_msr_pr); + assign single_instr_mode_d = spr_ccr3_si | spr_msr_fe0 | spr_msr_fe1 | instr_trace_mode; + assign xu_iu_single_instr_mode = single_instr_mode_2_q; + assign machine_check_d = |(mcsr_q); + assign ac_tc_machine_check = machine_check_q; + assign tspr_cspr_ex2_np1_flush = ex2_is_mtspr_q & (ex2_dbcr0_wdec | ex2_epcr_wdec); + + // Debug + assign tspr_debug = {12{1'b0}}; + + assign ex2_srr0_re2 = iu_rfi_q; + assign ex2_gsrr0_re2 = iu_rfgi_q; + assign ex2_csrr0_re2 = iu_rfci_q; + assign ex2_mcsrr0_re2 = iu_rfmci_q; + + generate + if (a2mode == 0 & hvmode == 0) + begin : readmux_00 + assign ex3_tspr_rt_d = + (ccr3_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr3_re }}) | + (dbcr0_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_dbcr0_re }}) | + (dbcr1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_dbcr1_re }}) | + (dbsr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_dbsr_re }}) | + (dear_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_dear_re }}) | + (dec_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_dec_re }}) | + (dnhdr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_dnhdr_re }}) | + (esr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_esr_re }}) | + (iar_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_iar_re }}) | + (msr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_is_mfmsr }}) | + (siar_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_siar_re }}) | + (srr0_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{(ex2_srr0_re | ex2_srr0_re2)}}) | + (srr1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_srr1_re }}) | + (xucr1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xucr1_re }}); + end + endgenerate + generate + if (a2mode == 0 & hvmode == 1) + begin : readmux_01 + assign ex3_tspr_rt_d = + (ccr3_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr3_re }}) | + (dbcr0_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_dbcr0_re }}) | + (dbcr1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_dbcr1_re }}) | + (dbsr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_dbsr_re }}) | + (dear_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_dear_re }}) | + (dec_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_dec_re }}) | + (dnhdr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_dnhdr_re }}) | + (epcr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_epcr_re }}) | + (esr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_esr_re }}) | + (gdear_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_gdear_re }}) | + (gdec_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_gdec_re }}) | + (gdecar_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_gdecar_re }}) | + (gesr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_gesr_re }}) | + (gpir_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_gpir_re }}) | + (gsrr0_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{(ex2_gsrr0_re | ex2_gsrr0_re2)}}) | + (gsrr1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_gsrr1_re }}) | + (gtcr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_gtcr_re }}) | + (gtsr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_gtsr_re }}) | + (iar_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_iar_re }}) | + (msr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_is_mfmsr }}) | + (msrp_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_msrp_re }}) | + (siar_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_siar_re }}) | + (srr0_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{(ex2_srr0_re | ex2_srr0_re2)}}) | + (srr1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_srr1_re }}) | + (xucr1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xucr1_re }}); + end + endgenerate + generate + if (a2mode == 1 & hvmode == 0) + begin : readmux_10 + assign ex3_tspr_rt_d = + (ccr3_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr3_re }}) | + (csrr0_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{(ex2_csrr0_re | ex2_csrr0_re2)}}) | + (csrr1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_csrr1_re }}) | + (dbcr0_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_dbcr0_re }}) | + (dbcr1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_dbcr1_re }}) | + (dbsr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_dbsr_re }}) | + (dear_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_dear_re }}) | + (dec_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_dec_re }}) | + (decar_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_decar_re }}) | + (dnhdr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_dnhdr_re }}) | + (esr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_esr_re }}) | + (iar_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_iar_re }}) | + (mcsr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_mcsr_re }}) | + (mcsrr0_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{(ex2_mcsrr0_re | ex2_mcsrr0_re2)}}) | + (mcsrr1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_mcsrr1_re }}) | + (msr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_is_mfmsr }}) | + (siar_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_siar_re }}) | + (srr0_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{(ex2_srr0_re | ex2_srr0_re2)}}) | + (srr1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_srr1_re }}) | + (tcr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tcr_re }}) | + (tsr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tsr_re }}) | + (udec_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_udec_re }}) | + (xucr1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xucr1_re }}); + end + endgenerate + generate + if (a2mode == 1 & hvmode == 1) + begin : readmux_11 + assign ex3_tspr_rt_d = + (ccr3_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr3_re }}) | + (csrr0_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{(ex2_csrr0_re | ex2_csrr0_re2)}}) | + (csrr1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_csrr1_re }}) | + (dbcr0_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_dbcr0_re }}) | + (dbcr1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_dbcr1_re }}) | + (dbsr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_dbsr_re }}) | + (dear_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_dear_re }}) | + (dec_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_dec_re }}) | + (decar_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_decar_re }}) | + (dnhdr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_dnhdr_re }}) | + (epcr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_epcr_re }}) | + (esr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_esr_re }}) | + (gdear_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_gdear_re }}) | + (gdec_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_gdec_re }}) | + (gdecar_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_gdecar_re }}) | + (gesr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_gesr_re }}) | + (gpir_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_gpir_re }}) | + (gsrr0_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{(ex2_gsrr0_re | ex2_gsrr0_re2)}}) | + (gsrr1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_gsrr1_re }}) | + (gtcr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_gtcr_re }}) | + (gtsr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_gtsr_re }}) | + (iar_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_iar_re }}) | + (mcsr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_mcsr_re }}) | + (mcsrr0_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{(ex2_mcsrr0_re | ex2_mcsrr0_re2)}}) | + (mcsrr1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_mcsrr1_re }}) | + (msr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_is_mfmsr }}) | + (msrp_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_msrp_re }}) | + (siar_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_siar_re }}) | + (srr0_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{(ex2_srr0_re | ex2_srr0_re2)}}) | + (srr1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_srr1_re }}) | + (tcr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tcr_re }}) | + (tsr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tsr_re }}) | + (udec_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_udec_re }}) | + (xucr1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xucr1_re }}); + end + endgenerate + + generate + genvar i; + for (i=0;i<`GPR_WIDTH;i=i+1) + begin : ex3_tid_rpwr_gen + assign tspr_cspr_ex3_tspr_rt[i] = ex3_tspr_rt_q[i] & ex3_tid_rpwr_q[i % (`GPR_WIDTH/8)]; + end + endgenerate + + // Reads + assign ex2_pir_rdec = (ex2_instr[11:20] == 10'b1111001000); // 286 + assign ex2_ccr3_rdec = (ex2_instr[11:20] == 10'b1010111111); // 1013 + assign ex2_csrr0_rdec = (ex2_instr[11:20] == 10'b1101000001); // 58 + assign ex2_csrr1_rdec = (ex2_instr[11:20] == 10'b1101100001); // 59 + assign ex2_dbcr0_rdec = (ex2_instr[11:20] == 10'b1010001001); // 308 + assign ex2_dbcr1_rdec = (ex2_instr[11:20] == 10'b1010101001); // 309 + assign ex2_dbsr_rdec = (ex2_instr[11:20] == 10'b1000001001); // 304 + assign ex2_dear_rdec = (ex2_instr[11:20] == 10'b1110100001); // 61 + assign ex2_dec_rdec = (ex2_instr[11:20] == 10'b1011000000); // 22 + assign ex2_decar_rdec = (ex2_instr[11:20] == 10'b1011000001); // 54 + assign ex2_dnhdr_rdec = (ex2_instr[11:20] == 10'b1011111010); // 855 + assign ex2_epcr_rdec = (ex2_instr[11:20] == 10'b1001101001); // 307 + assign ex2_esr_rdec = (ex2_instr[11:20] == 10'b1111000001); // 62 + assign ex2_gdear_rdec = (ex2_instr[11:20] == 10'b1110101011); // 381 + assign ex2_gdec_rdec = (ex2_instr[11:20] == 10'b1011001011); // 374 + assign ex2_gdecar_rdec = (ex2_instr[11:20] == 10'b1010100001); // 53 + assign ex2_gesr_rdec = (ex2_instr[11:20] == 10'b1111101011); // 383 + assign ex2_gpir_rdec = (ex2_instr[11:20] == 10'b1111001011); // 382 + assign ex2_gsrr0_rdec = (ex2_instr[11:20] == 10'b1101001011); // 378 + assign ex2_gsrr1_rdec = (ex2_instr[11:20] == 10'b1101101011); // 379 + assign ex2_gtcr_rdec = (ex2_instr[11:20] == 10'b1011101011); // 375 + assign ex2_gtsr_rdec = (ex2_instr[11:20] == 10'b1100001011); // 376 + assign ex2_iar_rdec = (ex2_instr[11:20] == 10'b1001011011); // 882 + assign ex2_mcsr_rdec = (ex2_instr[11:20] == 10'b1110010001); // 572 + assign ex2_mcsrr0_rdec = (ex2_instr[11:20] == 10'b1101010001); // 570 + assign ex2_mcsrr1_rdec = (ex2_instr[11:20] == 10'b1101110001); // 571 + assign ex2_msrp_rdec = (ex2_instr[11:20] == 10'b1011101001); // 311 + assign ex2_siar_rdec = (ex2_instr[11:20] == 10'b1110011000); // 796 + assign ex2_srr0_rdec = (ex2_instr[11:20] == 10'b1101000000); // 26 + assign ex2_srr1_rdec = (ex2_instr[11:20] == 10'b1101100000); // 27 + assign ex2_tcr_rdec = (ex2_instr[11:20] == 10'b1010001010); // 340 + assign ex2_tsr_rdec = (ex2_instr[11:20] == 10'b1000001010); // 336 + assign ex2_udec_rdec = udec_en & + (ex2_instr[11:20] == 10'b0011010001); // 550 + assign ex2_xucr1_rdec = (ex2_instr[11:20] == 10'b1001111010); // 851 + assign ex2_ccr3_re = ex2_ccr3_rdec; + assign ex2_csrr0_re = ex2_csrr0_rdec; + assign ex2_csrr1_re = ex2_csrr1_rdec; + assign ex2_dbcr0_re = ex2_dbcr0_rdec; + assign ex2_dbcr1_re = ex2_dbcr1_rdec; + assign ex2_dbsr_re = ex2_dbsr_rdec; + assign ex2_dear_re = ex2_dear_rdec & ~mux_msr_gs_q[0]; + assign ex2_dec_re = ex2_dec_rdec & ~mux_msr_gs_q[0]; + assign ex2_decar_re = ex2_decar_rdec & ~mux_msr_gs_q[0]; + assign ex2_dnhdr_re = ex2_dnhdr_rdec; + assign ex2_epcr_re = ex2_epcr_rdec; + assign ex2_esr_re = ex2_esr_rdec & ~mux_msr_gs_q[0]; + assign ex2_gdear_re = (ex2_gdear_rdec | (ex2_dear_rdec & mux_msr_gs_q[0])); + assign ex2_gdec_re = (ex2_gdec_rdec | (ex2_dec_rdec & mux_msr_gs_q[0])); + assign ex2_gdecar_re = (ex2_gdecar_rdec | (ex2_decar_rdec & mux_msr_gs_q[0])); + assign ex2_gesr_re = (ex2_gesr_rdec | (ex2_esr_rdec & mux_msr_gs_q[0])); + assign ex2_gpir_re = (ex2_gpir_rdec | (ex2_pir_rdec & mux_msr_gs_q[0])); + assign ex2_gsrr0_re = (ex2_gsrr0_rdec | (ex2_srr0_rdec & mux_msr_gs_q[0])); + assign ex2_gsrr1_re = (ex2_gsrr1_rdec | (ex2_srr1_rdec & mux_msr_gs_q[0])); + assign ex2_gtcr_re = (ex2_gtcr_rdec | (ex2_tcr_rdec & mux_msr_gs_q[0])); + assign ex2_gtsr_re = (ex2_gtsr_rdec | (ex2_tsr_rdec & mux_msr_gs_q[0])); + assign ex2_iar_re = ex2_iar_rdec; + assign ex2_mcsr_re = ex2_mcsr_rdec; + assign ex2_mcsrr0_re = ex2_mcsrr0_rdec; + assign ex2_mcsrr1_re = ex2_mcsrr1_rdec; + assign ex2_msrp_re = ex2_msrp_rdec; + assign ex2_siar_re = ex2_siar_rdec; + assign ex2_srr0_re = ex2_srr0_rdec & ~mux_msr_gs_q[0]; + assign ex2_srr1_re = ex2_srr1_rdec & ~mux_msr_gs_q[0]; + assign ex2_tcr_re = ex2_tcr_rdec & ~mux_msr_gs_q[0]; + assign ex2_tsr_re = ex2_tsr_rdec & ~mux_msr_gs_q[0]; + assign ex2_udec_re = ex2_udec_rdec; + assign ex2_xucr1_re = ex2_xucr1_rdec; + + // Writes + assign ex2_ccr3_wdec = ex2_ccr3_rdec; + assign ex2_csrr0_wdec = ex2_csrr0_rdec; + assign ex2_csrr1_wdec = ex2_csrr1_rdec; + assign ex2_dbcr0_wdec = ex2_dbcr0_rdec; + assign ex2_dbcr1_wdec = ex2_dbcr1_rdec; + assign ex2_dbsr_wdec = ex2_dbsr_rdec; + assign ex2_dbsrwr_wdec = (ex2_instr[11:20] == 10'b1001001001); // 306 + assign ex2_dear_wdec = ex2_dear_rdec; + assign ex2_dec_wdec = ex2_dec_rdec; + assign ex2_decar_wdec = ex2_decar_rdec; + assign ex2_dnhdr_wdec = ex2_dnhdr_rdec; + assign ex2_epcr_wdec = ex2_epcr_rdec; + assign ex2_esr_wdec = ex2_esr_rdec; + assign ex2_gdear_wdec = ex2_gdear_rdec; + assign ex2_gdec_wdec = ex2_gdec_rdec; + assign ex2_gdecar_wdec = ex2_gdecar_rdec; + assign ex2_gesr_wdec = ex2_gesr_rdec; + assign ex2_gpir_wdec = (ex2_instr[11:20] == 10'b1111001011); // 382 + assign ex2_gsrr0_wdec = ex2_gsrr0_rdec; + assign ex2_gsrr1_wdec = ex2_gsrr1_rdec; + assign ex2_gtcr_wdec = ex2_gtcr_rdec; + assign ex2_gtsr_wdec = ex2_gtsr_rdec; + assign ex2_gtsrwr_wdec = (ex2_instr[11:20] == 10'b1110000001); // 60 + assign ex2_iar_wdec = ex2_iar_rdec; + assign ex2_mcsr_wdec = ex2_mcsr_rdec; + assign ex2_mcsrr0_wdec = ex2_mcsrr0_rdec; + assign ex2_mcsrr1_wdec = ex2_mcsrr1_rdec; + assign ex2_msrp_wdec = ex2_msrp_rdec; + assign ex2_siar_wdec = ex2_siar_rdec; + assign ex2_srr0_wdec = ex2_srr0_rdec; + assign ex2_srr1_wdec = ex2_srr1_rdec; + assign ex2_tcr_wdec = ex2_tcr_rdec; + assign ex2_tsr_wdec = ex2_tsr_rdec; + assign ex2_udec_wdec = udec_en & + ex2_udec_rdec; + assign ex2_xucr1_wdec = ex2_xucr1_rdec; + assign ex2_ccr3_we = ex2_ccr3_wdec; + assign ex2_csrr0_we = ex2_csrr0_wdec; + assign ex2_csrr1_we = ex2_csrr1_wdec; + assign ex2_dbcr0_we = ex2_dbcr0_wdec; + assign ex2_dbcr1_we = ex2_dbcr1_wdec; + assign ex2_dbsr_we = ex2_dbsr_wdec; + assign ex2_dbsrwr_we = ex2_dbsrwr_wdec; + assign ex2_dear_we = ex2_dear_wdec & ~mux_msr_gs_q[1]; + assign ex2_dec_we = ex2_dec_wdec & ~mux_msr_gs_q[1]; + assign ex2_decar_we = ex2_decar_wdec & ~mux_msr_gs_q[1]; + assign ex2_dnhdr_we = ex2_dnhdr_wdec; + assign ex2_epcr_we = ex2_epcr_wdec; + assign ex2_esr_we = ex2_esr_wdec & ~mux_msr_gs_q[1]; + assign ex2_gdear_we = (ex2_gdear_wdec | (ex2_dear_wdec & mux_msr_gs_q[1])); + assign ex2_gdec_we = (ex2_gdec_wdec | (ex2_dec_wdec & mux_msr_gs_q[1])); + assign ex2_gdecar_we = (ex2_gdecar_wdec | (ex2_decar_wdec & mux_msr_gs_q[1])); + assign ex2_gesr_we = (ex2_gesr_wdec | (ex2_esr_wdec & mux_msr_gs_q[1])); + assign ex2_gpir_we = ex2_gpir_wdec; + assign ex2_gsrr0_we = (ex2_gsrr0_wdec | (ex2_srr0_wdec & mux_msr_gs_q[1])); + assign ex2_gsrr1_we = (ex2_gsrr1_wdec | (ex2_srr1_wdec & mux_msr_gs_q[1])); + assign ex2_gtcr_we = (ex2_gtcr_wdec | (ex2_tcr_wdec & mux_msr_gs_q[1])); + assign ex2_gtsr_we = (ex2_gtsr_wdec | (ex2_tsr_wdec & mux_msr_gs_q[1])); + assign ex2_gtsrwr_we = ex2_gtsrwr_wdec; + assign ex2_iar_we = ex2_iar_wdec; + assign ex2_mcsr_we = ex2_mcsr_wdec; + assign ex2_mcsrr0_we = ex2_mcsrr0_wdec; + assign ex2_mcsrr1_we = ex2_mcsrr1_wdec; + assign ex2_msrp_we = ex2_msrp_wdec; + assign ex2_siar_we = ex2_siar_wdec; + assign ex2_srr0_we = ex2_srr0_wdec & ~mux_msr_gs_q[1]; + assign ex2_srr1_we = ex2_srr1_wdec & ~mux_msr_gs_q[1]; + assign ex2_tcr_we = ex2_tcr_wdec & ~mux_msr_gs_q[1]; + assign ex2_tsr_we = ex2_tsr_wdec & ~mux_msr_gs_q[1]; + assign ex2_udec_we = ex2_udec_wdec; + assign ex2_xucr1_we = ex2_xucr1_wdec; + + // Write Enable + assign ex3_ccr3_wdec = (ex3_instr[11:20] == 10'b1010111111); // 1013 + assign ex3_csrr0_wdec = (ex3_instr[11:20] == 10'b1101000001); // 58 + assign ex3_csrr1_wdec = (ex3_instr[11:20] == 10'b1101100001); // 59 + assign ex3_dbcr0_wdec = (ex3_instr[11:20] == 10'b1010001001); // 308 + assign ex3_dbcr1_wdec = (ex3_instr[11:20] == 10'b1010101001); // 309 + assign ex3_dbsr_wdec = (ex3_instr[11:20] == 10'b1000001001); // 304 + assign ex3_dbsrwr_wdec = (ex3_instr[11:20] == 10'b1001001001); // 306 + assign ex3_dear_wdec = (ex3_instr[11:20] == 10'b1110100001); // 61 + assign ex3_dec_wdec = (ex3_instr[11:20] == 10'b1011000000); // 22 + assign ex3_decar_wdec = (ex3_instr[11:20] == 10'b1011000001); // 54 + assign ex3_dnhdr_wdec = (ex3_instr[11:20] == 10'b1011111010); // 855 + assign ex3_epcr_wdec = (ex3_instr[11:20] == 10'b1001101001); // 307 + assign ex3_esr_wdec = (ex3_instr[11:20] == 10'b1111000001); // 62 + assign ex3_gdear_wdec = (ex3_instr[11:20] == 10'b1110101011); // 381 + assign ex3_gdec_wdec = (ex3_instr[11:20] == 10'b1011001011); // 374 + assign ex3_gdecar_wdec = (ex3_instr[11:20] == 10'b1010100001); // 53 + assign ex3_gesr_wdec = (ex3_instr[11:20] == 10'b1111101011); // 383 + assign ex3_gpir_wdec = (ex3_instr[11:20] == 10'b1111001011); // 382 + assign ex3_gsrr0_wdec = (ex3_instr[11:20] == 10'b1101001011); // 378 + assign ex3_gsrr1_wdec = (ex3_instr[11:20] == 10'b1101101011); // 379 + assign ex3_gtcr_wdec = (ex3_instr[11:20] == 10'b1011101011); // 375 + assign ex3_gtsr_wdec = (ex3_instr[11:20] == 10'b1100001011); // 376 + assign ex3_gtsrwr_wdec = (ex3_instr[11:20] == 10'b1110000001); // 60 + assign ex3_iar_wdec = (ex3_instr[11:20] == 10'b1001011011); // 882 + assign ex3_mcsr_wdec = (ex3_instr[11:20] == 10'b1110010001); // 572 + assign ex3_mcsrr0_wdec = (ex3_instr[11:20] == 10'b1101010001); // 570 + assign ex3_mcsrr1_wdec = (ex3_instr[11:20] == 10'b1101110001); // 571 + assign ex3_msr_wdec = ex3_is_mtmsr; + assign ex3_msrp_wdec = (ex3_instr[11:20] == 10'b1011101001); // 311 + assign ex3_siar_wdec = (ex3_instr[11:20] == 10'b1110011000); // 796 + assign ex3_srr0_wdec = (ex3_instr[11:20] == 10'b1101000000); // 26 + assign ex3_srr1_wdec = (ex3_instr[11:20] == 10'b1101100000); // 27 + assign ex3_tcr_wdec = (ex3_instr[11:20] == 10'b1010001010); // 340 + assign ex3_tsr_wdec = (ex3_instr[11:20] == 10'b1000001010); // 336 + assign ex3_udec_wdec = udec_en & + (ex3_instr[11:20] == 10'b0011010001); // 550 + assign ex3_xucr1_wdec = (ex3_instr[11:20] == 10'b1001111010); // 851 + assign ex3_ccr3_we = ex3_spr_we & ex3_is_mtspr & ex3_ccr3_wdec; + assign ex3_csrr0_we = ex3_spr_we & ex3_is_mtspr & ex3_csrr0_wdec; + assign ex3_csrr1_we = ex3_spr_we & ex3_is_mtspr & ex3_csrr1_wdec; + assign ex3_dbcr0_we = ex3_spr_we & ex3_is_mtspr & ex3_dbcr0_wdec; + assign ex3_dbcr1_we = ex3_spr_we & ex3_is_mtspr & ex3_dbcr1_wdec; + assign ex3_dbsr_we = ex3_spr_we & ex3_is_mtspr & ex3_dbsr_wdec; + assign ex3_dbsrwr_we = ex3_spr_we & ex3_is_mtspr & ex3_dbsrwr_wdec; + assign ex3_dear_we = ex3_spr_we & ex3_is_mtspr & ex3_dear_wdec & ~mux_msr_gs_q[1]; + assign ex3_dec_we = ex3_spr_we & ex3_is_mtspr & ex3_dec_wdec & ~mux_msr_gs_q[1]; + assign ex3_decar_we = ex3_spr_we & ex3_is_mtspr & ex3_decar_wdec & ~mux_msr_gs_q[1]; + assign ex3_dnhdr_we = ex3_spr_we & ex3_is_mtspr & ex3_dnhdr_wdec; + assign ex3_epcr_we = ex3_spr_we & ex3_is_mtspr & ex3_epcr_wdec; + assign ex3_esr_we = ex3_spr_we & ex3_is_mtspr & ex3_esr_wdec & ~mux_msr_gs_q[1]; + assign ex3_gdear_we = ex3_spr_we & ex3_is_mtspr & (ex3_gdear_wdec | (ex3_dear_wdec & mux_msr_gs_q[1])); + assign ex3_gdec_we = ex3_spr_we & ex3_is_mtspr & (ex3_gdec_wdec | (ex3_dec_wdec & mux_msr_gs_q[1])); + assign ex3_gdecar_we = ex3_spr_we & ex3_is_mtspr & (ex3_gdecar_wdec | (ex3_decar_wdec & mux_msr_gs_q[1])); + assign ex3_gesr_we = ex3_spr_we & ex3_is_mtspr & (ex3_gesr_wdec | (ex3_esr_wdec & mux_msr_gs_q[1])); + assign ex3_gpir_we = ex3_spr_we & ex3_is_mtspr & ex3_gpir_wdec; + assign ex3_gsrr0_we = ex3_spr_we & ex3_is_mtspr & (ex3_gsrr0_wdec | (ex3_srr0_wdec & mux_msr_gs_q[1])); + assign ex3_gsrr1_we = ex3_spr_we & ex3_is_mtspr & (ex3_gsrr1_wdec | (ex3_srr1_wdec & mux_msr_gs_q[1])); + assign ex3_gtcr_we = ex3_spr_we & ex3_is_mtspr & (ex3_gtcr_wdec | (ex3_tcr_wdec & mux_msr_gs_q[1])); + assign ex3_gtsr_we = ex3_spr_we & ex3_is_mtspr & (ex3_gtsr_wdec | (ex3_tsr_wdec & mux_msr_gs_q[1])); + assign ex3_gtsrwr_we = ex3_spr_we & ex3_is_mtspr & ex3_gtsrwr_wdec; + assign ex3_iar_we = ex3_spr_we & ex3_is_mtspr & ex3_iar_wdec; + assign ex3_mcsr_we = ex3_spr_we & ex3_is_mtspr & ex3_mcsr_wdec; + assign ex3_mcsrr0_we = ex3_spr_we & ex3_is_mtspr & ex3_mcsrr0_wdec; + assign ex3_mcsrr1_we = ex3_spr_we & ex3_is_mtspr & ex3_mcsrr1_wdec; + assign ex3_msr_we = ex3_spr_we & ex3_msr_wdec; + assign ex3_msrp_we = ex3_spr_we & ex3_is_mtspr & ex3_msrp_wdec; + assign ex3_siar_we = ex3_spr_we & ex3_is_mtspr & ex3_siar_wdec; + assign ex3_srr0_we = ex3_spr_we & ex3_is_mtspr & ex3_srr0_wdec & ~mux_msr_gs_q[1]; + assign ex3_srr1_we = ex3_spr_we & ex3_is_mtspr & ex3_srr1_wdec & ~mux_msr_gs_q[1]; + assign ex3_tcr_we = ex3_spr_we & ex3_is_mtspr & ex3_tcr_wdec & ~mux_msr_gs_q[1]; + assign ex3_tsr_we = ex3_spr_we & ex3_is_mtspr & ex3_tsr_wdec & ~mux_msr_gs_q[1]; + assign ex3_udec_we = ex3_spr_we & ex3_is_mtspr & ex3_udec_wdec; + assign ex3_xucr1_we = ex3_spr_we & ex3_is_mtspr & ex3_xucr1_wdec; + + // Illegal SPR checks + generate + if (a2mode == 0 & hvmode == 0) + begin : ill_spr_00 + assign tspr_cspr_illeg_mtspr_b = + ex2_ccr3_wdec | ex2_dbcr0_wdec | ex2_dbcr1_wdec + | ex2_dbsr_wdec | ex2_dear_wdec | ex2_dec_wdec + | ex2_dnhdr_wdec | ex2_esr_wdec | ex2_iar_wdec + | ex2_siar_wdec | ex2_srr0_wdec | ex2_srr1_wdec + | ex2_xucr1_wdec ; + + assign tspr_cspr_illeg_mfspr_b = + ex2_ccr3_rdec | ex2_dbcr0_rdec | ex2_dbcr1_rdec + | ex2_dbsr_rdec | ex2_dear_rdec | ex2_dec_rdec + | ex2_dnhdr_rdec | ex2_esr_rdec | ex2_iar_rdec + | ex2_siar_rdec | ex2_srr0_rdec | ex2_srr1_rdec + | ex2_xucr1_rdec ; + + assign tspr_cspr_hypv_mtspr = + ex2_ccr3_we | ex2_dbcr0_we | ex2_dbcr1_we + | ex2_dbsr_we | ex2_dnhdr_we | ex2_iar_we + | ex2_xucr1_we ; + + assign tspr_cspr_hypv_mfspr = + ex2_ccr3_re | ex2_dbcr0_re | ex2_dbcr1_re + | ex2_dbsr_re | ex2_dnhdr_re | ex2_iar_re + | ex2_xucr1_re ; + end + endgenerate + + generate + if (a2mode == 0 & hvmode == 1) + begin : ill_spr_01 + assign tspr_cspr_illeg_mtspr_b = + ex2_ccr3_wdec | ex2_dbcr0_wdec | ex2_dbcr1_wdec + | ex2_dbsr_wdec | ex2_dbsrwr_wdec | ex2_dear_wdec + | ex2_dec_wdec | ex2_dnhdr_wdec | ex2_epcr_wdec + | ex2_esr_wdec | ex2_gdear_wdec | ex2_gdec_wdec + | ex2_gdecar_wdec | ex2_gesr_wdec | ex2_gpir_wdec + | ex2_gsrr0_wdec | ex2_gsrr1_wdec | ex2_gtcr_wdec + | ex2_gtsr_wdec | ex2_gtsrwr_wdec | ex2_iar_wdec + | ex2_msrp_wdec | ex2_siar_wdec | ex2_srr0_wdec + | ex2_srr1_wdec | ex2_xucr1_wdec ; + + assign tspr_cspr_illeg_mfspr_b = + ex2_ccr3_rdec | ex2_dbcr0_rdec | ex2_dbcr1_rdec + | ex2_dbsr_rdec | ex2_dear_rdec | ex2_dec_rdec + | ex2_dnhdr_rdec | ex2_epcr_rdec | ex2_esr_rdec + | ex2_gdear_rdec | ex2_gdec_rdec | ex2_gdecar_rdec + | ex2_gesr_rdec | ex2_gpir_rdec | ex2_gsrr0_rdec + | ex2_gsrr1_rdec | ex2_gtcr_rdec | ex2_gtsr_rdec + | ex2_iar_rdec | ex2_msrp_rdec | ex2_siar_rdec + | ex2_srr0_rdec | ex2_srr1_rdec | ex2_xucr1_rdec ; + + assign tspr_cspr_hypv_mtspr = + ex2_ccr3_we | ex2_dbcr0_we | ex2_dbcr1_we + | ex2_dbsr_we | ex2_dbsrwr_we | ex2_dnhdr_we + | ex2_epcr_we | ex2_gpir_we | ex2_gtsrwr_we + | ex2_iar_we | ex2_msrp_we | ex2_xucr1_we ; + + assign tspr_cspr_hypv_mfspr = + ex2_ccr3_re | ex2_dbcr0_re | ex2_dbcr1_re + | ex2_dbsr_re | ex2_dnhdr_re | ex2_epcr_re + | ex2_iar_re | ex2_msrp_re | ex2_xucr1_re ; + end + endgenerate + + generate + if (a2mode == 1 & hvmode == 0) + begin : ill_spr_10 + assign tspr_cspr_illeg_mtspr_b = + ex2_ccr3_wdec | ex2_csrr0_wdec | ex2_csrr1_wdec + | ex2_dbcr0_wdec | ex2_dbcr1_wdec | ex2_dbsr_wdec + | ex2_dear_wdec | ex2_dec_wdec | ex2_decar_wdec + | ex2_dnhdr_wdec | ex2_esr_wdec | ex2_iar_wdec + | ex2_mcsr_wdec | ex2_mcsrr0_wdec | ex2_mcsrr1_wdec + | ex2_siar_wdec | ex2_srr0_wdec | ex2_srr1_wdec + | ex2_tcr_wdec | ex2_tsr_wdec | ex2_udec_wdec + | ex2_xucr1_wdec ; + + assign tspr_cspr_illeg_mfspr_b = + ex2_ccr3_rdec | ex2_csrr0_rdec | ex2_csrr1_rdec + | ex2_dbcr0_rdec | ex2_dbcr1_rdec | ex2_dbsr_rdec + | ex2_dear_rdec | ex2_dec_rdec | ex2_decar_rdec + | ex2_dnhdr_rdec | ex2_esr_rdec | ex2_iar_rdec + | ex2_mcsr_rdec | ex2_mcsrr0_rdec | ex2_mcsrr1_rdec + | ex2_siar_rdec | ex2_srr0_rdec | ex2_srr1_rdec + | ex2_tcr_rdec | ex2_tsr_rdec | ex2_udec_rdec + | ex2_xucr1_rdec ; + + assign tspr_cspr_hypv_mtspr = + ex2_ccr3_we | ex2_csrr0_we | ex2_csrr1_we + | ex2_dbcr0_we | ex2_dbcr1_we | ex2_dbsr_we + | ex2_dnhdr_we | ex2_iar_we | ex2_mcsr_we + | ex2_mcsrr0_we | ex2_mcsrr1_we | ex2_xucr1_we ; + + assign tspr_cspr_hypv_mfspr = + ex2_ccr3_re | ex2_csrr0_re | ex2_csrr1_re + | ex2_dbcr0_re | ex2_dbcr1_re | ex2_dbsr_re + | ex2_dnhdr_re | ex2_iar_re | ex2_mcsr_re + | ex2_mcsrr0_re | ex2_mcsrr1_re | ex2_xucr1_re ; + end + endgenerate + + generate + if (a2mode == 1 & hvmode == 1) + begin : ill_spr_11 + assign tspr_cspr_illeg_mtspr_b = + ex2_ccr3_wdec | ex2_csrr0_wdec | ex2_csrr1_wdec + | ex2_dbcr0_wdec | ex2_dbcr1_wdec | ex2_dbsr_wdec + | ex2_dbsrwr_wdec | ex2_dear_wdec | ex2_dec_wdec + | ex2_decar_wdec | ex2_dnhdr_wdec | ex2_epcr_wdec + | ex2_esr_wdec | ex2_gdear_wdec | ex2_gdec_wdec + | ex2_gdecar_wdec | ex2_gesr_wdec | ex2_gpir_wdec + | ex2_gsrr0_wdec | ex2_gsrr1_wdec | ex2_gtcr_wdec + | ex2_gtsr_wdec | ex2_gtsrwr_wdec | ex2_iar_wdec + | ex2_mcsr_wdec | ex2_mcsrr0_wdec | ex2_mcsrr1_wdec + | ex2_msrp_wdec | ex2_siar_wdec | ex2_srr0_wdec + | ex2_srr1_wdec | ex2_tcr_wdec | ex2_tsr_wdec + | ex2_udec_wdec | ex2_xucr1_wdec ; + + assign tspr_cspr_illeg_mfspr_b = + ex2_ccr3_rdec | ex2_csrr0_rdec | ex2_csrr1_rdec + | ex2_dbcr0_rdec | ex2_dbcr1_rdec | ex2_dbsr_rdec + | ex2_dear_rdec | ex2_dec_rdec | ex2_decar_rdec + | ex2_dnhdr_rdec | ex2_epcr_rdec | ex2_esr_rdec + | ex2_gdear_rdec | ex2_gdec_rdec | ex2_gdecar_rdec + | ex2_gesr_rdec | ex2_gpir_rdec | ex2_gsrr0_rdec + | ex2_gsrr1_rdec | ex2_gtcr_rdec | ex2_gtsr_rdec + | ex2_iar_rdec | ex2_mcsr_rdec | ex2_mcsrr0_rdec + | ex2_mcsrr1_rdec | ex2_msrp_rdec | ex2_siar_rdec + | ex2_srr0_rdec | ex2_srr1_rdec | ex2_tcr_rdec + | ex2_tsr_rdec | ex2_udec_rdec | ex2_xucr1_rdec ; + + assign tspr_cspr_hypv_mtspr = + ex2_ccr3_we | ex2_csrr0_we | ex2_csrr1_we + | ex2_dbcr0_we | ex2_dbcr1_we | ex2_dbsr_we + | ex2_dbsrwr_we | ex2_dnhdr_we | ex2_epcr_we + | ex2_gpir_we | ex2_gtsrwr_we | ex2_iar_we + | ex2_mcsr_we | ex2_mcsrr0_we | ex2_mcsrr1_we + | ex2_msrp_we | ex2_xucr1_we ; + + assign tspr_cspr_hypv_mfspr = + ex2_ccr3_re | ex2_csrr0_re | ex2_csrr1_re + | ex2_dbcr0_re | ex2_dbcr1_re | ex2_dbsr_re + | ex2_dnhdr_re | ex2_epcr_re | ex2_iar_re + | ex2_mcsr_re | ex2_mcsrr0_re | ex2_mcsrr1_re + | ex2_msrp_re | ex2_xucr1_re ; + end + endgenerate + + assign spr_ccr3_en_eepri = ccr3_q[62]; + assign spr_ccr3_si = ccr3_q[63]; + assign spr_csrr1_cm = csrr1_q[50]; + assign spr_dbcr0_idm = dbcr0_q[43]; + assign spr_dbcr0_rst = dbcr0_q[44:45]; + assign spr_dbcr0_icmp = dbcr0_q[46]; + assign spr_dbcr0_brt = dbcr0_q[47]; + assign spr_dbcr0_irpt = dbcr0_q[48]; + assign spr_dbcr0_trap = dbcr0_q[49]; + assign spr_dbcr0_iac1 = dbcr0_q[50]; + assign spr_dbcr0_iac2 = dbcr0_q[51]; + assign spr_dbcr0_iac3 = dbcr0_q[52]; + assign spr_dbcr0_iac4 = dbcr0_q[53]; + assign spr_dbcr0_dac1 = dbcr0_q[54:55]; + assign spr_dbcr0_dac2 = dbcr0_q[56:57]; + assign spr_dbcr0_ret = dbcr0_q[58]; + assign spr_dbcr0_dac3 = dbcr0_q[59:60]; + assign spr_dbcr0_dac4 = dbcr0_q[61:62]; + assign spr_dbcr0_ft = dbcr0_q[63]; + assign spr_dbcr1_iac1us = dbcr1_q[46:47]; + assign spr_dbcr1_iac1er = dbcr1_q[48:49]; + assign spr_dbcr1_iac2us = dbcr1_q[50:51]; + assign spr_dbcr1_iac2er = dbcr1_q[52:53]; + assign spr_dbcr1_iac12m = dbcr1_q[54]; + assign spr_dbcr1_iac3us = dbcr1_q[55:56]; + assign spr_dbcr1_iac3er = dbcr1_q[57:58]; + assign spr_dbcr1_iac4us = dbcr1_q[59:60]; + assign spr_dbcr1_iac4er = dbcr1_q[61:62]; + assign spr_dbcr1_iac34m = dbcr1_q[63]; + assign spr_dbsr_ide = dbsr_q[44]; + assign spr_epcr_extgs = epcr_q[54]; + assign spr_epcr_dtlbgs = epcr_q[55]; + assign spr_epcr_itlbgs = epcr_q[56]; + assign spr_epcr_dsigs = epcr_q[57]; + assign spr_epcr_isigs = epcr_q[58]; + assign spr_epcr_duvd = epcr_q[59]; + assign spr_epcr_icm = epcr_q[60]; + assign spr_epcr_gicm = epcr_q[61]; + assign spr_epcr_dgtmi = epcr_q[62]; + assign xu_mm_spr_epcr_dmiuh = epcr_q[63]; + assign spr_gsrr1_cm = gsrr1_q[50]; + assign spr_gtcr_wp = gtcr_q[54:55]; + assign spr_gtcr_wrc = gtcr_q[56:57]; + assign spr_gtcr_wie = gtcr_q[58]; + assign spr_gtcr_die = gtcr_q[59]; + assign spr_gtcr_fp = gtcr_q[60:61]; + assign spr_gtcr_fie = gtcr_q[62]; + assign spr_gtcr_are = gtcr_q[63]; + assign spr_gtsr_enw = gtsr_q[60]; + assign spr_gtsr_wis = gtsr_q[61]; + assign spr_gtsr_dis = gtsr_q[62]; + assign spr_gtsr_fis = gtsr_q[63]; + assign spr_mcsrr1_cm = mcsrr1_q[50]; + assign spr_msr_cm = msr_q[50]; + assign spr_msr_gs = msr_q[51]; + assign spr_msr_ucle = msr_q[52]; + assign spr_msr_spv = msr_q[53]; + assign spr_msr_ce = msr_q[54]; + assign spr_msr_ee = msr_q[55]; + assign spr_msr_pr = msr_q[56]; + assign spr_msr_fp = msr_q[57]; + assign spr_msr_me = msr_q[58]; + assign spr_msr_fe0 = msr_q[59]; + assign spr_msr_de = msr_q[60]; + assign spr_msr_fe1 = msr_q[61]; + assign spr_msr_is = msr_q[62]; + assign spr_msr_ds = msr_q[63]; + assign spr_msrp_uclep = msrp_q[62]; + assign spr_srr1_cm = srr1_q[50]; + assign spr_tcr_wp = tcr_q[52:53]; + assign spr_tcr_wrc = tcr_q[54:55]; + assign spr_tcr_wie = tcr_q[56]; + assign spr_tcr_die = tcr_q[57]; + assign spr_tcr_fp = tcr_q[58:59]; + assign spr_tcr_fie = tcr_q[60]; + assign spr_tcr_are = tcr_q[61]; + assign spr_tcr_udie = tcr_q[62]; + assign spr_tcr_ud = tcr_q[63]; + assign spr_tsr_enw = tsr_q[59]; + assign spr_tsr_wis = tsr_q[60]; + assign spr_tsr_dis = tsr_q[61]; + assign spr_tsr_fis = tsr_q[62]; + assign spr_tsr_udis = tsr_q[63]; + assign spr_xucr1_ll_tb_sel = xucr1_q[59:61]; + assign spr_xucr1_ll_sel = xucr1_q[62]; + assign spr_xucr1_ll_en = xucr1_q[63]; + + // CCR3 + assign ex3_ccr3_di = { ex3_spr_wd[62:62] , //EN_EEPRI + ex3_spr_wd[63:63] }; //SI + + assign ccr3_do = { tidn[0:0] , + tidn[0:31] , ///// + tidn[32:61] , ///// + ccr3_q[62:62] , //EN_EEPRI + ccr3_q[63:63] }; //SI + // CSRR0 + assign ex3_csrr0_di = { ex3_spr_wd[62-(`EFF_IFAR_ARCH):61]}; //SRR0 + + assign csrr0_do = { tidn[0:62-(`EFF_IFAR_ARCH)] , + csrr0_q[64-(`EFF_IFAR_ARCH):63] , //SRR0 + tidn[62:63] }; ///// + // CSRR1 + assign ex3_csrr1_di = { ex3_spr_wd[32:32] , //CM + ex3_spr_wd[35:35] , //GS + ex3_spr_wd[37:37] , //UCLE + ex3_spr_wd[38:38] , //SPV + ex3_spr_wd[46:46] , //CE + ex3_spr_wd[48:48] , //EE + ex3_spr_wd[49:49] , //PR + ex3_spr_wd[50:50] , //FP + ex3_spr_wd[51:51] , //ME + ex3_spr_wd[52:52] , //FE0 + ex3_spr_wd[54:54] , //DE + ex3_spr_wd[55:55] , //FE1 + ex3_spr_wd[58:58] , //IS + ex3_spr_wd[59:59] }; //DS + + assign csrr1_do = { tidn[0:0] , + tidn[0:31] , ///// + csrr1_q[50:50] , //CM + tidn[33:34] , ///// + csrr1_q[51:51] , //GS + tidn[36:36] , ///// + csrr1_q[52:52] , //UCLE + csrr1_q[53:53] , //SPV + tidn[39:45] , ///// + csrr1_q[54:54] , //CE + tidn[47:47] , ///// + csrr1_q[55:55] , //EE + csrr1_q[56:56] , //PR + csrr1_q[57:57] , //FP + csrr1_q[58:58] , //ME + csrr1_q[59:59] , //FE0 + tidn[53:53] , ///// + csrr1_q[60:60] , //DE + csrr1_q[61:61] , //FE1 + tidn[56:57] , ///// + csrr1_q[62:62] , //IS + csrr1_q[63:63] , //DS + tidn[60:63] }; ///// + // DBCR0 + assign ex3_dbcr0_di = { ex3_spr_wd[33:33] , //IDM + ex3_spr_wd[34:35] , //RST + ex3_spr_wd[36:36] , //ICMP + ex3_spr_wd[37:37] , //BRT + ex3_spr_wd[38:38] , //IRPT + ex3_spr_wd[39:39] , //TRAP + ex3_spr_wd[40:40] , //IAC1 + ex3_spr_wd[41:41] , //IAC2 + ex3_spr_wd[42:42] , //IAC3 + ex3_spr_wd[43:43] , //IAC4 + ex3_spr_wd[44:45] , //DAC1 + ex3_spr_wd[46:47] , //DAC2 + ex3_spr_wd[48:48] , //RET + ex3_spr_wd[59:60] , //DAC3 + ex3_spr_wd[61:62] , //DAC4 + ex3_spr_wd[63:63] }; //FT + + assign dbcr0_do = { tidn[0:0] , + tidn[0:31] , ///// + spr_dbcr0_edm , //EDM + dbcr0_q[43:43] , //IDM + dbcr0_q[44:45] , //RST + dbcr0_q[46:46] , //ICMP + dbcr0_q[47:47] , //BRT + dbcr0_q[48:48] , //IRPT + dbcr0_q[49:49] , //TRAP + dbcr0_q[50:50] , //IAC1 + dbcr0_q[51:51] , //IAC2 + dbcr0_q[52:52] , //IAC3 + dbcr0_q[53:53] , //IAC4 + dbcr0_q[54:55] , //DAC1 + dbcr0_q[56:57] , //DAC2 + dbcr0_q[58:58] , //RET + tidn[49:58] , ///// + dbcr0_q[59:60] , //DAC3 + dbcr0_q[61:62] , //DAC4 + dbcr0_q[63:63] }; //FT + // DBCR1 + assign ex3_dbcr1_di = { ex3_spr_wd[32:33] , //IAC1US + ex3_spr_wd[34:35] , //IAC1ER + ex3_spr_wd[36:37] , //IAC2US + ex3_spr_wd[38:39] , //IAC2ER + ex3_spr_wd[41:41] , //IAC12M + ex3_spr_wd[48:49] , //IAC3US + ex3_spr_wd[50:51] , //IAC3ER + ex3_spr_wd[52:53] , //IAC4US + ex3_spr_wd[54:55] , //IAC4ER + ex3_spr_wd[57:57] }; //IAC34M + + assign dbcr1_do = { tidn[0:0] , + tidn[0:31] , ///// + dbcr1_q[46:47] , //IAC1US + dbcr1_q[48:49] , //IAC1ER + dbcr1_q[50:51] , //IAC2US + dbcr1_q[52:53] , //IAC2ER + tidn[40:40] , ///// + dbcr1_q[54:54] , //IAC12M + tidn[42:47] , ///// + dbcr1_q[55:56] , //IAC3US + dbcr1_q[57:58] , //IAC3ER + dbcr1_q[59:60] , //IAC4US + dbcr1_q[61:62] , //IAC4ER + tidn[56:56] , ///// + dbcr1_q[63:63] , //IAC34M + tidn[58:63] }; ///// + // DBSR + assign ex3_dbsr_di = { ex3_spr_wd[32:32] , //IDE + ex3_spr_wd[33:33] , //UDE + ex3_spr_wd[36:36] , //ICMP + ex3_spr_wd[37:37] , //BRT + ex3_spr_wd[38:38] , //IRPT + ex3_spr_wd[39:39] , //TRAP + ex3_spr_wd[40:40] , //IAC1 + ex3_spr_wd[41:41] , //IAC2 + ex3_spr_wd[42:42] , //IAC3 + ex3_spr_wd[43:43] , //IAC4 + ex3_spr_wd[44:44] , //DAC1R + ex3_spr_wd[45:45] , //DAC1W + ex3_spr_wd[46:46] , //DAC2R + ex3_spr_wd[47:47] , //DAC2W + ex3_spr_wd[48:48] , //RET + ex3_spr_wd[59:59] , //DAC3R + ex3_spr_wd[60:60] , //DAC3W + ex3_spr_wd[61:61] , //DAC4R + ex3_spr_wd[62:62] , //DAC4W + ex3_spr_wd[63:63] }; //IVC + + assign dbsr_do = { tidn[0:0] , + tidn[0:31] , ///// + dbsr_q[44:44] , //IDE + dbsr_q[45:45] , //UDE + dbsr_mrr_q[0:1] , //MRR + dbsr_q[46:46] , //ICMP + dbsr_q[47:47] , //BRT + dbsr_q[48:48] , //IRPT + dbsr_q[49:49] , //TRAP + dbsr_q[50:50] , //IAC1 + dbsr_q[51:51] , //IAC2 + dbsr_q[52:52] , //IAC3 + dbsr_q[53:53] , //IAC4 + dbsr_q[54:54] , //DAC1R + dbsr_q[55:55] , //DAC1W + dbsr_q[56:56] , //DAC2R + dbsr_q[57:57] , //DAC2W + dbsr_q[58:58] , //RET + tidn[49:58] , ///// + dbsr_q[59:59] , //DAC3R + dbsr_q[60:60] , //DAC3W + dbsr_q[61:61] , //DAC4R + dbsr_q[62:62] , //DAC4W + dbsr_q[63:63] }; //IVC + // DEAR + assign ex3_dear_di = { ex3_spr_wd[64-(`GPR_WIDTH):63] }; //DEAR + + assign dear_do = { tidn[0:64-(`GPR_WIDTH)] , + dear_q[64-(`GPR_WIDTH):63] }; //DEAR + // DEC + assign ex3_dec_di = { ex3_spr_wd[32:63] }; //DEC + + assign dec_do = { tidn[0:0] , + tidn[0:31] , ///// + dec_q[32:63] }; //DEC + // DECAR + assign ex3_decar_di = { ex3_spr_wd[32:63] }; //DECAR + + assign decar_do = { tidn[0:0] , + tidn[0:31] , ///// + decar_q[32:63] }; //DECAR + // DNHDR + assign ex3_dnhdr_di = { ex3_spr_wd[48:52] , //DUI + ex3_spr_wd[54:63] }; //DUIS + + assign dnhdr_do = { tidn[0:0] , + tidn[0:31] , ///// + tidn[32:47] , ///// + dnhdr_q[49:53] , //DUI + tidn[53:53] , ///// + dnhdr_q[54:63] }; //DUIS + // EPCR + assign ex3_epcr_di = { ex3_spr_wd[32:32] , //EXTGS + ex3_spr_wd[33:33] , //DTLBGS + ex3_spr_wd[34:34] , //ITLBGS + ex3_spr_wd[35:35] , //DSIGS + ex3_spr_wd[36:36] , //ISIGS + ex3_spr_wd[37:37] , //DUVD + ex3_spr_wd[38:38] , //ICM + ex3_spr_wd[39:39] , //GICM + ex3_spr_wd[40:40] , //DGTMI + ex3_spr_wd[41:41] }; //DMIUH + + assign epcr_do = { tidn[0:0] , + tidn[0:31] , ///// + epcr_q[54:54] , //EXTGS + epcr_q[55:55] , //DTLBGS + epcr_q[56:56] , //ITLBGS + epcr_q[57:57] , //DSIGS + epcr_q[58:58] , //ISIGS + epcr_q[59:59] , //DUVD + epcr_q[60:60] , //ICM + epcr_q[61:61] , //GICM + epcr_q[62:62] , //DGTMI + epcr_q[63:63] , //DMIUH + tidn[42:63] }; ///// + // ESR + assign ex3_esr_di = { ex3_spr_wd[36:36] , //PIL + ex3_spr_wd[37:37] , //PPR + ex3_spr_wd[38:38] , //PTR + ex3_spr_wd[39:39] , //FP + ex3_spr_wd[40:40] , //ST + ex3_spr_wd[42:42] , //DLK0 + ex3_spr_wd[43:43] , //DLK1 + ex3_spr_wd[44:44] , //AP + ex3_spr_wd[45:45] , //PUO + ex3_spr_wd[46:46] , //BO + ex3_spr_wd[47:47] , //PIE + ex3_spr_wd[49:49] , //UCT + ex3_spr_wd[53:53] , //DATA + ex3_spr_wd[54:54] , //TLBI + ex3_spr_wd[55:55] , //PT + ex3_spr_wd[56:56] , //SPV + ex3_spr_wd[57:57] }; //EPID + + assign esr_do = { tidn[0:0] , + tidn[0:31] , ///// + tidn[32:35] , ///// + esr_q[47:47] , //PIL + esr_q[48:48] , //PPR + esr_q[49:49] , //PTR + esr_q[50:50] , //FP + esr_q[51:51] , //ST + tidn[41:41] , ///// + esr_q[52:52] , //DLK0 + esr_q[53:53] , //DLK1 + esr_q[54:54] , //AP + esr_q[55:55] , //PUO + esr_q[56:56] , //BO + esr_q[57:57] , //PIE + tidn[48:48] , ///// + esr_q[58:58] , //UCT + tidn[50:52] , ///// + esr_q[59:59] , //DATA + esr_q[60:60] , //TLBI + esr_q[61:61] , //PT + esr_q[62:62] , //SPV + esr_q[63:63] , //EPID + tidn[58:63] }; ///// + // GDEAR + assign ex3_gdear_di = { ex3_spr_wd[64-(`GPR_WIDTH):63] }; //GDEAR + + assign gdear_do = { tidn[0:64-(`GPR_WIDTH)] , + gdear_q[64-(`GPR_WIDTH):63] }; //GDEAR + // GDEC + assign ex3_gdec_di = { ex3_spr_wd[32:63] }; //DEC + + assign gdec_do = { tidn[0:0] , + tidn[0:31] , ///// + gdec_q[32:63] }; //DEC + // GDECAR + assign ex3_gdecar_di = { ex3_spr_wd[32:63] }; //DECAR + + assign gdecar_do = { tidn[0:0] , + tidn[0:31] , ///// + gdecar_q[32:63] }; //DECAR + // GESR + assign ex3_gesr_di = { ex3_spr_wd[36:36] , //PIL + ex3_spr_wd[37:37] , //PPR + ex3_spr_wd[38:38] , //PTR + ex3_spr_wd[39:39] , //FP + ex3_spr_wd[40:40] , //ST + ex3_spr_wd[42:42] , //DLK0 + ex3_spr_wd[43:43] , //DLK1 + ex3_spr_wd[44:44] , //AP + ex3_spr_wd[45:45] , //PUO + ex3_spr_wd[46:46] , //BO + ex3_spr_wd[47:47] , //PIE + ex3_spr_wd[49:49] , //UCT + ex3_spr_wd[53:53] , //DATA + ex3_spr_wd[54:54] , //TLBI + ex3_spr_wd[55:55] , //PT + ex3_spr_wd[56:56] , //SPV + ex3_spr_wd[57:57] }; //EPID + + assign gesr_do = { tidn[0:0] , + tidn[0:31] , ///// + tidn[32:35] , ///// + gesr_q[47:47] , //PIL + gesr_q[48:48] , //PPR + gesr_q[49:49] , //PTR + gesr_q[50:50] , //FP + gesr_q[51:51] , //ST + tidn[41:41] , ///// + gesr_q[52:52] , //DLK0 + gesr_q[53:53] , //DLK1 + gesr_q[54:54] , //AP + gesr_q[55:55] , //PUO + gesr_q[56:56] , //BO + gesr_q[57:57] , //PIE + tidn[48:48] , ///// + gesr_q[58:58] , //UCT + tidn[50:52] , ///// + gesr_q[59:59] , //DATA + gesr_q[60:60] , //TLBI + gesr_q[61:61] , //PT + gesr_q[62:62] , //SPV + gesr_q[63:63] , //EPID + tidn[58:63] }; ///// + // GPIR + assign ex3_gpir_di = { ex3_spr_wd[32:49] , //VPTAG + ex3_spr_wd[50:63] }; //DBTAG + + assign gpir_do = { tidn[0:0] , + tidn[0:31] , ///// + gpir_q[32:49] , //VPTAG + gpir_q[50:63] }; //DBTAG + // GSRR0 + assign ex3_gsrr0_di = { ex3_spr_wd[62-(`EFF_IFAR_ARCH):61]}; //GSRR0 + + assign gsrr0_do = { tidn[0:62-(`EFF_IFAR_ARCH)] , + gsrr0_q[64-(`EFF_IFAR_ARCH):63] , //GSRR0 + tidn[62:63] }; ///// + // GSRR1 + assign ex3_gsrr1_di = { ex3_spr_wd[32:32] , //CM + ex3_spr_wd[35:35] , //GS + ex3_spr_wd[37:37] , //UCLE + ex3_spr_wd[38:38] , //SPV + ex3_spr_wd[46:46] , //CE + ex3_spr_wd[48:48] , //EE + ex3_spr_wd[49:49] , //PR + ex3_spr_wd[50:50] , //FP + ex3_spr_wd[51:51] , //ME + ex3_spr_wd[52:52] , //FE0 + ex3_spr_wd[54:54] , //DE + ex3_spr_wd[55:55] , //FE1 + ex3_spr_wd[58:58] , //IS + ex3_spr_wd[59:59] }; //DS + + assign gsrr1_do = { tidn[0:0] , + tidn[0:31] , ///// + gsrr1_q[50:50] , //CM + tidn[33:34] , ///// + gsrr1_q[51:51] , //GS + tidn[36:36] , ///// + gsrr1_q[52:52] , //UCLE + gsrr1_q[53:53] , //SPV + tidn[39:45] , ///// + gsrr1_q[54:54] , //CE + tidn[47:47] , ///// + gsrr1_q[55:55] , //EE + gsrr1_q[56:56] , //PR + gsrr1_q[57:57] , //FP + gsrr1_q[58:58] , //ME + gsrr1_q[59:59] , //FE0 + tidn[53:53] , ///// + gsrr1_q[60:60] , //DE + gsrr1_q[61:61] , //FE1 + tidn[56:57] , ///// + gsrr1_q[62:62] , //IS + gsrr1_q[63:63] , //DS + tidn[60:63] }; ///// + // GTCR + assign ex3_gtcr_di = { ex3_spr_wd[32:33] , //WP + ex3_spr_wd[34:35] , //WRC + ex3_spr_wd[36:36] , //WIE + ex3_spr_wd[37:37] , //DIE + ex3_spr_wd[38:39] , //FP + ex3_spr_wd[40:40] , //FIE + ex3_spr_wd[41:41] }; //ARE + + assign gtcr_do = { tidn[0:0] , + tidn[0:31] , ///// + gtcr_q[54:55] , //WP + gtcr_q[56:57] , //WRC + gtcr_q[58:58] , //WIE + gtcr_q[59:59] , //DIE + gtcr_q[60:61] , //FP + gtcr_q[62:62] , //FIE + gtcr_q[63:63] , //ARE + tidn[42:63] }; ///// + // GTSR + assign ex3_gtsr_di = { ex3_spr_wd[32:32] , //ENW + ex3_spr_wd[33:33] , //WIS + ex3_spr_wd[36:36] , //DIS + ex3_spr_wd[37:37] }; //FIS + + assign gtsr_do = { tidn[0:0] , + tidn[0:31] , ///// + gtsr_q[60:60] , //ENW + gtsr_q[61:61] , //WIS + tsr_wrs_q[0:1] , //WRS + gtsr_q[62:62] , //DIS + gtsr_q[63:63] , //FIS + tidn[38:63] }; ///// + // IAR + assign iar_do = { tidn[0:64-(`EFF_IFAR_ARCH+2)] , + ex2_iar[62-`EFF_IFAR_ARCH:61] , //IAR + tidn[62:63] }; ///// + // MCSR + assign ex3_mcsr_di = { ex3_spr_wd[48:48] , //DPOVR + ex3_spr_wd[49:49] , //DDMH + ex3_spr_wd[50:50] , //TLBIVAXSR + ex3_spr_wd[51:51] , //TLBLRUPE + ex3_spr_wd[52:52] , //IL2ECC + ex3_spr_wd[53:53] , //DL2ECC + ex3_spr_wd[54:54] , //DDPE + ex3_spr_wd[55:55] , //EXT + ex3_spr_wd[56:56] , //DCPE + ex3_spr_wd[57:57] , //IEMH + ex3_spr_wd[58:58] , //DEMH + ex3_spr_wd[59:59] , //TLBMH + ex3_spr_wd[60:60] , //IEPE + ex3_spr_wd[61:61] , //DEPE + ex3_spr_wd[62:62] }; //TLBPE + + assign mcsr_do = { tidn[0:0] , + tidn[0:31] , ///// + tidn[32:47] , ///// + mcsr_q[49:49] , //DPOVR + mcsr_q[50:50] , //DDMH + mcsr_q[51:51] , //TLBIVAXSR + mcsr_q[52:52] , //TLBLRUPE + mcsr_q[53:53] , //IL2ECC + mcsr_q[54:54] , //DL2ECC + mcsr_q[55:55] , //DDPE + mcsr_q[56:56] , //EXT + mcsr_q[57:57] , //DCPE + mcsr_q[58:58] , //IEMH + mcsr_q[59:59] , //DEMH + mcsr_q[60:60] , //TLBMH + mcsr_q[61:61] , //IEPE + mcsr_q[62:62] , //DEPE + mcsr_q[63:63] , //TLBPE + tidn[63:63] }; ///// + // MCSRR0 + assign ex3_mcsrr0_di = { ex3_spr_wd[62-(`EFF_IFAR_ARCH):61]}; //SRR0 + + assign mcsrr0_do = { tidn[0:62-(`EFF_IFAR_ARCH)] , + mcsrr0_q[64-(`EFF_IFAR_ARCH):63] , //SRR0 + tidn[62:63] }; ///// + // MCSRR1 + assign ex3_mcsrr1_di = { ex3_spr_wd[32:32] , //CM + ex3_spr_wd[35:35] , //GS + ex3_spr_wd[37:37] , //UCLE + ex3_spr_wd[38:38] , //SPV + ex3_spr_wd[46:46] , //CE + ex3_spr_wd[48:48] , //EE + ex3_spr_wd[49:49] , //PR + ex3_spr_wd[50:50] , //FP + ex3_spr_wd[51:51] , //ME + ex3_spr_wd[52:52] , //FE0 + ex3_spr_wd[54:54] , //DE + ex3_spr_wd[55:55] , //FE1 + ex3_spr_wd[58:58] , //IS + ex3_spr_wd[59:59] }; //DS + + assign mcsrr1_do = { tidn[0:0] , + tidn[0:31] , ///// + mcsrr1_q[50:50] , //CM + tidn[33:34] , ///// + mcsrr1_q[51:51] , //GS + tidn[36:36] , ///// + mcsrr1_q[52:52] , //UCLE + mcsrr1_q[53:53] , //SPV + tidn[39:45] , ///// + mcsrr1_q[54:54] , //CE + tidn[47:47] , ///// + mcsrr1_q[55:55] , //EE + mcsrr1_q[56:56] , //PR + mcsrr1_q[57:57] , //FP + mcsrr1_q[58:58] , //ME + mcsrr1_q[59:59] , //FE0 + tidn[53:53] , ///// + mcsrr1_q[60:60] , //DE + mcsrr1_q[61:61] , //FE1 + tidn[56:57] , ///// + mcsrr1_q[62:62] , //IS + mcsrr1_q[63:63] , //DS + tidn[60:63] }; ///// + // MSR + assign ex3_msr_di = { ex3_spr_wd[32:32] , //CM + ex3_spr_wd[35:35] , //GS + ex3_spr_wd[37:37] , //UCLE + ex3_spr_wd[38:38] , //SPV + ex3_spr_wd[46:46] , //CE + ex3_spr_wd[48:48] , //EE + ex3_spr_wd[49:49] , //PR + ex3_spr_wd[50:50] , //FP + ex3_spr_wd[51:51] , //ME + ex3_spr_wd[52:52] , //FE0 + ex3_spr_wd[54:54] , //DE + ex3_spr_wd[55:55] , //FE1 + ex3_spr_wd[58:58] , //IS + ex3_spr_wd[59:59] }; //DS + + assign msr_do = { tidn[0:0] , + tidn[0:31] , ///// + msr_q[50:50] , //CM + tidn[33:34] , ///// + msr_q[51:51] , //GS + tidn[36:36] , ///// + msr_q[52:52] , //UCLE + msr_q[53:53] , //SPV + tidn[39:45] , ///// + msr_q[54:54] , //CE + tidn[47:47] , ///// + msr_q[55:55] , //EE + msr_q[56:56] , //PR + msr_q[57:57] , //FP + msr_q[58:58] , //ME + msr_q[59:59] , //FE0 + tidn[53:53] , ///// + msr_q[60:60] , //DE + msr_q[61:61] , //FE1 + tidn[56:57] , ///// + msr_q[62:62] , //IS + msr_q[63:63] , //DS + tidn[60:63] }; ///// + // MSRP + assign ex3_msrp_di = { ex3_spr_wd[37:37] , //UCLEP + ex3_spr_wd[54:54] }; //DEP + + assign msrp_do = { tidn[0:0] , + tidn[0:31] , ///// + tidn[32:36] , ///// + msrp_q[62:62] , //UCLEP + tidn[38:53] , ///// + msrp_q[63:63] , //DEP + tidn[55:63] }; ///// + // SIAR + assign ex3_siar_di = { ex3_spr_wd[62-(`EFF_IFAR_ARCH):61], //IAR + ex3_spr_wd[62:62] , //GS + ex3_spr_wd[63:63] }; //PR + + assign siar_do = { tidn[0:62-(`EFF_IFAR_ARCH)] , + siar_q[62-(`EFF_IFAR_ARCH):61] , //IAR + siar_q[62:62] , //GS + siar_q[63:63] }; //PR + // SRR0 + assign ex3_srr0_di = { ex3_spr_wd[62-(`EFF_IFAR_ARCH):61]}; //SRR0 + + assign srr0_do = { tidn[0:62-(`EFF_IFAR_ARCH)] , + srr0_q[64-(`EFF_IFAR_ARCH):63] , //SRR0 + tidn[62:63] }; ///// + // SRR1 + assign ex3_srr1_di = { ex3_spr_wd[32:32] , //CM + ex3_spr_wd[35:35] , //GS + ex3_spr_wd[37:37] , //UCLE + ex3_spr_wd[38:38] , //SPV + ex3_spr_wd[46:46] , //CE + ex3_spr_wd[48:48] , //EE + ex3_spr_wd[49:49] , //PR + ex3_spr_wd[50:50] , //FP + ex3_spr_wd[51:51] , //ME + ex3_spr_wd[52:52] , //FE0 + ex3_spr_wd[54:54] , //DE + ex3_spr_wd[55:55] , //FE1 + ex3_spr_wd[58:58] , //IS + ex3_spr_wd[59:59] }; //DS + + assign srr1_do = { tidn[0:0] , + tidn[0:31] , ///// + srr1_q[50:50] , //CM + tidn[33:34] , ///// + srr1_q[51:51] , //GS + tidn[36:36] , ///// + srr1_q[52:52] , //UCLE + srr1_q[53:53] , //SPV + tidn[39:45] , ///// + srr1_q[54:54] , //CE + tidn[47:47] , ///// + srr1_q[55:55] , //EE + srr1_q[56:56] , //PR + srr1_q[57:57] , //FP + srr1_q[58:58] , //ME + srr1_q[59:59] , //FE0 + tidn[53:53] , ///// + srr1_q[60:60] , //DE + srr1_q[61:61] , //FE1 + tidn[56:57] , ///// + srr1_q[62:62] , //IS + srr1_q[63:63] , //DS + tidn[60:63] }; ///// + // TCR + assign ex3_tcr_di = { ex3_spr_wd[32:33] , //WP + ex3_spr_wd[34:35] , //WRC + ex3_spr_wd[36:36] , //WIE + ex3_spr_wd[37:37] , //DIE + ex3_spr_wd[38:39] , //FP + ex3_spr_wd[40:40] , //FIE + ex3_spr_wd[41:41] , //ARE + ex3_spr_wd[42:42] , //UDIE + ex3_spr_wd[51:51] }; //UD + + assign tcr_do = { tidn[0:0] , + tidn[0:31] , ///// + tcr_q[52:53] , //WP + tcr_q[54:55] , //WRC + tcr_q[56:56] , //WIE + tcr_q[57:57] , //DIE + tcr_q[58:59] , //FP + tcr_q[60:60] , //FIE + tcr_q[61:61] , //ARE + tcr_q[62:62] , //UDIE + tidn[43:50] , ///// + tcr_q[63:63] , //UD + tidn[52:63] }; ///// + // TSR + assign ex3_tsr_di = { ex3_spr_wd[32:32] , //ENW + ex3_spr_wd[33:33] , //WIS + ex3_spr_wd[36:36] , //DIS + ex3_spr_wd[37:37] , //FIS + ex3_spr_wd[38:38] }; //UDIS + + assign tsr_do = { tidn[0:0] , + tidn[0:31] , ///// + tsr_q[59:59] , //ENW + tsr_q[60:60] , //WIS + tsr_wrs_q[0:1] , //WRS + tsr_q[61:61] , //DIS + tsr_q[62:62] , //FIS + tsr_q[63:63] , //UDIS + tidn[39:63] }; ///// + // UDEC + assign ex3_udec_di = { ex3_spr_wd[32:63] }; //UDEC + + assign udec_do = { tidn[0:0] , + tidn[0:31] , ///// + udec_q[32:63] }; //UDEC + // XUCR1 + assign ex3_xucr1_di = { ex3_spr_wd[57:59] , //LL_TB_SEL + ex3_spr_wd[62:62] , //LL_SEL + ex3_spr_wd[63:63] }; //LL_EN + + assign xucr1_do = { tidn[0:0] , + tidn[0:31] , ///// + tidn[32:56] , ///// + xucr1_q[59:61] , //LL_TB_SEL + llstate[0:1] , //LL_STATE + xucr1_q[62:62] , //LL_SEL + xucr1_q[63:63] }; //LL_EN + + // Unused Signals + assign unused_do_bits = |{ + ccr3_do[0:64-`GPR_WIDTH] + ,csrr0_do[0:64-`GPR_WIDTH] + ,csrr1_do[0:64-`GPR_WIDTH] + ,dbcr0_do[0:64-`GPR_WIDTH] + ,dbcr1_do[0:64-`GPR_WIDTH] + ,dbsr_do[0:64-`GPR_WIDTH] + ,dear_do[0:64-`GPR_WIDTH] + ,dec_do[0:64-`GPR_WIDTH] + ,decar_do[0:64-`GPR_WIDTH] + ,dnhdr_do[0:64-`GPR_WIDTH] + ,epcr_do[0:64-`GPR_WIDTH] + ,esr_do[0:64-`GPR_WIDTH] + ,gdear_do[0:64-`GPR_WIDTH] + ,gdec_do[0:64-`GPR_WIDTH] + ,gdecar_do[0:64-`GPR_WIDTH] + ,gesr_do[0:64-`GPR_WIDTH] + ,gpir_do[0:64-`GPR_WIDTH] + ,gsrr0_do[0:64-`GPR_WIDTH] + ,gsrr1_do[0:64-`GPR_WIDTH] + ,gtcr_do[0:64-`GPR_WIDTH] + ,gtsr_do[0:64-`GPR_WIDTH] + ,iar_do[0:64-`GPR_WIDTH] + ,mcsr_do[0:64-`GPR_WIDTH] + ,mcsrr0_do[0:64-`GPR_WIDTH] + ,mcsrr1_do[0:64-`GPR_WIDTH] + ,msr_do[0:64-`GPR_WIDTH] + ,msrp_do[0:64-`GPR_WIDTH] + ,siar_do[0:64-`GPR_WIDTH] + ,srr0_do[0:64-`GPR_WIDTH] + ,srr1_do[0:64-`GPR_WIDTH] + ,tcr_do[0:64-`GPR_WIDTH] + ,tsr_do[0:64-`GPR_WIDTH] + ,udec_do[0:64-`GPR_WIDTH] + ,xucr1_do[0:64-`GPR_WIDTH] + }; + + // Unused Signals + assign unused = |{ex2_siar_we,ex2_dear_we,ex2_dec_we,ex2_gdec_we,ex2_gdecar_we,ex2_gtsr_we,ex2_gtsrwr_we,ex2_gtcr_we,ex2_esr_we,ex2_gdear_we,ex2_gesr_we,ex2_gsrr0_we,ex2_gsrr1_we,ex2_srr0_we,ex2_srr1_we,ex2_udec_we,cspr_tspr_ex1_instr[6:10],cspr_tspr_ex1_instr[31],ex3_gdear_di,exx_act_data[1],iar_act}; + + assign spr_dvc1 = dvc1_q[64-(`GPR_WIDTH):63]; + assign spr_dvc2 = dvc2_q[64 - (`GPR_WIDTH):63]; + + // SPR Latch Instances + tri_ser_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ccr3_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(ccr3_act), + .force_t(ccfg_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(ccfg_sl_thold_0_b), + .sg(sg_0), + .scin(siv_ccfg[ccr3_offset_ccfg:ccr3_offset_ccfg + 2 - 1]), + .scout(sov_ccfg[ccr3_offset_ccfg:ccr3_offset_ccfg + 2 - 1]), + .din(ccr3_d), + .dout(ccr3_q) + ); +generate + if (a2mode == 1) begin : csrr0_latch_gen + tri_ser_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0), .NEEDS_SRESET(1)) csrr0_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(csrr0_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[csrr0_offset:csrr0_offset + `EFF_IFAR_ARCH - 1]), + .scout(sov[csrr0_offset:csrr0_offset + `EFF_IFAR_ARCH - 1]), + .din(csrr0_d), + .dout(csrr0_q) + ); + end + if (a2mode == 0) begin : csrr0_latch_tie + assign csrr0_q = {`EFF_IFAR_ARCH{1'b0}}; + end +endgenerate +generate + if (a2mode == 1) begin : csrr1_latch_gen + tri_ser_rlmreg_p #(.WIDTH(14), .INIT(0), .NEEDS_SRESET(1)) csrr1_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(csrr1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[csrr1_offset:csrr1_offset + 14 - 1]), + .scout(sov[csrr1_offset:csrr1_offset + 14 - 1]), + .din(csrr1_d), + .dout(csrr1_q) + ); + end + if (a2mode == 0) begin : csrr1_latch_tie + assign csrr1_q = {14{1'b0}}; + end +endgenerate + tri_ser_rlmreg_p #(.WIDTH(21), .INIT(0), .NEEDS_SRESET(1)) dbcr0_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(dbcr0_act), + .force_t(dcfg_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(dcfg_sl_thold_0_b), + .sg(sg_0), + .scin(siv_dcfg[dbcr0_offset_dcfg:dbcr0_offset_dcfg + 21 - 1]), + .scout(sov_dcfg[dbcr0_offset_dcfg:dbcr0_offset_dcfg + 21 - 1]), + .din(dbcr0_d), + .dout(dbcr0_q) + ); + tri_ser_rlmreg_p #(.WIDTH(18), .INIT(0), .NEEDS_SRESET(1)) dbcr1_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(dbcr1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[dbcr1_offset:dbcr1_offset + 18 - 1]), + .scout(sov[dbcr1_offset:dbcr1_offset + 18 - 1]), + .din(dbcr1_d), + .dout(dbcr1_q) + ); + tri_ser_rlmreg_p #(.WIDTH(20), .INIT(0), .NEEDS_SRESET(1)) dbsr_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(dbsr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[dbsr_offset:dbsr_offset + 20 - 1]), + .scout(sov[dbsr_offset:dbsr_offset + 20 - 1]), + .din(dbsr_d), + .dout(dbsr_q) + ); + tri_ser_rlmreg_p #(.WIDTH(`GPR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) dear_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(dear_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[dear_offset:dear_offset + `GPR_WIDTH - 1]), + .scout(sov[dear_offset:dear_offset + `GPR_WIDTH - 1]), + .din(dear_d), + .dout(dear_q) + ); + tri_ser_rlmreg_p #(.WIDTH(32), .INIT(2147483647), .NEEDS_SRESET(1)) dec_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(dec_act), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[dec_offset:dec_offset + 32 - 1]), + .scout(sov[dec_offset:dec_offset + 32 - 1]), + .din(dec_d), + .dout(dec_q) + ); +generate + if (a2mode == 1) begin : decar_latch_gen + tri_ser_rlmreg_p #(.WIDTH(32), .INIT(2147483647), .NEEDS_SRESET(1)) decar_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(decar_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[decar_offset:decar_offset + 32 - 1]), + .scout(sov[decar_offset:decar_offset + 32 - 1]), + .din(decar_d), + .dout(decar_q) + ); + end + if (a2mode == 0) begin : decar_latch_tie + assign decar_q = {32{1'b0}}; + end +endgenerate + tri_ser_rlmreg_p #(.WIDTH(15), .INIT(0), .NEEDS_SRESET(1)) dnhdr_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(dnhdr_act), + .force_t(dcfg_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(dcfg_sl_thold_0_b), + .sg(sg_0), + .scin(siv_dcfg[dnhdr_offset_dcfg:dnhdr_offset_dcfg + 15 - 1]), + .scout(sov_dcfg[dnhdr_offset_dcfg:dnhdr_offset_dcfg + 15 - 1]), + .din(dnhdr_d), + .dout(dnhdr_q) + ); +generate + if (hvmode == 1) begin : epcr_latch_gen + tri_ser_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) epcr_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(epcr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[epcr_offset:epcr_offset + 10 - 1]), + .scout(sov[epcr_offset:epcr_offset + 10 - 1]), + .din(epcr_d), + .dout(epcr_q) + ); + end + if (hvmode == 0) begin : epcr_latch_tie + assign epcr_q = {10{1'b0}}; + end +endgenerate + tri_ser_rlmreg_p #(.WIDTH(17), .INIT(0), .NEEDS_SRESET(1)) esr_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(esr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[esr_offset:esr_offset + 17 - 1]), + .scout(sov[esr_offset:esr_offset + 17 - 1]), + .din(esr_d), + .dout(esr_q) + ); +generate + if (hvmode == 1) begin : gdear_latch_gen + tri_ser_rlmreg_p #(.WIDTH(`GPR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) gdear_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(gdear_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[gdear_offset:gdear_offset + `GPR_WIDTH - 1]), + .scout(sov[gdear_offset:gdear_offset + `GPR_WIDTH - 1]), + .din(gdear_d), + .dout(gdear_q) + ); + end + if (hvmode == 0) begin : gdear_latch_tie + assign gdear_q = {`GPR_WIDTH{1'b0}}; + end +endgenerate +generate + if (hvmode == 1) begin : gdec_latch_gen + tri_ser_rlmreg_p #(.WIDTH(32), .INIT(2147483647), .NEEDS_SRESET(1)) gdec_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(gdec_act), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[gdec_offset:gdec_offset + 32 - 1]), + .scout(sov[gdec_offset:gdec_offset + 32 - 1]), + .din(gdec_d), + .dout(gdec_q) + ); + end + if (hvmode == 0) begin : gdec_latch_tie + assign gdec_q = {32{1'b0}}; + end +endgenerate +generate + if (hvmode == 1) begin : gdecar_latch_gen + tri_ser_rlmreg_p #(.WIDTH(32), .INIT(2147483647), .NEEDS_SRESET(1)) gdecar_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(gdecar_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[gdecar_offset:gdecar_offset + 32 - 1]), + .scout(sov[gdecar_offset:gdecar_offset + 32 - 1]), + .din(gdecar_d), + .dout(gdecar_q) + ); + end + if (hvmode == 0) begin : gdecar_latch_tie + assign gdecar_q = {32{1'b0}}; + end +endgenerate +generate + if (hvmode == 1) begin : gesr_latch_gen + tri_ser_rlmreg_p #(.WIDTH(17), .INIT(0), .NEEDS_SRESET(1)) gesr_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(gesr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[gesr_offset:gesr_offset + 17 - 1]), + .scout(sov[gesr_offset:gesr_offset + 17 - 1]), + .din(gesr_d), + .dout(gesr_q) + ); + end + if (hvmode == 0) begin : gesr_latch_tie + assign gesr_q = {17{1'b0}}; + end +endgenerate +generate + if (hvmode == 1) begin : gpir_latch_gen + tri_ser_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) gpir_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(gpir_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[gpir_offset:gpir_offset + 32 - 1]), + .scout(sov[gpir_offset:gpir_offset + 32 - 1]), + .din(gpir_d), + .dout(gpir_q) + ); + end + if (hvmode == 0) begin : gpir_latch_tie + assign gpir_q = {32{1'b0}}; + end +endgenerate +generate + if (hvmode == 1) begin : gsrr0_latch_gen + tri_ser_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0), .NEEDS_SRESET(1)) gsrr0_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(gsrr0_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[gsrr0_offset:gsrr0_offset + `EFF_IFAR_ARCH - 1]), + .scout(sov[gsrr0_offset:gsrr0_offset + `EFF_IFAR_ARCH - 1]), + .din(gsrr0_d), + .dout(gsrr0_q) + ); + end + if (hvmode == 0) begin : gsrr0_latch_tie + assign gsrr0_q = {`EFF_IFAR_ARCH{1'b0}}; + end +endgenerate +generate + if (hvmode == 1) begin : gsrr1_latch_gen + tri_ser_rlmreg_p #(.WIDTH(14), .INIT(0), .NEEDS_SRESET(1)) gsrr1_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(gsrr1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[gsrr1_offset:gsrr1_offset + 14 - 1]), + .scout(sov[gsrr1_offset:gsrr1_offset + 14 - 1]), + .din(gsrr1_d), + .dout(gsrr1_q) + ); + end + if (hvmode == 0) begin : gsrr1_latch_tie + assign gsrr1_q = {14{1'b0}}; + end +endgenerate +generate + if (hvmode == 1) begin : gtcr_latch_gen + tri_ser_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) gtcr_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(gtcr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[gtcr_offset:gtcr_offset + 10 - 1]), + .scout(sov[gtcr_offset:gtcr_offset + 10 - 1]), + .din(gtcr_d), + .dout(gtcr_q) + ); + end + if (hvmode == 0) begin : gtcr_latch_tie + assign gtcr_q = {10{1'b0}}; + end +endgenerate +generate + if (hvmode == 1) begin : gtsr_latch_gen + tri_ser_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) gtsr_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(gtsr_act), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[gtsr_offset:gtsr_offset + 4 - 1]), + .scout(sov[gtsr_offset:gtsr_offset + 4 - 1]), + .din(gtsr_d), + .dout(gtsr_q) + ); + end + if (hvmode == 0) begin : gtsr_latch_tie + assign gtsr_q = {4{1'b0}}; + end +endgenerate +generate + if (a2mode == 1) begin : mcsr_latch_gen + tri_ser_rlmreg_p #(.WIDTH(15), .INIT(0), .NEEDS_SRESET(1)) mcsr_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(mcsr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[mcsr_offset:mcsr_offset + 15 - 1]), + .scout(sov[mcsr_offset:mcsr_offset + 15 - 1]), + .din(mcsr_d), + .dout(mcsr_q) + ); + end + if (a2mode == 0) begin : mcsr_latch_tie + assign mcsr_q = {15{1'b0}}; + end +endgenerate +generate + if (a2mode == 1) begin : mcsrr0_latch_gen + tri_ser_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0), .NEEDS_SRESET(1)) mcsrr0_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(mcsrr0_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[mcsrr0_offset:mcsrr0_offset + `EFF_IFAR_ARCH - 1]), + .scout(sov[mcsrr0_offset:mcsrr0_offset + `EFF_IFAR_ARCH - 1]), + .din(mcsrr0_d), + .dout(mcsrr0_q) + ); + end + if (a2mode == 0) begin : mcsrr0_latch_tie + assign mcsrr0_q = {`EFF_IFAR_ARCH{1'b0}}; + end +endgenerate +generate + if (a2mode == 1) begin : mcsrr1_latch_gen + tri_ser_rlmreg_p #(.WIDTH(14), .INIT(0), .NEEDS_SRESET(1)) mcsrr1_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(mcsrr1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[mcsrr1_offset:mcsrr1_offset + 14 - 1]), + .scout(sov[mcsrr1_offset:mcsrr1_offset + 14 - 1]), + .din(mcsrr1_d), + .dout(mcsrr1_q) + ); + end + if (a2mode == 0) begin : mcsrr1_latch_tie + assign mcsrr1_q = {14{1'b0}}; + end +endgenerate + tri_ser_rlmreg_p #(.WIDTH(14), .INIT(0), .NEEDS_SRESET(1)) msr_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(msr_act), + .force_t(ccfg_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(ccfg_sl_thold_0_b), + .sg(sg_0), + .scin(siv_ccfg[msr_offset_ccfg:msr_offset_ccfg + 14 - 1]), + .scout(sov_ccfg[msr_offset_ccfg:msr_offset_ccfg + 14 - 1]), + .din(msr_d), + .dout(msr_q) + ); +generate + if (hvmode == 1) begin : msrp_latch_gen + tri_ser_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) msrp_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(msrp_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[msrp_offset:msrp_offset + 2 - 1]), + .scout(sov[msrp_offset:msrp_offset + 2 - 1]), + .din(msrp_d), + .dout(msrp_q) + ); + end + if (hvmode == 0) begin : msrp_latch_tie + assign msrp_q = {2{1'b0}}; + end +endgenerate + tri_ser_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH+2), .INIT(0), .NEEDS_SRESET(1)) siar_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(siar_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[siar_offset:siar_offset + `EFF_IFAR_ARCH+2 - 1]), + .scout(sov[siar_offset:siar_offset + `EFF_IFAR_ARCH+2 - 1]), + .din(siar_d), + .dout(siar_q) + ); + tri_ser_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0), .NEEDS_SRESET(1)) srr0_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(srr0_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[srr0_offset:srr0_offset + `EFF_IFAR_ARCH - 1]), + .scout(sov[srr0_offset:srr0_offset + `EFF_IFAR_ARCH - 1]), + .din(srr0_d), + .dout(srr0_q) + ); + tri_ser_rlmreg_p #(.WIDTH(14), .INIT(0), .NEEDS_SRESET(1)) srr1_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(srr1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[srr1_offset:srr1_offset + 14 - 1]), + .scout(sov[srr1_offset:srr1_offset + 14 - 1]), + .din(srr1_d), + .dout(srr1_q) + ); +generate + if (a2mode == 1) begin : tcr_latch_gen + tri_ser_rlmreg_p #(.WIDTH(12), .INIT(0), .NEEDS_SRESET(1)) tcr_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(tcr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[tcr_offset:tcr_offset + 12 - 1]), + .scout(sov[tcr_offset:tcr_offset + 12 - 1]), + .din(tcr_d), + .dout(tcr_q) + ); + end + if (a2mode == 0) begin : tcr_latch_tie + assign tcr_q = {12{1'b0}}; + end +endgenerate +generate + if (a2mode == 1) begin : tsr_latch_gen + tri_ser_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) tsr_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(tsr_act), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[tsr_offset:tsr_offset + 5 - 1]), + .scout(sov[tsr_offset:tsr_offset + 5 - 1]), + .din(tsr_d), + .dout(tsr_q) + ); + end + if (a2mode == 0) begin : tsr_latch_tie + assign tsr_q = {5{1'b0}}; + end +endgenerate +generate + if (a2mode == 1) begin : udec_latch_gen + tri_ser_rlmreg_p #(.WIDTH(32), .INIT(2147483647), .NEEDS_SRESET(1)) udec_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(udec_act), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[udec_offset:udec_offset + 32 - 1]), + .scout(sov[udec_offset:udec_offset + 32 - 1]), + .din(udec_d), + .dout(udec_q) + ); + end + if (a2mode == 0) begin : udec_latch_tie + assign udec_q = {32{1'b0}}; + end +endgenerate + tri_ser_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) xucr1_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(xucr1_act), + .force_t(ccfg_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(ccfg_sl_thold_0_b), + .sg(sg_0), + .scin(siv_ccfg[xucr1_offset_ccfg:xucr1_offset_ccfg + 5 - 1]), + .scout(sov_ccfg[xucr1_offset_ccfg:xucr1_offset_ccfg + 5 - 1]), + .din(xucr1_d), + .dout(xucr1_q) + ); + + + + + // DVC Shadow SPRs + generate + if (a2mode == 1) + begin : dvc1_latch_gen + + tri_ser_rlmreg_p #(.WIDTH(`GPR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) dvc1_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(dvc1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[dvc1_offset:dvc1_offset + `GPR_WIDTH - 1]), + .scout(sov[dvc1_offset:dvc1_offset + `GPR_WIDTH - 1]), + .din(dvc1_d), + .dout(dvc1_q) + ); + end + endgenerate + generate + if (a2mode == 0) + begin : dvc1_latch_tie + assign dvc1_q = {64-`GPR_WIDTH-63+1{1'b0}}; + end + endgenerate + generate + if (a2mode == 1) + begin : dvc2_latch_gen + + tri_ser_rlmreg_p #(.WIDTH(`GPR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) dvc2_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(dvc2_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[dvc2_offset:dvc2_offset + `GPR_WIDTH - 1]), + .scout(sov[dvc2_offset:dvc2_offset + `GPR_WIDTH - 1]), + .din(dvc2_d), + .dout(dvc2_q) + ); + end + endgenerate + generate + if (a2mode == 0) + begin : dvc2_latch_tie + assign dvc2_q = {64-`GPR_WIDTH-63+1{1'b0}}; + end + endgenerate + + // Latch Instances + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_xu_act_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[iu_xu_act_offset]), + .scout(sov[iu_xu_act_offset]), + .din(iu_xu_act), + .dout(iu_xu_act_q) + ); + tri_rlmreg_p #(.WIDTH(2), .OFFSET(1),.INIT(0), .NEEDS_SRESET(1)) exx_act_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[exx_act_offset : exx_act_offset + 2-1]), + .scout(sov[exx_act_offset : exx_act_offset + 2-1]), + .din(exx_act_d), + .dout(exx_act_q) + ); + tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_is_mfmsr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_is_mfmsr_offset]), + .scout(sov[ex2_is_mfmsr_offset]), + .din(ex1_is_mfmsr), + .dout(ex2_is_mfmsr_q) + ); + tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_wrtee_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_wrtee_offset]), + .scout(sov[ex2_wrtee_offset]), + .din(ex1_is_wrtee), + .dout(ex2_wrtee_q) + ); + tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_wrteei_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_wrteei_offset]), + .scout(sov[ex2_wrteei_offset]), + .din(ex1_is_wrteei), + .dout(ex2_wrteei_q) + ); + tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_dnh_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_dnh_offset]), + .scout(sov[ex2_dnh_offset]), + .din(ex1_is_dnh), + .dout(ex2_dnh_q) + ); + tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_is_mtmsr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_is_mtmsr_offset]), + .scout(sov[ex2_is_mtmsr_offset]), + .din(ex1_is_mtmsr), + .dout(ex2_is_mtmsr_q) + ); + tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_is_mtspr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_is_mtspr_offset]), + .scout(sov[ex2_is_mtspr_offset]), + .din(ex1_is_mtspr), + .dout(ex2_is_mtspr_q) + ); + tri_regk #(.WIDTH(15), .OFFSET(6),.INIT(0), .NEEDS_SRESET(1)) ex2_instr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_instr_offset : ex2_instr_offset + 15-1]), + .scout(sov[ex2_instr_offset : ex2_instr_offset + 15-1]), + .din(ex2_instr_d), + .dout(ex2_instr_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_is_mtspr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_is_mtspr_offset]), + .scout(sov[ex3_is_mtspr_offset]), + .din(ex2_is_mtspr_q), + .dout(ex3_is_mtspr_q) + ); + tri_rlmreg_p #(.WIDTH(15), .OFFSET(6),.INIT(0), .NEEDS_SRESET(1)) ex3_instr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex3_instr_offset : ex3_instr_offset + 15-1]), + .scout(sov[ex3_instr_offset : ex3_instr_offset + 15-1]), + .din(ex2_instr_q), + .dout(ex3_instr_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_wrtee_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_wrtee_offset]), + .scout(sov[ex3_wrtee_offset]), + .din(ex2_wrtee_q), + .dout(ex3_wrtee_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_wrteei_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_wrteei_offset]), + .scout(sov[ex3_wrteei_offset]), + .din(ex2_wrteei_q), + .dout(ex3_wrteei_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_dnh_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_dnh_offset]), + .scout(sov[ex3_dnh_offset]), + .din(ex2_dnh_q), + .dout(ex3_dnh_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_is_mtmsr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_is_mtmsr_offset]), + .scout(sov[ex3_is_mtmsr_offset]), + .din(ex2_is_mtmsr_q), + .dout(ex3_is_mtmsr_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_rfi_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[iu_rfi_offset]), + .scout(sov[iu_rfi_offset]), + .din(iu_xu_rfi), + .dout(iu_rfi_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_rfgi_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[iu_rfgi_offset]), + .scout(sov[iu_rfgi_offset]), + .din(iu_xu_rfgi), + .dout(iu_rfgi_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_rfci_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[iu_rfci_offset]), + .scout(sov[iu_rfci_offset]), + .din(iu_xu_rfci), + .dout(iu_rfci_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_rfmci_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[iu_rfmci_offset]), + .scout(sov[iu_rfmci_offset]), + .din(iu_xu_rfmci), + .dout(iu_rfmci_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_int_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(iu_int_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[iu_int_offset]), + .scout(sov[iu_int_offset]), + .din(iu_xu_int), + .dout(iu_int_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_gint_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(iu_int_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[iu_gint_offset]), + .scout(sov[iu_gint_offset]), + .din(iu_xu_gint), + .dout(iu_gint_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_cint_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(iu_int_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[iu_cint_offset]), + .scout(sov[iu_cint_offset]), + .din(iu_xu_cint), + .dout(iu_cint_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_mcint_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(iu_int_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[iu_mcint_offset]), + .scout(sov[iu_mcint_offset]), + .din(iu_xu_mcint), + .dout(iu_mcint_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) iu_dear_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(iu_xu_dear_update), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[iu_dear_offset : iu_dear_offset + `GPR_WIDTH-1]), + .scout(sov[iu_dear_offset : iu_dear_offset + `GPR_WIDTH-1]), + .din(iu_xu_dear), + .dout(iu_dear_q) + ); + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .OFFSET(62-`EFF_IFAR_ARCH),.INIT(0), .NEEDS_SRESET(1)) iu_nia_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(iu_nia_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[iu_nia_offset : iu_nia_offset + `EFF_IFAR_ARCH-1]), + .scout(sov[iu_nia_offset : iu_nia_offset + `EFF_IFAR_ARCH-1]), + .din(iu_xu_nia), + .dout(iu_nia_q) + ); + tri_rlmreg_p #(.WIDTH(17), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) iu_esr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(iu_xu_esr_update), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[iu_esr_offset : iu_esr_offset + 17-1]), + .scout(sov[iu_esr_offset : iu_esr_offset + 17-1]), + .din(iu_xu_esr), + .dout(iu_esr_q) + ); + tri_rlmreg_p #(.WIDTH(15), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) iu_mcsr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(iu_int_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[iu_mcsr_offset : iu_mcsr_offset + 15-1]), + .scout(sov[iu_mcsr_offset : iu_mcsr_offset + 15-1]), + .din(iu_xu_mcsr), + .dout(iu_mcsr_q) + ); + tri_rlmreg_p #(.WIDTH(19), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) iu_dbsr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(iu_xu_dbsr_update), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[iu_dbsr_offset : iu_dbsr_offset + 19-1]), + .scout(sov[iu_dbsr_offset : iu_dbsr_offset + 19-1]), + .din(iu_xu_dbsr), + .dout(iu_dbsr_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_dear_update_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(iu_int_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[iu_dear_update_offset]), + .scout(sov[iu_dear_update_offset]), + .din(iu_xu_dear_update), + .dout(iu_dear_update_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_dbsr_update_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(iu_int_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[iu_dbsr_update_offset]), + .scout(sov[iu_dbsr_update_offset]), + .din(iu_xu_dbsr_update), + .dout(iu_dbsr_update_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_esr_update_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(iu_int_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[iu_esr_update_offset]), + .scout(sov[iu_esr_update_offset]), + .din(iu_xu_esr_update), + .dout(iu_esr_update_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_force_gsrr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(iu_int_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[iu_force_gsrr_offset]), + .scout(sov[iu_force_gsrr_offset]), + .din(iu_xu_force_gsrr), + .dout(iu_force_gsrr_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_dbsr_ude_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[iu_dbsr_ude_offset]), + .scout(sov[iu_dbsr_ude_offset]), + .din(iu_xu_dbsr_ude), + .dout(iu_dbsr_ude_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_dbsr_ide_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[iu_dbsr_ide_offset]), + .scout(sov[iu_dbsr_ide_offset]), + .din(iu_xu_dbsr_ide), + .dout(iu_dbsr_ide_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex3_spr_wd_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act_data[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex3_spr_wd_offset : ex3_spr_wd_offset + `GPR_WIDTH-1]), + .scout(sov[ex3_spr_wd_offset : ex3_spr_wd_offset + `GPR_WIDTH-1]), + .din(ex2_spr_wd), + .dout(ex3_spr_wd_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH/8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex3_tid_rpwr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex3_tid_rpwr_offset : ex3_tid_rpwr_offset + `GPR_WIDTH/8-1]), + .scout(sov[ex3_tid_rpwr_offset : ex3_tid_rpwr_offset + `GPR_WIDTH/8-1]), + .din(ex3_tid_rpwr_d), + .dout(ex3_tid_rpwr_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex3_tspr_rt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act_data[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex3_tspr_rt_offset : ex3_tspr_rt_offset + `GPR_WIDTH-1]), + .scout(sov[ex3_tspr_rt_offset : ex3_tspr_rt_offset + `GPR_WIDTH-1]), + .din(ex3_tspr_rt_d), + .dout(ex3_tspr_rt_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) fit_tb_tap_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fit_tb_tap_offset]), + .scout(sov[fit_tb_tap_offset]), + .din(fit_tb_tap_d), + .dout(fit_tb_tap_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) wdog_tb_tap_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[wdog_tb_tap_offset]), + .scout(sov[wdog_tb_tap_offset]), + .din(wdog_tb_tap_d), + .dout(wdog_tb_tap_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) gfit_tb_tap_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[gfit_tb_tap_offset]), + .scout(sov[gfit_tb_tap_offset]), + .din(gfit_tb_tap_d), + .dout(gfit_tb_tap_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) gwdog_tb_tap_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[gwdog_tb_tap_offset]), + .scout(sov[gwdog_tb_tap_offset]), + .din(gwdog_tb_tap_d), + .dout(gwdog_tb_tap_q) + ); + tri_rlmreg_p #(.WIDTH(4), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) hang_pulse_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[hang_pulse_offset : hang_pulse_offset + 4-1]), + .scout(sov[hang_pulse_offset : hang_pulse_offset + 4-1]), + .din(hang_pulse_d), + .dout(hang_pulse_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lltap_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lltap_offset]), + .scout(sov[lltap_offset]), + .din(lltap_d), + .dout(lltap_q) + ); + tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) llcnt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[llcnt_offset : llcnt_offset + 2-1]), + .scout(sov[llcnt_offset : llcnt_offset + 2-1]), + .din(llcnt_d), + .dout(llcnt_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) msrovride_pr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[msrovride_pr_offset]), + .scout(sov[msrovride_pr_offset]), + .din(pc_xu_msrovride_pr), + .dout(msrovride_pr_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) msrovride_gs_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[msrovride_gs_offset]), + .scout(sov[msrovride_gs_offset]), + .din(pc_xu_msrovride_gs), + .dout(msrovride_gs_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) msrovride_de_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[msrovride_de_offset]), + .scout(sov[msrovride_de_offset]), + .din(pc_xu_msrovride_de), + .dout(msrovride_de_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) an_ac_ext_interrupt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[an_ac_ext_interrupt_offset]), + .scout(sov[an_ac_ext_interrupt_offset]), + .din(an_ac_ext_interrupt), + .dout(an_ac_ext_interrupt_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) an_ac_crit_interrupt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[an_ac_crit_interrupt_offset]), + .scout(sov[an_ac_crit_interrupt_offset]), + .din(an_ac_crit_interrupt), + .dout(an_ac_crit_interrupt_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) an_ac_perf_interrupt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[an_ac_perf_interrupt_offset]), + .scout(sov[an_ac_perf_interrupt_offset]), + .din(an_ac_perf_interrupt), + .dout(an_ac_perf_interrupt_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) an_ac_perf_interrupt2_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[an_ac_perf_interrupt2_offset]), + .scout(sov[an_ac_perf_interrupt2_offset]), + .din(an_ac_perf_interrupt_q), + .dout(an_ac_perf_interrupt2_q) + ); + tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) mux_msr_gs_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[mux_msr_gs_offset : mux_msr_gs_offset + 3-1]), + .scout(sov[mux_msr_gs_offset : mux_msr_gs_offset + 3-1]), + .din(mux_msr_gs_d), + .dout(mux_msr_gs_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mux_msr_pr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[mux_msr_pr_offset]), + .scout(sov[mux_msr_pr_offset]), + .din(mux_msr_pr_d), + .dout(mux_msr_pr_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) err_llbust_attempt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[err_llbust_attempt_offset]), + .scout(sov[err_llbust_attempt_offset]), + .din(err_llbust_attempt_d), + .dout(err_llbust_attempt_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) err_llbust_failed_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[err_llbust_failed_offset]), + .scout(sov[err_llbust_failed_offset]), + .din(err_llbust_failed_d), + .dout(err_llbust_failed_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) inj_llbust_attempt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[inj_llbust_attempt_offset]), + .scout(sov[inj_llbust_attempt_offset]), + .din(pc_xu_inj_llbust_attempt), + .dout(inj_llbust_attempt_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) inj_llbust_failed_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[inj_llbust_failed_offset]), + .scout(sov[inj_llbust_failed_offset]), + .din(pc_xu_inj_llbust_failed), + .dout(inj_llbust_failed_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) an_ac_external_mchk_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[an_ac_external_mchk_offset]), + .scout(sov[an_ac_external_mchk_offset]), + .din(an_ac_external_mchk), + .dout(an_ac_external_mchk_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mchk_interrupt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[mchk_interrupt_offset]), + .scout(sov[mchk_interrupt_offset]), + .din(mchk_interrupt), + .dout(mchk_interrupt_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) crit_interrupt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[crit_interrupt_offset]), + .scout(sov[crit_interrupt_offset]), + .din(crit_interrupt), + .dout(crit_interrupt_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) wdog_interrupt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[wdog_interrupt_offset]), + .scout(sov[wdog_interrupt_offset]), + .din(wdog_interrupt), + .dout(wdog_interrupt_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dec_interrupt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[dec_interrupt_offset]), + .scout(sov[dec_interrupt_offset]), + .din(dec_interrupt), + .dout(dec_interrupt_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) udec_interrupt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[udec_interrupt_offset]), + .scout(sov[udec_interrupt_offset]), + .din(udec_interrupt), + .dout(udec_interrupt_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) perf_interrupt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[perf_interrupt_offset]), + .scout(sov[perf_interrupt_offset]), + .din(perf_interrupt), + .dout(perf_interrupt_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) fit_interrupt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[fit_interrupt_offset]), + .scout(sov[fit_interrupt_offset]), + .din(fit_interrupt), + .dout(fit_interrupt_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ext_interrupt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ext_interrupt_offset]), + .scout(sov[ext_interrupt_offset]), + .din(ext_interrupt), + .dout(ext_interrupt_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) gwdog_interrupt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[gwdog_interrupt_offset]), + .scout(sov[gwdog_interrupt_offset]), + .din(gwdog_interrupt), + .dout(gwdog_interrupt_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) gdec_interrupt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[gdec_interrupt_offset]), + .scout(sov[gdec_interrupt_offset]), + .din(gdec_interrupt), + .dout(gdec_interrupt_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) gfit_interrupt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[gfit_interrupt_offset]), + .scout(sov[gfit_interrupt_offset]), + .din(gfit_interrupt), + .dout(gfit_interrupt_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) single_instr_mode_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[single_instr_mode_offset]), + .scout(sov[single_instr_mode_offset]), + .din(single_instr_mode_d), + .dout(single_instr_mode_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) single_instr_mode_2_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[single_instr_mode_2_offset]), + .scout(sov[single_instr_mode_2_offset]), + .din(single_instr_mode_q), + .dout(single_instr_mode_2_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) machine_check_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[machine_check_offset]), + .scout(sov[machine_check_offset]), + .din(machine_check_d), + .dout(machine_check_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) raise_iss_pri_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[raise_iss_pri_offset]), + .scout(sov[raise_iss_pri_offset]), + .din(raise_iss_pri_d), + .dout(raise_iss_pri_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) raise_iss_pri_2_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[raise_iss_pri_2_offset]), + .scout(sov[raise_iss_pri_2_offset]), + .din(raise_iss_pri_q), + .dout(raise_iss_pri_2_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pc_xu_inj_wdt_reset_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[pc_xu_inj_wdt_reset_offset]), + .scout(sov[pc_xu_inj_wdt_reset_offset]), + .din(pc_xu_inj_wdt_reset), + .dout(pc_xu_inj_wdt_reset_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) err_wdt_reset_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[err_wdt_reset_offset]), + .scout(sov[err_wdt_reset_offset]), + .din(err_wdt_reset_d), + .dout(err_wdt_reset_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ram_active_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ram_active_offset]), + .scout(sov[ram_active_offset]), + .din(cspr_tspr_ram_active), + .dout(ram_active_q) + ); + tri_rlmreg_p #(.WIDTH(10), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) timebase_taps_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[timebase_taps_offset : timebase_taps_offset + 10-1]), + .scout(sov[timebase_taps_offset : timebase_taps_offset + 10-1]), + .din(cspr_tspr_timebase_taps), + .dout(timebase_taps_q) + ); + tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) dbsr_mrr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(dbsr_mrr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[dbsr_mrr_offset : dbsr_mrr_offset + 2-1]), + .scout(sov[dbsr_mrr_offset : dbsr_mrr_offset + 2-1]), + .din(dbsr_mrr_d), + .dout(dbsr_mrr_q) + ); + tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) tsr_wrs_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(tsr_wrs_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[tsr_wrs_offset : tsr_wrs_offset + 2-1]), + .scout(sov[tsr_wrs_offset : tsr_wrs_offset + 2-1]), + .din(tsr_wrs_d), + .dout(tsr_wrs_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iac1_en_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[iac1_en_offset]), + .scout(sov[iac1_en_offset]), + .din(iac1_en_d), + .dout(iac1_en_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iac2_en_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[iac2_en_offset]), + .scout(sov[iac2_en_offset]), + .din(iac2_en_d), + .dout(iac2_en_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iac3_en_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[iac3_en_offset]), + .scout(sov[iac3_en_offset]), + .din(iac3_en_d), + .dout(iac3_en_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iac4_en_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[iac4_en_offset]), + .scout(sov[iac4_en_offset]), + .din(iac4_en_d), + .dout(iac4_en_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_dnh_val_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_dnh_val_offset]), + .scout(sov[ex3_dnh_val_offset]), + .din(ex3_dnh), + .dout(ex3_dnh_val_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) an_ac_perf_interrupt_edge_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[an_ac_perf_interrupt_edge_offset]), + .scout(sov[an_ac_perf_interrupt_edge_offset]), + .din(an_ac_perf_interrupt_edge), + .dout(an_ac_perf_interrupt_edge_q) + ); + + tri_lcbnd spare_0_lcb( + .vd(vdd), + .gd(gnd), + .act(1'b1), + .nclk(nclk), + .force_t(func_sl_force), + .thold_b(func_sl_thold_0_b), + .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), + .mpw2_b(mpw2_dc_b), + .sg(sg_0), + .lclk(spare_0_lclk), + .d1clk(spare_0_d1clk), + .d2clk(spare_0_d2clk) + ); + + tri_inv_nlats #(.WIDTH(16), .BTR("NLI0001_X2_A12TH"), .INIT(0)) spare_0_latch( + .vd(vdd), + .gd(gnd), + .lclk(spare_0_lclk), + .d1clk(spare_0_d1clk), + .d2clk(spare_0_d2clk), + .scanin(siv[spare_0_offset:spare_0_offset + 16 - 1]), + .scanout(sov[spare_0_offset:spare_0_offset + 16 - 1]), + .d(spare_0_d), + .qb(spare_0_q) + ); + assign spare_0_d = (~spare_0_q); + + assign siv[0:scan_right - 1] = {sov[1:scan_right - 1], scan_in}; + assign scan_out = sov[0]; + + generate + // CCFG + if (scan_right_ccfg > 1) + begin : ccfg_l + assign siv_ccfg[0:scan_right_ccfg - 1] = {sov_ccfg[1:scan_right_ccfg - 1], ccfg_scan_in}; + assign ccfg_scan_out = sov_ccfg[0]; + end + if (scan_right_ccfg == 1) + begin : ccfg_s + assign siv_ccfg[0] = ccfg_scan_in; + assign ccfg_scan_out = sov_ccfg[0]; + end + if (scan_right_ccfg == 0) + begin : ccfg_z + assign ccfg_scan_out = ccfg_scan_in; + end + // DCFG + if (scan_right_dcfg > 1) + begin : dcfg_l + assign siv_dcfg[0:scan_right_dcfg - 1] = {sov_dcfg[1:scan_right_dcfg - 1], dcfg_scan_in}; + assign dcfg_scan_out = sov_dcfg[0]; + end + if (scan_right_dcfg == 1) + begin : dcfg_s + assign siv_dcfg[0] = dcfg_scan_in; + assign dcfg_scan_out = sov_dcfg[0]; + end + if (scan_right_dcfg == 0) + begin : dcfg_z + assign dcfg_scan_out = dcfg_scan_in; + end + endgenerate + + + +endmodule